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tests/MC/AArch64/SME2/scvtf.s.yaml | 80 + tests/MC/AArch64/SME2/sdot.s.yaml | 4320 +++ tests/MC/AArch64/SME2/sel.s.yaml | 320 + tests/MC/AArch64/SME2/smax.s.yaml | 640 + tests/MC/AArch64/SME2/smin.s.yaml | 640 + tests/MC/AArch64/SME2/smlal.s.yaml | 1680 ++ tests/MC/AArch64/SME2/smlall.s.yaml | 3360 +++ tests/MC/AArch64/SME2/smlsl.s.yaml | 1680 ++ tests/MC/AArch64/SME2/smlsll.s.yaml | 3360 +++ tests/MC/AArch64/SME2/smopa.s.yaml | 120 + tests/MC/AArch64/SME2/smops.s.yaml | 120 + tests/MC/AArch64/SME2/sqcvt.s.yaml | 120 + tests/MC/AArch64/SME2/sqcvtn.s.yaml | 80 + tests/MC/AArch64/SME2/sqcvtu.s.yaml | 120 + tests/MC/AArch64/SME2/sqcvtun.s.yaml | 80 + tests/MC/AArch64/SME2/sqdmulh.s.yaml | 640 + tests/MC/AArch64/SME2/sqrshr.s.yaml | 120 + tests/MC/AArch64/SME2/sqrshrn.s.yaml | 80 + tests/MC/AArch64/SME2/sqrshru.s.yaml | 120 + tests/MC/AArch64/SME2/sqrshrun.s.yaml | 80 + tests/MC/AArch64/SME2/srshl.s.yaml | 640 + tests/MC/AArch64/SME2/st1b.s.yaml | 160 + tests/MC/AArch64/SME2/st1d.s.yaml | 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| 60 + tests/MC/AArch64/SVE/frecpx.s.yaml | 140 + tests/MC/AArch64/SVE/frinta.s.yaml | 140 + tests/MC/AArch64/SVE/frinti.s.yaml | 140 + tests/MC/AArch64/SVE/frintm.s.yaml | 140 + tests/MC/AArch64/SVE/frintn.s.yaml | 140 + tests/MC/AArch64/SVE/frintp.s.yaml | 140 + tests/MC/AArch64/SVE/frintx.s.yaml | 140 + tests/MC/AArch64/SVE/frintz.s.yaml | 140 + tests/MC/AArch64/SVE/frsqrte.s.yaml | 60 + tests/MC/AArch64/SVE/frsqrts.s.yaml | 60 + tests/MC/AArch64/SVE/fscale.s.yaml | 140 + tests/MC/AArch64/SVE/fsqrt.s.yaml | 140 + tests/MC/AArch64/SVE/fsub.s.yaml | 440 + tests/MC/AArch64/SVE/fsubr.s.yaml | 380 + tests/MC/AArch64/SVE/ftmad.s.yaml | 50 + tests/MC/AArch64/SVE/ftsmul.s.yaml | 30 + tests/MC/AArch64/SVE/ftssel.s.yaml | 30 + tests/MC/AArch64/SVE/incb.s.yaml | 660 + tests/MC/AArch64/SVE/incd.s.yaml | 600 + tests/MC/AArch64/SVE/inch.s.yaml | 600 + tests/MC/AArch64/SVE/incp.s.yaml | 320 + tests/MC/AArch64/SVE/incw.s.yaml | 600 + tests/MC/AArch64/SVE/index.s.yaml | 640 + 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tests/MC/SystemZ/insn-good-z196.s.yaml create mode 100644 tests/MC/SystemZ/insn-good.s.yaml create mode 100644 tests/MC/SystemZ/regs-good.s.yaml create mode 100644 tests/MC/TriCore/ADC_Background_Scan_1_KIT_TC275_LK.s.yaml create mode 100644 tests/MC/TriCore/ADC_Queued_Scan_1_KIT_TC397_TFT.s.yaml create mode 100644 tests/MC/TriCore/J_Call_Loop.s.yaml create mode 100644 tests/MC/TriCore/LoadStore.s.yaml create mode 100644 tests/MC/TriCore/csfr.s.yaml create mode 100644 tests/MC/TriCore/debug.s.yaml create mode 100644 tests/MC/TriCore/extr_u.s.yaml create mode 100644 tests/MC/TriCore/handwrite.s.yaml create mode 100644 tests/MC/TriCore/iLLD_TC375_ADS_Bluetooth_RFCOMM.s.yaml create mode 100644 tests/MC/TriCore/ldst_br_circ.s.yaml create mode 100644 tests/MC/TriCore/rr_insn.s.yaml create mode 100644 tests/MC/TriCore/tc110.s.yaml create mode 100644 tests/MC/TriCore/tc120.s.yaml create mode 100644 tests/MC/TriCore/tc130.s.yaml create mode 100644 tests/MC/TriCore/tc131.s.yaml create mode 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100644 tests/MC/X86/x86_64-rtm-encoding.s.yaml create mode 100644 tests/MC/X86/x86_64-tbm-encoding.s.yaml create mode 100644 tests/MC/X86/x86_64-xop-encoding.s.yaml delete mode 100644 tests/Makefile delete mode 100644 tests/README create mode 100644 tests/README.md delete mode 100644 tests/cs_details/issue.cs rename tests/{cs_details => details}/README.md (100%) create mode 100644 tests/details/aarch64.yaml create mode 100644 tests/details/alpha.yaml create mode 100644 tests/details/arm.yaml create mode 100644 tests/details/bpf.yaml create mode 100644 tests/details/cs_common_details.yaml create mode 100644 tests/details/evm.yaml create mode 100644 tests/details/hppa.yaml create mode 100644 tests/details/loongarch.yaml create mode 100644 tests/details/m680x.yaml create mode 100644 tests/details/m68k.yaml create mode 100644 tests/details/mips.yaml create mode 100644 tests/details/mos65xx.yaml create mode 100644 tests/details/ppc.yaml create mode 100644 tests/details/riscv.yaml create mode 100644 tests/details/sh.yaml create mode 100644 tests/details/sparc.yaml create mode 100644 tests/details/systemz.yaml create mode 100644 tests/details/tms320c64x.yaml create mode 100644 tests/details/tricore.yaml create mode 100644 tests/details/wasm.yaml create mode 100644 tests/details/x86.yaml create mode 100644 tests/details/xcore.yaml create mode 100644 tests/features/skipdata.yaml create mode 100644 tests/integration/CMakeLists.txt create mode 100644 tests/integration/README.md rename tests/{ => integration}/test_customized_mnem.c (100%) rename tests/{ => integration}/test_iter.c (100%) rename tests/{ => integration}/test_skipdata.c (100%) rename tests/{ => integration}/test_winkernel.cpp (100%) create mode 100644 tests/issues/issues.yaml delete mode 100644 tests/test_aarch64.c delete mode 100644 tests/test_all.sh delete mode 100644 tests/test_alpha.c delete mode 100644 tests/test_arm.c delete mode 100644 tests/test_basic.c delete mode 100644 tests/test_bpf.c delete mode 100644 tests/test_detail.c delete mode 100644 tests/test_evm.c delete mode 100644 tests/test_hppa.c delete mode 100644 tests/test_loongarch.c delete mode 100644 tests/test_m680x.c delete mode 100644 tests/test_m68k.c delete mode 100644 tests/test_mips.c delete mode 100644 tests/test_mos65xx.c delete mode 100644 tests/test_ppc.c delete mode 100644 tests/test_riscv.c delete mode 100644 tests/test_sh.c delete mode 100644 tests/test_sparc.c delete mode 100644 tests/test_systemz.c delete mode 100644 tests/test_tms320c64x.c delete mode 100644 tests/test_tricore.c delete mode 100644 tests/test_wasm.c delete mode 100644 tests/test_x86.c delete mode 100644 tests/test_xcore.c create mode 100644 tests/unit/CMakeLists.txt create mode 100644 tests/unit/README.md diff --git a/.github/workflows/CITest.yml b/.github/workflows/CITest.yml index 6b1850d14b..898abd619f 100644 --- a/.github/workflows/CITest.yml +++ b/.github/workflows/CITest.yml @@ -6,7 +6,7 @@ on: - "docs/**" - "ChangeLog" - "CREDITS.TXT" - - "COMPILE.TXT" + - "COMPILE_MAKE.TXT" - "COMPILE_MSVC.TXT" - "COMPILE_CMAKE.TXT" - "HACK.TXT" @@ -34,6 +34,7 @@ jobs: os: ubuntu-22.04, arch: x64, build-system: 'make', + diet-build: 'OFF', enable-asan: 'OFF' } - { @@ -41,34 +42,37 @@ jobs: os: ubuntu-22.04, arch: x64, build-system: 'cmake', + diet-build: 'OFF', enable-asan: 'OFF' } - { - name: 'ubuntu-22.04 x64 ASAN', - os: ubuntu-latest, + name: 'ubuntu-24.04 x64 ASAN', + os: ubuntu-24.04, arch: x64, build-system: 'cmake', + diet-build: 'OFF', enable-asan: 'ON' } steps: - uses: actions/checkout@v3 - - name: prepare + - name: Set up Python + uses: actions/setup-python@v4 + with: + python-version: ${{ matrix.config.python-version }} + + - name: Prepare fuzzing run: | export LD_LIBRARY_PATH=`pwd`/tests/:$LD_LIBRARY_PATH wget https://github.com/groundx/capstonefuzz/raw/master/corpus/corpus-libFuzzer-capstone_fuzz_disasmnext-latest.zip unzip -q corpus-libFuzzer-capstone_fuzz_disasmnext-latest.zip -d suite/fuzz - git clone https://git.cryptomilk.org/projects/cmocka.git suite/cstest/cmocka - chmod +x suite/cstest/build_cstest.sh - name: make if: startsWith(matrix.config.build-system, 'make') run: | ./make.sh - make check sudo make install - cp libcapstone.so.5 libcapstone.so.5.0 - name: cmake if: startsWith(matrix.config.build-system, 'cmake') @@ -82,47 +86,55 @@ jobs: # build shared library cmake -DCAPSTONE_INSTALL=1 -DBUILD_SHARED_LIBS=1 -DCMAKE_INSTALL_PREFIX=/usr -DCAPSTONE_BUILD_CSTEST=ON -DENABLE_ASAN=${asan} .. sudo cmake --build . --config Release --target install - cp libcapstone.* ../ - cp libcapstone.* ../tests/ - cp test_* ../tests/ - name: Lower number of KASL randomized address bits run: | # Work-around ASAN bug https://github.com/google/sanitizers/issues/1716 sudo sysctl vm.mmap_rnd_bits=28 - - name: "Compatibility header test build" - if: matrix.config.diet-build == 'OFF' - env: - asan: ${{ matrix.config.enable-asan }} + - name: "Compatibility header test" + if: startsWith(matrix.config.build-system, 'cmake') && matrix.config.diet-build == 'OFF' run: | - cd "$(git rev-parse --show-toplevel)/suite/auto-sync/c_tests/" - if [ "$asan" = "ON" ]; then - clang -lcapstone -fsanitize=address src/test_arm64_compatibility_header.c -o test_arm64_compatibility_header - else - clang -lcapstone src/test_arm64_compatibility_header.c -o test_arm64_compatibility_header - fi - ./test_arm64_compatibility_header + ctest --test-dir build --output-on-failure -R ASCompatibilityHeaderTest - name: cstool - reaches disassembler engine run: | sh suite/run_invalid_cstool.sh - - name: cstest (cmake) + - name: cstest unit tests if: startsWith(matrix.config.build-system, 'cmake') run: | - python suite/cstest/cstest_report.py -D -d suite/MC - python suite/cstest/cstest_report.py -D -f suite/cstest/issues.cs - python suite/cstest/cstest_report.py -D -f tests/cs_details/issue.cs + ctest --test-dir build --output-on-failure -R UnitCSTest - - name: cstest (make) - if: startsWith(matrix.config.build-system, 'make') + - name: cstest integration tests + if: startsWith(matrix.config.build-system, 'cmake') + run: | + ctest --test-dir build --output-on-failure -R IntegrationCSTest + + - name: cstest MC + if: startsWith(matrix.config.build-system, 'cmake') + run: | + ctest --test-dir build --output-on-failure -R MCTests + + - name: cstest details + if: startsWith(matrix.config.build-system, 'cmake') + run: | + ctest --test-dir build --output-on-failure -R DetailTests + + - name: cstest issues + if: startsWith(matrix.config.build-system, 'cmake') + run: | + ctest --test-dir build --output-on-failure -R IssueTests + + - name: cstest features + if: startsWith(matrix.config.build-system, 'cmake') + run: | + ctest --test-dir build --output-on-failure -R FeaturesTests + + - name: Legacy integration tests + if: startsWith(matrix.config.build-system, 'cmake') run: | - cd suite/cstest && ./build_cstest.sh - python cstest_report.py -D -t build/cstest -d ../MC - python cstest_report.py -D -t build/cstest -f issues.cs - python cstest_report.py -D -t build/cstest -f ../../tests/cs_details/issue.cs - cd ../../ + ctest --test-dir build --output-on-failure -R legacy* Windows: runs-on: ${{ matrix.config.os }} diff --git a/.github/workflows/auto-sync.yml b/.github/workflows/auto-sync.yml index 6cdaaf3251..d22729333e 100644 --- a/.github/workflows/auto-sync.yml +++ b/.github/workflows/auto-sync.yml @@ -3,11 +3,17 @@ on: push: paths: - "suite/auto-sync/**" + - ".github/workflows/auto-sync.yml" pull_request: +# Stop previous runs on the same branch on new push +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: true + jobs: check: - runs-on: ubuntu-latest + runs-on: ubuntu-24.04 defaults: run: working-directory: suite/auto-sync/ @@ -30,9 +36,22 @@ jobs: run: | python3.11 -m black --check src/autosync - - name: Build llvm-tblgen + - name: Install llvm-mc + run: | + sudo apt install llvm-18 + llvm-mc-18 --version + FileCheck-18 --version + sudo ln -s $(whereis -b llvm-mc-18 | grep -Eo "/.*") /usr/local/bin/llvm-mc + sudo ln -s $(whereis -b FileCheck-18 | grep -Eo "/.*") /usr/local/bin/FileCheck + llvm-mc --version + FileCheck --version + + - name: Clone llvm-capstone run: | git clone https://github.com/capstone-engine/llvm-capstone.git vendor/llvm_root + + - name: Build llvm-tblgen + run: | cd vendor/llvm_root mkdir build cd build @@ -40,6 +59,17 @@ jobs: cmake --build . --target llvm-tblgen --config Debug cd ../../../ + - name: Test Header patcher + run: | + python -m unittest src/autosync/Tests/test_header_patcher.py + python -m unittest src/autosync/Tests/test_mcupdater.py + + - name: Remove llvm-mc + run: | + sudo apt remove llvm-18 + sudo rm /usr/local/bin/llvm-mc + sudo rm /usr/local/bin/FileCheck + - name: Test generation of inc files run: | ./src/autosync/ASUpdater.py -d -a AArch64 -s IncGen @@ -63,11 +93,9 @@ jobs: ./src/autosync/ASUpdater.py --ci -d -a PPC -s Translate ./src/autosync/ASUpdater.py --ci -d -a LoongArch -s Translate - - name: Test Header patcher - run: | - python -m unittest src/autosync/Tests/test_header_patcher.py - python -m unittest src/autosync/Tests/test_mcupdater.py - - name: Differ - Test save file is up-to-date run: | ./src/autosync/cpptranslator/Differ.py -a AArch64 --check_saved + ./src/autosync/cpptranslator/Differ.py -a ARM --check_saved + ./src/autosync/cpptranslator/Differ.py -a PPC --check_saved + ./src/autosync/cpptranslator/Differ.py -a LoongArch --check_saved diff --git a/.github/workflows/clang-tidy.yml b/.github/workflows/clang-tidy.yml index 0c36d6777f..792a5b22db 100644 --- a/.github/workflows/clang-tidy.yml +++ b/.github/workflows/clang-tidy.yml @@ -8,11 +8,11 @@ on: jobs: analyze: - runs-on: ubuntu-latest + runs-on: ubuntu-24.04 name: clang-tidy steps: - - uses: actions/checkout@v3 + - uses: actions/checkout@v4 with: fetch-depth: 0 - name: Install clang-tidy @@ -26,9 +26,9 @@ jobs: CC=clang sudo cmake --build . --config Release cd .. - - name: Install clang-tidy-15 + - name: Install clang-tidy-18 run: | - sudo apt install clang-tidy-15 + sudo apt install clang-tidy-18 - name: Check for warnings env: @@ -36,3 +36,8 @@ jobs: head_sha: ${{ github.event.pull_request.head.sha }} run: | ./run-clang-tidy.sh build + + - uses: actions/upload-artifact@v4 + if: ${{ failure() }} + with: + path: ct-warnings.txt diff --git a/.github/workflows/python-tests.yml b/.github/workflows/python-tests.yml index c47993a2b2..e72b8a4d81 100644 --- a/.github/workflows/python-tests.yml +++ b/.github/workflows/python-tests.yml @@ -28,5 +28,30 @@ jobs: - name: Build and install capstone run: pip install ./bindings/python - - name: Run tests + - name: Install cstest_py + run: pip install ./bindings/python/cstest_py + + - name: Run legacy tests run: python ./bindings/python/tests/test_all.py + + - name: cstest_py integration tests + run: | + cd suite/cstest/test/ + python3 ./integration_tests.py cstest_py + cd ../../../ + + - name: cstest_py MC + run: | + cstest_py tests/MC/ + + - name: cstest_py details + run: | + cstest_py tests/details/ + + - name: cstest_py issues + run: | + cstest_py tests/issues/ + + - name: cstest_py features + run: | + cstest_py tests/features/ diff --git a/.gitignore b/.gitignore index a0a9012662..698c6d154f 100644 --- a/.gitignore +++ b/.gitignore @@ -25,6 +25,7 @@ # python bindings/python/build/ bindings/python/capstone.egg-info/ +bindings/python/cstest_py/src/cstest_py.egg** bindings/cython/capstone.egg-info/ *.pyc @@ -133,7 +134,6 @@ fuzz_disasm fuzz_decode_platform capstone_get_setup suite/fuzz/corpus -suite/cstest/cmocka/ *.s @@ -147,3 +147,6 @@ android-ndk-* # Auto-sync files suite/auto-sync/src/autosync.egg-info + +# clangd cache +/.cache diff --git a/CMakeLists.txt b/CMakeLists.txt index c6acc49880..125f8b639d 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -60,7 +60,7 @@ option(BUILD_SHARED_LIBS "Build shared library" OFF) option(CAPSTONE_BUILD_STATIC_RUNTIME "Embed static runtime" ${BUILD_SHARED_LIBS}) option(CAPSTONE_BUILD_MACOS_THIN "Disable universal2 builds on macOS" OFF) option(CAPSTONE_BUILD_DIET "Build diet library" OFF) -option(CAPSTONE_BUILD_TESTS "Build tests" ${PROJECT_IS_TOP_LEVEL}) +option(CAPSTONE_BUILD_LEGACY_TESTS "Build legacy tests" ${PROJECT_IS_TOP_LEVEL}) option(CAPSTONE_BUILD_CSTOOL "Build cstool" ${PROJECT_IS_TOP_LEVEL}) option(CAPSTONE_BUILD_CSTEST "Build cstest" OFF) option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON) @@ -69,13 +69,21 @@ option(CAPSTONE_ARCHITECTURE_DEFAULT "Whether architectures are enabled by defau option(CAPSTONE_DEBUG "Whether to enable extra debug assertions" OFF) option(CAPSTONE_INSTALL "Generate install target" ${PROJECT_IS_TOP_LEVEL}) option(ENABLE_ASAN "Enable address sanitizer" OFF) +option(ENABLE_COVERAGE "Enable test coverage" OFF) if (ENABLE_ASAN) + message("Enabling ASAN") add_definitions(-DASAN_ENABLED) add_compile_options(-fsanitize=address) add_link_options(-fsanitize=address) endif() +if (ENABLE_COVERAGE) + message("Enabling COVERAGE") + add_compile_options(--coverage) + add_link_options(--coverage) +endif() + # If building for OSX it's best to allow CMake to handle building both architectures if(APPLE AND NOT CAPSTONE_BUILD_MACOS_THIN) set(CMAKE_OSX_ARCHITECTURES "x86_64;arm64") @@ -208,8 +216,6 @@ set(HEADERS_COMMON include/capstone/loongarch.h ) -set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c) - ## architecture support if(CAPSTONE_ARM_SUPPORT) add_definitions(-DCAPSTONE_HAS_ARM) @@ -239,7 +245,6 @@ if(CAPSTONE_ARM_SUPPORT) arch/ARM/ARMGenCSMappingInsnName.inc arch/ARM/ARMGenSystemRegister.inc ) - set(TEST_SOURCES ${TEST_SOURCES} test_arm.c) endif() if(CAPSTONE_AARCH64_SUPPORT) @@ -270,7 +275,6 @@ if(CAPSTONE_AARCH64_SUPPORT) arch/AArch64/AArch64GenCSMappingInsnName.inc arch/AArch64/AArch64GenCSMappingInsnOp.inc ) - set(TEST_SOURCES ${TEST_SOURCES} test_aarch64.c) endif() if(CAPSTONE_MIPS_SUPPORT) @@ -302,7 +306,6 @@ if(CAPSTONE_MIPS_SUPPORT) arch/Mips/MipsInstPrinter.h arch/Mips/MipsMapping.h ) - set(TEST_SOURCES ${TEST_SOURCES} test_mips.c) endif() if(CAPSTONE_PPC_SUPPORT) @@ -332,7 +335,6 @@ if(CAPSTONE_PPC_SUPPORT) arch/PowerPC/PPCGenSubtargetInfo.inc arch/PowerPC/PPCGenRegisterInfo.inc ) - set(TEST_SOURCES ${TEST_SOURCES} test_ppc.c) endif() if(CAPSTONE_X86_SUPPORT) @@ -386,7 +388,6 @@ if(CAPSTONE_X86_SUPPORT) if(NOT CAPSTONE_BUILD_DIET) set(SOURCES_X86 ${SOURCES_X86} arch/X86/X86ATTInstPrinter.c) endif() - set(TEST_SOURCES ${TEST_SOURCES} test_x86.c test_customized_mnem.c) endif() if(CAPSTONE_SPARC_SUPPORT) @@ -409,7 +410,6 @@ if(CAPSTONE_SPARC_SUPPORT) arch/Sparc/SparcMapping.h arch/Sparc/SparcMappingInsn.inc ) - set(TEST_SOURCES ${TEST_SOURCES} test_sparc.c) endif() if(CAPSTONE_SYSZ_SUPPORT) @@ -434,7 +434,6 @@ if(CAPSTONE_SYSZ_SUPPORT) arch/SystemZ/SystemZMappingInsn.inc arch/SystemZ/SystemZMCTargetDesc.h ) - set(TEST_SOURCES ${TEST_SOURCES} test_systemz.c) endif() if(CAPSTONE_XCORE_SUPPORT) @@ -455,7 +454,6 @@ if(CAPSTONE_XCORE_SUPPORT) arch/XCore/XCoreMapping.h arch/XCore/XCoreMappingInsn.inc ) - set(TEST_SOURCES ${TEST_SOURCES} test_xcore.c) endif() if(CAPSTONE_M68K_SUPPORT) @@ -468,7 +466,6 @@ if(CAPSTONE_M68K_SUPPORT) set(HEADERS_M68K arch/M68K/M68KDisassembler.h ) - set(TEST_SOURCES ${TEST_SOURCES} test_m68k.c) endif() if(CAPSTONE_TMS320C64X_SUPPORT) @@ -488,7 +485,6 @@ if(CAPSTONE_TMS320C64X_SUPPORT) arch/TMS320C64x/TMS320C64xInstPrinter.h arch/TMS320C64x/TMS320C64xMapping.h ) - set(TEST_SOURCES ${TEST_SOURCES} test_tms320c64x.c) endif() if(CAPSTONE_M680X_SUPPORT) @@ -503,7 +499,6 @@ if(CAPSTONE_M680X_SUPPORT) arch/M680X/M680XDisassembler.h arch/M680X/M680XDisassemblerInternals.h ) - set(TEST_SOURCES ${TEST_SOURCES} test_m680x.c) endif() if(CAPSTONE_EVM_SUPPORT) @@ -520,7 +515,6 @@ if(CAPSTONE_EVM_SUPPORT) arch/EVM/EVMMapping.h arch/EVM/EVMMappingInsn.inc ) - set(TEST_SOURCES ${TEST_SOURCES} test_evm.c) endif() if(CAPSTONE_WASM_SUPPORT) @@ -536,7 +530,6 @@ if(CAPSTONE_WASM_SUPPORT) arch/WASM/WASMInstPrinter.h arch/WASM/WASMMapping.h ) - set(TEST_SOURCES ${TEST_SOURCES} test_wasm.c) endif() if(CAPSTONE_MOS65XX_SUPPORT) @@ -547,7 +540,6 @@ if(CAPSTONE_MOS65XX_SUPPORT) set(HEADERS_SOURCES_MOS65XX arch/MOS65XX/MOS65XXDisassembler.h ) - set(TEST_SOURCES ${TEST_SOURCES} test_mos65xx.c) endif() if(CAPSTONE_BPF_SUPPORT) @@ -565,7 +557,6 @@ if(CAPSTONE_BPF_SUPPORT) arch/BPF/BPFMapping.h arch/BPF/BPFModule.h ) - set(TEST_SOURCES ${TEST_SOURCES} test_bpf.c) endif() if(CAPSTONE_RISCV_SUPPORT) @@ -591,7 +582,6 @@ if(CAPSTONE_RISCV_SUPPORT) arch/RISCV/RISCVMappingInsn.inc arch/RISCV/RISCVMappingInsnOp.inc ) - set(TEST_SOURCES ${TEST_SOURCES} test_riscv.c) endif() if(CAPSTONE_SH_SUPPORT) @@ -607,7 +597,6 @@ if(CAPSTONE_SH_SUPPORT) arch/SH/SHModule.h arch/SH/SHInsnTable.inc ) - set(TEST_SOURCES ${TEST_SOURCES} test_sh.c) endif() if (CAPSTONE_TRICORE_SUPPORT) @@ -628,7 +617,6 @@ if (CAPSTONE_TRICORE_SUPPORT) arch/TriCore/TriCoreMapping.h arch/TriCore/TriCoreModule.h ) - set(TEST_SOURCES ${TEST_SOURCES} test_tricore.c) endif () if (CAPSTONE_ALPHA_SUPPORT) @@ -652,7 +640,6 @@ if (CAPSTONE_ALPHA_SUPPORT) arch/Alpha/AlphaGenCSMappingInsn.inc arch/Alpha/AlphaGenCSMappingInsnName.inc ) - set(TEST_SOURCES ${TEST_SOURCES} test_alpha.c) endif () if(CAPSTONE_HPPA_SUPPORT) @@ -670,7 +657,6 @@ if(CAPSTONE_HPPA_SUPPORT) arch/HPPA/HPPAMapping.h arch/HPPA/HPPAModule.h ) - set(TEST_SOURCES ${TEST_SOURCES} test_hppa.c) endif() if (CAPSTONE_LOONGARCH_SUPPORT) @@ -688,7 +674,6 @@ if (CAPSTONE_LOONGARCH_SUPPORT) arch/LoongArch/LoongArchModule.h arch/LoongArch/LoongArchLinkage.h ) - set(TEST_SOURCES ${TEST_SOURCES} test_loongarch.c) endif () if (CAPSTONE_OSXKERNEL_SUPPORT) @@ -766,27 +751,13 @@ if(BUILD_SHARED_LIBS) ) endif() -if(CAPSTONE_BUILD_TESTS) - set(CMAKE_FOLDER "Tests") - enable_testing() - foreach(TSRC ${TEST_SOURCES}) - string(REGEX REPLACE ".c$" "" TBIN ${TSRC}) - add_executable(${TBIN} "tests/${TSRC}") - target_link_libraries(${TBIN} PRIVATE capstone) - add_test(NAME "capstone_${TBIN}" COMMAND ${TBIN}) - endforeach() - if(CAPSTONE_ARM_SUPPORT) - set(ARM_REGRESS_TEST test_arm_regression.c) - string(REGEX REPLACE ".c$" "" ARM_REGRESS_BIN ${ARM_REGRESS_TEST}) - add_executable(${ARM_REGRESS_BIN} "suite/arm/${ARM_REGRESS_TEST}") - target_link_libraries(${ARM_REGRESS_BIN} PRIVATE capstone) - add_test(NAME "capstone_${ARM_REGRESS_BIN}" COMMAND ${ARM_REGRESS_BIN}) - endif() - # fuzz target built with the tests - add_executable(fuzz_disasm suite/fuzz/onefile.c suite/fuzz/fuzz_disasm.c suite/fuzz/platform.c) - target_link_libraries(fuzz_disasm PRIVATE capstone) - unset(CMAKE_FOLDER) -endif() +# Fuzzer if this is moved to it's own CMakeLists.txt (as it should be) +# the OSS fuzzer build fails. And must be fixed. +# Simply because it builds the fuzzer there again with hard-coded paths. +# See: https://github.com/google/oss-fuzz/blob/master/projects/capstone/build.sh +# and: https://github.com/capstone-engine/capstone/issues/2454 +add_executable(fuzz_disasm ${PROJECT_SOURCE_DIR}/suite/fuzz/onefile.c ${PROJECT_SOURCE_DIR}/suite/fuzz/fuzz_disasm.c ${PROJECT_SOURCE_DIR}/suite/fuzz/platform.c) +target_link_libraries(fuzz_disasm PRIVATE capstone) source_group("Source\\Engine" FILES ${SOURCES_ENGINE}) source_group("Source\\ARM" FILES ${SOURCES_ARM}) @@ -900,7 +871,6 @@ if(CAPSTONE_INSTALL) "${CMAKE_CURRENT_BINARY_DIR}/cmake_uninstall.cmake" IMMEDIATE @ONLY ) - set(CMAKE_FOLDER) add_custom_target(UNINSTALL COMMAND ${CMAKE_COMMAND} -P ${CMAKE_CURRENT_BINARY_DIR}/cmake_uninstall.cmake) set_target_properties(UNINSTALL PROPERTIES FOLDER CMakePredefinedTargets @@ -919,32 +889,17 @@ if(CAPSTONE_BUILD_CSTOOL) endif() if(CAPSTONE_BUILD_CSTEST) - include(ExternalProject) - ExternalProject_Add(cmocka_ext - PREFIX extern - GIT_REPOSITORY "https://git.cryptomilk.org/projects/cmocka.git" - GIT_TAG "origin/stable-1.1" - GIT_SHALLOW true - CONFIGURE_COMMAND cmake -DBUILD_SHARED_LIBS=OFF ../cmocka_ext/ - BUILD_COMMAND cmake --build . --config Release - INSTALL_COMMAND "" - ) - set(CMOCKA_INCLUDE_DIR ${CMAKE_CURRENT_BINARY_DIR}/extern/src/cmocka_ext/include) - set(CMOCKA_LIB_DIR ${CMAKE_CURRENT_BINARY_DIR}/extern/src/cmocka_ext-build/src/) - add_library(cmocka STATIC IMPORTED) - set_target_properties(cmocka PROPERTIES IMPORTED_LOCATION ${CMOCKA_LIB_DIR}/libcmocka.a) - - file(GLOB CSTEST_SRC suite/cstest/src/*.c) - add_executable(cstest ${CSTEST_SRC}) - add_dependencies(cstest cmocka_ext) - target_link_libraries(cstest PUBLIC capstone cmocka) - target_include_directories(cstest PRIVATE - $ - ${PROJECT_SOURCE_DIR}/suite/cstest/include - ${CMOCKA_INCLUDE_DIR} - ) - - if(CAPSTONE_INSTALL) - install(TARGETS cstest EXPORT capstone-targets DESTINATION ${CMAKE_INSTALL_BINDIR}) - endif() + enable_testing() + set(CSTEST_DIR ${PROJECT_SOURCE_DIR}/suite/cstest) + add_subdirectory(${CSTEST_DIR}) + + # Integration and unit tests + set(TESTS_INTEGRATION_DIR ${PROJECT_SOURCE_DIR}/tests/integration) + add_subdirectory(${TESTS_INTEGRATION_DIR}) + set(TESTS_UNIT_DIR ${PROJECT_SOURCE_DIR}/tests/unit) + add_subdirectory(${TESTS_UNIT_DIR}) + + # Unit tests for auto-sync + set(AUTO_SYNC_C_TEST_DIR ${PROJECT_SOURCE_DIR}/suite/auto-sync/c_tests/) + add_subdirectory(${AUTO_SYNC_C_TEST_DIR}) endif() diff --git a/COMPILE_CMAKE.TXT b/COMPILE_CMAKE.TXT index ad28dab88a..abf143aad4 100644 --- a/COMPILE_CMAKE.TXT +++ b/COMPILE_CMAKE.TXT @@ -1,8 +1,6 @@ This documentation explains how to compile Capstone with CMake, focus on using Microsoft Visual C as the compiler. -To compile Capstone on *nix, see COMPILE.TXT. - To compile Capstone on Windows using Visual Studio, see COMPILE_MSVC.TXT. *-*-*-*-*-* @@ -57,7 +55,7 @@ Get CMake for free from http://www.cmake.org. - CAPSTONE_X86_REDUCE: change this to ON to make X86 binary smaller. - CAPSTONE_X86_ATT_DISABLE: change this to ON to disable AT&T syntax on x86. - CAPSTONE_DEBUG: change this to ON to enable extra debug assertions. - - CAPSTONE_BUILD_CSTEST: Build `cstest` in `suite/cstest/` + - CAPSTONE_BUILD_CSTEST: Build `cstest` in `suite/cstest/`. `cstest` requires `libyaml` on your system. - ENABLE_ASAN: Compiles Capstone with the address sanitizer. By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE diff --git a/COMPILE.TXT b/COMPILE_MAKE.TXT similarity index 98% rename from COMPILE.TXT rename to COMPILE_MAKE.TXT index 63cbf3ecdc..1bafd4dc7c 100644 --- a/COMPILE.TXT +++ b/COMPILE_MAKE.TXT @@ -1,3 +1,11 @@ + +# NOTICE + +> Please be aware that the Makefile build is deprecated. +> Use cmake instead. + +
+ This documentation explains how to compile, install & run Capstone on MacOSX, Linux, *BSD & Solaris. We also show steps to cross-compile for Microsoft Windows. diff --git a/COMPILE_MSVC.TXT b/COMPILE_MSVC.TXT index 77d16c558b..4e023ceaa3 100644 --- a/COMPILE_MSVC.TXT +++ b/COMPILE_MSVC.TXT @@ -1,7 +1,7 @@ This documentation explains how to compile Capstone on Windows using Microsoft Visual Studio version 2010 or newer. -To compile Capstone on *nix, see COMPILE.TXT +To compile Capstone on *nix, see COMPILE_CMAKE.TXT To compile Capstone with CMake, see COMPILE_CMAKE.TXT diff --git a/HACK.TXT b/HACK.TXT index 5858f61cd9..7085adcc3a 100644 --- a/HACK.TXT +++ b/HACK.TXT @@ -3,7 +3,7 @@ Code structure Capstone source is organized as followings. -. <- core engine + README + COMPILE.TXT etc +. <- core engine + README + COMPILE_CMAKE.TXT etc ├── arch <- code handling disasm engine for each arch │   ├── AArch64 <- AArch64 engine │   ├── Alpha <- Alpha engine @@ -39,7 +39,7 @@ Capstone source is organized as followings. └── xcode <- Xcode support (for MacOSX compile) -Follow the instructions in COMPILE.TXT for how to compile and run test code. +Follow the instructions in COMPILE_CMAKE.TXT for how to compile and run test code. Note: if you find some strange bugs, it is recommended to firstly clean the code and try to recompile/reinstall again. This can be done with: @@ -111,13 +111,13 @@ Compile: Tests: - tests/Makefile - tests/test_basic.c -- tests/test_detail.c - tests/test_iter.c - tests/test_newarch.c - suite/fuzz/platform.c: add the architecture and its modes to the list of fuzzed platforms - suite/capstone_get_setup.c - suite/MC/newarch/mode.mc: samples - suite/test_corpus.py: correspondence between architecture and mode as text and architecture number for fuzzing +- suite/cstest/ Bindings: - bindings/Makefile diff --git a/Makefile b/Makefile index 15ca6db23c..12214c28d9 100644 --- a/Makefile +++ b/Makefile @@ -457,12 +457,6 @@ PKGCFGF = $(BLDIR)/$(LIBNAME).pc all: $(LIBRARY) $(ARCHIVE) $(PKGCFGF) ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY))) @V=$(V) CC=$(CC) $(MAKE) -C cstool -ifndef BUILDDIR - $(MAKE) -C tests -else - $(MAKE) -C tests BUILDDIR=$(BLDIR) -endif - $(call install-library,$(BLDIR)/tests/) endif ifeq ($(CAPSTONE_SHARED),yes) @@ -556,9 +550,7 @@ clean: ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY))) $(MAKE) -C cstool clean - $(MAKE) -C tests clean $(MAKE) -C suite/fuzz clean - rm -f $(BLDIR)/tests/lib$(LIBNAME).$(EXT) endif ifdef BUILDDIR @@ -583,23 +575,8 @@ dist: git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip -TESTS = test_basic test_detail test_arm test_aarch64 test_m68k test_mips test_ppc test_sparc test_tricore test_hppa -TESTS += test_systemz test_x86 test_xcore test_iter test_evm test_riscv test_mos65xx test_wasm test_bpf test_alpha -TESTS += test_loongarch -TESTS += test_basic.static test_detail.static test_arm.static test_aarch64.static -TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static -TESTS += test_systemz.static test_x86.static test_xcore.static test_m680x.static -TESTS += test_skipdata test_skipdata.static test_iter.static test_evm.static test_riscv.static -TESTS += test_mos65xx.static test_wasm.static test_bpf.static test_alpha.static test_hppa.static -TESTS += test_loongarch.static - -check: $(TESTS) - checkfuzz: fuzztest fuzzallcorp -test_%: - ./tests/$@ > /dev/null && echo OK || echo FAILED - FUZZ_INPUTS = $(shell find suite/MC -type f -name '*.cs') buildfuzz: diff --git a/Mapping.c b/Mapping.c index 2f871273d8..c4f352185e 100644 --- a/Mapping.c +++ b/Mapping.c @@ -400,3 +400,44 @@ void map_set_alias_id(MCInst *MI, const SStream *O, const name_map *alias_mnem_i MI->flat_insn->alias_id = name2id(alias_mnem_id_map, map_size, alias_mnem); } +/// Does a binary search over the given map and searches for @id. +/// If @id exists in @map, it sets @found to true and returns +/// the value for the @id. +/// Otherwise, @found is set to false and it returns UINT64_MAX. +/// +/// Of course it assumes the map is sorted. +uint64_t enum_map_bin_search(const cs_enum_id_map *map, size_t map_len, + const char *id, bool *found) +{ + size_t l = 0; + size_t r = map_len; + size_t id_len = strlen(id); + + while (l <= r) { + size_t m = (l + r) / 2; + size_t j = 0; + size_t i = 0; + size_t entry_len = strlen(map[m].str); + + while (j < entry_len && i < id_len && id[i] == map[m].str[j]) { + ++j, ++i; + } + if (i == id_len && j == entry_len) { + *found = true; + return map[m].val; + } + + if (id[i] < map[m].str[j]) { + r = m - 1; + } else if (id[i] > map[m].str[j]) { + l = m + 1; + } + if (m == 0 || (l + r) / 2 >= map_len) { + // Break before we go out of bounds. + break; + } + } + *found = false; + return UINT64_MAX; +} + diff --git a/Mapping.h b/Mapping.h index 3efd3f3ca5..a2f60cabfe 100644 --- a/Mapping.h +++ b/Mapping.h @@ -232,4 +232,27 @@ bool map_use_alias_details(const MCInst *MI); void map_set_alias_id(MCInst *MI, const SStream *O, const name_map *alias_mnem_id_map, int map_size); +/// Mapping from Capstone enumeration identifiers and their values. +/// +/// This map MUST BE sorted to allow binary searches. +/// Please always ensure the map is sorted after you added a value. +/// +/// You can sort the map with Python. +/// Copy the map into a file and run: +/// +/// ```python +/// with open("/tmp/file_with_map_entries") as f: +/// text = f.readlines() +/// +/// text.sort() +/// print(''.join(text)) +/// ``` +typedef struct { + const char *str; ///< The name of the enumeration identifier + uint64_t val; ///< The value of the identifier +} cs_enum_id_map; + +uint64_t enum_map_bin_search(const cs_enum_id_map *map, size_t map_len, + const char *id, bool *found); + #endif // CS_MAPPING_H diff --git a/README.md b/README.md index f1a53a0e02..9dbfbe5427 100644 --- a/README.md +++ b/README.md @@ -49,7 +49,7 @@ Further information is available at https://www.capstone-engine.org Compile ------- -See COMPILE.TXT file for how to compile and install Capstone. +See [COMPILE_CMAKE.TXT](COMPILE_CMAKE.TXT) file for how to compile and install Capstone. Documentation diff --git a/arch/AArch64/AArch64GenDisassemblerTables.inc b/arch/AArch64/AArch64GenDisassemblerTables.inc index 6956ba2590..015d8f709e 100644 --- a/arch/AArch64/AArch64GenDisassemblerTables.inc +++ b/arch/AArch64/AArch64GenDisassemblerTables.inc @@ -35510,6 +35510,7 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ /* Decoding complete. */ \ return S; \ } else { \ + MCInst_clear(MI); \ /* If the decoding was incomplete, skip. */ \ Ptr += NumToSkip; \ /* Reset decode status. This also drops a SoftFail status that could be */ \ diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c index 73acbaf155..4db25f2ab6 100644 --- a/arch/AArch64/AArch64InstPrinter.c +++ b/arch/AArch64/AArch64InstPrinter.c @@ -462,12 +462,18 @@ void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O) if ((Opcode == AArch64_MOVZXi || Opcode == AArch64_MOVZWi || Opcode == AArch64_MOVNXi || Opcode == AArch64_MOVNWi) && MCOperand_isExpr(MCInst_getOperand(MI, (1)))) { - SStream_concat0(O, ""); + printUInt64Bang(O, MCInst_getOpVal(MI, 1)); + if (detail_is_set(MI) && useAliasDetails) { + AArch64_set_detail_op_imm(MI, 1, AARCH64_OP_IMM, MCInst_getOpVal(MI, 1)); + } } if ((Opcode == AArch64_MOVKXi || Opcode == AArch64_MOVKWi) && MCOperand_isExpr(MCInst_getOperand(MI, (2)))) { - SStream_concat0(O, ""); + printUInt64Bang(O, MCInst_getOpVal(MI, 2)); + if (detail_is_set(MI) && useAliasDetails) { + AArch64_set_detail_op_imm(MI, 2, AARCH64_OP_IMM, MCInst_getOpVal(MI, 2)); + } } // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but @@ -994,7 +1000,7 @@ void printOperand(MCInst *MI, unsigned OpNo, SStream *O) printInt64Bang(O, MCOperand_getImm(Op)); SStream_concat0(O, markup(">")); } else { - SStream_concat0(O, ""); + printUInt64Bang(O, MCInst_getOpVal(MI, OpNo)); } } @@ -1282,7 +1288,7 @@ DEFINE_printRegWithShiftExtend(false, 128, x, 0); assert(0 && \ "Unsupported predicate-as-counter register"); \ SStream_concat(O, "%s", "pn"); \ - printUInt32(O, (Reg - AArch64_P0)); \ + printUInt32(O, (Reg - AArch64_PN0)); \ switch (EltSize) { \ case 0: \ break; \ @@ -1380,7 +1386,7 @@ void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O) printUInt32Bang(O, (MCOperand_getImm(MO) * Scale)); SStream_concat0(O, markup(">")); } else { - SStream_concat0(O, ""); + printUInt64Bang(O, MCOperand_getImm(MO)); } } @@ -1395,7 +1401,7 @@ void printAMIndexedWB(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O) printUInt32Bang(O, MCOperand_getImm(MO1) * Scale); SStream_concat0(O, markup(">")); } else { - SStream_concat0(O, ""); + printUInt64Bang(O, MCOperand_getImm(MO1)); } SStream_concat0(O, "]"); } @@ -1964,7 +1970,7 @@ void printImplicitlyTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O) NumLanes), \ LaneKind), \ OpNum, NumLanes, CHAR(LaneKind)); \ - if (CHAR(LaneKind) == 0) { \ + if (CHAR(LaneKind) == '0') { \ printVectorList(MI, OpNum, O, ""); \ return; \ } \ @@ -2026,7 +2032,7 @@ void printAlignedLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O) return; } - SStream_concat0(O, ""); + printUInt64Bang(O, MCOperand_getImm(Op)); } void printAdrLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O) @@ -2048,7 +2054,7 @@ void printAdrLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O) return; } - SStream_concat0(O, ""); + printUInt64Bang(O, MCOperand_getImm(Op)); } void printAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O) @@ -2070,7 +2076,7 @@ void printAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O) return; } - SStream_concat0(O, ""); + printUInt64Bang(O, MCOperand_getImm(Op)); } void printAdrAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O) { @@ -2095,7 +2101,7 @@ void printAdrAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O) return; } - SStream_concat0(O, ""); + printUInt64Bang(O, MCOperand_getImm(Op)); } void printBarrierOption(MCInst *MI, unsigned OpNo, SStream *O) @@ -2287,6 +2293,8 @@ void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O) AArch64SVEPredPattern_lookupSVEPREDPATByEncoding(Val); if (Pat) SStream_concat0(O, Pat->Name); + else + printUInt32Bang(O, Val); } void printSVEVecLenSpecifier(MCInst *MI, unsigned OpNum, SStream *O) @@ -2371,7 +2379,7 @@ DECLARE_printImmSVE_U64(uint64_t); #define DEFINE_isSignedType(T) \ static inline bool CONCAT(isSignedType, T)() \ { \ - return CHAR(t) == 'i'; \ + return CHAR(T) == 'i'; \ } DEFINE_isSignedType(int8_t); DEFINE_isSignedType(int16_t); diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c index ceaaff7d90..68d588c190 100644 --- a/arch/AArch64/AArch64Mapping.c +++ b/arch/AArch64/AArch64Mapping.c @@ -97,9 +97,9 @@ static void setup_sme_operand(MCInst *MI) AArch64_get_detail_op(MI, 0)->sme.type = AARCH64_SME_OP_INVALID; AArch64_get_detail_op(MI, 0)->sme.tile = AARCH64_REG_INVALID; AArch64_get_detail_op(MI, 0)->sme.slice_reg = AARCH64_REG_INVALID; - AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm = -1; - AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm_range.first = -1; - AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm_range.offset = -1; + AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm = AARCH64_SLICE_IMM_INVALID; + AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm_range.first = AARCH64_SLICE_IMM_RANGE_INVALID; + AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm_range.offset = AARCH64_SLICE_IMM_RANGE_INVALID; } static void setup_pred_operand(MCInst *MI) @@ -556,6 +556,9 @@ static void AArch64_add_not_defined_ops(MCInst *MI, const SStream *OS) default: return; case AARCH64_INS_ALIAS_FMOV: + if (AArch64_get_detail_op(MI, -1)->type == AARCH64_OP_FP) { + break; + } AArch64_insert_detail_op_float_at(MI, -1, 0.0f, CS_AC_READ); break; case AARCH64_INS_ALIAS_LD1: @@ -1315,6 +1318,10 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group, int64_t Offset = MCInst_getOpVal(MI, OpNum); AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM, (MI->address & -4) + Offset); + } else { + // Expression + AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM, + MCOperand_isImm(MCInst_getOperand(MI, OpNum))); } break; } @@ -1323,11 +1330,18 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group, int64_t Offset = MCInst_getOpVal(MI, OpNum) * 4096; AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM, (MI->address & -4096) + Offset); + } else { + // Expression + AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM, + MCOperand_isImm(MCInst_getOperand(MI, OpNum))); } break; } case AArch64_OP_GROUP_AdrAdrpLabel: { if (!MCOperand_isImm(MCInst_getOperand(MI, OpNum))) { + // Expression + AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM, + MCOperand_isImm(MCInst_getOperand(MI, OpNum))); break; } int64_t Offset = MCInst_getOpVal(MI, OpNum); @@ -1345,6 +1359,10 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group, int64_t Offset = MCInst_getOpVal(MI, OpNum) * 4; AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM, MI->address + Offset); + } else { + // Expression + AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM, + MCOperand_isImm(MCInst_getOperand(MI, OpNum))); } break; } @@ -1502,7 +1520,7 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group, AArch64_set_detail_op_sme(MI, OpNum, AARCH64_SME_MATRIX_TILE_LIST, AARCH64LAYOUT_VL_D, - AARCH64_REG_ZAD0 + I); + (int) (AARCH64_REG_ZAD0 + I)); AArch64_inc_op_count(MI); } break; @@ -1607,8 +1625,10 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group, unsigned Val = MCInst_getOpVal(MI, OpNum); const AArch64SVEPredPattern_SVEPREDPAT *Pat = AArch64SVEPredPattern_lookupSVEPREDPATByEncoding(Val); - if (!Pat) + if (!Pat) { + AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM, Val); break; + } aarch64_sysop sysop; sysop.alias = Pat->SysAlias; sysop.sub_type = AARCH64_OP_SVEPREDPAT; @@ -1738,6 +1758,7 @@ static void add_cs_detail_template_1(MCInst *MI, aarch64_op_group op_group, (1 << AArch64_AM_getShiftValue(Shift)); AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM, Val); + break; } case AArch64_OP_GROUP_Imm8OptLsl_uint16_t: case AArch64_OP_GROUP_Imm8OptLsl_uint32_t: @@ -1747,6 +1768,7 @@ static void add_cs_detail_template_1(MCInst *MI, aarch64_op_group op_group, (1 << AArch64_AM_getShiftValue(Shift)); AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM, Val); + break; } } break; @@ -1791,7 +1813,7 @@ static void add_cs_detail_template_1(MCInst *MI, aarch64_op_group op_group, AArch64_set_detail_op_sme(MI, OpNum, AARCH64_SME_MATRIX_SLICE_OFF, AARCH64LAYOUT_INVALID, - MCInst_getOpVal(MI, OpNum) * scale); + (uint32_t) (MCInst_getOpVal(MI, OpNum) * scale)); } else if (AArch64_get_detail_op(MI, 0)->type == AARCH64_OP_PRED) { // The index is part of a predicate AArch64_set_detail_op_pred(MI, OpNum); @@ -1852,7 +1874,7 @@ static void add_cs_detail_template_1(MCInst *MI, aarch64_op_group op_group, unsigned EltSize = temp_arg_0; AArch64_get_detail_op(MI, 0)->vas = EltSize; AArch64_set_detail_op_reg( - MI, OpNum, MCInst_getOpVal(MI, OpNum) - AArch64_P0); + MI, OpNum, MCInst_getOpVal(MI, OpNum) - AArch64_PN0); break; } case AArch64_OP_GROUP_PrefetchOp_0: @@ -1925,7 +1947,8 @@ static void add_cs_detail_template_1(MCInst *MI, aarch64_op_group op_group, case AArch64_OP_GROUP_UImm12Offset_2: case AArch64_OP_GROUP_UImm12Offset_4: case AArch64_OP_GROUP_UImm12Offset_8: { - unsigned Scale = temp_arg_0; + // Otherwise it is an expression. For which we only add the immediate + unsigned Scale = MCOperand_isImm(MCInst_getOperand(MI, OpNum)) ? temp_arg_0 : 1; AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM, Scale * MCInst_getOpVal(MI, OpNum)); break; @@ -2050,6 +2073,7 @@ static void add_cs_detail_template_2(MCInst *MI, aarch64_op_group op_group, case AArch64_OP_GROUP_TypedVectorList_0_h: case AArch64_OP_GROUP_TypedVectorList_0_q: case AArch64_OP_GROUP_TypedVectorList_0_s: + case AArch64_OP_GROUP_TypedVectorList_0_0: case AArch64_OP_GROUP_TypedVectorList_16_b: case AArch64_OP_GROUP_TypedVectorList_1_d: case AArch64_OP_GROUP_TypedVectorList_2_d: @@ -2107,7 +2131,7 @@ static void add_cs_detail_template_2(MCInst *MI, aarch64_op_group op_group, case 'q': vas = AARCH64LAYOUT_VL_Q; break; - case '\0': + case '0': // Implicitly Typed register break; } @@ -2389,6 +2413,7 @@ void AArch64_add_cs_detail(MCInst *MI, int /* aarch64_op_group */ op_group, case AArch64_OP_GROUP_TypedVectorList_0_h: case AArch64_OP_GROUP_TypedVectorList_0_q: case AArch64_OP_GROUP_TypedVectorList_0_s: + case AArch64_OP_GROUP_TypedVectorList_0_0: case AArch64_OP_GROUP_TypedVectorList_16_b: case AArch64_OP_GROUP_TypedVectorList_1_d: case AArch64_OP_GROUP_TypedVectorList_2_d: @@ -2500,7 +2525,7 @@ void AArch64_set_detail_op_imm(MCInst *MI, unsigned OpNum, if (AArch64_get_detail_op(MI, 0)->type == AARCH64_OP_SME) { AArch64_set_detail_op_sme(MI, OpNum, AARCH64_SME_MATRIX_SLICE_OFF, - AARCH64LAYOUT_INVALID, 1); + AARCH64LAYOUT_INVALID, (uint32_t) 1); } else if (AArch64_get_detail_op(MI, 0)->type == AARCH64_OP_PRED) { AArch64_set_detail_op_pred(MI, OpNum); } else { @@ -2524,7 +2549,7 @@ void AArch64_set_detail_op_imm(MCInst *MI, unsigned OpNum, } void AArch64_set_detail_op_imm_range(MCInst *MI, unsigned OpNum, - int64_t FirstImm, int64_t Offset) + uint32_t FirstImm, uint32_t Offset) { if (!detail_is_set(MI)) return; @@ -2534,8 +2559,8 @@ void AArch64_set_detail_op_imm_range(MCInst *MI, unsigned OpNum, if (AArch64_get_detail_op(MI, 0)->type == AARCH64_OP_SME) { AArch64_set_detail_op_sme(MI, OpNum, AARCH64_SME_MATRIX_SLICE_OFF_RANGE, - AARCH64LAYOUT_INVALID, FirstImm, - Offset); + AARCH64LAYOUT_INVALID, (uint32_t) FirstImm, + (uint32_t) Offset); } else if (AArch64_get_detail_op(MI, 0)->type == AARCH64_OP_PRED) { assert(0 && "Unkown SME predicate imm range type"); } else { @@ -2694,15 +2719,15 @@ void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum, if (!detail_is_set(MI)) return; AArch64_get_detail_op(MI, 0)->type = AARCH64_OP_SME; - va_list args; switch (part) { default: printf("Unhandled SME operand part %d\n", part); assert(0); - case AARCH64_SME_MATRIX_TILE_LIST: + case AARCH64_SME_MATRIX_TILE_LIST: { setup_sme_operand(MI); + va_list args; va_start(args, vas); - int Tile = va_arg(args, int); + int Tile = va_arg(args, int); // NOLINT(clang-analyzer-valist.Uninitialized) va_end(args); AArch64_get_detail_op(MI, 0)->sme.type = AARCH64_SME_OP_TILE; AArch64_get_detail_op(MI, 0)->sme.tile = Tile; @@ -2710,6 +2735,7 @@ void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum, AArch64_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); AArch64_get_detail(MI)->is_doing_sme = true; break; + } case AARCH64_SME_MATRIX_TILE: assert(map_get_op_type(MI, OpNum) == CS_OP_REG); @@ -2731,23 +2757,26 @@ void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum, AArch64_get_detail_op(MI, 0)->sme.slice_reg = MCInst_getOpVal(MI, OpNum); break; - case AARCH64_SME_MATRIX_SLICE_OFF: + case AARCH64_SME_MATRIX_SLICE_OFF: { assert((map_get_op_type(MI, OpNum) & ~(CS_OP_MEM | CS_OP_BOUND)) == CS_OP_IMM); // Because we took care of the slice register before, the op at -1 must be a SME operand. assert(AArch64_get_detail_op(MI, 0)->type == AARCH64_OP_SME); assert(AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm == - -1); + AARCH64_SLICE_IMM_INVALID); + va_list args; va_start(args, vas); - int64_t offset = va_arg(args, int64_t); + uint16_t offset = va_arg(args, uint32_t); // NOLINT(clang-analyzer-valist.Uninitialized) va_end(args); AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm = offset; break; + } case AARCH64_SME_MATRIX_SLICE_OFF_RANGE: { + va_list args; va_start(args, vas); - int8_t First = va_arg(args, int); - int8_t Offset = va_arg(args, int); + uint8_t First = va_arg(args, uint32_t); // NOLINT(clang-analyzer-valist.Uninitialized) + uint8_t Offset = va_arg(args, uint32_t); // NOLINT(clang-analyzer-valist.Uninitialized) va_end(args); AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm_range.first = First; diff --git a/arch/AArch64/AArch64Mapping.h b/arch/AArch64/AArch64Mapping.h index dd47fee57d..3afdbeefca 100644 --- a/arch/AArch64/AArch64Mapping.h +++ b/arch/AArch64/AArch64Mapping.h @@ -56,7 +56,7 @@ void AArch64_set_detail_op_reg(MCInst *MI, unsigned OpNum, aarch64_reg Reg); void AArch64_set_detail_op_imm(MCInst *MI, unsigned OpNum, aarch64_op_type ImmType, int64_t Imm); void AArch64_set_detail_op_imm_range(MCInst *MI, unsigned OpNum, - int64_t FirstImm, int64_t offset); + uint32_t FirstImm, uint32_t offset); void AArch64_set_detail_op_mem(MCInst *MI, unsigned OpNum, uint64_t Val); void AArch64_set_detail_op_mem_offset(MCInst *MI, unsigned OpNum, uint64_t Val); void AArch64_set_detail_shift_ext(MCInst *MI, unsigned OpNum, bool SignExtend, diff --git a/arch/Alpha/AlphaModule.c b/arch/Alpha/AlphaModule.c index 271f177656..4d2279c6ca 100644 --- a/arch/Alpha/AlphaModule.c +++ b/arch/Alpha/AlphaModule.c @@ -32,8 +32,11 @@ cs_err ALPHA_global_init(cs_struct *ud) cs_err ALPHA_option(cs_struct *handle, cs_opt_type type, size_t value) { - if (type == CS_OPT_SYNTAX) + if (type == CS_OPT_SYNTAX) { handle->syntax = (int)value; + } else if (type == CS_OPT_MODE) { + handle->mode = (cs_mode)value; + } return CS_ERR_OK; } diff --git a/arch/M68K/M68KDisassembler.c b/arch/M68K/M68KDisassembler.c index 5c555ae4c1..61d8b3dbf5 100644 --- a/arch/M68K/M68KDisassembler.c +++ b/arch/M68K/M68KDisassembler.c @@ -278,10 +278,10 @@ static unsigned int peek_imm_16(const m68k_info *info) { return m68k_read_safe_1 static unsigned int peek_imm_32(const m68k_info *info) { return m68k_read_safe_32((info), (info)->pc); } static unsigned long long peek_imm_64(const m68k_info *info) { return m68k_read_safe_64((info), (info)->pc); } -static unsigned int read_imm_8(m68k_info *info) { const unsigned int value = peek_imm_8(info); (info)->pc+=2; return value; } -static unsigned int read_imm_16(m68k_info *info) { const unsigned int value = peek_imm_16(info); (info)->pc+=2; return value; } -static unsigned int read_imm_32(m68k_info *info) { const unsigned int value = peek_imm_32(info); (info)->pc+=4; return value; } -static unsigned long long read_imm_64(m68k_info *info) { const unsigned long long value = peek_imm_64(info); (info)->pc+=8; return value; } +static unsigned int read_imm_8(m68k_info *info) { const unsigned int value = peek_imm_8(info); (info)->pc+=2; return value & 0xff; } +static unsigned int read_imm_16(m68k_info *info) { const unsigned int value = peek_imm_16(info); (info)->pc+=2; return value & 0xffff; } +static unsigned int read_imm_32(m68k_info *info) { const unsigned int value = peek_imm_32(info); (info)->pc+=4; return value & 0xffffffff; } +static unsigned long long read_imm_64(m68k_info *info) { const unsigned long long value = peek_imm_64(info); (info)->pc+=8; return value & 0xffffffffffffffff; } /* Fake a split interface */ #define get_ea_mode_str_8(instruction) get_ea_mode_str(instruction, 0) @@ -472,9 +472,9 @@ static void get_ea_mode_op(m68k_info *info, cs_m68k_op* op, uint32_t instruction op->type = M68K_OP_IMM; if (size == 1) - op->imm = read_imm_8(info) & 0xff; + op->imm = read_imm_8(info); else if (size == 2) - op->imm = read_imm_16(info) & 0xffff; + op->imm = read_imm_16(info); else if (size == 4) op->imm = read_imm_32(info); else @@ -604,7 +604,7 @@ static void build_imm_ea(m68k_info *info, int opcode, uint8_t size, int imm) op0->type = M68K_OP_IMM; op0->address_mode = M68K_AM_IMMEDIATE; - op0->imm = imm; + op0->imm = imm & info->address_mask; get_ea_mode_op(info, op1, info->ir, size); } @@ -878,7 +878,8 @@ static uint16_t reverse_bits(uint32_t v) s--; } - return r <<= s; // shift when v's highest bits are zero + r <<= s; // shift when v's highest bits are zero + return r; } static uint8_t reverse_bits_8(uint32_t v) @@ -892,7 +893,8 @@ static uint8_t reverse_bits_8(uint32_t v) s--; } - return r <<= s; // shift when v's highest bits are zero + r <<= s; // shift when v's highest bits are zero + return r; } diff --git a/arch/M68K/M68KInstPrinter.c b/arch/M68K/M68KInstPrinter.c index f6805ed974..1268a46f56 100644 --- a/arch/M68K/M68KInstPrinter.c +++ b/arch/M68K/M68KInstPrinter.c @@ -1,17 +1,6 @@ /* Capstone Disassembly Engine */ /* M68K Backend by Daniel Collin 2015-2016 */ -#ifdef _MSC_VER -// Disable security warnings for strcat & sprintf -#ifndef _CRT_SECURE_NO_WARNINGS -#define _CRT_SECURE_NO_WARNINGS -#endif - -//Banned API Usage : strcat / sprintf is a Banned API as listed in dontuse.h for -//security purposes. -#pragma warning(disable:28719) -#endif - #include // DEBUG #include #include @@ -78,7 +67,7 @@ static const char* getRegName(m68k_reg reg) return s_reg_names[(int)reg]; } -static void printRegbitsRange(char* buffer, uint32_t data, const char* prefix) +static void printRegbitsRange(char* buffer, size_t buf_len, uint32_t data, const char* prefix) { unsigned int first = 0; unsigned int run_length = 0; @@ -95,11 +84,11 @@ static void printRegbitsRange(char* buffer, uint32_t data, const char* prefix) } if (buffer[0] != 0) - strcat(buffer, "/"); + strncat(buffer, "/", buf_len - 1); - sprintf(buffer + strlen(buffer), "%s%d", prefix, first); + snprintf(buffer + strlen(buffer), buf_len, "%s%d", prefix, first); if (run_length > 0) - sprintf(buffer + strlen(buffer), "-%s%d", prefix, first + run_length); + snprintf(buffer + strlen(buffer), buf_len, "-%s%d", prefix, first + run_length); } } } @@ -116,9 +105,9 @@ static void registerBits(SStream* O, const cs_m68k_op* op) return; } - printRegbitsRange(buffer, data & 0xff, "d"); - printRegbitsRange(buffer, (data >> 8) & 0xff, "a"); - printRegbitsRange(buffer, (data >> 16) & 0xff, "fp"); + printRegbitsRange(buffer, sizeof(buffer), data & 0xff, "d"); + printRegbitsRange(buffer, sizeof(buffer), (data >> 8) & 0xff, "a"); + printRegbitsRange(buffer, sizeof(buffer), (data >> 16) & 0xff, "fp"); SStream_concat(O, "%s", buffer); } @@ -386,3 +375,24 @@ const char *M68K_group_name(csh handle, unsigned int id) #endif } +#ifndef CAPSTONE_DIET +void M68K_reg_access(const cs_insn *insn, + cs_regs regs_read, uint8_t *regs_read_count, + cs_regs regs_write, uint8_t *regs_write_count) +{ + uint8_t read_count, write_count; + + read_count = insn->detail->regs_read_count; + write_count = insn->detail->regs_write_count; + + // implicit registers + memcpy(regs_read, insn->detail->regs_read, + read_count * sizeof(insn->detail->regs_read[0])); + memcpy(regs_write, insn->detail->regs_write, + write_count * sizeof(insn->detail->regs_write[0])); + + *regs_read_count = read_count; + *regs_write_count = write_count; +} +#endif + diff --git a/arch/M68K/M68KInstPrinter.h b/arch/M68K/M68KInstPrinter.h index 45841ed2d7..8b9ed1b623 100644 --- a/arch/M68K/M68KInstPrinter.h +++ b/arch/M68K/M68KInstPrinter.h @@ -17,5 +17,10 @@ void M68K_get_insn_id(cs_struct* h, cs_insn* insn, unsigned int id); const char *M68K_insn_name(csh handle, unsigned int id); const char* M68K_group_name(csh handle, unsigned int id); void M68K_post_printer(csh handle, cs_insn* flat_insn, char* insn_asm, MCInst* mci); +#ifndef CAPSTONE_DIET +void M68K_reg_access(const cs_insn *insn, + cs_regs regs_read, uint8_t *regs_read_count, + cs_regs regs_write, uint8_t *regs_write_count); +#endif #endif diff --git a/arch/M68K/M68KModule.c b/arch/M68K/M68KModule.c index 03e73f7b9d..799b2c4c09 100644 --- a/arch/M68K/M68KModule.c +++ b/arch/M68K/M68KModule.c @@ -13,7 +13,7 @@ cs_err M68K_global_init(cs_struct *ud) { m68k_info *info; - info = cs_mem_malloc(sizeof(m68k_info)); + info = cs_mem_calloc(sizeof(m68k_info), 1); if (!info) { return CS_ERR_MEM; } @@ -29,6 +29,9 @@ cs_err M68K_global_init(cs_struct *ud) ud->insn_id = M68K_get_insn_id; ud->insn_name = M68K_insn_name; ud->group_name = M68K_group_name; +#ifndef CAPSTONE_DIET + ud->reg_access = M68K_reg_access; +#endif return CS_ERR_OK; } diff --git a/arch/RISCV/RISCVModule.c b/arch/RISCV/RISCVModule.c index cefd4b11a6..62b2b3b982 100644 --- a/arch/RISCV/RISCVModule.c +++ b/arch/RISCV/RISCVModule.c @@ -33,8 +33,11 @@ cs_err RISCV_global_init(cs_struct * ud) cs_err RISCV_option(cs_struct * handle, cs_opt_type type, size_t value) { - if (type == CS_OPT_SYNTAX) + if (type == CS_OPT_SYNTAX) { handle->syntax = (int)value; + } else if (type == CS_OPT_MODE) { + handle->mode = (cs_mode)value; + } return CS_ERR_OK; } diff --git a/arch/TriCore/TriCoreModule.c b/arch/TriCore/TriCoreModule.c index c97d36b2ec..e28ae3a11e 100644 --- a/arch/TriCore/TriCoreModule.c +++ b/arch/TriCore/TriCoreModule.c @@ -35,8 +35,11 @@ cs_err TRICORE_global_init(cs_struct *ud) cs_err TRICORE_option(cs_struct *handle, cs_opt_type type, size_t value) { - if (type == CS_OPT_SYNTAX) + if (type == CS_OPT_SYNTAX) { handle->syntax = (int)value; + } else if (type == CS_OPT_MODE) { + handle->mode = (cs_mode)value; + } return CS_ERR_OK; } diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c index 3106dc74a0..6bff62062f 100644 --- a/arch/X86/X86ATTInstPrinter.c +++ b/arch/X86/X86ATTInstPrinter.c @@ -288,9 +288,7 @@ static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64 // initialize access memset(access, 0, CS_X86_MAXIMUM_OPERAND_SIZE * sizeof(access[0])); - if (!arr) { - access[0] = 0; return; } @@ -302,7 +300,7 @@ static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64 // copy in reverse order this access array from Intel syntax -> AT&T syntax count--; - for(i = 0; i <= count; i++) { + for(i = 0; i <= count && ((count - i) < CS_X86_MAXIMUM_OPERAND_SIZE) && i < CS_X86_MAXIMUM_OPERAND_SIZE; i++) { if (arr[count - i] != CS_AC_IGNORE) access[i] = arr[count - i]; else diff --git a/bindings/Makefile b/bindings/Makefile deleted file mode 100644 index 85e5705001..0000000000 --- a/bindings/Makefile +++ /dev/null @@ -1,150 +0,0 @@ -TMPDIR = /tmp/capstone_test - -DIFF = diff -u -w - -TEST_BASIC = $(TMPDIR)/test_basic -TEST_DETAIL = $(TMPDIR)/test_detail -TEST_CUSTOMIZED_MNEM = $(TMPDIR)/test_customized_mnem -TEST_ARM = $(TMPDIR)/test_arm -TEST_ARM64 = $(TMPDIR)/test_aarch64 -TEST_M68K = $(TMPDIR)/test_m68k -TEST_MIPS = $(TMPDIR)/test_mips -TEST_MOS65XX = $(TMPDIR)/test_mos65xx -TEST_PPC = $(TMPDIR)/test_ppc -TEST_SPARC = $(TMPDIR)/test_sparc -TEST_SYSZ = $(TMPDIR)/test_systemz -TEST_X86 = $(TMPDIR)/test_x86 -TEST_XCORE = $(TMPDIR)/test_xcore -TEST_WASM = $(TMPDIR)/test_wasm -TEST_BPF = $(TMPDIR)/test_bpf -TEST_RISCV = $(TMPDIR)/test_riscv -TEST_EVM = $(TMPDIR)/test_evm -TEST_M680X = $(TMPDIR)/test_m680x -TEST_TRICORE = $(TMPDIR)/test_tricore -TEST_SH = $(TMPDIR)/test_sh -TEST_TMS320C64X = $(TMPDIR)/test_tms320c64x -TEST_ALPHA = $(TMPDIR)/test_alpha -TEST_HPPA = $(TMPDIR)/test_hppa - -PYTHON3 ?= python3 - -BUILD_TESTS ?= yes - -.PHONY: all expected python java ocaml - -all: - cd python && $(MAKE) gen_const - cd java && $(MAKE) gen_const - cd ocaml && $(MAKE) gen_const - -tests: expected python #java oclma ruby - -test_java: expected java -test_python: expected python - -expected: - if [ "$(BUILD_TESTS)" = "yes" ]; then cd ../tests && $(MAKE); fi - mkdir -p $(TMPDIR) - ../tests/test_basic > $(TEST_BASIC)_e - ../tests/test_detail > $(TEST_DETAIL)_e - ../tests/test_customized_mnem > $(TEST_CUSTOMIZED_MNEM)_e - ../tests/test_arm > $(TEST_ARM)_e - ../tests/test_aarch64 > $(TEST_ARM64)_e - ../tests/test_m68k > $(TEST_M68K)_e - ../tests/test_mips > $(TEST_MIPS)_e - ../tests/test_mos65xx > $(TEST_MOS65XX)_e - ../tests/test_ppc > $(TEST_PPC)_e - ../tests/test_sparc > $(TEST_SPARC)_e - ../tests/test_systemz > $(TEST_SYSZ)_e - ../tests/test_x86 > $(TEST_X86)_e - ../tests/test_xcore > $(TEST_XCORE)_e - ../tests/test_wasm > $(TEST_WASM)_e - ../tests/test_bpf > $(TEST_BPF)_e - ../tests/test_riscv > $(TEST_RISCV)_e - ../tests/test_evm > $(TEST_EVM)_e - ../tests/test_m680x > $(TEST_M680X)_e - ../tests/test_sh > $(TEST_SH)_e - ../tests/test_tricore > $(TEST_TRICORE)_e - ../tests/test_tms320c64x > $(TEST_TMS320C64X)_e - ../tests/test_alpha > $(TEST_ALPHA)_e - ../tests/test_hppa > $(TEST_HPPA)_e - -python: FORCE - cd python && $(MAKE) - $(PYTHON3) python/test_basic.py > $(TEST_BASIC)_o - $(PYTHON3) python/test_detail.py > $(TEST_DETAIL)_o - $(PYTHON3) python/test_customized_mnem.py > $(TEST_CUSTOMIZED_MNEM)_o - $(PYTHON3) python/test_arm.py > $(TEST_ARM)_o - $(PYTHON3) python/test_aarch64.py > $(TEST_ARM64)_o - $(PYTHON3) python/test_m68k.py > $(TEST_M68K)_o - $(PYTHON3) python/test_mips.py > $(TEST_MIPS)_o - $(PYTHON3) python/test_mos65xx.py > $(TEST_MOS65XX)_o - $(PYTHON3) python/test_ppc.py > $(TEST_PPC)_o - $(PYTHON3) python/test_sparc.py > $(TEST_SPARC)_o - $(PYTHON3) python/test_systemz.py > $(TEST_SYSZ)_o - $(PYTHON3) python/test_x86.py > $(TEST_X86)_o - $(PYTHON3) python/test_xcore.py > $(TEST_XCORE)_o - $(PYTHON3) python/test_wasm.py > $(TEST_WASM)_o - $(PYTHON3) python/test_bpf.py > $(TEST_BPF)_o - $(PYTHON3) python/test_riscv.py > $(TEST_RISCV)_o - $(PYTHON3) python/test_evm.py > $(TEST_EVM)_o - $(PYTHON3) python/test_m680x.py > $(TEST_M680X)_o - $(PYTHON3) python/test_sh.py > $(TEST_SH)_o - $(PYTHON3) python/test_tricore.py > $(TEST_TRICORE)_o - $(PYTHON3) python/test_tms320c64x.py > $(TEST_TMS320C64X)_o - $(PYTHON3) python/test_alpha.py > $(TEST_ALPHA)_o - $(PYTHON3) python/test_hppa.py > $(TEST_HPPA)_o - $(MAKE) test_diff - -java: FORCE - cd java && $(MAKE) - cd java && ./run.sh > $(TEST_BASIC)_o - cd java && ./run.sh arm > $(TEST_ARM)_o - cd java && ./run.sh arm64 > $(TEST_ARM64)_o - cd java && ./run.sh mips > $(TEST_MIPS)_o - cd java && ./run.sh ppc > $(TEST_PPC)_o - cd java && ./run.sh sparc > $(TEST_SPARC)_o - cd java && ./run.sh systemz > $(TEST_SYSZ)_o - cd java && ./run.sh x86 > $(TEST_X86)_o - cd java && ./run.sh xcore > $(TEST_XCORE)_o - $(MAKE) test_diff - -ocaml: FORCE - -test_diff: FORCE - $(DIFF) $(TEST_BASIC)_e $(TEST_BASIC)_o - $(DIFF) $(TEST_DETAIL)_e $(TEST_DETAIL)_o - $(DIFF) $(TEST_CUSTOMIZED_MNEM)_e $(TEST_CUSTOMIZED_MNEM)_o - $(DIFF) $(TEST_ARM)_e $(TEST_ARM)_o - $(DIFF) $(TEST_ARM64)_e $(TEST_ARM64)_o - $(DIFF) $(TEST_M68K)_e $(TEST_M68K)_o - $(DIFF) $(TEST_MIPS)_e $(TEST_MIPS)_o - $(DIFF) $(TEST_MOS65XX)_e $(TEST_MOS65XX)_o - $(DIFF) $(TEST_PPC)_e $(TEST_PPC)_o - $(DIFF) $(TEST_SPARC)_e $(TEST_SPARC)_o - $(DIFF) $(TEST_SYSZ)_e $(TEST_SYSZ)_o - $(DIFF) $(TEST_X86)_e $(TEST_X86)_o - $(DIFF) $(TEST_XCORE)_e $(TEST_XCORE)_o - $(DIFF) $(TEST_WASM)_e $(TEST_WASM)_o - $(DIFF) $(TEST_BPF)_e $(TEST_BPF)_o - $(DIFF) $(TEST_RISCV)_e $(TEST_RISCV)_o - $(DIFF) $(TEST_EVM)_e $(TEST_EVM)_o - $(DIFF) $(TEST_M680X)_e $(TEST_M680X)_o - $(DIFF) $(TEST_SH)_e $(TEST_SH)_o - $(DIFF) $(TEST_TRICORE)_e $(TEST_TRICORE)_o - $(DIFF) $(TEST_TMS320C64X)_e $(TEST_TMS320C64X)_o - $(DIFF) $(TEST_ALPHA)_e $(TEST_ALPHA)_o - $(DIFF) $(TEST_HPPA)_e $(TEST_HPPA)_o - -clean: - rm -rf $(TMPDIR) - cd java && $(MAKE) clean - cd python && $(MAKE) clean - cd ocaml && $(MAKE) clean - -check: - make -C ocaml check - make -C python check - make -C java check - -FORCE: diff --git a/bindings/const_generator.py b/bindings/const_generator.py index 1f4ec14f62..e164e62a93 100644 --- a/bindings/const_generator.py +++ b/bindings/const_generator.py @@ -1,11 +1,12 @@ # Capstone Disassembler Engine # By Dang Hoang Vu, 2013 from __future__ import print_function -import sys, re +import sys +import re INCL_DIR = '../include/capstone/' -include = [ 'arm.h', 'aarch64.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'sh.h', 'tricore.h', 'alpha.h', 'hppa.h' ] +include = [ 'arm.h', 'aarch64.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'sh.h', 'tricore.h', 'alpha.h', 'hppa.h', 'loongarch.h' ] template = { 'java': { @@ -56,6 +57,7 @@ 'tricore.h': ['TRICORE', 'TriCore'], 'alpha.h': ['ALPHA', 'Alpha'], 'hppa.h': 'hppa', + 'loongarch.h': 'loongarch', 'comment_open': '#', 'comment_close': '', }, @@ -80,81 +82,6 @@ 'comment_open': '(*', 'comment_close': ' *)', }, - # 'swift': { - # 'header': "// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT (%s)\n\n", - # 'footer': "", - # 'enum_doc': '/// %s\n', - # 'enum_header': 'public enum %s: %s {\n', - # 'enum_default_type': 'UInt32', - # 'enum_types': { - # 'UInt16': r'^\w+Reg$', - # 'UInt8': r'^\w+Grp$' - # }, - # 'option_set_header': 'public struct %s: OptionSet {\n public typealias RawValue = %s\n public let rawValue: RawValue\n public init(rawValue: RawValue) { self.rawValue = rawValue }\n', - # 'option_sets': { - # 'X86Eflags': 'UInt64', - # 'X86FpuFlags': 'UInt64', - # 'SparcHint': 'UInt32', - # 'M680xIdx': 'UInt8', - # 'M680xOpFlags': 'UInt8', - # }, - # 'rename': { - # r'^M680X_(\w+_OP_IN_MNEM)$': r'M680X_OP_FLAGS_\1', - # }, - # 'option_format': ' public static let {option} = {type}(rawValue: {value})\n', - # 'enum_extra_options': { - # # swift enum != OptionSet, so options must be specified - # 'ArmSysreg': { - # 'spsrCx': 'spsrC + spsrX', - # 'spsrCs': 'spsrC + spsrS', - # 'spsrXs': 'spsrX + spsrS', - # 'spsrCxs': 'spsrC + spsrX + spsrS', - # 'spsrCf': 'spsrC + spsrF', - # 'spsrXf': 'spsrX + spsrF', - # 'spsrCxf': 'spsrC + spsrX + spsrF', - # 'spsrSf': 'spsrS + spsrF', - # 'spsrCsf': 'spsrC + spsrS + spsrF', - # 'spsrXsf': 'spsrX + spsrS + spsrF', - # 'spsrCxsf': 'spsrC + spsrX + spsrS + spsrF', - # 'cpsrCx': 'cpsrC + cpsrX', - # 'cpsrCs': 'cpsrC + cpsrS', - # 'cpsrXs': 'cpsrX + cpsrS', - # 'cpsrCxs': 'cpsrC + cpsrX + cpsrS', - # 'cpsrCf': 'cpsrC + cpsrF', - # 'cpsrXf': 'cpsrX + cpsrF', - # 'cpsrCxf': 'cpsrC + cpsrX + cpsrF', - # 'cpsrSf': 'cpsrS + cpsrF', - # 'cpsrCsf': 'cpsrC + cpsrS + cpsrF', - # 'cpsrXsf': 'cpsrX + cpsrS + cpsrF', - # 'cpsrCxsf': 'cpsrC + cpsrX + cpsrS + cpsrF', - # } - # }, - # 'enum_footer': '}\n\n', - # 'doc_line_format': ' /// %s\n', - # 'line_format': ' case %s = %s\n', - # 'dup_line_format': ' public static let %s = %s\n', - # 'out_file': './swift/Sources/Capstone/%sEnums.swift', - # 'reserved_words': [ - # 'break', 'class', 'for', 'false', 'in', 'init', 'return', 'true' - # ], - # 'reserved_word_format': '`%s`', - # # prefixes for constant filenames of all archs - case sensitive - # 'arm.h': 'Arm', - # 'arm64.h': 'Arm64', - # 'm68k.h': 'M68k', - # 'mips.h': 'Mips', - # 'x86.h': 'X86', - # 'ppc.h': 'Ppc', - # 'sparc.h': 'Sparc', - # 'systemz.h': 'Sysz', - # 'xcore.h': 'Xcore', - # 'tms320c64x.h': 'TMS320C64x', - # 'm680x.h': 'M680x', - # 'evm.h': 'Evm', - # 'mos65xx.h': 'Mos65xx', - # 'comment_open': '\t//', - # 'comment_close': '', - # }, } excluded_prefixes = { @@ -237,6 +164,11 @@ def gen(lang): elif line.startswith('}') or line.startswith('#'): doc_lines = [] pass + elif re.search(r"^(\s*typedef\s+)?enum", line): + # First new enum value should be 0. + # Because `rhs` is incremented later, it must be set to -1 here. + # Everything about this code is so broken -.- + rhs = "-1" if line == '' or line.startswith('//'): continue @@ -251,7 +183,7 @@ def gen(lang): xline.insert(1, '=') # insert an = so the expression below can parse it line = ' '.join(xline) - def is_with_prefix(x): + def has_special_arch_prefix(x): if target in excluded_prefixes and any(x.startswith(excl_pre) for excl_pre in excluded_prefixes[target]): return False if prefixs: @@ -259,7 +191,7 @@ def is_with_prefix(x): else: return x.startswith(prefix.upper()) - if not is_with_prefix(line): + if not has_special_arch_prefix(line): continue tmp = line.strip().split(',') @@ -271,7 +203,7 @@ def is_with_prefix(x): t = re.sub(r'\((\d+)ULL << (\d+)\)', r'\1 << \2', t) # (1ULL<<1) to 1 << 1 f = re.split('\s+', t) - if not is_with_prefix(f[0]): + if not has_special_arch_prefix(f[0]): continue if len(f) > 1 and f[1] not in ('//', '///<', '='): diff --git a/bindings/python/.gitignore b/bindings/python/.gitignore index 61178e6a1b..5ed7ca830b 100644 --- a/bindings/python/.gitignore +++ b/bindings/python/.gitignore @@ -1,6 +1,5 @@ MANIFEST dist/ -src/ capstone/lib capstone/include pyx/lib diff --git a/bindings/python/BUILDING.txt b/bindings/python/BUILDING.md similarity index 58% rename from bindings/python/BUILDING.txt rename to bindings/python/BUILDING.md index 78fcb0ded9..9b6a1d680e 100644 --- a/bindings/python/BUILDING.txt +++ b/bindings/python/BUILDING.md @@ -4,17 +4,12 @@ 1. To install Capstone and the Python bindings on *nix, run the command below: - $ sudo make install - - To control the install destination, set the DESTDIR environment variable. +``` +pip install bindings/python/ +``` 2. The tests directory contains some test code to show how to use the Capstone API. -- test_basic.py - This code shows the most simple form of API where we only want to get basic - information out of disassembled instruction, such as address, mnemonic and - operand string. - - test_lite.py Similarly to test_basic.py, but this code shows how to use disasm_lite(), a lighter method to disassemble binary. Unlike disasm() API (used by test_basic.py), which returns @@ -23,12 +18,3 @@ The main reason for using this API is better performance: disasm_lite() is at least 20% faster than disasm(). Memory usage is also less. So if you just need basic information out of disassembler, use disasm_lite() instead of disasm(). - -- test_detail.py: - This code shows how to access to architecture-neutral information in disassembled - instructions, such as implicit registers read/written, or groups of instructions - that this instruction belong to. - -- test_.py - These code show how to access architecture-specific information for each - architecture. diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py index 75ad68083f..f70c6e96ea 100755 --- a/bindings/python/capstone/__init__.py +++ b/bindings/python/capstone/__init__.py @@ -40,6 +40,7 @@ 'CS_ARCH_TRICORE', 'CS_ARCH_ALPHA', 'CS_ARCH_HPPA', + 'CS_ARCH_LOONGARCH', 'CS_ARCH_ALL', 'CS_MODE_LITTLE_ENDIAN', @@ -107,6 +108,8 @@ 'CS_MODE_HPPA_11', 'CS_MODE_HPPA_20', 'CS_MODE_HPPA_20W', + 'CS_MODE_LOONGARCH32', + 'CS_MODE_LOONGARCH64', 'CS_OPT_SYNTAX', 'CS_OPT_SYNTAX_DEFAULT', @@ -225,6 +228,7 @@ CS_ARCH_TRICORE = 17 CS_ARCH_ALPHA = 18 CS_ARCH_HPPA = 19 +CS_ARCH_LOONGARCH = 20 CS_ARCH_MAX = 20 CS_ARCH_ALL = 0xFFFF @@ -294,6 +298,8 @@ CS_MODE_HPPA_11 = 1 << 1 # HPPA 1.1 CS_MODE_HPPA_20 = 1 << 2 # HPPA 2.0 CS_MODE_HPPA_20W = CS_MODE_HPPA_20 | (1 << 3) # HPPA 2.0 wide +CS_MODE_LOONGARCH32 = 1 << 0 +CS_MODE_LOONGARCH64 = 1 << 1 # Capstone option type CS_OPT_INVALID = 0 # No option specified @@ -347,16 +353,18 @@ CS_AC_INVALID = 0 # Invalid/uninitialized access type. CS_AC_READ = (1 << 0) # Operand that is read from. CS_AC_WRITE = (1 << 1) # Operand that is written to. -CS_AC_READ_WRITE = (2) +CS_AC_READ_WRITE = CS_AC_READ | CS_AC_WRITE # Capstone syntax value -CS_OPT_SYNTAX_DEFAULT = 1 << 1 # Default assembly syntax of all platforms (CS_OPT_SYNTAX) -CS_OPT_SYNTAX_INTEL = 1 << 2 # Intel X86 asm syntax - default syntax on X86 (CS_OPT_SYNTAX, CS_ARCH_X86) -CS_OPT_SYNTAX_ATT = 1 << 3 # ATT asm syntax (CS_OPT_SYNTAX, CS_ARCH_X86) -CS_OPT_SYNTAX_NOREGNAME = 1 << 4 # Asm syntax prints register name with only number - (CS_OPT_SYNTAX, CS_ARCH_PPC, CS_ARCH_ARM) -CS_OPT_SYNTAX_MASM = 1 << 5 # MASM syntax (CS_OPT_SYNTAX, CS_ARCH_X86) -CS_OPT_SYNTAX_MOTOROLA = 1 << 6 # MOS65XX use $ as hex prefix -CS_OPT_SYNTAX_CS_REG_ALIAS = 1 << 7 # Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.) +CS_OPT_SYNTAX_DEFAULT = (1 << 1) # Default assembly syntax of all platforms (CS_OPT_SYNTAX) +CS_OPT_SYNTAX_INTEL = (1 << 2) # Intel X86 asm syntax - default syntax on X86 (CS_OPT_SYNTAX, CS_ARCH_X86) +CS_OPT_SYNTAX_ATT = (1 << 3) # ATT asm syntax (CS_OPT_SYNTAX, CS_ARCH_X86) +CS_OPT_SYNTAX_NOREGNAME = (1 << 4) # Asm syntax prints register name with only number - (CS_OPT_SYNTAX, CS_ARCH_PPC, CS_ARCH_ARM) +CS_OPT_SYNTAX_MASM = (1 << 5) # MASM syntax (CS_OPT_SYNTAX, CS_ARCH_X86) +CS_OPT_SYNTAX_MOTOROLA = (1 << 6) # MOS65XX use $ as hex prefix +CS_OPT_SYNTAX_CS_REG_ALIAS = (1 << 7) # Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.) +CS_OPT_SYNTAX_PERCENT = (1 << 8) # Prints the % in front of PPC registers. +CS_OPT_DETAIL_REAL = (1 << 1) # If enabled, always sets the real instruction detail.Even if the instruction is an alias. # Capstone error type CS_ERR_OK = 0 # No error: everything was fine @@ -460,7 +468,7 @@ def copy_ctypes_list(src): return [copy_ctypes(n) for n in src] # Weird import placement because these modules are needed by the below code but need the above functions -from . import arm, aarch64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, riscv, sh, tricore, alpha, hppa +from . import arm, aarch64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, riscv, sh, tricore, alpha, hppa, loongarch class _cs_arch(ctypes.Union): _fields_ = ( @@ -484,6 +492,7 @@ class _cs_arch(ctypes.Union): ('tricore', tricore.CsTriCore), ('alpha', alpha.CsAlpha), ('hppa', hppa.CsHPPA), + ('loongarch', loongarch.CsLoongArch), ) class _cs_detail(ctypes.Structure): @@ -695,6 +704,21 @@ def address(self): def size(self): return self._raw.size + # return instruction's is_alias flag + @property + def is_alias(self): + return self._raw.is_alias + + # return instruction's alias_id + @property + def alias_id(self): + return self._raw.alias_id + + # return instruction's flag if it uses alias details + @property + def uses_alias_details(self): + return self._raw.usesAliasDetails + # return instruction's machine bytes (which should have @size bytes). @property def bytes(self): @@ -802,7 +826,7 @@ def __gen_detail(self): elif arch == CS_ARCH_MIPS: self.operands = mips.get_arch_info(self._raw.detail.contents.arch.mips) elif arch == CS_ARCH_PPC: - (self.bc, self.update_cr0, self.operands) = \ + (self.bc, self.update_cr0, self.format, self.operands) = \ ppc.get_arch_info(self._raw.detail.contents.arch.ppc) elif arch == CS_ARCH_SPARC: (self.cc, self.hint, self.operands) = sparc.get_arch_info(self._raw.detail.contents.arch.sparc) @@ -832,6 +856,8 @@ def __gen_detail(self): (self.operands) = alpha.get_arch_info(self._raw.detail.contents.arch.alpha) elif arch == CS_ARCH_HPPA: (self.operands) = hppa.get_arch_info(self._raw.detail.contents.arch.hppa) + elif arch == CS_ARCH_LOONGARCH: + (self.format, self.operands) = loongarch.get_arch_info(self._raw.detail.contents.arch.loongarch) def __getattr__(self, name): @@ -840,14 +866,14 @@ def __getattr__(self, name): attr = object.__getattribute__ if not attr(self, '_cs')._detail: - raise AttributeError(name) + raise AttributeError(f"'CsInsn' has no attribute '{name}'") _dict = attr(self, '__dict__') if 'operands' not in _dict: self.__gen_detail() if name not in _dict: if self._raw.id == 0: raise CsError(CS_ERR_SKIPDATA) - raise AttributeError(name) + raise AttributeError(f"'CsInsn' has no attribute '{name}'") return _dict[name] # get the last error code @@ -1021,9 +1047,16 @@ def __del__(self): except: # _cs might be pulled from under our feet pass - - # def option(self, opt_type, opt_value): - # return _cs.cs_option(self.csh, opt_type, opt_value) + def option(self, opt_type, opt_value): + status = _cs.cs_option(self.csh, opt_type, opt_value) + if status != CS_ERR_OK: + raise CsError(status) + if opt_type == CS_OPT_DETAIL: + self._detail = opt_value == CS_OPT_ON + elif opt_type == CS_OPT_SKIPDATA: + self._skipdata = opt_value == CS_OPT_ON + elif opt_type == CS_OPT_UNSIGNED: + self._imm_unsigned = opt_value == CS_OPT_ON # is this a diet engine? @@ -1321,7 +1354,7 @@ def debug(): "m680x": CS_ARCH_M680X, 'evm': CS_ARCH_EVM, 'mos65xx': CS_ARCH_MOS65XX, 'bpf': CS_ARCH_BPF, 'riscv': CS_ARCH_RISCV, 'tricore': CS_ARCH_TRICORE, 'wasm': CS_ARCH_WASM, 'sh': CS_ARCH_SH, 'alpha': CS_ARCH_ALPHA, - 'hppa': CS_ARCH_HPPA + 'hppa': CS_ARCH_HPPA, 'loongarch': CS_ARCH_LOONGARCH } all_archs = "" diff --git a/bindings/python/capstone/aarch64.py b/bindings/python/capstone/aarch64.py index b5d4a87bd3..bcceb8a959 100644 --- a/bindings/python/capstone/aarch64.py +++ b/bindings/python/capstone/aarch64.py @@ -14,7 +14,7 @@ class AArch64OpMem(ctypes.Structure): class AArch64ImmRange(ctypes.Structure): _fields_ = ( - ('imm', ctypes.c_int8), + ('first', ctypes.c_int8), ('offset', ctypes.c_int8), ) diff --git a/bindings/python/capstone/aarch64_const.py b/bindings/python/capstone/aarch64_const.py index 8ce35150eb..4831adb6d9 100644 --- a/bindings/python/capstone/aarch64_const.py +++ b/bindings/python/capstone/aarch64_const.py @@ -1615,7 +1615,7 @@ AARCH64_SYSREG_ZCR_EL3 = 0xf090 AARCH64_SYSREG_ENDING = UINT16_MAX AARCH64_TSB_CSYNC = 0x0 -AArch64_TSB_ENDING = 1 +AARCH64_TSB_ENDING = 1 AARCH64_OP_INVALID = CS_OP_INVALID AARCH64_OP_REG = CS_OP_REG AARCH64_OP_IMM = CS_OP_IMM @@ -2358,1787 +2358,1790 @@ AARCH64_REG_IP1 = AARCH64_REG_X17 AARCH64_REG_X29 = AARCH64_REG_FP AARCH64_REG_X30 = AARCH64_REG_LR -AARCH64_SME_MATRIX_TILE = 701 -AARCH64_SME_MATRIX_TILE_LIST = 702 -AARCH64_SME_MATRIX_SLICE_REG = 703 -AARCH64_SME_MATRIX_SLICE_OFF = 704 -AARCH64_SME_MATRIX_SLICE_OFF_RANGE = 705 -AARCH64_SME_OP_INVALID = 706 -AARCH64_SME_OP_TILE = 707 -AARCH64_SME_OP_TILE_VEC = 708 -AARCH64_INS_INVALID = 709 -AARCH64_INS_ABS = 710 -AARCH64_INS_ADCLB = 711 -AARCH64_INS_ADCLT = 712 -AARCH64_INS_ADCS = 713 -AARCH64_INS_ADC = 714 -AARCH64_INS_ADDG = 715 -AARCH64_INS_ADDHA = 716 -AARCH64_INS_ADDHNB = 717 -AARCH64_INS_ADDHNT = 718 -AARCH64_INS_ADDHN = 719 -AARCH64_INS_ADDHN2 = 720 -AARCH64_INS_ADDPL = 721 -AARCH64_INS_ADDPT = 722 -AARCH64_INS_ADDP = 723 -AARCH64_INS_ADDQV = 724 -AARCH64_INS_ADDSPL = 725 -AARCH64_INS_ADDSVL = 726 -AARCH64_INS_ADDS = 727 -AARCH64_INS_ADDVA = 728 -AARCH64_INS_ADDVL = 729 -AARCH64_INS_ADDV = 730 -AARCH64_INS_ADD = 731 -AARCH64_INS_ADR = 732 -AARCH64_INS_ADRP = 733 -AARCH64_INS_AESD = 734 -AARCH64_INS_AESE = 735 -AARCH64_INS_AESIMC = 736 -AARCH64_INS_AESMC = 737 -AARCH64_INS_ANDQV = 738 -AARCH64_INS_ANDS = 739 -AARCH64_INS_ANDV = 740 -AARCH64_INS_AND = 741 -AARCH64_INS_ASRD = 742 -AARCH64_INS_ASRR = 743 -AARCH64_INS_ASR = 744 -AARCH64_INS_AUTDA = 745 -AARCH64_INS_AUTDB = 746 -AARCH64_INS_AUTDZA = 747 -AARCH64_INS_AUTDZB = 748 -AARCH64_INS_AUTIA = 749 -AARCH64_INS_HINT = 750 -AARCH64_INS_AUTIA171615 = 751 -AARCH64_INS_AUTIASPPC = 752 -AARCH64_INS_AUTIB = 753 -AARCH64_INS_AUTIB171615 = 754 -AARCH64_INS_AUTIBSPPC = 755 -AARCH64_INS_AUTIZA = 756 -AARCH64_INS_AUTIZB = 757 -AARCH64_INS_AXFLAG = 758 -AARCH64_INS_B = 759 -AARCH64_INS_BCAX = 760 -AARCH64_INS_BC = 761 -AARCH64_INS_BDEP = 762 -AARCH64_INS_BEXT = 763 -AARCH64_INS_BFDOT = 764 -AARCH64_INS_BF1CVTL2 = 765 -AARCH64_INS_BF1CVTLT = 766 -AARCH64_INS_BF1CVTL = 767 -AARCH64_INS_BF1CVT = 768 -AARCH64_INS_BF2CVTL2 = 769 -AARCH64_INS_BF2CVTLT = 770 -AARCH64_INS_BF2CVTL = 771 -AARCH64_INS_BF2CVT = 772 -AARCH64_INS_BFADD = 773 -AARCH64_INS_BFCLAMP = 774 -AARCH64_INS_BFCVT = 775 -AARCH64_INS_BFCVTN = 776 -AARCH64_INS_BFCVTN2 = 777 -AARCH64_INS_BFCVTNT = 778 -AARCH64_INS_BFMAXNM = 779 -AARCH64_INS_BFMAX = 780 -AARCH64_INS_BFMINNM = 781 -AARCH64_INS_BFMIN = 782 -AARCH64_INS_BFMLALB = 783 -AARCH64_INS_BFMLALT = 784 -AARCH64_INS_BFMLAL = 785 -AARCH64_INS_BFMLA = 786 -AARCH64_INS_BFMLSLB = 787 -AARCH64_INS_BFMLSLT = 788 -AARCH64_INS_BFMLSL = 789 -AARCH64_INS_BFMLS = 790 -AARCH64_INS_BFMMLA = 791 -AARCH64_INS_BFMOPA = 792 -AARCH64_INS_BFMOPS = 793 -AARCH64_INS_BFMUL = 794 -AARCH64_INS_BFM = 795 -AARCH64_INS_BFSUB = 796 -AARCH64_INS_BFVDOT = 797 -AARCH64_INS_BGRP = 798 -AARCH64_INS_BICS = 799 -AARCH64_INS_BIC = 800 -AARCH64_INS_BIF = 801 -AARCH64_INS_BIT = 802 -AARCH64_INS_BL = 803 -AARCH64_INS_BLR = 804 -AARCH64_INS_BLRAA = 805 -AARCH64_INS_BLRAAZ = 806 -AARCH64_INS_BLRAB = 807 -AARCH64_INS_BLRABZ = 808 -AARCH64_INS_BMOPA = 809 -AARCH64_INS_BMOPS = 810 -AARCH64_INS_BR = 811 -AARCH64_INS_BRAA = 812 -AARCH64_INS_BRAAZ = 813 -AARCH64_INS_BRAB = 814 -AARCH64_INS_BRABZ = 815 -AARCH64_INS_BRB = 816 -AARCH64_INS_BRK = 817 -AARCH64_INS_BRKAS = 818 -AARCH64_INS_BRKA = 819 -AARCH64_INS_BRKBS = 820 -AARCH64_INS_BRKB = 821 -AARCH64_INS_BRKNS = 822 -AARCH64_INS_BRKN = 823 -AARCH64_INS_BRKPAS = 824 -AARCH64_INS_BRKPA = 825 -AARCH64_INS_BRKPBS = 826 -AARCH64_INS_BRKPB = 827 -AARCH64_INS_BSL1N = 828 -AARCH64_INS_BSL2N = 829 -AARCH64_INS_BSL = 830 -AARCH64_INS_CADD = 831 -AARCH64_INS_CASAB = 832 -AARCH64_INS_CASAH = 833 -AARCH64_INS_CASALB = 834 -AARCH64_INS_CASALH = 835 -AARCH64_INS_CASAL = 836 -AARCH64_INS_CASA = 837 -AARCH64_INS_CASB = 838 -AARCH64_INS_CASH = 839 -AARCH64_INS_CASLB = 840 -AARCH64_INS_CASLH = 841 -AARCH64_INS_CASL = 842 -AARCH64_INS_CASPAL = 843 -AARCH64_INS_CASPA = 844 -AARCH64_INS_CASPL = 845 -AARCH64_INS_CASP = 846 -AARCH64_INS_CAS = 847 -AARCH64_INS_CBNZ = 848 -AARCH64_INS_CBZ = 849 -AARCH64_INS_CCMN = 850 -AARCH64_INS_CCMP = 851 -AARCH64_INS_CDOT = 852 -AARCH64_INS_CFINV = 853 -AARCH64_INS_CLASTA = 854 -AARCH64_INS_CLASTB = 855 -AARCH64_INS_CLREX = 856 -AARCH64_INS_CLS = 857 -AARCH64_INS_CLZ = 858 -AARCH64_INS_CMEQ = 859 -AARCH64_INS_CMGE = 860 -AARCH64_INS_CMGT = 861 -AARCH64_INS_CMHI = 862 -AARCH64_INS_CMHS = 863 -AARCH64_INS_CMLA = 864 -AARCH64_INS_CMLE = 865 -AARCH64_INS_CMLT = 866 -AARCH64_INS_CMPEQ = 867 -AARCH64_INS_CMPGE = 868 -AARCH64_INS_CMPGT = 869 -AARCH64_INS_CMPHI = 870 -AARCH64_INS_CMPHS = 871 -AARCH64_INS_CMPLE = 872 -AARCH64_INS_CMPLO = 873 -AARCH64_INS_CMPLS = 874 -AARCH64_INS_CMPLT = 875 -AARCH64_INS_CMPNE = 876 -AARCH64_INS_CMTST = 877 -AARCH64_INS_CNOT = 878 -AARCH64_INS_CNTB = 879 -AARCH64_INS_CNTD = 880 -AARCH64_INS_CNTH = 881 -AARCH64_INS_CNTP = 882 -AARCH64_INS_CNTW = 883 -AARCH64_INS_CNT = 884 -AARCH64_INS_COMPACT = 885 -AARCH64_INS_CPYE = 886 -AARCH64_INS_CPYEN = 887 -AARCH64_INS_CPYERN = 888 -AARCH64_INS_CPYERT = 889 -AARCH64_INS_CPYERTN = 890 -AARCH64_INS_CPYERTRN = 891 -AARCH64_INS_CPYERTWN = 892 -AARCH64_INS_CPYET = 893 -AARCH64_INS_CPYETN = 894 -AARCH64_INS_CPYETRN = 895 -AARCH64_INS_CPYETWN = 896 -AARCH64_INS_CPYEWN = 897 -AARCH64_INS_CPYEWT = 898 -AARCH64_INS_CPYEWTN = 899 -AARCH64_INS_CPYEWTRN = 900 -AARCH64_INS_CPYEWTWN = 901 -AARCH64_INS_CPYFE = 902 -AARCH64_INS_CPYFEN = 903 -AARCH64_INS_CPYFERN = 904 -AARCH64_INS_CPYFERT = 905 -AARCH64_INS_CPYFERTN = 906 -AARCH64_INS_CPYFERTRN = 907 -AARCH64_INS_CPYFERTWN = 908 -AARCH64_INS_CPYFET = 909 -AARCH64_INS_CPYFETN = 910 -AARCH64_INS_CPYFETRN = 911 -AARCH64_INS_CPYFETWN = 912 -AARCH64_INS_CPYFEWN = 913 -AARCH64_INS_CPYFEWT = 914 -AARCH64_INS_CPYFEWTN = 915 -AARCH64_INS_CPYFEWTRN = 916 -AARCH64_INS_CPYFEWTWN = 917 -AARCH64_INS_CPYFM = 918 -AARCH64_INS_CPYFMN = 919 -AARCH64_INS_CPYFMRN = 920 -AARCH64_INS_CPYFMRT = 921 -AARCH64_INS_CPYFMRTN = 922 -AARCH64_INS_CPYFMRTRN = 923 -AARCH64_INS_CPYFMRTWN = 924 -AARCH64_INS_CPYFMT = 925 -AARCH64_INS_CPYFMTN = 926 -AARCH64_INS_CPYFMTRN = 927 -AARCH64_INS_CPYFMTWN = 928 -AARCH64_INS_CPYFMWN = 929 -AARCH64_INS_CPYFMWT = 930 -AARCH64_INS_CPYFMWTN = 931 -AARCH64_INS_CPYFMWTRN = 932 -AARCH64_INS_CPYFMWTWN = 933 -AARCH64_INS_CPYFP = 934 -AARCH64_INS_CPYFPN = 935 -AARCH64_INS_CPYFPRN = 936 -AARCH64_INS_CPYFPRT = 937 -AARCH64_INS_CPYFPRTN = 938 -AARCH64_INS_CPYFPRTRN = 939 -AARCH64_INS_CPYFPRTWN = 940 -AARCH64_INS_CPYFPT = 941 -AARCH64_INS_CPYFPTN = 942 -AARCH64_INS_CPYFPTRN = 943 -AARCH64_INS_CPYFPTWN = 944 -AARCH64_INS_CPYFPWN = 945 -AARCH64_INS_CPYFPWT = 946 -AARCH64_INS_CPYFPWTN = 947 -AARCH64_INS_CPYFPWTRN = 948 -AARCH64_INS_CPYFPWTWN = 949 -AARCH64_INS_CPYM = 950 -AARCH64_INS_CPYMN = 951 -AARCH64_INS_CPYMRN = 952 -AARCH64_INS_CPYMRT = 953 -AARCH64_INS_CPYMRTN = 954 -AARCH64_INS_CPYMRTRN = 955 -AARCH64_INS_CPYMRTWN = 956 -AARCH64_INS_CPYMT = 957 -AARCH64_INS_CPYMTN = 958 -AARCH64_INS_CPYMTRN = 959 -AARCH64_INS_CPYMTWN = 960 -AARCH64_INS_CPYMWN = 961 -AARCH64_INS_CPYMWT = 962 -AARCH64_INS_CPYMWTN = 963 -AARCH64_INS_CPYMWTRN = 964 -AARCH64_INS_CPYMWTWN = 965 -AARCH64_INS_CPYP = 966 -AARCH64_INS_CPYPN = 967 -AARCH64_INS_CPYPRN = 968 -AARCH64_INS_CPYPRT = 969 -AARCH64_INS_CPYPRTN = 970 -AARCH64_INS_CPYPRTRN = 971 -AARCH64_INS_CPYPRTWN = 972 -AARCH64_INS_CPYPT = 973 -AARCH64_INS_CPYPTN = 974 -AARCH64_INS_CPYPTRN = 975 -AARCH64_INS_CPYPTWN = 976 -AARCH64_INS_CPYPWN = 977 -AARCH64_INS_CPYPWT = 978 -AARCH64_INS_CPYPWTN = 979 -AARCH64_INS_CPYPWTRN = 980 -AARCH64_INS_CPYPWTWN = 981 -AARCH64_INS_CPY = 982 -AARCH64_INS_CRC32B = 983 -AARCH64_INS_CRC32CB = 984 -AARCH64_INS_CRC32CH = 985 -AARCH64_INS_CRC32CW = 986 -AARCH64_INS_CRC32CX = 987 -AARCH64_INS_CRC32H = 988 -AARCH64_INS_CRC32W = 989 -AARCH64_INS_CRC32X = 990 -AARCH64_INS_CSEL = 991 -AARCH64_INS_CSINC = 992 -AARCH64_INS_CSINV = 993 -AARCH64_INS_CSNEG = 994 -AARCH64_INS_CTERMEQ = 995 -AARCH64_INS_CTERMNE = 996 -AARCH64_INS_CTZ = 997 -AARCH64_INS_DCPS1 = 998 -AARCH64_INS_DCPS2 = 999 -AARCH64_INS_DCPS3 = 1000 -AARCH64_INS_DECB = 1001 -AARCH64_INS_DECD = 1002 -AARCH64_INS_DECH = 1003 -AARCH64_INS_DECP = 1004 -AARCH64_INS_DECW = 1005 -AARCH64_INS_DMB = 1006 -AARCH64_INS_DRPS = 1007 -AARCH64_INS_DSB = 1008 -AARCH64_INS_DUPM = 1009 -AARCH64_INS_DUPQ = 1010 -AARCH64_INS_DUP = 1011 -AARCH64_INS_MOV = 1012 -AARCH64_INS_EON = 1013 -AARCH64_INS_EOR3 = 1014 -AARCH64_INS_EORBT = 1015 -AARCH64_INS_EORQV = 1016 -AARCH64_INS_EORS = 1017 -AARCH64_INS_EORTB = 1018 -AARCH64_INS_EORV = 1019 -AARCH64_INS_EOR = 1020 -AARCH64_INS_ERET = 1021 -AARCH64_INS_ERETAA = 1022 -AARCH64_INS_ERETAB = 1023 -AARCH64_INS_EXTQ = 1024 -AARCH64_INS_MOVA = 1025 -AARCH64_INS_EXTR = 1026 -AARCH64_INS_EXT = 1027 -AARCH64_INS_F1CVTL2 = 1028 -AARCH64_INS_F1CVTLT = 1029 -AARCH64_INS_F1CVTL = 1030 -AARCH64_INS_F1CVT = 1031 -AARCH64_INS_F2CVTL2 = 1032 -AARCH64_INS_F2CVTLT = 1033 -AARCH64_INS_F2CVTL = 1034 -AARCH64_INS_F2CVT = 1035 -AARCH64_INS_FABD = 1036 -AARCH64_INS_FABS = 1037 -AARCH64_INS_FACGE = 1038 -AARCH64_INS_FACGT = 1039 -AARCH64_INS_FADDA = 1040 -AARCH64_INS_FADD = 1041 -AARCH64_INS_FADDP = 1042 -AARCH64_INS_FADDQV = 1043 -AARCH64_INS_FADDV = 1044 -AARCH64_INS_FAMAX = 1045 -AARCH64_INS_FAMIN = 1046 -AARCH64_INS_FCADD = 1047 -AARCH64_INS_FCCMP = 1048 -AARCH64_INS_FCCMPE = 1049 -AARCH64_INS_FCLAMP = 1050 -AARCH64_INS_FCMEQ = 1051 -AARCH64_INS_FCMGE = 1052 -AARCH64_INS_FCMGT = 1053 -AARCH64_INS_FCMLA = 1054 -AARCH64_INS_FCMLE = 1055 -AARCH64_INS_FCMLT = 1056 -AARCH64_INS_FCMNE = 1057 -AARCH64_INS_FCMP = 1058 -AARCH64_INS_FCMPE = 1059 -AARCH64_INS_FCMUO = 1060 -AARCH64_INS_FCPY = 1061 -AARCH64_INS_FCSEL = 1062 -AARCH64_INS_FCVTAS = 1063 -AARCH64_INS_FCVTAU = 1064 -AARCH64_INS_FCVT = 1065 -AARCH64_INS_FCVTLT = 1066 -AARCH64_INS_FCVTL = 1067 -AARCH64_INS_FCVTL2 = 1068 -AARCH64_INS_FCVTMS = 1069 -AARCH64_INS_FCVTMU = 1070 -AARCH64_INS_FCVTNB = 1071 -AARCH64_INS_FCVTNS = 1072 -AARCH64_INS_FCVTNT = 1073 -AARCH64_INS_FCVTNU = 1074 -AARCH64_INS_FCVTN = 1075 -AARCH64_INS_FCVTN2 = 1076 -AARCH64_INS_FCVTPS = 1077 -AARCH64_INS_FCVTPU = 1078 -AARCH64_INS_FCVTXNT = 1079 -AARCH64_INS_FCVTXN = 1080 -AARCH64_INS_FCVTXN2 = 1081 -AARCH64_INS_FCVTX = 1082 -AARCH64_INS_FCVTZS = 1083 -AARCH64_INS_FCVTZU = 1084 -AARCH64_INS_FDIV = 1085 -AARCH64_INS_FDIVR = 1086 -AARCH64_INS_FDOT = 1087 -AARCH64_INS_FDUP = 1088 -AARCH64_INS_FEXPA = 1089 -AARCH64_INS_FJCVTZS = 1090 -AARCH64_INS_FLOGB = 1091 -AARCH64_INS_FMADD = 1092 -AARCH64_INS_FMAD = 1093 -AARCH64_INS_FMAX = 1094 -AARCH64_INS_FMAXNM = 1095 -AARCH64_INS_FMAXNMP = 1096 -AARCH64_INS_FMAXNMQV = 1097 -AARCH64_INS_FMAXNMV = 1098 -AARCH64_INS_FMAXP = 1099 -AARCH64_INS_FMAXQV = 1100 -AARCH64_INS_FMAXV = 1101 -AARCH64_INS_FMIN = 1102 -AARCH64_INS_FMINNM = 1103 -AARCH64_INS_FMINNMP = 1104 -AARCH64_INS_FMINNMQV = 1105 -AARCH64_INS_FMINNMV = 1106 -AARCH64_INS_FMINP = 1107 -AARCH64_INS_FMINQV = 1108 -AARCH64_INS_FMINV = 1109 -AARCH64_INS_FMLAL2 = 1110 -AARCH64_INS_FMLALB = 1111 -AARCH64_INS_FMLALLBB = 1112 -AARCH64_INS_FMLALLBT = 1113 -AARCH64_INS_FMLALLTB = 1114 -AARCH64_INS_FMLALLTT = 1115 -AARCH64_INS_FMLALL = 1116 -AARCH64_INS_FMLALT = 1117 -AARCH64_INS_FMLAL = 1118 -AARCH64_INS_FMLA = 1119 -AARCH64_INS_FMLSL2 = 1120 -AARCH64_INS_FMLSLB = 1121 -AARCH64_INS_FMLSLT = 1122 -AARCH64_INS_FMLSL = 1123 -AARCH64_INS_FMLS = 1124 -AARCH64_INS_FMMLA = 1125 -AARCH64_INS_FMOPA = 1126 -AARCH64_INS_FMOPS = 1127 -AARCH64_INS_FMOV = 1128 -AARCH64_INS_FMSB = 1129 -AARCH64_INS_FMSUB = 1130 -AARCH64_INS_FMUL = 1131 -AARCH64_INS_FMULX = 1132 -AARCH64_INS_FNEG = 1133 -AARCH64_INS_FNMADD = 1134 -AARCH64_INS_FNMAD = 1135 -AARCH64_INS_FNMLA = 1136 -AARCH64_INS_FNMLS = 1137 -AARCH64_INS_FNMSB = 1138 -AARCH64_INS_FNMSUB = 1139 -AARCH64_INS_FNMUL = 1140 -AARCH64_INS_FRECPE = 1141 -AARCH64_INS_FRECPS = 1142 -AARCH64_INS_FRECPX = 1143 -AARCH64_INS_FRINT32X = 1144 -AARCH64_INS_FRINT32Z = 1145 -AARCH64_INS_FRINT64X = 1146 -AARCH64_INS_FRINT64Z = 1147 -AARCH64_INS_FRINTA = 1148 -AARCH64_INS_FRINTI = 1149 -AARCH64_INS_FRINTM = 1150 -AARCH64_INS_FRINTN = 1151 -AARCH64_INS_FRINTP = 1152 -AARCH64_INS_FRINTX = 1153 -AARCH64_INS_FRINTZ = 1154 -AARCH64_INS_FRSQRTE = 1155 -AARCH64_INS_FRSQRTS = 1156 -AARCH64_INS_FSCALE = 1157 -AARCH64_INS_FSQRT = 1158 -AARCH64_INS_FSUB = 1159 -AARCH64_INS_FSUBR = 1160 -AARCH64_INS_FTMAD = 1161 -AARCH64_INS_FTSMUL = 1162 -AARCH64_INS_FTSSEL = 1163 -AARCH64_INS_FVDOTB = 1164 -AARCH64_INS_FVDOTT = 1165 -AARCH64_INS_FVDOT = 1166 -AARCH64_INS_GCSPOPCX = 1167 -AARCH64_INS_GCSPOPM = 1168 -AARCH64_INS_GCSPOPX = 1169 -AARCH64_INS_GCSPUSHM = 1170 -AARCH64_INS_GCSPUSHX = 1171 -AARCH64_INS_GCSSS1 = 1172 -AARCH64_INS_GCSSS2 = 1173 -AARCH64_INS_GCSSTR = 1174 -AARCH64_INS_GCSSTTR = 1175 -AARCH64_INS_LD1B = 1176 -AARCH64_INS_LD1D = 1177 -AARCH64_INS_LD1H = 1178 -AARCH64_INS_LD1Q = 1179 -AARCH64_INS_LD1SB = 1180 -AARCH64_INS_LD1SH = 1181 -AARCH64_INS_LD1SW = 1182 -AARCH64_INS_LD1W = 1183 -AARCH64_INS_LDFF1B = 1184 -AARCH64_INS_LDFF1D = 1185 -AARCH64_INS_LDFF1H = 1186 -AARCH64_INS_LDFF1SB = 1187 -AARCH64_INS_LDFF1SH = 1188 -AARCH64_INS_LDFF1SW = 1189 -AARCH64_INS_LDFF1W = 1190 -AARCH64_INS_GMI = 1191 -AARCH64_INS_HISTCNT = 1192 -AARCH64_INS_HISTSEG = 1193 -AARCH64_INS_HLT = 1194 -AARCH64_INS_HVC = 1195 -AARCH64_INS_INCB = 1196 -AARCH64_INS_INCD = 1197 -AARCH64_INS_INCH = 1198 -AARCH64_INS_INCP = 1199 -AARCH64_INS_INCW = 1200 -AARCH64_INS_INDEX = 1201 -AARCH64_INS_INSR = 1202 -AARCH64_INS_INS = 1203 -AARCH64_INS_IRG = 1204 -AARCH64_INS_ISB = 1205 -AARCH64_INS_LASTA = 1206 -AARCH64_INS_LASTB = 1207 -AARCH64_INS_LD1 = 1208 -AARCH64_INS_LD1RB = 1209 -AARCH64_INS_LD1RD = 1210 -AARCH64_INS_LD1RH = 1211 -AARCH64_INS_LD1ROB = 1212 -AARCH64_INS_LD1ROD = 1213 -AARCH64_INS_LD1ROH = 1214 -AARCH64_INS_LD1ROW = 1215 -AARCH64_INS_LD1RQB = 1216 -AARCH64_INS_LD1RQD = 1217 -AARCH64_INS_LD1RQH = 1218 -AARCH64_INS_LD1RQW = 1219 -AARCH64_INS_LD1RSB = 1220 -AARCH64_INS_LD1RSH = 1221 -AARCH64_INS_LD1RSW = 1222 -AARCH64_INS_LD1RW = 1223 -AARCH64_INS_LD1R = 1224 -AARCH64_INS_LD2B = 1225 -AARCH64_INS_LD2D = 1226 -AARCH64_INS_LD2H = 1227 -AARCH64_INS_LD2Q = 1228 -AARCH64_INS_LD2R = 1229 -AARCH64_INS_LD2 = 1230 -AARCH64_INS_LD2W = 1231 -AARCH64_INS_LD3B = 1232 -AARCH64_INS_LD3D = 1233 -AARCH64_INS_LD3H = 1234 -AARCH64_INS_LD3Q = 1235 -AARCH64_INS_LD3R = 1236 -AARCH64_INS_LD3 = 1237 -AARCH64_INS_LD3W = 1238 -AARCH64_INS_LD4B = 1239 -AARCH64_INS_LD4D = 1240 -AARCH64_INS_LD4 = 1241 -AARCH64_INS_LD4H = 1242 -AARCH64_INS_LD4Q = 1243 -AARCH64_INS_LD4R = 1244 -AARCH64_INS_LD4W = 1245 -AARCH64_INS_LD64B = 1246 -AARCH64_INS_LDADDAB = 1247 -AARCH64_INS_LDADDAH = 1248 -AARCH64_INS_LDADDALB = 1249 -AARCH64_INS_LDADDALH = 1250 -AARCH64_INS_LDADDAL = 1251 -AARCH64_INS_LDADDA = 1252 -AARCH64_INS_LDADDB = 1253 -AARCH64_INS_LDADDH = 1254 -AARCH64_INS_LDADDLB = 1255 -AARCH64_INS_LDADDLH = 1256 -AARCH64_INS_LDADDL = 1257 -AARCH64_INS_LDADD = 1258 -AARCH64_INS_LDAP1 = 1259 -AARCH64_INS_LDAPRB = 1260 -AARCH64_INS_LDAPRH = 1261 -AARCH64_INS_LDAPR = 1262 -AARCH64_INS_LDAPURB = 1263 -AARCH64_INS_LDAPURH = 1264 -AARCH64_INS_LDAPURSB = 1265 -AARCH64_INS_LDAPURSH = 1266 -AARCH64_INS_LDAPURSW = 1267 -AARCH64_INS_LDAPUR = 1268 -AARCH64_INS_LDARB = 1269 -AARCH64_INS_LDARH = 1270 -AARCH64_INS_LDAR = 1271 -AARCH64_INS_LDAXP = 1272 -AARCH64_INS_LDAXRB = 1273 -AARCH64_INS_LDAXRH = 1274 -AARCH64_INS_LDAXR = 1275 -AARCH64_INS_LDCLRAB = 1276 -AARCH64_INS_LDCLRAH = 1277 -AARCH64_INS_LDCLRALB = 1278 -AARCH64_INS_LDCLRALH = 1279 -AARCH64_INS_LDCLRAL = 1280 -AARCH64_INS_LDCLRA = 1281 -AARCH64_INS_LDCLRB = 1282 -AARCH64_INS_LDCLRH = 1283 -AARCH64_INS_LDCLRLB = 1284 -AARCH64_INS_LDCLRLH = 1285 -AARCH64_INS_LDCLRL = 1286 -AARCH64_INS_LDCLRP = 1287 -AARCH64_INS_LDCLRPA = 1288 -AARCH64_INS_LDCLRPAL = 1289 -AARCH64_INS_LDCLRPL = 1290 -AARCH64_INS_LDCLR = 1291 -AARCH64_INS_LDEORAB = 1292 -AARCH64_INS_LDEORAH = 1293 -AARCH64_INS_LDEORALB = 1294 -AARCH64_INS_LDEORALH = 1295 -AARCH64_INS_LDEORAL = 1296 -AARCH64_INS_LDEORA = 1297 -AARCH64_INS_LDEORB = 1298 -AARCH64_INS_LDEORH = 1299 -AARCH64_INS_LDEORLB = 1300 -AARCH64_INS_LDEORLH = 1301 -AARCH64_INS_LDEORL = 1302 -AARCH64_INS_LDEOR = 1303 -AARCH64_INS_LDG = 1304 -AARCH64_INS_LDGM = 1305 -AARCH64_INS_LDIAPP = 1306 -AARCH64_INS_LDLARB = 1307 -AARCH64_INS_LDLARH = 1308 -AARCH64_INS_LDLAR = 1309 -AARCH64_INS_LDNF1B = 1310 -AARCH64_INS_LDNF1D = 1311 -AARCH64_INS_LDNF1H = 1312 -AARCH64_INS_LDNF1SB = 1313 -AARCH64_INS_LDNF1SH = 1314 -AARCH64_INS_LDNF1SW = 1315 -AARCH64_INS_LDNF1W = 1316 -AARCH64_INS_LDNP = 1317 -AARCH64_INS_LDNT1B = 1318 -AARCH64_INS_LDNT1D = 1319 -AARCH64_INS_LDNT1H = 1320 -AARCH64_INS_LDNT1SB = 1321 -AARCH64_INS_LDNT1SH = 1322 -AARCH64_INS_LDNT1SW = 1323 -AARCH64_INS_LDNT1W = 1324 -AARCH64_INS_LDP = 1325 -AARCH64_INS_LDPSW = 1326 -AARCH64_INS_LDRAA = 1327 -AARCH64_INS_LDRAB = 1328 -AARCH64_INS_LDRB = 1329 -AARCH64_INS_LDR = 1330 -AARCH64_INS_LDRH = 1331 -AARCH64_INS_LDRSB = 1332 -AARCH64_INS_LDRSH = 1333 -AARCH64_INS_LDRSW = 1334 -AARCH64_INS_LDSETAB = 1335 -AARCH64_INS_LDSETAH = 1336 -AARCH64_INS_LDSETALB = 1337 -AARCH64_INS_LDSETALH = 1338 -AARCH64_INS_LDSETAL = 1339 -AARCH64_INS_LDSETA = 1340 -AARCH64_INS_LDSETB = 1341 -AARCH64_INS_LDSETH = 1342 -AARCH64_INS_LDSETLB = 1343 -AARCH64_INS_LDSETLH = 1344 -AARCH64_INS_LDSETL = 1345 -AARCH64_INS_LDSETP = 1346 -AARCH64_INS_LDSETPA = 1347 -AARCH64_INS_LDSETPAL = 1348 -AARCH64_INS_LDSETPL = 1349 -AARCH64_INS_LDSET = 1350 -AARCH64_INS_LDSMAXAB = 1351 -AARCH64_INS_LDSMAXAH = 1352 -AARCH64_INS_LDSMAXALB = 1353 -AARCH64_INS_LDSMAXALH = 1354 -AARCH64_INS_LDSMAXAL = 1355 -AARCH64_INS_LDSMAXA = 1356 -AARCH64_INS_LDSMAXB = 1357 -AARCH64_INS_LDSMAXH = 1358 -AARCH64_INS_LDSMAXLB = 1359 -AARCH64_INS_LDSMAXLH = 1360 -AARCH64_INS_LDSMAXL = 1361 -AARCH64_INS_LDSMAX = 1362 -AARCH64_INS_LDSMINAB = 1363 -AARCH64_INS_LDSMINAH = 1364 -AARCH64_INS_LDSMINALB = 1365 -AARCH64_INS_LDSMINALH = 1366 -AARCH64_INS_LDSMINAL = 1367 -AARCH64_INS_LDSMINA = 1368 -AARCH64_INS_LDSMINB = 1369 -AARCH64_INS_LDSMINH = 1370 -AARCH64_INS_LDSMINLB = 1371 -AARCH64_INS_LDSMINLH = 1372 -AARCH64_INS_LDSMINL = 1373 -AARCH64_INS_LDSMIN = 1374 -AARCH64_INS_LDTRB = 1375 -AARCH64_INS_LDTRH = 1376 -AARCH64_INS_LDTRSB = 1377 -AARCH64_INS_LDTRSH = 1378 -AARCH64_INS_LDTRSW = 1379 -AARCH64_INS_LDTR = 1380 -AARCH64_INS_LDUMAXAB = 1381 -AARCH64_INS_LDUMAXAH = 1382 -AARCH64_INS_LDUMAXALB = 1383 -AARCH64_INS_LDUMAXALH = 1384 -AARCH64_INS_LDUMAXAL = 1385 -AARCH64_INS_LDUMAXA = 1386 -AARCH64_INS_LDUMAXB = 1387 -AARCH64_INS_LDUMAXH = 1388 -AARCH64_INS_LDUMAXLB = 1389 -AARCH64_INS_LDUMAXLH = 1390 -AARCH64_INS_LDUMAXL = 1391 -AARCH64_INS_LDUMAX = 1392 -AARCH64_INS_LDUMINAB = 1393 -AARCH64_INS_LDUMINAH = 1394 -AARCH64_INS_LDUMINALB = 1395 -AARCH64_INS_LDUMINALH = 1396 -AARCH64_INS_LDUMINAL = 1397 -AARCH64_INS_LDUMINA = 1398 -AARCH64_INS_LDUMINB = 1399 -AARCH64_INS_LDUMINH = 1400 -AARCH64_INS_LDUMINLB = 1401 -AARCH64_INS_LDUMINLH = 1402 -AARCH64_INS_LDUMINL = 1403 -AARCH64_INS_LDUMIN = 1404 -AARCH64_INS_LDURB = 1405 -AARCH64_INS_LDUR = 1406 -AARCH64_INS_LDURH = 1407 -AARCH64_INS_LDURSB = 1408 -AARCH64_INS_LDURSH = 1409 -AARCH64_INS_LDURSW = 1410 -AARCH64_INS_LDXP = 1411 -AARCH64_INS_LDXRB = 1412 -AARCH64_INS_LDXRH = 1413 -AARCH64_INS_LDXR = 1414 -AARCH64_INS_LSLR = 1415 -AARCH64_INS_LSL = 1416 -AARCH64_INS_LSRR = 1417 -AARCH64_INS_LSR = 1418 -AARCH64_INS_LUTI2 = 1419 -AARCH64_INS_LUTI4 = 1420 -AARCH64_INS_MADDPT = 1421 -AARCH64_INS_MADD = 1422 -AARCH64_INS_MADPT = 1423 -AARCH64_INS_MAD = 1424 -AARCH64_INS_MATCH = 1425 -AARCH64_INS_MLAPT = 1426 -AARCH64_INS_MLA = 1427 -AARCH64_INS_MLS = 1428 -AARCH64_INS_SETGE = 1429 -AARCH64_INS_SETGEN = 1430 -AARCH64_INS_SETGET = 1431 -AARCH64_INS_SETGETN = 1432 -AARCH64_INS_MOVAZ = 1433 -AARCH64_INS_MOVI = 1434 -AARCH64_INS_MOVK = 1435 -AARCH64_INS_MOVN = 1436 -AARCH64_INS_MOVPRFX = 1437 -AARCH64_INS_MOVT = 1438 -AARCH64_INS_MOVZ = 1439 -AARCH64_INS_MRRS = 1440 -AARCH64_INS_MRS = 1441 -AARCH64_INS_MSB = 1442 -AARCH64_INS_MSR = 1443 -AARCH64_INS_MSRR = 1444 -AARCH64_INS_MSUBPT = 1445 -AARCH64_INS_MSUB = 1446 -AARCH64_INS_MUL = 1447 -AARCH64_INS_MVNI = 1448 -AARCH64_INS_NANDS = 1449 -AARCH64_INS_NAND = 1450 -AARCH64_INS_NBSL = 1451 -AARCH64_INS_NEG = 1452 -AARCH64_INS_NMATCH = 1453 -AARCH64_INS_NORS = 1454 -AARCH64_INS_NOR = 1455 -AARCH64_INS_NOT = 1456 -AARCH64_INS_ORNS = 1457 -AARCH64_INS_ORN = 1458 -AARCH64_INS_ORQV = 1459 -AARCH64_INS_ORRS = 1460 -AARCH64_INS_ORR = 1461 -AARCH64_INS_ORV = 1462 -AARCH64_INS_PACDA = 1463 -AARCH64_INS_PACDB = 1464 -AARCH64_INS_PACDZA = 1465 -AARCH64_INS_PACDZB = 1466 -AARCH64_INS_PACGA = 1467 -AARCH64_INS_PACIA = 1468 -AARCH64_INS_PACIA171615 = 1469 -AARCH64_INS_PACIASPPC = 1470 -AARCH64_INS_PACIB = 1471 -AARCH64_INS_PACIB171615 = 1472 -AARCH64_INS_PACIBSPPC = 1473 -AARCH64_INS_PACIZA = 1474 -AARCH64_INS_PACIZB = 1475 -AARCH64_INS_PACNBIASPPC = 1476 -AARCH64_INS_PACNBIBSPPC = 1477 -AARCH64_INS_PEXT = 1478 -AARCH64_INS_PFALSE = 1479 -AARCH64_INS_PFIRST = 1480 -AARCH64_INS_PMOV = 1481 -AARCH64_INS_PMULLB = 1482 -AARCH64_INS_PMULLT = 1483 -AARCH64_INS_PMULL2 = 1484 -AARCH64_INS_PMULL = 1485 -AARCH64_INS_PMUL = 1486 -AARCH64_INS_PNEXT = 1487 -AARCH64_INS_PRFB = 1488 -AARCH64_INS_PRFD = 1489 -AARCH64_INS_PRFH = 1490 -AARCH64_INS_PRFM = 1491 -AARCH64_INS_PRFUM = 1492 -AARCH64_INS_PRFW = 1493 -AARCH64_INS_PSEL = 1494 -AARCH64_INS_PTEST = 1495 -AARCH64_INS_PTRUES = 1496 -AARCH64_INS_PTRUE = 1497 -AARCH64_INS_PUNPKHI = 1498 -AARCH64_INS_PUNPKLO = 1499 -AARCH64_INS_RADDHNB = 1500 -AARCH64_INS_RADDHNT = 1501 -AARCH64_INS_RADDHN = 1502 -AARCH64_INS_RADDHN2 = 1503 -AARCH64_INS_RAX1 = 1504 -AARCH64_INS_RBIT = 1505 -AARCH64_INS_RCWCAS = 1506 -AARCH64_INS_RCWCASA = 1507 -AARCH64_INS_RCWCASAL = 1508 -AARCH64_INS_RCWCASL = 1509 -AARCH64_INS_RCWCASP = 1510 -AARCH64_INS_RCWCASPA = 1511 -AARCH64_INS_RCWCASPAL = 1512 -AARCH64_INS_RCWCASPL = 1513 -AARCH64_INS_RCWCLR = 1514 -AARCH64_INS_RCWCLRA = 1515 -AARCH64_INS_RCWCLRAL = 1516 -AARCH64_INS_RCWCLRL = 1517 -AARCH64_INS_RCWCLRP = 1518 -AARCH64_INS_RCWCLRPA = 1519 -AARCH64_INS_RCWCLRPAL = 1520 -AARCH64_INS_RCWCLRPL = 1521 -AARCH64_INS_RCWSCLR = 1522 -AARCH64_INS_RCWSCLRA = 1523 -AARCH64_INS_RCWSCLRAL = 1524 -AARCH64_INS_RCWSCLRL = 1525 -AARCH64_INS_RCWSCLRP = 1526 -AARCH64_INS_RCWSCLRPA = 1527 -AARCH64_INS_RCWSCLRPAL = 1528 -AARCH64_INS_RCWSCLRPL = 1529 -AARCH64_INS_RCWSCAS = 1530 -AARCH64_INS_RCWSCASA = 1531 -AARCH64_INS_RCWSCASAL = 1532 -AARCH64_INS_RCWSCASL = 1533 -AARCH64_INS_RCWSCASP = 1534 -AARCH64_INS_RCWSCASPA = 1535 -AARCH64_INS_RCWSCASPAL = 1536 -AARCH64_INS_RCWSCASPL = 1537 -AARCH64_INS_RCWSET = 1538 -AARCH64_INS_RCWSETA = 1539 -AARCH64_INS_RCWSETAL = 1540 -AARCH64_INS_RCWSETL = 1541 -AARCH64_INS_RCWSETP = 1542 -AARCH64_INS_RCWSETPA = 1543 -AARCH64_INS_RCWSETPAL = 1544 -AARCH64_INS_RCWSETPL = 1545 -AARCH64_INS_RCWSSET = 1546 -AARCH64_INS_RCWSSETA = 1547 -AARCH64_INS_RCWSSETAL = 1548 -AARCH64_INS_RCWSSETL = 1549 -AARCH64_INS_RCWSSETP = 1550 -AARCH64_INS_RCWSSETPA = 1551 -AARCH64_INS_RCWSSETPAL = 1552 -AARCH64_INS_RCWSSETPL = 1553 -AARCH64_INS_RCWSWP = 1554 -AARCH64_INS_RCWSWPA = 1555 -AARCH64_INS_RCWSWPAL = 1556 -AARCH64_INS_RCWSWPL = 1557 -AARCH64_INS_RCWSWPP = 1558 -AARCH64_INS_RCWSWPPA = 1559 -AARCH64_INS_RCWSWPPAL = 1560 -AARCH64_INS_RCWSWPPL = 1561 -AARCH64_INS_RCWSSWP = 1562 -AARCH64_INS_RCWSSWPA = 1563 -AARCH64_INS_RCWSSWPAL = 1564 -AARCH64_INS_RCWSSWPL = 1565 -AARCH64_INS_RCWSSWPP = 1566 -AARCH64_INS_RCWSSWPPA = 1567 -AARCH64_INS_RCWSSWPPAL = 1568 -AARCH64_INS_RCWSSWPPL = 1569 -AARCH64_INS_RDFFRS = 1570 -AARCH64_INS_RDFFR = 1571 -AARCH64_INS_RDSVL = 1572 -AARCH64_INS_RDVL = 1573 -AARCH64_INS_RET = 1574 -AARCH64_INS_RETAA = 1575 -AARCH64_INS_RETAASPPC = 1576 -AARCH64_INS_RETAB = 1577 -AARCH64_INS_RETABSPPC = 1578 -AARCH64_INS_REV16 = 1579 -AARCH64_INS_REV32 = 1580 -AARCH64_INS_REV64 = 1581 -AARCH64_INS_REVB = 1582 -AARCH64_INS_REVD = 1583 -AARCH64_INS_REVH = 1584 -AARCH64_INS_REVW = 1585 -AARCH64_INS_REV = 1586 -AARCH64_INS_RMIF = 1587 -AARCH64_INS_ROR = 1588 -AARCH64_INS_RPRFM = 1589 -AARCH64_INS_RSHRNB = 1590 -AARCH64_INS_RSHRNT = 1591 -AARCH64_INS_RSHRN2 = 1592 -AARCH64_INS_RSHRN = 1593 -AARCH64_INS_RSUBHNB = 1594 -AARCH64_INS_RSUBHNT = 1595 -AARCH64_INS_RSUBHN = 1596 -AARCH64_INS_RSUBHN2 = 1597 -AARCH64_INS_SABALB = 1598 -AARCH64_INS_SABALT = 1599 -AARCH64_INS_SABAL2 = 1600 -AARCH64_INS_SABAL = 1601 -AARCH64_INS_SABA = 1602 -AARCH64_INS_SABDLB = 1603 -AARCH64_INS_SABDLT = 1604 -AARCH64_INS_SABDL2 = 1605 -AARCH64_INS_SABDL = 1606 -AARCH64_INS_SABD = 1607 -AARCH64_INS_SADALP = 1608 -AARCH64_INS_SADDLBT = 1609 -AARCH64_INS_SADDLB = 1610 -AARCH64_INS_SADDLP = 1611 -AARCH64_INS_SADDLT = 1612 -AARCH64_INS_SADDLV = 1613 -AARCH64_INS_SADDL2 = 1614 -AARCH64_INS_SADDL = 1615 -AARCH64_INS_SADDV = 1616 -AARCH64_INS_SADDWB = 1617 -AARCH64_INS_SADDWT = 1618 -AARCH64_INS_SADDW2 = 1619 -AARCH64_INS_SADDW = 1620 -AARCH64_INS_SB = 1621 -AARCH64_INS_SBCLB = 1622 -AARCH64_INS_SBCLT = 1623 -AARCH64_INS_SBCS = 1624 -AARCH64_INS_SBC = 1625 -AARCH64_INS_SBFM = 1626 -AARCH64_INS_SCLAMP = 1627 -AARCH64_INS_SCVTF = 1628 -AARCH64_INS_SDIVR = 1629 -AARCH64_INS_SDIV = 1630 -AARCH64_INS_SDOT = 1631 -AARCH64_INS_SEL = 1632 -AARCH64_INS_SETE = 1633 -AARCH64_INS_SETEN = 1634 -AARCH64_INS_SETET = 1635 -AARCH64_INS_SETETN = 1636 -AARCH64_INS_SETF16 = 1637 -AARCH64_INS_SETF8 = 1638 -AARCH64_INS_SETFFR = 1639 -AARCH64_INS_SETGM = 1640 -AARCH64_INS_SETGMN = 1641 -AARCH64_INS_SETGMT = 1642 -AARCH64_INS_SETGMTN = 1643 -AARCH64_INS_SETGP = 1644 -AARCH64_INS_SETGPN = 1645 -AARCH64_INS_SETGPT = 1646 -AARCH64_INS_SETGPTN = 1647 -AARCH64_INS_SETM = 1648 -AARCH64_INS_SETMN = 1649 -AARCH64_INS_SETMT = 1650 -AARCH64_INS_SETMTN = 1651 -AARCH64_INS_SETP = 1652 -AARCH64_INS_SETPN = 1653 -AARCH64_INS_SETPT = 1654 -AARCH64_INS_SETPTN = 1655 -AARCH64_INS_SHA1C = 1656 -AARCH64_INS_SHA1H = 1657 -AARCH64_INS_SHA1M = 1658 -AARCH64_INS_SHA1P = 1659 -AARCH64_INS_SHA1SU0 = 1660 -AARCH64_INS_SHA1SU1 = 1661 -AARCH64_INS_SHA256H2 = 1662 -AARCH64_INS_SHA256H = 1663 -AARCH64_INS_SHA256SU0 = 1664 -AARCH64_INS_SHA256SU1 = 1665 -AARCH64_INS_SHA512H = 1666 -AARCH64_INS_SHA512H2 = 1667 -AARCH64_INS_SHA512SU0 = 1668 -AARCH64_INS_SHA512SU1 = 1669 -AARCH64_INS_SHADD = 1670 -AARCH64_INS_SHLL2 = 1671 -AARCH64_INS_SHLL = 1672 -AARCH64_INS_SHL = 1673 -AARCH64_INS_SHRNB = 1674 -AARCH64_INS_SHRNT = 1675 -AARCH64_INS_SHRN2 = 1676 -AARCH64_INS_SHRN = 1677 -AARCH64_INS_SHSUBR = 1678 -AARCH64_INS_SHSUB = 1679 -AARCH64_INS_SLI = 1680 -AARCH64_INS_SM3PARTW1 = 1681 -AARCH64_INS_SM3PARTW2 = 1682 -AARCH64_INS_SM3SS1 = 1683 -AARCH64_INS_SM3TT1A = 1684 -AARCH64_INS_SM3TT1B = 1685 -AARCH64_INS_SM3TT2A = 1686 -AARCH64_INS_SM3TT2B = 1687 -AARCH64_INS_SM4E = 1688 -AARCH64_INS_SM4EKEY = 1689 -AARCH64_INS_SMADDL = 1690 -AARCH64_INS_SMAXP = 1691 -AARCH64_INS_SMAXQV = 1692 -AARCH64_INS_SMAXV = 1693 -AARCH64_INS_SMAX = 1694 -AARCH64_INS_SMC = 1695 -AARCH64_INS_SMINP = 1696 -AARCH64_INS_SMINQV = 1697 -AARCH64_INS_SMINV = 1698 -AARCH64_INS_SMIN = 1699 -AARCH64_INS_SMLALB = 1700 -AARCH64_INS_SMLALL = 1701 -AARCH64_INS_SMLALT = 1702 -AARCH64_INS_SMLAL = 1703 -AARCH64_INS_SMLAL2 = 1704 -AARCH64_INS_SMLSLB = 1705 -AARCH64_INS_SMLSLL = 1706 -AARCH64_INS_SMLSLT = 1707 -AARCH64_INS_SMLSL = 1708 -AARCH64_INS_SMLSL2 = 1709 -AARCH64_INS_SMMLA = 1710 -AARCH64_INS_SMOPA = 1711 -AARCH64_INS_SMOPS = 1712 -AARCH64_INS_SMOV = 1713 -AARCH64_INS_SMSUBL = 1714 -AARCH64_INS_SMULH = 1715 -AARCH64_INS_SMULLB = 1716 -AARCH64_INS_SMULLT = 1717 -AARCH64_INS_SMULL2 = 1718 -AARCH64_INS_SMULL = 1719 -AARCH64_INS_SPLICE = 1720 -AARCH64_INS_SQABS = 1721 -AARCH64_INS_SQADD = 1722 -AARCH64_INS_SQCADD = 1723 -AARCH64_INS_SQCVTN = 1724 -AARCH64_INS_SQCVTUN = 1725 -AARCH64_INS_SQCVTU = 1726 -AARCH64_INS_SQCVT = 1727 -AARCH64_INS_SQDECB = 1728 -AARCH64_INS_SQDECD = 1729 -AARCH64_INS_SQDECH = 1730 -AARCH64_INS_SQDECP = 1731 -AARCH64_INS_SQDECW = 1732 -AARCH64_INS_SQDMLALBT = 1733 -AARCH64_INS_SQDMLALB = 1734 -AARCH64_INS_SQDMLALT = 1735 -AARCH64_INS_SQDMLAL = 1736 -AARCH64_INS_SQDMLAL2 = 1737 -AARCH64_INS_SQDMLSLBT = 1738 -AARCH64_INS_SQDMLSLB = 1739 -AARCH64_INS_SQDMLSLT = 1740 -AARCH64_INS_SQDMLSL = 1741 -AARCH64_INS_SQDMLSL2 = 1742 -AARCH64_INS_SQDMULH = 1743 -AARCH64_INS_SQDMULLB = 1744 -AARCH64_INS_SQDMULLT = 1745 -AARCH64_INS_SQDMULL = 1746 -AARCH64_INS_SQDMULL2 = 1747 -AARCH64_INS_SQINCB = 1748 -AARCH64_INS_SQINCD = 1749 -AARCH64_INS_SQINCH = 1750 -AARCH64_INS_SQINCP = 1751 -AARCH64_INS_SQINCW = 1752 -AARCH64_INS_SQNEG = 1753 -AARCH64_INS_SQRDCMLAH = 1754 -AARCH64_INS_SQRDMLAH = 1755 -AARCH64_INS_SQRDMLSH = 1756 -AARCH64_INS_SQRDMULH = 1757 -AARCH64_INS_SQRSHLR = 1758 -AARCH64_INS_SQRSHL = 1759 -AARCH64_INS_SQRSHRNB = 1760 -AARCH64_INS_SQRSHRNT = 1761 -AARCH64_INS_SQRSHRN = 1762 -AARCH64_INS_SQRSHRN2 = 1763 -AARCH64_INS_SQRSHRUNB = 1764 -AARCH64_INS_SQRSHRUNT = 1765 -AARCH64_INS_SQRSHRUN = 1766 -AARCH64_INS_SQRSHRUN2 = 1767 -AARCH64_INS_SQRSHRU = 1768 -AARCH64_INS_SQRSHR = 1769 -AARCH64_INS_SQSHLR = 1770 -AARCH64_INS_SQSHLU = 1771 -AARCH64_INS_SQSHL = 1772 -AARCH64_INS_SQSHRNB = 1773 -AARCH64_INS_SQSHRNT = 1774 -AARCH64_INS_SQSHRN = 1775 -AARCH64_INS_SQSHRN2 = 1776 -AARCH64_INS_SQSHRUNB = 1777 -AARCH64_INS_SQSHRUNT = 1778 -AARCH64_INS_SQSHRUN = 1779 -AARCH64_INS_SQSHRUN2 = 1780 -AARCH64_INS_SQSUBR = 1781 -AARCH64_INS_SQSUB = 1782 -AARCH64_INS_SQXTNB = 1783 -AARCH64_INS_SQXTNT = 1784 -AARCH64_INS_SQXTN2 = 1785 -AARCH64_INS_SQXTN = 1786 -AARCH64_INS_SQXTUNB = 1787 -AARCH64_INS_SQXTUNT = 1788 -AARCH64_INS_SQXTUN2 = 1789 -AARCH64_INS_SQXTUN = 1790 -AARCH64_INS_SRHADD = 1791 -AARCH64_INS_SRI = 1792 -AARCH64_INS_SRSHLR = 1793 -AARCH64_INS_SRSHL = 1794 -AARCH64_INS_SRSHR = 1795 -AARCH64_INS_SRSRA = 1796 -AARCH64_INS_SSHLLB = 1797 -AARCH64_INS_SSHLLT = 1798 -AARCH64_INS_SSHLL2 = 1799 -AARCH64_INS_SSHLL = 1800 -AARCH64_INS_SSHL = 1801 -AARCH64_INS_SSHR = 1802 -AARCH64_INS_SSRA = 1803 -AARCH64_INS_ST1B = 1804 -AARCH64_INS_ST1D = 1805 -AARCH64_INS_ST1H = 1806 -AARCH64_INS_ST1Q = 1807 -AARCH64_INS_ST1W = 1808 -AARCH64_INS_SSUBLBT = 1809 -AARCH64_INS_SSUBLB = 1810 -AARCH64_INS_SSUBLTB = 1811 -AARCH64_INS_SSUBLT = 1812 -AARCH64_INS_SSUBL2 = 1813 -AARCH64_INS_SSUBL = 1814 -AARCH64_INS_SSUBWB = 1815 -AARCH64_INS_SSUBWT = 1816 -AARCH64_INS_SSUBW2 = 1817 -AARCH64_INS_SSUBW = 1818 -AARCH64_INS_ST1 = 1819 -AARCH64_INS_ST2B = 1820 -AARCH64_INS_ST2D = 1821 -AARCH64_INS_ST2G = 1822 -AARCH64_INS_ST2H = 1823 -AARCH64_INS_ST2Q = 1824 -AARCH64_INS_ST2 = 1825 -AARCH64_INS_ST2W = 1826 -AARCH64_INS_ST3B = 1827 -AARCH64_INS_ST3D = 1828 -AARCH64_INS_ST3H = 1829 -AARCH64_INS_ST3Q = 1830 -AARCH64_INS_ST3 = 1831 -AARCH64_INS_ST3W = 1832 -AARCH64_INS_ST4B = 1833 -AARCH64_INS_ST4D = 1834 -AARCH64_INS_ST4 = 1835 -AARCH64_INS_ST4H = 1836 -AARCH64_INS_ST4Q = 1837 -AARCH64_INS_ST4W = 1838 -AARCH64_INS_ST64B = 1839 -AARCH64_INS_ST64BV = 1840 -AARCH64_INS_ST64BV0 = 1841 -AARCH64_INS_STGM = 1842 -AARCH64_INS_STGP = 1843 -AARCH64_INS_STG = 1844 -AARCH64_INS_STILP = 1845 -AARCH64_INS_STL1 = 1846 -AARCH64_INS_STLLRB = 1847 -AARCH64_INS_STLLRH = 1848 -AARCH64_INS_STLLR = 1849 -AARCH64_INS_STLRB = 1850 -AARCH64_INS_STLRH = 1851 -AARCH64_INS_STLR = 1852 -AARCH64_INS_STLURB = 1853 -AARCH64_INS_STLURH = 1854 -AARCH64_INS_STLUR = 1855 -AARCH64_INS_STLXP = 1856 -AARCH64_INS_STLXRB = 1857 -AARCH64_INS_STLXRH = 1858 -AARCH64_INS_STLXR = 1859 -AARCH64_INS_STNP = 1860 -AARCH64_INS_STNT1B = 1861 -AARCH64_INS_STNT1D = 1862 -AARCH64_INS_STNT1H = 1863 -AARCH64_INS_STNT1W = 1864 -AARCH64_INS_STP = 1865 -AARCH64_INS_STRB = 1866 -AARCH64_INS_STR = 1867 -AARCH64_INS_STRH = 1868 -AARCH64_INS_STTRB = 1869 -AARCH64_INS_STTRH = 1870 -AARCH64_INS_STTR = 1871 -AARCH64_INS_STURB = 1872 -AARCH64_INS_STUR = 1873 -AARCH64_INS_STURH = 1874 -AARCH64_INS_STXP = 1875 -AARCH64_INS_STXRB = 1876 -AARCH64_INS_STXRH = 1877 -AARCH64_INS_STXR = 1878 -AARCH64_INS_STZ2G = 1879 -AARCH64_INS_STZGM = 1880 -AARCH64_INS_STZG = 1881 -AARCH64_INS_SUBG = 1882 -AARCH64_INS_SUBHNB = 1883 -AARCH64_INS_SUBHNT = 1884 -AARCH64_INS_SUBHN = 1885 -AARCH64_INS_SUBHN2 = 1886 -AARCH64_INS_SUBP = 1887 -AARCH64_INS_SUBPS = 1888 -AARCH64_INS_SUBPT = 1889 -AARCH64_INS_SUBR = 1890 -AARCH64_INS_SUBS = 1891 -AARCH64_INS_SUB = 1892 -AARCH64_INS_SUDOT = 1893 -AARCH64_INS_SUMLALL = 1894 -AARCH64_INS_SUMOPA = 1895 -AARCH64_INS_SUMOPS = 1896 -AARCH64_INS_SUNPKHI = 1897 -AARCH64_INS_SUNPKLO = 1898 -AARCH64_INS_SUNPK = 1899 -AARCH64_INS_SUQADD = 1900 -AARCH64_INS_SUVDOT = 1901 -AARCH64_INS_SVC = 1902 -AARCH64_INS_SVDOT = 1903 -AARCH64_INS_SWPAB = 1904 -AARCH64_INS_SWPAH = 1905 -AARCH64_INS_SWPALB = 1906 -AARCH64_INS_SWPALH = 1907 -AARCH64_INS_SWPAL = 1908 -AARCH64_INS_SWPA = 1909 -AARCH64_INS_SWPB = 1910 -AARCH64_INS_SWPH = 1911 -AARCH64_INS_SWPLB = 1912 -AARCH64_INS_SWPLH = 1913 -AARCH64_INS_SWPL = 1914 -AARCH64_INS_SWPP = 1915 -AARCH64_INS_SWPPA = 1916 -AARCH64_INS_SWPPAL = 1917 -AARCH64_INS_SWPPL = 1918 -AARCH64_INS_SWP = 1919 -AARCH64_INS_SXTB = 1920 -AARCH64_INS_SXTH = 1921 -AARCH64_INS_SXTW = 1922 -AARCH64_INS_SYSL = 1923 -AARCH64_INS_SYSP = 1924 -AARCH64_INS_SYS = 1925 -AARCH64_INS_TBLQ = 1926 -AARCH64_INS_TBL = 1927 -AARCH64_INS_TBNZ = 1928 -AARCH64_INS_TBXQ = 1929 -AARCH64_INS_TBX = 1930 -AARCH64_INS_TBZ = 1931 -AARCH64_INS_TCANCEL = 1932 -AARCH64_INS_TCOMMIT = 1933 -AARCH64_INS_TRCIT = 1934 -AARCH64_INS_TRN1 = 1935 -AARCH64_INS_TRN2 = 1936 -AARCH64_INS_TSB = 1937 -AARCH64_INS_TSTART = 1938 -AARCH64_INS_TTEST = 1939 -AARCH64_INS_UABALB = 1940 -AARCH64_INS_UABALT = 1941 -AARCH64_INS_UABAL2 = 1942 -AARCH64_INS_UABAL = 1943 -AARCH64_INS_UABA = 1944 -AARCH64_INS_UABDLB = 1945 -AARCH64_INS_UABDLT = 1946 -AARCH64_INS_UABDL2 = 1947 -AARCH64_INS_UABDL = 1948 -AARCH64_INS_UABD = 1949 -AARCH64_INS_UADALP = 1950 -AARCH64_INS_UADDLB = 1951 -AARCH64_INS_UADDLP = 1952 -AARCH64_INS_UADDLT = 1953 -AARCH64_INS_UADDLV = 1954 -AARCH64_INS_UADDL2 = 1955 -AARCH64_INS_UADDL = 1956 -AARCH64_INS_UADDV = 1957 -AARCH64_INS_UADDWB = 1958 -AARCH64_INS_UADDWT = 1959 -AARCH64_INS_UADDW2 = 1960 -AARCH64_INS_UADDW = 1961 -AARCH64_INS_UBFM = 1962 -AARCH64_INS_UCLAMP = 1963 -AARCH64_INS_UCVTF = 1964 -AARCH64_INS_UDF = 1965 -AARCH64_INS_UDIVR = 1966 -AARCH64_INS_UDIV = 1967 -AARCH64_INS_UDOT = 1968 -AARCH64_INS_UHADD = 1969 -AARCH64_INS_UHSUBR = 1970 -AARCH64_INS_UHSUB = 1971 -AARCH64_INS_UMADDL = 1972 -AARCH64_INS_UMAXP = 1973 -AARCH64_INS_UMAXQV = 1974 -AARCH64_INS_UMAXV = 1975 -AARCH64_INS_UMAX = 1976 -AARCH64_INS_UMINP = 1977 -AARCH64_INS_UMINQV = 1978 -AARCH64_INS_UMINV = 1979 -AARCH64_INS_UMIN = 1980 -AARCH64_INS_UMLALB = 1981 -AARCH64_INS_UMLALL = 1982 -AARCH64_INS_UMLALT = 1983 -AARCH64_INS_UMLAL = 1984 -AARCH64_INS_UMLAL2 = 1985 -AARCH64_INS_UMLSLB = 1986 -AARCH64_INS_UMLSLL = 1987 -AARCH64_INS_UMLSLT = 1988 -AARCH64_INS_UMLSL = 1989 -AARCH64_INS_UMLSL2 = 1990 -AARCH64_INS_UMMLA = 1991 -AARCH64_INS_UMOPA = 1992 -AARCH64_INS_UMOPS = 1993 -AARCH64_INS_UMOV = 1994 -AARCH64_INS_UMSUBL = 1995 -AARCH64_INS_UMULH = 1996 -AARCH64_INS_UMULLB = 1997 -AARCH64_INS_UMULLT = 1998 -AARCH64_INS_UMULL2 = 1999 -AARCH64_INS_UMULL = 2000 -AARCH64_INS_UQADD = 2001 -AARCH64_INS_UQCVTN = 2002 -AARCH64_INS_UQCVT = 2003 -AARCH64_INS_UQDECB = 2004 -AARCH64_INS_UQDECD = 2005 -AARCH64_INS_UQDECH = 2006 -AARCH64_INS_UQDECP = 2007 -AARCH64_INS_UQDECW = 2008 -AARCH64_INS_UQINCB = 2009 -AARCH64_INS_UQINCD = 2010 -AARCH64_INS_UQINCH = 2011 -AARCH64_INS_UQINCP = 2012 -AARCH64_INS_UQINCW = 2013 -AARCH64_INS_UQRSHLR = 2014 -AARCH64_INS_UQRSHL = 2015 -AARCH64_INS_UQRSHRNB = 2016 -AARCH64_INS_UQRSHRNT = 2017 -AARCH64_INS_UQRSHRN = 2018 -AARCH64_INS_UQRSHRN2 = 2019 -AARCH64_INS_UQRSHR = 2020 -AARCH64_INS_UQSHLR = 2021 -AARCH64_INS_UQSHL = 2022 -AARCH64_INS_UQSHRNB = 2023 -AARCH64_INS_UQSHRNT = 2024 -AARCH64_INS_UQSHRN = 2025 -AARCH64_INS_UQSHRN2 = 2026 -AARCH64_INS_UQSUBR = 2027 -AARCH64_INS_UQSUB = 2028 -AARCH64_INS_UQXTNB = 2029 -AARCH64_INS_UQXTNT = 2030 -AARCH64_INS_UQXTN2 = 2031 -AARCH64_INS_UQXTN = 2032 -AARCH64_INS_URECPE = 2033 -AARCH64_INS_URHADD = 2034 -AARCH64_INS_URSHLR = 2035 -AARCH64_INS_URSHL = 2036 -AARCH64_INS_URSHR = 2037 -AARCH64_INS_URSQRTE = 2038 -AARCH64_INS_URSRA = 2039 -AARCH64_INS_USDOT = 2040 -AARCH64_INS_USHLLB = 2041 -AARCH64_INS_USHLLT = 2042 -AARCH64_INS_USHLL2 = 2043 -AARCH64_INS_USHLL = 2044 -AARCH64_INS_USHL = 2045 -AARCH64_INS_USHR = 2046 -AARCH64_INS_USMLALL = 2047 -AARCH64_INS_USMMLA = 2048 -AARCH64_INS_USMOPA = 2049 -AARCH64_INS_USMOPS = 2050 -AARCH64_INS_USQADD = 2051 -AARCH64_INS_USRA = 2052 -AARCH64_INS_USUBLB = 2053 -AARCH64_INS_USUBLT = 2054 -AARCH64_INS_USUBL2 = 2055 -AARCH64_INS_USUBL = 2056 -AARCH64_INS_USUBWB = 2057 -AARCH64_INS_USUBWT = 2058 -AARCH64_INS_USUBW2 = 2059 -AARCH64_INS_USUBW = 2060 -AARCH64_INS_USVDOT = 2061 -AARCH64_INS_UUNPKHI = 2062 -AARCH64_INS_UUNPKLO = 2063 -AARCH64_INS_UUNPK = 2064 -AARCH64_INS_UVDOT = 2065 -AARCH64_INS_UXTB = 2066 -AARCH64_INS_UXTH = 2067 -AARCH64_INS_UXTW = 2068 -AARCH64_INS_UZP1 = 2069 -AARCH64_INS_UZP2 = 2070 -AARCH64_INS_UZPQ1 = 2071 -AARCH64_INS_UZPQ2 = 2072 -AARCH64_INS_UZP = 2073 -AARCH64_INS_WFET = 2074 -AARCH64_INS_WFIT = 2075 -AARCH64_INS_WHILEGE = 2076 -AARCH64_INS_WHILEGT = 2077 -AARCH64_INS_WHILEHI = 2078 -AARCH64_INS_WHILEHS = 2079 -AARCH64_INS_WHILELE = 2080 -AARCH64_INS_WHILELO = 2081 -AARCH64_INS_WHILELS = 2082 -AARCH64_INS_WHILELT = 2083 -AARCH64_INS_WHILERW = 2084 -AARCH64_INS_WHILEWR = 2085 -AARCH64_INS_WRFFR = 2086 -AARCH64_INS_XAFLAG = 2087 -AARCH64_INS_XAR = 2088 -AARCH64_INS_XPACD = 2089 -AARCH64_INS_XPACI = 2090 -AARCH64_INS_XTN2 = 2091 -AARCH64_INS_XTN = 2092 -AARCH64_INS_ZERO = 2093 -AARCH64_INS_ZIP1 = 2094 -AARCH64_INS_ZIP2 = 2095 -AARCH64_INS_ZIPQ1 = 2096 -AARCH64_INS_ZIPQ2 = 2097 -AARCH64_INS_ZIP = 2098 -AARCH64_INS_ENDING = 2099 -AARCH64_INS_ALIAS_BEGIN = 2100 -AARCH64_INS_ALIAS_ADDPT = 2101 -AARCH64_INS_ALIAS_GCSB = 2102 -AARCH64_INS_ALIAS_GCSPOPM = 2103 -AARCH64_INS_ALIAS_LDAPUR = 2104 -AARCH64_INS_ALIAS_STLLRB = 2105 -AARCH64_INS_ALIAS_STLLRH = 2106 -AARCH64_INS_ALIAS_STLLR = 2107 -AARCH64_INS_ALIAS_STLRB = 2108 -AARCH64_INS_ALIAS_STLRH = 2109 -AARCH64_INS_ALIAS_STLR = 2110 -AARCH64_INS_ALIAS_STLUR = 2111 -AARCH64_INS_ALIAS_SUBPT = 2112 -AARCH64_INS_ALIAS_LDRAA = 2113 -AARCH64_INS_ALIAS_ADD = 2114 -AARCH64_INS_ALIAS_CMN = 2115 -AARCH64_INS_ALIAS_ADDS = 2116 -AARCH64_INS_ALIAS_AND = 2117 -AARCH64_INS_ALIAS_ANDS = 2118 -AARCH64_INS_ALIAS_LDR = 2119 -AARCH64_INS_ALIAS_STR = 2120 -AARCH64_INS_ALIAS_LDRB = 2121 -AARCH64_INS_ALIAS_STRB = 2122 -AARCH64_INS_ALIAS_LDRH = 2123 -AARCH64_INS_ALIAS_STRH = 2124 -AARCH64_INS_ALIAS_PRFM = 2125 -AARCH64_INS_ALIAS_LDAPURB = 2126 -AARCH64_INS_ALIAS_STLURB = 2127 -AARCH64_INS_ALIAS_LDUR = 2128 -AARCH64_INS_ALIAS_STUR = 2129 -AARCH64_INS_ALIAS_PRFUM = 2130 -AARCH64_INS_ALIAS_LDTR = 2131 -AARCH64_INS_ALIAS_STTR = 2132 -AARCH64_INS_ALIAS_LDP = 2133 -AARCH64_INS_ALIAS_STGP = 2134 -AARCH64_INS_ALIAS_LDNP = 2135 -AARCH64_INS_ALIAS_STNP = 2136 -AARCH64_INS_ALIAS_STG = 2137 -AARCH64_INS_ALIAS_MOV = 2138 -AARCH64_INS_ALIAS_LD1 = 2139 -AARCH64_INS_ALIAS_LD1R = 2140 -AARCH64_INS_ALIAS_STADDLB = 2141 -AARCH64_INS_ALIAS_STADDLH = 2142 -AARCH64_INS_ALIAS_STADDL = 2143 -AARCH64_INS_ALIAS_STADDB = 2144 -AARCH64_INS_ALIAS_STADDH = 2145 -AARCH64_INS_ALIAS_STADD = 2146 -AARCH64_INS_ALIAS_PTRUE = 2147 -AARCH64_INS_ALIAS_PTRUES = 2148 -AARCH64_INS_ALIAS_CNTB = 2149 -AARCH64_INS_ALIAS_SQINCH = 2150 -AARCH64_INS_ALIAS_INCB = 2151 -AARCH64_INS_ALIAS_SQINCB = 2152 -AARCH64_INS_ALIAS_UQINCB = 2153 -AARCH64_INS_ALIAS_ORR = 2154 -AARCH64_INS_ALIAS_DUPM = 2155 -AARCH64_INS_ALIAS_FMOV = 2156 -AARCH64_INS_ALIAS_EOR3 = 2157 -AARCH64_INS_ALIAS_ST1B = 2158 -AARCH64_INS_ALIAS_ST2B = 2159 -AARCH64_INS_ALIAS_ST2Q = 2160 -AARCH64_INS_ALIAS_STNT1B = 2161 -AARCH64_INS_ALIAS_LD1B = 2162 -AARCH64_INS_ALIAS_LDNT1B = 2163 -AARCH64_INS_ALIAS_LD1RQB = 2164 -AARCH64_INS_ALIAS_LD1RB = 2165 -AARCH64_INS_ALIAS_LDFF1B = 2166 -AARCH64_INS_ALIAS_LDNF1B = 2167 -AARCH64_INS_ALIAS_LD2B = 2168 -AARCH64_INS_ALIAS_LD1SB = 2169 -AARCH64_INS_ALIAS_PRFB = 2170 -AARCH64_INS_ALIAS_LDNT1SB = 2171 -AARCH64_INS_ALIAS_LD1ROB = 2172 -AARCH64_INS_ALIAS_LD1Q = 2173 -AARCH64_INS_ALIAS_ST1Q = 2174 -AARCH64_INS_ALIAS_LD1W = 2175 -AARCH64_INS_ALIAS_PMOV = 2176 -AARCH64_INS_ALIAS_SMSTART = 2177 -AARCH64_INS_ALIAS_SMSTOP = 2178 -AARCH64_INS_ALIAS_ZERO = 2179 -AARCH64_INS_ALIAS_MOVT = 2180 -AARCH64_INS_ALIAS_NOP = 2181 -AARCH64_INS_ALIAS_YIELD = 2182 -AARCH64_INS_ALIAS_WFE = 2183 -AARCH64_INS_ALIAS_WFI = 2184 -AARCH64_INS_ALIAS_SEV = 2185 -AARCH64_INS_ALIAS_SEVL = 2186 -AARCH64_INS_ALIAS_DGH = 2187 -AARCH64_INS_ALIAS_ESB = 2188 -AARCH64_INS_ALIAS_CSDB = 2189 -AARCH64_INS_ALIAS_BTI = 2190 -AARCH64_INS_ALIAS_PSB = 2191 -AARCH64_INS_ALIAS_CHKFEAT = 2192 -AARCH64_INS_ALIAS_PACIAZ = 2193 -AARCH64_INS_ALIAS_PACIBZ = 2194 -AARCH64_INS_ALIAS_AUTIAZ = 2195 -AARCH64_INS_ALIAS_AUTIBZ = 2196 -AARCH64_INS_ALIAS_PACIASP = 2197 -AARCH64_INS_ALIAS_PACIBSP = 2198 -AARCH64_INS_ALIAS_AUTIASP = 2199 -AARCH64_INS_ALIAS_AUTIBSP = 2200 -AARCH64_INS_ALIAS_PACIA1716 = 2201 -AARCH64_INS_ALIAS_PACIB1716 = 2202 -AARCH64_INS_ALIAS_AUTIA1716 = 2203 -AARCH64_INS_ALIAS_AUTIB1716 = 2204 -AARCH64_INS_ALIAS_XPACLRI = 2205 -AARCH64_INS_ALIAS_LDRAB = 2206 -AARCH64_INS_ALIAS_PACM = 2207 -AARCH64_INS_ALIAS_CLREX = 2208 -AARCH64_INS_ALIAS_ISB = 2209 -AARCH64_INS_ALIAS_SSBB = 2210 -AARCH64_INS_ALIAS_PSSBB = 2211 -AARCH64_INS_ALIAS_DFB = 2212 -AARCH64_INS_ALIAS_SYS = 2213 -AARCH64_INS_ALIAS_MOVN = 2214 -AARCH64_INS_ALIAS_MOVZ = 2215 -AARCH64_INS_ALIAS_NGC = 2216 -AARCH64_INS_ALIAS_NGCS = 2217 -AARCH64_INS_ALIAS_SUB = 2218 -AARCH64_INS_ALIAS_CMP = 2219 -AARCH64_INS_ALIAS_SUBS = 2220 -AARCH64_INS_ALIAS_NEG = 2221 -AARCH64_INS_ALIAS_NEGS = 2222 -AARCH64_INS_ALIAS_MUL = 2223 -AARCH64_INS_ALIAS_MNEG = 2224 -AARCH64_INS_ALIAS_SMULL = 2225 -AARCH64_INS_ALIAS_SMNEGL = 2226 -AARCH64_INS_ALIAS_UMULL = 2227 -AARCH64_INS_ALIAS_UMNEGL = 2228 -AARCH64_INS_ALIAS_STCLRLB = 2229 -AARCH64_INS_ALIAS_STCLRLH = 2230 -AARCH64_INS_ALIAS_STCLRL = 2231 -AARCH64_INS_ALIAS_STCLRB = 2232 -AARCH64_INS_ALIAS_STCLRH = 2233 -AARCH64_INS_ALIAS_STCLR = 2234 -AARCH64_INS_ALIAS_STEORLB = 2235 -AARCH64_INS_ALIAS_STEORLH = 2236 -AARCH64_INS_ALIAS_STEORL = 2237 -AARCH64_INS_ALIAS_STEORB = 2238 -AARCH64_INS_ALIAS_STEORH = 2239 -AARCH64_INS_ALIAS_STEOR = 2240 -AARCH64_INS_ALIAS_STSETLB = 2241 -AARCH64_INS_ALIAS_STSETLH = 2242 -AARCH64_INS_ALIAS_STSETL = 2243 -AARCH64_INS_ALIAS_STSETB = 2244 -AARCH64_INS_ALIAS_STSETH = 2245 -AARCH64_INS_ALIAS_STSET = 2246 -AARCH64_INS_ALIAS_STSMAXLB = 2247 -AARCH64_INS_ALIAS_STSMAXLH = 2248 -AARCH64_INS_ALIAS_STSMAXL = 2249 -AARCH64_INS_ALIAS_STSMAXB = 2250 -AARCH64_INS_ALIAS_STSMAXH = 2251 -AARCH64_INS_ALIAS_STSMAX = 2252 -AARCH64_INS_ALIAS_STSMINLB = 2253 -AARCH64_INS_ALIAS_STSMINLH = 2254 -AARCH64_INS_ALIAS_STSMINL = 2255 -AARCH64_INS_ALIAS_STSMINB = 2256 -AARCH64_INS_ALIAS_STSMINH = 2257 -AARCH64_INS_ALIAS_STSMIN = 2258 -AARCH64_INS_ALIAS_STUMAXLB = 2259 -AARCH64_INS_ALIAS_STUMAXLH = 2260 -AARCH64_INS_ALIAS_STUMAXL = 2261 -AARCH64_INS_ALIAS_STUMAXB = 2262 -AARCH64_INS_ALIAS_STUMAXH = 2263 -AARCH64_INS_ALIAS_STUMAX = 2264 -AARCH64_INS_ALIAS_STUMINLB = 2265 -AARCH64_INS_ALIAS_STUMINLH = 2266 -AARCH64_INS_ALIAS_STUMINL = 2267 -AARCH64_INS_ALIAS_STUMINB = 2268 -AARCH64_INS_ALIAS_STUMINH = 2269 -AARCH64_INS_ALIAS_STUMIN = 2270 -AARCH64_INS_ALIAS_IRG = 2271 -AARCH64_INS_ALIAS_LDG = 2272 -AARCH64_INS_ALIAS_STZG = 2273 -AARCH64_INS_ALIAS_ST2G = 2274 -AARCH64_INS_ALIAS_STZ2G = 2275 -AARCH64_INS_ALIAS_BICS = 2276 -AARCH64_INS_ALIAS_BIC = 2277 -AARCH64_INS_ALIAS_EON = 2278 -AARCH64_INS_ALIAS_EOR = 2279 -AARCH64_INS_ALIAS_ORN = 2280 -AARCH64_INS_ALIAS_MVN = 2281 -AARCH64_INS_ALIAS_TST = 2282 -AARCH64_INS_ALIAS_ROR = 2283 -AARCH64_INS_ALIAS_ASR = 2284 -AARCH64_INS_ALIAS_SXTB = 2285 -AARCH64_INS_ALIAS_SXTH = 2286 -AARCH64_INS_ALIAS_SXTW = 2287 -AARCH64_INS_ALIAS_LSR = 2288 -AARCH64_INS_ALIAS_UXTB = 2289 -AARCH64_INS_ALIAS_UXTH = 2290 -AARCH64_INS_ALIAS_UXTW = 2291 -AARCH64_INS_ALIAS_CSET = 2292 -AARCH64_INS_ALIAS_CSETM = 2293 -AARCH64_INS_ALIAS_CINC = 2294 -AARCH64_INS_ALIAS_CINV = 2295 -AARCH64_INS_ALIAS_CNEG = 2296 -AARCH64_INS_ALIAS_RET = 2297 -AARCH64_INS_ALIAS_DCPS1 = 2298 -AARCH64_INS_ALIAS_DCPS2 = 2299 -AARCH64_INS_ALIAS_DCPS3 = 2300 -AARCH64_INS_ALIAS_LDPSW = 2301 -AARCH64_INS_ALIAS_LDRSH = 2302 -AARCH64_INS_ALIAS_LDRSB = 2303 -AARCH64_INS_ALIAS_LDRSW = 2304 -AARCH64_INS_ALIAS_LDURH = 2305 -AARCH64_INS_ALIAS_LDURB = 2306 -AARCH64_INS_ALIAS_LDURSH = 2307 -AARCH64_INS_ALIAS_LDURSB = 2308 -AARCH64_INS_ALIAS_LDURSW = 2309 -AARCH64_INS_ALIAS_LDTRH = 2310 -AARCH64_INS_ALIAS_LDTRB = 2311 -AARCH64_INS_ALIAS_LDTRSH = 2312 -AARCH64_INS_ALIAS_LDTRSB = 2313 -AARCH64_INS_ALIAS_LDTRSW = 2314 -AARCH64_INS_ALIAS_STP = 2315 -AARCH64_INS_ALIAS_STURH = 2316 -AARCH64_INS_ALIAS_STURB = 2317 -AARCH64_INS_ALIAS_STLURH = 2318 -AARCH64_INS_ALIAS_LDAPURSB = 2319 -AARCH64_INS_ALIAS_LDAPURH = 2320 -AARCH64_INS_ALIAS_LDAPURSH = 2321 -AARCH64_INS_ALIAS_LDAPURSW = 2322 -AARCH64_INS_ALIAS_STTRH = 2323 -AARCH64_INS_ALIAS_STTRB = 2324 -AARCH64_INS_ALIAS_BIC_4H = 2325 -AARCH64_INS_ALIAS_BIC_8H = 2326 -AARCH64_INS_ALIAS_BIC_2S = 2327 -AARCH64_INS_ALIAS_BIC_4S = 2328 -AARCH64_INS_ALIAS_ORR_4H = 2329 -AARCH64_INS_ALIAS_ORR_8H = 2330 -AARCH64_INS_ALIAS_ORR_2S = 2331 -AARCH64_INS_ALIAS_ORR_4S = 2332 -AARCH64_INS_ALIAS_SXTL_8H = 2333 -AARCH64_INS_ALIAS_SXTL = 2334 -AARCH64_INS_ALIAS_SXTL_4S = 2335 -AARCH64_INS_ALIAS_SXTL_2D = 2336 -AARCH64_INS_ALIAS_SXTL2_8H = 2337 -AARCH64_INS_ALIAS_SXTL2 = 2338 -AARCH64_INS_ALIAS_SXTL2_4S = 2339 -AARCH64_INS_ALIAS_SXTL2_2D = 2340 -AARCH64_INS_ALIAS_UXTL_8H = 2341 -AARCH64_INS_ALIAS_UXTL = 2342 -AARCH64_INS_ALIAS_UXTL_4S = 2343 -AARCH64_INS_ALIAS_UXTL_2D = 2344 -AARCH64_INS_ALIAS_UXTL2_8H = 2345 -AARCH64_INS_ALIAS_UXTL2 = 2346 -AARCH64_INS_ALIAS_UXTL2_4S = 2347 -AARCH64_INS_ALIAS_UXTL2_2D = 2348 -AARCH64_INS_ALIAS_LD2 = 2349 -AARCH64_INS_ALIAS_LD3 = 2350 -AARCH64_INS_ALIAS_LD4 = 2351 -AARCH64_INS_ALIAS_ST1 = 2352 -AARCH64_INS_ALIAS_ST2 = 2353 -AARCH64_INS_ALIAS_ST3 = 2354 -AARCH64_INS_ALIAS_ST4 = 2355 -AARCH64_INS_ALIAS_LD2R = 2356 -AARCH64_INS_ALIAS_LD3R = 2357 -AARCH64_INS_ALIAS_LD4R = 2358 -AARCH64_INS_ALIAS_CLRBHB = 2359 -AARCH64_INS_ALIAS_STILP = 2360 -AARCH64_INS_ALIAS_STL1 = 2361 -AARCH64_INS_ALIAS_SYSP = 2362 -AARCH64_INS_ALIAS_LD1SW = 2363 -AARCH64_INS_ALIAS_LD1H = 2364 -AARCH64_INS_ALIAS_LD1SH = 2365 -AARCH64_INS_ALIAS_LD1D = 2366 -AARCH64_INS_ALIAS_LD1RSW = 2367 -AARCH64_INS_ALIAS_LD1RH = 2368 -AARCH64_INS_ALIAS_LD1RSH = 2369 -AARCH64_INS_ALIAS_LD1RW = 2370 -AARCH64_INS_ALIAS_LD1RSB = 2371 -AARCH64_INS_ALIAS_LD1RD = 2372 -AARCH64_INS_ALIAS_LD1RQH = 2373 -AARCH64_INS_ALIAS_LD1RQW = 2374 -AARCH64_INS_ALIAS_LD1RQD = 2375 -AARCH64_INS_ALIAS_LDNF1SW = 2376 -AARCH64_INS_ALIAS_LDNF1H = 2377 -AARCH64_INS_ALIAS_LDNF1SH = 2378 -AARCH64_INS_ALIAS_LDNF1W = 2379 -AARCH64_INS_ALIAS_LDNF1SB = 2380 -AARCH64_INS_ALIAS_LDNF1D = 2381 -AARCH64_INS_ALIAS_LDFF1SW = 2382 -AARCH64_INS_ALIAS_LDFF1H = 2383 -AARCH64_INS_ALIAS_LDFF1SH = 2384 -AARCH64_INS_ALIAS_LDFF1W = 2385 -AARCH64_INS_ALIAS_LDFF1SB = 2386 -AARCH64_INS_ALIAS_LDFF1D = 2387 -AARCH64_INS_ALIAS_LD3B = 2388 -AARCH64_INS_ALIAS_LD4B = 2389 -AARCH64_INS_ALIAS_LD2H = 2390 -AARCH64_INS_ALIAS_LD3H = 2391 -AARCH64_INS_ALIAS_LD4H = 2392 -AARCH64_INS_ALIAS_LD2W = 2393 -AARCH64_INS_ALIAS_LD3W = 2394 -AARCH64_INS_ALIAS_LD4W = 2395 -AARCH64_INS_ALIAS_LD2D = 2396 -AARCH64_INS_ALIAS_LD3D = 2397 -AARCH64_INS_ALIAS_LD4D = 2398 -AARCH64_INS_ALIAS_LD2Q = 2399 -AARCH64_INS_ALIAS_LD3Q = 2400 -AARCH64_INS_ALIAS_LD4Q = 2401 -AARCH64_INS_ALIAS_LDNT1H = 2402 -AARCH64_INS_ALIAS_LDNT1W = 2403 -AARCH64_INS_ALIAS_LDNT1D = 2404 -AARCH64_INS_ALIAS_ST1H = 2405 -AARCH64_INS_ALIAS_ST1W = 2406 -AARCH64_INS_ALIAS_ST1D = 2407 -AARCH64_INS_ALIAS_ST3B = 2408 -AARCH64_INS_ALIAS_ST4B = 2409 -AARCH64_INS_ALIAS_ST2H = 2410 -AARCH64_INS_ALIAS_ST3H = 2411 -AARCH64_INS_ALIAS_ST4H = 2412 -AARCH64_INS_ALIAS_ST2W = 2413 -AARCH64_INS_ALIAS_ST3W = 2414 -AARCH64_INS_ALIAS_ST4W = 2415 -AARCH64_INS_ALIAS_ST2D = 2416 -AARCH64_INS_ALIAS_ST3D = 2417 -AARCH64_INS_ALIAS_ST4D = 2418 -AARCH64_INS_ALIAS_ST3Q = 2419 -AARCH64_INS_ALIAS_ST4Q = 2420 -AARCH64_INS_ALIAS_STNT1H = 2421 -AARCH64_INS_ALIAS_STNT1W = 2422 -AARCH64_INS_ALIAS_STNT1D = 2423 -AARCH64_INS_ALIAS_PRFH = 2424 -AARCH64_INS_ALIAS_PRFW = 2425 -AARCH64_INS_ALIAS_PRFD = 2426 -AARCH64_INS_ALIAS_CNTH = 2427 -AARCH64_INS_ALIAS_CNTW = 2428 -AARCH64_INS_ALIAS_CNTD = 2429 -AARCH64_INS_ALIAS_DECB = 2430 -AARCH64_INS_ALIAS_INCH = 2431 -AARCH64_INS_ALIAS_DECH = 2432 -AARCH64_INS_ALIAS_INCW = 2433 -AARCH64_INS_ALIAS_DECW = 2434 -AARCH64_INS_ALIAS_INCD = 2435 -AARCH64_INS_ALIAS_DECD = 2436 -AARCH64_INS_ALIAS_SQDECB = 2437 -AARCH64_INS_ALIAS_UQDECB = 2438 -AARCH64_INS_ALIAS_UQINCH = 2439 -AARCH64_INS_ALIAS_SQDECH = 2440 -AARCH64_INS_ALIAS_UQDECH = 2441 -AARCH64_INS_ALIAS_SQINCW = 2442 -AARCH64_INS_ALIAS_UQINCW = 2443 -AARCH64_INS_ALIAS_SQDECW = 2444 -AARCH64_INS_ALIAS_UQDECW = 2445 -AARCH64_INS_ALIAS_SQINCD = 2446 -AARCH64_INS_ALIAS_UQINCD = 2447 -AARCH64_INS_ALIAS_SQDECD = 2448 -AARCH64_INS_ALIAS_UQDECD = 2449 -AARCH64_INS_ALIAS_MOVS = 2450 -AARCH64_INS_ALIAS_NOT = 2451 -AARCH64_INS_ALIAS_NOTS = 2452 -AARCH64_INS_ALIAS_LD1ROH = 2453 -AARCH64_INS_ALIAS_LD1ROW = 2454 -AARCH64_INS_ALIAS_LD1ROD = 2455 -AARCH64_INS_ALIAS_BCAX = 2456 -AARCH64_INS_ALIAS_BSL = 2457 -AARCH64_INS_ALIAS_BSL1N = 2458 -AARCH64_INS_ALIAS_BSL2N = 2459 -AARCH64_INS_ALIAS_NBSL = 2460 -AARCH64_INS_ALIAS_LDNT1SH = 2461 -AARCH64_INS_ALIAS_LDNT1SW = 2462 -AARCH64_INS_ALIAS_CFP = 2463 -AARCH64_INS_ALIAS_DVP = 2464 -AARCH64_INS_ALIAS_COSP = 2465 -AARCH64_INS_ALIAS_CPP = 2466 -AARCH64_INS_ALIAS_IC = 2467 -AARCH64_INS_ALIAS_DC = 2468 -AARCH64_INS_ALIAS_AT = 2469 -AARCH64_INS_ALIAS_TLBI = 2470 -AARCH64_INS_ALIAS_TLBIP = 2471 -AARCH64_INS_ALIAS_RPRFM = 2472 -AARCH64_INS_ALIAS_LSL = 2473 -AARCH64_INS_ALIAS_SBFX = 2474 -AARCH64_INS_ALIAS_UBFX = 2475 -AARCH64_INS_ALIAS_SBFIZ = 2476 -AARCH64_INS_ALIAS_UBFIZ = 2477 -AARCH64_INS_ALIAS_BFC = 2478 -AARCH64_INS_ALIAS_BFI = 2479 -AARCH64_INS_ALIAS_BFXIL = 2480 -AARCH64_INS_ALIAS_END = 2481 + +AARCH64_SME_MATRIX_TILE = 0 +AARCH64_SME_MATRIX_TILE_LIST = 1 +AARCH64_SME_MATRIX_SLICE_REG = 2 +AARCH64_SME_MATRIX_SLICE_OFF = 3 +AARCH64_SME_MATRIX_SLICE_OFF_RANGE = 4 + +AARCH64_SME_OP_INVALID = 0 +AARCH64_SME_OP_TILE = 1 +AARCH64_SME_OP_TILE_VEC = 2 + +AARCH64_INS_INVALID = 0 +AARCH64_INS_ABS = 1 +AARCH64_INS_ADCLB = 2 +AARCH64_INS_ADCLT = 3 +AARCH64_INS_ADCS = 4 +AARCH64_INS_ADC = 5 +AARCH64_INS_ADDG = 6 +AARCH64_INS_ADDHA = 7 +AARCH64_INS_ADDHNB = 8 +AARCH64_INS_ADDHNT = 9 +AARCH64_INS_ADDHN = 10 +AARCH64_INS_ADDHN2 = 11 +AARCH64_INS_ADDPL = 12 +AARCH64_INS_ADDPT = 13 +AARCH64_INS_ADDP = 14 +AARCH64_INS_ADDQV = 15 +AARCH64_INS_ADDSPL = 16 +AARCH64_INS_ADDSVL = 17 +AARCH64_INS_ADDS = 18 +AARCH64_INS_ADDVA = 19 +AARCH64_INS_ADDVL = 20 +AARCH64_INS_ADDV = 21 +AARCH64_INS_ADD = 22 +AARCH64_INS_ADR = 23 +AARCH64_INS_ADRP = 24 +AARCH64_INS_AESD = 25 +AARCH64_INS_AESE = 26 +AARCH64_INS_AESIMC = 27 +AARCH64_INS_AESMC = 28 +AARCH64_INS_ANDQV = 29 +AARCH64_INS_ANDS = 30 +AARCH64_INS_ANDV = 31 +AARCH64_INS_AND = 32 +AARCH64_INS_ASRD = 33 +AARCH64_INS_ASRR = 34 +AARCH64_INS_ASR = 35 +AARCH64_INS_AUTDA = 36 +AARCH64_INS_AUTDB = 37 +AARCH64_INS_AUTDZA = 38 +AARCH64_INS_AUTDZB = 39 +AARCH64_INS_AUTIA = 40 +AARCH64_INS_HINT = 41 +AARCH64_INS_AUTIA171615 = 42 +AARCH64_INS_AUTIASPPC = 43 +AARCH64_INS_AUTIB = 44 +AARCH64_INS_AUTIB171615 = 45 +AARCH64_INS_AUTIBSPPC = 46 +AARCH64_INS_AUTIZA = 47 +AARCH64_INS_AUTIZB = 48 +AARCH64_INS_AXFLAG = 49 +AARCH64_INS_B = 50 +AARCH64_INS_BCAX = 51 +AARCH64_INS_BC = 52 +AARCH64_INS_BDEP = 53 +AARCH64_INS_BEXT = 54 +AARCH64_INS_BFDOT = 55 +AARCH64_INS_BF1CVTL2 = 56 +AARCH64_INS_BF1CVTLT = 57 +AARCH64_INS_BF1CVTL = 58 +AARCH64_INS_BF1CVT = 59 +AARCH64_INS_BF2CVTL2 = 60 +AARCH64_INS_BF2CVTLT = 61 +AARCH64_INS_BF2CVTL = 62 +AARCH64_INS_BF2CVT = 63 +AARCH64_INS_BFADD = 64 +AARCH64_INS_BFCLAMP = 65 +AARCH64_INS_BFCVT = 66 +AARCH64_INS_BFCVTN = 67 +AARCH64_INS_BFCVTN2 = 68 +AARCH64_INS_BFCVTNT = 69 +AARCH64_INS_BFMAXNM = 70 +AARCH64_INS_BFMAX = 71 +AARCH64_INS_BFMINNM = 72 +AARCH64_INS_BFMIN = 73 +AARCH64_INS_BFMLALB = 74 +AARCH64_INS_BFMLALT = 75 +AARCH64_INS_BFMLAL = 76 +AARCH64_INS_BFMLA = 77 +AARCH64_INS_BFMLSLB = 78 +AARCH64_INS_BFMLSLT = 79 +AARCH64_INS_BFMLSL = 80 +AARCH64_INS_BFMLS = 81 +AARCH64_INS_BFMMLA = 82 +AARCH64_INS_BFMOPA = 83 +AARCH64_INS_BFMOPS = 84 +AARCH64_INS_BFMUL = 85 +AARCH64_INS_BFM = 86 +AARCH64_INS_BFSUB = 87 +AARCH64_INS_BFVDOT = 88 +AARCH64_INS_BGRP = 89 +AARCH64_INS_BICS = 90 +AARCH64_INS_BIC = 91 +AARCH64_INS_BIF = 92 +AARCH64_INS_BIT = 93 +AARCH64_INS_BL = 94 +AARCH64_INS_BLR = 95 +AARCH64_INS_BLRAA = 96 +AARCH64_INS_BLRAAZ = 97 +AARCH64_INS_BLRAB = 98 +AARCH64_INS_BLRABZ = 99 +AARCH64_INS_BMOPA = 100 +AARCH64_INS_BMOPS = 101 +AARCH64_INS_BR = 102 +AARCH64_INS_BRAA = 103 +AARCH64_INS_BRAAZ = 104 +AARCH64_INS_BRAB = 105 +AARCH64_INS_BRABZ = 106 +AARCH64_INS_BRB = 107 +AARCH64_INS_BRK = 108 +AARCH64_INS_BRKAS = 109 +AARCH64_INS_BRKA = 110 +AARCH64_INS_BRKBS = 111 +AARCH64_INS_BRKB = 112 +AARCH64_INS_BRKNS = 113 +AARCH64_INS_BRKN = 114 +AARCH64_INS_BRKPAS = 115 +AARCH64_INS_BRKPA = 116 +AARCH64_INS_BRKPBS = 117 +AARCH64_INS_BRKPB = 118 +AARCH64_INS_BSL1N = 119 +AARCH64_INS_BSL2N = 120 +AARCH64_INS_BSL = 121 +AARCH64_INS_CADD = 122 +AARCH64_INS_CASAB = 123 +AARCH64_INS_CASAH = 124 +AARCH64_INS_CASALB = 125 +AARCH64_INS_CASALH = 126 +AARCH64_INS_CASAL = 127 +AARCH64_INS_CASA = 128 +AARCH64_INS_CASB = 129 +AARCH64_INS_CASH = 130 +AARCH64_INS_CASLB = 131 +AARCH64_INS_CASLH = 132 +AARCH64_INS_CASL = 133 +AARCH64_INS_CASPAL = 134 +AARCH64_INS_CASPA = 135 +AARCH64_INS_CASPL = 136 +AARCH64_INS_CASP = 137 +AARCH64_INS_CAS = 138 +AARCH64_INS_CBNZ = 139 +AARCH64_INS_CBZ = 140 +AARCH64_INS_CCMN = 141 +AARCH64_INS_CCMP = 142 +AARCH64_INS_CDOT = 143 +AARCH64_INS_CFINV = 144 +AARCH64_INS_CLASTA = 145 +AARCH64_INS_CLASTB = 146 +AARCH64_INS_CLREX = 147 +AARCH64_INS_CLS = 148 +AARCH64_INS_CLZ = 149 +AARCH64_INS_CMEQ = 150 +AARCH64_INS_CMGE = 151 +AARCH64_INS_CMGT = 152 +AARCH64_INS_CMHI = 153 +AARCH64_INS_CMHS = 154 +AARCH64_INS_CMLA = 155 +AARCH64_INS_CMLE = 156 +AARCH64_INS_CMLT = 157 +AARCH64_INS_CMPEQ = 158 +AARCH64_INS_CMPGE = 159 +AARCH64_INS_CMPGT = 160 +AARCH64_INS_CMPHI = 161 +AARCH64_INS_CMPHS = 162 +AARCH64_INS_CMPLE = 163 +AARCH64_INS_CMPLO = 164 +AARCH64_INS_CMPLS = 165 +AARCH64_INS_CMPLT = 166 +AARCH64_INS_CMPNE = 167 +AARCH64_INS_CMTST = 168 +AARCH64_INS_CNOT = 169 +AARCH64_INS_CNTB = 170 +AARCH64_INS_CNTD = 171 +AARCH64_INS_CNTH = 172 +AARCH64_INS_CNTP = 173 +AARCH64_INS_CNTW = 174 +AARCH64_INS_CNT = 175 +AARCH64_INS_COMPACT = 176 +AARCH64_INS_CPYE = 177 +AARCH64_INS_CPYEN = 178 +AARCH64_INS_CPYERN = 179 +AARCH64_INS_CPYERT = 180 +AARCH64_INS_CPYERTN = 181 +AARCH64_INS_CPYERTRN = 182 +AARCH64_INS_CPYERTWN = 183 +AARCH64_INS_CPYET = 184 +AARCH64_INS_CPYETN = 185 +AARCH64_INS_CPYETRN = 186 +AARCH64_INS_CPYETWN = 187 +AARCH64_INS_CPYEWN = 188 +AARCH64_INS_CPYEWT = 189 +AARCH64_INS_CPYEWTN = 190 +AARCH64_INS_CPYEWTRN = 191 +AARCH64_INS_CPYEWTWN = 192 +AARCH64_INS_CPYFE = 193 +AARCH64_INS_CPYFEN = 194 +AARCH64_INS_CPYFERN = 195 +AARCH64_INS_CPYFERT = 196 +AARCH64_INS_CPYFERTN = 197 +AARCH64_INS_CPYFERTRN = 198 +AARCH64_INS_CPYFERTWN = 199 +AARCH64_INS_CPYFET = 200 +AARCH64_INS_CPYFETN = 201 +AARCH64_INS_CPYFETRN = 202 +AARCH64_INS_CPYFETWN = 203 +AARCH64_INS_CPYFEWN = 204 +AARCH64_INS_CPYFEWT = 205 +AARCH64_INS_CPYFEWTN = 206 +AARCH64_INS_CPYFEWTRN = 207 +AARCH64_INS_CPYFEWTWN = 208 +AARCH64_INS_CPYFM = 209 +AARCH64_INS_CPYFMN = 210 +AARCH64_INS_CPYFMRN = 211 +AARCH64_INS_CPYFMRT = 212 +AARCH64_INS_CPYFMRTN = 213 +AARCH64_INS_CPYFMRTRN = 214 +AARCH64_INS_CPYFMRTWN = 215 +AARCH64_INS_CPYFMT = 216 +AARCH64_INS_CPYFMTN = 217 +AARCH64_INS_CPYFMTRN = 218 +AARCH64_INS_CPYFMTWN = 219 +AARCH64_INS_CPYFMWN = 220 +AARCH64_INS_CPYFMWT = 221 +AARCH64_INS_CPYFMWTN = 222 +AARCH64_INS_CPYFMWTRN = 223 +AARCH64_INS_CPYFMWTWN = 224 +AARCH64_INS_CPYFP = 225 +AARCH64_INS_CPYFPN = 226 +AARCH64_INS_CPYFPRN = 227 +AARCH64_INS_CPYFPRT = 228 +AARCH64_INS_CPYFPRTN = 229 +AARCH64_INS_CPYFPRTRN = 230 +AARCH64_INS_CPYFPRTWN = 231 +AARCH64_INS_CPYFPT = 232 +AARCH64_INS_CPYFPTN = 233 +AARCH64_INS_CPYFPTRN = 234 +AARCH64_INS_CPYFPTWN = 235 +AARCH64_INS_CPYFPWN = 236 +AARCH64_INS_CPYFPWT = 237 +AARCH64_INS_CPYFPWTN = 238 +AARCH64_INS_CPYFPWTRN = 239 +AARCH64_INS_CPYFPWTWN = 240 +AARCH64_INS_CPYM = 241 +AARCH64_INS_CPYMN = 242 +AARCH64_INS_CPYMRN = 243 +AARCH64_INS_CPYMRT = 244 +AARCH64_INS_CPYMRTN = 245 +AARCH64_INS_CPYMRTRN = 246 +AARCH64_INS_CPYMRTWN = 247 +AARCH64_INS_CPYMT = 248 +AARCH64_INS_CPYMTN = 249 +AARCH64_INS_CPYMTRN = 250 +AARCH64_INS_CPYMTWN = 251 +AARCH64_INS_CPYMWN = 252 +AARCH64_INS_CPYMWT = 253 +AARCH64_INS_CPYMWTN = 254 +AARCH64_INS_CPYMWTRN = 255 +AARCH64_INS_CPYMWTWN = 256 +AARCH64_INS_CPYP = 257 +AARCH64_INS_CPYPN = 258 +AARCH64_INS_CPYPRN = 259 +AARCH64_INS_CPYPRT = 260 +AARCH64_INS_CPYPRTN = 261 +AARCH64_INS_CPYPRTRN = 262 +AARCH64_INS_CPYPRTWN = 263 +AARCH64_INS_CPYPT = 264 +AARCH64_INS_CPYPTN = 265 +AARCH64_INS_CPYPTRN = 266 +AARCH64_INS_CPYPTWN = 267 +AARCH64_INS_CPYPWN = 268 +AARCH64_INS_CPYPWT = 269 +AARCH64_INS_CPYPWTN = 270 +AARCH64_INS_CPYPWTRN = 271 +AARCH64_INS_CPYPWTWN = 272 +AARCH64_INS_CPY = 273 +AARCH64_INS_CRC32B = 274 +AARCH64_INS_CRC32CB = 275 +AARCH64_INS_CRC32CH = 276 +AARCH64_INS_CRC32CW = 277 +AARCH64_INS_CRC32CX = 278 +AARCH64_INS_CRC32H = 279 +AARCH64_INS_CRC32W = 280 +AARCH64_INS_CRC32X = 281 +AARCH64_INS_CSEL = 282 +AARCH64_INS_CSINC = 283 +AARCH64_INS_CSINV = 284 +AARCH64_INS_CSNEG = 285 +AARCH64_INS_CTERMEQ = 286 +AARCH64_INS_CTERMNE = 287 +AARCH64_INS_CTZ = 288 +AARCH64_INS_DCPS1 = 289 +AARCH64_INS_DCPS2 = 290 +AARCH64_INS_DCPS3 = 291 +AARCH64_INS_DECB = 292 +AARCH64_INS_DECD = 293 +AARCH64_INS_DECH = 294 +AARCH64_INS_DECP = 295 +AARCH64_INS_DECW = 296 +AARCH64_INS_DMB = 297 +AARCH64_INS_DRPS = 298 +AARCH64_INS_DSB = 299 +AARCH64_INS_DUPM = 300 +AARCH64_INS_DUPQ = 301 +AARCH64_INS_DUP = 302 +AARCH64_INS_MOV = 303 +AARCH64_INS_EON = 304 +AARCH64_INS_EOR3 = 305 +AARCH64_INS_EORBT = 306 +AARCH64_INS_EORQV = 307 +AARCH64_INS_EORS = 308 +AARCH64_INS_EORTB = 309 +AARCH64_INS_EORV = 310 +AARCH64_INS_EOR = 311 +AARCH64_INS_ERET = 312 +AARCH64_INS_ERETAA = 313 +AARCH64_INS_ERETAB = 314 +AARCH64_INS_EXTQ = 315 +AARCH64_INS_MOVA = 316 +AARCH64_INS_EXTR = 317 +AARCH64_INS_EXT = 318 +AARCH64_INS_F1CVTL2 = 319 +AARCH64_INS_F1CVTLT = 320 +AARCH64_INS_F1CVTL = 321 +AARCH64_INS_F1CVT = 322 +AARCH64_INS_F2CVTL2 = 323 +AARCH64_INS_F2CVTLT = 324 +AARCH64_INS_F2CVTL = 325 +AARCH64_INS_F2CVT = 326 +AARCH64_INS_FABD = 327 +AARCH64_INS_FABS = 328 +AARCH64_INS_FACGE = 329 +AARCH64_INS_FACGT = 330 +AARCH64_INS_FADDA = 331 +AARCH64_INS_FADD = 332 +AARCH64_INS_FADDP = 333 +AARCH64_INS_FADDQV = 334 +AARCH64_INS_FADDV = 335 +AARCH64_INS_FAMAX = 336 +AARCH64_INS_FAMIN = 337 +AARCH64_INS_FCADD = 338 +AARCH64_INS_FCCMP = 339 +AARCH64_INS_FCCMPE = 340 +AARCH64_INS_FCLAMP = 341 +AARCH64_INS_FCMEQ = 342 +AARCH64_INS_FCMGE = 343 +AARCH64_INS_FCMGT = 344 +AARCH64_INS_FCMLA = 345 +AARCH64_INS_FCMLE = 346 +AARCH64_INS_FCMLT = 347 +AARCH64_INS_FCMNE = 348 +AARCH64_INS_FCMP = 349 +AARCH64_INS_FCMPE = 350 +AARCH64_INS_FCMUO = 351 +AARCH64_INS_FCPY = 352 +AARCH64_INS_FCSEL = 353 +AARCH64_INS_FCVTAS = 354 +AARCH64_INS_FCVTAU = 355 +AARCH64_INS_FCVT = 356 +AARCH64_INS_FCVTLT = 357 +AARCH64_INS_FCVTL = 358 +AARCH64_INS_FCVTL2 = 359 +AARCH64_INS_FCVTMS = 360 +AARCH64_INS_FCVTMU = 361 +AARCH64_INS_FCVTNB = 362 +AARCH64_INS_FCVTNS = 363 +AARCH64_INS_FCVTNT = 364 +AARCH64_INS_FCVTNU = 365 +AARCH64_INS_FCVTN = 366 +AARCH64_INS_FCVTN2 = 367 +AARCH64_INS_FCVTPS = 368 +AARCH64_INS_FCVTPU = 369 +AARCH64_INS_FCVTXNT = 370 +AARCH64_INS_FCVTXN = 371 +AARCH64_INS_FCVTXN2 = 372 +AARCH64_INS_FCVTX = 373 +AARCH64_INS_FCVTZS = 374 +AARCH64_INS_FCVTZU = 375 +AARCH64_INS_FDIV = 376 +AARCH64_INS_FDIVR = 377 +AARCH64_INS_FDOT = 378 +AARCH64_INS_FDUP = 379 +AARCH64_INS_FEXPA = 380 +AARCH64_INS_FJCVTZS = 381 +AARCH64_INS_FLOGB = 382 +AARCH64_INS_FMADD = 383 +AARCH64_INS_FMAD = 384 +AARCH64_INS_FMAX = 385 +AARCH64_INS_FMAXNM = 386 +AARCH64_INS_FMAXNMP = 387 +AARCH64_INS_FMAXNMQV = 388 +AARCH64_INS_FMAXNMV = 389 +AARCH64_INS_FMAXP = 390 +AARCH64_INS_FMAXQV = 391 +AARCH64_INS_FMAXV = 392 +AARCH64_INS_FMIN = 393 +AARCH64_INS_FMINNM = 394 +AARCH64_INS_FMINNMP = 395 +AARCH64_INS_FMINNMQV = 396 +AARCH64_INS_FMINNMV = 397 +AARCH64_INS_FMINP = 398 +AARCH64_INS_FMINQV = 399 +AARCH64_INS_FMINV = 400 +AARCH64_INS_FMLAL2 = 401 +AARCH64_INS_FMLALB = 402 +AARCH64_INS_FMLALLBB = 403 +AARCH64_INS_FMLALLBT = 404 +AARCH64_INS_FMLALLTB = 405 +AARCH64_INS_FMLALLTT = 406 +AARCH64_INS_FMLALL = 407 +AARCH64_INS_FMLALT = 408 +AARCH64_INS_FMLAL = 409 +AARCH64_INS_FMLA = 410 +AARCH64_INS_FMLSL2 = 411 +AARCH64_INS_FMLSLB = 412 +AARCH64_INS_FMLSLT = 413 +AARCH64_INS_FMLSL = 414 +AARCH64_INS_FMLS = 415 +AARCH64_INS_FMMLA = 416 +AARCH64_INS_FMOPA = 417 +AARCH64_INS_FMOPS = 418 +AARCH64_INS_FMOV = 419 +AARCH64_INS_FMSB = 420 +AARCH64_INS_FMSUB = 421 +AARCH64_INS_FMUL = 422 +AARCH64_INS_FMULX = 423 +AARCH64_INS_FNEG = 424 +AARCH64_INS_FNMADD = 425 +AARCH64_INS_FNMAD = 426 +AARCH64_INS_FNMLA = 427 +AARCH64_INS_FNMLS = 428 +AARCH64_INS_FNMSB = 429 +AARCH64_INS_FNMSUB = 430 +AARCH64_INS_FNMUL = 431 +AARCH64_INS_FRECPE = 432 +AARCH64_INS_FRECPS = 433 +AARCH64_INS_FRECPX = 434 +AARCH64_INS_FRINT32X = 435 +AARCH64_INS_FRINT32Z = 436 +AARCH64_INS_FRINT64X = 437 +AARCH64_INS_FRINT64Z = 438 +AARCH64_INS_FRINTA = 439 +AARCH64_INS_FRINTI = 440 +AARCH64_INS_FRINTM = 441 +AARCH64_INS_FRINTN = 442 +AARCH64_INS_FRINTP = 443 +AARCH64_INS_FRINTX = 444 +AARCH64_INS_FRINTZ = 445 +AARCH64_INS_FRSQRTE = 446 +AARCH64_INS_FRSQRTS = 447 +AARCH64_INS_FSCALE = 448 +AARCH64_INS_FSQRT = 449 +AARCH64_INS_FSUB = 450 +AARCH64_INS_FSUBR = 451 +AARCH64_INS_FTMAD = 452 +AARCH64_INS_FTSMUL = 453 +AARCH64_INS_FTSSEL = 454 +AARCH64_INS_FVDOTB = 455 +AARCH64_INS_FVDOTT = 456 +AARCH64_INS_FVDOT = 457 +AARCH64_INS_GCSPOPCX = 458 +AARCH64_INS_GCSPOPM = 459 +AARCH64_INS_GCSPOPX = 460 +AARCH64_INS_GCSPUSHM = 461 +AARCH64_INS_GCSPUSHX = 462 +AARCH64_INS_GCSSS1 = 463 +AARCH64_INS_GCSSS2 = 464 +AARCH64_INS_GCSSTR = 465 +AARCH64_INS_GCSSTTR = 466 +AARCH64_INS_LD1B = 467 +AARCH64_INS_LD1D = 468 +AARCH64_INS_LD1H = 469 +AARCH64_INS_LD1Q = 470 +AARCH64_INS_LD1SB = 471 +AARCH64_INS_LD1SH = 472 +AARCH64_INS_LD1SW = 473 +AARCH64_INS_LD1W = 474 +AARCH64_INS_LDFF1B = 475 +AARCH64_INS_LDFF1D = 476 +AARCH64_INS_LDFF1H = 477 +AARCH64_INS_LDFF1SB = 478 +AARCH64_INS_LDFF1SH = 479 +AARCH64_INS_LDFF1SW = 480 +AARCH64_INS_LDFF1W = 481 +AARCH64_INS_GMI = 482 +AARCH64_INS_HISTCNT = 483 +AARCH64_INS_HISTSEG = 484 +AARCH64_INS_HLT = 485 +AARCH64_INS_HVC = 486 +AARCH64_INS_INCB = 487 +AARCH64_INS_INCD = 488 +AARCH64_INS_INCH = 489 +AARCH64_INS_INCP = 490 +AARCH64_INS_INCW = 491 +AARCH64_INS_INDEX = 492 +AARCH64_INS_INSR = 493 +AARCH64_INS_INS = 494 +AARCH64_INS_IRG = 495 +AARCH64_INS_ISB = 496 +AARCH64_INS_LASTA = 497 +AARCH64_INS_LASTB = 498 +AARCH64_INS_LD1 = 499 +AARCH64_INS_LD1RB = 500 +AARCH64_INS_LD1RD = 501 +AARCH64_INS_LD1RH = 502 +AARCH64_INS_LD1ROB = 503 +AARCH64_INS_LD1ROD = 504 +AARCH64_INS_LD1ROH = 505 +AARCH64_INS_LD1ROW = 506 +AARCH64_INS_LD1RQB = 507 +AARCH64_INS_LD1RQD = 508 +AARCH64_INS_LD1RQH = 509 +AARCH64_INS_LD1RQW = 510 +AARCH64_INS_LD1RSB = 511 +AARCH64_INS_LD1RSH = 512 +AARCH64_INS_LD1RSW = 513 +AARCH64_INS_LD1RW = 514 +AARCH64_INS_LD1R = 515 +AARCH64_INS_LD2B = 516 +AARCH64_INS_LD2D = 517 +AARCH64_INS_LD2H = 518 +AARCH64_INS_LD2Q = 519 +AARCH64_INS_LD2R = 520 +AARCH64_INS_LD2 = 521 +AARCH64_INS_LD2W = 522 +AARCH64_INS_LD3B = 523 +AARCH64_INS_LD3D = 524 +AARCH64_INS_LD3H = 525 +AARCH64_INS_LD3Q = 526 +AARCH64_INS_LD3R = 527 +AARCH64_INS_LD3 = 528 +AARCH64_INS_LD3W = 529 +AARCH64_INS_LD4B = 530 +AARCH64_INS_LD4D = 531 +AARCH64_INS_LD4 = 532 +AARCH64_INS_LD4H = 533 +AARCH64_INS_LD4Q = 534 +AARCH64_INS_LD4R = 535 +AARCH64_INS_LD4W = 536 +AARCH64_INS_LD64B = 537 +AARCH64_INS_LDADDAB = 538 +AARCH64_INS_LDADDAH = 539 +AARCH64_INS_LDADDALB = 540 +AARCH64_INS_LDADDALH = 541 +AARCH64_INS_LDADDAL = 542 +AARCH64_INS_LDADDA = 543 +AARCH64_INS_LDADDB = 544 +AARCH64_INS_LDADDH = 545 +AARCH64_INS_LDADDLB = 546 +AARCH64_INS_LDADDLH = 547 +AARCH64_INS_LDADDL = 548 +AARCH64_INS_LDADD = 549 +AARCH64_INS_LDAP1 = 550 +AARCH64_INS_LDAPRB = 551 +AARCH64_INS_LDAPRH = 552 +AARCH64_INS_LDAPR = 553 +AARCH64_INS_LDAPURB = 554 +AARCH64_INS_LDAPURH = 555 +AARCH64_INS_LDAPURSB = 556 +AARCH64_INS_LDAPURSH = 557 +AARCH64_INS_LDAPURSW = 558 +AARCH64_INS_LDAPUR = 559 +AARCH64_INS_LDARB = 560 +AARCH64_INS_LDARH = 561 +AARCH64_INS_LDAR = 562 +AARCH64_INS_LDAXP = 563 +AARCH64_INS_LDAXRB = 564 +AARCH64_INS_LDAXRH = 565 +AARCH64_INS_LDAXR = 566 +AARCH64_INS_LDCLRAB = 567 +AARCH64_INS_LDCLRAH = 568 +AARCH64_INS_LDCLRALB = 569 +AARCH64_INS_LDCLRALH = 570 +AARCH64_INS_LDCLRAL = 571 +AARCH64_INS_LDCLRA = 572 +AARCH64_INS_LDCLRB = 573 +AARCH64_INS_LDCLRH = 574 +AARCH64_INS_LDCLRLB = 575 +AARCH64_INS_LDCLRLH = 576 +AARCH64_INS_LDCLRL = 577 +AARCH64_INS_LDCLRP = 578 +AARCH64_INS_LDCLRPA = 579 +AARCH64_INS_LDCLRPAL = 580 +AARCH64_INS_LDCLRPL = 581 +AARCH64_INS_LDCLR = 582 +AARCH64_INS_LDEORAB = 583 +AARCH64_INS_LDEORAH = 584 +AARCH64_INS_LDEORALB = 585 +AARCH64_INS_LDEORALH = 586 +AARCH64_INS_LDEORAL = 587 +AARCH64_INS_LDEORA = 588 +AARCH64_INS_LDEORB = 589 +AARCH64_INS_LDEORH = 590 +AARCH64_INS_LDEORLB = 591 +AARCH64_INS_LDEORLH = 592 +AARCH64_INS_LDEORL = 593 +AARCH64_INS_LDEOR = 594 +AARCH64_INS_LDG = 595 +AARCH64_INS_LDGM = 596 +AARCH64_INS_LDIAPP = 597 +AARCH64_INS_LDLARB = 598 +AARCH64_INS_LDLARH = 599 +AARCH64_INS_LDLAR = 600 +AARCH64_INS_LDNF1B = 601 +AARCH64_INS_LDNF1D = 602 +AARCH64_INS_LDNF1H = 603 +AARCH64_INS_LDNF1SB = 604 +AARCH64_INS_LDNF1SH = 605 +AARCH64_INS_LDNF1SW = 606 +AARCH64_INS_LDNF1W = 607 +AARCH64_INS_LDNP = 608 +AARCH64_INS_LDNT1B = 609 +AARCH64_INS_LDNT1D = 610 +AARCH64_INS_LDNT1H = 611 +AARCH64_INS_LDNT1SB = 612 +AARCH64_INS_LDNT1SH = 613 +AARCH64_INS_LDNT1SW = 614 +AARCH64_INS_LDNT1W = 615 +AARCH64_INS_LDP = 616 +AARCH64_INS_LDPSW = 617 +AARCH64_INS_LDRAA = 618 +AARCH64_INS_LDRAB = 619 +AARCH64_INS_LDRB = 620 +AARCH64_INS_LDR = 621 +AARCH64_INS_LDRH = 622 +AARCH64_INS_LDRSB = 623 +AARCH64_INS_LDRSH = 624 +AARCH64_INS_LDRSW = 625 +AARCH64_INS_LDSETAB = 626 +AARCH64_INS_LDSETAH = 627 +AARCH64_INS_LDSETALB = 628 +AARCH64_INS_LDSETALH = 629 +AARCH64_INS_LDSETAL = 630 +AARCH64_INS_LDSETA = 631 +AARCH64_INS_LDSETB = 632 +AARCH64_INS_LDSETH = 633 +AARCH64_INS_LDSETLB = 634 +AARCH64_INS_LDSETLH = 635 +AARCH64_INS_LDSETL = 636 +AARCH64_INS_LDSETP = 637 +AARCH64_INS_LDSETPA = 638 +AARCH64_INS_LDSETPAL = 639 +AARCH64_INS_LDSETPL = 640 +AARCH64_INS_LDSET = 641 +AARCH64_INS_LDSMAXAB = 642 +AARCH64_INS_LDSMAXAH = 643 +AARCH64_INS_LDSMAXALB = 644 +AARCH64_INS_LDSMAXALH = 645 +AARCH64_INS_LDSMAXAL = 646 +AARCH64_INS_LDSMAXA = 647 +AARCH64_INS_LDSMAXB = 648 +AARCH64_INS_LDSMAXH = 649 +AARCH64_INS_LDSMAXLB = 650 +AARCH64_INS_LDSMAXLH = 651 +AARCH64_INS_LDSMAXL = 652 +AARCH64_INS_LDSMAX = 653 +AARCH64_INS_LDSMINAB = 654 +AARCH64_INS_LDSMINAH = 655 +AARCH64_INS_LDSMINALB = 656 +AARCH64_INS_LDSMINALH = 657 +AARCH64_INS_LDSMINAL = 658 +AARCH64_INS_LDSMINA = 659 +AARCH64_INS_LDSMINB = 660 +AARCH64_INS_LDSMINH = 661 +AARCH64_INS_LDSMINLB = 662 +AARCH64_INS_LDSMINLH = 663 +AARCH64_INS_LDSMINL = 664 +AARCH64_INS_LDSMIN = 665 +AARCH64_INS_LDTRB = 666 +AARCH64_INS_LDTRH = 667 +AARCH64_INS_LDTRSB = 668 +AARCH64_INS_LDTRSH = 669 +AARCH64_INS_LDTRSW = 670 +AARCH64_INS_LDTR = 671 +AARCH64_INS_LDUMAXAB = 672 +AARCH64_INS_LDUMAXAH = 673 +AARCH64_INS_LDUMAXALB = 674 +AARCH64_INS_LDUMAXALH = 675 +AARCH64_INS_LDUMAXAL = 676 +AARCH64_INS_LDUMAXA = 677 +AARCH64_INS_LDUMAXB = 678 +AARCH64_INS_LDUMAXH = 679 +AARCH64_INS_LDUMAXLB = 680 +AARCH64_INS_LDUMAXLH = 681 +AARCH64_INS_LDUMAXL = 682 +AARCH64_INS_LDUMAX = 683 +AARCH64_INS_LDUMINAB = 684 +AARCH64_INS_LDUMINAH = 685 +AARCH64_INS_LDUMINALB = 686 +AARCH64_INS_LDUMINALH = 687 +AARCH64_INS_LDUMINAL = 688 +AARCH64_INS_LDUMINA = 689 +AARCH64_INS_LDUMINB = 690 +AARCH64_INS_LDUMINH = 691 +AARCH64_INS_LDUMINLB = 692 +AARCH64_INS_LDUMINLH = 693 +AARCH64_INS_LDUMINL = 694 +AARCH64_INS_LDUMIN = 695 +AARCH64_INS_LDURB = 696 +AARCH64_INS_LDUR = 697 +AARCH64_INS_LDURH = 698 +AARCH64_INS_LDURSB = 699 +AARCH64_INS_LDURSH = 700 +AARCH64_INS_LDURSW = 701 +AARCH64_INS_LDXP = 702 +AARCH64_INS_LDXRB = 703 +AARCH64_INS_LDXRH = 704 +AARCH64_INS_LDXR = 705 +AARCH64_INS_LSLR = 706 +AARCH64_INS_LSL = 707 +AARCH64_INS_LSRR = 708 +AARCH64_INS_LSR = 709 +AARCH64_INS_LUTI2 = 710 +AARCH64_INS_LUTI4 = 711 +AARCH64_INS_MADDPT = 712 +AARCH64_INS_MADD = 713 +AARCH64_INS_MADPT = 714 +AARCH64_INS_MAD = 715 +AARCH64_INS_MATCH = 716 +AARCH64_INS_MLAPT = 717 +AARCH64_INS_MLA = 718 +AARCH64_INS_MLS = 719 +AARCH64_INS_SETGE = 720 +AARCH64_INS_SETGEN = 721 +AARCH64_INS_SETGET = 722 +AARCH64_INS_SETGETN = 723 +AARCH64_INS_MOVAZ = 724 +AARCH64_INS_MOVI = 725 +AARCH64_INS_MOVK = 726 +AARCH64_INS_MOVN = 727 +AARCH64_INS_MOVPRFX = 728 +AARCH64_INS_MOVT = 729 +AARCH64_INS_MOVZ = 730 +AARCH64_INS_MRRS = 731 +AARCH64_INS_MRS = 732 +AARCH64_INS_MSB = 733 +AARCH64_INS_MSR = 734 +AARCH64_INS_MSRR = 735 +AARCH64_INS_MSUBPT = 736 +AARCH64_INS_MSUB = 737 +AARCH64_INS_MUL = 738 +AARCH64_INS_MVNI = 739 +AARCH64_INS_NANDS = 740 +AARCH64_INS_NAND = 741 +AARCH64_INS_NBSL = 742 +AARCH64_INS_NEG = 743 +AARCH64_INS_NMATCH = 744 +AARCH64_INS_NORS = 745 +AARCH64_INS_NOR = 746 +AARCH64_INS_NOT = 747 +AARCH64_INS_ORNS = 748 +AARCH64_INS_ORN = 749 +AARCH64_INS_ORQV = 750 +AARCH64_INS_ORRS = 751 +AARCH64_INS_ORR = 752 +AARCH64_INS_ORV = 753 +AARCH64_INS_PACDA = 754 +AARCH64_INS_PACDB = 755 +AARCH64_INS_PACDZA = 756 +AARCH64_INS_PACDZB = 757 +AARCH64_INS_PACGA = 758 +AARCH64_INS_PACIA = 759 +AARCH64_INS_PACIA171615 = 760 +AARCH64_INS_PACIASPPC = 761 +AARCH64_INS_PACIB = 762 +AARCH64_INS_PACIB171615 = 763 +AARCH64_INS_PACIBSPPC = 764 +AARCH64_INS_PACIZA = 765 +AARCH64_INS_PACIZB = 766 +AARCH64_INS_PACNBIASPPC = 767 +AARCH64_INS_PACNBIBSPPC = 768 +AARCH64_INS_PEXT = 769 +AARCH64_INS_PFALSE = 770 +AARCH64_INS_PFIRST = 771 +AARCH64_INS_PMOV = 772 +AARCH64_INS_PMULLB = 773 +AARCH64_INS_PMULLT = 774 +AARCH64_INS_PMULL2 = 775 +AARCH64_INS_PMULL = 776 +AARCH64_INS_PMUL = 777 +AARCH64_INS_PNEXT = 778 +AARCH64_INS_PRFB = 779 +AARCH64_INS_PRFD = 780 +AARCH64_INS_PRFH = 781 +AARCH64_INS_PRFM = 782 +AARCH64_INS_PRFUM = 783 +AARCH64_INS_PRFW = 784 +AARCH64_INS_PSEL = 785 +AARCH64_INS_PTEST = 786 +AARCH64_INS_PTRUES = 787 +AARCH64_INS_PTRUE = 788 +AARCH64_INS_PUNPKHI = 789 +AARCH64_INS_PUNPKLO = 790 +AARCH64_INS_RADDHNB = 791 +AARCH64_INS_RADDHNT = 792 +AARCH64_INS_RADDHN = 793 +AARCH64_INS_RADDHN2 = 794 +AARCH64_INS_RAX1 = 795 +AARCH64_INS_RBIT = 796 +AARCH64_INS_RCWCAS = 797 +AARCH64_INS_RCWCASA = 798 +AARCH64_INS_RCWCASAL = 799 +AARCH64_INS_RCWCASL = 800 +AARCH64_INS_RCWCASP = 801 +AARCH64_INS_RCWCASPA = 802 +AARCH64_INS_RCWCASPAL = 803 +AARCH64_INS_RCWCASPL = 804 +AARCH64_INS_RCWCLR = 805 +AARCH64_INS_RCWCLRA = 806 +AARCH64_INS_RCWCLRAL = 807 +AARCH64_INS_RCWCLRL = 808 +AARCH64_INS_RCWCLRP = 809 +AARCH64_INS_RCWCLRPA = 810 +AARCH64_INS_RCWCLRPAL = 811 +AARCH64_INS_RCWCLRPL = 812 +AARCH64_INS_RCWSCLR = 813 +AARCH64_INS_RCWSCLRA = 814 +AARCH64_INS_RCWSCLRAL = 815 +AARCH64_INS_RCWSCLRL = 816 +AARCH64_INS_RCWSCLRP = 817 +AARCH64_INS_RCWSCLRPA = 818 +AARCH64_INS_RCWSCLRPAL = 819 +AARCH64_INS_RCWSCLRPL = 820 +AARCH64_INS_RCWSCAS = 821 +AARCH64_INS_RCWSCASA = 822 +AARCH64_INS_RCWSCASAL = 823 +AARCH64_INS_RCWSCASL = 824 +AARCH64_INS_RCWSCASP = 825 +AARCH64_INS_RCWSCASPA = 826 +AARCH64_INS_RCWSCASPAL = 827 +AARCH64_INS_RCWSCASPL = 828 +AARCH64_INS_RCWSET = 829 +AARCH64_INS_RCWSETA = 830 +AARCH64_INS_RCWSETAL = 831 +AARCH64_INS_RCWSETL = 832 +AARCH64_INS_RCWSETP = 833 +AARCH64_INS_RCWSETPA = 834 +AARCH64_INS_RCWSETPAL = 835 +AARCH64_INS_RCWSETPL = 836 +AARCH64_INS_RCWSSET = 837 +AARCH64_INS_RCWSSETA = 838 +AARCH64_INS_RCWSSETAL = 839 +AARCH64_INS_RCWSSETL = 840 +AARCH64_INS_RCWSSETP = 841 +AARCH64_INS_RCWSSETPA = 842 +AARCH64_INS_RCWSSETPAL = 843 +AARCH64_INS_RCWSSETPL = 844 +AARCH64_INS_RCWSWP = 845 +AARCH64_INS_RCWSWPA = 846 +AARCH64_INS_RCWSWPAL = 847 +AARCH64_INS_RCWSWPL = 848 +AARCH64_INS_RCWSWPP = 849 +AARCH64_INS_RCWSWPPA = 850 +AARCH64_INS_RCWSWPPAL = 851 +AARCH64_INS_RCWSWPPL = 852 +AARCH64_INS_RCWSSWP = 853 +AARCH64_INS_RCWSSWPA = 854 +AARCH64_INS_RCWSSWPAL = 855 +AARCH64_INS_RCWSSWPL = 856 +AARCH64_INS_RCWSSWPP = 857 +AARCH64_INS_RCWSSWPPA = 858 +AARCH64_INS_RCWSSWPPAL = 859 +AARCH64_INS_RCWSSWPPL = 860 +AARCH64_INS_RDFFRS = 861 +AARCH64_INS_RDFFR = 862 +AARCH64_INS_RDSVL = 863 +AARCH64_INS_RDVL = 864 +AARCH64_INS_RET = 865 +AARCH64_INS_RETAA = 866 +AARCH64_INS_RETAASPPC = 867 +AARCH64_INS_RETAB = 868 +AARCH64_INS_RETABSPPC = 869 +AARCH64_INS_REV16 = 870 +AARCH64_INS_REV32 = 871 +AARCH64_INS_REV64 = 872 +AARCH64_INS_REVB = 873 +AARCH64_INS_REVD = 874 +AARCH64_INS_REVH = 875 +AARCH64_INS_REVW = 876 +AARCH64_INS_REV = 877 +AARCH64_INS_RMIF = 878 +AARCH64_INS_ROR = 879 +AARCH64_INS_RPRFM = 880 +AARCH64_INS_RSHRNB = 881 +AARCH64_INS_RSHRNT = 882 +AARCH64_INS_RSHRN2 = 883 +AARCH64_INS_RSHRN = 884 +AARCH64_INS_RSUBHNB = 885 +AARCH64_INS_RSUBHNT = 886 +AARCH64_INS_RSUBHN = 887 +AARCH64_INS_RSUBHN2 = 888 +AARCH64_INS_SABALB = 889 +AARCH64_INS_SABALT = 890 +AARCH64_INS_SABAL2 = 891 +AARCH64_INS_SABAL = 892 +AARCH64_INS_SABA = 893 +AARCH64_INS_SABDLB = 894 +AARCH64_INS_SABDLT = 895 +AARCH64_INS_SABDL2 = 896 +AARCH64_INS_SABDL = 897 +AARCH64_INS_SABD = 898 +AARCH64_INS_SADALP = 899 +AARCH64_INS_SADDLBT = 900 +AARCH64_INS_SADDLB = 901 +AARCH64_INS_SADDLP = 902 +AARCH64_INS_SADDLT = 903 +AARCH64_INS_SADDLV = 904 +AARCH64_INS_SADDL2 = 905 +AARCH64_INS_SADDL = 906 +AARCH64_INS_SADDV = 907 +AARCH64_INS_SADDWB = 908 +AARCH64_INS_SADDWT = 909 +AARCH64_INS_SADDW2 = 910 +AARCH64_INS_SADDW = 911 +AARCH64_INS_SB = 912 +AARCH64_INS_SBCLB = 913 +AARCH64_INS_SBCLT = 914 +AARCH64_INS_SBCS = 915 +AARCH64_INS_SBC = 916 +AARCH64_INS_SBFM = 917 +AARCH64_INS_SCLAMP = 918 +AARCH64_INS_SCVTF = 919 +AARCH64_INS_SDIVR = 920 +AARCH64_INS_SDIV = 921 +AARCH64_INS_SDOT = 922 +AARCH64_INS_SEL = 923 +AARCH64_INS_SETE = 924 +AARCH64_INS_SETEN = 925 +AARCH64_INS_SETET = 926 +AARCH64_INS_SETETN = 927 +AARCH64_INS_SETF16 = 928 +AARCH64_INS_SETF8 = 929 +AARCH64_INS_SETFFR = 930 +AARCH64_INS_SETGM = 931 +AARCH64_INS_SETGMN = 932 +AARCH64_INS_SETGMT = 933 +AARCH64_INS_SETGMTN = 934 +AARCH64_INS_SETGP = 935 +AARCH64_INS_SETGPN = 936 +AARCH64_INS_SETGPT = 937 +AARCH64_INS_SETGPTN = 938 +AARCH64_INS_SETM = 939 +AARCH64_INS_SETMN = 940 +AARCH64_INS_SETMT = 941 +AARCH64_INS_SETMTN = 942 +AARCH64_INS_SETP = 943 +AARCH64_INS_SETPN = 944 +AARCH64_INS_SETPT = 945 +AARCH64_INS_SETPTN = 946 +AARCH64_INS_SHA1C = 947 +AARCH64_INS_SHA1H = 948 +AARCH64_INS_SHA1M = 949 +AARCH64_INS_SHA1P = 950 +AARCH64_INS_SHA1SU0 = 951 +AARCH64_INS_SHA1SU1 = 952 +AARCH64_INS_SHA256H2 = 953 +AARCH64_INS_SHA256H = 954 +AARCH64_INS_SHA256SU0 = 955 +AARCH64_INS_SHA256SU1 = 956 +AARCH64_INS_SHA512H = 957 +AARCH64_INS_SHA512H2 = 958 +AARCH64_INS_SHA512SU0 = 959 +AARCH64_INS_SHA512SU1 = 960 +AARCH64_INS_SHADD = 961 +AARCH64_INS_SHLL2 = 962 +AARCH64_INS_SHLL = 963 +AARCH64_INS_SHL = 964 +AARCH64_INS_SHRNB = 965 +AARCH64_INS_SHRNT = 966 +AARCH64_INS_SHRN2 = 967 +AARCH64_INS_SHRN = 968 +AARCH64_INS_SHSUBR = 969 +AARCH64_INS_SHSUB = 970 +AARCH64_INS_SLI = 971 +AARCH64_INS_SM3PARTW1 = 972 +AARCH64_INS_SM3PARTW2 = 973 +AARCH64_INS_SM3SS1 = 974 +AARCH64_INS_SM3TT1A = 975 +AARCH64_INS_SM3TT1B = 976 +AARCH64_INS_SM3TT2A = 977 +AARCH64_INS_SM3TT2B = 978 +AARCH64_INS_SM4E = 979 +AARCH64_INS_SM4EKEY = 980 +AARCH64_INS_SMADDL = 981 +AARCH64_INS_SMAXP = 982 +AARCH64_INS_SMAXQV = 983 +AARCH64_INS_SMAXV = 984 +AARCH64_INS_SMAX = 985 +AARCH64_INS_SMC = 986 +AARCH64_INS_SMINP = 987 +AARCH64_INS_SMINQV = 988 +AARCH64_INS_SMINV = 989 +AARCH64_INS_SMIN = 990 +AARCH64_INS_SMLALB = 991 +AARCH64_INS_SMLALL = 992 +AARCH64_INS_SMLALT = 993 +AARCH64_INS_SMLAL = 994 +AARCH64_INS_SMLAL2 = 995 +AARCH64_INS_SMLSLB = 996 +AARCH64_INS_SMLSLL = 997 +AARCH64_INS_SMLSLT = 998 +AARCH64_INS_SMLSL = 999 +AARCH64_INS_SMLSL2 = 1000 +AARCH64_INS_SMMLA = 1001 +AARCH64_INS_SMOPA = 1002 +AARCH64_INS_SMOPS = 1003 +AARCH64_INS_SMOV = 1004 +AARCH64_INS_SMSUBL = 1005 +AARCH64_INS_SMULH = 1006 +AARCH64_INS_SMULLB = 1007 +AARCH64_INS_SMULLT = 1008 +AARCH64_INS_SMULL2 = 1009 +AARCH64_INS_SMULL = 1010 +AARCH64_INS_SPLICE = 1011 +AARCH64_INS_SQABS = 1012 +AARCH64_INS_SQADD = 1013 +AARCH64_INS_SQCADD = 1014 +AARCH64_INS_SQCVTN = 1015 +AARCH64_INS_SQCVTUN = 1016 +AARCH64_INS_SQCVTU = 1017 +AARCH64_INS_SQCVT = 1018 +AARCH64_INS_SQDECB = 1019 +AARCH64_INS_SQDECD = 1020 +AARCH64_INS_SQDECH = 1021 +AARCH64_INS_SQDECP = 1022 +AARCH64_INS_SQDECW = 1023 +AARCH64_INS_SQDMLALBT = 1024 +AARCH64_INS_SQDMLALB = 1025 +AARCH64_INS_SQDMLALT = 1026 +AARCH64_INS_SQDMLAL = 1027 +AARCH64_INS_SQDMLAL2 = 1028 +AARCH64_INS_SQDMLSLBT = 1029 +AARCH64_INS_SQDMLSLB = 1030 +AARCH64_INS_SQDMLSLT = 1031 +AARCH64_INS_SQDMLSL = 1032 +AARCH64_INS_SQDMLSL2 = 1033 +AARCH64_INS_SQDMULH = 1034 +AARCH64_INS_SQDMULLB = 1035 +AARCH64_INS_SQDMULLT = 1036 +AARCH64_INS_SQDMULL = 1037 +AARCH64_INS_SQDMULL2 = 1038 +AARCH64_INS_SQINCB = 1039 +AARCH64_INS_SQINCD = 1040 +AARCH64_INS_SQINCH = 1041 +AARCH64_INS_SQINCP = 1042 +AARCH64_INS_SQINCW = 1043 +AARCH64_INS_SQNEG = 1044 +AARCH64_INS_SQRDCMLAH = 1045 +AARCH64_INS_SQRDMLAH = 1046 +AARCH64_INS_SQRDMLSH = 1047 +AARCH64_INS_SQRDMULH = 1048 +AARCH64_INS_SQRSHLR = 1049 +AARCH64_INS_SQRSHL = 1050 +AARCH64_INS_SQRSHRNB = 1051 +AARCH64_INS_SQRSHRNT = 1052 +AARCH64_INS_SQRSHRN = 1053 +AARCH64_INS_SQRSHRN2 = 1054 +AARCH64_INS_SQRSHRUNB = 1055 +AARCH64_INS_SQRSHRUNT = 1056 +AARCH64_INS_SQRSHRUN = 1057 +AARCH64_INS_SQRSHRUN2 = 1058 +AARCH64_INS_SQRSHRU = 1059 +AARCH64_INS_SQRSHR = 1060 +AARCH64_INS_SQSHLR = 1061 +AARCH64_INS_SQSHLU = 1062 +AARCH64_INS_SQSHL = 1063 +AARCH64_INS_SQSHRNB = 1064 +AARCH64_INS_SQSHRNT = 1065 +AARCH64_INS_SQSHRN = 1066 +AARCH64_INS_SQSHRN2 = 1067 +AARCH64_INS_SQSHRUNB = 1068 +AARCH64_INS_SQSHRUNT = 1069 +AARCH64_INS_SQSHRUN = 1070 +AARCH64_INS_SQSHRUN2 = 1071 +AARCH64_INS_SQSUBR = 1072 +AARCH64_INS_SQSUB = 1073 +AARCH64_INS_SQXTNB = 1074 +AARCH64_INS_SQXTNT = 1075 +AARCH64_INS_SQXTN2 = 1076 +AARCH64_INS_SQXTN = 1077 +AARCH64_INS_SQXTUNB = 1078 +AARCH64_INS_SQXTUNT = 1079 +AARCH64_INS_SQXTUN2 = 1080 +AARCH64_INS_SQXTUN = 1081 +AARCH64_INS_SRHADD = 1082 +AARCH64_INS_SRI = 1083 +AARCH64_INS_SRSHLR = 1084 +AARCH64_INS_SRSHL = 1085 +AARCH64_INS_SRSHR = 1086 +AARCH64_INS_SRSRA = 1087 +AARCH64_INS_SSHLLB = 1088 +AARCH64_INS_SSHLLT = 1089 +AARCH64_INS_SSHLL2 = 1090 +AARCH64_INS_SSHLL = 1091 +AARCH64_INS_SSHL = 1092 +AARCH64_INS_SSHR = 1093 +AARCH64_INS_SSRA = 1094 +AARCH64_INS_ST1B = 1095 +AARCH64_INS_ST1D = 1096 +AARCH64_INS_ST1H = 1097 +AARCH64_INS_ST1Q = 1098 +AARCH64_INS_ST1W = 1099 +AARCH64_INS_SSUBLBT = 1100 +AARCH64_INS_SSUBLB = 1101 +AARCH64_INS_SSUBLTB = 1102 +AARCH64_INS_SSUBLT = 1103 +AARCH64_INS_SSUBL2 = 1104 +AARCH64_INS_SSUBL = 1105 +AARCH64_INS_SSUBWB = 1106 +AARCH64_INS_SSUBWT = 1107 +AARCH64_INS_SSUBW2 = 1108 +AARCH64_INS_SSUBW = 1109 +AARCH64_INS_ST1 = 1110 +AARCH64_INS_ST2B = 1111 +AARCH64_INS_ST2D = 1112 +AARCH64_INS_ST2G = 1113 +AARCH64_INS_ST2H = 1114 +AARCH64_INS_ST2Q = 1115 +AARCH64_INS_ST2 = 1116 +AARCH64_INS_ST2W = 1117 +AARCH64_INS_ST3B = 1118 +AARCH64_INS_ST3D = 1119 +AARCH64_INS_ST3H = 1120 +AARCH64_INS_ST3Q = 1121 +AARCH64_INS_ST3 = 1122 +AARCH64_INS_ST3W = 1123 +AARCH64_INS_ST4B = 1124 +AARCH64_INS_ST4D = 1125 +AARCH64_INS_ST4 = 1126 +AARCH64_INS_ST4H = 1127 +AARCH64_INS_ST4Q = 1128 +AARCH64_INS_ST4W = 1129 +AARCH64_INS_ST64B = 1130 +AARCH64_INS_ST64BV = 1131 +AARCH64_INS_ST64BV0 = 1132 +AARCH64_INS_STGM = 1133 +AARCH64_INS_STGP = 1134 +AARCH64_INS_STG = 1135 +AARCH64_INS_STILP = 1136 +AARCH64_INS_STL1 = 1137 +AARCH64_INS_STLLRB = 1138 +AARCH64_INS_STLLRH = 1139 +AARCH64_INS_STLLR = 1140 +AARCH64_INS_STLRB = 1141 +AARCH64_INS_STLRH = 1142 +AARCH64_INS_STLR = 1143 +AARCH64_INS_STLURB = 1144 +AARCH64_INS_STLURH = 1145 +AARCH64_INS_STLUR = 1146 +AARCH64_INS_STLXP = 1147 +AARCH64_INS_STLXRB = 1148 +AARCH64_INS_STLXRH = 1149 +AARCH64_INS_STLXR = 1150 +AARCH64_INS_STNP = 1151 +AARCH64_INS_STNT1B = 1152 +AARCH64_INS_STNT1D = 1153 +AARCH64_INS_STNT1H = 1154 +AARCH64_INS_STNT1W = 1155 +AARCH64_INS_STP = 1156 +AARCH64_INS_STRB = 1157 +AARCH64_INS_STR = 1158 +AARCH64_INS_STRH = 1159 +AARCH64_INS_STTRB = 1160 +AARCH64_INS_STTRH = 1161 +AARCH64_INS_STTR = 1162 +AARCH64_INS_STURB = 1163 +AARCH64_INS_STUR = 1164 +AARCH64_INS_STURH = 1165 +AARCH64_INS_STXP = 1166 +AARCH64_INS_STXRB = 1167 +AARCH64_INS_STXRH = 1168 +AARCH64_INS_STXR = 1169 +AARCH64_INS_STZ2G = 1170 +AARCH64_INS_STZGM = 1171 +AARCH64_INS_STZG = 1172 +AARCH64_INS_SUBG = 1173 +AARCH64_INS_SUBHNB = 1174 +AARCH64_INS_SUBHNT = 1175 +AARCH64_INS_SUBHN = 1176 +AARCH64_INS_SUBHN2 = 1177 +AARCH64_INS_SUBP = 1178 +AARCH64_INS_SUBPS = 1179 +AARCH64_INS_SUBPT = 1180 +AARCH64_INS_SUBR = 1181 +AARCH64_INS_SUBS = 1182 +AARCH64_INS_SUB = 1183 +AARCH64_INS_SUDOT = 1184 +AARCH64_INS_SUMLALL = 1185 +AARCH64_INS_SUMOPA = 1186 +AARCH64_INS_SUMOPS = 1187 +AARCH64_INS_SUNPKHI = 1188 +AARCH64_INS_SUNPKLO = 1189 +AARCH64_INS_SUNPK = 1190 +AARCH64_INS_SUQADD = 1191 +AARCH64_INS_SUVDOT = 1192 +AARCH64_INS_SVC = 1193 +AARCH64_INS_SVDOT = 1194 +AARCH64_INS_SWPAB = 1195 +AARCH64_INS_SWPAH = 1196 +AARCH64_INS_SWPALB = 1197 +AARCH64_INS_SWPALH = 1198 +AARCH64_INS_SWPAL = 1199 +AARCH64_INS_SWPA = 1200 +AARCH64_INS_SWPB = 1201 +AARCH64_INS_SWPH = 1202 +AARCH64_INS_SWPLB = 1203 +AARCH64_INS_SWPLH = 1204 +AARCH64_INS_SWPL = 1205 +AARCH64_INS_SWPP = 1206 +AARCH64_INS_SWPPA = 1207 +AARCH64_INS_SWPPAL = 1208 +AARCH64_INS_SWPPL = 1209 +AARCH64_INS_SWP = 1210 +AARCH64_INS_SXTB = 1211 +AARCH64_INS_SXTH = 1212 +AARCH64_INS_SXTW = 1213 +AARCH64_INS_SYSL = 1214 +AARCH64_INS_SYSP = 1215 +AARCH64_INS_SYS = 1216 +AARCH64_INS_TBLQ = 1217 +AARCH64_INS_TBL = 1218 +AARCH64_INS_TBNZ = 1219 +AARCH64_INS_TBXQ = 1220 +AARCH64_INS_TBX = 1221 +AARCH64_INS_TBZ = 1222 +AARCH64_INS_TCANCEL = 1223 +AARCH64_INS_TCOMMIT = 1224 +AARCH64_INS_TRCIT = 1225 +AARCH64_INS_TRN1 = 1226 +AARCH64_INS_TRN2 = 1227 +AARCH64_INS_TSB = 1228 +AARCH64_INS_TSTART = 1229 +AARCH64_INS_TTEST = 1230 +AARCH64_INS_UABALB = 1231 +AARCH64_INS_UABALT = 1232 +AARCH64_INS_UABAL2 = 1233 +AARCH64_INS_UABAL = 1234 +AARCH64_INS_UABA = 1235 +AARCH64_INS_UABDLB = 1236 +AARCH64_INS_UABDLT = 1237 +AARCH64_INS_UABDL2 = 1238 +AARCH64_INS_UABDL = 1239 +AARCH64_INS_UABD = 1240 +AARCH64_INS_UADALP = 1241 +AARCH64_INS_UADDLB = 1242 +AARCH64_INS_UADDLP = 1243 +AARCH64_INS_UADDLT = 1244 +AARCH64_INS_UADDLV = 1245 +AARCH64_INS_UADDL2 = 1246 +AARCH64_INS_UADDL = 1247 +AARCH64_INS_UADDV = 1248 +AARCH64_INS_UADDWB = 1249 +AARCH64_INS_UADDWT = 1250 +AARCH64_INS_UADDW2 = 1251 +AARCH64_INS_UADDW = 1252 +AARCH64_INS_UBFM = 1253 +AARCH64_INS_UCLAMP = 1254 +AARCH64_INS_UCVTF = 1255 +AARCH64_INS_UDF = 1256 +AARCH64_INS_UDIVR = 1257 +AARCH64_INS_UDIV = 1258 +AARCH64_INS_UDOT = 1259 +AARCH64_INS_UHADD = 1260 +AARCH64_INS_UHSUBR = 1261 +AARCH64_INS_UHSUB = 1262 +AARCH64_INS_UMADDL = 1263 +AARCH64_INS_UMAXP = 1264 +AARCH64_INS_UMAXQV = 1265 +AARCH64_INS_UMAXV = 1266 +AARCH64_INS_UMAX = 1267 +AARCH64_INS_UMINP = 1268 +AARCH64_INS_UMINQV = 1269 +AARCH64_INS_UMINV = 1270 +AARCH64_INS_UMIN = 1271 +AARCH64_INS_UMLALB = 1272 +AARCH64_INS_UMLALL = 1273 +AARCH64_INS_UMLALT = 1274 +AARCH64_INS_UMLAL = 1275 +AARCH64_INS_UMLAL2 = 1276 +AARCH64_INS_UMLSLB = 1277 +AARCH64_INS_UMLSLL = 1278 +AARCH64_INS_UMLSLT = 1279 +AARCH64_INS_UMLSL = 1280 +AARCH64_INS_UMLSL2 = 1281 +AARCH64_INS_UMMLA = 1282 +AARCH64_INS_UMOPA = 1283 +AARCH64_INS_UMOPS = 1284 +AARCH64_INS_UMOV = 1285 +AARCH64_INS_UMSUBL = 1286 +AARCH64_INS_UMULH = 1287 +AARCH64_INS_UMULLB = 1288 +AARCH64_INS_UMULLT = 1289 +AARCH64_INS_UMULL2 = 1290 +AARCH64_INS_UMULL = 1291 +AARCH64_INS_UQADD = 1292 +AARCH64_INS_UQCVTN = 1293 +AARCH64_INS_UQCVT = 1294 +AARCH64_INS_UQDECB = 1295 +AARCH64_INS_UQDECD = 1296 +AARCH64_INS_UQDECH = 1297 +AARCH64_INS_UQDECP = 1298 +AARCH64_INS_UQDECW = 1299 +AARCH64_INS_UQINCB = 1300 +AARCH64_INS_UQINCD = 1301 +AARCH64_INS_UQINCH = 1302 +AARCH64_INS_UQINCP = 1303 +AARCH64_INS_UQINCW = 1304 +AARCH64_INS_UQRSHLR = 1305 +AARCH64_INS_UQRSHL = 1306 +AARCH64_INS_UQRSHRNB = 1307 +AARCH64_INS_UQRSHRNT = 1308 +AARCH64_INS_UQRSHRN = 1309 +AARCH64_INS_UQRSHRN2 = 1310 +AARCH64_INS_UQRSHR = 1311 +AARCH64_INS_UQSHLR = 1312 +AARCH64_INS_UQSHL = 1313 +AARCH64_INS_UQSHRNB = 1314 +AARCH64_INS_UQSHRNT = 1315 +AARCH64_INS_UQSHRN = 1316 +AARCH64_INS_UQSHRN2 = 1317 +AARCH64_INS_UQSUBR = 1318 +AARCH64_INS_UQSUB = 1319 +AARCH64_INS_UQXTNB = 1320 +AARCH64_INS_UQXTNT = 1321 +AARCH64_INS_UQXTN2 = 1322 +AARCH64_INS_UQXTN = 1323 +AARCH64_INS_URECPE = 1324 +AARCH64_INS_URHADD = 1325 +AARCH64_INS_URSHLR = 1326 +AARCH64_INS_URSHL = 1327 +AARCH64_INS_URSHR = 1328 +AARCH64_INS_URSQRTE = 1329 +AARCH64_INS_URSRA = 1330 +AARCH64_INS_USDOT = 1331 +AARCH64_INS_USHLLB = 1332 +AARCH64_INS_USHLLT = 1333 +AARCH64_INS_USHLL2 = 1334 +AARCH64_INS_USHLL = 1335 +AARCH64_INS_USHL = 1336 +AARCH64_INS_USHR = 1337 +AARCH64_INS_USMLALL = 1338 +AARCH64_INS_USMMLA = 1339 +AARCH64_INS_USMOPA = 1340 +AARCH64_INS_USMOPS = 1341 +AARCH64_INS_USQADD = 1342 +AARCH64_INS_USRA = 1343 +AARCH64_INS_USUBLB = 1344 +AARCH64_INS_USUBLT = 1345 +AARCH64_INS_USUBL2 = 1346 +AARCH64_INS_USUBL = 1347 +AARCH64_INS_USUBWB = 1348 +AARCH64_INS_USUBWT = 1349 +AARCH64_INS_USUBW2 = 1350 +AARCH64_INS_USUBW = 1351 +AARCH64_INS_USVDOT = 1352 +AARCH64_INS_UUNPKHI = 1353 +AARCH64_INS_UUNPKLO = 1354 +AARCH64_INS_UUNPK = 1355 +AARCH64_INS_UVDOT = 1356 +AARCH64_INS_UXTB = 1357 +AARCH64_INS_UXTH = 1358 +AARCH64_INS_UXTW = 1359 +AARCH64_INS_UZP1 = 1360 +AARCH64_INS_UZP2 = 1361 +AARCH64_INS_UZPQ1 = 1362 +AARCH64_INS_UZPQ2 = 1363 +AARCH64_INS_UZP = 1364 +AARCH64_INS_WFET = 1365 +AARCH64_INS_WFIT = 1366 +AARCH64_INS_WHILEGE = 1367 +AARCH64_INS_WHILEGT = 1368 +AARCH64_INS_WHILEHI = 1369 +AARCH64_INS_WHILEHS = 1370 +AARCH64_INS_WHILELE = 1371 +AARCH64_INS_WHILELO = 1372 +AARCH64_INS_WHILELS = 1373 +AARCH64_INS_WHILELT = 1374 +AARCH64_INS_WHILERW = 1375 +AARCH64_INS_WHILEWR = 1376 +AARCH64_INS_WRFFR = 1377 +AARCH64_INS_XAFLAG = 1378 +AARCH64_INS_XAR = 1379 +AARCH64_INS_XPACD = 1380 +AARCH64_INS_XPACI = 1381 +AARCH64_INS_XTN2 = 1382 +AARCH64_INS_XTN = 1383 +AARCH64_INS_ZERO = 1384 +AARCH64_INS_ZIP1 = 1385 +AARCH64_INS_ZIP2 = 1386 +AARCH64_INS_ZIPQ1 = 1387 +AARCH64_INS_ZIPQ2 = 1388 +AARCH64_INS_ZIP = 1389 +AARCH64_INS_ENDING = 1390 +AARCH64_INS_ALIAS_BEGIN = 1391 +AARCH64_INS_ALIAS_ADDPT = 1392 +AARCH64_INS_ALIAS_GCSB = 1393 +AARCH64_INS_ALIAS_GCSPOPM = 1394 +AARCH64_INS_ALIAS_LDAPUR = 1395 +AARCH64_INS_ALIAS_STLLRB = 1396 +AARCH64_INS_ALIAS_STLLRH = 1397 +AARCH64_INS_ALIAS_STLLR = 1398 +AARCH64_INS_ALIAS_STLRB = 1399 +AARCH64_INS_ALIAS_STLRH = 1400 +AARCH64_INS_ALIAS_STLR = 1401 +AARCH64_INS_ALIAS_STLUR = 1402 +AARCH64_INS_ALIAS_SUBPT = 1403 +AARCH64_INS_ALIAS_LDRAA = 1404 +AARCH64_INS_ALIAS_ADD = 1405 +AARCH64_INS_ALIAS_CMN = 1406 +AARCH64_INS_ALIAS_ADDS = 1407 +AARCH64_INS_ALIAS_AND = 1408 +AARCH64_INS_ALIAS_ANDS = 1409 +AARCH64_INS_ALIAS_LDR = 1410 +AARCH64_INS_ALIAS_STR = 1411 +AARCH64_INS_ALIAS_LDRB = 1412 +AARCH64_INS_ALIAS_STRB = 1413 +AARCH64_INS_ALIAS_LDRH = 1414 +AARCH64_INS_ALIAS_STRH = 1415 +AARCH64_INS_ALIAS_PRFM = 1416 +AARCH64_INS_ALIAS_LDAPURB = 1417 +AARCH64_INS_ALIAS_STLURB = 1418 +AARCH64_INS_ALIAS_LDUR = 1419 +AARCH64_INS_ALIAS_STUR = 1420 +AARCH64_INS_ALIAS_PRFUM = 1421 +AARCH64_INS_ALIAS_LDTR = 1422 +AARCH64_INS_ALIAS_STTR = 1423 +AARCH64_INS_ALIAS_LDP = 1424 +AARCH64_INS_ALIAS_STGP = 1425 +AARCH64_INS_ALIAS_LDNP = 1426 +AARCH64_INS_ALIAS_STNP = 1427 +AARCH64_INS_ALIAS_STG = 1428 +AARCH64_INS_ALIAS_MOV = 1429 +AARCH64_INS_ALIAS_LD1 = 1430 +AARCH64_INS_ALIAS_LD1R = 1431 +AARCH64_INS_ALIAS_STADDLB = 1432 +AARCH64_INS_ALIAS_STADDLH = 1433 +AARCH64_INS_ALIAS_STADDL = 1434 +AARCH64_INS_ALIAS_STADDB = 1435 +AARCH64_INS_ALIAS_STADDH = 1436 +AARCH64_INS_ALIAS_STADD = 1437 +AARCH64_INS_ALIAS_PTRUE = 1438 +AARCH64_INS_ALIAS_PTRUES = 1439 +AARCH64_INS_ALIAS_CNTB = 1440 +AARCH64_INS_ALIAS_SQINCH = 1441 +AARCH64_INS_ALIAS_INCB = 1442 +AARCH64_INS_ALIAS_SQINCB = 1443 +AARCH64_INS_ALIAS_UQINCB = 1444 +AARCH64_INS_ALIAS_ORR = 1445 +AARCH64_INS_ALIAS_DUPM = 1446 +AARCH64_INS_ALIAS_FMOV = 1447 +AARCH64_INS_ALIAS_EOR3 = 1448 +AARCH64_INS_ALIAS_ST1B = 1449 +AARCH64_INS_ALIAS_ST2B = 1450 +AARCH64_INS_ALIAS_ST2Q = 1451 +AARCH64_INS_ALIAS_STNT1B = 1452 +AARCH64_INS_ALIAS_LD1B = 1453 +AARCH64_INS_ALIAS_LDNT1B = 1454 +AARCH64_INS_ALIAS_LD1RQB = 1455 +AARCH64_INS_ALIAS_LD1RB = 1456 +AARCH64_INS_ALIAS_LDFF1B = 1457 +AARCH64_INS_ALIAS_LDNF1B = 1458 +AARCH64_INS_ALIAS_LD2B = 1459 +AARCH64_INS_ALIAS_LD1SB = 1460 +AARCH64_INS_ALIAS_PRFB = 1461 +AARCH64_INS_ALIAS_LDNT1SB = 1462 +AARCH64_INS_ALIAS_LD1ROB = 1463 +AARCH64_INS_ALIAS_LD1Q = 1464 +AARCH64_INS_ALIAS_ST1Q = 1465 +AARCH64_INS_ALIAS_LD1W = 1466 +AARCH64_INS_ALIAS_PMOV = 1467 +AARCH64_INS_ALIAS_SMSTART = 1468 +AARCH64_INS_ALIAS_SMSTOP = 1469 +AARCH64_INS_ALIAS_ZERO = 1470 +AARCH64_INS_ALIAS_MOVT = 1471 +AARCH64_INS_ALIAS_NOP = 1472 +AARCH64_INS_ALIAS_YIELD = 1473 +AARCH64_INS_ALIAS_WFE = 1474 +AARCH64_INS_ALIAS_WFI = 1475 +AARCH64_INS_ALIAS_SEV = 1476 +AARCH64_INS_ALIAS_SEVL = 1477 +AARCH64_INS_ALIAS_DGH = 1478 +AARCH64_INS_ALIAS_ESB = 1479 +AARCH64_INS_ALIAS_CSDB = 1480 +AARCH64_INS_ALIAS_BTI = 1481 +AARCH64_INS_ALIAS_PSB = 1482 +AARCH64_INS_ALIAS_CHKFEAT = 1483 +AARCH64_INS_ALIAS_PACIAZ = 1484 +AARCH64_INS_ALIAS_PACIBZ = 1485 +AARCH64_INS_ALIAS_AUTIAZ = 1486 +AARCH64_INS_ALIAS_AUTIBZ = 1487 +AARCH64_INS_ALIAS_PACIASP = 1488 +AARCH64_INS_ALIAS_PACIBSP = 1489 +AARCH64_INS_ALIAS_AUTIASP = 1490 +AARCH64_INS_ALIAS_AUTIBSP = 1491 +AARCH64_INS_ALIAS_PACIA1716 = 1492 +AARCH64_INS_ALIAS_PACIB1716 = 1493 +AARCH64_INS_ALIAS_AUTIA1716 = 1494 +AARCH64_INS_ALIAS_AUTIB1716 = 1495 +AARCH64_INS_ALIAS_XPACLRI = 1496 +AARCH64_INS_ALIAS_LDRAB = 1497 +AARCH64_INS_ALIAS_PACM = 1498 +AARCH64_INS_ALIAS_CLREX = 1499 +AARCH64_INS_ALIAS_ISB = 1500 +AARCH64_INS_ALIAS_SSBB = 1501 +AARCH64_INS_ALIAS_PSSBB = 1502 +AARCH64_INS_ALIAS_DFB = 1503 +AARCH64_INS_ALIAS_SYS = 1504 +AARCH64_INS_ALIAS_MOVN = 1505 +AARCH64_INS_ALIAS_MOVZ = 1506 +AARCH64_INS_ALIAS_NGC = 1507 +AARCH64_INS_ALIAS_NGCS = 1508 +AARCH64_INS_ALIAS_SUB = 1509 +AARCH64_INS_ALIAS_CMP = 1510 +AARCH64_INS_ALIAS_SUBS = 1511 +AARCH64_INS_ALIAS_NEG = 1512 +AARCH64_INS_ALIAS_NEGS = 1513 +AARCH64_INS_ALIAS_MUL = 1514 +AARCH64_INS_ALIAS_MNEG = 1515 +AARCH64_INS_ALIAS_SMULL = 1516 +AARCH64_INS_ALIAS_SMNEGL = 1517 +AARCH64_INS_ALIAS_UMULL = 1518 +AARCH64_INS_ALIAS_UMNEGL = 1519 +AARCH64_INS_ALIAS_STCLRLB = 1520 +AARCH64_INS_ALIAS_STCLRLH = 1521 +AARCH64_INS_ALIAS_STCLRL = 1522 +AARCH64_INS_ALIAS_STCLRB = 1523 +AARCH64_INS_ALIAS_STCLRH = 1524 +AARCH64_INS_ALIAS_STCLR = 1525 +AARCH64_INS_ALIAS_STEORLB = 1526 +AARCH64_INS_ALIAS_STEORLH = 1527 +AARCH64_INS_ALIAS_STEORL = 1528 +AARCH64_INS_ALIAS_STEORB = 1529 +AARCH64_INS_ALIAS_STEORH = 1530 +AARCH64_INS_ALIAS_STEOR = 1531 +AARCH64_INS_ALIAS_STSETLB = 1532 +AARCH64_INS_ALIAS_STSETLH = 1533 +AARCH64_INS_ALIAS_STSETL = 1534 +AARCH64_INS_ALIAS_STSETB = 1535 +AARCH64_INS_ALIAS_STSETH = 1536 +AARCH64_INS_ALIAS_STSET = 1537 +AARCH64_INS_ALIAS_STSMAXLB = 1538 +AARCH64_INS_ALIAS_STSMAXLH = 1539 +AARCH64_INS_ALIAS_STSMAXL = 1540 +AARCH64_INS_ALIAS_STSMAXB = 1541 +AARCH64_INS_ALIAS_STSMAXH = 1542 +AARCH64_INS_ALIAS_STSMAX = 1543 +AARCH64_INS_ALIAS_STSMINLB = 1544 +AARCH64_INS_ALIAS_STSMINLH = 1545 +AARCH64_INS_ALIAS_STSMINL = 1546 +AARCH64_INS_ALIAS_STSMINB = 1547 +AARCH64_INS_ALIAS_STSMINH = 1548 +AARCH64_INS_ALIAS_STSMIN = 1549 +AARCH64_INS_ALIAS_STUMAXLB = 1550 +AARCH64_INS_ALIAS_STUMAXLH = 1551 +AARCH64_INS_ALIAS_STUMAXL = 1552 +AARCH64_INS_ALIAS_STUMAXB = 1553 +AARCH64_INS_ALIAS_STUMAXH = 1554 +AARCH64_INS_ALIAS_STUMAX = 1555 +AARCH64_INS_ALIAS_STUMINLB = 1556 +AARCH64_INS_ALIAS_STUMINLH = 1557 +AARCH64_INS_ALIAS_STUMINL = 1558 +AARCH64_INS_ALIAS_STUMINB = 1559 +AARCH64_INS_ALIAS_STUMINH = 1560 +AARCH64_INS_ALIAS_STUMIN = 1561 +AARCH64_INS_ALIAS_IRG = 1562 +AARCH64_INS_ALIAS_LDG = 1563 +AARCH64_INS_ALIAS_STZG = 1564 +AARCH64_INS_ALIAS_ST2G = 1565 +AARCH64_INS_ALIAS_STZ2G = 1566 +AARCH64_INS_ALIAS_BICS = 1567 +AARCH64_INS_ALIAS_BIC = 1568 +AARCH64_INS_ALIAS_EON = 1569 +AARCH64_INS_ALIAS_EOR = 1570 +AARCH64_INS_ALIAS_ORN = 1571 +AARCH64_INS_ALIAS_MVN = 1572 +AARCH64_INS_ALIAS_TST = 1573 +AARCH64_INS_ALIAS_ROR = 1574 +AARCH64_INS_ALIAS_ASR = 1575 +AARCH64_INS_ALIAS_SXTB = 1576 +AARCH64_INS_ALIAS_SXTH = 1577 +AARCH64_INS_ALIAS_SXTW = 1578 +AARCH64_INS_ALIAS_LSR = 1579 +AARCH64_INS_ALIAS_UXTB = 1580 +AARCH64_INS_ALIAS_UXTH = 1581 +AARCH64_INS_ALIAS_UXTW = 1582 +AARCH64_INS_ALIAS_CSET = 1583 +AARCH64_INS_ALIAS_CSETM = 1584 +AARCH64_INS_ALIAS_CINC = 1585 +AARCH64_INS_ALIAS_CINV = 1586 +AARCH64_INS_ALIAS_CNEG = 1587 +AARCH64_INS_ALIAS_RET = 1588 +AARCH64_INS_ALIAS_DCPS1 = 1589 +AARCH64_INS_ALIAS_DCPS2 = 1590 +AARCH64_INS_ALIAS_DCPS3 = 1591 +AARCH64_INS_ALIAS_LDPSW = 1592 +AARCH64_INS_ALIAS_LDRSH = 1593 +AARCH64_INS_ALIAS_LDRSB = 1594 +AARCH64_INS_ALIAS_LDRSW = 1595 +AARCH64_INS_ALIAS_LDURH = 1596 +AARCH64_INS_ALIAS_LDURB = 1597 +AARCH64_INS_ALIAS_LDURSH = 1598 +AARCH64_INS_ALIAS_LDURSB = 1599 +AARCH64_INS_ALIAS_LDURSW = 1600 +AARCH64_INS_ALIAS_LDTRH = 1601 +AARCH64_INS_ALIAS_LDTRB = 1602 +AARCH64_INS_ALIAS_LDTRSH = 1603 +AARCH64_INS_ALIAS_LDTRSB = 1604 +AARCH64_INS_ALIAS_LDTRSW = 1605 +AARCH64_INS_ALIAS_STP = 1606 +AARCH64_INS_ALIAS_STURH = 1607 +AARCH64_INS_ALIAS_STURB = 1608 +AARCH64_INS_ALIAS_STLURH = 1609 +AARCH64_INS_ALIAS_LDAPURSB = 1610 +AARCH64_INS_ALIAS_LDAPURH = 1611 +AARCH64_INS_ALIAS_LDAPURSH = 1612 +AARCH64_INS_ALIAS_LDAPURSW = 1613 +AARCH64_INS_ALIAS_STTRH = 1614 +AARCH64_INS_ALIAS_STTRB = 1615 +AARCH64_INS_ALIAS_BIC_4H = 1616 +AARCH64_INS_ALIAS_BIC_8H = 1617 +AARCH64_INS_ALIAS_BIC_2S = 1618 +AARCH64_INS_ALIAS_BIC_4S = 1619 +AARCH64_INS_ALIAS_ORR_4H = 1620 +AARCH64_INS_ALIAS_ORR_8H = 1621 +AARCH64_INS_ALIAS_ORR_2S = 1622 +AARCH64_INS_ALIAS_ORR_4S = 1623 +AARCH64_INS_ALIAS_SXTL_8H = 1624 +AARCH64_INS_ALIAS_SXTL = 1625 +AARCH64_INS_ALIAS_SXTL_4S = 1626 +AARCH64_INS_ALIAS_SXTL_2D = 1627 +AARCH64_INS_ALIAS_SXTL2_8H = 1628 +AARCH64_INS_ALIAS_SXTL2 = 1629 +AARCH64_INS_ALIAS_SXTL2_4S = 1630 +AARCH64_INS_ALIAS_SXTL2_2D = 1631 +AARCH64_INS_ALIAS_UXTL_8H = 1632 +AARCH64_INS_ALIAS_UXTL = 1633 +AARCH64_INS_ALIAS_UXTL_4S = 1634 +AARCH64_INS_ALIAS_UXTL_2D = 1635 +AARCH64_INS_ALIAS_UXTL2_8H = 1636 +AARCH64_INS_ALIAS_UXTL2 = 1637 +AARCH64_INS_ALIAS_UXTL2_4S = 1638 +AARCH64_INS_ALIAS_UXTL2_2D = 1639 +AARCH64_INS_ALIAS_LD2 = 1640 +AARCH64_INS_ALIAS_LD3 = 1641 +AARCH64_INS_ALIAS_LD4 = 1642 +AARCH64_INS_ALIAS_ST1 = 1643 +AARCH64_INS_ALIAS_ST2 = 1644 +AARCH64_INS_ALIAS_ST3 = 1645 +AARCH64_INS_ALIAS_ST4 = 1646 +AARCH64_INS_ALIAS_LD2R = 1647 +AARCH64_INS_ALIAS_LD3R = 1648 +AARCH64_INS_ALIAS_LD4R = 1649 +AARCH64_INS_ALIAS_CLRBHB = 1650 +AARCH64_INS_ALIAS_STILP = 1651 +AARCH64_INS_ALIAS_STL1 = 1652 +AARCH64_INS_ALIAS_SYSP = 1653 +AARCH64_INS_ALIAS_LD1SW = 1654 +AARCH64_INS_ALIAS_LD1H = 1655 +AARCH64_INS_ALIAS_LD1SH = 1656 +AARCH64_INS_ALIAS_LD1D = 1657 +AARCH64_INS_ALIAS_LD1RSW = 1658 +AARCH64_INS_ALIAS_LD1RH = 1659 +AARCH64_INS_ALIAS_LD1RSH = 1660 +AARCH64_INS_ALIAS_LD1RW = 1661 +AARCH64_INS_ALIAS_LD1RSB = 1662 +AARCH64_INS_ALIAS_LD1RD = 1663 +AARCH64_INS_ALIAS_LD1RQH = 1664 +AARCH64_INS_ALIAS_LD1RQW = 1665 +AARCH64_INS_ALIAS_LD1RQD = 1666 +AARCH64_INS_ALIAS_LDNF1SW = 1667 +AARCH64_INS_ALIAS_LDNF1H = 1668 +AARCH64_INS_ALIAS_LDNF1SH = 1669 +AARCH64_INS_ALIAS_LDNF1W = 1670 +AARCH64_INS_ALIAS_LDNF1SB = 1671 +AARCH64_INS_ALIAS_LDNF1D = 1672 +AARCH64_INS_ALIAS_LDFF1SW = 1673 +AARCH64_INS_ALIAS_LDFF1H = 1674 +AARCH64_INS_ALIAS_LDFF1SH = 1675 +AARCH64_INS_ALIAS_LDFF1W = 1676 +AARCH64_INS_ALIAS_LDFF1SB = 1677 +AARCH64_INS_ALIAS_LDFF1D = 1678 +AARCH64_INS_ALIAS_LD3B = 1679 +AARCH64_INS_ALIAS_LD4B = 1680 +AARCH64_INS_ALIAS_LD2H = 1681 +AARCH64_INS_ALIAS_LD3H = 1682 +AARCH64_INS_ALIAS_LD4H = 1683 +AARCH64_INS_ALIAS_LD2W = 1684 +AARCH64_INS_ALIAS_LD3W = 1685 +AARCH64_INS_ALIAS_LD4W = 1686 +AARCH64_INS_ALIAS_LD2D = 1687 +AARCH64_INS_ALIAS_LD3D = 1688 +AARCH64_INS_ALIAS_LD4D = 1689 +AARCH64_INS_ALIAS_LD2Q = 1690 +AARCH64_INS_ALIAS_LD3Q = 1691 +AARCH64_INS_ALIAS_LD4Q = 1692 +AARCH64_INS_ALIAS_LDNT1H = 1693 +AARCH64_INS_ALIAS_LDNT1W = 1694 +AARCH64_INS_ALIAS_LDNT1D = 1695 +AARCH64_INS_ALIAS_ST1H = 1696 +AARCH64_INS_ALIAS_ST1W = 1697 +AARCH64_INS_ALIAS_ST1D = 1698 +AARCH64_INS_ALIAS_ST3B = 1699 +AARCH64_INS_ALIAS_ST4B = 1700 +AARCH64_INS_ALIAS_ST2H = 1701 +AARCH64_INS_ALIAS_ST3H = 1702 +AARCH64_INS_ALIAS_ST4H = 1703 +AARCH64_INS_ALIAS_ST2W = 1704 +AARCH64_INS_ALIAS_ST3W = 1705 +AARCH64_INS_ALIAS_ST4W = 1706 +AARCH64_INS_ALIAS_ST2D = 1707 +AARCH64_INS_ALIAS_ST3D = 1708 +AARCH64_INS_ALIAS_ST4D = 1709 +AARCH64_INS_ALIAS_ST3Q = 1710 +AARCH64_INS_ALIAS_ST4Q = 1711 +AARCH64_INS_ALIAS_STNT1H = 1712 +AARCH64_INS_ALIAS_STNT1W = 1713 +AARCH64_INS_ALIAS_STNT1D = 1714 +AARCH64_INS_ALIAS_PRFH = 1715 +AARCH64_INS_ALIAS_PRFW = 1716 +AARCH64_INS_ALIAS_PRFD = 1717 +AARCH64_INS_ALIAS_CNTH = 1718 +AARCH64_INS_ALIAS_CNTW = 1719 +AARCH64_INS_ALIAS_CNTD = 1720 +AARCH64_INS_ALIAS_DECB = 1721 +AARCH64_INS_ALIAS_INCH = 1722 +AARCH64_INS_ALIAS_DECH = 1723 +AARCH64_INS_ALIAS_INCW = 1724 +AARCH64_INS_ALIAS_DECW = 1725 +AARCH64_INS_ALIAS_INCD = 1726 +AARCH64_INS_ALIAS_DECD = 1727 +AARCH64_INS_ALIAS_SQDECB = 1728 +AARCH64_INS_ALIAS_UQDECB = 1729 +AARCH64_INS_ALIAS_UQINCH = 1730 +AARCH64_INS_ALIAS_SQDECH = 1731 +AARCH64_INS_ALIAS_UQDECH = 1732 +AARCH64_INS_ALIAS_SQINCW = 1733 +AARCH64_INS_ALIAS_UQINCW = 1734 +AARCH64_INS_ALIAS_SQDECW = 1735 +AARCH64_INS_ALIAS_UQDECW = 1736 +AARCH64_INS_ALIAS_SQINCD = 1737 +AARCH64_INS_ALIAS_UQINCD = 1738 +AARCH64_INS_ALIAS_SQDECD = 1739 +AARCH64_INS_ALIAS_UQDECD = 1740 +AARCH64_INS_ALIAS_MOVS = 1741 +AARCH64_INS_ALIAS_NOT = 1742 +AARCH64_INS_ALIAS_NOTS = 1743 +AARCH64_INS_ALIAS_LD1ROH = 1744 +AARCH64_INS_ALIAS_LD1ROW = 1745 +AARCH64_INS_ALIAS_LD1ROD = 1746 +AARCH64_INS_ALIAS_BCAX = 1747 +AARCH64_INS_ALIAS_BSL = 1748 +AARCH64_INS_ALIAS_BSL1N = 1749 +AARCH64_INS_ALIAS_BSL2N = 1750 +AARCH64_INS_ALIAS_NBSL = 1751 +AARCH64_INS_ALIAS_LDNT1SH = 1752 +AARCH64_INS_ALIAS_LDNT1SW = 1753 +AARCH64_INS_ALIAS_CFP = 1754 +AARCH64_INS_ALIAS_DVP = 1755 +AARCH64_INS_ALIAS_COSP = 1756 +AARCH64_INS_ALIAS_CPP = 1757 +AARCH64_INS_ALIAS_IC = 1758 +AARCH64_INS_ALIAS_DC = 1759 +AARCH64_INS_ALIAS_AT = 1760 +AARCH64_INS_ALIAS_TLBI = 1761 +AARCH64_INS_ALIAS_TLBIP = 1762 +AARCH64_INS_ALIAS_RPRFM = 1763 +AARCH64_INS_ALIAS_LSL = 1764 +AARCH64_INS_ALIAS_SBFX = 1765 +AARCH64_INS_ALIAS_UBFX = 1766 +AARCH64_INS_ALIAS_SBFIZ = 1767 +AARCH64_INS_ALIAS_UBFIZ = 1768 +AARCH64_INS_ALIAS_BFC = 1769 +AARCH64_INS_ALIAS_BFI = 1770 +AARCH64_INS_ALIAS_BFXIL = 1771 +AARCH64_INS_ALIAS_END = 1772 AARCH64_GRP_INVALID = 0 AARCH64_GRP_JUMP = 1 diff --git a/bindings/python/capstone/alpha_const.py b/bindings/python/capstone/alpha_const.py index 6cede69965..f6e5892fb6 100644 --- a/bindings/python/capstone/alpha_const.py +++ b/bindings/python/capstone/alpha_const.py @@ -76,164 +76,166 @@ Alpha_REG_ENDING = 65 # Alpha instruction -Alpha_INS_INVALID = 66 -Alpha_INS_ADDL = 67 -Alpha_INS_ADDQ = 68 -Alpha_INS_ADDSsSU = 69 -Alpha_INS_ADDTsSU = 70 -Alpha_INS_AND = 71 -Alpha_INS_BEQ = 72 -Alpha_INS_BGE = 73 -Alpha_INS_BGT = 74 -Alpha_INS_BIC = 75 -Alpha_INS_BIS = 76 -Alpha_INS_BLBC = 77 -Alpha_INS_BLBS = 78 -Alpha_INS_BLE = 79 -Alpha_INS_BLT = 80 -Alpha_INS_BNE = 81 -Alpha_INS_BR = 82 -Alpha_INS_BSR = 83 -Alpha_INS_CMOVEQ = 84 -Alpha_INS_CMOVGE = 85 -Alpha_INS_CMOVGT = 86 -Alpha_INS_CMOVLBC = 87 -Alpha_INS_CMOVLBS = 88 -Alpha_INS_CMOVLE = 89 -Alpha_INS_CMOVLT = 90 -Alpha_INS_CMOVNE = 91 -Alpha_INS_CMPBGE = 92 -Alpha_INS_CMPEQ = 93 -Alpha_INS_CMPLE = 94 -Alpha_INS_CMPLT = 95 -Alpha_INS_CMPTEQsSU = 96 -Alpha_INS_CMPTLEsSU = 97 -Alpha_INS_CMPTLTsSU = 98 -Alpha_INS_CMPTUNsSU = 99 -Alpha_INS_CMPULE = 100 -Alpha_INS_CMPULT = 101 -Alpha_INS_COND_BRANCH = 102 -Alpha_INS_CPYSE = 103 -Alpha_INS_CPYSN = 104 -Alpha_INS_CPYS = 105 -Alpha_INS_CTLZ = 106 -Alpha_INS_CTPOP = 107 -Alpha_INS_CTTZ = 108 -Alpha_INS_CVTQSsSUI = 109 -Alpha_INS_CVTQTsSUI = 110 -Alpha_INS_CVTSTsS = 111 -Alpha_INS_CVTTQsSVC = 112 -Alpha_INS_CVTTSsSUI = 113 -Alpha_INS_DIVSsSU = 114 -Alpha_INS_DIVTsSU = 115 -Alpha_INS_ECB = 116 -Alpha_INS_EQV = 117 -Alpha_INS_EXCB = 118 -Alpha_INS_EXTBL = 119 -Alpha_INS_EXTLH = 120 -Alpha_INS_EXTLL = 121 -Alpha_INS_EXTQH = 122 -Alpha_INS_EXTQL = 123 -Alpha_INS_EXTWH = 124 -Alpha_INS_EXTWL = 125 -Alpha_INS_FBEQ = 126 -Alpha_INS_FBGE = 127 -Alpha_INS_FBGT = 128 -Alpha_INS_FBLE = 129 -Alpha_INS_FBLT = 130 -Alpha_INS_FBNE = 131 -Alpha_INS_FCMOVEQ = 132 -Alpha_INS_FCMOVGE = 133 -Alpha_INS_FCMOVGT = 134 -Alpha_INS_FCMOVLE = 135 -Alpha_INS_FCMOVLT = 136 -Alpha_INS_FCMOVNE = 137 -Alpha_INS_FETCH = 138 -Alpha_INS_FETCH_M = 139 -Alpha_INS_FTOIS = 140 -Alpha_INS_FTOIT = 141 -Alpha_INS_INSBL = 142 -Alpha_INS_INSLH = 143 -Alpha_INS_INSLL = 144 -Alpha_INS_INSQH = 145 -Alpha_INS_INSQL = 146 -Alpha_INS_INSWH = 147 -Alpha_INS_INSWL = 148 -Alpha_INS_ITOFS = 149 -Alpha_INS_ITOFT = 150 -Alpha_INS_JMP = 151 -Alpha_INS_JSR = 152 -Alpha_INS_JSR_COROUTINE = 153 -Alpha_INS_LDA = 154 -Alpha_INS_LDAH = 155 -Alpha_INS_LDBU = 156 -Alpha_INS_LDL = 157 -Alpha_INS_LDL_L = 158 -Alpha_INS_LDQ = 159 -Alpha_INS_LDQ_L = 160 -Alpha_INS_LDQ_U = 161 -Alpha_INS_LDS = 162 -Alpha_INS_LDT = 163 -Alpha_INS_LDWU = 164 -Alpha_INS_MB = 165 -Alpha_INS_MSKBL = 166 -Alpha_INS_MSKLH = 167 -Alpha_INS_MSKLL = 168 -Alpha_INS_MSKQH = 169 -Alpha_INS_MSKQL = 170 -Alpha_INS_MSKWH = 171 -Alpha_INS_MSKWL = 172 -Alpha_INS_MULL = 173 -Alpha_INS_MULQ = 174 -Alpha_INS_MULSsSU = 175 -Alpha_INS_MULTsSU = 176 -Alpha_INS_ORNOT = 177 -Alpha_INS_RC = 178 -Alpha_INS_RET = 179 -Alpha_INS_RPCC = 180 -Alpha_INS_RS = 181 -Alpha_INS_S4ADDL = 182 -Alpha_INS_S4ADDQ = 183 -Alpha_INS_S4SUBL = 184 -Alpha_INS_S4SUBQ = 185 -Alpha_INS_S8ADDL = 186 -Alpha_INS_S8ADDQ = 187 -Alpha_INS_S8SUBL = 188 -Alpha_INS_S8SUBQ = 189 -Alpha_INS_SEXTB = 190 -Alpha_INS_SEXTW = 191 -Alpha_INS_SLL = 192 -Alpha_INS_SQRTSsSU = 193 -Alpha_INS_SQRTTsSU = 194 -Alpha_INS_SRA = 195 -Alpha_INS_SRL = 196 -Alpha_INS_STB = 197 -Alpha_INS_STL = 198 -Alpha_INS_STL_C = 199 -Alpha_INS_STQ = 200 -Alpha_INS_STQ_C = 201 -Alpha_INS_STQ_U = 202 -Alpha_INS_STS = 203 -Alpha_INS_STT = 204 -Alpha_INS_STW = 205 -Alpha_INS_SUBL = 206 -Alpha_INS_SUBQ = 207 -Alpha_INS_SUBSsSU = 208 -Alpha_INS_SUBTsSU = 209 -Alpha_INS_TRAPB = 210 -Alpha_INS_UMULH = 211 -Alpha_INS_WH64 = 212 -Alpha_INS_WH64EN = 213 -Alpha_INS_WMB = 214 -Alpha_INS_XOR = 215 -Alpha_INS_ZAPNOT = 216 -ALPHA_INS_ENDING = 217 + +Alpha_INS_INVALID = 0 +Alpha_INS_ADDL = 1 +Alpha_INS_ADDQ = 2 +Alpha_INS_ADDSsSU = 3 +Alpha_INS_ADDTsSU = 4 +Alpha_INS_AND = 5 +Alpha_INS_BEQ = 6 +Alpha_INS_BGE = 7 +Alpha_INS_BGT = 8 +Alpha_INS_BIC = 9 +Alpha_INS_BIS = 10 +Alpha_INS_BLBC = 11 +Alpha_INS_BLBS = 12 +Alpha_INS_BLE = 13 +Alpha_INS_BLT = 14 +Alpha_INS_BNE = 15 +Alpha_INS_BR = 16 +Alpha_INS_BSR = 17 +Alpha_INS_CMOVEQ = 18 +Alpha_INS_CMOVGE = 19 +Alpha_INS_CMOVGT = 20 +Alpha_INS_CMOVLBC = 21 +Alpha_INS_CMOVLBS = 22 +Alpha_INS_CMOVLE = 23 +Alpha_INS_CMOVLT = 24 +Alpha_INS_CMOVNE = 25 +Alpha_INS_CMPBGE = 26 +Alpha_INS_CMPEQ = 27 +Alpha_INS_CMPLE = 28 +Alpha_INS_CMPLT = 29 +Alpha_INS_CMPTEQsSU = 30 +Alpha_INS_CMPTLEsSU = 31 +Alpha_INS_CMPTLTsSU = 32 +Alpha_INS_CMPTUNsSU = 33 +Alpha_INS_CMPULE = 34 +Alpha_INS_CMPULT = 35 +Alpha_INS_COND_BRANCH = 36 +Alpha_INS_CPYSE = 37 +Alpha_INS_CPYSN = 38 +Alpha_INS_CPYS = 39 +Alpha_INS_CTLZ = 40 +Alpha_INS_CTPOP = 41 +Alpha_INS_CTTZ = 42 +Alpha_INS_CVTQSsSUI = 43 +Alpha_INS_CVTQTsSUI = 44 +Alpha_INS_CVTSTsS = 45 +Alpha_INS_CVTTQsSVC = 46 +Alpha_INS_CVTTSsSUI = 47 +Alpha_INS_DIVSsSU = 48 +Alpha_INS_DIVTsSU = 49 +Alpha_INS_ECB = 50 +Alpha_INS_EQV = 51 +Alpha_INS_EXCB = 52 +Alpha_INS_EXTBL = 53 +Alpha_INS_EXTLH = 54 +Alpha_INS_EXTLL = 55 +Alpha_INS_EXTQH = 56 +Alpha_INS_EXTQL = 57 +Alpha_INS_EXTWH = 58 +Alpha_INS_EXTWL = 59 +Alpha_INS_FBEQ = 60 +Alpha_INS_FBGE = 61 +Alpha_INS_FBGT = 62 +Alpha_INS_FBLE = 63 +Alpha_INS_FBLT = 64 +Alpha_INS_FBNE = 65 +Alpha_INS_FCMOVEQ = 66 +Alpha_INS_FCMOVGE = 67 +Alpha_INS_FCMOVGT = 68 +Alpha_INS_FCMOVLE = 69 +Alpha_INS_FCMOVLT = 70 +Alpha_INS_FCMOVNE = 71 +Alpha_INS_FETCH = 72 +Alpha_INS_FETCH_M = 73 +Alpha_INS_FTOIS = 74 +Alpha_INS_FTOIT = 75 +Alpha_INS_INSBL = 76 +Alpha_INS_INSLH = 77 +Alpha_INS_INSLL = 78 +Alpha_INS_INSQH = 79 +Alpha_INS_INSQL = 80 +Alpha_INS_INSWH = 81 +Alpha_INS_INSWL = 82 +Alpha_INS_ITOFS = 83 +Alpha_INS_ITOFT = 84 +Alpha_INS_JMP = 85 +Alpha_INS_JSR = 86 +Alpha_INS_JSR_COROUTINE = 87 +Alpha_INS_LDA = 88 +Alpha_INS_LDAH = 89 +Alpha_INS_LDBU = 90 +Alpha_INS_LDL = 91 +Alpha_INS_LDL_L = 92 +Alpha_INS_LDQ = 93 +Alpha_INS_LDQ_L = 94 +Alpha_INS_LDQ_U = 95 +Alpha_INS_LDS = 96 +Alpha_INS_LDT = 97 +Alpha_INS_LDWU = 98 +Alpha_INS_MB = 99 +Alpha_INS_MSKBL = 100 +Alpha_INS_MSKLH = 101 +Alpha_INS_MSKLL = 102 +Alpha_INS_MSKQH = 103 +Alpha_INS_MSKQL = 104 +Alpha_INS_MSKWH = 105 +Alpha_INS_MSKWL = 106 +Alpha_INS_MULL = 107 +Alpha_INS_MULQ = 108 +Alpha_INS_MULSsSU = 109 +Alpha_INS_MULTsSU = 110 +Alpha_INS_ORNOT = 111 +Alpha_INS_RC = 112 +Alpha_INS_RET = 113 +Alpha_INS_RPCC = 114 +Alpha_INS_RS = 115 +Alpha_INS_S4ADDL = 116 +Alpha_INS_S4ADDQ = 117 +Alpha_INS_S4SUBL = 118 +Alpha_INS_S4SUBQ = 119 +Alpha_INS_S8ADDL = 120 +Alpha_INS_S8ADDQ = 121 +Alpha_INS_S8SUBL = 122 +Alpha_INS_S8SUBQ = 123 +Alpha_INS_SEXTB = 124 +Alpha_INS_SEXTW = 125 +Alpha_INS_SLL = 126 +Alpha_INS_SQRTSsSU = 127 +Alpha_INS_SQRTTsSU = 128 +Alpha_INS_SRA = 129 +Alpha_INS_SRL = 130 +Alpha_INS_STB = 131 +Alpha_INS_STL = 132 +Alpha_INS_STL_C = 133 +Alpha_INS_STQ = 134 +Alpha_INS_STQ_C = 135 +Alpha_INS_STQ_U = 136 +Alpha_INS_STS = 137 +Alpha_INS_STT = 138 +Alpha_INS_STW = 139 +Alpha_INS_SUBL = 140 +Alpha_INS_SUBQ = 141 +Alpha_INS_SUBSsSU = 142 +Alpha_INS_SUBTsSU = 143 +Alpha_INS_TRAPB = 144 +Alpha_INS_UMULH = 145 +Alpha_INS_WH64 = 146 +Alpha_INS_WH64EN = 147 +Alpha_INS_WMB = 148 +Alpha_INS_XOR = 149 +Alpha_INS_ZAPNOT = 150 +ALPHA_INS_ENDING = 151 # Group of Alpha instructions -Alpha_GRP_INVALID = 218 + +Alpha_GRP_INVALID = 0 # Generic groups -Alpha_GRP_CALL = 219 -Alpha_GRP_JUMP = 220 -Alpha_GRP_BRANCH_RELATIVE = 221 -Alpha_GRP_ENDING = 222 +Alpha_GRP_CALL = 1 +Alpha_GRP_JUMP = 2 +Alpha_GRP_BRANCH_RELATIVE = 3 +Alpha_GRP_ENDING = 4 diff --git a/bindings/python/capstone/arm.py b/bindings/python/capstone/arm.py index 32718f497c..8c2fe9266e 100644 --- a/bindings/python/capstone/arm.py +++ b/bindings/python/capstone/arm.py @@ -12,6 +12,7 @@ class ArmOpMem(ctypes.Structure): ('scale', ctypes.c_int), ('disp', ctypes.c_int), ('lshift', ctypes.c_int), + ('align', ctypes.c_uint), ) class ArmOpShift(ctypes.Structure): @@ -38,7 +39,7 @@ class ArmOpValue(ctypes.Union): _fields_ = ( ('reg', ctypes.c_uint), ('sysop', ArmOpSysop), - ('imm', ctypes.c_int32), + ('imm', ctypes.c_int64), ('pred', ctypes.c_int), ('fp', ctypes.c_double), ('mem', ArmOpMem), diff --git a/bindings/python/capstone/arm_const.py b/bindings/python/capstone/arm_const.py index 2e6a13808b..804481bc49 100644 --- a/bindings/python/capstone/arm_const.py +++ b/bindings/python/capstone/arm_const.py @@ -48,22 +48,23 @@ ARM_SFT_LSR_REG = 8 ARM_SFT_ROR_REG = 9 ARM_SFT_RRX_REG = 10 -ARM_MB_RESERVED_0 = 11 -ARM_MB_OSHLD = 12 -ARM_MB_OSHST = 13 -ARM_MB_OSH = 14 -ARM_MB_RESERVED_4 = 15 -ARM_MB_NSHLD = 16 -ARM_MB_NSHST = 17 -ARM_MB_NSH = 18 -ARM_MB_RESERVED_8 = 19 -ARM_MB_ISHLD = 20 -ARM_MB_ISHST = 21 -ARM_MB_ISH = 22 -ARM_MB_RESERVED_12 = 23 -ARM_MB_LD = 24 -ARM_MB_ST = 25 -ARM_MB_SY = 26 + +ARM_MB_RESERVED_0 = 0 +ARM_MB_OSHLD = 1 +ARM_MB_OSHST = 2 +ARM_MB_OSH = 3 +ARM_MB_RESERVED_4 = 4 +ARM_MB_NSHLD = 5 +ARM_MB_NSHST = 6 +ARM_MB_NSH = 7 +ARM_MB_RESERVED_8 = 8 +ARM_MB_ISHLD = 9 +ARM_MB_ISHST = 10 +ARM_MB_ISH = 11 +ARM_MB_RESERVED_12 = 12 +ARM_MB_LD = 13 +ARM_MB_ST = 14 +ARM_MB_SY = 15 ARM_FIELD_SPSR_C = 1 ARM_FIELD_SPSR_X = 2 ARM_FIELD_SPSR_S = 4 @@ -542,694 +543,695 @@ ARM_REG_SL = ARM_REG_R10 ARM_REG_FP = ARM_REG_R11 ARM_REG_IP = ARM_REG_R12 -ARM_INS_INVALID = 297 -ARM_INS_ASR = 298 -ARM_INS_IT = 299 -ARM_INS_LDRBT = 300 -ARM_INS_LDR = 301 -ARM_INS_LDRHT = 302 -ARM_INS_LDRSBT = 303 -ARM_INS_LDRSHT = 304 -ARM_INS_LDRT = 305 -ARM_INS_LSL = 306 -ARM_INS_LSR = 307 -ARM_INS_ROR = 308 -ARM_INS_RRX = 309 -ARM_INS_STRBT = 310 -ARM_INS_STRT = 311 -ARM_INS_VLD1 = 312 -ARM_INS_VLD2 = 313 -ARM_INS_VLD3 = 314 -ARM_INS_VLD4 = 315 -ARM_INS_VST1 = 316 -ARM_INS_VST2 = 317 -ARM_INS_VST3 = 318 -ARM_INS_VST4 = 319 -ARM_INS_LDRB = 320 -ARM_INS_LDRH = 321 -ARM_INS_LDRSB = 322 -ARM_INS_LDRSH = 323 -ARM_INS_MOVS = 324 -ARM_INS_MOV = 325 -ARM_INS_STR = 326 -ARM_INS_ADC = 327 -ARM_INS_ADD = 328 -ARM_INS_ADR = 329 -ARM_INS_AESD = 330 -ARM_INS_AESE = 331 -ARM_INS_AESIMC = 332 -ARM_INS_AESMC = 333 -ARM_INS_AND = 334 -ARM_INS_VDOT = 335 -ARM_INS_VCVT = 336 -ARM_INS_VCVTB = 337 -ARM_INS_VCVTT = 338 -ARM_INS_BFC = 339 -ARM_INS_BFI = 340 -ARM_INS_BIC = 341 -ARM_INS_BKPT = 342 -ARM_INS_BL = 343 -ARM_INS_BLX = 344 -ARM_INS_BX = 345 -ARM_INS_BXJ = 346 -ARM_INS_B = 347 -ARM_INS_CX1 = 348 -ARM_INS_CX1A = 349 -ARM_INS_CX1D = 350 -ARM_INS_CX1DA = 351 -ARM_INS_CX2 = 352 -ARM_INS_CX2A = 353 -ARM_INS_CX2D = 354 -ARM_INS_CX2DA = 355 -ARM_INS_CX3 = 356 -ARM_INS_CX3A = 357 -ARM_INS_CX3D = 358 -ARM_INS_CX3DA = 359 -ARM_INS_VCX1A = 360 -ARM_INS_VCX1 = 361 -ARM_INS_VCX2A = 362 -ARM_INS_VCX2 = 363 -ARM_INS_VCX3A = 364 -ARM_INS_VCX3 = 365 -ARM_INS_CDP = 366 -ARM_INS_CDP2 = 367 -ARM_INS_CLREX = 368 -ARM_INS_CLZ = 369 -ARM_INS_CMN = 370 -ARM_INS_CMP = 371 -ARM_INS_CPS = 372 -ARM_INS_CRC32B = 373 -ARM_INS_CRC32CB = 374 -ARM_INS_CRC32CH = 375 -ARM_INS_CRC32CW = 376 -ARM_INS_CRC32H = 377 -ARM_INS_CRC32W = 378 -ARM_INS_DBG = 379 -ARM_INS_DMB = 380 -ARM_INS_DSB = 381 -ARM_INS_EOR = 382 -ARM_INS_ERET = 383 -ARM_INS_VMOV = 384 -ARM_INS_FLDMDBX = 385 -ARM_INS_FLDMIAX = 386 -ARM_INS_VMRS = 387 -ARM_INS_FSTMDBX = 388 -ARM_INS_FSTMIAX = 389 -ARM_INS_HINT = 390 -ARM_INS_HLT = 391 -ARM_INS_HVC = 392 -ARM_INS_ISB = 393 -ARM_INS_LDA = 394 -ARM_INS_LDAB = 395 -ARM_INS_LDAEX = 396 -ARM_INS_LDAEXB = 397 -ARM_INS_LDAEXD = 398 -ARM_INS_LDAEXH = 399 -ARM_INS_LDAH = 400 -ARM_INS_LDC2L = 401 -ARM_INS_LDC2 = 402 -ARM_INS_LDCL = 403 -ARM_INS_LDC = 404 -ARM_INS_LDMDA = 405 -ARM_INS_LDMDB = 406 -ARM_INS_LDM = 407 -ARM_INS_LDMIB = 408 -ARM_INS_LDRD = 409 -ARM_INS_LDREX = 410 -ARM_INS_LDREXB = 411 -ARM_INS_LDREXD = 412 -ARM_INS_LDREXH = 413 -ARM_INS_MCR = 414 -ARM_INS_MCR2 = 415 -ARM_INS_MCRR = 416 -ARM_INS_MCRR2 = 417 -ARM_INS_MLA = 418 -ARM_INS_MLS = 419 -ARM_INS_MOVT = 420 -ARM_INS_MOVW = 421 -ARM_INS_MRC = 422 -ARM_INS_MRC2 = 423 -ARM_INS_MRRC = 424 -ARM_INS_MRRC2 = 425 -ARM_INS_MRS = 426 -ARM_INS_MSR = 427 -ARM_INS_MUL = 428 -ARM_INS_ASRL = 429 -ARM_INS_DLSTP = 430 -ARM_INS_LCTP = 431 -ARM_INS_LETP = 432 -ARM_INS_LSLL = 433 -ARM_INS_LSRL = 434 -ARM_INS_SQRSHR = 435 -ARM_INS_SQRSHRL = 436 -ARM_INS_SQSHL = 437 -ARM_INS_SQSHLL = 438 -ARM_INS_SRSHR = 439 -ARM_INS_SRSHRL = 440 -ARM_INS_UQRSHL = 441 -ARM_INS_UQRSHLL = 442 -ARM_INS_UQSHL = 443 -ARM_INS_UQSHLL = 444 -ARM_INS_URSHR = 445 -ARM_INS_URSHRL = 446 -ARM_INS_VABAV = 447 -ARM_INS_VABD = 448 -ARM_INS_VABS = 449 -ARM_INS_VADC = 450 -ARM_INS_VADCI = 451 -ARM_INS_VADDLVA = 452 -ARM_INS_VADDLV = 453 -ARM_INS_VADDVA = 454 -ARM_INS_VADDV = 455 -ARM_INS_VADD = 456 -ARM_INS_VAND = 457 -ARM_INS_VBIC = 458 -ARM_INS_VBRSR = 459 -ARM_INS_VCADD = 460 -ARM_INS_VCLS = 461 -ARM_INS_VCLZ = 462 -ARM_INS_VCMLA = 463 -ARM_INS_VCMP = 464 -ARM_INS_VCMUL = 465 -ARM_INS_VCTP = 466 -ARM_INS_VCVTA = 467 -ARM_INS_VCVTM = 468 -ARM_INS_VCVTN = 469 -ARM_INS_VCVTP = 470 -ARM_INS_VDDUP = 471 -ARM_INS_VDUP = 472 -ARM_INS_VDWDUP = 473 -ARM_INS_VEOR = 474 -ARM_INS_VFMAS = 475 -ARM_INS_VFMA = 476 -ARM_INS_VFMS = 477 -ARM_INS_VHADD = 478 -ARM_INS_VHCADD = 479 -ARM_INS_VHSUB = 480 -ARM_INS_VIDUP = 481 -ARM_INS_VIWDUP = 482 -ARM_INS_VLD20 = 483 -ARM_INS_VLD21 = 484 -ARM_INS_VLD40 = 485 -ARM_INS_VLD41 = 486 -ARM_INS_VLD42 = 487 -ARM_INS_VLD43 = 488 -ARM_INS_VLDRB = 489 -ARM_INS_VLDRD = 490 -ARM_INS_VLDRH = 491 -ARM_INS_VLDRW = 492 -ARM_INS_VMAXAV = 493 -ARM_INS_VMAXA = 494 -ARM_INS_VMAXNMAV = 495 -ARM_INS_VMAXNMA = 496 -ARM_INS_VMAXNMV = 497 -ARM_INS_VMAXNM = 498 -ARM_INS_VMAXV = 499 -ARM_INS_VMAX = 500 -ARM_INS_VMINAV = 501 -ARM_INS_VMINA = 502 -ARM_INS_VMINNMAV = 503 -ARM_INS_VMINNMA = 504 -ARM_INS_VMINNMV = 505 -ARM_INS_VMINNM = 506 -ARM_INS_VMINV = 507 -ARM_INS_VMIN = 508 -ARM_INS_VMLADAVA = 509 -ARM_INS_VMLADAVAX = 510 -ARM_INS_VMLADAV = 511 -ARM_INS_VMLADAVX = 512 -ARM_INS_VMLALDAVA = 513 -ARM_INS_VMLALDAVAX = 514 -ARM_INS_VMLALDAV = 515 -ARM_INS_VMLALDAVX = 516 -ARM_INS_VMLAS = 517 -ARM_INS_VMLA = 518 -ARM_INS_VMLSDAVA = 519 -ARM_INS_VMLSDAVAX = 520 -ARM_INS_VMLSDAV = 521 -ARM_INS_VMLSDAVX = 522 -ARM_INS_VMLSLDAVA = 523 -ARM_INS_VMLSLDAVAX = 524 -ARM_INS_VMLSLDAV = 525 -ARM_INS_VMLSLDAVX = 526 -ARM_INS_VMOVLB = 527 -ARM_INS_VMOVLT = 528 -ARM_INS_VMOVNB = 529 -ARM_INS_VMOVNT = 530 -ARM_INS_VMULH = 531 -ARM_INS_VMULLB = 532 -ARM_INS_VMULLT = 533 -ARM_INS_VMUL = 534 -ARM_INS_VMVN = 535 -ARM_INS_VNEG = 536 -ARM_INS_VORN = 537 -ARM_INS_VORR = 538 -ARM_INS_VPNOT = 539 -ARM_INS_VPSEL = 540 -ARM_INS_VPST = 541 -ARM_INS_VPT = 542 -ARM_INS_VQABS = 543 -ARM_INS_VQADD = 544 -ARM_INS_VQDMLADHX = 545 -ARM_INS_VQDMLADH = 546 -ARM_INS_VQDMLAH = 547 -ARM_INS_VQDMLASH = 548 -ARM_INS_VQDMLSDHX = 549 -ARM_INS_VQDMLSDH = 550 -ARM_INS_VQDMULH = 551 -ARM_INS_VQDMULLB = 552 -ARM_INS_VQDMULLT = 553 -ARM_INS_VQMOVNB = 554 -ARM_INS_VQMOVNT = 555 -ARM_INS_VQMOVUNB = 556 -ARM_INS_VQMOVUNT = 557 -ARM_INS_VQNEG = 558 -ARM_INS_VQRDMLADHX = 559 -ARM_INS_VQRDMLADH = 560 -ARM_INS_VQRDMLAH = 561 -ARM_INS_VQRDMLASH = 562 -ARM_INS_VQRDMLSDHX = 563 -ARM_INS_VQRDMLSDH = 564 -ARM_INS_VQRDMULH = 565 -ARM_INS_VQRSHL = 566 -ARM_INS_VQRSHRNB = 567 -ARM_INS_VQRSHRNT = 568 -ARM_INS_VQRSHRUNB = 569 -ARM_INS_VQRSHRUNT = 570 -ARM_INS_VQSHLU = 571 -ARM_INS_VQSHL = 572 -ARM_INS_VQSHRNB = 573 -ARM_INS_VQSHRNT = 574 -ARM_INS_VQSHRUNB = 575 -ARM_INS_VQSHRUNT = 576 -ARM_INS_VQSUB = 577 -ARM_INS_VREV16 = 578 -ARM_INS_VREV32 = 579 -ARM_INS_VREV64 = 580 -ARM_INS_VRHADD = 581 -ARM_INS_VRINTA = 582 -ARM_INS_VRINTM = 583 -ARM_INS_VRINTN = 584 -ARM_INS_VRINTP = 585 -ARM_INS_VRINTX = 586 -ARM_INS_VRINTZ = 587 -ARM_INS_VRMLALDAVHA = 588 -ARM_INS_VRMLALDAVHAX = 589 -ARM_INS_VRMLALDAVH = 590 -ARM_INS_VRMLALDAVHX = 591 -ARM_INS_VRMLSLDAVHA = 592 -ARM_INS_VRMLSLDAVHAX = 593 -ARM_INS_VRMLSLDAVH = 594 -ARM_INS_VRMLSLDAVHX = 595 -ARM_INS_VRMULH = 596 -ARM_INS_VRSHL = 597 -ARM_INS_VRSHRNB = 598 -ARM_INS_VRSHRNT = 599 -ARM_INS_VRSHR = 600 -ARM_INS_VSBC = 601 -ARM_INS_VSBCI = 602 -ARM_INS_VSHLC = 603 -ARM_INS_VSHLLB = 604 -ARM_INS_VSHLLT = 605 -ARM_INS_VSHL = 606 -ARM_INS_VSHRNB = 607 -ARM_INS_VSHRNT = 608 -ARM_INS_VSHR = 609 -ARM_INS_VSLI = 610 -ARM_INS_VSRI = 611 -ARM_INS_VST20 = 612 -ARM_INS_VST21 = 613 -ARM_INS_VST40 = 614 -ARM_INS_VST41 = 615 -ARM_INS_VST42 = 616 -ARM_INS_VST43 = 617 -ARM_INS_VSTRB = 618 -ARM_INS_VSTRD = 619 -ARM_INS_VSTRH = 620 -ARM_INS_VSTRW = 621 -ARM_INS_VSUB = 622 -ARM_INS_WLSTP = 623 -ARM_INS_MVN = 624 -ARM_INS_ORR = 625 -ARM_INS_PKHBT = 626 -ARM_INS_PKHTB = 627 -ARM_INS_PLDW = 628 -ARM_INS_PLD = 629 -ARM_INS_PLI = 630 -ARM_INS_QADD = 631 -ARM_INS_QADD16 = 632 -ARM_INS_QADD8 = 633 -ARM_INS_QASX = 634 -ARM_INS_QDADD = 635 -ARM_INS_QDSUB = 636 -ARM_INS_QSAX = 637 -ARM_INS_QSUB = 638 -ARM_INS_QSUB16 = 639 -ARM_INS_QSUB8 = 640 -ARM_INS_RBIT = 641 -ARM_INS_REV = 642 -ARM_INS_REV16 = 643 -ARM_INS_REVSH = 644 -ARM_INS_RFEDA = 645 -ARM_INS_RFEDB = 646 -ARM_INS_RFEIA = 647 -ARM_INS_RFEIB = 648 -ARM_INS_RSB = 649 -ARM_INS_RSC = 650 -ARM_INS_SADD16 = 651 -ARM_INS_SADD8 = 652 -ARM_INS_SASX = 653 -ARM_INS_SB = 654 -ARM_INS_SBC = 655 -ARM_INS_SBFX = 656 -ARM_INS_SDIV = 657 -ARM_INS_SEL = 658 -ARM_INS_SETEND = 659 -ARM_INS_SETPAN = 660 -ARM_INS_SHA1C = 661 -ARM_INS_SHA1H = 662 -ARM_INS_SHA1M = 663 -ARM_INS_SHA1P = 664 -ARM_INS_SHA1SU0 = 665 -ARM_INS_SHA1SU1 = 666 -ARM_INS_SHA256H = 667 -ARM_INS_SHA256H2 = 668 -ARM_INS_SHA256SU0 = 669 -ARM_INS_SHA256SU1 = 670 -ARM_INS_SHADD16 = 671 -ARM_INS_SHADD8 = 672 -ARM_INS_SHASX = 673 -ARM_INS_SHSAX = 674 -ARM_INS_SHSUB16 = 675 -ARM_INS_SHSUB8 = 676 -ARM_INS_SMC = 677 -ARM_INS_SMLABB = 678 -ARM_INS_SMLABT = 679 -ARM_INS_SMLAD = 680 -ARM_INS_SMLADX = 681 -ARM_INS_SMLAL = 682 -ARM_INS_SMLALBB = 683 -ARM_INS_SMLALBT = 684 -ARM_INS_SMLALD = 685 -ARM_INS_SMLALDX = 686 -ARM_INS_SMLALTB = 687 -ARM_INS_SMLALTT = 688 -ARM_INS_SMLATB = 689 -ARM_INS_SMLATT = 690 -ARM_INS_SMLAWB = 691 -ARM_INS_SMLAWT = 692 -ARM_INS_SMLSD = 693 -ARM_INS_SMLSDX = 694 -ARM_INS_SMLSLD = 695 -ARM_INS_SMLSLDX = 696 -ARM_INS_SMMLA = 697 -ARM_INS_SMMLAR = 698 -ARM_INS_SMMLS = 699 -ARM_INS_SMMLSR = 700 -ARM_INS_SMMUL = 701 -ARM_INS_SMMULR = 702 -ARM_INS_SMUAD = 703 -ARM_INS_SMUADX = 704 -ARM_INS_SMULBB = 705 -ARM_INS_SMULBT = 706 -ARM_INS_SMULL = 707 -ARM_INS_SMULTB = 708 -ARM_INS_SMULTT = 709 -ARM_INS_SMULWB = 710 -ARM_INS_SMULWT = 711 -ARM_INS_SMUSD = 712 -ARM_INS_SMUSDX = 713 -ARM_INS_SRSDA = 714 -ARM_INS_SRSDB = 715 -ARM_INS_SRSIA = 716 -ARM_INS_SRSIB = 717 -ARM_INS_SSAT = 718 -ARM_INS_SSAT16 = 719 -ARM_INS_SSAX = 720 -ARM_INS_SSUB16 = 721 -ARM_INS_SSUB8 = 722 -ARM_INS_STC2L = 723 -ARM_INS_STC2 = 724 -ARM_INS_STCL = 725 -ARM_INS_STC = 726 -ARM_INS_STL = 727 -ARM_INS_STLB = 728 -ARM_INS_STLEX = 729 -ARM_INS_STLEXB = 730 -ARM_INS_STLEXD = 731 -ARM_INS_STLEXH = 732 -ARM_INS_STLH = 733 -ARM_INS_STMDA = 734 -ARM_INS_STMDB = 735 -ARM_INS_STM = 736 -ARM_INS_STMIB = 737 -ARM_INS_STRB = 738 -ARM_INS_STRD = 739 -ARM_INS_STREX = 740 -ARM_INS_STREXB = 741 -ARM_INS_STREXD = 742 -ARM_INS_STREXH = 743 -ARM_INS_STRH = 744 -ARM_INS_STRHT = 745 -ARM_INS_SUB = 746 -ARM_INS_SVC = 747 -ARM_INS_SWP = 748 -ARM_INS_SWPB = 749 -ARM_INS_SXTAB = 750 -ARM_INS_SXTAB16 = 751 -ARM_INS_SXTAH = 752 -ARM_INS_SXTB = 753 -ARM_INS_SXTB16 = 754 -ARM_INS_SXTH = 755 -ARM_INS_TEQ = 756 -ARM_INS_TRAP = 757 -ARM_INS_TSB = 758 -ARM_INS_TST = 759 -ARM_INS_UADD16 = 760 -ARM_INS_UADD8 = 761 -ARM_INS_UASX = 762 -ARM_INS_UBFX = 763 -ARM_INS_UDF = 764 -ARM_INS_UDIV = 765 -ARM_INS_UHADD16 = 766 -ARM_INS_UHADD8 = 767 -ARM_INS_UHASX = 768 -ARM_INS_UHSAX = 769 -ARM_INS_UHSUB16 = 770 -ARM_INS_UHSUB8 = 771 -ARM_INS_UMAAL = 772 -ARM_INS_UMLAL = 773 -ARM_INS_UMULL = 774 -ARM_INS_UQADD16 = 775 -ARM_INS_UQADD8 = 776 -ARM_INS_UQASX = 777 -ARM_INS_UQSAX = 778 -ARM_INS_UQSUB16 = 779 -ARM_INS_UQSUB8 = 780 -ARM_INS_USAD8 = 781 -ARM_INS_USADA8 = 782 -ARM_INS_USAT = 783 -ARM_INS_USAT16 = 784 -ARM_INS_USAX = 785 -ARM_INS_USUB16 = 786 -ARM_INS_USUB8 = 787 -ARM_INS_UXTAB = 788 -ARM_INS_UXTAB16 = 789 -ARM_INS_UXTAH = 790 -ARM_INS_UXTB = 791 -ARM_INS_UXTB16 = 792 -ARM_INS_UXTH = 793 -ARM_INS_VABAL = 794 -ARM_INS_VABA = 795 -ARM_INS_VABDL = 796 -ARM_INS_VACGE = 797 -ARM_INS_VACGT = 798 -ARM_INS_VADDHN = 799 -ARM_INS_VADDL = 800 -ARM_INS_VADDW = 801 -ARM_INS_VFMAB = 802 -ARM_INS_VFMAT = 803 -ARM_INS_VBIF = 804 -ARM_INS_VBIT = 805 -ARM_INS_VBSL = 806 -ARM_INS_VCEQ = 807 -ARM_INS_VCGE = 808 -ARM_INS_VCGT = 809 -ARM_INS_VCLE = 810 -ARM_INS_VCLT = 811 -ARM_INS_VCMPE = 812 -ARM_INS_VCNT = 813 -ARM_INS_VDIV = 814 -ARM_INS_VEXT = 815 -ARM_INS_VFMAL = 816 -ARM_INS_VFMSL = 817 -ARM_INS_VFNMA = 818 -ARM_INS_VFNMS = 819 -ARM_INS_VINS = 820 -ARM_INS_VJCVT = 821 -ARM_INS_VLDMDB = 822 -ARM_INS_VLDMIA = 823 -ARM_INS_VLDR = 824 -ARM_INS_VLLDM = 825 -ARM_INS_VLSTM = 826 -ARM_INS_VMLAL = 827 -ARM_INS_VMLS = 828 -ARM_INS_VMLSL = 829 -ARM_INS_VMMLA = 830 -ARM_INS_VMOVX = 831 -ARM_INS_VMOVL = 832 -ARM_INS_VMOVN = 833 -ARM_INS_VMSR = 834 -ARM_INS_VMULL = 835 -ARM_INS_VNMLA = 836 -ARM_INS_VNMLS = 837 -ARM_INS_VNMUL = 838 -ARM_INS_VPADAL = 839 -ARM_INS_VPADDL = 840 -ARM_INS_VPADD = 841 -ARM_INS_VPMAX = 842 -ARM_INS_VPMIN = 843 -ARM_INS_VQDMLAL = 844 -ARM_INS_VQDMLSL = 845 -ARM_INS_VQDMULL = 846 -ARM_INS_VQMOVUN = 847 -ARM_INS_VQMOVN = 848 -ARM_INS_VQRDMLSH = 849 -ARM_INS_VQRSHRN = 850 -ARM_INS_VQRSHRUN = 851 -ARM_INS_VQSHRN = 852 -ARM_INS_VQSHRUN = 853 -ARM_INS_VRADDHN = 854 -ARM_INS_VRECPE = 855 -ARM_INS_VRECPS = 856 -ARM_INS_VRINTR = 857 -ARM_INS_VRSHRN = 858 -ARM_INS_VRSQRTE = 859 -ARM_INS_VRSQRTS = 860 -ARM_INS_VRSRA = 861 -ARM_INS_VRSUBHN = 862 -ARM_INS_VSCCLRM = 863 -ARM_INS_VSDOT = 864 -ARM_INS_VSELEQ = 865 -ARM_INS_VSELGE = 866 -ARM_INS_VSELGT = 867 -ARM_INS_VSELVS = 868 -ARM_INS_VSHLL = 869 -ARM_INS_VSHRN = 870 -ARM_INS_VSMMLA = 871 -ARM_INS_VSQRT = 872 -ARM_INS_VSRA = 873 -ARM_INS_VSTMDB = 874 -ARM_INS_VSTMIA = 875 -ARM_INS_VSTR = 876 -ARM_INS_VSUBHN = 877 -ARM_INS_VSUBL = 878 -ARM_INS_VSUBW = 879 -ARM_INS_VSUDOT = 880 -ARM_INS_VSWP = 881 -ARM_INS_VTBL = 882 -ARM_INS_VTBX = 883 -ARM_INS_VCVTR = 884 -ARM_INS_VTRN = 885 -ARM_INS_VTST = 886 -ARM_INS_VUDOT = 887 -ARM_INS_VUMMLA = 888 -ARM_INS_VUSDOT = 889 -ARM_INS_VUSMMLA = 890 -ARM_INS_VUZP = 891 -ARM_INS_VZIP = 892 -ARM_INS_ADDW = 893 -ARM_INS_AUT = 894 -ARM_INS_AUTG = 895 -ARM_INS_BFL = 896 -ARM_INS_BFLX = 897 -ARM_INS_BF = 898 -ARM_INS_BFCSEL = 899 -ARM_INS_BFX = 900 -ARM_INS_BTI = 901 -ARM_INS_BXAUT = 902 -ARM_INS_CLRM = 903 -ARM_INS_CSEL = 904 -ARM_INS_CSINC = 905 -ARM_INS_CSINV = 906 -ARM_INS_CSNEG = 907 -ARM_INS_DCPS1 = 908 -ARM_INS_DCPS2 = 909 -ARM_INS_DCPS3 = 910 -ARM_INS_DLS = 911 -ARM_INS_LE = 912 -ARM_INS_ORN = 913 -ARM_INS_PAC = 914 -ARM_INS_PACBTI = 915 -ARM_INS_PACG = 916 -ARM_INS_SG = 917 -ARM_INS_SUBS = 918 -ARM_INS_SUBW = 919 -ARM_INS_TBB = 920 -ARM_INS_TBH = 921 -ARM_INS_TT = 922 -ARM_INS_TTA = 923 -ARM_INS_TTAT = 924 -ARM_INS_TTT = 925 -ARM_INS_WLS = 926 -ARM_INS_BLXNS = 927 -ARM_INS_BXNS = 928 -ARM_INS_CBNZ = 929 -ARM_INS_CBZ = 930 -ARM_INS_POP = 931 -ARM_INS_PUSH = 932 -ARM_INS___BRKDIV0 = 933 -ARM_INS_ENDING = 934 -ARM_INS_ALIAS_BEGIN = 935 -ARM_INS_ALIAS_VMOV = 936 -ARM_INS_ALIAS_NOP = 937 -ARM_INS_ALIAS_YIELD = 938 -ARM_INS_ALIAS_WFE = 939 -ARM_INS_ALIAS_WFI = 940 -ARM_INS_ALIAS_SEV = 941 -ARM_INS_ALIAS_SEVL = 942 -ARM_INS_ALIAS_ESB = 943 -ARM_INS_ALIAS_CSDB = 944 -ARM_INS_ALIAS_CLRBHB = 945 -ARM_INS_ALIAS_PACBTI = 946 -ARM_INS_ALIAS_BTI = 947 -ARM_INS_ALIAS_PAC = 948 -ARM_INS_ALIAS_AUT = 949 -ARM_INS_ALIAS_SSBB = 950 -ARM_INS_ALIAS_PSSBB = 951 -ARM_INS_ALIAS_DFB = 952 -ARM_INS_ALIAS_CSETM = 953 -ARM_INS_ALIAS_CSET = 954 -ARM_INS_ALIAS_CINC = 955 -ARM_INS_ALIAS_CINV = 956 -ARM_INS_ALIAS_CNEG = 957 -ARM_INS_ALIAS_VMLAV = 958 -ARM_INS_ALIAS_VMLAVA = 959 -ARM_INS_ALIAS_VRMLALVH = 960 -ARM_INS_ALIAS_VRMLALVHA = 961 -ARM_INS_ALIAS_VMLALV = 962 -ARM_INS_ALIAS_VMLALVA = 963 -ARM_INS_ALIAS_VBIC = 964 -ARM_INS_ALIAS_VEOR = 965 -ARM_INS_ALIAS_VORN = 966 -ARM_INS_ALIAS_VORR = 967 -ARM_INS_ALIAS_VAND = 968 -ARM_INS_ALIAS_VPSEL = 969 -ARM_INS_ALIAS_ERET = 970 -ARM_INS_ALIAS_ASR = 971 -ARM_INS_ALIAS_LSL = 972 -ARM_INS_ALIAS_LSR = 973 -ARM_INS_ALIAS_ROR = 974 -ARM_INS_ALIAS_RRX = 975 -ARM_INS_ALIAS_UXTW = 976 -ARM_INS_ALIAS_LDM = 977 -ARM_INS_ALIAS_POP = 978 -ARM_INS_ALIAS_PUSH = 979 -ARM_INS_ALIAS_POPW = 980 -ARM_INS_ALIAS_PUSHW = 981 -ARM_INS_ALIAS_VPOP = 982 -ARM_INS_ALIAS_VPUSH = 983 -ARM_INS_ALIAS_END = 984 + +ARM_INS_INVALID = 0 +ARM_INS_ASR = 1 +ARM_INS_IT = 2 +ARM_INS_LDRBT = 3 +ARM_INS_LDR = 4 +ARM_INS_LDRHT = 5 +ARM_INS_LDRSBT = 6 +ARM_INS_LDRSHT = 7 +ARM_INS_LDRT = 8 +ARM_INS_LSL = 9 +ARM_INS_LSR = 10 +ARM_INS_ROR = 11 +ARM_INS_RRX = 12 +ARM_INS_STRBT = 13 +ARM_INS_STRT = 14 +ARM_INS_VLD1 = 15 +ARM_INS_VLD2 = 16 +ARM_INS_VLD3 = 17 +ARM_INS_VLD4 = 18 +ARM_INS_VST1 = 19 +ARM_INS_VST2 = 20 +ARM_INS_VST3 = 21 +ARM_INS_VST4 = 22 +ARM_INS_LDRB = 23 +ARM_INS_LDRH = 24 +ARM_INS_LDRSB = 25 +ARM_INS_LDRSH = 26 +ARM_INS_MOVS = 27 +ARM_INS_MOV = 28 +ARM_INS_STR = 29 +ARM_INS_ADC = 30 +ARM_INS_ADD = 31 +ARM_INS_ADR = 32 +ARM_INS_AESD = 33 +ARM_INS_AESE = 34 +ARM_INS_AESIMC = 35 +ARM_INS_AESMC = 36 +ARM_INS_AND = 37 +ARM_INS_VDOT = 38 +ARM_INS_VCVT = 39 +ARM_INS_VCVTB = 40 +ARM_INS_VCVTT = 41 +ARM_INS_BFC = 42 +ARM_INS_BFI = 43 +ARM_INS_BIC = 44 +ARM_INS_BKPT = 45 +ARM_INS_BL = 46 +ARM_INS_BLX = 47 +ARM_INS_BX = 48 +ARM_INS_BXJ = 49 +ARM_INS_B = 50 +ARM_INS_CX1 = 51 +ARM_INS_CX1A = 52 +ARM_INS_CX1D = 53 +ARM_INS_CX1DA = 54 +ARM_INS_CX2 = 55 +ARM_INS_CX2A = 56 +ARM_INS_CX2D = 57 +ARM_INS_CX2DA = 58 +ARM_INS_CX3 = 59 +ARM_INS_CX3A = 60 +ARM_INS_CX3D = 61 +ARM_INS_CX3DA = 62 +ARM_INS_VCX1A = 63 +ARM_INS_VCX1 = 64 +ARM_INS_VCX2A = 65 +ARM_INS_VCX2 = 66 +ARM_INS_VCX3A = 67 +ARM_INS_VCX3 = 68 +ARM_INS_CDP = 69 +ARM_INS_CDP2 = 70 +ARM_INS_CLREX = 71 +ARM_INS_CLZ = 72 +ARM_INS_CMN = 73 +ARM_INS_CMP = 74 +ARM_INS_CPS = 75 +ARM_INS_CRC32B = 76 +ARM_INS_CRC32CB = 77 +ARM_INS_CRC32CH = 78 +ARM_INS_CRC32CW = 79 +ARM_INS_CRC32H = 80 +ARM_INS_CRC32W = 81 +ARM_INS_DBG = 82 +ARM_INS_DMB = 83 +ARM_INS_DSB = 84 +ARM_INS_EOR = 85 +ARM_INS_ERET = 86 +ARM_INS_VMOV = 87 +ARM_INS_FLDMDBX = 88 +ARM_INS_FLDMIAX = 89 +ARM_INS_VMRS = 90 +ARM_INS_FSTMDBX = 91 +ARM_INS_FSTMIAX = 92 +ARM_INS_HINT = 93 +ARM_INS_HLT = 94 +ARM_INS_HVC = 95 +ARM_INS_ISB = 96 +ARM_INS_LDA = 97 +ARM_INS_LDAB = 98 +ARM_INS_LDAEX = 99 +ARM_INS_LDAEXB = 100 +ARM_INS_LDAEXD = 101 +ARM_INS_LDAEXH = 102 +ARM_INS_LDAH = 103 +ARM_INS_LDC2L = 104 +ARM_INS_LDC2 = 105 +ARM_INS_LDCL = 106 +ARM_INS_LDC = 107 +ARM_INS_LDMDA = 108 +ARM_INS_LDMDB = 109 +ARM_INS_LDM = 110 +ARM_INS_LDMIB = 111 +ARM_INS_LDRD = 112 +ARM_INS_LDREX = 113 +ARM_INS_LDREXB = 114 +ARM_INS_LDREXD = 115 +ARM_INS_LDREXH = 116 +ARM_INS_MCR = 117 +ARM_INS_MCR2 = 118 +ARM_INS_MCRR = 119 +ARM_INS_MCRR2 = 120 +ARM_INS_MLA = 121 +ARM_INS_MLS = 122 +ARM_INS_MOVT = 123 +ARM_INS_MOVW = 124 +ARM_INS_MRC = 125 +ARM_INS_MRC2 = 126 +ARM_INS_MRRC = 127 +ARM_INS_MRRC2 = 128 +ARM_INS_MRS = 129 +ARM_INS_MSR = 130 +ARM_INS_MUL = 131 +ARM_INS_ASRL = 132 +ARM_INS_DLSTP = 133 +ARM_INS_LCTP = 134 +ARM_INS_LETP = 135 +ARM_INS_LSLL = 136 +ARM_INS_LSRL = 137 +ARM_INS_SQRSHR = 138 +ARM_INS_SQRSHRL = 139 +ARM_INS_SQSHL = 140 +ARM_INS_SQSHLL = 141 +ARM_INS_SRSHR = 142 +ARM_INS_SRSHRL = 143 +ARM_INS_UQRSHL = 144 +ARM_INS_UQRSHLL = 145 +ARM_INS_UQSHL = 146 +ARM_INS_UQSHLL = 147 +ARM_INS_URSHR = 148 +ARM_INS_URSHRL = 149 +ARM_INS_VABAV = 150 +ARM_INS_VABD = 151 +ARM_INS_VABS = 152 +ARM_INS_VADC = 153 +ARM_INS_VADCI = 154 +ARM_INS_VADDLVA = 155 +ARM_INS_VADDLV = 156 +ARM_INS_VADDVA = 157 +ARM_INS_VADDV = 158 +ARM_INS_VADD = 159 +ARM_INS_VAND = 160 +ARM_INS_VBIC = 161 +ARM_INS_VBRSR = 162 +ARM_INS_VCADD = 163 +ARM_INS_VCLS = 164 +ARM_INS_VCLZ = 165 +ARM_INS_VCMLA = 166 +ARM_INS_VCMP = 167 +ARM_INS_VCMUL = 168 +ARM_INS_VCTP = 169 +ARM_INS_VCVTA = 170 +ARM_INS_VCVTM = 171 +ARM_INS_VCVTN = 172 +ARM_INS_VCVTP = 173 +ARM_INS_VDDUP = 174 +ARM_INS_VDUP = 175 +ARM_INS_VDWDUP = 176 +ARM_INS_VEOR = 177 +ARM_INS_VFMAS = 178 +ARM_INS_VFMA = 179 +ARM_INS_VFMS = 180 +ARM_INS_VHADD = 181 +ARM_INS_VHCADD = 182 +ARM_INS_VHSUB = 183 +ARM_INS_VIDUP = 184 +ARM_INS_VIWDUP = 185 +ARM_INS_VLD20 = 186 +ARM_INS_VLD21 = 187 +ARM_INS_VLD40 = 188 +ARM_INS_VLD41 = 189 +ARM_INS_VLD42 = 190 +ARM_INS_VLD43 = 191 +ARM_INS_VLDRB = 192 +ARM_INS_VLDRD = 193 +ARM_INS_VLDRH = 194 +ARM_INS_VLDRW = 195 +ARM_INS_VMAXAV = 196 +ARM_INS_VMAXA = 197 +ARM_INS_VMAXNMAV = 198 +ARM_INS_VMAXNMA = 199 +ARM_INS_VMAXNMV = 200 +ARM_INS_VMAXNM = 201 +ARM_INS_VMAXV = 202 +ARM_INS_VMAX = 203 +ARM_INS_VMINAV = 204 +ARM_INS_VMINA = 205 +ARM_INS_VMINNMAV = 206 +ARM_INS_VMINNMA = 207 +ARM_INS_VMINNMV = 208 +ARM_INS_VMINNM = 209 +ARM_INS_VMINV = 210 +ARM_INS_VMIN = 211 +ARM_INS_VMLADAVA = 212 +ARM_INS_VMLADAVAX = 213 +ARM_INS_VMLADAV = 214 +ARM_INS_VMLADAVX = 215 +ARM_INS_VMLALDAVA = 216 +ARM_INS_VMLALDAVAX = 217 +ARM_INS_VMLALDAV = 218 +ARM_INS_VMLALDAVX = 219 +ARM_INS_VMLAS = 220 +ARM_INS_VMLA = 221 +ARM_INS_VMLSDAVA = 222 +ARM_INS_VMLSDAVAX = 223 +ARM_INS_VMLSDAV = 224 +ARM_INS_VMLSDAVX = 225 +ARM_INS_VMLSLDAVA = 226 +ARM_INS_VMLSLDAVAX = 227 +ARM_INS_VMLSLDAV = 228 +ARM_INS_VMLSLDAVX = 229 +ARM_INS_VMOVLB = 230 +ARM_INS_VMOVLT = 231 +ARM_INS_VMOVNB = 232 +ARM_INS_VMOVNT = 233 +ARM_INS_VMULH = 234 +ARM_INS_VMULLB = 235 +ARM_INS_VMULLT = 236 +ARM_INS_VMUL = 237 +ARM_INS_VMVN = 238 +ARM_INS_VNEG = 239 +ARM_INS_VORN = 240 +ARM_INS_VORR = 241 +ARM_INS_VPNOT = 242 +ARM_INS_VPSEL = 243 +ARM_INS_VPST = 244 +ARM_INS_VPT = 245 +ARM_INS_VQABS = 246 +ARM_INS_VQADD = 247 +ARM_INS_VQDMLADHX = 248 +ARM_INS_VQDMLADH = 249 +ARM_INS_VQDMLAH = 250 +ARM_INS_VQDMLASH = 251 +ARM_INS_VQDMLSDHX = 252 +ARM_INS_VQDMLSDH = 253 +ARM_INS_VQDMULH = 254 +ARM_INS_VQDMULLB = 255 +ARM_INS_VQDMULLT = 256 +ARM_INS_VQMOVNB = 257 +ARM_INS_VQMOVNT = 258 +ARM_INS_VQMOVUNB = 259 +ARM_INS_VQMOVUNT = 260 +ARM_INS_VQNEG = 261 +ARM_INS_VQRDMLADHX = 262 +ARM_INS_VQRDMLADH = 263 +ARM_INS_VQRDMLAH = 264 +ARM_INS_VQRDMLASH = 265 +ARM_INS_VQRDMLSDHX = 266 +ARM_INS_VQRDMLSDH = 267 +ARM_INS_VQRDMULH = 268 +ARM_INS_VQRSHL = 269 +ARM_INS_VQRSHRNB = 270 +ARM_INS_VQRSHRNT = 271 +ARM_INS_VQRSHRUNB = 272 +ARM_INS_VQRSHRUNT = 273 +ARM_INS_VQSHLU = 274 +ARM_INS_VQSHL = 275 +ARM_INS_VQSHRNB = 276 +ARM_INS_VQSHRNT = 277 +ARM_INS_VQSHRUNB = 278 +ARM_INS_VQSHRUNT = 279 +ARM_INS_VQSUB = 280 +ARM_INS_VREV16 = 281 +ARM_INS_VREV32 = 282 +ARM_INS_VREV64 = 283 +ARM_INS_VRHADD = 284 +ARM_INS_VRINTA = 285 +ARM_INS_VRINTM = 286 +ARM_INS_VRINTN = 287 +ARM_INS_VRINTP = 288 +ARM_INS_VRINTX = 289 +ARM_INS_VRINTZ = 290 +ARM_INS_VRMLALDAVHA = 291 +ARM_INS_VRMLALDAVHAX = 292 +ARM_INS_VRMLALDAVH = 293 +ARM_INS_VRMLALDAVHX = 294 +ARM_INS_VRMLSLDAVHA = 295 +ARM_INS_VRMLSLDAVHAX = 296 +ARM_INS_VRMLSLDAVH = 297 +ARM_INS_VRMLSLDAVHX = 298 +ARM_INS_VRMULH = 299 +ARM_INS_VRSHL = 300 +ARM_INS_VRSHRNB = 301 +ARM_INS_VRSHRNT = 302 +ARM_INS_VRSHR = 303 +ARM_INS_VSBC = 304 +ARM_INS_VSBCI = 305 +ARM_INS_VSHLC = 306 +ARM_INS_VSHLLB = 307 +ARM_INS_VSHLLT = 308 +ARM_INS_VSHL = 309 +ARM_INS_VSHRNB = 310 +ARM_INS_VSHRNT = 311 +ARM_INS_VSHR = 312 +ARM_INS_VSLI = 313 +ARM_INS_VSRI = 314 +ARM_INS_VST20 = 315 +ARM_INS_VST21 = 316 +ARM_INS_VST40 = 317 +ARM_INS_VST41 = 318 +ARM_INS_VST42 = 319 +ARM_INS_VST43 = 320 +ARM_INS_VSTRB = 321 +ARM_INS_VSTRD = 322 +ARM_INS_VSTRH = 323 +ARM_INS_VSTRW = 324 +ARM_INS_VSUB = 325 +ARM_INS_WLSTP = 326 +ARM_INS_MVN = 327 +ARM_INS_ORR = 328 +ARM_INS_PKHBT = 329 +ARM_INS_PKHTB = 330 +ARM_INS_PLDW = 331 +ARM_INS_PLD = 332 +ARM_INS_PLI = 333 +ARM_INS_QADD = 334 +ARM_INS_QADD16 = 335 +ARM_INS_QADD8 = 336 +ARM_INS_QASX = 337 +ARM_INS_QDADD = 338 +ARM_INS_QDSUB = 339 +ARM_INS_QSAX = 340 +ARM_INS_QSUB = 341 +ARM_INS_QSUB16 = 342 +ARM_INS_QSUB8 = 343 +ARM_INS_RBIT = 344 +ARM_INS_REV = 345 +ARM_INS_REV16 = 346 +ARM_INS_REVSH = 347 +ARM_INS_RFEDA = 348 +ARM_INS_RFEDB = 349 +ARM_INS_RFEIA = 350 +ARM_INS_RFEIB = 351 +ARM_INS_RSB = 352 +ARM_INS_RSC = 353 +ARM_INS_SADD16 = 354 +ARM_INS_SADD8 = 355 +ARM_INS_SASX = 356 +ARM_INS_SB = 357 +ARM_INS_SBC = 358 +ARM_INS_SBFX = 359 +ARM_INS_SDIV = 360 +ARM_INS_SEL = 361 +ARM_INS_SETEND = 362 +ARM_INS_SETPAN = 363 +ARM_INS_SHA1C = 364 +ARM_INS_SHA1H = 365 +ARM_INS_SHA1M = 366 +ARM_INS_SHA1P = 367 +ARM_INS_SHA1SU0 = 368 +ARM_INS_SHA1SU1 = 369 +ARM_INS_SHA256H = 370 +ARM_INS_SHA256H2 = 371 +ARM_INS_SHA256SU0 = 372 +ARM_INS_SHA256SU1 = 373 +ARM_INS_SHADD16 = 374 +ARM_INS_SHADD8 = 375 +ARM_INS_SHASX = 376 +ARM_INS_SHSAX = 377 +ARM_INS_SHSUB16 = 378 +ARM_INS_SHSUB8 = 379 +ARM_INS_SMC = 380 +ARM_INS_SMLABB = 381 +ARM_INS_SMLABT = 382 +ARM_INS_SMLAD = 383 +ARM_INS_SMLADX = 384 +ARM_INS_SMLAL = 385 +ARM_INS_SMLALBB = 386 +ARM_INS_SMLALBT = 387 +ARM_INS_SMLALD = 388 +ARM_INS_SMLALDX = 389 +ARM_INS_SMLALTB = 390 +ARM_INS_SMLALTT = 391 +ARM_INS_SMLATB = 392 +ARM_INS_SMLATT = 393 +ARM_INS_SMLAWB = 394 +ARM_INS_SMLAWT = 395 +ARM_INS_SMLSD = 396 +ARM_INS_SMLSDX = 397 +ARM_INS_SMLSLD = 398 +ARM_INS_SMLSLDX = 399 +ARM_INS_SMMLA = 400 +ARM_INS_SMMLAR = 401 +ARM_INS_SMMLS = 402 +ARM_INS_SMMLSR = 403 +ARM_INS_SMMUL = 404 +ARM_INS_SMMULR = 405 +ARM_INS_SMUAD = 406 +ARM_INS_SMUADX = 407 +ARM_INS_SMULBB = 408 +ARM_INS_SMULBT = 409 +ARM_INS_SMULL = 410 +ARM_INS_SMULTB = 411 +ARM_INS_SMULTT = 412 +ARM_INS_SMULWB = 413 +ARM_INS_SMULWT = 414 +ARM_INS_SMUSD = 415 +ARM_INS_SMUSDX = 416 +ARM_INS_SRSDA = 417 +ARM_INS_SRSDB = 418 +ARM_INS_SRSIA = 419 +ARM_INS_SRSIB = 420 +ARM_INS_SSAT = 421 +ARM_INS_SSAT16 = 422 +ARM_INS_SSAX = 423 +ARM_INS_SSUB16 = 424 +ARM_INS_SSUB8 = 425 +ARM_INS_STC2L = 426 +ARM_INS_STC2 = 427 +ARM_INS_STCL = 428 +ARM_INS_STC = 429 +ARM_INS_STL = 430 +ARM_INS_STLB = 431 +ARM_INS_STLEX = 432 +ARM_INS_STLEXB = 433 +ARM_INS_STLEXD = 434 +ARM_INS_STLEXH = 435 +ARM_INS_STLH = 436 +ARM_INS_STMDA = 437 +ARM_INS_STMDB = 438 +ARM_INS_STM = 439 +ARM_INS_STMIB = 440 +ARM_INS_STRB = 441 +ARM_INS_STRD = 442 +ARM_INS_STREX = 443 +ARM_INS_STREXB = 444 +ARM_INS_STREXD = 445 +ARM_INS_STREXH = 446 +ARM_INS_STRH = 447 +ARM_INS_STRHT = 448 +ARM_INS_SUB = 449 +ARM_INS_SVC = 450 +ARM_INS_SWP = 451 +ARM_INS_SWPB = 452 +ARM_INS_SXTAB = 453 +ARM_INS_SXTAB16 = 454 +ARM_INS_SXTAH = 455 +ARM_INS_SXTB = 456 +ARM_INS_SXTB16 = 457 +ARM_INS_SXTH = 458 +ARM_INS_TEQ = 459 +ARM_INS_TRAP = 460 +ARM_INS_TSB = 461 +ARM_INS_TST = 462 +ARM_INS_UADD16 = 463 +ARM_INS_UADD8 = 464 +ARM_INS_UASX = 465 +ARM_INS_UBFX = 466 +ARM_INS_UDF = 467 +ARM_INS_UDIV = 468 +ARM_INS_UHADD16 = 469 +ARM_INS_UHADD8 = 470 +ARM_INS_UHASX = 471 +ARM_INS_UHSAX = 472 +ARM_INS_UHSUB16 = 473 +ARM_INS_UHSUB8 = 474 +ARM_INS_UMAAL = 475 +ARM_INS_UMLAL = 476 +ARM_INS_UMULL = 477 +ARM_INS_UQADD16 = 478 +ARM_INS_UQADD8 = 479 +ARM_INS_UQASX = 480 +ARM_INS_UQSAX = 481 +ARM_INS_UQSUB16 = 482 +ARM_INS_UQSUB8 = 483 +ARM_INS_USAD8 = 484 +ARM_INS_USADA8 = 485 +ARM_INS_USAT = 486 +ARM_INS_USAT16 = 487 +ARM_INS_USAX = 488 +ARM_INS_USUB16 = 489 +ARM_INS_USUB8 = 490 +ARM_INS_UXTAB = 491 +ARM_INS_UXTAB16 = 492 +ARM_INS_UXTAH = 493 +ARM_INS_UXTB = 494 +ARM_INS_UXTB16 = 495 +ARM_INS_UXTH = 496 +ARM_INS_VABAL = 497 +ARM_INS_VABA = 498 +ARM_INS_VABDL = 499 +ARM_INS_VACGE = 500 +ARM_INS_VACGT = 501 +ARM_INS_VADDHN = 502 +ARM_INS_VADDL = 503 +ARM_INS_VADDW = 504 +ARM_INS_VFMAB = 505 +ARM_INS_VFMAT = 506 +ARM_INS_VBIF = 507 +ARM_INS_VBIT = 508 +ARM_INS_VBSL = 509 +ARM_INS_VCEQ = 510 +ARM_INS_VCGE = 511 +ARM_INS_VCGT = 512 +ARM_INS_VCLE = 513 +ARM_INS_VCLT = 514 +ARM_INS_VCMPE = 515 +ARM_INS_VCNT = 516 +ARM_INS_VDIV = 517 +ARM_INS_VEXT = 518 +ARM_INS_VFMAL = 519 +ARM_INS_VFMSL = 520 +ARM_INS_VFNMA = 521 +ARM_INS_VFNMS = 522 +ARM_INS_VINS = 523 +ARM_INS_VJCVT = 524 +ARM_INS_VLDMDB = 525 +ARM_INS_VLDMIA = 526 +ARM_INS_VLDR = 527 +ARM_INS_VLLDM = 528 +ARM_INS_VLSTM = 529 +ARM_INS_VMLAL = 530 +ARM_INS_VMLS = 531 +ARM_INS_VMLSL = 532 +ARM_INS_VMMLA = 533 +ARM_INS_VMOVX = 534 +ARM_INS_VMOVL = 535 +ARM_INS_VMOVN = 536 +ARM_INS_VMSR = 537 +ARM_INS_VMULL = 538 +ARM_INS_VNMLA = 539 +ARM_INS_VNMLS = 540 +ARM_INS_VNMUL = 541 +ARM_INS_VPADAL = 542 +ARM_INS_VPADDL = 543 +ARM_INS_VPADD = 544 +ARM_INS_VPMAX = 545 +ARM_INS_VPMIN = 546 +ARM_INS_VQDMLAL = 547 +ARM_INS_VQDMLSL = 548 +ARM_INS_VQDMULL = 549 +ARM_INS_VQMOVUN = 550 +ARM_INS_VQMOVN = 551 +ARM_INS_VQRDMLSH = 552 +ARM_INS_VQRSHRN = 553 +ARM_INS_VQRSHRUN = 554 +ARM_INS_VQSHRN = 555 +ARM_INS_VQSHRUN = 556 +ARM_INS_VRADDHN = 557 +ARM_INS_VRECPE = 558 +ARM_INS_VRECPS = 559 +ARM_INS_VRINTR = 560 +ARM_INS_VRSHRN = 561 +ARM_INS_VRSQRTE = 562 +ARM_INS_VRSQRTS = 563 +ARM_INS_VRSRA = 564 +ARM_INS_VRSUBHN = 565 +ARM_INS_VSCCLRM = 566 +ARM_INS_VSDOT = 567 +ARM_INS_VSELEQ = 568 +ARM_INS_VSELGE = 569 +ARM_INS_VSELGT = 570 +ARM_INS_VSELVS = 571 +ARM_INS_VSHLL = 572 +ARM_INS_VSHRN = 573 +ARM_INS_VSMMLA = 574 +ARM_INS_VSQRT = 575 +ARM_INS_VSRA = 576 +ARM_INS_VSTMDB = 577 +ARM_INS_VSTMIA = 578 +ARM_INS_VSTR = 579 +ARM_INS_VSUBHN = 580 +ARM_INS_VSUBL = 581 +ARM_INS_VSUBW = 582 +ARM_INS_VSUDOT = 583 +ARM_INS_VSWP = 584 +ARM_INS_VTBL = 585 +ARM_INS_VTBX = 586 +ARM_INS_VCVTR = 587 +ARM_INS_VTRN = 588 +ARM_INS_VTST = 589 +ARM_INS_VUDOT = 590 +ARM_INS_VUMMLA = 591 +ARM_INS_VUSDOT = 592 +ARM_INS_VUSMMLA = 593 +ARM_INS_VUZP = 594 +ARM_INS_VZIP = 595 +ARM_INS_ADDW = 596 +ARM_INS_AUT = 597 +ARM_INS_AUTG = 598 +ARM_INS_BFL = 599 +ARM_INS_BFLX = 600 +ARM_INS_BF = 601 +ARM_INS_BFCSEL = 602 +ARM_INS_BFX = 603 +ARM_INS_BTI = 604 +ARM_INS_BXAUT = 605 +ARM_INS_CLRM = 606 +ARM_INS_CSEL = 607 +ARM_INS_CSINC = 608 +ARM_INS_CSINV = 609 +ARM_INS_CSNEG = 610 +ARM_INS_DCPS1 = 611 +ARM_INS_DCPS2 = 612 +ARM_INS_DCPS3 = 613 +ARM_INS_DLS = 614 +ARM_INS_LE = 615 +ARM_INS_ORN = 616 +ARM_INS_PAC = 617 +ARM_INS_PACBTI = 618 +ARM_INS_PACG = 619 +ARM_INS_SG = 620 +ARM_INS_SUBS = 621 +ARM_INS_SUBW = 622 +ARM_INS_TBB = 623 +ARM_INS_TBH = 624 +ARM_INS_TT = 625 +ARM_INS_TTA = 626 +ARM_INS_TTAT = 627 +ARM_INS_TTT = 628 +ARM_INS_WLS = 629 +ARM_INS_BLXNS = 630 +ARM_INS_BXNS = 631 +ARM_INS_CBNZ = 632 +ARM_INS_CBZ = 633 +ARM_INS_POP = 634 +ARM_INS_PUSH = 635 +ARM_INS___BRKDIV0 = 636 +ARM_INS_ENDING = 637 +ARM_INS_ALIAS_BEGIN = 638 +ARM_INS_ALIAS_VMOV = 639 +ARM_INS_ALIAS_NOP = 640 +ARM_INS_ALIAS_YIELD = 641 +ARM_INS_ALIAS_WFE = 642 +ARM_INS_ALIAS_WFI = 643 +ARM_INS_ALIAS_SEV = 644 +ARM_INS_ALIAS_SEVL = 645 +ARM_INS_ALIAS_ESB = 646 +ARM_INS_ALIAS_CSDB = 647 +ARM_INS_ALIAS_CLRBHB = 648 +ARM_INS_ALIAS_PACBTI = 649 +ARM_INS_ALIAS_BTI = 650 +ARM_INS_ALIAS_PAC = 651 +ARM_INS_ALIAS_AUT = 652 +ARM_INS_ALIAS_SSBB = 653 +ARM_INS_ALIAS_PSSBB = 654 +ARM_INS_ALIAS_DFB = 655 +ARM_INS_ALIAS_CSETM = 656 +ARM_INS_ALIAS_CSET = 657 +ARM_INS_ALIAS_CINC = 658 +ARM_INS_ALIAS_CINV = 659 +ARM_INS_ALIAS_CNEG = 660 +ARM_INS_ALIAS_VMLAV = 661 +ARM_INS_ALIAS_VMLAVA = 662 +ARM_INS_ALIAS_VRMLALVH = 663 +ARM_INS_ALIAS_VRMLALVHA = 664 +ARM_INS_ALIAS_VMLALV = 665 +ARM_INS_ALIAS_VMLALVA = 666 +ARM_INS_ALIAS_VBIC = 667 +ARM_INS_ALIAS_VEOR = 668 +ARM_INS_ALIAS_VORN = 669 +ARM_INS_ALIAS_VORR = 670 +ARM_INS_ALIAS_VAND = 671 +ARM_INS_ALIAS_VPSEL = 672 +ARM_INS_ALIAS_ERET = 673 +ARM_INS_ALIAS_ASR = 674 +ARM_INS_ALIAS_LSL = 675 +ARM_INS_ALIAS_LSR = 676 +ARM_INS_ALIAS_ROR = 677 +ARM_INS_ALIAS_RRX = 678 +ARM_INS_ALIAS_UXTW = 679 +ARM_INS_ALIAS_LDM = 680 +ARM_INS_ALIAS_POP = 681 +ARM_INS_ALIAS_PUSH = 682 +ARM_INS_ALIAS_POPW = 683 +ARM_INS_ALIAS_PUSHW = 684 +ARM_INS_ALIAS_VPOP = 685 +ARM_INS_ALIAS_VPUSH = 686 +ARM_INS_ALIAS_END = 687 ARM_GRP_INVALID = 0 ARM_GRP_JUMP = 1 diff --git a/bindings/python/capstone/loongarch.py b/bindings/python/capstone/loongarch.py new file mode 100644 index 0000000000..df4f09b557 --- /dev/null +++ b/bindings/python/capstone/loongarch.py @@ -0,0 +1,55 @@ +# Copyright © 2024 Rot127 +# SPDX-License-Identifier: BSD-3 + +import ctypes +from . import copy_ctypes_list +from .loongarch_const import * + + +class LoongArchOpMem(ctypes.Structure): + _fields_ = ( + ("base", ctypes.c_uint), + ("index", ctypes.c_uint), + ("disp", ctypes.c_int64), + ) + + +class LoongArchOpValue(ctypes.Union): + _fields_ = ( + ("reg", ctypes.c_uint), + ("imm", ctypes.c_int64), + ("mem", LoongArchOpMem), + ) + + +class LoongArchOp(ctypes.Structure): + _fields_ = ( + ("type", ctypes.c_uint8), + ("value", LoongArchOpValue), + ("access", ctypes.c_uint8), + ) + + @property + def imm(self): + return self.value.imm + + @property + def reg(self): + return self.value.reg + + @property + def mem(self): + return self.value.mem + + +# Instruction structure +class CsLoongArch(ctypes.Structure): + _fields_ = ( + ("format", ctypes.c_int), + ("op_count", ctypes.c_uint8), + ("operands", LoongArchOp * 8) + ) + + +def get_arch_info(a): + return a.format, copy_ctypes_list(a.operands[: a.op_count]) diff --git a/bindings/python/capstone/loongarch_const.py b/bindings/python/capstone/loongarch_const.py new file mode 100644 index 0000000000..c2c953d427 --- /dev/null +++ b/bindings/python/capstone/loongarch_const.py @@ -0,0 +1,2401 @@ +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [loongarch_const.py] +LOONGARCH_OP_INVALID = CS_OP_INVALID +LOONGARCH_OP_REG = CS_OP_REG +LOONGARCH_OP_IMM = CS_OP_IMM +LOONGARCH_OP_MEM = CS_OP_MEM + +LOONGARCH_INSN_FORM_PSEUDO = 0 +LOONGARCH_INSN_FORM_FMT3R = 1 +LOONGARCH_INSN_FORM_FMT2RI12 = 2 +LOONGARCH_INSN_FORM_FMT2RI5 = 3 +LOONGARCH_INSN_FORM_FMT2RI16 = 4 +LOONGARCH_INSN_FORM_FMT3RI2 = 5 +LOONGARCH_INSN_FORM_NODSTFMT2RI4 = 6 +LOONGARCH_INSN_FORM_FMT1RI8 = 7 +LOONGARCH_INSN_FORM_FMT2RI4 = 8 +LOONGARCH_INSN_FORM_NODSTFMT1RI4 = 9 +LOONGARCH_INSN_FORM_NODSTFMT1RI5I4 = 10 +LOONGARCH_INSN_FORM_FMTASRT = 11 +LOONGARCH_INSN_FORM_FMTI26 = 12 +LOONGARCH_INSN_FORM_FPFMTBR = 13 +LOONGARCH_INSN_FORM_FMT1RI21 = 14 +LOONGARCH_INSN_FORM_FMT2R = 15 +LOONGARCH_INSN_FORM_FMTI15 = 16 +LOONGARCH_INSN_FORM_FMTBSTR_D = 17 +LOONGARCH_INSN_FORM_FMTBSTR_W = 18 +LOONGARCH_INSN_FORM_FMT3RI3 = 19 +LOONGARCH_INSN_FORM_FMTCACOP = 20 +LOONGARCH_INSN_FORM_FMTCSR = 21 +LOONGARCH_INSN_FORM_FMTCSRXCHG = 22 +LOONGARCH_INSN_FORM_FMTI32 = 23 +LOONGARCH_INSN_FORM_FPFMT2R = 24 +LOONGARCH_INSN_FORM_FPFMT3R = 25 +LOONGARCH_INSN_FORM_FPFMTFCMP = 26 +LOONGARCH_INSN_FORM_FPFMTMEM = 27 +LOONGARCH_INSN_FORM_FPFMT2RI12 = 28 +LOONGARCH_INSN_FORM_FPFMT4R = 29 +LOONGARCH_INSN_FORM_FPFMTMOV = 30 +LOONGARCH_INSN_FORM_FPFMTFSEL = 31 +LOONGARCH_INSN_FORM_FMTINVTLB = 32 +LOONGARCH_INSN_FORM_FMTJISCR = 33 +LOONGARCH_INSN_FORM_FMT2RI8 = 34 +LOONGARCH_INSN_FORM_FMTLDPTE = 35 +LOONGARCH_INSN_FORM_FMT2RI14 = 36 +LOONGARCH_INSN_FORM_FMT1RI20 = 37 +LOONGARCH_INSN_FORM_FMTGR2SCR = 38 +LOONGARCH_INSN_FORM_FMTSCR2GR = 39 +LOONGARCH_INSN_FORM_FMTPRELD = 40 +LOONGARCH_INSN_FORM_FMTPRELDX = 41 +LOONGARCH_INSN_FORM_FMT2RI3 = 42 +LOONGARCH_INSN_FORM_FMT2RI6 = 43 +LOONGARCH_INSN_FORM_FMT1RI4 = 44 +LOONGARCH_INSN_FORM_FMT3R_VVV = 45 +LOONGARCH_INSN_FORM_FMT2RI5_VVI = 46 +LOONGARCH_INSN_FORM_FMT2RI8_VVI = 47 +LOONGARCH_INSN_FORM_FMT2RI3_VVI = 48 +LOONGARCH_INSN_FORM_FMT2RI6_VVI = 49 +LOONGARCH_INSN_FORM_FMT2RI4_VVI = 50 +LOONGARCH_INSN_FORM_FMT4R_VVVV = 51 +LOONGARCH_INSN_FORM_FMT2R_VV = 52 +LOONGARCH_INSN_FORM_FMT2R_XX = 53 +LOONGARCH_INSN_FORM_FMT2RI4_VRI = 54 +LOONGARCH_INSN_FORM_FMT2RI1_VRI = 55 +LOONGARCH_INSN_FORM_FMT2RI3_VRI = 56 +LOONGARCH_INSN_FORM_FMT2RI2_VRI = 57 +LOONGARCH_INSN_FORM_FMT2RI12_VRI = 58 +LOONGARCH_INSN_FORM_FMT1RI13_VI = 59 +LOONGARCH_INSN_FORM_FMT2RI9_VRI = 60 +LOONGARCH_INSN_FORM_FMT2RI11_VRI = 61 +LOONGARCH_INSN_FORM_FMT2RI10_VRI = 62 +LOONGARCH_INSN_FORM_FMT3R_VRR = 63 +LOONGARCH_INSN_FORM_FMT2RI4_RVI = 64 +LOONGARCH_INSN_FORM_FMT2RI1_RVI = 65 +LOONGARCH_INSN_FORM_FMT2RI3_RVI = 66 +LOONGARCH_INSN_FORM_FMT2RI2_RVI = 67 +LOONGARCH_INSN_FORM_FMT2R_VR = 68 +LOONGARCH_INSN_FORM_FMT2RI1_VVI = 69 +LOONGARCH_INSN_FORM_FMT2RI2_VVI = 70 +LOONGARCH_INSN_FORM_FMT3R_VVR = 71 +LOONGARCH_INSN_FORM_FMT2R_CV = 72 +LOONGARCH_INSN_FORM_FMT2RI7_VVI = 73 +LOONGARCH_INSN_FORM_FMT2RI8I4_VRII = 74 +LOONGARCH_INSN_FORM_FMT2RI8I1_VRII = 75 +LOONGARCH_INSN_FORM_FMT2RI8I3_VRII = 76 +LOONGARCH_INSN_FORM_FMT2RI8I2_VRII = 77 +LOONGARCH_INSN_FORM_NODSTFMT2R = 78 +LOONGARCH_INSN_FORM_NODSTFMT1R = 79 +LOONGARCH_INSN_FORM_FMTMFTOP = 80 +LOONGARCH_INSN_FORM_FMTMTTOP = 81 +LOONGARCH_INSN_FORM_NODSTFMT1RI3 = 82 +LOONGARCH_INSN_FORM_NODSTFMT1RI6 = 83 +LOONGARCH_INSN_FORM_NODSTFMT1RI5 = 84 +LOONGARCH_INSN_FORM_FMT1RI5I8 = 85 +LOONGARCH_INSN_FORM_FMT3R_XXX = 86 +LOONGARCH_INSN_FORM_FMT2RI5_XXI = 87 +LOONGARCH_INSN_FORM_FMT2RI8_XXI = 88 +LOONGARCH_INSN_FORM_FMT2RI3_XXI = 89 +LOONGARCH_INSN_FORM_FMT2RI6_XXI = 90 +LOONGARCH_INSN_FORM_FMT2RI4_XXI = 91 +LOONGARCH_INSN_FORM_FMT4R_XXXX = 92 +LOONGARCH_INSN_FORM_FMT2RI2_XRI = 93 +LOONGARCH_INSN_FORM_FMT2RI3_XRI = 94 +LOONGARCH_INSN_FORM_FMT2RI2_XXI = 95 +LOONGARCH_INSN_FORM_FMT2RI12_XRI = 96 +LOONGARCH_INSN_FORM_FMT1RI13_XI = 97 +LOONGARCH_INSN_FORM_FMT2RI9_XRI = 98 +LOONGARCH_INSN_FORM_FMT2RI11_XRI = 99 +LOONGARCH_INSN_FORM_FMT2RI10_XRI = 100 +LOONGARCH_INSN_FORM_FMT3R_XRR = 101 +LOONGARCH_INSN_FORM_FMT2RI2_RXI = 102 +LOONGARCH_INSN_FORM_FMT2RI3_RXI = 103 +LOONGARCH_INSN_FORM_FMT2RI1_XXI = 104 +LOONGARCH_INSN_FORM_FMT2R_XR = 105 +LOONGARCH_INSN_FORM_FMT3R_XXR = 106 +LOONGARCH_INSN_FORM_FMT2R_CX = 107 +LOONGARCH_INSN_FORM_FMT2RI7_XXI = 108 +LOONGARCH_INSN_FORM_FMT2RI8I5_XRII = 109 +LOONGARCH_INSN_FORM_FMT2RI8I2_XRII = 110 +LOONGARCH_INSN_FORM_FMT2RI8I4_XRII = 111 +LOONGARCH_INSN_FORM_FMT2RI8I3_XRII = 112 + +LOONGARCH_REG_INVALID = 0 +LOONGARCH_REG_F0 = 1 +LOONGARCH_REG_F1 = 2 +LOONGARCH_REG_F2 = 3 +LOONGARCH_REG_F3 = 4 +LOONGARCH_REG_F4 = 5 +LOONGARCH_REG_F5 = 6 +LOONGARCH_REG_F6 = 7 +LOONGARCH_REG_F7 = 8 +LOONGARCH_REG_F8 = 9 +LOONGARCH_REG_F9 = 10 +LOONGARCH_REG_F10 = 11 +LOONGARCH_REG_F11 = 12 +LOONGARCH_REG_F12 = 13 +LOONGARCH_REG_F13 = 14 +LOONGARCH_REG_F14 = 15 +LOONGARCH_REG_F15 = 16 +LOONGARCH_REG_F16 = 17 +LOONGARCH_REG_F17 = 18 +LOONGARCH_REG_F18 = 19 +LOONGARCH_REG_F19 = 20 +LOONGARCH_REG_F20 = 21 +LOONGARCH_REG_F21 = 22 +LOONGARCH_REG_F22 = 23 +LOONGARCH_REG_F23 = 24 +LOONGARCH_REG_F24 = 25 +LOONGARCH_REG_F25 = 26 +LOONGARCH_REG_F26 = 27 +LOONGARCH_REG_F27 = 28 +LOONGARCH_REG_F28 = 29 +LOONGARCH_REG_F29 = 30 +LOONGARCH_REG_F30 = 31 +LOONGARCH_REG_F31 = 32 +LOONGARCH_REG_FCC0 = 33 +LOONGARCH_REG_FCC1 = 34 +LOONGARCH_REG_FCC2 = 35 +LOONGARCH_REG_FCC3 = 36 +LOONGARCH_REG_FCC4 = 37 +LOONGARCH_REG_FCC5 = 38 +LOONGARCH_REG_FCC6 = 39 +LOONGARCH_REG_FCC7 = 40 +LOONGARCH_REG_FCSR0 = 41 +LOONGARCH_REG_FCSR1 = 42 +LOONGARCH_REG_FCSR2 = 43 +LOONGARCH_REG_FCSR3 = 44 +LOONGARCH_REG_R0 = 45 +LOONGARCH_REG_R1 = 46 +LOONGARCH_REG_R2 = 47 +LOONGARCH_REG_R3 = 48 +LOONGARCH_REG_R4 = 49 +LOONGARCH_REG_R5 = 50 +LOONGARCH_REG_R6 = 51 +LOONGARCH_REG_R7 = 52 +LOONGARCH_REG_R8 = 53 +LOONGARCH_REG_R9 = 54 +LOONGARCH_REG_R10 = 55 +LOONGARCH_REG_R11 = 56 +LOONGARCH_REG_R12 = 57 +LOONGARCH_REG_R13 = 58 +LOONGARCH_REG_R14 = 59 +LOONGARCH_REG_R15 = 60 +LOONGARCH_REG_R16 = 61 +LOONGARCH_REG_R17 = 62 +LOONGARCH_REG_R18 = 63 +LOONGARCH_REG_R19 = 64 +LOONGARCH_REG_R20 = 65 +LOONGARCH_REG_R21 = 66 +LOONGARCH_REG_R22 = 67 +LOONGARCH_REG_R23 = 68 +LOONGARCH_REG_R24 = 69 +LOONGARCH_REG_R25 = 70 +LOONGARCH_REG_R26 = 71 +LOONGARCH_REG_R27 = 72 +LOONGARCH_REG_R28 = 73 +LOONGARCH_REG_R29 = 74 +LOONGARCH_REG_R30 = 75 +LOONGARCH_REG_R31 = 76 +LOONGARCH_REG_SCR0 = 77 +LOONGARCH_REG_SCR1 = 78 +LOONGARCH_REG_SCR2 = 79 +LOONGARCH_REG_SCR3 = 80 +LOONGARCH_REG_VR0 = 81 +LOONGARCH_REG_VR1 = 82 +LOONGARCH_REG_VR2 = 83 +LOONGARCH_REG_VR3 = 84 +LOONGARCH_REG_VR4 = 85 +LOONGARCH_REG_VR5 = 86 +LOONGARCH_REG_VR6 = 87 +LOONGARCH_REG_VR7 = 88 +LOONGARCH_REG_VR8 = 89 +LOONGARCH_REG_VR9 = 90 +LOONGARCH_REG_VR10 = 91 +LOONGARCH_REG_VR11 = 92 +LOONGARCH_REG_VR12 = 93 +LOONGARCH_REG_VR13 = 94 +LOONGARCH_REG_VR14 = 95 +LOONGARCH_REG_VR15 = 96 +LOONGARCH_REG_VR16 = 97 +LOONGARCH_REG_VR17 = 98 +LOONGARCH_REG_VR18 = 99 +LOONGARCH_REG_VR19 = 100 +LOONGARCH_REG_VR20 = 101 +LOONGARCH_REG_VR21 = 102 +LOONGARCH_REG_VR22 = 103 +LOONGARCH_REG_VR23 = 104 +LOONGARCH_REG_VR24 = 105 +LOONGARCH_REG_VR25 = 106 +LOONGARCH_REG_VR26 = 107 +LOONGARCH_REG_VR27 = 108 +LOONGARCH_REG_VR28 = 109 +LOONGARCH_REG_VR29 = 110 +LOONGARCH_REG_VR30 = 111 +LOONGARCH_REG_VR31 = 112 +LOONGARCH_REG_XR0 = 113 +LOONGARCH_REG_XR1 = 114 +LOONGARCH_REG_XR2 = 115 +LOONGARCH_REG_XR3 = 116 +LOONGARCH_REG_XR4 = 117 +LOONGARCH_REG_XR5 = 118 +LOONGARCH_REG_XR6 = 119 +LOONGARCH_REG_XR7 = 120 +LOONGARCH_REG_XR8 = 121 +LOONGARCH_REG_XR9 = 122 +LOONGARCH_REG_XR10 = 123 +LOONGARCH_REG_XR11 = 124 +LOONGARCH_REG_XR12 = 125 +LOONGARCH_REG_XR13 = 126 +LOONGARCH_REG_XR14 = 127 +LOONGARCH_REG_XR15 = 128 +LOONGARCH_REG_XR16 = 129 +LOONGARCH_REG_XR17 = 130 +LOONGARCH_REG_XR18 = 131 +LOONGARCH_REG_XR19 = 132 +LOONGARCH_REG_XR20 = 133 +LOONGARCH_REG_XR21 = 134 +LOONGARCH_REG_XR22 = 135 +LOONGARCH_REG_XR23 = 136 +LOONGARCH_REG_XR24 = 137 +LOONGARCH_REG_XR25 = 138 +LOONGARCH_REG_XR26 = 139 +LOONGARCH_REG_XR27 = 140 +LOONGARCH_REG_XR28 = 141 +LOONGARCH_REG_XR29 = 142 +LOONGARCH_REG_XR30 = 143 +LOONGARCH_REG_XR31 = 144 +LOONGARCH_REG_F0_64 = 145 +LOONGARCH_REG_F1_64 = 146 +LOONGARCH_REG_F2_64 = 147 +LOONGARCH_REG_F3_64 = 148 +LOONGARCH_REG_F4_64 = 149 +LOONGARCH_REG_F5_64 = 150 +LOONGARCH_REG_F6_64 = 151 +LOONGARCH_REG_F7_64 = 152 +LOONGARCH_REG_F8_64 = 153 +LOONGARCH_REG_F9_64 = 154 +LOONGARCH_REG_F10_64 = 155 +LOONGARCH_REG_F11_64 = 156 +LOONGARCH_REG_F12_64 = 157 +LOONGARCH_REG_F13_64 = 158 +LOONGARCH_REG_F14_64 = 159 +LOONGARCH_REG_F15_64 = 160 +LOONGARCH_REG_F16_64 = 161 +LOONGARCH_REG_F17_64 = 162 +LOONGARCH_REG_F18_64 = 163 +LOONGARCH_REG_F19_64 = 164 +LOONGARCH_REG_F20_64 = 165 +LOONGARCH_REG_F21_64 = 166 +LOONGARCH_REG_F22_64 = 167 +LOONGARCH_REG_F23_64 = 168 +LOONGARCH_REG_F24_64 = 169 +LOONGARCH_REG_F25_64 = 170 +LOONGARCH_REG_F26_64 = 171 +LOONGARCH_REG_F27_64 = 172 +LOONGARCH_REG_F28_64 = 173 +LOONGARCH_REG_F29_64 = 174 +LOONGARCH_REG_F30_64 = 175 +LOONGARCH_REG_F31_64 = 176 +LOONGARCH_REG_ENDING = 177 +LOONGARCH_REG_ZERO = LOONGARCH_REG_R0 +LOONGARCH_REG_RA = LOONGARCH_REG_R1 +LOONGARCH_REG_TP = LOONGARCH_REG_R2 +LOONGARCH_REG_SP = LOONGARCH_REG_R3 +LOONGARCH_REG_A0 = LOONGARCH_REG_R4 +LOONGARCH_REG_A1 = LOONGARCH_REG_R5 +LOONGARCH_REG_A2 = LOONGARCH_REG_R6 +LOONGARCH_REG_A3 = LOONGARCH_REG_R7 +LOONGARCH_REG_A4 = LOONGARCH_REG_R8 +LOONGARCH_REG_A5 = LOONGARCH_REG_R9 +LOONGARCH_REG_A6 = LOONGARCH_REG_R10 +LOONGARCH_REG_A7 = LOONGARCH_REG_R11 +LOONGARCH_REG_T0 = LOONGARCH_REG_R12 +LOONGARCH_REG_T1 = LOONGARCH_REG_R13 +LOONGARCH_REG_T2 = LOONGARCH_REG_R14 +LOONGARCH_REG_T3 = LOONGARCH_REG_R15 +LOONGARCH_REG_T4 = LOONGARCH_REG_R16 +LOONGARCH_REG_T5 = LOONGARCH_REG_R17 +LOONGARCH_REG_T6 = LOONGARCH_REG_R18 +LOONGARCH_REG_T7 = LOONGARCH_REG_R19 +LOONGARCH_REG_T8 = LOONGARCH_REG_R20 +LOONGARCH_REG_FP = LOONGARCH_REG_R22 +LOONGARCH_REG_S9 = LOONGARCH_REG_R22 +LOONGARCH_REG_S0 = LOONGARCH_REG_R23 +LOONGARCH_REG_S1 = LOONGARCH_REG_R24 +LOONGARCH_REG_S2 = LOONGARCH_REG_R25 +LOONGARCH_REG_S3 = LOONGARCH_REG_R26 +LOONGARCH_REG_S4 = LOONGARCH_REG_R27 +LOONGARCH_REG_S5 = LOONGARCH_REG_R28 +LOONGARCH_REG_S6 = LOONGARCH_REG_R29 +LOONGARCH_REG_S7 = LOONGARCH_REG_R30 +LOONGARCH_REG_S8 = LOONGARCH_REG_R31 + +LOONGARCH_INS_INVALID = 0 +LOONGARCH_INS_CALL36 = 1 +LOONGARCH_INS_LA_ABS = 2 +LOONGARCH_INS_LA_GOT = 3 +LOONGARCH_INS_LA_PCREL = 4 +LOONGARCH_INS_LA_TLS_GD = 5 +LOONGARCH_INS_LA_TLS_IE = 6 +LOONGARCH_INS_LA_TLS_LD = 7 +LOONGARCH_INS_LA_TLS_LE = 8 +LOONGARCH_INS_LI_D = 9 +LOONGARCH_INS_LI_W = 10 +LOONGARCH_INS_TAIL36 = 11 +LOONGARCH_INS_VREPLI_B = 12 +LOONGARCH_INS_VREPLI_D = 13 +LOONGARCH_INS_VREPLI_H = 14 +LOONGARCH_INS_VREPLI_W = 15 +LOONGARCH_INS_XVREPLI_B = 16 +LOONGARCH_INS_XVREPLI_D = 17 +LOONGARCH_INS_XVREPLI_H = 18 +LOONGARCH_INS_XVREPLI_W = 19 +LOONGARCH_INS_ADC_B = 20 +LOONGARCH_INS_ADC_D = 21 +LOONGARCH_INS_ADC_H = 22 +LOONGARCH_INS_ADC_W = 23 +LOONGARCH_INS_ADDI_D = 24 +LOONGARCH_INS_ADDI_W = 25 +LOONGARCH_INS_ADDU12I_D = 26 +LOONGARCH_INS_ADDU12I_W = 27 +LOONGARCH_INS_ADDU16I_D = 28 +LOONGARCH_INS_ADD_D = 29 +LOONGARCH_INS_ADD_W = 30 +LOONGARCH_INS_ALSL_D = 31 +LOONGARCH_INS_ALSL_W = 32 +LOONGARCH_INS_ALSL_WU = 33 +LOONGARCH_INS_AMADD_B = 34 +LOONGARCH_INS_AMADD_D = 35 +LOONGARCH_INS_AMADD_H = 36 +LOONGARCH_INS_AMADD_W = 37 +LOONGARCH_INS_AMADD_DB_B = 38 +LOONGARCH_INS_AMADD_DB_D = 39 +LOONGARCH_INS_AMADD_DB_H = 40 +LOONGARCH_INS_AMADD_DB_W = 41 +LOONGARCH_INS_AMAND_D = 42 +LOONGARCH_INS_AMAND_W = 43 +LOONGARCH_INS_AMAND_DB_D = 44 +LOONGARCH_INS_AMAND_DB_W = 45 +LOONGARCH_INS_AMCAS_B = 46 +LOONGARCH_INS_AMCAS_D = 47 +LOONGARCH_INS_AMCAS_H = 48 +LOONGARCH_INS_AMCAS_W = 49 +LOONGARCH_INS_AMCAS_DB_B = 50 +LOONGARCH_INS_AMCAS_DB_D = 51 +LOONGARCH_INS_AMCAS_DB_H = 52 +LOONGARCH_INS_AMCAS_DB_W = 53 +LOONGARCH_INS_AMMAX_D = 54 +LOONGARCH_INS_AMMAX_DU = 55 +LOONGARCH_INS_AMMAX_W = 56 +LOONGARCH_INS_AMMAX_WU = 57 +LOONGARCH_INS_AMMAX_DB_D = 58 +LOONGARCH_INS_AMMAX_DB_DU = 59 +LOONGARCH_INS_AMMAX_DB_W = 60 +LOONGARCH_INS_AMMAX_DB_WU = 61 +LOONGARCH_INS_AMMIN_D = 62 +LOONGARCH_INS_AMMIN_DU = 63 +LOONGARCH_INS_AMMIN_W = 64 +LOONGARCH_INS_AMMIN_WU = 65 +LOONGARCH_INS_AMMIN_DB_D = 66 +LOONGARCH_INS_AMMIN_DB_DU = 67 +LOONGARCH_INS_AMMIN_DB_W = 68 +LOONGARCH_INS_AMMIN_DB_WU = 69 +LOONGARCH_INS_AMOR_D = 70 +LOONGARCH_INS_AMOR_W = 71 +LOONGARCH_INS_AMOR_DB_D = 72 +LOONGARCH_INS_AMOR_DB_W = 73 +LOONGARCH_INS_AMSWAP_B = 74 +LOONGARCH_INS_AMSWAP_D = 75 +LOONGARCH_INS_AMSWAP_H = 76 +LOONGARCH_INS_AMSWAP_W = 77 +LOONGARCH_INS_AMSWAP_DB_B = 78 +LOONGARCH_INS_AMSWAP_DB_D = 79 +LOONGARCH_INS_AMSWAP_DB_H = 80 +LOONGARCH_INS_AMSWAP_DB_W = 81 +LOONGARCH_INS_AMXOR_D = 82 +LOONGARCH_INS_AMXOR_W = 83 +LOONGARCH_INS_AMXOR_DB_D = 84 +LOONGARCH_INS_AMXOR_DB_W = 85 +LOONGARCH_INS_AND = 86 +LOONGARCH_INS_ANDI = 87 +LOONGARCH_INS_ANDN = 88 +LOONGARCH_INS_ARMADC_W = 89 +LOONGARCH_INS_ARMADD_W = 90 +LOONGARCH_INS_ARMAND_W = 91 +LOONGARCH_INS_ARMMFFLAG = 92 +LOONGARCH_INS_ARMMOVE = 93 +LOONGARCH_INS_ARMMOV_D = 94 +LOONGARCH_INS_ARMMOV_W = 95 +LOONGARCH_INS_ARMMTFLAG = 96 +LOONGARCH_INS_ARMNOT_W = 97 +LOONGARCH_INS_ARMOR_W = 98 +LOONGARCH_INS_ARMROTRI_W = 99 +LOONGARCH_INS_ARMROTR_W = 100 +LOONGARCH_INS_ARMRRX_W = 101 +LOONGARCH_INS_ARMSBC_W = 102 +LOONGARCH_INS_ARMSLLI_W = 103 +LOONGARCH_INS_ARMSLL_W = 104 +LOONGARCH_INS_ARMSRAI_W = 105 +LOONGARCH_INS_ARMSRA_W = 106 +LOONGARCH_INS_ARMSRLI_W = 107 +LOONGARCH_INS_ARMSRL_W = 108 +LOONGARCH_INS_ARMSUB_W = 109 +LOONGARCH_INS_ARMXOR_W = 110 +LOONGARCH_INS_ASRTGT_D = 111 +LOONGARCH_INS_ASRTLE_D = 112 +LOONGARCH_INS_B = 113 +LOONGARCH_INS_BCEQZ = 114 +LOONGARCH_INS_BCNEZ = 115 +LOONGARCH_INS_BEQ = 116 +LOONGARCH_INS_BEQZ = 117 +LOONGARCH_INS_BGE = 118 +LOONGARCH_INS_BGEU = 119 +LOONGARCH_INS_BITREV_4B = 120 +LOONGARCH_INS_BITREV_8B = 121 +LOONGARCH_INS_BITREV_D = 122 +LOONGARCH_INS_BITREV_W = 123 +LOONGARCH_INS_BL = 124 +LOONGARCH_INS_BLT = 125 +LOONGARCH_INS_BLTU = 126 +LOONGARCH_INS_BNE = 127 +LOONGARCH_INS_BNEZ = 128 +LOONGARCH_INS_BREAK = 129 +LOONGARCH_INS_BSTRINS_D = 130 +LOONGARCH_INS_BSTRINS_W = 131 +LOONGARCH_INS_BSTRPICK_D = 132 +LOONGARCH_INS_BSTRPICK_W = 133 +LOONGARCH_INS_BYTEPICK_D = 134 +LOONGARCH_INS_BYTEPICK_W = 135 +LOONGARCH_INS_CACOP = 136 +LOONGARCH_INS_CLO_D = 137 +LOONGARCH_INS_CLO_W = 138 +LOONGARCH_INS_CLZ_D = 139 +LOONGARCH_INS_CLZ_W = 140 +LOONGARCH_INS_CPUCFG = 141 +LOONGARCH_INS_CRCC_W_B_W = 142 +LOONGARCH_INS_CRCC_W_D_W = 143 +LOONGARCH_INS_CRCC_W_H_W = 144 +LOONGARCH_INS_CRCC_W_W_W = 145 +LOONGARCH_INS_CRC_W_B_W = 146 +LOONGARCH_INS_CRC_W_D_W = 147 +LOONGARCH_INS_CRC_W_H_W = 148 +LOONGARCH_INS_CRC_W_W_W = 149 +LOONGARCH_INS_CSRRD = 150 +LOONGARCH_INS_CSRWR = 151 +LOONGARCH_INS_CSRXCHG = 152 +LOONGARCH_INS_CTO_D = 153 +LOONGARCH_INS_CTO_W = 154 +LOONGARCH_INS_CTZ_D = 155 +LOONGARCH_INS_CTZ_W = 156 +LOONGARCH_INS_DBAR = 157 +LOONGARCH_INS_DBCL = 158 +LOONGARCH_INS_DIV_D = 159 +LOONGARCH_INS_DIV_DU = 160 +LOONGARCH_INS_DIV_W = 161 +LOONGARCH_INS_DIV_WU = 162 +LOONGARCH_INS_ERTN = 163 +LOONGARCH_INS_EXT_W_B = 164 +LOONGARCH_INS_EXT_W_H = 165 +LOONGARCH_INS_FABS_D = 166 +LOONGARCH_INS_FABS_S = 167 +LOONGARCH_INS_FADD_D = 168 +LOONGARCH_INS_FADD_S = 169 +LOONGARCH_INS_FCLASS_D = 170 +LOONGARCH_INS_FCLASS_S = 171 +LOONGARCH_INS_FCMP_CAF_D = 172 +LOONGARCH_INS_FCMP_CAF_S = 173 +LOONGARCH_INS_FCMP_CEQ_D = 174 +LOONGARCH_INS_FCMP_CEQ_S = 175 +LOONGARCH_INS_FCMP_CLE_D = 176 +LOONGARCH_INS_FCMP_CLE_S = 177 +LOONGARCH_INS_FCMP_CLT_D = 178 +LOONGARCH_INS_FCMP_CLT_S = 179 +LOONGARCH_INS_FCMP_CNE_D = 180 +LOONGARCH_INS_FCMP_CNE_S = 181 +LOONGARCH_INS_FCMP_COR_D = 182 +LOONGARCH_INS_FCMP_COR_S = 183 +LOONGARCH_INS_FCMP_CUEQ_D = 184 +LOONGARCH_INS_FCMP_CUEQ_S = 185 +LOONGARCH_INS_FCMP_CULE_D = 186 +LOONGARCH_INS_FCMP_CULE_S = 187 +LOONGARCH_INS_FCMP_CULT_D = 188 +LOONGARCH_INS_FCMP_CULT_S = 189 +LOONGARCH_INS_FCMP_CUNE_D = 190 +LOONGARCH_INS_FCMP_CUNE_S = 191 +LOONGARCH_INS_FCMP_CUN_D = 192 +LOONGARCH_INS_FCMP_CUN_S = 193 +LOONGARCH_INS_FCMP_SAF_D = 194 +LOONGARCH_INS_FCMP_SAF_S = 195 +LOONGARCH_INS_FCMP_SEQ_D = 196 +LOONGARCH_INS_FCMP_SEQ_S = 197 +LOONGARCH_INS_FCMP_SLE_D = 198 +LOONGARCH_INS_FCMP_SLE_S = 199 +LOONGARCH_INS_FCMP_SLT_D = 200 +LOONGARCH_INS_FCMP_SLT_S = 201 +LOONGARCH_INS_FCMP_SNE_D = 202 +LOONGARCH_INS_FCMP_SNE_S = 203 +LOONGARCH_INS_FCMP_SOR_D = 204 +LOONGARCH_INS_FCMP_SOR_S = 205 +LOONGARCH_INS_FCMP_SUEQ_D = 206 +LOONGARCH_INS_FCMP_SUEQ_S = 207 +LOONGARCH_INS_FCMP_SULE_D = 208 +LOONGARCH_INS_FCMP_SULE_S = 209 +LOONGARCH_INS_FCMP_SULT_D = 210 +LOONGARCH_INS_FCMP_SULT_S = 211 +LOONGARCH_INS_FCMP_SUNE_D = 212 +LOONGARCH_INS_FCMP_SUNE_S = 213 +LOONGARCH_INS_FCMP_SUN_D = 214 +LOONGARCH_INS_FCMP_SUN_S = 215 +LOONGARCH_INS_FCOPYSIGN_D = 216 +LOONGARCH_INS_FCOPYSIGN_S = 217 +LOONGARCH_INS_FCVT_D_LD = 218 +LOONGARCH_INS_FCVT_D_S = 219 +LOONGARCH_INS_FCVT_LD_D = 220 +LOONGARCH_INS_FCVT_S_D = 221 +LOONGARCH_INS_FCVT_UD_D = 222 +LOONGARCH_INS_FDIV_D = 223 +LOONGARCH_INS_FDIV_S = 224 +LOONGARCH_INS_FFINT_D_L = 225 +LOONGARCH_INS_FFINT_D_W = 226 +LOONGARCH_INS_FFINT_S_L = 227 +LOONGARCH_INS_FFINT_S_W = 228 +LOONGARCH_INS_FLDGT_D = 229 +LOONGARCH_INS_FLDGT_S = 230 +LOONGARCH_INS_FLDLE_D = 231 +LOONGARCH_INS_FLDLE_S = 232 +LOONGARCH_INS_FLDX_D = 233 +LOONGARCH_INS_FLDX_S = 234 +LOONGARCH_INS_FLD_D = 235 +LOONGARCH_INS_FLD_S = 236 +LOONGARCH_INS_FLOGB_D = 237 +LOONGARCH_INS_FLOGB_S = 238 +LOONGARCH_INS_FMADD_D = 239 +LOONGARCH_INS_FMADD_S = 240 +LOONGARCH_INS_FMAXA_D = 241 +LOONGARCH_INS_FMAXA_S = 242 +LOONGARCH_INS_FMAX_D = 243 +LOONGARCH_INS_FMAX_S = 244 +LOONGARCH_INS_FMINA_D = 245 +LOONGARCH_INS_FMINA_S = 246 +LOONGARCH_INS_FMIN_D = 247 +LOONGARCH_INS_FMIN_S = 248 +LOONGARCH_INS_FMOV_D = 249 +LOONGARCH_INS_FMOV_S = 250 +LOONGARCH_INS_FMSUB_D = 251 +LOONGARCH_INS_FMSUB_S = 252 +LOONGARCH_INS_FMUL_D = 253 +LOONGARCH_INS_FMUL_S = 254 +LOONGARCH_INS_FNEG_D = 255 +LOONGARCH_INS_FNEG_S = 256 +LOONGARCH_INS_FNMADD_D = 257 +LOONGARCH_INS_FNMADD_S = 258 +LOONGARCH_INS_FNMSUB_D = 259 +LOONGARCH_INS_FNMSUB_S = 260 +LOONGARCH_INS_FRECIPE_D = 261 +LOONGARCH_INS_FRECIPE_S = 262 +LOONGARCH_INS_FRECIP_D = 263 +LOONGARCH_INS_FRECIP_S = 264 +LOONGARCH_INS_FRINT_D = 265 +LOONGARCH_INS_FRINT_S = 266 +LOONGARCH_INS_FRSQRTE_D = 267 +LOONGARCH_INS_FRSQRTE_S = 268 +LOONGARCH_INS_FRSQRT_D = 269 +LOONGARCH_INS_FRSQRT_S = 270 +LOONGARCH_INS_FSCALEB_D = 271 +LOONGARCH_INS_FSCALEB_S = 272 +LOONGARCH_INS_FSEL = 273 +LOONGARCH_INS_FSQRT_D = 274 +LOONGARCH_INS_FSQRT_S = 275 +LOONGARCH_INS_FSTGT_D = 276 +LOONGARCH_INS_FSTGT_S = 277 +LOONGARCH_INS_FSTLE_D = 278 +LOONGARCH_INS_FSTLE_S = 279 +LOONGARCH_INS_FSTX_D = 280 +LOONGARCH_INS_FSTX_S = 281 +LOONGARCH_INS_FST_D = 282 +LOONGARCH_INS_FST_S = 283 +LOONGARCH_INS_FSUB_D = 284 +LOONGARCH_INS_FSUB_S = 285 +LOONGARCH_INS_FTINTRM_L_D = 286 +LOONGARCH_INS_FTINTRM_L_S = 287 +LOONGARCH_INS_FTINTRM_W_D = 288 +LOONGARCH_INS_FTINTRM_W_S = 289 +LOONGARCH_INS_FTINTRNE_L_D = 290 +LOONGARCH_INS_FTINTRNE_L_S = 291 +LOONGARCH_INS_FTINTRNE_W_D = 292 +LOONGARCH_INS_FTINTRNE_W_S = 293 +LOONGARCH_INS_FTINTRP_L_D = 294 +LOONGARCH_INS_FTINTRP_L_S = 295 +LOONGARCH_INS_FTINTRP_W_D = 296 +LOONGARCH_INS_FTINTRP_W_S = 297 +LOONGARCH_INS_FTINTRZ_L_D = 298 +LOONGARCH_INS_FTINTRZ_L_S = 299 +LOONGARCH_INS_FTINTRZ_W_D = 300 +LOONGARCH_INS_FTINTRZ_W_S = 301 +LOONGARCH_INS_FTINT_L_D = 302 +LOONGARCH_INS_FTINT_L_S = 303 +LOONGARCH_INS_FTINT_W_D = 304 +LOONGARCH_INS_FTINT_W_S = 305 +LOONGARCH_INS_GCSRRD = 306 +LOONGARCH_INS_GCSRWR = 307 +LOONGARCH_INS_GCSRXCHG = 308 +LOONGARCH_INS_GTLBFLUSH = 309 +LOONGARCH_INS_HVCL = 310 +LOONGARCH_INS_IBAR = 311 +LOONGARCH_INS_IDLE = 312 +LOONGARCH_INS_INVTLB = 313 +LOONGARCH_INS_IOCSRRD_B = 314 +LOONGARCH_INS_IOCSRRD_D = 315 +LOONGARCH_INS_IOCSRRD_H = 316 +LOONGARCH_INS_IOCSRRD_W = 317 +LOONGARCH_INS_IOCSRWR_B = 318 +LOONGARCH_INS_IOCSRWR_D = 319 +LOONGARCH_INS_IOCSRWR_H = 320 +LOONGARCH_INS_IOCSRWR_W = 321 +LOONGARCH_INS_JIRL = 322 +LOONGARCH_INS_JISCR0 = 323 +LOONGARCH_INS_JISCR1 = 324 +LOONGARCH_INS_LDDIR = 325 +LOONGARCH_INS_LDGT_B = 326 +LOONGARCH_INS_LDGT_D = 327 +LOONGARCH_INS_LDGT_H = 328 +LOONGARCH_INS_LDGT_W = 329 +LOONGARCH_INS_LDLE_B = 330 +LOONGARCH_INS_LDLE_D = 331 +LOONGARCH_INS_LDLE_H = 332 +LOONGARCH_INS_LDLE_W = 333 +LOONGARCH_INS_LDL_D = 334 +LOONGARCH_INS_LDL_W = 335 +LOONGARCH_INS_LDPTE = 336 +LOONGARCH_INS_LDPTR_D = 337 +LOONGARCH_INS_LDPTR_W = 338 +LOONGARCH_INS_LDR_D = 339 +LOONGARCH_INS_LDR_W = 340 +LOONGARCH_INS_LDX_B = 341 +LOONGARCH_INS_LDX_BU = 342 +LOONGARCH_INS_LDX_D = 343 +LOONGARCH_INS_LDX_H = 344 +LOONGARCH_INS_LDX_HU = 345 +LOONGARCH_INS_LDX_W = 346 +LOONGARCH_INS_LDX_WU = 347 +LOONGARCH_INS_LD_B = 348 +LOONGARCH_INS_LD_BU = 349 +LOONGARCH_INS_LD_D = 350 +LOONGARCH_INS_LD_H = 351 +LOONGARCH_INS_LD_HU = 352 +LOONGARCH_INS_LD_W = 353 +LOONGARCH_INS_LD_WU = 354 +LOONGARCH_INS_LLACQ_D = 355 +LOONGARCH_INS_LLACQ_W = 356 +LOONGARCH_INS_LL_D = 357 +LOONGARCH_INS_LL_W = 358 +LOONGARCH_INS_LU12I_W = 359 +LOONGARCH_INS_LU32I_D = 360 +LOONGARCH_INS_LU52I_D = 361 +LOONGARCH_INS_MASKEQZ = 362 +LOONGARCH_INS_MASKNEZ = 363 +LOONGARCH_INS_MOD_D = 364 +LOONGARCH_INS_MOD_DU = 365 +LOONGARCH_INS_MOD_W = 366 +LOONGARCH_INS_MOD_WU = 367 +LOONGARCH_INS_MOVCF2FR = 368 +LOONGARCH_INS_MOVCF2GR = 369 +LOONGARCH_INS_MOVFCSR2GR = 370 +LOONGARCH_INS_MOVFR2CF = 371 +LOONGARCH_INS_MOVFR2GR_D = 372 +LOONGARCH_INS_MOVFR2GR_S = 373 +LOONGARCH_INS_MOVFRH2GR_S = 374 +LOONGARCH_INS_MOVGR2CF = 375 +LOONGARCH_INS_MOVGR2FCSR = 376 +LOONGARCH_INS_MOVGR2FRH_W = 377 +LOONGARCH_INS_MOVGR2FR_D = 378 +LOONGARCH_INS_MOVGR2FR_W = 379 +LOONGARCH_INS_MOVGR2SCR = 380 +LOONGARCH_INS_MOVSCR2GR = 381 +LOONGARCH_INS_MULH_D = 382 +LOONGARCH_INS_MULH_DU = 383 +LOONGARCH_INS_MULH_W = 384 +LOONGARCH_INS_MULH_WU = 385 +LOONGARCH_INS_MULW_D_W = 386 +LOONGARCH_INS_MULW_D_WU = 387 +LOONGARCH_INS_MUL_D = 388 +LOONGARCH_INS_MUL_W = 389 +LOONGARCH_INS_NOR = 390 +LOONGARCH_INS_OR = 391 +LOONGARCH_INS_ORI = 392 +LOONGARCH_INS_ORN = 393 +LOONGARCH_INS_PCADDI = 394 +LOONGARCH_INS_PCADDU12I = 395 +LOONGARCH_INS_PCADDU18I = 396 +LOONGARCH_INS_PCALAU12I = 397 +LOONGARCH_INS_PRELD = 398 +LOONGARCH_INS_PRELDX = 399 +LOONGARCH_INS_RCRI_B = 400 +LOONGARCH_INS_RCRI_D = 401 +LOONGARCH_INS_RCRI_H = 402 +LOONGARCH_INS_RCRI_W = 403 +LOONGARCH_INS_RCR_B = 404 +LOONGARCH_INS_RCR_D = 405 +LOONGARCH_INS_RCR_H = 406 +LOONGARCH_INS_RCR_W = 407 +LOONGARCH_INS_RDTIMEH_W = 408 +LOONGARCH_INS_RDTIMEL_W = 409 +LOONGARCH_INS_RDTIME_D = 410 +LOONGARCH_INS_REVB_2H = 411 +LOONGARCH_INS_REVB_2W = 412 +LOONGARCH_INS_REVB_4H = 413 +LOONGARCH_INS_REVB_D = 414 +LOONGARCH_INS_REVH_2W = 415 +LOONGARCH_INS_REVH_D = 416 +LOONGARCH_INS_ROTRI_B = 417 +LOONGARCH_INS_ROTRI_D = 418 +LOONGARCH_INS_ROTRI_H = 419 +LOONGARCH_INS_ROTRI_W = 420 +LOONGARCH_INS_ROTR_B = 421 +LOONGARCH_INS_ROTR_D = 422 +LOONGARCH_INS_ROTR_H = 423 +LOONGARCH_INS_ROTR_W = 424 +LOONGARCH_INS_SBC_B = 425 +LOONGARCH_INS_SBC_D = 426 +LOONGARCH_INS_SBC_H = 427 +LOONGARCH_INS_SBC_W = 428 +LOONGARCH_INS_SCREL_D = 429 +LOONGARCH_INS_SCREL_W = 430 +LOONGARCH_INS_SC_D = 431 +LOONGARCH_INS_SC_Q = 432 +LOONGARCH_INS_SC_W = 433 +LOONGARCH_INS_SETARMJ = 434 +LOONGARCH_INS_SETX86J = 435 +LOONGARCH_INS_SETX86LOOPE = 436 +LOONGARCH_INS_SETX86LOOPNE = 437 +LOONGARCH_INS_SLLI_D = 438 +LOONGARCH_INS_SLLI_W = 439 +LOONGARCH_INS_SLL_D = 440 +LOONGARCH_INS_SLL_W = 441 +LOONGARCH_INS_SLT = 442 +LOONGARCH_INS_SLTI = 443 +LOONGARCH_INS_SLTU = 444 +LOONGARCH_INS_SLTUI = 445 +LOONGARCH_INS_SRAI_D = 446 +LOONGARCH_INS_SRAI_W = 447 +LOONGARCH_INS_SRA_D = 448 +LOONGARCH_INS_SRA_W = 449 +LOONGARCH_INS_SRLI_D = 450 +LOONGARCH_INS_SRLI_W = 451 +LOONGARCH_INS_SRL_D = 452 +LOONGARCH_INS_SRL_W = 453 +LOONGARCH_INS_STGT_B = 454 +LOONGARCH_INS_STGT_D = 455 +LOONGARCH_INS_STGT_H = 456 +LOONGARCH_INS_STGT_W = 457 +LOONGARCH_INS_STLE_B = 458 +LOONGARCH_INS_STLE_D = 459 +LOONGARCH_INS_STLE_H = 460 +LOONGARCH_INS_STLE_W = 461 +LOONGARCH_INS_STL_D = 462 +LOONGARCH_INS_STL_W = 463 +LOONGARCH_INS_STPTR_D = 464 +LOONGARCH_INS_STPTR_W = 465 +LOONGARCH_INS_STR_D = 466 +LOONGARCH_INS_STR_W = 467 +LOONGARCH_INS_STX_B = 468 +LOONGARCH_INS_STX_D = 469 +LOONGARCH_INS_STX_H = 470 +LOONGARCH_INS_STX_W = 471 +LOONGARCH_INS_ST_B = 472 +LOONGARCH_INS_ST_D = 473 +LOONGARCH_INS_ST_H = 474 +LOONGARCH_INS_ST_W = 475 +LOONGARCH_INS_SUB_D = 476 +LOONGARCH_INS_SUB_W = 477 +LOONGARCH_INS_SYSCALL = 478 +LOONGARCH_INS_TLBCLR = 479 +LOONGARCH_INS_TLBFILL = 480 +LOONGARCH_INS_TLBFLUSH = 481 +LOONGARCH_INS_TLBRD = 482 +LOONGARCH_INS_TLBSRCH = 483 +LOONGARCH_INS_TLBWR = 484 +LOONGARCH_INS_VABSD_B = 485 +LOONGARCH_INS_VABSD_BU = 486 +LOONGARCH_INS_VABSD_D = 487 +LOONGARCH_INS_VABSD_DU = 488 +LOONGARCH_INS_VABSD_H = 489 +LOONGARCH_INS_VABSD_HU = 490 +LOONGARCH_INS_VABSD_W = 491 +LOONGARCH_INS_VABSD_WU = 492 +LOONGARCH_INS_VADDA_B = 493 +LOONGARCH_INS_VADDA_D = 494 +LOONGARCH_INS_VADDA_H = 495 +LOONGARCH_INS_VADDA_W = 496 +LOONGARCH_INS_VADDI_BU = 497 +LOONGARCH_INS_VADDI_DU = 498 +LOONGARCH_INS_VADDI_HU = 499 +LOONGARCH_INS_VADDI_WU = 500 +LOONGARCH_INS_VADDWEV_D_W = 501 +LOONGARCH_INS_VADDWEV_D_WU = 502 +LOONGARCH_INS_VADDWEV_D_WU_W = 503 +LOONGARCH_INS_VADDWEV_H_B = 504 +LOONGARCH_INS_VADDWEV_H_BU = 505 +LOONGARCH_INS_VADDWEV_H_BU_B = 506 +LOONGARCH_INS_VADDWEV_Q_D = 507 +LOONGARCH_INS_VADDWEV_Q_DU = 508 +LOONGARCH_INS_VADDWEV_Q_DU_D = 509 +LOONGARCH_INS_VADDWEV_W_H = 510 +LOONGARCH_INS_VADDWEV_W_HU = 511 +LOONGARCH_INS_VADDWEV_W_HU_H = 512 +LOONGARCH_INS_VADDWOD_D_W = 513 +LOONGARCH_INS_VADDWOD_D_WU = 514 +LOONGARCH_INS_VADDWOD_D_WU_W = 515 +LOONGARCH_INS_VADDWOD_H_B = 516 +LOONGARCH_INS_VADDWOD_H_BU = 517 +LOONGARCH_INS_VADDWOD_H_BU_B = 518 +LOONGARCH_INS_VADDWOD_Q_D = 519 +LOONGARCH_INS_VADDWOD_Q_DU = 520 +LOONGARCH_INS_VADDWOD_Q_DU_D = 521 +LOONGARCH_INS_VADDWOD_W_H = 522 +LOONGARCH_INS_VADDWOD_W_HU = 523 +LOONGARCH_INS_VADDWOD_W_HU_H = 524 +LOONGARCH_INS_VADD_B = 525 +LOONGARCH_INS_VADD_D = 526 +LOONGARCH_INS_VADD_H = 527 +LOONGARCH_INS_VADD_Q = 528 +LOONGARCH_INS_VADD_W = 529 +LOONGARCH_INS_VANDI_B = 530 +LOONGARCH_INS_VANDN_V = 531 +LOONGARCH_INS_VAND_V = 532 +LOONGARCH_INS_VAVGR_B = 533 +LOONGARCH_INS_VAVGR_BU = 534 +LOONGARCH_INS_VAVGR_D = 535 +LOONGARCH_INS_VAVGR_DU = 536 +LOONGARCH_INS_VAVGR_H = 537 +LOONGARCH_INS_VAVGR_HU = 538 +LOONGARCH_INS_VAVGR_W = 539 +LOONGARCH_INS_VAVGR_WU = 540 +LOONGARCH_INS_VAVG_B = 541 +LOONGARCH_INS_VAVG_BU = 542 +LOONGARCH_INS_VAVG_D = 543 +LOONGARCH_INS_VAVG_DU = 544 +LOONGARCH_INS_VAVG_H = 545 +LOONGARCH_INS_VAVG_HU = 546 +LOONGARCH_INS_VAVG_W = 547 +LOONGARCH_INS_VAVG_WU = 548 +LOONGARCH_INS_VBITCLRI_B = 549 +LOONGARCH_INS_VBITCLRI_D = 550 +LOONGARCH_INS_VBITCLRI_H = 551 +LOONGARCH_INS_VBITCLRI_W = 552 +LOONGARCH_INS_VBITCLR_B = 553 +LOONGARCH_INS_VBITCLR_D = 554 +LOONGARCH_INS_VBITCLR_H = 555 +LOONGARCH_INS_VBITCLR_W = 556 +LOONGARCH_INS_VBITREVI_B = 557 +LOONGARCH_INS_VBITREVI_D = 558 +LOONGARCH_INS_VBITREVI_H = 559 +LOONGARCH_INS_VBITREVI_W = 560 +LOONGARCH_INS_VBITREV_B = 561 +LOONGARCH_INS_VBITREV_D = 562 +LOONGARCH_INS_VBITREV_H = 563 +LOONGARCH_INS_VBITREV_W = 564 +LOONGARCH_INS_VBITSELI_B = 565 +LOONGARCH_INS_VBITSEL_V = 566 +LOONGARCH_INS_VBITSETI_B = 567 +LOONGARCH_INS_VBITSETI_D = 568 +LOONGARCH_INS_VBITSETI_H = 569 +LOONGARCH_INS_VBITSETI_W = 570 +LOONGARCH_INS_VBITSET_B = 571 +LOONGARCH_INS_VBITSET_D = 572 +LOONGARCH_INS_VBITSET_H = 573 +LOONGARCH_INS_VBITSET_W = 574 +LOONGARCH_INS_VBSLL_V = 575 +LOONGARCH_INS_VBSRL_V = 576 +LOONGARCH_INS_VCLO_B = 577 +LOONGARCH_INS_VCLO_D = 578 +LOONGARCH_INS_VCLO_H = 579 +LOONGARCH_INS_VCLO_W = 580 +LOONGARCH_INS_VCLZ_B = 581 +LOONGARCH_INS_VCLZ_D = 582 +LOONGARCH_INS_VCLZ_H = 583 +LOONGARCH_INS_VCLZ_W = 584 +LOONGARCH_INS_VDIV_B = 585 +LOONGARCH_INS_VDIV_BU = 586 +LOONGARCH_INS_VDIV_D = 587 +LOONGARCH_INS_VDIV_DU = 588 +LOONGARCH_INS_VDIV_H = 589 +LOONGARCH_INS_VDIV_HU = 590 +LOONGARCH_INS_VDIV_W = 591 +LOONGARCH_INS_VDIV_WU = 592 +LOONGARCH_INS_VEXT2XV_DU_BU = 593 +LOONGARCH_INS_VEXT2XV_DU_HU = 594 +LOONGARCH_INS_VEXT2XV_DU_WU = 595 +LOONGARCH_INS_VEXT2XV_D_B = 596 +LOONGARCH_INS_VEXT2XV_D_H = 597 +LOONGARCH_INS_VEXT2XV_D_W = 598 +LOONGARCH_INS_VEXT2XV_HU_BU = 599 +LOONGARCH_INS_VEXT2XV_H_B = 600 +LOONGARCH_INS_VEXT2XV_WU_BU = 601 +LOONGARCH_INS_VEXT2XV_WU_HU = 602 +LOONGARCH_INS_VEXT2XV_W_B = 603 +LOONGARCH_INS_VEXT2XV_W_H = 604 +LOONGARCH_INS_VEXTH_DU_WU = 605 +LOONGARCH_INS_VEXTH_D_W = 606 +LOONGARCH_INS_VEXTH_HU_BU = 607 +LOONGARCH_INS_VEXTH_H_B = 608 +LOONGARCH_INS_VEXTH_QU_DU = 609 +LOONGARCH_INS_VEXTH_Q_D = 610 +LOONGARCH_INS_VEXTH_WU_HU = 611 +LOONGARCH_INS_VEXTH_W_H = 612 +LOONGARCH_INS_VEXTL_QU_DU = 613 +LOONGARCH_INS_VEXTL_Q_D = 614 +LOONGARCH_INS_VEXTRINS_B = 615 +LOONGARCH_INS_VEXTRINS_D = 616 +LOONGARCH_INS_VEXTRINS_H = 617 +LOONGARCH_INS_VEXTRINS_W = 618 +LOONGARCH_INS_VFADD_D = 619 +LOONGARCH_INS_VFADD_S = 620 +LOONGARCH_INS_VFCLASS_D = 621 +LOONGARCH_INS_VFCLASS_S = 622 +LOONGARCH_INS_VFCMP_CAF_D = 623 +LOONGARCH_INS_VFCMP_CAF_S = 624 +LOONGARCH_INS_VFCMP_CEQ_D = 625 +LOONGARCH_INS_VFCMP_CEQ_S = 626 +LOONGARCH_INS_VFCMP_CLE_D = 627 +LOONGARCH_INS_VFCMP_CLE_S = 628 +LOONGARCH_INS_VFCMP_CLT_D = 629 +LOONGARCH_INS_VFCMP_CLT_S = 630 +LOONGARCH_INS_VFCMP_CNE_D = 631 +LOONGARCH_INS_VFCMP_CNE_S = 632 +LOONGARCH_INS_VFCMP_COR_D = 633 +LOONGARCH_INS_VFCMP_COR_S = 634 +LOONGARCH_INS_VFCMP_CUEQ_D = 635 +LOONGARCH_INS_VFCMP_CUEQ_S = 636 +LOONGARCH_INS_VFCMP_CULE_D = 637 +LOONGARCH_INS_VFCMP_CULE_S = 638 +LOONGARCH_INS_VFCMP_CULT_D = 639 +LOONGARCH_INS_VFCMP_CULT_S = 640 +LOONGARCH_INS_VFCMP_CUNE_D = 641 +LOONGARCH_INS_VFCMP_CUNE_S = 642 +LOONGARCH_INS_VFCMP_CUN_D = 643 +LOONGARCH_INS_VFCMP_CUN_S = 644 +LOONGARCH_INS_VFCMP_SAF_D = 645 +LOONGARCH_INS_VFCMP_SAF_S = 646 +LOONGARCH_INS_VFCMP_SEQ_D = 647 +LOONGARCH_INS_VFCMP_SEQ_S = 648 +LOONGARCH_INS_VFCMP_SLE_D = 649 +LOONGARCH_INS_VFCMP_SLE_S = 650 +LOONGARCH_INS_VFCMP_SLT_D = 651 +LOONGARCH_INS_VFCMP_SLT_S = 652 +LOONGARCH_INS_VFCMP_SNE_D = 653 +LOONGARCH_INS_VFCMP_SNE_S = 654 +LOONGARCH_INS_VFCMP_SOR_D = 655 +LOONGARCH_INS_VFCMP_SOR_S = 656 +LOONGARCH_INS_VFCMP_SUEQ_D = 657 +LOONGARCH_INS_VFCMP_SUEQ_S = 658 +LOONGARCH_INS_VFCMP_SULE_D = 659 +LOONGARCH_INS_VFCMP_SULE_S = 660 +LOONGARCH_INS_VFCMP_SULT_D = 661 +LOONGARCH_INS_VFCMP_SULT_S = 662 +LOONGARCH_INS_VFCMP_SUNE_D = 663 +LOONGARCH_INS_VFCMP_SUNE_S = 664 +LOONGARCH_INS_VFCMP_SUN_D = 665 +LOONGARCH_INS_VFCMP_SUN_S = 666 +LOONGARCH_INS_VFCVTH_D_S = 667 +LOONGARCH_INS_VFCVTH_S_H = 668 +LOONGARCH_INS_VFCVTL_D_S = 669 +LOONGARCH_INS_VFCVTL_S_H = 670 +LOONGARCH_INS_VFCVT_H_S = 671 +LOONGARCH_INS_VFCVT_S_D = 672 +LOONGARCH_INS_VFDIV_D = 673 +LOONGARCH_INS_VFDIV_S = 674 +LOONGARCH_INS_VFFINTH_D_W = 675 +LOONGARCH_INS_VFFINTL_D_W = 676 +LOONGARCH_INS_VFFINT_D_L = 677 +LOONGARCH_INS_VFFINT_D_LU = 678 +LOONGARCH_INS_VFFINT_S_L = 679 +LOONGARCH_INS_VFFINT_S_W = 680 +LOONGARCH_INS_VFFINT_S_WU = 681 +LOONGARCH_INS_VFLOGB_D = 682 +LOONGARCH_INS_VFLOGB_S = 683 +LOONGARCH_INS_VFMADD_D = 684 +LOONGARCH_INS_VFMADD_S = 685 +LOONGARCH_INS_VFMAXA_D = 686 +LOONGARCH_INS_VFMAXA_S = 687 +LOONGARCH_INS_VFMAX_D = 688 +LOONGARCH_INS_VFMAX_S = 689 +LOONGARCH_INS_VFMINA_D = 690 +LOONGARCH_INS_VFMINA_S = 691 +LOONGARCH_INS_VFMIN_D = 692 +LOONGARCH_INS_VFMIN_S = 693 +LOONGARCH_INS_VFMSUB_D = 694 +LOONGARCH_INS_VFMSUB_S = 695 +LOONGARCH_INS_VFMUL_D = 696 +LOONGARCH_INS_VFMUL_S = 697 +LOONGARCH_INS_VFNMADD_D = 698 +LOONGARCH_INS_VFNMADD_S = 699 +LOONGARCH_INS_VFNMSUB_D = 700 +LOONGARCH_INS_VFNMSUB_S = 701 +LOONGARCH_INS_VFRECIPE_D = 702 +LOONGARCH_INS_VFRECIPE_S = 703 +LOONGARCH_INS_VFRECIP_D = 704 +LOONGARCH_INS_VFRECIP_S = 705 +LOONGARCH_INS_VFRINTRM_D = 706 +LOONGARCH_INS_VFRINTRM_S = 707 +LOONGARCH_INS_VFRINTRNE_D = 708 +LOONGARCH_INS_VFRINTRNE_S = 709 +LOONGARCH_INS_VFRINTRP_D = 710 +LOONGARCH_INS_VFRINTRP_S = 711 +LOONGARCH_INS_VFRINTRZ_D = 712 +LOONGARCH_INS_VFRINTRZ_S = 713 +LOONGARCH_INS_VFRINT_D = 714 +LOONGARCH_INS_VFRINT_S = 715 +LOONGARCH_INS_VFRSQRTE_D = 716 +LOONGARCH_INS_VFRSQRTE_S = 717 +LOONGARCH_INS_VFRSQRT_D = 718 +LOONGARCH_INS_VFRSQRT_S = 719 +LOONGARCH_INS_VFRSTPI_B = 720 +LOONGARCH_INS_VFRSTPI_H = 721 +LOONGARCH_INS_VFRSTP_B = 722 +LOONGARCH_INS_VFRSTP_H = 723 +LOONGARCH_INS_VFSQRT_D = 724 +LOONGARCH_INS_VFSQRT_S = 725 +LOONGARCH_INS_VFSUB_D = 726 +LOONGARCH_INS_VFSUB_S = 727 +LOONGARCH_INS_VFTINTH_L_S = 728 +LOONGARCH_INS_VFTINTL_L_S = 729 +LOONGARCH_INS_VFTINTRMH_L_S = 730 +LOONGARCH_INS_VFTINTRML_L_S = 731 +LOONGARCH_INS_VFTINTRM_L_D = 732 +LOONGARCH_INS_VFTINTRM_W_D = 733 +LOONGARCH_INS_VFTINTRM_W_S = 734 +LOONGARCH_INS_VFTINTRNEH_L_S = 735 +LOONGARCH_INS_VFTINTRNEL_L_S = 736 +LOONGARCH_INS_VFTINTRNE_L_D = 737 +LOONGARCH_INS_VFTINTRNE_W_D = 738 +LOONGARCH_INS_VFTINTRNE_W_S = 739 +LOONGARCH_INS_VFTINTRPH_L_S = 740 +LOONGARCH_INS_VFTINTRPL_L_S = 741 +LOONGARCH_INS_VFTINTRP_L_D = 742 +LOONGARCH_INS_VFTINTRP_W_D = 743 +LOONGARCH_INS_VFTINTRP_W_S = 744 +LOONGARCH_INS_VFTINTRZH_L_S = 745 +LOONGARCH_INS_VFTINTRZL_L_S = 746 +LOONGARCH_INS_VFTINTRZ_LU_D = 747 +LOONGARCH_INS_VFTINTRZ_L_D = 748 +LOONGARCH_INS_VFTINTRZ_WU_S = 749 +LOONGARCH_INS_VFTINTRZ_W_D = 750 +LOONGARCH_INS_VFTINTRZ_W_S = 751 +LOONGARCH_INS_VFTINT_LU_D = 752 +LOONGARCH_INS_VFTINT_L_D = 753 +LOONGARCH_INS_VFTINT_WU_S = 754 +LOONGARCH_INS_VFTINT_W_D = 755 +LOONGARCH_INS_VFTINT_W_S = 756 +LOONGARCH_INS_VHADDW_DU_WU = 757 +LOONGARCH_INS_VHADDW_D_W = 758 +LOONGARCH_INS_VHADDW_HU_BU = 759 +LOONGARCH_INS_VHADDW_H_B = 760 +LOONGARCH_INS_VHADDW_QU_DU = 761 +LOONGARCH_INS_VHADDW_Q_D = 762 +LOONGARCH_INS_VHADDW_WU_HU = 763 +LOONGARCH_INS_VHADDW_W_H = 764 +LOONGARCH_INS_VHSUBW_DU_WU = 765 +LOONGARCH_INS_VHSUBW_D_W = 766 +LOONGARCH_INS_VHSUBW_HU_BU = 767 +LOONGARCH_INS_VHSUBW_H_B = 768 +LOONGARCH_INS_VHSUBW_QU_DU = 769 +LOONGARCH_INS_VHSUBW_Q_D = 770 +LOONGARCH_INS_VHSUBW_WU_HU = 771 +LOONGARCH_INS_VHSUBW_W_H = 772 +LOONGARCH_INS_VILVH_B = 773 +LOONGARCH_INS_VILVH_D = 774 +LOONGARCH_INS_VILVH_H = 775 +LOONGARCH_INS_VILVH_W = 776 +LOONGARCH_INS_VILVL_B = 777 +LOONGARCH_INS_VILVL_D = 778 +LOONGARCH_INS_VILVL_H = 779 +LOONGARCH_INS_VILVL_W = 780 +LOONGARCH_INS_VINSGR2VR_B = 781 +LOONGARCH_INS_VINSGR2VR_D = 782 +LOONGARCH_INS_VINSGR2VR_H = 783 +LOONGARCH_INS_VINSGR2VR_W = 784 +LOONGARCH_INS_VLD = 785 +LOONGARCH_INS_VLDI = 786 +LOONGARCH_INS_VLDREPL_B = 787 +LOONGARCH_INS_VLDREPL_D = 788 +LOONGARCH_INS_VLDREPL_H = 789 +LOONGARCH_INS_VLDREPL_W = 790 +LOONGARCH_INS_VLDX = 791 +LOONGARCH_INS_VMADDWEV_D_W = 792 +LOONGARCH_INS_VMADDWEV_D_WU = 793 +LOONGARCH_INS_VMADDWEV_D_WU_W = 794 +LOONGARCH_INS_VMADDWEV_H_B = 795 +LOONGARCH_INS_VMADDWEV_H_BU = 796 +LOONGARCH_INS_VMADDWEV_H_BU_B = 797 +LOONGARCH_INS_VMADDWEV_Q_D = 798 +LOONGARCH_INS_VMADDWEV_Q_DU = 799 +LOONGARCH_INS_VMADDWEV_Q_DU_D = 800 +LOONGARCH_INS_VMADDWEV_W_H = 801 +LOONGARCH_INS_VMADDWEV_W_HU = 802 +LOONGARCH_INS_VMADDWEV_W_HU_H = 803 +LOONGARCH_INS_VMADDWOD_D_W = 804 +LOONGARCH_INS_VMADDWOD_D_WU = 805 +LOONGARCH_INS_VMADDWOD_D_WU_W = 806 +LOONGARCH_INS_VMADDWOD_H_B = 807 +LOONGARCH_INS_VMADDWOD_H_BU = 808 +LOONGARCH_INS_VMADDWOD_H_BU_B = 809 +LOONGARCH_INS_VMADDWOD_Q_D = 810 +LOONGARCH_INS_VMADDWOD_Q_DU = 811 +LOONGARCH_INS_VMADDWOD_Q_DU_D = 812 +LOONGARCH_INS_VMADDWOD_W_H = 813 +LOONGARCH_INS_VMADDWOD_W_HU = 814 +LOONGARCH_INS_VMADDWOD_W_HU_H = 815 +LOONGARCH_INS_VMADD_B = 816 +LOONGARCH_INS_VMADD_D = 817 +LOONGARCH_INS_VMADD_H = 818 +LOONGARCH_INS_VMADD_W = 819 +LOONGARCH_INS_VMAXI_B = 820 +LOONGARCH_INS_VMAXI_BU = 821 +LOONGARCH_INS_VMAXI_D = 822 +LOONGARCH_INS_VMAXI_DU = 823 +LOONGARCH_INS_VMAXI_H = 824 +LOONGARCH_INS_VMAXI_HU = 825 +LOONGARCH_INS_VMAXI_W = 826 +LOONGARCH_INS_VMAXI_WU = 827 +LOONGARCH_INS_VMAX_B = 828 +LOONGARCH_INS_VMAX_BU = 829 +LOONGARCH_INS_VMAX_D = 830 +LOONGARCH_INS_VMAX_DU = 831 +LOONGARCH_INS_VMAX_H = 832 +LOONGARCH_INS_VMAX_HU = 833 +LOONGARCH_INS_VMAX_W = 834 +LOONGARCH_INS_VMAX_WU = 835 +LOONGARCH_INS_VMINI_B = 836 +LOONGARCH_INS_VMINI_BU = 837 +LOONGARCH_INS_VMINI_D = 838 +LOONGARCH_INS_VMINI_DU = 839 +LOONGARCH_INS_VMINI_H = 840 +LOONGARCH_INS_VMINI_HU = 841 +LOONGARCH_INS_VMINI_W = 842 +LOONGARCH_INS_VMINI_WU = 843 +LOONGARCH_INS_VMIN_B = 844 +LOONGARCH_INS_VMIN_BU = 845 +LOONGARCH_INS_VMIN_D = 846 +LOONGARCH_INS_VMIN_DU = 847 +LOONGARCH_INS_VMIN_H = 848 +LOONGARCH_INS_VMIN_HU = 849 +LOONGARCH_INS_VMIN_W = 850 +LOONGARCH_INS_VMIN_WU = 851 +LOONGARCH_INS_VMOD_B = 852 +LOONGARCH_INS_VMOD_BU = 853 +LOONGARCH_INS_VMOD_D = 854 +LOONGARCH_INS_VMOD_DU = 855 +LOONGARCH_INS_VMOD_H = 856 +LOONGARCH_INS_VMOD_HU = 857 +LOONGARCH_INS_VMOD_W = 858 +LOONGARCH_INS_VMOD_WU = 859 +LOONGARCH_INS_VMSKGEZ_B = 860 +LOONGARCH_INS_VMSKLTZ_B = 861 +LOONGARCH_INS_VMSKLTZ_D = 862 +LOONGARCH_INS_VMSKLTZ_H = 863 +LOONGARCH_INS_VMSKLTZ_W = 864 +LOONGARCH_INS_VMSKNZ_B = 865 +LOONGARCH_INS_VMSUB_B = 866 +LOONGARCH_INS_VMSUB_D = 867 +LOONGARCH_INS_VMSUB_H = 868 +LOONGARCH_INS_VMSUB_W = 869 +LOONGARCH_INS_VMUH_B = 870 +LOONGARCH_INS_VMUH_BU = 871 +LOONGARCH_INS_VMUH_D = 872 +LOONGARCH_INS_VMUH_DU = 873 +LOONGARCH_INS_VMUH_H = 874 +LOONGARCH_INS_VMUH_HU = 875 +LOONGARCH_INS_VMUH_W = 876 +LOONGARCH_INS_VMUH_WU = 877 +LOONGARCH_INS_VMULWEV_D_W = 878 +LOONGARCH_INS_VMULWEV_D_WU = 879 +LOONGARCH_INS_VMULWEV_D_WU_W = 880 +LOONGARCH_INS_VMULWEV_H_B = 881 +LOONGARCH_INS_VMULWEV_H_BU = 882 +LOONGARCH_INS_VMULWEV_H_BU_B = 883 +LOONGARCH_INS_VMULWEV_Q_D = 884 +LOONGARCH_INS_VMULWEV_Q_DU = 885 +LOONGARCH_INS_VMULWEV_Q_DU_D = 886 +LOONGARCH_INS_VMULWEV_W_H = 887 +LOONGARCH_INS_VMULWEV_W_HU = 888 +LOONGARCH_INS_VMULWEV_W_HU_H = 889 +LOONGARCH_INS_VMULWOD_D_W = 890 +LOONGARCH_INS_VMULWOD_D_WU = 891 +LOONGARCH_INS_VMULWOD_D_WU_W = 892 +LOONGARCH_INS_VMULWOD_H_B = 893 +LOONGARCH_INS_VMULWOD_H_BU = 894 +LOONGARCH_INS_VMULWOD_H_BU_B = 895 +LOONGARCH_INS_VMULWOD_Q_D = 896 +LOONGARCH_INS_VMULWOD_Q_DU = 897 +LOONGARCH_INS_VMULWOD_Q_DU_D = 898 +LOONGARCH_INS_VMULWOD_W_H = 899 +LOONGARCH_INS_VMULWOD_W_HU = 900 +LOONGARCH_INS_VMULWOD_W_HU_H = 901 +LOONGARCH_INS_VMUL_B = 902 +LOONGARCH_INS_VMUL_D = 903 +LOONGARCH_INS_VMUL_H = 904 +LOONGARCH_INS_VMUL_W = 905 +LOONGARCH_INS_VNEG_B = 906 +LOONGARCH_INS_VNEG_D = 907 +LOONGARCH_INS_VNEG_H = 908 +LOONGARCH_INS_VNEG_W = 909 +LOONGARCH_INS_VNORI_B = 910 +LOONGARCH_INS_VNOR_V = 911 +LOONGARCH_INS_VORI_B = 912 +LOONGARCH_INS_VORN_V = 913 +LOONGARCH_INS_VOR_V = 914 +LOONGARCH_INS_VPACKEV_B = 915 +LOONGARCH_INS_VPACKEV_D = 916 +LOONGARCH_INS_VPACKEV_H = 917 +LOONGARCH_INS_VPACKEV_W = 918 +LOONGARCH_INS_VPACKOD_B = 919 +LOONGARCH_INS_VPACKOD_D = 920 +LOONGARCH_INS_VPACKOD_H = 921 +LOONGARCH_INS_VPACKOD_W = 922 +LOONGARCH_INS_VPCNT_B = 923 +LOONGARCH_INS_VPCNT_D = 924 +LOONGARCH_INS_VPCNT_H = 925 +LOONGARCH_INS_VPCNT_W = 926 +LOONGARCH_INS_VPERMI_W = 927 +LOONGARCH_INS_VPICKEV_B = 928 +LOONGARCH_INS_VPICKEV_D = 929 +LOONGARCH_INS_VPICKEV_H = 930 +LOONGARCH_INS_VPICKEV_W = 931 +LOONGARCH_INS_VPICKOD_B = 932 +LOONGARCH_INS_VPICKOD_D = 933 +LOONGARCH_INS_VPICKOD_H = 934 +LOONGARCH_INS_VPICKOD_W = 935 +LOONGARCH_INS_VPICKVE2GR_B = 936 +LOONGARCH_INS_VPICKVE2GR_BU = 937 +LOONGARCH_INS_VPICKVE2GR_D = 938 +LOONGARCH_INS_VPICKVE2GR_DU = 939 +LOONGARCH_INS_VPICKVE2GR_H = 940 +LOONGARCH_INS_VPICKVE2GR_HU = 941 +LOONGARCH_INS_VPICKVE2GR_W = 942 +LOONGARCH_INS_VPICKVE2GR_WU = 943 +LOONGARCH_INS_VREPLGR2VR_B = 944 +LOONGARCH_INS_VREPLGR2VR_D = 945 +LOONGARCH_INS_VREPLGR2VR_H = 946 +LOONGARCH_INS_VREPLGR2VR_W = 947 +LOONGARCH_INS_VREPLVEI_B = 948 +LOONGARCH_INS_VREPLVEI_D = 949 +LOONGARCH_INS_VREPLVEI_H = 950 +LOONGARCH_INS_VREPLVEI_W = 951 +LOONGARCH_INS_VREPLVE_B = 952 +LOONGARCH_INS_VREPLVE_D = 953 +LOONGARCH_INS_VREPLVE_H = 954 +LOONGARCH_INS_VREPLVE_W = 955 +LOONGARCH_INS_VROTRI_B = 956 +LOONGARCH_INS_VROTRI_D = 957 +LOONGARCH_INS_VROTRI_H = 958 +LOONGARCH_INS_VROTRI_W = 959 +LOONGARCH_INS_VROTR_B = 960 +LOONGARCH_INS_VROTR_D = 961 +LOONGARCH_INS_VROTR_H = 962 +LOONGARCH_INS_VROTR_W = 963 +LOONGARCH_INS_VSADD_B = 964 +LOONGARCH_INS_VSADD_BU = 965 +LOONGARCH_INS_VSADD_D = 966 +LOONGARCH_INS_VSADD_DU = 967 +LOONGARCH_INS_VSADD_H = 968 +LOONGARCH_INS_VSADD_HU = 969 +LOONGARCH_INS_VSADD_W = 970 +LOONGARCH_INS_VSADD_WU = 971 +LOONGARCH_INS_VSAT_B = 972 +LOONGARCH_INS_VSAT_BU = 973 +LOONGARCH_INS_VSAT_D = 974 +LOONGARCH_INS_VSAT_DU = 975 +LOONGARCH_INS_VSAT_H = 976 +LOONGARCH_INS_VSAT_HU = 977 +LOONGARCH_INS_VSAT_W = 978 +LOONGARCH_INS_VSAT_WU = 979 +LOONGARCH_INS_VSEQI_B = 980 +LOONGARCH_INS_VSEQI_D = 981 +LOONGARCH_INS_VSEQI_H = 982 +LOONGARCH_INS_VSEQI_W = 983 +LOONGARCH_INS_VSEQ_B = 984 +LOONGARCH_INS_VSEQ_D = 985 +LOONGARCH_INS_VSEQ_H = 986 +LOONGARCH_INS_VSEQ_W = 987 +LOONGARCH_INS_VSETALLNEZ_B = 988 +LOONGARCH_INS_VSETALLNEZ_D = 989 +LOONGARCH_INS_VSETALLNEZ_H = 990 +LOONGARCH_INS_VSETALLNEZ_W = 991 +LOONGARCH_INS_VSETANYEQZ_B = 992 +LOONGARCH_INS_VSETANYEQZ_D = 993 +LOONGARCH_INS_VSETANYEQZ_H = 994 +LOONGARCH_INS_VSETANYEQZ_W = 995 +LOONGARCH_INS_VSETEQZ_V = 996 +LOONGARCH_INS_VSETNEZ_V = 997 +LOONGARCH_INS_VSHUF4I_B = 998 +LOONGARCH_INS_VSHUF4I_D = 999 +LOONGARCH_INS_VSHUF4I_H = 1000 +LOONGARCH_INS_VSHUF4I_W = 1001 +LOONGARCH_INS_VSHUF_B = 1002 +LOONGARCH_INS_VSHUF_D = 1003 +LOONGARCH_INS_VSHUF_H = 1004 +LOONGARCH_INS_VSHUF_W = 1005 +LOONGARCH_INS_VSIGNCOV_B = 1006 +LOONGARCH_INS_VSIGNCOV_D = 1007 +LOONGARCH_INS_VSIGNCOV_H = 1008 +LOONGARCH_INS_VSIGNCOV_W = 1009 +LOONGARCH_INS_VSLEI_B = 1010 +LOONGARCH_INS_VSLEI_BU = 1011 +LOONGARCH_INS_VSLEI_D = 1012 +LOONGARCH_INS_VSLEI_DU = 1013 +LOONGARCH_INS_VSLEI_H = 1014 +LOONGARCH_INS_VSLEI_HU = 1015 +LOONGARCH_INS_VSLEI_W = 1016 +LOONGARCH_INS_VSLEI_WU = 1017 +LOONGARCH_INS_VSLE_B = 1018 +LOONGARCH_INS_VSLE_BU = 1019 +LOONGARCH_INS_VSLE_D = 1020 +LOONGARCH_INS_VSLE_DU = 1021 +LOONGARCH_INS_VSLE_H = 1022 +LOONGARCH_INS_VSLE_HU = 1023 +LOONGARCH_INS_VSLE_W = 1024 +LOONGARCH_INS_VSLE_WU = 1025 +LOONGARCH_INS_VSLLI_B = 1026 +LOONGARCH_INS_VSLLI_D = 1027 +LOONGARCH_INS_VSLLI_H = 1028 +LOONGARCH_INS_VSLLI_W = 1029 +LOONGARCH_INS_VSLLWIL_DU_WU = 1030 +LOONGARCH_INS_VSLLWIL_D_W = 1031 +LOONGARCH_INS_VSLLWIL_HU_BU = 1032 +LOONGARCH_INS_VSLLWIL_H_B = 1033 +LOONGARCH_INS_VSLLWIL_WU_HU = 1034 +LOONGARCH_INS_VSLLWIL_W_H = 1035 +LOONGARCH_INS_VSLL_B = 1036 +LOONGARCH_INS_VSLL_D = 1037 +LOONGARCH_INS_VSLL_H = 1038 +LOONGARCH_INS_VSLL_W = 1039 +LOONGARCH_INS_VSLTI_B = 1040 +LOONGARCH_INS_VSLTI_BU = 1041 +LOONGARCH_INS_VSLTI_D = 1042 +LOONGARCH_INS_VSLTI_DU = 1043 +LOONGARCH_INS_VSLTI_H = 1044 +LOONGARCH_INS_VSLTI_HU = 1045 +LOONGARCH_INS_VSLTI_W = 1046 +LOONGARCH_INS_VSLTI_WU = 1047 +LOONGARCH_INS_VSLT_B = 1048 +LOONGARCH_INS_VSLT_BU = 1049 +LOONGARCH_INS_VSLT_D = 1050 +LOONGARCH_INS_VSLT_DU = 1051 +LOONGARCH_INS_VSLT_H = 1052 +LOONGARCH_INS_VSLT_HU = 1053 +LOONGARCH_INS_VSLT_W = 1054 +LOONGARCH_INS_VSLT_WU = 1055 +LOONGARCH_INS_VSRAI_B = 1056 +LOONGARCH_INS_VSRAI_D = 1057 +LOONGARCH_INS_VSRAI_H = 1058 +LOONGARCH_INS_VSRAI_W = 1059 +LOONGARCH_INS_VSRANI_B_H = 1060 +LOONGARCH_INS_VSRANI_D_Q = 1061 +LOONGARCH_INS_VSRANI_H_W = 1062 +LOONGARCH_INS_VSRANI_W_D = 1063 +LOONGARCH_INS_VSRAN_B_H = 1064 +LOONGARCH_INS_VSRAN_H_W = 1065 +LOONGARCH_INS_VSRAN_W_D = 1066 +LOONGARCH_INS_VSRARI_B = 1067 +LOONGARCH_INS_VSRARI_D = 1068 +LOONGARCH_INS_VSRARI_H = 1069 +LOONGARCH_INS_VSRARI_W = 1070 +LOONGARCH_INS_VSRARNI_B_H = 1071 +LOONGARCH_INS_VSRARNI_D_Q = 1072 +LOONGARCH_INS_VSRARNI_H_W = 1073 +LOONGARCH_INS_VSRARNI_W_D = 1074 +LOONGARCH_INS_VSRARN_B_H = 1075 +LOONGARCH_INS_VSRARN_H_W = 1076 +LOONGARCH_INS_VSRARN_W_D = 1077 +LOONGARCH_INS_VSRAR_B = 1078 +LOONGARCH_INS_VSRAR_D = 1079 +LOONGARCH_INS_VSRAR_H = 1080 +LOONGARCH_INS_VSRAR_W = 1081 +LOONGARCH_INS_VSRA_B = 1082 +LOONGARCH_INS_VSRA_D = 1083 +LOONGARCH_INS_VSRA_H = 1084 +LOONGARCH_INS_VSRA_W = 1085 +LOONGARCH_INS_VSRLI_B = 1086 +LOONGARCH_INS_VSRLI_D = 1087 +LOONGARCH_INS_VSRLI_H = 1088 +LOONGARCH_INS_VSRLI_W = 1089 +LOONGARCH_INS_VSRLNI_B_H = 1090 +LOONGARCH_INS_VSRLNI_D_Q = 1091 +LOONGARCH_INS_VSRLNI_H_W = 1092 +LOONGARCH_INS_VSRLNI_W_D = 1093 +LOONGARCH_INS_VSRLN_B_H = 1094 +LOONGARCH_INS_VSRLN_H_W = 1095 +LOONGARCH_INS_VSRLN_W_D = 1096 +LOONGARCH_INS_VSRLRI_B = 1097 +LOONGARCH_INS_VSRLRI_D = 1098 +LOONGARCH_INS_VSRLRI_H = 1099 +LOONGARCH_INS_VSRLRI_W = 1100 +LOONGARCH_INS_VSRLRNI_B_H = 1101 +LOONGARCH_INS_VSRLRNI_D_Q = 1102 +LOONGARCH_INS_VSRLRNI_H_W = 1103 +LOONGARCH_INS_VSRLRNI_W_D = 1104 +LOONGARCH_INS_VSRLRN_B_H = 1105 +LOONGARCH_INS_VSRLRN_H_W = 1106 +LOONGARCH_INS_VSRLRN_W_D = 1107 +LOONGARCH_INS_VSRLR_B = 1108 +LOONGARCH_INS_VSRLR_D = 1109 +LOONGARCH_INS_VSRLR_H = 1110 +LOONGARCH_INS_VSRLR_W = 1111 +LOONGARCH_INS_VSRL_B = 1112 +LOONGARCH_INS_VSRL_D = 1113 +LOONGARCH_INS_VSRL_H = 1114 +LOONGARCH_INS_VSRL_W = 1115 +LOONGARCH_INS_VSSRANI_BU_H = 1116 +LOONGARCH_INS_VSSRANI_B_H = 1117 +LOONGARCH_INS_VSSRANI_DU_Q = 1118 +LOONGARCH_INS_VSSRANI_D_Q = 1119 +LOONGARCH_INS_VSSRANI_HU_W = 1120 +LOONGARCH_INS_VSSRANI_H_W = 1121 +LOONGARCH_INS_VSSRANI_WU_D = 1122 +LOONGARCH_INS_VSSRANI_W_D = 1123 +LOONGARCH_INS_VSSRAN_BU_H = 1124 +LOONGARCH_INS_VSSRAN_B_H = 1125 +LOONGARCH_INS_VSSRAN_HU_W = 1126 +LOONGARCH_INS_VSSRAN_H_W = 1127 +LOONGARCH_INS_VSSRAN_WU_D = 1128 +LOONGARCH_INS_VSSRAN_W_D = 1129 +LOONGARCH_INS_VSSRARNI_BU_H = 1130 +LOONGARCH_INS_VSSRARNI_B_H = 1131 +LOONGARCH_INS_VSSRARNI_DU_Q = 1132 +LOONGARCH_INS_VSSRARNI_D_Q = 1133 +LOONGARCH_INS_VSSRARNI_HU_W = 1134 +LOONGARCH_INS_VSSRARNI_H_W = 1135 +LOONGARCH_INS_VSSRARNI_WU_D = 1136 +LOONGARCH_INS_VSSRARNI_W_D = 1137 +LOONGARCH_INS_VSSRARN_BU_H = 1138 +LOONGARCH_INS_VSSRARN_B_H = 1139 +LOONGARCH_INS_VSSRARN_HU_W = 1140 +LOONGARCH_INS_VSSRARN_H_W = 1141 +LOONGARCH_INS_VSSRARN_WU_D = 1142 +LOONGARCH_INS_VSSRARN_W_D = 1143 +LOONGARCH_INS_VSSRLNI_BU_H = 1144 +LOONGARCH_INS_VSSRLNI_B_H = 1145 +LOONGARCH_INS_VSSRLNI_DU_Q = 1146 +LOONGARCH_INS_VSSRLNI_D_Q = 1147 +LOONGARCH_INS_VSSRLNI_HU_W = 1148 +LOONGARCH_INS_VSSRLNI_H_W = 1149 +LOONGARCH_INS_VSSRLNI_WU_D = 1150 +LOONGARCH_INS_VSSRLNI_W_D = 1151 +LOONGARCH_INS_VSSRLN_BU_H = 1152 +LOONGARCH_INS_VSSRLN_B_H = 1153 +LOONGARCH_INS_VSSRLN_HU_W = 1154 +LOONGARCH_INS_VSSRLN_H_W = 1155 +LOONGARCH_INS_VSSRLN_WU_D = 1156 +LOONGARCH_INS_VSSRLN_W_D = 1157 +LOONGARCH_INS_VSSRLRNI_BU_H = 1158 +LOONGARCH_INS_VSSRLRNI_B_H = 1159 +LOONGARCH_INS_VSSRLRNI_DU_Q = 1160 +LOONGARCH_INS_VSSRLRNI_D_Q = 1161 +LOONGARCH_INS_VSSRLRNI_HU_W = 1162 +LOONGARCH_INS_VSSRLRNI_H_W = 1163 +LOONGARCH_INS_VSSRLRNI_WU_D = 1164 +LOONGARCH_INS_VSSRLRNI_W_D = 1165 +LOONGARCH_INS_VSSRLRN_BU_H = 1166 +LOONGARCH_INS_VSSRLRN_B_H = 1167 +LOONGARCH_INS_VSSRLRN_HU_W = 1168 +LOONGARCH_INS_VSSRLRN_H_W = 1169 +LOONGARCH_INS_VSSRLRN_WU_D = 1170 +LOONGARCH_INS_VSSRLRN_W_D = 1171 +LOONGARCH_INS_VSSUB_B = 1172 +LOONGARCH_INS_VSSUB_BU = 1173 +LOONGARCH_INS_VSSUB_D = 1174 +LOONGARCH_INS_VSSUB_DU = 1175 +LOONGARCH_INS_VSSUB_H = 1176 +LOONGARCH_INS_VSSUB_HU = 1177 +LOONGARCH_INS_VSSUB_W = 1178 +LOONGARCH_INS_VSSUB_WU = 1179 +LOONGARCH_INS_VST = 1180 +LOONGARCH_INS_VSTELM_B = 1181 +LOONGARCH_INS_VSTELM_D = 1182 +LOONGARCH_INS_VSTELM_H = 1183 +LOONGARCH_INS_VSTELM_W = 1184 +LOONGARCH_INS_VSTX = 1185 +LOONGARCH_INS_VSUBI_BU = 1186 +LOONGARCH_INS_VSUBI_DU = 1187 +LOONGARCH_INS_VSUBI_HU = 1188 +LOONGARCH_INS_VSUBI_WU = 1189 +LOONGARCH_INS_VSUBWEV_D_W = 1190 +LOONGARCH_INS_VSUBWEV_D_WU = 1191 +LOONGARCH_INS_VSUBWEV_H_B = 1192 +LOONGARCH_INS_VSUBWEV_H_BU = 1193 +LOONGARCH_INS_VSUBWEV_Q_D = 1194 +LOONGARCH_INS_VSUBWEV_Q_DU = 1195 +LOONGARCH_INS_VSUBWEV_W_H = 1196 +LOONGARCH_INS_VSUBWEV_W_HU = 1197 +LOONGARCH_INS_VSUBWOD_D_W = 1198 +LOONGARCH_INS_VSUBWOD_D_WU = 1199 +LOONGARCH_INS_VSUBWOD_H_B = 1200 +LOONGARCH_INS_VSUBWOD_H_BU = 1201 +LOONGARCH_INS_VSUBWOD_Q_D = 1202 +LOONGARCH_INS_VSUBWOD_Q_DU = 1203 +LOONGARCH_INS_VSUBWOD_W_H = 1204 +LOONGARCH_INS_VSUBWOD_W_HU = 1205 +LOONGARCH_INS_VSUB_B = 1206 +LOONGARCH_INS_VSUB_D = 1207 +LOONGARCH_INS_VSUB_H = 1208 +LOONGARCH_INS_VSUB_Q = 1209 +LOONGARCH_INS_VSUB_W = 1210 +LOONGARCH_INS_VXORI_B = 1211 +LOONGARCH_INS_VXOR_V = 1212 +LOONGARCH_INS_X86ADC_B = 1213 +LOONGARCH_INS_X86ADC_D = 1214 +LOONGARCH_INS_X86ADC_H = 1215 +LOONGARCH_INS_X86ADC_W = 1216 +LOONGARCH_INS_X86ADD_B = 1217 +LOONGARCH_INS_X86ADD_D = 1218 +LOONGARCH_INS_X86ADD_DU = 1219 +LOONGARCH_INS_X86ADD_H = 1220 +LOONGARCH_INS_X86ADD_W = 1221 +LOONGARCH_INS_X86ADD_WU = 1222 +LOONGARCH_INS_X86AND_B = 1223 +LOONGARCH_INS_X86AND_D = 1224 +LOONGARCH_INS_X86AND_H = 1225 +LOONGARCH_INS_X86AND_W = 1226 +LOONGARCH_INS_X86CLRTM = 1227 +LOONGARCH_INS_X86DECTOP = 1228 +LOONGARCH_INS_X86DEC_B = 1229 +LOONGARCH_INS_X86DEC_D = 1230 +LOONGARCH_INS_X86DEC_H = 1231 +LOONGARCH_INS_X86DEC_W = 1232 +LOONGARCH_INS_X86INCTOP = 1233 +LOONGARCH_INS_X86INC_B = 1234 +LOONGARCH_INS_X86INC_D = 1235 +LOONGARCH_INS_X86INC_H = 1236 +LOONGARCH_INS_X86INC_W = 1237 +LOONGARCH_INS_X86MFFLAG = 1238 +LOONGARCH_INS_X86MFTOP = 1239 +LOONGARCH_INS_X86MTFLAG = 1240 +LOONGARCH_INS_X86MTTOP = 1241 +LOONGARCH_INS_X86MUL_B = 1242 +LOONGARCH_INS_X86MUL_BU = 1243 +LOONGARCH_INS_X86MUL_D = 1244 +LOONGARCH_INS_X86MUL_DU = 1245 +LOONGARCH_INS_X86MUL_H = 1246 +LOONGARCH_INS_X86MUL_HU = 1247 +LOONGARCH_INS_X86MUL_W = 1248 +LOONGARCH_INS_X86MUL_WU = 1249 +LOONGARCH_INS_X86OR_B = 1250 +LOONGARCH_INS_X86OR_D = 1251 +LOONGARCH_INS_X86OR_H = 1252 +LOONGARCH_INS_X86OR_W = 1253 +LOONGARCH_INS_X86RCLI_B = 1254 +LOONGARCH_INS_X86RCLI_D = 1255 +LOONGARCH_INS_X86RCLI_H = 1256 +LOONGARCH_INS_X86RCLI_W = 1257 +LOONGARCH_INS_X86RCL_B = 1258 +LOONGARCH_INS_X86RCL_D = 1259 +LOONGARCH_INS_X86RCL_H = 1260 +LOONGARCH_INS_X86RCL_W = 1261 +LOONGARCH_INS_X86RCRI_B = 1262 +LOONGARCH_INS_X86RCRI_D = 1263 +LOONGARCH_INS_X86RCRI_H = 1264 +LOONGARCH_INS_X86RCRI_W = 1265 +LOONGARCH_INS_X86RCR_B = 1266 +LOONGARCH_INS_X86RCR_D = 1267 +LOONGARCH_INS_X86RCR_H = 1268 +LOONGARCH_INS_X86RCR_W = 1269 +LOONGARCH_INS_X86ROTLI_B = 1270 +LOONGARCH_INS_X86ROTLI_D = 1271 +LOONGARCH_INS_X86ROTLI_H = 1272 +LOONGARCH_INS_X86ROTLI_W = 1273 +LOONGARCH_INS_X86ROTL_B = 1274 +LOONGARCH_INS_X86ROTL_D = 1275 +LOONGARCH_INS_X86ROTL_H = 1276 +LOONGARCH_INS_X86ROTL_W = 1277 +LOONGARCH_INS_X86ROTRI_B = 1278 +LOONGARCH_INS_X86ROTRI_D = 1279 +LOONGARCH_INS_X86ROTRI_H = 1280 +LOONGARCH_INS_X86ROTRI_W = 1281 +LOONGARCH_INS_X86ROTR_B = 1282 +LOONGARCH_INS_X86ROTR_D = 1283 +LOONGARCH_INS_X86ROTR_H = 1284 +LOONGARCH_INS_X86ROTR_W = 1285 +LOONGARCH_INS_X86SBC_B = 1286 +LOONGARCH_INS_X86SBC_D = 1287 +LOONGARCH_INS_X86SBC_H = 1288 +LOONGARCH_INS_X86SBC_W = 1289 +LOONGARCH_INS_X86SETTAG = 1290 +LOONGARCH_INS_X86SETTM = 1291 +LOONGARCH_INS_X86SLLI_B = 1292 +LOONGARCH_INS_X86SLLI_D = 1293 +LOONGARCH_INS_X86SLLI_H = 1294 +LOONGARCH_INS_X86SLLI_W = 1295 +LOONGARCH_INS_X86SLL_B = 1296 +LOONGARCH_INS_X86SLL_D = 1297 +LOONGARCH_INS_X86SLL_H = 1298 +LOONGARCH_INS_X86SLL_W = 1299 +LOONGARCH_INS_X86SRAI_B = 1300 +LOONGARCH_INS_X86SRAI_D = 1301 +LOONGARCH_INS_X86SRAI_H = 1302 +LOONGARCH_INS_X86SRAI_W = 1303 +LOONGARCH_INS_X86SRA_B = 1304 +LOONGARCH_INS_X86SRA_D = 1305 +LOONGARCH_INS_X86SRA_H = 1306 +LOONGARCH_INS_X86SRA_W = 1307 +LOONGARCH_INS_X86SRLI_B = 1308 +LOONGARCH_INS_X86SRLI_D = 1309 +LOONGARCH_INS_X86SRLI_H = 1310 +LOONGARCH_INS_X86SRLI_W = 1311 +LOONGARCH_INS_X86SRL_B = 1312 +LOONGARCH_INS_X86SRL_D = 1313 +LOONGARCH_INS_X86SRL_H = 1314 +LOONGARCH_INS_X86SRL_W = 1315 +LOONGARCH_INS_X86SUB_B = 1316 +LOONGARCH_INS_X86SUB_D = 1317 +LOONGARCH_INS_X86SUB_DU = 1318 +LOONGARCH_INS_X86SUB_H = 1319 +LOONGARCH_INS_X86SUB_W = 1320 +LOONGARCH_INS_X86SUB_WU = 1321 +LOONGARCH_INS_X86XOR_B = 1322 +LOONGARCH_INS_X86XOR_D = 1323 +LOONGARCH_INS_X86XOR_H = 1324 +LOONGARCH_INS_X86XOR_W = 1325 +LOONGARCH_INS_XOR = 1326 +LOONGARCH_INS_XORI = 1327 +LOONGARCH_INS_XVABSD_B = 1328 +LOONGARCH_INS_XVABSD_BU = 1329 +LOONGARCH_INS_XVABSD_D = 1330 +LOONGARCH_INS_XVABSD_DU = 1331 +LOONGARCH_INS_XVABSD_H = 1332 +LOONGARCH_INS_XVABSD_HU = 1333 +LOONGARCH_INS_XVABSD_W = 1334 +LOONGARCH_INS_XVABSD_WU = 1335 +LOONGARCH_INS_XVADDA_B = 1336 +LOONGARCH_INS_XVADDA_D = 1337 +LOONGARCH_INS_XVADDA_H = 1338 +LOONGARCH_INS_XVADDA_W = 1339 +LOONGARCH_INS_XVADDI_BU = 1340 +LOONGARCH_INS_XVADDI_DU = 1341 +LOONGARCH_INS_XVADDI_HU = 1342 +LOONGARCH_INS_XVADDI_WU = 1343 +LOONGARCH_INS_XVADDWEV_D_W = 1344 +LOONGARCH_INS_XVADDWEV_D_WU = 1345 +LOONGARCH_INS_XVADDWEV_D_WU_W = 1346 +LOONGARCH_INS_XVADDWEV_H_B = 1347 +LOONGARCH_INS_XVADDWEV_H_BU = 1348 +LOONGARCH_INS_XVADDWEV_H_BU_B = 1349 +LOONGARCH_INS_XVADDWEV_Q_D = 1350 +LOONGARCH_INS_XVADDWEV_Q_DU = 1351 +LOONGARCH_INS_XVADDWEV_Q_DU_D = 1352 +LOONGARCH_INS_XVADDWEV_W_H = 1353 +LOONGARCH_INS_XVADDWEV_W_HU = 1354 +LOONGARCH_INS_XVADDWEV_W_HU_H = 1355 +LOONGARCH_INS_XVADDWOD_D_W = 1356 +LOONGARCH_INS_XVADDWOD_D_WU = 1357 +LOONGARCH_INS_XVADDWOD_D_WU_W = 1358 +LOONGARCH_INS_XVADDWOD_H_B = 1359 +LOONGARCH_INS_XVADDWOD_H_BU = 1360 +LOONGARCH_INS_XVADDWOD_H_BU_B = 1361 +LOONGARCH_INS_XVADDWOD_Q_D = 1362 +LOONGARCH_INS_XVADDWOD_Q_DU = 1363 +LOONGARCH_INS_XVADDWOD_Q_DU_D = 1364 +LOONGARCH_INS_XVADDWOD_W_H = 1365 +LOONGARCH_INS_XVADDWOD_W_HU = 1366 +LOONGARCH_INS_XVADDWOD_W_HU_H = 1367 +LOONGARCH_INS_XVADD_B = 1368 +LOONGARCH_INS_XVADD_D = 1369 +LOONGARCH_INS_XVADD_H = 1370 +LOONGARCH_INS_XVADD_Q = 1371 +LOONGARCH_INS_XVADD_W = 1372 +LOONGARCH_INS_XVANDI_B = 1373 +LOONGARCH_INS_XVANDN_V = 1374 +LOONGARCH_INS_XVAND_V = 1375 +LOONGARCH_INS_XVAVGR_B = 1376 +LOONGARCH_INS_XVAVGR_BU = 1377 +LOONGARCH_INS_XVAVGR_D = 1378 +LOONGARCH_INS_XVAVGR_DU = 1379 +LOONGARCH_INS_XVAVGR_H = 1380 +LOONGARCH_INS_XVAVGR_HU = 1381 +LOONGARCH_INS_XVAVGR_W = 1382 +LOONGARCH_INS_XVAVGR_WU = 1383 +LOONGARCH_INS_XVAVG_B = 1384 +LOONGARCH_INS_XVAVG_BU = 1385 +LOONGARCH_INS_XVAVG_D = 1386 +LOONGARCH_INS_XVAVG_DU = 1387 +LOONGARCH_INS_XVAVG_H = 1388 +LOONGARCH_INS_XVAVG_HU = 1389 +LOONGARCH_INS_XVAVG_W = 1390 +LOONGARCH_INS_XVAVG_WU = 1391 +LOONGARCH_INS_XVBITCLRI_B = 1392 +LOONGARCH_INS_XVBITCLRI_D = 1393 +LOONGARCH_INS_XVBITCLRI_H = 1394 +LOONGARCH_INS_XVBITCLRI_W = 1395 +LOONGARCH_INS_XVBITCLR_B = 1396 +LOONGARCH_INS_XVBITCLR_D = 1397 +LOONGARCH_INS_XVBITCLR_H = 1398 +LOONGARCH_INS_XVBITCLR_W = 1399 +LOONGARCH_INS_XVBITREVI_B = 1400 +LOONGARCH_INS_XVBITREVI_D = 1401 +LOONGARCH_INS_XVBITREVI_H = 1402 +LOONGARCH_INS_XVBITREVI_W = 1403 +LOONGARCH_INS_XVBITREV_B = 1404 +LOONGARCH_INS_XVBITREV_D = 1405 +LOONGARCH_INS_XVBITREV_H = 1406 +LOONGARCH_INS_XVBITREV_W = 1407 +LOONGARCH_INS_XVBITSELI_B = 1408 +LOONGARCH_INS_XVBITSEL_V = 1409 +LOONGARCH_INS_XVBITSETI_B = 1410 +LOONGARCH_INS_XVBITSETI_D = 1411 +LOONGARCH_INS_XVBITSETI_H = 1412 +LOONGARCH_INS_XVBITSETI_W = 1413 +LOONGARCH_INS_XVBITSET_B = 1414 +LOONGARCH_INS_XVBITSET_D = 1415 +LOONGARCH_INS_XVBITSET_H = 1416 +LOONGARCH_INS_XVBITSET_W = 1417 +LOONGARCH_INS_XVBSLL_V = 1418 +LOONGARCH_INS_XVBSRL_V = 1419 +LOONGARCH_INS_XVCLO_B = 1420 +LOONGARCH_INS_XVCLO_D = 1421 +LOONGARCH_INS_XVCLO_H = 1422 +LOONGARCH_INS_XVCLO_W = 1423 +LOONGARCH_INS_XVCLZ_B = 1424 +LOONGARCH_INS_XVCLZ_D = 1425 +LOONGARCH_INS_XVCLZ_H = 1426 +LOONGARCH_INS_XVCLZ_W = 1427 +LOONGARCH_INS_XVDIV_B = 1428 +LOONGARCH_INS_XVDIV_BU = 1429 +LOONGARCH_INS_XVDIV_D = 1430 +LOONGARCH_INS_XVDIV_DU = 1431 +LOONGARCH_INS_XVDIV_H = 1432 +LOONGARCH_INS_XVDIV_HU = 1433 +LOONGARCH_INS_XVDIV_W = 1434 +LOONGARCH_INS_XVDIV_WU = 1435 +LOONGARCH_INS_XVEXTH_DU_WU = 1436 +LOONGARCH_INS_XVEXTH_D_W = 1437 +LOONGARCH_INS_XVEXTH_HU_BU = 1438 +LOONGARCH_INS_XVEXTH_H_B = 1439 +LOONGARCH_INS_XVEXTH_QU_DU = 1440 +LOONGARCH_INS_XVEXTH_Q_D = 1441 +LOONGARCH_INS_XVEXTH_WU_HU = 1442 +LOONGARCH_INS_XVEXTH_W_H = 1443 +LOONGARCH_INS_XVEXTL_QU_DU = 1444 +LOONGARCH_INS_XVEXTL_Q_D = 1445 +LOONGARCH_INS_XVEXTRINS_B = 1446 +LOONGARCH_INS_XVEXTRINS_D = 1447 +LOONGARCH_INS_XVEXTRINS_H = 1448 +LOONGARCH_INS_XVEXTRINS_W = 1449 +LOONGARCH_INS_XVFADD_D = 1450 +LOONGARCH_INS_XVFADD_S = 1451 +LOONGARCH_INS_XVFCLASS_D = 1452 +LOONGARCH_INS_XVFCLASS_S = 1453 +LOONGARCH_INS_XVFCMP_CAF_D = 1454 +LOONGARCH_INS_XVFCMP_CAF_S = 1455 +LOONGARCH_INS_XVFCMP_CEQ_D = 1456 +LOONGARCH_INS_XVFCMP_CEQ_S = 1457 +LOONGARCH_INS_XVFCMP_CLE_D = 1458 +LOONGARCH_INS_XVFCMP_CLE_S = 1459 +LOONGARCH_INS_XVFCMP_CLT_D = 1460 +LOONGARCH_INS_XVFCMP_CLT_S = 1461 +LOONGARCH_INS_XVFCMP_CNE_D = 1462 +LOONGARCH_INS_XVFCMP_CNE_S = 1463 +LOONGARCH_INS_XVFCMP_COR_D = 1464 +LOONGARCH_INS_XVFCMP_COR_S = 1465 +LOONGARCH_INS_XVFCMP_CUEQ_D = 1466 +LOONGARCH_INS_XVFCMP_CUEQ_S = 1467 +LOONGARCH_INS_XVFCMP_CULE_D = 1468 +LOONGARCH_INS_XVFCMP_CULE_S = 1469 +LOONGARCH_INS_XVFCMP_CULT_D = 1470 +LOONGARCH_INS_XVFCMP_CULT_S = 1471 +LOONGARCH_INS_XVFCMP_CUNE_D = 1472 +LOONGARCH_INS_XVFCMP_CUNE_S = 1473 +LOONGARCH_INS_XVFCMP_CUN_D = 1474 +LOONGARCH_INS_XVFCMP_CUN_S = 1475 +LOONGARCH_INS_XVFCMP_SAF_D = 1476 +LOONGARCH_INS_XVFCMP_SAF_S = 1477 +LOONGARCH_INS_XVFCMP_SEQ_D = 1478 +LOONGARCH_INS_XVFCMP_SEQ_S = 1479 +LOONGARCH_INS_XVFCMP_SLE_D = 1480 +LOONGARCH_INS_XVFCMP_SLE_S = 1481 +LOONGARCH_INS_XVFCMP_SLT_D = 1482 +LOONGARCH_INS_XVFCMP_SLT_S = 1483 +LOONGARCH_INS_XVFCMP_SNE_D = 1484 +LOONGARCH_INS_XVFCMP_SNE_S = 1485 +LOONGARCH_INS_XVFCMP_SOR_D = 1486 +LOONGARCH_INS_XVFCMP_SOR_S = 1487 +LOONGARCH_INS_XVFCMP_SUEQ_D = 1488 +LOONGARCH_INS_XVFCMP_SUEQ_S = 1489 +LOONGARCH_INS_XVFCMP_SULE_D = 1490 +LOONGARCH_INS_XVFCMP_SULE_S = 1491 +LOONGARCH_INS_XVFCMP_SULT_D = 1492 +LOONGARCH_INS_XVFCMP_SULT_S = 1493 +LOONGARCH_INS_XVFCMP_SUNE_D = 1494 +LOONGARCH_INS_XVFCMP_SUNE_S = 1495 +LOONGARCH_INS_XVFCMP_SUN_D = 1496 +LOONGARCH_INS_XVFCMP_SUN_S = 1497 +LOONGARCH_INS_XVFCVTH_D_S = 1498 +LOONGARCH_INS_XVFCVTH_S_H = 1499 +LOONGARCH_INS_XVFCVTL_D_S = 1500 +LOONGARCH_INS_XVFCVTL_S_H = 1501 +LOONGARCH_INS_XVFCVT_H_S = 1502 +LOONGARCH_INS_XVFCVT_S_D = 1503 +LOONGARCH_INS_XVFDIV_D = 1504 +LOONGARCH_INS_XVFDIV_S = 1505 +LOONGARCH_INS_XVFFINTH_D_W = 1506 +LOONGARCH_INS_XVFFINTL_D_W = 1507 +LOONGARCH_INS_XVFFINT_D_L = 1508 +LOONGARCH_INS_XVFFINT_D_LU = 1509 +LOONGARCH_INS_XVFFINT_S_L = 1510 +LOONGARCH_INS_XVFFINT_S_W = 1511 +LOONGARCH_INS_XVFFINT_S_WU = 1512 +LOONGARCH_INS_XVFLOGB_D = 1513 +LOONGARCH_INS_XVFLOGB_S = 1514 +LOONGARCH_INS_XVFMADD_D = 1515 +LOONGARCH_INS_XVFMADD_S = 1516 +LOONGARCH_INS_XVFMAXA_D = 1517 +LOONGARCH_INS_XVFMAXA_S = 1518 +LOONGARCH_INS_XVFMAX_D = 1519 +LOONGARCH_INS_XVFMAX_S = 1520 +LOONGARCH_INS_XVFMINA_D = 1521 +LOONGARCH_INS_XVFMINA_S = 1522 +LOONGARCH_INS_XVFMIN_D = 1523 +LOONGARCH_INS_XVFMIN_S = 1524 +LOONGARCH_INS_XVFMSUB_D = 1525 +LOONGARCH_INS_XVFMSUB_S = 1526 +LOONGARCH_INS_XVFMUL_D = 1527 +LOONGARCH_INS_XVFMUL_S = 1528 +LOONGARCH_INS_XVFNMADD_D = 1529 +LOONGARCH_INS_XVFNMADD_S = 1530 +LOONGARCH_INS_XVFNMSUB_D = 1531 +LOONGARCH_INS_XVFNMSUB_S = 1532 +LOONGARCH_INS_XVFRECIPE_D = 1533 +LOONGARCH_INS_XVFRECIPE_S = 1534 +LOONGARCH_INS_XVFRECIP_D = 1535 +LOONGARCH_INS_XVFRECIP_S = 1536 +LOONGARCH_INS_XVFRINTRM_D = 1537 +LOONGARCH_INS_XVFRINTRM_S = 1538 +LOONGARCH_INS_XVFRINTRNE_D = 1539 +LOONGARCH_INS_XVFRINTRNE_S = 1540 +LOONGARCH_INS_XVFRINTRP_D = 1541 +LOONGARCH_INS_XVFRINTRP_S = 1542 +LOONGARCH_INS_XVFRINTRZ_D = 1543 +LOONGARCH_INS_XVFRINTRZ_S = 1544 +LOONGARCH_INS_XVFRINT_D = 1545 +LOONGARCH_INS_XVFRINT_S = 1546 +LOONGARCH_INS_XVFRSQRTE_D = 1547 +LOONGARCH_INS_XVFRSQRTE_S = 1548 +LOONGARCH_INS_XVFRSQRT_D = 1549 +LOONGARCH_INS_XVFRSQRT_S = 1550 +LOONGARCH_INS_XVFRSTPI_B = 1551 +LOONGARCH_INS_XVFRSTPI_H = 1552 +LOONGARCH_INS_XVFRSTP_B = 1553 +LOONGARCH_INS_XVFRSTP_H = 1554 +LOONGARCH_INS_XVFSQRT_D = 1555 +LOONGARCH_INS_XVFSQRT_S = 1556 +LOONGARCH_INS_XVFSUB_D = 1557 +LOONGARCH_INS_XVFSUB_S = 1558 +LOONGARCH_INS_XVFTINTH_L_S = 1559 +LOONGARCH_INS_XVFTINTL_L_S = 1560 +LOONGARCH_INS_XVFTINTRMH_L_S = 1561 +LOONGARCH_INS_XVFTINTRML_L_S = 1562 +LOONGARCH_INS_XVFTINTRM_L_D = 1563 +LOONGARCH_INS_XVFTINTRM_W_D = 1564 +LOONGARCH_INS_XVFTINTRM_W_S = 1565 +LOONGARCH_INS_XVFTINTRNEH_L_S = 1566 +LOONGARCH_INS_XVFTINTRNEL_L_S = 1567 +LOONGARCH_INS_XVFTINTRNE_L_D = 1568 +LOONGARCH_INS_XVFTINTRNE_W_D = 1569 +LOONGARCH_INS_XVFTINTRNE_W_S = 1570 +LOONGARCH_INS_XVFTINTRPH_L_S = 1571 +LOONGARCH_INS_XVFTINTRPL_L_S = 1572 +LOONGARCH_INS_XVFTINTRP_L_D = 1573 +LOONGARCH_INS_XVFTINTRP_W_D = 1574 +LOONGARCH_INS_XVFTINTRP_W_S = 1575 +LOONGARCH_INS_XVFTINTRZH_L_S = 1576 +LOONGARCH_INS_XVFTINTRZL_L_S = 1577 +LOONGARCH_INS_XVFTINTRZ_LU_D = 1578 +LOONGARCH_INS_XVFTINTRZ_L_D = 1579 +LOONGARCH_INS_XVFTINTRZ_WU_S = 1580 +LOONGARCH_INS_XVFTINTRZ_W_D = 1581 +LOONGARCH_INS_XVFTINTRZ_W_S = 1582 +LOONGARCH_INS_XVFTINT_LU_D = 1583 +LOONGARCH_INS_XVFTINT_L_D = 1584 +LOONGARCH_INS_XVFTINT_WU_S = 1585 +LOONGARCH_INS_XVFTINT_W_D = 1586 +LOONGARCH_INS_XVFTINT_W_S = 1587 +LOONGARCH_INS_XVHADDW_DU_WU = 1588 +LOONGARCH_INS_XVHADDW_D_W = 1589 +LOONGARCH_INS_XVHADDW_HU_BU = 1590 +LOONGARCH_INS_XVHADDW_H_B = 1591 +LOONGARCH_INS_XVHADDW_QU_DU = 1592 +LOONGARCH_INS_XVHADDW_Q_D = 1593 +LOONGARCH_INS_XVHADDW_WU_HU = 1594 +LOONGARCH_INS_XVHADDW_W_H = 1595 +LOONGARCH_INS_XVHSELI_D = 1596 +LOONGARCH_INS_XVHSUBW_DU_WU = 1597 +LOONGARCH_INS_XVHSUBW_D_W = 1598 +LOONGARCH_INS_XVHSUBW_HU_BU = 1599 +LOONGARCH_INS_XVHSUBW_H_B = 1600 +LOONGARCH_INS_XVHSUBW_QU_DU = 1601 +LOONGARCH_INS_XVHSUBW_Q_D = 1602 +LOONGARCH_INS_XVHSUBW_WU_HU = 1603 +LOONGARCH_INS_XVHSUBW_W_H = 1604 +LOONGARCH_INS_XVILVH_B = 1605 +LOONGARCH_INS_XVILVH_D = 1606 +LOONGARCH_INS_XVILVH_H = 1607 +LOONGARCH_INS_XVILVH_W = 1608 +LOONGARCH_INS_XVILVL_B = 1609 +LOONGARCH_INS_XVILVL_D = 1610 +LOONGARCH_INS_XVILVL_H = 1611 +LOONGARCH_INS_XVILVL_W = 1612 +LOONGARCH_INS_XVINSGR2VR_D = 1613 +LOONGARCH_INS_XVINSGR2VR_W = 1614 +LOONGARCH_INS_XVINSVE0_D = 1615 +LOONGARCH_INS_XVINSVE0_W = 1616 +LOONGARCH_INS_XVLD = 1617 +LOONGARCH_INS_XVLDI = 1618 +LOONGARCH_INS_XVLDREPL_B = 1619 +LOONGARCH_INS_XVLDREPL_D = 1620 +LOONGARCH_INS_XVLDREPL_H = 1621 +LOONGARCH_INS_XVLDREPL_W = 1622 +LOONGARCH_INS_XVLDX = 1623 +LOONGARCH_INS_XVMADDWEV_D_W = 1624 +LOONGARCH_INS_XVMADDWEV_D_WU = 1625 +LOONGARCH_INS_XVMADDWEV_D_WU_W = 1626 +LOONGARCH_INS_XVMADDWEV_H_B = 1627 +LOONGARCH_INS_XVMADDWEV_H_BU = 1628 +LOONGARCH_INS_XVMADDWEV_H_BU_B = 1629 +LOONGARCH_INS_XVMADDWEV_Q_D = 1630 +LOONGARCH_INS_XVMADDWEV_Q_DU = 1631 +LOONGARCH_INS_XVMADDWEV_Q_DU_D = 1632 +LOONGARCH_INS_XVMADDWEV_W_H = 1633 +LOONGARCH_INS_XVMADDWEV_W_HU = 1634 +LOONGARCH_INS_XVMADDWEV_W_HU_H = 1635 +LOONGARCH_INS_XVMADDWOD_D_W = 1636 +LOONGARCH_INS_XVMADDWOD_D_WU = 1637 +LOONGARCH_INS_XVMADDWOD_D_WU_W = 1638 +LOONGARCH_INS_XVMADDWOD_H_B = 1639 +LOONGARCH_INS_XVMADDWOD_H_BU = 1640 +LOONGARCH_INS_XVMADDWOD_H_BU_B = 1641 +LOONGARCH_INS_XVMADDWOD_Q_D = 1642 +LOONGARCH_INS_XVMADDWOD_Q_DU = 1643 +LOONGARCH_INS_XVMADDWOD_Q_DU_D = 1644 +LOONGARCH_INS_XVMADDWOD_W_H = 1645 +LOONGARCH_INS_XVMADDWOD_W_HU = 1646 +LOONGARCH_INS_XVMADDWOD_W_HU_H = 1647 +LOONGARCH_INS_XVMADD_B = 1648 +LOONGARCH_INS_XVMADD_D = 1649 +LOONGARCH_INS_XVMADD_H = 1650 +LOONGARCH_INS_XVMADD_W = 1651 +LOONGARCH_INS_XVMAXI_B = 1652 +LOONGARCH_INS_XVMAXI_BU = 1653 +LOONGARCH_INS_XVMAXI_D = 1654 +LOONGARCH_INS_XVMAXI_DU = 1655 +LOONGARCH_INS_XVMAXI_H = 1656 +LOONGARCH_INS_XVMAXI_HU = 1657 +LOONGARCH_INS_XVMAXI_W = 1658 +LOONGARCH_INS_XVMAXI_WU = 1659 +LOONGARCH_INS_XVMAX_B = 1660 +LOONGARCH_INS_XVMAX_BU = 1661 +LOONGARCH_INS_XVMAX_D = 1662 +LOONGARCH_INS_XVMAX_DU = 1663 +LOONGARCH_INS_XVMAX_H = 1664 +LOONGARCH_INS_XVMAX_HU = 1665 +LOONGARCH_INS_XVMAX_W = 1666 +LOONGARCH_INS_XVMAX_WU = 1667 +LOONGARCH_INS_XVMINI_B = 1668 +LOONGARCH_INS_XVMINI_BU = 1669 +LOONGARCH_INS_XVMINI_D = 1670 +LOONGARCH_INS_XVMINI_DU = 1671 +LOONGARCH_INS_XVMINI_H = 1672 +LOONGARCH_INS_XVMINI_HU = 1673 +LOONGARCH_INS_XVMINI_W = 1674 +LOONGARCH_INS_XVMINI_WU = 1675 +LOONGARCH_INS_XVMIN_B = 1676 +LOONGARCH_INS_XVMIN_BU = 1677 +LOONGARCH_INS_XVMIN_D = 1678 +LOONGARCH_INS_XVMIN_DU = 1679 +LOONGARCH_INS_XVMIN_H = 1680 +LOONGARCH_INS_XVMIN_HU = 1681 +LOONGARCH_INS_XVMIN_W = 1682 +LOONGARCH_INS_XVMIN_WU = 1683 +LOONGARCH_INS_XVMOD_B = 1684 +LOONGARCH_INS_XVMOD_BU = 1685 +LOONGARCH_INS_XVMOD_D = 1686 +LOONGARCH_INS_XVMOD_DU = 1687 +LOONGARCH_INS_XVMOD_H = 1688 +LOONGARCH_INS_XVMOD_HU = 1689 +LOONGARCH_INS_XVMOD_W = 1690 +LOONGARCH_INS_XVMOD_WU = 1691 +LOONGARCH_INS_XVMSKGEZ_B = 1692 +LOONGARCH_INS_XVMSKLTZ_B = 1693 +LOONGARCH_INS_XVMSKLTZ_D = 1694 +LOONGARCH_INS_XVMSKLTZ_H = 1695 +LOONGARCH_INS_XVMSKLTZ_W = 1696 +LOONGARCH_INS_XVMSKNZ_B = 1697 +LOONGARCH_INS_XVMSUB_B = 1698 +LOONGARCH_INS_XVMSUB_D = 1699 +LOONGARCH_INS_XVMSUB_H = 1700 +LOONGARCH_INS_XVMSUB_W = 1701 +LOONGARCH_INS_XVMUH_B = 1702 +LOONGARCH_INS_XVMUH_BU = 1703 +LOONGARCH_INS_XVMUH_D = 1704 +LOONGARCH_INS_XVMUH_DU = 1705 +LOONGARCH_INS_XVMUH_H = 1706 +LOONGARCH_INS_XVMUH_HU = 1707 +LOONGARCH_INS_XVMUH_W = 1708 +LOONGARCH_INS_XVMUH_WU = 1709 +LOONGARCH_INS_XVMULWEV_D_W = 1710 +LOONGARCH_INS_XVMULWEV_D_WU = 1711 +LOONGARCH_INS_XVMULWEV_D_WU_W = 1712 +LOONGARCH_INS_XVMULWEV_H_B = 1713 +LOONGARCH_INS_XVMULWEV_H_BU = 1714 +LOONGARCH_INS_XVMULWEV_H_BU_B = 1715 +LOONGARCH_INS_XVMULWEV_Q_D = 1716 +LOONGARCH_INS_XVMULWEV_Q_DU = 1717 +LOONGARCH_INS_XVMULWEV_Q_DU_D = 1718 +LOONGARCH_INS_XVMULWEV_W_H = 1719 +LOONGARCH_INS_XVMULWEV_W_HU = 1720 +LOONGARCH_INS_XVMULWEV_W_HU_H = 1721 +LOONGARCH_INS_XVMULWOD_D_W = 1722 +LOONGARCH_INS_XVMULWOD_D_WU = 1723 +LOONGARCH_INS_XVMULWOD_D_WU_W = 1724 +LOONGARCH_INS_XVMULWOD_H_B = 1725 +LOONGARCH_INS_XVMULWOD_H_BU = 1726 +LOONGARCH_INS_XVMULWOD_H_BU_B = 1727 +LOONGARCH_INS_XVMULWOD_Q_D = 1728 +LOONGARCH_INS_XVMULWOD_Q_DU = 1729 +LOONGARCH_INS_XVMULWOD_Q_DU_D = 1730 +LOONGARCH_INS_XVMULWOD_W_H = 1731 +LOONGARCH_INS_XVMULWOD_W_HU = 1732 +LOONGARCH_INS_XVMULWOD_W_HU_H = 1733 +LOONGARCH_INS_XVMUL_B = 1734 +LOONGARCH_INS_XVMUL_D = 1735 +LOONGARCH_INS_XVMUL_H = 1736 +LOONGARCH_INS_XVMUL_W = 1737 +LOONGARCH_INS_XVNEG_B = 1738 +LOONGARCH_INS_XVNEG_D = 1739 +LOONGARCH_INS_XVNEG_H = 1740 +LOONGARCH_INS_XVNEG_W = 1741 +LOONGARCH_INS_XVNORI_B = 1742 +LOONGARCH_INS_XVNOR_V = 1743 +LOONGARCH_INS_XVORI_B = 1744 +LOONGARCH_INS_XVORN_V = 1745 +LOONGARCH_INS_XVOR_V = 1746 +LOONGARCH_INS_XVPACKEV_B = 1747 +LOONGARCH_INS_XVPACKEV_D = 1748 +LOONGARCH_INS_XVPACKEV_H = 1749 +LOONGARCH_INS_XVPACKEV_W = 1750 +LOONGARCH_INS_XVPACKOD_B = 1751 +LOONGARCH_INS_XVPACKOD_D = 1752 +LOONGARCH_INS_XVPACKOD_H = 1753 +LOONGARCH_INS_XVPACKOD_W = 1754 +LOONGARCH_INS_XVPCNT_B = 1755 +LOONGARCH_INS_XVPCNT_D = 1756 +LOONGARCH_INS_XVPCNT_H = 1757 +LOONGARCH_INS_XVPCNT_W = 1758 +LOONGARCH_INS_XVPERMI_D = 1759 +LOONGARCH_INS_XVPERMI_Q = 1760 +LOONGARCH_INS_XVPERMI_W = 1761 +LOONGARCH_INS_XVPERM_W = 1762 +LOONGARCH_INS_XVPICKEV_B = 1763 +LOONGARCH_INS_XVPICKEV_D = 1764 +LOONGARCH_INS_XVPICKEV_H = 1765 +LOONGARCH_INS_XVPICKEV_W = 1766 +LOONGARCH_INS_XVPICKOD_B = 1767 +LOONGARCH_INS_XVPICKOD_D = 1768 +LOONGARCH_INS_XVPICKOD_H = 1769 +LOONGARCH_INS_XVPICKOD_W = 1770 +LOONGARCH_INS_XVPICKVE2GR_D = 1771 +LOONGARCH_INS_XVPICKVE2GR_DU = 1772 +LOONGARCH_INS_XVPICKVE2GR_W = 1773 +LOONGARCH_INS_XVPICKVE2GR_WU = 1774 +LOONGARCH_INS_XVPICKVE_D = 1775 +LOONGARCH_INS_XVPICKVE_W = 1776 +LOONGARCH_INS_XVREPL128VEI_B = 1777 +LOONGARCH_INS_XVREPL128VEI_D = 1778 +LOONGARCH_INS_XVREPL128VEI_H = 1779 +LOONGARCH_INS_XVREPL128VEI_W = 1780 +LOONGARCH_INS_XVREPLGR2VR_B = 1781 +LOONGARCH_INS_XVREPLGR2VR_D = 1782 +LOONGARCH_INS_XVREPLGR2VR_H = 1783 +LOONGARCH_INS_XVREPLGR2VR_W = 1784 +LOONGARCH_INS_XVREPLVE0_B = 1785 +LOONGARCH_INS_XVREPLVE0_D = 1786 +LOONGARCH_INS_XVREPLVE0_H = 1787 +LOONGARCH_INS_XVREPLVE0_Q = 1788 +LOONGARCH_INS_XVREPLVE0_W = 1789 +LOONGARCH_INS_XVREPLVE_B = 1790 +LOONGARCH_INS_XVREPLVE_D = 1791 +LOONGARCH_INS_XVREPLVE_H = 1792 +LOONGARCH_INS_XVREPLVE_W = 1793 +LOONGARCH_INS_XVROTRI_B = 1794 +LOONGARCH_INS_XVROTRI_D = 1795 +LOONGARCH_INS_XVROTRI_H = 1796 +LOONGARCH_INS_XVROTRI_W = 1797 +LOONGARCH_INS_XVROTR_B = 1798 +LOONGARCH_INS_XVROTR_D = 1799 +LOONGARCH_INS_XVROTR_H = 1800 +LOONGARCH_INS_XVROTR_W = 1801 +LOONGARCH_INS_XVSADD_B = 1802 +LOONGARCH_INS_XVSADD_BU = 1803 +LOONGARCH_INS_XVSADD_D = 1804 +LOONGARCH_INS_XVSADD_DU = 1805 +LOONGARCH_INS_XVSADD_H = 1806 +LOONGARCH_INS_XVSADD_HU = 1807 +LOONGARCH_INS_XVSADD_W = 1808 +LOONGARCH_INS_XVSADD_WU = 1809 +LOONGARCH_INS_XVSAT_B = 1810 +LOONGARCH_INS_XVSAT_BU = 1811 +LOONGARCH_INS_XVSAT_D = 1812 +LOONGARCH_INS_XVSAT_DU = 1813 +LOONGARCH_INS_XVSAT_H = 1814 +LOONGARCH_INS_XVSAT_HU = 1815 +LOONGARCH_INS_XVSAT_W = 1816 +LOONGARCH_INS_XVSAT_WU = 1817 +LOONGARCH_INS_XVSEQI_B = 1818 +LOONGARCH_INS_XVSEQI_D = 1819 +LOONGARCH_INS_XVSEQI_H = 1820 +LOONGARCH_INS_XVSEQI_W = 1821 +LOONGARCH_INS_XVSEQ_B = 1822 +LOONGARCH_INS_XVSEQ_D = 1823 +LOONGARCH_INS_XVSEQ_H = 1824 +LOONGARCH_INS_XVSEQ_W = 1825 +LOONGARCH_INS_XVSETALLNEZ_B = 1826 +LOONGARCH_INS_XVSETALLNEZ_D = 1827 +LOONGARCH_INS_XVSETALLNEZ_H = 1828 +LOONGARCH_INS_XVSETALLNEZ_W = 1829 +LOONGARCH_INS_XVSETANYEQZ_B = 1830 +LOONGARCH_INS_XVSETANYEQZ_D = 1831 +LOONGARCH_INS_XVSETANYEQZ_H = 1832 +LOONGARCH_INS_XVSETANYEQZ_W = 1833 +LOONGARCH_INS_XVSETEQZ_V = 1834 +LOONGARCH_INS_XVSETNEZ_V = 1835 +LOONGARCH_INS_XVSHUF4I_B = 1836 +LOONGARCH_INS_XVSHUF4I_D = 1837 +LOONGARCH_INS_XVSHUF4I_H = 1838 +LOONGARCH_INS_XVSHUF4I_W = 1839 +LOONGARCH_INS_XVSHUF_B = 1840 +LOONGARCH_INS_XVSHUF_D = 1841 +LOONGARCH_INS_XVSHUF_H = 1842 +LOONGARCH_INS_XVSHUF_W = 1843 +LOONGARCH_INS_XVSIGNCOV_B = 1844 +LOONGARCH_INS_XVSIGNCOV_D = 1845 +LOONGARCH_INS_XVSIGNCOV_H = 1846 +LOONGARCH_INS_XVSIGNCOV_W = 1847 +LOONGARCH_INS_XVSLEI_B = 1848 +LOONGARCH_INS_XVSLEI_BU = 1849 +LOONGARCH_INS_XVSLEI_D = 1850 +LOONGARCH_INS_XVSLEI_DU = 1851 +LOONGARCH_INS_XVSLEI_H = 1852 +LOONGARCH_INS_XVSLEI_HU = 1853 +LOONGARCH_INS_XVSLEI_W = 1854 +LOONGARCH_INS_XVSLEI_WU = 1855 +LOONGARCH_INS_XVSLE_B = 1856 +LOONGARCH_INS_XVSLE_BU = 1857 +LOONGARCH_INS_XVSLE_D = 1858 +LOONGARCH_INS_XVSLE_DU = 1859 +LOONGARCH_INS_XVSLE_H = 1860 +LOONGARCH_INS_XVSLE_HU = 1861 +LOONGARCH_INS_XVSLE_W = 1862 +LOONGARCH_INS_XVSLE_WU = 1863 +LOONGARCH_INS_XVSLLI_B = 1864 +LOONGARCH_INS_XVSLLI_D = 1865 +LOONGARCH_INS_XVSLLI_H = 1866 +LOONGARCH_INS_XVSLLI_W = 1867 +LOONGARCH_INS_XVSLLWIL_DU_WU = 1868 +LOONGARCH_INS_XVSLLWIL_D_W = 1869 +LOONGARCH_INS_XVSLLWIL_HU_BU = 1870 +LOONGARCH_INS_XVSLLWIL_H_B = 1871 +LOONGARCH_INS_XVSLLWIL_WU_HU = 1872 +LOONGARCH_INS_XVSLLWIL_W_H = 1873 +LOONGARCH_INS_XVSLL_B = 1874 +LOONGARCH_INS_XVSLL_D = 1875 +LOONGARCH_INS_XVSLL_H = 1876 +LOONGARCH_INS_XVSLL_W = 1877 +LOONGARCH_INS_XVSLTI_B = 1878 +LOONGARCH_INS_XVSLTI_BU = 1879 +LOONGARCH_INS_XVSLTI_D = 1880 +LOONGARCH_INS_XVSLTI_DU = 1881 +LOONGARCH_INS_XVSLTI_H = 1882 +LOONGARCH_INS_XVSLTI_HU = 1883 +LOONGARCH_INS_XVSLTI_W = 1884 +LOONGARCH_INS_XVSLTI_WU = 1885 +LOONGARCH_INS_XVSLT_B = 1886 +LOONGARCH_INS_XVSLT_BU = 1887 +LOONGARCH_INS_XVSLT_D = 1888 +LOONGARCH_INS_XVSLT_DU = 1889 +LOONGARCH_INS_XVSLT_H = 1890 +LOONGARCH_INS_XVSLT_HU = 1891 +LOONGARCH_INS_XVSLT_W = 1892 +LOONGARCH_INS_XVSLT_WU = 1893 +LOONGARCH_INS_XVSRAI_B = 1894 +LOONGARCH_INS_XVSRAI_D = 1895 +LOONGARCH_INS_XVSRAI_H = 1896 +LOONGARCH_INS_XVSRAI_W = 1897 +LOONGARCH_INS_XVSRANI_B_H = 1898 +LOONGARCH_INS_XVSRANI_D_Q = 1899 +LOONGARCH_INS_XVSRANI_H_W = 1900 +LOONGARCH_INS_XVSRANI_W_D = 1901 +LOONGARCH_INS_XVSRAN_B_H = 1902 +LOONGARCH_INS_XVSRAN_H_W = 1903 +LOONGARCH_INS_XVSRAN_W_D = 1904 +LOONGARCH_INS_XVSRARI_B = 1905 +LOONGARCH_INS_XVSRARI_D = 1906 +LOONGARCH_INS_XVSRARI_H = 1907 +LOONGARCH_INS_XVSRARI_W = 1908 +LOONGARCH_INS_XVSRARNI_B_H = 1909 +LOONGARCH_INS_XVSRARNI_D_Q = 1910 +LOONGARCH_INS_XVSRARNI_H_W = 1911 +LOONGARCH_INS_XVSRARNI_W_D = 1912 +LOONGARCH_INS_XVSRARN_B_H = 1913 +LOONGARCH_INS_XVSRARN_H_W = 1914 +LOONGARCH_INS_XVSRARN_W_D = 1915 +LOONGARCH_INS_XVSRAR_B = 1916 +LOONGARCH_INS_XVSRAR_D = 1917 +LOONGARCH_INS_XVSRAR_H = 1918 +LOONGARCH_INS_XVSRAR_W = 1919 +LOONGARCH_INS_XVSRA_B = 1920 +LOONGARCH_INS_XVSRA_D = 1921 +LOONGARCH_INS_XVSRA_H = 1922 +LOONGARCH_INS_XVSRA_W = 1923 +LOONGARCH_INS_XVSRLI_B = 1924 +LOONGARCH_INS_XVSRLI_D = 1925 +LOONGARCH_INS_XVSRLI_H = 1926 +LOONGARCH_INS_XVSRLI_W = 1927 +LOONGARCH_INS_XVSRLNI_B_H = 1928 +LOONGARCH_INS_XVSRLNI_D_Q = 1929 +LOONGARCH_INS_XVSRLNI_H_W = 1930 +LOONGARCH_INS_XVSRLNI_W_D = 1931 +LOONGARCH_INS_XVSRLN_B_H = 1932 +LOONGARCH_INS_XVSRLN_H_W = 1933 +LOONGARCH_INS_XVSRLN_W_D = 1934 +LOONGARCH_INS_XVSRLRI_B = 1935 +LOONGARCH_INS_XVSRLRI_D = 1936 +LOONGARCH_INS_XVSRLRI_H = 1937 +LOONGARCH_INS_XVSRLRI_W = 1938 +LOONGARCH_INS_XVSRLRNI_B_H = 1939 +LOONGARCH_INS_XVSRLRNI_D_Q = 1940 +LOONGARCH_INS_XVSRLRNI_H_W = 1941 +LOONGARCH_INS_XVSRLRNI_W_D = 1942 +LOONGARCH_INS_XVSRLRN_B_H = 1943 +LOONGARCH_INS_XVSRLRN_H_W = 1944 +LOONGARCH_INS_XVSRLRN_W_D = 1945 +LOONGARCH_INS_XVSRLR_B = 1946 +LOONGARCH_INS_XVSRLR_D = 1947 +LOONGARCH_INS_XVSRLR_H = 1948 +LOONGARCH_INS_XVSRLR_W = 1949 +LOONGARCH_INS_XVSRL_B = 1950 +LOONGARCH_INS_XVSRL_D = 1951 +LOONGARCH_INS_XVSRL_H = 1952 +LOONGARCH_INS_XVSRL_W = 1953 +LOONGARCH_INS_XVSSRANI_BU_H = 1954 +LOONGARCH_INS_XVSSRANI_B_H = 1955 +LOONGARCH_INS_XVSSRANI_DU_Q = 1956 +LOONGARCH_INS_XVSSRANI_D_Q = 1957 +LOONGARCH_INS_XVSSRANI_HU_W = 1958 +LOONGARCH_INS_XVSSRANI_H_W = 1959 +LOONGARCH_INS_XVSSRANI_WU_D = 1960 +LOONGARCH_INS_XVSSRANI_W_D = 1961 +LOONGARCH_INS_XVSSRAN_BU_H = 1962 +LOONGARCH_INS_XVSSRAN_B_H = 1963 +LOONGARCH_INS_XVSSRAN_HU_W = 1964 +LOONGARCH_INS_XVSSRAN_H_W = 1965 +LOONGARCH_INS_XVSSRAN_WU_D = 1966 +LOONGARCH_INS_XVSSRAN_W_D = 1967 +LOONGARCH_INS_XVSSRARNI_BU_H = 1968 +LOONGARCH_INS_XVSSRARNI_B_H = 1969 +LOONGARCH_INS_XVSSRARNI_DU_Q = 1970 +LOONGARCH_INS_XVSSRARNI_D_Q = 1971 +LOONGARCH_INS_XVSSRARNI_HU_W = 1972 +LOONGARCH_INS_XVSSRARNI_H_W = 1973 +LOONGARCH_INS_XVSSRARNI_WU_D = 1974 +LOONGARCH_INS_XVSSRARNI_W_D = 1975 +LOONGARCH_INS_XVSSRARN_BU_H = 1976 +LOONGARCH_INS_XVSSRARN_B_H = 1977 +LOONGARCH_INS_XVSSRARN_HU_W = 1978 +LOONGARCH_INS_XVSSRARN_H_W = 1979 +LOONGARCH_INS_XVSSRARN_WU_D = 1980 +LOONGARCH_INS_XVSSRARN_W_D = 1981 +LOONGARCH_INS_XVSSRLNI_BU_H = 1982 +LOONGARCH_INS_XVSSRLNI_B_H = 1983 +LOONGARCH_INS_XVSSRLNI_DU_Q = 1984 +LOONGARCH_INS_XVSSRLNI_D_Q = 1985 +LOONGARCH_INS_XVSSRLNI_HU_W = 1986 +LOONGARCH_INS_XVSSRLNI_H_W = 1987 +LOONGARCH_INS_XVSSRLNI_WU_D = 1988 +LOONGARCH_INS_XVSSRLNI_W_D = 1989 +LOONGARCH_INS_XVSSRLN_BU_H = 1990 +LOONGARCH_INS_XVSSRLN_B_H = 1991 +LOONGARCH_INS_XVSSRLN_HU_W = 1992 +LOONGARCH_INS_XVSSRLN_H_W = 1993 +LOONGARCH_INS_XVSSRLN_WU_D = 1994 +LOONGARCH_INS_XVSSRLN_W_D = 1995 +LOONGARCH_INS_XVSSRLRNI_BU_H = 1996 +LOONGARCH_INS_XVSSRLRNI_B_H = 1997 +LOONGARCH_INS_XVSSRLRNI_DU_Q = 1998 +LOONGARCH_INS_XVSSRLRNI_D_Q = 1999 +LOONGARCH_INS_XVSSRLRNI_HU_W = 2000 +LOONGARCH_INS_XVSSRLRNI_H_W = 2001 +LOONGARCH_INS_XVSSRLRNI_WU_D = 2002 +LOONGARCH_INS_XVSSRLRNI_W_D = 2003 +LOONGARCH_INS_XVSSRLRN_BU_H = 2004 +LOONGARCH_INS_XVSSRLRN_B_H = 2005 +LOONGARCH_INS_XVSSRLRN_HU_W = 2006 +LOONGARCH_INS_XVSSRLRN_H_W = 2007 +LOONGARCH_INS_XVSSRLRN_WU_D = 2008 +LOONGARCH_INS_XVSSRLRN_W_D = 2009 +LOONGARCH_INS_XVSSUB_B = 2010 +LOONGARCH_INS_XVSSUB_BU = 2011 +LOONGARCH_INS_XVSSUB_D = 2012 +LOONGARCH_INS_XVSSUB_DU = 2013 +LOONGARCH_INS_XVSSUB_H = 2014 +LOONGARCH_INS_XVSSUB_HU = 2015 +LOONGARCH_INS_XVSSUB_W = 2016 +LOONGARCH_INS_XVSSUB_WU = 2017 +LOONGARCH_INS_XVST = 2018 +LOONGARCH_INS_XVSTELM_B = 2019 +LOONGARCH_INS_XVSTELM_D = 2020 +LOONGARCH_INS_XVSTELM_H = 2021 +LOONGARCH_INS_XVSTELM_W = 2022 +LOONGARCH_INS_XVSTX = 2023 +LOONGARCH_INS_XVSUBI_BU = 2024 +LOONGARCH_INS_XVSUBI_DU = 2025 +LOONGARCH_INS_XVSUBI_HU = 2026 +LOONGARCH_INS_XVSUBI_WU = 2027 +LOONGARCH_INS_XVSUBWEV_D_W = 2028 +LOONGARCH_INS_XVSUBWEV_D_WU = 2029 +LOONGARCH_INS_XVSUBWEV_H_B = 2030 +LOONGARCH_INS_XVSUBWEV_H_BU = 2031 +LOONGARCH_INS_XVSUBWEV_Q_D = 2032 +LOONGARCH_INS_XVSUBWEV_Q_DU = 2033 +LOONGARCH_INS_XVSUBWEV_W_H = 2034 +LOONGARCH_INS_XVSUBWEV_W_HU = 2035 +LOONGARCH_INS_XVSUBWOD_D_W = 2036 +LOONGARCH_INS_XVSUBWOD_D_WU = 2037 +LOONGARCH_INS_XVSUBWOD_H_B = 2038 +LOONGARCH_INS_XVSUBWOD_H_BU = 2039 +LOONGARCH_INS_XVSUBWOD_Q_D = 2040 +LOONGARCH_INS_XVSUBWOD_Q_DU = 2041 +LOONGARCH_INS_XVSUBWOD_W_H = 2042 +LOONGARCH_INS_XVSUBWOD_W_HU = 2043 +LOONGARCH_INS_XVSUB_B = 2044 +LOONGARCH_INS_XVSUB_D = 2045 +LOONGARCH_INS_XVSUB_H = 2046 +LOONGARCH_INS_XVSUB_Q = 2047 +LOONGARCH_INS_XVSUB_W = 2048 +LOONGARCH_INS_XVXORI_B = 2049 +LOONGARCH_INS_XVXOR_V = 2050 +LOONGARCH_INS_ENDING = 2051 + +# Group of LOONGARCH instructions + +LOONGARCH_GRP_INVALID = 0 +LOONGARCH_GRP_JUMP = 1 +LOONGARCH_GRP_CALL = 2 +LOONGARCH_GRP_RET = 3 +LOONGARCH_GRP_INT = 4 +LOONGARCH_GRP_IRET = 5 +LOONGARCH_GRP_PRIVILEGE = 6 +LOONGARCH_GRP_BRANCH_RELATIVE = 7 +LOONGARCH_FEATURE_ISLA64 = 128 +LOONGARCH_FEATURE_ISLA32 = 129 +LOONGARCH_FEATURE_HASLAGLOBALWITHPCREL = 130 +LOONGARCH_FEATURE_HASLAGLOBALWITHABS = 131 +LOONGARCH_FEATURE_HASLALOCALWITHABS = 132 +LOONGARCH_GRP_ENDING = 133 diff --git a/bindings/python/capstone/ppc.py b/bindings/python/capstone/ppc.py index d739408090..b30a140c53 100644 --- a/bindings/python/capstone/ppc.py +++ b/bindings/python/capstone/ppc.py @@ -60,5 +60,5 @@ class CsPpc(ctypes.Structure): ) def get_arch_info(a): - return (a.bc, a.update_cr0, copy_ctypes_list(a.operands[:a.op_count])) + return (a.bc, a.update_cr0, a.format, copy_ctypes_list(a.operands[:a.op_count])) diff --git a/bindings/python/capstone/ppc_const.py b/bindings/python/capstone/ppc_const.py index 71fb0671e0..2feba7cc95 100644 --- a/bindings/python/capstone/ppc_const.py +++ b/bindings/python/capstone/ppc_const.py @@ -606,2337 +606,2338 @@ PPC_REG_G8p14 = 530 PPC_REG_G8p15 = 531 PPC_REG_ENDING = 532 -PPC_INS_INVALID = 533 -PPC_INS_CLRLSLDI = 534 -PPC_INS_CLRLSLWI = 535 -PPC_INS_CLRRDI = 536 -PPC_INS_CLRRWI = 537 -PPC_INS_DCBFL = 538 -PPC_INS_DCBFLP = 539 -PPC_INS_DCBFPS = 540 -PPC_INS_DCBF = 541 -PPC_INS_DCBSTPS = 542 -PPC_INS_DCBTCT = 543 -PPC_INS_DCBTDS = 544 -PPC_INS_DCBTSTCT = 545 -PPC_INS_DCBTSTDS = 546 -PPC_INS_DCBTSTT = 547 -PPC_INS_DCBTST = 548 -PPC_INS_DCBTT = 549 -PPC_INS_DCBT = 550 -PPC_INS_EXTLDI = 551 -PPC_INS_EXTLWI = 552 -PPC_INS_EXTRDI = 553 -PPC_INS_EXTRWI = 554 -PPC_INS_INSLWI = 555 -PPC_INS_INSRDI = 556 -PPC_INS_INSRWI = 557 -PPC_INS_LA = 558 -PPC_INS_RLWIMI = 559 -PPC_INS_RLWINM = 560 -PPC_INS_RLWNM = 561 -PPC_INS_ROTRDI = 562 -PPC_INS_ROTRWI = 563 -PPC_INS_SLDI = 564 -PPC_INS_SLWI = 565 -PPC_INS_SRDI = 566 -PPC_INS_SRWI = 567 -PPC_INS_SUBI = 568 -PPC_INS_SUBIC = 569 -PPC_INS_SUBIS = 570 -PPC_INS_SUBPCIS = 571 -PPC_INS_ADD = 572 -PPC_INS_ADDO = 573 -PPC_INS_ADDC = 574 -PPC_INS_ADDCO = 575 -PPC_INS_ADDE = 576 -PPC_INS_ADDEO = 577 -PPC_INS_ADDEX = 578 -PPC_INS_ADDI = 579 -PPC_INS_ADDIC = 580 -PPC_INS_ADDIS = 581 -PPC_INS_ADDME = 582 -PPC_INS_ADDMEO = 583 -PPC_INS_ADDPCIS = 584 -PPC_INS_ADDZE = 585 -PPC_INS_ADDZEO = 586 -PPC_INS_AND = 587 -PPC_INS_ANDC = 588 -PPC_INS_ANDIS = 589 -PPC_INS_ANDI = 590 -PPC_INS_ATTN = 591 -PPC_INS_B = 592 -PPC_INS_BA = 593 -PPC_INS_BCDADD = 594 -PPC_INS_BCDCFN = 595 -PPC_INS_BCDCFSQ = 596 -PPC_INS_BCDCFZ = 597 -PPC_INS_BCDCPSGN = 598 -PPC_INS_BCDCTN = 599 -PPC_INS_BCDCTSQ = 600 -PPC_INS_BCDCTZ = 601 -PPC_INS_BCDSETSGN = 602 -PPC_INS_BCDSR = 603 -PPC_INS_BCDSUB = 604 -PPC_INS_BCDS = 605 -PPC_INS_BCDTRUNC = 606 -PPC_INS_BCDUS = 607 -PPC_INS_BCDUTRUNC = 608 -PPC_INS_BCTR = 609 -PPC_INS_BCTRL = 610 -PPC_INS_BL = 611 -PPC_INS_BLA = 612 -PPC_INS_BLR = 613 -PPC_INS_BLRL = 614 -PPC_INS_BPERMD = 615 -PPC_INS_BRD = 616 -PPC_INS_BRH = 617 -PPC_INS_BRINC = 618 -PPC_INS_BRW = 619 -PPC_INS_CFUGED = 620 -PPC_INS_CLRBHRB = 621 -PPC_INS_CMPB = 622 -PPC_INS_CMPD = 623 -PPC_INS_CMPDI = 624 -PPC_INS_CMPEQB = 625 -PPC_INS_CMPLD = 626 -PPC_INS_CMPLDI = 627 -PPC_INS_CMPLW = 628 -PPC_INS_CMPLWI = 629 -PPC_INS_CMPRB = 630 -PPC_INS_CMPW = 631 -PPC_INS_CMPWI = 632 -PPC_INS_CNTLZD = 633 -PPC_INS_CNTLZDM = 634 -PPC_INS_CNTLZW = 635 -PPC_INS_CNTTZD = 636 -PPC_INS_CNTTZDM = 637 -PPC_INS_CNTTZW = 638 -PPC_INS_CPABORT = 639 -PPC_INS_COPY = 640 -PPC_INS_PASTE = 641 -PPC_INS_CRAND = 642 -PPC_INS_CRANDC = 643 -PPC_INS_CREQV = 644 -PPC_INS_CRNAND = 645 -PPC_INS_CRNOR = 646 -PPC_INS_CROR = 647 -PPC_INS_CRORC = 648 -PPC_INS_CRXOR = 649 -PPC_INS_DARN = 650 -PPC_INS_DCBA = 651 -PPC_INS_DCBFEP = 652 -PPC_INS_DCBI = 653 -PPC_INS_DCBST = 654 -PPC_INS_DCBSTEP = 655 -PPC_INS_DCBTEP = 656 -PPC_INS_DCBTSTEP = 657 -PPC_INS_DCBZ = 658 -PPC_INS_DCBZEP = 659 -PPC_INS_DCBZL = 660 -PPC_INS_DCBZLEP = 661 -PPC_INS_DCCCI = 662 -PPC_INS_DIVD = 663 -PPC_INS_DIVDE = 664 -PPC_INS_DIVDEO = 665 -PPC_INS_DIVDEU = 666 -PPC_INS_DIVDEUO = 667 -PPC_INS_DIVDO = 668 -PPC_INS_DIVDU = 669 -PPC_INS_DIVDUO = 670 -PPC_INS_DIVW = 671 -PPC_INS_DIVWE = 672 -PPC_INS_DIVWEO = 673 -PPC_INS_DIVWEU = 674 -PPC_INS_DIVWEUO = 675 -PPC_INS_DIVWO = 676 -PPC_INS_DIVWU = 677 -PPC_INS_DIVWUO = 678 -PPC_INS_DMMR = 679 -PPC_INS_DMSETDMRZ = 680 -PPC_INS_DMXOR = 681 -PPC_INS_DMXXEXTFDMR256 = 682 -PPC_INS_DMXXEXTFDMR512 = 683 -PPC_INS_DMXXINSTFDMR256 = 684 -PPC_INS_DMXXINSTFDMR512 = 685 -PPC_INS_DSS = 686 -PPC_INS_DSSALL = 687 -PPC_INS_DST = 688 -PPC_INS_DSTST = 689 -PPC_INS_DSTSTT = 690 -PPC_INS_DSTT = 691 -PPC_INS_EFDABS = 692 -PPC_INS_EFDADD = 693 -PPC_INS_EFDCFS = 694 -PPC_INS_EFDCFSF = 695 -PPC_INS_EFDCFSI = 696 -PPC_INS_EFDCFSID = 697 -PPC_INS_EFDCFUF = 698 -PPC_INS_EFDCFUI = 699 -PPC_INS_EFDCFUID = 700 -PPC_INS_EFDCMPEQ = 701 -PPC_INS_EFDCMPGT = 702 -PPC_INS_EFDCMPLT = 703 -PPC_INS_EFDCTSF = 704 -PPC_INS_EFDCTSI = 705 -PPC_INS_EFDCTSIDZ = 706 -PPC_INS_EFDCTSIZ = 707 -PPC_INS_EFDCTUF = 708 -PPC_INS_EFDCTUI = 709 -PPC_INS_EFDCTUIDZ = 710 -PPC_INS_EFDCTUIZ = 711 -PPC_INS_EFDDIV = 712 -PPC_INS_EFDMUL = 713 -PPC_INS_EFDNABS = 714 -PPC_INS_EFDNEG = 715 -PPC_INS_EFDSUB = 716 -PPC_INS_EFDTSTEQ = 717 -PPC_INS_EFDTSTGT = 718 -PPC_INS_EFDTSTLT = 719 -PPC_INS_EFSABS = 720 -PPC_INS_EFSADD = 721 -PPC_INS_EFSCFD = 722 -PPC_INS_EFSCFSF = 723 -PPC_INS_EFSCFSI = 724 -PPC_INS_EFSCFUF = 725 -PPC_INS_EFSCFUI = 726 -PPC_INS_EFSCMPEQ = 727 -PPC_INS_EFSCMPGT = 728 -PPC_INS_EFSCMPLT = 729 -PPC_INS_EFSCTSF = 730 -PPC_INS_EFSCTSI = 731 -PPC_INS_EFSCTSIZ = 732 -PPC_INS_EFSCTUF = 733 -PPC_INS_EFSCTUI = 734 -PPC_INS_EFSCTUIZ = 735 -PPC_INS_EFSDIV = 736 -PPC_INS_EFSMUL = 737 -PPC_INS_EFSNABS = 738 -PPC_INS_EFSNEG = 739 -PPC_INS_EFSSUB = 740 -PPC_INS_EFSTSTEQ = 741 -PPC_INS_EFSTSTGT = 742 -PPC_INS_EFSTSTLT = 743 -PPC_INS_EQV = 744 -PPC_INS_EVABS = 745 -PPC_INS_EVADDIW = 746 -PPC_INS_EVADDSMIAAW = 747 -PPC_INS_EVADDSSIAAW = 748 -PPC_INS_EVADDUMIAAW = 749 -PPC_INS_EVADDUSIAAW = 750 -PPC_INS_EVADDW = 751 -PPC_INS_EVAND = 752 -PPC_INS_EVANDC = 753 -PPC_INS_EVCMPEQ = 754 -PPC_INS_EVCMPGTS = 755 -PPC_INS_EVCMPGTU = 756 -PPC_INS_EVCMPLTS = 757 -PPC_INS_EVCMPLTU = 758 -PPC_INS_EVCNTLSW = 759 -PPC_INS_EVCNTLZW = 760 -PPC_INS_EVDIVWS = 761 -PPC_INS_EVDIVWU = 762 -PPC_INS_EVEQV = 763 -PPC_INS_EVEXTSB = 764 -PPC_INS_EVEXTSH = 765 -PPC_INS_EVFSABS = 766 -PPC_INS_EVFSADD = 767 -PPC_INS_EVFSCFSF = 768 -PPC_INS_EVFSCFSI = 769 -PPC_INS_EVFSCFUF = 770 -PPC_INS_EVFSCFUI = 771 -PPC_INS_EVFSCMPEQ = 772 -PPC_INS_EVFSCMPGT = 773 -PPC_INS_EVFSCMPLT = 774 -PPC_INS_EVFSCTSF = 775 -PPC_INS_EVFSCTSI = 776 -PPC_INS_EVFSCTSIZ = 777 -PPC_INS_EVFSCTUI = 778 -PPC_INS_EVFSDIV = 779 -PPC_INS_EVFSMUL = 780 -PPC_INS_EVFSNABS = 781 -PPC_INS_EVFSNEG = 782 -PPC_INS_EVFSSUB = 783 -PPC_INS_EVFSTSTEQ = 784 -PPC_INS_EVFSTSTGT = 785 -PPC_INS_EVFSTSTLT = 786 -PPC_INS_EVLDD = 787 -PPC_INS_EVLDDX = 788 -PPC_INS_EVLDH = 789 -PPC_INS_EVLDHX = 790 -PPC_INS_EVLDW = 791 -PPC_INS_EVLDWX = 792 -PPC_INS_EVLHHESPLAT = 793 -PPC_INS_EVLHHESPLATX = 794 -PPC_INS_EVLHHOSSPLAT = 795 -PPC_INS_EVLHHOSSPLATX = 796 -PPC_INS_EVLHHOUSPLAT = 797 -PPC_INS_EVLHHOUSPLATX = 798 -PPC_INS_EVLWHE = 799 -PPC_INS_EVLWHEX = 800 -PPC_INS_EVLWHOS = 801 -PPC_INS_EVLWHOSX = 802 -PPC_INS_EVLWHOU = 803 -PPC_INS_EVLWHOUX = 804 -PPC_INS_EVLWHSPLAT = 805 -PPC_INS_EVLWHSPLATX = 806 -PPC_INS_EVLWWSPLAT = 807 -PPC_INS_EVLWWSPLATX = 808 -PPC_INS_EVMERGEHI = 809 -PPC_INS_EVMERGEHILO = 810 -PPC_INS_EVMERGELO = 811 -PPC_INS_EVMERGELOHI = 812 -PPC_INS_EVMHEGSMFAA = 813 -PPC_INS_EVMHEGSMFAN = 814 -PPC_INS_EVMHEGSMIAA = 815 -PPC_INS_EVMHEGSMIAN = 816 -PPC_INS_EVMHEGUMIAA = 817 -PPC_INS_EVMHEGUMIAN = 818 -PPC_INS_EVMHESMF = 819 -PPC_INS_EVMHESMFA = 820 -PPC_INS_EVMHESMFAAW = 821 -PPC_INS_EVMHESMFANW = 822 -PPC_INS_EVMHESMI = 823 -PPC_INS_EVMHESMIA = 824 -PPC_INS_EVMHESMIAAW = 825 -PPC_INS_EVMHESMIANW = 826 -PPC_INS_EVMHESSF = 827 -PPC_INS_EVMHESSFA = 828 -PPC_INS_EVMHESSFAAW = 829 -PPC_INS_EVMHESSFANW = 830 -PPC_INS_EVMHESSIAAW = 831 -PPC_INS_EVMHESSIANW = 832 -PPC_INS_EVMHEUMI = 833 -PPC_INS_EVMHEUMIA = 834 -PPC_INS_EVMHEUMIAAW = 835 -PPC_INS_EVMHEUMIANW = 836 -PPC_INS_EVMHEUSIAAW = 837 -PPC_INS_EVMHEUSIANW = 838 -PPC_INS_EVMHOGSMFAA = 839 -PPC_INS_EVMHOGSMFAN = 840 -PPC_INS_EVMHOGSMIAA = 841 -PPC_INS_EVMHOGSMIAN = 842 -PPC_INS_EVMHOGUMIAA = 843 -PPC_INS_EVMHOGUMIAN = 844 -PPC_INS_EVMHOSMF = 845 -PPC_INS_EVMHOSMFA = 846 -PPC_INS_EVMHOSMFAAW = 847 -PPC_INS_EVMHOSMFANW = 848 -PPC_INS_EVMHOSMI = 849 -PPC_INS_EVMHOSMIA = 850 -PPC_INS_EVMHOSMIAAW = 851 -PPC_INS_EVMHOSMIANW = 852 -PPC_INS_EVMHOSSF = 853 -PPC_INS_EVMHOSSFA = 854 -PPC_INS_EVMHOSSFAAW = 855 -PPC_INS_EVMHOSSFANW = 856 -PPC_INS_EVMHOSSIAAW = 857 -PPC_INS_EVMHOSSIANW = 858 -PPC_INS_EVMHOUMI = 859 -PPC_INS_EVMHOUMIA = 860 -PPC_INS_EVMHOUMIAAW = 861 -PPC_INS_EVMHOUMIANW = 862 -PPC_INS_EVMHOUSIAAW = 863 -PPC_INS_EVMHOUSIANW = 864 -PPC_INS_EVMRA = 865 -PPC_INS_EVMWHSMF = 866 -PPC_INS_EVMWHSMFA = 867 -PPC_INS_EVMWHSMI = 868 -PPC_INS_EVMWHSMIA = 869 -PPC_INS_EVMWHSSF = 870 -PPC_INS_EVMWHSSFA = 871 -PPC_INS_EVMWHUMI = 872 -PPC_INS_EVMWHUMIA = 873 -PPC_INS_EVMWLSMIAAW = 874 -PPC_INS_EVMWLSMIANW = 875 -PPC_INS_EVMWLSSIAAW = 876 -PPC_INS_EVMWLSSIANW = 877 -PPC_INS_EVMWLUMI = 878 -PPC_INS_EVMWLUMIA = 879 -PPC_INS_EVMWLUMIAAW = 880 -PPC_INS_EVMWLUMIANW = 881 -PPC_INS_EVMWLUSIAAW = 882 -PPC_INS_EVMWLUSIANW = 883 -PPC_INS_EVMWSMF = 884 -PPC_INS_EVMWSMFA = 885 -PPC_INS_EVMWSMFAA = 886 -PPC_INS_EVMWSMFAN = 887 -PPC_INS_EVMWSMI = 888 -PPC_INS_EVMWSMIA = 889 -PPC_INS_EVMWSMIAA = 890 -PPC_INS_EVMWSMIAN = 891 -PPC_INS_EVMWSSF = 892 -PPC_INS_EVMWSSFA = 893 -PPC_INS_EVMWSSFAA = 894 -PPC_INS_EVMWSSFAN = 895 -PPC_INS_EVMWUMI = 896 -PPC_INS_EVMWUMIA = 897 -PPC_INS_EVMWUMIAA = 898 -PPC_INS_EVMWUMIAN = 899 -PPC_INS_EVNAND = 900 -PPC_INS_EVNEG = 901 -PPC_INS_EVNOR = 902 -PPC_INS_EVOR = 903 -PPC_INS_EVORC = 904 -PPC_INS_EVRLW = 905 -PPC_INS_EVRLWI = 906 -PPC_INS_EVRNDW = 907 -PPC_INS_EVSEL = 908 -PPC_INS_EVSLW = 909 -PPC_INS_EVSLWI = 910 -PPC_INS_EVSPLATFI = 911 -PPC_INS_EVSPLATI = 912 -PPC_INS_EVSRWIS = 913 -PPC_INS_EVSRWIU = 914 -PPC_INS_EVSRWS = 915 -PPC_INS_EVSRWU = 916 -PPC_INS_EVSTDD = 917 -PPC_INS_EVSTDDX = 918 -PPC_INS_EVSTDH = 919 -PPC_INS_EVSTDHX = 920 -PPC_INS_EVSTDW = 921 -PPC_INS_EVSTDWX = 922 -PPC_INS_EVSTWHE = 923 -PPC_INS_EVSTWHEX = 924 -PPC_INS_EVSTWHO = 925 -PPC_INS_EVSTWHOX = 926 -PPC_INS_EVSTWWE = 927 -PPC_INS_EVSTWWEX = 928 -PPC_INS_EVSTWWO = 929 -PPC_INS_EVSTWWOX = 930 -PPC_INS_EVSUBFSMIAAW = 931 -PPC_INS_EVSUBFSSIAAW = 932 -PPC_INS_EVSUBFUMIAAW = 933 -PPC_INS_EVSUBFUSIAAW = 934 -PPC_INS_EVSUBFW = 935 -PPC_INS_EVSUBIFW = 936 -PPC_INS_EVXOR = 937 -PPC_INS_EXTSB = 938 -PPC_INS_EXTSH = 939 -PPC_INS_EXTSW = 940 -PPC_INS_EXTSWSLI = 941 -PPC_INS_EIEIO = 942 -PPC_INS_FABS = 943 -PPC_INS_FADD = 944 -PPC_INS_FADDS = 945 -PPC_INS_FCFID = 946 -PPC_INS_FCFIDS = 947 -PPC_INS_FCFIDU = 948 -PPC_INS_FCFIDUS = 949 -PPC_INS_FCMPO = 950 -PPC_INS_FCMPU = 951 -PPC_INS_FCPSGN = 952 -PPC_INS_FCTID = 953 -PPC_INS_FCTIDU = 954 -PPC_INS_FCTIDUZ = 955 -PPC_INS_FCTIDZ = 956 -PPC_INS_FCTIW = 957 -PPC_INS_FCTIWU = 958 -PPC_INS_FCTIWUZ = 959 -PPC_INS_FCTIWZ = 960 -PPC_INS_FDIV = 961 -PPC_INS_FDIVS = 962 -PPC_INS_FMADD = 963 -PPC_INS_FMADDS = 964 -PPC_INS_FMR = 965 -PPC_INS_FMSUB = 966 -PPC_INS_FMSUBS = 967 -PPC_INS_FMUL = 968 -PPC_INS_FMULS = 969 -PPC_INS_FNABS = 970 -PPC_INS_FNEG = 971 -PPC_INS_FNMADD = 972 -PPC_INS_FNMADDS = 973 -PPC_INS_FNMSUB = 974 -PPC_INS_FNMSUBS = 975 -PPC_INS_FRE = 976 -PPC_INS_FRES = 977 -PPC_INS_FRIM = 978 -PPC_INS_FRIN = 979 -PPC_INS_FRIP = 980 -PPC_INS_FRIZ = 981 -PPC_INS_FRSP = 982 -PPC_INS_FRSQRTE = 983 -PPC_INS_FRSQRTES = 984 -PPC_INS_FSEL = 985 -PPC_INS_FSQRT = 986 -PPC_INS_FSQRTS = 987 -PPC_INS_FSUB = 988 -PPC_INS_FSUBS = 989 -PPC_INS_FTDIV = 990 -PPC_INS_FTSQRT = 991 -PPC_INS_HASHCHK = 992 -PPC_INS_HASHCHKP = 993 -PPC_INS_HASHST = 994 -PPC_INS_HASHSTP = 995 -PPC_INS_HRFID = 996 -PPC_INS_ICBI = 997 -PPC_INS_ICBIEP = 998 -PPC_INS_ICBLC = 999 -PPC_INS_ICBLQ = 1000 -PPC_INS_ICBT = 1001 -PPC_INS_ICBTLS = 1002 -PPC_INS_ICCCI = 1003 -PPC_INS_ISEL = 1004 -PPC_INS_ISYNC = 1005 -PPC_INS_LBARX = 1006 -PPC_INS_LBEPX = 1007 -PPC_INS_LBZ = 1008 -PPC_INS_LBZCIX = 1009 -PPC_INS_LBZU = 1010 -PPC_INS_LBZUX = 1011 -PPC_INS_LBZX = 1012 -PPC_INS_LD = 1013 -PPC_INS_LDARX = 1014 -PPC_INS_LDAT = 1015 -PPC_INS_LDBRX = 1016 -PPC_INS_LDCIX = 1017 -PPC_INS_LDU = 1018 -PPC_INS_LDUX = 1019 -PPC_INS_LDX = 1020 -PPC_INS_LFD = 1021 -PPC_INS_LFDEPX = 1022 -PPC_INS_LFDU = 1023 -PPC_INS_LFDUX = 1024 -PPC_INS_LFDX = 1025 -PPC_INS_LFIWAX = 1026 -PPC_INS_LFIWZX = 1027 -PPC_INS_LFS = 1028 -PPC_INS_LFSU = 1029 -PPC_INS_LFSUX = 1030 -PPC_INS_LFSX = 1031 -PPC_INS_LHA = 1032 -PPC_INS_LHARX = 1033 -PPC_INS_LHAU = 1034 -PPC_INS_LHAUX = 1035 -PPC_INS_LHAX = 1036 -PPC_INS_LHBRX = 1037 -PPC_INS_LHEPX = 1038 -PPC_INS_LHZ = 1039 -PPC_INS_LHZCIX = 1040 -PPC_INS_LHZU = 1041 -PPC_INS_LHZUX = 1042 -PPC_INS_LHZX = 1043 -PPC_INS_LMW = 1044 -PPC_INS_LQ = 1045 -PPC_INS_LQARX = 1046 -PPC_INS_LSWI = 1047 -PPC_INS_LVEBX = 1048 -PPC_INS_LVEHX = 1049 -PPC_INS_LVEWX = 1050 -PPC_INS_LVSL = 1051 -PPC_INS_LVSR = 1052 -PPC_INS_LVX = 1053 -PPC_INS_LVXL = 1054 -PPC_INS_LWA = 1055 -PPC_INS_LWARX = 1056 -PPC_INS_LWAT = 1057 -PPC_INS_LWAUX = 1058 -PPC_INS_LWAX = 1059 -PPC_INS_LWBRX = 1060 -PPC_INS_LWEPX = 1061 -PPC_INS_LWZ = 1062 -PPC_INS_LWZCIX = 1063 -PPC_INS_LWZU = 1064 -PPC_INS_LWZUX = 1065 -PPC_INS_LWZX = 1066 -PPC_INS_LXSD = 1067 -PPC_INS_LXSDX = 1068 -PPC_INS_LXSIBZX = 1069 -PPC_INS_LXSIHZX = 1070 -PPC_INS_LXSIWAX = 1071 -PPC_INS_LXSIWZX = 1072 -PPC_INS_LXSSP = 1073 -PPC_INS_LXSSPX = 1074 -PPC_INS_LXV = 1075 -PPC_INS_LXVB16X = 1076 -PPC_INS_LXVD2X = 1077 -PPC_INS_LXVDSX = 1078 -PPC_INS_LXVH8X = 1079 -PPC_INS_LXVKQ = 1080 -PPC_INS_LXVL = 1081 -PPC_INS_LXVLL = 1082 -PPC_INS_LXVP = 1083 -PPC_INS_LXVPRL = 1084 -PPC_INS_LXVPRLL = 1085 -PPC_INS_LXVPX = 1086 -PPC_INS_LXVRBX = 1087 -PPC_INS_LXVRDX = 1088 -PPC_INS_LXVRHX = 1089 -PPC_INS_LXVRL = 1090 -PPC_INS_LXVRLL = 1091 -PPC_INS_LXVRWX = 1092 -PPC_INS_LXVW4X = 1093 -PPC_INS_LXVWSX = 1094 -PPC_INS_LXVX = 1095 -PPC_INS_MADDHD = 1096 -PPC_INS_MADDHDU = 1097 -PPC_INS_MADDLD = 1098 -PPC_INS_MBAR = 1099 -PPC_INS_MCRF = 1100 -PPC_INS_MCRFS = 1101 -PPC_INS_MCRXRX = 1102 -PPC_INS_MFBHRBE = 1103 -PPC_INS_MFCR = 1104 -PPC_INS_MFCTR = 1105 -PPC_INS_MFDCR = 1106 -PPC_INS_MFFS = 1107 -PPC_INS_MFFSCDRN = 1108 -PPC_INS_MFFSCDRNI = 1109 -PPC_INS_MFFSCE = 1110 -PPC_INS_MFFSCRN = 1111 -PPC_INS_MFFSCRNI = 1112 -PPC_INS_MFFSL = 1113 -PPC_INS_MFLR = 1114 -PPC_INS_MFMSR = 1115 -PPC_INS_MFOCRF = 1116 -PPC_INS_MFPMR = 1117 -PPC_INS_MFSPR = 1118 -PPC_INS_MFSR = 1119 -PPC_INS_MFSRIN = 1120 -PPC_INS_MFTB = 1121 -PPC_INS_MFVSCR = 1122 -PPC_INS_MFVSRD = 1123 -PPC_INS_MFVSRLD = 1124 -PPC_INS_MFVSRWZ = 1125 -PPC_INS_MODSD = 1126 -PPC_INS_MODSW = 1127 -PPC_INS_MODUD = 1128 -PPC_INS_MODUW = 1129 -PPC_INS_MSGSYNC = 1130 -PPC_INS_MTCRF = 1131 -PPC_INS_MTCTR = 1132 -PPC_INS_MTDCR = 1133 -PPC_INS_MTFSB0 = 1134 -PPC_INS_MTFSB1 = 1135 -PPC_INS_MTFSF = 1136 -PPC_INS_MTFSFI = 1137 -PPC_INS_MTLR = 1138 -PPC_INS_MTMSR = 1139 -PPC_INS_MTMSRD = 1140 -PPC_INS_MTOCRF = 1141 -PPC_INS_MTPMR = 1142 -PPC_INS_MTSPR = 1143 -PPC_INS_MTSR = 1144 -PPC_INS_MTSRIN = 1145 -PPC_INS_MTVSCR = 1146 -PPC_INS_MTVSRBM = 1147 -PPC_INS_MTVSRBMI = 1148 -PPC_INS_MTVSRD = 1149 -PPC_INS_MTVSRDD = 1150 -PPC_INS_MTVSRDM = 1151 -PPC_INS_MTVSRHM = 1152 -PPC_INS_MTVSRQM = 1153 -PPC_INS_MTVSRWA = 1154 -PPC_INS_MTVSRWM = 1155 -PPC_INS_MTVSRWS = 1156 -PPC_INS_MTVSRWZ = 1157 -PPC_INS_MULHD = 1158 -PPC_INS_MULHDU = 1159 -PPC_INS_MULHW = 1160 -PPC_INS_MULHWU = 1161 -PPC_INS_MULLD = 1162 -PPC_INS_MULLDO = 1163 -PPC_INS_MULLI = 1164 -PPC_INS_MULLW = 1165 -PPC_INS_MULLWO = 1166 -PPC_INS_NAND = 1167 -PPC_INS_NAP = 1168 -PPC_INS_NEG = 1169 -PPC_INS_NEGO = 1170 -PPC_INS_NOP = 1171 -PPC_INS_NOR = 1172 -PPC_INS_OR = 1173 -PPC_INS_ORC = 1174 -PPC_INS_ORI = 1175 -PPC_INS_ORIS = 1176 -PPC_INS_PADDI = 1177 -PPC_INS_PDEPD = 1178 -PPC_INS_PEXTD = 1179 -PPC_INS_PLBZ = 1180 -PPC_INS_PLD = 1181 -PPC_INS_PLFD = 1182 -PPC_INS_PLFS = 1183 -PPC_INS_PLHA = 1184 -PPC_INS_PLHZ = 1185 -PPC_INS_PLI = 1186 -PPC_INS_PLWA = 1187 -PPC_INS_PLWZ = 1188 -PPC_INS_PLXSD = 1189 -PPC_INS_PLXSSP = 1190 -PPC_INS_PLXV = 1191 -PPC_INS_PLXVP = 1192 -PPC_INS_PMXVBF16GER2 = 1193 -PPC_INS_PMXVBF16GER2NN = 1194 -PPC_INS_PMXVBF16GER2NP = 1195 -PPC_INS_PMXVBF16GER2PN = 1196 -PPC_INS_PMXVBF16GER2PP = 1197 -PPC_INS_PMXVF16GER2 = 1198 -PPC_INS_PMXVF16GER2NN = 1199 -PPC_INS_PMXVF16GER2NP = 1200 -PPC_INS_PMXVF16GER2PN = 1201 -PPC_INS_PMXVF16GER2PP = 1202 -PPC_INS_PMXVF32GER = 1203 -PPC_INS_PMXVF32GERNN = 1204 -PPC_INS_PMXVF32GERNP = 1205 -PPC_INS_PMXVF32GERPN = 1206 -PPC_INS_PMXVF32GERPP = 1207 -PPC_INS_PMXVF64GER = 1208 -PPC_INS_PMXVF64GERNN = 1209 -PPC_INS_PMXVF64GERNP = 1210 -PPC_INS_PMXVF64GERPN = 1211 -PPC_INS_PMXVF64GERPP = 1212 -PPC_INS_PMXVI16GER2 = 1213 -PPC_INS_PMXVI16GER2PP = 1214 -PPC_INS_PMXVI16GER2S = 1215 -PPC_INS_PMXVI16GER2SPP = 1216 -PPC_INS_PMXVI4GER8 = 1217 -PPC_INS_PMXVI4GER8PP = 1218 -PPC_INS_PMXVI8GER4 = 1219 -PPC_INS_PMXVI8GER4PP = 1220 -PPC_INS_PMXVI8GER4SPP = 1221 -PPC_INS_POPCNTB = 1222 -PPC_INS_POPCNTD = 1223 -PPC_INS_POPCNTW = 1224 -PPC_INS_DCBZ_L = 1225 -PPC_INS_PSQ_L = 1226 -PPC_INS_PSQ_LU = 1227 -PPC_INS_PSQ_LUX = 1228 -PPC_INS_PSQ_LX = 1229 -PPC_INS_PSQ_ST = 1230 -PPC_INS_PSQ_STU = 1231 -PPC_INS_PSQ_STUX = 1232 -PPC_INS_PSQ_STX = 1233 -PPC_INS_PSTB = 1234 -PPC_INS_PSTD = 1235 -PPC_INS_PSTFD = 1236 -PPC_INS_PSTFS = 1237 -PPC_INS_PSTH = 1238 -PPC_INS_PSTW = 1239 -PPC_INS_PSTXSD = 1240 -PPC_INS_PSTXSSP = 1241 -PPC_INS_PSTXV = 1242 -PPC_INS_PSTXVP = 1243 -PPC_INS_PS_ABS = 1244 -PPC_INS_PS_ADD = 1245 -PPC_INS_PS_CMPO0 = 1246 -PPC_INS_PS_CMPO1 = 1247 -PPC_INS_PS_CMPU0 = 1248 -PPC_INS_PS_CMPU1 = 1249 -PPC_INS_PS_DIV = 1250 -PPC_INS_PS_MADD = 1251 -PPC_INS_PS_MADDS0 = 1252 -PPC_INS_PS_MADDS1 = 1253 -PPC_INS_PS_MERGE00 = 1254 -PPC_INS_PS_MERGE01 = 1255 -PPC_INS_PS_MERGE10 = 1256 -PPC_INS_PS_MERGE11 = 1257 -PPC_INS_PS_MR = 1258 -PPC_INS_PS_MSUB = 1259 -PPC_INS_PS_MUL = 1260 -PPC_INS_PS_MULS0 = 1261 -PPC_INS_PS_MULS1 = 1262 -PPC_INS_PS_NABS = 1263 -PPC_INS_PS_NEG = 1264 -PPC_INS_PS_NMADD = 1265 -PPC_INS_PS_NMSUB = 1266 -PPC_INS_PS_RES = 1267 -PPC_INS_PS_RSQRTE = 1268 -PPC_INS_PS_SEL = 1269 -PPC_INS_PS_SUB = 1270 -PPC_INS_PS_SUM0 = 1271 -PPC_INS_PS_SUM1 = 1272 -PPC_INS_QVALIGNI = 1273 -PPC_INS_QVESPLATI = 1274 -PPC_INS_QVFABS = 1275 -PPC_INS_QVFADD = 1276 -PPC_INS_QVFADDS = 1277 -PPC_INS_QVFCFID = 1278 -PPC_INS_QVFCFIDS = 1279 -PPC_INS_QVFCFIDU = 1280 -PPC_INS_QVFCFIDUS = 1281 -PPC_INS_QVFCMPEQ = 1282 -PPC_INS_QVFCMPGT = 1283 -PPC_INS_QVFCMPLT = 1284 -PPC_INS_QVFCPSGN = 1285 -PPC_INS_QVFCTID = 1286 -PPC_INS_QVFCTIDU = 1287 -PPC_INS_QVFCTIDUZ = 1288 -PPC_INS_QVFCTIDZ = 1289 -PPC_INS_QVFCTIW = 1290 -PPC_INS_QVFCTIWU = 1291 -PPC_INS_QVFCTIWUZ = 1292 -PPC_INS_QVFCTIWZ = 1293 -PPC_INS_QVFLOGICAL = 1294 -PPC_INS_QVFMADD = 1295 -PPC_INS_QVFMADDS = 1296 -PPC_INS_QVFMR = 1297 -PPC_INS_QVFMSUB = 1298 -PPC_INS_QVFMSUBS = 1299 -PPC_INS_QVFMUL = 1300 -PPC_INS_QVFMULS = 1301 -PPC_INS_QVFNABS = 1302 -PPC_INS_QVFNEG = 1303 -PPC_INS_QVFNMADD = 1304 -PPC_INS_QVFNMADDS = 1305 -PPC_INS_QVFNMSUB = 1306 -PPC_INS_QVFNMSUBS = 1307 -PPC_INS_QVFPERM = 1308 -PPC_INS_QVFRE = 1309 -PPC_INS_QVFRES = 1310 -PPC_INS_QVFRIM = 1311 -PPC_INS_QVFRIN = 1312 -PPC_INS_QVFRIP = 1313 -PPC_INS_QVFRIZ = 1314 -PPC_INS_QVFRSP = 1315 -PPC_INS_QVFRSQRTE = 1316 -PPC_INS_QVFRSQRTES = 1317 -PPC_INS_QVFSEL = 1318 -PPC_INS_QVFSUB = 1319 -PPC_INS_QVFSUBS = 1320 -PPC_INS_QVFTSTNAN = 1321 -PPC_INS_QVFXMADD = 1322 -PPC_INS_QVFXMADDS = 1323 -PPC_INS_QVFXMUL = 1324 -PPC_INS_QVFXMULS = 1325 -PPC_INS_QVFXXCPNMADD = 1326 -PPC_INS_QVFXXCPNMADDS = 1327 -PPC_INS_QVFXXMADD = 1328 -PPC_INS_QVFXXMADDS = 1329 -PPC_INS_QVFXXNPMADD = 1330 -PPC_INS_QVFXXNPMADDS = 1331 -PPC_INS_QVGPCI = 1332 -PPC_INS_QVLFCDUX = 1333 -PPC_INS_QVLFCDUXA = 1334 -PPC_INS_QVLFCDX = 1335 -PPC_INS_QVLFCDXA = 1336 -PPC_INS_QVLFCSUX = 1337 -PPC_INS_QVLFCSUXA = 1338 -PPC_INS_QVLFCSX = 1339 -PPC_INS_QVLFCSXA = 1340 -PPC_INS_QVLFDUX = 1341 -PPC_INS_QVLFDUXA = 1342 -PPC_INS_QVLFDX = 1343 -PPC_INS_QVLFDXA = 1344 -PPC_INS_QVLFIWAX = 1345 -PPC_INS_QVLFIWAXA = 1346 -PPC_INS_QVLFIWZX = 1347 -PPC_INS_QVLFIWZXA = 1348 -PPC_INS_QVLFSUX = 1349 -PPC_INS_QVLFSUXA = 1350 -PPC_INS_QVLFSX = 1351 -PPC_INS_QVLFSXA = 1352 -PPC_INS_QVLPCLDX = 1353 -PPC_INS_QVLPCLSX = 1354 -PPC_INS_QVLPCRDX = 1355 -PPC_INS_QVLPCRSX = 1356 -PPC_INS_QVSTFCDUX = 1357 -PPC_INS_QVSTFCDUXA = 1358 -PPC_INS_QVSTFCDUXI = 1359 -PPC_INS_QVSTFCDUXIA = 1360 -PPC_INS_QVSTFCDX = 1361 -PPC_INS_QVSTFCDXA = 1362 -PPC_INS_QVSTFCDXI = 1363 -PPC_INS_QVSTFCDXIA = 1364 -PPC_INS_QVSTFCSUX = 1365 -PPC_INS_QVSTFCSUXA = 1366 -PPC_INS_QVSTFCSUXI = 1367 -PPC_INS_QVSTFCSUXIA = 1368 -PPC_INS_QVSTFCSX = 1369 -PPC_INS_QVSTFCSXA = 1370 -PPC_INS_QVSTFCSXI = 1371 -PPC_INS_QVSTFCSXIA = 1372 -PPC_INS_QVSTFDUX = 1373 -PPC_INS_QVSTFDUXA = 1374 -PPC_INS_QVSTFDUXI = 1375 -PPC_INS_QVSTFDUXIA = 1376 -PPC_INS_QVSTFDX = 1377 -PPC_INS_QVSTFDXA = 1378 -PPC_INS_QVSTFDXI = 1379 -PPC_INS_QVSTFDXIA = 1380 -PPC_INS_QVSTFIWX = 1381 -PPC_INS_QVSTFIWXA = 1382 -PPC_INS_QVSTFSUX = 1383 -PPC_INS_QVSTFSUXA = 1384 -PPC_INS_QVSTFSUXI = 1385 -PPC_INS_QVSTFSUXIA = 1386 -PPC_INS_QVSTFSX = 1387 -PPC_INS_QVSTFSXA = 1388 -PPC_INS_QVSTFSXI = 1389 -PPC_INS_QVSTFSXIA = 1390 -PPC_INS_RFCI = 1391 -PPC_INS_RFDI = 1392 -PPC_INS_RFEBB = 1393 -PPC_INS_RFI = 1394 -PPC_INS_RFID = 1395 -PPC_INS_RFMCI = 1396 -PPC_INS_RLDCL = 1397 -PPC_INS_RLDCR = 1398 -PPC_INS_RLDIC = 1399 -PPC_INS_RLDICL = 1400 -PPC_INS_RLDICR = 1401 -PPC_INS_RLDIMI = 1402 -PPC_INS_SC = 1403 -PPC_INS_SETB = 1404 -PPC_INS_SETBC = 1405 -PPC_INS_SETBCR = 1406 -PPC_INS_SETNBC = 1407 -PPC_INS_SETNBCR = 1408 -PPC_INS_SLBFEE = 1409 -PPC_INS_SLBIA = 1410 -PPC_INS_SLBIE = 1411 -PPC_INS_SLBIEG = 1412 -PPC_INS_SLBMFEE = 1413 -PPC_INS_SLBMFEV = 1414 -PPC_INS_SLBMTE = 1415 -PPC_INS_SLBSYNC = 1416 -PPC_INS_SLD = 1417 -PPC_INS_SLW = 1418 -PPC_INS_STW = 1419 -PPC_INS_STWX = 1420 -PPC_INS_SRAD = 1421 -PPC_INS_SRADI = 1422 -PPC_INS_SRAW = 1423 -PPC_INS_SRAWI = 1424 -PPC_INS_SRD = 1425 -PPC_INS_SRW = 1426 -PPC_INS_STB = 1427 -PPC_INS_STBCIX = 1428 -PPC_INS_STBCX = 1429 -PPC_INS_STBEPX = 1430 -PPC_INS_STBU = 1431 -PPC_INS_STBUX = 1432 -PPC_INS_STBX = 1433 -PPC_INS_STD = 1434 -PPC_INS_STDAT = 1435 -PPC_INS_STDBRX = 1436 -PPC_INS_STDCIX = 1437 -PPC_INS_STDCX = 1438 -PPC_INS_STDU = 1439 -PPC_INS_STDUX = 1440 -PPC_INS_STDX = 1441 -PPC_INS_STFD = 1442 -PPC_INS_STFDEPX = 1443 -PPC_INS_STFDU = 1444 -PPC_INS_STFDUX = 1445 -PPC_INS_STFDX = 1446 -PPC_INS_STFIWX = 1447 -PPC_INS_STFS = 1448 -PPC_INS_STFSU = 1449 -PPC_INS_STFSUX = 1450 -PPC_INS_STFSX = 1451 -PPC_INS_STH = 1452 -PPC_INS_STHBRX = 1453 -PPC_INS_STHCIX = 1454 -PPC_INS_STHCX = 1455 -PPC_INS_STHEPX = 1456 -PPC_INS_STHU = 1457 -PPC_INS_STHUX = 1458 -PPC_INS_STHX = 1459 -PPC_INS_STMW = 1460 -PPC_INS_STOP = 1461 -PPC_INS_STQ = 1462 -PPC_INS_STQCX = 1463 -PPC_INS_STSWI = 1464 -PPC_INS_STVEBX = 1465 -PPC_INS_STVEHX = 1466 -PPC_INS_STVEWX = 1467 -PPC_INS_STVX = 1468 -PPC_INS_STVXL = 1469 -PPC_INS_STWAT = 1470 -PPC_INS_STWBRX = 1471 -PPC_INS_STWCIX = 1472 -PPC_INS_STWCX = 1473 -PPC_INS_STWEPX = 1474 -PPC_INS_STWU = 1475 -PPC_INS_STWUX = 1476 -PPC_INS_STXSD = 1477 -PPC_INS_STXSDX = 1478 -PPC_INS_STXSIBX = 1479 -PPC_INS_STXSIHX = 1480 -PPC_INS_STXSIWX = 1481 -PPC_INS_STXSSP = 1482 -PPC_INS_STXSSPX = 1483 -PPC_INS_STXV = 1484 -PPC_INS_STXVB16X = 1485 -PPC_INS_STXVD2X = 1486 -PPC_INS_STXVH8X = 1487 -PPC_INS_STXVL = 1488 -PPC_INS_STXVLL = 1489 -PPC_INS_STXVP = 1490 -PPC_INS_STXVPRL = 1491 -PPC_INS_STXVPRLL = 1492 -PPC_INS_STXVPX = 1493 -PPC_INS_STXVRBX = 1494 -PPC_INS_STXVRDX = 1495 -PPC_INS_STXVRHX = 1496 -PPC_INS_STXVRL = 1497 -PPC_INS_STXVRLL = 1498 -PPC_INS_STXVRWX = 1499 -PPC_INS_STXVW4X = 1500 -PPC_INS_STXVX = 1501 -PPC_INS_SUBF = 1502 -PPC_INS_SUBFC = 1503 -PPC_INS_SUBFCO = 1504 -PPC_INS_SUBFE = 1505 -PPC_INS_SUBFEO = 1506 -PPC_INS_SUBFIC = 1507 -PPC_INS_SUBFME = 1508 -PPC_INS_SUBFMEO = 1509 -PPC_INS_SUBFO = 1510 -PPC_INS_SUBFUS = 1511 -PPC_INS_SUBFZE = 1512 -PPC_INS_SUBFZEO = 1513 -PPC_INS_SYNC = 1514 -PPC_INS_TABORT = 1515 -PPC_INS_TABORTDC = 1516 -PPC_INS_TABORTDCI = 1517 -PPC_INS_TABORTWC = 1518 -PPC_INS_TABORTWCI = 1519 -PPC_INS_TBEGIN = 1520 -PPC_INS_TCHECK = 1521 -PPC_INS_TD = 1522 -PPC_INS_TDI = 1523 -PPC_INS_TEND = 1524 -PPC_INS_TLBIA = 1525 -PPC_INS_TLBIE = 1526 -PPC_INS_TLBIEL = 1527 -PPC_INS_TLBIVAX = 1528 -PPC_INS_TLBLD = 1529 -PPC_INS_TLBLI = 1530 -PPC_INS_TLBRE = 1531 -PPC_INS_TLBSX = 1532 -PPC_INS_TLBSYNC = 1533 -PPC_INS_TLBWE = 1534 -PPC_INS_TRAP = 1535 -PPC_INS_TRECHKPT = 1536 -PPC_INS_TRECLAIM = 1537 -PPC_INS_TSR = 1538 -PPC_INS_TW = 1539 -PPC_INS_TWI = 1540 -PPC_INS_VABSDUB = 1541 -PPC_INS_VABSDUH = 1542 -PPC_INS_VABSDUW = 1543 -PPC_INS_VADDCUQ = 1544 -PPC_INS_VADDCUW = 1545 -PPC_INS_VADDECUQ = 1546 -PPC_INS_VADDEUQM = 1547 -PPC_INS_VADDFP = 1548 -PPC_INS_VADDSBS = 1549 -PPC_INS_VADDSHS = 1550 -PPC_INS_VADDSWS = 1551 -PPC_INS_VADDUBM = 1552 -PPC_INS_VADDUBS = 1553 -PPC_INS_VADDUDM = 1554 -PPC_INS_VADDUHM = 1555 -PPC_INS_VADDUHS = 1556 -PPC_INS_VADDUQM = 1557 -PPC_INS_VADDUWM = 1558 -PPC_INS_VADDUWS = 1559 -PPC_INS_VAND = 1560 -PPC_INS_VANDC = 1561 -PPC_INS_VAVGSB = 1562 -PPC_INS_VAVGSH = 1563 -PPC_INS_VAVGSW = 1564 -PPC_INS_VAVGUB = 1565 -PPC_INS_VAVGUH = 1566 -PPC_INS_VAVGUW = 1567 -PPC_INS_VBPERMD = 1568 -PPC_INS_VBPERMQ = 1569 -PPC_INS_VCFSX = 1570 -PPC_INS_VCFUGED = 1571 -PPC_INS_VCFUX = 1572 -PPC_INS_VCIPHER = 1573 -PPC_INS_VCIPHERLAST = 1574 -PPC_INS_VCLRLB = 1575 -PPC_INS_VCLRRB = 1576 -PPC_INS_VCLZB = 1577 -PPC_INS_VCLZD = 1578 -PPC_INS_VCLZDM = 1579 -PPC_INS_VCLZH = 1580 -PPC_INS_VCLZLSBB = 1581 -PPC_INS_VCLZW = 1582 -PPC_INS_VCMPBFP = 1583 -PPC_INS_VCMPEQFP = 1584 -PPC_INS_VCMPEQUB = 1585 -PPC_INS_VCMPEQUD = 1586 -PPC_INS_VCMPEQUH = 1587 -PPC_INS_VCMPEQUQ = 1588 -PPC_INS_VCMPEQUW = 1589 -PPC_INS_VCMPGEFP = 1590 -PPC_INS_VCMPGTFP = 1591 -PPC_INS_VCMPGTSB = 1592 -PPC_INS_VCMPGTSD = 1593 -PPC_INS_VCMPGTSH = 1594 -PPC_INS_VCMPGTSQ = 1595 -PPC_INS_VCMPGTSW = 1596 -PPC_INS_VCMPGTUB = 1597 -PPC_INS_VCMPGTUD = 1598 -PPC_INS_VCMPGTUH = 1599 -PPC_INS_VCMPGTUQ = 1600 -PPC_INS_VCMPGTUW = 1601 -PPC_INS_VCMPNEB = 1602 -PPC_INS_VCMPNEH = 1603 -PPC_INS_VCMPNEW = 1604 -PPC_INS_VCMPNEZB = 1605 -PPC_INS_VCMPNEZH = 1606 -PPC_INS_VCMPNEZW = 1607 -PPC_INS_VCMPSQ = 1608 -PPC_INS_VCMPUQ = 1609 -PPC_INS_VCNTMBB = 1610 -PPC_INS_VCNTMBD = 1611 -PPC_INS_VCNTMBH = 1612 -PPC_INS_VCNTMBW = 1613 -PPC_INS_VCTSXS = 1614 -PPC_INS_VCTUXS = 1615 -PPC_INS_VCTZB = 1616 -PPC_INS_VCTZD = 1617 -PPC_INS_VCTZDM = 1618 -PPC_INS_VCTZH = 1619 -PPC_INS_VCTZLSBB = 1620 -PPC_INS_VCTZW = 1621 -PPC_INS_VDIVESD = 1622 -PPC_INS_VDIVESQ = 1623 -PPC_INS_VDIVESW = 1624 -PPC_INS_VDIVEUD = 1625 -PPC_INS_VDIVEUQ = 1626 -PPC_INS_VDIVEUW = 1627 -PPC_INS_VDIVSD = 1628 -PPC_INS_VDIVSQ = 1629 -PPC_INS_VDIVSW = 1630 -PPC_INS_VDIVUD = 1631 -PPC_INS_VDIVUQ = 1632 -PPC_INS_VDIVUW = 1633 -PPC_INS_VEQV = 1634 -PPC_INS_VEXPANDBM = 1635 -PPC_INS_VEXPANDDM = 1636 -PPC_INS_VEXPANDHM = 1637 -PPC_INS_VEXPANDQM = 1638 -PPC_INS_VEXPANDWM = 1639 -PPC_INS_VEXPTEFP = 1640 -PPC_INS_VEXTDDVLX = 1641 -PPC_INS_VEXTDDVRX = 1642 -PPC_INS_VEXTDUBVLX = 1643 -PPC_INS_VEXTDUBVRX = 1644 -PPC_INS_VEXTDUHVLX = 1645 -PPC_INS_VEXTDUHVRX = 1646 -PPC_INS_VEXTDUWVLX = 1647 -PPC_INS_VEXTDUWVRX = 1648 -PPC_INS_VEXTRACTBM = 1649 -PPC_INS_VEXTRACTD = 1650 -PPC_INS_VEXTRACTDM = 1651 -PPC_INS_VEXTRACTHM = 1652 -PPC_INS_VEXTRACTQM = 1653 -PPC_INS_VEXTRACTUB = 1654 -PPC_INS_VEXTRACTUH = 1655 -PPC_INS_VEXTRACTUW = 1656 -PPC_INS_VEXTRACTWM = 1657 -PPC_INS_VEXTSB2D = 1658 -PPC_INS_VEXTSB2W = 1659 -PPC_INS_VEXTSD2Q = 1660 -PPC_INS_VEXTSH2D = 1661 -PPC_INS_VEXTSH2W = 1662 -PPC_INS_VEXTSW2D = 1663 -PPC_INS_VEXTUBLX = 1664 -PPC_INS_VEXTUBRX = 1665 -PPC_INS_VEXTUHLX = 1666 -PPC_INS_VEXTUHRX = 1667 -PPC_INS_VEXTUWLX = 1668 -PPC_INS_VEXTUWRX = 1669 -PPC_INS_VGBBD = 1670 -PPC_INS_VGNB = 1671 -PPC_INS_VINSBLX = 1672 -PPC_INS_VINSBRX = 1673 -PPC_INS_VINSBVLX = 1674 -PPC_INS_VINSBVRX = 1675 -PPC_INS_VINSD = 1676 -PPC_INS_VINSDLX = 1677 -PPC_INS_VINSDRX = 1678 -PPC_INS_VINSERTB = 1679 -PPC_INS_VINSERTD = 1680 -PPC_INS_VINSERTH = 1681 -PPC_INS_VINSERTW = 1682 -PPC_INS_VINSHLX = 1683 -PPC_INS_VINSHRX = 1684 -PPC_INS_VINSHVLX = 1685 -PPC_INS_VINSHVRX = 1686 -PPC_INS_VINSW = 1687 -PPC_INS_VINSWLX = 1688 -PPC_INS_VINSWRX = 1689 -PPC_INS_VINSWVLX = 1690 -PPC_INS_VINSWVRX = 1691 -PPC_INS_VLOGEFP = 1692 -PPC_INS_VMADDFP = 1693 -PPC_INS_VMAXFP = 1694 -PPC_INS_VMAXSB = 1695 -PPC_INS_VMAXSD = 1696 -PPC_INS_VMAXSH = 1697 -PPC_INS_VMAXSW = 1698 -PPC_INS_VMAXUB = 1699 -PPC_INS_VMAXUD = 1700 -PPC_INS_VMAXUH = 1701 -PPC_INS_VMAXUW = 1702 -PPC_INS_VMHADDSHS = 1703 -PPC_INS_VMHRADDSHS = 1704 -PPC_INS_VMINFP = 1705 -PPC_INS_VMINSB = 1706 -PPC_INS_VMINSD = 1707 -PPC_INS_VMINSH = 1708 -PPC_INS_VMINSW = 1709 -PPC_INS_VMINUB = 1710 -PPC_INS_VMINUD = 1711 -PPC_INS_VMINUH = 1712 -PPC_INS_VMINUW = 1713 -PPC_INS_VMLADDUHM = 1714 -PPC_INS_VMODSD = 1715 -PPC_INS_VMODSQ = 1716 -PPC_INS_VMODSW = 1717 -PPC_INS_VMODUD = 1718 -PPC_INS_VMODUQ = 1719 -PPC_INS_VMODUW = 1720 -PPC_INS_VMRGEW = 1721 -PPC_INS_VMRGHB = 1722 -PPC_INS_VMRGHH = 1723 -PPC_INS_VMRGHW = 1724 -PPC_INS_VMRGLB = 1725 -PPC_INS_VMRGLH = 1726 -PPC_INS_VMRGLW = 1727 -PPC_INS_VMRGOW = 1728 -PPC_INS_VMSUMCUD = 1729 -PPC_INS_VMSUMMBM = 1730 -PPC_INS_VMSUMSHM = 1731 -PPC_INS_VMSUMSHS = 1732 -PPC_INS_VMSUMUBM = 1733 -PPC_INS_VMSUMUDM = 1734 -PPC_INS_VMSUMUHM = 1735 -PPC_INS_VMSUMUHS = 1736 -PPC_INS_VMUL10CUQ = 1737 -PPC_INS_VMUL10ECUQ = 1738 -PPC_INS_VMUL10EUQ = 1739 -PPC_INS_VMUL10UQ = 1740 -PPC_INS_VMULESB = 1741 -PPC_INS_VMULESD = 1742 -PPC_INS_VMULESH = 1743 -PPC_INS_VMULESW = 1744 -PPC_INS_VMULEUB = 1745 -PPC_INS_VMULEUD = 1746 -PPC_INS_VMULEUH = 1747 -PPC_INS_VMULEUW = 1748 -PPC_INS_VMULHSD = 1749 -PPC_INS_VMULHSW = 1750 -PPC_INS_VMULHUD = 1751 -PPC_INS_VMULHUW = 1752 -PPC_INS_VMULLD = 1753 -PPC_INS_VMULOSB = 1754 -PPC_INS_VMULOSD = 1755 -PPC_INS_VMULOSH = 1756 -PPC_INS_VMULOSW = 1757 -PPC_INS_VMULOUB = 1758 -PPC_INS_VMULOUD = 1759 -PPC_INS_VMULOUH = 1760 -PPC_INS_VMULOUW = 1761 -PPC_INS_VMULUWM = 1762 -PPC_INS_VNAND = 1763 -PPC_INS_VNCIPHER = 1764 -PPC_INS_VNCIPHERLAST = 1765 -PPC_INS_VNEGD = 1766 -PPC_INS_VNEGW = 1767 -PPC_INS_VNMSUBFP = 1768 -PPC_INS_VNOR = 1769 -PPC_INS_VOR = 1770 -PPC_INS_VORC = 1771 -PPC_INS_VPDEPD = 1772 -PPC_INS_VPERM = 1773 -PPC_INS_VPERMR = 1774 -PPC_INS_VPERMXOR = 1775 -PPC_INS_VPEXTD = 1776 -PPC_INS_VPKPX = 1777 -PPC_INS_VPKSDSS = 1778 -PPC_INS_VPKSDUS = 1779 -PPC_INS_VPKSHSS = 1780 -PPC_INS_VPKSHUS = 1781 -PPC_INS_VPKSWSS = 1782 -PPC_INS_VPKSWUS = 1783 -PPC_INS_VPKUDUM = 1784 -PPC_INS_VPKUDUS = 1785 -PPC_INS_VPKUHUM = 1786 -PPC_INS_VPKUHUS = 1787 -PPC_INS_VPKUWUM = 1788 -PPC_INS_VPKUWUS = 1789 -PPC_INS_VPMSUMB = 1790 -PPC_INS_VPMSUMD = 1791 -PPC_INS_VPMSUMH = 1792 -PPC_INS_VPMSUMW = 1793 -PPC_INS_VPOPCNTB = 1794 -PPC_INS_VPOPCNTD = 1795 -PPC_INS_VPOPCNTH = 1796 -PPC_INS_VPOPCNTW = 1797 -PPC_INS_VPRTYBD = 1798 -PPC_INS_VPRTYBQ = 1799 -PPC_INS_VPRTYBW = 1800 -PPC_INS_VREFP = 1801 -PPC_INS_VRFIM = 1802 -PPC_INS_VRFIN = 1803 -PPC_INS_VRFIP = 1804 -PPC_INS_VRFIZ = 1805 -PPC_INS_VRLB = 1806 -PPC_INS_VRLD = 1807 -PPC_INS_VRLDMI = 1808 -PPC_INS_VRLDNM = 1809 -PPC_INS_VRLH = 1810 -PPC_INS_VRLQ = 1811 -PPC_INS_VRLQMI = 1812 -PPC_INS_VRLQNM = 1813 -PPC_INS_VRLW = 1814 -PPC_INS_VRLWMI = 1815 -PPC_INS_VRLWNM = 1816 -PPC_INS_VRSQRTEFP = 1817 -PPC_INS_VSBOX = 1818 -PPC_INS_VSEL = 1819 -PPC_INS_VSHASIGMAD = 1820 -PPC_INS_VSHASIGMAW = 1821 -PPC_INS_VSL = 1822 -PPC_INS_VSLB = 1823 -PPC_INS_VSLD = 1824 -PPC_INS_VSLDBI = 1825 -PPC_INS_VSLDOI = 1826 -PPC_INS_VSLH = 1827 -PPC_INS_VSLO = 1828 -PPC_INS_VSLQ = 1829 -PPC_INS_VSLV = 1830 -PPC_INS_VSLW = 1831 -PPC_INS_VSPLTB = 1832 -PPC_INS_VSPLTH = 1833 -PPC_INS_VSPLTISB = 1834 -PPC_INS_VSPLTISH = 1835 -PPC_INS_VSPLTISW = 1836 -PPC_INS_VSPLTW = 1837 -PPC_INS_VSR = 1838 -PPC_INS_VSRAB = 1839 -PPC_INS_VSRAD = 1840 -PPC_INS_VSRAH = 1841 -PPC_INS_VSRAQ = 1842 -PPC_INS_VSRAW = 1843 -PPC_INS_VSRB = 1844 -PPC_INS_VSRD = 1845 -PPC_INS_VSRDBI = 1846 -PPC_INS_VSRH = 1847 -PPC_INS_VSRO = 1848 -PPC_INS_VSRQ = 1849 -PPC_INS_VSRV = 1850 -PPC_INS_VSRW = 1851 -PPC_INS_VSTRIBL = 1852 -PPC_INS_VSTRIBR = 1853 -PPC_INS_VSTRIHL = 1854 -PPC_INS_VSTRIHR = 1855 -PPC_INS_VSUBCUQ = 1856 -PPC_INS_VSUBCUW = 1857 -PPC_INS_VSUBECUQ = 1858 -PPC_INS_VSUBEUQM = 1859 -PPC_INS_VSUBFP = 1860 -PPC_INS_VSUBSBS = 1861 -PPC_INS_VSUBSHS = 1862 -PPC_INS_VSUBSWS = 1863 -PPC_INS_VSUBUBM = 1864 -PPC_INS_VSUBUBS = 1865 -PPC_INS_VSUBUDM = 1866 -PPC_INS_VSUBUHM = 1867 -PPC_INS_VSUBUHS = 1868 -PPC_INS_VSUBUQM = 1869 -PPC_INS_VSUBUWM = 1870 -PPC_INS_VSUBUWS = 1871 -PPC_INS_VSUM2SWS = 1872 -PPC_INS_VSUM4SBS = 1873 -PPC_INS_VSUM4SHS = 1874 -PPC_INS_VSUM4UBS = 1875 -PPC_INS_VSUMSWS = 1876 -PPC_INS_VUPKHPX = 1877 -PPC_INS_VUPKHSB = 1878 -PPC_INS_VUPKHSH = 1879 -PPC_INS_VUPKHSW = 1880 -PPC_INS_VUPKLPX = 1881 -PPC_INS_VUPKLSB = 1882 -PPC_INS_VUPKLSH = 1883 -PPC_INS_VUPKLSW = 1884 -PPC_INS_VXOR = 1885 -PPC_INS_WAIT = 1886 -PPC_INS_WRTEE = 1887 -PPC_INS_WRTEEI = 1888 -PPC_INS_XOR = 1889 -PPC_INS_XORI = 1890 -PPC_INS_XORIS = 1891 -PPC_INS_XSABSDP = 1892 -PPC_INS_XSABSQP = 1893 -PPC_INS_XSADDDP = 1894 -PPC_INS_XSADDQP = 1895 -PPC_INS_XSADDQPO = 1896 -PPC_INS_XSADDSP = 1897 -PPC_INS_XSCMPEQDP = 1898 -PPC_INS_XSCMPEQQP = 1899 -PPC_INS_XSCMPEXPDP = 1900 -PPC_INS_XSCMPEXPQP = 1901 -PPC_INS_XSCMPGEDP = 1902 -PPC_INS_XSCMPGEQP = 1903 -PPC_INS_XSCMPGTDP = 1904 -PPC_INS_XSCMPGTQP = 1905 -PPC_INS_XSCMPODP = 1906 -PPC_INS_XSCMPOQP = 1907 -PPC_INS_XSCMPUDP = 1908 -PPC_INS_XSCMPUQP = 1909 -PPC_INS_XSCPSGNDP = 1910 -PPC_INS_XSCPSGNQP = 1911 -PPC_INS_XSCVDPHP = 1912 -PPC_INS_XSCVDPQP = 1913 -PPC_INS_XSCVDPSP = 1914 -PPC_INS_XSCVDPSPN = 1915 -PPC_INS_XSCVDPSXDS = 1916 -PPC_INS_XSCVDPSXWS = 1917 -PPC_INS_XSCVDPUXDS = 1918 -PPC_INS_XSCVDPUXWS = 1919 -PPC_INS_XSCVHPDP = 1920 -PPC_INS_XSCVQPDP = 1921 -PPC_INS_XSCVQPDPO = 1922 -PPC_INS_XSCVQPSDZ = 1923 -PPC_INS_XSCVQPSQZ = 1924 -PPC_INS_XSCVQPSWZ = 1925 -PPC_INS_XSCVQPUDZ = 1926 -PPC_INS_XSCVQPUQZ = 1927 -PPC_INS_XSCVQPUWZ = 1928 -PPC_INS_XSCVSDQP = 1929 -PPC_INS_XSCVSPDP = 1930 -PPC_INS_XSCVSPDPN = 1931 -PPC_INS_XSCVSQQP = 1932 -PPC_INS_XSCVSXDDP = 1933 -PPC_INS_XSCVSXDSP = 1934 -PPC_INS_XSCVUDQP = 1935 -PPC_INS_XSCVUQQP = 1936 -PPC_INS_XSCVUXDDP = 1937 -PPC_INS_XSCVUXDSP = 1938 -PPC_INS_XSDIVDP = 1939 -PPC_INS_XSDIVQP = 1940 -PPC_INS_XSDIVQPO = 1941 -PPC_INS_XSDIVSP = 1942 -PPC_INS_XSIEXPDP = 1943 -PPC_INS_XSIEXPQP = 1944 -PPC_INS_XSMADDADP = 1945 -PPC_INS_XSMADDASP = 1946 -PPC_INS_XSMADDMDP = 1947 -PPC_INS_XSMADDMSP = 1948 -PPC_INS_XSMADDQP = 1949 -PPC_INS_XSMADDQPO = 1950 -PPC_INS_XSMAXCDP = 1951 -PPC_INS_XSMAXCQP = 1952 -PPC_INS_XSMAXDP = 1953 -PPC_INS_XSMAXJDP = 1954 -PPC_INS_XSMINCDP = 1955 -PPC_INS_XSMINCQP = 1956 -PPC_INS_XSMINDP = 1957 -PPC_INS_XSMINJDP = 1958 -PPC_INS_XSMSUBADP = 1959 -PPC_INS_XSMSUBASP = 1960 -PPC_INS_XSMSUBMDP = 1961 -PPC_INS_XSMSUBMSP = 1962 -PPC_INS_XSMSUBQP = 1963 -PPC_INS_XSMSUBQPO = 1964 -PPC_INS_XSMULDP = 1965 -PPC_INS_XSMULQP = 1966 -PPC_INS_XSMULQPO = 1967 -PPC_INS_XSMULSP = 1968 -PPC_INS_XSNABSDP = 1969 -PPC_INS_XSNABSQP = 1970 -PPC_INS_XSNEGDP = 1971 -PPC_INS_XSNEGQP = 1972 -PPC_INS_XSNMADDADP = 1973 -PPC_INS_XSNMADDASP = 1974 -PPC_INS_XSNMADDMDP = 1975 -PPC_INS_XSNMADDMSP = 1976 -PPC_INS_XSNMADDQP = 1977 -PPC_INS_XSNMADDQPO = 1978 -PPC_INS_XSNMSUBADP = 1979 -PPC_INS_XSNMSUBASP = 1980 -PPC_INS_XSNMSUBMDP = 1981 -PPC_INS_XSNMSUBMSP = 1982 -PPC_INS_XSNMSUBQP = 1983 -PPC_INS_XSNMSUBQPO = 1984 -PPC_INS_XSRDPI = 1985 -PPC_INS_XSRDPIC = 1986 -PPC_INS_XSRDPIM = 1987 -PPC_INS_XSRDPIP = 1988 -PPC_INS_XSRDPIZ = 1989 -PPC_INS_XSREDP = 1990 -PPC_INS_XSRESP = 1991 -PPC_INS_XSRQPI = 1992 -PPC_INS_XSRQPIX = 1993 -PPC_INS_XSRQPXP = 1994 -PPC_INS_XSRSP = 1995 -PPC_INS_XSRSQRTEDP = 1996 -PPC_INS_XSRSQRTESP = 1997 -PPC_INS_XSSQRTDP = 1998 -PPC_INS_XSSQRTQP = 1999 -PPC_INS_XSSQRTQPO = 2000 -PPC_INS_XSSQRTSP = 2001 -PPC_INS_XSSUBDP = 2002 -PPC_INS_XSSUBQP = 2003 -PPC_INS_XSSUBQPO = 2004 -PPC_INS_XSSUBSP = 2005 -PPC_INS_XSTDIVDP = 2006 -PPC_INS_XSTSQRTDP = 2007 -PPC_INS_XSTSTDCDP = 2008 -PPC_INS_XSTSTDCQP = 2009 -PPC_INS_XSTSTDCSP = 2010 -PPC_INS_XSXEXPDP = 2011 -PPC_INS_XSXEXPQP = 2012 -PPC_INS_XSXSIGDP = 2013 -PPC_INS_XSXSIGQP = 2014 -PPC_INS_XVABSDP = 2015 -PPC_INS_XVABSSP = 2016 -PPC_INS_XVADDDP = 2017 -PPC_INS_XVADDSP = 2018 -PPC_INS_XVBF16GER2 = 2019 -PPC_INS_XVBF16GER2NN = 2020 -PPC_INS_XVBF16GER2NP = 2021 -PPC_INS_XVBF16GER2PN = 2022 -PPC_INS_XVBF16GER2PP = 2023 -PPC_INS_XVCMPEQDP = 2024 -PPC_INS_XVCMPEQSP = 2025 -PPC_INS_XVCMPGEDP = 2026 -PPC_INS_XVCMPGESP = 2027 -PPC_INS_XVCMPGTDP = 2028 -PPC_INS_XVCMPGTSP = 2029 -PPC_INS_XVCPSGNDP = 2030 -PPC_INS_XVCPSGNSP = 2031 -PPC_INS_XVCVBF16SPN = 2032 -PPC_INS_XVCVDPSP = 2033 -PPC_INS_XVCVDPSXDS = 2034 -PPC_INS_XVCVDPSXWS = 2035 -PPC_INS_XVCVDPUXDS = 2036 -PPC_INS_XVCVDPUXWS = 2037 -PPC_INS_XVCVHPSP = 2038 -PPC_INS_XVCVSPBF16 = 2039 -PPC_INS_XVCVSPDP = 2040 -PPC_INS_XVCVSPHP = 2041 -PPC_INS_XVCVSPSXDS = 2042 -PPC_INS_XVCVSPSXWS = 2043 -PPC_INS_XVCVSPUXDS = 2044 -PPC_INS_XVCVSPUXWS = 2045 -PPC_INS_XVCVSXDDP = 2046 -PPC_INS_XVCVSXDSP = 2047 -PPC_INS_XVCVSXWDP = 2048 -PPC_INS_XVCVSXWSP = 2049 -PPC_INS_XVCVUXDDP = 2050 -PPC_INS_XVCVUXDSP = 2051 -PPC_INS_XVCVUXWDP = 2052 -PPC_INS_XVCVUXWSP = 2053 -PPC_INS_XVDIVDP = 2054 -PPC_INS_XVDIVSP = 2055 -PPC_INS_XVF16GER2 = 2056 -PPC_INS_XVF16GER2NN = 2057 -PPC_INS_XVF16GER2NP = 2058 -PPC_INS_XVF16GER2PN = 2059 -PPC_INS_XVF16GER2PP = 2060 -PPC_INS_XVF32GER = 2061 -PPC_INS_XVF32GERNN = 2062 -PPC_INS_XVF32GERNP = 2063 -PPC_INS_XVF32GERPN = 2064 -PPC_INS_XVF32GERPP = 2065 -PPC_INS_XVF64GER = 2066 -PPC_INS_XVF64GERNN = 2067 -PPC_INS_XVF64GERNP = 2068 -PPC_INS_XVF64GERPN = 2069 -PPC_INS_XVF64GERPP = 2070 -PPC_INS_XVI16GER2 = 2071 -PPC_INS_XVI16GER2PP = 2072 -PPC_INS_XVI16GER2S = 2073 -PPC_INS_XVI16GER2SPP = 2074 -PPC_INS_XVI4GER8 = 2075 -PPC_INS_XVI4GER8PP = 2076 -PPC_INS_XVI8GER4 = 2077 -PPC_INS_XVI8GER4PP = 2078 -PPC_INS_XVI8GER4SPP = 2079 -PPC_INS_XVIEXPDP = 2080 -PPC_INS_XVIEXPSP = 2081 -PPC_INS_XVMADDADP = 2082 -PPC_INS_XVMADDASP = 2083 -PPC_INS_XVMADDMDP = 2084 -PPC_INS_XVMADDMSP = 2085 -PPC_INS_XVMAXDP = 2086 -PPC_INS_XVMAXSP = 2087 -PPC_INS_XVMINDP = 2088 -PPC_INS_XVMINSP = 2089 -PPC_INS_XVMSUBADP = 2090 -PPC_INS_XVMSUBASP = 2091 -PPC_INS_XVMSUBMDP = 2092 -PPC_INS_XVMSUBMSP = 2093 -PPC_INS_XVMULDP = 2094 -PPC_INS_XVMULSP = 2095 -PPC_INS_XVNABSDP = 2096 -PPC_INS_XVNABSSP = 2097 -PPC_INS_XVNEGDP = 2098 -PPC_INS_XVNEGSP = 2099 -PPC_INS_XVNMADDADP = 2100 -PPC_INS_XVNMADDASP = 2101 -PPC_INS_XVNMADDMDP = 2102 -PPC_INS_XVNMADDMSP = 2103 -PPC_INS_XVNMSUBADP = 2104 -PPC_INS_XVNMSUBASP = 2105 -PPC_INS_XVNMSUBMDP = 2106 -PPC_INS_XVNMSUBMSP = 2107 -PPC_INS_XVRDPI = 2108 -PPC_INS_XVRDPIC = 2109 -PPC_INS_XVRDPIM = 2110 -PPC_INS_XVRDPIP = 2111 -PPC_INS_XVRDPIZ = 2112 -PPC_INS_XVREDP = 2113 -PPC_INS_XVRESP = 2114 -PPC_INS_XVRSPI = 2115 -PPC_INS_XVRSPIC = 2116 -PPC_INS_XVRSPIM = 2117 -PPC_INS_XVRSPIP = 2118 -PPC_INS_XVRSPIZ = 2119 -PPC_INS_XVRSQRTEDP = 2120 -PPC_INS_XVRSQRTESP = 2121 -PPC_INS_XVSQRTDP = 2122 -PPC_INS_XVSQRTSP = 2123 -PPC_INS_XVSUBDP = 2124 -PPC_INS_XVSUBSP = 2125 -PPC_INS_XVTDIVDP = 2126 -PPC_INS_XVTDIVSP = 2127 -PPC_INS_XVTLSBB = 2128 -PPC_INS_XVTSQRTDP = 2129 -PPC_INS_XVTSQRTSP = 2130 -PPC_INS_XVTSTDCDP = 2131 -PPC_INS_XVTSTDCSP = 2132 -PPC_INS_XVXEXPDP = 2133 -PPC_INS_XVXEXPSP = 2134 -PPC_INS_XVXSIGDP = 2135 -PPC_INS_XVXSIGSP = 2136 -PPC_INS_XXBLENDVB = 2137 -PPC_INS_XXBLENDVD = 2138 -PPC_INS_XXBLENDVH = 2139 -PPC_INS_XXBLENDVW = 2140 -PPC_INS_XXBRD = 2141 -PPC_INS_XXBRH = 2142 -PPC_INS_XXBRQ = 2143 -PPC_INS_XXBRW = 2144 -PPC_INS_XXEVAL = 2145 -PPC_INS_XXEXTRACTUW = 2146 -PPC_INS_XXGENPCVBM = 2147 -PPC_INS_XXGENPCVDM = 2148 -PPC_INS_XXGENPCVHM = 2149 -PPC_INS_XXGENPCVWM = 2150 -PPC_INS_XXINSERTW = 2151 -PPC_INS_XXLAND = 2152 -PPC_INS_XXLANDC = 2153 -PPC_INS_XXLEQV = 2154 -PPC_INS_XXLNAND = 2155 -PPC_INS_XXLNOR = 2156 -PPC_INS_XXLOR = 2157 -PPC_INS_XXLORC = 2158 -PPC_INS_XXLXOR = 2159 -PPC_INS_XXMFACC = 2160 -PPC_INS_XXMRGHW = 2161 -PPC_INS_XXMRGLW = 2162 -PPC_INS_XXMTACC = 2163 -PPC_INS_XXPERM = 2164 -PPC_INS_XXPERMDI = 2165 -PPC_INS_XXPERMR = 2166 -PPC_INS_XXPERMX = 2167 -PPC_INS_XXSEL = 2168 -PPC_INS_XXSETACCZ = 2169 -PPC_INS_XXSLDWI = 2170 -PPC_INS_XXSPLTI32DX = 2171 -PPC_INS_XXSPLTIB = 2172 -PPC_INS_XXSPLTIDP = 2173 -PPC_INS_XXSPLTIW = 2174 -PPC_INS_XXSPLTW = 2175 -PPC_INS_BC = 2176 -PPC_INS_BCA = 2177 -PPC_INS_BCCTR = 2178 -PPC_INS_BCCTRL = 2179 -PPC_INS_BCL = 2180 -PPC_INS_BCLA = 2181 -PPC_INS_BCLR = 2182 -PPC_INS_BCLRL = 2183 -PPC_INS_ENDING = 2184 -PPC_INS_ALIAS_BEGIN = 2185 -PPC_INS_ALIAS_RFEBB = 2186 -PPC_INS_ALIAS_LI = 2187 -PPC_INS_ALIAS_LIS = 2188 -PPC_INS_ALIAS_MR = 2189 -PPC_INS_ALIAS_MR_ = 2190 -PPC_INS_ALIAS_NOT = 2191 -PPC_INS_ALIAS_NOT_ = 2192 -PPC_INS_ALIAS_NOP = 2193 -PPC_INS_ALIAS_MTUDSCR = 2194 -PPC_INS_ALIAS_MFUDSCR = 2195 -PPC_INS_ALIAS_MTVRSAVE = 2196 -PPC_INS_ALIAS_MFVRSAVE = 2197 -PPC_INS_ALIAS_MTCR = 2198 -PPC_INS_ALIAS_SUB = 2199 -PPC_INS_ALIAS_SUB_ = 2200 -PPC_INS_ALIAS_SUBC = 2201 -PPC_INS_ALIAS_SUBC_ = 2202 -PPC_INS_ALIAS_VMR = 2203 -PPC_INS_ALIAS_VNOT = 2204 -PPC_INS_ALIAS_ROTLWI = 2205 -PPC_INS_ALIAS_ROTLWI_ = 2206 -PPC_INS_ALIAS_ROTLW = 2207 -PPC_INS_ALIAS_ROTLW_ = 2208 -PPC_INS_ALIAS_CLRLWI = 2209 -PPC_INS_ALIAS_CLRLWI_ = 2210 -PPC_INS_ALIAS_ISELLT = 2211 -PPC_INS_ALIAS_ISELGT = 2212 -PPC_INS_ALIAS_ISELEQ = 2213 -PPC_INS_ALIAS_XNOP = 2214 -PPC_INS_ALIAS_CNTLZW = 2215 -PPC_INS_ALIAS_CNTLZW_ = 2216 -PPC_INS_ALIAS_MTXER = 2217 -PPC_INS_ALIAS_MFXER = 2218 -PPC_INS_ALIAS_MFRTCU = 2219 -PPC_INS_ALIAS_MFRTCL = 2220 -PPC_INS_ALIAS_MTLR = 2221 -PPC_INS_ALIAS_MFLR = 2222 -PPC_INS_ALIAS_MTCTR = 2223 -PPC_INS_ALIAS_MFCTR = 2224 -PPC_INS_ALIAS_MTUAMR = 2225 -PPC_INS_ALIAS_MFUAMR = 2226 -PPC_INS_ALIAS_MTDSCR = 2227 -PPC_INS_ALIAS_MFDSCR = 2228 -PPC_INS_ALIAS_MTDSISR = 2229 -PPC_INS_ALIAS_MFDSISR = 2230 -PPC_INS_ALIAS_MTDAR = 2231 -PPC_INS_ALIAS_MFDAR = 2232 -PPC_INS_ALIAS_MTDEC = 2233 -PPC_INS_ALIAS_MFDEC = 2234 -PPC_INS_ALIAS_MTSDR1 = 2235 -PPC_INS_ALIAS_MFSDR1 = 2236 -PPC_INS_ALIAS_MTSRR0 = 2237 -PPC_INS_ALIAS_MFSRR0 = 2238 -PPC_INS_ALIAS_MTSRR1 = 2239 -PPC_INS_ALIAS_MFSRR1 = 2240 -PPC_INS_ALIAS_MTCFAR = 2241 -PPC_INS_ALIAS_MFCFAR = 2242 -PPC_INS_ALIAS_MTAMR = 2243 -PPC_INS_ALIAS_MFAMR = 2244 -PPC_INS_ALIAS_MFSPRG = 2245 -PPC_INS_ALIAS_MFSPRG0 = 2246 -PPC_INS_ALIAS_MTSPRG = 2247 -PPC_INS_ALIAS_MTSPRG0 = 2248 -PPC_INS_ALIAS_MFSPRG1 = 2249 -PPC_INS_ALIAS_MTSPRG1 = 2250 -PPC_INS_ALIAS_MFSPRG2 = 2251 -PPC_INS_ALIAS_MTSPRG2 = 2252 -PPC_INS_ALIAS_MFSPRG3 = 2253 -PPC_INS_ALIAS_MTSPRG3 = 2254 -PPC_INS_ALIAS_MFASR = 2255 -PPC_INS_ALIAS_MTASR = 2256 -PPC_INS_ALIAS_MTTBL = 2257 -PPC_INS_ALIAS_MTTBU = 2258 -PPC_INS_ALIAS_MFPVR = 2259 -PPC_INS_ALIAS_MFSPEFSCR = 2260 -PPC_INS_ALIAS_MTSPEFSCR = 2261 -PPC_INS_ALIAS_XVMOVDP = 2262 -PPC_INS_ALIAS_XVMOVSP = 2263 -PPC_INS_ALIAS_XXSPLTD = 2264 -PPC_INS_ALIAS_XXMRGHD = 2265 -PPC_INS_ALIAS_XXMRGLD = 2266 -PPC_INS_ALIAS_XXSWAPD = 2267 -PPC_INS_ALIAS_MFFPRD = 2268 -PPC_INS_ALIAS_MTFPRD = 2269 -PPC_INS_ALIAS_MFFPRWZ = 2270 -PPC_INS_ALIAS_MTFPRWA = 2271 -PPC_INS_ALIAS_MTFPRWZ = 2272 -PPC_INS_ALIAS_TEND_ = 2273 -PPC_INS_ALIAS_TENDALL_ = 2274 -PPC_INS_ALIAS_TSUSPEND_ = 2275 -PPC_INS_ALIAS_TRESUME_ = 2276 -PPC_INS_ALIAS_DCI = 2277 -PPC_INS_ALIAS_DCCCI = 2278 -PPC_INS_ALIAS_ICI = 2279 -PPC_INS_ALIAS_ICCCI = 2280 -PPC_INS_ALIAS_MTFSFI = 2281 -PPC_INS_ALIAS_MTFSFI_ = 2282 -PPC_INS_ALIAS_MTFSF = 2283 -PPC_INS_ALIAS_MTFSF_ = 2284 -PPC_INS_ALIAS_SC = 2285 -PPC_INS_ALIAS_SYNC = 2286 -PPC_INS_ALIAS_LWSYNC = 2287 -PPC_INS_ALIAS_PTESYNC = 2288 -PPC_INS_ALIAS_WAIT = 2289 -PPC_INS_ALIAS_WAITRSV = 2290 -PPC_INS_ALIAS_WAITIMPL = 2291 -PPC_INS_ALIAS_MBAR = 2292 -PPC_INS_ALIAS_CRSET = 2293 -PPC_INS_ALIAS_CRCLR = 2294 -PPC_INS_ALIAS_CRMOVE = 2295 -PPC_INS_ALIAS_CRNOT = 2296 -PPC_INS_ALIAS_MFTB = 2297 -PPC_INS_ALIAS_MFTBL = 2298 -PPC_INS_ALIAS_MFTBU = 2299 -PPC_INS_ALIAS_MFBR0 = 2300 -PPC_INS_ALIAS_MTBR0 = 2301 -PPC_INS_ALIAS_MFBR1 = 2302 -PPC_INS_ALIAS_MTBR1 = 2303 -PPC_INS_ALIAS_MFBR2 = 2304 -PPC_INS_ALIAS_MTBR2 = 2305 -PPC_INS_ALIAS_MFBR3 = 2306 -PPC_INS_ALIAS_MTBR3 = 2307 -PPC_INS_ALIAS_MFBR4 = 2308 -PPC_INS_ALIAS_MTBR4 = 2309 -PPC_INS_ALIAS_MFBR5 = 2310 -PPC_INS_ALIAS_MTBR5 = 2311 -PPC_INS_ALIAS_MFBR6 = 2312 -PPC_INS_ALIAS_MTBR6 = 2313 -PPC_INS_ALIAS_MFBR7 = 2314 -PPC_INS_ALIAS_MTBR7 = 2315 -PPC_INS_ALIAS_MTMSRD = 2316 -PPC_INS_ALIAS_MTMSR = 2317 -PPC_INS_ALIAS_MTPID = 2318 -PPC_INS_ALIAS_MFPID = 2319 -PPC_INS_ALIAS_MFSPRG4 = 2320 -PPC_INS_ALIAS_MTSPRG4 = 2321 -PPC_INS_ALIAS_MFSPRG5 = 2322 -PPC_INS_ALIAS_MTSPRG5 = 2323 -PPC_INS_ALIAS_MFSPRG6 = 2324 -PPC_INS_ALIAS_MTSPRG6 = 2325 -PPC_INS_ALIAS_MFSPRG7 = 2326 -PPC_INS_ALIAS_MTSPRG7 = 2327 -PPC_INS_ALIAS_MTDBATU = 2328 -PPC_INS_ALIAS_MFDBATU = 2329 -PPC_INS_ALIAS_MTDBATL = 2330 -PPC_INS_ALIAS_MFDBATL = 2331 -PPC_INS_ALIAS_MTIBATU = 2332 -PPC_INS_ALIAS_MFIBATU = 2333 -PPC_INS_ALIAS_MTIBATL = 2334 -PPC_INS_ALIAS_MFIBATL = 2335 -PPC_INS_ALIAS_MTPPR = 2336 -PPC_INS_ALIAS_MFPPR = 2337 -PPC_INS_ALIAS_MTESR = 2338 -PPC_INS_ALIAS_MFESR = 2339 -PPC_INS_ALIAS_MTDEAR = 2340 -PPC_INS_ALIAS_MFDEAR = 2341 -PPC_INS_ALIAS_MTTCR = 2342 -PPC_INS_ALIAS_MFTCR = 2343 -PPC_INS_ALIAS_MFTBHI = 2344 -PPC_INS_ALIAS_MTTBHI = 2345 -PPC_INS_ALIAS_MFTBLO = 2346 -PPC_INS_ALIAS_MTTBLO = 2347 -PPC_INS_ALIAS_MTSRR2 = 2348 -PPC_INS_ALIAS_MFSRR2 = 2349 -PPC_INS_ALIAS_MTSRR3 = 2350 -PPC_INS_ALIAS_MFSRR3 = 2351 -PPC_INS_ALIAS_MTDCCR = 2352 -PPC_INS_ALIAS_MFDCCR = 2353 -PPC_INS_ALIAS_MTICCR = 2354 -PPC_INS_ALIAS_MFICCR = 2355 -PPC_INS_ALIAS_TLBIE = 2356 -PPC_INS_ALIAS_TLBREHI = 2357 -PPC_INS_ALIAS_TLBRELO = 2358 -PPC_INS_ALIAS_TLBWEHI = 2359 -PPC_INS_ALIAS_TLBWELO = 2360 -PPC_INS_ALIAS_ROTLDI = 2361 -PPC_INS_ALIAS_ROTLDI_ = 2362 -PPC_INS_ALIAS_ROTLD = 2363 -PPC_INS_ALIAS_ROTLD_ = 2364 -PPC_INS_ALIAS_CLRLDI = 2365 -PPC_INS_ALIAS_CLRLDI_ = 2366 -PPC_INS_ALIAS_LNIA = 2367 -PPC_INS_ALIAS_BCp = 2368 -PPC_INS_ALIAS_BCAp = 2369 -PPC_INS_ALIAS_BCLp = 2370 -PPC_INS_ALIAS_BCLAp = 2371 -PPC_INS_ALIAS_BCm = 2372 -PPC_INS_ALIAS_BCAm = 2373 -PPC_INS_ALIAS_BCLm = 2374 -PPC_INS_ALIAS_BCLAm = 2375 -PPC_INS_ALIAS_BT = 2376 -PPC_INS_ALIAS_BTA = 2377 -PPC_INS_ALIAS_BTLR = 2378 -PPC_INS_ALIAS_BTL = 2379 -PPC_INS_ALIAS_BTLA = 2380 -PPC_INS_ALIAS_BTLRL = 2381 -PPC_INS_ALIAS_BTCTR = 2382 -PPC_INS_ALIAS_BTCTRL = 2383 -PPC_INS_ALIAS_BDZLR = 2384 -PPC_INS_ALIAS_BDZLRL = 2385 -PPC_INS_ALIAS_BDZL = 2386 -PPC_INS_ALIAS_BDZLA = 2387 -PPC_INS_ALIAS_BDZ = 2388 -PPC_INS_ALIAS_BDNZL = 2389 -PPC_INS_ALIAS_BDNZLA = 2390 -PPC_INS_ALIAS_BDNZ = 2391 -PPC_INS_ALIAS_BDZLp = 2392 -PPC_INS_ALIAS_BDZLAp = 2393 -PPC_INS_ALIAS_BDZp = 2394 -PPC_INS_ALIAS_BDNZLp = 2395 -PPC_INS_ALIAS_BDNZLAp = 2396 -PPC_INS_ALIAS_BDNZp = 2397 -PPC_INS_ALIAS_BDZLm = 2398 -PPC_INS_ALIAS_BDZLAm = 2399 -PPC_INS_ALIAS_BDZm = 2400 -PPC_INS_ALIAS_BDNZLm = 2401 -PPC_INS_ALIAS_BDNZLAm = 2402 -PPC_INS_ALIAS_BDNZm = 2403 -PPC_INS_ALIAS_BDNZLR = 2404 -PPC_INS_ALIAS_BDNZLRL = 2405 -PPC_INS_ALIAS_BDZLRp = 2406 -PPC_INS_ALIAS_BDZLRLp = 2407 -PPC_INS_ALIAS_BDNZLRp = 2408 -PPC_INS_ALIAS_BDNZLRLp = 2409 -PPC_INS_ALIAS_BDZLRm = 2410 -PPC_INS_ALIAS_BDZLRLm = 2411 -PPC_INS_ALIAS_BDNZLRm = 2412 -PPC_INS_ALIAS_BDNZLRLm = 2413 -PPC_INS_ALIAS_BF = 2414 -PPC_INS_ALIAS_BFA = 2415 -PPC_INS_ALIAS_BFLR = 2416 -PPC_INS_ALIAS_BFL = 2417 -PPC_INS_ALIAS_BFLA = 2418 -PPC_INS_ALIAS_BFLRL = 2419 -PPC_INS_ALIAS_BFCTR = 2420 -PPC_INS_ALIAS_BFCTRL = 2421 -PPC_INS_ALIAS_BTm = 2422 -PPC_INS_ALIAS_BTAm = 2423 -PPC_INS_ALIAS_BTLRm = 2424 -PPC_INS_ALIAS_BTLm = 2425 -PPC_INS_ALIAS_BTLAm = 2426 -PPC_INS_ALIAS_BTLRLm = 2427 -PPC_INS_ALIAS_BTCTRm = 2428 -PPC_INS_ALIAS_BTCTRLm = 2429 -PPC_INS_ALIAS_BFm = 2430 -PPC_INS_ALIAS_BFAm = 2431 -PPC_INS_ALIAS_BFLRm = 2432 -PPC_INS_ALIAS_BFLm = 2433 -PPC_INS_ALIAS_BFLAm = 2434 -PPC_INS_ALIAS_BFLRLm = 2435 -PPC_INS_ALIAS_BFCTRm = 2436 -PPC_INS_ALIAS_BFCTRLm = 2437 -PPC_INS_ALIAS_BTp = 2438 -PPC_INS_ALIAS_BTAp = 2439 -PPC_INS_ALIAS_BTLRp = 2440 -PPC_INS_ALIAS_BTLp = 2441 -PPC_INS_ALIAS_BTLAp = 2442 -PPC_INS_ALIAS_BTLRLp = 2443 -PPC_INS_ALIAS_BTCTRp = 2444 -PPC_INS_ALIAS_BTCTRLp = 2445 -PPC_INS_ALIAS_BFp = 2446 -PPC_INS_ALIAS_BFAp = 2447 -PPC_INS_ALIAS_BFLRp = 2448 -PPC_INS_ALIAS_BFLp = 2449 -PPC_INS_ALIAS_BFLAp = 2450 -PPC_INS_ALIAS_BFLRLp = 2451 -PPC_INS_ALIAS_BFCTRp = 2452 -PPC_INS_ALIAS_BFCTRLp = 2453 -PPC_INS_ALIAS_BDNZT = 2454 -PPC_INS_ALIAS_BDNZTA = 2455 -PPC_INS_ALIAS_BDNZTLR = 2456 -PPC_INS_ALIAS_BDNZTL = 2457 -PPC_INS_ALIAS_BDNZTLA = 2458 -PPC_INS_ALIAS_BDNZTLRL = 2459 -PPC_INS_ALIAS_BDNZF = 2460 -PPC_INS_ALIAS_BDNZFA = 2461 -PPC_INS_ALIAS_BDNZFLR = 2462 -PPC_INS_ALIAS_BDNZFL = 2463 -PPC_INS_ALIAS_BDNZFLA = 2464 -PPC_INS_ALIAS_BDNZFLRL = 2465 -PPC_INS_ALIAS_BDZT = 2466 -PPC_INS_ALIAS_BDZTA = 2467 -PPC_INS_ALIAS_BDZTLR = 2468 -PPC_INS_ALIAS_BDZTL = 2469 -PPC_INS_ALIAS_BDZTLA = 2470 -PPC_INS_ALIAS_BDZTLRL = 2471 -PPC_INS_ALIAS_BDZF = 2472 -PPC_INS_ALIAS_BDZFA = 2473 -PPC_INS_ALIAS_BDZFLR = 2474 -PPC_INS_ALIAS_BDZFL = 2475 -PPC_INS_ALIAS_BDZFLA = 2476 -PPC_INS_ALIAS_BDZFLRL = 2477 -PPC_INS_ALIAS_B = 2478 -PPC_INS_ALIAS_BA = 2479 -PPC_INS_ALIAS_BL = 2480 -PPC_INS_ALIAS_BLA = 2481 -PPC_INS_ALIAS_BLR = 2482 -PPC_INS_ALIAS_BLRL = 2483 -PPC_INS_ALIAS_BCTR = 2484 -PPC_INS_ALIAS_BCTRL = 2485 -PPC_INS_ALIAS_BLT = 2486 -PPC_INS_ALIAS_BLTA = 2487 -PPC_INS_ALIAS_BLTLR = 2488 -PPC_INS_ALIAS_BLTCTR = 2489 -PPC_INS_ALIAS_BLTL = 2490 -PPC_INS_ALIAS_BLTLA = 2491 -PPC_INS_ALIAS_BLTLRL = 2492 -PPC_INS_ALIAS_BLTCTRL = 2493 -PPC_INS_ALIAS_BLTm = 2494 -PPC_INS_ALIAS_BLTAm = 2495 -PPC_INS_ALIAS_BLTLRm = 2496 -PPC_INS_ALIAS_BLTCTRm = 2497 -PPC_INS_ALIAS_BLTLm = 2498 -PPC_INS_ALIAS_BLTLAm = 2499 -PPC_INS_ALIAS_BLTLRLm = 2500 -PPC_INS_ALIAS_BLTCTRLm = 2501 -PPC_INS_ALIAS_BLTp = 2502 -PPC_INS_ALIAS_BLTAp = 2503 -PPC_INS_ALIAS_BLTLRp = 2504 -PPC_INS_ALIAS_BLTCTRp = 2505 -PPC_INS_ALIAS_BLTLp = 2506 -PPC_INS_ALIAS_BLTLAp = 2507 -PPC_INS_ALIAS_BLTLRLp = 2508 -PPC_INS_ALIAS_BLTCTRLp = 2509 -PPC_INS_ALIAS_BGT = 2510 -PPC_INS_ALIAS_BGTA = 2511 -PPC_INS_ALIAS_BGTLR = 2512 -PPC_INS_ALIAS_BGTCTR = 2513 -PPC_INS_ALIAS_BGTL = 2514 -PPC_INS_ALIAS_BGTLA = 2515 -PPC_INS_ALIAS_BGTLRL = 2516 -PPC_INS_ALIAS_BGTCTRL = 2517 -PPC_INS_ALIAS_BGTm = 2518 -PPC_INS_ALIAS_BGTAm = 2519 -PPC_INS_ALIAS_BGTLRm = 2520 -PPC_INS_ALIAS_BGTCTRm = 2521 -PPC_INS_ALIAS_BGTLm = 2522 -PPC_INS_ALIAS_BGTLAm = 2523 -PPC_INS_ALIAS_BGTLRLm = 2524 -PPC_INS_ALIAS_BGTCTRLm = 2525 -PPC_INS_ALIAS_BGTp = 2526 -PPC_INS_ALIAS_BGTAp = 2527 -PPC_INS_ALIAS_BGTLRp = 2528 -PPC_INS_ALIAS_BGTCTRp = 2529 -PPC_INS_ALIAS_BGTLp = 2530 -PPC_INS_ALIAS_BGTLAp = 2531 -PPC_INS_ALIAS_BGTLRLp = 2532 -PPC_INS_ALIAS_BGTCTRLp = 2533 -PPC_INS_ALIAS_BEQ = 2534 -PPC_INS_ALIAS_BEQA = 2535 -PPC_INS_ALIAS_BEQLR = 2536 -PPC_INS_ALIAS_BEQCTR = 2537 -PPC_INS_ALIAS_BEQL = 2538 -PPC_INS_ALIAS_BEQLA = 2539 -PPC_INS_ALIAS_BEQLRL = 2540 -PPC_INS_ALIAS_BEQCTRL = 2541 -PPC_INS_ALIAS_BEQm = 2542 -PPC_INS_ALIAS_BEQAm = 2543 -PPC_INS_ALIAS_BEQLRm = 2544 -PPC_INS_ALIAS_BEQCTRm = 2545 -PPC_INS_ALIAS_BEQLm = 2546 -PPC_INS_ALIAS_BEQLAm = 2547 -PPC_INS_ALIAS_BEQLRLm = 2548 -PPC_INS_ALIAS_BEQCTRLm = 2549 -PPC_INS_ALIAS_BEQp = 2550 -PPC_INS_ALIAS_BEQAp = 2551 -PPC_INS_ALIAS_BEQLRp = 2552 -PPC_INS_ALIAS_BEQCTRp = 2553 -PPC_INS_ALIAS_BEQLp = 2554 -PPC_INS_ALIAS_BEQLAp = 2555 -PPC_INS_ALIAS_BEQLRLp = 2556 -PPC_INS_ALIAS_BEQCTRLp = 2557 -PPC_INS_ALIAS_BUN = 2558 -PPC_INS_ALIAS_BUNA = 2559 -PPC_INS_ALIAS_BUNLR = 2560 -PPC_INS_ALIAS_BUNCTR = 2561 -PPC_INS_ALIAS_BUNL = 2562 -PPC_INS_ALIAS_BUNLA = 2563 -PPC_INS_ALIAS_BUNLRL = 2564 -PPC_INS_ALIAS_BUNCTRL = 2565 -PPC_INS_ALIAS_BUNm = 2566 -PPC_INS_ALIAS_BUNAm = 2567 -PPC_INS_ALIAS_BUNLRm = 2568 -PPC_INS_ALIAS_BUNCTRm = 2569 -PPC_INS_ALIAS_BUNLm = 2570 -PPC_INS_ALIAS_BUNLAm = 2571 -PPC_INS_ALIAS_BUNLRLm = 2572 -PPC_INS_ALIAS_BUNCTRLm = 2573 -PPC_INS_ALIAS_BUNp = 2574 -PPC_INS_ALIAS_BUNAp = 2575 -PPC_INS_ALIAS_BUNLRp = 2576 -PPC_INS_ALIAS_BUNCTRp = 2577 -PPC_INS_ALIAS_BUNLp = 2578 -PPC_INS_ALIAS_BUNLAp = 2579 -PPC_INS_ALIAS_BUNLRLp = 2580 -PPC_INS_ALIAS_BUNCTRLp = 2581 -PPC_INS_ALIAS_BSO = 2582 -PPC_INS_ALIAS_BSOA = 2583 -PPC_INS_ALIAS_BSOLR = 2584 -PPC_INS_ALIAS_BSOCTR = 2585 -PPC_INS_ALIAS_BSOL = 2586 -PPC_INS_ALIAS_BSOLA = 2587 -PPC_INS_ALIAS_BSOLRL = 2588 -PPC_INS_ALIAS_BSOCTRL = 2589 -PPC_INS_ALIAS_BSOm = 2590 -PPC_INS_ALIAS_BSOAm = 2591 -PPC_INS_ALIAS_BSOLRm = 2592 -PPC_INS_ALIAS_BSOCTRm = 2593 -PPC_INS_ALIAS_BSOLm = 2594 -PPC_INS_ALIAS_BSOLAm = 2595 -PPC_INS_ALIAS_BSOLRLm = 2596 -PPC_INS_ALIAS_BSOCTRLm = 2597 -PPC_INS_ALIAS_BSOp = 2598 -PPC_INS_ALIAS_BSOAp = 2599 -PPC_INS_ALIAS_BSOLRp = 2600 -PPC_INS_ALIAS_BSOCTRp = 2601 -PPC_INS_ALIAS_BSOLp = 2602 -PPC_INS_ALIAS_BSOLAp = 2603 -PPC_INS_ALIAS_BSOLRLp = 2604 -PPC_INS_ALIAS_BSOCTRLp = 2605 -PPC_INS_ALIAS_BGE = 2606 -PPC_INS_ALIAS_BGEA = 2607 -PPC_INS_ALIAS_BGELR = 2608 -PPC_INS_ALIAS_BGECTR = 2609 -PPC_INS_ALIAS_BGEL = 2610 -PPC_INS_ALIAS_BGELA = 2611 -PPC_INS_ALIAS_BGELRL = 2612 -PPC_INS_ALIAS_BGECTRL = 2613 -PPC_INS_ALIAS_BGEm = 2614 -PPC_INS_ALIAS_BGEAm = 2615 -PPC_INS_ALIAS_BGELRm = 2616 -PPC_INS_ALIAS_BGECTRm = 2617 -PPC_INS_ALIAS_BGELm = 2618 -PPC_INS_ALIAS_BGELAm = 2619 -PPC_INS_ALIAS_BGELRLm = 2620 -PPC_INS_ALIAS_BGECTRLm = 2621 -PPC_INS_ALIAS_BGEp = 2622 -PPC_INS_ALIAS_BGEAp = 2623 -PPC_INS_ALIAS_BGELRp = 2624 -PPC_INS_ALIAS_BGECTRp = 2625 -PPC_INS_ALIAS_BGELp = 2626 -PPC_INS_ALIAS_BGELAp = 2627 -PPC_INS_ALIAS_BGELRLp = 2628 -PPC_INS_ALIAS_BGECTRLp = 2629 -PPC_INS_ALIAS_BNL = 2630 -PPC_INS_ALIAS_BNLA = 2631 -PPC_INS_ALIAS_BNLLR = 2632 -PPC_INS_ALIAS_BNLCTR = 2633 -PPC_INS_ALIAS_BNLL = 2634 -PPC_INS_ALIAS_BNLLA = 2635 -PPC_INS_ALIAS_BNLLRL = 2636 -PPC_INS_ALIAS_BNLCTRL = 2637 -PPC_INS_ALIAS_BNLm = 2638 -PPC_INS_ALIAS_BNLAm = 2639 -PPC_INS_ALIAS_BNLLRm = 2640 -PPC_INS_ALIAS_BNLCTRm = 2641 -PPC_INS_ALIAS_BNLLm = 2642 -PPC_INS_ALIAS_BNLLAm = 2643 -PPC_INS_ALIAS_BNLLRLm = 2644 -PPC_INS_ALIAS_BNLCTRLm = 2645 -PPC_INS_ALIAS_BNLp = 2646 -PPC_INS_ALIAS_BNLAp = 2647 -PPC_INS_ALIAS_BNLLRp = 2648 -PPC_INS_ALIAS_BNLCTRp = 2649 -PPC_INS_ALIAS_BNLLp = 2650 -PPC_INS_ALIAS_BNLLAp = 2651 -PPC_INS_ALIAS_BNLLRLp = 2652 -PPC_INS_ALIAS_BNLCTRLp = 2653 -PPC_INS_ALIAS_BLE = 2654 -PPC_INS_ALIAS_BLEA = 2655 -PPC_INS_ALIAS_BLELR = 2656 -PPC_INS_ALIAS_BLECTR = 2657 -PPC_INS_ALIAS_BLEL = 2658 -PPC_INS_ALIAS_BLELA = 2659 -PPC_INS_ALIAS_BLELRL = 2660 -PPC_INS_ALIAS_BLECTRL = 2661 -PPC_INS_ALIAS_BLEm = 2662 -PPC_INS_ALIAS_BLEAm = 2663 -PPC_INS_ALIAS_BLELRm = 2664 -PPC_INS_ALIAS_BLECTRm = 2665 -PPC_INS_ALIAS_BLELm = 2666 -PPC_INS_ALIAS_BLELAm = 2667 -PPC_INS_ALIAS_BLELRLm = 2668 -PPC_INS_ALIAS_BLECTRLm = 2669 -PPC_INS_ALIAS_BLEp = 2670 -PPC_INS_ALIAS_BLEAp = 2671 -PPC_INS_ALIAS_BLELRp = 2672 -PPC_INS_ALIAS_BLECTRp = 2673 -PPC_INS_ALIAS_BLELp = 2674 -PPC_INS_ALIAS_BLELAp = 2675 -PPC_INS_ALIAS_BLELRLp = 2676 -PPC_INS_ALIAS_BLECTRLp = 2677 -PPC_INS_ALIAS_BNG = 2678 -PPC_INS_ALIAS_BNGA = 2679 -PPC_INS_ALIAS_BNGLR = 2680 -PPC_INS_ALIAS_BNGCTR = 2681 -PPC_INS_ALIAS_BNGL = 2682 -PPC_INS_ALIAS_BNGLA = 2683 -PPC_INS_ALIAS_BNGLRL = 2684 -PPC_INS_ALIAS_BNGCTRL = 2685 -PPC_INS_ALIAS_BNGm = 2686 -PPC_INS_ALIAS_BNGAm = 2687 -PPC_INS_ALIAS_BNGLRm = 2688 -PPC_INS_ALIAS_BNGCTRm = 2689 -PPC_INS_ALIAS_BNGLm = 2690 -PPC_INS_ALIAS_BNGLAm = 2691 -PPC_INS_ALIAS_BNGLRLm = 2692 -PPC_INS_ALIAS_BNGCTRLm = 2693 -PPC_INS_ALIAS_BNGp = 2694 -PPC_INS_ALIAS_BNGAp = 2695 -PPC_INS_ALIAS_BNGLRp = 2696 -PPC_INS_ALIAS_BNGCTRp = 2697 -PPC_INS_ALIAS_BNGLp = 2698 -PPC_INS_ALIAS_BNGLAp = 2699 -PPC_INS_ALIAS_BNGLRLp = 2700 -PPC_INS_ALIAS_BNGCTRLp = 2701 -PPC_INS_ALIAS_BNE = 2702 -PPC_INS_ALIAS_BNEA = 2703 -PPC_INS_ALIAS_BNELR = 2704 -PPC_INS_ALIAS_BNECTR = 2705 -PPC_INS_ALIAS_BNEL = 2706 -PPC_INS_ALIAS_BNELA = 2707 -PPC_INS_ALIAS_BNELRL = 2708 -PPC_INS_ALIAS_BNECTRL = 2709 -PPC_INS_ALIAS_BNEm = 2710 -PPC_INS_ALIAS_BNEAm = 2711 -PPC_INS_ALIAS_BNELRm = 2712 -PPC_INS_ALIAS_BNECTRm = 2713 -PPC_INS_ALIAS_BNELm = 2714 -PPC_INS_ALIAS_BNELAm = 2715 -PPC_INS_ALIAS_BNELRLm = 2716 -PPC_INS_ALIAS_BNECTRLm = 2717 -PPC_INS_ALIAS_BNEp = 2718 -PPC_INS_ALIAS_BNEAp = 2719 -PPC_INS_ALIAS_BNELRp = 2720 -PPC_INS_ALIAS_BNECTRp = 2721 -PPC_INS_ALIAS_BNELp = 2722 -PPC_INS_ALIAS_BNELAp = 2723 -PPC_INS_ALIAS_BNELRLp = 2724 -PPC_INS_ALIAS_BNECTRLp = 2725 -PPC_INS_ALIAS_BNU = 2726 -PPC_INS_ALIAS_BNUA = 2727 -PPC_INS_ALIAS_BNULR = 2728 -PPC_INS_ALIAS_BNUCTR = 2729 -PPC_INS_ALIAS_BNUL = 2730 -PPC_INS_ALIAS_BNULA = 2731 -PPC_INS_ALIAS_BNULRL = 2732 -PPC_INS_ALIAS_BNUCTRL = 2733 -PPC_INS_ALIAS_BNUm = 2734 -PPC_INS_ALIAS_BNUAm = 2735 -PPC_INS_ALIAS_BNULRm = 2736 -PPC_INS_ALIAS_BNUCTRm = 2737 -PPC_INS_ALIAS_BNULm = 2738 -PPC_INS_ALIAS_BNULAm = 2739 -PPC_INS_ALIAS_BNULRLm = 2740 -PPC_INS_ALIAS_BNUCTRLm = 2741 -PPC_INS_ALIAS_BNUp = 2742 -PPC_INS_ALIAS_BNUAp = 2743 -PPC_INS_ALIAS_BNULRp = 2744 -PPC_INS_ALIAS_BNUCTRp = 2745 -PPC_INS_ALIAS_BNULp = 2746 -PPC_INS_ALIAS_BNULAp = 2747 -PPC_INS_ALIAS_BNULRLp = 2748 -PPC_INS_ALIAS_BNUCTRLp = 2749 -PPC_INS_ALIAS_BNS = 2750 -PPC_INS_ALIAS_BNSA = 2751 -PPC_INS_ALIAS_BNSLR = 2752 -PPC_INS_ALIAS_BNSCTR = 2753 -PPC_INS_ALIAS_BNSL = 2754 -PPC_INS_ALIAS_BNSLA = 2755 -PPC_INS_ALIAS_BNSLRL = 2756 -PPC_INS_ALIAS_BNSCTRL = 2757 -PPC_INS_ALIAS_BNSm = 2758 -PPC_INS_ALIAS_BNSAm = 2759 -PPC_INS_ALIAS_BNSLRm = 2760 -PPC_INS_ALIAS_BNSCTRm = 2761 -PPC_INS_ALIAS_BNSLm = 2762 -PPC_INS_ALIAS_BNSLAm = 2763 -PPC_INS_ALIAS_BNSLRLm = 2764 -PPC_INS_ALIAS_BNSCTRLm = 2765 -PPC_INS_ALIAS_BNSp = 2766 -PPC_INS_ALIAS_BNSAp = 2767 -PPC_INS_ALIAS_BNSLRp = 2768 -PPC_INS_ALIAS_BNSCTRp = 2769 -PPC_INS_ALIAS_BNSLp = 2770 -PPC_INS_ALIAS_BNSLAp = 2771 -PPC_INS_ALIAS_BNSLRLp = 2772 -PPC_INS_ALIAS_BNSCTRLp = 2773 -PPC_INS_ALIAS_CMPWI = 2774 -PPC_INS_ALIAS_CMPW = 2775 -PPC_INS_ALIAS_CMPLWI = 2776 -PPC_INS_ALIAS_CMPLW = 2777 -PPC_INS_ALIAS_CMPDI = 2778 -PPC_INS_ALIAS_CMPD = 2779 -PPC_INS_ALIAS_CMPLDI = 2780 -PPC_INS_ALIAS_CMPLD = 2781 -PPC_INS_ALIAS_CMPI = 2782 -PPC_INS_ALIAS_CMP = 2783 -PPC_INS_ALIAS_CMPLI = 2784 -PPC_INS_ALIAS_CMPL = 2785 -PPC_INS_ALIAS_TRAP = 2786 -PPC_INS_ALIAS_TDLTI = 2787 -PPC_INS_ALIAS_TDLT = 2788 -PPC_INS_ALIAS_TWLTI = 2789 -PPC_INS_ALIAS_TWLT = 2790 -PPC_INS_ALIAS_TDLEI = 2791 -PPC_INS_ALIAS_TDLE = 2792 -PPC_INS_ALIAS_TWLEI = 2793 -PPC_INS_ALIAS_TWLE = 2794 -PPC_INS_ALIAS_TDEQI = 2795 -PPC_INS_ALIAS_TDEQ = 2796 -PPC_INS_ALIAS_TWEQI = 2797 -PPC_INS_ALIAS_TWEQ = 2798 -PPC_INS_ALIAS_TDGEI = 2799 -PPC_INS_ALIAS_TDGE = 2800 -PPC_INS_ALIAS_TWGEI = 2801 -PPC_INS_ALIAS_TWGE = 2802 -PPC_INS_ALIAS_TDGTI = 2803 -PPC_INS_ALIAS_TDGT = 2804 -PPC_INS_ALIAS_TWGTI = 2805 -PPC_INS_ALIAS_TWGT = 2806 -PPC_INS_ALIAS_TDNLI = 2807 -PPC_INS_ALIAS_TDNL = 2808 -PPC_INS_ALIAS_TWNLI = 2809 -PPC_INS_ALIAS_TWNL = 2810 -PPC_INS_ALIAS_TDNEI = 2811 -PPC_INS_ALIAS_TDNE = 2812 -PPC_INS_ALIAS_TWNEI = 2813 -PPC_INS_ALIAS_TWNE = 2814 -PPC_INS_ALIAS_TDNGI = 2815 -PPC_INS_ALIAS_TDNG = 2816 -PPC_INS_ALIAS_TWNGI = 2817 -PPC_INS_ALIAS_TWNG = 2818 -PPC_INS_ALIAS_TDLLTI = 2819 -PPC_INS_ALIAS_TDLLT = 2820 -PPC_INS_ALIAS_TWLLTI = 2821 -PPC_INS_ALIAS_TWLLT = 2822 -PPC_INS_ALIAS_TDLLEI = 2823 -PPC_INS_ALIAS_TDLLE = 2824 -PPC_INS_ALIAS_TWLLEI = 2825 -PPC_INS_ALIAS_TWLLE = 2826 -PPC_INS_ALIAS_TDLGEI = 2827 -PPC_INS_ALIAS_TDLGE = 2828 -PPC_INS_ALIAS_TWLGEI = 2829 -PPC_INS_ALIAS_TWLGE = 2830 -PPC_INS_ALIAS_TDLGTI = 2831 -PPC_INS_ALIAS_TDLGT = 2832 -PPC_INS_ALIAS_TWLGTI = 2833 -PPC_INS_ALIAS_TWLGT = 2834 -PPC_INS_ALIAS_TDLNLI = 2835 -PPC_INS_ALIAS_TDLNL = 2836 -PPC_INS_ALIAS_TWLNLI = 2837 -PPC_INS_ALIAS_TWLNL = 2838 -PPC_INS_ALIAS_TDLNGI = 2839 -PPC_INS_ALIAS_TDLNG = 2840 -PPC_INS_ALIAS_TWLNGI = 2841 -PPC_INS_ALIAS_TWLNG = 2842 -PPC_INS_ALIAS_TDUI = 2843 -PPC_INS_ALIAS_TDU = 2844 -PPC_INS_ALIAS_TWUI = 2845 -PPC_INS_ALIAS_TWU = 2846 -PPC_INS_ALIAS_PASTE_ = 2847 -PPC_INS_ALIAS_QVFCLR = 2848 -PPC_INS_ALIAS_QVFAND = 2849 -PPC_INS_ALIAS_QVFANDC = 2850 -PPC_INS_ALIAS_QVFCTFB = 2851 -PPC_INS_ALIAS_QVFXOR = 2852 -PPC_INS_ALIAS_QVFOR = 2853 -PPC_INS_ALIAS_QVFNOR = 2854 -PPC_INS_ALIAS_QVFEQU = 2855 -PPC_INS_ALIAS_QVFNOT = 2856 -PPC_INS_ALIAS_QVFORC = 2857 -PPC_INS_ALIAS_QVFNAND = 2858 -PPC_INS_ALIAS_QVFSET = 2859 -PPC_INS_ALIAS_SLWI = 2860 -PPC_INS_ALIAS_SRWI = 2861 -PPC_INS_ALIAS_SLDI = 2862 -PPC_INS_ALIAS_END = 2863 + +PPC_INS_INVALID = 0 +PPC_INS_CLRLSLDI = 1 +PPC_INS_CLRLSLWI = 2 +PPC_INS_CLRRDI = 3 +PPC_INS_CLRRWI = 4 +PPC_INS_DCBFL = 5 +PPC_INS_DCBFLP = 6 +PPC_INS_DCBFPS = 7 +PPC_INS_DCBF = 8 +PPC_INS_DCBSTPS = 9 +PPC_INS_DCBTCT = 10 +PPC_INS_DCBTDS = 11 +PPC_INS_DCBTSTCT = 12 +PPC_INS_DCBTSTDS = 13 +PPC_INS_DCBTSTT = 14 +PPC_INS_DCBTST = 15 +PPC_INS_DCBTT = 16 +PPC_INS_DCBT = 17 +PPC_INS_EXTLDI = 18 +PPC_INS_EXTLWI = 19 +PPC_INS_EXTRDI = 20 +PPC_INS_EXTRWI = 21 +PPC_INS_INSLWI = 22 +PPC_INS_INSRDI = 23 +PPC_INS_INSRWI = 24 +PPC_INS_LA = 25 +PPC_INS_RLWIMI = 26 +PPC_INS_RLWINM = 27 +PPC_INS_RLWNM = 28 +PPC_INS_ROTRDI = 29 +PPC_INS_ROTRWI = 30 +PPC_INS_SLDI = 31 +PPC_INS_SLWI = 32 +PPC_INS_SRDI = 33 +PPC_INS_SRWI = 34 +PPC_INS_SUBI = 35 +PPC_INS_SUBIC = 36 +PPC_INS_SUBIS = 37 +PPC_INS_SUBPCIS = 38 +PPC_INS_ADD = 39 +PPC_INS_ADDO = 40 +PPC_INS_ADDC = 41 +PPC_INS_ADDCO = 42 +PPC_INS_ADDE = 43 +PPC_INS_ADDEO = 44 +PPC_INS_ADDEX = 45 +PPC_INS_ADDI = 46 +PPC_INS_ADDIC = 47 +PPC_INS_ADDIS = 48 +PPC_INS_ADDME = 49 +PPC_INS_ADDMEO = 50 +PPC_INS_ADDPCIS = 51 +PPC_INS_ADDZE = 52 +PPC_INS_ADDZEO = 53 +PPC_INS_AND = 54 +PPC_INS_ANDC = 55 +PPC_INS_ANDIS = 56 +PPC_INS_ANDI = 57 +PPC_INS_ATTN = 58 +PPC_INS_B = 59 +PPC_INS_BA = 60 +PPC_INS_BCDADD = 61 +PPC_INS_BCDCFN = 62 +PPC_INS_BCDCFSQ = 63 +PPC_INS_BCDCFZ = 64 +PPC_INS_BCDCPSGN = 65 +PPC_INS_BCDCTN = 66 +PPC_INS_BCDCTSQ = 67 +PPC_INS_BCDCTZ = 68 +PPC_INS_BCDSETSGN = 69 +PPC_INS_BCDSR = 70 +PPC_INS_BCDSUB = 71 +PPC_INS_BCDS = 72 +PPC_INS_BCDTRUNC = 73 +PPC_INS_BCDUS = 74 +PPC_INS_BCDUTRUNC = 75 +PPC_INS_BCTR = 76 +PPC_INS_BCTRL = 77 +PPC_INS_BL = 78 +PPC_INS_BLA = 79 +PPC_INS_BLR = 80 +PPC_INS_BLRL = 81 +PPC_INS_BPERMD = 82 +PPC_INS_BRD = 83 +PPC_INS_BRH = 84 +PPC_INS_BRINC = 85 +PPC_INS_BRW = 86 +PPC_INS_CFUGED = 87 +PPC_INS_CLRBHRB = 88 +PPC_INS_CMPB = 89 +PPC_INS_CMPD = 90 +PPC_INS_CMPDI = 91 +PPC_INS_CMPEQB = 92 +PPC_INS_CMPLD = 93 +PPC_INS_CMPLDI = 94 +PPC_INS_CMPLW = 95 +PPC_INS_CMPLWI = 96 +PPC_INS_CMPRB = 97 +PPC_INS_CMPW = 98 +PPC_INS_CMPWI = 99 +PPC_INS_CNTLZD = 100 +PPC_INS_CNTLZDM = 101 +PPC_INS_CNTLZW = 102 +PPC_INS_CNTTZD = 103 +PPC_INS_CNTTZDM = 104 +PPC_INS_CNTTZW = 105 +PPC_INS_CPABORT = 106 +PPC_INS_COPY = 107 +PPC_INS_PASTE = 108 +PPC_INS_CRAND = 109 +PPC_INS_CRANDC = 110 +PPC_INS_CREQV = 111 +PPC_INS_CRNAND = 112 +PPC_INS_CRNOR = 113 +PPC_INS_CROR = 114 +PPC_INS_CRORC = 115 +PPC_INS_CRXOR = 116 +PPC_INS_DARN = 117 +PPC_INS_DCBA = 118 +PPC_INS_DCBFEP = 119 +PPC_INS_DCBI = 120 +PPC_INS_DCBST = 121 +PPC_INS_DCBSTEP = 122 +PPC_INS_DCBTEP = 123 +PPC_INS_DCBTSTEP = 124 +PPC_INS_DCBZ = 125 +PPC_INS_DCBZEP = 126 +PPC_INS_DCBZL = 127 +PPC_INS_DCBZLEP = 128 +PPC_INS_DCCCI = 129 +PPC_INS_DIVD = 130 +PPC_INS_DIVDE = 131 +PPC_INS_DIVDEO = 132 +PPC_INS_DIVDEU = 133 +PPC_INS_DIVDEUO = 134 +PPC_INS_DIVDO = 135 +PPC_INS_DIVDU = 136 +PPC_INS_DIVDUO = 137 +PPC_INS_DIVW = 138 +PPC_INS_DIVWE = 139 +PPC_INS_DIVWEO = 140 +PPC_INS_DIVWEU = 141 +PPC_INS_DIVWEUO = 142 +PPC_INS_DIVWO = 143 +PPC_INS_DIVWU = 144 +PPC_INS_DIVWUO = 145 +PPC_INS_DMMR = 146 +PPC_INS_DMSETDMRZ = 147 +PPC_INS_DMXOR = 148 +PPC_INS_DMXXEXTFDMR256 = 149 +PPC_INS_DMXXEXTFDMR512 = 150 +PPC_INS_DMXXINSTFDMR256 = 151 +PPC_INS_DMXXINSTFDMR512 = 152 +PPC_INS_DSS = 153 +PPC_INS_DSSALL = 154 +PPC_INS_DST = 155 +PPC_INS_DSTST = 156 +PPC_INS_DSTSTT = 157 +PPC_INS_DSTT = 158 +PPC_INS_EFDABS = 159 +PPC_INS_EFDADD = 160 +PPC_INS_EFDCFS = 161 +PPC_INS_EFDCFSF = 162 +PPC_INS_EFDCFSI = 163 +PPC_INS_EFDCFSID = 164 +PPC_INS_EFDCFUF = 165 +PPC_INS_EFDCFUI = 166 +PPC_INS_EFDCFUID = 167 +PPC_INS_EFDCMPEQ = 168 +PPC_INS_EFDCMPGT = 169 +PPC_INS_EFDCMPLT = 170 +PPC_INS_EFDCTSF = 171 +PPC_INS_EFDCTSI = 172 +PPC_INS_EFDCTSIDZ = 173 +PPC_INS_EFDCTSIZ = 174 +PPC_INS_EFDCTUF = 175 +PPC_INS_EFDCTUI = 176 +PPC_INS_EFDCTUIDZ = 177 +PPC_INS_EFDCTUIZ = 178 +PPC_INS_EFDDIV = 179 +PPC_INS_EFDMUL = 180 +PPC_INS_EFDNABS = 181 +PPC_INS_EFDNEG = 182 +PPC_INS_EFDSUB = 183 +PPC_INS_EFDTSTEQ = 184 +PPC_INS_EFDTSTGT = 185 +PPC_INS_EFDTSTLT = 186 +PPC_INS_EFSABS = 187 +PPC_INS_EFSADD = 188 +PPC_INS_EFSCFD = 189 +PPC_INS_EFSCFSF = 190 +PPC_INS_EFSCFSI = 191 +PPC_INS_EFSCFUF = 192 +PPC_INS_EFSCFUI = 193 +PPC_INS_EFSCMPEQ = 194 +PPC_INS_EFSCMPGT = 195 +PPC_INS_EFSCMPLT = 196 +PPC_INS_EFSCTSF = 197 +PPC_INS_EFSCTSI = 198 +PPC_INS_EFSCTSIZ = 199 +PPC_INS_EFSCTUF = 200 +PPC_INS_EFSCTUI = 201 +PPC_INS_EFSCTUIZ = 202 +PPC_INS_EFSDIV = 203 +PPC_INS_EFSMUL = 204 +PPC_INS_EFSNABS = 205 +PPC_INS_EFSNEG = 206 +PPC_INS_EFSSUB = 207 +PPC_INS_EFSTSTEQ = 208 +PPC_INS_EFSTSTGT = 209 +PPC_INS_EFSTSTLT = 210 +PPC_INS_EQV = 211 +PPC_INS_EVABS = 212 +PPC_INS_EVADDIW = 213 +PPC_INS_EVADDSMIAAW = 214 +PPC_INS_EVADDSSIAAW = 215 +PPC_INS_EVADDUMIAAW = 216 +PPC_INS_EVADDUSIAAW = 217 +PPC_INS_EVADDW = 218 +PPC_INS_EVAND = 219 +PPC_INS_EVANDC = 220 +PPC_INS_EVCMPEQ = 221 +PPC_INS_EVCMPGTS = 222 +PPC_INS_EVCMPGTU = 223 +PPC_INS_EVCMPLTS = 224 +PPC_INS_EVCMPLTU = 225 +PPC_INS_EVCNTLSW = 226 +PPC_INS_EVCNTLZW = 227 +PPC_INS_EVDIVWS = 228 +PPC_INS_EVDIVWU = 229 +PPC_INS_EVEQV = 230 +PPC_INS_EVEXTSB = 231 +PPC_INS_EVEXTSH = 232 +PPC_INS_EVFSABS = 233 +PPC_INS_EVFSADD = 234 +PPC_INS_EVFSCFSF = 235 +PPC_INS_EVFSCFSI = 236 +PPC_INS_EVFSCFUF = 237 +PPC_INS_EVFSCFUI = 238 +PPC_INS_EVFSCMPEQ = 239 +PPC_INS_EVFSCMPGT = 240 +PPC_INS_EVFSCMPLT = 241 +PPC_INS_EVFSCTSF = 242 +PPC_INS_EVFSCTSI = 243 +PPC_INS_EVFSCTSIZ = 244 +PPC_INS_EVFSCTUI = 245 +PPC_INS_EVFSDIV = 246 +PPC_INS_EVFSMUL = 247 +PPC_INS_EVFSNABS = 248 +PPC_INS_EVFSNEG = 249 +PPC_INS_EVFSSUB = 250 +PPC_INS_EVFSTSTEQ = 251 +PPC_INS_EVFSTSTGT = 252 +PPC_INS_EVFSTSTLT = 253 +PPC_INS_EVLDD = 254 +PPC_INS_EVLDDX = 255 +PPC_INS_EVLDH = 256 +PPC_INS_EVLDHX = 257 +PPC_INS_EVLDW = 258 +PPC_INS_EVLDWX = 259 +PPC_INS_EVLHHESPLAT = 260 +PPC_INS_EVLHHESPLATX = 261 +PPC_INS_EVLHHOSSPLAT = 262 +PPC_INS_EVLHHOSSPLATX = 263 +PPC_INS_EVLHHOUSPLAT = 264 +PPC_INS_EVLHHOUSPLATX = 265 +PPC_INS_EVLWHE = 266 +PPC_INS_EVLWHEX = 267 +PPC_INS_EVLWHOS = 268 +PPC_INS_EVLWHOSX = 269 +PPC_INS_EVLWHOU = 270 +PPC_INS_EVLWHOUX = 271 +PPC_INS_EVLWHSPLAT = 272 +PPC_INS_EVLWHSPLATX = 273 +PPC_INS_EVLWWSPLAT = 274 +PPC_INS_EVLWWSPLATX = 275 +PPC_INS_EVMERGEHI = 276 +PPC_INS_EVMERGEHILO = 277 +PPC_INS_EVMERGELO = 278 +PPC_INS_EVMERGELOHI = 279 +PPC_INS_EVMHEGSMFAA = 280 +PPC_INS_EVMHEGSMFAN = 281 +PPC_INS_EVMHEGSMIAA = 282 +PPC_INS_EVMHEGSMIAN = 283 +PPC_INS_EVMHEGUMIAA = 284 +PPC_INS_EVMHEGUMIAN = 285 +PPC_INS_EVMHESMF = 286 +PPC_INS_EVMHESMFA = 287 +PPC_INS_EVMHESMFAAW = 288 +PPC_INS_EVMHESMFANW = 289 +PPC_INS_EVMHESMI = 290 +PPC_INS_EVMHESMIA = 291 +PPC_INS_EVMHESMIAAW = 292 +PPC_INS_EVMHESMIANW = 293 +PPC_INS_EVMHESSF = 294 +PPC_INS_EVMHESSFA = 295 +PPC_INS_EVMHESSFAAW = 296 +PPC_INS_EVMHESSFANW = 297 +PPC_INS_EVMHESSIAAW = 298 +PPC_INS_EVMHESSIANW = 299 +PPC_INS_EVMHEUMI = 300 +PPC_INS_EVMHEUMIA = 301 +PPC_INS_EVMHEUMIAAW = 302 +PPC_INS_EVMHEUMIANW = 303 +PPC_INS_EVMHEUSIAAW = 304 +PPC_INS_EVMHEUSIANW = 305 +PPC_INS_EVMHOGSMFAA = 306 +PPC_INS_EVMHOGSMFAN = 307 +PPC_INS_EVMHOGSMIAA = 308 +PPC_INS_EVMHOGSMIAN = 309 +PPC_INS_EVMHOGUMIAA = 310 +PPC_INS_EVMHOGUMIAN = 311 +PPC_INS_EVMHOSMF = 312 +PPC_INS_EVMHOSMFA = 313 +PPC_INS_EVMHOSMFAAW = 314 +PPC_INS_EVMHOSMFANW = 315 +PPC_INS_EVMHOSMI = 316 +PPC_INS_EVMHOSMIA = 317 +PPC_INS_EVMHOSMIAAW = 318 +PPC_INS_EVMHOSMIANW = 319 +PPC_INS_EVMHOSSF = 320 +PPC_INS_EVMHOSSFA = 321 +PPC_INS_EVMHOSSFAAW = 322 +PPC_INS_EVMHOSSFANW = 323 +PPC_INS_EVMHOSSIAAW = 324 +PPC_INS_EVMHOSSIANW = 325 +PPC_INS_EVMHOUMI = 326 +PPC_INS_EVMHOUMIA = 327 +PPC_INS_EVMHOUMIAAW = 328 +PPC_INS_EVMHOUMIANW = 329 +PPC_INS_EVMHOUSIAAW = 330 +PPC_INS_EVMHOUSIANW = 331 +PPC_INS_EVMRA = 332 +PPC_INS_EVMWHSMF = 333 +PPC_INS_EVMWHSMFA = 334 +PPC_INS_EVMWHSMI = 335 +PPC_INS_EVMWHSMIA = 336 +PPC_INS_EVMWHSSF = 337 +PPC_INS_EVMWHSSFA = 338 +PPC_INS_EVMWHUMI = 339 +PPC_INS_EVMWHUMIA = 340 +PPC_INS_EVMWLSMIAAW = 341 +PPC_INS_EVMWLSMIANW = 342 +PPC_INS_EVMWLSSIAAW = 343 +PPC_INS_EVMWLSSIANW = 344 +PPC_INS_EVMWLUMI = 345 +PPC_INS_EVMWLUMIA = 346 +PPC_INS_EVMWLUMIAAW = 347 +PPC_INS_EVMWLUMIANW = 348 +PPC_INS_EVMWLUSIAAW = 349 +PPC_INS_EVMWLUSIANW = 350 +PPC_INS_EVMWSMF = 351 +PPC_INS_EVMWSMFA = 352 +PPC_INS_EVMWSMFAA = 353 +PPC_INS_EVMWSMFAN = 354 +PPC_INS_EVMWSMI = 355 +PPC_INS_EVMWSMIA = 356 +PPC_INS_EVMWSMIAA = 357 +PPC_INS_EVMWSMIAN = 358 +PPC_INS_EVMWSSF = 359 +PPC_INS_EVMWSSFA = 360 +PPC_INS_EVMWSSFAA = 361 +PPC_INS_EVMWSSFAN = 362 +PPC_INS_EVMWUMI = 363 +PPC_INS_EVMWUMIA = 364 +PPC_INS_EVMWUMIAA = 365 +PPC_INS_EVMWUMIAN = 366 +PPC_INS_EVNAND = 367 +PPC_INS_EVNEG = 368 +PPC_INS_EVNOR = 369 +PPC_INS_EVOR = 370 +PPC_INS_EVORC = 371 +PPC_INS_EVRLW = 372 +PPC_INS_EVRLWI = 373 +PPC_INS_EVRNDW = 374 +PPC_INS_EVSEL = 375 +PPC_INS_EVSLW = 376 +PPC_INS_EVSLWI = 377 +PPC_INS_EVSPLATFI = 378 +PPC_INS_EVSPLATI = 379 +PPC_INS_EVSRWIS = 380 +PPC_INS_EVSRWIU = 381 +PPC_INS_EVSRWS = 382 +PPC_INS_EVSRWU = 383 +PPC_INS_EVSTDD = 384 +PPC_INS_EVSTDDX = 385 +PPC_INS_EVSTDH = 386 +PPC_INS_EVSTDHX = 387 +PPC_INS_EVSTDW = 388 +PPC_INS_EVSTDWX = 389 +PPC_INS_EVSTWHE = 390 +PPC_INS_EVSTWHEX = 391 +PPC_INS_EVSTWHO = 392 +PPC_INS_EVSTWHOX = 393 +PPC_INS_EVSTWWE = 394 +PPC_INS_EVSTWWEX = 395 +PPC_INS_EVSTWWO = 396 +PPC_INS_EVSTWWOX = 397 +PPC_INS_EVSUBFSMIAAW = 398 +PPC_INS_EVSUBFSSIAAW = 399 +PPC_INS_EVSUBFUMIAAW = 400 +PPC_INS_EVSUBFUSIAAW = 401 +PPC_INS_EVSUBFW = 402 +PPC_INS_EVSUBIFW = 403 +PPC_INS_EVXOR = 404 +PPC_INS_EXTSB = 405 +PPC_INS_EXTSH = 406 +PPC_INS_EXTSW = 407 +PPC_INS_EXTSWSLI = 408 +PPC_INS_EIEIO = 409 +PPC_INS_FABS = 410 +PPC_INS_FADD = 411 +PPC_INS_FADDS = 412 +PPC_INS_FCFID = 413 +PPC_INS_FCFIDS = 414 +PPC_INS_FCFIDU = 415 +PPC_INS_FCFIDUS = 416 +PPC_INS_FCMPO = 417 +PPC_INS_FCMPU = 418 +PPC_INS_FCPSGN = 419 +PPC_INS_FCTID = 420 +PPC_INS_FCTIDU = 421 +PPC_INS_FCTIDUZ = 422 +PPC_INS_FCTIDZ = 423 +PPC_INS_FCTIW = 424 +PPC_INS_FCTIWU = 425 +PPC_INS_FCTIWUZ = 426 +PPC_INS_FCTIWZ = 427 +PPC_INS_FDIV = 428 +PPC_INS_FDIVS = 429 +PPC_INS_FMADD = 430 +PPC_INS_FMADDS = 431 +PPC_INS_FMR = 432 +PPC_INS_FMSUB = 433 +PPC_INS_FMSUBS = 434 +PPC_INS_FMUL = 435 +PPC_INS_FMULS = 436 +PPC_INS_FNABS = 437 +PPC_INS_FNEG = 438 +PPC_INS_FNMADD = 439 +PPC_INS_FNMADDS = 440 +PPC_INS_FNMSUB = 441 +PPC_INS_FNMSUBS = 442 +PPC_INS_FRE = 443 +PPC_INS_FRES = 444 +PPC_INS_FRIM = 445 +PPC_INS_FRIN = 446 +PPC_INS_FRIP = 447 +PPC_INS_FRIZ = 448 +PPC_INS_FRSP = 449 +PPC_INS_FRSQRTE = 450 +PPC_INS_FRSQRTES = 451 +PPC_INS_FSEL = 452 +PPC_INS_FSQRT = 453 +PPC_INS_FSQRTS = 454 +PPC_INS_FSUB = 455 +PPC_INS_FSUBS = 456 +PPC_INS_FTDIV = 457 +PPC_INS_FTSQRT = 458 +PPC_INS_HASHCHK = 459 +PPC_INS_HASHCHKP = 460 +PPC_INS_HASHST = 461 +PPC_INS_HASHSTP = 462 +PPC_INS_HRFID = 463 +PPC_INS_ICBI = 464 +PPC_INS_ICBIEP = 465 +PPC_INS_ICBLC = 466 +PPC_INS_ICBLQ = 467 +PPC_INS_ICBT = 468 +PPC_INS_ICBTLS = 469 +PPC_INS_ICCCI = 470 +PPC_INS_ISEL = 471 +PPC_INS_ISYNC = 472 +PPC_INS_LBARX = 473 +PPC_INS_LBEPX = 474 +PPC_INS_LBZ = 475 +PPC_INS_LBZCIX = 476 +PPC_INS_LBZU = 477 +PPC_INS_LBZUX = 478 +PPC_INS_LBZX = 479 +PPC_INS_LD = 480 +PPC_INS_LDARX = 481 +PPC_INS_LDAT = 482 +PPC_INS_LDBRX = 483 +PPC_INS_LDCIX = 484 +PPC_INS_LDU = 485 +PPC_INS_LDUX = 486 +PPC_INS_LDX = 487 +PPC_INS_LFD = 488 +PPC_INS_LFDEPX = 489 +PPC_INS_LFDU = 490 +PPC_INS_LFDUX = 491 +PPC_INS_LFDX = 492 +PPC_INS_LFIWAX = 493 +PPC_INS_LFIWZX = 494 +PPC_INS_LFS = 495 +PPC_INS_LFSU = 496 +PPC_INS_LFSUX = 497 +PPC_INS_LFSX = 498 +PPC_INS_LHA = 499 +PPC_INS_LHARX = 500 +PPC_INS_LHAU = 501 +PPC_INS_LHAUX = 502 +PPC_INS_LHAX = 503 +PPC_INS_LHBRX = 504 +PPC_INS_LHEPX = 505 +PPC_INS_LHZ = 506 +PPC_INS_LHZCIX = 507 +PPC_INS_LHZU = 508 +PPC_INS_LHZUX = 509 +PPC_INS_LHZX = 510 +PPC_INS_LMW = 511 +PPC_INS_LQ = 512 +PPC_INS_LQARX = 513 +PPC_INS_LSWI = 514 +PPC_INS_LVEBX = 515 +PPC_INS_LVEHX = 516 +PPC_INS_LVEWX = 517 +PPC_INS_LVSL = 518 +PPC_INS_LVSR = 519 +PPC_INS_LVX = 520 +PPC_INS_LVXL = 521 +PPC_INS_LWA = 522 +PPC_INS_LWARX = 523 +PPC_INS_LWAT = 524 +PPC_INS_LWAUX = 525 +PPC_INS_LWAX = 526 +PPC_INS_LWBRX = 527 +PPC_INS_LWEPX = 528 +PPC_INS_LWZ = 529 +PPC_INS_LWZCIX = 530 +PPC_INS_LWZU = 531 +PPC_INS_LWZUX = 532 +PPC_INS_LWZX = 533 +PPC_INS_LXSD = 534 +PPC_INS_LXSDX = 535 +PPC_INS_LXSIBZX = 536 +PPC_INS_LXSIHZX = 537 +PPC_INS_LXSIWAX = 538 +PPC_INS_LXSIWZX = 539 +PPC_INS_LXSSP = 540 +PPC_INS_LXSSPX = 541 +PPC_INS_LXV = 542 +PPC_INS_LXVB16X = 543 +PPC_INS_LXVD2X = 544 +PPC_INS_LXVDSX = 545 +PPC_INS_LXVH8X = 546 +PPC_INS_LXVKQ = 547 +PPC_INS_LXVL = 548 +PPC_INS_LXVLL = 549 +PPC_INS_LXVP = 550 +PPC_INS_LXVPRL = 551 +PPC_INS_LXVPRLL = 552 +PPC_INS_LXVPX = 553 +PPC_INS_LXVRBX = 554 +PPC_INS_LXVRDX = 555 +PPC_INS_LXVRHX = 556 +PPC_INS_LXVRL = 557 +PPC_INS_LXVRLL = 558 +PPC_INS_LXVRWX = 559 +PPC_INS_LXVW4X = 560 +PPC_INS_LXVWSX = 561 +PPC_INS_LXVX = 562 +PPC_INS_MADDHD = 563 +PPC_INS_MADDHDU = 564 +PPC_INS_MADDLD = 565 +PPC_INS_MBAR = 566 +PPC_INS_MCRF = 567 +PPC_INS_MCRFS = 568 +PPC_INS_MCRXRX = 569 +PPC_INS_MFBHRBE = 570 +PPC_INS_MFCR = 571 +PPC_INS_MFCTR = 572 +PPC_INS_MFDCR = 573 +PPC_INS_MFFS = 574 +PPC_INS_MFFSCDRN = 575 +PPC_INS_MFFSCDRNI = 576 +PPC_INS_MFFSCE = 577 +PPC_INS_MFFSCRN = 578 +PPC_INS_MFFSCRNI = 579 +PPC_INS_MFFSL = 580 +PPC_INS_MFLR = 581 +PPC_INS_MFMSR = 582 +PPC_INS_MFOCRF = 583 +PPC_INS_MFPMR = 584 +PPC_INS_MFSPR = 585 +PPC_INS_MFSR = 586 +PPC_INS_MFSRIN = 587 +PPC_INS_MFTB = 588 +PPC_INS_MFVSCR = 589 +PPC_INS_MFVSRD = 590 +PPC_INS_MFVSRLD = 591 +PPC_INS_MFVSRWZ = 592 +PPC_INS_MODSD = 593 +PPC_INS_MODSW = 594 +PPC_INS_MODUD = 595 +PPC_INS_MODUW = 596 +PPC_INS_MSGSYNC = 597 +PPC_INS_MTCRF = 598 +PPC_INS_MTCTR = 599 +PPC_INS_MTDCR = 600 +PPC_INS_MTFSB0 = 601 +PPC_INS_MTFSB1 = 602 +PPC_INS_MTFSF = 603 +PPC_INS_MTFSFI = 604 +PPC_INS_MTLR = 605 +PPC_INS_MTMSR = 606 +PPC_INS_MTMSRD = 607 +PPC_INS_MTOCRF = 608 +PPC_INS_MTPMR = 609 +PPC_INS_MTSPR = 610 +PPC_INS_MTSR = 611 +PPC_INS_MTSRIN = 612 +PPC_INS_MTVSCR = 613 +PPC_INS_MTVSRBM = 614 +PPC_INS_MTVSRBMI = 615 +PPC_INS_MTVSRD = 616 +PPC_INS_MTVSRDD = 617 +PPC_INS_MTVSRDM = 618 +PPC_INS_MTVSRHM = 619 +PPC_INS_MTVSRQM = 620 +PPC_INS_MTVSRWA = 621 +PPC_INS_MTVSRWM = 622 +PPC_INS_MTVSRWS = 623 +PPC_INS_MTVSRWZ = 624 +PPC_INS_MULHD = 625 +PPC_INS_MULHDU = 626 +PPC_INS_MULHW = 627 +PPC_INS_MULHWU = 628 +PPC_INS_MULLD = 629 +PPC_INS_MULLDO = 630 +PPC_INS_MULLI = 631 +PPC_INS_MULLW = 632 +PPC_INS_MULLWO = 633 +PPC_INS_NAND = 634 +PPC_INS_NAP = 635 +PPC_INS_NEG = 636 +PPC_INS_NEGO = 637 +PPC_INS_NOP = 638 +PPC_INS_NOR = 639 +PPC_INS_OR = 640 +PPC_INS_ORC = 641 +PPC_INS_ORI = 642 +PPC_INS_ORIS = 643 +PPC_INS_PADDI = 644 +PPC_INS_PDEPD = 645 +PPC_INS_PEXTD = 646 +PPC_INS_PLBZ = 647 +PPC_INS_PLD = 648 +PPC_INS_PLFD = 649 +PPC_INS_PLFS = 650 +PPC_INS_PLHA = 651 +PPC_INS_PLHZ = 652 +PPC_INS_PLI = 653 +PPC_INS_PLWA = 654 +PPC_INS_PLWZ = 655 +PPC_INS_PLXSD = 656 +PPC_INS_PLXSSP = 657 +PPC_INS_PLXV = 658 +PPC_INS_PLXVP = 659 +PPC_INS_PMXVBF16GER2 = 660 +PPC_INS_PMXVBF16GER2NN = 661 +PPC_INS_PMXVBF16GER2NP = 662 +PPC_INS_PMXVBF16GER2PN = 663 +PPC_INS_PMXVBF16GER2PP = 664 +PPC_INS_PMXVF16GER2 = 665 +PPC_INS_PMXVF16GER2NN = 666 +PPC_INS_PMXVF16GER2NP = 667 +PPC_INS_PMXVF16GER2PN = 668 +PPC_INS_PMXVF16GER2PP = 669 +PPC_INS_PMXVF32GER = 670 +PPC_INS_PMXVF32GERNN = 671 +PPC_INS_PMXVF32GERNP = 672 +PPC_INS_PMXVF32GERPN = 673 +PPC_INS_PMXVF32GERPP = 674 +PPC_INS_PMXVF64GER = 675 +PPC_INS_PMXVF64GERNN = 676 +PPC_INS_PMXVF64GERNP = 677 +PPC_INS_PMXVF64GERPN = 678 +PPC_INS_PMXVF64GERPP = 679 +PPC_INS_PMXVI16GER2 = 680 +PPC_INS_PMXVI16GER2PP = 681 +PPC_INS_PMXVI16GER2S = 682 +PPC_INS_PMXVI16GER2SPP = 683 +PPC_INS_PMXVI4GER8 = 684 +PPC_INS_PMXVI4GER8PP = 685 +PPC_INS_PMXVI8GER4 = 686 +PPC_INS_PMXVI8GER4PP = 687 +PPC_INS_PMXVI8GER4SPP = 688 +PPC_INS_POPCNTB = 689 +PPC_INS_POPCNTD = 690 +PPC_INS_POPCNTW = 691 +PPC_INS_DCBZ_L = 692 +PPC_INS_PSQ_L = 693 +PPC_INS_PSQ_LU = 694 +PPC_INS_PSQ_LUX = 695 +PPC_INS_PSQ_LX = 696 +PPC_INS_PSQ_ST = 697 +PPC_INS_PSQ_STU = 698 +PPC_INS_PSQ_STUX = 699 +PPC_INS_PSQ_STX = 700 +PPC_INS_PSTB = 701 +PPC_INS_PSTD = 702 +PPC_INS_PSTFD = 703 +PPC_INS_PSTFS = 704 +PPC_INS_PSTH = 705 +PPC_INS_PSTW = 706 +PPC_INS_PSTXSD = 707 +PPC_INS_PSTXSSP = 708 +PPC_INS_PSTXV = 709 +PPC_INS_PSTXVP = 710 +PPC_INS_PS_ABS = 711 +PPC_INS_PS_ADD = 712 +PPC_INS_PS_CMPO0 = 713 +PPC_INS_PS_CMPO1 = 714 +PPC_INS_PS_CMPU0 = 715 +PPC_INS_PS_CMPU1 = 716 +PPC_INS_PS_DIV = 717 +PPC_INS_PS_MADD = 718 +PPC_INS_PS_MADDS0 = 719 +PPC_INS_PS_MADDS1 = 720 +PPC_INS_PS_MERGE00 = 721 +PPC_INS_PS_MERGE01 = 722 +PPC_INS_PS_MERGE10 = 723 +PPC_INS_PS_MERGE11 = 724 +PPC_INS_PS_MR = 725 +PPC_INS_PS_MSUB = 726 +PPC_INS_PS_MUL = 727 +PPC_INS_PS_MULS0 = 728 +PPC_INS_PS_MULS1 = 729 +PPC_INS_PS_NABS = 730 +PPC_INS_PS_NEG = 731 +PPC_INS_PS_NMADD = 732 +PPC_INS_PS_NMSUB = 733 +PPC_INS_PS_RES = 734 +PPC_INS_PS_RSQRTE = 735 +PPC_INS_PS_SEL = 736 +PPC_INS_PS_SUB = 737 +PPC_INS_PS_SUM0 = 738 +PPC_INS_PS_SUM1 = 739 +PPC_INS_QVALIGNI = 740 +PPC_INS_QVESPLATI = 741 +PPC_INS_QVFABS = 742 +PPC_INS_QVFADD = 743 +PPC_INS_QVFADDS = 744 +PPC_INS_QVFCFID = 745 +PPC_INS_QVFCFIDS = 746 +PPC_INS_QVFCFIDU = 747 +PPC_INS_QVFCFIDUS = 748 +PPC_INS_QVFCMPEQ = 749 +PPC_INS_QVFCMPGT = 750 +PPC_INS_QVFCMPLT = 751 +PPC_INS_QVFCPSGN = 752 +PPC_INS_QVFCTID = 753 +PPC_INS_QVFCTIDU = 754 +PPC_INS_QVFCTIDUZ = 755 +PPC_INS_QVFCTIDZ = 756 +PPC_INS_QVFCTIW = 757 +PPC_INS_QVFCTIWU = 758 +PPC_INS_QVFCTIWUZ = 759 +PPC_INS_QVFCTIWZ = 760 +PPC_INS_QVFLOGICAL = 761 +PPC_INS_QVFMADD = 762 +PPC_INS_QVFMADDS = 763 +PPC_INS_QVFMR = 764 +PPC_INS_QVFMSUB = 765 +PPC_INS_QVFMSUBS = 766 +PPC_INS_QVFMUL = 767 +PPC_INS_QVFMULS = 768 +PPC_INS_QVFNABS = 769 +PPC_INS_QVFNEG = 770 +PPC_INS_QVFNMADD = 771 +PPC_INS_QVFNMADDS = 772 +PPC_INS_QVFNMSUB = 773 +PPC_INS_QVFNMSUBS = 774 +PPC_INS_QVFPERM = 775 +PPC_INS_QVFRE = 776 +PPC_INS_QVFRES = 777 +PPC_INS_QVFRIM = 778 +PPC_INS_QVFRIN = 779 +PPC_INS_QVFRIP = 780 +PPC_INS_QVFRIZ = 781 +PPC_INS_QVFRSP = 782 +PPC_INS_QVFRSQRTE = 783 +PPC_INS_QVFRSQRTES = 784 +PPC_INS_QVFSEL = 785 +PPC_INS_QVFSUB = 786 +PPC_INS_QVFSUBS = 787 +PPC_INS_QVFTSTNAN = 788 +PPC_INS_QVFXMADD = 789 +PPC_INS_QVFXMADDS = 790 +PPC_INS_QVFXMUL = 791 +PPC_INS_QVFXMULS = 792 +PPC_INS_QVFXXCPNMADD = 793 +PPC_INS_QVFXXCPNMADDS = 794 +PPC_INS_QVFXXMADD = 795 +PPC_INS_QVFXXMADDS = 796 +PPC_INS_QVFXXNPMADD = 797 +PPC_INS_QVFXXNPMADDS = 798 +PPC_INS_QVGPCI = 799 +PPC_INS_QVLFCDUX = 800 +PPC_INS_QVLFCDUXA = 801 +PPC_INS_QVLFCDX = 802 +PPC_INS_QVLFCDXA = 803 +PPC_INS_QVLFCSUX = 804 +PPC_INS_QVLFCSUXA = 805 +PPC_INS_QVLFCSX = 806 +PPC_INS_QVLFCSXA = 807 +PPC_INS_QVLFDUX = 808 +PPC_INS_QVLFDUXA = 809 +PPC_INS_QVLFDX = 810 +PPC_INS_QVLFDXA = 811 +PPC_INS_QVLFIWAX = 812 +PPC_INS_QVLFIWAXA = 813 +PPC_INS_QVLFIWZX = 814 +PPC_INS_QVLFIWZXA = 815 +PPC_INS_QVLFSUX = 816 +PPC_INS_QVLFSUXA = 817 +PPC_INS_QVLFSX = 818 +PPC_INS_QVLFSXA = 819 +PPC_INS_QVLPCLDX = 820 +PPC_INS_QVLPCLSX = 821 +PPC_INS_QVLPCRDX = 822 +PPC_INS_QVLPCRSX = 823 +PPC_INS_QVSTFCDUX = 824 +PPC_INS_QVSTFCDUXA = 825 +PPC_INS_QVSTFCDUXI = 826 +PPC_INS_QVSTFCDUXIA = 827 +PPC_INS_QVSTFCDX = 828 +PPC_INS_QVSTFCDXA = 829 +PPC_INS_QVSTFCDXI = 830 +PPC_INS_QVSTFCDXIA = 831 +PPC_INS_QVSTFCSUX = 832 +PPC_INS_QVSTFCSUXA = 833 +PPC_INS_QVSTFCSUXI = 834 +PPC_INS_QVSTFCSUXIA = 835 +PPC_INS_QVSTFCSX = 836 +PPC_INS_QVSTFCSXA = 837 +PPC_INS_QVSTFCSXI = 838 +PPC_INS_QVSTFCSXIA = 839 +PPC_INS_QVSTFDUX = 840 +PPC_INS_QVSTFDUXA = 841 +PPC_INS_QVSTFDUXI = 842 +PPC_INS_QVSTFDUXIA = 843 +PPC_INS_QVSTFDX = 844 +PPC_INS_QVSTFDXA = 845 +PPC_INS_QVSTFDXI = 846 +PPC_INS_QVSTFDXIA = 847 +PPC_INS_QVSTFIWX = 848 +PPC_INS_QVSTFIWXA = 849 +PPC_INS_QVSTFSUX = 850 +PPC_INS_QVSTFSUXA = 851 +PPC_INS_QVSTFSUXI = 852 +PPC_INS_QVSTFSUXIA = 853 +PPC_INS_QVSTFSX = 854 +PPC_INS_QVSTFSXA = 855 +PPC_INS_QVSTFSXI = 856 +PPC_INS_QVSTFSXIA = 857 +PPC_INS_RFCI = 858 +PPC_INS_RFDI = 859 +PPC_INS_RFEBB = 860 +PPC_INS_RFI = 861 +PPC_INS_RFID = 862 +PPC_INS_RFMCI = 863 +PPC_INS_RLDCL = 864 +PPC_INS_RLDCR = 865 +PPC_INS_RLDIC = 866 +PPC_INS_RLDICL = 867 +PPC_INS_RLDICR = 868 +PPC_INS_RLDIMI = 869 +PPC_INS_SC = 870 +PPC_INS_SETB = 871 +PPC_INS_SETBC = 872 +PPC_INS_SETBCR = 873 +PPC_INS_SETNBC = 874 +PPC_INS_SETNBCR = 875 +PPC_INS_SLBFEE = 876 +PPC_INS_SLBIA = 877 +PPC_INS_SLBIE = 878 +PPC_INS_SLBIEG = 879 +PPC_INS_SLBMFEE = 880 +PPC_INS_SLBMFEV = 881 +PPC_INS_SLBMTE = 882 +PPC_INS_SLBSYNC = 883 +PPC_INS_SLD = 884 +PPC_INS_SLW = 885 +PPC_INS_STW = 886 +PPC_INS_STWX = 887 +PPC_INS_SRAD = 888 +PPC_INS_SRADI = 889 +PPC_INS_SRAW = 890 +PPC_INS_SRAWI = 891 +PPC_INS_SRD = 892 +PPC_INS_SRW = 893 +PPC_INS_STB = 894 +PPC_INS_STBCIX = 895 +PPC_INS_STBCX = 896 +PPC_INS_STBEPX = 897 +PPC_INS_STBU = 898 +PPC_INS_STBUX = 899 +PPC_INS_STBX = 900 +PPC_INS_STD = 901 +PPC_INS_STDAT = 902 +PPC_INS_STDBRX = 903 +PPC_INS_STDCIX = 904 +PPC_INS_STDCX = 905 +PPC_INS_STDU = 906 +PPC_INS_STDUX = 907 +PPC_INS_STDX = 908 +PPC_INS_STFD = 909 +PPC_INS_STFDEPX = 910 +PPC_INS_STFDU = 911 +PPC_INS_STFDUX = 912 +PPC_INS_STFDX = 913 +PPC_INS_STFIWX = 914 +PPC_INS_STFS = 915 +PPC_INS_STFSU = 916 +PPC_INS_STFSUX = 917 +PPC_INS_STFSX = 918 +PPC_INS_STH = 919 +PPC_INS_STHBRX = 920 +PPC_INS_STHCIX = 921 +PPC_INS_STHCX = 922 +PPC_INS_STHEPX = 923 +PPC_INS_STHU = 924 +PPC_INS_STHUX = 925 +PPC_INS_STHX = 926 +PPC_INS_STMW = 927 +PPC_INS_STOP = 928 +PPC_INS_STQ = 929 +PPC_INS_STQCX = 930 +PPC_INS_STSWI = 931 +PPC_INS_STVEBX = 932 +PPC_INS_STVEHX = 933 +PPC_INS_STVEWX = 934 +PPC_INS_STVX = 935 +PPC_INS_STVXL = 936 +PPC_INS_STWAT = 937 +PPC_INS_STWBRX = 938 +PPC_INS_STWCIX = 939 +PPC_INS_STWCX = 940 +PPC_INS_STWEPX = 941 +PPC_INS_STWU = 942 +PPC_INS_STWUX = 943 +PPC_INS_STXSD = 944 +PPC_INS_STXSDX = 945 +PPC_INS_STXSIBX = 946 +PPC_INS_STXSIHX = 947 +PPC_INS_STXSIWX = 948 +PPC_INS_STXSSP = 949 +PPC_INS_STXSSPX = 950 +PPC_INS_STXV = 951 +PPC_INS_STXVB16X = 952 +PPC_INS_STXVD2X = 953 +PPC_INS_STXVH8X = 954 +PPC_INS_STXVL = 955 +PPC_INS_STXVLL = 956 +PPC_INS_STXVP = 957 +PPC_INS_STXVPRL = 958 +PPC_INS_STXVPRLL = 959 +PPC_INS_STXVPX = 960 +PPC_INS_STXVRBX = 961 +PPC_INS_STXVRDX = 962 +PPC_INS_STXVRHX = 963 +PPC_INS_STXVRL = 964 +PPC_INS_STXVRLL = 965 +PPC_INS_STXVRWX = 966 +PPC_INS_STXVW4X = 967 +PPC_INS_STXVX = 968 +PPC_INS_SUBF = 969 +PPC_INS_SUBFC = 970 +PPC_INS_SUBFCO = 971 +PPC_INS_SUBFE = 972 +PPC_INS_SUBFEO = 973 +PPC_INS_SUBFIC = 974 +PPC_INS_SUBFME = 975 +PPC_INS_SUBFMEO = 976 +PPC_INS_SUBFO = 977 +PPC_INS_SUBFUS = 978 +PPC_INS_SUBFZE = 979 +PPC_INS_SUBFZEO = 980 +PPC_INS_SYNC = 981 +PPC_INS_TABORT = 982 +PPC_INS_TABORTDC = 983 +PPC_INS_TABORTDCI = 984 +PPC_INS_TABORTWC = 985 +PPC_INS_TABORTWCI = 986 +PPC_INS_TBEGIN = 987 +PPC_INS_TCHECK = 988 +PPC_INS_TD = 989 +PPC_INS_TDI = 990 +PPC_INS_TEND = 991 +PPC_INS_TLBIA = 992 +PPC_INS_TLBIE = 993 +PPC_INS_TLBIEL = 994 +PPC_INS_TLBIVAX = 995 +PPC_INS_TLBLD = 996 +PPC_INS_TLBLI = 997 +PPC_INS_TLBRE = 998 +PPC_INS_TLBSX = 999 +PPC_INS_TLBSYNC = 1000 +PPC_INS_TLBWE = 1001 +PPC_INS_TRAP = 1002 +PPC_INS_TRECHKPT = 1003 +PPC_INS_TRECLAIM = 1004 +PPC_INS_TSR = 1005 +PPC_INS_TW = 1006 +PPC_INS_TWI = 1007 +PPC_INS_VABSDUB = 1008 +PPC_INS_VABSDUH = 1009 +PPC_INS_VABSDUW = 1010 +PPC_INS_VADDCUQ = 1011 +PPC_INS_VADDCUW = 1012 +PPC_INS_VADDECUQ = 1013 +PPC_INS_VADDEUQM = 1014 +PPC_INS_VADDFP = 1015 +PPC_INS_VADDSBS = 1016 +PPC_INS_VADDSHS = 1017 +PPC_INS_VADDSWS = 1018 +PPC_INS_VADDUBM = 1019 +PPC_INS_VADDUBS = 1020 +PPC_INS_VADDUDM = 1021 +PPC_INS_VADDUHM = 1022 +PPC_INS_VADDUHS = 1023 +PPC_INS_VADDUQM = 1024 +PPC_INS_VADDUWM = 1025 +PPC_INS_VADDUWS = 1026 +PPC_INS_VAND = 1027 +PPC_INS_VANDC = 1028 +PPC_INS_VAVGSB = 1029 +PPC_INS_VAVGSH = 1030 +PPC_INS_VAVGSW = 1031 +PPC_INS_VAVGUB = 1032 +PPC_INS_VAVGUH = 1033 +PPC_INS_VAVGUW = 1034 +PPC_INS_VBPERMD = 1035 +PPC_INS_VBPERMQ = 1036 +PPC_INS_VCFSX = 1037 +PPC_INS_VCFUGED = 1038 +PPC_INS_VCFUX = 1039 +PPC_INS_VCIPHER = 1040 +PPC_INS_VCIPHERLAST = 1041 +PPC_INS_VCLRLB = 1042 +PPC_INS_VCLRRB = 1043 +PPC_INS_VCLZB = 1044 +PPC_INS_VCLZD = 1045 +PPC_INS_VCLZDM = 1046 +PPC_INS_VCLZH = 1047 +PPC_INS_VCLZLSBB = 1048 +PPC_INS_VCLZW = 1049 +PPC_INS_VCMPBFP = 1050 +PPC_INS_VCMPEQFP = 1051 +PPC_INS_VCMPEQUB = 1052 +PPC_INS_VCMPEQUD = 1053 +PPC_INS_VCMPEQUH = 1054 +PPC_INS_VCMPEQUQ = 1055 +PPC_INS_VCMPEQUW = 1056 +PPC_INS_VCMPGEFP = 1057 +PPC_INS_VCMPGTFP = 1058 +PPC_INS_VCMPGTSB = 1059 +PPC_INS_VCMPGTSD = 1060 +PPC_INS_VCMPGTSH = 1061 +PPC_INS_VCMPGTSQ = 1062 +PPC_INS_VCMPGTSW = 1063 +PPC_INS_VCMPGTUB = 1064 +PPC_INS_VCMPGTUD = 1065 +PPC_INS_VCMPGTUH = 1066 +PPC_INS_VCMPGTUQ = 1067 +PPC_INS_VCMPGTUW = 1068 +PPC_INS_VCMPNEB = 1069 +PPC_INS_VCMPNEH = 1070 +PPC_INS_VCMPNEW = 1071 +PPC_INS_VCMPNEZB = 1072 +PPC_INS_VCMPNEZH = 1073 +PPC_INS_VCMPNEZW = 1074 +PPC_INS_VCMPSQ = 1075 +PPC_INS_VCMPUQ = 1076 +PPC_INS_VCNTMBB = 1077 +PPC_INS_VCNTMBD = 1078 +PPC_INS_VCNTMBH = 1079 +PPC_INS_VCNTMBW = 1080 +PPC_INS_VCTSXS = 1081 +PPC_INS_VCTUXS = 1082 +PPC_INS_VCTZB = 1083 +PPC_INS_VCTZD = 1084 +PPC_INS_VCTZDM = 1085 +PPC_INS_VCTZH = 1086 +PPC_INS_VCTZLSBB = 1087 +PPC_INS_VCTZW = 1088 +PPC_INS_VDIVESD = 1089 +PPC_INS_VDIVESQ = 1090 +PPC_INS_VDIVESW = 1091 +PPC_INS_VDIVEUD = 1092 +PPC_INS_VDIVEUQ = 1093 +PPC_INS_VDIVEUW = 1094 +PPC_INS_VDIVSD = 1095 +PPC_INS_VDIVSQ = 1096 +PPC_INS_VDIVSW = 1097 +PPC_INS_VDIVUD = 1098 +PPC_INS_VDIVUQ = 1099 +PPC_INS_VDIVUW = 1100 +PPC_INS_VEQV = 1101 +PPC_INS_VEXPANDBM = 1102 +PPC_INS_VEXPANDDM = 1103 +PPC_INS_VEXPANDHM = 1104 +PPC_INS_VEXPANDQM = 1105 +PPC_INS_VEXPANDWM = 1106 +PPC_INS_VEXPTEFP = 1107 +PPC_INS_VEXTDDVLX = 1108 +PPC_INS_VEXTDDVRX = 1109 +PPC_INS_VEXTDUBVLX = 1110 +PPC_INS_VEXTDUBVRX = 1111 +PPC_INS_VEXTDUHVLX = 1112 +PPC_INS_VEXTDUHVRX = 1113 +PPC_INS_VEXTDUWVLX = 1114 +PPC_INS_VEXTDUWVRX = 1115 +PPC_INS_VEXTRACTBM = 1116 +PPC_INS_VEXTRACTD = 1117 +PPC_INS_VEXTRACTDM = 1118 +PPC_INS_VEXTRACTHM = 1119 +PPC_INS_VEXTRACTQM = 1120 +PPC_INS_VEXTRACTUB = 1121 +PPC_INS_VEXTRACTUH = 1122 +PPC_INS_VEXTRACTUW = 1123 +PPC_INS_VEXTRACTWM = 1124 +PPC_INS_VEXTSB2D = 1125 +PPC_INS_VEXTSB2W = 1126 +PPC_INS_VEXTSD2Q = 1127 +PPC_INS_VEXTSH2D = 1128 +PPC_INS_VEXTSH2W = 1129 +PPC_INS_VEXTSW2D = 1130 +PPC_INS_VEXTUBLX = 1131 +PPC_INS_VEXTUBRX = 1132 +PPC_INS_VEXTUHLX = 1133 +PPC_INS_VEXTUHRX = 1134 +PPC_INS_VEXTUWLX = 1135 +PPC_INS_VEXTUWRX = 1136 +PPC_INS_VGBBD = 1137 +PPC_INS_VGNB = 1138 +PPC_INS_VINSBLX = 1139 +PPC_INS_VINSBRX = 1140 +PPC_INS_VINSBVLX = 1141 +PPC_INS_VINSBVRX = 1142 +PPC_INS_VINSD = 1143 +PPC_INS_VINSDLX = 1144 +PPC_INS_VINSDRX = 1145 +PPC_INS_VINSERTB = 1146 +PPC_INS_VINSERTD = 1147 +PPC_INS_VINSERTH = 1148 +PPC_INS_VINSERTW = 1149 +PPC_INS_VINSHLX = 1150 +PPC_INS_VINSHRX = 1151 +PPC_INS_VINSHVLX = 1152 +PPC_INS_VINSHVRX = 1153 +PPC_INS_VINSW = 1154 +PPC_INS_VINSWLX = 1155 +PPC_INS_VINSWRX = 1156 +PPC_INS_VINSWVLX = 1157 +PPC_INS_VINSWVRX = 1158 +PPC_INS_VLOGEFP = 1159 +PPC_INS_VMADDFP = 1160 +PPC_INS_VMAXFP = 1161 +PPC_INS_VMAXSB = 1162 +PPC_INS_VMAXSD = 1163 +PPC_INS_VMAXSH = 1164 +PPC_INS_VMAXSW = 1165 +PPC_INS_VMAXUB = 1166 +PPC_INS_VMAXUD = 1167 +PPC_INS_VMAXUH = 1168 +PPC_INS_VMAXUW = 1169 +PPC_INS_VMHADDSHS = 1170 +PPC_INS_VMHRADDSHS = 1171 +PPC_INS_VMINFP = 1172 +PPC_INS_VMINSB = 1173 +PPC_INS_VMINSD = 1174 +PPC_INS_VMINSH = 1175 +PPC_INS_VMINSW = 1176 +PPC_INS_VMINUB = 1177 +PPC_INS_VMINUD = 1178 +PPC_INS_VMINUH = 1179 +PPC_INS_VMINUW = 1180 +PPC_INS_VMLADDUHM = 1181 +PPC_INS_VMODSD = 1182 +PPC_INS_VMODSQ = 1183 +PPC_INS_VMODSW = 1184 +PPC_INS_VMODUD = 1185 +PPC_INS_VMODUQ = 1186 +PPC_INS_VMODUW = 1187 +PPC_INS_VMRGEW = 1188 +PPC_INS_VMRGHB = 1189 +PPC_INS_VMRGHH = 1190 +PPC_INS_VMRGHW = 1191 +PPC_INS_VMRGLB = 1192 +PPC_INS_VMRGLH = 1193 +PPC_INS_VMRGLW = 1194 +PPC_INS_VMRGOW = 1195 +PPC_INS_VMSUMCUD = 1196 +PPC_INS_VMSUMMBM = 1197 +PPC_INS_VMSUMSHM = 1198 +PPC_INS_VMSUMSHS = 1199 +PPC_INS_VMSUMUBM = 1200 +PPC_INS_VMSUMUDM = 1201 +PPC_INS_VMSUMUHM = 1202 +PPC_INS_VMSUMUHS = 1203 +PPC_INS_VMUL10CUQ = 1204 +PPC_INS_VMUL10ECUQ = 1205 +PPC_INS_VMUL10EUQ = 1206 +PPC_INS_VMUL10UQ = 1207 +PPC_INS_VMULESB = 1208 +PPC_INS_VMULESD = 1209 +PPC_INS_VMULESH = 1210 +PPC_INS_VMULESW = 1211 +PPC_INS_VMULEUB = 1212 +PPC_INS_VMULEUD = 1213 +PPC_INS_VMULEUH = 1214 +PPC_INS_VMULEUW = 1215 +PPC_INS_VMULHSD = 1216 +PPC_INS_VMULHSW = 1217 +PPC_INS_VMULHUD = 1218 +PPC_INS_VMULHUW = 1219 +PPC_INS_VMULLD = 1220 +PPC_INS_VMULOSB = 1221 +PPC_INS_VMULOSD = 1222 +PPC_INS_VMULOSH = 1223 +PPC_INS_VMULOSW = 1224 +PPC_INS_VMULOUB = 1225 +PPC_INS_VMULOUD = 1226 +PPC_INS_VMULOUH = 1227 +PPC_INS_VMULOUW = 1228 +PPC_INS_VMULUWM = 1229 +PPC_INS_VNAND = 1230 +PPC_INS_VNCIPHER = 1231 +PPC_INS_VNCIPHERLAST = 1232 +PPC_INS_VNEGD = 1233 +PPC_INS_VNEGW = 1234 +PPC_INS_VNMSUBFP = 1235 +PPC_INS_VNOR = 1236 +PPC_INS_VOR = 1237 +PPC_INS_VORC = 1238 +PPC_INS_VPDEPD = 1239 +PPC_INS_VPERM = 1240 +PPC_INS_VPERMR = 1241 +PPC_INS_VPERMXOR = 1242 +PPC_INS_VPEXTD = 1243 +PPC_INS_VPKPX = 1244 +PPC_INS_VPKSDSS = 1245 +PPC_INS_VPKSDUS = 1246 +PPC_INS_VPKSHSS = 1247 +PPC_INS_VPKSHUS = 1248 +PPC_INS_VPKSWSS = 1249 +PPC_INS_VPKSWUS = 1250 +PPC_INS_VPKUDUM = 1251 +PPC_INS_VPKUDUS = 1252 +PPC_INS_VPKUHUM = 1253 +PPC_INS_VPKUHUS = 1254 +PPC_INS_VPKUWUM = 1255 +PPC_INS_VPKUWUS = 1256 +PPC_INS_VPMSUMB = 1257 +PPC_INS_VPMSUMD = 1258 +PPC_INS_VPMSUMH = 1259 +PPC_INS_VPMSUMW = 1260 +PPC_INS_VPOPCNTB = 1261 +PPC_INS_VPOPCNTD = 1262 +PPC_INS_VPOPCNTH = 1263 +PPC_INS_VPOPCNTW = 1264 +PPC_INS_VPRTYBD = 1265 +PPC_INS_VPRTYBQ = 1266 +PPC_INS_VPRTYBW = 1267 +PPC_INS_VREFP = 1268 +PPC_INS_VRFIM = 1269 +PPC_INS_VRFIN = 1270 +PPC_INS_VRFIP = 1271 +PPC_INS_VRFIZ = 1272 +PPC_INS_VRLB = 1273 +PPC_INS_VRLD = 1274 +PPC_INS_VRLDMI = 1275 +PPC_INS_VRLDNM = 1276 +PPC_INS_VRLH = 1277 +PPC_INS_VRLQ = 1278 +PPC_INS_VRLQMI = 1279 +PPC_INS_VRLQNM = 1280 +PPC_INS_VRLW = 1281 +PPC_INS_VRLWMI = 1282 +PPC_INS_VRLWNM = 1283 +PPC_INS_VRSQRTEFP = 1284 +PPC_INS_VSBOX = 1285 +PPC_INS_VSEL = 1286 +PPC_INS_VSHASIGMAD = 1287 +PPC_INS_VSHASIGMAW = 1288 +PPC_INS_VSL = 1289 +PPC_INS_VSLB = 1290 +PPC_INS_VSLD = 1291 +PPC_INS_VSLDBI = 1292 +PPC_INS_VSLDOI = 1293 +PPC_INS_VSLH = 1294 +PPC_INS_VSLO = 1295 +PPC_INS_VSLQ = 1296 +PPC_INS_VSLV = 1297 +PPC_INS_VSLW = 1298 +PPC_INS_VSPLTB = 1299 +PPC_INS_VSPLTH = 1300 +PPC_INS_VSPLTISB = 1301 +PPC_INS_VSPLTISH = 1302 +PPC_INS_VSPLTISW = 1303 +PPC_INS_VSPLTW = 1304 +PPC_INS_VSR = 1305 +PPC_INS_VSRAB = 1306 +PPC_INS_VSRAD = 1307 +PPC_INS_VSRAH = 1308 +PPC_INS_VSRAQ = 1309 +PPC_INS_VSRAW = 1310 +PPC_INS_VSRB = 1311 +PPC_INS_VSRD = 1312 +PPC_INS_VSRDBI = 1313 +PPC_INS_VSRH = 1314 +PPC_INS_VSRO = 1315 +PPC_INS_VSRQ = 1316 +PPC_INS_VSRV = 1317 +PPC_INS_VSRW = 1318 +PPC_INS_VSTRIBL = 1319 +PPC_INS_VSTRIBR = 1320 +PPC_INS_VSTRIHL = 1321 +PPC_INS_VSTRIHR = 1322 +PPC_INS_VSUBCUQ = 1323 +PPC_INS_VSUBCUW = 1324 +PPC_INS_VSUBECUQ = 1325 +PPC_INS_VSUBEUQM = 1326 +PPC_INS_VSUBFP = 1327 +PPC_INS_VSUBSBS = 1328 +PPC_INS_VSUBSHS = 1329 +PPC_INS_VSUBSWS = 1330 +PPC_INS_VSUBUBM = 1331 +PPC_INS_VSUBUBS = 1332 +PPC_INS_VSUBUDM = 1333 +PPC_INS_VSUBUHM = 1334 +PPC_INS_VSUBUHS = 1335 +PPC_INS_VSUBUQM = 1336 +PPC_INS_VSUBUWM = 1337 +PPC_INS_VSUBUWS = 1338 +PPC_INS_VSUM2SWS = 1339 +PPC_INS_VSUM4SBS = 1340 +PPC_INS_VSUM4SHS = 1341 +PPC_INS_VSUM4UBS = 1342 +PPC_INS_VSUMSWS = 1343 +PPC_INS_VUPKHPX = 1344 +PPC_INS_VUPKHSB = 1345 +PPC_INS_VUPKHSH = 1346 +PPC_INS_VUPKHSW = 1347 +PPC_INS_VUPKLPX = 1348 +PPC_INS_VUPKLSB = 1349 +PPC_INS_VUPKLSH = 1350 +PPC_INS_VUPKLSW = 1351 +PPC_INS_VXOR = 1352 +PPC_INS_WAIT = 1353 +PPC_INS_WRTEE = 1354 +PPC_INS_WRTEEI = 1355 +PPC_INS_XOR = 1356 +PPC_INS_XORI = 1357 +PPC_INS_XORIS = 1358 +PPC_INS_XSABSDP = 1359 +PPC_INS_XSABSQP = 1360 +PPC_INS_XSADDDP = 1361 +PPC_INS_XSADDQP = 1362 +PPC_INS_XSADDQPO = 1363 +PPC_INS_XSADDSP = 1364 +PPC_INS_XSCMPEQDP = 1365 +PPC_INS_XSCMPEQQP = 1366 +PPC_INS_XSCMPEXPDP = 1367 +PPC_INS_XSCMPEXPQP = 1368 +PPC_INS_XSCMPGEDP = 1369 +PPC_INS_XSCMPGEQP = 1370 +PPC_INS_XSCMPGTDP = 1371 +PPC_INS_XSCMPGTQP = 1372 +PPC_INS_XSCMPODP = 1373 +PPC_INS_XSCMPOQP = 1374 +PPC_INS_XSCMPUDP = 1375 +PPC_INS_XSCMPUQP = 1376 +PPC_INS_XSCPSGNDP = 1377 +PPC_INS_XSCPSGNQP = 1378 +PPC_INS_XSCVDPHP = 1379 +PPC_INS_XSCVDPQP = 1380 +PPC_INS_XSCVDPSP = 1381 +PPC_INS_XSCVDPSPN = 1382 +PPC_INS_XSCVDPSXDS = 1383 +PPC_INS_XSCVDPSXWS = 1384 +PPC_INS_XSCVDPUXDS = 1385 +PPC_INS_XSCVDPUXWS = 1386 +PPC_INS_XSCVHPDP = 1387 +PPC_INS_XSCVQPDP = 1388 +PPC_INS_XSCVQPDPO = 1389 +PPC_INS_XSCVQPSDZ = 1390 +PPC_INS_XSCVQPSQZ = 1391 +PPC_INS_XSCVQPSWZ = 1392 +PPC_INS_XSCVQPUDZ = 1393 +PPC_INS_XSCVQPUQZ = 1394 +PPC_INS_XSCVQPUWZ = 1395 +PPC_INS_XSCVSDQP = 1396 +PPC_INS_XSCVSPDP = 1397 +PPC_INS_XSCVSPDPN = 1398 +PPC_INS_XSCVSQQP = 1399 +PPC_INS_XSCVSXDDP = 1400 +PPC_INS_XSCVSXDSP = 1401 +PPC_INS_XSCVUDQP = 1402 +PPC_INS_XSCVUQQP = 1403 +PPC_INS_XSCVUXDDP = 1404 +PPC_INS_XSCVUXDSP = 1405 +PPC_INS_XSDIVDP = 1406 +PPC_INS_XSDIVQP = 1407 +PPC_INS_XSDIVQPO = 1408 +PPC_INS_XSDIVSP = 1409 +PPC_INS_XSIEXPDP = 1410 +PPC_INS_XSIEXPQP = 1411 +PPC_INS_XSMADDADP = 1412 +PPC_INS_XSMADDASP = 1413 +PPC_INS_XSMADDMDP = 1414 +PPC_INS_XSMADDMSP = 1415 +PPC_INS_XSMADDQP = 1416 +PPC_INS_XSMADDQPO = 1417 +PPC_INS_XSMAXCDP = 1418 +PPC_INS_XSMAXCQP = 1419 +PPC_INS_XSMAXDP = 1420 +PPC_INS_XSMAXJDP = 1421 +PPC_INS_XSMINCDP = 1422 +PPC_INS_XSMINCQP = 1423 +PPC_INS_XSMINDP = 1424 +PPC_INS_XSMINJDP = 1425 +PPC_INS_XSMSUBADP = 1426 +PPC_INS_XSMSUBASP = 1427 +PPC_INS_XSMSUBMDP = 1428 +PPC_INS_XSMSUBMSP = 1429 +PPC_INS_XSMSUBQP = 1430 +PPC_INS_XSMSUBQPO = 1431 +PPC_INS_XSMULDP = 1432 +PPC_INS_XSMULQP = 1433 +PPC_INS_XSMULQPO = 1434 +PPC_INS_XSMULSP = 1435 +PPC_INS_XSNABSDP = 1436 +PPC_INS_XSNABSQP = 1437 +PPC_INS_XSNEGDP = 1438 +PPC_INS_XSNEGQP = 1439 +PPC_INS_XSNMADDADP = 1440 +PPC_INS_XSNMADDASP = 1441 +PPC_INS_XSNMADDMDP = 1442 +PPC_INS_XSNMADDMSP = 1443 +PPC_INS_XSNMADDQP = 1444 +PPC_INS_XSNMADDQPO = 1445 +PPC_INS_XSNMSUBADP = 1446 +PPC_INS_XSNMSUBASP = 1447 +PPC_INS_XSNMSUBMDP = 1448 +PPC_INS_XSNMSUBMSP = 1449 +PPC_INS_XSNMSUBQP = 1450 +PPC_INS_XSNMSUBQPO = 1451 +PPC_INS_XSRDPI = 1452 +PPC_INS_XSRDPIC = 1453 +PPC_INS_XSRDPIM = 1454 +PPC_INS_XSRDPIP = 1455 +PPC_INS_XSRDPIZ = 1456 +PPC_INS_XSREDP = 1457 +PPC_INS_XSRESP = 1458 +PPC_INS_XSRQPI = 1459 +PPC_INS_XSRQPIX = 1460 +PPC_INS_XSRQPXP = 1461 +PPC_INS_XSRSP = 1462 +PPC_INS_XSRSQRTEDP = 1463 +PPC_INS_XSRSQRTESP = 1464 +PPC_INS_XSSQRTDP = 1465 +PPC_INS_XSSQRTQP = 1466 +PPC_INS_XSSQRTQPO = 1467 +PPC_INS_XSSQRTSP = 1468 +PPC_INS_XSSUBDP = 1469 +PPC_INS_XSSUBQP = 1470 +PPC_INS_XSSUBQPO = 1471 +PPC_INS_XSSUBSP = 1472 +PPC_INS_XSTDIVDP = 1473 +PPC_INS_XSTSQRTDP = 1474 +PPC_INS_XSTSTDCDP = 1475 +PPC_INS_XSTSTDCQP = 1476 +PPC_INS_XSTSTDCSP = 1477 +PPC_INS_XSXEXPDP = 1478 +PPC_INS_XSXEXPQP = 1479 +PPC_INS_XSXSIGDP = 1480 +PPC_INS_XSXSIGQP = 1481 +PPC_INS_XVABSDP = 1482 +PPC_INS_XVABSSP = 1483 +PPC_INS_XVADDDP = 1484 +PPC_INS_XVADDSP = 1485 +PPC_INS_XVBF16GER2 = 1486 +PPC_INS_XVBF16GER2NN = 1487 +PPC_INS_XVBF16GER2NP = 1488 +PPC_INS_XVBF16GER2PN = 1489 +PPC_INS_XVBF16GER2PP = 1490 +PPC_INS_XVCMPEQDP = 1491 +PPC_INS_XVCMPEQSP = 1492 +PPC_INS_XVCMPGEDP = 1493 +PPC_INS_XVCMPGESP = 1494 +PPC_INS_XVCMPGTDP = 1495 +PPC_INS_XVCMPGTSP = 1496 +PPC_INS_XVCPSGNDP = 1497 +PPC_INS_XVCPSGNSP = 1498 +PPC_INS_XVCVBF16SPN = 1499 +PPC_INS_XVCVDPSP = 1500 +PPC_INS_XVCVDPSXDS = 1501 +PPC_INS_XVCVDPSXWS = 1502 +PPC_INS_XVCVDPUXDS = 1503 +PPC_INS_XVCVDPUXWS = 1504 +PPC_INS_XVCVHPSP = 1505 +PPC_INS_XVCVSPBF16 = 1506 +PPC_INS_XVCVSPDP = 1507 +PPC_INS_XVCVSPHP = 1508 +PPC_INS_XVCVSPSXDS = 1509 +PPC_INS_XVCVSPSXWS = 1510 +PPC_INS_XVCVSPUXDS = 1511 +PPC_INS_XVCVSPUXWS = 1512 +PPC_INS_XVCVSXDDP = 1513 +PPC_INS_XVCVSXDSP = 1514 +PPC_INS_XVCVSXWDP = 1515 +PPC_INS_XVCVSXWSP = 1516 +PPC_INS_XVCVUXDDP = 1517 +PPC_INS_XVCVUXDSP = 1518 +PPC_INS_XVCVUXWDP = 1519 +PPC_INS_XVCVUXWSP = 1520 +PPC_INS_XVDIVDP = 1521 +PPC_INS_XVDIVSP = 1522 +PPC_INS_XVF16GER2 = 1523 +PPC_INS_XVF16GER2NN = 1524 +PPC_INS_XVF16GER2NP = 1525 +PPC_INS_XVF16GER2PN = 1526 +PPC_INS_XVF16GER2PP = 1527 +PPC_INS_XVF32GER = 1528 +PPC_INS_XVF32GERNN = 1529 +PPC_INS_XVF32GERNP = 1530 +PPC_INS_XVF32GERPN = 1531 +PPC_INS_XVF32GERPP = 1532 +PPC_INS_XVF64GER = 1533 +PPC_INS_XVF64GERNN = 1534 +PPC_INS_XVF64GERNP = 1535 +PPC_INS_XVF64GERPN = 1536 +PPC_INS_XVF64GERPP = 1537 +PPC_INS_XVI16GER2 = 1538 +PPC_INS_XVI16GER2PP = 1539 +PPC_INS_XVI16GER2S = 1540 +PPC_INS_XVI16GER2SPP = 1541 +PPC_INS_XVI4GER8 = 1542 +PPC_INS_XVI4GER8PP = 1543 +PPC_INS_XVI8GER4 = 1544 +PPC_INS_XVI8GER4PP = 1545 +PPC_INS_XVI8GER4SPP = 1546 +PPC_INS_XVIEXPDP = 1547 +PPC_INS_XVIEXPSP = 1548 +PPC_INS_XVMADDADP = 1549 +PPC_INS_XVMADDASP = 1550 +PPC_INS_XVMADDMDP = 1551 +PPC_INS_XVMADDMSP = 1552 +PPC_INS_XVMAXDP = 1553 +PPC_INS_XVMAXSP = 1554 +PPC_INS_XVMINDP = 1555 +PPC_INS_XVMINSP = 1556 +PPC_INS_XVMSUBADP = 1557 +PPC_INS_XVMSUBASP = 1558 +PPC_INS_XVMSUBMDP = 1559 +PPC_INS_XVMSUBMSP = 1560 +PPC_INS_XVMULDP = 1561 +PPC_INS_XVMULSP = 1562 +PPC_INS_XVNABSDP = 1563 +PPC_INS_XVNABSSP = 1564 +PPC_INS_XVNEGDP = 1565 +PPC_INS_XVNEGSP = 1566 +PPC_INS_XVNMADDADP = 1567 +PPC_INS_XVNMADDASP = 1568 +PPC_INS_XVNMADDMDP = 1569 +PPC_INS_XVNMADDMSP = 1570 +PPC_INS_XVNMSUBADP = 1571 +PPC_INS_XVNMSUBASP = 1572 +PPC_INS_XVNMSUBMDP = 1573 +PPC_INS_XVNMSUBMSP = 1574 +PPC_INS_XVRDPI = 1575 +PPC_INS_XVRDPIC = 1576 +PPC_INS_XVRDPIM = 1577 +PPC_INS_XVRDPIP = 1578 +PPC_INS_XVRDPIZ = 1579 +PPC_INS_XVREDP = 1580 +PPC_INS_XVRESP = 1581 +PPC_INS_XVRSPI = 1582 +PPC_INS_XVRSPIC = 1583 +PPC_INS_XVRSPIM = 1584 +PPC_INS_XVRSPIP = 1585 +PPC_INS_XVRSPIZ = 1586 +PPC_INS_XVRSQRTEDP = 1587 +PPC_INS_XVRSQRTESP = 1588 +PPC_INS_XVSQRTDP = 1589 +PPC_INS_XVSQRTSP = 1590 +PPC_INS_XVSUBDP = 1591 +PPC_INS_XVSUBSP = 1592 +PPC_INS_XVTDIVDP = 1593 +PPC_INS_XVTDIVSP = 1594 +PPC_INS_XVTLSBB = 1595 +PPC_INS_XVTSQRTDP = 1596 +PPC_INS_XVTSQRTSP = 1597 +PPC_INS_XVTSTDCDP = 1598 +PPC_INS_XVTSTDCSP = 1599 +PPC_INS_XVXEXPDP = 1600 +PPC_INS_XVXEXPSP = 1601 +PPC_INS_XVXSIGDP = 1602 +PPC_INS_XVXSIGSP = 1603 +PPC_INS_XXBLENDVB = 1604 +PPC_INS_XXBLENDVD = 1605 +PPC_INS_XXBLENDVH = 1606 +PPC_INS_XXBLENDVW = 1607 +PPC_INS_XXBRD = 1608 +PPC_INS_XXBRH = 1609 +PPC_INS_XXBRQ = 1610 +PPC_INS_XXBRW = 1611 +PPC_INS_XXEVAL = 1612 +PPC_INS_XXEXTRACTUW = 1613 +PPC_INS_XXGENPCVBM = 1614 +PPC_INS_XXGENPCVDM = 1615 +PPC_INS_XXGENPCVHM = 1616 +PPC_INS_XXGENPCVWM = 1617 +PPC_INS_XXINSERTW = 1618 +PPC_INS_XXLAND = 1619 +PPC_INS_XXLANDC = 1620 +PPC_INS_XXLEQV = 1621 +PPC_INS_XXLNAND = 1622 +PPC_INS_XXLNOR = 1623 +PPC_INS_XXLOR = 1624 +PPC_INS_XXLORC = 1625 +PPC_INS_XXLXOR = 1626 +PPC_INS_XXMFACC = 1627 +PPC_INS_XXMRGHW = 1628 +PPC_INS_XXMRGLW = 1629 +PPC_INS_XXMTACC = 1630 +PPC_INS_XXPERM = 1631 +PPC_INS_XXPERMDI = 1632 +PPC_INS_XXPERMR = 1633 +PPC_INS_XXPERMX = 1634 +PPC_INS_XXSEL = 1635 +PPC_INS_XXSETACCZ = 1636 +PPC_INS_XXSLDWI = 1637 +PPC_INS_XXSPLTI32DX = 1638 +PPC_INS_XXSPLTIB = 1639 +PPC_INS_XXSPLTIDP = 1640 +PPC_INS_XXSPLTIW = 1641 +PPC_INS_XXSPLTW = 1642 +PPC_INS_BC = 1643 +PPC_INS_BCA = 1644 +PPC_INS_BCCTR = 1645 +PPC_INS_BCCTRL = 1646 +PPC_INS_BCL = 1647 +PPC_INS_BCLA = 1648 +PPC_INS_BCLR = 1649 +PPC_INS_BCLRL = 1650 +PPC_INS_ENDING = 1651 +PPC_INS_ALIAS_BEGIN = 1652 +PPC_INS_ALIAS_RFEBB = 1653 +PPC_INS_ALIAS_LI = 1654 +PPC_INS_ALIAS_LIS = 1655 +PPC_INS_ALIAS_MR = 1656 +PPC_INS_ALIAS_MR_ = 1657 +PPC_INS_ALIAS_NOT = 1658 +PPC_INS_ALIAS_NOT_ = 1659 +PPC_INS_ALIAS_NOP = 1660 +PPC_INS_ALIAS_MTUDSCR = 1661 +PPC_INS_ALIAS_MFUDSCR = 1662 +PPC_INS_ALIAS_MTVRSAVE = 1663 +PPC_INS_ALIAS_MFVRSAVE = 1664 +PPC_INS_ALIAS_MTCR = 1665 +PPC_INS_ALIAS_SUB = 1666 +PPC_INS_ALIAS_SUB_ = 1667 +PPC_INS_ALIAS_SUBC = 1668 +PPC_INS_ALIAS_SUBC_ = 1669 +PPC_INS_ALIAS_VMR = 1670 +PPC_INS_ALIAS_VNOT = 1671 +PPC_INS_ALIAS_ROTLWI = 1672 +PPC_INS_ALIAS_ROTLWI_ = 1673 +PPC_INS_ALIAS_ROTLW = 1674 +PPC_INS_ALIAS_ROTLW_ = 1675 +PPC_INS_ALIAS_CLRLWI = 1676 +PPC_INS_ALIAS_CLRLWI_ = 1677 +PPC_INS_ALIAS_ISELLT = 1678 +PPC_INS_ALIAS_ISELGT = 1679 +PPC_INS_ALIAS_ISELEQ = 1680 +PPC_INS_ALIAS_XNOP = 1681 +PPC_INS_ALIAS_CNTLZW = 1682 +PPC_INS_ALIAS_CNTLZW_ = 1683 +PPC_INS_ALIAS_MTXER = 1684 +PPC_INS_ALIAS_MFXER = 1685 +PPC_INS_ALIAS_MFRTCU = 1686 +PPC_INS_ALIAS_MFRTCL = 1687 +PPC_INS_ALIAS_MTLR = 1688 +PPC_INS_ALIAS_MFLR = 1689 +PPC_INS_ALIAS_MTCTR = 1690 +PPC_INS_ALIAS_MFCTR = 1691 +PPC_INS_ALIAS_MTUAMR = 1692 +PPC_INS_ALIAS_MFUAMR = 1693 +PPC_INS_ALIAS_MTDSCR = 1694 +PPC_INS_ALIAS_MFDSCR = 1695 +PPC_INS_ALIAS_MTDSISR = 1696 +PPC_INS_ALIAS_MFDSISR = 1697 +PPC_INS_ALIAS_MTDAR = 1698 +PPC_INS_ALIAS_MFDAR = 1699 +PPC_INS_ALIAS_MTDEC = 1700 +PPC_INS_ALIAS_MFDEC = 1701 +PPC_INS_ALIAS_MTSDR1 = 1702 +PPC_INS_ALIAS_MFSDR1 = 1703 +PPC_INS_ALIAS_MTSRR0 = 1704 +PPC_INS_ALIAS_MFSRR0 = 1705 +PPC_INS_ALIAS_MTSRR1 = 1706 +PPC_INS_ALIAS_MFSRR1 = 1707 +PPC_INS_ALIAS_MTCFAR = 1708 +PPC_INS_ALIAS_MFCFAR = 1709 +PPC_INS_ALIAS_MTAMR = 1710 +PPC_INS_ALIAS_MFAMR = 1711 +PPC_INS_ALIAS_MFSPRG = 1712 +PPC_INS_ALIAS_MFSPRG0 = 1713 +PPC_INS_ALIAS_MTSPRG = 1714 +PPC_INS_ALIAS_MTSPRG0 = 1715 +PPC_INS_ALIAS_MFSPRG1 = 1716 +PPC_INS_ALIAS_MTSPRG1 = 1717 +PPC_INS_ALIAS_MFSPRG2 = 1718 +PPC_INS_ALIAS_MTSPRG2 = 1719 +PPC_INS_ALIAS_MFSPRG3 = 1720 +PPC_INS_ALIAS_MTSPRG3 = 1721 +PPC_INS_ALIAS_MFASR = 1722 +PPC_INS_ALIAS_MTASR = 1723 +PPC_INS_ALIAS_MTTBL = 1724 +PPC_INS_ALIAS_MTTBU = 1725 +PPC_INS_ALIAS_MFPVR = 1726 +PPC_INS_ALIAS_MFSPEFSCR = 1727 +PPC_INS_ALIAS_MTSPEFSCR = 1728 +PPC_INS_ALIAS_XVMOVDP = 1729 +PPC_INS_ALIAS_XVMOVSP = 1730 +PPC_INS_ALIAS_XXSPLTD = 1731 +PPC_INS_ALIAS_XXMRGHD = 1732 +PPC_INS_ALIAS_XXMRGLD = 1733 +PPC_INS_ALIAS_XXSWAPD = 1734 +PPC_INS_ALIAS_MFFPRD = 1735 +PPC_INS_ALIAS_MTFPRD = 1736 +PPC_INS_ALIAS_MFFPRWZ = 1737 +PPC_INS_ALIAS_MTFPRWA = 1738 +PPC_INS_ALIAS_MTFPRWZ = 1739 +PPC_INS_ALIAS_TEND_ = 1740 +PPC_INS_ALIAS_TENDALL_ = 1741 +PPC_INS_ALIAS_TSUSPEND_ = 1742 +PPC_INS_ALIAS_TRESUME_ = 1743 +PPC_INS_ALIAS_DCI = 1744 +PPC_INS_ALIAS_DCCCI = 1745 +PPC_INS_ALIAS_ICI = 1746 +PPC_INS_ALIAS_ICCCI = 1747 +PPC_INS_ALIAS_MTFSFI = 1748 +PPC_INS_ALIAS_MTFSFI_ = 1749 +PPC_INS_ALIAS_MTFSF = 1750 +PPC_INS_ALIAS_MTFSF_ = 1751 +PPC_INS_ALIAS_SC = 1752 +PPC_INS_ALIAS_SYNC = 1753 +PPC_INS_ALIAS_LWSYNC = 1754 +PPC_INS_ALIAS_PTESYNC = 1755 +PPC_INS_ALIAS_WAIT = 1756 +PPC_INS_ALIAS_WAITRSV = 1757 +PPC_INS_ALIAS_WAITIMPL = 1758 +PPC_INS_ALIAS_MBAR = 1759 +PPC_INS_ALIAS_CRSET = 1760 +PPC_INS_ALIAS_CRCLR = 1761 +PPC_INS_ALIAS_CRMOVE = 1762 +PPC_INS_ALIAS_CRNOT = 1763 +PPC_INS_ALIAS_MFTB = 1764 +PPC_INS_ALIAS_MFTBL = 1765 +PPC_INS_ALIAS_MFTBU = 1766 +PPC_INS_ALIAS_MFBR0 = 1767 +PPC_INS_ALIAS_MTBR0 = 1768 +PPC_INS_ALIAS_MFBR1 = 1769 +PPC_INS_ALIAS_MTBR1 = 1770 +PPC_INS_ALIAS_MFBR2 = 1771 +PPC_INS_ALIAS_MTBR2 = 1772 +PPC_INS_ALIAS_MFBR3 = 1773 +PPC_INS_ALIAS_MTBR3 = 1774 +PPC_INS_ALIAS_MFBR4 = 1775 +PPC_INS_ALIAS_MTBR4 = 1776 +PPC_INS_ALIAS_MFBR5 = 1777 +PPC_INS_ALIAS_MTBR5 = 1778 +PPC_INS_ALIAS_MFBR6 = 1779 +PPC_INS_ALIAS_MTBR6 = 1780 +PPC_INS_ALIAS_MFBR7 = 1781 +PPC_INS_ALIAS_MTBR7 = 1782 +PPC_INS_ALIAS_MTMSRD = 1783 +PPC_INS_ALIAS_MTMSR = 1784 +PPC_INS_ALIAS_MTPID = 1785 +PPC_INS_ALIAS_MFPID = 1786 +PPC_INS_ALIAS_MFSPRG4 = 1787 +PPC_INS_ALIAS_MTSPRG4 = 1788 +PPC_INS_ALIAS_MFSPRG5 = 1789 +PPC_INS_ALIAS_MTSPRG5 = 1790 +PPC_INS_ALIAS_MFSPRG6 = 1791 +PPC_INS_ALIAS_MTSPRG6 = 1792 +PPC_INS_ALIAS_MFSPRG7 = 1793 +PPC_INS_ALIAS_MTSPRG7 = 1794 +PPC_INS_ALIAS_MTDBATU = 1795 +PPC_INS_ALIAS_MFDBATU = 1796 +PPC_INS_ALIAS_MTDBATL = 1797 +PPC_INS_ALIAS_MFDBATL = 1798 +PPC_INS_ALIAS_MTIBATU = 1799 +PPC_INS_ALIAS_MFIBATU = 1800 +PPC_INS_ALIAS_MTIBATL = 1801 +PPC_INS_ALIAS_MFIBATL = 1802 +PPC_INS_ALIAS_MTPPR = 1803 +PPC_INS_ALIAS_MFPPR = 1804 +PPC_INS_ALIAS_MTESR = 1805 +PPC_INS_ALIAS_MFESR = 1806 +PPC_INS_ALIAS_MTDEAR = 1807 +PPC_INS_ALIAS_MFDEAR = 1808 +PPC_INS_ALIAS_MTTCR = 1809 +PPC_INS_ALIAS_MFTCR = 1810 +PPC_INS_ALIAS_MFTBHI = 1811 +PPC_INS_ALIAS_MTTBHI = 1812 +PPC_INS_ALIAS_MFTBLO = 1813 +PPC_INS_ALIAS_MTTBLO = 1814 +PPC_INS_ALIAS_MTSRR2 = 1815 +PPC_INS_ALIAS_MFSRR2 = 1816 +PPC_INS_ALIAS_MTSRR3 = 1817 +PPC_INS_ALIAS_MFSRR3 = 1818 +PPC_INS_ALIAS_MTDCCR = 1819 +PPC_INS_ALIAS_MFDCCR = 1820 +PPC_INS_ALIAS_MTICCR = 1821 +PPC_INS_ALIAS_MFICCR = 1822 +PPC_INS_ALIAS_TLBIE = 1823 +PPC_INS_ALIAS_TLBREHI = 1824 +PPC_INS_ALIAS_TLBRELO = 1825 +PPC_INS_ALIAS_TLBWEHI = 1826 +PPC_INS_ALIAS_TLBWELO = 1827 +PPC_INS_ALIAS_ROTLDI = 1828 +PPC_INS_ALIAS_ROTLDI_ = 1829 +PPC_INS_ALIAS_ROTLD = 1830 +PPC_INS_ALIAS_ROTLD_ = 1831 +PPC_INS_ALIAS_CLRLDI = 1832 +PPC_INS_ALIAS_CLRLDI_ = 1833 +PPC_INS_ALIAS_LNIA = 1834 +PPC_INS_ALIAS_BCp = 1835 +PPC_INS_ALIAS_BCAp = 1836 +PPC_INS_ALIAS_BCLp = 1837 +PPC_INS_ALIAS_BCLAp = 1838 +PPC_INS_ALIAS_BCm = 1839 +PPC_INS_ALIAS_BCAm = 1840 +PPC_INS_ALIAS_BCLm = 1841 +PPC_INS_ALIAS_BCLAm = 1842 +PPC_INS_ALIAS_BT = 1843 +PPC_INS_ALIAS_BTA = 1844 +PPC_INS_ALIAS_BTLR = 1845 +PPC_INS_ALIAS_BTL = 1846 +PPC_INS_ALIAS_BTLA = 1847 +PPC_INS_ALIAS_BTLRL = 1848 +PPC_INS_ALIAS_BTCTR = 1849 +PPC_INS_ALIAS_BTCTRL = 1850 +PPC_INS_ALIAS_BDZLR = 1851 +PPC_INS_ALIAS_BDZLRL = 1852 +PPC_INS_ALIAS_BDZL = 1853 +PPC_INS_ALIAS_BDZLA = 1854 +PPC_INS_ALIAS_BDZ = 1855 +PPC_INS_ALIAS_BDNZL = 1856 +PPC_INS_ALIAS_BDNZLA = 1857 +PPC_INS_ALIAS_BDNZ = 1858 +PPC_INS_ALIAS_BDZLp = 1859 +PPC_INS_ALIAS_BDZLAp = 1860 +PPC_INS_ALIAS_BDZp = 1861 +PPC_INS_ALIAS_BDNZLp = 1862 +PPC_INS_ALIAS_BDNZLAp = 1863 +PPC_INS_ALIAS_BDNZp = 1864 +PPC_INS_ALIAS_BDZLm = 1865 +PPC_INS_ALIAS_BDZLAm = 1866 +PPC_INS_ALIAS_BDZm = 1867 +PPC_INS_ALIAS_BDNZLm = 1868 +PPC_INS_ALIAS_BDNZLAm = 1869 +PPC_INS_ALIAS_BDNZm = 1870 +PPC_INS_ALIAS_BDNZLR = 1871 +PPC_INS_ALIAS_BDNZLRL = 1872 +PPC_INS_ALIAS_BDZLRp = 1873 +PPC_INS_ALIAS_BDZLRLp = 1874 +PPC_INS_ALIAS_BDNZLRp = 1875 +PPC_INS_ALIAS_BDNZLRLp = 1876 +PPC_INS_ALIAS_BDZLRm = 1877 +PPC_INS_ALIAS_BDZLRLm = 1878 +PPC_INS_ALIAS_BDNZLRm = 1879 +PPC_INS_ALIAS_BDNZLRLm = 1880 +PPC_INS_ALIAS_BF = 1881 +PPC_INS_ALIAS_BFA = 1882 +PPC_INS_ALIAS_BFLR = 1883 +PPC_INS_ALIAS_BFL = 1884 +PPC_INS_ALIAS_BFLA = 1885 +PPC_INS_ALIAS_BFLRL = 1886 +PPC_INS_ALIAS_BFCTR = 1887 +PPC_INS_ALIAS_BFCTRL = 1888 +PPC_INS_ALIAS_BTm = 1889 +PPC_INS_ALIAS_BTAm = 1890 +PPC_INS_ALIAS_BTLRm = 1891 +PPC_INS_ALIAS_BTLm = 1892 +PPC_INS_ALIAS_BTLAm = 1893 +PPC_INS_ALIAS_BTLRLm = 1894 +PPC_INS_ALIAS_BTCTRm = 1895 +PPC_INS_ALIAS_BTCTRLm = 1896 +PPC_INS_ALIAS_BFm = 1897 +PPC_INS_ALIAS_BFAm = 1898 +PPC_INS_ALIAS_BFLRm = 1899 +PPC_INS_ALIAS_BFLm = 1900 +PPC_INS_ALIAS_BFLAm = 1901 +PPC_INS_ALIAS_BFLRLm = 1902 +PPC_INS_ALIAS_BFCTRm = 1903 +PPC_INS_ALIAS_BFCTRLm = 1904 +PPC_INS_ALIAS_BTp = 1905 +PPC_INS_ALIAS_BTAp = 1906 +PPC_INS_ALIAS_BTLRp = 1907 +PPC_INS_ALIAS_BTLp = 1908 +PPC_INS_ALIAS_BTLAp = 1909 +PPC_INS_ALIAS_BTLRLp = 1910 +PPC_INS_ALIAS_BTCTRp = 1911 +PPC_INS_ALIAS_BTCTRLp = 1912 +PPC_INS_ALIAS_BFp = 1913 +PPC_INS_ALIAS_BFAp = 1914 +PPC_INS_ALIAS_BFLRp = 1915 +PPC_INS_ALIAS_BFLp = 1916 +PPC_INS_ALIAS_BFLAp = 1917 +PPC_INS_ALIAS_BFLRLp = 1918 +PPC_INS_ALIAS_BFCTRp = 1919 +PPC_INS_ALIAS_BFCTRLp = 1920 +PPC_INS_ALIAS_BDNZT = 1921 +PPC_INS_ALIAS_BDNZTA = 1922 +PPC_INS_ALIAS_BDNZTLR = 1923 +PPC_INS_ALIAS_BDNZTL = 1924 +PPC_INS_ALIAS_BDNZTLA = 1925 +PPC_INS_ALIAS_BDNZTLRL = 1926 +PPC_INS_ALIAS_BDNZF = 1927 +PPC_INS_ALIAS_BDNZFA = 1928 +PPC_INS_ALIAS_BDNZFLR = 1929 +PPC_INS_ALIAS_BDNZFL = 1930 +PPC_INS_ALIAS_BDNZFLA = 1931 +PPC_INS_ALIAS_BDNZFLRL = 1932 +PPC_INS_ALIAS_BDZT = 1933 +PPC_INS_ALIAS_BDZTA = 1934 +PPC_INS_ALIAS_BDZTLR = 1935 +PPC_INS_ALIAS_BDZTL = 1936 +PPC_INS_ALIAS_BDZTLA = 1937 +PPC_INS_ALIAS_BDZTLRL = 1938 +PPC_INS_ALIAS_BDZF = 1939 +PPC_INS_ALIAS_BDZFA = 1940 +PPC_INS_ALIAS_BDZFLR = 1941 +PPC_INS_ALIAS_BDZFL = 1942 +PPC_INS_ALIAS_BDZFLA = 1943 +PPC_INS_ALIAS_BDZFLRL = 1944 +PPC_INS_ALIAS_B = 1945 +PPC_INS_ALIAS_BA = 1946 +PPC_INS_ALIAS_BL = 1947 +PPC_INS_ALIAS_BLA = 1948 +PPC_INS_ALIAS_BLR = 1949 +PPC_INS_ALIAS_BLRL = 1950 +PPC_INS_ALIAS_BCTR = 1951 +PPC_INS_ALIAS_BCTRL = 1952 +PPC_INS_ALIAS_BLT = 1953 +PPC_INS_ALIAS_BLTA = 1954 +PPC_INS_ALIAS_BLTLR = 1955 +PPC_INS_ALIAS_BLTCTR = 1956 +PPC_INS_ALIAS_BLTL = 1957 +PPC_INS_ALIAS_BLTLA = 1958 +PPC_INS_ALIAS_BLTLRL = 1959 +PPC_INS_ALIAS_BLTCTRL = 1960 +PPC_INS_ALIAS_BLTm = 1961 +PPC_INS_ALIAS_BLTAm = 1962 +PPC_INS_ALIAS_BLTLRm = 1963 +PPC_INS_ALIAS_BLTCTRm = 1964 +PPC_INS_ALIAS_BLTLm = 1965 +PPC_INS_ALIAS_BLTLAm = 1966 +PPC_INS_ALIAS_BLTLRLm = 1967 +PPC_INS_ALIAS_BLTCTRLm = 1968 +PPC_INS_ALIAS_BLTp = 1969 +PPC_INS_ALIAS_BLTAp = 1970 +PPC_INS_ALIAS_BLTLRp = 1971 +PPC_INS_ALIAS_BLTCTRp = 1972 +PPC_INS_ALIAS_BLTLp = 1973 +PPC_INS_ALIAS_BLTLAp = 1974 +PPC_INS_ALIAS_BLTLRLp = 1975 +PPC_INS_ALIAS_BLTCTRLp = 1976 +PPC_INS_ALIAS_BGT = 1977 +PPC_INS_ALIAS_BGTA = 1978 +PPC_INS_ALIAS_BGTLR = 1979 +PPC_INS_ALIAS_BGTCTR = 1980 +PPC_INS_ALIAS_BGTL = 1981 +PPC_INS_ALIAS_BGTLA = 1982 +PPC_INS_ALIAS_BGTLRL = 1983 +PPC_INS_ALIAS_BGTCTRL = 1984 +PPC_INS_ALIAS_BGTm = 1985 +PPC_INS_ALIAS_BGTAm = 1986 +PPC_INS_ALIAS_BGTLRm = 1987 +PPC_INS_ALIAS_BGTCTRm = 1988 +PPC_INS_ALIAS_BGTLm = 1989 +PPC_INS_ALIAS_BGTLAm = 1990 +PPC_INS_ALIAS_BGTLRLm = 1991 +PPC_INS_ALIAS_BGTCTRLm = 1992 +PPC_INS_ALIAS_BGTp = 1993 +PPC_INS_ALIAS_BGTAp = 1994 +PPC_INS_ALIAS_BGTLRp = 1995 +PPC_INS_ALIAS_BGTCTRp = 1996 +PPC_INS_ALIAS_BGTLp = 1997 +PPC_INS_ALIAS_BGTLAp = 1998 +PPC_INS_ALIAS_BGTLRLp = 1999 +PPC_INS_ALIAS_BGTCTRLp = 2000 +PPC_INS_ALIAS_BEQ = 2001 +PPC_INS_ALIAS_BEQA = 2002 +PPC_INS_ALIAS_BEQLR = 2003 +PPC_INS_ALIAS_BEQCTR = 2004 +PPC_INS_ALIAS_BEQL = 2005 +PPC_INS_ALIAS_BEQLA = 2006 +PPC_INS_ALIAS_BEQLRL = 2007 +PPC_INS_ALIAS_BEQCTRL = 2008 +PPC_INS_ALIAS_BEQm = 2009 +PPC_INS_ALIAS_BEQAm = 2010 +PPC_INS_ALIAS_BEQLRm = 2011 +PPC_INS_ALIAS_BEQCTRm = 2012 +PPC_INS_ALIAS_BEQLm = 2013 +PPC_INS_ALIAS_BEQLAm = 2014 +PPC_INS_ALIAS_BEQLRLm = 2015 +PPC_INS_ALIAS_BEQCTRLm = 2016 +PPC_INS_ALIAS_BEQp = 2017 +PPC_INS_ALIAS_BEQAp = 2018 +PPC_INS_ALIAS_BEQLRp = 2019 +PPC_INS_ALIAS_BEQCTRp = 2020 +PPC_INS_ALIAS_BEQLp = 2021 +PPC_INS_ALIAS_BEQLAp = 2022 +PPC_INS_ALIAS_BEQLRLp = 2023 +PPC_INS_ALIAS_BEQCTRLp = 2024 +PPC_INS_ALIAS_BUN = 2025 +PPC_INS_ALIAS_BUNA = 2026 +PPC_INS_ALIAS_BUNLR = 2027 +PPC_INS_ALIAS_BUNCTR = 2028 +PPC_INS_ALIAS_BUNL = 2029 +PPC_INS_ALIAS_BUNLA = 2030 +PPC_INS_ALIAS_BUNLRL = 2031 +PPC_INS_ALIAS_BUNCTRL = 2032 +PPC_INS_ALIAS_BUNm = 2033 +PPC_INS_ALIAS_BUNAm = 2034 +PPC_INS_ALIAS_BUNLRm = 2035 +PPC_INS_ALIAS_BUNCTRm = 2036 +PPC_INS_ALIAS_BUNLm = 2037 +PPC_INS_ALIAS_BUNLAm = 2038 +PPC_INS_ALIAS_BUNLRLm = 2039 +PPC_INS_ALIAS_BUNCTRLm = 2040 +PPC_INS_ALIAS_BUNp = 2041 +PPC_INS_ALIAS_BUNAp = 2042 +PPC_INS_ALIAS_BUNLRp = 2043 +PPC_INS_ALIAS_BUNCTRp = 2044 +PPC_INS_ALIAS_BUNLp = 2045 +PPC_INS_ALIAS_BUNLAp = 2046 +PPC_INS_ALIAS_BUNLRLp = 2047 +PPC_INS_ALIAS_BUNCTRLp = 2048 +PPC_INS_ALIAS_BSO = 2049 +PPC_INS_ALIAS_BSOA = 2050 +PPC_INS_ALIAS_BSOLR = 2051 +PPC_INS_ALIAS_BSOCTR = 2052 +PPC_INS_ALIAS_BSOL = 2053 +PPC_INS_ALIAS_BSOLA = 2054 +PPC_INS_ALIAS_BSOLRL = 2055 +PPC_INS_ALIAS_BSOCTRL = 2056 +PPC_INS_ALIAS_BSOm = 2057 +PPC_INS_ALIAS_BSOAm = 2058 +PPC_INS_ALIAS_BSOLRm = 2059 +PPC_INS_ALIAS_BSOCTRm = 2060 +PPC_INS_ALIAS_BSOLm = 2061 +PPC_INS_ALIAS_BSOLAm = 2062 +PPC_INS_ALIAS_BSOLRLm = 2063 +PPC_INS_ALIAS_BSOCTRLm = 2064 +PPC_INS_ALIAS_BSOp = 2065 +PPC_INS_ALIAS_BSOAp = 2066 +PPC_INS_ALIAS_BSOLRp = 2067 +PPC_INS_ALIAS_BSOCTRp = 2068 +PPC_INS_ALIAS_BSOLp = 2069 +PPC_INS_ALIAS_BSOLAp = 2070 +PPC_INS_ALIAS_BSOLRLp = 2071 +PPC_INS_ALIAS_BSOCTRLp = 2072 +PPC_INS_ALIAS_BGE = 2073 +PPC_INS_ALIAS_BGEA = 2074 +PPC_INS_ALIAS_BGELR = 2075 +PPC_INS_ALIAS_BGECTR = 2076 +PPC_INS_ALIAS_BGEL = 2077 +PPC_INS_ALIAS_BGELA = 2078 +PPC_INS_ALIAS_BGELRL = 2079 +PPC_INS_ALIAS_BGECTRL = 2080 +PPC_INS_ALIAS_BGEm = 2081 +PPC_INS_ALIAS_BGEAm = 2082 +PPC_INS_ALIAS_BGELRm = 2083 +PPC_INS_ALIAS_BGECTRm = 2084 +PPC_INS_ALIAS_BGELm = 2085 +PPC_INS_ALIAS_BGELAm = 2086 +PPC_INS_ALIAS_BGELRLm = 2087 +PPC_INS_ALIAS_BGECTRLm = 2088 +PPC_INS_ALIAS_BGEp = 2089 +PPC_INS_ALIAS_BGEAp = 2090 +PPC_INS_ALIAS_BGELRp = 2091 +PPC_INS_ALIAS_BGECTRp = 2092 +PPC_INS_ALIAS_BGELp = 2093 +PPC_INS_ALIAS_BGELAp = 2094 +PPC_INS_ALIAS_BGELRLp = 2095 +PPC_INS_ALIAS_BGECTRLp = 2096 +PPC_INS_ALIAS_BNL = 2097 +PPC_INS_ALIAS_BNLA = 2098 +PPC_INS_ALIAS_BNLLR = 2099 +PPC_INS_ALIAS_BNLCTR = 2100 +PPC_INS_ALIAS_BNLL = 2101 +PPC_INS_ALIAS_BNLLA = 2102 +PPC_INS_ALIAS_BNLLRL = 2103 +PPC_INS_ALIAS_BNLCTRL = 2104 +PPC_INS_ALIAS_BNLm = 2105 +PPC_INS_ALIAS_BNLAm = 2106 +PPC_INS_ALIAS_BNLLRm = 2107 +PPC_INS_ALIAS_BNLCTRm = 2108 +PPC_INS_ALIAS_BNLLm = 2109 +PPC_INS_ALIAS_BNLLAm = 2110 +PPC_INS_ALIAS_BNLLRLm = 2111 +PPC_INS_ALIAS_BNLCTRLm = 2112 +PPC_INS_ALIAS_BNLp = 2113 +PPC_INS_ALIAS_BNLAp = 2114 +PPC_INS_ALIAS_BNLLRp = 2115 +PPC_INS_ALIAS_BNLCTRp = 2116 +PPC_INS_ALIAS_BNLLp = 2117 +PPC_INS_ALIAS_BNLLAp = 2118 +PPC_INS_ALIAS_BNLLRLp = 2119 +PPC_INS_ALIAS_BNLCTRLp = 2120 +PPC_INS_ALIAS_BLE = 2121 +PPC_INS_ALIAS_BLEA = 2122 +PPC_INS_ALIAS_BLELR = 2123 +PPC_INS_ALIAS_BLECTR = 2124 +PPC_INS_ALIAS_BLEL = 2125 +PPC_INS_ALIAS_BLELA = 2126 +PPC_INS_ALIAS_BLELRL = 2127 +PPC_INS_ALIAS_BLECTRL = 2128 +PPC_INS_ALIAS_BLEm = 2129 +PPC_INS_ALIAS_BLEAm = 2130 +PPC_INS_ALIAS_BLELRm = 2131 +PPC_INS_ALIAS_BLECTRm = 2132 +PPC_INS_ALIAS_BLELm = 2133 +PPC_INS_ALIAS_BLELAm = 2134 +PPC_INS_ALIAS_BLELRLm = 2135 +PPC_INS_ALIAS_BLECTRLm = 2136 +PPC_INS_ALIAS_BLEp = 2137 +PPC_INS_ALIAS_BLEAp = 2138 +PPC_INS_ALIAS_BLELRp = 2139 +PPC_INS_ALIAS_BLECTRp = 2140 +PPC_INS_ALIAS_BLELp = 2141 +PPC_INS_ALIAS_BLELAp = 2142 +PPC_INS_ALIAS_BLELRLp = 2143 +PPC_INS_ALIAS_BLECTRLp = 2144 +PPC_INS_ALIAS_BNG = 2145 +PPC_INS_ALIAS_BNGA = 2146 +PPC_INS_ALIAS_BNGLR = 2147 +PPC_INS_ALIAS_BNGCTR = 2148 +PPC_INS_ALIAS_BNGL = 2149 +PPC_INS_ALIAS_BNGLA = 2150 +PPC_INS_ALIAS_BNGLRL = 2151 +PPC_INS_ALIAS_BNGCTRL = 2152 +PPC_INS_ALIAS_BNGm = 2153 +PPC_INS_ALIAS_BNGAm = 2154 +PPC_INS_ALIAS_BNGLRm = 2155 +PPC_INS_ALIAS_BNGCTRm = 2156 +PPC_INS_ALIAS_BNGLm = 2157 +PPC_INS_ALIAS_BNGLAm = 2158 +PPC_INS_ALIAS_BNGLRLm = 2159 +PPC_INS_ALIAS_BNGCTRLm = 2160 +PPC_INS_ALIAS_BNGp = 2161 +PPC_INS_ALIAS_BNGAp = 2162 +PPC_INS_ALIAS_BNGLRp = 2163 +PPC_INS_ALIAS_BNGCTRp = 2164 +PPC_INS_ALIAS_BNGLp = 2165 +PPC_INS_ALIAS_BNGLAp = 2166 +PPC_INS_ALIAS_BNGLRLp = 2167 +PPC_INS_ALIAS_BNGCTRLp = 2168 +PPC_INS_ALIAS_BNE = 2169 +PPC_INS_ALIAS_BNEA = 2170 +PPC_INS_ALIAS_BNELR = 2171 +PPC_INS_ALIAS_BNECTR = 2172 +PPC_INS_ALIAS_BNEL = 2173 +PPC_INS_ALIAS_BNELA = 2174 +PPC_INS_ALIAS_BNELRL = 2175 +PPC_INS_ALIAS_BNECTRL = 2176 +PPC_INS_ALIAS_BNEm = 2177 +PPC_INS_ALIAS_BNEAm = 2178 +PPC_INS_ALIAS_BNELRm = 2179 +PPC_INS_ALIAS_BNECTRm = 2180 +PPC_INS_ALIAS_BNELm = 2181 +PPC_INS_ALIAS_BNELAm = 2182 +PPC_INS_ALIAS_BNELRLm = 2183 +PPC_INS_ALIAS_BNECTRLm = 2184 +PPC_INS_ALIAS_BNEp = 2185 +PPC_INS_ALIAS_BNEAp = 2186 +PPC_INS_ALIAS_BNELRp = 2187 +PPC_INS_ALIAS_BNECTRp = 2188 +PPC_INS_ALIAS_BNELp = 2189 +PPC_INS_ALIAS_BNELAp = 2190 +PPC_INS_ALIAS_BNELRLp = 2191 +PPC_INS_ALIAS_BNECTRLp = 2192 +PPC_INS_ALIAS_BNU = 2193 +PPC_INS_ALIAS_BNUA = 2194 +PPC_INS_ALIAS_BNULR = 2195 +PPC_INS_ALIAS_BNUCTR = 2196 +PPC_INS_ALIAS_BNUL = 2197 +PPC_INS_ALIAS_BNULA = 2198 +PPC_INS_ALIAS_BNULRL = 2199 +PPC_INS_ALIAS_BNUCTRL = 2200 +PPC_INS_ALIAS_BNUm = 2201 +PPC_INS_ALIAS_BNUAm = 2202 +PPC_INS_ALIAS_BNULRm = 2203 +PPC_INS_ALIAS_BNUCTRm = 2204 +PPC_INS_ALIAS_BNULm = 2205 +PPC_INS_ALIAS_BNULAm = 2206 +PPC_INS_ALIAS_BNULRLm = 2207 +PPC_INS_ALIAS_BNUCTRLm = 2208 +PPC_INS_ALIAS_BNUp = 2209 +PPC_INS_ALIAS_BNUAp = 2210 +PPC_INS_ALIAS_BNULRp = 2211 +PPC_INS_ALIAS_BNUCTRp = 2212 +PPC_INS_ALIAS_BNULp = 2213 +PPC_INS_ALIAS_BNULAp = 2214 +PPC_INS_ALIAS_BNULRLp = 2215 +PPC_INS_ALIAS_BNUCTRLp = 2216 +PPC_INS_ALIAS_BNS = 2217 +PPC_INS_ALIAS_BNSA = 2218 +PPC_INS_ALIAS_BNSLR = 2219 +PPC_INS_ALIAS_BNSCTR = 2220 +PPC_INS_ALIAS_BNSL = 2221 +PPC_INS_ALIAS_BNSLA = 2222 +PPC_INS_ALIAS_BNSLRL = 2223 +PPC_INS_ALIAS_BNSCTRL = 2224 +PPC_INS_ALIAS_BNSm = 2225 +PPC_INS_ALIAS_BNSAm = 2226 +PPC_INS_ALIAS_BNSLRm = 2227 +PPC_INS_ALIAS_BNSCTRm = 2228 +PPC_INS_ALIAS_BNSLm = 2229 +PPC_INS_ALIAS_BNSLAm = 2230 +PPC_INS_ALIAS_BNSLRLm = 2231 +PPC_INS_ALIAS_BNSCTRLm = 2232 +PPC_INS_ALIAS_BNSp = 2233 +PPC_INS_ALIAS_BNSAp = 2234 +PPC_INS_ALIAS_BNSLRp = 2235 +PPC_INS_ALIAS_BNSCTRp = 2236 +PPC_INS_ALIAS_BNSLp = 2237 +PPC_INS_ALIAS_BNSLAp = 2238 +PPC_INS_ALIAS_BNSLRLp = 2239 +PPC_INS_ALIAS_BNSCTRLp = 2240 +PPC_INS_ALIAS_CMPWI = 2241 +PPC_INS_ALIAS_CMPW = 2242 +PPC_INS_ALIAS_CMPLWI = 2243 +PPC_INS_ALIAS_CMPLW = 2244 +PPC_INS_ALIAS_CMPDI = 2245 +PPC_INS_ALIAS_CMPD = 2246 +PPC_INS_ALIAS_CMPLDI = 2247 +PPC_INS_ALIAS_CMPLD = 2248 +PPC_INS_ALIAS_CMPI = 2249 +PPC_INS_ALIAS_CMP = 2250 +PPC_INS_ALIAS_CMPLI = 2251 +PPC_INS_ALIAS_CMPL = 2252 +PPC_INS_ALIAS_TRAP = 2253 +PPC_INS_ALIAS_TDLTI = 2254 +PPC_INS_ALIAS_TDLT = 2255 +PPC_INS_ALIAS_TWLTI = 2256 +PPC_INS_ALIAS_TWLT = 2257 +PPC_INS_ALIAS_TDLEI = 2258 +PPC_INS_ALIAS_TDLE = 2259 +PPC_INS_ALIAS_TWLEI = 2260 +PPC_INS_ALIAS_TWLE = 2261 +PPC_INS_ALIAS_TDEQI = 2262 +PPC_INS_ALIAS_TDEQ = 2263 +PPC_INS_ALIAS_TWEQI = 2264 +PPC_INS_ALIAS_TWEQ = 2265 +PPC_INS_ALIAS_TDGEI = 2266 +PPC_INS_ALIAS_TDGE = 2267 +PPC_INS_ALIAS_TWGEI = 2268 +PPC_INS_ALIAS_TWGE = 2269 +PPC_INS_ALIAS_TDGTI = 2270 +PPC_INS_ALIAS_TDGT = 2271 +PPC_INS_ALIAS_TWGTI = 2272 +PPC_INS_ALIAS_TWGT = 2273 +PPC_INS_ALIAS_TDNLI = 2274 +PPC_INS_ALIAS_TDNL = 2275 +PPC_INS_ALIAS_TWNLI = 2276 +PPC_INS_ALIAS_TWNL = 2277 +PPC_INS_ALIAS_TDNEI = 2278 +PPC_INS_ALIAS_TDNE = 2279 +PPC_INS_ALIAS_TWNEI = 2280 +PPC_INS_ALIAS_TWNE = 2281 +PPC_INS_ALIAS_TDNGI = 2282 +PPC_INS_ALIAS_TDNG = 2283 +PPC_INS_ALIAS_TWNGI = 2284 +PPC_INS_ALIAS_TWNG = 2285 +PPC_INS_ALIAS_TDLLTI = 2286 +PPC_INS_ALIAS_TDLLT = 2287 +PPC_INS_ALIAS_TWLLTI = 2288 +PPC_INS_ALIAS_TWLLT = 2289 +PPC_INS_ALIAS_TDLLEI = 2290 +PPC_INS_ALIAS_TDLLE = 2291 +PPC_INS_ALIAS_TWLLEI = 2292 +PPC_INS_ALIAS_TWLLE = 2293 +PPC_INS_ALIAS_TDLGEI = 2294 +PPC_INS_ALIAS_TDLGE = 2295 +PPC_INS_ALIAS_TWLGEI = 2296 +PPC_INS_ALIAS_TWLGE = 2297 +PPC_INS_ALIAS_TDLGTI = 2298 +PPC_INS_ALIAS_TDLGT = 2299 +PPC_INS_ALIAS_TWLGTI = 2300 +PPC_INS_ALIAS_TWLGT = 2301 +PPC_INS_ALIAS_TDLNLI = 2302 +PPC_INS_ALIAS_TDLNL = 2303 +PPC_INS_ALIAS_TWLNLI = 2304 +PPC_INS_ALIAS_TWLNL = 2305 +PPC_INS_ALIAS_TDLNGI = 2306 +PPC_INS_ALIAS_TDLNG = 2307 +PPC_INS_ALIAS_TWLNGI = 2308 +PPC_INS_ALIAS_TWLNG = 2309 +PPC_INS_ALIAS_TDUI = 2310 +PPC_INS_ALIAS_TDU = 2311 +PPC_INS_ALIAS_TWUI = 2312 +PPC_INS_ALIAS_TWU = 2313 +PPC_INS_ALIAS_PASTE_ = 2314 +PPC_INS_ALIAS_QVFCLR = 2315 +PPC_INS_ALIAS_QVFAND = 2316 +PPC_INS_ALIAS_QVFANDC = 2317 +PPC_INS_ALIAS_QVFCTFB = 2318 +PPC_INS_ALIAS_QVFXOR = 2319 +PPC_INS_ALIAS_QVFOR = 2320 +PPC_INS_ALIAS_QVFNOR = 2321 +PPC_INS_ALIAS_QVFEQU = 2322 +PPC_INS_ALIAS_QVFNOT = 2323 +PPC_INS_ALIAS_QVFORC = 2324 +PPC_INS_ALIAS_QVFNAND = 2325 +PPC_INS_ALIAS_QVFSET = 2326 +PPC_INS_ALIAS_SLWI = 2327 +PPC_INS_ALIAS_SRWI = 2328 +PPC_INS_ALIAS_SLDI = 2329 +PPC_INS_ALIAS_END = 2330 PPC_GRP_INVALID = 0 PPC_GRP_JUMP = 1 @@ -2964,128 +2965,130 @@ PPC_FEATURE_HasQPX = 145 PPC_FEATURE_IsPPC6xx = 146 PPC_GRP_ENDING = 147 -PPC_INSN_FORM_XOFORM_1 = 148 -PPC_INSN_FORM_Z23FORM_RTAB5_CY2 = 149 -PPC_INSN_FORM_DFORM_BASE = 150 -PPC_INSN_FORM_DXFORM = 151 -PPC_INSN_FORM_XFORM_BASE_R3XO_SWAPPED = 152 -PPC_INSN_FORM_DFORM_4 = 153 -PPC_INSN_FORM_XFORM_ATTN = 154 -PPC_INSN_FORM_IFORM = 155 -PPC_INSN_FORM_VX_RD5_RSP5_PS1_XO9 = 156 -PPC_INSN_FORM_VX_RD5_EO5_RS5_PS1_XO9 = 157 -PPC_INSN_FORM_VXFORM_1 = 158 -PPC_INSN_FORM_XLFORM_2 = 159 -PPC_INSN_FORM_BFORM = 160 -PPC_INSN_FORM_EVXFORM_1 = 161 -PPC_INSN_FORM_XFORM_BASE_R3XO = 162 -PPC_INSN_FORM_XFORM_16 = 163 -PPC_INSN_FORM_DFORM_5 = 164 -PPC_INSN_FORM_X_BF3_RS5_RS5 = 165 -PPC_INSN_FORM_X_BF3_L1_RS5_RS5 = 166 -PPC_INSN_FORM_XLFORM_1 = 167 -PPC_INSN_FORM_XFORM_45 = 168 -PPC_INSN_FORM_DCB_FORM = 169 -PPC_INSN_FORM_DCB_FORM_HINT = 170 -PPC_INSN_FORM_XFORM_ATB3 = 171 -PPC_INSN_FORM_XFORM_AT3 = 172 -PPC_INSN_FORM_XX2FORM_AT3_XBP5_P2 = 173 -PPC_INSN_FORM_XX3FORM_AT3_XABP5_P1 = 174 -PPC_INSN_FORM_DSS_FORM = 175 -PPC_INSN_FORM_EFXFORM_1 = 176 -PPC_INSN_FORM_EFXFORM_3 = 177 -PPC_INSN_FORM_EVXFORM_3 = 178 -PPC_INSN_FORM_EVXFORM_D = 179 -PPC_INSN_FORM_EVXFORM_4 = 180 -PPC_INSN_FORM_XSFORM_1 = 181 -PPC_INSN_FORM_XFORM_24_SYNC = 182 -PPC_INSN_FORM_AFORM_1 = 183 -PPC_INSN_FORM_XFORM_17 = 184 -PPC_INSN_FORM_XFORM_XD6_RA5_RB5 = 185 -PPC_INSN_FORM_XFORM_ICBT = 186 -PPC_INSN_FORM_AFORM_4 = 187 -PPC_INSN_FORM_DFORM_1 = 188 -PPC_INSN_FORM_DSFORM_1 = 189 -PPC_INSN_FORM_DFORM_2_R0 = 190 -PPC_INSN_FORM_DQFORM_RTP5_RA17_MEM = 191 -PPC_INSN_FORM_XX1FORM = 192 -PPC_INSN_FORM_DQ_RD6_RS5_DQ12 = 193 -PPC_INSN_FORM_XFORM_XT6_IMM5 = 194 -PPC_INSN_FORM_DQFORM_XTP5_RA17_MEM = 195 -PPC_INSN_FORM_XFORMMEMOP = 196 -PPC_INSN_FORM_VAFORM_1A = 197 -PPC_INSN_FORM_XFORM_MBAR = 198 -PPC_INSN_FORM_XLFORM_3 = 199 -PPC_INSN_FORM_XFXFORM_3P = 200 -PPC_INSN_FORM_XFXFORM_3 = 201 -PPC_INSN_FORM_XFXFORM_1 = 202 -PPC_INSN_FORM_XFXFORM_5A = 203 -PPC_INSN_FORM_XFORM_SR = 204 -PPC_INSN_FORM_XFORM_SRIN = 205 -PPC_INSN_FORM_VXFORM_4 = 206 -PPC_INSN_FORM_XFXFORM_5 = 207 -PPC_INSN_FORM_XFLFORM_1 = 208 -PPC_INSN_FORM_XLFORM_4 = 209 -PPC_INSN_FORM_XFORM_MTMSR = 210 -PPC_INSN_FORM_VXFORM_5 = 211 -PPC_INSN_FORM_VXFORM_RD5_XO5_RS5 = 212 -PPC_INSN_FORM_DCBZL_FORM = 213 -PPC_INSN_FORM_PSFORM_QD = 214 -PPC_INSN_FORM_PSFORM_QI = 215 -PPC_INSN_FORM_PSFORM_Y = 216 -PPC_INSN_FORM_PSFORM_X = 217 -PPC_INSN_FORM_PSFORM_C = 218 -PPC_INSN_FORM_Z23FORM_1 = 219 -PPC_INSN_FORM_XFORM_18 = 220 -PPC_INSN_FORM_XFORM_20 = 221 -PPC_INSN_FORM_Z23FORM_3 = 222 -PPC_INSN_FORM_XLFORM_S = 223 -PPC_INSN_FORM_MDSFORM_1 = 224 -PPC_INSN_FORM_MDFORM_1 = 225 -PPC_INSN_FORM_MFORM_1 = 226 -PPC_INSN_FORM_SCFORM = 227 -PPC_INSN_FORM_XFORM_44 = 228 -PPC_INSN_FORM_XOFORM_RTAB5_L1 = 229 -PPC_INSN_FORM_XFORM_HTM0 = 230 -PPC_INSN_FORM_XFORM_HTM3 = 231 -PPC_INSN_FORM_XFORM_HTM1 = 232 -PPC_INSN_FORM_XFORM_TLBWS = 233 -PPC_INSN_FORM_XFORM_24 = 234 -PPC_INSN_FORM_XFORM_HTM2 = 235 -PPC_INSN_FORM_VXFORM_2 = 236 -PPC_INSN_FORM_VXRFORM_1 = 237 -PPC_INSN_FORM_VXFORM_BF3_VAB5 = 238 -PPC_INSN_FORM_VXFORM_RD5_MP_VB5 = 239 -PPC_INSN_FORM_VXFORM_RD5_N3_VB5 = 240 -PPC_INSN_FORM_VAFORM_1 = 241 -PPC_INSN_FORM_VXFORM_BX = 242 -PPC_INSN_FORM_VXFORM_CR = 243 -PPC_INSN_FORM_VNFORM_VTAB5_SD3 = 244 -PPC_INSN_FORM_VAFORM_2 = 245 -PPC_INSN_FORM_VXFORM_3 = 246 -PPC_INSN_FORM_VXFORM_VTB5_RC = 247 -PPC_INSN_FORM_REQUIRES = 248 -PPC_INSN_FORM_XX2FORM = 249 -PPC_INSN_FORM_XX3FORM = 250 -PPC_INSN_FORM_XX3FORM_1 = 251 -PPC_INSN_FORM_XX2_RD6_XO5_RS6 = 252 -PPC_INSN_FORM_Z23FORM_8 = 253 -PPC_INSN_FORM_XX2FORM_1 = 254 -PPC_INSN_FORM_XX2_BF3_DCMX7_RS6 = 255 -PPC_INSN_FORM_X_BF3_DCMX7_RS5 = 256 -PPC_INSN_FORM_XX2_RD5_XO5_RS6 = 257 -PPC_INSN_FORM_XX3FORM_AT3_XAB6 = 258 -PPC_INSN_FORM_XX3FORM_RC = 259 -PPC_INSN_FORM_XX2_BF3_XO5_XB6_XO9 = 260 -PPC_INSN_FORM_XX2_RD6_DCMX7_RS6 = 261 -PPC_INSN_FORM_XX2_RD6_UIM5_RS6 = 262 -PPC_INSN_FORM_XFORM_XT6_IMM5_VB5 = 263 -PPC_INSN_FORM_XX3FORM_2 = 264 -PPC_INSN_FORM_XX4FORM = 265 -PPC_INSN_FORM_X_RD6_IMM8 = 266 -PPC_INSN_FORM_XX2FORM_2 = 267 -PPC_INSN_FORM_BFORM_3 = 268 -PPC_INSN_FORM_BFORM_3_AT = 269 + +PPC_INSN_FORM_INVALID = 0 +PPC_INSN_FORM_XOFORM_1 = 1 +PPC_INSN_FORM_Z23FORM_RTAB5_CY2 = 2 +PPC_INSN_FORM_DFORM_BASE = 3 +PPC_INSN_FORM_DXFORM = 4 +PPC_INSN_FORM_XFORM_BASE_R3XO_SWAPPED = 5 +PPC_INSN_FORM_DFORM_4 = 6 +PPC_INSN_FORM_XFORM_ATTN = 7 +PPC_INSN_FORM_IFORM = 8 +PPC_INSN_FORM_VX_RD5_RSP5_PS1_XO9 = 9 +PPC_INSN_FORM_VX_RD5_EO5_RS5_PS1_XO9 = 10 +PPC_INSN_FORM_VXFORM_1 = 11 +PPC_INSN_FORM_XLFORM_2 = 12 +PPC_INSN_FORM_BFORM = 13 +PPC_INSN_FORM_EVXFORM_1 = 14 +PPC_INSN_FORM_XFORM_BASE_R3XO = 15 +PPC_INSN_FORM_XFORM_16 = 16 +PPC_INSN_FORM_DFORM_5 = 17 +PPC_INSN_FORM_X_BF3_RS5_RS5 = 18 +PPC_INSN_FORM_X_BF3_L1_RS5_RS5 = 19 +PPC_INSN_FORM_XLFORM_1 = 20 +PPC_INSN_FORM_XFORM_45 = 21 +PPC_INSN_FORM_DCB_FORM = 22 +PPC_INSN_FORM_DCB_FORM_HINT = 23 +PPC_INSN_FORM_XFORM_ATB3 = 24 +PPC_INSN_FORM_XFORM_AT3 = 25 +PPC_INSN_FORM_XX2FORM_AT3_XBP5_P2 = 26 +PPC_INSN_FORM_XX3FORM_AT3_XABP5_P1 = 27 +PPC_INSN_FORM_DSS_FORM = 28 +PPC_INSN_FORM_EFXFORM_1 = 29 +PPC_INSN_FORM_EFXFORM_3 = 30 +PPC_INSN_FORM_EVXFORM_3 = 31 +PPC_INSN_FORM_EVXFORM_D = 32 +PPC_INSN_FORM_EVXFORM_4 = 33 +PPC_INSN_FORM_XSFORM_1 = 34 +PPC_INSN_FORM_XFORM_24_SYNC = 35 +PPC_INSN_FORM_AFORM_1 = 36 +PPC_INSN_FORM_XFORM_17 = 37 +PPC_INSN_FORM_XFORM_XD6_RA5_RB5 = 38 +PPC_INSN_FORM_XFORM_ICBT = 39 +PPC_INSN_FORM_AFORM_4 = 40 +PPC_INSN_FORM_DFORM_1 = 41 +PPC_INSN_FORM_DSFORM_1 = 42 +PPC_INSN_FORM_DFORM_2_R0 = 43 +PPC_INSN_FORM_DQFORM_RTP5_RA17_MEM = 44 +PPC_INSN_FORM_XX1FORM = 45 +PPC_INSN_FORM_DQ_RD6_RS5_DQ12 = 46 +PPC_INSN_FORM_XFORM_XT6_IMM5 = 47 +PPC_INSN_FORM_DQFORM_XTP5_RA17_MEM = 48 +PPC_INSN_FORM_XFORMMEMOP = 49 +PPC_INSN_FORM_VAFORM_1A = 50 +PPC_INSN_FORM_XFORM_MBAR = 51 +PPC_INSN_FORM_XLFORM_3 = 52 +PPC_INSN_FORM_XFXFORM_3P = 53 +PPC_INSN_FORM_XFXFORM_3 = 54 +PPC_INSN_FORM_XFXFORM_1 = 55 +PPC_INSN_FORM_XFXFORM_5A = 56 +PPC_INSN_FORM_XFORM_SR = 57 +PPC_INSN_FORM_XFORM_SRIN = 58 +PPC_INSN_FORM_VXFORM_4 = 59 +PPC_INSN_FORM_XFXFORM_5 = 60 +PPC_INSN_FORM_XFLFORM_1 = 61 +PPC_INSN_FORM_XLFORM_4 = 62 +PPC_INSN_FORM_XFORM_MTMSR = 63 +PPC_INSN_FORM_VXFORM_5 = 64 +PPC_INSN_FORM_VXFORM_RD5_XO5_RS5 = 65 +PPC_INSN_FORM_DCBZL_FORM = 66 +PPC_INSN_FORM_PSFORM_QD = 67 +PPC_INSN_FORM_PSFORM_QI = 68 +PPC_INSN_FORM_PSFORM_Y = 69 +PPC_INSN_FORM_PSFORM_X = 70 +PPC_INSN_FORM_PSFORM_C = 71 +PPC_INSN_FORM_Z23FORM_1 = 72 +PPC_INSN_FORM_XFORM_18 = 73 +PPC_INSN_FORM_XFORM_20 = 74 +PPC_INSN_FORM_Z23FORM_3 = 75 +PPC_INSN_FORM_XLFORM_S = 76 +PPC_INSN_FORM_MDSFORM_1 = 77 +PPC_INSN_FORM_MDFORM_1 = 78 +PPC_INSN_FORM_MFORM_1 = 79 +PPC_INSN_FORM_SCFORM = 80 +PPC_INSN_FORM_XFORM_44 = 81 +PPC_INSN_FORM_XOFORM_RTAB5_L1 = 82 +PPC_INSN_FORM_XFORM_HTM0 = 83 +PPC_INSN_FORM_XFORM_HTM3 = 84 +PPC_INSN_FORM_XFORM_HTM1 = 85 +PPC_INSN_FORM_XFORM_TLBWS = 86 +PPC_INSN_FORM_XFORM_24 = 87 +PPC_INSN_FORM_XFORM_HTM2 = 88 +PPC_INSN_FORM_VXFORM_2 = 89 +PPC_INSN_FORM_VXRFORM_1 = 90 +PPC_INSN_FORM_VXFORM_BF3_VAB5 = 91 +PPC_INSN_FORM_VXFORM_RD5_MP_VB5 = 92 +PPC_INSN_FORM_VXFORM_RD5_N3_VB5 = 93 +PPC_INSN_FORM_VAFORM_1 = 94 +PPC_INSN_FORM_VXFORM_BX = 95 +PPC_INSN_FORM_VXFORM_CR = 96 +PPC_INSN_FORM_VNFORM_VTAB5_SD3 = 97 +PPC_INSN_FORM_VAFORM_2 = 98 +PPC_INSN_FORM_VXFORM_3 = 99 +PPC_INSN_FORM_VXFORM_VTB5_RC = 100 +PPC_INSN_FORM_REQUIRES = 101 +PPC_INSN_FORM_XX2FORM = 102 +PPC_INSN_FORM_XX3FORM = 103 +PPC_INSN_FORM_XX3FORM_1 = 104 +PPC_INSN_FORM_XX2_RD6_XO5_RS6 = 105 +PPC_INSN_FORM_Z23FORM_8 = 106 +PPC_INSN_FORM_XX2FORM_1 = 107 +PPC_INSN_FORM_XX2_BF3_DCMX7_RS6 = 108 +PPC_INSN_FORM_X_BF3_DCMX7_RS5 = 109 +PPC_INSN_FORM_XX2_RD5_XO5_RS6 = 110 +PPC_INSN_FORM_XX3FORM_AT3_XAB6 = 111 +PPC_INSN_FORM_XX3FORM_RC = 112 +PPC_INSN_FORM_XX2_BF3_XO5_XB6_XO9 = 113 +PPC_INSN_FORM_XX2_RD6_DCMX7_RS6 = 114 +PPC_INSN_FORM_XX2_RD6_UIM5_RS6 = 115 +PPC_INSN_FORM_XFORM_XT6_IMM5_VB5 = 116 +PPC_INSN_FORM_XX3FORM_2 = 117 +PPC_INSN_FORM_XX4FORM = 118 +PPC_INSN_FORM_X_RD6_IMM8 = 119 +PPC_INSN_FORM_XX2FORM_2 = 120 +PPC_INSN_FORM_BFORM_3 = 121 +PPC_INSN_FORM_BFORM_3_AT = 122 PPC_INSN_FORM_B_BO_MASK = 0x03e00000 PPC_INSN_FORM_XL_BO_MASK = 0x03e00000 PPC_INSN_FORM_B_BI_MASK = 0x001f0000 diff --git a/bindings/python/capstone/sh_const.py b/bindings/python/capstone/sh_const.py index da02844bdd..5a1f05193b 100644 --- a/bindings/python/capstone/sh_const.py +++ b/bindings/python/capstone/sh_const.py @@ -140,10 +140,11 @@ SH_OP_MEM_GBR_R0 = 7 SH_OP_MEM_PCR = 8 SH_OP_MEM_TBR_DISP = 9 -SH_INS_DSP_INVALID = 10 -SH_INS_DSP_DOUBLE = 11 -SH_INS_DSP_SINGLE = 12 -SH_INS_DSP_PARALLEL = 13 + +SH_INS_DSP_INVALID = 0 +SH_INS_DSP_DOUBLE = 1 +SH_INS_DSP_SINGLE = 2 +SH_INS_DSP_PARALLEL = 3 SH_INS_DSP_NOP = 1 SH_INS_DSP_MOV = 2 SH_INS_DSP_PSHL = 3 @@ -174,177 +175,180 @@ SH_INS_DSP_PSWAP = 28 SH_INS_DSP_PWAD = 29 SH_INS_DSP_PWSB = 30 -SH_OP_DSP_INVALID = 31 -SH_OP_DSP_REG_PRE = 32 -SH_OP_DSP_REG_IND = 33 -SH_OP_DSP_REG_POST = 34 -SH_OP_DSP_REG_INDEX = 35 -SH_OP_DSP_REG = 36 -SH_OP_DSP_IMM = 37 -SH_DSP_CC_INVALID = 38 -SH_DSP_CC_NONE = 39 -SH_DSP_CC_DCT = 40 -SH_DSP_CC_DCF = 41 -SH_INS_INVALID = 42 -SH_INS_ADD_r = 43 -SH_INS_ADD = 44 -SH_INS_ADDC = 45 -SH_INS_ADDV = 46 -SH_INS_AND = 47 -SH_INS_BAND = 48 -SH_INS_BANDNOT = 49 -SH_INS_BCLR = 50 -SH_INS_BF = 51 -SH_INS_BF_S = 52 -SH_INS_BLD = 53 -SH_INS_BLDNOT = 54 -SH_INS_BOR = 55 -SH_INS_BORNOT = 56 -SH_INS_BRA = 57 -SH_INS_BRAF = 58 -SH_INS_BSET = 59 -SH_INS_BSR = 60 -SH_INS_BSRF = 61 -SH_INS_BST = 62 -SH_INS_BT = 63 -SH_INS_BT_S = 64 -SH_INS_BXOR = 65 -SH_INS_CLIPS = 66 -SH_INS_CLIPU = 67 -SH_INS_CLRDMXY = 68 -SH_INS_CLRMAC = 69 -SH_INS_CLRS = 70 -SH_INS_CLRT = 71 -SH_INS_CMP_EQ = 72 -SH_INS_CMP_GE = 73 -SH_INS_CMP_GT = 74 -SH_INS_CMP_HI = 75 -SH_INS_CMP_HS = 76 -SH_INS_CMP_PL = 77 -SH_INS_CMP_PZ = 78 -SH_INS_CMP_STR = 79 -SH_INS_DIV0S = 80 -SH_INS_DIV0U = 81 -SH_INS_DIV1 = 82 -SH_INS_DIVS = 83 -SH_INS_DIVU = 84 -SH_INS_DMULS_L = 85 -SH_INS_DMULU_L = 86 -SH_INS_DT = 87 -SH_INS_EXTS_B = 88 -SH_INS_EXTS_W = 89 -SH_INS_EXTU_B = 90 -SH_INS_EXTU_W = 91 -SH_INS_FABS = 92 -SH_INS_FADD = 93 -SH_INS_FCMP_EQ = 94 -SH_INS_FCMP_GT = 95 -SH_INS_FCNVDS = 96 -SH_INS_FCNVSD = 97 -SH_INS_FDIV = 98 -SH_INS_FIPR = 99 -SH_INS_FLDI0 = 100 -SH_INS_FLDI1 = 101 -SH_INS_FLDS = 102 -SH_INS_FLOAT = 103 -SH_INS_FMAC = 104 -SH_INS_FMOV = 105 -SH_INS_FMUL = 106 -SH_INS_FNEG = 107 -SH_INS_FPCHG = 108 -SH_INS_FRCHG = 109 -SH_INS_FSCA = 110 -SH_INS_FSCHG = 111 -SH_INS_FSQRT = 112 -SH_INS_FSRRA = 113 -SH_INS_FSTS = 114 -SH_INS_FSUB = 115 -SH_INS_FTRC = 116 -SH_INS_FTRV = 117 -SH_INS_ICBI = 118 -SH_INS_JMP = 119 -SH_INS_JSR = 120 -SH_INS_JSR_N = 121 -SH_INS_LDBANK = 122 -SH_INS_LDC = 123 -SH_INS_LDRC = 124 -SH_INS_LDRE = 125 -SH_INS_LDRS = 126 -SH_INS_LDS = 127 -SH_INS_LDTLB = 128 -SH_INS_MAC_L = 129 -SH_INS_MAC_W = 130 -SH_INS_MOV = 131 -SH_INS_MOVA = 132 -SH_INS_MOVCA = 133 -SH_INS_MOVCO = 134 -SH_INS_MOVI20 = 135 -SH_INS_MOVI20S = 136 -SH_INS_MOVLI = 137 -SH_INS_MOVML = 138 -SH_INS_MOVMU = 139 -SH_INS_MOVRT = 140 -SH_INS_MOVT = 141 -SH_INS_MOVU = 142 -SH_INS_MOVUA = 143 -SH_INS_MUL_L = 144 -SH_INS_MULR = 145 -SH_INS_MULS_W = 146 -SH_INS_MULU_W = 147 -SH_INS_NEG = 148 -SH_INS_NEGC = 149 -SH_INS_NOP = 150 -SH_INS_NOT = 151 -SH_INS_NOTT = 152 -SH_INS_OCBI = 153 -SH_INS_OCBP = 154 -SH_INS_OCBWB = 155 -SH_INS_OR = 156 -SH_INS_PREF = 157 -SH_INS_PREFI = 158 -SH_INS_RESBANK = 159 -SH_INS_ROTCL = 160 -SH_INS_ROTCR = 161 -SH_INS_ROTL = 162 -SH_INS_ROTR = 163 -SH_INS_RTE = 164 -SH_INS_RTS = 165 -SH_INS_RTS_N = 166 -SH_INS_RTV_N = 167 -SH_INS_SETDMX = 168 -SH_INS_SETDMY = 169 -SH_INS_SETRC = 170 -SH_INS_SETS = 171 -SH_INS_SETT = 172 -SH_INS_SHAD = 173 -SH_INS_SHAL = 174 -SH_INS_SHAR = 175 -SH_INS_SHLD = 176 -SH_INS_SHLL = 177 -SH_INS_SHLL16 = 178 -SH_INS_SHLL2 = 179 -SH_INS_SHLL8 = 180 -SH_INS_SHLR = 181 -SH_INS_SHLR16 = 182 -SH_INS_SHLR2 = 183 -SH_INS_SHLR8 = 184 -SH_INS_SLEEP = 185 -SH_INS_STBANK = 186 -SH_INS_STC = 187 -SH_INS_STS = 188 -SH_INS_SUB = 189 -SH_INS_SUBC = 190 -SH_INS_SUBV = 191 -SH_INS_SWAP_B = 192 -SH_INS_SWAP_W = 193 -SH_INS_SYNCO = 194 -SH_INS_TAS = 195 -SH_INS_TRAPA = 196 -SH_INS_TST = 197 -SH_INS_XOR = 198 -SH_INS_XTRCT = 199 -SH_INS_DSP = 200 -SH_INS_ENDING = 201 + +SH_OP_DSP_INVALID = 0 +SH_OP_DSP_REG_PRE = 1 +SH_OP_DSP_REG_IND = 2 +SH_OP_DSP_REG_POST = 3 +SH_OP_DSP_REG_INDEX = 4 +SH_OP_DSP_REG = 5 +SH_OP_DSP_IMM = 6 + +SH_DSP_CC_INVALID = 0 +SH_DSP_CC_NONE = 1 +SH_DSP_CC_DCT = 2 +SH_DSP_CC_DCF = 3 + +SH_INS_INVALID = 0 +SH_INS_ADD_r = 1 +SH_INS_ADD = 2 +SH_INS_ADDC = 3 +SH_INS_ADDV = 4 +SH_INS_AND = 5 +SH_INS_BAND = 6 +SH_INS_BANDNOT = 7 +SH_INS_BCLR = 8 +SH_INS_BF = 9 +SH_INS_BF_S = 10 +SH_INS_BLD = 11 +SH_INS_BLDNOT = 12 +SH_INS_BOR = 13 +SH_INS_BORNOT = 14 +SH_INS_BRA = 15 +SH_INS_BRAF = 16 +SH_INS_BSET = 17 +SH_INS_BSR = 18 +SH_INS_BSRF = 19 +SH_INS_BST = 20 +SH_INS_BT = 21 +SH_INS_BT_S = 22 +SH_INS_BXOR = 23 +SH_INS_CLIPS = 24 +SH_INS_CLIPU = 25 +SH_INS_CLRDMXY = 26 +SH_INS_CLRMAC = 27 +SH_INS_CLRS = 28 +SH_INS_CLRT = 29 +SH_INS_CMP_EQ = 30 +SH_INS_CMP_GE = 31 +SH_INS_CMP_GT = 32 +SH_INS_CMP_HI = 33 +SH_INS_CMP_HS = 34 +SH_INS_CMP_PL = 35 +SH_INS_CMP_PZ = 36 +SH_INS_CMP_STR = 37 +SH_INS_DIV0S = 38 +SH_INS_DIV0U = 39 +SH_INS_DIV1 = 40 +SH_INS_DIVS = 41 +SH_INS_DIVU = 42 +SH_INS_DMULS_L = 43 +SH_INS_DMULU_L = 44 +SH_INS_DT = 45 +SH_INS_EXTS_B = 46 +SH_INS_EXTS_W = 47 +SH_INS_EXTU_B = 48 +SH_INS_EXTU_W = 49 +SH_INS_FABS = 50 +SH_INS_FADD = 51 +SH_INS_FCMP_EQ = 52 +SH_INS_FCMP_GT = 53 +SH_INS_FCNVDS = 54 +SH_INS_FCNVSD = 55 +SH_INS_FDIV = 56 +SH_INS_FIPR = 57 +SH_INS_FLDI0 = 58 +SH_INS_FLDI1 = 59 +SH_INS_FLDS = 60 +SH_INS_FLOAT = 61 +SH_INS_FMAC = 62 +SH_INS_FMOV = 63 +SH_INS_FMUL = 64 +SH_INS_FNEG = 65 +SH_INS_FPCHG = 66 +SH_INS_FRCHG = 67 +SH_INS_FSCA = 68 +SH_INS_FSCHG = 69 +SH_INS_FSQRT = 70 +SH_INS_FSRRA = 71 +SH_INS_FSTS = 72 +SH_INS_FSUB = 73 +SH_INS_FTRC = 74 +SH_INS_FTRV = 75 +SH_INS_ICBI = 76 +SH_INS_JMP = 77 +SH_INS_JSR = 78 +SH_INS_JSR_N = 79 +SH_INS_LDBANK = 80 +SH_INS_LDC = 81 +SH_INS_LDRC = 82 +SH_INS_LDRE = 83 +SH_INS_LDRS = 84 +SH_INS_LDS = 85 +SH_INS_LDTLB = 86 +SH_INS_MAC_L = 87 +SH_INS_MAC_W = 88 +SH_INS_MOV = 89 +SH_INS_MOVA = 90 +SH_INS_MOVCA = 91 +SH_INS_MOVCO = 92 +SH_INS_MOVI20 = 93 +SH_INS_MOVI20S = 94 +SH_INS_MOVLI = 95 +SH_INS_MOVML = 96 +SH_INS_MOVMU = 97 +SH_INS_MOVRT = 98 +SH_INS_MOVT = 99 +SH_INS_MOVU = 100 +SH_INS_MOVUA = 101 +SH_INS_MUL_L = 102 +SH_INS_MULR = 103 +SH_INS_MULS_W = 104 +SH_INS_MULU_W = 105 +SH_INS_NEG = 106 +SH_INS_NEGC = 107 +SH_INS_NOP = 108 +SH_INS_NOT = 109 +SH_INS_NOTT = 110 +SH_INS_OCBI = 111 +SH_INS_OCBP = 112 +SH_INS_OCBWB = 113 +SH_INS_OR = 114 +SH_INS_PREF = 115 +SH_INS_PREFI = 116 +SH_INS_RESBANK = 117 +SH_INS_ROTCL = 118 +SH_INS_ROTCR = 119 +SH_INS_ROTL = 120 +SH_INS_ROTR = 121 +SH_INS_RTE = 122 +SH_INS_RTS = 123 +SH_INS_RTS_N = 124 +SH_INS_RTV_N = 125 +SH_INS_SETDMX = 126 +SH_INS_SETDMY = 127 +SH_INS_SETRC = 128 +SH_INS_SETS = 129 +SH_INS_SETT = 130 +SH_INS_SHAD = 131 +SH_INS_SHAL = 132 +SH_INS_SHAR = 133 +SH_INS_SHLD = 134 +SH_INS_SHLL = 135 +SH_INS_SHLL16 = 136 +SH_INS_SHLL2 = 137 +SH_INS_SHLL8 = 138 +SH_INS_SHLR = 139 +SH_INS_SHLR16 = 140 +SH_INS_SHLR2 = 141 +SH_INS_SHLR8 = 142 +SH_INS_SLEEP = 143 +SH_INS_STBANK = 144 +SH_INS_STC = 145 +SH_INS_STS = 146 +SH_INS_SUB = 147 +SH_INS_SUBC = 148 +SH_INS_SUBV = 149 +SH_INS_SWAP_B = 150 +SH_INS_SWAP_W = 151 +SH_INS_SYNCO = 152 +SH_INS_TAS = 153 +SH_INS_TRAPA = 154 +SH_INS_TST = 155 +SH_INS_XOR = 156 +SH_INS_XTRCT = 157 +SH_INS_DSP = 158 +SH_INS_ENDING = 159 SH_GRP_INVALID = 0 SH_GRP_JUMP = 1 diff --git a/bindings/python/capstone/sparc_const.py b/bindings/python/capstone/sparc_const.py index e009800e77..19de48d73f 100644 --- a/bindings/python/capstone/sparc_const.py +++ b/bindings/python/capstone/sparc_const.py @@ -39,6 +39,8 @@ SPARC_HINT_A = 1<<0 SPARC_HINT_PT = 1<<1 SPARC_HINT_PN = 1<<2 +SPARC_HINT_A_PN = SPARC_HINT_A|SPARC_HINT_PN +SPARC_HINT_A_PT = SPARC_HINT_A|SPARC_HINT_PT SPARC_OP_INVALID = 0 SPARC_OP_REG = 1 diff --git a/bindings/python/capstone/tricore_const.py b/bindings/python/capstone/tricore_const.py index 5a7a7f7ea0..3353f32093 100644 --- a/bindings/python/capstone/tricore_const.py +++ b/bindings/python/capstone/tricore_const.py @@ -461,10 +461,11 @@ TRICORE_INS_XOR_NE = 389 TRICORE_INS_XOR = 390 TRICORE_INS_ENDING = 391 -TRICORE_GRP_INVALID = 392 -TRICORE_GRP_CALL = 393 -TRICORE_GRP_JUMP = 394 -TRICORE_GRP_ENDING = 395 + +TRICORE_GRP_INVALID = 0 +TRICORE_GRP_CALL = 1 +TRICORE_GRP_JUMP = 2 +TRICORE_GRP_ENDING = 3 TRICORE_FEATURE_INVALID = 0 TRICORE_FEATURE_HasV110 = 128 diff --git a/bindings/python/capstone/x86_const.py b/bindings/python/capstone/x86_const.py index 0f193a50c0..ae3f93c30e 100644 --- a/bindings/python/capstone/x86_const.py +++ b/bindings/python/capstone/x86_const.py @@ -398,6 +398,7 @@ X86_AVX_RM_RD = 2 X86_AVX_RM_RU = 3 X86_AVX_RM_RZ = 4 +X86_PREFIX_0 = 0x0 X86_PREFIX_LOCK = 0xf0 X86_PREFIX_REP = 0xf3 X86_PREFIX_REPE = 0xf3 diff --git a/bindings/python/cstest_py/README.md b/bindings/python/cstest_py/README.md new file mode 100644 index 0000000000..e6587450da --- /dev/null +++ b/bindings/python/cstest_py/README.md @@ -0,0 +1,4 @@ +## Python cstest + +This is the equivalent testing tool to `suite/cstest/`. It consumes the `yaml` test files +in `/tests/` and reports the results. diff --git a/bindings/python/cstest_py/pyproject.toml b/bindings/python/cstest_py/pyproject.toml new file mode 100644 index 0000000000..34b27c5aaa --- /dev/null +++ b/bindings/python/cstest_py/pyproject.toml @@ -0,0 +1,18 @@ +# Copyright © 2024 Rot127 +# SPDX-License-Identifier: BSD-3 + +[project] +name = "cstest_py" +version = "0.1.0" +dependencies = [ + "pyyaml >= 6.0.2", + "capstone >= 5.0.0", +] +requires-python = ">= 3.8" + +[tool.setuptools] +packages = ["cstest_py"] +package-dir = {"" = "src"} + +[project.scripts] +cstest_py = "cstest_py.cstest:main" diff --git a/bindings/python/cstest_py/src/cstest_py/compare.py b/bindings/python/cstest_py/src/cstest_py/compare.py new file mode 100644 index 0000000000..7e679ec552 --- /dev/null +++ b/bindings/python/cstest_py/src/cstest_py/compare.py @@ -0,0 +1,337 @@ +# Copyright © 2024 Rot127 +# SPDX-License-Identifier: BSD-3 + +# Typing for Python3.8 +from __future__ import annotations + +import struct +import capstone +import re +from capstone import arm_const +from capstone import aarch64_const +from capstone import m68k_const +from capstone import mips_const +from capstone import ppc_const +from capstone import sparc_const +from capstone import sysz_const +from capstone import x86_const +from capstone import xcore_const +from capstone import tms320c64x_const +from capstone import m680x_const +from capstone import evm_const +from capstone import mos65xx_const +from capstone import wasm_const +from capstone import bpf_const +from capstone import riscv_const +from capstone import sh_const +from capstone import tricore_const +from capstone import alpha_const +from capstone import hppa_const +from capstone import loongarch_const + + +def cs_const_getattr(identifier: str): + attr = getattr(capstone, identifier, None) + if attr is not None: + return attr + attr = getattr(arm_const, identifier, None) + if attr is not None: + return attr + attr = getattr(aarch64_const, identifier, None) + if attr is not None: + return attr + attr = getattr(m68k_const, identifier, None) + if attr is not None: + return attr + attr = getattr(mips_const, identifier, None) + if attr is not None: + return attr + attr = getattr(ppc_const, identifier, None) + if attr is not None: + return attr + attr = getattr(sparc_const, identifier, None) + if attr is not None: + return attr + attr = getattr(sysz_const, identifier, None) + if attr is not None: + return attr + attr = getattr(x86_const, identifier, None) + if attr is not None: + return attr + attr = getattr(xcore_const, identifier, None) + if attr is not None: + return attr + attr = getattr(tms320c64x_const, identifier, None) + if attr is not None: + return attr + attr = getattr(m680x_const, identifier, None) + if attr is not None: + return attr + attr = getattr(evm_const, identifier, None) + if attr is not None: + return attr + attr = getattr(mos65xx_const, identifier, None) + if attr is not None: + return attr + attr = getattr(wasm_const, identifier, None) + if attr is not None: + return attr + attr = getattr(bpf_const, identifier, None) + if attr is not None: + return attr + attr = getattr(riscv_const, identifier, None) + if attr is not None: + return attr + attr = getattr(sh_const, identifier, None) + if attr is not None: + return attr + attr = getattr(tricore_const, identifier, None) + if attr is not None: + return attr + attr = getattr(alpha_const, identifier, None) + if attr is not None: + return attr + attr = getattr(hppa_const, identifier, None) + if attr is not None: + return attr + attr = getattr(loongarch_const, identifier, None) + if attr is not None: + return attr + raise ValueError(f"Python capstone doesn't have the constant: {identifier}") + + +def twos_complement(val, bits): + if (val & (1 << (bits - 1))) != 0: + val = val - (1 << bits) + return val & ((1 << bits) - 1) + + +def normalize_asm_text(text: str, arch_bits: int) -> str: + text = text.strip() + text = re.sub(r"\s+", " ", text) + # Replace hex numbers with decimals + for hex_num in re.findall(r"0x[0-9a-fA-F]+", text): + text = re.sub(hex_num, f"{int(hex_num, base=16)}", text, count=1) + # Replace negatives with twos-complement + for num in re.findall(r"-\d+", text): + n = twos_complement(int(num, base=10), arch_bits) + text = re.sub(num, f"{n}", text) + text = text.lower() + return text + + +def compare_asm_text( + a_insn: capstone.CsInsn, expected: None | str, arch_bits: int +) -> bool: + if expected is None: + return True + from cstest_py.cstest import log + + actual = f"{a_insn.mnemonic} {a_insn.op_str}" + actual = normalize_asm_text(actual, arch_bits) + expected = normalize_asm_text(expected, arch_bits) + + if actual != expected: + log.error( + "Normalized asm-text doesn't match:\n" + f"decoded: '{actual}'\n" + f"expected: '{expected}'\n" + ) + return False + return True + + +def compare_str(actual: str, expected: None | str, msg: str) -> bool: + if expected is None: + return True + from cstest_py.cstest import log + + if actual != expected: + log.error(f"{msg}: {actual} != {expected}") + return False + return True + + +def compare_tbool(actual: bool, expected: None | int, msg: str) -> bool: + if expected is None: + return True + from cstest_py.cstest import log + + if expected == 0: + # Unset + return True + + if (expected < 0 and actual) or (expected > 0 and not actual): + log.error(f"{msg}: {actual} != {expected}") + return False + return True + + +def compare_uint8(actual: int, expected: None | int, msg: str) -> bool: + if expected is None: + return True + from cstest_py.cstest import log + + actual = actual & 0xFF + expected = expected & 0xFF + if actual != expected: + log.error(f"{msg}: {actual} != {expected}") + return False + return True + + +def compare_int8(actual: int, expected: None | int, msg: str) -> bool: + if expected is None: + return True + from cstest_py.cstest import log + + actual = actual & 0xFF + expected = expected & 0xFF + if actual != expected: + log.error(f"{msg}: {actual} != {expected}") + return False + return True + + +def compare_uint16(actual: int, expected: None | int, msg: str) -> bool: + if expected is None: + return True + from cstest_py.cstest import log + + actual = actual & 0xFFFF + expected = expected & 0xFFFF + if actual != expected: + log.error(f"{msg}: {actual} != {expected}") + return False + return True + + +def compare_int16(actual: int, expected: None | int, msg: str) -> bool: + if expected is None: + return True + from cstest_py.cstest import log + + actual = actual & 0xFFFF + expected = expected & 0xFFFF + if actual != expected: + log.error(f"{msg}: {actual} != {expected}") + return False + return True + + +def compare_uint32(actual: int, expected: None | int, msg: str) -> bool: + if expected is None: + return True + from cstest_py.cstest import log + + actual = actual & 0xFFFFFFFF + expected = expected & 0xFFFFFFFF + if actual != expected: + log.error(f"{msg}: {actual} != {expected}") + return False + return True + + +def compare_int32(actual: int, expected: None | int, msg: str) -> bool: + if expected is None: + return True + from cstest_py.cstest import log + + actual = actual & 0xFFFFFFFF + expected = expected & 0xFFFFFFFF + if actual != expected: + log.error(f"{msg}: {actual} != {expected}") + return False + return True + + +def compare_uint64(actual: int, expected: None | int, msg: str) -> bool: + if expected is None: + return True + from cstest_py.cstest import log + + actual = actual & 0xFFFFFFFFFFFFFFFF + expected = expected & 0xFFFFFFFFFFFFFFFF + if actual != expected: + log.error(f"{msg}: {actual} != {expected}") + return False + return True + + +def compare_int64(actual: int, expected: None | int, msg: str) -> bool: + if expected is None: + return True + from cstest_py.cstest import log + + actual = actual & 0xFFFFFFFFFFFFFFFF + expected = expected & 0xFFFFFFFFFFFFFFFF + if actual != expected: + log.error(f"{msg}: {actual} != {expected}") + return False + return True + + +def compare_fp(actual: float, expected: None | float, msg: str) -> bool: + if expected is None: + return True + from cstest_py.cstest import log + + def floatToBits(f): + return struct.unpack("=L", struct.pack("=f", f))[0] + + if floatToBits(actual) != floatToBits(expected): + log.error(f"{msg}: {actual} != {expected}") + return False + return True + + +def compare_dp(actual: float, expected: None | float, msg: str) -> bool: + if expected is None: + return True + from cstest_py.cstest import log + + def doubleToBits(f): + return struct.unpack("=Q", struct.pack("=d", f))[0] + + if doubleToBits(actual) != doubleToBits(expected): + log.error(f"{msg}: {actual} != {expected}") + return False + return True + + +def compare_enum(actual, expected: None | str, msg: str) -> bool: + if expected is None: + return True + from cstest_py.cstest import log + + enum_val = cs_const_getattr(expected) + if actual != enum_val: + log.error(f"{msg}: {actual} != {expected} ({enum_val})") + return False + return True + + +def compare_bit_flags(actual: int, expected: None | list[str], msg: str) -> bool: + if expected is None: + return True + from cstest_py.cstest import log + + for flag in expected: + enum_val = cs_const_getattr(flag) + if not actual & enum_val: + log.error(f"{msg}: In {actual:x} the flag {expected} isn't set.") + return False + return True + + +def compare_reg( + insn: capstone.CsInsn, actual: int, expected: None | str, msg: str +) -> bool: + if expected is None: + return True + from cstest_py.cstest import log + + if insn.reg_name(actual) != expected: + log.error(f"{msg}: {actual} != {expected}") + return False + return True diff --git a/bindings/python/cstest_py/src/cstest_py/cs_modes.py b/bindings/python/cstest_py/src/cstest_py/cs_modes.py new file mode 100644 index 0000000000..0290bca796 --- /dev/null +++ b/bindings/python/cstest_py/src/cstest_py/cs_modes.py @@ -0,0 +1,41 @@ +# Copyright © 2024 Rot127 +# SPDX-License-Identifier: BSD-3 + +import capstone as cs + +configs = { + "CS_OPT_DETAIL": {"type": cs.CS_OPT_DETAIL, "val": cs.CS_OPT_ON}, + "CS_OPT_DETAIL_REAL": { + "type": cs.CS_OPT_DETAIL, + "val": cs.CS_OPT_DETAIL_REAL | cs.CS_OPT_ON, + }, + "CS_OPT_SKIPDATA": {"type": cs.CS_OPT_SKIPDATA, "val": cs.CS_OPT_ON}, + "CS_OPT_UNSIGNED": {"type": cs.CS_OPT_UNSIGNED, "val": cs.CS_OPT_ON}, + "CS_OPT_NO_BRANCH_OFFSET": { + "type": cs.CS_OPT_NO_BRANCH_OFFSET, + "val": cs.CS_OPT_ON, + }, + "CS_OPT_SYNTAX_DEFAULT": { + "type": cs.CS_OPT_SYNTAX, + "val": cs.CS_OPT_SYNTAX_DEFAULT, + }, + "CS_OPT_SYNTAX_INTEL": {"type": cs.CS_OPT_SYNTAX, "val": cs.CS_OPT_SYNTAX_INTEL}, + "CS_OPT_SYNTAX_ATT": {"type": cs.CS_OPT_SYNTAX, "val": cs.CS_OPT_SYNTAX_ATT}, + "CS_OPT_SYNTAX_NOREGNAME": { + "type": cs.CS_OPT_SYNTAX, + "val": cs.CS_OPT_SYNTAX_NOREGNAME, + }, + "CS_OPT_SYNTAX_MASM": {"type": cs.CS_OPT_SYNTAX, "val": cs.CS_OPT_SYNTAX_MASM}, + "CS_OPT_SYNTAX_MOTOROLA": { + "type": cs.CS_OPT_SYNTAX, + "val": cs.CS_OPT_SYNTAX_MOTOROLA, + }, + "CS_OPT_SYNTAX_CS_REG_ALIAS": { + "type": cs.CS_OPT_SYNTAX, + "val": cs.CS_OPT_SYNTAX_CS_REG_ALIAS, + }, + "CS_OPT_SYNTAX_PERCENT": { + "type": cs.CS_OPT_SYNTAX, + "val": cs.CS_OPT_SYNTAX_PERCENT, + }, +} diff --git a/bindings/python/cstest_py/src/cstest_py/cstest.py b/bindings/python/cstest_py/src/cstest_py/cstest.py new file mode 100755 index 0000000000..4fd244914b --- /dev/null +++ b/bindings/python/cstest_py/src/cstest_py/cstest.py @@ -0,0 +1,493 @@ +#!/usr/bin/env python3 +# Copyright © 2024 Rot127 +# SPDX-License-Identifier: BSD-3 + +# Typing for Python3.8 +from __future__ import annotations + +import argparse +import logging +import subprocess as sp +import sys +import os +import yaml +import capstone +import traceback + +from capstone import CsInsn, Cs, CS_ARCH_AARCH64, CS_MODE_64, CS_MODE_16 + +from cstest_py.cs_modes import configs +from cstest_py.details import compare_details +from cstest_py.compare import ( + compare_asm_text, + compare_str, + compare_tbool, + compare_uint32, +) +from enum import Enum +from pathlib import Path + +log = logging.getLogger("__name__") + + +def get_cs_int_attr(cs, attr: str, err_msg_pre: str): + try: + attr_int = getattr(cs, attr) + if not isinstance(attr_int, int): + raise AttributeError(f"{attr} not found") + return attr_int + except AttributeError: + log.warning(f"{err_msg_pre}: Capstone doesn't have the attribute '{attr}'") + return None + + +def arch_bits(arch: int, mode: int) -> int: + if arch == CS_ARCH_AARCH64 or mode & CS_MODE_64: + return 64 + elif mode & CS_MODE_16: + return 16 + return 32 + + +class TestResult(Enum): + SUCCESS = 0 + FAILED = 1 + SKIPPED = 2 + ERROR = 3 + + +class TestStats: + def __init__(self, total_file_count: int): + self.total_file_count = total_file_count + self.valid_test_files = 0 + self.test_case_count = 0 + self.success = 0 + self.failed = 0 + self.skipped = 0 + self.errors = 0 + self.invalid_files = 0 + self.total_valid_files = 0 + self.err_msgs: list[str] = list() + self.failing_files = set() + + def add_failing_file(self, test_file: Path): + self.failing_files.add(test_file) + + def add_error_msg(self, msg: str): + self.err_msgs.append(msg) + + def add_invalid_file_dp(self, tfile: Path): + self.invalid_files += 1 + self.errors += 1 + self.add_failing_file(tfile) + + def add_test_case_data_point(self, dp: TestResult): + if dp == TestResult.SUCCESS: + self.success += 1 + elif dp == TestResult.FAILED: + self.failed += 1 + elif dp == TestResult.SKIPPED: + self.skipped += 1 + elif dp == TestResult.ERROR: + self.errors += 1 + self.failed += 1 + else: + raise ValueError(f"Unhandled TestResult: {dp}") + + def set_total_valid_files(self, total_valid_files: int): + self.total_valid_files = total_valid_files + + def set_total_test_cases(self, total_test_cases: int): + self.test_case_count = total_test_cases + + def get_test_case_count(self) -> int: + return self.test_case_count + + def print_evaluate(self): + if self.total_file_count == 0: + log.error("No test files found!") + exit(-1) + if self.test_case_count == 0: + log.error("No test cases found!") + exit(-1) + if self.failing_files: + print("Test files with failures:") + for tf in self.failing_files: + print(f" - {tf}") + print() + if self.err_msgs: + print("Error messages:") + for error in self.err_msgs: + print(f" - {error}") + + print("\n-----------------------------------------") + print("Test run statistics\n") + print(f"Valid files: {self.total_valid_files}") + print(f"Invalid files: {self.invalid_files}") + print(f"Errors: {self.errors}\n") + print("Test cases:") + print(f"\tTotal: {self.test_case_count}") + print(f"\tSuccessful: {self.success}") + print(f"\tSkipped: {self.skipped}") + print(f"\tFailed: {self.failed}") + print("-----------------------------------------") + print("") + + if self.test_case_count != self.success + self.failed + self.skipped: + log.error( + "Inconsistent statistics: total != successful + failed + skipped\n" + ) + + if self.errors != 0: + log.error("Failed with errors\n") + exit(-1) + elif self.failed != 0: + log.warning("Not all tests succeeded\n") + exit(-1) + log.info("All tests succeeded.\n") + exit(0) + + +class TestInput: + def __init__(self, input_dict: dict): + self.input_dict = input_dict + if "bytes" not in self.input_dict: + raise ValueError("Error: 'Missing required mapping field'\nField: 'bytes'.") + if "options" not in self.input_dict: + raise ValueError( + "Error: 'Missing required mapping field'\nField: 'options'." + ) + if "arch" not in self.input_dict: + raise ValueError("Error: 'Missing required mapping field'\nField: 'arch'.") + self.in_bytes = bytes(self.input_dict["bytes"]) + self.options = self.input_dict["options"] + self.arch = self.input_dict["arch"] + + self.name = "" if "name" not in self.input_dict else self.input_dict["name"] + if "address" not in self.input_dict: + self.address: int = 0 + else: + assert isinstance(self.input_dict["address"], int) + self.address = self.input_dict["address"] + self.handle = None + self.arch_bits = 0 + + def setup(self): + log.debug(f"Init {self}") + arch = get_cs_int_attr(capstone, self.arch, "CS_ARCH") + if arch is None: + cs_name = f"CS_ARCH_{self.arch.upper()}" + arch = get_cs_int_attr(capstone, cs_name, "CS_ARCH") + if arch is None: + raise ValueError( + f"Couldn't init architecture as '{self.arch}' or '{cs_name}'.\n" + f"'{self.arch}' is not mapped to a capstone architecture." + ) + new_mode = 0 + for opt in self.options: + if "CS_MODE_" in opt: + mode = get_cs_int_attr(capstone, opt, "CS_OPT") + if mode is not None: + new_mode |= mode + continue + self.handle = Cs(arch, new_mode) + + for opt in self.options: + if "CS_MODE_" in opt: + continue + if "CS_OPT_" in opt and opt in configs: + mtype = configs[opt]["type"] + val = configs[opt]["val"] + self.handle.option(mtype, val) + continue + log.warning(f"Option: '{opt}' not used") + + self.arch_bits = arch_bits(self.handle.arch, self.handle.mode) + log.debug("Init done") + + def decode(self) -> list[CsInsn]: + if not self.handle: + raise ValueError("self.handle is None. Must be setup before.") + return [i for i in self.handle.disasm(self.in_bytes, self.address)] + + def __str__(self): + default = ( + f"TestInput {{ arch: {self.arch}, options: {self.options}, " + f"addr: {self.address:x}, bytes: [ {','.join([f'{b:#04x}' for b in self.in_bytes])} ] }}" + ) + if self.name: + return f"{self.name} -- {default}" + return default + + +class TestExpected: + def __init__(self, expected_dict: dict): + self.expected_dict = expected_dict + self.insns = ( + list() if "insns" not in self.expected_dict else self.expected_dict["insns"] + ) + + def compare(self, actual_insns: list[CsInsn], bits: int) -> TestResult: + if len(actual_insns) != len(self.insns): + log.error( + "Number of decoded instructions don't match (actual != expected): " + f"{len(actual_insns)} != {len(self.insns):#x}" + ) + return TestResult.FAILED + for a_insn, e_insn in zip(actual_insns, self.insns): + if not compare_asm_text( + a_insn, + e_insn.get("asm_text"), + bits, + ): + return TestResult.FAILED + + if not compare_str(a_insn.mnemonic, e_insn.get("mnemonic"), "mnemonic"): + return TestResult.FAILED + + if not compare_str(a_insn.op_str, e_insn.get("op_str"), "op_str"): + return TestResult.FAILED + + if not compare_uint32(a_insn.id, e_insn.get("id"), "id"): + return TestResult.FAILED + + if not compare_tbool(a_insn.is_alias, e_insn.get("is_alias"), "is_alias"): + return TestResult.FAILED + + if not compare_uint32(a_insn.alias_id, e_insn.get("alias_id"), "alias_id"): + return TestResult.FAILED + + if not compare_details(a_insn, e_insn.get("details")): + return TestResult.FAILED + return TestResult.SUCCESS + + +class TestCase: + def __init__(self, test_case_dict: dict): + self.tc_dict = test_case_dict + if "input" not in self.tc_dict: + raise ValueError("Mandatory field 'input' missing") + if "expected" not in self.tc_dict: + raise ValueError("Mandatory field 'expected' missing") + self.input = TestInput(self.tc_dict["input"]) + self.expected = TestExpected(self.tc_dict["expected"]) + self.skip = "skip" in self.tc_dict + if self.skip and "skip_reason" not in self.tc_dict: + raise ValueError( + "If 'skip' field is set a 'skip_reason' field must be set as well." + ) + self.skip_reason = ( + self.tc_dict["skip_reason"] if "skip_reason" in self.tc_dict else "" + ) + + def __str__(self) -> str: + return f"{self.input}" + + def test(self) -> TestResult: + if self.skip: + log.info(f"Skip {self}\nReason: {self.skip_reason}") + return TestResult.SKIPPED + + try: + self.input.setup() + except Exception as e: + log.error(f"Setup failed at with: {e}") + traceback.print_exc() + return TestResult.ERROR + + try: + insns = self.input.decode() + except Exception as e: + log.error(f"Decode failed with: {e}") + traceback.print_exc() + return TestResult.ERROR + + try: + return self.expected.compare(insns, self.input.arch_bits) + except Exception as e: + log.error(f"Compare expected failed with: {e}") + traceback.print_exc() + return TestResult.ERROR + + +class TestFile: + def __init__(self, tfile_path: Path): + self.path = tfile_path + with open(tfile_path) as f: + try: + self.content = yaml.safe_load(f) + except yaml.YAMLError as e: + raise e + self.test_cases = list() + if not self.content: + raise ValueError("Empty file") + for tc_dict in self.content["test_cases"]: + tc = TestCase(tc_dict) + self.test_cases.append(tc) + + def num_test_cases(self) -> int: + return len(self.test_cases) + + def __str__(self) -> str: + return f"{self.path}" + + +class CSTest: + def __init__(self, path: Path, exclude: list[Path], include: list[Path]): + self.yaml_paths: list[Path] = list() + + log.info(f"Search test files in {path}") + if path.is_file(): + self.yaml_paths.append(path) + else: + for root, dirs, files in os.walk(path, onerror=print): + for file in files: + f = Path(root).joinpath(file) + if f.suffix not in [".yaml", ".yml"]: + continue + if f.name in exclude: + continue + if not include or f.name in include: + log.debug(f"Add: {f}") + self.yaml_paths.append(f) + + log.info(f"Test files found: {len(self.yaml_paths)}") + self.stats = TestStats(len(self.yaml_paths)) + self.test_files: list[TestFile] = list() + + def parse_files(self): + total_test_cases = 0 + total_files = len(self.yaml_paths) + count = 1 + for tfile in self.yaml_paths: + print( + f"Parse {count}/{total_files}: {tfile.name}", + end=f"{' ' * 20}\r", + flush=True, + ) + try: + tf = TestFile(tfile) + total_test_cases += tf.num_test_cases() + self.test_files.append(tf) + except yaml.YAMLError as e: + self.stats.add_error_msg(str(e)) + self.stats.add_invalid_file_dp(tfile) + log.error("Error: 'libyaml parser error'") + log.error(f"{e}") + log.error(f"Failed to parse test file '{tfile}'") + except ValueError as e: + self.stats.add_error_msg(str(e)) + self.stats.add_invalid_file_dp(tfile) + log.error(f"Error: ValueError: {e}") + log.error(f"Failed to parse test file '{tfile}'") + finally: + count += 1 + self.stats.set_total_valid_files(len(self.test_files)) + self.stats.set_total_test_cases(total_test_cases) + log.info(f"Found {self.stats.get_test_case_count()} test cases.{' ' * 20}") + + def run_tests(self): + self.parse_files() + for tf in self.test_files: + log.info(f"Test file: {tf}\n") + for tc in tf.test_cases: + log.info(f"Run test: {tc}") + try: + result = tc.test() + except Exception as e: + result = TestResult.ERROR + self.stats.add_error_msg(str(e)) + if result == TestResult.FAILED or result == TestResult.ERROR: + self.stats.add_failing_file(tf.path) + self.stats.add_test_case_data_point(result) + log.info(result) + print() + self.stats.print_evaluate() + + +def get_repo_root() -> str | None: + res = sp.run(["git", "rev-parse", "--show-toplevel"], capture_output=True) + if res.stderr: + log.error("Could not get repository root directory.") + return None + return res.stdout.decode("utf8").strip() + + +def parse_args() -> argparse.Namespace: + parser = argparse.ArgumentParser( + prog="Python CSTest", + description="Pyton binding cstest implementation.", + ) + repo_root = get_repo_root() + if repo_root: + parser.add_argument( + dest="search_dir", + help="Directory to search for .yaml test files.", + default=Path(f"{repo_root}/tests/"), + type=Path, + ) + else: + parser.add_argument( + dest="search_dir", + help="Directory to search for .yaml test files.", + required=True, + type=Path, + ) + parser.add_argument( + "-e", + dest="exclude", + help="List of file names to exclude.", + nargs="+", + required=False, + default=list(), + ) + parser.add_argument( + "-i", + dest="include", + help="List of file names to include.", + nargs="+", + required=False, + default=list(), + ) + parser.add_argument( + "-v", + dest="verbosity", + help="Verbosity of the log messages.", + choices=["debug", "info", "warning", "error", "fatal", "critical"], + default="info", + ) + arguments = parser.parse_args() + return arguments + + +def main(): + log_levels = { + "debug": logging.DEBUG, + "info": logging.INFO, + "warning": logging.WARNING, + "error": logging.ERROR, + "fatal": logging.FATAL, + "critical": logging.CRITICAL, + } + args = parse_args() + format = logging.Formatter("%(levelname)-5s - %(message)s", None, "%") + log.setLevel(log_levels[args.verbosity]) + + h1 = logging.StreamHandler(sys.stdout) + h1.addFilter( + lambda record: record.levelno >= log_levels[args.verbosity] + and record.levelno < logging.WARNING + ) + h1.setFormatter(format) + + h2 = logging.StreamHandler(sys.stderr) + h2.setLevel(logging.WARNING) + h2.setFormatter(format) + + log.addHandler(h1) + log.addHandler(h2) + CSTest(args.search_dir, args.exclude, args.include).run_tests() + + +if __name__ == "__main__": + main() diff --git a/bindings/python/cstest_py/src/cstest_py/details.py b/bindings/python/cstest_py/src/cstest_py/details.py new file mode 100644 index 0000000000..e5236495b0 --- /dev/null +++ b/bindings/python/cstest_py/src/cstest_py/details.py @@ -0,0 +1,1511 @@ +# Copyright © 2024 Rot127 +# SPDX-License-Identifier: BSD-3 + +# Typing for Python3.8 +from __future__ import annotations + +from capstone import ( + Cs, + CsInsn, +) +from capstone.alpha_const import ALPHA_OP_IMM, ALPHA_OP_REG +from capstone.bpf_const import ( + BPF_OP_REG, + BPF_OP_IMM, + BPF_OP_OFF, + BPF_OP_MMEM, + BPF_OP_MSH, + BPF_OP_EXT, + BPF_OP_MEM, +) +from capstone.hppa_const import ( + HPPA_OP_REG, + HPPA_OP_IMM, + HPPA_OP_MEM, + HPPA_OP_IDX_REG, + HPPA_OP_DISP, + HPPA_OP_TARGET, +) +from capstone.loongarch_const import ( + LOONGARCH_OP_REG, + LOONGARCH_OP_IMM, + LOONGARCH_OP_MEM, +) + +from capstone.m680x_const import ( + M680X_OP_REGISTER, + M680X_OP_IMMEDIATE, + M680X_OP_INDEXED, + M680X_OP_EXTENDED, + M680X_OP_DIRECT, + M680X_OP_RELATIVE, + M680X_OP_CONSTANT, +) + +from capstone.aarch64_const import ( + AARCH64_OP_SME, + AARCH64_OP_PRED, + AARCH64_OP_SYSALIAS, + AARCH64_OP_SYSIMM, + AARCH64_OP_SYSREG, + AARCH64_OP_FP, + AARCH64_OP_IMM_RANGE, + AARCH64_OP_MEM, + AARCH64_OP_IMM, + AARCH64_OP_REG, +) +from capstone.m68k_const import ( + M68K_OP_REG, + M68K_OP_REG_PAIR, + M68K_OP_IMM, + M68K_OP_BR_DISP, + M68K_OP_REG_BITS, + M68K_OP_FP_DOUBLE, + M68K_OP_FP_SINGLE, + M68K_OP_MEM, +) +from capstone.mips_const import MIPS_OP_REG, MIPS_OP_IMM, MIPS_OP_MEM +from capstone.mos65xx_const import MOS65XX_OP_REG, MOS65XX_OP_MEM, MOS65XX_OP_IMM +from capstone.riscv_const import RISCV_OP_MEM, RISCV_OP_IMM, RISCV_OP_REG +from capstone.sh_const import SH_OP_REG, SH_OP_MEM, SH_OP_IMM +from capstone.sparc_const import SPARC_OP_REG, SPARC_OP_IMM, SPARC_OP_MEM +from capstone.sysz_const import SYSZ_OP_REG, SYSZ_OP_IMM, SYSZ_OP_MEM +from capstone.tms320c64x_const import ( + TMS320C64X_OP_REG, + TMS320C64X_OP_REGPAIR, + TMS320C64X_MEM_DISP_CONSTANT, + TMS320C64X_MEM_DISP_REGISTER, + TMS320C64X_OP_MEM, + TMS320C64X_OP_IMM, +) +from capstone.tricore_const import TRICORE_OP_REG, TRICORE_OP_IMM, TRICORE_OP_MEM +from capstone.wasm_const import ( + WASM_OP_INT7, + WASM_OP_VARUINT32, + WASM_OP_VARUINT64, + WASM_OP_UINT32, + WASM_OP_UINT64, + WASM_OP_IMM, + WASM_OP_BRTABLE, +) + +from capstone.x86_const import ( + X86_OP_MEM, + X86_OP_IMM, + X86_OP_REG, +) + +from capstone.ppc_const import ( + PPC_OP_MEM, + PPC_OP_IMM, + PPC_OP_REG, +) + +from capstone.arm_const import ( + ARM_OP_PRED, + ARM_OP_CIMM, + ARM_OP_PIMM, + ARM_OP_SETEND, + ARM_OP_SYSREG, + ARM_OP_BANKEDREG, + ARM_OP_SPSR, + ARM_OP_CPSR, + ARM_OP_SYSM, + ARM_OP_FP, + ARM_OP_MEM, + ARM_OP_IMM, + ARM_OP_REG, +) +from capstone.xcore_const import XCORE_OP_REG, XCORE_OP_IMM, XCORE_OP_MEM + +from cstest_py.compare import ( + compare_tbool, + compare_uint8, + compare_int8, + compare_uint16, + compare_int16, + compare_uint32, + compare_int32, + compare_uint64, + compare_int64, + compare_fp, + compare_dp, + compare_enum, + compare_bit_flags, + compare_reg, +) + + +def test_reg_rw_access(insn: CsInsn, expected: dict): + if ("regs_read" not in expected or len(expected["regs_read"]) <= 0) and ( + "regs_write" not in expected or len(expected["regs_write"]) <= 0 + ): + return True + + regs_read, regs_write = insn.regs_access() + if "regs_read" in expected and len(expected["regs_read"]) > 0: + if not compare_uint32( + len(regs_read), len(expected["regs_read"]), "regs_read_count" + ): + return False + for i, rreg in enumerate(regs_read): + if not compare_reg(insn, rreg, expected["regs_read"][i], "regs_read"): + return False + + if "regs_write" in expected and len(expected["regs_write"]) > 0: + if not compare_uint32( + len(regs_write), len(expected["regs_write"]), "regs_write_count" + ): + return False + for i, wreg in enumerate(regs_write): + if not compare_reg(insn, wreg, expected["regs_write"][i], "regs_write"): + return False + + return True + + +def test_impl_reg_rw_access(insn: CsInsn, expected: dict): + if ("regs_impl_read" not in expected or len(expected["regs_impl_read"]) <= 0) and ( + "regs_impl_write" not in expected or len(expected["regs_impl_write"]) <= 0 + ): + return True + + regs_impl_read = insn.regs_read + regs_impl_write = insn.regs_write + + if "regs_impl_read" in expected and len(expected["regs_impl_read"]) > 0: + if not compare_uint32( + len(regs_impl_read), len(expected["regs_impl_read"]), "regs_impl_read_count" + ): + return False + for i, rreg in enumerate(regs_impl_read): + if not compare_reg( + insn, rreg, expected["regs_impl_read"][i], "regs_impl_read" + ): + return False + + if "regs_impl_write" in expected and len(expected["regs_impl_write"]) > 0: + if not compare_uint32( + len(regs_impl_write), + len(expected["regs_impl_write"]), + "regs_impl_write_count", + ): + return False + for i, wreg in enumerate(regs_impl_write): + if not compare_reg( + insn, wreg, expected["regs_impl_write"][i], "regs_impl_write" + ): + return False + + return True + + +def compare_details(insn: CsInsn, expected: dict) -> bool: + if expected is None: + return True + + if not test_reg_rw_access(insn, expected): + return False + + if not test_impl_reg_rw_access(insn, expected): + return False + + # The current Python bindings don't have such a thing as + # an detail attribute for each architecture. + # The attributes of each are directly + # an attribute of the instruction. + actual = insn + if "groups" in expected and len(expected["groups"]) > 0: + if not compare_uint32(len(actual.groups), len(expected["groups"]), "group"): + return False + + for agroup, egroup in zip(actual.groups, expected["groups"]): + if insn.group_name(agroup) == egroup: + continue + if not compare_enum(agroup, egroup, "group"): + return False + + if not compare_tbool(insn.writeback, expected.get("writeback"), "writeback"): + return False + + if "aarch64" in expected: + return test_expected_aarch64(actual, expected["aarch64"]) + elif "arm" in expected: + return test_expected_arm(actual, expected["arm"]) + elif "ppc" in expected: + return test_expected_ppc(actual, expected["ppc"]) + elif "tricore" in expected: + return test_expected_tricore(actual, expected["tricore"]) + elif "alpha" in expected: + return test_expected_alpha(actual, expected["alpha"]) + elif "bpf" in expected: + return test_expected_bpf(actual, expected["bpf"]) + elif "hppa" in expected: + return test_expected_hppa(actual, expected["hppa"]) + elif "xcore" in expected: + return test_expected_xcore(actual, expected["xcore"]) + elif "systemz" in expected: + return test_expected_sysz(actual, expected["systemz"]) + elif "sparc" in expected: + return test_expected_sparc(actual, expected["sparc"]) + elif "sh" in expected: + return test_expected_sh(actual, expected["sh"]) + elif "mips" in expected: + return test_expected_mips(actual, expected["mips"]) + elif "riscv" in expected: + return test_expected_riscv(actual, expected["riscv"]) + elif "m680x" in expected: + return test_expected_m680x(actual, expected["m680x"]) + elif "tms320c64x" in expected: + return test_expected_tms320c64x(actual, expected["tms320c64x"]) + elif "mos65xx" in expected: + return test_expected_mos65xx(actual, expected["mos65xx"]) + elif "evm" in expected: + return test_expected_evm(actual, expected["evm"]) + elif "loongarch" in expected: + return test_expected_loongarch(actual, expected["loongarch"]) + elif "wasm" in expected: + return test_expected_wasm(actual, expected["wasm"]) + elif "x86" in expected: + return test_expected_x86(actual, expected["x86"]) + elif "m68k" in expected: + return test_expected_m68k(actual, expected["m68k"]) + + return True + + +def test_expected_x86(actual: CsInsn, expected: dict) -> bool: + if not compare_reg( + actual, actual.sib_index, expected.get("sib_index"), "sib_index" + ): + return False + if not compare_reg(actual, actual.sib_base, expected.get("sib_base"), "sib_base"): + return False + if not compare_enum(actual.xop_cc, expected.get("xop_cc"), "xop_cc"): + return False + if not compare_enum(actual.sse_cc, expected.get("sse_cc"), "sse_cc"): + return False + if not compare_enum(actual.avx_cc, expected.get("avx_cc"), "avx_cc"): + return False + if not compare_enum(actual.avx_rm, expected.get("avx_rm"), "avx_rm"): + return False + + if "prefix" in expected: + for i, prefix in enumerate(expected.get("prefix")): + if not compare_enum(actual.prefix[i], expected.get("prefix")[i], "prefix"): + return False + + if "opcode" in expected: + for i, opcode in enumerate(expected.get("opcode")): + if not compare_uint8(actual.opcode[i], expected.get("opcode")[i], "opcode"): + return False + + if not compare_uint8(actual.rex, expected.get("rex"), "rex"): + return False + if not compare_uint8(actual.addr_size, expected.get("addr_size"), "addr_size"): + return False + if not compare_uint8(actual.modrm, expected.get("modrm"), "modrm"): + return False + if not compare_uint8(actual.sib, expected.get("sib"), "sib"): + return False + if not compare_int64(actual.disp, expected.get("disp"), "disp"): + return False + if not compare_int8(actual.sib_scale, expected.get("sib_scale"), "sib_scale"): + return False + if not compare_tbool(actual.avx_sae, expected.get("avx_sae"), "avx_sae"): + return False + + if not compare_bit_flags(actual.eflags, expected.get("eflags"), "eflags"): + return False + if not compare_bit_flags(actual.fpu_flags, expected.get("fpu_flags"), "fpu_flags"): + return False + + if not compare_uint8( + actual.encoding.modrm_offset, + expected.get("enc_modrm_offset"), + "enc_modrm_offset", + ): + return False + if not compare_uint8( + actual.encoding.disp_offset, expected.get("enc_disp_offset"), "enc_disp_offset" + ): + return False + if not compare_uint8( + actual.encoding.disp_size, expected.get("enc_disp_size"), "enc_disp_size" + ): + return False + if not compare_uint8( + actual.encoding.imm_offset, expected.get("enc_imm_offset"), "enc_imm_offset" + ): + return False + if not compare_uint8( + actual.encoding.imm_size, expected.get("enc_imm_size"), "enc_imm_size" + ): + return False + + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected["operands"]), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.type, eop.get("type"), "type"): + return False + if not compare_enum(aop.access, eop.get("access"), "access"): + return False + if not compare_uint8(aop.size, eop.get("size"), "size"): + return False + if not compare_enum(aop.avx_bcast, eop.get("avx_bcast"), "avx_bcast"): + return False + if not compare_tbool( + aop.avx_zero_opmask, eop.get("avx_zero_opmask"), "avx_zero_opmask" + ): + return False + + if aop.type == X86_OP_REG: + if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): + return False + elif aop.type == X86_OP_IMM: + if not compare_int64(aop.imm, eop.get("imm"), "imm"): + return False + elif aop.type == X86_OP_MEM: + if not compare_reg( + actual, aop.mem.segment, eop.get("mem_segment"), "mem_segment" + ): + return False + if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"): + return False + if not compare_reg( + actual, aop.mem.index, eop.get("mem_index"), "mem_index" + ): + return False + if not compare_int32(aop.mem.scale, eop.get("mem_scale"), "mem_scale"): + return False + if not compare_int64(aop.mem.disp, eop.get("mem_disp"), "mem_disp"): + return False + else: + raise ValueError("x86 operand type not handled") + + return True + + +def test_expected_ppc(actual: CsInsn, expected: dict) -> bool: + if "bc" in expected and not compare_uint8(actual.bc.bo, expected["bc"].get("bo"), "bo"): + return False + + if "bc" in expected and not compare_uint8(actual.bc.bi, expected["bc"].get("bi"), "bi"): + return False + + if "bc" in expected and not compare_enum( + actual.bc.crX_bit, expected.get("bc").get("crX_bit"), "crX_bit" + ): + return False + if "bc" in expected and not compare_reg( + actual, actual.bc.crX, expected.get("bc").get("crX"), "crX" + ): + return False + if "bc" in expected and not compare_enum( + actual.bc.hint, expected.get("bc").get("hint"), "hint" + ): + return False + if "bc" in expected and not compare_enum( + actual.bc.pred_cr, expected.get("bc").get("pred_cr"), "pred_cr" + ): + return False + if "bc" in expected and not compare_enum( + actual.bc.pred_ctr, expected.get("bc").get("pred_ctr"), "pred_ctr" + ): + return False + if "bc" in expected and not compare_enum( + actual.bc.bh, expected.get("bc").get("bh"), "bh" + ): + return False + + if not compare_tbool(actual.update_cr0, expected.get("update_cr0"), "update_cr0"): + return False + if not compare_enum(actual.format, expected.get("format"), "format"): + return False + + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected["operands"]), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.type, eop.get("type"), "type"): + return False + if not compare_enum(aop.access, eop.get("access"), "access"): + return False + + if aop.type == PPC_OP_REG: + if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): + return False + elif aop.type == PPC_OP_IMM: + if not compare_int64(aop.imm, eop.get("imm"), "imm"): + return False + elif aop.type == PPC_OP_MEM: + if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"): + return False + if not compare_reg( + actual, aop.mem.offset, eop.get("mem_offset"), "mem_offset" + ): + return False + if not compare_int32(aop.mem.disp, eop.get("mem_disp"), "mem_disp"): + return False + return True + + +def test_expected_arm(actual: CsInsn, expected: dict) -> bool: + if not compare_int32( + actual.vector_size, expected.get("vector_size"), "vector_size" + ): + return False + if not compare_enum(actual.vector_data, expected.get("vector_data"), "vector_data"): + return False + if not compare_enum(actual.cps_mode, expected.get("cps_mode"), "cps_mode"): + return False + if not compare_enum(actual.cps_flag, expected.get("cps_flag"), "cps_flag"): + return False + if not compare_enum(actual.cc, expected.get("cc"), "cc"): + return False + if not compare_enum(actual.vcc, expected.get("vcc"), "vcc"): + return False + if not compare_enum(actual.mem_barrier, expected.get("mem_barrier"), "mem_barrier"): + return False + if not compare_uint8(actual.pred_mask, expected.get("pred_mask"), "pred_mask"): + return False + + if not compare_tbool(actual.usermode, expected.get("usermode"), "usermode"): + return False + if not compare_tbool( + actual.update_flags, expected.get("update_flags"), "update_flags" + ): + return False + if not compare_tbool( + actual.post_index, expected.get("post_indexed"), "post_indexed" + ): + return False + + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected.get("operands")), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.type, eop.get("type"), "type"): + return False + if not compare_enum(aop.access, eop.get("access"), "access"): + return False + + if aop.type == ARM_OP_REG: + if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): + return False + elif ( + aop.type == ARM_OP_IMM or aop.type == ARM_OP_PIMM or aop.type == ARM_OP_CIMM + ): + if not compare_int64(aop.imm, eop.get("imm"), "imm"): + return False + elif aop.type == ARM_OP_SETEND: + if not compare_enum(aop.setend, eop.get("setend"), "setend"): + return False + elif aop.type == ARM_OP_PRED: + if not compare_int32(aop.pred, eop.get("pred"), "pred"): + return False + elif aop.type == ARM_OP_FP: + if not compare_fp(aop.fp, eop.get("fp"), "fp"): + return False + elif aop.type == ARM_OP_MEM: + if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"): + return False + if not compare_reg( + actual, aop.mem.index, eop.get("mem_index"), "mem_index" + ): + return False + if not compare_int32(aop.mem.scale, eop.get("mem_scale"), "mem_scale"): + return False + if not compare_int32(aop.mem.disp, eop.get("mem_disp"), "mem_disp"): + return False + if not compare_uint32(aop.mem.align, eop.get("mem_align"), "mem_align"): + return False + elif aop.type == ARM_OP_SYSREG: + if not compare_enum( + aop.sysop.reg.mclasssysreg, eop.get("sys_reg"), "sys_reg" + ): + return False + if not compare_int32(aop.sysop.sysm, eop.get("sys_sysm"), "sys_sysm"): + return False + if not compare_int32( + aop.sysop.msr_mask, eop.get("sys_msr_mask"), "sys_msr_mask" + ): + return False + elif aop.type == ARM_OP_BANKEDREG: + if not compare_enum(aop.sysop.reg.bankedreg, eop.get("sys_reg"), "sys_reg"): + return False + if not compare_int32(aop.sysop.sysm, eop.get("sys_sysm"), "sys_sysm"): + return False + if not compare_int32( + aop.sysop.msr_mask, eop.get("sys_msr_mask"), "sys_msr_mask" + ): + return False + elif aop.type == ARM_OP_SPSR or aop.type == ARM_OP_CPSR: + if not compare_bit_flags( + aop.sysop.psr_bits, eop.get("sys_psr_bits"), "sys_psr_bits" + ): + return False + if not compare_int32(aop.sysop.sysm, eop.get("sys_sysm"), "sys_sysm"): + return False + if not compare_int32( + aop.sysop.msr_mask, eop.get("sys_msr_mask"), "sys_msr_mask" + ): + return False + elif aop.type == ARM_OP_SYSM: + if not compare_int32(aop.sysop.sysm, eop.get("sys_sysm"), "sys_sysm"): + return False + if not compare_int32( + aop.sysop.msr_mask, eop.get("sys_msr_mask"), "sys_msr_mask" + ): + return False + else: + raise ValueError("ARM operand type not handled") + + if not compare_enum(aop.shift.type, eop.get("shift_type"), "shift_type"): + return False + if not compare_uint32(aop.shift.value, eop.get("shift_value"), "shift_value"): + return False + + if not compare_int8(aop.neon_lane, eop.get("neon_lane"), "neon_lane"): + return False + + if not compare_int32( + aop.vector_index, eop.get("vector_index"), "vector_index" + ): + return False + + if not compare_tbool(aop.subtracted, eop.get("subtracted"), "subtracted"): + return False + return True + + +def test_expected_m680x(actual: CsInsn, expected: dict) -> bool: + if not compare_bit_flags(actual.flags, expected.get("flags"), "flags"): + return False + + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected.get("operands")), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.type, eop.get("type"), "type"): + return False + if not compare_enum(aop.access, eop.get("access"), "access"): + return False + if not compare_uint8(aop.size, eop.get("size"), "size"): + return False + + if aop.type == M680X_OP_INDEXED: + if "idx" not in eop: + continue + if not compare_reg( + actual, aop.idx.base_reg, eop["idx"].get("base_reg"), "base_reg" + ): + return False + if not compare_reg( + actual, aop.idx.offset_reg, eop["idx"].get("offset_reg"), "offset_reg" + ): + return False + if not compare_int16(aop.idx.offset, eop["idx"].get("offset"), "offset"): + return False + if not compare_uint16( + aop.idx.offset_addr, eop["idx"].get("offset_addr"), "offset_addr" + ): + return False + if not compare_uint8( + aop.idx.offset_bits, eop["idx"].get("offset_bits"), "offset_bits" + ): + return False + if not compare_int8(aop.idx.inc_dec, eop["idx"].get("inc_dec"), "inc_dec"): + return False + if not compare_bit_flags(aop.idx.flags, eop["idx"].get("flags"), "flags"): + return False + + elif aop.type == M680X_OP_REGISTER: + if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): + return False + elif aop.type == M680X_OP_IMMEDIATE: + if not compare_int32(aop.imm, eop.get("imm"), "imm"): + return False + elif aop.type == M680X_OP_RELATIVE: + if not compare_uint16( + aop.rel.address, eop.get("rel_address"), "rel_address" + ): + return False + if not compare_int16(aop.rel.offset, eop.get("rel_offset"), "rel_offset"): + return False + elif aop.type == M680X_OP_EXTENDED: + if not compare_uint16( + aop.ext.address, eop.get("ext_address"), "ext_address" + ): + return False + if not compare_tbool( + aop.ext.indirect, eop.get("ext_indirect"), "ext_indirect" + ): + return False + elif aop.type == M680X_OP_DIRECT: + if not compare_uint8( + aop.direct_addr, eop.get("direct_addr"), "direct_addr" + ): + return False + elif aop.type == M680X_OP_CONSTANT: + if not compare_uint8(aop.const_val, eop.get("const_val"), "const_val"): + return False + + return True + + +def test_expected_aarch64(actual: CsInsn, expected: dict) -> bool: + if not compare_enum(actual.cc, expected.get("cc"), "cc"): + return False + if not compare_tbool( + actual.update_flags, expected.get("update_flags"), "update_flags" + ): + return False + if not compare_tbool( + actual.post_index, expected.get("post_indexed"), "post_indexed" + ): + return False + + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected.get("operands")), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.access, eop.get("access"), "access"): + return False + + if not compare_enum(aop.shift.type, eop.get("shift_type"), "shift_type"): + return False + if not compare_uint32(aop.shift.value, eop.get("shift_value"), "shift_value"): + return False + if not compare_enum(aop.ext, eop.get("ext"), "ext"): + return False + + if not compare_enum(aop.vas, eop.get("vas"), "vas"): + return False + if not compare_tbool(aop.is_vreg, eop.get("is_vreg"), "is_vreg"): + return False + + if not compare_int32( + aop.vector_index, eop.get("vector_index"), "vector_index" + ): + return False + + if not compare_tbool( + aop.is_list_member, eop.get("is_list_member"), "is_list_member" + ): + return False + + if not compare_enum(aop.type, eop["type"], "op type"): + return False + # Operand + if aop.type == AARCH64_OP_REG: + if not compare_reg(actual, aop.value.reg, eop.get("reg"), "reg"): + return False + elif aop.type == AARCH64_OP_IMM: + if not compare_int64(aop.value.imm, eop.get("imm"), "imm"): + return False + elif aop.type == AARCH64_OP_MEM: + if not compare_reg( + actual, aop.value.mem.base, eop.get("mem_base"), "mem_base" + ): + return False + if not compare_reg( + actual, aop.value.mem.index, eop.get("mem_index"), "mem_index" + ): + return False + if not compare_int32(aop.value.mem.disp, eop.get("mem_disp"), "mem_disp"): + return False + elif aop.type == AARCH64_OP_IMM_RANGE: + if not compare_int8( + aop.value.imm_range.first, eop.get("imm_range_first"), "imm_range_first" + ): + return False + if not compare_int8( + aop.value.imm_range.offset, + eop.get("imm_range_offset"), + "imm_range_offset", + ): + return False + elif aop.type == AARCH64_OP_FP: + if not compare_fp(aop.value.fp, eop.get("fp"), "fp"): + return False + elif aop.type == AARCH64_OP_SYSREG: + if not compare_enum( + aop.value.sysop.sub_type, eop.get("sub_type"), "sub_type" + ): + return False + if not compare_uint64( + aop.value.sysop.reg.raw_val, eop.get("sys_raw_val"), "sys_raw_val" + ): + return False + elif aop.type == AARCH64_OP_SYSIMM: + if not compare_enum( + aop.value.sysop.sub_type, eop.get("sub_type"), "sub_type" + ): + return False + if not compare_uint64( + aop.value.sysop.imm.raw_val, eop.get("sys_raw_val"), "sys_raw_val" + ): + return False + elif aop.type == AARCH64_OP_SYSALIAS: + if not compare_enum( + aop.value.sysop.sub_type, eop.get("sub_type"), "sub_type" + ): + return False + if not compare_uint64( + aop.value.sysop.alias.raw_val, eop.get("sys_raw_val"), "sys_raw_val" + ): + return False + elif aop.type == AARCH64_OP_PRED: + if not compare_reg( + actual, aop.value.pred.reg, eop.get("pred_reg"), "pred_reg" + ): + return False + if not compare_reg( + actual, + aop.value.pred.vec_select, + eop.get("pred_vec_select"), + "pred_vec_select", + ): + return False + if not compare_int32( + aop.value.pred.imm_index, + eop.get("pred_imm_index"), + "pred_imm_index", + ): + return False + elif aop.type == AARCH64_OP_SME: + if "sme" not in eop: + continue + + if not compare_enum(aop.value.sme.type, eop["sme"].get("type"), "type"): + return False + if not compare_reg( + actual, aop.value.sme.tile, eop["sme"].get("tile"), "tile" + ): + return False + if not compare_reg( + actual, + aop.value.sme.slice_reg, + eop["sme"].get("slice_reg"), + "slice_reg", + ): + return False + if not compare_int8( + aop.value.sme.slice_offset.imm, + eop["sme"].get("slice_offset_imm"), + "slice_offset_imm", + ): + return False + if not compare_int8( + aop.value.sme.slice_offset.imm_range.first, + eop["sme"].get("slice_offset_ir_first"), + "slice_offset_ir_first", + ): + return False + if not compare_int8( + aop.value.sme.slice_offset.imm_range.offset, + eop["sme"].get("slice_offset_ir_offset"), + "slice_offset_ir_offset", + ): + return False + if not compare_tbool( + aop.value.sme.has_range_offset, + eop["sme"].get("has_range_offset"), + "has_range_offset", + ): + return False + if not compare_tbool( + aop.value.sme.is_vertical, eop["sme"].get("is_vertical"), "is_vertical" + ): + return False + else: + raise ValueError(f"Operand type not handled: {aop.type}") + return True + + +def test_expected_sparc(actual: CsInsn, expected: dict) -> bool: + if not compare_enum(actual.cc, expected.get("cc"), "cc"): + return False + if not compare_enum(actual.hint, expected.get("hint"), "hint"): + return False + + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected.get("operands")), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.type, eop.get("type"), "type"): + return False + + if aop.type == SPARC_OP_REG: + if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): + return False + elif aop.type == SPARC_OP_IMM: + if not compare_int64(aop.imm, eop.get("imm"), "imm"): + return False + elif aop.type == SPARC_OP_MEM: + if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"): + return False + if not compare_reg( + actual, aop.mem.index, eop.get("mem_index"), "mem_index" + ): + return False + if not compare_int32(aop.mem.disp, eop.get("mem_disp"), "mem_disp"): + return False + else: + raise ValueError("Operand type not handled.") + return True + + +def test_expected_tricore(actual: CsInsn, expected: dict) -> bool: + if not compare_tbool( + actual.update_flags, expected.get("update_flags"), "update_flags" + ): + return False + + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected.get("operands")), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.type, eop.get("type"), "type"): + return False + if not compare_enum(aop.access, eop.get("access"), "access"): + return False + + if aop.type == TRICORE_OP_REG: + if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): + return False + elif aop.type == TRICORE_OP_IMM: + if not compare_int64(aop.imm, eop.get("imm"), "imm"): + return False + elif aop.type == TRICORE_OP_MEM: + if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"): + return False + if not compare_int64(aop.mem.disp, eop.get("mem_disp"), "mem_disp"): + return False + else: + raise ValueError("Operand type not handled.") + return True + + +def test_expected_evm(actual: CsInsn, expected: dict) -> bool: + if not compare_uint8(actual.pop, expected.get("pop"), "pop"): + return False + if not compare_uint8(actual.push, expected.get("push"), "push"): + return False + if not compare_int32(actual.fee, expected.get("fee"), "fee"): + return False + return True + + +def test_expected_alpha(actual: CsInsn, expected: dict) -> bool: + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected.get("operands")), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.type, eop.get("type"), "type"): + return False + if not compare_enum(aop.access, eop.get("access"), "access"): + return False + + if aop.type == ALPHA_OP_REG: + if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): + return False + elif aop.type == ALPHA_OP_IMM: + if not compare_int32(aop.imm, eop.get("imm"), "imm"): + return False + else: + raise ValueError("Operand type not handled.") + return True + + +def test_expected_xcore(actual: CsInsn, expected: dict) -> bool: + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected.get("operands")), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.type, eop.get("type"), "type"): + return False + + if aop.type == XCORE_OP_REG: + if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): + return False + elif aop.type == XCORE_OP_IMM: + if not compare_int32(aop.imm, eop.get("imm"), "imm"): + return False + elif aop.type == XCORE_OP_MEM: + if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"): + return False + if not compare_reg( + actual, aop.mem.index, eop.get("mem_index"), "mem_index" + ): + return False + if not compare_int32(aop.mem.disp, eop.get("mem_disp"), "mem_disp"): + return False + if not compare_int32(aop.mem.direct, eop.get("mem_direct"), "mem_direct"): + return False + else: + raise ValueError("Operand type not handled.") + return True + + +def test_expected_tms320c64x(actual: CsInsn, expected: dict) -> bool: + if not compare_reg( + actual, actual.condition.reg, expected.get("cond_reg"), "cond_reg" + ): + return False + if not compare_tbool(actual.condition.zero, expected.get("cond_zero"), "cond_zero"): + return False + + if not compare_enum(actual.funit.unit, expected.get("funit_unit"), "funit_unit"): + return False + if not compare_uint8(actual.funit.side, expected.get("funit_side"), "funit_side"): + return False + if not compare_uint8( + actual.funit.crosspath, expected.get("funit_crosspath"), "funit_crosspath" + ): + return False + + if not compare_int8(actual.parallel, expected.get("parallel"), "parallel"): + return False + + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected.get("operands")), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.type, eop.get("type"), "type"): + return False + + if aop.type == TMS320C64X_OP_REG: + if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): + return False + elif aop.type == TMS320C64X_OP_REGPAIR: + if not compare_reg( + actual, aop.reg + 1, eop.get("reg_pair_0"), "reg_pair_0" + ): + return False + if not compare_reg(actual, aop.reg, eop.get("reg_pair_1"), "reg_pair_1"): + return False + elif aop.type == TMS320C64X_OP_IMM: + if not compare_int32(aop.imm, eop.get("imm"), "imm"): + return False + elif aop.type == TMS320C64X_OP_MEM: + if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"): + return False + if not compare_tbool(aop.mem.scaled, eop.get("mem_scaled"), "mem_scaled"): + return False + if not compare_enum( + aop.mem.disptype, eop.get("mem_disptype"), "mem_disptype" + ): + return False + if not compare_enum( + aop.mem.direction, eop.get("mem_direction"), "mem_direction" + ): + return False + if not compare_enum(aop.mem.modify, eop.get("mem_modify"), "mem_modify"): + return False + if aop.mem.disptype == TMS320C64X_MEM_DISP_REGISTER: + if not compare_reg( + actual, aop.mem.disp, eop.get("mem_disp_reg"), "mem_disp_reg" + ): + return False + elif aop.mem.disptype == TMS320C64X_MEM_DISP_CONSTANT: + if not compare_uint32( + aop.mem.disp, eop.get("mem_disp_const"), "mem_disp_const" + ): + return False + else: + raise ValueError("TMS320c64x memory offset type not handled.") + + if not compare_uint32(aop.mem.unit, eop.get("mem_unit"), "mem_unit"): + return False + else: + raise ValueError("Operand type not handled.") + + return True + + +def test_expected_m68k(actual: CsInsn, expected: dict) -> bool: + if not compare_enum( + actual.op_size.type, expected.get("op_size_type"), "op_size_type" + ): + return False + if not compare_enum( + actual.op_size.size, expected.get("op_size_fpu"), "op_size_fpu" + ): + return False + if not compare_enum( + actual.op_size.size, expected.get("op_size_cpu"), "op_size_cpu" + ): + return False + + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected.get("operands")), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.type, eop.get("type"), "type"): + return False + if not compare_enum(aop.address_mode, eop.get("address_mode"), "address_mode"): + return False + + if aop.type == M68K_OP_REG: + if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): + return False + elif aop.type == M68K_OP_REG_PAIR: + if not compare_reg( + actual, aop.reg_pair.reg_0, eop.get("reg_pair_0"), "reg_pair_0" + ): + return False + if not compare_reg( + actual, aop.reg_pair.reg_1, eop.get("reg_pair_1"), "reg_pair_1" + ): + return False + elif aop.type == M68K_OP_IMM: + if not compare_uint64(aop.imm, eop.get("imm"), "imm"): + return False + elif aop.type == M68K_OP_BR_DISP: + if not compare_int32(aop.br_disp.disp, eop.get("br_disp"), "br_disp"): + return False + if not compare_uint8( + aop.br_disp.disp_size, eop.get("br_disp_size"), "br_disp_size" + ): + return False + elif aop.type == M68K_OP_REG_BITS: + if not compare_uint32( + aop.register_bits, eop.get("register_bits"), "register_bits" + ): + return False + elif aop.type == M68K_OP_FP_DOUBLE: + if not compare_dp(aop.dimm, eop.get("dimm"), "dimm"): + return False + elif aop.type == M68K_OP_FP_SINGLE: + if not compare_fp(aop.simm, eop.get("simm"), "simm"): + return False + elif aop.type == M68K_OP_MEM: + if "mem" not in eop: + continue + + if not compare_reg( + actual, aop.mem.base_reg, eop["mem"].get("base_reg"), "base_reg" + ): + return False + if not compare_reg( + actual, aop.mem.index_reg, eop["mem"].get("index_reg"), "index_reg" + ): + return False + if not compare_reg( + actual, + aop.mem.in_base_reg, + eop["mem"].get("in_base_reg"), + "in_base_reg", + ): + return False + if not compare_tbool( + aop.mem.index_size, eop["mem"].get("index_size"), "index_size" + ): + return False + if not compare_int16(aop.mem.disp, eop["mem"].get("disp"), "disp"): + return False + if not compare_uint32( + aop.mem.in_disp, eop["mem"].get("in_disp"), "in_disp" + ): + return False + if not compare_uint32( + aop.mem.out_disp, eop["mem"].get("out_disp"), "out_disp" + ): + return False + if not compare_uint8(aop.mem.scale, eop["mem"].get("scale"), "scale"): + return False + if not compare_uint8( + aop.mem.bitfield, eop["mem"].get("bitfield"), "bitfield" + ): + return False + if not compare_uint8(aop.mem.width, eop["mem"].get("width"), "width"): + return False + if not compare_uint8(aop.mem.offset, eop["mem"].get("offset"), "offset"): + return False + else: + raise ValueError("Operand type not handled.") + return True + + +def test_expected_bpf(actual: CsInsn, expected: dict) -> bool: + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected.get("operands")), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.type, eop.get("type"), "type"): + return False + if not compare_enum(aop.access, eop.get("access"), "access"): + return False + + if aop.type == BPF_OP_REG: + if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): + return False + elif aop.type == BPF_OP_IMM: + if not compare_uint64(aop.imm, eop.get("imm"), "imm"): + return False + elif aop.type == BPF_OP_OFF: + if not compare_uint32(aop.off, eop.get("off"), "off"): + return False + elif aop.type == BPF_OP_MMEM: + if not compare_uint32(aop.mmem, eop.get("mmem"), "mmem"): + return False + elif aop.type == BPF_OP_MSH: + if not compare_uint32(aop.msh, eop.get("msh"), "msh"): + return False + elif aop.type == BPF_OP_EXT: + if not compare_enum(aop.ext, eop.get("ext"), "ext"): + return False + elif aop.type == BPF_OP_MEM: + if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"): + return False + if not compare_uint32(aop.mem.disp, eop.get("mem_disp"), "mem_disp"): + return False + else: + raise ValueError("Operand type not handled.") + return True + + +def test_expected_sh(actual: CsInsn, expected: dict) -> bool: + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected.get("operands")), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.type, eop.get("type"), "type"): + return False + + if aop.type == SH_OP_REG: + if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): + return False + elif aop.type == SH_OP_IMM: + if not compare_uint64(aop.imm, eop.get("imm"), "imm"): + return False + elif aop.type == SH_OP_MEM: + if not compare_reg(actual, aop.mem.reg, eop.get("mem_reg"), "mem_reg"): + return False + if not compare_reg( + actual, aop.mem.address, eop.get("mem_address"), "mem_address" + ): + return False + if not compare_int32(aop.mem.disp, eop.get("mem_disp"), "mem_disp"): + return False + else: + raise ValueError("Operand type not handled.") + return True + + +def test_expected_hppa(actual: CsInsn, expected: dict) -> bool: + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected.get("operands")), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.type, eop.get("type"), "type"): + return False + if not compare_enum(aop.access, eop.get("access"), "access"): + return False + + if aop.type == HPPA_OP_REG or aop.type == HPPA_OP_IDX_REG: + if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): + return False + elif ( + aop.type == HPPA_OP_IMM + or aop.type == HPPA_OP_DISP + or aop.type == HPPA_OP_TARGET + ): + if not compare_int64(aop.imm, eop.get("imm"), "imm"): + return False + elif aop.type == HPPA_OP_MEM: + if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"): + return False + if not compare_reg( + actual, aop.mem.space, eop.get("mem_space"), "mem_space" + ): + return False + if not compare_reg( + actual, + aop.mem.base_access, + eop.get("mem_base_access"), + "mem_base_access", + ): + return False + else: + raise ValueError("Operand type not handled.") + return True + + +def test_expected_riscv(actual: CsInsn, expected: dict) -> bool: + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected.get("operands")), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.type, eop.get("type"), "type"): + return False + if not compare_enum(aop.access, eop.get("access"), "access"): + return False + + if aop.type == RISCV_OP_REG: + if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): + return False + elif aop.type == RISCV_OP_IMM: + if not compare_uint64(aop.imm, eop.get("imm"), "imm"): + return False + elif aop.type == RISCV_OP_MEM: + if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"): + return False + if not compare_int64(aop.mem.disp, eop.get("mem_disp"), "mem_disp"): + return False + else: + raise ValueError("Operand type not handled.") + return True + + +def test_expected_mips(actual: CsInsn, expected: dict) -> bool: + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected.get("operands")), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.type, eop.get("type"), "type"): + return False + + if aop.type == MIPS_OP_REG: + if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): + return False + elif aop.type == MIPS_OP_IMM: + if not compare_uint64(aop.imm, eop.get("imm"), "imm"): + return False + elif aop.type == MIPS_OP_MEM: + if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"): + return False + if not compare_int64(aop.mem.disp, eop.get("mem_disp"), "mem_disp"): + return False + else: + raise ValueError("Operand type not handled.") + return True + + +def test_expected_sysz(actual: CsInsn, expected: dict) -> bool: + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected.get("operands")), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.type, eop.get("type"), "type"): + return False + + if aop.type == SYSZ_OP_REG: + if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): + return False + elif aop.type == SYSZ_OP_IMM: + if not compare_int64(aop.imm, eop.get("imm"), "imm"): + return False + elif aop.type == SYSZ_OP_MEM: + if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"): + return False + if not compare_reg( + actual, aop.mem.index, eop.get("mem_index"), "mem_index" + ): + return False + if not compare_int64(aop.mem.disp, eop.get("mem_disp"), "mem_disp"): + return False + if not compare_uint64(aop.mem.length, eop.get("mem_length"), "mem_length"): + return False + else: + raise ValueError("Operand type not handled.") + return True + + +def test_expected_mos65xx(actual: CsInsn, expected: dict) -> bool: + if not compare_enum(actual.am, expected.get("am"), "am"): + return False + if not compare_tbool( + actual.modifies_flags, expected.get("modifies_flags"), "modifies_flags" + ): + return False + + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected.get("operands")), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.type, eop.get("type"), "type"): + return False + + if aop.type == MOS65XX_OP_REG: + if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): + return False + elif aop.type == MOS65XX_OP_IMM: + if not compare_uint16(aop.imm, eop.get("imm"), "imm"): + return False + elif aop.type == MOS65XX_OP_MEM: + if not compare_uint32(aop.mem, eop.get("mem"), "mem"): + return False + else: + raise ValueError("Operand type not handled.") + return True + + +def test_expected_loongarch(actual: CsInsn, expected: dict) -> bool: + if not compare_enum(actual.format, expected.get("format"), "format"): + return False + + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected.get("operands")), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.type, eop.get("type"), "type"): + return False + if not compare_enum(aop.access, eop.get("access"), "access"): + return False + + if aop.type == LOONGARCH_OP_REG: + if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): + return False + elif aop.type == LOONGARCH_OP_IMM: + if not compare_uint64(aop.imm, eop.get("imm"), "imm"): + return False + elif aop.type == LOONGARCH_OP_MEM: + if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"): + return False + if not compare_reg( + actual, aop.mem.index, eop.get("mem_index"), "mem_index" + ): + return False + if not compare_int64(aop.mem.disp, eop.get("mem_disp"), "mem_disp"): + return False + else: + raise ValueError("Operand type not handled.") + return True + + +def test_expected_wasm(actual: CsInsn, expected: dict) -> bool: + if "operands" not in expected: + return True + elif not compare_uint32( + len(actual.operands), len(expected.get("operands")), "operands_count" + ): + return False + + for aop, eop in zip(actual.operands, expected["operands"]): + if not compare_enum(aop.type, eop.get("type"), "type"): + return False + + if not compare_uint32(aop.size, eop.get("size"), "size"): + return False + if aop.type == WASM_OP_INT7: + if not compare_int8(aop.int7, eop.get("int7"), "int7"): + return False + elif aop.type == WASM_OP_VARUINT32: + if not compare_uint32(aop.varuint32, eop.get("varuint32"), "varuint32"): + return False + elif aop.type == WASM_OP_VARUINT64: + if not compare_uint64(aop.varuint64, eop.get("varuint64"), "varuint64"): + return False + elif aop.type == WASM_OP_UINT32: + if not compare_uint32(aop.uint32, eop.get("uint32"), "uint32"): + return False + elif aop.type == WASM_OP_UINT64: + if not compare_uint64(aop.uint64, eop.get("uint64"), "uint64"): + return False + elif aop.type == WASM_OP_IMM: + if not compare_uint32( + aop.immediate[0], eop.get("immediate_0"), "immediate_0" + ): + return False + if not compare_uint32( + aop.immediate[1], eop.get("immediate_1"), "immediate_1" + ): + return False + elif aop.type == WASM_OP_BRTABLE: + if not compare_uint32( + aop.brtable.length, eop.get("brt_length"), "brt_length" + ): + return False + if not compare_uint64( + aop.brtable.address, eop.get("brt_address"), "brt_address" + ): + return False + if not compare_uint32( + aop.brtable.default_target, + eop.get("brt_default_target"), + "brt_default_target", + ): + return False + else: + raise ValueError("Operand type not handled.") + return True diff --git a/bindings/python/setup.py b/bindings/python/setup.py index f72ea393c8..e96a4589e8 100755 --- a/bindings/python/setup.py +++ b/bindings/python/setup.py @@ -72,10 +72,12 @@ LIBRARY_FILE = "libcapstone.so" STATIC_LIBRARY_FILE = 'libcapstone.a' + def clean_bins(): shutil.rmtree(LIBS_DIR, ignore_errors=True) shutil.rmtree(HEADERS_DIR, ignore_errors=True) + def copy_sources(): """Copy the C sources into the source directory. This rearranges the source files under the python distribution @@ -92,22 +94,19 @@ def copy_sources(): shutil.copytree(os.path.join(BUILD_DIR, "include"), os.path.join(SRC_DIR, "include")) src.extend(glob.glob(os.path.join(BUILD_DIR, "*.[ch]"))) - src.extend(glob.glob(os.path.join(BUILD_DIR, "*.mk"))) - src.extend(glob.glob(os.path.join(BUILD_DIR, "Makefile"))) src.extend(glob.glob(os.path.join(BUILD_DIR, "LICENSES/*"))) src.extend(glob.glob(os.path.join(BUILD_DIR, "README"))) src.extend(glob.glob(os.path.join(BUILD_DIR, "*.TXT"))) src.extend(glob.glob(os.path.join(BUILD_DIR, "RELEASE_NOTES"))) - src.extend(glob.glob(os.path.join(BUILD_DIR, "make.sh"))) src.extend(glob.glob(os.path.join(BUILD_DIR, "CMakeLists.txt"))) - src.extend(glob.glob(os.path.join(BUILD_DIR, "pkgconfig.mk"))) for filename in src: outpath = os.path.join(SRC_DIR, os.path.basename(filename)) logger.info("%s -> %s" % (filename, outpath)) shutil.copy(filename, outpath) + def build_libraries(): """ Prepare the capstone directory for a binary distribution or installation. @@ -134,23 +133,22 @@ def build_libraries(): os.chdir(BUILD_DIR) - # platform description refers at https://docs.python.org/3/library/sys.html#sys.platform - # Use cmake for both Darwin and Windows since it can generate fat binaries - if SYSTEM == "win32" or SYSTEM == 'darwin': - # Windows build: this process requires few things: - # - CMake + MSVC installed - # - Run this command in an environment setup for MSVC - if not os.path.exists("build"): os.mkdir("build") - os.chdir("build") - print("Build Directory: {}\n".format(os.getcwd())) - # Only build capstone.dll / libcapstone.dylib - if SYSTEM == "win32": - os.system('cmake -DCMAKE_BUILD_TYPE=Release -DBUILD_SHARED_LIBS=ON -DCAPSTONE_BUILD_TESTS=OFF -DCAPSTONE_BUILD_CSTOOL=OFF -G "NMake Makefiles" ..') - else: - os.system('cmake -DCMAKE_BUILD_TYPE=Release -DBUILD_SHARED_LIBS=ON -DCAPSTONE_BUILD_TESTS=OFF -DCAPSTONE_BUILD_CSTOOL=OFF -G "Unix Makefiles" ..') - os.system("cmake --build .") - else: # Unix incl. cygwin - os.system("CAPSTONE_BUILD_CORE_ONLY=yes bash ./make.sh") + # Windows build: this process requires few things: + # - MSVC installed + # - Run this command in an environment setup for MSVC + if not os.path.exists("build_py"): + os.mkdir("build_py") + os.chdir("build_py") + print("Build Directory: {}\n".format(os.getcwd())) + # Only build capstone.dll / libcapstone.dylib + if SYSTEM == "win32": + os.system('cmake -DCMAKE_BUILD_TYPE=Release -DBUILD_SHARED_LIBS=ON -DCAPSTONE_BUILD_LEGACY_TESTS=OFF -DCAPSTONE_BUILD_CSTOOL=OFF -G "NMake Makefiles" ..') + elif 'AFL_NOOPT' in os.environ: + # build for test_corpus + os.system('cmake -DBUILD_SHARED_LIBS=ON -DCAPSTONE_BUILD_LEGACY_TESTS=OFF -DCAPSTONE_BUILD_CSTOOL=OFF ..') + else: + os.system('cmake -DCMAKE_BUILD_TYPE=Release -DBUILD_SHARED_LIBS=ON -DCAPSTONE_BUILD_LEGACY_TESTS=OFF -DCAPSTONE_BUILD_CSTOOL=OFF -G "Unix Makefiles" ..') + os.system("cmake --build .") shutil.copy(VERSIONED_LIBRARY_FILE, os.path.join(LIBS_DIR, LIBRARY_FILE)) @@ -182,8 +180,6 @@ def run(self): self.run_command('build') return bdist_egg.run(self) -def dummy_src(): - return [] cmdclass = {} cmdclass['build'] = custom_build @@ -192,6 +188,7 @@ def dummy_src(): try: from setuptools.command.develop import develop + class custom_develop(develop): def run(self): logger.info("Building C extensions") diff --git a/bindings/python/tests/test_aarch64.py b/bindings/python/tests/test_aarch64.py deleted file mode 100755 index df9ca0e623..0000000000 --- a/bindings/python/tests/test_aarch64.py +++ /dev/null @@ -1,193 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Nguyen Anh Quynnh - -from capstone import * -from capstone.aarch64 import * -from xprint import to_hex, to_x, to_x_32 - - -AArch64_CODE = b"\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c\xfd\x7b\xba\xa9\xfd\xc7\x43\xf8" - -all_tests = ( - (CS_ARCH_AARCH64, CS_MODE_ARM, AArch64_CODE, "AARCH64"), - ) - - -def print_insn_detail(insn): - # print address, mnemonic and operands - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - - if len(insn.operands) > 0: - print("\top_count: %u" % len(insn.operands)) - c = -1 - for i in insn.operands: - c += 1 - if i.type == AARCH64_OP_REG: - print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) - if i.type == AARCH64_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) - if i.type == AARCH64_OP_CIMM: - print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm)) - if i.type == AARCH64_OP_FP: - print("\t\toperands[%u].type: FP = %f" % (c, i.fp)) - if i.type == AARCH64_OP_MEM: - print("\t\toperands[%u].type: MEM" % c) - if i.mem.base != 0: - print("\t\t\toperands[%u].mem.base: REG = %s" \ - % (c, insn.reg_name(i.mem.base))) - if i.mem.index != 0: - print("\t\t\toperands[%u].mem.index: REG = %s" \ - % (c, insn.reg_name(i.mem.index))) - if i.mem.disp != 0: - print("\t\t\toperands[%u].mem.disp: 0x%s" \ - % (c, to_x_32(i.mem.disp))) - if insn.post_index: - print("\t\t\tpost-indexed: true"); - if i.type == AARCH64_OP_SME: - print("\t\toperands[%u].type: SME_MATRIX" % (c)) - print("\t\toperands[%u].sme.type: %d" % (c, i.sme.type)) - - if i.sme.tile != AARCH64_REG_INVALID: - print("\t\toperands[%u].sme.tile: %s" % (c, insn.reg_name(i.sme.tile))) - if i.sme.slice_reg != AARCH64_REG_INVALID: - print("\t\toperands[%u].sme.slice_reg: %s" % (c, insn.reg_name(i.sme.slice_reg))) - if i.sme.slice_offset.imm != -1 or i.sme.slice_offset.imm_range.first != -1: - print("\t\toperands[%u].sme.slice_offset: " % (c)) - if i.sme.has_range_offset: - print("%hhd:%hhd" % (i.sme.slice_offset.imm_range.first, i.sme.slice_offset.imm_range.offset)) - else: - print("%d" % (i.sme.slice_offset.imm)) - if i.sme.slice_reg != AARCH64_REG_INVALID or i.sme.slice_offset.imm != -1: - print("\t\toperands[%u].sme.is_vertical: %s" % (c, ("true" if i.sme.is_vertical else "false"))) - if i.type == AARCH64_OP_PRED: - print("\t\toperands[%u].type: PREDICATE\n" % c); - if (op.pred.reg != AARCH64_REG_INVALID): - print("\t\toperands[%u].pred.reg: %s\n" % (c, insn.reg_name(i.pred.reg))); - if (op.pred.vec_select != AARCH64_REG_INVALID): - print("\t\toperands[%u].pred.vec_select: %s\n" % (c, insn.reg_name(i.pred.vec_select))); - if (op.pred.imm_index != -1): - print("\t\toperands[%u].pred.imm_index: %d\n" % (i, op.pred.imm_index)); - break; - if i.type == AARCH64_OP_SYSREG: - print("\t\toperands[%u].type: SYS REG:" % (c)) - if i.sysop.sub_type == AARCH64_OP_REG_MRS: - print("\t\toperands[%u].subtype: REG_MRS = 0x%x" % (c, i.sysop.reg.sysreg)) - if i.sysop.sub_type == AARCH64_OP_REG_MSR: - print("\t\toperands[%u].subtype: REG_MSR = 0x%x" % (c, i.sysop.reg.sysreg)) - if i.sysop.sub_type == AARCH64_OP_TLBI: - print("\t\toperands[%u].subtype TLBI = 0x%x" % (c, i.sysop.reg.tlbi)) - if i.sysop.sub_type == AARCH64_OP_IC: - print("\t\toperands[%u].subtype IC = 0x%x" % (c, i.sysop.reg.ic)) - if i.type == AARCH64_OP_SYSALIAS: - print("\t\toperands[%u].type: SYS ALIAS:" % (c)) - if i.sysop.sub_type == AARCH64_OP_SVCR: - if i.sysop.alias.svcr == AARCH64_SVCR_SVCRSM: - print("\t\t\toperands[%u].svcr: BIT = SM" % (c)) - elif i.sysop.alias.svcr == AARCH64_SVCR_SVCRZA: - print("\t\t\toperands[%u].svcr: BIT = ZA" % (c)) - elif i.sysop.alias.svcr == AARCH64_SVCR_SVCRSMZA: - print("\t\t\toperands[%u].svcr: BIT = SM & ZA" % (c)) - if i.sysop.sub_type == AARCH64_OP_AT: - print("\t\toperands[%u].subtype AT = 0x%x" % (c, i.sysop.alias.at)) - if i.sysop.sub_type == AARCH64_OP_DB: - print("\t\toperands[%u].subtype DB = 0x%x" % (c, i.sysop.alias.db)) - if i.sysop.sub_type == AARCH64_OP_DC: - print("\t\toperands[%u].subtype DC = 0x%x" % (c, i.sysop.alias.dc)) - if i.sysop.sub_type == AARCH64_OP_ISB: - print("\t\toperands[%u].subtype ISB = 0x%x" % (c, i.sysop.alias.isb)) - if i.sysop.sub_type == AARCH64_OP_TSB: - print("\t\toperands[%u].subtype TSB = 0x%x" % (c, i.sysop.alias.tsb)) - if i.sysop.sub_type == AARCH64_OP_PRFM: - print("\t\toperands[%u].subtype PRFM = 0x%x" % (c, i.sysop.alias.prfm)) - if i.sysop.sub_type == AARCH64_OP_SVEPRFM: - print("\t\toperands[%u].subtype SVEPRFM = 0x%x" % (c, i.sysop.alias.sveprfm)) - if i.sysop.sub_type == AARCH64_OP_RPRFM: - print("\t\toperands[%u].subtype RPRFM = 0x%x" % (c, i.sysop.alias.rprfm)) - if i.sysop.sub_type == AARCH64_OP_PSTATEIMM0_15: - print("\t\toperands[%u].subtype PSTATEIMM0_15 = 0x%x" % (c, i.sysop.alias.pstateimm0_15)) - if i.sysop.sub_type == AARCH64_OP_PSTATEIMM0_1: - print("\t\toperands[%u].subtype PSTATEIMM0_1 = 0x%x" % (c, i.sysop.alias.pstateimm0_1)) - if i.sysop.sub_type == AARCH64_OP_PSB: - print("\t\toperands[%u].subtype PSB = 0x%x" % (c, i.sysop.alias.psb)) - if i.sysop.sub_type == AARCH64_OP_BTI: - print("\t\toperands[%u].subtype BTI = 0x%x" % (c, i.sysop.alias.bti)) - if i.sysop.sub_type == AARCH64_OP_SVEPREDPAT: - print("\t\toperands[%u].subtype SVEPREDPAT = 0x%x" % (c, i.sysop.alias.svepredpat)) - if i.sysop.sub_type == AARCH64_OP_SVEVECLENSPECIFIER: - print("\t\toperands[%u].subtype SVEVECLENSPECIFIER = 0x%x" % (c, i.sysop.alias.sveveclenspecifier)) - if i.type == AARCH64_OP_SYSIMM: - print("\t\toperands[%u].type: SYS IMM:" % (c)) - if i.sysop.sub_type == AARCH64_OP_EXACTFPIMM: - print("\t\toperands[%u].subtype EXACTFPIMM = %d" % (c, i.sysop.imm.exactfpimm)) - if i.sysop.sub_type == AARCH64_OP_DBNXS: - print("\t\toperands[%u].subtype DBNXS = %d" % (c, i.sysop.imm.dbnxs)) - - if i.access == CS_AC_READ: - print("\t\toperands[%u].access: READ" % (c)) - elif i.access == CS_AC_WRITE: - print("\t\toperands[%u].access: WRITE" % (c)) - elif i.access == CS_AC_READ | CS_AC_WRITE: - print("\t\toperands[%u].access: READ | WRITE" % (c)) - - if i.shift.type != AARCH64_SFT_INVALID and i.shift.value: - print("\t\t\tShift: type = %u, value = %u" % (i.shift.type, i.shift.value)) - - if i.ext != AARCH64_EXT_INVALID: - print("\t\t\tExt: %u" % i.ext) - - if i.vas != AARCH64LAYOUT_INVALID: - print("\t\t\tVector Arrangement Specifier: 0x%x" % i.vas) - - if i.vector_index != -1: - print("\t\t\tVector Index: %u" % i.vector_index) - - if insn.writeback: - print("\tWrite-back: True") - - if insn.cc != AArch64CC_Invalid: - print("\tCode-condition: %u" % insn.cc) - if insn.update_flags: - print("\tUpdate-flags: True") - - (regs_read, regs_write) = insn.regs_access() - - if len(regs_read) > 0: - print("\tRegisters read:", end="") - for r in regs_read: - print(" %s" %(insn.reg_name(r)), end="") - print("") - - if len(regs_write) > 0: - print("\tRegisters modified:", end="") - for r in regs_write: - print(" %s" %(insn.reg_name(r)), end="") - print("") - - -# ## Test class Cs -def test_class(): - - for (arch, mode, code, comment) in all_tests: - print("*" * 16) - print("Platform: %s" % comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - md.detail = True - for insn in md.disasm(code, 0x2c): - print_insn_detail(insn) - print () - print("0x%x:\n" % (insn.address + insn.size)) - except CsError as e: - print("ERROR: %s" % e) - - -if __name__ == '__main__': - test_class() diff --git a/bindings/python/tests/test_all.py b/bindings/python/tests/test_all.py index 4b9ead884e..b5f3942f09 100755 --- a/bindings/python/tests/test_all.py +++ b/bindings/python/tests/test_all.py @@ -1,26 +1,9 @@ #!/usr/bin/env python3 -import test_basic, test_arm, test_aarch64, test_detail, test_lite, test_m68k, test_mips, \ - test_ppc, test_x86, test_skipdata, test_sparc, test_systemz, test_tms320c64x, test_customized_mnem, \ - test_m680x, test_mos65xx, test_xcore, test_riscv, test_alpha, test_hppa +import test_lite +import test_skipdata +import test_customized_mnem -test_basic.test_class() -test_arm.test_class() -test_aarch64.test_class() -test_detail.test_class() test_lite.test_class() -test_m68k.test_class() -test_mips.test_class() -test_mos65xx.test_class() -test_ppc.test_class() -test_sparc.test_class() -test_systemz.test_class() -test_x86.test_class() -test_tms320c64x.test_class() -test_m680x.test_class() test_skipdata.test_class() test_customized_mnem.test() -test_xcore.test_class() -test_riscv.test_class() -test_alpha.test_class() -test_hppa.test_class() diff --git a/bindings/python/tests/test_alpha.py b/bindings/python/tests/test_alpha.py deleted file mode 100755 index 056288ae2d..0000000000 --- a/bindings/python/tests/test_alpha.py +++ /dev/null @@ -1,57 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Dmitry Sibirtsev - -from capstone import * -from capstone.alpha import * -from xprint import to_x, to_hex - -ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7' -ALPHA_CODE_BE = b'\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00' - -all_tests = ( - (CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN, ALPHA_CODE, "Alpha (Little-endian)"), - (CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN, ALPHA_CODE_BE, "Alpha (Big-endian)"), -) - - -def print_insn_detail(insn): - # print address, mnemonic and operands - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - - if len(insn.operands) > 0: - print("\top_count: %u" % len(insn.operands)) - c = 0 - for i in insn.operands: - if i.type == ALPHA_OP_REG: - print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) - if i.type == ALPHA_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) - c += 1 - - -# ## Test class Cs -def test_class(): - for (arch, mode, code, comment) in all_tests: - print("*" * 16) - print("Platform: %s" % comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - md.detail = True - for insn in md.disasm(code, 0x1000): - print_insn_detail(insn) - print() - print("0x%x:\n" % (insn.address + insn.size)) - except CsError as e: - print("ERROR: %s" % e) - - -if __name__ == '__main__': - test_class() diff --git a/bindings/python/tests/test_arm.py b/bindings/python/tests/test_arm.py deleted file mode 100755 index 3056744628..0000000000 --- a/bindings/python/tests/test_arm.py +++ /dev/null @@ -1,189 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Nguyen Anh Quynnh - -from capstone import * -from capstone.arm import * -from xprint import to_hex, to_x_32 - - -ARM_CODE = b"\x86\x48\x60\xf4\x4d\x0f\xe2\xf4\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00" -ARM_CODE2 = b"\xd1\xe8\x00\xf0\xf0\x24\x04\x07\x1f\x3c\xf2\xc0\x00\x00\x4f\xf0\x00\x01\x46\x6c" -THUMB_CODE = b"\x60\xf9\x1f\x04\xe0\xf9\x4f\x07\x70\x47\x00\xf0\x10\xe8\xeb\x46\x83\xb0\xc9\x68\x1f\xb1\x30\xbf\xaf\xf3\x20\x84\x52\xf8\x23\xf0" -THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0\x18\xbf\xad\xbf\xf3\xff\x0b\x0c\x86\xf3\x00\x89\x80\xf3\x00\x8c\x4f\xfa\x99\xf6\xd0\xff\xa2\x01" -THUMB_MCLASS = b"\xef\xf3\x02\x80" -ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5" - -all_tests = ( - (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None), - (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "Thumb", None), - (CS_ARCH_ARM, CS_MODE_THUMB, ARM_CODE2, "Thumb-mixed", None), - (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "Thumb-2 & register named with numbers", CS_OPT_SYNTAX_NOREGNAME), - (CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None), - (CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None), - ) - - -def print_insn_detail(insn): - # print address, mnemonic and operands - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - - if len(insn.operands) > 0: - print("\top_count: %u" % len(insn.operands)) - c = 0 - for i in insn.operands: - if i.type == ARM_OP_REG: - print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) - elif i.type == ARM_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm))) - elif i.type == ARM_OP_FP: - print("\t\toperands[%u].type: FP = %f" % (c, i.fp)) - elif i.type == ARM_OP_PRED: - print("\t\toperands[%u].type: PRED = %d" % (c, i.pred)) - elif i.type == ARM_OP_CIMM: - print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm)) - elif i.type == ARM_OP_PIMM: - print("\t\toperands[%u].type: P-IMM = %u" % (c, i.imm)) - elif i.type == ARM_OP_SETEND: - if i.setend == ARM_SETEND_BE: - print("\t\toperands[%u].type: SETEND = be" % c) - else: - print("\t\toperands[%u].type: SETEND = le" % c) - elif i.type == ARM_OP_MEM: - print("\t\toperands[%u].type: MEM" % c) - if i.mem.base != 0: - print("\t\t\toperands[%u].mem.base: REG = %s" \ - % (c, insn.reg_name(i.mem.base))) - if i.mem.index != 0: - print("\t\t\toperands[%u].mem.index: REG = %s" \ - % (c, insn.reg_name(i.mem.index))) - if i.mem.scale != 1: - print("\t\t\toperands[%u].mem.scale: %u" \ - % (c, i.mem.scale)) - if i.mem.disp != 0: - print("\t\t\toperands[%u].mem.disp: 0x%s" \ - % (c, to_x_32(i.mem.disp))) - if i.mem.lshift != 0: - print("\t\t\toperands[%u].mem.lshift: 0x%s" \ - % (c, to_x_32(i.mem.lshift))) - elif i.type == ARM_OP_SYSM: - print("\t\toperands[%u].type: SYSM = 0x%x" % (c, i.sysop.sysm)) - print("\t\toperands[%u].type: MASK = %u" % (c, i.sysop.msr_mask)) - elif i.type == ARM_OP_SYSREG: - print("\t\toperands[%u].type: SYSREG = %s" % (c, insn.reg_name(i.sysop.reg.mclasssysreg))) - print("\t\toperands[%u].type: MASK = %u" % (c, i.sysop.msr_mask)) - elif i.type == ARM_OP_BANKEDREG: - print("\t\toperands[%u].type: BANKEDREG = %u" % (c, i.sysop.reg.bankedreg)) - if i.sysop.msr_mask != 2 ** (ctypes.sizeof(ctypes.c_uint8) * 8) - 1: - print("\t\toperands[%u].type: MASK = %u" % (c, i.sysop.msr_mask)) - elif i.type in [ARM_OP_SPSR, ARM_OP_CPSR]: - print("\t\toperands[%u].type: %sPSR = " % (c, "S" if i.type == ARM_OP_SPSR else "C"), end="") - field = i.sysop.psr_bits - if (field & ARM_FIELD_SPSR_F) > 0 or (field & ARM_FIELD_CPSR_F) > 0: - print("f", end="") - if (field & ARM_FIELD_SPSR_S) > 0 or (field & ARM_FIELD_CPSR_S) > 0: - print("s", end="") - if (field & ARM_FIELD_SPSR_X) > 0 or (field & ARM_FIELD_CPSR_X) > 0: - print("x", end="") - if (field & ARM_FIELD_SPSR_C) > 0 or (field & ARM_FIELD_CPSR_C) > 0: - print("c", end="") - print() - print("\t\toperands[%u].type: MASK = %u" % (c, i.sysop.msr_mask)) - else: - print("\t\toperands[%u].type: UNKNOWN = %u" % (c, i.type)) - - if i.neon_lane != -1: - print("\t\toperands[%u].neon_lane = %u" % (c, i.neon_lane)) - - if i.access == CS_AC_READ: - print("\t\toperands[%u].access: READ" % (c)) - elif i.access == CS_AC_WRITE: - print("\t\toperands[%u].access: WRITE" % (c)) - elif i.access == CS_AC_READ | CS_AC_WRITE: - print("\t\toperands[%u].access: READ | WRITE" % (c)) - - if i.shift.type != ARM_SFT_INVALID and i.shift.value: - if i.shift.type < ARM_SFT_ASR_REG: - # shift with constant value - print("\t\t\tShift: %u = %u" \ - % (i.shift.type, i.shift.value)) - else: - # shift with register - print("\t\t\tShift: %u = %s" \ - % (i.shift.type, insn.reg_name(i.shift.value))) - if i.vector_index != -1: - print("\t\t\toperands[%u].vector_index = %u" %(c, i.vector_index)) - if i.subtracted: - print("\t\t\toperands[%u].subtracted = True" %c) - - c += 1 - - if not insn.cc in [ARMCC_AL, ARMCC_UNDEF]: - print("\tCode condition: %u" % insn.cc) - if insn.vcc != ARMVCC_None: - print("\tVector code condition: %u" % insn.vcc) - if insn.update_flags: - print("\tUpdate-flags: True") - if insn.writeback: - if insn.post_index: - print("\tWrite-back: Post") - else: - print("\tWrite-back: Pre") - if insn.cps_mode: - print("\tCPSI-mode: %u" %(insn.cps_mode)) - if insn.cps_flag: - print("\tCPSI-flag: %u" %(insn.cps_flag)) - if insn.vector_data: - print("\tVector-data: %u" %(insn.vector_data)) - if insn.vector_size: - print("\tVector-size: %u" %(insn.vector_size)) - if insn.usermode: - print("\tUser-mode: True") - if insn.mem_barrier: - print("\tMemory-barrier: %u" %(insn.mem_barrier)) - if insn.pred_mask: - print("\tPredicate Mask: 0x%x" %(insn.pred_mask)) - - (regs_read, regs_write) = insn.regs_access() - - if len(regs_read) > 0: - print("\tRegisters read:", end="") - for r in regs_read: - print(" %s" %(insn.reg_name(r)), end="") - print("") - - if len(regs_write) > 0: - print("\tRegisters modified:", end="") - for r in regs_write: - print(" %s" %(insn.reg_name(r)), end="") - print("") - - -# ## Test class Cs -def test_class(): - - for (arch, mode, code, comment, syntax) in all_tests: - print("*" * 16) - print("Platform: %s" % comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - if syntax is not None: - md.syntax = syntax - md.detail = True - for insn in md.disasm(code, 0x80001000): - print_insn_detail(insn) - print () - print("0x%x:\n" % (insn.address + insn.size)) - except CsError as e: - print("ERROR: %s" % e) - - -if __name__ == '__main__': - test_class() diff --git a/bindings/python/tests/test_basic.py b/bindings/python/tests/test_basic.py deleted file mode 100755 index a114b1f0c5..0000000000 --- a/bindings/python/tests/test_basic.py +++ /dev/null @@ -1,144 +0,0 @@ -#!/usr/bin/env python3 -# Capstone Python bindings, by Nguyen Anh Quynnh - -from capstone import * - -from xprint import to_hex - - -X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" -X86_CODE32 = b"\xba\xcd\xab\x00\x00\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" -X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00" -ARM_CODE = b"\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3" -ARM_CODE2 = b"\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3" -THUMB_CODE = b"\x70\x47\xeb\x46\x83\xb0\xc9\x68" -THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0" -THUMB_MCLASS = b"\xef\xf3\x02\x80" -ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5" -MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56" -MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00" -MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0" -MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0" -AARCH64_CODE = b"\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9" -PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21" -PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f" -SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" -SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" -SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78" -XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10" -M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75" -TMS320C64X_CODE = b"\x01\xac\x88\x40\x81\xac\x88\x43\x00\x00\x00\x00\x02\x90\x32\x96\x02\x80\x46\x9e\x05\x3c\x83\xe6\x0b\x0c\x8b\x24" -M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39" -EVM_CODE = b"\x60\x61" -WASM_CODE = b"\x20\x00\x20\x01\x41\x20\x10\xc9\x01\x45\x0b" -MOS65XX_CODE = b"\x0d\x34\x12\x00\x81\x65\x6c\x01\x00\x85\xFF\x10\x00\x19\x42\x42\x00\x49\x42" -EBPF_CODE = b"\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00" -RISCV_CODE32 = b"\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xff\xe7\x00\x45\x00\xe7\x00\xc0\xff\x63\x05\x41\x00\xe3\x9d\x61\xfe\x63\xca\x93\x00\x63\x53\xb5\x00\x63\x65\xd6\x00\x63\x76\xf7\x00\x03\x88\x18\x00\x03\x99\x49\x00\x03\xaa\x6a\x00\x03\xcb\x2b\x01\x03\xdc\x8c\x01\x23\x86\xad\x03\x23\x9a\xce\x03\x23\x8f\xef\x01\x93\x00\xe0\x00\x13\xa1\x01\x01\x13\xb2\x02\x7d\x13\xc3\x03\xdd\x13\xe4\xc4\x12\x13\xf5\x85\x0c\x13\x96\xe6\x01\x13\xd7\x97\x01\x13\xd8\xf8\x40\x33\x89\x49\x01\xb3\x0a\x7b\x41\x33\xac\xac\x01\xb3\x3d\xde\x01\x33\xd2\x62\x40\xb3\x43\x94\x00\x33\xe5\xc5\x00\xb3\x76\xf7\x00\xb3\x54\x39\x01\xb3\x50\x31\x00\x33\x9f\x0f\x00" -RISCV_CODE64 = b"\x13\x04\xa8\x7a" -ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7' -ALPHA_CODE_BE = b'\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00' -HPPA_20_CODE_BE = b'\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad' -HPPA_20_CODE = b'\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14' -HPPA_11_CODE_BE = b'\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1' -HPPA_11_CODE = b'\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c' - - -all_tests = ( - (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None), - (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_SYNTAX_ATT), - (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None), - (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (MASM syntax)", CS_OPT_SYNTAX_MASM), - (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", None), - (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None), - (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", None), - (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", None), - (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", None), - (CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None), - (CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None), - (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", None), - (CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", None), - (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", None), - (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", None), - (CS_ARCH_AARCH64, CS_MODE_ARM, AARCH64_CODE, "AARCH64", None), - (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", None), - (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME), - (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", None), - (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", None), - (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", None), - (CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", None), - (CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None), - (CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K", None), - (CS_ARCH_TMS320C64X, 0, TMS320C64X_CODE, "TMS320C64x", None), - (CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None), - (CS_ARCH_EVM, 0, EVM_CODE, "EVM", None), - (CS_ARCH_WASM, 0, WASM_CODE, "WASM", None), - (CS_ARCH_MOS65XX, 0, MOS65XX_CODE, "MOS65XX", None), - (CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED, EBPF_CODE, "eBPF", None), - (CS_ARCH_RISCV, CS_MODE_RISCV32, RISCV_CODE32, "RISCV32", None), - (CS_ARCH_RISCV, CS_MODE_RISCV64, RISCV_CODE64, "RISCV64", None), - (CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN, ALPHA_CODE, "Alpha (Little-endian)", None), - (CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN, ALPHA_CODE_BE, "Alpha (Big-endian)", None), - (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE_BE, "HPPA 2.0 (Big-endian)", None), - (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE, "HPPA 2.0 (Little-endian)", None), - (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE_BE, "HPPA 1.1 (Big-endian)", None), - (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE, "HPPA 1.1 (Little-endian)", None), -) - -# ## Test cs_disasm_quick() -def test_cs_disasm_quick(): - for arch, mode, code, comment, syntax in all_tests: - print('*' * 40) - print("Platform: %s" % comment) - print("Disasm:") - print(to_hex(code)) - for insn in cs_disasm_quick(arch, mode, code, 0x1000): - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - print() - - -def test_different_data_formats(): - data = bytes.fromhex('4831C948F7E1043B48BB0A2F62696E2F2F736852530A545F5257545E0F05') - mnemonics = ['xor', 'mul', 'add', 'movabs', 'push', 'pop', 'push', 'push', 'push', 'pop', 'syscall'] - disassembler = Cs(CS_ARCH_X86, CS_MODE_64) - for name, code in ( - ('bytearray', bytearray(data)), - ('memoryview of bytearray', memoryview(bytearray(data))), - ('memoryview of data', memoryview(data)), - ('raw data', data) - ): - if mnemonics != [op for _, _, op, _ in disassembler.disasm_lite(code, 0)]: - print('failure in disassemble-lite for %s.' % name) - if mnemonics != [instruction.mnemonic for instruction in disassembler.disasm(code, 0)]: - print('failure in disassemble-full for %s.' % name) - - -# ## Test class Cs -def test_class(): - for arch, mode, code, comment, syntax in all_tests: - print('*' * 16) - print("Platform: %s" % comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - - if syntax is not None: - md.syntax = syntax - - for insn in md.disasm(code, 0x1000): - # bytes = binascii.hexlify(insn.bytes) - # print("0x%x:\t%s\t%s\t// hex-code: %s" %(insn.address, insn.mnemonic, insn.op_str, bytes)) - print("0x%x:\t%s\t\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - - print("0x%x:" % (insn.address + insn.size)) - print() - except CsError as e: - print("ERROR: %s" % e) - - -# test_cs_disasm_quick() -# print ("*" * 40) -if __name__ == '__main__': - test_class() - test_different_data_formats() diff --git a/bindings/python/tests/test_bpf.py b/bindings/python/tests/test_bpf.py deleted file mode 100755 index f7f5538a07..0000000000 --- a/bindings/python/tests/test_bpf.py +++ /dev/null @@ -1,91 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings -# BPF tests by david942j , 2019 - -from capstone import * -from capstone.bpf import * -from xprint import to_hex, to_x, to_x_32 - - -CBPF_CODE = b"\x94\x09\x00\x00\x37\x13\x03\x00\x87\x00\x00\x00\x00\x00\x00\x00\x07\x00\x00\x00\x00\x00\x00\x00\x16\x00\x00\x00\x00\x00\x00\x00\x80\x00\x00\x00\x00\x00\x00\x00" -EBPF_CODE = b"\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00" - -all_tests = ( - (CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC, CBPF_CODE, "cBPF Le", None), - (CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED, EBPF_CODE, "eBPF Le", None), - ) - -ext_name = {} -ext_name[BPF_EXT_LEN] = '#len' - -def print_insn_detail(insn): - # print address, mnemonic and operands - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - - if len(insn.groups) > 0: - print('\tGroups: ' + ' '.join(map(lambda g: insn.group_name(g), insn.groups))) - - print("\tOperand count: %u" % len(insn.operands)) - for c, op in enumerate(insn.operands): - print("\t\toperands[%u].type: " % c, end='') - if op.type == BPF_OP_REG: - print("REG = " + insn.reg_name(op.reg)) - elif op.type == BPF_OP_IMM: - print("IMM = 0x" + to_x(op.imm)) - elif op.type == BPF_OP_OFF: - print("OFF = +0x" + to_x_32(op.off)) - elif op.type == BPF_OP_MEM: - print("MEM") - if op.mem.base != 0: - print("\t\t\toperands[%u].mem.base: REG = %s" \ - % (c, insn.reg_name(op.mem.base))) - print("\t\t\toperands[%u].mem.disp: 0x%s" \ - % (c, to_x_32(op.mem.disp))) - elif op.type == BPF_OP_MMEM: - print("MMEM = 0x" + to_x_32(op.mmem)) - elif op.type == BPF_OP_MSH: - print("MSH = 4*([0x%s]&0xf)" % to_x_32(op.msh)) - elif op.type == BPF_OP_EXT: - print("EXT = " + ext_name[op.ext]) - - (regs_read, regs_write) = insn.regs_access() - - if len(regs_read) > 0: - print("\tRegisters read:", end="") - for r in regs_read: - print(" %s" % insn.reg_name(r), end="") - print("") - - if len(regs_write) > 0: - print("\tRegisters modified:", end="") - for r in regs_write: - print(" %s" % insn.reg_name(r), end="") - print("") - -def test_class(): - - for (arch, mode, code, comment, syntax) in all_tests: - print("*" * 16) - print("Platform: %s" % comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - if syntax is not None: - md.syntax = syntax - md.detail = True - for insn in md.disasm(code, 0x0): - print_insn_detail(insn) - print () - except CsError as e: - print("ERROR: %s" % e) - - -if __name__ == '__main__': - test_class() diff --git a/bindings/python/tests/test_detail.py b/bindings/python/tests/test_detail.py deleted file mode 100755 index 4f966109fd..0000000000 --- a/bindings/python/tests/test_detail.py +++ /dev/null @@ -1,126 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Nguyen Anh Quynnh -from capstone import * - -from xprint import to_hex - -X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" -X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" -X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00" -ARM_CODE = b"\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3" -ARM_CODE2 = b"\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3" -THUMB_CODE = b"\x70\x47\xeb\x46\x83\xb0\xc9\x68" -THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0" -THUMB_MCLASS = b"\xef\xf3\x02\x80" -ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5" -MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56\x00\x80\x04\x08" -MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00" -MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0" -MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0" -AARCH64_CODE = b"\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c" -PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14" -PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f" -SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" -SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" -SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78" -XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10" -M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75" -M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39" -MOS65XX_CODE = b"\x0A\x00\xFE\x34\x12\xD0\xFF\xEA\x19\x56\x34\x46\x80" -EBPF_CODE = b"\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00" -ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7' -ALPHA_CODE_BE = b'\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00' -HPPA_20_CODE_BE = b'\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad' -HPPA_20_CODE = b'\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14' -HPPA_11_CODE_BE = b'\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1' -HPPA_11_CODE = b'\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c' - -all_tests = ( - (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None), - (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_SYNTAX_ATT), - (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None), - (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", None), - (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None), - (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", None), - (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", None), - (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", None), - (CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None), - (CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None), - (CS_ARCH_AARCH64, CS_MODE_ARM, AARCH64_CODE, "AARCH64", None), - (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", None), - (CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", None), - (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", None), - (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", None), - (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", None), - (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", None), - (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", None), - (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", None), - (CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", None), - (CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None), - (CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K", None), - (CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None), - (CS_ARCH_MOS65XX, 0, MOS65XX_CODE, "MOS65XX", None), - (CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED, EBPF_CODE, "eBPF", None), - (CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN, ALPHA_CODE, "Alpha (Little-endian)", None), - (CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN, ALPHA_CODE_BE, "Alpha (Big-endian)", None), - (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE_BE, "HPPA 2.0 (Big-endian)", None), - (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE, "HPPA 2.0 (Little-endian)", None), - (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE_BE, "HPPA 1.1 (Big-endian)", None), - (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE, "HPPA 1.1 (Little-endian)", None), -) - - -def print_detail(insn): - print("0x%x:\t%s\t%s // insn-ID: %u, insn-mnem: %s" \ - % (insn.address, insn.mnemonic, insn.op_str, insn.id, \ - insn.insn_name())) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - - if len(insn.regs_read) > 0: - print("\tImplicit registers read: ", end='') - for m in insn.regs_read: - print("%s " % insn.reg_name(m), end='') - print() - - if len(insn.regs_write) > 0: - print("\tImplicit registers modified: ", end='') - for m in insn.regs_write: - print("%s " % insn.reg_name(m), end='') - print() - - if len(insn.groups) > 0: - print("\tThis instruction belongs to groups: ", end='') - for m in insn.groups: - print("%s " % insn.group_name(m), end='') - print() - - -# ## Test class Cs -def test_class(): - for (arch, mode, code, comment, syntax) in all_tests: - print('*' * 16) - print("Platform: %s" % comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - md.detail = True - - if syntax is not None: - md.syntax = syntax - - for insn in md.disasm(code, 0x1000): - print_detail(insn) - - print("0x%x:" % (insn.address + insn.size)) - print() - except CsError as e: - print("ERROR: %s" % e) - -if __name__ == '__main__': - test_class() diff --git a/bindings/python/tests/test_evm.py b/bindings/python/tests/test_evm.py deleted file mode 100755 index 3fd90fdfc5..0000000000 --- a/bindings/python/tests/test_evm.py +++ /dev/null @@ -1,48 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Nguyen Anh Quynnh - -from capstone import * - -from xprint import to_hex - - -EVM_CODE = b"\x60\x61\x50" - -all_tests = ( - (CS_ARCH_EVM, 0, EVM_CODE, "EVM"), -) - - -def test_class(): - address = 0x80001000 - for (arch, mode, code, comment) in all_tests: - print("*" * 16) - print("Platform: %s" % comment) - print("Code: %s " % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - md.detail = True - for i in md.disasm(code, address): - print("0x%x:\t%s\t%s" %(i.address, i.mnemonic, i.op_str)) - if i.pop > 0: - print("\tPop: %u" %i.pop) - if i.push > 0: - print("\tPush: %u" %i.push) - if i.fee > 0: - print("\tGas fee: %u" %i.fee) - if len(i.groups) > 0: - print("\tGroups: ", end=''), - for m in i.groups: - print("%s " % i.group_name(m), end=''), - print() - print ("0x%x:\n" % (i.address + i.size)) - - except CsError as e: - print("ERROR: %s" % e.__str__()) - - -if __name__ == '__main__': - test_class() diff --git a/bindings/python/tests/test_hppa.py b/bindings/python/tests/test_hppa.py deleted file mode 100755 index dfbe08fa3d..0000000000 --- a/bindings/python/tests/test_hppa.py +++ /dev/null @@ -1,74 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Dmitry Sibirtsev - -from capstone import * -from capstone.hppa import * -from xprint import to_x, to_hex - -HPPA_20_CODE_BE = b'\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad' -HPPA_20_CODE = b'\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14' -HPPA_11_CODE_BE = b'\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1' -HPPA_11_CODE = b'\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c' - -all_tests = ( - (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE_BE, "HPPA 2.0 (Big-endian)"), - (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE, "HPPA 2.0 (Little-endian)"), - (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE_BE, "HPPA 1.1 (Big-endian)"), - (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE, "HPPA 1.1 (Little-endian)"), -) - - -def print_insn_detail(insn): - # print address, mnemonic and operands - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - - if len(insn.operands) > 0: - print("\top_count: %u" % len(insn.operands)) - c = 0 - for i in insn.operands: - if i.type == HPPA_OP_REG: - print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) - if i.type == HPPA_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) - if i.type == HPPA_OP_IDX_REG: - print("\t\toperands[%u].type: IDX_REG = %s" % (c, insn.reg_name(i.reg))) - if i.type == HPPA_OP_DISP: - print("\t\toperands[%u].type: DISP = 0x%s" % (c, to_x(i.imm))) - if i.type == HPPA_OP_MEM: - print("\t\toperands[%u].type: MEM" % c) - if i.mem.space != HPPA_REG_INVALID: - print("\t\t\toperands[%u].mem.space: REG = %s" % (c, insn.reg_name(i.mem.space))) - print("\t\t\toperands[%u].mem.base: REG = %s" % (c, insn.reg_name(i.mem.base))) - if i.type == HPPA_OP_TARGET: - if i.imm >= 0x8000000000000000: - print("TARGET = -0x%lx" % i.imm) - else: - print("TARGET = 0x%lx" % i.imm) - c += 1 - -# ## Test class Cs -def test_class(): - for (arch, mode, code, comment) in all_tests: - print("*" * 16) - print("Platform: %s" % comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - md.detail = True - for insn in md.disasm(code, 0x1000): - print_insn_detail(insn) - print() - print("0x%x:\n" % (insn.address + insn.size)) - except CsError as e: - print("ERROR: %s" % e) - - -if __name__ == '__main__': - test_class() diff --git a/bindings/python/tests/test_m680x.py b/bindings/python/tests/test_m680x.py deleted file mode 100755 index 8512ff0ccb..0000000000 --- a/bindings/python/tests/test_m680x.py +++ /dev/null @@ -1,153 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Wolfgang Schwotzer - -from capstone import * -from capstone.m680x import * - - -s_access = ( - "UNCHANGED", "READ", "WRITE", "READ | WRITE", - ) - -M6800_CODE = b"\x01\x09\x36\x64\x7f\x74\x10\x00\x90\x10\xA4\x10\xb6\x10\x00\x39" - -M6801_CODE = b"\x04\x05\x3c\x3d\x38\x93\x10\xec\x10\xed\x10\x39" -M6805_CODE = b"\x04\x7f\x00\x17\x22\x28\x00\x2e\x00\x40\x42\x5a\x70\x8e\x97\x9c\xa0\x15\xad\x00\xc3\x10\x00\xda\x12\x34\xe5\x7f\xfe" -M6808_CODE = b"\x31\x22\x00\x35\x22\x45\x10\x00\x4b\x00\x51\x10\x52\x5e\x22\x62\x65\x12\x34\x72\x84\x85\x86\x87\x8a\x8b\x8c\x94\x95\xa7\x10\xaf\x10\x9e\x60\x7f\x9e\x6b\x7f\x00\x9e\xd6\x10\x00\x9e\xe6\x7f" -HCS08_CODE = b"\x32\x10\x00\x9e\xae\x9e\xce\x7f\x9e\xbe\x10\x00\x9e\xfe\x7f\x3e\x10\x00\x9e\xf3\x7f\x96\x10\x00\x9e\xff\x7f\x82" -HD6301_CODE = b"\x6b\x10\x00\x71\x10\x00\x72\x10\x10\x39" -M6809_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39\xA6\x07\xA6\x27\xA6\x47\xA6\x67\xA6\x0F\xA6\x10\xA6\x80\xA6\x81\xA6\x82\xA6\x83\xA6\x84\xA6\x85\xA6\x86\xA6\x88\x7F\xA6\x88\x80\xA6\x89\x7F\xFF\xA6\x89\x80\x00\xA6\x8B\xA6\x8C\x10\xA6\x8D\x10\x00\xA6\x91\xA6\x93\xA6\x94\xA6\x95\xA6\x96\xA6\x98\x7F\xA6\x98\x80\xA6\x99\x7F\xFF\xA6\x99\x80\x00\xA6\x9B\xA6\x9C\x10\xA6\x9D\x10\x00\xA6\x9F\x10\x00" -M6811_CODE = b"\x02\x03\x12\x7f\x10\x00\x13\x99\x08\x00\x14\x7f\x02\x15\x7f\x01\x1e\x7f\x20\x00\x8f\xcf\x18\x08\x18\x30\x18\x3c\x18\x67\x18\x8c\x10\x00\x18\x8f\x18\xce\x10\x00\x18\xff\x10\x00\x1a\xa3\x7f\x1a\xac\x1a\xee\x7f\x1a\xef\x7f\xcd\xac\x7f" -CPU12_CODE = b"\x00\x04\x01\x00\x0c\x00\x80\x0e\x00\x80\x00\x11\x1e\x10\x00\x80\x00\x3b\x4a\x10\x00\x04\x4b\x01\x04\x4f\x7f\x80\x00\x8f\x10\x00\xb7\x52\xb7\xb1\xa6\x67\xa6\xfe\xa6\xf7\x18\x02\xe2\x30\x39\xe2\x10\x00\x18\x0c\x30\x39\x10\x00\x18\x11\x18\x12\x10\x00\x18\x19\x00\x18\x1e\x00\x18\x3e\x18\x3f\x00" -HD6309_CODE = b"\x01\x10\x10\x62\x10\x10\x7b\x10\x10\x00\xcd\x49\x96\x02\xd2\x10\x30\x23\x10\x38\x10\x3b\x10\x53\x10\x5d\x11\x30\x43\x10\x11\x37\x25\x10\x11\x38\x12\x11\x39\x23\x11\x3b\x34\x11\x8e\x10\x00\x11\xaf\x10\x11\xab\x10\x11\xf6\x80\x00" - -all_tests = ( - (CS_ARCH_M680X, CS_MODE_M680X_6301, HD6301_CODE, "M680X_HD6301", None), - (CS_ARCH_M680X, CS_MODE_M680X_6309, HD6309_CODE, "M680X_HD6309", None), - (CS_ARCH_M680X, CS_MODE_M680X_6800, M6800_CODE, "M680X_M6800", None), - (CS_ARCH_M680X, CS_MODE_M680X_6801, M6801_CODE, "M680X_M6801", None), - (CS_ARCH_M680X, CS_MODE_M680X_6805, M6805_CODE, "M680X_M68HC05", None), - (CS_ARCH_M680X, CS_MODE_M680X_6808, M6808_CODE, "M680X_M68HC08", None), - (CS_ARCH_M680X, CS_MODE_M680X_6809, M6809_CODE, "M680X_M6809", None), - (CS_ARCH_M680X, CS_MODE_M680X_6811, M6811_CODE, "M680X_M68HC11", None), - (CS_ARCH_M680X, CS_MODE_M680X_CPU12, CPU12_CODE, "M680X_CPU12", None), - (CS_ARCH_M680X, CS_MODE_M680X_HCS08, HCS08_CODE, "M680X_HCS08", None), - ) - -# print hex dump from string all upper case -def to_hex_uc(string): - return " ".join("0x%02x" % c for c in string) - -# print short hex dump from byte array all upper case -def to_hex_short_uc(byte_array): - return "".join("%02x" % b for b in byte_array) - -def print_insn_detail(insn): - # print address, mnemonic and operands - #print("0x%x:\t%s\t%s\t%s" % (insn.address, binascii.hexlify(bytearray(insn.bytes)), \ - print("0x%04x: %s\t%s\t%s" % (insn.address, to_hex_short_uc(insn.bytes), \ - insn.mnemonic, insn.op_str)) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - - if len(insn.operands) > 0: - print("\top_count: %u" % len(insn.operands)) - c = 0 - for i in insn.operands: - if i.type == M680X_OP_REGISTER: - comment = ""; - if (((c == 0) and (insn.flags & M680X_FIRST_OP_IN_MNEM)) or - ((c == 1) and (insn.flags & M680X_SECOND_OP_IN_MNEM))): - comment = " (in mnemonic)"; - print("\t\toperands[%u].type: REGISTER = %s%s" % (c, - insn.reg_name(i.reg), comment)) - if i.type == M680X_OP_CONSTANT: - print("\t\toperands[%u].type: CONSTANT = %u" % (c, i.const_val)) - if i.type == M680X_OP_IMMEDIATE: - print("\t\toperands[%u].type: IMMEDIATE = #%d" % (c, i.imm)) - if i.type == M680X_OP_DIRECT: - print("\t\toperands[%u].type: DIRECT = 0x%02x" % (c, i.direct_addr)) - if i.type == M680X_OP_EXTENDED: - if i.ext.indirect: - indirect = "INDIRECT" - else: - indirect = "" - print("\t\toperands[%u].type: EXTENDED %s = 0x%04x" % (c, indirect, i.ext.address)) - if i.type == M680X_OP_RELATIVE: - print("\t\toperands[%u].type: RELATIVE = 0x%04x" % (c, i.rel.address)) - if i.type == M680X_OP_INDEXED: - if (i.idx.flags & M680X_IDX_INDIRECT): - indirect = " INDIRECT" - else: - indirect = "" - print("\t\toperands[%u].type: INDEXED%s" % (c, indirect)) - if i.idx.base_reg != M680X_REG_INVALID: - print("\t\t\tbase register: %s" % insn.reg_name(i.idx.base_reg)) - if i.idx.offset_reg != M680X_REG_INVALID: - print("\t\t\toffset register: %s" % insn.reg_name(i.idx.offset_reg)) - if (i.idx.offset_bits != 0) and (i.idx.offset_reg == M680X_REG_INVALID) and (i.idx.inc_dec == 0): - print("\t\t\toffset: %u" % i.idx.offset) - if i.idx.base_reg == M680X_REG_PC: - print("\t\t\toffset address: 0x%04x" % i.idx.offset_addr) - print("\t\t\toffset bits: %u" % i.idx.offset_bits) - if i.idx.inc_dec != 0: - if i.idx.flags & M680X_IDX_POST_INC_DEC: - s_post_pre = "post" - else: - s_post_pre = "pre" - if i.idx.inc_dec > 0: - s_inc_dec = "increment" - else: - s_inc_dec = "decrement" - print("\t\t\t%s %s: %d" % - (s_post_pre, s_inc_dec, abs(i.idx.inc_dec))) - if (i.size != 0): - print("\t\t\tsize: %d" % i.size) - if (i.access != CS_AC_INVALID): - print("\t\t\taccess: %s" % s_access[i.access]) - - c += 1 - - (regs_read, regs_write) = insn.regs_access() - - if len(regs_read) > 0: - print("\tRegisters read:", end="") - for r in regs_read: - print(" %s" %(insn.reg_name(r)), end="") - print("") - - if len(regs_write) > 0: - print("\tRegisters modified:", end="") - for r in regs_write: - print(" %s" %(insn.reg_name(r)), end="") - print("") - - if len(insn.groups) > 0: - print("\tgroups_count: %u" % len(insn.groups)) - -# ## Test class Cs -def test_class(): - - for (arch, mode, code, comment, syntax) in all_tests: - print("*" * 20) - print("Platform: %s" % comment) - print("Code: %s" % to_hex_uc(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - if syntax is not None: - md.syntax = syntax - md.detail = True - for insn in md.disasm(code, 0x1000): - print_insn_detail(insn) - print () - except CsError as e: - print("ERROR: %s" % e) - - -if __name__ == '__main__': - test_class() diff --git a/bindings/python/tests/test_m68k.py b/bindings/python/tests/test_m68k.py deleted file mode 100755 index 6efdfaedbd..0000000000 --- a/bindings/python/tests/test_m68k.py +++ /dev/null @@ -1,123 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Nicolas PLANEL -from capstone import * -from capstone.m68k import * -from xprint import to_hex - -M68K_CODE = b"\xf0\x10\xf0\x00\x48\xaf\xff\xff\x7f\xff\x11\xb0\x01\x37\x7f\xff\xff\xff\x12\x34\x56\x78\x01\x33\x10\x10\x10\x10\x32\x32\x32\x32\x4C\x00\x54\x04\x48\xe7\xe0\x30\x4C\xDF\x0C\x07\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75" - -all_tests = ( - (CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K"), -) - -s_addressing_modes = { - 0: "", - - 1: "Register Direct - Data", - 2: "Register Direct - Address", - - 3: "Register Indirect - Address", - 4: "Register Indirect - Address with Postincrement", - 5: "Register Indirect - Address with Predecrement", - 6: "Register Indirect - Address with Displacement", - - 7: "Address Register Indirect With Index - 8-bit displacement", - 8: "Address Register Indirect With Index - Base displacement", - - 9: "Memory indirect - Postindex", - 10: "Memory indirect - Preindex", - - 11: "Program Counter Indirect - with Displacement", - - 12: "Program Counter Indirect with Index - with 8-Bit Displacement", - 13: "Program Counter Indirect with Index - with Base Displacement", - - 14: "Program Counter Memory Indirect - Postindexed", - 15: "Program Counter Memory Indirect - Preindexed", - - 16: "Absolute Data Addressing - Short", - 17: "Absolute Data Addressing - Long", - 18: "Immediate value", - - 19: "Branch Displacement", -} - -def print_read_write_regs(insn): - for m in insn.regs_read: - print("\treading from reg: %s" % insn.reg_name(m)) - - for m in insn.regs_write: - print("\twriting to reg: %s" % insn.reg_name(m)) - -def print_insn_detail(insn): - if len(insn.operands) > 0: - print("\top_count: %u" % (len(insn.operands))) - - print_read_write_regs(insn) - print("\tgroups_count: %u" % len(insn.groups)) - - for i, op in enumerate(insn.operands): - if op.type == M68K_OP_REG: - print("\t\toperands[%u].type: REG = %s" % (i, insn.reg_name(op.reg))) - elif op.type == M68K_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%x" % (i, op.imm & 0xffffffff)) - elif op.type == M68K_OP_MEM: - print("\t\toperands[%u].type: MEM" % (i)) - if op.mem.base_reg != M68K_REG_INVALID: - print("\t\t\toperands[%u].mem.base: REG = %s" % (i, insn.reg_name(op.mem.base_reg))) - if op.mem.index_reg != M68K_REG_INVALID: - print("\t\t\toperands[%u].mem.index: REG = %s" % (i, insn.reg_name(op.mem.index_reg))) - mem_index_str = "w" - if op.mem.index_size > 0: - mem_index_str = "l" - print("\t\t\toperands[%u].mem.index: size = %s" % (i, mem_index_str)) - if op.mem.disp != 0: - print("\t\t\toperands[%u].mem.disp: 0x%x" % (i, op.mem.disp)) - if op.mem.scale != 0: - print("\t\t\toperands[%u].mem.scale: %d" % (i, op.mem.scale)) - print("\t\taddress mode: %s" % (s_addressing_modes[op.address_mode])) - elif op.type == M68K_OP_FP_SINGLE: - print("\t\toperands[%u].type: FP_SINGLE" % i) - print("\t\toperands[%u].simm: %f" % (i, op.simm)) - elif op.type == M68K_OP_FP_DOUBLE: - print("\t\toperands[%u].type: FP_DOUBLE" % i) - print("\t\toperands[%u].dimm: %lf" % (i, op.dimm)) - elif op.type == M68K_OP_REG_BITS: - print("\t\toperands[%u].type: REG_BITS = $%x" % (i, op.register_bits)) - elif op.type == M68K_OP_REG_PAIR: - print("\t\toperands[%u].type: REG_PAIR = (%s, %s)" % (i, insn.reg_name(op.reg_pair.reg_0), insn.reg_name(op.reg_pair.reg_1))) - elif op.type == M68K_OP_BR_DISP: - print("\t\toperands[%u].br_disp.disp: 0x%x" % (i, op.br_disp.disp)) - print("\t\toperands[%u].br_disp.disp_size: %d" % (i, op.br_disp.disp_size)) - print() - -# ## Test class Cs -def test_class(): - address = 0x01000 - for (arch, mode, code, comment) in all_tests: - print("*" * 16) - print("Platform: %s" % comment) - print("Code: %s " % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - md.detail = True - last_address = 0 - for insn in md.disasm(code, address): - last_address = insn.address + insn.size - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - print_insn_detail(insn) - print("0x%x:\n" % (last_address)) - - except CsError as e: - print("ERROR: %s" % e.__str__()) - -if __name__ == '__main__': - test_class() - - - - - diff --git a/bindings/python/tests/test_mips.py b/bindings/python/tests/test_mips.py deleted file mode 100755 index b6a2502995..0000000000 --- a/bindings/python/tests/test_mips.py +++ /dev/null @@ -1,73 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Nguyen Anh Quynnh -from capstone import * -from capstone.mips import * -from xprint import to_hex, to_x - - -MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56" -MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00" -MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0" -MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0" -MIPS_64SD = b"\x70\x00\xb2\xff" - -all_tests = ( - (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)"), - (CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)"), - (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)"), - (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)"), - (CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_MIPS2 | CS_MODE_LITTLE_ENDIAN, MIPS_64SD, "MIPS-64-EL + Mips II (Little-endian)"), - (CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN, MIPS_64SD, "MIPS-64-EL (Little-endian)"), -) - - -def print_insn_detail(insn): - # print address, mnemonic and operands - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - - if len(insn.operands) > 0: - print("\top_count: %u" % len(insn.operands)) - c = -1 - for i in insn.operands: - c += 1 - if i.type == MIPS_OP_REG: - print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) - if i.type == MIPS_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) - if i.type == MIPS_OP_MEM: - print("\t\toperands[%u].type: MEM" % c) - if i.mem.base != 0: - print("\t\t\toperands[%u].mem.base: REG = %s" \ - % (c, insn.reg_name(i.mem.base))) - if i.mem.disp != 0: - print("\t\t\toperands[%u].mem.disp: 0x%s" \ - % (c, to_x(i.mem.disp))) - - -# ## Test class Cs -def test_class(): - for (arch, mode, code, comment) in all_tests: - print("*" * 16) - print("Platform: %s" % comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - md.detail = True - for insn in md.disasm(code, 0x1000): - print_insn_detail(insn) - print() - - print("0x%x:\n" % (insn.address + insn.size)) - except CsError as e: - print("ERROR: %s" % e) - - -if __name__ == '__main__': - test_class() diff --git a/bindings/python/tests/test_mos65xx.py b/bindings/python/tests/test_mos65xx.py deleted file mode 100755 index ae5db53c54..0000000000 --- a/bindings/python/tests/test_mos65xx.py +++ /dev/null @@ -1,94 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Sebastian Macke -from capstone import * -from capstone.mos65xx import * -from xprint import to_hex, to_x - -M6502_CODE = b"\xa1\x12\xa5\x12\xa9\x12\xad\x34\x12\xb1\x12\xb5\x12\xb9\x34\x12\xbd\x34\x12\x0d\x34\x12\x00\x81\x87\x6c\x01\x00\x85\xFF\x10\x00\x19\x42\x42\x00\x49\x42" -M65C02_CODE = b"\x1a\x3a\x02\x12\x03\x5c\x34\x12" -MW65C02_CODE = b"\x07\x12\x27\x12\x47\x12\x67\x12\x87\x12\xa7\x12\xc7\x12\xe7\x12\x10\xfe\x0f\x12\xfd\x4f\x12\xfd\x8f\x12\xfd\xcf\x12\xfd" -M65816_CODE = b"\xa9\x34\x12\xad\x34\x12\xbd\x34\x12\xb9\x34\x12\xaf\x56\x34\x12\xbf\x56\x34\x12\xa5\x12\xb5\x12\xb2\x12\xa1\x12\xb1\x12\xa7\x12\xb7\x12\xa3\x12\xb3\x12\xc2\x00\xe2\x00\x54\x34\x12\x44\x34\x12\x02\x12" - -all_tests = ( - (CS_ARCH_MOS65XX, CS_MODE_MOS65XX_6502, M6502_CODE, "MOS65XX_6502"), - (CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65C02, M65C02_CODE, "MOS65XX_65C02"), - (CS_ARCH_MOS65XX, CS_MODE_MOS65XX_W65C02, MW65C02_CODE, "MOS65XX_W65C02"), - (CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65816_LONG_MX, M65816_CODE, "MOS65XX_65816 (long m/x)"), -) - -address_modes=[ - "No address mode", - "implied", - "accumulator", - "immediate value", - "relative", - "interrupt signature", - "block move", - "zero page", - "zero page indexed with x", - "zero page indexed with y", - "relative bit branch", - "zero page indirect", - "zero page indexed with x indirect", - "zero page indirect indexed with y", - "zero page indirect long", - "zero page indirect long indexed with y", - "absolute", - "absolute indexed with x", - "absolute indexed with y", - "absolute indirect", - "absolute indexed with x indirect", - "absolute indirect long", - "absolute long", - "absolute long indexed with x", - "stack relative", - "stack relative indirect indexed with y", -] - - -def print_insn_detail(insn): - # print address, mnemonic and operands - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - print("\taddress mode: %s" % (address_modes[insn.am])) - print("\tmodifies flags: %s" % ('true' if insn.modifies_flags != 0 else 'false')) - if len(insn.operands) > 0: - print("\top_count: %u" % len(insn.operands)) - c = -1 - for i in insn.operands: - c += 1 - if i.type == MOS65XX_OP_REG: - print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) - if i.type == MOS65XX_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) - if i.type == MOS65XX_OP_MEM: - print("\t\toperands[%u].type: MEM = 0x%s" % (c, to_x(i.mem))) - - -# ## Test class Cs -def test_class(): - for (arch, mode, code, comment) in all_tests: - print("*" * 16) - print("Platform: %s" % comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - md.detail = True - md.syntax = CS_OPT_SYNTAX_MOTOROLA - for insn in md.disasm(code, 0x1000): - print_insn_detail(insn) - print() - - print("0x%x:\n" % (insn.address + insn.size)) - except CsError as e: - print("ERROR: %s" % e) - - -if __name__ == '__main__': - test_class() diff --git a/bindings/python/tests/test_ppc.py b/bindings/python/tests/test_ppc.py deleted file mode 100755 index 9f2b493865..0000000000 --- a/bindings/python/tests/test_ppc.py +++ /dev/null @@ -1,93 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Nguyen Anh Quynnh -from capstone import * -from capstone.ppc import * -from xprint import to_hex, to_x, to_x_32 - -PPC_CODE = b"\x43\x20\x0c\x07\x41\x56\xff\x17\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14" -PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f" -PPC_CODE3 = b"\x10\x00\x1f\xec\xe0\x6d\x80\x04\xe4\x6d\x80\x04\x10\x60\x1c\x4c\x10\x60\x1c\x0c\xf0\x6d\x80\x04\xf4\x6d\x80\x04\x10\x60\x1c\x4e\x10\x60\x1c\x0e\x10\x60\x1a\x10\x10\x60\x1a\x11\x10\x63\x20\x2a\x10\x63\x20\x2b\x10\x83\x20\x40\x10\x83\x20\xC0\x10\x83\x20\x00\x10\x83\x20\x80\x10\x63\x20\x24\x10\x63\x20\x25\x10\x63\x29\x3a\x10\x63\x29\x3b\x10\x63\x29\x1c\x10\x63\x29\x1d\x10\x63\x29\x1e\x10\x63\x29\x1f\x10\x63\x24\x20\x10\x63\x24\x21\x10\x63\x24\x60\x10\x63\x24\x61\x10\x63\x24\xA0\x10\x63\x24\xA1\x10\x63\x24\xE0\x10\x63\x24\xE1\x10\x60\x20\x90\x10\x60\x20\x91\x10\x63\x29\x38\x10\x63\x29\x39\x10\x63\x01\x32\x10\x63\x01\x33\x10\x63\x01\x18\x10\x63\x01\x19\x10\x63\x01\x1A\x10\x63\x01\x1B\x10\x60\x19\x10\x10\x60\x19\x11\x10\x60\x18\x50\x10\x60\x18\x51\x10\x63\x29\x3e\x10\x63\x29\x3f\x10\x63\x29\x3c\x10\x63\x29\x3d\x10\x60\x18\x30\x10\x60\x18\x31\x10\x60\x18\x34\x10\x60\x18\x35\x10\x63\x29\x2e\x10\x63\x29\x2f\x10\x63\x20\x28\x10\x63\x20\x29\x10\x63\x29\x14\x10\x63\x29\x15\x10\x63\x29\x16\x10\x63\x29\x17" - -all_tests = ( - (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64"), - (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX"), - (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_32 + CS_MODE_PS, PPC_CODE3, "PPC + PS"), - ) - - -def print_insn_detail(insn): - # print address, mnemonic and operands - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - - if len(insn.operands) > 0: - print("\top_count: %u" % len(insn.operands)) - c = 0 - for i in insn.operands: - if i.type == PPC_OP_REG: - print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) - if i.type == PPC_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) - if i.type == PPC_OP_MEM: - print("\t\toperands[%u].type: MEM" % c) - if i.mem.base != PPC_REG_INVALID: - print("\t\t\toperands[%u].mem.base: REG = %s" \ - % (c, insn.reg_name(i.mem.base))) - if i.mem.offset != 0: - print("\t\t\toperands[%u].mem.offset: REG = %s" \ - % (c, insn.reg_name(i.mem.offset))) - if i.mem.disp != 0: - print("\t\t\toperands[%u].mem.disp: 0x%s" \ - % (c, to_x_32(i.mem.disp))) - if i.access == CS_AC_READ: - print("\t\toperands[%u].access: READ" % (c)) - elif i.access == CS_AC_WRITE: - print("\t\toperands[%u].access: WRITE" % (c)) - elif i.access == CS_AC_READ | CS_AC_WRITE: - print("\t\toperands[%u].access: READ | WRITE" % (c)) - c += 1 - if insn.bc.pred_cr != PPC_PRED_INVALID or \ - insn.bc.pred_ctr != PPC_PRED_INVALID: - print("\tBranch:") - print("\t\tbi: %u" % insn.bc.bi) - print("\t\tbo: %u" % insn.bc.bo) - if insn.bc.bh != PPC_BH_INVALID: - print("\t\tbh: %u" %insn.bc.bh) - if insn.bc.pred_cr != PPC_PRED_INVALID: - print("\t\tcrX: %s" % insn.reg_name(insn.bc.crX)) - print("\t\tpred CR-bit: %u" % insn.bc.pred_cr) - if insn.bc.pred_ctr != PPC_PRED_INVALID: - print("\t\tpred CTR: %u" % insn.bc.pred_ctr) - if insn.bc.hint != PPC_BR_NOT_GIVEN: - print("\t\thint: %u" % insn.bc.hint) - - if insn.update_cr0: - print("\tUpdate-CR0: True") - - -# ## Test class Cs -def test_class(): - - for (arch, mode, code, comment) in all_tests: - print("*" * 16) - print("Platform: %s" % comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - md.detail = True - for insn in md.disasm(code, 0x1000): - print_insn_detail(insn) - print () - print("0x%x:\n" % (insn.address + insn.size)) - except CsError as e: - print("ERROR: %s" % e) - - -if __name__ == '__main__': - test_class() diff --git a/bindings/python/tests/test_riscv.py b/bindings/python/tests/test_riscv.py deleted file mode 100755 index 396ef92285..0000000000 --- a/bindings/python/tests/test_riscv.py +++ /dev/null @@ -1,79 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Nguyen Anh Quynnh - -from capstone import * -from capstone.riscv import * -from xprint import to_x, to_hex - -RISCV_CODE32 = b"\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xff\xe7\x00\x45\x00\xe7\x00\xc0\xff\x63\x05\x41\x00\xe3\x9d\x61\xfe\x63\xca\x93\x00\x63\x53\xb5\x00\x63\x65\xd6\x00\x63\x76\xf7\x00\x03\x88\x18\x00\x03\x99\x49\x00\x03\xaa\x6a\x00\x03\xcb\x2b\x01\x03\xdc\x8c\x01\x23\x86\xad\x03\x23\x9a\xce\x03\x23\x8f\xef\x01\x93\x00\xe0\x00\x13\xa1\x01\x01\x13\xb2\x02\x7d\x13\xc3\x03\xdd\x13\xe4\xc4\x12\x13\xf5\x85\x0c\x13\x96\xe6\x01\x13\xd7\x97\x01\x13\xd8\xf8\x40\x33\x89\x49\x01\xb3\x0a\x7b\x41\x33\xac\xac\x01\xb3\x3d\xde\x01\x33\xd2\x62\x40\xb3\x43\x94\x00\x33\xe5\xc5\x00\xb3\x76\xf7\x00\xb3\x54\x39\x01\xb3\x50\x31\x00\x33\x9f\x0f\x00\x73\x15\x04\xb0\xf3\x56\x00\x10\x33\x05\x7b\x03\xb3\x45\x9c\x03\x33\x66\xbd\x03\x2f\xa4\x02\x10\xaf\x23\x65\x18\x2f\x27\x2f\x01\x43\xf0\x20\x18\xd3\x72\x73\x00\x53\xf4\x04\x58\x53\x85\xc5\x28\x53\x2e\xde\xa1\xd3\x84\x05\xf0\x53\x06\x05\xe0\x53\x75\x00\xc0\xd3\xf0\x05\xd0\xd3\x15\x08\xe0\x87\xaa\x75\x00\x27\x27\x66\x01\x43\xf0\x20\x1a\xd3\x72\x73\x02\x53\xf4\x04\x5a\x53\x85\xc5\x2a\x53\x2e\xde\xa3" -RISCV_CODE64 = b"\x13\x04\xa8\x7a\xbb\x07\x9c\x02\xbb\x40\x5d\x02\x3b\x63\xb7\x03\x2f\xb4\x02\x10\xaf\x33\x65\x18\x2f\x37\x2f\x01\x53\x75\x20\xc0\xd3\xf0\x25\xd0\xd3\x84\x05\xf2\x53\x06\x05\xe2\x53\x75\x00\xc2\xd3\x80\x05\xd2\xd3\x15\x08\xe2\x87\xba\x75\x00\x27\x37\x66\x01" -RISCV_CODEC = b"\xe8\x1f\x7d\x61\x80\x25\x00\x46\x88\xa2\x04\xcb\x55\x13\xf2\x93\x5d\x45\x19\x80\x15\x68\x2a\xa4\x62\x24\xa6\xff\x2a\x65\x76\x86\x65\xdd\x01\x00\xfd\xaf\x82\x82\x11\x20\x82\x94" - -all_tests = ( - (CS_ARCH_RISCV, CS_MODE_RISCV32, RISCV_CODE32, "riscv32"), - (CS_ARCH_RISCV, CS_MODE_RISCV64, RISCV_CODE64, "riscv64"), - (CS_ARCH_RISCV, CS_MODE_RISCVC, RISCV_CODEC, "riscvc"), -) - - -def print_insn_detail(insn): - # print address, mnemonic and operands - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - - if len(insn.operands) > 0: - print("\top_count: %u" % len(insn.operands)) - c = 0 - for i in insn.operands: - if i.type == RISCV_OP_REG: - print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) - if i.type == RISCV_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) - if i.type == RISCV_OP_MEM: - print("\t\toperands[%u].type: MEM" % c) - if i.mem.base != 0: - print("\t\t\toperands[%u].mem.base: REG = %s" \ - % (c, insn.reg_name(i.mem.base))) - if i.mem.disp != 0: - print("\t\t\toperands[%u].mem.disp: 0x%s" \ - % (c, to_x(i.mem.disp))) - - if i.access == CS_AC_READ: - print("\t\toperands[%u].access: READ" % (c)) - elif i.access == CS_AC_WRITE: - print("\t\toperands[%u].access: WRITE" % (c)) - elif i.access == CS_AC_READ | CS_AC_WRITE: - print("\t\toperands[%u].access: READ | WRITE" % (c)) - - c += 1 - - if len(insn.groups) > 0: - print('\tgroups: ' + ' '.join(map(lambda g: insn.group_name(g), insn.groups))) - - -# ## Test class Cs -def test_class(): - - for (arch, mode, code, comment) in all_tests: - print("*" * 16) - print("Platform: %s" %comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - md.detail = True - for insn in md.disasm(code, 0x1000): - print_insn_detail(insn) - print () - print("0x%x:\n" % (insn.address + insn.size)) - except CsError as e: - print("ERROR: %s" %e) - - -if __name__ == '__main__': - test_class() diff --git a/bindings/python/tests/test_sh.py b/bindings/python/tests/test_sh.py deleted file mode 100755 index e5c2f3514e..0000000000 --- a/bindings/python/tests/test_sh.py +++ /dev/null @@ -1,96 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Peace-Maker - -from capstone import * -from capstone.sh import * -from xprint import to_x, to_hex - -SH4A_CODE = b"\x0c\x31\x10\x20\x22\x21\x36\x64\x46\x25\x12\x12\x1c\x02\x08\xc1\x05\xc7\x0c\x71\x1f\x02\x22\xcf\x06\x89\x23\x00\x2b\x41\x0b\x00\x0e\x40\x32\x00\x0a\xf1\x09\x00" -SH2A_CODE = b"\x32\x11\x92\x00\x32\x49\x31\x00" -all_tests = ( - (CS_ARCH_SH, CS_MODE_SH4A | CS_MODE_SHFPU, SH4A_CODE, "SH_SH4A"), - (CS_ARCH_SH, CS_MODE_SH2A | CS_MODE_SHFPU | CS_MODE_BIG_ENDIAN, SH2A_CODE, "SH_SH2A"), -) - - -reg_address_msg = [ - "Register indirect", - "Register indirect with predecrement", - "Register indirect with postincrement", -] - -def print_read_write_regs(insn): - if len(insn.regs_read) > 0: - print("\tRegisters read: %s" % " ".join(insn.reg_name(m) for m in insn.regs_read)) - - if len(insn.regs_write) > 0: - print("\tRegisters modified: %s" % " ".join(insn.reg_name(m) for m in insn.regs_write)) - -def print_insn_detail(insn): - # print address, mnemonic and operands - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - - if len(insn.operands) > 0: - print("\top_count: %u" % len(insn.operands)) - c = 0 - for i in insn.operands: - if i.type == SH_OP_REG: - print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) - elif i.type == SH_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) - elif i.type == SH_OP_MEM: - print("\t\toperands[%u].type: MEM " % c) - if i.mem.address in [SH_OP_MEM_REG_IND, SH_OP_MEM_REG_POST, SH_OP_MEM_REG_PRE]: - print("%s REG %s" % (reg_address_msg[i.mem.address - SH_OP_MEM_REG_IND], insn.reg_name(i.mem.reg))) - elif i.mem.address == SH_OP_MEM_REG_DISP: - print("Register indirect with displacement REG %s, DISP %d" % (insn.reg_name(i.mem.reg), i.mem.disp)) - elif i.mem.address == SH_OP_MEM_REG_R0: - print("R0 indexed") - elif i.mem.address == SH_OP_MEM_GBR_DISP: - print("GBR base with displacement DISP %d" % i.mem.disp) - elif i.mem.address == SH_OP_MEM_GBR_R0: - print("GBR base with R0 indexed") - elif i.mem.address == SH_OP_MEM_PCR: - print("PC relative Address=0x%08x" % i.mem.disp) - elif i.mem.address == SH_OP_MEM_TBR_DISP: - print("TBR base with displacement DISP %d", i.mem.disp) - else: - print("Unknown addressing mode %x" % i.mem.address) - - if i.sh_size != 0: - print("\t\t\tsh_size: %u" % i.sh_size) - c += 1 - - print_read_write_regs(insn) - - if len(insn.groups) > 0: - print('\tgroups: ' + ' '.join(map(lambda g: insn.group_name(g), insn.groups))) - - -# ## Test class Cs -def test_class(): - - for (arch, mode, code, comment) in all_tests: - print("*" * 16) - print("Platform: %s" %comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - md.detail = True - for insn in md.disasm(code, 0x80000000): - print_insn_detail(insn) - print() - print("0x%x:" % (insn.address + insn.size)) - except CsError as e: - print("ERROR: %s" %e) - - -if __name__ == '__main__': - test_class() diff --git a/bindings/python/tests/test_sparc.py b/bindings/python/tests/test_sparc.py deleted file mode 100755 index e1b1344ab3..0000000000 --- a/bindings/python/tests/test_sparc.py +++ /dev/null @@ -1,74 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Nguyen Anh Quynnh - -from capstone import * -from capstone.sparc import * -from xprint import to_hex, to_x_32 - - -SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" -SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" - -all_tests = ( - (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc"), - (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN+CS_MODE_V9, SPARCV9_CODE, "SparcV9"), -) - - -def print_insn_detail(insn): - # print address, mnemonic and operands - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - - if len(insn.operands) > 0: - print("\top_count: %u" % len(insn.operands)) - c = 0 - for i in insn.operands: - if i.type == SPARC_OP_REG: - print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) - if i.type == SPARC_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm))) - if i.type == SPARC_OP_MEM: - print("\t\toperands[%u].type: MEM" % c) - if i.mem.base != 0: - print("\t\t\toperands[%u].mem.base: REG = %s" \ - % (c, insn.reg_name(i.mem.base))) - if i.mem.index != 0: - print("\t\t\toperands[%u].mem.index: REG = %s" \ - % (c, insn.reg_name(i.mem.index))) - if i.mem.disp != 0: - print("\t\t\toperands[%u].mem.disp: 0x%s" \ - % (c, to_x_32(i.mem.disp))) - c += 1 - - if insn.cc: - print("\tCode condition: %u" % insn.cc) - if insn.hint: - print("\tHint code: %u" % insn.hint) - - -# ## Test class Cs -def test_class(): - for (arch, mode, code, comment) in all_tests: - print("*" * 16) - print("Platform: %s" % comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - md.detail = True - for insn in md.disasm(code, 0x1000): - print_insn_detail(insn) - print () - print("0x%x:\n" % (insn.address + insn.size)) - except CsError as e: - print("ERROR: %s" %e) - - -if __name__ == '__main__': - test_class() diff --git a/bindings/python/tests/test_systemz.py b/bindings/python/tests/test_systemz.py deleted file mode 100755 index a628494fd8..0000000000 --- a/bindings/python/tests/test_systemz.py +++ /dev/null @@ -1,76 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Nguyen Anh Quynnh - -from capstone import * -from capstone.systemz import * -from xprint import to_x, to_hex - - -SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78\xec\x18\x00\x00\xc1\x7f" - -all_tests = ( - (CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ"), -) - - -def print_insn_detail(insn): - # print address, mnemonic and operands - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - - if len(insn.operands) > 0: - print("\top_count: %u" % len(insn.operands)) - c = 0 - for i in insn.operands: - if i.type == SYSZ_OP_REG: - print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) - if i.type == SYSZ_OP_ACREG: - print("\t\toperands[%u].type: ACREG = %u" % (c, i.reg)) - if i.type == SYSZ_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) - if i.type == SYSZ_OP_MEM: - print("\t\toperands[%u].type: MEM" % c) - if i.mem.base != 0: - print("\t\t\toperands[%u].mem.base: REG = %s" \ - % (c, insn.reg_name(i.mem.base))) - if i.mem.index != 0: - print("\t\t\toperands[%u].mem.index: REG = %s" \ - % (c, insn.reg_name(i.mem.index))) - if i.mem.length != 0: - print("\t\t\toperands[%u].mem.length: 0x%s" \ - % (c, to_x(i.mem.length))) - if i.mem.disp != 0: - print("\t\t\toperands[%u].mem.disp: 0x%s" \ - % (c, to_x(i.mem.disp))) - c += 1 - - if insn.cc: - print("\tConditional code: %u" % insn.cc) - - -# ## Test class Cs -def test_class(): - - for (arch, mode, code, comment) in all_tests: - print("*" * 16) - print("Platform: %s" %comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - md.detail = True - for insn in md.disasm(code, 0x1000): - print_insn_detail(insn) - print () - print("0x%x:\n" % (insn.address + insn.size)) - except CsError as e: - print("ERROR: %s" %e) - - -if __name__ == '__main__': - test_class() diff --git a/bindings/python/tests/test_tms320c64x.py b/bindings/python/tests/test_tms320c64x.py deleted file mode 100755 index 1bb64b0c11..0000000000 --- a/bindings/python/tests/test_tms320c64x.py +++ /dev/null @@ -1,113 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Fotis Loukos - -from capstone import * -from capstone.tms320c64x import * -from xprint import to_x, to_hex, to_x_32 - - -TMS320C64X_CODE = b"\x01\xac\x88\x40\x81\xac\x88\x43\x00\x00\x00\x00\x02\x90\x32\x96\x02\x80\x46\x9e\x05\x3c\x83\xe6\x0b\x0c\x8b\x24" - -all_tests = ( - (CS_ARCH_TMS320C64X, 0, TMS320C64X_CODE, "TMS320C64x"), -) - - -def print_insn_detail(insn): - # print address, mnemonic and operands - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - - if len(insn.operands) > 0: - print("\top_count: %u" % len(insn.operands)) - c = 0 - for i in insn.operands: - if i.type == TMS320C64X_OP_REG: - print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) - if i.type == TMS320C64X_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) - if i.type == TMS320C64X_OP_MEM: - print("\t\toperands[%u].type: MEM" % c) - if i.mem.base != 0: - print("\t\t\toperands[%u].mem.base: REG = %s" \ - % (c, insn.reg_name(i.mem.base))) - if i.mem.disptype == TMS320C64X_MEM_DISP_INVALID: - print("\t\t\toperands[%u].mem.disptype: Invalid" % (c)) - print("\t\t\toperands[%u].mem.disp: 0x%s" \ - % (c, to_x(i.mem.disp))) - if i.mem.disptype == TMS320C64X_MEM_DISP_CONSTANT: - print("\t\t\toperands[%u].mem.disptype: Constant" % (c)) - print("\t\t\toperands[%u].mem.disp: 0x%s" \ - % (c, to_x(i.mem.disp))) - if i.mem.disptype == TMS320C64X_MEM_DISP_REGISTER: - print("\t\t\toperands[%u].mem.disptype: Register" % (c)) - print("\t\t\toperands[%u].mem.disp: %s" \ - % (c, insn.reg_name(i.mem.disp))) - print("\t\t\toperands[%u].mem.unit: %u" % (c, i.mem.unit)) - if i.mem.direction == TMS320C64X_MEM_DIR_INVALID: - print("\t\t\toperands[%u].mem.direction: Invalid" % (c)) - if i.mem.direction == TMS320C64X_MEM_DIR_FW: - print("\t\t\toperands[%u].mem.direction: Forward" % (c)) - if i.mem.direction == TMS320C64X_MEM_DIR_BW: - print("\t\t\toperands[%u].mem.direction: Backward" % (c)) - if i.mem.modify == TMS320C64X_MEM_MOD_INVALID: - print("\t\t\toperands[%u].mem.modify: Invalid" % (c)) - if i.mem.modify == TMS320C64X_MEM_MOD_NO: - print("\t\t\toperands[%u].mem.modify: No" % (c)) - if i.mem.modify == TMS320C64X_MEM_MOD_PRE: - print("\t\t\toperands[%u].mem.modify: Pre" % (c)) - if i.mem.modify == TMS320C64X_MEM_MOD_POST: - print("\t\t\toperands[%u].mem.modify: Post" % (c)) - print("\t\t\toperands[%u].mem.scaled: %u" % (c, i.mem.scaled)) - if i.type == TMS320C64X_OP_REGPAIR: - print("\t\toperands[%u].type: REGPAIR = %s:%s" % (c, insn.reg_name(i.reg + 1), insn.reg_name(i.reg))) - c += 1 - - print("\tFunctional unit: ", end="") - if insn.funit.unit == TMS320C64X_FUNIT_D: - print("D%u" % insn.funit.side) - elif insn.funit.unit == TMS320C64X_FUNIT_L: - print("L%u" % insn.funit.side) - elif insn.funit.unit == TMS320C64X_FUNIT_M: - print("M%u" % insn.funit.side) - elif insn.funit.unit == TMS320C64X_FUNIT_S: - print("S%u" % insn.funit.side) - elif insn.funit.unit == TMS320C64X_FUNIT_NO: - print("No Functional Unit") - else: - print("Unknown (Unit %u, Side %u)" % (insn.funit.unit, insn.funit.side)) - - if insn.funit.crosspath == 1: - print("\tCrosspath: 1") - - if insn.condition.reg != TMS320C64X_REG_INVALID: - print("\tCondition: [%c%s]" % ("!" if insn.condition.zero == 1 else " ", insn.reg_name(insn.condition.reg))) - print("\tParallel: %s" % ("true" if insn.parallel == 1 else "false")) - - print() - -# ## Test class Cs -def test_class(): - - for (arch, mode, code, comment) in all_tests: - print("*" * 16) - print("Platform: %s" %comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - md.detail = True - for insn in md.disasm(code, 0x1000): - print_insn_detail(insn) - print("0x%x:\n" % (insn.address + insn.size)) - except CsError as e: - print("ERROR: %s" %e) - - -if __name__ == '__main__': - test_class() diff --git a/bindings/python/tests/test_tricore.py b/bindings/python/tests/test_tricore.py deleted file mode 100755 index 632a026ada..0000000000 --- a/bindings/python/tests/test_tricore.py +++ /dev/null @@ -1,63 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Nguyen Anh Quynnh - -from capstone import * -from capstone.tricore import * -from xprint import to_hex, to_x - -TRICORE_CODE = b"\x09\xcf\xbc\xf5\x09\xf4\x01\x00\x89\xfb\x8f\x74\x89\xfe\x48\x01\x29\x00\x19\x25\x29\x03\x09\xf4\x85\xf9\x68\x0f\x16\x01" - -all_tests = ( - (CS_ARCH_TRICORE, CS_MODE_TRICORE_162, TRICORE_CODE, "TriCore"), -) - - -def print_insn_detail(insn): - # print address, mnemonic and operands - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - - if len(insn.operands) > 0: - print("\top_count: %u" % len(insn.operands)) - c = 0 - for i in insn.operands: - if i.type == TRICORE_OP_REG: - print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) - if i.type == TRICORE_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) - if i.type == TRICORE_OP_MEM: - print("\t\toperands[%u].type: MEM" % c) - if i.mem.base != 0: - print("\t\t\toperands[%u].mem.base: REG = %s" \ - % (c, insn.reg_name(i.mem.base))) - if i.mem.disp != 0: - print("\t\t\toperands[%u].mem.disp: 0x%s" \ - % (c, to_x(i.mem.disp))) - c += 1 - print() - - -# ## Test class Cs -def test_class(): - for (arch, mode, code, comment) in all_tests: - print("*" * 16) - print("Platform: %s" % comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - md.detail = True - for insn in md.disasm(code, 0x1000): - print_insn_detail(insn) - print("0x%x:" % (insn.address + insn.size)) - except CsError as e: - print("ERROR: %s" % e) - - -if __name__ == '__main__': - test_class() diff --git a/bindings/python/tests/test_wasm.py b/bindings/python/tests/test_wasm.py deleted file mode 100755 index eea8549827..0000000000 --- a/bindings/python/tests/test_wasm.py +++ /dev/null @@ -1,80 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Peace-Maker - -from capstone import * -from capstone.wasm import * -from xprint import to_hex - -WASM_CODE = b"\x20\x00\x20\x01\x41\x20\x10\xc9\x01\x45\x0b" - -all_tests = ( - (CS_ARCH_WASM, 0, WASM_CODE, "WASM"), -) - - -def print_insn_detail(insn): - # print address, mnemonic and operands - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - - if len(insn.groups) > 0: - print("\tGroups: ", end="") - for group in insn.groups: - print("%s " % insn.group_name(group), end="") - print() - - if len(insn.operands) > 0: - print("\tOperand count: %u" % len(insn.operands)) - c = 0 - for i in insn.operands: - if i.type == WASM_OP_INT7: - print("\t\tOperand[%u] type: int7" % c) - print("\t\tOperand[%u] value: %d" % (c, i.int7)) - elif i.type == WASM_OP_VARUINT32: - print("\t\tOperand[%u] type: varuint32" % c) - print("\t\tOperand[%u] value: %#x" % (c, i.varuint32)) - elif i.type == WASM_OP_VARUINT64: - print("\t\tOperand[%u] type: varuint64" % c) - print("\t\tOperand[%u] value: %#x" % (c, i.varuint64)) - elif i.type == WASM_OP_UINT32: - print("\t\tOperand[%u] type: uint32" % c) - print("\t\tOperand[%u] value: %#x" % (c, i.uint32)) - elif i.type == WASM_OP_UINT64: - print("\t\tOperand[%u] type: uint64" % c) - print("\t\tOperand[%u] value: %#x" % (c, i.uint64)) - elif i.type == WASM_OP_IMM: - print("\t\tOperand[%u] type: imm" % c) - print("\t\tOperand[%u] value: %#x %#x" % (c, i.immediate[0], i.immediate[1])) - elif i.type == WASM_OP_BRTABLE: - print("\t\tOperand[%u] type: brtable" % c) - print("\t\tOperand[%u] value: length=%#x, address=%#x, default_target=%#x" % (c, i.brtable.length, i.brtable.address, i.brtable.default_target)) - print("\t\tOperand[%u] size: %u" % (c, i.size)) - c += 1 - - - -# ## Test class Cs -def test_class(): - for (arch, mode, code, comment) in all_tests: - print("*" * 16) - print("Platform: %s" % comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - md.detail = True - for insn in md.disasm(code, 0xffff): - print_insn_detail(insn) - print() - print("0x%x:\n" % (insn.address + insn.size)) - except CsError as e: - print("ERROR: %s" % e) - - -if __name__ == '__main__': - test_class() diff --git a/bindings/python/tests/test_x86.py b/bindings/python/tests/test_x86.py deleted file mode 100755 index 4bcf4238bd..0000000000 --- a/bindings/python/tests/test_x86.py +++ /dev/null @@ -1,344 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Nguyen Anh Quynnh -from capstone import * -from capstone.x86 import * -from xprint import to_hex, to_x - - -X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00\xe9\xea\xbe\xad\xde\xff\x25\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff" -X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\x66\xe9\xb8\x00\x00\x00\x67\xff\xa0\x23\x01\x00\x00\x66\xe8\xcb\x00\x00\x00\x74\xfc" -X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\xe9\xea\xbe\xad\xde\xff\xa0\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff" - -all_tests = ( - (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None), - (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (AT&T syntax)", CS_OPT_SYNTAX_ATT), - (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None), - (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", None), - ) - - -def get_eflag_name(eflag): - if eflag == X86_EFLAGS_UNDEFINED_OF: - return "UNDEF_OF" - elif eflag == X86_EFLAGS_UNDEFINED_SF: - return "UNDEF_SF" - elif eflag == X86_EFLAGS_UNDEFINED_ZF: - return "UNDEF_ZF" - elif eflag == X86_EFLAGS_MODIFY_AF: - return "MOD_AF" - elif eflag == X86_EFLAGS_UNDEFINED_PF: - return "UNDEF_PF" - elif eflag == X86_EFLAGS_MODIFY_CF: - return "MOD_CF" - elif eflag == X86_EFLAGS_MODIFY_SF: - return "MOD_SF" - elif eflag == X86_EFLAGS_MODIFY_ZF: - return "MOD_ZF" - elif eflag == X86_EFLAGS_UNDEFINED_AF: - return "UNDEF_AF" - elif eflag == X86_EFLAGS_MODIFY_PF: - return "MOD_PF" - elif eflag == X86_EFLAGS_UNDEFINED_CF: - return "UNDEF_CF" - elif eflag == X86_EFLAGS_MODIFY_OF: - return "MOD_OF" - elif eflag == X86_EFLAGS_RESET_OF: - return "RESET_OF" - elif eflag == X86_EFLAGS_RESET_CF: - return "RESET_CF" - elif eflag == X86_EFLAGS_RESET_DF: - return "RESET_DF" - elif eflag == X86_EFLAGS_RESET_IF: - return "RESET_IF" - elif eflag == X86_EFLAGS_TEST_OF: - return "TEST_OF" - elif eflag == X86_EFLAGS_TEST_SF: - return "TEST_SF" - elif eflag == X86_EFLAGS_TEST_ZF: - return "TEST_ZF" - elif eflag == X86_EFLAGS_TEST_PF: - return "TEST_PF" - elif eflag == X86_EFLAGS_TEST_CF: - return "TEST_CF" - elif eflag == X86_EFLAGS_RESET_SF: - return "RESET_SF" - elif eflag == X86_EFLAGS_RESET_AF: - return "RESET_AF" - elif eflag == X86_EFLAGS_RESET_TF: - return "RESET_TF" - elif eflag == X86_EFLAGS_RESET_NT: - return "RESET_NT" - elif eflag == X86_EFLAGS_PRIOR_OF: - return "PRIOR_OF" - elif eflag == X86_EFLAGS_PRIOR_SF: - return "PRIOR_SF" - elif eflag == X86_EFLAGS_PRIOR_ZF: - return "PRIOR_ZF" - elif eflag == X86_EFLAGS_PRIOR_AF: - return "PRIOR_AF" - elif eflag == X86_EFLAGS_PRIOR_PF: - return "PRIOR_PF" - elif eflag == X86_EFLAGS_PRIOR_CF: - return "PRIOR_CF" - elif eflag == X86_EFLAGS_PRIOR_TF: - return "PRIOR_TF" - elif eflag == X86_EFLAGS_PRIOR_IF: - return "PRIOR_IF" - elif eflag == X86_EFLAGS_PRIOR_DF: - return "PRIOR_DF" - elif eflag == X86_EFLAGS_TEST_NT: - return "TEST_NT" - elif eflag == X86_EFLAGS_TEST_DF: - return "TEST_DF" - elif eflag == X86_EFLAGS_RESET_PF: - return "RESET_PF" - elif eflag == X86_EFLAGS_PRIOR_NT: - return "PRIOR_NT" - elif eflag == X86_EFLAGS_MODIFY_TF: - return "MOD_TF" - elif eflag == X86_EFLAGS_MODIFY_IF: - return "MOD_IF" - elif eflag == X86_EFLAGS_MODIFY_DF: - return "MOD_DF" - elif eflag == X86_EFLAGS_MODIFY_NT: - return "MOD_NT" - elif eflag == X86_EFLAGS_MODIFY_RF: - return "MOD_RF" - elif eflag == X86_EFLAGS_SET_CF: - return "SET_CF" - elif eflag == X86_EFLAGS_SET_DF: - return "SET_DF" - elif eflag == X86_EFLAGS_SET_IF: - return "SET_IF" - else: - return None - -def get_fpu_flag_name(flag): - if flag == X86_FPU_FLAGS_MODIFY_C0: - return "MOD_C0" - elif flag == X86_FPU_FLAGS_MODIFY_C1: - return "MOD_C1" - elif flag == X86_FPU_FLAGS_MODIFY_C2: - return "MOD_C2" - elif flag == X86_FPU_FLAGS_MODIFY_C3: - return "MOD_C3" - elif flag == X86_FPU_FLAGS_RESET_C0: - return "RESET_C0" - elif flag == X86_FPU_FLAGS_RESET_C1: - return "RESET_C1" - elif flag == X86_FPU_FLAGS_RESET_C2: - return "RESET_C2" - elif flag == X86_FPU_FLAGS_RESET_C3: - return "RESET_C3" - elif flag == X86_FPU_FLAGS_SET_C0: - return "SET_C0" - elif flag == X86_FPU_FLAGS_SET_C1: - return "SET_C1" - elif flag == X86_FPU_FLAGS_SET_C2: - return "SET_C2" - elif flag == X86_FPU_FLAGS_SET_C3: - return "SET_C3" - elif flag == X86_FPU_FLAGS_UNDEFINED_C0: - return "UNDEF_C0" - elif flag == X86_FPU_FLAGS_UNDEFINED_C1: - return "UNDEF_C1" - elif flag == X86_FPU_FLAGS_UNDEFINED_C2: - return "UNDEF_C2" - elif flag == X86_FPU_FLAGS_UNDEFINED_C3: - return "UNDEF_C3" - elif flag == X86_FPU_FLAGS_TEST_C0: - return "TEST_C0" - elif flag == X86_FPU_FLAGS_TEST_C1: - return "TEST_C1" - elif flag == X86_FPU_FLAGS_TEST_C2: - return "TEST_C2" - elif flag == X86_FPU_FLAGS_TEST_C3: - return "TEST_C3" - else: - return None - - -def print_insn_detail(mode, insn): - def print_string_hex(comment, str): - print(comment, end=' '), - for c in str: - print("0x%02x " % c, end=''), - print() - - # print address, mnemonic and operands - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - - # print instruction prefix - print_string_hex("\tPrefix:", insn.prefix) - - # print instruction's opcode - print_string_hex("\tOpcode:", insn.opcode) - - # print operand's REX prefix (non-zero value is relevant for x86_64 instructions) - print("\trex: 0x%x" % (insn.rex)) - - # print operand's address size - print("\taddr_size: %u" % (insn.addr_size)) - - # print modRM byte - print("\tmodrm: 0x%x" % (insn.modrm)) - - # print modRM offset - if insn.encoding.modrm_offset != 0: - print("\tmodrm_offset: 0x%x" % (insn.encoding.modrm_offset)) - - # print displacement value - print("\tdisp: 0x%s" % to_x(insn.disp)) - - # print displacement offset (offset into instruction bytes) - if insn.encoding.disp_offset != 0: - print("\tdisp_offset: 0x%x" % (insn.encoding.disp_offset)) - - # print displacement size - if insn.encoding.disp_size != 0: - print("\tdisp_size: 0x%x" % (insn.encoding.disp_size)) - - # SIB is not available in 16-bit mode - if (mode & CS_MODE_16 == 0): - # print SIB byte - print("\tsib: 0x%x" % (insn.sib)) - if (insn.sib): - if insn.sib_base != 0: - print("\t\tsib_base: %s" % (insn.reg_name(insn.sib_base))) - if insn.sib_index != 0: - print("\t\tsib_index: %s" % (insn.reg_name(insn.sib_index))) - if insn.sib_scale != 0: - print("\t\tsib_scale: %d" % (insn.sib_scale)) - - # XOP CC type - if insn.xop_cc != X86_XOP_CC_INVALID: - print("\txop_cc: %u" % (insn.xop_cc)) - - # SSE CC type - if insn.sse_cc != X86_SSE_CC_INVALID: - print("\tsse_cc: %u" % (insn.sse_cc)) - - # AVX CC type - if insn.avx_cc != X86_AVX_CC_INVALID: - print("\tavx_cc: %u" % (insn.avx_cc)) - - # AVX Suppress All Exception - if insn.avx_sae: - print("\tavx_sae: TRUE") - - # AVX Rounding Mode type - if insn.avx_rm != X86_AVX_RM_INVALID: - print("\tavx_rm: %u" % (insn.avx_rm)) - - count = insn.op_count(X86_OP_IMM) - if count > 0: - print("\timm_count: %u" % count) - for i in range(count): - op = insn.op_find(X86_OP_IMM, i + 1) - print("\t\timms[%u]: 0x%s" % (i + 1, to_x(op.imm))) - if insn.encoding.imm_offset != 0: - print("\timm_offset: 0x%x" % (insn.encoding.imm_offset)) - if insn.encoding.imm_size != 0: - print("\timm_size: 0x%x" % (insn.encoding.imm_size)) - - if len(insn.operands) > 0: - print("\top_count: %u" % len(insn.operands)) - c = -1 - for i in insn.operands: - c += 1 - if i.type == X86_OP_REG: - print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) - if i.type == X86_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) - if i.type == X86_OP_MEM: - print("\t\toperands[%u].type: MEM" % c) - if i.mem.segment != 0: - print("\t\t\toperands[%u].mem.segment: REG = %s" % (c, insn.reg_name(i.mem.segment))) - if i.mem.base != 0: - print("\t\t\toperands[%u].mem.base: REG = %s" % (c, insn.reg_name(i.mem.base))) - if i.mem.index != 0: - print("\t\t\toperands[%u].mem.index: REG = %s" % (c, insn.reg_name(i.mem.index))) - if i.mem.scale != 1: - print("\t\t\toperands[%u].mem.scale: %u" % (c, i.mem.scale)) - if i.mem.disp != 0: - print("\t\t\toperands[%u].mem.disp: 0x%s" % (c, to_x(i.mem.disp))) - - # AVX broadcast type - if i.avx_bcast != X86_AVX_BCAST_INVALID: - print("\t\toperands[%u].avx_bcast: %u" % (c, i.avx_bcast)) - - # AVX zero opmask {z} - if i.avx_zero_opmask: - print("\t\toperands[%u].avx_zero_opmask: TRUE" % (c)) - - print("\t\toperands[%u].size: %u" % (c, i.size)) - - if i.access == CS_AC_READ: - print("\t\toperands[%u].access: READ" % (c)) - elif i.access == CS_AC_WRITE: - print("\t\toperands[%u].access: WRITE" % (c)) - elif i.access == CS_AC_READ | CS_AC_WRITE: - print("\t\toperands[%u].access: READ | WRITE" % (c)) - - (regs_read, regs_write) = insn.regs_access() - - if len(regs_read) > 0: - print("\tRegisters read:", end="") - for r in regs_read: - print(" %s" %(insn.reg_name(r)), end="") - print("") - - if len(regs_write) > 0: - print("\tRegisters modified:", end="") - for r in regs_write: - print(" %s" %(insn.reg_name(r)), end="") - print("") - - if insn.eflags or insn.fpu_flags: - updated_flags = [] - for group in insn.groups: - if group == X86_GRP_FPU: - for i in range(64): - if insn.fpu_flags & (1 << i): - updated_flags.append(get_fpu_flag_name(1 << i)) - print("\tFPU_FLAGS: %s" % (' '.join(p for p in updated_flags))) - break - - if not updated_flags: - for i in range(64): - if insn.eflags & (1 << i): - updated_flags.append(get_eflag_name(1 << i)) - print("\tEFLAGS: %s" % (' '.join(p for p in updated_flags))) - - -# ## Test class Cs -def test_class(): - - for (arch, mode, code, comment, syntax) in all_tests: - print("*" * 16) - print("Platform: %s" % comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - md.detail = True - - if syntax is not None: - md.syntax = syntax - - for insn in md.disasm(code, 0x1000): - print_insn_detail(mode, insn) - print () - print ("0x%x:\n" % (insn.address + insn.size)) - except CsError as e: - print("ERROR: %s" % e) - - -if __name__ == '__main__': - test_class() diff --git a/bindings/python/tests/test_xcore.py b/bindings/python/tests/test_xcore.py deleted file mode 100755 index 628a5a0c8c..0000000000 --- a/bindings/python/tests/test_xcore.py +++ /dev/null @@ -1,70 +0,0 @@ -#!/usr/bin/env python3 - -# Capstone Python bindings, by Nguyen Anh Quynnh - -from capstone import * -from capstone.xcore import * -from xprint import to_x, to_hex - - -XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10\x09\xfd\xec\xa7" - -all_tests = ( - (CS_ARCH_XCORE, 0, XCORE_CODE, "XCore"), -) - - -def print_insn_detail(insn): - # print address, mnemonic and operands - print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) - - # "data" instruction generated by SKIPDATA option has no detail - if insn.id == 0: - return - - if len(insn.operands) > 0: - print("\top_count: %u" % len(insn.operands)) - c = 0 - for i in insn.operands: - if i.type == XCORE_OP_REG: - print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) - if i.type == XCORE_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) - if i.type == XCORE_OP_MEM: - print("\t\toperands[%u].type: MEM" % c) - if i.mem.base != 0: - print("\t\t\toperands[%u].mem.base: REG = %s" \ - % (c, insn.reg_name(i.mem.base))) - if i.mem.index != 0: - print("\t\t\toperands[%u].mem.index: REG = %s" \ - % (c, insn.reg_name(i.mem.index))) - if i.mem.disp != 0: - print("\t\t\toperands[%u].mem.disp: 0x%s" \ - % (c, to_x(i.mem.disp))) - if i.mem.direct != 1: - print("\t\t\toperands[%u].mem.direct: -1" % c) - c += 1 - - -# ## Test class Cs -def test_class(): - - for (arch, mode, code, comment) in all_tests: - print("*" * 16) - print("Platform: %s" %comment) - print("Code: %s" % to_hex(code)) - print("Disasm:") - - try: - md = Cs(arch, mode) - md.detail = True - for insn in md.disasm(code, 0x1000): - print_insn_detail(insn) - print () - print("0x%x:\n" % (insn.address + insn.size)) - except CsError as e: - print("ERROR: %s" %e) - - -if __name__ == '__main__': - test_class() diff --git a/config.mk b/config.mk index 5d5ac63694..fa26997294 100644 --- a/config.mk +++ b/config.mk @@ -1,5 +1,5 @@ # This file contains all customized compile options for Capstone. -# Consult COMPILE.TXT & docs/README for details. +# Consult COMPILE_MAKE.TXT & docs/README for details. ################################################################################ # Specify which archs you want to compile in. By default, we build all archs. diff --git a/cs.c b/cs.c index 2c02d9da8c..4bb739a407 100644 --- a/cs.c +++ b/cs.c @@ -1110,9 +1110,8 @@ cs_err CAPSTONE_API cs_option(csh ud, cs_opt_type type, size_t value) } break; case CS_OPT_NO_BRANCH_OFFSET: - if (handle->PrintBranchImmNotAsAddress) - return CS_ERR_OK; - break; + handle->PrintBranchImmNotAsAddress = value == CS_OPT_ON ? true : false; + return CS_ERR_OK; } if (!arch_configs[handle->arch].arch_option) diff --git a/cstool/cstool_aarch64.c b/cstool/cstool_aarch64.c index 7a55fa12f1..294193a587 100644 --- a/cstool/cstool_aarch64.c +++ b/cstool/cstool_aarch64.c @@ -66,14 +66,14 @@ void print_insn_detail_aarch64(csh handle, cs_insn *ins) printf("\t\toperands[%u].sme.tile: %s\n", i, cs_reg_name(handle, op->sme.tile)); if (op->sme.slice_reg != AARCH64_REG_INVALID) printf("\t\toperands[%u].sme.slice_reg: %s\n", i, cs_reg_name(handle, op->sme.slice_reg)); - if (op->sme.slice_offset.imm != -1 || op->sme.slice_offset.imm_range.first != -1) { + if (op->sme.slice_offset.imm != AARCH64_SLICE_IMM_INVALID || op->sme.slice_offset.imm_range.first != AARCH64_SLICE_IMM_RANGE_INVALID) { printf("\t\toperands[%u].sme.slice_offset: ", i); if (op->sme.has_range_offset) printf("%hhd:%hhd\n", op->sme.slice_offset.imm_range.first, op->sme.slice_offset.imm_range.offset); else printf("%d\n", op->sme.slice_offset.imm); } - if (op->sme.slice_reg != AARCH64_REG_INVALID || op->sme.slice_offset.imm != -1) + if (op->sme.slice_reg != AARCH64_REG_INVALID || op->sme.slice_offset.imm != AARCH64_SLICE_IMM_INVALID) printf("\t\toperands[%u].sme.is_vertical: %s\n", i, (op->sme.is_vertical ? "true" : "false")); break; case AARCH64_OP_PRED: diff --git a/include/capstone/aarch64.h b/include/capstone/aarch64.h index 034a120e4a..e25ca28a82 100644 --- a/include/capstone/aarch64.h +++ b/include/capstone/aarch64.h @@ -1965,7 +1965,7 @@ typedef enum { // clang-format on // generated content end - AArch64_TSB_ENDING, + AARCH64_TSB_ENDING, } aarch64_tsb; typedef union { @@ -2788,9 +2788,12 @@ typedef enum { AARCH64_SME_OP_TILE_VEC, ///< SME operand is a tile indexed by a register and/or immediate } aarch64_sme_op_type; +#define AARCH64_SLICE_IMM_INVALID UINT16_MAX +#define AARCH64_SLICE_IMM_RANGE_INVALID UINT8_MAX + typedef struct { - int8_t first; - int8_t offset; + uint8_t first; + uint8_t offset; } aarch64_imm_range; /// SME Instruction's matrix operand @@ -2799,9 +2802,9 @@ typedef struct { aarch64_reg tile; ///< Matrix tile register aarch64_reg slice_reg; ///< slice index reg union { - int8_t imm; - aarch64_imm_range imm_range; - } slice_offset; ///< slice index offset. Is set to -1 if invalid. + uint16_t imm; ///< Invalid if equal to AARCH64_SLICE_IMM_INVALID + aarch64_imm_range imm_range; ///< Members are set to AARCH64_SLICE_IMM_RANGE_INVALID if invalid. + } slice_offset; ///< slice index offset. bool has_range_offset; ///< If true, the offset is a range. bool is_vertical; ///< Flag if slice is vertical or horizontal } aarch64_op_sme; diff --git a/include/capstone/alpha.h b/include/capstone/alpha.h index 60932d0fd3..839ce02b41 100644 --- a/include/capstone/alpha.h +++ b/include/capstone/alpha.h @@ -299,4 +299,4 @@ typedef enum alpha_insn_group { } #endif -#endif \ No newline at end of file +#endif diff --git a/include/capstone/arm.h b/include/capstone/arm.h index 1fc608eb0b..3824da4472 100644 --- a/include/capstone/arm.h +++ b/include/capstone/arm.h @@ -903,7 +903,7 @@ typedef struct cs_arm { ARMVCC_VPTCodes vcc; ///< Vector conditional code for this instruction. bool update_flags; ///< does this insn update flags? bool post_index; ///< only set if writeback is 'True', if 'False' pre-index, otherwise post. - int /* arm_mem_bo_opt */ mem_barrier; ///< Option for some memory barrier instructions + arm_mem_bo_opt mem_barrier; ///< Option for some memory barrier instructions // Check ARM_PredBlockMask for encoding details. uint8_t /* ARM_PredBlockMask */ pred_mask; ///< Used by IT/VPT block instructions. /// Number of operands of this instruction, diff --git a/include/capstone/arm64.h b/include/capstone/arm64.h index 600b55b977..f7a5ca27f8 100644 --- a/include/capstone/arm64.h +++ b/include/capstone/arm64.h @@ -1863,7 +1863,7 @@ typedef enum { ARM64_TSB_CSYNC = AARCH64_TSB_CSYNC, - ARM64_TSB_ENDING = AArch64_TSB_ENDING, + ARM64_TSB_ENDING = AARCH64_TSB_ENDING, } arm64_tsb; typedef aarch64_sysop_reg arm64_sysop_reg; diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h index f40774d039..7de50bfd18 100644 --- a/include/capstone/capstone.h +++ b/include/capstone/capstone.h @@ -284,7 +284,7 @@ typedef enum cs_opt_type { CS_OPT_SKIPDATA_SETUP, ///< Setup user-defined function for SKIPDATA option CS_OPT_MNEMONIC, ///< Customize instruction mnemonic CS_OPT_UNSIGNED, ///< print immediate operands in unsigned form - CS_OPT_NO_BRANCH_OFFSET, ///< ARM, prints branch immediates without offset. + CS_OPT_NO_BRANCH_OFFSET, ///< ARM, PPC, AArch64, prints branch immediates without offset. } cs_opt_type; /// Runtime option value (associated with option type above) @@ -302,6 +302,12 @@ typedef enum cs_opt_value { CS_OPT_DETAIL_REAL = 1 << 1, ///< If enabled, always sets the real instruction detail. Even if the instruction is an alias. } cs_opt_value; +/// An option +typedef struct { + cs_opt_type type; ///< The option type + cs_opt_value val; ///< The option value to set. +} cs_opt; + /// Common instruction groups - to be consistent across all architectures. typedef enum cs_group_type { CS_GRP_INVALID = 0, ///< uninitialized/invalid group. diff --git a/include/capstone/hppa.h b/include/capstone/hppa.h index 1fa66be63b..fffb6ef73d 100644 --- a/include/capstone/hppa.h +++ b/include/capstone/hppa.h @@ -540,4 +540,4 @@ typedef enum hppa_insn_group { } #endif -#endif \ No newline at end of file +#endif diff --git a/include/capstone/ppc.h b/include/capstone/ppc.h index f308b4df2e..2b04b7a915 100644 --- a/include/capstone/ppc.h +++ b/include/capstone/ppc.h @@ -3280,6 +3280,8 @@ typedef enum ppc_insn_group { /// PPC instruction formats. To get details about them please /// refer to `PPCInstrFormats.td` in LLVM. typedef enum { + PPC_INSN_FORM_INVALID = 0, + // generated content begin // clang-format off diff --git a/include/capstone/sparc.h b/include/capstone/sparc.h index e33d17391c..f09b5ca7ef 100644 --- a/include/capstone/sparc.h +++ b/include/capstone/sparc.h @@ -64,6 +64,8 @@ typedef enum sparc_hint { SPARC_HINT_A = 1 << 0, ///< annul delay slot instruction SPARC_HINT_PT = 1 << 1, ///< branch taken SPARC_HINT_PN = 1 << 2, ///< branch NOT taken + SPARC_HINT_A_PN = SPARC_HINT_A | SPARC_HINT_PN, + SPARC_HINT_A_PT = SPARC_HINT_A | SPARC_HINT_PT, } sparc_hint; /// Operand type for instruction's operands diff --git a/include/capstone/x86.h b/include/capstone/x86.h index b6b56c050c..1761cc4e06 100644 --- a/include/capstone/x86.h +++ b/include/capstone/x86.h @@ -246,6 +246,7 @@ typedef enum x86_avx_rm { /// Instruction prefixes - to be used in cs_x86.prefix[] typedef enum x86_prefix { + X86_PREFIX_0 = 0x0, X86_PREFIX_LOCK = 0xf0, ///< lock (cs_x86.prefix[0] X86_PREFIX_REP = 0xf3, ///< rep (cs_x86.prefix[0] X86_PREFIX_REPE = 0xf3, ///< repe/repz (cs_x86.prefix[0] diff --git a/run-clang-tidy.sh b/run-clang-tidy.sh index 9178f72e2f..6f71db8d36 100755 --- a/run-clang-tidy.sh +++ b/run-clang-tidy.sh @@ -18,10 +18,12 @@ BUILD_PATH="$1" check_list="clang-analyzer-*,-clang-analyzer-cplusplus*,-clang-analyzer-optin.performance.Padding" -if $(hash clang-tidy-15); then - clang-tidy-15 $(find ./arch ./*.c -type f -iregex ".*\.[c]") -p "$BUILD_PATH" -checks="$check_list" > ct-warnings.txt +if $(hash clang-tidy-18); then + echo -e "#############\nProduced by\n$(clang-tidy-18 --version)\n#############\n\n" > ct-warnings.txt + clang-tidy-18 $(find ./arch ./*.c -type f -iregex ".*\.[c]") -p "$BUILD_PATH" -checks="$check_list" >> ct-warnings.txt else - clang-tidy $(find ./arch ./*.c -type f -iregex ".*\.[c]") -p "$BUILD_PATH" -checks="$check_list" > ct-warnings.txt + echo -e "#############\nProduced by\n$(clang-tidy --version)\n#############\n\n" > ct-warnings.txt + clang-tidy $(find ./arch ./*.c -type f -iregex ".*\.[c]") -p "$BUILD_PATH" -checks="$check_list" >> ct-warnings.txt fi if [ $? -ne 0 ]; then diff --git a/suite/MC/README b/suite/MC/README deleted file mode 100644 index 6f2555e04f..0000000000 --- a/suite/MC/README +++ /dev/null @@ -1,47 +0,0 @@ -## Input files for testing Capstone engine. - -Input files used to test instructions of architectures and modes. - -The test cases are taken from `llvm/test/MC`. Note that most of the LLVM tests -are for **encoding** of instructions (`asm_string -> bytes`). - -We test the decoding (`bytes -> asm_string`). -A few tests might decode to a different asm string than -used to encode the instruction (because the behavior -of instructions can be equivalent). - -Fix the obvious broken tests first and test the rest -against `llvm-objdump`. - -### Update test files - -Check `suite/auto-sync/README.md` - -### Test file formatting - -**Format of input files:** -``` -# ARCH, MODE, OPTION -hexcode = assembly -``` - -**Example** -``` -# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None -0xa0,0x0b,0x71,0xee = vadd.f64 d16, d17, d16 -... -``` - -**Format of issue file:** - -``` -!# ARCH, MODE, OPTION -hexcode = assembly | regs_read | regs_read_count | regs_write | regs_write_count | groups | groups_count -``` - -**Example** -``` -!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL -0xc0,0x1e,0x0c,0x4e == mov v0.s[1], w22 ; operands[0].vas: 0xb ; operands[0].vector_index: 1 -... -``` diff --git a/suite/MC/README.md b/suite/MC/README.md new file mode 100644 index 0000000000..d86ea1992a --- /dev/null +++ b/suite/MC/README.md @@ -0,0 +1,19 @@ +# Input files for fuzzing input + +These files were the legacy test files but replaced. +No it only is consumed by `test_corpus3.py` to generate input cases for the fuzzer. + +### Test file formatting + +**Format of input files:** +``` +# ARCH, MODE, OPTION + = +``` + +**Example** +``` +# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None +0xa0,0x0b,0x71,0xee = vadd.f64 d16, d17, d16 +... +``` diff --git a/suite/README b/suite/README index fc9b59a585..e501632f15 100644 --- a/suite/README +++ b/suite/README @@ -2,20 +2,9 @@ This directory contains some tools used by developers of Capstone project. Average users should ignore all the contents here. -- arm/ - Test some ARM's special input. - -- MC/ - Input used to test various architectures & modes. - - benchmark.py This script benchmarks Python binding by disassembling some random code. -- test_*.sh - Run all the tests and send the output to external file to be compared later. - This is useful when we want to verify if a commit (wrongly) changes - the disassemble result. - - compile_all.sh Compile Capstone for all platforms (*nix32, clang, cygwin, cross-compile) & report the result as pass or fail. @@ -24,10 +13,6 @@ Average users should ignore all the contents here. This simple script disassembles random code for all archs (or selected arch) in order to find segfaults. -- test_mc.sh - This script compares the output of Capstone with LLVM's llvm-mc with the - input coming from MC/. This relies on test_mc.py to do all the hard works. - - x86odd.py Test some tricky X86 instructions. diff --git a/suite/arm/Makefile b/suite/arm/Makefile deleted file mode 100644 index aaf4d05d72..0000000000 --- a/suite/arm/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# Sample Makefile for Capstone Disassembly Engine - -LIBNAME = capstone - -test_arm_regression: test_arm_regression.o - ${CC} $< -O3 -Wall -l$(LIBNAME) -o $@ - -%.o: %.c - ${CC} -c -I../../include $< -o $@ - -clean: - rm -rf *.o test_arm_regression diff --git a/suite/arm/test_arm_regression.c b/suite/arm/test_arm_regression.c deleted file mode 100644 index fade56b490..0000000000 --- a/suite/arm/test_arm_regression.c +++ /dev/null @@ -1,391 +0,0 @@ -/* Capstone Disassembler Engine */ -/* By David Hogarty, 2014 */ - -// the following must precede stdio (woo, thanks msft) -#if defined(_MSC_VER) && _MSC_VER < 1900 -#define _CRT_SECURE_NO_WARNINGS -#define snprintf _snprintf -#endif -#include -#include -#include - -#include -#include - -static csh handle; - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - char *comment; - int syntax; -}; - -static char *hex_string(unsigned char *str, size_t len) -{ - // returns a malloced string that has the hex version of the string in it - // null if failed to malloc - char *hex_out; - size_t i; - - hex_out = (char *) malloc(len*2 + 1); // two ascii characters per input character, plus trailing null - if (!hex_out) { goto Exit; } - - for (i = 0; i < len; ++i) { - snprintf(hex_out + (i * 2), 3, "%02x", str[i]); - } - - hex_out[len*2] = 0; // trailing null - -Exit: - return hex_out; -} - -static void snprint_insn_detail(char * buf, size_t * cur, size_t * left, cs_insn *ins) -{ -#define _this_printf(...) \ - { \ - size_t used = 0; \ - used = snprintf(buf + *cur, *left, __VA_ARGS__); \ - *left -= used; \ - *cur += used; \ - } - - cs_arm *arm; - int i; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - arm = &(ins->detail->arm); - - if (arm->op_count) - _this_printf("\top_count: %u\n", arm->op_count); - - for (i = 0; i < arm->op_count; i++) { - cs_arm_op *op = &(arm->operands[i]); - switch((int)op->type) { - default: - break; - case ARM_OP_REG: - _this_printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); - break; - case ARM_OP_IMM: - _this_printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); - break; - case ARM_OP_FP: - _this_printf("\t\toperands[%u].type: FP = %f\n", i, op->fp); - break; - case ARM_OP_MEM: - _this_printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.base != ARM_REG_INVALID) - _this_printf("\t\t\toperands[%u].mem.base: REG = %s\n", - i, cs_reg_name(handle, op->mem.base)); - if (op->mem.index != ARM_REG_INVALID) - _this_printf("\t\t\toperands[%u].mem.index: REG = %s\n", - i, cs_reg_name(handle, op->mem.index)); - if (op->mem.scale != 1) - _this_printf("\t\t\toperands[%u].mem.scale: %u\n", i, op->mem.scale); - if (op->mem.disp != 0) - _this_printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); - - break; - case ARM_OP_PIMM: - _this_printf("\t\toperands[%u].type: P-IMM = %" PRIu64 "\n", i, op->imm); - break; - case ARM_OP_CIMM: - _this_printf("\t\toperands[%u].type: C-IMM = %" PRIu64 "\n", i, op->imm); - break; - } - - if (op->shift.type != ARM_SFT_INVALID && op->shift.value) { - if (op->shift.type < ARM_SFT_ASR_REG) { - // shift with constant value - _this_printf("\t\t\tShift: %u = %u\n", op->shift.type, op->shift.value); - } else { - // shift with register - _this_printf("\t\t\tShift: %u = %s\n", op->shift.type, - cs_reg_name(handle, op->shift.value)); - } - } - } - - if (arm->cc != ARMCC_AL && arm->cc != ARMCC_UNDEF) { - _this_printf("\tCode condition: %u\n", arm->cc); - } - - if (arm->update_flags) { - _this_printf("\tUpdate-flags: True\n"); - } - - if (ins->detail->writeback) { - _this_printf("\tWrite-back: True\n"); - } - -#undef _this_printf -} - -static void print_insn_detail(cs_insn *ins) -{ - char a_buf[2048]; - size_t cur=0, left=2048; - snprint_insn_detail(a_buf, &cur, &left, ins); - printf("%s\n", a_buf); -} - -struct invalid_code { - unsigned char *code; - size_t size; - char *comment; -}; - -#define MAX_INVALID_CODES 16 - -struct invalid_instructions { - cs_arch arch; - cs_mode mode; - char *platform_comment; - int num_invalid_codes; - struct invalid_code invalid_codes[MAX_INVALID_CODES]; -}; - -static void test_invalids() -{ - struct invalid_instructions invalids[] = {{ - CS_ARCH_ARM, - CS_MODE_THUMB, - "Thumb", - 1, - {{ - (unsigned char *)"\xbd\xe8\x1e\xff", - 4, - "invalid thumb2 pop because sp used and because both pc and lr are " - "present at the same time" - }}, - }}; - - struct invalid_instructions * invalid = NULL; - - uint64_t address = 0x1000; - cs_insn *insn; - int i; - int j; - size_t count; - - printf("\nShould be invalid\n" - "-----------------\n"); - - for (i = 0; i < sizeof(invalids)/sizeof(invalids[0]); i++) { - cs_err err; - - invalid = invalids + i; - err = cs_open(invalid->arch, invalid->mode, &handle); - - if (err) { - printf("Failed on cs_open() with error returned: %u\n", err); - continue; - } - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME); - - for (j = 0; j < invalid->num_invalid_codes; ++j) { - struct invalid_code *invalid_code = NULL; - char *hex_str = NULL; - - invalid_code = invalid->invalid_codes + j; - - hex_str = hex_string(invalid_code->code, invalid_code->size); - - printf("%s %s: %s\n", invalid->platform_comment, hex_str, invalid_code->comment); - - free(hex_str); - - count = cs_disasm(handle, - invalid_code->code, invalid_code->size, address, 0, &insn - ); - - if (count) { - size_t k; - printf(" ERROR:\n"); - - for (k = 0; k < count; k++) { - printf(" 0x%"PRIx64":\t%s\t%s\n", - insn[k].address, insn[k].mnemonic, insn[k].op_str); - print_insn_detail(&insn[k]); - } - cs_free(insn, count); - - } else { - printf(" SUCCESS: invalid\n"); - } - } - - cs_close(&handle); - } -} - -struct valid_code { - unsigned char *code; - size_t size; - uint32_t start_addr; - char *expected_out; - char *comment; -}; - -#define MAX_VALID_CODES 16 -struct valid_instructions { - cs_arch arch; - cs_mode mode; - char *platform_comment; - int num_valid_codes; - struct valid_code valid_codes[MAX_VALID_CODES]; -}; - -static void test_valids() -{ - struct valid_instructions valids[] = {{ - CS_ARCH_ARM, - CS_MODE_THUMB, - "Thumb", - 3, - {{ (unsigned char *)"\x00\xf0\x26\xe8", 4, 0x352, - "0x352:\tblx\t#0x3a0\n" - "\top_count: 1\n" - "\t\toperands[0].type: IMM = 0x3a0\n", - - "thumb2 blx with misaligned immediate" - }, { (unsigned char *)"\x05\xdd", 2, 0x1f0, - "0x1f0:\tble\t#0x1fe\n" - "\top_count: 1\n" - "\t\toperands[0].type: IMM = 0x1fe\n" - "\tCode condition: 14\n", - - "thumb b cc with thumb-aligned target" - }, { (unsigned char *)"\xbd\xe8\xf0\x8f", 4, 0, - "0x0:\tpop.w\t{r4, r5, r6, r7, r8, r9, r10, r11, pc}\n" - "\top_count: 9\n" - "\t\toperands[0].type: REG = r4\n" - "\t\toperands[1].type: REG = r5\n" - "\t\toperands[2].type: REG = r6\n" - "\t\toperands[3].type: REG = r7\n" - "\t\toperands[4].type: REG = r8\n" - "\t\toperands[5].type: REG = r9\n" - "\t\toperands[6].type: REG = r10\n" - "\t\toperands[7].type: REG = r11\n" - "\t\toperands[8].type: REG = pc\n", - - "thumb2 pop that should be valid" - }, - } - }}; - - struct valid_instructions *valid = NULL; - - cs_insn *insn; - int i; - int j; - size_t count; - - - for (i = 0; i < sizeof(valids)/sizeof(valids[0]); i++) { - cs_err err; - - valid = valids + i; - err = cs_open(valid->arch, valid->mode, &handle); - - if (err) { - printf("Failed on cs_open() with error returned: %u\n", err); - continue; - } - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME); - -#define _this_printf(...) \ - { \ - size_t used = 0; \ - used = snprintf(tmp_buf + cur, left, __VA_ARGS__); \ - left -= used; \ - cur += used; \ - } - printf("\nShould be valid\n" - "---------------\n"); - - for (j = 0; j < valid->num_valid_codes; ++j) { - char tmp_buf[2048]; - size_t left = 2048; - size_t cur = 0; - char * hex_str = NULL; - - struct valid_code * valid_code = NULL; - valid_code = valid->valid_codes + j; - - hex_str = hex_string(valid_code->code, valid_code->size); - - printf("%s %s @ 0x%04x: %s\n %s", - valid->platform_comment, hex_str, valid_code->start_addr, - valid_code->comment, valid_code->expected_out); - - free(hex_str); - - count = cs_disasm(handle, - valid_code->code, valid_code->size, - valid_code->start_addr, 0, &insn - ); - - if (count) { - size_t k; - size_t max_len = 0; - size_t tmp_len = 0; - - for (k = 0; k < count; k++) { - _this_printf( - "0x%"PRIx64":\t%s\t%s\n", - insn[k].address, insn[k].mnemonic, - insn[k].op_str - ); - - snprint_insn_detail(tmp_buf, &cur, &left, &insn[k]); - } - - max_len = strlen(tmp_buf); - tmp_len = strlen(valid_code->expected_out); - if (tmp_len > max_len) { - max_len = tmp_len; - } - - if (memcmp(tmp_buf, valid_code->expected_out, max_len)) { - printf( - " ERROR: '''\n%s''' does not match" - " expected '''\n%s'''\n", - tmp_buf, valid_code->expected_out - ); - } else { - printf(" SUCCESS: valid\n"); - } - - cs_free(insn, count); - - } else { - printf("ERROR: invalid\n"); - } - } - - cs_close(&handle); - } - -#undef _this_prinf -} - -int main() -{ - test_invalids(); - test_valids(); - return 0; -} - diff --git a/suite/auto-sync/.gitignore b/suite/auto-sync/.gitignore index fca115d2e0..95a3a6a432 100644 --- a/suite/auto-sync/.gitignore +++ b/suite/auto-sync/.gitignore @@ -4,4 +4,9 @@ vendor/llvm_root src/auto-sync/config.json src/autosync/cpptranslator/Tests/Differ/test_saved_patches.json src/autosync.egg-info - +src/autosync/Tests/MCUpdaterTests/ARCH/Output +src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/Output +src/autosync/lit_config/test_dir_* +src/autosync/lit_config/.lit_test_times.txt +src/autosync/Tests/MCUpdaterTests/test_output +src/autosync/Tests/MCUpdaterTests/ARCH/Output diff --git a/suite/auto-sync/README.md b/suite/auto-sync/README.md index 5c519139c1..7973209364 100644 --- a/suite/auto-sync/README.md +++ b/suite/auto-sync/README.md @@ -15,7 +15,7 @@ Please refer to [intro.md](intro.md) for an introduction about this tool. ## Install -Setup Python environment and Tree-sitter +#### Setup Python environment and Tree-sitter ``` cd @@ -26,13 +26,35 @@ python3 -m venv ./.venv source ./.venv/bin/activate ``` -Install Auto-Sync framework +#### Install Auto-Sync framework ``` cd suite/auto-sync/ pip install -e . ``` +#### Clone Capstones LLVM fork and build `llvm-tblgen` + +```bash +git clone https://github.com/capstone-engine/llvm-capstone vendor/llvm_root/ +cd llvm-capstone +git checkout auto-sync +mkdir build +cd build +# You can also build the "Release" version +cmake -G Ninja -DCMAKE_BUILD_TYPE=Debug ../llvm +cmake --build . --target llvm-tblgen --config Debug +cd ../../ +``` + +#### Install `llvm-mc` and `FileCheck` + +Additionally, we need `llvm-mc` and `FileCheck` to generate our regression tests. +You can build it, but it will take a lot of space on your hard drive. +You can also get the binaries [here](https://releases.llvm.org/download.html) or +install it with your package manager (usually something like `llvm-18-dev`). +Just ensure it is in your `PATH` as `llvm-mc` and `FileCheck` (not as `llvm-mc-18` or similar though!). + ## Architecture Please read [ARCHITECTURE.md](https://github.com/capstone-engine/capstone/blob/next/docs/ARCHITECTURE.md) to understand how Auto-Sync works. @@ -50,20 +72,6 @@ Check if your architecture is supported. ./src/autosync/ASUpdater.py -h ``` -Clone Capstones LLVM fork and build `llvm-tblgen` - -``` -git clone https://github.com/capstone-engine/llvm-capstone vendor/llvm_root/ -cd llvm-capstone -git checkout auto-sync -mkdir build -cd build -# You can also build the "Release" version -cmake -G Ninja -DCMAKE_BUILD_TYPE=Debug ../llvm -cmake --build . --target llvm-tblgen --config Debug -cd ../../ -``` - Run the updater ``` diff --git a/suite/auto-sync/c_tests/CMakeLists.txt b/suite/auto-sync/c_tests/CMakeLists.txt new file mode 100644 index 0000000000..ae54d3101a --- /dev/null +++ b/suite/auto-sync/c_tests/CMakeLists.txt @@ -0,0 +1,16 @@ +cmake_minimum_required(VERSION 3.15) + +set(AUTO_SYNC_C_TEST_SRC_DIR ${AUTO_SYNC_C_TEST_DIR}/src) +set(AUTO_SYNC_C_TEST_INC_DIR ${AUTO_SYNC_C_TEST_DIR}/include) + +include_directories(${AUTO_SYNC_C_TEST_INC_DIR} ${PROJECT_SOURCE_DIR}/include) + +file(GLOB AUTO_SYNC_C_SRC ${AUTO_SYNC_C_TEST_SRC_DIR}/*.c) +add_executable(compat_header_build_test ${AUTO_SYNC_C_SRC}) +add_dependencies(compat_header_build_test capstone) +target_link_libraries(compat_header_build_test PUBLIC capstone) + +add_test(NAME ASCompatibilityHeaderTest + COMMAND compat_header_build_test + WORKING_DIRECTORY ${AUTO_SYNC_C_TEST_DIR} +) diff --git a/suite/auto-sync/c_tests/src/test_arm64_compatibility_header.c b/suite/auto-sync/c_tests/src/test_arm64_compatibility_header.c index 4af052056f..d1ddb86440 100644 --- a/suite/auto-sync/c_tests/src/test_arm64_compatibility_header.c +++ b/suite/auto-sync/c_tests/src/test_arm64_compatibility_header.c @@ -12,7 +12,7 @@ int main(void) csh handle; if (cs_open(CS_ARCH_ARM64, CS_MODE_BIG_ENDIAN, &handle) != CS_ERR_OK) { - printf("cs_open failed\n"); + fprintf(stderr, "cs_open failed\n"); return -1; } @@ -20,21 +20,48 @@ int main(void) cs_insn *insn; uint8_t bytes[] = "0x1a,0x48,0xa0,0xf8"; - size_t count = cs_disasm(handle, bytes, sizeof(bytes), 0x1000, 1, &insn); - if (count > 0) { - printf("0x%" PRIx64 ":\t%s\t\t%s\n", insn[0].address, - insn[0].mnemonic, insn[0].op_str); - printf("A register = %s\n", cs_reg_name(handle, insn[0].detail->arm64.operands[0].reg)); - printf("An imm = 0x%" PRIx64 "\n", insn[0].detail->arm64.operands[1].imm); - - cs_free(insn, count); - } else { - printf("ERROR: Failed to disassemble given code!\n"); - cs_close(&handle); - return -1; + size_t count = + cs_disasm(handle, bytes, sizeof(bytes), 0x1000, 1, &insn); + if (count != 1) { + fprintf(stderr, "Failed to disassemble code.\n"); + goto err; } + printf("0x%" PRIx64 ":\t%s\t\t%s\n", insn[0].address, insn[0].mnemonic, + insn[0].op_str); + printf("A register = %s\n", + cs_reg_name(handle, insn[0].detail->arm64.operands[0].reg)); + printf("An imm = 0x%" PRIx64 "\n", + insn[0].detail->arm64.operands[1].imm); - cs_close(&handle); + if (insn[0].address != 0x1000) { + fprintf(stderr, "Address wrong.\n"); + goto err; + } + if (strcmp(insn[0].mnemonic, "adr") != 0) { + fprintf(stderr, "Mnemonic wrong.\n"); + goto err; + } + if (strcmp(insn[0].op_str, "x1, 0xf162d") != 0) { + fprintf(stderr, "op_str wrong.\n"); + goto err; + } + if (strcmp(cs_reg_name(handle, insn[0].detail->arm64.operands[0].reg), + "x1") != 0) { + fprintf(stderr, "register wrong.\n"); + goto err; + } + if (insn[0].detail->arm64.operands[1].imm != 0xf162d) { + fprintf(stderr, "Immediate wrong.\n"); + goto err; + } + cs_free(insn, count); + cs_close(&handle); return 0; + +err: + printf("ERROR: Failed to disassemble given code corrcetly!\n"); + cs_free(insn, count); + cs_close(&handle); + return -1; } diff --git a/suite/auto-sync/format_py.sh b/suite/auto-sync/format_py.sh index b5fc2c64f8..53e0569957 100755 --- a/suite/auto-sync/format_py.sh +++ b/suite/auto-sync/format_py.sh @@ -1,3 +1,3 @@ #!/usr/bin/bash -python3.11 -m black src/autosync +python3 -m black src/autosync diff --git a/suite/auto-sync/pyproject.toml b/suite/auto-sync/pyproject.toml index bc77298317..907d88ada2 100644 --- a/suite/auto-sync/pyproject.toml +++ b/suite/auto-sync/pyproject.toml @@ -7,15 +7,15 @@ name = "autosync" version = "0.1.0" dependencies = [ "termcolor >= 2.3.0", - "tree_sitter >= 0.21.3", + "tree_sitter == 0.22.3", "tree-sitter-cpp >=0.22.0", "black >= 24.3.0", "usort >= 1.0.8", "setuptools >= 69.2.0", "ninja >= 1.11.1.1", - "cmake >= 3.28.3", "reuse >= 3.0.1", "clang-format >= 18.1.1", + "lit >= 18.1.8", ] requires-python = ">= 3.11" diff --git a/suite/auto-sync/src/autosync/ASUpdater.py b/suite/auto-sync/src/autosync/ASUpdater.py index b88c683f61..a69803001b 100755 --- a/suite/auto-sync/src/autosync/ASUpdater.py +++ b/suite/auto-sync/src/autosync/ASUpdater.py @@ -73,7 +73,11 @@ def __init__( self.inc_list, ) self.mc_updater = MCUpdater( - self.arch, get_path("{LLVM_MC_TEST_DIR}"), None, None + self.arch, + get_path("{LLVM_MC_TEST_DIR}"), + None, + None, + True if self.arch == "ARM" else False, ) def clean_build_dir(self) -> None: @@ -192,6 +196,7 @@ def update(self) -> None: log.info(f"Copied {i} files") # MC tests + i = 0 mc_dir = get_path("{MC_DIR}").joinpath(self.arch) log.info(f"Copy MC test files to {mc_dir}") for file in get_path("{MCUPDATER_OUT_DIR}").iterdir(): diff --git a/suite/auto-sync/src/autosync/Helper.py b/suite/auto-sync/src/autosync/Helper.py index 6f7b352877..b91c1cbb82 100644 --- a/suite/auto-sync/src/autosync/Helper.py +++ b/suite/auto-sync/src/autosync/Helper.py @@ -34,8 +34,8 @@ def find_id_by_type(node: Node, node_types: [str], type_must_match: bool) -> byt """ Recursively searches for a node sequence with given node types. - A valid sequence is a path from !\f$node_n\f$ to !\f$node_{(n + |node\_types|-1)}\f$ where - !\f$\forall i \in \{0, ..., |node\_types|-1\}: type(node_{(n + i)}) = node\_types_i\f$. + A valid sequence is a path from node_n to node_{(n + |node_types|-1)} where + forall i in {0, ..., |node_types|-1}: type(node_{(n + i)}) = node_types_i. If a node sequence is found, this functions returns the text associated with the last node in the sequence. @@ -159,6 +159,11 @@ def get_path(config_path: str) -> Path: return PathVarHandler().complete_path(config_path) +def test_only_overwrite_path_var(var_name: str, new_path: Path): + """Don't use outside of testing.""" + return PathVarHandler().test_only_overwrite_var(var_name, new_path) + + def fail_exit(msg: str) -> None: """Logs a fatal message and exits with error code 1.""" log.fatal(msg) diff --git a/suite/auto-sync/src/autosync/MCUpdater.py b/suite/auto-sync/src/autosync/MCUpdater.py index b52ee6f665..afc64873c3 100755 --- a/suite/auto-sync/src/autosync/MCUpdater.py +++ b/suite/auto-sync/src/autosync/MCUpdater.py @@ -1,387 +1,449 @@ #!/usr/bin/env python3 # Copyright © 2024 Rot127 # SPDX-License-Identifier: BSD-3 + import argparse import logging as log +import json import re import sys -from enum import Enum +import subprocess as sp + from pathlib import Path +from autosync.Targets import TARGETS_LLVM_NAMING from autosync.Helper import convert_loglevel, get_path -# The CHECK prefix for tests. -VALID_PREFIX = r"(CHECK(-NEXT)?|FP[A-Z0-9]+)" -CHECK = rf"((#|//)\s*{VALID_PREFIX}:)" -ASM = r"(?P[^/@]+)" -ENC = r"(\[?(?P((0x[a-fA-F0-9]{1,2}[, ]{0,2}))+)[^, ]?\]?)" -match_patterns = { - # A commented encoding with only CHECK or something similar in front of it, skip it. - "skip_pattern": ( - rf"(^((#|//)\s*[-A-Z0-9]+):\s*{ENC}\s*$)|" r"(warning: .*)|" r"((#\s+)?NO.+)" - ), - # The encoding bytes pattern is in every file the same. - # But the disassembler and assembler tests pre-fix them differently. - # This is only the pattern for the encoding bytes. Without any prefix. - # - # The bytes are encoded with `0x` prefix and every byte is separated with a `,` or ` `. - # Optionally, they are enclosed in `[0x10,...]` brackets. - # E.g.: `[0x01,0xaa,0xb1,0x81]` or `0x01,0xaa,0xb1,0x81`. - # In the disassembler tests they don't have any prefix. - # In assembler tests they might have different prefixes like `CHECK-ENCODING` - # The matched bytes can be accessed from the group "enc_bytes" - "enc_bytes": ENC, - # Encodings in disassembly tests can have several prefixes - "enc_prefix_disas": - # start of line with CHECK: ... prefix - r"((^\s*)|" - # start of line with `CHECK: ...` prefix and the encoding after the asm text. - rf"({CHECK}.+encoding:\s+))", - # The asm checking line for `MC/Disassembler/*` tests follows the pattern: - # `# CHECK: ` - # Usually multiple 'CHECK' come before or after the encoding bytes. - # Meaning: first comes a block of `# CHECK: ...` and afterwards for every `# CHECK: ...` - # line the encoding bytes. - # And wise versa, with the encoding bytes first and afterwards the asm text checks. - # The matched asm text can be accessed from the group "asm_text" - "asm_check": rf"{CHECK}\s+{ASM}(\s*(#|//)\s+encoding:\s+{ENC})?", - # Single line disassembly test - "single_line_disas": rf"^{ENC}\s+#\s+{ASM}", - # The RUN line, with the command to run the test file, contains sometimes the `mattr` flags. - # These are relevant, because they enable or disable features we might need to - # respect in our tests as well. - # The matched `mattr` cmd line option (if any) can be accessed from the group `mattr` - "run_line": r"RUN:.*(?Pmattr=[^ ]+).+", -} - - -class Test: - def __init__(self, encoding: str | None, asm_text: str | None): - self.encoding: str | None = encoding - self.asm_text: str | None = asm_text - - def __str__(self): - self.encoding.replace(" ", ",") - self.encoding = self.encoding.strip("[]") - return f"{self.encoding} == {self.asm_text}" - - def test_complete(self) -> bool: - return self.encoding is not None and self.asm_text is not None - - def add_missing(self, encoding: str | None, asm_text: str | None): - if encoding is None and asm_text is None: - raise ValueError("One of the arguments must be set.") - if not self.encoding: - if not encoding: - raise ValueError("Test still needs the encoding but it is None.") - self.encoding = encoding - if not self.asm_text: - if not asm_text: - raise ValueError("Test still needs the asm_text but it is None.") - self.asm_text = asm_text - - -class TestManager: - """Class to manage incomplete tests. It automatically assigns the encoding and asm text - to the correct Test objects it holds. - It assumes that incomplete tests (only encoding OR the asm_text is given) - are all given in the same order. - Meaning: The first test without any asm_text but the encoding, is the same test - which is later given with only the asm_text but without encoding. - - E.g.: - Order in which tests must be given to this Manager: - - Test 1 -> (, None) - Test 2 -> (, None) - Test 3 -> (, None) - ... - - Test 1 -> (None, ) - Test 2 -> (None, ) - Test 3 -> (None, ) - ... - """ - class AddingState(Enum): - ENCODING = 0 - ASM_TEXT = 1 - UNSET = 2 - - def __init__(self): - # If set, the already added tests are completed with the given information. - self.switched = False - self.state = self.AddingState.UNSET - # List of all tests which still miss a part. - self.incomplete_tests: list[Test] = list() - # Tests which are complete - self.completed: list[Test] = list() - - def add_test(self, encoding: str | None, asm_text: str | None): - if encoding is not None and asm_text is not None: - if not ( - self.state == self.AddingState.UNSET and len(self.incomplete_tests) == 0 - ): - log.debug( - f"Complete test found. Drop incomplete {len(self.incomplete_tests)} tests" +class LLVM_MC_Command: + def __init__(self, cmd_line: str, mattr: str): + self.cmd: str = "" + self.opts: str = "" + self.file: Path | None = None + self.mattr: str = mattr + + self.cmd, self.opts, self.file = self.parse_llvm_mc_line(cmd_line) + if not (self.cmd and self.opts and self.file): + log.warning(f"Could not parse llvm-mc command: {cmd_line}") + elif not "--show-encoding" in self.cmd: + self.cmd = re.sub("llvm-mc", "llvm-mc --show-encoding", self.cmd) + + def parse_llvm_mc_line(self, line: str) -> tuple[str, str, Path]: + test_file_base_dir = str(get_path("{LLVM_LIT_TEST_DIR}").absolute()) + file = re.findall(rf"{test_file_base_dir}\S+", line) + if not file: + log.warning(f"llvm-mc command doesn't contain a file: {line}") + return None, None, None + test_file = file[0] + cmd = re.sub(rf"{test_file}", "", line).strip() + cmd = re.sub(r"\s+", " ", cmd) + arch = re.finditer(r"(triple|arch)[=\s](\S+)", cmd) + mattr = re.finditer(r"(mattr|mcpu)[=\s](\S+)", cmd) + opts = ",".join([m.group(2) for m in arch]) if arch else "" + if mattr: + opts += "" if not opts else "," + opts += ",".join([m.group(2).strip("+") for m in mattr]) + return cmd, opts, Path(test_file) + + def exec(self) -> sp.CompletedProcess: + with open(self.file, "b+r") as f: + content = f.read() + if self.mattr: + # If mattr exists, patch it into the cmd + if "mattr" in self.cmd: + self.cmd = re.sub( + r"mattr[=\s]+", f"mattr={self.mattr} -mattr=", self.cmd ) - self.reset_incomplete() - self.state = self.AddingState.UNSET - self.completed.append(Test(encoding, asm_text)) - return - - if self.state == self.AddingState.UNSET: - assert len(self.incomplete_tests) == 0 - # Add the first incomplete test - if encoding and asm_text: - self.state = self.AddingState.UNSET - elif encoding: - self.state = self.AddingState.ENCODING else: - self.state = self.AddingState.ASM_TEXT - - # Check if we complete the already added tests - if (self.state == self.AddingState.ENCODING and encoding is None) or ( - self.state == self.AddingState.ASM_TEXT and asm_text is None - ): - self.switched = True - oldstate = self.state - self.state = ( - self.AddingState.ENCODING - if self.state == self.AddingState.ASM_TEXT - else self.AddingState.ASM_TEXT - ) - log.debug(f"switch {oldstate} -> {self.state}") + self.cmd = re.sub(r"llvm-mc", f"llvm-mc -mattr={self.mattr}", self.cmd) + + log.debug(f"Run: {self.cmd}") + result = sp.run(self.cmd.split(" "), input=content, capture_output=True) + return result + + def get_opts_list(self) -> list[str]: + opts = self.opts.strip().strip(",") + opts = re.sub(r"[, ]+", ",", opts) + return opts.split(",") + + def __str__(self) -> str: + return f"{self.cmd} < {str(self.file.absolute())}" + - if self.switched: - log.debug(f"Add incomplete II: {encoding} {asm_text}") - test = self.incomplete_tests.pop(0) - test.add_missing(encoding, asm_text) - self.completed.append(test) +class MCTest: + """ + A single test. It can contain multiple decoded instruction for a given byte sequence. + In general a MCTest always tests a sequence of instructions in a single .text segment. + """ + + def __init__(self, arch: str, opts: list[str], encoding: str, asm_text: str): + self.arch = arch + if arch.lower() in ["arm", "powerpc", "ppc", "aarch64"]: + # Arch and PPC require this option for MC tests. + self.opts = ["CS_OPT_NO_BRANCH_OFFSET"] + opts else: - log.debug(f"Add incomplete I: {encoding} {asm_text}") - self.incomplete_tests.append(Test(encoding, asm_text)) - - # Lastly check if we can reset. - if len(self.incomplete_tests) == 0: - # All tests are completed. Reset - self.state = self.AddingState.UNSET - self.switched = False - log.debug(f"Reset: {self.state}") - - def check_all_complete(self) -> bool: - if len(self.incomplete_tests) != 0: - log.debug(f"We have {len(self.incomplete_tests)} incomplete tests.") - return False - return True - - def get_completed(self) -> list[Test]: - return self.completed - - def get_stats(self) -> str: - return ( - f"completed: {len(self.completed)} incomplete: {len(self.incomplete_tests)}" - ) + self.opts = opts + self.encoding: list[str] = [encoding] + self.asm_text: list[str] = [asm_text] - def get_num_completed(self) -> int: - return len(self.completed) + def extend(self, encoding: str, asm_text: str): + self.encoding.append(encoding) + self.asm_text.append(asm_text) - def get_num_incomplete(self) -> int: - return len(self.incomplete_tests) + def __str__(self): + encoding = ",".join(self.encoding) + encoding = re.sub(r"[\[\]]", "", encoding) + encoding = encoding.strip() + encoding = re.sub(r"[\s,]+", ", ", encoding) + yaml_tc = ( + " -\n" + " input:\n" + " bytes: [ ]\n" + ' arch: ""\n' + " options: [ ]\n" + " expected:\n" + " insns:\n" + ) + template = " -\n asm_text: \n" + insn_cases = "" + for text in self.asm_text: + insn_cases += template.replace("", f'"{text}"') - def reset_incomplete(self): - self.incomplete_tests.clear() - self.state = self.AddingState.UNSET - self.switched = False + yaml_tc = yaml_tc.replace("", encoding) + yaml_tc = yaml_tc.replace("", f"CS_ARCH_{self.arch.upper()}") + yaml_tc = yaml_tc.replace("", ", ".join([f'"{o}"' for o in self.opts])) + yaml_tc += insn_cases + return yaml_tc class TestFile: def __init__( - self, arch: str, filename: str, manager: TestManager, mattrs: list[str] | None + self, + arch: str, + file_path: Path, + opts: list[str] | None, + mc_cmd: LLVM_MC_Command, + unified_test_cases: bool, ): - self.arch = arch - self.filename = filename - self.manager = manager - self.mattrs: list[str] = list() if not mattrs else mattrs - self.tests = list() - - def add_mattr(self, mattr: str): - if not self.mattrs: - self.mattrs = list() - if mattr not in self.mattrs: - self.mattrs.append(mattr) + self.arch: str = arch + self.file_path: Path = file_path + self.opts: list[str] = list() if not opts else opts + self.mc_cmd: LLVM_MC_Command = mc_cmd + # Indexed by .text section count + self.tests: dict[int : list[MCTest]] = dict() + + self.init_tests(unified_test_cases) + + def init_tests(self, unified_test_cases: bool): + mc_output = self.mc_cmd.exec() + if mc_output.stderr and not mc_output.stdout: + # We can still continue. We just ignore the failed cases. + log.debug(f"llvm-mc cmd stderr: {mc_output.stderr}") + log.debug(f"llvm-mc result: {mc_output}") + text_section = 0 # Counts the .text sections + asm_pat = f"(?P.+)" + enc_pat = r"(\[?(?P(?P((0x[a-fA-F0-9]{1,2}[, ]{0,2}))+)[^, ]?)\]?)" + for line in mc_output.stdout.splitlines(): + line = line.decode("utf8") + if ".text" in line: + text_section += 1 + continue + match = re.search( + rf"^\s*{asm_pat}\s*(#|//|@)\s*encoding:\s*{enc_pat}", line + ) + if not match: + continue + full_enc_string = match.group("full_enc_string") + if not re.search(r"0x[a-fA-F0-9]{1,2}$", full_enc_string[:-1]): + log.debug(f"Ignore because symbol injection is needed: {line}") + # The encoding string contains symbol information of the form: + # [0xc0,0xe0,A,A,A... or similar. We ignore these for now. + continue + enc_bytes = match.group("enc_bytes").strip() + asm_text = match.group("asm_text").strip() + asm_text = re.sub(r"\t+", " ", asm_text) + asm_text = asm_text.strip() + if not self.valid_byte_seq(enc_bytes): + continue - def add_tests(self, tests: list[Test]): - self.tests = tests + if text_section in self.tests: + if unified_test_cases: + self.tests[text_section][0].extend(enc_bytes, asm_text) + else: + self.tests[text_section].append( + MCTest(self.arch, self.opts, enc_bytes, asm_text) + ) + else: + self.tests[text_section] = [ + MCTest(self.arch, self.opts, enc_bytes, asm_text) + ] def has_tests(self) -> bool: return len(self.tests) != 0 - def get_cs_testfile_content(self) -> str: - old_mc_test_file = get_path("{MC_DIR}").joinpath( - f"{self.arch}/{self.filename}.cs" - ) - if not old_mc_test_file.exists(): - header = ( - f"# CS_ARCH_{self.arch.upper()}, None, None\n" - "# This regression test file is new. The option flags could not be determined.\n" - f"# LLVM uses the following mattr = {self.mattrs}" - ) - else: - with open(old_mc_test_file) as f: - init_line = f.readlines()[0] - assert init_line != "" and "# CS_ARCH_" in init_line - header = init_line - - content = header + "\n" - for test in self.tests: - content += f"{test}\n" + def get_cs_testfile_content(self, only_test: bool) -> str: + content = "\n" if only_test else "test_cases:\n" + for tl in self.tests.values(): + content += "\n".join([str(t) for t in tl]) return content + def num_test_cases(self) -> int: + return len(self.tests) + + def valid_byte_seq(self, enc_bytes): + match self.arch: + case "AArch64": + # It always needs 4 bytes. + # Otherwise it is likely a reloc or symbol test + return enc_bytes.count("0x") == 4 + case _: + return True + + def get_multi_mode_filename(self) -> Path: + filename = self.file_path.stem + parent = self.file_path.parent + detailed_name = f"{filename}_{'_'.join(self.opts)}.txt" + detailed_name = re.sub(r"[+-]", "_", detailed_name) + out_path = parent.joinpath(detailed_name) + return Path(out_path) + + def get_simple_filename(self) -> Path: + return self.file_path + + def __lt__(self, other) -> bool: + return str(self.file_path) < str(other.file_path) + class MCUpdater: + """ + The MCUpdater parses all test files of the LLVM MC regression tests. + Each of those LLVM files can contain several llvm-mc commands to run on the same file. + Mostly this is done to test the same file with different CPU features enabled. + So it can test different flavors of assembly etc. + + In Capstone all modules enable always all CPU features (even if this is not + possible in reality). + Due to this we always parse all llvm-mc commands run on a test file, generate a TestFile + object for each of it, but only write the last one of them to disk. + Once https://github.com/capstone-engine/capstone/issues/1992 is resolved, we can + write all variants of a test file to disk. + + This is already implemented and tested with multi_mode = True. + """ + def __init__( self, arch: str, mc_dir: Path, excluded: list[str] | None, included: list[str] | None, + unified_test_cases: bool, + multi_mode: bool = False, ): + self.symbolic_links = list() self.arch = arch + self.test_dir_link_prefix = f"test_dir_{arch}_" self.mc_dir = mc_dir self.excluded = excluded if excluded else list() self.included = included if included else list() - self.test_files: dict[str:TestFile] = dict() + self.test_files: list[TestFile] = list() + self.unified_test_cases = unified_test_cases + with open(get_path("{MCUPDATER_CONFIG_FILE}")) as f: + self.conf = json.loads(f.read()) + # Additional mattr passed to llvm-mc + self.mattr: str = ( + ",".join(self.conf["additional_mattr"][self.arch]) + if self.arch in self.conf["additional_mattr"] + else "" + ) + # A list of options which are always added. + self.mandatory_options: str = ( + self.conf["mandatory_options"][self.arch] + if self.arch in self.conf["mandatory_options"] + else list() + ) + self.multi_mode = multi_mode - def parse_file(self, filepath: Path) -> TestFile | None: - """Parse a MC test file and return it as an object with all tests found. - If it couldn't parse the file cleanly, it prints errors but returns it anyways. + def check_prerequisites(self, paths): + for path in paths: + if not path.exists() or not path.is_dir(): + raise ValueError( + f"'{path}' does not exits or is not a directory. Cannot generate tests from there." + ) + llvm_lit_cfg = get_path("{LLVM_LIT_TEST_DIR}") + if not llvm_lit_cfg.exists(): + raise ValueError( + f"Could not find '{llvm_lit_cfg}'. Check {{LLVM_LIT_TEST_DIR}} in path_vars.json." + ) + + def write_to_build_dir(self): + file_cnt = 0 + test_cnt = 0 + overwritten = 0 + files_written = set() + for test in sorted(self.test_files): + if not test.has_tests(): + continue + file_cnt += 1 + test_cnt += test.num_test_cases() + + if self.multi_mode: + rel_path = str( + test.get_multi_mode_filename().relative_to( + get_path("{LLVM_LIT_TEST_DIR}") + ) + ) + else: + rel_path = str( + test.get_simple_filename().relative_to( + get_path("{LLVM_LIT_TEST_DIR}") + ) + ) + + filename = re.sub(rf"{self.test_dir_link_prefix}\d+", ".", rel_path) + filename = get_path("{MCUPDATER_OUT_DIR}").joinpath(f"{filename}.yaml") + if filename in files_written: + write_mode = "a" + else: + write_mode = "w+" + filename.parent.mkdir(parents=True, exist_ok=True) + if self.multi_mode and filename.exists(): + raise ValueError( + f"The following file exists already: {filename}\n" + "This is not allowed in multi-mode." + ) + else: + log.debug(f"Overwrite: {filename}") + overwritten += 1 + with open(filename, write_mode) as f: + f.write(test.get_cs_testfile_content(only_test=(write_mode == "a"))) + log.debug(f"Write {filename}") + files_written.add(filename) + log.info( + f"Processed {file_cnt} files with {test_cnt} test cases. Generated {len(files_written)} files" + ) + if overwritten > 0: + log.warning( + f"Overwrote {overwritten} test files with the same name.\n" + f"These files contain instructions of several different cpu features.\n" + f"You have to use multi-mode to write them into distinct files.\n" + f"The current setting will only keep the last one written.\n" + f"See also: https://github.com/capstone-engine/capstone/issues/1992" + ) + + def build_test_files(self, mc_cmds: list[LLVM_MC_Command]) -> list[TestFile]: + log.info("Build TestFile objects") + test_files = list() + n_all = len(mc_cmds) + for i, mcc in enumerate(mc_cmds): + print(f"{i + 1}/{n_all} {mcc.file.name}", flush=True, end="\r") + test_files.append( + TestFile( + self.arch, + mcc.file, + mcc.get_opts_list() + self.mandatory_options, + mcc, + self.unified_test_cases, + ) + ) + return test_files + + def run_llvm_lit(self, paths: list[Path]) -> list[LLVM_MC_Command]: + """ + Calls llvm-lit with the given paths to the tests. + It parses the llvm-lit commands to LLVM_MC_Commands. """ - with open(filepath) as f: - lines = f.readlines() - - test_file = TestFile(self.arch, filepath.name, TestManager(), None) - manager = test_file.manager - for line in lines: - if line == "\n": - # New line means new block starts. Drop all incomplete tests. - log.debug("New line. Drop all incomplete tests") - test_file.manager.reset_incomplete() + lit_cfg_dir = get_path("{LLVM_LIT_TEST_DIR}") + llvm_lit_cfg = str(lit_cfg_dir.absolute()) + args = ["lit", "-v", "-a", llvm_lit_cfg] + for i, p in enumerate(paths): + slink = lit_cfg_dir.joinpath(f"{self.test_dir_link_prefix}{i}") + self.symbolic_links.append(slink) + log.debug(f"Create link: {slink} -> {p}") try: - if mattr := self.get_mattr(line): - test_file.add_mattr(mattr) - continue - encoding, asm_text = self.get_enc_asm(line) - if not encoding and not asm_text: - continue - manager.add_test(encoding, asm_text) - except ValueError as e: + slink.symlink_to(p, target_is_directory=True) + except FileExistsError as e: + print("Failed: Link existed. Please delete it") raise e - log.debug(f"Failed to parse {test_file.filename}. Skipping it") - return None - - manager.check_all_complete() - test_file.add_tests(manager.get_completed()) - log.debug(f"Parsed {manager.get_num_completed()} tests:\t{filepath.name}") - return test_file - - @staticmethod - def get_mattr(line: str) -> str | None: - match = re.search(match_patterns["run_line"], line) - if not match or not match.group("mattr"): - return None - return match.group("mattr") - - @staticmethod - def get_enc_asm(line: str) -> tuple[str | None, str | None]: - enc: str | None = None - asm_text: str | None = None - if re.search(match_patterns["skip_pattern"], line): - return None, None - # Check for single line tests - single_match = re.search(match_patterns["single_line_disas"], line) - if single_match: - return ( - single_match.group("enc_bytes"), - single_match.group("asm_text").strip(), - ) - asm_match = re.search(match_patterns["asm_check"], line) - if asm_match: - asm_text = asm_match.group("asm_text") - if asm_match.group("enc_bytes"): - # Single line test - enc = asm_match.group("enc_bytes") - if asm_text: - asm_text = asm_text.strip() - # A single line test. Return the result - if asm_text and enc: - return enc, asm_text - - # Check if the line contains at least encoding bytes - pattern = rf"{match_patterns['enc_prefix_disas']}{match_patterns['enc_bytes']}" - enc_match = re.search(pattern, line) - if enc_match: - enc = enc_match.group("enc_bytes") - - return enc, asm_text - - def gen_tests_in_dir(self, curr_dir: Path) -> list[str]: - """Generate testcases from the files in the given dir. - Returns a list of files which failed to parse. - """ - fails = list() - for file in curr_dir.iterdir(): - if file.is_dir(): - self.gen_tests_in_dir(file) - continue - if len(self.included) != 0 and not any( - re.search(x, file.name) is not None for x in self.included + log.info(f"Run lit: {' '.join(args)}") + cmds = sp.run(args, capture_output=True) + if cmds.stderr: + raise ValueError(f"llvm-lit failed with {cmds.stderr}") + return self.extract_llvm_mc_cmds(cmds.stdout.decode("utf8")) + + def extract_llvm_mc_cmds(self, cmds: str) -> list[LLVM_MC_Command]: + log.debug("Parsing llvm-mc commands") + # Get only the RUN lines which have a show-encoding set. + cmd_lines = cmds.splitlines() + log.debug(f"NO FILTER: {cmd_lines}") + matches = list( + filter( + lambda l: ( + l + if re.search(r"^RUN.+(show-encoding|disassemble)[^|]+", l) + else None + ), + cmd_lines, + ) + ) + log.debug(f"FILTER RUN: {' '.join(matches)}") + # Don't add tests which are allowed to fail + matches = list( + filter(lambda m: None if re.search(r"not\s+llvm-mc", m) else m, matches) + ) + log.debug(f"FILTER not llvm-mc: {' '.join(matches)}") + # Skip object file tests + matches = list( + filter(lambda m: None if re.search(r"filetype=obj", m) else m, matches) + ) + log.debug(f"FILTER filetype=obj-mc: {' '.join(matches)}") + # Skip any relocation related tests. + matches = filter(lambda m: None if re.search(r"reloc", m) else m, matches) + # Remove 'RUN: at ...' prefix + matches = map(lambda m: re.sub(r"^RUN: at line \d+: ", "", m), matches) + # Remove redirection + matches = map(lambda m: re.sub(r"\d>&\d", "", m), matches) + # Remove unused arguments + matches = map(lambda m: re.sub(r"-o\s?-", "", m), matches) + # Remove redirection of stderr to a file + matches = map(lambda m: re.sub(r"2>\s?\S+", "", m), matches) + # Remove piping to FileCheck + matches = map(lambda m: re.sub(r"\|\s*FileCheck\s+.+", "", m), matches) + # Remove input stream + matches = map(lambda m: re.sub(r"\s+<", "", m), matches) + + all_cmds = list() + for match in matches: + if self.included and not any( + re.search(x, match) is not None for x in self.included ): continue - if any(re.search(x, file.name) is not None for x in self.excluded): + if any(re.search(x, match) is not None for x in self.excluded): continue - if test_file := self.parse_file(curr_dir.joinpath(file)): - self.test_files[file.name] = test_file - else: - fails.append(file.name) - return fails + llvm_mc_cmd = LLVM_MC_Command(match, self.mattr) + if not llvm_mc_cmd.cmd: + # Invalid + continue + all_cmds.append(llvm_mc_cmd) + log.debug(f"Added: {llvm_mc_cmd}") + log.debug(f"Extracted {len(all_cmds)} llvm-mc commands") + return all_cmds def gen_all(self): - log.info("Generate MC regression tests") - assembly_tests = self.mc_dir.joinpath(f"{self.arch}") + log.info("Check prerequisites") disas_tests = self.mc_dir.joinpath(f"Disassembler/{self.arch}") - if not disas_tests.exists() or not disas_tests.is_dir(): - raise ValueError( - f"'{disas_tests}' does not exits or is not a directory. Cannot generate tests from there." - ) - if not assembly_tests.exists() or not assembly_tests.is_dir(): - raise ValueError( - f"'{assembly_tests}' does not exits or is not a directory. Cannot generate tests from there." - ) - - fails = self.gen_tests_in_dir(disas_tests) - fails.extend(self.gen_tests_in_dir(assembly_tests)) - sum_tests = sum([len(tf.tests) for tf in self.test_files.values()]) - log.info( - f"Parse {len(self.test_files)} MC test files with a total of {sum_tests} tests." - ) - if fails: - log.warning("The following files failed to parse:") - for f in fails: - log.warning(f"\t{f}") + test_paths = [disas_tests] + self.check_prerequisites(test_paths) + log.info("Generate MC regression tests") + llvm_mc_cmds = self.run_llvm_lit(test_paths) + log.info(f"Got {len(llvm_mc_cmds)} llvm-mc commands to run") + self.test_files = self.build_test_files(llvm_mc_cmds) + for slink in self.symbolic_links: + log.debug(f"Unlink {slink}") + slink.unlink() self.write_to_build_dir() - def write_to_build_dir(self): - for filename, test in self.test_files.items(): - if not test.has_tests(): - continue - with open( - get_path("{MCUPDATER_OUT_DIR}").joinpath(f"{filename}.cs"), "w+" - ) as f: - f.write(test.get_cs_testfile_content()) - log.debug(f"Write {filename}") - def parse_args() -> argparse.Namespace: parser = argparse.ArgumentParser( @@ -399,7 +461,7 @@ def parse_args() -> argparse.Namespace: "-a", dest="arch", help="Name of architecture to update.", - choices=["ARM", "PowerPC", "AArch64", "LoongArch"], + choices=TARGETS_LLVM_NAMING, required=True, ) parser.add_argument( @@ -416,6 +478,13 @@ def parse_args() -> argparse.Namespace: nargs="+", help="Specific list of file names to update (can be a regex pattern).", ) + parser.add_argument( + "-u", + dest="unified_tests", + action="store_true", + default=False, + help="If set, all instructions of a text segment will decoded and tested at once. Should be set, if instructions depend on each other.", + ) parser.add_argument( "-v", dest="verbosity", @@ -437,5 +506,9 @@ def parse_args() -> argparse.Namespace: ) MCUpdater( - args.arch, args.mc_dir, args.excluded_files, args.included_files + args.arch, + args.mc_dir, + args.excluded_files, + args.included_files, + args.unified_tests, ).gen_all() diff --git a/suite/auto-sync/src/autosync/PathVarHandler.py b/suite/auto-sync/src/autosync/PathVarHandler.py index a973f84dcf..df5f83627c 100644 --- a/suite/auto-sync/src/autosync/PathVarHandler.py +++ b/suite/auto-sync/src/autosync/PathVarHandler.py @@ -71,6 +71,13 @@ def __init__(self) -> None: log.fatal(f"\t{m}") exit(1) + def test_only_overwrite_var(self, var_name: str, new_path: Path): + if var_name not in self.paths: + raise ValueError(f"PathVarHandler doesn't have a path for '{var_name}'") + if not new_path.exists(): + raise ValueError(f"New path doesn't exists: '{new_path}") + self.paths[var_name] = new_path + def get_path(self, name: str) -> Path: if name not in self.paths: raise ValueError(f"Path variable {name} has no path saved.") diff --git a/suite/auto-sync/src/autosync/Targets.py b/suite/auto-sync/src/autosync/Targets.py new file mode 100644 index 0000000000..d3dfdd1c5a --- /dev/null +++ b/suite/auto-sync/src/autosync/Targets.py @@ -0,0 +1,4 @@ +# Copyright © 2024 Rot127 +# SPDX-License-Identifier: BSD-3 + +TARGETS_LLVM_NAMING = ["ARM", "PowerPC", "Alpha", "AArch64", "LoongArch"] diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/test_a.txt b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/test_a.txt new file mode 100644 index 0000000000..6cbdbb6ac5 --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/test_a.txt @@ -0,0 +1,34 @@ +# RUN: llvm-mc -triple=aarch64 -mattr=+v8a,+fp-armv8 -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=+v8.2a -disassemble < %s | FileCheck %s --check-prefix=CHECK-V82 + +#------------------------------------------------------------------------------ +# Compare and branch (immediate) +#------------------------------------------------------------------------------ + +# CHECK: sbfx x1, x2, #3, #2 +# CHECK: asr x3, x4, #63 +# CHECK: asr wzr, wzr, #31 +# CHECK: sbfx w12, w9, #0, #1 +0x41 0x10 0x43 0x93 +0x83 0xfc 0x7f 0x93 +0xff 0x7f 0x1f 0x13 +0x2c 0x1 0x0 0x13 + +# CHECK: ubfiz x4, x5, #52, #11 +# CHECK: ubfx xzr, x4, #0, #1 +# CHECK: ubfiz x4, xzr, #1, #6 +# CHECK: lsr x5, x6, #12 +0xa4 0x28 0x4c 0xd3 +0x9f 0x0 0x40 0xd3 +0xe4 0x17 0x7f 0xd3 +0xc5 0xfc 0x4c 0xd3 + +# CHECK: bfi x4, x5, #52, #11 +# CHECK: bfxil xzr, x4, #0, #1 +# CHECK: bfi x4, xzr, #1, #6 +# CHECK-V82: bfc x4, #1, #6 +# CHECK: bfxil x5, x6, #12, #52 +0xa4 0x28 0x4c 0xb3 +0x9f 0x0 0x40 0xb3 +0xe4 0x17 0x7f 0xb3 +0xc5 0xfc 0x4c 0xb3 diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/test_b.txt b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/test_b.txt new file mode 100644 index 0000000000..8aa3152ae6 --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/test_b.txt @@ -0,0 +1,9 @@ +# The RUN line parsing +# RUN: llvm-mc --disassemble -triple=arm64 < %s | FileCheck %s + + +[0x00,0x0a,0x31,0xd5] +# CHECK: mrs x0, TRCRSR + +[0x80,0x08,0x31,0xd5] +# CHECK: mrs x0, TRCEXTINSELR diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/test_no_symbol.s.txt b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/test_no_symbol.s.txt new file mode 100644 index 0000000000..428b7535a7 --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/test_no_symbol.s.txt @@ -0,0 +1,41 @@ +# RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=z13 --show-encoding %s | FileCheck %s + +# RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=z13 -filetype=obj %s | \ +# RUN: llvm-readobj -r - | FileCheck %s -check-prefix=CHECK-REL + +# RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=z13 -filetype=obj %s | \ +# RUN: llvm-objdump -d - | FileCheck %s -check-prefix=CHECK-DIS + +# CHECK: larl %r14, target # encoding: [0xc0,0xe0,A,A,A,A] +# CHECK-NEXT: # fixup A - offset: 2, value: target+2, kind: FK_390_PC32DBL +# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_PC32DBL target 0x2 + .align 16 + larl %r14, target + +# CHECK: larl %r14, target@GOT # encoding: [0xc0,0xe0,A,A,A,A] +# CHECK-NEXT: # fixup A - offset: 2, value: target@GOT+2, kind: FK_390_PC32DBL +# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_GOTENT target 0x2 + .align 16 + larl %r14, target@got + +# CHECK: vl %v0, src(%r1) # encoding: [0xe7,0x00,0b0001AAAA,A,0x00,0x06] +# CHECK-NEXT: # fixup A - offset: 2, value: src, kind: FK_390_U12Imm +# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 src 0x0 + .align 16 + vl %v0, src(%r1) + + +# CHECK: .insn ss,238594023227392,dst(%r2,%r1),src,%r3 # encoding: [0xd9,0x23,0b0001AAAA,A,0b0000BBBB,B] +# CHECK-NEXT: # fixup A - offset: 2, value: dst, kind: FK_390_U12Imm +# CHECK-NEXT: # fixup B - offset: 4, value: src, kind: FK_390_U12Imm +# CHECK-REL: 0x{{[0-9A-F]*2}} R_390_12 dst 0x0 +# CHECK-REL: 0x{{[0-9A-F]*4}} R_390_12 src 0x0 + .align 16 + .insn ss,0xd90000000000,dst(%r2,%r1),src,%r3 # mvck + +##S8 +# CHECK: asi 0(%r1), src # encoding: [0xeb,A,0x10,0x00,0x00,0x6a] +# CHECK-NEXT: # fixup A - offset: 1, value: src, kind: FK_390_S8Imm +# CHECK-REL: 0x{{[0-9A-F]+}} R_390_8 src 0x0 + .align 16 + asi 0(%r1),src diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/separated/test_a.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/separated/test_a.txt.yaml new file mode 100644 index 0000000000..abc0c29711 --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/separated/test_a.txt.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x41, 0x10, 0x43, 0x93 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbfx x1, x2, #3, #2" + + - + input: + bytes: [ 0x83, 0xfc, 0x7f, 0x93 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr x3, x4, #63" + + - + input: + bytes: [ 0xff, 0x7f, 0x1f, 0x13 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr wzr, wzr, #31" + + - + input: + bytes: [ 0x2c, 0x01, 0x00, 0x13 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbfx w12, w9, #0, #1" + + - + input: + bytes: [ 0xa4, 0x28, 0x4c, 0xd3 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ubfiz x4, x5, #52, #11" + + - + input: + bytes: [ 0x9f, 0x00, 0x40, 0xd3 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ubfx xzr, x4, #0, #1" + + - + input: + bytes: [ 0xe4, 0x17, 0x7f, 0xd3 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ubfiz x4, xzr, #1, #6" + + - + input: + bytes: [ 0xc5, 0xfc, 0x4c, 0xd3 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr x5, x6, #12" + + - + input: + bytes: [ 0xa4, 0x28, 0x4c, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfi x4, x5, #52, #11" + + - + input: + bytes: [ 0x9f, 0x00, 0x40, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfxil xzr, x4, #0, #1" + + - + input: + bytes: [ 0xe4, 0x17, 0x7f, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfi x4, xzr, #1, #6" + + - + input: + bytes: [ 0xc5, 0xfc, 0x4c, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfxil x5, x6, #12, #52" + + - + input: + bytes: [ 0x41, 0x10, 0x43, 0x93 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "sbfx x1, x2, #3, #2" + + - + input: + bytes: [ 0x83, 0xfc, 0x7f, 0x93 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "asr x3, x4, #63" + + - + input: + bytes: [ 0xff, 0x7f, 0x1f, 0x13 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "asr wzr, wzr, #31" + + - + input: + bytes: [ 0x2c, 0x01, 0x00, 0x13 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "sbfx w12, w9, #0, #1" + + - + input: + bytes: [ 0xa4, 0x28, 0x4c, 0xd3 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "ubfiz x4, x5, #52, #11" + + - + input: + bytes: [ 0x9f, 0x00, 0x40, 0xd3 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "ubfx xzr, x4, #0, #1" + + - + input: + bytes: [ 0xe4, 0x17, 0x7f, 0xd3 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "ubfiz x4, xzr, #1, #6" + + - + input: + bytes: [ 0xc5, 0xfc, 0x4c, 0xd3 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "lsr x5, x6, #12" + + - + input: + bytes: [ 0xa4, 0x28, 0x4c, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "bfi x4, x5, #52, #11" + + - + input: + bytes: [ 0x9f, 0x00, 0x40, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "bfxil xzr, x4, #0, #1" + + - + input: + bytes: [ 0xe4, 0x17, 0x7f, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "bfc x4, #1, #6" + + - + input: + bytes: [ 0xc5, 0xfc, 0x4c, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "bfxil x5, x6, #12, #52" diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/separated/test_b.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/separated/test_b.txt.yaml new file mode 100644 index 0000000000..16cf14af77 --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/separated/test_b.txt.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x0a, 0x31, 0xd5 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64" ] + expected: + insns: + - + asm_text: "mrs x0, TRCRSR" + + - + input: + bytes: [ 0x80, 0x08, 0x31, 0xd5 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64" ] + expected: + insns: + - + asm_text: "mrs x0, TRCEXTINSELR" diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/unified/test_a.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/unified/test_a.txt.yaml new file mode 100644 index 0000000000..243d98623a --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/unified/test_a.txt.yaml @@ -0,0 +1,64 @@ +test_cases: + - + input: + bytes: [ 0x41, 0x10, 0x43, 0x93, 0x83, 0xfc, 0x7f, 0x93, 0xff, 0x7f, 0x1f, 0x13, 0x2c, 0x01, 0x00, 0x13, 0xa4, 0x28, 0x4c, 0xd3, 0x9f, 0x00, 0x40, 0xd3, 0xe4, 0x17, 0x7f, 0xd3, 0xc5, 0xfc, 0x4c, 0xd3, 0xa4, 0x28, 0x4c, 0xb3, 0x9f, 0x00, 0x40, 0xb3, 0xe4, 0x17, 0x7f, 0xb3, 0xc5, 0xfc, 0x4c, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbfx x1, x2, #3, #2" + - + asm_text: "asr x3, x4, #63" + - + asm_text: "asr wzr, wzr, #31" + - + asm_text: "sbfx w12, w9, #0, #1" + - + asm_text: "ubfiz x4, x5, #52, #11" + - + asm_text: "ubfx xzr, x4, #0, #1" + - + asm_text: "ubfiz x4, xzr, #1, #6" + - + asm_text: "lsr x5, x6, #12" + - + asm_text: "bfi x4, x5, #52, #11" + - + asm_text: "bfxil xzr, x4, #0, #1" + - + asm_text: "bfi x4, xzr, #1, #6" + - + asm_text: "bfxil x5, x6, #12, #52" + + - + input: + bytes: [ 0x41, 0x10, 0x43, 0x93, 0x83, 0xfc, 0x7f, 0x93, 0xff, 0x7f, 0x1f, 0x13, 0x2c, 0x01, 0x00, 0x13, 0xa4, 0x28, 0x4c, 0xd3, 0x9f, 0x00, 0x40, 0xd3, 0xe4, 0x17, 0x7f, 0xd3, 0xc5, 0xfc, 0x4c, 0xd3, 0xa4, 0x28, 0x4c, 0xb3, 0x9f, 0x00, 0x40, 0xb3, 0xe4, 0x17, 0x7f, 0xb3, 0xc5, 0xfc, 0x4c, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "sbfx x1, x2, #3, #2" + - + asm_text: "asr x3, x4, #63" + - + asm_text: "asr wzr, wzr, #31" + - + asm_text: "sbfx w12, w9, #0, #1" + - + asm_text: "ubfiz x4, x5, #52, #11" + - + asm_text: "ubfx xzr, x4, #0, #1" + - + asm_text: "ubfiz x4, xzr, #1, #6" + - + asm_text: "lsr x5, x6, #12" + - + asm_text: "bfi x4, x5, #52, #11" + - + asm_text: "bfxil xzr, x4, #0, #1" + - + asm_text: "bfc x4, #1, #6" + - + asm_text: "bfxil x5, x6, #12, #52" diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/unified/test_b.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/unified/test_b.txt.yaml new file mode 100644 index 0000000000..914ce4bad7 --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/unified/test_b.txt.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x0a, 0x31, 0xd5, 0x80, 0x08, 0x31, 0xd5 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64" ] + expected: + insns: + - + asm_text: "mrs x0, TRCRSR" + - + asm_text: "mrs x0, TRCEXTINSELR" diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/separated/test_a_aarch64_v8a__fp_armv8.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/separated/test_a_aarch64_v8a__fp_armv8.txt.yaml new file mode 100644 index 0000000000..f44613e360 --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/separated/test_a_aarch64_v8a__fp_armv8.txt.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x41, 0x10, 0x43, 0x93 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbfx x1, x2, #3, #2" + + - + input: + bytes: [ 0x83, 0xfc, 0x7f, 0x93 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr x3, x4, #63" + + - + input: + bytes: [ 0xff, 0x7f, 0x1f, 0x13 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr wzr, wzr, #31" + + - + input: + bytes: [ 0x2c, 0x01, 0x00, 0x13 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbfx w12, w9, #0, #1" + + - + input: + bytes: [ 0xa4, 0x28, 0x4c, 0xd3 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ubfiz x4, x5, #52, #11" + + - + input: + bytes: [ 0x9f, 0x00, 0x40, 0xd3 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ubfx xzr, x4, #0, #1" + + - + input: + bytes: [ 0xe4, 0x17, 0x7f, 0xd3 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ubfiz x4, xzr, #1, #6" + + - + input: + bytes: [ 0xc5, 0xfc, 0x4c, 0xd3 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr x5, x6, #12" + + - + input: + bytes: [ 0xa4, 0x28, 0x4c, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfi x4, x5, #52, #11" + + - + input: + bytes: [ 0x9f, 0x00, 0x40, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfxil xzr, x4, #0, #1" + + - + input: + bytes: [ 0xe4, 0x17, 0x7f, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfi x4, xzr, #1, #6" + + - + input: + bytes: [ 0xc5, 0xfc, 0x4c, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfxil x5, x6, #12, #52" diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/separated/test_a_arm64_v8.2a.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/separated/test_a_arm64_v8.2a.txt.yaml new file mode 100644 index 0000000000..4702ca3fd2 --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/separated/test_a_arm64_v8.2a.txt.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x41, 0x10, 0x43, 0x93 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "sbfx x1, x2, #3, #2" + + - + input: + bytes: [ 0x83, 0xfc, 0x7f, 0x93 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "asr x3, x4, #63" + + - + input: + bytes: [ 0xff, 0x7f, 0x1f, 0x13 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "asr wzr, wzr, #31" + + - + input: + bytes: [ 0x2c, 0x01, 0x00, 0x13 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "sbfx w12, w9, #0, #1" + + - + input: + bytes: [ 0xa4, 0x28, 0x4c, 0xd3 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "ubfiz x4, x5, #52, #11" + + - + input: + bytes: [ 0x9f, 0x00, 0x40, 0xd3 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "ubfx xzr, x4, #0, #1" + + - + input: + bytes: [ 0xe4, 0x17, 0x7f, 0xd3 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "ubfiz x4, xzr, #1, #6" + + - + input: + bytes: [ 0xc5, 0xfc, 0x4c, 0xd3 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "lsr x5, x6, #12" + + - + input: + bytes: [ 0xa4, 0x28, 0x4c, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "bfi x4, x5, #52, #11" + + - + input: + bytes: [ 0x9f, 0x00, 0x40, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "bfxil xzr, x4, #0, #1" + + - + input: + bytes: [ 0xe4, 0x17, 0x7f, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "bfc x4, #1, #6" + + - + input: + bytes: [ 0xc5, 0xfc, 0x4c, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "bfxil x5, x6, #12, #52" diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/separated/test_b_arm64.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/separated/test_b_arm64.txt.yaml new file mode 100644 index 0000000000..16cf14af77 --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/separated/test_b_arm64.txt.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x0a, 0x31, 0xd5 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64" ] + expected: + insns: + - + asm_text: "mrs x0, TRCRSR" + + - + input: + bytes: [ 0x80, 0x08, 0x31, 0xd5 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64" ] + expected: + insns: + - + asm_text: "mrs x0, TRCEXTINSELR" diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/unified/test_a_aarch64_v8a__fp_armv8.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/unified/test_a_aarch64_v8a__fp_armv8.txt.yaml new file mode 100644 index 0000000000..1ee32dd8aa --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/unified/test_a_aarch64_v8a__fp_armv8.txt.yaml @@ -0,0 +1,32 @@ +test_cases: + - + input: + bytes: [ 0x41, 0x10, 0x43, 0x93, 0x83, 0xfc, 0x7f, 0x93, 0xff, 0x7f, 0x1f, 0x13, 0x2c, 0x01, 0x00, 0x13, 0xa4, 0x28, 0x4c, 0xd3, 0x9f, 0x00, 0x40, 0xd3, 0xe4, 0x17, 0x7f, 0xd3, 0xc5, 0xfc, 0x4c, 0xd3, 0xa4, 0x28, 0x4c, 0xb3, 0x9f, 0x00, 0x40, 0xb3, 0xe4, 0x17, 0x7f, 0xb3, 0xc5, 0xfc, 0x4c, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "aarch64", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbfx x1, x2, #3, #2" + - + asm_text: "asr x3, x4, #63" + - + asm_text: "asr wzr, wzr, #31" + - + asm_text: "sbfx w12, w9, #0, #1" + - + asm_text: "ubfiz x4, x5, #52, #11" + - + asm_text: "ubfx xzr, x4, #0, #1" + - + asm_text: "ubfiz x4, xzr, #1, #6" + - + asm_text: "lsr x5, x6, #12" + - + asm_text: "bfi x4, x5, #52, #11" + - + asm_text: "bfxil xzr, x4, #0, #1" + - + asm_text: "bfi x4, xzr, #1, #6" + - + asm_text: "bfxil x5, x6, #12, #52" diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/unified/test_a_arm64_v8.2a.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/unified/test_a_arm64_v8.2a.txt.yaml new file mode 100644 index 0000000000..bad3cb31d8 --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/unified/test_a_arm64_v8.2a.txt.yaml @@ -0,0 +1,32 @@ +test_cases: + - + input: + bytes: [ 0x41, 0x10, 0x43, 0x93, 0x83, 0xfc, 0x7f, 0x93, 0xff, 0x7f, 0x1f, 0x13, 0x2c, 0x01, 0x00, 0x13, 0xa4, 0x28, 0x4c, 0xd3, 0x9f, 0x00, 0x40, 0xd3, 0xe4, 0x17, 0x7f, 0xd3, 0xc5, 0xfc, 0x4c, 0xd3, 0xa4, 0x28, 0x4c, 0xb3, 0x9f, 0x00, 0x40, 0xb3, 0xe4, 0x17, 0x7f, 0xb3, 0xc5, 0xfc, 0x4c, 0xb3 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64", "v8.2a" ] + expected: + insns: + - + asm_text: "sbfx x1, x2, #3, #2" + - + asm_text: "asr x3, x4, #63" + - + asm_text: "asr wzr, wzr, #31" + - + asm_text: "sbfx w12, w9, #0, #1" + - + asm_text: "ubfiz x4, x5, #52, #11" + - + asm_text: "ubfx xzr, x4, #0, #1" + - + asm_text: "ubfiz x4, xzr, #1, #6" + - + asm_text: "lsr x5, x6, #12" + - + asm_text: "bfi x4, x5, #52, #11" + - + asm_text: "bfxil xzr, x4, #0, #1" + - + asm_text: "bfc x4, #1, #6" + - + asm_text: "bfxil x5, x6, #12, #52" diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/unified/test_b_arm64.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/unified/test_b_arm64.txt.yaml new file mode 100644 index 0000000000..914ce4bad7 --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/unified/test_b_arm64.txt.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x0a, 0x31, 0xd5, 0x80, 0x08, 0x31, 0xd5 ] + arch: "CS_ARCH_ARCH" + options: [ "arm64" ] + expected: + insns: + - + asm_text: "mrs x0, TRCRSR" + - + asm_text: "mrs x0, TRCEXTINSELR" diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/test_a.txt b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/test_a.txt deleted file mode 100644 index 4e3379f721..0000000000 --- a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/test_a.txt +++ /dev/null @@ -1,78 +0,0 @@ -# Test simple disassembly decoding tests - -# The RUN line parsing -# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s | FileCheck %s -# RUN: llvm-mc -triple=arm64 -mattr=+crc -disassemble < %s | FileCheck %s - - -[0x00,0x0a,0x31,0xd5] -# CHECK: mrs x0, TRCRSR - -[0x80,0x08,0x31,0xd5] -# CHECK: mrs x0, TRCEXTINSELR - -[0x80,0x09,0x31,0xd5] -# CHECK: mrs x0, TRCEXTINSELR1 - -# Now a block of instruction tests - -[0x41,0x01,0x00,0x19] -[0x41,0x01,0x10,0x19] -[0x62,0xf1,0x0f,0x19] -[0xe3,0xd3,0x1f,0x19] -#CHECK: stlurb w1, [x10] -#CHECK-NEXT: stlurb w1, [x10, #-256] -#CHECK-NEXT: stlurb w2, [x11, #255] -#CHECK-NEXT: stlurb w3, [sp, #-3] - -# Now the other way around defined - -# CHECK: crc32b w5, w7, w20 -//CHECK: crc32h w28, wzr, w30 -# CHECK: crc32w w0, w1, w2 -// CHECK: crc32x w7, w9, x20 -# CHECK: crc32cb w9, w5, w4 -#CHECK: crc32ch w13, w17, w25 -# CHECK: crc32cw wzr, w3, w5 -# CHECK: crc32cx w18, w16, xzr -0xe5 0x40 0xd4 0x1a -0xfc 0x47 0xde 0x1a -0x20 0x48 0xc2 0x1a -0x27 0x4d 0xd4 0x9a -0xa9 0x50 0xc4 0x1a -0x2d 0x56 0xd9 0x1a -0x7f 0x58 0xc5 0x1a -0x12 0x5e 0xdf 0x9a - -# Now one line tests - -# CHECK-NEXT: mrs x0, AMCG1IDR_EL0 // encoding: [0xc0,0xd2,0x3b,0xd5] -// CHECK-NEXT: msr AMEVCNTVOFF00_EL2, x0 // encoding: [0x00,0xd8,0x1c,0xd5] -// CHECK: msr AMEVCNTVOFF00_EL2, x0 // encoding: [0x00,0xd8,0x1c,0xd5] - -# Annoying case. The last CHECK: should not be matched. - -[0x20,0x84,0xc2,0x6e] # sqrdmlah v0.2d, v1.2d, v2.2d -[0x20,0x8c,0xc2,0x6e] # sqrdmlsh v0.2d, v1.2d, v2.2d -# CHECK: warning: invalid instruction encoding -# CHECK: [0x20,0x84,0x02,0x2e] - - -[0x62,0xfc,0x44,0x2e] -[0x62,0xfc,0x44,0x6e] -# Dont' parse this: -# NOBF16: warning: invalid instruction encoding -# NOBF16-NEXT: [0x62,0xfc,0x44,0x2e] -# NOBF16: warning: invalid instruction encoding -# NOBF16-NEXT: [0x62,0xfc,0x44,0x6e] -NOBF16-NEXT: [0x62,0xfc,0x44,0x2e] -# But this please. It belongs to the encding above -# CHECK: bfdot v2.2s, v3.4h, v4.4h -# CHECK: bfdot v2.4s, v3.8h, v4.8h - -# Single digit hex numbers - -# CHECK: svc #0 -# CHECK: svc #{{65535|0xffff}} -0x1 0x0 0x0 0xd4 -0xe1 0xff 0x1f 0xd4 diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/test_a.txt.cs b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/test_a.txt.cs deleted file mode 100644 index a36dc2b50b..0000000000 --- a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/test_a.txt.cs +++ /dev/null @@ -1,27 +0,0 @@ -# CS_ARCH_ARCH, None, None -# This regression test file is new. The option flags could not be determined. -# LLVM uses the following mattr = ['mattr=+v8.1a', 'mattr=+crc'] -0x00,0x0a,0x31,0xd5 == mrs x0, TRCRSR -0x80,0x08,0x31,0xd5 == mrs x0, TRCEXTINSELR -0x80,0x09,0x31,0xd5 == mrs x0, TRCEXTINSELR1 -0x41,0x01,0x00,0x19 == stlurb w1, [x10] -0x41,0x01,0x10,0x19 == stlurb w1, [x10, #-256] -0x62,0xf1,0x0f,0x19 == stlurb w2, [x11, #255] -0xe3,0xd3,0x1f,0x19 == stlurb w3, [sp, #-3] -0xe5 0x40 0xd4 0x1a == crc32b w5, w7, w20 -0xfc 0x47 0xde 0x1a == crc32h w28, wzr, w30 -0x20 0x48 0xc2 0x1a == crc32w w0, w1, w2 -0x27 0x4d 0xd4 0x9a == crc32x w7, w9, x20 -0xa9 0x50 0xc4 0x1a == crc32cb w9, w5, w4 -0x2d 0x56 0xd9 0x1a == crc32ch w13, w17, w25 -0x7f 0x58 0xc5 0x1a == crc32cw wzr, w3, w5 -0x12 0x5e 0xdf 0x9a == crc32cx w18, w16, xzr -0xc0,0xd2,0x3b,0xd5 == mrs x0, AMCG1IDR_EL0 -0x00,0xd8,0x1c,0xd5 == msr AMEVCNTVOFF00_EL2, x0 -0x00,0xd8,0x1c,0xd5 == msr AMEVCNTVOFF00_EL2, x0 -0x20,0x84,0xc2,0x6e == sqrdmlah v0.2d, v1.2d, v2.2d -0x20,0x8c,0xc2,0x6e == sqrdmlsh v0.2d, v1.2d, v2.2d -0x62,0xfc,0x44,0x2e == bfdot v2.2s, v3.4h, v4.4h -0x62,0xfc,0x44,0x6e == bfdot v2.4s, v3.8h, v4.8h -0x1 0x0 0x0 0xd4 == svc #0 -0xe1 0xff 0x1f 0xd4 == svc #{{65535|0xffff}} diff --git a/suite/auto-sync/src/autosync/Tests/test_mcupdater.py b/suite/auto-sync/src/autosync/Tests/test_mcupdater.py index 34c42ee429..eefa205179 100644 --- a/suite/auto-sync/src/autosync/Tests/test_mcupdater.py +++ b/suite/auto-sync/src/autosync/Tests/test_mcupdater.py @@ -1,10 +1,13 @@ # SPDX-FileCopyrightText: 2024 Rot127 # SPDX-License-Identifier: BSD-3 + import logging +import os import sys import unittest +from pathlib import Path -from autosync.Helper import get_path +from autosync.Helper import get_path, test_only_overwrite_path_var from autosync.MCUpdater import MCUpdater @@ -17,43 +20,173 @@ def setUpClass(cls): format="%(levelname)-5s - %(message)s", force=True, ) - cls.updater = MCUpdater( - "ARCH", get_path("{MCUPDATER_TEST_DIR}"), [r".*\.cs"], None + + def test_test_case_gen(self): + """ + To enforce sequential execution of the tests, we execute them in here. + And don't make them a separated test. + """ + self.assertTrue(self.unified_test_cases(), "Failed: unified_test_cases") + self.assertTrue(self.separated_test_cases(), "Failed: separated_test_cases") + self.assertTrue( + self.multi_mode_unified_test_cases(), + "Failed: multi_mode_unified_test_cases", + ) + self.assertTrue( + self.multi_mode_separated_test_cases(), + "Failed: multi_mode_separated_test_cases", ) - def test_parsing(self): - self.updater.included.append("test_a.txt") - self.updater.gen_tests_in_dir(self.updater.mc_dir) - self.assertEqual(len(self.updater.test_files), 1) - self.assertListEqual( - self.updater.test_files["test_a.txt"].mattrs, ["mattr=+v8.1a", "mattr=+crc"] + def unified_test_cases(self): + out_dir = Path( + get_path("{MCUPDATER_TEST_OUT_DIR}").joinpath("merged").joinpath("unified") ) - self.assertEqual(len(self.updater.test_files["test_a.txt"].tests), 24) - self.assertEqual( - self.updater.test_files["test_a.txt"].manager.get_num_incomplete(), 0 + if not out_dir.exists(): + out_dir.mkdir(parents=True) + for file in out_dir.iterdir(): + logging.debug(f"Delete old file: {file}") + os.remove(file) + test_only_overwrite_path_var( + "{MCUPDATER_OUT_DIR}", + out_dir, ) - with open(get_path("{MCUPDATER_TEST_DIR}").joinpath("test_a.txt.cs")) as f: - correct = f.read() - self.assertEqual( - correct, self.updater.test_files["test_a.txt"].get_cs_testfile_content() + self.updater = MCUpdater("ARCH", get_path("{MCUPDATER_TEST_DIR}"), [], [], True) + self.updater.gen_all() + return self.compare_files(out_dir, ["test_a.txt.yaml", "test_b.txt.yaml"]) + + def separated_test_cases(self): + out_dir = Path( + get_path("{MCUPDATER_TEST_OUT_DIR}") + .joinpath("merged") + .joinpath("separated") + ) + if not out_dir.exists(): + out_dir.mkdir(parents=True) + for file in out_dir.iterdir(): + logging.debug(f"Delete old file: {file}") + os.remove(file) + test_only_overwrite_path_var( + "{MCUPDATER_OUT_DIR}", + out_dir, + ) + self.updater = MCUpdater( + "ARCH", get_path("{MCUPDATER_TEST_DIR}"), [], [], False ) + self.updater.gen_all() + return self.compare_files(out_dir, ["test_a.txt.yaml", "test_b.txt.yaml"]) - def test_adding_header_from_mc(self): + def multi_mode_unified_test_cases(self): + out_dir = Path( + get_path("{MCUPDATER_TEST_OUT_DIR}").joinpath("multi").joinpath("unified") + ) + if not out_dir.exists(): + out_dir.mkdir(parents=True) + for file in out_dir.iterdir(): + logging.debug(f"Delete old file: {file}") + os.remove(file) + test_only_overwrite_path_var( + "{MCUPDATER_OUT_DIR}", + out_dir, + ) self.updater = MCUpdater( - arch="ARM", - mc_dir=get_path("{MCUPDATER_TEST_DIR}"), - excluded=[r".*\.cs"], - included=None, - ) - self.updater.gen_tests_in_dir(self.updater.mc_dir) - self.assertEqual(len(self.updater.test_files), 3) - self.assertListEqual(self.updater.test_files["cps.s"].mattrs, []) - self.assertEqual(len(self.updater.test_files["cps.s"].tests), 1) - self.assertEqual( - self.updater.test_files["cps.s"].manager.get_num_incomplete(), 0 - ) - with open(get_path("{MCUPDATER_TEST_DIR}").joinpath("cps.s.cs")) as f: - correct = f.read() - self.assertEqual( - correct, self.updater.test_files["cps.s"].get_cs_testfile_content() + "ARCH", get_path("{MCUPDATER_TEST_DIR}"), [], [], True, multi_mode=True + ) + self.updater.gen_all() + return self.compare_files( + out_dir, + [ + "test_a_aarch64_v8a__fp_armv8.txt.yaml", + "test_a_arm64_v8.2a.txt.yaml", + "test_b_arm64.txt.yaml", + ], + ) + + def multi_mode_separated_test_cases(self): + out_dir = Path( + get_path("{MCUPDATER_TEST_OUT_DIR}").joinpath("multi").joinpath("separated") + ) + if not out_dir.exists(): + out_dir.mkdir(parents=True) + for file in out_dir.iterdir(): + logging.debug(f"Delete old file: {file}") + os.remove(file) + test_only_overwrite_path_var( + "{MCUPDATER_OUT_DIR}", + out_dir, ) + self.updater = MCUpdater( + "ARCH", get_path("{MCUPDATER_TEST_DIR}"), [], [], False, multi_mode=True + ) + self.updater.gen_all() + return self.compare_files( + out_dir, + [ + "test_a_aarch64_v8a__fp_armv8.txt.yaml", + "test_a_arm64_v8.2a.txt.yaml", + "test_b_arm64.txt.yaml", + ], + ) + + def test_no_symbol_tests(self): + out_dir = Path(get_path("{MCUPDATER_TEST_OUT_DIR}").joinpath("no_symbol")) + if not out_dir.exists(): + out_dir.mkdir(parents=True) + for file in out_dir.iterdir(): + logging.debug(f"Delete old file: {file}") + os.remove(file) + test_only_overwrite_path_var( + "{MCUPDATER_OUT_DIR}", + out_dir, + ) + self.updater = MCUpdater( + "ARCH", + get_path("{MCUPDATER_TEST_DIR}"), + [], + [], + False, + ) + self.updater.gen_all() + self.assertFalse( + out_dir.joinpath("test_no_symbol.s.txt.yaml").exists(), + "File should not exist", + ) + + def compare_files(self, out_dir: Path, filenames: list[str]) -> bool: + if not out_dir.is_dir(): + logging.error(f"{out_dir} is not a directory.") + return False + + parent_name = out_dir.parent.name + expected_dir = ( + get_path("{MCUPDATER_TEST_DIR_EXPECTED}") + .joinpath(parent_name) + .joinpath(out_dir.name) + ) + if not expected_dir.exists() or not expected_dir.is_dir(): + logging.error(f"{expected_dir} is not a directory.") + return False + for file in filenames: + efile = expected_dir.joinpath(file) + if not efile.exists(): + logging.error(f"{efile} does not exist") + return False + with open(efile) as f: + logging.debug(f"Read {efile}") + expected = f.read() + + afile = out_dir.joinpath(file) + if not afile.exists(): + logging.error(f"{afile} does not exist") + return False + with open(afile) as f: + logging.debug(f"Read {afile}") + actual = f.read() + if expected != actual: + logging.error("Files mismatch") + print(f"Expected: {efile}") + print(f"Actual: {afile}\n") + print(f"Expected:\n\n{expected}\n") + print(f"Actual:\n\n{actual}\n") + return False + logging.debug(f"OK: actual == expected") + return True diff --git a/suite/auto-sync/src/autosync/cpptranslator/Differ.py b/suite/auto-sync/src/autosync/cpptranslator/Differ.py index 03aef025e4..8cc2a39ad0 100755 --- a/suite/auto-sync/src/autosync/cpptranslator/Differ.py +++ b/suite/auto-sync/src/autosync/cpptranslator/Differ.py @@ -851,6 +851,10 @@ def check_saved_patches(self): filename, node_id = self.all_choices_saved( old_filepath, new_file[k]["nodes"], old_file[k]["nodes"] ) + if not node_id: + # Edge case of file has all nodes matching. And therefore has + # no decision saved because the user never was asked. + continue if filename or node_id: print( f"{get_path('{DIFFER_PERSISTENCE_FILE}').name} is not up-to-date!\n" @@ -918,7 +922,7 @@ def parse_args() -> argparse.Namespace: "-a", dest="arch", help="Name of target architecture (ignored with -t option)", - choices=["ARM", "PPC", "AArch64", "Alpha"], + choices=["ARM", "PPC", "AArch64", "Alpha", "LoongArch"], required=True, ) parser.add_argument( diff --git a/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json b/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json index 8fe03810d4..ba5380dd0f 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json +++ b/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json @@ -1,2379 +1,2411 @@ { - "ARMDisassembler.c": { - "AddThumb1SBit": { + "AArch64Disassembler.c": { + "\"AArch64GenInstrInfo.inc\"": { "apply_type": "OLD", - "old_hash": "e16fd83b02dc4539a153f003f89ecd789699e8c689212e8a051fd7dfd71515be", - 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"new_hash": "6713eccf00c4127a96b8147da41c2eb7d8d91896dedd7ff01f97b6b8c91ab492", + "old_hash": "08109600525dbe56f3fa90e7f30d6b489b889f650efcc158378f952bd5cb1531", + "new_hash": "d5b6473a7ae44c2b6b4719e02496312eec0a8943814c9ba6fc6f3ef363e054c0", "edit": "" }, - "ARM_AM_getVMOVModImmVal": { + "DecodeBankedReg": { "apply_type": "OLD", - "old_hash": "b7e474123c49f78fc16b20a129d160ebd473d5a5e00a0ca8dd91834e94d602f8", - "new_hash": "cb1525c3552784d93be28f8330c116273df1685eb7ed974edb744d32621a1dee", + "old_hash": "8f0dc5c9b1ebbe5d34e7e49d3d298951885bc05583ec16cf6e6ecdd96d0ce12e", + "new_hash": "09fe278cb0491368bd73c4947277f95b0432d61f47f5ad082615414159149212", "edit": "" }, - "ARM_AM_isNEONBytesplat": { + "DecodeCopMemInstruction": { "apply_type": "OLD", - "old_hash": "8332f2fd86baed5a2427550d62ee833cd3c6054a99a4cef38e7fba2e2d889c6b", - "new_hash": "53190f9c11fc5a7e0c1e38474b72156d69c5b3893d538a4c76d090e6f6034a0a", + "old_hash": "de10bfb4efaf077a24827f5e6437c4b5478c8916c064a392ea697c8361eacd07", + "new_hash": "c68d236650331f6a54cc6100c3f48ee5f8908e9b10897a8af794817b01f8a2a5", "edit": "" }, - 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} - }, - "ARMBaseInfo.c": { - "ARMSysReg_lookupMClassSysRegAPSRNonDeprecated": { + }, + "DecodePredicateOperand": { "apply_type": "OLD", - "old_hash": "", - "new_hash": "46a413e3efb1147c7f53e9bfca46a008b1e674743af943a919aa9da3a621a24e", + "old_hash": "58ddc2d7f52d45ea3ccd0856bbcd7f32d136a24c8196b258be92c4eed6a0bd28", + "new_hash": "777e16b280bf44870e23e1c841318c7e5482f4f5461ecff030757652bbcf4e2a", "edit": "" }, - "ARMSysReg_lookupMClassSysRegBy12bitSYSmValue": { + "DecodeRegListOperand": { "apply_type": "OLD", - "old_hash": "", - "new_hash": "faa313843f323f690e2b7d068f4c73ddfd02a855c6929b974cfe5619ac5bf77f", + "old_hash": "98f3f08ea7ab1be3c3bd753dd28f5f99976881c5abc5df88bb694bc1a3804c22", + "new_hash": "198f27e7978abc81e58089e9fb5b5bb3cf74e183cd46bbe7d86f831aa7f66adf", "edit": "" }, - "ARMSysReg_lookupMClassSysRegBy8bitSYSmValue": { + "DecodeSORegMemOperand": { "apply_type": "OLD", - "old_hash": "", - "new_hash": "a742d04516ad454bbae24b897a8446be964c2fe94d69c8bfd70e1049042c990b", + "old_hash": "b2227c76cd763f0dc348043ade36236489c8997d988f73ee86b6a4e7cfa406e1", + "new_hash": "5b48e3c244940fd13918bd34ac445a4054088259e4a6fd891a95afbaabd717f4", "edit": "" }, - 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"lookupMClassSysRegAPSRNonDeprecated": { + "DecodeT2SOImm": { "apply_type": "OLD", - "old_hash": "b424a3c3bb4fd75e9e0cdb11fd783c942519fa25fe31e930fde1e033bc7c695a", - "new_hash": "", + "old_hash": "47594759546172ee88b4ce5b088bff8d315903e0d4068196c5869eda95bb6a3a", + "new_hash": "cbe6d50c0c012cee271bfede1bce414d73851440d87fb71a3790e91ae759e039", "edit": "" }, - "lookupMClassSysRegBy12bitSYSmValue": { + "DecodeThumbBLXOffset": { "apply_type": "OLD", - "old_hash": "eea213a2863c54ffa542d667b376919e4a1b8094f3f41cf950e9a1cc2fd73b1c", - "new_hash": "", + "old_hash": "de0f984972ddfaa3edf04e8347315b6624525522d85885f689afc8fa5c3239ee", + "new_hash": "e42325ddadd6f84c7a56277fc61e6f879160c0a250a19601d58ff48fb2afc9e2", "edit": "" }, - "lookupMClassSysRegBy8bitSYSmValue": { + "DecodeVPTMaskOperand": { "apply_type": "OLD", - "old_hash": "544a8a7ac86577daa605ad976141d8166491017176b0e3a73d2e79581dff8501", - "new_hash": "", + "old_hash": "9e9be3cb7845da6d4c5336797421aa92210188b23ee73cf5154e4d851a2ffd49", + "new_hash": "5f831a1b9cee232e5c667e2b95bcada8f5d2e10e56e5f27cfe904a9830f7f339", "edit": "" }, - "\"ARMBaseInfo.h\"": { + "DecodeVpredNOperand": { "apply_type": "OLD", - "old_hash": "c2628208478c4f7d6c48f4657e7cf14e1f896657f8370938b8c438ca5517c45f", - "new_hash": "2be2e93095820dd9bd4b4974e4568fb2c45c8f7401a92553fc0e222812889efa", + "old_hash": "", + "new_hash": "a84ee46adfefbc0d1fdab9c6f5324a9bb324c1a122ac4ac502827240a6230e86", "edit": "" }, - "\"ARMGenSystemRegister.inc\"": { + "DecoderForMRRC2AndMCRR2": { "apply_type": "OLD", - "old_hash": "76a3d513fb74a9c14aaf369a2e41e6692dcb2ea64984e6430e7be44b72c8cbc3", - "new_hash": "", + "old_hash": "6951fd79b5390c810eedaaf7b903b3b29eb212d155791af226e47c8478c50a21", + "new_hash": "dc9e397cd6b2d69c635e535a753364c3d43507bc5c7410fb2246df10ff4d0c1d", "edit": "" }, - "\"ARMMapping.h\"": { + "UpdateThumbVFPPredicate": { "apply_type": "OLD", - "old_hash": "e010fe7fc5dbf57e7bdcec6beec5538edecf8fa40f2426bf12d2b37fff5cde57", - "new_hash": "", + "old_hash": "f3c01f859c405a12b7db109afe3a70854a923a9b7473fbd6fbed0248feea74fa", + "new_hash": "0e92a16b350185abea1aa073bff5fe5a03b3394dd842700b5f11251b50605a4a", "edit": "" - } - }, - "PPCDisassembler.c": { - "DEFINE_decodeSImmOperand": { + }, + "checkDecodedInstruction": { "apply_type": "OLD", - "old_hash": "f82506a3702d696d8550d29eb9381c63cb493c6668705b8717563b353c61199d", - "new_hash": "6ef5acbc7cb8f9ca5194b0ac8fd7aecceeb820180598e19964081f00136648bf", + "old_hash": "89be7681c295f7309a4d4840f3d651a1cd8c0ae47930aa38ddf31cbcac09cc31", + "new_hash": "5ac65fb3a6939b724f963c7a0f1fd196ce91b82972b1b4e6754bf626ca7db83d", "edit": "" }, - "DecodeQFRCRegisterClass": { + "createARMDisassembler": { "apply_type": "OLD", - "old_hash": "8a27cd3e61e6668c274cab496a5fa7041b19fa728e9243d985a73da4de93f675", - "new_hash": "", + "old_hash": "", + "new_hash": "606ce64d2ffb7388277a2167d951b14bec44db29d7fcba17c19c5eea0f6e4f58", "edit": "" }, - "PPC_LLVM_getInstruction": { + "endianSensitiveOpcode16": { "apply_type": "OLD", - "old_hash": "9826020ad71dc7e08c2986de1b30ad57ab2f62bf03c0faae937261ca4593c62e", + "old_hash": "62d92f7c8bac5715e5d6b4a5f24d9db2bf4bbe65908df8db065f21d6acc9f3b3", "new_hash": "", "edit": "" }, - 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"printU10ImmOperand": { + "printFBits16": { "apply_type": "OLD", - "old_hash": "329c2bb4576258a16cde9a6bddb56c6c2aab830af5ef81685e13d780c5d718a8", - "new_hash": "efed5cb256c3fd8ad1da010aa116f265b5af3c0395b48a685bed05208664f84e", + "old_hash": "b0482329e694f34c699bbd6e464417fbdd348fd7a000ab375411c8fac5f01b95", + "new_hash": "5d67d2312505ebb26c996b8ad69103ab68d95553c58d1121781bf06b4f1c7127", "edit": "" }, - "printU12ImmOperand": { + "printFBits32": { "apply_type": "OLD", - "old_hash": "d2c328eca98550f32ee46a015308f0ab5d1d7bffaebe26e14397654db9bfaa56", - "new_hash": "a1157724f4d2a16a74034a724ce3da71386c8b6bcb1aec3107a85bc9b070499e", + "old_hash": "cf8b1fbec5f2523b933028dd0ed39912d4783035d79522e79c718fd05639a67d", + "new_hash": "a5fd6f698da980b74803e7d70e9e34a67a02037c6f784f7df361f04eba2b58ba", "edit": "" }, - "printU16ImmOperand": { + "printFPImmOperand": { "apply_type": "OLD", - "old_hash": "1ccae5f6b81085142313d7b34cb3b8d76b727143846aa09dea1be7996165ebcd", - "new_hash": "96b3c068fcc34315cb98869940c52b7fcc53c4ab97db7d8e6d04a0bc28f49494", + "old_hash": "f145952b34b4c7651b5ec4b42e5ca351f39f386d5cb7bc31e238b50626fd089c", + "new_hash": "d8e1d8d1c222437dc7ef4fecb2d8e810923871ca819c73fe63cc4db2de8e3b6f", "edit": "" }, - "printU1ImmOperand": { + "printImmPlusOneOperand": { "apply_type": "OLD", - "old_hash": "2ec13a0fa3a425f9318c6e66f81d0a4b1311926b3b47f26b797c983abb8e9b06", - "new_hash": "14add063ba02ca135e9ab95af77248c9410c0ed05ae40d1d9da36c5a895017d1", + "old_hash": "ec1dafafd60de21c0a274d68812f99e12f0baaff5067f184e4374ff2b37a28f7", + "new_hash": "eb5a91897ddd33f62104f816588f84282aa3d90fa8a69d38ef345a861c7e497e", "edit": "" }, - "printU2ImmOperand": { + "printInst": { "apply_type": "OLD", - "old_hash": "b5b1fab385df93dc26707cae3815f59d5f5613f79477c0ea28e049683a6326f2", - "new_hash": "1bdd4fc7273c4fa743ba3332d3f45460150b89bf2da7c5c5f57ce4e7aa7d7ce0", + "old_hash": "3032c82a512aee24413d9ea498609749ff006cbc3a4ca5fd38141b221c34c61a", + "new_hash": "ed5337f98a7ad8a23ff50efc09fb1d937af30124d5489524fec3855015d831b2", "edit": "" }, - "printU3ImmOperand": { + "printLdStmModeOperand": { "apply_type": "OLD", - "old_hash": "31a78dedd0eab05c4ccc59c2d7473b6e19a220e29e39c0b6970277c9da597ed3", - "new_hash": "4a985f3277a9233344b93606a6ff52730ffaf7b39917b9ac4bba5caabedcaaf6", + "old_hash": "e0915e25965812eeba03a18b081c60a258b0b8009af3d98774da71324a26a91f", + "new_hash": "a6f788b71bc47f9aabcc567c2d00777e2725732f07a5b515bca08501fde9c796", "edit": "" }, - "printU4ImmOperand": { + "printMSRMaskOperand": { "apply_type": "OLD", - "old_hash": "b5da847a59417586de4c4dd58690c5a4d8e23db832994e8ac22e52c419d1d99f", - "new_hash": "784c9cd8868d7ad6b227fbe0ff91924862ffdb29af2f39ad89f48efeb78b91e3", + "old_hash": "36b8784994fcdbcf324f7d85f58656adacbb82e53406de60cc8dccb0da757b50", + "new_hash": "fe94465767c783435dcd121e8f84437a67a7c1219daf566178059567e9d295b6", "edit": "" }, - "printU5ImmOperand": { + "printMemBOption": { "apply_type": "OLD", - "old_hash": "04fc13f1ccfb0b361c17ed3eed0f4a188d580eb02e9cf533c60e0f902c9d5308", - "new_hash": "a082ee91177d93645b19098fda0c2a34110f4b54253f2050fe2558eef44135e8", + "old_hash": "d2ac567c8e4947b8a7189783a6b1d4659f8186471c2f8458801af60ccea51240", + "new_hash": "83efbcd369ce2d8abce14dabbe6b9620c7a7bde228f15955718cb41c168c353c", "edit": "" }, - "printU6ImmOperand": { + "printModImmOperand": { "apply_type": "OLD", - "old_hash": "85cf7076d9a8cca621968d357d4b77f0f3836a9bf032e3e2ae9f68c444931607", - "new_hash": "7819971c0d52699284edfed676084e9aa48c7e693b949edaae936feafeb5f832", + "old_hash": "1788c640009cc9e48d624b96019c445aeb1346e5d8ce7f5cd9376bf03ce84d7a", + "new_hash": "03c0c913a770fd7dabc604d8c1c6dc8a06fe2afaa3fdf9c798d521c6c99f3948", "edit": "" }, - "printU7ImmOperand": { + "printMveSaturateOp": { "apply_type": "OLD", - "old_hash": "3bda685d7d6ed4f550dd02d0b8b098687e66ff3ed9151328ec8362b9deed7bfe", - "new_hash": "c13555c7693c7aa52a0edc3e7af16f82ace9a13dd4fa8c8ccdba49c94a6193ed", + "old_hash": "19041125e884b3bcfdebd4a88c316dbff6ed17637baac100fc35681db10f3346", + "new_hash": "8daaad36c055497f8ba1ebb559fd65c427fec3c74576d6c216a9fac73e784835", "edit": "" }, - "printU8ImmOperand": { + "printNoHashImmediate": { "apply_type": "OLD", - "old_hash": "a38744403d5221940825b10a5f6c42d430c5be4ef1d2f49d82231893a0239f31", - "new_hash": "76830ed242e9f7ec8d48f4119f14350016bf43378015821af6be3f9452bd29dd", + "old_hash": "5eca0dcad4b6a9556639c1e27d56eafd7148cc22ff5c44dcb86d39b322cae69e", + "new_hash": "6ba021d35466d081b88b56b2e6d8920533c77885bb8b7eaa8185b0c026c00396", "edit": "" }, - "printcrbitm": { + "printOperand": { "apply_type": "OLD", - "old_hash": "ed93ddcf6f973cc7eb12d1b898e5a9299a2885dbe53f73f63672b793d7c18bde", - "new_hash": "6aef7937ccfd4055a6af7f1ca9851761a6173c9be62204340bb70830bd1bb326", + "old_hash": "40455b1543c1df57c63397d1f01e955be51c97a10149ee4ad3c4e982833d89f4", + "new_hash": "", "edit": "" }, - "showRegistersWithPercentPrefix": { + "printOperandAddr": { "apply_type": "OLD", - "old_hash": "8f5d37257fdb23ebaeff1baa4877a074baa8208c6ec6e08d9dcc99c3cba87248", - "new_hash": "e8454aec44c50d6a4fa18cbdc38d5d2b49a7d0a8f35ab64a826127b90decb818", + "old_hash": "6731ee5b725c31f0ffa5bd0efd912c031f18e5407c4161ff972f17c4c9d797b7", + "new_hash": "", "edit": "" }, - "showRegistersWithPrefix": { + "printPCLabel": { "apply_type": "OLD", - "old_hash": "4d9a4c310c0f65f5266028c8ba3efed35e25397b53028dafa87032ab16c5e4e6", - "new_hash": "823ac915ff5e36aef0221553c4251b4e0ea96a896587b79b3f3394893ee82bed", + "old_hash": "9fed7969e83fad1c33bee6c48ecf4c24d475d84e8cb42858f6bddc6237c951e1", + "new_hash": "ade84eb1a15afb848ef6613ecc22dd9635c287961d68284954e0d80da13af5bb", "edit": "" - } - }, - "PPCInstPrinter.h": { - "\"PPCMCTargetDesc.h\"": { + }, + "printPImmediate": { "apply_type": "OLD", - "old_hash": "321933e4a3b33bab5e97c6c12212d63428777290b52cfde3ea7089f2d11edd10", - "new_hash": "c00944cd062db89032103615e00d70bcc12d9ee37f4a5df8109d7e25881c7967", + "old_hash": "f0aeba64412d7ace872e047ebc9e674415f5a5828d0b131b4ad0b51746165b6c", + "new_hash": "682ddf037f5302a3a5b0b0b84181f1a90ed7ccf475e68142f11a6496624238fc", "edit": "" - } - }, - "PPCMCTargetDesc.h": { - "\"PPCGenInstrInfo.inc\"": { + }, + "printPKHASRShiftImm": { "apply_type": "OLD", - "old_hash": "ec36362bfa2667dd75c36bf9dbf9da9ae58fde9414045ed779f2da859b86f90f", - "new_hash": "", + "old_hash": "71d2c4b54a4593979975483eb0b1235c7e98ff8279b2bb0e10628b5323021062", + "new_hash": "f810bcad5c2a91153bb142e6d4a89c7ce5c33b8296179e8e0f16cee6bb656670", "edit": "" }, - "\"PPCGenRegisterInfo.inc\"": { + "printPKHLSLShiftImm": { "apply_type": "OLD", - "old_hash": "ae8b462c1a17f021435477f80cb5003126e3176688674ecae32ea1ad0cd86f2a", - "new_hash": "", + "old_hash": "bdf1d8a29f6ba423b1e5e2aa8ecb75025135cc9e0b00afc03bf8cbfa91c3bbed", + "new_hash": "e34539b6c5f59574f671e1456bd2f260b784e5e32a8f27b1343589543b41c9b1", "edit": "" }, - "\"PPCGenSubtargetInfo.inc\"": { + "printPostIdxImm8Operand": { "apply_type": "OLD", - "old_hash": "e4f3e0f7dc2b54037b0a9cb2540e8d03ed3cab84775ff96fee93a09ba0dd77d1", - "new_hash": "", + "old_hash": "19577955ef15d0ffd3f4da5d6250103256997f30603326a3a900ca344f66999a", + "new_hash": "5ea82276e26da933866ac05a2c4d578d5dfea56121d4c83861683ef9cf6e626f", "edit": "" }, - "isRunOfOnes": { + "printPostIdxImm8s4Operand": { "apply_type": "OLD", - "old_hash": "c3de3de94ebba955e03feb016ca0aed64716eb14a2e89ba46fa56af6f2dd7401", - "new_hash": "f2134b05f922fb4eeddbd97be9e2312fdfdab4457e742ec1d15054b6e32f87c7", + "old_hash": "d86795b49368c0085fdce9d3b0d225a737f9371a8c3b63b560d6e47de1886350", + "new_hash": "bdcbc4287c441472f3b7a5af9a5fd263d58bf5d506b6cd6d65d5c9f78bd1f58f", "edit": "" }, - "isRunOfOnes64": { + "printPredicateOperand": { "apply_type": "OLD", - "old_hash": "93f39dbf36c667d3a320e4d3ea81765ad08950cba0f53fb0f7bc9272c4b57828", - "new_hash": "8defa0b1fce2eaf346f4be645281dffe4cb67fb4ff367dd2ed34c37f7205897f", + "old_hash": "3932565457d2a4af42da2ab2d7447d855aac9764df70370d9cd1878f8382e9c3", + "new_hash": "5b19fb63c4e2ac199d61b4c3330df297566142adcce15a7f2e50caad22e33ac8", "edit": "" - } - }, - "PPCPredicates.h": { - "PPC_getPredicate": { + }, + "printRegImmShift": { "apply_type": "OLD", - "old_hash": "16e2de8b27885d9216adae987eea4a12a4e6a1395d5f44462049e6a2aa53fd54", - "new_hash": "2745cb11387ee4c9fa7c692356ec2ef778870f08428df3666ae218a23a02927f", + "old_hash": "5f0717b8c6b8adf379dc0fce2f7ebae5a90403ca92a446f6574334304e5b3442", + "new_hash": "70f7f28dda0dac5e056d6020610064c1690ab444185131a825bc8d8952f82286", "edit": "" }, - "PPC_getPredicateCondition": { + "printRegName": { "apply_type": "OLD", - "old_hash": "6680b6f42d3644d2ed656077554c6c34a403a62b47d2226810d6ad9f25ef30a8", - "new_hash": "96ae9e8cc826c5da2bddd91c8d109856c7234749c064ef9e1d4ec77ddfb2efdc", + "old_hash": "c1eb60a0d7d33b057623433b82571a760df70ad3154db7b0b19946d35089f1b2", + "new_hash": "76093e8d5ef4e71ae65ad578dadfb11aae8344a58ea6d7a8b3c745707ef9e6e2", "edit": "" }, - "PPC_getPredicateHint": { + "printRotImmOperand": { "apply_type": "OLD", - "old_hash": "f51873e40d9a5bc6f49f1cde2418a111b356a438fdb9f20f13b625142f16dbcf", - "new_hash": "02eaaa869cf975da8203666135470c113ad9246dd2f73061dbf6ee1706683299", + "old_hash": "449126f378f30164371e523d6eaba8d5459456ce4db01b32b01a83a263a541dd", + "new_hash": "0aece7379e3e2437fe6ac740d551bf1ceea0c3dc8a0bebf0ffab0d657057adf8", "edit": "" - } - }, - "AArch64Disassembler.c": { - "\"AArch64GenInstrInfo.inc\"": { + }, + "printSORegImmOperand": { "apply_type": "OLD", - "old_hash": "cf7aa34be7a72b5363681d20acdec9b28e904e495835884c103f3e6670de28a3", - "new_hash": "", + "old_hash": "a1fe068c5ceba67576ab8258cc219873407977d389a13013b4667acbf5f98961", + "new_hash": "ee6be5af2d248114795e4aa984aff8f7d84d9b458dc64a4365ee49565f12bea9", "edit": "" }, - "AArch64_LLVM_getInstruction": { + "printShiftImmOperand": { "apply_type": "OLD", - "old_hash": "725effa985946d8b86b44d9f5bc3c5ae22b415d3ddeb6ed8c850ce09599faf69", - "new_hash": "", + "old_hash": "7f1299f202c7103edbe37fa729326c7da3c76b98d000d7b3adc5245bd72ba955", + "new_hash": "5ac17ae57aefe4888c045a8959afe9ad3cfbc1b6a451962551a9cadd4522f024", "edit": "" }, - "DecodeAddSubImmShift": { + "printT2AddrModeImm0_1020s4Operand": { "apply_type": "OLD", - "old_hash": "e4d6f979492d1caa080401a5a67a052771bafd2440ac9d95bd1c3ddc99ea40a3", - "new_hash": "f0abaf4318761d265396777fbe530c935878375fb4a12089aa35a782649ce01a", + "old_hash": "b20a6c57a7acdbf382d69329f956b48f7728189bf1a9ff25b109ae59b2efaf44", + "new_hash": "375142b95895fa4e40df63f164ba24d5f7b45466779ce08d7324eb97d47636d8", "edit": "" }, - "DecodeAdrInstruction": { + "printT2AddrModeImm8OffsetOperand": { "apply_type": "OLD", - "old_hash": "b368887ed1bc790c7f3670e381a2860825b8665103db17f7a4339b1f920609e0", - "new_hash": "774343e7c81b0fba91cbb35d514910bfdd4e71df5b30b0f31c9db8a96cb7e463", + "old_hash": "57b6bebfa994d0e9154b232a5fa13283bb37f070ec0f12f24cc5c22510f35500", + "new_hash": "4ffba0d957ef4da97aed16b02e59e68252d56028a64759c37d199076a356823b", "edit": "" }, - "DecodeFMOVLaneInstruction": { + "printT2AddrModeImm8s4OffsetOperand": { "apply_type": "OLD", - "old_hash": "dac4e494466b422ed0366fe0f9fc89c252137e8254a90d051c106dcf5d88e568", - "new_hash": "34fcd7054e57a9efaf3acb6d99c27d739c4025446b3233ce1bd5978afcde8f85", + "old_hash": "f2069b50e98d4faf11b5200b418abac998deda28baf95f0be081a8e8449b4528", + "new_hash": "8e5a320189ab6ea0220f3ccfa4c0aef459fd7f1e28ed8fab1f92f80131d09f66", "edit": "" }, - "DecodeMRSSystemRegister": { + "printT2AddrModeSoRegOperand": { "apply_type": "OLD", - "old_hash": "b586961a60ec97c7c0ae0536e5744c2f4b6094618a331bdc1a2b4e0f671b35f5", - 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"DecodeSyspXzrInstruction": { + "printThumbAddrModeImm5S2Operand": { "apply_type": "OLD", - "old_hash": "f18f29407e58f88ca4697c770773baceaaa9824d5b2110bb8172c82cca86c706", - "new_hash": "b31e6d7f9c360cad5eab2c9d8d9e89784fbef9393d7839bb6079e995ff063ab4", + "old_hash": "c1828a2e08a01240583f68c9d59bde99ca4555d65490dc547029cae94299a83a", + "new_hash": "517873dc4755e3bc6d7ce50a80bd716e03fef549b344295ad908bc84e6101c41", "edit": "" }, - "DecodeSystemPStateImm0_15Instruction": { + "printThumbAddrModeImm5S4Operand": { "apply_type": "OLD", - "old_hash": "4f537b4b005000621707c91b04175d2c586a9a7320e362bf5b3cc2019d62941c", - "new_hash": "1ff2252bcdd3f95706b0cb52980c50bedeb2106a81696db21ba3d4c74b8c025c", + "old_hash": "196c943ec78b1aad2ad8377c1ed245074f8d0c4cb2f875a5ed5a83a9b2b60bb2", + "new_hash": "083d4bdec37438584a608c2daeea1fa1589bd3de77f156bce608007aad0e2d16", "edit": "" }, - "DecodeSystemPStateImm0_1Instruction": { + "printThumbAddrModeImm5SOperand": { "apply_type": "OLD", - "old_hash": "3518d2bbc21bf37f6d4c0ac5c1e54376209172f99115357c91d10ce139ed9cca", - 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"printPostIncOperand": { + "decodeCRBitMOperand": { "apply_type": "OLD", - "old_hash": "b055ee50d42dbe7b69adfe3625258e392ef376c74bc7a1fdd1422a108daffd13", - "new_hash": "1c9ca6bfc5801c5ea025419d640d7f4ef6c6a9d79321a491e7b5bfd8dde73462", + "old_hash": "fb18241cd88deb19fbe3f4376a6d48f072342793ab3db2dd3fc727a9ef4b4aa9", + "new_hash": "7c74af36ff0b1822e4f495be05a034aa5bb1f8415cedfa0eb2d673edff2eb593", "edit": "" }, - "printRPRFMOperand": { + "decodeCondBrTarget": { "apply_type": "OLD", - "old_hash": "4c1bb639354ce7d4be9c4ee967d571b0e6179eea23a0d651915cfb49c02a9d34", - "new_hash": "1b9a563b6158136a94c14fed167e61daa1279115c8d74f2272f5fa8cdb156ce6", + "old_hash": "ea9e32f678a855e1d192e49f0f98c6ab634a03e7527a72bd604f5df888f16f55", + "new_hash": "94fd8dbfbb0cb0fcd90e0efddac51f17ca56ef5140486db9a6c8accee4a539d1", "edit": "" }, - "printRangePrefetchAlias": { + "decodeDirectBrTarget": { "apply_type": "OLD", - "old_hash": "6c822a316e30241156879d677559b3c0fe1bd6dfe5e219ceec81f6a39f8ed7ef", - "new_hash": "4d3ef668b725d469213cbf614431c3471006fb6af0b1e3d48d5675dfdab9e69c", + "old_hash": "bf49afc5f8e9131ae1a4852c330bb5214b0fb96218dc90a348aade8dc702044e", + "new_hash": "b47373f0a20d809a0aa38ba059045b33ff88c8338dfe72cbcd3c14b599abbf9a", "edit": "" }, - "printRegName": { + "decodeDispRIHashOperand": { "apply_type": "OLD", - "old_hash": "6713f913e8d8f9f2144ddb394d485a9b6dd4e2975d0d28d69252b903892c3def", - "new_hash": "", + "old_hash": "", + "new_hash": "1b34b98bab88ce771f50ae9f966ef78bb389eb6b281266597e9cbffc6a908cb0", "edit": "" }, - "printRegNameAlt": { + "decodeDispRIX16Operand": { "apply_type": "OLD", - "old_hash": "924a2c423f59f680ca5c9c5131ac3c52d0b525201a84eaf2288311dbd1a5fe04", - "new_hash": "", + "old_hash": "", + "new_hash": "1f2dc28c5f981f7ac9212932f00a18a09e382bef532376bb9db4ae6382408d68", "edit": "" }, - "printSIMDType10Operand": { + "decodeDispRIXOperand": { "apply_type": "OLD", - "old_hash": "b6e562d86fd6791053fd539f53d3ad2770e5a600ccfbc2af966594d90d757827", - "new_hash": "dc79bb6126a53e2b35eff8a39234c513c060f9b3ed10d970e9e0f3ad8cfe19af", + "old_hash": "", + "new_hash": "d185c48343d6ad885a7c40927ffc4e4f36899ca97dce00886e3117c0eaeeef65", "edit": "" }, - "printSVCROp": { + "decodeDispSPE2Operand": { "apply_type": "OLD", - "old_hash": "0d65151f55e3938701ef097ca0a16ffd868ae191a15d8329ba3dc29bc9a36d95", - "new_hash": "7705462f94d6a5b21db30dab5bf0ce7b612f5f861e97c1942eb826861047067d", + "old_hash": "", + "new_hash": "c0e01d088225db6729f5bb24bdb62ddd73899cce78ceb984d7dc879682509202", "edit": "" }, - "printSVEPattern": { + "decodeDispSPE4Operand": { "apply_type": "OLD", - "old_hash": "fa41064f8852c15334745f29f622a606cb341be16eb4959b340417b0a682eff7", - "new_hash": "77aef0a120cc4fb1cdd668113cfb6f8dfbc5018bcf375ee745d2f415e6ea1717", + "old_hash": "", + "new_hash": "5d757df8ba53c9ba8568fdc8fedc8cfbfddfdca8806fa8ea900f9137386fa05f", "edit": "" }, - "printSVEVecLenSpecifier": { + "decodeDispSPE8Operand": { "apply_type": "OLD", - "old_hash": "12546ccb31f7b4cdea8f3bab5c72164ae1174195b90b4b487e4364109bb1f025", - "new_hash": "d7bf289de98efd77f0e3b54329de085ddd01fc8c7953a844673a33f8f1e83d80", + "old_hash": "", + "new_hash": "e90312c2af9fc2efe1b7574ea405bba70e211083f93c6be73445aa7177de7fa2", "edit": "" }, - "printShifter": { + "decodeImmZeroOperand": { "apply_type": "OLD", - "old_hash": "8780e3d55b20ca3d0fcd56253bdc12e5e29c78b5ebed404468a6e62e28a6b7e1", - "new_hash": "1a7340ea98ddfc471529d13620851ce811605cb33374e2d2935e0a4ad23c48ca", + "old_hash": "dc7192c8dcca845a50fd1a775df9a79a883c4eea71f20e5042457d15b2936799", + "new_hash": "a1d6b9c56142dfbedd08f0c73862248d1fc5924032cafe131979e3b774c6117d", "edit": "" }, - "printSysAlias": { + "decodeMemRI34Operands": { "apply_type": "OLD", - "old_hash": "545512a84bc61032f5dcb350b278a03b5e46841ff8600336b077e221b15cac91", - "new_hash": "bb9b756f6b10697e649933c71d62f9da17a8c7b593c4640164ca4049ac278f14", + "old_hash": "effea0efbf97b8d4b039d52b3b30e883cf88acf25503026853925c9e09ba57f5", + "new_hash": "", "edit": "" }, - "printSysCROperand": { + "decodeMemRI34PCRelOperands": { "apply_type": "OLD", - "old_hash": "4365ffcfb7610b3d99f1c4366c6075bea2d97f1aa0e9f6903961a044e414a92f", - "new_hash": "aeb33a6e608ea95c13003280a930fd4fd976035ca3952b7ef19956c84d091e6f", + "old_hash": "191f7e082fe3fffb28957b3a0eff5682ff4476e8977ca4aa2699adc280ea6f9f", + "new_hash": "", "edit": "" }, - "printSyspAlias": { + "decodeMemRIHashOperands": { "apply_type": "OLD", - "old_hash": "d0554a4751c8b0189f7cbbe2a41a4a6f945ad20aae9e0d17dfff0f2a0eb16609", - "new_hash": "5df179695096301fd3ab92a005c4b67d4c4e063a71b7da3b8b58a1c03762b27d", + "old_hash": "b905a8557bbc5385950d74035e77c858fb5c1af03c10d752768fbfe71d944095", + "new_hash": "", "edit": "" }, - "printSyspXzrPair": { + "decodeMemRIOperands": { "apply_type": "OLD", - "old_hash": "09aedf75d181cc9c7a9e4f942018f96ea595826d507380789ca30dcf9ad84b95", - "new_hash": "eae4aac4b34f6fc8501568bcd83c3a905259fd9bfc8a8a8fd06721467208cd32", + "old_hash": "4c7e8eddca16ab5048e12c82347534d5e08271adbb0acc1ed2ac1c391cbeec4b", + "new_hash": "", "edit": "" }, - "printSystemPStateField": { + "decodeMemRIX16Operands": { "apply_type": "OLD", - "old_hash": "4c07d2a91d7998bc3b667d4cdfa31c31dbaac6535ca7735984502d955562da19", - "new_hash": "4297502f835ed48d48b5e637644ddd70df0189560ab60f45b708083bf01b68a0", + "old_hash": "a7e0eea11e3e73a38957a633fbb4c8bf2a3b1aadf10a2646064803a95093f0ef", + "new_hash": "", "edit": "" }, - "printUImm12Offset": { + "decodeMemRIXOperands": { "apply_type": "OLD", - "old_hash": "4eac20c0c67389228d78bdae46a29e5f32df7ad2202dd5893dabffba49319b7d", - "new_hash": "47363cd6a2686d6a9e73271238c087d86d9d6ecf32757caf60004151785270f1", + "old_hash": "24e7c72ebcf794efd16d38c9f37102f7fd892ec5a7ff1e456ba096e2728c083b", + "new_hash": "", "edit": "" }, - "printVRegOperand": { + "decodeRegisterClass": { "apply_type": "OLD", - "old_hash": "7559da8c8c54fe9a399ef66515b2a34fc25c2312cb1331b1ca3b51d59e2a9f95", - "new_hash": "97ad0e3c86f991dc8f2b07a4d6188fad8f61fd15dbfb43d527dbb29b851a423a", + "old_hash": "35e25f6cc24d1a13cb7235a901496bebf7a1f9d082282495bb56de652a2ef1f3", + "new_hash": "c4ae91d25883a1d6d95c647fb2bbbf9d01781689c1a3c4488badb9245ffc2317", "edit": "" }, - "printVectorIndex": { + "decodeSPE2Operands": { "apply_type": "OLD", - "old_hash": "", - "new_hash": "8247fcc4b244c9ac9cf912b5e34f35f010ecd75c2a637d146f290d87950e3e57", + "old_hash": "126fcb6277e4a2fc967e74990ebfdfe3ab83adf1a58a3290e5fdf17085a3c8b2", + "new_hash": "", "edit": "" }, - "printVectorList": { + "decodeSPE4Operands": { "apply_type": "OLD", - "old_hash": "b32871b8dfd97a2aa17d98a965060e399075a64010d740bb71364da6c2ea666e", - "new_hash": "28013ffeef0a3b287e0277976cddf9e983fb4f334988013bf61002f7a4df5120", + "old_hash": "fd80f242361764a6dc69b7a612b68edfe6ded7714b5d32727c7181d6dc5e5b2c", + "new_hash": "", "edit": "" - } - }, - "AArch64InstPrinter.h": { - "CHAR": { + }, + "decodeSPE8Operands": { "apply_type": "OLD", - "old_hash": "124752d5ccb0a58a33fda6a56b3019e8ee64c807473745b1024920475a41b6c1", + "old_hash": "58d0b69eb70dbc98d21c0ae8025b4e3f176be9119c7848fe536be3dcef0d86c2", "new_hash": "", "edit": "" }, - "DECLARE_printComplexRotationOp": { + "getInstruction": { + "apply_type": "OLD", + "old_hash": "bf6afd23ac43a419c4fe562edaaf08373b831b96e4318b7e281f5c7ca132a598", + "new_hash": "6124d5bd062f28f910fa50b1d63e8a45b8dde3065a59da859237d97742f4dbfe", + "edit": "" + } + }, + "PPCInstPrinter.c": { + "\"../../Mapping.h\"": { "apply_type": "OLD", - "old_hash": "", - "new_hash": "fce2e8a1bcf52e4cee15c639d6dd1ea06daa80101a70821da09a89744770f012", + "old_hash": "204ac68dcb32024c325b99a0843719c321ab57c60c41b12adbea497c20b7d436", + "new_hash": "", "edit": "" }, - "DECLARE_printImmSVE": { + "PPC_LLVM_getRegisterName": { "apply_type": "OLD", - "old_hash": "3a1480e4bea3cb04f44a5e38b6178bb999163db484dfe0382e09994493d5fe15", + "old_hash": "83384bb6920ca435750803566108eff77442720a35423c0f5b6bfebca4466b5f", "new_hash": "", "edit": "" }, - "DECLARE_printMatrixIndex": { + "PPC_LLVM_printInst": { "apply_type": "OLD", - "old_hash": "1529c1641329f4a2d2671dbf20e010a0c4911185528a04e4aee0edcc9db08f21", - "new_hash": "a6d3e38cc44b34ee39d257a5ebf1fcc2a08873a81a76cd27379be1eae804df31", + "old_hash": "bc6df651b2a5f3810df3f9b77c29ac7f9e92013d4cbc3f3187b3ea6e237a1ae6", + "new_hash": "", "edit": "" }, - "DECLARE_printPrefetchOp": { + "getVerboseConditionRegName": { "apply_type": "OLD", - "old_hash": "5eabf8f14973634b0e6c3ae130701902224d800b10afcadbd528e35f1a6507ed", - "new_hash": "c13bb1f006d1df40067c2e231dec5ca76f5172df7b58e6b417005bb9083a19b8", + "old_hash": "c014e2d8b222be07d6fb574a3d9b2c0bd5f7084044a3bad372980efd5931e9d7", + "new_hash": "7686715daa951f40105c858a2a6962d56a255bfd3919ae995f3136e40d50358b", "edit": "" }, - "DECLARE_printSVERegOp": { + "printAbsBranchOperand": { "apply_type": "OLD", - "old_hash": "0aa7571e6104798c55f0b805490867a646f05ed2f3e5c5c06446fa8abedf5599", - "new_hash": "9b06b1f1aa8767f9937fdfa7f3d226ac80e08fa948f7f0e910d3ffc0891c3097", + "old_hash": "1157d42eb9a1920fb0b6a448fda5168a217c706732869b9b1bdb4ae9aecf8495", + "new_hash": "d04a7678c4c21e3df33cc039143fb700f9416932ac11a18c95ed40ba8ea08841", "edit": "" }, - "DECLARE_printVectorIndex": { + "printBranchOperand": { "apply_type": "OLD", - "old_hash": "812a06ae0581f7b2cbf0025580440716a39506b2f3c4511f13754eff92b40b55", - "new_hash": "", + "old_hash": "c20e1c20fae0bcf418c30c3a06302936e823bb04ee8060d84715d7dd9a460810", + "new_hash": "dbd988ddfe9f9e9bfaf86d57347950c0b7cbac68625e8a67e4e5b38369f0136f", "edit": "" }, - "DEFINE_printMemExtend": { + "printImmZeroOperand": { "apply_type": "OLD", - "old_hash": "b4d8d692afc2e76d684f030d5e726653ab27d46189f23fd24dd59e51f93d7820", - "new_hash": "7937a72a3d61ce68fc93e430e85fffdc8a340f6cf36e0b4560191dc84cd0c563", + "old_hash": "cbacd7e6f47c813e31eeb35797001aff4fc5e5491c51bd8359dfd9bc082df986", + "new_hash": "46036217bb3043cf754e707dd98e37e7d2c62fe08bd8a75456e6232e68a9a0f0", "edit": "" }, - "DEFINE_printPostIncOperand": { + "printInst": { "apply_type": "OLD", - "old_hash": "f5270534ba460fe91b3b5f32d9a689437f046f97f7aba10c3e4960c9b01544fa", - "new_hash": "4e307c8cda062824c3f2b3fef783c5f059a9d27864ee17885b6738d5ef3b04c8", + "old_hash": "3f3f6e26181e91a6a98bc893a05404413797db9b7ddf3e77ea5b6c7cb1760919", + "new_hash": "576c2e923095863e98ea4255f512049421dc7d10b42459904f03a480c9c724f9", "edit": "" }, - "DEFINE_printUImm12Offset": { + "printMemRegImm": { "apply_type": "OLD", - "old_hash": "ec7e4542129a565d36fdf56432a21390b2f9f92e34db1f1d400791022b5cc0b2", - "new_hash": "c9cd1eb0352f26b7849971a253706ce9e48bbc2ed3a8ad69405631ab8acbf1d3", + "old_hash": "6154062a675a628b76a2b597c1ae9736a847979d193f1bfaa3eba0451d948268", + "new_hash": "4aafa39c3f666d0c4399738b3c6ae26eea315e76a66d4e469f95b118b68f8c30", "edit": "" }, - "printAMIndexedWB": { - "apply_type": "OLD", - "old_hash": "", - "new_hash": "db56e4bb1f56913177897f46aca4e4653980d5fdb91ea6c50370ef26ecea3820", - "edit": "" - } - }, - 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"getXRegFromWReg": { + "PPC_getPredicateCondition": { "apply_type": "OLD", - "old_hash": "d3fb4dbdea7dd52ac590777ea9aee8a03f12192addcaca4dfabe4d534a5214de", - "new_hash": "b2475a663b67cb2ce8d5f16994c02b275582b0f0bc663afe4ff105bd6bcbb511", + "old_hash": "6680b6f42d3644d2ed656077554c6c34a403a62b47d2226810d6ad9f25ef30a8", + "new_hash": "96ae9e8cc826c5da2bddd91c8d109856c7234749c064ef9e1d4ec77ddfb2efdc", "edit": "" }, - "getXRegFromXRegTuple": { + "PPC_getPredicateHint": { "apply_type": "OLD", - "old_hash": "4c1346113fe176c3418754eb1507d88eea4865ed6d27a0b9238c2ed112667062", - "new_hash": "b148e4b22d7b4797a64a9a818430da372d8224dee020bf5ec049c07677bff5cc", + "old_hash": "f51873e40d9a5bc6f49f1cde2418a111b356a438fdb9f20f13b625142f16dbcf", + "new_hash": "02eaaa869cf975da8203666135470c113ad9246dd2f73061dbf6ee1706683299", "edit": "" } } diff --git a/suite/auto-sync/src/autosync/lit_config/README.md b/suite/auto-sync/src/autosync/lit_config/README.md new file mode 100644 index 0000000000..b5c253464b --- /dev/null +++ b/suite/auto-sync/src/autosync/lit_config/README.md @@ -0,0 +1,7 @@ + + +lit configurations for MC regression test generation. +As an introduction see: https://medium.com/@mshockwave/using-llvm-lit-out-of-tree-5cddada85a78 ([archived](https://web.archive.org/web/20240421091240/https://medium.com/@mshockwave/using-llvm-lit-out-of-tree-5cddada85a78)) diff --git a/suite/auto-sync/src/autosync/lit_config/lit.cfg.py b/suite/auto-sync/src/autosync/lit_config/lit.cfg.py new file mode 100644 index 0000000000..837216c83c --- /dev/null +++ b/suite/auto-sync/src/autosync/lit_config/lit.cfg.py @@ -0,0 +1,14 @@ +# Copyright © 2024 Rot127 +# SPDX-License-Identifier: BSD-3 + +from autosync.PathVarHandler import PathVarHandler +import lit.formats + +config.name = "Generate Capstone MC regression tests" +config.test_format = lit.formats.ShTest(True) + +config.suffixes = [".txt", ".s"] + +config.excludes = ["Inputs", "CMakeLists.txt", "README.txt", "LICENSE.txt"] + +config.test_source_root = PathVarHandler().get_path("{LLVM_LIT_TEST_DIR}") diff --git a/suite/auto-sync/src/autosync/lit_config/lit.site.cfg.py b/suite/auto-sync/src/autosync/lit_config/lit.site.cfg.py new file mode 100644 index 0000000000..5685955f33 --- /dev/null +++ b/suite/auto-sync/src/autosync/lit_config/lit.site.cfg.py @@ -0,0 +1,16 @@ +# Copyright © 2024 Rot127 +# SPDX-License-Identifier: BSD-3 + +from autosync.Targets import TARGETS_LLVM_NAMING +from autosync.PathVarHandler import PathVarHandler +from pathlib import Path + +import lit.llvm + +lit.llvm.initialize(lit_config, config) + +config.llvm_src_root = str(PathVarHandler().get_path("{LLVM_ROOT}").absolute()) +config.root.targets = " ".join(TARGETS_LLVM_NAMING) + +lit_cfg_dir = PathVarHandler().get_path("{LLVM_LIT_TEST_DIR}") +lit_config.load_config(config, lit_cfg_dir.joinpath("lit.cfg.py")) diff --git a/suite/auto-sync/src/autosync/mcupdater.json b/suite/auto-sync/src/autosync/mcupdater.json new file mode 100644 index 0000000000..5e0e26618d --- /dev/null +++ b/suite/auto-sync/src/autosync/mcupdater.json @@ -0,0 +1,10 @@ +{ + "additional_mattr": + { + "AArch64": [ "+all" ] + }, + "mandatory_options": + { + "SystemZ": [ "CS_MODE_BIG_ENDIAN" ] + } +} diff --git a/suite/auto-sync/src/autosync/path_vars.json b/suite/auto-sync/src/autosync/path_vars.json index 26ac90e4b7..8f51c14bba 100644 --- a/suite/auto-sync/src/autosync/path_vars.json +++ b/suite/auto-sync/src/autosync/path_vars.json @@ -4,6 +4,7 @@ "{LLVM_TARGET_DIR}": "{LLVM_ROOT}/llvm/lib/Target/", "{LLVM_MC_TEST_DIR}": "{LLVM_ROOT}/llvm/test/MC/", "{LLVM_TBLGEN_BIN}": "{LLVM_ROOT}/build/bin/llvm-tblgen", + "{LLVM_LIT_TEST_DIR}": "{AUTO_SYNC_SRC}/lit_config/", "{LLVM_INCLUDE_DIR}": "{LLVM_ROOT}/llvm/include/", "{VENDOR_DIR}": "{AUTO_SYNC_ROOT}/vendor/", "{BUILD_DIR}": "{AUTO_SYNC_ROOT}/build/", @@ -32,9 +33,12 @@ "{DIFFER_TEST_NEW_SRC_DIR}": "{DIFFER_TEST_DIR}/new_src/", "{DIFFER_TEST_PERSISTENCE_FILE}": "{DIFFER_TEST_DIR}/test_saved_patches.json", "{AUTO_SYNC_TEST_DIR}": "{AUTO_SYNC_SRC}/Tests/", + "{MCUPDATER_CONFIG_FILE}": "{AUTO_SYNC_SRC}/mcupdater.json", "{MCUPDATER_TEST_DIR}": "{AUTO_SYNC_TEST_DIR}/MCUpdaterTests/", + "{MCUPDATER_TEST_DIR_EXPECTED}": "{AUTO_SYNC_TEST_DIR}/MCUpdaterTests/expected", "{MCUPDATER_OUT_DIR}": "{BUILD_DIR}/mc_out/", - "{MC_DIR}": "{CS_ROOT}/suite/MC/" + "{MCUPDATER_TEST_OUT_DIR}": "{MCUPDATER_TEST_DIR}/test_output/", + "{MC_DIR}": "{CS_ROOT}/tests/MC/" }, "create_during_runtime": [ "{BUILD_DIR}", @@ -43,7 +47,8 @@ "{CPP_TRANSLATOR_TRANSLATION_OUT_DIR}", "{CPP_TRANSLATOR_DIFF_OUT_DIR}", "{HEADER_GEN_TEST_ARM64_OUT_FILE}", - "{MCUPDATER_OUT_DIR}" + "{MCUPDATER_OUT_DIR}", + "{MCUPDATER_TEST_OUT_DIR}" ], "ignore_missing": [ "{DIFFER_TEST_PERSISTENCE_FILE}" diff --git a/suite/compile_all.sh b/suite/compile_all.sh deleted file mode 100755 index 8360f2b1ee..0000000000 --- a/suite/compile_all.sh +++ /dev/null @@ -1,30 +0,0 @@ -#! /bin/bash -# By Daniel Godas-Lopez. - -export LD_LIBRARY_PATH=. - -for x in default nix32 cross-win32 cross-win64 cygwin-mingw32 cygwin-mingw64 bsd clang gcc; do - echo -n "Compiling: $x ... " - ./compile.sh $x &> /dev/null - - if [ $? == 0 ]; then - echo "-> PASS" - else - echo -e "-> FAILED\n" - continue - fi - - for t in test test_arm test_aarch64 test_detail test_mips test_x86 test_ppc; do - ./tests/$t &> /dev/null - - if [ $? -eq 0 ]; then - echo " Run $t -> PASS" - else - echo " Run $t -> FAIL" - fi - done - - echo -done - -make clean &> /dev/null diff --git a/suite/cstest/CMakeLists.txt b/suite/cstest/CMakeLists.txt new file mode 100644 index 0000000000..637ae90672 --- /dev/null +++ b/suite/cstest/CMakeLists.txt @@ -0,0 +1,88 @@ +cmake_minimum_required(VERSION 3.15) + +include(ExternalProject) +find_library(libyaml + NAMES libyaml yaml + REQUIRED) +ExternalProject_Add(cmocka_ext + PREFIX extern + URL "https://cmocka.org/files/1.1/cmocka-1.1.7.tar.xz" + URL_HASH SHA256=810570eb0b8d64804331f82b29ff47c790ce9cd6b163e98d47a4807047ecad82 + DOWNLOAD_EXTRACT_TIMESTAMP true + CONFIGURE_COMMAND cmake -DBUILD_SHARED_LIBS=OFF -DCMAKE_BUILD_TYPE=${CMAKE_BUILD_TYPE} ../cmocka_ext/ + BUILD_COMMAND cmake --build . --config Release + INSTALL_COMMAND "" +) + +if ("${CMAKE_BUILD_TYPE}" STREQUAL "Debug") + set(LIBCYAML_VARIANT "debug") +else() + set(LIBCYAML_VARIANT "release") +endif() + +ExternalProject_Add(libcyaml_ext + PREFIX extern + URL "https://github.com/tlsa/libcyaml/archive/refs/tags/v1.4.1.tar.gz" + URL_HASH SHA256=8dbd216e1fce90f9f7cca341e5178710adc76ee360a7793ef867edb28f3e4130 + DOWNLOAD_EXTRACT_TIMESTAMP true + CONFIGURE_COMMAND "" + BUILD_COMMAND make VARIANT=${LIBCYAML_VARIANT} + BUILD_IN_SOURCE true + INSTALL_COMMAND "" +) +set(CMOCKA_INCLUDE_DIR ${CMAKE_CURRENT_BINARY_DIR}/extern/src/cmocka_ext/include) +set(CMOCKA_LIB_DIR ${CMAKE_CURRENT_BINARY_DIR}/extern/src/cmocka_ext-build/src/) +set(LIBCYAML_INCLUDE_DIR ${CMAKE_CURRENT_BINARY_DIR}/extern/src/libcyaml_ext/include) +set(LIBCYAML_LIB_DIR ${CMAKE_CURRENT_BINARY_DIR}/extern/src/libcyaml_ext/build/${LIBCYAML_VARIANT}/) +add_library(cmocka STATIC IMPORTED) +add_library(libcyaml STATIC IMPORTED) +set_target_properties(cmocka PROPERTIES IMPORTED_LOCATION ${CMOCKA_LIB_DIR}/libcmocka.a) +set_target_properties(libcyaml PROPERTIES IMPORTED_LOCATION ${LIBCYAML_LIB_DIR}/libcyaml.a) + +set(CSTEST_INCLUDE_DIR ${CSTEST_DIR}/include) +file(GLOB CSTEST_SRC ${CSTEST_DIR}/src/*.c) +add_executable(cstest ${CSTEST_SRC}) +add_library(libcstest STATIC ${CSTEST_SRC}) +add_dependencies(cstest cmocka_ext) +add_dependencies(cstest libcyaml_ext) +target_link_libraries(cstest PUBLIC capstone cmocka libcyaml yaml) +target_link_libraries(libcstest PUBLIC capstone cmocka libcyaml yaml) +target_include_directories(cstest PRIVATE + ${PROJECT_SOURCE_DIR}/include> + ${CSTEST_INCLUDE_DIR} + ${CMOCKA_INCLUDE_DIR} + ${LIBCYAML_INCLUDE_DIR} + ) +target_include_directories(libcstest PRIVATE + ${PROJECT_SOURCE_DIR}/include> + ${CSTEST_INCLUDE_DIR} + ${CMOCKA_INCLUDE_DIR} + ${LIBCYAML_INCLUDE_DIR} + ) + +# Unit tests for cstest +set(CSTEST_TEST_DIR ${CSTEST_DIR}/test/) +add_subdirectory(${CSTEST_TEST_DIR}) + +# Test targets +add_test(MCTests + cstest ${PROJECT_SOURCE_DIR}/tests/MC + WORKING_DIRECTORY ${PROJECT_SOURCE_DIR} +) +add_test(DetailTests + cstest ${PROJECT_SOURCE_DIR}/tests/details + WORKING_DIRECTORY ${PROJECT_SOURCE_DIR} +) +add_test(IssueTests + cstest ${PROJECT_SOURCE_DIR}/tests/issues + WORKING_DIRECTORY ${PROJECT_SOURCE_DIR} +) +add_test(FeaturesTests + cstest ${PROJECT_SOURCE_DIR}/tests/features + WORKING_DIRECTORY ${PROJECT_SOURCE_DIR} +) + + +if(CAPSTONE_INSTALL) + install(TARGETS cstest EXPORT capstone-targets DESTINATION ${CMAKE_INSTALL_BINDIR}) +endif() diff --git a/suite/cstest/Makefile b/suite/cstest/Makefile deleted file mode 100644 index ae80597807..0000000000 --- a/suite/cstest/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -SOURCE = src -INCLUDE = include ../../include -BUILD = build -LIBRARY = -lcmocka -lcapstone -L../.. - -all: - rm -rf $(BUILD) - mkdir $(BUILD) - $(CC) $(SOURCE)/*.c $(INCLUDE:%=-I %) ${CMAKE_C_FLAGS} -g -o $(BUILD)/cstest $(LIBRARY) -cstest: - $(BUILD)/cstest -d ../MC -clean: - rm -rf $(BUILD) diff --git a/suite/cstest/README.md b/suite/cstest/README.md index dfc31cdea3..d2893aedd3 100644 --- a/suite/cstest/README.md +++ b/suite/cstest/README.md @@ -1,67 +1,16 @@ -# Regression testing -This directory contains a tool for regression testing core of Capstone + -## Dependency +## Building -- MacOS users can install cmocka with: +`cstest` is build together with Capstone by adding the flag `-DCAPSTONE_BUILD_CSTEST`. -``` -brew install cmocka -``` +The build requires `libyaml`. It is a fairly common package and should be provided by your package manager. -- Or download & build from source code [Cmocka](https://git.cryptomilk.org/projects/cmocka.git) +## Testing -- Build Cmocka - -## Build - -You can build `cstest` with `cmake` when building Capstone. Just pass the `CAPSTONE_BUILD_CSTEST` flag -during configuration. - -Alternatively you can use the `build_cstest.sh` file in this directory. - -## Usage - -- Usage: `cstest [-e] [-f ] [-d ]` - - `-e` : test all commented test - -- Test for all closed issues - -``` -cd suite/cstest -./build/cstest -f ./issues.cs -``` - -- Test for some input from LLVM - -``` -cd suite/cstest -./build/cstest -f ../MC/AArch64/basic-a64-instructions.s.cs -``` - -- Test for all cs file in a folder - -``` -cd suite/cstest -./build/cstest -d ../MC -``` - -- Test all - -``` -cd suite/cstest -make cstest -``` - -## Report tool - -- Usage `cstest_report.py [-Dc] -t [-f ] [-d ]` - - `-D` : print details - - `-c` : auto comment out failed test - -- Example: - -``` -./cstest_report.py -t build/cstest -d ../MC/PowerPC/ -./cstest_report.py -t build/cstest -f issues.cs -``` +Files to test `cstest` itself are located in `suite/cstest/test`. +And yes, testing with a shell script is not nice. But I have time constraints, and +for integration testing it does pretty much exactly what it should. diff --git a/suite/cstest/build_cstest.sh b/suite/cstest/build_cstest.sh deleted file mode 100755 index ba3c81d81c..0000000000 --- a/suite/cstest/build_cstest.sh +++ /dev/null @@ -1,21 +0,0 @@ -#!/bin/sh -x - -cd cmocka -mkdir build -cd build - -if [ "$(uname)" = Darwin ]; then - cmake -DCMAKE_INSTALL_PREFIX=/usr/local .. && make -j2 && sudo make install -elif [ "$asan" = "ON" ]; then - CMAKE_C_FLAGS="-fsanitize=address" CMAKE_LINK_FLAGS="-fsanitize=address" cmake -DCMAKE_INSTALL_PREFIX=/usr/local .. && make -j2 && sudo make install -else # Linux - cmake -DCMAKE_INSTALL_PREFIX=/usr .. && make -j2 && sudo make install -fi - -cd ../.. - -if [ "$asan" = "ON" ]; then - CMAKE_C_FLAGS="-fsanitize=address" make -else - make -fi diff --git a/suite/cstest/cstest_report.py b/suite/cstest/cstest_report.py deleted file mode 100755 index 45254c65c0..0000000000 --- a/suite/cstest/cstest_report.py +++ /dev/null @@ -1,114 +0,0 @@ -#!/usr/bin/python - -import re -import sys -import getopt -from subprocess import Popen, PIPE -from pprint import pprint as ppr -import os - -_python3 = sys.version_info.major == 3 - - -def Usage(s): - print('Usage: {} -t [-f ] [-d ]'.format(s)) - sys.exit(-1) - -def get_report_file(toolpath, filepath, getDetails, cmt_out): - cmd = [toolpath if toolpath else "cstest", '-f', filepath] - process = Popen(cmd, stdout=PIPE, stderr=PIPE) - stdout, stderr = process.communicate() - if process.returncode != 0: - print('[-] Failed to run cstest on {}'.format(filepath)) - print('[-] stdout:') - print(stdout) - print('[-] stderr:') - print(stderr) - return 0 - -# stdout - failed_tests = [] - if _python3: - stdout = bytes.decode(stdout) - stderr = bytes.decode(stderr) - # print('---> stdout\n', stdout) - # print('---> stderr\n', stderr) - matches = re.finditer(r'\[\s+RUN\s+\]\s+(.*)\n\[\s+FAILED\s+\]', stdout) - for match in matches: - failed_tests.append(match.group(1)) -# stderr - counter = 0 - details = [] - for line in stderr.split('\n'): - if '[ PASSED ] 0 test(s).' in line: - break - elif 'LINE' in line: - continue - elif 'ERROR' in line and ' --- ' in line: - parts = line.split(' --- ') - try: - details.append((parts[1], failed_tests[counter], parts[2])) - except IndexError: - details.append(('', 'Unknown test', line.split(' --- ')[1])) - counter += 1 - else: - continue - print('\n[-] There are/is {} failed test(s)'.format(len(details))) - if len(details) > 0 and getDetails: - print('[-] Detailed report for {}:\n'.format(filepath)) - for c, f, d in details: - print('\t[+] {}: {}\n\t\t{}\n'.format(f, c, d)) - print('\n') - return 0 - elif len(details) > 0: - for c, f, d in details: - if len(f) > 0 and cmt_out is True: - tmp_cmd = ['sed', '-E', '-i.bak', 's/({})(.*)/\/\/ \\1\\2/g'.format(c), filepath] - sed_proc = Popen(tmp_cmd, stdout=PIPE, stderr=PIPE) - sed_proc.communicate() - tmp_cmd2 = ['rm', '-f', filepath + '.bak'] - rm_proc = Popen(tmp_cmd2, stdout=PIPE, stderr=PIPE) - rm_proc.communicate() - - return 0 - return 1 - -def get_report_folder(toolpath, folderpath, details, cmt_out): - result = 1 - for root, dirs, files in os.walk(folderpath): - path = root.split(os.sep) - for f in files: - if f.split('.')[-1] == 'cs': - print('[-] Target:', f,) - result *= get_report_file(toolpath, os.sep.join(x for x in path) + os.sep + f, details, cmt_out) - - sys.exit(result ^ 1) - -if __name__ == '__main__': - Done = False - details = False - toolpath = '' - cmt_out = False - try: - opts, args = getopt.getopt(sys.argv[1:], "ct:f:d:D") - for opt, arg in opts: - if opt == '-f': - result = get_report_file(toolpath, arg, details, cmt_out) - if result == 0: - sys.exit(1) - Done = True - elif opt == '-d': - get_report_folder(toolpath, arg, details, cmt_out) - Done = True - elif opt == '-t': - toolpath = arg - elif opt == '-D': - details = True - elif opt == '-c': - cmt_out = True - - except getopt.GetoptError: - Usage(sys.argv[0]) - - if Done is False: - Usage(sys.argv[0]) diff --git a/suite/cstest/include/capstone_test.h b/suite/cstest/include/capstone_test.h deleted file mode 100644 index 45901af89d..0000000000 --- a/suite/cstest/include/capstone_test.h +++ /dev/null @@ -1,63 +0,0 @@ -/* Capstone testing regression */ -/* By Do Minh Tuan , 02-2019 */ - - -#ifndef CAPSTONE_TEST_H -#define CAPSTONE_TEST_H - -#include -#include -#include -#include -#include -#include -#include -#include -#include "helper.h" -#include "factory.h" - -#define cs_assert_err(expect, err) \ - do { \ - cs_err __err = err; \ - if (__err != expect) { \ - fail_msg("%s",cs_strerror(__err)); \ - } \ - } while (0) - - -#define cs_assert_success(err) cs_assert_err(CS_ERR_OK, err) - - -#define cs_assert_fail(err) \ - do { \ - cs_err __err = err; \ - if (__err == CS_ERR_OK) { \ - fail_msg("%s",cs_strerror(__err)); \ - } \ - } while (0) - -#define NUMARCH 10 -#define NUMMODE 35 -#define NUMOPTION 41 -#define MAXMEM 1024 - -typedef struct { - const char *str; - unsigned int value; -} single_dict; - -typedef struct { - const char *str; - unsigned int first_value; - unsigned int second_value; -} double_dict; - -extern char *(*function)(csh *, cs_mode, cs_insn*); - -int get_index(double_dict d[], unsigned size, const char *str); -int get_value(single_dict d[], unsigned size, const char *str); -void test_single_MC(csh *handle, int mc_mode, char *line); -void test_single_issue(csh *handle, cs_mode mode, char *line, int detail); -int set_function(int arch); - -#endif /* CAPSTONE_TEST_H */ diff --git a/suite/cstest/include/factory.h b/suite/cstest/include/factory.h deleted file mode 100644 index d3c36dba76..0000000000 --- a/suite/cstest/include/factory.h +++ /dev/null @@ -1,31 +0,0 @@ -/* Capstone testing regression */ -/* By Do Minh Tuan , 02-2019 */ - - -#ifndef FACTORY_H -#define FACTORY_H - -#include -#include "helper.h" - -char *get_detail_evm(csh *handle, cs_mode mode, cs_insn *ins); -char *get_detail_arm(csh *handle, cs_mode mode, cs_insn *ins); -char *get_detail_aarch64(csh *handle, cs_mode mode, cs_insn *ins); -char *get_detail_m680x(csh *handle, cs_mode mode, cs_insn *ins); -char *get_detail_mips(csh *handle, cs_mode mode, cs_insn *ins); -char *get_detail_ppc(csh *handle, cs_mode mode, cs_insn *ins); -char *get_detail_sparc(csh *handle, cs_mode mode, cs_insn *ins); -char *get_detail_sysz(csh *handle, cs_mode mode, cs_insn *ins); -char *get_detail_x86(csh *handle, cs_mode mode, cs_insn *ins); -char *get_detail_xcore(csh *handle, cs_mode mode, cs_insn *ins); -char *get_detail_riscv(csh *handle, cs_mode mode, cs_insn *ins); -char *get_detail_m68k(csh *handle, cs_mode mode, cs_insn *ins); -char *get_detail_mos65xx(csh *handle, cs_mode mode, cs_insn *ins); -char *get_detail_tms320c64x(csh *handle, cs_mode mode, cs_insn *ins); -char *get_detail_bpf(csh *handle, cs_mode mode, cs_insn *ins); -char *get_detail_tricore(csh *handle, cs_mode mode, cs_insn *ins); -char *get_detail_alpha(csh *handle, cs_mode mode, cs_insn *ins); -char *get_detail_hppa(csh *handle, cs_mode mode, cs_insn *ins); -char *get_detail_loongarch(csh *handle, cs_mode mode, cs_insn *ins); - -#endif /* FACTORY_H */ diff --git a/suite/cstest/include/helper.h b/suite/cstest/include/helper.h index a20dcca13b..b9b89773f6 100644 --- a/suite/cstest/include/helper.h +++ b/suite/cstest/include/helper.h @@ -1,33 +1,21 @@ /* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ - #ifndef HELPER_H #define HELPER_H -#include -#include -#include -#include -#include -#include -#include "capstone_test.h" +#include +#define MAX_ASM_TXT_MEM 1024 #define X86_16 0 #define X86_32 1 #define X86_64 2 -char **split(const char *str, const char *delim, int *size); -void print_strs(char **list_str, int size); -void free_strs(char **list_str, int size); +void trim_str(char *str); void add_str(char **src, const char *format, ...); -void trim_str(char *src); -void replace_hex(char *src); -void replace_negative(char *src, int mode); -void replace_tabs(char *str); -const char *get_filename_ext(const char *filename); - -char *readfile(const char *filename); -void listdir(const char *name, char ***files, int *num_files); +void replace_hex(char *src, size_t src_len); +void replace_negative(char *src, size_t src_len, size_t arch_bits); +void norm_spaces(char *str); +void str_to_lower(char *str); #endif /* HELPER_H */ diff --git a/suite/cstest/include/test_case.h b/suite/cstest/include/test_case.h new file mode 100644 index 0000000000..b5f7657a0f --- /dev/null +++ b/suite/cstest/include/test_case.h @@ -0,0 +1,175 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TESTCASE_H +#define TESTCASE_H + +#include "test_detail.h" +#include +#include +#include +#include + +/// Input data for a test case. +typedef struct { + char *name; + uint8_t *bytes; // mandatory + uint32_t bytes_count; // Filled by cyaml + char *arch; // mandatory + uint64_t address; + char **options; // mandatory + uint32_t options_count; // Filled by cyaml +} TestInput; + +TestInput *test_input_new(); +void test_input_free(TestInput *test_input); +TestInput *test_input_clone(TestInput *test_input); +char *test_input_stringify(const TestInput *test_input, const char *postfix); +cs_arch test_input_get_cs_arch(const TestInput *test_input); +cs_mode test_input_get_cs_mode(const TestInput *test_input); +void test_input_get_cs_option(const TestInput *test_input, cs_opt_type *otype, + cs_opt_value *oval); + +/// A single byte +static const cyaml_schema_value_t byte_schema = { + CYAML_VALUE_UINT(CYAML_FLAG_DEFAULT, uint8_t), +}; + +/// A single option string +static const cyaml_schema_value_t option_schema = { + CYAML_VALUE_STRING(CYAML_FLAG_POINTER, char, 0, CYAML_UNLIMITED), +}; + +static const cyaml_schema_field_t test_input_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("name", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestInput, name, + 0, CYAML_UNLIMITED), + CYAML_FIELD_SEQUENCE("bytes", CYAML_FLAG_POINTER, TestInput, bytes, + &byte_schema, 0, CYAML_UNLIMITED), // 0-MAX bytes + CYAML_FIELD_STRING_PTR("arch", CYAML_FLAG_POINTER, TestInput, arch, 0, + CYAML_UNLIMITED), + CYAML_FIELD_UINT("address", + CYAML_FLAG_SCALAR_PLAIN | CYAML_FLAG_OPTIONAL, + TestInput, address), + CYAML_FIELD_SEQUENCE("options", CYAML_FLAG_POINTER, TestInput, options, + &option_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +/// Data compared to the produced cs_insn. +typedef struct { + uint32_t id; + char *asm_text; // mandatory + char *op_str; + int32_t is_alias; ///< 0 == not given, >0 == true, <0 == false + uint64_t alias_id; + char *mnemonic; + TestDetail *details; +} TestInsnData; + +TestInsnData *test_insn_data_new(); +void test_insn_data_free(TestInsnData *test_insn_data); +TestInsnData *test_insn_data_clone(TestInsnData *test_insn_data); + +static const cyaml_schema_field_t test_insn_data_mapping_schema[] = { + CYAML_FIELD_UINT("id", CYAML_FLAG_SCALAR_PLAIN | CYAML_FLAG_OPTIONAL, + TestInsnData, id), + CYAML_FIELD_STRING_PTR("asm_text", CYAML_FLAG_POINTER, TestInsnData, + asm_text, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "op_str", CYAML_FLAG_POINTER_NULL_STR | CYAML_FLAG_OPTIONAL, + TestInsnData, op_str, 0, CYAML_UNLIMITED), + CYAML_FIELD_UINT("is_alias", CYAML_FLAG_OPTIONAL, TestInsnData, + is_alias), + CYAML_FIELD_INT("alias_id", + CYAML_FLAG_SCALAR_PLAIN | CYAML_FLAG_OPTIONAL, + TestInsnData, alias_id), + CYAML_FIELD_STRING_PTR( + "mnemonic", CYAML_FLAG_POINTER_NULL_STR | CYAML_FLAG_OPTIONAL, + TestInsnData, mnemonic, 0, CYAML_UNLIMITED), + CYAML_FIELD_MAPPING_PTR( + "details", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestInsnData, details, test_detail_mapping_schema), + CYAML_FIELD_END +}; + +/// The expected data for a test. This can hold multiple instructions +/// if enough bytes were given. +typedef struct { + TestInsnData **insns; ///< Zero to N disassembled instructions. + uint32_t insns_count; ///< Filled by cyaml. +} TestExpected; + +TestExpected *test_expected_new(); +void test_expected_free(TestExpected *test_expected); +TestExpected *test_expected_clone(TestExpected *test_expected); +void test_expected_compare(csh *handle, TestExpected *expected, cs_insn *insns, + size_t insns_count, size_t arch_bits); + +static const cyaml_schema_value_t insn_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestInsnData, + test_insn_data_mapping_schema), +}; + +static const cyaml_schema_field_t test_expected_mapping_schema[] = { + CYAML_FIELD_SEQUENCE("insns", CYAML_FLAG_POINTER, TestExpected, insns, + &insn_schema, 0, CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +/// A single test case. +typedef struct { + TestInput *input; ///< Input data for a test case + TestExpected *expected; ///< Expected data of the test case. + bool skip; ///< If set, the test is skipped + char *skip_reason; ///< Reason this test is skipped. +} TestCase; + +TestCase *test_case_new(); +void test_case_free(TestCase *test_case); +TestCase *test_case_clone(TestCase *test_case); + +static const cyaml_schema_field_t test_case_mapping_schema[] = { + CYAML_FIELD_MAPPING_PTR("input", CYAML_FLAG_POINTER, TestCase, input, + test_input_mapping_schema), + CYAML_FIELD_MAPPING_PTR("expected", CYAML_FLAG_POINTER, TestCase, + expected, test_expected_mapping_schema), + CYAML_FIELD_BOOL("skip", CYAML_FLAG_OPTIONAL, TestCase, skip), + CYAML_FIELD_STRING_PTR("skip_reason", + CYAML_FLAG_POINTER_NULL_STR | + CYAML_FLAG_OPTIONAL, + TestCase, skip_reason, 0, CYAML_UNLIMITED), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_case_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestCase, + test_case_mapping_schema), +}; + +typedef struct { + char *filename; ///< Filename. NOT filled by cyaml. + TestCase **test_cases; + uint32_t test_cases_count; +} TestFile; + +TestFile *test_file_new(); +void test_file_free(TestFile *test_file); +TestFile *test_file_clone(TestFile *test_file); + +static const cyaml_schema_field_t test_file_mapping_schema[] = { + CYAML_FIELD_STRING_PTR( + "filename", CYAML_FLAG_OPTIONAL | CYAML_FLAG_POINTER_NULL_STR, + TestFile, filename, 0, 0), + CYAML_FIELD_SEQUENCE("test_cases", CYAML_FLAG_POINTER, TestFile, + test_cases, &test_case_schema, 1, + CYAML_UNLIMITED), // 1-MAX options + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_file_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestFile, + test_file_mapping_schema), +}; + +#endif // TESTCASE_H diff --git a/suite/cstest/include/test_compare.h b/suite/cstest/include/test_compare.h new file mode 100644 index 0000000000..8850d2c1b4 --- /dev/null +++ b/suite/cstest/include/test_compare.h @@ -0,0 +1,230 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_COMPARE_H +#define TEST_COMPARE_H + +#include +#include "test_mapping.h" +#include "../../../utils.h" + +/// An integer encoding a boolean value from the test files. +/// libcyaml saves 0 by default, if an optional value was not set. +/// Due to that, boolean values are represented as integer with the +/// interpretation: +/// +/// = 0 => unset +/// < 0 => false +/// > 0 => true +typedef int32_t tbool; + +/// Compares the @actual bool against the @expected tbool: +/// It returns with @ret_val, if expected is set but the values mismatch. +#define compare_tbool_ret(actual, expected, ret_val) \ + if (expected != 0 && \ + ((actual && expected <= 0) || (!actual && expected >= 0))) { \ + fprintf(stderr, \ + #actual " is %s but expected is %" PRId32 \ + " (=0 unset, >0 true, <0 false)\n", \ + actual ? "true" : "false", expected); \ + return ret_val; \ + } + +/// Compares two unsigned int values. +/// It returns with @ret_val if they mismatch. +#define compare_uint_ret(actual, expected, ret_val) \ + if (((unsigned int)actual) != ((unsigned int)expected)) { \ + fprintf(stderr, \ + #actual " != " #expected ": 0x%" PRIx32 \ + " != 0x%" PRIx32 "\n", \ + actual, expected); \ + return ret_val; \ + } + +/// Compares two uint8_t values. +/// It returns with @ret_val if they mismatch. +#define compare_uint8_ret(actual, expected, ret_val) \ + if (((uint8_t)actual) != ((uint8_t)expected)) { \ + fprintf(stderr, \ + #actual " != " #expected ": %" PRId8 " != %" PRId8 \ + "\n", \ + actual, expected); \ + return ret_val; \ + } + +/// Compares two uint16_t values. +/// It returns with @ret_val if they mismatch. +#define compare_uint16_ret(actual, expected, ret_val) \ + if (((uint16_t)actual) != ((uint16_t)expected)) { \ + fprintf(stderr, \ + #actual " != " #expected ": 0x%" PRIx16 \ + " != 0x%" PRIx16 "\n", \ + actual, expected); \ + return ret_val; \ + } + +/// Compares two uint32_t values. +/// It returns with @ret_val if they mismatch. +#define compare_uint32_ret(actual, expected, ret_val) \ + if (((uint32_t)actual) != ((uint32_t)expected)) { \ + fprintf(stderr, \ + #actual " != " #expected ": 0x%" PRIx32 \ + " != 0x%" PRIx32 "\n", \ + actual, expected); \ + return ret_val; \ + } + +/// Compares two uint64_t values. +/// It returns with @ret_val if they mismatch. +#define compare_uint64_ret(actual, expected, ret_val) \ + if (((uint64_t)actual) != ((uint64_t)expected)) { \ + fprintf(stderr, \ + #actual " != " #expected ": 0x%" PRIx64 \ + " != 0x%" PRIx64 "\n", \ + actual, expected); \ + return ret_val; \ + } + +/// Compares two int values. +/// It returns with @ret_val if they mismatch. +#define compare_int_ret(actual, expected, ret_val) \ + if (((int)actual) != ((int)expected)) { \ + fprintf(stderr, \ + #actual " != " #expected ": 0x%" PRIx32 \ + " != 0x%" PRIx32 "\n", \ + actual, expected); \ + return ret_val; \ + } + +/// Compares two int8_t values. +/// It returns with @ret_val if they mismatch. +#define compare_int8_ret(actual, expected, ret_val) \ + if (((int8_t)actual) != ((int8_t)expected)) { \ + fprintf(stderr, \ + #actual " != " #expected ": 0x%" PRIx8 " != 0x%" PRIx8 \ + "\n", \ + actual, expected); \ + return ret_val; \ + } + +/// Compares two int16_t values. +/// It returns with @ret_val if they mismatch. +#define compare_int16_ret(actual, expected, ret_val) \ + if (((int16_t)actual) != ((int16_t)expected)) { \ + fprintf(stderr, \ + #actual " != " #expected ": 0x%" PRIx16 \ + " != 0x%" PRIx16 "\n", \ + actual, expected); \ + return ret_val; \ + } + +/// Compares two int32_t values. +/// It returns with @ret_val if they mismatch. +#define compare_int32_ret(actual, expected, ret_val) \ + if (((int32_t)actual) != ((int32_t)expected)) { \ + fprintf(stderr, \ + #actual " != " #expected ": 0x%" PRIx32 \ + " != 0x%" PRIx32 "\n", \ + actual, expected); \ + return ret_val; \ + } + +/// Compares two int64_t values. +/// It returns with @ret_val if they mismatch. +#define compare_int64_ret(actual, expected, ret_val) \ + if (((int64_t)actual) != ((int64_t)expected)) { \ + fprintf(stderr, \ + #actual " != " #expected ": 0x%" PRIx64 \ + " != 0x%" PRIx64 "\n", \ + actual, expected); \ + return ret_val; \ + } + +/// Compares two floating point values. +/// It returns with @ret_val if they mismatch. +#define compare_fp_ret(actual, expected, ret_val) \ + if (actual != expected) { \ + fprintf(stderr, #actual " != " #expected ": %f != %f\n", \ + actual, expected); \ + return ret_val; \ + } + +/// Compares enum id. +/// Actual is the value, expected is the enum idetifer as string. +/// It returns with @ret_val if they mismatch. +#define compare_enum_ret(actual, expected, ret_val) \ + if (expected) { \ + bool found = false; \ + uint32_t eval = enum_map_bin_search( \ + cs_enum_map, ARR_SIZE(cs_enum_map), expected, &found); \ + if (expected && (actual != eval || !found)) { \ + fprintf(stderr, \ + #actual " != " #expected ": %" PRId32 \ + " != %s%s\n", \ + actual, expected, \ + found ? "" : " <== id not found"); \ + return ret_val; \ + } \ + } + +/// Checks if all bit flags in @expected are set in @actual. +/// Actual is the value with all bits set. +/// @expected is a list the @len enum identifiers as string. +/// It returns with @ret_val if they mismatch. +#define compare_bit_flags_ret(actual, expected, len, ret_val) \ + if (expected) { \ + for (size_t cmp_i = 0; cmp_i < len; ++cmp_i) { \ + bool found = false; \ + uint32_t eval = enum_map_bin_search( \ + cs_enum_map, ARR_SIZE(cs_enum_map), \ + expected[cmp_i], &found); \ + if (!(actual & eval) || !found) { \ + fprintf(stderr, \ + #actual " != " #expected ": %" PRId32 \ + " != %s%s\n", \ + actual, expected[cmp_i], \ + found ? " <== Flag not set" : \ + " <== id not found"); \ + return ret_val; \ + } \ + } \ + } + +/// Checks if all bit flags in @expected are set in @actual. +/// Actual is the value with all bits set. +/// @expected is a list the @len enum identifiers as string. +/// It returns with @ret_val if they mismatch. +#define compare_bit_flags_64_ret(actual, expected, len, ret_val) \ + if (expected) { \ + for (size_t cmp_i = 0; cmp_i < len; ++cmp_i) { \ + bool found = false; \ + uint64_t eval = enum_map_bin_search( \ + cs_enum_map, ARR_SIZE(cs_enum_map), \ + expected[cmp_i], &found); \ + if (!(actual & eval) || !found) { \ + fprintf(stderr, \ + #actual " != " #expected ": %" PRId64 \ + " != %s%s\n", \ + actual, expected[cmp_i], \ + found ? " <== Flag not set" : \ + " <== id not found"); \ + return ret_val; \ + } \ + } \ + } + +/// Compares register names. +/// Actual is the register id, expected is name as string. +/// It returns with @ret_val if they mismatch. +#define compare_reg_ret(handle, actual, expected, ret_val) \ + if (expected) { \ + const char *reg_name = cs_reg_name(handle, actual); \ + if (expected && !strings_match(reg_name, expected)) { \ + fprintf(stderr, \ + #actual " != " #expected ": '%s' != '%s'\n", \ + reg_name, expected); \ + return ret_val; \ + } \ + } + +#endif // TEST_COMPARE_H diff --git a/suite/cstest/include/test_detail.h b/suite/cstest/include/test_detail.h new file mode 100644 index 0000000000..fe682f0891 --- /dev/null +++ b/suite/cstest/include/test_detail.h @@ -0,0 +1,174 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +/// @file Defines all detail structures to test against and their yaml schemas. +/// The structs currently need to be partially redefined, if they contain unions. +/// And they won't be supported until libcyaml v2: +/// https://github.com/tlsa/libcyaml/issues/186 + +#ifndef TEST_DETAIL_H +#define TEST_DETAIL_H + +#include "test_detail_aarch64.h" +#include "test_detail_arm.h" +#include "test_detail_evm.h" +#include "test_detail_loongarch.h" +#include "test_detail_mos65xx.h" +#include "test_detail_ppc.h" +#include "test_detail_riscv.h" +#include "test_detail_tricore.h" +#include "test_detail_systemz.h" +#include "test_detail_sh.h" +#include "test_detail_sparc.h" +#include "test_detail_alpha.h" +#include "test_detail_bpf.h" +#include "test_detail_hppa.h" +#include "test_detail_xcore.h" +#include "test_detail_mips.h" +#include "test_detail_riscv.h" +#include "test_detail_m680x.h" +#include "test_detail_tms320c64x.h" +#include "test_detail_wasm.h" +#include "test_detail_x86.h" +#include "test_detail_m68k.h" +#include "test_compare.h" +#include +#include + +/// The equivalent to cs_detail in capstone.h +/// but with pointers and no unions. Because cyaml does not support them. +typedef struct { + TestDetailAArch64 *aarch64; + TestDetailARM *arm; + TestDetailPPC *ppc; + TestDetailTriCore *tricore; + TestDetailAlpha *alpha; + TestDetailHPPA *hppa; + TestDetailBPF *bpf; + TestDetailSystemZ *systemz; + TestDetailSparc *sparc; + TestDetailXCore *xcore; + TestDetailSH *sh; + TestDetailMips *mips; + TestDetailRISCV *riscv; + TestDetailM680x *m680x; + TestDetailTMS320c64x *tms320c64x; + TestDetailMos65xx *mos65xx; + TestDetailEVM *evm; + TestDetailLoongArch *loongarch; + TestDetailWASM *wasm; + TestDetailX86 *x86; + TestDetailM68K *m68k; + + char **regs_read; + uint8_t regs_read_count; + + char **regs_write; + uint8_t regs_write_count; + + // Implicit read/writes only + char **regs_impl_read; + uint8_t regs_impl_read_count; + char **regs_impl_write; + uint8_t regs_impl_write_count; + + char **groups; + uint8_t groups_count; + + tbool writeback; +} TestDetail; + +static const cyaml_schema_value_t single_string_schema = { + CYAML_VALUE_STRING(CYAML_FLAG_POINTER, char, 0, CYAML_UNLIMITED), +}; + +static const cyaml_schema_field_t test_detail_mapping_schema[] = { + CYAML_FIELD_MAPPING_PTR( + "aarch64", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail, + aarch64, test_detail_aarch64_mapping_schema), + CYAML_FIELD_MAPPING_PTR("arm", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetail, arm, + test_detail_arm_mapping_schema), + CYAML_FIELD_MAPPING_PTR("ppc", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetail, ppc, + test_detail_ppc_mapping_schema), + CYAML_FIELD_MAPPING_PTR( + "tricore", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail, + tricore, test_detail_tricore_mapping_schema), + CYAML_FIELD_MAPPING_PTR( + "alpha", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail, + alpha, test_detail_alpha_mapping_schema), + CYAML_FIELD_MAPPING_PTR( + "hppa", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail, + hppa, test_detail_hppa_mapping_schema), + CYAML_FIELD_MAPPING_PTR("bpf", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetail, bpf, + test_detail_bpf_mapping_schema), + CYAML_FIELD_MAPPING_PTR( + "systemz", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail, + systemz, test_detail_systemz_mapping_schema), + CYAML_FIELD_MAPPING_PTR( + "sparc", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail, + sparc, test_detail_sparc_mapping_schema), + CYAML_FIELD_MAPPING_PTR( + "xcore", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail, + xcore, test_detail_xcore_mapping_schema), + CYAML_FIELD_MAPPING_PTR("sh", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetail, sh, test_detail_sh_mapping_schema), + CYAML_FIELD_MAPPING_PTR( + "mips", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail, + mips, test_detail_mips_mapping_schema), + CYAML_FIELD_MAPPING_PTR( + "riscv", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail, + riscv, test_detail_riscv_mapping_schema), + CYAML_FIELD_MAPPING_PTR( + "m680x", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail, + m680x, test_detail_m680x_mapping_schema), + CYAML_FIELD_MAPPING_PTR( + "tms320c64x", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetail, tms320c64x, test_detail_tms320c64x_mapping_schema), + CYAML_FIELD_MAPPING_PTR( + "mos65xx", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail, + mos65xx, test_detail_mos65xx_mapping_schema), + CYAML_FIELD_MAPPING_PTR("evm", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetail, evm, + test_detail_evm_mapping_schema), + CYAML_FIELD_MAPPING_PTR( + "loongarch", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetail, loongarch, test_detail_loongarch_mapping_schema), + CYAML_FIELD_MAPPING_PTR( + "wasm", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail, + wasm, test_detail_wasm_mapping_schema), + CYAML_FIELD_MAPPING_PTR("x86", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetail, x86, + test_detail_x86_mapping_schema), + CYAML_FIELD_MAPPING_PTR( + "m68k", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail, + m68k, test_detail_m68k_mapping_schema), + CYAML_FIELD_SEQUENCE("regs_read", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetail, regs_read, &single_string_schema, 0, 255), + CYAML_FIELD_SEQUENCE("regs_write", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetail, regs_write, &single_string_schema, 0, 255), + CYAML_FIELD_SEQUENCE( + "regs_impl_read", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetail, regs_impl_read, &single_string_schema, 0, 255), + CYAML_FIELD_SEQUENCE( + "regs_impl_write", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetail, regs_impl_write, &single_string_schema, 0, 255), + CYAML_FIELD_SEQUENCE("groups", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetail, groups, &single_string_schema, 0, 255), + CYAML_FIELD_INT("writeback", CYAML_FLAG_OPTIONAL, TestDetail, + writeback), + CYAML_FIELD_END +}; + +TestDetail *test_detail_new(); +TestDetail *test_detail_clone(TestDetail *detail); +void test_detail_free(TestDetail *detail); + +bool test_expected_detail(csh *handle, const cs_insn *insn, + TestDetail *expected); + +#endif // TEST_DETAIL_H diff --git a/suite/cstest/include/test_detail_aarch64.h b/suite/cstest/include/test_detail_aarch64.h new file mode 100644 index 0000000000..3df113c4d6 --- /dev/null +++ b/suite/cstest/include/test_detail_aarch64.h @@ -0,0 +1,182 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_AARCH64_H +#define TEST_DETAIL_AARCH64_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *type; + char *tile; + char *slice_reg; + int8_t slice_offset_imm; + int8_t slice_offset_ir_first; + int8_t slice_offset_ir_offset; + bool slice_offset_ir_set; + tbool has_range_offset; + tbool is_vertical; +} TestDetailAArch64SME; + +static const cyaml_schema_field_t test_detail_aarch64_sme_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAArch64SME, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("tile", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAArch64SME, tile, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "slice_reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAArch64SME, slice_reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("slice_offset_imm", CYAML_FLAG_OPTIONAL, + TestDetailAArch64SME, slice_offset_imm), + CYAML_FIELD_INT("slice_offset_ir_first", CYAML_FLAG_OPTIONAL, + TestDetailAArch64SME, slice_offset_ir_first), + CYAML_FIELD_INT("slice_offset_ir_offset", CYAML_FLAG_OPTIONAL, + TestDetailAArch64SME, slice_offset_ir_offset), + CYAML_FIELD_BOOL("slice_offset_ir_set", CYAML_FLAG_OPTIONAL, + TestDetailAArch64SME, slice_offset_ir_set), + CYAML_FIELD_INT("has_range_offset", CYAML_FLAG_OPTIONAL, + TestDetailAArch64SME, has_range_offset), + CYAML_FIELD_INT("is_vertical", CYAML_FLAG_OPTIONAL, + TestDetailAArch64SME, is_vertical), + CYAML_FIELD_END +}; + +typedef struct { + char *type; + char *sub_type; + char *access; + + char *reg; + int64_t imm; + char *mem_base; + char *mem_index; + int32_t mem_disp; + + int8_t imm_range_first; + int8_t imm_range_offset; + double fp; + uint64_t sys_raw_val; + + TestDetailAArch64SME *sme; + + char *pred_reg; + char *pred_vec_select; + int32_t pred_imm_index; + bool pred_imm_index_set; + + char *shift_type; + uint32_t shift_value; + char *ext; + + char *vas; + tbool is_vreg; + int vector_index; + bool vector_index_is_set; + + tbool is_list_member; +} TestDetailAArch64Op; + +static const cyaml_schema_field_t test_detail_aarch64_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "sub_type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, sub_type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("access", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, access, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailAArch64Op, imm), + CYAML_FIELD_STRING_PTR( + "mem_base", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, mem_base, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "mem_index", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, mem_index, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailAArch64Op, + mem_disp), + CYAML_FIELD_INT("imm_range_first", CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, imm_range_first), + CYAML_FIELD_INT("imm_range_offset", CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, imm_range_offset), + CYAML_FIELD_FLOAT("fp", CYAML_FLAG_OPTIONAL, TestDetailAArch64Op, fp), + CYAML_FIELD_UINT("sys_raw_val", CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, sys_raw_val), + CYAML_FIELD_MAPPING_PTR("sme", CYAML_FLAG_OPTIONAL, TestDetailAArch64Op, + sme, test_detail_aarch64_sme_mapping_schema), + CYAML_FIELD_STRING_PTR( + "pred_reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, pred_reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "pred_vec_select", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, pred_vec_select, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("pred_imm_index", CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, pred_imm_index), + CYAML_FIELD_BOOL("pred_imm_index_set", CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, pred_imm_index_set), + CYAML_FIELD_STRING_PTR( + "shift_type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, shift_type, 0, CYAML_UNLIMITED), + CYAML_FIELD_UINT("shift_value", CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, shift_value), + CYAML_FIELD_STRING_PTR("ext", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, ext, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("vas", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, vas, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("is_vreg", CYAML_FLAG_OPTIONAL, TestDetailAArch64Op, + is_vreg), + CYAML_FIELD_INT("vector_index", CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, vector_index), + CYAML_FIELD_BOOL("vector_index_is_set", CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, vector_index_is_set), + CYAML_FIELD_INT("is_list_member", CYAML_FLAG_OPTIONAL, + TestDetailAArch64Op, is_list_member), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_aarch64_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailAArch64Op, + test_detail_aarch64_op_mapping_schema), +}; + +typedef struct { + char *cc; + tbool update_flags; + tbool post_indexed; + TestDetailAArch64Op **operands; + uint32_t operands_count; +} TestDetailAArch64; + +static const cyaml_schema_field_t test_detail_aarch64_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("cc", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAArch64, cc, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("update_flags", CYAML_FLAG_OPTIONAL, TestDetailAArch64, + update_flags), + CYAML_FIELD_INT("post_indexed", CYAML_FLAG_OPTIONAL, TestDetailAArch64, + post_indexed), + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAArch64, operands, &test_detail_aarch64_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailAArch64 *test_detail_aarch64_new(); +TestDetailAArch64 *test_detail_aarch64_clone(TestDetailAArch64 *detail); +void test_detail_aarch64_free(TestDetailAArch64 *detail); + +TestDetailAArch64Op *test_detail_aarch64_op_new(); +TestDetailAArch64Op *test_detail_aarch64_op_clone(TestDetailAArch64Op *detail); +void test_detail_aarch64_op_free(TestDetailAArch64Op *detail); + +TestDetailAArch64SME *test_detail_aarch64_op_sme_new(); +TestDetailAArch64SME *test_detail_aarch64_op_sme_clone(TestDetailAArch64SME *sme); +void test_detail_aarch64_op_sme_free(TestDetailAArch64SME *sme); + +bool test_expected_aarch64(csh *handle, cs_aarch64 *actual, + TestDetailAArch64 *expected); + +#endif // TEST_DETAIL_AARCH64_H diff --git a/suite/cstest/include/test_detail_alpha.h b/suite/cstest/include/test_detail_alpha.h new file mode 100644 index 0000000000..2b105c3301 --- /dev/null +++ b/suite/cstest/include/test_detail_alpha.h @@ -0,0 +1,60 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_ALPHA_H +#define TEST_DETAIL_ALPHA_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *type; + char *access; + + char *reg; + int32_t imm; +} TestDetailAlphaOp; + +static const cyaml_schema_field_t test_detail_alpha_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAlphaOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("access", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAlphaOp, access, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAlphaOp, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailAlphaOp, imm), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_alpha_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailAlphaOp, + test_detail_alpha_op_mapping_schema), +}; + +typedef struct { + TestDetailAlphaOp **operands; + uint32_t operands_count; +} TestDetailAlpha; + +static const cyaml_schema_field_t test_detail_alpha_mapping_schema[] = { + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailAlpha, operands, &test_detail_alpha_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailAlpha *test_detail_alpha_new(); +TestDetailAlpha *test_detail_alpha_clone(const TestDetailAlpha *detail); +void test_detail_alpha_free(TestDetailAlpha *detail); + +TestDetailAlphaOp *test_detail_alpha_op_new(); +TestDetailAlphaOp *test_detail_alpha_op_clone(const TestDetailAlphaOp *detail); +void test_detail_alpha_op_free(TestDetailAlphaOp *detail); + +bool test_expected_alpha(csh *handle, const cs_alpha *actual, + const TestDetailAlpha *expected); + +#endif // TEST_DETAIL_ALPHA_H diff --git a/suite/cstest/include/test_detail_arm.h b/suite/cstest/include/test_detail_arm.h new file mode 100644 index 0000000000..5828258bb8 --- /dev/null +++ b/suite/cstest/include/test_detail_arm.h @@ -0,0 +1,165 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_ARM_H +#define TEST_DETAIL_ARM_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *type; + char *access; + + char *reg; + int64_t imm; + char *setend; + int pred; + double fp; + char *mem_base; + char *mem_index; + int32_t mem_scale; + int32_t mem_disp; + uint32_t mem_align; + char *sys_reg; + char **sys_psr_bits; + uint32_t sys_psr_bits_count; + int sys_sysm; + int sys_msr_mask; + + char *shift_type; + uint32_t shift_value; + + int8_t neon_lane; + int vector_index; + bool vector_index_is_set; + + tbool subtracted; +} TestDetailARMOp; + +static const cyaml_schema_value_t test_detail_arm_op_sys_psr_schema = { + CYAML_VALUE_STRING(CYAML_FLAG_POINTER, char, 0, CYAML_UNLIMITED), +}; + +static const cyaml_schema_field_t test_detail_arm_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailARMOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("access", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailARMOp, access, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailARMOp, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailARMOp, imm), + CYAML_FIELD_STRING_PTR("setend", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailARMOp, setend, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("pred", CYAML_FLAG_OPTIONAL, TestDetailARMOp, pred), + CYAML_FIELD_FLOAT("fp", CYAML_FLAG_OPTIONAL, TestDetailARMOp, fp), + CYAML_FIELD_STRING_PTR("mem_base", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailARMOp, mem_base, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("mem_index", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailARMOp, mem_index, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailARMOp, + mem_disp), + CYAML_FIELD_INT("mem_scale", CYAML_FLAG_OPTIONAL, TestDetailARMOp, + mem_scale), + CYAML_FIELD_UINT("mem_align", CYAML_FLAG_OPTIONAL, TestDetailARMOp, + mem_align), + CYAML_FIELD_STRING_PTR("sys_reg", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailARMOp, sys_reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_SEQUENCE( + "sys_psr_bits", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailARMOp, sys_psr_bits, + &test_detail_arm_op_sys_psr_schema, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("sys_sysm", CYAML_FLAG_OPTIONAL, TestDetailARMOp, + sys_sysm), + CYAML_FIELD_INT("sys_msr_mask", CYAML_FLAG_OPTIONAL, TestDetailARMOp, + sys_msr_mask), + CYAML_FIELD_STRING_PTR("shift_type", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailARMOp, shift_type, 0, CYAML_UNLIMITED), + CYAML_FIELD_UINT("shift_value", CYAML_FLAG_OPTIONAL, TestDetailARMOp, + shift_value), + CYAML_FIELD_INT("neon_lane", CYAML_FLAG_OPTIONAL, TestDetailARMOp, + neon_lane), + CYAML_FIELD_INT("vector_index", CYAML_FLAG_OPTIONAL, TestDetailARMOp, + vector_index), + CYAML_FIELD_BOOL("vector_index_is_set", CYAML_FLAG_OPTIONAL, + TestDetailARMOp, vector_index_is_set), + CYAML_FIELD_INT("subtracted", CYAML_FLAG_OPTIONAL, TestDetailARMOp, + subtracted), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_arm_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailARMOp, + test_detail_arm_op_mapping_schema), +}; + +typedef struct { + int vector_size; + char *vector_data; + char *cps_mode; + char *cps_flag; + char *cc; + char *vcc; + char *mem_barrier; + uint8_t pred_mask; + + tbool usermode; + tbool update_flags; + tbool post_indexed; + + TestDetailARMOp **operands; + uint32_t operands_count; +} TestDetailARM; + +static const cyaml_schema_field_t test_detail_arm_mapping_schema[] = { + CYAML_FIELD_INT("vector_size", CYAML_FLAG_OPTIONAL, TestDetailARM, + vector_size), + CYAML_FIELD_STRING_PTR("vector_data", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailARM, vector_data, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("cps_mode", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailARM, cps_mode, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("cps_flag", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailARM, cps_flag, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("cc", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailARM, cc, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("vcc", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailARM, vcc, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("mem_barrier", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailARM, mem_barrier, 0, CYAML_UNLIMITED), + CYAML_FIELD_UINT("pred_mask", CYAML_FLAG_OPTIONAL, TestDetailARM, + pred_mask), + CYAML_FIELD_INT("usermode", CYAML_FLAG_OPTIONAL, TestDetailARM, + usermode), + CYAML_FIELD_INT("update_flags", CYAML_FLAG_OPTIONAL, TestDetailARM, + update_flags), + CYAML_FIELD_INT("post_indexed", CYAML_FLAG_OPTIONAL, TestDetailARM, + post_indexed), + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailARM, operands, &test_detail_arm_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailARM *test_detail_arm_new(); +TestDetailARM *test_detail_arm_clone(TestDetailARM *detail); +void test_detail_arm_free(TestDetailARM *detail); + +TestDetailARMOp *test_detail_arm_op_new(); +TestDetailARMOp *test_detail_arm_op_clone(TestDetailARMOp *detail); +void test_detail_arm_op_free(TestDetailARMOp *detail); + +bool test_expected_arm(csh *handle, cs_arm *actual, TestDetailARM *expected); + +#endif // TEST_DETAIL_ARM_H diff --git a/suite/cstest/include/test_detail_bpf.h b/suite/cstest/include/test_detail_bpf.h new file mode 100644 index 0000000000..2dd3658d5e --- /dev/null +++ b/suite/cstest/include/test_detail_bpf.h @@ -0,0 +1,76 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_BPF_H +#define TEST_DETAIL_BPF_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *type; + char *access; + + char *reg; + uint64_t imm; + uint32_t off; + uint32_t mmem; + uint32_t msh; + char *ext; + char *mem_base; + uint32_t mem_disp; +} TestDetailBPFOp; + +static const cyaml_schema_field_t test_detail_bpf_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailBPFOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("access", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailBPFOp, access, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailBPFOp, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailBPFOp, imm), + CYAML_FIELD_INT("off", CYAML_FLAG_OPTIONAL, TestDetailBPFOp, off), + CYAML_FIELD_INT("mmem", CYAML_FLAG_OPTIONAL, TestDetailBPFOp, mmem), + CYAML_FIELD_INT("msh", CYAML_FLAG_OPTIONAL, TestDetailBPFOp, msh), + CYAML_FIELD_STRING_PTR("ext", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailBPFOp, ext, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("mem_base", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailBPFOp, mem_base, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailBPFOp, + mem_disp), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_bpf_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailBPFOp, + test_detail_bpf_op_mapping_schema), +}; + +typedef struct { + TestDetailBPFOp **operands; + uint32_t operands_count; +} TestDetailBPF; + +static const cyaml_schema_field_t test_detail_bpf_mapping_schema[] = { + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailBPF, operands, &test_detail_bpf_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailBPF *test_detail_bpf_new(); +TestDetailBPF *test_detail_bpf_clone(const TestDetailBPF *detail); +void test_detail_bpf_free(TestDetailBPF *detail); + +TestDetailBPFOp *test_detail_bpf_op_new(); +TestDetailBPFOp *test_detail_bpf_op_clone(const TestDetailBPFOp *detail); +void test_detail_bpf_op_free(TestDetailBPFOp *detail); + +bool test_expected_bpf(csh *handle, const cs_bpf *actual, + const TestDetailBPF *expected); + +#endif // TEST_DETAIL_BPF_H diff --git a/suite/cstest/include/test_detail_evm.h b/suite/cstest/include/test_detail_evm.h new file mode 100644 index 0000000000..e6c8a59d67 --- /dev/null +++ b/suite/cstest/include/test_detail_evm.h @@ -0,0 +1,30 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_EVM_H +#define TEST_DETAIL_EVM_H + +#include +#include + +typedef struct { + unsigned char pop; + unsigned char push; + unsigned int fee; +} TestDetailEVM; + +static const cyaml_schema_field_t test_detail_evm_mapping_schema[] = { + CYAML_FIELD_UINT("pop", CYAML_FLAG_OPTIONAL, TestDetailEVM, pop), + CYAML_FIELD_UINT("push", CYAML_FLAG_OPTIONAL, TestDetailEVM, push), + CYAML_FIELD_UINT("fee", CYAML_FLAG_OPTIONAL, TestDetailEVM, fee), + CYAML_FIELD_END +}; + +TestDetailEVM *test_detail_evm_new(); +TestDetailEVM *test_detail_evm_clone(const TestDetailEVM *detail); +void test_detail_evm_free(TestDetailEVM *detail); + +bool test_expected_evm(csh *handle, const cs_evm *actual, + const TestDetailEVM *expected); + +#endif // TEST_DETAIL_EVM_H diff --git a/suite/cstest/include/test_detail_hppa.h b/suite/cstest/include/test_detail_hppa.h new file mode 100644 index 0000000000..83a95027d3 --- /dev/null +++ b/suite/cstest/include/test_detail_hppa.h @@ -0,0 +1,72 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_HPPA_H +#define TEST_DETAIL_HPPA_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *type; + char *access; + + char *reg; + int64_t imm; + char *mem_base; + char *mem_space; + char *mem_base_access; +} TestDetailHPPAOp; + +static const cyaml_schema_field_t test_detail_hppa_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailHPPAOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("access", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailHPPAOp, access, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailHPPAOp, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailHPPAOp, imm), + CYAML_FIELD_STRING_PTR("mem_base", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailHPPAOp, mem_base, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("mem_space", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailHPPAOp, mem_space, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "mem_base_access", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailHPPAOp, mem_base_access, 0, CYAML_UNLIMITED), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_hppa_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailHPPAOp, + test_detail_hppa_op_mapping_schema), +}; + +typedef struct { + TestDetailHPPAOp **operands; + uint32_t operands_count; +} TestDetailHPPA; + +static const cyaml_schema_field_t test_detail_hppa_mapping_schema[] = { + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailHPPA, operands, &test_detail_hppa_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailHPPA *test_detail_hppa_new(); +TestDetailHPPA *test_detail_hppa_clone(const TestDetailHPPA *detail); +void test_detail_hppa_free(TestDetailHPPA *detail); + +TestDetailHPPAOp *test_detail_hppa_op_new(); +TestDetailHPPAOp *test_detail_hppa_op_clone(const TestDetailHPPAOp *detail); +void test_detail_hppa_op_free(TestDetailHPPAOp *detail); + +bool test_expected_hppa(csh *handle, const cs_hppa *actual, + const TestDetailHPPA *expected); + +#endif // TEST_DETAIL_HPPA_H diff --git a/suite/cstest/include/test_detail_loongarch.h b/suite/cstest/include/test_detail_loongarch.h new file mode 100644 index 0000000000..2042200594 --- /dev/null +++ b/suite/cstest/include/test_detail_loongarch.h @@ -0,0 +1,77 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_LOONGARCH_H +#define TEST_DETAIL_LOONGARCH_H + +#include +#include + +typedef struct { + char *type; + char *access; + + char *reg; + uint64_t imm; + char *mem_base; + char *mem_index; + int64_t mem_disp; +} TestDetailLoongArchOp; + +static const cyaml_schema_field_t test_detail_loongarch_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailLoongArchOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "access", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailLoongArchOp, access, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailLoongArchOp, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailLoongArchOp, imm), + CYAML_FIELD_STRING_PTR( + "mem_base", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailLoongArchOp, mem_base, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "mem_index", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailLoongArchOp, mem_index, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailLoongArchOp, + mem_disp), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_loongarch_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailLoongArchOp, + test_detail_loongarch_op_mapping_schema), +}; + +typedef struct { + char *format; + TestDetailLoongArchOp **operands; + uint32_t operands_count; +} TestDetailLoongArch; + +static const cyaml_schema_field_t test_detail_loongarch_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("format", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailLoongArch, format, 0, CYAML_UNLIMITED), + CYAML_FIELD_SEQUENCE("operands", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailLoongArch, operands, + &test_detail_loongarch_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailLoongArch *test_detail_loongarch_new(); +TestDetailLoongArch * +test_detail_loongarch_clone(const TestDetailLoongArch *detail); +void test_detail_loongarch_free(TestDetailLoongArch *detail); + +TestDetailLoongArchOp *test_detail_loongarch_op_new(); +TestDetailLoongArchOp * +test_detail_loongarch_op_clone(const TestDetailLoongArchOp *detail); +void test_detail_loongarch_op_free(TestDetailLoongArchOp *detail); + +bool test_expected_loongarch(csh *handle, const cs_loongarch *actual, + const TestDetailLoongArch *expected); + +#endif // TEST_DETAIL_LOONGARCH_H diff --git a/suite/cstest/include/test_detail_m680x.h b/suite/cstest/include/test_detail_m680x.h new file mode 100644 index 0000000000..c68054a8a7 --- /dev/null +++ b/suite/cstest/include/test_detail_m680x.h @@ -0,0 +1,133 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_M680X_H +#define TEST_DETAIL_M680X_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *base_reg; + char *offset_reg; + int16_t offset; + uint16_t offset_addr; + uint8_t offset_bits; + int8_t inc_dec; + char **flags; + uint32_t flags_count; +} TestDetailM680xIdx; + +static const cyaml_schema_value_t flag_schema = { + CYAML_VALUE_STRING(CYAML_FLAG_POINTER, char, 0, CYAML_UNLIMITED), +}; + +static const cyaml_schema_field_t test_detail_m680x_idx_mapping_schema[] = { + CYAML_FIELD_STRING_PTR( + "base_reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM680xIdx, base_reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "offset_reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM680xIdx, offset_reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("offset", CYAML_FLAG_OPTIONAL, TestDetailM680xIdx, + offset), + CYAML_FIELD_UINT("offset_addr", CYAML_FLAG_OPTIONAL, TestDetailM680xIdx, + offset_addr), + CYAML_FIELD_UINT("offset_bits", CYAML_FLAG_OPTIONAL, TestDetailM680xIdx, + offset_bits), + CYAML_FIELD_INT("inc_dec", CYAML_FLAG_OPTIONAL, TestDetailM680xIdx, + inc_dec), + CYAML_FIELD_SEQUENCE("flags", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM680xIdx, flags, &flag_schema, 0, + CYAML_UNLIMITED), // 0-MAX flags + CYAML_FIELD_END +}; + +typedef struct { + char *type; + char *access; + + TestDetailM680xIdx *idx; + char *reg; + int32_t imm; + uint16_t rel_address; + uint16_t ext_address; + int16_t rel_offset; + tbool ext_indirect; + uint8_t direct_addr; + bool direct_addr_set; + uint8_t const_val; + uint8_t size; +} TestDetailM680xOp; + +static const cyaml_schema_field_t test_detail_m680x_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM680xOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("access", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM680xOp, access, 0, CYAML_UNLIMITED), + CYAML_FIELD_MAPPING_PTR("idx", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM680xOp, idx, + test_detail_m680x_idx_mapping_schema), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM680xOp, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailM680xOp, imm), + CYAML_FIELD_UINT("rel_address", CYAML_FLAG_OPTIONAL, TestDetailM680xOp, + rel_address), + CYAML_FIELD_UINT("ext_address", CYAML_FLAG_OPTIONAL, TestDetailM680xOp, + ext_address), + CYAML_FIELD_INT("rel_offset", CYAML_FLAG_OPTIONAL, TestDetailM680xOp, + rel_offset), + CYAML_FIELD_INT("ext_indirect", CYAML_FLAG_OPTIONAL, TestDetailM680xOp, + ext_indirect), + CYAML_FIELD_UINT("direct_addr", CYAML_FLAG_OPTIONAL, TestDetailM680xOp, + direct_addr), + CYAML_FIELD_BOOL("direct_addr_set", CYAML_FLAG_OPTIONAL, + TestDetailM680xOp, direct_addr_set), + CYAML_FIELD_UINT("const_val", CYAML_FLAG_OPTIONAL, TestDetailM680xOp, + const_val), + CYAML_FIELD_UINT("size", CYAML_FLAG_OPTIONAL, TestDetailM680xOp, size), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_m680x_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailM680xOp, + test_detail_m680x_op_mapping_schema), +}; + +typedef struct { + char **flags; + size_t flags_count; + TestDetailM680xOp **operands; + uint32_t operands_count; +} TestDetailM680x; + +static const cyaml_schema_field_t test_detail_m680x_mapping_schema[] = { + CYAML_FIELD_SEQUENCE("flags", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM680x, flags, &flag_schema, 0, + CYAML_UNLIMITED), // 0-MAX flags + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM680x, operands, &test_detail_m680x_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailM680x *test_detail_m680x_new(); +TestDetailM680x *test_detail_m680x_clone(const TestDetailM680x *detail); +void test_detail_m680x_free(TestDetailM680x *detail); + +TestDetailM680xOp *test_detail_m680x_op_new(); +TestDetailM680xOp *test_detail_m680x_op_clone(const TestDetailM680xOp *detail); +void test_detail_m680x_op_free(TestDetailM680xOp *detail); + +TestDetailM680xIdx *test_detail_m680x_idx_new(); +TestDetailM680xIdx * +test_detail_m680x_idx_clone(const TestDetailM680xIdx *detail); +void test_detail_m680x_idx_free(TestDetailM680xIdx *detail); + +bool test_expected_m680x(csh *handle, const cs_m680x *actual, + const TestDetailM680x *expected); + +#endif // TEST_DETAIL_M680X_H diff --git a/suite/cstest/include/test_detail_m68k.h b/suite/cstest/include/test_detail_m68k.h new file mode 100644 index 0000000000..78fd1a18cb --- /dev/null +++ b/suite/cstest/include/test_detail_m68k.h @@ -0,0 +1,151 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_M68K_H +#define TEST_DETAIL_M68K_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *base_reg; + char *index_reg; + char *in_base_reg; + tbool index_size; // -1 == word, 1 == long + int16_t disp; + uint32_t in_disp; + uint32_t out_disp; + uint8_t scale; + uint8_t bitfield; + uint8_t width; + uint8_t offset; +} TestDetailM68KOpMem; + +static const cyaml_schema_field_t test_detail_m68k_op_mem_mapping_schema[] = { + CYAML_FIELD_INT("disp", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem, disp), + CYAML_FIELD_STRING_PTR( + "base_reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM68KOpMem, base_reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "index_reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM68KOpMem, index_reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "in_base_reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM68KOpMem, in_base_reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("index_size", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM68KOpMem, index_size), + CYAML_FIELD_INT("disp", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem, disp), + CYAML_FIELD_UINT("in_disp", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem, + in_disp), + CYAML_FIELD_UINT("out_disp", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem, + out_disp), + CYAML_FIELD_UINT("scale", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem, + scale), + CYAML_FIELD_UINT("bitfield", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem, + bitfield), + CYAML_FIELD_UINT("width", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem, + width), + CYAML_FIELD_UINT("offset", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem, + offset), + CYAML_FIELD_END +}; + +typedef struct { + char *type; + char *address_mode; + + char *reg; + char *reg_pair_0; + char *reg_pair_1; + + uint64_t imm; + int32_t br_disp; + uint8_t br_disp_size; + + uint32_t register_bits; + + double dimm; + float simm; + + TestDetailM68KOpMem *mem; +} TestDetailM68KOp; + +static const cyaml_schema_value_t test_detail_m68k_op_sys_psr_schema = { + CYAML_VALUE_STRING(CYAML_FLAG_POINTER, char, 0, CYAML_UNLIMITED), +}; + +static const cyaml_schema_field_t test_detail_m68k_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM68KOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "address_mode", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM68KOp, address_mode, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM68KOp, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "reg_pair_0", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM68KOp, reg_pair_0, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "reg_pair_1", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM68KOp, reg_pair_1, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailM68KOp, imm), + CYAML_FIELD_INT("br_disp", CYAML_FLAG_OPTIONAL, TestDetailM68KOp, + br_disp), + CYAML_FIELD_UINT("br_disp_size", CYAML_FLAG_OPTIONAL, TestDetailM68KOp, + br_disp_size), + CYAML_FIELD_UINT("register_bits", CYAML_FLAG_OPTIONAL, TestDetailM68KOp, + register_bits), + CYAML_FIELD_FLOAT("dimm", CYAML_FLAG_OPTIONAL, TestDetailM68KOp, dimm), + CYAML_FIELD_FLOAT("simm", CYAML_FLAG_OPTIONAL, TestDetailM68KOp, simm), + CYAML_FIELD_MAPPING_PTR("mem", CYAML_FLAG_OPTIONAL, TestDetailM68KOp, + mem, test_detail_m68k_op_mem_mapping_schema), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_m68k_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailM68KOp, + test_detail_m68k_op_mapping_schema), +}; + +typedef struct { + char *op_size_type; + char *op_size_fpu; + char *op_size_cpu; + + TestDetailM68KOp **operands; + uint32_t operands_count; +} TestDetailM68K; + +static const cyaml_schema_field_t test_detail_m68k_mapping_schema[] = { + CYAML_FIELD_STRING_PTR( + "op_size_type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM68K, op_size_type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("op_size_fpu", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM68K, op_size_fpu, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("op_size_cpu", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM68K, op_size_cpu, 0, CYAML_UNLIMITED), + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM68K, operands, &test_detail_m68k_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailM68K *test_detail_m68k_new(); +TestDetailM68K *test_detail_m68k_clone(TestDetailM68K *detail); +void test_detail_m68k_free(TestDetailM68K *detail); + +TestDetailM68KOp *test_detail_m68k_op_new(); +TestDetailM68KOp *test_detail_m68k_op_clone(TestDetailM68KOp *detail); +void test_detail_m68k_op_free(TestDetailM68KOp *detail); + +TestDetailM68KOpMem *test_detail_m68k_op_mem_new(); +TestDetailM68KOpMem *test_detail_m68k_op_mem_clone(TestDetailM68KOpMem *detail); +void test_detail_m68k_op_mem_free(TestDetailM68KOpMem *detail); + +bool test_expected_m68k(csh *handle, cs_m68k *actual, TestDetailM68K *expected); + +#endif // TEST_DETAIL_M68K_H diff --git a/suite/cstest/include/test_detail_mips.h b/suite/cstest/include/test_detail_mips.h new file mode 100644 index 0000000000..c5491e3461 --- /dev/null +++ b/suite/cstest/include/test_detail_mips.h @@ -0,0 +1,63 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_MIPS_H +#define TEST_DETAIL_MIPS_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *type; + + char *reg; + uint64_t imm; + char *mem_base; + int64_t mem_disp; +} TestDetailMipsOp; + +static const cyaml_schema_field_t test_detail_mips_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailMipsOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailMipsOp, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailMipsOp, imm), + CYAML_FIELD_STRING_PTR("mem_base", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailMipsOp, mem_base, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailMipsOp, + mem_disp), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_mips_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailMipsOp, + test_detail_mips_op_mapping_schema), +}; + +typedef struct { + TestDetailMipsOp **operands; + uint32_t operands_count; +} TestDetailMips; + +static const cyaml_schema_field_t test_detail_mips_mapping_schema[] = { + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailMips, operands, &test_detail_mips_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailMips *test_detail_mips_new(); +TestDetailMips *test_detail_mips_clone(const TestDetailMips *detail); +void test_detail_mips_free(TestDetailMips *detail); + +TestDetailMipsOp *test_detail_mips_op_new(); +TestDetailMipsOp *test_detail_mips_op_clone(const TestDetailMipsOp *detail); +void test_detail_mips_op_free(TestDetailMipsOp *detail); + +bool test_expected_mips(csh *handle, const cs_mips *actual, + const TestDetailMips *expected); + +#endif // TEST_DETAIL_MIPS_H diff --git a/suite/cstest/include/test_detail_mos65xx.h b/suite/cstest/include/test_detail_mos65xx.h new file mode 100644 index 0000000000..f18fe030a5 --- /dev/null +++ b/suite/cstest/include/test_detail_mos65xx.h @@ -0,0 +1,66 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_MOS65XX_H +#define TEST_DETAIL_MOS65XX_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *type; + + char *reg; + uint16_t imm; + uint32_t mem; +} TestDetailMos65xxOp; + +static const cyaml_schema_field_t test_detail_mos65xx_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailMos65xxOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailMos65xxOp, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_UINT("imm", CYAML_FLAG_OPTIONAL, TestDetailMos65xxOp, imm), + CYAML_FIELD_UINT("mem", CYAML_FLAG_OPTIONAL, TestDetailMos65xxOp, mem), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_mos65xx_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailMos65xxOp, + test_detail_mos65xx_op_mapping_schema), +}; + +typedef struct { + char *am; + tbool modifies_flags; + + TestDetailMos65xxOp **operands; + uint32_t operands_count; +} TestDetailMos65xx; + +static const cyaml_schema_field_t test_detail_mos65xx_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("am", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailMos65xx, am, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("modifies_flags", CYAML_FLAG_OPTIONAL, + TestDetailMos65xx, modifies_flags), + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailMos65xx, operands, &test_detail_mos65xx_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailMos65xx *test_detail_mos65xx_new(); +TestDetailMos65xx *test_detail_mos65xx_clone(const TestDetailMos65xx *detail); +void test_detail_mos65xx_free(TestDetailMos65xx *detail); + +TestDetailMos65xxOp *test_detail_mos65xx_op_new(); +TestDetailMos65xxOp * +test_detail_mos65xx_op_clone(const TestDetailMos65xxOp *detail); +void test_detail_mos65xx_op_free(TestDetailMos65xxOp *detail); + +bool test_expected_mos65xx(csh *handle, const cs_mos65xx *actual, + const TestDetailMos65xx *expected); + +#endif // TEST_DETAIL_MOS65XX_H diff --git a/suite/cstest/include/test_detail_ppc.h b/suite/cstest/include/test_detail_ppc.h new file mode 100644 index 0000000000..1c242a0291 --- /dev/null +++ b/suite/cstest/include/test_detail_ppc.h @@ -0,0 +1,124 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_PPC_H +#define TEST_DETAIL_PPC_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *type; + char *access; + + char *reg; + int64_t imm; + char *mem_base; + char *mem_offset; + int32_t mem_disp; +} TestDetailPPCOp; + +static const cyaml_schema_field_t test_detail_ppc_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailPPCOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("access", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailPPCOp, access, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailPPCOp, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailPPCOp, imm), + CYAML_FIELD_STRING_PTR("mem_base", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailPPCOp, mem_base, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("mem_offset", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailPPCOp, mem_offset, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailPPCOp, + mem_disp), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_ppc_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailPPCOp, + test_detail_ppc_op_mapping_schema), +}; + +typedef struct { + uint8_t bo; + bool bo_set; + uint8_t bi; + bool bi_set; + + char *crX_bit; + char *crX; + char *hint; + char *pred_cr; + char *pred_ctr; + char *bh; +} TestDetailPPCBC; + +static const cyaml_schema_field_t test_detail_ppc_bc_mapping_schema[] = { + CYAML_FIELD_INT("bi", CYAML_FLAG_OPTIONAL, TestDetailPPCBC, bi), + CYAML_FIELD_BOOL("bi_set", CYAML_FLAG_OPTIONAL, TestDetailPPCBC, + bi_set), + CYAML_FIELD_INT("bo", CYAML_FLAG_OPTIONAL, TestDetailPPCBC, bo), + CYAML_FIELD_BOOL("bo_set", CYAML_FLAG_OPTIONAL, TestDetailPPCBC, + bo_set), + CYAML_FIELD_STRING_PTR("crX_bit", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailPPCBC, crX_bit, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("crX", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailPPCBC, crX, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("hint", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailPPCBC, hint, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("pred_cr", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailPPCBC, pred_cr, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("pred_ctr", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailPPCBC, pred_ctr, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("bh", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailPPCBC, bh, 0, CYAML_UNLIMITED), + CYAML_FIELD_END +}; + +typedef struct { + TestDetailPPCBC *bc; + tbool update_cr0; + char *format; + TestDetailPPCOp **operands; + uint32_t operands_count; +} TestDetailPPC; + +static const cyaml_schema_field_t test_detail_ppc_mapping_schema[] = { + CYAML_FIELD_MAPPING_PTR("bc", CYAML_FLAG_OPTIONAL, TestDetailPPC, bc, + test_detail_ppc_bc_mapping_schema), + CYAML_FIELD_STRING_PTR("format", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailPPC, format, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("update_cr0", CYAML_FLAG_OPTIONAL, TestDetailPPC, + update_cr0), + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailPPC, operands, &test_detail_ppc_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailPPC *test_detail_ppc_new(); +TestDetailPPC *test_detail_ppc_clone(const TestDetailPPC *detail); +void test_detail_ppc_free(TestDetailPPC *detail); + +TestDetailPPCOp *test_detail_ppc_op_new(); +TestDetailPPCOp *test_detail_ppc_op_clone(const TestDetailPPCOp *detail); +void test_detail_ppc_op_free(TestDetailPPCOp *detail); + +TestDetailPPCBC *test_detail_ppc_bc_new(); +TestDetailPPCBC *test_detail_ppc_bc_clone(const TestDetailPPCBC *detail); +void test_detail_ppc_bc_free(TestDetailPPCBC *detail); + +bool test_expected_ppc(csh *handle, const cs_ppc *actual, + const TestDetailPPC *expected); + +#endif // TEST_DETAIL_PPC_H diff --git a/suite/cstest/include/test_detail_riscv.h b/suite/cstest/include/test_detail_riscv.h new file mode 100644 index 0000000000..0ba4d98e0d --- /dev/null +++ b/suite/cstest/include/test_detail_riscv.h @@ -0,0 +1,67 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_RISCV_H +#define TEST_DETAIL_RISCV_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *type; + char *access; + + char *reg; + uint64_t imm; + char *mem_base; + int64_t mem_disp; +} TestDetailRISCVOp; + +static const cyaml_schema_field_t test_detail_riscv_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailRISCVOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("access", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailRISCVOp, access, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailRISCVOp, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailRISCVOp, imm), + CYAML_FIELD_STRING_PTR("mem_base", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailRISCVOp, mem_base, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailRISCVOp, + mem_disp), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_riscv_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailRISCVOp, + test_detail_riscv_op_mapping_schema), +}; + +typedef struct { + TestDetailRISCVOp **operands; + uint32_t operands_count; +} TestDetailRISCV; + +static const cyaml_schema_field_t test_detail_riscv_mapping_schema[] = { + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailRISCV, operands, &test_detail_riscv_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailRISCV *test_detail_riscv_new(); +TestDetailRISCV *test_detail_riscv_clone(const TestDetailRISCV *detail); +void test_detail_riscv_free(TestDetailRISCV *detail); + +TestDetailRISCVOp *test_detail_riscv_op_new(); +TestDetailRISCVOp *test_detail_riscv_op_clone(const TestDetailRISCVOp *detail); +void test_detail_riscv_op_free(TestDetailRISCVOp *detail); + +bool test_expected_riscv(csh *handle, const cs_riscv *actual, + const TestDetailRISCV *expected); + +#endif // TEST_DETAIL_RISCV_H diff --git a/suite/cstest/include/test_detail_sh.h b/suite/cstest/include/test_detail_sh.h new file mode 100644 index 0000000000..3e6dea96b8 --- /dev/null +++ b/suite/cstest/include/test_detail_sh.h @@ -0,0 +1,67 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_SH_H +#define TEST_DETAIL_SH_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *type; + + char *reg; + uint64_t imm; + char *mem_reg; + char *mem_address; + int32_t mem_disp; +} TestDetailSHOp; + +static const cyaml_schema_field_t test_detail_sh_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSHOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSHOp, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailSHOp, imm), + CYAML_FIELD_STRING_PTR("mem_reg", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSHOp, mem_reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("mem_address", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSHOp, mem_address, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailSHOp, + mem_disp), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_sh_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailSHOp, + test_detail_sh_op_mapping_schema), +}; + +typedef struct { + TestDetailSHOp **operands; + uint32_t operands_count; +} TestDetailSH; + +static const cyaml_schema_field_t test_detail_sh_mapping_schema[] = { + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSH, operands, &test_detail_sh_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailSH *test_detail_sh_new(); +TestDetailSH *test_detail_sh_clone(const TestDetailSH *detail); +void test_detail_sh_free(TestDetailSH *detail); + +TestDetailSHOp *test_detail_sh_op_new(); +TestDetailSHOp *test_detail_sh_op_clone(const TestDetailSHOp *detail); +void test_detail_sh_op_free(TestDetailSHOp *detail); + +bool test_expected_sh(csh *handle, const cs_sh *actual, + const TestDetailSH *expected); + +#endif // TEST_DETAIL_SH_H diff --git a/suite/cstest/include/test_detail_sparc.h b/suite/cstest/include/test_detail_sparc.h new file mode 100644 index 0000000000..8008d94db2 --- /dev/null +++ b/suite/cstest/include/test_detail_sparc.h @@ -0,0 +1,73 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_SPARC_H +#define TEST_DETAIL_SPARC_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *type; + + char *reg; + int64_t imm; + char *mem_base; + char *mem_index; + int32_t mem_disp; +} TestDetailSparcOp; + +static const cyaml_schema_field_t test_detail_sparc_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSparcOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSparcOp, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailSparcOp, imm), + CYAML_FIELD_STRING_PTR("mem_base", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSparcOp, mem_base, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "mem_index", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSparcOp, mem_index, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailSparcOp, + mem_disp), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_sparc_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailSparcOp, + test_detail_sparc_op_mapping_schema), +}; + +typedef struct { + char *cc; + char *hint; + TestDetailSparcOp **operands; + uint32_t operands_count; +} TestDetailSparc; + +static const cyaml_schema_field_t test_detail_sparc_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("cc", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSparc, cc, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("hint", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSparc, hint, 0, CYAML_UNLIMITED), + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSparc, operands, &test_detail_sparc_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailSparc *test_detail_sparc_new(); +TestDetailSparc *test_detail_sparc_clone(const TestDetailSparc *detail); +void test_detail_sparc_free(TestDetailSparc *detail); + +TestDetailSparcOp *test_detail_sparc_op_new(); +TestDetailSparcOp *test_detail_sparc_op_clone(const TestDetailSparcOp *detail); +void test_detail_sparc_op_free(TestDetailSparcOp *detail); + +bool test_expected_sparc(csh *handle, const cs_sparc *actual, + const TestDetailSparc *expected); + +#endif // TEST_DETAIL_SPARC_H diff --git a/suite/cstest/include/test_detail_systemz.h b/suite/cstest/include/test_detail_systemz.h new file mode 100644 index 0000000000..d7c0231a08 --- /dev/null +++ b/suite/cstest/include/test_detail_systemz.h @@ -0,0 +1,71 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_SYSTEMZ_H +#define TEST_DETAIL_SYSTEMZ_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *type; + + char *reg; + int64_t imm; + char *mem_base; + char *mem_index; + int64_t mem_disp; + uint64_t mem_length; +} TestDetailSystemZOp; + +static const cyaml_schema_field_t test_detail_systemz_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSystemZOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSystemZOp, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailSystemZOp, imm), + CYAML_FIELD_STRING_PTR( + "mem_base", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSystemZOp, mem_base, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "mem_index", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSystemZOp, mem_index, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailSystemZOp, + mem_disp), + CYAML_FIELD_INT("mem_length", CYAML_FLAG_OPTIONAL, TestDetailSystemZOp, + mem_length), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_systemz_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailSystemZOp, + test_detail_systemz_op_mapping_schema), +}; + +typedef struct { + TestDetailSystemZOp **operands; + uint32_t operands_count; +} TestDetailSystemZ; + +static const cyaml_schema_field_t test_detail_systemz_mapping_schema[] = { + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSystemZ, operands, &test_detail_systemz_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailSystemZ *test_detail_systemz_new(); +TestDetailSystemZ *test_detail_systemz_clone(const TestDetailSystemZ *detail); +void test_detail_systemz_free(TestDetailSystemZ *detail); + +TestDetailSystemZOp *test_detail_systemz_op_new(); +TestDetailSystemZOp * +test_detail_systemz_op_clone(const TestDetailSystemZOp *detail); +void test_detail_systemz_op_free(TestDetailSystemZOp *detail); + +bool test_expected_systemz(csh *handle, const cs_sysz *actual, + const TestDetailSystemZ *expected); + +#endif // TEST_DETAIL_SYSTEMZ_H diff --git a/suite/cstest/include/test_detail_tms320c64x.h b/suite/cstest/include/test_detail_tms320c64x.h new file mode 100644 index 0000000000..b5fa96e1e2 --- /dev/null +++ b/suite/cstest/include/test_detail_tms320c64x.h @@ -0,0 +1,134 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_TMS320C64X_H +#define TEST_DETAIL_TMS320C64X_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *type; + + char *reg; + char *reg_pair_0; + char *reg_pair_1; + int32_t imm; + char *mem_base; + tbool mem_scaled; + char *mem_disptype; + char *mem_direction; + char *mem_modify; + char *mem_disp_reg; + unsigned int mem_disp_const; + unsigned int mem_unit; +} TestDetailTMS320c64xOp; + +static const cyaml_schema_value_t test_detail_tms320c64x_op_sys_psr_schema = { + CYAML_VALUE_STRING(CYAML_FLAG_POINTER, char, 0, CYAML_UNLIMITED), +}; + +static const cyaml_schema_field_t test_detail_tms320c64x_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64xOp, type, 0, + CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64xOp, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "reg_pair_0", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64xOp, reg_pair_0, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "reg_pair_1", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64xOp, reg_pair_1, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailTMS320c64xOp, + imm), + CYAML_FIELD_INT("mem_scaled", CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64xOp, mem_scaled), + CYAML_FIELD_STRING_PTR( + "mem_base", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64xOp, mem_base, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "mem_disptype", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64xOp, mem_disptype, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "mem_direction", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64xOp, mem_direction, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "mem_modify", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64xOp, mem_modify, 0, CYAML_UNLIMITED), + CYAML_FIELD_UINT("mem_disp_const", CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64xOp, mem_disp_const), + CYAML_FIELD_STRING_PTR( + "mem_disp_reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64xOp, mem_disp_reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_UINT("mem_unit", CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64xOp, mem_unit), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_tms320c64x_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailTMS320c64xOp, + test_detail_tms320c64x_op_mapping_schema), +}; + +typedef struct { + char *cond_reg; + tbool cond_zero; + + char *funit_unit; + uint8_t funit_side; + bool funit_side_set; + uint8_t funit_crosspath; + bool funit_crosspath_set; + + int8_t parallel; + bool parallel_set; + + TestDetailTMS320c64xOp **operands; + uint32_t operands_count; +} TestDetailTMS320c64x; + +static const cyaml_schema_field_t test_detail_tms320c64x_mapping_schema[] = { + CYAML_FIELD_STRING_PTR( + "cond_reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64x, cond_reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("cond_zero", CYAML_FLAG_OPTIONAL, TestDetailTMS320c64x, + cond_zero), + CYAML_FIELD_STRING_PTR( + "funit_unit", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64x, funit_unit, 0, CYAML_UNLIMITED), + CYAML_FIELD_UINT("funit_side", CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64x, funit_side), + CYAML_FIELD_BOOL("funit_side_set", CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64x, funit_side_set), + CYAML_FIELD_UINT("funit_crosspath", CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64x, funit_crosspath), + CYAML_FIELD_BOOL("funit_crosspath_set", CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64x, funit_crosspath_set), + CYAML_FIELD_INT("parallel", CYAML_FLAG_OPTIONAL, TestDetailTMS320c64x, + parallel), + CYAML_FIELD_BOOL("parallel_set", CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64x, parallel_set), + CYAML_FIELD_SEQUENCE("operands", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailTMS320c64x, operands, + &test_detail_tms320c64x_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailTMS320c64x *test_detail_tms320c64x_new(); +TestDetailTMS320c64x * +test_detail_tms320c64x_clone(TestDetailTMS320c64x *detail); +void test_detail_tms320c64x_free(TestDetailTMS320c64x *detail); + +TestDetailTMS320c64xOp *test_detail_tms320c64x_op_new(); +TestDetailTMS320c64xOp * +test_detail_tms320c64x_op_clone(TestDetailTMS320c64xOp *detail); +void test_detail_tms320c64x_op_free(TestDetailTMS320c64xOp *detail); + +bool test_expected_tms320c64x(csh *handle, cs_tms320c64x *actual, + TestDetailTMS320c64x *expected); + +#endif // TEST_DETAIL_TMS320C64X_H diff --git a/suite/cstest/include/test_detail_tricore.h b/suite/cstest/include/test_detail_tricore.h new file mode 100644 index 0000000000..a31e6f8167 --- /dev/null +++ b/suite/cstest/include/test_detail_tricore.h @@ -0,0 +1,71 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_TRICORE_H +#define TEST_DETAIL_TRICORE_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *type; + char *access; + + char *reg; + int64_t imm; + char *mem_base; + int64_t mem_disp; +} TestDetailTriCoreOp; + +static const cyaml_schema_field_t test_detail_tricore_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailTriCoreOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("access", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailTriCoreOp, access, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailTriCoreOp, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailTriCoreOp, imm), + CYAML_FIELD_STRING_PTR( + "mem_base", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailTriCoreOp, mem_base, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailTriCoreOp, + mem_disp), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_tricore_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailTriCoreOp, + test_detail_tricore_op_mapping_schema), +}; + +typedef struct { + tbool update_flags; + TestDetailTriCoreOp **operands; + uint32_t operands_count; +} TestDetailTriCore; + +static const cyaml_schema_field_t test_detail_tricore_mapping_schema[] = { + CYAML_FIELD_INT("update_flags", CYAML_FLAG_OPTIONAL, TestDetailTriCore, + update_flags), + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailTriCore, operands, &test_detail_tricore_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailTriCore *test_detail_tricore_new(); +TestDetailTriCore *test_detail_tricore_clone(const TestDetailTriCore *detail); +void test_detail_tricore_free(TestDetailTriCore *detail); + +TestDetailTriCoreOp *test_detail_tricore_op_new(); +TestDetailTriCoreOp * +test_detail_tricore_op_clone(const TestDetailTriCoreOp *detail); +void test_detail_tricore_op_free(TestDetailTriCoreOp *detail); + +bool test_expected_tricore(csh *handle, const cs_tricore *actual, + const TestDetailTriCore *expected); + +#endif // TEST_DETAIL_TRICORE_H diff --git a/suite/cstest/include/test_detail_wasm.h b/suite/cstest/include/test_detail_wasm.h new file mode 100644 index 0000000000..814fe95a82 --- /dev/null +++ b/suite/cstest/include/test_detail_wasm.h @@ -0,0 +1,82 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_WASM_H +#define TEST_DETAIL_WASM_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *type; + + uint32_t size; + int8_t int7; + uint32_t varuint32; + uint64_t varuint64; + uint32_t uint32; + uint64_t uint64; + uint32_t immediate_0; + uint32_t immediate_1; + uint32_t brt_length; + uint64_t brt_address; + uint32_t brt_default_target; +} TestDetailWASMOp; + +static const cyaml_schema_field_t test_detail_wasm_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailWASMOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_UINT("size", CYAML_FLAG_OPTIONAL, TestDetailWASMOp, size), + CYAML_FIELD_INT("int7", CYAML_FLAG_OPTIONAL, TestDetailWASMOp, int7), + CYAML_FIELD_UINT("varuint32", CYAML_FLAG_OPTIONAL, TestDetailWASMOp, + varuint32), + CYAML_FIELD_UINT("varuint64", CYAML_FLAG_OPTIONAL, TestDetailWASMOp, + varuint64), + CYAML_FIELD_UINT("uint64", CYAML_FLAG_OPTIONAL, TestDetailWASMOp, + uint64), + CYAML_FIELD_UINT("uint32", CYAML_FLAG_OPTIONAL, TestDetailWASMOp, + uint32), + CYAML_FIELD_UINT("immediate_0", CYAML_FLAG_OPTIONAL, TestDetailWASMOp, + immediate_0), + CYAML_FIELD_UINT("immediate_1", CYAML_FLAG_OPTIONAL, TestDetailWASMOp, + immediate_1), + CYAML_FIELD_UINT("brt_length", CYAML_FLAG_OPTIONAL, TestDetailWASMOp, + brt_length), + CYAML_FIELD_UINT("brt_address", CYAML_FLAG_OPTIONAL, TestDetailWASMOp, + brt_address), + CYAML_FIELD_UINT("brt_default_target", CYAML_FLAG_OPTIONAL, + TestDetailWASMOp, brt_default_target), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_wasm_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailWASMOp, + test_detail_wasm_op_mapping_schema), +}; + +typedef struct { + TestDetailWASMOp **operands; + uint32_t operands_count; +} TestDetailWASM; + +static const cyaml_schema_field_t test_detail_wasm_mapping_schema[] = { + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailWASM, operands, &test_detail_wasm_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailWASM *test_detail_wasm_new(); +TestDetailWASM *test_detail_wasm_clone(const TestDetailWASM *detail); +void test_detail_wasm_free(TestDetailWASM *detail); + +TestDetailWASMOp *test_detail_wasm_op_new(); +TestDetailWASMOp *test_detail_wasm_op_clone(const TestDetailWASMOp *detail); +void test_detail_wasm_op_free(TestDetailWASMOp *detail); + +bool test_expected_wasm(csh *handle, const cs_wasm *actual, + const TestDetailWASM *expected); + +#endif // TEST_DETAIL_WASM_H diff --git a/suite/cstest/include/test_detail_x86.h b/suite/cstest/include/test_detail_x86.h new file mode 100644 index 0000000000..3dd51b833e --- /dev/null +++ b/suite/cstest/include/test_detail_x86.h @@ -0,0 +1,178 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_X86_H +#define TEST_DETAIL_X86_H + +#include "test_compare.h" +#include +#include +#include + +typedef struct { + char *type; + char *access; + uint8_t size; + + char *reg; + int64_t imm; + char *mem_segment; + char *mem_base; + char *mem_index; + int mem_scale; + int64_t mem_disp; + + char *avx_bcast; + tbool avx_zero_opmask; +} TestDetailX86Op; + +static const cyaml_schema_value_t test_detail_x86_op_sys_psr_schema = { + CYAML_VALUE_STRING(CYAML_FLAG_POINTER, char, 0, CYAML_UNLIMITED), +}; + +static const cyaml_schema_field_t test_detail_x86_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailX86Op, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("access", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailX86Op, access, 0, CYAML_UNLIMITED), + CYAML_FIELD_UINT("size", CYAML_FLAG_OPTIONAL, TestDetailX86Op, size), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailX86Op, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailX86Op, imm), + CYAML_FIELD_STRING_PTR( + "mem_segment", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailX86Op, mem_segment, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("mem_base", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailX86Op, mem_base, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("mem_index", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailX86Op, mem_index, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailX86Op, + mem_disp), + CYAML_FIELD_INT("mem_scale", CYAML_FLAG_OPTIONAL, TestDetailX86Op, + mem_scale), + CYAML_FIELD_INT("avx_zero_opmask", CYAML_FLAG_OPTIONAL, TestDetailX86Op, + avx_zero_opmask), + CYAML_FIELD_STRING_PTR("avx_bcast", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailX86Op, avx_bcast, 0, CYAML_UNLIMITED), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_x86_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailX86Op, + test_detail_x86_op_mapping_schema), +}; + +static const cyaml_schema_value_t test_detail_x86_opcode_schema = { + CYAML_VALUE_UINT(CYAML_FLAG_DEFAULT, uint8_t), +}; + +static const cyaml_schema_value_t test_detail_x86_string_schema = { + CYAML_VALUE_STRING(CYAML_FLAG_POINTER, char, 0, CYAML_UNLIMITED), +}; + +typedef struct { + char *sib_index; + char *sib_base; + char *xop_cc; + char *sse_cc; + char *avx_cc; + char *avx_rm; + + char *prefix[4]; + uint8_t opcode[4]; + + uint8_t rex; + uint8_t addr_size; + uint8_t modrm; + uint8_t sib; + int64_t disp; + int8_t sib_scale; + tbool avx_sae; + + char **eflags; + size_t eflags_count; + char **fpu_flags; + size_t fpu_flags_count; + + uint8_t enc_modrm_offset; + uint8_t enc_disp_offset; + uint8_t enc_disp_size; + uint8_t enc_imm_offset; + uint8_t enc_imm_size; + + TestDetailX86Op **operands; + uint32_t operands_count; +} TestDetailX86; + +static const cyaml_schema_field_t test_detail_x86_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("sib_index", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailX86, sib_index, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("sib_base", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailX86, sib_base, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("xop_cc", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailX86, xop_cc, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("sse_cc", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailX86, sse_cc, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("avx_cc", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailX86, avx_cc, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("avx_rm", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailX86, avx_rm, 0, CYAML_UNLIMITED), + CYAML_FIELD_SEQUENCE_FIXED("prefix", CYAML_FLAG_OPTIONAL, TestDetailX86, + prefix, &test_detail_x86_string_schema, 4), + CYAML_FIELD_SEQUENCE_FIXED("opcode", CYAML_FLAG_OPTIONAL, TestDetailX86, + opcode, &test_detail_x86_opcode_schema, 4), + CYAML_FIELD_UINT("rex", CYAML_FLAG_OPTIONAL, TestDetailX86, rex), + CYAML_FIELD_UINT("addr_size", CYAML_FLAG_OPTIONAL, TestDetailX86, + addr_size), + CYAML_FIELD_UINT("modrm", CYAML_FLAG_OPTIONAL, TestDetailX86, modrm), + CYAML_FIELD_UINT("sib", CYAML_FLAG_OPTIONAL, TestDetailX86, sib), + CYAML_FIELD_INT("disp", CYAML_FLAG_OPTIONAL, TestDetailX86, disp), + CYAML_FIELD_INT("sib_scale", CYAML_FLAG_OPTIONAL, TestDetailX86, + sib_scale), + CYAML_FIELD_INT("avx_sae", CYAML_FLAG_OPTIONAL, TestDetailX86, avx_sae), + CYAML_FIELD_SEQUENCE("eflags", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailX86, eflags, + &test_detail_x86_string_schema, 0, + CYAML_UNLIMITED), + CYAML_FIELD_SEQUENCE( + "fpu_flags", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailX86, fpu_flags, &test_detail_x86_string_schema, 0, + CYAML_UNLIMITED), + CYAML_FIELD_UINT("enc_modrm_offset", CYAML_FLAG_OPTIONAL, TestDetailX86, + enc_modrm_offset), + CYAML_FIELD_UINT("enc_disp_offset", CYAML_FLAG_OPTIONAL, TestDetailX86, + enc_disp_offset), + CYAML_FIELD_UINT("enc_disp_size", CYAML_FLAG_OPTIONAL, TestDetailX86, + enc_disp_size), + CYAML_FIELD_UINT("enc_imm_offset", CYAML_FLAG_OPTIONAL, TestDetailX86, + enc_imm_offset), + CYAML_FIELD_UINT("enc_imm_size", CYAML_FLAG_OPTIONAL, TestDetailX86, + enc_imm_size), + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailX86, operands, &test_detail_x86_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailX86 *test_detail_x86_new(); +TestDetailX86 *test_detail_x86_clone(TestDetailX86 *detail); +void test_detail_x86_free(TestDetailX86 *detail); + +TestDetailX86Op *test_detail_x86_op_new(); +TestDetailX86Op *test_detail_x86_op_clone(TestDetailX86Op *detail); +void test_detail_x86_op_free(TestDetailX86Op *detail); + +bool test_expected_x86(csh *handle, cs_x86 *actual, TestDetailX86 *expected); + +#endif // TEST_DETAIL_X86_H diff --git a/suite/cstest/include/test_detail_xcore.h b/suite/cstest/include/test_detail_xcore.h new file mode 100644 index 0000000000..9a8976726a --- /dev/null +++ b/suite/cstest/include/test_detail_xcore.h @@ -0,0 +1,70 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_DETAIL_XCORE_H +#define TEST_DETAIL_XCORE_H + +#include "test_compare.h" +#include +#include + +typedef struct { + char *type; + + char *reg; + int32_t imm; + char *mem_base; + char *mem_index; + int32_t mem_disp; + int32_t mem_direct; +} TestDetailXCoreOp; + +static const cyaml_schema_field_t test_detail_xcore_op_mapping_schema[] = { + CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailXCoreOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailXCoreOp, reg, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailXCoreOp, imm), + CYAML_FIELD_STRING_PTR("mem_base", + CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailXCoreOp, mem_base, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR( + "mem_index", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailXCoreOp, mem_index, 0, CYAML_UNLIMITED), + CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailXCoreOp, + mem_disp), + CYAML_FIELD_INT("mem_direct", CYAML_FLAG_OPTIONAL, TestDetailXCoreOp, + mem_direct), + CYAML_FIELD_END +}; + +static const cyaml_schema_value_t test_detail_xcore_op_schema = { + CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailXCoreOp, + test_detail_xcore_op_mapping_schema), +}; + +typedef struct { + TestDetailXCoreOp **operands; + uint32_t operands_count; +} TestDetailXCore; + +static const cyaml_schema_field_t test_detail_xcore_mapping_schema[] = { + CYAML_FIELD_SEQUENCE( + "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailXCore, operands, &test_detail_xcore_op_schema, 0, + CYAML_UNLIMITED), // 0-MAX options + CYAML_FIELD_END +}; + +TestDetailXCore *test_detail_xcore_new(); +TestDetailXCore *test_detail_xcore_clone(const TestDetailXCore *detail); +void test_detail_xcore_free(TestDetailXCore *detail); + +TestDetailXCoreOp *test_detail_xcore_op_new(); +TestDetailXCoreOp *test_detail_xcore_op_clone(const TestDetailXCoreOp *detail); +void test_detail_xcore_op_free(TestDetailXCoreOp *detail); + +bool test_expected_xcore(csh *handle, const cs_xcore *actual, + const TestDetailXCore *expected); + +#endif // TEST_DETAIL_XCORE_H diff --git a/suite/cstest/include/test_mapping.h b/suite/cstest/include/test_mapping.h new file mode 100644 index 0000000000..7ef546b52d --- /dev/null +++ b/suite/cstest/include/test_mapping.h @@ -0,0 +1,1348 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TEST_MAPPING_H +#define TEST_MAPPING_H + +#include "../../../Mapping.h" +#include + +/// Maps a string to an option +typedef struct { + const char *str; + cs_opt opt; +} TestOptionMapEntry; + +/// REMEMBER TO SORT AFTER EDIT +static const cs_enum_id_map test_arch_map[] = { + { .str = "AArch64", .val = CS_ARCH_AARCH64 }, + { .str = "CS_ARCH_AARCH64", .val = CS_ARCH_AARCH64 }, + { .str = "CS_ARCH_ALPHA", .val = CS_ARCH_ALPHA }, + { .str = "CS_ARCH_ARM", .val = CS_ARCH_ARM }, + { .str = "CS_ARCH_BPF", .val = CS_ARCH_BPF }, + { .str = "CS_ARCH_EVM", .val = CS_ARCH_EVM }, + { .str = "CS_ARCH_HPPA", .val = CS_ARCH_HPPA }, + { .str = "CS_ARCH_LOONGARCH", .val = CS_ARCH_LOONGARCH }, + { .str = "CS_ARCH_M680X", .val = CS_ARCH_M680X }, + { .str = "CS_ARCH_M68K", .val = CS_ARCH_M68K }, + { .str = "CS_ARCH_MIPS", .val = CS_ARCH_MIPS }, + { .str = "CS_ARCH_MOS65XX", .val = CS_ARCH_MOS65XX }, + { .str = "CS_ARCH_PPC", .val = CS_ARCH_PPC }, + { .str = "CS_ARCH_RISCV", .val = CS_ARCH_RISCV }, + { .str = "CS_ARCH_SH", .val = CS_ARCH_SH }, + { .str = "CS_ARCH_SPARC", .val = CS_ARCH_SPARC }, + { .str = "CS_ARCH_SYSZ", .val = CS_ARCH_SYSZ }, + { .str = "CS_ARCH_TMS320C64X", .val = CS_ARCH_TMS320C64X }, + { .str = "CS_ARCH_TRICORE", .val = CS_ARCH_TRICORE }, + { .str = "CS_ARCH_WASM", .val = CS_ARCH_WASM }, + { .str = "CS_ARCH_X86", .val = CS_ARCH_X86 }, + { .str = "CS_ARCH_XCORE", .val = CS_ARCH_XCORE }, + { .str = "aarch64", .val = CS_ARCH_AARCH64 }, + { .str = "alpha", .val = CS_ARCH_ALPHA }, + { .str = "arm", .val = CS_ARCH_ARM }, + { .str = "bpf", .val = CS_ARCH_BPF }, + { .str = "evm", .val = CS_ARCH_EVM }, + { .str = "hppa", .val = CS_ARCH_HPPA }, + { .str = "loongarch", .val = CS_ARCH_LOONGARCH }, + { .str = "m680x", .val = CS_ARCH_M680X }, + { .str = "m68k", .val = CS_ARCH_M68K }, + { .str = "mips", .val = CS_ARCH_MIPS }, + { .str = "mos65xx", .val = CS_ARCH_MOS65XX }, + { .str = "ppc", .val = CS_ARCH_PPC }, + { .str = "riscv", .val = CS_ARCH_RISCV }, + { .str = "sh", .val = CS_ARCH_SH }, + { .str = "sparc", .val = CS_ARCH_SPARC }, + { .str = "systemz", .val = CS_ARCH_SYSZ }, + { .str = "tms320c64x", .val = CS_ARCH_TMS320C64X }, + { .str = "tricore", .val = CS_ARCH_TRICORE }, + { .str = "wasm", .val = CS_ARCH_WASM }, + { .str = "x86", .val = CS_ARCH_X86 }, + { .str = "xcore", .val = CS_ARCH_XCORE }, +}; + +/// REMEMBER TO SORT AFTER EDIT +static const cs_enum_id_map test_mode_map[] = { + { .str = "CS_MODE_16", .val = CS_MODE_16 }, + { .str = "CS_MODE_32", .val = CS_MODE_32 }, + { .str = "CS_MODE_64", .val = CS_MODE_64 }, + { .str = "CS_MODE_ARM", .val = CS_MODE_ARM }, + { .str = "CS_MODE_BIG_ENDIAN", .val = CS_MODE_BIG_ENDIAN }, + { .str = "CS_MODE_BOOKE", .val = CS_MODE_BOOKE }, + { .str = "CS_MODE_BPF_CLASSIC", .val = CS_MODE_BPF_CLASSIC }, + { .str = "CS_MODE_BPF_EXTENDED", .val = CS_MODE_BPF_EXTENDED }, + { .str = "CS_MODE_HPPA_11", .val = CS_MODE_HPPA_11 }, + { .str = "CS_MODE_HPPA_20", .val = CS_MODE_HPPA_20 }, + { .str = "CS_MODE_HPPA_20W", .val = CS_MODE_HPPA_20W }, + { .str = "CS_MODE_LITTLE_ENDIAN", .val = CS_MODE_LITTLE_ENDIAN }, + { .str = "CS_MODE_LOONGARCH32", .val = CS_MODE_LOONGARCH32 }, + { .str = "CS_MODE_LOONGARCH64", .val = CS_MODE_LOONGARCH64 }, + { .str = "CS_MODE_M680X_6301", .val = CS_MODE_M680X_6301 }, + { .str = "CS_MODE_M680X_6309", .val = CS_MODE_M680X_6309 }, + { .str = "CS_MODE_M680X_6800", .val = CS_MODE_M680X_6800 }, + { .str = "CS_MODE_M680X_6801", .val = CS_MODE_M680X_6801 }, + { .str = "CS_MODE_M680X_6805", .val = CS_MODE_M680X_6805 }, + { .str = "CS_MODE_M680X_6808", .val = CS_MODE_M680X_6808 }, + { .str = "CS_MODE_M680X_6809", .val = CS_MODE_M680X_6809 }, + { .str = "CS_MODE_M680X_6811", .val = CS_MODE_M680X_6811 }, + { .str = "CS_MODE_M680X_CPU12", .val = CS_MODE_M680X_CPU12 }, + { .str = "CS_MODE_M680X_HCS08", .val = CS_MODE_M680X_HCS08 }, + { .str = "CS_MODE_M68K_000", .val = CS_MODE_M68K_000 }, + { .str = "CS_MODE_M68K_010", .val = CS_MODE_M68K_010 }, + { .str = "CS_MODE_M68K_020", .val = CS_MODE_M68K_020 }, + { .str = "CS_MODE_M68K_030", .val = CS_MODE_M68K_030 }, + { .str = "CS_MODE_M68K_040", .val = CS_MODE_M68K_040 }, + { .str = "CS_MODE_M68K_060", .val = CS_MODE_M68K_060 }, + { .str = "CS_MODE_MCLASS", .val = CS_MODE_MCLASS }, + { .str = "CS_MODE_MICRO", .val = CS_MODE_MICRO }, + { .str = "CS_MODE_MIPS2", .val = CS_MODE_MIPS2 }, + { .str = "CS_MODE_MIPS3", .val = CS_MODE_MIPS3 }, + { .str = "CS_MODE_MIPS32", .val = CS_MODE_MIPS32 }, + { .str = "CS_MODE_MIPS32R6", .val = CS_MODE_MIPS32R6 }, + { .str = "CS_MODE_MIPS64", .val = CS_MODE_MIPS64 }, + { .str = "CS_MODE_MOS65XX_6502", .val = CS_MODE_MOS65XX_6502 }, + { .str = "CS_MODE_MOS65XX_65816", .val = CS_MODE_MOS65XX_65816 }, + { .str = "CS_MODE_MOS65XX_65816_LONG_M", + .val = CS_MODE_MOS65XX_65816_LONG_M }, + { .str = "CS_MODE_MOS65XX_65816_LONG_MX", + .val = CS_MODE_MOS65XX_65816_LONG_M | CS_MODE_MOS65XX_65816_LONG_X }, + { .str = "CS_MODE_MOS65XX_65816_LONG_X", + .val = CS_MODE_MOS65XX_65816_LONG_X }, + { .str = "CS_MODE_MOS65XX_65C02", .val = CS_MODE_MOS65XX_65C02 }, + { .str = "CS_MODE_MOS65XX_W65C02", .val = CS_MODE_MOS65XX_W65C02 }, + { .str = "CS_MODE_PS", .val = CS_MODE_PS }, + { .str = "CS_MODE_QPX", .val = CS_MODE_QPX }, + { .str = "CS_MODE_RISCV32", .val = CS_MODE_RISCV32 }, + { .str = "CS_MODE_RISCV64", .val = CS_MODE_RISCV64 }, + { .str = "CS_MODE_RISCVC", .val = CS_MODE_RISCVC }, + { .str = "CS_MODE_SH2", .val = CS_MODE_SH2 }, + { .str = "CS_MODE_SH2A", .val = CS_MODE_SH2A }, + { .str = "CS_MODE_SH3", .val = CS_MODE_SH3 }, + { .str = "CS_MODE_SH4", .val = CS_MODE_SH4 }, + { .str = "CS_MODE_SH4A", .val = CS_MODE_SH4A }, + { .str = "CS_MODE_SHDSP", .val = CS_MODE_SHDSP }, + { .str = "CS_MODE_SHFPU", .val = CS_MODE_SHFPU }, + { .str = "CS_MODE_SPE", .val = CS_MODE_SPE }, + { .str = "CS_MODE_THUMB", .val = CS_MODE_THUMB }, + { .str = "CS_MODE_TRICORE_110", .val = CS_MODE_TRICORE_110 }, + { .str = "CS_MODE_TRICORE_120", .val = CS_MODE_TRICORE_120 }, + { .str = "CS_MODE_TRICORE_130", .val = CS_MODE_TRICORE_130 }, + { .str = "CS_MODE_TRICORE_131", .val = CS_MODE_TRICORE_131 }, + { .str = "CS_MODE_TRICORE_160", .val = CS_MODE_TRICORE_160 }, + { .str = "CS_MODE_TRICORE_161", .val = CS_MODE_TRICORE_161 }, + { .str = "CS_MODE_TRICORE_162", .val = CS_MODE_TRICORE_162 }, + { .str = "CS_MODE_V8", .val = CS_MODE_V8 }, + { .str = "CS_MODE_V9", .val = CS_MODE_V9 }, +}; + +static const TestOptionMapEntry test_option_map[] = { + { .str = "CS_OPT_DETAIL", + .opt = { .type = CS_OPT_DETAIL, .val = CS_OPT_ON } }, + { .str = "CS_OPT_DETAIL_REAL", + .opt = { .type = CS_OPT_DETAIL, + .val = CS_OPT_DETAIL_REAL | CS_OPT_ON } }, + { .str = "CS_OPT_SKIPDATA", + .opt = { .type = CS_OPT_SKIPDATA, .val = CS_OPT_ON } }, + { .str = "CS_OPT_UNSIGNED", + .opt = { .type = CS_OPT_UNSIGNED, .val = CS_OPT_ON } }, + { .str = "CS_OPT_NO_BRANCH_OFFSET", + .opt = { .type = CS_OPT_NO_BRANCH_OFFSET, .val = CS_OPT_ON } }, + { .str = "CS_OPT_SYNTAX_DEFAULT", + .opt = { .type = CS_OPT_SYNTAX, .val = CS_OPT_SYNTAX_DEFAULT } }, + { .str = "CS_OPT_SYNTAX_INTEL", + .opt = { .type = CS_OPT_SYNTAX, .val = CS_OPT_SYNTAX_INTEL } }, + { .str = "CS_OPT_SYNTAX_ATT", + .opt = { .type = CS_OPT_SYNTAX, .val = CS_OPT_SYNTAX_ATT } }, + { .str = "CS_OPT_SYNTAX_NOREGNAME", + .opt = { .type = CS_OPT_SYNTAX, .val = CS_OPT_SYNTAX_NOREGNAME } }, + { .str = "CS_OPT_SYNTAX_MASM", + .opt = { .type = CS_OPT_SYNTAX, .val = CS_OPT_SYNTAX_MASM } }, + { .str = "CS_OPT_SYNTAX_MOTOROLA", + .opt = { .type = CS_OPT_SYNTAX, .val = CS_OPT_SYNTAX_MOTOROLA } }, + { .str = "CS_OPT_SYNTAX_CS_REG_ALIAS", + .opt = { .type = CS_OPT_SYNTAX, .val = CS_OPT_SYNTAX_CS_REG_ALIAS } }, + { .str = "CS_OPT_SYNTAX_PERCENT", + .opt = { .type = CS_OPT_SYNTAX, .val = CS_OPT_SYNTAX_PERCENT } }, +}; + +static const cs_enum_id_map cs_enum_map[] = { + { .str = "AAAAAAAAAAAAAAAAAAAAAAAAAA", .val = 0xffffff }, // For testing + { .str = "AARCH64LAYOUT_INVALID", .val = AARCH64LAYOUT_INVALID }, + { .str = "AARCH64LAYOUT_VL_16B", .val = AARCH64LAYOUT_VL_16B }, + { .str = "AARCH64LAYOUT_VL_16S", .val = AARCH64LAYOUT_VL_16S }, + { .str = "AARCH64LAYOUT_VL_1D", .val = AARCH64LAYOUT_VL_1D }, + { .str = "AARCH64LAYOUT_VL_1Q", .val = AARCH64LAYOUT_VL_1Q }, + { .str = "AARCH64LAYOUT_VL_1S", .val = AARCH64LAYOUT_VL_1S }, + { .str = "AARCH64LAYOUT_VL_2D", .val = AARCH64LAYOUT_VL_2D }, + { .str = "AARCH64LAYOUT_VL_2H", .val = AARCH64LAYOUT_VL_2H }, + { .str = "AARCH64LAYOUT_VL_2S", .val = AARCH64LAYOUT_VL_2S }, + { .str = "AARCH64LAYOUT_VL_32H", .val = AARCH64LAYOUT_VL_32H }, + { .str = "AARCH64LAYOUT_VL_4B", .val = AARCH64LAYOUT_VL_4B }, + { .str = "AARCH64LAYOUT_VL_4H", .val = AARCH64LAYOUT_VL_4H }, + { .str = "AARCH64LAYOUT_VL_4S", .val = AARCH64LAYOUT_VL_4S }, + { .str = "AARCH64LAYOUT_VL_64B", .val = AARCH64LAYOUT_VL_64B }, + { .str = "AARCH64LAYOUT_VL_8B", .val = AARCH64LAYOUT_VL_8B }, + { .str = "AARCH64LAYOUT_VL_8D", .val = AARCH64LAYOUT_VL_8D }, + { .str = "AARCH64LAYOUT_VL_8H", .val = AARCH64LAYOUT_VL_8H }, + { .str = "AARCH64LAYOUT_VL_B", .val = AARCH64LAYOUT_VL_B }, + { .str = "AARCH64LAYOUT_VL_COMPLETE", + .val = AARCH64LAYOUT_VL_COMPLETE }, + { .str = "AARCH64LAYOUT_VL_D", .val = AARCH64LAYOUT_VL_D }, + { .str = "AARCH64LAYOUT_VL_H", .val = AARCH64LAYOUT_VL_H }, + { .str = "AARCH64LAYOUT_VL_Q", .val = AARCH64LAYOUT_VL_Q }, + { .str = "AARCH64LAYOUT_VL_S", .val = AARCH64LAYOUT_VL_S }, + { .str = "AARCH64_EXT_INVALID", .val = AARCH64_EXT_INVALID }, + { .str = "AARCH64_EXT_SXTB", .val = AARCH64_EXT_SXTB }, + { .str = "AARCH64_EXT_SXTH", .val = AARCH64_EXT_SXTH }, + { .str = "AARCH64_EXT_SXTW", .val = AARCH64_EXT_SXTW }, + { .str = "AARCH64_EXT_SXTX", .val = AARCH64_EXT_SXTX }, + { .str = "AARCH64_EXT_UXTB", .val = AARCH64_EXT_UXTB }, + { .str = "AARCH64_EXT_UXTH", .val = AARCH64_EXT_UXTH }, + { .str = "AARCH64_EXT_UXTW", .val = AARCH64_EXT_UXTW }, + { .str = "AARCH64_EXT_UXTX", .val = AARCH64_EXT_UXTX }, + { .str = "AARCH64_OP_AT", .val = AARCH64_OP_AT }, + { .str = "AARCH64_OP_BTI", .val = AARCH64_OP_BTI }, + { .str = "AARCH64_OP_CIMM", .val = AARCH64_OP_CIMM }, + { .str = "AARCH64_OP_DB", .val = AARCH64_OP_DB }, + { .str = "AARCH64_OP_DBNXS", .val = AARCH64_OP_DBNXS }, + { .str = "AARCH64_OP_DC", .val = AARCH64_OP_DC }, + { .str = "AARCH64_OP_EXACTFPIMM", .val = AARCH64_OP_EXACTFPIMM }, + { .str = "AARCH64_OP_FP", .val = AARCH64_OP_FP }, + { .str = "AARCH64_OP_IC", .val = AARCH64_OP_IC }, + { .str = "AARCH64_OP_IMM", .val = AARCH64_OP_IMM }, + { .str = "AARCH64_OP_IMM_RANGE", .val = AARCH64_OP_IMM_RANGE }, + { .str = "AARCH64_OP_IMPLICIT_IMM_0", + .val = AARCH64_OP_IMPLICIT_IMM_0 }, + { .str = "AARCH64_OP_ISB", .val = AARCH64_OP_ISB }, + { .str = "AARCH64_OP_MEM", .val = AARCH64_OP_MEM }, + { .str = "AARCH64_OP_MEM_IMM", .val = AARCH64_OP_MEM_IMM }, + { .str = "AARCH64_OP_MEM_REG", .val = AARCH64_OP_MEM_REG }, + { .str = "AARCH64_OP_PRED", .val = AARCH64_OP_PRED }, + { .str = "AARCH64_OP_PRFM", .val = AARCH64_OP_PRFM }, + { .str = "AARCH64_OP_PSB", .val = AARCH64_OP_PSB }, + { .str = "AARCH64_OP_PSTATEIMM0_1", .val = AARCH64_OP_PSTATEIMM0_1 }, + { .str = "AARCH64_OP_PSTATEIMM0_15", .val = AARCH64_OP_PSTATEIMM0_15 }, + { .str = "AARCH64_OP_REG", .val = AARCH64_OP_REG }, + { .str = "AARCH64_OP_REG_MRS", .val = AARCH64_OP_REG_MRS }, + { .str = "AARCH64_OP_REG_MSR", .val = AARCH64_OP_REG_MSR }, + { .str = "AARCH64_OP_RPRFM", .val = AARCH64_OP_RPRFM }, + { .str = "AARCH64_OP_SME", .val = AARCH64_OP_SME }, + { .str = "AARCH64_OP_SVCR", .val = AARCH64_OP_SVCR }, + { .str = "AARCH64_OP_SVEPREDPAT", .val = AARCH64_OP_SVEPREDPAT }, + { .str = "AARCH64_OP_SVEPRFM", .val = AARCH64_OP_SVEPRFM }, + { .str = "AARCH64_OP_SVEVECLENSPECIFIER", + .val = AARCH64_OP_SVEVECLENSPECIFIER }, + { .str = "AARCH64_OP_SYSALIAS", .val = AARCH64_OP_SYSALIAS }, + { .str = "AARCH64_OP_SYSIMM", .val = AARCH64_OP_SYSIMM }, + { .str = "AARCH64_OP_SYSREG", .val = AARCH64_OP_SYSREG }, + { .str = "AARCH64_OP_TLBI", .val = AARCH64_OP_TLBI }, + { .str = "AARCH64_OP_TSB", .val = AARCH64_OP_TSB }, + { .str = "AARCH64_SFT_ASR", .val = AARCH64_SFT_ASR }, + { .str = "AARCH64_SFT_INVALID", .val = AARCH64_SFT_INVALID }, + { .str = "AARCH64_SFT_LSL", .val = AARCH64_SFT_LSL }, + { .str = "AARCH64_SFT_LSR", .val = AARCH64_SFT_LSR }, + { .str = "AARCH64_SFT_MSL", .val = AARCH64_SFT_MSL }, + { .str = "AARCH64_SFT_ROR", .val = AARCH64_SFT_ROR }, + { .str = "AARCH64_SME_MATRIX_SLICE_OFF", + .val = AARCH64_SME_MATRIX_SLICE_OFF }, + { .str = "AARCH64_SME_MATRIX_SLICE_OFF_RANGE", + .val = AARCH64_SME_MATRIX_SLICE_OFF_RANGE }, + { .str = "AARCH64_SME_MATRIX_SLICE_REG", + .val = AARCH64_SME_MATRIX_SLICE_REG }, + { .str = "AARCH64_SME_MATRIX_TILE", .val = AARCH64_SME_MATRIX_TILE }, + { .str = "AARCH64_SME_MATRIX_TILE_LIST", + .val = AARCH64_SME_MATRIX_TILE_LIST }, + { .str = "AARCH64_SME_OP_INVALID", .val = AARCH64_SME_OP_INVALID }, + { .str = "AARCH64_SME_OP_TILE", .val = AARCH64_SME_OP_TILE }, + { .str = "AARCH64_SME_OP_TILE_VEC", .val = AARCH64_SME_OP_TILE_VEC }, + { .str = "AArch64CC_AL", .val = AArch64CC_AL }, + { .str = "AArch64CC_EQ", .val = AArch64CC_EQ }, + { .str = "AArch64CC_GE", .val = AArch64CC_GE }, + { .str = "AArch64CC_GT", .val = AArch64CC_GT }, + { .str = "AArch64CC_HI", .val = AArch64CC_HI }, + { .str = "AArch64CC_HS", .val = AArch64CC_HS }, + { .str = "AArch64CC_Invalid", .val = AArch64CC_Invalid }, + { .str = "AArch64CC_LE", .val = AArch64CC_LE }, + { .str = "AArch64CC_LO", .val = AArch64CC_LO }, + { .str = "AArch64CC_LS", .val = AArch64CC_LS }, + { .str = "AArch64CC_LT", .val = AArch64CC_LT }, + { .str = "AArch64CC_MI", .val = AArch64CC_MI }, + { .str = "AArch64CC_NE", .val = AArch64CC_NE }, + { .str = "AArch64CC_NV", .val = AArch64CC_NV }, + { .str = "AArch64CC_PL", .val = AArch64CC_PL }, + { .str = "AArch64CC_VC", .val = AArch64CC_VC }, + { .str = "AArch64CC_VS", .val = AArch64CC_VS }, + { .str = "ALPHA_OP_IMM", .val = ALPHA_OP_IMM }, + { .str = "ALPHA_OP_REG", .val = ALPHA_OP_REG }, + { .str = "ARMCC_AL", .val = ARMCC_AL }, + { .str = "ARMCC_EQ", .val = ARMCC_EQ }, + { .str = "ARMCC_GE", .val = ARMCC_GE }, + { .str = "ARMCC_GT", .val = ARMCC_GT }, + { .str = "ARMCC_HI", .val = ARMCC_HI }, + { .str = "ARMCC_HS", .val = ARMCC_HS }, + { .str = "ARMCC_LE", .val = ARMCC_LE }, + { .str = "ARMCC_LO", .val = ARMCC_LO }, + { .str = "ARMCC_LS", .val = ARMCC_LS }, + { .str = "ARMCC_LT", .val = ARMCC_LT }, + { .str = "ARMCC_MI", .val = ARMCC_MI }, + { .str = "ARMCC_NE", .val = ARMCC_NE }, + { .str = "ARMCC_PL", .val = ARMCC_PL }, + { .str = "ARMCC_UNDEF", .val = ARMCC_UNDEF }, + { .str = "ARMCC_VC", .val = ARMCC_VC }, + { .str = "ARMCC_VS", .val = ARMCC_VS }, + { .str = "ARMVCC_Else", .val = ARMVCC_Else }, + { .str = "ARMVCC_None", .val = ARMVCC_None }, + { .str = "ARMVCC_Then", .val = ARMVCC_Then }, + { .str = "ARM_CPSFLAG_A", .val = ARM_CPSFLAG_A }, + { .str = "ARM_CPSFLAG_F", .val = ARM_CPSFLAG_F }, + { .str = "ARM_CPSFLAG_I", .val = ARM_CPSFLAG_I }, + { .str = "ARM_CPSFLAG_INVALID", .val = ARM_CPSFLAG_INVALID }, + { .str = "ARM_CPSFLAG_NONE", .val = ARM_CPSFLAG_NONE }, + { .str = "ARM_CPSMODE_ID", .val = ARM_CPSMODE_ID }, + { .str = "ARM_CPSMODE_IE", .val = ARM_CPSMODE_IE }, + { .str = "ARM_CPSMODE_INVALID", .val = ARM_CPSMODE_INVALID }, + { .str = "ARM_FIELD_CPSR_C", .val = ARM_FIELD_CPSR_C }, + { .str = "ARM_FIELD_CPSR_F", .val = ARM_FIELD_CPSR_F }, + { .str = "ARM_FIELD_CPSR_S", .val = ARM_FIELD_CPSR_S }, + { .str = "ARM_FIELD_CPSR_X", .val = ARM_FIELD_CPSR_X }, + { .str = "ARM_FIELD_SPSR_C", .val = ARM_FIELD_SPSR_C }, + { .str = "ARM_FIELD_SPSR_F", .val = ARM_FIELD_SPSR_F }, + { .str = "ARM_FIELD_SPSR_S", .val = ARM_FIELD_SPSR_S }, + { .str = "ARM_FIELD_SPSR_X", .val = ARM_FIELD_SPSR_X }, + { .str = "ARM_MB_ISH", .val = ARM_MB_ISH }, + { .str = "ARM_MB_ISHLD", .val = ARM_MB_ISHLD }, + { .str = "ARM_MB_ISHST", .val = ARM_MB_ISHST }, + { .str = "ARM_MB_LD", .val = ARM_MB_LD }, + { .str = "ARM_MB_NSH", .val = ARM_MB_NSH }, + { .str = "ARM_MB_NSHLD", .val = ARM_MB_NSHLD }, + { .str = "ARM_MB_NSHST", .val = ARM_MB_NSHST }, + { .str = "ARM_MB_OSH", .val = ARM_MB_OSH }, + { .str = "ARM_MB_OSHLD", .val = ARM_MB_OSHLD }, + { .str = "ARM_MB_OSHST", .val = ARM_MB_OSHST }, + { .str = "ARM_MB_RESERVED_0", .val = ARM_MB_RESERVED_0 }, + { .str = "ARM_MB_RESERVED_12", .val = ARM_MB_RESERVED_12 }, + { .str = "ARM_MB_RESERVED_4", .val = ARM_MB_RESERVED_4 }, + { .str = "ARM_MB_RESERVED_8", .val = ARM_MB_RESERVED_8 }, + { .str = "ARM_MB_ST", .val = ARM_MB_ST }, + { .str = "ARM_MB_SY", .val = ARM_MB_SY }, + { .str = "ARM_OP_BANKEDREG", .val = ARM_OP_BANKEDREG }, + { .str = "ARM_OP_CIMM", .val = ARM_OP_CIMM }, + { .str = "ARM_OP_CPSR", .val = ARM_OP_CPSR }, + { .str = "ARM_OP_FP", .val = ARM_OP_FP }, + { .str = "ARM_OP_IMM", .val = ARM_OP_IMM }, + { .str = "ARM_OP_MEM", .val = ARM_OP_MEM }, + { .str = "ARM_OP_PIMM", .val = ARM_OP_PIMM }, + { .str = "ARM_OP_PRED", .val = ARM_OP_PRED }, + { .str = "ARM_OP_REG", .val = ARM_OP_REG }, + { .str = "ARM_OP_SETEND", .val = ARM_OP_SETEND }, + { .str = "ARM_OP_SPSR", .val = ARM_OP_SPSR }, + { .str = "ARM_OP_SYSM", .val = ARM_OP_SYSM }, + { .str = "ARM_OP_SYSREG", .val = ARM_OP_SYSREG }, + { .str = "ARM_OP_VPRED_N", .val = ARM_OP_VPRED_N }, + { .str = "ARM_OP_VPRED_R", .val = ARM_OP_VPRED_R }, + { .str = "ARM_SETEND_BE", .val = ARM_SETEND_BE }, + { .str = "ARM_SETEND_INVALID", .val = ARM_SETEND_INVALID }, + { .str = "ARM_SETEND_LE", .val = ARM_SETEND_LE }, + { .str = "ARM_SFT_ASR", .val = ARM_SFT_ASR }, + { .str = "ARM_SFT_ASR_REG", .val = ARM_SFT_ASR_REG }, + { .str = "ARM_SFT_INVALID", .val = ARM_SFT_INVALID }, + { .str = "ARM_SFT_LSL", .val = ARM_SFT_LSL }, + { .str = "ARM_SFT_LSL_REG", .val = ARM_SFT_LSL_REG }, + { .str = "ARM_SFT_LSR", .val = ARM_SFT_LSR }, + { .str = "ARM_SFT_LSR_REG", .val = ARM_SFT_LSR_REG }, + { .str = "ARM_SFT_ROR", .val = ARM_SFT_ROR }, + { .str = "ARM_SFT_ROR_REG", .val = ARM_SFT_ROR_REG }, + { .str = "ARM_SFT_RRX", .val = ARM_SFT_RRX }, + { .str = "ARM_SFT_RRX_REG", .val = ARM_SFT_RRX_REG }, + { .str = "ARM_T", .val = ARM_T }, + { .str = "ARM_TE", .val = ARM_TE }, + { .str = "ARM_TEE", .val = ARM_TEE }, + { .str = "ARM_TEEE", .val = ARM_TEEE }, + { .str = "ARM_TEET", .val = ARM_TEET }, + { .str = "ARM_TET", .val = ARM_TET }, + { .str = "ARM_TETE", .val = ARM_TETE }, + { .str = "ARM_TETT", .val = ARM_TETT }, + { .str = "ARM_TT", .val = ARM_TT }, + { .str = "ARM_TTE", .val = ARM_TTE }, + { .str = "ARM_TTEE", .val = ARM_TTEE }, + { .str = "ARM_TTET", .val = ARM_TTET }, + { .str = "ARM_TTT", .val = ARM_TTT }, + { .str = "ARM_TTTE", .val = ARM_TTTE }, + { .str = "ARM_TTTT", .val = ARM_TTTT }, + { .str = "ARM_VECTORDATA_F16", .val = ARM_VECTORDATA_F16 }, + { .str = "ARM_VECTORDATA_F16F32", .val = ARM_VECTORDATA_F16F32 }, + { .str = "ARM_VECTORDATA_F16F64", .val = ARM_VECTORDATA_F16F64 }, + { .str = "ARM_VECTORDATA_F16S16", .val = ARM_VECTORDATA_F16S16 }, + { .str = "ARM_VECTORDATA_F16S32", .val = ARM_VECTORDATA_F16S32 }, + { .str = "ARM_VECTORDATA_F16U16", .val = ARM_VECTORDATA_F16U16 }, + { .str = "ARM_VECTORDATA_F16U32", .val = ARM_VECTORDATA_F16U32 }, + { .str = "ARM_VECTORDATA_F32", .val = ARM_VECTORDATA_F32 }, + { .str = "ARM_VECTORDATA_F32F16", .val = ARM_VECTORDATA_F32F16 }, + { .str = "ARM_VECTORDATA_F32F64", .val = ARM_VECTORDATA_F32F64 }, + { .str = "ARM_VECTORDATA_F32S16", .val = ARM_VECTORDATA_F32S16 }, + { .str = "ARM_VECTORDATA_F32S32", .val = ARM_VECTORDATA_F32S32 }, + { .str = "ARM_VECTORDATA_F32U16", .val = ARM_VECTORDATA_F32U16 }, + { .str = "ARM_VECTORDATA_F32U32", .val = ARM_VECTORDATA_F32U32 }, + { .str = "ARM_VECTORDATA_F64", .val = ARM_VECTORDATA_F64 }, + { .str = "ARM_VECTORDATA_F64F16", .val = ARM_VECTORDATA_F64F16 }, + { .str = "ARM_VECTORDATA_F64F32", .val = ARM_VECTORDATA_F64F32 }, + { .str = "ARM_VECTORDATA_F64S16", .val = ARM_VECTORDATA_F64S16 }, + { .str = "ARM_VECTORDATA_F64S32", .val = ARM_VECTORDATA_F64S32 }, + { .str = "ARM_VECTORDATA_F64U16", .val = ARM_VECTORDATA_F64U16 }, + { .str = "ARM_VECTORDATA_F64U32", .val = ARM_VECTORDATA_F64U32 }, + { .str = "ARM_VECTORDATA_I16", .val = ARM_VECTORDATA_I16 }, + { .str = "ARM_VECTORDATA_I32", .val = ARM_VECTORDATA_I32 }, + { .str = "ARM_VECTORDATA_I64", .val = ARM_VECTORDATA_I64 }, + { .str = "ARM_VECTORDATA_I8", .val = ARM_VECTORDATA_I8 }, + { .str = "ARM_VECTORDATA_INVALID", .val = ARM_VECTORDATA_INVALID }, + { .str = "ARM_VECTORDATA_P16", .val = ARM_VECTORDATA_P16 }, + { .str = "ARM_VECTORDATA_P8", .val = ARM_VECTORDATA_P8 }, + { .str = "ARM_VECTORDATA_S16", .val = ARM_VECTORDATA_S16 }, + { .str = "ARM_VECTORDATA_S16F16", .val = ARM_VECTORDATA_S16F16 }, + { .str = "ARM_VECTORDATA_S16F32", .val = ARM_VECTORDATA_S16F32 }, + { .str = "ARM_VECTORDATA_S16F64", .val = ARM_VECTORDATA_S16F64 }, + { .str = "ARM_VECTORDATA_S32", .val = ARM_VECTORDATA_S32 }, + { .str = "ARM_VECTORDATA_S32F16", .val = ARM_VECTORDATA_S32F16 }, + { .str = "ARM_VECTORDATA_S32F32", .val = ARM_VECTORDATA_S32F32 }, + { .str = "ARM_VECTORDATA_S32F64", .val = ARM_VECTORDATA_S32F64 }, + { .str = "ARM_VECTORDATA_S64", .val = ARM_VECTORDATA_S64 }, + { .str = "ARM_VECTORDATA_S8", .val = ARM_VECTORDATA_S8 }, + { .str = "ARM_VECTORDATA_U16", .val = ARM_VECTORDATA_U16 }, + { .str = "ARM_VECTORDATA_U16F16", .val = ARM_VECTORDATA_U16F16 }, + { .str = "ARM_VECTORDATA_U16F32", .val = ARM_VECTORDATA_U16F32 }, + { .str = "ARM_VECTORDATA_U16F64", .val = ARM_VECTORDATA_U16F64 }, + { .str = "ARM_VECTORDATA_U32", .val = ARM_VECTORDATA_U32 }, + { .str = "ARM_VECTORDATA_U32F16", .val = ARM_VECTORDATA_U32F16 }, + { .str = "ARM_VECTORDATA_U32F32", .val = ARM_VECTORDATA_U32F32 }, + { .str = "ARM_VECTORDATA_U32F64", .val = ARM_VECTORDATA_U32F64 }, + { .str = "ARM_VECTORDATA_U64", .val = ARM_VECTORDATA_U64 }, + { .str = "ARM_VECTORDATA_U8", .val = ARM_VECTORDATA_U8 }, + { .str = "Alpha_GRP_BRANCH_RELATIVE", + .val = Alpha_GRP_BRANCH_RELATIVE }, + { .str = "Alpha_GRP_CALL", .val = Alpha_GRP_CALL }, + { .str = "Alpha_GRP_ENDING", .val = Alpha_GRP_ENDING }, + { .str = "Alpha_GRP_JUMP", .val = Alpha_GRP_JUMP }, + { .str = "BPF_EXT_LEN", .val = BPF_EXT_LEN }, + { .str = "BPF_GRP_ALU", .val = BPF_GRP_ALU }, + { .str = "BPF_GRP_CALL", .val = BPF_GRP_CALL }, + { .str = "BPF_GRP_JUMP", .val = BPF_GRP_JUMP }, + { .str = "BPF_GRP_LOAD", .val = BPF_GRP_LOAD }, + { .str = "BPF_GRP_MISC", .val = BPF_GRP_MISC }, + { .str = "BPF_GRP_RETURN", .val = BPF_GRP_RETURN }, + { .str = "BPF_GRP_STORE", .val = BPF_GRP_STORE }, + { .str = "BPF_OP_EXT", .val = BPF_OP_EXT }, + { .str = "BPF_OP_IMM", .val = BPF_OP_IMM }, + { .str = "BPF_OP_MEM", .val = BPF_OP_MEM }, + { .str = "BPF_OP_MMEM", .val = BPF_OP_MMEM }, + { .str = "BPF_OP_MSH", .val = BPF_OP_MSH }, + { .str = "BPF_OP_OFF", .val = BPF_OP_OFF }, + { .str = "BPF_OP_REG", .val = BPF_OP_REG }, + { .str = "CS_AC_READ", .val = CS_AC_READ }, + { .str = "CS_AC_READ_WRITE", .val = CS_AC_READ_WRITE }, + { .str = "CS_AC_WRITE", .val = CS_AC_WRITE }, + { .str = "EVM_GRP_HALT", .val = EVM_GRP_HALT }, + { .str = "EVM_GRP_JUMP", .val = EVM_GRP_JUMP }, + { .str = "EVM_GRP_MATH", .val = EVM_GRP_MATH }, + { .str = "EVM_GRP_MEM_READ", .val = EVM_GRP_MEM_READ }, + { .str = "EVM_GRP_MEM_WRITE", .val = EVM_GRP_MEM_WRITE }, + { .str = "EVM_GRP_STACK_READ", .val = EVM_GRP_STACK_READ }, + { .str = "EVM_GRP_STACK_WRITE", .val = EVM_GRP_STACK_WRITE }, + { .str = "EVM_GRP_STORE_READ", .val = EVM_GRP_STORE_READ }, + { .str = "EVM_GRP_STORE_WRITE", .val = EVM_GRP_STORE_WRITE }, + { .str = "HPPA_GRP_ASSIST", .val = HPPA_GRP_ASSIST }, + { .str = "HPPA_GRP_BRANCH", .val = HPPA_GRP_BRANCH }, + { .str = "HPPA_GRP_COMPUTATION", .val = HPPA_GRP_COMPUTATION }, + { .str = "HPPA_GRP_FLOAT", .val = HPPA_GRP_FLOAT }, + { .str = "HPPA_GRP_LONG_IMM", .val = HPPA_GRP_LONG_IMM }, + { .str = "HPPA_GRP_MEM_REF", .val = HPPA_GRP_MEM_REF }, + { .str = "HPPA_GRP_MULTIMEDIA", .val = HPPA_GRP_MULTIMEDIA }, + { .str = "HPPA_GRP_PERFMON", .val = HPPA_GRP_PERFMON }, + { .str = "HPPA_GRP_SYSCTRL", .val = HPPA_GRP_SYSCTRL }, + { .str = "HPPA_OP_DISP", .val = HPPA_OP_DISP }, + { .str = "HPPA_OP_IDX_REG", .val = HPPA_OP_IDX_REG }, + { .str = "HPPA_OP_IMM", .val = HPPA_OP_IMM }, + { .str = "HPPA_OP_MEM", .val = HPPA_OP_MEM }, + { .str = "HPPA_OP_REG", .val = HPPA_OP_REG }, + { .str = "HPPA_OP_TARGET", .val = HPPA_OP_TARGET }, + { .str = "LOONGARCH_FEATURE_HASLAGLOBALWITHABS", + .val = LOONGARCH_FEATURE_HASLAGLOBALWITHABS }, + { .str = "LOONGARCH_FEATURE_HASLAGLOBALWITHPCREL", + .val = LOONGARCH_FEATURE_HASLAGLOBALWITHPCREL }, + { .str = "LOONGARCH_FEATURE_HASLALOCALWITHABS", + .val = LOONGARCH_FEATURE_HASLALOCALWITHABS }, + { .str = "LOONGARCH_FEATURE_ISLA32", .val = LOONGARCH_FEATURE_ISLA32 }, + { .str = "LOONGARCH_FEATURE_ISLA64", .val = LOONGARCH_FEATURE_ISLA64 }, + { .str = "LOONGARCH_GRP_BRANCH_RELATIVE", + .val = LOONGARCH_GRP_BRANCH_RELATIVE }, + { .str = "LOONGARCH_GRP_CALL", .val = LOONGARCH_GRP_CALL }, + { .str = "LOONGARCH_GRP_INT", .val = LOONGARCH_GRP_INT }, + { .str = "LOONGARCH_GRP_IRET", .val = LOONGARCH_GRP_IRET }, + { .str = "LOONGARCH_GRP_JUMP", .val = LOONGARCH_GRP_JUMP }, + { .str = "LOONGARCH_GRP_PRIVILEGE", .val = LOONGARCH_GRP_PRIVILEGE }, + { .str = "LOONGARCH_GRP_RET", .val = LOONGARCH_GRP_RET }, + { .str = "LOONGARCH_INSN_FORM_FMT1RI13_VI", + .val = LOONGARCH_INSN_FORM_FMT1RI13_VI }, + { .str = "LOONGARCH_INSN_FORM_FMT1RI13_XI", + .val = LOONGARCH_INSN_FORM_FMT1RI13_XI }, + { .str = "LOONGARCH_INSN_FORM_FMT1RI20", + .val = LOONGARCH_INSN_FORM_FMT1RI20 }, + { .str = "LOONGARCH_INSN_FORM_FMT1RI21", + .val = LOONGARCH_INSN_FORM_FMT1RI21 }, + { .str = "LOONGARCH_INSN_FORM_FMT1RI4", + .val = LOONGARCH_INSN_FORM_FMT1RI4 }, + { .str = "LOONGARCH_INSN_FORM_FMT1RI5I8", + .val = LOONGARCH_INSN_FORM_FMT1RI5I8 }, + { .str = "LOONGARCH_INSN_FORM_FMT1RI8", + .val = LOONGARCH_INSN_FORM_FMT1RI8 }, + { .str = "LOONGARCH_INSN_FORM_FMT2R", + .val = LOONGARCH_INSN_FORM_FMT2R }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI10_VRI", + .val = LOONGARCH_INSN_FORM_FMT2RI10_VRI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI10_XRI", + .val = LOONGARCH_INSN_FORM_FMT2RI10_XRI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI11_VRI", + .val = LOONGARCH_INSN_FORM_FMT2RI11_VRI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI11_XRI", + .val = LOONGARCH_INSN_FORM_FMT2RI11_XRI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI12", + .val = LOONGARCH_INSN_FORM_FMT2RI12 }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI12_VRI", + .val = LOONGARCH_INSN_FORM_FMT2RI12_VRI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI12_XRI", + .val = LOONGARCH_INSN_FORM_FMT2RI12_XRI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI14", + .val = LOONGARCH_INSN_FORM_FMT2RI14 }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI16", + .val = LOONGARCH_INSN_FORM_FMT2RI16 }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI1_RVI", + .val = LOONGARCH_INSN_FORM_FMT2RI1_RVI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI1_VRI", + .val = LOONGARCH_INSN_FORM_FMT2RI1_VRI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI1_VVI", + .val = LOONGARCH_INSN_FORM_FMT2RI1_VVI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI1_XXI", + .val = LOONGARCH_INSN_FORM_FMT2RI1_XXI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI2_RVI", + .val = LOONGARCH_INSN_FORM_FMT2RI2_RVI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI2_RXI", + .val = LOONGARCH_INSN_FORM_FMT2RI2_RXI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI2_VRI", + .val = LOONGARCH_INSN_FORM_FMT2RI2_VRI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI2_VVI", + .val = LOONGARCH_INSN_FORM_FMT2RI2_VVI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI2_XRI", + .val = LOONGARCH_INSN_FORM_FMT2RI2_XRI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI2_XXI", + .val = LOONGARCH_INSN_FORM_FMT2RI2_XXI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI3", + .val = LOONGARCH_INSN_FORM_FMT2RI3 }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI3_RVI", + .val = LOONGARCH_INSN_FORM_FMT2RI3_RVI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI3_RXI", + .val = LOONGARCH_INSN_FORM_FMT2RI3_RXI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI3_VRI", + .val = LOONGARCH_INSN_FORM_FMT2RI3_VRI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI3_VVI", + .val = LOONGARCH_INSN_FORM_FMT2RI3_VVI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI3_XRI", + .val = LOONGARCH_INSN_FORM_FMT2RI3_XRI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI3_XXI", + .val = LOONGARCH_INSN_FORM_FMT2RI3_XXI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI4", + .val = LOONGARCH_INSN_FORM_FMT2RI4 }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI4_RVI", + .val = LOONGARCH_INSN_FORM_FMT2RI4_RVI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI4_VRI", + .val = LOONGARCH_INSN_FORM_FMT2RI4_VRI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI4_VVI", + .val = LOONGARCH_INSN_FORM_FMT2RI4_VVI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI4_XXI", + .val = LOONGARCH_INSN_FORM_FMT2RI4_XXI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI5", + .val = LOONGARCH_INSN_FORM_FMT2RI5 }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI5_VVI", + .val = LOONGARCH_INSN_FORM_FMT2RI5_VVI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI5_XXI", + .val = LOONGARCH_INSN_FORM_FMT2RI5_XXI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI6", + .val = LOONGARCH_INSN_FORM_FMT2RI6 }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI6_VVI", + .val = LOONGARCH_INSN_FORM_FMT2RI6_VVI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI6_XXI", + .val = LOONGARCH_INSN_FORM_FMT2RI6_XXI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI7_VVI", + .val = LOONGARCH_INSN_FORM_FMT2RI7_VVI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI7_XXI", + .val = LOONGARCH_INSN_FORM_FMT2RI7_XXI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI8", + .val = LOONGARCH_INSN_FORM_FMT2RI8 }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI8I1_VRII", + .val = LOONGARCH_INSN_FORM_FMT2RI8I1_VRII }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI8I2_VRII", + .val = LOONGARCH_INSN_FORM_FMT2RI8I2_VRII }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI8I2_XRII", + .val = LOONGARCH_INSN_FORM_FMT2RI8I2_XRII }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI8I3_VRII", + .val = LOONGARCH_INSN_FORM_FMT2RI8I3_VRII }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI8I3_XRII", + .val = LOONGARCH_INSN_FORM_FMT2RI8I3_XRII }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI8I4_VRII", + .val = LOONGARCH_INSN_FORM_FMT2RI8I4_VRII }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI8I4_XRII", + .val = LOONGARCH_INSN_FORM_FMT2RI8I4_XRII }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI8I5_XRII", + .val = LOONGARCH_INSN_FORM_FMT2RI8I5_XRII }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI8_VVI", + .val = LOONGARCH_INSN_FORM_FMT2RI8_VVI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI8_XXI", + .val = LOONGARCH_INSN_FORM_FMT2RI8_XXI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI9_VRI", + .val = LOONGARCH_INSN_FORM_FMT2RI9_VRI }, + { .str = "LOONGARCH_INSN_FORM_FMT2RI9_XRI", + .val = LOONGARCH_INSN_FORM_FMT2RI9_XRI }, + { .str = "LOONGARCH_INSN_FORM_FMT2R_CV", + .val = LOONGARCH_INSN_FORM_FMT2R_CV }, + { .str = "LOONGARCH_INSN_FORM_FMT2R_CX", + .val = LOONGARCH_INSN_FORM_FMT2R_CX }, + { .str = "LOONGARCH_INSN_FORM_FMT2R_VR", + .val = LOONGARCH_INSN_FORM_FMT2R_VR }, + { .str = "LOONGARCH_INSN_FORM_FMT2R_VV", + .val = LOONGARCH_INSN_FORM_FMT2R_VV }, + { .str = "LOONGARCH_INSN_FORM_FMT2R_XR", + .val = LOONGARCH_INSN_FORM_FMT2R_XR }, + { .str = "LOONGARCH_INSN_FORM_FMT2R_XX", + .val = LOONGARCH_INSN_FORM_FMT2R_XX }, + { .str = "LOONGARCH_INSN_FORM_FMT3R", + .val = LOONGARCH_INSN_FORM_FMT3R }, + { .str = "LOONGARCH_INSN_FORM_FMT3RI2", + .val = LOONGARCH_INSN_FORM_FMT3RI2 }, + { .str = "LOONGARCH_INSN_FORM_FMT3RI3", + .val = LOONGARCH_INSN_FORM_FMT3RI3 }, + { .str = "LOONGARCH_INSN_FORM_FMT3R_VRR", + .val = LOONGARCH_INSN_FORM_FMT3R_VRR }, + { .str = "LOONGARCH_INSN_FORM_FMT3R_VVR", + .val = LOONGARCH_INSN_FORM_FMT3R_VVR }, + { .str = "LOONGARCH_INSN_FORM_FMT3R_VVV", + .val = LOONGARCH_INSN_FORM_FMT3R_VVV }, + { .str = "LOONGARCH_INSN_FORM_FMT3R_XRR", + .val = LOONGARCH_INSN_FORM_FMT3R_XRR }, + { .str = "LOONGARCH_INSN_FORM_FMT3R_XXR", + .val = LOONGARCH_INSN_FORM_FMT3R_XXR }, + { .str = "LOONGARCH_INSN_FORM_FMT3R_XXX", + .val = LOONGARCH_INSN_FORM_FMT3R_XXX }, + { .str = "LOONGARCH_INSN_FORM_FMT4R_VVVV", + .val = LOONGARCH_INSN_FORM_FMT4R_VVVV }, + { .str = "LOONGARCH_INSN_FORM_FMT4R_XXXX", + .val = LOONGARCH_INSN_FORM_FMT4R_XXXX }, + { .str = "LOONGARCH_INSN_FORM_FMTASRT", + .val = LOONGARCH_INSN_FORM_FMTASRT }, + { .str = "LOONGARCH_INSN_FORM_FMTBSTR_D", + .val = LOONGARCH_INSN_FORM_FMTBSTR_D }, + { .str = "LOONGARCH_INSN_FORM_FMTBSTR_W", + .val = LOONGARCH_INSN_FORM_FMTBSTR_W }, + { .str = "LOONGARCH_INSN_FORM_FMTCACOP", + .val = LOONGARCH_INSN_FORM_FMTCACOP }, + { .str = "LOONGARCH_INSN_FORM_FMTCSR", + .val = LOONGARCH_INSN_FORM_FMTCSR }, + { .str = "LOONGARCH_INSN_FORM_FMTCSRXCHG", + .val = LOONGARCH_INSN_FORM_FMTCSRXCHG }, + { .str = "LOONGARCH_INSN_FORM_FMTGR2SCR", + .val = LOONGARCH_INSN_FORM_FMTGR2SCR }, + { .str = "LOONGARCH_INSN_FORM_FMTI15", + .val = LOONGARCH_INSN_FORM_FMTI15 }, + { .str = "LOONGARCH_INSN_FORM_FMTI26", + .val = LOONGARCH_INSN_FORM_FMTI26 }, + { .str = "LOONGARCH_INSN_FORM_FMTI32", + .val = LOONGARCH_INSN_FORM_FMTI32 }, + { .str = "LOONGARCH_INSN_FORM_FMTINVTLB", + .val = LOONGARCH_INSN_FORM_FMTINVTLB }, + { .str = "LOONGARCH_INSN_FORM_FMTJISCR", + .val = LOONGARCH_INSN_FORM_FMTJISCR }, + { .str = "LOONGARCH_INSN_FORM_FMTLDPTE", + .val = LOONGARCH_INSN_FORM_FMTLDPTE }, + { .str = "LOONGARCH_INSN_FORM_FMTMFTOP", + .val = LOONGARCH_INSN_FORM_FMTMFTOP }, + { .str = "LOONGARCH_INSN_FORM_FMTMTTOP", + .val = LOONGARCH_INSN_FORM_FMTMTTOP }, + { .str = "LOONGARCH_INSN_FORM_FMTPRELD", + .val = LOONGARCH_INSN_FORM_FMTPRELD }, + { .str = "LOONGARCH_INSN_FORM_FMTPRELDX", + .val = LOONGARCH_INSN_FORM_FMTPRELDX }, + { .str = "LOONGARCH_INSN_FORM_FMTSCR2GR", + .val = LOONGARCH_INSN_FORM_FMTSCR2GR }, + { .str = "LOONGARCH_INSN_FORM_FPFMT2R", + .val = LOONGARCH_INSN_FORM_FPFMT2R }, + { .str = "LOONGARCH_INSN_FORM_FPFMT2RI12", + .val = LOONGARCH_INSN_FORM_FPFMT2RI12 }, + { .str = "LOONGARCH_INSN_FORM_FPFMT3R", + .val = LOONGARCH_INSN_FORM_FPFMT3R }, + { .str = "LOONGARCH_INSN_FORM_FPFMT4R", + .val = LOONGARCH_INSN_FORM_FPFMT4R }, + { .str = "LOONGARCH_INSN_FORM_FPFMTBR", + .val = LOONGARCH_INSN_FORM_FPFMTBR }, + { .str = "LOONGARCH_INSN_FORM_FPFMTFCMP", + .val = LOONGARCH_INSN_FORM_FPFMTFCMP }, + { .str = "LOONGARCH_INSN_FORM_FPFMTFSEL", + .val = LOONGARCH_INSN_FORM_FPFMTFSEL }, + { .str = "LOONGARCH_INSN_FORM_FPFMTMEM", + .val = LOONGARCH_INSN_FORM_FPFMTMEM }, + { .str = "LOONGARCH_INSN_FORM_FPFMTMOV", + .val = LOONGARCH_INSN_FORM_FPFMTMOV }, + { .str = "LOONGARCH_INSN_FORM_NODSTFMT1R", + .val = LOONGARCH_INSN_FORM_NODSTFMT1R }, + { .str = "LOONGARCH_INSN_FORM_NODSTFMT1RI3", + .val = LOONGARCH_INSN_FORM_NODSTFMT1RI3 }, + { .str = "LOONGARCH_INSN_FORM_NODSTFMT1RI4", + .val = LOONGARCH_INSN_FORM_NODSTFMT1RI4 }, + { .str = "LOONGARCH_INSN_FORM_NODSTFMT1RI5", + .val = LOONGARCH_INSN_FORM_NODSTFMT1RI5 }, + { .str = "LOONGARCH_INSN_FORM_NODSTFMT1RI5I4", + .val = LOONGARCH_INSN_FORM_NODSTFMT1RI5I4 }, + { .str = "LOONGARCH_INSN_FORM_NODSTFMT1RI6", + .val = LOONGARCH_INSN_FORM_NODSTFMT1RI6 }, + { .str = "LOONGARCH_INSN_FORM_NODSTFMT2R", + .val = LOONGARCH_INSN_FORM_NODSTFMT2R }, + { .str = "LOONGARCH_INSN_FORM_NODSTFMT2RI4", + .val = LOONGARCH_INSN_FORM_NODSTFMT2RI4 }, + { .str = "LOONGARCH_INSN_FORM_PSEUDO", + .val = LOONGARCH_INSN_FORM_PSEUDO }, + { .str = "LOONGARCH_OP_IMM", .val = LOONGARCH_OP_IMM }, + { .str = "LOONGARCH_OP_MEM", .val = LOONGARCH_OP_MEM }, + { .str = "LOONGARCH_OP_REG", .val = LOONGARCH_OP_REG }, + { .str = "M680X_FIRST_OP_IN_MNEM", .val = M680X_FIRST_OP_IN_MNEM }, + { .str = "M680X_GRP_BRAREL", .val = M680X_GRP_BRAREL }, + { .str = "M680X_GRP_CALL", .val = M680X_GRP_CALL }, + { .str = "M680X_GRP_INT", .val = M680X_GRP_INT }, + { .str = "M680X_GRP_IRET", .val = M680X_GRP_IRET }, + { .str = "M680X_GRP_JUMP", .val = M680X_GRP_JUMP }, + { .str = "M680X_GRP_PRIV", .val = M680X_GRP_PRIV }, + { .str = "M680X_GRP_RET", .val = M680X_GRP_RET }, + { .str = "M680X_IDX_INDIRECT", .val = M680X_IDX_INDIRECT }, + { .str = "M680X_IDX_NO_COMMA", .val = M680X_IDX_NO_COMMA }, + { .str = "M680X_IDX_POST_INC_DEC", .val = M680X_IDX_POST_INC_DEC }, + { .str = "M680X_OFFSET_BITS_16", .val = M680X_OFFSET_BITS_16 }, + { .str = "M680X_OFFSET_BITS_5", .val = M680X_OFFSET_BITS_5 }, + { .str = "M680X_OFFSET_BITS_8", .val = M680X_OFFSET_BITS_8 }, + { .str = "M680X_OFFSET_BITS_9", .val = M680X_OFFSET_BITS_9 }, + { .str = "M680X_OFFSET_NONE", .val = M680X_OFFSET_NONE }, + { .str = "M680X_OP_CONSTANT", .val = M680X_OP_CONSTANT }, + { .str = "M680X_OP_DIRECT", .val = M680X_OP_DIRECT }, + { .str = "M680X_OP_EXTENDED", .val = M680X_OP_EXTENDED }, + { .str = "M680X_OP_IMMEDIATE", .val = M680X_OP_IMMEDIATE }, + { .str = "M680X_OP_INDEXED", .val = M680X_OP_INDEXED }, + { .str = "M680X_OP_REGISTER", .val = M680X_OP_REGISTER }, + { .str = "M680X_OP_RELATIVE", .val = M680X_OP_RELATIVE }, + { .str = "M680X_SECOND_OP_IN_MNEM", .val = M680X_SECOND_OP_IN_MNEM }, + { .str = "M68K_AM_ABSOLUTE_DATA_LONG", + .val = M68K_AM_ABSOLUTE_DATA_LONG }, + { .str = "M68K_AM_ABSOLUTE_DATA_SHORT", + .val = M68K_AM_ABSOLUTE_DATA_SHORT }, + { .str = "M68K_AM_AREGI_INDEX_8_BIT_DISP", + .val = M68K_AM_AREGI_INDEX_8_BIT_DISP }, + { .str = "M68K_AM_AREGI_INDEX_BASE_DISP", + .val = M68K_AM_AREGI_INDEX_BASE_DISP }, + { .str = "M68K_AM_BRANCH_DISPLACEMENT", + .val = M68K_AM_BRANCH_DISPLACEMENT }, + { .str = "M68K_AM_IMMEDIATE", .val = M68K_AM_IMMEDIATE }, + { .str = "M68K_AM_MEMI_POST_INDEX", .val = M68K_AM_MEMI_POST_INDEX }, + { .str = "M68K_AM_MEMI_PRE_INDEX", .val = M68K_AM_MEMI_PRE_INDEX }, + { .str = "M68K_AM_NONE", .val = M68K_AM_NONE }, + { .str = "M68K_AM_PCI_DISP", .val = M68K_AM_PCI_DISP }, + { .str = "M68K_AM_PCI_INDEX_8_BIT_DISP", + .val = M68K_AM_PCI_INDEX_8_BIT_DISP }, + { .str = "M68K_AM_PCI_INDEX_BASE_DISP", + .val = M68K_AM_PCI_INDEX_BASE_DISP }, + { .str = "M68K_AM_PC_MEMI_POST_INDEX", + .val = M68K_AM_PC_MEMI_POST_INDEX }, + { .str = "M68K_AM_PC_MEMI_PRE_INDEX", + .val = M68K_AM_PC_MEMI_PRE_INDEX }, + { .str = "M68K_AM_REGI_ADDR", .val = M68K_AM_REGI_ADDR }, + { .str = "M68K_AM_REGI_ADDR_DISP", .val = M68K_AM_REGI_ADDR_DISP }, + { .str = "M68K_AM_REGI_ADDR_POST_INC", + .val = M68K_AM_REGI_ADDR_POST_INC }, + { .str = "M68K_AM_REGI_ADDR_PRE_DEC", + .val = M68K_AM_REGI_ADDR_PRE_DEC }, + { .str = "M68K_AM_REG_DIRECT_ADDR", .val = M68K_AM_REG_DIRECT_ADDR }, + { .str = "M68K_AM_REG_DIRECT_DATA", .val = M68K_AM_REG_DIRECT_DATA }, + { .str = "M68K_CPU_SIZE_BYTE", .val = M68K_CPU_SIZE_BYTE }, + { .str = "M68K_CPU_SIZE_LONG", .val = M68K_CPU_SIZE_LONG }, + { .str = "M68K_CPU_SIZE_NONE", .val = M68K_CPU_SIZE_NONE }, + { .str = "M68K_CPU_SIZE_WORD", .val = M68K_CPU_SIZE_WORD }, + { .str = "M68K_FPU_SIZE_DOUBLE", .val = M68K_FPU_SIZE_DOUBLE }, + { .str = "M68K_FPU_SIZE_EXTENDED", .val = M68K_FPU_SIZE_EXTENDED }, + { .str = "M68K_FPU_SIZE_NONE", .val = M68K_FPU_SIZE_NONE }, + { .str = "M68K_FPU_SIZE_SINGLE", .val = M68K_FPU_SIZE_SINGLE }, + { .str = "M68K_GRP_BRANCH_RELATIVE", .val = M68K_GRP_BRANCH_RELATIVE }, + { .str = "M68K_GRP_IRET", .val = M68K_GRP_IRET }, + { .str = "M68K_GRP_JUMP", .val = M68K_GRP_JUMP }, + { .str = "M68K_GRP_RET", .val = M68K_GRP_RET }, + { .str = "M68K_OP_BR_DISP", .val = M68K_OP_BR_DISP }, + { .str = "M68K_OP_BR_DISP_SIZE_BYTE", + .val = M68K_OP_BR_DISP_SIZE_BYTE }, + { .str = "M68K_OP_BR_DISP_SIZE_LONG", + .val = M68K_OP_BR_DISP_SIZE_LONG }, + { .str = "M68K_OP_BR_DISP_SIZE_WORD", + .val = M68K_OP_BR_DISP_SIZE_WORD }, + { .str = "M68K_OP_FP_DOUBLE", .val = M68K_OP_FP_DOUBLE }, + { .str = "M68K_OP_FP_SINGLE", .val = M68K_OP_FP_SINGLE }, + { .str = "M68K_OP_IMM", .val = M68K_OP_IMM }, + { .str = "M68K_OP_MEM", .val = M68K_OP_MEM }, + { .str = "M68K_OP_REG", .val = M68K_OP_REG }, + { .str = "M68K_OP_REG_BITS", .val = M68K_OP_REG_BITS }, + { .str = "M68K_OP_REG_PAIR", .val = M68K_OP_REG_PAIR }, + { .str = "M68K_SIZE_TYPE_CPU", .val = M68K_SIZE_TYPE_CPU }, + { .str = "M68K_SIZE_TYPE_FPU", .val = M68K_SIZE_TYPE_FPU }, + { .str = "MIPS_OP_IMM", .val = MIPS_OP_IMM }, + { .str = "MIPS_OP_MEM", .val = MIPS_OP_MEM }, + { .str = "MIPS_OP_REG", .val = MIPS_OP_REG }, + { .str = "MOS65XX_AM_ABS", .val = MOS65XX_AM_ABS }, + { .str = "MOS65XX_AM_ABS_IND", .val = MOS65XX_AM_ABS_IND }, + { .str = "MOS65XX_AM_ABS_IND_LONG", .val = MOS65XX_AM_ABS_IND_LONG }, + { .str = "MOS65XX_AM_ABS_LONG", .val = MOS65XX_AM_ABS_LONG }, + { .str = "MOS65XX_AM_ABS_LONG_X", .val = MOS65XX_AM_ABS_LONG_X }, + { .str = "MOS65XX_AM_ABS_X", .val = MOS65XX_AM_ABS_X }, + { .str = "MOS65XX_AM_ABS_X_IND", .val = MOS65XX_AM_ABS_X_IND }, + { .str = "MOS65XX_AM_ABS_Y", .val = MOS65XX_AM_ABS_Y }, + { .str = "MOS65XX_AM_ACC", .val = MOS65XX_AM_ACC }, + { .str = "MOS65XX_AM_BLOCK", .val = MOS65XX_AM_BLOCK }, + { .str = "MOS65XX_AM_IMM", .val = MOS65XX_AM_IMM }, + { .str = "MOS65XX_AM_IMP", .val = MOS65XX_AM_IMP }, + { .str = "MOS65XX_AM_INT", .val = MOS65XX_AM_INT }, + { .str = "MOS65XX_AM_REL", .val = MOS65XX_AM_REL }, + { .str = "MOS65XX_AM_SR", .val = MOS65XX_AM_SR }, + { .str = "MOS65XX_AM_SR_IND_Y", .val = MOS65XX_AM_SR_IND_Y }, + { .str = "MOS65XX_AM_ZP", .val = MOS65XX_AM_ZP }, + { .str = "MOS65XX_AM_ZP_IND", .val = MOS65XX_AM_ZP_IND }, + { .str = "MOS65XX_AM_ZP_IND_LONG", .val = MOS65XX_AM_ZP_IND_LONG }, + { .str = "MOS65XX_AM_ZP_IND_LONG_Y", .val = MOS65XX_AM_ZP_IND_LONG_Y }, + { .str = "MOS65XX_AM_ZP_IND_Y", .val = MOS65XX_AM_ZP_IND_Y }, + { .str = "MOS65XX_AM_ZP_REL", .val = MOS65XX_AM_ZP_REL }, + { .str = "MOS65XX_AM_ZP_X", .val = MOS65XX_AM_ZP_X }, + { .str = "MOS65XX_AM_ZP_X_IND", .val = MOS65XX_AM_ZP_X_IND }, + { .str = "MOS65XX_AM_ZP_Y", .val = MOS65XX_AM_ZP_Y }, + { .str = "MOS65XX_GRP_BRANCH_RELATIVE", + .val = MOS65XX_GRP_BRANCH_RELATIVE }, + { .str = "MOS65XX_GRP_CALL", .val = MOS65XX_GRP_CALL }, + { .str = "MOS65XX_GRP_INT", .val = MOS65XX_GRP_INT }, + { .str = "MOS65XX_GRP_IRET", .val = MOS65XX_GRP_IRET }, + { .str = "MOS65XX_GRP_JUMP", .val = MOS65XX_GRP_JUMP }, + { .str = "MOS65XX_GRP_RET", .val = MOS65XX_GRP_RET }, + { .str = "MOS65XX_OP_IMM", .val = MOS65XX_OP_IMM }, + { .str = "MOS65XX_OP_MEM", .val = MOS65XX_OP_MEM }, + { .str = "MOS65XX_OP_REG", .val = MOS65XX_OP_REG }, + { .str = "PPC_BH_INVALID", .val = PPC_BH_INVALID }, + { .str = "PPC_BH_NOT_PREDICTABLE", .val = PPC_BH_NOT_PREDICTABLE }, + { .str = "PPC_BH_NO_SUBROUTINE_RET", .val = PPC_BH_NO_SUBROUTINE_RET }, + { .str = "PPC_BH_RESERVED", .val = PPC_BH_RESERVED }, + { .str = "PPC_BH_SUBROUTINE_RET", .val = PPC_BH_SUBROUTINE_RET }, + { .str = "PPC_BI_GT", .val = PPC_BI_GT }, + { .str = "PPC_BI_LT", .val = PPC_BI_LT }, + { .str = "PPC_BI_SO", .val = PPC_BI_SO }, + { .str = "PPC_BI_Z", .val = PPC_BI_Z }, + { .str = "PPC_BO_CR_CMP", .val = PPC_BO_CR_CMP }, + { .str = "PPC_BO_CTR_CMP", .val = PPC_BO_CTR_CMP }, + { .str = "PPC_BO_DECR_CTR", .val = PPC_BO_DECR_CTR }, + { .str = "PPC_BO_T", .val = PPC_BO_T }, + { .str = "PPC_BO_TEST_CR", .val = PPC_BO_TEST_CR }, + { .str = "PPC_BR_HINT_MASK", .val = PPC_BR_HINT_MASK }, + { .str = "PPC_BR_NOT_GIVEN", .val = PPC_BR_NOT_GIVEN }, + { .str = "PPC_BR_NOT_TAKEN", .val = PPC_BR_NOT_TAKEN }, + { .str = "PPC_BR_RESERVED", .val = PPC_BR_RESERVED }, + { .str = "PPC_BR_TAKEN", .val = PPC_BR_TAKEN }, + { .str = "PPC_INSN_FORM_AFORM_1", .val = PPC_INSN_FORM_AFORM_1 }, + { .str = "PPC_INSN_FORM_AFORM_4", .val = PPC_INSN_FORM_AFORM_4 }, + { .str = "PPC_INSN_FORM_BFORM", .val = PPC_INSN_FORM_BFORM }, + { .str = "PPC_INSN_FORM_BFORM_3", .val = PPC_INSN_FORM_BFORM_3 }, + { .str = "PPC_INSN_FORM_BFORM_3_AT", .val = PPC_INSN_FORM_BFORM_3_AT }, + { .str = "PPC_INSN_FORM_DCBZL_FORM", .val = PPC_INSN_FORM_DCBZL_FORM }, + { .str = "PPC_INSN_FORM_DCB_FORM", .val = PPC_INSN_FORM_DCB_FORM }, + { .str = "PPC_INSN_FORM_DCB_FORM_HINT", + .val = PPC_INSN_FORM_DCB_FORM_HINT }, + { .str = "PPC_INSN_FORM_DFORM_1", .val = PPC_INSN_FORM_DFORM_1 }, + { .str = "PPC_INSN_FORM_DFORM_2_R0", .val = PPC_INSN_FORM_DFORM_2_R0 }, + { .str = "PPC_INSN_FORM_DFORM_4", .val = PPC_INSN_FORM_DFORM_4 }, + { .str = "PPC_INSN_FORM_DFORM_5", .val = PPC_INSN_FORM_DFORM_5 }, + { .str = "PPC_INSN_FORM_DFORM_BASE", .val = PPC_INSN_FORM_DFORM_BASE }, + { .str = "PPC_INSN_FORM_DQFORM_RTP5_RA17_MEM", + .val = PPC_INSN_FORM_DQFORM_RTP5_RA17_MEM }, + { .str = "PPC_INSN_FORM_DQFORM_XTP5_RA17_MEM", + .val = PPC_INSN_FORM_DQFORM_XTP5_RA17_MEM }, + { .str = "PPC_INSN_FORM_DQ_RD6_RS5_DQ12", + .val = PPC_INSN_FORM_DQ_RD6_RS5_DQ12 }, + { .str = "PPC_INSN_FORM_DSFORM_1", .val = PPC_INSN_FORM_DSFORM_1 }, + { .str = "PPC_INSN_FORM_DSS_FORM", .val = PPC_INSN_FORM_DSS_FORM }, + { .str = "PPC_INSN_FORM_DXFORM", .val = PPC_INSN_FORM_DXFORM }, + { .str = "PPC_INSN_FORM_EFXFORM_1", .val = PPC_INSN_FORM_EFXFORM_1 }, + { .str = "PPC_INSN_FORM_EFXFORM_3", .val = PPC_INSN_FORM_EFXFORM_3 }, + { .str = "PPC_INSN_FORM_EVXFORM_1", .val = PPC_INSN_FORM_EVXFORM_1 }, + { .str = "PPC_INSN_FORM_EVXFORM_3", .val = PPC_INSN_FORM_EVXFORM_3 }, + { .str = "PPC_INSN_FORM_EVXFORM_4", .val = PPC_INSN_FORM_EVXFORM_4 }, + { .str = "PPC_INSN_FORM_EVXFORM_D", .val = PPC_INSN_FORM_EVXFORM_D }, + { .str = "PPC_INSN_FORM_IFORM", .val = PPC_INSN_FORM_IFORM }, + { .str = "PPC_INSN_FORM_MDFORM_1", .val = PPC_INSN_FORM_MDFORM_1 }, + { .str = "PPC_INSN_FORM_MDSFORM_1", .val = PPC_INSN_FORM_MDSFORM_1 }, + { .str = "PPC_INSN_FORM_MFORM_1", .val = PPC_INSN_FORM_MFORM_1 }, + { .str = "PPC_INSN_FORM_PSFORM_C", .val = PPC_INSN_FORM_PSFORM_C }, + { .str = "PPC_INSN_FORM_PSFORM_QD", .val = PPC_INSN_FORM_PSFORM_QD }, + { .str = "PPC_INSN_FORM_PSFORM_QI", .val = PPC_INSN_FORM_PSFORM_QI }, + { .str = "PPC_INSN_FORM_PSFORM_X", .val = PPC_INSN_FORM_PSFORM_X }, + { .str = "PPC_INSN_FORM_PSFORM_Y", .val = PPC_INSN_FORM_PSFORM_Y }, + { .str = "PPC_INSN_FORM_REQUIRES", .val = PPC_INSN_FORM_REQUIRES }, + { .str = "PPC_INSN_FORM_SCFORM", .val = PPC_INSN_FORM_SCFORM }, + { .str = "PPC_INSN_FORM_VAFORM_1", .val = PPC_INSN_FORM_VAFORM_1 }, + { .str = "PPC_INSN_FORM_VAFORM_1A", .val = PPC_INSN_FORM_VAFORM_1A }, + { .str = "PPC_INSN_FORM_VAFORM_2", .val = PPC_INSN_FORM_VAFORM_2 }, + { .str = "PPC_INSN_FORM_VNFORM_VTAB5_SD3", + .val = PPC_INSN_FORM_VNFORM_VTAB5_SD3 }, + { .str = "PPC_INSN_FORM_VXFORM_1", .val = PPC_INSN_FORM_VXFORM_1 }, + { .str = "PPC_INSN_FORM_VXFORM_2", .val = PPC_INSN_FORM_VXFORM_2 }, + { .str = "PPC_INSN_FORM_VXFORM_3", .val = PPC_INSN_FORM_VXFORM_3 }, + { .str = "PPC_INSN_FORM_VXFORM_4", .val = PPC_INSN_FORM_VXFORM_4 }, + { .str = "PPC_INSN_FORM_VXFORM_5", .val = PPC_INSN_FORM_VXFORM_5 }, + { .str = "PPC_INSN_FORM_VXFORM_BF3_VAB5", + .val = PPC_INSN_FORM_VXFORM_BF3_VAB5 }, + { .str = "PPC_INSN_FORM_VXFORM_BX", .val = PPC_INSN_FORM_VXFORM_BX }, + { .str = "PPC_INSN_FORM_VXFORM_CR", .val = PPC_INSN_FORM_VXFORM_CR }, + { .str = "PPC_INSN_FORM_VXFORM_RD5_MP_VB5", + .val = PPC_INSN_FORM_VXFORM_RD5_MP_VB5 }, + { .str = "PPC_INSN_FORM_VXFORM_RD5_N3_VB5", + .val = PPC_INSN_FORM_VXFORM_RD5_N3_VB5 }, + { .str = "PPC_INSN_FORM_VXFORM_RD5_XO5_RS5", + .val = PPC_INSN_FORM_VXFORM_RD5_XO5_RS5 }, + { .str = "PPC_INSN_FORM_VXFORM_VTB5_RC", + .val = PPC_INSN_FORM_VXFORM_VTB5_RC }, + { .str = "PPC_INSN_FORM_VXRFORM_1", .val = PPC_INSN_FORM_VXRFORM_1 }, + { .str = "PPC_INSN_FORM_VX_RD5_EO5_RS5_PS1_XO9", + .val = PPC_INSN_FORM_VX_RD5_EO5_RS5_PS1_XO9 }, + { .str = "PPC_INSN_FORM_VX_RD5_RSP5_PS1_XO9", + .val = PPC_INSN_FORM_VX_RD5_RSP5_PS1_XO9 }, + { .str = "PPC_INSN_FORM_XFLFORM_1", .val = PPC_INSN_FORM_XFLFORM_1 }, + { .str = "PPC_INSN_FORM_XFORMMEMOP", .val = PPC_INSN_FORM_XFORMMEMOP }, + { .str = "PPC_INSN_FORM_XFORM_16", .val = PPC_INSN_FORM_XFORM_16 }, + { .str = "PPC_INSN_FORM_XFORM_17", .val = PPC_INSN_FORM_XFORM_17 }, + { .str = "PPC_INSN_FORM_XFORM_18", .val = PPC_INSN_FORM_XFORM_18 }, + { .str = "PPC_INSN_FORM_XFORM_20", .val = PPC_INSN_FORM_XFORM_20 }, + { .str = "PPC_INSN_FORM_XFORM_24", .val = PPC_INSN_FORM_XFORM_24 }, + { .str = "PPC_INSN_FORM_XFORM_24_SYNC", + .val = PPC_INSN_FORM_XFORM_24_SYNC }, + { .str = "PPC_INSN_FORM_XFORM_44", .val = PPC_INSN_FORM_XFORM_44 }, + { .str = "PPC_INSN_FORM_XFORM_45", .val = PPC_INSN_FORM_XFORM_45 }, + { .str = "PPC_INSN_FORM_XFORM_AT3", .val = PPC_INSN_FORM_XFORM_AT3 }, + { .str = "PPC_INSN_FORM_XFORM_ATB3", .val = PPC_INSN_FORM_XFORM_ATB3 }, + { .str = "PPC_INSN_FORM_XFORM_ATTN", .val = PPC_INSN_FORM_XFORM_ATTN }, + { .str = "PPC_INSN_FORM_XFORM_BASE_R3XO", + .val = PPC_INSN_FORM_XFORM_BASE_R3XO }, + { .str = "PPC_INSN_FORM_XFORM_BASE_R3XO_SWAPPED", + .val = PPC_INSN_FORM_XFORM_BASE_R3XO_SWAPPED }, + { .str = "PPC_INSN_FORM_XFORM_HTM0", .val = PPC_INSN_FORM_XFORM_HTM0 }, + { .str = "PPC_INSN_FORM_XFORM_HTM1", .val = PPC_INSN_FORM_XFORM_HTM1 }, + { .str = "PPC_INSN_FORM_XFORM_HTM2", .val = PPC_INSN_FORM_XFORM_HTM2 }, + { .str = "PPC_INSN_FORM_XFORM_HTM3", .val = PPC_INSN_FORM_XFORM_HTM3 }, + { .str = "PPC_INSN_FORM_XFORM_ICBT", .val = PPC_INSN_FORM_XFORM_ICBT }, + { .str = "PPC_INSN_FORM_XFORM_MBAR", .val = PPC_INSN_FORM_XFORM_MBAR }, + { .str = "PPC_INSN_FORM_XFORM_MTMSR", + .val = PPC_INSN_FORM_XFORM_MTMSR }, + { .str = "PPC_INSN_FORM_XFORM_SR", .val = PPC_INSN_FORM_XFORM_SR }, + { .str = "PPC_INSN_FORM_XFORM_SRIN", .val = PPC_INSN_FORM_XFORM_SRIN }, + { .str = "PPC_INSN_FORM_XFORM_TLBWS", + .val = PPC_INSN_FORM_XFORM_TLBWS }, + { .str = "PPC_INSN_FORM_XFORM_XD6_RA5_RB5", + .val = PPC_INSN_FORM_XFORM_XD6_RA5_RB5 }, + { .str = "PPC_INSN_FORM_XFORM_XT6_IMM5", + .val = PPC_INSN_FORM_XFORM_XT6_IMM5 }, + { .str = "PPC_INSN_FORM_XFORM_XT6_IMM5_VB5", + .val = PPC_INSN_FORM_XFORM_XT6_IMM5_VB5 }, + { .str = "PPC_INSN_FORM_XFXFORM_1", .val = PPC_INSN_FORM_XFXFORM_1 }, + { .str = "PPC_INSN_FORM_XFXFORM_3", .val = PPC_INSN_FORM_XFXFORM_3 }, + { .str = "PPC_INSN_FORM_XFXFORM_3P", .val = PPC_INSN_FORM_XFXFORM_3P }, + { .str = "PPC_INSN_FORM_XFXFORM_5", .val = PPC_INSN_FORM_XFXFORM_5 }, + { .str = "PPC_INSN_FORM_XFXFORM_5A", .val = PPC_INSN_FORM_XFXFORM_5A }, + { .str = "PPC_INSN_FORM_XLFORM_1", .val = PPC_INSN_FORM_XLFORM_1 }, + { .str = "PPC_INSN_FORM_XLFORM_2", .val = PPC_INSN_FORM_XLFORM_2 }, + { .str = "PPC_INSN_FORM_XLFORM_3", .val = PPC_INSN_FORM_XLFORM_3 }, + { .str = "PPC_INSN_FORM_XLFORM_4", .val = PPC_INSN_FORM_XLFORM_4 }, + { .str = "PPC_INSN_FORM_XLFORM_S", .val = PPC_INSN_FORM_XLFORM_S }, + { .str = "PPC_INSN_FORM_XOFORM_1", .val = PPC_INSN_FORM_XOFORM_1 }, + { .str = "PPC_INSN_FORM_XOFORM_RTAB5_L1", + .val = PPC_INSN_FORM_XOFORM_RTAB5_L1 }, + { .str = "PPC_INSN_FORM_XSFORM_1", .val = PPC_INSN_FORM_XSFORM_1 }, + { .str = "PPC_INSN_FORM_XX1FORM", .val = PPC_INSN_FORM_XX1FORM }, + { .str = "PPC_INSN_FORM_XX2FORM", .val = PPC_INSN_FORM_XX2FORM }, + { .str = "PPC_INSN_FORM_XX2FORM_1", .val = PPC_INSN_FORM_XX2FORM_1 }, + { .str = "PPC_INSN_FORM_XX2FORM_2", .val = PPC_INSN_FORM_XX2FORM_2 }, + { .str = "PPC_INSN_FORM_XX2FORM_AT3_XBP5_P2", + .val = PPC_INSN_FORM_XX2FORM_AT3_XBP5_P2 }, + { .str = "PPC_INSN_FORM_XX2_BF3_DCMX7_RS6", + .val = PPC_INSN_FORM_XX2_BF3_DCMX7_RS6 }, + { .str = "PPC_INSN_FORM_XX2_BF3_XO5_XB6_XO9", + .val = PPC_INSN_FORM_XX2_BF3_XO5_XB6_XO9 }, + { .str = "PPC_INSN_FORM_XX2_RD5_XO5_RS6", + .val = PPC_INSN_FORM_XX2_RD5_XO5_RS6 }, + { .str = "PPC_INSN_FORM_XX2_RD6_DCMX7_RS6", + .val = PPC_INSN_FORM_XX2_RD6_DCMX7_RS6 }, + { .str = "PPC_INSN_FORM_XX2_RD6_UIM5_RS6", + .val = PPC_INSN_FORM_XX2_RD6_UIM5_RS6 }, + { .str = "PPC_INSN_FORM_XX2_RD6_XO5_RS6", + .val = PPC_INSN_FORM_XX2_RD6_XO5_RS6 }, + { .str = "PPC_INSN_FORM_XX3FORM", .val = PPC_INSN_FORM_XX3FORM }, + { .str = "PPC_INSN_FORM_XX3FORM_1", .val = PPC_INSN_FORM_XX3FORM_1 }, + { .str = "PPC_INSN_FORM_XX3FORM_2", .val = PPC_INSN_FORM_XX3FORM_2 }, + { .str = "PPC_INSN_FORM_XX3FORM_AT3_XAB6", + .val = PPC_INSN_FORM_XX3FORM_AT3_XAB6 }, + { .str = "PPC_INSN_FORM_XX3FORM_AT3_XABP5_P1", + .val = PPC_INSN_FORM_XX3FORM_AT3_XABP5_P1 }, + { .str = "PPC_INSN_FORM_XX3FORM_RC", .val = PPC_INSN_FORM_XX3FORM_RC }, + { .str = "PPC_INSN_FORM_XX4FORM", .val = PPC_INSN_FORM_XX4FORM }, + { .str = "PPC_INSN_FORM_X_BF3_DCMX7_RS5", + .val = PPC_INSN_FORM_X_BF3_DCMX7_RS5 }, + { .str = "PPC_INSN_FORM_X_BF3_L1_RS5_RS5", + .val = PPC_INSN_FORM_X_BF3_L1_RS5_RS5 }, + { .str = "PPC_INSN_FORM_X_BF3_RS5_RS5", + .val = PPC_INSN_FORM_X_BF3_RS5_RS5 }, + { .str = "PPC_INSN_FORM_X_RD6_IMM8", .val = PPC_INSN_FORM_X_RD6_IMM8 }, + { .str = "PPC_INSN_FORM_Z23FORM_1", .val = PPC_INSN_FORM_Z23FORM_1 }, + { .str = "PPC_INSN_FORM_Z23FORM_3", .val = PPC_INSN_FORM_Z23FORM_3 }, + { .str = "PPC_INSN_FORM_Z23FORM_8", .val = PPC_INSN_FORM_Z23FORM_8 }, + { .str = "PPC_INSN_FORM_Z23FORM_RTAB5_CY2", + .val = PPC_INSN_FORM_Z23FORM_RTAB5_CY2 }, + { .str = "PPC_OP_IMM", .val = PPC_OP_IMM }, + { .str = "PPC_OP_MEM", .val = PPC_OP_MEM }, + { .str = "PPC_OP_REG", .val = PPC_OP_REG }, + { .str = "PPC_PRED_BIT_SET", .val = PPC_PRED_BIT_SET }, + { .str = "PPC_PRED_BIT_UNSET", .val = PPC_PRED_BIT_UNSET }, + { .str = "PPC_PRED_EQ", .val = PPC_PRED_EQ }, + { .str = "PPC_PRED_EQ_MINUS", .val = PPC_PRED_EQ_MINUS }, + { .str = "PPC_PRED_EQ_PLUS", .val = PPC_PRED_EQ_PLUS }, + { .str = "PPC_PRED_EQ_RESERVED", .val = PPC_PRED_EQ_RESERVED }, + { .str = "PPC_PRED_GE", .val = PPC_PRED_GE }, + { .str = "PPC_PRED_GE_MINUS", .val = PPC_PRED_GE_MINUS }, + { .str = "PPC_PRED_GE_PLUS", .val = PPC_PRED_GE_PLUS }, + { .str = "PPC_PRED_GE_RESERVED", .val = PPC_PRED_GE_RESERVED }, + { .str = "PPC_PRED_GT", .val = PPC_PRED_GT }, + { .str = "PPC_PRED_GT_MINUS", .val = PPC_PRED_GT_MINUS }, + { .str = "PPC_PRED_GT_PLUS", .val = PPC_PRED_GT_PLUS }, + { .str = "PPC_PRED_GT_RESERVED", .val = PPC_PRED_GT_RESERVED }, + { .str = "PPC_PRED_LE", .val = PPC_PRED_LE }, + { .str = "PPC_PRED_LE_MINUS", .val = PPC_PRED_LE_MINUS }, + { .str = "PPC_PRED_LE_PLUS", .val = PPC_PRED_LE_PLUS }, + { .str = "PPC_PRED_LE_RESERVED", .val = PPC_PRED_LE_RESERVED }, + { .str = "PPC_PRED_LT", .val = PPC_PRED_LT }, + { .str = "PPC_PRED_LT_MINUS", .val = PPC_PRED_LT_MINUS }, + { .str = "PPC_PRED_LT_PLUS", .val = PPC_PRED_LT_PLUS }, + { .str = "PPC_PRED_LT_RESERVED", .val = PPC_PRED_LT_RESERVED }, + { .str = "PPC_PRED_NE", .val = PPC_PRED_NE }, + { .str = "PPC_PRED_NE_MINUS", .val = PPC_PRED_NE_MINUS }, + { .str = "PPC_PRED_NE_PLUS", .val = PPC_PRED_NE_PLUS }, + { .str = "PPC_PRED_NE_RESERVED", .val = PPC_PRED_NE_RESERVED }, + { .str = "PPC_PRED_NS", .val = PPC_PRED_NS }, + { .str = "PPC_PRED_NU", .val = PPC_PRED_NU }, + { .str = "PPC_PRED_NU_MINUS", .val = PPC_PRED_NU_MINUS }, + { .str = "PPC_PRED_NU_PLUS", .val = PPC_PRED_NU_PLUS }, + { .str = "PPC_PRED_NU_RESERVED", .val = PPC_PRED_NU_RESERVED }, + { .str = "PPC_PRED_NZ", .val = PPC_PRED_NZ }, + { .str = "PPC_PRED_NZ_MINUS", .val = PPC_PRED_NZ_MINUS }, + { .str = "PPC_PRED_NZ_PLUS", .val = PPC_PRED_NZ_PLUS }, + { .str = "PPC_PRED_NZ_RESERVED", .val = PPC_PRED_NZ_RESERVED }, + { .str = "PPC_PRED_SO", .val = PPC_PRED_SO }, + { .str = "PPC_PRED_SPE", .val = PPC_PRED_SPE }, + { .str = "PPC_PRED_UN", .val = PPC_PRED_UN }, + { .str = "PPC_PRED_UN_MINUS", .val = PPC_PRED_UN_MINUS }, + { .str = "PPC_PRED_UN_PLUS", .val = PPC_PRED_UN_PLUS }, + { .str = "PPC_PRED_UN_RESERVED", .val = PPC_PRED_UN_RESERVED }, + { .str = "PPC_PRED_Z", .val = PPC_PRED_Z }, + { .str = "PPC_PRED_Z_MINUS", .val = PPC_PRED_Z_MINUS }, + { .str = "PPC_PRED_Z_PLUS", .val = PPC_PRED_Z_PLUS }, + { .str = "PPC_PRED_Z_RESERVED", .val = PPC_PRED_Z_RESERVED }, + { .str = "RISCV_GRP_BRANCH_RELATIVE", + .val = RISCV_GRP_BRANCH_RELATIVE }, + { .str = "RISCV_GRP_CALL", .val = RISCV_GRP_CALL }, + { .str = "RISCV_GRP_HASSTDEXTA", .val = RISCV_GRP_HASSTDEXTA }, + { .str = "RISCV_GRP_HASSTDEXTC", .val = RISCV_GRP_HASSTDEXTC }, + { .str = "RISCV_GRP_HASSTDEXTD", .val = RISCV_GRP_HASSTDEXTD }, + { .str = "RISCV_GRP_HASSTDEXTF", .val = RISCV_GRP_HASSTDEXTF }, + { .str = "RISCV_GRP_HASSTDEXTM", .val = RISCV_GRP_HASSTDEXTM }, + { .str = "RISCV_GRP_INT", .val = RISCV_GRP_INT }, + { .str = "RISCV_GRP_IRET", .val = RISCV_GRP_IRET }, + { .str = "RISCV_GRP_ISRV32", .val = RISCV_GRP_ISRV32 }, + { .str = "RISCV_GRP_ISRV64", .val = RISCV_GRP_ISRV64 }, + { .str = "RISCV_GRP_JUMP", .val = RISCV_GRP_JUMP }, + { .str = "RISCV_GRP_PRIVILEGE", .val = RISCV_GRP_PRIVILEGE }, + { .str = "RISCV_GRP_RET", .val = RISCV_GRP_RET }, + { .str = "RISCV_OP_IMM", .val = RISCV_OP_IMM }, + { .str = "RISCV_OP_MEM", .val = RISCV_OP_MEM }, + { .str = "RISCV_OP_REG", .val = RISCV_OP_REG }, + { .str = "SH_GRP_BRANCH_RELATIVE", .val = SH_GRP_BRANCH_RELATIVE }, + { .str = "SH_GRP_CALL", .val = SH_GRP_CALL }, + { .str = "SH_GRP_INT", .val = SH_GRP_INT }, + { .str = "SH_GRP_IRET", .val = SH_GRP_IRET }, + { .str = "SH_GRP_JUMP", .val = SH_GRP_JUMP }, + { .str = "SH_GRP_PRIVILEGE", .val = SH_GRP_PRIVILEGE }, + { .str = "SH_GRP_RET", .val = SH_GRP_RET }, + { .str = "SH_GRP_SH1", .val = SH_GRP_SH1 }, + { .str = "SH_GRP_SH2", .val = SH_GRP_SH2 }, + { .str = "SH_GRP_SH2A", .val = SH_GRP_SH2A }, + { .str = "SH_GRP_SH2AFPU", .val = SH_GRP_SH2AFPU }, + { .str = "SH_GRP_SH2DSP", .val = SH_GRP_SH2DSP }, + { .str = "SH_GRP_SH2E", .val = SH_GRP_SH2E }, + { .str = "SH_GRP_SH3", .val = SH_GRP_SH3 }, + { .str = "SH_GRP_SH3DSP", .val = SH_GRP_SH3DSP }, + { .str = "SH_GRP_SH4", .val = SH_GRP_SH4 }, + { .str = "SH_GRP_SH4A", .val = SH_GRP_SH4A }, + { .str = "SH_OP_IMM", .val = SH_OP_IMM }, + { .str = "SH_OP_MEM", .val = SH_OP_MEM }, + { .str = "SH_OP_MEM_GBR_DISP", .val = SH_OP_MEM_GBR_DISP }, + { .str = "SH_OP_MEM_GBR_R0", .val = SH_OP_MEM_GBR_R0 }, + { .str = "SH_OP_MEM_PCR", .val = SH_OP_MEM_PCR }, + { .str = "SH_OP_MEM_REG_DISP", .val = SH_OP_MEM_REG_DISP }, + { .str = "SH_OP_MEM_REG_IND", .val = SH_OP_MEM_REG_IND }, + { .str = "SH_OP_MEM_REG_POST", .val = SH_OP_MEM_REG_POST }, + { .str = "SH_OP_MEM_REG_PRE", .val = SH_OP_MEM_REG_PRE }, + { .str = "SH_OP_MEM_REG_R0", .val = SH_OP_MEM_REG_R0 }, + { .str = "SH_OP_MEM_TBR_DISP", .val = SH_OP_MEM_TBR_DISP }, + { .str = "SH_OP_REG", .val = SH_OP_REG }, + { .str = "SPARC_CC_FCC_A", .val = SPARC_CC_FCC_A }, + { .str = "SPARC_CC_FCC_E", .val = SPARC_CC_FCC_E }, + { .str = "SPARC_CC_FCC_G", .val = SPARC_CC_FCC_G }, + { .str = "SPARC_CC_FCC_GE", .val = SPARC_CC_FCC_GE }, + { .str = "SPARC_CC_FCC_L", .val = SPARC_CC_FCC_L }, + { .str = "SPARC_CC_FCC_LE", .val = SPARC_CC_FCC_LE }, + { .str = "SPARC_CC_FCC_LG", .val = SPARC_CC_FCC_LG }, + { .str = "SPARC_CC_FCC_N", .val = SPARC_CC_FCC_N }, + { .str = "SPARC_CC_FCC_NE", .val = SPARC_CC_FCC_NE }, + { .str = "SPARC_CC_FCC_O", .val = SPARC_CC_FCC_O }, + { .str = "SPARC_CC_FCC_U", .val = SPARC_CC_FCC_U }, + { .str = "SPARC_CC_FCC_UE", .val = SPARC_CC_FCC_UE }, + { .str = "SPARC_CC_FCC_UG", .val = SPARC_CC_FCC_UG }, + { .str = "SPARC_CC_FCC_UGE", .val = SPARC_CC_FCC_UGE }, + { .str = "SPARC_CC_FCC_UL", .val = SPARC_CC_FCC_UL }, + { .str = "SPARC_CC_FCC_ULE", .val = SPARC_CC_FCC_ULE }, + { .str = "SPARC_CC_ICC_A", .val = SPARC_CC_ICC_A }, + { .str = "SPARC_CC_ICC_CC", .val = SPARC_CC_ICC_CC }, + { .str = "SPARC_CC_ICC_CS", .val = SPARC_CC_ICC_CS }, + { .str = "SPARC_CC_ICC_E", .val = SPARC_CC_ICC_E }, + { .str = "SPARC_CC_ICC_G", .val = SPARC_CC_ICC_G }, + { .str = "SPARC_CC_ICC_GE", .val = SPARC_CC_ICC_GE }, + { .str = "SPARC_CC_ICC_GU", .val = SPARC_CC_ICC_GU }, + { .str = "SPARC_CC_ICC_L", .val = SPARC_CC_ICC_L }, + { .str = "SPARC_CC_ICC_LE", .val = SPARC_CC_ICC_LE }, + { .str = "SPARC_CC_ICC_LEU", .val = SPARC_CC_ICC_LEU }, + { .str = "SPARC_CC_ICC_N", .val = SPARC_CC_ICC_N }, + { .str = "SPARC_CC_ICC_NE", .val = SPARC_CC_ICC_NE }, + { .str = "SPARC_CC_ICC_NEG", .val = SPARC_CC_ICC_NEG }, + { .str = "SPARC_CC_ICC_POS", .val = SPARC_CC_ICC_POS }, + { .str = "SPARC_CC_ICC_VC", .val = SPARC_CC_ICC_VC }, + { .str = "SPARC_CC_ICC_VS", .val = SPARC_CC_ICC_VS }, + { .str = "SPARC_HINT_A", .val = SPARC_HINT_A }, + { .str = "SPARC_HINT_A_PN", .val = SPARC_HINT_A_PN }, + { .str = "SPARC_HINT_A_PT", .val = SPARC_HINT_A_PT }, + { .str = "SPARC_HINT_PN", .val = SPARC_HINT_PN }, + { .str = "SPARC_HINT_PT", .val = SPARC_HINT_PT }, + { .str = "SPARC_OP_IMM", .val = SPARC_OP_IMM }, + { .str = "SPARC_OP_MEM", .val = SPARC_OP_MEM }, + { .str = "SPARC_OP_REG", .val = SPARC_OP_REG }, + { .str = "SYSZ_OP_ACREG", .val = SYSZ_OP_ACREG }, + { .str = "SYSZ_OP_IMM", .val = SYSZ_OP_IMM }, + { .str = "SYSZ_OP_MEM", .val = SYSZ_OP_MEM }, + { .str = "SYSZ_OP_REG", .val = SYSZ_OP_REG }, + { .str = "TMS320C64X_FUNIT_D", .val = TMS320C64X_FUNIT_D }, + { .str = "TMS320C64X_FUNIT_L", .val = TMS320C64X_FUNIT_L }, + { .str = "TMS320C64X_FUNIT_M", .val = TMS320C64X_FUNIT_M }, + { .str = "TMS320C64X_FUNIT_NO", .val = TMS320C64X_FUNIT_NO }, + { .str = "TMS320C64X_FUNIT_S", .val = TMS320C64X_FUNIT_S }, + { .str = "TMS320C64X_GRP_FUNIT_D", .val = TMS320C64X_GRP_FUNIT_D }, + { .str = "TMS320C64X_GRP_FUNIT_L", .val = TMS320C64X_GRP_FUNIT_L }, + { .str = "TMS320C64X_GRP_FUNIT_M", .val = TMS320C64X_GRP_FUNIT_M }, + { .str = "TMS320C64X_GRP_FUNIT_NO", .val = TMS320C64X_GRP_FUNIT_NO }, + { .str = "TMS320C64X_GRP_FUNIT_S", .val = TMS320C64X_GRP_FUNIT_S }, + { .str = "TMS320C64X_GRP_JUMP", .val = TMS320C64X_GRP_JUMP }, + { .str = "TMS320C64X_MEM_DIR_BW", .val = TMS320C64X_MEM_DIR_BW }, + { .str = "TMS320C64X_MEM_DIR_FW", .val = TMS320C64X_MEM_DIR_FW }, + { .str = "TMS320C64X_MEM_DISP_CONSTANT", + .val = TMS320C64X_MEM_DISP_CONSTANT }, + { .str = "TMS320C64X_MEM_DISP_REGISTER", + .val = TMS320C64X_MEM_DISP_REGISTER }, + { .str = "TMS320C64X_MEM_MOD_NO", .val = TMS320C64X_MEM_MOD_NO }, + { .str = "TMS320C64X_MEM_MOD_POST", .val = TMS320C64X_MEM_MOD_POST }, + { .str = "TMS320C64X_MEM_MOD_PRE", .val = TMS320C64X_MEM_MOD_PRE }, + { .str = "TMS320C64X_OP_IMM", .val = TMS320C64X_OP_IMM }, + { .str = "TMS320C64X_OP_MEM", .val = TMS320C64X_OP_MEM }, + { .str = "TMS320C64X_OP_REG", .val = TMS320C64X_OP_REG }, + { .str = "TMS320C64X_OP_REGPAIR", .val = TMS320C64X_OP_REGPAIR }, + { .str = "TRICORE_OP_IMM", .val = TRICORE_OP_IMM }, + { .str = "TRICORE_OP_MEM", .val = TRICORE_OP_MEM }, + { .str = "TRICORE_OP_REG", .val = TRICORE_OP_REG }, + { .str = "WASM_GRP_CONTROL", .val = WASM_GRP_CONTROL }, + { .str = "WASM_GRP_MEMORY", .val = WASM_GRP_MEMORY }, + { .str = "WASM_GRP_NUMBERIC", .val = WASM_GRP_NUMBERIC }, + { .str = "WASM_GRP_PARAMETRIC", .val = WASM_GRP_PARAMETRIC }, + { .str = "WASM_GRP_VARIABLE", .val = WASM_GRP_VARIABLE }, + { .str = "WASM_OP_BRTABLE", .val = WASM_OP_BRTABLE }, + { .str = "WASM_OP_IMM", .val = WASM_OP_IMM }, + { .str = "WASM_OP_INT7", .val = WASM_OP_INT7 }, + { .str = "WASM_OP_NONE", .val = WASM_OP_NONE }, + { .str = "WASM_OP_UINT32", .val = WASM_OP_UINT32 }, + { .str = "WASM_OP_UINT64", .val = WASM_OP_UINT64 }, + { .str = "WASM_OP_VARUINT32", .val = WASM_OP_VARUINT32 }, + { .str = "WASM_OP_VARUINT64", .val = WASM_OP_VARUINT64 }, + { .str = "X86_AVX_BCAST_16", .val = X86_AVX_BCAST_16 }, + { .str = "X86_AVX_BCAST_2", .val = X86_AVX_BCAST_2 }, + { .str = "X86_AVX_BCAST_4", .val = X86_AVX_BCAST_4 }, + { .str = "X86_AVX_BCAST_8", .val = X86_AVX_BCAST_8 }, + { .str = "X86_AVX_CC_EQ", .val = X86_AVX_CC_EQ }, + { .str = "X86_AVX_CC_EQ_OS", .val = X86_AVX_CC_EQ_OS }, + { .str = "X86_AVX_CC_EQ_UQ", .val = X86_AVX_CC_EQ_UQ }, + { .str = "X86_AVX_CC_EQ_US", .val = X86_AVX_CC_EQ_US }, + { .str = "X86_AVX_CC_FALSE", .val = X86_AVX_CC_FALSE }, + { .str = "X86_AVX_CC_FALSE_OS", .val = X86_AVX_CC_FALSE_OS }, + { .str = "X86_AVX_CC_GE", .val = X86_AVX_CC_GE }, + { .str = "X86_AVX_CC_GE_OQ", .val = X86_AVX_CC_GE_OQ }, + { .str = "X86_AVX_CC_GT", .val = X86_AVX_CC_GT }, + { .str = "X86_AVX_CC_GT_OQ", .val = X86_AVX_CC_GT_OQ }, + { .str = "X86_AVX_CC_LE", .val = X86_AVX_CC_LE }, + { .str = "X86_AVX_CC_LE_OQ", .val = X86_AVX_CC_LE_OQ }, + { .str = "X86_AVX_CC_LT", .val = X86_AVX_CC_LT }, + { .str = "X86_AVX_CC_LT_OQ", .val = X86_AVX_CC_LT_OQ }, + { .str = "X86_AVX_CC_NEQ", .val = X86_AVX_CC_NEQ }, + { .str = "X86_AVX_CC_NEQ_OQ", .val = X86_AVX_CC_NEQ_OQ }, + { .str = "X86_AVX_CC_NEQ_OS", .val = X86_AVX_CC_NEQ_OS }, + { .str = "X86_AVX_CC_NEQ_US", .val = X86_AVX_CC_NEQ_US }, + { .str = "X86_AVX_CC_NGE", .val = X86_AVX_CC_NGE }, + { .str = "X86_AVX_CC_NGE_UQ", .val = X86_AVX_CC_NGE_UQ }, + { .str = "X86_AVX_CC_NGT", .val = X86_AVX_CC_NGT }, + { .str = "X86_AVX_CC_NGT_UQ", .val = X86_AVX_CC_NGT_UQ }, + { .str = "X86_AVX_CC_NLE", .val = X86_AVX_CC_NLE }, + { .str = "X86_AVX_CC_NLE_UQ", .val = X86_AVX_CC_NLE_UQ }, + { .str = "X86_AVX_CC_NLT", .val = X86_AVX_CC_NLT }, + { .str = "X86_AVX_CC_NLT_UQ", .val = X86_AVX_CC_NLT_UQ }, + { .str = "X86_AVX_CC_ORD", .val = X86_AVX_CC_ORD }, + { .str = "X86_AVX_CC_ORD_S", .val = X86_AVX_CC_ORD_S }, + { .str = "X86_AVX_CC_TRUE", .val = X86_AVX_CC_TRUE }, + { .str = "X86_AVX_CC_TRUE_US", .val = X86_AVX_CC_TRUE_US }, + { .str = "X86_AVX_CC_UNORD", .val = X86_AVX_CC_UNORD }, + { .str = "X86_AVX_CC_UNORD_S", .val = X86_AVX_CC_UNORD_S }, + { .str = "X86_AVX_RM_RD", .val = X86_AVX_RM_RD }, + { .str = "X86_AVX_RM_RN", .val = X86_AVX_RM_RN }, + { .str = "X86_AVX_RM_RU", .val = X86_AVX_RM_RU }, + { .str = "X86_AVX_RM_RZ", .val = X86_AVX_RM_RZ }, + { .str = "X86_EFLAGS_MODIFY_AF", .val = X86_EFLAGS_MODIFY_AF }, + { .str = "X86_EFLAGS_MODIFY_CF", .val = X86_EFLAGS_MODIFY_CF }, + { .str = "X86_EFLAGS_MODIFY_DF", .val = X86_EFLAGS_MODIFY_DF }, + { .str = "X86_EFLAGS_MODIFY_IF", .val = X86_EFLAGS_MODIFY_IF }, + { .str = "X86_EFLAGS_MODIFY_NT", .val = X86_EFLAGS_MODIFY_NT }, + { .str = "X86_EFLAGS_MODIFY_OF", .val = X86_EFLAGS_MODIFY_OF }, + { .str = "X86_EFLAGS_MODIFY_PF", .val = X86_EFLAGS_MODIFY_PF }, + { .str = "X86_EFLAGS_MODIFY_RF", .val = X86_EFLAGS_MODIFY_RF }, + { .str = "X86_EFLAGS_MODIFY_SF", .val = X86_EFLAGS_MODIFY_SF }, + { .str = "X86_EFLAGS_MODIFY_TF", .val = X86_EFLAGS_MODIFY_TF }, + { .str = "X86_EFLAGS_MODIFY_ZF", .val = X86_EFLAGS_MODIFY_ZF }, + { .str = "X86_EFLAGS_PRIOR_AF", .val = X86_EFLAGS_PRIOR_AF }, + { .str = "X86_EFLAGS_PRIOR_CF", .val = X86_EFLAGS_PRIOR_CF }, + { .str = "X86_EFLAGS_PRIOR_DF", .val = X86_EFLAGS_PRIOR_DF }, + { .str = "X86_EFLAGS_PRIOR_IF", .val = X86_EFLAGS_PRIOR_IF }, + { .str = "X86_EFLAGS_PRIOR_NT", .val = X86_EFLAGS_PRIOR_NT }, + { .str = "X86_EFLAGS_PRIOR_OF", .val = X86_EFLAGS_PRIOR_OF }, + { .str = "X86_EFLAGS_PRIOR_PF", .val = X86_EFLAGS_PRIOR_PF }, + { .str = "X86_EFLAGS_PRIOR_SF", .val = X86_EFLAGS_PRIOR_SF }, + { .str = "X86_EFLAGS_PRIOR_TF", .val = X86_EFLAGS_PRIOR_TF }, + { .str = "X86_EFLAGS_PRIOR_ZF", .val = X86_EFLAGS_PRIOR_ZF }, + { .str = "X86_EFLAGS_RESET_0F", .val = X86_EFLAGS_RESET_0F }, + { .str = "X86_EFLAGS_RESET_AC", .val = X86_EFLAGS_RESET_AC }, + { .str = "X86_EFLAGS_RESET_AF", .val = X86_EFLAGS_RESET_AF }, + { .str = "X86_EFLAGS_RESET_CF", .val = X86_EFLAGS_RESET_CF }, + { .str = "X86_EFLAGS_RESET_DF", .val = X86_EFLAGS_RESET_DF }, + { .str = "X86_EFLAGS_RESET_IF", .val = X86_EFLAGS_RESET_IF }, + { .str = "X86_EFLAGS_RESET_NT", .val = X86_EFLAGS_RESET_NT }, + { .str = "X86_EFLAGS_RESET_OF", .val = X86_EFLAGS_RESET_OF }, + { .str = "X86_EFLAGS_RESET_PF", .val = X86_EFLAGS_RESET_PF }, + { .str = "X86_EFLAGS_RESET_RF", .val = X86_EFLAGS_RESET_RF }, + { .str = "X86_EFLAGS_RESET_SF", .val = X86_EFLAGS_RESET_SF }, + { .str = "X86_EFLAGS_RESET_TF", .val = X86_EFLAGS_RESET_TF }, + { .str = "X86_EFLAGS_RESET_ZF", .val = X86_EFLAGS_RESET_ZF }, + { .str = "X86_EFLAGS_SET_AF", .val = X86_EFLAGS_SET_AF }, + { .str = "X86_EFLAGS_SET_CF", .val = X86_EFLAGS_SET_CF }, + { .str = "X86_EFLAGS_SET_DF", .val = X86_EFLAGS_SET_DF }, + { .str = "X86_EFLAGS_SET_IF", .val = X86_EFLAGS_SET_IF }, + { .str = "X86_EFLAGS_SET_OF", .val = X86_EFLAGS_SET_OF }, + { .str = "X86_EFLAGS_SET_PF", .val = X86_EFLAGS_SET_PF }, + { .str = "X86_EFLAGS_SET_SF", .val = X86_EFLAGS_SET_SF }, + { .str = "X86_EFLAGS_SET_ZF", .val = X86_EFLAGS_SET_ZF }, + { .str = "X86_EFLAGS_TEST_AF", .val = X86_EFLAGS_TEST_AF }, + { .str = "X86_EFLAGS_TEST_CF", .val = X86_EFLAGS_TEST_CF }, + { .str = "X86_EFLAGS_TEST_DF", .val = X86_EFLAGS_TEST_DF }, + { .str = "X86_EFLAGS_TEST_IF", .val = X86_EFLAGS_TEST_IF }, + { .str = "X86_EFLAGS_TEST_NT", .val = X86_EFLAGS_TEST_NT }, + { .str = "X86_EFLAGS_TEST_OF", .val = X86_EFLAGS_TEST_OF }, + { .str = "X86_EFLAGS_TEST_PF", .val = X86_EFLAGS_TEST_PF }, + { .str = "X86_EFLAGS_TEST_RF", .val = X86_EFLAGS_TEST_RF }, + { .str = "X86_EFLAGS_TEST_SF", .val = X86_EFLAGS_TEST_SF }, + { .str = "X86_EFLAGS_TEST_TF", .val = X86_EFLAGS_TEST_TF }, + { .str = "X86_EFLAGS_TEST_ZF", .val = X86_EFLAGS_TEST_ZF }, + { .str = "X86_EFLAGS_UNDEFINED_AF", .val = X86_EFLAGS_UNDEFINED_AF }, + { .str = "X86_EFLAGS_UNDEFINED_CF", .val = X86_EFLAGS_UNDEFINED_CF }, + { .str = "X86_EFLAGS_UNDEFINED_OF", .val = X86_EFLAGS_UNDEFINED_OF }, + { .str = "X86_EFLAGS_UNDEFINED_PF", .val = X86_EFLAGS_UNDEFINED_PF }, + { .str = "X86_EFLAGS_UNDEFINED_SF", .val = X86_EFLAGS_UNDEFINED_SF }, + { .str = "X86_EFLAGS_UNDEFINED_ZF", .val = X86_EFLAGS_UNDEFINED_ZF }, + { .str = "X86_FPU_FLAGS_MODIFY_C0", .val = X86_FPU_FLAGS_MODIFY_C0 }, + { .str = "X86_FPU_FLAGS_MODIFY_C1", .val = X86_FPU_FLAGS_MODIFY_C1 }, + { .str = "X86_FPU_FLAGS_MODIFY_C2", .val = X86_FPU_FLAGS_MODIFY_C2 }, + { .str = "X86_FPU_FLAGS_MODIFY_C3", .val = X86_FPU_FLAGS_MODIFY_C3 }, + { .str = "X86_FPU_FLAGS_RESET_C0", .val = X86_FPU_FLAGS_RESET_C0 }, + { .str = "X86_FPU_FLAGS_RESET_C1", .val = X86_FPU_FLAGS_RESET_C1 }, + { .str = "X86_FPU_FLAGS_RESET_C2", .val = X86_FPU_FLAGS_RESET_C2 }, + { .str = "X86_FPU_FLAGS_RESET_C3", .val = X86_FPU_FLAGS_RESET_C3 }, + { .str = "X86_FPU_FLAGS_SET_C0", .val = X86_FPU_FLAGS_SET_C0 }, + { .str = "X86_FPU_FLAGS_SET_C1", .val = X86_FPU_FLAGS_SET_C1 }, + { .str = "X86_FPU_FLAGS_SET_C2", .val = X86_FPU_FLAGS_SET_C2 }, + { .str = "X86_FPU_FLAGS_SET_C3", .val = X86_FPU_FLAGS_SET_C3 }, + { .str = "X86_FPU_FLAGS_TEST_C0", .val = X86_FPU_FLAGS_TEST_C0 }, + { .str = "X86_FPU_FLAGS_TEST_C1", .val = X86_FPU_FLAGS_TEST_C1 }, + { .str = "X86_FPU_FLAGS_TEST_C2", .val = X86_FPU_FLAGS_TEST_C2 }, + { .str = "X86_FPU_FLAGS_TEST_C3", .val = X86_FPU_FLAGS_TEST_C3 }, + { .str = "X86_FPU_FLAGS_UNDEFINED_C0", + .val = X86_FPU_FLAGS_UNDEFINED_C0 }, + { .str = "X86_FPU_FLAGS_UNDEFINED_C1", + .val = X86_FPU_FLAGS_UNDEFINED_C1 }, + { .str = "X86_FPU_FLAGS_UNDEFINED_C2", + .val = X86_FPU_FLAGS_UNDEFINED_C2 }, + { .str = "X86_FPU_FLAGS_UNDEFINED_C3", + .val = X86_FPU_FLAGS_UNDEFINED_C3 }, + { .str = "X86_OP_IMM", .val = X86_OP_IMM }, + { .str = "X86_OP_MEM", .val = X86_OP_MEM }, + { .str = "X86_OP_REG", .val = X86_OP_REG }, + { .str = "X86_PREFIX_0", .val = 0 }, + { .str = "X86_PREFIX_ADDRSIZE", .val = X86_PREFIX_ADDRSIZE }, + { .str = "X86_PREFIX_CS", .val = X86_PREFIX_CS }, + { .str = "X86_PREFIX_DS", .val = X86_PREFIX_DS }, + { .str = "X86_PREFIX_ES", .val = X86_PREFIX_ES }, + { .str = "X86_PREFIX_FS", .val = X86_PREFIX_FS }, + { .str = "X86_PREFIX_GS", .val = X86_PREFIX_GS }, + { .str = "X86_PREFIX_LOCK", .val = X86_PREFIX_LOCK }, + { .str = "X86_PREFIX_OPSIZE", .val = X86_PREFIX_OPSIZE }, + { .str = "X86_PREFIX_REP", .val = X86_PREFIX_REP }, + { .str = "X86_PREFIX_REPE", .val = X86_PREFIX_REPE }, + { .str = "X86_PREFIX_REPNE", .val = X86_PREFIX_REPNE }, + { .str = "X86_PREFIX_SS", .val = X86_PREFIX_SS }, + { .str = "X86_SSE_CC_EQ", .val = X86_SSE_CC_EQ }, + { .str = "X86_SSE_CC_LE", .val = X86_SSE_CC_LE }, + { .str = "X86_SSE_CC_LT", .val = X86_SSE_CC_LT }, + { .str = "X86_SSE_CC_NEQ", .val = X86_SSE_CC_NEQ }, + { .str = "X86_SSE_CC_NLE", .val = X86_SSE_CC_NLE }, + { .str = "X86_SSE_CC_NLT", .val = X86_SSE_CC_NLT }, + { .str = "X86_SSE_CC_ORD", .val = X86_SSE_CC_ORD }, + { .str = "X86_SSE_CC_UNORD", .val = X86_SSE_CC_UNORD }, + { .str = "X86_XOP_CC_EQ", .val = X86_XOP_CC_EQ }, + { .str = "X86_XOP_CC_FALSE", .val = X86_XOP_CC_FALSE }, + { .str = "X86_XOP_CC_GE", .val = X86_XOP_CC_GE }, + { .str = "X86_XOP_CC_GT", .val = X86_XOP_CC_GT }, + { .str = "X86_XOP_CC_LE", .val = X86_XOP_CC_LE }, + { .str = "X86_XOP_CC_LT", .val = X86_XOP_CC_LT }, + { .str = "X86_XOP_CC_NEQ", .val = X86_XOP_CC_NEQ }, + { .str = "X86_XOP_CC_TRUE", .val = X86_XOP_CC_TRUE }, + { .str = "XCORE_OP_IMM", .val = XCORE_OP_IMM }, + { .str = "XCORE_OP_MEM", .val = XCORE_OP_MEM }, + { .str = "XCORE_OP_REG", .val = XCORE_OP_REG }, + { .str = "zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz", + .val = 0xffffff }, // For testing +}; + +#endif // TEST_MAPPING_H diff --git a/suite/cstest/include/test_run.h b/suite/cstest/include/test_run.h new file mode 100644 index 0000000000..c21700cf26 --- /dev/null +++ b/suite/cstest/include/test_run.h @@ -0,0 +1,47 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef TESTRUN_H +#define TESTRUN_H + +#include "test_case.h" +#include + +typedef enum { + TEST_RUN_SUCCESS = 0, ///< All test cases succeeded. + TEST_RUN_FAILURE = 1, ///< At least one test case failed. + TEST_RUN_ERROR = 2, ///< Test run had errors. +} TestRunResult; + +typedef struct { + uint32_t valid_test_files; ///< Total number of test files. + uint32_t invalid_files; ///< Number of invalid files. + uint32_t tc_total; ///< Total number of test cases. + uint32_t successful; ///< Number of successful test cases. + uint32_t failed; ///< Number of failed test cases. + uint32_t errors; ///< Number errors (parsing errors etc). + uint32_t skipped; ///< Number skipped test cases. +} TestRunStats; + +typedef struct { + uint32_t case_cnt; + TestCase *cases; +} TestRun; + +/* CYAML configuration. */ +static const cyaml_config_t cyaml_config = { + .log_fn = cyaml_log, /* Use the default logging function. */ + .mem_fn = cyaml_mem, /* Use the default memory allocator. */ + .log_level = CYAML_LOG_WARNING, /* Logging errors and warnings only. */ +}; + +typedef struct { + size_t arch_bits; ///< Bits of the architecture. + TestCase *tcase; ///< The test case to check. + csh handle; ///< The Capstone instance for this test. Setup and teared down by the cmocka handlers. +} UnitTestState; + +TestRunResult cstest_run_tests(char **test_file_paths, uint32_t path_count, + TestRunStats *stats); + +#endif // TESTRUN_H diff --git a/suite/cstest/issues.cs b/suite/cstest/issues.cs deleted file mode 100644 index 189f397bf8..0000000000 --- a/suite/cstest/issues.cs +++ /dev/null @@ -1,1132 +0,0 @@ -!# issue 2323 eBPF bswap16 instruction -!# CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_EXTENDED, CS_OPT_DETAIL -0xd7,0x53,0x3f,0x0c,0x10,0x00,0x00,0x00 == bswap16 r3 - -!# issue 2323 eBPF bswap32 instruction -!# CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_EXTENDED, CS_OPT_DETAIL -0xd7,0x53,0x3f,0x0c,0x20,0x00,0x00,0x00 == bswap32 r3 - -!# issue 2323 eBPF bswap64 instruction -!# CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_EXTENDED, CS_OPT_DETAIL -0xd7,0x53,0x3f,0x0c,0x40,0x00,0x00,0x00 == bswap64 r3 - -!# issue 2258 vcmpunordss incorrect read/modified register -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL -0x62,0xd1,0x56,0x08,0xc2,0xca,0x03 == vcmpunordss k1, xmm5, xmm10 ; operands[0].access: WRITE ; operands[1].access: READ ; operands[2].access: READ - -!# issue 2062 repz Prefix -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL -0xf3,0xc3 == repz ret ; Prefix:0xf3 0x00 0x00 0x00 - -!# issue 2007 RISCV64 instruction groups -!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL -0x63,0x04,0x03,0x00 == beqz t1, 8 ; op_count: 2 ; operands[0].type: REG = t1 ; operands[1].type: IMM = 0x8 ; Groups: branch_relative jump - -!# issue 2007 RISCV64 instruction groups -!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL -0x73,0x00,0x00,0x00 == ecall ; Groups: int - -!# issue 2007 RISCV64 instruction groups -!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL -0xef,0x00,0x40,0x00 == jal 4 ; op_count: 1 ; operands[0].type: IMM = 0x4 ; Groups: call - -!# issue 2007 RISCV32 instruction groups -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x63,0x04,0x03,0x00 == beqz t1, 8 ; op_count: 2 ; operands[0].type: REG = t1 ; operands[1].type: IMM = 0x8 ; Groups: branch_relative jump - -!# issue 2007 RISCV32 instruction groups -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x73,0x00,0x00,0x00 == ecall ; Groups: int - -!# issue 2007 RISCV32 instruction groups -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xef,0x00,0x40,0x00 == jal 4 ; op_count: 1 ; operands[0].type: IMM = 0x4 ; Groups: call - -!# issue 2007 RISCV32 instruction groups -!# CS_ARCH_RISCV, CS_MODE_RISCV32 CS_MODE_RISCVC, CS_OPT_DETAIL -0x11,0x20 == c.jal 4 ; op_count: 1 ; operands[0].type: IMM = 0x4 ; Groups: hasStdExtC isrv32 call - -!# issue 2007 RISCV32 instruction groups -!# CS_ARCH_RISCV, CS_MODE_RISCV32 CS_MODE_RISCVC, CS_OPT_DETAIL -0x91,0xc1 == c.beqz a1, 4 ; op_count: 2 ; operands[0].type: REG = a1 ; operands[1].type: IMM = 0x4 ; Groups: hasStdExtC branch_relative jump - -!# issue 1997 notrack jmp -!# CS_ARCH_X86, CS_MODE_64, None -0x3e,0xff,0xe0 == notrack jmp rax - -!# issue 1997 notrack call -!# CS_ARCH_X86, CS_MODE_64, None -0x3e,0xff,0xd0 == notrack call rax - -!# issue 1924 SME Index instruction alias printing is not always valid -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x02,0x00,0x9f,0xe0 == ld1w {za0h.s[w12, 2]}, p0/z, [x0] ; op_count: 3 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.tile: za0.s ; operands[0].sme.slice_reg: w12 ; operands[0].sme.slice_offset: 2 ; operands[0].sme.is_vertical: false ; operands[0].access: WRITE ; operands[0].vas: 0x20 ; operands[1].type: PREDICATE ; operands[1].pred.reg: p0 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = x0 ; operands[2].access: READ ; Registers read: w12 p0 x0 ; Registers modified: za0.s ; Groups: HasSME - -!# issue 1912 PPC register name -!# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, None -0x2d,0x03,0x00,0x80 == cmpwi cr2, r3, 0x80 - -!# issue 1912 PPC no register name -!# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME -0x2d,0x03,0x00,0x80 == cmpwi 2, 3, 0x80 - -!# issue 1902 PPC psq_st negative displacement -!# CS_ARCH_PPC, CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_PS, CS_OPT_DETAIL -0xf3,0xec,0x0f,0xf8 == psq_st f31, -8(r12), 0, 0 ; op_count: 4 ; operands[0].type: REG = f31 ; operands[1].type: MEM ; operands[1].mem.base: REG = r12 ; operands[1].mem.disp: 0xfffffff8 ; operands[2].type: IMM = 0x0 ; operands[3].type: IMM = 0x0 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x21,0x04,0x03,0x5e == mov b1, v1.b[1] ; operands[1].vas: 0x8 ; operands[1].vector_index: 1 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0xc0,0x1e,0x03,0x4e == mov v0.b[1], w22 ; operands[0].vas: 0x8 ; operands[0].vector_index: 1 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0xc0,0x1e,0x06,0x4e == mov v0.h[1], w22 ; operands[0].vas: 0x10 ; operands[0].vector_index: 1 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0xc0,0x1e,0x0c,0x4e == mov v0.s[1], w22 ; operands[0].vas: 0x20 ; operands[0].vector_index: 1 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0xc0,0x1e,0x18,0x4e == mov v0.d[1], x22 ; operands[0].vas: 0x40 ; operands[0].vector_index: 1 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x20,0x0c,0x03,0x6e == mov v0.b[1], v1.b[1] ; operands[0].vas: 0x8 ; operands[0].vector_index: 1 ; operands[1].vas: 0x8 ; operands[1].vector_index: 1 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x20,0x14,0x06,0x6e == mov v0.h[1], v1.h[1] ; operands[0].vas: 0x10 ; operands[0].vector_index: 1 ; operands[1].vas: 0x10 ; operands[1].vector_index: 1 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x20,0x24,0x0c,0x6e == mov v0.s[1], v1.s[1] ; operands[0].vas: 0x20 ; operands[0].vector_index: 1 ; operands[1].vas: 0x20 ; operands[1].vector_index: 1 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x20,0x44,0x18,0x6e == mov v0.d[1], v1.d[1] ; operands[0].vas: 0x40 ; operands[0].vector_index: 1 ; operands[1].vas: 0x40 ; operands[1].vector_index: 1 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x20,0x3c,0x0c,0x0e == mov w0, v1.s[1] ; operands[1].vas: 0x20 ; operands[1].vector_index: 1 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x20,0x3c,0x0c,0x0e == mov w0, v1.s[1] ; operands[1].vas: 0x20 ; operands[1].vector_index: 1 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x20,0x3c,0x18,0x4e == mov x0, v1.d[1] ; operands[1].vas: 0x40 ; operands[1].vector_index: 1 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x20,0x3c,0x18,0x4e == mov x0, v1.d[1] ; operands[1].vas: 0x40 ; operands[1].vector_index: 1 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x00,0xc0,0x50,0x05 == fmov z0.h, p0/m, #2.00000000 ; operands[0].vas: 0x10 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x00,0xc0,0x79,0x25 == fmov z0.h, #2.00000000 ; operands[0].vas: 0x10 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0xa1,0xca,0xf8,0x25 == mov z1.d, #0x55 ; operands[0].vas: 0x40 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x21,0x44,0x81,0x25 == mov p1.b, p1.b ; operands[0].vas: 0x8 ; operands[1].vas: 0x8 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x21,0x40,0x51,0x05 == mov z1.h, p1/m, #1 ; operands[0].vas: 0x10 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x21,0x00,0x51,0x05 == mov z1.h, p1/z, #1 ; operands[0].vas: 0x10 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x20,0xc0,0x38,0x25 == mov z0.b, #1 ; operands[0].vas: 0x8 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x71,0x4a,0x01,0x25 == mov p1.b, p2/m, p3.b ; operands[0].vas: 0x8 ; operands[2].vas: 0x8 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x61,0x48,0x03,0x25 == mov p1.b, p2/z, p3.b ; operands[0].vas: 0x8 ; operands[2].vas: 0x8 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x21,0xa8,0x28,0x05 == mov z1.b, p2/m, w1 ; operands[0].vas: 0x8 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x21,0x38,0x20,0x05 == mov z1.b, w1 ; operands[0].vas: 0x8 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x01,0x88,0x20,0x05 == mov z1.b, p2/m, b0 ; operands[0].vas: 0x8 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x00,0x20,0x21,0x05 == mov z0.b, b0 ; operands[0].vas: 0x8 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x00,0x20,0x23,0x05 == mov z0.b, z0.b[1] ; operands[0].vas: 0x8 ; operands[1].vas: 0x8 ; operands[1].vector_index: 1 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x20,0xc4,0x20,0x05 == mov z0.b, p1/m, z1.b ; operands[0].vas: 0x8 ; operands[2].vas: 0x8 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x20,0x30,0x61,0x04 == mov z0.d, z1.d ; operands[0].vas: 0x40 ; operands[1].vas: 0x40 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x40,0x44,0x42,0x25 == movs p0.b, p1/z, p2.b ; operands[0].vas: 0x8 ; operands[2].vas: 0x8 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x20,0x44,0xc1,0x25 == movs p0.b, p1.b ; operands[0].vas: 0x8 ; operands[1].vas: 0x8 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x40,0x46,0x01,0x25 == not p0.b, p1/z, p2.b ; operands[0].vas: 0x8 ; operands[2].vas: 0x8 - -!# issue 1873 AArch64 missing VAS specifiers in aliased instructions -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x40,0x46,0x41,0x25 == nots p0.b, p1/z, p2.b ; operands[0].vas: 0x8 ; operands[2].vas: 0x8 - -!# issue 1856 AArch64 SYS instruction operands: tlbi 1 op -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x1f,0x83,0x08,0xd5 == tlbi vmalle1is ; op_count: 1 ; operands[0].subtype TLBI = 0x418 - -!# issue 1856 AArch64 SYS instruction operands: tlbi 2 op -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x22,0x87,0x08,0xd5 == tlbi vae1, x2 ; op_count: 2 ; operands[0].subtype TLBI = 0x439 - -!# issue 1856 AArch64 SYS instruction operands: at -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0xc0,0x78,0x0c,0xd5 == at s12e0r, x0 ; op_count: 2 ; operands[0].subtype AT = 0x23c6 - -!# issue 1856 AArch64 SYS instruction operands: dc -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x22,0x7b,0x0b,0xd5 == dc cvau, x2 ; op_count: 2 ; operands[0].subtype DC = 0x1bd9 - -!# issue 1856 AArch64 SYS instruction operands: ic -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x20,0x75,0x0b,0xd5 == ic ivau, x0 ; op_count: 2 ; operands[0].subtype IC = 0x1ba9 - -!# issue 1843 AArch64 missing VAS specifiers in aliased instructions: mov 16b -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x40,0x1e,0xb2,0x4e == mov v0.16b, v18.16b ; operands[0].type: REG = q0 (vreg) ; operands[0].vas: 0x1008 ; operands[1].type: REG = q18 (vreg) ; operands[1].vas: 0x1008 - -!# issue 1843 AArch64 missing VAS specifiers in aliased instructions: mov 8b -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x40,0x1e,0xb2,0x0e == mov v0.8b, v18.8b ; operands[0].type: REG = d0 (vreg) ; operands[0].vas: 0x808 ; operands[1].type: REG = d18 (vreg) ; operands[1].vas: 0x808 - -!# issue 1843 AArch64 missing VAS specifiers in aliased instructions: mvn 16b -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x40,0x5a,0x20,0x6e == mvn v0.16b, v18.16b ; operands[0].type: REG = q0 (vreg) ; operands[0].vas: 0x1008 ; operands[1].type: REG = q18 (vreg) ; operands[1].vas: 0x1008 - -!# issue 1843 AArch64 missing VAS specifiers in aliased instructions: mvn 8b -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x40,0x5a,0x20,0x2e == mvn v0.8b, v18.8b ; operands[0].type: REG = d0 (vreg) ; operands[0].vas: 0x808 ; operands[1].type: REG = d18 (vreg) ; operands[1].vas: 0x808 - -!# issue 1839 AArch64 Incorrect detailed disassembly of ldr -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x41,0x00,0x40,0xf9 == ldr x1, [x2] ; operands[0].access: WRITE ; operands[1].access: READ - -// !# issue 1827 x86-16 lcall 0:0xd -// !# CS_ARCH_X86, CS_MODE_16, CS_OPT_DETAIL -// 0x9a,0x0d,0x00,0x00,0x00 == lcall 0:0xd - -!# issue 1827 x16 lcall seg:off format -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL -0xb8,0x01,0x00,0x00,0x00 == mov eax, 1 -0xb9,0x00,0x00,0x00,0x00 == mov ecx, 0 -0x80,0xb8,0x01,0x00,0x00,0x00,0xb9 == cmp byte ptr [eax + 1], 0xb9 -0x00,0x00 == add byte ptr [eax], al -0x01,0x00 == add dword ptr [eax], eax - -!# issue 1827 x16 lcall seg:off format -!# CS_ARCH_X86, CS_MODE_16, CS_OPT_DETAIL -0x33,0xc0 == xor ax, ax -0xba,0x5a,0xff == mov dx, 0xff5a - -!# issue 1710 M68K floating point immediates broken on big endian hosts -!# CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, None -0xf2,0x3c,0x44,0x22,0x40,0x49,0x0e,0x56 == fadd.s #3.141500, fp0 - -!# issue 1708 M68K floating point loads and stores generate the same op_str -!# CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, None -0xf2,0x27,0x74,0x00 == fmove.d fp0, -(a7) -0xf2,0x1f,0x54,0x80 == fmove.d (a7)+, fp1 -0x4e,0x75 == rts - -!# issue 1661 M68K invalid transfer direction in MOVEC instruction -!# CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, None -0x4E,0x7A,0x00,0x02 == movec cacr, d0 - -// !# issue 1653 AArch64 wrong register access read/write flags on cmp instruction -// !# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -// 0x3F,0x00,0x02,0xEB == cmp x1, x2 ; operands[0].access: READ - -!# issue 1643 M68K incorrect read of 32-bit imm for bsr -!# CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040 , None -0x61,0xff,0x00,0x00,0x0b,0xea == bsr.l $bec - -!# issue 1627 Arm64 LD1 missing immediate operand -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0xe0,0x73,0xdf,0x0c == ld1 { v0.8b }, [sp], #8 ; operands[0].vas: 0x808 ; operands[1].type: MEM ; operands[1].mem.base: REG = sp ; operands[1].mem.disp: 0x8 ; operands[1].access: READ - -!# issue 1587 ARM thumb pushed registers write -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0x2d,0xe9,0xf0,0x47 == push.w {r4, r5, r6, r7, r8, r9, r10, lr} ; operands[0].access: READ - -!# issue 1504 movhps qword ptr -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL -0x0f,0x16,0x08 == movhps xmm1, qword ptr [rax] ; Opcode:0x0f 0x16 0x00 0x00 - -!# issue 1505 opcode 0f -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL -0x0f,0xa5,0xc2 == shld edx, eax, cl ; Opcode:0x0f 0xa5 0x00 0x00 - -!# issue 1478 tbegin. -!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL -0x7c,0x20,0x05,0x1d == tbegin. 1 ; Update-CR0: True - -!# issue 970 PPC bdnzt lt -!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL -0x41,0x00,0xff,0xac == bdnzt lt, 0xffffffffffffffac ; operands[0].type: REG = 0 - -!# issue 970 PPC bdnzt eq -!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL -0x41,0x02,0xff,0xac == bdnzt eq, 0xffffffffffffffac ; operands[0].type: REG = 2 - -!# issue 969 PPC bdnzflr operand 2 -!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL -0x4c,0x10,0x00,0x20 == bdnzflr 4*cr4+lt ; operands[0].type: REG = 16 - -0x41,0x82,0x00,0x10 == bt eq, 0x10 ; Groups: jump - -!# issue 1481 AARCH64 LDR operand2 -!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL -0xe9,0x03,0x40,0xf9 == ldr x9, [sp] ; operands[1].mem.base: REG = sp - -!# issue 968 PPC absolute branch: bdnzla -!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, None -0x1000: 0x42,0x00,0x12,0x37 == bcla 0x10, lt, 0x1234 - -!# issue 968 PPC absolute branch: bdzla -!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, None -0x1000: 0x42,0x40,0x12,0x37 == bcla 0x12, lt, 0x1234 - -!# issue X86 xrelease xchg -!# CS_ARCH_X86, CS_MODE_32, None -0xf3,0x87,0x03 == xrelease xchg dword ptr [ebx], eax - -!# issue X86 xacquire xchg -!# CS_ARCH_X86, CS_MODE_32, None -0xf2,0x87,0x03 == xacquire xchg dword ptr [ebx], eax - -!# issue X86 xrelease -!# CS_ARCH_X86, CS_MODE_64, None -0xf3,0xf0,0x31,0x1f == xrelease lock xor dword ptr [rdi], ebx - -!# issue 1477 X86 xacquire -!# CS_ARCH_X86, CS_MODE_64, None -0xf2,0xf0,0x31,0x1f == xacquire lock xor dword ptr [rdi], ebx - -!# issue PPC JUMP group -!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL -0x41,0x82,0x00,0x10 == bt eq, 0x10 ; Groups: jump branch_relative - -!# issue 1468 PPC bdnz -!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, None -0x101086c: 0x42,0x00,0xff,0xf8 == bc 0x10, lt, 0x1010864 - -!# issue PPC bdnzt -!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, None -0x1000: 0x41,0x00,0xff,0xac == bdnzt lt, 0xfac - -!# issue 1469 PPC CRx -!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL -0x4c,0x02,0x39,0x82 == crxor lt, eq, 4*cr1+un ; operands[0].type: REG = 0 ; operands[1].type: REG = 2 ; operands[2].type: REG = 7 - -!# issue 1468 B target -!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, None -0x1000: 0x4b,0xff,0xf8,0x00 == b 0x800 - -!# issue 1456 test alt 1 -!# CS_ARCH_X86, CS_MODE_32, None -0xf6,0x08,0x00 == test byte ptr [eax], 0 - -!# issue 1456 test alt 2 -!# CS_ARCH_X86, CS_MODE_32, None -0xf7,0x08,0x00,0x00,0x00,0x00 == test dword ptr [eax], 0 - -!# issue 1472 lock sub -!# CS_ARCH_X86, CS_MODE_32, None -0xF0,0x2B,0x45,0x08 == lock sub eax, dword ptr [ebp + 8] - -!# issue 1472 lock or -!# CS_ARCH_X86, CS_MODE_32, None -0xF0,0x0B,0x45,0x08 == lock or eax, dword ptr [ebp + 8] - -!# issue 1472 lock and -!# CS_ARCH_X86, CS_MODE_32, None -0xF0,0x23,0x45,0x08 == lock and eax, dword ptr [ebp + 8] - -!# issue 1472 lock add -!# CS_ARCH_X86, CS_MODE_32, None -0xF0,0x03,0x45,0x08 == lock add eax, dword ptr [ebp + 8] - -!# issue 1456 MOV dr -!# CS_ARCH_X86, CS_MODE_32, None -0x0f,0x23,0x00 == mov dr0, eax - -!# issue 1456 MOV dr -!# CS_ARCH_X86, CS_MODE_32, None -0x0f,0x21,0x00 == mov eax, dr0 - -!# issue 1456 MOV cr -!# CS_ARCH_X86, CS_MODE_32, None -0x0f,0x22,0x00 == mov cr0, eax - -!# issue 1472 lock adc -!# CS_ARCH_X86, CS_MODE_32, None -0xf0,0x12,0x45,0x08 == lock adc al, byte ptr [ebp + 8] - -!# issue 1456 xmmword -!# CS_ARCH_X86, CS_MODE_32, None -0x66,0x0f,0x2f,0x00 == comisd xmm0, xmmword ptr [eax] - -!# issue 1456 ARM printPKHASRShiftImm -!# CS_ARCH_ARM, CS_MODE_THUMB, None -0xca,0xea,0x21,0x06 == pkhtb r6, r10, r1, asr #0x20 - -!# issue 1456 EIZ -!# CS_ARCH_X86, CS_MODE_32, None -0x8d,0xb4,0x26,0x00,0x00,0x00,0x00 == lea esi, [esi] - -!# issue 1456 ARM POP -!# CS_ARCH_ARM, CS_MODE_LITTLE_ENDIAN, None -0x04,0x10,0x9d,0xe4 == pop {r1} - -!# issue 1456 -!# CS_ARCH_ARM, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL -0x31,0x02,0xa0,0xe1 == lsr r0, r1, r2 ; operands[2].type: REG = r2 - -!# issue 1456 -!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL -0x0c,0x00,0x80,0x12 == mov w12, #-1 ; operands[1].type: IMM = 0xffffffffffffffff - -0xb8,0x00,0x00,0x00,0x00 == movl $0, %eax - -!# issue 1456 -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT -0xb8,0x00,0x00,0x00,0x00 == movl $0, %eax - -0xd1,0x5e,0x48 == rcrl $1, 0x48(%esi) - -!# issue 1456 -!# CS_ARCH_X86, CS_MODE_32, None -0xd1,0x5e,0x48 == rcr dword ptr [esi + 0x48], 1 - -!# issue 1456 -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT -0xd1,0x5e,0x48 == rcrl $1, 0x48(%esi) - -!# issue 1456 -!# CS_ARCH_X86, CS_MODE_32, None -0x62,0x00 == bound eax, qword ptr [eax] - -!# issue 1454 -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL -0xf0,0x0f,0xb1,0x1e == lock cmpxchg dword ptr [esi], ebx ; Registers read: eax esi ebx - -!# issue 1452 -!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL -0x20,0x3c,0x0c,0x0e == mov w0, v1.s[1] ; operands[1].vas: 0x20 - -!# issue 1452 -!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL -0x20,0x3c,0x18,0x4e == mov x0, v1.d[1] ; operands[1].vas: 0x40 - -!# issue 1452 -!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL -0x20,0x3c,0x03,0x0e == umov w0, v1.b[1] ; operands[1].vas: 0x8 - -!# issue 1452 -!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL -0x20,0x3c,0x06,0x0e == umov w0, v1.h[1] ; operands[1].vas: 0x10 - -!# issue 1211 -!# CS_ARCH_X86, CS_MODE_64, None -0xc4,0xe1,0xf8,0x90,0xc0 == kmovq k0, k0 - -!# issue 1211 -!# CS_ARCH_X86, CS_MODE_64, None -0xc4,0xe1,0xfb,0x92,0xc3 == kmovq k0, rbx - -!# issue 1211 -!# CS_ARCH_X86, CS_MODE_64, None -0x62,0xf1,0x7d,0x48,0x74,0x83,0x12,0x00,0x00,0x00 == vpcmpeqb k0, zmm0, zmmword ptr [rbx + 0x12] - -!# issue 1211 -!# CS_ARCH_X86, CS_MODE_64, None -0x62,0xf2,0x7d,0x48,0x30,0x43,0x08 == vpmovzxbw zmm0, ymmword ptr [rbx + 0x100] - -!# issue x86 BND register (OSS-fuzz #13467) -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL -0x0f,0x1a,0x1a == bndldx bnd3, [edx] ; operands[0].type: REG = bnd3 - -!# issue 1335 -!# CS_ARCH_X86, CS_MODE_32, None -0x0f,0x1f,0xc0 == nop eax - -!# issue 1335 -!# CS_ARCH_X86, CS_MODE_64, None -0x48,0x0f,0x1f,0x00 == nop qword ptr [rax] - -!# issue 1259 -!# CS_ARCH_X86, CS_MODE_64, None -0x0f,0x0d,0x44,0x11,0x40 == prefetch byte ptr [rcx + rdx + 0x40] - -!# issue 1259 -!# CS_ARCH_X86, CS_MODE_64, None -0x41,0x0f,0x0d,0x44,0x12,0x40 == prefetch byte ptr [r10 + rdx + 0x40] - -!# issue 1304 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL -0x66,0x0f,0x7f,0x4c,0x24,0x40 == movdqa xmmword ptr [rsp + 0x40], xmm1 ; operands[0].access: WRITE - -!# issue 1304 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL -0x66,0x0f,0x7e,0x04,0x24 == movd dword ptr [rsp], xmm0 ; operands[0].access: WRITE - -!# issue 1304 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL -0xf3,0x41,0x0f,0x7f,0x4d,0x00 == movdqu xmmword ptr [r13], xmm1 ; operands[0].access: WRITE - -!# issue 1346 -!# CS_ARCH_X86, CS_MODE_64, None -0xf3,0x48,0x0f,0x1e,0xc8 == rdsspq rax - -!# issue 1346 -!# CS_ARCH_X86, CS_MODE_64, None -0xf3,0x0f,0x1e,0xc8 == rdsspd eax - -!# issue 1346 -!# CS_ARCH_X86, CS_MODE_64, None -0xf3,0x48,0x0f,0xae,0xe8 == incsspq rax - -!# issue 1346 -!# CS_ARCH_X86, CS_MODE_64, None -0xf3,0x0f,0xae,0xe8 == incsspd eax - -!# issue 1346 -!# CS_ARCH_X86, CS_MODE_64, None -0xf3,0x0f,0x01,0xea == saveprevssp - -!# issue 1346 -!# CS_ARCH_X86, CS_MODE_64, None -0xf3,0x0f,0x01,0x28 == rstorssp dword ptr [rax] - -!# issue 1346 -!# CS_ARCH_X86, CS_MODE_64, None -0x67,0xf3,0x0f,0x01,0x28 == rstorssp dword ptr [eax] - -!# issue 1346 -!# CS_ARCH_X86, CS_MODE_64, None -0x48,0x0f,0x38,0xf6,0x00 == wrssq qword ptr [rax], rax - -!# issue 1346 -!# CS_ARCH_X86, CS_MODE_64, None -0x67,0x0f,0x38,0xf6,0x00 == wrssd dword ptr [eax], eax - -!# issue 1346 -!# CS_ARCH_X86, CS_MODE_64, None -0xf3,0x0f,0x01,0xe8 == setssbsy - -!# issue 1346 -!# CS_ARCH_X86, CS_MODE_64, None -0xf3,0x0f,0xae,0x30 == clrssbsy dword ptr [rax] - -!# issue 1346 -!# CS_ARCH_X86, CS_MODE_64, None -0x67,0xf3,0x0f,0xae,0x30 == clrssbsy dword ptr [eax] - -!# issue 1206 -!# CS_ARCH_X86, CS_MODE_64, None -0xc4,0xe2,0x7d,0x5a,0x0c,0x0e == vbroadcasti128 ymm1, xmmword ptr [rsi + rcx] - -!# issue xchg 16bit -!# CS_ARCH_X86, CS_MODE_16, None -0x91 == xchg cx, ax - -!# issue ROL 1, ATT syntax -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT -0x66,0x48,0xf3,0xd1,0xc0 == rolw $1, %ax - -!# issue 1129 -!# CS_ARCH_X86, CS_MODE_64, None -0xf3,0x0f,0x1e,0xfa == endbr64 - -!# issue 1129 -!# CS_ARCH_X86, CS_MODE_32, None -0xf3,0x0f,0x1e,0xfa == endbr64 - -!# issue 1129 -!# CS_ARCH_X86, CS_MODE_64, None -0xf3,0x0f,0x1e,0xfb == endbr32 - -!# issue 1129 -!# CS_ARCH_X86, CS_MODE_32, None -0xf3,0x0f,0x1e,0xfb == endbr32 - -!# issue x64 jmp -!# CS_ARCH_X86, CS_MODE_64, None -0x1000: 0xeb,0xfe == jmp 0x1000 - -!# issue x64att jmp -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT -0x1000: 0xeb,0xfe == jmp 0x1000 - -!# issue x32 jmp -!# CS_ARCH_X86, CS_MODE_32, None -0x1000: 0xeb,0xfe == jmp 0x1000 - -!# issue x32att jmp -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT -0x1000: 0xeb,0xfe == jmp 0x1000 - -!# issue 1389 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL -0x66,0x0f,0x73,0xf9,0x01 == pslldq xmm1, 1 ; operands[1].size: 1 - -!# issue 1389 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT | CS_OPT_DETAIL -0x66,0x0f,0x73,0xf9,0x01 == pslldq $1, %xmm1 ; operands[0].size: 1 - -!# issue x64 unsigned -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_UNSIGNED -0x66,0x83,0xc0,0x80 == add ax, 0xff80 - -!# issue x64att unsigned -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT | CS_OPT_UNSIGNED -0x66,0x83,0xc0,0x80 == addw $0xff80, %ax - -!# issue 1323 -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0x0: 0x70,0x47,0x00 == bx lr ; op_count: 1 ; operands[0].type: REG = r14 ; operands[0].access: READ ; Registers read: r14 ; Groups: jump IsThumb - -!# issue 1317 -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0x0: 0xd0,0xe8,0x11,0xf0 == tbh [r0, r1, lsl #1] ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = r0 ; operands[0].mem.index: REG = r1 ; operands[0].mem.lshift: 0x1 ; operands[0].access: READ ; Shift: 2 = 1 ; Registers read: r0 r1 ; Groups: jump IsThumb2 - -!# issue 1308 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL -0x0: 0x83,0x3d,0xa1,0x75,0x21,0x00,0x04 == cmp dword ptr [rip + 0x2175a1], 4 ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x83 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0x3d ; disp: 0x2175a1 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0x4 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.base: REG = rip ; operands[0].mem.disp: 0x2175a1 ; operands[0].size: 4 ; operands[0].access: READ ; operands[1].type: IMM = 0x4 ; operands[1].size: 4 ; Registers read: rip ; Registers modified: rflags ; EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF - -!# issue 1262 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL -0x0: 0x0f,0x95,0x44,0x24,0x5e == setne byte ptr [rsp + 0x5e] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x0f 0x95 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0x44 ; disp: 0x5e ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x5e ; operands[0].size: 1 ; operands[0].access: WRITE ; Registers read: rflags rsp ; EFLAGS: TEST_ZF - -!# issue 1262 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL -0x0: 0x0f,0x94,0x44,0x24,0x1f == sete byte ptr [rsp + 0x1f] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x0f 0x94 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0x44 ; disp: 0x1f ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x1f ; operands[0].size: 1 ; operands[0].access: WRITE ; Registers read: rflags rsp ; EFLAGS: TEST_ZF - -!# issue 1263 -!# CS_ARCH_X86, CS_MODE_64, None -0x0: 0x67,0x48,0x89,0x18 == mov qword ptr [eax], rbx - -!# issue 1263 -!# CS_ARCH_X86, CS_MODE_64, None -0x0: 0x67,0x48,0x8b,0x03 == mov rax, qword ptr [ebx] - -!# issue 1255 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL -0x0: 0xdb,0x7c,0x24,0x40 == fstp xword ptr [rsp + 0x40] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xdb 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0x7c ; disp: 0x40 ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x40 ; operands[0].size: 10 ; operands[0].access: WRITE ; Registers read: rsp ; Registers modified: fpsw ; FPU_FLAGS: MOD_C1 UNDEF_C0 UNDEF_C2 UNDEF_C3 ; Groups: fpu - -!# issue 1255 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL -0x0: 0xdd,0xd9 == fstp st(1) ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xdd 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0xd9 ; disp: 0x0 ; sib: 0x0 ; op_count: 1 ; operands[0].type: REG = st(1) ; operands[0].size: 10 ; operands[0].access: WRITE ; Registers modified: fpsw st(1) ; EFLAGS: MOD_CF PRIOR_SF PRIOR_AF PRIOR_PF - -!# issue 1255 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL -0x0: 0xdf,0x7c,0x24,0x68 == fistp qword ptr [rsp + 0x68] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xdf 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0x7c ; disp: 0x68 ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x68 ; operands[0].size: 8 ; operands[0].access: WRITE ; Registers read: rsp ; Registers modified: fpsw ; FPU_FLAGS: RESET_C1 UNDEF_C0 UNDEF_C2 UNDEF_C3 ; Groups: fpu - -!# issue 1221 -!# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None -0x0: 0x55,0x48,0x89,0xe5 == call 0x55222794 - -!# issue 1144 -!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, None -0x0: 0x00,0x00,0x02,0xb6 == tbz x0, #0x20, 0x4000 - -!# issue 1144 -!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, None -0x0: 0x00,0x00,0x04,0xb6 == tbz x0, #0x20, 0xffffffffffff8000 - -!# issue 1144 -!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, None -0x0: 0x00,0x00,0x02,0xb7 == tbnz x0, #0x20, 0x4000 - -!# issue 1144 -!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, None -0x0: 0x00,0x00,0x04,0xb7 == tbnz x0, #0x20, 0xffffffffffff8000 - -!# issue 826 -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x0: 0x0b,0x00,0x00,0x0a == beq 0x34 ; op_count: 1 ; operands[0].type: IMM = 0x34 ; Code condition: 0 ; Registers read: cpsr ; Groups: jump branch_relative IsARM - -!# issue 1047 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT -0x0: 0x48,0x83,0xe4,0xf0 == andq $0xfffffffffffffff0, %rsp - -!# issue 959 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0xa0,0x28,0x57,0x88,0x7c == mov al, byte ptr [0x7c885728] - -!# issue 950 -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL -0x0: 0x66,0xa3,0x94,0x90,0x04,0x08 == mov word ptr [0x8049094], ax ; Prefix:0x00 0x00 0x66 0x00 ; Opcode:0xa3 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x8049094 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.disp: 0x8049094 ; operands[0].size: 2 ; operands[0].access: WRITE ; operands[1].type: REG = ax ; operands[1].size: 2 ; operands[1].access: READ ; Registers read: ax - -!# issue 938 -!# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN, None -0x0: 0x70,0x00,0xb2,0xff == sd $s2, 0x70($sp) - -!# issue 915 -!# CS_ARCH_X86, CS_MODE_64, None -0x0: 0xf0,0x0f,0x1f,0x00 == lock nop dword ptr [rax] - -// !# issue 913 -// !# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x0: 0x04,0x10,0x9d,0xe4 == pop {r1} ; op_count: 1 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; Write-back: True ; Registers read: sp ; Registers modified: sp r1 ; Groups: arm - -!# issue 884 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT -0x0: 0x64,0x48,0x03,0x04,0x25,0x00,0x00,0x00,0x00 == addq %fs:0, %rax - -!# issue 872 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0xf2,0xeb,0x3e == bnd jmp 0x41 - -!# issue 861 -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x0: 0x01,0x81,0xa0,0xfc == stc2 p1, c8, [r0], #4 ; op_count: 3 ; operands[0].type: P-IMM = 1 ; operands[0].access: READ ; operands[1].type: C-IMM = 8 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = r0 ; operands[2].mem.disp: 0x4 ; operands[2].access: WRITE ; Registers read: r0 ; Groups: IsARM PreV8 - -!# issue 852 -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL -0x0: 0x64,0xa3,0x00,0x00,0x00,0x00 == mov dword ptr fs:[0], eax ; Prefix:0x00 0x64 0x00 0x00 ; Opcode:0xa3 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.segment: REG = fs ; operands[0].size: 4 ; operands[0].access: WRITE ; operands[1].type: REG = eax ; operands[1].size: 4 ; operands[1].access: READ ; Registers read: fs eax - -!# issue 825 -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x0: 0x0e,0xf0,0xa0,0xe1 == mov pc, lr ; op_count: 2 ; operands[0].type: REG = r15 ; operands[0].access: WRITE ; operands[1].type: REG = r14 ; operands[1].access: READ ; Registers read: r14 ; Registers modified: r15 ; Groups: jump return IsARM - -!# issue 813 -!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_BIG_ENDIAN, None -0x0: 0xF6,0xC0,0x04,0x01 == movt r4, #0x801 - -!# issue 809 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL -0x0: 0x0f,0x29,0x8d,0xf0,0xfd,0xff,0xff == movaps xmmword ptr [rbp - 0x210], xmm1 ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x0f 0x29 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0x8d ; disp: 0xfffffffffffffdf0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.base: REG = rbp ; operands[0].mem.disp: 0xfffffffffffffdf0 ; operands[0].size: 16 ; operands[0].access: WRITE ; operands[1].type: REG = xmm1 ; operands[1].size: 16 ; operands[1].access: READ ; Registers read: rbp xmm1 ; Groups: sse1 - -!# issue 807 -!# CS_ARCH_X86, CS_MODE_64, None -0x0: 0x4c,0x0f,0x00,0x80,0x16,0x76,0x8a,0xfe == sldt word ptr [rax - 0x17589ea] - -!# issue 806 -!# CS_ARCH_X86, CS_MODE_64, None -0x0: 0x0f,0x35 == sysexit - -!# issue 805 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT -0x0: 0x48,0x4c,0x0f,0xb5,0x80,0x16,0x76,0x8a,0xfe == lgs -0x17589ea(%rax), %r8 - -!# issue 804 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT -0x0: 0x66,0x48,0xf3,0xd1,0xc0 == rolw $1, %ax - -!# issue 789 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT -0x0: 0x8e,0x1e == movw (%rsi), %ds - -!# issue 767 -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0x0: 0xb1,0xe8,0xfc,0x07 == ldm.w r1!, {r2, r3, r4, r5, r6, r7, r8, r9, r10} ; ldm.w r1!, {r2, r3, r4, r5, r6, r7, r8, r9, r10} ; op_count: 10 ; operands[0].type: REG = r1 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r2 ; operands[1].access: WRITE ; operands[2].type: REG = r3 ; operands[2].access: WRITE ; operands[3].type: REG = r4 ; operands[3].access: WRITE ; operands[4].type: REG = r5 ; operands[4].access: WRITE ; operands[5].type: REG = r6 ; operands[5].access: WRITE ; operands[6].type: REG = r7 ; operands[6].access: WRITE ; operands[7].type: REG = r8 ; operands[7].access: WRITE ; operands[8].type: REG = r9 ; operands[8].access: WRITE ; operands[9].type: REG = r10 ; operands[9].access: WRITE ; Write-back: True ; Registers read: r1 ; Registers modified: r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 ; Groups: IsThumb2 - -!# issue 760 -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x0: 0x02,0x80,0xbd,0xe8 == pop {r1, pc} ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: REG = r15 ; operands[1].access: WRITE ; Write-back: True ; Registers read: r13 ; Registers modified: r13 r1 r15 ; Groups: IsARM return jump - -!# issue 750 -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x0: 0x0e,0x00,0x20,0xe9 == stmdb r0!, {r1, r2, r3} ; op_count: 4 ; operands[0].type: REG = r0 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r1 ; operands[1].access: READ ; operands[2].type: REG = r2 ; operands[2].access: READ ; operands[3].type: REG = r3 ; operands[3].access: READ ; Write-back: True ; Registers read: r0 r1 r2 r3 ; Registers modified: r0 ; Groups: IsARM - -!# issue 747 -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x0: 0x0e,0x00,0xb0,0xe8 == ldm r0!, {r1, r2, r3} ; op_count: 4 ; operands[0].type: REG = r0 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r1 ; operands[1].access: WRITE ; operands[2].type: REG = r2 ; operands[2].access: WRITE ; operands[3].type: REG = r3 ; operands[3].access: WRITE ; Write-back: True ; Registers read: r0 ; Registers modified: r0 r1 r2 r3 ; Groups: IsARM - -!# issue 747 -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0x0: 0x0e,0xc8 == ldm r0!, {r1, r2, r3} ; op_count: 4 ; operands[0].type: REG = r0 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r1 ; operands[1].access: WRITE ; operands[2].type: REG = r2 ; operands[2].access: WRITE ; operands[3].type: REG = r3 ; operands[3].access: WRITE ; Write-back: True ; Registers read: r0 ; Registers modified: r0 r1 r2 r3 ; Groups: IsThumb - -!# issue 746 -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x0: 0x89,0x00,0x2d,0xe9 == push {r0, r3, r7} ; op_count: 3 ; operands[0].type: REG = r0 ; operands[0].access: READ ; operands[1].type: REG = r3 ; operands[1].access: READ ; operands[2].type: REG = r7 ; operands[2].access: READ ; Write-back: True ; Registers read: r13 r0 r3 r7 ; Registers modified: r13 ; Groups: IsARM - -!# issue 744 -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x0: 0x02,0x80,0xbd,0xe8 == pop {r1, pc} ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: REG = r15 ; operands[1].access: WRITE ; Write-back: True ; Registers read: r13 ; Registers modified: r13 r1 r15 ; Groups: IsARM return jump - -!# issue 741 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0x83,0xff,0xf7 == cmp edi, -9 - -!# issue 717 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT -0x0: 0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00 == movq 0, %rax - -!# issue 711 -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL -0x0: 0xa3,0x44,0xb0,0x00,0x10 == mov dword ptr [0x1000b044], eax ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xa3 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x1000b044 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.disp: 0x1000b044 ; operands[0].size: 4 ; operands[0].access: WRITE ; operands[1].type: REG = eax ; operands[1].size: 4 ; operands[1].access: READ ; Registers read: eax - -!# issue 613 -!# CS_ARCH_X86, CS_MODE_64, None -0x0: 0xd9,0x74,0x24,0xd8 == fnstenv [rsp - 0x28] - -!# issue 554 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0xe7,0x84 == out 0x84, eax - -!# issue 554 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0xe5,0x8c == in eax, 0x8c - -!# issue 545 -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL -0x0: 0x95 == xchg ebp, eax ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x95 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: REG = ebp ; operands[0].size: 4 ; operands[0].access: READ | WRITE ; operands[1].type: REG = eax ; operands[1].size: 4 ; operands[1].access: READ | WRITE ; Registers read: ebp eax ; Registers modified: ebp eax ; Groups: not64bitmode - -!# issue 544 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0xdf,0x30 == fbstp tbyte ptr [eax] - -!# issue 544 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0xdf,0x20 == fbld tbyte ptr [eax] - -!# issue 541 -!# CS_ARCH_X86, CS_MODE_64, None -0x0: 0x48,0xb8,0x00,0x00,0x00,0x00,0x80,0xf8,0xff,0xff == movabs rax, 0xfffff88000000000 - -!# issue 499 -!# CS_ARCH_X86, CS_MODE_64, None -0x0: 0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80 == movabs rax, 0x8000000000000000 - -!# issue 492 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0xff,0x18 == call ptr [eax] - -!# issue 492 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0xff,0x28 == jmp ptr [eax] - -!# issue 492 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0x0f,0xae,0x04,0x24 == fxsave [esp] - -!# issue 492 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0x0f,0xae,0x0c,0x24 == fxrstor [esp] - -!# issue 470 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0x0f,0x01,0x05,0xa0,0x90,0x04,0x08 == sgdt [0x80490a0] - -!# issue 470 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0x0f,0x01,0x0d,0xa7,0x90,0x04,0x08 == sidt [0x80490a7] - -!# issue 470 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0x0f,0x01,0x15,0xa0,0x90,0x04,0x08 == lgdt [0x80490a0] - -!# issue 470 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0x0f,0x01,0x1d,0xa7,0x90,0x04,0x08 == lidt [0x80490a7] - -!# issue 459 -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x0: 0xd3,0x20,0x11,0xe1 == ldrsb r2, [r1, -r3] ; op_count: 2 ; operands[0].type: REG = r2 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r1 ; operands[1].mem.index: REG = r3 ; operands[1].mem.scale: 0 ; operands[1].access: READ ; Subtracted: True ; Registers read: r1 r3 ; Registers modified: r2 ; Groups: IsARM - -!# issue 456 -!# CS_ARCH_X86, CS_MODE_16, None -0x0: 0xe8,0x35,0x64 == call 0x6438 - -!# issue 456 -!# CS_ARCH_X86, CS_MODE_16, None -0x0: 0xe9,0x35,0x64 == jmp 0x6438 - -!# issue 456 -!# CS_ARCH_X86, CS_MODE_16, None -0x0: 0x66,0xe9,0x35,0x64,0x93,0x53 == jmp 0x5393643b - -!# issue 456 -!# CS_ARCH_X86, CS_MODE_16, None -0x0: 0x66,0xe8,0x35,0x64,0x93,0x53 == call 0x5393643b - -!# issue 456 -!# CS_ARCH_X86, CS_MODE_16, None -0x0: 0x66,0xe9,0x35,0x64,0x93,0x53 == jmp 0x5393643b - -!# issue 456 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0x66,0xe8,0x35,0x64 == call 0x6439 - -!# issue 456 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0xe9,0x35,0x64,0x93,0x53 == jmp 0x5393643a - -!# issue 456 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0x66,0xe9,0x35,0x64 == jmp 0x6439 - -!# issue 458 -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL -0x0: 0xA1,0x12,0x34,0x90,0x90 == mov eax, dword ptr [0x90903412] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xa1 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x90903412 ; sib: 0x0 ; op_count: 2 ; operands[0].type: REG = eax ; operands[0].size: 4 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.disp: 0x90903412 ; operands[1].size: 4 ; operands[1].access: READ ; Registers modified: eax - -!# issue 454 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0xf2,0x6c == repne insb byte ptr es:[edi], dx - -!# issue 454 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0xf2,0x6d == repne insd dword ptr es:[edi], dx - -!# issue 454 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0xf2,0x6e == repne outsb dx, byte ptr [esi] - -!# issue 454 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0xf2,0x6f == repne outsd dx, dword ptr [esi] - -!# issue 454 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0xf2,0xac == repne lodsb al, byte ptr [esi] - -!# issue 454 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0xf2,0xad == repne lodsd eax, dword ptr [esi] - -!# issue 450 -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL -0x0: 0xff,0x2d,0x34,0x35,0x23,0x01 == jmp ptr [0x1233534] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xff 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x2d ; disp: 0x1233534 ; sib: 0x0 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.disp: 0x1233534 ; operands[0].size: 6 ; Groups: jump - -!# issue 448 -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL -0x0: 0xea,0x12,0x34,0x56,0x78,0x9a,0xbc == ljmp 0xbc9a:0x78563412 ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xea 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 2 ; imms[1]: 0xbc9a ; imms[2]: 0x78563412 ; op_count: 2 ; operands[0].type: IMM = 0xbc9a ; operands[0].size: 2 ; operands[1].type: IMM = 0x78563412 ; operands[1].size: 4 ; Groups: not64bitmode jump - -!# issue 426 -!# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None -0x0: 0xbb,0x70,0x00,0x00 == popc %g0, %i5 - -!# issue 358 -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL -0x0: 0xe8,0xe3,0xf6,0xff,0xff == call 0xfffff6e8 ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xe8 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0xfffff6e8 ; op_count: 1 ; operands[0].type: IMM = 0xfffff6e8 ; operands[0].size: 4 ; Registers read: esp eip ; Registers modified: esp ; Groups: call branch_relative not64bitmode - -!# issue 353 -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL -0x0: 0xe6,0xa2 == out 0xa2, al ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xe6 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0xa2 ; op_count: 2 ; operands[0].type: IMM = 0xa2 ; operands[0].size: 1 ; operands[1].type: REG = al ; operands[1].size: 1 ; operands[1].access: READ ; Registers read: al - -!# issue 305 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0x34,0x8b == xor al, 0x8b - -!# issue 298 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0xf3,0x90 == pause - -!# issue 298 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0x66,0xf3,0xf2,0x0f,0x59,0xff == mulsd xmm7, xmm7 - -// !# issue 298 -// !# CS_ARCH_X86, CS_MODE_32, None -// 0x0: 0xf2,0x66,0x0f,0x59,0xff == mulpd xmm7, xmm7 - -!# issue 294 -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL -0x0: 0xc1,0xe6,0x08 == shl esi, 8 ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xc1 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0xe6 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0x8 ; op_count: 2 ; operands[0].type: REG = esi ; operands[0].size: 4 ; operands[0].access: READ | WRITE ; operands[1].type: IMM = 0x8 ; operands[1].size: 1 ; Registers read: esi ; Registers modified: eflags esi ; EFLAGS: MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF UNDEF_AF - -!# issue 285 -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL -0x0: 0x3c,0x12,0x80 == cmp al, 0x12 ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x3c 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0x12 ; op_count: 2 ; operands[0].type: REG = al ; operands[0].size: 1 ; operands[0].access: READ ; operands[1].type: IMM = 0x12 ; operands[1].size: 1 ; Registers read: al ; Registers modified: eflags ; EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF - -!# issue 265 -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0x0: 0x52,0xf8,0x23,0x30 == dr.w r3, [r2, r3, lsl #2] ; op_count: 2 ; operands[0].type: REG = r3 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r2 ; operands[1].mem.index: REG = r3 ; operands[1].mem.scale: 0 ; Shift: 2 = 2 ; Registers read: r2 r3 ; Registers modified: r3 ; Groups: IsThumb2 - -!# issue 264 -!# CS_ARCH_ARM, CS_MODE_THUMB, None -0x0: 0x0c,0xbf == ite eq - -!# issue 264 -!# CS_ARCH_ARM, CS_MODE_THUMB, None -0x0: 0x17,0x20 == movs r0, #0x17 - -!# issue 264 -!# CS_ARCH_ARM, CS_MODE_THUMB, None -0x0: 0x4f,0xf0,0xff,0x30 == mov.w r0, #0xffffffff - -!# issue 246 -!# CS_ARCH_ARM, CS_MODE_THUMB, None -0x0: 0x52,0xf8,0x23,0xf0 == ldr.w pc, [r2, r3, lsl #2] - -!# issue 232 -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL -0x0: 0x8e,0x10 == mov ss, word ptr [eax] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x8e 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x10 ; disp: 0x0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: REG = ss ; operands[0].size: 2 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = eax ; operands[1].size: 2 ; operands[1].access: READ ; Registers read: eax ; Registers modified: ss ; Groups: privilege - -!# issue 231 -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL -0x0: 0x66,0x6b,0xc0,0x02 == imul ax, ax, 2 ; Prefix:0x00 0x00 0x66 0x00 ; Opcode:0x6b 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0xc0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0x2 ; op_count: 3 ; operands[0].type: REG = ax ; operands[0].size: 2 ; operands[0].access: WRITE ; operands[1].type: REG = ax ; operands[1].size: 2 ; operands[1].access: READ ; operands[2].type: IMM = 0x2 ; operands[2].size: 2 ; Registers read: ax ; Registers modified: eflags ax ; EFLAGS: MOD_CF MOD_SF MOD_OF UNDEF_ZF UNDEF_PF UNDEF_AF - -!# issue 230 -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL -0x0: 0xec == in al, dx ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xec 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: REG = al ; operands[0].size: 1 ; operands[0].access: WRITE ; operands[1].type: REG = dx ; operands[1].size: 2 ; operands[1].access: READ ; Registers read: dx ; Registers modified: al - -!# issue 213 -!# CS_ARCH_X86, CS_MODE_16, None -0x0: 0xea,0xaa,0xff,0x00,0xf0 == ljmp 0xf000:0xffaa - -!# issue 191 -!# CS_ARCH_X86, CS_MODE_64, None -0x0: 0xc5,0xe8,0xc2,0x33,0x9b == vcmpps xmm6, xmm2, xmmword ptr [rbx], 0x9b - -!# issue 176 -!# CS_ARCH_ARM, CS_MODE_ARM, None -0x0: 0xfd,0xff,0xff,0x1a == bne 0xfffffffc - -!# issue 151 -!# CS_ARCH_X86, CS_MODE_64, None -0x0: 0x4d,0x8d,0x3d,0x02,0x00,0x00,0x00 == lea r15, [rip + 2] - -!# issue 151 -!# CS_ARCH_X86, CS_MODE_64, None -0x0: 0xeb,0xb0 == jmp 0xffffffffffffffb2 - -!# issue 134 -!# CS_ARCH_ARM, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL -0x0: 0xe7,0x92,0x11,0x80 == ldr r1, [r2, r0, lsl #3] ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r2 ; operands[1].mem.index: REG = r0 ; operands[1].access: READ ; Shift: 2 = 3 ; Registers read: r2 r0 ; Registers modified: r1 ; Groups: IsARM - -!# issue 133 -!# CS_ARCH_ARM, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL -0x0: 0xed,0xdf,0x2b,0x1b == vldr d18, [pc, #0x6c] ; op_count: 2 ; operands[0].type: REG = d18 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r15 ; operands[1].mem.disp: 0x6c ; operands[1].access: READ ; Registers read: r15 ; Registers modified: d18 ; Groups: HasFPRegs - -!# issue 132 -!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL -0x0: 0x49,0x19 == ldr r1, [pc, #0x64] ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r15 ; operands[1].mem.disp: 0x64 ; operands[1].access: READ ; Registers read: r15 ; Registers modified: r1 ; Groups: IsThumb - -!# issue 130 -!# CS_ARCH_ARM, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL -0x0: 0xe1,0xa0,0xf0,0x0e == mov pc, lr ; op_count: 2 ; operands[0].type: REG = r15 ; operands[0].access: WRITE ; operands[1].type: REG = r14 ; operands[1].access: READ ; Registers read: r14 ; Registers modified: r15 ; Groups: jump return IsARM - -!# issue 85 -!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, None -0x0: 0xee,0x3f,0xbf,0x29 == stp w14, w15, [sp, #-8]! - -!# issue 82 -!# CS_ARCH_X86, CS_MODE_64, None -0x0: 0xf2,0x66,0xaf == repne scasw ax, word ptr [rdi] - -!# issue 35 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0xe8,0xc6,0x02,0x00,0x00 == call 0x2cb - -!# issue 8 -!# CS_ARCH_X86, CS_MODE_32, None -0x0: 0xff,0x8c,0xf9,0xff,0xff,0x9b,0xf9 == dec dword ptr [ecx + edi*8 - 0x6640001] - -!# issue 29 -!# CS_ARCH_AARCH64, CS_MODE_ARM, None -0x0: 0x00,0x00,0x00,0x4c == st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] - -!# issue 2233 ARM write to PC is branch -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0x87,0x46 == mov pc, r0 ; Groups: IsThumb jump - -!# issue 2128 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL -0x0: 0x4c,0x85,0x7d,0x30 == test qword ptr [rbp + 0x30], r15 ; operands[1].type: REG = r15 ; operands[1].access: READ ; Registers read: rbp r15 ; Registers modified: rflags - -!# issue 2079 -!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL -0x0: 0xd1,0x10 == rcl dword ptr [eax] ; operands[1].type: IMM = 0x1 - -!# issue 2244 -!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL -0x0: 0xc5,0xfb,0xc2,0xda,0x06 == vcmpnlesd xmm3, xmm0, xmm2 ; ID: 797 - -!# issue 2349 -!# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, CS_OPT_DETAIL -0x0: 0xcf, 0x41, 0xd0, 0x28 == ld.d $t3, $t2, 0x410 ; operands[1].type: MEM ; operands[1].mem.base: REG = t2 ; operands[1].mem.disp: 0x410 - -!# issue 2349 -!# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, CS_OPT_DETAIL -0x0: 0x8d, 0x59, 0x10, 0x27 == stptr.d $t1, $t0, 0x1058 ; operands[1].type: MEM ; operands[1].mem.base: REG = t0 ; operands[1].mem.disp: 0x1058 - -!# issue 2349 -!# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, CS_OPT_DETAIL -0x0: 0xa4, 0x15, 0x20, 0x30 == vldrepl.w $vr4, $t1, 0x14 ; operands[1].type: MEM ; operands[1].mem.base: REG = t1 ; operands[1].mem.disp: 0x14 - -!# issue 2349 -!# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, CS_OPT_DETAIL -0x0: 0x68, 0x22, 0xc2, 0x2a == preld 8, $t7, 0x88 ; operands[1].type: MEM ; operands[1].mem.base: REG = t7 ; operands[1].mem.disp: 0x88 - -!# issue 2349 -!# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, CS_OPT_DETAIL -0x0: 0xe1, 0x2c, 0x30, 0x38 == fldx.s $fa1, $a3, $a7 ; operands[1].type: MEM ; operands[1].mem.base: REG = a3 ; operands[1].mem.index: REG = a7 - -!# issue 2349 -!# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, CS_OPT_DETAIL -0x0: 0xc4, 0x14, 0x57, 0x38 == sc.q $a0, $a1, $a2 ; operands[2].type: MEM ; operands[2].mem.base: REG = a2 - -!# issue 2349 -!# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, CS_OPT_DETAIL -0x0: 0xc4, 0x14, 0x61, 0x38 == amadd.w $a0, $a1, $a2 ; operands[2].type: MEM ; operands[2].mem.base: REG = a2 - -!# issue 2349 -!# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, CS_OPT_DETAIL -0x0: 0xa4, 0x18, 0x78, 0x38 == ldgt.b $a0, $a1, $a2 ; operands[1].type: MEM ; operands[1].mem.base: REG = a1 ; operands[2].type: REG = a2 - -!# issue 2268 -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x0: 0x00,0x80,0x58,0x65 == fadd z0.h, p0/m, z0.h, #0.5 ; operands[3].subtype EXACTFPIMM = 1 - -!# issue 2268 -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x0: 0x20,0x80,0x58,0x65 == fadd z0.h, p0/m, z0.h, #1.0 ; operands[3].subtype EXACTFPIMM = 2 - -!# issue 2268 -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x0: 0x3f,0x9c,0xda,0x65 == fmul z31.d, p7/m, z31.d, #2.0 ; operands[3].subtype EXACTFPIMM = 3 - -!# issue 2268 -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x0: 0x6a,0xd9,0xf8,0x7e == fcmle h10, h11, #0.0 ; operands[2].subtype EXACTFPIMM = 0 - -!# issue 2419 -!# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL -0x0: 0x12,0xbf,0xff,0xff == bne -4 ; Code condition: 265 diff --git a/suite/cstest/src/aarch64_detail.c b/suite/cstest/src/aarch64_detail.c deleted file mode 100644 index e6cafa1430..0000000000 --- a/suite/cstest/src/aarch64_detail.c +++ /dev/null @@ -1,245 +0,0 @@ -/* Capstone testing regression */ -/* By Do Minh Tuan , 02-2019 */ - - -#include "factory.h" - -char *get_detail_aarch64(csh *handle, cs_mode mode, cs_insn *ins) -{ - cs_aarch64 *aarch64; - int i; - cs_regs regs_read, regs_write; - uint8_t regs_read_count, regs_write_count; - uint8_t access; - char *result; - - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; - - // detail can be NULL if SKIPDATA option is turned ON - if (ins->detail == NULL) - return result; - - aarch64 = &(ins->detail->aarch64); - if (aarch64->op_count) - add_str(&result, " ; op_count: %u", aarch64->op_count); - - for (i = 0; i < aarch64->op_count; i++) { - cs_aarch64_op *op = &(aarch64->operands[i]); - switch(op->type) { - default: - break; - case AARCH64_OP_REG: - add_str(&result, " ; operands[%u].type: REG = %s%s", i, cs_reg_name(*handle, op->reg), op->is_vreg ? " (vreg)" : ""); - if (op->is_list_member) { - add_str(&result, " ; operands[%u].is_list_member: true", i); - } - break; - case AARCH64_OP_IMM: - add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64, i, op->imm); - break; - case AARCH64_OP_FP: -#if defined(_KERNEL_MODE) - // Issue #681: Windows kernel does not support formatting float point - add_str(&result, " ; operands[%u].type: FP = ", i); -#else - add_str(&result, " ; operands[%u].type: FP = %f", i, op->fp); -#endif - break; - case AARCH64_OP_MEM: - add_str(&result, " ; operands[%u].type: MEM", i); - if (op->mem.base != AARCH64_REG_INVALID) - add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); - if (op->mem.index != AARCH64_REG_INVALID) - add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index)); - if (op->mem.disp != 0) - add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); - - break; - case AARCH64_OP_CIMM: - add_str(&result, " ; operands[%u].type: C-IMM = %u", i, (int)op->imm); - break; - case AARCH64_OP_REG_MRS: - add_str(&result, " ; operands[%u].type: REG_MRS = 0x%x", i, op->reg); - break; - case AARCH64_OP_REG_MSR: - add_str(&result, " ; operands[%u].type: REG_MSR = 0x%x", i, op->reg); - break; - case AARCH64_OP_SME: - add_str(&result, " ; operands[%u].type: SME_MATRIX", i); - add_str(&result, " ; operands[%u].sme.type: %d", i, op->sme.type); - - if (op->sme.tile != AARCH64_REG_INVALID) - add_str(&result, " ; operands[%u].sme.tile: %s", i, cs_reg_name(*handle, op->sme.tile)); - if (op->sme.slice_reg != AARCH64_REG_INVALID) - add_str(&result, " ; operands[%u].sme.slice_reg: %s", i, cs_reg_name(*handle, op->sme.slice_reg)); - if (op->sme.slice_offset.imm != -1 || op->sme.slice_offset.imm_range.first != -1) { - add_str(&result, " ; operands[%u].sme.slice_offset: ", i); - if (op->sme.has_range_offset) - add_str(&result, "%hhd:%hhd", op->sme.slice_offset.imm_range.first, op->sme.slice_offset.imm_range.offset); - else - add_str(&result, "%d", op->sme.slice_offset.imm); - } - if (op->sme.slice_reg != AARCH64_REG_INVALID || op->sme.slice_offset.imm != -1) - add_str(&result, " ; operands[%u].sme.is_vertical: %s", i, (op->sme.is_vertical ? "true" : "false")); - break; - case AARCH64_OP_PRED: - add_str(&result, " ; operands[%u].type: PREDICATE", i); - if (op->pred.reg != AARCH64_REG_INVALID) - add_str(&result, " ; operands[%u].pred.reg: %s", i, cs_reg_name(*handle, op->pred.reg)); - if (op->pred.vec_select != AARCH64_REG_INVALID) - add_str(&result, " ; operands[%u].pred.vec_select: %s", i, cs_reg_name(*handle, op->pred.vec_select)); - if (op->pred.imm_index != -1) - add_str(&result, " ; operands[%u].pred.imm_index: %d", i, op->pred.imm_index); - break; - case AARCH64_OP_SYSREG: - add_str(&result, " ; operands[%u].type: SYS REG:", i); - switch (op->sysop.sub_type) { - default: - break; - case AARCH64_OP_REG_MRS: - add_str(&result, " ; operands[%u].subtype: REG_MRS = 0x%x", i, op->sysop.reg.sysreg); - break; - case AARCH64_OP_REG_MSR: - add_str(&result, " ; operands[%u].subtype: REG_MSR = 0x%x", i, op->sysop.reg.sysreg); - break; - case AARCH64_OP_TLBI: - add_str(&result, " ; operands[%u].subtype TLBI = 0x%x", i, op->sysop.reg.tlbi); - break; - case AARCH64_OP_IC: - add_str(&result, " ; operands[%u].subtype IC = 0x%x", i, op->sysop.reg.ic); - break; - } - break; - case AARCH64_OP_SYSALIAS: - add_str(&result, " ; operands[%u].type: SYS ALIAS:", i); - switch (op->sysop.sub_type) { - default: - break; - case AARCH64_OP_SVCR: - if(op->sysop.alias.svcr == AARCH64_SVCR_SVCRSM) - add_str(&result, " ; operands[%u].svcr: BIT = SM", i); - else if(op->sysop.alias.svcr == AARCH64_SVCR_SVCRZA) - add_str(&result, " ; operands[%u].svcr: BIT = ZA", i); - else if(op->sysop.alias.svcr == AARCH64_SVCR_SVCRSMZA) - add_str(&result, " ; operands[%u].svcr: BIT = SM & ZA", i); - break; - case AARCH64_OP_AT: - add_str(&result, " ; operands[%u].subtype AT = 0x%x", i, op->sysop.alias.at); - break; - case AARCH64_OP_DB: - add_str(&result, " ; operands[%u].subtype DB = 0x%x", i, op->sysop.alias.db); - break; - case AARCH64_OP_DC: - add_str(&result, " ; operands[%u].subtype DC = 0x%x", i, op->sysop.alias.dc); - break; - case AARCH64_OP_ISB: - add_str(&result, " ; operands[%u].subtype ISB = 0x%x", i, op->sysop.alias.isb); - break; - case AARCH64_OP_TSB: - add_str(&result, " ; operands[%u].subtype TSB = 0x%x", i, op->sysop.alias.tsb); - break; - case AARCH64_OP_PRFM: - add_str(&result, " ; operands[%u].subtype PRFM = 0x%x", i, op->sysop.alias.prfm); - break; - case AARCH64_OP_SVEPRFM: - add_str(&result, " ; operands[%u].subtype SVEPRFM = 0x%x", i, op->sysop.alias.sveprfm); - break; - case AARCH64_OP_RPRFM: - add_str(&result, " ; operands[%u].subtype RPRFM = 0x%x", i, op->sysop.alias.rprfm); - break; - case AARCH64_OP_PSTATEIMM0_15: - add_str(&result, " ; operands[%u].subtype PSTATEIMM0_15 = 0x%x", i, op->sysop.alias.pstateimm0_15); - break; - case AARCH64_OP_PSTATEIMM0_1: - add_str(&result, " ; operands[%u].subtype PSTATEIMM0_1 = 0x%x", i, op->sysop.alias.pstateimm0_1); - break; - case AARCH64_OP_PSB: - add_str(&result, " ; operands[%u].subtype PSB = 0x%x", i, op->sysop.alias.psb); - break; - case AARCH64_OP_BTI: - add_str(&result, " ; operands[%u].subtype BTI = 0x%x", i, op->sysop.alias.bti); - break; - case AARCH64_OP_SVEPREDPAT: - add_str(&result, " ; operands[%u].subtype SVEPREDPAT = 0x%x", i, op->sysop.alias.svepredpat); - break; - case AARCH64_OP_SVEVECLENSPECIFIER: - add_str(&result, " ; operands[%u].subtype SVEVECLENSPECIFIER = 0x%x", i, op->sysop.alias.sveveclenspecifier); - break; - } - break; - case AARCH64_OP_SYSIMM: - add_str(&result, " ; operands[%u].type: SYS IMM:", i); - switch(op->sysop.sub_type) { - default: - break; - case AARCH64_OP_EXACTFPIMM: - add_str(&result, " ; operands[%u].subtype EXACTFPIMM = %d", i, op->sysop.imm.exactfpimm); - break; - case AARCH64_OP_DBNXS: - add_str(&result, " ; operands[%u].subtype DBNXS = %d", i, op->sysop.imm.dbnxs); - break; - } - break; - } - - access = op->access; - switch(access) { - default: - break; - case CS_AC_READ: - add_str(&result, " ; operands[%u].access: READ", i); - break; - case CS_AC_WRITE: - add_str(&result, " ; operands[%u].access: WRITE", i); - break; - case CS_AC_READ | CS_AC_WRITE: - add_str(&result, " ; operands[%u].access: READ | WRITE", i); - break; - } - - if (op->shift.type != AARCH64_SFT_INVALID && - op->shift.value) - add_str(&result, " ; Shift: type = %u, value = %u", - op->shift.type, op->shift.value); - - if (op->ext != AARCH64_EXT_INVALID) - add_str(&result, " ; Ext: %u", op->ext); - - if (op->vas != AARCH64LAYOUT_INVALID) - add_str(&result, " ; operands[%u].vas: 0x%x", i, op->vas); - - if (op->vector_index != -1) - add_str(&result, " ; operands[%u].vector_index: %u", i, op->vector_index); - } - - if (aarch64->update_flags) - add_str(&result, " ; Update-flags: True"); - - if (ins->detail->writeback) - add_str(&result, " ; Write-back: True"); - - if (aarch64->cc) - add_str(&result, " ; Code-condition: %u", aarch64->cc); - - // Print out all registers accessed by this instruction (either implicit or explicit) - if (!cs_regs_access(*handle, ins, - regs_read, ®s_read_count, - regs_write, ®s_write_count)) { - if (regs_read_count) { - add_str(&result, " ; Registers read:"); - for(i = 0; i < regs_read_count; i++) { - add_str(&result, " %s", cs_reg_name(*handle, regs_read[i])); - } - } - - if (regs_write_count) { - add_str(&result, " ; Registers modified:"); - for(i = 0; i < regs_write_count; i++) { - add_str(&result, " %s", cs_reg_name(*handle, regs_write[i])); - } - } - } - - return result; -} diff --git a/suite/cstest/src/alpha_detail.c b/suite/cstest/src/alpha_detail.c deleted file mode 100644 index 4f41783370..0000000000 --- a/suite/cstest/src/alpha_detail.c +++ /dev/null @@ -1,69 +0,0 @@ -/* Capstone testing regression */ -/* By Dmitry Sibirtsev , 2023 */ - -#include "factory.h" - -char *get_detail_alpha(csh *p_handle, cs_mode mode, cs_insn *ins) -{ - cs_alpha *alpha; - int i; - cs_regs regs_read, regs_write; - uint8_t regs_read_count, regs_write_count; - - char *result; - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; - - if (ins->detail == NULL) - return result; - - csh handle = *p_handle; - - alpha = &(ins->detail->alpha); - - if (alpha->op_count) - add_str(&result, "\top_count: %u\n", alpha->op_count); - - for (i = 0; i < alpha->op_count; i++) { - cs_alpha_op *op = &(alpha->operands[i]); - switch ((int)op->type) { - default: - break; - case ALPHA_OP_REG: - add_str(&result, "\t\toperands[%u].type: REG = %s\n", i, - cs_reg_name(handle, op->reg)); - break; - case ALPHA_OP_IMM: - add_str(&result, "\t\toperands[%u].type: IMM = 0x%x\n", - i, op->imm); - break; - } - - // Print out all registers accessed by this instruction (either implicit or - // explicit) - if (!cs_regs_access(handle, ins, regs_read, ®s_read_count, - regs_write, ®s_write_count)) { - if (regs_read_count) { - add_str(&result, "\tRegisters read:"); - for (i = 0; i < regs_read_count; i++) { - add_str(&result, " %s", - cs_reg_name(handle, - regs_read[i])); - } - add_str(&result, "\n"); - } - - if (regs_write_count) { - add_str(&result, "\tRegisters modified:"); - for (i = 0; i < regs_write_count; i++) { - add_str(&result, " %s", - cs_reg_name(handle, - regs_write[i])); - } - add_str(&result, "\n"); - } - } - } - - return result; -} diff --git a/suite/cstest/src/arm_detail.c b/suite/cstest/src/arm_detail.c deleted file mode 100644 index 42ac67e5eb..0000000000 --- a/suite/cstest/src/arm_detail.c +++ /dev/null @@ -1,185 +0,0 @@ -/* Capstone testing regression */ -/* By Do Minh Tuan , 02-2019 */ - - -#include "factory.h" - -char *get_detail_arm(csh *handle, cs_mode mode, cs_insn *ins) -{ - cs_arm *arm; - int i; - cs_regs regs_read, regs_write; - uint8_t regs_read_count, regs_write_count; - char *result; - - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; - - if (ins->detail == NULL) - return result; - - arm = &(ins->detail->arm); - - if (arm->op_count) - add_str(&result, " ; op_count: %u", arm->op_count); - - for (i = 0; i < arm->op_count; i++) { - cs_arm_op *op = &(arm->operands[i]); - switch((int)op->type) { - default: - break; - case ARM_OP_REG: - add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); - break; - case ARM_OP_IMM: - add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm); - break; - case ARM_OP_FP: -#if defined(_KERNEL_MODE) - // Issue #681: Windows kernel does not support formatting float point - add_str(&result, " ; operands[%u].type: FP = ", i); -#else - add_str(&result, " ; operands[%u].type: FP = %f", i, op->fp); -#endif - break; - case ARM_OP_MEM: - add_str(&result, " ; operands[%u].type: MEM", i); - if (op->mem.base != ARM_REG_INVALID) - add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); - if (op->mem.index != ARM_REG_INVALID) - add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index)); - if (op->mem.scale != 1) - add_str(&result, " ; operands[%u].mem.scale: %d", i, op->mem.scale); - if (op->mem.disp != 0) - add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); - if (op->mem.align != 0) - add_str(&result, " ; operands[%u].mem.align: 0x%x", i, op->mem.align); - if (op->mem.lshift != 0) - add_str(&result, " ; operands[%u].mem.lshift: 0x%x", i, op->mem.lshift); - - break; - case ARM_OP_PIMM: - add_str(&result, " ; operands[%u].type: P-IMM = %u", i, op->imm); - break; - case ARM_OP_CIMM: - add_str(&result, " ; operands[%u].type: C-IMM = %u", i, op->imm); - break; - case ARM_OP_SETEND: - add_str(&result, " ; operands[%u].type: SETEND = %s", i, op->setend == ARM_SETEND_BE? "be" : "le"); - break; - case ARM_OP_SYSM: - add_str(&result, " ; operands[%u].type: SYSM = 0x%" PRIx16 "\n", i, op->sysop.sysm); - add_str(&result, " ; operands[%u].type: MASK = %" PRIu8 "\n", i, op->sysop.msr_mask); - break; - case ARM_OP_SYSREG: - add_str(&result, " ; operands[%u].type: SYSREG = %s", i, cs_reg_name(*handle, (uint32_t) op->sysop.reg.mclasssysreg)); - add_str(&result, " ; operands[%u].type: MASK = %" PRIu8, i, op->sysop.msr_mask); - break; - case ARM_OP_BANKEDREG: - // FIXME: Printing the name is currenliy not supported if the encodings overlap - // with system registers. - add_str(&result, " ; operands[%u].type: BANKEDREG = %" PRIu32, i, (uint32_t) op->sysop.reg.bankedreg); - if (op->sysop.msr_mask != UINT8_MAX) - add_str(&result, " ; operands[%u].type: MASK = %" PRIu8, i, op->sysop.msr_mask); - case ARM_OP_SPSR: - case ARM_OP_CPSR: { - const char type = op->type == ARM_OP_SPSR ? 'S' : 'C'; - add_str(&result, " ; operands[%u].type: %cPSR = ", i, type); - uint16_t field = op->sysop.psr_bits; - if ((field & ARM_FIELD_SPSR_F) || (field & ARM_FIELD_CPSR_F)) - add_str(&result, "f"); - if ((field & ARM_FIELD_SPSR_S) || (field & ARM_FIELD_CPSR_S)) - add_str(&result, "s"); - if ((field & ARM_FIELD_SPSR_X) || (field & ARM_FIELD_CPSR_X)) - add_str(&result, "x"); - if ((field & ARM_FIELD_SPSR_C) || (field & ARM_FIELD_CPSR_C)) - add_str(&result, "c"); - add_str(&result, " ; operands[%u].type: MASK = %" PRIu8, i, op->sysop.msr_mask); - break; - } - } - - if (op->neon_lane != -1) { - add_str(&result, " ; operands[%u].neon_lane = %u", i, op->neon_lane); - } - - switch(op->access) { - default: - break; - case CS_AC_READ: - add_str(&result, " ; operands[%u].access: READ", i); - break; - case CS_AC_WRITE: - add_str(&result, " ; operands[%u].access: WRITE", i); - break; - case CS_AC_READ | CS_AC_WRITE: - add_str(&result, " ; operands[%u].access: READ | WRITE", i); - break; - } - - if (op->shift.type != ARM_SFT_INVALID && op->shift.value) { - if (op->shift.type < ARM_SFT_ASR_REG) - add_str(&result, " ; Shift: %u = %u", op->shift.type, op->shift.value); - else - add_str(&result, " ; Shift: %u = %s", op->shift.type, cs_reg_name(*handle, op->shift.value)); - } - - if (op->vector_index != -1) { - add_str(&result, " ; operands[%u].vector_index = %u", i, op->vector_index); - } - - if (op->subtracted) - add_str(&result, " ; Subtracted: True"); - } - - if (arm->cc != ARMCC_AL && arm->cc != ARMCC_UNDEF) - add_str(&result, " ; Code condition: %u", arm->cc); - - if (arm->pred_mask) - add_str(&result, " ; Predicate Mask: 0x%x", arm->pred_mask); - - if (arm->vcc != ARMVCC_None) - add_str(&result, " ; Vector code condition: %u", arm->vcc); - - if (arm->update_flags) - add_str(&result, " ; Update-flags: True"); - - if (ins->detail->writeback) - add_str(&result, " ; Write-back: True"); - - if (arm->cps_mode) - add_str(&result, " ; CPSI-mode: %u", arm->cps_mode); - - if (arm->cps_flag) - add_str(&result, " ; CPSI-flag: %u", arm->cps_flag); - - if (arm->vector_data) - add_str(&result, " ; Vector-data: %u", arm->vector_data); - - if (arm->vector_size) - add_str(&result, " ; Vector-size: %u", arm->vector_size); - - if (arm->usermode) - add_str(&result, " ; User-mode: True"); - - if (arm->mem_barrier) - add_str(&result, " ; Memory-barrier: %u", arm->mem_barrier); - - if (!cs_regs_access(*handle, ins, regs_read, ®s_read_count, regs_write, ®s_write_count)) { - if (regs_read_count) { - add_str(&result, " ; Registers read:"); - for(i = 0; i < regs_read_count; i++) { - add_str(&result, " %s", cs_reg_name(*handle, regs_read[i])); - } - } - - if (regs_write_count) { - add_str(&result, " ; Registers modified:"); - for(i = 0; i < regs_write_count; i++) { - add_str(&result, " %s", cs_reg_name(*handle, regs_write[i])); - } - } - } - - return result; -} diff --git a/suite/cstest/src/bpf_detail.c b/suite/cstest/src/bpf_detail.c deleted file mode 100644 index d72332f79a..0000000000 --- a/suite/cstest/src/bpf_detail.c +++ /dev/null @@ -1,77 +0,0 @@ -/* Capstone testing regression */ -/* By david942j , 2019 */ - -#include - -#include "factory.h" - -static char * ext_name[] = { - [BPF_EXT_LEN] = "#len", -}; - -char *get_detail_bpf(csh *handle, cs_mode mode, cs_insn *ins) -{ - cs_bpf *bpf; - unsigned int i; - cs_regs regs_read, regs_write; - uint8_t regs_read_count, regs_write_count; - char *result; - - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; - if (ins->detail == NULL) - return result; - - bpf = &(ins->detail->bpf); - - if (bpf->op_count) - add_str(&result, " ; op_count: %u", bpf->op_count); - for (i = 0; i < bpf->op_count; i++) { - cs_bpf_op *op = &(bpf->operands[i]); - add_str(&result, " ; operands[%u].type: ", i); - switch (op->type) { - case BPF_OP_INVALID: - add_str(&result, "INVALID"); - break; - case BPF_OP_REG: - add_str(&result, "REG = %s", cs_reg_name(*handle, op->reg)); - break; - case BPF_OP_IMM: - add_str(&result, "IMM = 0x%" PRIx64, op->imm); - break; - case BPF_OP_OFF: - add_str(&result, "OFF = +0x%x", op->off); - break; - case BPF_OP_MEM: - add_str(&result, "MEM [base=%s, disp=0x%x]", - cs_reg_name(*handle, op->mem.base), op->mem.disp); - break; - case BPF_OP_MMEM: - add_str(&result, "MMEM = M[0x%x]", op->mmem); - break; - case BPF_OP_MSH: - add_str(&result, "MSH = 4*([0x%x]&0xf)", op->msh); - break; - case BPF_OP_EXT: - add_str(&result, "EXT = %s", ext_name[op->ext]); - break; - } - } - - if (!cs_regs_access(*handle, ins, - regs_read, ®s_read_count, - regs_write, ®s_write_count)) { - if (regs_read_count) { - add_str(&result, " ; Registers read:"); - for(i = 0; i < regs_read_count; i++) - add_str(&result, " %s", cs_reg_name(*handle, regs_read[i])); - } - - if (regs_write_count) { - add_str(&result, " ; Registers modified:"); - for(i = 0; i < regs_write_count; i++) - add_str(&result, " %s", cs_reg_name(*handle, regs_write[i])); - } - } - return result; -} diff --git a/suite/cstest/src/capstone_test.c b/suite/cstest/src/capstone_test.c deleted file mode 100644 index 3cf3c0f88d..0000000000 --- a/suite/cstest/src/capstone_test.c +++ /dev/null @@ -1,307 +0,0 @@ -/* Capstone testing regression */ -/* By Do Minh Tuan , 02-2019 */ - - -#include "../../../cs_priv.h" -#include "capstone_test.h" - -char *(*function)(csh *, cs_mode, cs_insn*) = NULL; - -void test_single_MC(csh *handle, int mc_mode, char *line) -{ - char **list_part, **list_byte; - int size_part, size_byte; - int i, count; - unsigned char *code; - cs_insn *insn; - char tmp[MAXMEM], tmp_mc[MAXMEM], origin[MAXMEM], tmp_noreg[MAXMEM]; - char **offset_opcode; - int size_offset_opcode; - unsigned long offset; - char *p; - - list_part = split(line, " = ", &size_part); - if (size_part <= 1) { - free_strs(list_part, size_part); - return; - } - - offset_opcode = split(list_part[0], ": ", &size_offset_opcode); - if (size_offset_opcode > 1) { - offset = (unsigned int)strtol(offset_opcode[0], NULL, 16); - list_byte = split(offset_opcode[1], ",", &size_byte); - } else { - offset = 0; - list_byte = split(offset_opcode[0], ",", &size_byte); - } - - code = (unsigned char *)malloc(size_byte * sizeof(char)); - for (i = 0; i < size_byte; ++i) { - code[i] = (unsigned char)strtol(list_byte[i], NULL, 16); - } - - ((struct cs_struct *)(uintptr_t)*handle)->PrintBranchImmNotAsAddress = true; - count = cs_disasm(*handle, code, size_byte, offset, 0, &insn); - if (count == 0) { - fprintf(stderr, "[ ERROR ] --- %s --- Failed to disassemble given code!\n", list_part[0]); - free_strs(list_part, size_part); - free_strs(offset_opcode, size_offset_opcode); - free_strs(list_byte, size_byte); - free(code); - _fail(__FILE__, __LINE__); - } - if (count > 1) { - fprintf(stderr, "[ ERROR ] --- %s --- Multiple instructions(%d) disassembling doesn't support!\n", list_part[0], count); - free_strs(list_part, size_part); - free_strs(offset_opcode, size_offset_opcode); - free_strs(list_byte, size_byte); - free(code); - _fail(__FILE__, __LINE__); - } - - for (p = list_part[1]; *p; ++p) *p = tolower(*p); - for (p = list_part[1]; *p; ++p) - if (*p == '\t') *p = ' '; - trim_str(list_part[1]); - strcpy(tmp_mc, list_part[1]); - replace_hex(tmp_mc); - replace_negative(tmp_mc, mc_mode); - replace_tabs(tmp_mc); - - strcpy(tmp, insn[0].mnemonic); - if (strlen(insn[0].op_str) > 0) { - tmp[strlen(insn[0].mnemonic)] = ' '; - strcpy(tmp + strlen(insn[0].mnemonic) + 1, insn[0].op_str); - } - - trim_str(tmp); - strcpy(origin, tmp); - replace_hex(tmp); - replace_negative(tmp, mc_mode); - replace_tabs(tmp); - for (p = tmp; *p; ++p) *p = tolower(*p); - - // Skip ARM because the duplicate disassembly messes with the IT/VPT states - // and laeds to wrong results. - cs_arch arch = ((struct cs_struct *)(uintptr_t)*handle)->arch; - if (arch != CS_ARCH_ARM) { - if (insn->detail) { - free(insn->detail); - } - free(insn); - cs_disasm(*handle, code, size_byte, offset, 0, &insn); - - strcpy(tmp_noreg, insn[0].mnemonic); - if (strlen(insn[0].op_str) > 0) { - tmp_noreg[strlen(insn[0].mnemonic)] = ' '; - strcpy(tmp_noreg + strlen(insn[0].mnemonic) + 1, insn[0].op_str); - } - - trim_str(tmp_noreg); - replace_hex(tmp_noreg); - replace_negative(tmp_noreg, mc_mode); - - if (strcmp(tmp, tmp_mc) && strcmp(tmp_noreg, tmp_mc)) { - fprintf(stderr, "[ ERROR ] --- %s --- \"%s\" != \"%s\" ( \"%s\" != \"%s\" and \"%s\" != \"%s\" )\n", list_part[0], origin, list_part[1], tmp, tmp_mc, tmp_noreg, tmp_mc); - free_strs(list_part, size_part); - free_strs(offset_opcode, size_offset_opcode); - free_strs(list_byte, size_byte); - free(code); - cs_free(insn, count); - _fail(__FILE__, __LINE__); - } - } else if (strcmp(tmp, tmp_mc)) { - fprintf(stderr, "[ ERROR ] --- %s --- \"%s\" != \"%s\" ( \"%s\" != \"%s\" )\n", list_part[0], origin, list_part[1], tmp, tmp_mc); - free_strs(list_part, size_part); - free_strs(offset_opcode, size_offset_opcode); - free_strs(list_byte, size_byte); - free(code); - cs_free(insn, count); - _fail(__FILE__, __LINE__); - } - - free_strs(list_part, size_part); - free_strs(offset_opcode, size_offset_opcode); - free_strs(list_byte, size_byte); - free(code); - cs_free(insn, count); -} - -int get_value(single_dict d[], unsigned int size, const char *str) -{ - int i; - - for (i = 0; i < size; ++i) - if (!strcmp(d[i].str, str)) - return d[i].value; - return -1; -} - -int get_index(double_dict d[], unsigned int size, const char *s) -{ - int i; - - for (i = 0; i < size; ++i) { - if (!strcmp(s, d[i].str)) - return i; - } - return -1; -} - -int set_function(int arch) -{ - switch(arch) { - case CS_ARCH_ARM: - function = get_detail_arm; - break; - case CS_ARCH_AARCH64: - function = get_detail_aarch64; - break; - case CS_ARCH_MIPS: - function = get_detail_mips; - break; - case CS_ARCH_PPC: - function = get_detail_ppc; - break; - case CS_ARCH_SPARC: - function = get_detail_sparc; - break; - case CS_ARCH_SYSZ: - function = get_detail_sysz; - break; - case CS_ARCH_X86: - function = get_detail_x86; - break; - case CS_ARCH_XCORE: - function = get_detail_xcore; - break; - case CS_ARCH_M68K: - function = get_detail_m68k; - break; - case CS_ARCH_M680X: - function = get_detail_m680x; - break; - case CS_ARCH_EVM: - function = get_detail_evm; - break; - case CS_ARCH_MOS65XX: - function = get_detail_mos65xx; - break; - case CS_ARCH_TMS320C64X: - function = get_detail_tms320c64x; - break; - case CS_ARCH_BPF: - function = get_detail_bpf; - break; - case CS_ARCH_RISCV: - function = get_detail_riscv; - break; - case CS_ARCH_TRICORE: - function = get_detail_tricore; - break; - case CS_ARCH_ALPHA: - function = get_detail_alpha; - break; - case CS_ARCH_HPPA: - function = get_detail_hppa; - break; - case CS_ARCH_LOONGARCH: - function = get_detail_loongarch; - break; - default: - return -1; - } - return 0; -} - -void test_single_issue(csh *handle, cs_mode mode, char *line, int detail) -{ - char **list_part, **list_byte, **list_part_issue_result; - int size_part, size_byte, size_part_issue_result; - int i, count, j; - unsigned char *code; - cs_insn *insn; - char *cs_result, *tmp, *p; - char **offset_opcode; - int size_offset_opcode; - unsigned long offset; - - cs_result = (char *)malloc(sizeof(char)); - cs_result[0] = '\0'; - - list_part = split(line, " == ", &size_part); - - offset_opcode = split(list_part[0], ": ", &size_offset_opcode); - if (size_offset_opcode > 1) { - offset = (unsigned int)strtol(offset_opcode[0], NULL, 16); - list_byte = split(offset_opcode[1], ",", &size_byte); - } else { - offset = 0; - list_byte = split(offset_opcode[0], ",", &size_byte); - } - free_strs(offset_opcode, size_offset_opcode); - - code = (unsigned char *)malloc(sizeof(char) * size_byte); - for (i = 0; i < size_byte; ++i) { - code[i] = (unsigned char)strtol(list_byte[i], NULL, 16); - } - - count = cs_disasm(*handle, code, size_byte, offset, 0, &insn); - free_strs(list_byte, size_byte); - free(code); - for (i = 0; i < count; ++i) { - tmp = (char *)malloc(strlen(insn[i].mnemonic) + strlen(insn[i].op_str) + 100); - strcpy(tmp, insn[i].mnemonic); - if (strlen(insn[i].op_str) > 0) { - tmp[strlen(insn[i].mnemonic)] = ' '; - strcpy(tmp + strlen(insn[i].mnemonic) + 1, insn[i].op_str); - } - add_str(&cs_result, "%s", tmp); - free(tmp); - } - - if (detail == 1) { - tmp = (*function)(handle, mode, insn); - add_str(&cs_result, "%s", tmp); - free(tmp); - - if (insn->detail->groups_count) { - add_str(&cs_result, " ; Groups: "); - for (j = 0; j < insn->detail->groups_count; j++) { - add_str(&cs_result, "%s ", cs_group_name(*handle, insn->detail->groups[j])); - } - } - } - - trim_str(cs_result); - add_str(&cs_result, " ;"); - // list_part_cs_result = split(cs_result, " ; ", &size_part_cs_result); - for (p = list_part[1]; *p; ++p) if (*p == '\t') *p = ' '; - list_part_issue_result = split(list_part[1], " ; ", &size_part_issue_result); - - for (i = 0; i < size_part_issue_result; ++i) { - trim_str(list_part_issue_result[i]); - char *tmptmp = (char *)malloc(sizeof(char)); - tmptmp[0] = '\0'; - add_str(&tmptmp, "%s", list_part_issue_result[i]); - add_str(&tmptmp, " ;"); - - if ((strstr(cs_result, tmptmp)) == NULL) { - fprintf(stderr, "[ ERROR ] --- %s --- \"%s\" not in \"%s\"\n", list_part[0], list_part_issue_result[i], cs_result); - cs_free(insn, count); - free_strs(list_part, size_part); - free(cs_result); - // free_strs(list_part_cs_result, size_part_cs_result); - free_strs(list_part_issue_result, size_part_issue_result); - free(tmptmp); - _fail(__FILE__, __LINE__); - } - free(tmptmp); - } - - cs_free(insn, count); - free_strs(list_part, size_part); - free(cs_result); - // free_strs(list_part_cs_result, size_part_cs_result); - free_strs(list_part_issue_result, size_part_issue_result); -} diff --git a/suite/cstest/src/cstest.c b/suite/cstest/src/cstest.c new file mode 100644 index 0000000000..6c25f5db9e --- /dev/null +++ b/suite/cstest/src/cstest.c @@ -0,0 +1,111 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#define _XOPEN_SOURCE 500 +#include "../../../utils.h" +#include "test_run.h" +#include +#include +#include +#include +#include +#include + +// Pointer to the file list table +// Must be a thread local, because we cannot pass arguments to `nftw`. +// So the found test files can only be saved, very annoyingly, +// to a global/thread-local mutable variables. +char ***test_files = NULL; +uint32_t file_count = 0; + +static void help(const char *self) +{ + fprintf(stderr, "%s / ...\n", self); +} + +static int handle_ftree_entry(const char *fpath, const struct stat *sb, + int typeflag, struct FTW *ftwbuf) +{ + if (typeflag != FTW_F) { + return 0; + } + const char *suffix = strstr(fpath, ".yaml"); + if (!suffix || suffix - fpath != strlen(fpath) - 5) { + // Misses the .yaml suffix. + return 0; + } + + file_count++; + *test_files = cs_mem_realloc(*test_files, sizeof(char *) * file_count); + if (!*test_files) { + fprintf(stderr, "[!] realloc failed\n"); + return -1; + } + test_files[0][file_count - 1] = cs_strdup(fpath); + return 0; +} + +/// Parses the test file paths from the @argv array. +static void get_tfiles(int argc, const char **argv) +{ + for (size_t i = 1; i < argc; ++i) { + if (nftw(argv[i], handle_ftree_entry, 20, + FTW_DEPTH | FTW_PHYS) == -1) { + fprintf(stderr, "[!] nftw failed.\n"); + return; + } + } +} + +void print_test_run_stats(const TestRunStats *stats) +{ + printf("\n-----------------------------------------\n"); + printf("Test run statistics\n\n"); + printf("Valid files: %" PRId32 "\n", stats->valid_test_files); + printf("Invalid files: %" PRId32 "\n", stats->invalid_files); + printf("Errors: %" PRId32 "\n\n", stats->errors); + printf("Test cases:\n"); + printf("\tTotal: %" PRId32 "\n", stats->tc_total); + printf("\tSuccessful: %" PRId32 "\n", stats->successful); + printf("\tSkipped: %" PRId32 "\n", stats->skipped); + printf("\tFailed: %" PRId32 "\n", stats->failed); + printf("-----------------------------------------\n"); + printf("\n"); +} + +int main(int argc, const char **argv) +{ + if (argc < 2 || strcmp(argv[1], "-h") == 0 || + strcmp(argv[1], "--help") == 0) { + help(argv[0]); + exit(EXIT_FAILURE); + } + test_files = malloc(sizeof(char **)); + *test_files = NULL; + + get_tfiles(argc, argv); + if (!*test_files || file_count == 0) { + fprintf(stderr, "Arguments are invalid. No files found.\n"); + exit(EXIT_FAILURE); + } + + printf("Test files found: %" PRId32 "\n", file_count); + TestRunStats stats = { 0 }; + TestRunResult res = cstest_run_tests(*test_files, file_count, &stats); + + print_test_run_stats(&stats); + if (res == TEST_RUN_ERROR) { + fprintf(stderr, "[!] An error occured.\n"); + exit(EXIT_FAILURE); + } else if (res == TEST_RUN_SUCCESS) { + printf("[o] All tests succeeded.\n"); + exit(EXIT_SUCCESS); + } else if (res == TEST_RUN_FAILURE) { + printf("\nNOTE: Asserts have the actual data on the left side: 'actual' != 'expected'\n\n"); + fprintf(stderr, "[!] Some tests failed.\n"); + exit(EXIT_FAILURE); + } + + fprintf(stderr, "[!] Unhandled Test Run result\n"); + exit(EXIT_FAILURE); +} diff --git a/suite/cstest/src/evm_detail.c b/suite/cstest/src/evm_detail.c deleted file mode 100644 index 635d309e35..0000000000 --- a/suite/cstest/src/evm_detail.c +++ /dev/null @@ -1,30 +0,0 @@ -/* Capstone testing regression */ -/* By Do Minh Tuan , 02-2019 */ - - -#include "factory.h" - -char *get_detail_evm(csh *handle, cs_mode mode, cs_insn *ins) -{ - cs_evm *evm; - char *result; - - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; - - if (ins->detail == NULL) - return result; - - evm = &(ins->detail->evm); - - if (evm->pop) - add_str(&result, " ; Pop: %u", evm->pop); - - if (evm->push) - add_str(&result, " ; Push: %u", evm->push); - - if (evm->fee) - add_str(&result, " ; Gas fee: %u", evm->fee); - - return result; -} diff --git a/suite/cstest/src/helper.c b/suite/cstest/src/helper.c index 6c3080e7f6..f3eccd550a 100644 --- a/suite/cstest/src/helper.c +++ b/suite/cstest/src/helper.c @@ -1,88 +1,20 @@ /* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ - +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cmocka.h" #include "helper.h" -char **split(const char *str, const char *delim, int *size) -{ - char **result = NULL; - char *token = NULL; - const char *src = str; - int cnt = 0; - - while ((token = strstr(src, delim)) != NULL) { - result = (char **)realloc(result, sizeof(char *) * (cnt + 1)); - result[cnt] = (char *)calloc(1, sizeof(char) * (int)(token - src + 10)); - memcpy(result[cnt], src, token - src); - result[cnt][token - src] = '\0'; - src = token + strlen(delim); - cnt ++; - } - - if (strlen(src) > 0) { - result = (char **)realloc(result, sizeof(char *) * (cnt + 1)); - result[cnt] = strdup(src); - cnt ++; - } - - *size = cnt; - return result; -} - -void print_strs(char **list_str, int size) -{ - int i; - - printf("[+] Debug %d strings:\n", size); - for (i = 0; i < size; ++i) - printf("String %d'th: %s\n", i+1, list_str[i]); -} - -void free_strs(char **list_str, int size) -{ - int i; - for (i = 0; i < size; ++i) - free(list_str[i]); - - free(list_str); -} - -const char *get_filename_ext(const char *filename) -{ - const char *dot; - - dot = strrchr(filename, '.'); - if (!dot || dot == filename) - return ""; - - return dot + 1; -} - -char *readfile(const char *filename) -{ - char *result; - FILE *fp; - int size; - - fp = fopen(filename, "r"); - if (fp == NULL) { - puts("No such file"); - exit(-1); - } - - fseek(fp, 0, SEEK_END); - size = ftell(fp); - rewind(fp); - - result = (char *)calloc(1, sizeof(char) * size + 1); - fread(result, size, 1, fp); - result[size] = '\0'; - - fclose(fp); - return result; -} - void add_str(char **src, const char *format, ...) { char *tmp; @@ -94,7 +26,7 @@ void add_str(char **src, const char *format, ...) vsprintf(tmp, format, args); va_end(args); - len1 = strlen(*src); + len1 = strlen(*src); len2 = strlen(tmp); *src = (char *)realloc(*src, sizeof(char) * (len1 + len2 + 10)); @@ -102,7 +34,7 @@ void add_str(char **src, const char *format, ...) free(tmp); } -void replace_hex(char *src) +void replace_hex(char *src, size_t src_len) { char *tmp, *result, *found, *origin, *orig_found; int valid; @@ -123,24 +55,29 @@ void replace_hex(char *src) tmp_tmp = strndup(tmp, orig_found - tmp); while (*found != '\0' && isxdigit(*found)) { valid = 1; - if (*found >= 'a' && *found <='f') - value = value*0x10 + (*found - 'a' + 10); + if (*found >= 'a' && *found <= 'f') + value = value * 0x10 + (*found - 'a' + 10); + else if (*found >= 'A' && *found <= 'F') + value = value * 0x10 + (*found - 'A' + 10); else - value = value*0x10 + (*found - '0'); + value = value * 0x10 + (*found - '0'); found++; } - if (valid == 1) add_str(&result, "%s%llu", tmp_tmp, value); - else add_str(&result, "%s0x", tmp_tmp); + if (valid == 1) + add_str(&result, "%s%llu", tmp_tmp, value); + else + add_str(&result, "%s0x", tmp_tmp); tmp = found; free(tmp_tmp); } add_str(&result, "%s", tmp); - if (strlen(result) >= MAXMEM) { - fprintf(stderr, "[ Error ] --- Buffer Overflow in replace_hex()\n"); + if (strlen(result) >= src_len) { free(result); free(origin); + fprintf(stderr, + "[ Error ] --- Buffer Overflow in replace_hex()\n"); _fail(__FILE__, __LINE__); } @@ -149,7 +86,7 @@ void replace_hex(char *src) free(origin); } -void replace_negative(char *src, int mode) +void replace_negative(char *src, size_t src_len, size_t arch_bits) { char *tmp, *result, *found, *origin, *orig_found; int cnt, valid; @@ -165,9 +102,9 @@ void replace_negative(char *src, int mode) while ((found = strstr(tmp, "-")) != NULL) { orig_found = found; - found ++; + found++; valid = 0; - + value = strdup("-"); cnt = 2; @@ -176,25 +113,26 @@ void replace_negative(char *src, int mode) value = (char *)realloc(value, cnt + 1); value[cnt - 1] = *found; value[cnt] = '\0'; - cnt ++; + cnt++; found++; } tmp_tmp = strndup(tmp, orig_found - tmp); if (valid == 1) { *orig_found = '\0'; - if (mode == X86_16) { + if (arch_bits == 16) { sscanf(value, "%hu", &tmp_short); add_str(&result, "%s%hu", tmp_tmp, tmp_short); - } else if (mode == X86_32) { + } else if (arch_bits == 32) { sscanf(value, "%u", &tmp_int); add_str(&result, "%s%u", tmp_tmp, tmp_int); - } else if (mode == X86_64) { + } else if (arch_bits == 64) { sscanf(value, "%lu", &tmp_long); add_str(&result, "%s%lu", tmp_tmp, tmp_long); } - } - else add_str(&result, "%s-", tmp_tmp); + + } else + add_str(&result, "%s-", tmp_tmp); tmp = found; free(value); @@ -202,8 +140,9 @@ void replace_negative(char *src, int mode) } add_str(&result, "%s", tmp); - if (strlen(result) >= MAXMEM) { - fprintf(stderr, "[ Error ] --- Buffer Overflow in replace_negative()\n"); + if (strlen(result) >= src_len) { + fprintf(stderr, + "[ Error ] --- Buffer Overflow in replace_negative()\n"); free(result); free(origin); _fail(__FILE__, __LINE__); @@ -214,45 +153,18 @@ void replace_negative(char *src, int mode) free(origin); } -void listdir(const char *name, char ***files, int *num_files) -{ - DIR *dir; - struct dirent *entry; - int cnt; - - if (!(dir = opendir(name))) - return; - - while ((entry = readdir(dir)) != NULL) { - if (entry->d_type == DT_DIR) { - char path[1024]; - if (strcmp(entry->d_name, ".") == 0 || strcmp(entry->d_name, "..") == 0) - continue; - snprintf(path, sizeof(path), "%s/%s", name, entry->d_name); - listdir(path, files, num_files); - } else { - cnt = *num_files; - *files = (char **)realloc(*files, sizeof(char *) * (cnt + 1)); - (*files)[cnt] = (char *)malloc(sizeof(char) * ( strlen(name) + 1 + strlen(entry->d_name) + 10)); - sprintf((*files)[cnt], "%s/%s", name, entry->d_name); - cnt ++; - *num_files = cnt; - } - } - - closedir(dir); -} - void trim_str(char *str) { - char tmp[MAXMEM]; + char tmp[MAX_ASM_TXT_MEM]; int start, end, j, i; start = 0; end = strlen(str) - 1; j = 0; - while (start < strlen(str) && isspace(str[start])) start++; - while (end >= 0 && isspace(str[end])) end--; + while (start < strlen(str) && isspace(str[start])) + start++; + while (end >= 0 && isspace(str[end])) + end--; for (i = start; i <= end; ++i) tmp[j++] = str[i]; @@ -263,27 +175,26 @@ void trim_str(char *str) return; } -void replace_tabs(char *str) +/// Normalizes the usage of spaces in the given string. +/// It does: +/// - Replaces '\t' with '\s' +/// - Replace '\s\s+' with a single space. +void norm_spaces(char *str) { - char tmp[MAXMEM]; - bool space_char = false; - - int j = 0; - for (int i = 0; i <= strlen(str); ++i) { - if (str[i] == ' ' || str[i] == '\t') { - space_char = true; - continue; - } - if (space_char) { - space_char = false; - tmp[j++] = ' '; - } - - tmp[j++] = str[i]; + assert(str); + char *space_ptr = NULL; + while ((space_ptr = strstr(str, "\t")) != NULL) { + *space_ptr = ' '; + } + while ((space_ptr = strstr(str, " ")) != NULL) { + memmove(space_ptr, space_ptr + 1, strlen(space_ptr)); } - - tmp[j] = '\0'; - strcpy(str, tmp); - return; } + +void str_to_lower(char *str) +{ + assert(str); + for (size_t i = 0; i < strlen(str); ++i) + str[i] = tolower(str[i]); +} diff --git a/suite/cstest/src/hppa_detail.c b/suite/cstest/src/hppa_detail.c deleted file mode 100644 index 213a73c4f9..0000000000 --- a/suite/cstest/src/hppa_detail.c +++ /dev/null @@ -1,96 +0,0 @@ -/* Capstone testing regression */ -/* By Dmitry Sibirtsev , 2023 */ - -#include "factory.h" - -char *get_detail_hppa(csh *p_handle, cs_mode mode, cs_insn *ins) -{ - cs_hppa *hppa; - int i; - cs_regs regs_read, regs_write; - uint8_t regs_read_count, regs_write_count; - - char *result; - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; - - if (ins->detail == NULL) - return result; - - csh handle = *p_handle; - - hppa = &(ins->detail->hppa); - - if (hppa->op_count) - add_str(&result, "\top_count: %u\n", hppa->op_count); - - for (i = 0; i < hppa->op_count; i++) { - cs_hppa_op *op = &(hppa->operands[i]); - switch ((int)op->type) { - default: - break; - case HPPA_OP_REG: - add_str(&result, "\t\toperands[%u].type: REG = %s\n", i, - cs_reg_name(handle, op->reg)); - break; - case HPPA_OP_IMM: - add_str(&result, "\t\toperands[%u].type: IMM = 0x%x\n", - i, op->imm); - break; - case HPPA_OP_IDX_REG: - add_str(&result, - "\t\toperands[%u].type: IDX_REG = %s\n", i, - cs_reg_name(handle, op->reg)); - break; - case HPPA_OP_DISP: - add_str(&result, "\t\toperands[%u].type: DISP = 0x%x\n", - i, op->imm); - break; - case HPPA_OP_MEM: - add_str(&result, "\t\toperands[%u].type: MEM\n", i); - if (op->mem.space != HPPA_REG_INVALID) { - add_str(&result, - "\t\t\toperands[%u].mem.space: REG = %s\n", - i, cs_reg_name(handle, op->mem.space)); - } - add_str(&result, - "\t\t\toperands[%u].mem.base: REG = %s\n", i, - cs_reg_name(handle, op->mem.base)); - break; - case HPPA_OP_TARGET: - add_str(&result, "\t\toperands[%u].type: ", i); - if (op->imm >= 0x8000000000000000) - add_str(&result, "TARGET = -0x%lx\n", -op->imm); - else - add_str(&result, "TARGET = 0x%lx\n", op->imm); - break; - } - - // Print out all registers accessed by this instruction (either implicit or - // explicit) - if (!cs_regs_access(handle, ins, regs_read, ®s_read_count, - regs_write, ®s_write_count)) { - if (regs_read_count) { - add_str(&result, "\tRegisters read:"); - for (i = 0; i < regs_read_count; i++) { - add_str(&result, " %s", - cs_reg_name(handle, - regs_read[i])); - } - add_str(&result, "\n"); - } - - if (regs_write_count) { - add_str(&result, "\tRegisters modified:"); - for (i = 0; i < regs_write_count; i++) { - add_str(&result, " %s", - cs_reg_name(handle, - regs_write[i])); - } - add_str(&result, "\n"); - } - } - } - - return result; -} diff --git a/suite/cstest/src/loongarch_detail.c b/suite/cstest/src/loongarch_detail.c deleted file mode 100644 index c96d7dc870..0000000000 --- a/suite/cstest/src/loongarch_detail.c +++ /dev/null @@ -1,51 +0,0 @@ -/* Capstone testing regression */ -/* By Do Minh Tuan , 02-2019 */ -/* Jiajie Chen , 2024 */ - - -#include "factory.h" - -char *get_detail_loongarch(csh *handle, cs_mode mode, cs_insn *ins) -{ - cs_loongarch *loongarch; - int i; - char *result; - - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; - - if (ins->detail == NULL) - return result; - - loongarch = &(ins->detail->loongarch); - if (loongarch->op_count) - add_str(&result, " ; op_count: %u", loongarch->op_count); - - for (i = 0; i < loongarch->op_count; i++) { - cs_loongarch_op *op = &(loongarch->operands[i]); - switch((int)op->type) { - default: - break; - case LOONGARCH_OP_REG: - add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); - break; - case LOONGARCH_OP_IMM: - add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm); - break; - case LOONGARCH_OP_MEM: - add_str(&result, " ; operands[%u].type: MEM", i); - if (op->mem.base != LOONGARCH_REG_INVALID) - add_str(&result, " ; operands[%u].mem.base: REG = %s", - i, cs_reg_name(*handle, op->mem.base)); - if (op->mem.index != LOONGARCH_REG_INVALID) - add_str(&result, " ; operands[%u].mem.index: REG = %s", - i, cs_reg_name(*handle, op->mem.index)); - if (op->mem.disp != 0) - add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); - break; - } - } - - return result; -} - diff --git a/suite/cstest/src/m680x_detail.c b/suite/cstest/src/m680x_detail.c deleted file mode 100644 index 62c4298121..0000000000 --- a/suite/cstest/src/m680x_detail.c +++ /dev/null @@ -1,137 +0,0 @@ -/* Capstone testing regression */ -/* By Do Minh Tuan , 02-2019 */ - - -#include "factory.h" - -static const char *s_access[] = { - "UNCHANGED", "READ", "WRITE", "READ ; WRITE", -}; - -static void print_read_write_regs(char *result, csh *handle, cs_detail *detail) -{ - int i; - - if (detail->regs_read_count > 0) { - add_str(&result, "\treading from regs: "); - - for (i = 0; i < detail->regs_read_count; ++i) { - if (i > 0) - add_str(&result, ", "); - - add_str(&result, "%s", cs_reg_name(*handle, detail->regs_read[i])); - } - } - - if (detail->regs_write_count > 0) { - add_str(&result, "\twriting to regs: "); - - for (i = 0; i < detail->regs_write_count; ++i) { - if (i > 0) - add_str(&result, ", "); - - add_str(&result, "%s", cs_reg_name(*handle, detail->regs_write[i])); - } - } -} - -char *get_detail_m680x(csh *handle, cs_mode mode, cs_insn *insn) -{ - cs_detail *detail = insn->detail; - cs_m680x *m680x = NULL; - int i; - char *result; - - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; - - if (detail == NULL) - return result; - - m680x = &detail->m680x; - - if (m680x->op_count) - add_str(&result, " ; op_count: %u", m680x->op_count); - - for (i = 0; i < m680x->op_count; i++) { - cs_m680x_op *op = &(m680x->operands[i]); - const char *comment; - - switch ((int)op->type) { - default: - break; - - case M680X_OP_REGISTER: - comment = ""; - - if ((i == 0 && m680x->flags & M680X_FIRST_OP_IN_MNEM) || - (i == 1 && m680x->flags & - M680X_SECOND_OP_IN_MNEM)) - comment = " (in mnemonic)"; - - add_str(&result, " ; operands[%u].type: REGISTER = %s%s", i, cs_reg_name(*handle, op->reg), comment); - break; - - case M680X_OP_CONSTANT: - add_str(&result, " ; operands[%u].type: CONSTANT = %u", i, op->const_val); - break; - - case M680X_OP_IMMEDIATE: - add_str(&result, " ; operands[%u].type: IMMEDIATE = #%d", i, op->imm); - break; - - case M680X_OP_DIRECT: - add_str(&result, " ; operands[%u].type: DIRECT = 0x%02x", i, op->direct_addr); - break; - - case M680X_OP_EXTENDED: - add_str(&result, " ; operands[%u].type: EXTENDED %s = 0x%04x", i, op->ext.indirect ? "INDIRECT" : "", op->ext.address); - break; - - case M680X_OP_RELATIVE: - add_str(&result, " ; operands[%u].type: RELATIVE = 0x%04x", i, op->rel.address); - break; - - case M680X_OP_INDEXED: - add_str(&result, " ; operands[%u].type: INDEXED%s", i, (op->idx.flags & M680X_IDX_INDIRECT) ? " INDIRECT" : ""); - - if (op->idx.base_reg != M680X_REG_INVALID) - add_str(&result, " ; base register: %s", cs_reg_name(*handle, op->idx.base_reg)); - - if (op->idx.offset_reg != M680X_REG_INVALID) - add_str(&result, " ; offset register: %s", cs_reg_name(*handle, op->idx.offset_reg)); - - if ((op->idx.offset_bits != 0) && - (op->idx.offset_reg == M680X_REG_INVALID) && - !op->idx.inc_dec) { - add_str(&result, " ; offset: %d", op->idx.offset); - - if (op->idx.base_reg == M680X_REG_PC) - add_str(&result, " ; offset address: 0x%x", op->idx.offset_addr); - - add_str(&result, " ; offset bits: %u", op->idx.offset_bits); - } - - if (op->idx.inc_dec) { - const char *post_pre = op->idx.flags & - M680X_IDX_POST_INC_DEC ? "post" : "pre"; - const char *inc_dec = (op->idx.inc_dec > 0) ? - "increment" : "decrement"; - - add_str(&result, " ; %s %s: %d", post_pre, inc_dec, abs(op->idx.inc_dec)); - } - - break; - } - - if (op->size != 0) - add_str(&result, " ; size: %u", op->size); - - if (op->access != CS_AC_INVALID) - add_str(&result, " ; access: %s", s_access[op->access]); - } - - print_read_write_regs(result, handle, detail); - - return result; -} diff --git a/suite/cstest/src/m68k_detail.c b/suite/cstest/src/m68k_detail.c deleted file mode 100644 index a3dfc74913..0000000000 --- a/suite/cstest/src/m68k_detail.c +++ /dev/null @@ -1,116 +0,0 @@ -/* Capstone testing regression */ -/* By Do Minh Tuan , 02-2019 */ - - -#include "factory.h" - -static const char* s_addressing_modes[] = { - "", - - "Register Direct - Data", - "Register Direct - Address", - - "Register Indirect - Address", - "Register Indirect - Address with Postincrement", - "Register Indirect - Address with Predecrement", - "Register Indirect - Address with Displacement", - - "Address Register Indirect With Index - 8-bit displacement", - "Address Register Indirect With Index - Base displacement", - - "Memory indirect - Postindex", - "Memory indirect - Preindex", - - "Program Counter Indirect - with Displacement", - - "Program Counter Indirect with Index - with 8-Bit Displacement", - "Program Counter Indirect with Index - with Base Displacement", - - "Program Counter Memory Indirect - Postindexed", - "Program Counter Memory Indirect - Preindexed", - - "Absolute Data Addressing - Short", - "Absolute Data Addressing - Long", - "Immediate value", -}; - -static void print_read_write_regs(char *result, cs_detail* detail, csh *handle) -{ - int i; - - for (i = 0; i < detail->regs_read_count; ++i) { - uint16_t reg_id = detail->regs_read[i]; - const char* reg_name = cs_reg_name(*handle, reg_id); - add_str(&result, " ; reading from reg: %s", reg_name); - } - - for (i = 0; i < detail->regs_write_count; ++i) { - uint16_t reg_id = detail->regs_write[i]; - const char* reg_name = cs_reg_name(*handle, reg_id); - add_str(&result, " ; writing to reg: %s", reg_name); - } -} - -char *get_detail_m68k(csh *handle, cs_mode mode, cs_insn *ins) -{ - cs_m68k* m68k; - cs_detail* detail; - int i; - char *result; - - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; - - if (ins->detail == NULL) - return result; - - - detail = ins->detail; - m68k = &detail->m68k; - if (m68k->op_count) - add_str(&result, " ; op_count: %u", m68k->op_count); - - print_read_write_regs(result, detail, handle); - - add_str(&result, " ; groups_count: %u", detail->groups_count); - - for (i = 0; i < m68k->op_count; i++) { - cs_m68k_op* op = &(m68k->operands[i]); - - switch((int)op->type) { - default: - break; - case M68K_OP_REG: - add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); - break; - case M68K_OP_IMM: - add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, (int)op->imm); - break; - case M68K_OP_MEM: - add_str(&result, " ; operands[%u].type: MEM", i); - if (op->mem.base_reg != M68K_REG_INVALID) - add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base_reg)); - if (op->mem.index_reg != M68K_REG_INVALID) { - add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index_reg)); - add_str(&result, " ; operands[%u].mem.index: size = %c", i, op->mem.index_size ? 'l' : 'w'); - } - if (op->mem.disp != 0) - add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); - if (op->mem.scale != 0) - add_str(&result, " ; operands[%u].mem.scale: %d", i, op->mem.scale); - - add_str(&result, " ; address mode: %s", s_addressing_modes[op->address_mode]); - break; - case M68K_OP_FP_SINGLE: - add_str(&result, " ; operands[%u].type: FP_SINGLE", i); - add_str(&result, " ; operands[%u].simm: %f", i, op->simm); - break; - case M68K_OP_FP_DOUBLE: - add_str(&result, " ; operands[%u].type: FP_DOUBLE", i); - add_str(&result, " ; operands[%u].dimm: %lf", i, op->dimm); - break; - } - } - - return result; -} diff --git a/suite/cstest/src/main.c b/suite/cstest/src/main.c deleted file mode 100644 index 5da0e4998e..0000000000 --- a/suite/cstest/src/main.c +++ /dev/null @@ -1,493 +0,0 @@ -/* Capstone testing regression */ -/* By Do Minh Tuan , 02-2019 */ - - -#include "helper.h" -#include "capstone_test.h" -#include - -#define ARR_SIZE(a) (sizeof(a)/sizeof(a[0])) - -static single_dict arches[] = { - {"CS_ARCH_ARM", CS_ARCH_ARM}, - {"CS_ARCH_AARCH64", CS_ARCH_AARCH64}, - {"CS_ARCH_MIPS", CS_ARCH_MIPS}, - {"CS_ARCH_PPC", CS_ARCH_PPC}, - {"CS_ARCH_SPARC", CS_ARCH_SPARC}, - {"CS_ARCH_SYSZ", CS_ARCH_SYSZ}, - {"CS_ARCH_X86", CS_ARCH_X86}, - {"CS_ARCH_XCORE", CS_ARCH_XCORE}, - {"CS_ARCH_M68K", CS_ARCH_M68K}, - {"CS_ARCH_BPF", CS_ARCH_BPF}, - {"CS_ARCH_RISCV", CS_ARCH_RISCV}, - {"CS_ARCH_TRICORE", CS_ARCH_TRICORE}, - {"CS_ARCH_ALPHA", CS_ARCH_ALPHA}, - {"CS_ARCH_HPPA", CS_ARCH_HPPA}, - {"CS_ARCH_LOONGARCH", CS_ARCH_LOONGARCH}, -}; - - static single_dict modes[] = { - {"CS_MODE_LITTLE_ENDIAN", CS_MODE_LITTLE_ENDIAN}, - {"CS_MODE_ARM", CS_MODE_ARM}, - {"CS_MODE_16", CS_MODE_16}, - {"CS_MODE_32", CS_MODE_32}, - {"CS_MODE_64", CS_MODE_64}, - {"CS_MODE_THUMB", CS_MODE_THUMB}, - {"CS_MODE_MCLASS", CS_MODE_MCLASS}, - {"CS_MODE_V8", CS_MODE_V8}, - {"CS_MODE_MICRO", CS_MODE_MICRO}, - {"CS_MODE_MIPS3", CS_MODE_MIPS3}, - {"CS_MODE_MIPS32R6", CS_MODE_MIPS32R6}, - {"CS_MODE_MIPS2", CS_MODE_MIPS2}, - {"CS_MODE_V9", CS_MODE_V9}, - {"CS_MODE_QPX", CS_MODE_QPX}, - {"CS_MODE_PS", CS_MODE_PS}, - {"CS_MODE_M68K_000", CS_MODE_M68K_000}, - {"CS_MODE_M68K_010", CS_MODE_M68K_010}, - {"CS_MODE_M68K_020", CS_MODE_M68K_020}, - {"CS_MODE_M68K_030", CS_MODE_M68K_030}, - {"CS_MODE_M68K_040", CS_MODE_M68K_040}, - {"CS_MODE_M68K_060", CS_MODE_M68K_060}, - {"CS_MODE_BIG_ENDIAN", CS_MODE_BIG_ENDIAN}, - {"CS_MODE_MIPS32", CS_MODE_MIPS32}, - {"CS_MODE_MIPS64", CS_MODE_MIPS64}, - {"CS_MODE_M680X_6301", CS_MODE_M680X_6301}, - {"CS_MODE_M680X_6309", CS_MODE_M680X_6309}, - {"CS_MODE_M680X_6800", CS_MODE_M680X_6800}, - {"CS_MODE_M680X_6801", CS_MODE_M680X_6801}, - {"CS_MODE_M680X_6805", CS_MODE_M680X_6805}, - {"CS_MODE_M680X_6808", CS_MODE_M680X_6808}, - {"CS_MODE_M680X_6809", CS_MODE_M680X_6809}, - {"CS_MODE_M680X_6811", CS_MODE_M680X_6811}, - {"CS_MODE_M680X_CPU12", CS_MODE_M680X_CPU12}, - {"CS_MODE_M680X_HCS08", CS_MODE_M680X_HCS08}, - {"CS_MODE_BPF_CLASSIC", CS_MODE_BPF_CLASSIC}, - {"CS_MODE_BPF_EXTENDED", CS_MODE_BPF_EXTENDED}, - {"CS_MODE_RISCV32", CS_MODE_RISCV32}, - {"CS_MODE_RISCV64", CS_MODE_RISCV64}, - {"CS_MODE_RISCVC", CS_MODE_RISCVC}, - {"CS_MODE_TRICORE_110", CS_MODE_TRICORE_110}, - {"CS_MODE_TRICORE_120", CS_MODE_TRICORE_120}, - {"CS_MODE_TRICORE_130", CS_MODE_TRICORE_130}, - {"CS_MODE_TRICORE_131", CS_MODE_TRICORE_131}, - {"CS_MODE_TRICORE_160", CS_MODE_TRICORE_160}, - {"CS_MODE_TRICORE_161", CS_MODE_TRICORE_161}, - {"CS_MODE_TRICORE_162", CS_MODE_TRICORE_162}, - {"CS_MODE_HPPA_20", CS_MODE_HPPA_20}, - {"CS_MODE_HPPA_20W", CS_MODE_HPPA_20W}, - {"CS_MODE_HPPA_11", CS_MODE_HPPA_11}, - {"CS_MODE_LOONGARCH32", CS_MODE_LOONGARCH32}, - {"CS_MODE_LOONGARCH64", CS_MODE_LOONGARCH64}, -}; - - static double_dict options[] = { - {"CS_OPT_DETAIL", CS_OPT_DETAIL, CS_OPT_ON}, - {"CS_OPT_SKIPDATA", CS_OPT_SKIPDATA, CS_OPT_ON}, - {"CS_OPT_SYNTAX_DEFAULT", CS_OPT_SYNTAX, CS_OPT_SYNTAX_DEFAULT}, - {"CS_OPT_SYNTAX_INTEL", CS_OPT_SYNTAX, CS_OPT_SYNTAX_INTEL}, - {"CS_OPT_SYNTAX_ATT", CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT}, - {"CS_OPT_SYNTAX_NOREGNAME", CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME}, - {"CS_OPT_SYNTAX_MASM", CS_OPT_SYNTAX, CS_OPT_SYNTAX_MASM}, - {"CS_OPT_BRANCH_OFFSET", CS_OPT_NO_BRANCH_OFFSET, CS_OPT_NO_BRANCH_OFFSET}, - {"CS_MODE_LITTLE_ENDIAN", CS_OPT_MODE, CS_MODE_LITTLE_ENDIAN}, - {"CS_MODE_ARM", CS_OPT_MODE, CS_MODE_ARM}, - {"CS_MODE_16", CS_OPT_MODE, CS_MODE_16}, - {"CS_MODE_32", CS_OPT_MODE, CS_MODE_32}, - {"CS_MODE_64", CS_OPT_MODE, CS_MODE_64}, - {"CS_MODE_THUMB", CS_OPT_MODE, CS_MODE_THUMB}, - {"CS_MODE_MCLASS", CS_OPT_MODE, CS_MODE_MCLASS}, - {"CS_MODE_V8", CS_OPT_MODE, CS_MODE_V8}, - {"CS_MODE_MICRO", CS_OPT_MODE, CS_MODE_MICRO}, - {"CS_MODE_MIPS3", CS_OPT_MODE, CS_MODE_MIPS3}, - {"CS_MODE_MIPS32R6", CS_OPT_MODE, CS_MODE_MIPS32R6}, - {"CS_MODE_MIPS2", CS_OPT_MODE, CS_MODE_MIPS2}, - {"CS_MODE_V9", CS_OPT_MODE, CS_MODE_V9}, - {"CS_MODE_QPX", CS_OPT_MODE, CS_MODE_QPX}, - {"CS_MODE_PS", CS_OPT_MODE, CS_MODE_PS}, - {"CS_MODE_BOOKE", CS_OPT_MODE, CS_MODE_BOOKE}, - {"CS_MODE_M68K_000", CS_OPT_MODE, CS_MODE_M68K_000}, - {"CS_MODE_M68K_010", CS_OPT_MODE, CS_MODE_M68K_010}, - {"CS_MODE_M68K_020", CS_OPT_MODE, CS_MODE_M68K_020}, - {"CS_MODE_M68K_030", CS_OPT_MODE, CS_MODE_M68K_030}, - {"CS_MODE_M68K_040", CS_OPT_MODE, CS_MODE_M68K_040}, - {"CS_MODE_M68K_060", CS_OPT_MODE, CS_MODE_M68K_060}, - {"CS_MODE_BIG_ENDIAN", CS_OPT_MODE, CS_MODE_BIG_ENDIAN}, - {"CS_MODE_MIPS32", CS_OPT_MODE, CS_MODE_MIPS32}, - {"CS_MODE_MIPS64", CS_OPT_MODE, CS_MODE_MIPS64}, - {"CS_MODE_M680X_6301", CS_OPT_MODE, CS_MODE_M680X_6301}, - {"CS_MODE_M680X_6309", CS_OPT_MODE, CS_MODE_M680X_6309}, - {"CS_MODE_M680X_6800", CS_OPT_MODE, CS_MODE_M680X_6800}, - {"CS_MODE_M680X_6801", CS_OPT_MODE, CS_MODE_M680X_6801}, - {"CS_MODE_M680X_6805", CS_OPT_MODE, CS_MODE_M680X_6805}, - {"CS_MODE_M680X_6808", CS_OPT_MODE, CS_MODE_M680X_6808}, - {"CS_MODE_M680X_6809", CS_OPT_MODE, CS_MODE_M680X_6809}, - {"CS_MODE_M680X_6811", CS_OPT_MODE, CS_MODE_M680X_6811}, - {"CS_MODE_M680X_CPU12", CS_OPT_MODE, CS_MODE_M680X_CPU12}, - {"CS_MODE_M680X_HCS08", CS_OPT_MODE, CS_MODE_M680X_HCS08}, - {"CS_MODE_RISCV32", CS_OPT_MODE, CS_MODE_RISCV32}, - {"CS_MODE_RISCV64", CS_OPT_MODE, CS_MODE_RISCV64}, - {"CS_MODE_TRICORE_110", CS_OPT_MODE, CS_MODE_TRICORE_110}, - {"CS_MODE_TRICORE_120", CS_OPT_MODE, CS_MODE_TRICORE_120}, - {"CS_MODE_TRICORE_130", CS_OPT_MODE, CS_MODE_TRICORE_130}, - {"CS_MODE_TRICORE_131", CS_OPT_MODE, CS_MODE_TRICORE_131}, - {"CS_MODE_TRICORE_160", CS_OPT_MODE, CS_MODE_TRICORE_160}, - {"CS_MODE_TRICORE_161", CS_OPT_MODE, CS_MODE_TRICORE_161}, - {"CS_MODE_TRICORE_162", CS_OPT_MODE, CS_MODE_TRICORE_162}, - {"CS_OPT_UNSIGNED", CS_OPT_UNSIGNED, CS_OPT_ON}, - {"CS_MODE_HPPA_20", CS_OPT_MODE, CS_MODE_HPPA_20}, - {"CS_MODE_HPPA_20W", CS_OPT_MODE, CS_MODE_HPPA_20W}, - {"CS_MODE_HPPA_11", CS_OPT_MODE, CS_MODE_HPPA_11}, - {"CS_MODE_LOONGARCH32", CS_OPT_MODE, CS_MODE_LOONGARCH32}, - {"CS_MODE_LOONGARCH64", CS_OPT_MODE, CS_MODE_LOONGARCH64}, -}; - -static int counter; -static char **list_lines; -static int failed_setup; -static int size_lines; -static cs_mode issue_mode; -static int getDetail; -static int mc_mode; -static int e_flag; - -static int setup_state(void **state) { - csh *handle; - char **list_params; - int size_params; - int arch, mode; - int i, tmp_counter; - - if (failed_setup) { - fprintf(stderr, "[ ERROR ] --- Invalid file to setup\n"); - return -1; - } - - tmp_counter = 0; - while (tmp_counter < size_lines && list_lines[tmp_counter][0] != '#') - tmp_counter++; - - list_params = split(list_lines[tmp_counter] + 2, ", ", &size_params); - if (size_params != 3) { - fprintf(stderr, "[ ERROR ] --- Invalid options ( arch, mode, option )\n"); - failed_setup = 1; - return -1; - } - - arch = get_value(arches, ARR_SIZE(arches), list_params[0]); - if (arch == -1) { - fprintf(stderr, "[ ERROR ] --- Arch is not supported!\n"); - failed_setup = 1; - return -1; - } - - if (!strcmp(list_params[0], "CS_ARCH_AARCH64")) - mc_mode = 2; - else - mc_mode = 1; - - mode = 0; - for (i = 0; i < ARR_SIZE(modes); ++i) { - if (strstr(list_params[1], modes[i].str)) { - mode += modes[i].value; - switch (modes[i].value) { - case CS_MODE_16: - mc_mode = 0; - break; - case CS_MODE_64: - mc_mode = 2; - break; - case CS_MODE_THUMB: - mc_mode = 1; - break; - default: - break; - } - } - } - - handle = (csh *)malloc(sizeof(csh)); - if(cs_open(arch, mode, handle) != CS_ERR_OK) { - fprintf(stderr, "[ ERROR ] --- Cannot initialize capstone\n"); - failed_setup = 1; - return -1; - } - - for (i = 0; i < ARR_SIZE(options); ++i) { - if (strstr(list_params[2], options[i].str)) { - if (cs_option(*handle, options[i].first_value, options[i].second_value) != CS_ERR_OK) { - fprintf(stderr, "[ ERROR ] --- Option is not supported for this arch/mode\n"); - failed_setup = 1; - return -1; - } - } - } - *state = (void *)handle; - free_strs(list_params, size_params); - return 0; -} - -static int setup_MC(void **state) -{ - counter++; - if (e_flag == 0) - while (counter < size_lines && strncmp(list_lines[counter], "0x", 2)) - counter++; - else - while (counter < size_lines && strncmp(list_lines[counter], "// 0x", 5)) - counter++; - - return 0; -} - -static void test_MC(void **state) -{ - if (e_flag == 1) - test_single_MC((csh *)*state, mc_mode, list_lines[counter] + 3); - else - test_single_MC((csh *)*state, mc_mode, list_lines[counter]); -} - -static int teardown_state(void **state) -{ - cs_close(*state); - free(*state); - return 0; -} - -static int setup_issue(void **state) -{ - csh *handle; - char **list_params; - int size_params; - int arch, mode; - int i, result; - - getDetail = 0; - failed_setup = 0; - - if (e_flag == 0) - while (counter < size_lines && strncmp(list_lines[counter], "!# ", 3)) - counter++; // get issue line - else - while (counter < size_lines && strncmp(list_lines[counter], "// !# ", 6)) - counter++; - - counter++; - if (e_flag == 0) - while (counter < size_lines && strncmp(list_lines[counter], "!#", 2)) - counter++; // get arch line - else - while (counter < size_lines && strncmp(list_lines[counter], "// !# ", 6)) - counter++; - - if (e_flag == 0) - list_params = split(list_lines[counter] + 3, ", ", &size_params); - else - list_params = split(list_lines[counter] + 6, ", ", &size_params); - - arch = get_value(arches, ARR_SIZE(arches), list_params[0]); - - if (!strcmp(list_params[0], "CS_ARCH_AARCH64")) - mc_mode = 2; - else - mc_mode = 1; - - mode = 0; - for (i = 0; i < ARR_SIZE(modes); ++i) { - if (strstr(list_params[1], modes[i].str)) { - mode += modes[i].value; - switch (modes[i].value) { - case CS_MODE_16: - mc_mode = 0; - break; - case CS_MODE_64: - mc_mode = 2; - break; - case CS_MODE_THUMB: - mc_mode = 1; - break; - default: - break; - } - } - } - - if (arch == -1) { - fprintf(stderr, "[ ERROR ] --- Arch is not supported!\n"); - failed_setup = 1; - return -1; - } - - handle = (csh *)calloc(1, sizeof(csh)); - if(cs_open(arch, mode, handle) != CS_ERR_OK) { - fprintf(stderr, "[ ERROR ] --- Cannot initialize capstone\n"); - failed_setup = 1; - return -1; - } - - for (i = 0; i < ARR_SIZE(options); ++i) { - if (strstr(list_params[2], options[i].str)) { - if (cs_option(*handle, options[i].first_value, options[i].second_value) != CS_ERR_OK) { - fprintf(stderr, "[ ERROR ] --- Option is not supported for this arch/mode\n"); - failed_setup = 1; - return -1; - } - - if (i == 0) { - result = set_function(arch); - if (result == -1) { - fprintf(stderr, "[ ERROR ] --- Cannot get details\n"); - failed_setup = 1; - return -1; - } - - getDetail = 1; - } - } - } - - *state = (void *)handle; - issue_mode = mode; - - if (e_flag == 0) - while (counter < size_lines && strncmp(list_lines[counter], "0x", 2)) - counter++; - else - while (counter < size_lines && strncmp(list_lines[counter], "// 0x", 5)) - counter++; - - free_strs(list_params, size_params); - return 0; -} - -static void test_issue(void **state) -{ - if (e_flag == 0) - test_single_issue((csh *)*state, issue_mode, list_lines[counter], getDetail); - else - test_single_issue((csh *)*state, issue_mode, list_lines[counter] + 3, getDetail); - - return; -} - -static int teardown_issue(void **state) -{ - if (e_flag == 0) - while (counter < size_lines && strncmp(list_lines[counter], "!# ", 3)) - counter++; - else - while (counter < size_lines && strncmp(list_lines[counter], "// !# ", 6)) - counter++; - - cs_close(*state); - free(*state); - function = NULL; - return 0; -} - -static void test_file(const char *filename) -{ - int i; - char *content, *tmp; - struct CMUnitTest *tests; - int number_of_tests; - - printf("[+] TARGET: %s\n", filename); - content = readfile(filename); - counter = 0; - failed_setup = 0; - function = NULL; - - if (strstr(filename, "issue")) { - number_of_tests = 0; - list_lines = split(content, "\n", &size_lines); - tests = NULL; - for (i = 0; i < size_lines; ++i) { - if ((!strncmp(list_lines[i], "// !# issue", 11) && e_flag == 1) || - (!strncmp(list_lines[i], "!# issue", 8) && e_flag == 0)) { - tests = (struct CMUnitTest *)realloc(tests, sizeof(struct CMUnitTest) * (number_of_tests + 1)); - tests[number_of_tests] = (struct CMUnitTest)cmocka_unit_test_setup_teardown(test_issue, setup_issue, teardown_issue); - tests[number_of_tests].name = strdup(list_lines[i]); - number_of_tests ++; - } - } - - _cmocka_run_group_tests("Testing issues", tests, number_of_tests, NULL, NULL); - } else { - list_lines = split(content, "\n", &size_lines); - number_of_tests = 0; - - tests = NULL; - for (i = 1; i < size_lines; ++i) { - if ((!strncmp(list_lines[i], "// 0x", 5) && e_flag == 1) || (!strncmp(list_lines[i], "0x", 2) && e_flag == 0)) { - tmp = (char *)malloc(sizeof(char) * 100); - sprintf(tmp, "Line %d", i+1); - tests = (struct CMUnitTest *)realloc(tests, sizeof(struct CMUnitTest) * (number_of_tests + 1)); - tests[number_of_tests] = (struct CMUnitTest)cmocka_unit_test_setup_teardown(test_MC, setup_MC, NULL); - tests[number_of_tests].name = tmp; - number_of_tests ++; - } - } - - _cmocka_run_group_tests("Testing MC", tests, number_of_tests, setup_state, teardown_state); - } - - printf("[+] DONE: %s\n", filename); - printf("[!] Noted:\n[ ERROR ] --- \"\" != \"\"\n"); - printf("\n\n"); - free_strs(list_lines, size_lines); - for (int k = 0; tests && k < number_of_tests; k++) { - free((char *)tests[k].name); - } - free(tests); - free(content); -} - -static void test_folder(const char *folder) -{ - char **files; - int num_files, i; - - files = NULL; - num_files = 0; - listdir(folder, &files, &num_files); - for (i = 0; i < num_files; ++i) { - if (strcmp("cs", get_filename_ext(files[i]))) - continue; - test_file(files[i]); - } -} - -int main(int argc, char *argv[]) -{ - int opt, flag; - - flag = 0; - e_flag = 0; - - while ((opt = getopt(argc, argv, "ef:d:")) > 0) { - switch (opt) { - case 'f': - test_file(optarg); - flag = 1; - break; - case 'd': - test_folder(optarg); - flag = 1; - break; - case 'e': - e_flag = 1; - break; - default: - printf("Usage: %s [-e] [-f ] [-d ]\n", argv[0]); - exit(-1); - } - } - - if (flag == 0) { - printf("Usage: %s [-e] [-f ] [-d ]\n", argv[0]); - exit(-1); - } - - return 0; -} diff --git a/suite/cstest/src/mips_detail.c b/suite/cstest/src/mips_detail.c deleted file mode 100644 index c859ab6d7f..0000000000 --- a/suite/cstest/src/mips_detail.c +++ /dev/null @@ -1,48 +0,0 @@ -/* Capstone testing regression */ -/* By Do Minh Tuan , 02-2019 */ - - -#include "factory.h" - -char *get_detail_mips(csh *handle, cs_mode mode, cs_insn *ins) -{ - int i; - cs_mips *mips; - char *result; - - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; - - if (ins->detail == NULL) - return result; - - mips = &(ins->detail->mips); - if (mips->op_count) - add_str(&result, " ; op_count: %u", mips->op_count); - - for (i = 0; i < mips->op_count; i++) { - cs_mips_op *op = &(mips->operands[i]); - switch((int)op->type) { - default: - break; - case MIPS_OP_REG: - add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); - break; - case MIPS_OP_IMM: - add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm); - break; - case MIPS_OP_MEM: - add_str(&result, " ; operands[%u].type: MEM", i); - if (op->mem.base != MIPS_REG_INVALID) - add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); - if (op->mem.disp != 0) - add_str(&result, " ; operands[%u].mem.disp: 0x%" PRIx64 "", i, op->mem.disp); - - break; - } - - } - - return result; -} - diff --git a/suite/cstest/src/mos65xx_detail.c b/suite/cstest/src/mos65xx_detail.c deleted file mode 100644 index b039f2e764..0000000000 --- a/suite/cstest/src/mos65xx_detail.c +++ /dev/null @@ -1,103 +0,0 @@ -/* Capstone testing regression */ -/* By Do Minh Tuan , 02-2019 */ - - -#include "factory.h" - -static const char *get_am_name(mos65xx_address_mode mode) -{ - switch(mode) { - default: - case MOS65XX_AM_NONE: - return "No address mode"; - case MOS65XX_AM_IMP: - return "implied"; - case MOS65XX_AM_ACC: - return "accumulator"; - case MOS65XX_AM_IMM: - return "immediate value"; - case MOS65XX_AM_REL: - return "relative"; - case MOS65XX_AM_INT: - return "interrupt signature"; - case MOS65XX_AM_BLOCK: - return "block move"; - case MOS65XX_AM_ZP: - return "zero page"; - case MOS65XX_AM_ZP_X: - return "zero page indexed with x"; - case MOS65XX_AM_ZP_Y: - return "zero page indexed with y"; - case MOS65XX_AM_ZP_REL: - return "relative bit branch"; - case MOS65XX_AM_ZP_IND: - return "zero page indirect"; - case MOS65XX_AM_ZP_X_IND: - return "zero page indexed with x indirect"; - case MOS65XX_AM_ZP_IND_Y: - return "zero page indirect indexed with y"; - case MOS65XX_AM_ZP_IND_LONG: - return "zero page indirect long"; - case MOS65XX_AM_ZP_IND_LONG_Y: - return "zero page indirect long indexed with y"; - case MOS65XX_AM_ABS: - return "absolute"; - case MOS65XX_AM_ABS_X: - return "absolute indexed with x"; - case MOS65XX_AM_ABS_Y: - return "absolute indexed with y"; - case MOS65XX_AM_ABS_IND: - return "absolute indirect"; - case MOS65XX_AM_ABS_X_IND: - return "absolute indexed with x indirect"; - case MOS65XX_AM_ABS_IND_LONG: - return "absolute indirect long"; - case MOS65XX_AM_ABS_LONG: - return "absolute long"; - case MOS65XX_AM_ABS_LONG_X: - return "absolute long indexed with x"; - case MOS65XX_AM_SR: - return "stack relative"; - case MOS65XX_AM_SR_IND_Y: - return "stack relative indirect indexed with y"; - } -} - - -char *get_detail_mos65xx(csh *handle, cs_mode mode, cs_insn *ins) -{ - int i; - cs_mos65xx *mos65xx; - char *result; - - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; - - if (ins->detail == NULL) - return result; - - mos65xx = &(ins->detail->mos65xx); - add_str(&result, " ; address mode: %s", get_am_name(mos65xx->am)); - add_str(&result, " ; modifies flags: %s", mos65xx->modifies_flags ? "true": "false"); - - if (mos65xx->op_count) - add_str(&result, " ; op_count: %u", mos65xx->op_count); - - for (i = 0; i < mos65xx->op_count; i++) { - cs_mos65xx_op *op = &(mos65xx->operands[i]); - switch((int)op->type) { - default: - break; - case MOS65XX_OP_REG: - add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); - break; - case MOS65XX_OP_IMM: - add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm); - break; - case MOS65XX_OP_MEM: - add_str(&result, " ; operands[%u].type: MEM = 0x%x", i, op->mem); - break; - } - } - return result; -} diff --git a/suite/cstest/src/ppc_detail.c b/suite/cstest/src/ppc_detail.c deleted file mode 100644 index 53660e50f4..0000000000 --- a/suite/cstest/src/ppc_detail.c +++ /dev/null @@ -1,96 +0,0 @@ -/* Capstone testing regression */ -/* By Do Minh Tuan , 02-2019 */ - - -#include "factory.h" - -static const char* get_pred_name(int bc) -{ - switch(bc) { - default: - case PPC_PRED_LT: - return ("lt"); - case PPC_PRED_LE: - return ("le"); - case PPC_PRED_EQ: - return ("eq"); - case PPC_PRED_GE: - return ("ge"); - case PPC_PRED_GT: - return ("gt"); - case PPC_PRED_NE: - return ("ne"); - case PPC_PRED_UN: - return ("so/un"); - case PPC_PRED_NU: - return ("ns/nu"); - } -} - -char *get_detail_ppc(csh *handle, cs_mode mode, cs_insn *ins) -{ - cs_ppc *ppc; - int i; - char *result; - - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; - - if (ins->detail == NULL) - return result; - - ppc = &(ins->detail->ppc); - if (ppc->op_count) - add_str(&result, " ; op_count: %u", ppc->op_count); - - for (i = 0; i < ppc->op_count; i++) { - cs_ppc_op *op = &(ppc->operands[i]); - switch((int)op->type) { - default: - break; - case PPC_OP_REG: - add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); - break; - case PPC_OP_IMM: - add_str(&result, " ; operands[%u].type: IMM = 0x%"PRIx64"", i, op->imm); - break; - case PPC_OP_MEM: - add_str(&result, " ; operands[%u].type: MEM", i); - if (op->mem.base != PPC_REG_INVALID) - add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); - if (op->mem.disp != 0) - add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); - - break; - } - } - - if (ppc->bc.pred_cr != PPC_PRED_INVALID || - ppc->bc.pred_ctr != PPC_PRED_INVALID) { - printf("\tBranch:\n"); - printf("\t\tbi: %u\n", ppc->bc.bi); - printf("\t\tbo: %u\n", ppc->bc.bo); - if (ppc->bc.bh != PPC_BH_INVALID) - printf("\t\tbh: %u\n", ppc->bc.bh); - if (ppc->bc.pred_cr != PPC_PRED_INVALID) { - printf("\t\tcrX: %s\n", cs_reg_name(*handle, ppc->bc.crX)); - printf("\t\tpred CR-bit: %s\n", get_pred_name(ppc->bc.pred_cr)); - } - if (ppc->bc.pred_ctr != PPC_PRED_INVALID) - printf("\t\tpred CTR: %s\n", get_pred_name(ppc->bc.pred_ctr)); - if (ppc->bc.hint != PPC_BR_NOT_GIVEN) - printf("\t\thint: %u\n", ppc->bc.hint); - } - - if (ppc->bc.hint != PPC_BR_NOT_GIVEN) - printf("\tBranch hint: %u\n", ppc->bc.hint); - - if (ppc->bc.hint != PPC_BR_NOT_GIVEN) - add_str(&result, " ; Branch hint: %u", ppc->bc.hint); - - if (ppc->update_cr0) - add_str(&result, " ; Update-CR0: True"); - - return result; -} - diff --git a/suite/cstest/src/riscv_detail.c b/suite/cstest/src/riscv_detail.c deleted file mode 100644 index ac9ea03d86..0000000000 --- a/suite/cstest/src/riscv_detail.c +++ /dev/null @@ -1,61 +0,0 @@ -/* Capstone testing regression */ -/* By Do Minh Tuan , 02-2019 */ - - -#include "factory.h" - -char *get_detail_riscv(csh *handle, cs_mode mode, cs_insn *ins) -{ - cs_riscv *riscv; - int i; - char *result; - - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; - - if (ins->detail == NULL) - return result; - - riscv = &(ins->detail->riscv); - if (riscv->op_count) - add_str(&result, " ; op_count: %u", riscv->op_count); - - for (i = 0; i < riscv->op_count; i++) { - cs_riscv_op *op = &(riscv->operands[i]); - switch((int)op->type) { - default: - break; - case RISCV_OP_REG: - add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); - break; - case RISCV_OP_IMM: - add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm); - break; - case RISCV_OP_MEM: - add_str(&result, " ; operands[%u].type: MEM", i); - if (op->mem.base != RISCV_REG_INVALID) - add_str(&result, " ; operands[%u].mem.base: REG = %s", - i, cs_reg_name(*handle, op->mem.base)); - if (op->mem.disp != 0) - add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); - break; - } - - switch(op->access) { - default: - break; - case CS_AC_READ: - add_str(&result, " ; operands[%u].access: READ", i); - break; - case CS_AC_WRITE: - add_str(&result, " ; operands[%u].access: WRITE", i); - break; - case CS_AC_READ | CS_AC_WRITE: - add_str(&result, " ; operands[%u].access: READ | WRITE", i); - break; - } - } - - return result; -} - diff --git a/suite/cstest/src/sparc_detail.c b/suite/cstest/src/sparc_detail.c deleted file mode 100644 index 54c6bb4837..0000000000 --- a/suite/cstest/src/sparc_detail.c +++ /dev/null @@ -1,55 +0,0 @@ -/* Capstone testing regression */ -/* By Do Minh Tuan , 02-2019 */ - - -#include "factory.h" - -char *get_detail_sparc(csh *handle, cs_mode mode, cs_insn *ins) -{ - cs_sparc *sparc; - int i; - char *result; - - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; - - if (ins->detail == NULL) - return result; - - sparc = &(ins->detail->sparc); - if (sparc->op_count) - add_str(&result, " ; op_count: %u", sparc->op_count); - - for (i = 0; i < sparc->op_count; i++) { - cs_sparc_op *op = &(sparc->operands[i]); - switch((int)op->type) { - default: - break; - case SPARC_OP_REG: - add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); - break; - case SPARC_OP_IMM: - add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm); - break; - case SPARC_OP_MEM: - add_str(&result, " ; operands[%u].type: MEM", i); - if (op->mem.base != X86_REG_INVALID) - add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); - if (op->mem.index != X86_REG_INVALID) - add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index)); - if (op->mem.disp != 0) - add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); - - break; - } - } - - if (sparc->cc != 0) - add_str(&result, " ; Code condition: %u", sparc->cc); - - if (sparc->hint != 0) - add_str(&result, " ; Hint code: %u", sparc->hint); - - return result; -} - diff --git a/suite/cstest/src/systemz_detail.c b/suite/cstest/src/systemz_detail.c deleted file mode 100644 index b9d24a055e..0000000000 --- a/suite/cstest/src/systemz_detail.c +++ /dev/null @@ -1,57 +0,0 @@ -/* Capstone testing regression */ -/* By Do Minh Tuan , 02-2019 */ - - -#include "factory.h" - -char *get_detail_sysz(csh *handle, cs_mode mode, cs_insn *ins) -{ - cs_sysz *sysz; - int i; - char *result; - - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; - - if (ins->detail == NULL) - return result; - - sysz = &(ins->detail->sysz); - if (sysz->op_count) - add_str(&result, " ; op_count: %u", sysz->op_count); - - for (i = 0; i < sysz->op_count; i++) { - cs_sysz_op *op = &(sysz->operands[i]); - switch((int)op->type) { - default: - break; - case SYSZ_OP_REG: - add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); - break; - case SYSZ_OP_ACREG: - add_str(&result, " ; operands[%u].type: ACREG = %u", i, op->reg); - break; - case SYSZ_OP_IMM: - add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm); - break; - case SYSZ_OP_MEM: - add_str(&result, " ; operands[%u].type: MEM", i); - if (op->mem.base != SYSZ_REG_INVALID) - add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); - if (op->mem.index != SYSZ_REG_INVALID) - add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index)); - if (op->mem.length != 0) - add_str(&result, " ; operands[%u].mem.length: 0x%" PRIx64 "", i, op->mem.length); - if (op->mem.disp != 0) - add_str(&result, " ; operands[%u].mem.disp: 0x%" PRIx64 "", i, op->mem.disp); - - break; - } - } - - if (sysz->cc != 0) - add_str(&result, " ; Code condition: %u", sysz->cc); - - return result; -} - diff --git a/suite/cstest/src/test_case.c b/suite/cstest/src/test_case.c new file mode 100644 index 0000000000..cd1ece6bbe --- /dev/null +++ b/suite/cstest/src/test_case.c @@ -0,0 +1,330 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include +#include +#include +#include "cmocka.h" +#include "test_detail.h" +#include "test_case.h" +#include "helper.h" +#include "../../../utils.h" +#include +#include + +TestInput *test_input_new() +{ + TestInput *p = cs_mem_calloc(sizeof(TestInput), 1); + assert(p); + return p; +} + +void test_input_free(TestInput *test_input) +{ + if (!test_input) { + return; + } + cs_mem_free(test_input->name); + cs_mem_free(test_input->bytes); + cs_mem_free(test_input->arch); + for (size_t i = 0; i < test_input->options_count; i++) { + cs_mem_free(test_input->options[i]); + } + cs_mem_free(test_input->options); + cs_mem_free(test_input); +} + +TestInput *test_input_clone(TestInput *test_input) +{ + assert(test_input); + TestInput *ti = test_input_new(); + ti->address = test_input->address; + + for (size_t i = 0; i < test_input->options_count; i++) { + ti->options = cs_mem_realloc( + ti->options, sizeof(char *) * (ti->options_count + 1)); + ti->options[i] = cs_strdup(test_input->options[i]); + ti->options_count++; + } + ti->name = test_input->name ? cs_strdup(test_input->name) : NULL; + ti->arch = cs_strdup(test_input->arch); + ti->bytes = cs_mem_calloc(sizeof(uint8_t), test_input->bytes_count); + ti->bytes_count = test_input->bytes_count; + memcpy(ti->bytes, test_input->bytes, test_input->bytes_count); + return ti; +} + +char *test_input_stringify(const TestInput *test_input, const char *postfix) +{ + size_t msg_len = 2048; + char *msg = cs_mem_calloc(sizeof(char), msg_len); + char *byte_seq = + byte_seq_to_str(test_input->bytes, test_input->bytes_count); + if (!msg) { + return NULL; + } + char opt_seq[128] = { 0 }; + append_to_str(opt_seq, sizeof(opt_seq), "["); + for (size_t i = 0; i < test_input->options_count; ++i) { + append_to_str(opt_seq, sizeof(opt_seq), test_input->options[i]); + if (i < test_input->options_count - 1) { + append_to_str(opt_seq, sizeof(opt_seq), ", "); + } + } + append_to_str(opt_seq, sizeof(opt_seq), "]"); + cs_snprintf(msg, msg_len, + "%sTestInput { arch: %s, options: %s, addr: 0x%" PRIx64 + ", bytes: %s }", + postfix, test_input->arch, opt_seq, test_input->address, + byte_seq); + cs_mem_free(byte_seq); + return msg; +} + +TestInsnData *test_insn_data_new() +{ + TestInsnData *p = cs_mem_calloc(sizeof(TestInsnData), 1); + assert(p); + return p; +} + +void test_insn_data_free(TestInsnData *test_insn_data) +{ + if (!test_insn_data) { + return; + } + cs_mem_free(test_insn_data->asm_text); + cs_mem_free(test_insn_data->op_str); + cs_mem_free(test_insn_data->mnemonic); + test_detail_free(test_insn_data->details); + cs_mem_free(test_insn_data); +} + +TestInsnData *test_insn_data_clone(TestInsnData *test_insn_data) +{ + assert(test_insn_data); + TestInsnData *tid = test_insn_data_new(); + tid->alias_id = test_insn_data->alias_id; + tid->is_alias = test_insn_data->is_alias; + tid->id = test_insn_data->id; + tid->mnemonic = test_insn_data->mnemonic ? + cs_strdup(test_insn_data->mnemonic) : + NULL; + tid->op_str = test_insn_data->op_str ? + cs_strdup(test_insn_data->op_str) : + NULL; + tid->asm_text = test_insn_data->asm_text ? + cs_strdup(test_insn_data->asm_text) : + NULL; + if (test_insn_data->details) { + tid->details = test_detail_clone(test_insn_data->details); + } + return tid; +} + +TestExpected *test_expected_new() +{ + TestExpected *p = cs_mem_calloc(sizeof(TestExpected), 1); + assert(p); + return p; +} + +void test_expected_free(TestExpected *test_expected) +{ + if (!test_expected) { + return; + } + for (size_t i = 0; i < test_expected->insns_count; i++) { + test_insn_data_free(test_expected->insns[i]); + } + cs_mem_free(test_expected->insns); + cs_mem_free(test_expected); +} + +TestExpected *test_expected_clone(TestExpected *test_expected) +{ + assert(test_expected); + TestExpected *te = test_expected_new(); + te->insns = cs_mem_calloc(sizeof(TestInsnData *), + test_expected->insns_count); + for (size_t i = 0; i < test_expected->insns_count; i++) { + te->insns[i] = test_insn_data_clone(test_expected->insns[i]); + te->insns_count++; + } + return te; +} + +/// Compares the given @asm_text to the @expected one. +/// Because Capstone sometimes deviates from the LLVM syntax +/// the strings don't need to be the same to be considered a valid match. +/// E.g. Capstone sometimes prints decimal numbers instead of hexadecimal +/// for readability. +static bool compare_asm_text(const char *asm_text, const char *expected, + size_t arch_bits) +{ + if (!asm_text || !expected) { + fprintf(stderr, "[!] asm_text or expected was NULL\n"); + return false; + } + if (strcmp(asm_text, expected) == 0) { + return true; + } + // Normalize both strings + char asm_copy[MAX_ASM_TXT_MEM] = { 0 }; + strncpy(asm_copy, asm_text, MAX_ASM_TXT_MEM - 1); + trim_str(asm_copy); + replace_hex(asm_copy, sizeof(asm_copy)); + replace_negative(asm_copy, sizeof(asm_copy), arch_bits); + norm_spaces(asm_copy); + str_to_lower(asm_copy); + + char expected_copy[MAX_ASM_TXT_MEM] = { 0 }; + strncpy(expected_copy, expected, MAX_ASM_TXT_MEM - 1); + trim_str(expected_copy); + replace_hex(expected_copy, sizeof(expected_copy)); + replace_negative(expected_copy, sizeof(expected_copy), arch_bits); + norm_spaces(expected_copy); + str_to_lower(expected_copy); + + if (strcmp(asm_copy, expected_copy) == 0) { + return true; + } + + fprintf(stderr, + "Normalized asm-text doesn't match:\n" + "decoded: '%s'\n" + "expected: '%s'\n", + asm_copy, expected_copy); + return false; +} + +/// Compares the decoded instructions @insns against the @expected values and returns the result. +void test_expected_compare(csh *handle, TestExpected *expected, cs_insn *insns, + size_t insns_count, size_t arch_bits) +{ + assert_int_equal(insns_count, expected->insns_count); + for (size_t i = 0; i < insns_count; ++i) { + TestInsnData *expec_data = expected->insns[i]; + // Test mandatory fields first + // The asm text is saved differently for different architectures. + // Either all in op_str or split in mnemonic and op_str + char asm_text[256] = { 0 }; + if (insns[i].mnemonic[0] != '\0') { + append_to_str(asm_text, sizeof(asm_text), + insns[i].mnemonic); + append_to_str(asm_text, sizeof(asm_text), " "); + } + if (insns[i].op_str[0] != '\0') { + append_to_str(asm_text, sizeof(asm_text), + insns[i].op_str); + } + if (!compare_asm_text(asm_text, expec_data->asm_text, + arch_bits)) { + fail_msg("asm-text mismatch\n"); + } + + // Not mandatory fields. If not initialized they should still match. + if (expec_data->id != 0) { + assert_int_equal(insns[i].id, expec_data->id); + } + if (expec_data->is_alias != 0) { + if (expec_data->is_alias > 0) { + assert_true(insns[i].is_alias); + } else { + assert_false(insns[i].is_alias); + } + } + if (expec_data->alias_id != 0) { + assert_int_equal(insns[i].alias_id, + expec_data->alias_id); + } + if (expec_data->mnemonic) { + assert_string_equal(insns[i].mnemonic, + expec_data->mnemonic); + } + if (expec_data->op_str) { + assert_string_equal(insns[i].op_str, + expec_data->op_str); + } + if (expec_data->details) { + if (!insns[i].detail) { + fprintf(stderr, "detail is NULL\n"); + assert_non_null(insns[i].detail); + } + assert_true(test_expected_detail(handle, &insns[i], + expec_data->details)); + } + } +} + +TestCase *test_case_new() +{ + TestCase *p = cs_mem_calloc(sizeof(TestCase), 1); + assert(p); + return p; +} + +void test_case_free(TestCase *test_case) +{ + if (!test_case) { + return; + } + test_input_free(test_case->input); + test_expected_free(test_case->expected); + cs_mem_free(test_case->skip_reason); + cs_mem_free(test_case); +} + +TestCase *test_case_clone(TestCase *test_case) +{ + assert(test_case); + TestCase *tc = test_case_new(); + TestInput *ti = test_input_clone(test_case->input); + tc->input = ti; + TestExpected *te = test_expected_clone(test_case->expected); + tc->expected = te; + tc->skip = test_case->skip; + if (tc->skip) { + tc->skip_reason = strdup(test_case->skip_reason); + } + return tc; +} + +TestFile *test_file_new() +{ + TestFile *p = cs_mem_calloc(sizeof(TestFile), 1); + assert(p); + return p; +} + +void test_file_free(TestFile *test_file) +{ + if (!test_file) { + return; + } + + for (size_t i = 0; i < test_file->test_cases_count; ++i) { + test_case_free(test_file->test_cases[i]); + } + + cs_mem_free(test_file->test_cases); + cs_mem_free(test_file->filename); + test_file->filename = NULL; + cs_mem_free(test_file); +} + +TestFile *test_file_clone(TestFile *test_file) +{ + assert(test_file); + TestFile *tf = test_file_new(); + tf->filename = test_file->filename ? strdup(test_file->filename) : NULL; + tf->test_cases = + cs_mem_calloc(sizeof(TestCase *), test_file->test_cases_count); + + for (size_t i = 0; i < test_file->test_cases_count; + i++, tf->test_cases_count++) { + TestCase *tc = test_case_clone(test_file->test_cases[i]); + tf->test_cases[i] = tc; + } + return tf; +} diff --git a/suite/cstest/src/test_detail.c b/suite/cstest/src/test_detail.c new file mode 100644 index 0000000000..0128217ae3 --- /dev/null +++ b/suite/cstest/src/test_detail.c @@ -0,0 +1,408 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_detail.h" +#include "test_compare.h" +#include + +TestDetail *test_detail_new() +{ + return cs_mem_calloc(sizeof(TestDetail), 1); +} + +TestDetail *test_detail_clone(TestDetail *detail) +{ + assert(detail); + TestDetail *clone = test_detail_new(); + + clone->regs_read = + detail->regs_read_count > 0 ? + cs_mem_calloc(sizeof(char *), detail->regs_read_count) : + NULL; + clone->regs_read_count = detail->regs_read_count; + for (size_t i = 0; i < detail->regs_read_count; ++i) { + clone->regs_read[i] = strdup(detail->regs_read[i]); + } + + clone->regs_write = detail->regs_write_count > 0 ? + cs_mem_calloc(sizeof(char *), + detail->regs_write_count) : + NULL; + clone->regs_write_count = detail->regs_write_count; + for (size_t i = 0; i < detail->regs_write_count; ++i) { + clone->regs_write[i] = strdup(detail->regs_write[i]); + } + + clone->regs_impl_read = + detail->regs_impl_read_count > 0 ? + cs_mem_calloc(sizeof(char *), + detail->regs_impl_read_count) : + NULL; + clone->regs_impl_read_count = detail->regs_impl_read_count; + for (size_t i = 0; i < detail->regs_impl_read_count; ++i) { + clone->regs_impl_read[i] = strdup(detail->regs_impl_read[i]); + } + + clone->regs_impl_write = + detail->regs_impl_write_count > 0 ? + cs_mem_calloc(sizeof(char *), + detail->regs_impl_write_count) : + NULL; + clone->regs_impl_write_count = detail->regs_impl_write_count; + for (size_t i = 0; i < detail->regs_impl_write_count; ++i) { + clone->regs_impl_write[i] = strdup(detail->regs_impl_write[i]); + } + + clone->groups = + detail->groups_count > 0 ? + cs_mem_calloc(sizeof(char *), detail->groups_count) : + NULL; + clone->groups_count = detail->groups_count; + for (size_t i = 0; i < detail->groups_count; ++i) { + clone->groups[i] = strdup(detail->groups[i]); + } + + if (detail->aarch64) { + clone->aarch64 = test_detail_aarch64_clone(detail->aarch64); + } + if (detail->arm) { + clone->arm = test_detail_arm_clone(detail->arm); + } + if (detail->ppc) { + clone->ppc = test_detail_ppc_clone(detail->ppc); + } + if (detail->tricore) { + clone->tricore = test_detail_tricore_clone(detail->tricore); + } + if (detail->alpha) { + clone->alpha = test_detail_alpha_clone(detail->alpha); + } + if (detail->bpf) { + clone->bpf = test_detail_bpf_clone(detail->bpf); + } + if (detail->hppa) { + clone->hppa = test_detail_hppa_clone(detail->hppa); + } + if (detail->xcore) { + clone->xcore = test_detail_xcore_clone(detail->xcore); + } + if (detail->systemz) { + clone->systemz = test_detail_systemz_clone(detail->systemz); + } + if (detail->sparc) { + clone->sparc = test_detail_sparc_clone(detail->sparc); + } + if (detail->sh) { + clone->sh = test_detail_sh_clone(detail->sh); + } + if (detail->mips) { + clone->mips = test_detail_mips_clone(detail->mips); + } + if (detail->riscv) { + clone->riscv = test_detail_riscv_clone(detail->riscv); + } + if (detail->m680x) { + clone->m680x = test_detail_m680x_clone(detail->m680x); + } + if (detail->tms320c64x) { + clone->tms320c64x = + test_detail_tms320c64x_clone(detail->tms320c64x); + } + if (detail->mos65xx) { + clone->mos65xx = test_detail_mos65xx_clone(detail->mos65xx); + } + if (detail->evm) { + clone->evm = test_detail_evm_clone(detail->evm); + } + if (detail->loongarch) { + clone->loongarch = + test_detail_loongarch_clone(detail->loongarch); + } + if (detail->wasm) { + clone->wasm = test_detail_wasm_clone(detail->wasm); + } + if (detail->x86) { + clone->x86 = test_detail_x86_clone(detail->x86); + } + if (detail->m68k) { + clone->m68k = test_detail_m68k_clone(detail->m68k); + } + + return clone; +} + +void test_detail_free(TestDetail *detail) +{ + if (!detail) { + return; + } + + for (size_t i = 0; i < detail->regs_read_count; ++i) { + cs_mem_free(detail->regs_read[i]); + } + cs_mem_free(detail->regs_read); + + for (size_t i = 0; i < detail->regs_write_count; ++i) { + cs_mem_free(detail->regs_write[i]); + } + cs_mem_free(detail->regs_write); + + for (size_t i = 0; i < detail->regs_impl_read_count; ++i) { + cs_mem_free(detail->regs_impl_read[i]); + } + cs_mem_free(detail->regs_impl_read); + + for (size_t i = 0; i < detail->regs_impl_write_count; ++i) { + cs_mem_free(detail->regs_impl_write[i]); + } + cs_mem_free(detail->regs_impl_write); + + for (size_t i = 0; i < detail->groups_count; ++i) { + cs_mem_free(detail->groups[i]); + } + cs_mem_free(detail->groups); + + if (detail->aarch64) { + test_detail_aarch64_free(detail->aarch64); + } + if (detail->arm) { + test_detail_arm_free(detail->arm); + } + if (detail->ppc) { + test_detail_ppc_free(detail->ppc); + } + if (detail->tricore) { + test_detail_tricore_free(detail->tricore); + } + if (detail->alpha) { + test_detail_alpha_free(detail->alpha); + } + if (detail->hppa) { + test_detail_hppa_free(detail->hppa); + } + if (detail->bpf) { + test_detail_bpf_free(detail->bpf); + } + if (detail->xcore) { + test_detail_xcore_free(detail->xcore); + } + if (detail->systemz) { + test_detail_systemz_free(detail->systemz); + } + if (detail->sparc) { + test_detail_sparc_free(detail->sparc); + } + if (detail->sh) { + test_detail_sh_free(detail->sh); + } + if (detail->mips) { + test_detail_mips_free(detail->mips); + } + if (detail->riscv) { + test_detail_riscv_free(detail->riscv); + } + if (detail->m680x) { + test_detail_m680x_free(detail->m680x); + } + if (detail->tms320c64x) { + test_detail_tms320c64x_free(detail->tms320c64x); + } + if (detail->mos65xx) { + test_detail_mos65xx_free(detail->mos65xx); + } + if (detail->evm) { + test_detail_evm_free(detail->evm); + } + if (detail->loongarch) { + test_detail_loongarch_free(detail->loongarch); + } + if (detail->wasm) { + test_detail_wasm_free(detail->wasm); + } + if (detail->x86) { + test_detail_x86_free(detail->x86); + } + if (detail->m68k) { + test_detail_m68k_free(detail->m68k); + } + + cs_mem_free(detail); +} + +static bool test_reg_rw_access(csh *handle, const cs_insn *insn, + TestDetail *expected) +{ + assert(handle && insn && expected); + if (expected->regs_read_count <= 0 && expected->regs_write_count <= 0) { + return true; + } + + cs_regs regs_read, regs_write; + uint8_t regs_read_count, regs_write_count; + cs_err err = cs_regs_access(*handle, insn, regs_read, ®s_read_count, + regs_write, ®s_write_count); + if (err != CS_ERR_OK) { + fprintf(stderr, "cs_regs_access() failed with '%s'\n", + cs_strerror(err)); + return false; + } + + if (expected->regs_read_count > 0) { + compare_uint32_ret(regs_read_count, expected->regs_read_count, + false); + for (size_t i = 0; i < regs_read_count; ++i) { + compare_reg_ret(*handle, regs_read[i], + expected->regs_read[i], false); + } + } + + if (expected->regs_write_count > 0) { + compare_uint32_ret(regs_write_count, expected->regs_write_count, + false); + for (size_t i = 0; i < regs_write_count; ++i) { + compare_reg_ret(*handle, regs_write[i], + expected->regs_write[i], false); + } + } + return true; +} + +static bool test_impl_reg_rw_access(csh *handle, const cs_insn *insn, + TestDetail *expected) +{ + assert(handle && insn && expected); + if (expected->regs_impl_read_count <= 0 && + expected->regs_impl_write_count <= 0) { + return true; + } + cs_detail *actual = insn->detail; + + // Test exclusively the implicitly read or written register. + if (expected->regs_impl_read_count > 0) { + compare_uint32_ret(actual->regs_read_count, + expected->regs_impl_read_count, false); + for (size_t i = 0; i < actual->regs_read_count; ++i) { + compare_reg_ret(*handle, actual->regs_read[i], + expected->regs_impl_read[i], false); + } + } + + if (expected->regs_impl_write_count > 0) { + compare_uint32_ret(actual->regs_write_count, + expected->regs_impl_write_count, false); + for (size_t i = 0; i < actual->regs_write_count; ++i) { + compare_reg_ret(*handle, actual->regs_write[i], + expected->regs_impl_write[i], false); + } + } + return true; +} + +bool test_expected_detail(csh *handle, const cs_insn *insn, + TestDetail *expected) +{ + assert(handle && insn && insn->detail && expected); + cs_detail *actual = insn->detail; + + if (!test_reg_rw_access(handle, insn, expected)) { + return false; + } + + if (!test_impl_reg_rw_access(handle, insn, expected)) { + return false; + } + + if (expected->groups_count > 0) { + compare_uint32_ret(actual->groups_count, expected->groups_count, + false); + for (size_t i = 0; i < actual->groups_count; ++i) { + if (strings_match(cs_group_name(*handle, + actual->groups[i]), + expected->groups[i])) { + continue; + } + compare_enum_ret(actual->groups[i], expected->groups[i], + false); + } + } + + if (expected->aarch64) { + return test_expected_aarch64(handle, &actual->aarch64, + expected->aarch64); + } + if (expected->arm) { + return test_expected_arm(handle, &actual->arm, expected->arm); + } + if (expected->ppc) { + return test_expected_ppc(handle, &actual->ppc, expected->ppc); + } + if (expected->tricore) { + return test_expected_tricore(handle, &actual->tricore, + expected->tricore); + } + if (expected->alpha) { + return test_expected_alpha(handle, &actual->alpha, + expected->alpha); + } + if (expected->bpf) { + return test_expected_bpf(handle, &actual->bpf, expected->bpf); + } + if (expected->hppa) { + return test_expected_hppa(handle, &actual->hppa, + expected->hppa); + } + if (expected->xcore) { + return test_expected_xcore(handle, &actual->xcore, + expected->xcore); + } + if (expected->systemz) { + return test_expected_systemz(handle, &actual->sysz, + expected->systemz); + } + if (expected->sparc) { + return test_expected_sparc(handle, &actual->sparc, + expected->sparc); + } + if (expected->sh) { + return test_expected_sh(handle, &actual->sh, expected->sh); + } + if (expected->mips) { + return test_expected_mips(handle, &actual->mips, + expected->mips); + } + if (expected->riscv) { + return test_expected_riscv(handle, &actual->riscv, + expected->riscv); + } + if (expected->m680x) { + return test_expected_m680x(handle, &actual->m680x, + expected->m680x); + } + if (expected->tms320c64x) { + return test_expected_tms320c64x(handle, &actual->tms320c64x, + expected->tms320c64x); + } + if (expected->mos65xx) { + return test_expected_mos65xx(handle, &actual->mos65xx, + expected->mos65xx); + } + if (expected->evm) { + return test_expected_evm(handle, &actual->evm, expected->evm); + } + if (expected->loongarch) { + return test_expected_loongarch(handle, &actual->loongarch, + expected->loongarch); + } + if (expected->wasm) { + return test_expected_wasm(handle, &actual->wasm, + expected->wasm); + } + if (expected->x86) { + return test_expected_x86(handle, &actual->x86, expected->x86); + } + if (expected->m68k) { + return test_expected_m68k(handle, &actual->m68k, + expected->m68k); + } + return true; +} diff --git a/suite/cstest/src/test_detail_aarch64.c b/suite/cstest/src/test_detail_aarch64.c new file mode 100644 index 0000000000..d87e1ec779 --- /dev/null +++ b/suite/cstest/src/test_detail_aarch64.c @@ -0,0 +1,256 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_compare.h" +#include "test_detail_aarch64.h" +#include +#include +#include + +TestDetailAArch64 *test_detail_aarch64_new() +{ + return cs_mem_calloc(sizeof(TestDetailAArch64), 1); +} + +void test_detail_aarch64_free(TestDetailAArch64 *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_aarch64_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail->cc); + cs_mem_free(detail); +} + +TestDetailAArch64 *test_detail_aarch64_clone(TestDetailAArch64 *detail) +{ + TestDetailAArch64 *clone = test_detail_aarch64_new(); + clone->cc = detail->cc ? strdup(detail->cc) : NULL; + clone->update_flags = detail->update_flags; + clone->post_indexed = detail->post_indexed; + + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailAArch64Op *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_aarch64_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailAArch64Op *test_detail_aarch64_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailAArch64Op), 1); +} + +TestDetailAArch64Op *test_detail_aarch64_op_clone(TestDetailAArch64Op *op) +{ + TestDetailAArch64Op *clone = test_detail_aarch64_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->sub_type = op->sub_type ? strdup(op->sub_type) : NULL; + clone->access = op->access ? strdup(op->access) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL; + clone->mem_index = op->mem_index ? strdup(op->mem_index) : NULL; + clone->shift_type = op->shift_type ? strdup(op->shift_type) : NULL; + clone->ext = op->ext ? strdup(op->ext) : NULL; + clone->vas = op->vas ? strdup(op->vas) : NULL; + clone->imm = op->imm; + clone->sme = op->sme ? test_detail_aarch64_op_sme_clone(op->sme) : NULL; + clone->pred_reg = op->pred_reg ? strdup(op->pred_reg) : NULL; + clone->pred_vec_select = + op->pred_vec_select ? strdup(op->pred_vec_select) : NULL; + clone->pred_imm_index = op->pred_imm_index; + clone->pred_imm_index_set = op->pred_imm_index_set; + clone->mem_disp = op->mem_disp; + clone->imm_range_first = op->imm_range_first; + clone->imm_range_offset = op->imm_range_offset; + clone->fp = op->fp; + clone->sys_raw_val = op->sys_raw_val; + clone->shift_value = op->shift_value; + clone->is_vreg = op->is_vreg; + clone->vector_index = op->vector_index; + clone->vector_index_is_set = op->vector_index_is_set; + clone->is_list_member = op->is_list_member; + + return clone; +} + +void test_detail_aarch64_op_free(TestDetailAArch64Op *op) +{ + if (!op) { + return; + } + test_detail_aarch64_op_sme_free(op->sme); + cs_mem_free(op->type); + cs_mem_free(op->sub_type); + cs_mem_free(op->access); + cs_mem_free(op->reg); + cs_mem_free(op->mem_base); + cs_mem_free(op->mem_index); + cs_mem_free(op->shift_type); + cs_mem_free(op->ext); + cs_mem_free(op->vas); + cs_mem_free(op->pred_reg); + cs_mem_free(op->pred_vec_select); + cs_mem_free(op); +} + +TestDetailAArch64SME *test_detail_aarch64_op_sme_new() +{ + return cs_mem_calloc(sizeof(TestDetailAArch64SME), 1); +} + +TestDetailAArch64SME *test_detail_aarch64_op_sme_clone(TestDetailAArch64SME *sme) +{ + TestDetailAArch64SME *clone = test_detail_aarch64_op_sme_new(); + + clone->type = sme->type ? strdup(sme->type) : NULL; + clone->tile = sme->tile ? strdup(sme->tile) : NULL; + clone->slice_reg = sme->slice_reg ? strdup(sme->slice_reg) : NULL; + clone->slice_offset_imm = sme->slice_offset_imm; + clone->slice_offset_ir_first = sme->slice_offset_ir_first; + clone->slice_offset_ir_offset = sme->slice_offset_ir_offset; + clone->slice_offset_ir_set = sme->slice_offset_ir_set; + clone->has_range_offset = sme->has_range_offset; + clone->is_vertical = sme->is_vertical; + + return clone; +} + +void test_detail_aarch64_op_sme_free(TestDetailAArch64SME *sme) +{ + if (!sme) { + return; + } + cs_mem_free(sme->type); + cs_mem_free(sme->tile); + cs_mem_free(sme->slice_reg); + cs_mem_free(sme); +} + +bool test_expected_aarch64(csh *handle, cs_aarch64 *actual, + TestDetailAArch64 *expected) +{ + assert(handle && actual && expected); + + compare_enum_ret(actual->cc, expected->cc, false); + compare_tbool_ret(actual->update_flags, expected->update_flags, false); + compare_tbool_ret(actual->post_index, expected->post_indexed, false); + + if (expected->operands_count == 0) { + return true; + } + compare_uint8_ret(actual->op_count, expected->operands_count, false); + for (size_t i = 0; i < actual->op_count; ++i) { + cs_aarch64_op *op = &actual->operands[i]; + TestDetailAArch64Op *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + compare_enum_ret(op->access, eop->access, false); + switch (op->type) { + default: + fprintf(stderr, + "AArch64 op type %" PRId32 " not handled.\n", + op->type); + return false; + case AARCH64_OP_REG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case AARCH64_OP_IMM: + compare_int64_ret(op->imm, eop->imm, false); + break; + case AARCH64_OP_IMM_RANGE: + compare_int8_ret(op->imm_range.first, + eop->imm_range_first, false); + compare_int8_ret(op->imm_range.offset, + eop->imm_range_offset, false); + break; + case AARCH64_OP_FP: + compare_fp_ret(op->fp, eop->fp, false); + break; + case AARCH64_OP_SYSREG: + compare_enum_ret(op->sysop.sub_type, eop->sub_type, + false); + compare_uint64_ret(op->sysop.reg.raw_val, + eop->sys_raw_val, false); + break; + case AARCH64_OP_SYSIMM: + compare_enum_ret(op->sysop.sub_type, eop->sub_type, + false); + compare_uint64_ret(op->sysop.imm.raw_val, + eop->sys_raw_val, false); + break; + case AARCH64_OP_SYSALIAS: + compare_enum_ret(op->sysop.sub_type, eop->sub_type, + false); + compare_uint64_ret(op->sysop.alias.raw_val, + eop->sys_raw_val, false); + break; + case AARCH64_OP_MEM: + compare_reg_ret(*handle, op->mem.base, eop->mem_base, + false); + compare_reg_ret(*handle, op->mem.index, eop->mem_index, + false); + compare_int32_ret(op->mem.disp, eop->mem_disp, false); + break; + case AARCH64_OP_PRED: + compare_reg_ret(*handle, op->pred.reg, eop->pred_reg, + false); + compare_reg_ret(*handle, op->pred.vec_select, eop->pred_vec_select, + false); + if (eop->pred_imm_index_set) { + compare_int32_ret(op->pred.imm_index, eop->pred_imm_index, false); + } else { + assert(eop->pred_imm_index == 0); + } + break; + case AARCH64_OP_SME: + compare_enum_ret(op->sme.type, eop->sme->type, + false); + compare_reg_ret(*handle, op->sme.tile, eop->sme->tile, + false); + compare_reg_ret(*handle, op->sme.slice_reg, eop->sme->slice_reg, + false); + compare_tbool_ret(op->sme.has_range_offset, eop->sme->has_range_offset, + false); + compare_tbool_ret(op->sme.is_vertical, eop->sme->is_vertical, + false); + if (eop->sme->slice_offset_imm) { + compare_int32_ret(op->sme.slice_offset.imm, eop->sme->slice_offset_imm, false); + } + if (eop->sme->slice_offset_ir_set) { + compare_int32_ret(op->sme.slice_offset.imm_range.first, eop->sme->slice_offset_ir_first, false); + compare_int32_ret(op->sme.slice_offset.imm_range.offset, eop->sme->slice_offset_ir_offset, false); + } else { + assert(eop->sme->slice_offset_ir_first == 0 && eop->sme->slice_offset_ir_offset == 0); + } + break; + } + + compare_enum_ret(op->shift.type, eop->shift_type, false); + compare_uint32_ret(op->shift.value, eop->shift_value, false); + compare_enum_ret(op->ext, eop->ext, false); + + compare_enum_ret(op->vas, eop->vas, false); + compare_tbool_ret(op->is_vreg, eop->is_vreg, false); + if (eop->vector_index_is_set) { + compare_int32_ret(op->vector_index, eop->vector_index, + false); + } else { + assert(eop->vector_index == 0); + } + + compare_tbool_ret(op->is_list_member, eop->is_list_member, + false); + } + + return true; +} diff --git a/suite/cstest/src/test_detail_alpha.c b/suite/cstest/src/test_detail_alpha.c new file mode 100644 index 0000000000..0fce65a27a --- /dev/null +++ b/suite/cstest/src/test_detail_alpha.c @@ -0,0 +1,99 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_compare.h" +#include "test_detail_alpha.h" +#include +#include +#include + +TestDetailAlpha *test_detail_alpha_new() +{ + return cs_mem_calloc(sizeof(TestDetailAlpha), 1); +} + +void test_detail_alpha_free(TestDetailAlpha *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_alpha_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail); +} + +TestDetailAlpha *test_detail_alpha_clone(const TestDetailAlpha *detail) +{ + TestDetailAlpha *clone = test_detail_alpha_new(); + + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailAlphaOp *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_alpha_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailAlphaOp *test_detail_alpha_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailAlphaOp), 1); +} + +TestDetailAlphaOp *test_detail_alpha_op_clone(const TestDetailAlphaOp *op) +{ + TestDetailAlphaOp *clone = test_detail_alpha_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->access = op->access ? strdup(op->access) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->imm = op->imm; + + return clone; +} + +void test_detail_alpha_op_free(TestDetailAlphaOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->access); + cs_mem_free(op->reg); + cs_mem_free(op); +} + +bool test_expected_alpha(csh *handle, const cs_alpha *actual, + const TestDetailAlpha *expected) +{ + assert(handle && actual && expected); + + compare_uint8_ret(actual->op_count, expected->operands_count, false); + for (size_t i = 0; i < actual->op_count; ++i) { + const cs_alpha_op *op = &actual->operands[i]; + TestDetailAlphaOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + compare_enum_ret(op->access, eop->access, false); + switch (op->type) { + default: + fprintf(stderr, + "alpha op type %" PRId32 " not handled.\n", + op->type); + return false; + case ALPHA_OP_REG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case ALPHA_OP_IMM: + compare_int32_ret(op->imm, eop->imm, false); + break; + } + } + + return true; +} diff --git a/suite/cstest/src/test_detail_arm.c b/suite/cstest/src/test_detail_arm.c new file mode 100644 index 0000000000..090cafeaad --- /dev/null +++ b/suite/cstest/src/test_detail_arm.c @@ -0,0 +1,256 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_compare.h" +#include "test_detail_arm.h" +#include +#include +#include + +TestDetailARM *test_detail_arm_new() +{ + return cs_mem_calloc(sizeof(TestDetailARM), 1); +} + +void test_detail_arm_free(TestDetailARM *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_arm_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail->vector_data); + cs_mem_free(detail->cps_mode); + cs_mem_free(detail->cps_flag); + cs_mem_free(detail->cc); + cs_mem_free(detail->vcc); + cs_mem_free(detail->mem_barrier); + cs_mem_free(detail); +} + +TestDetailARM *test_detail_arm_clone(TestDetailARM *detail) +{ + TestDetailARM *clone = test_detail_arm_new(); + clone->update_flags = detail->update_flags; + clone->post_indexed = detail->post_indexed; + clone->vector_data = detail->vector_data ? strdup(detail->vector_data) : NULL; + clone->cps_mode = detail->cps_mode ? strdup(detail->cps_mode) : NULL; + clone->cps_flag = detail->cps_flag ? strdup(detail->cps_flag) : NULL; + clone->cc = detail->cc ? strdup(detail->cc) : NULL; + clone->vcc = detail->vcc ? strdup(detail->vcc) : NULL; + clone->mem_barrier = detail->mem_barrier ? strdup(detail->mem_barrier) : NULL; + + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailARMOp *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_arm_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailARMOp *test_detail_arm_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailARMOp), 1); +} + +TestDetailARMOp *test_detail_arm_op_clone(TestDetailARMOp *op) +{ + TestDetailARMOp *clone = test_detail_arm_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->access = op->access ? strdup(op->access) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->imm = op->imm; + clone->setend = op->setend ? strdup(op->setend) : NULL; + clone->pred = op->pred; + clone->fp = op->fp; + clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL; + clone->mem_index = op->mem_index ? strdup(op->mem_index) : NULL; + clone->mem_scale = op->mem_scale; + clone->mem_disp = op->mem_disp; + clone->mem_align = op->mem_align; + clone->sys_reg = op->sys_reg ? strdup(op->sys_reg) : NULL; + clone->sys_psr_bits_count = op->sys_psr_bits_count; + clone->sys_psr_bits = + op->sys_psr_bits_count == 0 ? + NULL : + cs_mem_calloc(sizeof(char *), op->sys_psr_bits_count); + for (size_t i = 0; i < op->sys_psr_bits_count; ++i) { + clone->sys_psr_bits[i] = strdup(op->sys_psr_bits[i]); + } + clone->sys_sysm = op->sys_sysm; + clone->sys_msr_mask = op->sys_msr_mask; + clone->shift_type = op->shift_type ? strdup(op->shift_type) : NULL; + clone->shift_value = op->shift_value; + clone->neon_lane = op->neon_lane; + clone->vector_index = op->vector_index; + clone->vector_index_is_set = op->vector_index_is_set; + clone->subtracted = op->subtracted; + + return clone; +} + +void test_detail_arm_op_free(TestDetailARMOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->access); + cs_mem_free(op->reg); + cs_mem_free(op->setend); + cs_mem_free(op->mem_base); + cs_mem_free(op->mem_index); + cs_mem_free(op->shift_type); + cs_mem_free(op->sys_reg); + if (op->sys_psr_bits_count != 0) { + for (size_t i = 0; i < op->sys_psr_bits_count; ++i) { + cs_mem_free(op->sys_psr_bits[i]); + } + cs_mem_free(op->sys_psr_bits); + } + cs_mem_free(op); +} + +bool test_expected_arm(csh *handle, cs_arm *actual, TestDetailARM *expected) +{ + assert(handle && actual && expected); + + if (expected->vector_size) { + compare_int_ret(actual->vector_size, expected->vector_size, + false); + } + compare_enum_ret(actual->vector_data, expected->vector_data, false); + compare_enum_ret(actual->cps_flag, expected->cps_flag, false); + compare_enum_ret(actual->cps_mode, expected->cps_mode, false); + compare_enum_ret(actual->cc, expected->cc, false); + compare_enum_ret(actual->vcc, expected->vcc, false); + compare_enum_ret(actual->mem_barrier, expected->mem_barrier, false); + if (expected->pred_mask) { + compare_uint8_ret(actual->pred_mask, expected->pred_mask, + false); + } + compare_tbool_ret(actual->usermode, expected->usermode, false); + compare_tbool_ret(actual->update_flags, expected->update_flags, false); + compare_tbool_ret(actual->post_index, expected->post_indexed, false); + + if (expected->operands_count == 0) { + return true; + } + compare_uint8_ret(actual->op_count, expected->operands_count, false); + for (size_t i = 0; i < actual->op_count; ++i) { + cs_arm_op *op = &actual->operands[i]; + TestDetailARMOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + compare_enum_ret(op->access, eop->access, false); + switch (op->type) { + default: + fprintf(stderr, + "arm op type %" PRId32 " not handled.\n", + op->type); + return false; + case ARM_OP_REG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case ARM_OP_IMM: + case ARM_OP_PIMM: + case ARM_OP_CIMM: + compare_int64_ret(op->imm, eop->imm, false); + break; + case ARM_OP_PRED: + compare_int_ret(op->pred, eop->pred, false); + break; + case ARM_OP_SETEND: + compare_enum_ret(op->setend, eop->setend, false); + break; + case ARM_OP_FP: + compare_fp_ret(op->fp, eop->fp, false); + break; + case ARM_OP_SYSREG: + compare_enum_ret(op->sysop.reg.mclasssysreg, + eop->sys_reg, false); + if (eop->sys_sysm) { + compare_uint16_ret(op->sysop.sysm, + eop->sys_sysm, false); + } + if (eop->sys_msr_mask) { + compare_uint8_ret(op->sysop.msr_mask, + eop->sys_msr_mask, false); + } + break; + case ARM_OP_BANKEDREG: + compare_enum_ret(op->sysop.reg.bankedreg, eop->sys_reg, + false); + if (eop->sys_sysm) { + compare_uint16_ret(op->sysop.sysm, + eop->sys_sysm, false); + } + if (eop->sys_msr_mask) { + compare_uint8_ret(op->sysop.msr_mask, + eop->sys_msr_mask, false); + } + break; + case ARM_OP_SPSR: + case ARM_OP_CPSR: + compare_bit_flags_ret(op->sysop.psr_bits, + eop->sys_psr_bits, + eop->sys_psr_bits_count, false); + if (eop->sys_sysm) { + compare_uint16_ret(op->sysop.sysm, + eop->sys_sysm, false); + } + if (eop->sys_msr_mask) { + compare_uint8_ret(op->sysop.msr_mask, + eop->sys_msr_mask, false); + } + break; + case ARM_OP_SYSM: + if (eop->sys_sysm) { + compare_uint16_ret(op->sysop.sysm, + eop->sys_sysm, false); + } + if (eop->sys_msr_mask) { + compare_uint8_ret(op->sysop.msr_mask, + eop->sys_msr_mask, false); + } + break; + case ARM_OP_MEM: + compare_reg_ret(*handle, op->mem.base, eop->mem_base, + false); + compare_reg_ret(*handle, op->mem.index, eop->mem_index, + false); + compare_int_ret(op->mem.disp, eop->mem_disp, false); + compare_uint_ret(op->mem.align, eop->mem_align, false); + if (eop->mem_scale) { + compare_int_ret(op->mem.scale, eop->mem_scale, false); + } + break; + } + + compare_enum_ret(op->shift.type, eop->shift_type, false); + if (eop->shift_value) { + compare_uint32_ret(op->shift.value, eop->shift_value, + false); + } + if (eop->neon_lane) { + compare_uint8_ret(op->neon_lane, eop->neon_lane, false); + } + + if (eop->vector_index_is_set) { + compare_int32_ret(op->vector_index, eop->vector_index, + false); + } else { + assert(eop->vector_index == 0); + } + compare_tbool_ret(op->subtracted, eop->subtracted, false); + } + + return true; +} diff --git a/suite/cstest/src/test_detail_bpf.c b/suite/cstest/src/test_detail_bpf.c new file mode 100644 index 0000000000..e84ee541b6 --- /dev/null +++ b/suite/cstest/src/test_detail_bpf.c @@ -0,0 +1,125 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "capstone/bpf.h" +#include "test_compare.h" +#include "test_detail_bpf.h" +#include +#include +#include + +TestDetailBPF *test_detail_bpf_new() +{ + return cs_mem_calloc(sizeof(TestDetailBPF), 1); +} + +void test_detail_bpf_free(TestDetailBPF *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_bpf_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail); +} + +TestDetailBPF *test_detail_bpf_clone(const TestDetailBPF *detail) +{ + TestDetailBPF *clone = test_detail_bpf_new(); + + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailBPFOp *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_bpf_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailBPFOp *test_detail_bpf_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailBPFOp), 1); +} + +TestDetailBPFOp *test_detail_bpf_op_clone(const TestDetailBPFOp *op) +{ + TestDetailBPFOp *clone = test_detail_bpf_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->access = op->access ? strdup(op->access) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->imm = op->imm; + clone->off = op->off; + clone->mmem = op->mmem; + clone->msh = op->msh; + clone->ext = op->ext ? strdup(op->ext) : NULL; + clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL; + clone->mem_disp = op->mem_disp; + + return clone; +} + +void test_detail_bpf_op_free(TestDetailBPFOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->access); + cs_mem_free(op->reg); + cs_mem_free(op->ext); + cs_mem_free(op->mem_base); + cs_mem_free(op); +} + +bool test_expected_bpf(csh *handle, const cs_bpf *actual, + const TestDetailBPF *expected) +{ + assert(handle && actual && expected); + + compare_uint8_ret(actual->op_count, expected->operands_count, false); + for (size_t i = 0; i < actual->op_count; ++i) { + const cs_bpf_op *op = &actual->operands[i]; + TestDetailBPFOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + compare_enum_ret(op->access, eop->access, false); + switch (op->type) { + default: + fprintf(stderr, + "bpf op type %" PRId32 " not handled.\n", + op->type); + return false; + case BPF_OP_REG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case BPF_OP_IMM: + compare_uint64_ret(op->imm, eop->imm, false); + break; + case BPF_OP_OFF: + compare_uint32_ret(op->off, eop->off, false); + break; + case BPF_OP_MMEM: + compare_uint32_ret(op->mmem, eop->mmem, false); + break; + case BPF_OP_MSH: + compare_uint32_ret(op->msh, eop->msh, false); + break; + case BPF_OP_EXT: + compare_enum_ret(op->ext, eop->ext, false); + break; + case BPF_OP_MEM: + compare_reg_ret(*handle, op->mem.base, eop->mem_base, + false); + compare_uint32_ret(op->mem.disp, eop->mem_disp, false); + break; + } + } + + return true; +} diff --git a/suite/cstest/src/test_detail_evm.c b/suite/cstest/src/test_detail_evm.c new file mode 100644 index 0000000000..53a14da2ac --- /dev/null +++ b/suite/cstest/src/test_detail_evm.c @@ -0,0 +1,40 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_compare.h" +#include "test_detail_evm.h" +#include + +TestDetailEVM *test_detail_evm_new() +{ + return cs_mem_calloc(sizeof(TestDetailEVM), 1); +} + +void test_detail_evm_free(TestDetailEVM *detail) +{ + if (!detail) { + return; + } + cs_mem_free(detail); +} + +TestDetailEVM *test_detail_evm_clone(const TestDetailEVM *detail) +{ + TestDetailEVM *clone = test_detail_evm_new(); + clone->fee = detail->fee; + clone->pop = detail->pop; + clone->push = detail->push; + return clone; +} + +bool test_expected_evm(csh *handle, const cs_evm *actual, + const TestDetailEVM *expected) +{ + assert(handle && actual && expected); + + compare_uint8_ret(actual->fee, expected->fee, false); + compare_uint8_ret(actual->pop, expected->pop, false); + compare_uint8_ret(actual->push, expected->push, false); + + return true; +} diff --git a/suite/cstest/src/test_detail_hppa.c b/suite/cstest/src/test_detail_hppa.c new file mode 100644 index 0000000000..6a9a1410e6 --- /dev/null +++ b/suite/cstest/src/test_detail_hppa.c @@ -0,0 +1,118 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "capstone/hppa.h" +#include "test_compare.h" +#include "test_detail_hppa.h" +#include +#include +#include + +TestDetailHPPA *test_detail_hppa_new() +{ + return cs_mem_calloc(sizeof(TestDetailHPPA), 1); +} + +void test_detail_hppa_free(TestDetailHPPA *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_hppa_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail); +} + +TestDetailHPPA *test_detail_hppa_clone(const TestDetailHPPA *detail) +{ + TestDetailHPPA *clone = test_detail_hppa_new(); + + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailHPPAOp *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_hppa_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailHPPAOp *test_detail_hppa_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailHPPAOp), 1); +} + +TestDetailHPPAOp *test_detail_hppa_op_clone(const TestDetailHPPAOp *op) +{ + TestDetailHPPAOp *clone = test_detail_hppa_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->access = op->access ? strdup(op->access) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->imm = op->imm; + clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL; + clone->mem_space = op->mem_space ? strdup(op->mem_space) : NULL; + clone->mem_base_access = + op->mem_base_access ? strdup(op->mem_base_access) : NULL; + + return clone; +} + +void test_detail_hppa_op_free(TestDetailHPPAOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->access); + cs_mem_free(op->reg); + cs_mem_free(op->mem_base); + cs_mem_free(op->mem_base_access); + cs_mem_free(op->mem_space); + cs_mem_free(op); +} + +bool test_expected_hppa(csh *handle, const cs_hppa *actual, + const TestDetailHPPA *expected) +{ + assert(handle && actual && expected); + + compare_uint8_ret(actual->op_count, expected->operands_count, false); + for (size_t i = 0; i < actual->op_count; ++i) { + const cs_hppa_op *op = &actual->operands[i]; + TestDetailHPPAOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + compare_enum_ret(op->access, eop->access, false); + switch (op->type) { + default: + fprintf(stderr, + "hppa op type %" PRId32 " not handled.\n", + op->type); + return false; + case HPPA_OP_REG: + case HPPA_OP_IDX_REG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case HPPA_OP_DISP: + case HPPA_OP_IMM: + case HPPA_OP_TARGET: + compare_int64_ret(op->imm, eop->imm, false); + break; + case HPPA_OP_MEM: + compare_reg_ret(*handle, op->mem.base, eop->mem_base, + false); + compare_reg_ret(*handle, op->mem.space, eop->mem_space, + false); + compare_enum_ret(op->mem.base_access, + eop->mem_base_access, false); + break; + } + } + + return true; +} diff --git a/suite/cstest/src/test_detail_loongarch.c b/suite/cstest/src/test_detail_loongarch.c new file mode 100644 index 0000000000..3a86bbcf63 --- /dev/null +++ b/suite/cstest/src/test_detail_loongarch.c @@ -0,0 +1,114 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_compare.h" +#include "test_detail_loongarch.h" +#include +#include +#include + +TestDetailLoongArch *test_detail_loongarch_new() +{ + return cs_mem_calloc(sizeof(TestDetailLoongArch), 1); +} + +void test_detail_loongarch_free(TestDetailLoongArch *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_loongarch_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail->format); + cs_mem_free(detail); +} + +TestDetailLoongArch * +test_detail_loongarch_clone(const TestDetailLoongArch *detail) +{ + TestDetailLoongArch *clone = test_detail_loongarch_new(); + + clone->format = detail->format ? strdup(detail->format) : NULL; + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailLoongArchOp *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_loongarch_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailLoongArchOp *test_detail_loongarch_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailLoongArchOp), 1); +} + +TestDetailLoongArchOp * +test_detail_loongarch_op_clone(const TestDetailLoongArchOp *op) +{ + TestDetailLoongArchOp *clone = test_detail_loongarch_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->access = op->access ? strdup(op->access) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->imm = op->imm; + clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL; + clone->mem_disp = op->mem_disp; + + return clone; +} + +void test_detail_loongarch_op_free(TestDetailLoongArchOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->access); + cs_mem_free(op->reg); + cs_mem_free(op->mem_base); + cs_mem_free(op); +} + +bool test_expected_loongarch(csh *handle, const cs_loongarch *actual, + const TestDetailLoongArch *expected) +{ + assert(handle && actual && expected); + + compare_uint8_ret(actual->op_count, expected->operands_count, false); + compare_enum_ret(actual->format, expected->format, false); + for (size_t i = 0; i < actual->op_count; ++i) { + const cs_loongarch_op *op = &actual->operands[i]; + TestDetailLoongArchOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + compare_enum_ret(op->access, eop->access, false); + switch (op->type) { + default: + fprintf(stderr, + "loongarch op type %" PRId32 " not handled.\n", + op->type); + return false; + case LOONGARCH_OP_REG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case LOONGARCH_OP_IMM: + compare_uint64_ret(op->imm, eop->imm, false); + break; + case LOONGARCH_OP_MEM: + compare_reg_ret(*handle, op->mem.base, eop->mem_base, + false); + compare_reg_ret(*handle, op->mem.index, eop->mem_index, + false); + compare_int64_ret(op->mem.disp, eop->mem_disp, false); + break; + } + } + + return true; +} diff --git a/suite/cstest/src/test_detail_m680x.c b/suite/cstest/src/test_detail_m680x.c new file mode 100644 index 0000000000..c2d748ff42 --- /dev/null +++ b/suite/cstest/src/test_detail_m680x.c @@ -0,0 +1,215 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_compare.h" +#include "test_detail_m680x.h" +#include +#include +#include + +TestDetailM680xIdx *test_detail_m680x_idx_new() +{ + return cs_mem_calloc(sizeof(TestDetailM680xIdx), 1); +} + +TestDetailM680xIdx *test_detail_m680x_idx_clone(const TestDetailM680xIdx *idx) +{ + assert(idx); + TestDetailM680xIdx *clone = test_detail_m680x_idx_new(); + clone->base_reg = idx->base_reg ? strdup(idx->base_reg) : NULL; + clone->offset_reg = idx->offset_reg ? strdup(idx->offset_reg) : NULL; + clone->flags = idx->flags_count > 0 ? + cs_mem_calloc(sizeof(char *), idx->flags_count) : + NULL; + clone->flags_count = idx->flags_count; + for (size_t i = 0; i < clone->flags_count; ++i) { + clone->flags[i] = idx->flags[i] ? strdup(idx->flags[i]) : NULL; + } + clone->offset = idx->offset; + clone->offset_addr = idx->offset_addr; + clone->offset_bits = idx->offset_bits; + clone->inc_dec = idx->inc_dec; + return clone; +} + +void test_detail_m680x_idx_free(TestDetailM680xIdx *idx) +{ + if (!idx) { + return; + } + cs_mem_free(idx->base_reg); + cs_mem_free(idx->offset_reg); + for (size_t i = 0; i < idx->flags_count; ++i) { + cs_mem_free(idx->flags[i]); + } + cs_mem_free(idx->flags); + cs_mem_free(idx); +} + +TestDetailM680x *test_detail_m680x_new() +{ + return cs_mem_calloc(sizeof(TestDetailM680x), 1); +} + +void test_detail_m680x_free(TestDetailM680x *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_m680x_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + for (size_t i = 0; i < detail->flags_count; ++i) { + cs_mem_free(detail->flags[i]); + } + cs_mem_free(detail->flags); + cs_mem_free(detail); +} + +TestDetailM680x *test_detail_m680x_clone(const TestDetailM680x *detail) +{ + TestDetailM680x *clone = test_detail_m680x_new(); + + clone->flags_count = detail->flags_count; + if (detail->flags_count > 0) { + clone->flags = + cs_mem_calloc(sizeof(char *), detail->flags_count); + } + for (size_t i = 0; i < detail->flags_count; ++i) { + clone->flags[i] = detail->flags[i] ? strdup(detail->flags[i]) : + NULL; + } + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailM680xOp *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_m680x_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailM680xOp *test_detail_m680x_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailM680xOp), 1); +} + +TestDetailM680xOp *test_detail_m680x_op_clone(const TestDetailM680xOp *op) +{ + TestDetailM680xOp *clone = test_detail_m680x_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->access = op->access ? strdup(op->access) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->idx = op->idx ? test_detail_m680x_idx_clone(op->idx) : NULL; + clone->imm = op->imm; + clone->rel_address = op->rel_address; + clone->rel_offset = op->rel_offset; + clone->ext_address = op->ext_address; + clone->ext_indirect = op->ext_indirect; + clone->direct_addr = op->direct_addr; + clone->direct_addr_set = op->direct_addr_set; + clone->const_val = op->const_val; + clone->size = op->size; + + return clone; +} + +void test_detail_m680x_op_free(TestDetailM680xOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->access); + cs_mem_free(op->reg); + test_detail_m680x_idx_free(op->idx); + cs_mem_free(op); +} + +bool test_expected_m680x(csh *handle, const cs_m680x *actual, + const TestDetailM680x *expected) +{ + assert(handle && actual && expected); + + compare_uint8_ret(actual->op_count, expected->operands_count, false); + for (size_t i = 0; i < actual->op_count; ++i) { + const cs_m680x_op *op = &actual->operands[i]; + TestDetailM680xOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + compare_enum_ret(op->access, eop->access, false); + if (eop->size > 0) { + compare_uint8_ret(op->size, eop->size, false); + } + switch (op->type) { + default: + fprintf(stderr, + "m680x op type %" PRId32 " not handled.\n", + op->type); + return false; + case M680X_OP_REGISTER: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case M680X_OP_IMMEDIATE: + compare_int32_ret(op->imm, eop->imm, false); + break; + case M680X_OP_EXTENDED: + compare_uint16_ret(op->ext.address, eop->ext_address, + false); + compare_tbool_ret(op->ext.indirect, eop->ext_indirect, + false); + break; + case M680X_OP_DIRECT: + if (eop->direct_addr_set) { + compare_uint8_ret(op->direct_addr, + eop->direct_addr, false); + } else { + assert(eop->direct_addr == 0); + } + break; + case M680X_OP_RELATIVE: + compare_uint16_ret(op->rel.address, eop->rel_address, + false); + compare_int16_ret(op->rel.offset, eop->rel_offset, + false); + break; + case M680X_OP_CONSTANT: + compare_uint8_ret(op->const_val, eop->const_val, false); + break; + case M680X_OP_INDEXED: + if (!eop->idx) { + break; + } + compare_reg_ret(*handle, op->idx.base_reg, + eop->idx->base_reg, false); + compare_reg_ret(*handle, op->idx.offset_reg, + eop->idx->offset_reg, false); + if (eop->idx->offset) { + compare_int16_ret(op->idx.offset, + eop->idx->offset, false); + } + if (eop->idx->offset_addr) { + compare_uint16_ret(op->idx.offset_addr, + eop->idx->offset_addr, + false); + } + if (eop->idx->offset_bits) { + compare_uint8_ret(op->idx.offset_bits, + eop->idx->offset_bits, false); + } + if (eop->idx->inc_dec) { + compare_int8_ret(op->idx.inc_dec, + eop->idx->inc_dec, false); + } + compare_bit_flags_ret(op->idx.flags, eop->idx->flags, + eop->idx->flags_count, false); + break; + } + } + + return true; +} diff --git a/suite/cstest/src/test_detail_m68k.c b/suite/cstest/src/test_detail_m68k.c new file mode 100644 index 0000000000..028b71d948 --- /dev/null +++ b/suite/cstest/src/test_detail_m68k.c @@ -0,0 +1,226 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "capstone/m68k.h" +#include "test_compare.h" +#include "test_detail_m68k.h" +#include +#include +#include + +TestDetailM68KOpMem *test_detail_m68k_op_mem_new() +{ + return cs_mem_calloc(sizeof(TestDetailM68KOpMem), 1); +} + +TestDetailM68KOpMem *test_detail_m68k_op_mem_clone(TestDetailM68KOpMem *mem) +{ + assert(mem); + TestDetailM68KOpMem *clone = test_detail_m68k_op_mem_new(); + + clone->base_reg = mem->base_reg ? strdup(mem->base_reg) : NULL; + clone->index_reg = mem->index_reg ? strdup(mem->index_reg) : NULL; + clone->in_base_reg = mem->in_base_reg ? strdup(mem->in_base_reg) : NULL; + clone->index_size = mem->index_size; + clone->disp = mem->disp; + clone->in_disp = mem->in_disp; + clone->out_disp = mem->out_disp; + clone->scale = mem->scale; + clone->bitfield = mem->bitfield; + clone->width = mem->width; + clone->offset = mem->offset; + + return clone; +} + +void test_detail_m68k_op_mem_free(TestDetailM68KOpMem *mem) +{ + if (!mem) { + return; + } + cs_mem_free(mem->base_reg); + cs_mem_free(mem->index_reg); + cs_mem_free(mem->in_base_reg); + cs_mem_free(mem); +} + +TestDetailM68K *test_detail_m68k_new() +{ + return cs_mem_calloc(sizeof(TestDetailM68K), 1); +} + +void test_detail_m68k_free(TestDetailM68K *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_m68k_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail->op_size_type); + cs_mem_free(detail->op_size_fpu); + cs_mem_free(detail->op_size_cpu); + cs_mem_free(detail); +} + +TestDetailM68K *test_detail_m68k_clone(TestDetailM68K *detail) +{ + TestDetailM68K *clone = test_detail_m68k_new(); + clone->op_size_type = + detail->op_size_type ? strdup(detail->op_size_type) : NULL; + clone->op_size_fpu = detail->op_size_fpu ? strdup(detail->op_size_fpu) : + NULL; + clone->op_size_cpu = detail->op_size_cpu ? strdup(detail->op_size_cpu) : + NULL; + + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailM68KOp *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_m68k_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailM68KOp *test_detail_m68k_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailM68KOp), 1); +} + +TestDetailM68KOp *test_detail_m68k_op_clone(TestDetailM68KOp *op) +{ + TestDetailM68KOp *clone = test_detail_m68k_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->reg_pair_0 = op->reg_pair_0 ? strdup(op->reg_pair_0) : NULL; + clone->reg_pair_1 = op->reg_pair_1 ? strdup(op->reg_pair_1) : NULL; + clone->address_mode = op->address_mode ? strdup(op->address_mode) : + NULL; + + clone->imm = op->imm; + clone->dimm = op->dimm; + clone->simm = op->simm; + clone->br_disp = op->br_disp; + clone->br_disp_size = op->br_disp_size; + clone->register_bits = op->register_bits; + + clone->mem = op->mem ? test_detail_m68k_op_mem_clone(op->mem) : NULL; + return clone; +} + +void test_detail_m68k_op_free(TestDetailM68KOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->reg); + cs_mem_free(op->reg_pair_0); + cs_mem_free(op->reg_pair_1); + cs_mem_free(op->address_mode); + test_detail_m68k_op_mem_free(op->mem); + cs_mem_free(op); +} + +bool test_expected_m68k(csh *handle, cs_m68k *actual, TestDetailM68K *expected) +{ + assert(handle && actual && expected); + + compare_uint8_ret(actual->op_count, expected->operands_count, false); + compare_enum_ret(actual->op_size.type, expected->op_size_type, false); + compare_enum_ret(actual->op_size.fpu_size, expected->op_size_fpu, + false); + compare_enum_ret(actual->op_size.cpu_size, expected->op_size_cpu, + false); + + for (size_t i = 0; i < actual->op_count; ++i) { + cs_m68k_op *op = &actual->operands[i]; + TestDetailM68KOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + compare_enum_ret(op->address_mode, eop->address_mode, false); + switch (op->type) { + default: + fprintf(stderr, + "M68K op type %" PRId32 " not handled.\n", + op->type); + return false; + case M68K_OP_REG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case M68K_OP_REG_PAIR: + compare_reg_ret(*handle, op->reg_pair.reg_0, + eop->reg_pair_0, false); + compare_reg_ret(*handle, op->reg_pair.reg_1, + eop->reg_pair_1, false); + break; + case M68K_OP_IMM: + compare_uint64_ret(op->imm, eop->imm, false); + break; + case M68K_OP_FP_SINGLE: + compare_fp_ret(op->simm, eop->simm, false); + break; + case M68K_OP_FP_DOUBLE: + compare_fp_ret(op->dimm, eop->dimm, false); + break; + case M68K_OP_REG_BITS: + compare_uint32_ret(op->register_bits, + eop->register_bits, false); + break; + case M68K_OP_BR_DISP: + compare_int32_ret(op->br_disp.disp, eop->br_disp, + false); + compare_uint8_ret(op->br_disp.disp_size, + eop->br_disp_size, false); + break; + case M68K_OP_MEM: + if (!eop->mem) { + break; + } + compare_reg_ret(*handle, op->mem.base_reg, + eop->mem->base_reg, false); + compare_reg_ret(*handle, op->mem.index_reg, + eop->mem->index_reg, false); + compare_reg_ret(*handle, op->mem.in_base_reg, + eop->mem->in_base_reg, false); + compare_tbool_ret(op->mem.index_size, + eop->mem->index_size, false); + if (eop->mem->in_disp) { + compare_uint32_ret(op->mem.in_disp, + eop->mem->in_disp, false); + } + if (eop->mem->out_disp) { + compare_uint32_ret(op->mem.out_disp, + eop->mem->out_disp, false); + } + if (eop->mem->disp) { + compare_int16_ret(op->mem.disp, eop->mem->disp, + false); + } + if (eop->mem->scale) { + compare_uint8_ret(op->mem.scale, + eop->mem->scale, false); + } + if (eop->mem->bitfield) { + compare_uint8_ret(op->mem.bitfield, + eop->mem->bitfield, false); + } + if (eop->mem->width) { + compare_uint8_ret(op->mem.width, + eop->mem->width, false); + } + if (eop->mem->offset) { + compare_uint8_ret(op->mem.offset, + eop->mem->offset, false); + } + break; + } + } + + return true; +} diff --git a/suite/cstest/src/test_detail_mips.c b/suite/cstest/src/test_detail_mips.c new file mode 100644 index 0000000000..a1b8836e95 --- /dev/null +++ b/suite/cstest/src/test_detail_mips.c @@ -0,0 +1,103 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_compare.h" +#include "test_detail_mips.h" +#include +#include +#include + +TestDetailMips *test_detail_mips_new() +{ + return cs_mem_calloc(sizeof(TestDetailMips), 1); +} + +void test_detail_mips_free(TestDetailMips *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_mips_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail); +} + +TestDetailMips *test_detail_mips_clone(const TestDetailMips *detail) +{ + TestDetailMips *clone = test_detail_mips_new(); + + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailMipsOp *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_mips_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailMipsOp *test_detail_mips_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailMipsOp), 1); +} + +TestDetailMipsOp *test_detail_mips_op_clone(const TestDetailMipsOp *op) +{ + TestDetailMipsOp *clone = test_detail_mips_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->imm = op->imm; + clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL; + clone->mem_disp = op->mem_disp; + + return clone; +} + +void test_detail_mips_op_free(TestDetailMipsOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->reg); + cs_mem_free(op->mem_base); + cs_mem_free(op); +} + +bool test_expected_mips(csh *handle, const cs_mips *actual, + const TestDetailMips *expected) +{ + assert(handle && actual && expected); + + compare_uint8_ret(actual->op_count, expected->operands_count, false); + for (size_t i = 0; i < actual->op_count; ++i) { + const cs_mips_op *op = &actual->operands[i]; + TestDetailMipsOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + switch (op->type) { + default: + fprintf(stderr, "sh op type %" PRId32 " not handled.\n", + op->type); + return false; + case MIPS_OP_REG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case MIPS_OP_IMM: + compare_uint64_ret(op->imm, eop->imm, false); + break; + case MIPS_OP_MEM: + compare_reg_ret(*handle, op->mem.base, eop->mem_base, + false); + compare_int64_ret(op->mem.disp, eop->mem_disp, false); + break; + } + } + + return true; +} diff --git a/suite/cstest/src/test_detail_mos65xx.c b/suite/cstest/src/test_detail_mos65xx.c new file mode 100644 index 0000000000..8cf859b636 --- /dev/null +++ b/suite/cstest/src/test_detail_mos65xx.c @@ -0,0 +1,105 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_compare.h" +#include "test_detail_mos65xx.h" +#include +#include +#include + +TestDetailMos65xx *test_detail_mos65xx_new() +{ + return cs_mem_calloc(sizeof(TestDetailMos65xx), 1); +} + +void test_detail_mos65xx_free(TestDetailMos65xx *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_mos65xx_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail->am); + cs_mem_free(detail); +} + +TestDetailMos65xx *test_detail_mos65xx_clone(const TestDetailMos65xx *detail) +{ + TestDetailMos65xx *clone = test_detail_mos65xx_new(); + + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailMos65xxOp *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_mos65xx_op_clone(detail->operands[i]); + } + clone->am = detail->am ? strdup(detail->am) : NULL; + clone->modifies_flags = detail->modifies_flags; + + return clone; +} + +TestDetailMos65xxOp *test_detail_mos65xx_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailMos65xxOp), 1); +} + +TestDetailMos65xxOp *test_detail_mos65xx_op_clone(const TestDetailMos65xxOp *op) +{ + TestDetailMos65xxOp *clone = test_detail_mos65xx_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->imm = op->imm; + clone->mem = op->mem; + + return clone; +} + +void test_detail_mos65xx_op_free(TestDetailMos65xxOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->reg); + cs_mem_free(op); +} + +bool test_expected_mos65xx(csh *handle, const cs_mos65xx *actual, + const TestDetailMos65xx *expected) +{ + assert(handle && actual && expected); + + compare_uint8_ret(actual->op_count, expected->operands_count, false); + compare_enum_ret(actual->am, expected->am, false); + compare_tbool_ret(actual->modifies_flags, expected->modifies_flags, + false); + for (size_t i = 0; i < actual->op_count; ++i) { + const cs_mos65xx_op *op = &actual->operands[i]; + TestDetailMos65xxOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + switch (op->type) { + default: + fprintf(stderr, "sh op type %" PRId32 " not handled.\n", + op->type); + return false; + case MOS65XX_OP_REG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case MOS65XX_OP_IMM: + compare_uint16_ret(op->imm, eop->imm, false); + break; + case MOS65XX_OP_MEM: + compare_uint16_ret(op->mem, eop->mem, false); + break; + } + } + + return true; +} diff --git a/suite/cstest/src/test_detail_ppc.c b/suite/cstest/src/test_detail_ppc.c new file mode 100644 index 0000000000..17dc33122e --- /dev/null +++ b/suite/cstest/src/test_detail_ppc.c @@ -0,0 +1,185 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_compare.h" +#include "test_detail_ppc.h" +#include +#include +#include + +TestDetailPPCBC *test_detail_ppc_bc_new() +{ + return cs_mem_calloc(sizeof(TestDetailPPCBC), 1); +} + +TestDetailPPCBC *test_detail_ppc_bc_clone(const TestDetailPPCBC *bc) +{ + assert(bc); + TestDetailPPCBC *clone = test_detail_ppc_bc_new(); + clone->bh = bc->bh ? strdup(bc->bh) : NULL; + clone->crX = bc->crX ? strdup(bc->crX) : NULL; + clone->crX_bit = bc->crX_bit ? strdup(bc->crX_bit) : NULL; + clone->hint = bc->hint ? strdup(bc->hint) : NULL; + clone->pred_cr = bc->pred_cr ? strdup(bc->pred_cr) : NULL; + clone->pred_ctr = bc->pred_ctr ? strdup(bc->pred_ctr) : NULL; + clone->bi = bc->bi; + clone->bi_set = bc->bi_set; + clone->bo = bc->bo; + clone->bo_set = bc->bo_set; + return clone; +} + +void test_detail_ppc_bc_free(TestDetailPPCBC *bc) +{ + if (!bc) { + return; + } + cs_mem_free(bc->bh); + cs_mem_free(bc->crX); + cs_mem_free(bc->crX_bit); + cs_mem_free(bc->hint); + cs_mem_free(bc->pred_cr); + cs_mem_free(bc->pred_ctr); + cs_mem_free(bc); +} + +TestDetailPPC *test_detail_ppc_new() +{ + return cs_mem_calloc(sizeof(TestDetailPPC), 1); +} + +void test_detail_ppc_free(TestDetailPPC *detail) +{ + if (!detail) { + return; + } + test_detail_ppc_bc_free(detail->bc); + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_ppc_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail->format); + cs_mem_free(detail); +} + +TestDetailPPC *test_detail_ppc_clone(const TestDetailPPC *detail) +{ + TestDetailPPC *clone = test_detail_ppc_new(); + clone->format = detail->format ? strdup(detail->format) : NULL; + clone->update_cr0 = detail->update_cr0; + clone->bc = detail->bc ? test_detail_ppc_bc_clone(detail->bc) : NULL; + + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailPPCOp *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_ppc_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailPPCOp *test_detail_ppc_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailPPCOp), 1); +} + +TestDetailPPCOp *test_detail_ppc_op_clone(const TestDetailPPCOp *op) +{ + TestDetailPPCOp *clone = test_detail_ppc_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->access = op->access ? strdup(op->access) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->imm = op->imm; + clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL; + clone->mem_offset = op->mem_offset ? strdup(op->mem_offset) : NULL; + clone->mem_disp = op->mem_disp; + + return clone; +} + +void test_detail_ppc_op_free(TestDetailPPCOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->access); + cs_mem_free(op->reg); + cs_mem_free(op->mem_base); + cs_mem_free(op->mem_offset); + cs_mem_free(op); +} + +bool test_expected_ppc(csh *handle, const cs_ppc *actual, + const TestDetailPPC *expected) +{ + assert(handle && actual && expected); + + compare_enum_ret(actual->format, expected->format, false); + compare_tbool_ret(actual->update_cr0, expected->update_cr0, false); + + if (expected->operands_count == 0) { + return true; + } + compare_uint8_ret(actual->op_count, expected->operands_count, false); + for (size_t i = 0; i < actual->op_count; ++i) { + const cs_ppc_op *op = &actual->operands[i]; + TestDetailPPCOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + compare_enum_ret(op->access, eop->access, false); + switch (op->type) { + default: + fprintf(stderr, + "arm op type %" PRId32 " not handled.\n", + op->type); + return false; + case PPC_OP_REG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case PPC_OP_IMM: + compare_int64_ret(op->imm, eop->imm, false); + break; + case PPC_OP_MEM: + compare_reg_ret(*handle, op->mem.base, eop->mem_base, + false); + compare_reg_ret(*handle, op->mem.offset, + eop->mem_offset, false); + compare_int_ret(op->mem.disp, eop->mem_disp, false); + break; + } + + if (expected->bc) { + if (expected->bc->bi_set) { + compare_uint8_ret(actual->bc.bi, + expected->bc->bi, false); + } else { + assert(expected->bc->bi == 0); + } + if (expected->bc->bo_set) { + compare_uint8_ret(actual->bc.bo, + expected->bc->bo, false); + } else { + assert(expected->bc->bo == 0); + } + compare_enum_ret(actual->bc.bh, expected->bc->bh, + false); + compare_reg_ret(*handle, actual->bc.crX, + expected->bc->crX, false); + compare_enum_ret(actual->bc.crX_bit, + expected->bc->crX_bit, false); + compare_enum_ret(actual->bc.hint, expected->bc->hint, + false); + compare_enum_ret(actual->bc.pred_cr, + expected->bc->pred_cr, false); + compare_enum_ret(actual->bc.pred_ctr, + expected->bc->pred_ctr, false); + } + } + + return true; +} diff --git a/suite/cstest/src/test_detail_riscv.c b/suite/cstest/src/test_detail_riscv.c new file mode 100644 index 0000000000..ef3a59e69e --- /dev/null +++ b/suite/cstest/src/test_detail_riscv.c @@ -0,0 +1,106 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_compare.h" +#include "test_detail_riscv.h" +#include +#include +#include + +TestDetailRISCV *test_detail_riscv_new() +{ + return cs_mem_calloc(sizeof(TestDetailRISCV), 1); +} + +void test_detail_riscv_free(TestDetailRISCV *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_riscv_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail); +} + +TestDetailRISCV *test_detail_riscv_clone(const TestDetailRISCV *detail) +{ + TestDetailRISCV *clone = test_detail_riscv_new(); + + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailRISCVOp *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_riscv_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailRISCVOp *test_detail_riscv_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailRISCVOp), 1); +} + +TestDetailRISCVOp *test_detail_riscv_op_clone(const TestDetailRISCVOp *op) +{ + TestDetailRISCVOp *clone = test_detail_riscv_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->access = op->access ? strdup(op->access) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->imm = op->imm; + clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL; + clone->mem_disp = op->mem_disp; + + return clone; +} + +void test_detail_riscv_op_free(TestDetailRISCVOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->access); + cs_mem_free(op->reg); + cs_mem_free(op->mem_base); + cs_mem_free(op); +} + +bool test_expected_riscv(csh *handle, const cs_riscv *actual, + const TestDetailRISCV *expected) +{ + assert(handle && actual && expected); + + compare_uint8_ret(actual->op_count, expected->operands_count, false); + for (size_t i = 0; i < actual->op_count; ++i) { + const cs_riscv_op *op = &actual->operands[i]; + TestDetailRISCVOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + compare_enum_ret(op->access, eop->access, false); + switch (op->type) { + default: + fprintf(stderr, "sh op type %" PRId32 " not handled.\n", + op->type); + return false; + case RISCV_OP_REG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case RISCV_OP_IMM: + compare_uint64_ret(op->imm, eop->imm, false); + break; + case RISCV_OP_MEM: + compare_reg_ret(*handle, op->mem.base, eop->mem_base, + false); + compare_int64_ret(op->mem.disp, eop->mem_disp, false); + break; + } + } + + return true; +} diff --git a/suite/cstest/src/test_detail_sh.c b/suite/cstest/src/test_detail_sh.c new file mode 100644 index 0000000000..c86ab57ce3 --- /dev/null +++ b/suite/cstest/src/test_detail_sh.c @@ -0,0 +1,107 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_compare.h" +#include "test_detail_sh.h" +#include +#include +#include + +TestDetailSH *test_detail_sh_new() +{ + return cs_mem_calloc(sizeof(TestDetailSH), 1); +} + +void test_detail_sh_free(TestDetailSH *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_sh_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail); +} + +TestDetailSH *test_detail_sh_clone(const TestDetailSH *detail) +{ + TestDetailSH *clone = test_detail_sh_new(); + + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailSHOp *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_sh_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailSHOp *test_detail_sh_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailSHOp), 1); +} + +TestDetailSHOp *test_detail_sh_op_clone(const TestDetailSHOp *op) +{ + TestDetailSHOp *clone = test_detail_sh_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->imm = op->imm; + clone->mem_reg = op->mem_reg ? strdup(op->mem_reg) : NULL; + clone->mem_address = op->mem_address ? strdup(op->mem_address) : NULL; + clone->mem_disp = op->mem_disp; + + return clone; +} + +void test_detail_sh_op_free(TestDetailSHOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->reg); + cs_mem_free(op->mem_reg); + cs_mem_free(op->mem_address); + cs_mem_free(op); +} + +bool test_expected_sh(csh *handle, const cs_sh *actual, + const TestDetailSH *expected) +{ + assert(handle && actual && expected); + + compare_uint8_ret(actual->op_count, expected->operands_count, false); + for (size_t i = 0; i < actual->op_count; ++i) { + const cs_sh_op *op = &actual->operands[i]; + TestDetailSHOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + switch (op->type) { + default: + fprintf(stderr, "sh op type %" PRId32 " not handled.\n", + op->type); + return false; + case SH_OP_REG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case SH_OP_IMM: + compare_uint64_ret(op->imm, eop->imm, false); + break; + case SH_OP_MEM: + compare_reg_ret(*handle, op->mem.reg, eop->mem_reg, + false); + compare_reg_ret(*handle, op->mem.address, + eop->mem_address, false); + compare_int_ret(op->mem.disp, eop->mem_disp, false); + break; + } + } + + return true; +} diff --git a/suite/cstest/src/test_detail_sparc.c b/suite/cstest/src/test_detail_sparc.c new file mode 100644 index 0000000000..1f929cc693 --- /dev/null +++ b/suite/cstest/src/test_detail_sparc.c @@ -0,0 +1,123 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_compare.h" +#include "test_detail_sparc.h" +#include +#include +#include + +TestDetailSparc *test_detail_sparc_new() +{ + return cs_mem_calloc(sizeof(TestDetailSparc), 1); +} + +void test_detail_sparc_free(TestDetailSparc *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_sparc_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail->cc); + cs_mem_free(detail->hint); + cs_mem_free(detail); +} + +TestDetailSparc *test_detail_sparc_clone(const TestDetailSparc *detail) +{ + TestDetailSparc *clone = test_detail_sparc_new(); + + clone->operands_count = detail->operands_count; + clone->cc = detail->cc ? strdup(detail->cc) : NULL; + clone->hint = detail->hint ? strdup(detail->hint) : NULL; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailSparcOp *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_sparc_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailSparcOp *test_detail_sparc_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailSparcOp), 1); +} + +TestDetailSparcOp *test_detail_sparc_op_clone(const TestDetailSparcOp *op) +{ + TestDetailSparcOp *clone = test_detail_sparc_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->imm = op->imm; + clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL; + clone->mem_index = op->mem_index ? strdup(op->mem_index) : NULL; + clone->mem_disp = op->mem_disp; + + return clone; +} + +void test_detail_sparc_op_free(TestDetailSparcOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->reg); + cs_mem_free(op->mem_base); + cs_mem_free(op->mem_index); + cs_mem_free(op); +} + +bool test_expected_sparc(csh *handle, const cs_sparc *actual, + const TestDetailSparc *expected) +{ + assert(handle && actual && expected); + + if (expected->cc) { + compare_enum_ret(actual->cc, expected->cc, false); + } + if (expected->hint) { + compare_enum_ret(actual->hint, expected->hint, false); + } + + if (expected->operands_count == 0) { + return true; + } + compare_uint8_ret(actual->op_count, expected->operands_count, false); + + for (size_t i = 0; i < expected->operands_count; ++i) { + const cs_sparc_op *op = &actual->operands[i]; + TestDetailSparcOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + switch (op->type) { + default: + fprintf(stderr, + "arm op type %" PRId32 " not handled.\n", + op->type); + return false; + case SPARC_OP_REG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case SPARC_OP_IMM: + compare_int64_ret(op->imm, eop->imm, false); + break; + case SPARC_OP_MEM: + compare_reg_ret(*handle, op->mem.base, eop->mem_base, + false); + compare_reg_ret(*handle, op->mem.index, eop->mem_index, + false); + compare_int32_ret(op->mem.disp, eop->mem_disp, false); + break; + } + } + + return true; +} diff --git a/suite/cstest/src/test_detail_systemz.c b/suite/cstest/src/test_detail_systemz.c new file mode 100644 index 0000000000..a15fbca632 --- /dev/null +++ b/suite/cstest/src/test_detail_systemz.c @@ -0,0 +1,112 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_compare.h" +#include "test_detail_systemz.h" +#include +#include +#include + +TestDetailSystemZ *test_detail_systemz_new() +{ + return cs_mem_calloc(sizeof(TestDetailSystemZ), 1); +} + +void test_detail_systemz_free(TestDetailSystemZ *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_systemz_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail); +} + +TestDetailSystemZ *test_detail_systemz_clone(const TestDetailSystemZ *detail) +{ + TestDetailSystemZ *clone = test_detail_systemz_new(); + + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailSystemZOp *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_systemz_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailSystemZOp *test_detail_systemz_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailSystemZOp), 1); +} + +TestDetailSystemZOp *test_detail_systemz_op_clone(const TestDetailSystemZOp *op) +{ + TestDetailSystemZOp *clone = test_detail_systemz_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->imm = op->imm; + clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL; + clone->mem_index = op->mem_index ? strdup(op->mem_index) : NULL; + clone->mem_disp = op->mem_disp; + clone->mem_length = op->mem_length; + + return clone; +} + +void test_detail_systemz_op_free(TestDetailSystemZOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->reg); + cs_mem_free(op->mem_base); + cs_mem_free(op->mem_index); + cs_mem_free(op); +} + +bool test_expected_systemz(csh *handle, const cs_sysz *actual, + const TestDetailSystemZ *expected) +{ + assert(handle && actual && expected); + + compare_uint8_ret(actual->op_count, expected->operands_count, false); + for (size_t i = 0; i < actual->op_count; ++i) { + const cs_sysz_op *op = &actual->operands[i]; + TestDetailSystemZOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + switch (op->type) { + default: + fprintf(stderr, + "arm op type %" PRId32 " not handled.\n", + op->type); + return false; + case SYSZ_OP_REG: + case SYSZ_OP_ACREG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case SYSZ_OP_IMM: + compare_int64_ret(op->imm, eop->imm, false); + break; + case SYSZ_OP_MEM: + compare_reg_ret(*handle, op->mem.base, eop->mem_base, + false); + compare_reg_ret(*handle, op->mem.index, eop->mem_index, + false); + compare_int64_ret(op->mem.disp, eop->mem_disp, false); + compare_uint64_ret(op->mem.length, eop->mem_length, + false); + break; + } + } + + return true; +} diff --git a/suite/cstest/src/test_detail_tms320c64x.c b/suite/cstest/src/test_detail_tms320c64x.c new file mode 100644 index 0000000000..99d8cd8298 --- /dev/null +++ b/suite/cstest/src/test_detail_tms320c64x.c @@ -0,0 +1,179 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "capstone/tms320c64x.h" +#include "test_compare.h" +#include "test_detail_tms320c64x.h" +#include +#include +#include + +TestDetailTMS320c64x *test_detail_tms320c64x_new() +{ + return cs_mem_calloc(sizeof(TestDetailTMS320c64x), 1); +} + +void test_detail_tms320c64x_free(TestDetailTMS320c64x *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_tms320c64x_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail->cond_reg); + cs_mem_free(detail->funit_unit); + cs_mem_free(detail); +} + +TestDetailTMS320c64x *test_detail_tms320c64x_clone(TestDetailTMS320c64x *detail) +{ + TestDetailTMS320c64x *clone = test_detail_tms320c64x_new(); + clone->cond_reg = detail->cond_reg ? strdup(detail->cond_reg) : NULL; + clone->cond_zero = detail->cond_zero; + clone->funit_unit = detail->funit_unit ? strdup(detail->funit_unit) : + NULL; + clone->funit_side = detail->funit_side; + clone->funit_side_set = detail->funit_side_set; + clone->funit_crosspath = detail->funit_crosspath; + clone->funit_crosspath_set = detail->funit_crosspath_set; + + clone->parallel = detail->parallel; + clone->parallel_set = detail->parallel_set; + + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = + cs_mem_calloc(sizeof(TestDetailTMS320c64xOp *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_tms320c64x_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailTMS320c64xOp *test_detail_tms320c64x_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailTMS320c64xOp), 1); +} + +TestDetailTMS320c64xOp * +test_detail_tms320c64x_op_clone(TestDetailTMS320c64xOp *op) +{ + TestDetailTMS320c64xOp *clone = test_detail_tms320c64x_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->reg_pair_0 = op->reg_pair_0 ? strdup(op->reg_pair_0) : NULL; + clone->reg_pair_1 = op->reg_pair_1 ? strdup(op->reg_pair_1) : NULL; + clone->imm = op->imm; + clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL; + clone->mem_scaled = op->mem_scaled; + clone->mem_disptype = op->mem_disptype ? strdup(op->mem_disptype) : + NULL; + clone->mem_direction = op->mem_direction ? strdup(op->mem_direction) : + NULL; + clone->mem_modify = op->mem_modify ? strdup(op->mem_modify) : NULL; + clone->mem_disp_const = op->mem_disp_const; + clone->mem_disp_reg = op->mem_disp_reg ? strdup(op->mem_disp_reg) : + NULL; + clone->mem_unit = op->mem_unit; + + return clone; +} + +void test_detail_tms320c64x_op_free(TestDetailTMS320c64xOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->mem_base); + cs_mem_free(op->mem_disp_reg); + cs_mem_free(op->mem_disptype); + cs_mem_free(op->mem_direction); + cs_mem_free(op->mem_modify); + cs_mem_free(op->reg); + cs_mem_free(op->reg_pair_0); + cs_mem_free(op->reg_pair_1); + cs_mem_free(op); +} + +bool test_expected_tms320c64x(csh *handle, cs_tms320c64x *actual, + TestDetailTMS320c64x *expected) +{ + assert(handle && actual && expected); + + compare_uint8_ret(actual->op_count, expected->operands_count, false); + compare_reg_ret(*handle, actual->condition.reg, expected->cond_reg, + false); + compare_tbool_ret(actual->condition.zero, expected->cond_zero, false); + compare_enum_ret(actual->funit.unit, expected->funit_unit, false); + if (expected->funit_side_set) { + compare_uint8_ret(actual->funit.side, expected->funit_side, + false); + } else { + assert(expected->funit_side == 0); + } + if (expected->funit_crosspath_set) { + compare_uint8_ret(actual->funit.crosspath, + expected->funit_crosspath, false); + } else { + assert(expected->funit_crosspath == 0); + } + if (expected->parallel_set) { + compare_uint8_ret(actual->parallel, expected->parallel, false); + } else { + assert(expected->parallel == 0); + } + for (size_t i = 0; i < actual->op_count; ++i) { + cs_tms320c64x_op *op = &actual->operands[i]; + TestDetailTMS320c64xOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + switch (op->type) { + default: + fprintf(stderr, + "tms320c64x op type %" PRId32 " not handled.\n", + op->type); + return false; + case TMS320C64X_OP_REG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case TMS320C64X_OP_REGPAIR: + compare_reg_ret(*handle, op->reg + 1, eop->reg_pair_0, + false); + compare_reg_ret(*handle, op->reg, eop->reg_pair_1, + false); + break; + case TMS320C64X_OP_IMM: + compare_int32_ret(op->imm, eop->imm, false); + break; + case TMS320C64X_OP_MEM: + compare_reg_ret(*handle, op->mem.base, eop->mem_base, + false); + compare_enum_ret(op->mem.direction, eop->mem_direction, + false); + compare_tbool_ret(op->mem.scaled, eop->mem_scaled, + false); + compare_enum_ret(op->mem.disptype, eop->mem_disptype, + false); + if (op->mem.disptype == TMS320C64X_MEM_DISP_REGISTER) { + compare_reg_ret(*handle, op->mem.disp, + eop->mem_disp_reg, false); + } else { + compare_uint_ret(op->mem.disp, + eop->mem_disp_const, false); + } + compare_enum_ret(op->mem.modify, eop->mem_modify, + false); + compare_uint_ret(op->mem.unit, eop->mem_unit, false); + break; + } + } + + return true; +} diff --git a/suite/cstest/src/test_detail_tricore.c b/suite/cstest/src/test_detail_tricore.c new file mode 100644 index 0000000000..899cff5487 --- /dev/null +++ b/suite/cstest/src/test_detail_tricore.c @@ -0,0 +1,109 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_compare.h" +#include "test_detail_tricore.h" +#include +#include +#include + +TestDetailTriCore *test_detail_tricore_new() +{ + return cs_mem_calloc(sizeof(TestDetailTriCore), 1); +} + +void test_detail_tricore_free(TestDetailTriCore *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_tricore_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail); +} + +TestDetailTriCore *test_detail_tricore_clone(const TestDetailTriCore *detail) +{ + TestDetailTriCore *clone = test_detail_tricore_new(); + clone->update_flags = detail->update_flags; + + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailTriCoreOp *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_tricore_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailTriCoreOp *test_detail_tricore_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailTriCoreOp), 1); +} + +TestDetailTriCoreOp *test_detail_tricore_op_clone(const TestDetailTriCoreOp *op) +{ + TestDetailTriCoreOp *clone = test_detail_tricore_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->access = op->access ? strdup(op->access) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->imm = op->imm; + clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL; + clone->mem_disp = op->mem_disp; + + return clone; +} + +void test_detail_tricore_op_free(TestDetailTriCoreOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->access); + cs_mem_free(op->reg); + cs_mem_free(op->mem_base); + cs_mem_free(op); +} + +bool test_expected_tricore(csh *handle, const cs_tricore *actual, + const TestDetailTriCore *expected) +{ + assert(handle && actual && expected); + + compare_uint8_ret(actual->op_count, expected->operands_count, false); + compare_tbool_ret(actual->update_flags, expected->update_flags, false); + for (size_t i = 0; i < actual->op_count; ++i) { + const cs_tricore_op *op = &actual->operands[i]; + TestDetailTriCoreOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + compare_enum_ret(op->access, eop->access, false); + switch (op->type) { + default: + fprintf(stderr, + "tricore op type %" PRId32 " not handled.\n", + op->type); + return false; + case TRICORE_OP_REG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case TRICORE_OP_IMM: + compare_int64_ret(op->imm, eop->imm, false); + break; + case TRICORE_OP_MEM: + compare_reg_ret(*handle, op->mem.base, eop->mem_base, + false); + compare_int64_ret(op->mem.disp, eop->mem_disp, false); + break; + } + } + + return true; +} diff --git a/suite/cstest/src/test_detail_wasm.c b/suite/cstest/src/test_detail_wasm.c new file mode 100644 index 0000000000..a5dcd9381b --- /dev/null +++ b/suite/cstest/src/test_detail_wasm.c @@ -0,0 +1,128 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_compare.h" +#include "test_detail_wasm.h" +#include +#include +#include + +TestDetailWASM *test_detail_wasm_new() +{ + return cs_mem_calloc(sizeof(TestDetailWASM), 1); +} + +void test_detail_wasm_free(TestDetailWASM *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_wasm_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail); +} + +TestDetailWASM *test_detail_wasm_clone(const TestDetailWASM *detail) +{ + TestDetailWASM *clone = test_detail_wasm_new(); + + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailWASMOp *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_wasm_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailWASMOp *test_detail_wasm_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailWASMOp), 1); +} + +TestDetailWASMOp *test_detail_wasm_op_clone(const TestDetailWASMOp *op) +{ + TestDetailWASMOp *clone = test_detail_wasm_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->size = op->size; + clone->int7 = op->int7; + clone->varuint32 = op->varuint32; + clone->varuint64 = op->varuint64; + clone->uint32 = op->uint32; + clone->uint64 = op->uint64; + clone->immediate_0 = op->immediate_0; + clone->immediate_1 = op->immediate_1; + clone->brt_length = op->brt_length; + clone->brt_address = op->brt_address; + clone->brt_default_target = op->brt_default_target; + return clone; +} + +void test_detail_wasm_op_free(TestDetailWASMOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op); +} + +bool test_expected_wasm(csh *handle, const cs_wasm *actual, + const TestDetailWASM *expected) +{ + assert(handle && actual && expected); + + compare_uint8_ret(actual->op_count, expected->operands_count, false); + for (size_t i = 0; i < actual->op_count; ++i) { + const cs_wasm_op *op = &actual->operands[i]; + TestDetailWASMOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + switch (op->type) { + default: + fprintf(stderr, + "WASM op type %" PRId32 " not handled.\n", + op->type); + return false; + case WASM_OP_INT7: + compare_int8_ret(op->int7, eop->int7, false); + break; + case WASM_OP_VARUINT32: + compare_uint32_ret(op->varuint32, eop->varuint32, + false); + break; + case WASM_OP_VARUINT64: + compare_uint64_ret(op->varuint64, eop->varuint64, + false); + break; + case WASM_OP_UINT32: + compare_uint32_ret(op->uint32, eop->uint32, false); + break; + case WASM_OP_UINT64: + compare_uint64_ret(op->uint64, eop->uint64, false); + break; + case WASM_OP_IMM: + compare_uint32_ret(op->immediate[0], eop->immediate_0, + false); + compare_uint32_ret(op->immediate[1], eop->immediate_1, + false); + break; + case WASM_OP_BRTABLE: + compare_uint32_ret(op->brtable.length, eop->brt_length, + false); + compare_uint32_ret(op->brtable.default_target, + eop->brt_default_target, false); + compare_uint64_ret(op->brtable.address, + eop->brt_address, false); + break; + } + } + + return true; +} diff --git a/suite/cstest/src/test_detail_x86.c b/suite/cstest/src/test_detail_x86.c new file mode 100644 index 0000000000..b7a3836511 --- /dev/null +++ b/suite/cstest/src/test_detail_x86.c @@ -0,0 +1,264 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_compare.h" +#include "test_detail_x86.h" +#include +#include +#include + +TestDetailX86 *test_detail_x86_new() +{ + return cs_mem_calloc(sizeof(TestDetailX86), 1); +} + +void test_detail_x86_free(TestDetailX86 *detail) +{ + if (!detail) { + return; + } + if (detail->prefix[0]) { + for (size_t i = 0; i < ARR_SIZE(detail->prefix); ++i) { + cs_mem_free(detail->prefix[i]); + } + } + for (size_t i = 0; i < detail->eflags_count; ++i) { + cs_mem_free(detail->eflags[i]); + } + cs_mem_free(detail->eflags); + for (size_t i = 0; i < detail->fpu_flags_count; ++i) { + cs_mem_free(detail->fpu_flags[i]); + } + cs_mem_free(detail->fpu_flags); + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_x86_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + + cs_mem_free(detail->sib_index); + cs_mem_free(detail->sib_base); + cs_mem_free(detail->xop_cc); + cs_mem_free(detail->sse_cc); + cs_mem_free(detail->avx_cc); + cs_mem_free(detail->avx_rm); + cs_mem_free(detail); +} + +TestDetailX86 *test_detail_x86_clone(TestDetailX86 *detail) +{ + TestDetailX86 *clone = test_detail_x86_new(); + clone->sib_index = detail->sib_index ? strdup(detail->sib_index) : NULL; + clone->sib_base = detail->sib_base ? strdup(detail->sib_base) : NULL; + clone->xop_cc = detail->xop_cc ? strdup(detail->xop_cc) : NULL; + clone->sse_cc = detail->sse_cc ? strdup(detail->sse_cc) : NULL; + clone->avx_cc = detail->avx_cc ? strdup(detail->avx_cc) : NULL; + clone->avx_rm = detail->avx_rm ? strdup(detail->avx_rm) : NULL; + + if (detail->prefix[0]) { + for (size_t i = 0; i < ARR_SIZE(clone->prefix); ++i) { + clone->prefix[i] = strdup(detail->prefix[i]); + } + } + memcpy(clone->opcode, detail->opcode, sizeof(clone->opcode)); + + clone->rex = detail->rex; + clone->addr_size = detail->addr_size; + clone->modrm = detail->modrm; + clone->sib = detail->sib; + clone->disp = detail->disp; + clone->sib_scale = detail->sib_scale; + clone->avx_sae = detail->avx_sae; + + clone->enc_modrm_offset = detail->enc_modrm_offset; + clone->enc_disp_offset = detail->enc_disp_offset; + clone->enc_disp_size = detail->enc_disp_size; + clone->enc_imm_offset = detail->enc_imm_offset; + clone->enc_imm_size = detail->enc_imm_size; + + clone->eflags_count = detail->eflags_count; + clone->eflags = detail->eflags ? cs_mem_calloc(sizeof(char *), + detail->eflags_count) : + NULL; + for (size_t i = 0; i < detail->eflags_count; ++i) { + clone->eflags[i] = + detail->eflags[i] ? strdup(detail->eflags[i]) : NULL; + } + + clone->fpu_flags_count = detail->fpu_flags_count; + clone->fpu_flags = + detail->fpu_flags ? + cs_mem_calloc(sizeof(char *), detail->fpu_flags_count) : + NULL; + for (size_t i = 0; i < detail->fpu_flags_count; ++i) { + clone->fpu_flags[i] = detail->fpu_flags[i] ? + strdup(detail->fpu_flags[i]) : + NULL; + } + + clone->operands_count = detail->operands_count; + clone->operands = detail->operands_count > 0 ? + cs_mem_calloc(sizeof(TestDetailX86Op *), + detail->operands_count) : + NULL; + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_x86_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailX86Op *test_detail_x86_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailX86Op), 1); +} + +TestDetailX86Op *test_detail_x86_op_clone(TestDetailX86Op *op) +{ + TestDetailX86Op *clone = test_detail_x86_op_new(); + + clone->size = op->size; + clone->type = op->type ? strdup(op->type) : NULL; + clone->access = op->access ? strdup(op->access) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->imm = op->imm; + clone->mem_segment = op->mem_segment ? strdup(op->mem_segment) : NULL; + clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL; + clone->mem_index = op->mem_index ? strdup(op->mem_index) : NULL; + clone->mem_scale = op->mem_scale; + clone->mem_disp = op->mem_disp; + clone->avx_bcast = op->avx_bcast ? strdup(op->avx_bcast) : NULL; + clone->avx_zero_opmask = op->avx_zero_opmask; + + return clone; +} + +void test_detail_x86_op_free(TestDetailX86Op *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->access); + cs_mem_free(op->reg); + cs_mem_free(op->mem_segment); + cs_mem_free(op->mem_base); + cs_mem_free(op->mem_index); + cs_mem_free(op->avx_bcast); + cs_mem_free(op); +} + +bool test_expected_x86(csh *handle, cs_x86 *actual, TestDetailX86 *expected) +{ + assert(handle && actual && expected); + + compare_reg_ret(*handle, actual->sib_index, expected->sib_index, false); + compare_reg_ret(*handle, actual->sib_base, expected->sib_base, false); + + compare_enum_ret(actual->xop_cc, expected->xop_cc, false); + compare_enum_ret(actual->sse_cc, expected->sse_cc, false); + compare_enum_ret(actual->avx_cc, expected->avx_cc, false); + compare_enum_ret(actual->avx_rm, expected->avx_rm, false); + + if (expected->rex) { + compare_uint8_ret(actual->rex, expected->rex, false); + } + if (expected->addr_size) { + compare_uint8_ret(actual->addr_size, expected->addr_size, false); + } + if (expected->modrm) { + compare_uint8_ret(actual->modrm, expected->modrm, false); + } + if (expected->sib) { + compare_uint8_ret(actual->sib, expected->sib, false); + } + if (expected->disp) { + compare_int64_ret(actual->disp, expected->disp, false); + } + if (expected->sib_scale) { + compare_int8_ret(actual->sib_scale, expected->sib_scale, false); + } + compare_tbool_ret(actual->avx_sae, expected->avx_sae, false); + + for (size_t i = 0; i < ARR_SIZE(actual->prefix); ++i) { + compare_enum_ret(actual->prefix[i], expected->prefix[i], + false); + } + for (size_t i = 0; i < ARR_SIZE(actual->opcode); ++i) { + if (expected->opcode[i] != 0) { + compare_uint8_ret(actual->opcode[i], expected->opcode[i], + false); + } + } + + compare_bit_flags_64_ret(actual->eflags, expected->eflags, + expected->eflags_count, false); + compare_bit_flags_64_ret(actual->fpu_flags, expected->fpu_flags, + expected->fpu_flags_count, false); + + if (expected->enc_modrm_offset) { + compare_uint8_ret(actual->encoding.modrm_offset, + expected->enc_modrm_offset, false); + } + if (expected->enc_disp_offset) { + compare_uint8_ret(actual->encoding.disp_offset, + expected->enc_disp_offset, false); + } + if (expected->enc_disp_size) { + compare_uint8_ret(actual->encoding.disp_size, + expected->enc_disp_size, false); + } + if (expected->enc_imm_offset) { + compare_uint8_ret(actual->encoding.imm_offset, + expected->enc_imm_offset, false); + } + if (expected->enc_imm_size) { + compare_uint8_ret(actual->encoding.imm_size, + expected->enc_imm_size, false); + } + + if (expected->operands_count == 0) { + return true; + } + compare_uint8_ret(actual->op_count, expected->operands_count, false); + + for (size_t i = 0; i < actual->op_count; ++i) { + cs_x86_op *op = &actual->operands[i]; + TestDetailX86Op *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + compare_enum_ret(op->access, eop->access, false); + compare_enum_ret(op->avx_bcast, eop->avx_bcast, false); + compare_tbool_ret(op->avx_zero_opmask, eop->avx_zero_opmask, + false); + switch (op->type) { + default: + fprintf(stderr, + "arm op type %" PRId32 " not handled.\n", + op->type); + return false; + case X86_OP_REG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case X86_OP_IMM: + compare_int64_ret(op->imm, eop->imm, false); + break; + case X86_OP_MEM: + compare_reg_ret(*handle, op->mem.segment, + eop->mem_segment, false); + compare_reg_ret(*handle, op->mem.base, eop->mem_base, + false); + compare_reg_ret(*handle, op->mem.index, eop->mem_index, + false); + if (eop->mem_disp) { + compare_int64_ret(op->mem.disp, eop->mem_disp, false); + } + if (eop->mem_scale) { + compare_int_ret(op->mem.scale, eop->mem_scale, + false); + } + break; + } + } + + return true; +} diff --git a/suite/cstest/src/test_detail_xcore.c b/suite/cstest/src/test_detail_xcore.c new file mode 100644 index 0000000000..2eda4d306b --- /dev/null +++ b/suite/cstest/src/test_detail_xcore.c @@ -0,0 +1,113 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_compare.h" +#include "test_detail_xcore.h" +#include +#include +#include + +TestDetailXCore *test_detail_xcore_new() +{ + return cs_mem_calloc(sizeof(TestDetailXCore), 1); +} + +void test_detail_xcore_free(TestDetailXCore *detail) +{ + if (!detail) { + return; + } + for (size_t i = 0; i < detail->operands_count; ++i) { + test_detail_xcore_op_free(detail->operands[i]); + } + cs_mem_free(detail->operands); + cs_mem_free(detail); +} + +TestDetailXCore *test_detail_xcore_clone(const TestDetailXCore *detail) +{ + TestDetailXCore *clone = test_detail_xcore_new(); + + clone->operands_count = detail->operands_count; + if (detail->operands_count > 0) { + clone->operands = cs_mem_calloc(sizeof(TestDetailXCoreOp *), + detail->operands_count); + } + for (size_t i = 0; i < detail->operands_count; ++i) { + clone->operands[i] = + test_detail_xcore_op_clone(detail->operands[i]); + } + + return clone; +} + +TestDetailXCoreOp *test_detail_xcore_op_new() +{ + return cs_mem_calloc(sizeof(TestDetailXCoreOp), 1); +} + +TestDetailXCoreOp *test_detail_xcore_op_clone(const TestDetailXCoreOp *op) +{ + TestDetailXCoreOp *clone = test_detail_xcore_op_new(); + + clone->type = op->type ? strdup(op->type) : NULL; + clone->reg = op->reg ? strdup(op->reg) : NULL; + clone->imm = op->imm; + clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL; + clone->mem_index = op->mem_index ? strdup(op->mem_index) : NULL; + clone->mem_disp = op->mem_disp; + clone->mem_direct = op->mem_direct; + + return clone; +} + +void test_detail_xcore_op_free(TestDetailXCoreOp *op) +{ + if (!op) { + return; + } + cs_mem_free(op->type); + cs_mem_free(op->reg); + cs_mem_free(op->mem_base); + cs_mem_free(op->mem_index); + cs_mem_free(op); +} + +bool test_expected_xcore(csh *handle, const cs_xcore *actual, + const TestDetailXCore *expected) +{ + assert(handle && actual && expected); + + compare_uint8_ret(actual->op_count, expected->operands_count, false); + for (size_t i = 0; i < actual->op_count; ++i) { + const cs_xcore_op *op = &actual->operands[i]; + TestDetailXCoreOp *eop = expected->operands[i]; + compare_enum_ret(op->type, eop->type, false); + switch (op->type) { + default: + fprintf(stderr, + "arm op type %" PRId32 " not handled.\n", + op->type); + return false; + case XCORE_OP_REG: + compare_reg_ret(*handle, op->reg, eop->reg, false); + break; + case XCORE_OP_IMM: + compare_int32_ret(op->imm, eop->imm, false); + break; + case XCORE_OP_MEM: + compare_reg_ret(*handle, op->mem.base, eop->mem_base, + false); + compare_reg_ret(*handle, op->mem.index, eop->mem_index, + false); + compare_int_ret(op->mem.disp, eop->mem_disp, false); + if (eop->mem_direct) { + compare_int_ret(op->mem.direct, eop->mem_direct, + false); + } + break; + } + } + + return true; +} diff --git a/suite/cstest/src/test_run.c b/suite/cstest/src/test_run.c new file mode 100644 index 0000000000..36e2b0a593 --- /dev/null +++ b/suite/cstest/src/test_run.c @@ -0,0 +1,323 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "test_run.h" +#include "test_case.h" +#include "test_mapping.h" +#include "../../../utils.h" +#include +#include +#include +#include "cmocka.h" +#include +#include +#include + +static TestRunResult get_test_run_result(TestRunStats *stats) +{ + if (stats->tc_total != + stats->successful + stats->failed + stats->skipped) { + fprintf(stderr, + "[!] Inconsistent statistics: total != successful + failed + skipped\n"); + stats->errors++; + return TEST_RUN_ERROR; + } + + if (stats->errors != 0) { + return TEST_RUN_ERROR; + } else if (stats->failed != 0) { + return TEST_RUN_FAILURE; + } + return TEST_RUN_SUCCESS; +} + +/// Extract all test cases from the given test files. +static TestFile **parse_test_files(char **tf_paths, uint32_t path_count, + TestRunStats *stats) +{ + TestFile **files = NULL; + stats->tc_total = 0; + + for (size_t i = 0; i < path_count; ++i) { + TestFile *test_file_data = NULL; + cyaml_err_t err = cyaml_load_file( + tf_paths[i], &cyaml_config, &test_file_schema, + (cyaml_data_t **)&test_file_data, NULL); + + if (err != CYAML_OK || !test_file_data) { + fprintf(stderr, "[!] Failed to parse test file '%s'\n", + tf_paths[i]); + fprintf(stderr, "[!] Error: '%s'\n", + !test_file_data && err == CYAML_OK ? + "Empty file" : + cyaml_strerror(err)); + stats->invalid_files++; + stats->errors++; + continue; + } + + size_t k = stats->valid_test_files++; + // Copy all test cases of a test file + files = cs_mem_realloc(files, sizeof(TestFile *) * + stats->valid_test_files); + + files[k] = test_file_clone(test_file_data); + assert(files[k]); + stats->tc_total += files[k]->test_cases_count; + files[k]->filename = strrchr(tf_paths[i], '/') ? + strdup(strrchr(tf_paths[i], '/')) : + strdup(tf_paths[i]); + + err = cyaml_free(&cyaml_config, &test_file_schema, + test_file_data, 0); + if (err != CYAML_OK) { + fprintf(stderr, "[!] Error: '%s'\n", + cyaml_strerror(err)); + stats->errors++; + continue; + } + } + + return files; +} + +/// Parses the @input and saves the results in the other arguments. +static bool parse_input_options(const TestInput *input, cs_arch *arch, + cs_mode *mode, cs_opt *opt_arr, + size_t opt_arr_size, size_t *opt_set) +{ + assert(input && arch && mode && opt_arr); + bool arch_found = false; + const char *opt_str = input->arch; + + int val = enum_map_bin_search(test_arch_map, ARR_SIZE(test_arch_map), + opt_str, &arch_found); + if (arch_found) { + *arch = val; + } else { + fprintf(stderr, + "[!] '%s' is not mapped to a capstone architecture.\n", + input->arch); + return false; + } + + *mode = 0; + bool mode_found = false; + size_t opt_idx = 0; + char **options = input->options; + for (size_t i = 0; i < input->options_count; ++i) { + opt_str = options[i]; + val = enum_map_bin_search(test_mode_map, + ARR_SIZE(test_mode_map), opt_str, + &mode_found); + if (mode_found) { + *mode |= val; + goto next_option; + } + + // Might be an option descriptor + for (size_t k = 0; k < ARR_SIZE(test_option_map); k++) { + if (strings_match(opt_str, test_option_map[k].str)) { + if (opt_idx >= opt_arr_size) { + fprintf(stderr, + "Too many options given in: '%s'. Maximum is: %" PRId64 + "\n", + opt_str, opt_arr_size); + return false; + } + opt_arr[opt_idx++] = test_option_map[k].opt; + goto next_option; + } + } + fprintf(stderr, "[!] Option: '%s' not used\n", opt_str); +next_option: + continue; + } + *opt_set = opt_idx; + return true; +} + +/// Parses the options for cs_open/cs_option and initializes the handle. +/// Returns true for success and false otherwise. +static bool open_cs_handle(UnitTestState *ustate) +{ + cs_arch arch = 0; + cs_mode mode = 0; + cs_opt options[8] = { 0 }; + size_t options_set = 0; + + if (!parse_input_options(ustate->tcase->input, &arch, &mode, options, 8, + &options_set)) { + char *tc_str = test_input_stringify(ustate->tcase->input, ""); + fprintf(stderr, "Could not parse options: %s\n", tc_str); + cs_mem_free(tc_str); + return false; + } + + cs_err err = cs_open(arch, mode, &ustate->handle); + if (err != CS_ERR_OK) { + char *tc_str = test_input_stringify(ustate->tcase->input, ""); + fprintf(stderr, + "[!] cs_open() failed with: '%s'. TestInput: %s\n", + cs_strerror(err), tc_str); + cs_mem_free(tc_str); + return false; + } + + // The bit mode must be set, otherwise the numbers are + // not normalized correctly in the asm-test comparison step. + if (arch == CS_ARCH_AARCH64 || mode & CS_MODE_64) { + ustate->arch_bits = 64; + } else if (mode & CS_MODE_16) { + ustate->arch_bits = 16; + } else { + ustate->arch_bits = 32; + } + if (err != CS_ERR_OK) { + goto option_error; + } + + if (err != CS_ERR_OK) { + goto option_error; + } + for (size_t i = 0; i < options_set; ++i) { + err = cs_option(ustate->handle, options[i].type, + options[i].val); + if (err != CS_ERR_OK) { + goto option_error; + } + } + return true; + +option_error: { + char *tc_str = test_input_stringify(ustate->tcase->input, ""); + fprintf(stderr, "[!] cs_option() failed with: '%s'. TestInput: %s\n", + cs_strerror(err), tc_str); + cs_mem_free(tc_str); + cs_close(&ustate->handle); + return false; +} +} + +static int cstest_unit_test_setup(void **state) +{ + assert(state); + UnitTestState *ustate = *state; + assert(ustate->tcase); + if (!open_cs_handle(ustate)) { + fail_msg("Failed to initialize Capstone with given options."); + return -1; + } + return 0; +} + +static int cstest_unit_test_teardown(void **state) +{ + if (!state) { + return 0; + } + UnitTestState *ustate = *state; + if (ustate->handle) { + cs_err err = cs_close(&ustate->handle); + if (err != CS_ERR_OK) { + fail_msg("cs_close() failed with: '%s'.", + cs_strerror(err)); + return -1; + } + } + return 0; +} + +static void cstest_unit_test(void **state) +{ + assert(state); + UnitTestState *ustate = *state; + assert(ustate); + assert(ustate->handle); + assert(ustate->tcase); + csh handle = ustate->handle; + TestCase *tcase = ustate->tcase; + + cs_insn *insns = NULL; + size_t insns_count = cs_disasm(handle, tcase->input->bytes, + tcase->input->bytes_count, + tcase->input->address, 0, &insns); + test_expected_compare(&ustate->handle, tcase->expected, insns, + insns_count, ustate->arch_bits); + cs_free(insns, insns_count); +} + +static void eval_test_cases(TestFile **test_files, TestRunStats *stats) +{ + assert(test_files && stats); + // CMocka's API doesn't allow to init a CMUnitTest with a partially initialized state + // (which is later initialized in the test setup). + // So we do it manually here. + struct CMUnitTest *utest_table = + cs_mem_calloc(sizeof(struct CMUnitTest), + stats->tc_total); // Number of test cases. + + char utest_id[128] = { 0 }; + + size_t tci = 0; + for (size_t i = 0; i < stats->valid_test_files; ++i) { + TestCase **test_cases = test_files[i]->test_cases; + const char *filename = test_files[i]->filename ? + test_files[i]->filename : + NULL; + + for (size_t k = 0; k < test_files[i]->test_cases_count; + ++k, ++tci) { + cs_snprintf(utest_id, sizeof(utest_id), + "%s - TC #%" PRIx32 ": ", filename, k); + if (test_cases[k]->skip) { + char *tc_name = test_input_stringify( + test_cases[k]->input, utest_id); + fprintf(stderr, "SKIP: %s\nReason: %s\n", + tc_name, test_cases[k]->skip_reason); + cs_mem_free(tc_name); + stats->skipped++; + continue; + } + + UnitTestState *ut_state = + cs_mem_calloc(sizeof(UnitTestState), 1); + ut_state->tcase = test_cases[k]; + utest_table[tci].name = test_input_stringify( + ut_state->tcase->input, utest_id); + utest_table[tci].initial_state = ut_state; + utest_table[tci].setup_func = cstest_unit_test_setup; + utest_table[tci].teardown_func = + cstest_unit_test_teardown; + utest_table[tci].test_func = cstest_unit_test; + } + } + // Use private function here, because the API takes only constant tables. + int failed_tests = _cmocka_run_group_tests( + "All test cases", utest_table, stats->tc_total, NULL, NULL); + for (size_t i = 0; i < stats->tc_total; ++i) { + cs_mem_free((char *)utest_table[i].name); + cs_mem_free(utest_table[i].initial_state); + } + cs_mem_free(utest_table); + stats->failed += failed_tests; + stats->successful += stats->tc_total - failed_tests - stats->skipped; +} + +/// Runs runs all valid tests in the given @test_files +/// and returns the result as well as statistics in @stats. +TestRunResult cstest_run_tests(char **test_file_paths, uint32_t path_count, + TestRunStats *stats) +{ + TestFile **files = parse_test_files(test_file_paths, path_count, stats); + if (!files) { + return get_test_run_result(stats); + } + eval_test_cases(files, stats); + for (size_t i = 0; i < stats->valid_test_files; ++i) { + test_file_free(files[i]); + } + cs_mem_free(files); + + return get_test_run_result(stats); +} diff --git a/suite/cstest/src/tms320c64x_detail.c b/suite/cstest/src/tms320c64x_detail.c deleted file mode 100644 index f6b0b9185b..0000000000 --- a/suite/cstest/src/tms320c64x_detail.c +++ /dev/null @@ -1,107 +0,0 @@ -/* Capstone testing regression */ -/* By Do Minh Tuan , 02-2019 */ - - -#include "factory.h" - -char *get_detail_tms320c64x(csh *handle, cs_mode mode, cs_insn *ins) -{ - cs_tms320c64x *tms320c64x; - int i; - char *result; - - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; - - if (ins->detail == NULL) - return result; - - tms320c64x = &(ins->detail->tms320c64x); - if (tms320c64x->op_count) - add_str(&result, " ; op_count: %u", tms320c64x->op_count); - - for (i = 0; i < tms320c64x->op_count; i++) { - cs_tms320c64x_op *op = &(tms320c64x->operands[i]); - switch((int)op->type) { - default: - break; - case TMS320C64X_OP_REG: - add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); - break; - case TMS320C64X_OP_IMM: - add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm); - break; - case TMS320C64X_OP_MEM: - add_str(&result, " ; operands[%u].type: MEM", i); - if (op->mem.base != TMS320C64X_REG_INVALID) - add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); - add_str(&result, " ; operands[%u].mem.disptype: ", i); - if (op->mem.disptype == TMS320C64X_MEM_DISP_INVALID) { - add_str(&result, "Invalid"); - add_str(&result, " ; operands[%u].mem.disp: %u", i, op->mem.disp); - } - if (op->mem.disptype == TMS320C64X_MEM_DISP_CONSTANT) { - add_str(&result, "Constant"); - add_str(&result, " ; operands[%u].mem.disp: %u", i, op->mem.disp); - } - if (op->mem.disptype == TMS320C64X_MEM_DISP_REGISTER) { - add_str(&result, "Register"); - add_str(&result, " ; operands[%u].mem.disp: %s", i, cs_reg_name(*handle, op->mem.disp)); - } - add_str(&result, " ; operands[%u].mem.unit: %u", i, op->mem.unit); - add_str(&result, " ; operands[%u].mem.direction: ", i); - if (op->mem.direction == TMS320C64X_MEM_DIR_INVALID) - add_str(&result, "Invalid"); - if (op->mem.direction == TMS320C64X_MEM_DIR_FW) - add_str(&result, "Forward"); - if (op->mem.direction == TMS320C64X_MEM_DIR_BW) - add_str(&result, "Backward"); - add_str(&result, " ; operands[%u].mem.modify: ", i); - if (op->mem.modify == TMS320C64X_MEM_MOD_INVALID) - add_str(&result, "Invalid"); - if (op->mem.modify == TMS320C64X_MEM_MOD_NO) - add_str(&result, "No"); - if (op->mem.modify == TMS320C64X_MEM_MOD_PRE) - add_str(&result, "Pre"); - if (op->mem.modify == TMS320C64X_MEM_MOD_POST) - add_str(&result, "Post"); - add_str(&result, " ; operands[%u].mem.scaled: %u", i, op->mem.scaled); - - break; - case TMS320C64X_OP_REGPAIR: - add_str(&result, " ; operands[%u].type: REGPAIR = %s:%s", i, cs_reg_name(*handle, op->reg + 1), cs_reg_name(*handle, op->reg)); - break; - } - } - - add_str(&result, " ; Functional unit: "); - switch(tms320c64x->funit.unit) { - case TMS320C64X_FUNIT_D: - add_str(&result, "D%u", tms320c64x->funit.side); - break; - case TMS320C64X_FUNIT_L: - add_str(&result, "L%u", tms320c64x->funit.side); - break; - case TMS320C64X_FUNIT_M: - add_str(&result, "M%u", tms320c64x->funit.side); - break; - case TMS320C64X_FUNIT_S: - add_str(&result, "S%u", tms320c64x->funit.side); - break; - case TMS320C64X_FUNIT_NO: - add_str(&result, "No Functional Unit"); - break; - default: - add_str(&result, "Unknown (Unit %u, Side %u)", tms320c64x->funit.unit, tms320c64x->funit.side); - break; - } - if (tms320c64x->funit.crosspath == 1) - add_str(&result, " ; Crosspath: 1"); - - if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID) - add_str(&result, " ; Condition: [%c%s]", (tms320c64x->condition.zero == 1) ? '!' : ' ', cs_reg_name(*handle, tms320c64x->condition.reg)); - add_str(&result, " ; Parallel: %s", (tms320c64x->parallel == 1) ? "true" : "false"); - - return result; -} - diff --git a/suite/cstest/src/tricore_detail.c b/suite/cstest/src/tricore_detail.c deleted file mode 100644 index 462d64aeaa..0000000000 --- a/suite/cstest/src/tricore_detail.c +++ /dev/null @@ -1,81 +0,0 @@ -// -// Created by aya on 3/24/23. -// - -#include "factory.h" - -char *get_detail_tricore(csh *p_handle, cs_mode mode, cs_insn *ins) -{ - cs_tricore *tricore; - int i; - cs_regs regs_read, regs_write; - uint8_t regs_read_count, regs_write_count; - - char *result; - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; - - if (ins->detail == NULL) - return result; - - csh handle = *p_handle; - - tricore = &(ins->detail->tricore); - - if (tricore->op_count) - add_str(&result, "\top_count: %u\n", tricore->op_count); - - for (i = 0; i < tricore->op_count; i++) { - cs_tricore_op *op = &(tricore->operands[i]); - switch ((int)op->type) { - default: - break; - case TRICORE_OP_REG: - add_str(&result, "\t\toperands[%u].type: REG = %s\n", i, - cs_reg_name(handle, op->reg)); - break; - case TRICORE_OP_IMM: - add_str(&result, "\t\toperands[%u].type: IMM = 0x%x\n", - i, op->imm); - break; - case TRICORE_OP_MEM: - add_str(&result, "\t\toperands[%u].type: MEM\n", i); - if (op->mem.base != TRICORE_REG_INVALID) - add_str(&result, - "\t\t\toperands[%u].mem.base: REG = %s\n", - i, cs_reg_name(handle, op->mem.base)); - if (op->mem.disp != 0) - add_str(&result, - "\t\t\toperands[%u].mem.disp: 0x%x\n", - i, op->mem.disp); - break; - } - - // Print out all registers accessed by this instruction (either implicit or - // explicit) - if (!cs_regs_access(handle, ins, regs_read, ®s_read_count, - regs_write, ®s_write_count)) { - if (regs_read_count) { - add_str(&result, "\tRegisters read:"); - for (i = 0; i < regs_read_count; i++) { - add_str(&result, " %s", - cs_reg_name(handle, - regs_read[i])); - } - add_str(&result, "\n"); - } - - if (regs_write_count) { - add_str(&result, "\tRegisters modified:"); - for (i = 0; i < regs_write_count; i++) { - add_str(&result, " %s", - cs_reg_name(handle, - regs_write[i])); - } - add_str(&result, "\n"); - } - } - } - - return result; -} diff --git a/suite/cstest/src/x86_detail.c b/suite/cstest/src/x86_detail.c deleted file mode 100644 index 9d02bf7cc1..0000000000 --- a/suite/cstest/src/x86_detail.c +++ /dev/null @@ -1,345 +0,0 @@ -/* Capstone testing regression */ -/* By Do Minh Tuan , 02-2019 */ - - -#include "factory.h" - -static void print_string_hex(char **result, const char *comment, unsigned char *str, size_t len) -{ - unsigned char *c; - - add_str(result, "%s", comment); - for (c = str; c < str + len; c++) { - add_str(result, "0x%02x", *c & 0xff); - if (c < str + len - 1) - add_str(result, " "); - } - -} - -static const char *get_eflag_name(uint64_t flag) -{ - switch(flag) { - default: - return NULL; - case X86_EFLAGS_UNDEFINED_OF: - return "UNDEF_OF"; - case X86_EFLAGS_UNDEFINED_SF: - return "UNDEF_SF"; - case X86_EFLAGS_UNDEFINED_ZF: - return "UNDEF_ZF"; - case X86_EFLAGS_MODIFY_AF: - return "MOD_AF"; - case X86_EFLAGS_UNDEFINED_PF: - return "UNDEF_PF"; - case X86_EFLAGS_MODIFY_CF: - return "MOD_CF"; - case X86_EFLAGS_MODIFY_SF: - return "MOD_SF"; - case X86_EFLAGS_MODIFY_ZF: - return "MOD_ZF"; - case X86_EFLAGS_UNDEFINED_AF: - return "UNDEF_AF"; - case X86_EFLAGS_MODIFY_PF: - return "MOD_PF"; - case X86_EFLAGS_UNDEFINED_CF: - return "UNDEF_CF"; - case X86_EFLAGS_MODIFY_OF: - return "MOD_OF"; - case X86_EFLAGS_RESET_OF: - return "RESET_OF"; - case X86_EFLAGS_RESET_CF: - return "RESET_CF"; - case X86_EFLAGS_RESET_DF: - return "RESET_DF"; - case X86_EFLAGS_RESET_IF: - return "RESET_IF"; - case X86_EFLAGS_RESET_ZF: - return "RESET_ZF"; - case X86_EFLAGS_TEST_OF: - return "TEST_OF"; - case X86_EFLAGS_TEST_SF: - return "TEST_SF"; - case X86_EFLAGS_TEST_ZF: - return "TEST_ZF"; - case X86_EFLAGS_TEST_PF: - return "TEST_PF"; - case X86_EFLAGS_TEST_CF: - return "TEST_CF"; - case X86_EFLAGS_RESET_SF: - return "RESET_SF"; - case X86_EFLAGS_RESET_AF: - return "RESET_AF"; - case X86_EFLAGS_RESET_TF: - return "RESET_TF"; - case X86_EFLAGS_RESET_NT: - return "RESET_NT"; - case X86_EFLAGS_PRIOR_OF: - return "PRIOR_OF"; - case X86_EFLAGS_PRIOR_SF: - return "PRIOR_SF"; - case X86_EFLAGS_PRIOR_ZF: - return "PRIOR_ZF"; - case X86_EFLAGS_PRIOR_AF: - return "PRIOR_AF"; - case X86_EFLAGS_PRIOR_PF: - return "PRIOR_PF"; - case X86_EFLAGS_PRIOR_CF: - return "PRIOR_CF"; - case X86_EFLAGS_PRIOR_TF: - return "PRIOR_TF"; - case X86_EFLAGS_PRIOR_IF: - return "PRIOR_IF"; - case X86_EFLAGS_PRIOR_DF: - return "PRIOR_DF"; - case X86_EFLAGS_TEST_NT: - return "TEST_NT"; - case X86_EFLAGS_TEST_DF: - return "TEST_DF"; - case X86_EFLAGS_RESET_PF: - return "RESET_PF"; - case X86_EFLAGS_PRIOR_NT: - return "PRIOR_NT"; - case X86_EFLAGS_MODIFY_TF: - return "MOD_TF"; - case X86_EFLAGS_MODIFY_IF: - return "MOD_IF"; - case X86_EFLAGS_MODIFY_DF: - return "MOD_DF"; - case X86_EFLAGS_MODIFY_NT: - return "MOD_NT"; - case X86_EFLAGS_MODIFY_RF: - return "MOD_RF"; - case X86_EFLAGS_SET_CF: - return "SET_CF"; - case X86_EFLAGS_SET_DF: - return "SET_DF"; - case X86_EFLAGS_SET_IF: - return "SET_IF"; - case X86_EFLAGS_SET_OF: - return "SET_OF"; - case X86_EFLAGS_SET_SF: - return "SET_SF"; - case X86_EFLAGS_SET_ZF: - return "SET_ZF"; - case X86_EFLAGS_SET_AF: - return "SET_AF"; - case X86_EFLAGS_SET_PF: - return "SET_PF"; - case X86_EFLAGS_TEST_AF: - return "TEST_AF"; - case X86_EFLAGS_TEST_TF: - return "TEST_TF"; - case X86_EFLAGS_TEST_RF: - return "TEST_RF"; - case X86_EFLAGS_RESET_0F: - return "RESET_0F"; - case X86_EFLAGS_RESET_AC: - return "RESET_AC"; - } -} - -static const char *get_fpu_flag_name(uint64_t flag) -{ - switch (flag) { - default: - return NULL; - case X86_FPU_FLAGS_MODIFY_C0: - return "MOD_C0"; - case X86_FPU_FLAGS_MODIFY_C1: - return "MOD_C1"; - case X86_FPU_FLAGS_MODIFY_C2: - return "MOD_C2"; - case X86_FPU_FLAGS_MODIFY_C3: - return "MOD_C3"; - case X86_FPU_FLAGS_RESET_C0: - return "RESET_C0"; - case X86_FPU_FLAGS_RESET_C1: - return "RESET_C1"; - case X86_FPU_FLAGS_RESET_C2: - return "RESET_C2"; - case X86_FPU_FLAGS_RESET_C3: - return "RESET_C3"; - case X86_FPU_FLAGS_SET_C0: - return "SET_C0"; - case X86_FPU_FLAGS_SET_C1: - return "SET_C1"; - case X86_FPU_FLAGS_SET_C2: - return "SET_C2"; - case X86_FPU_FLAGS_SET_C3: - return "SET_C3"; - case X86_FPU_FLAGS_UNDEFINED_C0: - return "UNDEF_C0"; - case X86_FPU_FLAGS_UNDEFINED_C1: - return "UNDEF_C1"; - case X86_FPU_FLAGS_UNDEFINED_C2: - return "UNDEF_C2"; - case X86_FPU_FLAGS_UNDEFINED_C3: - return "UNDEF_C3"; - case X86_FPU_FLAGS_TEST_C0: - return "TEST_C0"; - case X86_FPU_FLAGS_TEST_C1: - return "TEST_C1"; - case X86_FPU_FLAGS_TEST_C2: - return "TEST_C2"; - case X86_FPU_FLAGS_TEST_C3: - return "TEST_C3"; - } -} - -char *get_detail_x86(csh *ud, cs_mode mode, cs_insn *ins) -{ - int count, i; - cs_x86 *x86; - cs_regs regs_read, regs_write; - uint8_t regs_read_count, regs_write_count; - char *result; - - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; - - if (ins->detail == NULL) - return result; - - x86 = &(ins->detail->x86); - - add_str(&result, " ; ID: %" PRIu32 , ins->id); - print_string_hex(&result, " ; Prefix:", x86->prefix, 4); - print_string_hex(&result, " ; Opcode:", x86->opcode, 4); - add_str(&result, " ; rex: 0x%x", x86->rex); - add_str(&result, " ; addr_size: %u", x86->addr_size); - add_str(&result, " ; modrm: 0x%x", x86->modrm); - add_str(&result, " ; disp: 0x%" PRIx64 "", x86->disp); - - if ((mode & CS_MODE_16) == 0) { - add_str(&result, " ; sib: 0x%x", x86->sib); - if (x86->sib_base != X86_REG_INVALID) - add_str(&result, " ; sib_base: %s", cs_reg_name(*ud, x86->sib_base)); - if (x86->sib_index != X86_REG_INVALID) - add_str(&result, " ; sib_index: %s", cs_reg_name(*ud, x86->sib_index)); - if (x86->sib_scale != 0) - add_str(&result, " ; sib_scale: %d", x86->sib_scale); - } - - if (x86->xop_cc != X86_XOP_CC_INVALID) { - add_str(&result, " ; xop_cc: %u", x86->xop_cc); - } - - if (x86->sse_cc != X86_SSE_CC_INVALID) { - add_str(&result, " ; sse_cc: %u", x86->sse_cc); - } - - if (x86->avx_cc != X86_AVX_CC_INVALID) { - add_str(&result, " ; avx_cc: %u", x86->avx_cc); - } - - if (x86->avx_sae) { - add_str(&result, " ; avx_sae: %u", x86->avx_sae); - } - - if (x86->avx_rm != X86_AVX_RM_INVALID) { - add_str(&result, " ; avx_rm: %u", x86->avx_rm); - } - - count = cs_op_count(*ud, ins, X86_OP_IMM); - if (count > 0) { - add_str(&result, " ; imm_count: %u", count); - for (i = 1; i < count + 1; i++) { - int index = cs_op_index(*ud, ins, X86_OP_IMM, i); - add_str(&result, " ; imms[%u]: 0x%" PRIx64 "", i, x86->operands[index].imm); - } - } - - if (x86->op_count) - add_str(&result, " ; op_count: %u", x86->op_count); - - for (i = 0; i < x86->op_count; i++) { - cs_x86_op *op = &(x86->operands[i]); - - switch((int)op->type) { - case X86_OP_REG: - add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*ud, op->reg)); - break; - case X86_OP_IMM: - add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm); - break; - case X86_OP_MEM: - add_str(&result, " ; operands[%u].type: MEM", i); - if (op->mem.segment != X86_REG_INVALID) - add_str(&result, " ; operands[%u].mem.segment: REG = %s", i, cs_reg_name(*ud, op->mem.segment)); - if (op->mem.base != X86_REG_INVALID) - add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*ud, op->mem.base)); - if (op->mem.index != X86_REG_INVALID) - add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*ud, op->mem.index)); - if (op->mem.scale != 1) - add_str(&result, " ; operands[%u].mem.scale: %u", i, op->mem.scale); - if (op->mem.disp != 0) - add_str(&result, " ; operands[%u].mem.disp: 0x%" PRIx64 "", i, op->mem.disp); - break; - default: - break; - } - - if (op->avx_bcast != X86_AVX_BCAST_INVALID) - add_str(&result, " ; operands[%u].avx_bcast: %u", i, op->avx_bcast); - - if (op->avx_zero_opmask != false) - add_str(&result, " ; operands[%u].avx_zero_opmask: TRUE", i); - - add_str(&result, " ; operands[%u].size: %u", i, op->size); - - switch(op->access) { - default: - break; - case CS_AC_READ: - add_str(&result, " ; operands[%u].access: READ", i); - break; - case CS_AC_WRITE: - add_str(&result, " ; operands[%u].access: WRITE", i); - break; - case CS_AC_READ | CS_AC_WRITE: - add_str(&result, " ; operands[%u].access: READ | WRITE", i); - break; - } - } - - if (!cs_regs_access(*ud, ins, regs_read, ®s_read_count, regs_write, ®s_write_count)) { - if (regs_read_count) { - add_str(&result, " ; Registers read:"); - for(i = 0; i < regs_read_count; i++) { - add_str(&result, " %s", cs_reg_name(*ud, regs_read[i])); - } - } - - if (regs_write_count) { - add_str(&result, " ; Registers modified:"); - for(i = 0; i < regs_write_count; i++) { - add_str(&result, " %s", cs_reg_name(*ud, regs_write[i])); - } - } - } - - if (x86->eflags || x86->fpu_flags) { - for(i = 0; i < ins->detail->groups_count; i++) { - if (ins->detail->groups[i] == X86_GRP_FPU) { - add_str(&result, " ; FPU_FLAGS:"); - for(i = 0; i <= 63; i++) - if (x86->fpu_flags & ((uint64_t)1 << i)) { - add_str(&result, " %s", get_fpu_flag_name((uint64_t)1 << i)); - } - break; - } - } - - if (i == ins->detail->groups_count) { - add_str(&result, " ; EFLAGS:"); - for(i = 0; i <= 63; i++) - if (x86->eflags & ((uint64_t)1 << i)) { - add_str(&result, " %s", get_eflag_name((uint64_t)1 << i)); - } - } - } - - return result; -} - diff --git a/suite/cstest/src/xcore_detail.c b/suite/cstest/src/xcore_detail.c deleted file mode 100644 index d4f51f8180..0000000000 --- a/suite/cstest/src/xcore_detail.c +++ /dev/null @@ -1,52 +0,0 @@ -/* Capstone testing regression */ -/* By Do Minh Tuan , 02-2019 */ - - -#include "factory.h" - -char *get_detail_xcore(csh *handle, cs_mode mode, cs_insn *ins) -{ - cs_xcore *xcore; - int i; - char *result; - - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; - - if (ins->detail == NULL) - return result; - - xcore = &(ins->detail->xcore); - if (xcore->op_count) - add_str(&result, " ; op_count: %u", xcore->op_count); - - for (i = 0; i < xcore->op_count; i++) { - cs_xcore_op *op = &(xcore->operands[i]); - switch((int)op->type) { - default: - break; - case XCORE_OP_REG: - add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); - break; - case XCORE_OP_IMM: - add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm); - break; - case XCORE_OP_MEM: - add_str(&result, " ; operands[%u].type: MEM", i); - if (op->mem.base != XCORE_REG_INVALID) - add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); - if (op->mem.index != XCORE_REG_INVALID) - add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index)); - if (op->mem.disp != 0) - add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); - if (op->mem.direct != 1) - add_str(&result, " ; operands[%u].mem.direct: -1", i); - - - break; - } - } - - return result; -} - diff --git a/suite/cstest/test/CMakeLists.txt b/suite/cstest/test/CMakeLists.txt new file mode 100644 index 0000000000..b1c56cf592 --- /dev/null +++ b/suite/cstest/test/CMakeLists.txt @@ -0,0 +1,23 @@ +cmake_minimum_required(VERSION 3.15) + +set(CSTEST_TEST_SRC_DIR ${CSTEST_TEST_DIR}/src) +set(CSTEST_TEST_INC_DIR ${CSTEST_TEST_DIR}/include) + +include_directories(${CSTEST_TEST_INC_DIR} + ${CSTEST_INCLUDE_DIR} + ${PROJECT_SOURCE_DIR} + ${PROJECT_SOURCE_DIR}/include) + +file(GLOB CSTEST_TEST_SRC ${CSTEST_TEST_SRC_DIR}/*.c) +add_executable(unit_test ${CSTEST_TEST_SRC}) +add_dependencies(unit_test libcstest) +target_link_libraries(unit_test PUBLIC libcstest) + +add_test(NAME UnitCSTest + COMMAND unit_test + WORKING_DIRECTORY ${CSTEST_TEST_DIR} +) +add_test(NAME IntegrationCSTest + COMMAND python3 ${CSTEST_TEST_DIR}/integration_tests.py cstest + WORKING_DIRECTORY ${CSTEST_TEST_DIR} +) diff --git a/suite/cstest/test/README.md b/suite/cstest/test/README.md new file mode 100644 index 0000000000..eb169ab5c0 --- /dev/null +++ b/suite/cstest/test/README.md @@ -0,0 +1 @@ +Integration tests of cstest diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/test_c.txt b/suite/cstest/test/empty_test_file.yaml similarity index 100% rename from suite/auto-sync/src/autosync/Tests/MCUpdaterTests/test_c.txt rename to suite/cstest/test/empty_test_file.yaml diff --git a/suite/cstest/test/integration_tests.py b/suite/cstest/test/integration_tests.py new file mode 100755 index 0000000000..6ca6d57117 --- /dev/null +++ b/suite/cstest/test/integration_tests.py @@ -0,0 +1,134 @@ +#!/usr/bin/env python3 + +# Copyright © 2024 Rot127 +# SPDX-License-Identifier: BSD-3 + +# Typing for Python3.8 +from __future__ import annotations + +import sys +import subprocess as sp + +from pathlib import Path + + +def check(cmd: list[str], expected_stdout: str, expected_stderr: str, fail_msg: str): + print(f"Run: {' '.join(cmd)}") + result = sp.run(cmd, capture_output=True) + stderr = result.stderr.decode("utf8") + stdout = result.stdout.decode("utf8") + if expected_stderr and expected_stderr not in stderr: + print(f"STDERR mismatch: '{expected_stderr}' not in stderr") + print("\n###################### STDERR ######################\n") + print(stderr) + print("####################################################\n") + print(fail_msg) + exit(1) + if expected_stdout and expected_stdout not in stdout: + print(f"STDOUT mismatch: '{expected_stdout}' not in stdout") + print("\n###################### STDOUT ######################\n") + print(stdout) + print("####################################################\n") + print(fail_msg) + exit(1) + + +def run_tests(cmd: str): + p = ( + sp.run(["git", "rev-parse", "--show-toplevel"], check=True, capture_output=True) + .stdout.decode("utf8") + .strip() + ) + path = Path(p).joinpath("suite").joinpath("cstest").joinpath("test") + + cmd = cmd.split(" ") + check( + cmd + [f"{path.joinpath('empty_test_file.yaml')}"], + expected_stderr="Failed to parse test file ", + expected_stdout="", + fail_msg="Failed the empty file test", + ) + + check( + cmd + [f"{path.joinpath('missing_madatory_field.yaml')}"], + expected_stderr="Error: 'Missing required mapping field'", + expected_stdout="", + fail_msg="Failed the mandatory field test", + ) + + check( + cmd + [f"{path.joinpath('invalid_test_file.yaml')}"], + expected_stderr="Error: 'libyaml parser error'", + expected_stdout="", + fail_msg="Failed the invalid test file test", + ) + + check( + cmd + [f"{path.joinpath('min_valid_test_file.yaml')}"], + expected_stdout="All tests succeeded.", + expected_stderr="", + fail_msg="Failed the minimal valid parsing test", + ) + + check( + cmd + [f"{path.joinpath('invalid_cs_input.yaml')}"], + expected_stderr="'ar' is not mapped to a capstone architecture.", + expected_stdout="", + fail_msg="Test: Invalid CS option failed", + ) + + check( + cmd + [f"{path.joinpath('invalid_cs_input.yaml')}"], + expected_stderr="0 != 0x1", + expected_stdout="", + fail_msg="Test: Wrong number of instruction disassembled failed", + ) + + check( + cmd + [f"{path.joinpath('invalid_cs_input.yaml')}"], + expected_stderr="Option: 'thum' not used", + expected_stdout="", + fail_msg="Test: Invalid disassembly due to wrong option failed", + ) + + check( + cmd + [f"{path}"], + expected_stdout="Test files found: 6", + expected_stderr="", + fail_msg="Test: Detecting file in directory failed.", + ) + + if "cstest_py" in cmd: + check( + cmd + + [ + f"{path}", + "-e", + "invalid_cs_input.yaml", + "-i", + "invalid_cs_input.yaml", + "min_valid_test_file.yaml", + "-v", + "debug", + ], + expected_stdout="Test files found: 2", + expected_stderr="", + fail_msg="Test: Detecting file in directory failed.", + ) + + +def print_usage_exit(): + print(f'{sys.argv[0]} "cstest_command"') + print('"cstest_command" examples:') + print('\t"python3 ../../bindings/python/cstest.py"') + print("\tcstest") + exit(1) + + +if __name__ == "__main__": + if len(sys.argv) != 2: + print_usage_exit() + + run_tests(sys.argv[1]) + print("All tests passed") + exit(0) diff --git a/suite/cstest/test/invalid_cs_input.yaml b/suite/cstest/test/invalid_cs_input.yaml new file mode 100644 index 0000000000..62f760d291 --- /dev/null +++ b/suite/cstest/test/invalid_cs_input.yaml @@ -0,0 +1,29 @@ +test_cases: + - + input: + bytes: [ 0x05, 0xb0, 0xa0, 0xe1 ] + arch: "ar" # Wrong arch + options: ["arm"] + expected: + insns: + - + asm_text: "mov r11, r5" + - + input: + bytes: [ 0x06 ] # Wrong number of bytes. + arch: "aarch64" + options: [] + expected: + insns: + - + asm_text: "mov r1, r6" + - + input: + bytes: [ 0xc2, 0xf3, 0x00, 0x8f ] + arch: "arm" + options: ["thum"] # Wrong mode + expected: + insns: + - + asm_text: "bxj r2" + diff --git a/suite/cstest/test/invalid_test_file.yaml b/suite/cstest/test/invalid_test_file.yaml new file mode 100644 index 0000000000..075cd4078f --- /dev/null +++ b/suite/cstest/test/invalid_test_file.yaml @@ -0,0 +1,11 @@ +test_cases: + - + input: + bytes: [ 0x05, 0xb0, 0xa0, 0xe1 ] + arch: "arm" + options: ["arm"] + expected: + insns: + - + op_str: "mov r11, r5" + # Invisble tab diff --git a/suite/cstest/test/min_valid_test_file.yaml b/suite/cstest/test/min_valid_test_file.yaml new file mode 100644 index 0000000000..c67c1f6c75 --- /dev/null +++ b/suite/cstest/test/min_valid_test_file.yaml @@ -0,0 +1,31 @@ +test_cases: + - + input: + bytes: [ 0x05, 0xb0, 0xa0, 0xe1 ] + arch: "arm" + options: ["arm"] + expected: + insns: + - + asm_text: "mov r11, r5" + - + input: + bytes: [ 0x06, 0x10, 0xa0, 0xe1 ] + arch: "arm" + options: ["arm"] + expected: + insns: + - + asm_text: "mov r1, r6" + - + input: + bytes: [ 0x06, 0x10, 0xa0, 0xe1, 0x05, 0xb0, 0xa0, 0xe1 ] + arch: "arm" + options: ["arm"] + expected: + insns: + - + asm_text: "mov r1, r6" + - + asm_text: "mov r11, r5" + diff --git a/suite/cstest/test/missing_madatory_field.yaml b/suite/cstest/test/missing_madatory_field.yaml new file mode 100644 index 0000000000..5778dbf25d --- /dev/null +++ b/suite/cstest/test/missing_madatory_field.yaml @@ -0,0 +1,8 @@ +test_cases: + - + input: + arch: "arm" + expected: + insns: + - + op_str: "mov r11, r5" diff --git a/suite/cstest/test/some_dir/some_other_dir/min_valid_test_file.yaml b/suite/cstest/test/some_dir/some_other_dir/min_valid_test_file.yaml new file mode 100644 index 0000000000..c67c1f6c75 --- /dev/null +++ b/suite/cstest/test/some_dir/some_other_dir/min_valid_test_file.yaml @@ -0,0 +1,31 @@ +test_cases: + - + input: + bytes: [ 0x05, 0xb0, 0xa0, 0xe1 ] + arch: "arm" + options: ["arm"] + expected: + insns: + - + asm_text: "mov r11, r5" + - + input: + bytes: [ 0x06, 0x10, 0xa0, 0xe1 ] + arch: "arm" + options: ["arm"] + expected: + insns: + - + asm_text: "mov r1, r6" + - + input: + bytes: [ 0x06, 0x10, 0xa0, 0xe1, 0x05, 0xb0, 0xa0, 0xe1 ] + arch: "arm" + options: ["arm"] + expected: + insns: + - + asm_text: "mov r1, r6" + - + asm_text: "mov r11, r5" + diff --git a/suite/cstest/test/src/unit_tests.c b/suite/cstest/test/src/unit_tests.c new file mode 100644 index 0000000000..fcc34e4be1 --- /dev/null +++ b/suite/cstest/test/src/unit_tests.c @@ -0,0 +1,74 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "../../../utils.h" +#include "../../../Mapping.h" +#include "test_mapping.h" +#include + +bool test_cs_enum_get_val() +{ + bool found = false; + // Get first value + uint32_t val = enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), + "AAAAAAAAAAAAAAAAAAAAAAAAAA", + &found); + if (!found || val != 0xffffff) { + fprintf(stderr, + "enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), AAAAAAAAAAAAAAAAAAAAAAAAAA) failed is %d.\n", + val); + return false; + } + + // Get last value + val = enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), + "zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz", &found); + if (!found || val != 0xffffff) { + fprintf(stderr, + "enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz) failed is %d.\n", + val); + return false; + } + + // Some values + val = enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), + "AArch64CC_EQ", &found); + if (!found || val != AArch64CC_EQ) { + fprintf(stderr, + "enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), AArch64CC_EQ) failed is %d.\n", + val); + return false; + } + val = enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), + "AArch64CC_Invalid", &found); + if (!found || val != AArch64CC_Invalid) { + fprintf(stderr, + "enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), AArch64CC_In) failed is %d.\n", + val); + return false; + } + + enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), "\0", &found); + if (found) { + fprintf(stderr, "Out of bounds failed.\n"); + return false; + } + + enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), + "~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~", + &found); + if (found) { + fprintf(stderr, "Out of bounds failed.\n"); + return false; + } + + return true; +} + +int main() +{ + bool success = true; + success &= test_cs_enum_get_val(); + printf("test_cs_enum_get_val: %s\n", success ? "ok" : "fail"); + return success ? 0 : 1; +} diff --git a/suite/disasm_mc.py b/suite/disasm_mc.py deleted file mode 100755 index d0ad2caf57..0000000000 --- a/suite/disasm_mc.py +++ /dev/null @@ -1,193 +0,0 @@ -#!/usr/bin/python -# Test tool to disassemble MC files. By Nguyen Anh Quynh, 2017 -import array, os.path, sys -from capstone import * - - -# convert all hex numbers to decimal numbers in a text -def normalize_hex(a): - while(True): - i = a.find('0x') - if i == -1: # no more hex number - break - hexnum = '0x' - for c in a[i + 2:]: - if c in '0123456789abcdefABCDEF': - hexnum += c - else: - break - num = int(hexnum, 16) - a = a.replace(hexnum, str(num)) - return a - - -def test_file(fname): - print("Test %s" %fname); - f = open(fname) - lines = f.readlines() - f.close() - - if not lines[0].startswith('# '): - print("ERROR: decoding information is missing") - return - - # skip '# ' at the front, then split line to get out hexcode - # Note: option can be '', or 'None' - #print lines[0] - #print lines[0][2:].split(', ') - (arch, mode, option) = lines[0][2:].split(', ') - mode = mode.replace(' ', '') - option = option.strip() - - archs = { - "CS_ARCH_ARM": CS_ARCH_ARM, - "CS_ARCH_AARCH64": CS_ARCH_AARCH64, - "CS_ARCH_MIPS": CS_ARCH_MIPS, - "CS_ARCH_PPC": CS_ARCH_PPC, - "CS_ARCH_SPARC": CS_ARCH_SPARC, - "CS_ARCH_SYSZ": CS_ARCH_SYSZ, - "CS_ARCH_X86": CS_ARCH_X86, - "CS_ARCH_XCORE": CS_ARCH_XCORE, - "CS_ARCH_M68K": CS_ARCH_M68K, - "CS_ARCH_RISCV": CS_ARCH_RISCV, - } - - modes = { - "CS_MODE_16": CS_MODE_16, - "CS_MODE_32": CS_MODE_32, - "CS_MODE_64": CS_MODE_64, - "CS_MODE_MIPS32": CS_MODE_MIPS32, - "CS_MODE_MIPS64": CS_MODE_MIPS64, - "0": CS_MODE_ARM, - "CS_MODE_ARM": CS_MODE_ARM, - "CS_MODE_THUMB": CS_MODE_THUMB, - "CS_MODE_ARM+CS_MODE_V8": CS_MODE_ARM+CS_MODE_V8, - "CS_MODE_THUMB+CS_MODE_V8": CS_MODE_THUMB+CS_MODE_V8, - "CS_MODE_THUMB+CS_MODE_MCLASS": CS_MODE_THUMB+CS_MODE_MCLASS, - "CS_MODE_LITTLE_ENDIAN": CS_MODE_LITTLE_ENDIAN, - "CS_MODE_BIG_ENDIAN": CS_MODE_BIG_ENDIAN, - "CS_MODE_64+CS_MODE_LITTLE_ENDIAN": CS_MODE_64+CS_MODE_LITTLE_ENDIAN, - "CS_MODE_64+CS_MODE_BIG_ENDIAN": CS_MODE_64+CS_MODE_BIG_ENDIAN, - "CS_MODE_MIPS32+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO, - "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, - "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, - "CS_MODE_BIG_ENDIAN+CS_MODE_V9": CS_MODE_BIG_ENDIAN + CS_MODE_V9, - "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, - "CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN, - "CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN, - "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, - "CS_MODE_RISCV32": CS_MODE_RISCV32, - "CS_MODE_RISCV64": CS_MODE_RISCV64, - } - - options = { - "CS_OPT_SYNTAX_ATT": CS_OPT_SYNTAX_ATT, - "CS_OPT_SYNTAX_NOREGNAME": CS_OPT_SYNTAX_NOREGNAME, - } - - mc_modes = { - ("CS_ARCH_X86", "CS_MODE_32"): ['-triple=i386'], - ("CS_ARCH_X86", "CS_MODE_64"): ['-triple=x86_64'], - ("CS_ARCH_ARM", "CS_MODE_ARM"): ['-triple=armv7'], - ("CS_ARCH_ARM", "CS_MODE_THUMB"): ['-triple=thumbv7'], - ("CS_ARCH_ARM", "CS_MODE_ARM+CS_MODE_V8"): ['-triple=armv8'], - ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_V8"): ['-triple=thumbv8'], - ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_MCLASS"): ['-triple=thumbv7m'], - ("CS_ARCH_AARCH64", "0"): ['-triple=aarch64'], - ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN"): ['-triple=mips'], - ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO"): ['-triple=mipsel', '-mattr=+micromips'], - ("CS_ARCH_MIPS", "CS_MODE_MIPS64"): ['-triple=mips64el'], - ("CS_ARCH_MIPS", "CS_MODE_MIPS32"): ['-triple=mipsel'], - ("CS_ARCH_MIPS", "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN"): ['-triple=mips64'], - ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): ['-triple=mips', '-mattr=+micromips'], - ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO"): ['-triple=mips', '-mattr=+micromips'], - ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN"): ['-triple=powerpc64'], - ('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN'): ['-triple=sparc'], - ('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN+CS_MODE_V9'): ['-triple=sparcv9'], - ('CS_ARCH_SYSZ', '0'): ['-triple=s390x', '-mcpu=z196'], - ('CS_ARCH_RISCV', 'CS_MODE_RISCV32'): ['-triple=riscv32'], - ('CS_ARCH_RISCV', 'CS_MODE_RISCV64'): ['-triple=riscv64'], - } - - #if not option in ('', 'None'): - # print archs[arch], modes[mode], options[option] - - #print(arch, mode, option) - md = Cs(archs[arch], modes[mode]) - - if arch == 'CS_ARCH_ARM' or arch == 'CS_ARCH_PPC' : - md.syntax = CS_OPT_SYNTAX_NOREGNAME - - if fname.endswith('3DNow.s.cs'): - md.syntax = CS_OPT_SYNTAX_ATT - - for line in lines[1:]: - # ignore all the input lines having # in front. - if line.startswith('#'): - continue - #print("Check %s" %line) - code = line.split(' = ')[0] - asm = ''.join(line.split(' = ')[1:]) - hex_code = code.replace('0x', '') - hex_code = hex_code.replace(',', '') - hex_data = hex_code.decode('hex') - #hex_bytes = array.array('B', hex_data) - - x = list(md.disasm(hex_data, 0)) - if len(x) > 0: - if x[0].op_str != '': - cs_output = "%s %s" %(x[0].mnemonic, x[0].op_str) - else: - cs_output = x[0].mnemonic - else: - cs_output = 'FAILED to disassemble' - - cs_output2 = normalize_hex(cs_output) - cs_output2 = cs_output2.replace(' ', '') - - if arch == 'CS_ARCH_MIPS': - # normalize register alias names - cs_output2 = cs_output2.replace('$at', '$1') - cs_output2 = cs_output2.replace('$v0', '$2') - cs_output2 = cs_output2.replace('$v1', '$3') - - cs_output2 = cs_output2.replace('$a0', '$4') - cs_output2 = cs_output2.replace('$a1', '$5') - cs_output2 = cs_output2.replace('$a2', '$6') - cs_output2 = cs_output2.replace('$a3', '$7') - - cs_output2 = cs_output2.replace('$t0', '$8') - cs_output2 = cs_output2.replace('$t1', '$9') - cs_output2 = cs_output2.replace('$t2', '$10') - cs_output2 = cs_output2.replace('$t3', '$11') - cs_output2 = cs_output2.replace('$t4', '$12') - cs_output2 = cs_output2.replace('$t5', '$13') - cs_output2 = cs_output2.replace('$t6', '$14') - cs_output2 = cs_output2.replace('$t7', '$15') - cs_output2 = cs_output2.replace('$t8', '$24') - cs_output2 = cs_output2.replace('$t9', '$25') - - cs_output2 = cs_output2.replace('$s0', '$16') - cs_output2 = cs_output2.replace('$s1', '$17') - cs_output2 = cs_output2.replace('$s2', '$18') - cs_output2 = cs_output2.replace('$s3', '$19') - cs_output2 = cs_output2.replace('$s4', '$20') - cs_output2 = cs_output2.replace('$s5', '$21') - cs_output2 = cs_output2.replace('$s6', '$22') - cs_output2 = cs_output2.replace('$s7', '$23') - - cs_output2 = cs_output2.replace('$k0', '$26') - cs_output2 = cs_output2.replace('$k1', '$27') - - print("\t%s = %s" %(hex_code, cs_output)) - - -if __name__ == '__main__': - if len(sys.argv) == 1: - fnames = sys.stdin.readlines() - for fname in fnames: - test_file(fname.strip()) - else: - #print("Usage: ./test_mc.py ") - test_file(sys.argv[1]) - diff --git a/suite/disasm_mc.sh b/suite/disasm_mc.sh deleted file mode 100755 index 6b8936cd2c..0000000000 --- a/suite/disasm_mc.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/sh - -# This script test all architectures by default. - -find MC/ -name *.cs | ./disasm_mc.py - -# To test just one architecture, specify the corresponding dir: -# $ find MC/X86 -name *.cs | ./disasm_mc.py - -# To test just one input file, run disasm_mc.py with that file: -# $ ./disasm_mc.py MC/X86/x86-32-fma3.s.cs diff --git a/suite/fuzz/Makefile b/suite/fuzz/Makefile index 99f9106321..4c84681497 100644 --- a/suite/fuzz/Makefile +++ b/suite/fuzz/Makefile @@ -81,7 +81,7 @@ else $(link-static) endif -$(FUZZERBIN): FUZZLDFLAGS="-fsanitize=fuzzer" +$(FUZZERBIN): FUZZLDFLAGS="-fsanitize=fuzzer -fno-sanitize-coverage=stack-depth" $(FUZZERBIN): fuzz_disasm.o platform.o @mkdir -p $(@D) diff --git a/suite/gencstest.py b/suite/gencstest.py deleted file mode 100755 index 50618ded7a..0000000000 --- a/suite/gencstest.py +++ /dev/null @@ -1,145 +0,0 @@ -#!/usr/bin/env python3 - -import sys -import re -import argparse -from pathlib import Path - -# 80001c1a : -# 80001c1a: 40 4f mov.aa %a15,%a4 -# 80001c1c: 02 48 mov %d8,%d4 -# 80001c1e: 6d ff 9d ff call 80001b58 - -unique_set = set() - - -def num2prefix_hex(x, prefix="#"): - if x.startswith("0x") or x.startswith("-0x") or x == "0": - x = prefix + x - if x.isdigit() or (x.startswith("-") and x[1:].isdigit()): - x = prefix + hex(int(x)) - return x - -def op2prefix_hex(x): - x = num2prefix_hex(x) - if "]" in x: - xs = x.split("]") - if xs[1].isdigit() or xs[1].startswith('-'): - x = xs[0] + "]" + num2prefix_hex(xs[1]) - return x - -def gen(filename): - with open(filename, "r") as f: - for line in f: - caps = re.findall( - r"([0-9a-f]+):\s+([0-9a-f]+) ([0-9a-f]+) ([0-9a-f]+)? ([0-9a-f]+)?\s+" - r"(\S+) (\S+)", - line, - ) - if not caps: - continue - caps = caps[0] - addr = int(caps[0], 16) - hexstr = caps[1:5] - mnemonic: str = caps[5] - operands = caps[6] - - def try_dedisp(x): - try: - disp = int(x, 16) - if disp > 0x80000000: - x = hex(disp - addr) - return x - except ValueError: - pass - return x - - def is_hex_string(s: str) -> bool: - if not s.isalnum(): - return False - return all(c.isdigit() or c.lower() in "abcdef" for c in s) and any( - c.lower() in "abcdef" for c in s - ) - - hexstr = ",".join(f"0x{x}" for x in hexstr if x) - fun = re.match(r"\s*<.+>\s*", operands) - # print(hex(addr), hexstr, mnemonic, operands) - if any( - [ - mnemonic.startswith(pre) - for pre in [ - "mtcr", - "mfcr", - "st.a", - "st.b", - "st.d", - "st.w", - "ld.a", - "ld.b", - "ld.d", - "ld.w", - ] - ] - ): - # unique_set.add(f"# {hexstr.ljust(19)} = {mnemonic}\t{operands}") - continue - - ops = operands.split(",") - if ( - any( - [mnemonic.startswith(pre) for pre in ["j", "call", "loop", "fcall"]] - ) - or fun - ): - re.sub(r"\s*<.+>\s*", "", operands) - # de relative addressing - ops = list(map(try_dedisp, ops)) - - for i, x in enumerate(ops): - if is_hex_string(x) and not x.startswith("0x"): - x = "#0x" + x - x = op2prefix_hex(x) - ops[i] = x - - operands = ", ".join(ops) - operands = operands.replace("%", "") - unique_set.add(f"{hexstr.ljust(19)} = {mnemonic}\t{operands}") - - print("# CS_ARCH_TRICORE, CS_MODE_TRICORE_162, None") - print("\n".join(unique_set)) - -def att2intel(filename): - with open(filename, "r") as fp: - lines = [] - for line in fp.readlines(): - if not '=' in line: - lines.append(line) - continue - insn = line.split('=') - hexstr = insn[0] - insn = insn[1] - ops = insn.strip().split(', ') - ops = ops[0].split('\t') + ops[1:] - mnemonic = ops[0] - ops = ops[1:] - for i,op in enumerate(ops): - op = op.strip() - op = op2prefix_hex(op) - ops[i] = op - operands = ", ".join(ops) - lines.append(f"{hexstr.ljust(19)} = {mnemonic}\t{operands}") - print('\n'.join(lines)) - -def main(): - parser = argparse.ArgumentParser(description="Convert objdump's output to .s.cs test file") - parser.add_argument('input', type=Path, help='input file path') - parser.add_argument('--intel', action='store_true', help='convert .s.cs file to intel syntax') - args = parser.parse_args() - if not args.intel: - gen(args.input) - else: - att2intel(args.input) - - -if __name__ == "__main__": - main() diff --git a/suite/regress/LICENSE b/suite/regress/LICENSE deleted file mode 100644 index dd85900f20..0000000000 --- a/suite/regress/LICENSE +++ /dev/null @@ -1,30 +0,0 @@ -This is the software license for Unicorn regression tests. The regression tests -are written by several Unicorn contributors (See CREDITS.TXT) and maintained by -Hoang-Vu Dang - -Copyright (c) 2015, Unicorn contributors -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. -* Neither the name of the developer(s) nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. diff --git a/suite/regress/Makefile b/suite/regress/Makefile deleted file mode 100644 index bbc73c74a9..0000000000 --- a/suite/regress/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -LIBNAME = capstone - -invalid_read_in_print_operand: invalid_read_in_print_operand.o - ${CC} $< -O3 -Wall -l$(LIBNAME) -o $@ - -%.o: %.c - ${CC} -c -I../../include $< -o $@ - -clean: - rm -rf *.o invalid_read_in_print_operand diff --git a/suite/regress/invalid_read_in_print_operand.c b/suite/regress/invalid_read_in_print_operand.c deleted file mode 100644 index 144ae9411f..0000000000 --- a/suite/regress/invalid_read_in_print_operand.c +++ /dev/null @@ -1,14 +0,0 @@ -#include - -#define BINARY "\x3b\x30\x62\x93\x5d\x61\x03\xe8" - -int main(int argc, char **argv, char **envp) { - csh handle; - if (cs_open(CS_ARCH_X86, CS_MODE_64, &handle)) { - printf("cs_open(…) failed\n"); - return 1; - } - cs_insn *insn; - cs_disasm(handle, (uint8_t *)BINARY, sizeof(BINARY) - 1, 0x1000, 0, &insn); - return 0; -} diff --git a/suite/regress/regress.py b/suite/regress/regress.py deleted file mode 100755 index 2e4f2536bc..0000000000 --- a/suite/regress/regress.py +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/python - -import unittest - -from os.path import dirname, basename, isfile -import glob - -# Find all unittest type in this directory and run it. - -class RegressTest(unittest.TestCase): - pass - -def main(): - unittest.main() - -if __name__ == '__main__': - directory = dirname(__file__) - if directory == '': - directory = '.' - modules = glob.glob(directory+"/*.py") - __all__ = [ basename(f)[:-3] for f in modules if isfile(f)] - suite = unittest.TestSuite() - - for module in __all__: - m = __import__(module) - for cl in dir(m): - try: - realcl = getattr(m,cl) - if issubclass(realcl, unittest.TestCase): - suite.addTest(realcl()) - except Exception as e: - pass - - unittest.TextTestRunner().run(suite) diff --git a/suite/regress/test_arm64_bra.py b/suite/regress/test_arm64_bra.py deleted file mode 100644 index e16764170b..0000000000 --- a/suite/regress/test_arm64_bra.py +++ /dev/null @@ -1,57 +0,0 @@ -import unittest -from capstone import * -from capstone.arm64 import * - -class ARM64BRAARegAccessTest(unittest.TestCase): - - # These instructions should all have all their register operands being READ. - # https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/BRAA--BRAAZ--BRAB--BRABZ--Branch-to-Register--with-pointer-authentication- - PATTERNS = [ - ("5F 08 1F D6", "braaz x2"), - ("11 0A 1F D7", "braa x16, x17"), - ("1F 0C 1F D6", "brabz x0"), - ("11 0E 1F D7", "brab x16, x17"), - ] - - def setUp(self): - self.insts = [] - self.cs = Cs(CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN) - self.cs.detail = True - - for pattern, asm in self.PATTERNS: - # Disassemble the instruction. Any error here means Capstone doesn't handle the instruction (maybe the wrong branch) - inst = next(self.cs.disasm(bytes.fromhex(pattern), 0)) - - expected_regs_read = list(map(lambda r: r.strip(', '), asm.split()[1:])) - expected_regs_written = [] # nothing written - expected_regs = [expected_regs_read, expected_regs_written] - - self.insts.append((inst, asm, expected_regs)) - - - def test_regs_access(self): - """Check that the `regs_access` API provides correct data""" - - for inst, asm, expected_regs in self.insts: - - # Check that the instruction writes the first register operand and reads the second - for i, decoded_regs in enumerate(map(lambda l: list(map(self.cs.reg_name, l)), inst.regs_access())): - self.assertEqual(decoded_regs, expected_regs[i], "%s has %r %s registers instead of %r" % (asm, decoded_regs, ["read", "written"][i], expected_regs[i])) - - - def test_operands(self): - """Check that the `operands` API provides correct data""" - for inst, asm, expected_regs in self.insts: - ops = inst.operands - - expected_regs_read, expected_regs_written = expected_regs - self.assertEqual(len(expected_regs_written), 0) - #print("Ensuring %s has the following read registers: %r" % (asm, expected_regs_read)) - self.assertEqual(len(ops), len(expected_regs_read)) - - for i, op in enumerate(ops): - self.assertEqual(op.type, CS_OP_REG, "%s has operand %d with invalid type" % (asm, i)) - self.assertEqual(op.access, CS_AC_READ, "%s has operand %d with invalid access" % (asm, i)) - -if __name__ == '__main__': - unittest.main() diff --git a/suite/regress/test_arm64_ldr_registers.py b/suite/regress/test_arm64_ldr_registers.py deleted file mode 100644 index fded0ae896..0000000000 --- a/suite/regress/test_arm64_ldr_registers.py +++ /dev/null @@ -1,63 +0,0 @@ -import unittest -from capstone import * -from capstone.arm64 import * - -_python3 = sys.version_info.major == 3 - - -class SubRegTest(unittest.TestCase): - - PATTERNS = [ - ("41 00 40 F9", "ldr x1, [x2]"), - ("41 00 40 39", "ldrb w1, [x2]"), - ("41 00 C0 39", "ldrsb w1, [x2]"), - ("41 00 40 79", "ldrh w1, [x2]"), - ("88 c2 bf f8", "ldapr x8, [x20]"), - ] - - def setUp(self): - self.insts = [] - self.cs = Cs(CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN) - self.cs.detail = True - - for pattern, asm in self.PATTERNS: - if _python3: - l = list(self.cs.disasm(bytes.fromhex(pattern), 0)) - else: - l = list(self.cs.disasm(bytearray.fromhex(pattern), 0)) - self.assertTrue(len(l) == 1) - - _, expected_reg_written, expected_reg_read = asm.split() - # strip comma and [] - expected_reg_written = expected_reg_written[:-1] - expected_reg_read = expected_reg_read[1:-1] - expected_regs = [expected_reg_read, expected_reg_written] - - self.insts.append((l[0], asm, expected_regs)) - - - def test_registers(self): - """Check that the `regs_access` API provides correct data""" - - for inst, asm, expected_regs in self.insts: - - # Check that the instruction writes the first register operand and reads the second - for i, decoded_regs in enumerate(map(lambda l: list(map(self.cs.reg_name, l)), inst.regs_access())): - self.assertEqual(len(decoded_regs), 1, "%s has %d %s registers instead of 1" % (asm, len(decoded_regs), ["read", "written"][i])) - decoded_reg = decoded_regs[0] - self.assertEqual(expected_regs[i], decoded_reg, "%s test"%i) - - def test_operands(self): - """Check that the `operands` API provides correct data""" - for inst, asm, expected_regs in self.insts: - ops = inst.operands - self.assertEqual(len(ops), 2) - - self.assertEqual(ops[0].type, CS_OP_REG, "%s has operand 0 with invalid type" % asm) - self.assertEqual(ops[0].access, CS_AC_WRITE, "%s has operand 0 with invalid access" % asm) - self.assertEqual(ops[1].type, CS_OP_MEM, "%s has operand 0 with invalid type" % asm) - self.assertEqual(self.cs.reg_name(ops[1].mem.base), expected_regs[0], "%s has operand 1 with invalid reg" % asm) - self.assertEqual(ops[1].access, CS_AC_READ, "%s has operand 1 with invalid access" % asm) - -if __name__ == '__main__': - unittest.main() diff --git a/suite/regress/test_arm64_mov.py b/suite/regress/test_arm64_mov.py deleted file mode 100755 index 4ef4a5f529..0000000000 --- a/suite/regress/test_arm64_mov.py +++ /dev/null @@ -1,76 +0,0 @@ -import unittest -from capstone import * -from capstone.arm64 import * - -# By Stevie Lavern , 2023. -class ARM64MovRegAccessTest(unittest.TestCase): - # These instructions should all have their 1st operand register being WRITTEN and not READ. - PATTERNS_IMM = [ - ("00 00 80 D2", "mov x0, #0"), - ("E2 66 82 52", "movz w2, #0x1337"), - ("A3 D5 9B 92", "movn x3, #0xdead"), - ("E4 DD 97 12", "movn w4, #0xbeef"), - ("03 40 A0 D2", "mov x3, #0x2000000") # aliased to MOVZXi. - ] - - PATTERNS_REG = [ - ("00 20 18 D5", "msr ttbr0_el1, x0"), - ("20 20 38 D5", "mrs x0, ttbr1_el1") - ] - - def setUp(self): - self.insts = [] - self.cs = Cs(CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN) - self.cs.detail = True - - for pattern, asm in self.PATTERNS_IMM: - l = list(self.cs.disasm(bytes.fromhex(pattern), 0)) - self.assertTrue(len(l) == 1) - - _, expected_reg_written, _ = asm.split() - # strip comma and []. - expected_reg_written = [expected_reg_written[:-1]] - expected_reg_read = [] # nothing should be read. - expected_regs = [expected_reg_read, expected_reg_written] - - self.insts.append((l[0], asm, expected_regs, False)) - - for pattern, asm in self.PATTERNS_REG: - l = list(self.cs.disasm(bytes.fromhex(pattern), 0)) - self.assertTrue(len(l) == 1) - - _, expected_reg_written, expected_reg_read = asm.split() - # strip comma and [], only keep general purpose registers. - expected_reg_written = expected_reg_written[:-1] - expected_reg_written = [expected_reg_written] if expected_reg_written[0].lower() == 'x' else [] - expected_reg_read = [expected_reg_read] if expected_reg_read[0].lower() == 'x' else [] - expected_regs = [expected_reg_read, expected_reg_written] - - self.insts.append((l[0], asm, expected_regs, True)) - - def test_regs_access(self): - """Check that the `regs_access` API provides correct data""" - - for inst, asm, expected_regs, pattern_reg in self.insts: - # Check that the instruction writes the first register operand and reads the second. - for i, decoded_regs in enumerate(map(lambda l: list(map(self.cs.reg_name, l)), inst.regs_access())): - self.assertEqual(decoded_regs, expected_regs[i], "%s has %r %s registers instead of %r" % (asm, decoded_regs, ["read", "written"][i], expected_regs[i])) - - def test_operands(self): - """Check that the `operands` API provides correct data""" - for inst, asm, expected_regs, pattern_reg in self.insts: - ops = inst.operands - self.assertEqual(len(ops), 2) - - reg_types = [CS_OP_REG, ARM64_OP_SYS] if pattern_reg else [CS_OP_REG] - - self.assertIn(ops[0].type, reg_types, "%s has operand 0 with invalid type" % asm) - self.assertEqual(ops[0].access, CS_AC_WRITE, "%s has operand 0 with invalid access" % asm) - if pattern_reg: - self.assertIn(ops[1].type, reg_types, "%s has operand 0 with invalid type" % asm) - else: - self.assertEqual(ops[1].type, CS_OP_IMM, "%s has operand 0 with invalid type" % asm) - -if __name__ == '__main__': - unittest.main() - diff --git a/suite/regress/test_arm64_pac.py b/suite/regress/test_arm64_pac.py deleted file mode 100644 index 33f169fd08..0000000000 --- a/suite/regress/test_arm64_pac.py +++ /dev/null @@ -1,97 +0,0 @@ -import unittest -from capstone import * -from capstone.arm64 import * -from collections import defaultdict - -class ARM64PACRegAccessTest(unittest.TestCase): - - PATTERNS = [ - ("41 00 C1 DA", "pacia x1, x2"), - ("3F 23 03 D5", "paciasp"), - ("E1 23 C1 DA", "paciza x1"), - ("41 04 C1 DA", "pacib x1, x2"), - ("7F 23 03 D5", "pacibsp"), - ("E1 27 C1 DA", "pacizb x1"), - ("41 08 C1 DA", "pacda x1, x2"), - ("E1 2B C1 DA", "pacdza x1"), - ("41 0C C1 DA", "pacdb x1, x2"), - ("E1 2F C1 DA", "pacdzb x1"), - ("41 18 C1 DA", "autda x1, x2"), - ("E1 3B C1 DA", "autdza x1"), - ("41 1C C1 DA", "autdb x1, x2"), - ("E1 3F C1 DA", "autdzb x1"), - ("41 10 C1 DA", "autia x1, x2"), - ("BF 23 03 D5", "autiasp"), - ("E1 33 C1 DA", "autiza x1"), - ("9F 23 03 D5", "autiaz"), - ("41 14 C1 DA", "autib x1, x2"), - ("FF 23 03 D5", "autibsp"), - ("E1 37 C1 DA", "autizb x1"), - ("DF 23 03 D5", "autibz"), - ("E1 47 C1 DA", "xpacd x1"), - ("E1 43 C1 DA", "xpaci x1"), - ("FF 20 03 D5", "xpaclri"), - ] - - def setUp(self): - self.insts = [] - self.cs = Cs(CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN) - self.cs.detail = True - - for pattern, asm in self.PATTERNS: - # Disassemble the instruction. Any error here means Capstone doesn't handle the instruction (maybe the wrong branch) - inst = next(self.cs.disasm(bytes.fromhex(pattern), 0)) - - # Build the lists of expected read and written registers - regs = list(map(lambda r: r.strip(', '), asm.split()[1:])) - expected_regs_read = [] - n = len(regs) - if(n == 0): - expected_regs_written = ["lr"] - expected_regs_read = ["lr"] - if(asm.endswith("sp")): - expected_regs_read += ["sp"] - elif(n == 1): - expected_regs_written = [regs[0]] - expected_regs_read = [regs[0]] - elif(n == 2): - expected_regs_written = [regs[0]] - expected_regs_read = regs - - expected_regs = [expected_regs_read, expected_regs_written] - #print((inst, asm, expected_regs)) - - self.insts.append((inst, asm, expected_regs)) - - - def test_regs_access(self): - """Check that the `regs_access` API provides correct data""" - - for inst, asm, expected_regs in self.insts: - for i, decoded_regs in enumerate(map(lambda l: list(map(self.cs.reg_name, l)), inst.regs_access())): - self.assertEqual(set(decoded_regs), set(expected_regs[i]), "%s has %r %s registers instead of %r" % (asm, decoded_regs, ["read", "written"][i], expected_regs[i])) - - - def test_operands(self): - """Check that the `operands` API provides correct data""" - for inst, asm, expected_regs in self.insts: - ops = inst.operands - asm_regs = list(map(lambda r: r.strip(', '), asm.split()[1:])) - self.assertEqual(len(ops), len(asm_regs)) - - expected_regs_accesses = defaultdict(int) - - expected_regs_read, expected_regs_written = expected_regs - for reg in expected_regs_written: - expected_regs_accesses[reg] |= CS_AC_WRITE - for reg in expected_regs_read: - expected_regs_accesses[reg] |= CS_AC_READ - - for i, op in enumerate(ops): - self.assertEqual(op.type, CS_OP_REG, "%s has operand %d with invalid type" % (asm, i)) - regname = self.cs.reg_name(op.reg) - self.assertEqual(op.access, expected_regs_accesses[regname], "%s has operand %d (%s) with invalid access (%d != %d)" % (asm, i, regname, op.access, expected_regs_accesses[regname])) - - -if __name__ == '__main__': - unittest.main() diff --git a/suite/test_all.sh b/suite/test_all.sh deleted file mode 100755 index 1c68bc862d..0000000000 --- a/suite/test_all.sh +++ /dev/null @@ -1,9 +0,0 @@ -#!/bin/sh - -# dump test output to /tmp/ for diffing -# this is useful to detect if a change modifies any disasm output - -# syntax: test_all.sh - -# ./test_archs.py > /tmp/$1_arch -./test_c.sh $1_c diff --git a/suite/test_c.sh b/suite/test_c.sh deleted file mode 100755 index 3ba937650f..0000000000 --- a/suite/test_c.sh +++ /dev/null @@ -1,28 +0,0 @@ -#!/bin/bash - -# Run all the Python tests, and send the output that to a file to be compared later -# This is useful when we want to verify if a commit (wrongly) changes the disassemble result. - -../tests/test_arm > /tmp/$1 -../tests/test_aarch64 > /tmp/$1 -../tests/test_basic > /tmp/$1 -../tests/test_bpf > /tmp/$1 -../tests/test_customized_mnem > /tmp/$1 -../tests/test_detail > /tmp/$1 -../tests/test_evm > /tmp/$1 -../tests/test_iter > /tmp/$1 -../tests/test_m680x > /tmp/$1 -../tests/test_m68k > /tmp/$1 -../tests/test_mips > /tmp/$1 -../tests/test_mos65xx > /tmp/$1 -../tests/test_ppc > /tmp/$1 -../tests/test_skipdata > /tmp/$1 -../tests/test_sparc > /tmp/$1 -../tests/test_systemz > /tmp/$1 -../tests/test_tms320c64x > /tmp/$1 -../tests/test_wasm > /tmp/$1 -../tests/test_winkernel > /tmp/$1 -../tests/test_x86 > /tmp/$1 -../tests/test_xcore > /tmp/$1 -../tests/test_alpha > /tmp/$1 -../tests/test_hppa > /tmp/$1 \ No newline at end of file diff --git a/suite/test_group_name.py b/suite/test_group_name.py deleted file mode 100755 index 7f6be5110e..0000000000 --- a/suite/test_group_name.py +++ /dev/null @@ -1,283 +0,0 @@ -#!/usr/bin/python - -from capstone import * -from capstone.arm import * -from capstone.arm64 import * -from capstone.mips import * -from capstone.ppc import * -from capstone.sparc import * -from capstone.systemz import * -from capstone.x86 import * -from capstone.xcore import * -from capstone.riscv import * -import sys - -class GroupTest: - def __init__(self, name, arch, mode, data): - self.name = name - self.arch = arch - self.mode = mode - self.data = data - - def run(self): - print('Testing %s' %self.name) - cap = Cs(self.arch, self.mode) - for group_id in xrange(0,255): - name = self.data.get(group_id) - res = cap.group_name(group_id) - if res != name: - print("ERROR: id = %u expected '%s', but got '%s'" %(group_id, name, res)) - print("") - -arm_dict = { - ARM_GRP_JUMP: "jump", - ARM_GRP_CALL: "call", - ARM_GRP_INT: "int", - ARM_GRP_PRIVILEGE: "privilege", - - ARM_GRP_CRYPTO: "crypto", - ARM_GRP_DATABARRIER: "databarrier", - ARM_GRP_DIVIDE: "divide", - ARM_GRP_FPARMV8: "fparmv8", - ARM_GRP_MULTPRO: "multpro", - ARM_GRP_NEON: "neon", - ARM_GRP_T2EXTRACTPACK: "T2EXTRACTPACK", - ARM_GRP_THUMB2DSP: "THUMB2DSP", - ARM_GRP_TRUSTZONE: "TRUSTZONE", - ARM_GRP_V4T: "v4t", - ARM_GRP_V5T: "v5t", - ARM_GRP_V5TE: "v5te", - ARM_GRP_V6: "v6", - ARM_GRP_V6T2: "v6t2", - ARM_GRP_V7: "v7", - ARM_GRP_V8: "v8", - ARM_GRP_VFP2: "vfp2", - ARM_GRP_VFP3: "vfp3", - ARM_GRP_VFP4: "vfp4", - ARM_GRP_ARM: "arm", - ARM_GRP_MCLASS: "mclass", - ARM_GRP_NOTMCLASS: "notmclass", - ARM_GRP_THUMB: "thumb", - ARM_GRP_THUMB1ONLY: "thumb1only", - ARM_GRP_THUMB2: "thumb2", - ARM_GRP_PREV8: "prev8", - ARM_GRP_FPVMLX: "fpvmlx", - ARM_GRP_MULOPS: "mulops", - ARM_GRP_CRC: "crc", - ARM_GRP_DPVFP: "dpvfp", - ARM_GRP_V6M: "v6m", - ARM_GRP_VIRTUALIZATION: "virtualization", -} - -arm64_dict = { - AARCH64_GRP_JUMP: "jump", - AARCH64_GRP_CALL: "call", - AARCH64_GRP_RET: "return", - AARCH64_GRP_INT: "int", - AARCH64_GRP_PRIVILEGE: "privilege", - - AARCH64_GRP_CRYPTO: "crypto", - AARCH64_GRP_FPARMV8: "fparmv8", - AARCH64_GRP_NEON: "neon", - AARCH64_GRP_CRC: "crc" -} - -mips_dict = { - MIPS_GRP_JUMP: "jump", - MIPS_GRP_CALL: "call", - MIPS_GRP_RET: "ret", - MIPS_GRP_INT: "int", - MIPS_GRP_IRET: "iret", - MIPS_GRP_PRIVILEGE: "privilege", - MIPS_GRP_BITCOUNT: "bitcount", - MIPS_GRP_DSP: "dsp", - MIPS_GRP_DSPR2: "dspr2", - MIPS_GRP_FPIDX: "fpidx", - MIPS_GRP_MSA: "msa", - MIPS_GRP_MIPS32R2: "mips32r2", - MIPS_GRP_MIPS64: "mips64", - MIPS_GRP_MIPS64R2: "mips64r2", - MIPS_GRP_SEINREG: "seinreg", - MIPS_GRP_STDENC: "stdenc", - MIPS_GRP_SWAP: "swap", - MIPS_GRP_MICROMIPS: "micromips", - MIPS_GRP_MIPS16MODE: "mips16mode", - MIPS_GRP_FP64BIT: "fp64bit", - MIPS_GRP_NONANSFPMATH: "nonansfpmath", - MIPS_GRP_NOTFP64BIT: "notfp64bit", - MIPS_GRP_NOTINMICROMIPS: "notinmicromips", - MIPS_GRP_NOTNACL: "notnacl", - - MIPS_GRP_NOTMIPS32R6: "notmips32r6", - MIPS_GRP_NOTMIPS64R6: "notmips64r6", - MIPS_GRP_CNMIPS: "cnmips", - - MIPS_GRP_MIPS32: "mips32", - MIPS_GRP_MIPS32R6: "mips32r6", - MIPS_GRP_MIPS64R6: "mips64r6", - - MIPS_GRP_MIPS2: "mips2", - MIPS_GRP_MIPS3: "mips3", - MIPS_GRP_MIPS3_32: "mips3_32", - MIPS_GRP_MIPS3_32R2: "mips3_32r2", - - MIPS_GRP_MIPS4_32: "mips4_32", - MIPS_GRP_MIPS4_32R2: "mips4_32r2", - MIPS_GRP_MIPS5_32R2: "mips5_32r2", - - MIPS_GRP_GP32BIT: "gp32bit", - MIPS_GRP_GP64BIT: "gp64bit", -} - -ppc_dict = { - PPC_GRP_JUMP: "jump", - - PPC_GRP_ALTIVEC: "altivec", - PPC_GRP_MODE32: "mode32", - PPC_GRP_MODE64: "mode64", - PPC_GRP_BOOKE: "booke", - PPC_GRP_NOTBOOKE: "notbooke", - PPC_GRP_SPE: "spe", - PPC_GRP_VSX: "vsx", - PPC_GRP_E500: "e500", - PPC_GRP_PPC4XX: "ppc4xx", - PPC_GRP_PPC6XX: "ppc6xx", - PPC_GRP_ICBT: "icbt", - PPC_GRP_P8ALTIVEC: "p8altivec", - PPC_GRP_P8VECTOR: "p8vector", - PPC_GRP_QPX: "qpx", - PPC_GRP_PS: "ps", -} - -sparc_dict = { - SPARC_GRP_JUMP: "jump", - - SPARC_GRP_HARDQUAD: "hardquad", - SPARC_GRP_V9: "v9", - SPARC_GRP_VIS: "vis", - SPARC_GRP_VIS2: "vis2", - SPARC_GRP_VIS3: "vis3", - SPARC_GRP_32BIT: "32bit", - SPARC_GRP_64BIT: "64bit", -} - -sysz_dict = { - SYSZ_GRP_JUMP: "jump", - - SYSZ_GRP_DISTINCTOPS: "distinctops", - SYSZ_GRP_FPEXTENSION: "fpextension", - SYSZ_GRP_HIGHWORD: "highword", - SYSZ_GRP_INTERLOCKEDACCESS1: "interlockedaccess1", - SYSZ_GRP_LOADSTOREONCOND: "loadstoreoncond", -} - -x86_dict = { - X86_GRP_JUMP: "jump", - X86_GRP_CALL: "call", - X86_GRP_RET: "ret", - X86_GRP_INT: "int", - X86_GRP_IRET: "iret", - X86_GRP_PRIVILEGE: "privilege", - - X86_GRP_VM: "vm", - X86_GRP_3DNOW: "3dnow", - X86_GRP_AES: "aes", - X86_GRP_ADX: "adx", - X86_GRP_AVX: "avx", - X86_GRP_AVX2: "avx2", - X86_GRP_AVX512: "avx512", - X86_GRP_BMI: "bmi", - X86_GRP_BMI2: "bmi2", - X86_GRP_CMOV: "cmov", - X86_GRP_F16C: "fc16", - X86_GRP_FMA: "fma", - X86_GRP_FMA4: "fma4", - X86_GRP_FSGSBASE: "fsgsbase", - X86_GRP_HLE: "hle", - X86_GRP_MMX: "mmx", - X86_GRP_MODE32: "mode32", - X86_GRP_MODE64: "mode64", - X86_GRP_RTM: "rtm", - X86_GRP_SHA: "sha", - X86_GRP_SSE1: "sse1", - X86_GRP_SSE2: "sse2", - X86_GRP_SSE3: "sse3", - X86_GRP_SSE41: "sse41", - X86_GRP_SSE42: "sse42", - X86_GRP_SSE4A: "sse4a", - X86_GRP_SSSE3: "ssse3", - X86_GRP_PCLMUL: "pclmul", - X86_GRP_XOP: "xop", - X86_GRP_CDI: "cdi", - X86_GRP_ERI: "eri", - X86_GRP_TBM: "tbm", - X86_GRP_16BITMODE: "16bitmode", - X86_GRP_NOT64BITMODE: "not64bitmode", - X86_GRP_SGX: "sgx", - X86_GRP_DQI: "dqi", - X86_GRP_BWI: "bwi", - X86_GRP_PFI: "pfi", - X86_GRP_VLX: "vlx", - X86_GRP_SMAP: "smap", - X86_GRP_NOVLX: "novlx", -} - -xcore_dict = { - XCORE_GRP_JUMP: "jump", -} - -riscv32_dict = { - RISCV_GRP_JUMP : "jump", - RISCV_GRP_CALL : "call", - RISCV_GRP_RET : "ret", - RISCV_GRP_INT : "int", - RISCV_GRP_IRET : "iret", - RISCV_GRP_PRIVILEGE : "privileged", - RISCV_GRP_BRANCH_RELATIVE: "branch_relative", - RISCV_GRP_ISRV32 : "isrv32", - RISCV_GRP_HASSTDEXTA : "hasstdexta", - RISCV_GRP_HASSTDEXTC : "hasstdextc", - RISCV_GRP_HASSTDEXTD : "hasstdextd", - RISCV_GRP_HASSTDEXTF : "hasstdextf", - RISCV_GRP_HASSTDEXTM : "hasstdextm", -} - -riscv64_dict = { - RISCV_GRP_JUMP : "jump", - RISCV_GRP_CALL : "call", - RISCV_GRP_RET : "ret", - RISCV_GRP_INT : "int", - RISCV_GRP_IRET : "iret", - RISCV_GRP_PRIVILEGE : "privileged", - RISCV_GRP_BRANCH_RELATIVE: "branch_relative", - RISCV_GRP_ISRV64 : "isrv64", - RISCV_GRP_HASSTDEXTA : "hasstdexta", - RISCV_GRP_HASSTDEXTC : "hasstdextc", - RISCV_GRP_HASSTDEXTD : "hasstdextd", - RISCV_GRP_HASSTDEXTF : "hasstdextf", - RISCV_GRP_HASSTDEXTM : "hasstdextm", -} - -tests = [ - GroupTest('arm', CS_ARCH_ARM, CS_MODE_THUMB, arm_dict), - GroupTest('arm64', CS_ARCH_AARCH64, CS_MODE_ARM, arm64_dict), - GroupTest('mips', CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN, mips_dict), - GroupTest('ppc', CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, ppc_dict), - GroupTest('sparc', CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, sparc_dict), - GroupTest('sysz', CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN, sysz_dict), - GroupTest('x86', CS_ARCH_X86, CS_MODE_32, x86_dict), - GroupTest('xcore', CS_ARCH_XCORE, CS_MODE_BIG_ENDIAN, xcore_dict), - GroupTest('m68k', CS_ARCH_M68K, CS_MODE_BIG_ENDIAN, xcore_dict), - GroupTest('riscv32', CS_ARCH_RISCV, CS_MODE_RISCV32, riscv32_dict), - GroupTest('riscv64', CS_ARCH_RISCV, CS_MODE_RISCV64, riscv64_dict), -] - -if __name__ == '__main__': - args = sys.argv[1:] - all = len(args) == 0 or 'all' in args - for t in tests: - if all or t.name in args: - t.run() - else: - print('Skipping %s' %t.name) - diff --git a/suite/test_mc.py b/suite/test_mc.py deleted file mode 100755 index c895814b1c..0000000000 --- a/suite/test_mc.py +++ /dev/null @@ -1,267 +0,0 @@ -#!/usr/bin/python -# Test tool to compare Capstone output with llvm-mc. By Nguyen Anh Quynh, 2014 -import array, os.path, sys -from subprocess import Popen, PIPE, STDOUT -from capstone import * - - -# convert all hex numbers to decimal numbers in a text -def normalize_hex(a): - while(True): - i = a.find('0x') - if i == -1: # no more hex number - break - hexnum = '0x' - for c in a[i + 2:]: - if c in '0123456789abcdefABCDEF': - hexnum += c - else: - break - num = int(hexnum, 16) - a = a.replace(hexnum, str(num)) - return a - - -def run_mc(arch, hexcode, option, syntax=None): - def normalize(text): - # remove tabs - text = text.lower() - items = text.split() - text = ' '.join(items) - if arch == CS_ARCH_X86: - # remove comment after # - i = text.find('# ') - if i != -1: - return text[:i].strip() - if arch == CS_ARCH_AARCH64: - # remove comment after # - i = text.find('// ') - if i != -1: - return text[:i].strip() - # remove some redundant spaces - text = text.replace('{ ', '{') - text = text.replace(' }', '}') - return text.strip() - - #print("Trying to decode: %s" %hexcode) - if syntax: - if arch == CS_ARCH_MIPS: - p = Popen(['llvm-mc', '-disassemble', '-print-imm-hex', '-mattr=+msa', syntax] + option, stdout=PIPE, stdin=PIPE, stderr=STDOUT) - else: - p = Popen(['llvm-mc', '-disassemble', '-print-imm-hex', syntax] + option, stdout=PIPE, stdin=PIPE, stderr=STDOUT) - else: - if arch == CS_ARCH_MIPS: - p = Popen(['llvm-mc', '-disassemble', '-print-imm-hex', '-mattr=+msa'] + option, stdout=PIPE, stdin=PIPE, stderr=STDOUT) - else: - p = Popen(['llvm-mc', '-disassemble', '-print-imm-hex'] + option, stdout=PIPE, stdin=PIPE, stderr=STDOUT) - output = p.communicate(input=hexcode)[0] - lines = output.split('\n') - #print lines - if 'invalid' in lines[0]: - #print 'invalid ----' - return 'FAILED to disassemble (MC)' - else: - #print 'OK:', lines[1] - return normalize(lines[1].strip()) - -def test_file(fname): - print("Test %s" %fname); - f = open(fname) - lines = f.readlines() - f.close() - - if not lines[0].startswith('# '): - print("ERROR: decoding information is missing") - return - - # skip '# ' at the front, then split line to get out hexcode - # Note: option can be '', or 'None' - #print lines[0] - #print lines[0][2:].split(', ') - (arch, mode, option) = lines[0][2:].split(', ') - mode = mode.replace(' ', '') - option = option.strip() - - archs = { - "CS_ARCH_ARM": CS_ARCH_ARM, - "CS_ARCH_AARCH64": CS_ARCH_AARCH64, - "CS_ARCH_MIPS": CS_ARCH_MIPS, - "CS_ARCH_PPC": CS_ARCH_PPC, - "CS_ARCH_SPARC": CS_ARCH_SPARC, - "CS_ARCH_SYSZ": CS_ARCH_SYSZ, - "CS_ARCH_X86": CS_ARCH_X86, - "CS_ARCH_XCORE": CS_ARCH_XCORE, - "CS_ARCH_RISCV": CS_ARCH_RISCV - # "CS_ARCH_M68K": CS_ARCH_M68K, - } - - modes = { - "CS_MODE_16": CS_MODE_16, - "CS_MODE_32": CS_MODE_32, - "CS_MODE_64": CS_MODE_64, - "CS_MODE_MIPS32": CS_MODE_MIPS32, - "CS_MODE_MIPS64": CS_MODE_MIPS64, - "0": CS_MODE_ARM, - "CS_MODE_ARM": CS_MODE_ARM, - "CS_MODE_THUMB": CS_MODE_THUMB, - "CS_MODE_ARM+CS_MODE_V8": CS_MODE_ARM+CS_MODE_V8, - "CS_MODE_THUMB+CS_MODE_V8": CS_MODE_THUMB+CS_MODE_V8, - "CS_MODE_THUMB+CS_MODE_MCLASS": CS_MODE_THUMB+CS_MODE_MCLASS, - "CS_MODE_LITTLE_ENDIAN": CS_MODE_LITTLE_ENDIAN, - "CS_MODE_BIG_ENDIAN": CS_MODE_BIG_ENDIAN, - "CS_MODE_64+CS_MODE_LITTLE_ENDIAN": CS_MODE_64+CS_MODE_LITTLE_ENDIAN, - "CS_MODE_64+CS_MODE_BIG_ENDIAN": CS_MODE_64+CS_MODE_BIG_ENDIAN, - "CS_MODE_MIPS32+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO, - "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, - "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, - "CS_MODE_BIG_ENDIAN+CS_MODE_V9": CS_MODE_BIG_ENDIAN + CS_MODE_V9, - "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, - "CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN, - "CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN, - "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, - "CS_MODE_RISCV32": CS_MODE_RISCV32, - "CS_MODE_RISCV64": CS_MODE_RISCV64, - } - - options = { - "CS_OPT_SYNTAX_ATT": CS_OPT_SYNTAX_ATT, - "CS_OPT_SYNTAX_NOREGNAME": CS_OPT_SYNTAX_NOREGNAME, - } - - mc_modes = { - ("CS_ARCH_X86", "CS_MODE_32"): ['-triple=i386'], - ("CS_ARCH_X86", "CS_MODE_64"): ['-triple=x86_64'], - ("CS_ARCH_ARM", "CS_MODE_ARM"): ['-triple=armv7'], - ("CS_ARCH_ARM", "CS_MODE_THUMB"): ['-triple=thumbv7'], - ("CS_ARCH_ARM", "CS_MODE_ARM+CS_MODE_V8"): ['-triple=armv8'], - ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_V8"): ['-triple=thumbv8'], - ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_MCLASS"): ['-triple=thumbv7m'], - ("CS_ARCH_AARCH64", "0"): ['-triple=aarch64'], - ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN"): ['-triple=mips'], - ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO"): ['-triple=mipsel', '-mattr=+micromips'], - ("CS_ARCH_MIPS", "CS_MODE_MIPS64"): ['-triple=mips64el'], - ("CS_ARCH_MIPS", "CS_MODE_MIPS32"): ['-triple=mipsel'], - ("CS_ARCH_MIPS", "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN"): ['-triple=mips64'], - ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): ['-triple=mips', '-mattr=+micromips'], - ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO"): ['-triple=mips', '-mattr=+micromips'], - ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN"): ['-triple=powerpc64'], - ('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN'): ['-triple=sparc'], - ('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN+CS_MODE_V9'): ['-triple=sparcv9'], - ('CS_ARCH_SYSZ', '0'): ['-triple=s390x', '-mcpu=z196'], - ('CS_ARCH_RISCV', 'CS_MODE_RISCV32'): ['-triple=riscv32'], - ('CS_ARCH_RISCV', 'CS_MODE_RISCV64'): ['-triple=riscv64'], - } - - #if not option in ('', 'None'): - # print archs[arch], modes[mode], options[option] - - #print(arch, mode, option) - md = Cs(archs[arch], modes[mode]) - - mc_option = None - if arch == 'CS_ARCH_X86': - # tell llvm-mc to use Intel syntax - mc_option = '-output-asm-variant=1' - - if arch == 'CS_ARCH_ARM' or arch == 'CS_ARCH_PPC' : - md.syntax = CS_OPT_SYNTAX_NOREGNAME - - if fname.endswith('3DNow.s.cs'): - md.syntax = CS_OPT_SYNTAX_ATT - - for line in lines[1:]: - # ignore all the input lines having # in front. - if line.startswith('#'): - continue - #print("Check %s" %line) - code = line.split(' = ')[0] - asm = ''.join(line.split(' = ')[1:]) - hex_code = code.replace('0x', '') - hex_code = hex_code.replace(',', '') - hex_data = hex_code.decode('hex') - #hex_bytes = array.array('B', hex_data) - - x = list(md.disasm(hex_data, 0)) - if len(x) > 0: - if x[0].op_str != '': - cs_output = "%s %s" %(x[0].mnemonic, x[0].op_str) - else: - cs_output = x[0].mnemonic - else: - cs_output = 'FAILED to disassemble' - - cs_output2 = normalize_hex(cs_output) - cs_output2 = cs_output2.replace(' ', '') - - if arch == 'CS_ARCH_MIPS': - # normalize register alias names - cs_output2 = cs_output2.replace('$at', '$1') - cs_output2 = cs_output2.replace('$v0', '$2') - cs_output2 = cs_output2.replace('$v1', '$3') - - cs_output2 = cs_output2.replace('$a0', '$4') - cs_output2 = cs_output2.replace('$a1', '$5') - cs_output2 = cs_output2.replace('$a2', '$6') - cs_output2 = cs_output2.replace('$a3', '$7') - - cs_output2 = cs_output2.replace('$t0', '$8') - cs_output2 = cs_output2.replace('$t1', '$9') - cs_output2 = cs_output2.replace('$t2', '$10') - cs_output2 = cs_output2.replace('$t3', '$11') - cs_output2 = cs_output2.replace('$t4', '$12') - cs_output2 = cs_output2.replace('$t5', '$13') - cs_output2 = cs_output2.replace('$t6', '$14') - cs_output2 = cs_output2.replace('$t7', '$15') - cs_output2 = cs_output2.replace('$t8', '$24') - cs_output2 = cs_output2.replace('$t9', '$25') - - cs_output2 = cs_output2.replace('$s0', '$16') - cs_output2 = cs_output2.replace('$s1', '$17') - cs_output2 = cs_output2.replace('$s2', '$18') - cs_output2 = cs_output2.replace('$s3', '$19') - cs_output2 = cs_output2.replace('$s4', '$20') - cs_output2 = cs_output2.replace('$s5', '$21') - cs_output2 = cs_output2.replace('$s6', '$22') - cs_output2 = cs_output2.replace('$s7', '$23') - - cs_output2 = cs_output2.replace('$k0', '$26') - cs_output2 = cs_output2.replace('$k1', '$27') - - #print("Running MC ...") - if fname.endswith('thumb-fp-armv8.s.cs'): - mc_output = run_mc(archs[arch], code, ['-triple=thumbv8'], mc_option) - elif fname.endswith('mips64-alu-instructions.s.cs'): - mc_output = run_mc(archs[arch], code, ['-triple=mips64el', '-mcpu=mips64r2'], mc_option) - else: - mc_output = run_mc(archs[arch], code, mc_modes[(arch, mode)], mc_option) - mc_output2 = normalize_hex(mc_output) - - if arch == 'CS_ARCH_MIPS': - mc_output2 = mc_output2.replace(' 0(', '(') - - if arch == 'CS_ARCH_PPC': - mc_output2 = mc_output2.replace('.+', '') - mc_output2 = mc_output2.replace('.', '') - mc_output2 = mc_output2.replace(' 0(', '(') - - mc_output2 = mc_output2.replace(' ', '') - mc_output2 = mc_output2.replace('opaque', '') - - - if (cs_output2 != mc_output2): - asm = asm.replace(' ', '').strip().lower() - if asm != cs_output2: - print("Mismatch: %s" %line.strip()) - print("\tMC = %s" %mc_output) - print("\tCS = %s" %cs_output) - - -if __name__ == '__main__': - if len(sys.argv) == 1: - fnames = sys.stdin.readlines() - for fname in fnames: - test_file(fname.strip()) - else: - #print("Usage: ./test_mc.py ") - test_file(sys.argv[1]) - diff --git a/suite/test_mc.sh b/suite/test_mc.sh deleted file mode 100755 index b4552aedad..0000000000 --- a/suite/test_mc.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/sh - -# This script test all architectures by default. -# At the output are all the mismatches between Capstone (CS) & LLVM (MC). -# While most differences coming from the fact that Capstone uses more friendly -# number format, some mismatches might be because Capstone is based on older -# version of LLVM (which should be fixed in the next release) - -find MC/ -name *.cs | ./test_mc.py - -# To test just one architecture, specify the corresponding dir: -# $ find MC/X86 -name *.cs | ./test_mc.py - -# To test just one input file, run test_mc.py with that file: -# $ ./test_mc.py MC/X86/x86-32-fma3.s.cs diff --git a/suite/test_python.sh b/suite/test_python.sh deleted file mode 100755 index 5445eb2277..0000000000 --- a/suite/test_python.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/bash - -# Run all the Python tests, and send the output that to a file to be compared later -# This is useful when we want to verify if a commit (wrongly) changes the disassemble result. - -../bindings/python/test.py > /tmp/$1 -../bindings/python/test_detail.py >> /tmp/$1 -../bindings/python/test_arm.py >> /tmp/$1 -../bindings/python/test_aarch64.py >> /tmp/$1 -../bindings/python/test_mips.py >> /tmp/$1 -../bindings/python/test_ppc.py >> /tmp/$1 -../bindings/python/test_sparc.py >> /tmp/$1 -../bindings/python/test_x86.py >> /tmp/$1 -../bindings/python/test_alpha.py >> /tmp/$1 -../bindings/python/test_hppa.py >> /tmp/$1 \ No newline at end of file diff --git a/tests/MC/AArch64/CSSC/abs_32.s.yaml b/tests/MC/AArch64/CSSC/abs_32.s.yaml new file mode 100644 index 0000000000..789beaeda9 --- /dev/null +++ b/tests/MC/AArch64/CSSC/abs_32.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "abs w0, w0" + + - + input: + bytes: [ 0x55, 0x21, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "abs w21, w10" + + - + input: + bytes: [ 0xb7, 0x21, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "abs w23, w13" + + - + input: + bytes: [ 0xff, 0x23, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "abs wzr, wzr" diff --git a/tests/MC/AArch64/CSSC/abs_64.s.yaml b/tests/MC/AArch64/CSSC/abs_64.s.yaml new file mode 100644 index 0000000000..1a24d25b7d --- /dev/null +++ b/tests/MC/AArch64/CSSC/abs_64.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "abs x0, x0" + + - + input: + bytes: [ 0x55, 0x21, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "abs x21, x10" + + - + input: + bytes: [ 0xb7, 0x21, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "abs x23, x13" + + - + input: + bytes: [ 0xff, 0x23, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "abs xzr, xzr" diff --git a/tests/MC/AArch64/CSSC/cnt_32.s.yaml b/tests/MC/AArch64/CSSC/cnt_32.s.yaml new file mode 100644 index 0000000000..138541f345 --- /dev/null +++ b/tests/MC/AArch64/CSSC/cnt_32.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x1c, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "cnt w0, w0" + + - + input: + bytes: [ 0x55, 0x1d, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "cnt w21, w10" + + - + input: + bytes: [ 0xb7, 0x1d, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "cnt w23, w13" + + - + input: + bytes: [ 0xff, 0x1f, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "cnt wzr, wzr" diff --git a/tests/MC/AArch64/CSSC/cnt_64.s.yaml b/tests/MC/AArch64/CSSC/cnt_64.s.yaml new file mode 100644 index 0000000000..b02122c84b --- /dev/null +++ b/tests/MC/AArch64/CSSC/cnt_64.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x1c, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "cnt x0, x0" + + - + input: + bytes: [ 0x55, 0x1d, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "cnt x21, x10" + + - + input: + bytes: [ 0xb7, 0x1d, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "cnt x23, x13" + + - + input: + bytes: [ 0xff, 0x1f, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "cnt xzr, xzr" diff --git a/tests/MC/AArch64/CSSC/ctz_32.s.yaml b/tests/MC/AArch64/CSSC/ctz_32.s.yaml new file mode 100644 index 0000000000..5c5fff3671 --- /dev/null +++ b/tests/MC/AArch64/CSSC/ctz_32.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x18, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "ctz w0, w0" + + - + input: + bytes: [ 0x55, 0x19, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "ctz w21, w10" + + - + input: + bytes: [ 0xb7, 0x19, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "ctz w23, w13" + + - + input: + bytes: [ 0xff, 0x1b, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "ctz wzr, wzr" diff --git a/tests/MC/AArch64/CSSC/ctz_64.s.yaml b/tests/MC/AArch64/CSSC/ctz_64.s.yaml new file mode 100644 index 0000000000..14f2eff38d --- /dev/null +++ b/tests/MC/AArch64/CSSC/ctz_64.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x18, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "ctz x0, x0" + + - + input: + bytes: [ 0x55, 0x19, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "ctz x21, x10" + + - + input: + bytes: [ 0xb7, 0x19, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "ctz x23, x13" + + - + input: + bytes: [ 0xff, 0x1b, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "ctz xzr, xzr" diff --git a/tests/MC/AArch64/CSSC/smax_32_imm.s.yaml b/tests/MC/AArch64/CSSC/smax_32_imm.s.yaml new file mode 100644 index 0000000000..4d774a9465 --- /dev/null +++ b/tests/MC/AArch64/CSSC/smax_32_imm.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smax w0, w0, #0" + + - + input: + bytes: [ 0x55, 0x55, 0xc1, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smax w21, w10, #85" + + - + input: + bytes: [ 0xb7, 0xed, 0xc0, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smax w23, w13, #59" + + - + input: + bytes: [ 0xff, 0xff, 0xc3, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smax wzr, wzr, #-1" diff --git a/tests/MC/AArch64/CSSC/smax_32_reg.s.yaml b/tests/MC/AArch64/CSSC/smax_32_reg.s.yaml new file mode 100644 index 0000000000..061ab87255 --- /dev/null +++ b/tests/MC/AArch64/CSSC/smax_32_reg.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0xc0, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smax w0, w0, w0" + + - + input: + bytes: [ 0x55, 0x61, 0xd5, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smax w21, w10, w21" + + - + input: + bytes: [ 0xb7, 0x61, 0xc8, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smax w23, w13, w8" + + - + input: + bytes: [ 0xff, 0x63, 0xdf, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smax wzr, wzr, wzr" diff --git a/tests/MC/AArch64/CSSC/smax_64_imm.s.yaml b/tests/MC/AArch64/CSSC/smax_64_imm.s.yaml new file mode 100644 index 0000000000..09a6bd83f8 --- /dev/null +++ b/tests/MC/AArch64/CSSC/smax_64_imm.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smax x0, x0, #0" + + - + input: + bytes: [ 0x55, 0x55, 0xc1, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smax x21, x10, #85" + + - + input: + bytes: [ 0xb7, 0xed, 0xc0, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smax x23, x13, #59" + + - + input: + bytes: [ 0xff, 0xff, 0xc3, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smax xzr, xzr, #-1" diff --git a/tests/MC/AArch64/CSSC/smax_64_reg.s.yaml b/tests/MC/AArch64/CSSC/smax_64_reg.s.yaml new file mode 100644 index 0000000000..eeed9baa8f --- /dev/null +++ b/tests/MC/AArch64/CSSC/smax_64_reg.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0xc0, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smax x0, x0, x0" + + - + input: + bytes: [ 0x55, 0x61, 0xd5, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smax x21, x10, x21" + + - + input: + bytes: [ 0xb7, 0x61, 0xc8, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smax x23, x13, x8" + + - + input: + bytes: [ 0xff, 0x63, 0xdf, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smax xzr, xzr, xzr" diff --git a/tests/MC/AArch64/CSSC/smin_32_imm.s.yaml b/tests/MC/AArch64/CSSC/smin_32_imm.s.yaml new file mode 100644 index 0000000000..e9f490ccd6 --- /dev/null +++ b/tests/MC/AArch64/CSSC/smin_32_imm.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xc8, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smin w0, w0, #0" + + - + input: + bytes: [ 0x55, 0x55, 0xc9, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smin w21, w10, #85" + + - + input: + bytes: [ 0xb7, 0xed, 0xc8, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smin w23, w13, #59" + + - + input: + bytes: [ 0xff, 0xff, 0xcb, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smin wzr, wzr, #-1" diff --git a/tests/MC/AArch64/CSSC/smin_32_reg.s.yaml b/tests/MC/AArch64/CSSC/smin_32_reg.s.yaml new file mode 100644 index 0000000000..0188ef1a85 --- /dev/null +++ b/tests/MC/AArch64/CSSC/smin_32_reg.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x68, 0xc0, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smin w0, w0, w0" + + - + input: + bytes: [ 0x55, 0x69, 0xd5, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smin w21, w10, w21" + + - + input: + bytes: [ 0xb7, 0x69, 0xc8, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smin w23, w13, w8" + + - + input: + bytes: [ 0xff, 0x6b, 0xdf, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smin wzr, wzr, wzr" diff --git a/tests/MC/AArch64/CSSC/smin_64_imm.s.yaml b/tests/MC/AArch64/CSSC/smin_64_imm.s.yaml new file mode 100644 index 0000000000..a714773102 --- /dev/null +++ b/tests/MC/AArch64/CSSC/smin_64_imm.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xc8, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smin x0, x0, #0" + + - + input: + bytes: [ 0x55, 0x55, 0xc9, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smin x21, x10, #85" + + - + input: + bytes: [ 0xb7, 0xed, 0xc8, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smin x23, x13, #59" + + - + input: + bytes: [ 0xff, 0xff, 0xcb, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smin xzr, xzr, #-1" diff --git a/tests/MC/AArch64/CSSC/smin_64_reg.s.yaml b/tests/MC/AArch64/CSSC/smin_64_reg.s.yaml new file mode 100644 index 0000000000..614883b4d5 --- /dev/null +++ b/tests/MC/AArch64/CSSC/smin_64_reg.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x68, 0xc0, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smin x0, x0, x0" + + - + input: + bytes: [ 0x55, 0x69, 0xd5, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smin x21, x10, x21" + + - + input: + bytes: [ 0xb7, 0x69, 0xc8, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smin x23, x13, x8" + + - + input: + bytes: [ 0xff, 0x6b, 0xdf, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "smin xzr, xzr, xzr" diff --git a/tests/MC/AArch64/CSSC/umax_32_imm.s.yaml b/tests/MC/AArch64/CSSC/umax_32_imm.s.yaml new file mode 100644 index 0000000000..6d64938c4b --- /dev/null +++ b/tests/MC/AArch64/CSSC/umax_32_imm.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xc4, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umax w0, w0, #0" + + - + input: + bytes: [ 0x55, 0x55, 0xc5, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umax w21, w10, #85" + + - + input: + bytes: [ 0xb7, 0xed, 0xc4, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umax w23, w13, #59" + + - + input: + bytes: [ 0xff, 0xff, 0xc7, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umax wzr, wzr, #255" diff --git a/tests/MC/AArch64/CSSC/umax_32_reg.s.yaml b/tests/MC/AArch64/CSSC/umax_32_reg.s.yaml new file mode 100644 index 0000000000..7e76f6ada9 --- /dev/null +++ b/tests/MC/AArch64/CSSC/umax_32_reg.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x64, 0xc0, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umax w0, w0, w0" + + - + input: + bytes: [ 0x55, 0x65, 0xd5, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umax w21, w10, w21" + + - + input: + bytes: [ 0xb7, 0x65, 0xc8, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umax w23, w13, w8" + + - + input: + bytes: [ 0xff, 0x67, 0xdf, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umax wzr, wzr, wzr" diff --git a/tests/MC/AArch64/CSSC/umax_64_imm.s.yaml b/tests/MC/AArch64/CSSC/umax_64_imm.s.yaml new file mode 100644 index 0000000000..a7d12d27c8 --- /dev/null +++ b/tests/MC/AArch64/CSSC/umax_64_imm.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xc4, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umax x0, x0, #0" + + - + input: + bytes: [ 0x55, 0x55, 0xc5, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umax x21, x10, #85" + + - + input: + bytes: [ 0xb7, 0xed, 0xc4, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umax x23, x13, #59" + + - + input: + bytes: [ 0xff, 0xff, 0xc7, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umax xzr, xzr, #255" diff --git a/tests/MC/AArch64/CSSC/umax_64_reg.s.yaml b/tests/MC/AArch64/CSSC/umax_64_reg.s.yaml new file mode 100644 index 0000000000..57c722eb21 --- /dev/null +++ b/tests/MC/AArch64/CSSC/umax_64_reg.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x64, 0xc0, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umax x0, x0, x0" + + - + input: + bytes: [ 0x55, 0x65, 0xd5, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umax x21, x10, x21" + + - + input: + bytes: [ 0xb7, 0x65, 0xc8, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umax x23, x13, x8" + + - + input: + bytes: [ 0xff, 0x67, 0xdf, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umax xzr, xzr, xzr" diff --git a/tests/MC/AArch64/CSSC/umin_32_imm.s.yaml b/tests/MC/AArch64/CSSC/umin_32_imm.s.yaml new file mode 100644 index 0000000000..0173a51017 --- /dev/null +++ b/tests/MC/AArch64/CSSC/umin_32_imm.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xcc, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umin w0, w0, #0" + + - + input: + bytes: [ 0x55, 0x55, 0xcd, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umin w21, w10, #85" + + - + input: + bytes: [ 0xb7, 0xed, 0xcc, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umin w23, w13, #59" + + - + input: + bytes: [ 0xff, 0xff, 0xcf, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umin wzr, wzr, #255" diff --git a/tests/MC/AArch64/CSSC/umin_32_reg.s.yaml b/tests/MC/AArch64/CSSC/umin_32_reg.s.yaml new file mode 100644 index 0000000000..9e321eefcd --- /dev/null +++ b/tests/MC/AArch64/CSSC/umin_32_reg.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x6c, 0xc0, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umin w0, w0, w0" + + - + input: + bytes: [ 0x55, 0x6d, 0xd5, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umin w21, w10, w21" + + - + input: + bytes: [ 0xb7, 0x6d, 0xc8, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umin w23, w13, w8" + + - + input: + bytes: [ 0xff, 0x6f, 0xdf, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umin wzr, wzr, wzr" diff --git a/tests/MC/AArch64/CSSC/umin_64_imm.s.yaml b/tests/MC/AArch64/CSSC/umin_64_imm.s.yaml new file mode 100644 index 0000000000..c73be6c477 --- /dev/null +++ b/tests/MC/AArch64/CSSC/umin_64_imm.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xcc, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umin x0, x0, #0" + + - + input: + bytes: [ 0x55, 0x55, 0xcd, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umin x21, x10, #85" + + - + input: + bytes: [ 0xb7, 0xed, 0xcc, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umin x23, x13, #59" + + - + input: + bytes: [ 0xff, 0xff, 0xcf, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umin xzr, xzr, #255" diff --git a/tests/MC/AArch64/CSSC/umin_64_reg.s.yaml b/tests/MC/AArch64/CSSC/umin_64_reg.s.yaml new file mode 100644 index 0000000000..8e3e58d9e1 --- /dev/null +++ b/tests/MC/AArch64/CSSC/umin_64_reg.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x6c, 0xc0, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umin x0, x0, x0" + + - + input: + bytes: [ 0x55, 0x6d, 0xd5, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umin x21, x10, x21" + + - + input: + bytes: [ 0xb7, 0x6d, 0xc8, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umin x23, x13, x8" + + - + input: + bytes: [ 0xff, 0x6f, 0xdf, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "umin xzr, xzr, xzr" diff --git a/tests/MC/AArch64/FP8/dot.s.yaml b/tests/MC/AArch64/FP8/dot.s.yaml new file mode 100644 index 0000000000..7a2716fdc5 --- /dev/null +++ b/tests/MC/AArch64/FP8/dot.s.yaml @@ -0,0 +1,90 @@ +test_cases: + - + input: + bytes: [ 0x1f, 0xfc, 0x40, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8dot2", "+fp8dot4" ] + expected: + insns: + - + asm_text: "fdot v31.4h, v0.8b, v0.8b" + + - + input: + bytes: [ 0x1f, 0xfc, 0x5f, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8dot2", "+fp8dot4" ] + expected: + insns: + - + asm_text: "fdot v31.8h, v0.16b, v31.16b" + + - + input: + bytes: [ 0x00, 0xfc, 0x1f, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8dot2", "+fp8dot4" ] + expected: + insns: + - + asm_text: "fdot v0.2s, v0.8b, v31.8b" + + - + input: + bytes: [ 0x1f, 0xfc, 0x1f, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8dot2", "+fp8dot4" ] + expected: + insns: + - + asm_text: "fdot v31.4s, v0.16b, v31.16b" + + - + input: + bytes: [ 0xff, 0x03, 0x4f, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8dot2", "+fp8dot4" ] + expected: + insns: + - + asm_text: "fdot v31.4h, v31.8b, v15.2b[0]" + + - + input: + bytes: [ 0xda, 0x02, 0x49, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8dot2", "+fp8dot4" ] + expected: + insns: + - + asm_text: "fdot v26.8h, v22.16b, v9.2b[0]" + + - + input: + bytes: [ 0x00, 0x08, 0x7f, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8dot2", "+fp8dot4" ] + expected: + insns: + - + asm_text: "fdot v0.8h, v0.16b, v15.2b[7]" + + - + input: + bytes: [ 0x00, 0x00, 0x1f, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8dot2", "+fp8dot4" ] + expected: + insns: + - + asm_text: "fdot v0.2s, v0.8b, v31.4b[0]" + + - + input: + bytes: [ 0xe0, 0x0b, 0x20, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8dot2", "+fp8dot4" ] + expected: + insns: + - + asm_text: "fdot v0.4s, v31.16b, v0.4b[3]" diff --git a/tests/MC/AArch64/FP8/faminmax.s.yaml b/tests/MC/AArch64/FP8/faminmax.s.yaml new file mode 100644 index 0000000000..25292d895a --- /dev/null +++ b/tests/MC/AArch64/FP8/faminmax.s.yaml @@ -0,0 +1,300 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x1f, 0xdf, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famax v31.4h, v31.4h, v31.4h" + + - + input: + bytes: [ 0x1f, 0x1c, 0xdf, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famax v31.4h, v0.4h, v31.4h" + + - + input: + bytes: [ 0x00, 0x1c, 0xc0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famax v0.4h, v0.4h, v0.4h" + + - + input: + bytes: [ 0xff, 0x1f, 0xdf, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famax v31.8h, v31.8h, v31.8h" + + - + input: + bytes: [ 0xff, 0x1f, 0xc0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famax v31.8h, v31.8h, v0.8h" + + - + input: + bytes: [ 0x00, 0x1c, 0xc0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famax v0.8h, v0.8h, v0.8h" + + - + input: + bytes: [ 0xff, 0xdf, 0xbf, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famax v31.2s, v31.2s, v31.2s" + + - + input: + bytes: [ 0x1f, 0xdc, 0xa0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famax v31.2s, v0.2s, v0.2s" + + - + input: + bytes: [ 0x00, 0xdc, 0xa0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famax v0.2s, v0.2s, v0.2s" + + - + input: + bytes: [ 0xff, 0xdf, 0xbf, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famax v31.4s, v31.4s, v31.4s" + + - + input: + bytes: [ 0xe0, 0xdf, 0xbf, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famax v0.4s, v31.4s, v31.4s" + + - + input: + bytes: [ 0x00, 0xdc, 0xa0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famax v0.4s, v0.4s, v0.4s" + + - + input: + bytes: [ 0xff, 0xdf, 0xff, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famax v31.2d, v31.2d, v31.2d" + + - + input: + bytes: [ 0x00, 0xdc, 0xff, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famax v0.2d, v0.2d, v31.2d" + + - + input: + bytes: [ 0x00, 0xdc, 0xe0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famax v0.2d, v0.2d, v0.2d" + + - + input: + bytes: [ 0xff, 0x1f, 0xdf, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famin v31.4h, v31.4h, v31.4h" + + - + input: + bytes: [ 0x1f, 0x1c, 0xdf, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famin v31.4h, v0.4h, v31.4h" + + - + input: + bytes: [ 0x00, 0x1c, 0xc0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famin v0.4h, v0.4h, v0.4h" + + - + input: + bytes: [ 0xff, 0x1f, 0xdf, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famin v31.8h, v31.8h, v31.8h" + + - + input: + bytes: [ 0xff, 0x1f, 0xc0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famin v31.8h, v31.8h, v0.8h" + + - + input: + bytes: [ 0x00, 0x1c, 0xc0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famin v0.8h, v0.8h, v0.8h" + + - + input: + bytes: [ 0xff, 0xdf, 0xbf, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famin v31.2s, v31.2s, v31.2s" + + - + input: + bytes: [ 0x1f, 0xdc, 0xa0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famin v31.2s, v0.2s, v0.2s" + + - + input: + bytes: [ 0x00, 0xdc, 0xa0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famin v0.2s, v0.2s, v0.2s" + + - + input: + bytes: [ 0xff, 0xdf, 0xbf, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famin v31.4s, v31.4s, v31.4s" + + - + input: + bytes: [ 0xe0, 0xdf, 0xbf, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famin v0.4s, v31.4s, v31.4s" + + - + input: + bytes: [ 0x00, 0xdc, 0xa0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famin v0.4s, v0.4s, v0.4s" + + - + input: + bytes: [ 0xff, 0xdf, 0xff, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famin v31.2d, v31.2d, v31.2d" + + - + input: + bytes: [ 0x00, 0xdc, 0xff, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famin v0.2d, v0.2d, v31.2d" + + - + input: + bytes: [ 0x00, 0xdc, 0xe0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ] + expected: + insns: + - + asm_text: "famin v0.2d, v0.2d, v0.2d" diff --git a/tests/MC/AArch64/FP8/luti2.s.yaml b/tests/MC/AArch64/FP8/luti2.s.yaml new file mode 100644 index 0000000000..59b52d4123 --- /dev/null +++ b/tests/MC/AArch64/FP8/luti2.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x41, 0x10, 0x80, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "lut" ] + expected: + insns: + - + asm_text: "luti2 v1.16b, { v2.16b }, v0[0]" + + - + input: + bytes: [ 0x9e, 0x72, 0x9f, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "lut" ] + expected: + insns: + - + asm_text: "luti2 v30.16b, { v20.16b }, v31[3]" + + - + input: + bytes: [ 0x41, 0x00, 0xc0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "lut" ] + expected: + insns: + - + asm_text: "luti2 v1.8h, { v2.8h }, v0[0]" + + - + input: + bytes: [ 0x9e, 0x72, 0xdf, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "lut" ] + expected: + insns: + - + asm_text: "luti2 v30.8h, { v20.8h }, v31[7]" diff --git a/tests/MC/AArch64/FP8/luti4.s.yaml b/tests/MC/AArch64/FP8/luti4.s.yaml new file mode 100644 index 0000000000..ecd19031ad --- /dev/null +++ b/tests/MC/AArch64/FP8/luti4.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x41, 0x20, 0x40, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "lut" ] + expected: + insns: + - + asm_text: "luti4 v1.16b, { v2.16b }, v0[0]" + + - + input: + bytes: [ 0x9e, 0x62, 0x5f, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "lut" ] + expected: + insns: + - + asm_text: "luti4 v30.16b, { v20.16b }, v31[1]" + + - + input: + bytes: [ 0x41, 0x10, 0x40, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "lut" ] + expected: + insns: + - + asm_text: "luti4 v1.8h, { v2.8h, v3.8h }, v0[0]" + + - + input: + bytes: [ 0x9e, 0x72, 0x5f, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "lut" ] + expected: + insns: + - + asm_text: "luti4 v30.8h, { v20.8h, v21.8h }, v31[3]" diff --git a/tests/MC/AArch64/FP8/miscellaneous-fp8.s.yaml b/tests/MC/AArch64/FP8/miscellaneous-fp8.s.yaml new file mode 100644 index 0000000000..35e095d292 --- /dev/null +++ b/tests/MC/AArch64/FP8/miscellaneous-fp8.s.yaml @@ -0,0 +1,510 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x78, 0xa1, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "bf1cvtl v0.8h, v0.8b" + + - + input: + bytes: [ 0xe0, 0x7b, 0xa1, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "bf1cvtl v0.8h, v31.8b" + + - + input: + bytes: [ 0xff, 0x7b, 0xa1, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "bf1cvtl v31.8h, v31.8b" + + - + input: + bytes: [ 0x00, 0x78, 0xa1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "bf1cvtl2 v0.8h, v0.16b" + + - + input: + bytes: [ 0xe0, 0x7b, 0xa1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "bf1cvtl2 v0.8h, v31.16b" + + - + input: + bytes: [ 0xff, 0x7b, 0xa1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "bf1cvtl2 v31.8h, v31.16b" + + - + input: + bytes: [ 0x00, 0x78, 0xe1, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "bf2cvtl v0.8h, v0.8b" + + - + input: + bytes: [ 0xe0, 0x7b, 0xe1, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "bf2cvtl v0.8h, v31.8b" + + - + input: + bytes: [ 0xff, 0x7b, 0xe1, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "bf2cvtl v31.8h, v31.8b" + + - + input: + bytes: [ 0x00, 0x78, 0xe1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "bf2cvtl2 v0.8h, v0.16b" + + - + input: + bytes: [ 0xe0, 0x7b, 0xe1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "bf2cvtl2 v0.8h, v31.16b" + + - + input: + bytes: [ 0xff, 0x7b, 0xe1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "bf2cvtl2 v31.8h, v31.16b" + + - + input: + bytes: [ 0x00, 0x78, 0x21, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "f1cvtl v0.8h, v0.8b" + + - + input: + bytes: [ 0xe0, 0x7b, 0x21, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "f1cvtl v0.8h, v31.8b" + + - + input: + bytes: [ 0xff, 0x7b, 0x21, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "f1cvtl v31.8h, v31.8b" + + - + input: + bytes: [ 0x00, 0x78, 0x21, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "f1cvtl2 v0.8h, v0.16b" + + - + input: + bytes: [ 0xe0, 0x7b, 0x21, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "f1cvtl2 v0.8h, v31.16b" + + - + input: + bytes: [ 0xff, 0x7b, 0x21, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "f1cvtl2 v31.8h, v31.16b" + + - + input: + bytes: [ 0x00, 0x78, 0x61, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "f2cvtl v0.8h, v0.8b" + + - + input: + bytes: [ 0xe0, 0x7b, 0x61, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "f2cvtl v0.8h, v31.8b" + + - + input: + bytes: [ 0xff, 0x7b, 0x61, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "f2cvtl v31.8h, v31.8b" + + - + input: + bytes: [ 0x00, 0x78, 0x61, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "f2cvtl2 v0.8h, v0.16b" + + - + input: + bytes: [ 0xe0, 0x7b, 0x61, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "f2cvtl2 v0.8h, v31.16b" + + - + input: + bytes: [ 0xff, 0x7b, 0x61, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "f2cvtl2 v31.8h, v31.16b" + + - + input: + bytes: [ 0xff, 0xf7, 0x5f, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fcvtn v31.8b, v31.4h, v31.4h" + + - + input: + bytes: [ 0x1f, 0xf4, 0x40, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fcvtn v31.8b, v0.4h, v0.4h" + + - + input: + bytes: [ 0x00, 0xf4, 0x40, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fcvtn v0.8b, v0.4h, v0.4h" + + - + input: + bytes: [ 0x00, 0xf4, 0x40, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fcvtn v0.16b, v0.8h, v0.8h" + + - + input: + bytes: [ 0x1f, 0xf4, 0x40, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fcvtn v31.16b, v0.8h, v0.8h" + + - + input: + bytes: [ 0xff, 0xf7, 0x5f, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fcvtn v31.16b, v31.8h, v31.8h" + + - + input: + bytes: [ 0x00, 0xf4, 0x00, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fcvtn v0.8b, v0.4s, v0.4s" + + - + input: + bytes: [ 0xe0, 0xf7, 0x1f, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fcvtn v0.8b, v31.4s, v31.4s" + + - + input: + bytes: [ 0xff, 0xf7, 0x1f, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fcvtn v31.8b, v31.4s, v31.4s" + + - + input: + bytes: [ 0x00, 0xf4, 0x00, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fcvtn2 v0.16b, v0.4s, v0.4s" + + - + input: + bytes: [ 0x00, 0xf4, 0x1f, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fcvtn2 v0.16b, v0.4s, v31.4s" + + - + input: + bytes: [ 0xff, 0xf7, 0x1f, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fcvtn2 v31.16b, v31.4s, v31.4s" + + - + input: + bytes: [ 0x00, 0x3c, 0xc0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fscale v0.4h, v0.4h, v0.4h" + + - + input: + bytes: [ 0xe0, 0x3f, 0xdf, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fscale v0.4h, v31.4h, v31.4h" + + - + input: + bytes: [ 0xff, 0x3f, 0xdf, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fscale v31.4h, v31.4h, v31.4h" + + - + input: + bytes: [ 0x00, 0x3c, 0xc0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fscale v0.8h, v0.8h, v0.8h" + + - + input: + bytes: [ 0x1f, 0x3c, 0xc0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fscale v31.8h, v0.8h, v0.8h" + + - + input: + bytes: [ 0xff, 0x3f, 0xdf, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fscale v31.8h, v31.8h, v31.8h" + + - + input: + bytes: [ 0x00, 0xfc, 0xa0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fscale v0.2s, v0.2s, v0.2s" + + - + input: + bytes: [ 0x00, 0xfc, 0xbf, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fscale v0.2s, v0.2s, v31.2s" + + - + input: + bytes: [ 0xff, 0xff, 0xbf, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fscale v31.2s, v31.2s, v31.2s" + + - + input: + bytes: [ 0x00, 0xfc, 0xa0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fscale v0.4s, v0.4s, v0.4s" + + - + input: + bytes: [ 0xe0, 0xff, 0xa0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fscale v0.4s, v31.4s, v0.4s" + + - + input: + bytes: [ 0xff, 0xff, 0xbf, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fscale v31.4s, v31.4s, v31.4s" + + - + input: + bytes: [ 0x00, 0xfc, 0xe0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fscale v0.2d, v0.2d, v0.2d" + + - + input: + bytes: [ 0xe0, 0xff, 0xe0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fscale v0.2d, v31.2d, v0.2d" + + - + input: + bytes: [ 0xff, 0xff, 0xff, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ] + expected: + insns: + - + asm_text: "fscale v31.2d, v31.2d, v31.2d" diff --git a/tests/MC/AArch64/FP8/mla.s.yaml b/tests/MC/AArch64/FP8/mla.s.yaml new file mode 100644 index 0000000000..cae0c65382 --- /dev/null +++ b/tests/MC/AArch64/FP8/mla.s.yaml @@ -0,0 +1,130 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xfc, 0xc0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ] + expected: + insns: + - + asm_text: "fmlalb v0.8h, v0.16b, v0.16b" + + - + input: + bytes: [ 0xff, 0xff, 0xdf, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ] + expected: + insns: + - + asm_text: "fmlalt v31.8h, v31.16b, v31.16b" + + - + input: + bytes: [ 0x00, 0xc4, 0x1f, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ] + expected: + insns: + - + asm_text: "fmlallbb v0.4s, v0.16b, v31.16b" + + - + input: + bytes: [ 0xff, 0xc7, 0x40, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ] + expected: + insns: + - + asm_text: "fmlallbt v31.4s, v31.16b, v0.16b" + + - + input: + bytes: [ 0xff, 0xc7, 0x00, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ] + expected: + insns: + - + asm_text: "fmlalltb v31.4s, v31.16b, v0.16b" + + - + input: + bytes: [ 0x00, 0xc4, 0x5f, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ] + expected: + insns: + - + asm_text: "fmlalltt v0.4s, v0.16b, v31.16b" + + - + input: + bytes: [ 0xff, 0xc7, 0x5f, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ] + expected: + insns: + - + asm_text: "fmlalltt v31.4s, v31.16b, v31.16b" + + - + input: + bytes: [ 0x1f, 0x00, 0xc0, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ] + expected: + insns: + - + asm_text: "fmlalb v31.8h, v0.16b, v0.b[0]" + + - + input: + bytes: [ 0x1f, 0x08, 0xf8, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ] + expected: + insns: + - + asm_text: "fmlalt v31.8h, v0.16b, v0.b[15]" + + - + input: + bytes: [ 0x1f, 0x80, 0x07, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ] + expected: + insns: + - + asm_text: "fmlallbb v31.4s, v0.16b, v7.b[0]" + + - + input: + bytes: [ 0x1f, 0x80, 0x47, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ] + expected: + insns: + - + asm_text: "fmlalltt v31.4s, v0.16b, v7.b[0]" + + - + input: + bytes: [ 0xe0, 0x8b, 0x3f, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ] + expected: + insns: + - + asm_text: "fmlalltb v0.4s, v31.16b, v7.b[15]" + + - + input: + bytes: [ 0xe0, 0x8b, 0x78, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ] + expected: + insns: + - + asm_text: "fmlallbt v0.4s, v31.16b, v0.b[15]" diff --git a/tests/MC/AArch64/FP8/system-regs.s.yaml b/tests/MC/AArch64/FP8/system-regs.s.yaml new file mode 100644 index 0000000000..4acc7a8284 --- /dev/null +++ b/tests/MC/AArch64/FP8/system-regs.s.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0x43, 0x44, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fpmr" ] + expected: + insns: + - + asm_text: "mrs x3, FPMR" + + - + input: + bytes: [ 0xe3, 0x04, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fpmr" ] + expected: + insns: + - + asm_text: "mrs x3, ID_AA64FPFR0_EL1" + + - + input: + bytes: [ 0x43, 0x44, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fpmr" ] + expected: + insns: + - + asm_text: "msr FPMR, x3" diff --git a/tests/MC/AArch64/FP8_SME2/cvt.s.yaml b/tests/MC/AArch64/FP8_SME2/cvt.s.yaml new file mode 100644 index 0000000000..89b871cf8d --- /dev/null +++ b/tests/MC/AArch64/FP8_SME2/cvt.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x26, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvt { z0.h, z1.h }, z0.b" + + - + input: + bytes: [ 0xfe, 0xe3, 0x26, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvt { z30.h, z31.h }, z31.b" + + - + input: + bytes: [ 0x01, 0xe0, 0x26, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvtl { z0.h, z1.h }, z0.b" + + - + input: + bytes: [ 0xff, 0xe3, 0x26, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvtl { z30.h, z31.h }, z31.b" + + - + input: + bytes: [ 0x00, 0xe0, 0x66, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvt { z0.h, z1.h }, z0.b" + + - + input: + bytes: [ 0xfe, 0xe3, 0x66, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvt { z30.h, z31.h }, z31.b" + + - + input: + bytes: [ 0x01, 0xe0, 0x66, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvtl { z0.h, z1.h }, z0.b" + + - + input: + bytes: [ 0xff, 0xe3, 0x66, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvtl { z30.h, z31.h }, z31.b" + + - + input: + bytes: [ 0x00, 0xe0, 0xe6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvt { z0.h, z1.h }, z0.b" + + - + input: + bytes: [ 0xfe, 0xe3, 0xe6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvt { z30.h, z31.h }, z31.b" + + - + input: + bytes: [ 0x01, 0xe0, 0xe6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvtl { z0.h, z1.h }, z0.b" + + - + input: + bytes: [ 0xff, 0xe3, 0xe6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvtl { z30.h, z31.h }, z31.b" + + - + input: + bytes: [ 0x00, 0xe0, 0xa6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvt { z0.h, z1.h }, z0.b" + + - + input: + bytes: [ 0xfe, 0xe3, 0xa6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvt { z30.h, z31.h }, z31.b" + + - + input: + bytes: [ 0x01, 0xe0, 0xa6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvtl { z0.h, z1.h }, z0.b" + + - + input: + bytes: [ 0xff, 0xe3, 0xa6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvtl { z30.h, z31.h }, z31.b" + + - + input: + bytes: [ 0x00, 0xe0, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvt z0.b, { z0.h, z1.h }" + + - + input: + bytes: [ 0xdf, 0xe3, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvt z31.b, { z30.h, z31.h }" + + - + input: + bytes: [ 0x00, 0xe0, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvt z0.b, { z0.s - z3.s }" + + - + input: + bytes: [ 0x9f, 0xe3, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvt z31.b, { z28.s - z31.s }" + + - + input: + bytes: [ 0x20, 0xe0, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtn z0.b, { z0.s - z3.s }" + + - + input: + bytes: [ 0xbf, 0xe3, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtn z31.b, { z28.s - z31.s }" + + - + input: + bytes: [ 0x00, 0xe0, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bfcvt z0.b, { z0.h, z1.h }" + + - + input: + bytes: [ 0xdf, 0xe3, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bfcvt z31.b, { z30.h, z31.h }" diff --git a/tests/MC/AArch64/FP8_SME2/dot.s.yaml b/tests/MC/AArch64/FP8_SME2/dot.s.yaml new file mode 100644 index 0000000000..e762d7cc87 --- /dev/null +++ b/tests/MC/AArch64/FP8_SME2/dot.s.yaml @@ -0,0 +1,560 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x10, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x08, 0x10, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0xaf, 0x71, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w11, 7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xef, 0x73, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w11, 7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0x18, 0x10, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x18, 0x10, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0xff, 0x73, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0xff, 0x73, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0x20, 0x10, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x20, 0x10, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0xe7, 0x73, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xe7, 0x73, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x30, 0x10, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x30, 0x10, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0xf7, 0x73, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xf7, 0x73, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x20, 0x00, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x20, 0x00, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0xef, 0x6f, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w11, 7, vgx2], { z30.b, z31.b }, z15.b[7]" + + - + input: + bytes: [ 0xef, 0x6f, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w11, 7, vgx2], { z30.b, z31.b }, z15.b[7]" + + - + input: + bytes: [ 0x38, 0x00, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x38, 0x00, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0xff, 0x6f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]" + + - + input: + bytes: [ 0xff, 0x6f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]" + + - + input: + bytes: [ 0x08, 0x10, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w8, 0, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x08, 0x10, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w8, 0, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0xef, 0x73, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0xef, 0x73, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0x18, 0x10, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x18, 0x10, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0xff, 0x73, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0xff, 0x73, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0x20, 0x10, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x20, 0x10, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0xa7, 0x73, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0xa7, 0x73, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x40, 0x90, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x30, 0x10, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x30, 0x10, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0xb7, 0x73, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0xb7, 0x73, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x40, 0x90, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0xcf, 0xff, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w11, 7, vgx4], { z28.b - z31.b }, z15.b[7]" + + - + input: + bytes: [ 0xcf, 0xff, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.h[w11, 7, vgx4], { z28.b - z31.b }, z15.b[7]" + + - + input: + bytes: [ 0x08, 0x80, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x08, 0x80, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x8f, 0xef, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]" + + - + input: + bytes: [ 0x8f, 0xef, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]" + + - + input: + bytes: [ 0x20, 0x10, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fvdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x20, 0x10, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fvdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0xef, 0x7f, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fvdot za.h[w11, 7, vgx2], { z30.b, z31.b }, z15.b[7]" + + - + input: + bytes: [ 0xef, 0x7f, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fvdot za.h[w11, 7, vgx2], { z30.b, z31.b }, z15.b[7]" + + - + input: + bytes: [ 0x00, 0x08, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fvdotb za.s[w8, 0, vgx4], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0xcf, 0x6f, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fvdotb za.s[w11, 7, vgx4], { z30.b, z31.b }, z15.b[3]" + + - + input: + bytes: [ 0x10, 0x08, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fvdott za.s[w8, 0, vgx4], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0xdf, 0x6f, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fvdott za.s[w11, 7, vgx4], { z30.b, z31.b }, z15.b[3]" diff --git a/tests/MC/AArch64/FP8_SME2/faminmax.s.yaml b/tests/MC/AArch64/FP8_SME2/faminmax.s.yaml new file mode 100644 index 0000000000..c678bcbf6c --- /dev/null +++ b/tests/MC/AArch64/FP8_SME2/faminmax.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x40, 0xb1, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x5e, 0xb1, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x40, 0xb1, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x5e, 0xb1, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x40, 0xb1, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x5e, 0xb1, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x40, 0xb9, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x5c, 0xb9, 0x7c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x40, 0xb9, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x5c, 0xb9, 0xbc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x40, 0xb9, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x5c, 0xb9, 0x7c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x41, 0xb1, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x5f, 0xb1, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x41, 0xb1, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x5f, 0xb1, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x41, 0xb1, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x5f, 0xb1, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x41, 0xb9, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x5d, 0xb9, 0x7c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x41, 0xb9, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x5d, 0xb9, 0xbc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x41, 0xb9, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x5d, 0xb9, 0xfc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }" diff --git a/tests/MC/AArch64/FP8_SME2/fscale.s.yaml b/tests/MC/AArch64/FP8_SME2/fscale.s.yaml new file mode 100644 index 0000000000..ed662e0d1e --- /dev/null +++ b/tests/MC/AArch64/FP8_SME2/fscale.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x80, 0xa1, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z0.h, z1.h }, { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x9e, 0xa1, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z30.h, z31.h }, { z30.h, z31.h }, z15.h" + + - + input: + bytes: [ 0x80, 0xa1, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z0.s, z1.s }, { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x9e, 0xa1, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z30.s, z31.s }, { z30.s, z31.s }, z15.s" + + - + input: + bytes: [ 0x80, 0xa1, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z0.d, z1.d }, { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x9e, 0xa1, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z30.d, z31.d }, { z30.d, z31.d }, z15.d" + + - + input: + bytes: [ 0x80, 0xb1, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x9e, 0xb1, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x80, 0xb1, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x9e, 0xb1, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x80, 0xb1, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x9e, 0xb1, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x80, 0xa9, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z0.h - z3.h }, { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x9c, 0xa9, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z28.h - z31.h }, { z28.h - z31.h }, z15.h" + + - + input: + bytes: [ 0x80, 0xa9, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z0.s - z3.s }, { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x9c, 0xa9, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z28.s - z31.s }, { z28.s - z31.s }, z15.s" + + - + input: + bytes: [ 0x80, 0xa9, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z0.d - z3.d }, { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x9c, 0xa9, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z28.d - z31.d }, { z28.d - z31.d }, z15.d" + + - + input: + bytes: [ 0x80, 0xb9, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x9c, 0xb9, 0x7c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x80, 0xb9, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x9c, 0xb9, 0xbc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x80, 0xb9, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x9c, 0xb9, 0xfc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fscale { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }" diff --git a/tests/MC/AArch64/FP8_SME2/lut.s.yaml b/tests/MC/AArch64/FP8_SME2/lut.s.yaml new file mode 100644 index 0000000000..271782a4b6 --- /dev/null +++ b/tests/MC/AArch64/FP8_SME2/lut.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x8b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme2p1", "+sme-lutv2" ] + expected: + insns: + - + asm_text: "luti4 { z0.b - z3.b }, zt0, { z0, z1 }" + + - + input: + bytes: [ 0xdc, 0x03, 0x8b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme2p1", "+sme-lutv2" ] + expected: + insns: + - + asm_text: "luti4 { z28.b - z31.b }, zt0, { z30, z31 }" + + - + input: + bytes: [ 0x00, 0x00, 0x9b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme2p1", "+sme-lutv2" ] + expected: + insns: + - + asm_text: "luti4 { z0.b, z4.b, z8.b, z12.b }, zt0, { z0, z1 }" + + - + input: + bytes: [ 0xd3, 0x03, 0x9b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme2p1", "+sme-lutv2" ] + expected: + insns: + - + asm_text: "luti4 { z19.b, z23.b, z27.b, z31.b }, zt0, { z30, z31 }" diff --git a/tests/MC/AArch64/FP8_SME2/mla.s.yaml b/tests/MC/AArch64/FP8_SME2/mla.s.yaml new file mode 100644 index 0000000000..7b0f23e79d --- /dev/null +++ b/tests/MC/AArch64/FP8_SME2/mla.s.yaml @@ -0,0 +1,560 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x0c, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w8, 0:1], z0.b, z0.b" + + - + input: + bytes: [ 0xe7, 0x6f, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w11, 14:15], z31.b, z15.b" + + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w8, 0:1], z0.b, z0.b[0]" + + - + input: + bytes: [ 0xef, 0xef, 0xcf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w11, 14:15], z31.b, z15.b[15]" + + - + input: + bytes: [ 0x04, 0x08, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w8, 0:1, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x04, 0x08, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w8, 0:1, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0xe7, 0x6b, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w11, 6:7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0xe7, 0x6b, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w11, 6:7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0x20, 0x08, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w8, 0:1, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x20, 0x08, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w8, 0:1, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0xe3, 0x6b, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w11, 6:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xe3, 0x6b, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w11, 6:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x30, 0x10, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w8, 0:1, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x30, 0x10, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w8, 0:1, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0xff, 0x7f, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w11, 6:7, vgx2], { z30.b, z31.b }, z15.b[15]" + + - + input: + bytes: [ 0xff, 0x7f, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w11, 6:7, vgx2], { z30.b, z31.b }, z15.b[15]" + + - + input: + bytes: [ 0x04, 0x08, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w8, 0:1, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x04, 0x08, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w8, 0:1, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0xe7, 0x6b, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w11, 6:7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0xe7, 0x6b, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w11, 6:7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0x20, 0x08, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w8, 0:1, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x20, 0x08, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w8, 0:1, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0xa3, 0x6b, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w11, 6:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0xa3, 0x6b, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w11, 6:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x20, 0x90, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w8, 0:1, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x20, 0x90, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w8, 0:1, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0xaf, 0xff, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w11, 6:7, vgx4], { z28.b - z31.b }, z15.b[15]" + + - + input: + bytes: [ 0xaf, 0xff, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlal za.h[w11, 6:7, vgx4], { z28.b - z31.b }, z15.b[15]" + + - + input: + bytes: [ 0x00, 0x04, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w8, 0:3], z0.b, z0.b" + + - + input: + bytes: [ 0xe3, 0x67, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w11, 12:15], z31.b, z15.b" + + - + input: + bytes: [ 0x00, 0x00, 0x40, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w8, 0:3], z0.b, z0.b[0]" + + - + input: + bytes: [ 0xe3, 0xff, 0x4f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w11, 12:15], z31.b, z15.b[15]" + + - + input: + bytes: [ 0x02, 0x00, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x02, 0x00, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0xe3, 0x63, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w11, 4:7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0xe3, 0x63, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w11, 4:7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0x20, 0x00, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x20, 0x00, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0xe1, 0x63, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xe1, 0x63, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x20, 0x00, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x20, 0x00, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0xe7, 0x6f, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]" + + - + input: + bytes: [ 0xe7, 0x6f, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]" + + - + input: + bytes: [ 0x02, 0x00, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x02, 0x00, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0xe3, 0x63, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w11, 4:7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0xe3, 0x63, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w11, 4:7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0x20, 0x00, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x20, 0x00, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0xa1, 0x63, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0xa1, 0x63, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x40, 0x80, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x40, 0x80, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0xc7, 0xef, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]" + + - + input: + bytes: [ 0xc7, 0xef, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]" diff --git a/tests/MC/AArch64/FP8_SME2/mopa.s.yaml b/tests/MC/AArch64/FP8_SME2/mopa.s.yaml new file mode 100644 index 0000000000..7f831e83dc --- /dev/null +++ b/tests/MC/AArch64/FP8_SME2/mopa.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x00, 0xa0, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmopa za0.h, p0/m, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0xe9, 0xff, 0xbf, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmopa za1.h, p7/m, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0x00, 0xa0, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmopa za0.s, p0/m, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0xe3, 0xff, 0xbf, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ] + expected: + insns: + - + asm_text: "fmopa za3.s, p7/m, p7/m, z31.b, z31.b" diff --git a/tests/MC/AArch64/FP8_SME2/movt.s.yaml b/tests/MC/AArch64/FP8_SME2/movt.s.yaml new file mode 100644 index 0000000000..f8364b7a60 --- /dev/null +++ b/tests/MC/AArch64/FP8_SME2/movt.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x03, 0x4f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-lutv2" ] + expected: + insns: + - + asm_text: "movt zt0, z0" + + - + input: + bytes: [ 0xff, 0x33, 0x4f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-lutv2" ] + expected: + insns: + - + asm_text: "movt zt0[3, mul vl], z31" diff --git a/tests/MC/AArch64/FP8_SVE2/faminmax.s.yaml b/tests/MC/AArch64/FP8_SVE2/faminmax.s.yaml new file mode 100644 index 0000000000..63e32a4f5a --- /dev/null +++ b/tests/MC/AArch64/FP8_SVE2/faminmax.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x4f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x8d, 0x4f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xdf, 0x9f, 0x4f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin z31.h, p7/m, z31.h, z30.h" + + - + input: + bytes: [ 0x20, 0x80, 0x8f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin z0.s, p0/m, z0.s, z1.s" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x8d, 0x8f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin z23.s, p3/m, z23.s, z13.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0x8f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin z31.s, p7/m, z31.s, z30.s" + + - + input: + bytes: [ 0x20, 0x80, 0xcf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin z0.d, p0/m, z0.d, z1.d" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x8d, 0xcf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin z23.d, p3/m, z23.d, z13.d" + + - + input: + bytes: [ 0xdf, 0x9f, 0xcf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x4e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x8d, 0x4e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xdf, 0x9f, 0x4e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax z31.h, p7/m, z31.h, z30.h" + + - + input: + bytes: [ 0x20, 0x80, 0x8e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax z0.s, p0/m, z0.s, z1.s" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x8d, 0x8e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax z23.s, p3/m, z23.s, z13.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0x8e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax z31.s, p7/m, z31.s, z30.s" + + - + input: + bytes: [ 0x20, 0x80, 0xce, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax z0.d, p0/m, z0.d, z1.d" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x8d, 0xce, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax z23.d, p3/m, z23.d, z13.d" + + - + input: + bytes: [ 0xdf, 0x9f, 0xce, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x4f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x8d, 0x4f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xdf, 0x9f, 0x4f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin z31.h, p7/m, z31.h, z30.h" + + - + input: + bytes: [ 0x20, 0x80, 0x8f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin z0.s, p0/m, z0.s, z1.s" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x8d, 0x8f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin z23.s, p3/m, z23.s, z13.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0x8f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin z31.s, p7/m, z31.s, z30.s" + + - + input: + bytes: [ 0x20, 0x80, 0xcf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin z0.d, p0/m, z0.d, z1.d" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x8d, 0xcf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin z23.d, p3/m, z23.d, z13.d" + + - + input: + bytes: [ 0xdf, 0x9f, 0xcf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famin z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x4e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x8d, 0x4e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xdf, 0x9f, 0x4e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax z31.h, p7/m, z31.h, z30.h" + + - + input: + bytes: [ 0x20, 0x80, 0x8e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax z0.s, p0/m, z0.s, z1.s" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x8d, 0x8e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax z23.s, p3/m, z23.s, z13.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0x8e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax z31.s, p7/m, z31.s, z30.s" + + - + input: + bytes: [ 0x20, 0x80, 0xce, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax z0.d, p0/m, z0.d, z1.d" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x8d, 0xce, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax z23.d, p3/m, z23.d, z13.d" + + - + input: + bytes: [ 0xdf, 0x9f, 0xce, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ] + expected: + insns: + - + asm_text: "famax z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/FP8_SVE2/fcvt.s.yaml b/tests/MC/AArch64/FP8_SVE2/fcvt.s.yaml new file mode 100644 index 0000000000..2da807e2d9 --- /dev/null +++ b/tests/MC/AArch64/FP8_SVE2/fcvt.s.yaml @@ -0,0 +1,640 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x30, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvt z0.h, z0.b" + + - + input: + bytes: [ 0xe0, 0x33, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvt z0.h, z31.b" + + - + input: + bytes: [ 0x1f, 0x30, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvt z31.h, z0.b" + + - + input: + bytes: [ 0xff, 0x33, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvt z31.h, z31.b" + + - + input: + bytes: [ 0x00, 0x34, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvt z0.h, z0.b" + + - + input: + bytes: [ 0xe0, 0x37, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvt z0.h, z31.b" + + - + input: + bytes: [ 0x1f, 0x34, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvt z31.h, z0.b" + + - + input: + bytes: [ 0xff, 0x37, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvt z31.h, z31.b" + + - + input: + bytes: [ 0x00, 0x38, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvt z0.h, z0.b" + + - + input: + bytes: [ 0xe0, 0x3b, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvt z0.h, z31.b" + + - + input: + bytes: [ 0x1f, 0x38, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvt z31.h, z0.b" + + - + input: + bytes: [ 0xff, 0x3b, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvt z31.h, z31.b" + + - + input: + bytes: [ 0x00, 0x3c, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvt z0.h, z0.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvt z0.h, z31.b" + + - + input: + bytes: [ 0x1f, 0x3c, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvt z31.h, z0.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvt z31.h, z31.b" + + - + input: + bytes: [ 0x00, 0x30, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvtlt z0.h, z0.b" + + - + input: + bytes: [ 0xe0, 0x33, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvtlt z0.h, z31.b" + + - + input: + bytes: [ 0x1f, 0x30, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvtlt z31.h, z0.b" + + - + input: + bytes: [ 0xff, 0x33, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvtlt z31.h, z31.b" + + - + input: + bytes: [ 0x00, 0x34, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvtlt z0.h, z0.b" + + - + input: + bytes: [ 0xe0, 0x37, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvtlt z0.h, z31.b" + + - + input: + bytes: [ 0x1f, 0x34, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvtlt z31.h, z0.b" + + - + input: + bytes: [ 0xff, 0x37, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvtlt z31.h, z31.b" + + - + input: + bytes: [ 0x00, 0x38, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvtlt z0.h, z0.b" + + - + input: + bytes: [ 0xe0, 0x3b, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvtlt z0.h, z31.b" + + - + input: + bytes: [ 0x1f, 0x38, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvtlt z31.h, z0.b" + + - + input: + bytes: [ 0xff, 0x3b, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvtlt z31.h, z31.b" + + - + input: + bytes: [ 0x00, 0x3c, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvtlt z0.h, z0.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvtlt z0.h, z31.b" + + - + input: + bytes: [ 0x1f, 0x3c, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvtlt z31.h, z0.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvtlt z31.h, z31.b" + + - + input: + bytes: [ 0x00, 0x30, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvt z0.h, z0.b" + + - + input: + bytes: [ 0xe0, 0x33, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvt z0.h, z31.b" + + - + input: + bytes: [ 0x1f, 0x30, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvt z31.h, z0.b" + + - + input: + bytes: [ 0xff, 0x33, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvt z31.h, z31.b" + + - + input: + bytes: [ 0x00, 0x34, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvt z0.h, z0.b" + + - + input: + bytes: [ 0xe0, 0x37, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvt z0.h, z31.b" + + - + input: + bytes: [ 0x1f, 0x34, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvt z31.h, z0.b" + + - + input: + bytes: [ 0xff, 0x37, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvt z31.h, z31.b" + + - + input: + bytes: [ 0x00, 0x38, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvt z0.h, z0.b" + + - + input: + bytes: [ 0xe0, 0x3b, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvt z0.h, z31.b" + + - + input: + bytes: [ 0x1f, 0x38, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvt z31.h, z0.b" + + - + input: + bytes: [ 0xff, 0x3b, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvt z31.h, z31.b" + + - + input: + bytes: [ 0x00, 0x3c, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvt z0.h, z0.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvt z0.h, z31.b" + + - + input: + bytes: [ 0x1f, 0x3c, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvt z31.h, z0.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvt z31.h, z31.b" + + - + input: + bytes: [ 0x00, 0x30, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvtlt z0.h, z0.b" + + - + input: + bytes: [ 0xe0, 0x33, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvtlt z0.h, z31.b" + + - + input: + bytes: [ 0x1f, 0x30, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvtlt z31.h, z0.b" + + - + input: + bytes: [ 0xff, 0x33, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f1cvtlt z31.h, z31.b" + + - + input: + bytes: [ 0x00, 0x34, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvtlt z0.h, z0.b" + + - + input: + bytes: [ 0xe0, 0x37, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvtlt z0.h, z31.b" + + - + input: + bytes: [ 0x1f, 0x34, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvtlt z31.h, z0.b" + + - + input: + bytes: [ 0xff, 0x37, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "f2cvtlt z31.h, z31.b" + + - + input: + bytes: [ 0x00, 0x38, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvtlt z0.h, z0.b" + + - + input: + bytes: [ 0xe0, 0x3b, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvtlt z0.h, z31.b" + + - + input: + bytes: [ 0x1f, 0x38, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvtlt z31.h, z0.b" + + - + input: + bytes: [ 0xff, 0x3b, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf1cvtlt z31.h, z31.b" + + - + input: + bytes: [ 0x00, 0x3c, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvtlt z0.h, z0.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvtlt z0.h, z31.b" + + - + input: + bytes: [ 0x1f, 0x3c, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvtlt z31.h, z0.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x09, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bf2cvtlt z31.h, z31.b" diff --git a/tests/MC/AArch64/FP8_SVE2/fcvtn.s.yaml b/tests/MC/AArch64/FP8_SVE2/fcvtn.s.yaml new file mode 100644 index 0000000000..c3bacb5f4a --- /dev/null +++ b/tests/MC/AArch64/FP8_SVE2/fcvtn.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x30, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtn z0.b, { z0.h, z1.h }" + + - + input: + bytes: [ 0xc0, 0x33, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtn z0.b, { z30.h, z31.h }" + + - + input: + bytes: [ 0x1f, 0x30, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtn z31.b, { z0.h, z1.h }" + + - + input: + bytes: [ 0xdf, 0x33, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtn z31.b, { z30.h, z31.h }" + + - + input: + bytes: [ 0x00, 0x34, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtnb z0.b, { z0.s, z1.s }" + + - + input: + bytes: [ 0xc0, 0x37, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtnb z0.b, { z30.s, z31.s }" + + - + input: + bytes: [ 0x1f, 0x34, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtnb z31.b, { z0.s, z1.s }" + + - + input: + bytes: [ 0xdf, 0x37, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtnb z31.b, { z30.s, z31.s }" + + - + input: + bytes: [ 0x00, 0x38, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bfcvtn z0.b, { z0.h, z1.h }" + + - + input: + bytes: [ 0xc0, 0x3b, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bfcvtn z0.b, { z30.h, z31.h }" + + - + input: + bytes: [ 0x1f, 0x38, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bfcvtn z31.b, { z0.h, z1.h }" + + - + input: + bytes: [ 0xdf, 0x3b, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "bfcvtn z31.b, { z30.h, z31.h }" + + - + input: + bytes: [ 0x00, 0x3c, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtnt z0.b, { z0.s, z1.s }" + + - + input: + bytes: [ 0xc0, 0x3f, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtnt z0.b, { z30.s, z31.s }" + + - + input: + bytes: [ 0x1f, 0x3c, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtnt z31.b, { z0.s, z1.s }" + + - + input: + bytes: [ 0xdf, 0x3f, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtnt z31.b, { z30.s, z31.s }" + + - + input: + bytes: [ 0x00, 0x30, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtn z0.b, { z0.h, z1.h }" + + - + input: + bytes: [ 0xc0, 0x33, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtn z0.b, { z30.h, z31.h }" + + - + input: + bytes: [ 0x1f, 0x30, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtn z31.b, { z0.h, z1.h }" + + - + input: + bytes: [ 0xdf, 0x33, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtn z31.b, { z30.h, z31.h }" + + - + input: + bytes: [ 0x00, 0x34, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtnb z0.b, { z0.s, z1.s }" + + - + input: + bytes: [ 0xc0, 0x37, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtnb z0.b, { z30.s, z31.s }" + + - + input: + bytes: [ 0x1f, 0x34, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtnb z31.b, { z0.s, z1.s }" + + - + input: + bytes: [ 0xdf, 0x37, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtnb z31.b, { z30.s, z31.s }" + + - + input: + bytes: [ 0x00, 0x38, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bfcvtn z0.b, { z0.h, z1.h }" + + - + input: + bytes: [ 0xc0, 0x3b, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bfcvtn z0.b, { z30.h, z31.h }" + + - + input: + bytes: [ 0x1f, 0x38, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bfcvtn z31.b, { z0.h, z1.h }" + + - + input: + bytes: [ 0xdf, 0x3b, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "bfcvtn z31.b, { z30.h, z31.h }" + + - + input: + bytes: [ 0x00, 0x3c, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtnt z0.b, { z0.s, z1.s }" + + - + input: + bytes: [ 0xc0, 0x3f, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtnt z0.b, { z30.s, z31.s }" + + - + input: + bytes: [ 0x1f, 0x3c, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtnt z31.b, { z0.s, z1.s }" + + - + input: + bytes: [ 0xdf, 0x3f, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ] + expected: + insns: + - + asm_text: "fcvtnt z31.b, { z30.s, z31.s }" diff --git a/tests/MC/AArch64/FP8_SVE2/fdot.s.yaml b/tests/MC/AArch64/FP8_SVE2/fdot.s.yaml new file mode 100644 index 0000000000..1eefeab3ef --- /dev/null +++ b/tests/MC/AArch64/FP8_SVE2/fdot.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x44, 0x20, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ] + expected: + insns: + - + asm_text: "fdot z0.h, z0.b, z0.b[0]" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x4d, 0x28, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ] + expected: + insns: + - + asm_text: "fdot z23.h, z13.b, z0.b[3]" + + - + input: + bytes: [ 0xff, 0x4f, 0x3f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ] + expected: + insns: + - + asm_text: "fdot z31.h, z31.b, z7.b[7]" + + - + input: + bytes: [ 0x00, 0x84, 0x20, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ] + expected: + insns: + - + asm_text: "fdot z0.h, z0.b, z0.b" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x85, 0x28, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ] + expected: + insns: + - + asm_text: "fdot z23.h, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0x87, 0x3f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ] + expected: + insns: + - + asm_text: "fdot z31.h, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0x44, 0x60, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ] + expected: + insns: + - + asm_text: "fdot z0.s, z0.b, z0.b[0]" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x45, 0x68, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ] + expected: + insns: + - + asm_text: "fdot z23.s, z13.b, z0.b[1]" + + - + input: + bytes: [ 0xff, 0x47, 0x7f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ] + expected: + insns: + - + asm_text: "fdot z31.s, z31.b, z7.b[3]" + + - + input: + bytes: [ 0x00, 0x84, 0x60, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ] + expected: + insns: + - + asm_text: "fdot z0.s, z0.b, z0.b" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x85, 0x68, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ] + expected: + insns: + - + asm_text: "fdot z23.s, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0x87, 0x7f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ] + expected: + insns: + - + asm_text: "fdot z31.s, z31.b, z31.b" diff --git a/tests/MC/AArch64/FP8_SVE2/fmlal.s.yaml b/tests/MC/AArch64/FP8_SVE2/fmlal.s.yaml new file mode 100644 index 0000000000..dd9dadc10f --- /dev/null +++ b/tests/MC/AArch64/FP8_SVE2/fmlal.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x50, 0x20, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalb z0.h, z0.b, z0.b[0]" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x5d, 0x28, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalb z23.h, z13.b, z0.b[7]" + + - + input: + bytes: [ 0xff, 0x5f, 0x3f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalb z31.h, z31.b, z7.b[15]" + + - + input: + bytes: [ 0x00, 0x88, 0xa0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalb z0.h, z0.b, z0.b" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x89, 0xa8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalb z23.h, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0x8b, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalb z31.h, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0x50, 0xa0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalt z0.h, z0.b, z0.b[0]" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x5d, 0xa8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalt z23.h, z13.b, z0.b[7]" + + - + input: + bytes: [ 0xff, 0x5f, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalt z31.h, z31.b, z7.b[15]" + + - + input: + bytes: [ 0x00, 0x98, 0xa0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalt z0.h, z0.b, z0.b" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x99, 0xa8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalt z23.h, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0x9b, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalt z31.h, z31.b, z31.b" diff --git a/tests/MC/AArch64/FP8_SVE2/fmlall.s.yaml b/tests/MC/AArch64/FP8_SVE2/fmlall.s.yaml new file mode 100644 index 0000000000..1df1a42277 --- /dev/null +++ b/tests/MC/AArch64/FP8_SVE2/fmlall.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0x20, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlallbb z0.s, z0.b, z0.b[0]" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0xcd, 0x28, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlallbb z23.s, z13.b, z0.b[7]" + + - + input: + bytes: [ 0xff, 0xcf, 0x3f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlallbb z31.s, z31.b, z7.b[15]" + + - + input: + bytes: [ 0x00, 0x88, 0x20, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlallbb z0.s, z0.b, z0.b" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x89, 0x28, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlallbb z23.s, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0x8b, 0x3f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlallbb z31.s, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0xc0, 0x60, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlallbt z0.s, z0.b, z0.b[0]" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0xcd, 0x68, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlallbt z23.s, z13.b, z0.b[7]" + + - + input: + bytes: [ 0xff, 0xcf, 0x7f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlallbt z31.s, z31.b, z7.b[15]" + + - + input: + bytes: [ 0x00, 0x98, 0x20, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlallbt z0.s, z0.b, z0.b" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x99, 0x28, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlallbt z23.s, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0x9b, 0x3f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlallbt z31.s, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0xc0, 0xa0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalltb z0.s, z0.b, z0.b[0]" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0xcd, 0xa8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalltb z23.s, z13.b, z0.b[7]" + + - + input: + bytes: [ 0xff, 0xcf, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalltb z31.s, z31.b, z7.b[15]" + + - + input: + bytes: [ 0x00, 0xa8, 0x20, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalltb z0.s, z0.b, z0.b" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0xa9, 0x28, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalltb z23.s, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0xab, 0x3f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalltb z31.s, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0xc0, 0xe0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalltt z0.s, z0.b, z0.b[0]" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0xcd, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalltt z23.s, z13.b, z0.b[7]" + + - + input: + bytes: [ 0xff, 0xcf, 0xff, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalltt z31.s, z31.b, z7.b[15]" + + - + input: + bytes: [ 0x00, 0xb8, 0x20, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalltt z0.s, z0.b, z0.b" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0xb9, 0x28, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalltt z23.s, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0xbb, 0x3f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ] + expected: + insns: + - + asm_text: "fmlalltt z31.s, z31.b, z31.b" diff --git a/tests/MC/AArch64/FP8_SVE2/luti2.s.yaml b/tests/MC/AArch64/FP8_SVE2/luti2.s.yaml new file mode 100644 index 0000000000..69f78b8eb6 --- /dev/null +++ b/tests/MC/AArch64/FP8_SVE2/luti2.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xb0, 0x20, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ] + expected: + insns: + - + asm_text: "luti2 z0.b, { z0.b }, z0[0]" + + - + input: + bytes: [ 0x55, 0xb1, 0x75, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ] + expected: + insns: + - + asm_text: "luti2 z21.b, { z10.b }, z21[1]" + + - + input: + bytes: [ 0xff, 0xb3, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ] + expected: + insns: + - + asm_text: "luti2 z31.b, { z31.b }, z31[3]" + + - + input: + bytes: [ 0x00, 0xa8, 0x20, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ] + expected: + insns: + - + asm_text: "luti2 z0.h, { z0.h }, z0[0]" + + - + input: + bytes: [ 0x55, 0xb9, 0x75, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ] + expected: + insns: + - + asm_text: "luti2 z21.h, { z10.h }, z21[3]" + + - + input: + bytes: [ 0xff, 0xbb, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ] + expected: + insns: + - + asm_text: "luti2 z31.h, { z31.h }, z31[7]" diff --git a/tests/MC/AArch64/FP8_SVE2/luti4.s.yaml b/tests/MC/AArch64/FP8_SVE2/luti4.s.yaml new file mode 100644 index 0000000000..c7fba91963 --- /dev/null +++ b/tests/MC/AArch64/FP8_SVE2/luti4.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa4, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ] + expected: + insns: + - + asm_text: "luti4 z0.b, { z0.b }, z0[0]" + + - + input: + bytes: [ 0xff, 0xa7, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ] + expected: + insns: + - + asm_text: "luti4 z31.b, { z31.b }, z31[1]" + + - + input: + bytes: [ 0x00, 0xbc, 0x20, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ] + expected: + insns: + - + asm_text: "luti4 z0.h, { z0.h }, z0[0]" + + - + input: + bytes: [ 0x55, 0xbd, 0x75, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ] + expected: + insns: + - + asm_text: "luti4 z21.h, { z10.h }, z21[1]" + + - + input: + bytes: [ 0xff, 0xbf, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ] + expected: + insns: + - + asm_text: "luti4 z31.h, { z31.h }, z31[3]" + + - + input: + bytes: [ 0x00, 0xb4, 0x20, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ] + expected: + insns: + - + asm_text: "luti4 z0.h, { z0.h, z1.h }, z0[0]" + + - + input: + bytes: [ 0x55, 0xb5, 0x75, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ] + expected: + insns: + - + asm_text: "luti4 z21.h, { z10.h, z11.h }, z21[1]" + + - + input: + bytes: [ 0xff, 0xb7, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ] + expected: + insns: + - + asm_text: "luti4 z31.h, { z31.h, z0.h }, z31[3]" diff --git a/tests/MC/AArch64/SME/addha-u32.s.yaml b/tests/MC/AArch64/SME/addha-u32.s.yaml new file mode 100644 index 0000000000..38bb8db8b6 --- /dev/null +++ b/tests/MC/AArch64/SME/addha-u32.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x90, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addha za0.s, p0/m, p0/m, z0.s" + + - + input: + bytes: [ 0x41, 0x55, 0x90, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addha za1.s, p5/m, p2/m, z10.s" + + - + input: + bytes: [ 0xa3, 0xed, 0x90, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addha za3.s, p3/m, p7/m, z13.s" + + - + input: + bytes: [ 0xe3, 0xff, 0x90, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addha za3.s, p7/m, p7/m, z31.s" + + - + input: + bytes: [ 0x21, 0x0e, 0x90, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addha za1.s, p3/m, p0/m, z17.s" + + - + input: + bytes: [ 0x21, 0x84, 0x90, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addha za1.s, p1/m, p4/m, z1.s" + + - + input: + bytes: [ 0x60, 0x56, 0x90, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addha za0.s, p5/m, p2/m, z19.s" + + - + input: + bytes: [ 0x80, 0x19, 0x90, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addha za0.s, p6/m, p0/m, z12.s" + + - + input: + bytes: [ 0x21, 0xc8, 0x90, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addha za1.s, p2/m, p6/m, z1.s" + + - + input: + bytes: [ 0xc1, 0x0a, 0x90, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addha za1.s, p2/m, p0/m, z22.s" + + - + input: + bytes: [ 0x22, 0xf5, 0x90, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addha za2.s, p5/m, p7/m, z9.s" + + - + input: + bytes: [ 0x83, 0xa9, 0x90, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addha za3.s, p2/m, p5/m, z12.s" diff --git a/tests/MC/AArch64/SME/addha-u64.s.yaml b/tests/MC/AArch64/SME/addha-u64.s.yaml new file mode 100644 index 0000000000..f90e1332b2 --- /dev/null +++ b/tests/MC/AArch64/SME/addha-u64.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xd0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addha za0.d, p0/m, p0/m, z0.d" + + - + input: + bytes: [ 0x45, 0x55, 0xd0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addha za5.d, p5/m, p2/m, z10.d" + + - + input: + bytes: [ 0xa7, 0xed, 0xd0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addha za7.d, p3/m, p7/m, z13.d" + + - + input: + bytes: [ 0xe7, 0xff, 0xd0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addha za7.d, p7/m, p7/m, z31.d" + + - + input: + bytes: [ 0x25, 0x0e, 0xd0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addha za5.d, p3/m, p0/m, z17.d" + + - + input: + bytes: [ 0x21, 0x84, 0xd0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addha za1.d, p1/m, p4/m, z1.d" + + - + input: + bytes: [ 0x60, 0x56, 0xd0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addha za0.d, p5/m, p2/m, z19.d" + + - + input: + bytes: [ 0x80, 0x19, 0xd0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addha za0.d, p6/m, p0/m, z12.d" + + - + input: + bytes: [ 0x21, 0xc8, 0xd0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addha za1.d, p2/m, p6/m, z1.d" + + - + input: + bytes: [ 0xc5, 0x0a, 0xd0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addha za5.d, p2/m, p0/m, z22.d" + + - + input: + bytes: [ 0x22, 0xf5, 0xd0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addha za2.d, p5/m, p7/m, z9.d" + + - + input: + bytes: [ 0x87, 0xa9, 0xd0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addha za7.d, p2/m, p5/m, z12.d" diff --git a/tests/MC/AArch64/SME/addspl.s.yaml b/tests/MC/AArch64/SME/addspl.s.yaml new file mode 100644 index 0000000000..802b028498 --- /dev/null +++ b/tests/MC/AArch64/SME/addspl.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x15, 0x58, 0x75, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addspl x21, x21, #0" + + - + input: + bytes: [ 0xf7, 0x5f, 0x68, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addspl x23, x8, #-1" + + - + input: + bytes: [ 0xff, 0x5b, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addspl sp, sp, #31" + + - + input: + bytes: [ 0x00, 0x5c, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addspl x0, x0, #-32" diff --git a/tests/MC/AArch64/SME/addsvl.s.yaml b/tests/MC/AArch64/SME/addsvl.s.yaml new file mode 100644 index 0000000000..89b8462fe3 --- /dev/null +++ b/tests/MC/AArch64/SME/addsvl.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x15, 0x58, 0x35, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addsvl x21, x21, #0" + + - + input: + bytes: [ 0xf7, 0x5f, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addsvl x23, x8, #-1" + + - + input: + bytes: [ 0xff, 0x5b, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addsvl sp, sp, #31" + + - + input: + bytes: [ 0x00, 0x5c, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addsvl x0, x0, #-32" diff --git a/tests/MC/AArch64/SME/addva-u32.s.yaml b/tests/MC/AArch64/SME/addva-u32.s.yaml new file mode 100644 index 0000000000..6de6174808 --- /dev/null +++ b/tests/MC/AArch64/SME/addva-u32.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x91, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addva za0.s, p0/m, p0/m, z0.s" + + - + input: + bytes: [ 0x41, 0x55, 0x91, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addva za1.s, p5/m, p2/m, z10.s" + + - + input: + bytes: [ 0xa3, 0xed, 0x91, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addva za3.s, p3/m, p7/m, z13.s" + + - + input: + bytes: [ 0xe3, 0xff, 0x91, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addva za3.s, p7/m, p7/m, z31.s" + + - + input: + bytes: [ 0x21, 0x0e, 0x91, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addva za1.s, p3/m, p0/m, z17.s" + + - + input: + bytes: [ 0x21, 0x84, 0x91, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addva za1.s, p1/m, p4/m, z1.s" + + - + input: + bytes: [ 0x60, 0x56, 0x91, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addva za0.s, p5/m, p2/m, z19.s" + + - + input: + bytes: [ 0x80, 0x19, 0x91, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addva za0.s, p6/m, p0/m, z12.s" + + - + input: + bytes: [ 0x21, 0xc8, 0x91, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addva za1.s, p2/m, p6/m, z1.s" + + - + input: + bytes: [ 0xc1, 0x0a, 0x91, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addva za1.s, p2/m, p0/m, z22.s" + + - + input: + bytes: [ 0x22, 0xf5, 0x91, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addva za2.s, p5/m, p7/m, z9.s" + + - + input: + bytes: [ 0x83, 0xa9, 0x91, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addva za3.s, p2/m, p5/m, z12.s" diff --git a/tests/MC/AArch64/SME/addva-u64.s.yaml b/tests/MC/AArch64/SME/addva-u64.s.yaml new file mode 100644 index 0000000000..25db5ab3ee --- /dev/null +++ b/tests/MC/AArch64/SME/addva-u64.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xd1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addva za0.d, p0/m, p0/m, z0.d" + + - + input: + bytes: [ 0x45, 0x55, 0xd1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addva za5.d, p5/m, p2/m, z10.d" + + - + input: + bytes: [ 0xa7, 0xed, 0xd1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addva za7.d, p3/m, p7/m, z13.d" + + - + input: + bytes: [ 0xe7, 0xff, 0xd1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addva za7.d, p7/m, p7/m, z31.d" + + - + input: + bytes: [ 0x25, 0x0e, 0xd1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addva za5.d, p3/m, p0/m, z17.d" + + - + input: + bytes: [ 0x21, 0x84, 0xd1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addva za1.d, p1/m, p4/m, z1.d" + + - + input: + bytes: [ 0x60, 0x56, 0xd1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addva za0.d, p5/m, p2/m, z19.d" + + - + input: + bytes: [ 0x80, 0x19, 0xd1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addva za0.d, p6/m, p0/m, z12.d" + + - + input: + bytes: [ 0x21, 0xc8, 0xd1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addva za1.d, p2/m, p6/m, z1.d" + + - + input: + bytes: [ 0xc5, 0x0a, 0xd1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addva za5.d, p2/m, p0/m, z22.d" + + - + input: + bytes: [ 0x22, 0xf5, 0xd1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addva za2.d, p5/m, p7/m, z9.d" + + - + input: + bytes: [ 0x87, 0xa9, 0xd1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "addva za7.d, p2/m, p5/m, z12.d" diff --git a/tests/MC/AArch64/SME/bfmopa.s.yaml b/tests/MC/AArch64/SME/bfmopa.s.yaml new file mode 100644 index 0000000000..c608593db0 --- /dev/null +++ b/tests/MC/AArch64/SME/bfmopa.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x80, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmopa za0.s, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x41, 0x55, 0x95, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmopa za1.s, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xa3, 0xed, 0x88, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmopa za3.s, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xe3, 0xff, 0x9f, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmopa za3.s, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x21, 0x0e, 0x90, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmopa za1.s, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x21, 0x84, 0x9e, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmopa za1.s, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x60, 0x56, 0x94, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmopa za0.s, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x80, 0x19, 0x82, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmopa za0.s, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x21, 0xc8, 0x9a, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmopa za1.s, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xc1, 0x0a, 0x9e, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmopa za1.s, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x22, 0xf5, 0x81, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmopa za2.s, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x83, 0xa9, 0x8b, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmopa za3.s, p2/m, p5/m, z12.h, z11.h" diff --git a/tests/MC/AArch64/SME/bfmops.s.yaml b/tests/MC/AArch64/SME/bfmops.s.yaml new file mode 100644 index 0000000000..972e298fd1 --- /dev/null +++ b/tests/MC/AArch64/SME/bfmops.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x00, 0x80, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmops za0.s, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x51, 0x55, 0x95, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmops za1.s, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xb3, 0xed, 0x88, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmops za3.s, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xf3, 0xff, 0x9f, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmops za3.s, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x31, 0x0e, 0x90, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmops za1.s, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x31, 0x84, 0x9e, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmops za1.s, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x70, 0x56, 0x94, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmops za0.s, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x90, 0x19, 0x82, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmops za0.s, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x31, 0xc8, 0x9a, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmops za1.s, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xd1, 0x0a, 0x9e, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmops za1.s, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x32, 0xf5, 0x81, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmops za2.s, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x93, 0xa9, 0x8b, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bfmops za3.s, p2/m, p5/m, z12.h, z11.h" diff --git a/tests/MC/AArch64/SME/fa64-implies-sve2.s.yaml b/tests/MC/AArch64/SME/fa64-implies-sve2.s.yaml new file mode 100644 index 0000000000..90bdc92eea --- /dev/null +++ b/tests/MC/AArch64/SME/fa64-implies-sve2.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x9f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "sme-fa64" ] + expected: + insns: + - + asm_text: "ldnt1sh { z0.s }, p0/z, [z1.s]" diff --git a/tests/MC/AArch64/SME/feature.s.yaml b/tests/MC/AArch64/SME/feature.s.yaml new file mode 100644 index 0000000000..b57e031451 --- /dev/null +++ b/tests/MC/AArch64/SME/feature.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x2c, 0x22, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "sme" ] + expected: + insns: + - + asm_text: "tbx z0.b, z1.b, z2.b" + + - + input: + bytes: [ 0x20, 0x80, 0x62, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "sme" ] + expected: + insns: + - + asm_text: "bfdot z0.s, z1.h, z2.h" + + - + input: + bytes: [ 0x20, 0x2c, 0x22, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "sme-f64f64" ] + expected: + insns: + - + asm_text: "tbx z0.b, z1.b, z2.b" + + - + input: + bytes: [ 0x20, 0x80, 0x62, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "sme-f64f64" ] + expected: + insns: + - + asm_text: "bfdot z0.s, z1.h, z2.h" + + - + input: + bytes: [ 0x20, 0x2c, 0x22, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "sme-i16i64" ] + expected: + insns: + - + asm_text: "tbx z0.b, z1.b, z2.b" + + - + input: + bytes: [ 0x20, 0x80, 0x62, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "sme-i16i64" ] + expected: + insns: + - + asm_text: "bfdot z0.s, z1.h, z2.h" diff --git a/tests/MC/AArch64/SME/fmopa-fp64.s.yaml b/tests/MC/AArch64/SME/fmopa-fp64.s.yaml new file mode 100644 index 0000000000..534d986793 --- /dev/null +++ b/tests/MC/AArch64/SME/fmopa-fp64.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmopa za0.d, p0/m, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0x45, 0x55, 0xd5, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmopa za5.d, p5/m, p2/m, z10.d, z21.d" + + - + input: + bytes: [ 0xa7, 0xed, 0xc8, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmopa za7.d, p3/m, p7/m, z13.d, z8.d" + + - + input: + bytes: [ 0xe7, 0xff, 0xdf, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmopa za7.d, p7/m, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0x25, 0x0e, 0xd0, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmopa za5.d, p3/m, p0/m, z17.d, z16.d" + + - + input: + bytes: [ 0x21, 0x84, 0xde, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmopa za1.d, p1/m, p4/m, z1.d, z30.d" + + - + input: + bytes: [ 0x60, 0x56, 0xd4, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmopa za0.d, p5/m, p2/m, z19.d, z20.d" + + - + input: + bytes: [ 0x80, 0x19, 0xc2, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmopa za0.d, p6/m, p0/m, z12.d, z2.d" + + - + input: + bytes: [ 0x21, 0xc8, 0xda, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmopa za1.d, p2/m, p6/m, z1.d, z26.d" + + - + input: + bytes: [ 0xc5, 0x0a, 0xde, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmopa za5.d, p2/m, p0/m, z22.d, z30.d" + + - + input: + bytes: [ 0x22, 0xf5, 0xc1, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmopa za2.d, p5/m, p7/m, z9.d, z1.d" + + - + input: + bytes: [ 0x87, 0xa9, 0xcb, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmopa za7.d, p2/m, p5/m, z12.d, z11.d" diff --git a/tests/MC/AArch64/SME/fmopa.s.yaml b/tests/MC/AArch64/SME/fmopa.s.yaml new file mode 100644 index 0000000000..f12e64073d --- /dev/null +++ b/tests/MC/AArch64/SME/fmopa.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xa0, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za0.s, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x41, 0x55, 0xb5, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za1.s, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xa3, 0xed, 0xa8, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za3.s, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xe3, 0xff, 0xbf, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za3.s, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x21, 0x0e, 0xb0, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za1.s, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x21, 0x84, 0xbe, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za1.s, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x60, 0x56, 0xb4, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za0.s, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x80, 0x19, 0xa2, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za0.s, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x21, 0xc8, 0xba, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za1.s, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xc1, 0x0a, 0xbe, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za1.s, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x22, 0xf5, 0xa1, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za2.s, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x83, 0xa9, 0xab, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za3.s, p2/m, p5/m, z12.h, z11.h" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za0.s, p0/m, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x41, 0x55, 0x95, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za1.s, p5/m, p2/m, z10.s, z21.s" + + - + input: + bytes: [ 0xa3, 0xed, 0x88, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za3.s, p3/m, p7/m, z13.s, z8.s" + + - + input: + bytes: [ 0xe3, 0xff, 0x9f, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za3.s, p7/m, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0x21, 0x0e, 0x90, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za1.s, p3/m, p0/m, z17.s, z16.s" + + - + input: + bytes: [ 0x21, 0x84, 0x9e, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za1.s, p1/m, p4/m, z1.s, z30.s" + + - + input: + bytes: [ 0x60, 0x56, 0x94, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za0.s, p5/m, p2/m, z19.s, z20.s" + + - + input: + bytes: [ 0x80, 0x19, 0x82, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za0.s, p6/m, p0/m, z12.s, z2.s" + + - + input: + bytes: [ 0x21, 0xc8, 0x9a, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za1.s, p2/m, p6/m, z1.s, z26.s" + + - + input: + bytes: [ 0xc1, 0x0a, 0x9e, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za1.s, p2/m, p0/m, z22.s, z30.s" + + - + input: + bytes: [ 0x22, 0xf5, 0x81, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za2.s, p5/m, p7/m, z9.s, z1.s" + + - + input: + bytes: [ 0x83, 0xa9, 0x8b, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmopa za3.s, p2/m, p5/m, z12.s, z11.s" diff --git a/tests/MC/AArch64/SME/fmops-fp64.s.yaml b/tests/MC/AArch64/SME/fmops-fp64.s.yaml new file mode 100644 index 0000000000..2d8918aa1e --- /dev/null +++ b/tests/MC/AArch64/SME/fmops-fp64.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x00, 0xc0, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmops za0.d, p0/m, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0x55, 0x55, 0xd5, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmops za5.d, p5/m, p2/m, z10.d, z21.d" + + - + input: + bytes: [ 0xb7, 0xed, 0xc8, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmops za7.d, p3/m, p7/m, z13.d, z8.d" + + - + input: + bytes: [ 0xf7, 0xff, 0xdf, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmops za7.d, p7/m, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0x35, 0x0e, 0xd0, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmops za5.d, p3/m, p0/m, z17.d, z16.d" + + - + input: + bytes: [ 0x31, 0x84, 0xde, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmops za1.d, p1/m, p4/m, z1.d, z30.d" + + - + input: + bytes: [ 0x70, 0x56, 0xd4, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmops za0.d, p5/m, p2/m, z19.d, z20.d" + + - + input: + bytes: [ 0x90, 0x19, 0xc2, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmops za0.d, p6/m, p0/m, z12.d, z2.d" + + - + input: + bytes: [ 0x31, 0xc8, 0xda, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmops za1.d, p2/m, p6/m, z1.d, z26.d" + + - + input: + bytes: [ 0xd5, 0x0a, 0xde, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmops za5.d, p2/m, p0/m, z22.d, z30.d" + + - + input: + bytes: [ 0x32, 0xf5, 0xc1, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmops za2.d, p5/m, p7/m, z9.d, z1.d" + + - + input: + bytes: [ 0x97, 0xa9, 0xcb, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ] + expected: + insns: + - + asm_text: "fmops za7.d, p2/m, p5/m, z12.d, z11.d" diff --git a/tests/MC/AArch64/SME/fmops.s.yaml b/tests/MC/AArch64/SME/fmops.s.yaml new file mode 100644 index 0000000000..e5f3eef751 --- /dev/null +++ b/tests/MC/AArch64/SME/fmops.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x00, 0xa0, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za0.s, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x51, 0x55, 0xb5, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za1.s, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xb3, 0xed, 0xa8, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za3.s, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xf3, 0xff, 0xbf, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za3.s, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x31, 0x0e, 0xb0, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za1.s, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x31, 0x84, 0xbe, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za1.s, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x70, 0x56, 0xb4, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za0.s, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x90, 0x19, 0xa2, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za0.s, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x31, 0xc8, 0xba, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za1.s, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xd1, 0x0a, 0xbe, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za1.s, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x32, 0xf5, 0xa1, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za2.s, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x93, 0xa9, 0xab, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za3.s, p2/m, p5/m, z12.h, z11.h" + + - + input: + bytes: [ 0x10, 0x00, 0x80, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za0.s, p0/m, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x51, 0x55, 0x95, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za1.s, p5/m, p2/m, z10.s, z21.s" + + - + input: + bytes: [ 0xb3, 0xed, 0x88, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za3.s, p3/m, p7/m, z13.s, z8.s" + + - + input: + bytes: [ 0xf3, 0xff, 0x9f, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za3.s, p7/m, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0x31, 0x0e, 0x90, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za1.s, p3/m, p0/m, z17.s, z16.s" + + - + input: + bytes: [ 0x31, 0x84, 0x9e, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za1.s, p1/m, p4/m, z1.s, z30.s" + + - + input: + bytes: [ 0x70, 0x56, 0x94, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za0.s, p5/m, p2/m, z19.s, z20.s" + + - + input: + bytes: [ 0x90, 0x19, 0x82, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za0.s, p6/m, p0/m, z12.s, z2.s" + + - + input: + bytes: [ 0x31, 0xc8, 0x9a, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za1.s, p2/m, p6/m, z1.s, z26.s" + + - + input: + bytes: [ 0xd1, 0x0a, 0x9e, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za1.s, p2/m, p0/m, z22.s, z30.s" + + - + input: + bytes: [ 0x32, 0xf5, 0x81, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za2.s, p5/m, p7/m, z9.s, z1.s" + + - + input: + bytes: [ 0x93, 0xa9, 0x8b, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmops za3.s, p2/m, p5/m, z12.s, z11.s" diff --git a/tests/MC/AArch64/SME/ld1b.s.yaml b/tests/MC/AArch64/SME/ld1b.s.yaml new file mode 100644 index 0000000000..bfd7653f70 --- /dev/null +++ b/tests/MC/AArch64/SME/ld1b.s.yaml @@ -0,0 +1,500 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w12, 0]}, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x45, 0x55, 0x15, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w14, 5]}, p5/z, [x10, x21]" + + - + input: + bytes: [ 0xa7, 0x6d, 0x08, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w15, 7]}, p3/z, [x13, x8]" + + - + input: + bytes: [ 0xef, 0x7f, 0x1f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w15, 15]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0x10, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w12, 5]}, p3/z, [x17, x16]" + + - + input: + bytes: [ 0x21, 0x04, 0x1e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w12, 1]}, p1/z, [x1, x30]" + + - + input: + bytes: [ 0x68, 0x56, 0x14, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w14, 8]}, p5/z, [x19, x20]" + + - + input: + bytes: [ 0x80, 0x19, 0x02, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w12, 0]}, p6/z, [x12, x2]" + + - + input: + bytes: [ 0x21, 0x48, 0x1a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w14, 1]}, p2/z, [x1, x26]" + + - + input: + bytes: [ 0xcd, 0x0a, 0x1e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w12, 13]}, p2/z, [x22, x30]" + + - + input: + bytes: [ 0x22, 0x75, 0x01, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w15, 2]}, p5/z, [x9, x1]" + + - + input: + bytes: [ 0x87, 0x29, 0x0b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w13, 7]}, p2/z, [x12, x11]" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w12, 0]}, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x45, 0x55, 0x15, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w14, 5]}, p5/z, [x10, x21]" + + - + input: + bytes: [ 0xa7, 0x6d, 0x08, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w15, 7]}, p3/z, [x13, x8]" + + - + input: + bytes: [ 0xef, 0x7f, 0x1f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w15, 15]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0x10, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w12, 5]}, p3/z, [x17, x16]" + + - + input: + bytes: [ 0x21, 0x04, 0x1e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w12, 1]}, p1/z, [x1, x30]" + + - + input: + bytes: [ 0x68, 0x56, 0x14, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w14, 8]}, p5/z, [x19, x20]" + + - + input: + bytes: [ 0x80, 0x19, 0x02, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w12, 0]}, p6/z, [x12, x2]" + + - + input: + bytes: [ 0x21, 0x48, 0x1a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w14, 1]}, p2/z, [x1, x26]" + + - + input: + bytes: [ 0xcd, 0x0a, 0x1e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w12, 13]}, p2/z, [x22, x30]" + + - + input: + bytes: [ 0x22, 0x75, 0x01, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w15, 2]}, p5/z, [x9, x1]" + + - + input: + bytes: [ 0x87, 0x29, 0x0b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w13, 7]}, p2/z, [x12, x11]" + + - + input: + bytes: [ 0x00, 0x80, 0x00, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w12, 0]}, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x45, 0xd5, 0x15, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w14, 5]}, p5/z, [x10, x21]" + + - + input: + bytes: [ 0xa7, 0xed, 0x08, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w15, 7]}, p3/z, [x13, x8]" + + - + input: + bytes: [ 0xef, 0xff, 0x1f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w15, 15]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0x10, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w12, 5]}, p3/z, [x17, x16]" + + - + input: + bytes: [ 0x21, 0x84, 0x1e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w12, 1]}, p1/z, [x1, x30]" + + - + input: + bytes: [ 0x68, 0xd6, 0x14, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w14, 8]}, p5/z, [x19, x20]" + + - + input: + bytes: [ 0x80, 0x99, 0x02, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w12, 0]}, p6/z, [x12, x2]" + + - + input: + bytes: [ 0x21, 0xc8, 0x1a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w14, 1]}, p2/z, [x1, x26]" + + - + input: + bytes: [ 0xcd, 0x8a, 0x1e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w12, 13]}, p2/z, [x22, x30]" + + - + input: + bytes: [ 0x22, 0xf5, 0x01, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w15, 2]}, p5/z, [x9, x1]" + + - + input: + bytes: [ 0x87, 0xa9, 0x0b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w13, 7]}, p2/z, [x12, x11]" + + - + input: + bytes: [ 0x00, 0x80, 0x00, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w12, 0]}, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x45, 0xd5, 0x15, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w14, 5]}, p5/z, [x10, x21]" + + - + input: + bytes: [ 0xa7, 0xed, 0x08, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w15, 7]}, p3/z, [x13, x8]" + + - + input: + bytes: [ 0xef, 0xff, 0x1f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w15, 15]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0x10, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w12, 5]}, p3/z, [x17, x16]" + + - + input: + bytes: [ 0x21, 0x84, 0x1e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w12, 1]}, p1/z, [x1, x30]" + + - + input: + bytes: [ 0x68, 0xd6, 0x14, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w14, 8]}, p5/z, [x19, x20]" + + - + input: + bytes: [ 0x80, 0x99, 0x02, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w12, 0]}, p6/z, [x12, x2]" + + - + input: + bytes: [ 0x21, 0xc8, 0x1a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w14, 1]}, p2/z, [x1, x26]" + + - + input: + bytes: [ 0xcd, 0x8a, 0x1e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w12, 13]}, p2/z, [x22, x30]" + + - + input: + bytes: [ 0x22, 0xf5, 0x01, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w15, 2]}, p5/z, [x9, x1]" + + - + input: + bytes: [ 0x87, 0xa9, 0x0b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w13, 7]}, p2/z, [x12, x11]" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0h.b[w12, 0]}, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x00, 0x80, 0x00, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b {za0v.b[w12, 0]}, p0/z, [x0, x0]" diff --git a/tests/MC/AArch64/SME/ld1d.s.yaml b/tests/MC/AArch64/SME/ld1d.s.yaml new file mode 100644 index 0000000000..1f50c896b5 --- /dev/null +++ b/tests/MC/AArch64/SME/ld1d.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za0h.d[w12, 0]}, p0/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x45, 0x55, 0xd5, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za2h.d[w14, 1]}, p5/z, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xa7, 0x6d, 0xc8, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za3h.d[w15, 1]}, p3/z, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xef, 0x7f, 0xdf, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za7h.d[w15, 1]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0xd0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za2h.d[w12, 1]}, p3/z, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x21, 0x04, 0xde, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za0h.d[w12, 1]}, p1/z, [x1, x30, lsl #3]" + + - + input: + bytes: [ 0x68, 0x56, 0xd4, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za4h.d[w14, 0]}, p5/z, [x19, x20, lsl #3]" + + - + input: + bytes: [ 0x80, 0x19, 0xc2, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za0h.d[w12, 0]}, p6/z, [x12, x2, lsl #3]" + + - + input: + bytes: [ 0x21, 0x48, 0xda, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za0h.d[w14, 1]}, p2/z, [x1, x26, lsl #3]" + + - + input: + bytes: [ 0xcd, 0x0a, 0xde, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za6h.d[w12, 1]}, p2/z, [x22, x30, lsl #3]" + + - + input: + bytes: [ 0x22, 0x75, 0xc1, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za1h.d[w15, 0]}, p5/z, [x9, x1, lsl #3]" + + - + input: + bytes: [ 0x87, 0x29, 0xcb, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za3h.d[w13, 1]}, p2/z, [x12, x11, lsl #3]" + + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za0h.d[w12, 0]}, p0/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x45, 0x55, 0xd5, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za2h.d[w14, 1]}, p5/z, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xa7, 0x6d, 0xc8, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za3h.d[w15, 1]}, p3/z, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xef, 0x7f, 0xdf, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za7h.d[w15, 1]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0xd0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za2h.d[w12, 1]}, p3/z, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x21, 0x04, 0xde, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za0h.d[w12, 1]}, p1/z, [x1, x30, lsl #3]" + + - + input: + bytes: [ 0x68, 0x56, 0xd4, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za4h.d[w14, 0]}, p5/z, [x19, x20, lsl #3]" + + - + input: + bytes: [ 0x80, 0x19, 0xc2, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za0h.d[w12, 0]}, p6/z, [x12, x2, lsl #3]" + + - + input: + bytes: [ 0x21, 0x48, 0xda, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za0h.d[w14, 1]}, p2/z, [x1, x26, lsl #3]" + + - + input: + bytes: [ 0xcd, 0x0a, 0xde, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za6h.d[w12, 1]}, p2/z, [x22, x30, lsl #3]" + + - + input: + bytes: [ 0x22, 0x75, 0xc1, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za1h.d[w15, 0]}, p5/z, [x9, x1, lsl #3]" + + - + input: + bytes: [ 0x87, 0x29, 0xcb, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za3h.d[w13, 1]}, p2/z, [x12, x11, lsl #3]" + + - + input: + bytes: [ 0x00, 0x80, 0xc0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za0v.d[w12, 0]}, p0/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x45, 0xd5, 0xd5, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za2v.d[w14, 1]}, p5/z, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xa7, 0xed, 0xc8, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za3v.d[w15, 1]}, p3/z, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xef, 0xff, 0xdf, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za7v.d[w15, 1]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0xd0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za2v.d[w12, 1]}, p3/z, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x21, 0x84, 0xde, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za0v.d[w12, 1]}, p1/z, [x1, x30, lsl #3]" + + - + input: + bytes: [ 0x68, 0xd6, 0xd4, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za4v.d[w14, 0]}, p5/z, [x19, x20, lsl #3]" + + - + input: + bytes: [ 0x80, 0x99, 0xc2, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za0v.d[w12, 0]}, p6/z, [x12, x2, lsl #3]" + + - + input: + bytes: [ 0x21, 0xc8, 0xda, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za0v.d[w14, 1]}, p2/z, [x1, x26, lsl #3]" + + - + input: + bytes: [ 0xcd, 0x8a, 0xde, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za6v.d[w12, 1]}, p2/z, [x22, x30, lsl #3]" + + - + input: + bytes: [ 0x22, 0xf5, 0xc1, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za1v.d[w15, 0]}, p5/z, [x9, x1, lsl #3]" + + - + input: + bytes: [ 0x87, 0xa9, 0xcb, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za3v.d[w13, 1]}, p2/z, [x12, x11, lsl #3]" + + - + input: + bytes: [ 0x00, 0x80, 0xc0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za0v.d[w12, 0]}, p0/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x45, 0xd5, 0xd5, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za2v.d[w14, 1]}, p5/z, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xa7, 0xed, 0xc8, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za3v.d[w15, 1]}, p3/z, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xef, 0xff, 0xdf, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za7v.d[w15, 1]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0xd0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za2v.d[w12, 1]}, p3/z, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x21, 0x84, 0xde, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za0v.d[w12, 1]}, p1/z, [x1, x30, lsl #3]" + + - + input: + bytes: [ 0x68, 0xd6, 0xd4, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za4v.d[w14, 0]}, p5/z, [x19, x20, lsl #3]" + + - + input: + bytes: [ 0x80, 0x99, 0xc2, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za0v.d[w12, 0]}, p6/z, [x12, x2, lsl #3]" + + - + input: + bytes: [ 0x21, 0xc8, 0xda, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za0v.d[w14, 1]}, p2/z, [x1, x26, lsl #3]" + + - + input: + bytes: [ 0xcd, 0x8a, 0xde, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za6v.d[w12, 1]}, p2/z, [x22, x30, lsl #3]" + + - + input: + bytes: [ 0x22, 0xf5, 0xc1, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za1v.d[w15, 0]}, p5/z, [x9, x1, lsl #3]" + + - + input: + bytes: [ 0x87, 0xa9, 0xcb, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d {za3v.d[w13, 1]}, p2/z, [x12, x11, lsl #3]" diff --git a/tests/MC/AArch64/SME/ld1h.s.yaml b/tests/MC/AArch64/SME/ld1h.s.yaml new file mode 100644 index 0000000000..5b24eeed8d --- /dev/null +++ b/tests/MC/AArch64/SME/ld1h.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x40, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0h.h[w12, 0]}, p0/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x45, 0x55, 0x55, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0h.h[w14, 5]}, p5/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xa7, 0x6d, 0x48, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0h.h[w15, 7]}, p3/z, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xef, 0x7f, 0x5f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za1h.h[w15, 7]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0x50, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0h.h[w12, 5]}, p3/z, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x21, 0x04, 0x5e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0h.h[w12, 1]}, p1/z, [x1, x30, lsl #1]" + + - + input: + bytes: [ 0x68, 0x56, 0x54, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za1h.h[w14, 0]}, p5/z, [x19, x20, lsl #1]" + + - + input: + bytes: [ 0x80, 0x19, 0x42, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0h.h[w12, 0]}, p6/z, [x12, x2, lsl #1]" + + - + input: + bytes: [ 0x21, 0x48, 0x5a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0h.h[w14, 1]}, p2/z, [x1, x26, lsl #1]" + + - + input: + bytes: [ 0xcd, 0x0a, 0x5e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za1h.h[w12, 5]}, p2/z, [x22, x30, lsl #1]" + + - + input: + bytes: [ 0x22, 0x75, 0x41, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0h.h[w15, 2]}, p5/z, [x9, x1, lsl #1]" + + - + input: + bytes: [ 0x87, 0x29, 0x4b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0h.h[w13, 7]}, p2/z, [x12, x11, lsl #1]" + + - + input: + bytes: [ 0x00, 0x00, 0x40, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0h.h[w12, 0]}, p0/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x45, 0x55, 0x55, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0h.h[w14, 5]}, p5/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xa7, 0x6d, 0x48, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0h.h[w15, 7]}, p3/z, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xef, 0x7f, 0x5f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za1h.h[w15, 7]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0x50, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0h.h[w12, 5]}, p3/z, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x21, 0x04, 0x5e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0h.h[w12, 1]}, p1/z, [x1, x30, lsl #1]" + + - + input: + bytes: [ 0x68, 0x56, 0x54, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za1h.h[w14, 0]}, p5/z, [x19, x20, lsl #1]" + + - + input: + bytes: [ 0x80, 0x19, 0x42, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0h.h[w12, 0]}, p6/z, [x12, x2, lsl #1]" + + - + input: + bytes: [ 0x21, 0x48, 0x5a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0h.h[w14, 1]}, p2/z, [x1, x26, lsl #1]" + + - + input: + bytes: [ 0xcd, 0x0a, 0x5e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za1h.h[w12, 5]}, p2/z, [x22, x30, lsl #1]" + + - + input: + bytes: [ 0x22, 0x75, 0x41, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0h.h[w15, 2]}, p5/z, [x9, x1, lsl #1]" + + - + input: + bytes: [ 0x87, 0x29, 0x4b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0h.h[w13, 7]}, p2/z, [x12, x11, lsl #1]" + + - + input: + bytes: [ 0x00, 0x80, 0x40, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0v.h[w12, 0]}, p0/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x45, 0xd5, 0x55, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0v.h[w14, 5]}, p5/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xa7, 0xed, 0x48, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0v.h[w15, 7]}, p3/z, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xef, 0xff, 0x5f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za1v.h[w15, 7]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0x50, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0v.h[w12, 5]}, p3/z, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x21, 0x84, 0x5e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0v.h[w12, 1]}, p1/z, [x1, x30, lsl #1]" + + - + input: + bytes: [ 0x68, 0xd6, 0x54, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za1v.h[w14, 0]}, p5/z, [x19, x20, lsl #1]" + + - + input: + bytes: [ 0x80, 0x99, 0x42, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0v.h[w12, 0]}, p6/z, [x12, x2, lsl #1]" + + - + input: + bytes: [ 0x21, 0xc8, 0x5a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0v.h[w14, 1]}, p2/z, [x1, x26, lsl #1]" + + - + input: + bytes: [ 0xcd, 0x8a, 0x5e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za1v.h[w12, 5]}, p2/z, [x22, x30, lsl #1]" + + - + input: + bytes: [ 0x22, 0xf5, 0x41, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0v.h[w15, 2]}, p5/z, [x9, x1, lsl #1]" + + - + input: + bytes: [ 0x87, 0xa9, 0x4b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0v.h[w13, 7]}, p2/z, [x12, x11, lsl #1]" + + - + input: + bytes: [ 0x00, 0x80, 0x40, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0v.h[w12, 0]}, p0/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x45, 0xd5, 0x55, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0v.h[w14, 5]}, p5/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xa7, 0xed, 0x48, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0v.h[w15, 7]}, p3/z, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xef, 0xff, 0x5f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za1v.h[w15, 7]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0x50, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0v.h[w12, 5]}, p3/z, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x21, 0x84, 0x5e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0v.h[w12, 1]}, p1/z, [x1, x30, lsl #1]" + + - + input: + bytes: [ 0x68, 0xd6, 0x54, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za1v.h[w14, 0]}, p5/z, [x19, x20, lsl #1]" + + - + input: + bytes: [ 0x80, 0x99, 0x42, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0v.h[w12, 0]}, p6/z, [x12, x2, lsl #1]" + + - + input: + bytes: [ 0x21, 0xc8, 0x5a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0v.h[w14, 1]}, p2/z, [x1, x26, lsl #1]" + + - + input: + bytes: [ 0xcd, 0x8a, 0x5e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za1v.h[w12, 5]}, p2/z, [x22, x30, lsl #1]" + + - + input: + bytes: [ 0x22, 0xf5, 0x41, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0v.h[w15, 2]}, p5/z, [x9, x1, lsl #1]" + + - + input: + bytes: [ 0x87, 0xa9, 0x4b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h {za0v.h[w13, 7]}, p2/z, [x12, x11, lsl #1]" diff --git a/tests/MC/AArch64/SME/ld1q.s.yaml b/tests/MC/AArch64/SME/ld1q.s.yaml new file mode 100644 index 0000000000..addbe42796 --- /dev/null +++ b/tests/MC/AArch64/SME/ld1q.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za0h.q[w12, 0]}, p0/z, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x45, 0x55, 0xd5, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za5h.q[w14, 0]}, p5/z, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xa7, 0x6d, 0xc8, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za7h.q[w15, 0]}, p3/z, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0xef, 0x7f, 0xdf, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za15h.q[w15, 0]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0xd0, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za5h.q[w12, 0]}, p3/z, [x17, x16, lsl #4]" + + - + input: + bytes: [ 0x21, 0x04, 0xde, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za1h.q[w12, 0]}, p1/z, [x1, x30, lsl #4]" + + - + input: + bytes: [ 0x68, 0x56, 0xd4, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za8h.q[w14, 0]}, p5/z, [x19, x20, lsl #4]" + + - + input: + bytes: [ 0x80, 0x19, 0xc2, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za0h.q[w12, 0]}, p6/z, [x12, x2, lsl #4]" + + - + input: + bytes: [ 0x21, 0x48, 0xda, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za1h.q[w14, 0]}, p2/z, [x1, x26, lsl #4]" + + - + input: + bytes: [ 0xcd, 0x0a, 0xde, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za13h.q[w12, 0]}, p2/z, [x22, x30, lsl #4]" + + - + input: + bytes: [ 0x22, 0x75, 0xc1, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za2h.q[w15, 0]}, p5/z, [x9, x1, lsl #4]" + + - + input: + bytes: [ 0x87, 0x29, 0xcb, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za7h.q[w13, 0]}, p2/z, [x12, x11, lsl #4]" + + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za0h.q[w12, 0]}, p0/z, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x45, 0x55, 0xd5, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za5h.q[w14, 0]}, p5/z, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xa7, 0x6d, 0xc8, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za7h.q[w15, 0]}, p3/z, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0xef, 0x7f, 0xdf, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za15h.q[w15, 0]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0xd0, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za5h.q[w12, 0]}, p3/z, [x17, x16, lsl #4]" + + - + input: + bytes: [ 0x21, 0x04, 0xde, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za1h.q[w12, 0]}, p1/z, [x1, x30, lsl #4]" + + - + input: + bytes: [ 0x68, 0x56, 0xd4, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za8h.q[w14, 0]}, p5/z, [x19, x20, lsl #4]" + + - + input: + bytes: [ 0x80, 0x19, 0xc2, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za0h.q[w12, 0]}, p6/z, [x12, x2, lsl #4]" + + - + input: + bytes: [ 0x21, 0x48, 0xda, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za1h.q[w14, 0]}, p2/z, [x1, x26, lsl #4]" + + - + input: + bytes: [ 0xcd, 0x0a, 0xde, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za13h.q[w12, 0]}, p2/z, [x22, x30, lsl #4]" + + - + input: + bytes: [ 0x22, 0x75, 0xc1, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za2h.q[w15, 0]}, p5/z, [x9, x1, lsl #4]" + + - + input: + bytes: [ 0x87, 0x29, 0xcb, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za7h.q[w13, 0]}, p2/z, [x12, x11, lsl #4]" + + - + input: + bytes: [ 0x00, 0x80, 0xc0, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za0v.q[w12, 0]}, p0/z, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x45, 0xd5, 0xd5, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za5v.q[w14, 0]}, p5/z, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xa7, 0xed, 0xc8, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za7v.q[w15, 0]}, p3/z, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0xef, 0xff, 0xdf, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za15v.q[w15, 0]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0xd0, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za5v.q[w12, 0]}, p3/z, [x17, x16, lsl #4]" + + - + input: + bytes: [ 0x21, 0x84, 0xde, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za1v.q[w12, 0]}, p1/z, [x1, x30, lsl #4]" + + - + input: + bytes: [ 0x68, 0xd6, 0xd4, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za8v.q[w14, 0]}, p5/z, [x19, x20, lsl #4]" + + - + input: + bytes: [ 0x80, 0x99, 0xc2, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za0v.q[w12, 0]}, p6/z, [x12, x2, lsl #4]" + + - + input: + bytes: [ 0x21, 0xc8, 0xda, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za1v.q[w14, 0]}, p2/z, [x1, x26, lsl #4]" + + - + input: + bytes: [ 0xcd, 0x8a, 0xde, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za13v.q[w12, 0]}, p2/z, [x22, x30, lsl #4]" + + - + input: + bytes: [ 0x22, 0xf5, 0xc1, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za2v.q[w15, 0]}, p5/z, [x9, x1, lsl #4]" + + - + input: + bytes: [ 0x87, 0xa9, 0xcb, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za7v.q[w13, 0]}, p2/z, [x12, x11, lsl #4]" + + - + input: + bytes: [ 0x00, 0x80, 0xc0, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za0v.q[w12, 0]}, p0/z, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x45, 0xd5, 0xd5, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za5v.q[w14, 0]}, p5/z, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xa7, 0xed, 0xc8, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za7v.q[w15, 0]}, p3/z, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0xef, 0xff, 0xdf, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za15v.q[w15, 0]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0xd0, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za5v.q[w12, 0]}, p3/z, [x17, x16, lsl #4]" + + - + input: + bytes: [ 0x21, 0x84, 0xde, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za1v.q[w12, 0]}, p1/z, [x1, x30, lsl #4]" + + - + input: + bytes: [ 0x68, 0xd6, 0xd4, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za8v.q[w14, 0]}, p5/z, [x19, x20, lsl #4]" + + - + input: + bytes: [ 0x80, 0x99, 0xc2, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za0v.q[w12, 0]}, p6/z, [x12, x2, lsl #4]" + + - + input: + bytes: [ 0x21, 0xc8, 0xda, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za1v.q[w14, 0]}, p2/z, [x1, x26, lsl #4]" + + - + input: + bytes: [ 0xcd, 0x8a, 0xde, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za13v.q[w12, 0]}, p2/z, [x22, x30, lsl #4]" + + - + input: + bytes: [ 0x22, 0xf5, 0xc1, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za2v.q[w15, 0]}, p5/z, [x9, x1, lsl #4]" + + - + input: + bytes: [ 0x87, 0xa9, 0xcb, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1q {za7v.q[w13, 0]}, p2/z, [x12, x11, lsl #4]" diff --git a/tests/MC/AArch64/SME/ld1w.s.yaml b/tests/MC/AArch64/SME/ld1w.s.yaml new file mode 100644 index 0000000000..02aaa0755e --- /dev/null +++ b/tests/MC/AArch64/SME/ld1w.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x80, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0h.s[w12, 0]}, p0/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x45, 0x55, 0x95, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za1h.s[w14, 1]}, p5/z, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xa7, 0x6d, 0x88, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za1h.s[w15, 3]}, p3/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xef, 0x7f, 0x9f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za3h.s[w15, 3]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0x90, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za1h.s[w12, 1]}, p3/z, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x21, 0x04, 0x9e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0h.s[w12, 1]}, p1/z, [x1, x30, lsl #2]" + + - + input: + bytes: [ 0x68, 0x56, 0x94, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za2h.s[w14, 0]}, p5/z, [x19, x20, lsl #2]" + + - + input: + bytes: [ 0x80, 0x19, 0x82, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0h.s[w12, 0]}, p6/z, [x12, x2, lsl #2]" + + - + input: + bytes: [ 0x21, 0x48, 0x9a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0h.s[w14, 1]}, p2/z, [x1, x26, lsl #2]" + + - + input: + bytes: [ 0xcd, 0x0a, 0x9e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za3h.s[w12, 1]}, p2/z, [x22, x30, lsl #2]" + + - + input: + bytes: [ 0x22, 0x75, 0x81, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0h.s[w15, 2]}, p5/z, [x9, x1, lsl #2]" + + - + input: + bytes: [ 0x87, 0x29, 0x8b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za1h.s[w13, 3]}, p2/z, [x12, x11, lsl #2]" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0h.s[w12, 0]}, p0/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x45, 0x55, 0x95, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za1h.s[w14, 1]}, p5/z, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xa7, 0x6d, 0x88, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za1h.s[w15, 3]}, p3/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xef, 0x7f, 0x9f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za3h.s[w15, 3]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0x90, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za1h.s[w12, 1]}, p3/z, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x21, 0x04, 0x9e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0h.s[w12, 1]}, p1/z, [x1, x30, lsl #2]" + + - + input: + bytes: [ 0x68, 0x56, 0x94, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za2h.s[w14, 0]}, p5/z, [x19, x20, lsl #2]" + + - + input: + bytes: [ 0x80, 0x19, 0x82, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0h.s[w12, 0]}, p6/z, [x12, x2, lsl #2]" + + - + input: + bytes: [ 0x21, 0x48, 0x9a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0h.s[w14, 1]}, p2/z, [x1, x26, lsl #2]" + + - + input: + bytes: [ 0xcd, 0x0a, 0x9e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za3h.s[w12, 1]}, p2/z, [x22, x30, lsl #2]" + + - + input: + bytes: [ 0x22, 0x75, 0x81, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0h.s[w15, 2]}, p5/z, [x9, x1, lsl #2]" + + - + input: + bytes: [ 0x87, 0x29, 0x8b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za1h.s[w13, 3]}, p2/z, [x12, x11, lsl #2]" + + - + input: + bytes: [ 0x00, 0x80, 0x80, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0v.s[w12, 0]}, p0/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x45, 0xd5, 0x95, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za1v.s[w14, 1]}, p5/z, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xa7, 0xed, 0x88, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za1v.s[w15, 3]}, p3/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xef, 0xff, 0x9f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za3v.s[w15, 3]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0x90, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za1v.s[w12, 1]}, p3/z, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x21, 0x84, 0x9e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0v.s[w12, 1]}, p1/z, [x1, x30, lsl #2]" + + - + input: + bytes: [ 0x68, 0xd6, 0x94, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za2v.s[w14, 0]}, p5/z, [x19, x20, lsl #2]" + + - + input: + bytes: [ 0x80, 0x99, 0x82, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0v.s[w12, 0]}, p6/z, [x12, x2, lsl #2]" + + - + input: + bytes: [ 0x21, 0xc8, 0x9a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0v.s[w14, 1]}, p2/z, [x1, x26, lsl #2]" + + - + input: + bytes: [ 0xcd, 0x8a, 0x9e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za3v.s[w12, 1]}, p2/z, [x22, x30, lsl #2]" + + - + input: + bytes: [ 0x22, 0xf5, 0x81, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0v.s[w15, 2]}, p5/z, [x9, x1, lsl #2]" + + - + input: + bytes: [ 0x87, 0xa9, 0x8b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za1v.s[w13, 3]}, p2/z, [x12, x11, lsl #2]" + + - + input: + bytes: [ 0x00, 0x80, 0x80, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0v.s[w12, 0]}, p0/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x45, 0xd5, 0x95, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za1v.s[w14, 1]}, p5/z, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xa7, 0xed, 0x88, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za1v.s[w15, 3]}, p3/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xef, 0xff, 0x9f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za3v.s[w15, 3]}, p7/z, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0x90, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za1v.s[w12, 1]}, p3/z, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x21, 0x84, 0x9e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0v.s[w12, 1]}, p1/z, [x1, x30, lsl #2]" + + - + input: + bytes: [ 0x68, 0xd6, 0x94, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za2v.s[w14, 0]}, p5/z, [x19, x20, lsl #2]" + + - + input: + bytes: [ 0x80, 0x99, 0x82, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0v.s[w12, 0]}, p6/z, [x12, x2, lsl #2]" + + - + input: + bytes: [ 0x21, 0xc8, 0x9a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0v.s[w14, 1]}, p2/z, [x1, x26, lsl #2]" + + - + input: + bytes: [ 0xcd, 0x8a, 0x9e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za3v.s[w12, 1]}, p2/z, [x22, x30, lsl #2]" + + - + input: + bytes: [ 0x22, 0xf5, 0x81, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za0v.s[w15, 2]}, p5/z, [x9, x1, lsl #2]" + + - + input: + bytes: [ 0x87, 0xa9, 0x8b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w {za1v.s[w13, 3]}, p2/z, [x12, x11, lsl #2]" diff --git a/tests/MC/AArch64/SME/ldr.s.yaml b/tests/MC/AArch64/SME/ldr.s.yaml new file mode 100644 index 0000000000..1122e7ccf7 --- /dev/null +++ b/tests/MC/AArch64/SME/ldr.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr za[w12, 0], [x0]" + + - + input: + bytes: [ 0x45, 0x41, 0x00, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr za[w14, 5], [x10, #5, mul vl]" + + - + input: + bytes: [ 0xa7, 0x61, 0x00, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr za[w15, 7], [x13, #7, mul vl]" + + - + input: + bytes: [ 0xef, 0x63, 0x00, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr za[w15, 15], [sp, #15, mul vl]" + + - + input: + bytes: [ 0x25, 0x02, 0x00, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr za[w12, 5], [x17, #5, mul vl]" + + - + input: + bytes: [ 0x21, 0x00, 0x00, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr za[w12, 1], [x1, #1, mul vl]" + + - + input: + bytes: [ 0x68, 0x42, 0x00, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr za[w14, 8], [x19, #8, mul vl]" + + - + input: + bytes: [ 0x80, 0x01, 0x00, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr za[w12, 0], [x12]" + + - + input: + bytes: [ 0x21, 0x40, 0x00, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr za[w14, 1], [x1, #1, mul vl]" + + - + input: + bytes: [ 0xcd, 0x02, 0x00, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr za[w12, 13], [x22, #13, mul vl]" + + - + input: + bytes: [ 0x22, 0x61, 0x00, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr za[w15, 2], [x9, #2, mul vl]" + + - + input: + bytes: [ 0x87, 0x21, 0x00, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr za[w13, 7], [x12, #7, mul vl]" diff --git a/tests/MC/AArch64/SME/mova.s.yaml b/tests/MC/AArch64/SME/mova.s.yaml new file mode 100644 index 0000000000..628c83c2c3 --- /dev/null +++ b/tests/MC/AArch64/SME/mova.s.yaml @@ -0,0 +1,4800 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, p0/m, za0h.b[w12, 0]" + + - + input: + bytes: [ 0x55, 0x55, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.b, p5/m, za0h.b[w14, 10]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.b, p3/m, za0h.b[w15, 13]" + + - + input: + bytes: [ 0xff, 0x7d, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.b, p7/m, za0h.b[w15, 15]" + + - + input: + bytes: [ 0x25, 0x0c, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.b, p3/m, za0h.b[w12, 1]" + + - + input: + bytes: [ 0x21, 0x04, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.b, p1/m, za0h.b[w12, 1]" + + - + input: + bytes: [ 0x78, 0x54, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.b, p5/m, za0h.b[w14, 3]" + + - + input: + bytes: [ 0x80, 0x19, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, p6/m, za0h.b[w12, 12]" + + - + input: + bytes: [ 0x31, 0x48, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.b, p2/m, za0h.b[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x08, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.b, p2/m, za0h.b[w12, 6]" + + - + input: + bytes: [ 0x22, 0x75, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.b, p5/m, za0h.b[w15, 9]" + + - + input: + bytes: [ 0x87, 0x29, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.b, p2/m, za0h.b[w13, 12]" + + - + input: + bytes: [ 0x00, 0x00, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, p0/m, za0h.b[w12, 0]" + + - + input: + bytes: [ 0x55, 0x55, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.b, p5/m, za0h.b[w14, 10]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.b, p3/m, za0h.b[w15, 13]" + + - + input: + bytes: [ 0xff, 0x7d, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.b, p7/m, za0h.b[w15, 15]" + + - + input: + bytes: [ 0x25, 0x0c, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.b, p3/m, za0h.b[w12, 1]" + + - + input: + bytes: [ 0x21, 0x04, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.b, p1/m, za0h.b[w12, 1]" + + - + input: + bytes: [ 0x78, 0x54, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.b, p5/m, za0h.b[w14, 3]" + + - + input: + bytes: [ 0x80, 0x19, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, p6/m, za0h.b[w12, 12]" + + - + input: + bytes: [ 0x31, 0x48, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.b, p2/m, za0h.b[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x08, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.b, p2/m, za0h.b[w12, 6]" + + - + input: + bytes: [ 0x22, 0x75, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.b, p5/m, za0h.b[w15, 9]" + + - + input: + bytes: [ 0x87, 0x29, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.b, p2/m, za0h.b[w13, 12]" + + - + input: + bytes: [ 0x00, 0x80, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, p0/m, za0v.b[w12, 0]" + + - + input: + bytes: [ 0x55, 0xd5, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.b, p5/m, za0v.b[w14, 10]" + + - + input: + bytes: [ 0xb7, 0xed, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.b, p3/m, za0v.b[w15, 13]" + + - + input: + bytes: [ 0xff, 0xfd, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.b, p7/m, za0v.b[w15, 15]" + + - + input: + bytes: [ 0x25, 0x8c, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.b, p3/m, za0v.b[w12, 1]" + + - + input: + bytes: [ 0x21, 0x84, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.b, p1/m, za0v.b[w12, 1]" + + - + input: + bytes: [ 0x78, 0xd4, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.b, p5/m, za0v.b[w14, 3]" + + - + input: + bytes: [ 0x80, 0x99, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, p6/m, za0v.b[w12, 12]" + + - + input: + bytes: [ 0x31, 0xc8, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.b, p2/m, za0v.b[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x88, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.b, p2/m, za0v.b[w12, 6]" + + - + input: + bytes: [ 0x22, 0xf5, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.b, p5/m, za0v.b[w15, 9]" + + - + input: + bytes: [ 0x87, 0xa9, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.b, p2/m, za0v.b[w13, 12]" + + - + input: + bytes: [ 0x00, 0x80, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, p0/m, za0v.b[w12, 0]" + + - + input: + bytes: [ 0x55, 0xd5, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.b, p5/m, za0v.b[w14, 10]" + + - + input: + bytes: [ 0xb7, 0xed, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.b, p3/m, za0v.b[w15, 13]" + + - + input: + bytes: [ 0xff, 0xfd, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.b, p7/m, za0v.b[w15, 15]" + + - + input: + bytes: [ 0x25, 0x8c, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.b, p3/m, za0v.b[w12, 1]" + + - + input: + bytes: [ 0x21, 0x84, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.b, p1/m, za0v.b[w12, 1]" + + - + input: + bytes: [ 0x78, 0xd4, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.b, p5/m, za0v.b[w14, 3]" + + - + input: + bytes: [ 0x80, 0x99, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, p6/m, za0v.b[w12, 12]" + + - + input: + bytes: [ 0x31, 0xc8, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.b, p2/m, za0v.b[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x88, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.b, p2/m, za0v.b[w12, 6]" + + - + input: + bytes: [ 0x22, 0xf5, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.b, p5/m, za0v.b[w15, 9]" + + - + input: + bytes: [ 0x87, 0xa9, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.b, p2/m, za0v.b[w13, 12]" + + - + input: + bytes: [ 0x00, 0x00, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/m, za0h.h[w12, 0]" + + - + input: + bytes: [ 0x55, 0x55, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p5/m, za1h.h[w14, 2]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.h, p3/m, za1h.h[w15, 5]" + + - + input: + bytes: [ 0xff, 0x7d, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.h, p7/m, za1h.h[w15, 7]" + + - + input: + bytes: [ 0x25, 0x0c, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.h, p3/m, za0h.h[w12, 1]" + + - + input: + bytes: [ 0x21, 0x04, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.h, p1/m, za0h.h[w12, 1]" + + - + input: + bytes: [ 0x78, 0x54, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.h, p5/m, za0h.h[w14, 3]" + + - + input: + bytes: [ 0x80, 0x19, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, p6/m, za1h.h[w12, 4]" + + - + input: + bytes: [ 0x31, 0x48, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.h, p2/m, za0h.h[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x08, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.h, p2/m, za0h.h[w12, 6]" + + - + input: + bytes: [ 0x22, 0x75, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.h, p5/m, za1h.h[w15, 1]" + + - + input: + bytes: [ 0x87, 0x29, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.h, p2/m, za1h.h[w13, 4]" + + - + input: + bytes: [ 0x00, 0x00, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/m, za0h.h[w12, 0]" + + - + input: + bytes: [ 0x55, 0x55, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p5/m, za1h.h[w14, 2]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.h, p3/m, za1h.h[w15, 5]" + + - + input: + bytes: [ 0xff, 0x7d, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.h, p7/m, za1h.h[w15, 7]" + + - + input: + bytes: [ 0x25, 0x0c, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.h, p3/m, za0h.h[w12, 1]" + + - + input: + bytes: [ 0x21, 0x04, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.h, p1/m, za0h.h[w12, 1]" + + - + input: + bytes: [ 0x78, 0x54, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.h, p5/m, za0h.h[w14, 3]" + + - + input: + bytes: [ 0x80, 0x19, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, p6/m, za1h.h[w12, 4]" + + - + input: + bytes: [ 0x31, 0x48, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.h, p2/m, za0h.h[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x08, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.h, p2/m, za0h.h[w12, 6]" + + - + input: + bytes: [ 0x22, 0x75, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.h, p5/m, za1h.h[w15, 1]" + + - + input: + bytes: [ 0x87, 0x29, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.h, p2/m, za1h.h[w13, 4]" + + - + input: + bytes: [ 0x00, 0x80, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/m, za0v.h[w12, 0]" + + - + input: + bytes: [ 0x55, 0xd5, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p5/m, za1v.h[w14, 2]" + + - + input: + bytes: [ 0xb7, 0xed, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.h, p3/m, za1v.h[w15, 5]" + + - + input: + bytes: [ 0xff, 0xfd, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.h, p7/m, za1v.h[w15, 7]" + + - + input: + bytes: [ 0x25, 0x8c, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.h, p3/m, za0v.h[w12, 1]" + + - + input: + bytes: [ 0x21, 0x84, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.h, p1/m, za0v.h[w12, 1]" + + - + input: + bytes: [ 0x78, 0xd4, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.h, p5/m, za0v.h[w14, 3]" + + - + input: + bytes: [ 0x80, 0x99, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, p6/m, za1v.h[w12, 4]" + + - + input: + bytes: [ 0x31, 0xc8, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.h, p2/m, za0v.h[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x88, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.h, p2/m, za0v.h[w12, 6]" + + - + input: + bytes: [ 0x22, 0xf5, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.h, p5/m, za1v.h[w15, 1]" + + - + input: + bytes: [ 0x87, 0xa9, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.h, p2/m, za1v.h[w13, 4]" + + - + input: + bytes: [ 0x00, 0x80, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/m, za0v.h[w12, 0]" + + - + input: + bytes: [ 0x55, 0xd5, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p5/m, za1v.h[w14, 2]" + + - + input: + bytes: [ 0xb7, 0xed, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.h, p3/m, za1v.h[w15, 5]" + + - + input: + bytes: [ 0xff, 0xfd, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.h, p7/m, za1v.h[w15, 7]" + + - + input: + bytes: [ 0x25, 0x8c, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.h, p3/m, za0v.h[w12, 1]" + + - + input: + bytes: [ 0x21, 0x84, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.h, p1/m, za0v.h[w12, 1]" + + - + input: + bytes: [ 0x78, 0xd4, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.h, p5/m, za0v.h[w14, 3]" + + - + input: + bytes: [ 0x80, 0x99, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, p6/m, za1v.h[w12, 4]" + + - + input: + bytes: [ 0x31, 0xc8, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.h, p2/m, za0v.h[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x88, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.h, p2/m, za0v.h[w12, 6]" + + - + input: + bytes: [ 0x22, 0xf5, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.h, p5/m, za1v.h[w15, 1]" + + - + input: + bytes: [ 0x87, 0xa9, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.h, p2/m, za1v.h[w13, 4]" + + - + input: + bytes: [ 0x00, 0x00, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, p0/m, za0h.s[w12, 0]" + + - + input: + bytes: [ 0x55, 0x55, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p5/m, za2h.s[w14, 2]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.s, p3/m, za3h.s[w15, 1]" + + - + input: + bytes: [ 0xff, 0x7d, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.s, p7/m, za3h.s[w15, 3]" + + - + input: + bytes: [ 0x25, 0x0c, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.s, p3/m, za0h.s[w12, 1]" + + - + input: + bytes: [ 0x21, 0x04, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.s, p1/m, za0h.s[w12, 1]" + + - + input: + bytes: [ 0x78, 0x54, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.s, p5/m, za0h.s[w14, 3]" + + - + input: + bytes: [ 0x80, 0x19, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, p6/m, za3h.s[w12, 0]" + + - + input: + bytes: [ 0x31, 0x48, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.s, p2/m, za0h.s[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x08, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.s, p2/m, za1h.s[w12, 2]" + + - + input: + bytes: [ 0x22, 0x75, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.s, p5/m, za2h.s[w15, 1]" + + - + input: + bytes: [ 0x87, 0x29, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.s, p2/m, za3h.s[w13, 0]" + + - + input: + bytes: [ 0x00, 0x00, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, p0/m, za0h.s[w12, 0]" + + - + input: + bytes: [ 0x55, 0x55, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p5/m, za2h.s[w14, 2]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.s, p3/m, za3h.s[w15, 1]" + + - + input: + bytes: [ 0xff, 0x7d, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.s, p7/m, za3h.s[w15, 3]" + + - + input: + bytes: [ 0x25, 0x0c, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.s, p3/m, za0h.s[w12, 1]" + + - + input: + bytes: [ 0x21, 0x04, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.s, p1/m, za0h.s[w12, 1]" + + - + input: + bytes: [ 0x78, 0x54, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.s, p5/m, za0h.s[w14, 3]" + + - + input: + bytes: [ 0x80, 0x19, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, p6/m, za3h.s[w12, 0]" + + - + input: + bytes: [ 0x31, 0x48, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.s, p2/m, za0h.s[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x08, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.s, p2/m, za1h.s[w12, 2]" + + - + input: + bytes: [ 0x22, 0x75, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.s, p5/m, za2h.s[w15, 1]" + + - + input: + bytes: [ 0x87, 0x29, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.s, p2/m, za3h.s[w13, 0]" + + - + input: + bytes: [ 0x00, 0x80, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, p0/m, za0v.s[w12, 0]" + + - + input: + bytes: [ 0x55, 0xd5, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p5/m, za2v.s[w14, 2]" + + - + input: + bytes: [ 0xb7, 0xed, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.s, p3/m, za3v.s[w15, 1]" + + - + input: + bytes: [ 0xff, 0xfd, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.s, p7/m, za3v.s[w15, 3]" + + - + input: + bytes: [ 0x25, 0x8c, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.s, p3/m, za0v.s[w12, 1]" + + - + input: + bytes: [ 0x21, 0x84, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.s, p1/m, za0v.s[w12, 1]" + + - + input: + bytes: [ 0x78, 0xd4, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.s, p5/m, za0v.s[w14, 3]" + + - + input: + bytes: [ 0x80, 0x99, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, p6/m, za3v.s[w12, 0]" + + - + input: + bytes: [ 0x31, 0xc8, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.s, p2/m, za0v.s[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x88, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.s, p2/m, za1v.s[w12, 2]" + + - + input: + bytes: [ 0x22, 0xf5, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.s, p5/m, za2v.s[w15, 1]" + + - + input: + bytes: [ 0x87, 0xa9, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.s, p2/m, za3v.s[w13, 0]" + + - + input: + bytes: [ 0x00, 0x80, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, p0/m, za0v.s[w12, 0]" + + - + input: + bytes: [ 0x55, 0xd5, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p5/m, za2v.s[w14, 2]" + + - + input: + bytes: [ 0xb7, 0xed, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.s, p3/m, za3v.s[w15, 1]" + + - + input: + bytes: [ 0xff, 0xfd, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.s, p7/m, za3v.s[w15, 3]" + + - + input: + bytes: [ 0x25, 0x8c, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.s, p3/m, za0v.s[w12, 1]" + + - + input: + bytes: [ 0x21, 0x84, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.s, p1/m, za0v.s[w12, 1]" + + - + input: + bytes: [ 0x78, 0xd4, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.s, p5/m, za0v.s[w14, 3]" + + - + input: + bytes: [ 0x80, 0x99, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, p6/m, za3v.s[w12, 0]" + + - + input: + bytes: [ 0x31, 0xc8, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.s, p2/m, za0v.s[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x88, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.s, p2/m, za1v.s[w12, 2]" + + - + input: + bytes: [ 0x22, 0xf5, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.s, p5/m, za2v.s[w15, 1]" + + - + input: + bytes: [ 0x87, 0xa9, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.s, p2/m, za3v.s[w13, 0]" + + - + input: + bytes: [ 0x00, 0x00, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, p0/m, za0h.d[w12, 0]" + + - + input: + bytes: [ 0x55, 0x55, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p5/m, za5h.d[w14, 0]" + + - + input: + bytes: [ 0xb7, 0x6d, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.d, p3/m, za6h.d[w15, 1]" + + - + input: + bytes: [ 0xff, 0x7d, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, za7h.d[w15, 1]" + + - + input: + bytes: [ 0x25, 0x0c, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.d, p3/m, za0h.d[w12, 1]" + + - + input: + bytes: [ 0x21, 0x04, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.d, p1/m, za0h.d[w12, 1]" + + - + input: + bytes: [ 0x78, 0x54, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.d, p5/m, za1h.d[w14, 1]" + + - + input: + bytes: [ 0x80, 0x19, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, p6/m, za6h.d[w12, 0]" + + - + input: + bytes: [ 0x31, 0x48, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.d, p2/m, za0h.d[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x08, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.d, p2/m, za3h.d[w12, 0]" + + - + input: + bytes: [ 0x22, 0x75, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.d, p5/m, za4h.d[w15, 1]" + + - + input: + bytes: [ 0x87, 0x29, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.d, p2/m, za6h.d[w13, 0]" + + - + input: + bytes: [ 0x00, 0x00, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, p0/m, za0h.d[w12, 0]" + + - + input: + bytes: [ 0x55, 0x55, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p5/m, za5h.d[w14, 0]" + + - + input: + bytes: [ 0xb7, 0x6d, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.d, p3/m, za6h.d[w15, 1]" + + - + input: + bytes: [ 0xff, 0x7d, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, za7h.d[w15, 1]" + + - + input: + bytes: [ 0x25, 0x0c, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.d, p3/m, za0h.d[w12, 1]" + + - + input: + bytes: [ 0x21, 0x04, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.d, p1/m, za0h.d[w12, 1]" + + - + input: + bytes: [ 0x78, 0x54, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.d, p5/m, za1h.d[w14, 1]" + + - + input: + bytes: [ 0x80, 0x19, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, p6/m, za6h.d[w12, 0]" + + - + input: + bytes: [ 0x31, 0x48, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.d, p2/m, za0h.d[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x08, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.d, p2/m, za3h.d[w12, 0]" + + - + input: + bytes: [ 0x22, 0x75, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.d, p5/m, za4h.d[w15, 1]" + + - + input: + bytes: [ 0x87, 0x29, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.d, p2/m, za6h.d[w13, 0]" + + - + input: + bytes: [ 0x00, 0x80, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, p0/m, za0v.d[w12, 0]" + + - + input: + bytes: [ 0x55, 0xd5, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p5/m, za5v.d[w14, 0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.d, p3/m, za6v.d[w15, 1]" + + - + input: + bytes: [ 0xff, 0xfd, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, za7v.d[w15, 1]" + + - + input: + bytes: [ 0x25, 0x8c, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.d, p3/m, za0v.d[w12, 1]" + + - + input: + bytes: [ 0x21, 0x84, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.d, p1/m, za0v.d[w12, 1]" + + - + input: + bytes: [ 0x78, 0xd4, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.d, p5/m, za1v.d[w14, 1]" + + - + input: + bytes: [ 0x80, 0x99, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, p6/m, za6v.d[w12, 0]" + + - + input: + bytes: [ 0x31, 0xc8, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.d, p2/m, za0v.d[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x88, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.d, p2/m, za3v.d[w12, 0]" + + - + input: + bytes: [ 0x22, 0xf5, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.d, p5/m, za4v.d[w15, 1]" + + - + input: + bytes: [ 0x87, 0xa9, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.d, p2/m, za6v.d[w13, 0]" + + - + input: + bytes: [ 0x00, 0x80, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, p0/m, za0v.d[w12, 0]" + + - + input: + bytes: [ 0x55, 0xd5, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p5/m, za5v.d[w14, 0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.d, p3/m, za6v.d[w15, 1]" + + - + input: + bytes: [ 0xff, 0xfd, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, za7v.d[w15, 1]" + + - + input: + bytes: [ 0x25, 0x8c, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.d, p3/m, za0v.d[w12, 1]" + + - + input: + bytes: [ 0x21, 0x84, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.d, p1/m, za0v.d[w12, 1]" + + - + input: + bytes: [ 0x78, 0xd4, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.d, p5/m, za1v.d[w14, 1]" + + - + input: + bytes: [ 0x80, 0x99, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, p6/m, za6v.d[w12, 0]" + + - + input: + bytes: [ 0x31, 0xc8, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.d, p2/m, za0v.d[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x88, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.d, p2/m, za3v.d[w12, 0]" + + - + input: + bytes: [ 0x22, 0xf5, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.d, p5/m, za4v.d[w15, 1]" + + - + input: + bytes: [ 0x87, 0xa9, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.d, p2/m, za6v.d[w13, 0]" + + - + input: + bytes: [ 0x00, 0x00, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.q, p0/m, za0h.q[w12, 0]" + + - + input: + bytes: [ 0x55, 0x55, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.q, p5/m, za10h.q[w14, 0]" + + - + input: + bytes: [ 0xb7, 0x6d, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.q, p3/m, za13h.q[w15, 0]" + + - + input: + bytes: [ 0xff, 0x7d, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.q, p7/m, za15h.q[w15, 0]" + + - + input: + bytes: [ 0x25, 0x0c, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.q, p3/m, za1h.q[w12, 0]" + + - + input: + bytes: [ 0x21, 0x04, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.q, p1/m, za1h.q[w12, 0]" + + - + input: + bytes: [ 0x78, 0x54, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.q, p5/m, za3h.q[w14, 0]" + + - + input: + bytes: [ 0x80, 0x19, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.q, p6/m, za12h.q[w12, 0]" + + - + input: + bytes: [ 0x31, 0x48, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.q, p2/m, za1h.q[w14, 0]" + + - + input: + bytes: [ 0xdd, 0x08, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.q, p2/m, za6h.q[w12, 0]" + + - + input: + bytes: [ 0x22, 0x75, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.q, p5/m, za9h.q[w15, 0]" + + - + input: + bytes: [ 0x87, 0x29, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.q, p2/m, za12h.q[w13, 0]" + + - + input: + bytes: [ 0x00, 0x00, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.q, p0/m, za0h.q[w12, 0]" + + - + input: + bytes: [ 0x55, 0x55, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.q, p5/m, za10h.q[w14, 0]" + + - + input: + bytes: [ 0xb7, 0x6d, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.q, p3/m, za13h.q[w15, 0]" + + - + input: + bytes: [ 0xff, 0x7d, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.q, p7/m, za15h.q[w15, 0]" + + - + input: + bytes: [ 0x25, 0x0c, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.q, p3/m, za1h.q[w12, 0]" + + - + input: + bytes: [ 0x21, 0x04, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.q, p1/m, za1h.q[w12, 0]" + + - + input: + bytes: [ 0x78, 0x54, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.q, p5/m, za3h.q[w14, 0]" + + - + input: + bytes: [ 0x80, 0x19, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.q, p6/m, za12h.q[w12, 0]" + + - + input: + bytes: [ 0x31, 0x48, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.q, p2/m, za1h.q[w14, 0]" + + - + input: + bytes: [ 0xdd, 0x08, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.q, p2/m, za6h.q[w12, 0]" + + - + input: + bytes: [ 0x22, 0x75, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.q, p5/m, za9h.q[w15, 0]" + + - + input: + bytes: [ 0x87, 0x29, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.q, p2/m, za12h.q[w13, 0]" + + - + input: + bytes: [ 0x00, 0x80, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.q, p0/m, za0v.q[w12, 0]" + + - + input: + bytes: [ 0x55, 0xd5, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.q, p5/m, za10v.q[w14, 0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.q, p3/m, za13v.q[w15, 0]" + + - + input: + bytes: [ 0xff, 0xfd, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.q, p7/m, za15v.q[w15, 0]" + + - + input: + bytes: [ 0x25, 0x8c, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.q, p3/m, za1v.q[w12, 0]" + + - + input: + bytes: [ 0x21, 0x84, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.q, p1/m, za1v.q[w12, 0]" + + - + input: + bytes: [ 0x78, 0xd4, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.q, p5/m, za3v.q[w14, 0]" + + - + input: + bytes: [ 0x80, 0x99, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.q, p6/m, za12v.q[w12, 0]" + + - + input: + bytes: [ 0x31, 0xc8, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.q, p2/m, za1v.q[w14, 0]" + + - + input: + bytes: [ 0xdd, 0x88, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.q, p2/m, za6v.q[w12, 0]" + + - + input: + bytes: [ 0x22, 0xf5, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.q, p5/m, za9v.q[w15, 0]" + + - + input: + bytes: [ 0x87, 0xa9, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.q, p2/m, za12v.q[w13, 0]" + + - + input: + bytes: [ 0x00, 0x80, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.q, p0/m, za0v.q[w12, 0]" + + - + input: + bytes: [ 0x55, 0xd5, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.q, p5/m, za10v.q[w14, 0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z23.q, p3/m, za13v.q[w15, 0]" + + - + input: + bytes: [ 0xff, 0xfd, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.q, p7/m, za15v.q[w15, 0]" + + - + input: + bytes: [ 0x25, 0x8c, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.q, p3/m, za1v.q[w12, 0]" + + - + input: + bytes: [ 0x21, 0x84, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z1.q, p1/m, za1v.q[w12, 0]" + + - + input: + bytes: [ 0x78, 0xd4, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z24.q, p5/m, za3v.q[w14, 0]" + + - + input: + bytes: [ 0x80, 0x99, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.q, p6/m, za12v.q[w12, 0]" + + - + input: + bytes: [ 0x31, 0xc8, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z17.q, p2/m, za1v.q[w14, 0]" + + - + input: + bytes: [ 0xdd, 0x88, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z29.q, p2/m, za6v.q[w12, 0]" + + - + input: + bytes: [ 0x22, 0xf5, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z2.q, p5/m, za9v.q[w15, 0]" + + - + input: + bytes: [ 0x87, 0xa9, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z7.q, p2/m, za12v.q[w13, 0]" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 0], p0/m, z0.b" + + - + input: + bytes: [ 0x45, 0x55, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w14, 5], p5/m, z10.b" + + - + input: + bytes: [ 0xa7, 0x6d, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w15, 7], p3/m, z13.b" + + - + input: + bytes: [ 0xef, 0x7f, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w15, 15], p7/m, z31.b" + + - + input: + bytes: [ 0x25, 0x0e, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 5], p3/m, z17.b" + + - + input: + bytes: [ 0x21, 0x04, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 1], p1/m, z1.b" + + - + input: + bytes: [ 0x68, 0x56, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w14, 8], p5/m, z19.b" + + - + input: + bytes: [ 0x80, 0x19, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 0], p6/m, z12.b" + + - + input: + bytes: [ 0x21, 0x48, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w14, 1], p2/m, z1.b" + + - + input: + bytes: [ 0xcd, 0x0a, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 13], p2/m, z22.b" + + - + input: + bytes: [ 0x22, 0x75, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w15, 2], p5/m, z9.b" + + - + input: + bytes: [ 0x87, 0x29, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w13, 7], p2/m, z12.b" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 0], p0/m, z0.b" + + - + input: + bytes: [ 0x45, 0x55, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w14, 5], p5/m, z10.b" + + - + input: + bytes: [ 0xa7, 0x6d, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w15, 7], p3/m, z13.b" + + - + input: + bytes: [ 0xef, 0x7f, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w15, 15], p7/m, z31.b" + + - + input: + bytes: [ 0x25, 0x0e, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 5], p3/m, z17.b" + + - + input: + bytes: [ 0x21, 0x04, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 1], p1/m, z1.b" + + - + input: + bytes: [ 0x68, 0x56, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w14, 8], p5/m, z19.b" + + - + input: + bytes: [ 0x80, 0x19, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 0], p6/m, z12.b" + + - + input: + bytes: [ 0x21, 0x48, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w14, 1], p2/m, z1.b" + + - + input: + bytes: [ 0xcd, 0x0a, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 13], p2/m, z22.b" + + - + input: + bytes: [ 0x22, 0x75, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w15, 2], p5/m, z9.b" + + - + input: + bytes: [ 0x87, 0x29, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.b[w13, 7], p2/m, z12.b" + + - + input: + bytes: [ 0x00, 0x80, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 0], p0/m, z0.b" + + - + input: + bytes: [ 0x45, 0xd5, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w14, 5], p5/m, z10.b" + + - + input: + bytes: [ 0xa7, 0xed, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w15, 7], p3/m, z13.b" + + - + input: + bytes: [ 0xef, 0xff, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w15, 15], p7/m, z31.b" + + - + input: + bytes: [ 0x25, 0x8e, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 5], p3/m, z17.b" + + - + input: + bytes: [ 0x21, 0x84, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 1], p1/m, z1.b" + + - + input: + bytes: [ 0x68, 0xd6, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w14, 8], p5/m, z19.b" + + - + input: + bytes: [ 0x80, 0x99, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 0], p6/m, z12.b" + + - + input: + bytes: [ 0x21, 0xc8, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w14, 1], p2/m, z1.b" + + - + input: + bytes: [ 0xcd, 0x8a, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 13], p2/m, z22.b" + + - + input: + bytes: [ 0x22, 0xf5, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w15, 2], p5/m, z9.b" + + - + input: + bytes: [ 0x87, 0xa9, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w13, 7], p2/m, z12.b" + + - + input: + bytes: [ 0x00, 0x80, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 0], p0/m, z0.b" + + - + input: + bytes: [ 0x45, 0xd5, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w14, 5], p5/m, z10.b" + + - + input: + bytes: [ 0xa7, 0xed, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w15, 7], p3/m, z13.b" + + - + input: + bytes: [ 0xef, 0xff, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w15, 15], p7/m, z31.b" + + - + input: + bytes: [ 0x25, 0x8e, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 5], p3/m, z17.b" + + - + input: + bytes: [ 0x21, 0x84, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 1], p1/m, z1.b" + + - + input: + bytes: [ 0x68, 0xd6, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w14, 8], p5/m, z19.b" + + - + input: + bytes: [ 0x80, 0x99, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 0], p6/m, z12.b" + + - + input: + bytes: [ 0x21, 0xc8, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w14, 1], p2/m, z1.b" + + - + input: + bytes: [ 0xcd, 0x8a, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 13], p2/m, z22.b" + + - + input: + bytes: [ 0x22, 0xf5, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w15, 2], p5/m, z9.b" + + - + input: + bytes: [ 0x87, 0xa9, 0x00, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.b[w13, 7], p2/m, z12.b" + + - + input: + bytes: [ 0x00, 0x00, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 0], p0/m, z0.h" + + - + input: + bytes: [ 0x45, 0x55, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.h[w14, 5], p5/m, z10.h" + + - + input: + bytes: [ 0xa7, 0x6d, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.h[w15, 7], p3/m, z13.h" + + - + input: + bytes: [ 0xef, 0x7f, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.h[w15, 7], p7/m, z31.h" + + - + input: + bytes: [ 0x25, 0x0e, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 5], p3/m, z17.h" + + - + input: + bytes: [ 0x21, 0x04, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 1], p1/m, z1.h" + + - + input: + bytes: [ 0x68, 0x56, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.h[w14, 0], p5/m, z19.h" + + - + input: + bytes: [ 0x80, 0x19, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 0], p6/m, z12.h" + + - + input: + bytes: [ 0x21, 0x48, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.h[w14, 1], p2/m, z1.h" + + - + input: + bytes: [ 0xcd, 0x0a, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.h[w12, 5], p2/m, z22.h" + + - + input: + bytes: [ 0x22, 0x75, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.h[w15, 2], p5/m, z9.h" + + - + input: + bytes: [ 0x87, 0x29, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.h[w13, 7], p2/m, z12.h" + + - + input: + bytes: [ 0x00, 0x00, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 0], p0/m, z0.h" + + - + input: + bytes: [ 0x45, 0x55, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.h[w14, 5], p5/m, z10.h" + + - + input: + bytes: [ 0xa7, 0x6d, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.h[w15, 7], p3/m, z13.h" + + - + input: + bytes: [ 0xef, 0x7f, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.h[w15, 7], p7/m, z31.h" + + - + input: + bytes: [ 0x25, 0x0e, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 5], p3/m, z17.h" + + - + input: + bytes: [ 0x21, 0x04, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 1], p1/m, z1.h" + + - + input: + bytes: [ 0x68, 0x56, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.h[w14, 0], p5/m, z19.h" + + - + input: + bytes: [ 0x80, 0x19, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 0], p6/m, z12.h" + + - + input: + bytes: [ 0x21, 0x48, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.h[w14, 1], p2/m, z1.h" + + - + input: + bytes: [ 0xcd, 0x0a, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.h[w12, 5], p2/m, z22.h" + + - + input: + bytes: [ 0x22, 0x75, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.h[w15, 2], p5/m, z9.h" + + - + input: + bytes: [ 0x87, 0x29, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.h[w13, 7], p2/m, z12.h" + + - + input: + bytes: [ 0x00, 0x80, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 0], p0/m, z0.h" + + - + input: + bytes: [ 0x45, 0xd5, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.h[w14, 5], p5/m, z10.h" + + - + input: + bytes: [ 0xa7, 0xed, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.h[w15, 7], p3/m, z13.h" + + - + input: + bytes: [ 0xef, 0xff, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.h[w15, 7], p7/m, z31.h" + + - + input: + bytes: [ 0x25, 0x8e, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 5], p3/m, z17.h" + + - + input: + bytes: [ 0x21, 0x84, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 1], p1/m, z1.h" + + - + input: + bytes: [ 0x68, 0xd6, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.h[w14, 0], p5/m, z19.h" + + - + input: + bytes: [ 0x80, 0x99, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 0], p6/m, z12.h" + + - + input: + bytes: [ 0x21, 0xc8, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.h[w14, 1], p2/m, z1.h" + + - + input: + bytes: [ 0xcd, 0x8a, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.h[w12, 5], p2/m, z22.h" + + - + input: + bytes: [ 0x22, 0xf5, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.h[w15, 2], p5/m, z9.h" + + - + input: + bytes: [ 0x87, 0xa9, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.h[w13, 7], p2/m, z12.h" + + - + input: + bytes: [ 0x00, 0x80, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 0], p0/m, z0.h" + + - + input: + bytes: [ 0x45, 0xd5, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.h[w14, 5], p5/m, z10.h" + + - + input: + bytes: [ 0xa7, 0xed, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.h[w15, 7], p3/m, z13.h" + + - + input: + bytes: [ 0xef, 0xff, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.h[w15, 7], p7/m, z31.h" + + - + input: + bytes: [ 0x25, 0x8e, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 5], p3/m, z17.h" + + - + input: + bytes: [ 0x21, 0x84, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 1], p1/m, z1.h" + + - + input: + bytes: [ 0x68, 0xd6, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.h[w14, 0], p5/m, z19.h" + + - + input: + bytes: [ 0x80, 0x99, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 0], p6/m, z12.h" + + - + input: + bytes: [ 0x21, 0xc8, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.h[w14, 1], p2/m, z1.h" + + - + input: + bytes: [ 0xcd, 0x8a, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.h[w12, 5], p2/m, z22.h" + + - + input: + bytes: [ 0x22, 0xf5, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.h[w15, 2], p5/m, z9.h" + + - + input: + bytes: [ 0x87, 0xa9, 0x40, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.h[w13, 7], p2/m, z12.h" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.s[w12, 0], p0/m, z0.s" + + - + input: + bytes: [ 0x45, 0x55, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.s[w14, 1], p5/m, z10.s" + + - + input: + bytes: [ 0xa7, 0x6d, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.s[w15, 3], p3/m, z13.s" + + - + input: + bytes: [ 0xef, 0x7f, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za3h.s[w15, 3], p7/m, z31.s" + + - + input: + bytes: [ 0x25, 0x0e, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.s[w12, 1], p3/m, z17.s" + + - + input: + bytes: [ 0x21, 0x04, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.s[w12, 1], p1/m, z1.s" + + - + input: + bytes: [ 0x68, 0x56, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za2h.s[w14, 0], p5/m, z19.s" + + - + input: + bytes: [ 0x80, 0x19, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.s[w12, 0], p6/m, z12.s" + + - + input: + bytes: [ 0x21, 0x48, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.s[w14, 1], p2/m, z1.s" + + - + input: + bytes: [ 0xcd, 0x0a, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za3h.s[w12, 1], p2/m, z22.s" + + - + input: + bytes: [ 0x22, 0x75, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.s[w15, 2], p5/m, z9.s" + + - + input: + bytes: [ 0x87, 0x29, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.s[w13, 3], p2/m, z12.s" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.s[w12, 0], p0/m, z0.s" + + - + input: + bytes: [ 0x45, 0x55, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.s[w14, 1], p5/m, z10.s" + + - + input: + bytes: [ 0xa7, 0x6d, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.s[w15, 3], p3/m, z13.s" + + - + input: + bytes: [ 0xef, 0x7f, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za3h.s[w15, 3], p7/m, z31.s" + + - + input: + bytes: [ 0x25, 0x0e, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.s[w12, 1], p3/m, z17.s" + + - + input: + bytes: [ 0x21, 0x04, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.s[w12, 1], p1/m, z1.s" + + - + input: + bytes: [ 0x68, 0x56, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za2h.s[w14, 0], p5/m, z19.s" + + - + input: + bytes: [ 0x80, 0x19, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.s[w12, 0], p6/m, z12.s" + + - + input: + bytes: [ 0x21, 0x48, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.s[w14, 1], p2/m, z1.s" + + - + input: + bytes: [ 0xcd, 0x0a, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za3h.s[w12, 1], p2/m, z22.s" + + - + input: + bytes: [ 0x22, 0x75, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.s[w15, 2], p5/m, z9.s" + + - + input: + bytes: [ 0x87, 0x29, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.s[w13, 3], p2/m, z12.s" + + - + input: + bytes: [ 0x00, 0x80, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.s[w12, 0], p0/m, z0.s" + + - + input: + bytes: [ 0x45, 0xd5, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.s[w14, 1], p5/m, z10.s" + + - + input: + bytes: [ 0xa7, 0xed, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.s[w15, 3], p3/m, z13.s" + + - + input: + bytes: [ 0xef, 0xff, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za3v.s[w15, 3], p7/m, z31.s" + + - + input: + bytes: [ 0x25, 0x8e, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.s[w12, 1], p3/m, z17.s" + + - + input: + bytes: [ 0x21, 0x84, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.s[w12, 1], p1/m, z1.s" + + - + input: + bytes: [ 0x68, 0xd6, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za2v.s[w14, 0], p5/m, z19.s" + + - + input: + bytes: [ 0x80, 0x99, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.s[w12, 0], p6/m, z12.s" + + - + input: + bytes: [ 0x21, 0xc8, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.s[w14, 1], p2/m, z1.s" + + - + input: + bytes: [ 0xcd, 0x8a, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za3v.s[w12, 1], p2/m, z22.s" + + - + input: + bytes: [ 0x22, 0xf5, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.s[w15, 2], p5/m, z9.s" + + - + input: + bytes: [ 0x87, 0xa9, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.s[w13, 3], p2/m, z12.s" + + - + input: + bytes: [ 0x00, 0x80, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.s[w12, 0], p0/m, z0.s" + + - + input: + bytes: [ 0x45, 0xd5, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.s[w14, 1], p5/m, z10.s" + + - + input: + bytes: [ 0xa7, 0xed, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.s[w15, 3], p3/m, z13.s" + + - + input: + bytes: [ 0xef, 0xff, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za3v.s[w15, 3], p7/m, z31.s" + + - + input: + bytes: [ 0x25, 0x8e, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.s[w12, 1], p3/m, z17.s" + + - + input: + bytes: [ 0x21, 0x84, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.s[w12, 1], p1/m, z1.s" + + - + input: + bytes: [ 0x68, 0xd6, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za2v.s[w14, 0], p5/m, z19.s" + + - + input: + bytes: [ 0x80, 0x99, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.s[w12, 0], p6/m, z12.s" + + - + input: + bytes: [ 0x21, 0xc8, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.s[w14, 1], p2/m, z1.s" + + - + input: + bytes: [ 0xcd, 0x8a, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za3v.s[w12, 1], p2/m, z22.s" + + - + input: + bytes: [ 0x22, 0xf5, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.s[w15, 2], p5/m, z9.s" + + - + input: + bytes: [ 0x87, 0xa9, 0x80, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.s[w13, 3], p2/m, z12.s" + + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.d[w12, 0], p0/m, z0.d" + + - + input: + bytes: [ 0x45, 0x55, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za2h.d[w14, 1], p5/m, z10.d" + + - + input: + bytes: [ 0xa7, 0x6d, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za3h.d[w15, 1], p3/m, z13.d" + + - + input: + bytes: [ 0xef, 0x7f, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za7h.d[w15, 1], p7/m, z31.d" + + - + input: + bytes: [ 0x25, 0x0e, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za2h.d[w12, 1], p3/m, z17.d" + + - + input: + bytes: [ 0x21, 0x04, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.d[w12, 1], p1/m, z1.d" + + - + input: + bytes: [ 0x68, 0x56, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za4h.d[w14, 0], p5/m, z19.d" + + - + input: + bytes: [ 0x80, 0x19, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.d[w12, 0], p6/m, z12.d" + + - + input: + bytes: [ 0x21, 0x48, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.d[w14, 1], p2/m, z1.d" + + - + input: + bytes: [ 0xcd, 0x0a, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za6h.d[w12, 1], p2/m, z22.d" + + - + input: + bytes: [ 0x22, 0x75, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.d[w15, 0], p5/m, z9.d" + + - + input: + bytes: [ 0x87, 0x29, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za3h.d[w13, 1], p2/m, z12.d" + + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.d[w12, 0], p0/m, z0.d" + + - + input: + bytes: [ 0x45, 0x55, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za2h.d[w14, 1], p5/m, z10.d" + + - + input: + bytes: [ 0xa7, 0x6d, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za3h.d[w15, 1], p3/m, z13.d" + + - + input: + bytes: [ 0xef, 0x7f, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za7h.d[w15, 1], p7/m, z31.d" + + - + input: + bytes: [ 0x25, 0x0e, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za2h.d[w12, 1], p3/m, z17.d" + + - + input: + bytes: [ 0x21, 0x04, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.d[w12, 1], p1/m, z1.d" + + - + input: + bytes: [ 0x68, 0x56, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za4h.d[w14, 0], p5/m, z19.d" + + - + input: + bytes: [ 0x80, 0x19, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.d[w12, 0], p6/m, z12.d" + + - + input: + bytes: [ 0x21, 0x48, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.d[w14, 1], p2/m, z1.d" + + - + input: + bytes: [ 0xcd, 0x0a, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za6h.d[w12, 1], p2/m, z22.d" + + - + input: + bytes: [ 0x22, 0x75, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.d[w15, 0], p5/m, z9.d" + + - + input: + bytes: [ 0x87, 0x29, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za3h.d[w13, 1], p2/m, z12.d" + + - + input: + bytes: [ 0x00, 0x80, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.d[w12, 0], p0/m, z0.d" + + - + input: + bytes: [ 0x45, 0xd5, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za2v.d[w14, 1], p5/m, z10.d" + + - + input: + bytes: [ 0xa7, 0xed, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za3v.d[w15, 1], p3/m, z13.d" + + - + input: + bytes: [ 0xef, 0xff, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za7v.d[w15, 1], p7/m, z31.d" + + - + input: + bytes: [ 0x25, 0x8e, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za2v.d[w12, 1], p3/m, z17.d" + + - + input: + bytes: [ 0x21, 0x84, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.d[w12, 1], p1/m, z1.d" + + - + input: + bytes: [ 0x68, 0xd6, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za4v.d[w14, 0], p5/m, z19.d" + + - + input: + bytes: [ 0x80, 0x99, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.d[w12, 0], p6/m, z12.d" + + - + input: + bytes: [ 0x21, 0xc8, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.d[w14, 1], p2/m, z1.d" + + - + input: + bytes: [ 0xcd, 0x8a, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za6v.d[w12, 1], p2/m, z22.d" + + - + input: + bytes: [ 0x22, 0xf5, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.d[w15, 0], p5/m, z9.d" + + - + input: + bytes: [ 0x87, 0xa9, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za3v.d[w13, 1], p2/m, z12.d" + + - + input: + bytes: [ 0x00, 0x80, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.d[w12, 0], p0/m, z0.d" + + - + input: + bytes: [ 0x45, 0xd5, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za2v.d[w14, 1], p5/m, z10.d" + + - + input: + bytes: [ 0xa7, 0xed, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za3v.d[w15, 1], p3/m, z13.d" + + - + input: + bytes: [ 0xef, 0xff, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za7v.d[w15, 1], p7/m, z31.d" + + - + input: + bytes: [ 0x25, 0x8e, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za2v.d[w12, 1], p3/m, z17.d" + + - + input: + bytes: [ 0x21, 0x84, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.d[w12, 1], p1/m, z1.d" + + - + input: + bytes: [ 0x68, 0xd6, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za4v.d[w14, 0], p5/m, z19.d" + + - + input: + bytes: [ 0x80, 0x99, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.d[w12, 0], p6/m, z12.d" + + - + input: + bytes: [ 0x21, 0xc8, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.d[w14, 1], p2/m, z1.d" + + - + input: + bytes: [ 0xcd, 0x8a, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za6v.d[w12, 1], p2/m, z22.d" + + - + input: + bytes: [ 0x22, 0xf5, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.d[w15, 0], p5/m, z9.d" + + - + input: + bytes: [ 0x87, 0xa9, 0xc0, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za3v.d[w13, 1], p2/m, z12.d" + + - + input: + bytes: [ 0x00, 0x00, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.q[w12, 0], p0/m, z0.q" + + - + input: + bytes: [ 0x45, 0x55, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za5h.q[w14, 0], p5/m, z10.q" + + - + input: + bytes: [ 0xa7, 0x6d, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za7h.q[w15, 0], p3/m, z13.q" + + - + input: + bytes: [ 0xef, 0x7f, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za15h.q[w15, 0], p7/m, z31.q" + + - + input: + bytes: [ 0x25, 0x0e, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za5h.q[w12, 0], p3/m, z17.q" + + - + input: + bytes: [ 0x21, 0x04, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.q[w12, 0], p1/m, z1.q" + + - + input: + bytes: [ 0x68, 0x56, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za8h.q[w14, 0], p5/m, z19.q" + + - + input: + bytes: [ 0x80, 0x19, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.q[w12, 0], p6/m, z12.q" + + - + input: + bytes: [ 0x21, 0x48, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.q[w14, 0], p2/m, z1.q" + + - + input: + bytes: [ 0xcd, 0x0a, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za13h.q[w12, 0], p2/m, z22.q" + + - + input: + bytes: [ 0x22, 0x75, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za2h.q[w15, 0], p5/m, z9.q" + + - + input: + bytes: [ 0x87, 0x29, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za7h.q[w13, 0], p2/m, z12.q" + + - + input: + bytes: [ 0x00, 0x00, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.q[w12, 0], p0/m, z0.q" + + - + input: + bytes: [ 0x45, 0x55, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za5h.q[w14, 0], p5/m, z10.q" + + - + input: + bytes: [ 0xa7, 0x6d, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za7h.q[w15, 0], p3/m, z13.q" + + - + input: + bytes: [ 0xef, 0x7f, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za15h.q[w15, 0], p7/m, z31.q" + + - + input: + bytes: [ 0x25, 0x0e, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za5h.q[w12, 0], p3/m, z17.q" + + - + input: + bytes: [ 0x21, 0x04, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.q[w12, 0], p1/m, z1.q" + + - + input: + bytes: [ 0x68, 0x56, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za8h.q[w14, 0], p5/m, z19.q" + + - + input: + bytes: [ 0x80, 0x19, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0h.q[w12, 0], p6/m, z12.q" + + - + input: + bytes: [ 0x21, 0x48, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1h.q[w14, 0], p2/m, z1.q" + + - + input: + bytes: [ 0xcd, 0x0a, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za13h.q[w12, 0], p2/m, z22.q" + + - + input: + bytes: [ 0x22, 0x75, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za2h.q[w15, 0], p5/m, z9.q" + + - + input: + bytes: [ 0x87, 0x29, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za7h.q[w13, 0], p2/m, z12.q" + + - + input: + bytes: [ 0x00, 0x80, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.q[w12, 0], p0/m, z0.q" + + - + input: + bytes: [ 0x45, 0xd5, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za5v.q[w14, 0], p5/m, z10.q" + + - + input: + bytes: [ 0xa7, 0xed, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za7v.q[w15, 0], p3/m, z13.q" + + - + input: + bytes: [ 0xef, 0xff, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za15v.q[w15, 0], p7/m, z31.q" + + - + input: + bytes: [ 0x25, 0x8e, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za5v.q[w12, 0], p3/m, z17.q" + + - + input: + bytes: [ 0x21, 0x84, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.q[w12, 0], p1/m, z1.q" + + - + input: + bytes: [ 0x68, 0xd6, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za8v.q[w14, 0], p5/m, z19.q" + + - + input: + bytes: [ 0x80, 0x99, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.q[w12, 0], p6/m, z12.q" + + - + input: + bytes: [ 0x21, 0xc8, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.q[w14, 0], p2/m, z1.q" + + - + input: + bytes: [ 0xcd, 0x8a, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za13v.q[w12, 0], p2/m, z22.q" + + - + input: + bytes: [ 0x22, 0xf5, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za2v.q[w15, 0], p5/m, z9.q" + + - + input: + bytes: [ 0x87, 0xa9, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za7v.q[w13, 0], p2/m, z12.q" + + - + input: + bytes: [ 0x00, 0x80, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.q[w12, 0], p0/m, z0.q" + + - + input: + bytes: [ 0x45, 0xd5, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za5v.q[w14, 0], p5/m, z10.q" + + - + input: + bytes: [ 0xa7, 0xed, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za7v.q[w15, 0], p3/m, z13.q" + + - + input: + bytes: [ 0xef, 0xff, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za15v.q[w15, 0], p7/m, z31.q" + + - + input: + bytes: [ 0x25, 0x8e, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za5v.q[w12, 0], p3/m, z17.q" + + - + input: + bytes: [ 0x21, 0x84, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.q[w12, 0], p1/m, z1.q" + + - + input: + bytes: [ 0x68, 0xd6, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za8v.q[w14, 0], p5/m, z19.q" + + - + input: + bytes: [ 0x80, 0x99, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za0v.q[w12, 0], p6/m, z12.q" + + - + input: + bytes: [ 0x21, 0xc8, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za1v.q[w14, 0], p2/m, z1.q" + + - + input: + bytes: [ 0xcd, 0x8a, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za13v.q[w12, 0], p2/m, z22.q" + + - + input: + bytes: [ 0x22, 0xf5, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za2v.q[w15, 0], p5/m, z9.q" + + - + input: + bytes: [ 0x87, 0xa9, 0xc1, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov za7v.q[w13, 0], p2/m, z12.q" diff --git a/tests/MC/AArch64/SME/psel.s.yaml b/tests/MC/AArch64/SME/psel.s.yaml new file mode 100644 index 0000000000..abb202ca3d --- /dev/null +++ b/tests/MC/AArch64/SME/psel.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0x24, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p0, p0, p0.b[w12, 0]" + + - + input: + bytes: [ 0x45, 0x55, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p5, p5, p10.b[w13, 6]" + + - + input: + bytes: [ 0xa7, 0x6d, 0x6c, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p7, p11, p13.b[w12, 5]" + + - + input: + bytes: [ 0xef, 0x7d, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p15, p15, p15.b[w15, 15]" + + - + input: + bytes: [ 0x00, 0x40, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p0, p0, p0.h[w12, 0]" + + - + input: + bytes: [ 0x45, 0x55, 0x79, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p5, p5, p10.h[w13, 3]" + + - + input: + bytes: [ 0xa7, 0x6d, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p7, p11, p13.h[w12, 2]" + + - + input: + bytes: [ 0xef, 0x7d, 0xfb, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p15, p15, p15.h[w15, 7]" + + - + input: + bytes: [ 0x00, 0x40, 0x30, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p0, p0, p0.s[w12, 0]" + + - + input: + bytes: [ 0x45, 0x55, 0x71, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p5, p5, p10.s[w13, 1]" + + - + input: + bytes: [ 0xa7, 0x6d, 0x70, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p7, p11, p13.s[w12, 1]" + + - + input: + bytes: [ 0xef, 0x7d, 0xf3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p15, p15, p15.s[w15, 3]" + + - + input: + bytes: [ 0x00, 0x40, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p0, p0, p0.d[w12, 0]" + + - + input: + bytes: [ 0x45, 0x55, 0x61, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p5, p5, p10.d[w13, 0]" + + - + input: + bytes: [ 0xa7, 0x6d, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p7, p11, p13.d[w12, 0]" + + - + input: + bytes: [ 0xef, 0x7d, 0xe3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p15, p15, p15.d[w15, 1]" + + - + input: + bytes: [ 0xef, 0x7d, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p15, p15, p15.b[w15, 15]" + + - + input: + bytes: [ 0xef, 0x7d, 0xfb, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p15, p15, p15.h[w15, 7]" + + - + input: + bytes: [ 0xef, 0x7d, 0xf3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p15, p15, p15.s[w15, 3]" + + - + input: + bytes: [ 0xef, 0x7d, 0xe3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "psel p15, p15, p15.d[w15, 1]" diff --git a/tests/MC/AArch64/SME/rdsvl.s.yaml b/tests/MC/AArch64/SME/rdsvl.s.yaml new file mode 100644 index 0000000000..9487686b83 --- /dev/null +++ b/tests/MC/AArch64/SME/rdsvl.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x58, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rdsvl x0, #0" + + - + input: + bytes: [ 0xff, 0x5f, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rdsvl xzr, #-1" + + - + input: + bytes: [ 0xf7, 0x5b, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rdsvl x23, #31" + + - + input: + bytes: [ 0x15, 0x5c, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rdsvl x21, #-32" diff --git a/tests/MC/AArch64/SME/revd.s.yaml b/tests/MC/AArch64/SME/revd.s.yaml new file mode 100644 index 0000000000..75d3967917 --- /dev/null +++ b/tests/MC/AArch64/SME/revd.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x2e, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "revd z0.q, p0/m, z0.q" + + - + input: + bytes: [ 0x55, 0x95, 0x2e, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "revd z21.q, p5/m, z10.q" + + - + input: + bytes: [ 0xb7, 0x8d, 0x2e, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "revd z23.q, p3/m, z13.q" + + - + input: + bytes: [ 0xff, 0x9f, 0x2e, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "revd z31.q, p7/m, z31.q" + + - + input: + bytes: [ 0x35, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z25" + + - + input: + bytes: [ 0x55, 0x95, 0x2e, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "revd z21.q, p5/m, z10.q" diff --git a/tests/MC/AArch64/SME/sclamp.s.yaml b/tests/MC/AArch64/SME/sclamp.s.yaml new file mode 100644 index 0000000000..a84fbe1f94 --- /dev/null +++ b/tests/MC/AArch64/SME/sclamp.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0x00, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x55, 0xc1, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z21.b, z10.b, z21.b" + + - + input: + bytes: [ 0xb7, 0xc1, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z23.b, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0xc3, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0xc0, 0x40, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xc1, 0x55, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xc1, 0x48, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xc3, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0xc0, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x55, 0xc1, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z21.s, z10.s, z21.s" + + - + input: + bytes: [ 0xb7, 0xc1, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0xff, 0xc3, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0xc0, 0xc0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x55, 0xc1, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z21.d, z10.d, z21.d" + + - + input: + bytes: [ 0xb7, 0xc1, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0xc3, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x77, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z23, z27" + + - + input: + bytes: [ 0xb7, 0xc1, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z23.b, z13.b, z8.b" + + - + input: + bytes: [ 0x77, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z23, z27" + + - + input: + bytes: [ 0xb7, 0xc1, 0x48, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0x77, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z23, z27" + + - + input: + bytes: [ 0xb7, 0xc1, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0x77, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z23, z27" + + - + input: + bytes: [ 0xb7, 0xc1, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sclamp z23.d, z13.d, z8.d" diff --git a/tests/MC/AArch64/SME/smopa-32.s.yaml b/tests/MC/AArch64/SME/smopa-32.s.yaml new file mode 100644 index 0000000000..18283aec5f --- /dev/null +++ b/tests/MC/AArch64/SME/smopa-32.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x80, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smopa za0.s, p0/m, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x41, 0x55, 0x95, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smopa za1.s, p5/m, p2/m, z10.b, z21.b" + + - + input: + bytes: [ 0xa3, 0xed, 0x88, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smopa za3.s, p3/m, p7/m, z13.b, z8.b" + + - + input: + bytes: [ 0xe3, 0xff, 0x9f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smopa za3.s, p7/m, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0x21, 0x0e, 0x90, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smopa za1.s, p3/m, p0/m, z17.b, z16.b" + + - + input: + bytes: [ 0x21, 0x84, 0x9e, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smopa za1.s, p1/m, p4/m, z1.b, z30.b" + + - + input: + bytes: [ 0x60, 0x56, 0x94, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smopa za0.s, p5/m, p2/m, z19.b, z20.b" + + - + input: + bytes: [ 0x80, 0x19, 0x82, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smopa za0.s, p6/m, p0/m, z12.b, z2.b" + + - + input: + bytes: [ 0x21, 0xc8, 0x9a, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smopa za1.s, p2/m, p6/m, z1.b, z26.b" + + - + input: + bytes: [ 0xc1, 0x0a, 0x9e, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smopa za1.s, p2/m, p0/m, z22.b, z30.b" + + - + input: + bytes: [ 0x22, 0xf5, 0x81, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smopa za2.s, p5/m, p7/m, z9.b, z1.b" + + - + input: + bytes: [ 0x83, 0xa9, 0x8b, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smopa za3.s, p2/m, p5/m, z12.b, z11.b" diff --git a/tests/MC/AArch64/SME/smopa-64.s.yaml b/tests/MC/AArch64/SME/smopa-64.s.yaml new file mode 100644 index 0000000000..9c538c3d7e --- /dev/null +++ b/tests/MC/AArch64/SME/smopa-64.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smopa za0.d, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x45, 0x55, 0xd5, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smopa za5.d, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xa7, 0xed, 0xc8, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smopa za7.d, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xe7, 0xff, 0xdf, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smopa za7.d, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x25, 0x0e, 0xd0, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smopa za5.d, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x21, 0x84, 0xde, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smopa za1.d, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x60, 0x56, 0xd4, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smopa za0.d, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x80, 0x19, 0xc2, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smopa za0.d, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x21, 0xc8, 0xda, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smopa za1.d, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xc5, 0x0a, 0xde, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smopa za5.d, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x22, 0xf5, 0xc1, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smopa za2.d, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x87, 0xa9, 0xcb, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smopa za7.d, p2/m, p5/m, z12.h, z11.h" diff --git a/tests/MC/AArch64/SME/smops-32.s.yaml b/tests/MC/AArch64/SME/smops-32.s.yaml new file mode 100644 index 0000000000..e7d3d8bd6e --- /dev/null +++ b/tests/MC/AArch64/SME/smops-32.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x00, 0x80, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smops za0.s, p0/m, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x51, 0x55, 0x95, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smops za1.s, p5/m, p2/m, z10.b, z21.b" + + - + input: + bytes: [ 0xb3, 0xed, 0x88, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smops za3.s, p3/m, p7/m, z13.b, z8.b" + + - + input: + bytes: [ 0xf3, 0xff, 0x9f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smops za3.s, p7/m, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0x31, 0x0e, 0x90, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smops za1.s, p3/m, p0/m, z17.b, z16.b" + + - + input: + bytes: [ 0x31, 0x84, 0x9e, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smops za1.s, p1/m, p4/m, z1.b, z30.b" + + - + input: + bytes: [ 0x70, 0x56, 0x94, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smops za0.s, p5/m, p2/m, z19.b, z20.b" + + - + input: + bytes: [ 0x90, 0x19, 0x82, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smops za0.s, p6/m, p0/m, z12.b, z2.b" + + - + input: + bytes: [ 0x31, 0xc8, 0x9a, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smops za1.s, p2/m, p6/m, z1.b, z26.b" + + - + input: + bytes: [ 0xd1, 0x0a, 0x9e, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smops za1.s, p2/m, p0/m, z22.b, z30.b" + + - + input: + bytes: [ 0x32, 0xf5, 0x81, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smops za2.s, p5/m, p7/m, z9.b, z1.b" + + - + input: + bytes: [ 0x93, 0xa9, 0x8b, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smops za3.s, p2/m, p5/m, z12.b, z11.b" diff --git a/tests/MC/AArch64/SME/smops-64.s.yaml b/tests/MC/AArch64/SME/smops-64.s.yaml new file mode 100644 index 0000000000..689e3c89d6 --- /dev/null +++ b/tests/MC/AArch64/SME/smops-64.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x00, 0xc0, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smops za0.d, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x55, 0xd5, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smops za5.d, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xed, 0xc8, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smops za7.d, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xf7, 0xff, 0xdf, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smops za7.d, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x35, 0x0e, 0xd0, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smops za5.d, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x31, 0x84, 0xde, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smops za1.d, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x70, 0x56, 0xd4, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smops za0.d, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x90, 0x19, 0xc2, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smops za0.d, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x31, 0xc8, 0xda, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smops za1.d, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xd5, 0x0a, 0xde, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smops za5.d, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x32, 0xf5, 0xc1, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smops za2.d, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x97, 0xa9, 0xcb, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "smops za7.d, p2/m, p5/m, z12.h, z11.h" diff --git a/tests/MC/AArch64/SME/smstart.s.yaml b/tests/MC/AArch64/SME/smstart.s.yaml new file mode 100644 index 0000000000..f2c0eaf6de --- /dev/null +++ b/tests/MC/AArch64/SME/smstart.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x7f, 0x47, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smstart" + + - + input: + bytes: [ 0x7f, 0x43, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smstart sm" + + - + input: + bytes: [ 0x7f, 0x45, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smstart za" + + - + input: + bytes: [ 0x7f, 0x43, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smstart sm" + + - + input: + bytes: [ 0x7f, 0x45, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smstart za" + + - + input: + bytes: [ 0x7f, 0x47, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "smstart" + + - + input: + bytes: [ 0x7f, 0x43, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "smstart sm" + + - + input: + bytes: [ 0x7f, 0x45, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "smstart za" + + - + input: + bytes: [ 0x7f, 0x43, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "smstart sm" + + - + input: + bytes: [ 0x7f, 0x45, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "smstart za" diff --git a/tests/MC/AArch64/SME/smstop.s.yaml b/tests/MC/AArch64/SME/smstop.s.yaml new file mode 100644 index 0000000000..54d880a8c6 --- /dev/null +++ b/tests/MC/AArch64/SME/smstop.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x7f, 0x46, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smstop" + + - + input: + bytes: [ 0x7f, 0x42, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smstop sm" + + - + input: + bytes: [ 0x7f, 0x44, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smstop za" + + - + input: + bytes: [ 0x7f, 0x42, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smstop sm" + + - + input: + bytes: [ 0x7f, 0x44, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smstop za" + + - + input: + bytes: [ 0x7f, 0x46, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "smstop" + + - + input: + bytes: [ 0x7f, 0x42, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "smstop sm" + + - + input: + bytes: [ 0x7f, 0x44, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "smstop za" + + - + input: + bytes: [ 0x7f, 0x42, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "smstop sm" + + - + input: + bytes: [ 0x7f, 0x44, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "smstop za" diff --git a/tests/MC/AArch64/SME/st1b.s.yaml b/tests/MC/AArch64/SME/st1b.s.yaml new file mode 100644 index 0000000000..733d8b8bc2 --- /dev/null +++ b/tests/MC/AArch64/SME/st1b.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x20, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w12, 0]}, p0, [x0, x0]" + + - + input: + bytes: [ 0x45, 0x55, 0x35, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w14, 5]}, p5, [x10, x21]" + + - + input: + bytes: [ 0xa7, 0x6d, 0x28, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w15, 7]}, p3, [x13, x8]" + + - + input: + bytes: [ 0xef, 0x7f, 0x3f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w15, 15]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0x30, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w12, 5]}, p3, [x17, x16]" + + - + input: + bytes: [ 0x21, 0x04, 0x3e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w12, 1]}, p1, [x1, x30]" + + - + input: + bytes: [ 0x68, 0x56, 0x34, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w14, 8]}, p5, [x19, x20]" + + - + input: + bytes: [ 0x80, 0x19, 0x22, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w12, 0]}, p6, [x12, x2]" + + - + input: + bytes: [ 0x21, 0x48, 0x3a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w14, 1]}, p2, [x1, x26]" + + - + input: + bytes: [ 0xcd, 0x0a, 0x3e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w12, 13]}, p2, [x22, x30]" + + - + input: + bytes: [ 0x22, 0x75, 0x21, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w15, 2]}, p5, [x9, x1]" + + - + input: + bytes: [ 0x87, 0x29, 0x2b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w13, 7]}, p2, [x12, x11]" + + - + input: + bytes: [ 0x00, 0x00, 0x20, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w12, 0]}, p0, [x0, x0]" + + - + input: + bytes: [ 0x45, 0x55, 0x35, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w14, 5]}, p5, [x10, x21]" + + - + input: + bytes: [ 0xa7, 0x6d, 0x28, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w15, 7]}, p3, [x13, x8]" + + - + input: + bytes: [ 0xef, 0x7f, 0x3f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w15, 15]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0x30, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w12, 5]}, p3, [x17, x16]" + + - + input: + bytes: [ 0x21, 0x04, 0x3e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w12, 1]}, p1, [x1, x30]" + + - + input: + bytes: [ 0x68, 0x56, 0x34, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w14, 8]}, p5, [x19, x20]" + + - + input: + bytes: [ 0x80, 0x19, 0x22, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w12, 0]}, p6, [x12, x2]" + + - + input: + bytes: [ 0x21, 0x48, 0x3a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w14, 1]}, p2, [x1, x26]" + + - + input: + bytes: [ 0xcd, 0x0a, 0x3e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w12, 13]}, p2, [x22, x30]" + + - + input: + bytes: [ 0x22, 0x75, 0x21, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w15, 2]}, p5, [x9, x1]" + + - + input: + bytes: [ 0x87, 0x29, 0x2b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0h.b[w13, 7]}, p2, [x12, x11]" + + - + input: + bytes: [ 0x00, 0x80, 0x20, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w12, 0]}, p0, [x0, x0]" + + - + input: + bytes: [ 0x45, 0xd5, 0x35, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w14, 5]}, p5, [x10, x21]" + + - + input: + bytes: [ 0xa7, 0xed, 0x28, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w15, 7]}, p3, [x13, x8]" + + - + input: + bytes: [ 0xef, 0xff, 0x3f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w15, 15]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0x30, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w12, 5]}, p3, [x17, x16]" + + - + input: + bytes: [ 0x21, 0x84, 0x3e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w12, 1]}, p1, [x1, x30]" + + - + input: + bytes: [ 0x68, 0xd6, 0x34, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w14, 8]}, p5, [x19, x20]" + + - + input: + bytes: [ 0x80, 0x99, 0x22, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w12, 0]}, p6, [x12, x2]" + + - + input: + bytes: [ 0x21, 0xc8, 0x3a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w14, 1]}, p2, [x1, x26]" + + - + input: + bytes: [ 0xcd, 0x8a, 0x3e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w12, 13]}, p2, [x22, x30]" + + - + input: + bytes: [ 0x22, 0xf5, 0x21, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w15, 2]}, p5, [x9, x1]" + + - + input: + bytes: [ 0x87, 0xa9, 0x2b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w13, 7]}, p2, [x12, x11]" + + - + input: + bytes: [ 0x00, 0x80, 0x20, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w12, 0]}, p0, [x0, x0]" + + - + input: + bytes: [ 0x45, 0xd5, 0x35, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w14, 5]}, p5, [x10, x21]" + + - + input: + bytes: [ 0xa7, 0xed, 0x28, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w15, 7]}, p3, [x13, x8]" + + - + input: + bytes: [ 0xef, 0xff, 0x3f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w15, 15]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0x30, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w12, 5]}, p3, [x17, x16]" + + - + input: + bytes: [ 0x21, 0x84, 0x3e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w12, 1]}, p1, [x1, x30]" + + - + input: + bytes: [ 0x68, 0xd6, 0x34, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w14, 8]}, p5, [x19, x20]" + + - + input: + bytes: [ 0x80, 0x99, 0x22, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w12, 0]}, p6, [x12, x2]" + + - + input: + bytes: [ 0x21, 0xc8, 0x3a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w14, 1]}, p2, [x1, x26]" + + - + input: + bytes: [ 0xcd, 0x8a, 0x3e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w12, 13]}, p2, [x22, x30]" + + - + input: + bytes: [ 0x22, 0xf5, 0x21, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w15, 2]}, p5, [x9, x1]" + + - + input: + bytes: [ 0x87, 0xa9, 0x2b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b {za0v.b[w13, 7]}, p2, [x12, x11]" diff --git a/tests/MC/AArch64/SME/st1d.s.yaml b/tests/MC/AArch64/SME/st1d.s.yaml new file mode 100644 index 0000000000..edbdfdca02 --- /dev/null +++ b/tests/MC/AArch64/SME/st1d.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xe0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za0h.d[w12, 0]}, p0, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x45, 0x55, 0xf5, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za2h.d[w14, 1]}, p5, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xa7, 0x6d, 0xe8, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za3h.d[w15, 1]}, p3, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xef, 0x7f, 0xff, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za7h.d[w15, 1]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0xf0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za2h.d[w12, 1]}, p3, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x21, 0x04, 0xfe, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za0h.d[w12, 1]}, p1, [x1, x30, lsl #3]" + + - + input: + bytes: [ 0x68, 0x56, 0xf4, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za4h.d[w14, 0]}, p5, [x19, x20, lsl #3]" + + - + input: + bytes: [ 0x80, 0x19, 0xe2, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za0h.d[w12, 0]}, p6, [x12, x2, lsl #3]" + + - + input: + bytes: [ 0x21, 0x48, 0xfa, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za0h.d[w14, 1]}, p2, [x1, x26, lsl #3]" + + - + input: + bytes: [ 0xcd, 0x0a, 0xfe, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za6h.d[w12, 1]}, p2, [x22, x30, lsl #3]" + + - + input: + bytes: [ 0x22, 0x75, 0xe1, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za1h.d[w15, 0]}, p5, [x9, x1, lsl #3]" + + - + input: + bytes: [ 0x87, 0x29, 0xeb, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za3h.d[w13, 1]}, p2, [x12, x11, lsl #3]" + + - + input: + bytes: [ 0x00, 0x00, 0xe0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za0h.d[w12, 0]}, p0, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x45, 0x55, 0xf5, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za2h.d[w14, 1]}, p5, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xa7, 0x6d, 0xe8, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za3h.d[w15, 1]}, p3, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xef, 0x7f, 0xff, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za7h.d[w15, 1]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0xf0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za2h.d[w12, 1]}, p3, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x21, 0x04, 0xfe, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za0h.d[w12, 1]}, p1, [x1, x30, lsl #3]" + + - + input: + bytes: [ 0x68, 0x56, 0xf4, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za4h.d[w14, 0]}, p5, [x19, x20, lsl #3]" + + - + input: + bytes: [ 0x80, 0x19, 0xe2, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za0h.d[w12, 0]}, p6, [x12, x2, lsl #3]" + + - + input: + bytes: [ 0x21, 0x48, 0xfa, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za0h.d[w14, 1]}, p2, [x1, x26, lsl #3]" + + - + input: + bytes: [ 0xcd, 0x0a, 0xfe, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za6h.d[w12, 1]}, p2, [x22, x30, lsl #3]" + + - + input: + bytes: [ 0x22, 0x75, 0xe1, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za1h.d[w15, 0]}, p5, [x9, x1, lsl #3]" + + - + input: + bytes: [ 0x87, 0x29, 0xeb, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za3h.d[w13, 1]}, p2, [x12, x11, lsl #3]" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za0v.d[w12, 0]}, p0, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x45, 0xd5, 0xf5, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za2v.d[w14, 1]}, p5, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xa7, 0xed, 0xe8, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za3v.d[w15, 1]}, p3, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xef, 0xff, 0xff, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za7v.d[w15, 1]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0xf0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za2v.d[w12, 1]}, p3, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x21, 0x84, 0xfe, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za0v.d[w12, 1]}, p1, [x1, x30, lsl #3]" + + - + input: + bytes: [ 0x68, 0xd6, 0xf4, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za4v.d[w14, 0]}, p5, [x19, x20, lsl #3]" + + - + input: + bytes: [ 0x80, 0x99, 0xe2, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za0v.d[w12, 0]}, p6, [x12, x2, lsl #3]" + + - + input: + bytes: [ 0x21, 0xc8, 0xfa, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za0v.d[w14, 1]}, p2, [x1, x26, lsl #3]" + + - + input: + bytes: [ 0xcd, 0x8a, 0xfe, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za6v.d[w12, 1]}, p2, [x22, x30, lsl #3]" + + - + input: + bytes: [ 0x22, 0xf5, 0xe1, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za1v.d[w15, 0]}, p5, [x9, x1, lsl #3]" + + - + input: + bytes: [ 0x87, 0xa9, 0xeb, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za3v.d[w13, 1]}, p2, [x12, x11, lsl #3]" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za0v.d[w12, 0]}, p0, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x45, 0xd5, 0xf5, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za2v.d[w14, 1]}, p5, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xa7, 0xed, 0xe8, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za3v.d[w15, 1]}, p3, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xef, 0xff, 0xff, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za7v.d[w15, 1]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0xf0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za2v.d[w12, 1]}, p3, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x21, 0x84, 0xfe, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za0v.d[w12, 1]}, p1, [x1, x30, lsl #3]" + + - + input: + bytes: [ 0x68, 0xd6, 0xf4, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za4v.d[w14, 0]}, p5, [x19, x20, lsl #3]" + + - + input: + bytes: [ 0x80, 0x99, 0xe2, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za0v.d[w12, 0]}, p6, [x12, x2, lsl #3]" + + - + input: + bytes: [ 0x21, 0xc8, 0xfa, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za0v.d[w14, 1]}, p2, [x1, x26, lsl #3]" + + - + input: + bytes: [ 0xcd, 0x8a, 0xfe, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za6v.d[w12, 1]}, p2, [x22, x30, lsl #3]" + + - + input: + bytes: [ 0x22, 0xf5, 0xe1, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za1v.d[w15, 0]}, p5, [x9, x1, lsl #3]" + + - + input: + bytes: [ 0x87, 0xa9, 0xeb, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d {za3v.d[w13, 1]}, p2, [x12, x11, lsl #3]" diff --git a/tests/MC/AArch64/SME/st1h.s.yaml b/tests/MC/AArch64/SME/st1h.s.yaml new file mode 100644 index 0000000000..012fe6fc9b --- /dev/null +++ b/tests/MC/AArch64/SME/st1h.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x60, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0h.h[w12, 0]}, p0, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x45, 0x55, 0x75, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0h.h[w14, 5]}, p5, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xa7, 0x6d, 0x68, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0h.h[w15, 7]}, p3, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xef, 0x7f, 0x7f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za1h.h[w15, 7]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0x70, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0h.h[w12, 5]}, p3, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x21, 0x04, 0x7e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0h.h[w12, 1]}, p1, [x1, x30, lsl #1]" + + - + input: + bytes: [ 0x68, 0x56, 0x74, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za1h.h[w14, 0]}, p5, [x19, x20, lsl #1]" + + - + input: + bytes: [ 0x80, 0x19, 0x62, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0h.h[w12, 0]}, p6, [x12, x2, lsl #1]" + + - + input: + bytes: [ 0x21, 0x48, 0x7a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0h.h[w14, 1]}, p2, [x1, x26, lsl #1]" + + - + input: + bytes: [ 0xcd, 0x0a, 0x7e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za1h.h[w12, 5]}, p2, [x22, x30, lsl #1]" + + - + input: + bytes: [ 0x22, 0x75, 0x61, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0h.h[w15, 2]}, p5, [x9, x1, lsl #1]" + + - + input: + bytes: [ 0x87, 0x29, 0x6b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0h.h[w13, 7]}, p2, [x12, x11, lsl #1]" + + - + input: + bytes: [ 0x00, 0x00, 0x60, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0h.h[w12, 0]}, p0, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x45, 0x55, 0x75, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0h.h[w14, 5]}, p5, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xa7, 0x6d, 0x68, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0h.h[w15, 7]}, p3, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xef, 0x7f, 0x7f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za1h.h[w15, 7]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0x70, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0h.h[w12, 5]}, p3, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x21, 0x04, 0x7e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0h.h[w12, 1]}, p1, [x1, x30, lsl #1]" + + - + input: + bytes: [ 0x68, 0x56, 0x74, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za1h.h[w14, 0]}, p5, [x19, x20, lsl #1]" + + - + input: + bytes: [ 0x80, 0x19, 0x62, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0h.h[w12, 0]}, p6, [x12, x2, lsl #1]" + + - + input: + bytes: [ 0x21, 0x48, 0x7a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0h.h[w14, 1]}, p2, [x1, x26, lsl #1]" + + - + input: + bytes: [ 0xcd, 0x0a, 0x7e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za1h.h[w12, 5]}, p2, [x22, x30, lsl #1]" + + - + input: + bytes: [ 0x22, 0x75, 0x61, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0h.h[w15, 2]}, p5, [x9, x1, lsl #1]" + + - + input: + bytes: [ 0x87, 0x29, 0x6b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0h.h[w13, 7]}, p2, [x12, x11, lsl #1]" + + - + input: + bytes: [ 0x00, 0x80, 0x60, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0v.h[w12, 0]}, p0, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x45, 0xd5, 0x75, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0v.h[w14, 5]}, p5, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xa7, 0xed, 0x68, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0v.h[w15, 7]}, p3, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xef, 0xff, 0x7f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za1v.h[w15, 7]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0x70, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0v.h[w12, 5]}, p3, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x21, 0x84, 0x7e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0v.h[w12, 1]}, p1, [x1, x30, lsl #1]" + + - + input: + bytes: [ 0x68, 0xd6, 0x74, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za1v.h[w14, 0]}, p5, [x19, x20, lsl #1]" + + - + input: + bytes: [ 0x80, 0x99, 0x62, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0v.h[w12, 0]}, p6, [x12, x2, lsl #1]" + + - + input: + bytes: [ 0x21, 0xc8, 0x7a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0v.h[w14, 1]}, p2, [x1, x26, lsl #1]" + + - + input: + bytes: [ 0xcd, 0x8a, 0x7e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za1v.h[w12, 5]}, p2, [x22, x30, lsl #1]" + + - + input: + bytes: [ 0x22, 0xf5, 0x61, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0v.h[w15, 2]}, p5, [x9, x1, lsl #1]" + + - + input: + bytes: [ 0x87, 0xa9, 0x6b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0v.h[w13, 7]}, p2, [x12, x11, lsl #1]" + + - + input: + bytes: [ 0x00, 0x80, 0x60, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0v.h[w12, 0]}, p0, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x45, 0xd5, 0x75, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0v.h[w14, 5]}, p5, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xa7, 0xed, 0x68, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0v.h[w15, 7]}, p3, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xef, 0xff, 0x7f, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za1v.h[w15, 7]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0x70, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0v.h[w12, 5]}, p3, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x21, 0x84, 0x7e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0v.h[w12, 1]}, p1, [x1, x30, lsl #1]" + + - + input: + bytes: [ 0x68, 0xd6, 0x74, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za1v.h[w14, 0]}, p5, [x19, x20, lsl #1]" + + - + input: + bytes: [ 0x80, 0x99, 0x62, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0v.h[w12, 0]}, p6, [x12, x2, lsl #1]" + + - + input: + bytes: [ 0x21, 0xc8, 0x7a, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0v.h[w14, 1]}, p2, [x1, x26, lsl #1]" + + - + input: + bytes: [ 0xcd, 0x8a, 0x7e, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za1v.h[w12, 5]}, p2, [x22, x30, lsl #1]" + + - + input: + bytes: [ 0x22, 0xf5, 0x61, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0v.h[w15, 2]}, p5, [x9, x1, lsl #1]" + + - + input: + bytes: [ 0x87, 0xa9, 0x6b, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h {za0v.h[w13, 7]}, p2, [x12, x11, lsl #1]" diff --git a/tests/MC/AArch64/SME/st1q.s.yaml b/tests/MC/AArch64/SME/st1q.s.yaml new file mode 100644 index 0000000000..ff8344c529 --- /dev/null +++ b/tests/MC/AArch64/SME/st1q.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xe0, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za0h.q[w12, 0]}, p0, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x45, 0x55, 0xf5, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za5h.q[w14, 0]}, p5, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xa7, 0x6d, 0xe8, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za7h.q[w15, 0]}, p3, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0xef, 0x7f, 0xff, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za15h.q[w15, 0]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0xf0, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za5h.q[w12, 0]}, p3, [x17, x16, lsl #4]" + + - + input: + bytes: [ 0x21, 0x04, 0xfe, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za1h.q[w12, 0]}, p1, [x1, x30, lsl #4]" + + - + input: + bytes: [ 0x68, 0x56, 0xf4, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za8h.q[w14, 0]}, p5, [x19, x20, lsl #4]" + + - + input: + bytes: [ 0x80, 0x19, 0xe2, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za0h.q[w12, 0]}, p6, [x12, x2, lsl #4]" + + - + input: + bytes: [ 0x21, 0x48, 0xfa, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za1h.q[w14, 0]}, p2, [x1, x26, lsl #4]" + + - + input: + bytes: [ 0xcd, 0x0a, 0xfe, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za13h.q[w12, 0]}, p2, [x22, x30, lsl #4]" + + - + input: + bytes: [ 0x22, 0x75, 0xe1, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za2h.q[w15, 0]}, p5, [x9, x1, lsl #4]" + + - + input: + bytes: [ 0x87, 0x29, 0xeb, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za7h.q[w13, 0]}, p2, [x12, x11, lsl #4]" + + - + input: + bytes: [ 0x00, 0x00, 0xe0, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za0h.q[w12, 0]}, p0, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x45, 0x55, 0xf5, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za5h.q[w14, 0]}, p5, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xa7, 0x6d, 0xe8, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za7h.q[w15, 0]}, p3, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0xef, 0x7f, 0xff, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za15h.q[w15, 0]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0xf0, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za5h.q[w12, 0]}, p3, [x17, x16, lsl #4]" + + - + input: + bytes: [ 0x21, 0x04, 0xfe, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za1h.q[w12, 0]}, p1, [x1, x30, lsl #4]" + + - + input: + bytes: [ 0x68, 0x56, 0xf4, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za8h.q[w14, 0]}, p5, [x19, x20, lsl #4]" + + - + input: + bytes: [ 0x80, 0x19, 0xe2, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za0h.q[w12, 0]}, p6, [x12, x2, lsl #4]" + + - + input: + bytes: [ 0x21, 0x48, 0xfa, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za1h.q[w14, 0]}, p2, [x1, x26, lsl #4]" + + - + input: + bytes: [ 0xcd, 0x0a, 0xfe, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za13h.q[w12, 0]}, p2, [x22, x30, lsl #4]" + + - + input: + bytes: [ 0x22, 0x75, 0xe1, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za2h.q[w15, 0]}, p5, [x9, x1, lsl #4]" + + - + input: + bytes: [ 0x87, 0x29, 0xeb, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za7h.q[w13, 0]}, p2, [x12, x11, lsl #4]" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za0v.q[w12, 0]}, p0, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x45, 0xd5, 0xf5, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za5v.q[w14, 0]}, p5, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xa7, 0xed, 0xe8, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za7v.q[w15, 0]}, p3, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0xef, 0xff, 0xff, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za15v.q[w15, 0]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0xf0, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za5v.q[w12, 0]}, p3, [x17, x16, lsl #4]" + + - + input: + bytes: [ 0x21, 0x84, 0xfe, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za1v.q[w12, 0]}, p1, [x1, x30, lsl #4]" + + - + input: + bytes: [ 0x68, 0xd6, 0xf4, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za8v.q[w14, 0]}, p5, [x19, x20, lsl #4]" + + - + input: + bytes: [ 0x80, 0x99, 0xe2, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za0v.q[w12, 0]}, p6, [x12, x2, lsl #4]" + + - + input: + bytes: [ 0x21, 0xc8, 0xfa, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za1v.q[w14, 0]}, p2, [x1, x26, lsl #4]" + + - + input: + bytes: [ 0xcd, 0x8a, 0xfe, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za13v.q[w12, 0]}, p2, [x22, x30, lsl #4]" + + - + input: + bytes: [ 0x22, 0xf5, 0xe1, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za2v.q[w15, 0]}, p5, [x9, x1, lsl #4]" + + - + input: + bytes: [ 0x87, 0xa9, 0xeb, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za7v.q[w13, 0]}, p2, [x12, x11, lsl #4]" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za0v.q[w12, 0]}, p0, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x45, 0xd5, 0xf5, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za5v.q[w14, 0]}, p5, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xa7, 0xed, 0xe8, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za7v.q[w15, 0]}, p3, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0xef, 0xff, 0xff, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za15v.q[w15, 0]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0xf0, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za5v.q[w12, 0]}, p3, [x17, x16, lsl #4]" + + - + input: + bytes: [ 0x21, 0x84, 0xfe, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za1v.q[w12, 0]}, p1, [x1, x30, lsl #4]" + + - + input: + bytes: [ 0x68, 0xd6, 0xf4, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za8v.q[w14, 0]}, p5, [x19, x20, lsl #4]" + + - + input: + bytes: [ 0x80, 0x99, 0xe2, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za0v.q[w12, 0]}, p6, [x12, x2, lsl #4]" + + - + input: + bytes: [ 0x21, 0xc8, 0xfa, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za1v.q[w14, 0]}, p2, [x1, x26, lsl #4]" + + - + input: + bytes: [ 0xcd, 0x8a, 0xfe, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za13v.q[w12, 0]}, p2, [x22, x30, lsl #4]" + + - + input: + bytes: [ 0x22, 0xf5, 0xe1, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za2v.q[w15, 0]}, p5, [x9, x1, lsl #4]" + + - + input: + bytes: [ 0x87, 0xa9, 0xeb, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1q {za7v.q[w13, 0]}, p2, [x12, x11, lsl #4]" diff --git a/tests/MC/AArch64/SME/st1w.s.yaml b/tests/MC/AArch64/SME/st1w.s.yaml new file mode 100644 index 0000000000..75d270c022 --- /dev/null +++ b/tests/MC/AArch64/SME/st1w.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xa0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0h.s[w12, 0]}, p0, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x45, 0x55, 0xb5, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za1h.s[w14, 1]}, p5, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xa7, 0x6d, 0xa8, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za1h.s[w15, 3]}, p3, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xef, 0x7f, 0xbf, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za3h.s[w15, 3]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0xb0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za1h.s[w12, 1]}, p3, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x21, 0x04, 0xbe, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0h.s[w12, 1]}, p1, [x1, x30, lsl #2]" + + - + input: + bytes: [ 0x68, 0x56, 0xb4, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za2h.s[w14, 0]}, p5, [x19, x20, lsl #2]" + + - + input: + bytes: [ 0x80, 0x19, 0xa2, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0h.s[w12, 0]}, p6, [x12, x2, lsl #2]" + + - + input: + bytes: [ 0x21, 0x48, 0xba, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0h.s[w14, 1]}, p2, [x1, x26, lsl #2]" + + - + input: + bytes: [ 0xcd, 0x0a, 0xbe, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za3h.s[w12, 1]}, p2, [x22, x30, lsl #2]" + + - + input: + bytes: [ 0x22, 0x75, 0xa1, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0h.s[w15, 2]}, p5, [x9, x1, lsl #2]" + + - + input: + bytes: [ 0x87, 0x29, 0xab, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za1h.s[w13, 3]}, p2, [x12, x11, lsl #2]" + + - + input: + bytes: [ 0x00, 0x00, 0xa0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0h.s[w12, 0]}, p0, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x45, 0x55, 0xb5, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za1h.s[w14, 1]}, p5, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xa7, 0x6d, 0xa8, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za1h.s[w15, 3]}, p3, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xef, 0x7f, 0xbf, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za3h.s[w15, 3]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x0e, 0xb0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za1h.s[w12, 1]}, p3, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x21, 0x04, 0xbe, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0h.s[w12, 1]}, p1, [x1, x30, lsl #2]" + + - + input: + bytes: [ 0x68, 0x56, 0xb4, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za2h.s[w14, 0]}, p5, [x19, x20, lsl #2]" + + - + input: + bytes: [ 0x80, 0x19, 0xa2, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0h.s[w12, 0]}, p6, [x12, x2, lsl #2]" + + - + input: + bytes: [ 0x21, 0x48, 0xba, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0h.s[w14, 1]}, p2, [x1, x26, lsl #2]" + + - + input: + bytes: [ 0xcd, 0x0a, 0xbe, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za3h.s[w12, 1]}, p2, [x22, x30, lsl #2]" + + - + input: + bytes: [ 0x22, 0x75, 0xa1, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0h.s[w15, 2]}, p5, [x9, x1, lsl #2]" + + - + input: + bytes: [ 0x87, 0x29, 0xab, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za1h.s[w13, 3]}, p2, [x12, x11, lsl #2]" + + - + input: + bytes: [ 0x00, 0x80, 0xa0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0v.s[w12, 0]}, p0, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x45, 0xd5, 0xb5, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za1v.s[w14, 1]}, p5, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xa7, 0xed, 0xa8, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za1v.s[w15, 3]}, p3, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xef, 0xff, 0xbf, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za3v.s[w15, 3]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0xb0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za1v.s[w12, 1]}, p3, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x21, 0x84, 0xbe, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0v.s[w12, 1]}, p1, [x1, x30, lsl #2]" + + - + input: + bytes: [ 0x68, 0xd6, 0xb4, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za2v.s[w14, 0]}, p5, [x19, x20, lsl #2]" + + - + input: + bytes: [ 0x80, 0x99, 0xa2, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0v.s[w12, 0]}, p6, [x12, x2, lsl #2]" + + - + input: + bytes: [ 0x21, 0xc8, 0xba, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0v.s[w14, 1]}, p2, [x1, x26, lsl #2]" + + - + input: + bytes: [ 0xcd, 0x8a, 0xbe, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za3v.s[w12, 1]}, p2, [x22, x30, lsl #2]" + + - + input: + bytes: [ 0x22, 0xf5, 0xa1, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0v.s[w15, 2]}, p5, [x9, x1, lsl #2]" + + - + input: + bytes: [ 0x87, 0xa9, 0xab, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za1v.s[w13, 3]}, p2, [x12, x11, lsl #2]" + + - + input: + bytes: [ 0x00, 0x80, 0xa0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0v.s[w12, 0]}, p0, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x45, 0xd5, 0xb5, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za1v.s[w14, 1]}, p5, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xa7, 0xed, 0xa8, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za1v.s[w15, 3]}, p3, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xef, 0xff, 0xbf, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za3v.s[w15, 3]}, p7, [sp]" + + - + input: + bytes: [ 0x25, 0x8e, 0xb0, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za1v.s[w12, 1]}, p3, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x21, 0x84, 0xbe, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0v.s[w12, 1]}, p1, [x1, x30, lsl #2]" + + - + input: + bytes: [ 0x68, 0xd6, 0xb4, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za2v.s[w14, 0]}, p5, [x19, x20, lsl #2]" + + - + input: + bytes: [ 0x80, 0x99, 0xa2, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0v.s[w12, 0]}, p6, [x12, x2, lsl #2]" + + - + input: + bytes: [ 0x21, 0xc8, 0xba, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0v.s[w14, 1]}, p2, [x1, x26, lsl #2]" + + - + input: + bytes: [ 0xcd, 0x8a, 0xbe, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za3v.s[w12, 1]}, p2, [x22, x30, lsl #2]" + + - + input: + bytes: [ 0x22, 0xf5, 0xa1, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za0v.s[w15, 2]}, p5, [x9, x1, lsl #2]" + + - + input: + bytes: [ 0x87, 0xa9, 0xab, 0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w {za1v.s[w13, 3]}, p2, [x12, x11, lsl #2]" diff --git a/tests/MC/AArch64/SME/str.s.yaml b/tests/MC/AArch64/SME/str.s.yaml new file mode 100644 index 0000000000..3652fbc112 --- /dev/null +++ b/tests/MC/AArch64/SME/str.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x20, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str za[w12, 0], [x0]" + + - + input: + bytes: [ 0x45, 0x41, 0x20, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str za[w14, 5], [x10, #5, mul vl]" + + - + input: + bytes: [ 0xa7, 0x61, 0x20, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str za[w15, 7], [x13, #7, mul vl]" + + - + input: + bytes: [ 0xef, 0x63, 0x20, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str za[w15, 15], [sp, #15, mul vl]" + + - + input: + bytes: [ 0x25, 0x02, 0x20, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str za[w12, 5], [x17, #5, mul vl]" + + - + input: + bytes: [ 0x21, 0x00, 0x20, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str za[w12, 1], [x1, #1, mul vl]" + + - + input: + bytes: [ 0x68, 0x42, 0x20, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str za[w14, 8], [x19, #8, mul vl]" + + - + input: + bytes: [ 0x80, 0x01, 0x20, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str za[w12, 0], [x12]" + + - + input: + bytes: [ 0x21, 0x40, 0x20, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str za[w14, 1], [x1, #1, mul vl]" + + - + input: + bytes: [ 0xcd, 0x02, 0x20, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str za[w12, 13], [x22, #13, mul vl]" + + - + input: + bytes: [ 0x22, 0x61, 0x20, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str za[w15, 2], [x9, #2, mul vl]" + + - + input: + bytes: [ 0x87, 0x21, 0x20, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str za[w13, 7], [x12, #7, mul vl]" diff --git a/tests/MC/AArch64/SME/streaming-mode-neon-bf16.s.yaml b/tests/MC/AArch64/SME/streaming-mode-neon-bf16.s.yaml new file mode 100644 index 0000000000..71fa19e0b6 --- /dev/null +++ b/tests/MC/AArch64/SME/streaming-mode-neon-bf16.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x65, 0x40, 0x63, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "bfcvt h5, s3" diff --git a/tests/MC/AArch64/SME/streaming-mode-neon-fp16.s.yaml b/tests/MC/AArch64/SME/streaming-mode-neon-fp16.s.yaml new file mode 100644 index 0000000000..1847441e89 --- /dev/null +++ b/tests/MC/AArch64/SME/streaming-mode-neon-fp16.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x1c, 0x42, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmulx h0, h1, h2" + + - + input: + bytes: [ 0x20, 0x3c, 0x42, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecps h0, h1, h2" + + - + input: + bytes: [ 0x20, 0x3c, 0xc2, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+fullfp16" ] + expected: + insns: + - + asm_text: "frsqrts h0, h1, h2" + + - + input: + bytes: [ 0x20, 0xd8, 0xf9, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecpe h0, h1" + + - + input: + bytes: [ 0x20, 0xf8, 0xf9, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecpx h0, h1" + + - + input: + bytes: [ 0x20, 0xd8, 0xf9, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+fullfp16" ] + expected: + insns: + - + asm_text: "frsqrte h0, h1" diff --git a/tests/MC/AArch64/SME/streaming-mode-neon.s.yaml b/tests/MC/AArch64/SME/streaming-mode-neon.s.yaml new file mode 100644 index 0000000000..f6addaab30 --- /dev/null +++ b/tests/MC/AArch64/SME/streaming-mode-neon.s.yaml @@ -0,0 +1,230 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xdc, 0x22, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "fmulx s0, s1, s2" + + - + input: + bytes: [ 0x20, 0xdc, 0x62, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "fmulx d0, d1, d2" + + - + input: + bytes: [ 0x20, 0xfc, 0x22, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "frecps s0, s1, s2" + + - + input: + bytes: [ 0x20, 0xfc, 0x62, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "frecps d0, d1, d2" + + - + input: + bytes: [ 0x20, 0xfc, 0xa2, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "frsqrts s0, s1, s2" + + - + input: + bytes: [ 0x20, 0xfc, 0xe2, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "frsqrts d0, d1, d2" + + - + input: + bytes: [ 0x20, 0xd8, 0xa1, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "frecpe s0, s1" + + - + input: + bytes: [ 0x20, 0xd8, 0xe1, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "frecpe d0, d1" + + - + input: + bytes: [ 0x20, 0xf8, 0xa1, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "frecpx s0, s1" + + - + input: + bytes: [ 0x20, 0xf8, 0xe1, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "frecpx d0, d1" + + - + input: + bytes: [ 0x20, 0xd8, 0xa1, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "frsqrte s0, s1" + + - + input: + bytes: [ 0x20, 0xd8, 0xe1, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "frsqrte d0, d1" + + - + input: + bytes: [ 0x00, 0x2c, 0x01, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "smov w0, v0.b[0]" + + - + input: + bytes: [ 0x00, 0x2c, 0x01, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "smov x0, v0.b[0]" + + - + input: + bytes: [ 0x00, 0x2c, 0x02, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "smov w0, v0.h[0]" + + - + input: + bytes: [ 0x00, 0x2c, 0x02, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "smov x0, v0.h[0]" + + - + input: + bytes: [ 0x00, 0x2c, 0x04, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "smov x0, v0.s[0]" + + - + input: + bytes: [ 0x00, 0x3c, 0x01, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "umov w0, v0.b[0]" + + - + input: + bytes: [ 0x00, 0x3c, 0x02, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "umov w0, v0.h[0]" + + - + input: + bytes: [ 0x00, 0x3c, 0x04, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "mov w0, v0.s[0]" + + - + input: + bytes: [ 0x00, 0x3c, 0x08, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "mov x0, v0.d[0]" + + - + input: + bytes: [ 0x00, 0x3c, 0x04, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "mov w0, v0.s[0]" + + - + input: + bytes: [ 0x00, 0x3c, 0x08, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ] + expected: + insns: + - + asm_text: "mov x0, v0.d[0]" diff --git a/tests/MC/AArch64/SME/sumopa-32.s.yaml b/tests/MC/AArch64/SME/sumopa-32.s.yaml new file mode 100644 index 0000000000..52c5a05e65 --- /dev/null +++ b/tests/MC/AArch64/SME/sumopa-32.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xa0, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumopa za0.s, p0/m, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x41, 0x55, 0xb5, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumopa za1.s, p5/m, p2/m, z10.b, z21.b" + + - + input: + bytes: [ 0xa3, 0xed, 0xa8, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumopa za3.s, p3/m, p7/m, z13.b, z8.b" + + - + input: + bytes: [ 0xe3, 0xff, 0xbf, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumopa za3.s, p7/m, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0x21, 0x0e, 0xb0, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumopa za1.s, p3/m, p0/m, z17.b, z16.b" + + - + input: + bytes: [ 0x21, 0x84, 0xbe, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumopa za1.s, p1/m, p4/m, z1.b, z30.b" + + - + input: + bytes: [ 0x60, 0x56, 0xb4, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumopa za0.s, p5/m, p2/m, z19.b, z20.b" + + - + input: + bytes: [ 0x80, 0x19, 0xa2, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumopa za0.s, p6/m, p0/m, z12.b, z2.b" + + - + input: + bytes: [ 0x21, 0xc8, 0xba, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumopa za1.s, p2/m, p6/m, z1.b, z26.b" + + - + input: + bytes: [ 0xc1, 0x0a, 0xbe, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumopa za1.s, p2/m, p0/m, z22.b, z30.b" + + - + input: + bytes: [ 0x22, 0xf5, 0xa1, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumopa za2.s, p5/m, p7/m, z9.b, z1.b" + + - + input: + bytes: [ 0x83, 0xa9, 0xab, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumopa za3.s, p2/m, p5/m, z12.b, z11.b" diff --git a/tests/MC/AArch64/SME/sumopa-64.s.yaml b/tests/MC/AArch64/SME/sumopa-64.s.yaml new file mode 100644 index 0000000000..5b69c39e45 --- /dev/null +++ b/tests/MC/AArch64/SME/sumopa-64.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xe0, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumopa za0.d, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x45, 0x55, 0xf5, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumopa za5.d, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xa7, 0xed, 0xe8, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumopa za7.d, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumopa za7.d, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x25, 0x0e, 0xf0, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumopa za5.d, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x21, 0x84, 0xfe, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumopa za1.d, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x60, 0x56, 0xf4, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumopa za0.d, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x80, 0x19, 0xe2, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumopa za0.d, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x21, 0xc8, 0xfa, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumopa za1.d, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xc5, 0x0a, 0xfe, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumopa za5.d, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x22, 0xf5, 0xe1, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumopa za2.d, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x87, 0xa9, 0xeb, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumopa za7.d, p2/m, p5/m, z12.h, z11.h" diff --git a/tests/MC/AArch64/SME/sumops-32.s.yaml b/tests/MC/AArch64/SME/sumops-32.s.yaml new file mode 100644 index 0000000000..bf4019d862 --- /dev/null +++ b/tests/MC/AArch64/SME/sumops-32.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x00, 0xa0, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumops za0.s, p0/m, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x51, 0x55, 0xb5, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumops za1.s, p5/m, p2/m, z10.b, z21.b" + + - + input: + bytes: [ 0xb3, 0xed, 0xa8, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumops za3.s, p3/m, p7/m, z13.b, z8.b" + + - + input: + bytes: [ 0xf3, 0xff, 0xbf, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumops za3.s, p7/m, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0x31, 0x0e, 0xb0, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumops za1.s, p3/m, p0/m, z17.b, z16.b" + + - + input: + bytes: [ 0x31, 0x84, 0xbe, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumops za1.s, p1/m, p4/m, z1.b, z30.b" + + - + input: + bytes: [ 0x70, 0x56, 0xb4, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumops za0.s, p5/m, p2/m, z19.b, z20.b" + + - + input: + bytes: [ 0x90, 0x19, 0xa2, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumops za0.s, p6/m, p0/m, z12.b, z2.b" + + - + input: + bytes: [ 0x31, 0xc8, 0xba, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumops za1.s, p2/m, p6/m, z1.b, z26.b" + + - + input: + bytes: [ 0xd1, 0x0a, 0xbe, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumops za1.s, p2/m, p0/m, z22.b, z30.b" + + - + input: + bytes: [ 0x32, 0xf5, 0xa1, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumops za2.s, p5/m, p7/m, z9.b, z1.b" + + - + input: + bytes: [ 0x93, 0xa9, 0xab, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sumops za3.s, p2/m, p5/m, z12.b, z11.b" diff --git a/tests/MC/AArch64/SME/sumops-64.s.yaml b/tests/MC/AArch64/SME/sumops-64.s.yaml new file mode 100644 index 0000000000..e4af650b61 --- /dev/null +++ b/tests/MC/AArch64/SME/sumops-64.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x00, 0xe0, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumops za0.d, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x55, 0xf5, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumops za5.d, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xed, 0xe8, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumops za7.d, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xf7, 0xff, 0xff, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumops za7.d, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x35, 0x0e, 0xf0, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumops za5.d, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x31, 0x84, 0xfe, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumops za1.d, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x70, 0x56, 0xf4, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumops za0.d, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x90, 0x19, 0xe2, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumops za0.d, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x31, 0xc8, 0xfa, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumops za1.d, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xd5, 0x0a, 0xfe, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumops za5.d, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x32, 0xf5, 0xe1, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumops za2.d, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x97, 0xa9, 0xeb, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "sumops za7.d, p2/m, p5/m, z12.h, z11.h" diff --git a/tests/MC/AArch64/SME/system-regs-mpam.s.yaml b/tests/MC/AArch64/SME/system-regs-mpam.s.yaml new file mode 100644 index 0000000000..0310094cf5 --- /dev/null +++ b/tests/MC/AArch64/SME/system-regs-mpam.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x63, 0xa5, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+mpam" ] + expected: + insns: + - + asm_text: "mrs x3, MPAMSM_EL1" + + - + input: + bytes: [ 0x63, 0xa5, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+mpam" ] + expected: + insns: + - + asm_text: "msr MPAMSM_EL1, x3" diff --git a/tests/MC/AArch64/SME/system-regs.s.yaml b/tests/MC/AArch64/SME/system-regs.s.yaml new file mode 100644 index 0000000000..23e8847e68 --- /dev/null +++ b/tests/MC/AArch64/SME/system-regs.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0xa3, 0x04, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mrs x3, ID_AA64SMFR0_EL1" + + - + input: + bytes: [ 0xc3, 0x12, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mrs x3, SMCR_EL1" + + - + input: + bytes: [ 0xc3, 0x12, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mrs x3, SMCR_EL2" + + - + input: + bytes: [ 0xc3, 0x12, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mrs x3, SMCR_EL3" + + - + input: + bytes: [ 0xc3, 0x12, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mrs x3, SMCR_EL12" + + - + input: + bytes: [ 0x43, 0x42, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mrs x3, SVCR" + + - + input: + bytes: [ 0x83, 0x12, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mrs x3, SMPRI_EL1" + + - + input: + bytes: [ 0xa3, 0x12, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mrs x3, SMPRIMAP_EL2" + + - + input: + bytes: [ 0xc3, 0x00, 0x39, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mrs x3, SMIDR_EL1" + + - + input: + bytes: [ 0xa3, 0xd0, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mrs x3, TPIDR2_EL0" + + - + input: + bytes: [ 0xc3, 0x12, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "msr SMCR_EL1, x3" + + - + input: + bytes: [ 0xc3, 0x12, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "msr SMCR_EL2, x3" + + - + input: + bytes: [ 0xc3, 0x12, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "msr SMCR_EL3, x3" + + - + input: + bytes: [ 0xc3, 0x12, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "msr SMCR_EL12, x3" + + - + input: + bytes: [ 0x43, 0x42, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "msr SVCR, x3" + + - + input: + bytes: [ 0x83, 0x12, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "msr SMPRI_EL1, x3" + + - + input: + bytes: [ 0xa3, 0x12, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "msr SMPRIMAP_EL2, x3" + + - + input: + bytes: [ 0x7f, 0x42, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smstop sm" + + - + input: + bytes: [ 0x7f, 0x43, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smstart sm" + + - + input: + bytes: [ 0x7f, 0x44, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smstop za" + + - + input: + bytes: [ 0x7f, 0x45, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smstart za" + + - + input: + bytes: [ 0x7f, 0x46, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smstop" + + - + input: + bytes: [ 0x7f, 0x47, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smstart" + + - + input: + bytes: [ 0xa3, 0xd0, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "msr TPIDR2_EL0, x3" diff --git a/tests/MC/AArch64/SME/uclamp.s.yaml b/tests/MC/AArch64/SME/uclamp.s.yaml new file mode 100644 index 0000000000..629c08ce60 --- /dev/null +++ b/tests/MC/AArch64/SME/uclamp.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc4, 0x00, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x55, 0xc5, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z21.b, z10.b, z21.b" + + - + input: + bytes: [ 0xb7, 0xc5, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z23.b, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0xc7, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0xc4, 0x40, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xc5, 0x55, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xc5, 0x48, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xc7, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0xc4, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x55, 0xc5, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z21.s, z10.s, z21.s" + + - + input: + bytes: [ 0xb7, 0xc5, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0xff, 0xc7, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0xc4, 0xc0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x55, 0xc5, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z21.d, z10.d, z21.d" + + - + input: + bytes: [ 0xb7, 0xc5, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0xc7, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x77, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z23, z27" + + - + input: + bytes: [ 0xb7, 0xc5, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z23.b, z13.b, z8.b" + + - + input: + bytes: [ 0x77, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z23, z27" + + - + input: + bytes: [ 0xb7, 0xc5, 0x48, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0x77, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z23, z27" + + - + input: + bytes: [ 0xb7, 0xc5, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0x77, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z23, z27" + + - + input: + bytes: [ 0xb7, 0xc5, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uclamp z23.d, z13.d, z8.d" diff --git a/tests/MC/AArch64/SME/umopa-32.s.yaml b/tests/MC/AArch64/SME/umopa-32.s.yaml new file mode 100644 index 0000000000..8bc7af7bd5 --- /dev/null +++ b/tests/MC/AArch64/SME/umopa-32.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xa0, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umopa za0.s, p0/m, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x41, 0x55, 0xb5, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umopa za1.s, p5/m, p2/m, z10.b, z21.b" + + - + input: + bytes: [ 0xa3, 0xed, 0xa8, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umopa za3.s, p3/m, p7/m, z13.b, z8.b" + + - + input: + bytes: [ 0xe3, 0xff, 0xbf, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umopa za3.s, p7/m, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0x21, 0x0e, 0xb0, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umopa za1.s, p3/m, p0/m, z17.b, z16.b" + + - + input: + bytes: [ 0x21, 0x84, 0xbe, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umopa za1.s, p1/m, p4/m, z1.b, z30.b" + + - + input: + bytes: [ 0x60, 0x56, 0xb4, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umopa za0.s, p5/m, p2/m, z19.b, z20.b" + + - + input: + bytes: [ 0x80, 0x19, 0xa2, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umopa za0.s, p6/m, p0/m, z12.b, z2.b" + + - + input: + bytes: [ 0x21, 0xc8, 0xba, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umopa za1.s, p2/m, p6/m, z1.b, z26.b" + + - + input: + bytes: [ 0xc1, 0x0a, 0xbe, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umopa za1.s, p2/m, p0/m, z22.b, z30.b" + + - + input: + bytes: [ 0x22, 0xf5, 0xa1, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umopa za2.s, p5/m, p7/m, z9.b, z1.b" + + - + input: + bytes: [ 0x83, 0xa9, 0xab, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umopa za3.s, p2/m, p5/m, z12.b, z11.b" diff --git a/tests/MC/AArch64/SME/umopa-64.s.yaml b/tests/MC/AArch64/SME/umopa-64.s.yaml new file mode 100644 index 0000000000..dd12efabc4 --- /dev/null +++ b/tests/MC/AArch64/SME/umopa-64.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xe0, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umopa za0.d, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x45, 0x55, 0xf5, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umopa za5.d, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xa7, 0xed, 0xe8, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umopa za7.d, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umopa za7.d, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x25, 0x0e, 0xf0, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umopa za5.d, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x21, 0x84, 0xfe, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umopa za1.d, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x60, 0x56, 0xf4, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umopa za0.d, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x80, 0x19, 0xe2, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umopa za0.d, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x21, 0xc8, 0xfa, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umopa za1.d, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xc5, 0x0a, 0xfe, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umopa za5.d, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x22, 0xf5, 0xe1, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umopa za2.d, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x87, 0xa9, 0xeb, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umopa za7.d, p2/m, p5/m, z12.h, z11.h" diff --git a/tests/MC/AArch64/SME/umops-32.s.yaml b/tests/MC/AArch64/SME/umops-32.s.yaml new file mode 100644 index 0000000000..d92c8230f2 --- /dev/null +++ b/tests/MC/AArch64/SME/umops-32.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x00, 0xa0, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umops za0.s, p0/m, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x51, 0x55, 0xb5, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umops za1.s, p5/m, p2/m, z10.b, z21.b" + + - + input: + bytes: [ 0xb3, 0xed, 0xa8, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umops za3.s, p3/m, p7/m, z13.b, z8.b" + + - + input: + bytes: [ 0xf3, 0xff, 0xbf, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umops za3.s, p7/m, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0x31, 0x0e, 0xb0, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umops za1.s, p3/m, p0/m, z17.b, z16.b" + + - + input: + bytes: [ 0x31, 0x84, 0xbe, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umops za1.s, p1/m, p4/m, z1.b, z30.b" + + - + input: + bytes: [ 0x70, 0x56, 0xb4, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umops za0.s, p5/m, p2/m, z19.b, z20.b" + + - + input: + bytes: [ 0x90, 0x19, 0xa2, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umops za0.s, p6/m, p0/m, z12.b, z2.b" + + - + input: + bytes: [ 0x31, 0xc8, 0xba, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umops za1.s, p2/m, p6/m, z1.b, z26.b" + + - + input: + bytes: [ 0xd1, 0x0a, 0xbe, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umops za1.s, p2/m, p0/m, z22.b, z30.b" + + - + input: + bytes: [ 0x32, 0xf5, 0xa1, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umops za2.s, p5/m, p7/m, z9.b, z1.b" + + - + input: + bytes: [ 0x93, 0xa9, 0xab, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umops za3.s, p2/m, p5/m, z12.b, z11.b" diff --git a/tests/MC/AArch64/SME/umops-64.s.yaml b/tests/MC/AArch64/SME/umops-64.s.yaml new file mode 100644 index 0000000000..347449d0c7 --- /dev/null +++ b/tests/MC/AArch64/SME/umops-64.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x00, 0xe0, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umops za0.d, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x55, 0xf5, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umops za5.d, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xed, 0xe8, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umops za7.d, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xf7, 0xff, 0xff, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umops za7.d, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x35, 0x0e, 0xf0, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umops za5.d, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x31, 0x84, 0xfe, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umops za1.d, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x70, 0x56, 0xf4, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umops za0.d, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x90, 0x19, 0xe2, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umops za0.d, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x31, 0xc8, 0xfa, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umops za1.d, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xd5, 0x0a, 0xfe, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umops za5.d, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x32, 0xf5, 0xe1, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umops za2.d, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x97, 0xa9, 0xeb, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "umops za7.d, p2/m, p5/m, z12.h, z11.h" diff --git a/tests/MC/AArch64/SME/usmopa-32.s.yaml b/tests/MC/AArch64/SME/usmopa-32.s.yaml new file mode 100644 index 0000000000..62a3437bec --- /dev/null +++ b/tests/MC/AArch64/SME/usmopa-32.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x80, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmopa za0.s, p0/m, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x41, 0x55, 0x95, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmopa za1.s, p5/m, p2/m, z10.b, z21.b" + + - + input: + bytes: [ 0xa3, 0xed, 0x88, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmopa za3.s, p3/m, p7/m, z13.b, z8.b" + + - + input: + bytes: [ 0xe3, 0xff, 0x9f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmopa za3.s, p7/m, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0x21, 0x0e, 0x90, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmopa za1.s, p3/m, p0/m, z17.b, z16.b" + + - + input: + bytes: [ 0x21, 0x84, 0x9e, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmopa za1.s, p1/m, p4/m, z1.b, z30.b" + + - + input: + bytes: [ 0x60, 0x56, 0x94, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmopa za0.s, p5/m, p2/m, z19.b, z20.b" + + - + input: + bytes: [ 0x80, 0x19, 0x82, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmopa za0.s, p6/m, p0/m, z12.b, z2.b" + + - + input: + bytes: [ 0x21, 0xc8, 0x9a, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmopa za1.s, p2/m, p6/m, z1.b, z26.b" + + - + input: + bytes: [ 0xc1, 0x0a, 0x9e, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmopa za1.s, p2/m, p0/m, z22.b, z30.b" + + - + input: + bytes: [ 0x22, 0xf5, 0x81, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmopa za2.s, p5/m, p7/m, z9.b, z1.b" + + - + input: + bytes: [ 0x83, 0xa9, 0x8b, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmopa za3.s, p2/m, p5/m, z12.b, z11.b" diff --git a/tests/MC/AArch64/SME/usmopa-64.s.yaml b/tests/MC/AArch64/SME/usmopa-64.s.yaml new file mode 100644 index 0000000000..0e8f364b6a --- /dev/null +++ b/tests/MC/AArch64/SME/usmopa-64.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmopa za0.d, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x45, 0x55, 0xd5, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmopa za5.d, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xa7, 0xed, 0xc8, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmopa za7.d, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xe7, 0xff, 0xdf, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmopa za7.d, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x25, 0x0e, 0xd0, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmopa za5.d, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x21, 0x84, 0xde, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmopa za1.d, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x60, 0x56, 0xd4, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmopa za0.d, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x80, 0x19, 0xc2, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmopa za0.d, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x21, 0xc8, 0xda, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmopa za1.d, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xc5, 0x0a, 0xde, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmopa za5.d, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x22, 0xf5, 0xc1, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmopa za2.d, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x87, 0xa9, 0xcb, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmopa za7.d, p2/m, p5/m, z12.h, z11.h" diff --git a/tests/MC/AArch64/SME/usmops-32.s.yaml b/tests/MC/AArch64/SME/usmops-32.s.yaml new file mode 100644 index 0000000000..0d52f8bef9 --- /dev/null +++ b/tests/MC/AArch64/SME/usmops-32.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x00, 0x80, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmops za0.s, p0/m, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x51, 0x55, 0x95, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmops za1.s, p5/m, p2/m, z10.b, z21.b" + + - + input: + bytes: [ 0xb3, 0xed, 0x88, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmops za3.s, p3/m, p7/m, z13.b, z8.b" + + - + input: + bytes: [ 0xf3, 0xff, 0x9f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmops za3.s, p7/m, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0x31, 0x0e, 0x90, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmops za1.s, p3/m, p0/m, z17.b, z16.b" + + - + input: + bytes: [ 0x31, 0x84, 0x9e, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmops za1.s, p1/m, p4/m, z1.b, z30.b" + + - + input: + bytes: [ 0x70, 0x56, 0x94, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmops za0.s, p5/m, p2/m, z19.b, z20.b" + + - + input: + bytes: [ 0x90, 0x19, 0x82, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmops za0.s, p6/m, p0/m, z12.b, z2.b" + + - + input: + bytes: [ 0x31, 0xc8, 0x9a, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmops za1.s, p2/m, p6/m, z1.b, z26.b" + + - + input: + bytes: [ 0xd1, 0x0a, 0x9e, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmops za1.s, p2/m, p0/m, z22.b, z30.b" + + - + input: + bytes: [ 0x32, 0xf5, 0x81, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmops za2.s, p5/m, p7/m, z9.b, z1.b" + + - + input: + bytes: [ 0x93, 0xa9, 0x8b, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usmops za3.s, p2/m, p5/m, z12.b, z11.b" diff --git a/tests/MC/AArch64/SME/usmops-64.s.yaml b/tests/MC/AArch64/SME/usmops-64.s.yaml new file mode 100644 index 0000000000..e6cc96e0b6 --- /dev/null +++ b/tests/MC/AArch64/SME/usmops-64.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x00, 0xc0, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmops za0.d, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x55, 0xd5, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmops za5.d, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xed, 0xc8, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmops za7.d, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xf7, 0xff, 0xdf, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmops za7.d, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x35, 0x0e, 0xd0, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmops za5.d, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x31, 0x84, 0xde, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmops za1.d, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x70, 0x56, 0xd4, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmops za0.d, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x90, 0x19, 0xc2, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmops za0.d, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x31, 0xc8, 0xda, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmops za1.d, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xd5, 0x0a, 0xde, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmops za5.d, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x32, 0xf5, 0xc1, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmops za2.d, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x97, 0xa9, 0xcb, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ] + expected: + insns: + - + asm_text: "usmops za7.d, p2/m, p5/m, z12.h, z11.h" diff --git a/tests/MC/AArch64/SME/zero.s.yaml b/tests/MC/AArch64/SME/zero.s.yaml new file mode 100644 index 0000000000..299fe3c397 --- /dev/null +++ b/tests/MC/AArch64/SME/zero.s.yaml @@ -0,0 +1,390 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {}" + + - + input: + bytes: [ 0x55, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za0.h}" + + - + input: + bytes: [ 0xb7, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za0.d, za1.d, za2.d, za4.d, za5.d, za7.d}" + + - + input: + bytes: [ 0xff, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za}" + + - + input: + bytes: [ 0xff, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za}" + + - + input: + bytes: [ 0xff, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za}" + + - + input: + bytes: [ 0x55, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za0.h}" + + - + input: + bytes: [ 0xaa, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za1.h}" + + - + input: + bytes: [ 0xff, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za}" + + - + input: + bytes: [ 0x11, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za0.s}" + + - + input: + bytes: [ 0x22, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za1.s}" + + - + input: + bytes: [ 0x44, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za2.s}" + + - + input: + bytes: [ 0x88, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za3.s}" + + - + input: + bytes: [ 0x33, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za0.s,za1.s}" + + - + input: + bytes: [ 0x55, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za0.h}" + + - + input: + bytes: [ 0x99, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za0.s,za3.s}" + + - + input: + bytes: [ 0x66, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za1.s,za2.s}" + + - + input: + bytes: [ 0xaa, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za1.h}" + + - + input: + bytes: [ 0xcc, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za2.s,za3.s}" + + - + input: + bytes: [ 0x77, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za0.s,za1.s,za2.s}" + + - + input: + bytes: [ 0xbb, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za0.s,za1.s,za3.s}" + + - + input: + bytes: [ 0xdd, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za0.s,za2.s,za3.s}" + + - + input: + bytes: [ 0xee, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za1.s,za2.s,za3.s}" + + - + input: + bytes: [ 0xff, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za}" + + - + input: + bytes: [ 0xff, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za}" + + - + input: + bytes: [ 0x55, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za0.h}" + + - + input: + bytes: [ 0xaa, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za1.h}" + + - + input: + bytes: [ 0x11, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za0.s}" + + - + input: + bytes: [ 0x22, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za1.s}" + + - + input: + bytes: [ 0x44, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za2.s}" + + - + input: + bytes: [ 0x88, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za3.s}" + + - + input: + bytes: [ 0x33, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za0.s,za1.s}" + + - + input: + bytes: [ 0x99, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za0.s,za3.s}" + + - + input: + bytes: [ 0x66, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za1.s,za2.s}" + + - + input: + bytes: [ 0xcc, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za2.s,za3.s}" + + - + input: + bytes: [ 0x77, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za0.s,za1.s,za2.s}" + + - + input: + bytes: [ 0xbb, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za0.s,za1.s,za3.s}" + + - + input: + bytes: [ 0xdd, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za0.s,za2.s,za3.s}" + + - + input: + bytes: [ 0xee, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zero {za1.s,za2.s,za3.s}" diff --git a/tests/MC/AArch64/SME2/add.s.yaml b/tests/MC/AArch64/SME2/add.s.yaml new file mode 100644 index 0000000000..23235b57c3 --- /dev/null +++ b/tests/MC/AArch64/SME2/add.s.yaml @@ -0,0 +1,3430 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa3, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z0.h, z1.h }, { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x14, 0xa3, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z20.h, z21.h }, { z20.h, z21.h }, z5.h" + + - + input: + bytes: [ 0x16, 0xa3, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z22.h, z23.h }, { z22.h, z23.h }, z8.h" + + - + input: + bytes: [ 0x1e, 0xa3, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z30.h, z31.h }, { z30.h, z31.h }, z15.h" + + - + input: + bytes: [ 0x10, 0x1c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x10, 0x1c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x55, 0x5d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 5, vgx2], { z10.s, z11.s }" + + - + input: + bytes: [ 0x55, 0x5d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 5, vgx2], { z10.s, z11.s }" + + - + input: + bytes: [ 0x97, 0x7d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0x97, 0x7d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0xd7, 0x7f, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx2], { z30.s, z31.s }" + + - + input: + bytes: [ 0xd7, 0x7f, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx2], { z30.s, z31.s }" + + - + input: + bytes: [ 0x15, 0x1e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx2], { z16.s, z17.s }" + + - + input: + bytes: [ 0x15, 0x1e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx2], { z16.s, z17.s }" + + - + input: + bytes: [ 0x11, 0x1c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 1, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x11, 0x1c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 1, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x50, 0x5e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 0, vgx2], { z18.s, z19.s }" + + - + input: + bytes: [ 0x50, 0x5e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 0, vgx2], { z18.s, z19.s }" + + - + input: + bytes: [ 0x90, 0x1d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0x11, 0x5c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 1, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x11, 0x5c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 1, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0xd5, 0x1e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx2], { z22.s, z23.s }" + + - + input: + bytes: [ 0xd5, 0x1e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx2], { z22.s, z23.s }" + + - + input: + bytes: [ 0x12, 0x7d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 2, vgx2], { z8.s, z9.s }" + + - + input: + bytes: [ 0x12, 0x7d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 2, vgx2], { z8.s, z9.s }" + + - + input: + bytes: [ 0x97, 0x3d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w9, 7, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0x97, 0x3d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w9, 7, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0x10, 0x18, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x10, 0x18, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x55, 0x59, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s" + + - + input: + bytes: [ 0x55, 0x59, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s" + + - + input: + bytes: [ 0xb7, 0x79, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx2], { z13.s, z14.s }, z8.s" + + - + input: + bytes: [ 0xb7, 0x79, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx2], { z13.s, z14.s }, z8.s" + + - + input: + bytes: [ 0xf7, 0x7b, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx2], { z31.s, z0.s }, z15.s" + + - + input: + bytes: [ 0xf7, 0x7b, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx2], { z31.s, z0.s }, z15.s" + + - + input: + bytes: [ 0x35, 0x1a, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx2], { z17.s, z18.s }, z0.s" + + - + input: + bytes: [ 0x35, 0x1a, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx2], { z17.s, z18.s }, z0.s" + + - + input: + bytes: [ 0x31, 0x18, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 1, vgx2], { z1.s, z2.s }, z14.s" + + - + input: + bytes: [ 0x31, 0x18, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 1, vgx2], { z1.s, z2.s }, z14.s" + + - + input: + bytes: [ 0x70, 0x5a, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 0, vgx2], { z19.s, z20.s }, z4.s" + + - + input: + bytes: [ 0x70, 0x5a, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 0, vgx2], { z19.s, z20.s }, z4.s" + + - + input: + bytes: [ 0x90, 0x19, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s" + + - + input: + bytes: [ 0x90, 0x19, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s" + + - + input: + bytes: [ 0x31, 0x58, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 1, vgx2], { z1.s, z2.s }, z10.s" + + - + input: + bytes: [ 0x31, 0x58, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 1, vgx2], { z1.s, z2.s }, z10.s" + + - + input: + bytes: [ 0xd5, 0x1a, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s" + + - + input: + bytes: [ 0xd5, 0x1a, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s" + + - + input: + bytes: [ 0x32, 0x79, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 2, vgx2], { z9.s, z10.s }, z1.s" + + - + input: + bytes: [ 0x32, 0x79, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 2, vgx2], { z9.s, z10.s }, z1.s" + + - + input: + bytes: [ 0x97, 0x39, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s" + + - + input: + bytes: [ 0x97, 0x39, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s" + + - + input: + bytes: [ 0x00, 0xa3, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z0.s, z1.s }, { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x14, 0xa3, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z20.s, z21.s }, { z20.s, z21.s }, z5.s" + + - + input: + bytes: [ 0x16, 0xa3, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z22.s, z23.s }, { z22.s, z23.s }, z8.s" + + - + input: + bytes: [ 0x1e, 0xa3, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z30.s, z31.s }, { z30.s, z31.s }, z15.s" + + - + input: + bytes: [ 0x10, 0x18, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x10, 0x18, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x55, 0x59, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x55, 0x59, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x97, 0x79, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0x97, 0x79, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0xd7, 0x7b, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0xd7, 0x7b, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x15, 0x1a, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }" + + - + input: + bytes: [ 0x15, 0x1a, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }" + + - + input: + bytes: [ 0x11, 0x18, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x11, 0x18, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x50, 0x5a, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x50, 0x5a, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x90, 0x19, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }" + + - + input: + bytes: [ 0x90, 0x19, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }" + + - + input: + bytes: [ 0x11, 0x58, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }" + + - + input: + bytes: [ 0x11, 0x58, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }" + + - + input: + bytes: [ 0xd5, 0x1a, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0xd5, 0x1a, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x12, 0x79, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x12, 0x79, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x97, 0x39, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }" + + - + input: + bytes: [ 0x97, 0x39, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }" + + - + input: + bytes: [ 0x10, 0x1c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x10, 0x1c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x55, 0x5d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 5, vgx2], { z10.d, z11.d }" + + - + input: + bytes: [ 0x55, 0x5d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 5, vgx2], { z10.d, z11.d }" + + - + input: + bytes: [ 0x97, 0x7d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x97, 0x7d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0xd7, 0x7f, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx2], { z30.d, z31.d }" + + - + input: + bytes: [ 0xd7, 0x7f, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx2], { z30.d, z31.d }" + + - + input: + bytes: [ 0x15, 0x1e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx2], { z16.d, z17.d }" + + - + input: + bytes: [ 0x15, 0x1e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx2], { z16.d, z17.d }" + + - + input: + bytes: [ 0x11, 0x1c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x11, 0x1c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x50, 0x5e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 0, vgx2], { z18.d, z19.d }" + + - + input: + bytes: [ 0x50, 0x5e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 0, vgx2], { z18.d, z19.d }" + + - + input: + bytes: [ 0x90, 0x1d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x90, 0x1d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x11, 0x5c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x11, 0x5c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0xd5, 0x1e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx2], { z22.d, z23.d }" + + - + input: + bytes: [ 0xd5, 0x1e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx2], { z22.d, z23.d }" + + - + input: + bytes: [ 0x12, 0x7d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 2, vgx2], { z8.d, z9.d }" + + - + input: + bytes: [ 0x12, 0x7d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 2, vgx2], { z8.d, z9.d }" + + - + input: + bytes: [ 0x97, 0x3d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w9, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x97, 0x3d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w9, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x10, 0x18, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x10, 0x18, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x55, 0x59, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d" + + - + input: + bytes: [ 0x55, 0x59, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d" + + - + input: + bytes: [ 0xb7, 0x79, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx2], { z13.d, z14.d }, z8.d" + + - + input: + bytes: [ 0xb7, 0x79, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx2], { z13.d, z14.d }, z8.d" + + - + input: + bytes: [ 0xf7, 0x7b, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx2], { z31.d, z0.d }, z15.d" + + - + input: + bytes: [ 0xf7, 0x7b, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx2], { z31.d, z0.d }, z15.d" + + - + input: + bytes: [ 0x35, 0x1a, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx2], { z17.d, z18.d }, z0.d" + + - + input: + bytes: [ 0x35, 0x1a, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx2], { z17.d, z18.d }, z0.d" + + - + input: + bytes: [ 0x31, 0x18, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 1, vgx2], { z1.d, z2.d }, z14.d" + + - + input: + bytes: [ 0x31, 0x18, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 1, vgx2], { z1.d, z2.d }, z14.d" + + - + input: + bytes: [ 0x70, 0x5a, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 0, vgx2], { z19.d, z20.d }, z4.d" + + - + input: + bytes: [ 0x70, 0x5a, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 0, vgx2], { z19.d, z20.d }, z4.d" + + - + input: + bytes: [ 0x90, 0x19, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d" + + - + input: + bytes: [ 0x90, 0x19, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d" + + - + input: + bytes: [ 0x31, 0x58, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 1, vgx2], { z1.d, z2.d }, z10.d" + + - + input: + bytes: [ 0x31, 0x58, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 1, vgx2], { z1.d, z2.d }, z10.d" + + - + input: + bytes: [ 0xd5, 0x1a, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d" + + - + input: + bytes: [ 0xd5, 0x1a, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d" + + - + input: + bytes: [ 0x32, 0x79, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 2, vgx2], { z9.d, z10.d }, z1.d" + + - + input: + bytes: [ 0x32, 0x79, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 2, vgx2], { z9.d, z10.d }, z1.d" + + - + input: + bytes: [ 0x97, 0x39, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d" + + - + input: + bytes: [ 0x97, 0x39, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d" + + - + input: + bytes: [ 0x00, 0xa3, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z0.d, z1.d }, { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x14, 0xa3, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z20.d, z21.d }, { z20.d, z21.d }, z5.d" + + - + input: + bytes: [ 0x16, 0xa3, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z22.d, z23.d }, { z22.d, z23.d }, z8.d" + + - + input: + bytes: [ 0x1e, 0xa3, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z30.d, z31.d }, { z30.d, z31.d }, z15.d" + + - + input: + bytes: [ 0x10, 0x18, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x10, 0x18, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x55, 0x59, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x55, 0x59, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x97, 0x79, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0x97, 0x79, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0xd7, 0x7b, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0xd7, 0x7b, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x15, 0x1a, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }" + + - + input: + bytes: [ 0x15, 0x1a, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }" + + - + input: + bytes: [ 0x11, 0x18, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x11, 0x18, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x50, 0x5a, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x50, 0x5a, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x90, 0x19, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }" + + - + input: + bytes: [ 0x90, 0x19, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }" + + - + input: + bytes: [ 0x11, 0x58, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }" + + - + input: + bytes: [ 0x11, 0x58, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }" + + - + input: + bytes: [ 0xd5, 0x1a, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0xd5, 0x1a, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x12, 0x79, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x12, 0x79, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x97, 0x39, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }" + + - + input: + bytes: [ 0x97, 0x39, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }" + + - + input: + bytes: [ 0x00, 0xa3, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z0.b, z1.b }, { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x14, 0xa3, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z20.b, z21.b }, { z20.b, z21.b }, z5.b" + + - + input: + bytes: [ 0x16, 0xa3, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z22.b, z23.b }, { z22.b, z23.b }, z8.b" + + - + input: + bytes: [ 0x1e, 0xa3, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z30.b, z31.b }, { z30.b, z31.b }, z15.b" + + - + input: + bytes: [ 0x00, 0xab, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z0.h - z3.h }, { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x14, 0xab, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z20.h - z23.h }, { z20.h - z23.h }, z5.h" + + - + input: + bytes: [ 0x14, 0xab, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z20.h - z23.h }, { z20.h - z23.h }, z8.h" + + - + input: + bytes: [ 0x1c, 0xab, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z28.h - z31.h }, { z28.h - z31.h }, z15.h" + + - + input: + bytes: [ 0x10, 0x1c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x10, 0x1c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x15, 0x5d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 5, vgx4], { z8.s - z11.s }" + + - + input: + bytes: [ 0x15, 0x5d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 5, vgx4], { z8.s - z11.s }" + + - + input: + bytes: [ 0x97, 0x7d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x97, 0x7d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x97, 0x7f, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx4], { z28.s - z31.s }" + + - + input: + bytes: [ 0x97, 0x7f, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx4], { z28.s - z31.s }" + + - + input: + bytes: [ 0x15, 0x1e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx4], { z16.s - z19.s }" + + - + input: + bytes: [ 0x15, 0x1e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx4], { z16.s - z19.s }" + + - + input: + bytes: [ 0x11, 0x1c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 1, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x11, 0x1c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 1, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x10, 0x5e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 0, vgx4], { z16.s - z19.s }" + + - + input: + bytes: [ 0x10, 0x5e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 0, vgx4], { z16.s - z19.s }" + + - + input: + bytes: [ 0x90, 0x1d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x90, 0x1d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x11, 0x5c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 1, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x11, 0x5c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 1, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x95, 0x1e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx4], { z20.s - z23.s }" + + - + input: + bytes: [ 0x95, 0x1e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx4], { z20.s - z23.s }" + + - + input: + bytes: [ 0x12, 0x7d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 2, vgx4], { z8.s - z11.s }" + + - + input: + bytes: [ 0x12, 0x7d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 2, vgx4], { z8.s - z11.s }" + + - + input: + bytes: [ 0x97, 0x3d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w9, 7, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x97, 0x3d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w9, 7, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x10, 0x18, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x10, 0x18, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x55, 0x59, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 5, vgx4], { z10.s - z13.s }, z5.s" + + - + input: + bytes: [ 0x55, 0x59, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 5, vgx4], { z10.s - z13.s }, z5.s" + + - + input: + bytes: [ 0xb7, 0x79, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx4], { z13.s - z16.s }, z8.s" + + - + input: + bytes: [ 0xb7, 0x79, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx4], { z13.s - z16.s }, z8.s" + + - + input: + bytes: [ 0xf7, 0x7b, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx4], { z31.s, z0.s, z1.s, z2.s }, z15.s" + + - + input: + bytes: [ 0xf7, 0x7b, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx4], { z31.s, z0.s, z1.s, z2.s }, z15.s" + + - + input: + bytes: [ 0x35, 0x1a, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx4], { z17.s - z20.s }, z0.s" + + - + input: + bytes: [ 0x35, 0x1a, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx4], { z17.s - z20.s }, z0.s" + + - + input: + bytes: [ 0x31, 0x18, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 1, vgx4], { z1.s - z4.s }, z14.s" + + - + input: + bytes: [ 0x31, 0x18, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 1, vgx4], { z1.s - z4.s }, z14.s" + + - + input: + bytes: [ 0x70, 0x5a, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 0, vgx4], { z19.s - z22.s }, z4.s" + + - + input: + bytes: [ 0x70, 0x5a, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 0, vgx4], { z19.s - z22.s }, z4.s" + + - + input: + bytes: [ 0x90, 0x19, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s" + + - + input: + bytes: [ 0x90, 0x19, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s" + + - + input: + bytes: [ 0x31, 0x58, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 1, vgx4], { z1.s - z4.s }, z10.s" + + - + input: + bytes: [ 0x31, 0x58, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 1, vgx4], { z1.s - z4.s }, z10.s" + + - + input: + bytes: [ 0xd5, 0x1a, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx4], { z22.s - z25.s }, z14.s" + + - + input: + bytes: [ 0xd5, 0x1a, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx4], { z22.s - z25.s }, z14.s" + + - + input: + bytes: [ 0x32, 0x79, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 2, vgx4], { z9.s - z12.s }, z1.s" + + - + input: + bytes: [ 0x32, 0x79, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 2, vgx4], { z9.s - z12.s }, z1.s" + + - + input: + bytes: [ 0x97, 0x39, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s" + + - + input: + bytes: [ 0x97, 0x39, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s" + + - + input: + bytes: [ 0x00, 0xab, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z0.s - z3.s }, { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x14, 0xab, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z20.s - z23.s }, { z20.s - z23.s }, z5.s" + + - + input: + bytes: [ 0x14, 0xab, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z20.s - z23.s }, { z20.s - z23.s }, z8.s" + + - + input: + bytes: [ 0x1c, 0xab, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z28.s - z31.s }, { z28.s - z31.s }, z15.s" + + - + input: + bytes: [ 0x10, 0x18, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x10, 0x18, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x15, 0x59, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x15, 0x59, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x97, 0x79, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x97, 0x79, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x97, 0x7b, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x97, 0x7b, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x15, 0x1a, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }" + + - + input: + bytes: [ 0x15, 0x1a, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }" + + - + input: + bytes: [ 0x11, 0x18, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x11, 0x18, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x10, 0x5a, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x10, 0x5a, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x90, 0x19, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x90, 0x19, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x11, 0x58, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }" + + - + input: + bytes: [ 0x11, 0x58, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }" + + - + input: + bytes: [ 0x95, 0x1a, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x95, 0x1a, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x12, 0x79, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x12, 0x79, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x97, 0x39, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x97, 0x39, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x10, 0x1c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x10, 0x1c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x15, 0x5d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 5, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x15, 0x5d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 5, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x97, 0x7d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x97, 0x7d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x97, 0x7f, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx4], { z28.d - z31.d }" + + - + input: + bytes: [ 0x97, 0x7f, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx4], { z28.d - z31.d }" + + - + input: + bytes: [ 0x15, 0x1e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x15, 0x1e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x11, 0x1c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x11, 0x1c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x10, 0x5e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 0, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x10, 0x5e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 0, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x90, 0x1d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x90, 0x1d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x11, 0x5c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x11, 0x5c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x95, 0x1e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx4], { z20.d - z23.d }" + + - + input: + bytes: [ 0x95, 0x1e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx4], { z20.d - z23.d }" + + - + input: + bytes: [ 0x12, 0x7d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 2, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x12, 0x7d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 2, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x97, 0x3d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w9, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x97, 0x3d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w9, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x10, 0x18, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x10, 0x18, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x55, 0x59, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 5, vgx4], { z10.d - z13.d }, z5.d" + + - + input: + bytes: [ 0x55, 0x59, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 5, vgx4], { z10.d - z13.d }, z5.d" + + - + input: + bytes: [ 0xb7, 0x79, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx4], { z13.d - z16.d }, z8.d" + + - + input: + bytes: [ 0xb7, 0x79, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx4], { z13.d - z16.d }, z8.d" + + - + input: + bytes: [ 0xf7, 0x7b, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx4], { z31.d, z0.d, z1.d, z2.d }, z15.d" + + - + input: + bytes: [ 0xf7, 0x7b, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx4], { z31.d, z0.d, z1.d, z2.d }, z15.d" + + - + input: + bytes: [ 0x35, 0x1a, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx4], { z17.d - z20.d }, z0.d" + + - + input: + bytes: [ 0x35, 0x1a, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx4], { z17.d - z20.d }, z0.d" + + - + input: + bytes: [ 0x31, 0x18, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 1, vgx4], { z1.d - z4.d }, z14.d" + + - + input: + bytes: [ 0x31, 0x18, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 1, vgx4], { z1.d - z4.d }, z14.d" + + - + input: + bytes: [ 0x70, 0x5a, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 0, vgx4], { z19.d - z22.d }, z4.d" + + - + input: + bytes: [ 0x70, 0x5a, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 0, vgx4], { z19.d - z22.d }, z4.d" + + - + input: + bytes: [ 0x90, 0x19, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d" + + - + input: + bytes: [ 0x90, 0x19, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d" + + - + input: + bytes: [ 0x31, 0x58, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 1, vgx4], { z1.d - z4.d }, z10.d" + + - + input: + bytes: [ 0x31, 0x58, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 1, vgx4], { z1.d - z4.d }, z10.d" + + - + input: + bytes: [ 0xd5, 0x1a, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx4], { z22.d - z25.d }, z14.d" + + - + input: + bytes: [ 0xd5, 0x1a, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx4], { z22.d - z25.d }, z14.d" + + - + input: + bytes: [ 0x32, 0x79, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 2, vgx4], { z9.d - z12.d }, z1.d" + + - + input: + bytes: [ 0x32, 0x79, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 2, vgx4], { z9.d - z12.d }, z1.d" + + - + input: + bytes: [ 0x97, 0x39, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d" + + - + input: + bytes: [ 0x97, 0x39, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d" + + - + input: + bytes: [ 0x10, 0x18, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x10, 0x18, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x15, 0x59, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x15, 0x59, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x97, 0x79, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x97, 0x79, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x97, 0x7b, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x97, 0x7b, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x15, 0x1a, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }" + + - + input: + bytes: [ 0x15, 0x1a, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }" + + - + input: + bytes: [ 0x11, 0x18, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x11, 0x18, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x10, 0x5a, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x10, 0x5a, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x90, 0x19, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x90, 0x19, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x11, 0x58, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }" + + - + input: + bytes: [ 0x11, 0x58, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }" + + - + input: + bytes: [ 0x95, 0x1a, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x95, 0x1a, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x12, 0x79, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x12, 0x79, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x97, 0x39, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x97, 0x39, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x00, 0xab, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z0.d - z3.d }, { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x14, 0xab, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z20.d - z23.d }, { z20.d - z23.d }, z5.d" + + - + input: + bytes: [ 0x14, 0xab, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z20.d - z23.d }, { z20.d - z23.d }, z8.d" + + - + input: + bytes: [ 0x1c, 0xab, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z28.d - z31.d }, { z28.d - z31.d }, z15.d" + + - + input: + bytes: [ 0x10, 0x18, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x10, 0x18, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x15, 0x59, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x15, 0x59, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x97, 0x79, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x97, 0x79, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x97, 0x7b, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x97, 0x7b, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x15, 0x1a, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }" + + - + input: + bytes: [ 0x15, 0x1a, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }" + + - + input: + bytes: [ 0x11, 0x18, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x11, 0x18, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x10, 0x5a, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x10, 0x5a, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x90, 0x19, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x90, 0x19, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x11, 0x58, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }" + + - + input: + bytes: [ 0x11, 0x58, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }" + + - + input: + bytes: [ 0x95, 0x1a, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x95, 0x1a, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x12, 0x79, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x12, 0x79, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x97, 0x39, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x97, 0x39, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x00, 0xab, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z0.b - z3.b }, { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x14, 0xab, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z20.b - z23.b }, { z20.b - z23.b }, z5.b" + + - + input: + bytes: [ 0x14, 0xab, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z20.b - z23.b }, { z20.b - z23.b }, z8.b" + + - + input: + bytes: [ 0x1c, 0xab, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "add { z28.b - z31.b }, { z28.b - z31.b }, z15.b" diff --git a/tests/MC/AArch64/SME2/bfadd.s.yaml b/tests/MC/AArch64/SME2/bfadd.s.yaml new file mode 100644 index 0000000000..81131eac39 --- /dev/null +++ b/tests/MC/AArch64/SME2/bfadd.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x1c, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 0, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0x00, 0x1c, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 0, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0x45, 0x5d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w10, 5, vgx2], { z10.h, z11.h }" + + - + input: + bytes: [ 0x45, 0x5d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w10, 5, vgx2], { z10.h, z11.h }" + + - + input: + bytes: [ 0x87, 0x7d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w11, 7, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x87, 0x7d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w11, 7, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0xc7, 0x7f, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w11, 7, vgx2], { z30.h, z31.h }" + + - + input: + bytes: [ 0xc7, 0x7f, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w11, 7, vgx2], { z30.h, z31.h }" + + - + input: + bytes: [ 0x05, 0x1e, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 5, vgx2], { z16.h, z17.h }" + + - + input: + bytes: [ 0x05, 0x1e, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 5, vgx2], { z16.h, z17.h }" + + - + input: + bytes: [ 0x01, 0x1c, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 1, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0x01, 0x1c, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 1, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0x40, 0x5e, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w10, 0, vgx2], { z18.h, z19.h }" + + - + input: + bytes: [ 0x40, 0x5e, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w10, 0, vgx2], { z18.h, z19.h }" + + - + input: + bytes: [ 0x80, 0x1d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 0, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x80, 0x1d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 0, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x01, 0x5c, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w10, 1, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0x01, 0x5c, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w10, 1, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0xc5, 0x1e, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 5, vgx2], { z22.h, z23.h }" + + - + input: + bytes: [ 0xc5, 0x1e, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 5, vgx2], { z22.h, z23.h }" + + - + input: + bytes: [ 0x02, 0x7d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w11, 2, vgx2], { z8.h, z9.h }" + + - + input: + bytes: [ 0x02, 0x7d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w11, 2, vgx2], { z8.h, z9.h }" + + - + input: + bytes: [ 0x87, 0x3d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w9, 7, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x87, 0x3d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w9, 7, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x00, 0x1c, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 0, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x00, 0x1c, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 0, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x05, 0x5d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w10, 5, vgx4], { z8.h - z11.h }" + + - + input: + bytes: [ 0x05, 0x5d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w10, 5, vgx4], { z8.h - z11.h }" + + - + input: + bytes: [ 0x87, 0x7d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w11, 7, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x87, 0x7d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w11, 7, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x87, 0x7f, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w11, 7, vgx4], { z28.h - z31.h }" + + - + input: + bytes: [ 0x87, 0x7f, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w11, 7, vgx4], { z28.h - z31.h }" + + - + input: + bytes: [ 0x05, 0x1e, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 5, vgx4], { z16.h - z19.h }" + + - + input: + bytes: [ 0x05, 0x1e, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 5, vgx4], { z16.h - z19.h }" + + - + input: + bytes: [ 0x01, 0x1c, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 1, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x01, 0x1c, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 1, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x00, 0x5e, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w10, 0, vgx4], { z16.h - z19.h }" + + - + input: + bytes: [ 0x00, 0x5e, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w10, 0, vgx4], { z16.h - z19.h }" + + - + input: + bytes: [ 0x80, 0x1d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 0, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x80, 0x1d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 0, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x01, 0x5c, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w10, 1, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x01, 0x5c, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w10, 1, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x85, 0x1e, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 5, vgx4], { z20.h - z23.h }" + + - + input: + bytes: [ 0x85, 0x1e, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w8, 5, vgx4], { z20.h - z23.h }" + + - + input: + bytes: [ 0x02, 0x7d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w11, 2, vgx4], { z8.h - z11.h }" + + - + input: + bytes: [ 0x02, 0x7d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w11, 2, vgx4], { z8.h - z11.h }" + + - + input: + bytes: [ 0x87, 0x3d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w9, 7, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x87, 0x3d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd za.h[w9, 7, vgx4], { z12.h - z15.h }" diff --git a/tests/MC/AArch64/SME2/bfclamp.s.yaml b/tests/MC/AArch64/SME2/bfclamp.s.yaml new file mode 100644 index 0000000000..55e2467ccb --- /dev/null +++ b/tests/MC/AArch64/SME2/bfclamp.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfclamp { z0.h, z1.h }, z0.h, z0.h" + + - + input: + bytes: [ 0x54, 0xc1, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfclamp { z20.h, z21.h }, z10.h, z21.h" + + - + input: + bytes: [ 0xb6, 0xc1, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfclamp { z22.h, z23.h }, z13.h, z8.h" + + - + input: + bytes: [ 0xfe, 0xc3, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfclamp { z30.h, z31.h }, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0xc8, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfclamp { z0.h - z3.h }, z0.h, z0.h" + + - + input: + bytes: [ 0x54, 0xc9, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfclamp { z20.h - z23.h }, z10.h, z21.h" + + - + input: + bytes: [ 0xb4, 0xc9, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfclamp { z20.h - z23.h }, z13.h, z8.h" + + - + input: + bytes: [ 0xfc, 0xcb, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfclamp { z28.h - z31.h }, z31.h, z31.h" diff --git a/tests/MC/AArch64/SME2/bfcvt.s.yaml b/tests/MC/AArch64/SME2/bfcvt.s.yaml new file mode 100644 index 0000000000..d7a6cff817 --- /dev/null +++ b/tests/MC/AArch64/SME2/bfcvt.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfcvt z0.h, { z0.s, z1.s }" + + - + input: + bytes: [ 0x55, 0xe1, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfcvt z21.h, { z10.s, z11.s }" + + - + input: + bytes: [ 0x97, 0xe1, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfcvt z23.h, { z12.s, z13.s }" + + - + input: + bytes: [ 0xdf, 0xe3, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfcvt z31.h, { z30.s, z31.s }" diff --git a/tests/MC/AArch64/SME2/bfcvtn.s.yaml b/tests/MC/AArch64/SME2/bfcvtn.s.yaml new file mode 100644 index 0000000000..4b62a4b0e7 --- /dev/null +++ b/tests/MC/AArch64/SME2/bfcvtn.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xe0, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfcvtn z0.h, { z0.s, z1.s }" + + - + input: + bytes: [ 0x75, 0xe1, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfcvtn z21.h, { z10.s, z11.s }" + + - + input: + bytes: [ 0xb7, 0xe1, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfcvtn z23.h, { z12.s, z13.s }" + + - + input: + bytes: [ 0xff, 0xe3, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfcvtn z31.h, { z30.s, z31.s }" diff --git a/tests/MC/AArch64/SME2/bfdot.s.yaml b/tests/MC/AArch64/SME2/bfdot.s.yaml new file mode 100644 index 0000000000..1d178868d2 --- /dev/null +++ b/tests/MC/AArch64/SME2/bfdot.s.yaml @@ -0,0 +1,1440 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x10, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x10, 0x10, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x55, 0x51, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x55, 0x51, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xb7, 0x71, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xb7, 0x71, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xf7, 0x73, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xf7, 0x73, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x35, 0x12, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x35, 0x12, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x31, 0x10, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x31, 0x10, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x70, 0x52, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x70, 0x52, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x90, 0x11, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x90, 0x11, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x31, 0x50, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x31, 0x50, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xd5, 0x12, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xd5, 0x12, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x32, 0x71, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x32, 0x71, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x97, 0x31, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x97, 0x31, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x18, 0x10, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x18, 0x10, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x5d, 0x55, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x5d, 0x55, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x9f, 0x7d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]" + + - + input: + bytes: [ 0x9f, 0x7d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]" + + - + input: + bytes: [ 0xdf, 0x7f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]" + + - + input: + bytes: [ 0xdf, 0x7f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]" + + - + input: + bytes: [ 0x1d, 0x1e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]" + + - + input: + bytes: [ 0x1d, 0x1e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]" + + - + input: + bytes: [ 0x19, 0x14, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x19, 0x14, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x58, 0x56, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x58, 0x56, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x98, 0x19, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]" + + - + input: + bytes: [ 0x98, 0x19, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]" + + - + input: + bytes: [ 0x19, 0x58, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]" + + - + input: + bytes: [ 0x19, 0x58, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]" + + - + input: + bytes: [ 0xdd, 0x1a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0xdd, 0x1a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x1a, 0x75, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0x1a, 0x75, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0x9f, 0x39, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]" + + - + input: + bytes: [ 0x9f, 0x39, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]" + + - + input: + bytes: [ 0x10, 0x10, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x10, 0x10, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x55, 0x51, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x55, 0x51, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x97, 0x71, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x97, 0x71, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xd7, 0x73, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xd7, 0x73, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x15, 0x12, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x15, 0x12, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x11, 0x10, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x11, 0x10, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x50, 0x52, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x50, 0x52, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x90, 0x11, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x90, 0x11, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x11, 0x50, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x11, 0x50, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xd5, 0x12, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xd5, 0x12, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x12, 0x71, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x12, 0x71, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x97, 0x31, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x97, 0x31, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x10, 0x10, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x10, 0x10, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x55, 0x51, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x55, 0x51, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xb7, 0x71, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xb7, 0x71, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xf7, 0x73, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xf7, 0x73, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x35, 0x12, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x35, 0x12, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x31, 0x10, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x31, 0x10, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x70, 0x52, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x70, 0x52, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x90, 0x11, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x90, 0x11, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x31, 0x50, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x31, 0x50, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xd5, 0x12, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xd5, 0x12, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x32, 0x71, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x32, 0x71, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x97, 0x31, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x97, 0x31, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x18, 0x90, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x18, 0x90, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x1d, 0xd5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x1d, 0xd5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x9f, 0xfd, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]" + + - + input: + bytes: [ 0x9f, 0xfd, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]" + + - + input: + bytes: [ 0x9f, 0xff, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]" + + - + input: + bytes: [ 0x9f, 0xff, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]" + + - + input: + bytes: [ 0x1d, 0x9e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]" + + - + input: + bytes: [ 0x1d, 0x9e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]" + + - + input: + bytes: [ 0x19, 0x94, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]" + + - + input: + bytes: [ 0x19, 0x94, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]" + + - + input: + bytes: [ 0x18, 0xd6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x18, 0xd6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x98, 0x99, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]" + + - + input: + bytes: [ 0x98, 0x99, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]" + + - + input: + bytes: [ 0x19, 0xd8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]" + + - + input: + bytes: [ 0x19, 0xd8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]" + + - + input: + bytes: [ 0x9d, 0x9a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x9d, 0x9a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x1a, 0xf5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]" + + - + input: + bytes: [ 0x1a, 0xf5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]" + + - + input: + bytes: [ 0x9f, 0xb9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]" + + - + input: + bytes: [ 0x9f, 0xb9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]" + + - + input: + bytes: [ 0x10, 0x10, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x10, 0x10, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x15, 0x51, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x15, 0x51, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x97, 0x71, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x97, 0x71, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x97, 0x73, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x97, 0x73, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x15, 0x12, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x15, 0x12, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x11, 0x10, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x11, 0x10, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x10, 0x52, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x10, 0x52, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x90, 0x11, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x90, 0x11, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x11, 0x50, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x11, 0x50, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x95, 0x12, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x95, 0x12, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x12, 0x71, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x12, 0x71, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x97, 0x31, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x97, 0x31, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfdot za.s[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2/bfmax.s.yaml b/tests/MC/AArch64/SME2/bfmax.s.yaml new file mode 100644 index 0000000000..b350092785 --- /dev/null +++ b/tests/MC/AArch64/SME2/bfmax.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa1, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax { z0.h, z1.h }, { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x14, 0xa1, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax { z20.h, z21.h }, { z20.h, z21.h }, z5.h" + + - + input: + bytes: [ 0x16, 0xa1, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax { z22.h, z23.h }, { z22.h, z23.h }, z8.h" + + - + input: + bytes: [ 0x1e, 0xa1, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax { z30.h, z31.h }, { z30.h, z31.h }, z15.h" + + - + input: + bytes: [ 0x00, 0xb1, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x14, 0xb1, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x16, 0xb1, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x1e, 0xb1, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x00, 0xa9, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax { z0.h - z3.h }, { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x14, 0xa9, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax { z20.h - z23.h }, { z20.h - z23.h }, z5.h" + + - + input: + bytes: [ 0x14, 0xa9, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax { z20.h - z23.h }, { z20.h - z23.h }, z8.h" + + - + input: + bytes: [ 0x1c, 0xa9, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax { z28.h - z31.h }, { z28.h - z31.h }, z15.h" + + - + input: + bytes: [ 0x00, 0xb9, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x14, 0xb9, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x14, 0xb9, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x1c, 0xb9, 0x3c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }" diff --git a/tests/MC/AArch64/SME2/bfmaxnm.s.yaml b/tests/MC/AArch64/SME2/bfmaxnm.s.yaml new file mode 100644 index 0000000000..4311bd5e8b --- /dev/null +++ b/tests/MC/AArch64/SME2/bfmaxnm.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa1, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm { z0.h, z1.h }, { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x34, 0xa1, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm { z20.h, z21.h }, { z20.h, z21.h }, z5.h" + + - + input: + bytes: [ 0x36, 0xa1, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm { z22.h, z23.h }, { z22.h, z23.h }, z8.h" + + - + input: + bytes: [ 0x3e, 0xa1, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm { z30.h, z31.h }, { z30.h, z31.h }, z15.h" + + - + input: + bytes: [ 0x20, 0xb1, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x34, 0xb1, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x36, 0xb1, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x3e, 0xb1, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x20, 0xa9, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm { z0.h - z3.h }, { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x34, 0xa9, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm { z20.h - z23.h }, { z20.h - z23.h }, z5.h" + + - + input: + bytes: [ 0x34, 0xa9, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm { z20.h - z23.h }, { z20.h - z23.h }, z8.h" + + - + input: + bytes: [ 0x3c, 0xa9, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm { z28.h - z31.h }, { z28.h - z31.h }, z15.h" + + - + input: + bytes: [ 0x20, 0xb9, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x34, 0xb9, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x34, 0xb9, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x3c, 0xb9, 0x3c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }" diff --git a/tests/MC/AArch64/SME2/bfmin.s.yaml b/tests/MC/AArch64/SME2/bfmin.s.yaml new file mode 100644 index 0000000000..82added9da --- /dev/null +++ b/tests/MC/AArch64/SME2/bfmin.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x01, 0xa1, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin { z0.h, z1.h }, { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x15, 0xa1, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin { z20.h, z21.h }, { z20.h, z21.h }, z5.h" + + - + input: + bytes: [ 0x17, 0xa1, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin { z22.h, z23.h }, { z22.h, z23.h }, z8.h" + + - + input: + bytes: [ 0x1f, 0xa1, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin { z30.h, z31.h }, { z30.h, z31.h }, z15.h" + + - + input: + bytes: [ 0x01, 0xb1, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x15, 0xb1, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x17, 0xb1, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x1f, 0xb1, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x01, 0xa9, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin { z0.h - z3.h }, { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x15, 0xa9, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin { z20.h - z23.h }, { z20.h - z23.h }, z5.h" + + - + input: + bytes: [ 0x15, 0xa9, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin { z20.h - z23.h }, { z20.h - z23.h }, z8.h" + + - + input: + bytes: [ 0x1d, 0xa9, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin { z28.h - z31.h }, { z28.h - z31.h }, z15.h" + + - + input: + bytes: [ 0x01, 0xb9, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x15, 0xb9, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x15, 0xb9, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x1d, 0xb9, 0x3c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }" diff --git a/tests/MC/AArch64/SME2/bfminnm.s.yaml b/tests/MC/AArch64/SME2/bfminnm.s.yaml new file mode 100644 index 0000000000..366144caf2 --- /dev/null +++ b/tests/MC/AArch64/SME2/bfminnm.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x21, 0xa1, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm { z0.h, z1.h }, { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x35, 0xa1, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm { z20.h, z21.h }, { z20.h, z21.h }, z5.h" + + - + input: + bytes: [ 0x37, 0xa1, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm { z22.h, z23.h }, { z22.h, z23.h }, z8.h" + + - + input: + bytes: [ 0x3f, 0xa1, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm { z30.h, z31.h }, { z30.h, z31.h }, z15.h" + + - + input: + bytes: [ 0x21, 0xb1, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x35, 0xb1, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x37, 0xb1, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x3f, 0xb1, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x21, 0xa9, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm { z0.h - z3.h }, { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x35, 0xa9, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm { z20.h - z23.h }, { z20.h - z23.h }, z5.h" + + - + input: + bytes: [ 0x35, 0xa9, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm { z20.h - z23.h }, { z20.h - z23.h }, z8.h" + + - + input: + bytes: [ 0x3d, 0xa9, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm { z28.h - z31.h }, { z28.h - z31.h }, z15.h" + + - + input: + bytes: [ 0x21, 0xb9, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x35, 0xb9, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x35, 0xb9, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x3d, 0xb9, 0x3c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }" diff --git a/tests/MC/AArch64/SME2/bfmla.s.yaml b/tests/MC/AArch64/SME2/bfmla.s.yaml new file mode 100644 index 0000000000..2e16e02b1d --- /dev/null +++ b/tests/MC/AArch64/SME2/bfmla.s.yaml @@ -0,0 +1,1440 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x1c, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x00, 0x1c, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x45, 0x5d, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x45, 0x5d, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xa7, 0x7d, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xa7, 0x7d, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xe7, 0x7f, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xe7, 0x7f, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x25, 0x1e, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x25, 0x1e, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x1c, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x21, 0x1c, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x60, 0x5e, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x60, 0x5e, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x80, 0x1d, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x80, 0x1d, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x21, 0x5c, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x21, 0x5c, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xc5, 0x1e, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xc5, 0x1e, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x22, 0x7d, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x22, 0x7d, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x87, 0x3d, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x87, 0x3d, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x20, 0x10, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x20, 0x10, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x65, 0x55, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2]" + + - + input: + bytes: [ 0x65, 0x55, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2]" + + - + input: + bytes: [ 0xa7, 0x7d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6]" + + - + input: + bytes: [ 0xa7, 0x7d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6]" + + - + input: + bytes: [ 0xef, 0x7f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0xef, 0x7f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x25, 0x1e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6]" + + - + input: + bytes: [ 0x25, 0x1e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6]" + + - + input: + bytes: [ 0x21, 0x14, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x21, 0x14, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x68, 0x56, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3]" + + - + input: + bytes: [ 0x68, 0x56, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3]" + + - + input: + bytes: [ 0xa0, 0x19, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0xa0, 0x19, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x21, 0x58, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0x21, 0x58, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0xed, 0x1a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0xed, 0x1a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x22, 0x75, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x22, 0x75, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0xa7, 0x39, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4]" + + - + input: + bytes: [ 0xa7, 0x39, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4]" + + - + input: + bytes: [ 0x08, 0x10, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x08, 0x10, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x4d, 0x51, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x4d, 0x51, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x8f, 0x71, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x8f, 0x71, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xcf, 0x73, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xcf, 0x73, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x0d, 0x12, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x0d, 0x12, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x09, 0x10, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x09, 0x10, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x48, 0x52, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x48, 0x52, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x88, 0x11, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x88, 0x11, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x09, 0x50, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x09, 0x50, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xcd, 0x12, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xcd, 0x12, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x0a, 0x71, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x0a, 0x71, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x8f, 0x31, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x8f, 0x31, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x00, 0x1c, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x00, 0x1c, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x45, 0x5d, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x45, 0x5d, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xa7, 0x7d, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xa7, 0x7d, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xe7, 0x7f, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xe7, 0x7f, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x25, 0x1e, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x25, 0x1e, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x1c, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x21, 0x1c, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x60, 0x5e, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x60, 0x5e, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x80, 0x1d, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x80, 0x1d, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x21, 0x5c, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x21, 0x5c, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xc5, 0x1e, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xc5, 0x1e, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x22, 0x7d, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x22, 0x7d, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x87, 0x3d, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x87, 0x3d, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x20, 0x90, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x20, 0x90, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x25, 0xd5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2]" + + - + input: + bytes: [ 0x25, 0xd5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2]" + + - + input: + bytes: [ 0xa7, 0xfd, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6]" + + - + input: + bytes: [ 0xa7, 0xfd, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6]" + + - + input: + bytes: [ 0xaf, 0xff, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0xaf, 0xff, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x25, 0x9e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6]" + + - + input: + bytes: [ 0x25, 0x9e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6]" + + - + input: + bytes: [ 0x21, 0x94, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x21, 0x94, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x28, 0xd6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3]" + + - + input: + bytes: [ 0x28, 0xd6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3]" + + - + input: + bytes: [ 0xa0, 0x99, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0xa0, 0x99, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x21, 0xd8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x21, 0xd8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0xad, 0x9a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0xad, 0x9a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x22, 0xf5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x22, 0xf5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0xa7, 0xb9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4]" + + - + input: + bytes: [ 0xa7, 0xb9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4]" + + - + input: + bytes: [ 0x08, 0x10, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x08, 0x10, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x0d, 0x51, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x0d, 0x51, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x8f, 0x71, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x8f, 0x71, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x8f, 0x73, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x8f, 0x73, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x0d, 0x12, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x0d, 0x12, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x09, 0x10, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x09, 0x10, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x08, 0x52, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x08, 0x52, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x88, 0x11, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x88, 0x11, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x09, 0x50, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x09, 0x50, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x8d, 0x12, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x8d, 0x12, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x0a, 0x71, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x0a, 0x71, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x8f, 0x31, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x8f, 0x31, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2/bfmlal.s.yaml b/tests/MC/AArch64/SME2/bfmlal.s.yaml new file mode 100644 index 0000000000..1ca16cdb9e --- /dev/null +++ b/tests/MC/AArch64/SME2/bfmlal.s.yaml @@ -0,0 +1,1680 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x0c, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1], z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x4d, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 10:11], z10.h, z5.h" + + - + input: + bytes: [ 0xb7, 0x6d, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 14:15], z13.h, z8.h" + + - + input: + bytes: [ 0xf7, 0x6f, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 14:15], z31.h, z15.h" + + - + input: + bytes: [ 0x35, 0x0e, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 10:11], z17.h, z0.h" + + - + input: + bytes: [ 0x31, 0x0c, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3], z1.h, z14.h" + + - + input: + bytes: [ 0x70, 0x4e, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 0:1], z19.h, z4.h" + + - + input: + bytes: [ 0x90, 0x0d, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1], z12.h, z2.h" + + - + input: + bytes: [ 0x31, 0x4c, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3], z1.h, z10.h" + + - + input: + bytes: [ 0xd5, 0x0e, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 10:11], z22.h, z14.h" + + - + input: + bytes: [ 0x32, 0x6d, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 4:5], z9.h, z1.h" + + - + input: + bytes: [ 0x97, 0x2d, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w9, 14:15], z12.h, z11.h" + + - + input: + bytes: [ 0x10, 0x10, 0x80, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1], z0.h, z0.h[0]" + + - + input: + bytes: [ 0x55, 0x55, 0x85, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 10:11], z10.h, z5.h[1]" + + - + input: + bytes: [ 0xb7, 0xfd, 0x88, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 14:15], z13.h, z8.h[7]" + + - + input: + bytes: [ 0xf7, 0xff, 0x8f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 14:15], z31.h, z15.h[7]" + + - + input: + bytes: [ 0x35, 0x1e, 0x80, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 10:11], z17.h, z0.h[3]" + + - + input: + bytes: [ 0x31, 0x94, 0x8e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3], z1.h, z14.h[5]" + + - + input: + bytes: [ 0x70, 0x56, 0x84, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 0:1], z19.h, z4.h[1]" + + - + input: + bytes: [ 0x90, 0x19, 0x82, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1], z12.h, z2.h[2]" + + - + input: + bytes: [ 0x31, 0xd8, 0x8a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3], z1.h, z10.h[6]" + + - + input: + bytes: [ 0xd5, 0x1a, 0x8e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 10:11], z22.h, z14.h[2]" + + - + input: + bytes: [ 0x32, 0xf5, 0x81, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 4:5], z9.h, z1.h[5]" + + - + input: + bytes: [ 0x97, 0xb9, 0x8b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w9, 14:15], z12.h, z11.h[6]" + + - + input: + bytes: [ 0x10, 0x08, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x10, 0x08, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x51, 0x49, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x51, 0x49, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xb3, 0x69, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xb3, 0x69, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xf3, 0x6b, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xf3, 0x6b, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x31, 0x0a, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x31, 0x0a, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x31, 0x08, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x31, 0x08, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x70, 0x4a, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x70, 0x4a, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x90, 0x09, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x90, 0x09, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x31, 0x48, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x31, 0x48, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xd1, 0x0a, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xd1, 0x0a, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x32, 0x69, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x32, 0x69, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x93, 0x29, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x93, 0x29, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x10, 0x10, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x10, 0x10, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x55, 0x55, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x55, 0x55, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x97, 0x7d, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0x97, 0x7d, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0xd7, 0x7f, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0xd7, 0x7f, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x15, 0x1e, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]" + + - + input: + bytes: [ 0x15, 0x1e, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]" + + - + input: + bytes: [ 0x11, 0x14, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x11, 0x14, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x50, 0x56, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x50, 0x56, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x90, 0x19, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x90, 0x19, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x11, 0x58, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0x11, 0x58, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0xd5, 0x1a, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0xd5, 0x1a, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x12, 0x75, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x12, 0x75, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x97, 0x39, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]" + + - + input: + bytes: [ 0x97, 0x39, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]" + + - + input: + bytes: [ 0x10, 0x08, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x10, 0x08, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x51, 0x49, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x51, 0x49, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x93, 0x69, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x93, 0x69, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xd3, 0x6b, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xd3, 0x6b, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x11, 0x0a, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x11, 0x0a, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x11, 0x08, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x11, 0x08, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x50, 0x4a, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x50, 0x4a, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x90, 0x09, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x90, 0x09, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x11, 0x48, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x11, 0x48, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xd1, 0x0a, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xd1, 0x0a, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x12, 0x69, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x12, 0x69, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x93, 0x29, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x93, 0x29, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x10, 0x08, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x10, 0x08, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x51, 0x49, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x51, 0x49, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xb3, 0x69, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xb3, 0x69, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xf3, 0x6b, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xf3, 0x6b, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x31, 0x0a, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x31, 0x0a, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x31, 0x08, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x31, 0x08, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x70, 0x4a, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x70, 0x4a, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x90, 0x09, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x90, 0x09, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x31, 0x48, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x31, 0x48, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xd1, 0x0a, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xd1, 0x0a, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x32, 0x69, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x32, 0x69, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x93, 0x29, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x93, 0x29, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x10, 0x90, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x10, 0x90, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x15, 0xd5, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x15, 0xd5, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x97, 0xfd, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x97, 0xfd, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x97, 0xff, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x97, 0xff, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x15, 0x9e, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]" + + - + input: + bytes: [ 0x15, 0x9e, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]" + + - + input: + bytes: [ 0x11, 0x94, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x11, 0x94, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x10, 0xd6, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x10, 0xd6, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x90, 0x99, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x90, 0x99, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x11, 0xd8, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x11, 0xd8, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x95, 0x9a, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x95, 0x9a, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x12, 0xf5, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x12, 0xf5, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x97, 0xb9, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]" + + - + input: + bytes: [ 0x97, 0xb9, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]" + + - + input: + bytes: [ 0x10, 0x08, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x10, 0x08, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x11, 0x49, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x11, 0x49, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x93, 0x69, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x93, 0x69, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x93, 0x6b, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x93, 0x6b, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x11, 0x0a, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x11, 0x0a, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x11, 0x08, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x11, 0x08, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x10, 0x4a, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x10, 0x4a, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x90, 0x09, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x90, 0x09, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x11, 0x48, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x11, 0x48, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x91, 0x0a, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x91, 0x0a, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x12, 0x69, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x12, 0x69, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x93, 0x29, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x93, 0x29, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2/bfmls.s.yaml b/tests/MC/AArch64/SME2/bfmls.s.yaml new file mode 100644 index 0000000000..101b7433cf --- /dev/null +++ b/tests/MC/AArch64/SME2/bfmls.s.yaml @@ -0,0 +1,1440 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x1c, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x08, 0x1c, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x4d, 0x5d, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x4d, 0x5d, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xaf, 0x7d, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xaf, 0x7d, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xef, 0x7f, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xef, 0x7f, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x2d, 0x1e, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x2d, 0x1e, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x29, 0x1c, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x29, 0x1c, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x68, 0x5e, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x68, 0x5e, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x88, 0x1d, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x88, 0x1d, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x29, 0x5c, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x29, 0x5c, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xcd, 0x1e, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xcd, 0x1e, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x2a, 0x7d, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x2a, 0x7d, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x8f, 0x3d, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x8f, 0x3d, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x30, 0x10, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x30, 0x10, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x75, 0x55, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2]" + + - + input: + bytes: [ 0x75, 0x55, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2]" + + - + input: + bytes: [ 0xb7, 0x7d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6]" + + - + input: + bytes: [ 0xb7, 0x7d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6]" + + - + input: + bytes: [ 0xff, 0x7f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0xff, 0x7f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x35, 0x1e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6]" + + - + input: + bytes: [ 0x35, 0x1e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6]" + + - + input: + bytes: [ 0x31, 0x14, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x31, 0x14, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x78, 0x56, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3]" + + - + input: + bytes: [ 0x78, 0x56, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3]" + + - + input: + bytes: [ 0xb0, 0x19, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0xb0, 0x19, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x31, 0x58, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0x31, 0x58, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0xfd, 0x1a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0xfd, 0x1a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x32, 0x75, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x32, 0x75, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0xb7, 0x39, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4]" + + - + input: + bytes: [ 0xb7, 0x39, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4]" + + - + input: + bytes: [ 0x18, 0x10, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x18, 0x10, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x5d, 0x51, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x5d, 0x51, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x9f, 0x71, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x9f, 0x71, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xdf, 0x73, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xdf, 0x73, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x1d, 0x12, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x1d, 0x12, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x19, 0x10, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x19, 0x10, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x58, 0x52, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x58, 0x52, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x98, 0x11, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x98, 0x11, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x19, 0x50, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x19, 0x50, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xdd, 0x12, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xdd, 0x12, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x1a, 0x71, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x1a, 0x71, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x9f, 0x31, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x9f, 0x31, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x08, 0x1c, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x08, 0x1c, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x4d, 0x5d, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x4d, 0x5d, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xaf, 0x7d, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xaf, 0x7d, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xef, 0x7f, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xef, 0x7f, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x2d, 0x1e, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x2d, 0x1e, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x29, 0x1c, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x29, 0x1c, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x68, 0x5e, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x68, 0x5e, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x88, 0x1d, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x88, 0x1d, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x29, 0x5c, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x29, 0x5c, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xcd, 0x1e, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xcd, 0x1e, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x2a, 0x7d, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x2a, 0x7d, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x8f, 0x3d, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x8f, 0x3d, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x30, 0x90, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x30, 0x90, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x35, 0xd5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2]" + + - + input: + bytes: [ 0x35, 0xd5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2]" + + - + input: + bytes: [ 0xb7, 0xfd, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6]" + + - + input: + bytes: [ 0xb7, 0xfd, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6]" + + - + input: + bytes: [ 0xbf, 0xff, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0xbf, 0xff, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x35, 0x9e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6]" + + - + input: + bytes: [ 0x35, 0x9e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6]" + + - + input: + bytes: [ 0x31, 0x94, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x31, 0x94, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x38, 0xd6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3]" + + - + input: + bytes: [ 0x38, 0xd6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3]" + + - + input: + bytes: [ 0xb0, 0x99, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0xb0, 0x99, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x31, 0xd8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x31, 0xd8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0xbd, 0x9a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0xbd, 0x9a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x32, 0xf5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x32, 0xf5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0xb7, 0xb9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4]" + + - + input: + bytes: [ 0xb7, 0xb9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4]" + + - + input: + bytes: [ 0x18, 0x10, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x18, 0x10, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x1d, 0x51, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x1d, 0x51, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x9f, 0x71, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x9f, 0x71, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x9f, 0x73, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x9f, 0x73, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x1d, 0x12, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x1d, 0x12, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x19, 0x10, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x19, 0x10, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x18, 0x52, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x18, 0x52, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x98, 0x11, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x98, 0x11, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x19, 0x50, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x19, 0x50, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x9d, 0x12, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x9d, 0x12, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x1a, 0x71, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x1a, 0x71, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x9f, 0x31, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x9f, 0x31, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2/bfmlsl.s.yaml b/tests/MC/AArch64/SME2/bfmlsl.s.yaml new file mode 100644 index 0000000000..8e07472f1b --- /dev/null +++ b/tests/MC/AArch64/SME2/bfmlsl.s.yaml @@ -0,0 +1,1680 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x0c, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1], z0.h, z0.h" + + - + input: + bytes: [ 0x5d, 0x4d, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 10:11], z10.h, z5.h" + + - + input: + bytes: [ 0xbf, 0x6d, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 14:15], z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0x6f, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 14:15], z31.h, z15.h" + + - + input: + bytes: [ 0x3d, 0x0e, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 10:11], z17.h, z0.h" + + - + input: + bytes: [ 0x39, 0x0c, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3], z1.h, z14.h" + + - + input: + bytes: [ 0x78, 0x4e, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 0:1], z19.h, z4.h" + + - + input: + bytes: [ 0x98, 0x0d, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1], z12.h, z2.h" + + - + input: + bytes: [ 0x39, 0x4c, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3], z1.h, z10.h" + + - + input: + bytes: [ 0xdd, 0x0e, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 10:11], z22.h, z14.h" + + - + input: + bytes: [ 0x3a, 0x6d, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 4:5], z9.h, z1.h" + + - + input: + bytes: [ 0x9f, 0x2d, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w9, 14:15], z12.h, z11.h" + + - + input: + bytes: [ 0x18, 0x10, 0x80, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1], z0.h, z0.h[0]" + + - + input: + bytes: [ 0x5d, 0x55, 0x85, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 10:11], z10.h, z5.h[1]" + + - + input: + bytes: [ 0xbf, 0xfd, 0x88, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 14:15], z13.h, z8.h[7]" + + - + input: + bytes: [ 0xff, 0xff, 0x8f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 14:15], z31.h, z15.h[7]" + + - + input: + bytes: [ 0x3d, 0x1e, 0x80, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 10:11], z17.h, z0.h[3]" + + - + input: + bytes: [ 0x39, 0x94, 0x8e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3], z1.h, z14.h[5]" + + - + input: + bytes: [ 0x78, 0x56, 0x84, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 0:1], z19.h, z4.h[1]" + + - + input: + bytes: [ 0x98, 0x19, 0x82, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1], z12.h, z2.h[2]" + + - + input: + bytes: [ 0x39, 0xd8, 0x8a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3], z1.h, z10.h[6]" + + - + input: + bytes: [ 0xdd, 0x1a, 0x8e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 10:11], z22.h, z14.h[2]" + + - + input: + bytes: [ 0x3a, 0xf5, 0x81, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 4:5], z9.h, z1.h[5]" + + - + input: + bytes: [ 0x9f, 0xb9, 0x8b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w9, 14:15], z12.h, z11.h[6]" + + - + input: + bytes: [ 0x18, 0x08, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x18, 0x08, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x59, 0x49, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x59, 0x49, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xbb, 0x69, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xbb, 0x69, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xfb, 0x6b, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xfb, 0x6b, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x39, 0x0a, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x39, 0x0a, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x39, 0x08, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x39, 0x08, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x78, 0x4a, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x78, 0x4a, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x98, 0x09, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x98, 0x09, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x39, 0x48, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x39, 0x48, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xd9, 0x0a, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xd9, 0x0a, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x3a, 0x69, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x3a, 0x69, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x9b, 0x29, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x9b, 0x29, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x18, 0x10, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x18, 0x10, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x5d, 0x55, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x5d, 0x55, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x9f, 0x7d, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0x9f, 0x7d, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0xdf, 0x7f, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0xdf, 0x7f, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x1d, 0x1e, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]" + + - + input: + bytes: [ 0x1d, 0x1e, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]" + + - + input: + bytes: [ 0x19, 0x14, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x19, 0x14, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x58, 0x56, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x58, 0x56, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x98, 0x19, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x98, 0x19, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x19, 0x58, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0x19, 0x58, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0xdd, 0x1a, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0xdd, 0x1a, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x1a, 0x75, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x1a, 0x75, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x9f, 0x39, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]" + + - + input: + bytes: [ 0x9f, 0x39, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]" + + - + input: + bytes: [ 0x18, 0x08, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x18, 0x08, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x59, 0x49, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x59, 0x49, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x9b, 0x69, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x9b, 0x69, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xdb, 0x6b, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xdb, 0x6b, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x19, 0x0a, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x19, 0x0a, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x19, 0x08, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x19, 0x08, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x58, 0x4a, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x58, 0x4a, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x98, 0x09, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x98, 0x09, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x19, 0x48, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x19, 0x48, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xd9, 0x0a, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xd9, 0x0a, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x1a, 0x69, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x1a, 0x69, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x9b, 0x29, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x9b, 0x29, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x18, 0x08, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x18, 0x08, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x59, 0x49, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x59, 0x49, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xbb, 0x69, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xbb, 0x69, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xfb, 0x6b, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xfb, 0x6b, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x39, 0x0a, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x39, 0x0a, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x39, 0x08, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x39, 0x08, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x78, 0x4a, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x78, 0x4a, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x98, 0x09, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x98, 0x09, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x39, 0x48, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x39, 0x48, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xd9, 0x0a, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xd9, 0x0a, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x3a, 0x69, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x3a, 0x69, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x9b, 0x29, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x9b, 0x29, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x18, 0x90, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x18, 0x90, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x1d, 0xd5, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x1d, 0xd5, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x9f, 0xfd, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x9f, 0xfd, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x9f, 0xff, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x9f, 0xff, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x1d, 0x9e, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]" + + - + input: + bytes: [ 0x1d, 0x9e, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]" + + - + input: + bytes: [ 0x19, 0x94, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x19, 0x94, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x18, 0xd6, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x18, 0xd6, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x98, 0x99, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x98, 0x99, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x19, 0xd8, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x19, 0xd8, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x9d, 0x9a, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x9d, 0x9a, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x1a, 0xf5, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x1a, 0xf5, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x9f, 0xb9, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]" + + - + input: + bytes: [ 0x9f, 0xb9, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]" + + - + input: + bytes: [ 0x18, 0x08, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x18, 0x08, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x19, 0x49, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x19, 0x49, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x9b, 0x69, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x9b, 0x69, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x9b, 0x6b, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x9b, 0x6b, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x19, 0x0a, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x19, 0x0a, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x19, 0x08, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x19, 0x08, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x18, 0x4a, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x18, 0x4a, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x98, 0x09, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x98, 0x09, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x19, 0x48, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x19, 0x48, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x99, 0x0a, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x99, 0x0a, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x1a, 0x69, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x1a, 0x69, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x9b, 0x29, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x9b, 0x29, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2/bfmopa.s.yaml b/tests/MC/AArch64/SME2/bfmopa.s.yaml new file mode 100644 index 0000000000..1b930d7731 --- /dev/null +++ b/tests/MC/AArch64/SME2/bfmopa.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x00, 0xa0, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmopa za0.h, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x49, 0x55, 0xb5, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmopa za1.h, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xa9, 0xed, 0xa8, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmopa za1.h, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xe9, 0xff, 0xbf, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmopa za1.h, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x29, 0x0e, 0xb0, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmopa za1.h, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x29, 0x84, 0xbe, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmopa za1.h, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x68, 0x56, 0xb4, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmopa za0.h, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x88, 0x19, 0xa2, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmopa za0.h, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x29, 0xc8, 0xba, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmopa za1.h, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xc9, 0x0a, 0xbe, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmopa za1.h, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x28, 0xf5, 0xa1, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmopa za0.h, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x89, 0xa9, 0xab, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmopa za1.h, p2/m, p5/m, z12.h, z11.h" diff --git a/tests/MC/AArch64/SME2/bfmops.s.yaml b/tests/MC/AArch64/SME2/bfmops.s.yaml new file mode 100644 index 0000000000..dd40d3e602 --- /dev/null +++ b/tests/MC/AArch64/SME2/bfmops.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x00, 0xa0, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmops za0.h, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x59, 0x55, 0xb5, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmops za1.h, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xb9, 0xed, 0xa8, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmops za1.h, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xf9, 0xff, 0xbf, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmops za1.h, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x39, 0x0e, 0xb0, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmops za1.h, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x39, 0x84, 0xbe, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmops za1.h, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x78, 0x56, 0xb4, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmops za0.h, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x98, 0x19, 0xa2, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmops za0.h, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x39, 0xc8, 0xba, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmops za1.h, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xd9, 0x0a, 0xbe, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmops za1.h, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x38, 0xf5, 0xa1, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmops za0.h, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x99, 0xa9, 0xab, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmops za1.h, p2/m, p5/m, z12.h, z11.h" diff --git a/tests/MC/AArch64/SME2/bfsub.s.yaml b/tests/MC/AArch64/SME2/bfsub.s.yaml new file mode 100644 index 0000000000..48ebb3c432 --- /dev/null +++ b/tests/MC/AArch64/SME2/bfsub.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x1c, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 0, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0x08, 0x1c, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 0, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0x4d, 0x5d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w10, 5, vgx2], { z10.h, z11.h }" + + - + input: + bytes: [ 0x4d, 0x5d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w10, 5, vgx2], { z10.h, z11.h }" + + - + input: + bytes: [ 0x8f, 0x7d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w11, 7, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x8f, 0x7d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w11, 7, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0xcf, 0x7f, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w11, 7, vgx2], { z30.h, z31.h }" + + - + input: + bytes: [ 0xcf, 0x7f, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w11, 7, vgx2], { z30.h, z31.h }" + + - + input: + bytes: [ 0x0d, 0x1e, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 5, vgx2], { z16.h, z17.h }" + + - + input: + bytes: [ 0x0d, 0x1e, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 5, vgx2], { z16.h, z17.h }" + + - + input: + bytes: [ 0x09, 0x1c, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 1, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0x09, 0x1c, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 1, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0x48, 0x5e, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w10, 0, vgx2], { z18.h, z19.h }" + + - + input: + bytes: [ 0x48, 0x5e, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w10, 0, vgx2], { z18.h, z19.h }" + + - + input: + bytes: [ 0x88, 0x1d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 0, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x88, 0x1d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 0, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x09, 0x5c, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w10, 1, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0x09, 0x5c, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w10, 1, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0xcd, 0x1e, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 5, vgx2], { z22.h, z23.h }" + + - + input: + bytes: [ 0xcd, 0x1e, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 5, vgx2], { z22.h, z23.h }" + + - + input: + bytes: [ 0x0a, 0x7d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w11, 2, vgx2], { z8.h, z9.h }" + + - + input: + bytes: [ 0x0a, 0x7d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w11, 2, vgx2], { z8.h, z9.h }" + + - + input: + bytes: [ 0x8f, 0x3d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w9, 7, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x8f, 0x3d, 0xe4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w9, 7, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x08, 0x1c, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 0, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x08, 0x1c, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 0, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x0d, 0x5d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w10, 5, vgx4], { z8.h - z11.h }" + + - + input: + bytes: [ 0x0d, 0x5d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w10, 5, vgx4], { z8.h - z11.h }" + + - + input: + bytes: [ 0x8f, 0x7d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w11, 7, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x8f, 0x7d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w11, 7, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x8f, 0x7f, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w11, 7, vgx4], { z28.h - z31.h }" + + - + input: + bytes: [ 0x8f, 0x7f, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w11, 7, vgx4], { z28.h - z31.h }" + + - + input: + bytes: [ 0x0d, 0x1e, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 5, vgx4], { z16.h - z19.h }" + + - + input: + bytes: [ 0x0d, 0x1e, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 5, vgx4], { z16.h - z19.h }" + + - + input: + bytes: [ 0x09, 0x1c, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 1, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x09, 0x1c, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 1, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x08, 0x5e, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w10, 0, vgx4], { z16.h - z19.h }" + + - + input: + bytes: [ 0x08, 0x5e, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w10, 0, vgx4], { z16.h - z19.h }" + + - + input: + bytes: [ 0x88, 0x1d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 0, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x88, 0x1d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 0, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x09, 0x5c, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w10, 1, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x09, 0x5c, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w10, 1, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x8d, 0x1e, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 5, vgx4], { z20.h - z23.h }" + + - + input: + bytes: [ 0x8d, 0x1e, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w8, 5, vgx4], { z20.h - z23.h }" + + - + input: + bytes: [ 0x0a, 0x7d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w11, 2, vgx4], { z8.h - z11.h }" + + - + input: + bytes: [ 0x0a, 0x7d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w11, 2, vgx4], { z8.h - z11.h }" + + - + input: + bytes: [ 0x8f, 0x3d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w9, 7, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x8f, 0x3d, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub za.h[w9, 7, vgx4], { z12.h - z15.h }" diff --git a/tests/MC/AArch64/SME2/bfvdot.s.yaml b/tests/MC/AArch64/SME2/bfvdot.s.yaml new file mode 100644 index 0000000000..f068776e9b --- /dev/null +++ b/tests/MC/AArch64/SME2/bfvdot.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x00, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x18, 0x00, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x5d, 0x45, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x5d, 0x45, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x9f, 0x6d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]" + + - + input: + bytes: [ 0x9f, 0x6d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]" + + - + input: + bytes: [ 0xdf, 0x6f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]" + + - + input: + bytes: [ 0xdf, 0x6f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]" + + - + input: + bytes: [ 0x1d, 0x0e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]" + + - + input: + bytes: [ 0x1d, 0x0e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]" + + - + input: + bytes: [ 0x19, 0x04, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x19, 0x04, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x58, 0x46, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x58, 0x46, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x98, 0x09, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]" + + - + input: + bytes: [ 0x98, 0x09, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]" + + - + input: + bytes: [ 0x19, 0x48, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]" + + - + input: + bytes: [ 0x19, 0x48, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]" + + - + input: + bytes: [ 0xdd, 0x0a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0xdd, 0x0a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x1a, 0x65, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0x1a, 0x65, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0x9f, 0x29, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]" + + - + input: + bytes: [ 0x9f, 0x29, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]" diff --git a/tests/MC/AArch64/SME2/bmopa.s.yaml b/tests/MC/AArch64/SME2/bmopa.s.yaml new file mode 100644 index 0000000000..e257e4fc57 --- /dev/null +++ b/tests/MC/AArch64/SME2/bmopa.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x00, 0x80, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmopa za0.s, p0/m, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x49, 0x55, 0x95, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmopa za1.s, p5/m, p2/m, z10.s, z21.s" + + - + input: + bytes: [ 0xab, 0xed, 0x88, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmopa za3.s, p3/m, p7/m, z13.s, z8.s" + + - + input: + bytes: [ 0xeb, 0xff, 0x9f, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmopa za3.s, p7/m, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0x29, 0x0e, 0x90, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmopa za1.s, p3/m, p0/m, z17.s, z16.s" + + - + input: + bytes: [ 0x29, 0x84, 0x9e, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmopa za1.s, p1/m, p4/m, z1.s, z30.s" + + - + input: + bytes: [ 0x68, 0x56, 0x94, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmopa za0.s, p5/m, p2/m, z19.s, z20.s" + + - + input: + bytes: [ 0x88, 0x19, 0x82, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmopa za0.s, p6/m, p0/m, z12.s, z2.s" + + - + input: + bytes: [ 0x29, 0xc8, 0x9a, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmopa za1.s, p2/m, p6/m, z1.s, z26.s" + + - + input: + bytes: [ 0xc9, 0x0a, 0x9e, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmopa za1.s, p2/m, p0/m, z22.s, z30.s" + + - + input: + bytes: [ 0x2a, 0xf5, 0x81, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmopa za2.s, p5/m, p7/m, z9.s, z1.s" + + - + input: + bytes: [ 0x8b, 0xa9, 0x8b, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmopa za3.s, p2/m, p5/m, z12.s, z11.s" diff --git a/tests/MC/AArch64/SME2/bmops.s.yaml b/tests/MC/AArch64/SME2/bmops.s.yaml new file mode 100644 index 0000000000..b38bff8223 --- /dev/null +++ b/tests/MC/AArch64/SME2/bmops.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x00, 0x80, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmops za0.s, p0/m, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x59, 0x55, 0x95, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmops za1.s, p5/m, p2/m, z10.s, z21.s" + + - + input: + bytes: [ 0xbb, 0xed, 0x88, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmops za3.s, p3/m, p7/m, z13.s, z8.s" + + - + input: + bytes: [ 0xfb, 0xff, 0x9f, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmops za3.s, p7/m, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0x39, 0x0e, 0x90, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmops za1.s, p3/m, p0/m, z17.s, z16.s" + + - + input: + bytes: [ 0x39, 0x84, 0x9e, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmops za1.s, p1/m, p4/m, z1.s, z30.s" + + - + input: + bytes: [ 0x78, 0x56, 0x94, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmops za0.s, p5/m, p2/m, z19.s, z20.s" + + - + input: + bytes: [ 0x98, 0x19, 0x82, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmops za0.s, p6/m, p0/m, z12.s, z2.s" + + - + input: + bytes: [ 0x39, 0xc8, 0x9a, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmops za1.s, p2/m, p6/m, z1.s, z26.s" + + - + input: + bytes: [ 0xd9, 0x0a, 0x9e, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmops za1.s, p2/m, p0/m, z22.s, z30.s" + + - + input: + bytes: [ 0x3a, 0xf5, 0x81, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmops za2.s, p5/m, p7/m, z9.s, z1.s" + + - + input: + bytes: [ 0x9b, 0xa9, 0x8b, 0x80 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bmops za3.s, p2/m, p5/m, z12.s, z11.s" diff --git a/tests/MC/AArch64/SME2/fadd.s.yaml b/tests/MC/AArch64/SME2/fadd.s.yaml new file mode 100644 index 0000000000..d829bb48e3 --- /dev/null +++ b/tests/MC/AArch64/SME2/fadd.s.yaml @@ -0,0 +1,960 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x1c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 0, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x00, 0x1c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 0, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x45, 0x5d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w10, 5, vgx2], { z10.d, z11.d }" + + - + input: + bytes: [ 0x45, 0x5d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w10, 5, vgx2], { z10.d, z11.d }" + + - + input: + bytes: [ 0x87, 0x7d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w11, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x87, 0x7d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w11, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0xc7, 0x7f, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w11, 7, vgx2], { z30.d, z31.d }" + + - + input: + bytes: [ 0xc7, 0x7f, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w11, 7, vgx2], { z30.d, z31.d }" + + - + input: + bytes: [ 0x05, 0x1e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 5, vgx2], { z16.d, z17.d }" + + - + input: + bytes: [ 0x05, 0x1e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 5, vgx2], { z16.d, z17.d }" + + - + input: + bytes: [ 0x01, 0x1c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x01, 0x1c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x40, 0x5e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w10, 0, vgx2], { z18.d, z19.d }" + + - + input: + bytes: [ 0x40, 0x5e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w10, 0, vgx2], { z18.d, z19.d }" + + - + input: + bytes: [ 0x80, 0x1d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 0, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x80, 0x1d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 0, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x01, 0x5c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w10, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x01, 0x5c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w10, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0xc5, 0x1e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 5, vgx2], { z22.d, z23.d }" + + - + input: + bytes: [ 0xc5, 0x1e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 5, vgx2], { z22.d, z23.d }" + + - + input: + bytes: [ 0x02, 0x7d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w11, 2, vgx2], { z8.d, z9.d }" + + - + input: + bytes: [ 0x02, 0x7d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w11, 2, vgx2], { z8.d, z9.d }" + + - + input: + bytes: [ 0x87, 0x3d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w9, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x87, 0x3d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w9, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x00, 0x1c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 0, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x00, 0x1c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 0, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x45, 0x5d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w10, 5, vgx2], { z10.s, z11.s }" + + - + input: + bytes: [ 0x45, 0x5d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w10, 5, vgx2], { z10.s, z11.s }" + + - + input: + bytes: [ 0x87, 0x7d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w11, 7, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0x87, 0x7d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w11, 7, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0xc7, 0x7f, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w11, 7, vgx2], { z30.s, z31.s }" + + - + input: + bytes: [ 0xc7, 0x7f, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w11, 7, vgx2], { z30.s, z31.s }" + + - + input: + bytes: [ 0x05, 0x1e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 5, vgx2], { z16.s, z17.s }" + + - + input: + bytes: [ 0x05, 0x1e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 5, vgx2], { z16.s, z17.s }" + + - + input: + bytes: [ 0x01, 0x1c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 1, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x01, 0x1c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 1, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x40, 0x5e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w10, 0, vgx2], { z18.s, z19.s }" + + - + input: + bytes: [ 0x40, 0x5e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w10, 0, vgx2], { z18.s, z19.s }" + + - + input: + bytes: [ 0x80, 0x1d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 0, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0x80, 0x1d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 0, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0x01, 0x5c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w10, 1, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x01, 0x5c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w10, 1, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0xc5, 0x1e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 5, vgx2], { z22.s, z23.s }" + + - + input: + bytes: [ 0xc5, 0x1e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 5, vgx2], { z22.s, z23.s }" + + - + input: + bytes: [ 0x02, 0x7d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w11, 2, vgx2], { z8.s, z9.s }" + + - + input: + bytes: [ 0x02, 0x7d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w11, 2, vgx2], { z8.s, z9.s }" + + - + input: + bytes: [ 0x87, 0x3d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w9, 7, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0x87, 0x3d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w9, 7, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0x00, 0x1c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 0, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x00, 0x1c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 0, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x05, 0x5d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w10, 5, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x05, 0x5d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w10, 5, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x87, 0x7d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w11, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x87, 0x7d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w11, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x87, 0x7f, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w11, 7, vgx4], { z28.d - z31.d }" + + - + input: + bytes: [ 0x87, 0x7f, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w11, 7, vgx4], { z28.d - z31.d }" + + - + input: + bytes: [ 0x05, 0x1e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 5, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x05, 0x1e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 5, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x01, 0x1c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x01, 0x1c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x00, 0x5e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w10, 0, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x00, 0x5e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w10, 0, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x80, 0x1d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 0, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x80, 0x1d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 0, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x01, 0x5c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w10, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x01, 0x5c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w10, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x85, 0x1e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 5, vgx4], { z20.d - z23.d }" + + - + input: + bytes: [ 0x85, 0x1e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w8, 5, vgx4], { z20.d - z23.d }" + + - + input: + bytes: [ 0x02, 0x7d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w11, 2, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x02, 0x7d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w11, 2, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x87, 0x3d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w9, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x87, 0x3d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.d[w9, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x00, 0x1c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 0, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x00, 0x1c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 0, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x05, 0x5d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w10, 5, vgx4], { z8.s - z11.s }" + + - + input: + bytes: [ 0x05, 0x5d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w10, 5, vgx4], { z8.s - z11.s }" + + - + input: + bytes: [ 0x87, 0x7d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w11, 7, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x87, 0x7d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w11, 7, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x87, 0x7f, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w11, 7, vgx4], { z28.s - z31.s }" + + - + input: + bytes: [ 0x87, 0x7f, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w11, 7, vgx4], { z28.s - z31.s }" + + - + input: + bytes: [ 0x05, 0x1e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 5, vgx4], { z16.s - z19.s }" + + - + input: + bytes: [ 0x05, 0x1e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 5, vgx4], { z16.s - z19.s }" + + - + input: + bytes: [ 0x01, 0x1c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 1, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x01, 0x1c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 1, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x00, 0x5e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w10, 0, vgx4], { z16.s - z19.s }" + + - + input: + bytes: [ 0x00, 0x5e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w10, 0, vgx4], { z16.s - z19.s }" + + - + input: + bytes: [ 0x80, 0x1d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 0, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x80, 0x1d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 0, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x01, 0x5c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w10, 1, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x01, 0x5c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w10, 1, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x85, 0x1e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 5, vgx4], { z20.s - z23.s }" + + - + input: + bytes: [ 0x85, 0x1e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w8, 5, vgx4], { z20.s - z23.s }" + + - + input: + bytes: [ 0x02, 0x7d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w11, 2, vgx4], { z8.s - z11.s }" + + - + input: + bytes: [ 0x02, 0x7d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w11, 2, vgx4], { z8.s - z11.s }" + + - + input: + bytes: [ 0x87, 0x3d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w9, 7, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x87, 0x3d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fadd za.s[w9, 7, vgx4], { z12.s - z15.s }" diff --git a/tests/MC/AArch64/SME2/fclamp.s.yaml b/tests/MC/AArch64/SME2/fclamp.s.yaml new file mode 100644 index 0000000000..5c4d8d3cb2 --- /dev/null +++ b/tests/MC/AArch64/SME2/fclamp.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z0.d, z1.d }, z0.d, z0.d" + + - + input: + bytes: [ 0x54, 0xc1, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z20.d, z21.d }, z10.d, z21.d" + + - + input: + bytes: [ 0xb6, 0xc1, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z22.d, z23.d }, z13.d, z8.d" + + - + input: + bytes: [ 0xfe, 0xc3, 0xff, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z30.d, z31.d }, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0xc0, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z0.h, z1.h }, z0.h, z0.h" + + - + input: + bytes: [ 0x54, 0xc1, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z20.h, z21.h }, z10.h, z21.h" + + - + input: + bytes: [ 0xb6, 0xc1, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z22.h, z23.h }, z13.h, z8.h" + + - + input: + bytes: [ 0xfe, 0xc3, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z30.h, z31.h }, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0xc0, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z0.s, z1.s }, z0.s, z0.s" + + - + input: + bytes: [ 0x54, 0xc1, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z20.s, z21.s }, z10.s, z21.s" + + - + input: + bytes: [ 0xb6, 0xc1, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z22.s, z23.s }, z13.s, z8.s" + + - + input: + bytes: [ 0xfe, 0xc3, 0xbf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z30.s, z31.s }, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0xc8, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z0.d - z3.d }, z0.d, z0.d" + + - + input: + bytes: [ 0x54, 0xc9, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z20.d - z23.d }, z10.d, z21.d" + + - + input: + bytes: [ 0xb4, 0xc9, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z20.d - z23.d }, z13.d, z8.d" + + - + input: + bytes: [ 0xfc, 0xcb, 0xff, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z28.d - z31.d }, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0xc8, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z0.h - z3.h }, z0.h, z0.h" + + - + input: + bytes: [ 0x54, 0xc9, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z20.h - z23.h }, z10.h, z21.h" + + - + input: + bytes: [ 0xb4, 0xc9, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z20.h - z23.h }, z13.h, z8.h" + + - + input: + bytes: [ 0xfc, 0xcb, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z28.h - z31.h }, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0xc8, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z0.s - z3.s }, z0.s, z0.s" + + - + input: + bytes: [ 0x54, 0xc9, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z20.s - z23.s }, z10.s, z21.s" + + - + input: + bytes: [ 0xb4, 0xc9, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z20.s - z23.s }, z13.s, z8.s" + + - + input: + bytes: [ 0xfc, 0xcb, 0xbf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp { z28.s - z31.s }, z31.s, z31.s" diff --git a/tests/MC/AArch64/SME2/fcvt.s.yaml b/tests/MC/AArch64/SME2/fcvt.s.yaml new file mode 100644 index 0000000000..a6c87c625c --- /dev/null +++ b/tests/MC/AArch64/SME2/fcvt.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvt z0.h, { z0.s, z1.s }" + + - + input: + bytes: [ 0x55, 0xe1, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvt z21.h, { z10.s, z11.s }" + + - + input: + bytes: [ 0x97, 0xe1, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvt z23.h, { z12.s, z13.s }" + + - + input: + bytes: [ 0xdf, 0xe3, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvt z31.h, { z30.s, z31.s }" diff --git a/tests/MC/AArch64/SME2/fcvtn.s.yaml b/tests/MC/AArch64/SME2/fcvtn.s.yaml new file mode 100644 index 0000000000..58214af160 --- /dev/null +++ b/tests/MC/AArch64/SME2/fcvtn.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xe0, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtn z0.h, { z0.s, z1.s }" + + - + input: + bytes: [ 0x75, 0xe1, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtn z21.h, { z10.s, z11.s }" + + - + input: + bytes: [ 0xb7, 0xe1, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtn z23.h, { z12.s, z13.s }" + + - + input: + bytes: [ 0xff, 0xe3, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtn z31.h, { z30.s, z31.s }" diff --git a/tests/MC/AArch64/SME2/fcvtzs.s.yaml b/tests/MC/AArch64/SME2/fcvtzs.s.yaml new file mode 100644 index 0000000000..873341955a --- /dev/null +++ b/tests/MC/AArch64/SME2/fcvtzs.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtzs { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x54, 0xe1, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtzs { z20.s, z21.s }, { z10.s, z11.s }" + + - + input: + bytes: [ 0x96, 0xe1, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtzs { z22.s, z23.s }, { z12.s, z13.s }" + + - + input: + bytes: [ 0xde, 0xe3, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtzs { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x00, 0xe0, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtzs { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x14, 0xe1, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtzs { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x94, 0xe1, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtzs { z20.s - z23.s }, { z12.s - z15.s }" + + - + input: + bytes: [ 0x9c, 0xe3, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtzs { z28.s - z31.s }, { z28.s - z31.s }" diff --git a/tests/MC/AArch64/SME2/fcvtzu.s.yaml b/tests/MC/AArch64/SME2/fcvtzu.s.yaml new file mode 100644 index 0000000000..2c6b4a3d3f --- /dev/null +++ b/tests/MC/AArch64/SME2/fcvtzu.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xe0, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtzu { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x74, 0xe1, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtzu { z20.s, z21.s }, { z10.s, z11.s }" + + - + input: + bytes: [ 0xb6, 0xe1, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtzu { z22.s, z23.s }, { z12.s, z13.s }" + + - + input: + bytes: [ 0xfe, 0xe3, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtzu { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x20, 0xe0, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtzu { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x34, 0xe1, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtzu { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0xb4, 0xe1, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtzu { z20.s - z23.s }, { z12.s - z15.s }" + + - + input: + bytes: [ 0xbc, 0xe3, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fcvtzu { z28.s - z31.s }, { z28.s - z31.s }" diff --git a/tests/MC/AArch64/SME2/fdot.s.yaml b/tests/MC/AArch64/SME2/fdot.s.yaml new file mode 100644 index 0000000000..8a069140aa --- /dev/null +++ b/tests/MC/AArch64/SME2/fdot.s.yaml @@ -0,0 +1,1440 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x10, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x00, 0x10, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x45, 0x51, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x45, 0x51, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xa7, 0x71, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xa7, 0x71, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xe7, 0x73, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xe7, 0x73, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x25, 0x12, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x25, 0x12, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x10, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x21, 0x10, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x60, 0x52, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x60, 0x52, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x80, 0x11, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x80, 0x11, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x21, 0x50, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x21, 0x50, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xc5, 0x12, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xc5, 0x12, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x22, 0x71, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x22, 0x71, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x87, 0x31, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x87, 0x31, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x08, 0x10, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x08, 0x10, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x4d, 0x55, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x4d, 0x55, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x8f, 0x7d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]" + + - + input: + bytes: [ 0x8f, 0x7d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]" + + - + input: + bytes: [ 0xcf, 0x7f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]" + + - + input: + bytes: [ 0xcf, 0x7f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]" + + - + input: + bytes: [ 0x0d, 0x1e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]" + + - + input: + bytes: [ 0x0d, 0x1e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]" + + - + input: + bytes: [ 0x09, 0x14, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x09, 0x14, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x48, 0x56, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x48, 0x56, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x88, 0x19, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]" + + - + input: + bytes: [ 0x88, 0x19, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]" + + - + input: + bytes: [ 0x09, 0x58, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]" + + - + input: + bytes: [ 0x09, 0x58, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]" + + - + input: + bytes: [ 0xcd, 0x1a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0xcd, 0x1a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x0a, 0x75, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0x0a, 0x75, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0x8f, 0x39, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]" + + - + input: + bytes: [ 0x8f, 0x39, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]" + + - + input: + bytes: [ 0x00, 0x10, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x00, 0x10, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x45, 0x51, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x45, 0x51, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x87, 0x71, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x87, 0x71, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xc7, 0x73, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xc7, 0x73, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x05, 0x12, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x05, 0x12, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x01, 0x10, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x01, 0x10, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x40, 0x52, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x40, 0x52, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x80, 0x11, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x80, 0x11, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x01, 0x50, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x01, 0x50, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xc5, 0x12, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xc5, 0x12, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x02, 0x71, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x02, 0x71, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x87, 0x31, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x87, 0x31, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x00, 0x10, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x00, 0x10, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x45, 0x51, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x45, 0x51, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xa7, 0x71, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xa7, 0x71, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xe7, 0x73, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xe7, 0x73, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x25, 0x12, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x25, 0x12, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x10, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x21, 0x10, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x60, 0x52, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x60, 0x52, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x80, 0x11, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x80, 0x11, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x21, 0x50, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x21, 0x50, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xc5, 0x12, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xc5, 0x12, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x22, 0x71, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x22, 0x71, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x87, 0x31, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x87, 0x31, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x08, 0x90, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x08, 0x90, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x0d, 0xd5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x0d, 0xd5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x8f, 0xfd, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]" + + - + input: + bytes: [ 0x8f, 0xfd, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]" + + - + input: + bytes: [ 0x8f, 0xff, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]" + + - + input: + bytes: [ 0x8f, 0xff, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]" + + - + input: + bytes: [ 0x0d, 0x9e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]" + + - + input: + bytes: [ 0x0d, 0x9e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]" + + - + input: + bytes: [ 0x09, 0x94, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]" + + - + input: + bytes: [ 0x09, 0x94, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]" + + - + input: + bytes: [ 0x08, 0xd6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x08, 0xd6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x88, 0x99, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]" + + - + input: + bytes: [ 0x88, 0x99, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]" + + - + input: + bytes: [ 0x09, 0xd8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]" + + - + input: + bytes: [ 0x09, 0xd8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]" + + - + input: + bytes: [ 0x8d, 0x9a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x8d, 0x9a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x0a, 0xf5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]" + + - + input: + bytes: [ 0x0a, 0xf5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]" + + - + input: + bytes: [ 0x8f, 0xb9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]" + + - + input: + bytes: [ 0x8f, 0xb9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]" + + - + input: + bytes: [ 0x00, 0x10, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x00, 0x10, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x05, 0x51, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x05, 0x51, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x87, 0x71, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x87, 0x71, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x87, 0x73, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x87, 0x73, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x05, 0x12, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x05, 0x12, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x01, 0x10, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x01, 0x10, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x00, 0x52, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x00, 0x52, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x80, 0x11, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x80, 0x11, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x01, 0x50, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x01, 0x50, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x85, 0x12, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x85, 0x12, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x02, 0x71, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x02, 0x71, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x87, 0x31, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x87, 0x31, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot za.s[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2/feature-sme2-implies-sme.s.yaml b/tests/MC/AArch64/SME2/feature-sme2-implies-sme.s.yaml new file mode 100644 index 0000000000..14e92c0c2e --- /dev/null +++ b/tests/MC/AArch64/SME2/feature-sme2-implies-sme.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x90, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "addha za0.s, p0/m, p0/m, z0.s" diff --git a/tests/MC/AArch64/SME2/fmax.s.yaml b/tests/MC/AArch64/SME2/fmax.s.yaml new file mode 100644 index 0000000000..fbf7b486d9 --- /dev/null +++ b/tests/MC/AArch64/SME2/fmax.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa1, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z0.d, z1.d }, { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x14, 0xa1, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z20.d, z21.d }, { z20.d, z21.d }, z5.d" + + - + input: + bytes: [ 0x16, 0xa1, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z22.d, z23.d }, { z22.d, z23.d }, z8.d" + + - + input: + bytes: [ 0x1e, 0xa1, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z30.d, z31.d }, { z30.d, z31.d }, z15.d" + + - + input: + bytes: [ 0x00, 0xb1, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x14, 0xb1, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x16, 0xb1, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0x1e, 0xb1, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x00, 0xa1, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z0.h, z1.h }, { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x14, 0xa1, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z20.h, z21.h }, { z20.h, z21.h }, z5.h" + + - + input: + bytes: [ 0x16, 0xa1, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z22.h, z23.h }, { z22.h, z23.h }, z8.h" + + - + input: + bytes: [ 0x1e, 0xa1, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z30.h, z31.h }, { z30.h, z31.h }, z15.h" + + - + input: + bytes: [ 0x00, 0xb1, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x14, 0xb1, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x16, 0xb1, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x1e, 0xb1, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x00, 0xa1, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z0.s, z1.s }, { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x14, 0xa1, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z20.s, z21.s }, { z20.s, z21.s }, z5.s" + + - + input: + bytes: [ 0x16, 0xa1, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z22.s, z23.s }, { z22.s, z23.s }, z8.s" + + - + input: + bytes: [ 0x1e, 0xa1, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z30.s, z31.s }, { z30.s, z31.s }, z15.s" + + - + input: + bytes: [ 0x00, 0xb1, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x14, 0xb1, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x16, 0xb1, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0x1e, 0xb1, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x00, 0xa9, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z0.d - z3.d }, { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x14, 0xa9, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z20.d - z23.d }, { z20.d - z23.d }, z5.d" + + - + input: + bytes: [ 0x14, 0xa9, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z20.d - z23.d }, { z20.d - z23.d }, z8.d" + + - + input: + bytes: [ 0x1c, 0xa9, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z28.d - z31.d }, { z28.d - z31.d }, z15.d" + + - + input: + bytes: [ 0x00, 0xb9, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x14, 0xb9, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x14, 0xb9, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x1c, 0xb9, 0xfc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x00, 0xa9, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z0.h - z3.h }, { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x14, 0xa9, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z20.h - z23.h }, { z20.h - z23.h }, z5.h" + + - + input: + bytes: [ 0x14, 0xa9, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z20.h - z23.h }, { z20.h - z23.h }, z8.h" + + - + input: + bytes: [ 0x1c, 0xa9, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z28.h - z31.h }, { z28.h - z31.h }, z15.h" + + - + input: + bytes: [ 0x00, 0xb9, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x14, 0xb9, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x14, 0xb9, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x1c, 0xb9, 0x7c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x00, 0xa9, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z0.s - z3.s }, { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x14, 0xa9, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z20.s - z23.s }, { z20.s - z23.s }, z5.s" + + - + input: + bytes: [ 0x14, 0xa9, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z20.s - z23.s }, { z20.s - z23.s }, z8.s" + + - + input: + bytes: [ 0x1c, 0xa9, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z28.s - z31.s }, { z28.s - z31.s }, z15.s" + + - + input: + bytes: [ 0x00, 0xb9, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x14, 0xb9, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x14, 0xb9, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x1c, 0xb9, 0xbc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmax { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }" diff --git a/tests/MC/AArch64/SME2/fmaxnm.s.yaml b/tests/MC/AArch64/SME2/fmaxnm.s.yaml new file mode 100644 index 0000000000..4e7ab36600 --- /dev/null +++ b/tests/MC/AArch64/SME2/fmaxnm.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa1, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z0.d, z1.d }, { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x34, 0xa1, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z20.d, z21.d }, { z20.d, z21.d }, z5.d" + + - + input: + bytes: [ 0x36, 0xa1, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z22.d, z23.d }, { z22.d, z23.d }, z8.d" + + - + input: + bytes: [ 0x3e, 0xa1, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z30.d, z31.d }, { z30.d, z31.d }, z15.d" + + - + input: + bytes: [ 0x20, 0xb1, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x34, 0xb1, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x36, 0xb1, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0x3e, 0xb1, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x20, 0xa1, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z0.h, z1.h }, { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x34, 0xa1, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z20.h, z21.h }, { z20.h, z21.h }, z5.h" + + - + input: + bytes: [ 0x36, 0xa1, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z22.h, z23.h }, { z22.h, z23.h }, z8.h" + + - + input: + bytes: [ 0x3e, 0xa1, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z30.h, z31.h }, { z30.h, z31.h }, z15.h" + + - + input: + bytes: [ 0x20, 0xb1, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x34, 0xb1, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x36, 0xb1, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x3e, 0xb1, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x20, 0xa1, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z0.s, z1.s }, { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x34, 0xa1, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z20.s, z21.s }, { z20.s, z21.s }, z5.s" + + - + input: + bytes: [ 0x36, 0xa1, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z22.s, z23.s }, { z22.s, z23.s }, z8.s" + + - + input: + bytes: [ 0x3e, 0xa1, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z30.s, z31.s }, { z30.s, z31.s }, z15.s" + + - + input: + bytes: [ 0x20, 0xb1, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x34, 0xb1, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x36, 0xb1, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0x3e, 0xb1, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x20, 0xa9, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z0.d - z3.d }, { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x34, 0xa9, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z20.d - z23.d }, { z20.d - z23.d }, z5.d" + + - + input: + bytes: [ 0x34, 0xa9, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z20.d - z23.d }, { z20.d - z23.d }, z8.d" + + - + input: + bytes: [ 0x3c, 0xa9, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z28.d - z31.d }, { z28.d - z31.d }, z15.d" + + - + input: + bytes: [ 0x20, 0xb9, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x34, 0xb9, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x34, 0xb9, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x3c, 0xb9, 0xfc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x20, 0xa9, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z0.h - z3.h }, { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x34, 0xa9, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z20.h - z23.h }, { z20.h - z23.h }, z5.h" + + - + input: + bytes: [ 0x34, 0xa9, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z20.h - z23.h }, { z20.h - z23.h }, z8.h" + + - + input: + bytes: [ 0x3c, 0xa9, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z28.h - z31.h }, { z28.h - z31.h }, z15.h" + + - + input: + bytes: [ 0x20, 0xb9, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x34, 0xb9, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x34, 0xb9, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x3c, 0xb9, 0x7c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x20, 0xa9, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z0.s - z3.s }, { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x34, 0xa9, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z20.s - z23.s }, { z20.s - z23.s }, z5.s" + + - + input: + bytes: [ 0x34, 0xa9, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z20.s - z23.s }, { z20.s - z23.s }, z8.s" + + - + input: + bytes: [ 0x3c, 0xa9, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z28.s - z31.s }, { z28.s - z31.s }, z15.s" + + - + input: + bytes: [ 0x20, 0xb9, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x34, 0xb9, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x34, 0xb9, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x3c, 0xb9, 0xbc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmaxnm { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }" diff --git a/tests/MC/AArch64/SME2/fmin.s.yaml b/tests/MC/AArch64/SME2/fmin.s.yaml new file mode 100644 index 0000000000..b5db8d4792 --- /dev/null +++ b/tests/MC/AArch64/SME2/fmin.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x01, 0xa1, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z0.d, z1.d }, { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x15, 0xa1, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z20.d, z21.d }, { z20.d, z21.d }, z5.d" + + - + input: + bytes: [ 0x17, 0xa1, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z22.d, z23.d }, { z22.d, z23.d }, z8.d" + + - + input: + bytes: [ 0x1f, 0xa1, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z30.d, z31.d }, { z30.d, z31.d }, z15.d" + + - + input: + bytes: [ 0x01, 0xb1, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x15, 0xb1, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x17, 0xb1, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0x1f, 0xb1, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x01, 0xa1, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z0.h, z1.h }, { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x15, 0xa1, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z20.h, z21.h }, { z20.h, z21.h }, z5.h" + + - + input: + bytes: [ 0x17, 0xa1, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z22.h, z23.h }, { z22.h, z23.h }, z8.h" + + - + input: + bytes: [ 0x1f, 0xa1, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z30.h, z31.h }, { z30.h, z31.h }, z15.h" + + - + input: + bytes: [ 0x01, 0xb1, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x15, 0xb1, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x17, 0xb1, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x1f, 0xb1, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x01, 0xa1, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z0.s, z1.s }, { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x15, 0xa1, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z20.s, z21.s }, { z20.s, z21.s }, z5.s" + + - + input: + bytes: [ 0x17, 0xa1, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z22.s, z23.s }, { z22.s, z23.s }, z8.s" + + - + input: + bytes: [ 0x1f, 0xa1, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z30.s, z31.s }, { z30.s, z31.s }, z15.s" + + - + input: + bytes: [ 0x01, 0xb1, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x15, 0xb1, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x17, 0xb1, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0x1f, 0xb1, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x01, 0xa9, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z0.d - z3.d }, { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x15, 0xa9, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z20.d - z23.d }, { z20.d - z23.d }, z5.d" + + - + input: + bytes: [ 0x15, 0xa9, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z20.d - z23.d }, { z20.d - z23.d }, z8.d" + + - + input: + bytes: [ 0x1d, 0xa9, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z28.d - z31.d }, { z28.d - z31.d }, z15.d" + + - + input: + bytes: [ 0x01, 0xb9, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x15, 0xb9, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x15, 0xb9, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x1d, 0xb9, 0xfc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x01, 0xa9, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z0.h - z3.h }, { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x15, 0xa9, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z20.h - z23.h }, { z20.h - z23.h }, z5.h" + + - + input: + bytes: [ 0x15, 0xa9, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z20.h - z23.h }, { z20.h - z23.h }, z8.h" + + - + input: + bytes: [ 0x1d, 0xa9, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z28.h - z31.h }, { z28.h - z31.h }, z15.h" + + - + input: + bytes: [ 0x01, 0xb9, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x15, 0xb9, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x15, 0xb9, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x1d, 0xb9, 0x7c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x01, 0xa9, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z0.s - z3.s }, { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x15, 0xa9, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z20.s - z23.s }, { z20.s - z23.s }, z5.s" + + - + input: + bytes: [ 0x15, 0xa9, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z20.s - z23.s }, { z20.s - z23.s }, z8.s" + + - + input: + bytes: [ 0x1d, 0xa9, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z28.s - z31.s }, { z28.s - z31.s }, z15.s" + + - + input: + bytes: [ 0x01, 0xb9, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x15, 0xb9, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x15, 0xb9, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x1d, 0xb9, 0xbc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmin { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }" diff --git a/tests/MC/AArch64/SME2/fminnm.s.yaml b/tests/MC/AArch64/SME2/fminnm.s.yaml new file mode 100644 index 0000000000..9c332ef6ae --- /dev/null +++ b/tests/MC/AArch64/SME2/fminnm.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x21, 0xa1, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z0.d, z1.d }, { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x35, 0xa1, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z20.d, z21.d }, { z20.d, z21.d }, z5.d" + + - + input: + bytes: [ 0x37, 0xa1, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z22.d, z23.d }, { z22.d, z23.d }, z8.d" + + - + input: + bytes: [ 0x3f, 0xa1, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z30.d, z31.d }, { z30.d, z31.d }, z15.d" + + - + input: + bytes: [ 0x21, 0xb1, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x35, 0xb1, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x37, 0xb1, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0x3f, 0xb1, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x21, 0xa1, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z0.h, z1.h }, { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x35, 0xa1, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z20.h, z21.h }, { z20.h, z21.h }, z5.h" + + - + input: + bytes: [ 0x37, 0xa1, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z22.h, z23.h }, { z22.h, z23.h }, z8.h" + + - + input: + bytes: [ 0x3f, 0xa1, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z30.h, z31.h }, { z30.h, z31.h }, z15.h" + + - + input: + bytes: [ 0x21, 0xb1, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x35, 0xb1, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x37, 0xb1, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x3f, 0xb1, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x21, 0xa1, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z0.s, z1.s }, { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x35, 0xa1, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z20.s, z21.s }, { z20.s, z21.s }, z5.s" + + - + input: + bytes: [ 0x37, 0xa1, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z22.s, z23.s }, { z22.s, z23.s }, z8.s" + + - + input: + bytes: [ 0x3f, 0xa1, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z30.s, z31.s }, { z30.s, z31.s }, z15.s" + + - + input: + bytes: [ 0x21, 0xb1, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x35, 0xb1, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x37, 0xb1, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0x3f, 0xb1, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x21, 0xa9, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z0.d - z3.d }, { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x35, 0xa9, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z20.d - z23.d }, { z20.d - z23.d }, z5.d" + + - + input: + bytes: [ 0x35, 0xa9, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z20.d - z23.d }, { z20.d - z23.d }, z8.d" + + - + input: + bytes: [ 0x3d, 0xa9, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z28.d - z31.d }, { z28.d - z31.d }, z15.d" + + - + input: + bytes: [ 0x21, 0xb9, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x35, 0xb9, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x35, 0xb9, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x3d, 0xb9, 0xfc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x21, 0xa9, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z0.h - z3.h }, { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x35, 0xa9, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z20.h - z23.h }, { z20.h - z23.h }, z5.h" + + - + input: + bytes: [ 0x35, 0xa9, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z20.h - z23.h }, { z20.h - z23.h }, z8.h" + + - + input: + bytes: [ 0x3d, 0xa9, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z28.h - z31.h }, { z28.h - z31.h }, z15.h" + + - + input: + bytes: [ 0x21, 0xb9, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x35, 0xb9, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x35, 0xb9, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x3d, 0xb9, 0x7c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x21, 0xa9, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z0.s - z3.s }, { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x35, 0xa9, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z20.s - z23.s }, { z20.s - z23.s }, z5.s" + + - + input: + bytes: [ 0x35, 0xa9, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z20.s - z23.s }, { z20.s - z23.s }, z8.s" + + - + input: + bytes: [ 0x3d, 0xa9, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z28.s - z31.s }, { z28.s - z31.s }, z15.s" + + - + input: + bytes: [ 0x21, 0xb9, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x35, 0xb9, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x35, 0xb9, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x3d, 0xb9, 0xbc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fminnm { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }" diff --git a/tests/MC/AArch64/SME2/fmla.s.yaml b/tests/MC/AArch64/SME2/fmla.s.yaml new file mode 100644 index 0000000000..1849c203a7 --- /dev/null +++ b/tests/MC/AArch64/SME2/fmla.s.yaml @@ -0,0 +1,2880 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x18, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x00, 0x18, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x45, 0x59, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d" + + - + input: + bytes: [ 0x45, 0x59, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d" + + - + input: + bytes: [ 0xa7, 0x79, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx2], { z13.d, z14.d }, z8.d" + + - + input: + bytes: [ 0xa7, 0x79, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx2], { z13.d, z14.d }, z8.d" + + - + input: + bytes: [ 0xe7, 0x7b, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx2], { z31.d, z0.d }, z15.d" + + - + input: + bytes: [ 0xe7, 0x7b, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx2], { z31.d, z0.d }, z15.d" + + - + input: + bytes: [ 0x25, 0x1a, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx2], { z17.d, z18.d }, z0.d" + + - + input: + bytes: [ 0x25, 0x1a, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx2], { z17.d, z18.d }, z0.d" + + - + input: + bytes: [ 0x21, 0x18, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 1, vgx2], { z1.d, z2.d }, z14.d" + + - + input: + bytes: [ 0x21, 0x18, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 1, vgx2], { z1.d, z2.d }, z14.d" + + - + input: + bytes: [ 0x60, 0x5a, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 0, vgx2], { z19.d, z20.d }, z4.d" + + - + input: + bytes: [ 0x60, 0x5a, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 0, vgx2], { z19.d, z20.d }, z4.d" + + - + input: + bytes: [ 0x80, 0x19, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d" + + - + input: + bytes: [ 0x80, 0x19, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d" + + - + input: + bytes: [ 0x21, 0x58, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 1, vgx2], { z1.d, z2.d }, z10.d" + + - + input: + bytes: [ 0x21, 0x58, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 1, vgx2], { z1.d, z2.d }, z10.d" + + - + input: + bytes: [ 0xc5, 0x1a, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d" + + - + input: + bytes: [ 0xc5, 0x1a, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d" + + - + input: + bytes: [ 0x22, 0x79, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 2, vgx2], { z9.d, z10.d }, z1.d" + + - + input: + bytes: [ 0x22, 0x79, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 2, vgx2], { z9.d, z10.d }, z1.d" + + - + input: + bytes: [ 0x87, 0x39, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d" + + - + input: + bytes: [ 0x87, 0x39, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d" + + - + input: + bytes: [ 0x00, 0x00, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d[0]" + + - + input: + bytes: [ 0x00, 0x00, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d[0]" + + - + input: + bytes: [ 0x45, 0x45, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d[1]" + + - + input: + bytes: [ 0x45, 0x45, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d[1]" + + - + input: + bytes: [ 0x87, 0x65, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx2], { z12.d, z13.d }, z8.d[1]" + + - + input: + bytes: [ 0x87, 0x65, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx2], { z12.d, z13.d }, z8.d[1]" + + - + input: + bytes: [ 0xc7, 0x67, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx2], { z30.d, z31.d }, z15.d[1]" + + - + input: + bytes: [ 0xc7, 0x67, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx2], { z30.d, z31.d }, z15.d[1]" + + - + input: + bytes: [ 0x05, 0x06, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx2], { z16.d, z17.d }, z0.d[1]" + + - + input: + bytes: [ 0x05, 0x06, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx2], { z16.d, z17.d }, z0.d[1]" + + - + input: + bytes: [ 0x01, 0x04, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 1, vgx2], { z0.d, z1.d }, z14.d[1]" + + - + input: + bytes: [ 0x01, 0x04, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 1, vgx2], { z0.d, z1.d }, z14.d[1]" + + - + input: + bytes: [ 0x40, 0x46, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 0, vgx2], { z18.d, z19.d }, z4.d[1]" + + - + input: + bytes: [ 0x40, 0x46, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 0, vgx2], { z18.d, z19.d }, z4.d[1]" + + - + input: + bytes: [ 0x80, 0x01, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d[0]" + + - + input: + bytes: [ 0x80, 0x01, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d[0]" + + - + input: + bytes: [ 0x01, 0x40, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 1, vgx2], { z0.d, z1.d }, z10.d[0]" + + - + input: + bytes: [ 0x01, 0x40, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 1, vgx2], { z0.d, z1.d }, z10.d[0]" + + - + input: + bytes: [ 0xc5, 0x02, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d[0]" + + - + input: + bytes: [ 0xc5, 0x02, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d[0]" + + - + input: + bytes: [ 0x02, 0x65, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 2, vgx2], { z8.d, z9.d }, z1.d[1]" + + - + input: + bytes: [ 0x02, 0x65, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 2, vgx2], { z8.d, z9.d }, z1.d[1]" + + - + input: + bytes: [ 0x87, 0x21, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d[0]" + + - + input: + bytes: [ 0x87, 0x21, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d[0]" + + - + input: + bytes: [ 0x00, 0x18, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x00, 0x18, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x45, 0x59, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x45, 0x59, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x87, 0x79, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0x87, 0x79, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0xc7, 0x7b, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0xc7, 0x7b, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x05, 0x1a, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }" + + - + input: + bytes: [ 0x05, 0x1a, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }" + + - + input: + bytes: [ 0x01, 0x18, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x01, 0x18, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x40, 0x5a, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x40, 0x5a, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x80, 0x19, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }" + + - + input: + bytes: [ 0x80, 0x19, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }" + + - + input: + bytes: [ 0x01, 0x58, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }" + + - + input: + bytes: [ 0x01, 0x58, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }" + + - + input: + bytes: [ 0xc5, 0x1a, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0xc5, 0x1a, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x02, 0x79, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x02, 0x79, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x87, 0x39, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }" + + - + input: + bytes: [ 0x87, 0x39, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }" + + - + input: + bytes: [ 0x00, 0x18, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x00, 0x18, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x45, 0x59, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s" + + - + input: + bytes: [ 0x45, 0x59, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s" + + - + input: + bytes: [ 0xa7, 0x79, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx2], { z13.s, z14.s }, z8.s" + + - + input: + bytes: [ 0xa7, 0x79, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx2], { z13.s, z14.s }, z8.s" + + - + input: + bytes: [ 0xe7, 0x7b, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx2], { z31.s, z0.s }, z15.s" + + - + input: + bytes: [ 0xe7, 0x7b, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx2], { z31.s, z0.s }, z15.s" + + - + input: + bytes: [ 0x25, 0x1a, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx2], { z17.s, z18.s }, z0.s" + + - + input: + bytes: [ 0x25, 0x1a, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx2], { z17.s, z18.s }, z0.s" + + - + input: + bytes: [ 0x21, 0x18, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 1, vgx2], { z1.s, z2.s }, z14.s" + + - + input: + bytes: [ 0x21, 0x18, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 1, vgx2], { z1.s, z2.s }, z14.s" + + - + input: + bytes: [ 0x60, 0x5a, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 0, vgx2], { z19.s, z20.s }, z4.s" + + - + input: + bytes: [ 0x60, 0x5a, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 0, vgx2], { z19.s, z20.s }, z4.s" + + - + input: + bytes: [ 0x80, 0x19, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s" + + - + input: + bytes: [ 0x80, 0x19, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s" + + - + input: + bytes: [ 0x21, 0x58, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 1, vgx2], { z1.s, z2.s }, z10.s" + + - + input: + bytes: [ 0x21, 0x58, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 1, vgx2], { z1.s, z2.s }, z10.s" + + - + input: + bytes: [ 0xc5, 0x1a, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s" + + - + input: + bytes: [ 0xc5, 0x1a, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s" + + - + input: + bytes: [ 0x22, 0x79, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 2, vgx2], { z9.s, z10.s }, z1.s" + + - + input: + bytes: [ 0x22, 0x79, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 2, vgx2], { z9.s, z10.s }, z1.s" + + - + input: + bytes: [ 0x87, 0x39, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s" + + - + input: + bytes: [ 0x87, 0x39, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s" + + - + input: + bytes: [ 0x00, 0x00, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s[0]" + + - + input: + bytes: [ 0x00, 0x00, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s[0]" + + - + input: + bytes: [ 0x45, 0x45, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s[1]" + + - + input: + bytes: [ 0x45, 0x45, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s[1]" + + - + input: + bytes: [ 0x87, 0x6d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx2], { z12.s, z13.s }, z8.s[3]" + + - + input: + bytes: [ 0x87, 0x6d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx2], { z12.s, z13.s }, z8.s[3]" + + - + input: + bytes: [ 0xc7, 0x6f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx2], { z30.s, z31.s }, z15.s[3]" + + - + input: + bytes: [ 0xc7, 0x6f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx2], { z30.s, z31.s }, z15.s[3]" + + - + input: + bytes: [ 0x05, 0x0e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx2], { z16.s, z17.s }, z0.s[3]" + + - + input: + bytes: [ 0x05, 0x0e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx2], { z16.s, z17.s }, z0.s[3]" + + - + input: + bytes: [ 0x01, 0x04, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 1, vgx2], { z0.s, z1.s }, z14.s[1]" + + - + input: + bytes: [ 0x01, 0x04, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 1, vgx2], { z0.s, z1.s }, z14.s[1]" + + - + input: + bytes: [ 0x40, 0x46, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 0, vgx2], { z18.s, z19.s }, z4.s[1]" + + - + input: + bytes: [ 0x40, 0x46, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 0, vgx2], { z18.s, z19.s }, z4.s[1]" + + - + input: + bytes: [ 0x80, 0x09, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s[2]" + + - + input: + bytes: [ 0x80, 0x09, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s[2]" + + - + input: + bytes: [ 0x01, 0x48, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 1, vgx2], { z0.s, z1.s }, z10.s[2]" + + - + input: + bytes: [ 0x01, 0x48, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 1, vgx2], { z0.s, z1.s }, z10.s[2]" + + - + input: + bytes: [ 0xc5, 0x0a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s[2]" + + - + input: + bytes: [ 0xc5, 0x0a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s[2]" + + - + input: + bytes: [ 0x02, 0x65, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 2, vgx2], { z8.s, z9.s }, z1.s[1]" + + - + input: + bytes: [ 0x02, 0x65, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 2, vgx2], { z8.s, z9.s }, z1.s[1]" + + - + input: + bytes: [ 0x87, 0x29, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s[2]" + + - + input: + bytes: [ 0x87, 0x29, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s[2]" + + - + input: + bytes: [ 0x00, 0x18, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x00, 0x18, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x45, 0x59, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x45, 0x59, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x87, 0x79, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0x87, 0x79, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0xc7, 0x7b, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0xc7, 0x7b, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x05, 0x1a, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }" + + - + input: + bytes: [ 0x05, 0x1a, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }" + + - + input: + bytes: [ 0x01, 0x18, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x01, 0x18, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x40, 0x5a, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x40, 0x5a, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x80, 0x19, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }" + + - + input: + bytes: [ 0x80, 0x19, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }" + + - + input: + bytes: [ 0x01, 0x58, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }" + + - + input: + bytes: [ 0x01, 0x58, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }" + + - + input: + bytes: [ 0xc5, 0x1a, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0xc5, 0x1a, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x02, 0x79, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x02, 0x79, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x87, 0x39, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }" + + - + input: + bytes: [ 0x87, 0x39, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }" + + - + input: + bytes: [ 0x00, 0x18, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x00, 0x18, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x45, 0x59, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 5, vgx4], { z10.d - z13.d }, z5.d" + + - + input: + bytes: [ 0x45, 0x59, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 5, vgx4], { z10.d - z13.d }, z5.d" + + - + input: + bytes: [ 0xa7, 0x79, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx4], { z13.d - z16.d }, z8.d" + + - + input: + bytes: [ 0xa7, 0x79, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx4], { z13.d - z16.d }, z8.d" + + - + input: + bytes: [ 0xe7, 0x7b, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx4], { z31.d, z0.d, z1.d, z2.d }, z15.d" + + - + input: + bytes: [ 0xe7, 0x7b, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx4], { z31.d, z0.d, z1.d, z2.d }, z15.d" + + - + input: + bytes: [ 0x25, 0x1a, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx4], { z17.d - z20.d }, z0.d" + + - + input: + bytes: [ 0x25, 0x1a, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx4], { z17.d - z20.d }, z0.d" + + - + input: + bytes: [ 0x21, 0x18, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 1, vgx4], { z1.d - z4.d }, z14.d" + + - + input: + bytes: [ 0x21, 0x18, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 1, vgx4], { z1.d - z4.d }, z14.d" + + - + input: + bytes: [ 0x60, 0x5a, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 0, vgx4], { z19.d - z22.d }, z4.d" + + - + input: + bytes: [ 0x60, 0x5a, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 0, vgx4], { z19.d - z22.d }, z4.d" + + - + input: + bytes: [ 0x80, 0x19, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d" + + - + input: + bytes: [ 0x80, 0x19, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d" + + - + input: + bytes: [ 0x21, 0x58, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 1, vgx4], { z1.d - z4.d }, z10.d" + + - + input: + bytes: [ 0x21, 0x58, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 1, vgx4], { z1.d - z4.d }, z10.d" + + - + input: + bytes: [ 0xc5, 0x1a, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx4], { z22.d - z25.d }, z14.d" + + - + input: + bytes: [ 0xc5, 0x1a, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx4], { z22.d - z25.d }, z14.d" + + - + input: + bytes: [ 0x22, 0x79, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 2, vgx4], { z9.d - z12.d }, z1.d" + + - + input: + bytes: [ 0x22, 0x79, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 2, vgx4], { z9.d - z12.d }, z1.d" + + - + input: + bytes: [ 0x87, 0x39, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d" + + - + input: + bytes: [ 0x87, 0x39, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d" + + - + input: + bytes: [ 0x00, 0x80, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0]" + + - + input: + bytes: [ 0x00, 0x80, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0]" + + - + input: + bytes: [ 0x05, 0xc5, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 5, vgx4], { z8.d - z11.d }, z5.d[1]" + + - + input: + bytes: [ 0x05, 0xc5, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 5, vgx4], { z8.d - z11.d }, z5.d[1]" + + - + input: + bytes: [ 0x87, 0xe5, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx4], { z12.d - z15.d }, z8.d[1]" + + - + input: + bytes: [ 0x87, 0xe5, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx4], { z12.d - z15.d }, z8.d[1]" + + - + input: + bytes: [ 0x87, 0xe7, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx4], { z28.d - z31.d }, z15.d[1]" + + - + input: + bytes: [ 0x87, 0xe7, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx4], { z28.d - z31.d }, z15.d[1]" + + - + input: + bytes: [ 0x05, 0x86, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx4], { z16.d - z19.d }, z0.d[1]" + + - + input: + bytes: [ 0x05, 0x86, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx4], { z16.d - z19.d }, z0.d[1]" + + - + input: + bytes: [ 0x01, 0x84, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 1, vgx4], { z0.d - z3.d }, z14.d[1]" + + - + input: + bytes: [ 0x01, 0x84, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 1, vgx4], { z0.d - z3.d }, z14.d[1]" + + - + input: + bytes: [ 0x00, 0xc6, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 0, vgx4], { z16.d - z19.d }, z4.d[1]" + + - + input: + bytes: [ 0x00, 0xc6, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 0, vgx4], { z16.d - z19.d }, z4.d[1]" + + - + input: + bytes: [ 0x80, 0x81, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d[0]" + + - + input: + bytes: [ 0x80, 0x81, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d[0]" + + - + input: + bytes: [ 0x01, 0xc0, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 1, vgx4], { z0.d - z3.d }, z10.d[0]" + + - + input: + bytes: [ 0x01, 0xc0, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 1, vgx4], { z0.d - z3.d }, z10.d[0]" + + - + input: + bytes: [ 0x85, 0x82, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx4], { z20.d - z23.d }, z14.d[0]" + + - + input: + bytes: [ 0x85, 0x82, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx4], { z20.d - z23.d }, z14.d[0]" + + - + input: + bytes: [ 0x02, 0xe5, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 2, vgx4], { z8.d - z11.d }, z1.d[1]" + + - + input: + bytes: [ 0x02, 0xe5, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 2, vgx4], { z8.d - z11.d }, z1.d[1]" + + - + input: + bytes: [ 0x87, 0xa1, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d[0]" + + - + input: + bytes: [ 0x87, 0xa1, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d[0]" + + - + input: + bytes: [ 0x00, 0x18, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x00, 0x18, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x05, 0x59, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x05, 0x59, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x87, 0x79, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x87, 0x79, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x87, 0x7b, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x87, 0x7b, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x05, 0x1a, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }" + + - + input: + bytes: [ 0x05, 0x1a, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }" + + - + input: + bytes: [ 0x01, 0x18, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x01, 0x18, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x00, 0x5a, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x00, 0x5a, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x80, 0x19, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x80, 0x19, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x01, 0x58, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }" + + - + input: + bytes: [ 0x01, 0x58, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }" + + - + input: + bytes: [ 0x85, 0x1a, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x85, 0x1a, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x02, 0x79, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x02, 0x79, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x87, 0x39, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x87, 0x39, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x00, 0x18, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x00, 0x18, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x45, 0x59, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 5, vgx4], { z10.s - z13.s }, z5.s" + + - + input: + bytes: [ 0x45, 0x59, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 5, vgx4], { z10.s - z13.s }, z5.s" + + - + input: + bytes: [ 0xa7, 0x79, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx4], { z13.s - z16.s }, z8.s" + + - + input: + bytes: [ 0xa7, 0x79, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx4], { z13.s - z16.s }, z8.s" + + - + input: + bytes: [ 0xe7, 0x7b, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx4], { z31.s, z0.s, z1.s, z2.s }, z15.s" + + - + input: + bytes: [ 0xe7, 0x7b, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx4], { z31.s, z0.s, z1.s, z2.s }, z15.s" + + - + input: + bytes: [ 0x25, 0x1a, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx4], { z17.s - z20.s }, z0.s" + + - + input: + bytes: [ 0x25, 0x1a, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx4], { z17.s - z20.s }, z0.s" + + - + input: + bytes: [ 0x21, 0x18, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 1, vgx4], { z1.s - z4.s }, z14.s" + + - + input: + bytes: [ 0x21, 0x18, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 1, vgx4], { z1.s - z4.s }, z14.s" + + - + input: + bytes: [ 0x60, 0x5a, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 0, vgx4], { z19.s - z22.s }, z4.s" + + - + input: + bytes: [ 0x60, 0x5a, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 0, vgx4], { z19.s - z22.s }, z4.s" + + - + input: + bytes: [ 0x80, 0x19, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s" + + - + input: + bytes: [ 0x80, 0x19, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s" + + - + input: + bytes: [ 0x21, 0x58, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 1, vgx4], { z1.s - z4.s }, z10.s" + + - + input: + bytes: [ 0x21, 0x58, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 1, vgx4], { z1.s - z4.s }, z10.s" + + - + input: + bytes: [ 0xc5, 0x1a, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx4], { z22.s - z25.s }, z14.s" + + - + input: + bytes: [ 0xc5, 0x1a, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx4], { z22.s - z25.s }, z14.s" + + - + input: + bytes: [ 0x22, 0x79, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 2, vgx4], { z9.s - z12.s }, z1.s" + + - + input: + bytes: [ 0x22, 0x79, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 2, vgx4], { z9.s - z12.s }, z1.s" + + - + input: + bytes: [ 0x87, 0x39, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s" + + - + input: + bytes: [ 0x87, 0x39, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s" + + - + input: + bytes: [ 0x00, 0x80, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0]" + + - + input: + bytes: [ 0x00, 0x80, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0]" + + - + input: + bytes: [ 0x05, 0xc5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 5, vgx4], { z8.s - z11.s }, z5.s[1]" + + - + input: + bytes: [ 0x05, 0xc5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 5, vgx4], { z8.s - z11.s }, z5.s[1]" + + - + input: + bytes: [ 0x87, 0xed, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx4], { z12.s - z15.s }, z8.s[3]" + + - + input: + bytes: [ 0x87, 0xed, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx4], { z12.s - z15.s }, z8.s[3]" + + - + input: + bytes: [ 0x87, 0xef, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx4], { z28.s - z31.s }, z15.s[3]" + + - + input: + bytes: [ 0x87, 0xef, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx4], { z28.s - z31.s }, z15.s[3]" + + - + input: + bytes: [ 0x05, 0x8e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx4], { z16.s - z19.s }, z0.s[3]" + + - + input: + bytes: [ 0x05, 0x8e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx4], { z16.s - z19.s }, z0.s[3]" + + - + input: + bytes: [ 0x01, 0x84, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 1, vgx4], { z0.s - z3.s }, z14.s[1]" + + - + input: + bytes: [ 0x01, 0x84, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 1, vgx4], { z0.s - z3.s }, z14.s[1]" + + - + input: + bytes: [ 0x00, 0xc6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 0, vgx4], { z16.s - z19.s }, z4.s[1]" + + - + input: + bytes: [ 0x00, 0xc6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 0, vgx4], { z16.s - z19.s }, z4.s[1]" + + - + input: + bytes: [ 0x80, 0x89, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s[2]" + + - + input: + bytes: [ 0x80, 0x89, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s[2]" + + - + input: + bytes: [ 0x01, 0xc8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 1, vgx4], { z0.s - z3.s }, z10.s[2]" + + - + input: + bytes: [ 0x01, 0xc8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 1, vgx4], { z0.s - z3.s }, z10.s[2]" + + - + input: + bytes: [ 0x85, 0x8a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx4], { z20.s - z23.s }, z14.s[2]" + + - + input: + bytes: [ 0x85, 0x8a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx4], { z20.s - z23.s }, z14.s[2]" + + - + input: + bytes: [ 0x02, 0xe5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 2, vgx4], { z8.s - z11.s }, z1.s[1]" + + - + input: + bytes: [ 0x02, 0xe5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 2, vgx4], { z8.s - z11.s }, z1.s[1]" + + - + input: + bytes: [ 0x87, 0xa9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s[2]" + + - + input: + bytes: [ 0x87, 0xa9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s[2]" + + - + input: + bytes: [ 0x00, 0x18, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x00, 0x18, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x05, 0x59, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x05, 0x59, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x87, 0x79, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x87, 0x79, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x87, 0x7b, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x87, 0x7b, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x05, 0x1a, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }" + + - + input: + bytes: [ 0x05, 0x1a, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }" + + - + input: + bytes: [ 0x01, 0x18, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x01, 0x18, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x00, 0x5a, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x00, 0x5a, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x80, 0x19, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x80, 0x19, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x01, 0x58, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }" + + - + input: + bytes: [ 0x01, 0x58, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }" + + - + input: + bytes: [ 0x85, 0x1a, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x85, 0x1a, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x02, 0x79, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x02, 0x79, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x87, 0x39, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x87, 0x39, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmla za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }" diff --git a/tests/MC/AArch64/SME2/fmlal.s.yaml b/tests/MC/AArch64/SME2/fmlal.s.yaml new file mode 100644 index 0000000000..0919a252f3 --- /dev/null +++ b/tests/MC/AArch64/SME2/fmlal.s.yaml @@ -0,0 +1,1680 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x0c, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1], z0.h, z0.h" + + - + input: + bytes: [ 0x45, 0x4d, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 10:11], z10.h, z5.h" + + - + input: + bytes: [ 0xa7, 0x6d, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 14:15], z13.h, z8.h" + + - + input: + bytes: [ 0xe7, 0x6f, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 14:15], z31.h, z15.h" + + - + input: + bytes: [ 0x25, 0x0e, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 10:11], z17.h, z0.h" + + - + input: + bytes: [ 0x21, 0x0c, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3], z1.h, z14.h" + + - + input: + bytes: [ 0x60, 0x4e, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 0:1], z19.h, z4.h" + + - + input: + bytes: [ 0x80, 0x0d, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1], z12.h, z2.h" + + - + input: + bytes: [ 0x21, 0x4c, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3], z1.h, z10.h" + + - + input: + bytes: [ 0xc5, 0x0e, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 10:11], z22.h, z14.h" + + - + input: + bytes: [ 0x22, 0x6d, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 4:5], z9.h, z1.h" + + - + input: + bytes: [ 0x87, 0x2d, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w9, 14:15], z12.h, z11.h" + + - + input: + bytes: [ 0x00, 0x10, 0x80, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1], z0.h, z0.h[0]" + + - + input: + bytes: [ 0x45, 0x55, 0x85, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 10:11], z10.h, z5.h[1]" + + - + input: + bytes: [ 0xa7, 0xfd, 0x88, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 14:15], z13.h, z8.h[7]" + + - + input: + bytes: [ 0xe7, 0xff, 0x8f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 14:15], z31.h, z15.h[7]" + + - + input: + bytes: [ 0x25, 0x1e, 0x80, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 10:11], z17.h, z0.h[3]" + + - + input: + bytes: [ 0x21, 0x94, 0x8e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3], z1.h, z14.h[5]" + + - + input: + bytes: [ 0x60, 0x56, 0x84, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 0:1], z19.h, z4.h[1]" + + - + input: + bytes: [ 0x80, 0x19, 0x82, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1], z12.h, z2.h[2]" + + - + input: + bytes: [ 0x21, 0xd8, 0x8a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3], z1.h, z10.h[6]" + + - + input: + bytes: [ 0xc5, 0x1a, 0x8e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 10:11], z22.h, z14.h[2]" + + - + input: + bytes: [ 0x22, 0xf5, 0x81, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 4:5], z9.h, z1.h[5]" + + - + input: + bytes: [ 0x87, 0xb9, 0x8b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w9, 14:15], z12.h, z11.h[6]" + + - + input: + bytes: [ 0x00, 0x08, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x00, 0x08, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x41, 0x49, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x41, 0x49, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xa3, 0x69, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xa3, 0x69, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xe3, 0x6b, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xe3, 0x6b, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x21, 0x0a, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x0a, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x08, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x21, 0x08, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x60, 0x4a, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x60, 0x4a, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x80, 0x09, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x80, 0x09, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x21, 0x48, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x21, 0x48, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xc1, 0x0a, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xc1, 0x0a, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x22, 0x69, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x22, 0x69, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x83, 0x29, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x83, 0x29, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x00, 0x10, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x00, 0x10, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x45, 0x55, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x45, 0x55, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x87, 0x7d, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0x87, 0x7d, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0xc7, 0x7f, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0xc7, 0x7f, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x05, 0x1e, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]" + + - + input: + bytes: [ 0x05, 0x1e, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]" + + - + input: + bytes: [ 0x01, 0x14, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x01, 0x14, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x40, 0x56, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x40, 0x56, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x80, 0x19, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x80, 0x19, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x01, 0x58, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0x01, 0x58, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0xc5, 0x1a, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0xc5, 0x1a, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x02, 0x75, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x02, 0x75, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x87, 0x39, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]" + + - + input: + bytes: [ 0x87, 0x39, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]" + + - + input: + bytes: [ 0x00, 0x08, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x00, 0x08, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x41, 0x49, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x41, 0x49, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x83, 0x69, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x83, 0x69, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xc3, 0x6b, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xc3, 0x6b, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x01, 0x0a, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x01, 0x0a, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x01, 0x08, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x01, 0x08, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x40, 0x4a, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x40, 0x4a, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x80, 0x09, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x80, 0x09, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x01, 0x48, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x01, 0x48, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xc1, 0x0a, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xc1, 0x0a, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x02, 0x69, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x02, 0x69, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x83, 0x29, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x83, 0x29, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x00, 0x08, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x00, 0x08, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x41, 0x49, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x41, 0x49, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xa3, 0x69, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xa3, 0x69, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xe3, 0x6b, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xe3, 0x6b, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x21, 0x0a, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x0a, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x08, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x21, 0x08, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x60, 0x4a, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x60, 0x4a, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x80, 0x09, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x80, 0x09, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x21, 0x48, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x21, 0x48, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xc1, 0x0a, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xc1, 0x0a, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x22, 0x69, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x22, 0x69, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x83, 0x29, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x83, 0x29, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x00, 0x90, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x00, 0x90, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x05, 0xd5, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x05, 0xd5, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x87, 0xfd, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x87, 0xfd, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x87, 0xff, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x87, 0xff, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x05, 0x9e, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]" + + - + input: + bytes: [ 0x05, 0x9e, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]" + + - + input: + bytes: [ 0x01, 0x94, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x01, 0x94, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x00, 0xd6, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x00, 0xd6, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x80, 0x99, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x80, 0x99, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x01, 0xd8, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x01, 0xd8, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x85, 0x9a, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x85, 0x9a, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x02, 0xf5, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x02, 0xf5, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x87, 0xb9, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]" + + - + input: + bytes: [ 0x87, 0xb9, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]" + + - + input: + bytes: [ 0x00, 0x08, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x00, 0x08, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x01, 0x49, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x01, 0x49, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x83, 0x69, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x83, 0x69, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x83, 0x6b, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x83, 0x6b, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x01, 0x0a, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x01, 0x0a, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x01, 0x08, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x01, 0x08, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x00, 0x4a, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x00, 0x4a, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x80, 0x09, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x80, 0x09, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x01, 0x48, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x01, 0x48, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x81, 0x0a, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x81, 0x0a, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x02, 0x69, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x02, 0x69, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x83, 0x29, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x83, 0x29, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2/fmls.s.yaml b/tests/MC/AArch64/SME2/fmls.s.yaml new file mode 100644 index 0000000000..05764aed6d --- /dev/null +++ b/tests/MC/AArch64/SME2/fmls.s.yaml @@ -0,0 +1,2880 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x18, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x08, 0x18, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x4d, 0x59, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d" + + - + input: + bytes: [ 0x4d, 0x59, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d" + + - + input: + bytes: [ 0xaf, 0x79, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx2], { z13.d, z14.d }, z8.d" + + - + input: + bytes: [ 0xaf, 0x79, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx2], { z13.d, z14.d }, z8.d" + + - + input: + bytes: [ 0xef, 0x7b, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx2], { z31.d, z0.d }, z15.d" + + - + input: + bytes: [ 0xef, 0x7b, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx2], { z31.d, z0.d }, z15.d" + + - + input: + bytes: [ 0x2d, 0x1a, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx2], { z17.d, z18.d }, z0.d" + + - + input: + bytes: [ 0x2d, 0x1a, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx2], { z17.d, z18.d }, z0.d" + + - + input: + bytes: [ 0x29, 0x18, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 1, vgx2], { z1.d, z2.d }, z14.d" + + - + input: + bytes: [ 0x29, 0x18, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 1, vgx2], { z1.d, z2.d }, z14.d" + + - + input: + bytes: [ 0x68, 0x5a, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 0, vgx2], { z19.d, z20.d }, z4.d" + + - + input: + bytes: [ 0x68, 0x5a, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 0, vgx2], { z19.d, z20.d }, z4.d" + + - + input: + bytes: [ 0x88, 0x19, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d" + + - + input: + bytes: [ 0x88, 0x19, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d" + + - + input: + bytes: [ 0x29, 0x58, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 1, vgx2], { z1.d, z2.d }, z10.d" + + - + input: + bytes: [ 0x29, 0x58, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 1, vgx2], { z1.d, z2.d }, z10.d" + + - + input: + bytes: [ 0xcd, 0x1a, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d" + + - + input: + bytes: [ 0xcd, 0x1a, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d" + + - + input: + bytes: [ 0x2a, 0x79, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 2, vgx2], { z9.d, z10.d }, z1.d" + + - + input: + bytes: [ 0x2a, 0x79, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 2, vgx2], { z9.d, z10.d }, z1.d" + + - + input: + bytes: [ 0x8f, 0x39, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d" + + - + input: + bytes: [ 0x8f, 0x39, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d" + + - + input: + bytes: [ 0x10, 0x00, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d[0]" + + - + input: + bytes: [ 0x10, 0x00, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d[0]" + + - + input: + bytes: [ 0x55, 0x45, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d[1]" + + - + input: + bytes: [ 0x55, 0x45, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d[1]" + + - + input: + bytes: [ 0x97, 0x65, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx2], { z12.d, z13.d }, z8.d[1]" + + - + input: + bytes: [ 0x97, 0x65, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx2], { z12.d, z13.d }, z8.d[1]" + + - + input: + bytes: [ 0xd7, 0x67, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx2], { z30.d, z31.d }, z15.d[1]" + + - + input: + bytes: [ 0xd7, 0x67, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx2], { z30.d, z31.d }, z15.d[1]" + + - + input: + bytes: [ 0x15, 0x06, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx2], { z16.d, z17.d }, z0.d[1]" + + - + input: + bytes: [ 0x15, 0x06, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx2], { z16.d, z17.d }, z0.d[1]" + + - + input: + bytes: [ 0x11, 0x04, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 1, vgx2], { z0.d, z1.d }, z14.d[1]" + + - + input: + bytes: [ 0x11, 0x04, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 1, vgx2], { z0.d, z1.d }, z14.d[1]" + + - + input: + bytes: [ 0x50, 0x46, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 0, vgx2], { z18.d, z19.d }, z4.d[1]" + + - + input: + bytes: [ 0x50, 0x46, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 0, vgx2], { z18.d, z19.d }, z4.d[1]" + + - + input: + bytes: [ 0x90, 0x01, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d[0]" + + - + input: + bytes: [ 0x90, 0x01, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d[0]" + + - + input: + bytes: [ 0x11, 0x40, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 1, vgx2], { z0.d, z1.d }, z10.d[0]" + + - + input: + bytes: [ 0x11, 0x40, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 1, vgx2], { z0.d, z1.d }, z10.d[0]" + + - + input: + bytes: [ 0xd5, 0x02, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d[0]" + + - + input: + bytes: [ 0xd5, 0x02, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d[0]" + + - + input: + bytes: [ 0x12, 0x65, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 2, vgx2], { z8.d, z9.d }, z1.d[1]" + + - + input: + bytes: [ 0x12, 0x65, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 2, vgx2], { z8.d, z9.d }, z1.d[1]" + + - + input: + bytes: [ 0x97, 0x21, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d[0]" + + - + input: + bytes: [ 0x97, 0x21, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d[0]" + + - + input: + bytes: [ 0x08, 0x18, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x08, 0x18, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x4d, 0x59, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x4d, 0x59, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x8f, 0x79, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0x8f, 0x79, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0xcf, 0x7b, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0xcf, 0x7b, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x0d, 0x1a, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }" + + - + input: + bytes: [ 0x0d, 0x1a, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }" + + - + input: + bytes: [ 0x09, 0x18, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x09, 0x18, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x48, 0x5a, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x48, 0x5a, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x88, 0x19, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }" + + - + input: + bytes: [ 0x88, 0x19, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }" + + - + input: + bytes: [ 0x09, 0x58, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }" + + - + input: + bytes: [ 0x09, 0x58, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }" + + - + input: + bytes: [ 0xcd, 0x1a, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0xcd, 0x1a, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x0a, 0x79, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x0a, 0x79, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x8f, 0x39, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }" + + - + input: + bytes: [ 0x8f, 0x39, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }" + + - + input: + bytes: [ 0x08, 0x18, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x08, 0x18, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x4d, 0x59, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s" + + - + input: + bytes: [ 0x4d, 0x59, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s" + + - + input: + bytes: [ 0xaf, 0x79, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx2], { z13.s, z14.s }, z8.s" + + - + input: + bytes: [ 0xaf, 0x79, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx2], { z13.s, z14.s }, z8.s" + + - + input: + bytes: [ 0xef, 0x7b, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx2], { z31.s, z0.s }, z15.s" + + - + input: + bytes: [ 0xef, 0x7b, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx2], { z31.s, z0.s }, z15.s" + + - + input: + bytes: [ 0x2d, 0x1a, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx2], { z17.s, z18.s }, z0.s" + + - + input: + bytes: [ 0x2d, 0x1a, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx2], { z17.s, z18.s }, z0.s" + + - + input: + bytes: [ 0x29, 0x18, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 1, vgx2], { z1.s, z2.s }, z14.s" + + - + input: + bytes: [ 0x29, 0x18, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 1, vgx2], { z1.s, z2.s }, z14.s" + + - + input: + bytes: [ 0x68, 0x5a, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 0, vgx2], { z19.s, z20.s }, z4.s" + + - + input: + bytes: [ 0x68, 0x5a, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 0, vgx2], { z19.s, z20.s }, z4.s" + + - + input: + bytes: [ 0x88, 0x19, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s" + + - + input: + bytes: [ 0x88, 0x19, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s" + + - + input: + bytes: [ 0x29, 0x58, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 1, vgx2], { z1.s, z2.s }, z10.s" + + - + input: + bytes: [ 0x29, 0x58, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 1, vgx2], { z1.s, z2.s }, z10.s" + + - + input: + bytes: [ 0xcd, 0x1a, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s" + + - + input: + bytes: [ 0xcd, 0x1a, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s" + + - + input: + bytes: [ 0x2a, 0x79, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 2, vgx2], { z9.s, z10.s }, z1.s" + + - + input: + bytes: [ 0x2a, 0x79, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 2, vgx2], { z9.s, z10.s }, z1.s" + + - + input: + bytes: [ 0x8f, 0x39, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s" + + - + input: + bytes: [ 0x8f, 0x39, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s" + + - + input: + bytes: [ 0x10, 0x00, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s[0]" + + - + input: + bytes: [ 0x10, 0x00, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s[0]" + + - + input: + bytes: [ 0x55, 0x45, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s[1]" + + - + input: + bytes: [ 0x55, 0x45, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s[1]" + + - + input: + bytes: [ 0x97, 0x6d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx2], { z12.s, z13.s }, z8.s[3]" + + - + input: + bytes: [ 0x97, 0x6d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx2], { z12.s, z13.s }, z8.s[3]" + + - + input: + bytes: [ 0xd7, 0x6f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx2], { z30.s, z31.s }, z15.s[3]" + + - + input: + bytes: [ 0xd7, 0x6f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx2], { z30.s, z31.s }, z15.s[3]" + + - + input: + bytes: [ 0x15, 0x0e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx2], { z16.s, z17.s }, z0.s[3]" + + - + input: + bytes: [ 0x15, 0x0e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx2], { z16.s, z17.s }, z0.s[3]" + + - + input: + bytes: [ 0x11, 0x04, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 1, vgx2], { z0.s, z1.s }, z14.s[1]" + + - + input: + bytes: [ 0x11, 0x04, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 1, vgx2], { z0.s, z1.s }, z14.s[1]" + + - + input: + bytes: [ 0x50, 0x46, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 0, vgx2], { z18.s, z19.s }, z4.s[1]" + + - + input: + bytes: [ 0x50, 0x46, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 0, vgx2], { z18.s, z19.s }, z4.s[1]" + + - + input: + bytes: [ 0x90, 0x09, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s[2]" + + - + input: + bytes: [ 0x90, 0x09, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s[2]" + + - + input: + bytes: [ 0x11, 0x48, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 1, vgx2], { z0.s, z1.s }, z10.s[2]" + + - + input: + bytes: [ 0x11, 0x48, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 1, vgx2], { z0.s, z1.s }, z10.s[2]" + + - + input: + bytes: [ 0xd5, 0x0a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s[2]" + + - + input: + bytes: [ 0xd5, 0x0a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s[2]" + + - + input: + bytes: [ 0x12, 0x65, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 2, vgx2], { z8.s, z9.s }, z1.s[1]" + + - + input: + bytes: [ 0x12, 0x65, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 2, vgx2], { z8.s, z9.s }, z1.s[1]" + + - + input: + bytes: [ 0x97, 0x29, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s[2]" + + - + input: + bytes: [ 0x97, 0x29, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s[2]" + + - + input: + bytes: [ 0x08, 0x18, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x08, 0x18, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x4d, 0x59, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x4d, 0x59, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x8f, 0x79, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0x8f, 0x79, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0xcf, 0x7b, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0xcf, 0x7b, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x0d, 0x1a, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }" + + - + input: + bytes: [ 0x0d, 0x1a, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }" + + - + input: + bytes: [ 0x09, 0x18, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x09, 0x18, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x48, 0x5a, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x48, 0x5a, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x88, 0x19, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }" + + - + input: + bytes: [ 0x88, 0x19, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }" + + - + input: + bytes: [ 0x09, 0x58, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }" + + - + input: + bytes: [ 0x09, 0x58, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }" + + - + input: + bytes: [ 0xcd, 0x1a, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0xcd, 0x1a, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x0a, 0x79, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x0a, 0x79, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x8f, 0x39, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }" + + - + input: + bytes: [ 0x8f, 0x39, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }" + + - + input: + bytes: [ 0x08, 0x18, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x08, 0x18, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x4d, 0x59, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 5, vgx4], { z10.d - z13.d }, z5.d" + + - + input: + bytes: [ 0x4d, 0x59, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 5, vgx4], { z10.d - z13.d }, z5.d" + + - + input: + bytes: [ 0xaf, 0x79, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx4], { z13.d - z16.d }, z8.d" + + - + input: + bytes: [ 0xaf, 0x79, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx4], { z13.d - z16.d }, z8.d" + + - + input: + bytes: [ 0xef, 0x7b, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx4], { z31.d, z0.d, z1.d, z2.d }, z15.d" + + - + input: + bytes: [ 0xef, 0x7b, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx4], { z31.d, z0.d, z1.d, z2.d }, z15.d" + + - + input: + bytes: [ 0x2d, 0x1a, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx4], { z17.d - z20.d }, z0.d" + + - + input: + bytes: [ 0x2d, 0x1a, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx4], { z17.d - z20.d }, z0.d" + + - + input: + bytes: [ 0x29, 0x18, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 1, vgx4], { z1.d - z4.d }, z14.d" + + - + input: + bytes: [ 0x29, 0x18, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 1, vgx4], { z1.d - z4.d }, z14.d" + + - + input: + bytes: [ 0x68, 0x5a, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 0, vgx4], { z19.d - z22.d }, z4.d" + + - + input: + bytes: [ 0x68, 0x5a, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 0, vgx4], { z19.d - z22.d }, z4.d" + + - + input: + bytes: [ 0x88, 0x19, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d" + + - + input: + bytes: [ 0x88, 0x19, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d" + + - + input: + bytes: [ 0x29, 0x58, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 1, vgx4], { z1.d - z4.d }, z10.d" + + - + input: + bytes: [ 0x29, 0x58, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 1, vgx4], { z1.d - z4.d }, z10.d" + + - + input: + bytes: [ 0xcd, 0x1a, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx4], { z22.d - z25.d }, z14.d" + + - + input: + bytes: [ 0xcd, 0x1a, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx4], { z22.d - z25.d }, z14.d" + + - + input: + bytes: [ 0x2a, 0x79, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 2, vgx4], { z9.d - z12.d }, z1.d" + + - + input: + bytes: [ 0x2a, 0x79, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 2, vgx4], { z9.d - z12.d }, z1.d" + + - + input: + bytes: [ 0x8f, 0x39, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d" + + - + input: + bytes: [ 0x8f, 0x39, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d" + + - + input: + bytes: [ 0x10, 0x80, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0]" + + - + input: + bytes: [ 0x10, 0x80, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0]" + + - + input: + bytes: [ 0x15, 0xc5, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 5, vgx4], { z8.d - z11.d }, z5.d[1]" + + - + input: + bytes: [ 0x15, 0xc5, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 5, vgx4], { z8.d - z11.d }, z5.d[1]" + + - + input: + bytes: [ 0x97, 0xe5, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx4], { z12.d - z15.d }, z8.d[1]" + + - + input: + bytes: [ 0x97, 0xe5, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx4], { z12.d - z15.d }, z8.d[1]" + + - + input: + bytes: [ 0x97, 0xe7, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx4], { z28.d - z31.d }, z15.d[1]" + + - + input: + bytes: [ 0x97, 0xe7, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx4], { z28.d - z31.d }, z15.d[1]" + + - + input: + bytes: [ 0x15, 0x86, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx4], { z16.d - z19.d }, z0.d[1]" + + - + input: + bytes: [ 0x15, 0x86, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx4], { z16.d - z19.d }, z0.d[1]" + + - + input: + bytes: [ 0x11, 0x84, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 1, vgx4], { z0.d - z3.d }, z14.d[1]" + + - + input: + bytes: [ 0x11, 0x84, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 1, vgx4], { z0.d - z3.d }, z14.d[1]" + + - + input: + bytes: [ 0x10, 0xc6, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 0, vgx4], { z16.d - z19.d }, z4.d[1]" + + - + input: + bytes: [ 0x10, 0xc6, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 0, vgx4], { z16.d - z19.d }, z4.d[1]" + + - + input: + bytes: [ 0x90, 0x81, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d[0]" + + - + input: + bytes: [ 0x90, 0x81, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d[0]" + + - + input: + bytes: [ 0x11, 0xc0, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 1, vgx4], { z0.d - z3.d }, z10.d[0]" + + - + input: + bytes: [ 0x11, 0xc0, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 1, vgx4], { z0.d - z3.d }, z10.d[0]" + + - + input: + bytes: [ 0x95, 0x82, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx4], { z20.d - z23.d }, z14.d[0]" + + - + input: + bytes: [ 0x95, 0x82, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx4], { z20.d - z23.d }, z14.d[0]" + + - + input: + bytes: [ 0x12, 0xe5, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 2, vgx4], { z8.d - z11.d }, z1.d[1]" + + - + input: + bytes: [ 0x12, 0xe5, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 2, vgx4], { z8.d - z11.d }, z1.d[1]" + + - + input: + bytes: [ 0x97, 0xa1, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d[0]" + + - + input: + bytes: [ 0x97, 0xa1, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d[0]" + + - + input: + bytes: [ 0x08, 0x18, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x08, 0x18, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x0d, 0x59, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x0d, 0x59, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x8f, 0x79, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x8f, 0x79, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x8f, 0x7b, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x8f, 0x7b, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x0d, 0x1a, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }" + + - + input: + bytes: [ 0x0d, 0x1a, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }" + + - + input: + bytes: [ 0x09, 0x18, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x09, 0x18, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x08, 0x5a, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x08, 0x5a, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x88, 0x19, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x88, 0x19, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x09, 0x58, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }" + + - + input: + bytes: [ 0x09, 0x58, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }" + + - + input: + bytes: [ 0x8d, 0x1a, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x8d, 0x1a, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x0a, 0x79, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x0a, 0x79, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x8f, 0x39, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x8f, 0x39, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x08, 0x18, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x08, 0x18, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x4d, 0x59, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 5, vgx4], { z10.s - z13.s }, z5.s" + + - + input: + bytes: [ 0x4d, 0x59, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 5, vgx4], { z10.s - z13.s }, z5.s" + + - + input: + bytes: [ 0xaf, 0x79, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx4], { z13.s - z16.s }, z8.s" + + - + input: + bytes: [ 0xaf, 0x79, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx4], { z13.s - z16.s }, z8.s" + + - + input: + bytes: [ 0xef, 0x7b, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx4], { z31.s, z0.s, z1.s, z2.s }, z15.s" + + - + input: + bytes: [ 0xef, 0x7b, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx4], { z31.s, z0.s, z1.s, z2.s }, z15.s" + + - + input: + bytes: [ 0x2d, 0x1a, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx4], { z17.s - z20.s }, z0.s" + + - + input: + bytes: [ 0x2d, 0x1a, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx4], { z17.s - z20.s }, z0.s" + + - + input: + bytes: [ 0x29, 0x18, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 1, vgx4], { z1.s - z4.s }, z14.s" + + - + input: + bytes: [ 0x29, 0x18, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 1, vgx4], { z1.s - z4.s }, z14.s" + + - + input: + bytes: [ 0x68, 0x5a, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 0, vgx4], { z19.s - z22.s }, z4.s" + + - + input: + bytes: [ 0x68, 0x5a, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 0, vgx4], { z19.s - z22.s }, z4.s" + + - + input: + bytes: [ 0x88, 0x19, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s" + + - + input: + bytes: [ 0x88, 0x19, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s" + + - + input: + bytes: [ 0x29, 0x58, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 1, vgx4], { z1.s - z4.s }, z10.s" + + - + input: + bytes: [ 0x29, 0x58, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 1, vgx4], { z1.s - z4.s }, z10.s" + + - + input: + bytes: [ 0xcd, 0x1a, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx4], { z22.s - z25.s }, z14.s" + + - + input: + bytes: [ 0xcd, 0x1a, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx4], { z22.s - z25.s }, z14.s" + + - + input: + bytes: [ 0x2a, 0x79, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 2, vgx4], { z9.s - z12.s }, z1.s" + + - + input: + bytes: [ 0x2a, 0x79, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 2, vgx4], { z9.s - z12.s }, z1.s" + + - + input: + bytes: [ 0x8f, 0x39, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s" + + - + input: + bytes: [ 0x8f, 0x39, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s" + + - + input: + bytes: [ 0x10, 0x80, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0]" + + - + input: + bytes: [ 0x10, 0x80, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0]" + + - + input: + bytes: [ 0x15, 0xc5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 5, vgx4], { z8.s - z11.s }, z5.s[1]" + + - + input: + bytes: [ 0x15, 0xc5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 5, vgx4], { z8.s - z11.s }, z5.s[1]" + + - + input: + bytes: [ 0x97, 0xed, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx4], { z12.s - z15.s }, z8.s[3]" + + - + input: + bytes: [ 0x97, 0xed, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx4], { z12.s - z15.s }, z8.s[3]" + + - + input: + bytes: [ 0x97, 0xef, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx4], { z28.s - z31.s }, z15.s[3]" + + - + input: + bytes: [ 0x97, 0xef, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx4], { z28.s - z31.s }, z15.s[3]" + + - + input: + bytes: [ 0x15, 0x8e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx4], { z16.s - z19.s }, z0.s[3]" + + - + input: + bytes: [ 0x15, 0x8e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx4], { z16.s - z19.s }, z0.s[3]" + + - + input: + bytes: [ 0x11, 0x84, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 1, vgx4], { z0.s - z3.s }, z14.s[1]" + + - + input: + bytes: [ 0x11, 0x84, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 1, vgx4], { z0.s - z3.s }, z14.s[1]" + + - + input: + bytes: [ 0x10, 0xc6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 0, vgx4], { z16.s - z19.s }, z4.s[1]" + + - + input: + bytes: [ 0x10, 0xc6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 0, vgx4], { z16.s - z19.s }, z4.s[1]" + + - + input: + bytes: [ 0x90, 0x89, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s[2]" + + - + input: + bytes: [ 0x90, 0x89, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s[2]" + + - + input: + bytes: [ 0x11, 0xc8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 1, vgx4], { z0.s - z3.s }, z10.s[2]" + + - + input: + bytes: [ 0x11, 0xc8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 1, vgx4], { z0.s - z3.s }, z10.s[2]" + + - + input: + bytes: [ 0x95, 0x8a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx4], { z20.s - z23.s }, z14.s[2]" + + - + input: + bytes: [ 0x95, 0x8a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx4], { z20.s - z23.s }, z14.s[2]" + + - + input: + bytes: [ 0x12, 0xe5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 2, vgx4], { z8.s - z11.s }, z1.s[1]" + + - + input: + bytes: [ 0x12, 0xe5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 2, vgx4], { z8.s - z11.s }, z1.s[1]" + + - + input: + bytes: [ 0x97, 0xa9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s[2]" + + - + input: + bytes: [ 0x97, 0xa9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s[2]" + + - + input: + bytes: [ 0x08, 0x18, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x08, 0x18, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x0d, 0x59, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x0d, 0x59, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x8f, 0x79, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x8f, 0x79, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x8f, 0x7b, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x8f, 0x7b, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x0d, 0x1a, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }" + + - + input: + bytes: [ 0x0d, 0x1a, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }" + + - + input: + bytes: [ 0x09, 0x18, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x09, 0x18, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x08, 0x5a, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x08, 0x5a, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x88, 0x19, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x88, 0x19, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x09, 0x58, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }" + + - + input: + bytes: [ 0x09, 0x58, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }" + + - + input: + bytes: [ 0x8d, 0x1a, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x8d, 0x1a, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x0a, 0x79, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x0a, 0x79, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x8f, 0x39, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x8f, 0x39, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fmls za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }" diff --git a/tests/MC/AArch64/SME2/fmlsl.s.yaml b/tests/MC/AArch64/SME2/fmlsl.s.yaml new file mode 100644 index 0000000000..7281de6755 --- /dev/null +++ b/tests/MC/AArch64/SME2/fmlsl.s.yaml @@ -0,0 +1,1680 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x0c, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1], z0.h, z0.h" + + - + input: + bytes: [ 0x4d, 0x4d, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 10:11], z10.h, z5.h" + + - + input: + bytes: [ 0xaf, 0x6d, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 14:15], z13.h, z8.h" + + - + input: + bytes: [ 0xef, 0x6f, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 14:15], z31.h, z15.h" + + - + input: + bytes: [ 0x2d, 0x0e, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 10:11], z17.h, z0.h" + + - + input: + bytes: [ 0x29, 0x0c, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3], z1.h, z14.h" + + - + input: + bytes: [ 0x68, 0x4e, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 0:1], z19.h, z4.h" + + - + input: + bytes: [ 0x88, 0x0d, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1], z12.h, z2.h" + + - + input: + bytes: [ 0x29, 0x4c, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3], z1.h, z10.h" + + - + input: + bytes: [ 0xcd, 0x0e, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 10:11], z22.h, z14.h" + + - + input: + bytes: [ 0x2a, 0x6d, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 4:5], z9.h, z1.h" + + - + input: + bytes: [ 0x8f, 0x2d, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w9, 14:15], z12.h, z11.h" + + - + input: + bytes: [ 0x08, 0x10, 0x80, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1], z0.h, z0.h[0]" + + - + input: + bytes: [ 0x4d, 0x55, 0x85, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 10:11], z10.h, z5.h[1]" + + - + input: + bytes: [ 0xaf, 0xfd, 0x88, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 14:15], z13.h, z8.h[7]" + + - + input: + bytes: [ 0xef, 0xff, 0x8f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 14:15], z31.h, z15.h[7]" + + - + input: + bytes: [ 0x2d, 0x1e, 0x80, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 10:11], z17.h, z0.h[3]" + + - + input: + bytes: [ 0x29, 0x94, 0x8e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3], z1.h, z14.h[5]" + + - + input: + bytes: [ 0x68, 0x56, 0x84, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 0:1], z19.h, z4.h[1]" + + - + input: + bytes: [ 0x88, 0x19, 0x82, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1], z12.h, z2.h[2]" + + - + input: + bytes: [ 0x29, 0xd8, 0x8a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3], z1.h, z10.h[6]" + + - + input: + bytes: [ 0xcd, 0x1a, 0x8e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 10:11], z22.h, z14.h[2]" + + - + input: + bytes: [ 0x2a, 0xf5, 0x81, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 4:5], z9.h, z1.h[5]" + + - + input: + bytes: [ 0x8f, 0xb9, 0x8b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w9, 14:15], z12.h, z11.h[6]" + + - + input: + bytes: [ 0x08, 0x08, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x08, 0x08, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x49, 0x49, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x49, 0x49, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xab, 0x69, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xab, 0x69, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xeb, 0x6b, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xeb, 0x6b, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x29, 0x0a, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x29, 0x0a, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x29, 0x08, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x29, 0x08, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x68, 0x4a, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x68, 0x4a, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x88, 0x09, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x88, 0x09, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x29, 0x48, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x29, 0x48, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xc9, 0x0a, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xc9, 0x0a, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x2a, 0x69, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x2a, 0x69, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x8b, 0x29, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x8b, 0x29, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x08, 0x10, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x08, 0x10, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x4d, 0x55, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x4d, 0x55, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x8f, 0x7d, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0x8f, 0x7d, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0xcf, 0x7f, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0xcf, 0x7f, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x0d, 0x1e, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]" + + - + input: + bytes: [ 0x0d, 0x1e, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]" + + - + input: + bytes: [ 0x09, 0x14, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x09, 0x14, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x48, 0x56, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x48, 0x56, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x88, 0x19, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x88, 0x19, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x09, 0x58, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0x09, 0x58, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0xcd, 0x1a, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0xcd, 0x1a, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x0a, 0x75, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x0a, 0x75, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x8f, 0x39, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]" + + - + input: + bytes: [ 0x8f, 0x39, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]" + + - + input: + bytes: [ 0x08, 0x08, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x08, 0x08, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x49, 0x49, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x49, 0x49, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x8b, 0x69, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x8b, 0x69, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xcb, 0x6b, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xcb, 0x6b, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x09, 0x0a, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x09, 0x0a, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x09, 0x08, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x09, 0x08, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x48, 0x4a, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x48, 0x4a, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x88, 0x09, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x88, 0x09, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x09, 0x48, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x09, 0x48, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xc9, 0x0a, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xc9, 0x0a, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x0a, 0x69, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x0a, 0x69, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x8b, 0x29, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x8b, 0x29, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x08, 0x08, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x08, 0x08, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x49, 0x49, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x49, 0x49, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xab, 0x69, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xab, 0x69, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xeb, 0x6b, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xeb, 0x6b, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x29, 0x0a, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x29, 0x0a, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x29, 0x08, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x29, 0x08, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x68, 0x4a, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x68, 0x4a, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x88, 0x09, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x88, 0x09, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x29, 0x48, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x29, 0x48, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xc9, 0x0a, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xc9, 0x0a, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x2a, 0x69, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x2a, 0x69, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x8b, 0x29, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x8b, 0x29, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x08, 0x90, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x08, 0x90, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x0d, 0xd5, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x0d, 0xd5, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x8f, 0xfd, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x8f, 0xfd, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x8f, 0xff, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x8f, 0xff, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x0d, 0x9e, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]" + + - + input: + bytes: [ 0x0d, 0x9e, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]" + + - + input: + bytes: [ 0x09, 0x94, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x09, 0x94, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x08, 0xd6, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x08, 0xd6, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x88, 0x99, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x88, 0x99, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x09, 0xd8, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x09, 0xd8, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x8d, 0x9a, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x8d, 0x9a, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x0a, 0xf5, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x0a, 0xf5, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x8f, 0xb9, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]" + + - + input: + bytes: [ 0x8f, 0xb9, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]" + + - + input: + bytes: [ 0x08, 0x08, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x08, 0x08, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x09, 0x49, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x09, 0x49, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x8b, 0x69, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x8b, 0x69, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x8b, 0x6b, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x8b, 0x6b, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x09, 0x0a, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x09, 0x0a, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x09, 0x08, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x09, 0x08, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x08, 0x4a, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x08, 0x4a, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x88, 0x09, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x88, 0x09, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x09, 0x48, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x09, 0x48, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x89, 0x0a, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x89, 0x0a, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x0a, 0x69, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x0a, 0x69, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x8b, 0x29, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x8b, 0x29, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2/frinta.s.yaml b/tests/MC/AArch64/SME2/frinta.s.yaml new file mode 100644 index 0000000000..828b21eb8c --- /dev/null +++ b/tests/MC/AArch64/SME2/frinta.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0xac, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frinta { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x54, 0xe1, 0xac, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frinta { z20.s, z21.s }, { z10.s, z11.s }" + + - + input: + bytes: [ 0x96, 0xe1, 0xac, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frinta { z22.s, z23.s }, { z12.s, z13.s }" + + - + input: + bytes: [ 0xde, 0xe3, 0xac, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frinta { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x00, 0xe0, 0xbc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frinta { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x14, 0xe1, 0xbc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frinta { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x94, 0xe1, 0xbc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frinta { z20.s - z23.s }, { z12.s - z15.s }" + + - + input: + bytes: [ 0x9c, 0xe3, 0xbc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frinta { z28.s - z31.s }, { z28.s - z31.s }" diff --git a/tests/MC/AArch64/SME2/frintm.s.yaml b/tests/MC/AArch64/SME2/frintm.s.yaml new file mode 100644 index 0000000000..ea63de5995 --- /dev/null +++ b/tests/MC/AArch64/SME2/frintm.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintm { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x54, 0xe1, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintm { z20.s, z21.s }, { z10.s, z11.s }" + + - + input: + bytes: [ 0x96, 0xe1, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintm { z22.s, z23.s }, { z12.s, z13.s }" + + - + input: + bytes: [ 0xde, 0xe3, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintm { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x00, 0xe0, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintm { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x14, 0xe1, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintm { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x94, 0xe1, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintm { z20.s - z23.s }, { z12.s - z15.s }" + + - + input: + bytes: [ 0x9c, 0xe3, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintm { z28.s - z31.s }, { z28.s - z31.s }" diff --git a/tests/MC/AArch64/SME2/frintn.s.yaml b/tests/MC/AArch64/SME2/frintn.s.yaml new file mode 100644 index 0000000000..cd9e755a82 --- /dev/null +++ b/tests/MC/AArch64/SME2/frintn.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintn { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x54, 0xe1, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintn { z20.s, z21.s }, { z10.s, z11.s }" + + - + input: + bytes: [ 0x96, 0xe1, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintn { z22.s, z23.s }, { z12.s, z13.s }" + + - + input: + bytes: [ 0xde, 0xe3, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintn { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x00, 0xe0, 0xb8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintn { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x14, 0xe1, 0xb8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintn { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x94, 0xe1, 0xb8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintn { z20.s - z23.s }, { z12.s - z15.s }" + + - + input: + bytes: [ 0x9c, 0xe3, 0xb8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintn { z28.s - z31.s }, { z28.s - z31.s }" diff --git a/tests/MC/AArch64/SME2/frintp.s.yaml b/tests/MC/AArch64/SME2/frintp.s.yaml new file mode 100644 index 0000000000..1b63b5610d --- /dev/null +++ b/tests/MC/AArch64/SME2/frintp.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintp { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x54, 0xe1, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintp { z20.s, z21.s }, { z10.s, z11.s }" + + - + input: + bytes: [ 0x96, 0xe1, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintp { z22.s, z23.s }, { z12.s, z13.s }" + + - + input: + bytes: [ 0xde, 0xe3, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintp { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x00, 0xe0, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintp { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x14, 0xe1, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintp { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x94, 0xe1, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintp { z20.s - z23.s }, { z12.s - z15.s }" + + - + input: + bytes: [ 0x9c, 0xe3, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "frintp { z28.s - z31.s }, { z28.s - z31.s }" diff --git a/tests/MC/AArch64/SME2/fsub.s.yaml b/tests/MC/AArch64/SME2/fsub.s.yaml new file mode 100644 index 0000000000..9e508d6e3d --- /dev/null +++ b/tests/MC/AArch64/SME2/fsub.s.yaml @@ -0,0 +1,960 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x1c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 0, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x08, 0x1c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 0, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x4d, 0x5d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w10, 5, vgx2], { z10.d, z11.d }" + + - + input: + bytes: [ 0x4d, 0x5d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w10, 5, vgx2], { z10.d, z11.d }" + + - + input: + bytes: [ 0x8f, 0x7d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w11, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x8f, 0x7d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w11, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0xcf, 0x7f, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w11, 7, vgx2], { z30.d, z31.d }" + + - + input: + bytes: [ 0xcf, 0x7f, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w11, 7, vgx2], { z30.d, z31.d }" + + - + input: + bytes: [ 0x0d, 0x1e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 5, vgx2], { z16.d, z17.d }" + + - + input: + bytes: [ 0x0d, 0x1e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 5, vgx2], { z16.d, z17.d }" + + - + input: + bytes: [ 0x09, 0x1c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x09, 0x1c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x48, 0x5e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w10, 0, vgx2], { z18.d, z19.d }" + + - + input: + bytes: [ 0x48, 0x5e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w10, 0, vgx2], { z18.d, z19.d }" + + - + input: + bytes: [ 0x88, 0x1d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 0, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x88, 0x1d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 0, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x09, 0x5c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w10, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x09, 0x5c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w10, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0xcd, 0x1e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 5, vgx2], { z22.d, z23.d }" + + - + input: + bytes: [ 0xcd, 0x1e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 5, vgx2], { z22.d, z23.d }" + + - + input: + bytes: [ 0x0a, 0x7d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w11, 2, vgx2], { z8.d, z9.d }" + + - + input: + bytes: [ 0x0a, 0x7d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w11, 2, vgx2], { z8.d, z9.d }" + + - + input: + bytes: [ 0x8f, 0x3d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w9, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x8f, 0x3d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w9, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x08, 0x1c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 0, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x08, 0x1c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 0, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x4d, 0x5d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w10, 5, vgx2], { z10.s, z11.s }" + + - + input: + bytes: [ 0x4d, 0x5d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w10, 5, vgx2], { z10.s, z11.s }" + + - + input: + bytes: [ 0x8f, 0x7d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w11, 7, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0x8f, 0x7d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w11, 7, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0xcf, 0x7f, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w11, 7, vgx2], { z30.s, z31.s }" + + - + input: + bytes: [ 0xcf, 0x7f, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w11, 7, vgx2], { z30.s, z31.s }" + + - + input: + bytes: [ 0x0d, 0x1e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 5, vgx2], { z16.s, z17.s }" + + - + input: + bytes: [ 0x0d, 0x1e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 5, vgx2], { z16.s, z17.s }" + + - + input: + bytes: [ 0x09, 0x1c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 1, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x09, 0x1c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 1, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x48, 0x5e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w10, 0, vgx2], { z18.s, z19.s }" + + - + input: + bytes: [ 0x48, 0x5e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w10, 0, vgx2], { z18.s, z19.s }" + + - + input: + bytes: [ 0x88, 0x1d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 0, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0x88, 0x1d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 0, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0x09, 0x5c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w10, 1, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x09, 0x5c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w10, 1, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0xcd, 0x1e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 5, vgx2], { z22.s, z23.s }" + + - + input: + bytes: [ 0xcd, 0x1e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 5, vgx2], { z22.s, z23.s }" + + - + input: + bytes: [ 0x0a, 0x7d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w11, 2, vgx2], { z8.s, z9.s }" + + - + input: + bytes: [ 0x0a, 0x7d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w11, 2, vgx2], { z8.s, z9.s }" + + - + input: + bytes: [ 0x8f, 0x3d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w9, 7, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0x8f, 0x3d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w9, 7, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0x08, 0x1c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 0, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x08, 0x1c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 0, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x0d, 0x5d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w10, 5, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x0d, 0x5d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w10, 5, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x8f, 0x7d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w11, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x8f, 0x7d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w11, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x8f, 0x7f, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w11, 7, vgx4], { z28.d - z31.d }" + + - + input: + bytes: [ 0x8f, 0x7f, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w11, 7, vgx4], { z28.d - z31.d }" + + - + input: + bytes: [ 0x0d, 0x1e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 5, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x0d, 0x1e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 5, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x09, 0x1c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x09, 0x1c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x08, 0x5e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w10, 0, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x08, 0x5e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w10, 0, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x88, 0x1d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 0, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x88, 0x1d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 0, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x09, 0x5c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w10, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x09, 0x5c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w10, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x8d, 0x1e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 5, vgx4], { z20.d - z23.d }" + + - + input: + bytes: [ 0x8d, 0x1e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w8, 5, vgx4], { z20.d - z23.d }" + + - + input: + bytes: [ 0x0a, 0x7d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w11, 2, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x0a, 0x7d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w11, 2, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x8f, 0x3d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w9, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x8f, 0x3d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.d[w9, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x08, 0x1c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 0, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x08, 0x1c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 0, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x0d, 0x5d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w10, 5, vgx4], { z8.s - z11.s }" + + - + input: + bytes: [ 0x0d, 0x5d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w10, 5, vgx4], { z8.s - z11.s }" + + - + input: + bytes: [ 0x8f, 0x7d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w11, 7, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x8f, 0x7d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w11, 7, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x8f, 0x7f, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w11, 7, vgx4], { z28.s - z31.s }" + + - + input: + bytes: [ 0x8f, 0x7f, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w11, 7, vgx4], { z28.s - z31.s }" + + - + input: + bytes: [ 0x0d, 0x1e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 5, vgx4], { z16.s - z19.s }" + + - + input: + bytes: [ 0x0d, 0x1e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 5, vgx4], { z16.s - z19.s }" + + - + input: + bytes: [ 0x09, 0x1c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 1, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x09, 0x1c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 1, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x08, 0x5e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w10, 0, vgx4], { z16.s - z19.s }" + + - + input: + bytes: [ 0x08, 0x5e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w10, 0, vgx4], { z16.s - z19.s }" + + - + input: + bytes: [ 0x88, 0x1d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 0, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x88, 0x1d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 0, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x09, 0x5c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w10, 1, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x09, 0x5c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w10, 1, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x8d, 0x1e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 5, vgx4], { z20.s - z23.s }" + + - + input: + bytes: [ 0x8d, 0x1e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w8, 5, vgx4], { z20.s - z23.s }" + + - + input: + bytes: [ 0x0a, 0x7d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w11, 2, vgx4], { z8.s - z11.s }" + + - + input: + bytes: [ 0x0a, 0x7d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w11, 2, vgx4], { z8.s - z11.s }" + + - + input: + bytes: [ 0x8f, 0x3d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w9, 7, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x8f, 0x3d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ] + expected: + insns: + - + asm_text: "fsub za.s[w9, 7, vgx4], { z12.s - z15.s }" diff --git a/tests/MC/AArch64/SME2/fvdot.s.yaml b/tests/MC/AArch64/SME2/fvdot.s.yaml new file mode 100644 index 0000000000..eafd23ef8e --- /dev/null +++ b/tests/MC/AArch64/SME2/fvdot.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x00, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x08, 0x00, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x4d, 0x45, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x4d, 0x45, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x8f, 0x6d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]" + + - + input: + bytes: [ 0x8f, 0x6d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]" + + - + input: + bytes: [ 0xcf, 0x6f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]" + + - + input: + bytes: [ 0xcf, 0x6f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]" + + - + input: + bytes: [ 0x0d, 0x0e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]" + + - + input: + bytes: [ 0x0d, 0x0e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]" + + - + input: + bytes: [ 0x09, 0x04, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x09, 0x04, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x48, 0x46, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x48, 0x46, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x88, 0x09, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]" + + - + input: + bytes: [ 0x88, 0x09, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]" + + - + input: + bytes: [ 0x09, 0x48, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]" + + - + input: + bytes: [ 0x09, 0x48, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]" + + - + input: + bytes: [ 0xcd, 0x0a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0xcd, 0x0a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x0a, 0x65, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0x0a, 0x65, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0x8f, 0x29, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]" + + - + input: + bytes: [ 0x8f, 0x29, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]" diff --git a/tests/MC/AArch64/SME2/ld1b.s.yaml b/tests/MC/AArch64/SME2/ld1b.s.yaml new file mode 100644 index 0000000000..ea9b2ab9c0 --- /dev/null +++ b/tests/MC/AArch64/SME2/ld1b.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z0.b, z8.b }, pn8/z, [x0, x0]" + + - + input: + bytes: [ 0x55, 0x15, 0x15, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z21.b, z29.b }, pn13/z, [x10, x21]" + + - + input: + bytes: [ 0xb7, 0x0d, 0x08, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z23.b, z31.b }, pn11/z, [x13, x8]" + + - + input: + bytes: [ 0xf7, 0x1f, 0x1f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z23.b, z31.b }, pn15/z, [sp, xzr]" + + - + input: + bytes: [ 0x00, 0x00, 0x40, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z0.b, z8.b }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0x15, 0x45, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z21.b, z29.b }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x0d, 0x48, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z23.b, z31.b }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xf7, 0x1f, 0x4f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z23.b, z31.b }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0x80, 0x00, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x0]" + + - + input: + bytes: [ 0x51, 0x95, 0x15, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z17.b, z21.b, z25.b, z29.b }, pn13/z, [x10, x21]" + + - + input: + bytes: [ 0xb3, 0x8d, 0x08, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z19.b, z23.b, z27.b, z31.b }, pn11/z, [x13, x8]" + + - + input: + bytes: [ 0xf3, 0x9f, 0x1f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z19.b, z23.b, z27.b, z31.b }, pn15/z, [sp, xzr]" + + - + input: + bytes: [ 0x00, 0x80, 0x40, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0]" + + - + input: + bytes: [ 0x51, 0x95, 0x45, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z17.b, z21.b, z25.b, z29.b }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb3, 0x8d, 0x48, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z19.b, z23.b, z27.b, z31.b }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xf3, 0x9f, 0x4f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z19.b, z23.b, z27.b, z31.b }, pn15/z, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SME2/ld1d.s.yaml b/tests/MC/AArch64/SME2/ld1d.s.yaml new file mode 100644 index 0000000000..b2ad76bd50 --- /dev/null +++ b/tests/MC/AArch64/SME2/ld1d.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0x00, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z0.d, z8.d }, pn8/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x55, 0x75, 0x15, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z21.d, z29.d }, pn13/z, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x08, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z23.d, z31.d }, pn11/z, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xf7, 0x7f, 0x1f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z23.d, z31.d }, pn15/z, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x00, 0x60, 0x40, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z0.d, z8.d }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0x75, 0x45, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z21.d, z29.d }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x48, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z23.d, z31.d }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xf7, 0x7f, 0x4f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z23.d, z31.d }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x51, 0xf5, 0x15, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z17.d, z21.d, z25.d, z29.d }, pn13/z, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb3, 0xed, 0x08, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z19.d, z23.d, z27.d, z31.d }, pn11/z, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xf3, 0xff, 0x1f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z19.d, z23.d, z27.d, z31.d }, pn15/z, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0]" + + - + input: + bytes: [ 0x51, 0xf5, 0x45, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z17.d, z21.d, z25.d, z29.d }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb3, 0xed, 0x48, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z19.d, z23.d, z27.d, z31.d }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xf3, 0xff, 0x4f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z19.d, z23.d, z27.d, z31.d }, pn15/z, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SME2/ld1h.s.yaml b/tests/MC/AArch64/SME2/ld1h.s.yaml new file mode 100644 index 0000000000..72fe95b134 --- /dev/null +++ b/tests/MC/AArch64/SME2/ld1h.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x00, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z0.h, z8.h }, pn8/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x55, 0x35, 0x15, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z21.h, z29.h }, pn13/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x08, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z23.h, z31.h }, pn11/z, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xf7, 0x3f, 0x1f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z23.h, z31.h }, pn15/z, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x00, 0x20, 0x40, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z0.h, z8.h }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0x35, 0x45, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z21.h, z29.h }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x48, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z23.h, z31.h }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xf7, 0x3f, 0x4f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z23.h, z31.h }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x51, 0xb5, 0x15, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z17.h, z21.h, z25.h, z29.h }, pn13/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb3, 0xad, 0x08, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z19.h, z23.h, z27.h, z31.h }, pn11/z, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xf3, 0xbf, 0x1f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z19.h, z23.h, z27.h, z31.h }, pn15/z, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0]" + + - + input: + bytes: [ 0x51, 0xb5, 0x45, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z17.h, z21.h, z25.h, z29.h }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb3, 0xad, 0x48, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z19.h, z23.h, z27.h, z31.h }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xf3, 0xbf, 0x4f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z19.h, z23.h, z27.h, z31.h }, pn15/z, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SME2/ld1w.s.yaml b/tests/MC/AArch64/SME2/ld1w.s.yaml new file mode 100644 index 0000000000..3704d0098f --- /dev/null +++ b/tests/MC/AArch64/SME2/ld1w.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0x00, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z0.s, z8.s }, pn8/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x55, 0x55, 0x15, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z21.s, z29.s }, pn13/z, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x08, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z23.s, z31.s }, pn11/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xf7, 0x5f, 0x1f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z23.s, z31.s }, pn15/z, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x00, 0x40, 0x40, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z0.s, z8.s }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0x55, 0x45, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z21.s, z29.s }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x48, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z23.s, z31.s }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xf7, 0x5f, 0x4f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z23.s, z31.s }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x00, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x51, 0xd5, 0x15, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z17.s, z21.s, z25.s, z29.s }, pn13/z, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb3, 0xcd, 0x08, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z19.s, z23.s, z27.s, z31.s }, pn11/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xf3, 0xdf, 0x1f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z19.s, z23.s, z27.s, z31.s }, pn15/z, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x00, 0xc0, 0x40, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0]" + + - + input: + bytes: [ 0x51, 0xd5, 0x45, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z17.s, z21.s, z25.s, z29.s }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb3, 0xcd, 0x48, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z19.s, z23.s, z27.s, z31.s }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xf3, 0xdf, 0x4f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z19.s, z23.s, z27.s, z31.s }, pn15/z, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SME2/ldnt1b.s.yaml b/tests/MC/AArch64/SME2/ldnt1b.s.yaml new file mode 100644 index 0000000000..786d373bbc --- /dev/null +++ b/tests/MC/AArch64/SME2/ldnt1b.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x00, 0x00, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.b, z8.b }, pn8/z, [x0, x0]" + + - + input: + bytes: [ 0x5d, 0x15, 0x15, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z21.b, z29.b }, pn13/z, [x10, x21]" + + - + input: + bytes: [ 0xbf, 0x0d, 0x08, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z23.b, z31.b }, pn11/z, [x13, x8]" + + - + input: + bytes: [ 0xff, 0x1f, 0x1f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z23.b, z31.b }, pn15/z, [sp, xzr]" + + - + input: + bytes: [ 0x08, 0x00, 0x40, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.b, z8.b }, pn8/z, [x0]" + + - + input: + bytes: [ 0x5d, 0x15, 0x45, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z21.b, z29.b }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xbf, 0x0d, 0x48, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z23.b, z31.b }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x1f, 0x4f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z23.b, z31.b }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x08, 0x80, 0x00, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x0]" + + - + input: + bytes: [ 0x59, 0x95, 0x15, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z17.b, z21.b, z25.b, z29.b }, pn13/z, [x10, x21]" + + - + input: + bytes: [ 0xbb, 0x8d, 0x08, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z19.b, z23.b, z27.b, z31.b }, pn11/z, [x13, x8]" + + - + input: + bytes: [ 0xfb, 0x9f, 0x1f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z19.b, z23.b, z27.b, z31.b }, pn15/z, [sp, xzr]" + + - + input: + bytes: [ 0x08, 0x80, 0x40, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0]" + + - + input: + bytes: [ 0x59, 0x95, 0x45, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z17.b, z21.b, z25.b, z29.b }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xbb, 0x8d, 0x48, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z19.b, z23.b, z27.b, z31.b }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfb, 0x9f, 0x4f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z19.b, z23.b, z27.b, z31.b }, pn15/z, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SME2/ldnt1d.s.yaml b/tests/MC/AArch64/SME2/ldnt1d.s.yaml new file mode 100644 index 0000000000..f2f6383478 --- /dev/null +++ b/tests/MC/AArch64/SME2/ldnt1d.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x60, 0x00, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d, z8.d }, pn8/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x5d, 0x75, 0x15, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z21.d, z29.d }, pn13/z, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xbf, 0x6d, 0x08, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z23.d, z31.d }, pn11/z, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xff, 0x7f, 0x1f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z23.d, z31.d }, pn15/z, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x08, 0x60, 0x40, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d, z8.d }, pn8/z, [x0]" + + - + input: + bytes: [ 0x5d, 0x75, 0x45, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z21.d, z29.d }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xbf, 0x6d, 0x48, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z23.d, z31.d }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x7f, 0x4f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z23.d, z31.d }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x08, 0xe0, 0x00, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x59, 0xf5, 0x15, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z17.d, z21.d, z25.d, z29.d }, pn13/z, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xbb, 0xed, 0x08, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z19.d, z23.d, z27.d, z31.d }, pn11/z, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xfb, 0xff, 0x1f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z19.d, z23.d, z27.d, z31.d }, pn15/z, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x08, 0xe0, 0x40, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0]" + + - + input: + bytes: [ 0x59, 0xf5, 0x45, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z17.d, z21.d, z25.d, z29.d }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xbb, 0xed, 0x48, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z19.d, z23.d, z27.d, z31.d }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfb, 0xff, 0x4f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z19.d, z23.d, z27.d, z31.d }, pn15/z, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SME2/ldnt1h.s.yaml b/tests/MC/AArch64/SME2/ldnt1h.s.yaml new file mode 100644 index 0000000000..42ebce7210 --- /dev/null +++ b/tests/MC/AArch64/SME2/ldnt1h.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x20, 0x00, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.h, z8.h }, pn8/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x5d, 0x35, 0x15, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z21.h, z29.h }, pn13/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xbf, 0x2d, 0x08, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z23.h, z31.h }, pn11/z, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xff, 0x3f, 0x1f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z23.h, z31.h }, pn15/z, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x08, 0x20, 0x40, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.h, z8.h }, pn8/z, [x0]" + + - + input: + bytes: [ 0x5d, 0x35, 0x45, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z21.h, z29.h }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xbf, 0x2d, 0x48, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z23.h, z31.h }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x3f, 0x4f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z23.h, z31.h }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x08, 0xa0, 0x00, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x59, 0xb5, 0x15, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z17.h, z21.h, z25.h, z29.h }, pn13/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xbb, 0xad, 0x08, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z19.h, z23.h, z27.h, z31.h }, pn11/z, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xfb, 0xbf, 0x1f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z19.h, z23.h, z27.h, z31.h }, pn15/z, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x08, 0xa0, 0x40, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0]" + + - + input: + bytes: [ 0x59, 0xb5, 0x45, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z17.h, z21.h, z25.h, z29.h }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xbb, 0xad, 0x48, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z19.h, z23.h, z27.h, z31.h }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfb, 0xbf, 0x4f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z19.h, z23.h, z27.h, z31.h }, pn15/z, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SME2/ldnt1w.s.yaml b/tests/MC/AArch64/SME2/ldnt1w.s.yaml new file mode 100644 index 0000000000..2861ee921c --- /dev/null +++ b/tests/MC/AArch64/SME2/ldnt1w.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x40, 0x00, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s, z8.s }, pn8/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x5d, 0x55, 0x15, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z21.s, z29.s }, pn13/z, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xbf, 0x4d, 0x08, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z23.s, z31.s }, pn11/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xff, 0x5f, 0x1f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z23.s, z31.s }, pn15/z, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x08, 0x40, 0x40, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s, z8.s }, pn8/z, [x0]" + + - + input: + bytes: [ 0x5d, 0x55, 0x45, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z21.s, z29.s }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xbf, 0x4d, 0x48, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z23.s, z31.s }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x5f, 0x4f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z23.s, z31.s }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x08, 0xc0, 0x00, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x59, 0xd5, 0x15, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z17.s, z21.s, z25.s, z29.s }, pn13/z, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xbb, 0xcd, 0x08, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z19.s, z23.s, z27.s, z31.s }, pn11/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xfb, 0xdf, 0x1f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z19.s, z23.s, z27.s, z31.s }, pn15/z, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x08, 0xc0, 0x40, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0]" + + - + input: + bytes: [ 0x59, 0xd5, 0x45, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z17.s, z21.s, z25.s, z29.s }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xbb, 0xcd, 0x48, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z19.s, z23.s, z27.s, z31.s }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfb, 0xdf, 0x4f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z19.s, z23.s, z27.s, z31.s }, pn15/z, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SME2/ldr.s.yaml b/tests/MC/AArch64/SME2/ldr.s.yaml new file mode 100644 index 0000000000..bbaa3c0bcb --- /dev/null +++ b/tests/MC/AArch64/SME2/ldr.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x1f, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldr zt0, [x0]" + + - + input: + bytes: [ 0x40, 0x81, 0x1f, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldr zt0, [x10]" + + - + input: + bytes: [ 0xa0, 0x81, 0x1f, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldr zt0, [x13]" + + - + input: + bytes: [ 0xe0, 0x83, 0x1f, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldr zt0, [sp]" diff --git a/tests/MC/AArch64/SME2/luti2.s.yaml b/tests/MC/AArch64/SME2/luti2.s.yaml new file mode 100644 index 0000000000..e4eacd904f --- /dev/null +++ b/tests/MC/AArch64/SME2/luti2.s.yaml @@ -0,0 +1,360 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x10, 0xcc, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 z0.h, zt0, z0[0]" + + - + input: + bytes: [ 0x55, 0x51, 0xcd, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 z21.h, zt0, z10[5]" + + - + input: + bytes: [ 0xb7, 0xd1, 0xcc, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 z23.h, zt0, z13[3]" + + - + input: + bytes: [ 0xff, 0xd3, 0xcf, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 z31.h, zt0, z31[15]" + + - + input: + bytes: [ 0x00, 0x20, 0xcc, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 z0.s, zt0, z0[0]" + + - + input: + bytes: [ 0x55, 0x61, 0xcd, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 z21.s, zt0, z10[5]" + + - + input: + bytes: [ 0xb7, 0xe1, 0xcc, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 z23.s, zt0, z13[3]" + + - + input: + bytes: [ 0xff, 0xe3, 0xcf, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 z31.s, zt0, z31[15]" + + - + input: + bytes: [ 0x00, 0x00, 0xcc, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 z0.b, zt0, z0[0]" + + - + input: + bytes: [ 0x55, 0x41, 0xcd, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 z21.b, zt0, z10[5]" + + - + input: + bytes: [ 0xb7, 0xc1, 0xcc, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 z23.b, zt0, z13[3]" + + - + input: + bytes: [ 0xff, 0xc3, 0xcf, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 z31.b, zt0, z31[15]" + + - + input: + bytes: [ 0x00, 0x50, 0x8c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z0.h, z1.h }, zt0, z0[0]" + + - + input: + bytes: [ 0x54, 0x51, 0x8d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z20.h, z21.h }, zt0, z10[2]" + + - + input: + bytes: [ 0xb6, 0xd1, 0x8c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z22.h, z23.h }, zt0, z13[1]" + + - + input: + bytes: [ 0xfe, 0xd3, 0x8f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z30.h, z31.h }, zt0, z31[7]" + + - + input: + bytes: [ 0x00, 0x60, 0x8c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z0.s, z1.s }, zt0, z0[0]" + + - + input: + bytes: [ 0x54, 0x61, 0x8d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z20.s, z21.s }, zt0, z10[2]" + + - + input: + bytes: [ 0xb6, 0xe1, 0x8c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z22.s, z23.s }, zt0, z13[1]" + + - + input: + bytes: [ 0xfe, 0xe3, 0x8f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z30.s, z31.s }, zt0, z31[7]" + + - + input: + bytes: [ 0x00, 0x40, 0x8c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z0.b, z1.b }, zt0, z0[0]" + + - + input: + bytes: [ 0x54, 0x41, 0x8d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z20.b, z21.b }, zt0, z10[2]" + + - + input: + bytes: [ 0xb6, 0xc1, 0x8c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z22.b, z23.b }, zt0, z13[1]" + + - + input: + bytes: [ 0xfe, 0xc3, 0x8f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z30.b, z31.b }, zt0, z31[7]" + + - + input: + bytes: [ 0x00, 0x90, 0x8c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z0.h - z3.h }, zt0, z0[0]" + + - + input: + bytes: [ 0x54, 0x91, 0x8d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z20.h - z23.h }, zt0, z10[1]" + + - + input: + bytes: [ 0xb4, 0x91, 0x8c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z20.h - z23.h }, zt0, z13[0]" + + - + input: + bytes: [ 0xfc, 0x93, 0x8f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z28.h - z31.h }, zt0, z31[3]" + + - + input: + bytes: [ 0x00, 0xa0, 0x8c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z0.s - z3.s }, zt0, z0[0]" + + - + input: + bytes: [ 0x54, 0xa1, 0x8d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z20.s - z23.s }, zt0, z10[1]" + + - + input: + bytes: [ 0xb4, 0xa1, 0x8c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z20.s - z23.s }, zt0, z13[0]" + + - + input: + bytes: [ 0xfc, 0xa3, 0x8f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z28.s - z31.s }, zt0, z31[3]" + + - + input: + bytes: [ 0x00, 0x80, 0x8c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z0.b - z3.b }, zt0, z0[0]" + + - + input: + bytes: [ 0x54, 0x81, 0x8d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z20.b - z23.b }, zt0, z10[1]" + + - + input: + bytes: [ 0xb4, 0x81, 0x8c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z20.b - z23.b }, zt0, z13[0]" + + - + input: + bytes: [ 0xfc, 0x83, 0x8f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti2 { z28.b - z31.b }, zt0, z31[3]" diff --git a/tests/MC/AArch64/SME2/luti4.s.yaml b/tests/MC/AArch64/SME2/luti4.s.yaml new file mode 100644 index 0000000000..f49adc8cfb --- /dev/null +++ b/tests/MC/AArch64/SME2/luti4.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x10, 0xca, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 z0.h, zt0, z0[0]" + + - + input: + bytes: [ 0x55, 0x51, 0xcb, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 z21.h, zt0, z10[5]" + + - + input: + bytes: [ 0xb7, 0xd1, 0xca, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 z23.h, zt0, z13[3]" + + - + input: + bytes: [ 0xff, 0xd3, 0xcb, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 z31.h, zt0, z31[7]" + + - + input: + bytes: [ 0x00, 0x20, 0xca, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 z0.s, zt0, z0[0]" + + - + input: + bytes: [ 0x55, 0x61, 0xcb, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 z21.s, zt0, z10[5]" + + - + input: + bytes: [ 0xb7, 0xe1, 0xca, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 z23.s, zt0, z13[3]" + + - + input: + bytes: [ 0xff, 0xe3, 0xcb, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 z31.s, zt0, z31[7]" + + - + input: + bytes: [ 0x00, 0x00, 0xca, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 z0.b, zt0, z0[0]" + + - + input: + bytes: [ 0x55, 0x41, 0xcb, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 z21.b, zt0, z10[5]" + + - + input: + bytes: [ 0xb7, 0xc1, 0xca, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 z23.b, zt0, z13[3]" + + - + input: + bytes: [ 0xff, 0xc3, 0xcb, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 z31.b, zt0, z31[7]" + + - + input: + bytes: [ 0x00, 0x50, 0x8a, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z0.h, z1.h }, zt0, z0[0]" + + - + input: + bytes: [ 0x54, 0x51, 0x8b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z20.h, z21.h }, zt0, z10[2]" + + - + input: + bytes: [ 0xb6, 0xd1, 0x8a, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z22.h, z23.h }, zt0, z13[1]" + + - + input: + bytes: [ 0xfe, 0xd3, 0x8b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z30.h, z31.h }, zt0, z31[3]" + + - + input: + bytes: [ 0x00, 0x60, 0x8a, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z0.s, z1.s }, zt0, z0[0]" + + - + input: + bytes: [ 0x54, 0x61, 0x8b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z20.s, z21.s }, zt0, z10[2]" + + - + input: + bytes: [ 0xb6, 0xe1, 0x8a, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z22.s, z23.s }, zt0, z13[1]" + + - + input: + bytes: [ 0xfe, 0xe3, 0x8b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z30.s, z31.s }, zt0, z31[3]" + + - + input: + bytes: [ 0x00, 0x40, 0x8a, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z0.b, z1.b }, zt0, z0[0]" + + - + input: + bytes: [ 0x54, 0x41, 0x8b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z20.b, z21.b }, zt0, z10[2]" + + - + input: + bytes: [ 0xb6, 0xc1, 0x8a, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z22.b, z23.b }, zt0, z13[1]" + + - + input: + bytes: [ 0xfe, 0xc3, 0x8b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z30.b, z31.b }, zt0, z31[3]" + + - + input: + bytes: [ 0x00, 0x90, 0x8a, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z0.h - z3.h }, zt0, z0[0]" + + - + input: + bytes: [ 0x54, 0x91, 0x8b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z20.h - z23.h }, zt0, z10[1]" + + - + input: + bytes: [ 0xb4, 0x91, 0x8a, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z20.h - z23.h }, zt0, z13[0]" + + - + input: + bytes: [ 0xfc, 0x93, 0x8b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z28.h - z31.h }, zt0, z31[1]" + + - + input: + bytes: [ 0x00, 0xa0, 0x8a, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z0.s - z3.s }, zt0, z0[0]" + + - + input: + bytes: [ 0x54, 0xa1, 0x8b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z20.s - z23.s }, zt0, z10[1]" + + - + input: + bytes: [ 0xb4, 0xa1, 0x8a, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z20.s - z23.s }, zt0, z13[0]" + + - + input: + bytes: [ 0xfc, 0xa3, 0x8b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "luti4 { z28.s - z31.s }, zt0, z31[1]" diff --git a/tests/MC/AArch64/SME2/mova.s.yaml b/tests/MC/AArch64/SME2/mova.s.yaml new file mode 100644 index 0000000000..a5bcb16051 --- /dev/null +++ b/tests/MC/AArch64/SME2/mova.s.yaml @@ -0,0 +1,9000 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h, z1.h }, za0h.h[w12, 0:1]" + + - + input: + bytes: [ 0x54, 0x40, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.h, z21.h }, za0h.h[w14, 4:5]" + + - + input: + bytes: [ 0xb6, 0x60, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z22.h, z23.h }, za1h.h[w15, 2:3]" + + - + input: + bytes: [ 0xfe, 0x60, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z30.h, z31.h }, za1h.h[w15, 6:7]" + + - + input: + bytes: [ 0x24, 0x00, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.h, z5.h }, za0h.h[w12, 2:3]" + + - + input: + bytes: [ 0x20, 0x00, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h, z1.h }, za0h.h[w12, 2:3]" + + - + input: + bytes: [ 0x78, 0x40, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.h, z25.h }, za0h.h[w14, 6:7]" + + - + input: + bytes: [ 0x80, 0x00, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h, z1.h }, za1h.h[w12, 0:1]" + + - + input: + bytes: [ 0x30, 0x40, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.h, z17.h }, za0h.h[w14, 2:3]" + + - + input: + bytes: [ 0xdc, 0x00, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.h, z29.h }, za1h.h[w12, 4:5]" + + - + input: + bytes: [ 0x22, 0x60, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z2.h, z3.h }, za0h.h[w15, 2:3]" + + - + input: + bytes: [ 0x86, 0x20, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z6.h, z7.h }, za1h.h[w13, 0:1]" + + - + input: + bytes: [ 0x00, 0x00, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h, z1.h }, za0h.h[w12, 0:1]" + + - + input: + bytes: [ 0x54, 0x40, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.h, z21.h }, za0h.h[w14, 4:5]" + + - + input: + bytes: [ 0xb6, 0x60, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z22.h, z23.h }, za1h.h[w15, 2:3]" + + - + input: + bytes: [ 0xfe, 0x60, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z30.h, z31.h }, za1h.h[w15, 6:7]" + + - + input: + bytes: [ 0x24, 0x00, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.h, z5.h }, za0h.h[w12, 2:3]" + + - + input: + bytes: [ 0x20, 0x00, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h, z1.h }, za0h.h[w12, 2:3]" + + - + input: + bytes: [ 0x78, 0x40, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.h, z25.h }, za0h.h[w14, 6:7]" + + - + input: + bytes: [ 0x80, 0x00, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h, z1.h }, za1h.h[w12, 0:1]" + + - + input: + bytes: [ 0x30, 0x40, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.h, z17.h }, za0h.h[w14, 2:3]" + + - + input: + bytes: [ 0xdc, 0x00, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.h, z29.h }, za1h.h[w12, 4:5]" + + - + input: + bytes: [ 0x22, 0x60, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z2.h, z3.h }, za0h.h[w15, 2:3]" + + - + input: + bytes: [ 0x86, 0x20, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z6.h, z7.h }, za1h.h[w13, 0:1]" + + - + input: + bytes: [ 0x00, 0x80, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h, z1.h }, za0v.h[w12, 0:1]" + + - + input: + bytes: [ 0x54, 0xc0, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.h, z21.h }, za0v.h[w14, 4:5]" + + - + input: + bytes: [ 0xb6, 0xe0, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z22.h, z23.h }, za1v.h[w15, 2:3]" + + - + input: + bytes: [ 0xfe, 0xe0, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z30.h, z31.h }, za1v.h[w15, 6:7]" + + - + input: + bytes: [ 0x24, 0x80, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.h, z5.h }, za0v.h[w12, 2:3]" + + - + input: + bytes: [ 0x20, 0x80, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h, z1.h }, za0v.h[w12, 2:3]" + + - + input: + bytes: [ 0x78, 0xc0, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.h, z25.h }, za0v.h[w14, 6:7]" + + - + input: + bytes: [ 0x80, 0x80, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h, z1.h }, za1v.h[w12, 0:1]" + + - + input: + bytes: [ 0x30, 0xc0, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.h, z17.h }, za0v.h[w14, 2:3]" + + - + input: + bytes: [ 0xdc, 0x80, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.h, z29.h }, za1v.h[w12, 4:5]" + + - + input: + bytes: [ 0x22, 0xe0, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z2.h, z3.h }, za0v.h[w15, 2:3]" + + - + input: + bytes: [ 0x86, 0xa0, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z6.h, z7.h }, za1v.h[w13, 0:1]" + + - + input: + bytes: [ 0x00, 0x80, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h, z1.h }, za0v.h[w12, 0:1]" + + - + input: + bytes: [ 0x54, 0xc0, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.h, z21.h }, za0v.h[w14, 4:5]" + + - + input: + bytes: [ 0xb6, 0xe0, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z22.h, z23.h }, za1v.h[w15, 2:3]" + + - + input: + bytes: [ 0xfe, 0xe0, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z30.h, z31.h }, za1v.h[w15, 6:7]" + + - + input: + bytes: [ 0x24, 0x80, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.h, z5.h }, za0v.h[w12, 2:3]" + + - + input: + bytes: [ 0x20, 0x80, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h, z1.h }, za0v.h[w12, 2:3]" + + - + input: + bytes: [ 0x78, 0xc0, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.h, z25.h }, za0v.h[w14, 6:7]" + + - + input: + bytes: [ 0x80, 0x80, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h, z1.h }, za1v.h[w12, 0:1]" + + - + input: + bytes: [ 0x30, 0xc0, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.h, z17.h }, za0v.h[w14, 2:3]" + + - + input: + bytes: [ 0xdc, 0x80, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.h, z29.h }, za1v.h[w12, 4:5]" + + - + input: + bytes: [ 0x22, 0xe0, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z2.h, z3.h }, za0v.h[w15, 2:3]" + + - + input: + bytes: [ 0x86, 0xa0, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z6.h, z7.h }, za1v.h[w13, 0:1]" + + - + input: + bytes: [ 0x00, 0x00, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 0:1], { z0.h, z1.h }" + + - + input: + bytes: [ 0x45, 0x41, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w14, 2:3], { z10.h, z11.h }" + + - + input: + bytes: [ 0x87, 0x61, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w15, 6:7], { z12.h, z13.h }" + + - + input: + bytes: [ 0xc7, 0x63, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w15, 6:7], { z30.h, z31.h }" + + - + input: + bytes: [ 0x05, 0x02, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w12, 2:3], { z16.h, z17.h }" + + - + input: + bytes: [ 0x01, 0x00, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 2:3], { z0.h, z1.h }" + + - + input: + bytes: [ 0x40, 0x42, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w14, 0:1], { z18.h, z19.h }" + + - + input: + bytes: [ 0x80, 0x01, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 0:1], { z12.h, z13.h }" + + - + input: + bytes: [ 0x01, 0x40, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w14, 2:3], { z0.h, z1.h }" + + - + input: + bytes: [ 0xc5, 0x02, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w12, 2:3], { z22.h, z23.h }" + + - + input: + bytes: [ 0x02, 0x61, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w15, 4:5], { z8.h, z9.h }" + + - + input: + bytes: [ 0x87, 0x21, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w13, 6:7], { z12.h, z13.h }" + + - + input: + bytes: [ 0x00, 0x00, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 0:1], { z0.h, z1.h }" + + - + input: + bytes: [ 0x45, 0x41, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w14, 2:3], { z10.h, z11.h }" + + - + input: + bytes: [ 0x87, 0x61, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w15, 6:7], { z12.h, z13.h }" + + - + input: + bytes: [ 0xc7, 0x63, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w15, 6:7], { z30.h, z31.h }" + + - + input: + bytes: [ 0x05, 0x02, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w12, 2:3], { z16.h, z17.h }" + + - + input: + bytes: [ 0x01, 0x00, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 2:3], { z0.h, z1.h }" + + - + input: + bytes: [ 0x40, 0x42, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w14, 0:1], { z18.h, z19.h }" + + - + input: + bytes: [ 0x80, 0x01, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 0:1], { z12.h, z13.h }" + + - + input: + bytes: [ 0x01, 0x40, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w14, 2:3], { z0.h, z1.h }" + + - + input: + bytes: [ 0xc5, 0x02, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w12, 2:3], { z22.h, z23.h }" + + - + input: + bytes: [ 0x02, 0x61, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w15, 4:5], { z8.h, z9.h }" + + - + input: + bytes: [ 0x87, 0x21, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w13, 6:7], { z12.h, z13.h }" + + - + input: + bytes: [ 0x00, 0x80, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 0:1], { z0.h, z1.h }" + + - + input: + bytes: [ 0x45, 0xc1, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w14, 2:3], { z10.h, z11.h }" + + - + input: + bytes: [ 0x87, 0xe1, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w15, 6:7], { z12.h, z13.h }" + + - + input: + bytes: [ 0xc7, 0xe3, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w15, 6:7], { z30.h, z31.h }" + + - + input: + bytes: [ 0x05, 0x82, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w12, 2:3], { z16.h, z17.h }" + + - + input: + bytes: [ 0x01, 0x80, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 2:3], { z0.h, z1.h }" + + - + input: + bytes: [ 0x40, 0xc2, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w14, 0:1], { z18.h, z19.h }" + + - + input: + bytes: [ 0x80, 0x81, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 0:1], { z12.h, z13.h }" + + - + input: + bytes: [ 0x01, 0xc0, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w14, 2:3], { z0.h, z1.h }" + + - + input: + bytes: [ 0xc5, 0x82, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w12, 2:3], { z22.h, z23.h }" + + - + input: + bytes: [ 0x02, 0xe1, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w15, 4:5], { z8.h, z9.h }" + + - + input: + bytes: [ 0x87, 0xa1, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w13, 6:7], { z12.h, z13.h }" + + - + input: + bytes: [ 0x00, 0x80, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 0:1], { z0.h, z1.h }" + + - + input: + bytes: [ 0x45, 0xc1, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w14, 2:3], { z10.h, z11.h }" + + - + input: + bytes: [ 0x87, 0xe1, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w15, 6:7], { z12.h, z13.h }" + + - + input: + bytes: [ 0xc7, 0xe3, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w15, 6:7], { z30.h, z31.h }" + + - + input: + bytes: [ 0x05, 0x82, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w12, 2:3], { z16.h, z17.h }" + + - + input: + bytes: [ 0x01, 0x80, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 2:3], { z0.h, z1.h }" + + - + input: + bytes: [ 0x40, 0xc2, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w14, 0:1], { z18.h, z19.h }" + + - + input: + bytes: [ 0x80, 0x81, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 0:1], { z12.h, z13.h }" + + - + input: + bytes: [ 0x01, 0xc0, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w14, 2:3], { z0.h, z1.h }" + + - + input: + bytes: [ 0xc5, 0x82, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w12, 2:3], { z22.h, z23.h }" + + - + input: + bytes: [ 0x02, 0xe1, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w15, 4:5], { z8.h, z9.h }" + + - + input: + bytes: [ 0x87, 0xa1, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w13, 6:7], { z12.h, z13.h }" + + - + input: + bytes: [ 0x00, 0x00, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s, z1.s }, za0h.s[w12, 0:1]" + + - + input: + bytes: [ 0x54, 0x40, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.s, z21.s }, za1h.s[w14, 0:1]" + + - + input: + bytes: [ 0xb6, 0x60, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z22.s, z23.s }, za2h.s[w15, 2:3]" + + - + input: + bytes: [ 0xfe, 0x60, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z30.s, z31.s }, za3h.s[w15, 2:3]" + + - + input: + bytes: [ 0x24, 0x00, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.s, z5.s }, za0h.s[w12, 2:3]" + + - + input: + bytes: [ 0x20, 0x00, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s, z1.s }, za0h.s[w12, 2:3]" + + - + input: + bytes: [ 0x78, 0x40, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.s, z25.s }, za1h.s[w14, 2:3]" + + - + input: + bytes: [ 0x80, 0x00, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s, z1.s }, za2h.s[w12, 0:1]" + + - + input: + bytes: [ 0x30, 0x40, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.s, z17.s }, za0h.s[w14, 2:3]" + + - + input: + bytes: [ 0xdc, 0x00, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.s, z29.s }, za3h.s[w12, 0:1]" + + - + input: + bytes: [ 0x22, 0x60, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z2.s, z3.s }, za0h.s[w15, 2:3]" + + - + input: + bytes: [ 0x86, 0x20, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z6.s, z7.s }, za2h.s[w13, 0:1]" + + - + input: + bytes: [ 0x00, 0x00, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s, z1.s }, za0h.s[w12, 0:1]" + + - + input: + bytes: [ 0x54, 0x40, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.s, z21.s }, za1h.s[w14, 0:1]" + + - + input: + bytes: [ 0xb6, 0x60, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z22.s, z23.s }, za2h.s[w15, 2:3]" + + - + input: + bytes: [ 0xfe, 0x60, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z30.s, z31.s }, za3h.s[w15, 2:3]" + + - + input: + bytes: [ 0x24, 0x00, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.s, z5.s }, za0h.s[w12, 2:3]" + + - + input: + bytes: [ 0x20, 0x00, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s, z1.s }, za0h.s[w12, 2:3]" + + - + input: + bytes: [ 0x78, 0x40, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.s, z25.s }, za1h.s[w14, 2:3]" + + - + input: + bytes: [ 0x80, 0x00, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s, z1.s }, za2h.s[w12, 0:1]" + + - + input: + bytes: [ 0x30, 0x40, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.s, z17.s }, za0h.s[w14, 2:3]" + + - + input: + bytes: [ 0xdc, 0x00, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.s, z29.s }, za3h.s[w12, 0:1]" + + - + input: + bytes: [ 0x22, 0x60, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z2.s, z3.s }, za0h.s[w15, 2:3]" + + - + input: + bytes: [ 0x86, 0x20, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z6.s, z7.s }, za2h.s[w13, 0:1]" + + - + input: + bytes: [ 0x00, 0x80, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s, z1.s }, za0v.s[w12, 0:1]" + + - + input: + bytes: [ 0x54, 0xc0, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.s, z21.s }, za1v.s[w14, 0:1]" + + - + input: + bytes: [ 0xb6, 0xe0, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z22.s, z23.s }, za2v.s[w15, 2:3]" + + - + input: + bytes: [ 0xfe, 0xe0, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z30.s, z31.s }, za3v.s[w15, 2:3]" + + - + input: + bytes: [ 0x24, 0x80, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.s, z5.s }, za0v.s[w12, 2:3]" + + - + input: + bytes: [ 0x20, 0x80, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s, z1.s }, za0v.s[w12, 2:3]" + + - + input: + bytes: [ 0x78, 0xc0, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.s, z25.s }, za1v.s[w14, 2:3]" + + - + input: + bytes: [ 0x80, 0x80, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s, z1.s }, za2v.s[w12, 0:1]" + + - + input: + bytes: [ 0x30, 0xc0, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.s, z17.s }, za0v.s[w14, 2:3]" + + - + input: + bytes: [ 0xdc, 0x80, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.s, z29.s }, za3v.s[w12, 0:1]" + + - + input: + bytes: [ 0x22, 0xe0, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z2.s, z3.s }, za0v.s[w15, 2:3]" + + - + input: + bytes: [ 0x86, 0xa0, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z6.s, z7.s }, za2v.s[w13, 0:1]" + + - + input: + bytes: [ 0x00, 0x80, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s, z1.s }, za0v.s[w12, 0:1]" + + - + input: + bytes: [ 0x54, 0xc0, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.s, z21.s }, za1v.s[w14, 0:1]" + + - + input: + bytes: [ 0xb6, 0xe0, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z22.s, z23.s }, za2v.s[w15, 2:3]" + + - + input: + bytes: [ 0xfe, 0xe0, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z30.s, z31.s }, za3v.s[w15, 2:3]" + + - + input: + bytes: [ 0x24, 0x80, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.s, z5.s }, za0v.s[w12, 2:3]" + + - + input: + bytes: [ 0x20, 0x80, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s, z1.s }, za0v.s[w12, 2:3]" + + - + input: + bytes: [ 0x78, 0xc0, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.s, z25.s }, za1v.s[w14, 2:3]" + + - + input: + bytes: [ 0x80, 0x80, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s, z1.s }, za2v.s[w12, 0:1]" + + - + input: + bytes: [ 0x30, 0xc0, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.s, z17.s }, za0v.s[w14, 2:3]" + + - + input: + bytes: [ 0xdc, 0x80, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.s, z29.s }, za3v.s[w12, 0:1]" + + - + input: + bytes: [ 0x22, 0xe0, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z2.s, z3.s }, za0v.s[w15, 2:3]" + + - + input: + bytes: [ 0x86, 0xa0, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z6.s, z7.s }, za2v.s[w13, 0:1]" + + - + input: + bytes: [ 0x00, 0x00, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.s[w12, 0:1], { z0.s, z1.s }" + + - + input: + bytes: [ 0x45, 0x41, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2h.s[w14, 2:3], { z10.s, z11.s }" + + - + input: + bytes: [ 0x87, 0x61, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3h.s[w15, 2:3], { z12.s, z13.s }" + + - + input: + bytes: [ 0xc7, 0x63, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3h.s[w15, 2:3], { z30.s, z31.s }" + + - + input: + bytes: [ 0x05, 0x02, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2h.s[w12, 2:3], { z16.s, z17.s }" + + - + input: + bytes: [ 0x01, 0x00, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.s[w12, 2:3], { z0.s, z1.s }" + + - + input: + bytes: [ 0x40, 0x42, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.s[w14, 0:1], { z18.s, z19.s }" + + - + input: + bytes: [ 0x80, 0x01, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.s[w12, 0:1], { z12.s, z13.s }" + + - + input: + bytes: [ 0x01, 0x40, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.s[w14, 2:3], { z0.s, z1.s }" + + - + input: + bytes: [ 0xc5, 0x02, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2h.s[w12, 2:3], { z22.s, z23.s }" + + - + input: + bytes: [ 0x02, 0x61, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.s[w15, 0:1], { z8.s, z9.s }" + + - + input: + bytes: [ 0x87, 0x21, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3h.s[w13, 2:3], { z12.s, z13.s }" + + - + input: + bytes: [ 0x00, 0x00, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.s[w12, 0:1], { z0.s, z1.s }" + + - + input: + bytes: [ 0x45, 0x41, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2h.s[w14, 2:3], { z10.s, z11.s }" + + - + input: + bytes: [ 0x87, 0x61, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3h.s[w15, 2:3], { z12.s, z13.s }" + + - + input: + bytes: [ 0xc7, 0x63, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3h.s[w15, 2:3], { z30.s, z31.s }" + + - + input: + bytes: [ 0x05, 0x02, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2h.s[w12, 2:3], { z16.s, z17.s }" + + - + input: + bytes: [ 0x01, 0x00, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.s[w12, 2:3], { z0.s, z1.s }" + + - + input: + bytes: [ 0x40, 0x42, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.s[w14, 0:1], { z18.s, z19.s }" + + - + input: + bytes: [ 0x80, 0x01, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.s[w12, 0:1], { z12.s, z13.s }" + + - + input: + bytes: [ 0x01, 0x40, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.s[w14, 2:3], { z0.s, z1.s }" + + - + input: + bytes: [ 0xc5, 0x02, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2h.s[w12, 2:3], { z22.s, z23.s }" + + - + input: + bytes: [ 0x02, 0x61, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.s[w15, 0:1], { z8.s, z9.s }" + + - + input: + bytes: [ 0x87, 0x21, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3h.s[w13, 2:3], { z12.s, z13.s }" + + - + input: + bytes: [ 0x00, 0x80, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.s[w12, 0:1], { z0.s, z1.s }" + + - + input: + bytes: [ 0x45, 0xc1, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2v.s[w14, 2:3], { z10.s, z11.s }" + + - + input: + bytes: [ 0x87, 0xe1, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3v.s[w15, 2:3], { z12.s, z13.s }" + + - + input: + bytes: [ 0xc7, 0xe3, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3v.s[w15, 2:3], { z30.s, z31.s }" + + - + input: + bytes: [ 0x05, 0x82, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2v.s[w12, 2:3], { z16.s, z17.s }" + + - + input: + bytes: [ 0x01, 0x80, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.s[w12, 2:3], { z0.s, z1.s }" + + - + input: + bytes: [ 0x40, 0xc2, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.s[w14, 0:1], { z18.s, z19.s }" + + - + input: + bytes: [ 0x80, 0x81, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.s[w12, 0:1], { z12.s, z13.s }" + + - + input: + bytes: [ 0x01, 0xc0, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.s[w14, 2:3], { z0.s, z1.s }" + + - + input: + bytes: [ 0xc5, 0x82, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2v.s[w12, 2:3], { z22.s, z23.s }" + + - + input: + bytes: [ 0x02, 0xe1, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.s[w15, 0:1], { z8.s, z9.s }" + + - + input: + bytes: [ 0x87, 0xa1, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3v.s[w13, 2:3], { z12.s, z13.s }" + + - + input: + bytes: [ 0x00, 0x80, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.s[w12, 0:1], { z0.s, z1.s }" + + - + input: + bytes: [ 0x45, 0xc1, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2v.s[w14, 2:3], { z10.s, z11.s }" + + - + input: + bytes: [ 0x87, 0xe1, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3v.s[w15, 2:3], { z12.s, z13.s }" + + - + input: + bytes: [ 0xc7, 0xe3, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3v.s[w15, 2:3], { z30.s, z31.s }" + + - + input: + bytes: [ 0x05, 0x82, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2v.s[w12, 2:3], { z16.s, z17.s }" + + - + input: + bytes: [ 0x01, 0x80, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.s[w12, 2:3], { z0.s, z1.s }" + + - + input: + bytes: [ 0x40, 0xc2, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.s[w14, 0:1], { z18.s, z19.s }" + + - + input: + bytes: [ 0x80, 0x81, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.s[w12, 0:1], { z12.s, z13.s }" + + - + input: + bytes: [ 0x01, 0xc0, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.s[w14, 2:3], { z0.s, z1.s }" + + - + input: + bytes: [ 0xc5, 0x82, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2v.s[w12, 2:3], { z22.s, z23.s }" + + - + input: + bytes: [ 0x02, 0xe1, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.s[w15, 0:1], { z8.s, z9.s }" + + - + input: + bytes: [ 0x87, 0xa1, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3v.s[w13, 2:3], { z12.s, z13.s }" + + - + input: + bytes: [ 0x00, 0x00, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za0h.d[w12, 0:1]" + + - + input: + bytes: [ 0x54, 0x40, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d, z21.d }, za2h.d[w14, 0:1]" + + - + input: + bytes: [ 0xb6, 0x60, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z22.d, z23.d }, za5h.d[w15, 0:1]" + + - + input: + bytes: [ 0xfe, 0x60, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z30.d, z31.d }, za7h.d[w15, 0:1]" + + - + input: + bytes: [ 0x24, 0x00, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d, z5.d }, za1h.d[w12, 0:1]" + + - + input: + bytes: [ 0x20, 0x00, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za1h.d[w12, 0:1]" + + - + input: + bytes: [ 0x78, 0x40, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.d, z25.d }, za3h.d[w14, 0:1]" + + - + input: + bytes: [ 0x80, 0x00, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za4h.d[w12, 0:1]" + + - + input: + bytes: [ 0x30, 0x40, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.d, z17.d }, za1h.d[w14, 0:1]" + + - + input: + bytes: [ 0xdc, 0x00, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d, z29.d }, za6h.d[w12, 0:1]" + + - + input: + bytes: [ 0x22, 0x60, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z2.d, z3.d }, za1h.d[w15, 0:1]" + + - + input: + bytes: [ 0x86, 0x20, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z6.d, z7.d }, za4h.d[w13, 0:1]" + + - + input: + bytes: [ 0x00, 0x00, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za0h.d[w12, 0:1]" + + - + input: + bytes: [ 0x54, 0x40, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d, z21.d }, za2h.d[w14, 0:1]" + + - + input: + bytes: [ 0xb6, 0x60, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z22.d, z23.d }, za5h.d[w15, 0:1]" + + - + input: + bytes: [ 0xfe, 0x60, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z30.d, z31.d }, za7h.d[w15, 0:1]" + + - + input: + bytes: [ 0x24, 0x00, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d, z5.d }, za1h.d[w12, 0:1]" + + - + input: + bytes: [ 0x20, 0x00, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za1h.d[w12, 0:1]" + + - + input: + bytes: [ 0x78, 0x40, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.d, z25.d }, za3h.d[w14, 0:1]" + + - + input: + bytes: [ 0x80, 0x00, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za4h.d[w12, 0:1]" + + - + input: + bytes: [ 0x30, 0x40, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.d, z17.d }, za1h.d[w14, 0:1]" + + - + input: + bytes: [ 0xdc, 0x00, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d, z29.d }, za6h.d[w12, 0:1]" + + - + input: + bytes: [ 0x22, 0x60, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z2.d, z3.d }, za1h.d[w15, 0:1]" + + - + input: + bytes: [ 0x86, 0x20, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z6.d, z7.d }, za4h.d[w13, 0:1]" + + - + input: + bytes: [ 0x00, 0x80, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za0v.d[w12, 0:1]" + + - + input: + bytes: [ 0x54, 0xc0, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d, z21.d }, za2v.d[w14, 0:1]" + + - + input: + bytes: [ 0xb6, 0xe0, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z22.d, z23.d }, za5v.d[w15, 0:1]" + + - + input: + bytes: [ 0xfe, 0xe0, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z30.d, z31.d }, za7v.d[w15, 0:1]" + + - + input: + bytes: [ 0x24, 0x80, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d, z5.d }, za1v.d[w12, 0:1]" + + - + input: + bytes: [ 0x20, 0x80, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za1v.d[w12, 0:1]" + + - + input: + bytes: [ 0x78, 0xc0, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.d, z25.d }, za3v.d[w14, 0:1]" + + - + input: + bytes: [ 0x80, 0x80, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za4v.d[w12, 0:1]" + + - + input: + bytes: [ 0x30, 0xc0, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.d, z17.d }, za1v.d[w14, 0:1]" + + - + input: + bytes: [ 0xdc, 0x80, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d, z29.d }, za6v.d[w12, 0:1]" + + - + input: + bytes: [ 0x22, 0xe0, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z2.d, z3.d }, za1v.d[w15, 0:1]" + + - + input: + bytes: [ 0x86, 0xa0, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z6.d, z7.d }, za4v.d[w13, 0:1]" + + - + input: + bytes: [ 0x00, 0x80, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za0v.d[w12, 0:1]" + + - + input: + bytes: [ 0x54, 0xc0, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d, z21.d }, za2v.d[w14, 0:1]" + + - + input: + bytes: [ 0xb6, 0xe0, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z22.d, z23.d }, za5v.d[w15, 0:1]" + + - + input: + bytes: [ 0xfe, 0xe0, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z30.d, z31.d }, za7v.d[w15, 0:1]" + + - + input: + bytes: [ 0x24, 0x80, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d, z5.d }, za1v.d[w12, 0:1]" + + - + input: + bytes: [ 0x20, 0x80, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za1v.d[w12, 0:1]" + + - + input: + bytes: [ 0x78, 0xc0, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.d, z25.d }, za3v.d[w14, 0:1]" + + - + input: + bytes: [ 0x80, 0x80, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za4v.d[w12, 0:1]" + + - + input: + bytes: [ 0x30, 0xc0, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.d, z17.d }, za1v.d[w14, 0:1]" + + - + input: + bytes: [ 0xdc, 0x80, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d, z29.d }, za6v.d[w12, 0:1]" + + - + input: + bytes: [ 0x22, 0xe0, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z2.d, z3.d }, za1v.d[w15, 0:1]" + + - + input: + bytes: [ 0x86, 0xa0, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z6.d, z7.d }, za4v.d[w13, 0:1]" + + - + input: + bytes: [ 0x00, 0x08, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za.d[w8, 0, vgx2]" + + - + input: + bytes: [ 0x00, 0x08, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za.d[w8, 0, vgx2]" + + - + input: + bytes: [ 0x54, 0x48, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d, z21.d }, za.d[w10, 2, vgx2]" + + - + input: + bytes: [ 0x54, 0x48, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d, z21.d }, za.d[w10, 2, vgx2]" + + - + input: + bytes: [ 0xb6, 0x68, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z22.d, z23.d }, za.d[w11, 5, vgx2]" + + - + input: + bytes: [ 0xb6, 0x68, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z22.d, z23.d }, za.d[w11, 5, vgx2]" + + - + input: + bytes: [ 0xfe, 0x68, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z30.d, z31.d }, za.d[w11, 7, vgx2]" + + - + input: + bytes: [ 0xfe, 0x68, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z30.d, z31.d }, za.d[w11, 7, vgx2]" + + - + input: + bytes: [ 0x24, 0x08, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d, z5.d }, za.d[w8, 1, vgx2]" + + - + input: + bytes: [ 0x24, 0x08, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d, z5.d }, za.d[w8, 1, vgx2]" + + - + input: + bytes: [ 0x20, 0x08, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za.d[w8, 1, vgx2]" + + - + input: + bytes: [ 0x20, 0x08, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za.d[w8, 1, vgx2]" + + - + input: + bytes: [ 0x78, 0x48, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.d, z25.d }, za.d[w10, 3, vgx2]" + + - + input: + bytes: [ 0x78, 0x48, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.d, z25.d }, za.d[w10, 3, vgx2]" + + - + input: + bytes: [ 0x80, 0x08, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za.d[w8, 4, vgx2]" + + - + input: + bytes: [ 0x80, 0x08, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za.d[w8, 4, vgx2]" + + - + input: + bytes: [ 0x30, 0x48, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.d, z17.d }, za.d[w10, 1, vgx2]" + + - + input: + bytes: [ 0x30, 0x48, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.d, z17.d }, za.d[w10, 1, vgx2]" + + - + input: + bytes: [ 0xdc, 0x08, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d, z29.d }, za.d[w8, 6, vgx2]" + + - + input: + bytes: [ 0xdc, 0x08, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d, z29.d }, za.d[w8, 6, vgx2]" + + - + input: + bytes: [ 0x22, 0x68, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z2.d, z3.d }, za.d[w11, 1, vgx2]" + + - + input: + bytes: [ 0x22, 0x68, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z2.d, z3.d }, za.d[w11, 1, vgx2]" + + - + input: + bytes: [ 0x86, 0x28, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z6.d, z7.d }, za.d[w9, 4, vgx2]" + + - + input: + bytes: [ 0x86, 0x28, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z6.d, z7.d }, za.d[w9, 4, vgx2]" + + - + input: + bytes: [ 0x00, 0x08, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za.d[w8, 0, vgx2]" + + - + input: + bytes: [ 0x54, 0x48, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d, z21.d }, za.d[w10, 2, vgx2]" + + - + input: + bytes: [ 0xb6, 0x68, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z22.d, z23.d }, za.d[w11, 5, vgx2]" + + - + input: + bytes: [ 0xfe, 0x68, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z30.d, z31.d }, za.d[w11, 7, vgx2]" + + - + input: + bytes: [ 0x24, 0x08, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d, z5.d }, za.d[w8, 1, vgx2]" + + - + input: + bytes: [ 0x20, 0x08, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za.d[w8, 1, vgx2]" + + - + input: + bytes: [ 0x78, 0x48, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.d, z25.d }, za.d[w10, 3, vgx2]" + + - + input: + bytes: [ 0x80, 0x08, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d, z1.d }, za.d[w8, 4, vgx2]" + + - + input: + bytes: [ 0x30, 0x48, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.d, z17.d }, za.d[w10, 1, vgx2]" + + - + input: + bytes: [ 0xdc, 0x08, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d, z29.d }, za.d[w8, 6, vgx2]" + + - + input: + bytes: [ 0x22, 0x68, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z2.d, z3.d }, za.d[w11, 1, vgx2]" + + - + input: + bytes: [ 0x86, 0x28, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z6.d, z7.d }, za.d[w9, 4, vgx2]" + + - + input: + bytes: [ 0x00, 0x00, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.d[w12, 0:1], { z0.d, z1.d }" + + - + input: + bytes: [ 0x45, 0x41, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5h.d[w14, 0:1], { z10.d, z11.d }" + + - + input: + bytes: [ 0x87, 0x61, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7h.d[w15, 0:1], { z12.d, z13.d }" + + - + input: + bytes: [ 0xc7, 0x63, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7h.d[w15, 0:1], { z30.d, z31.d }" + + - + input: + bytes: [ 0x05, 0x02, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5h.d[w12, 0:1], { z16.d, z17.d }" + + - + input: + bytes: [ 0x01, 0x00, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.d[w12, 0:1], { z0.d, z1.d }" + + - + input: + bytes: [ 0x40, 0x42, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.d[w14, 0:1], { z18.d, z19.d }" + + - + input: + bytes: [ 0x80, 0x01, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.d[w12, 0:1], { z12.d, z13.d }" + + - + input: + bytes: [ 0x01, 0x40, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.d[w14, 0:1], { z0.d, z1.d }" + + - + input: + bytes: [ 0xc5, 0x02, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5h.d[w12, 0:1], { z22.d, z23.d }" + + - + input: + bytes: [ 0x02, 0x61, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2h.d[w15, 0:1], { z8.d, z9.d }" + + - + input: + bytes: [ 0x87, 0x21, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7h.d[w13, 0:1], { z12.d, z13.d }" + + - + input: + bytes: [ 0x00, 0x00, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.d[w12, 0:1], { z0.d, z1.d }" + + - + input: + bytes: [ 0x45, 0x41, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5h.d[w14, 0:1], { z10.d, z11.d }" + + - + input: + bytes: [ 0x87, 0x61, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7h.d[w15, 0:1], { z12.d, z13.d }" + + - + input: + bytes: [ 0xc7, 0x63, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7h.d[w15, 0:1], { z30.d, z31.d }" + + - + input: + bytes: [ 0x05, 0x02, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5h.d[w12, 0:1], { z16.d, z17.d }" + + - + input: + bytes: [ 0x01, 0x00, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.d[w12, 0:1], { z0.d, z1.d }" + + - + input: + bytes: [ 0x40, 0x42, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.d[w14, 0:1], { z18.d, z19.d }" + + - + input: + bytes: [ 0x80, 0x01, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.d[w12, 0:1], { z12.d, z13.d }" + + - + input: + bytes: [ 0x01, 0x40, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.d[w14, 0:1], { z0.d, z1.d }" + + - + input: + bytes: [ 0xc5, 0x02, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5h.d[w12, 0:1], { z22.d, z23.d }" + + - + input: + bytes: [ 0x02, 0x61, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2h.d[w15, 0:1], { z8.d, z9.d }" + + - + input: + bytes: [ 0x87, 0x21, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7h.d[w13, 0:1], { z12.d, z13.d }" + + - + input: + bytes: [ 0x00, 0x80, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.d[w12, 0:1], { z0.d, z1.d }" + + - + input: + bytes: [ 0x45, 0xc1, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5v.d[w14, 0:1], { z10.d, z11.d }" + + - + input: + bytes: [ 0x87, 0xe1, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7v.d[w15, 0:1], { z12.d, z13.d }" + + - + input: + bytes: [ 0xc7, 0xe3, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7v.d[w15, 0:1], { z30.d, z31.d }" + + - + input: + bytes: [ 0x05, 0x82, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5v.d[w12, 0:1], { z16.d, z17.d }" + + - + input: + bytes: [ 0x01, 0x80, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.d[w12, 0:1], { z0.d, z1.d }" + + - + input: + bytes: [ 0x40, 0xc2, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.d[w14, 0:1], { z18.d, z19.d }" + + - + input: + bytes: [ 0x80, 0x81, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.d[w12, 0:1], { z12.d, z13.d }" + + - + input: + bytes: [ 0x01, 0xc0, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.d[w14, 0:1], { z0.d, z1.d }" + + - + input: + bytes: [ 0xc5, 0x82, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5v.d[w12, 0:1], { z22.d, z23.d }" + + - + input: + bytes: [ 0x02, 0xe1, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2v.d[w15, 0:1], { z8.d, z9.d }" + + - + input: + bytes: [ 0x87, 0xa1, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7v.d[w13, 0:1], { z12.d, z13.d }" + + - + input: + bytes: [ 0x00, 0x80, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.d[w12, 0:1], { z0.d, z1.d }" + + - + input: + bytes: [ 0x45, 0xc1, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5v.d[w14, 0:1], { z10.d, z11.d }" + + - + input: + bytes: [ 0x87, 0xe1, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7v.d[w15, 0:1], { z12.d, z13.d }" + + - + input: + bytes: [ 0xc7, 0xe3, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7v.d[w15, 0:1], { z30.d, z31.d }" + + - + input: + bytes: [ 0x05, 0x82, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5v.d[w12, 0:1], { z16.d, z17.d }" + + - + input: + bytes: [ 0x01, 0x80, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.d[w12, 0:1], { z0.d, z1.d }" + + - + input: + bytes: [ 0x40, 0xc2, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.d[w14, 0:1], { z18.d, z19.d }" + + - + input: + bytes: [ 0x80, 0x81, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.d[w12, 0:1], { z12.d, z13.d }" + + - + input: + bytes: [ 0x01, 0xc0, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.d[w14, 0:1], { z0.d, z1.d }" + + - + input: + bytes: [ 0xc5, 0x82, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5v.d[w12, 0:1], { z22.d, z23.d }" + + - + input: + bytes: [ 0x02, 0xe1, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2v.d[w15, 0:1], { z8.d, z9.d }" + + - + input: + bytes: [ 0x87, 0xa1, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7v.d[w13, 0:1], { z12.d, z13.d }" + + - + input: + bytes: [ 0x00, 0x08, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 0, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x00, 0x08, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 0, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x45, 0x49, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w10, 5, vgx2], { z10.d, z11.d }" + + - + input: + bytes: [ 0x45, 0x49, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w10, 5, vgx2], { z10.d, z11.d }" + + - + input: + bytes: [ 0x87, 0x69, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w11, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x87, 0x69, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w11, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0xc7, 0x6b, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w11, 7, vgx2], { z30.d, z31.d }" + + - + input: + bytes: [ 0xc7, 0x6b, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w11, 7, vgx2], { z30.d, z31.d }" + + - + input: + bytes: [ 0x05, 0x0a, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 5, vgx2], { z16.d, z17.d }" + + - + input: + bytes: [ 0x05, 0x0a, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 5, vgx2], { z16.d, z17.d }" + + - + input: + bytes: [ 0x01, 0x08, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x01, 0x08, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x40, 0x4a, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w10, 0, vgx2], { z18.d, z19.d }" + + - + input: + bytes: [ 0x40, 0x4a, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w10, 0, vgx2], { z18.d, z19.d }" + + - + input: + bytes: [ 0x80, 0x09, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 0, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x80, 0x09, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 0, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x01, 0x48, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w10, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x01, 0x48, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w10, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0xc5, 0x0a, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 5, vgx2], { z22.d, z23.d }" + + - + input: + bytes: [ 0xc5, 0x0a, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 5, vgx2], { z22.d, z23.d }" + + - + input: + bytes: [ 0x02, 0x69, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w11, 2, vgx2], { z8.d, z9.d }" + + - + input: + bytes: [ 0x02, 0x69, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w11, 2, vgx2], { z8.d, z9.d }" + + - + input: + bytes: [ 0x87, 0x29, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w9, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x87, 0x29, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w9, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x00, 0x08, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 0, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x45, 0x49, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w10, 5, vgx2], { z10.d, z11.d }" + + - + input: + bytes: [ 0x87, 0x69, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w11, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0xc7, 0x6b, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w11, 7, vgx2], { z30.d, z31.d }" + + - + input: + bytes: [ 0x05, 0x0a, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 5, vgx2], { z16.d, z17.d }" + + - + input: + bytes: [ 0x01, 0x08, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x40, 0x4a, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w10, 0, vgx2], { z18.d, z19.d }" + + - + input: + bytes: [ 0x80, 0x09, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 0, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x01, 0x48, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w10, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0xc5, 0x0a, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 5, vgx2], { z22.d, z23.d }" + + - + input: + bytes: [ 0x02, 0x69, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w11, 2, vgx2], { z8.d, z9.d }" + + - + input: + bytes: [ 0x87, 0x29, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w9, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x00, 0x00, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b, z1.b }, za0h.b[w12, 0:1]" + + - + input: + bytes: [ 0x54, 0x40, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.b, z21.b }, za0h.b[w14, 4:5]" + + - + input: + bytes: [ 0xb6, 0x60, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z22.b, z23.b }, za0h.b[w15, 10:11]" + + - + input: + bytes: [ 0xfe, 0x60, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z30.b, z31.b }, za0h.b[w15, 14:15]" + + - + input: + bytes: [ 0x24, 0x00, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.b, z5.b }, za0h.b[w12, 2:3]" + + - + input: + bytes: [ 0x20, 0x00, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b, z1.b }, za0h.b[w12, 2:3]" + + - + input: + bytes: [ 0x78, 0x40, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.b, z25.b }, za0h.b[w14, 6:7]" + + - + input: + bytes: [ 0x80, 0x00, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b, z1.b }, za0h.b[w12, 8:9]" + + - + input: + bytes: [ 0x30, 0x40, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.b, z17.b }, za0h.b[w14, 2:3]" + + - + input: + bytes: [ 0xdc, 0x00, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.b, z29.b }, za0h.b[w12, 12:13]" + + - + input: + bytes: [ 0x22, 0x60, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z2.b, z3.b }, za0h.b[w15, 2:3]" + + - + input: + bytes: [ 0x86, 0x20, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z6.b, z7.b }, za0h.b[w13, 8:9]" + + - + input: + bytes: [ 0x00, 0x00, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b, z1.b }, za0h.b[w12, 0:1]" + + - + input: + bytes: [ 0x54, 0x40, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.b, z21.b }, za0h.b[w14, 4:5]" + + - + input: + bytes: [ 0xb6, 0x60, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z22.b, z23.b }, za0h.b[w15, 10:11]" + + - + input: + bytes: [ 0xfe, 0x60, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z30.b, z31.b }, za0h.b[w15, 14:15]" + + - + input: + bytes: [ 0x24, 0x00, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.b, z5.b }, za0h.b[w12, 2:3]" + + - + input: + bytes: [ 0x20, 0x00, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b, z1.b }, za0h.b[w12, 2:3]" + + - + input: + bytes: [ 0x78, 0x40, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.b, z25.b }, za0h.b[w14, 6:7]" + + - + input: + bytes: [ 0x80, 0x00, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b, z1.b }, za0h.b[w12, 8:9]" + + - + input: + bytes: [ 0x30, 0x40, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.b, z17.b }, za0h.b[w14, 2:3]" + + - + input: + bytes: [ 0xdc, 0x00, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.b, z29.b }, za0h.b[w12, 12:13]" + + - + input: + bytes: [ 0x22, 0x60, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z2.b, z3.b }, za0h.b[w15, 2:3]" + + - + input: + bytes: [ 0x86, 0x20, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z6.b, z7.b }, za0h.b[w13, 8:9]" + + - + input: + bytes: [ 0x00, 0x80, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b, z1.b }, za0v.b[w12, 0:1]" + + - + input: + bytes: [ 0x54, 0xc0, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.b, z21.b }, za0v.b[w14, 4:5]" + + - + input: + bytes: [ 0xb6, 0xe0, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z22.b, z23.b }, za0v.b[w15, 10:11]" + + - + input: + bytes: [ 0xfe, 0xe0, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z30.b, z31.b }, za0v.b[w15, 14:15]" + + - + input: + bytes: [ 0x24, 0x80, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.b, z5.b }, za0v.b[w12, 2:3]" + + - + input: + bytes: [ 0x20, 0x80, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b, z1.b }, za0v.b[w12, 2:3]" + + - + input: + bytes: [ 0x78, 0xc0, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.b, z25.b }, za0v.b[w14, 6:7]" + + - + input: + bytes: [ 0x80, 0x80, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b, z1.b }, za0v.b[w12, 8:9]" + + - + input: + bytes: [ 0x30, 0xc0, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.b, z17.b }, za0v.b[w14, 2:3]" + + - + input: + bytes: [ 0xdc, 0x80, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.b, z29.b }, za0v.b[w12, 12:13]" + + - + input: + bytes: [ 0x22, 0xe0, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z2.b, z3.b }, za0v.b[w15, 2:3]" + + - + input: + bytes: [ 0x86, 0xa0, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z6.b, z7.b }, za0v.b[w13, 8:9]" + + - + input: + bytes: [ 0x00, 0x80, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b, z1.b }, za0v.b[w12, 0:1]" + + - + input: + bytes: [ 0x54, 0xc0, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.b, z21.b }, za0v.b[w14, 4:5]" + + - + input: + bytes: [ 0xb6, 0xe0, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z22.b, z23.b }, za0v.b[w15, 10:11]" + + - + input: + bytes: [ 0xfe, 0xe0, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z30.b, z31.b }, za0v.b[w15, 14:15]" + + - + input: + bytes: [ 0x24, 0x80, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.b, z5.b }, za0v.b[w12, 2:3]" + + - + input: + bytes: [ 0x20, 0x80, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b, z1.b }, za0v.b[w12, 2:3]" + + - + input: + bytes: [ 0x78, 0xc0, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.b, z25.b }, za0v.b[w14, 6:7]" + + - + input: + bytes: [ 0x80, 0x80, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b, z1.b }, za0v.b[w12, 8:9]" + + - + input: + bytes: [ 0x30, 0xc0, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.b, z17.b }, za0v.b[w14, 2:3]" + + - + input: + bytes: [ 0xdc, 0x80, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.b, z29.b }, za0v.b[w12, 12:13]" + + - + input: + bytes: [ 0x22, 0xe0, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z2.b, z3.b }, za0v.b[w15, 2:3]" + + - + input: + bytes: [ 0x86, 0xa0, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z6.b, z7.b }, za0v.b[w13, 8:9]" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 0:1], { z0.b, z1.b }" + + - + input: + bytes: [ 0x45, 0x41, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w14, 10:11], { z10.b, z11.b }" + + - + input: + bytes: [ 0x87, 0x61, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w15, 14:15], { z12.b, z13.b }" + + - + input: + bytes: [ 0xc7, 0x63, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w15, 14:15], { z30.b, z31.b }" + + - + input: + bytes: [ 0x05, 0x02, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 10:11], { z16.b, z17.b }" + + - + input: + bytes: [ 0x01, 0x00, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 2:3], { z0.b, z1.b }" + + - + input: + bytes: [ 0x40, 0x42, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w14, 0:1], { z18.b, z19.b }" + + - + input: + bytes: [ 0x80, 0x01, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 0:1], { z12.b, z13.b }" + + - + input: + bytes: [ 0x01, 0x40, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w14, 2:3], { z0.b, z1.b }" + + - + input: + bytes: [ 0xc5, 0x02, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 10:11], { z22.b, z23.b }" + + - + input: + bytes: [ 0x02, 0x61, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w15, 4:5], { z8.b, z9.b }" + + - + input: + bytes: [ 0x87, 0x21, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w13, 14:15], { z12.b, z13.b }" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 0:1], { z0.b, z1.b }" + + - + input: + bytes: [ 0x45, 0x41, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w14, 10:11], { z10.b, z11.b }" + + - + input: + bytes: [ 0x87, 0x61, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w15, 14:15], { z12.b, z13.b }" + + - + input: + bytes: [ 0xc7, 0x63, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w15, 14:15], { z30.b, z31.b }" + + - + input: + bytes: [ 0x05, 0x02, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 10:11], { z16.b, z17.b }" + + - + input: + bytes: [ 0x01, 0x00, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 2:3], { z0.b, z1.b }" + + - + input: + bytes: [ 0x40, 0x42, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w14, 0:1], { z18.b, z19.b }" + + - + input: + bytes: [ 0x80, 0x01, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 0:1], { z12.b, z13.b }" + + - + input: + bytes: [ 0x01, 0x40, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w14, 2:3], { z0.b, z1.b }" + + - + input: + bytes: [ 0xc5, 0x02, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 10:11], { z22.b, z23.b }" + + - + input: + bytes: [ 0x02, 0x61, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w15, 4:5], { z8.b, z9.b }" + + - + input: + bytes: [ 0x87, 0x21, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w13, 14:15], { z12.b, z13.b }" + + - + input: + bytes: [ 0x00, 0x80, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 0:1], { z0.b, z1.b }" + + - + input: + bytes: [ 0x45, 0xc1, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w14, 10:11], { z10.b, z11.b }" + + - + input: + bytes: [ 0x87, 0xe1, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w15, 14:15], { z12.b, z13.b }" + + - + input: + bytes: [ 0xc7, 0xe3, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w15, 14:15], { z30.b, z31.b }" + + - + input: + bytes: [ 0x05, 0x82, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 10:11], { z16.b, z17.b }" + + - + input: + bytes: [ 0x01, 0x80, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 2:3], { z0.b, z1.b }" + + - + input: + bytes: [ 0x40, 0xc2, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w14, 0:1], { z18.b, z19.b }" + + - + input: + bytes: [ 0x80, 0x81, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 0:1], { z12.b, z13.b }" + + - + input: + bytes: [ 0x01, 0xc0, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w14, 2:3], { z0.b, z1.b }" + + - + input: + bytes: [ 0xc5, 0x82, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 10:11], { z22.b, z23.b }" + + - + input: + bytes: [ 0x02, 0xe1, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w15, 4:5], { z8.b, z9.b }" + + - + input: + bytes: [ 0x87, 0xa1, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w13, 14:15], { z12.b, z13.b }" + + - + input: + bytes: [ 0x00, 0x80, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 0:1], { z0.b, z1.b }" + + - + input: + bytes: [ 0x45, 0xc1, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w14, 10:11], { z10.b, z11.b }" + + - + input: + bytes: [ 0x87, 0xe1, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w15, 14:15], { z12.b, z13.b }" + + - + input: + bytes: [ 0xc7, 0xe3, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w15, 14:15], { z30.b, z31.b }" + + - + input: + bytes: [ 0x05, 0x82, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 10:11], { z16.b, z17.b }" + + - + input: + bytes: [ 0x01, 0x80, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 2:3], { z0.b, z1.b }" + + - + input: + bytes: [ 0x40, 0xc2, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w14, 0:1], { z18.b, z19.b }" + + - + input: + bytes: [ 0x80, 0x81, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 0:1], { z12.b, z13.b }" + + - + input: + bytes: [ 0x01, 0xc0, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w14, 2:3], { z0.b, z1.b }" + + - + input: + bytes: [ 0xc5, 0x82, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 10:11], { z22.b, z23.b }" + + - + input: + bytes: [ 0x02, 0xe1, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w15, 4:5], { z8.b, z9.b }" + + - + input: + bytes: [ 0x87, 0xa1, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w13, 14:15], { z12.b, z13.b }" + + - + input: + bytes: [ 0x00, 0x04, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h - z3.h }, za0h.h[w12, 0:3]" + + - + input: + bytes: [ 0x54, 0x44, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.h - z23.h }, za1h.h[w14, 0:3]" + + - + input: + bytes: [ 0x34, 0x64, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.h - z23.h }, za0h.h[w15, 4:7]" + + - + input: + bytes: [ 0x7c, 0x64, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.h - z31.h }, za1h.h[w15, 4:7]" + + - + input: + bytes: [ 0x24, 0x04, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.h - z7.h }, za0h.h[w12, 4:7]" + + - + input: + bytes: [ 0x20, 0x04, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h - z3.h }, za0h.h[w12, 4:7]" + + - + input: + bytes: [ 0x78, 0x44, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.h - z27.h }, za1h.h[w14, 4:7]" + + - + input: + bytes: [ 0x30, 0x44, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.h - z19.h }, za0h.h[w14, 4:7]" + + - + input: + bytes: [ 0x5c, 0x04, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.h - z31.h }, za1h.h[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0x64, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h - z3.h }, za0h.h[w15, 4:7]" + + - + input: + bytes: [ 0x04, 0x24, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.h - z7.h }, za0h.h[w13, 0:3]" + + - + input: + bytes: [ 0x00, 0x04, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h - z3.h }, za0h.h[w12, 0:3]" + + - + input: + bytes: [ 0x54, 0x44, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.h - z23.h }, za1h.h[w14, 0:3]" + + - + input: + bytes: [ 0x34, 0x64, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.h - z23.h }, za0h.h[w15, 4:7]" + + - + input: + bytes: [ 0x7c, 0x64, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.h - z31.h }, za1h.h[w15, 4:7]" + + - + input: + bytes: [ 0x24, 0x04, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.h - z7.h }, za0h.h[w12, 4:7]" + + - + input: + bytes: [ 0x20, 0x04, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h - z3.h }, za0h.h[w12, 4:7]" + + - + input: + bytes: [ 0x78, 0x44, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.h - z27.h }, za1h.h[w14, 4:7]" + + - + input: + bytes: [ 0x30, 0x44, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.h - z19.h }, za0h.h[w14, 4:7]" + + - + input: + bytes: [ 0x5c, 0x04, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.h - z31.h }, za1h.h[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0x64, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h - z3.h }, za0h.h[w15, 4:7]" + + - + input: + bytes: [ 0x04, 0x24, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.h - z7.h }, za0h.h[w13, 0:3]" + + - + input: + bytes: [ 0x00, 0x84, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h - z3.h }, za0v.h[w12, 0:3]" + + - + input: + bytes: [ 0x54, 0xc4, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.h - z23.h }, za1v.h[w14, 0:3]" + + - + input: + bytes: [ 0x34, 0xe4, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.h - z23.h }, za0v.h[w15, 4:7]" + + - + input: + bytes: [ 0x7c, 0xe4, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.h - z31.h }, za1v.h[w15, 4:7]" + + - + input: + bytes: [ 0x24, 0x84, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.h - z7.h }, za0v.h[w12, 4:7]" + + - + input: + bytes: [ 0x20, 0x84, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h - z3.h }, za0v.h[w12, 4:7]" + + - + input: + bytes: [ 0x78, 0xc4, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.h - z27.h }, za1v.h[w14, 4:7]" + + - + input: + bytes: [ 0x30, 0xc4, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.h - z19.h }, za0v.h[w14, 4:7]" + + - + input: + bytes: [ 0x5c, 0x84, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.h - z31.h }, za1v.h[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0xe4, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h - z3.h }, za0v.h[w15, 4:7]" + + - + input: + bytes: [ 0x04, 0xa4, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.h - z7.h }, za0v.h[w13, 0:3]" + + - + input: + bytes: [ 0x00, 0x84, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h - z3.h }, za0v.h[w12, 0:3]" + + - + input: + bytes: [ 0x54, 0xc4, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.h - z23.h }, za1v.h[w14, 0:3]" + + - + input: + bytes: [ 0x34, 0xe4, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.h - z23.h }, za0v.h[w15, 4:7]" + + - + input: + bytes: [ 0x7c, 0xe4, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.h - z31.h }, za1v.h[w15, 4:7]" + + - + input: + bytes: [ 0x24, 0x84, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.h - z7.h }, za0v.h[w12, 4:7]" + + - + input: + bytes: [ 0x20, 0x84, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h - z3.h }, za0v.h[w12, 4:7]" + + - + input: + bytes: [ 0x78, 0xc4, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.h - z27.h }, za1v.h[w14, 4:7]" + + - + input: + bytes: [ 0x30, 0xc4, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.h - z19.h }, za0v.h[w14, 4:7]" + + - + input: + bytes: [ 0x5c, 0x84, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.h - z31.h }, za1v.h[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0xe4, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.h - z3.h }, za0v.h[w15, 4:7]" + + - + input: + bytes: [ 0x04, 0xa4, 0x46, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.h - z7.h }, za0v.h[w13, 0:3]" + + - + input: + bytes: [ 0x00, 0x04, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 0:3], { z0.h - z3.h }" + + - + input: + bytes: [ 0x01, 0x45, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w14, 4:7], { z8.h - z11.h }" + + - + input: + bytes: [ 0x83, 0x65, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w15, 4:7], { z12.h - z15.h }" + + - + input: + bytes: [ 0x83, 0x67, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w15, 4:7], { z28.h - z31.h }" + + - + input: + bytes: [ 0x01, 0x06, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 4:7], { z16.h - z19.h }" + + - + input: + bytes: [ 0x01, 0x04, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 4:7], { z0.h - z3.h }" + + - + input: + bytes: [ 0x00, 0x46, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w14, 0:3], { z16.h - z19.h }" + + - + input: + bytes: [ 0x80, 0x05, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 0:3], { z12.h - z15.h }" + + - + input: + bytes: [ 0x01, 0x44, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w14, 4:7], { z0.h - z3.h }" + + - + input: + bytes: [ 0x81, 0x06, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 4:7], { z20.h - z23.h }" + + - + input: + bytes: [ 0x02, 0x65, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w15, 0:3], { z8.h - z11.h }" + + - + input: + bytes: [ 0x83, 0x25, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w13, 4:7], { z12.h - z15.h }" + + - + input: + bytes: [ 0x00, 0x04, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 0:3], { z0.h - z3.h }" + + - + input: + bytes: [ 0x01, 0x45, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w14, 4:7], { z8.h - z11.h }" + + - + input: + bytes: [ 0x83, 0x65, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w15, 4:7], { z12.h - z15.h }" + + - + input: + bytes: [ 0x83, 0x67, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w15, 4:7], { z28.h - z31.h }" + + - + input: + bytes: [ 0x01, 0x06, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 4:7], { z16.h - z19.h }" + + - + input: + bytes: [ 0x01, 0x04, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 4:7], { z0.h - z3.h }" + + - + input: + bytes: [ 0x00, 0x46, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w14, 0:3], { z16.h - z19.h }" + + - + input: + bytes: [ 0x80, 0x05, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 0:3], { z12.h - z15.h }" + + - + input: + bytes: [ 0x01, 0x44, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w14, 4:7], { z0.h - z3.h }" + + - + input: + bytes: [ 0x81, 0x06, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.h[w12, 4:7], { z20.h - z23.h }" + + - + input: + bytes: [ 0x02, 0x65, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w15, 0:3], { z8.h - z11.h }" + + - + input: + bytes: [ 0x83, 0x25, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.h[w13, 4:7], { z12.h - z15.h }" + + - + input: + bytes: [ 0x00, 0x84, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 0:3], { z0.h - z3.h }" + + - + input: + bytes: [ 0x01, 0xc5, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w14, 4:7], { z8.h - z11.h }" + + - + input: + bytes: [ 0x83, 0xe5, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w15, 4:7], { z12.h - z15.h }" + + - + input: + bytes: [ 0x83, 0xe7, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w15, 4:7], { z28.h - z31.h }" + + - + input: + bytes: [ 0x01, 0x86, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 4:7], { z16.h - z19.h }" + + - + input: + bytes: [ 0x01, 0x84, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 4:7], { z0.h - z3.h }" + + - + input: + bytes: [ 0x00, 0xc6, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w14, 0:3], { z16.h - z19.h }" + + - + input: + bytes: [ 0x80, 0x85, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 0:3], { z12.h - z15.h }" + + - + input: + bytes: [ 0x01, 0xc4, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w14, 4:7], { z0.h - z3.h }" + + - + input: + bytes: [ 0x81, 0x86, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 4:7], { z20.h - z23.h }" + + - + input: + bytes: [ 0x02, 0xe5, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w15, 0:3], { z8.h - z11.h }" + + - + input: + bytes: [ 0x83, 0xa5, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w13, 4:7], { z12.h - z15.h }" + + - + input: + bytes: [ 0x00, 0x84, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 0:3], { z0.h - z3.h }" + + - + input: + bytes: [ 0x01, 0xc5, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w14, 4:7], { z8.h - z11.h }" + + - + input: + bytes: [ 0x83, 0xe5, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w15, 4:7], { z12.h - z15.h }" + + - + input: + bytes: [ 0x83, 0xe7, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w15, 4:7], { z28.h - z31.h }" + + - + input: + bytes: [ 0x01, 0x86, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 4:7], { z16.h - z19.h }" + + - + input: + bytes: [ 0x01, 0x84, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 4:7], { z0.h - z3.h }" + + - + input: + bytes: [ 0x00, 0xc6, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w14, 0:3], { z16.h - z19.h }" + + - + input: + bytes: [ 0x80, 0x85, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 0:3], { z12.h - z15.h }" + + - + input: + bytes: [ 0x01, 0xc4, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w14, 4:7], { z0.h - z3.h }" + + - + input: + bytes: [ 0x81, 0x86, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.h[w12, 4:7], { z20.h - z23.h }" + + - + input: + bytes: [ 0x02, 0xe5, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w15, 0:3], { z8.h - z11.h }" + + - + input: + bytes: [ 0x83, 0xa5, 0x44, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.h[w13, 4:7], { z12.h - z15.h }" + + - + input: + bytes: [ 0x00, 0x04, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s - z3.s }, za0h.s[w12, 0:3]" + + - + input: + bytes: [ 0x54, 0x44, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.s - z23.s }, za2h.s[w14, 0:3]" + + - + input: + bytes: [ 0x34, 0x64, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.s - z23.s }, za1h.s[w15, 0:3]" + + - + input: + bytes: [ 0x7c, 0x64, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.s - z31.s }, za3h.s[w15, 0:3]" + + - + input: + bytes: [ 0x24, 0x04, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.s - z7.s }, za1h.s[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0x04, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s - z3.s }, za1h.s[w12, 0:3]" + + - + input: + bytes: [ 0x78, 0x44, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.s - z27.s }, za3h.s[w14, 0:3]" + + - + input: + bytes: [ 0x30, 0x44, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.s - z19.s }, za1h.s[w14, 0:3]" + + - + input: + bytes: [ 0x5c, 0x04, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.s - z31.s }, za2h.s[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0x64, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s - z3.s }, za1h.s[w15, 0:3]" + + - + input: + bytes: [ 0x04, 0x24, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.s - z7.s }, za0h.s[w13, 0:3]" + + - + input: + bytes: [ 0x00, 0x04, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s - z3.s }, za0h.s[w12, 0:3]" + + - + input: + bytes: [ 0x54, 0x44, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.s - z23.s }, za2h.s[w14, 0:3]" + + - + input: + bytes: [ 0x34, 0x64, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.s - z23.s }, za1h.s[w15, 0:3]" + + - + input: + bytes: [ 0x7c, 0x64, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.s - z31.s }, za3h.s[w15, 0:3]" + + - + input: + bytes: [ 0x24, 0x04, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.s - z7.s }, za1h.s[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0x04, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s - z3.s }, za1h.s[w12, 0:3]" + + - + input: + bytes: [ 0x78, 0x44, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.s - z27.s }, za3h.s[w14, 0:3]" + + - + input: + bytes: [ 0x30, 0x44, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.s - z19.s }, za1h.s[w14, 0:3]" + + - + input: + bytes: [ 0x5c, 0x04, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.s - z31.s }, za2h.s[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0x64, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s - z3.s }, za1h.s[w15, 0:3]" + + - + input: + bytes: [ 0x04, 0x24, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.s - z7.s }, za0h.s[w13, 0:3]" + + - + input: + bytes: [ 0x00, 0x84, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s - z3.s }, za0v.s[w12, 0:3]" + + - + input: + bytes: [ 0x54, 0xc4, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.s - z23.s }, za2v.s[w14, 0:3]" + + - + input: + bytes: [ 0x34, 0xe4, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.s - z23.s }, za1v.s[w15, 0:3]" + + - + input: + bytes: [ 0x7c, 0xe4, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.s - z31.s }, za3v.s[w15, 0:3]" + + - + input: + bytes: [ 0x24, 0x84, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.s - z7.s }, za1v.s[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0x84, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s - z3.s }, za1v.s[w12, 0:3]" + + - + input: + bytes: [ 0x78, 0xc4, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.s - z27.s }, za3v.s[w14, 0:3]" + + - + input: + bytes: [ 0x30, 0xc4, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.s - z19.s }, za1v.s[w14, 0:3]" + + - + input: + bytes: [ 0x5c, 0x84, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.s - z31.s }, za2v.s[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0xe4, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s - z3.s }, za1v.s[w15, 0:3]" + + - + input: + bytes: [ 0x04, 0xa4, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.s - z7.s }, za0v.s[w13, 0:3]" + + - + input: + bytes: [ 0x00, 0x84, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s - z3.s }, za0v.s[w12, 0:3]" + + - + input: + bytes: [ 0x54, 0xc4, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.s - z23.s }, za2v.s[w14, 0:3]" + + - + input: + bytes: [ 0x34, 0xe4, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.s - z23.s }, za1v.s[w15, 0:3]" + + - + input: + bytes: [ 0x7c, 0xe4, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.s - z31.s }, za3v.s[w15, 0:3]" + + - + input: + bytes: [ 0x24, 0x84, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.s - z7.s }, za1v.s[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0x84, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s - z3.s }, za1v.s[w12, 0:3]" + + - + input: + bytes: [ 0x78, 0xc4, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.s - z27.s }, za3v.s[w14, 0:3]" + + - + input: + bytes: [ 0x30, 0xc4, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.s - z19.s }, za1v.s[w14, 0:3]" + + - + input: + bytes: [ 0x5c, 0x84, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.s - z31.s }, za2v.s[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0xe4, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.s - z3.s }, za1v.s[w15, 0:3]" + + - + input: + bytes: [ 0x04, 0xa4, 0x86, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.s - z7.s }, za0v.s[w13, 0:3]" + + - + input: + bytes: [ 0x00, 0x04, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.s[w12, 0:3], { z0.s - z3.s }" + + - + input: + bytes: [ 0x01, 0x45, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.s[w14, 0:3], { z8.s - z11.s }" + + - + input: + bytes: [ 0x83, 0x65, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3h.s[w15, 0:3], { z12.s - z15.s }" + + - + input: + bytes: [ 0x83, 0x67, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3h.s[w15, 0:3], { z28.s - z31.s }" + + - + input: + bytes: [ 0x01, 0x06, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.s[w12, 0:3], { z16.s - z19.s }" + + - + input: + bytes: [ 0x01, 0x04, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.s[w12, 0:3], { z0.s - z3.s }" + + - + input: + bytes: [ 0x00, 0x46, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.s[w14, 0:3], { z16.s - z19.s }" + + - + input: + bytes: [ 0x80, 0x05, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.s[w12, 0:3], { z12.s - z15.s }" + + - + input: + bytes: [ 0x01, 0x44, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.s[w14, 0:3], { z0.s - z3.s }" + + - + input: + bytes: [ 0x81, 0x06, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.s[w12, 0:3], { z20.s - z23.s }" + + - + input: + bytes: [ 0x02, 0x65, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2h.s[w15, 0:3], { z8.s - z11.s }" + + - + input: + bytes: [ 0x83, 0x25, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3h.s[w13, 0:3], { z12.s - z15.s }" + + - + input: + bytes: [ 0x00, 0x04, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.s[w12, 0:3], { z0.s - z3.s }" + + - + input: + bytes: [ 0x01, 0x45, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.s[w14, 0:3], { z8.s - z11.s }" + + - + input: + bytes: [ 0x83, 0x65, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3h.s[w15, 0:3], { z12.s - z15.s }" + + - + input: + bytes: [ 0x83, 0x67, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3h.s[w15, 0:3], { z28.s - z31.s }" + + - + input: + bytes: [ 0x01, 0x06, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.s[w12, 0:3], { z16.s - z19.s }" + + - + input: + bytes: [ 0x01, 0x04, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.s[w12, 0:3], { z0.s - z3.s }" + + - + input: + bytes: [ 0x00, 0x46, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.s[w14, 0:3], { z16.s - z19.s }" + + - + input: + bytes: [ 0x80, 0x05, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.s[w12, 0:3], { z12.s - z15.s }" + + - + input: + bytes: [ 0x01, 0x44, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.s[w14, 0:3], { z0.s - z3.s }" + + - + input: + bytes: [ 0x81, 0x06, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.s[w12, 0:3], { z20.s - z23.s }" + + - + input: + bytes: [ 0x02, 0x65, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2h.s[w15, 0:3], { z8.s - z11.s }" + + - + input: + bytes: [ 0x83, 0x25, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3h.s[w13, 0:3], { z12.s - z15.s }" + + - + input: + bytes: [ 0x00, 0x84, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.s[w12, 0:3], { z0.s - z3.s }" + + - + input: + bytes: [ 0x01, 0xc5, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.s[w14, 0:3], { z8.s - z11.s }" + + - + input: + bytes: [ 0x83, 0xe5, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3v.s[w15, 0:3], { z12.s - z15.s }" + + - + input: + bytes: [ 0x83, 0xe7, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3v.s[w15, 0:3], { z28.s - z31.s }" + + - + input: + bytes: [ 0x01, 0x86, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.s[w12, 0:3], { z16.s - z19.s }" + + - + input: + bytes: [ 0x01, 0x84, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.s[w12, 0:3], { z0.s - z3.s }" + + - + input: + bytes: [ 0x00, 0xc6, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.s[w14, 0:3], { z16.s - z19.s }" + + - + input: + bytes: [ 0x80, 0x85, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.s[w12, 0:3], { z12.s - z15.s }" + + - + input: + bytes: [ 0x01, 0xc4, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.s[w14, 0:3], { z0.s - z3.s }" + + - + input: + bytes: [ 0x81, 0x86, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.s[w12, 0:3], { z20.s - z23.s }" + + - + input: + bytes: [ 0x02, 0xe5, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2v.s[w15, 0:3], { z8.s - z11.s }" + + - + input: + bytes: [ 0x83, 0xa5, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3v.s[w13, 0:3], { z12.s - z15.s }" + + - + input: + bytes: [ 0x00, 0x84, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.s[w12, 0:3], { z0.s - z3.s }" + + - + input: + bytes: [ 0x01, 0xc5, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.s[w14, 0:3], { z8.s - z11.s }" + + - + input: + bytes: [ 0x83, 0xe5, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3v.s[w15, 0:3], { z12.s - z15.s }" + + - + input: + bytes: [ 0x83, 0xe7, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3v.s[w15, 0:3], { z28.s - z31.s }" + + - + input: + bytes: [ 0x01, 0x86, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.s[w12, 0:3], { z16.s - z19.s }" + + - + input: + bytes: [ 0x01, 0x84, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.s[w12, 0:3], { z0.s - z3.s }" + + - + input: + bytes: [ 0x00, 0xc6, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.s[w14, 0:3], { z16.s - z19.s }" + + - + input: + bytes: [ 0x80, 0x85, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.s[w12, 0:3], { z12.s - z15.s }" + + - + input: + bytes: [ 0x01, 0xc4, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.s[w14, 0:3], { z0.s - z3.s }" + + - + input: + bytes: [ 0x81, 0x86, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.s[w12, 0:3], { z20.s - z23.s }" + + - + input: + bytes: [ 0x02, 0xe5, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2v.s[w15, 0:3], { z8.s - z11.s }" + + - + input: + bytes: [ 0x83, 0xa5, 0x84, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za3v.s[w13, 0:3], { z12.s - z15.s }" + + - + input: + bytes: [ 0x00, 0x04, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za0h.d[w12, 0:3]" + + - + input: + bytes: [ 0x54, 0x44, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d - z23.d }, za2h.d[w14, 0:3]" + + - + input: + bytes: [ 0xb4, 0x64, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d - z23.d }, za5h.d[w15, 0:3]" + + - + input: + bytes: [ 0xfc, 0x64, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d - z31.d }, za7h.d[w15, 0:3]" + + - + input: + bytes: [ 0x24, 0x04, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d - z7.d }, za1h.d[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0x04, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za1h.d[w12, 0:3]" + + - + input: + bytes: [ 0x78, 0x44, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.d - z27.d }, za3h.d[w14, 0:3]" + + - + input: + bytes: [ 0x80, 0x04, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za4h.d[w12, 0:3]" + + - + input: + bytes: [ 0x30, 0x44, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.d - z19.d }, za1h.d[w14, 0:3]" + + - + input: + bytes: [ 0xdc, 0x04, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d - z31.d }, za6h.d[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0x64, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za1h.d[w15, 0:3]" + + - + input: + bytes: [ 0x84, 0x24, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d - z7.d }, za4h.d[w13, 0:3]" + + - + input: + bytes: [ 0x00, 0x04, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za0h.d[w12, 0:3]" + + - + input: + bytes: [ 0x54, 0x44, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d - z23.d }, za2h.d[w14, 0:3]" + + - + input: + bytes: [ 0xb4, 0x64, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d - z23.d }, za5h.d[w15, 0:3]" + + - + input: + bytes: [ 0xfc, 0x64, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d - z31.d }, za7h.d[w15, 0:3]" + + - + input: + bytes: [ 0x24, 0x04, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d - z7.d }, za1h.d[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0x04, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za1h.d[w12, 0:3]" + + - + input: + bytes: [ 0x78, 0x44, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.d - z27.d }, za3h.d[w14, 0:3]" + + - + input: + bytes: [ 0x80, 0x04, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za4h.d[w12, 0:3]" + + - + input: + bytes: [ 0x30, 0x44, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.d - z19.d }, za1h.d[w14, 0:3]" + + - + input: + bytes: [ 0xdc, 0x04, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d - z31.d }, za6h.d[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0x64, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za1h.d[w15, 0:3]" + + - + input: + bytes: [ 0x84, 0x24, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d - z7.d }, za4h.d[w13, 0:3]" + + - + input: + bytes: [ 0x00, 0x84, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za0v.d[w12, 0:3]" + + - + input: + bytes: [ 0x54, 0xc4, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d - z23.d }, za2v.d[w14, 0:3]" + + - + input: + bytes: [ 0xb4, 0xe4, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d - z23.d }, za5v.d[w15, 0:3]" + + - + input: + bytes: [ 0xfc, 0xe4, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d - z31.d }, za7v.d[w15, 0:3]" + + - + input: + bytes: [ 0x24, 0x84, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d - z7.d }, za1v.d[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0x84, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za1v.d[w12, 0:3]" + + - + input: + bytes: [ 0x78, 0xc4, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.d - z27.d }, za3v.d[w14, 0:3]" + + - + input: + bytes: [ 0x80, 0x84, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za4v.d[w12, 0:3]" + + - + input: + bytes: [ 0x30, 0xc4, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.d - z19.d }, za1v.d[w14, 0:3]" + + - + input: + bytes: [ 0xdc, 0x84, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d - z31.d }, za6v.d[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0xe4, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za1v.d[w15, 0:3]" + + - + input: + bytes: [ 0x84, 0xa4, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d - z7.d }, za4v.d[w13, 0:3]" + + - + input: + bytes: [ 0x00, 0x84, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za0v.d[w12, 0:3]" + + - + input: + bytes: [ 0x54, 0xc4, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d - z23.d }, za2v.d[w14, 0:3]" + + - + input: + bytes: [ 0xb4, 0xe4, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d - z23.d }, za5v.d[w15, 0:3]" + + - + input: + bytes: [ 0xfc, 0xe4, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d - z31.d }, za7v.d[w15, 0:3]" + + - + input: + bytes: [ 0x24, 0x84, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d - z7.d }, za1v.d[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0x84, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za1v.d[w12, 0:3]" + + - + input: + bytes: [ 0x78, 0xc4, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.d - z27.d }, za3v.d[w14, 0:3]" + + - + input: + bytes: [ 0x80, 0x84, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za4v.d[w12, 0:3]" + + - + input: + bytes: [ 0x30, 0xc4, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.d - z19.d }, za1v.d[w14, 0:3]" + + - + input: + bytes: [ 0xdc, 0x84, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d - z31.d }, za6v.d[w12, 0:3]" + + - + input: + bytes: [ 0x20, 0xe4, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za1v.d[w15, 0:3]" + + - + input: + bytes: [ 0x84, 0xa4, 0xc6, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d - z7.d }, za4v.d[w13, 0:3]" + + - + input: + bytes: [ 0x00, 0x0c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za.d[w8, 0, vgx4]" + + - + input: + bytes: [ 0x00, 0x0c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za.d[w8, 0, vgx4]" + + - + input: + bytes: [ 0x54, 0x4c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d - z23.d }, za.d[w10, 2, vgx4]" + + - + input: + bytes: [ 0x54, 0x4c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d - z23.d }, za.d[w10, 2, vgx4]" + + - + input: + bytes: [ 0xb4, 0x6c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d - z23.d }, za.d[w11, 5, vgx4]" + + - + input: + bytes: [ 0xb4, 0x6c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d - z23.d }, za.d[w11, 5, vgx4]" + + - + input: + bytes: [ 0xfc, 0x6c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d - z31.d }, za.d[w11, 7, vgx4]" + + - + input: + bytes: [ 0xfc, 0x6c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d - z31.d }, za.d[w11, 7, vgx4]" + + - + input: + bytes: [ 0x24, 0x0c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d - z7.d }, za.d[w8, 1, vgx4]" + + - + input: + bytes: [ 0x24, 0x0c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d - z7.d }, za.d[w8, 1, vgx4]" + + - + input: + bytes: [ 0x20, 0x0c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za.d[w8, 1, vgx4]" + + - + input: + bytes: [ 0x20, 0x0c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za.d[w8, 1, vgx4]" + + - + input: + bytes: [ 0x78, 0x4c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.d - z27.d }, za.d[w10, 3, vgx4]" + + - + input: + bytes: [ 0x78, 0x4c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.d - z27.d }, za.d[w10, 3, vgx4]" + + - + input: + bytes: [ 0x80, 0x0c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za.d[w8, 4, vgx4]" + + - + input: + bytes: [ 0x80, 0x0c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za.d[w8, 4, vgx4]" + + - + input: + bytes: [ 0x30, 0x4c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.d - z19.d }, za.d[w10, 1, vgx4]" + + - + input: + bytes: [ 0x30, 0x4c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.d - z19.d }, za.d[w10, 1, vgx4]" + + - + input: + bytes: [ 0xdc, 0x0c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d - z31.d }, za.d[w8, 6, vgx4]" + + - + input: + bytes: [ 0xdc, 0x0c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d - z31.d }, za.d[w8, 6, vgx4]" + + - + input: + bytes: [ 0x20, 0x6c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za.d[w11, 1, vgx4]" + + - + input: + bytes: [ 0x20, 0x6c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za.d[w11, 1, vgx4]" + + - + input: + bytes: [ 0x84, 0x2c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d - z7.d }, za.d[w9, 4, vgx4]" + + - + input: + bytes: [ 0x84, 0x2c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d - z7.d }, za.d[w9, 4, vgx4]" + + - + input: + bytes: [ 0x00, 0x0c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za.d[w8, 0, vgx4]" + + - + input: + bytes: [ 0x54, 0x4c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d - z23.d }, za.d[w10, 2, vgx4]" + + - + input: + bytes: [ 0xb4, 0x6c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.d - z23.d }, za.d[w11, 5, vgx4]" + + - + input: + bytes: [ 0xfc, 0x6c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d - z31.d }, za.d[w11, 7, vgx4]" + + - + input: + bytes: [ 0x24, 0x0c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d - z7.d }, za.d[w8, 1, vgx4]" + + - + input: + bytes: [ 0x20, 0x0c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za.d[w8, 1, vgx4]" + + - + input: + bytes: [ 0x78, 0x4c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.d - z27.d }, za.d[w10, 3, vgx4]" + + - + input: + bytes: [ 0x80, 0x0c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za.d[w8, 4, vgx4]" + + - + input: + bytes: [ 0x30, 0x4c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.d - z19.d }, za.d[w10, 1, vgx4]" + + - + input: + bytes: [ 0xdc, 0x0c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.d - z31.d }, za.d[w8, 6, vgx4]" + + - + input: + bytes: [ 0x20, 0x6c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.d - z3.d }, za.d[w11, 1, vgx4]" + + - + input: + bytes: [ 0x84, 0x2c, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.d - z7.d }, za.d[w9, 4, vgx4]" + + - + input: + bytes: [ 0x00, 0x04, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.d[w12, 0:3], { z0.d - z3.d }" + + - + input: + bytes: [ 0x05, 0x45, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5h.d[w14, 0:3], { z8.d - z11.d }" + + - + input: + bytes: [ 0x87, 0x65, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7h.d[w15, 0:3], { z12.d - z15.d }" + + - + input: + bytes: [ 0x87, 0x67, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7h.d[w15, 0:3], { z28.d - z31.d }" + + - + input: + bytes: [ 0x05, 0x06, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5h.d[w12, 0:3], { z16.d - z19.d }" + + - + input: + bytes: [ 0x01, 0x04, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.d[w12, 0:3], { z0.d - z3.d }" + + - + input: + bytes: [ 0x00, 0x46, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.d[w14, 0:3], { z16.d - z19.d }" + + - + input: + bytes: [ 0x80, 0x05, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.d[w12, 0:3], { z12.d - z15.d }" + + - + input: + bytes: [ 0x01, 0x44, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.d[w14, 0:3], { z0.d - z3.d }" + + - + input: + bytes: [ 0x85, 0x06, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5h.d[w12, 0:3], { z20.d - z23.d }" + + - + input: + bytes: [ 0x02, 0x65, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2h.d[w15, 0:3], { z8.d - z11.d }" + + - + input: + bytes: [ 0x87, 0x25, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7h.d[w13, 0:3], { z12.d - z15.d }" + + - + input: + bytes: [ 0x00, 0x04, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.d[w12, 0:3], { z0.d - z3.d }" + + - + input: + bytes: [ 0x05, 0x45, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5h.d[w14, 0:3], { z8.d - z11.d }" + + - + input: + bytes: [ 0x87, 0x65, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7h.d[w15, 0:3], { z12.d - z15.d }" + + - + input: + bytes: [ 0x87, 0x67, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7h.d[w15, 0:3], { z28.d - z31.d }" + + - + input: + bytes: [ 0x05, 0x06, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5h.d[w12, 0:3], { z16.d - z19.d }" + + - + input: + bytes: [ 0x01, 0x04, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.d[w12, 0:3], { z0.d - z3.d }" + + - + input: + bytes: [ 0x00, 0x46, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.d[w14, 0:3], { z16.d - z19.d }" + + - + input: + bytes: [ 0x80, 0x05, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.d[w12, 0:3], { z12.d - z15.d }" + + - + input: + bytes: [ 0x01, 0x44, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1h.d[w14, 0:3], { z0.d - z3.d }" + + - + input: + bytes: [ 0x85, 0x06, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5h.d[w12, 0:3], { z20.d - z23.d }" + + - + input: + bytes: [ 0x02, 0x65, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2h.d[w15, 0:3], { z8.d - z11.d }" + + - + input: + bytes: [ 0x87, 0x25, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7h.d[w13, 0:3], { z12.d - z15.d }" + + - + input: + bytes: [ 0x00, 0x84, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.d[w12, 0:3], { z0.d - z3.d }" + + - + input: + bytes: [ 0x05, 0xc5, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5v.d[w14, 0:3], { z8.d - z11.d }" + + - + input: + bytes: [ 0x87, 0xe5, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7v.d[w15, 0:3], { z12.d - z15.d }" + + - + input: + bytes: [ 0x87, 0xe7, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7v.d[w15, 0:3], { z28.d - z31.d }" + + - + input: + bytes: [ 0x05, 0x86, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5v.d[w12, 0:3], { z16.d - z19.d }" + + - + input: + bytes: [ 0x01, 0x84, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.d[w12, 0:3], { z0.d - z3.d }" + + - + input: + bytes: [ 0x00, 0xc6, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.d[w14, 0:3], { z16.d - z19.d }" + + - + input: + bytes: [ 0x80, 0x85, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.d[w12, 0:3], { z12.d - z15.d }" + + - + input: + bytes: [ 0x01, 0xc4, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.d[w14, 0:3], { z0.d - z3.d }" + + - + input: + bytes: [ 0x85, 0x86, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5v.d[w12, 0:3], { z20.d - z23.d }" + + - + input: + bytes: [ 0x02, 0xe5, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2v.d[w15, 0:3], { z8.d - z11.d }" + + - + input: + bytes: [ 0x87, 0xa5, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7v.d[w13, 0:3], { z12.d - z15.d }" + + - + input: + bytes: [ 0x00, 0x84, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.d[w12, 0:3], { z0.d - z3.d }" + + - + input: + bytes: [ 0x05, 0xc5, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5v.d[w14, 0:3], { z8.d - z11.d }" + + - + input: + bytes: [ 0x87, 0xe5, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7v.d[w15, 0:3], { z12.d - z15.d }" + + - + input: + bytes: [ 0x87, 0xe7, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7v.d[w15, 0:3], { z28.d - z31.d }" + + - + input: + bytes: [ 0x05, 0x86, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5v.d[w12, 0:3], { z16.d - z19.d }" + + - + input: + bytes: [ 0x01, 0x84, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.d[w12, 0:3], { z0.d - z3.d }" + + - + input: + bytes: [ 0x00, 0xc6, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.d[w14, 0:3], { z16.d - z19.d }" + + - + input: + bytes: [ 0x80, 0x85, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.d[w12, 0:3], { z12.d - z15.d }" + + - + input: + bytes: [ 0x01, 0xc4, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za1v.d[w14, 0:3], { z0.d - z3.d }" + + - + input: + bytes: [ 0x85, 0x86, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za5v.d[w12, 0:3], { z20.d - z23.d }" + + - + input: + bytes: [ 0x02, 0xe5, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za2v.d[w15, 0:3], { z8.d - z11.d }" + + - + input: + bytes: [ 0x87, 0xa5, 0xc4, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za7v.d[w13, 0:3], { z12.d - z15.d }" + + - + input: + bytes: [ 0x00, 0x0c, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 0, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x00, 0x0c, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 0, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x05, 0x4d, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w10, 5, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x05, 0x4d, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w10, 5, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x87, 0x6d, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w11, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x87, 0x6d, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w11, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x87, 0x6f, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w11, 7, vgx4], { z28.d - z31.d }" + + - + input: + bytes: [ 0x87, 0x6f, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w11, 7, vgx4], { z28.d - z31.d }" + + - + input: + bytes: [ 0x05, 0x0e, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 5, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x05, 0x0e, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 5, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x01, 0x0c, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x01, 0x0c, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x00, 0x4e, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w10, 0, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x00, 0x4e, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w10, 0, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x80, 0x0d, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 0, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x80, 0x0d, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 0, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x01, 0x4c, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w10, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x01, 0x4c, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w10, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x85, 0x0e, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 5, vgx4], { z20.d - z23.d }" + + - + input: + bytes: [ 0x85, 0x0e, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 5, vgx4], { z20.d - z23.d }" + + - + input: + bytes: [ 0x02, 0x6d, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w11, 2, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x02, 0x6d, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w11, 2, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x87, 0x2d, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w9, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x87, 0x2d, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w9, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x00, 0x0c, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 0, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x05, 0x4d, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w10, 5, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x87, 0x6d, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w11, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x87, 0x6f, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w11, 7, vgx4], { z28.d - z31.d }" + + - + input: + bytes: [ 0x05, 0x0e, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 5, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x01, 0x0c, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x00, 0x4e, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w10, 0, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x80, 0x0d, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 0, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x01, 0x4c, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w10, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x85, 0x0e, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w8, 5, vgx4], { z20.d - z23.d }" + + - + input: + bytes: [ 0x02, 0x6d, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w11, 2, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x87, 0x2d, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za.d[w9, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x00, 0x04, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b - z3.b }, za0h.b[w12, 0:3]" + + - + input: + bytes: [ 0x54, 0x44, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.b - z23.b }, za0h.b[w14, 8:11]" + + - + input: + bytes: [ 0x34, 0x64, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.b - z23.b }, za0h.b[w15, 4:7]" + + - + input: + bytes: [ 0x7c, 0x64, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.b - z31.b }, za0h.b[w15, 12:15]" + + - + input: + bytes: [ 0x24, 0x04, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.b - z7.b }, za0h.b[w12, 4:7]" + + - + input: + bytes: [ 0x20, 0x04, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b - z3.b }, za0h.b[w12, 4:7]" + + - + input: + bytes: [ 0x78, 0x44, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.b - z27.b }, za0h.b[w14, 12:15]" + + - + input: + bytes: [ 0x30, 0x44, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.b - z19.b }, za0h.b[w14, 4:7]" + + - + input: + bytes: [ 0x5c, 0x04, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.b - z31.b }, za0h.b[w12, 8:11]" + + - + input: + bytes: [ 0x20, 0x64, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b - z3.b }, za0h.b[w15, 4:7]" + + - + input: + bytes: [ 0x04, 0x24, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.b - z7.b }, za0h.b[w13, 0:3]" + + - + input: + bytes: [ 0x00, 0x04, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b - z3.b }, za0h.b[w12, 0:3]" + + - + input: + bytes: [ 0x54, 0x44, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.b - z23.b }, za0h.b[w14, 8:11]" + + - + input: + bytes: [ 0x34, 0x64, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.b - z23.b }, za0h.b[w15, 4:7]" + + - + input: + bytes: [ 0x7c, 0x64, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.b - z31.b }, za0h.b[w15, 12:15]" + + - + input: + bytes: [ 0x24, 0x04, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.b - z7.b }, za0h.b[w12, 4:7]" + + - + input: + bytes: [ 0x20, 0x04, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b - z3.b }, za0h.b[w12, 4:7]" + + - + input: + bytes: [ 0x78, 0x44, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.b - z27.b }, za0h.b[w14, 12:15]" + + - + input: + bytes: [ 0x30, 0x44, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.b - z19.b }, za0h.b[w14, 4:7]" + + - + input: + bytes: [ 0x5c, 0x04, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.b - z31.b }, za0h.b[w12, 8:11]" + + - + input: + bytes: [ 0x20, 0x64, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b - z3.b }, za0h.b[w15, 4:7]" + + - + input: + bytes: [ 0x04, 0x24, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.b - z7.b }, za0h.b[w13, 0:3]" + + - + input: + bytes: [ 0x00, 0x84, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b - z3.b }, za0v.b[w12, 0:3]" + + - + input: + bytes: [ 0x54, 0xc4, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.b - z23.b }, za0v.b[w14, 8:11]" + + - + input: + bytes: [ 0x34, 0xe4, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.b - z23.b }, za0v.b[w15, 4:7]" + + - + input: + bytes: [ 0x7c, 0xe4, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.b - z31.b }, za0v.b[w15, 12:15]" + + - + input: + bytes: [ 0x24, 0x84, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.b - z7.b }, za0v.b[w12, 4:7]" + + - + input: + bytes: [ 0x20, 0x84, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b - z3.b }, za0v.b[w12, 4:7]" + + - + input: + bytes: [ 0x78, 0xc4, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.b - z27.b }, za0v.b[w14, 12:15]" + + - + input: + bytes: [ 0x30, 0xc4, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.b - z19.b }, za0v.b[w14, 4:7]" + + - + input: + bytes: [ 0x5c, 0x84, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.b - z31.b }, za0v.b[w12, 8:11]" + + - + input: + bytes: [ 0x20, 0xe4, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b - z3.b }, za0v.b[w15, 4:7]" + + - + input: + bytes: [ 0x04, 0xa4, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.b - z7.b }, za0v.b[w13, 0:3]" + + - + input: + bytes: [ 0x00, 0x84, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b - z3.b }, za0v.b[w12, 0:3]" + + - + input: + bytes: [ 0x54, 0xc4, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.b - z23.b }, za0v.b[w14, 8:11]" + + - + input: + bytes: [ 0x34, 0xe4, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z20.b - z23.b }, za0v.b[w15, 4:7]" + + - + input: + bytes: [ 0x7c, 0xe4, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.b - z31.b }, za0v.b[w15, 12:15]" + + - + input: + bytes: [ 0x24, 0x84, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.b - z7.b }, za0v.b[w12, 4:7]" + + - + input: + bytes: [ 0x20, 0x84, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b - z3.b }, za0v.b[w12, 4:7]" + + - + input: + bytes: [ 0x78, 0xc4, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z24.b - z27.b }, za0v.b[w14, 12:15]" + + - + input: + bytes: [ 0x30, 0xc4, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z16.b - z19.b }, za0v.b[w14, 4:7]" + + - + input: + bytes: [ 0x5c, 0x84, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z28.b - z31.b }, za0v.b[w12, 8:11]" + + - + input: + bytes: [ 0x20, 0xe4, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z0.b - z3.b }, za0v.b[w15, 4:7]" + + - + input: + bytes: [ 0x04, 0xa4, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov { z4.b - z7.b }, za0v.b[w13, 0:3]" + + - + input: + bytes: [ 0x00, 0x04, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 0:3], { z0.b - z3.b }" + + - + input: + bytes: [ 0x01, 0x45, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w14, 4:7], { z8.b - z11.b }" + + - + input: + bytes: [ 0x83, 0x65, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w15, 12:15], { z12.b - z15.b }" + + - + input: + bytes: [ 0x83, 0x67, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w15, 12:15], { z28.b - z31.b }" + + - + input: + bytes: [ 0x01, 0x06, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 4:7], { z16.b - z19.b }" + + - + input: + bytes: [ 0x01, 0x04, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 4:7], { z0.b - z3.b }" + + - + input: + bytes: [ 0x00, 0x46, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w14, 0:3], { z16.b - z19.b }" + + - + input: + bytes: [ 0x80, 0x05, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 0:3], { z12.b - z15.b }" + + - + input: + bytes: [ 0x01, 0x44, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w14, 4:7], { z0.b - z3.b }" + + - + input: + bytes: [ 0x81, 0x06, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 4:7], { z20.b - z23.b }" + + - + input: + bytes: [ 0x02, 0x65, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w15, 8:11], { z8.b - z11.b }" + + - + input: + bytes: [ 0x83, 0x25, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w13, 12:15], { z12.b - z15.b }" + + - + input: + bytes: [ 0x00, 0x04, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 0:3], { z0.b - z3.b }" + + - + input: + bytes: [ 0x01, 0x45, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w14, 4:7], { z8.b - z11.b }" + + - + input: + bytes: [ 0x83, 0x65, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w15, 12:15], { z12.b - z15.b }" + + - + input: + bytes: [ 0x83, 0x67, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w15, 12:15], { z28.b - z31.b }" + + - + input: + bytes: [ 0x01, 0x06, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 4:7], { z16.b - z19.b }" + + - + input: + bytes: [ 0x01, 0x04, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 4:7], { z0.b - z3.b }" + + - + input: + bytes: [ 0x00, 0x46, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w14, 0:3], { z16.b - z19.b }" + + - + input: + bytes: [ 0x80, 0x05, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 0:3], { z12.b - z15.b }" + + - + input: + bytes: [ 0x01, 0x44, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w14, 4:7], { z0.b - z3.b }" + + - + input: + bytes: [ 0x81, 0x06, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w12, 4:7], { z20.b - z23.b }" + + - + input: + bytes: [ 0x02, 0x65, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w15, 8:11], { z8.b - z11.b }" + + - + input: + bytes: [ 0x83, 0x25, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0h.b[w13, 12:15], { z12.b - z15.b }" + + - + input: + bytes: [ 0x00, 0x84, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 0:3], { z0.b - z3.b }" + + - + input: + bytes: [ 0x01, 0xc5, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w14, 4:7], { z8.b - z11.b }" + + - + input: + bytes: [ 0x83, 0xe5, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w15, 12:15], { z12.b - z15.b }" + + - + input: + bytes: [ 0x83, 0xe7, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w15, 12:15], { z28.b - z31.b }" + + - + input: + bytes: [ 0x01, 0x86, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 4:7], { z16.b - z19.b }" + + - + input: + bytes: [ 0x01, 0x84, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 4:7], { z0.b - z3.b }" + + - + input: + bytes: [ 0x00, 0xc6, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w14, 0:3], { z16.b - z19.b }" + + - + input: + bytes: [ 0x80, 0x85, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 0:3], { z12.b - z15.b }" + + - + input: + bytes: [ 0x01, 0xc4, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w14, 4:7], { z0.b - z3.b }" + + - + input: + bytes: [ 0x81, 0x86, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 4:7], { z20.b - z23.b }" + + - + input: + bytes: [ 0x02, 0xe5, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w15, 8:11], { z8.b - z11.b }" + + - + input: + bytes: [ 0x83, 0xa5, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w13, 12:15], { z12.b - z15.b }" + + - + input: + bytes: [ 0x00, 0x84, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 0:3], { z0.b - z3.b }" + + - + input: + bytes: [ 0x01, 0xc5, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w14, 4:7], { z8.b - z11.b }" + + - + input: + bytes: [ 0x83, 0xe5, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w15, 12:15], { z12.b - z15.b }" + + - + input: + bytes: [ 0x83, 0xe7, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w15, 12:15], { z28.b - z31.b }" + + - + input: + bytes: [ 0x01, 0x86, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 4:7], { z16.b - z19.b }" + + - + input: + bytes: [ 0x01, 0x84, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 4:7], { z0.b - z3.b }" + + - + input: + bytes: [ 0x00, 0xc6, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w14, 0:3], { z16.b - z19.b }" + + - + input: + bytes: [ 0x80, 0x85, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 0:3], { z12.b - z15.b }" + + - + input: + bytes: [ 0x01, 0xc4, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w14, 4:7], { z0.b - z3.b }" + + - + input: + bytes: [ 0x81, 0x86, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w12, 4:7], { z20.b - z23.b }" + + - + input: + bytes: [ 0x02, 0xe5, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w15, 8:11], { z8.b - z11.b }" + + - + input: + bytes: [ 0x83, 0xa5, 0x04, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "mov za0v.b[w13, 12:15], { z12.b - z15.b }" diff --git a/tests/MC/AArch64/SME2/movt.s.yaml b/tests/MC/AArch64/SME2/movt.s.yaml new file mode 100644 index 0000000000..73b6b0bbd0 --- /dev/null +++ b/tests/MC/AArch64/SME2/movt.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x03, 0x4c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movt x0, zt0[0]" + + - + input: + bytes: [ 0xf5, 0x53, 0x4c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movt x21, zt0[40]" + + - + input: + bytes: [ 0xf7, 0x63, 0x4c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movt x23, zt0[48]" + + - + input: + bytes: [ 0xff, 0x73, 0x4c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movt xzr, zt0[56]" + + - + input: + bytes: [ 0xe0, 0x03, 0x4e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movt zt0[0], x0" + + - + input: + bytes: [ 0xf5, 0x53, 0x4e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movt zt0[40], x21" + + - + input: + bytes: [ 0xf7, 0x63, 0x4e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movt zt0[48], x23" + + - + input: + bytes: [ 0xff, 0x73, 0x4e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movt zt0[56], xzr" diff --git a/tests/MC/AArch64/SME2/sclamp.s.yaml b/tests/MC/AArch64/SME2/sclamp.s.yaml new file mode 100644 index 0000000000..4b6a488be9 --- /dev/null +++ b/tests/MC/AArch64/SME2/sclamp.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc4, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z0.h, z1.h }, z0.h, z0.h" + + - + input: + bytes: [ 0x54, 0xc5, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z20.h, z21.h }, z10.h, z21.h" + + - + input: + bytes: [ 0xb6, 0xc5, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z22.h, z23.h }, z13.h, z8.h" + + - + input: + bytes: [ 0xfe, 0xc7, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z30.h, z31.h }, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0xc4, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z0.s, z1.s }, z0.s, z0.s" + + - + input: + bytes: [ 0x54, 0xc5, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z20.s, z21.s }, z10.s, z21.s" + + - + input: + bytes: [ 0xb6, 0xc5, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z22.s, z23.s }, z13.s, z8.s" + + - + input: + bytes: [ 0xfe, 0xc7, 0xbf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z30.s, z31.s }, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0xc4, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z0.d, z1.d }, z0.d, z0.d" + + - + input: + bytes: [ 0x54, 0xc5, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z20.d, z21.d }, z10.d, z21.d" + + - + input: + bytes: [ 0xb6, 0xc5, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z22.d, z23.d }, z13.d, z8.d" + + - + input: + bytes: [ 0xfe, 0xc7, 0xff, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z30.d, z31.d }, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0xc4, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z0.b, z1.b }, z0.b, z0.b" + + - + input: + bytes: [ 0x54, 0xc5, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z20.b, z21.b }, z10.b, z21.b" + + - + input: + bytes: [ 0xb6, 0xc5, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z22.b, z23.b }, z13.b, z8.b" + + - + input: + bytes: [ 0xfe, 0xc7, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z30.b, z31.b }, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0xcc, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z0.h - z3.h }, z0.h, z0.h" + + - + input: + bytes: [ 0x54, 0xcd, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z20.h - z23.h }, z10.h, z21.h" + + - + input: + bytes: [ 0xb4, 0xcd, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z20.h - z23.h }, z13.h, z8.h" + + - + input: + bytes: [ 0xfc, 0xcf, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z28.h - z31.h }, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0xcc, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z0.s - z3.s }, z0.s, z0.s" + + - + input: + bytes: [ 0x54, 0xcd, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z20.s - z23.s }, z10.s, z21.s" + + - + input: + bytes: [ 0xb4, 0xcd, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z20.s - z23.s }, z13.s, z8.s" + + - + input: + bytes: [ 0xfc, 0xcf, 0xbf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z28.s - z31.s }, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0xcc, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z0.d - z3.d }, z0.d, z0.d" + + - + input: + bytes: [ 0x54, 0xcd, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z20.d - z23.d }, z10.d, z21.d" + + - + input: + bytes: [ 0xb4, 0xcd, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z20.d - z23.d }, z13.d, z8.d" + + - + input: + bytes: [ 0xfc, 0xcf, 0xff, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z28.d - z31.d }, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0xcc, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z0.b - z3.b }, z0.b, z0.b" + + - + input: + bytes: [ 0x54, 0xcd, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z20.b - z23.b }, z10.b, z21.b" + + - + input: + bytes: [ 0xb4, 0xcd, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z20.b - z23.b }, z13.b, z8.b" + + - + input: + bytes: [ 0xfc, 0xcf, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sclamp { z28.b - z31.b }, z31.b, z31.b" diff --git a/tests/MC/AArch64/SME2/scvtf.s.yaml b/tests/MC/AArch64/SME2/scvtf.s.yaml new file mode 100644 index 0000000000..3e85a643ce --- /dev/null +++ b/tests/MC/AArch64/SME2/scvtf.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "scvtf { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x54, 0xe1, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "scvtf { z20.s, z21.s }, { z10.s, z11.s }" + + - + input: + bytes: [ 0x96, 0xe1, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "scvtf { z22.s, z23.s }, { z12.s, z13.s }" + + - + input: + bytes: [ 0xde, 0xe3, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "scvtf { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x00, 0xe0, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "scvtf { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x14, 0xe1, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "scvtf { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x94, 0xe1, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "scvtf { z20.s - z23.s }, { z12.s - z15.s }" + + - + input: + bytes: [ 0x9c, 0xe3, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "scvtf { z28.s - z31.s }, { z28.s - z31.s }" diff --git a/tests/MC/AArch64/SME2/sdot.s.yaml b/tests/MC/AArch64/SME2/sdot.s.yaml new file mode 100644 index 0000000000..6d623c6cf9 --- /dev/null +++ b/tests/MC/AArch64/SME2/sdot.s.yaml @@ -0,0 +1,4320 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x14, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x08, 0x14, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x4d, 0x55, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x4d, 0x55, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xaf, 0x75, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xaf, 0x75, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xef, 0x77, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xef, 0x77, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x2d, 0x16, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x2d, 0x16, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x29, 0x14, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x29, 0x14, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x68, 0x56, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x68, 0x56, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x88, 0x15, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x88, 0x15, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x29, 0x54, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x29, 0x54, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xcd, 0x16, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xcd, 0x16, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x2a, 0x75, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x2a, 0x75, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x8f, 0x35, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x8f, 0x35, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x00, 0x10, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x00, 0x10, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x45, 0x55, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x45, 0x55, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x87, 0x7d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]" + + - + input: + bytes: [ 0x87, 0x7d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]" + + - + input: + bytes: [ 0xc7, 0x7f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]" + + - + input: + bytes: [ 0xc7, 0x7f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]" + + - + input: + bytes: [ 0x05, 0x1e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]" + + - + input: + bytes: [ 0x05, 0x1e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]" + + - + input: + bytes: [ 0x01, 0x14, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x01, 0x14, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x40, 0x56, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x40, 0x56, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x80, 0x19, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]" + + - + input: + bytes: [ 0x80, 0x19, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]" + + - + input: + bytes: [ 0x01, 0x58, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]" + + - + input: + bytes: [ 0x01, 0x58, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]" + + - + input: + bytes: [ 0xc5, 0x1a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0xc5, 0x1a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x02, 0x75, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0x02, 0x75, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0x87, 0x39, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]" + + - + input: + bytes: [ 0x87, 0x39, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]" + + - + input: + bytes: [ 0x08, 0x14, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x08, 0x14, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x4d, 0x55, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x4d, 0x55, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x8f, 0x75, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x8f, 0x75, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xcf, 0x77, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xcf, 0x77, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x0d, 0x16, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x0d, 0x16, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x09, 0x14, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x09, 0x14, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x48, 0x56, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x48, 0x56, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x88, 0x15, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x88, 0x15, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x09, 0x54, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x09, 0x54, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xcd, 0x16, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xcd, 0x16, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x0a, 0x75, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x0a, 0x75, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x8f, 0x35, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x8f, 0x35, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x00, 0x14, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x00, 0x14, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x45, 0x55, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0x45, 0x55, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0xa7, 0x75, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xa7, 0x75, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xe7, 0x77, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0xe7, 0x77, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0x25, 0x16, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x25, 0x16, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x21, 0x14, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x21, 0x14, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x60, 0x56, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x60, 0x56, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x80, 0x15, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x80, 0x15, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x21, 0x54, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0x21, 0x54, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0xc5, 0x16, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0xc5, 0x16, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0x22, 0x75, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x22, 0x75, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x87, 0x35, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x87, 0x35, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x20, 0x10, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x20, 0x10, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x65, 0x55, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]" + + - + input: + bytes: [ 0x65, 0x55, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]" + + - + input: + bytes: [ 0xa7, 0x7d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]" + + - + input: + bytes: [ 0xa7, 0x7d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]" + + - + input: + bytes: [ 0xe7, 0x7f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]" + + - + input: + bytes: [ 0xe7, 0x7f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]" + + - + input: + bytes: [ 0x25, 0x1e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]" + + - + input: + bytes: [ 0x25, 0x1e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]" + + - + input: + bytes: [ 0x21, 0x14, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]" + + - + input: + bytes: [ 0x21, 0x14, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]" + + - + input: + bytes: [ 0x60, 0x56, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]" + + - + input: + bytes: [ 0x60, 0x56, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]" + + - + input: + bytes: [ 0xa0, 0x19, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]" + + - + input: + bytes: [ 0xa0, 0x19, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]" + + - + input: + bytes: [ 0x21, 0x58, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]" + + - + input: + bytes: [ 0x21, 0x58, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]" + + - + input: + bytes: [ 0xe5, 0x1a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]" + + - + input: + bytes: [ 0xe5, 0x1a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]" + + - + input: + bytes: [ 0x22, 0x75, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]" + + - + input: + bytes: [ 0x22, 0x75, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]" + + - + input: + bytes: [ 0xa7, 0x39, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]" + + - + input: + bytes: [ 0xa7, 0x39, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]" + + - + input: + bytes: [ 0x00, 0x14, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x00, 0x14, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x45, 0x55, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx2], { z10.b, z11.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x45, 0x55, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx2], { z10.b, z11.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x87, 0x75, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0x87, 0x75, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0xc7, 0x77, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xc7, 0x77, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x05, 0x16, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z16.b, z17.b }, { z16.b, z17.b }" + + - + input: + bytes: [ 0x05, 0x16, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z16.b, z17.b }, { z16.b, z17.b }" + + - + input: + bytes: [ 0x01, 0x14, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx2], { z0.b, z1.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x01, 0x14, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx2], { z0.b, z1.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x40, 0x56, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx2], { z18.b, z19.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x40, 0x56, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx2], { z18.b, z19.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x80, 0x15, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z12.b, z13.b }, { z2.b, z3.b }" + + - + input: + bytes: [ 0x80, 0x15, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx2], { z12.b, z13.b }, { z2.b, z3.b }" + + - + input: + bytes: [ 0x01, 0x54, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx2], { z0.b, z1.b }, { z26.b, z27.b }" + + - + input: + bytes: [ 0x01, 0x54, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx2], { z0.b, z1.b }, { z26.b, z27.b }" + + - + input: + bytes: [ 0xc5, 0x16, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z22.b, z23.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xc5, 0x16, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx2], { z22.b, z23.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x02, 0x75, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx2], { z8.b, z9.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x02, 0x75, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx2], { z8.b, z9.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x87, 0x35, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }" + + - + input: + bytes: [ 0x87, 0x35, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }" + + - + input: + bytes: [ 0x00, 0x14, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x00, 0x14, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x45, 0x55, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x45, 0x55, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xa7, 0x75, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xa7, 0x75, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xe7, 0x77, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xe7, 0x77, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x25, 0x16, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x25, 0x16, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x14, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x21, 0x14, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x60, 0x56, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x60, 0x56, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x80, 0x15, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x80, 0x15, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x21, 0x54, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x21, 0x54, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xc5, 0x16, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xc5, 0x16, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x22, 0x75, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x22, 0x75, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x87, 0x35, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x87, 0x35, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x08, 0x00, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x08, 0x00, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x4d, 0x45, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x4d, 0x45, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x8f, 0x65, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx2], { z12.h, z13.h }, z8.h[1]" + + - + input: + bytes: [ 0x8f, 0x65, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx2], { z12.h, z13.h }, z8.h[1]" + + - + input: + bytes: [ 0xcf, 0x67, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx2], { z30.h, z31.h }, z15.h[1]" + + - + input: + bytes: [ 0xcf, 0x67, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx2], { z30.h, z31.h }, z15.h[1]" + + - + input: + bytes: [ 0x0d, 0x06, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx2], { z16.h, z17.h }, z0.h[1]" + + - + input: + bytes: [ 0x0d, 0x06, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx2], { z16.h, z17.h }, z0.h[1]" + + - + input: + bytes: [ 0x09, 0x04, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x09, 0x04, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x48, 0x46, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x48, 0x46, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x88, 0x01, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h[0]" + + - + input: + bytes: [ 0x88, 0x01, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h[0]" + + - + input: + bytes: [ 0x09, 0x40, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 1, vgx2], { z0.h, z1.h }, z10.h[0]" + + - + input: + bytes: [ 0x09, 0x40, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 1, vgx2], { z0.h, z1.h }, z10.h[0]" + + - + input: + bytes: [ 0xcd, 0x02, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h[0]" + + - + input: + bytes: [ 0xcd, 0x02, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h[0]" + + - + input: + bytes: [ 0x0a, 0x65, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0x0a, 0x65, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0x8f, 0x21, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h[0]" + + - + input: + bytes: [ 0x8f, 0x21, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h[0]" + + - + input: + bytes: [ 0x00, 0x14, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x00, 0x14, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x45, 0x55, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x45, 0x55, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x87, 0x75, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x87, 0x75, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xc7, 0x77, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xc7, 0x77, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x05, 0x16, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x05, 0x16, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x01, 0x14, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x01, 0x14, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x40, 0x56, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x40, 0x56, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x80, 0x15, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x80, 0x15, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x01, 0x54, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x01, 0x54, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xc5, 0x16, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xc5, 0x16, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x02, 0x75, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x02, 0x75, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x87, 0x35, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x87, 0x35, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x08, 0x14, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x08, 0x14, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x4d, 0x55, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x4d, 0x55, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xaf, 0x75, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xaf, 0x75, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xef, 0x77, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xef, 0x77, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x2d, 0x16, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x2d, 0x16, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x29, 0x14, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x29, 0x14, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x68, 0x56, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x68, 0x56, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x88, 0x15, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x88, 0x15, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x29, 0x54, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x29, 0x54, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xcd, 0x16, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xcd, 0x16, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x2a, 0x75, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x2a, 0x75, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x8f, 0x35, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x8f, 0x35, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x00, 0x90, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x00, 0x90, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x05, 0xd5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x05, 0xd5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x87, 0xfd, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]" + + - + input: + bytes: [ 0x87, 0xfd, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]" + + - + input: + bytes: [ 0x87, 0xff, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]" + + - + input: + bytes: [ 0x87, 0xff, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]" + + - + input: + bytes: [ 0x05, 0x9e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]" + + - + input: + bytes: [ 0x05, 0x9e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]" + + - + input: + bytes: [ 0x01, 0x94, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]" + + - + input: + bytes: [ 0x01, 0x94, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]" + + - + input: + bytes: [ 0x00, 0xd6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x00, 0xd6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x80, 0x99, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]" + + - + input: + bytes: [ 0x80, 0x99, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]" + + - + input: + bytes: [ 0x01, 0xd8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]" + + - + input: + bytes: [ 0x01, 0xd8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]" + + - + input: + bytes: [ 0x85, 0x9a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x85, 0x9a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x02, 0xf5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]" + + - + input: + bytes: [ 0x02, 0xf5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]" + + - + input: + bytes: [ 0x87, 0xb9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]" + + - + input: + bytes: [ 0x87, 0xb9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]" + + - + input: + bytes: [ 0x08, 0x14, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x08, 0x14, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x0d, 0x55, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x0d, 0x55, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x8f, 0x75, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x8f, 0x75, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x8f, 0x77, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x8f, 0x77, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x0d, 0x16, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x0d, 0x16, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x09, 0x14, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x09, 0x14, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x08, 0x56, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x08, 0x56, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x88, 0x15, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x88, 0x15, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x09, 0x54, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x09, 0x54, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x8d, 0x16, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x8d, 0x16, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x0a, 0x75, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x0a, 0x75, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x8f, 0x35, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x8f, 0x35, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x00, 0x14, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x00, 0x14, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x45, 0x55, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0x45, 0x55, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0xa7, 0x75, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xa7, 0x75, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xe7, 0x77, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0xe7, 0x77, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0x25, 0x16, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x25, 0x16, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x21, 0x14, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x21, 0x14, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x60, 0x56, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x60, 0x56, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x80, 0x15, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x80, 0x15, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x21, 0x54, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0x21, 0x54, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0xc5, 0x16, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0xc5, 0x16, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0x22, 0x75, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x22, 0x75, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x87, 0x35, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x87, 0x35, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x20, 0x90, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x20, 0x90, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x25, 0xd5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]" + + - + input: + bytes: [ 0x25, 0xd5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]" + + - + input: + bytes: [ 0xa7, 0xfd, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]" + + - + input: + bytes: [ 0xa7, 0xfd, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]" + + - + input: + bytes: [ 0xa7, 0xff, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]" + + - + input: + bytes: [ 0xa7, 0xff, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]" + + - + input: + bytes: [ 0x25, 0x9e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]" + + - + input: + bytes: [ 0x25, 0x9e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]" + + - + input: + bytes: [ 0x21, 0x94, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]" + + - + input: + bytes: [ 0x21, 0x94, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]" + + - + input: + bytes: [ 0x20, 0xd6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]" + + - + input: + bytes: [ 0x20, 0xd6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]" + + - + input: + bytes: [ 0xa0, 0x99, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]" + + - + input: + bytes: [ 0xa0, 0x99, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]" + + - + input: + bytes: [ 0x21, 0xd8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]" + + - + input: + bytes: [ 0x21, 0xd8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]" + + - + input: + bytes: [ 0xa5, 0x9a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]" + + - + input: + bytes: [ 0xa5, 0x9a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]" + + - + input: + bytes: [ 0x22, 0xf5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]" + + - + input: + bytes: [ 0x22, 0xf5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]" + + - + input: + bytes: [ 0xa7, 0xb9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]" + + - + input: + bytes: [ 0xa7, 0xb9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]" + + - + input: + bytes: [ 0x00, 0x14, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x00, 0x14, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x05, 0x55, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx4], { z8.b - z11.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x05, 0x55, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 5, vgx4], { z8.b - z11.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x87, 0x75, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x87, 0x75, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x87, 0x77, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x87, 0x77, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x05, 0x16, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z16.b - z19.b }, { z16.b - z19.b }" + + - + input: + bytes: [ 0x05, 0x16, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z16.b - z19.b }, { z16.b - z19.b }" + + - + input: + bytes: [ 0x01, 0x14, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx4], { z0.b - z3.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x01, 0x14, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 1, vgx4], { z0.b - z3.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x00, 0x56, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx4], { z16.b - z19.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x00, 0x56, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 0, vgx4], { z16.b - z19.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x80, 0x15, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z12.b - z15.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x80, 0x15, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 0, vgx4], { z12.b - z15.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x01, 0x54, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx4], { z0.b - z3.b }, { z24.b - z27.b }" + + - + input: + bytes: [ 0x01, 0x54, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w10, 1, vgx4], { z0.b - z3.b }, { z24.b - z27.b }" + + - + input: + bytes: [ 0x85, 0x16, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z20.b - z23.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x85, 0x16, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w8, 5, vgx4], { z20.b - z23.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x02, 0x75, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx4], { z8.b - z11.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x02, 0x75, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx4], { z8.b - z11.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x87, 0x35, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x87, 0x35, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.s[w9, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x00, 0x14, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x00, 0x14, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x45, 0x55, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x45, 0x55, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xa7, 0x75, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xa7, 0x75, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xe7, 0x77, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xe7, 0x77, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x25, 0x16, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x25, 0x16, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x14, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x21, 0x14, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x60, 0x56, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x60, 0x56, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x80, 0x15, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x80, 0x15, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x21, 0x54, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x21, 0x54, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xc5, 0x16, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xc5, 0x16, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x22, 0x75, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x22, 0x75, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x87, 0x35, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x87, 0x35, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x08, 0x80, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x08, 0x80, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x0d, 0xc5, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x0d, 0xc5, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x8f, 0xe5, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]" + + - + input: + bytes: [ 0x8f, 0xe5, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]" + + - + input: + bytes: [ 0x8f, 0xe7, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]" + + - + input: + bytes: [ 0x8f, 0xe7, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]" + + - + input: + bytes: [ 0x0d, 0x86, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]" + + - + input: + bytes: [ 0x0d, 0x86, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]" + + - + input: + bytes: [ 0x09, 0x84, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]" + + - + input: + bytes: [ 0x09, 0x84, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]" + + - + input: + bytes: [ 0x08, 0xc6, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x08, 0xc6, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x88, 0x81, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]" + + - + input: + bytes: [ 0x88, 0x81, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]" + + - + input: + bytes: [ 0x09, 0xc0, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]" + + - + input: + bytes: [ 0x09, 0xc0, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]" + + - + input: + bytes: [ 0x8d, 0x82, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]" + + - + input: + bytes: [ 0x8d, 0x82, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]" + + - + input: + bytes: [ 0x0a, 0xe5, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]" + + - + input: + bytes: [ 0x0a, 0xe5, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]" + + - + input: + bytes: [ 0x8f, 0xa1, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]" + + - + input: + bytes: [ 0x8f, 0xa1, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]" + + - + input: + bytes: [ 0x00, 0x14, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x00, 0x14, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x05, 0x55, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x05, 0x55, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x87, 0x75, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x87, 0x75, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x87, 0x77, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x87, 0x77, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x05, 0x16, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x05, 0x16, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x01, 0x14, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x01, 0x14, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x00, 0x56, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x00, 0x56, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x80, 0x15, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x80, 0x15, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x01, 0x54, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x01, 0x54, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x85, 0x16, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x85, 0x16, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x02, 0x75, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x02, 0x75, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x87, 0x35, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x87, 0x35, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sdot za.d[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2/sel.s.yaml b/tests/MC/AArch64/SME2/sel.s.yaml new file mode 100644 index 0000000000..ef347776bd --- /dev/null +++ b/tests/MC/AArch64/SME2/sel.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z0.h, z1.h }, pn8, { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x54, 0x95, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z20.h, z21.h }, pn13, { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x96, 0x8d, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z22.h, z23.h }, pn11, { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xde, 0x9f, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z30.h, z31.h }, pn15, { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x00, 0x80, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z0.s, z1.s }, pn8, { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x54, 0x95, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z20.s, z21.s }, pn13, { z10.s, z11.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x96, 0x8d, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z22.s, z23.s }, pn11, { z12.s, z13.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0xde, 0x9f, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z30.s, z31.s }, pn15, { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z0.d, z1.d }, pn8, { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x54, 0x95, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z20.d, z21.d }, pn13, { z10.d, z11.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x96, 0x8d, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z22.d, z23.d }, pn11, { z12.d, z13.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0xde, 0x9f, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z30.d, z31.d }, pn15, { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x00, 0x80, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z0.b, z1.b }, pn8, { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x54, 0x95, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z20.b, z21.b }, pn13, { z10.b, z11.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x96, 0x8d, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z22.b, z23.b }, pn11, { z12.b, z13.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0xde, 0x9f, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z30.b, z31.b }, pn15, { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x00, 0x80, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z0.h - z3.h }, pn8, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x14, 0x95, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z20.h - z23.h }, pn13, { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x94, 0x8d, 0x69, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z20.h - z23.h }, pn11, { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x9c, 0x9f, 0x7d, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z28.h - z31.h }, pn15, { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x00, 0x80, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z0.s - z3.s }, pn8, { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x14, 0x95, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z20.s - z23.s }, pn13, { z8.s - z11.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x94, 0x8d, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z20.s - z23.s }, pn11, { z12.s - z15.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x9c, 0x9f, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z28.s - z31.s }, pn15, { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x00, 0x80, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z0.d - z3.d }, pn8, { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x14, 0x95, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z20.d - z23.d }, pn13, { z8.d - z11.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x94, 0x8d, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z20.d - z23.d }, pn11, { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x9c, 0x9f, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z28.d - z31.d }, pn15, { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x00, 0x80, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x14, 0x95, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z20.b - z23.b }, pn13, { z8.b - z11.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x94, 0x8d, 0x29, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z20.b - z23.b }, pn11, { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x9c, 0x9f, 0x3d, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sel { z28.b - z31.b }, pn15, { z28.b - z31.b }, { z28.b - z31.b }" diff --git a/tests/MC/AArch64/SME2/smax.s.yaml b/tests/MC/AArch64/SME2/smax.s.yaml new file mode 100644 index 0000000000..e83c6e731c --- /dev/null +++ b/tests/MC/AArch64/SME2/smax.s.yaml @@ -0,0 +1,640 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z0.h, z1.h }, { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x14, 0xa0, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.h, z21.h }, { z20.h, z21.h }, z5.h" + + - + input: + bytes: [ 0x16, 0xa0, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z22.h, z23.h }, { z22.h, z23.h }, z8.h" + + - + input: + bytes: [ 0x1e, 0xa0, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z30.h, z31.h }, { z30.h, z31.h }, z15.h" + + - + input: + bytes: [ 0x00, 0xb0, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x14, 0xb0, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x16, 0xb0, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x1e, 0xb0, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x00, 0xa0, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z0.s, z1.s }, { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x14, 0xa0, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.s, z21.s }, { z20.s, z21.s }, z5.s" + + - + input: + bytes: [ 0x16, 0xa0, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z22.s, z23.s }, { z22.s, z23.s }, z8.s" + + - + input: + bytes: [ 0x1e, 0xa0, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z30.s, z31.s }, { z30.s, z31.s }, z15.s" + + - + input: + bytes: [ 0x00, 0xb0, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x14, 0xb0, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x16, 0xb0, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0x1e, 0xb0, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x00, 0xa0, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z0.d, z1.d }, { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x14, 0xa0, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.d, z21.d }, { z20.d, z21.d }, z5.d" + + - + input: + bytes: [ 0x16, 0xa0, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z22.d, z23.d }, { z22.d, z23.d }, z8.d" + + - + input: + bytes: [ 0x1e, 0xa0, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z30.d, z31.d }, { z30.d, z31.d }, z15.d" + + - + input: + bytes: [ 0x00, 0xb0, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x14, 0xb0, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x16, 0xb0, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0x1e, 0xb0, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x00, 0xa0, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z0.b, z1.b }, { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x14, 0xa0, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.b, z21.b }, { z20.b, z21.b }, z5.b" + + - + input: + bytes: [ 0x16, 0xa0, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z22.b, z23.b }, { z22.b, z23.b }, z8.b" + + - + input: + bytes: [ 0x1e, 0xa0, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z30.b, z31.b }, { z30.b, z31.b }, z15.b" + + - + input: + bytes: [ 0x00, 0xb0, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x14, 0xb0, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x16, 0xb0, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0x1e, 0xb0, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x00, 0xa8, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z0.h - z3.h }, { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x14, 0xa8, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.h - z23.h }, { z20.h - z23.h }, z5.h" + + - + input: + bytes: [ 0x14, 0xa8, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.h - z23.h }, { z20.h - z23.h }, z8.h" + + - + input: + bytes: [ 0x1c, 0xa8, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z28.h - z31.h }, { z28.h - z31.h }, z15.h" + + - + input: + bytes: [ 0x00, 0xb8, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x14, 0xb8, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x14, 0xb8, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x1c, 0xb8, 0x7c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x00, 0xa8, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z0.s - z3.s }, { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x14, 0xa8, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.s - z23.s }, { z20.s - z23.s }, z5.s" + + - + input: + bytes: [ 0x14, 0xa8, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.s - z23.s }, { z20.s - z23.s }, z8.s" + + - + input: + bytes: [ 0x1c, 0xa8, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z28.s - z31.s }, { z28.s - z31.s }, z15.s" + + - + input: + bytes: [ 0x00, 0xb8, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x14, 0xb8, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x14, 0xb8, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x1c, 0xb8, 0xbc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x00, 0xa8, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z0.d - z3.d }, { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x14, 0xa8, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.d - z23.d }, { z20.d - z23.d }, z5.d" + + - + input: + bytes: [ 0x14, 0xa8, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.d - z23.d }, { z20.d - z23.d }, z8.d" + + - + input: + bytes: [ 0x1c, 0xa8, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z28.d - z31.d }, { z28.d - z31.d }, z15.d" + + - + input: + bytes: [ 0x00, 0xb8, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x14, 0xb8, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x14, 0xb8, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x1c, 0xb8, 0xfc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x00, 0xa8, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z0.b - z3.b }, { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x14, 0xa8, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.b - z23.b }, { z20.b - z23.b }, z5.b" + + - + input: + bytes: [ 0x14, 0xa8, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.b - z23.b }, { z20.b - z23.b }, z8.b" + + - + input: + bytes: [ 0x1c, 0xa8, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z28.b - z31.b }, { z28.b - z31.b }, z15.b" + + - + input: + bytes: [ 0x00, 0xb8, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x14, 0xb8, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x14, 0xb8, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x1c, 0xb8, 0x3c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smax { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }" diff --git a/tests/MC/AArch64/SME2/smin.s.yaml b/tests/MC/AArch64/SME2/smin.s.yaml new file mode 100644 index 0000000000..0a14a8b486 --- /dev/null +++ b/tests/MC/AArch64/SME2/smin.s.yaml @@ -0,0 +1,640 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa0, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z0.h, z1.h }, { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x34, 0xa0, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.h, z21.h }, { z20.h, z21.h }, z5.h" + + - + input: + bytes: [ 0x36, 0xa0, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z22.h, z23.h }, { z22.h, z23.h }, z8.h" + + - + input: + bytes: [ 0x3e, 0xa0, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z30.h, z31.h }, { z30.h, z31.h }, z15.h" + + - + input: + bytes: [ 0x20, 0xb0, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x34, 0xb0, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x36, 0xb0, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x3e, 0xb0, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x20, 0xa0, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z0.s, z1.s }, { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x34, 0xa0, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.s, z21.s }, { z20.s, z21.s }, z5.s" + + - + input: + bytes: [ 0x36, 0xa0, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z22.s, z23.s }, { z22.s, z23.s }, z8.s" + + - + input: + bytes: [ 0x3e, 0xa0, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z30.s, z31.s }, { z30.s, z31.s }, z15.s" + + - + input: + bytes: [ 0x20, 0xb0, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x34, 0xb0, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x36, 0xb0, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0x3e, 0xb0, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x20, 0xa0, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z0.d, z1.d }, { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x34, 0xa0, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.d, z21.d }, { z20.d, z21.d }, z5.d" + + - + input: + bytes: [ 0x36, 0xa0, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z22.d, z23.d }, { z22.d, z23.d }, z8.d" + + - + input: + bytes: [ 0x3e, 0xa0, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z30.d, z31.d }, { z30.d, z31.d }, z15.d" + + - + input: + bytes: [ 0x20, 0xb0, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x34, 0xb0, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x36, 0xb0, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0x3e, 0xb0, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x20, 0xa0, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z0.b, z1.b }, { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x34, 0xa0, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.b, z21.b }, { z20.b, z21.b }, z5.b" + + - + input: + bytes: [ 0x36, 0xa0, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z22.b, z23.b }, { z22.b, z23.b }, z8.b" + + - + input: + bytes: [ 0x3e, 0xa0, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z30.b, z31.b }, { z30.b, z31.b }, z15.b" + + - + input: + bytes: [ 0x20, 0xb0, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x34, 0xb0, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x36, 0xb0, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0x3e, 0xb0, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x20, 0xa8, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z0.h - z3.h }, { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x34, 0xa8, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.h - z23.h }, { z20.h - z23.h }, z5.h" + + - + input: + bytes: [ 0x34, 0xa8, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.h - z23.h }, { z20.h - z23.h }, z8.h" + + - + input: + bytes: [ 0x3c, 0xa8, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z28.h - z31.h }, { z28.h - z31.h }, z15.h" + + - + input: + bytes: [ 0x20, 0xb8, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x34, 0xb8, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x34, 0xb8, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x3c, 0xb8, 0x7c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x20, 0xa8, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z0.s - z3.s }, { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x34, 0xa8, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.s - z23.s }, { z20.s - z23.s }, z5.s" + + - + input: + bytes: [ 0x34, 0xa8, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.s - z23.s }, { z20.s - z23.s }, z8.s" + + - + input: + bytes: [ 0x3c, 0xa8, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z28.s - z31.s }, { z28.s - z31.s }, z15.s" + + - + input: + bytes: [ 0x20, 0xb8, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x34, 0xb8, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x34, 0xb8, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x3c, 0xb8, 0xbc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x20, 0xa8, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z0.d - z3.d }, { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x34, 0xa8, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.d - z23.d }, { z20.d - z23.d }, z5.d" + + - + input: + bytes: [ 0x34, 0xa8, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.d - z23.d }, { z20.d - z23.d }, z8.d" + + - + input: + bytes: [ 0x3c, 0xa8, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z28.d - z31.d }, { z28.d - z31.d }, z15.d" + + - + input: + bytes: [ 0x20, 0xb8, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x34, 0xb8, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x34, 0xb8, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x3c, 0xb8, 0xfc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x20, 0xa8, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z0.b - z3.b }, { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x34, 0xa8, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.b - z23.b }, { z20.b - z23.b }, z5.b" + + - + input: + bytes: [ 0x34, 0xa8, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.b - z23.b }, { z20.b - z23.b }, z8.b" + + - + input: + bytes: [ 0x3c, 0xa8, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z28.b - z31.b }, { z28.b - z31.b }, z15.b" + + - + input: + bytes: [ 0x20, 0xb8, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x34, 0xb8, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x34, 0xb8, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x3c, 0xb8, 0x3c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smin { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }" diff --git a/tests/MC/AArch64/SME2/smlal.s.yaml b/tests/MC/AArch64/SME2/smlal.s.yaml new file mode 100644 index 0000000000..dabcedc503 --- /dev/null +++ b/tests/MC/AArch64/SME2/smlal.s.yaml @@ -0,0 +1,1680 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x0c, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1], z0.h, z0.h" + + - + input: + bytes: [ 0x45, 0x4d, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 10:11], z10.h, z5.h" + + - + input: + bytes: [ 0xa7, 0x6d, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 14:15], z13.h, z8.h" + + - + input: + bytes: [ 0xe7, 0x6f, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 14:15], z31.h, z15.h" + + - + input: + bytes: [ 0x25, 0x0e, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 10:11], z17.h, z0.h" + + - + input: + bytes: [ 0x21, 0x0c, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3], z1.h, z14.h" + + - + input: + bytes: [ 0x60, 0x4e, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 0:1], z19.h, z4.h" + + - + input: + bytes: [ 0x80, 0x0d, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1], z12.h, z2.h" + + - + input: + bytes: [ 0x21, 0x4c, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3], z1.h, z10.h" + + - + input: + bytes: [ 0xc5, 0x0e, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 10:11], z22.h, z14.h" + + - + input: + bytes: [ 0x22, 0x6d, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 4:5], z9.h, z1.h" + + - + input: + bytes: [ 0x87, 0x2d, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w9, 14:15], z12.h, z11.h" + + - + input: + bytes: [ 0x00, 0x10, 0xc0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1], z0.h, z0.h[0]" + + - + input: + bytes: [ 0x45, 0x55, 0xc5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 10:11], z10.h, z5.h[1]" + + - + input: + bytes: [ 0xa7, 0xfd, 0xc8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 14:15], z13.h, z8.h[7]" + + - + input: + bytes: [ 0xe7, 0xff, 0xcf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 14:15], z31.h, z15.h[7]" + + - + input: + bytes: [ 0x25, 0x1e, 0xc0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 10:11], z17.h, z0.h[3]" + + - + input: + bytes: [ 0x21, 0x94, 0xce, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3], z1.h, z14.h[5]" + + - + input: + bytes: [ 0x60, 0x56, 0xc4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 0:1], z19.h, z4.h[1]" + + - + input: + bytes: [ 0x80, 0x19, 0xc2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1], z12.h, z2.h[2]" + + - + input: + bytes: [ 0x21, 0xd8, 0xca, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3], z1.h, z10.h[6]" + + - + input: + bytes: [ 0xc5, 0x1a, 0xce, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 10:11], z22.h, z14.h[2]" + + - + input: + bytes: [ 0x22, 0xf5, 0xc1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 4:5], z9.h, z1.h[5]" + + - + input: + bytes: [ 0x87, 0xb9, 0xcb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w9, 14:15], z12.h, z11.h[6]" + + - + input: + bytes: [ 0x00, 0x08, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x00, 0x08, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x41, 0x49, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x41, 0x49, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xa3, 0x69, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xa3, 0x69, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xe3, 0x6b, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xe3, 0x6b, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x21, 0x0a, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x0a, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x08, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x21, 0x08, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x60, 0x4a, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x60, 0x4a, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x80, 0x09, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x80, 0x09, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x21, 0x48, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x21, 0x48, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xc1, 0x0a, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xc1, 0x0a, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x22, 0x69, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x22, 0x69, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x83, 0x29, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x83, 0x29, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x00, 0x10, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x00, 0x10, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x45, 0x55, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x45, 0x55, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x87, 0x7d, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0x87, 0x7d, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0xc7, 0x7f, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0xc7, 0x7f, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x05, 0x1e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]" + + - + input: + bytes: [ 0x05, 0x1e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]" + + - + input: + bytes: [ 0x01, 0x14, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x01, 0x14, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x40, 0x56, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x40, 0x56, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x80, 0x19, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x80, 0x19, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x01, 0x58, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0x01, 0x58, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0xc5, 0x1a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0xc5, 0x1a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x02, 0x75, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x02, 0x75, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x87, 0x39, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]" + + - + input: + bytes: [ 0x87, 0x39, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]" + + - + input: + bytes: [ 0x00, 0x08, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x00, 0x08, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x41, 0x49, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x41, 0x49, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x83, 0x69, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x83, 0x69, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xc3, 0x6b, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xc3, 0x6b, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x01, 0x0a, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x01, 0x0a, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x01, 0x08, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x01, 0x08, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x40, 0x4a, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x40, 0x4a, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x80, 0x09, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x80, 0x09, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x01, 0x48, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x01, 0x48, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xc1, 0x0a, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xc1, 0x0a, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x02, 0x69, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x02, 0x69, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x83, 0x29, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x83, 0x29, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x00, 0x08, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x00, 0x08, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x41, 0x49, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x41, 0x49, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xa3, 0x69, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xa3, 0x69, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xe3, 0x6b, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xe3, 0x6b, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x21, 0x0a, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x0a, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x08, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x21, 0x08, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x60, 0x4a, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x60, 0x4a, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x80, 0x09, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x80, 0x09, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x21, 0x48, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x21, 0x48, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xc1, 0x0a, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xc1, 0x0a, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x22, 0x69, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x22, 0x69, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x83, 0x29, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x83, 0x29, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x00, 0x90, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x00, 0x90, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x05, 0xd5, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x05, 0xd5, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x87, 0xfd, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x87, 0xfd, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x87, 0xff, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x87, 0xff, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x05, 0x9e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]" + + - + input: + bytes: [ 0x05, 0x9e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]" + + - + input: + bytes: [ 0x01, 0x94, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x01, 0x94, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x00, 0xd6, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x00, 0xd6, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x80, 0x99, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x80, 0x99, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x01, 0xd8, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x01, 0xd8, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x85, 0x9a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x85, 0x9a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x02, 0xf5, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x02, 0xf5, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x87, 0xb9, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]" + + - + input: + bytes: [ 0x87, 0xb9, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]" + + - + input: + bytes: [ 0x00, 0x08, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x00, 0x08, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x01, 0x49, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x01, 0x49, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x83, 0x69, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x83, 0x69, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x83, 0x6b, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x83, 0x6b, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x01, 0x0a, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x01, 0x0a, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x01, 0x08, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x01, 0x08, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x00, 0x4a, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x00, 0x4a, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x80, 0x09, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x80, 0x09, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x01, 0x48, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x01, 0x48, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x81, 0x0a, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x81, 0x0a, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x02, 0x69, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x02, 0x69, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x83, 0x29, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x83, 0x29, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2/smlall.s.yaml b/tests/MC/AArch64/SME2/smlall.s.yaml new file mode 100644 index 0000000000..af6de474f3 --- /dev/null +++ b/tests/MC/AArch64/SME2/smlall.s.yaml @@ -0,0 +1,3360 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x04, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3], z0.b, z0.b" + + - + input: + bytes: [ 0x41, 0x45, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7], z10.b, z5.b" + + - + input: + bytes: [ 0xa3, 0x65, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 12:15], z13.b, z8.b" + + - + input: + bytes: [ 0xe3, 0x67, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 12:15], z31.b, z15.b" + + - + input: + bytes: [ 0x21, 0x06, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7], z17.b, z0.b" + + - + input: + bytes: [ 0x21, 0x04, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7], z1.b, z14.b" + + - + input: + bytes: [ 0x60, 0x46, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 0:3], z19.b, z4.b" + + - + input: + bytes: [ 0x80, 0x05, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3], z12.b, z2.b" + + - + input: + bytes: [ 0x21, 0x44, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7], z1.b, z10.b" + + - + input: + bytes: [ 0xc1, 0x06, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7], z22.b, z14.b" + + - + input: + bytes: [ 0x22, 0x65, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 8:11], z9.b, z1.b" + + - + input: + bytes: [ 0x83, 0x25, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w9, 12:15], z12.b, z11.b" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3], z0.b, z0.b[0]" + + - + input: + bytes: [ 0x41, 0x55, 0x05, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7], z10.b, z5.b[5]" + + - + input: + bytes: [ 0xa3, 0xed, 0x08, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 12:15], z13.b, z8.b[11]" + + - + input: + bytes: [ 0xe3, 0xff, 0x0f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 12:15], z31.b, z15.b[15]" + + - + input: + bytes: [ 0x21, 0x0e, 0x00, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7], z17.b, z0.b[3]" + + - + input: + bytes: [ 0x21, 0x84, 0x0e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7], z1.b, z14.b[9]" + + - + input: + bytes: [ 0x60, 0x56, 0x04, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 0:3], z19.b, z4.b[5]" + + - + input: + bytes: [ 0x80, 0x19, 0x02, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3], z12.b, z2.b[6]" + + - + input: + bytes: [ 0x21, 0xc8, 0x0a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7], z1.b, z10.b[10]" + + - + input: + bytes: [ 0xc1, 0x0a, 0x0e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7], z22.b, z14.b[2]" + + - + input: + bytes: [ 0x22, 0xf5, 0x01, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 8:11], z9.b, z1.b[13]" + + - + input: + bytes: [ 0x83, 0xa9, 0x0b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w9, 12:15], z12.b, z11.b[10]" + + - + input: + bytes: [ 0x00, 0x04, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3], z0.h, z0.h" + + - + input: + bytes: [ 0x41, 0x45, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7], z10.h, z5.h" + + - + input: + bytes: [ 0xa3, 0x65, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 12:15], z13.h, z8.h" + + - + input: + bytes: [ 0xe3, 0x67, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 12:15], z31.h, z15.h" + + - + input: + bytes: [ 0x21, 0x06, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7], z17.h, z0.h" + + - + input: + bytes: [ 0x21, 0x04, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7], z1.h, z14.h" + + - + input: + bytes: [ 0x60, 0x46, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 0:3], z19.h, z4.h" + + - + input: + bytes: [ 0x80, 0x05, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3], z12.h, z2.h" + + - + input: + bytes: [ 0x21, 0x44, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7], z1.h, z10.h" + + - + input: + bytes: [ 0xc1, 0x06, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7], z22.h, z14.h" + + - + input: + bytes: [ 0x22, 0x65, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 8:11], z9.h, z1.h" + + - + input: + bytes: [ 0x83, 0x25, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w9, 12:15], z12.h, z11.h" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3], z0.h, z0.h[0]" + + - + input: + bytes: [ 0x41, 0x45, 0x85, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7], z10.h, z5.h[1]" + + - + input: + bytes: [ 0xa3, 0xed, 0x88, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 12:15], z13.h, z8.h[7]" + + - + input: + bytes: [ 0xe3, 0xef, 0x8f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 12:15], z31.h, z15.h[7]" + + - + input: + bytes: [ 0x21, 0x0e, 0x80, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7], z17.h, z0.h[3]" + + - + input: + bytes: [ 0x21, 0x84, 0x8e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7], z1.h, z14.h[5]" + + - + input: + bytes: [ 0x60, 0x46, 0x84, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 0:3], z19.h, z4.h[1]" + + - + input: + bytes: [ 0x80, 0x09, 0x82, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3], z12.h, z2.h[2]" + + - + input: + bytes: [ 0x21, 0xc8, 0x8a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7], z1.h, z10.h[6]" + + - + input: + bytes: [ 0xc1, 0x0a, 0x8e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7], z22.h, z14.h[2]" + + - + input: + bytes: [ 0x22, 0xe5, 0x81, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 8:11], z9.h, z1.h[5]" + + - + input: + bytes: [ 0x83, 0xa9, 0x8b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w9, 12:15], z12.h, z11.h[6]" + + - + input: + bytes: [ 0x00, 0x00, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x00, 0x00, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x41, 0x41, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0x41, 0x41, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0xa1, 0x61, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xa1, 0x61, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xe1, 0x63, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0xe1, 0x63, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0x21, 0x02, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x21, 0x02, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x21, 0x00, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x21, 0x00, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x60, 0x42, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 0:3, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x60, 0x42, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 0:3, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x80, 0x01, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x80, 0x01, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x21, 0x40, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0x21, 0x40, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0xc1, 0x02, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0xc1, 0x02, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0x20, 0x61, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 0:3, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x20, 0x61, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 0:3, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x81, 0x21, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x81, 0x21, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x00, 0x00, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x00, 0x00, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x45, 0x45, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x45, 0x45, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x87, 0x6d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]" + + - + input: + bytes: [ 0x87, 0x6d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]" + + - + input: + bytes: [ 0xc7, 0x6f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]" + + - + input: + bytes: [ 0xc7, 0x6f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]" + + - + input: + bytes: [ 0x05, 0x0e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]" + + - + input: + bytes: [ 0x05, 0x0e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]" + + - + input: + bytes: [ 0x01, 0x04, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]" + + - + input: + bytes: [ 0x01, 0x04, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]" + + - + input: + bytes: [ 0x40, 0x46, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x40, 0x46, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x80, 0x09, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]" + + - + input: + bytes: [ 0x80, 0x09, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]" + + - + input: + bytes: [ 0x01, 0x48, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]" + + - + input: + bytes: [ 0x01, 0x48, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]" + + - + input: + bytes: [ 0xc5, 0x0a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]" + + - + input: + bytes: [ 0xc5, 0x0a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]" + + - + input: + bytes: [ 0x02, 0x65, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]" + + - + input: + bytes: [ 0x02, 0x65, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]" + + - + input: + bytes: [ 0x87, 0x29, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]" + + - + input: + bytes: [ 0x87, 0x29, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]" + + - + input: + bytes: [ 0x00, 0x00, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x00, 0x00, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x41, 0x41, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x41, 0x41, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x81, 0x61, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0x81, 0x61, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0xc1, 0x63, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xc1, 0x63, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x01, 0x02, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }" + + - + input: + bytes: [ 0x01, 0x02, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }" + + - + input: + bytes: [ 0x01, 0x00, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x01, 0x00, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x40, 0x42, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x40, 0x42, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x80, 0x01, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }" + + - + input: + bytes: [ 0x80, 0x01, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }" + + - + input: + bytes: [ 0x01, 0x40, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }" + + - + input: + bytes: [ 0x01, 0x40, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }" + + - + input: + bytes: [ 0xc1, 0x02, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xc1, 0x02, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x00, 0x61, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x00, 0x61, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x81, 0x21, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }" + + - + input: + bytes: [ 0x81, 0x21, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }" + + - + input: + bytes: [ 0x00, 0x00, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x00, 0x00, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x41, 0x41, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x41, 0x41, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xa1, 0x61, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xa1, 0x61, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xe1, 0x63, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xe1, 0x63, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x21, 0x02, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x02, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x00, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x21, 0x00, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x60, 0x42, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 0:3, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x60, 0x42, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 0:3, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x80, 0x01, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x80, 0x01, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x21, 0x40, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x21, 0x40, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xc1, 0x02, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xc1, 0x02, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x20, 0x61, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 0:3, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x20, 0x61, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 0:3, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x81, 0x21, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x81, 0x21, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x00, 0x00, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x00, 0x00, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x45, 0x45, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h[6]" + + - + input: + bytes: [ 0x45, 0x45, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h[6]" + + - + input: + bytes: [ 0x87, 0x65, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0x87, 0x65, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0xc7, 0x67, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0xc7, 0x67, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x05, 0x06, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx2], { z16.h, z17.h }, z0.h[6]" + + - + input: + bytes: [ 0x05, 0x06, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx2], { z16.h, z17.h }, z0.h[6]" + + - + input: + bytes: [ 0x01, 0x04, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx2], { z0.h, z1.h }, z14.h[4]" + + - + input: + bytes: [ 0x01, 0x04, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx2], { z0.h, z1.h }, z14.h[4]" + + - + input: + bytes: [ 0x40, 0x46, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 0:3, vgx2], { z18.h, z19.h }, z4.h[4]" + + - + input: + bytes: [ 0x40, 0x46, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 0:3, vgx2], { z18.h, z19.h }, z4.h[4]" + + - + input: + bytes: [ 0x80, 0x01, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h[0]" + + - + input: + bytes: [ 0x80, 0x01, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h[0]" + + - + input: + bytes: [ 0x01, 0x40, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx2], { z0.h, z1.h }, z10.h[0]" + + - + input: + bytes: [ 0x01, 0x40, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx2], { z0.h, z1.h }, z10.h[0]" + + - + input: + bytes: [ 0xc5, 0x02, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0xc5, 0x02, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x02, 0x65, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 0:3, vgx2], { z8.h, z9.h }, z1.h[5]" + + - + input: + bytes: [ 0x02, 0x65, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 0:3, vgx2], { z8.h, z9.h }, z1.h[5]" + + - + input: + bytes: [ 0x87, 0x21, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h[3]" + + - + input: + bytes: [ 0x87, 0x21, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h[3]" + + - + input: + bytes: [ 0x00, 0x00, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x00, 0x00, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x41, 0x41, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x41, 0x41, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x81, 0x61, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x81, 0x61, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xc1, 0x63, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xc1, 0x63, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x01, 0x02, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x01, 0x02, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x01, 0x00, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x01, 0x00, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x40, 0x42, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 0:3, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x40, 0x42, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 0:3, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x80, 0x01, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x80, 0x01, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x01, 0x40, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x01, 0x40, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xc1, 0x02, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xc1, 0x02, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x00, 0x61, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 0:3, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x00, 0x61, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 0:3, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x81, 0x21, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x81, 0x21, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x00, 0x00, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x00, 0x00, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x41, 0x41, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0x41, 0x41, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0xa1, 0x61, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xa1, 0x61, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xe1, 0x63, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0xe1, 0x63, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0x21, 0x02, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x21, 0x02, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x21, 0x00, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x21, 0x00, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x60, 0x42, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 0:3, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x60, 0x42, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 0:3, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x80, 0x01, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x80, 0x01, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x21, 0x40, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0x21, 0x40, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0xc1, 0x02, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0xc1, 0x02, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0x20, 0x61, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 0:3, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x20, 0x61, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 0:3, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x81, 0x21, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x81, 0x21, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x00, 0x80, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x00, 0x80, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x05, 0xc5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x05, 0xc5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x87, 0xed, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]" + + - + input: + bytes: [ 0x87, 0xed, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]" + + - + input: + bytes: [ 0x87, 0xef, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]" + + - + input: + bytes: [ 0x87, 0xef, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]" + + - + input: + bytes: [ 0x05, 0x8e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]" + + - + input: + bytes: [ 0x05, 0x8e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]" + + - + input: + bytes: [ 0x01, 0x84, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]" + + - + input: + bytes: [ 0x01, 0x84, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]" + + - + input: + bytes: [ 0x00, 0xc6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x00, 0xc6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x80, 0x89, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]" + + - + input: + bytes: [ 0x80, 0x89, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]" + + - + input: + bytes: [ 0x01, 0xc8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]" + + - + input: + bytes: [ 0x01, 0xc8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]" + + - + input: + bytes: [ 0x85, 0x8a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]" + + - + input: + bytes: [ 0x85, 0x8a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]" + + - + input: + bytes: [ 0x02, 0xe5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]" + + - + input: + bytes: [ 0x02, 0xe5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]" + + - + input: + bytes: [ 0x87, 0xa9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]" + + - + input: + bytes: [ 0x87, 0xa9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]" + + - + input: + bytes: [ 0x00, 0x00, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x00, 0x00, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x01, 0x41, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x01, 0x41, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x81, 0x61, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x81, 0x61, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x81, 0x63, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x81, 0x63, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x01, 0x02, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }" + + - + input: + bytes: [ 0x01, 0x02, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }" + + - + input: + bytes: [ 0x01, 0x00, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x01, 0x00, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x00, 0x42, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x00, 0x42, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x80, 0x01, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x80, 0x01, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x01, 0x40, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }" + + - + input: + bytes: [ 0x01, 0x40, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }" + + - + input: + bytes: [ 0x81, 0x02, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x81, 0x02, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x00, 0x61, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x00, 0x61, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x81, 0x21, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x81, 0x21, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x00, 0x00, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x00, 0x00, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x41, 0x41, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x41, 0x41, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xa1, 0x61, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xa1, 0x61, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xe1, 0x63, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xe1, 0x63, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x21, 0x02, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x02, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x00, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x21, 0x00, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x60, 0x42, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 0:3, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x60, 0x42, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 0:3, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x80, 0x01, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x80, 0x01, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x21, 0x40, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x21, 0x40, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xc1, 0x02, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xc1, 0x02, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x20, 0x61, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 0:3, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x20, 0x61, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 0:3, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x81, 0x21, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x81, 0x21, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x00, 0x80, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x00, 0x80, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x05, 0xc5, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx4], { z8.h - z11.h }, z5.h[6]" + + - + input: + bytes: [ 0x05, 0xc5, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx4], { z8.h - z11.h }, z5.h[6]" + + - + input: + bytes: [ 0x87, 0xe5, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x87, 0xe5, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x87, 0xe7, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x87, 0xe7, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x05, 0x86, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx4], { z16.h - z19.h }, z0.h[6]" + + - + input: + bytes: [ 0x05, 0x86, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx4], { z16.h - z19.h }, z0.h[6]" + + - + input: + bytes: [ 0x01, 0x84, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx4], { z0.h - z3.h }, z14.h[4]" + + - + input: + bytes: [ 0x01, 0x84, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx4], { z0.h - z3.h }, z14.h[4]" + + - + input: + bytes: [ 0x00, 0xc6, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 0:3, vgx4], { z16.h - z19.h }, z4.h[4]" + + - + input: + bytes: [ 0x00, 0xc6, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 0:3, vgx4], { z16.h - z19.h }, z4.h[4]" + + - + input: + bytes: [ 0x80, 0x81, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h[0]" + + - + input: + bytes: [ 0x80, 0x81, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h[0]" + + - + input: + bytes: [ 0x01, 0xc0, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx4], { z0.h - z3.h }, z10.h[0]" + + - + input: + bytes: [ 0x01, 0xc0, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx4], { z0.h - z3.h }, z10.h[0]" + + - + input: + bytes: [ 0x85, 0x82, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx4], { z20.h - z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x85, 0x82, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx4], { z20.h - z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x02, 0xe5, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 0:3, vgx4], { z8.h - z11.h }, z1.h[5]" + + - + input: + bytes: [ 0x02, 0xe5, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 0:3, vgx4], { z8.h - z11.h }, z1.h[5]" + + - + input: + bytes: [ 0x87, 0xa1, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h[3]" + + - + input: + bytes: [ 0x87, 0xa1, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h[3]" + + - + input: + bytes: [ 0x00, 0x00, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x00, 0x00, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x01, 0x41, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x01, 0x41, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x81, 0x61, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x81, 0x61, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x81, 0x63, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x81, 0x63, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 4:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x01, 0x02, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x01, 0x02, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x01, 0x00, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x01, 0x00, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x00, 0x42, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 0:3, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x00, 0x42, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 0:3, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x80, 0x01, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x80, 0x01, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x01, 0x40, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x01, 0x40, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w10, 4:7, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x81, 0x02, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x81, 0x02, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w8, 4:7, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x00, 0x61, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 0:3, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x00, 0x61, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w11, 0:3, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x81, 0x21, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x81, 0x21, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2/smlsl.s.yaml b/tests/MC/AArch64/SME2/smlsl.s.yaml new file mode 100644 index 0000000000..8a4515b770 --- /dev/null +++ b/tests/MC/AArch64/SME2/smlsl.s.yaml @@ -0,0 +1,1680 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x0c, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1], z0.h, z0.h" + + - + input: + bytes: [ 0x4d, 0x4d, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 10:11], z10.h, z5.h" + + - + input: + bytes: [ 0xaf, 0x6d, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 14:15], z13.h, z8.h" + + - + input: + bytes: [ 0xef, 0x6f, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 14:15], z31.h, z15.h" + + - + input: + bytes: [ 0x2d, 0x0e, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 10:11], z17.h, z0.h" + + - + input: + bytes: [ 0x29, 0x0c, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3], z1.h, z14.h" + + - + input: + bytes: [ 0x68, 0x4e, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 0:1], z19.h, z4.h" + + - + input: + bytes: [ 0x88, 0x0d, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1], z12.h, z2.h" + + - + input: + bytes: [ 0x29, 0x4c, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3], z1.h, z10.h" + + - + input: + bytes: [ 0xcd, 0x0e, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 10:11], z22.h, z14.h" + + - + input: + bytes: [ 0x2a, 0x6d, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 4:5], z9.h, z1.h" + + - + input: + bytes: [ 0x8f, 0x2d, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w9, 14:15], z12.h, z11.h" + + - + input: + bytes: [ 0x08, 0x10, 0xc0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1], z0.h, z0.h[0]" + + - + input: + bytes: [ 0x4d, 0x55, 0xc5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 10:11], z10.h, z5.h[1]" + + - + input: + bytes: [ 0xaf, 0xfd, 0xc8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 14:15], z13.h, z8.h[7]" + + - + input: + bytes: [ 0xef, 0xff, 0xcf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 14:15], z31.h, z15.h[7]" + + - + input: + bytes: [ 0x2d, 0x1e, 0xc0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 10:11], z17.h, z0.h[3]" + + - + input: + bytes: [ 0x29, 0x94, 0xce, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3], z1.h, z14.h[5]" + + - + input: + bytes: [ 0x68, 0x56, 0xc4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 0:1], z19.h, z4.h[1]" + + - + input: + bytes: [ 0x88, 0x19, 0xc2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1], z12.h, z2.h[2]" + + - + input: + bytes: [ 0x29, 0xd8, 0xca, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3], z1.h, z10.h[6]" + + - + input: + bytes: [ 0xcd, 0x1a, 0xce, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 10:11], z22.h, z14.h[2]" + + - + input: + bytes: [ 0x2a, 0xf5, 0xc1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 4:5], z9.h, z1.h[5]" + + - + input: + bytes: [ 0x8f, 0xb9, 0xcb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w9, 14:15], z12.h, z11.h[6]" + + - + input: + bytes: [ 0x08, 0x08, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x08, 0x08, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x49, 0x49, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x49, 0x49, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xab, 0x69, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xab, 0x69, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xeb, 0x6b, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xeb, 0x6b, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x29, 0x0a, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x29, 0x0a, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x29, 0x08, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x29, 0x08, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x68, 0x4a, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x68, 0x4a, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x88, 0x09, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x88, 0x09, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x29, 0x48, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x29, 0x48, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xc9, 0x0a, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xc9, 0x0a, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x2a, 0x69, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x2a, 0x69, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x8b, 0x29, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x8b, 0x29, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x08, 0x10, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x08, 0x10, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x4d, 0x55, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x4d, 0x55, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x8f, 0x7d, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0x8f, 0x7d, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0xcf, 0x7f, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0xcf, 0x7f, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x0d, 0x1e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]" + + - + input: + bytes: [ 0x0d, 0x1e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]" + + - + input: + bytes: [ 0x09, 0x14, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x09, 0x14, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x48, 0x56, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x48, 0x56, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x88, 0x19, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x88, 0x19, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x09, 0x58, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0x09, 0x58, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0xcd, 0x1a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0xcd, 0x1a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x0a, 0x75, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x0a, 0x75, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x8f, 0x39, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]" + + - + input: + bytes: [ 0x8f, 0x39, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]" + + - + input: + bytes: [ 0x08, 0x08, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x08, 0x08, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x49, 0x49, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x49, 0x49, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x8b, 0x69, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x8b, 0x69, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xcb, 0x6b, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xcb, 0x6b, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x09, 0x0a, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x09, 0x0a, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x09, 0x08, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x09, 0x08, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x48, 0x4a, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x48, 0x4a, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x88, 0x09, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x88, 0x09, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x09, 0x48, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x09, 0x48, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xc9, 0x0a, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xc9, 0x0a, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x0a, 0x69, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x0a, 0x69, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x8b, 0x29, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x8b, 0x29, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x08, 0x08, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x08, 0x08, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x49, 0x49, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x49, 0x49, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xab, 0x69, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xab, 0x69, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xeb, 0x6b, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xeb, 0x6b, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x29, 0x0a, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x29, 0x0a, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x29, 0x08, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x29, 0x08, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x68, 0x4a, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x68, 0x4a, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x88, 0x09, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x88, 0x09, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x29, 0x48, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x29, 0x48, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xc9, 0x0a, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xc9, 0x0a, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x2a, 0x69, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x2a, 0x69, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x8b, 0x29, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x8b, 0x29, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x08, 0x90, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x08, 0x90, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x0d, 0xd5, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x0d, 0xd5, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x8f, 0xfd, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x8f, 0xfd, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x8f, 0xff, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x8f, 0xff, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x0d, 0x9e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]" + + - + input: + bytes: [ 0x0d, 0x9e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]" + + - + input: + bytes: [ 0x09, 0x94, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x09, 0x94, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x08, 0xd6, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x08, 0xd6, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x88, 0x99, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x88, 0x99, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x09, 0xd8, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x09, 0xd8, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x8d, 0x9a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x8d, 0x9a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x0a, 0xf5, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x0a, 0xf5, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x8f, 0xb9, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]" + + - + input: + bytes: [ 0x8f, 0xb9, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]" + + - + input: + bytes: [ 0x08, 0x08, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x08, 0x08, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x09, 0x49, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x09, 0x49, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x8b, 0x69, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x8b, 0x69, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x8b, 0x6b, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x8b, 0x6b, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x09, 0x0a, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x09, 0x0a, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x09, 0x08, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x09, 0x08, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x08, 0x4a, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x08, 0x4a, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x88, 0x09, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x88, 0x09, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x09, 0x48, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x09, 0x48, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x89, 0x0a, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x89, 0x0a, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x0a, 0x69, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x0a, 0x69, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x8b, 0x29, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x8b, 0x29, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2/smlsll.s.yaml b/tests/MC/AArch64/SME2/smlsll.s.yaml new file mode 100644 index 0000000000..01b900310e --- /dev/null +++ b/tests/MC/AArch64/SME2/smlsll.s.yaml @@ -0,0 +1,3360 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x04, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3], z0.b, z0.b" + + - + input: + bytes: [ 0x49, 0x45, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7], z10.b, z5.b" + + - + input: + bytes: [ 0xab, 0x65, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 12:15], z13.b, z8.b" + + - + input: + bytes: [ 0xeb, 0x67, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 12:15], z31.b, z15.b" + + - + input: + bytes: [ 0x29, 0x06, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7], z17.b, z0.b" + + - + input: + bytes: [ 0x29, 0x04, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7], z1.b, z14.b" + + - + input: + bytes: [ 0x68, 0x46, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 0:3], z19.b, z4.b" + + - + input: + bytes: [ 0x88, 0x05, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3], z12.b, z2.b" + + - + input: + bytes: [ 0x29, 0x44, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7], z1.b, z10.b" + + - + input: + bytes: [ 0xc9, 0x06, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7], z22.b, z14.b" + + - + input: + bytes: [ 0x2a, 0x65, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 8:11], z9.b, z1.b" + + - + input: + bytes: [ 0x8b, 0x25, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w9, 12:15], z12.b, z11.b" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3], z0.b, z0.b[0]" + + - + input: + bytes: [ 0x49, 0x55, 0x05, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7], z10.b, z5.b[5]" + + - + input: + bytes: [ 0xab, 0xed, 0x08, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 12:15], z13.b, z8.b[11]" + + - + input: + bytes: [ 0xeb, 0xff, 0x0f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 12:15], z31.b, z15.b[15]" + + - + input: + bytes: [ 0x29, 0x0e, 0x00, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7], z17.b, z0.b[3]" + + - + input: + bytes: [ 0x29, 0x84, 0x0e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7], z1.b, z14.b[9]" + + - + input: + bytes: [ 0x68, 0x56, 0x04, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 0:3], z19.b, z4.b[5]" + + - + input: + bytes: [ 0x88, 0x19, 0x02, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3], z12.b, z2.b[6]" + + - + input: + bytes: [ 0x29, 0xc8, 0x0a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7], z1.b, z10.b[10]" + + - + input: + bytes: [ 0xc9, 0x0a, 0x0e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7], z22.b, z14.b[2]" + + - + input: + bytes: [ 0x2a, 0xf5, 0x01, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 8:11], z9.b, z1.b[13]" + + - + input: + bytes: [ 0x8b, 0xa9, 0x0b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w9, 12:15], z12.b, z11.b[10]" + + - + input: + bytes: [ 0x08, 0x04, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3], z0.h, z0.h" + + - + input: + bytes: [ 0x49, 0x45, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7], z10.h, z5.h" + + - + input: + bytes: [ 0xab, 0x65, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 12:15], z13.h, z8.h" + + - + input: + bytes: [ 0xeb, 0x67, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 12:15], z31.h, z15.h" + + - + input: + bytes: [ 0x29, 0x06, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7], z17.h, z0.h" + + - + input: + bytes: [ 0x29, 0x04, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7], z1.h, z14.h" + + - + input: + bytes: [ 0x68, 0x46, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 0:3], z19.h, z4.h" + + - + input: + bytes: [ 0x88, 0x05, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3], z12.h, z2.h" + + - + input: + bytes: [ 0x29, 0x44, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7], z1.h, z10.h" + + - + input: + bytes: [ 0xc9, 0x06, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7], z22.h, z14.h" + + - + input: + bytes: [ 0x2a, 0x65, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 8:11], z9.h, z1.h" + + - + input: + bytes: [ 0x8b, 0x25, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w9, 12:15], z12.h, z11.h" + + - + input: + bytes: [ 0x08, 0x00, 0x80, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3], z0.h, z0.h[0]" + + - + input: + bytes: [ 0x49, 0x45, 0x85, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7], z10.h, z5.h[1]" + + - + input: + bytes: [ 0xab, 0xed, 0x88, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 12:15], z13.h, z8.h[7]" + + - + input: + bytes: [ 0xeb, 0xef, 0x8f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 12:15], z31.h, z15.h[7]" + + - + input: + bytes: [ 0x29, 0x0e, 0x80, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7], z17.h, z0.h[3]" + + - + input: + bytes: [ 0x29, 0x84, 0x8e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7], z1.h, z14.h[5]" + + - + input: + bytes: [ 0x68, 0x46, 0x84, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 0:3], z19.h, z4.h[1]" + + - + input: + bytes: [ 0x88, 0x09, 0x82, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3], z12.h, z2.h[2]" + + - + input: + bytes: [ 0x29, 0xc8, 0x8a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7], z1.h, z10.h[6]" + + - + input: + bytes: [ 0xc9, 0x0a, 0x8e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7], z22.h, z14.h[2]" + + - + input: + bytes: [ 0x2a, 0xe5, 0x81, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 8:11], z9.h, z1.h[5]" + + - + input: + bytes: [ 0x8b, 0xa9, 0x8b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w9, 12:15], z12.h, z11.h[6]" + + - + input: + bytes: [ 0x08, 0x00, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x08, 0x00, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x49, 0x41, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0x49, 0x41, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0xa9, 0x61, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xa9, 0x61, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xe9, 0x63, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0xe9, 0x63, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0x29, 0x02, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x29, 0x02, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x29, 0x00, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x29, 0x00, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x68, 0x42, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 0:3, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x68, 0x42, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 0:3, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x88, 0x01, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x88, 0x01, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x29, 0x40, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0x29, 0x40, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0xc9, 0x02, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0xc9, 0x02, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0x28, 0x61, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 0:3, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x28, 0x61, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 0:3, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x89, 0x21, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x89, 0x21, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x08, 0x00, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x08, 0x00, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x4d, 0x45, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x4d, 0x45, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x8f, 0x6d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]" + + - + input: + bytes: [ 0x8f, 0x6d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]" + + - + input: + bytes: [ 0xcf, 0x6f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]" + + - + input: + bytes: [ 0xcf, 0x6f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]" + + - + input: + bytes: [ 0x0d, 0x0e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]" + + - + input: + bytes: [ 0x0d, 0x0e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]" + + - + input: + bytes: [ 0x09, 0x04, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]" + + - + input: + bytes: [ 0x09, 0x04, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]" + + - + input: + bytes: [ 0x48, 0x46, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x48, 0x46, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x88, 0x09, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]" + + - + input: + bytes: [ 0x88, 0x09, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]" + + - + input: + bytes: [ 0x09, 0x48, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]" + + - + input: + bytes: [ 0x09, 0x48, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]" + + - + input: + bytes: [ 0xcd, 0x0a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]" + + - + input: + bytes: [ 0xcd, 0x0a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]" + + - + input: + bytes: [ 0x0a, 0x65, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]" + + - + input: + bytes: [ 0x0a, 0x65, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]" + + - + input: + bytes: [ 0x8f, 0x29, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]" + + - + input: + bytes: [ 0x8f, 0x29, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]" + + - + input: + bytes: [ 0x08, 0x00, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x08, 0x00, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x49, 0x41, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x49, 0x41, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x89, 0x61, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0x89, 0x61, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0xc9, 0x63, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xc9, 0x63, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x09, 0x02, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }" + + - + input: + bytes: [ 0x09, 0x02, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }" + + - + input: + bytes: [ 0x09, 0x00, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x09, 0x00, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x48, 0x42, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x48, 0x42, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x88, 0x01, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }" + + - + input: + bytes: [ 0x88, 0x01, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }" + + - + input: + bytes: [ 0x09, 0x40, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }" + + - + input: + bytes: [ 0x09, 0x40, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }" + + - + input: + bytes: [ 0xc9, 0x02, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xc9, 0x02, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x08, 0x61, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x08, 0x61, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x89, 0x21, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }" + + - + input: + bytes: [ 0x89, 0x21, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }" + + - + input: + bytes: [ 0x08, 0x00, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x08, 0x00, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x49, 0x41, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x49, 0x41, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xa9, 0x61, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xa9, 0x61, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xe9, 0x63, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xe9, 0x63, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x29, 0x02, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x29, 0x02, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x29, 0x00, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x29, 0x00, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x68, 0x42, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 0:3, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x68, 0x42, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 0:3, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x88, 0x01, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x88, 0x01, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x29, 0x40, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x29, 0x40, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xc9, 0x02, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xc9, 0x02, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x28, 0x61, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 0:3, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x28, 0x61, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 0:3, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x89, 0x21, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x89, 0x21, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x08, 0x00, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x08, 0x00, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x4d, 0x45, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h[6]" + + - + input: + bytes: [ 0x4d, 0x45, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h[6]" + + - + input: + bytes: [ 0x8f, 0x65, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0x8f, 0x65, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0xcf, 0x67, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0xcf, 0x67, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x0d, 0x06, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx2], { z16.h, z17.h }, z0.h[6]" + + - + input: + bytes: [ 0x0d, 0x06, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx2], { z16.h, z17.h }, z0.h[6]" + + - + input: + bytes: [ 0x09, 0x04, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx2], { z0.h, z1.h }, z14.h[4]" + + - + input: + bytes: [ 0x09, 0x04, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx2], { z0.h, z1.h }, z14.h[4]" + + - + input: + bytes: [ 0x48, 0x46, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 0:3, vgx2], { z18.h, z19.h }, z4.h[4]" + + - + input: + bytes: [ 0x48, 0x46, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 0:3, vgx2], { z18.h, z19.h }, z4.h[4]" + + - + input: + bytes: [ 0x88, 0x01, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h[0]" + + - + input: + bytes: [ 0x88, 0x01, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h[0]" + + - + input: + bytes: [ 0x09, 0x40, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx2], { z0.h, z1.h }, z10.h[0]" + + - + input: + bytes: [ 0x09, 0x40, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx2], { z0.h, z1.h }, z10.h[0]" + + - + input: + bytes: [ 0xcd, 0x02, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0xcd, 0x02, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x0a, 0x65, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 0:3, vgx2], { z8.h, z9.h }, z1.h[5]" + + - + input: + bytes: [ 0x0a, 0x65, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 0:3, vgx2], { z8.h, z9.h }, z1.h[5]" + + - + input: + bytes: [ 0x8f, 0x21, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h[3]" + + - + input: + bytes: [ 0x8f, 0x21, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h[3]" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x49, 0x41, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x49, 0x41, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x89, 0x61, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x89, 0x61, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xc9, 0x63, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xc9, 0x63, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x09, 0x02, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x09, 0x02, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x09, 0x00, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x09, 0x00, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x48, 0x42, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 0:3, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x48, 0x42, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 0:3, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x88, 0x01, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x88, 0x01, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x09, 0x40, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x09, 0x40, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xc9, 0x02, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xc9, 0x02, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x08, 0x61, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 0:3, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x08, 0x61, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 0:3, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x89, 0x21, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x89, 0x21, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x08, 0x00, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x08, 0x00, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x49, 0x41, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0x49, 0x41, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0xa9, 0x61, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xa9, 0x61, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xe9, 0x63, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0xe9, 0x63, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0x29, 0x02, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x29, 0x02, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x29, 0x00, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x29, 0x00, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x68, 0x42, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 0:3, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x68, 0x42, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 0:3, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x88, 0x01, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x88, 0x01, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x29, 0x40, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0x29, 0x40, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0xc9, 0x02, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0xc9, 0x02, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0x28, 0x61, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 0:3, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x28, 0x61, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 0:3, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x89, 0x21, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x89, 0x21, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x08, 0x80, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x08, 0x80, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x0d, 0xc5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x0d, 0xc5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x8f, 0xed, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]" + + - + input: + bytes: [ 0x8f, 0xed, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]" + + - + input: + bytes: [ 0x8f, 0xef, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]" + + - + input: + bytes: [ 0x8f, 0xef, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]" + + - + input: + bytes: [ 0x0d, 0x8e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]" + + - + input: + bytes: [ 0x0d, 0x8e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]" + + - + input: + bytes: [ 0x09, 0x84, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]" + + - + input: + bytes: [ 0x09, 0x84, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]" + + - + input: + bytes: [ 0x08, 0xc6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x08, 0xc6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x88, 0x89, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]" + + - + input: + bytes: [ 0x88, 0x89, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]" + + - + input: + bytes: [ 0x09, 0xc8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]" + + - + input: + bytes: [ 0x09, 0xc8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]" + + - + input: + bytes: [ 0x8d, 0x8a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]" + + - + input: + bytes: [ 0x8d, 0x8a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]" + + - + input: + bytes: [ 0x0a, 0xe5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]" + + - + input: + bytes: [ 0x0a, 0xe5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]" + + - + input: + bytes: [ 0x8f, 0xa9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]" + + - + input: + bytes: [ 0x8f, 0xa9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]" + + - + input: + bytes: [ 0x08, 0x00, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x08, 0x00, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x09, 0x41, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x09, 0x41, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x89, 0x61, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x89, 0x61, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x89, 0x63, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x89, 0x63, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x09, 0x02, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }" + + - + input: + bytes: [ 0x09, 0x02, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }" + + - + input: + bytes: [ 0x09, 0x00, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x09, 0x00, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x08, 0x42, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x08, 0x42, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x88, 0x01, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x88, 0x01, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x09, 0x40, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }" + + - + input: + bytes: [ 0x09, 0x40, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }" + + - + input: + bytes: [ 0x89, 0x02, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x89, 0x02, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x08, 0x61, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x08, 0x61, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x89, 0x21, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x89, 0x21, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x08, 0x00, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x08, 0x00, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x49, 0x41, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x49, 0x41, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xa9, 0x61, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xa9, 0x61, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xe9, 0x63, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xe9, 0x63, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x29, 0x02, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x29, 0x02, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x29, 0x00, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x29, 0x00, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x68, 0x42, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 0:3, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x68, 0x42, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 0:3, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x88, 0x01, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x88, 0x01, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x29, 0x40, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x29, 0x40, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xc9, 0x02, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xc9, 0x02, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x28, 0x61, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 0:3, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x28, 0x61, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 0:3, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x89, 0x21, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x89, 0x21, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x08, 0x80, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x08, 0x80, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x0d, 0xc5, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx4], { z8.h - z11.h }, z5.h[6]" + + - + input: + bytes: [ 0x0d, 0xc5, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx4], { z8.h - z11.h }, z5.h[6]" + + - + input: + bytes: [ 0x8f, 0xe5, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x8f, 0xe5, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x8f, 0xe7, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x8f, 0xe7, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x0d, 0x86, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx4], { z16.h - z19.h }, z0.h[6]" + + - + input: + bytes: [ 0x0d, 0x86, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx4], { z16.h - z19.h }, z0.h[6]" + + - + input: + bytes: [ 0x09, 0x84, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx4], { z0.h - z3.h }, z14.h[4]" + + - + input: + bytes: [ 0x09, 0x84, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx4], { z0.h - z3.h }, z14.h[4]" + + - + input: + bytes: [ 0x08, 0xc6, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 0:3, vgx4], { z16.h - z19.h }, z4.h[4]" + + - + input: + bytes: [ 0x08, 0xc6, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 0:3, vgx4], { z16.h - z19.h }, z4.h[4]" + + - + input: + bytes: [ 0x88, 0x81, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h[0]" + + - + input: + bytes: [ 0x88, 0x81, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h[0]" + + - + input: + bytes: [ 0x09, 0xc0, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx4], { z0.h - z3.h }, z10.h[0]" + + - + input: + bytes: [ 0x09, 0xc0, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx4], { z0.h - z3.h }, z10.h[0]" + + - + input: + bytes: [ 0x8d, 0x82, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx4], { z20.h - z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x8d, 0x82, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx4], { z20.h - z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x0a, 0xe5, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 0:3, vgx4], { z8.h - z11.h }, z1.h[5]" + + - + input: + bytes: [ 0x0a, 0xe5, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 0:3, vgx4], { z8.h - z11.h }, z1.h[5]" + + - + input: + bytes: [ 0x8f, 0xa1, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h[3]" + + - + input: + bytes: [ 0x8f, 0xa1, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h[3]" + + - + input: + bytes: [ 0x08, 0x00, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x08, 0x00, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x09, 0x41, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x09, 0x41, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x89, 0x61, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x89, 0x61, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x89, 0x63, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x89, 0x63, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 4:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x09, 0x02, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x09, 0x02, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x09, 0x00, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x09, 0x00, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x08, 0x42, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 0:3, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x08, 0x42, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 0:3, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x88, 0x01, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x88, 0x01, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x09, 0x40, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x09, 0x40, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w10, 4:7, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x89, 0x02, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x89, 0x02, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w8, 4:7, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x08, 0x61, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 0:3, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x08, 0x61, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w11, 0:3, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x89, 0x21, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x89, 0x21, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "smlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2/smopa.s.yaml b/tests/MC/AArch64/SME2/smopa.s.yaml new file mode 100644 index 0000000000..692bc9523c --- /dev/null +++ b/tests/MC/AArch64/SME2/smopa.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x00, 0x80, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smopa za0.s, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x49, 0x55, 0x95, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smopa za1.s, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xab, 0xed, 0x88, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smopa za3.s, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xeb, 0xff, 0x9f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smopa za3.s, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x29, 0x0e, 0x90, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smopa za1.s, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x29, 0x84, 0x9e, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smopa za1.s, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x68, 0x56, 0x94, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smopa za0.s, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x88, 0x19, 0x82, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smopa za0.s, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x29, 0xc8, 0x9a, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smopa za1.s, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xc9, 0x0a, 0x9e, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smopa za1.s, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x2a, 0xf5, 0x81, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smopa za2.s, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x8b, 0xa9, 0x8b, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smopa za3.s, p2/m, p5/m, z12.h, z11.h" diff --git a/tests/MC/AArch64/SME2/smops.s.yaml b/tests/MC/AArch64/SME2/smops.s.yaml new file mode 100644 index 0000000000..7f649bfbfa --- /dev/null +++ b/tests/MC/AArch64/SME2/smops.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x00, 0x80, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smops za0.s, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x59, 0x55, 0x95, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smops za1.s, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xbb, 0xed, 0x88, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smops za3.s, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xfb, 0xff, 0x9f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smops za3.s, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x39, 0x0e, 0x90, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smops za1.s, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x39, 0x84, 0x9e, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smops za1.s, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x78, 0x56, 0x94, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smops za0.s, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x98, 0x19, 0x82, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smops za0.s, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x39, 0xc8, 0x9a, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smops za1.s, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xd9, 0x0a, 0x9e, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smops za1.s, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x3a, 0xf5, 0x81, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smops za2.s, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x9b, 0xa9, 0x8b, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "smops za3.s, p2/m, p5/m, z12.h, z11.h" diff --git a/tests/MC/AArch64/SME2/sqcvt.s.yaml b/tests/MC/AArch64/SME2/sqcvt.s.yaml new file mode 100644 index 0000000000..f27729306c --- /dev/null +++ b/tests/MC/AArch64/SME2/sqcvt.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x23, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvt z0.h, { z0.s, z1.s }" + + - + input: + bytes: [ 0x55, 0xe1, 0x23, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvt z21.h, { z10.s, z11.s }" + + - + input: + bytes: [ 0x97, 0xe1, 0x23, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvt z23.h, { z12.s, z13.s }" + + - + input: + bytes: [ 0xdf, 0xe3, 0x23, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvt z31.h, { z30.s, z31.s }" + + - + input: + bytes: [ 0x00, 0xe0, 0x33, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvt z0.b, { z0.s - z3.s }" + + - + input: + bytes: [ 0x15, 0xe1, 0x33, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvt z21.b, { z8.s - z11.s }" + + - + input: + bytes: [ 0x97, 0xe1, 0x33, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvt z23.b, { z12.s - z15.s }" + + - + input: + bytes: [ 0x9f, 0xe3, 0x33, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvt z31.b, { z28.s - z31.s }" + + - + input: + bytes: [ 0x00, 0xe0, 0xb3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvt z0.h, { z0.d - z3.d }" + + - + input: + bytes: [ 0x15, 0xe1, 0xb3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvt z21.h, { z8.d - z11.d }" + + - + input: + bytes: [ 0x97, 0xe1, 0xb3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvt z23.h, { z12.d - z15.d }" + + - + input: + bytes: [ 0x9f, 0xe3, 0xb3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvt z31.h, { z28.d - z31.d }" diff --git a/tests/MC/AArch64/SME2/sqcvtn.s.yaml b/tests/MC/AArch64/SME2/sqcvtn.s.yaml new file mode 100644 index 0000000000..3643e7f2e5 --- /dev/null +++ b/tests/MC/AArch64/SME2/sqcvtn.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x40, 0xe0, 0x33, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtn z0.b, { z0.s - z3.s }" + + - + input: + bytes: [ 0x55, 0xe1, 0x33, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtn z21.b, { z8.s - z11.s }" + + - + input: + bytes: [ 0xd7, 0xe1, 0x33, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtn z23.b, { z12.s - z15.s }" + + - + input: + bytes: [ 0xdf, 0xe3, 0x33, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtn z31.b, { z28.s - z31.s }" + + - + input: + bytes: [ 0x40, 0xe0, 0xb3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtn z0.h, { z0.d - z3.d }" + + - + input: + bytes: [ 0x55, 0xe1, 0xb3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtn z21.h, { z8.d - z11.d }" + + - + input: + bytes: [ 0xd7, 0xe1, 0xb3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtn z23.h, { z12.d - z15.d }" + + - + input: + bytes: [ 0xdf, 0xe3, 0xb3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtn z31.h, { z28.d - z31.d }" diff --git a/tests/MC/AArch64/SME2/sqcvtu.s.yaml b/tests/MC/AArch64/SME2/sqcvtu.s.yaml new file mode 100644 index 0000000000..f5b6d03d69 --- /dev/null +++ b/tests/MC/AArch64/SME2/sqcvtu.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x63, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtu z0.h, { z0.s, z1.s }" + + - + input: + bytes: [ 0x55, 0xe1, 0x63, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtu z21.h, { z10.s, z11.s }" + + - + input: + bytes: [ 0x97, 0xe1, 0x63, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtu z23.h, { z12.s, z13.s }" + + - + input: + bytes: [ 0xdf, 0xe3, 0x63, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtu z31.h, { z30.s, z31.s }" + + - + input: + bytes: [ 0x00, 0xe0, 0x73, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtu z0.b, { z0.s - z3.s }" + + - + input: + bytes: [ 0x15, 0xe1, 0x73, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtu z21.b, { z8.s - z11.s }" + + - + input: + bytes: [ 0x97, 0xe1, 0x73, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtu z23.b, { z12.s - z15.s }" + + - + input: + bytes: [ 0x9f, 0xe3, 0x73, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtu z31.b, { z28.s - z31.s }" + + - + input: + bytes: [ 0x00, 0xe0, 0xf3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtu z0.h, { z0.d - z3.d }" + + - + input: + bytes: [ 0x15, 0xe1, 0xf3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtu z21.h, { z8.d - z11.d }" + + - + input: + bytes: [ 0x97, 0xe1, 0xf3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtu z23.h, { z12.d - z15.d }" + + - + input: + bytes: [ 0x9f, 0xe3, 0xf3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtu z31.h, { z28.d - z31.d }" diff --git a/tests/MC/AArch64/SME2/sqcvtun.s.yaml b/tests/MC/AArch64/SME2/sqcvtun.s.yaml new file mode 100644 index 0000000000..0de86e9364 --- /dev/null +++ b/tests/MC/AArch64/SME2/sqcvtun.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x40, 0xe0, 0x73, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtun z0.b, { z0.s - z3.s }" + + - + input: + bytes: [ 0x55, 0xe1, 0x73, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtun z21.b, { z8.s - z11.s }" + + - + input: + bytes: [ 0xd7, 0xe1, 0x73, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtun z23.b, { z12.s - z15.s }" + + - + input: + bytes: [ 0xdf, 0xe3, 0x73, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtun z31.b, { z28.s - z31.s }" + + - + input: + bytes: [ 0x40, 0xe0, 0xf3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtun z0.h, { z0.d - z3.d }" + + - + input: + bytes: [ 0x55, 0xe1, 0xf3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtun z21.h, { z8.d - z11.d }" + + - + input: + bytes: [ 0xd7, 0xe1, 0xf3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtun z23.h, { z12.d - z15.d }" + + - + input: + bytes: [ 0xdf, 0xe3, 0xf3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtun z31.h, { z28.d - z31.d }" diff --git a/tests/MC/AArch64/SME2/sqdmulh.s.yaml b/tests/MC/AArch64/SME2/sqdmulh.s.yaml new file mode 100644 index 0000000000..a6dc4165e4 --- /dev/null +++ b/tests/MC/AArch64/SME2/sqdmulh.s.yaml @@ -0,0 +1,640 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa4, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z0.h, z1.h }, { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x14, 0xa4, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.h, z21.h }, { z20.h, z21.h }, z5.h" + + - + input: + bytes: [ 0x16, 0xa4, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z22.h, z23.h }, { z22.h, z23.h }, z8.h" + + - + input: + bytes: [ 0x1e, 0xa4, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z30.h, z31.h }, { z30.h, z31.h }, z15.h" + + - + input: + bytes: [ 0x00, 0xb4, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x14, 0xb4, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x16, 0xb4, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x1e, 0xb4, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x00, 0xa4, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z0.s, z1.s }, { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x14, 0xa4, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.s, z21.s }, { z20.s, z21.s }, z5.s" + + - + input: + bytes: [ 0x16, 0xa4, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z22.s, z23.s }, { z22.s, z23.s }, z8.s" + + - + input: + bytes: [ 0x1e, 0xa4, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z30.s, z31.s }, { z30.s, z31.s }, z15.s" + + - + input: + bytes: [ 0x00, 0xb4, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x14, 0xb4, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x16, 0xb4, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0x1e, 0xb4, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x00, 0xa4, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z0.d, z1.d }, { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x14, 0xa4, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.d, z21.d }, { z20.d, z21.d }, z5.d" + + - + input: + bytes: [ 0x16, 0xa4, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z22.d, z23.d }, { z22.d, z23.d }, z8.d" + + - + input: + bytes: [ 0x1e, 0xa4, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z30.d, z31.d }, { z30.d, z31.d }, z15.d" + + - + input: + bytes: [ 0x00, 0xb4, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x14, 0xb4, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x16, 0xb4, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0x1e, 0xb4, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x00, 0xa4, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z0.b, z1.b }, { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x14, 0xa4, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.b, z21.b }, { z20.b, z21.b }, z5.b" + + - + input: + bytes: [ 0x16, 0xa4, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z22.b, z23.b }, { z22.b, z23.b }, z8.b" + + - + input: + bytes: [ 0x1e, 0xa4, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z30.b, z31.b }, { z30.b, z31.b }, z15.b" + + - + input: + bytes: [ 0x00, 0xb4, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x14, 0xb4, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x16, 0xb4, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0x1e, 0xb4, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x00, 0xac, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z0.h - z3.h }, { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x14, 0xac, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.h - z23.h }, { z20.h - z23.h }, z5.h" + + - + input: + bytes: [ 0x14, 0xac, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.h - z23.h }, { z20.h - z23.h }, z8.h" + + - + input: + bytes: [ 0x1c, 0xac, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z28.h - z31.h }, { z28.h - z31.h }, z15.h" + + - + input: + bytes: [ 0x00, 0xbc, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x14, 0xbc, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x14, 0xbc, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x1c, 0xbc, 0x7c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x00, 0xac, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z0.s - z3.s }, { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x14, 0xac, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.s - z23.s }, { z20.s - z23.s }, z5.s" + + - + input: + bytes: [ 0x14, 0xac, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.s - z23.s }, { z20.s - z23.s }, z8.s" + + - + input: + bytes: [ 0x1c, 0xac, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z28.s - z31.s }, { z28.s - z31.s }, z15.s" + + - + input: + bytes: [ 0x00, 0xbc, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x14, 0xbc, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x14, 0xbc, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x1c, 0xbc, 0xbc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x00, 0xac, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z0.d - z3.d }, { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x14, 0xac, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.d - z23.d }, { z20.d - z23.d }, z5.d" + + - + input: + bytes: [ 0x14, 0xac, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.d - z23.d }, { z20.d - z23.d }, z8.d" + + - + input: + bytes: [ 0x1c, 0xac, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z28.d - z31.d }, { z28.d - z31.d }, z15.d" + + - + input: + bytes: [ 0x00, 0xbc, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x14, 0xbc, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x14, 0xbc, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x1c, 0xbc, 0xfc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x00, 0xac, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z0.b - z3.b }, { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x14, 0xac, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, z5.b" + + - + input: + bytes: [ 0x14, 0xac, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, z8.b" + + - + input: + bytes: [ 0x1c, 0xac, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z28.b - z31.b }, { z28.b - z31.b }, z15.b" + + - + input: + bytes: [ 0x00, 0xbc, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x14, 0xbc, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x14, 0xbc, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x1c, 0xbc, 0x3c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqdmulh { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }" diff --git a/tests/MC/AArch64/SME2/sqrshr.s.yaml b/tests/MC/AArch64/SME2/sqrshr.s.yaml new file mode 100644 index 0000000000..44bde4f57c --- /dev/null +++ b/tests/MC/AArch64/SME2/sqrshr.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xd4, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshr z0.h, { z0.s, z1.s }, #16" + + - + input: + bytes: [ 0x55, 0xd5, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshr z21.h, { z10.s, z11.s }, #11" + + - + input: + bytes: [ 0x97, 0xd5, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshr z23.h, { z12.s, z13.s }, #8" + + - + input: + bytes: [ 0xdf, 0xd7, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshr z31.h, { z30.s, z31.s }, #1" + + - + input: + bytes: [ 0x00, 0xd8, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshr z0.b, { z0.s - z3.s }, #32" + + - + input: + bytes: [ 0x15, 0xd9, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshr z21.b, { z8.s - z11.s }, #11" + + - + input: + bytes: [ 0x97, 0xd9, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshr z23.b, { z12.s - z15.s }, #24" + + - + input: + bytes: [ 0x9f, 0xdb, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshr z31.b, { z28.s - z31.s }, #1" + + - + input: + bytes: [ 0x00, 0xd8, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshr z0.h, { z0.d - z3.d }, #64" + + - + input: + bytes: [ 0x15, 0xd9, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshr z21.h, { z8.d - z11.d }, #11" + + - + input: + bytes: [ 0x97, 0xd9, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshr z23.h, { z12.d - z15.d }, #24" + + - + input: + bytes: [ 0x9f, 0xdb, 0xff, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshr z31.h, { z28.d - z31.d }, #1" diff --git a/tests/MC/AArch64/SME2/sqrshrn.s.yaml b/tests/MC/AArch64/SME2/sqrshrn.s.yaml new file mode 100644 index 0000000000..02799062f9 --- /dev/null +++ b/tests/MC/AArch64/SME2/sqrshrn.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xdc, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrn z0.b, { z0.s - z3.s }, #32" + + - + input: + bytes: [ 0x15, 0xdd, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrn z21.b, { z8.s - z11.s }, #11" + + - + input: + bytes: [ 0x97, 0xdd, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrn z23.b, { z12.s - z15.s }, #24" + + - + input: + bytes: [ 0x9f, 0xdf, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrn z31.b, { z28.s - z31.s }, #1" + + - + input: + bytes: [ 0x00, 0xdc, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrn z0.h, { z0.d - z3.d }, #64" + + - + input: + bytes: [ 0x15, 0xdd, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrn z21.h, { z8.d - z11.d }, #11" + + - + input: + bytes: [ 0x97, 0xdd, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrn z23.h, { z12.d - z15.d }, #24" + + - + input: + bytes: [ 0x9f, 0xdf, 0xff, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrn z31.h, { z28.d - z31.d }, #1" diff --git a/tests/MC/AArch64/SME2/sqrshru.s.yaml b/tests/MC/AArch64/SME2/sqrshru.s.yaml new file mode 100644 index 0000000000..3ef2d30566 --- /dev/null +++ b/tests/MC/AArch64/SME2/sqrshru.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xd4, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshru z0.h, { z0.s, z1.s }, #16" + + - + input: + bytes: [ 0x55, 0xd5, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshru z21.h, { z10.s, z11.s }, #11" + + - + input: + bytes: [ 0x97, 0xd5, 0xf8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshru z23.h, { z12.s, z13.s }, #8" + + - + input: + bytes: [ 0xdf, 0xd7, 0xff, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshru z31.h, { z30.s, z31.s }, #1" + + - + input: + bytes: [ 0x40, 0xd8, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshru z0.b, { z0.s - z3.s }, #32" + + - + input: + bytes: [ 0x55, 0xd9, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshru z21.b, { z8.s - z11.s }, #11" + + - + input: + bytes: [ 0xd7, 0xd9, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshru z23.b, { z12.s - z15.s }, #24" + + - + input: + bytes: [ 0xdf, 0xdb, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshru z31.b, { z28.s - z31.s }, #1" + + - + input: + bytes: [ 0x40, 0xd8, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshru z0.h, { z0.d - z3.d }, #64" + + - + input: + bytes: [ 0x55, 0xd9, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshru z21.h, { z8.d - z11.d }, #11" + + - + input: + bytes: [ 0xd7, 0xd9, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshru z23.h, { z12.d - z15.d }, #24" + + - + input: + bytes: [ 0xdf, 0xdb, 0xff, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshru z31.h, { z28.d - z31.d }, #1" diff --git a/tests/MC/AArch64/SME2/sqrshrun.s.yaml b/tests/MC/AArch64/SME2/sqrshrun.s.yaml new file mode 100644 index 0000000000..fb734ad5d2 --- /dev/null +++ b/tests/MC/AArch64/SME2/sqrshrun.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x40, 0xdc, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrun z0.b, { z0.s - z3.s }, #32" + + - + input: + bytes: [ 0x55, 0xdd, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrun z21.b, { z8.s - z11.s }, #11" + + - + input: + bytes: [ 0xd7, 0xdd, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrun z23.b, { z12.s - z15.s }, #24" + + - + input: + bytes: [ 0xdf, 0xdf, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrun z31.b, { z28.s - z31.s }, #1" + + - + input: + bytes: [ 0x40, 0xdc, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrun z0.h, { z0.d - z3.d }, #64" + + - + input: + bytes: [ 0x55, 0xdd, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrun z21.h, { z8.d - z11.d }, #11" + + - + input: + bytes: [ 0xd7, 0xdd, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrun z23.h, { z12.d - z15.d }, #24" + + - + input: + bytes: [ 0xdf, 0xdf, 0xff, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrun z31.h, { z28.d - z31.d }, #1" diff --git a/tests/MC/AArch64/SME2/srshl.s.yaml b/tests/MC/AArch64/SME2/srshl.s.yaml new file mode 100644 index 0000000000..d240f149df --- /dev/null +++ b/tests/MC/AArch64/SME2/srshl.s.yaml @@ -0,0 +1,640 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa2, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z0.h, z1.h }, { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x34, 0xa2, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.h, z21.h }, { z20.h, z21.h }, z5.h" + + - + input: + bytes: [ 0x36, 0xa2, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z22.h, z23.h }, { z22.h, z23.h }, z8.h" + + - + input: + bytes: [ 0x3e, 0xa2, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z30.h, z31.h }, { z30.h, z31.h }, z15.h" + + - + input: + bytes: [ 0x20, 0xb2, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x34, 0xb2, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x36, 0xb2, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x3e, 0xb2, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x20, 0xa2, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z0.s, z1.s }, { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x34, 0xa2, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.s, z21.s }, { z20.s, z21.s }, z5.s" + + - + input: + bytes: [ 0x36, 0xa2, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z22.s, z23.s }, { z22.s, z23.s }, z8.s" + + - + input: + bytes: [ 0x3e, 0xa2, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z30.s, z31.s }, { z30.s, z31.s }, z15.s" + + - + input: + bytes: [ 0x20, 0xb2, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x34, 0xb2, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x36, 0xb2, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0x3e, 0xb2, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x20, 0xa2, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z0.d, z1.d }, { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x34, 0xa2, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.d, z21.d }, { z20.d, z21.d }, z5.d" + + - + input: + bytes: [ 0x36, 0xa2, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z22.d, z23.d }, { z22.d, z23.d }, z8.d" + + - + input: + bytes: [ 0x3e, 0xa2, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z30.d, z31.d }, { z30.d, z31.d }, z15.d" + + - + input: + bytes: [ 0x20, 0xb2, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x34, 0xb2, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x36, 0xb2, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0x3e, 0xb2, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x20, 0xa2, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z0.b, z1.b }, { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x34, 0xa2, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.b, z21.b }, { z20.b, z21.b }, z5.b" + + - + input: + bytes: [ 0x36, 0xa2, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z22.b, z23.b }, { z22.b, z23.b }, z8.b" + + - + input: + bytes: [ 0x3e, 0xa2, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z30.b, z31.b }, { z30.b, z31.b }, z15.b" + + - + input: + bytes: [ 0x20, 0xb2, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x34, 0xb2, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x36, 0xb2, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0x3e, 0xb2, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x20, 0xaa, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z0.h - z3.h }, { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x34, 0xaa, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.h - z23.h }, { z20.h - z23.h }, z5.h" + + - + input: + bytes: [ 0x34, 0xaa, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.h - z23.h }, { z20.h - z23.h }, z8.h" + + - + input: + bytes: [ 0x3c, 0xaa, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z28.h - z31.h }, { z28.h - z31.h }, z15.h" + + - + input: + bytes: [ 0x20, 0xba, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x34, 0xba, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x34, 0xba, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x3c, 0xba, 0x7c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x20, 0xaa, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z0.s - z3.s }, { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x34, 0xaa, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.s - z23.s }, { z20.s - z23.s }, z5.s" + + - + input: + bytes: [ 0x34, 0xaa, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.s - z23.s }, { z20.s - z23.s }, z8.s" + + - + input: + bytes: [ 0x3c, 0xaa, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z28.s - z31.s }, { z28.s - z31.s }, z15.s" + + - + input: + bytes: [ 0x20, 0xba, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x34, 0xba, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x34, 0xba, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x3c, 0xba, 0xbc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x20, 0xaa, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z0.d - z3.d }, { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x34, 0xaa, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.d - z23.d }, { z20.d - z23.d }, z5.d" + + - + input: + bytes: [ 0x34, 0xaa, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.d - z23.d }, { z20.d - z23.d }, z8.d" + + - + input: + bytes: [ 0x3c, 0xaa, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z28.d - z31.d }, { z28.d - z31.d }, z15.d" + + - + input: + bytes: [ 0x20, 0xba, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x34, 0xba, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x34, 0xba, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x3c, 0xba, 0xfc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x20, 0xaa, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z0.b - z3.b }, { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x34, 0xaa, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.b - z23.b }, { z20.b - z23.b }, z5.b" + + - + input: + bytes: [ 0x34, 0xaa, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.b - z23.b }, { z20.b - z23.b }, z8.b" + + - + input: + bytes: [ 0x3c, 0xaa, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z28.b - z31.b }, { z28.b - z31.b }, z15.b" + + - + input: + bytes: [ 0x20, 0xba, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x34, 0xba, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x34, 0xba, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x3c, 0xba, 0x3c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "srshl { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }" diff --git a/tests/MC/AArch64/SME2/st1b.s.yaml b/tests/MC/AArch64/SME2/st1b.s.yaml new file mode 100644 index 0000000000..0bd3aaac38 --- /dev/null +++ b/tests/MC/AArch64/SME2/st1b.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x20, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z0.b, z8.b }, pn8, [x0, x0]" + + - + input: + bytes: [ 0x55, 0x15, 0x35, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z21.b, z29.b }, pn13, [x10, x21]" + + - + input: + bytes: [ 0xb7, 0x0d, 0x28, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z23.b, z31.b }, pn11, [x13, x8]" + + - + input: + bytes: [ 0xf7, 0x1f, 0x3f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z23.b, z31.b }, pn15, [sp, xzr]" + + - + input: + bytes: [ 0x00, 0x00, 0x60, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z0.b, z8.b }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0x15, 0x65, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z21.b, z29.b }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x0d, 0x68, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z23.b, z31.b }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xf7, 0x1f, 0x6f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z23.b, z31.b }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0x80, 0x20, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x0]" + + - + input: + bytes: [ 0x51, 0x95, 0x35, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, x21]" + + - + input: + bytes: [ 0xb3, 0x8d, 0x28, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, x8]" + + - + input: + bytes: [ 0xf3, 0x9f, 0x3f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, xzr]" + + - + input: + bytes: [ 0x00, 0x80, 0x60, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0]" + + - + input: + bytes: [ 0x51, 0x95, 0x65, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb3, 0x8d, 0x68, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xf3, 0x9f, 0x6f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SME2/st1d.s.yaml b/tests/MC/AArch64/SME2/st1d.s.yaml new file mode 100644 index 0000000000..c19ccf1877 --- /dev/null +++ b/tests/MC/AArch64/SME2/st1d.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0x20, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z0.d, z8.d }, pn8, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x55, 0x75, 0x35, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z21.d, z29.d }, pn13, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x28, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z23.d, z31.d }, pn11, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xf7, 0x7f, 0x3f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z23.d, z31.d }, pn15, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z0.d, z8.d }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0x75, 0x65, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z21.d, z29.d }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x68, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z23.d, z31.d }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xf7, 0x7f, 0x6f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z23.d, z31.d }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x51, 0xf5, 0x35, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb3, 0xed, 0x28, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xf3, 0xff, 0x3f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0]" + + - + input: + bytes: [ 0x51, 0xf5, 0x65, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb3, 0xed, 0x68, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xf3, 0xff, 0x6f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SME2/st1h.s.yaml b/tests/MC/AArch64/SME2/st1h.s.yaml new file mode 100644 index 0000000000..17421ee431 --- /dev/null +++ b/tests/MC/AArch64/SME2/st1h.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x20, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z0.h, z8.h }, pn8, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x55, 0x35, 0x35, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z21.h, z29.h }, pn13, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x28, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z23.h, z31.h }, pn11, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xf7, 0x3f, 0x3f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z23.h, z31.h }, pn15, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x00, 0x20, 0x60, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z0.h, z8.h }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0x35, 0x65, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z21.h, z29.h }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x68, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z23.h, z31.h }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xf7, 0x3f, 0x6f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z23.h, z31.h }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0xa0, 0x20, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x51, 0xb5, 0x35, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb3, 0xad, 0x28, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xf3, 0xbf, 0x3f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x00, 0xa0, 0x60, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0]" + + - + input: + bytes: [ 0x51, 0xb5, 0x65, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb3, 0xad, 0x68, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xf3, 0xbf, 0x6f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SME2/st1w.s.yaml b/tests/MC/AArch64/SME2/st1w.s.yaml new file mode 100644 index 0000000000..8fce0399e5 --- /dev/null +++ b/tests/MC/AArch64/SME2/st1w.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0x20, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z0.s, z8.s }, pn8, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x55, 0x55, 0x35, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z21.s, z29.s }, pn13, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x28, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z23.s, z31.s }, pn11, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xf7, 0x5f, 0x3f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z23.s, z31.s }, pn15, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x00, 0x40, 0x60, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z0.s, z8.s }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0x55, 0x65, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z21.s, z29.s }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x68, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z23.s, z31.s }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xf7, 0x5f, 0x6f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z23.s, z31.s }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x20, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x51, 0xd5, 0x35, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb3, 0xcd, 0x28, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xf3, 0xdf, 0x3f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x00, 0xc0, 0x60, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0]" + + - + input: + bytes: [ 0x51, 0xd5, 0x65, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb3, 0xcd, 0x68, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xf3, 0xdf, 0x6f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SME2/stnt1b.s.yaml b/tests/MC/AArch64/SME2/stnt1b.s.yaml new file mode 100644 index 0000000000..8c8263553b --- /dev/null +++ b/tests/MC/AArch64/SME2/stnt1b.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x00, 0x20, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z0.b, z8.b }, pn8, [x0, x0]" + + - + input: + bytes: [ 0x5d, 0x15, 0x35, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z21.b, z29.b }, pn13, [x10, x21]" + + - + input: + bytes: [ 0xbf, 0x0d, 0x28, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z23.b, z31.b }, pn11, [x13, x8]" + + - + input: + bytes: [ 0xff, 0x1f, 0x3f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z23.b, z31.b }, pn15, [sp, xzr]" + + - + input: + bytes: [ 0x08, 0x00, 0x60, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z0.b, z8.b }, pn8, [x0]" + + - + input: + bytes: [ 0x5d, 0x15, 0x65, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z21.b, z29.b }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xbf, 0x0d, 0x68, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z23.b, z31.b }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x1f, 0x6f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z23.b, z31.b }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x08, 0x80, 0x20, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x0]" + + - + input: + bytes: [ 0x59, 0x95, 0x35, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, x21]" + + - + input: + bytes: [ 0xbb, 0x8d, 0x28, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, x8]" + + - + input: + bytes: [ 0xfb, 0x9f, 0x3f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, xzr]" + + - + input: + bytes: [ 0x08, 0x80, 0x60, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0]" + + - + input: + bytes: [ 0x59, 0x95, 0x65, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xbb, 0x8d, 0x68, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfb, 0x9f, 0x6f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SME2/stnt1d.s.yaml b/tests/MC/AArch64/SME2/stnt1d.s.yaml new file mode 100644 index 0000000000..9b8589da86 --- /dev/null +++ b/tests/MC/AArch64/SME2/stnt1d.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x60, 0x20, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d, z8.d }, pn8, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x5d, 0x75, 0x35, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z21.d, z29.d }, pn13, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xbf, 0x6d, 0x28, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z23.d, z31.d }, pn11, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xff, 0x7f, 0x3f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z23.d, z31.d }, pn15, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x08, 0x60, 0x60, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d, z8.d }, pn8, [x0]" + + - + input: + bytes: [ 0x5d, 0x75, 0x65, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z21.d, z29.d }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xbf, 0x6d, 0x68, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z23.d, z31.d }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x7f, 0x6f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z23.d, z31.d }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x08, 0xe0, 0x20, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x59, 0xf5, 0x35, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xbb, 0xed, 0x28, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xfb, 0xff, 0x3f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x08, 0xe0, 0x60, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0]" + + - + input: + bytes: [ 0x59, 0xf5, 0x65, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xbb, 0xed, 0x68, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfb, 0xff, 0x6f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SME2/stnt1h.s.yaml b/tests/MC/AArch64/SME2/stnt1h.s.yaml new file mode 100644 index 0000000000..be809be3a9 --- /dev/null +++ b/tests/MC/AArch64/SME2/stnt1h.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x20, 0x20, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z0.h, z8.h }, pn8, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x5d, 0x35, 0x35, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z21.h, z29.h }, pn13, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xbf, 0x2d, 0x28, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z23.h, z31.h }, pn11, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xff, 0x3f, 0x3f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z23.h, z31.h }, pn15, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x08, 0x20, 0x60, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z0.h, z8.h }, pn8, [x0]" + + - + input: + bytes: [ 0x5d, 0x35, 0x65, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z21.h, z29.h }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xbf, 0x2d, 0x68, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z23.h, z31.h }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x3f, 0x6f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z23.h, z31.h }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x08, 0xa0, 0x20, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x59, 0xb5, 0x35, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xbb, 0xad, 0x28, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xfb, 0xbf, 0x3f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x08, 0xa0, 0x60, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0]" + + - + input: + bytes: [ 0x59, 0xb5, 0x65, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xbb, 0xad, 0x68, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfb, 0xbf, 0x6f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SME2/stnt1w.s.yaml b/tests/MC/AArch64/SME2/stnt1w.s.yaml new file mode 100644 index 0000000000..80324e9989 --- /dev/null +++ b/tests/MC/AArch64/SME2/stnt1w.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x40, 0x20, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s, z8.s }, pn8, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x5d, 0x55, 0x35, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z21.s, z29.s }, pn13, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xbf, 0x4d, 0x28, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z23.s, z31.s }, pn11, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xff, 0x5f, 0x3f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z23.s, z31.s }, pn15, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x08, 0x40, 0x60, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s, z8.s }, pn8, [x0]" + + - + input: + bytes: [ 0x5d, 0x55, 0x65, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z21.s, z29.s }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xbf, 0x4d, 0x68, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z23.s, z31.s }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x5f, 0x6f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z23.s, z31.s }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x08, 0xc0, 0x20, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x59, 0xd5, 0x35, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xbb, 0xcd, 0x28, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xfb, 0xdf, 0x3f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x08, 0xc0, 0x60, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0]" + + - + input: + bytes: [ 0x59, 0xd5, 0x65, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xbb, 0xcd, 0x68, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfb, 0xdf, 0x6f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SME2/str.s.yaml b/tests/MC/AArch64/SME2/str.s.yaml new file mode 100644 index 0000000000..b840c73047 --- /dev/null +++ b/tests/MC/AArch64/SME2/str.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x3f, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "str zt0, [x0]" + + - + input: + bytes: [ 0x40, 0x81, 0x3f, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "str zt0, [x10]" + + - + input: + bytes: [ 0xa0, 0x81, 0x3f, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "str zt0, [x13]" + + - + input: + bytes: [ 0xe0, 0x83, 0x3f, 0xe1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "str zt0, [sp]" diff --git a/tests/MC/AArch64/SME2/sub.s.yaml b/tests/MC/AArch64/SME2/sub.s.yaml new file mode 100644 index 0000000000..75bc549d29 --- /dev/null +++ b/tests/MC/AArch64/SME2/sub.s.yaml @@ -0,0 +1,2880 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x1c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x18, 0x1c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x5d, 0x5d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 5, vgx2], { z10.s, z11.s }" + + - + input: + bytes: [ 0x5d, 0x5d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 5, vgx2], { z10.s, z11.s }" + + - + input: + bytes: [ 0x9f, 0x7d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0x9f, 0x7d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0xdf, 0x7f, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx2], { z30.s, z31.s }" + + - + input: + bytes: [ 0xdf, 0x7f, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx2], { z30.s, z31.s }" + + - + input: + bytes: [ 0x1d, 0x1e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx2], { z16.s, z17.s }" + + - + input: + bytes: [ 0x1d, 0x1e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx2], { z16.s, z17.s }" + + - + input: + bytes: [ 0x19, 0x1c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 1, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x19, 0x1c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 1, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x58, 0x5e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 0, vgx2], { z18.s, z19.s }" + + - + input: + bytes: [ 0x58, 0x5e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 0, vgx2], { z18.s, z19.s }" + + - + input: + bytes: [ 0x98, 0x1d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0x98, 0x1d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0x19, 0x5c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 1, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0x19, 0x5c, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 1, vgx2], { z0.s, z1.s }" + + - + input: + bytes: [ 0xdd, 0x1e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx2], { z22.s, z23.s }" + + - + input: + bytes: [ 0xdd, 0x1e, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx2], { z22.s, z23.s }" + + - + input: + bytes: [ 0x1a, 0x7d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 2, vgx2], { z8.s, z9.s }" + + - + input: + bytes: [ 0x1a, 0x7d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 2, vgx2], { z8.s, z9.s }" + + - + input: + bytes: [ 0x9f, 0x3d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w9, 7, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0x9f, 0x3d, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w9, 7, vgx2], { z12.s, z13.s }" + + - + input: + bytes: [ 0x18, 0x18, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x18, 0x18, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x5d, 0x59, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s" + + - + input: + bytes: [ 0x5d, 0x59, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s" + + - + input: + bytes: [ 0xbf, 0x79, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx2], { z13.s, z14.s }, z8.s" + + - + input: + bytes: [ 0xbf, 0x79, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx2], { z13.s, z14.s }, z8.s" + + - + input: + bytes: [ 0xff, 0x7b, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx2], { z31.s, z0.s }, z15.s" + + - + input: + bytes: [ 0xff, 0x7b, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx2], { z31.s, z0.s }, z15.s" + + - + input: + bytes: [ 0x3d, 0x1a, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx2], { z17.s, z18.s }, z0.s" + + - + input: + bytes: [ 0x3d, 0x1a, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx2], { z17.s, z18.s }, z0.s" + + - + input: + bytes: [ 0x39, 0x18, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 1, vgx2], { z1.s, z2.s }, z14.s" + + - + input: + bytes: [ 0x39, 0x18, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 1, vgx2], { z1.s, z2.s }, z14.s" + + - + input: + bytes: [ 0x78, 0x5a, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 0, vgx2], { z19.s, z20.s }, z4.s" + + - + input: + bytes: [ 0x78, 0x5a, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 0, vgx2], { z19.s, z20.s }, z4.s" + + - + input: + bytes: [ 0x98, 0x19, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s" + + - + input: + bytes: [ 0x98, 0x19, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s" + + - + input: + bytes: [ 0x39, 0x58, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 1, vgx2], { z1.s, z2.s }, z10.s" + + - + input: + bytes: [ 0x39, 0x58, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 1, vgx2], { z1.s, z2.s }, z10.s" + + - + input: + bytes: [ 0xdd, 0x1a, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s" + + - + input: + bytes: [ 0xdd, 0x1a, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s" + + - + input: + bytes: [ 0x3a, 0x79, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 2, vgx2], { z9.s, z10.s }, z1.s" + + - + input: + bytes: [ 0x3a, 0x79, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 2, vgx2], { z9.s, z10.s }, z1.s" + + - + input: + bytes: [ 0x9f, 0x39, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s" + + - + input: + bytes: [ 0x9f, 0x39, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s" + + - + input: + bytes: [ 0x18, 0x18, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x18, 0x18, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x5d, 0x59, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x5d, 0x59, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x9f, 0x79, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0x9f, 0x79, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0xdf, 0x7b, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0xdf, 0x7b, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x1d, 0x1a, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }" + + - + input: + bytes: [ 0x1d, 0x1a, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }" + + - + input: + bytes: [ 0x19, 0x18, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x19, 0x18, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x58, 0x5a, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x58, 0x5a, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x98, 0x19, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }" + + - + input: + bytes: [ 0x98, 0x19, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }" + + - + input: + bytes: [ 0x19, 0x58, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }" + + - + input: + bytes: [ 0x19, 0x58, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }" + + - + input: + bytes: [ 0xdd, 0x1a, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0xdd, 0x1a, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x1a, 0x79, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x1a, 0x79, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x9f, 0x39, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }" + + - + input: + bytes: [ 0x9f, 0x39, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }" + + - + input: + bytes: [ 0x18, 0x1c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x18, 0x1c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x5d, 0x5d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 5, vgx2], { z10.d, z11.d }" + + - + input: + bytes: [ 0x5d, 0x5d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 5, vgx2], { z10.d, z11.d }" + + - + input: + bytes: [ 0x9f, 0x7d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x9f, 0x7d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0xdf, 0x7f, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx2], { z30.d, z31.d }" + + - + input: + bytes: [ 0xdf, 0x7f, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx2], { z30.d, z31.d }" + + - + input: + bytes: [ 0x1d, 0x1e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx2], { z16.d, z17.d }" + + - + input: + bytes: [ 0x1d, 0x1e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx2], { z16.d, z17.d }" + + - + input: + bytes: [ 0x19, 0x1c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x19, 0x1c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x58, 0x5e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 0, vgx2], { z18.d, z19.d }" + + - + input: + bytes: [ 0x58, 0x5e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 0, vgx2], { z18.d, z19.d }" + + - + input: + bytes: [ 0x98, 0x1d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x98, 0x1d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x19, 0x5c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0x19, 0x5c, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 1, vgx2], { z0.d, z1.d }" + + - + input: + bytes: [ 0xdd, 0x1e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx2], { z22.d, z23.d }" + + - + input: + bytes: [ 0xdd, 0x1e, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx2], { z22.d, z23.d }" + + - + input: + bytes: [ 0x1a, 0x7d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 2, vgx2], { z8.d, z9.d }" + + - + input: + bytes: [ 0x1a, 0x7d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 2, vgx2], { z8.d, z9.d }" + + - + input: + bytes: [ 0x9f, 0x3d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w9, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x9f, 0x3d, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w9, 7, vgx2], { z12.d, z13.d }" + + - + input: + bytes: [ 0x18, 0x18, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x18, 0x18, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x5d, 0x59, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d" + + - + input: + bytes: [ 0x5d, 0x59, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d" + + - + input: + bytes: [ 0xbf, 0x79, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx2], { z13.d, z14.d }, z8.d" + + - + input: + bytes: [ 0xbf, 0x79, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx2], { z13.d, z14.d }, z8.d" + + - + input: + bytes: [ 0xff, 0x7b, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx2], { z31.d, z0.d }, z15.d" + + - + input: + bytes: [ 0xff, 0x7b, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx2], { z31.d, z0.d }, z15.d" + + - + input: + bytes: [ 0x3d, 0x1a, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx2], { z17.d, z18.d }, z0.d" + + - + input: + bytes: [ 0x3d, 0x1a, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx2], { z17.d, z18.d }, z0.d" + + - + input: + bytes: [ 0x39, 0x18, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 1, vgx2], { z1.d, z2.d }, z14.d" + + - + input: + bytes: [ 0x39, 0x18, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 1, vgx2], { z1.d, z2.d }, z14.d" + + - + input: + bytes: [ 0x78, 0x5a, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 0, vgx2], { z19.d, z20.d }, z4.d" + + - + input: + bytes: [ 0x78, 0x5a, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 0, vgx2], { z19.d, z20.d }, z4.d" + + - + input: + bytes: [ 0x98, 0x19, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d" + + - + input: + bytes: [ 0x98, 0x19, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d" + + - + input: + bytes: [ 0x39, 0x58, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 1, vgx2], { z1.d, z2.d }, z10.d" + + - + input: + bytes: [ 0x39, 0x58, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 1, vgx2], { z1.d, z2.d }, z10.d" + + - + input: + bytes: [ 0xdd, 0x1a, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d" + + - + input: + bytes: [ 0xdd, 0x1a, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d" + + - + input: + bytes: [ 0x3a, 0x79, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 2, vgx2], { z9.d, z10.d }, z1.d" + + - + input: + bytes: [ 0x3a, 0x79, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 2, vgx2], { z9.d, z10.d }, z1.d" + + - + input: + bytes: [ 0x9f, 0x39, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d" + + - + input: + bytes: [ 0x9f, 0x39, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d" + + - + input: + bytes: [ 0x18, 0x18, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x18, 0x18, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x5d, 0x59, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x5d, 0x59, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x9f, 0x79, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0x9f, 0x79, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0xdf, 0x7b, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0xdf, 0x7b, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x1d, 0x1a, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }" + + - + input: + bytes: [ 0x1d, 0x1a, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }" + + - + input: + bytes: [ 0x19, 0x18, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x19, 0x18, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x58, 0x5a, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x58, 0x5a, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x98, 0x19, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }" + + - + input: + bytes: [ 0x98, 0x19, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }" + + - + input: + bytes: [ 0x19, 0x58, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }" + + - + input: + bytes: [ 0x19, 0x58, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }" + + - + input: + bytes: [ 0xdd, 0x1a, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0xdd, 0x1a, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x1a, 0x79, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x1a, 0x79, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x9f, 0x39, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }" + + - + input: + bytes: [ 0x9f, 0x39, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }" + + - + input: + bytes: [ 0x18, 0x1c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x18, 0x1c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x1d, 0x5d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 5, vgx4], { z8.s - z11.s }" + + - + input: + bytes: [ 0x1d, 0x5d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 5, vgx4], { z8.s - z11.s }" + + - + input: + bytes: [ 0x9f, 0x7d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x9f, 0x7d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x9f, 0x7f, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx4], { z28.s - z31.s }" + + - + input: + bytes: [ 0x9f, 0x7f, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx4], { z28.s - z31.s }" + + - + input: + bytes: [ 0x1d, 0x1e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx4], { z16.s - z19.s }" + + - + input: + bytes: [ 0x1d, 0x1e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx4], { z16.s - z19.s }" + + - + input: + bytes: [ 0x19, 0x1c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 1, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x19, 0x1c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 1, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x18, 0x5e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 0, vgx4], { z16.s - z19.s }" + + - + input: + bytes: [ 0x18, 0x5e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 0, vgx4], { z16.s - z19.s }" + + - + input: + bytes: [ 0x98, 0x1d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x98, 0x1d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x19, 0x5c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 1, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x19, 0x5c, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 1, vgx4], { z0.s - z3.s }" + + - + input: + bytes: [ 0x9d, 0x1e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx4], { z20.s - z23.s }" + + - + input: + bytes: [ 0x9d, 0x1e, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx4], { z20.s - z23.s }" + + - + input: + bytes: [ 0x1a, 0x7d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 2, vgx4], { z8.s - z11.s }" + + - + input: + bytes: [ 0x1a, 0x7d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 2, vgx4], { z8.s - z11.s }" + + - + input: + bytes: [ 0x9f, 0x3d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w9, 7, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x9f, 0x3d, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w9, 7, vgx4], { z12.s - z15.s }" + + - + input: + bytes: [ 0x18, 0x18, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x18, 0x18, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x5d, 0x59, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 5, vgx4], { z10.s - z13.s }, z5.s" + + - + input: + bytes: [ 0x5d, 0x59, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 5, vgx4], { z10.s - z13.s }, z5.s" + + - + input: + bytes: [ 0xbf, 0x79, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx4], { z13.s - z16.s }, z8.s" + + - + input: + bytes: [ 0xbf, 0x79, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx4], { z13.s - z16.s }, z8.s" + + - + input: + bytes: [ 0xff, 0x7b, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx4], { z31.s, z0.s, z1.s, z2.s }, z15.s" + + - + input: + bytes: [ 0xff, 0x7b, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx4], { z31.s, z0.s, z1.s, z2.s }, z15.s" + + - + input: + bytes: [ 0x3d, 0x1a, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx4], { z17.s - z20.s }, z0.s" + + - + input: + bytes: [ 0x3d, 0x1a, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx4], { z17.s - z20.s }, z0.s" + + - + input: + bytes: [ 0x39, 0x18, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 1, vgx4], { z1.s - z4.s }, z14.s" + + - + input: + bytes: [ 0x39, 0x18, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 1, vgx4], { z1.s - z4.s }, z14.s" + + - + input: + bytes: [ 0x78, 0x5a, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 0, vgx4], { z19.s - z22.s }, z4.s" + + - + input: + bytes: [ 0x78, 0x5a, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 0, vgx4], { z19.s - z22.s }, z4.s" + + - + input: + bytes: [ 0x98, 0x19, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s" + + - + input: + bytes: [ 0x98, 0x19, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s" + + - + input: + bytes: [ 0x39, 0x58, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 1, vgx4], { z1.s - z4.s }, z10.s" + + - + input: + bytes: [ 0x39, 0x58, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 1, vgx4], { z1.s - z4.s }, z10.s" + + - + input: + bytes: [ 0xdd, 0x1a, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx4], { z22.s - z25.s }, z14.s" + + - + input: + bytes: [ 0xdd, 0x1a, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx4], { z22.s - z25.s }, z14.s" + + - + input: + bytes: [ 0x3a, 0x79, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 2, vgx4], { z9.s - z12.s }, z1.s" + + - + input: + bytes: [ 0x3a, 0x79, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 2, vgx4], { z9.s - z12.s }, z1.s" + + - + input: + bytes: [ 0x9f, 0x39, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s" + + - + input: + bytes: [ 0x9f, 0x39, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s" + + - + input: + bytes: [ 0x18, 0x18, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x18, 0x18, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x1d, 0x59, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x1d, 0x59, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x9f, 0x79, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x9f, 0x79, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x9f, 0x7b, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x9f, 0x7b, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x1d, 0x1a, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }" + + - + input: + bytes: [ 0x1d, 0x1a, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }" + + - + input: + bytes: [ 0x19, 0x18, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x19, 0x18, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x18, 0x5a, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x18, 0x5a, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x98, 0x19, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x98, 0x19, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x19, 0x58, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }" + + - + input: + bytes: [ 0x19, 0x58, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }" + + - + input: + bytes: [ 0x9d, 0x1a, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x9d, 0x1a, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x1a, 0x79, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x1a, 0x79, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x9f, 0x39, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x9f, 0x39, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x18, 0x1c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x18, 0x1c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x1d, 0x5d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 5, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x1d, 0x5d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 5, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x9f, 0x7d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x9f, 0x7d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x9f, 0x7f, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx4], { z28.d - z31.d }" + + - + input: + bytes: [ 0x9f, 0x7f, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx4], { z28.d - z31.d }" + + - + input: + bytes: [ 0x1d, 0x1e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x1d, 0x1e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x19, 0x1c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x19, 0x1c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x18, 0x5e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 0, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x18, 0x5e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 0, vgx4], { z16.d - z19.d }" + + - + input: + bytes: [ 0x98, 0x1d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x98, 0x1d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x19, 0x5c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x19, 0x5c, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 1, vgx4], { z0.d - z3.d }" + + - + input: + bytes: [ 0x9d, 0x1e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx4], { z20.d - z23.d }" + + - + input: + bytes: [ 0x9d, 0x1e, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx4], { z20.d - z23.d }" + + - + input: + bytes: [ 0x1a, 0x7d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 2, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x1a, 0x7d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 2, vgx4], { z8.d - z11.d }" + + - + input: + bytes: [ 0x9f, 0x3d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w9, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x9f, 0x3d, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w9, 7, vgx4], { z12.d - z15.d }" + + - + input: + bytes: [ 0x18, 0x18, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x18, 0x18, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x5d, 0x59, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 5, vgx4], { z10.d - z13.d }, z5.d" + + - + input: + bytes: [ 0x5d, 0x59, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 5, vgx4], { z10.d - z13.d }, z5.d" + + - + input: + bytes: [ 0xbf, 0x79, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx4], { z13.d - z16.d }, z8.d" + + - + input: + bytes: [ 0xbf, 0x79, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx4], { z13.d - z16.d }, z8.d" + + - + input: + bytes: [ 0xff, 0x7b, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx4], { z31.d, z0.d, z1.d, z2.d }, z15.d" + + - + input: + bytes: [ 0xff, 0x7b, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx4], { z31.d, z0.d, z1.d, z2.d }, z15.d" + + - + input: + bytes: [ 0x3d, 0x1a, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx4], { z17.d - z20.d }, z0.d" + + - + input: + bytes: [ 0x3d, 0x1a, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx4], { z17.d - z20.d }, z0.d" + + - + input: + bytes: [ 0x39, 0x18, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 1, vgx4], { z1.d - z4.d }, z14.d" + + - + input: + bytes: [ 0x39, 0x18, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 1, vgx4], { z1.d - z4.d }, z14.d" + + - + input: + bytes: [ 0x78, 0x5a, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 0, vgx4], { z19.d - z22.d }, z4.d" + + - + input: + bytes: [ 0x78, 0x5a, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 0, vgx4], { z19.d - z22.d }, z4.d" + + - + input: + bytes: [ 0x98, 0x19, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d" + + - + input: + bytes: [ 0x98, 0x19, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d" + + - + input: + bytes: [ 0x39, 0x58, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 1, vgx4], { z1.d - z4.d }, z10.d" + + - + input: + bytes: [ 0x39, 0x58, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 1, vgx4], { z1.d - z4.d }, z10.d" + + - + input: + bytes: [ 0xdd, 0x1a, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx4], { z22.d - z25.d }, z14.d" + + - + input: + bytes: [ 0xdd, 0x1a, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx4], { z22.d - z25.d }, z14.d" + + - + input: + bytes: [ 0x3a, 0x79, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 2, vgx4], { z9.d - z12.d }, z1.d" + + - + input: + bytes: [ 0x3a, 0x79, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 2, vgx4], { z9.d - z12.d }, z1.d" + + - + input: + bytes: [ 0x9f, 0x39, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d" + + - + input: + bytes: [ 0x9f, 0x39, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d" + + - + input: + bytes: [ 0x18, 0x18, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x18, 0x18, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x1d, 0x59, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x1d, 0x59, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x9f, 0x79, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x9f, 0x79, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x9f, 0x7b, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x9f, 0x7b, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x1d, 0x1a, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }" + + - + input: + bytes: [ 0x1d, 0x1a, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }" + + - + input: + bytes: [ 0x19, 0x18, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x19, 0x18, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x18, 0x5a, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x18, 0x5a, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x98, 0x19, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x98, 0x19, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x19, 0x58, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }" + + - + input: + bytes: [ 0x19, 0x58, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }" + + - + input: + bytes: [ 0x9d, 0x1a, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x9d, 0x1a, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x1a, 0x79, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x1a, 0x79, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x9f, 0x39, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x9f, 0x39, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "sub za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }" diff --git a/tests/MC/AArch64/SME2/sudot.s.yaml b/tests/MC/AArch64/SME2/sudot.s.yaml new file mode 100644 index 0000000000..16a6ba80bd --- /dev/null +++ b/tests/MC/AArch64/SME2/sudot.s.yaml @@ -0,0 +1,960 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x14, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x18, 0x14, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x5d, 0x55, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0x5d, 0x55, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0xbf, 0x75, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xbf, 0x75, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xff, 0x77, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0xff, 0x77, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0x3d, 0x16, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 5, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x3d, 0x16, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 5, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x39, 0x14, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 1, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x39, 0x14, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 1, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x78, 0x56, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 0, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x78, 0x56, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 0, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x98, 0x15, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x98, 0x15, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x39, 0x54, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 1, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0x39, 0x54, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 1, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0xdd, 0x16, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0xdd, 0x16, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0x3a, 0x75, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 2, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x3a, 0x75, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 2, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x9f, 0x35, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x9f, 0x35, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x38, 0x10, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x38, 0x10, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x7d, 0x55, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]" + + - + input: + bytes: [ 0x7d, 0x55, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]" + + - + input: + bytes: [ 0xbf, 0x7d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]" + + - + input: + bytes: [ 0xbf, 0x7d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]" + + - + input: + bytes: [ 0xff, 0x7f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]" + + - + input: + bytes: [ 0xff, 0x7f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]" + + - + input: + bytes: [ 0x3d, 0x1e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]" + + - + input: + bytes: [ 0x3d, 0x1e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]" + + - + input: + bytes: [ 0x39, 0x14, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]" + + - + input: + bytes: [ 0x39, 0x14, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]" + + - + input: + bytes: [ 0x78, 0x56, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]" + + - + input: + bytes: [ 0x78, 0x56, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]" + + - + input: + bytes: [ 0xb8, 0x19, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]" + + - + input: + bytes: [ 0xb8, 0x19, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]" + + - + input: + bytes: [ 0x39, 0x58, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]" + + - + input: + bytes: [ 0x39, 0x58, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]" + + - + input: + bytes: [ 0xfd, 0x1a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]" + + - + input: + bytes: [ 0xfd, 0x1a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]" + + - + input: + bytes: [ 0x3a, 0x75, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]" + + - + input: + bytes: [ 0x3a, 0x75, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]" + + - + input: + bytes: [ 0xbf, 0x39, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]" + + - + input: + bytes: [ 0xbf, 0x39, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]" + + - + input: + bytes: [ 0x18, 0x14, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x18, 0x14, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x5d, 0x55, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 5, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0x5d, 0x55, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 5, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0xbf, 0x75, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xbf, 0x75, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xff, 0x77, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0xff, 0x77, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0x3d, 0x16, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 5, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x3d, 0x16, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 5, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x39, 0x14, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 1, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x39, 0x14, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 1, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x78, 0x56, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 0, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x78, 0x56, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 0, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x98, 0x15, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x98, 0x15, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x39, 0x54, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 1, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0x39, 0x54, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 1, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0xdd, 0x16, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 5, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0xdd, 0x16, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 5, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0x3a, 0x75, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 2, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x3a, 0x75, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 2, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x9f, 0x35, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x9f, 0x35, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x38, 0x90, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x38, 0x90, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x3d, 0xd5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]" + + - + input: + bytes: [ 0x3d, 0xd5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]" + + - + input: + bytes: [ 0xbf, 0xfd, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]" + + - + input: + bytes: [ 0xbf, 0xfd, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]" + + - + input: + bytes: [ 0xbf, 0xff, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]" + + - + input: + bytes: [ 0xbf, 0xff, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]" + + - + input: + bytes: [ 0x3d, 0x9e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]" + + - + input: + bytes: [ 0x3d, 0x9e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]" + + - + input: + bytes: [ 0x39, 0x94, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]" + + - + input: + bytes: [ 0x39, 0x94, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]" + + - + input: + bytes: [ 0x38, 0xd6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]" + + - + input: + bytes: [ 0x38, 0xd6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]" + + - + input: + bytes: [ 0xb8, 0x99, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]" + + - + input: + bytes: [ 0xb8, 0x99, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]" + + - + input: + bytes: [ 0x39, 0xd8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]" + + - + input: + bytes: [ 0x39, 0xd8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]" + + - + input: + bytes: [ 0xbd, 0x9a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]" + + - + input: + bytes: [ 0xbd, 0x9a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]" + + - + input: + bytes: [ 0x3a, 0xf5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]" + + - + input: + bytes: [ 0x3a, 0xf5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]" + + - + input: + bytes: [ 0xbf, 0xb9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]" + + - + input: + bytes: [ 0xbf, 0xb9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sudot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]" diff --git a/tests/MC/AArch64/SME2/sumlall.s.yaml b/tests/MC/AArch64/SME2/sumlall.s.yaml new file mode 100644 index 0000000000..56dec7af97 --- /dev/null +++ b/tests/MC/AArch64/SME2/sumlall.s.yaml @@ -0,0 +1,1080 @@ +test_cases: + - + input: + bytes: [ 0x14, 0x00, 0x00, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 0:3], z0.b, z0.b[0]" + + - + input: + bytes: [ 0x55, 0x55, 0x05, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 4:7], z10.b, z5.b[5]" + + - + input: + bytes: [ 0xb7, 0xed, 0x08, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 12:15], z13.b, z8.b[11]" + + - + input: + bytes: [ 0xf7, 0xff, 0x0f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 12:15], z31.b, z15.b[15]" + + - + input: + bytes: [ 0x35, 0x0e, 0x00, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7], z17.b, z0.b[3]" + + - + input: + bytes: [ 0x35, 0x84, 0x0e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7], z1.b, z14.b[9]" + + - + input: + bytes: [ 0x74, 0x56, 0x04, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 0:3], z19.b, z4.b[5]" + + - + input: + bytes: [ 0x94, 0x19, 0x02, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 0:3], z12.b, z2.b[6]" + + - + input: + bytes: [ 0x35, 0xc8, 0x0a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 4:7], z1.b, z10.b[10]" + + - + input: + bytes: [ 0xd5, 0x0a, 0x0e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7], z22.b, z14.b[2]" + + - + input: + bytes: [ 0x36, 0xf5, 0x01, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 8:11], z9.b, z1.b[13]" + + - + input: + bytes: [ 0x97, 0xa9, 0x0b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w9, 12:15], z12.b, z11.b[10]" + + - + input: + bytes: [ 0x14, 0x00, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x14, 0x00, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x55, 0x41, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0x55, 0x41, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0xb5, 0x61, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 4:7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xb5, 0x61, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 4:7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xf5, 0x63, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 4:7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0xf5, 0x63, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 4:7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0x35, 0x02, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x35, 0x02, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x35, 0x00, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x35, 0x00, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x74, 0x42, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 0:3, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x74, 0x42, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 0:3, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x94, 0x01, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x94, 0x01, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x35, 0x40, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 4:7, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0x35, 0x40, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 4:7, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0xd5, 0x02, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0xd5, 0x02, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0x34, 0x61, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 0:3, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x34, 0x61, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 0:3, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x95, 0x21, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x95, 0x21, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x30, 0x00, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x30, 0x00, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x75, 0x45, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x75, 0x45, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]" + + - + input: + bytes: [ 0xf7, 0x6f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]" + + - + input: + bytes: [ 0xf7, 0x6f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]" + + - + input: + bytes: [ 0x35, 0x0e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]" + + - + input: + bytes: [ 0x35, 0x0e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]" + + - + input: + bytes: [ 0x31, 0x04, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]" + + - + input: + bytes: [ 0x31, 0x04, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]" + + - + input: + bytes: [ 0x70, 0x46, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x70, 0x46, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]" + + - + input: + bytes: [ 0xb0, 0x09, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]" + + - + input: + bytes: [ 0xb0, 0x09, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]" + + - + input: + bytes: [ 0x31, 0x48, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]" + + - + input: + bytes: [ 0x31, 0x48, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]" + + - + input: + bytes: [ 0xf5, 0x0a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]" + + - + input: + bytes: [ 0xf5, 0x0a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]" + + - + input: + bytes: [ 0x32, 0x65, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]" + + - + input: + bytes: [ 0x32, 0x65, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]" + + - + input: + bytes: [ 0xb7, 0x29, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]" + + - + input: + bytes: [ 0xb7, 0x29, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]" + + - + input: + bytes: [ 0x14, 0x00, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x14, 0x00, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x55, 0x41, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 4:7, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0x55, 0x41, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 4:7, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0xb5, 0x61, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 4:7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xb5, 0x61, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 4:7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xf5, 0x63, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 4:7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0xf5, 0x63, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 4:7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0x35, 0x02, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x35, 0x02, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x35, 0x00, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x35, 0x00, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x74, 0x42, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 0:3, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x74, 0x42, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 0:3, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x94, 0x01, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x94, 0x01, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x35, 0x40, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 4:7, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0x35, 0x40, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 4:7, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0xd5, 0x02, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0xd5, 0x02, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0x34, 0x61, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 0:3, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x34, 0x61, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 0:3, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x95, 0x21, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x95, 0x21, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x30, 0x80, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x30, 0x80, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x35, 0xc5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x35, 0xc5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]" + + - + input: + bytes: [ 0xb7, 0xed, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]" + + - + input: + bytes: [ 0xb7, 0xed, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]" + + - + input: + bytes: [ 0xb7, 0xef, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]" + + - + input: + bytes: [ 0xb7, 0xef, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]" + + - + input: + bytes: [ 0x35, 0x8e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]" + + - + input: + bytes: [ 0x35, 0x8e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]" + + - + input: + bytes: [ 0x31, 0x84, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]" + + - + input: + bytes: [ 0x31, 0x84, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]" + + - + input: + bytes: [ 0x30, 0xc6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x30, 0xc6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]" + + - + input: + bytes: [ 0xb0, 0x89, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]" + + - + input: + bytes: [ 0xb0, 0x89, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]" + + - + input: + bytes: [ 0x31, 0xc8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]" + + - + input: + bytes: [ 0x31, 0xc8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]" + + - + input: + bytes: [ 0xb5, 0x8a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]" + + - + input: + bytes: [ 0xb5, 0x8a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]" + + - + input: + bytes: [ 0x32, 0xe5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]" + + - + input: + bytes: [ 0x32, 0xe5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]" + + - + input: + bytes: [ 0xb7, 0xa9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]" + + - + input: + bytes: [ 0xb7, 0xa9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sumlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]" diff --git a/tests/MC/AArch64/SME2/sunpk.s.yaml b/tests/MC/AArch64/SME2/sunpk.s.yaml new file mode 100644 index 0000000000..0cb656eebb --- /dev/null +++ b/tests/MC/AArch64/SME2/sunpk.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z0.h, z1.h }, z0.b" + + - + input: + bytes: [ 0x54, 0xe1, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z20.h, z21.h }, z10.b" + + - + input: + bytes: [ 0xb6, 0xe1, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z22.h, z23.h }, z13.b" + + - + input: + bytes: [ 0xfe, 0xe3, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z30.h, z31.h }, z31.b" + + - + input: + bytes: [ 0x00, 0xe0, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z0.s, z1.s }, z0.h" + + - + input: + bytes: [ 0x54, 0xe1, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z20.s, z21.s }, z10.h" + + - + input: + bytes: [ 0xb6, 0xe1, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z22.s, z23.s }, z13.h" + + - + input: + bytes: [ 0xfe, 0xe3, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z30.s, z31.s }, z31.h" + + - + input: + bytes: [ 0x00, 0xe0, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z0.d, z1.d }, z0.s" + + - + input: + bytes: [ 0x54, 0xe1, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z20.d, z21.d }, z10.s" + + - + input: + bytes: [ 0xb6, 0xe1, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z22.d, z23.d }, z13.s" + + - + input: + bytes: [ 0xfe, 0xe3, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z30.d, z31.d }, z31.s" + + - + input: + bytes: [ 0x00, 0xe0, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z0.h - z3.h }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x54, 0xe1, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z20.h - z23.h }, { z10.b, z11.b }" + + - + input: + bytes: [ 0x94, 0xe1, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z20.h - z23.h }, { z12.b, z13.b }" + + - + input: + bytes: [ 0xdc, 0xe3, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z28.h - z31.h }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x00, 0xe0, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z0.s - z3.s }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x54, 0xe1, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z20.s - z23.s }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x94, 0xe1, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z20.s - z23.s }, { z12.h, z13.h }" + + - + input: + bytes: [ 0xdc, 0xe3, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z28.s - z31.s }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x00, 0xe0, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z0.d - z3.d }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x54, 0xe1, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z20.d - z23.d }, { z10.s, z11.s }" + + - + input: + bytes: [ 0x94, 0xe1, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z20.d - z23.d }, { z12.s, z13.s }" + + - + input: + bytes: [ 0xdc, 0xe3, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sunpk { z28.d - z31.d }, { z30.s, z31.s }" diff --git a/tests/MC/AArch64/SME2/suvdot.s.yaml b/tests/MC/AArch64/SME2/suvdot.s.yaml new file mode 100644 index 0000000000..f3170acf88 --- /dev/null +++ b/tests/MC/AArch64/SME2/suvdot.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x38, 0x80, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x38, 0x80, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x3d, 0xc5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]" + + - + input: + bytes: [ 0x3d, 0xc5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]" + + - + input: + bytes: [ 0xbf, 0xed, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]" + + - + input: + bytes: [ 0xbf, 0xed, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]" + + - + input: + bytes: [ 0xbf, 0xef, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]" + + - + input: + bytes: [ 0xbf, 0xef, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]" + + - + input: + bytes: [ 0x3d, 0x8e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]" + + - + input: + bytes: [ 0x3d, 0x8e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]" + + - + input: + bytes: [ 0x39, 0x84, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]" + + - + input: + bytes: [ 0x39, 0x84, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]" + + - + input: + bytes: [ 0x38, 0xc6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]" + + - + input: + bytes: [ 0x38, 0xc6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]" + + - + input: + bytes: [ 0xb8, 0x89, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]" + + - + input: + bytes: [ 0xb8, 0x89, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]" + + - + input: + bytes: [ 0x39, 0xc8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]" + + - + input: + bytes: [ 0x39, 0xc8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]" + + - + input: + bytes: [ 0xbd, 0x8a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]" + + - + input: + bytes: [ 0xbd, 0x8a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]" + + - + input: + bytes: [ 0x3a, 0xe5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]" + + - + input: + bytes: [ 0x3a, 0xe5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]" + + - + input: + bytes: [ 0xbf, 0xa9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]" + + - + input: + bytes: [ 0xbf, 0xa9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "suvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]" diff --git a/tests/MC/AArch64/SME2/svdot.s.yaml b/tests/MC/AArch64/SME2/svdot.s.yaml new file mode 100644 index 0000000000..0dec64a3f9 --- /dev/null +++ b/tests/MC/AArch64/SME2/svdot.s.yaml @@ -0,0 +1,720 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x00, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x20, 0x00, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x65, 0x45, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x65, 0x45, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0xa7, 0x6d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]" + + - + input: + bytes: [ 0xa7, 0x6d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]" + + - + input: + bytes: [ 0xe7, 0x6f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]" + + - + input: + bytes: [ 0xe7, 0x6f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]" + + - + input: + bytes: [ 0x25, 0x0e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]" + + - + input: + bytes: [ 0x25, 0x0e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]" + + - + input: + bytes: [ 0x21, 0x04, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x21, 0x04, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x60, 0x46, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x60, 0x46, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0xa0, 0x09, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]" + + - + input: + bytes: [ 0xa0, 0x09, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]" + + - + input: + bytes: [ 0x21, 0x48, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]" + + - + input: + bytes: [ 0x21, 0x48, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]" + + - + input: + bytes: [ 0xe5, 0x0a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0xe5, 0x0a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x22, 0x65, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0x22, 0x65, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0xa7, 0x29, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]" + + - + input: + bytes: [ 0xa7, 0x29, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]" + + - + input: + bytes: [ 0x20, 0x80, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x20, 0x80, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x25, 0xc5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]" + + - + input: + bytes: [ 0x25, 0xc5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]" + + - + input: + bytes: [ 0xa7, 0xed, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]" + + - + input: + bytes: [ 0xa7, 0xed, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]" + + - + input: + bytes: [ 0xa7, 0xef, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]" + + - + input: + bytes: [ 0xa7, 0xef, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]" + + - + input: + bytes: [ 0x25, 0x8e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]" + + - + input: + bytes: [ 0x25, 0x8e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]" + + - + input: + bytes: [ 0x21, 0x84, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]" + + - + input: + bytes: [ 0x21, 0x84, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]" + + - + input: + bytes: [ 0x20, 0xc6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]" + + - + input: + bytes: [ 0x20, 0xc6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]" + + - + input: + bytes: [ 0xa0, 0x89, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]" + + - + input: + bytes: [ 0xa0, 0x89, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]" + + - + input: + bytes: [ 0x21, 0xc8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]" + + - + input: + bytes: [ 0x21, 0xc8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]" + + - + input: + bytes: [ 0xa5, 0x8a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]" + + - + input: + bytes: [ 0xa5, 0x8a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]" + + - + input: + bytes: [ 0x22, 0xe5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]" + + - + input: + bytes: [ 0x22, 0xe5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]" + + - + input: + bytes: [ 0xa7, 0xa9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]" + + - + input: + bytes: [ 0xa7, 0xa9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]" + + - + input: + bytes: [ 0x08, 0x88, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x08, 0x88, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x0d, 0xcd, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x0d, 0xcd, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x8f, 0xed, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]" + + - + input: + bytes: [ 0x8f, 0xed, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]" + + - + input: + bytes: [ 0x8f, 0xef, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]" + + - + input: + bytes: [ 0x8f, 0xef, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]" + + - + input: + bytes: [ 0x0d, 0x8e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]" + + - + input: + bytes: [ 0x0d, 0x8e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]" + + - + input: + bytes: [ 0x09, 0x8c, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]" + + - + input: + bytes: [ 0x09, 0x8c, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]" + + - + input: + bytes: [ 0x08, 0xce, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x08, 0xce, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x88, 0x89, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]" + + - + input: + bytes: [ 0x88, 0x89, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]" + + - + input: + bytes: [ 0x09, 0xc8, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]" + + - + input: + bytes: [ 0x09, 0xc8, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]" + + - + input: + bytes: [ 0x8d, 0x8a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]" + + - + input: + bytes: [ 0x8d, 0x8a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]" + + - + input: + bytes: [ 0x0a, 0xed, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]" + + - + input: + bytes: [ 0x0a, 0xed, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]" + + - + input: + bytes: [ 0x8f, 0xa9, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]" + + - + input: + bytes: [ 0x8f, 0xa9, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "svdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]" diff --git a/tests/MC/AArch64/SME2/uclamp.s.yaml b/tests/MC/AArch64/SME2/uclamp.s.yaml new file mode 100644 index 0000000000..2bf85823ee --- /dev/null +++ b/tests/MC/AArch64/SME2/uclamp.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x01, 0xc4, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z0.h, z1.h }, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xc5, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z20.h, z21.h }, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xc5, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z22.h, z23.h }, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xc7, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z30.h, z31.h }, z31.h, z31.h" + + - + input: + bytes: [ 0x01, 0xc4, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z0.s, z1.s }, z0.s, z0.s" + + - + input: + bytes: [ 0x55, 0xc5, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z20.s, z21.s }, z10.s, z21.s" + + - + input: + bytes: [ 0xb7, 0xc5, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z22.s, z23.s }, z13.s, z8.s" + + - + input: + bytes: [ 0xff, 0xc7, 0xbf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z30.s, z31.s }, z31.s, z31.s" + + - + input: + bytes: [ 0x01, 0xc4, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z0.d, z1.d }, z0.d, z0.d" + + - + input: + bytes: [ 0x55, 0xc5, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z20.d, z21.d }, z10.d, z21.d" + + - + input: + bytes: [ 0xb7, 0xc5, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z22.d, z23.d }, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0xc7, 0xff, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z30.d, z31.d }, z31.d, z31.d" + + - + input: + bytes: [ 0x01, 0xc4, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z0.b, z1.b }, z0.b, z0.b" + + - + input: + bytes: [ 0x55, 0xc5, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z20.b, z21.b }, z10.b, z21.b" + + - + input: + bytes: [ 0xb7, 0xc5, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z22.b, z23.b }, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0xc7, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z30.b, z31.b }, z31.b, z31.b" + + - + input: + bytes: [ 0x01, 0xcc, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z0.h - z3.h }, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xcd, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z20.h - z23.h }, z10.h, z21.h" + + - + input: + bytes: [ 0xb5, 0xcd, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z20.h - z23.h }, z13.h, z8.h" + + - + input: + bytes: [ 0xfd, 0xcf, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z28.h - z31.h }, z31.h, z31.h" + + - + input: + bytes: [ 0x01, 0xcc, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z0.s - z3.s }, z0.s, z0.s" + + - + input: + bytes: [ 0x55, 0xcd, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z20.s - z23.s }, z10.s, z21.s" + + - + input: + bytes: [ 0xb5, 0xcd, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z20.s - z23.s }, z13.s, z8.s" + + - + input: + bytes: [ 0xfd, 0xcf, 0xbf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z28.s - z31.s }, z31.s, z31.s" + + - + input: + bytes: [ 0x01, 0xcc, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z0.d - z3.d }, z0.d, z0.d" + + - + input: + bytes: [ 0x55, 0xcd, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z20.d - z23.d }, z10.d, z21.d" + + - + input: + bytes: [ 0xb5, 0xcd, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z20.d - z23.d }, z13.d, z8.d" + + - + input: + bytes: [ 0xfd, 0xcf, 0xff, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z28.d - z31.d }, z31.d, z31.d" + + - + input: + bytes: [ 0x01, 0xcc, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z0.b - z3.b }, z0.b, z0.b" + + - + input: + bytes: [ 0x55, 0xcd, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z20.b - z23.b }, z10.b, z21.b" + + - + input: + bytes: [ 0xb5, 0xcd, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z20.b - z23.b }, z13.b, z8.b" + + - + input: + bytes: [ 0xfd, 0xcf, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uclamp { z28.b - z31.b }, z31.b, z31.b" diff --git a/tests/MC/AArch64/SME2/ucvtf.s.yaml b/tests/MC/AArch64/SME2/ucvtf.s.yaml new file mode 100644 index 0000000000..67ff915821 --- /dev/null +++ b/tests/MC/AArch64/SME2/ucvtf.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xe0, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ucvtf { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x74, 0xe1, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ucvtf { z20.s, z21.s }, { z10.s, z11.s }" + + - + input: + bytes: [ 0xb6, 0xe1, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ucvtf { z22.s, z23.s }, { z12.s, z13.s }" + + - + input: + bytes: [ 0xfe, 0xe3, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ucvtf { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x20, 0xe0, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ucvtf { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x34, 0xe1, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ucvtf { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0xb4, 0xe1, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ucvtf { z20.s - z23.s }, { z12.s - z15.s }" + + - + input: + bytes: [ 0xbc, 0xe3, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ucvtf { z28.s - z31.s }, { z28.s - z31.s }" diff --git a/tests/MC/AArch64/SME2/udot.s.yaml b/tests/MC/AArch64/SME2/udot.s.yaml new file mode 100644 index 0000000000..3f62eebf1e --- /dev/null +++ b/tests/MC/AArch64/SME2/udot.s.yaml @@ -0,0 +1,4330 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x14, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x18, 0x14, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x5d, 0x55, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x5d, 0x55, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xbf, 0x75, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xbf, 0x75, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xff, 0x77, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xff, 0x77, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x3d, 0x16, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x3d, 0x16, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x39, 0x14, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x39, 0x14, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x78, 0x56, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x78, 0x56, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x98, 0x15, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x98, 0x15, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x39, 0x54, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x39, 0x54, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xdd, 0x16, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xdd, 0x16, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x3a, 0x75, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x3a, 0x75, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x9f, 0x35, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x9f, 0x35, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x10, 0x10, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x10, 0x10, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x55, 0x55, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x55, 0x55, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x97, 0x7d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]" + + - + input: + bytes: [ 0x97, 0x7d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]" + + - + input: + bytes: [ 0xd7, 0x7f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]" + + - + input: + bytes: [ 0xd7, 0x7f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]" + + - + input: + bytes: [ 0x15, 0x1e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]" + + - + input: + bytes: [ 0x15, 0x1e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]" + + - + input: + bytes: [ 0x11, 0x14, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x11, 0x14, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x50, 0x56, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x50, 0x56, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x90, 0x19, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]" + + - + input: + bytes: [ 0x90, 0x19, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]" + + - + input: + bytes: [ 0x11, 0x58, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]" + + - + input: + bytes: [ 0x11, 0x58, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]" + + - + input: + bytes: [ 0xd5, 0x1a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0xd5, 0x1a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x12, 0x75, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0x12, 0x75, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0x97, 0x39, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]" + + - + input: + bytes: [ 0x97, 0x39, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]" + + - + input: + bytes: [ 0x18, 0x14, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x18, 0x14, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x5d, 0x55, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x5d, 0x55, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x9f, 0x75, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x9f, 0x75, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xdf, 0x77, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xdf, 0x77, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x1d, 0x16, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x1d, 0x16, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x19, 0x14, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x19, 0x14, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x58, 0x56, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x58, 0x56, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x98, 0x15, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x98, 0x15, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x19, 0x54, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x19, 0x54, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xdd, 0x16, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xdd, 0x16, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x1a, 0x75, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x1a, 0x75, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x9f, 0x35, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x9f, 0x35, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x30, 0x10, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x30, 0x10, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x75, 0x55, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]" + + - + input: + bytes: [ 0x75, 0x55, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]" + + - + input: + bytes: [ 0xb7, 0x7d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]" + + - + input: + bytes: [ 0xb7, 0x7d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]" + + - + input: + bytes: [ 0xf7, 0x7f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]" + + - + input: + bytes: [ 0xf7, 0x7f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]" + + - + input: + bytes: [ 0x35, 0x1e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]" + + - + input: + bytes: [ 0x35, 0x1e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]" + + - + input: + bytes: [ 0x31, 0x14, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]" + + - + input: + bytes: [ 0x31, 0x14, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]" + + - + input: + bytes: [ 0x70, 0x56, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]" + + - + input: + bytes: [ 0x70, 0x56, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]" + + - + input: + bytes: [ 0xb0, 0x19, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]" + + - + input: + bytes: [ 0xb0, 0x19, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]" + + - + input: + bytes: [ 0x31, 0x58, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]" + + - + input: + bytes: [ 0x31, 0x58, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]" + + - + input: + bytes: [ 0xf5, 0x1a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]" + + - + input: + bytes: [ 0xf5, 0x1a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]" + + - + input: + bytes: [ 0x32, 0x75, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]" + + - + input: + bytes: [ 0x32, 0x75, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]" + + - + input: + bytes: [ 0xb7, 0x39, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]" + + - + input: + bytes: [ 0xb7, 0x39, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]" + + - + input: + bytes: [ 0x18, 0x00, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x18, 0x00, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x5d, 0x45, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x5d, 0x45, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x9f, 0x65, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx2], { z12.h, z13.h }, z8.h[1]" + + - + input: + bytes: [ 0x9f, 0x65, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx2], { z12.h, z13.h }, z8.h[1]" + + - + input: + bytes: [ 0xdf, 0x67, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx2], { z30.h, z31.h }, z15.h[1]" + + - + input: + bytes: [ 0xdf, 0x67, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx2], { z30.h, z31.h }, z15.h[1]" + + - + input: + bytes: [ 0x1d, 0x06, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx2], { z16.h, z17.h }, z0.h[1]" + + - + input: + bytes: [ 0x1d, 0x06, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx2], { z16.h, z17.h }, z0.h[1]" + + - + input: + bytes: [ 0x19, 0x04, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x19, 0x04, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x58, 0x46, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x58, 0x46, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x98, 0x01, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h[0]" + + - + input: + bytes: [ 0x98, 0x01, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h[0]" + + - + input: + bytes: [ 0x19, 0x40, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 1, vgx2], { z0.h, z1.h }, z10.h[0]" + + - + input: + bytes: [ 0x19, 0x40, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 1, vgx2], { z0.h, z1.h }, z10.h[0]" + + - + input: + bytes: [ 0xdd, 0x02, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h[0]" + + - + input: + bytes: [ 0xdd, 0x02, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h[0]" + + - + input: + bytes: [ 0x1a, 0x65, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0x1a, 0x65, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0x9f, 0x21, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h[0]" + + - + input: + bytes: [ 0x9f, 0x21, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h[0]" + + - + input: + bytes: [ 0x18, 0x14, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x18, 0x14, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x5d, 0x55, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x5d, 0x55, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xbf, 0x75, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xbf, 0x75, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xff, 0x77, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xff, 0x77, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x3d, 0x16, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x3d, 0x16, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x39, 0x14, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x39, 0x14, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x78, 0x56, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x78, 0x56, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x98, 0x15, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x98, 0x15, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x39, 0x54, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x39, 0x54, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xdd, 0x16, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xdd, 0x16, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x3a, 0x75, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x3a, 0x75, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x9f, 0x35, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x9f, 0x35, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x10, 0x90, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x10, 0x90, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x15, 0xd5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x15, 0xd5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x97, 0xfd, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]" + + - + input: + bytes: [ 0x97, 0xfd, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]" + + - + input: + bytes: [ 0x97, 0xff, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]" + + - + input: + bytes: [ 0x97, 0xff, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]" + + - + input: + bytes: [ 0x15, 0x9e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]" + + - + input: + bytes: [ 0x15, 0x9e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]" + + - + input: + bytes: [ 0x11, 0x94, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]" + + - + input: + bytes: [ 0x11, 0x94, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]" + + - + input: + bytes: [ 0x10, 0xd6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x10, 0xd6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x90, 0x99, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]" + + - + input: + bytes: [ 0x90, 0x99, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]" + + - + input: + bytes: [ 0x11, 0xd8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]" + + - + input: + bytes: [ 0x11, 0xd8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]" + + - + input: + bytes: [ 0x95, 0x9a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x95, 0x9a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x12, 0xf5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]" + + - + input: + bytes: [ 0x12, 0xf5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]" + + - + input: + bytes: [ 0x97, 0xb9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]" + + - + input: + bytes: [ 0x97, 0xb9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]" + + - + input: + bytes: [ 0x18, 0x14, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x18, 0x14, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x1d, 0x55, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x1d, 0x55, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x9f, 0x75, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x9f, 0x75, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x9f, 0x77, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x9f, 0x77, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x1d, 0x16, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x1d, 0x16, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x19, 0x14, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x19, 0x14, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x18, 0x56, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x18, 0x56, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x98, 0x15, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x98, 0x15, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x19, 0x54, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x19, 0x54, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x9d, 0x16, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x9d, 0x16, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x1a, 0x75, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x1a, 0x75, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x9f, 0x35, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x9f, 0x35, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x30, 0x90, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x30, 0x90, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x35, 0xd5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]" + + - + input: + bytes: [ 0x35, 0xd5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]" + + - + input: + bytes: [ 0xb7, 0xfd, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]" + + - + input: + bytes: [ 0xb7, 0xfd, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]" + + - + input: + bytes: [ 0xb7, 0xff, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]" + + - + input: + bytes: [ 0xb7, 0xff, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]" + + - + input: + bytes: [ 0x35, 0x9e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]" + + - + input: + bytes: [ 0x35, 0x9e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]" + + - + input: + bytes: [ 0x31, 0x94, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]" + + - + input: + bytes: [ 0x31, 0x94, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]" + + - + input: + bytes: [ 0x30, 0xd6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]" + + - + input: + bytes: [ 0x30, 0xd6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]" + + - + input: + bytes: [ 0xb0, 0x99, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]" + + - + input: + bytes: [ 0xb0, 0x99, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]" + + - + input: + bytes: [ 0x31, 0xd8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]" + + - + input: + bytes: [ 0x31, 0xd8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]" + + - + input: + bytes: [ 0xb5, 0x9a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]" + + - + input: + bytes: [ 0xb5, 0x9a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]" + + - + input: + bytes: [ 0x32, 0xf5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]" + + - + input: + bytes: [ 0x32, 0xf5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]" + + - + input: + bytes: [ 0xb7, 0xb9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]" + + - + input: + bytes: [ 0xb7, 0xb9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]" + + - + input: + bytes: [ 0x18, 0x80, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x18, 0x80, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x1d, 0xc5, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x1d, 0xc5, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x9f, 0xe5, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]" + + - + input: + bytes: [ 0x9f, 0xe5, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]" + + - + input: + bytes: [ 0x9f, 0xe7, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]" + + - + input: + bytes: [ 0x9f, 0xe7, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]" + + - + input: + bytes: [ 0x1d, 0x86, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]" + + - + input: + bytes: [ 0x1d, 0x86, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]" + + - + input: + bytes: [ 0x19, 0x84, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]" + + - + input: + bytes: [ 0x19, 0x84, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]" + + - + input: + bytes: [ 0x18, 0xc6, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x18, 0xc6, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x98, 0x81, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]" + + - + input: + bytes: [ 0x98, 0x81, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]" + + - + input: + bytes: [ 0x19, 0xc0, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]" + + - + input: + bytes: [ 0x19, 0xc0, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]" + + - + input: + bytes: [ 0x9d, 0x82, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]" + + - + input: + bytes: [ 0x9d, 0x82, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]" + + - + input: + bytes: [ 0x1a, 0xe5, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]" + + - + input: + bytes: [ 0x1a, 0xe5, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]" + + - + input: + bytes: [ 0x9f, 0xa1, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]" + + - + input: + bytes: [ 0x9f, 0xa1, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]" + + - + input: + bytes: [ 0x10, 0x14, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x10, 0x14, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x55, 0x55, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0x55, 0x55, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0xb7, 0x75, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xb7, 0x75, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xf7, 0x77, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0xf7, 0x77, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0x35, 0x16, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x35, 0x16, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x31, 0x14, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x31, 0x14, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x70, 0x56, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x70, 0x56, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x90, 0x15, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x90, 0x15, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x31, 0x54, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0x31, 0x54, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0xd5, 0x16, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0xd5, 0x16, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0x32, 0x75, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x32, 0x75, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x97, 0x35, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x97, 0x35, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x10, 0x14, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x10, 0x14, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x55, 0x55, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx2], { z10.b, z11.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x55, 0x55, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx2], { z10.b, z11.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x97, 0x75, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0x97, 0x75, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0xd7, 0x77, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xd7, 0x77, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x15, 0x16, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z16.b, z17.b }, { z16.b, z17.b }" + + - + input: + bytes: [ 0x15, 0x16, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z16.b, z17.b }, { z16.b, z17.b }" + + - + input: + bytes: [ 0x11, 0x14, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx2], { z0.b, z1.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x11, 0x14, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx2], { z0.b, z1.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x50, 0x56, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx2], { z18.b, z19.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x50, 0x56, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx2], { z18.b, z19.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x90, 0x15, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z12.b, z13.b }, { z2.b, z3.b }" + + - + input: + bytes: [ 0x90, 0x15, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx2], { z12.b, z13.b }, { z2.b, z3.b }" + + - + input: + bytes: [ 0x11, 0x54, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx2], { z0.b, z1.b }, { z26.b, z27.b }" + + - + input: + bytes: [ 0x11, 0x54, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx2], { z0.b, z1.b }, { z26.b, z27.b }" + + - + input: + bytes: [ 0xd5, 0x16, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z22.b, z23.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xd5, 0x16, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx2], { z22.b, z23.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x12, 0x75, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx2], { z8.b, z9.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x12, 0x75, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx2], { z8.b, z9.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x97, 0x35, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }" + + - + input: + bytes: [ 0x97, 0x35, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }" + + - + input: + bytes: [ 0x10, 0x14, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x10, 0x14, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x55, 0x55, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x55, 0x55, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xb7, 0x75, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xb7, 0x75, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xf7, 0x77, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xf7, 0x77, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x35, 0x16, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x35, 0x16, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x31, 0x14, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x31, 0x14, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x70, 0x56, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x70, 0x56, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x90, 0x15, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x90, 0x15, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x31, 0x54, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x31, 0x54, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xd5, 0x16, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xd5, 0x16, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x32, 0x75, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x32, 0x75, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x97, 0x35, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x97, 0x35, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x97, 0x35, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x10, 0x14, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x10, 0x14, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x55, 0x55, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x55, 0x55, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x97, 0x75, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x97, 0x75, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xd7, 0x77, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xd7, 0x77, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x15, 0x16, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x15, 0x16, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x11, 0x14, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x11, 0x14, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x50, 0x56, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x50, 0x56, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x90, 0x15, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x90, 0x15, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x11, 0x54, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x11, 0x54, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xd5, 0x16, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xd5, 0x16, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x12, 0x75, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x12, 0x75, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x97, 0x35, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x97, 0x35, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x10, 0x14, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x10, 0x14, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x55, 0x55, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0x55, 0x55, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0xb7, 0x75, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xb7, 0x75, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xf7, 0x77, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0xf7, 0x77, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0x35, 0x16, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x35, 0x16, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x31, 0x14, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x31, 0x14, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x70, 0x56, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x70, 0x56, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x90, 0x15, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x90, 0x15, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x31, 0x54, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0x31, 0x54, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0xd5, 0x16, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0xd5, 0x16, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0x32, 0x75, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x32, 0x75, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x97, 0x35, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x97, 0x35, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x10, 0x14, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x10, 0x14, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x15, 0x55, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx4], { z8.b - z11.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x15, 0x55, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 5, vgx4], { z8.b - z11.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x97, 0x75, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x97, 0x75, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x97, 0x77, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x97, 0x77, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x15, 0x16, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z16.b - z19.b }, { z16.b - z19.b }" + + - + input: + bytes: [ 0x15, 0x16, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z16.b - z19.b }, { z16.b - z19.b }" + + - + input: + bytes: [ 0x11, 0x14, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx4], { z0.b - z3.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x11, 0x14, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 1, vgx4], { z0.b - z3.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x10, 0x56, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx4], { z16.b - z19.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x10, 0x56, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 0, vgx4], { z16.b - z19.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x90, 0x15, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z12.b - z15.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x90, 0x15, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 0, vgx4], { z12.b - z15.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x11, 0x54, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx4], { z0.b - z3.b }, { z24.b - z27.b }" + + - + input: + bytes: [ 0x11, 0x54, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w10, 1, vgx4], { z0.b - z3.b }, { z24.b - z27.b }" + + - + input: + bytes: [ 0x95, 0x16, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z20.b - z23.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x95, 0x16, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w8, 5, vgx4], { z20.b - z23.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x12, 0x75, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx4], { z8.b - z11.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x12, 0x75, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w11, 2, vgx4], { z8.b - z11.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x97, 0x35, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x97, 0x35, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.s[w9, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x10, 0x14, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x10, 0x14, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x55, 0x55, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x55, 0x55, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xb7, 0x75, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xb7, 0x75, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xf7, 0x77, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xf7, 0x77, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x35, 0x16, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x35, 0x16, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x31, 0x14, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x31, 0x14, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x70, 0x56, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x70, 0x56, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x90, 0x15, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x90, 0x15, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x31, 0x54, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x31, 0x54, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xd5, 0x16, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xd5, 0x16, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x32, 0x75, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x32, 0x75, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x97, 0x35, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x97, 0x35, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x10, 0x14, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x10, 0x14, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x15, 0x55, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x15, 0x55, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x97, 0x75, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x97, 0x75, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x97, 0x77, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x97, 0x77, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x15, 0x16, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x15, 0x16, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x11, 0x14, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x11, 0x14, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x10, 0x56, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x10, 0x56, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x90, 0x15, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x90, 0x15, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x11, 0x54, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x11, 0x54, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x95, 0x16, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x95, 0x16, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x12, 0x75, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x12, 0x75, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x97, 0x35, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x97, 0x35, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "udot za.d[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2/umax.s.yaml b/tests/MC/AArch64/SME2/umax.s.yaml new file mode 100644 index 0000000000..88edc93393 --- /dev/null +++ b/tests/MC/AArch64/SME2/umax.s.yaml @@ -0,0 +1,640 @@ +test_cases: + - + input: + bytes: [ 0x01, 0xa0, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z0.h, z1.h }, { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x15, 0xa0, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.h, z21.h }, { z20.h, z21.h }, z5.h" + + - + input: + bytes: [ 0x17, 0xa0, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z22.h, z23.h }, { z22.h, z23.h }, z8.h" + + - + input: + bytes: [ 0x1f, 0xa0, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z30.h, z31.h }, { z30.h, z31.h }, z15.h" + + - + input: + bytes: [ 0x01, 0xb0, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x15, 0xb0, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x17, 0xb0, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x1f, 0xb0, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x01, 0xa0, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z0.s, z1.s }, { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x15, 0xa0, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.s, z21.s }, { z20.s, z21.s }, z5.s" + + - + input: + bytes: [ 0x17, 0xa0, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z22.s, z23.s }, { z22.s, z23.s }, z8.s" + + - + input: + bytes: [ 0x1f, 0xa0, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z30.s, z31.s }, { z30.s, z31.s }, z15.s" + + - + input: + bytes: [ 0x01, 0xb0, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x15, 0xb0, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x17, 0xb0, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0x1f, 0xb0, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x01, 0xa0, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z0.d, z1.d }, { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x15, 0xa0, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.d, z21.d }, { z20.d, z21.d }, z5.d" + + - + input: + bytes: [ 0x17, 0xa0, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z22.d, z23.d }, { z22.d, z23.d }, z8.d" + + - + input: + bytes: [ 0x1f, 0xa0, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z30.d, z31.d }, { z30.d, z31.d }, z15.d" + + - + input: + bytes: [ 0x01, 0xb0, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x15, 0xb0, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x17, 0xb0, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0x1f, 0xb0, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x01, 0xa0, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z0.b, z1.b }, { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x15, 0xa0, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.b, z21.b }, { z20.b, z21.b }, z5.b" + + - + input: + bytes: [ 0x17, 0xa0, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z22.b, z23.b }, { z22.b, z23.b }, z8.b" + + - + input: + bytes: [ 0x1f, 0xa0, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z30.b, z31.b }, { z30.b, z31.b }, z15.b" + + - + input: + bytes: [ 0x01, 0xb0, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x15, 0xb0, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x17, 0xb0, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0x1f, 0xb0, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x01, 0xa8, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z0.h - z3.h }, { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x15, 0xa8, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.h - z23.h }, { z20.h - z23.h }, z5.h" + + - + input: + bytes: [ 0x15, 0xa8, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.h - z23.h }, { z20.h - z23.h }, z8.h" + + - + input: + bytes: [ 0x1d, 0xa8, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z28.h - z31.h }, { z28.h - z31.h }, z15.h" + + - + input: + bytes: [ 0x01, 0xb8, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x15, 0xb8, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x15, 0xb8, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x1d, 0xb8, 0x7c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x01, 0xa8, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z0.s - z3.s }, { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x15, 0xa8, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.s - z23.s }, { z20.s - z23.s }, z5.s" + + - + input: + bytes: [ 0x15, 0xa8, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.s - z23.s }, { z20.s - z23.s }, z8.s" + + - + input: + bytes: [ 0x1d, 0xa8, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z28.s - z31.s }, { z28.s - z31.s }, z15.s" + + - + input: + bytes: [ 0x01, 0xb8, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x15, 0xb8, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x15, 0xb8, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x1d, 0xb8, 0xbc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x01, 0xa8, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z0.d - z3.d }, { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x15, 0xa8, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.d - z23.d }, { z20.d - z23.d }, z5.d" + + - + input: + bytes: [ 0x15, 0xa8, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.d - z23.d }, { z20.d - z23.d }, z8.d" + + - + input: + bytes: [ 0x1d, 0xa8, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z28.d - z31.d }, { z28.d - z31.d }, z15.d" + + - + input: + bytes: [ 0x01, 0xb8, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x15, 0xb8, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x15, 0xb8, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x1d, 0xb8, 0xfc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x01, 0xa8, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z0.b - z3.b }, { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x15, 0xa8, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.b - z23.b }, { z20.b - z23.b }, z5.b" + + - + input: + bytes: [ 0x15, 0xa8, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.b - z23.b }, { z20.b - z23.b }, z8.b" + + - + input: + bytes: [ 0x1d, 0xa8, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z28.b - z31.b }, { z28.b - z31.b }, z15.b" + + - + input: + bytes: [ 0x01, 0xb8, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x15, 0xb8, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x15, 0xb8, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x1d, 0xb8, 0x3c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umax { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }" diff --git a/tests/MC/AArch64/SME2/umin.s.yaml b/tests/MC/AArch64/SME2/umin.s.yaml new file mode 100644 index 0000000000..bf51a548a9 --- /dev/null +++ b/tests/MC/AArch64/SME2/umin.s.yaml @@ -0,0 +1,640 @@ +test_cases: + - + input: + bytes: [ 0x21, 0xa0, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z0.h, z1.h }, { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x35, 0xa0, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.h, z21.h }, { z20.h, z21.h }, z5.h" + + - + input: + bytes: [ 0x37, 0xa0, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z22.h, z23.h }, { z22.h, z23.h }, z8.h" + + - + input: + bytes: [ 0x3f, 0xa0, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z30.h, z31.h }, { z30.h, z31.h }, z15.h" + + - + input: + bytes: [ 0x21, 0xb0, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x35, 0xb0, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x37, 0xb0, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x3f, 0xb0, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x21, 0xa0, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z0.s, z1.s }, { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x35, 0xa0, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.s, z21.s }, { z20.s, z21.s }, z5.s" + + - + input: + bytes: [ 0x37, 0xa0, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z22.s, z23.s }, { z22.s, z23.s }, z8.s" + + - + input: + bytes: [ 0x3f, 0xa0, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z30.s, z31.s }, { z30.s, z31.s }, z15.s" + + - + input: + bytes: [ 0x21, 0xb0, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x35, 0xb0, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x37, 0xb0, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0x3f, 0xb0, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x21, 0xa0, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z0.d, z1.d }, { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x35, 0xa0, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.d, z21.d }, { z20.d, z21.d }, z5.d" + + - + input: + bytes: [ 0x37, 0xa0, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z22.d, z23.d }, { z22.d, z23.d }, z8.d" + + - + input: + bytes: [ 0x3f, 0xa0, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z30.d, z31.d }, { z30.d, z31.d }, z15.d" + + - + input: + bytes: [ 0x21, 0xb0, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x35, 0xb0, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x37, 0xb0, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0x3f, 0xb0, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x21, 0xa0, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z0.b, z1.b }, { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x35, 0xa0, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.b, z21.b }, { z20.b, z21.b }, z5.b" + + - + input: + bytes: [ 0x37, 0xa0, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z22.b, z23.b }, { z22.b, z23.b }, z8.b" + + - + input: + bytes: [ 0x3f, 0xa0, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z30.b, z31.b }, { z30.b, z31.b }, z15.b" + + - + input: + bytes: [ 0x21, 0xb0, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x35, 0xb0, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x37, 0xb0, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0x3f, 0xb0, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x21, 0xa8, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z0.h - z3.h }, { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x35, 0xa8, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.h - z23.h }, { z20.h - z23.h }, z5.h" + + - + input: + bytes: [ 0x35, 0xa8, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.h - z23.h }, { z20.h - z23.h }, z8.h" + + - + input: + bytes: [ 0x3d, 0xa8, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z28.h - z31.h }, { z28.h - z31.h }, z15.h" + + - + input: + bytes: [ 0x21, 0xb8, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x35, 0xb8, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x35, 0xb8, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x3d, 0xb8, 0x7c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x21, 0xa8, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z0.s - z3.s }, { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x35, 0xa8, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.s - z23.s }, { z20.s - z23.s }, z5.s" + + - + input: + bytes: [ 0x35, 0xa8, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.s - z23.s }, { z20.s - z23.s }, z8.s" + + - + input: + bytes: [ 0x3d, 0xa8, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z28.s - z31.s }, { z28.s - z31.s }, z15.s" + + - + input: + bytes: [ 0x21, 0xb8, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x35, 0xb8, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x35, 0xb8, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x3d, 0xb8, 0xbc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x21, 0xa8, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z0.d - z3.d }, { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x35, 0xa8, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.d - z23.d }, { z20.d - z23.d }, z5.d" + + - + input: + bytes: [ 0x35, 0xa8, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.d - z23.d }, { z20.d - z23.d }, z8.d" + + - + input: + bytes: [ 0x3d, 0xa8, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z28.d - z31.d }, { z28.d - z31.d }, z15.d" + + - + input: + bytes: [ 0x21, 0xb8, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x35, 0xb8, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x35, 0xb8, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x3d, 0xb8, 0xfc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x21, 0xa8, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z0.b - z3.b }, { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x35, 0xa8, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.b - z23.b }, { z20.b - z23.b }, z5.b" + + - + input: + bytes: [ 0x35, 0xa8, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.b - z23.b }, { z20.b - z23.b }, z8.b" + + - + input: + bytes: [ 0x3d, 0xa8, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z28.b - z31.b }, { z28.b - z31.b }, z15.b" + + - + input: + bytes: [ 0x21, 0xb8, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x35, 0xb8, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x35, 0xb8, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x3d, 0xb8, 0x3c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umin { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }" diff --git a/tests/MC/AArch64/SME2/umlal.s.yaml b/tests/MC/AArch64/SME2/umlal.s.yaml new file mode 100644 index 0000000000..3da9c6d53f --- /dev/null +++ b/tests/MC/AArch64/SME2/umlal.s.yaml @@ -0,0 +1,1680 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x0c, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1], z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x4d, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 10:11], z10.h, z5.h" + + - + input: + bytes: [ 0xb7, 0x6d, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 14:15], z13.h, z8.h" + + - + input: + bytes: [ 0xf7, 0x6f, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 14:15], z31.h, z15.h" + + - + input: + bytes: [ 0x35, 0x0e, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 10:11], z17.h, z0.h" + + - + input: + bytes: [ 0x31, 0x0c, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3], z1.h, z14.h" + + - + input: + bytes: [ 0x70, 0x4e, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 0:1], z19.h, z4.h" + + - + input: + bytes: [ 0x90, 0x0d, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1], z12.h, z2.h" + + - + input: + bytes: [ 0x31, 0x4c, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3], z1.h, z10.h" + + - + input: + bytes: [ 0xd5, 0x0e, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 10:11], z22.h, z14.h" + + - + input: + bytes: [ 0x32, 0x6d, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 4:5], z9.h, z1.h" + + - + input: + bytes: [ 0x97, 0x2d, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w9, 14:15], z12.h, z11.h" + + - + input: + bytes: [ 0x10, 0x10, 0xc0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1], z0.h, z0.h[0]" + + - + input: + bytes: [ 0x55, 0x55, 0xc5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 10:11], z10.h, z5.h[1]" + + - + input: + bytes: [ 0xb7, 0xfd, 0xc8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 14:15], z13.h, z8.h[7]" + + - + input: + bytes: [ 0xf7, 0xff, 0xcf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 14:15], z31.h, z15.h[7]" + + - + input: + bytes: [ 0x35, 0x1e, 0xc0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 10:11], z17.h, z0.h[3]" + + - + input: + bytes: [ 0x31, 0x94, 0xce, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3], z1.h, z14.h[5]" + + - + input: + bytes: [ 0x70, 0x56, 0xc4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 0:1], z19.h, z4.h[1]" + + - + input: + bytes: [ 0x90, 0x19, 0xc2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1], z12.h, z2.h[2]" + + - + input: + bytes: [ 0x31, 0xd8, 0xca, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3], z1.h, z10.h[6]" + + - + input: + bytes: [ 0xd5, 0x1a, 0xce, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 10:11], z22.h, z14.h[2]" + + - + input: + bytes: [ 0x32, 0xf5, 0xc1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 4:5], z9.h, z1.h[5]" + + - + input: + bytes: [ 0x97, 0xb9, 0xcb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w9, 14:15], z12.h, z11.h[6]" + + - + input: + bytes: [ 0x10, 0x08, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x10, 0x08, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x51, 0x49, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x51, 0x49, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xb3, 0x69, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xb3, 0x69, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xf3, 0x6b, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xf3, 0x6b, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x31, 0x0a, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x31, 0x0a, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x31, 0x08, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x31, 0x08, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x70, 0x4a, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x70, 0x4a, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x90, 0x09, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x90, 0x09, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x31, 0x48, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x31, 0x48, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xd1, 0x0a, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xd1, 0x0a, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x32, 0x69, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x32, 0x69, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x93, 0x29, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x93, 0x29, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x10, 0x10, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x10, 0x10, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x55, 0x55, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x55, 0x55, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x97, 0x7d, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0x97, 0x7d, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0xd7, 0x7f, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0xd7, 0x7f, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x15, 0x1e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]" + + - + input: + bytes: [ 0x15, 0x1e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]" + + - + input: + bytes: [ 0x11, 0x14, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x11, 0x14, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x50, 0x56, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x50, 0x56, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x90, 0x19, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x90, 0x19, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x11, 0x58, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0x11, 0x58, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0xd5, 0x1a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0xd5, 0x1a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x12, 0x75, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x12, 0x75, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x97, 0x39, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]" + + - + input: + bytes: [ 0x97, 0x39, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]" + + - + input: + bytes: [ 0x10, 0x08, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x10, 0x08, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x51, 0x49, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x51, 0x49, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x93, 0x69, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x93, 0x69, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xd3, 0x6b, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xd3, 0x6b, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x11, 0x0a, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x11, 0x0a, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x11, 0x08, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x11, 0x08, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x50, 0x4a, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x50, 0x4a, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x90, 0x09, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x90, 0x09, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x11, 0x48, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x11, 0x48, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xd1, 0x0a, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xd1, 0x0a, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x12, 0x69, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x12, 0x69, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x93, 0x29, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x93, 0x29, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x10, 0x08, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x10, 0x08, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x51, 0x49, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x51, 0x49, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xb3, 0x69, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xb3, 0x69, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xf3, 0x6b, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xf3, 0x6b, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x31, 0x0a, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x31, 0x0a, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x31, 0x08, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x31, 0x08, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x70, 0x4a, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x70, 0x4a, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x90, 0x09, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x90, 0x09, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x31, 0x48, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x31, 0x48, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xd1, 0x0a, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xd1, 0x0a, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x32, 0x69, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x32, 0x69, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x93, 0x29, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x93, 0x29, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x10, 0x90, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x10, 0x90, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x15, 0xd5, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x15, 0xd5, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x97, 0xfd, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x97, 0xfd, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x97, 0xff, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x97, 0xff, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x15, 0x9e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]" + + - + input: + bytes: [ 0x15, 0x9e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]" + + - + input: + bytes: [ 0x11, 0x94, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x11, 0x94, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x10, 0xd6, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x10, 0xd6, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x90, 0x99, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x90, 0x99, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x11, 0xd8, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x11, 0xd8, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x95, 0x9a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x95, 0x9a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x12, 0xf5, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x12, 0xf5, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x97, 0xb9, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]" + + - + input: + bytes: [ 0x97, 0xb9, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]" + + - + input: + bytes: [ 0x10, 0x08, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x10, 0x08, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x11, 0x49, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x11, 0x49, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x93, 0x69, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x93, 0x69, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x93, 0x6b, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x93, 0x6b, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x11, 0x0a, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x11, 0x0a, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x11, 0x08, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x11, 0x08, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x10, 0x4a, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x10, 0x4a, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x90, 0x09, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x90, 0x09, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x11, 0x48, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x11, 0x48, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x91, 0x0a, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x91, 0x0a, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x12, 0x69, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x12, 0x69, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x93, 0x29, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x93, 0x29, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2/umlall.s.yaml b/tests/MC/AArch64/SME2/umlall.s.yaml new file mode 100644 index 0000000000..da40815765 --- /dev/null +++ b/tests/MC/AArch64/SME2/umlall.s.yaml @@ -0,0 +1,3360 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x04, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3], z0.b, z0.b" + + - + input: + bytes: [ 0x51, 0x45, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7], z10.b, z5.b" + + - + input: + bytes: [ 0xb3, 0x65, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 12:15], z13.b, z8.b" + + - + input: + bytes: [ 0xf3, 0x67, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 12:15], z31.b, z15.b" + + - + input: + bytes: [ 0x31, 0x06, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7], z17.b, z0.b" + + - + input: + bytes: [ 0x31, 0x04, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7], z1.b, z14.b" + + - + input: + bytes: [ 0x70, 0x46, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 0:3], z19.b, z4.b" + + - + input: + bytes: [ 0x90, 0x05, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3], z12.b, z2.b" + + - + input: + bytes: [ 0x31, 0x44, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7], z1.b, z10.b" + + - + input: + bytes: [ 0xd1, 0x06, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7], z22.b, z14.b" + + - + input: + bytes: [ 0x32, 0x65, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 8:11], z9.b, z1.b" + + - + input: + bytes: [ 0x93, 0x25, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w9, 12:15], z12.b, z11.b" + + - + input: + bytes: [ 0x10, 0x00, 0x00, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3], z0.b, z0.b[0]" + + - + input: + bytes: [ 0x51, 0x55, 0x05, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7], z10.b, z5.b[5]" + + - + input: + bytes: [ 0xb3, 0xed, 0x08, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 12:15], z13.b, z8.b[11]" + + - + input: + bytes: [ 0xf3, 0xff, 0x0f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 12:15], z31.b, z15.b[15]" + + - + input: + bytes: [ 0x31, 0x0e, 0x00, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7], z17.b, z0.b[3]" + + - + input: + bytes: [ 0x31, 0x84, 0x0e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7], z1.b, z14.b[9]" + + - + input: + bytes: [ 0x70, 0x56, 0x04, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 0:3], z19.b, z4.b[5]" + + - + input: + bytes: [ 0x90, 0x19, 0x02, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3], z12.b, z2.b[6]" + + - + input: + bytes: [ 0x31, 0xc8, 0x0a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7], z1.b, z10.b[10]" + + - + input: + bytes: [ 0xd1, 0x0a, 0x0e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7], z22.b, z14.b[2]" + + - + input: + bytes: [ 0x32, 0xf5, 0x01, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 8:11], z9.b, z1.b[13]" + + - + input: + bytes: [ 0x93, 0xa9, 0x0b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w9, 12:15], z12.b, z11.b[10]" + + - + input: + bytes: [ 0x10, 0x04, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3], z0.h, z0.h" + + - + input: + bytes: [ 0x51, 0x45, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7], z10.h, z5.h" + + - + input: + bytes: [ 0xb3, 0x65, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 12:15], z13.h, z8.h" + + - + input: + bytes: [ 0xf3, 0x67, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 12:15], z31.h, z15.h" + + - + input: + bytes: [ 0x31, 0x06, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7], z17.h, z0.h" + + - + input: + bytes: [ 0x31, 0x04, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7], z1.h, z14.h" + + - + input: + bytes: [ 0x70, 0x46, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 0:3], z19.h, z4.h" + + - + input: + bytes: [ 0x90, 0x05, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3], z12.h, z2.h" + + - + input: + bytes: [ 0x31, 0x44, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7], z1.h, z10.h" + + - + input: + bytes: [ 0xd1, 0x06, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7], z22.h, z14.h" + + - + input: + bytes: [ 0x32, 0x65, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 8:11], z9.h, z1.h" + + - + input: + bytes: [ 0x93, 0x25, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w9, 12:15], z12.h, z11.h" + + - + input: + bytes: [ 0x10, 0x00, 0x80, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3], z0.h, z0.h[0]" + + - + input: + bytes: [ 0x51, 0x45, 0x85, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7], z10.h, z5.h[1]" + + - + input: + bytes: [ 0xb3, 0xed, 0x88, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 12:15], z13.h, z8.h[7]" + + - + input: + bytes: [ 0xf3, 0xef, 0x8f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 12:15], z31.h, z15.h[7]" + + - + input: + bytes: [ 0x31, 0x0e, 0x80, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7], z17.h, z0.h[3]" + + - + input: + bytes: [ 0x31, 0x84, 0x8e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7], z1.h, z14.h[5]" + + - + input: + bytes: [ 0x70, 0x46, 0x84, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 0:3], z19.h, z4.h[1]" + + - + input: + bytes: [ 0x90, 0x09, 0x82, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3], z12.h, z2.h[2]" + + - + input: + bytes: [ 0x31, 0xc8, 0x8a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7], z1.h, z10.h[6]" + + - + input: + bytes: [ 0xd1, 0x0a, 0x8e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7], z22.h, z14.h[2]" + + - + input: + bytes: [ 0x32, 0xe5, 0x81, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 8:11], z9.h, z1.h[5]" + + - + input: + bytes: [ 0x93, 0xa9, 0x8b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w9, 12:15], z12.h, z11.h[6]" + + - + input: + bytes: [ 0x10, 0x00, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x10, 0x00, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x51, 0x41, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0x51, 0x41, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0xb1, 0x61, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xb1, 0x61, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xf1, 0x63, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0xf1, 0x63, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0x31, 0x02, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x31, 0x02, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x31, 0x00, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x31, 0x00, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x70, 0x42, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 0:3, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x70, 0x42, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 0:3, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x90, 0x01, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x90, 0x01, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x31, 0x40, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0x31, 0x40, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0xd1, 0x02, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0xd1, 0x02, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0x30, 0x61, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 0:3, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x30, 0x61, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 0:3, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x91, 0x21, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x91, 0x21, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x10, 0x00, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x10, 0x00, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x55, 0x45, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x55, 0x45, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x97, 0x6d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]" + + - + input: + bytes: [ 0x97, 0x6d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]" + + - + input: + bytes: [ 0xd7, 0x6f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]" + + - + input: + bytes: [ 0xd7, 0x6f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]" + + - + input: + bytes: [ 0x15, 0x0e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]" + + - + input: + bytes: [ 0x15, 0x0e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]" + + - + input: + bytes: [ 0x11, 0x04, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]" + + - + input: + bytes: [ 0x11, 0x04, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]" + + - + input: + bytes: [ 0x50, 0x46, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x50, 0x46, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x90, 0x09, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]" + + - + input: + bytes: [ 0x90, 0x09, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]" + + - + input: + bytes: [ 0x11, 0x48, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]" + + - + input: + bytes: [ 0x11, 0x48, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]" + + - + input: + bytes: [ 0xd5, 0x0a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]" + + - + input: + bytes: [ 0xd5, 0x0a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]" + + - + input: + bytes: [ 0x12, 0x65, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]" + + - + input: + bytes: [ 0x12, 0x65, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]" + + - + input: + bytes: [ 0x97, 0x29, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]" + + - + input: + bytes: [ 0x97, 0x29, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]" + + - + input: + bytes: [ 0x10, 0x00, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x10, 0x00, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x51, 0x41, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x51, 0x41, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x91, 0x61, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0x91, 0x61, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0xd1, 0x63, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xd1, 0x63, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x11, 0x02, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }" + + - + input: + bytes: [ 0x11, 0x02, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }" + + - + input: + bytes: [ 0x11, 0x00, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x11, 0x00, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x50, 0x42, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x50, 0x42, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x90, 0x01, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }" + + - + input: + bytes: [ 0x90, 0x01, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }" + + - + input: + bytes: [ 0x11, 0x40, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }" + + - + input: + bytes: [ 0x11, 0x40, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }" + + - + input: + bytes: [ 0xd1, 0x02, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xd1, 0x02, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x10, 0x61, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x10, 0x61, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x91, 0x21, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }" + + - + input: + bytes: [ 0x91, 0x21, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }" + + - + input: + bytes: [ 0x10, 0x00, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x10, 0x00, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x51, 0x41, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x51, 0x41, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xb1, 0x61, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xb1, 0x61, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xf1, 0x63, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xf1, 0x63, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x31, 0x02, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x31, 0x02, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x31, 0x00, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x31, 0x00, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x70, 0x42, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 0:3, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x70, 0x42, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 0:3, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x90, 0x01, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x90, 0x01, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x31, 0x40, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x31, 0x40, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xd1, 0x02, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xd1, 0x02, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x30, 0x61, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 0:3, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x30, 0x61, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 0:3, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x91, 0x21, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x91, 0x21, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x10, 0x00, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x10, 0x00, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x55, 0x45, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h[6]" + + - + input: + bytes: [ 0x55, 0x45, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h[6]" + + - + input: + bytes: [ 0x97, 0x65, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0x97, 0x65, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0xd7, 0x67, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0xd7, 0x67, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x15, 0x06, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx2], { z16.h, z17.h }, z0.h[6]" + + - + input: + bytes: [ 0x15, 0x06, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx2], { z16.h, z17.h }, z0.h[6]" + + - + input: + bytes: [ 0x11, 0x04, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx2], { z0.h, z1.h }, z14.h[4]" + + - + input: + bytes: [ 0x11, 0x04, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx2], { z0.h, z1.h }, z14.h[4]" + + - + input: + bytes: [ 0x50, 0x46, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 0:3, vgx2], { z18.h, z19.h }, z4.h[4]" + + - + input: + bytes: [ 0x50, 0x46, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 0:3, vgx2], { z18.h, z19.h }, z4.h[4]" + + - + input: + bytes: [ 0x90, 0x01, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h[0]" + + - + input: + bytes: [ 0x90, 0x01, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h[0]" + + - + input: + bytes: [ 0x11, 0x40, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx2], { z0.h, z1.h }, z10.h[0]" + + - + input: + bytes: [ 0x11, 0x40, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx2], { z0.h, z1.h }, z10.h[0]" + + - + input: + bytes: [ 0xd5, 0x02, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0xd5, 0x02, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x12, 0x65, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 0:3, vgx2], { z8.h, z9.h }, z1.h[5]" + + - + input: + bytes: [ 0x12, 0x65, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 0:3, vgx2], { z8.h, z9.h }, z1.h[5]" + + - + input: + bytes: [ 0x97, 0x21, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h[3]" + + - + input: + bytes: [ 0x97, 0x21, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h[3]" + + - + input: + bytes: [ 0x10, 0x00, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x10, 0x00, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x51, 0x41, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x51, 0x41, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x91, 0x61, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x91, 0x61, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xd1, 0x63, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xd1, 0x63, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x11, 0x02, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x11, 0x02, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x11, 0x00, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x11, 0x00, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x50, 0x42, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 0:3, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x50, 0x42, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 0:3, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x90, 0x01, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x90, 0x01, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x11, 0x40, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x11, 0x40, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xd1, 0x02, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xd1, 0x02, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x10, 0x61, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 0:3, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x10, 0x61, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 0:3, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x91, 0x21, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x91, 0x21, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x10, 0x00, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x10, 0x00, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x51, 0x41, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0x51, 0x41, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0xb1, 0x61, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xb1, 0x61, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xf1, 0x63, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0xf1, 0x63, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0x31, 0x02, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x31, 0x02, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x31, 0x00, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x31, 0x00, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x70, 0x42, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 0:3, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x70, 0x42, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 0:3, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x90, 0x01, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x90, 0x01, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x31, 0x40, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0x31, 0x40, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0xd1, 0x02, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0xd1, 0x02, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0x30, 0x61, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 0:3, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x30, 0x61, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 0:3, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x91, 0x21, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x91, 0x21, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x10, 0x80, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x10, 0x80, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x15, 0xc5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x15, 0xc5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x97, 0xed, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]" + + - + input: + bytes: [ 0x97, 0xed, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]" + + - + input: + bytes: [ 0x97, 0xef, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]" + + - + input: + bytes: [ 0x97, 0xef, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]" + + - + input: + bytes: [ 0x15, 0x8e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]" + + - + input: + bytes: [ 0x15, 0x8e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]" + + - + input: + bytes: [ 0x11, 0x84, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]" + + - + input: + bytes: [ 0x11, 0x84, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]" + + - + input: + bytes: [ 0x10, 0xc6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x10, 0xc6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x90, 0x89, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]" + + - + input: + bytes: [ 0x90, 0x89, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]" + + - + input: + bytes: [ 0x11, 0xc8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]" + + - + input: + bytes: [ 0x11, 0xc8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]" + + - + input: + bytes: [ 0x95, 0x8a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]" + + - + input: + bytes: [ 0x95, 0x8a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]" + + - + input: + bytes: [ 0x12, 0xe5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]" + + - + input: + bytes: [ 0x12, 0xe5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]" + + - + input: + bytes: [ 0x97, 0xa9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]" + + - + input: + bytes: [ 0x97, 0xa9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]" + + - + input: + bytes: [ 0x10, 0x00, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x10, 0x00, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x11, 0x41, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x11, 0x41, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x91, 0x61, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x91, 0x61, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x91, 0x63, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x91, 0x63, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x11, 0x02, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }" + + - + input: + bytes: [ 0x11, 0x02, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }" + + - + input: + bytes: [ 0x11, 0x00, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x11, 0x00, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x10, 0x42, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x10, 0x42, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x90, 0x01, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x90, 0x01, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x11, 0x40, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }" + + - + input: + bytes: [ 0x11, 0x40, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }" + + - + input: + bytes: [ 0x91, 0x02, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x91, 0x02, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x10, 0x61, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x10, 0x61, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x91, 0x21, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x91, 0x21, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x10, 0x00, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x10, 0x00, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x51, 0x41, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x51, 0x41, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xb1, 0x61, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xb1, 0x61, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xf1, 0x63, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xf1, 0x63, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x31, 0x02, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x31, 0x02, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x31, 0x00, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x31, 0x00, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x70, 0x42, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 0:3, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x70, 0x42, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 0:3, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x90, 0x01, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x90, 0x01, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x31, 0x40, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x31, 0x40, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xd1, 0x02, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xd1, 0x02, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x30, 0x61, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 0:3, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x30, 0x61, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 0:3, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x91, 0x21, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x91, 0x21, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x10, 0x80, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x10, 0x80, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x15, 0xc5, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx4], { z8.h - z11.h }, z5.h[6]" + + - + input: + bytes: [ 0x15, 0xc5, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx4], { z8.h - z11.h }, z5.h[6]" + + - + input: + bytes: [ 0x97, 0xe5, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x97, 0xe5, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x97, 0xe7, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x97, 0xe7, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x15, 0x86, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx4], { z16.h - z19.h }, z0.h[6]" + + - + input: + bytes: [ 0x15, 0x86, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx4], { z16.h - z19.h }, z0.h[6]" + + - + input: + bytes: [ 0x11, 0x84, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx4], { z0.h - z3.h }, z14.h[4]" + + - + input: + bytes: [ 0x11, 0x84, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx4], { z0.h - z3.h }, z14.h[4]" + + - + input: + bytes: [ 0x10, 0xc6, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 0:3, vgx4], { z16.h - z19.h }, z4.h[4]" + + - + input: + bytes: [ 0x10, 0xc6, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 0:3, vgx4], { z16.h - z19.h }, z4.h[4]" + + - + input: + bytes: [ 0x90, 0x81, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h[0]" + + - + input: + bytes: [ 0x90, 0x81, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h[0]" + + - + input: + bytes: [ 0x11, 0xc0, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx4], { z0.h - z3.h }, z10.h[0]" + + - + input: + bytes: [ 0x11, 0xc0, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx4], { z0.h - z3.h }, z10.h[0]" + + - + input: + bytes: [ 0x95, 0x82, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx4], { z20.h - z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x95, 0x82, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx4], { z20.h - z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x12, 0xe5, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 0:3, vgx4], { z8.h - z11.h }, z1.h[5]" + + - + input: + bytes: [ 0x12, 0xe5, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 0:3, vgx4], { z8.h - z11.h }, z1.h[5]" + + - + input: + bytes: [ 0x97, 0xa1, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h[3]" + + - + input: + bytes: [ 0x97, 0xa1, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h[3]" + + - + input: + bytes: [ 0x10, 0x00, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x10, 0x00, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x11, 0x41, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x11, 0x41, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x91, 0x61, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x91, 0x61, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x91, 0x63, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x91, 0x63, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 4:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x11, 0x02, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x11, 0x02, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x11, 0x00, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x11, 0x00, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x10, 0x42, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 0:3, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x10, 0x42, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 0:3, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x90, 0x01, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x90, 0x01, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x11, 0x40, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x11, 0x40, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w10, 4:7, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x91, 0x02, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x91, 0x02, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w8, 4:7, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x10, 0x61, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 0:3, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x10, 0x61, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w11, 0:3, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x91, 0x21, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x91, 0x21, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2/umlsl.s.yaml b/tests/MC/AArch64/SME2/umlsl.s.yaml new file mode 100644 index 0000000000..fd9b404216 --- /dev/null +++ b/tests/MC/AArch64/SME2/umlsl.s.yaml @@ -0,0 +1,1680 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x0c, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1], z0.h, z0.h" + + - + input: + bytes: [ 0x5d, 0x4d, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 10:11], z10.h, z5.h" + + - + input: + bytes: [ 0xbf, 0x6d, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 14:15], z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0x6f, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 14:15], z31.h, z15.h" + + - + input: + bytes: [ 0x3d, 0x0e, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 10:11], z17.h, z0.h" + + - + input: + bytes: [ 0x39, 0x0c, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3], z1.h, z14.h" + + - + input: + bytes: [ 0x78, 0x4e, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 0:1], z19.h, z4.h" + + - + input: + bytes: [ 0x98, 0x0d, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1], z12.h, z2.h" + + - + input: + bytes: [ 0x39, 0x4c, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3], z1.h, z10.h" + + - + input: + bytes: [ 0xdd, 0x0e, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 10:11], z22.h, z14.h" + + - + input: + bytes: [ 0x3a, 0x6d, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 4:5], z9.h, z1.h" + + - + input: + bytes: [ 0x9f, 0x2d, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w9, 14:15], z12.h, z11.h" + + - + input: + bytes: [ 0x18, 0x10, 0xc0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1], z0.h, z0.h[0]" + + - + input: + bytes: [ 0x5d, 0x55, 0xc5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 10:11], z10.h, z5.h[1]" + + - + input: + bytes: [ 0xbf, 0xfd, 0xc8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 14:15], z13.h, z8.h[7]" + + - + input: + bytes: [ 0xff, 0xff, 0xcf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 14:15], z31.h, z15.h[7]" + + - + input: + bytes: [ 0x3d, 0x1e, 0xc0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 10:11], z17.h, z0.h[3]" + + - + input: + bytes: [ 0x39, 0x94, 0xce, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3], z1.h, z14.h[5]" + + - + input: + bytes: [ 0x78, 0x56, 0xc4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 0:1], z19.h, z4.h[1]" + + - + input: + bytes: [ 0x98, 0x19, 0xc2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1], z12.h, z2.h[2]" + + - + input: + bytes: [ 0x39, 0xd8, 0xca, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3], z1.h, z10.h[6]" + + - + input: + bytes: [ 0xdd, 0x1a, 0xce, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 10:11], z22.h, z14.h[2]" + + - + input: + bytes: [ 0x3a, 0xf5, 0xc1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 4:5], z9.h, z1.h[5]" + + - + input: + bytes: [ 0x9f, 0xb9, 0xcb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w9, 14:15], z12.h, z11.h[6]" + + - + input: + bytes: [ 0x18, 0x08, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x18, 0x08, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x59, 0x49, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x59, 0x49, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xbb, 0x69, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xbb, 0x69, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xfb, 0x6b, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xfb, 0x6b, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x39, 0x0a, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x39, 0x0a, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x39, 0x08, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x39, 0x08, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x78, 0x4a, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x78, 0x4a, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x98, 0x09, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x98, 0x09, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x39, 0x48, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x39, 0x48, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xd9, 0x0a, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xd9, 0x0a, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x3a, 0x69, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x3a, 0x69, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x9b, 0x29, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x9b, 0x29, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x18, 0x10, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x18, 0x10, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x5d, 0x55, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x5d, 0x55, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x9f, 0x7d, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0x9f, 0x7d, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0xdf, 0x7f, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0xdf, 0x7f, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x1d, 0x1e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]" + + - + input: + bytes: [ 0x1d, 0x1e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]" + + - + input: + bytes: [ 0x19, 0x14, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x19, 0x14, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x58, 0x56, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x58, 0x56, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x98, 0x19, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x98, 0x19, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x19, 0x58, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0x19, 0x58, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0xdd, 0x1a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0xdd, 0x1a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x1a, 0x75, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x1a, 0x75, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x9f, 0x39, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]" + + - + input: + bytes: [ 0x9f, 0x39, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]" + + - + input: + bytes: [ 0x18, 0x08, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x18, 0x08, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x59, 0x49, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x59, 0x49, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x9b, 0x69, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x9b, 0x69, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xdb, 0x6b, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xdb, 0x6b, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x19, 0x0a, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x19, 0x0a, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x19, 0x08, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x19, 0x08, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x58, 0x4a, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x58, 0x4a, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x98, 0x09, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x98, 0x09, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x19, 0x48, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x19, 0x48, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xd9, 0x0a, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xd9, 0x0a, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x1a, 0x69, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x1a, 0x69, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x9b, 0x29, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x9b, 0x29, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x18, 0x08, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x18, 0x08, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x59, 0x49, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x59, 0x49, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xbb, 0x69, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xbb, 0x69, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xfb, 0x6b, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xfb, 0x6b, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x39, 0x0a, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x39, 0x0a, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x39, 0x08, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x39, 0x08, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x78, 0x4a, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x78, 0x4a, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x98, 0x09, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x98, 0x09, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x39, 0x48, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x39, 0x48, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xd9, 0x0a, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xd9, 0x0a, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x3a, 0x69, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x3a, 0x69, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x9b, 0x29, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x9b, 0x29, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x18, 0x90, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x18, 0x90, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x1d, 0xd5, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x1d, 0xd5, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]" + + - + input: + bytes: [ 0x9f, 0xfd, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x9f, 0xfd, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x9f, 0xff, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x9f, 0xff, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x1d, 0x9e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]" + + - + input: + bytes: [ 0x1d, 0x9e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]" + + - + input: + bytes: [ 0x19, 0x94, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x19, 0x94, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x18, 0xd6, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x18, 0xd6, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]" + + - + input: + bytes: [ 0x98, 0x99, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x98, 0x99, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x19, 0xd8, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x19, 0xd8, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x9d, 0x9a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x9d, 0x9a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x1a, 0xf5, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x1a, 0xf5, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x9f, 0xb9, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]" + + - + input: + bytes: [ 0x9f, 0xb9, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]" + + - + input: + bytes: [ 0x18, 0x08, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x18, 0x08, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x19, 0x49, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x19, 0x49, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x9b, 0x69, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x9b, 0x69, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x9b, 0x6b, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x9b, 0x6b, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x19, 0x0a, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x19, 0x0a, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x19, 0x08, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x19, 0x08, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x18, 0x4a, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x18, 0x4a, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x98, 0x09, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x98, 0x09, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x19, 0x48, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x19, 0x48, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x99, 0x0a, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x99, 0x0a, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x1a, 0x69, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x1a, 0x69, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x9b, 0x29, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x9b, 0x29, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2/umlsll.s.yaml b/tests/MC/AArch64/SME2/umlsll.s.yaml new file mode 100644 index 0000000000..df3a568444 --- /dev/null +++ b/tests/MC/AArch64/SME2/umlsll.s.yaml @@ -0,0 +1,3360 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x04, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3], z0.b, z0.b" + + - + input: + bytes: [ 0x59, 0x45, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7], z10.b, z5.b" + + - + input: + bytes: [ 0xbb, 0x65, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 12:15], z13.b, z8.b" + + - + input: + bytes: [ 0xfb, 0x67, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 12:15], z31.b, z15.b" + + - + input: + bytes: [ 0x39, 0x06, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7], z17.b, z0.b" + + - + input: + bytes: [ 0x39, 0x04, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7], z1.b, z14.b" + + - + input: + bytes: [ 0x78, 0x46, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 0:3], z19.b, z4.b" + + - + input: + bytes: [ 0x98, 0x05, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3], z12.b, z2.b" + + - + input: + bytes: [ 0x39, 0x44, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7], z1.b, z10.b" + + - + input: + bytes: [ 0xd9, 0x06, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7], z22.b, z14.b" + + - + input: + bytes: [ 0x3a, 0x65, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 8:11], z9.b, z1.b" + + - + input: + bytes: [ 0x9b, 0x25, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w9, 12:15], z12.b, z11.b" + + - + input: + bytes: [ 0x18, 0x00, 0x00, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3], z0.b, z0.b[0]" + + - + input: + bytes: [ 0x59, 0x55, 0x05, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7], z10.b, z5.b[5]" + + - + input: + bytes: [ 0xbb, 0xed, 0x08, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 12:15], z13.b, z8.b[11]" + + - + input: + bytes: [ 0xfb, 0xff, 0x0f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 12:15], z31.b, z15.b[15]" + + - + input: + bytes: [ 0x39, 0x0e, 0x00, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7], z17.b, z0.b[3]" + + - + input: + bytes: [ 0x39, 0x84, 0x0e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7], z1.b, z14.b[9]" + + - + input: + bytes: [ 0x78, 0x56, 0x04, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 0:3], z19.b, z4.b[5]" + + - + input: + bytes: [ 0x98, 0x19, 0x02, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3], z12.b, z2.b[6]" + + - + input: + bytes: [ 0x39, 0xc8, 0x0a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7], z1.b, z10.b[10]" + + - + input: + bytes: [ 0xd9, 0x0a, 0x0e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7], z22.b, z14.b[2]" + + - + input: + bytes: [ 0x3a, 0xf5, 0x01, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 8:11], z9.b, z1.b[13]" + + - + input: + bytes: [ 0x9b, 0xa9, 0x0b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w9, 12:15], z12.b, z11.b[10]" + + - + input: + bytes: [ 0x18, 0x04, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3], z0.h, z0.h" + + - + input: + bytes: [ 0x59, 0x45, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7], z10.h, z5.h" + + - + input: + bytes: [ 0xbb, 0x65, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 12:15], z13.h, z8.h" + + - + input: + bytes: [ 0xfb, 0x67, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 12:15], z31.h, z15.h" + + - + input: + bytes: [ 0x39, 0x06, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7], z17.h, z0.h" + + - + input: + bytes: [ 0x39, 0x04, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7], z1.h, z14.h" + + - + input: + bytes: [ 0x78, 0x46, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 0:3], z19.h, z4.h" + + - + input: + bytes: [ 0x98, 0x05, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3], z12.h, z2.h" + + - + input: + bytes: [ 0x39, 0x44, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7], z1.h, z10.h" + + - + input: + bytes: [ 0xd9, 0x06, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7], z22.h, z14.h" + + - + input: + bytes: [ 0x3a, 0x65, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 8:11], z9.h, z1.h" + + - + input: + bytes: [ 0x9b, 0x25, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w9, 12:15], z12.h, z11.h" + + - + input: + bytes: [ 0x18, 0x00, 0x80, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3], z0.h, z0.h[0]" + + - + input: + bytes: [ 0x59, 0x45, 0x85, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7], z10.h, z5.h[1]" + + - + input: + bytes: [ 0xbb, 0xed, 0x88, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 12:15], z13.h, z8.h[7]" + + - + input: + bytes: [ 0xfb, 0xef, 0x8f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 12:15], z31.h, z15.h[7]" + + - + input: + bytes: [ 0x39, 0x0e, 0x80, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7], z17.h, z0.h[3]" + + - + input: + bytes: [ 0x39, 0x84, 0x8e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7], z1.h, z14.h[5]" + + - + input: + bytes: [ 0x78, 0x46, 0x84, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 0:3], z19.h, z4.h[1]" + + - + input: + bytes: [ 0x98, 0x09, 0x82, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3], z12.h, z2.h[2]" + + - + input: + bytes: [ 0x39, 0xc8, 0x8a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7], z1.h, z10.h[6]" + + - + input: + bytes: [ 0xd9, 0x0a, 0x8e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7], z22.h, z14.h[2]" + + - + input: + bytes: [ 0x3a, 0xe5, 0x81, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 8:11], z9.h, z1.h[5]" + + - + input: + bytes: [ 0x9b, 0xa9, 0x8b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w9, 12:15], z12.h, z11.h[6]" + + - + input: + bytes: [ 0x18, 0x00, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x18, 0x00, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x59, 0x41, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0x59, 0x41, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0xb9, 0x61, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xb9, 0x61, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xf9, 0x63, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0xf9, 0x63, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0x39, 0x02, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x39, 0x02, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x39, 0x00, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x39, 0x00, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x78, 0x42, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 0:3, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x78, 0x42, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 0:3, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x98, 0x01, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x98, 0x01, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x39, 0x40, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0x39, 0x40, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0xd9, 0x02, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0xd9, 0x02, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0x38, 0x61, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 0:3, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x38, 0x61, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 0:3, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x99, 0x21, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x99, 0x21, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x18, 0x00, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x18, 0x00, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x5d, 0x45, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x5d, 0x45, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x9f, 0x6d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]" + + - + input: + bytes: [ 0x9f, 0x6d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]" + + - + input: + bytes: [ 0xdf, 0x6f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]" + + - + input: + bytes: [ 0xdf, 0x6f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]" + + - + input: + bytes: [ 0x1d, 0x0e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]" + + - + input: + bytes: [ 0x1d, 0x0e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]" + + - + input: + bytes: [ 0x19, 0x04, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]" + + - + input: + bytes: [ 0x19, 0x04, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]" + + - + input: + bytes: [ 0x58, 0x46, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x58, 0x46, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x98, 0x09, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]" + + - + input: + bytes: [ 0x98, 0x09, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]" + + - + input: + bytes: [ 0x19, 0x48, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]" + + - + input: + bytes: [ 0x19, 0x48, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]" + + - + input: + bytes: [ 0xdd, 0x0a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]" + + - + input: + bytes: [ 0xdd, 0x0a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]" + + - + input: + bytes: [ 0x1a, 0x65, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]" + + - + input: + bytes: [ 0x1a, 0x65, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]" + + - + input: + bytes: [ 0x9f, 0x29, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]" + + - + input: + bytes: [ 0x9f, 0x29, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]" + + - + input: + bytes: [ 0x18, 0x00, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x18, 0x00, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x59, 0x41, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x59, 0x41, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x99, 0x61, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0x99, 0x61, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0xd9, 0x63, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xd9, 0x63, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x19, 0x02, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }" + + - + input: + bytes: [ 0x19, 0x02, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }" + + - + input: + bytes: [ 0x19, 0x00, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x19, 0x00, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x58, 0x42, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x58, 0x42, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x98, 0x01, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }" + + - + input: + bytes: [ 0x98, 0x01, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }" + + - + input: + bytes: [ 0x19, 0x40, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }" + + - + input: + bytes: [ 0x19, 0x40, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }" + + - + input: + bytes: [ 0xd9, 0x02, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xd9, 0x02, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x18, 0x61, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x18, 0x61, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x99, 0x21, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }" + + - + input: + bytes: [ 0x99, 0x21, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }" + + - + input: + bytes: [ 0x18, 0x00, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x18, 0x00, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x59, 0x41, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x59, 0x41, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xb9, 0x61, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xb9, 0x61, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xf9, 0x63, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xf9, 0x63, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x39, 0x02, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x39, 0x02, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x39, 0x00, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x39, 0x00, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x78, 0x42, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 0:3, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x78, 0x42, 0x64, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 0:3, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x98, 0x01, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x98, 0x01, 0x62, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x39, 0x40, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x39, 0x40, 0x6a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xd9, 0x02, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xd9, 0x02, 0x6e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x38, 0x61, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 0:3, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x38, 0x61, 0x61, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 0:3, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x99, 0x21, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x99, 0x21, 0x6b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x18, 0x00, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x18, 0x00, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x5d, 0x45, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h[6]" + + - + input: + bytes: [ 0x5d, 0x45, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h[6]" + + - + input: + bytes: [ 0x9f, 0x65, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0x9f, 0x65, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx2], { z12.h, z13.h }, z8.h[7]" + + - + input: + bytes: [ 0xdf, 0x67, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0xdf, 0x67, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x1d, 0x06, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx2], { z16.h, z17.h }, z0.h[6]" + + - + input: + bytes: [ 0x1d, 0x06, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx2], { z16.h, z17.h }, z0.h[6]" + + - + input: + bytes: [ 0x19, 0x04, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx2], { z0.h, z1.h }, z14.h[4]" + + - + input: + bytes: [ 0x19, 0x04, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx2], { z0.h, z1.h }, z14.h[4]" + + - + input: + bytes: [ 0x58, 0x46, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 0:3, vgx2], { z18.h, z19.h }, z4.h[4]" + + - + input: + bytes: [ 0x58, 0x46, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 0:3, vgx2], { z18.h, z19.h }, z4.h[4]" + + - + input: + bytes: [ 0x98, 0x01, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h[0]" + + - + input: + bytes: [ 0x98, 0x01, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h[0]" + + - + input: + bytes: [ 0x19, 0x40, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx2], { z0.h, z1.h }, z10.h[0]" + + - + input: + bytes: [ 0x19, 0x40, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx2], { z0.h, z1.h }, z10.h[0]" + + - + input: + bytes: [ 0xdd, 0x02, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0xdd, 0x02, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x1a, 0x65, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 0:3, vgx2], { z8.h, z9.h }, z1.h[5]" + + - + input: + bytes: [ 0x1a, 0x65, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 0:3, vgx2], { z8.h, z9.h }, z1.h[5]" + + - + input: + bytes: [ 0x9f, 0x21, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h[3]" + + - + input: + bytes: [ 0x9f, 0x21, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h[3]" + + - + input: + bytes: [ 0x18, 0x00, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x18, 0x00, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x59, 0x41, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x59, 0x41, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x99, 0x61, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x99, 0x61, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xd9, 0x63, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xd9, 0x63, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x19, 0x02, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x19, 0x02, 0xf0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x19, 0x00, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x19, 0x00, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x58, 0x42, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 0:3, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x58, 0x42, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 0:3, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x98, 0x01, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x98, 0x01, 0xe2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x19, 0x40, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x19, 0x40, 0xfa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xd9, 0x02, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xd9, 0x02, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x18, 0x61, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 0:3, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x18, 0x61, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 0:3, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x99, 0x21, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x99, 0x21, 0xea, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x18, 0x00, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x18, 0x00, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x59, 0x41, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0x59, 0x41, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0xb9, 0x61, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xb9, 0x61, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xf9, 0x63, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0xf9, 0x63, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0x39, 0x02, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x39, 0x02, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x39, 0x00, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x39, 0x00, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x78, 0x42, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 0:3, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x78, 0x42, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 0:3, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x98, 0x01, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x98, 0x01, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x39, 0x40, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0x39, 0x40, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0xd9, 0x02, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0xd9, 0x02, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0x38, 0x61, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 0:3, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x38, 0x61, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 0:3, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x99, 0x21, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x99, 0x21, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x18, 0x80, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x18, 0x80, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x1d, 0xc5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x1d, 0xc5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x9f, 0xed, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]" + + - + input: + bytes: [ 0x9f, 0xed, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]" + + - + input: + bytes: [ 0x9f, 0xef, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]" + + - + input: + bytes: [ 0x9f, 0xef, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]" + + - + input: + bytes: [ 0x1d, 0x8e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]" + + - + input: + bytes: [ 0x1d, 0x8e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]" + + - + input: + bytes: [ 0x19, 0x84, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]" + + - + input: + bytes: [ 0x19, 0x84, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]" + + - + input: + bytes: [ 0x18, 0xc6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x18, 0xc6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x98, 0x89, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]" + + - + input: + bytes: [ 0x98, 0x89, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]" + + - + input: + bytes: [ 0x19, 0xc8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]" + + - + input: + bytes: [ 0x19, 0xc8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]" + + - + input: + bytes: [ 0x9d, 0x8a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]" + + - + input: + bytes: [ 0x9d, 0x8a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]" + + - + input: + bytes: [ 0x1a, 0xe5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]" + + - + input: + bytes: [ 0x1a, 0xe5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]" + + - + input: + bytes: [ 0x9f, 0xa9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]" + + - + input: + bytes: [ 0x9f, 0xa9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]" + + - + input: + bytes: [ 0x18, 0x00, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x18, 0x00, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x19, 0x41, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x19, 0x41, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x99, 0x61, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x99, 0x61, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x99, 0x63, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x99, 0x63, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x19, 0x02, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }" + + - + input: + bytes: [ 0x19, 0x02, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }" + + - + input: + bytes: [ 0x19, 0x00, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x19, 0x00, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x18, 0x42, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x18, 0x42, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x98, 0x01, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x98, 0x01, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x19, 0x40, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }" + + - + input: + bytes: [ 0x19, 0x40, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }" + + - + input: + bytes: [ 0x99, 0x02, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x99, 0x02, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x18, 0x61, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x18, 0x61, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x99, 0x21, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x99, 0x21, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x18, 0x00, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x18, 0x00, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x59, 0x41, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x59, 0x41, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xb9, 0x61, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xb9, 0x61, 0x78, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xf9, 0x63, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xf9, 0x63, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x39, 0x02, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x39, 0x02, 0x70, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x39, 0x00, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x39, 0x00, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x78, 0x42, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 0:3, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x78, 0x42, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 0:3, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x98, 0x01, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x98, 0x01, 0x72, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x39, 0x40, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x39, 0x40, 0x7a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xd9, 0x02, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xd9, 0x02, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x38, 0x61, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 0:3, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x38, 0x61, 0x71, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 0:3, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x99, 0x21, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x99, 0x21, 0x7b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x18, 0x80, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x18, 0x80, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x1d, 0xc5, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx4], { z8.h - z11.h }, z5.h[6]" + + - + input: + bytes: [ 0x1d, 0xc5, 0x95, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx4], { z8.h - z11.h }, z5.h[6]" + + - + input: + bytes: [ 0x9f, 0xe5, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x9f, 0xe5, 0x98, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx4], { z12.h - z15.h }, z8.h[7]" + + - + input: + bytes: [ 0x9f, 0xe7, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x9f, 0xe7, 0x9f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x1d, 0x86, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx4], { z16.h - z19.h }, z0.h[6]" + + - + input: + bytes: [ 0x1d, 0x86, 0x90, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx4], { z16.h - z19.h }, z0.h[6]" + + - + input: + bytes: [ 0x19, 0x84, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx4], { z0.h - z3.h }, z14.h[4]" + + - + input: + bytes: [ 0x19, 0x84, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx4], { z0.h - z3.h }, z14.h[4]" + + - + input: + bytes: [ 0x18, 0xc6, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 0:3, vgx4], { z16.h - z19.h }, z4.h[4]" + + - + input: + bytes: [ 0x18, 0xc6, 0x94, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 0:3, vgx4], { z16.h - z19.h }, z4.h[4]" + + - + input: + bytes: [ 0x98, 0x81, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h[0]" + + - + input: + bytes: [ 0x98, 0x81, 0x92, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h[0]" + + - + input: + bytes: [ 0x19, 0xc0, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx4], { z0.h - z3.h }, z10.h[0]" + + - + input: + bytes: [ 0x19, 0xc0, 0x9a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx4], { z0.h - z3.h }, z10.h[0]" + + - + input: + bytes: [ 0x9d, 0x82, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx4], { z20.h - z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x9d, 0x82, 0x9e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx4], { z20.h - z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x1a, 0xe5, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 0:3, vgx4], { z8.h - z11.h }, z1.h[5]" + + - + input: + bytes: [ 0x1a, 0xe5, 0x91, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 0:3, vgx4], { z8.h - z11.h }, z1.h[5]" + + - + input: + bytes: [ 0x9f, 0xa1, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h[3]" + + - + input: + bytes: [ 0x9f, 0xa1, 0x9b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h[3]" + + - + input: + bytes: [ 0x18, 0x00, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x18, 0x00, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x19, 0x41, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x19, 0x41, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x99, 0x61, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x99, 0x61, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x99, 0x63, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x99, 0x63, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 4:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x19, 0x02, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x19, 0x02, 0xf1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x19, 0x00, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x19, 0x00, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x18, 0x42, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 0:3, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x18, 0x42, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 0:3, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x98, 0x01, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x98, 0x01, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x19, 0x40, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x19, 0x40, 0xf9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w10, 4:7, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x99, 0x02, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x99, 0x02, 0xfd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w8, 4:7, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x18, 0x61, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 0:3, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x18, 0x61, 0xe1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w11, 0:3, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x99, 0x21, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x99, 0x21, 0xe9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "umlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2/umopa.s.yaml b/tests/MC/AArch64/SME2/umopa.s.yaml new file mode 100644 index 0000000000..6a8ebc0f67 --- /dev/null +++ b/tests/MC/AArch64/SME2/umopa.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x00, 0x80, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umopa za0.s, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x49, 0x55, 0x95, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umopa za1.s, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xab, 0xed, 0x88, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umopa za3.s, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xeb, 0xff, 0x9f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umopa za3.s, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x29, 0x0e, 0x90, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umopa za1.s, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x29, 0x84, 0x9e, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umopa za1.s, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x68, 0x56, 0x94, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umopa za0.s, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x88, 0x19, 0x82, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umopa za0.s, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x29, 0xc8, 0x9a, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umopa za1.s, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xc9, 0x0a, 0x9e, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umopa za1.s, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x2a, 0xf5, 0x81, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umopa za2.s, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x8b, 0xa9, 0x8b, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umopa za3.s, p2/m, p5/m, z12.h, z11.h" diff --git a/tests/MC/AArch64/SME2/umops.s.yaml b/tests/MC/AArch64/SME2/umops.s.yaml new file mode 100644 index 0000000000..52dad4e1e9 --- /dev/null +++ b/tests/MC/AArch64/SME2/umops.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x00, 0x80, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umops za0.s, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x59, 0x55, 0x95, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umops za1.s, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xbb, 0xed, 0x88, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umops za3.s, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xfb, 0xff, 0x9f, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umops za3.s, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x39, 0x0e, 0x90, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umops za1.s, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x39, 0x84, 0x9e, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umops za1.s, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x78, 0x56, 0x94, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umops za0.s, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x98, 0x19, 0x82, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umops za0.s, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x39, 0xc8, 0x9a, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umops za1.s, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xd9, 0x0a, 0x9e, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umops za1.s, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x3a, 0xf5, 0x81, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umops za2.s, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x9b, 0xa9, 0x8b, 0xa1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "umops za3.s, p2/m, p5/m, z12.h, z11.h" diff --git a/tests/MC/AArch64/SME2/uqcvt.s.yaml b/tests/MC/AArch64/SME2/uqcvt.s.yaml new file mode 100644 index 0000000000..ba22e4a7f6 --- /dev/null +++ b/tests/MC/AArch64/SME2/uqcvt.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xe0, 0x23, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvt z0.h, { z0.s, z1.s }" + + - + input: + bytes: [ 0x75, 0xe1, 0x23, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvt z21.h, { z10.s, z11.s }" + + - + input: + bytes: [ 0xb7, 0xe1, 0x23, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvt z23.h, { z12.s, z13.s }" + + - + input: + bytes: [ 0xff, 0xe3, 0x23, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvt z31.h, { z30.s, z31.s }" + + - + input: + bytes: [ 0x20, 0xe0, 0x33, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvt z0.b, { z0.s - z3.s }" + + - + input: + bytes: [ 0x35, 0xe1, 0x33, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvt z21.b, { z8.s - z11.s }" + + - + input: + bytes: [ 0xb7, 0xe1, 0x33, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvt z23.b, { z12.s - z15.s }" + + - + input: + bytes: [ 0xbf, 0xe3, 0x33, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvt z31.b, { z28.s - z31.s }" + + - + input: + bytes: [ 0x20, 0xe0, 0xb3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvt z0.h, { z0.d - z3.d }" + + - + input: + bytes: [ 0x35, 0xe1, 0xb3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvt z21.h, { z8.d - z11.d }" + + - + input: + bytes: [ 0xb7, 0xe1, 0xb3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvt z23.h, { z12.d - z15.d }" + + - + input: + bytes: [ 0xbf, 0xe3, 0xb3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvt z31.h, { z28.d - z31.d }" diff --git a/tests/MC/AArch64/SME2/uqcvtn.s.yaml b/tests/MC/AArch64/SME2/uqcvtn.s.yaml new file mode 100644 index 0000000000..528d74e1bf --- /dev/null +++ b/tests/MC/AArch64/SME2/uqcvtn.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x60, 0xe0, 0x33, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvtn z0.b, { z0.s - z3.s }" + + - + input: + bytes: [ 0x75, 0xe1, 0x33, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvtn z21.b, { z8.s - z11.s }" + + - + input: + bytes: [ 0xf7, 0xe1, 0x33, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvtn z23.b, { z12.s - z15.s }" + + - + input: + bytes: [ 0xff, 0xe3, 0x33, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvtn z31.b, { z28.s - z31.s }" + + - + input: + bytes: [ 0x60, 0xe0, 0xb3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvtn z0.h, { z0.d - z3.d }" + + - + input: + bytes: [ 0x75, 0xe1, 0xb3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvtn z21.h, { z8.d - z11.d }" + + - + input: + bytes: [ 0xf7, 0xe1, 0xb3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvtn z23.h, { z12.d - z15.d }" + + - + input: + bytes: [ 0xff, 0xe3, 0xb3, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvtn z31.h, { z28.d - z31.d }" diff --git a/tests/MC/AArch64/SME2/uqrshr.s.yaml b/tests/MC/AArch64/SME2/uqrshr.s.yaml new file mode 100644 index 0000000000..3a85d8fcbd --- /dev/null +++ b/tests/MC/AArch64/SME2/uqrshr.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xd4, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshr z0.h, { z0.s, z1.s }, #16" + + - + input: + bytes: [ 0x75, 0xd5, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshr z21.h, { z10.s, z11.s }, #11" + + - + input: + bytes: [ 0xb7, 0xd5, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshr z23.h, { z12.s, z13.s }, #8" + + - + input: + bytes: [ 0xff, 0xd7, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshr z31.h, { z30.s, z31.s }, #1" + + - + input: + bytes: [ 0x20, 0xd8, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshr z0.b, { z0.s - z3.s }, #32" + + - + input: + bytes: [ 0x35, 0xd9, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshr z21.b, { z8.s - z11.s }, #11" + + - + input: + bytes: [ 0xb7, 0xd9, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshr z23.b, { z12.s - z15.s }, #24" + + - + input: + bytes: [ 0xbf, 0xdb, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshr z31.b, { z28.s - z31.s }, #1" + + - + input: + bytes: [ 0x20, 0xd8, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshr z0.h, { z0.d - z3.d }, #64" + + - + input: + bytes: [ 0x35, 0xd9, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshr z21.h, { z8.d - z11.d }, #11" + + - + input: + bytes: [ 0xb7, 0xd9, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshr z23.h, { z12.d - z15.d }, #24" + + - + input: + bytes: [ 0xbf, 0xdb, 0xff, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshr z31.h, { z28.d - z31.d }, #1" diff --git a/tests/MC/AArch64/SME2/uqrshrn.s.yaml b/tests/MC/AArch64/SME2/uqrshrn.s.yaml new file mode 100644 index 0000000000..67b5e5c291 --- /dev/null +++ b/tests/MC/AArch64/SME2/uqrshrn.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xdc, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshrn z0.b, { z0.s - z3.s }, #32" + + - + input: + bytes: [ 0x35, 0xdd, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshrn z21.b, { z8.s - z11.s }, #11" + + - + input: + bytes: [ 0xb7, 0xdd, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshrn z23.b, { z12.s - z15.s }, #24" + + - + input: + bytes: [ 0xbf, 0xdf, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshrn z31.b, { z28.s - z31.s }, #1" + + - + input: + bytes: [ 0x20, 0xdc, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshrn z0.h, { z0.d - z3.d }, #64" + + - + input: + bytes: [ 0x35, 0xdd, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshrn z21.h, { z8.d - z11.d }, #11" + + - + input: + bytes: [ 0xb7, 0xdd, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshrn z23.h, { z12.d - z15.d }, #24" + + - + input: + bytes: [ 0xbf, 0xdf, 0xff, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshrn z31.h, { z28.d - z31.d }, #1" diff --git a/tests/MC/AArch64/SME2/urshl.s.yaml b/tests/MC/AArch64/SME2/urshl.s.yaml new file mode 100644 index 0000000000..b5396e9832 --- /dev/null +++ b/tests/MC/AArch64/SME2/urshl.s.yaml @@ -0,0 +1,640 @@ +test_cases: + - + input: + bytes: [ 0x21, 0xa2, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z0.h, z1.h }, { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x35, 0xa2, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.h, z21.h }, { z20.h, z21.h }, z5.h" + + - + input: + bytes: [ 0x37, 0xa2, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z22.h, z23.h }, { z22.h, z23.h }, z8.h" + + - + input: + bytes: [ 0x3f, 0xa2, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z30.h, z31.h }, { z30.h, z31.h }, z15.h" + + - + input: + bytes: [ 0x21, 0xb2, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x35, 0xb2, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x37, 0xb2, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x3f, 0xb2, 0x7e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x21, 0xa2, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z0.s, z1.s }, { z0.s, z1.s }, z0.s" + + - + input: + bytes: [ 0x35, 0xa2, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.s, z21.s }, { z20.s, z21.s }, z5.s" + + - + input: + bytes: [ 0x37, 0xa2, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z22.s, z23.s }, { z22.s, z23.s }, z8.s" + + - + input: + bytes: [ 0x3f, 0xa2, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z30.s, z31.s }, { z30.s, z31.s }, z15.s" + + - + input: + bytes: [ 0x21, 0xb2, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x35, 0xb2, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }" + + - + input: + bytes: [ 0x37, 0xb2, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }" + + - + input: + bytes: [ 0x3f, 0xb2, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }" + + - + input: + bytes: [ 0x21, 0xa2, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z0.d, z1.d }, { z0.d, z1.d }, z0.d" + + - + input: + bytes: [ 0x35, 0xa2, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.d, z21.d }, { z20.d, z21.d }, z5.d" + + - + input: + bytes: [ 0x37, 0xa2, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z22.d, z23.d }, { z22.d, z23.d }, z8.d" + + - + input: + bytes: [ 0x3f, 0xa2, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z30.d, z31.d }, { z30.d, z31.d }, z15.d" + + - + input: + bytes: [ 0x21, 0xb2, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }" + + - + input: + bytes: [ 0x35, 0xb2, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }" + + - + input: + bytes: [ 0x37, 0xb2, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }" + + - + input: + bytes: [ 0x3f, 0xb2, 0xfe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }" + + - + input: + bytes: [ 0x21, 0xa2, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z0.b, z1.b }, { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x35, 0xa2, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.b, z21.b }, { z20.b, z21.b }, z5.b" + + - + input: + bytes: [ 0x37, 0xa2, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z22.b, z23.b }, { z22.b, z23.b }, z8.b" + + - + input: + bytes: [ 0x3f, 0xa2, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z30.b, z31.b }, { z30.b, z31.b }, z15.b" + + - + input: + bytes: [ 0x21, 0xb2, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x35, 0xb2, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x37, 0xb2, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0x3f, 0xb2, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x21, 0xaa, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z0.h - z3.h }, { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x35, 0xaa, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.h - z23.h }, { z20.h - z23.h }, z5.h" + + - + input: + bytes: [ 0x35, 0xaa, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.h - z23.h }, { z20.h - z23.h }, z8.h" + + - + input: + bytes: [ 0x3d, 0xaa, 0x6f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z28.h - z31.h }, { z28.h - z31.h }, z15.h" + + - + input: + bytes: [ 0x21, 0xba, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x35, 0xba, 0x74, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x35, 0xba, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x3d, 0xba, 0x7c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x21, 0xaa, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z0.s - z3.s }, { z0.s - z3.s }, z0.s" + + - + input: + bytes: [ 0x35, 0xaa, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.s - z23.s }, { z20.s - z23.s }, z5.s" + + - + input: + bytes: [ 0x35, 0xaa, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.s - z23.s }, { z20.s - z23.s }, z8.s" + + - + input: + bytes: [ 0x3d, 0xaa, 0xaf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z28.s - z31.s }, { z28.s - z31.s }, z15.s" + + - + input: + bytes: [ 0x21, 0xba, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x35, 0xba, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }" + + - + input: + bytes: [ 0x35, 0xba, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x3d, 0xba, 0xbc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x21, 0xaa, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z0.d - z3.d }, { z0.d - z3.d }, z0.d" + + - + input: + bytes: [ 0x35, 0xaa, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.d - z23.d }, { z20.d - z23.d }, z5.d" + + - + input: + bytes: [ 0x35, 0xaa, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.d - z23.d }, { z20.d - z23.d }, z8.d" + + - + input: + bytes: [ 0x3d, 0xaa, 0xef, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z28.d - z31.d }, { z28.d - z31.d }, z15.d" + + - + input: + bytes: [ 0x21, 0xba, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x35, 0xba, 0xf4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }" + + - + input: + bytes: [ 0x35, 0xba, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x3d, 0xba, 0xfc, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x21, 0xaa, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z0.b - z3.b }, { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x35, 0xaa, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.b - z23.b }, { z20.b - z23.b }, z5.b" + + - + input: + bytes: [ 0x35, 0xaa, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.b - z23.b }, { z20.b - z23.b }, z8.b" + + - + input: + bytes: [ 0x3d, 0xaa, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z28.b - z31.b }, { z28.b - z31.b }, z15.b" + + - + input: + bytes: [ 0x21, 0xba, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x35, 0xba, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x35, 0xba, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x3d, 0xba, 0x3c, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "urshl { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }" diff --git a/tests/MC/AArch64/SME2/usdot.s.yaml b/tests/MC/AArch64/SME2/usdot.s.yaml new file mode 100644 index 0000000000..67fd33e114 --- /dev/null +++ b/tests/MC/AArch64/SME2/usdot.s.yaml @@ -0,0 +1,1440 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x14, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x08, 0x14, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x4d, 0x55, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0x4d, 0x55, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0xaf, 0x75, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xaf, 0x75, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xef, 0x77, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0xef, 0x77, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0x2d, 0x16, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x2d, 0x16, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x29, 0x14, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 1, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x29, 0x14, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 1, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x68, 0x56, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 0, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x68, 0x56, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 0, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x88, 0x15, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x88, 0x15, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x29, 0x54, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 1, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0x29, 0x54, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 1, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0xcd, 0x16, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0xcd, 0x16, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0x2a, 0x75, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 2, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x2a, 0x75, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 2, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x8f, 0x35, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x8f, 0x35, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x28, 0x10, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x28, 0x10, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x6d, 0x55, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]" + + - + input: + bytes: [ 0x6d, 0x55, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]" + + - + input: + bytes: [ 0xaf, 0x7d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]" + + - + input: + bytes: [ 0xaf, 0x7d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]" + + - + input: + bytes: [ 0xef, 0x7f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]" + + - + input: + bytes: [ 0xef, 0x7f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]" + + - + input: + bytes: [ 0x2d, 0x1e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]" + + - + input: + bytes: [ 0x2d, 0x1e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]" + + - + input: + bytes: [ 0x29, 0x14, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]" + + - + input: + bytes: [ 0x29, 0x14, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]" + + - + input: + bytes: [ 0x68, 0x56, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]" + + - + input: + bytes: [ 0x68, 0x56, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]" + + - + input: + bytes: [ 0xa8, 0x19, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]" + + - + input: + bytes: [ 0xa8, 0x19, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]" + + - + input: + bytes: [ 0x29, 0x58, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]" + + - + input: + bytes: [ 0x29, 0x58, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]" + + - + input: + bytes: [ 0xed, 0x1a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]" + + - + input: + bytes: [ 0xed, 0x1a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]" + + - + input: + bytes: [ 0x2a, 0x75, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]" + + - + input: + bytes: [ 0x2a, 0x75, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]" + + - + input: + bytes: [ 0xaf, 0x39, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]" + + - + input: + bytes: [ 0xaf, 0x39, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]" + + - + input: + bytes: [ 0x08, 0x14, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x08, 0x14, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x4d, 0x55, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 5, vgx2], { z10.b, z11.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x4d, 0x55, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 5, vgx2], { z10.b, z11.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x8f, 0x75, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0x8f, 0x75, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0xcf, 0x77, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xcf, 0x77, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x0d, 0x16, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx2], { z16.b, z17.b }, { z16.b, z17.b }" + + - + input: + bytes: [ 0x0d, 0x16, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx2], { z16.b, z17.b }, { z16.b, z17.b }" + + - + input: + bytes: [ 0x09, 0x14, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 1, vgx2], { z0.b, z1.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x09, 0x14, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 1, vgx2], { z0.b, z1.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x48, 0x56, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 0, vgx2], { z18.b, z19.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x48, 0x56, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 0, vgx2], { z18.b, z19.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x88, 0x15, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx2], { z12.b, z13.b }, { z2.b, z3.b }" + + - + input: + bytes: [ 0x88, 0x15, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx2], { z12.b, z13.b }, { z2.b, z3.b }" + + - + input: + bytes: [ 0x09, 0x54, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 1, vgx2], { z0.b, z1.b }, { z26.b, z27.b }" + + - + input: + bytes: [ 0x09, 0x54, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 1, vgx2], { z0.b, z1.b }, { z26.b, z27.b }" + + - + input: + bytes: [ 0xcd, 0x16, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx2], { z22.b, z23.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xcd, 0x16, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx2], { z22.b, z23.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x0a, 0x75, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 2, vgx2], { z8.b, z9.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x0a, 0x75, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 2, vgx2], { z8.b, z9.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x8f, 0x35, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w9, 7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }" + + - + input: + bytes: [ 0x8f, 0x35, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w9, 7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }" + + - + input: + bytes: [ 0x08, 0x14, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x08, 0x14, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x4d, 0x55, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 5, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0x4d, 0x55, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 5, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0xaf, 0x75, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xaf, 0x75, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xef, 0x77, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0xef, 0x77, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0x2d, 0x16, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x2d, 0x16, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x29, 0x14, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 1, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x29, 0x14, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 1, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x68, 0x56, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 0, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x68, 0x56, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 0, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x88, 0x15, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x88, 0x15, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x29, 0x54, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 1, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0x29, 0x54, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 1, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0xcd, 0x16, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0xcd, 0x16, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0x2a, 0x75, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 2, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x2a, 0x75, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 2, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x8f, 0x35, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x8f, 0x35, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x28, 0x90, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x28, 0x90, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x2d, 0xd5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]" + + - + input: + bytes: [ 0x2d, 0xd5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]" + + - + input: + bytes: [ 0xaf, 0xfd, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]" + + - + input: + bytes: [ 0xaf, 0xfd, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]" + + - + input: + bytes: [ 0xaf, 0xff, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]" + + - + input: + bytes: [ 0xaf, 0xff, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]" + + - + input: + bytes: [ 0x2d, 0x9e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]" + + - + input: + bytes: [ 0x2d, 0x9e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]" + + - + input: + bytes: [ 0x29, 0x94, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]" + + - + input: + bytes: [ 0x29, 0x94, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]" + + - + input: + bytes: [ 0x28, 0xd6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]" + + - + input: + bytes: [ 0x28, 0xd6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]" + + - + input: + bytes: [ 0xa8, 0x99, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]" + + - + input: + bytes: [ 0xa8, 0x99, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]" + + - + input: + bytes: [ 0x29, 0xd8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]" + + - + input: + bytes: [ 0x29, 0xd8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]" + + - + input: + bytes: [ 0xad, 0x9a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]" + + - + input: + bytes: [ 0xad, 0x9a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]" + + - + input: + bytes: [ 0x2a, 0xf5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]" + + - + input: + bytes: [ 0x2a, 0xf5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]" + + - + input: + bytes: [ 0xaf, 0xb9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]" + + - + input: + bytes: [ 0xaf, 0xb9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]" + + - + input: + bytes: [ 0x08, 0x14, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x08, 0x14, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x0d, 0x55, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 5, vgx4], { z8.b - z11.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x0d, 0x55, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 5, vgx4], { z8.b - z11.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x8f, 0x75, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x8f, 0x75, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x8f, 0x77, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x8f, 0x77, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x0d, 0x16, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx4], { z16.b - z19.b }, { z16.b - z19.b }" + + - + input: + bytes: [ 0x0d, 0x16, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx4], { z16.b - z19.b }, { z16.b - z19.b }" + + - + input: + bytes: [ 0x09, 0x14, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 1, vgx4], { z0.b - z3.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x09, 0x14, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 1, vgx4], { z0.b - z3.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x08, 0x56, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 0, vgx4], { z16.b - z19.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x08, 0x56, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 0, vgx4], { z16.b - z19.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x88, 0x15, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx4], { z12.b - z15.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x88, 0x15, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 0, vgx4], { z12.b - z15.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x09, 0x54, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 1, vgx4], { z0.b - z3.b }, { z24.b - z27.b }" + + - + input: + bytes: [ 0x09, 0x54, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w10, 1, vgx4], { z0.b - z3.b }, { z24.b - z27.b }" + + - + input: + bytes: [ 0x8d, 0x16, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx4], { z20.b - z23.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x8d, 0x16, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w8, 5, vgx4], { z20.b - z23.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x0a, 0x75, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 2, vgx4], { z8.b - z11.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x0a, 0x75, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w11, 2, vgx4], { z8.b - z11.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x8f, 0x35, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w9, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x8f, 0x35, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usdot za.s[w9, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" diff --git a/tests/MC/AArch64/SME2/usmlall.s.yaml b/tests/MC/AArch64/SME2/usmlall.s.yaml new file mode 100644 index 0000000000..53a9109a0c --- /dev/null +++ b/tests/MC/AArch64/SME2/usmlall.s.yaml @@ -0,0 +1,1680 @@ +test_cases: + - + input: + bytes: [ 0x04, 0x04, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3], z0.b, z0.b" + + - + input: + bytes: [ 0x45, 0x45, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7], z10.b, z5.b" + + - + input: + bytes: [ 0xa7, 0x65, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 12:15], z13.b, z8.b" + + - + input: + bytes: [ 0xe7, 0x67, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 12:15], z31.b, z15.b" + + - + input: + bytes: [ 0x25, 0x06, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7], z17.b, z0.b" + + - + input: + bytes: [ 0x25, 0x04, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7], z1.b, z14.b" + + - + input: + bytes: [ 0x64, 0x46, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 0:3], z19.b, z4.b" + + - + input: + bytes: [ 0x84, 0x05, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3], z12.b, z2.b" + + - + input: + bytes: [ 0x25, 0x44, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7], z1.b, z10.b" + + - + input: + bytes: [ 0xc5, 0x06, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7], z22.b, z14.b" + + - + input: + bytes: [ 0x26, 0x65, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 8:11], z9.b, z1.b" + + - + input: + bytes: [ 0x87, 0x25, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w9, 12:15], z12.b, z11.b" + + - + input: + bytes: [ 0x04, 0x00, 0x00, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3], z0.b, z0.b[0]" + + - + input: + bytes: [ 0x45, 0x55, 0x05, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7], z10.b, z5.b[5]" + + - + input: + bytes: [ 0xa7, 0xed, 0x08, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 12:15], z13.b, z8.b[11]" + + - + input: + bytes: [ 0xe7, 0xff, 0x0f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 12:15], z31.b, z15.b[15]" + + - + input: + bytes: [ 0x25, 0x0e, 0x00, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7], z17.b, z0.b[3]" + + - + input: + bytes: [ 0x25, 0x84, 0x0e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7], z1.b, z14.b[9]" + + - + input: + bytes: [ 0x64, 0x56, 0x04, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 0:3], z19.b, z4.b[5]" + + - + input: + bytes: [ 0x84, 0x19, 0x02, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3], z12.b, z2.b[6]" + + - + input: + bytes: [ 0x25, 0xc8, 0x0a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7], z1.b, z10.b[10]" + + - + input: + bytes: [ 0xc5, 0x0a, 0x0e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7], z22.b, z14.b[2]" + + - + input: + bytes: [ 0x26, 0xf5, 0x01, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 8:11], z9.b, z1.b[13]" + + - + input: + bytes: [ 0x87, 0xa9, 0x0b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w9, 12:15], z12.b, z11.b[10]" + + - + input: + bytes: [ 0x04, 0x00, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x04, 0x00, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b" + + - + input: + bytes: [ 0x45, 0x41, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0x45, 0x41, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b" + + - + input: + bytes: [ 0xa5, 0x61, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xa5, 0x61, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx2], { z13.b, z14.b }, z8.b" + + - + input: + bytes: [ 0xe5, 0x63, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0xe5, 0x63, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx2], { z31.b, z0.b }, z15.b" + + - + input: + bytes: [ 0x25, 0x02, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x25, 0x02, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx2], { z17.b, z18.b }, z0.b" + + - + input: + bytes: [ 0x25, 0x00, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x25, 0x00, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx2], { z1.b, z2.b }, z14.b" + + - + input: + bytes: [ 0x64, 0x42, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 0:3, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x64, 0x42, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 0:3, vgx2], { z19.b, z20.b }, z4.b" + + - + input: + bytes: [ 0x84, 0x01, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x84, 0x01, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b" + + - + input: + bytes: [ 0x25, 0x40, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0x25, 0x40, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx2], { z1.b, z2.b }, z10.b" + + - + input: + bytes: [ 0xc5, 0x02, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0xc5, 0x02, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b" + + - + input: + bytes: [ 0x24, 0x61, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 0:3, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x24, 0x61, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 0:3, vgx2], { z9.b, z10.b }, z1.b" + + - + input: + bytes: [ 0x85, 0x21, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x85, 0x21, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b" + + - + input: + bytes: [ 0x20, 0x00, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x20, 0x00, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]" + + - + input: + bytes: [ 0x65, 0x45, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x65, 0x45, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]" + + - + input: + bytes: [ 0xa7, 0x6d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]" + + - + input: + bytes: [ 0xa7, 0x6d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]" + + - + input: + bytes: [ 0xe7, 0x6f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]" + + - + input: + bytes: [ 0xe7, 0x6f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]" + + - + input: + bytes: [ 0x25, 0x0e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]" + + - + input: + bytes: [ 0x25, 0x0e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]" + + - + input: + bytes: [ 0x21, 0x04, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]" + + - + input: + bytes: [ 0x21, 0x04, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]" + + - + input: + bytes: [ 0x60, 0x46, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x60, 0x46, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]" + + - + input: + bytes: [ 0xa0, 0x09, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]" + + - + input: + bytes: [ 0xa0, 0x09, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]" + + - + input: + bytes: [ 0x21, 0x48, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]" + + - + input: + bytes: [ 0x21, 0x48, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]" + + - + input: + bytes: [ 0xe5, 0x0a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]" + + - + input: + bytes: [ 0xe5, 0x0a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]" + + - + input: + bytes: [ 0x22, 0x65, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]" + + - + input: + bytes: [ 0x22, 0x65, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]" + + - + input: + bytes: [ 0xa7, 0x29, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]" + + - + input: + bytes: [ 0xa7, 0x29, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]" + + - + input: + bytes: [ 0x04, 0x00, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x04, 0x00, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x45, 0x41, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x45, 0x41, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x85, 0x61, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0x85, 0x61, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }" + + - + input: + bytes: [ 0xc5, 0x63, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xc5, 0x63, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x05, 0x02, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }" + + - + input: + bytes: [ 0x05, 0x02, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }" + + - + input: + bytes: [ 0x05, 0x00, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x05, 0x00, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x44, 0x42, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x44, 0x42, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }" + + - + input: + bytes: [ 0x84, 0x01, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }" + + - + input: + bytes: [ 0x84, 0x01, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }" + + - + input: + bytes: [ 0x05, 0x40, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }" + + - + input: + bytes: [ 0x05, 0x40, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }" + + - + input: + bytes: [ 0xc5, 0x02, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0xc5, 0x02, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x04, 0x61, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x04, 0x61, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x85, 0x21, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }" + + - + input: + bytes: [ 0x85, 0x21, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }" + + - + input: + bytes: [ 0x04, 0x00, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x04, 0x00, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b" + + - + input: + bytes: [ 0x45, 0x41, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0x45, 0x41, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx4], { z10.b - z13.b }, z5.b" + + - + input: + bytes: [ 0xa5, 0x61, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xa5, 0x61, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx4], { z13.b - z16.b }, z8.b" + + - + input: + bytes: [ 0xe5, 0x63, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0xe5, 0x63, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b" + + - + input: + bytes: [ 0x25, 0x02, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x25, 0x02, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx4], { z17.b - z20.b }, z0.b" + + - + input: + bytes: [ 0x25, 0x00, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x25, 0x00, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx4], { z1.b - z4.b }, z14.b" + + - + input: + bytes: [ 0x64, 0x42, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 0:3, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x64, 0x42, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 0:3, vgx4], { z19.b - z22.b }, z4.b" + + - + input: + bytes: [ 0x84, 0x01, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x84, 0x01, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b" + + - + input: + bytes: [ 0x25, 0x40, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0x25, 0x40, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx4], { z1.b - z4.b }, z10.b" + + - + input: + bytes: [ 0xc5, 0x02, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0xc5, 0x02, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx4], { z22.b - z25.b }, z14.b" + + - + input: + bytes: [ 0x24, 0x61, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 0:3, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x24, 0x61, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 0:3, vgx4], { z9.b - z12.b }, z1.b" + + - + input: + bytes: [ 0x85, 0x21, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x85, 0x21, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b" + + - + input: + bytes: [ 0x20, 0x80, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x20, 0x80, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x25, 0xc5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]" + + - + input: + bytes: [ 0x25, 0xc5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]" + + - + input: + bytes: [ 0xa7, 0xed, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]" + + - + input: + bytes: [ 0xa7, 0xed, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]" + + - + input: + bytes: [ 0xa7, 0xef, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]" + + - + input: + bytes: [ 0xa7, 0xef, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]" + + - + input: + bytes: [ 0x25, 0x8e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]" + + - + input: + bytes: [ 0x25, 0x8e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]" + + - + input: + bytes: [ 0x21, 0x84, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]" + + - + input: + bytes: [ 0x21, 0x84, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]" + + - + input: + bytes: [ 0x20, 0xc6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]" + + - + input: + bytes: [ 0x20, 0xc6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]" + + - + input: + bytes: [ 0xa0, 0x89, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]" + + - + input: + bytes: [ 0xa0, 0x89, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]" + + - + input: + bytes: [ 0x21, 0xc8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]" + + - + input: + bytes: [ 0x21, 0xc8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]" + + - + input: + bytes: [ 0xa5, 0x8a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]" + + - + input: + bytes: [ 0xa5, 0x8a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]" + + - + input: + bytes: [ 0x22, 0xe5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]" + + - + input: + bytes: [ 0x22, 0xe5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]" + + - + input: + bytes: [ 0xa7, 0xa9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]" + + - + input: + bytes: [ 0xa7, 0xa9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]" + + - + input: + bytes: [ 0x04, 0x00, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x04, 0x00, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x05, 0x41, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x05, 0x41, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x85, 0x61, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x85, 0x61, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x85, 0x63, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x85, 0x63, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x05, 0x02, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }" + + - + input: + bytes: [ 0x05, 0x02, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }" + + - + input: + bytes: [ 0x05, 0x00, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x05, 0x00, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x04, 0x42, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x04, 0x42, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }" + + - + input: + bytes: [ 0x84, 0x01, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x84, 0x01, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x05, 0x40, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }" + + - + input: + bytes: [ 0x05, 0x40, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }" + + - + input: + bytes: [ 0x85, 0x02, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x85, 0x02, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }" + + - + input: + bytes: [ 0x04, 0x61, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x04, 0x61, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x85, 0x21, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x85, 0x21, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usmlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }" diff --git a/tests/MC/AArch64/SME2/usvdot.s.yaml b/tests/MC/AArch64/SME2/usvdot.s.yaml new file mode 100644 index 0000000000..63d318fc18 --- /dev/null +++ b/tests/MC/AArch64/SME2/usvdot.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x28, 0x80, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x28, 0x80, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x2d, 0xc5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]" + + - + input: + bytes: [ 0x2d, 0xc5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]" + + - + input: + bytes: [ 0xaf, 0xed, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]" + + - + input: + bytes: [ 0xaf, 0xed, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]" + + - + input: + bytes: [ 0xaf, 0xef, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]" + + - + input: + bytes: [ 0xaf, 0xef, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]" + + - + input: + bytes: [ 0x2d, 0x8e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]" + + - + input: + bytes: [ 0x2d, 0x8e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]" + + - + input: + bytes: [ 0x29, 0x84, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]" + + - + input: + bytes: [ 0x29, 0x84, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]" + + - + input: + bytes: [ 0x28, 0xc6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]" + + - + input: + bytes: [ 0x28, 0xc6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]" + + - + input: + bytes: [ 0xa8, 0x89, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]" + + - + input: + bytes: [ 0xa8, 0x89, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]" + + - + input: + bytes: [ 0x29, 0xc8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]" + + - + input: + bytes: [ 0x29, 0xc8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]" + + - + input: + bytes: [ 0xad, 0x8a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]" + + - + input: + bytes: [ 0xad, 0x8a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]" + + - + input: + bytes: [ 0x2a, 0xe5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]" + + - + input: + bytes: [ 0x2a, 0xe5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]" + + - + input: + bytes: [ 0xaf, 0xa9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]" + + - + input: + bytes: [ 0xaf, 0xa9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "usvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]" diff --git a/tests/MC/AArch64/SME2/uunpk.s.yaml b/tests/MC/AArch64/SME2/uunpk.s.yaml new file mode 100644 index 0000000000..fed048e1fa --- /dev/null +++ b/tests/MC/AArch64/SME2/uunpk.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x01, 0xe0, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z0.h, z1.h }, z0.b" + + - + input: + bytes: [ 0x55, 0xe1, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z20.h, z21.h }, z10.b" + + - + input: + bytes: [ 0xb7, 0xe1, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z22.h, z23.h }, z13.b" + + - + input: + bytes: [ 0xff, 0xe3, 0x65, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z30.h, z31.h }, z31.b" + + - + input: + bytes: [ 0x01, 0xe0, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z0.s, z1.s }, z0.h" + + - + input: + bytes: [ 0x55, 0xe1, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z20.s, z21.s }, z10.h" + + - + input: + bytes: [ 0xb7, 0xe1, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z22.s, z23.s }, z13.h" + + - + input: + bytes: [ 0xff, 0xe3, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z30.s, z31.s }, z31.h" + + - + input: + bytes: [ 0x01, 0xe0, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z0.d, z1.d }, z0.s" + + - + input: + bytes: [ 0x55, 0xe1, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z20.d, z21.d }, z10.s" + + - + input: + bytes: [ 0xb7, 0xe1, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z22.d, z23.d }, z13.s" + + - + input: + bytes: [ 0xff, 0xe3, 0xe5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z30.d, z31.d }, z31.s" + + - + input: + bytes: [ 0x01, 0xe0, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z0.h - z3.h }, { z0.b, z1.b }" + + - + input: + bytes: [ 0x55, 0xe1, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z20.h - z23.h }, { z10.b, z11.b }" + + - + input: + bytes: [ 0x95, 0xe1, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z20.h - z23.h }, { z12.b, z13.b }" + + - + input: + bytes: [ 0xdd, 0xe3, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z28.h - z31.h }, { z30.b, z31.b }" + + - + input: + bytes: [ 0x01, 0xe0, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z0.s - z3.s }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x55, 0xe1, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z20.s - z23.s }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x95, 0xe1, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z20.s - z23.s }, { z12.h, z13.h }" + + - + input: + bytes: [ 0xdd, 0xe3, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z28.s - z31.s }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x01, 0xe0, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z0.d - z3.d }, { z0.s, z1.s }" + + - + input: + bytes: [ 0x55, 0xe1, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z20.d - z23.d }, { z10.s, z11.s }" + + - + input: + bytes: [ 0x95, 0xe1, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z20.d - z23.d }, { z12.s, z13.s }" + + - + input: + bytes: [ 0xdd, 0xe3, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uunpk { z28.d - z31.d }, { z30.s, z31.s }" diff --git a/tests/MC/AArch64/SME2/uvdot.s.yaml b/tests/MC/AArch64/SME2/uvdot.s.yaml new file mode 100644 index 0000000000..23ad138069 --- /dev/null +++ b/tests/MC/AArch64/SME2/uvdot.s.yaml @@ -0,0 +1,720 @@ +test_cases: + - + input: + bytes: [ 0x30, 0x00, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x30, 0x00, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x75, 0x45, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x75, 0x45, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]" + + - + input: + bytes: [ 0xf7, 0x6f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]" + + - + input: + bytes: [ 0xf7, 0x6f, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]" + + - + input: + bytes: [ 0x35, 0x0e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]" + + - + input: + bytes: [ 0x35, 0x0e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]" + + - + input: + bytes: [ 0x31, 0x04, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x31, 0x04, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]" + + - + input: + bytes: [ 0x70, 0x46, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x70, 0x46, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]" + + - + input: + bytes: [ 0xb0, 0x09, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]" + + - + input: + bytes: [ 0xb0, 0x09, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]" + + - + input: + bytes: [ 0x31, 0x48, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]" + + - + input: + bytes: [ 0x31, 0x48, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]" + + - + input: + bytes: [ 0xf5, 0x0a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0xf5, 0x0a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]" + + - + input: + bytes: [ 0x32, 0x65, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0x32, 0x65, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]" + + - + input: + bytes: [ 0xb7, 0x29, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]" + + - + input: + bytes: [ 0xb7, 0x29, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]" + + - + input: + bytes: [ 0x30, 0x80, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x30, 0x80, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]" + + - + input: + bytes: [ 0x35, 0xc5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]" + + - + input: + bytes: [ 0x35, 0xc5, 0x55, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]" + + - + input: + bytes: [ 0xb7, 0xed, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]" + + - + input: + bytes: [ 0xb7, 0xed, 0x58, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]" + + - + input: + bytes: [ 0xb7, 0xef, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]" + + - + input: + bytes: [ 0xb7, 0xef, 0x5f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]" + + - + input: + bytes: [ 0x35, 0x8e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]" + + - + input: + bytes: [ 0x35, 0x8e, 0x50, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]" + + - + input: + bytes: [ 0x31, 0x84, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]" + + - + input: + bytes: [ 0x31, 0x84, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]" + + - + input: + bytes: [ 0x30, 0xc6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]" + + - + input: + bytes: [ 0x30, 0xc6, 0x54, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]" + + - + input: + bytes: [ 0xb0, 0x89, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]" + + - + input: + bytes: [ 0xb0, 0x89, 0x52, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]" + + - + input: + bytes: [ 0x31, 0xc8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]" + + - + input: + bytes: [ 0x31, 0xc8, 0x5a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]" + + - + input: + bytes: [ 0xb5, 0x8a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]" + + - + input: + bytes: [ 0xb5, 0x8a, 0x5e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]" + + - + input: + bytes: [ 0x32, 0xe5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]" + + - + input: + bytes: [ 0x32, 0xe5, 0x51, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]" + + - + input: + bytes: [ 0xb7, 0xa9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]" + + - + input: + bytes: [ 0xb7, 0xa9, 0x5b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]" + + - + input: + bytes: [ 0x18, 0x88, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x18, 0x88, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x1d, 0xcd, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x1d, 0xcd, 0xd5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]" + + - + input: + bytes: [ 0x9f, 0xed, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]" + + - + input: + bytes: [ 0x9f, 0xed, 0xd8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]" + + - + input: + bytes: [ 0x9f, 0xef, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]" + + - + input: + bytes: [ 0x9f, 0xef, 0xdf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]" + + - + input: + bytes: [ 0x1d, 0x8e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]" + + - + input: + bytes: [ 0x1d, 0x8e, 0xd0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]" + + - + input: + bytes: [ 0x19, 0x8c, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]" + + - + input: + bytes: [ 0x19, 0x8c, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]" + + - + input: + bytes: [ 0x18, 0xce, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x18, 0xce, 0xd4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]" + + - + input: + bytes: [ 0x98, 0x89, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]" + + - + input: + bytes: [ 0x98, 0x89, 0xd2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]" + + - + input: + bytes: [ 0x19, 0xc8, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]" + + - + input: + bytes: [ 0x19, 0xc8, 0xda, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]" + + - + input: + bytes: [ 0x9d, 0x8a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]" + + - + input: + bytes: [ 0x9d, 0x8a, 0xde, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]" + + - + input: + bytes: [ 0x1a, 0xed, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]" + + - + input: + bytes: [ 0x1a, 0xed, 0xd1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]" + + - + input: + bytes: [ 0x9f, 0xa9, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]" + + - + input: + bytes: [ 0x9f, 0xa9, 0xdb, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ] + expected: + insns: + - + asm_text: "uvdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]" diff --git a/tests/MC/AArch64/SME2/uzp.s.yaml b/tests/MC/AArch64/SME2/uzp.s.yaml new file mode 100644 index 0000000000..7195e82c97 --- /dev/null +++ b/tests/MC/AArch64/SME2/uzp.s.yaml @@ -0,0 +1,400 @@ +test_cases: + - + input: + bytes: [ 0x01, 0xd4, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z0.q, z1.q }, z0.q, z0.q" + + - + input: + bytes: [ 0x55, 0xd5, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z20.q, z21.q }, z10.q, z21.q" + + - + input: + bytes: [ 0xb7, 0xd5, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z22.q, z23.q }, z13.q, z8.q" + + - + input: + bytes: [ 0xff, 0xd7, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z30.q, z31.q }, z31.q, z31.q" + + - + input: + bytes: [ 0x01, 0xd0, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z0.h, z1.h }, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xd1, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z20.h, z21.h }, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xd1, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z22.h, z23.h }, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xd3, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z30.h, z31.h }, z31.h, z31.h" + + - + input: + bytes: [ 0x01, 0xd0, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z0.s, z1.s }, z0.s, z0.s" + + - + input: + bytes: [ 0x55, 0xd1, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z20.s, z21.s }, z10.s, z21.s" + + - + input: + bytes: [ 0xb7, 0xd1, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z22.s, z23.s }, z13.s, z8.s" + + - + input: + bytes: [ 0xff, 0xd3, 0xbf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z30.s, z31.s }, z31.s, z31.s" + + - + input: + bytes: [ 0x01, 0xd0, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z0.d, z1.d }, z0.d, z0.d" + + - + input: + bytes: [ 0x55, 0xd1, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z20.d, z21.d }, z10.d, z21.d" + + - + input: + bytes: [ 0xb7, 0xd1, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z22.d, z23.d }, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0xd3, 0xff, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z30.d, z31.d }, z31.d, z31.d" + + - + input: + bytes: [ 0x01, 0xd0, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z0.b, z1.b }, z0.b, z0.b" + + - + input: + bytes: [ 0x55, 0xd1, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z20.b, z21.b }, z10.b, z21.b" + + - + input: + bytes: [ 0xb7, 0xd1, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z22.b, z23.b }, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0xd3, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z30.b, z31.b }, z31.b, z31.b" + + - + input: + bytes: [ 0x02, 0xe0, 0x37, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z0.q - z3.q }, { z0.q - z3.q }" + + - + input: + bytes: [ 0x16, 0xe1, 0x37, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z20.q - z23.q }, { z8.q - z11.q }" + + - + input: + bytes: [ 0x96, 0xe1, 0x37, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z20.q - z23.q }, { z12.q - z15.q }" + + - + input: + bytes: [ 0x9e, 0xe3, 0x37, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z28.q - z31.q }, { z28.q - z31.q }" + + - + input: + bytes: [ 0x02, 0xe0, 0x76, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x16, 0xe1, 0x76, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z20.h - z23.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x96, 0xe1, 0x76, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z20.h - z23.h }, { z12.h - z15.h }" + + - + input: + bytes: [ 0x9e, 0xe3, 0x76, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x02, 0xe0, 0xb6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x16, 0xe1, 0xb6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x96, 0xe1, 0xb6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z20.s - z23.s }, { z12.s - z15.s }" + + - + input: + bytes: [ 0x9e, 0xe3, 0xb6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x02, 0xe0, 0xf6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x16, 0xe1, 0xf6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z20.d - z23.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x96, 0xe1, 0xf6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z20.d - z23.d }, { z12.d - z15.d }" + + - + input: + bytes: [ 0x9e, 0xe3, 0xf6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x02, 0xe0, 0x36, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x16, 0xe1, 0x36, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z20.b - z23.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x96, 0xe1, 0x36, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z20.b - z23.b }, { z12.b - z15.b }" + + - + input: + bytes: [ 0x9e, 0xe3, 0x36, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uzp { z28.b - z31.b }, { z28.b - z31.b }" diff --git a/tests/MC/AArch64/SME2/zero.s.yaml b/tests/MC/AArch64/SME2/zero.s.yaml new file mode 100644 index 0000000000..c222c783cf --- /dev/null +++ b/tests/MC/AArch64/SME2/zero.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x00, 0x48, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zero { zt0 }" diff --git a/tests/MC/AArch64/SME2/zip.s.yaml b/tests/MC/AArch64/SME2/zip.s.yaml new file mode 100644 index 0000000000..8a43f41ddf --- /dev/null +++ b/tests/MC/AArch64/SME2/zip.s.yaml @@ -0,0 +1,400 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xd4, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z0.q, z1.q }, z0.q, z0.q" + + - + input: + bytes: [ 0x54, 0xd5, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z20.q, z21.q }, z10.q, z21.q" + + - + input: + bytes: [ 0xb6, 0xd5, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z22.q, z23.q }, z13.q, z8.q" + + - + input: + bytes: [ 0xfe, 0xd7, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z30.q, z31.q }, z31.q, z31.q" + + - + input: + bytes: [ 0x00, 0xd0, 0x60, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z0.h, z1.h }, z0.h, z0.h" + + - + input: + bytes: [ 0x54, 0xd1, 0x75, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z20.h, z21.h }, z10.h, z21.h" + + - + input: + bytes: [ 0xb6, 0xd1, 0x68, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z22.h, z23.h }, z13.h, z8.h" + + - + input: + bytes: [ 0xfe, 0xd3, 0x7f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z30.h, z31.h }, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0xd0, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z0.s, z1.s }, z0.s, z0.s" + + - + input: + bytes: [ 0x54, 0xd1, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z20.s, z21.s }, z10.s, z21.s" + + - + input: + bytes: [ 0xb6, 0xd1, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z22.s, z23.s }, z13.s, z8.s" + + - + input: + bytes: [ 0xfe, 0xd3, 0xbf, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z30.s, z31.s }, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0xd0, 0xe0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z0.d, z1.d }, z0.d, z0.d" + + - + input: + bytes: [ 0x54, 0xd1, 0xf5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z20.d, z21.d }, z10.d, z21.d" + + - + input: + bytes: [ 0xb6, 0xd1, 0xe8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z22.d, z23.d }, z13.d, z8.d" + + - + input: + bytes: [ 0xfe, 0xd3, 0xff, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z30.d, z31.d }, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0xd0, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z0.b, z1.b }, z0.b, z0.b" + + - + input: + bytes: [ 0x54, 0xd1, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z20.b, z21.b }, z10.b, z21.b" + + - + input: + bytes: [ 0xb6, 0xd1, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z22.b, z23.b }, z13.b, z8.b" + + - + input: + bytes: [ 0xfe, 0xd3, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z30.b, z31.b }, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0xe0, 0x37, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z0.q - z3.q }, { z0.q - z3.q }" + + - + input: + bytes: [ 0x14, 0xe1, 0x37, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z20.q - z23.q }, { z8.q - z11.q }" + + - + input: + bytes: [ 0x94, 0xe1, 0x37, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z20.q - z23.q }, { z12.q - z15.q }" + + - + input: + bytes: [ 0x9c, 0xe3, 0x37, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z28.q - z31.q }, { z28.q - z31.q }" + + - + input: + bytes: [ 0x00, 0xe0, 0x76, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x14, 0xe1, 0x76, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z20.h - z23.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x94, 0xe1, 0x76, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z20.h - z23.h }, { z12.h - z15.h }" + + - + input: + bytes: [ 0x9c, 0xe3, 0x76, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x00, 0xe0, 0xb6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z0.s - z3.s }, { z0.s - z3.s }" + + - + input: + bytes: [ 0x14, 0xe1, 0xb6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z20.s - z23.s }, { z8.s - z11.s }" + + - + input: + bytes: [ 0x94, 0xe1, 0xb6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z20.s - z23.s }, { z12.s - z15.s }" + + - + input: + bytes: [ 0x9c, 0xe3, 0xb6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z28.s - z31.s }, { z28.s - z31.s }" + + - + input: + bytes: [ 0x00, 0xe0, 0xf6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z0.d - z3.d }, { z0.d - z3.d }" + + - + input: + bytes: [ 0x14, 0xe1, 0xf6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z20.d - z23.d }, { z8.d - z11.d }" + + - + input: + bytes: [ 0x94, 0xe1, 0xf6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z20.d - z23.d }, { z12.d - z15.d }" + + - + input: + bytes: [ 0x9c, 0xe3, 0xf6, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z28.d - z31.d }, { z28.d - z31.d }" + + - + input: + bytes: [ 0x00, 0xe0, 0x36, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z0.b - z3.b }, { z0.b - z3.b }" + + - + input: + bytes: [ 0x14, 0xe1, 0x36, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z20.b - z23.b }, { z8.b - z11.b }" + + - + input: + bytes: [ 0x94, 0xe1, 0x36, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z20.b - z23.b }, { z12.b - z15.b }" + + - + input: + bytes: [ 0x9c, 0xe3, 0x36, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "zip { z28.b - z31.b }, { z28.b - z31.b }" diff --git a/tests/MC/AArch64/SME2p1/fadd.s.yaml b/tests/MC/AArch64/SME2p1/fadd.s.yaml new file mode 100644 index 0000000000..75e7cdb2f9 --- /dev/null +++ b/tests/MC/AArch64/SME2p1/fadd.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x1c, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 0, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0x00, 0x1c, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 0, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0x45, 0x5d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w10, 5, vgx2], { z10.h, z11.h }" + + - + input: + bytes: [ 0x45, 0x5d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w10, 5, vgx2], { z10.h, z11.h }" + + - + input: + bytes: [ 0x87, 0x7d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w11, 7, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x87, 0x7d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w11, 7, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0xc7, 0x7f, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w11, 7, vgx2], { z30.h, z31.h }" + + - + input: + bytes: [ 0xc7, 0x7f, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w11, 7, vgx2], { z30.h, z31.h }" + + - + input: + bytes: [ 0x05, 0x1e, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 5, vgx2], { z16.h, z17.h }" + + - + input: + bytes: [ 0x05, 0x1e, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 5, vgx2], { z16.h, z17.h }" + + - + input: + bytes: [ 0x01, 0x1c, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 1, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0x01, 0x1c, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 1, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0x40, 0x5e, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w10, 0, vgx2], { z18.h, z19.h }" + + - + input: + bytes: [ 0x40, 0x5e, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w10, 0, vgx2], { z18.h, z19.h }" + + - + input: + bytes: [ 0x80, 0x1d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 0, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x80, 0x1d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 0, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x01, 0x5c, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w10, 1, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0x01, 0x5c, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w10, 1, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0xc5, 0x1e, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 5, vgx2], { z22.h, z23.h }" + + - + input: + bytes: [ 0xc5, 0x1e, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 5, vgx2], { z22.h, z23.h }" + + - + input: + bytes: [ 0x02, 0x7d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w11, 2, vgx2], { z8.h, z9.h }" + + - + input: + bytes: [ 0x02, 0x7d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w11, 2, vgx2], { z8.h, z9.h }" + + - + input: + bytes: [ 0x87, 0x3d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w9, 7, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x87, 0x3d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w9, 7, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x00, 0x1c, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 0, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x00, 0x1c, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 0, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x05, 0x5d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w10, 5, vgx4], { z8.h - z11.h }" + + - + input: + bytes: [ 0x05, 0x5d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w10, 5, vgx4], { z8.h - z11.h }" + + - + input: + bytes: [ 0x87, 0x7d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w11, 7, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x87, 0x7d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w11, 7, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x87, 0x7f, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w11, 7, vgx4], { z28.h - z31.h }" + + - + input: + bytes: [ 0x87, 0x7f, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w11, 7, vgx4], { z28.h - z31.h }" + + - + input: + bytes: [ 0x05, 0x1e, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 5, vgx4], { z16.h - z19.h }" + + - + input: + bytes: [ 0x05, 0x1e, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 5, vgx4], { z16.h - z19.h }" + + - + input: + bytes: [ 0x01, 0x1c, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 1, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x01, 0x1c, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 1, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x00, 0x5e, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w10, 0, vgx4], { z16.h - z19.h }" + + - + input: + bytes: [ 0x00, 0x5e, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w10, 0, vgx4], { z16.h - z19.h }" + + - + input: + bytes: [ 0x80, 0x1d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 0, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x80, 0x1d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 0, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x01, 0x5c, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w10, 1, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x01, 0x5c, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w10, 1, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x85, 0x1e, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 5, vgx4], { z20.h - z23.h }" + + - + input: + bytes: [ 0x85, 0x1e, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w8, 5, vgx4], { z20.h - z23.h }" + + - + input: + bytes: [ 0x02, 0x7d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w11, 2, vgx4], { z8.h - z11.h }" + + - + input: + bytes: [ 0x02, 0x7d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w11, 2, vgx4], { z8.h - z11.h }" + + - + input: + bytes: [ 0x87, 0x3d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w9, 7, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x87, 0x3d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fadd za.h[w9, 7, vgx4], { z12.h - z15.h }" diff --git a/tests/MC/AArch64/SME2p1/fcvt.s.yaml b/tests/MC/AArch64/SME2p1/fcvt.s.yaml new file mode 100644 index 0000000000..394de62c98 --- /dev/null +++ b/tests/MC/AArch64/SME2p1/fcvt.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fcvt { z0.s, z1.s }, z0.h" + + - + input: + bytes: [ 0x54, 0xe1, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fcvt { z20.s, z21.s }, z10.h" + + - + input: + bytes: [ 0xb6, 0xe1, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fcvt { z22.s, z23.s }, z13.h" + + - + input: + bytes: [ 0xfe, 0xe3, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fcvt { z30.s, z31.s }, z31.h" diff --git a/tests/MC/AArch64/SME2p1/fcvtl.s.yaml b/tests/MC/AArch64/SME2p1/fcvtl.s.yaml new file mode 100644 index 0000000000..23d28aa4c1 --- /dev/null +++ b/tests/MC/AArch64/SME2p1/fcvtl.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x01, 0xe0, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fcvtl { z0.s, z1.s }, z0.h" + + - + input: + bytes: [ 0x55, 0xe1, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fcvtl { z20.s, z21.s }, z10.h" + + - + input: + bytes: [ 0xb7, 0xe1, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fcvtl { z22.s, z23.s }, z13.h" + + - + input: + bytes: [ 0xff, 0xe3, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fcvtl { z30.s, z31.s }, z31.h" diff --git a/tests/MC/AArch64/SME2p1/fmla.s.yaml b/tests/MC/AArch64/SME2p1/fmla.s.yaml new file mode 100644 index 0000000000..38c3351563 --- /dev/null +++ b/tests/MC/AArch64/SME2p1/fmla.s.yaml @@ -0,0 +1,1440 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x1c, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x00, 0x1c, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x45, 0x5d, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x45, 0x5d, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xa7, 0x7d, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xa7, 0x7d, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xe7, 0x7f, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xe7, 0x7f, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x25, 0x1e, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x25, 0x1e, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x1c, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x21, 0x1c, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x60, 0x5e, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x60, 0x5e, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x80, 0x1d, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x80, 0x1d, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x21, 0x5c, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x21, 0x5c, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xc5, 0x1e, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xc5, 0x1e, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x22, 0x7d, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x22, 0x7d, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x87, 0x3d, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x87, 0x3d, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x00, 0x10, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x00, 0x10, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x45, 0x55, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2]" + + - + input: + bytes: [ 0x45, 0x55, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2]" + + - + input: + bytes: [ 0x87, 0x7d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6]" + + - + input: + bytes: [ 0x87, 0x7d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6]" + + - + input: + bytes: [ 0xcf, 0x7f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0xcf, 0x7f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x05, 0x1e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6]" + + - + input: + bytes: [ 0x05, 0x1e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6]" + + - + input: + bytes: [ 0x01, 0x14, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x01, 0x14, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x48, 0x56, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3]" + + - + input: + bytes: [ 0x48, 0x56, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3]" + + - + input: + bytes: [ 0x80, 0x19, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x80, 0x19, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x01, 0x58, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0x01, 0x58, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0xcd, 0x1a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0xcd, 0x1a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x02, 0x75, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x02, 0x75, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x87, 0x39, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4]" + + - + input: + bytes: [ 0x87, 0x39, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4]" + + - + input: + bytes: [ 0x08, 0x10, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x08, 0x10, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x4d, 0x51, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x4d, 0x51, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x8f, 0x71, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x8f, 0x71, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xcf, 0x73, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xcf, 0x73, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x0d, 0x12, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x0d, 0x12, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x09, 0x10, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x09, 0x10, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x48, 0x52, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x48, 0x52, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x88, 0x11, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x88, 0x11, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x09, 0x50, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x09, 0x50, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xcd, 0x12, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xcd, 0x12, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x0a, 0x71, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x0a, 0x71, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x8f, 0x31, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x8f, 0x31, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x00, 0x1c, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x00, 0x1c, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x45, 0x5d, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x45, 0x5d, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xa7, 0x7d, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xa7, 0x7d, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xe7, 0x7f, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xe7, 0x7f, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x25, 0x1e, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x25, 0x1e, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x21, 0x1c, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x21, 0x1c, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x60, 0x5e, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x60, 0x5e, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x80, 0x1d, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x80, 0x1d, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x21, 0x5c, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x21, 0x5c, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xc5, 0x1e, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xc5, 0x1e, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x22, 0x7d, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x22, 0x7d, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x87, 0x3d, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x87, 0x3d, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x00, 0x90, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x00, 0x90, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x05, 0xd5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2]" + + - + input: + bytes: [ 0x05, 0xd5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2]" + + - + input: + bytes: [ 0x87, 0xfd, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6]" + + - + input: + bytes: [ 0x87, 0xfd, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6]" + + - + input: + bytes: [ 0x8f, 0xff, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x8f, 0xff, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x05, 0x9e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6]" + + - + input: + bytes: [ 0x05, 0x9e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6]" + + - + input: + bytes: [ 0x01, 0x94, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x01, 0x94, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x08, 0xd6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3]" + + - + input: + bytes: [ 0x08, 0xd6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3]" + + - + input: + bytes: [ 0x80, 0x99, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x80, 0x99, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x01, 0xd8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x01, 0xd8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x8d, 0x9a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x8d, 0x9a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x02, 0xf5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x02, 0xf5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x87, 0xb9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4]" + + - + input: + bytes: [ 0x87, 0xb9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4]" + + - + input: + bytes: [ 0x08, 0x10, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x08, 0x10, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x0d, 0x51, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x0d, 0x51, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x8f, 0x71, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x8f, 0x71, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x8f, 0x73, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x8f, 0x73, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x0d, 0x12, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x0d, 0x12, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x09, 0x10, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x09, 0x10, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x08, 0x52, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x08, 0x52, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x88, 0x11, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x88, 0x11, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x09, 0x50, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x09, 0x50, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x8d, 0x12, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x8d, 0x12, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x0a, 0x71, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x0a, 0x71, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x8f, 0x31, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x8f, 0x31, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmla za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2p1/fmls.s.yaml b/tests/MC/AArch64/SME2p1/fmls.s.yaml new file mode 100644 index 0000000000..f5f463d9d2 --- /dev/null +++ b/tests/MC/AArch64/SME2p1/fmls.s.yaml @@ -0,0 +1,1440 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x1c, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x08, 0x1c, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h" + + - + input: + bytes: [ 0x4d, 0x5d, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0x4d, 0x5d, 0x25, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h" + + - + input: + bytes: [ 0xaf, 0x7d, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xaf, 0x7d, 0x28, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h" + + - + input: + bytes: [ 0xef, 0x7f, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0xef, 0x7f, 0x2f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h" + + - + input: + bytes: [ 0x2d, 0x1e, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x2d, 0x1e, 0x20, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h" + + - + input: + bytes: [ 0x29, 0x1c, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x29, 0x1c, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h" + + - + input: + bytes: [ 0x68, 0x5e, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x68, 0x5e, 0x24, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h" + + - + input: + bytes: [ 0x88, 0x1d, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x88, 0x1d, 0x22, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h" + + - + input: + bytes: [ 0x29, 0x5c, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0x29, 0x5c, 0x2a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h" + + - + input: + bytes: [ 0xcd, 0x1e, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0xcd, 0x1e, 0x2e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h" + + - + input: + bytes: [ 0x2a, 0x7d, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x2a, 0x7d, 0x21, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h" + + - + input: + bytes: [ 0x8f, 0x3d, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x8f, 0x3d, 0x2b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h" + + - + input: + bytes: [ 0x10, 0x10, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x10, 0x10, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]" + + - + input: + bytes: [ 0x55, 0x55, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2]" + + - + input: + bytes: [ 0x55, 0x55, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2]" + + - + input: + bytes: [ 0x97, 0x7d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6]" + + - + input: + bytes: [ 0x97, 0x7d, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6]" + + - + input: + bytes: [ 0xdf, 0x7f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0xdf, 0x7f, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x15, 0x1e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6]" + + - + input: + bytes: [ 0x15, 0x1e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6]" + + - + input: + bytes: [ 0x11, 0x14, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x11, 0x14, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2]" + + - + input: + bytes: [ 0x58, 0x56, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3]" + + - + input: + bytes: [ 0x58, 0x56, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3]" + + - + input: + bytes: [ 0x90, 0x19, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x90, 0x19, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4]" + + - + input: + bytes: [ 0x11, 0x58, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0x11, 0x58, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4]" + + - + input: + bytes: [ 0xdd, 0x1a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0xdd, 0x1a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x12, 0x75, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x12, 0x75, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2]" + + - + input: + bytes: [ 0x97, 0x39, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4]" + + - + input: + bytes: [ 0x97, 0x39, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4]" + + - + input: + bytes: [ 0x18, 0x10, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x18, 0x10, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x5d, 0x51, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x5d, 0x51, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x9f, 0x71, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0x9f, 0x71, 0xa8, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }" + + - + input: + bytes: [ 0xdf, 0x73, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xdf, 0x73, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x1d, 0x12, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x1d, 0x12, 0xb0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }" + + - + input: + bytes: [ 0x19, 0x10, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x19, 0x10, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x58, 0x52, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x58, 0x52, 0xb4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }" + + - + input: + bytes: [ 0x98, 0x11, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x98, 0x11, 0xa2, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }" + + - + input: + bytes: [ 0x19, 0x50, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0x19, 0x50, 0xba, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }" + + - + input: + bytes: [ 0xdd, 0x12, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0xdd, 0x12, 0xbe, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }" + + - + input: + bytes: [ 0x1a, 0x71, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x1a, 0x71, 0xa0, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }" + + - + input: + bytes: [ 0x9f, 0x31, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x9f, 0x31, 0xaa, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }" + + - + input: + bytes: [ 0x08, 0x1c, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x08, 0x1c, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h" + + - + input: + bytes: [ 0x4d, 0x5d, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0x4d, 0x5d, 0x35, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h" + + - + input: + bytes: [ 0xaf, 0x7d, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xaf, 0x7d, 0x38, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h" + + - + input: + bytes: [ 0xef, 0x7f, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0xef, 0x7f, 0x3f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h" + + - + input: + bytes: [ 0x2d, 0x1e, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x2d, 0x1e, 0x30, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h" + + - + input: + bytes: [ 0x29, 0x1c, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x29, 0x1c, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h" + + - + input: + bytes: [ 0x68, 0x5e, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x68, 0x5e, 0x34, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h" + + - + input: + bytes: [ 0x88, 0x1d, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x88, 0x1d, 0x32, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h" + + - + input: + bytes: [ 0x29, 0x5c, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0x29, 0x5c, 0x3a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h" + + - + input: + bytes: [ 0xcd, 0x1e, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0xcd, 0x1e, 0x3e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h" + + - + input: + bytes: [ 0x2a, 0x7d, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x2a, 0x7d, 0x31, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h" + + - + input: + bytes: [ 0x8f, 0x3d, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x8f, 0x3d, 0x3b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h" + + - + input: + bytes: [ 0x10, 0x90, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x10, 0x90, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]" + + - + input: + bytes: [ 0x15, 0xd5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2]" + + - + input: + bytes: [ 0x15, 0xd5, 0x15, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2]" + + - + input: + bytes: [ 0x97, 0xfd, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6]" + + - + input: + bytes: [ 0x97, 0xfd, 0x18, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6]" + + - + input: + bytes: [ 0x9f, 0xff, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x9f, 0xff, 0x1f, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7]" + + - + input: + bytes: [ 0x15, 0x9e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6]" + + - + input: + bytes: [ 0x15, 0x9e, 0x10, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6]" + + - + input: + bytes: [ 0x11, 0x94, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x11, 0x94, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2]" + + - + input: + bytes: [ 0x18, 0xd6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3]" + + - + input: + bytes: [ 0x18, 0xd6, 0x14, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3]" + + - + input: + bytes: [ 0x90, 0x99, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x90, 0x99, 0x12, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4]" + + - + input: + bytes: [ 0x11, 0xd8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x11, 0xd8, 0x1a, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4]" + + - + input: + bytes: [ 0x9d, 0x9a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x9d, 0x9a, 0x1e, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5]" + + - + input: + bytes: [ 0x12, 0xf5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x12, 0xf5, 0x11, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2]" + + - + input: + bytes: [ 0x97, 0xb9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4]" + + - + input: + bytes: [ 0x97, 0xb9, 0x1b, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4]" + + - + input: + bytes: [ 0x18, 0x10, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x18, 0x10, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x1d, 0x51, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x1d, 0x51, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x9f, 0x71, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x9f, 0x71, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x9f, 0x73, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x9f, 0x73, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x1d, 0x12, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x1d, 0x12, 0xb1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }" + + - + input: + bytes: [ 0x19, 0x10, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x19, 0x10, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x18, 0x52, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x18, 0x52, 0xb5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }" + + - + input: + bytes: [ 0x98, 0x11, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x98, 0x11, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x19, 0x50, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x19, 0x50, 0xb9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }" + + - + input: + bytes: [ 0x9d, 0x12, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x9d, 0x12, 0xbd, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }" + + - + input: + bytes: [ 0x1a, 0x71, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x1a, 0x71, 0xa1, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }" + + - + input: + bytes: [ 0x9f, 0x31, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" + + - + input: + bytes: [ 0x9f, 0x31, 0xa9, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmls za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }" diff --git a/tests/MC/AArch64/SME2p1/fmopa.s.yaml b/tests/MC/AArch64/SME2p1/fmopa.s.yaml new file mode 100644 index 0000000000..b3b47b7f1e --- /dev/null +++ b/tests/MC/AArch64/SME2p1/fmopa.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x00, 0x80, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmopa za0.h, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x49, 0x55, 0x95, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmopa za1.h, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xa9, 0xed, 0x88, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmopa za1.h, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xe9, 0xff, 0x9f, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmopa za1.h, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x29, 0x0e, 0x90, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmopa za1.h, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x29, 0x84, 0x9e, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmopa za1.h, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x68, 0x56, 0x94, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmopa za0.h, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x88, 0x19, 0x82, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmopa za0.h, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x29, 0xc8, 0x9a, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmopa za1.h, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xc9, 0x0a, 0x9e, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmopa za1.h, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x28, 0xf5, 0x81, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmopa za0.h, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x89, 0xa9, 0x8b, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmopa za1.h, p2/m, p5/m, z12.h, z11.h" diff --git a/tests/MC/AArch64/SME2p1/fmops.s.yaml b/tests/MC/AArch64/SME2p1/fmops.s.yaml new file mode 100644 index 0000000000..2c1f8f83af --- /dev/null +++ b/tests/MC/AArch64/SME2p1/fmops.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x00, 0x80, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmops za0.h, p0/m, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x59, 0x55, 0x95, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmops za1.h, p5/m, p2/m, z10.h, z21.h" + + - + input: + bytes: [ 0xb9, 0xed, 0x88, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmops za1.h, p3/m, p7/m, z13.h, z8.h" + + - + input: + bytes: [ 0xf9, 0xff, 0x9f, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmops za1.h, p7/m, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x39, 0x0e, 0x90, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmops za1.h, p3/m, p0/m, z17.h, z16.h" + + - + input: + bytes: [ 0x39, 0x84, 0x9e, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmops za1.h, p1/m, p4/m, z1.h, z30.h" + + - + input: + bytes: [ 0x78, 0x56, 0x94, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmops za0.h, p5/m, p2/m, z19.h, z20.h" + + - + input: + bytes: [ 0x98, 0x19, 0x82, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmops za0.h, p6/m, p0/m, z12.h, z2.h" + + - + input: + bytes: [ 0x39, 0xc8, 0x9a, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmops za1.h, p2/m, p6/m, z1.h, z26.h" + + - + input: + bytes: [ 0xd9, 0x0a, 0x9e, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmops za1.h, p2/m, p0/m, z22.h, z30.h" + + - + input: + bytes: [ 0x38, 0xf5, 0x81, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmops za0.h, p5/m, p7/m, z9.h, z1.h" + + - + input: + bytes: [ 0x99, 0xa9, 0x8b, 0x81 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fmops za1.h, p2/m, p5/m, z12.h, z11.h" diff --git a/tests/MC/AArch64/SME2p1/fsub.s.yaml b/tests/MC/AArch64/SME2p1/fsub.s.yaml new file mode 100644 index 0000000000..a9ee6d650b --- /dev/null +++ b/tests/MC/AArch64/SME2p1/fsub.s.yaml @@ -0,0 +1,470 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x1c, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w8, 0, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0x4d, 0x5d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w10, 5, vgx2], { z10.h, z11.h }" + + - + input: + bytes: [ 0x4d, 0x5d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w10, 5, vgx2], { z10.h, z11.h }" + + - + input: + bytes: [ 0x8f, 0x7d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w11, 7, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x8f, 0x7d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w11, 7, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0xcf, 0x7f, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w11, 7, vgx2], { z30.h, z31.h }" + + - + input: + bytes: [ 0xcf, 0x7f, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w11, 7, vgx2], { z30.h, z31.h }" + + - + input: + bytes: [ 0x0d, 0x1e, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w8, 5, vgx2], { z16.h, z17.h }" + + - + input: + bytes: [ 0x0d, 0x1e, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w8, 5, vgx2], { z16.h, z17.h }" + + - + input: + bytes: [ 0x09, 0x1c, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w8, 1, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0x09, 0x1c, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w8, 1, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0x48, 0x5e, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w10, 0, vgx2], { z18.h, z19.h }" + + - + input: + bytes: [ 0x48, 0x5e, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w10, 0, vgx2], { z18.h, z19.h }" + + - + input: + bytes: [ 0x88, 0x1d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w8, 0, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x88, 0x1d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w8, 0, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x09, 0x5c, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w10, 1, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0x09, 0x5c, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w10, 1, vgx2], { z0.h, z1.h }" + + - + input: + bytes: [ 0xcd, 0x1e, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w8, 5, vgx2], { z22.h, z23.h }" + + - + input: + bytes: [ 0xcd, 0x1e, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w8, 5, vgx2], { z22.h, z23.h }" + + - + input: + bytes: [ 0x0a, 0x7d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w11, 2, vgx2], { z8.h, z9.h }" + + - + input: + bytes: [ 0x0a, 0x7d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w11, 2, vgx2], { z8.h, z9.h }" + + - + input: + bytes: [ 0x8f, 0x3d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w9, 7, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x8f, 0x3d, 0xa4, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w9, 7, vgx2], { z12.h, z13.h }" + + - + input: + bytes: [ 0x08, 0x1c, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w8, 0, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x08, 0x1c, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w8, 0, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x0d, 0x5d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w10, 5, vgx4], { z8.h - z11.h }" + + - + input: + bytes: [ 0x0d, 0x5d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w10, 5, vgx4], { z8.h - z11.h }" + + - + input: + bytes: [ 0x8f, 0x7d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w11, 7, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x8f, 0x7d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w11, 7, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x8f, 0x7f, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w11, 7, vgx4], { z28.h - z31.h }" + + - + input: + bytes: [ 0x8f, 0x7f, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w11, 7, vgx4], { z28.h - z31.h }" + + - + input: + bytes: [ 0x0d, 0x1e, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w8, 5, vgx4], { z16.h - z19.h }" + + - + input: + bytes: [ 0x0d, 0x1e, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w8, 5, vgx4], { z16.h - z19.h }" + + - + input: + bytes: [ 0x09, 0x1c, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w8, 1, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x09, 0x1c, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w8, 1, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x08, 0x5e, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w10, 0, vgx4], { z16.h - z19.h }" + + - + input: + bytes: [ 0x08, 0x5e, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w10, 0, vgx4], { z16.h - z19.h }" + + - + input: + bytes: [ 0x88, 0x1d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w8, 0, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x88, 0x1d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w8, 0, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x09, 0x5c, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w10, 1, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x09, 0x5c, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w10, 1, vgx4], { z0.h - z3.h }" + + - + input: + bytes: [ 0x8d, 0x1e, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w8, 5, vgx4], { z20.h - z23.h }" + + - + input: + bytes: [ 0x8d, 0x1e, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w8, 5, vgx4], { z20.h - z23.h }" + + - + input: + bytes: [ 0x0a, 0x7d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w11, 2, vgx4], { z8.h - z11.h }" + + - + input: + bytes: [ 0x0a, 0x7d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w11, 2, vgx4], { z8.h - z11.h }" + + - + input: + bytes: [ 0x8f, 0x3d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w9, 7, vgx4], { z12.h - z15.h }" + + - + input: + bytes: [ 0x8f, 0x3d, 0xa5, 0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ] + expected: + insns: + - + asm_text: "fsub za.h[w9, 7, vgx4], { z12.h - z15.h }" diff --git a/tests/MC/AArch64/SME2p1/luti2.s.yaml b/tests/MC/AArch64/SME2p1/luti2.s.yaml new file mode 100644 index 0000000000..f854edde0e --- /dev/null +++ b/tests/MC/AArch64/SME2p1/luti2.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x50, 0x9c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti2 { z0.h, z8.h }, zt0, z0[0]" + + - + input: + bytes: [ 0x55, 0x51, 0x9d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti2 { z21.h, z29.h }, zt0, z10[2]" + + - + input: + bytes: [ 0xb7, 0xd1, 0x9c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti2 { z23.h, z31.h }, zt0, z13[1]" + + - + input: + bytes: [ 0xf7, 0xd3, 0x9f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti2 { z23.h, z31.h }, zt0, z31[7]" + + - + input: + bytes: [ 0x00, 0x40, 0x9c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti2 { z0.b, z8.b }, zt0, z0[0]" + + - + input: + bytes: [ 0x55, 0x41, 0x9d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti2 { z21.b, z29.b }, zt0, z10[2]" + + - + input: + bytes: [ 0xb7, 0xc1, 0x9c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti2 { z23.b, z31.b }, zt0, z13[1]" + + - + input: + bytes: [ 0xf7, 0xc3, 0x9f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti2 { z23.b, z31.b }, zt0, z31[7]" + + - + input: + bytes: [ 0x00, 0x90, 0x9c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti2 { z0.h, z4.h, z8.h, z12.h }, zt0, z0[0]" + + - + input: + bytes: [ 0x51, 0x91, 0x9d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti2 { z17.h, z21.h, z25.h, z29.h }, zt0, z10[1]" + + - + input: + bytes: [ 0xb3, 0x91, 0x9c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti2 { z19.h, z23.h, z27.h, z31.h }, zt0, z13[0]" + + - + input: + bytes: [ 0xf3, 0x93, 0x9f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti2 { z19.h, z23.h, z27.h, z31.h }, zt0, z31[3]" + + - + input: + bytes: [ 0x00, 0x80, 0x9c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti2 { z0.b, z4.b, z8.b, z12.b }, zt0, z0[0]" + + - + input: + bytes: [ 0x51, 0x81, 0x9d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti2 { z17.b, z21.b, z25.b, z29.b }, zt0, z10[1]" + + - + input: + bytes: [ 0xb3, 0x81, 0x9c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti2 { z19.b, z23.b, z27.b, z31.b }, zt0, z13[0]" + + - + input: + bytes: [ 0xf3, 0x83, 0x9f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti2 { z19.b, z23.b, z27.b, z31.b }, zt0, z31[3]" diff --git a/tests/MC/AArch64/SME2p1/luti4.s.yaml b/tests/MC/AArch64/SME2p1/luti4.s.yaml new file mode 100644 index 0000000000..54c0396881 --- /dev/null +++ b/tests/MC/AArch64/SME2p1/luti4.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x50, 0x9a, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti4 { z0.h, z8.h }, zt0, z0[0]" + + - + input: + bytes: [ 0x55, 0x51, 0x9b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti4 { z21.h, z29.h }, zt0, z10[2]" + + - + input: + bytes: [ 0xb7, 0xd1, 0x9a, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti4 { z23.h, z31.h }, zt0, z13[1]" + + - + input: + bytes: [ 0xf7, 0xd3, 0x9b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti4 { z23.h, z31.h }, zt0, z31[3]" + + - + input: + bytes: [ 0x00, 0x40, 0x9a, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti4 { z0.b, z8.b }, zt0, z0[0]" + + - + input: + bytes: [ 0x55, 0x41, 0x9b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti4 { z21.b, z29.b }, zt0, z10[2]" + + - + input: + bytes: [ 0xb7, 0xc1, 0x9a, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti4 { z23.b, z31.b }, zt0, z13[1]" + + - + input: + bytes: [ 0xf7, 0xc3, 0x9b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti4 { z23.b, z31.b }, zt0, z31[3]" + + - + input: + bytes: [ 0x00, 0x90, 0x9a, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti4 { z0.h, z4.h, z8.h, z12.h }, zt0, z0[0]" + + - + input: + bytes: [ 0x51, 0x91, 0x9b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti4 { z17.h, z21.h, z25.h, z29.h }, zt0, z10[1]" + + - + input: + bytes: [ 0xb3, 0x91, 0x9a, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti4 { z19.h, z23.h, z27.h, z31.h }, zt0, z13[0]" + + - + input: + bytes: [ 0xf3, 0x93, 0x9b, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "luti4 { z19.h, z23.h, z27.h, z31.h }, zt0, z31[1]" diff --git a/tests/MC/AArch64/SME2p1/movaz.s.yaml b/tests/MC/AArch64/SME2p1/movaz.s.yaml new file mode 100644 index 0000000000..58e85d5619 --- /dev/null +++ b/tests/MC/AArch64/SME2p1/movaz.s.yaml @@ -0,0 +1,1680 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x0a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z0.d, z1.d }, za.d[w8, 0, vgx2]" + + - + input: + bytes: [ 0x00, 0x0a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z0.d, z1.d }, za.d[w8, 0, vgx2]" + + - + input: + bytes: [ 0x54, 0x4a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z20.d, z21.d }, za.d[w10, 2, vgx2]" + + - + input: + bytes: [ 0x54, 0x4a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z20.d, z21.d }, za.d[w10, 2, vgx2]" + + - + input: + bytes: [ 0xb6, 0x6a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z22.d, z23.d }, za.d[w11, 5, vgx2]" + + - + input: + bytes: [ 0xb6, 0x6a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z22.d, z23.d }, za.d[w11, 5, vgx2]" + + - + input: + bytes: [ 0xfe, 0x6a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z30.d, z31.d }, za.d[w11, 7, vgx2]" + + - + input: + bytes: [ 0xfe, 0x6a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z30.d, z31.d }, za.d[w11, 7, vgx2]" + + - + input: + bytes: [ 0x24, 0x0a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z4.d, z5.d }, za.d[w8, 1, vgx2]" + + - + input: + bytes: [ 0x24, 0x0a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z4.d, z5.d }, za.d[w8, 1, vgx2]" + + - + input: + bytes: [ 0x20, 0x0a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z0.d, z1.d }, za.d[w8, 1, vgx2]" + + - + input: + bytes: [ 0x20, 0x0a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z0.d, z1.d }, za.d[w8, 1, vgx2]" + + - + input: + bytes: [ 0x78, 0x4a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z24.d, z25.d }, za.d[w10, 3, vgx2]" + + - + input: + bytes: [ 0x78, 0x4a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z24.d, z25.d }, za.d[w10, 3, vgx2]" + + - + input: + bytes: [ 0x80, 0x0a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z0.d, z1.d }, za.d[w8, 4, vgx2]" + + - + input: + bytes: [ 0x80, 0x0a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z0.d, z1.d }, za.d[w8, 4, vgx2]" + + - + input: + bytes: [ 0x30, 0x4a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z16.d, z17.d }, za.d[w10, 1, vgx2]" + + - + input: + bytes: [ 0x30, 0x4a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z16.d, z17.d }, za.d[w10, 1, vgx2]" + + - + input: + bytes: [ 0xdc, 0x0a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z28.d, z29.d }, za.d[w8, 6, vgx2]" + + - + input: + bytes: [ 0xdc, 0x0a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z28.d, z29.d }, za.d[w8, 6, vgx2]" + + - + input: + bytes: [ 0x22, 0x6a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z2.d, z3.d }, za.d[w11, 1, vgx2]" + + - + input: + bytes: [ 0x22, 0x6a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z2.d, z3.d }, za.d[w11, 1, vgx2]" + + - + input: + bytes: [ 0x86, 0x2a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z6.d, z7.d }, za.d[w9, 4, vgx2]" + + - + input: + bytes: [ 0x86, 0x2a, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z6.d, z7.d }, za.d[w9, 4, vgx2]" + + - + input: + bytes: [ 0x00, 0x0e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z0.d - z3.d }, za.d[w8, 0, vgx4]" + + - + input: + bytes: [ 0x00, 0x0e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z0.d - z3.d }, za.d[w8, 0, vgx4]" + + - + input: + bytes: [ 0x54, 0x4e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z20.d - z23.d }, za.d[w10, 2, vgx4]" + + - + input: + bytes: [ 0x54, 0x4e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z20.d - z23.d }, za.d[w10, 2, vgx4]" + + - + input: + bytes: [ 0xb4, 0x6e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z20.d - z23.d }, za.d[w11, 5, vgx4]" + + - + input: + bytes: [ 0xb4, 0x6e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z20.d - z23.d }, za.d[w11, 5, vgx4]" + + - + input: + bytes: [ 0xfc, 0x6e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z28.d - z31.d }, za.d[w11, 7, vgx4]" + + - + input: + bytes: [ 0xfc, 0x6e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z28.d - z31.d }, za.d[w11, 7, vgx4]" + + - + input: + bytes: [ 0x24, 0x0e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z4.d - z7.d }, za.d[w8, 1, vgx4]" + + - + input: + bytes: [ 0x24, 0x0e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z4.d - z7.d }, za.d[w8, 1, vgx4]" + + - + input: + bytes: [ 0x20, 0x0e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z0.d - z3.d }, za.d[w8, 1, vgx4]" + + - + input: + bytes: [ 0x20, 0x0e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z0.d - z3.d }, za.d[w8, 1, vgx4]" + + - + input: + bytes: [ 0x78, 0x4e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z24.d - z27.d }, za.d[w10, 3, vgx4]" + + - + input: + bytes: [ 0x78, 0x4e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z24.d - z27.d }, za.d[w10, 3, vgx4]" + + - + input: + bytes: [ 0x80, 0x0e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z0.d - z3.d }, za.d[w8, 4, vgx4]" + + - + input: + bytes: [ 0x80, 0x0e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z0.d - z3.d }, za.d[w8, 4, vgx4]" + + - + input: + bytes: [ 0x30, 0x4e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z16.d - z19.d }, za.d[w10, 1, vgx4]" + + - + input: + bytes: [ 0x30, 0x4e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z16.d - z19.d }, za.d[w10, 1, vgx4]" + + - + input: + bytes: [ 0xdc, 0x0e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z28.d - z31.d }, za.d[w8, 6, vgx4]" + + - + input: + bytes: [ 0xdc, 0x0e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z28.d - z31.d }, za.d[w8, 6, vgx4]" + + - + input: + bytes: [ 0x20, 0x6e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z0.d - z3.d }, za.d[w11, 1, vgx4]" + + - + input: + bytes: [ 0x20, 0x6e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z0.d - z3.d }, za.d[w11, 1, vgx4]" + + - + input: + bytes: [ 0x84, 0x2e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z4.d - z7.d }, za.d[w9, 4, vgx4]" + + - + input: + bytes: [ 0x84, 0x2e, 0x06, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz { z4.d - z7.d }, za.d[w9, 4, vgx4]" + + - + input: + bytes: [ 0x00, 0x02, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.q, za0h.q[w12, 0]" + + - + input: + bytes: [ 0x55, 0x43, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z21.q, za10h.q[w14, 0]" + + - + input: + bytes: [ 0xb7, 0x63, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z23.q, za13h.q[w15, 0]" + + - + input: + bytes: [ 0xff, 0x63, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z31.q, za15h.q[w15, 0]" + + - + input: + bytes: [ 0x25, 0x02, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z5.q, za1h.q[w12, 0]" + + - + input: + bytes: [ 0x21, 0x02, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z1.q, za1h.q[w12, 0]" + + - + input: + bytes: [ 0x78, 0x42, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z24.q, za3h.q[w14, 0]" + + - + input: + bytes: [ 0x80, 0x03, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.q, za12h.q[w12, 0]" + + - + input: + bytes: [ 0x31, 0x42, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z17.q, za1h.q[w14, 0]" + + - + input: + bytes: [ 0xdd, 0x02, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z29.q, za6h.q[w12, 0]" + + - + input: + bytes: [ 0x22, 0x63, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z2.q, za9h.q[w15, 0]" + + - + input: + bytes: [ 0x87, 0x23, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z7.q, za12h.q[w13, 0]" + + - + input: + bytes: [ 0x00, 0x82, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.q, za0v.q[w12, 0]" + + - + input: + bytes: [ 0x55, 0xc3, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z21.q, za10v.q[w14, 0]" + + - + input: + bytes: [ 0xb7, 0xe3, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z23.q, za13v.q[w15, 0]" + + - + input: + bytes: [ 0xff, 0xe3, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z31.q, za15v.q[w15, 0]" + + - + input: + bytes: [ 0x25, 0x82, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z5.q, za1v.q[w12, 0]" + + - + input: + bytes: [ 0x21, 0x82, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z1.q, za1v.q[w12, 0]" + + - + input: + bytes: [ 0x78, 0xc2, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z24.q, za3v.q[w14, 0]" + + - + input: + bytes: [ 0x80, 0x83, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.q, za12v.q[w12, 0]" + + - + input: + bytes: [ 0x31, 0xc2, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z17.q, za1v.q[w14, 0]" + + - + input: + bytes: [ 0xdd, 0x82, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z29.q, za6v.q[w12, 0]" + + - + input: + bytes: [ 0x22, 0xe3, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z2.q, za9v.q[w15, 0]" + + - + input: + bytes: [ 0x87, 0xa3, 0xc3, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z7.q, za12v.q[w13, 0]" + + - + input: + bytes: [ 0x00, 0x02, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.h, za0h.h[w12, 0]" + + - + input: + bytes: [ 0x55, 0x43, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z21.h, za1h.h[w14, 2]" + + - + input: + bytes: [ 0xb7, 0x63, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z23.h, za1h.h[w15, 5]" + + - + input: + bytes: [ 0xff, 0x63, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z31.h, za1h.h[w15, 7]" + + - + input: + bytes: [ 0x25, 0x02, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z5.h, za0h.h[w12, 1]" + + - + input: + bytes: [ 0x21, 0x02, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z1.h, za0h.h[w12, 1]" + + - + input: + bytes: [ 0x78, 0x42, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z24.h, za0h.h[w14, 3]" + + - + input: + bytes: [ 0x80, 0x03, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.h, za1h.h[w12, 4]" + + - + input: + bytes: [ 0x31, 0x42, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z17.h, za0h.h[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x02, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z29.h, za0h.h[w12, 6]" + + - + input: + bytes: [ 0x22, 0x63, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z2.h, za1h.h[w15, 1]" + + - + input: + bytes: [ 0x87, 0x23, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z7.h, za1h.h[w13, 4]" + + - + input: + bytes: [ 0x00, 0x82, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.h, za0v.h[w12, 0]" + + - + input: + bytes: [ 0x55, 0xc3, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z21.h, za1v.h[w14, 2]" + + - + input: + bytes: [ 0xb7, 0xe3, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z23.h, za1v.h[w15, 5]" + + - + input: + bytes: [ 0xff, 0xe3, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z31.h, za1v.h[w15, 7]" + + - + input: + bytes: [ 0x25, 0x82, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z5.h, za0v.h[w12, 1]" + + - + input: + bytes: [ 0x21, 0x82, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z1.h, za0v.h[w12, 1]" + + - + input: + bytes: [ 0x78, 0xc2, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z24.h, za0v.h[w14, 3]" + + - + input: + bytes: [ 0x80, 0x83, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.h, za1v.h[w12, 4]" + + - + input: + bytes: [ 0x31, 0xc2, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z17.h, za0v.h[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x82, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z29.h, za0v.h[w12, 6]" + + - + input: + bytes: [ 0x22, 0xe3, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z2.h, za1v.h[w15, 1]" + + - + input: + bytes: [ 0x87, 0xa3, 0x42, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z7.h, za1v.h[w13, 4]" + + - + input: + bytes: [ 0x00, 0x02, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.s, za0h.s[w12, 0]" + + - + input: + bytes: [ 0x55, 0x43, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z21.s, za2h.s[w14, 2]" + + - + input: + bytes: [ 0xb7, 0x63, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z23.s, za3h.s[w15, 1]" + + - + input: + bytes: [ 0xff, 0x63, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z31.s, za3h.s[w15, 3]" + + - + input: + bytes: [ 0x25, 0x02, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z5.s, za0h.s[w12, 1]" + + - + input: + bytes: [ 0x21, 0x02, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z1.s, za0h.s[w12, 1]" + + - + input: + bytes: [ 0x78, 0x42, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z24.s, za0h.s[w14, 3]" + + - + input: + bytes: [ 0x80, 0x03, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.s, za3h.s[w12, 0]" + + - + input: + bytes: [ 0x31, 0x42, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z17.s, za0h.s[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x02, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z29.s, za1h.s[w12, 2]" + + - + input: + bytes: [ 0x22, 0x63, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z2.s, za2h.s[w15, 1]" + + - + input: + bytes: [ 0x87, 0x23, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z7.s, za3h.s[w13, 0]" + + - + input: + bytes: [ 0x00, 0x82, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.s, za0v.s[w12, 0]" + + - + input: + bytes: [ 0x55, 0xc3, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z21.s, za2v.s[w14, 2]" + + - + input: + bytes: [ 0xb7, 0xe3, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z23.s, za3v.s[w15, 1]" + + - + input: + bytes: [ 0xff, 0xe3, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z31.s, za3v.s[w15, 3]" + + - + input: + bytes: [ 0x25, 0x82, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z5.s, za0v.s[w12, 1]" + + - + input: + bytes: [ 0x21, 0x82, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z1.s, za0v.s[w12, 1]" + + - + input: + bytes: [ 0x78, 0xc2, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z24.s, za0v.s[w14, 3]" + + - + input: + bytes: [ 0x80, 0x83, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.s, za3v.s[w12, 0]" + + - + input: + bytes: [ 0x31, 0xc2, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z17.s, za0v.s[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x82, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z29.s, za1v.s[w12, 2]" + + - + input: + bytes: [ 0x22, 0xe3, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z2.s, za2v.s[w15, 1]" + + - + input: + bytes: [ 0x87, 0xa3, 0x82, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z7.s, za3v.s[w13, 0]" + + - + input: + bytes: [ 0x00, 0x02, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.d, za0h.d[w12, 0]" + + - + input: + bytes: [ 0x55, 0x43, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z21.d, za5h.d[w14, 0]" + + - + input: + bytes: [ 0xb7, 0x63, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z23.d, za6h.d[w15, 1]" + + - + input: + bytes: [ 0xff, 0x63, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z31.d, za7h.d[w15, 1]" + + - + input: + bytes: [ 0x25, 0x02, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z5.d, za0h.d[w12, 1]" + + - + input: + bytes: [ 0x21, 0x02, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z1.d, za0h.d[w12, 1]" + + - + input: + bytes: [ 0x78, 0x42, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z24.d, za1h.d[w14, 1]" + + - + input: + bytes: [ 0x80, 0x03, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.d, za6h.d[w12, 0]" + + - + input: + bytes: [ 0x31, 0x42, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z17.d, za0h.d[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x02, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z29.d, za3h.d[w12, 0]" + + - + input: + bytes: [ 0x22, 0x63, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z2.d, za4h.d[w15, 1]" + + - + input: + bytes: [ 0x87, 0x23, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z7.d, za6h.d[w13, 0]" + + - + input: + bytes: [ 0x00, 0x82, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.d, za0v.d[w12, 0]" + + - + input: + bytes: [ 0x55, 0xc3, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z21.d, za5v.d[w14, 0]" + + - + input: + bytes: [ 0xb7, 0xe3, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z23.d, za6v.d[w15, 1]" + + - + input: + bytes: [ 0xff, 0xe3, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z31.d, za7v.d[w15, 1]" + + - + input: + bytes: [ 0x25, 0x82, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z5.d, za0v.d[w12, 1]" + + - + input: + bytes: [ 0x21, 0x82, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z1.d, za0v.d[w12, 1]" + + - + input: + bytes: [ 0x78, 0xc2, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z24.d, za1v.d[w14, 1]" + + - + input: + bytes: [ 0x80, 0x83, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.d, za6v.d[w12, 0]" + + - + input: + bytes: [ 0x31, 0xc2, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z17.d, za0v.d[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x82, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z29.d, za3v.d[w12, 0]" + + - + input: + bytes: [ 0x22, 0xe3, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z2.d, za4v.d[w15, 1]" + + - + input: + bytes: [ 0x87, 0xa3, 0xc2, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z7.d, za6v.d[w13, 0]" + + - + input: + bytes: [ 0x00, 0x02, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.b, za0h.b[w12, 0]" + + - + input: + bytes: [ 0x55, 0x43, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z21.b, za0h.b[w14, 10]" + + - + input: + bytes: [ 0xb7, 0x63, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z23.b, za0h.b[w15, 13]" + + - + input: + bytes: [ 0xff, 0x63, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z31.b, za0h.b[w15, 15]" + + - + input: + bytes: [ 0x25, 0x02, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z5.b, za0h.b[w12, 1]" + + - + input: + bytes: [ 0x21, 0x02, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z1.b, za0h.b[w12, 1]" + + - + input: + bytes: [ 0x78, 0x42, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z24.b, za0h.b[w14, 3]" + + - + input: + bytes: [ 0x80, 0x03, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.b, za0h.b[w12, 12]" + + - + input: + bytes: [ 0x31, 0x42, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z17.b, za0h.b[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x02, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z29.b, za0h.b[w12, 6]" + + - + input: + bytes: [ 0x22, 0x63, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z2.b, za0h.b[w15, 9]" + + - + input: + bytes: [ 0x87, 0x23, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z7.b, za0h.b[w13, 12]" + + - + input: + bytes: [ 0x00, 0x82, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.b, za0v.b[w12, 0]" + + - + input: + bytes: [ 0x55, 0xc3, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z21.b, za0v.b[w14, 10]" + + - + input: + bytes: [ 0xb7, 0xe3, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z23.b, za0v.b[w15, 13]" + + - + input: + bytes: [ 0xff, 0xe3, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z31.b, za0v.b[w15, 15]" + + - + input: + bytes: [ 0x25, 0x82, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z5.b, za0v.b[w12, 1]" + + - + input: + bytes: [ 0x21, 0x82, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z1.b, za0v.b[w12, 1]" + + - + input: + bytes: [ 0x78, 0xc2, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z24.b, za0v.b[w14, 3]" + + - + input: + bytes: [ 0x80, 0x83, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z0.b, za0v.b[w12, 12]" + + - + input: + bytes: [ 0x31, 0xc2, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z17.b, za0v.b[w14, 1]" + + - + input: + bytes: [ 0xdd, 0x82, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z29.b, za0v.b[w12, 6]" + + - + input: + bytes: [ 0x22, 0xe3, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z2.b, za0v.b[w15, 9]" + + - + input: + bytes: [ 0x87, 0xa3, 0x02, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movaz z7.b, za0v.b[w13, 12]" diff --git a/tests/MC/AArch64/SME2p1/zero.s.yaml b/tests/MC/AArch64/SME2p1/zero.s.yaml new file mode 100644 index 0000000000..72e49e7179 --- /dev/null +++ b/tests/MC/AArch64/SME2p1/zero.s.yaml @@ -0,0 +1,620 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x0c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w8, 0:1]" + + - + input: + bytes: [ 0x05, 0xc0, 0x0c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w10, 10:11]" + + - + input: + bytes: [ 0x07, 0xe0, 0x0c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w11, 14:15]" + + - + input: + bytes: [ 0x05, 0x80, 0x0c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w8, 10:11]" + + - + input: + bytes: [ 0x01, 0x80, 0x0c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w8, 2:3]" + + - + input: + bytes: [ 0x00, 0xc0, 0x0c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w10, 0:1]" + + - + input: + bytes: [ 0x01, 0xc0, 0x0c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w10, 2:3]" + + - + input: + bytes: [ 0x02, 0xe0, 0x0c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w11, 4:5]" + + - + input: + bytes: [ 0x07, 0xa0, 0x0c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w9, 14:15]" + + - + input: + bytes: [ 0x00, 0x80, 0x0e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w8, 0:3]" + + - + input: + bytes: [ 0x01, 0xc0, 0x0e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w10, 4:7]" + + - + input: + bytes: [ 0x03, 0xe0, 0x0e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w11, 12:15]" + + - + input: + bytes: [ 0x01, 0x80, 0x0e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w8, 4:7]" + + - + input: + bytes: [ 0x00, 0xc0, 0x0e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w10, 0:3]" + + - + input: + bytes: [ 0x02, 0xe0, 0x0e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w11, 8:11]" + + - + input: + bytes: [ 0x03, 0xa0, 0x0e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w9, 12:15]" + + - + input: + bytes: [ 0x00, 0x00, 0x0c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w8, 0, vgx2]" + + - + input: + bytes: [ 0x05, 0x40, 0x0c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w10, 5, vgx2]" + + - + input: + bytes: [ 0x07, 0x60, 0x0c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w11, 7, vgx2]" + + - + input: + bytes: [ 0x05, 0x00, 0x0c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w8, 5, vgx2]" + + - + input: + bytes: [ 0x01, 0x00, 0x0c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w8, 1, vgx2]" + + - + input: + bytes: [ 0x00, 0x40, 0x0c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w10, 0, vgx2]" + + - + input: + bytes: [ 0x01, 0x40, 0x0c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w10, 1, vgx2]" + + - + input: + bytes: [ 0x02, 0x60, 0x0c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w11, 2, vgx2]" + + - + input: + bytes: [ 0x07, 0x20, 0x0c, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w9, 7, vgx2]" + + - + input: + bytes: [ 0x00, 0x00, 0x0d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w8, 0:1, vgx2]" + + - + input: + bytes: [ 0x01, 0x40, 0x0d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w10, 2:3, vgx2]" + + - + input: + bytes: [ 0x03, 0x60, 0x0d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w11, 6:7, vgx2]" + + - + input: + bytes: [ 0x01, 0x00, 0x0d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w8, 2:3, vgx2]" + + - + input: + bytes: [ 0x00, 0x40, 0x0d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w10, 0:1, vgx2]" + + - + input: + bytes: [ 0x02, 0x60, 0x0d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w11, 4:5, vgx2]" + + - + input: + bytes: [ 0x03, 0x20, 0x0d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w9, 6:7, vgx2]" + + - + input: + bytes: [ 0x00, 0x00, 0x0f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w8, 0:3, vgx2]" + + - + input: + bytes: [ 0x01, 0x40, 0x0f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w10, 4:7, vgx2]" + + - + input: + bytes: [ 0x01, 0x60, 0x0f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w11, 4:7, vgx2]" + + - + input: + bytes: [ 0x01, 0x00, 0x0f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w8, 4:7, vgx2]" + + - + input: + bytes: [ 0x00, 0x40, 0x0f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w10, 0:3, vgx2]" + + - + input: + bytes: [ 0x00, 0x60, 0x0f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w11, 0:3, vgx2]" + + - + input: + bytes: [ 0x01, 0x20, 0x0f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w9, 4:7, vgx2]" + + - + input: + bytes: [ 0x00, 0x00, 0x0e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w8, 0, vgx4]" + + - + input: + bytes: [ 0x05, 0x40, 0x0e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w10, 5, vgx4]" + + - + input: + bytes: [ 0x07, 0x60, 0x0e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w11, 7, vgx4]" + + - + input: + bytes: [ 0x05, 0x00, 0x0e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w8, 5, vgx4]" + + - + input: + bytes: [ 0x01, 0x00, 0x0e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w8, 1, vgx4]" + + - + input: + bytes: [ 0x00, 0x40, 0x0e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w10, 0, vgx4]" + + - + input: + bytes: [ 0x01, 0x40, 0x0e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w10, 1, vgx4]" + + - + input: + bytes: [ 0x02, 0x60, 0x0e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w11, 2, vgx4]" + + - + input: + bytes: [ 0x07, 0x20, 0x0e, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w9, 7, vgx4]" + + - + input: + bytes: [ 0x00, 0x80, 0x0d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w8, 0:1, vgx4]" + + - + input: + bytes: [ 0x01, 0xc0, 0x0d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w10, 2:3, vgx4]" + + - + input: + bytes: [ 0x03, 0xe0, 0x0d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w11, 6:7, vgx4]" + + - + input: + bytes: [ 0x01, 0x80, 0x0d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w8, 2:3, vgx4]" + + - + input: + bytes: [ 0x00, 0xc0, 0x0d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w10, 0:1, vgx4]" + + - + input: + bytes: [ 0x02, 0xe0, 0x0d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w11, 4:5, vgx4]" + + - + input: + bytes: [ 0x03, 0xa0, 0x0d, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w9, 6:7, vgx4]" + + - + input: + bytes: [ 0x00, 0x80, 0x0f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w8, 0:3, vgx4]" + + - + input: + bytes: [ 0x01, 0xc0, 0x0f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w10, 4:7, vgx4]" + + - + input: + bytes: [ 0x01, 0xe0, 0x0f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w11, 4:7, vgx4]" + + - + input: + bytes: [ 0x01, 0x80, 0x0f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w8, 4:7, vgx4]" + + - + input: + bytes: [ 0x00, 0xc0, 0x0f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w10, 0:3, vgx4]" + + - + input: + bytes: [ 0x00, 0xe0, 0x0f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w11, 0:3, vgx4]" + + - + input: + bytes: [ 0x01, 0xa0, 0x0f, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zero za.d[w9, 4:7, vgx4]" diff --git a/tests/MC/AArch64/SVE/abs.s.yaml b/tests/MC/AArch64/SVE/abs.s.yaml new file mode 100644 index 0000000000..37c56c133a --- /dev/null +++ b/tests/MC/AArch64/SVE/abs.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x16, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "abs z0.b, p0/m, z0.b" + + - + input: + bytes: [ 0x00, 0xa0, 0x56, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "abs z0.h, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x96, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "abs z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "abs z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x16, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "abs z31.b, p7/m, z31.b" + + - + input: + bytes: [ 0xff, 0xbf, 0x56, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "abs z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x96, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "abs z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xd6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "abs z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "abs z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "abs z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x16, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "abs z0.b, p0/m, z0.b" + + - + input: + bytes: [ 0x00, 0xa0, 0x56, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "abs z0.h, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x96, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "abs z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "abs z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x16, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "abs z31.b, p7/m, z31.b" + + - + input: + bytes: [ 0xff, 0xbf, 0x56, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "abs z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x96, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "abs z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xd6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "abs z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "abs z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "abs z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/add.s.yaml b/tests/MC/AArch64/SVE/add.s.yaml new file mode 100644 index 0000000000..6e8b3c61a1 --- /dev/null +++ b/tests/MC/AArch64/SVE/add.s.yaml @@ -0,0 +1,1040 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x03, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0xb7, 0x01, 0xe8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xb7, 0x0d, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z23.b, p3/m, z23.b, z13.b" + + - + input: + bytes: [ 0x00, 0x00, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0xff, 0x03, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x55, 0x01, 0x35, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z21.b, z10.b, z21.b" + + - + input: + bytes: [ 0xff, 0x03, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x00, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z0.b, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z0.s, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0xb7, 0x01, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z23.b, z13.b, z8.b" + + - + input: + bytes: [ 0x00, 0x00, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z0.d, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0xff, 0x03, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x55, 0x01, 0xf5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z21.d, z10.d, z21.d" + + - + input: + bytes: [ 0xb7, 0x0d, 0x40, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xb7, 0x0d, 0x80, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z23.s, p3/m, z23.s, z13.s" + + - + input: + bytes: [ 0xff, 0x1f, 0x80, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0x55, 0x01, 0x75, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0x0d, 0xc0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z23.d, p3/m, z23.d, z13.d" + + - + input: + bytes: [ 0x55, 0x15, 0xc0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z21.d, p5/m, z21.d, z10.d" + + - + input: + bytes: [ 0x55, 0x15, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z21.b, p5/m, z21.b, z10.b" + + - + input: + bytes: [ 0x55, 0x01, 0xb5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z21.s, z10.s, z21.s" + + - + input: + bytes: [ 0x55, 0x15, 0x40, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z21.h, p5/m, z21.h, z10.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x40, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xb7, 0x01, 0x68, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0x1f, 0xc0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0x55, 0x15, 0x80, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z21.s, p5/m, z21.s, z10.s" + + - + input: + bytes: [ 0xff, 0x1f, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xb7, 0x01, 0xa8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0x00, 0xc0, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z0.h, z0.h, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z0.h, z0.h, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z31.h, z31.h, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z31.h, z31.h, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z0.s, z0.s, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z0.s, z0.s, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z31.s, z31.s, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z31.s, z31.s, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z0.d, z0.d, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z0.d, z0.d, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xc4, 0x3c, 0x10, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.b, p7/z, z6.b" + + - + input: + bytes: [ 0xe4, 0x1f, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z4.b, p7/m, z4.b, z31.b" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z4.b, p7/m, z4.b, z31.b" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xff, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xff, 0x03, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0xb7, 0x01, 0xe8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xb7, 0x0d, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z23.b, p3/m, z23.b, z13.b" + + - + input: + bytes: [ 0x00, 0x00, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0xff, 0x03, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x55, 0x01, 0x35, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z21.b, z10.b, z21.b" + + - + input: + bytes: [ 0xff, 0x03, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x00, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z0.b, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z0.s, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0xb7, 0x01, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z23.b, z13.b, z8.b" + + - + input: + bytes: [ 0x00, 0x00, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z0.d, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0xff, 0x03, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x55, 0x01, 0xf5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z21.d, z10.d, z21.d" + + - + input: + bytes: [ 0xb7, 0x0d, 0x40, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xb7, 0x0d, 0x80, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z23.s, p3/m, z23.s, z13.s" + + - + input: + bytes: [ 0xff, 0x1f, 0x80, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0x55, 0x01, 0x75, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0x0d, 0xc0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z23.d, p3/m, z23.d, z13.d" + + - + input: + bytes: [ 0x55, 0x15, 0xc0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z21.d, p5/m, z21.d, z10.d" + + - + input: + bytes: [ 0x55, 0x15, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z21.b, p5/m, z21.b, z10.b" + + - + input: + bytes: [ 0x55, 0x01, 0xb5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z21.s, z10.s, z21.s" + + - + input: + bytes: [ 0x55, 0x15, 0x40, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z21.h, p5/m, z21.h, z10.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x40, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xb7, 0x01, 0x68, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0x1f, 0xc0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0x55, 0x15, 0x80, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z21.s, p5/m, z21.s, z10.s" + + - + input: + bytes: [ 0xff, 0x1f, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xb7, 0x01, 0xa8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0x00, 0xc0, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z0.h, z0.h, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z0.h, z0.h, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z31.h, z31.h, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z31.h, z31.h, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z0.s, z0.s, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z0.s, z0.s, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z31.s, z31.s, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z31.s, z31.s, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z0.d, z0.d, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z0.d, z0.d, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xc4, 0x3c, 0x10, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.b, p7/z, z6.b" + + - + input: + bytes: [ 0xe4, 0x1f, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z4.b, p7/m, z4.b, z31.b" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z4.b, p7/m, z4.b, z31.b" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xff, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z31.d, z31.d, #65280" diff --git a/tests/MC/AArch64/SVE/addpl.s.yaml b/tests/MC/AArch64/SVE/addpl.s.yaml new file mode 100644 index 0000000000..413cec1fc2 --- /dev/null +++ b/tests/MC/AArch64/SVE/addpl.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x15, 0x50, 0x75, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "addpl x21, x21, #0" + + - + input: + bytes: [ 0xf7, 0x57, 0x68, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "addpl x23, x8, #-1" + + - + input: + bytes: [ 0xff, 0x53, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "addpl sp, sp, #31" + + - + input: + bytes: [ 0x00, 0x54, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "addpl x0, x0, #-32" + + - + input: + bytes: [ 0x15, 0x50, 0x75, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addpl x21, x21, #0" + + - + input: + bytes: [ 0xf7, 0x57, 0x68, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addpl x23, x8, #-1" + + - + input: + bytes: [ 0xff, 0x53, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addpl sp, sp, #31" + + - + input: + bytes: [ 0x00, 0x54, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addpl x0, x0, #-32" diff --git a/tests/MC/AArch64/SVE/addvl.s.yaml b/tests/MC/AArch64/SVE/addvl.s.yaml new file mode 100644 index 0000000000..a3a1e6b01b --- /dev/null +++ b/tests/MC/AArch64/SVE/addvl.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x15, 0x50, 0x35, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "addvl x21, x21, #0" + + - + input: + bytes: [ 0xf7, 0x57, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "addvl x23, x8, #-1" + + - + input: + bytes: [ 0xff, 0x53, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "addvl sp, sp, #31" + + - + input: + bytes: [ 0x00, 0x54, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "addvl x0, x0, #-32" + + - + input: + bytes: [ 0x15, 0x50, 0x35, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addvl x21, x21, #0" + + - + input: + bytes: [ 0xf7, 0x57, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addvl x23, x8, #-1" + + - + input: + bytes: [ 0xff, 0x53, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addvl sp, sp, #31" + + - + input: + bytes: [ 0x00, 0x54, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addvl x0, x0, #-32" diff --git a/tests/MC/AArch64/SVE/adr.s.yaml b/tests/MC/AArch64/SVE/adr.s.yaml new file mode 100644 index 0000000000..6b13b0414d --- /dev/null +++ b/tests/MC/AArch64/SVE/adr.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.s, [z0.s, z0.s]" + + - + input: + bytes: [ 0x00, 0xa0, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.s, [z0.s, z0.s]" + + - + input: + bytes: [ 0x00, 0xa4, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.s, [z0.s, z0.s, lsl #1]" + + - + input: + bytes: [ 0x00, 0xa8, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.s, [z0.s, z0.s, lsl #2]" + + - + input: + bytes: [ 0x00, 0xac, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.s, [z0.s, z0.s, lsl #3]" + + - + input: + bytes: [ 0x00, 0xa0, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.d, [z0.d, z0.d]" + + - + input: + bytes: [ 0x00, 0xa0, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.d, [z0.d, z0.d]" + + - + input: + bytes: [ 0x00, 0xa4, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.d, [z0.d, z0.d, lsl #1]" + + - + input: + bytes: [ 0x00, 0xa8, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.d, [z0.d, z0.d, lsl #2]" + + - + input: + bytes: [ 0x00, 0xac, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.d, [z0.d, z0.d, lsl #3]" + + - + input: + bytes: [ 0x00, 0xa0, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.d, [z0.d, z0.d, uxtw]" + + - + input: + bytes: [ 0x00, 0xa0, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.d, [z0.d, z0.d, uxtw]" + + - + input: + bytes: [ 0x00, 0xa4, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.d, [z0.d, z0.d, uxtw #1]" + + - + input: + bytes: [ 0x00, 0xa8, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.d, [z0.d, z0.d, uxtw #2]" + + - + input: + bytes: [ 0x00, 0xac, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.d, [z0.d, z0.d, uxtw #3]" + + - + input: + bytes: [ 0x00, 0xa0, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.d, [z0.d, z0.d, sxtw]" + + - + input: + bytes: [ 0x00, 0xa0, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.d, [z0.d, z0.d, sxtw]" + + - + input: + bytes: [ 0x00, 0xa4, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.d, [z0.d, z0.d, sxtw #1]" + + - + input: + bytes: [ 0x00, 0xa8, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.d, [z0.d, z0.d, sxtw #2]" + + - + input: + bytes: [ 0x00, 0xac, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "adr z0.d, [z0.d, z0.d, sxtw #3]" diff --git a/tests/MC/AArch64/SVE/and.s.yaml b/tests/MC/AArch64/SVE/and.s.yaml new file mode 100644 index 0000000000..cafa684d92 --- /dev/null +++ b/tests/MC/AArch64/SVE/and.s.yaml @@ -0,0 +1,520 @@ +test_cases: + - + input: + bytes: [ 0xa5, 0x2e, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z5.b, z5.b, #0xf9" + + - + input: + bytes: [ 0xb7, 0x6d, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z23.h, z23.h, #0xfff9" + + - + input: + bytes: [ 0xa0, 0xeb, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z0.s, z0.s, #0xfffffff9" + + - + input: + bytes: [ 0xa0, 0xef, 0x83, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, #0xfffffffffffffff9" + + - + input: + bytes: [ 0x25, 0x3e, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z5.b, z5.b, #0x6" + + - + input: + bytes: [ 0x37, 0x7c, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z23.h, z23.h, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z0.s, z0.s, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x83, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, #0x6" + + - + input: + bytes: [ 0x00, 0x30, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0xb7, 0x31, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0x1f, 0x1a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x1f, 0x5a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x9a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0xda, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0x40, 0x01, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and p0.b, p0/z, p0.b, p1.b" + + - + input: + bytes: [ 0x00, 0x40, 0x00, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov p0.b, p0/z, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov p15.b, p15/z, p15.b" + + - + input: + bytes: [ 0x00, 0x30, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x30, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x30, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x1f, 0xda, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0xda, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xf8, 0x83, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, #0x6" + + - + input: + bytes: [ 0xa5, 0x2e, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z5.b, z5.b, #0xf9" + + - + input: + bytes: [ 0xb7, 0x6d, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z23.h, z23.h, #0xfff9" + + - + input: + bytes: [ 0xa0, 0xeb, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z0.s, z0.s, #0xfffffff9" + + - + input: + bytes: [ 0xa0, 0xef, 0x83, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, #0xfffffffffffffff9" + + - + input: + bytes: [ 0x25, 0x3e, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z5.b, z5.b, #0x6" + + - + input: + bytes: [ 0x37, 0x7c, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z23.h, z23.h, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z0.s, z0.s, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x83, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, #0x6" + + - + input: + bytes: [ 0x00, 0x30, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0xb7, 0x31, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0x1f, 0x1a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x1f, 0x5a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x9a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0xda, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0x40, 0x01, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and p0.b, p0/z, p0.b, p1.b" + + - + input: + bytes: [ 0x00, 0x40, 0x00, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov p0.b, p0/z, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov p15.b, p15/z, p15.b" + + - + input: + bytes: [ 0x00, 0x30, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x30, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x30, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x1f, 0xda, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0xda, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xf8, 0x83, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, #0x6" diff --git a/tests/MC/AArch64/SVE/ands.s.yaml b/tests/MC/AArch64/SVE/ands.s.yaml new file mode 100644 index 0000000000..f48e492a17 --- /dev/null +++ b/tests/MC/AArch64/SVE/ands.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0x41, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ands p0.b, p0/z, p0.b, p1.b" + + - + input: + bytes: [ 0x00, 0x40, 0x40, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movs p0.b, p0/z, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movs p15.b, p15/z, p15.b" + + - + input: + bytes: [ 0x00, 0x40, 0x41, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ands p0.b, p0/z, p0.b, p1.b" + + - + input: + bytes: [ 0x00, 0x40, 0x40, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movs p0.b, p0/z, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movs p15.b, p15/z, p15.b" diff --git a/tests/MC/AArch64/SVE/andv.s.yaml b/tests/MC/AArch64/SVE/andv.s.yaml new file mode 100644 index 0000000000..eebf898e5c --- /dev/null +++ b/tests/MC/AArch64/SVE/andv.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x3f, 0x1a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "andv b0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x5a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "andv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x9a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "andv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xda, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "andv d0, p7, z31.d" + + - + input: + bytes: [ 0xe0, 0x3f, 0x1a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "andv b0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x5a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "andv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x9a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "andv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xda, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "andv d0, p7, z31.d" diff --git a/tests/MC/AArch64/SVE/armv9.5a-cpa.s.yaml b/tests/MC/AArch64/SVE/armv9.5a-cpa.s.yaml new file mode 100644 index 0000000000..81de7a29e8 --- /dev/null +++ b/tests/MC/AArch64/SVE/armv9.5a-cpa.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xb7, 0x09, 0xe8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "cpa" ] + expected: + insns: + - + asm_text: "addpt z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xb7, 0x0d, 0xc4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "cpa" ] + expected: + insns: + - + asm_text: "addpt z23.d, p3/m, z23.d, z13.d" + + - + input: + bytes: [ 0xb7, 0x0d, 0xe8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "cpa" ] + expected: + insns: + - + asm_text: "subpt z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xb7, 0x0d, 0xc5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "cpa" ] + expected: + insns: + - + asm_text: "subpt z23.d, p3/m, z23.d, z13.d" + + - + input: + bytes: [ 0xe0, 0xdb, 0xc1, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "cpa" ] + expected: + insns: + - + asm_text: "madpt z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0xd0, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "cpa" ] + expected: + insns: + - + asm_text: "mlapt z0.d, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE/asr.s.yaml b/tests/MC/AArch64/SVE/asr.s.yaml new file mode 100644 index 0000000000..c515463cae --- /dev/null +++ b/tests/MC/AArch64/SVE/asr.s.yaml @@ -0,0 +1,680 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x90, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.b, z0.b, #1" + + - + input: + bytes: [ 0xff, 0x93, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z31.b, z31.b, #8" + + - + input: + bytes: [ 0x00, 0x90, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.h, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x93, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z31.h, z31.h, #16" + + - + input: + bytes: [ 0x00, 0x90, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.s, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x93, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z31.s, z31.s, #32" + + - + input: + bytes: [ 0x00, 0x90, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.d, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x93, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z31.d, z31.d, #64" + + - + input: + bytes: [ 0xe0, 0x81, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.b, p0/m, z0.b, #1" + + - + input: + bytes: [ 0x1f, 0x81, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z31.b, p0/m, z31.b, #8" + + - + input: + bytes: [ 0xe0, 0x83, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.h, p0/m, z0.h, #1" + + - + input: + bytes: [ 0x1f, 0x82, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z31.h, p0/m, z31.h, #16" + + - + input: + bytes: [ 0xe0, 0x83, 0x40, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.s, p0/m, z0.s, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x40, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z31.s, p0/m, z31.s, #32" + + - + input: + bytes: [ 0xe0, 0x83, 0xc0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.d, p0/m, z0.d, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x80, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0x00, 0x80, 0x10, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.b, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x80, 0x50, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.s, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.d, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0x20, 0x80, 0x18, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.b, p0/m, z0.b, z1.d" + + - + input: + bytes: [ 0x20, 0x80, 0x58, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.h, p0/m, z0.h, z1.d" + + - + input: + bytes: [ 0x20, 0x80, 0x98, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.s, p0/m, z0.s, z1.d" + + - + input: + bytes: [ 0x20, 0x80, 0x22, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.b, z1.b, z2.d" + + - + input: + bytes: [ 0x20, 0x80, 0x62, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.h, z1.h, z2.d" + + - + input: + bytes: [ 0x20, 0x80, 0xa2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.s, z1.s, z2.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0x1f, 0x80, 0x80, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x1f, 0x80, 0x80, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xe0, 0x20, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.s, p0/z, z7.s" + + - + input: + bytes: [ 0x20, 0x80, 0x98, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.s, p0/m, z0.s, z1.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x80, 0x98, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asr z0.s, p0/m, z0.s, z1.d" + + - + input: + bytes: [ 0x00, 0x90, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.b, z0.b, #1" + + - + input: + bytes: [ 0xff, 0x93, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z31.b, z31.b, #8" + + - + input: + bytes: [ 0x00, 0x90, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.h, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x93, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z31.h, z31.h, #16" + + - + input: + bytes: [ 0x00, 0x90, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.s, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x93, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z31.s, z31.s, #32" + + - + input: + bytes: [ 0x00, 0x90, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.d, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x93, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z31.d, z31.d, #64" + + - + input: + bytes: [ 0xe0, 0x81, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.b, p0/m, z0.b, #1" + + - + input: + bytes: [ 0x1f, 0x81, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z31.b, p0/m, z31.b, #8" + + - + input: + bytes: [ 0xe0, 0x83, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.h, p0/m, z0.h, #1" + + - + input: + bytes: [ 0x1f, 0x82, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z31.h, p0/m, z31.h, #16" + + - + input: + bytes: [ 0xe0, 0x83, 0x40, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.s, p0/m, z0.s, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x40, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z31.s, p0/m, z31.s, #32" + + - + input: + bytes: [ 0xe0, 0x83, 0xc0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.d, p0/m, z0.d, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x80, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0x00, 0x80, 0x10, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.b, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x80, 0x50, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.s, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.d, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0x20, 0x80, 0x18, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.b, p0/m, z0.b, z1.d" + + - + input: + bytes: [ 0x20, 0x80, 0x58, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.h, p0/m, z0.h, z1.d" + + - + input: + bytes: [ 0x20, 0x80, 0x98, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.s, p0/m, z0.s, z1.d" + + - + input: + bytes: [ 0x20, 0x80, 0x22, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.b, z1.b, z2.d" + + - + input: + bytes: [ 0x20, 0x80, 0x62, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.h, z1.h, z2.d" + + - + input: + bytes: [ 0x20, 0x80, 0xa2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.s, z1.s, z2.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0x1f, 0x80, 0x80, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x1f, 0x80, 0x80, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xe0, 0x20, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.s, p0/z, z7.s" + + - + input: + bytes: [ 0x20, 0x80, 0x98, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.s, p0/m, z0.s, z1.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x80, 0x98, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asr z0.s, p0/m, z0.s, z1.d" diff --git a/tests/MC/AArch64/SVE/asrd.s.yaml b/tests/MC/AArch64/SVE/asrd.s.yaml new file mode 100644 index 0000000000..e8ae5ecf5b --- /dev/null +++ b/tests/MC/AArch64/SVE/asrd.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x81, 0x04, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asrd z0.b, p0/m, z0.b, #1" + + - + input: + bytes: [ 0x1f, 0x81, 0x04, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asrd z31.b, p0/m, z31.b, #8" + + - + input: + bytes: [ 0xe0, 0x83, 0x04, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asrd z0.h, p0/m, z0.h, #1" + + - + input: + bytes: [ 0x1f, 0x82, 0x04, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asrd z31.h, p0/m, z31.h, #16" + + - + input: + bytes: [ 0xe0, 0x83, 0x44, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asrd z0.s, p0/m, z0.s, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x44, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asrd z31.s, p0/m, z31.s, #32" + + - + input: + bytes: [ 0xe0, 0x83, 0xc4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asrd z0.d, p0/m, z0.d, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x84, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asrd z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0x1f, 0x80, 0x84, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asrd z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x1f, 0x80, 0x84, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asrd z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xe0, 0x81, 0x04, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asrd z0.b, p0/m, z0.b, #1" + + - + input: + bytes: [ 0x1f, 0x81, 0x04, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asrd z31.b, p0/m, z31.b, #8" + + - + input: + bytes: [ 0xe0, 0x83, 0x04, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asrd z0.h, p0/m, z0.h, #1" + + - + input: + bytes: [ 0x1f, 0x82, 0x04, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asrd z31.h, p0/m, z31.h, #16" + + - + input: + bytes: [ 0xe0, 0x83, 0x44, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asrd z0.s, p0/m, z0.s, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x44, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asrd z31.s, p0/m, z31.s, #32" + + - + input: + bytes: [ 0xe0, 0x83, 0xc4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asrd z0.d, p0/m, z0.d, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x84, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asrd z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0x1f, 0x80, 0x84, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asrd z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x1f, 0x80, 0x84, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asrd z31.d, p0/m, z31.d, #64" diff --git a/tests/MC/AArch64/SVE/asrr.s.yaml b/tests/MC/AArch64/SVE/asrr.s.yaml new file mode 100644 index 0000000000..df49117380 --- /dev/null +++ b/tests/MC/AArch64/SVE/asrr.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x14, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asrr z0.b, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x80, 0x54, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asrr z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x94, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asrr z0.s, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asrr z0.d, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0x80, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asrr z5.d, p0/m, z5.d, z0.d" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0x80, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "asrr z5.d, p0/m, z5.d, z0.d" + + - + input: + bytes: [ 0x00, 0x80, 0x14, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asrr z0.b, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x80, 0x54, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asrr z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x94, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asrr z0.s, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asrr z0.d, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0x80, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asrr z5.d, p0/m, z5.d, z0.d" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0x80, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "asrr z5.d, p0/m, z5.d, z0.d" diff --git a/tests/MC/AArch64/SVE/bfcvt.s.yaml b/tests/MC/AArch64/SVE/bfcvt.s.yaml new file mode 100644 index 0000000000..0288514d49 --- /dev/null +++ b/tests/MC/AArch64/SVE/bfcvt.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa0, 0x8a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfcvt z0.h, p0/m, z1.s" + + - + input: + bytes: [ 0x40, 0x20, 0x91, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0.s, p0/m, z2.s" + + - + input: + bytes: [ 0x20, 0xa0, 0x8a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfcvt z0.h, p0/m, z1.s" + + - + input: + bytes: [ 0x40, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z2" + + - + input: + bytes: [ 0x20, 0xa0, 0x8a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfcvt z0.h, p0/m, z1.s" + + - + input: + bytes: [ 0x20, 0xa0, 0x8a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfcvt z0.h, p0/m, z1.s" + + - + input: + bytes: [ 0x40, 0x20, 0x91, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0.s, p0/m, z2.s" + + - + input: + bytes: [ 0x20, 0xa0, 0x8a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfcvt z0.h, p0/m, z1.s" + + - + input: + bytes: [ 0x40, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z2" + + - + input: + bytes: [ 0x20, 0xa0, 0x8a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfcvt z0.h, p0/m, z1.s" diff --git a/tests/MC/AArch64/SVE/bfcvtnt.s.yaml b/tests/MC/AArch64/SVE/bfcvtnt.s.yaml new file mode 100644 index 0000000000..e21e1d21a0 --- /dev/null +++ b/tests/MC/AArch64/SVE/bfcvtnt.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa0, 0x8a, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfcvtnt z0.h, p0/m, z1.s" + + - + input: + bytes: [ 0x40, 0x20, 0x91, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0.s, p0/m, z2.s" + + - + input: + bytes: [ 0x20, 0xa0, 0x8a, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfcvtnt z0.h, p0/m, z1.s" + + - + input: + bytes: [ 0x40, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z2" + + - + input: + bytes: [ 0x20, 0xa0, 0x8a, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfcvtnt z0.h, p0/m, z1.s" + + - + input: + bytes: [ 0x20, 0xa0, 0x8a, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfcvtnt z0.h, p0/m, z1.s" + + - + input: + bytes: [ 0x40, 0x20, 0x91, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0.s, p0/m, z2.s" + + - + input: + bytes: [ 0x20, 0xa0, 0x8a, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfcvtnt z0.h, p0/m, z1.s" + + - + input: + bytes: [ 0x40, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z2" + + - + input: + bytes: [ 0x20, 0xa0, 0x8a, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfcvtnt z0.h, p0/m, z1.s" diff --git a/tests/MC/AArch64/SVE/bfdot.s.yaml b/tests/MC/AArch64/SVE/bfdot.s.yaml new file mode 100644 index 0000000000..9da70342ff --- /dev/null +++ b/tests/MC/AArch64/SVE/bfdot.s.yaml @@ -0,0 +1,180 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x62, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfdot z0.s, z1.h, z2.h" + + - + input: + bytes: [ 0x20, 0x40, 0x62, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfdot z0.s, z1.h, z2.h[0]" + + - + input: + bytes: [ 0x20, 0x40, 0x7a, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfdot z0.s, z1.h, z2.h[3]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x80, 0x62, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfdot z0.s, z1.h, z2.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x40, 0x62, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfdot z0.s, z1.h, z2.h[0]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x40, 0x7a, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfdot z0.s, z1.h, z2.h[3]" + + - + input: + bytes: [ 0x20, 0x80, 0x62, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfdot z0.s, z1.h, z2.h" + + - + input: + bytes: [ 0x20, 0x40, 0x62, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfdot z0.s, z1.h, z2.h[0]" + + - + input: + bytes: [ 0x20, 0x40, 0x7a, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfdot z0.s, z1.h, z2.h[3]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x80, 0x62, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfdot z0.s, z1.h, z2.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x40, 0x62, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfdot z0.s, z1.h, z2.h[0]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x40, 0x7a, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfdot z0.s, z1.h, z2.h[3]" diff --git a/tests/MC/AArch64/SVE/bfmlal.s.yaml b/tests/MC/AArch64/SVE/bfmlal.s.yaml new file mode 100644 index 0000000000..819f7a7cf7 --- /dev/null +++ b/tests/MC/AArch64/SVE/bfmlal.s.yaml @@ -0,0 +1,600 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0xe2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z0.s, z1.h, z2.h" + + - + input: + bytes: [ 0x20, 0x84, 0xe2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z0.s, z1.h, z2.h" + + - + input: + bytes: [ 0x20, 0x40, 0xe2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z0.s, z1.h, z2.h[0]" + + - + input: + bytes: [ 0x20, 0x44, 0xe2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z0.s, z1.h, z2.h[0]" + + - + input: + bytes: [ 0x20, 0x48, 0xfa, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z0.s, z1.h, z2.h[7]" + + - + input: + bytes: [ 0x20, 0x4c, 0xfa, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z0.s, z1.h, z2.h[7]" + + - + input: + bytes: [ 0x20, 0x4c, 0xff, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0xaa, 0x82, 0xee, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z10.s, z21.h, z14.h" + + - + input: + bytes: [ 0x4e, 0x85, 0xf5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z14.s, z10.h, z21.h" + + - + input: + bytes: [ 0xd5, 0x41, 0xeb, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z21.s, z14.h, z3.h[2]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x80, 0xe2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z0.s, z1.h, z2.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x84, 0xe2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z0.s, z1.h, z2.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x40, 0xe2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z0.s, z1.h, z2.h[0]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x44, 0xe2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z0.s, z1.h, z2.h[0]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x48, 0xfa, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z0.s, z1.h, z2.h[7]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x4c, 0xfa, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z0.s, z1.h, z2.h[7]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x4c, 0xff, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0xea, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z10, z7" + + - + input: + bytes: [ 0xaa, 0x82, 0xee, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z10.s, z21.h, z14.h" + + - + input: + bytes: [ 0xee, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z14, z7" + + - + input: + bytes: [ 0x4e, 0x85, 0xf5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z14.s, z10.h, z21.h" + + - + input: + bytes: [ 0xf5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z21, z7" + + - + input: + bytes: [ 0xd5, 0x41, 0xeb, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z21.s, z14.h, z3.h[2]" + + - + input: + bytes: [ 0x20, 0x80, 0xe2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z0.s, z1.h, z2.h" + + - + input: + bytes: [ 0x20, 0x84, 0xe2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z0.s, z1.h, z2.h" + + - + input: + bytes: [ 0x20, 0x40, 0xe2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z0.s, z1.h, z2.h[0]" + + - + input: + bytes: [ 0x20, 0x44, 0xe2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z0.s, z1.h, z2.h[0]" + + - + input: + bytes: [ 0x20, 0x48, 0xfa, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z0.s, z1.h, z2.h[7]" + + - + input: + bytes: [ 0x20, 0x4c, 0xfa, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z0.s, z1.h, z2.h[7]" + + - + input: + bytes: [ 0x20, 0x4c, 0xff, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0xaa, 0x82, 0xee, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z10.s, z21.h, z14.h" + + - + input: + bytes: [ 0x4e, 0x85, 0xf5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z14.s, z10.h, z21.h" + + - + input: + bytes: [ 0xd5, 0x41, 0xeb, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z21.s, z14.h, z3.h[2]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x80, 0xe2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z0.s, z1.h, z2.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x84, 0xe2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z0.s, z1.h, z2.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x40, 0xe2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z0.s, z1.h, z2.h[0]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x44, 0xe2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z0.s, z1.h, z2.h[0]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x48, 0xfa, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z0.s, z1.h, z2.h[7]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x4c, 0xfa, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z0.s, z1.h, z2.h[7]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x4c, 0xff, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0xea, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z10, z7" + + - + input: + bytes: [ 0xaa, 0x82, 0xee, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z10.s, z21.h, z14.h" + + - + input: + bytes: [ 0xee, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z14, z7" + + - + input: + bytes: [ 0x4e, 0x85, 0xf5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalt z14.s, z10.h, z21.h" + + - + input: + bytes: [ 0xf5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z21, z7" + + - + input: + bytes: [ 0xd5, 0x41, 0xeb, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ] + expected: + insns: + - + asm_text: "bfmlalb z21.s, z14.h, z3.h[2]" diff --git a/tests/MC/AArch64/SVE/bfmmla.s.yaml b/tests/MC/AArch64/SVE/bfmmla.s.yaml new file mode 100644 index 0000000000..b9c02cf58c --- /dev/null +++ b/tests/MC/AArch64/SVE/bfmmla.s.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xe4, 0x62, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmmla z0.s, z1.h, z2.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xe4, 0x62, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ] + expected: + insns: + - + asm_text: "bfmmla z0.s, z1.h, z2.h" diff --git a/tests/MC/AArch64/SVE/bic.s.yaml b/tests/MC/AArch64/SVE/bic.s.yaml new file mode 100644 index 0000000000..4629837561 --- /dev/null +++ b/tests/MC/AArch64/SVE/bic.s.yaml @@ -0,0 +1,500 @@ +test_cases: + - + input: + bytes: [ 0x25, 0x3e, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z5.b, z5.b, #0x6" + + - + input: + bytes: [ 0x37, 0x7c, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z23.h, z23.h, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z0.s, z0.s, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x83, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, #0x6" + + - + input: + bytes: [ 0xa5, 0x2e, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z5.b, z5.b, #0xf9" + + - + input: + bytes: [ 0xb7, 0x6d, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z23.h, z23.h, #0xfff9" + + - + input: + bytes: [ 0xa0, 0xeb, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z0.s, z0.s, #0xfffffff9" + + - + input: + bytes: [ 0xa0, 0xef, 0x83, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, #0xfffffffffffffff9" + + - + input: + bytes: [ 0x00, 0x30, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "bic z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0xb7, 0x31, 0xe8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "bic z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0x1f, 0x1b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "bic z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x1f, 0x5b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "bic z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x9b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "bic z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0xdb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "bic z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0xff, 0x7d, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "bic p15.b, p15/z, p15.b, p15.b" + + - + input: + bytes: [ 0x10, 0x40, 0x00, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "bic p0.b, p0/z, p0.b, p0.b" + + - + input: + bytes: [ 0x00, 0x30, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "bic z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x30, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "bic z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x30, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "bic z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x1f, 0xdb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "bic z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0xdb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "bic z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xa0, 0xef, 0x83, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, #0xfffffffffffffff9" + + - + input: + bytes: [ 0x25, 0x3e, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z5.b, z5.b, #0x6" + + - + input: + bytes: [ 0x37, 0x7c, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z23.h, z23.h, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z0.s, z0.s, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x83, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, #0x6" + + - + input: + bytes: [ 0xa5, 0x2e, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z5.b, z5.b, #0xf9" + + - + input: + bytes: [ 0xb7, 0x6d, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z23.h, z23.h, #0xfff9" + + - + input: + bytes: [ 0xa0, 0xeb, 0x80, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z0.s, z0.s, #0xfffffff9" + + - + input: + bytes: [ 0xa0, 0xef, 0x83, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, #0xfffffffffffffff9" + + - + input: + bytes: [ 0x00, 0x30, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bic z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0xb7, 0x31, 0xe8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bic z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0x1f, 0x1b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bic z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x1f, 0x5b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bic z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x9b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bic z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0xdb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bic z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0xff, 0x7d, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bic p15.b, p15/z, p15.b, p15.b" + + - + input: + bytes: [ 0x10, 0x40, 0x00, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bic p0.b, p0/z, p0.b, p0.b" + + - + input: + bytes: [ 0x00, 0x30, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bic z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x30, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bic z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x30, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bic z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x1f, 0xdb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bic z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0xdb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bic z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xa0, 0xef, 0x83, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "and z0.d, z0.d, #0xfffffffffffffff9" diff --git a/tests/MC/AArch64/SVE/bics.s.yaml b/tests/MC/AArch64/SVE/bics.s.yaml new file mode 100644 index 0000000000..747e13e78e --- /dev/null +++ b/tests/MC/AArch64/SVE/bics.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x40, 0x40, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "bics p0.b, p0/z, p0.b, p0.b" + + - + input: + bytes: [ 0xff, 0x7d, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "bics p15.b, p15/z, p15.b, p15.b" + + - + input: + bytes: [ 0x10, 0x40, 0x40, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bics p0.b, p0/z, p0.b, p0.b" + + - + input: + bytes: [ 0xff, 0x7d, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bics p15.b, p15/z, p15.b, p15.b" diff --git a/tests/MC/AArch64/SVE/brka.s.yaml b/tests/MC/AArch64/SVE/brka.s.yaml new file mode 100644 index 0000000000..a5945fac43 --- /dev/null +++ b/tests/MC/AArch64/SVE/brka.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0xf0, 0x7d, 0x10, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brka p0.b, p15/m, p15.b" + + - + input: + bytes: [ 0xe0, 0x7d, 0x10, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brka p0.b, p15/z, p15.b" + + - + input: + bytes: [ 0xf0, 0x7d, 0x10, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brka p0.b, p15/m, p15.b" + + - + input: + bytes: [ 0xe0, 0x7d, 0x10, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brka p0.b, p15/z, p15.b" diff --git a/tests/MC/AArch64/SVE/brkas.s.yaml b/tests/MC/AArch64/SVE/brkas.s.yaml new file mode 100644 index 0000000000..e6c08ffe71 --- /dev/null +++ b/tests/MC/AArch64/SVE/brkas.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x7d, 0x50, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brkas p0.b, p15/z, p15.b" + + - + input: + bytes: [ 0xe0, 0x7d, 0x50, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brkas p0.b, p15/z, p15.b" diff --git a/tests/MC/AArch64/SVE/brkb.s.yaml b/tests/MC/AArch64/SVE/brkb.s.yaml new file mode 100644 index 0000000000..1d488fc23c --- /dev/null +++ b/tests/MC/AArch64/SVE/brkb.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0xf0, 0x7d, 0x90, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brkb p0.b, p15/m, p15.b" + + - + input: + bytes: [ 0xe0, 0x7d, 0x90, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brkb p0.b, p15/z, p15.b" + + - + input: + bytes: [ 0xf0, 0x7d, 0x90, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brkb p0.b, p15/m, p15.b" + + - + input: + bytes: [ 0xe0, 0x7d, 0x90, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brkb p0.b, p15/z, p15.b" diff --git a/tests/MC/AArch64/SVE/brkbs.s.yaml b/tests/MC/AArch64/SVE/brkbs.s.yaml new file mode 100644 index 0000000000..22b47cde0a --- /dev/null +++ b/tests/MC/AArch64/SVE/brkbs.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x7d, 0xd0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brkbs p0.b, p15/z, p15.b" + + - + input: + bytes: [ 0xe0, 0x7d, 0xd0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brkbs p0.b, p15/z, p15.b" diff --git a/tests/MC/AArch64/SVE/brkn.s.yaml b/tests/MC/AArch64/SVE/brkn.s.yaml new file mode 100644 index 0000000000..49bc07d785 --- /dev/null +++ b/tests/MC/AArch64/SVE/brkn.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x7c, 0x18, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brkn p0.b, p15/z, p1.b, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0x18, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brkn p15.b, p15/z, p15.b, p15.b" + + - + input: + bytes: [ 0x20, 0x7c, 0x18, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brkn p0.b, p15/z, p1.b, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0x18, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brkn p15.b, p15/z, p15.b, p15.b" diff --git a/tests/MC/AArch64/SVE/brkns.s.yaml b/tests/MC/AArch64/SVE/brkns.s.yaml new file mode 100644 index 0000000000..7789903cdf --- /dev/null +++ b/tests/MC/AArch64/SVE/brkns.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x7c, 0x58, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brkns p0.b, p15/z, p1.b, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0x58, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brkns p15.b, p15/z, p15.b, p15.b" + + - + input: + bytes: [ 0x20, 0x7c, 0x58, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brkns p0.b, p15/z, p1.b, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0x58, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brkns p15.b, p15/z, p15.b, p15.b" diff --git a/tests/MC/AArch64/SVE/brkpa.s.yaml b/tests/MC/AArch64/SVE/brkpa.s.yaml new file mode 100644 index 0000000000..612ee4d93d --- /dev/null +++ b/tests/MC/AArch64/SVE/brkpa.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xfc, 0x02, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brkpa p0.b, p15/z, p1.b, p2.b" + + - + input: + bytes: [ 0xef, 0xfd, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brkpa p15.b, p15/z, p15.b, p15.b" + + - + input: + bytes: [ 0x20, 0xfc, 0x02, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brkpa p0.b, p15/z, p1.b, p2.b" + + - + input: + bytes: [ 0xef, 0xfd, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brkpa p15.b, p15/z, p15.b, p15.b" diff --git a/tests/MC/AArch64/SVE/brkpas.s.yaml b/tests/MC/AArch64/SVE/brkpas.s.yaml new file mode 100644 index 0000000000..6f340336a7 --- /dev/null +++ b/tests/MC/AArch64/SVE/brkpas.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xfc, 0x42, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brkpas p0.b, p15/z, p1.b, p2.b" + + - + input: + bytes: [ 0xef, 0xfd, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brkpas p15.b, p15/z, p15.b, p15.b" + + - + input: + bytes: [ 0x20, 0xfc, 0x42, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brkpas p0.b, p15/z, p1.b, p2.b" + + - + input: + bytes: [ 0xef, 0xfd, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brkpas p15.b, p15/z, p15.b, p15.b" diff --git a/tests/MC/AArch64/SVE/brkpb.s.yaml b/tests/MC/AArch64/SVE/brkpb.s.yaml new file mode 100644 index 0000000000..b7fabbcba4 --- /dev/null +++ b/tests/MC/AArch64/SVE/brkpb.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x30, 0xfc, 0x02, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brkpb p0.b, p15/z, p1.b, p2.b" + + - + input: + bytes: [ 0xff, 0xfd, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brkpb p15.b, p15/z, p15.b, p15.b" + + - + input: + bytes: [ 0x30, 0xfc, 0x02, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brkpb p0.b, p15/z, p1.b, p2.b" + + - + input: + bytes: [ 0xff, 0xfd, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brkpb p15.b, p15/z, p15.b, p15.b" diff --git a/tests/MC/AArch64/SVE/brkpbs.s.yaml b/tests/MC/AArch64/SVE/brkpbs.s.yaml new file mode 100644 index 0000000000..1b21ad23ca --- /dev/null +++ b/tests/MC/AArch64/SVE/brkpbs.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x30, 0xfc, 0x42, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brkpbs p0.b, p15/z, p1.b, p2.b" + + - + input: + bytes: [ 0xff, 0xfd, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brkpbs p15.b, p15/z, p15.b, p15.b" + + - + input: + bytes: [ 0x30, 0xfc, 0x42, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brkpbs p0.b, p15/z, p1.b, p2.b" + + - + input: + bytes: [ 0xff, 0xfd, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brkpbs p15.b, p15/z, p15.b, p15.b" diff --git a/tests/MC/AArch64/SVE/clasta.s.yaml b/tests/MC/AArch64/SVE/clasta.s.yaml new file mode 100644 index 0000000000..039ac10b0e --- /dev/null +++ b/tests/MC/AArch64/SVE/clasta.s.yaml @@ -0,0 +1,280 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xbf, 0x30, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clasta w0, p7, w0, z31.b" + + - + input: + bytes: [ 0xe0, 0xbf, 0x70, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clasta w0, p7, w0, z31.h" + + - + input: + bytes: [ 0xe0, 0xbf, 0xb0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clasta w0, p7, w0, z31.s" + + - + input: + bytes: [ 0xe0, 0xbf, 0xf0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clasta x0, p7, x0, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0x2a, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clasta b0, p7, b0, z31.b" + + - + input: + bytes: [ 0xe0, 0x9f, 0x6a, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clasta h0, p7, h0, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0xaa, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clasta s0, p7, s0, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xea, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clasta d0, p7, d0, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clasta z0.b, p7, z0.b, z31.b" + + - + input: + bytes: [ 0xe0, 0x9f, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clasta z0.h, p7, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0xa8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clasta z0.s, p7, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clasta z0.d, p7, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clasta z0.d, p7, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbf, 0x30, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clasta w0, p7, w0, z31.b" + + - + input: + bytes: [ 0xe0, 0xbf, 0x70, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clasta w0, p7, w0, z31.h" + + - + input: + bytes: [ 0xe0, 0xbf, 0xb0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clasta w0, p7, w0, z31.s" + + - + input: + bytes: [ 0xe0, 0xbf, 0xf0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clasta x0, p7, x0, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0x2a, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clasta b0, p7, b0, z31.b" + + - + input: + bytes: [ 0xe0, 0x9f, 0x6a, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clasta h0, p7, h0, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0xaa, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clasta s0, p7, s0, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xea, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clasta d0, p7, d0, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clasta z0.b, p7, z0.b, z31.b" + + - + input: + bytes: [ 0xe0, 0x9f, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clasta z0.h, p7, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0xa8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clasta z0.s, p7, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clasta z0.d, p7, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clasta z0.d, p7, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/clastb.s.yaml b/tests/MC/AArch64/SVE/clastb.s.yaml new file mode 100644 index 0000000000..43f588322a --- /dev/null +++ b/tests/MC/AArch64/SVE/clastb.s.yaml @@ -0,0 +1,280 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xbf, 0x31, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clastb w0, p7, w0, z31.b" + + - + input: + bytes: [ 0xe0, 0xbf, 0x71, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clastb w0, p7, w0, z31.h" + + - + input: + bytes: [ 0xe0, 0xbf, 0xb1, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clastb w0, p7, w0, z31.s" + + - + input: + bytes: [ 0xe0, 0xbf, 0xf1, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clastb x0, p7, x0, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0x2b, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clastb b0, p7, b0, z31.b" + + - + input: + bytes: [ 0xe0, 0x9f, 0x6b, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clastb h0, p7, h0, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0xab, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clastb s0, p7, s0, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xeb, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clastb d0, p7, d0, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0x29, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clastb z0.b, p7, z0.b, z31.b" + + - + input: + bytes: [ 0xe0, 0x9f, 0x69, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clastb z0.h, p7, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0xa9, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clastb z0.s, p7, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe9, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clastb z0.d, p7, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe9, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clastb z0.d, p7, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbf, 0x31, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clastb w0, p7, w0, z31.b" + + - + input: + bytes: [ 0xe0, 0xbf, 0x71, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clastb w0, p7, w0, z31.h" + + - + input: + bytes: [ 0xe0, 0xbf, 0xb1, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clastb w0, p7, w0, z31.s" + + - + input: + bytes: [ 0xe0, 0xbf, 0xf1, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clastb x0, p7, x0, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0x2b, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clastb b0, p7, b0, z31.b" + + - + input: + bytes: [ 0xe0, 0x9f, 0x6b, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clastb h0, p7, h0, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0xab, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clastb s0, p7, s0, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xeb, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clastb d0, p7, d0, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0x29, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clastb z0.b, p7, z0.b, z31.b" + + - + input: + bytes: [ 0xe0, 0x9f, 0x69, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clastb z0.h, p7, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0xa9, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clastb z0.s, p7, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe9, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clastb z0.d, p7, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe9, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clastb z0.d, p7, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/cls.s.yaml b/tests/MC/AArch64/SVE/cls.s.yaml new file mode 100644 index 0000000000..bb4c10d0dd --- /dev/null +++ b/tests/MC/AArch64/SVE/cls.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x18, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cls z31.b, p7/m, z31.b" + + - + input: + bytes: [ 0xff, 0xbf, 0x58, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cls z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x98, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cls z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xd8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cls z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cls z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cls z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x18, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cls z31.b, p7/m, z31.b" + + - + input: + bytes: [ 0xff, 0xbf, 0x58, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cls z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x98, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cls z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xd8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cls z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cls z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cls z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/clz.s.yaml b/tests/MC/AArch64/SVE/clz.s.yaml new file mode 100644 index 0000000000..163f8959f8 --- /dev/null +++ b/tests/MC/AArch64/SVE/clz.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x19, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clz z31.b, p7/m, z31.b" + + - + input: + bytes: [ 0xff, 0xbf, 0x59, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clz z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x99, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clz z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xd9, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clz z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd9, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clz z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd9, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "clz z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x19, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clz z31.b, p7/m, z31.b" + + - + input: + bytes: [ 0xff, 0xbf, 0x59, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clz z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x99, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clz z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xd9, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clz z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd9, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clz z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd9, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "clz z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/cmpeq.s.yaml b/tests/MC/AArch64/SVE/cmpeq.s.yaml new file mode 100644 index 0000000000..e0b8ba01d4 --- /dev/null +++ b/tests/MC/AArch64/SVE/cmpeq.s.yaml @@ -0,0 +1,300 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpeq p0.b, p0/z, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpeq p0.h, p0/z, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpeq p0.s, p0/z, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpeq p0.d, p0/z, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x20, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpeq p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x00, 0x20, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpeq p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x00, 0x20, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpeq p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x00, 0x80, 0x10, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpeq p0.b, p0/z, z0.b, #-16" + + - + input: + bytes: [ 0x00, 0x80, 0x50, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpeq p0.h, p0/z, z0.h, #-16" + + - + input: + bytes: [ 0x00, 0x80, 0x90, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpeq p0.s, p0/z, z0.s, #-16" + + - + input: + bytes: [ 0x00, 0x80, 0xd0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpeq p0.d, p0/z, z0.d, #-16" + + - + input: + bytes: [ 0x00, 0x80, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpeq p0.b, p0/z, z0.b, #15" + + - + input: + bytes: [ 0x00, 0x80, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpeq p0.h, p0/z, z0.h, #15" + + - + input: + bytes: [ 0x00, 0x80, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpeq p0.s, p0/z, z0.s, #15" + + - + input: + bytes: [ 0x00, 0x80, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpeq p0.d, p0/z, z0.d, #15" + + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpeq p0.b, p0/z, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpeq p0.h, p0/z, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpeq p0.s, p0/z, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpeq p0.d, p0/z, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x20, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpeq p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x00, 0x20, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpeq p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x00, 0x20, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpeq p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x00, 0x80, 0x10, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpeq p0.b, p0/z, z0.b, #-16" + + - + input: + bytes: [ 0x00, 0x80, 0x50, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpeq p0.h, p0/z, z0.h, #-16" + + - + input: + bytes: [ 0x00, 0x80, 0x90, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpeq p0.s, p0/z, z0.s, #-16" + + - + input: + bytes: [ 0x00, 0x80, 0xd0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpeq p0.d, p0/z, z0.d, #-16" + + - + input: + bytes: [ 0x00, 0x80, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpeq p0.b, p0/z, z0.b, #15" + + - + input: + bytes: [ 0x00, 0x80, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpeq p0.h, p0/z, z0.h, #15" + + - + input: + bytes: [ 0x00, 0x80, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpeq p0.s, p0/z, z0.s, #15" + + - + input: + bytes: [ 0x00, 0x80, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpeq p0.d, p0/z, z0.d, #15" diff --git a/tests/MC/AArch64/SVE/cmpge.s.yaml b/tests/MC/AArch64/SVE/cmpge.s.yaml new file mode 100644 index 0000000000..48ab38c297 --- /dev/null +++ b/tests/MC/AArch64/SVE/cmpge.s.yaml @@ -0,0 +1,300 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpge p0.b, p0/z, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x80, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpge p0.h, p0/z, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpge p0.s, p0/z, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpge p0.d, p0/z, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x40, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpge p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x00, 0x40, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpge p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x00, 0x40, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpge p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x00, 0x00, 0x10, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpge p0.b, p0/z, z0.b, #-16" + + - + input: + bytes: [ 0x00, 0x00, 0x50, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpge p0.h, p0/z, z0.h, #-16" + + - + input: + bytes: [ 0x00, 0x00, 0x90, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpge p0.s, p0/z, z0.s, #-16" + + - + input: + bytes: [ 0x00, 0x00, 0xd0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpge p0.d, p0/z, z0.d, #-16" + + - + input: + bytes: [ 0x00, 0x00, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpge p0.b, p0/z, z0.b, #15" + + - + input: + bytes: [ 0x00, 0x00, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpge p0.h, p0/z, z0.h, #15" + + - + input: + bytes: [ 0x00, 0x00, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpge p0.s, p0/z, z0.s, #15" + + - + input: + bytes: [ 0x00, 0x00, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpge p0.d, p0/z, z0.d, #15" + + - + input: + bytes: [ 0x00, 0x80, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpge p0.b, p0/z, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x80, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpge p0.h, p0/z, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpge p0.s, p0/z, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpge p0.d, p0/z, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x40, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpge p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x00, 0x40, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpge p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x00, 0x40, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpge p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x00, 0x00, 0x10, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpge p0.b, p0/z, z0.b, #-16" + + - + input: + bytes: [ 0x00, 0x00, 0x50, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpge p0.h, p0/z, z0.h, #-16" + + - + input: + bytes: [ 0x00, 0x00, 0x90, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpge p0.s, p0/z, z0.s, #-16" + + - + input: + bytes: [ 0x00, 0x00, 0xd0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpge p0.d, p0/z, z0.d, #-16" + + - + input: + bytes: [ 0x00, 0x00, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpge p0.b, p0/z, z0.b, #15" + + - + input: + bytes: [ 0x00, 0x00, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpge p0.h, p0/z, z0.h, #15" + + - + input: + bytes: [ 0x00, 0x00, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpge p0.s, p0/z, z0.s, #15" + + - + input: + bytes: [ 0x00, 0x00, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpge p0.d, p0/z, z0.d, #15" diff --git a/tests/MC/AArch64/SVE/cmpgt.s.yaml b/tests/MC/AArch64/SVE/cmpgt.s.yaml new file mode 100644 index 0000000000..a3dfe962f9 --- /dev/null +++ b/tests/MC/AArch64/SVE/cmpgt.s.yaml @@ -0,0 +1,300 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x80, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpgt p0.b, p0/z, z0.b, z0.b" + + - + input: + bytes: [ 0x10, 0x80, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpgt p0.h, p0/z, z0.h, z0.h" + + - + input: + bytes: [ 0x10, 0x80, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpgt p0.s, p0/z, z0.s, z0.s" + + - + input: + bytes: [ 0x10, 0x80, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpgt p0.d, p0/z, z0.d, z0.d" + + - + input: + bytes: [ 0x10, 0x40, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpgt p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x10, 0x40, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpgt p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x10, 0x40, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpgt p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x10, 0x00, 0x10, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpgt p0.b, p0/z, z0.b, #-16" + + - + input: + bytes: [ 0x10, 0x00, 0x50, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpgt p0.h, p0/z, z0.h, #-16" + + - + input: + bytes: [ 0x10, 0x00, 0x90, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpgt p0.s, p0/z, z0.s, #-16" + + - + input: + bytes: [ 0x10, 0x00, 0xd0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpgt p0.d, p0/z, z0.d, #-16" + + - + input: + bytes: [ 0x10, 0x00, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpgt p0.b, p0/z, z0.b, #15" + + - + input: + bytes: [ 0x10, 0x00, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpgt p0.h, p0/z, z0.h, #15" + + - + input: + bytes: [ 0x10, 0x00, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpgt p0.s, p0/z, z0.s, #15" + + - + input: + bytes: [ 0x10, 0x00, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpgt p0.d, p0/z, z0.d, #15" + + - + input: + bytes: [ 0x10, 0x80, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpgt p0.b, p0/z, z0.b, z0.b" + + - + input: + bytes: [ 0x10, 0x80, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpgt p0.h, p0/z, z0.h, z0.h" + + - + input: + bytes: [ 0x10, 0x80, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpgt p0.s, p0/z, z0.s, z0.s" + + - + input: + bytes: [ 0x10, 0x80, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpgt p0.d, p0/z, z0.d, z0.d" + + - + input: + bytes: [ 0x10, 0x40, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpgt p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x10, 0x40, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpgt p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x10, 0x40, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpgt p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x10, 0x00, 0x10, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpgt p0.b, p0/z, z0.b, #-16" + + - + input: + bytes: [ 0x10, 0x00, 0x50, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpgt p0.h, p0/z, z0.h, #-16" + + - + input: + bytes: [ 0x10, 0x00, 0x90, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpgt p0.s, p0/z, z0.s, #-16" + + - + input: + bytes: [ 0x10, 0x00, 0xd0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpgt p0.d, p0/z, z0.d, #-16" + + - + input: + bytes: [ 0x10, 0x00, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpgt p0.b, p0/z, z0.b, #15" + + - + input: + bytes: [ 0x10, 0x00, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpgt p0.h, p0/z, z0.h, #15" + + - + input: + bytes: [ 0x10, 0x00, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpgt p0.s, p0/z, z0.s, #15" + + - + input: + bytes: [ 0x10, 0x00, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpgt p0.d, p0/z, z0.d, #15" diff --git a/tests/MC/AArch64/SVE/cmphi.s.yaml b/tests/MC/AArch64/SVE/cmphi.s.yaml new file mode 100644 index 0000000000..7396400ac6 --- /dev/null +++ b/tests/MC/AArch64/SVE/cmphi.s.yaml @@ -0,0 +1,300 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphi p0.b, p0/z, z0.b, z0.b" + + - + input: + bytes: [ 0x10, 0x00, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphi p0.h, p0/z, z0.h, z0.h" + + - + input: + bytes: [ 0x10, 0x00, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphi p0.s, p0/z, z0.s, z0.s" + + - + input: + bytes: [ 0x10, 0x00, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphi p0.d, p0/z, z0.d, z0.d" + + - + input: + bytes: [ 0x10, 0xc0, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphi p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x10, 0xc0, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphi p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x10, 0xc0, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphi p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x10, 0x00, 0x20, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphi p0.b, p0/z, z0.b, #0" + + - + input: + bytes: [ 0x10, 0x00, 0x60, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphi p0.h, p0/z, z0.h, #0" + + - + input: + bytes: [ 0x10, 0x00, 0xa0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphi p0.s, p0/z, z0.s, #0" + + - + input: + bytes: [ 0x10, 0x00, 0xe0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphi p0.d, p0/z, z0.d, #0" + + - + input: + bytes: [ 0x10, 0xc0, 0x3f, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphi p0.b, p0/z, z0.b, #127" + + - + input: + bytes: [ 0x10, 0xc0, 0x7f, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphi p0.h, p0/z, z0.h, #127" + + - + input: + bytes: [ 0x10, 0xc0, 0xbf, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphi p0.s, p0/z, z0.s, #127" + + - + input: + bytes: [ 0x10, 0xc0, 0xff, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphi p0.d, p0/z, z0.d, #127" + + - + input: + bytes: [ 0x10, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphi p0.b, p0/z, z0.b, z0.b" + + - + input: + bytes: [ 0x10, 0x00, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphi p0.h, p0/z, z0.h, z0.h" + + - + input: + bytes: [ 0x10, 0x00, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphi p0.s, p0/z, z0.s, z0.s" + + - + input: + bytes: [ 0x10, 0x00, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphi p0.d, p0/z, z0.d, z0.d" + + - + input: + bytes: [ 0x10, 0xc0, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphi p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x10, 0xc0, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphi p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x10, 0xc0, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphi p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x10, 0x00, 0x20, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphi p0.b, p0/z, z0.b, #0" + + - + input: + bytes: [ 0x10, 0x00, 0x60, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphi p0.h, p0/z, z0.h, #0" + + - + input: + bytes: [ 0x10, 0x00, 0xa0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphi p0.s, p0/z, z0.s, #0" + + - + input: + bytes: [ 0x10, 0x00, 0xe0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphi p0.d, p0/z, z0.d, #0" + + - + input: + bytes: [ 0x10, 0xc0, 0x3f, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphi p0.b, p0/z, z0.b, #127" + + - + input: + bytes: [ 0x10, 0xc0, 0x7f, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphi p0.h, p0/z, z0.h, #127" + + - + input: + bytes: [ 0x10, 0xc0, 0xbf, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphi p0.s, p0/z, z0.s, #127" + + - + input: + bytes: [ 0x10, 0xc0, 0xff, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphi p0.d, p0/z, z0.d, #127" diff --git a/tests/MC/AArch64/SVE/cmphs.s.yaml b/tests/MC/AArch64/SVE/cmphs.s.yaml new file mode 100644 index 0000000000..ef7f66121d --- /dev/null +++ b/tests/MC/AArch64/SVE/cmphs.s.yaml @@ -0,0 +1,300 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphs p0.b, p0/z, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x00, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphs p0.h, p0/z, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphs p0.s, p0/z, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphs p0.d, p0/z, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0xc0, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphs p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x00, 0xc0, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphs p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x00, 0xc0, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphs p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x00, 0x00, 0x20, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphs p0.b, p0/z, z0.b, #0" + + - + input: + bytes: [ 0x00, 0x00, 0x60, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphs p0.h, p0/z, z0.h, #0" + + - + input: + bytes: [ 0x00, 0x00, 0xa0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphs p0.s, p0/z, z0.s, #0" + + - + input: + bytes: [ 0x00, 0x00, 0xe0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphs p0.d, p0/z, z0.d, #0" + + - + input: + bytes: [ 0x00, 0xc0, 0x3f, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphs p0.b, p0/z, z0.b, #127" + + - + input: + bytes: [ 0x00, 0xc0, 0x7f, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphs p0.h, p0/z, z0.h, #127" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphs p0.s, p0/z, z0.s, #127" + + - + input: + bytes: [ 0x00, 0xc0, 0xff, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphs p0.d, p0/z, z0.d, #127" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphs p0.b, p0/z, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x00, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphs p0.h, p0/z, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphs p0.s, p0/z, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphs p0.d, p0/z, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0xc0, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphs p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x00, 0xc0, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphs p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x00, 0xc0, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphs p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x00, 0x00, 0x20, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphs p0.b, p0/z, z0.b, #0" + + - + input: + bytes: [ 0x00, 0x00, 0x60, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphs p0.h, p0/z, z0.h, #0" + + - + input: + bytes: [ 0x00, 0x00, 0xa0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphs p0.s, p0/z, z0.s, #0" + + - + input: + bytes: [ 0x00, 0x00, 0xe0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphs p0.d, p0/z, z0.d, #0" + + - + input: + bytes: [ 0x00, 0xc0, 0x3f, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphs p0.b, p0/z, z0.b, #127" + + - + input: + bytes: [ 0x00, 0xc0, 0x7f, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphs p0.h, p0/z, z0.h, #127" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphs p0.s, p0/z, z0.s, #127" + + - + input: + bytes: [ 0x00, 0xc0, 0xff, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphs p0.d, p0/z, z0.d, #127" diff --git a/tests/MC/AArch64/SVE/cmple.s.yaml b/tests/MC/AArch64/SVE/cmple.s.yaml new file mode 100644 index 0000000000..6bca879edb --- /dev/null +++ b/tests/MC/AArch64/SVE/cmple.s.yaml @@ -0,0 +1,300 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpge p0.b, p0/z, z1.b, z0.b" + + - + input: + bytes: [ 0x20, 0x80, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpge p0.h, p0/z, z1.h, z0.h" + + - + input: + bytes: [ 0x20, 0x80, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpge p0.s, p0/z, z1.s, z0.s" + + - + input: + bytes: [ 0x20, 0x80, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpge p0.d, p0/z, z1.d, z0.d" + + - + input: + bytes: [ 0x10, 0x60, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmple p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x10, 0x60, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmple p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x10, 0x60, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmple p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x10, 0x20, 0x10, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmple p0.b, p0/z, z0.b, #-16" + + - + input: + bytes: [ 0x10, 0x20, 0x50, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmple p0.h, p0/z, z0.h, #-16" + + - + input: + bytes: [ 0x10, 0x20, 0x90, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmple p0.s, p0/z, z0.s, #-16" + + - + input: + bytes: [ 0x10, 0x20, 0xd0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmple p0.d, p0/z, z0.d, #-16" + + - + input: + bytes: [ 0x10, 0x20, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmple p0.b, p0/z, z0.b, #15" + + - + input: + bytes: [ 0x10, 0x20, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmple p0.h, p0/z, z0.h, #15" + + - + input: + bytes: [ 0x10, 0x20, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmple p0.s, p0/z, z0.s, #15" + + - + input: + bytes: [ 0x10, 0x20, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmple p0.d, p0/z, z0.d, #15" + + - + input: + bytes: [ 0x20, 0x80, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpge p0.b, p0/z, z1.b, z0.b" + + - + input: + bytes: [ 0x20, 0x80, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpge p0.h, p0/z, z1.h, z0.h" + + - + input: + bytes: [ 0x20, 0x80, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpge p0.s, p0/z, z1.s, z0.s" + + - + input: + bytes: [ 0x20, 0x80, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpge p0.d, p0/z, z1.d, z0.d" + + - + input: + bytes: [ 0x10, 0x60, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmple p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x10, 0x60, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmple p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x10, 0x60, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmple p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x10, 0x20, 0x10, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmple p0.b, p0/z, z0.b, #-16" + + - + input: + bytes: [ 0x10, 0x20, 0x50, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmple p0.h, p0/z, z0.h, #-16" + + - + input: + bytes: [ 0x10, 0x20, 0x90, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmple p0.s, p0/z, z0.s, #-16" + + - + input: + bytes: [ 0x10, 0x20, 0xd0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmple p0.d, p0/z, z0.d, #-16" + + - + input: + bytes: [ 0x10, 0x20, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmple p0.b, p0/z, z0.b, #15" + + - + input: + bytes: [ 0x10, 0x20, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmple p0.h, p0/z, z0.h, #15" + + - + input: + bytes: [ 0x10, 0x20, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmple p0.s, p0/z, z0.s, #15" + + - + input: + bytes: [ 0x10, 0x20, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmple p0.d, p0/z, z0.d, #15" diff --git a/tests/MC/AArch64/SVE/cmplo.s.yaml b/tests/MC/AArch64/SVE/cmplo.s.yaml new file mode 100644 index 0000000000..b928dfa714 --- /dev/null +++ b/tests/MC/AArch64/SVE/cmplo.s.yaml @@ -0,0 +1,300 @@ +test_cases: + - + input: + bytes: [ 0x30, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphi p0.b, p0/z, z1.b, z0.b" + + - + input: + bytes: [ 0x30, 0x00, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphi p0.h, p0/z, z1.h, z0.h" + + - + input: + bytes: [ 0x30, 0x00, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphi p0.s, p0/z, z1.s, z0.s" + + - + input: + bytes: [ 0x30, 0x00, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphi p0.d, p0/z, z1.d, z0.d" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplo p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplo p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x00, 0xe0, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplo p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x00, 0x20, 0x20, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplo p0.b, p0/z, z0.b, #0" + + - + input: + bytes: [ 0x00, 0x20, 0x60, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplo p0.h, p0/z, z0.h, #0" + + - + input: + bytes: [ 0x00, 0x20, 0xa0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplo p0.s, p0/z, z0.s, #0" + + - + input: + bytes: [ 0x00, 0x20, 0xe0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplo p0.d, p0/z, z0.d, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0x3f, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplo p0.b, p0/z, z0.b, #127" + + - + input: + bytes: [ 0x00, 0xe0, 0x7f, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplo p0.h, p0/z, z0.h, #127" + + - + input: + bytes: [ 0x00, 0xe0, 0xbf, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplo p0.s, p0/z, z0.s, #127" + + - + input: + bytes: [ 0x00, 0xe0, 0xff, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplo p0.d, p0/z, z0.d, #127" + + - + input: + bytes: [ 0x30, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphi p0.b, p0/z, z1.b, z0.b" + + - + input: + bytes: [ 0x30, 0x00, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphi p0.h, p0/z, z1.h, z0.h" + + - + input: + bytes: [ 0x30, 0x00, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphi p0.s, p0/z, z1.s, z0.s" + + - + input: + bytes: [ 0x30, 0x00, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphi p0.d, p0/z, z1.d, z0.d" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplo p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplo p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x00, 0xe0, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplo p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x00, 0x20, 0x20, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplo p0.b, p0/z, z0.b, #0" + + - + input: + bytes: [ 0x00, 0x20, 0x60, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplo p0.h, p0/z, z0.h, #0" + + - + input: + bytes: [ 0x00, 0x20, 0xa0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplo p0.s, p0/z, z0.s, #0" + + - + input: + bytes: [ 0x00, 0x20, 0xe0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplo p0.d, p0/z, z0.d, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0x3f, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplo p0.b, p0/z, z0.b, #127" + + - + input: + bytes: [ 0x00, 0xe0, 0x7f, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplo p0.h, p0/z, z0.h, #127" + + - + input: + bytes: [ 0x00, 0xe0, 0xbf, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplo p0.s, p0/z, z0.s, #127" + + - + input: + bytes: [ 0x00, 0xe0, 0xff, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplo p0.d, p0/z, z0.d, #127" diff --git a/tests/MC/AArch64/SVE/cmpls.s.yaml b/tests/MC/AArch64/SVE/cmpls.s.yaml new file mode 100644 index 0000000000..ef0d933c97 --- /dev/null +++ b/tests/MC/AArch64/SVE/cmpls.s.yaml @@ -0,0 +1,300 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphs p0.b, p0/z, z1.b, z0.b" + + - + input: + bytes: [ 0x20, 0x00, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphs p0.h, p0/z, z1.h, z0.h" + + - + input: + bytes: [ 0x20, 0x00, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphs p0.s, p0/z, z1.s, z0.s" + + - + input: + bytes: [ 0x20, 0x00, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmphs p0.d, p0/z, z1.d, z0.d" + + - + input: + bytes: [ 0x10, 0xe0, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpls p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x10, 0xe0, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpls p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x10, 0xe0, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpls p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x10, 0x20, 0x20, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpls p0.b, p0/z, z0.b, #0" + + - + input: + bytes: [ 0x10, 0x20, 0x60, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpls p0.h, p0/z, z0.h, #0" + + - + input: + bytes: [ 0x10, 0x20, 0xa0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpls p0.s, p0/z, z0.s, #0" + + - + input: + bytes: [ 0x10, 0x20, 0xe0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpls p0.d, p0/z, z0.d, #0" + + - + input: + bytes: [ 0x10, 0xe0, 0x3f, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpls p0.b, p0/z, z0.b, #127" + + - + input: + bytes: [ 0x10, 0xe0, 0x7f, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpls p0.h, p0/z, z0.h, #127" + + - + input: + bytes: [ 0x10, 0xe0, 0xbf, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpls p0.s, p0/z, z0.s, #127" + + - + input: + bytes: [ 0x10, 0xe0, 0xff, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpls p0.d, p0/z, z0.d, #127" + + - + input: + bytes: [ 0x20, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphs p0.b, p0/z, z1.b, z0.b" + + - + input: + bytes: [ 0x20, 0x00, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphs p0.h, p0/z, z1.h, z0.h" + + - + input: + bytes: [ 0x20, 0x00, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphs p0.s, p0/z, z1.s, z0.s" + + - + input: + bytes: [ 0x20, 0x00, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmphs p0.d, p0/z, z1.d, z0.d" + + - + input: + bytes: [ 0x10, 0xe0, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpls p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x10, 0xe0, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpls p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x10, 0xe0, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpls p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x10, 0x20, 0x20, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpls p0.b, p0/z, z0.b, #0" + + - + input: + bytes: [ 0x10, 0x20, 0x60, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpls p0.h, p0/z, z0.h, #0" + + - + input: + bytes: [ 0x10, 0x20, 0xa0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpls p0.s, p0/z, z0.s, #0" + + - + input: + bytes: [ 0x10, 0x20, 0xe0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpls p0.d, p0/z, z0.d, #0" + + - + input: + bytes: [ 0x10, 0xe0, 0x3f, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpls p0.b, p0/z, z0.b, #127" + + - + input: + bytes: [ 0x10, 0xe0, 0x7f, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpls p0.h, p0/z, z0.h, #127" + + - + input: + bytes: [ 0x10, 0xe0, 0xbf, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpls p0.s, p0/z, z0.s, #127" + + - + input: + bytes: [ 0x10, 0xe0, 0xff, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpls p0.d, p0/z, z0.d, #127" diff --git a/tests/MC/AArch64/SVE/cmplt.s.yaml b/tests/MC/AArch64/SVE/cmplt.s.yaml new file mode 100644 index 0000000000..40a15b06bb --- /dev/null +++ b/tests/MC/AArch64/SVE/cmplt.s.yaml @@ -0,0 +1,300 @@ +test_cases: + - + input: + bytes: [ 0x30, 0x80, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpgt p0.b, p0/z, z1.b, z0.b" + + - + input: + bytes: [ 0x30, 0x80, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpgt p0.h, p0/z, z1.h, z0.h" + + - + input: + bytes: [ 0x30, 0x80, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpgt p0.s, p0/z, z1.s, z0.s" + + - + input: + bytes: [ 0x30, 0x80, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpgt p0.d, p0/z, z1.d, z0.d" + + - + input: + bytes: [ 0x00, 0x60, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplt p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x00, 0x60, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplt p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x00, 0x60, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplt p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x00, 0x20, 0x10, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplt p0.b, p0/z, z0.b, #-16" + + - + input: + bytes: [ 0x00, 0x20, 0x50, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplt p0.h, p0/z, z0.h, #-16" + + - + input: + bytes: [ 0x00, 0x20, 0x90, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplt p0.s, p0/z, z0.s, #-16" + + - + input: + bytes: [ 0x00, 0x20, 0xd0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplt p0.d, p0/z, z0.d, #-16" + + - + input: + bytes: [ 0x00, 0x20, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplt p0.b, p0/z, z0.b, #15" + + - + input: + bytes: [ 0x00, 0x20, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplt p0.h, p0/z, z0.h, #15" + + - + input: + bytes: [ 0x00, 0x20, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplt p0.s, p0/z, z0.s, #15" + + - + input: + bytes: [ 0x00, 0x20, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmplt p0.d, p0/z, z0.d, #15" + + - + input: + bytes: [ 0x30, 0x80, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpgt p0.b, p0/z, z1.b, z0.b" + + - + input: + bytes: [ 0x30, 0x80, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpgt p0.h, p0/z, z1.h, z0.h" + + - + input: + bytes: [ 0x30, 0x80, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpgt p0.s, p0/z, z1.s, z0.s" + + - + input: + bytes: [ 0x30, 0x80, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpgt p0.d, p0/z, z1.d, z0.d" + + - + input: + bytes: [ 0x00, 0x60, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplt p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x00, 0x60, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplt p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x00, 0x60, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplt p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x00, 0x20, 0x10, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplt p0.b, p0/z, z0.b, #-16" + + - + input: + bytes: [ 0x00, 0x20, 0x50, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplt p0.h, p0/z, z0.h, #-16" + + - + input: + bytes: [ 0x00, 0x20, 0x90, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplt p0.s, p0/z, z0.s, #-16" + + - + input: + bytes: [ 0x00, 0x20, 0xd0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplt p0.d, p0/z, z0.d, #-16" + + - + input: + bytes: [ 0x00, 0x20, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplt p0.b, p0/z, z0.b, #15" + + - + input: + bytes: [ 0x00, 0x20, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplt p0.h, p0/z, z0.h, #15" + + - + input: + bytes: [ 0x00, 0x20, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplt p0.s, p0/z, z0.s, #15" + + - + input: + bytes: [ 0x00, 0x20, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmplt p0.d, p0/z, z0.d, #15" diff --git a/tests/MC/AArch64/SVE/cmpne.s.yaml b/tests/MC/AArch64/SVE/cmpne.s.yaml new file mode 100644 index 0000000000..0ec9f97832 --- /dev/null +++ b/tests/MC/AArch64/SVE/cmpne.s.yaml @@ -0,0 +1,300 @@ +test_cases: + - + input: + bytes: [ 0x10, 0xa0, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpne p0.b, p0/z, z0.b, z0.b" + + - + input: + bytes: [ 0x10, 0xa0, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpne p0.h, p0/z, z0.h, z0.h" + + - + input: + bytes: [ 0x10, 0xa0, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpne p0.s, p0/z, z0.s, z0.s" + + - + input: + bytes: [ 0x10, 0xa0, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpne p0.d, p0/z, z0.d, z0.d" + + - + input: + bytes: [ 0x10, 0x20, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpne p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x10, 0x20, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpne p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x10, 0x20, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpne p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x10, 0x80, 0x10, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpne p0.b, p0/z, z0.b, #-16" + + - + input: + bytes: [ 0x10, 0x80, 0x50, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpne p0.h, p0/z, z0.h, #-16" + + - + input: + bytes: [ 0x10, 0x80, 0x90, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpne p0.s, p0/z, z0.s, #-16" + + - + input: + bytes: [ 0x10, 0x80, 0xd0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpne p0.d, p0/z, z0.d, #-16" + + - + input: + bytes: [ 0x10, 0x80, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpne p0.b, p0/z, z0.b, #15" + + - + input: + bytes: [ 0x10, 0x80, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpne p0.h, p0/z, z0.h, #15" + + - + input: + bytes: [ 0x10, 0x80, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpne p0.s, p0/z, z0.s, #15" + + - + input: + bytes: [ 0x10, 0x80, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cmpne p0.d, p0/z, z0.d, #15" + + - + input: + bytes: [ 0x10, 0xa0, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpne p0.b, p0/z, z0.b, z0.b" + + - + input: + bytes: [ 0x10, 0xa0, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpne p0.h, p0/z, z0.h, z0.h" + + - + input: + bytes: [ 0x10, 0xa0, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpne p0.s, p0/z, z0.s, z0.s" + + - + input: + bytes: [ 0x10, 0xa0, 0xc0, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpne p0.d, p0/z, z0.d, z0.d" + + - + input: + bytes: [ 0x10, 0x20, 0x00, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpne p0.b, p0/z, z0.b, z0.d" + + - + input: + bytes: [ 0x10, 0x20, 0x40, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpne p0.h, p0/z, z0.h, z0.d" + + - + input: + bytes: [ 0x10, 0x20, 0x80, 0x24 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpne p0.s, p0/z, z0.s, z0.d" + + - + input: + bytes: [ 0x10, 0x80, 0x10, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpne p0.b, p0/z, z0.b, #-16" + + - + input: + bytes: [ 0x10, 0x80, 0x50, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpne p0.h, p0/z, z0.h, #-16" + + - + input: + bytes: [ 0x10, 0x80, 0x90, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpne p0.s, p0/z, z0.s, #-16" + + - + input: + bytes: [ 0x10, 0x80, 0xd0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpne p0.d, p0/z, z0.d, #-16" + + - + input: + bytes: [ 0x10, 0x80, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpne p0.b, p0/z, z0.b, #15" + + - + input: + bytes: [ 0x10, 0x80, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpne p0.h, p0/z, z0.h, #15" + + - + input: + bytes: [ 0x10, 0x80, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpne p0.s, p0/z, z0.s, #15" + + - + input: + bytes: [ 0x10, 0x80, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmpne p0.d, p0/z, z0.d, #15" diff --git a/tests/MC/AArch64/SVE/cnot.s.yaml b/tests/MC/AArch64/SVE/cnot.s.yaml new file mode 100644 index 0000000000..bbce786429 --- /dev/null +++ b/tests/MC/AArch64/SVE/cnot.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x1b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cnot z31.b, p7/m, z31.b" + + - + input: + bytes: [ 0xff, 0xbf, 0x5b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cnot z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x9b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cnot z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xdb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cnot z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xdb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cnot z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xdb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cnot z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x1b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cnot z31.b, p7/m, z31.b" + + - + input: + bytes: [ 0xff, 0xbf, 0x5b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cnot z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x9b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cnot z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xdb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cnot z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xdb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cnot z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xdb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cnot z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/cnt.s.yaml b/tests/MC/AArch64/SVE/cnt.s.yaml new file mode 100644 index 0000000000..f602570e3e --- /dev/null +++ b/tests/MC/AArch64/SVE/cnt.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x1a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cnt z31.b, p7/m, z31.b" + + - + input: + bytes: [ 0xff, 0xbf, 0x5a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cnt z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x9a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cnt z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xda, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cnt z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xda, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cnt z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xda, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cnt z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x1a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cnt z31.b, p7/m, z31.b" + + - + input: + bytes: [ 0xff, 0xbf, 0x5a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cnt z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x9a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cnt z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xda, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cnt z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xda, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cnt z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xda, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cnt z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/cntb.s.yaml b/tests/MC/AArch64/SVE/cntb.s.yaml new file mode 100644 index 0000000000..89c2f042fd --- /dev/null +++ b/tests/MC/AArch64/SVE/cntb.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xe3, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntb x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntb x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntb x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntb x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntb x0, pow2" + + - + input: + bytes: [ 0x80, 0xe3, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntb x0, #28" + + - + input: + bytes: [ 0xe0, 0xe3, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntb x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntb x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntb x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntb x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntb x0, pow2" + + - + input: + bytes: [ 0x80, 0xe3, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntb x0, #28" diff --git a/tests/MC/AArch64/SVE/cntd.s.yaml b/tests/MC/AArch64/SVE/cntd.s.yaml new file mode 100644 index 0000000000..81897e9d03 --- /dev/null +++ b/tests/MC/AArch64/SVE/cntd.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xe3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntd x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntd x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntd x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntd x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe0, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntd x0, pow2" + + - + input: + bytes: [ 0x80, 0xe3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntd x0, #28" + + - + input: + bytes: [ 0xe0, 0xe3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntd x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntd x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntd x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntd x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe0, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntd x0, pow2" + + - + input: + bytes: [ 0x80, 0xe3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntd x0, #28" diff --git a/tests/MC/AArch64/SVE/cnth.s.yaml b/tests/MC/AArch64/SVE/cnth.s.yaml new file mode 100644 index 0000000000..4c33cde5e7 --- /dev/null +++ b/tests/MC/AArch64/SVE/cnth.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xe3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cnth x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cnth x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cnth x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cnth x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cnth x0, pow2" + + - + input: + bytes: [ 0x80, 0xe3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cnth x0, #28" + + - + input: + bytes: [ 0xe0, 0xe3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cnth x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cnth x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cnth x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cnth x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cnth x0, pow2" + + - + input: + bytes: [ 0x80, 0xe3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cnth x0, #28" diff --git a/tests/MC/AArch64/SVE/cntp.s.yaml b/tests/MC/AArch64/SVE/cntp.s.yaml new file mode 100644 index 0000000000..b975138bd0 --- /dev/null +++ b/tests/MC/AArch64/SVE/cntp.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xbc, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntp x0, p15, p0.b" + + - + input: + bytes: [ 0x00, 0xbc, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntp x0, p15, p0.h" + + - + input: + bytes: [ 0x00, 0xbc, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntp x0, p15, p0.s" + + - + input: + bytes: [ 0x00, 0xbc, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntp x0, p15, p0.d" + + - + input: + bytes: [ 0x00, 0xbc, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntp x0, p15, p0.b" + + - + input: + bytes: [ 0x00, 0xbc, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntp x0, p15, p0.h" + + - + input: + bytes: [ 0x00, 0xbc, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntp x0, p15, p0.s" + + - + input: + bytes: [ 0x00, 0xbc, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntp x0, p15, p0.d" diff --git a/tests/MC/AArch64/SVE/cntw.s.yaml b/tests/MC/AArch64/SVE/cntw.s.yaml new file mode 100644 index 0000000000..0121bebf0f --- /dev/null +++ b/tests/MC/AArch64/SVE/cntw.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xe3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntw x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntw x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntw x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntw x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe0, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntw x0, pow2" + + - + input: + bytes: [ 0x80, 0xe3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "cntw x0, #28" + + - + input: + bytes: [ 0xe0, 0xe3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntw x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntw x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntw x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntw x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe0, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntw x0, pow2" + + - + input: + bytes: [ 0x80, 0xe3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cntw x0, #28" diff --git a/tests/MC/AArch64/SVE/compact.s.yaml b/tests/MC/AArch64/SVE/compact.s.yaml new file mode 100644 index 0000000000..4940661a1b --- /dev/null +++ b/tests/MC/AArch64/SVE/compact.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x9f, 0xa1, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "compact z31.s, p7, z31.s" + + - + input: + bytes: [ 0xff, 0x9f, 0xe1, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "compact z31.d, p7, z31.d" diff --git a/tests/MC/AArch64/SVE/cpy.s.yaml b/tests/MC/AArch64/SVE/cpy.s.yaml new file mode 100644 index 0000000000..4564c697d8 --- /dev/null +++ b/tests/MC/AArch64/SVE/cpy.s.yaml @@ -0,0 +1,1180 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.b, p0/m, w0" + + - + input: + bytes: [ 0x00, 0xa0, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/m, w0" + + - + input: + bytes: [ 0x00, 0xa0, 0xa8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.s, p0/m, w0" + + - + input: + bytes: [ 0x00, 0xa0, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.d, p0/m, x0" + + - + input: + bytes: [ 0xff, 0xbf, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.b, p7/m, wsp" + + - + input: + bytes: [ 0xff, 0xbf, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.h, p7/m, wsp" + + - + input: + bytes: [ 0xff, 0xbf, 0xa8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.s, p7/m, wsp" + + - + input: + bytes: [ 0xff, 0xbf, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, sp" + + - + input: + bytes: [ 0x00, 0x80, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.b, p0/m, b0" + + - + input: + bytes: [ 0xff, 0x9f, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.b, p7/m, b31" + + - + input: + bytes: [ 0x00, 0x80, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/m, h0" + + - + input: + bytes: [ 0xff, 0x9f, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.h, p7/m, h31" + + - + input: + bytes: [ 0x00, 0x80, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.s, p0/m, s0" + + - + input: + bytes: [ 0xff, 0x9f, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.s, p7/m, s31" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.d, p0/m, d0" + + - + input: + bytes: [ 0xff, 0x9f, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, d31" + + - + input: + bytes: [ 0x05, 0x10, 0x10, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z5.b, p0/z, #-128" + + - + input: + bytes: [ 0xe5, 0x0f, 0x10, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z5.b, p0/z, #127" + + - + input: + bytes: [ 0xe5, 0x1f, 0x10, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z5.b, p0/z, #-1" + + - + input: + bytes: [ 0x15, 0x10, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #-128" + + - + input: + bytes: [ 0x15, 0x30, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #-32768" + + - + input: + bytes: [ 0x15, 0x30, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #-32768" + + - + input: + bytes: [ 0xf5, 0x0f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #127" + + - + input: + bytes: [ 0xf5, 0x2f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #32512" + + - + input: + bytes: [ 0xf5, 0x2f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #32512" + + - + input: + bytes: [ 0x15, 0x10, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #-128" + + - + input: + bytes: [ 0x15, 0x30, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #-32768" + + - + input: + bytes: [ 0x15, 0x30, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #-32768" + + - + input: + bytes: [ 0xf5, 0x0f, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #127" + + - + input: + bytes: [ 0xf5, 0x2f, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #32512" + + - + input: + bytes: [ 0xf5, 0x2f, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #32512" + + - + input: + bytes: [ 0x15, 0x10, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #-128" + + - + input: + bytes: [ 0x15, 0x30, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #-32768" + + - + input: + bytes: [ 0x15, 0x30, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #-32768" + + - + input: + bytes: [ 0xf5, 0x0f, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #127" + + - + input: + bytes: [ 0xf5, 0x2f, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #32512" + + - + input: + bytes: [ 0xf5, 0x2f, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #32512" + + - + input: + bytes: [ 0xe0, 0x0f, 0x10, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.b, p0/z, #127" + + - + input: + bytes: [ 0xe0, 0x2f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/z, #32512" + + - + input: + bytes: [ 0xe0, 0x2f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/z, #32512" + + - + input: + bytes: [ 0x05, 0x50, 0x1f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z5.b, p15/m, #-128" + + - + input: + bytes: [ 0x15, 0x50, 0x5f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, p15/m, #-128" + + - + input: + bytes: [ 0x15, 0x70, 0x5f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, p15/m, #-32768" + + - + input: + bytes: [ 0x15, 0x50, 0x9f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, p15/m, #-128" + + - + input: + bytes: [ 0x15, 0x70, 0x9f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, p15/m, #-32768" + + - + input: + bytes: [ 0x15, 0x50, 0xdf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p15/m, #-128" + + - + input: + bytes: [ 0x15, 0x70, 0xdf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p15/m, #-32768" + + - + input: + bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p7/z, z6.d" + + - + input: + bytes: [ 0xff, 0xbf, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, sp" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xbf, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, sp" + + - + input: + bytes: [ 0x95, 0x3f, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z21.d, p7/z, z28.d" + + - + input: + bytes: [ 0x15, 0x70, 0xd7, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p7/m, #-32768" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x15, 0x70, 0xdf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p15/m, #-32768" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x9f, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z4.d, p7/m, d31" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x9f, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z4.d, p7/m, d31" + + - + input: + bytes: [ 0x00, 0xa0, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, p0/m, w0" + + - + input: + bytes: [ 0x00, 0xa0, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/m, w0" + + - + input: + bytes: [ 0x00, 0xa0, 0xa8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, p0/m, w0" + + - + input: + bytes: [ 0x00, 0xa0, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, p0/m, x0" + + - + input: + bytes: [ 0xff, 0xbf, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.b, p7/m, wsp" + + - + input: + bytes: [ 0xff, 0xbf, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.h, p7/m, wsp" + + - + input: + bytes: [ 0xff, 0xbf, 0xa8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.s, p7/m, wsp" + + - + input: + bytes: [ 0xff, 0xbf, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, sp" + + - + input: + bytes: [ 0x00, 0x80, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, p0/m, b0" + + - + input: + bytes: [ 0xff, 0x9f, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.b, p7/m, b31" + + - + input: + bytes: [ 0x00, 0x80, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/m, h0" + + - + input: + bytes: [ 0xff, 0x9f, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.h, p7/m, h31" + + - + input: + bytes: [ 0x00, 0x80, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, p0/m, s0" + + - + input: + bytes: [ 0xff, 0x9f, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.s, p7/m, s31" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, p0/m, d0" + + - + input: + bytes: [ 0xff, 0x9f, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, d31" + + - + input: + bytes: [ 0x05, 0x10, 0x10, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.b, p0/z, #-128" + + - + input: + bytes: [ 0xe5, 0x0f, 0x10, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.b, p0/z, #127" + + - + input: + bytes: [ 0xe5, 0x1f, 0x10, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.b, p0/z, #-1" + + - + input: + bytes: [ 0x15, 0x10, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #-128" + + - + input: + bytes: [ 0x15, 0x30, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #-32768" + + - + input: + bytes: [ 0x15, 0x30, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #-32768" + + - + input: + bytes: [ 0xf5, 0x0f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #127" + + - + input: + bytes: [ 0xf5, 0x2f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #32512" + + - + input: + bytes: [ 0xf5, 0x2f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #32512" + + - + input: + bytes: [ 0x15, 0x10, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #-128" + + - + input: + bytes: [ 0x15, 0x30, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #-32768" + + - + input: + bytes: [ 0x15, 0x30, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #-32768" + + - + input: + bytes: [ 0xf5, 0x0f, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #127" + + - + input: + bytes: [ 0xf5, 0x2f, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #32512" + + - + input: + bytes: [ 0xf5, 0x2f, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #32512" + + - + input: + bytes: [ 0x15, 0x10, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #-128" + + - + input: + bytes: [ 0x15, 0x30, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #-32768" + + - + input: + bytes: [ 0x15, 0x30, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #-32768" + + - + input: + bytes: [ 0xf5, 0x0f, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #127" + + - + input: + bytes: [ 0xf5, 0x2f, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #32512" + + - + input: + bytes: [ 0xf5, 0x2f, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #32512" + + - + input: + bytes: [ 0xe0, 0x0f, 0x10, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, p0/z, #127" + + - + input: + bytes: [ 0xe0, 0x2f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/z, #32512" + + - + input: + bytes: [ 0xe0, 0x2f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/z, #32512" + + - + input: + bytes: [ 0x05, 0x50, 0x1f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.b, p15/m, #-128" + + - + input: + bytes: [ 0x15, 0x50, 0x5f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p15/m, #-128" + + - + input: + bytes: [ 0x15, 0x70, 0x5f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p15/m, #-32768" + + - + input: + bytes: [ 0x15, 0x50, 0x9f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p15/m, #-128" + + - + input: + bytes: [ 0x15, 0x70, 0x9f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p15/m, #-32768" + + - + input: + bytes: [ 0x15, 0x50, 0xdf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p15/m, #-128" + + - + input: + bytes: [ 0x15, 0x70, 0xdf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p15/m, #-32768" + + - + input: + bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p7/z, z6.d" + + - + input: + bytes: [ 0xff, 0xbf, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, sp" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xbf, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, sp" + + - + input: + bytes: [ 0x95, 0x3f, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21.d, p7/z, z28.d" + + - + input: + bytes: [ 0x15, 0x70, 0xd7, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p7/m, #-32768" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x15, 0x70, 0xdf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p15/m, #-32768" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x9f, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z4.d, p7/m, d31" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x9f, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z4.d, p7/m, d31" diff --git a/tests/MC/AArch64/SVE/ctermeq.s.yaml b/tests/MC/AArch64/SVE/ctermeq.s.yaml new file mode 100644 index 0000000000..bae5b91a52 --- /dev/null +++ b/tests/MC/AArch64/SVE/ctermeq.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xc0, 0x23, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ctermeq w30, wzr" + + - + input: + bytes: [ 0xe0, 0x23, 0xbe, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ctermeq wzr, w30" + + - + input: + bytes: [ 0xc0, 0x23, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ctermeq x30, xzr" + + - + input: + bytes: [ 0xe0, 0x23, 0xfe, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ctermeq xzr, x30" + + - + input: + bytes: [ 0xc0, 0x23, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ctermeq w30, wzr" + + - + input: + bytes: [ 0xe0, 0x23, 0xbe, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ctermeq wzr, w30" + + - + input: + bytes: [ 0xc0, 0x23, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ctermeq x30, xzr" + + - + input: + bytes: [ 0xe0, 0x23, 0xfe, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ctermeq xzr, x30" diff --git a/tests/MC/AArch64/SVE/ctermne.s.yaml b/tests/MC/AArch64/SVE/ctermne.s.yaml new file mode 100644 index 0000000000..845f178a41 --- /dev/null +++ b/tests/MC/AArch64/SVE/ctermne.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xd0, 0x23, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ctermne w30, wzr" + + - + input: + bytes: [ 0xf0, 0x23, 0xbe, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ctermne wzr, w30" + + - + input: + bytes: [ 0xd0, 0x23, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ctermne x30, xzr" + + - + input: + bytes: [ 0xf0, 0x23, 0xfe, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ctermne xzr, x30" + + - + input: + bytes: [ 0xd0, 0x23, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ctermne w30, wzr" + + - + input: + bytes: [ 0xf0, 0x23, 0xbe, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ctermne wzr, w30" + + - + input: + bytes: [ 0xd0, 0x23, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ctermne x30, xzr" + + - + input: + bytes: [ 0xf0, 0x23, 0xfe, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ctermne xzr, x30" diff --git a/tests/MC/AArch64/SVE/decb.s.yaml b/tests/MC/AArch64/SVE/decb.s.yaml new file mode 100644 index 0000000000..df9ede72d5 --- /dev/null +++ b/tests/MC/AArch64/SVE/decb.s.yaml @@ -0,0 +1,400 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xe7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0, pow2" + + - + input: + bytes: [ 0x20, 0xe4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0, vl1" + + - + input: + bytes: [ 0x40, 0xe4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0, vl2" + + - + input: + bytes: [ 0x60, 0xe4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0, vl3" + + - + input: + bytes: [ 0x80, 0xe4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0, vl4" + + - + input: + bytes: [ 0xa0, 0xe4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0, vl5" + + - + input: + bytes: [ 0xc0, 0xe4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0, vl6" + + - + input: + bytes: [ 0xe0, 0xe4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0, vl7" + + - + input: + bytes: [ 0x00, 0xe5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0, vl8" + + - + input: + bytes: [ 0x20, 0xe5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0, vl16" + + - + input: + bytes: [ 0x40, 0xe5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0, vl32" + + - + input: + bytes: [ 0x60, 0xe5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0, vl64" + + - + input: + bytes: [ 0x80, 0xe5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0, vl128" + + - + input: + bytes: [ 0xa0, 0xe5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0, vl256" + + - + input: + bytes: [ 0xc0, 0xe5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0, #14" + + - + input: + bytes: [ 0x80, 0xe7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decb x0, #28" + + - + input: + bytes: [ 0xe0, 0xe7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0, pow2" + + - + input: + bytes: [ 0x20, 0xe4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0, vl1" + + - + input: + bytes: [ 0x40, 0xe4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0, vl2" + + - + input: + bytes: [ 0x60, 0xe4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0, vl3" + + - + input: + bytes: [ 0x80, 0xe4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0, vl4" + + - + input: + bytes: [ 0xa0, 0xe4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0, vl5" + + - + input: + bytes: [ 0xc0, 0xe4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0, vl6" + + - + input: + bytes: [ 0xe0, 0xe4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0, vl7" + + - + input: + bytes: [ 0x00, 0xe5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0, vl8" + + - + input: + bytes: [ 0x20, 0xe5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0, vl16" + + - + input: + bytes: [ 0x40, 0xe5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0, vl32" + + - + input: + bytes: [ 0x60, 0xe5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0, vl64" + + - + input: + bytes: [ 0x80, 0xe5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0, vl128" + + - + input: + bytes: [ 0xa0, 0xe5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0, vl256" + + - + input: + bytes: [ 0xc0, 0xe5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0, #14" + + - + input: + bytes: [ 0x80, 0xe7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decb x0, #28" diff --git a/tests/MC/AArch64/SVE/decd.s.yaml b/tests/MC/AArch64/SVE/decd.s.yaml new file mode 100644 index 0000000000..c3ef0cc61a --- /dev/null +++ b/tests/MC/AArch64/SVE/decd.s.yaml @@ -0,0 +1,400 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xe7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0, pow2" + + - + input: + bytes: [ 0x20, 0xe4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0, vl1" + + - + input: + bytes: [ 0x40, 0xe4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0, vl2" + + - + input: + bytes: [ 0x60, 0xe4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0, vl3" + + - + input: + bytes: [ 0x80, 0xe4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0, vl4" + + - + input: + bytes: [ 0xa0, 0xe4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0, vl5" + + - + input: + bytes: [ 0xc0, 0xe4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0, vl6" + + - + input: + bytes: [ 0xe0, 0xe4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0, vl7" + + - + input: + bytes: [ 0x00, 0xe5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0, vl8" + + - + input: + bytes: [ 0x20, 0xe5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0, vl16" + + - + input: + bytes: [ 0x40, 0xe5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0, vl32" + + - + input: + bytes: [ 0x60, 0xe5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0, vl64" + + - + input: + bytes: [ 0x80, 0xe5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0, vl128" + + - + input: + bytes: [ 0xa0, 0xe5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0, vl256" + + - + input: + bytes: [ 0xc0, 0xe5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0, #14" + + - + input: + bytes: [ 0x80, 0xe7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decd x0, #28" + + - + input: + bytes: [ 0xe0, 0xe7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0, pow2" + + - + input: + bytes: [ 0x20, 0xe4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0, vl1" + + - + input: + bytes: [ 0x40, 0xe4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0, vl2" + + - + input: + bytes: [ 0x60, 0xe4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0, vl3" + + - + input: + bytes: [ 0x80, 0xe4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0, vl4" + + - + input: + bytes: [ 0xa0, 0xe4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0, vl5" + + - + input: + bytes: [ 0xc0, 0xe4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0, vl6" + + - + input: + bytes: [ 0xe0, 0xe4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0, vl7" + + - + input: + bytes: [ 0x00, 0xe5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0, vl8" + + - + input: + bytes: [ 0x20, 0xe5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0, vl16" + + - + input: + bytes: [ 0x40, 0xe5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0, vl32" + + - + input: + bytes: [ 0x60, 0xe5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0, vl64" + + - + input: + bytes: [ 0x80, 0xe5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0, vl128" + + - + input: + bytes: [ 0xa0, 0xe5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0, vl256" + + - + input: + bytes: [ 0xc0, 0xe5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0, #14" + + - + input: + bytes: [ 0x80, 0xe7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decd x0, #28" diff --git a/tests/MC/AArch64/SVE/dech.s.yaml b/tests/MC/AArch64/SVE/dech.s.yaml new file mode 100644 index 0000000000..7a7184d38d --- /dev/null +++ b/tests/MC/AArch64/SVE/dech.s.yaml @@ -0,0 +1,400 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xe7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0, pow2" + + - + input: + bytes: [ 0x20, 0xe4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0, vl1" + + - + input: + bytes: [ 0x40, 0xe4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0, vl2" + + - + input: + bytes: [ 0x60, 0xe4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0, vl3" + + - + input: + bytes: [ 0x80, 0xe4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0, vl4" + + - + input: + bytes: [ 0xa0, 0xe4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0, vl5" + + - + input: + bytes: [ 0xc0, 0xe4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0, vl6" + + - + input: + bytes: [ 0xe0, 0xe4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0, vl7" + + - + input: + bytes: [ 0x00, 0xe5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0, vl8" + + - + input: + bytes: [ 0x20, 0xe5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0, vl16" + + - + input: + bytes: [ 0x40, 0xe5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0, vl32" + + - + input: + bytes: [ 0x60, 0xe5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0, vl64" + + - + input: + bytes: [ 0x80, 0xe5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0, vl128" + + - + input: + bytes: [ 0xa0, 0xe5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0, vl256" + + - + input: + bytes: [ 0xc0, 0xe5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0, #14" + + - + input: + bytes: [ 0x80, 0xe7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dech x0, #28" + + - + input: + bytes: [ 0xe0, 0xe7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0, pow2" + + - + input: + bytes: [ 0x20, 0xe4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0, vl1" + + - + input: + bytes: [ 0x40, 0xe4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0, vl2" + + - + input: + bytes: [ 0x60, 0xe4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0, vl3" + + - + input: + bytes: [ 0x80, 0xe4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0, vl4" + + - + input: + bytes: [ 0xa0, 0xe4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0, vl5" + + - + input: + bytes: [ 0xc0, 0xe4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0, vl6" + + - + input: + bytes: [ 0xe0, 0xe4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0, vl7" + + - + input: + bytes: [ 0x00, 0xe5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0, vl8" + + - + input: + bytes: [ 0x20, 0xe5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0, vl16" + + - + input: + bytes: [ 0x40, 0xe5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0, vl32" + + - + input: + bytes: [ 0x60, 0xe5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0, vl64" + + - + input: + bytes: [ 0x80, 0xe5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0, vl128" + + - + input: + bytes: [ 0xa0, 0xe5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0, vl256" + + - + input: + bytes: [ 0xc0, 0xe5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0, #14" + + - + input: + bytes: [ 0x80, 0xe7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dech x0, #28" diff --git a/tests/MC/AArch64/SVE/decp.s.yaml b/tests/MC/AArch64/SVE/decp.s.yaml new file mode 100644 index 0000000000..b07fab2098 --- /dev/null +++ b/tests/MC/AArch64/SVE/decp.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x88, 0x2d, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decp x0, p0.b" + + - + input: + bytes: [ 0x00, 0x88, 0x6d, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decp x0, p0.h" + + - + input: + bytes: [ 0x00, 0x88, 0xad, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decp x0, p0.s" + + - + input: + bytes: [ 0x00, 0x88, 0xed, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decp x0, p0.d" + + - + input: + bytes: [ 0xff, 0x89, 0x2d, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decp xzr, p15.b" + + - + input: + bytes: [ 0xff, 0x89, 0x6d, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decp xzr, p15.h" + + - + input: + bytes: [ 0xff, 0x89, 0xad, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decp xzr, p15.s" + + - + input: + bytes: [ 0xff, 0x89, 0xed, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decp xzr, p15.d" + + - + input: + bytes: [ 0xff, 0x81, 0x6d, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decp z31.h, p15.h" + + - + input: + bytes: [ 0xff, 0x81, 0x6d, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decp z31.h, p15.h" + + - + input: + bytes: [ 0xff, 0x81, 0xad, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decp z31.s, p15.s" + + - + input: + bytes: [ 0xff, 0x81, 0xad, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decp z31.s, p15.s" + + - + input: + bytes: [ 0xff, 0x81, 0xed, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decp z31.d, p15.d" + + - + input: + bytes: [ 0xff, 0x81, 0xed, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decp z31.d, p15.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0x81, 0xed, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decp z31.d, p15.d" + + - + input: + bytes: [ 0x00, 0x88, 0x2d, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decp x0, p0.b" + + - + input: + bytes: [ 0x00, 0x88, 0x6d, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decp x0, p0.h" + + - + input: + bytes: [ 0x00, 0x88, 0xad, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decp x0, p0.s" + + - + input: + bytes: [ 0x00, 0x88, 0xed, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decp x0, p0.d" + + - + input: + bytes: [ 0xff, 0x89, 0x2d, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decp xzr, p15.b" + + - + input: + bytes: [ 0xff, 0x89, 0x6d, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decp xzr, p15.h" + + - + input: + bytes: [ 0xff, 0x89, 0xad, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decp xzr, p15.s" + + - + input: + bytes: [ 0xff, 0x89, 0xed, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decp xzr, p15.d" + + - + input: + bytes: [ 0xff, 0x81, 0x6d, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decp z31.h, p15.h" + + - + input: + bytes: [ 0xff, 0x81, 0x6d, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decp z31.h, p15.h" + + - + input: + bytes: [ 0xff, 0x81, 0xad, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decp z31.s, p15.s" + + - + input: + bytes: [ 0xff, 0x81, 0xad, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decp z31.s, p15.s" + + - + input: + bytes: [ 0xff, 0x81, 0xed, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decp z31.d, p15.d" + + - + input: + bytes: [ 0xff, 0x81, 0xed, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decp z31.d, p15.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0x81, 0xed, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decp z31.d, p15.d" diff --git a/tests/MC/AArch64/SVE/decw.s.yaml b/tests/MC/AArch64/SVE/decw.s.yaml new file mode 100644 index 0000000000..6a1e7dbedf --- /dev/null +++ b/tests/MC/AArch64/SVE/decw.s.yaml @@ -0,0 +1,400 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xe7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0, pow2" + + - + input: + bytes: [ 0x20, 0xe4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0, vl1" + + - + input: + bytes: [ 0x40, 0xe4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0, vl2" + + - + input: + bytes: [ 0x60, 0xe4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0, vl3" + + - + input: + bytes: [ 0x80, 0xe4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0, vl4" + + - + input: + bytes: [ 0xa0, 0xe4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0, vl5" + + - + input: + bytes: [ 0xc0, 0xe4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0, vl6" + + - + input: + bytes: [ 0xe0, 0xe4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0, vl7" + + - + input: + bytes: [ 0x00, 0xe5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0, vl8" + + - + input: + bytes: [ 0x20, 0xe5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0, vl16" + + - + input: + bytes: [ 0x40, 0xe5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0, vl32" + + - + input: + bytes: [ 0x60, 0xe5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0, vl64" + + - + input: + bytes: [ 0x80, 0xe5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0, vl128" + + - + input: + bytes: [ 0xa0, 0xe5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0, vl256" + + - + input: + bytes: [ 0xc0, 0xe5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0, #14" + + - + input: + bytes: [ 0x80, 0xe7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "decw x0, #28" + + - + input: + bytes: [ 0xe0, 0xe7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0" + + - + input: + bytes: [ 0xe0, 0xe7, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0, pow2" + + - + input: + bytes: [ 0x20, 0xe4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0, vl1" + + - + input: + bytes: [ 0x40, 0xe4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0, vl2" + + - + input: + bytes: [ 0x60, 0xe4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0, vl3" + + - + input: + bytes: [ 0x80, 0xe4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0, vl4" + + - + input: + bytes: [ 0xa0, 0xe4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0, vl5" + + - + input: + bytes: [ 0xc0, 0xe4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0, vl6" + + - + input: + bytes: [ 0xe0, 0xe4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0, vl7" + + - + input: + bytes: [ 0x00, 0xe5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0, vl8" + + - + input: + bytes: [ 0x20, 0xe5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0, vl16" + + - + input: + bytes: [ 0x40, 0xe5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0, vl32" + + - + input: + bytes: [ 0x60, 0xe5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0, vl64" + + - + input: + bytes: [ 0x80, 0xe5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0, vl128" + + - + input: + bytes: [ 0xa0, 0xe5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0, vl256" + + - + input: + bytes: [ 0xc0, 0xe5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0, #14" + + - + input: + bytes: [ 0x80, 0xe7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "decw x0, #28" diff --git a/tests/MC/AArch64/SVE/dot-req.s.yaml b/tests/MC/AArch64/SVE/dot-req.s.yaml new file mode 100644 index 0000000000..cb9e9d9df9 --- /dev/null +++ b/tests/MC/AArch64/SVE/dot-req.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x00, 0xa2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "sve" ] + expected: + insns: + - + asm_text: "add z0.s, z1.s, z2.s" diff --git a/tests/MC/AArch64/SVE/dup.s.yaml b/tests/MC/AArch64/SVE/dup.s.yaml new file mode 100644 index 0000000000..c6455d2255 --- /dev/null +++ b/tests/MC/AArch64/SVE/dup.s.yaml @@ -0,0 +1,840 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x38, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.b, w0" + + - + input: + bytes: [ 0x00, 0x38, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, w0" + + - + input: + bytes: [ 0x00, 0x38, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.s, w0" + + - + input: + bytes: [ 0x00, 0x38, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.d, x0" + + - + input: + bytes: [ 0xff, 0x3b, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.h, wsp" + + - + input: + bytes: [ 0xff, 0x3b, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.s, wsp" + + - + input: + bytes: [ 0xff, 0x3b, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.d, sp" + + - + input: + bytes: [ 0xff, 0x3b, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.b, wsp" + + - + input: + bytes: [ 0x05, 0xd0, 0x38, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z5.b, #-128" + + - + input: + bytes: [ 0xe5, 0xcf, 0x38, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z5.b, #127" + + - + input: + bytes: [ 0xe5, 0xdf, 0x38, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z5.b, #-1" + + - + input: + bytes: [ 0x15, 0xd0, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, #-128" + + - + input: + bytes: [ 0x15, 0xf0, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, #-32768" + + - + input: + bytes: [ 0x15, 0xf0, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, #-32768" + + - + input: + bytes: [ 0xf5, 0xcf, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, #127" + + - + input: + bytes: [ 0xf5, 0xef, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, #32512" + + - + input: + bytes: [ 0xf5, 0xef, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, #32512" + + - + input: + bytes: [ 0x15, 0xd0, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, #-128" + + - + input: + bytes: [ 0x15, 0xf0, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, #-32768" + + - + input: + bytes: [ 0x15, 0xf0, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, #-32768" + + - + input: + bytes: [ 0xf5, 0xcf, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, #127" + + - + input: + bytes: [ 0xf5, 0xef, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, #32512" + + - + input: + bytes: [ 0xf5, 0xef, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, #32512" + + - + input: + bytes: [ 0x15, 0xd0, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, #-128" + + - + input: + bytes: [ 0x15, 0xf0, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, #-32768" + + - + input: + bytes: [ 0x15, 0xf0, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, #-32768" + + - + input: + bytes: [ 0xf5, 0xcf, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, #127" + + - + input: + bytes: [ 0xf5, 0xef, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, #32512" + + - + input: + bytes: [ 0xf5, 0xef, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, #32512" + + - + input: + bytes: [ 0x00, 0x20, 0x21, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.b, b0" + + - + input: + bytes: [ 0x00, 0x20, 0x22, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, h0" + + - + input: + bytes: [ 0x00, 0x20, 0x24, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.s, s0" + + - + input: + bytes: [ 0x00, 0x20, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.d, d0" + + - + input: + bytes: [ 0x00, 0x20, 0x30, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.q, q0" + + - + input: + bytes: [ 0xff, 0x23, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.b, z31.b[63]" + + - + input: + bytes: [ 0xff, 0x23, 0xfe, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.h, z31.h[31]" + + - + input: + bytes: [ 0xff, 0x23, 0xfc, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.s, z31.s[15]" + + - + input: + bytes: [ 0xff, 0x23, 0xf8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.d, z31.d[7]" + + - + input: + bytes: [ 0x25, 0x22, 0xf0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z5.q, z17.q[3]" + + - + input: + bytes: [ 0xe0, 0xcf, 0x38, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.b, #127" + + - + input: + bytes: [ 0xe0, 0xef, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, #32512" + + - + input: + bytes: [ 0xe0, 0xef, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, #32512" + + - + input: + bytes: [ 0x00, 0x38, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, w0" + + - + input: + bytes: [ 0x00, 0x38, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, w0" + + - + input: + bytes: [ 0x00, 0x38, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, w0" + + - + input: + bytes: [ 0x00, 0x38, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, x0" + + - + input: + bytes: [ 0xff, 0x3b, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.h, wsp" + + - + input: + bytes: [ 0xff, 0x3b, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.s, wsp" + + - + input: + bytes: [ 0xff, 0x3b, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.d, sp" + + - + input: + bytes: [ 0xff, 0x3b, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.b, wsp" + + - + input: + bytes: [ 0x05, 0xd0, 0x38, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.b, #-128" + + - + input: + bytes: [ 0xe5, 0xcf, 0x38, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.b, #127" + + - + input: + bytes: [ 0xe5, 0xdf, 0x38, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.b, #-1" + + - + input: + bytes: [ 0x15, 0xd0, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, #-128" + + - + input: + bytes: [ 0x15, 0xf0, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, #-32768" + + - + input: + bytes: [ 0x15, 0xf0, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, #-32768" + + - + input: + bytes: [ 0xf5, 0xcf, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, #127" + + - + input: + bytes: [ 0xf5, 0xef, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, #32512" + + - + input: + bytes: [ 0xf5, 0xef, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, #32512" + + - + input: + bytes: [ 0x15, 0xd0, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, #-128" + + - + input: + bytes: [ 0x15, 0xf0, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, #-32768" + + - + input: + bytes: [ 0x15, 0xf0, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, #-32768" + + - + input: + bytes: [ 0xf5, 0xcf, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, #127" + + - + input: + bytes: [ 0xf5, 0xef, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, #32512" + + - + input: + bytes: [ 0xf5, 0xef, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, #32512" + + - + input: + bytes: [ 0x15, 0xd0, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, #-128" + + - + input: + bytes: [ 0x15, 0xf0, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, #-32768" + + - + input: + bytes: [ 0x15, 0xf0, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, #-32768" + + - + input: + bytes: [ 0xf5, 0xcf, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, #127" + + - + input: + bytes: [ 0xf5, 0xef, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, #32512" + + - + input: + bytes: [ 0xf5, 0xef, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, #32512" + + - + input: + bytes: [ 0x00, 0x20, 0x21, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, b0" + + - + input: + bytes: [ 0x00, 0x20, 0x22, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, h0" + + - + input: + bytes: [ 0x00, 0x20, 0x24, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, s0" + + - + input: + bytes: [ 0x00, 0x20, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, d0" + + - + input: + bytes: [ 0x00, 0x20, 0x30, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.q, q0" + + - + input: + bytes: [ 0xff, 0x23, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.b, z31.b[63]" + + - + input: + bytes: [ 0xff, 0x23, 0xfe, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.h, z31.h[31]" + + - + input: + bytes: [ 0xff, 0x23, 0xfc, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.s, z31.s[15]" + + - + input: + bytes: [ 0xff, 0x23, 0xf8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.d, z31.d[7]" + + - + input: + bytes: [ 0x25, 0x22, 0xf0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.q, z17.q[3]" + + - + input: + bytes: [ 0xe0, 0xcf, 0x38, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, #127" + + - + input: + bytes: [ 0xe0, 0xef, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, #32512" + + - + input: + bytes: [ 0xe0, 0xef, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, #32512" diff --git a/tests/MC/AArch64/SVE/dupm.s.yaml b/tests/MC/AArch64/SVE/dupm.s.yaml new file mode 100644 index 0000000000..3d841332f5 --- /dev/null +++ b/tests/MC/AArch64/SVE/dupm.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0xa5, 0x2e, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dupm z5.b, #0xf9" + + - + input: + bytes: [ 0xa5, 0x2e, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dupm z5.b, #0xf9" + + - + input: + bytes: [ 0xa5, 0x2e, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dupm z5.b, #0xf9" + + - + input: + bytes: [ 0xa5, 0x2e, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dupm z5.b, #0xf9" + + - + input: + bytes: [ 0xb7, 0x6d, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dupm z23.h, #0xfff9" + + - + input: + bytes: [ 0xb7, 0x6d, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dupm z23.h, #0xfff9" + + - + input: + bytes: [ 0xb7, 0x6d, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dupm z23.h, #0xfff9" + + - + input: + bytes: [ 0xa0, 0xeb, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dupm z0.s, #0xfffffff9" + + - + input: + bytes: [ 0xa0, 0xeb, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dupm z0.s, #0xfffffff9" + + - + input: + bytes: [ 0xa0, 0xef, 0xc3, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "dupm z0.d, #0xfffffffffffffff9" + + - + input: + bytes: [ 0xa5, 0x2e, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dupm z5.b, #0xf9" + + - + input: + bytes: [ 0xa5, 0x2e, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dupm z5.b, #0xf9" + + - + input: + bytes: [ 0xa5, 0x2e, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dupm z5.b, #0xf9" + + - + input: + bytes: [ 0xa5, 0x2e, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dupm z5.b, #0xf9" + + - + input: + bytes: [ 0xb7, 0x6d, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dupm z23.h, #0xfff9" + + - + input: + bytes: [ 0xb7, 0x6d, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dupm z23.h, #0xfff9" + + - + input: + bytes: [ 0xb7, 0x6d, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dupm z23.h, #0xfff9" + + - + input: + bytes: [ 0xa0, 0xeb, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dupm z0.s, #0xfffffff9" + + - + input: + bytes: [ 0xa0, 0xeb, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dupm z0.s, #0xfffffff9" + + - + input: + bytes: [ 0xa0, 0xef, 0xc3, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "dupm z0.d, #0xfffffffffffffff9" diff --git a/tests/MC/AArch64/SVE/eon.s.yaml b/tests/MC/AArch64/SVE/eon.s.yaml new file mode 100644 index 0000000000..ff6c9158be --- /dev/null +++ b/tests/MC/AArch64/SVE/eon.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0x25, 0x3e, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z5.b, z5.b, #0x6" + + - + input: + bytes: [ 0x37, 0x7c, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z23.h, z23.h, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z0.s, z0.s, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x43, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, #0x6" + + - + input: + bytes: [ 0xa5, 0x2e, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z5.b, z5.b, #0xf9" + + - + input: + bytes: [ 0xb7, 0x6d, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z23.h, z23.h, #0xfff9" + + - + input: + bytes: [ 0xa0, 0xeb, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z0.s, z0.s, #0xfffffff9" + + - + input: + bytes: [ 0xa0, 0xef, 0x43, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, #0xfffffffffffffff9" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xa0, 0xef, 0x43, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, #0xfffffffffffffff9" + + - + input: + bytes: [ 0x25, 0x3e, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z5.b, z5.b, #0x6" + + - + input: + bytes: [ 0x37, 0x7c, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z23.h, z23.h, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z0.s, z0.s, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x43, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, #0x6" + + - + input: + bytes: [ 0xa5, 0x2e, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z5.b, z5.b, #0xf9" + + - + input: + bytes: [ 0xb7, 0x6d, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z23.h, z23.h, #0xfff9" + + - + input: + bytes: [ 0xa0, 0xeb, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z0.s, z0.s, #0xfffffff9" + + - + input: + bytes: [ 0xa0, 0xef, 0x43, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, #0xfffffffffffffff9" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xa0, 0xef, 0x43, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, #0xfffffffffffffff9" diff --git a/tests/MC/AArch64/SVE/eor.s.yaml b/tests/MC/AArch64/SVE/eor.s.yaml new file mode 100644 index 0000000000..5bb2ce6944 --- /dev/null +++ b/tests/MC/AArch64/SVE/eor.s.yaml @@ -0,0 +1,520 @@ +test_cases: + - + input: + bytes: [ 0xa5, 0x2e, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z5.b, z5.b, #0xf9" + + - + input: + bytes: [ 0xb7, 0x6d, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z23.h, z23.h, #0xfff9" + + - + input: + bytes: [ 0xa0, 0xeb, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z0.s, z0.s, #0xfffffff9" + + - + input: + bytes: [ 0xa0, 0xef, 0x43, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, #0xfffffffffffffff9" + + - + input: + bytes: [ 0x25, 0x3e, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z5.b, z5.b, #0x6" + + - + input: + bytes: [ 0x37, 0x7c, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z23.h, z23.h, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z0.s, z0.s, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x43, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, #0x6" + + - + input: + bytes: [ 0xb7, 0x31, 0xa8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0x00, 0x30, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0xff, 0x1f, 0x99, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0x59, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0xd9, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0xff, 0x1f, 0x19, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0x42, 0x01, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor p0.b, p0/z, p0.b, p1.b" + + - + input: + bytes: [ 0x00, 0x42, 0x00, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "not p0.b, p0/z, p0.b" + + - + input: + bytes: [ 0xef, 0x7f, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "not p15.b, p15/z, p15.b" + + - + input: + bytes: [ 0x00, 0x30, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x30, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x30, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0x10, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.b, p7/z, z6.b" + + - + input: + bytes: [ 0xe4, 0x1f, 0x19, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z4.b, p7/m, z4.b, z31.b" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0x19, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z4.b, p7/m, z4.b, z31.b" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xf8, 0x43, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, #0x6" + + - + input: + bytes: [ 0xa5, 0x2e, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z5.b, z5.b, #0xf9" + + - + input: + bytes: [ 0xb7, 0x6d, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z23.h, z23.h, #0xfff9" + + - + input: + bytes: [ 0xa0, 0xeb, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z0.s, z0.s, #0xfffffff9" + + - + input: + bytes: [ 0xa0, 0xef, 0x43, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, #0xfffffffffffffff9" + + - + input: + bytes: [ 0x25, 0x3e, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z5.b, z5.b, #0x6" + + - + input: + bytes: [ 0x37, 0x7c, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z23.h, z23.h, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x40, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z0.s, z0.s, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x43, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, #0x6" + + - + input: + bytes: [ 0xb7, 0x31, 0xa8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0x00, 0x30, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0xff, 0x1f, 0x99, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0x59, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0xd9, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0xff, 0x1f, 0x19, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0x42, 0x01, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor p0.b, p0/z, p0.b, p1.b" + + - + input: + bytes: [ 0x00, 0x42, 0x00, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "not p0.b, p0/z, p0.b" + + - + input: + bytes: [ 0xef, 0x7f, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "not p15.b, p15/z, p15.b" + + - + input: + bytes: [ 0x00, 0x30, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x30, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x30, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0x10, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.b, p7/z, z6.b" + + - + input: + bytes: [ 0xe4, 0x1f, 0x19, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z4.b, p7/m, z4.b, z31.b" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0x19, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z4.b, p7/m, z4.b, z31.b" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xf8, 0x43, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor z0.d, z0.d, #0x6" diff --git a/tests/MC/AArch64/SVE/eors.s.yaml b/tests/MC/AArch64/SVE/eors.s.yaml new file mode 100644 index 0000000000..1d0836884a --- /dev/null +++ b/tests/MC/AArch64/SVE/eors.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x42, 0x41, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eors p0.b, p0/z, p0.b, p1.b" + + - + input: + bytes: [ 0x00, 0x42, 0x40, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "nots p0.b, p0/z, p0.b" + + - + input: + bytes: [ 0xef, 0x7f, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "nots p15.b, p15/z, p15.b" + + - + input: + bytes: [ 0x00, 0x42, 0x41, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eors p0.b, p0/z, p0.b, p1.b" + + - + input: + bytes: [ 0x00, 0x42, 0x40, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "nots p0.b, p0/z, p0.b" + + - + input: + bytes: [ 0xef, 0x7f, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "nots p15.b, p15/z, p15.b" diff --git a/tests/MC/AArch64/SVE/eorv.s.yaml b/tests/MC/AArch64/SVE/eorv.s.yaml new file mode 100644 index 0000000000..df4e1b56d0 --- /dev/null +++ b/tests/MC/AArch64/SVE/eorv.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x3f, 0x19, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eorv b0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x59, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eorv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x99, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eorv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xd9, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "eorv d0, p7, z31.d" + + - + input: + bytes: [ 0xe0, 0x3f, 0x19, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eorv b0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x59, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eorv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x99, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eorv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xd9, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eorv d0, p7, z31.d" diff --git a/tests/MC/AArch64/SVE/ext.s.yaml b/tests/MC/AArch64/SVE/ext.s.yaml new file mode 100644 index 0000000000..53e2c2871f --- /dev/null +++ b/tests/MC/AArch64/SVE/ext.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x1f, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ext z31.b, z31.b, z0.b, #0" + + - + input: + bytes: [ 0x1f, 0x1c, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ext z31.b, z31.b, z0.b, #255" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x1f, 0x1c, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ext z31.b, z31.b, z0.b, #255" + + - + input: + bytes: [ 0x1f, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ext z31.b, z31.b, z0.b, #0" + + - + input: + bytes: [ 0x1f, 0x1c, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ext z31.b, z31.b, z0.b, #255" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x1f, 0x1c, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ext z31.b, z31.b, z0.b, #255" diff --git a/tests/MC/AArch64/SVE/fabd.s.yaml b/tests/MC/AArch64/SVE/fabd.s.yaml new file mode 100644 index 0000000000..70063a0abb --- /dev/null +++ b/tests/MC/AArch64/SVE/fabd.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x9f, 0x48, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fabd z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x88, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fabd z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc8, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fabd z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc8, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fabd z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc8, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fabd z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0x48, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fabd z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x88, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fabd z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc8, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fabd z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc8, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fabd z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc8, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fabd z0.d, p7/m, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/fabs.s.yaml b/tests/MC/AArch64/SVE/fabs.s.yaml new file mode 100644 index 0000000000..902954087e --- /dev/null +++ b/tests/MC/AArch64/SVE/fabs.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x5c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fabs z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x9c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fabs z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xdc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fabs z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xdc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fabs z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xdc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fabs z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x5c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fabs z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x9c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fabs z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xdc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fabs z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xdc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fabs z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xdc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fabs z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/facge.s.yaml b/tests/MC/AArch64/SVE/facge.s.yaml new file mode 100644 index 0000000000..e93a9b695a --- /dev/null +++ b/tests/MC/AArch64/SVE/facge.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x10, 0xc0, 0x41, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "facge p0.h, p0/z, z0.h, z1.h" + + - + input: + bytes: [ 0x10, 0xc0, 0x81, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "facge p0.s, p0/z, z0.s, z1.s" + + - + input: + bytes: [ 0x10, 0xc0, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "facge p0.d, p0/z, z0.d, z1.d" + + - + input: + bytes: [ 0x10, 0xc0, 0x41, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "facge p0.h, p0/z, z0.h, z1.h" + + - + input: + bytes: [ 0x10, 0xc0, 0x81, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "facge p0.s, p0/z, z0.s, z1.s" + + - + input: + bytes: [ 0x10, 0xc0, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "facge p0.d, p0/z, z0.d, z1.d" diff --git a/tests/MC/AArch64/SVE/facgt.s.yaml b/tests/MC/AArch64/SVE/facgt.s.yaml new file mode 100644 index 0000000000..10e11fcea5 --- /dev/null +++ b/tests/MC/AArch64/SVE/facgt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x10, 0xe0, 0x41, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "facgt p0.h, p0/z, z0.h, z1.h" + + - + input: + bytes: [ 0x10, 0xe0, 0x81, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "facgt p0.s, p0/z, z0.s, z1.s" + + - + input: + bytes: [ 0x10, 0xe0, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "facgt p0.d, p0/z, z0.d, z1.d" + + - + input: + bytes: [ 0x10, 0xe0, 0x41, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "facgt p0.h, p0/z, z0.h, z1.h" + + - + input: + bytes: [ 0x10, 0xe0, 0x81, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "facgt p0.s, p0/z, z0.s, z1.s" + + - + input: + bytes: [ 0x10, 0xe0, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "facgt p0.d, p0/z, z0.d, z1.d" diff --git a/tests/MC/AArch64/SVE/facle.s.yaml b/tests/MC/AArch64/SVE/facle.s.yaml new file mode 100644 index 0000000000..abce925526 --- /dev/null +++ b/tests/MC/AArch64/SVE/facle.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x30, 0xc0, 0x40, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "facge p0.h, p0/z, z1.h, z0.h" + + - + input: + bytes: [ 0x30, 0xc0, 0x80, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "facge p0.s, p0/z, z1.s, z0.s" + + - + input: + bytes: [ 0x30, 0xc0, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "facge p0.d, p0/z, z1.d, z0.d" + + - + input: + bytes: [ 0x30, 0xc0, 0x40, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "facge p0.h, p0/z, z1.h, z0.h" + + - + input: + bytes: [ 0x30, 0xc0, 0x80, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "facge p0.s, p0/z, z1.s, z0.s" + + - + input: + bytes: [ 0x30, 0xc0, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "facge p0.d, p0/z, z1.d, z0.d" diff --git a/tests/MC/AArch64/SVE/faclt.s.yaml b/tests/MC/AArch64/SVE/faclt.s.yaml new file mode 100644 index 0000000000..54abcc3fc3 --- /dev/null +++ b/tests/MC/AArch64/SVE/faclt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x30, 0xe0, 0x40, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "facgt p0.h, p0/z, z1.h, z0.h" + + - + input: + bytes: [ 0x30, 0xe0, 0x80, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "facgt p0.s, p0/z, z1.s, z0.s" + + - + input: + bytes: [ 0x30, 0xe0, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "facgt p0.d, p0/z, z1.d, z0.d" + + - + input: + bytes: [ 0x30, 0xe0, 0x40, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "facgt p0.h, p0/z, z1.h, z0.h" + + - + input: + bytes: [ 0x30, 0xe0, 0x80, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "facgt p0.s, p0/z, z1.s, z0.s" + + - + input: + bytes: [ 0x30, 0xe0, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "facgt p0.d, p0/z, z1.d, z0.d" diff --git a/tests/MC/AArch64/SVE/fadd.s.yaml b/tests/MC/AArch64/SVE/fadd.s.yaml new file mode 100644 index 0000000000..ea6793e052 --- /dev/null +++ b/tests/MC/AArch64/SVE/fadd.s.yaml @@ -0,0 +1,440 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x58, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadd z0.h, p0/m, z0.h, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0x58, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadd z0.h, p0/m, z0.h, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0x98, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadd z0.s, p0/m, z0.s, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0xd8, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadd z0.d, p0/m, z0.d, #0.5" + + - + input: + bytes: [ 0x3f, 0x9c, 0x58, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadd z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x58, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadd z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x98, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadd z31.s, p7/m, z31.s, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0xd8, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadd z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x9f, 0x40, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadd z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x80, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadd z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadd z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0x20, 0x00, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadd z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x00, 0x9f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadd z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x00, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadd z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p7/z, z6.d" + + - + input: + bytes: [ 0x3f, 0x9c, 0xd8, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadd z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x3f, 0x9c, 0xd8, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadd z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadd z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadd z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0x00, 0x80, 0x58, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fadd z0.h, p0/m, z0.h, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0x58, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fadd z0.h, p0/m, z0.h, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0x98, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fadd z0.s, p0/m, z0.s, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0xd8, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fadd z0.d, p0/m, z0.d, #0.5" + + - + input: + bytes: [ 0x3f, 0x9c, 0x58, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fadd z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x58, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fadd z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x98, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fadd z31.s, p7/m, z31.s, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0xd8, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fadd z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x9f, 0x40, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fadd z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x80, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fadd z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fadd z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0x20, 0x00, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fadd z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x00, 0x9f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fadd z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x00, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fadd z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p7/z, z6.d" + + - + input: + bytes: [ 0x3f, 0x9c, 0xd8, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fadd z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x3f, 0x9c, 0xd8, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fadd z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fadd z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fadd z0.d, p7/m, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/fadda.s.yaml b/tests/MC/AArch64/SVE/fadda.s.yaml new file mode 100644 index 0000000000..d5552e608b --- /dev/null +++ b/tests/MC/AArch64/SVE/fadda.s.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x3f, 0x58, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadda h0, p7, h0, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x98, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadda s0, p7, s0, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xd8, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fadda d0, p7, d0, z31.d" diff --git a/tests/MC/AArch64/SVE/faddv.s.yaml b/tests/MC/AArch64/SVE/faddv.s.yaml new file mode 100644 index 0000000000..51216a137a --- /dev/null +++ b/tests/MC/AArch64/SVE/faddv.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x3f, 0x40, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "faddv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x80, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "faddv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "faddv d0, p7, z31.d" + + - + input: + bytes: [ 0xe0, 0x3f, 0x40, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "faddv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x80, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "faddv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "faddv d0, p7, z31.d" diff --git a/tests/MC/AArch64/SVE/fcadd.s.yaml b/tests/MC/AArch64/SVE/fcadd.s.yaml new file mode 100644 index 0000000000..8921245f4f --- /dev/null +++ b/tests/MC/AArch64/SVE/fcadd.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x40, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcadd z0.h, p0/m, z0.h, z0.h, #90" + + - + input: + bytes: [ 0x00, 0x80, 0x80, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcadd z0.s, p0/m, z0.s, z0.s, #90" + + - + input: + bytes: [ 0x00, 0x80, 0xc0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcadd z0.d, p0/m, z0.d, z0.d, #90" + + - + input: + bytes: [ 0xff, 0x9f, 0x41, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcadd z31.h, p7/m, z31.h, z31.h, #270" + + - + input: + bytes: [ 0xff, 0x9f, 0x81, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcadd z31.s, p7/m, z31.s, z31.s, #270" + + - + input: + bytes: [ 0xff, 0x9f, 0xc1, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcadd z31.d, p7/m, z31.d, z31.d, #270" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x9f, 0xc1, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcadd z4.d, p7/m, z4.d, z31.d, #270" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x9f, 0xc1, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcadd z4.d, p7/m, z4.d, z31.d, #270" + + - + input: + bytes: [ 0x00, 0x80, 0x40, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcadd z0.h, p0/m, z0.h, z0.h, #90" + + - + input: + bytes: [ 0x00, 0x80, 0x80, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcadd z0.s, p0/m, z0.s, z0.s, #90" + + - + input: + bytes: [ 0x00, 0x80, 0xc0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcadd z0.d, p0/m, z0.d, z0.d, #90" + + - + input: + bytes: [ 0xff, 0x9f, 0x41, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcadd z31.h, p7/m, z31.h, z31.h, #270" + + - + input: + bytes: [ 0xff, 0x9f, 0x81, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcadd z31.s, p7/m, z31.s, z31.s, #270" + + - + input: + bytes: [ 0xff, 0x9f, 0xc1, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcadd z31.d, p7/m, z31.d, z31.d, #270" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x9f, 0xc1, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcadd z4.d, p7/m, z4.d, z31.d, #270" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x9f, 0xc1, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcadd z4.d, p7/m, z4.d, z31.d, #270" diff --git a/tests/MC/AArch64/SVE/fcmeq.s.yaml b/tests/MC/AArch64/SVE/fcmeq.s.yaml new file mode 100644 index 0000000000..c035a05312 --- /dev/null +++ b/tests/MC/AArch64/SVE/fcmeq.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x52, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmeq p0.h, p0/z, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x20, 0x92, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmeq p0.s, p0/z, z0.s, #0.0" + + - + input: + bytes: [ 0x00, 0x20, 0xd2, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmeq p0.d, p0/z, z0.d, #0.0" + + - + input: + bytes: [ 0x00, 0x60, 0x41, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmeq p0.h, p0/z, z0.h, z1.h" + + - + input: + bytes: [ 0x00, 0x60, 0x81, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmeq p0.s, p0/z, z0.s, z1.s" + + - + input: + bytes: [ 0x00, 0x60, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmeq p0.d, p0/z, z0.d, z1.d" + + - + input: + bytes: [ 0x00, 0x20, 0x52, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmeq p0.h, p0/z, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x20, 0x92, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmeq p0.s, p0/z, z0.s, #0.0" + + - + input: + bytes: [ 0x00, 0x20, 0xd2, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmeq p0.d, p0/z, z0.d, #0.0" + + - + input: + bytes: [ 0x00, 0x60, 0x41, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmeq p0.h, p0/z, z0.h, z1.h" + + - + input: + bytes: [ 0x00, 0x60, 0x81, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmeq p0.s, p0/z, z0.s, z1.s" + + - + input: + bytes: [ 0x00, 0x60, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmeq p0.d, p0/z, z0.d, z1.d" diff --git a/tests/MC/AArch64/SVE/fcmge.s.yaml b/tests/MC/AArch64/SVE/fcmge.s.yaml new file mode 100644 index 0000000000..c8ed1a797f --- /dev/null +++ b/tests/MC/AArch64/SVE/fcmge.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x50, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmge p0.h, p0/z, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x20, 0x90, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmge p0.s, p0/z, z0.s, #0.0" + + - + input: + bytes: [ 0x00, 0x20, 0xd0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmge p0.d, p0/z, z0.d, #0.0" + + - + input: + bytes: [ 0x00, 0x40, 0x41, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmge p0.h, p0/z, z0.h, z1.h" + + - + input: + bytes: [ 0x00, 0x40, 0x81, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmge p0.s, p0/z, z0.s, z1.s" + + - + input: + bytes: [ 0x00, 0x40, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmge p0.d, p0/z, z0.d, z1.d" + + - + input: + bytes: [ 0x00, 0x20, 0x50, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmge p0.h, p0/z, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x20, 0x90, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmge p0.s, p0/z, z0.s, #0.0" + + - + input: + bytes: [ 0x00, 0x20, 0xd0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmge p0.d, p0/z, z0.d, #0.0" + + - + input: + bytes: [ 0x00, 0x40, 0x41, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmge p0.h, p0/z, z0.h, z1.h" + + - + input: + bytes: [ 0x00, 0x40, 0x81, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmge p0.s, p0/z, z0.s, z1.s" + + - + input: + bytes: [ 0x00, 0x40, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmge p0.d, p0/z, z0.d, z1.d" diff --git a/tests/MC/AArch64/SVE/fcmgt.s.yaml b/tests/MC/AArch64/SVE/fcmgt.s.yaml new file mode 100644 index 0000000000..5f1961e19b --- /dev/null +++ b/tests/MC/AArch64/SVE/fcmgt.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x20, 0x50, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmgt p0.h, p0/z, z0.h, #0.0" + + - + input: + bytes: [ 0x10, 0x20, 0x90, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmgt p0.s, p0/z, z0.s, #0.0" + + - + input: + bytes: [ 0x10, 0x20, 0xd0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmgt p0.d, p0/z, z0.d, #0.0" + + - + input: + bytes: [ 0x10, 0x40, 0x41, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmgt p0.h, p0/z, z0.h, z1.h" + + - + input: + bytes: [ 0x10, 0x40, 0x81, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmgt p0.s, p0/z, z0.s, z1.s" + + - + input: + bytes: [ 0x10, 0x40, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmgt p0.d, p0/z, z0.d, z1.d" + + - + input: + bytes: [ 0x10, 0x20, 0x50, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmgt p0.h, p0/z, z0.h, #0.0" + + - + input: + bytes: [ 0x10, 0x20, 0x90, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmgt p0.s, p0/z, z0.s, #0.0" + + - + input: + bytes: [ 0x10, 0x20, 0xd0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmgt p0.d, p0/z, z0.d, #0.0" + + - + input: + bytes: [ 0x10, 0x40, 0x41, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmgt p0.h, p0/z, z0.h, z1.h" + + - + input: + bytes: [ 0x10, 0x40, 0x81, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmgt p0.s, p0/z, z0.s, z1.s" + + - + input: + bytes: [ 0x10, 0x40, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmgt p0.d, p0/z, z0.d, z1.d" diff --git a/tests/MC/AArch64/SVE/fcmla.s.yaml b/tests/MC/AArch64/SVE/fcmla.s.yaml new file mode 100644 index 0000000000..caa51ef496 --- /dev/null +++ b/tests/MC/AArch64/SVE/fcmla.s.yaml @@ -0,0 +1,440 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x40, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmla z0.h, p0/m, z0.h, z0.h, #0" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmla z0.s, p0/m, z0.s, z0.s, #0" + + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmla z0.d, p0/m, z0.d, z0.d, #0" + + - + input: + bytes: [ 0x20, 0x20, 0x42, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmla z0.h, p0/m, z1.h, z2.h, #90" + + - + input: + bytes: [ 0x20, 0x20, 0x82, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmla z0.s, p0/m, z1.s, z2.s, #90" + + - + input: + bytes: [ 0x20, 0x20, 0xc2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmla z0.d, p0/m, z1.d, z2.d, #90" + + - + input: + bytes: [ 0xdd, 0x5f, 0x5f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmla z29.h, p7/m, z30.h, z31.h, #180" + + - + input: + bytes: [ 0xdd, 0x5f, 0x9f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmla z29.s, p7/m, z30.s, z31.s, #180" + + - + input: + bytes: [ 0xdd, 0x5f, 0xdf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmla z29.d, p7/m, z30.d, z31.d, #180" + + - + input: + bytes: [ 0xff, 0x7f, 0x5f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmla z31.h, p7/m, z31.h, z31.h, #270" + + - + input: + bytes: [ 0xff, 0x7f, 0x9f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmla z31.s, p7/m, z31.s, z31.s, #270" + + - + input: + bytes: [ 0xff, 0x7f, 0xdf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmla z31.d, p7/m, z31.d, z31.d, #270" + + - + input: + bytes: [ 0x00, 0x10, 0xa0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmla z0.h, z0.h, z0.h[0], #0" + + - + input: + bytes: [ 0xb7, 0x1d, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmla z23.s, z13.s, z8.s[0], #270" + + - + input: + bytes: [ 0xff, 0x1f, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmla z31.h, z31.h, z7.h[3], #270" + + - + input: + bytes: [ 0x55, 0x15, 0xf5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmla z21.s, z10.s, z5.s[1], #90" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x7f, 0xdf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmla z4.d, p7/m, z31.d, z31.d, #270" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x7f, 0xdf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmla z4.d, p7/m, z31.d, z31.d, #270" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x15, 0xf5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmla z21.s, z10.s, z5.s[1], #90" + + - + input: + bytes: [ 0x00, 0x00, 0x40, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmla z0.h, p0/m, z0.h, z0.h, #0" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmla z0.s, p0/m, z0.s, z0.s, #0" + + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmla z0.d, p0/m, z0.d, z0.d, #0" + + - + input: + bytes: [ 0x20, 0x20, 0x42, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmla z0.h, p0/m, z1.h, z2.h, #90" + + - + input: + bytes: [ 0x20, 0x20, 0x82, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmla z0.s, p0/m, z1.s, z2.s, #90" + + - + input: + bytes: [ 0x20, 0x20, 0xc2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmla z0.d, p0/m, z1.d, z2.d, #90" + + - + input: + bytes: [ 0xdd, 0x5f, 0x5f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmla z29.h, p7/m, z30.h, z31.h, #180" + + - + input: + bytes: [ 0xdd, 0x5f, 0x9f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmla z29.s, p7/m, z30.s, z31.s, #180" + + - + input: + bytes: [ 0xdd, 0x5f, 0xdf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmla z29.d, p7/m, z30.d, z31.d, #180" + + - + input: + bytes: [ 0xff, 0x7f, 0x5f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmla z31.h, p7/m, z31.h, z31.h, #270" + + - + input: + bytes: [ 0xff, 0x7f, 0x9f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmla z31.s, p7/m, z31.s, z31.s, #270" + + - + input: + bytes: [ 0xff, 0x7f, 0xdf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmla z31.d, p7/m, z31.d, z31.d, #270" + + - + input: + bytes: [ 0x00, 0x10, 0xa0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmla z0.h, z0.h, z0.h[0], #0" + + - + input: + bytes: [ 0xb7, 0x1d, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmla z23.s, z13.s, z8.s[0], #270" + + - + input: + bytes: [ 0xff, 0x1f, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmla z31.h, z31.h, z7.h[3], #270" + + - + input: + bytes: [ 0x55, 0x15, 0xf5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmla z21.s, z10.s, z5.s[1], #90" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x7f, 0xdf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmla z4.d, p7/m, z31.d, z31.d, #270" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x7f, 0xdf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmla z4.d, p7/m, z31.d, z31.d, #270" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x15, 0xf5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmla z21.s, z10.s, z5.s[1], #90" diff --git a/tests/MC/AArch64/SVE/fcmle.s.yaml b/tests/MC/AArch64/SVE/fcmle.s.yaml new file mode 100644 index 0000000000..6bf5268fb3 --- /dev/null +++ b/tests/MC/AArch64/SVE/fcmle.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x20, 0x51, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmle p0.h, p0/z, z0.h, #0.0" + + - + input: + bytes: [ 0x10, 0x20, 0x91, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmle p0.s, p0/z, z0.s, #0.0" + + - + input: + bytes: [ 0x10, 0x20, 0xd1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmle p0.d, p0/z, z0.d, #0.0" + + - + input: + bytes: [ 0x20, 0x40, 0x40, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmge p0.h, p0/z, z1.h, z0.h" + + - + input: + bytes: [ 0x20, 0x40, 0x80, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmge p0.s, p0/z, z1.s, z0.s" + + - + input: + bytes: [ 0x20, 0x40, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmge p0.d, p0/z, z1.d, z0.d" + + - + input: + bytes: [ 0x10, 0x20, 0x51, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmle p0.h, p0/z, z0.h, #0.0" + + - + input: + bytes: [ 0x10, 0x20, 0x91, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmle p0.s, p0/z, z0.s, #0.0" + + - + input: + bytes: [ 0x10, 0x20, 0xd1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmle p0.d, p0/z, z0.d, #0.0" + + - + input: + bytes: [ 0x20, 0x40, 0x40, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmge p0.h, p0/z, z1.h, z0.h" + + - + input: + bytes: [ 0x20, 0x40, 0x80, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmge p0.s, p0/z, z1.s, z0.s" + + - + input: + bytes: [ 0x20, 0x40, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmge p0.d, p0/z, z1.d, z0.d" diff --git a/tests/MC/AArch64/SVE/fcmlt.s.yaml b/tests/MC/AArch64/SVE/fcmlt.s.yaml new file mode 100644 index 0000000000..56ba75b4bc --- /dev/null +++ b/tests/MC/AArch64/SVE/fcmlt.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x51, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmlt p0.h, p0/z, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x20, 0x91, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmlt p0.s, p0/z, z0.s, #0.0" + + - + input: + bytes: [ 0x00, 0x20, 0xd1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmlt p0.d, p0/z, z0.d, #0.0" + + - + input: + bytes: [ 0x30, 0x40, 0x40, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmgt p0.h, p0/z, z1.h, z0.h" + + - + input: + bytes: [ 0x30, 0x40, 0x80, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmgt p0.s, p0/z, z1.s, z0.s" + + - + input: + bytes: [ 0x30, 0x40, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmgt p0.d, p0/z, z1.d, z0.d" + + - + input: + bytes: [ 0x00, 0x20, 0x51, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmlt p0.h, p0/z, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x20, 0x91, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmlt p0.s, p0/z, z0.s, #0.0" + + - + input: + bytes: [ 0x00, 0x20, 0xd1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmlt p0.d, p0/z, z0.d, #0.0" + + - + input: + bytes: [ 0x30, 0x40, 0x40, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmgt p0.h, p0/z, z1.h, z0.h" + + - + input: + bytes: [ 0x30, 0x40, 0x80, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmgt p0.s, p0/z, z1.s, z0.s" + + - + input: + bytes: [ 0x30, 0x40, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmgt p0.d, p0/z, z1.d, z0.d" diff --git a/tests/MC/AArch64/SVE/fcmne.s.yaml b/tests/MC/AArch64/SVE/fcmne.s.yaml new file mode 100644 index 0000000000..e6d42c53fd --- /dev/null +++ b/tests/MC/AArch64/SVE/fcmne.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x53, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmne p0.h, p0/z, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x20, 0x93, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmne p0.s, p0/z, z0.s, #0.0" + + - + input: + bytes: [ 0x00, 0x20, 0xd3, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmne p0.d, p0/z, z0.d, #0.0" + + - + input: + bytes: [ 0x10, 0x60, 0x41, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmne p0.h, p0/z, z0.h, z1.h" + + - + input: + bytes: [ 0x10, 0x60, 0x81, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmne p0.s, p0/z, z0.s, z1.s" + + - + input: + bytes: [ 0x10, 0x60, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmne p0.d, p0/z, z0.d, z1.d" + + - + input: + bytes: [ 0x00, 0x20, 0x53, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmne p0.h, p0/z, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x20, 0x93, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmne p0.s, p0/z, z0.s, #0.0" + + - + input: + bytes: [ 0x00, 0x20, 0xd3, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmne p0.d, p0/z, z0.d, #0.0" + + - + input: + bytes: [ 0x10, 0x60, 0x41, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmne p0.h, p0/z, z0.h, z1.h" + + - + input: + bytes: [ 0x10, 0x60, 0x81, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmne p0.s, p0/z, z0.s, z1.s" + + - + input: + bytes: [ 0x10, 0x60, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmne p0.d, p0/z, z0.d, z1.d" diff --git a/tests/MC/AArch64/SVE/fcmuo.s.yaml b/tests/MC/AArch64/SVE/fcmuo.s.yaml new file mode 100644 index 0000000000..db45ab38d0 --- /dev/null +++ b/tests/MC/AArch64/SVE/fcmuo.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0x41, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmuo p0.h, p0/z, z0.h, z1.h" + + - + input: + bytes: [ 0x00, 0xc0, 0x81, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmuo p0.s, p0/z, z0.s, z1.s" + + - + input: + bytes: [ 0x00, 0xc0, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcmuo p0.d, p0/z, z0.d, z1.d" + + - + input: + bytes: [ 0x00, 0xc0, 0x41, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmuo p0.h, p0/z, z0.h, z1.h" + + - + input: + bytes: [ 0x00, 0xc0, 0x81, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmuo p0.s, p0/z, z0.s, z1.s" + + - + input: + bytes: [ 0x00, 0xc0, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcmuo p0.d, p0/z, z0.d, z1.d" diff --git a/tests/MC/AArch64/SVE/fcpy.s.yaml b/tests/MC/AArch64/SVE/fcpy.s.yaml new file mode 100644 index 0000000000..ce2eec1044 --- /dev/null +++ b/tests/MC/AArch64/SVE/fcpy.s.yaml @@ -0,0 +1,5240 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xd8, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.h, p0/m, #-0.12500000" + + - + input: + bytes: [ 0x00, 0xd8, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.s, p0/m, #-0.12500000" + + - + input: + bytes: [ 0x00, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.12500000" + + - + input: + bytes: [ 0x20, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.13281250" + + - + input: + bytes: [ 0x40, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.14062500" + + - + input: + bytes: [ 0x60, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.14843750" + + - + input: + bytes: [ 0x80, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.15625000" + + - + input: + bytes: [ 0xa0, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.16406250" + + - + input: + bytes: [ 0xc0, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.17187500" + + - + input: + bytes: [ 0xe0, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.17968750" + + - + input: + bytes: [ 0x00, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.18750000" + + - + input: + bytes: [ 0x20, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.19531250" + + - + input: + bytes: [ 0x40, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.20312500" + + - + input: + bytes: [ 0x60, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.21093750" + + - + input: + bytes: [ 0x80, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.21875000" + + - + input: + bytes: [ 0xa0, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.22656250" + + - + input: + bytes: [ 0xc0, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.23437500" + + - + input: + bytes: [ 0xe0, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.24218750" + + - + input: + bytes: [ 0x00, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.25000000" + + - + input: + bytes: [ 0x20, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.26562500" + + - + input: + bytes: [ 0x40, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.28125000" + + - + input: + bytes: [ 0x60, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.29687500" + + - + input: + bytes: [ 0x80, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.31250000" + + - + input: + bytes: [ 0xa0, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.32812500" + + - + input: + bytes: [ 0xc0, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.34375000" + + - + input: + bytes: [ 0xe0, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.35937500" + + - + input: + bytes: [ 0x00, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.37500000" + + - + input: + bytes: [ 0x20, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.39062500" + + - + input: + bytes: [ 0x40, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.40625000" + + - + input: + bytes: [ 0x60, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.42187500" + + - + input: + bytes: [ 0x80, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.43750000" + + - + input: + bytes: [ 0xa0, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.45312500" + + - + input: + bytes: [ 0xc0, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.46875000" + + - + input: + bytes: [ 0xe0, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.48437500" + + - + input: + bytes: [ 0x00, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.50000000" + + - + input: + bytes: [ 0x20, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.53125000" + + - + input: + bytes: [ 0x40, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.56250000" + + - + input: + bytes: [ 0x60, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.59375000" + + - + input: + bytes: [ 0x80, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.62500000" + + - + input: + bytes: [ 0xa0, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.65625000" + + - + input: + bytes: [ 0xc0, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.68750000" + + - + input: + bytes: [ 0xe0, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.71875000" + + - + input: + bytes: [ 0x00, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.75000000" + + - + input: + bytes: [ 0x20, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.78125000" + + - + input: + bytes: [ 0x40, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.81250000" + + - + input: + bytes: [ 0x60, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.84375000" + + - + input: + bytes: [ 0x80, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.87500000" + + - + input: + bytes: [ 0xa0, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.90625000" + + - + input: + bytes: [ 0xc0, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.93750000" + + - + input: + bytes: [ 0xe0, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.96875000" + + - + input: + bytes: [ 0x00, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.00000000" + + - + input: + bytes: [ 0x20, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.06250000" + + - + input: + bytes: [ 0x40, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.12500000" + + - + input: + bytes: [ 0x60, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.18750000" + + - + input: + bytes: [ 0x80, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.25000000" + + - + input: + bytes: [ 0xa0, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.31250000" + + - + input: + bytes: [ 0xc0, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.37500000" + + - + input: + bytes: [ 0xe0, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.43750000" + + - + input: + bytes: [ 0x00, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.50000000" + + - + input: + bytes: [ 0x20, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.56250000" + + - + input: + bytes: [ 0x40, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.62500000" + + - + input: + bytes: [ 0x60, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.68750000" + + - + input: + bytes: [ 0x80, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.75000000" + + - + input: + bytes: [ 0xa0, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.81250000" + + - + input: + bytes: [ 0xc0, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.87500000" + + - + input: + bytes: [ 0xe0, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.93750000" + + - + input: + bytes: [ 0x00, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.00000000" + + - + input: + bytes: [ 0x20, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.12500000" + + - + input: + bytes: [ 0x40, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.25000000" + + - + input: + bytes: [ 0x60, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.37500000" + + - + input: + bytes: [ 0x80, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.50000000" + + - + input: + bytes: [ 0xa0, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.62500000" + + - + input: + bytes: [ 0xc0, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.75000000" + + - + input: + bytes: [ 0xe0, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.87500000" + + - + input: + bytes: [ 0x00, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.00000000" + + - + input: + bytes: [ 0x20, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.12500000" + + - + input: + bytes: [ 0x40, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.25000000" + + - + input: + bytes: [ 0x60, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.37500000" + + - + input: + bytes: [ 0x80, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.50000000" + + - + input: + bytes: [ 0xa0, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.62500000" + + - + input: + bytes: [ 0xc0, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.75000000" + + - + input: + bytes: [ 0xe0, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.87500000" + + - + input: + bytes: [ 0x00, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-4.00000000" + + - + input: + bytes: [ 0x20, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-4.25000000" + + - + input: + bytes: [ 0x40, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-4.50000000" + + - + input: + bytes: [ 0x60, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-4.75000000" + + - + input: + bytes: [ 0x80, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-5.00000000" + + - + input: + bytes: [ 0xa0, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-5.25000000" + + - + input: + bytes: [ 0xc0, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-5.50000000" + + - + input: + bytes: [ 0xe0, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-5.75000000" + + - + input: + bytes: [ 0x00, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-6.00000000" + + - + input: + bytes: [ 0x20, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-6.25000000" + + - + input: + bytes: [ 0x40, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-6.50000000" + + - + input: + bytes: [ 0x60, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-6.75000000" + + - + input: + bytes: [ 0x80, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-7.00000000" + + - + input: + bytes: [ 0xa0, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-7.25000000" + + - + input: + bytes: [ 0xc0, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-7.50000000" + + - + input: + bytes: [ 0xe0, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-7.75000000" + + - + input: + bytes: [ 0x00, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-8.00000000" + + - + input: + bytes: [ 0x20, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-8.50000000" + + - + input: + bytes: [ 0x40, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-9.00000000" + + - + input: + bytes: [ 0x60, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-9.50000000" + + - + input: + bytes: [ 0x80, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-10.00000000" + + - + input: + bytes: [ 0xa0, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-10.50000000" + + - + input: + bytes: [ 0xc0, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-11.00000000" + + - + input: + bytes: [ 0xe0, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-11.50000000" + + - + input: + bytes: [ 0x00, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-12.00000000" + + - + input: + bytes: [ 0x20, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-12.50000000" + + - + input: + bytes: [ 0x40, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-13.00000000" + + - + input: + bytes: [ 0x60, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-13.50000000" + + - + input: + bytes: [ 0x80, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-14.00000000" + + - + input: + bytes: [ 0xa0, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-14.50000000" + + - + input: + bytes: [ 0xc0, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-15.00000000" + + - + input: + bytes: [ 0xe0, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-15.50000000" + + - + input: + bytes: [ 0x00, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-16.00000000" + + - + input: + bytes: [ 0x20, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-17.00000000" + + - + input: + bytes: [ 0x40, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-18.00000000" + + - + input: + bytes: [ 0x60, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-19.00000000" + + - + input: + bytes: [ 0x80, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-20.00000000" + + - + input: + bytes: [ 0xa0, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-21.00000000" + + - + input: + bytes: [ 0xc0, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-22.00000000" + + - + input: + bytes: [ 0xe0, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-23.00000000" + + - + input: + bytes: [ 0x00, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-24.00000000" + + - + input: + bytes: [ 0x20, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-25.00000000" + + - + input: + bytes: [ 0x40, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-26.00000000" + + - + input: + bytes: [ 0x60, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-27.00000000" + + - + input: + bytes: [ 0x80, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-28.00000000" + + - + input: + bytes: [ 0xa0, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-29.00000000" + + - + input: + bytes: [ 0xc0, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-30.00000000" + + - + input: + bytes: [ 0xe0, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-31.00000000" + + - + input: + bytes: [ 0x00, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.12500000" + + - + input: + bytes: [ 0x20, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.13281250" + + - + input: + bytes: [ 0x40, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.14062500" + + - + input: + bytes: [ 0x60, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.14843750" + + - + input: + bytes: [ 0x80, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.15625000" + + - + input: + bytes: [ 0xa0, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.16406250" + + - + input: + bytes: [ 0xc0, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.17187500" + + - + input: + bytes: [ 0xe0, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.17968750" + + - + input: + bytes: [ 0x00, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.18750000" + + - + input: + bytes: [ 0x20, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.19531250" + + - + input: + bytes: [ 0x40, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.20312500" + + - + input: + bytes: [ 0x60, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.21093750" + + - + input: + bytes: [ 0x80, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.21875000" + + - + input: + bytes: [ 0xa0, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.22656250" + + - + input: + bytes: [ 0xc0, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.23437500" + + - + input: + bytes: [ 0xe0, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.24218750" + + - + input: + bytes: [ 0x00, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.25000000" + + - + input: + bytes: [ 0x20, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.26562500" + + - + input: + bytes: [ 0x40, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.28125000" + + - + input: + bytes: [ 0x60, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.29687500" + + - + input: + bytes: [ 0x80, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.31250000" + + - + input: + bytes: [ 0xa0, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.32812500" + + - + input: + bytes: [ 0xc0, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.34375000" + + - + input: + bytes: [ 0xe0, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.35937500" + + - + input: + bytes: [ 0x00, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.37500000" + + - + input: + bytes: [ 0x20, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.39062500" + + - + input: + bytes: [ 0x40, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.40625000" + + - + input: + bytes: [ 0x60, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.42187500" + + - + input: + bytes: [ 0x80, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.43750000" + + - + input: + bytes: [ 0xa0, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.45312500" + + - + input: + bytes: [ 0xc0, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.46875000" + + - + input: + bytes: [ 0xe0, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.48437500" + + - + input: + bytes: [ 0x00, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.50000000" + + - + input: + bytes: [ 0x20, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.53125000" + + - + input: + bytes: [ 0x40, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.56250000" + + - + input: + bytes: [ 0x60, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.59375000" + + - + input: + bytes: [ 0x80, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.62500000" + + - + input: + bytes: [ 0xa0, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.65625000" + + - + input: + bytes: [ 0xc0, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.68750000" + + - + input: + bytes: [ 0xe0, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.71875000" + + - + input: + bytes: [ 0x00, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.75000000" + + - + input: + bytes: [ 0x20, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.78125000" + + - + input: + bytes: [ 0x40, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.81250000" + + - + input: + bytes: [ 0x60, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.84375000" + + - + input: + bytes: [ 0x80, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.87500000" + + - + input: + bytes: [ 0xa0, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.90625000" + + - + input: + bytes: [ 0xc0, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.93750000" + + - + input: + bytes: [ 0xe0, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.96875000" + + - + input: + bytes: [ 0x00, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.00000000" + + - + input: + bytes: [ 0x20, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.06250000" + + - + input: + bytes: [ 0x40, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.12500000" + + - + input: + bytes: [ 0x60, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.18750000" + + - + input: + bytes: [ 0x80, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.25000000" + + - + input: + bytes: [ 0xa0, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.31250000" + + - + input: + bytes: [ 0xc0, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.37500000" + + - + input: + bytes: [ 0xe0, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.43750000" + + - + input: + bytes: [ 0x00, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.50000000" + + - + input: + bytes: [ 0x20, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.56250000" + + - + input: + bytes: [ 0x40, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.62500000" + + - + input: + bytes: [ 0x60, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.68750000" + + - + input: + bytes: [ 0x80, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.75000000" + + - + input: + bytes: [ 0xa0, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.81250000" + + - + input: + bytes: [ 0xc0, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.87500000" + + - + input: + bytes: [ 0xe0, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.93750000" + + - + input: + bytes: [ 0x00, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.00000000" + + - + input: + bytes: [ 0x20, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.12500000" + + - + input: + bytes: [ 0x40, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.25000000" + + - + input: + bytes: [ 0x60, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.37500000" + + - + input: + bytes: [ 0x80, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.50000000" + + - + input: + bytes: [ 0xa0, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.62500000" + + - + input: + bytes: [ 0xc0, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.75000000" + + - + input: + bytes: [ 0xe0, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.87500000" + + - + input: + bytes: [ 0x00, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.00000000" + + - + input: + bytes: [ 0x20, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.12500000" + + - + input: + bytes: [ 0x40, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.25000000" + + - + input: + bytes: [ 0x60, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.37500000" + + - + input: + bytes: [ 0x80, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.50000000" + + - + input: + bytes: [ 0xa0, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.62500000" + + - + input: + bytes: [ 0xc0, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.75000000" + + - + input: + bytes: [ 0xe0, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.87500000" + + - + input: + bytes: [ 0x00, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #4.00000000" + + - + input: + bytes: [ 0x20, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #4.25000000" + + - + input: + bytes: [ 0x40, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #4.50000000" + + - + input: + bytes: [ 0x60, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #4.75000000" + + - + input: + bytes: [ 0x80, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #5.00000000" + + - + input: + bytes: [ 0xa0, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #5.25000000" + + - + input: + bytes: [ 0xc0, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #5.50000000" + + - + input: + bytes: [ 0xe0, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #5.75000000" + + - + input: + bytes: [ 0x00, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #6.00000000" + + - + input: + bytes: [ 0x20, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #6.25000000" + + - + input: + bytes: [ 0x40, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #6.50000000" + + - + input: + bytes: [ 0x60, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #6.75000000" + + - + input: + bytes: [ 0x80, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #7.00000000" + + - + input: + bytes: [ 0xa0, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #7.25000000" + + - + input: + bytes: [ 0xc0, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #7.50000000" + + - + input: + bytes: [ 0xe0, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #7.75000000" + + - + input: + bytes: [ 0x00, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #8.00000000" + + - + input: + bytes: [ 0x20, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #8.50000000" + + - + input: + bytes: [ 0x40, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #9.00000000" + + - + input: + bytes: [ 0x60, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #9.50000000" + + - + input: + bytes: [ 0x80, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #10.00000000" + + - + input: + bytes: [ 0xa0, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #10.50000000" + + - + input: + bytes: [ 0xc0, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #11.00000000" + + - + input: + bytes: [ 0xe0, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #11.50000000" + + - + input: + bytes: [ 0x00, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #12.00000000" + + - + input: + bytes: [ 0x20, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #12.50000000" + + - + input: + bytes: [ 0x40, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #13.00000000" + + - + input: + bytes: [ 0x60, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #13.50000000" + + - + input: + bytes: [ 0x80, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #14.00000000" + + - + input: + bytes: [ 0xa0, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #14.50000000" + + - + input: + bytes: [ 0xc0, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #15.00000000" + + - + input: + bytes: [ 0xe0, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #15.50000000" + + - + input: + bytes: [ 0x00, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #16.00000000" + + - + input: + bytes: [ 0x20, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #17.00000000" + + - + input: + bytes: [ 0x40, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #18.00000000" + + - + input: + bytes: [ 0x60, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #19.00000000" + + - + input: + bytes: [ 0x80, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #20.00000000" + + - + input: + bytes: [ 0xa0, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #21.00000000" + + - + input: + bytes: [ 0xc0, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #22.00000000" + + - + input: + bytes: [ 0xe0, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #23.00000000" + + - + input: + bytes: [ 0x00, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #24.00000000" + + - + input: + bytes: [ 0x20, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #25.00000000" + + - + input: + bytes: [ 0x40, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #26.00000000" + + - + input: + bytes: [ 0x60, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #27.00000000" + + - + input: + bytes: [ 0x80, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #28.00000000" + + - + input: + bytes: [ 0xa0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #29.00000000" + + - + input: + bytes: [ 0xc0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #30.00000000" + + - + input: + bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #31.00000000" + + - + input: + bytes: [ 0xe0, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p0/z, z7.d" + + - + input: + bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #31.00000000" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #31.00000000" + + - + input: + bytes: [ 0x00, 0xd8, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.h, p0/m, #-0.12500000" + + - + input: + bytes: [ 0x00, 0xd8, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.s, p0/m, #-0.12500000" + + - + input: + bytes: [ 0x00, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.12500000" + + - + input: + bytes: [ 0x20, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.13281250" + + - + input: + bytes: [ 0x40, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.14062500" + + - + input: + bytes: [ 0x60, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.14843750" + + - + input: + bytes: [ 0x80, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.15625000" + + - + input: + bytes: [ 0xa0, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.16406250" + + - + input: + bytes: [ 0xc0, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.17187500" + + - + input: + bytes: [ 0xe0, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.17968750" + + - + input: + bytes: [ 0x00, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.18750000" + + - + input: + bytes: [ 0x20, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.19531250" + + - + input: + bytes: [ 0x40, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.20312500" + + - + input: + bytes: [ 0x60, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.21093750" + + - + input: + bytes: [ 0x80, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.21875000" + + - + input: + bytes: [ 0xa0, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.22656250" + + - + input: + bytes: [ 0xc0, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.23437500" + + - + input: + bytes: [ 0xe0, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.24218750" + + - + input: + bytes: [ 0x00, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.25000000" + + - + input: + bytes: [ 0x20, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.26562500" + + - + input: + bytes: [ 0x40, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.28125000" + + - + input: + bytes: [ 0x60, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.29687500" + + - + input: + bytes: [ 0x80, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.31250000" + + - + input: + bytes: [ 0xa0, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.32812500" + + - + input: + bytes: [ 0xc0, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.34375000" + + - + input: + bytes: [ 0xe0, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.35937500" + + - + input: + bytes: [ 0x00, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.37500000" + + - + input: + bytes: [ 0x20, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.39062500" + + - + input: + bytes: [ 0x40, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.40625000" + + - + input: + bytes: [ 0x60, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.42187500" + + - + input: + bytes: [ 0x80, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.43750000" + + - + input: + bytes: [ 0xa0, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.45312500" + + - + input: + bytes: [ 0xc0, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.46875000" + + - + input: + bytes: [ 0xe0, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.48437500" + + - + input: + bytes: [ 0x00, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.50000000" + + - + input: + bytes: [ 0x20, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.53125000" + + - + input: + bytes: [ 0x40, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.56250000" + + - + input: + bytes: [ 0x60, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.59375000" + + - + input: + bytes: [ 0x80, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.62500000" + + - + input: + bytes: [ 0xa0, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.65625000" + + - + input: + bytes: [ 0xc0, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.68750000" + + - + input: + bytes: [ 0xe0, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.71875000" + + - + input: + bytes: [ 0x00, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.75000000" + + - + input: + bytes: [ 0x20, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.78125000" + + - + input: + bytes: [ 0x40, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.81250000" + + - + input: + bytes: [ 0x60, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.84375000" + + - + input: + bytes: [ 0x80, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.87500000" + + - + input: + bytes: [ 0xa0, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.90625000" + + - + input: + bytes: [ 0xc0, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.93750000" + + - + input: + bytes: [ 0xe0, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.96875000" + + - + input: + bytes: [ 0x00, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.00000000" + + - + input: + bytes: [ 0x20, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.06250000" + + - + input: + bytes: [ 0x40, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.12500000" + + - + input: + bytes: [ 0x60, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.18750000" + + - + input: + bytes: [ 0x80, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.25000000" + + - + input: + bytes: [ 0xa0, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.31250000" + + - + input: + bytes: [ 0xc0, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.37500000" + + - + input: + bytes: [ 0xe0, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.43750000" + + - + input: + bytes: [ 0x00, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.50000000" + + - + input: + bytes: [ 0x20, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.56250000" + + - + input: + bytes: [ 0x40, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.62500000" + + - + input: + bytes: [ 0x60, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.68750000" + + - + input: + bytes: [ 0x80, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.75000000" + + - + input: + bytes: [ 0xa0, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.81250000" + + - + input: + bytes: [ 0xc0, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.87500000" + + - + input: + bytes: [ 0xe0, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.93750000" + + - + input: + bytes: [ 0x00, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.00000000" + + - + input: + bytes: [ 0x20, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.12500000" + + - + input: + bytes: [ 0x40, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.25000000" + + - + input: + bytes: [ 0x60, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.37500000" + + - + input: + bytes: [ 0x80, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.50000000" + + - + input: + bytes: [ 0xa0, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.62500000" + + - + input: + bytes: [ 0xc0, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.75000000" + + - + input: + bytes: [ 0xe0, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.87500000" + + - + input: + bytes: [ 0x00, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.00000000" + + - + input: + bytes: [ 0x20, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.12500000" + + - + input: + bytes: [ 0x40, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.25000000" + + - + input: + bytes: [ 0x60, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.37500000" + + - + input: + bytes: [ 0x80, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.50000000" + + - + input: + bytes: [ 0xa0, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.62500000" + + - + input: + bytes: [ 0xc0, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.75000000" + + - + input: + bytes: [ 0xe0, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.87500000" + + - + input: + bytes: [ 0x00, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-4.00000000" + + - + input: + bytes: [ 0x20, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-4.25000000" + + - + input: + bytes: [ 0x40, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-4.50000000" + + - + input: + bytes: [ 0x60, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-4.75000000" + + - + input: + bytes: [ 0x80, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-5.00000000" + + - + input: + bytes: [ 0xa0, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-5.25000000" + + - + input: + bytes: [ 0xc0, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-5.50000000" + + - + input: + bytes: [ 0xe0, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-5.75000000" + + - + input: + bytes: [ 0x00, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-6.00000000" + + - + input: + bytes: [ 0x20, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-6.25000000" + + - + input: + bytes: [ 0x40, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-6.50000000" + + - + input: + bytes: [ 0x60, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-6.75000000" + + - + input: + bytes: [ 0x80, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-7.00000000" + + - + input: + bytes: [ 0xa0, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-7.25000000" + + - + input: + bytes: [ 0xc0, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-7.50000000" + + - + input: + bytes: [ 0xe0, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-7.75000000" + + - + input: + bytes: [ 0x00, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-8.00000000" + + - + input: + bytes: [ 0x20, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-8.50000000" + + - + input: + bytes: [ 0x40, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-9.00000000" + + - + input: + bytes: [ 0x60, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-9.50000000" + + - + input: + bytes: [ 0x80, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-10.00000000" + + - + input: + bytes: [ 0xa0, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-10.50000000" + + - + input: + bytes: [ 0xc0, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-11.00000000" + + - + input: + bytes: [ 0xe0, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-11.50000000" + + - + input: + bytes: [ 0x00, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-12.00000000" + + - + input: + bytes: [ 0x20, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-12.50000000" + + - + input: + bytes: [ 0x40, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-13.00000000" + + - + input: + bytes: [ 0x60, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-13.50000000" + + - + input: + bytes: [ 0x80, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-14.00000000" + + - + input: + bytes: [ 0xa0, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-14.50000000" + + - + input: + bytes: [ 0xc0, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-15.00000000" + + - + input: + bytes: [ 0xe0, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-15.50000000" + + - + input: + bytes: [ 0x00, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-16.00000000" + + - + input: + bytes: [ 0x20, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-17.00000000" + + - + input: + bytes: [ 0x40, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-18.00000000" + + - + input: + bytes: [ 0x60, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-19.00000000" + + - + input: + bytes: [ 0x80, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-20.00000000" + + - + input: + bytes: [ 0xa0, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-21.00000000" + + - + input: + bytes: [ 0xc0, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-22.00000000" + + - + input: + bytes: [ 0xe0, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-23.00000000" + + - + input: + bytes: [ 0x00, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-24.00000000" + + - + input: + bytes: [ 0x20, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-25.00000000" + + - + input: + bytes: [ 0x40, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-26.00000000" + + - + input: + bytes: [ 0x60, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-27.00000000" + + - + input: + bytes: [ 0x80, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-28.00000000" + + - + input: + bytes: [ 0xa0, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-29.00000000" + + - + input: + bytes: [ 0xc0, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-30.00000000" + + - + input: + bytes: [ 0xe0, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-31.00000000" + + - + input: + bytes: [ 0x00, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.12500000" + + - + input: + bytes: [ 0x20, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.13281250" + + - + input: + bytes: [ 0x40, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.14062500" + + - + input: + bytes: [ 0x60, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.14843750" + + - + input: + bytes: [ 0x80, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.15625000" + + - + input: + bytes: [ 0xa0, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.16406250" + + - + input: + bytes: [ 0xc0, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.17187500" + + - + input: + bytes: [ 0xe0, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.17968750" + + - + input: + bytes: [ 0x00, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.18750000" + + - + input: + bytes: [ 0x20, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.19531250" + + - + input: + bytes: [ 0x40, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.20312500" + + - + input: + bytes: [ 0x60, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.21093750" + + - + input: + bytes: [ 0x80, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.21875000" + + - + input: + bytes: [ 0xa0, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.22656250" + + - + input: + bytes: [ 0xc0, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.23437500" + + - + input: + bytes: [ 0xe0, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.24218750" + + - + input: + bytes: [ 0x00, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.25000000" + + - + input: + bytes: [ 0x20, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.26562500" + + - + input: + bytes: [ 0x40, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.28125000" + + - + input: + bytes: [ 0x60, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.29687500" + + - + input: + bytes: [ 0x80, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.31250000" + + - + input: + bytes: [ 0xa0, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.32812500" + + - + input: + bytes: [ 0xc0, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.34375000" + + - + input: + bytes: [ 0xe0, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.35937500" + + - + input: + bytes: [ 0x00, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.37500000" + + - + input: + bytes: [ 0x20, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.39062500" + + - + input: + bytes: [ 0x40, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.40625000" + + - + input: + bytes: [ 0x60, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.42187500" + + - + input: + bytes: [ 0x80, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.43750000" + + - + input: + bytes: [ 0xa0, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.45312500" + + - + input: + bytes: [ 0xc0, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.46875000" + + - + input: + bytes: [ 0xe0, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.48437500" + + - + input: + bytes: [ 0x00, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.50000000" + + - + input: + bytes: [ 0x20, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.53125000" + + - + input: + bytes: [ 0x40, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.56250000" + + - + input: + bytes: [ 0x60, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.59375000" + + - + input: + bytes: [ 0x80, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.62500000" + + - + input: + bytes: [ 0xa0, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.65625000" + + - + input: + bytes: [ 0xc0, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.68750000" + + - + input: + bytes: [ 0xe0, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.71875000" + + - + input: + bytes: [ 0x00, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.75000000" + + - + input: + bytes: [ 0x20, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.78125000" + + - + input: + bytes: [ 0x40, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.81250000" + + - + input: + bytes: [ 0x60, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.84375000" + + - + input: + bytes: [ 0x80, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.87500000" + + - + input: + bytes: [ 0xa0, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.90625000" + + - + input: + bytes: [ 0xc0, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.93750000" + + - + input: + bytes: [ 0xe0, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.96875000" + + - + input: + bytes: [ 0x00, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.00000000" + + - + input: + bytes: [ 0x20, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.06250000" + + - + input: + bytes: [ 0x40, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.12500000" + + - + input: + bytes: [ 0x60, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.18750000" + + - + input: + bytes: [ 0x80, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.25000000" + + - + input: + bytes: [ 0xa0, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.31250000" + + - + input: + bytes: [ 0xc0, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.37500000" + + - + input: + bytes: [ 0xe0, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.43750000" + + - + input: + bytes: [ 0x00, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.50000000" + + - + input: + bytes: [ 0x20, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.56250000" + + - + input: + bytes: [ 0x40, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.62500000" + + - + input: + bytes: [ 0x60, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.68750000" + + - + input: + bytes: [ 0x80, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.75000000" + + - + input: + bytes: [ 0xa0, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.81250000" + + - + input: + bytes: [ 0xc0, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.87500000" + + - + input: + bytes: [ 0xe0, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.93750000" + + - + input: + bytes: [ 0x00, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.00000000" + + - + input: + bytes: [ 0x20, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.12500000" + + - + input: + bytes: [ 0x40, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.25000000" + + - + input: + bytes: [ 0x60, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.37500000" + + - + input: + bytes: [ 0x80, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.50000000" + + - + input: + bytes: [ 0xa0, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.62500000" + + - + input: + bytes: [ 0xc0, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.75000000" + + - + input: + bytes: [ 0xe0, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.87500000" + + - + input: + bytes: [ 0x00, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.00000000" + + - + input: + bytes: [ 0x20, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.12500000" + + - + input: + bytes: [ 0x40, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.25000000" + + - + input: + bytes: [ 0x60, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.37500000" + + - + input: + bytes: [ 0x80, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.50000000" + + - + input: + bytes: [ 0xa0, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.62500000" + + - + input: + bytes: [ 0xc0, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.75000000" + + - + input: + bytes: [ 0xe0, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.87500000" + + - + input: + bytes: [ 0x00, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #4.00000000" + + - + input: + bytes: [ 0x20, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #4.25000000" + + - + input: + bytes: [ 0x40, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #4.50000000" + + - + input: + bytes: [ 0x60, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #4.75000000" + + - + input: + bytes: [ 0x80, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #5.00000000" + + - + input: + bytes: [ 0xa0, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #5.25000000" + + - + input: + bytes: [ 0xc0, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #5.50000000" + + - + input: + bytes: [ 0xe0, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #5.75000000" + + - + input: + bytes: [ 0x00, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #6.00000000" + + - + input: + bytes: [ 0x20, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #6.25000000" + + - + input: + bytes: [ 0x40, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #6.50000000" + + - + input: + bytes: [ 0x60, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #6.75000000" + + - + input: + bytes: [ 0x80, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #7.00000000" + + - + input: + bytes: [ 0xa0, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #7.25000000" + + - + input: + bytes: [ 0xc0, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #7.50000000" + + - + input: + bytes: [ 0xe0, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #7.75000000" + + - + input: + bytes: [ 0x00, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #8.00000000" + + - + input: + bytes: [ 0x20, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #8.50000000" + + - + input: + bytes: [ 0x40, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #9.00000000" + + - + input: + bytes: [ 0x60, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #9.50000000" + + - + input: + bytes: [ 0x80, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #10.00000000" + + - + input: + bytes: [ 0xa0, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #10.50000000" + + - + input: + bytes: [ 0xc0, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #11.00000000" + + - + input: + bytes: [ 0xe0, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #11.50000000" + + - + input: + bytes: [ 0x00, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #12.00000000" + + - + input: + bytes: [ 0x20, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #12.50000000" + + - + input: + bytes: [ 0x40, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #13.00000000" + + - + input: + bytes: [ 0x60, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #13.50000000" + + - + input: + bytes: [ 0x80, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #14.00000000" + + - + input: + bytes: [ 0xa0, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #14.50000000" + + - + input: + bytes: [ 0xc0, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #15.00000000" + + - + input: + bytes: [ 0xe0, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #15.50000000" + + - + input: + bytes: [ 0x00, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #16.00000000" + + - + input: + bytes: [ 0x20, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #17.00000000" + + - + input: + bytes: [ 0x40, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #18.00000000" + + - + input: + bytes: [ 0x60, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #19.00000000" + + - + input: + bytes: [ 0x80, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #20.00000000" + + - + input: + bytes: [ 0xa0, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #21.00000000" + + - + input: + bytes: [ 0xc0, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #22.00000000" + + - + input: + bytes: [ 0xe0, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #23.00000000" + + - + input: + bytes: [ 0x00, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #24.00000000" + + - + input: + bytes: [ 0x20, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #25.00000000" + + - + input: + bytes: [ 0x40, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #26.00000000" + + - + input: + bytes: [ 0x60, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #27.00000000" + + - + input: + bytes: [ 0x80, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #28.00000000" + + - + input: + bytes: [ 0xa0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #29.00000000" + + - + input: + bytes: [ 0xc0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #30.00000000" + + - + input: + bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #31.00000000" + + - + input: + bytes: [ 0xe0, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p0/z, z7.d" + + - + input: + bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #31.00000000" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #31.00000000" diff --git a/tests/MC/AArch64/SVE/fcvt.s.yaml b/tests/MC/AArch64/SVE/fcvt.s.yaml new file mode 100644 index 0000000000..c1ad594335 --- /dev/null +++ b/tests/MC/AArch64/SVE/fcvt.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x88, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvt z0.h, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xc8, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvt z0.h, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x89, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvt z0.s, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0xca, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvt z0.s, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0xc9, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvt z0.d, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0xcb, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvt z0.d, p0/m, z0.s" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0xa0, 0xcb, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvt z5.d, p0/m, z0.s" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0xa0, 0xcb, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvt z5.d, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0x88, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvt z0.h, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xc8, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvt z0.h, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x89, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvt z0.s, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0xca, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvt z0.s, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0xc9, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvt z0.d, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0xcb, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvt z0.d, p0/m, z0.s" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0xa0, 0xcb, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvt z5.d, p0/m, z0.s" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0xa0, 0xcb, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvt z5.d, p0/m, z0.s" diff --git a/tests/MC/AArch64/SVE/fcvtzs.s.yaml b/tests/MC/AArch64/SVE/fcvtzs.s.yaml new file mode 100644 index 0000000000..0d9fab205e --- /dev/null +++ b/tests/MC/AArch64/SVE/fcvtzs.s.yaml @@ -0,0 +1,220 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x5a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvtzs z0.h, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x5c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvtzs z0.s, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x9c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvtzs z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd8, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvtzs z0.s, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x5e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvtzs z0.d, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0xdc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvtzs z0.d, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xde, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvtzs z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0xa0, 0xde, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvtzs z5.d, p0/m, z0.d" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0xa0, 0xde, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvtzs z5.d, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x5a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtzs z0.h, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x5c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtzs z0.s, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x9c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtzs z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd8, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtzs z0.s, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x5e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtzs z0.d, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0xdc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtzs z0.d, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xde, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtzs z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0xa0, 0xde, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtzs z5.d, p0/m, z0.d" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0xa0, 0xde, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtzs z5.d, p0/m, z0.d" diff --git a/tests/MC/AArch64/SVE/fcvtzu.s.yaml b/tests/MC/AArch64/SVE/fcvtzu.s.yaml new file mode 100644 index 0000000000..0047f6ebcf --- /dev/null +++ b/tests/MC/AArch64/SVE/fcvtzu.s.yaml @@ -0,0 +1,220 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x5b, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvtzu z0.h, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x5d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvtzu z0.s, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x9d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvtzu z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd9, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvtzu z0.s, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvtzu z0.d, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0xdd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvtzu z0.d, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvtzu z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0xa0, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvtzu z5.d, p0/m, z0.d" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0xa0, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fcvtzu z5.d, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x5b, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtzu z0.h, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x5d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtzu z0.s, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x9d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtzu z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd9, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtzu z0.s, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtzu z0.d, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0xdd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtzu z0.d, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtzu z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0xa0, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtzu z5.d, p0/m, z0.d" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0xa0, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtzu z5.d, p0/m, z0.d" diff --git a/tests/MC/AArch64/SVE/fdiv.s.yaml b/tests/MC/AArch64/SVE/fdiv.s.yaml new file mode 100644 index 0000000000..1cf952788f --- /dev/null +++ b/tests/MC/AArch64/SVE/fdiv.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x9f, 0x4d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fdiv z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x8d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fdiv z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xcd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fdiv z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xcd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fdiv z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xcd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fdiv z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0x4d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fdiv z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x8d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fdiv z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xcd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fdiv z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xcd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fdiv z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xcd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fdiv z0.d, p7/m, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/fdivr.s.yaml b/tests/MC/AArch64/SVE/fdivr.s.yaml new file mode 100644 index 0000000000..49e6b9286d --- /dev/null +++ b/tests/MC/AArch64/SVE/fdivr.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x9f, 0x4c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fdivr z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x8c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fdivr z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xcc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fdivr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xcc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fdivr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xcc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fdivr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0x4c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fdivr z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x8c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fdivr z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xcc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fdivr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xcc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fdivr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xcc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fdivr z0.d, p7/m, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/fdup.s.yaml b/tests/MC/AArch64/SVE/fdup.s.yaml new file mode 100644 index 0000000000..9195f8ee50 --- /dev/null +++ b/tests/MC/AArch64/SVE/fdup.s.yaml @@ -0,0 +1,5160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xd8, 0x79, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.h, #-0.12500000" + + - + input: + bytes: [ 0x00, 0xd8, 0xb9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.s, #-0.12500000" + + - + input: + bytes: [ 0x00, 0xd8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.12500000" + + - + input: + bytes: [ 0x20, 0xd8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.13281250" + + - + input: + bytes: [ 0x40, 0xd8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.14062500" + + - + input: + bytes: [ 0x60, 0xd8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.14843750" + + - + input: + bytes: [ 0x80, 0xd8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.15625000" + + - + input: + bytes: [ 0xa0, 0xd8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.16406250" + + - + input: + bytes: [ 0xc0, 0xd8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.17187500" + + - + input: + bytes: [ 0xe0, 0xd8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.17968750" + + - + input: + bytes: [ 0x00, 0xd9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.18750000" + + - + input: + bytes: [ 0x20, 0xd9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.19531250" + + - + input: + bytes: [ 0x40, 0xd9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.20312500" + + - + input: + bytes: [ 0x60, 0xd9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.21093750" + + - + input: + bytes: [ 0x80, 0xd9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.21875000" + + - + input: + bytes: [ 0xa0, 0xd9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.22656250" + + - + input: + bytes: [ 0xc0, 0xd9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.23437500" + + - + input: + bytes: [ 0xe0, 0xd9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.24218750" + + - + input: + bytes: [ 0x00, 0xda, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.25000000" + + - + input: + bytes: [ 0x20, 0xda, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.26562500" + + - + input: + bytes: [ 0x40, 0xda, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.28125000" + + - + input: + bytes: [ 0x60, 0xda, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.29687500" + + - + input: + bytes: [ 0x80, 0xda, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.31250000" + + - + input: + bytes: [ 0xa0, 0xda, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.32812500" + + - + input: + bytes: [ 0xc0, 0xda, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.34375000" + + - + input: + bytes: [ 0xe0, 0xda, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.35937500" + + - + input: + bytes: [ 0x00, 0xdb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.37500000" + + - + input: + bytes: [ 0x20, 0xdb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.39062500" + + - + input: + bytes: [ 0x40, 0xdb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.40625000" + + - + input: + bytes: [ 0x60, 0xdb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.42187500" + + - + input: + bytes: [ 0x80, 0xdb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.43750000" + + - + input: + bytes: [ 0xa0, 0xdb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.45312500" + + - + input: + bytes: [ 0xc0, 0xdb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.46875000" + + - + input: + bytes: [ 0xe0, 0xdb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.48437500" + + - + input: + bytes: [ 0x00, 0xdc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.50000000" + + - + input: + bytes: [ 0x20, 0xdc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.53125000" + + - + input: + bytes: [ 0x40, 0xdc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.56250000" + + - + input: + bytes: [ 0x60, 0xdc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.59375000" + + - + input: + bytes: [ 0x80, 0xdc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.62500000" + + - + input: + bytes: [ 0xa0, 0xdc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.65625000" + + - + input: + bytes: [ 0xc0, 0xdc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.68750000" + + - + input: + bytes: [ 0xe0, 0xdc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.71875000" + + - + input: + bytes: [ 0x00, 0xdd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.75000000" + + - + input: + bytes: [ 0x20, 0xdd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.78125000" + + - + input: + bytes: [ 0x40, 0xdd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.81250000" + + - + input: + bytes: [ 0x60, 0xdd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.84375000" + + - + input: + bytes: [ 0x80, 0xdd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.87500000" + + - + input: + bytes: [ 0xa0, 0xdd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.90625000" + + - + input: + bytes: [ 0xc0, 0xdd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.93750000" + + - + input: + bytes: [ 0xe0, 0xdd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.96875000" + + - + input: + bytes: [ 0x00, 0xde, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.00000000" + + - + input: + bytes: [ 0x20, 0xde, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.06250000" + + - + input: + bytes: [ 0x40, 0xde, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.12500000" + + - + input: + bytes: [ 0x60, 0xde, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.18750000" + + - + input: + bytes: [ 0x80, 0xde, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.25000000" + + - + input: + bytes: [ 0xa0, 0xde, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.31250000" + + - + input: + bytes: [ 0xc0, 0xde, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.37500000" + + - + input: + bytes: [ 0xe0, 0xde, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.43750000" + + - + input: + bytes: [ 0x00, 0xdf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.50000000" + + - + input: + bytes: [ 0x20, 0xdf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.56250000" + + - + input: + bytes: [ 0x40, 0xdf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.62500000" + + - + input: + bytes: [ 0x60, 0xdf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.68750000" + + - + input: + bytes: [ 0x80, 0xdf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.75000000" + + - + input: + bytes: [ 0xa0, 0xdf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.81250000" + + - + input: + bytes: [ 0xc0, 0xdf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.87500000" + + - + input: + bytes: [ 0xe0, 0xdf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.93750000" + + - + input: + bytes: [ 0x00, 0xd0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-2.00000000" + + - + input: + bytes: [ 0x20, 0xd0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-2.12500000" + + - + input: + bytes: [ 0x40, 0xd0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-2.25000000" + + - + input: + bytes: [ 0x60, 0xd0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-2.37500000" + + - + input: + bytes: [ 0x80, 0xd0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-2.50000000" + + - + input: + bytes: [ 0xa0, 0xd0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-2.62500000" + + - + input: + bytes: [ 0xc0, 0xd0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-2.75000000" + + - + input: + bytes: [ 0xe0, 0xd0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-2.87500000" + + - + input: + bytes: [ 0x00, 0xd1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-3.00000000" + + - + input: + bytes: [ 0x20, 0xd1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-3.12500000" + + - + input: + bytes: [ 0x40, 0xd1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-3.25000000" + + - + input: + bytes: [ 0x60, 0xd1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-3.37500000" + + - + input: + bytes: [ 0x80, 0xd1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-3.50000000" + + - + input: + bytes: [ 0xa0, 0xd1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-3.62500000" + + - + input: + bytes: [ 0xc0, 0xd1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-3.75000000" + + - + input: + bytes: [ 0xe0, 0xd1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-3.87500000" + + - + input: + bytes: [ 0x00, 0xd2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-4.00000000" + + - + input: + bytes: [ 0x20, 0xd2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-4.25000000" + + - + input: + bytes: [ 0x40, 0xd2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-4.50000000" + + - + input: + bytes: [ 0x60, 0xd2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-4.75000000" + + - + input: + bytes: [ 0x80, 0xd2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-5.00000000" + + - + input: + bytes: [ 0xa0, 0xd2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-5.25000000" + + - + input: + bytes: [ 0xc0, 0xd2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-5.50000000" + + - + input: + bytes: [ 0xe0, 0xd2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-5.75000000" + + - + input: + bytes: [ 0x00, 0xd3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-6.00000000" + + - + input: + bytes: [ 0x20, 0xd3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-6.25000000" + + - + input: + bytes: [ 0x40, 0xd3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-6.50000000" + + - + input: + bytes: [ 0x60, 0xd3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-6.75000000" + + - + input: + bytes: [ 0x80, 0xd3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-7.00000000" + + - + input: + bytes: [ 0xa0, 0xd3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-7.25000000" + + - + input: + bytes: [ 0xc0, 0xd3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-7.50000000" + + - + input: + bytes: [ 0xe0, 0xd3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-7.75000000" + + - + input: + bytes: [ 0x00, 0xd4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-8.00000000" + + - + input: + bytes: [ 0x20, 0xd4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-8.50000000" + + - + input: + bytes: [ 0x40, 0xd4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-9.00000000" + + - + input: + bytes: [ 0x60, 0xd4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-9.50000000" + + - + input: + bytes: [ 0x80, 0xd4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-10.00000000" + + - + input: + bytes: [ 0xa0, 0xd4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-10.50000000" + + - + input: + bytes: [ 0xc0, 0xd4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-11.00000000" + + - + input: + bytes: [ 0xe0, 0xd4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-11.50000000" + + - + input: + bytes: [ 0x00, 0xd5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-12.00000000" + + - + input: + bytes: [ 0x20, 0xd5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-12.50000000" + + - + input: + bytes: [ 0x40, 0xd5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-13.00000000" + + - + input: + bytes: [ 0x60, 0xd5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-13.50000000" + + - + input: + bytes: [ 0x80, 0xd5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-14.00000000" + + - + input: + bytes: [ 0xa0, 0xd5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-14.50000000" + + - + input: + bytes: [ 0xc0, 0xd5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-15.00000000" + + - + input: + bytes: [ 0xe0, 0xd5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-15.50000000" + + - + input: + bytes: [ 0x00, 0xd6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-16.00000000" + + - + input: + bytes: [ 0x20, 0xd6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-17.00000000" + + - + input: + bytes: [ 0x40, 0xd6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-18.00000000" + + - + input: + bytes: [ 0x60, 0xd6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-19.00000000" + + - + input: + bytes: [ 0x80, 0xd6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-20.00000000" + + - + input: + bytes: [ 0xa0, 0xd6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-21.00000000" + + - + input: + bytes: [ 0xc0, 0xd6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-22.00000000" + + - + input: + bytes: [ 0xe0, 0xd6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-23.00000000" + + - + input: + bytes: [ 0x00, 0xd7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-24.00000000" + + - + input: + bytes: [ 0x20, 0xd7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-25.00000000" + + - + input: + bytes: [ 0x40, 0xd7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-26.00000000" + + - + input: + bytes: [ 0x60, 0xd7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-27.00000000" + + - + input: + bytes: [ 0x80, 0xd7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-28.00000000" + + - + input: + bytes: [ 0xa0, 0xd7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-29.00000000" + + - + input: + bytes: [ 0xc0, 0xd7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-30.00000000" + + - + input: + bytes: [ 0xe0, 0xd7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-31.00000000" + + - + input: + bytes: [ 0x00, 0xc8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.12500000" + + - + input: + bytes: [ 0x20, 0xc8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.13281250" + + - + input: + bytes: [ 0x40, 0xc8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.14062500" + + - + input: + bytes: [ 0x60, 0xc8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.14843750" + + - + input: + bytes: [ 0x80, 0xc8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.15625000" + + - + input: + bytes: [ 0xa0, 0xc8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.16406250" + + - + input: + bytes: [ 0xc0, 0xc8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.17187500" + + - + input: + bytes: [ 0xe0, 0xc8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.17968750" + + - + input: + bytes: [ 0x00, 0xc9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.18750000" + + - + input: + bytes: [ 0x20, 0xc9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.19531250" + + - + input: + bytes: [ 0x40, 0xc9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.20312500" + + - + input: + bytes: [ 0x60, 0xc9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.21093750" + + - + input: + bytes: [ 0x80, 0xc9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.21875000" + + - + input: + bytes: [ 0xa0, 0xc9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.22656250" + + - + input: + bytes: [ 0xc0, 0xc9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.23437500" + + - + input: + bytes: [ 0xe0, 0xc9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.24218750" + + - + input: + bytes: [ 0x00, 0xca, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.25000000" + + - + input: + bytes: [ 0x20, 0xca, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.26562500" + + - + input: + bytes: [ 0x40, 0xca, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.28125000" + + - + input: + bytes: [ 0x60, 0xca, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.29687500" + + - + input: + bytes: [ 0x80, 0xca, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.31250000" + + - + input: + bytes: [ 0xa0, 0xca, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.32812500" + + - + input: + bytes: [ 0xc0, 0xca, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.34375000" + + - + input: + bytes: [ 0xe0, 0xca, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.35937500" + + - + input: + bytes: [ 0x00, 0xcb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.37500000" + + - + input: + bytes: [ 0x20, 0xcb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.39062500" + + - + input: + bytes: [ 0x40, 0xcb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.40625000" + + - + input: + bytes: [ 0x60, 0xcb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.42187500" + + - + input: + bytes: [ 0x80, 0xcb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.43750000" + + - + input: + bytes: [ 0xa0, 0xcb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.45312500" + + - + input: + bytes: [ 0xc0, 0xcb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.46875000" + + - + input: + bytes: [ 0xe0, 0xcb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.48437500" + + - + input: + bytes: [ 0x00, 0xcc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.50000000" + + - + input: + bytes: [ 0x20, 0xcc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.53125000" + + - + input: + bytes: [ 0x40, 0xcc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.56250000" + + - + input: + bytes: [ 0x60, 0xcc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.59375000" + + - + input: + bytes: [ 0x80, 0xcc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.62500000" + + - + input: + bytes: [ 0xa0, 0xcc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.65625000" + + - + input: + bytes: [ 0xc0, 0xcc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.68750000" + + - + input: + bytes: [ 0xe0, 0xcc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.71875000" + + - + input: + bytes: [ 0x00, 0xcd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.75000000" + + - + input: + bytes: [ 0x20, 0xcd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.78125000" + + - + input: + bytes: [ 0x40, 0xcd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.81250000" + + - + input: + bytes: [ 0x60, 0xcd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.84375000" + + - + input: + bytes: [ 0x80, 0xcd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.87500000" + + - + input: + bytes: [ 0xa0, 0xcd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.90625000" + + - + input: + bytes: [ 0xc0, 0xcd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.93750000" + + - + input: + bytes: [ 0xe0, 0xcd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.96875000" + + - + input: + bytes: [ 0x00, 0xce, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.00000000" + + - + input: + bytes: [ 0x20, 0xce, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.06250000" + + - + input: + bytes: [ 0x40, 0xce, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.12500000" + + - + input: + bytes: [ 0x60, 0xce, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.18750000" + + - + input: + bytes: [ 0x80, 0xce, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.25000000" + + - + input: + bytes: [ 0xa0, 0xce, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.31250000" + + - + input: + bytes: [ 0xc0, 0xce, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.37500000" + + - + input: + bytes: [ 0xe0, 0xce, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.43750000" + + - + input: + bytes: [ 0x00, 0xcf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.50000000" + + - + input: + bytes: [ 0x20, 0xcf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.56250000" + + - + input: + bytes: [ 0x40, 0xcf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.62500000" + + - + input: + bytes: [ 0x60, 0xcf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.68750000" + + - + input: + bytes: [ 0x80, 0xcf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.75000000" + + - + input: + bytes: [ 0xa0, 0xcf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.81250000" + + - + input: + bytes: [ 0xc0, 0xcf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.87500000" + + - + input: + bytes: [ 0xe0, 0xcf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.93750000" + + - + input: + bytes: [ 0x00, 0xc0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #2.00000000" + + - + input: + bytes: [ 0x20, 0xc0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #2.12500000" + + - + input: + bytes: [ 0x40, 0xc0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #2.25000000" + + - + input: + bytes: [ 0x60, 0xc0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #2.37500000" + + - + input: + bytes: [ 0x80, 0xc0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #2.50000000" + + - + input: + bytes: [ 0xa0, 0xc0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #2.62500000" + + - + input: + bytes: [ 0xc0, 0xc0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #2.75000000" + + - + input: + bytes: [ 0xe0, 0xc0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #2.87500000" + + - + input: + bytes: [ 0x00, 0xc1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #3.00000000" + + - + input: + bytes: [ 0x20, 0xc1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #3.12500000" + + - + input: + bytes: [ 0x40, 0xc1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #3.25000000" + + - + input: + bytes: [ 0x60, 0xc1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #3.37500000" + + - + input: + bytes: [ 0x80, 0xc1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #3.50000000" + + - + input: + bytes: [ 0xa0, 0xc1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #3.62500000" + + - + input: + bytes: [ 0xc0, 0xc1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #3.75000000" + + - + input: + bytes: [ 0xe0, 0xc1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #3.87500000" + + - + input: + bytes: [ 0x00, 0xc2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #4.00000000" + + - + input: + bytes: [ 0x20, 0xc2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #4.25000000" + + - + input: + bytes: [ 0x40, 0xc2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #4.50000000" + + - + input: + bytes: [ 0x60, 0xc2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #4.75000000" + + - + input: + bytes: [ 0x80, 0xc2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #5.00000000" + + - + input: + bytes: [ 0xa0, 0xc2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #5.25000000" + + - + input: + bytes: [ 0xc0, 0xc2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #5.50000000" + + - + input: + bytes: [ 0xe0, 0xc2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #5.75000000" + + - + input: + bytes: [ 0x00, 0xc3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #6.00000000" + + - + input: + bytes: [ 0x20, 0xc3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #6.25000000" + + - + input: + bytes: [ 0x40, 0xc3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #6.50000000" + + - + input: + bytes: [ 0x60, 0xc3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #6.75000000" + + - + input: + bytes: [ 0x80, 0xc3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #7.00000000" + + - + input: + bytes: [ 0xa0, 0xc3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #7.25000000" + + - + input: + bytes: [ 0xc0, 0xc3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #7.50000000" + + - + input: + bytes: [ 0xe0, 0xc3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #7.75000000" + + - + input: + bytes: [ 0x00, 0xc4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #8.00000000" + + - + input: + bytes: [ 0x20, 0xc4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #8.50000000" + + - + input: + bytes: [ 0x40, 0xc4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #9.00000000" + + - + input: + bytes: [ 0x60, 0xc4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #9.50000000" + + - + input: + bytes: [ 0x80, 0xc4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #10.00000000" + + - + input: + bytes: [ 0xa0, 0xc4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #10.50000000" + + - + input: + bytes: [ 0xc0, 0xc4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #11.00000000" + + - + input: + bytes: [ 0xe0, 0xc4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #11.50000000" + + - + input: + bytes: [ 0x00, 0xc5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #12.00000000" + + - + input: + bytes: [ 0x20, 0xc5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #12.50000000" + + - + input: + bytes: [ 0x40, 0xc5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #13.00000000" + + - + input: + bytes: [ 0x60, 0xc5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #13.50000000" + + - + input: + bytes: [ 0x80, 0xc5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #14.00000000" + + - + input: + bytes: [ 0xa0, 0xc5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #14.50000000" + + - + input: + bytes: [ 0xc0, 0xc5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #15.00000000" + + - + input: + bytes: [ 0xe0, 0xc5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #15.50000000" + + - + input: + bytes: [ 0x00, 0xc6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #16.00000000" + + - + input: + bytes: [ 0x20, 0xc6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #17.00000000" + + - + input: + bytes: [ 0x40, 0xc6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #18.00000000" + + - + input: + bytes: [ 0x60, 0xc6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #19.00000000" + + - + input: + bytes: [ 0x80, 0xc6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #20.00000000" + + - + input: + bytes: [ 0xa0, 0xc6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #21.00000000" + + - + input: + bytes: [ 0xc0, 0xc6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #22.00000000" + + - + input: + bytes: [ 0xe0, 0xc6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #23.00000000" + + - + input: + bytes: [ 0x00, 0xc7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #24.00000000" + + - + input: + bytes: [ 0x20, 0xc7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #25.00000000" + + - + input: + bytes: [ 0x40, 0xc7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #26.00000000" + + - + input: + bytes: [ 0x60, 0xc7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #27.00000000" + + - + input: + bytes: [ 0x80, 0xc7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #28.00000000" + + - + input: + bytes: [ 0xa0, 0xc7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #29.00000000" + + - + input: + bytes: [ 0xc0, 0xc7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #30.00000000" + + - + input: + bytes: [ 0xe0, 0xc7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #31.00000000" + + - + input: + bytes: [ 0x00, 0xd8, 0x79, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.h, #-0.12500000" + + - + input: + bytes: [ 0x00, 0xd8, 0xb9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.s, #-0.12500000" + + - + input: + bytes: [ 0x00, 0xd8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.12500000" + + - + input: + bytes: [ 0x20, 0xd8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.13281250" + + - + input: + bytes: [ 0x40, 0xd8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.14062500" + + - + input: + bytes: [ 0x60, 0xd8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.14843750" + + - + input: + bytes: [ 0x80, 0xd8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.15625000" + + - + input: + bytes: [ 0xa0, 0xd8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.16406250" + + - + input: + bytes: [ 0xc0, 0xd8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.17187500" + + - + input: + bytes: [ 0xe0, 0xd8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.17968750" + + - + input: + bytes: [ 0x00, 0xd9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.18750000" + + - + input: + bytes: [ 0x20, 0xd9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.19531250" + + - + input: + bytes: [ 0x40, 0xd9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.20312500" + + - + input: + bytes: [ 0x60, 0xd9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.21093750" + + - + input: + bytes: [ 0x80, 0xd9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.21875000" + + - + input: + bytes: [ 0xa0, 0xd9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.22656250" + + - + input: + bytes: [ 0xc0, 0xd9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.23437500" + + - + input: + bytes: [ 0xe0, 0xd9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.24218750" + + - + input: + bytes: [ 0x00, 0xda, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.25000000" + + - + input: + bytes: [ 0x20, 0xda, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.26562500" + + - + input: + bytes: [ 0x40, 0xda, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.28125000" + + - + input: + bytes: [ 0x60, 0xda, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.29687500" + + - + input: + bytes: [ 0x80, 0xda, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.31250000" + + - + input: + bytes: [ 0xa0, 0xda, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.32812500" + + - + input: + bytes: [ 0xc0, 0xda, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.34375000" + + - + input: + bytes: [ 0xe0, 0xda, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.35937500" + + - + input: + bytes: [ 0x00, 0xdb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.37500000" + + - + input: + bytes: [ 0x20, 0xdb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.39062500" + + - + input: + bytes: [ 0x40, 0xdb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.40625000" + + - + input: + bytes: [ 0x60, 0xdb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.42187500" + + - + input: + bytes: [ 0x80, 0xdb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.43750000" + + - + input: + bytes: [ 0xa0, 0xdb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.45312500" + + - + input: + bytes: [ 0xc0, 0xdb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.46875000" + + - + input: + bytes: [ 0xe0, 0xdb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.48437500" + + - + input: + bytes: [ 0x00, 0xdc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.50000000" + + - + input: + bytes: [ 0x20, 0xdc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.53125000" + + - + input: + bytes: [ 0x40, 0xdc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.56250000" + + - + input: + bytes: [ 0x60, 0xdc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.59375000" + + - + input: + bytes: [ 0x80, 0xdc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.62500000" + + - + input: + bytes: [ 0xa0, 0xdc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.65625000" + + - + input: + bytes: [ 0xc0, 0xdc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.68750000" + + - + input: + bytes: [ 0xe0, 0xdc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.71875000" + + - + input: + bytes: [ 0x00, 0xdd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.75000000" + + - + input: + bytes: [ 0x20, 0xdd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.78125000" + + - + input: + bytes: [ 0x40, 0xdd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.81250000" + + - + input: + bytes: [ 0x60, 0xdd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.84375000" + + - + input: + bytes: [ 0x80, 0xdd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.87500000" + + - + input: + bytes: [ 0xa0, 0xdd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.90625000" + + - + input: + bytes: [ 0xc0, 0xdd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.93750000" + + - + input: + bytes: [ 0xe0, 0xdd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.96875000" + + - + input: + bytes: [ 0x00, 0xde, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.00000000" + + - + input: + bytes: [ 0x20, 0xde, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.06250000" + + - + input: + bytes: [ 0x40, 0xde, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.12500000" + + - + input: + bytes: [ 0x60, 0xde, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.18750000" + + - + input: + bytes: [ 0x80, 0xde, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.25000000" + + - + input: + bytes: [ 0xa0, 0xde, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.31250000" + + - + input: + bytes: [ 0xc0, 0xde, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.37500000" + + - + input: + bytes: [ 0xe0, 0xde, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.43750000" + + - + input: + bytes: [ 0x00, 0xdf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.50000000" + + - + input: + bytes: [ 0x20, 0xdf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.56250000" + + - + input: + bytes: [ 0x40, 0xdf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.62500000" + + - + input: + bytes: [ 0x60, 0xdf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.68750000" + + - + input: + bytes: [ 0x80, 0xdf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.75000000" + + - + input: + bytes: [ 0xa0, 0xdf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.81250000" + + - + input: + bytes: [ 0xc0, 0xdf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.87500000" + + - + input: + bytes: [ 0xe0, 0xdf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-1.93750000" + + - + input: + bytes: [ 0x00, 0xd0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-2.00000000" + + - + input: + bytes: [ 0x20, 0xd0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-2.12500000" + + - + input: + bytes: [ 0x40, 0xd0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-2.25000000" + + - + input: + bytes: [ 0x60, 0xd0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-2.37500000" + + - + input: + bytes: [ 0x80, 0xd0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-2.50000000" + + - + input: + bytes: [ 0xa0, 0xd0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-2.62500000" + + - + input: + bytes: [ 0xc0, 0xd0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-2.75000000" + + - + input: + bytes: [ 0xe0, 0xd0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-2.87500000" + + - + input: + bytes: [ 0x00, 0xd1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-3.00000000" + + - + input: + bytes: [ 0x20, 0xd1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-3.12500000" + + - + input: + bytes: [ 0x40, 0xd1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-3.25000000" + + - + input: + bytes: [ 0x60, 0xd1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-3.37500000" + + - + input: + bytes: [ 0x80, 0xd1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-3.50000000" + + - + input: + bytes: [ 0xa0, 0xd1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-3.62500000" + + - + input: + bytes: [ 0xc0, 0xd1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-3.75000000" + + - + input: + bytes: [ 0xe0, 0xd1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-3.87500000" + + - + input: + bytes: [ 0x00, 0xd2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-4.00000000" + + - + input: + bytes: [ 0x20, 0xd2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-4.25000000" + + - + input: + bytes: [ 0x40, 0xd2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-4.50000000" + + - + input: + bytes: [ 0x60, 0xd2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-4.75000000" + + - + input: + bytes: [ 0x80, 0xd2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-5.00000000" + + - + input: + bytes: [ 0xa0, 0xd2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-5.25000000" + + - + input: + bytes: [ 0xc0, 0xd2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-5.50000000" + + - + input: + bytes: [ 0xe0, 0xd2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-5.75000000" + + - + input: + bytes: [ 0x00, 0xd3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-6.00000000" + + - + input: + bytes: [ 0x20, 0xd3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-6.25000000" + + - + input: + bytes: [ 0x40, 0xd3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-6.50000000" + + - + input: + bytes: [ 0x60, 0xd3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-6.75000000" + + - + input: + bytes: [ 0x80, 0xd3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-7.00000000" + + - + input: + bytes: [ 0xa0, 0xd3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-7.25000000" + + - + input: + bytes: [ 0xc0, 0xd3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-7.50000000" + + - + input: + bytes: [ 0xe0, 0xd3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-7.75000000" + + - + input: + bytes: [ 0x00, 0xd4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-8.00000000" + + - + input: + bytes: [ 0x20, 0xd4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-8.50000000" + + - + input: + bytes: [ 0x40, 0xd4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-9.00000000" + + - + input: + bytes: [ 0x60, 0xd4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-9.50000000" + + - + input: + bytes: [ 0x80, 0xd4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-10.00000000" + + - + input: + bytes: [ 0xa0, 0xd4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-10.50000000" + + - + input: + bytes: [ 0xc0, 0xd4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-11.00000000" + + - + input: + bytes: [ 0xe0, 0xd4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-11.50000000" + + - + input: + bytes: [ 0x00, 0xd5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-12.00000000" + + - + input: + bytes: [ 0x20, 0xd5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-12.50000000" + + - + input: + bytes: [ 0x40, 0xd5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-13.00000000" + + - + input: + bytes: [ 0x60, 0xd5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-13.50000000" + + - + input: + bytes: [ 0x80, 0xd5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-14.00000000" + + - + input: + bytes: [ 0xa0, 0xd5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-14.50000000" + + - + input: + bytes: [ 0xc0, 0xd5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-15.00000000" + + - + input: + bytes: [ 0xe0, 0xd5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-15.50000000" + + - + input: + bytes: [ 0x00, 0xd6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-16.00000000" + + - + input: + bytes: [ 0x20, 0xd6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-17.00000000" + + - + input: + bytes: [ 0x40, 0xd6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-18.00000000" + + - + input: + bytes: [ 0x60, 0xd6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-19.00000000" + + - + input: + bytes: [ 0x80, 0xd6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-20.00000000" + + - + input: + bytes: [ 0xa0, 0xd6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-21.00000000" + + - + input: + bytes: [ 0xc0, 0xd6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-22.00000000" + + - + input: + bytes: [ 0xe0, 0xd6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-23.00000000" + + - + input: + bytes: [ 0x00, 0xd7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-24.00000000" + + - + input: + bytes: [ 0x20, 0xd7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-25.00000000" + + - + input: + bytes: [ 0x40, 0xd7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-26.00000000" + + - + input: + bytes: [ 0x60, 0xd7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-27.00000000" + + - + input: + bytes: [ 0x80, 0xd7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-28.00000000" + + - + input: + bytes: [ 0xa0, 0xd7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-29.00000000" + + - + input: + bytes: [ 0xc0, 0xd7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-30.00000000" + + - + input: + bytes: [ 0xe0, 0xd7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-31.00000000" + + - + input: + bytes: [ 0x00, 0xc8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.12500000" + + - + input: + bytes: [ 0x20, 0xc8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.13281250" + + - + input: + bytes: [ 0x40, 0xc8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.14062500" + + - + input: + bytes: [ 0x60, 0xc8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.14843750" + + - + input: + bytes: [ 0x80, 0xc8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.15625000" + + - + input: + bytes: [ 0xa0, 0xc8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.16406250" + + - + input: + bytes: [ 0xc0, 0xc8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.17187500" + + - + input: + bytes: [ 0xe0, 0xc8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.17968750" + + - + input: + bytes: [ 0x00, 0xc9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.18750000" + + - + input: + bytes: [ 0x20, 0xc9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.19531250" + + - + input: + bytes: [ 0x40, 0xc9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.20312500" + + - + input: + bytes: [ 0x60, 0xc9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.21093750" + + - + input: + bytes: [ 0x80, 0xc9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.21875000" + + - + input: + bytes: [ 0xa0, 0xc9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.22656250" + + - + input: + bytes: [ 0xc0, 0xc9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.23437500" + + - + input: + bytes: [ 0xe0, 0xc9, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.24218750" + + - + input: + bytes: [ 0x00, 0xca, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.25000000" + + - + input: + bytes: [ 0x20, 0xca, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.26562500" + + - + input: + bytes: [ 0x40, 0xca, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.28125000" + + - + input: + bytes: [ 0x60, 0xca, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.29687500" + + - + input: + bytes: [ 0x80, 0xca, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.31250000" + + - + input: + bytes: [ 0xa0, 0xca, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.32812500" + + - + input: + bytes: [ 0xc0, 0xca, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.34375000" + + - + input: + bytes: [ 0xe0, 0xca, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.35937500" + + - + input: + bytes: [ 0x00, 0xcb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.37500000" + + - + input: + bytes: [ 0x20, 0xcb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.39062500" + + - + input: + bytes: [ 0x40, 0xcb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.40625000" + + - + input: + bytes: [ 0x60, 0xcb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.42187500" + + - + input: + bytes: [ 0x80, 0xcb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.43750000" + + - + input: + bytes: [ 0xa0, 0xcb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.45312500" + + - + input: + bytes: [ 0xc0, 0xcb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.46875000" + + - + input: + bytes: [ 0xe0, 0xcb, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.48437500" + + - + input: + bytes: [ 0x00, 0xcc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.50000000" + + - + input: + bytes: [ 0x20, 0xcc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.53125000" + + - + input: + bytes: [ 0x40, 0xcc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.56250000" + + - + input: + bytes: [ 0x60, 0xcc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.59375000" + + - + input: + bytes: [ 0x80, 0xcc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.62500000" + + - + input: + bytes: [ 0xa0, 0xcc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.65625000" + + - + input: + bytes: [ 0xc0, 0xcc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.68750000" + + - + input: + bytes: [ 0xe0, 0xcc, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.71875000" + + - + input: + bytes: [ 0x00, 0xcd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.75000000" + + - + input: + bytes: [ 0x20, 0xcd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.78125000" + + - + input: + bytes: [ 0x40, 0xcd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.81250000" + + - + input: + bytes: [ 0x60, 0xcd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.84375000" + + - + input: + bytes: [ 0x80, 0xcd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.87500000" + + - + input: + bytes: [ 0xa0, 0xcd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.90625000" + + - + input: + bytes: [ 0xc0, 0xcd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.93750000" + + - + input: + bytes: [ 0xe0, 0xcd, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #0.96875000" + + - + input: + bytes: [ 0x00, 0xce, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.00000000" + + - + input: + bytes: [ 0x20, 0xce, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.06250000" + + - + input: + bytes: [ 0x40, 0xce, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.12500000" + + - + input: + bytes: [ 0x60, 0xce, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.18750000" + + - + input: + bytes: [ 0x80, 0xce, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.25000000" + + - + input: + bytes: [ 0xa0, 0xce, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.31250000" + + - + input: + bytes: [ 0xc0, 0xce, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.37500000" + + - + input: + bytes: [ 0xe0, 0xce, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.43750000" + + - + input: + bytes: [ 0x00, 0xcf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.50000000" + + - + input: + bytes: [ 0x20, 0xcf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.56250000" + + - + input: + bytes: [ 0x40, 0xcf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.62500000" + + - + input: + bytes: [ 0x60, 0xcf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.68750000" + + - + input: + bytes: [ 0x80, 0xcf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.75000000" + + - + input: + bytes: [ 0xa0, 0xcf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.81250000" + + - + input: + bytes: [ 0xc0, 0xcf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.87500000" + + - + input: + bytes: [ 0xe0, 0xcf, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #1.93750000" + + - + input: + bytes: [ 0x00, 0xc0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #2.00000000" + + - + input: + bytes: [ 0x20, 0xc0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #2.12500000" + + - + input: + bytes: [ 0x40, 0xc0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #2.25000000" + + - + input: + bytes: [ 0x60, 0xc0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #2.37500000" + + - + input: + bytes: [ 0x80, 0xc0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #2.50000000" + + - + input: + bytes: [ 0xa0, 0xc0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #2.62500000" + + - + input: + bytes: [ 0xc0, 0xc0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #2.75000000" + + - + input: + bytes: [ 0xe0, 0xc0, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #2.87500000" + + - + input: + bytes: [ 0x00, 0xc1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #3.00000000" + + - + input: + bytes: [ 0x20, 0xc1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #3.12500000" + + - + input: + bytes: [ 0x40, 0xc1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #3.25000000" + + - + input: + bytes: [ 0x60, 0xc1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #3.37500000" + + - + input: + bytes: [ 0x80, 0xc1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #3.50000000" + + - + input: + bytes: [ 0xa0, 0xc1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #3.62500000" + + - + input: + bytes: [ 0xc0, 0xc1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #3.75000000" + + - + input: + bytes: [ 0xe0, 0xc1, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #3.87500000" + + - + input: + bytes: [ 0x00, 0xc2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #4.00000000" + + - + input: + bytes: [ 0x20, 0xc2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #4.25000000" + + - + input: + bytes: [ 0x40, 0xc2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #4.50000000" + + - + input: + bytes: [ 0x60, 0xc2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #4.75000000" + + - + input: + bytes: [ 0x80, 0xc2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #5.00000000" + + - + input: + bytes: [ 0xa0, 0xc2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #5.25000000" + + - + input: + bytes: [ 0xc0, 0xc2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #5.50000000" + + - + input: + bytes: [ 0xe0, 0xc2, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #5.75000000" + + - + input: + bytes: [ 0x00, 0xc3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #6.00000000" + + - + input: + bytes: [ 0x20, 0xc3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #6.25000000" + + - + input: + bytes: [ 0x40, 0xc3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #6.50000000" + + - + input: + bytes: [ 0x60, 0xc3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #6.75000000" + + - + input: + bytes: [ 0x80, 0xc3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #7.00000000" + + - + input: + bytes: [ 0xa0, 0xc3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #7.25000000" + + - + input: + bytes: [ 0xc0, 0xc3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #7.50000000" + + - + input: + bytes: [ 0xe0, 0xc3, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #7.75000000" + + - + input: + bytes: [ 0x00, 0xc4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #8.00000000" + + - + input: + bytes: [ 0x20, 0xc4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #8.50000000" + + - + input: + bytes: [ 0x40, 0xc4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #9.00000000" + + - + input: + bytes: [ 0x60, 0xc4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #9.50000000" + + - + input: + bytes: [ 0x80, 0xc4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #10.00000000" + + - + input: + bytes: [ 0xa0, 0xc4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #10.50000000" + + - + input: + bytes: [ 0xc0, 0xc4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #11.00000000" + + - + input: + bytes: [ 0xe0, 0xc4, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #11.50000000" + + - + input: + bytes: [ 0x00, 0xc5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #12.00000000" + + - + input: + bytes: [ 0x20, 0xc5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #12.50000000" + + - + input: + bytes: [ 0x40, 0xc5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #13.00000000" + + - + input: + bytes: [ 0x60, 0xc5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #13.50000000" + + - + input: + bytes: [ 0x80, 0xc5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #14.00000000" + + - + input: + bytes: [ 0xa0, 0xc5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #14.50000000" + + - + input: + bytes: [ 0xc0, 0xc5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #15.00000000" + + - + input: + bytes: [ 0xe0, 0xc5, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #15.50000000" + + - + input: + bytes: [ 0x00, 0xc6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #16.00000000" + + - + input: + bytes: [ 0x20, 0xc6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #17.00000000" + + - + input: + bytes: [ 0x40, 0xc6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #18.00000000" + + - + input: + bytes: [ 0x60, 0xc6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #19.00000000" + + - + input: + bytes: [ 0x80, 0xc6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #20.00000000" + + - + input: + bytes: [ 0xa0, 0xc6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #21.00000000" + + - + input: + bytes: [ 0xc0, 0xc6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #22.00000000" + + - + input: + bytes: [ 0xe0, 0xc6, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #23.00000000" + + - + input: + bytes: [ 0x00, 0xc7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #24.00000000" + + - + input: + bytes: [ 0x20, 0xc7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #25.00000000" + + - + input: + bytes: [ 0x40, 0xc7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #26.00000000" + + - + input: + bytes: [ 0x60, 0xc7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #27.00000000" + + - + input: + bytes: [ 0x80, 0xc7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #28.00000000" + + - + input: + bytes: [ 0xa0, 0xc7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #29.00000000" + + - + input: + bytes: [ 0xc0, 0xc7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #30.00000000" + + - + input: + bytes: [ 0xe0, 0xc7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #31.00000000" diff --git a/tests/MC/AArch64/SVE/fexpa.s.yaml b/tests/MC/AArch64/SVE/fexpa.s.yaml new file mode 100644 index 0000000000..e1477c8143 --- /dev/null +++ b/tests/MC/AArch64/SVE/fexpa.s.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xbb, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fexpa z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0xbb, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fexpa z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0xbb, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fexpa z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/fmad.s.yaml b/tests/MC/AArch64/SVE/fmad.s.yaml new file mode 100644 index 0000000000..d28664c438 --- /dev/null +++ b/tests/MC/AArch64/SVE/fmad.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x9c, 0x7f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmad z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x9c, 0xbf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmad z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x9c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmad z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0x9c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmad z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x9c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmad z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x9c, 0x7f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmad z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x9c, 0xbf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmad z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x9c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmad z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0x9c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmad z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x9c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmad z0.d, p7/m, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE/fmax.s.yaml b/tests/MC/AArch64/SVE/fmax.s.yaml new file mode 100644 index 0000000000..68997a3299 --- /dev/null +++ b/tests/MC/AArch64/SVE/fmax.s.yaml @@ -0,0 +1,360 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x5e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmax z0.h, p0/m, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0x5e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmax z0.h, p0/m, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0x9e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmax z0.s, p0/m, z0.s, #0.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0xde, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmax z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmax z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x9e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmax z31.s, p7/m, z31.s, #1.0" + + - + input: + bytes: [ 0x00, 0x80, 0xde, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmax z0.d, p0/m, z0.d, #0.0" + + - + input: + bytes: [ 0xe0, 0x9f, 0x46, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmax z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x86, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmax z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmax z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p0/z, z7.d" + + - + input: + bytes: [ 0x00, 0x80, 0xde, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmax z0.d, p0/m, z0.d, #0.0" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0x80, 0xde, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmax z0.d, p0/m, z0.d, #0.0" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmax z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmax z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0x00, 0x80, 0x5e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmax z0.h, p0/m, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0x5e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmax z0.h, p0/m, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0x9e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmax z0.s, p0/m, z0.s, #0.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0xde, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmax z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmax z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x9e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmax z31.s, p7/m, z31.s, #1.0" + + - + input: + bytes: [ 0x00, 0x80, 0xde, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmax z0.d, p0/m, z0.d, #0.0" + + - + input: + bytes: [ 0xe0, 0x9f, 0x46, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmax z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x86, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmax z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmax z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p0/z, z7.d" + + - + input: + bytes: [ 0x00, 0x80, 0xde, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmax z0.d, p0/m, z0.d, #0.0" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0x80, 0xde, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmax z0.d, p0/m, z0.d, #0.0" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmax z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmax z0.d, p7/m, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/fmaxnm.s.yaml b/tests/MC/AArch64/SVE/fmaxnm.s.yaml new file mode 100644 index 0000000000..bd3edffa33 --- /dev/null +++ b/tests/MC/AArch64/SVE/fmaxnm.s.yaml @@ -0,0 +1,380 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x5c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxnm z0.h, p0/m, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0x5c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxnm z0.h, p0/m, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0x9c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxnm z0.s, p0/m, z0.s, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0xdc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxnm z0.d, p0/m, z0.d, #0.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxnm z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxnm z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x9c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxnm z31.s, p7/m, z31.s, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxnm z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x9f, 0x44, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxnm z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x84, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxnm z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc4, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxnm z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p7/z, z6.d" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxnm z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxnm z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc4, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxnm z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc4, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxnm z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0x00, 0x80, 0x5c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnm z0.h, p0/m, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0x5c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnm z0.h, p0/m, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0x9c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnm z0.s, p0/m, z0.s, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0xdc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnm z0.d, p0/m, z0.d, #0.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnm z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnm z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x9c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnm z31.s, p7/m, z31.s, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnm z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x9f, 0x44, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnm z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x84, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnm z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc4, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnm z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p7/z, z6.d" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnm z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnm z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc4, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnm z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc4, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnm z0.d, p7/m, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/fmaxnmv.s.yaml b/tests/MC/AArch64/SVE/fmaxnmv.s.yaml new file mode 100644 index 0000000000..9780894f0c --- /dev/null +++ b/tests/MC/AArch64/SVE/fmaxnmv.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x3f, 0x44, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxnmv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x84, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxnmv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xc4, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxnmv d0, p7, z31.d" + + - + input: + bytes: [ 0xe0, 0x3f, 0x44, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnmv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x84, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnmv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xc4, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnmv d0, p7, z31.d" diff --git a/tests/MC/AArch64/SVE/fmaxv.s.yaml b/tests/MC/AArch64/SVE/fmaxv.s.yaml new file mode 100644 index 0000000000..4b3777d073 --- /dev/null +++ b/tests/MC/AArch64/SVE/fmaxv.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x3f, 0x46, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x86, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xc6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmaxv d0, p7, z31.d" + + - + input: + bytes: [ 0xe0, 0x3f, 0x46, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x86, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xc6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxv d0, p7, z31.d" diff --git a/tests/MC/AArch64/SVE/fmin.s.yaml b/tests/MC/AArch64/SVE/fmin.s.yaml new file mode 100644 index 0000000000..e24c8d5636 --- /dev/null +++ b/tests/MC/AArch64/SVE/fmin.s.yaml @@ -0,0 +1,380 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmin z0.h, p0/m, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmin z0.h, p0/m, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0x9f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmin z0.s, p0/m, z0.s, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmin z0.d, p0/m, z0.d, #0.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmin z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmin z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x9f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmin z31.s, p7/m, z31.s, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmin z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x9f, 0x47, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmin z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x87, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmin z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmin z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p7/z, z6.d" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmin z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmin z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmin z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmin z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0x00, 0x80, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmin z0.h, p0/m, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmin z0.h, p0/m, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0x9f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmin z0.s, p0/m, z0.s, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmin z0.d, p0/m, z0.d, #0.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmin z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmin z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x9f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmin z31.s, p7/m, z31.s, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmin z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x9f, 0x47, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmin z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x87, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmin z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmin z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p7/z, z6.d" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmin z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmin z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmin z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmin z0.d, p7/m, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/fminnm.s.yaml b/tests/MC/AArch64/SVE/fminnm.s.yaml new file mode 100644 index 0000000000..32349e7b6f --- /dev/null +++ b/tests/MC/AArch64/SVE/fminnm.s.yaml @@ -0,0 +1,380 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x5d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminnm z0.h, p0/m, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0x5d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminnm z0.h, p0/m, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0x9d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminnm z0.s, p0/m, z0.s, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0xdd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminnm z0.d, p0/m, z0.d, #0.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminnm z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminnm z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x9d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminnm z31.s, p7/m, z31.s, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminnm z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x9f, 0x45, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminnm z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x85, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminnm z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc5, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminnm z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p7/z, z6.d" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminnm z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminnm z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc5, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminnm z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc5, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminnm z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0x00, 0x80, 0x5d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnm z0.h, p0/m, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0x5d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnm z0.h, p0/m, z0.h, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0x9d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnm z0.s, p0/m, z0.s, #0.0" + + - + input: + bytes: [ 0x00, 0x80, 0xdd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnm z0.d, p0/m, z0.d, #0.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnm z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnm z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x9d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnm z31.s, p7/m, z31.s, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnm z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x9f, 0x45, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnm z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x85, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnm z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc5, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnm z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p7/z, z6.d" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnm z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnm z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc5, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnm z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc5, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnm z0.d, p7/m, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/fminnmv.s.yaml b/tests/MC/AArch64/SVE/fminnmv.s.yaml new file mode 100644 index 0000000000..4fb08c51dd --- /dev/null +++ b/tests/MC/AArch64/SVE/fminnmv.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x3f, 0x45, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminnmv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x85, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminnmv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xc5, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminnmv d0, p7, z31.d" + + - + input: + bytes: [ 0xe0, 0x3f, 0x45, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnmv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x85, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnmv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xc5, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnmv d0, p7, z31.d" diff --git a/tests/MC/AArch64/SVE/fminv.s.yaml b/tests/MC/AArch64/SVE/fminv.s.yaml new file mode 100644 index 0000000000..926fe4f567 --- /dev/null +++ b/tests/MC/AArch64/SVE/fminv.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x3f, 0x47, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x87, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xc7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fminv d0, p7, z31.d" + + - + input: + bytes: [ 0xe0, 0x3f, 0x47, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x87, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xc7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminv d0, p7, z31.d" diff --git a/tests/MC/AArch64/SVE/fmla.s.yaml b/tests/MC/AArch64/SVE/fmla.s.yaml new file mode 100644 index 0000000000..cd0fc4f8c7 --- /dev/null +++ b/tests/MC/AArch64/SVE/fmla.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x1c, 0x7f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmla z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x1c, 0xbf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmla z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x1c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmla z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x00, 0x7f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmla z0.h, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x00, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmla z0.s, z1.s, z7.s[3]" + + - + input: + bytes: [ 0x20, 0x00, 0xf7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmla z0.d, z1.d, z7.d[1]" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0x1c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmla z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x1c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmla z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x00, 0xf7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmla z0.d, z1.d, z7.d[1]" + + - + input: + bytes: [ 0x20, 0x1c, 0x7f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmla z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x1c, 0xbf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmla z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x1c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmla z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x00, 0x7f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmla z0.h, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x00, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmla z0.s, z1.s, z7.s[3]" + + - + input: + bytes: [ 0x20, 0x00, 0xf7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmla z0.d, z1.d, z7.d[1]" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0x1c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmla z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x1c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmla z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x00, 0xf7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmla z0.d, z1.d, z7.d[1]" diff --git a/tests/MC/AArch64/SVE/fmls.s.yaml b/tests/MC/AArch64/SVE/fmls.s.yaml new file mode 100644 index 0000000000..0982d9663a --- /dev/null +++ b/tests/MC/AArch64/SVE/fmls.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x3c, 0x7f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmls z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x3c, 0xbf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmls z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x3c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmls z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x04, 0x7f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmls z0.h, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x04, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmls z0.s, z1.s, z7.s[3]" + + - + input: + bytes: [ 0x20, 0x04, 0xf7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmls z0.d, z1.d, z7.d[1]" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0x3c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmls z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x3c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmls z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x04, 0xf7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmls z0.d, z1.d, z7.d[1]" + + - + input: + bytes: [ 0x20, 0x3c, 0x7f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmls z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x3c, 0xbf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmls z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x3c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmls z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x04, 0x7f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmls z0.h, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x04, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmls z0.s, z1.s, z7.s[3]" + + - + input: + bytes: [ 0x20, 0x04, 0xf7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmls z0.d, z1.d, z7.d[1]" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0x3c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmls z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x3c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmls z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x04, 0xf7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmls z0.d, z1.d, z7.d[1]" diff --git a/tests/MC/AArch64/SVE/fmov.s.yaml b/tests/MC/AArch64/SVE/fmov.s.yaml new file mode 100644 index 0000000000..e396ad5f66 --- /dev/null +++ b/tests/MC/AArch64/SVE/fmov.s.yaml @@ -0,0 +1,5380 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, #0" + + - + input: + bytes: [ 0x00, 0xc0, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.s, #0" + + - + input: + bytes: [ 0x00, 0xc0, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.d, #0" + + - + input: + bytes: [ 0x00, 0xd8, 0x79, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.h, #-0.12500000" + + - + input: + bytes: [ 0x00, 0xd8, 0xb9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.s, #-0.12500000" + + - + input: + bytes: [ 0x00, 0xd8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.12500000" + + - + input: + bytes: [ 0xe0, 0xc7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, #31.00000000" + + - + input: + bytes: [ 0x00, 0xd8, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.h, p0/m, #-0.12500000" + + - + input: + bytes: [ 0x00, 0xd8, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.s, p0/m, #-0.12500000" + + - + input: + bytes: [ 0x00, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.12500000" + + - + input: + bytes: [ 0x20, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.13281250" + + - + input: + bytes: [ 0x40, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.14062500" + + - + input: + bytes: [ 0x60, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.14843750" + + - + input: + bytes: [ 0x80, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.15625000" + + - + input: + bytes: [ 0xa0, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.16406250" + + - + input: + bytes: [ 0xc0, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.17187500" + + - + input: + bytes: [ 0xe0, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.17968750" + + - + input: + bytes: [ 0x00, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.18750000" + + - + input: + bytes: [ 0x20, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.19531250" + + - + input: + bytes: [ 0x40, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.20312500" + + - + input: + bytes: [ 0x60, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.21093750" + + - + input: + bytes: [ 0x80, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.21875000" + + - + input: + bytes: [ 0xa0, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.22656250" + + - + input: + bytes: [ 0xc0, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.23437500" + + - + input: + bytes: [ 0xe0, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.24218750" + + - + input: + bytes: [ 0x00, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.25000000" + + - + input: + bytes: [ 0x20, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.26562500" + + - + input: + bytes: [ 0x40, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.28125000" + + - + input: + bytes: [ 0x60, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.29687500" + + - + input: + bytes: [ 0x80, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.31250000" + + - + input: + bytes: [ 0xa0, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.32812500" + + - + input: + bytes: [ 0xc0, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.34375000" + + - + input: + bytes: [ 0xe0, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.35937500" + + - + input: + bytes: [ 0x00, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.37500000" + + - + input: + bytes: [ 0x20, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.39062500" + + - + input: + bytes: [ 0x40, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.40625000" + + - + input: + bytes: [ 0x60, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.42187500" + + - + input: + bytes: [ 0x80, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.43750000" + + - + input: + bytes: [ 0xa0, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.45312500" + + - + input: + bytes: [ 0xc0, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.46875000" + + - + input: + bytes: [ 0xe0, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.48437500" + + - + input: + bytes: [ 0x00, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.50000000" + + - + input: + bytes: [ 0x20, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.53125000" + + - + input: + bytes: [ 0x40, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.56250000" + + - + input: + bytes: [ 0x60, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.59375000" + + - + input: + bytes: [ 0x80, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.62500000" + + - + input: + bytes: [ 0xa0, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.65625000" + + - + input: + bytes: [ 0xc0, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.68750000" + + - + input: + bytes: [ 0xe0, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.71875000" + + - + input: + bytes: [ 0x00, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.75000000" + + - + input: + bytes: [ 0x20, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.78125000" + + - + input: + bytes: [ 0x40, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.81250000" + + - + input: + bytes: [ 0x60, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.84375000" + + - + input: + bytes: [ 0x80, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.87500000" + + - + input: + bytes: [ 0xa0, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.90625000" + + - + input: + bytes: [ 0xc0, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.93750000" + + - + input: + bytes: [ 0xe0, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.96875000" + + - + input: + bytes: [ 0x00, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.00000000" + + - + input: + bytes: [ 0x20, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.06250000" + + - + input: + bytes: [ 0x40, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.12500000" + + - + input: + bytes: [ 0x60, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.18750000" + + - + input: + bytes: [ 0x80, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.25000000" + + - + input: + bytes: [ 0xa0, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.31250000" + + - + input: + bytes: [ 0xc0, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.37500000" + + - + input: + bytes: [ 0xe0, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.43750000" + + - + input: + bytes: [ 0x00, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.50000000" + + - + input: + bytes: [ 0x20, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.56250000" + + - + input: + bytes: [ 0x40, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.62500000" + + - + input: + bytes: [ 0x60, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.68750000" + + - + input: + bytes: [ 0x80, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.75000000" + + - + input: + bytes: [ 0xa0, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.81250000" + + - + input: + bytes: [ 0xc0, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.87500000" + + - + input: + bytes: [ 0xe0, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.93750000" + + - + input: + bytes: [ 0x00, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.00000000" + + - + input: + bytes: [ 0x20, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.12500000" + + - + input: + bytes: [ 0x40, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.25000000" + + - + input: + bytes: [ 0x60, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.37500000" + + - + input: + bytes: [ 0x80, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.50000000" + + - + input: + bytes: [ 0xa0, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.62500000" + + - + input: + bytes: [ 0xc0, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.75000000" + + - + input: + bytes: [ 0xe0, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.87500000" + + - + input: + bytes: [ 0x00, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.00000000" + + - + input: + bytes: [ 0x20, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.12500000" + + - + input: + bytes: [ 0x40, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.25000000" + + - + input: + bytes: [ 0x60, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.37500000" + + - + input: + bytes: [ 0x80, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.50000000" + + - + input: + bytes: [ 0xa0, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.62500000" + + - + input: + bytes: [ 0xc0, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.75000000" + + - + input: + bytes: [ 0xe0, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.87500000" + + - + input: + bytes: [ 0x00, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-4.00000000" + + - + input: + bytes: [ 0x20, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-4.25000000" + + - + input: + bytes: [ 0x40, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-4.50000000" + + - + input: + bytes: [ 0x60, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-4.75000000" + + - + input: + bytes: [ 0x80, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-5.00000000" + + - + input: + bytes: [ 0xa0, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-5.25000000" + + - + input: + bytes: [ 0xc0, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-5.50000000" + + - + input: + bytes: [ 0xe0, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-5.75000000" + + - + input: + bytes: [ 0x00, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-6.00000000" + + - + input: + bytes: [ 0x20, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-6.25000000" + + - + input: + bytes: [ 0x40, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-6.50000000" + + - + input: + bytes: [ 0x60, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-6.75000000" + + - + input: + bytes: [ 0x80, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-7.00000000" + + - + input: + bytes: [ 0xa0, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-7.25000000" + + - + input: + bytes: [ 0xc0, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-7.50000000" + + - + input: + bytes: [ 0xe0, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-7.75000000" + + - + input: + bytes: [ 0x00, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-8.00000000" + + - + input: + bytes: [ 0x20, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-8.50000000" + + - + input: + bytes: [ 0x40, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-9.00000000" + + - + input: + bytes: [ 0x60, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-9.50000000" + + - + input: + bytes: [ 0x80, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-10.00000000" + + - + input: + bytes: [ 0xa0, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-10.50000000" + + - + input: + bytes: [ 0xc0, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-11.00000000" + + - + input: + bytes: [ 0xe0, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-11.50000000" + + - + input: + bytes: [ 0x00, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-12.00000000" + + - + input: + bytes: [ 0x20, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-12.50000000" + + - + input: + bytes: [ 0x40, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-13.00000000" + + - + input: + bytes: [ 0x60, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-13.50000000" + + - + input: + bytes: [ 0x80, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-14.00000000" + + - + input: + bytes: [ 0xa0, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-14.50000000" + + - + input: + bytes: [ 0xc0, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-15.00000000" + + - + input: + bytes: [ 0xe0, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-15.50000000" + + - + input: + bytes: [ 0x00, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-16.00000000" + + - + input: + bytes: [ 0x20, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-17.00000000" + + - + input: + bytes: [ 0x40, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-18.00000000" + + - + input: + bytes: [ 0x60, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-19.00000000" + + - + input: + bytes: [ 0x80, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-20.00000000" + + - + input: + bytes: [ 0xa0, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-21.00000000" + + - + input: + bytes: [ 0xc0, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-22.00000000" + + - + input: + bytes: [ 0xe0, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-23.00000000" + + - + input: + bytes: [ 0x00, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-24.00000000" + + - + input: + bytes: [ 0x20, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-25.00000000" + + - + input: + bytes: [ 0x40, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-26.00000000" + + - + input: + bytes: [ 0x60, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-27.00000000" + + - + input: + bytes: [ 0x80, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-28.00000000" + + - + input: + bytes: [ 0xa0, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-29.00000000" + + - + input: + bytes: [ 0xc0, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-30.00000000" + + - + input: + bytes: [ 0xe0, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-31.00000000" + + - + input: + bytes: [ 0x00, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.12500000" + + - + input: + bytes: [ 0x20, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.13281250" + + - + input: + bytes: [ 0x40, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.14062500" + + - + input: + bytes: [ 0x60, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.14843750" + + - + input: + bytes: [ 0x80, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.15625000" + + - + input: + bytes: [ 0xa0, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.16406250" + + - + input: + bytes: [ 0xc0, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.17187500" + + - + input: + bytes: [ 0xe0, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.17968750" + + - + input: + bytes: [ 0x00, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.18750000" + + - + input: + bytes: [ 0x20, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.19531250" + + - + input: + bytes: [ 0x40, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.20312500" + + - + input: + bytes: [ 0x60, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.21093750" + + - + input: + bytes: [ 0x80, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.21875000" + + - + input: + bytes: [ 0xa0, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.22656250" + + - + input: + bytes: [ 0xc0, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.23437500" + + - + input: + bytes: [ 0xe0, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.24218750" + + - + input: + bytes: [ 0x00, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.25000000" + + - + input: + bytes: [ 0x20, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.26562500" + + - + input: + bytes: [ 0x40, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.28125000" + + - + input: + bytes: [ 0x60, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.29687500" + + - + input: + bytes: [ 0x80, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.31250000" + + - + input: + bytes: [ 0xa0, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.32812500" + + - + input: + bytes: [ 0xc0, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.34375000" + + - + input: + bytes: [ 0xe0, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.35937500" + + - + input: + bytes: [ 0x00, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.37500000" + + - + input: + bytes: [ 0x20, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.39062500" + + - + input: + bytes: [ 0x40, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.40625000" + + - + input: + bytes: [ 0x60, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.42187500" + + - + input: + bytes: [ 0x80, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.43750000" + + - + input: + bytes: [ 0xa0, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.45312500" + + - + input: + bytes: [ 0xc0, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.46875000" + + - + input: + bytes: [ 0xe0, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.48437500" + + - + input: + bytes: [ 0x00, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.50000000" + + - + input: + bytes: [ 0x20, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.53125000" + + - + input: + bytes: [ 0x40, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.56250000" + + - + input: + bytes: [ 0x60, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.59375000" + + - + input: + bytes: [ 0x80, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.62500000" + + - + input: + bytes: [ 0xa0, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.65625000" + + - + input: + bytes: [ 0xc0, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.68750000" + + - + input: + bytes: [ 0xe0, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.71875000" + + - + input: + bytes: [ 0x00, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.75000000" + + - + input: + bytes: [ 0x20, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.78125000" + + - + input: + bytes: [ 0x40, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.81250000" + + - + input: + bytes: [ 0x60, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.84375000" + + - + input: + bytes: [ 0x80, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.87500000" + + - + input: + bytes: [ 0xa0, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.90625000" + + - + input: + bytes: [ 0xc0, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.93750000" + + - + input: + bytes: [ 0xe0, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.96875000" + + - + input: + bytes: [ 0x00, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.00000000" + + - + input: + bytes: [ 0x20, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.06250000" + + - + input: + bytes: [ 0x40, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.12500000" + + - + input: + bytes: [ 0x60, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.18750000" + + - + input: + bytes: [ 0x80, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.25000000" + + - + input: + bytes: [ 0xa0, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.31250000" + + - + input: + bytes: [ 0xc0, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.37500000" + + - + input: + bytes: [ 0xe0, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.43750000" + + - + input: + bytes: [ 0x00, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.50000000" + + - + input: + bytes: [ 0x20, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.56250000" + + - + input: + bytes: [ 0x40, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.62500000" + + - + input: + bytes: [ 0x60, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.68750000" + + - + input: + bytes: [ 0x80, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.75000000" + + - + input: + bytes: [ 0xa0, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.81250000" + + - + input: + bytes: [ 0xc0, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.87500000" + + - + input: + bytes: [ 0xe0, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.93750000" + + - + input: + bytes: [ 0x00, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.00000000" + + - + input: + bytes: [ 0x20, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.12500000" + + - + input: + bytes: [ 0x40, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.25000000" + + - + input: + bytes: [ 0x60, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.37500000" + + - + input: + bytes: [ 0x80, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.50000000" + + - + input: + bytes: [ 0xa0, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.62500000" + + - + input: + bytes: [ 0xc0, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.75000000" + + - + input: + bytes: [ 0xe0, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.87500000" + + - + input: + bytes: [ 0x00, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.00000000" + + - + input: + bytes: [ 0x20, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.12500000" + + - + input: + bytes: [ 0x40, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.25000000" + + - + input: + bytes: [ 0x60, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.37500000" + + - + input: + bytes: [ 0x80, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.50000000" + + - + input: + bytes: [ 0xa0, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.62500000" + + - + input: + bytes: [ 0xc0, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.75000000" + + - + input: + bytes: [ 0xe0, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.87500000" + + - + input: + bytes: [ 0x00, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #4.00000000" + + - + input: + bytes: [ 0x20, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #4.25000000" + + - + input: + bytes: [ 0x40, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #4.50000000" + + - + input: + bytes: [ 0x60, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #4.75000000" + + - + input: + bytes: [ 0x80, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #5.00000000" + + - + input: + bytes: [ 0xa0, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #5.25000000" + + - + input: + bytes: [ 0xc0, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #5.50000000" + + - + input: + bytes: [ 0xe0, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #5.75000000" + + - + input: + bytes: [ 0x00, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #6.00000000" + + - + input: + bytes: [ 0x20, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #6.25000000" + + - + input: + bytes: [ 0x40, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #6.50000000" + + - + input: + bytes: [ 0x60, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #6.75000000" + + - + input: + bytes: [ 0x80, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #7.00000000" + + - + input: + bytes: [ 0xa0, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #7.25000000" + + - + input: + bytes: [ 0xc0, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #7.50000000" + + - + input: + bytes: [ 0xe0, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #7.75000000" + + - + input: + bytes: [ 0x00, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #8.00000000" + + - + input: + bytes: [ 0x20, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #8.50000000" + + - + input: + bytes: [ 0x40, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #9.00000000" + + - + input: + bytes: [ 0x60, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #9.50000000" + + - + input: + bytes: [ 0x80, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #10.00000000" + + - + input: + bytes: [ 0xa0, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #10.50000000" + + - + input: + bytes: [ 0xc0, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #11.00000000" + + - + input: + bytes: [ 0xe0, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #11.50000000" + + - + input: + bytes: [ 0x00, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #12.00000000" + + - + input: + bytes: [ 0x20, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #12.50000000" + + - + input: + bytes: [ 0x40, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #13.00000000" + + - + input: + bytes: [ 0x60, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #13.50000000" + + - + input: + bytes: [ 0x80, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #14.00000000" + + - + input: + bytes: [ 0xa0, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #14.50000000" + + - + input: + bytes: [ 0xc0, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #15.00000000" + + - + input: + bytes: [ 0xe0, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #15.50000000" + + - + input: + bytes: [ 0x00, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #16.00000000" + + - + input: + bytes: [ 0x20, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #17.00000000" + + - + input: + bytes: [ 0x40, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #18.00000000" + + - + input: + bytes: [ 0x60, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #19.00000000" + + - + input: + bytes: [ 0x80, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #20.00000000" + + - + input: + bytes: [ 0xa0, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #21.00000000" + + - + input: + bytes: [ 0xc0, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #22.00000000" + + - + input: + bytes: [ 0xe0, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #23.00000000" + + - + input: + bytes: [ 0x00, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #24.00000000" + + - + input: + bytes: [ 0x20, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #25.00000000" + + - + input: + bytes: [ 0x40, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #26.00000000" + + - + input: + bytes: [ 0x60, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #27.00000000" + + - + input: + bytes: [ 0x80, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #28.00000000" + + - + input: + bytes: [ 0xa0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #29.00000000" + + - + input: + bytes: [ 0xc0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #30.00000000" + + - + input: + bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #31.00000000" + + - + input: + bytes: [ 0xe0, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p0/z, z7.d" + + - + input: + bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #31.00000000" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #31.00000000" + + - + input: + bytes: [ 0x00, 0xc0, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, #0" + + - + input: + bytes: [ 0x00, 0xc0, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, #0" + + - + input: + bytes: [ 0x00, 0xc0, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, #0" + + - + input: + bytes: [ 0x00, 0xd8, 0x79, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.h, #-0.12500000" + + - + input: + bytes: [ 0x00, 0xd8, 0xb9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.s, #-0.12500000" + + - + input: + bytes: [ 0x00, 0xd8, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #-0.12500000" + + - + input: + bytes: [ 0xe0, 0xc7, 0xf9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, #31.00000000" + + - + input: + bytes: [ 0x00, 0xd8, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.h, p0/m, #-0.12500000" + + - + input: + bytes: [ 0x00, 0xd8, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.s, p0/m, #-0.12500000" + + - + input: + bytes: [ 0x00, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.12500000" + + - + input: + bytes: [ 0x20, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.13281250" + + - + input: + bytes: [ 0x40, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.14062500" + + - + input: + bytes: [ 0x60, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.14843750" + + - + input: + bytes: [ 0x80, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.15625000" + + - + input: + bytes: [ 0xa0, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.16406250" + + - + input: + bytes: [ 0xc0, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.17187500" + + - + input: + bytes: [ 0xe0, 0xd8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.17968750" + + - + input: + bytes: [ 0x00, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.18750000" + + - + input: + bytes: [ 0x20, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.19531250" + + - + input: + bytes: [ 0x40, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.20312500" + + - + input: + bytes: [ 0x60, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.21093750" + + - + input: + bytes: [ 0x80, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.21875000" + + - + input: + bytes: [ 0xa0, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.22656250" + + - + input: + bytes: [ 0xc0, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.23437500" + + - + input: + bytes: [ 0xe0, 0xd9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.24218750" + + - + input: + bytes: [ 0x00, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.25000000" + + - + input: + bytes: [ 0x20, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.26562500" + + - + input: + bytes: [ 0x40, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.28125000" + + - + input: + bytes: [ 0x60, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.29687500" + + - + input: + bytes: [ 0x80, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.31250000" + + - + input: + bytes: [ 0xa0, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.32812500" + + - + input: + bytes: [ 0xc0, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.34375000" + + - + input: + bytes: [ 0xe0, 0xda, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.35937500" + + - + input: + bytes: [ 0x00, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.37500000" + + - + input: + bytes: [ 0x20, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.39062500" + + - + input: + bytes: [ 0x40, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.40625000" + + - + input: + bytes: [ 0x60, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.42187500" + + - + input: + bytes: [ 0x80, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.43750000" + + - + input: + bytes: [ 0xa0, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.45312500" + + - + input: + bytes: [ 0xc0, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.46875000" + + - + input: + bytes: [ 0xe0, 0xdb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.48437500" + + - + input: + bytes: [ 0x00, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.50000000" + + - + input: + bytes: [ 0x20, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.53125000" + + - + input: + bytes: [ 0x40, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.56250000" + + - + input: + bytes: [ 0x60, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.59375000" + + - + input: + bytes: [ 0x80, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.62500000" + + - + input: + bytes: [ 0xa0, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.65625000" + + - + input: + bytes: [ 0xc0, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.68750000" + + - + input: + bytes: [ 0xe0, 0xdc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.71875000" + + - + input: + bytes: [ 0x00, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.75000000" + + - + input: + bytes: [ 0x20, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.78125000" + + - + input: + bytes: [ 0x40, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.81250000" + + - + input: + bytes: [ 0x60, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.84375000" + + - + input: + bytes: [ 0x80, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.87500000" + + - + input: + bytes: [ 0xa0, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.90625000" + + - + input: + bytes: [ 0xc0, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.93750000" + + - + input: + bytes: [ 0xe0, 0xdd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-0.96875000" + + - + input: + bytes: [ 0x00, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.00000000" + + - + input: + bytes: [ 0x20, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.06250000" + + - + input: + bytes: [ 0x40, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.12500000" + + - + input: + bytes: [ 0x60, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.18750000" + + - + input: + bytes: [ 0x80, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.25000000" + + - + input: + bytes: [ 0xa0, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.31250000" + + - + input: + bytes: [ 0xc0, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.37500000" + + - + input: + bytes: [ 0xe0, 0xde, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.43750000" + + - + input: + bytes: [ 0x00, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.50000000" + + - + input: + bytes: [ 0x20, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.56250000" + + - + input: + bytes: [ 0x40, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.62500000" + + - + input: + bytes: [ 0x60, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.68750000" + + - + input: + bytes: [ 0x80, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.75000000" + + - + input: + bytes: [ 0xa0, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.81250000" + + - + input: + bytes: [ 0xc0, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.87500000" + + - + input: + bytes: [ 0xe0, 0xdf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-1.93750000" + + - + input: + bytes: [ 0x00, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.00000000" + + - + input: + bytes: [ 0x20, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.12500000" + + - + input: + bytes: [ 0x40, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.25000000" + + - + input: + bytes: [ 0x60, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.37500000" + + - + input: + bytes: [ 0x80, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.50000000" + + - + input: + bytes: [ 0xa0, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.62500000" + + - + input: + bytes: [ 0xc0, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.75000000" + + - + input: + bytes: [ 0xe0, 0xd0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-2.87500000" + + - + input: + bytes: [ 0x00, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.00000000" + + - + input: + bytes: [ 0x20, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.12500000" + + - + input: + bytes: [ 0x40, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.25000000" + + - + input: + bytes: [ 0x60, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.37500000" + + - + input: + bytes: [ 0x80, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.50000000" + + - + input: + bytes: [ 0xa0, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.62500000" + + - + input: + bytes: [ 0xc0, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.75000000" + + - + input: + bytes: [ 0xe0, 0xd1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-3.87500000" + + - + input: + bytes: [ 0x00, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-4.00000000" + + - + input: + bytes: [ 0x20, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-4.25000000" + + - + input: + bytes: [ 0x40, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-4.50000000" + + - + input: + bytes: [ 0x60, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-4.75000000" + + - + input: + bytes: [ 0x80, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-5.00000000" + + - + input: + bytes: [ 0xa0, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-5.25000000" + + - + input: + bytes: [ 0xc0, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-5.50000000" + + - + input: + bytes: [ 0xe0, 0xd2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-5.75000000" + + - + input: + bytes: [ 0x00, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-6.00000000" + + - + input: + bytes: [ 0x20, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-6.25000000" + + - + input: + bytes: [ 0x40, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-6.50000000" + + - + input: + bytes: [ 0x60, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-6.75000000" + + - + input: + bytes: [ 0x80, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-7.00000000" + + - + input: + bytes: [ 0xa0, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-7.25000000" + + - + input: + bytes: [ 0xc0, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-7.50000000" + + - + input: + bytes: [ 0xe0, 0xd3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-7.75000000" + + - + input: + bytes: [ 0x00, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-8.00000000" + + - + input: + bytes: [ 0x20, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-8.50000000" + + - + input: + bytes: [ 0x40, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-9.00000000" + + - + input: + bytes: [ 0x60, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-9.50000000" + + - + input: + bytes: [ 0x80, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-10.00000000" + + - + input: + bytes: [ 0xa0, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-10.50000000" + + - + input: + bytes: [ 0xc0, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-11.00000000" + + - + input: + bytes: [ 0xe0, 0xd4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-11.50000000" + + - + input: + bytes: [ 0x00, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-12.00000000" + + - + input: + bytes: [ 0x20, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-12.50000000" + + - + input: + bytes: [ 0x40, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-13.00000000" + + - + input: + bytes: [ 0x60, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-13.50000000" + + - + input: + bytes: [ 0x80, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-14.00000000" + + - + input: + bytes: [ 0xa0, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-14.50000000" + + - + input: + bytes: [ 0xc0, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-15.00000000" + + - + input: + bytes: [ 0xe0, 0xd5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-15.50000000" + + - + input: + bytes: [ 0x00, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-16.00000000" + + - + input: + bytes: [ 0x20, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-17.00000000" + + - + input: + bytes: [ 0x40, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-18.00000000" + + - + input: + bytes: [ 0x60, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-19.00000000" + + - + input: + bytes: [ 0x80, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-20.00000000" + + - + input: + bytes: [ 0xa0, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-21.00000000" + + - + input: + bytes: [ 0xc0, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-22.00000000" + + - + input: + bytes: [ 0xe0, 0xd6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-23.00000000" + + - + input: + bytes: [ 0x00, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-24.00000000" + + - + input: + bytes: [ 0x20, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-25.00000000" + + - + input: + bytes: [ 0x40, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-26.00000000" + + - + input: + bytes: [ 0x60, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-27.00000000" + + - + input: + bytes: [ 0x80, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-28.00000000" + + - + input: + bytes: [ 0xa0, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-29.00000000" + + - + input: + bytes: [ 0xc0, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-30.00000000" + + - + input: + bytes: [ 0xe0, 0xd7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #-31.00000000" + + - + input: + bytes: [ 0x00, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.12500000" + + - + input: + bytes: [ 0x20, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.13281250" + + - + input: + bytes: [ 0x40, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.14062500" + + - + input: + bytes: [ 0x60, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.14843750" + + - + input: + bytes: [ 0x80, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.15625000" + + - + input: + bytes: [ 0xa0, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.16406250" + + - + input: + bytes: [ 0xc0, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.17187500" + + - + input: + bytes: [ 0xe0, 0xc8, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.17968750" + + - + input: + bytes: [ 0x00, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.18750000" + + - + input: + bytes: [ 0x20, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.19531250" + + - + input: + bytes: [ 0x40, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.20312500" + + - + input: + bytes: [ 0x60, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.21093750" + + - + input: + bytes: [ 0x80, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.21875000" + + - + input: + bytes: [ 0xa0, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.22656250" + + - + input: + bytes: [ 0xc0, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.23437500" + + - + input: + bytes: [ 0xe0, 0xc9, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.24218750" + + - + input: + bytes: [ 0x00, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.25000000" + + - + input: + bytes: [ 0x20, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.26562500" + + - + input: + bytes: [ 0x40, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.28125000" + + - + input: + bytes: [ 0x60, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.29687500" + + - + input: + bytes: [ 0x80, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.31250000" + + - + input: + bytes: [ 0xa0, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.32812500" + + - + input: + bytes: [ 0xc0, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.34375000" + + - + input: + bytes: [ 0xe0, 0xca, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.35937500" + + - + input: + bytes: [ 0x00, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.37500000" + + - + input: + bytes: [ 0x20, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.39062500" + + - + input: + bytes: [ 0x40, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.40625000" + + - + input: + bytes: [ 0x60, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.42187500" + + - + input: + bytes: [ 0x80, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.43750000" + + - + input: + bytes: [ 0xa0, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.45312500" + + - + input: + bytes: [ 0xc0, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.46875000" + + - + input: + bytes: [ 0xe0, 0xcb, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.48437500" + + - + input: + bytes: [ 0x00, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.50000000" + + - + input: + bytes: [ 0x20, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.53125000" + + - + input: + bytes: [ 0x40, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.56250000" + + - + input: + bytes: [ 0x60, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.59375000" + + - + input: + bytes: [ 0x80, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.62500000" + + - + input: + bytes: [ 0xa0, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.65625000" + + - + input: + bytes: [ 0xc0, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.68750000" + + - + input: + bytes: [ 0xe0, 0xcc, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.71875000" + + - + input: + bytes: [ 0x00, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.75000000" + + - + input: + bytes: [ 0x20, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.78125000" + + - + input: + bytes: [ 0x40, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.81250000" + + - + input: + bytes: [ 0x60, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.84375000" + + - + input: + bytes: [ 0x80, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.87500000" + + - + input: + bytes: [ 0xa0, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.90625000" + + - + input: + bytes: [ 0xc0, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.93750000" + + - + input: + bytes: [ 0xe0, 0xcd, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #0.96875000" + + - + input: + bytes: [ 0x00, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.00000000" + + - + input: + bytes: [ 0x20, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.06250000" + + - + input: + bytes: [ 0x40, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.12500000" + + - + input: + bytes: [ 0x60, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.18750000" + + - + input: + bytes: [ 0x80, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.25000000" + + - + input: + bytes: [ 0xa0, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.31250000" + + - + input: + bytes: [ 0xc0, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.37500000" + + - + input: + bytes: [ 0xe0, 0xce, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.43750000" + + - + input: + bytes: [ 0x00, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.50000000" + + - + input: + bytes: [ 0x20, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.56250000" + + - + input: + bytes: [ 0x40, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.62500000" + + - + input: + bytes: [ 0x60, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.68750000" + + - + input: + bytes: [ 0x80, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.75000000" + + - + input: + bytes: [ 0xa0, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.81250000" + + - + input: + bytes: [ 0xc0, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.87500000" + + - + input: + bytes: [ 0xe0, 0xcf, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #1.93750000" + + - + input: + bytes: [ 0x00, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.00000000" + + - + input: + bytes: [ 0x20, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.12500000" + + - + input: + bytes: [ 0x40, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.25000000" + + - + input: + bytes: [ 0x60, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.37500000" + + - + input: + bytes: [ 0x80, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.50000000" + + - + input: + bytes: [ 0xa0, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.62500000" + + - + input: + bytes: [ 0xc0, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.75000000" + + - + input: + bytes: [ 0xe0, 0xc0, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #2.87500000" + + - + input: + bytes: [ 0x00, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.00000000" + + - + input: + bytes: [ 0x20, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.12500000" + + - + input: + bytes: [ 0x40, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.25000000" + + - + input: + bytes: [ 0x60, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.37500000" + + - + input: + bytes: [ 0x80, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.50000000" + + - + input: + bytes: [ 0xa0, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.62500000" + + - + input: + bytes: [ 0xc0, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.75000000" + + - + input: + bytes: [ 0xe0, 0xc1, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #3.87500000" + + - + input: + bytes: [ 0x00, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #4.00000000" + + - + input: + bytes: [ 0x20, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #4.25000000" + + - + input: + bytes: [ 0x40, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #4.50000000" + + - + input: + bytes: [ 0x60, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #4.75000000" + + - + input: + bytes: [ 0x80, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #5.00000000" + + - + input: + bytes: [ 0xa0, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #5.25000000" + + - + input: + bytes: [ 0xc0, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #5.50000000" + + - + input: + bytes: [ 0xe0, 0xc2, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #5.75000000" + + - + input: + bytes: [ 0x00, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #6.00000000" + + - + input: + bytes: [ 0x20, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #6.25000000" + + - + input: + bytes: [ 0x40, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #6.50000000" + + - + input: + bytes: [ 0x60, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #6.75000000" + + - + input: + bytes: [ 0x80, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #7.00000000" + + - + input: + bytes: [ 0xa0, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #7.25000000" + + - + input: + bytes: [ 0xc0, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #7.50000000" + + - + input: + bytes: [ 0xe0, 0xc3, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #7.75000000" + + - + input: + bytes: [ 0x00, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #8.00000000" + + - + input: + bytes: [ 0x20, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #8.50000000" + + - + input: + bytes: [ 0x40, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #9.00000000" + + - + input: + bytes: [ 0x60, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #9.50000000" + + - + input: + bytes: [ 0x80, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #10.00000000" + + - + input: + bytes: [ 0xa0, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #10.50000000" + + - + input: + bytes: [ 0xc0, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #11.00000000" + + - + input: + bytes: [ 0xe0, 0xc4, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #11.50000000" + + - + input: + bytes: [ 0x00, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #12.00000000" + + - + input: + bytes: [ 0x20, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #12.50000000" + + - + input: + bytes: [ 0x40, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #13.00000000" + + - + input: + bytes: [ 0x60, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #13.50000000" + + - + input: + bytes: [ 0x80, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #14.00000000" + + - + input: + bytes: [ 0xa0, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #14.50000000" + + - + input: + bytes: [ 0xc0, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #15.00000000" + + - + input: + bytes: [ 0xe0, 0xc5, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #15.50000000" + + - + input: + bytes: [ 0x00, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #16.00000000" + + - + input: + bytes: [ 0x20, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #17.00000000" + + - + input: + bytes: [ 0x40, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #18.00000000" + + - + input: + bytes: [ 0x60, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #19.00000000" + + - + input: + bytes: [ 0x80, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #20.00000000" + + - + input: + bytes: [ 0xa0, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #21.00000000" + + - + input: + bytes: [ 0xc0, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #22.00000000" + + - + input: + bytes: [ 0xe0, 0xc6, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #23.00000000" + + - + input: + bytes: [ 0x00, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #24.00000000" + + - + input: + bytes: [ 0x20, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #25.00000000" + + - + input: + bytes: [ 0x40, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #26.00000000" + + - + input: + bytes: [ 0x60, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #27.00000000" + + - + input: + bytes: [ 0x80, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #28.00000000" + + - + input: + bytes: [ 0xa0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #29.00000000" + + - + input: + bytes: [ 0xc0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #30.00000000" + + - + input: + bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #31.00000000" + + - + input: + bytes: [ 0xe0, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p0/z, z7.d" + + - + input: + bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #31.00000000" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmov z0.d, p0/m, #31.00000000" diff --git a/tests/MC/AArch64/SVE/fmsb.s.yaml b/tests/MC/AArch64/SVE/fmsb.s.yaml new file mode 100644 index 0000000000..6232522df2 --- /dev/null +++ b/tests/MC/AArch64/SVE/fmsb.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xbc, 0x7f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmsb z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xbc, 0xbf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmsb z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xbc, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmsb z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0xbc, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmsb z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xbc, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmsb z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0xbc, 0x7f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmsb z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xbc, 0xbf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmsb z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xbc, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmsb z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0xbc, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmsb z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xbc, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmsb z0.d, p7/m, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE/fmul.s.yaml b/tests/MC/AArch64/SVE/fmul.s.yaml new file mode 100644 index 0000000000..8eb012dd2a --- /dev/null +++ b/tests/MC/AArch64/SVE/fmul.s.yaml @@ -0,0 +1,540 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x5a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z0.h, p0/m, z0.h, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0x5a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z0.h, p0/m, z0.h, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0x9a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z0.s, p0/m, z0.s, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0xda, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z0.d, p0/m, z0.d, #0.5" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z31.h, p7/m, z31.h, #2.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x9a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z31.s, p7/m, z31.s, #2.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0xda, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z31.d, p7/m, z31.d, #2.0" + + - + input: + bytes: [ 0x00, 0x20, 0x20, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z0.h, z0.h, z0.h[0]" + + - + input: + bytes: [ 0x00, 0x20, 0xa0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z0.s, z0.s, z0.s[0]" + + - + input: + bytes: [ 0x00, 0x20, 0xe0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z0.d, z0.d, z0.d[0]" + + - + input: + bytes: [ 0xff, 0x23, 0x7f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z31.h, z31.h, z7.h[7]" + + - + input: + bytes: [ 0xff, 0x23, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z31.s, z31.s, z7.s[3]" + + - + input: + bytes: [ 0xff, 0x23, 0xff, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z31.d, z31.d, z15.d[1]" + + - + input: + bytes: [ 0xe0, 0x9f, 0x42, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x82, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc2, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0x20, 0x08, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x08, 0x9f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x08, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p7/z, z6.d" + + - + input: + bytes: [ 0x3f, 0x9c, 0xda, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z31.d, p7/m, z31.d, #2.0" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x3f, 0x9c, 0xda, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z31.d, p7/m, z31.d, #2.0" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc2, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc2, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmul z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0x00, 0x80, 0x5a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z0.h, p0/m, z0.h, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0x5a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z0.h, p0/m, z0.h, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0x9a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z0.s, p0/m, z0.s, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0xda, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z0.d, p0/m, z0.d, #0.5" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z31.h, p7/m, z31.h, #2.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x9a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z31.s, p7/m, z31.s, #2.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0xda, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z31.d, p7/m, z31.d, #2.0" + + - + input: + bytes: [ 0x00, 0x20, 0x20, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z0.h, z0.h, z0.h[0]" + + - + input: + bytes: [ 0x00, 0x20, 0xa0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z0.s, z0.s, z0.s[0]" + + - + input: + bytes: [ 0x00, 0x20, 0xe0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z0.d, z0.d, z0.d[0]" + + - + input: + bytes: [ 0xff, 0x23, 0x7f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z31.h, z31.h, z7.h[7]" + + - + input: + bytes: [ 0xff, 0x23, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z31.s, z31.s, z7.s[3]" + + - + input: + bytes: [ 0xff, 0x23, 0xff, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z31.d, z31.d, z15.d[1]" + + - + input: + bytes: [ 0xe0, 0x9f, 0x42, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x82, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc2, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0x20, 0x08, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x08, 0x9f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x08, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p7/z, z6.d" + + - + input: + bytes: [ 0x3f, 0x9c, 0xda, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z31.d, p7/m, z31.d, #2.0" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x3f, 0x9c, 0xda, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z31.d, p7/m, z31.d, #2.0" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc2, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc2, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmul z0.d, p7/m, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/fmulx.s.yaml b/tests/MC/AArch64/SVE/fmulx.s.yaml new file mode 100644 index 0000000000..dc8b03652c --- /dev/null +++ b/tests/MC/AArch64/SVE/fmulx.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x9f, 0x4a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmulx z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x8a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmulx z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xca, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmulx z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xca, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmulx z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xca, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fmulx z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0x4a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmulx z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x8a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmulx z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xca, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmulx z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xca, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmulx z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xca, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmulx z0.d, p7/m, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/fneg.s.yaml b/tests/MC/AArch64/SVE/fneg.s.yaml new file mode 100644 index 0000000000..e2544a24ef --- /dev/null +++ b/tests/MC/AArch64/SVE/fneg.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x5d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fneg z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x9d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fneg z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xdd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fneg z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xdd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fneg z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xdd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fneg z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x5d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fneg z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x9d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fneg z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xdd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fneg z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xdd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fneg z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xdd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fneg z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/fnmad.s.yaml b/tests/MC/AArch64/SVE/fnmad.s.yaml new file mode 100644 index 0000000000..ce71c91cae --- /dev/null +++ b/tests/MC/AArch64/SVE/fnmad.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xdc, 0x7f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmad z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xdc, 0xbf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmad z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xdc, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmad z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0xdc, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmad z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xdc, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmad z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0xdc, 0x7f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmad z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xdc, 0xbf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmad z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xdc, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmad z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0xdc, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmad z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xdc, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmad z0.d, p7/m, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE/fnmla.s.yaml b/tests/MC/AArch64/SVE/fnmla.s.yaml new file mode 100644 index 0000000000..302eb2fd06 --- /dev/null +++ b/tests/MC/AArch64/SVE/fnmla.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x5c, 0x7f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmla z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x5c, 0xbf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmla z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x5c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmla z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0x5c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmla z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x5c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmla z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x5c, 0x7f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmla z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x5c, 0xbf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmla z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x5c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmla z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0x5c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmla z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x5c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmla z0.d, p7/m, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE/fnmls.s.yaml b/tests/MC/AArch64/SVE/fnmls.s.yaml new file mode 100644 index 0000000000..ffbbc63919 --- /dev/null +++ b/tests/MC/AArch64/SVE/fnmls.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x7c, 0x7f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmls z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x7c, 0xbf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmls z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x7c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmls z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0x7c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmls z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x7c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmls z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x7c, 0x7f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmls z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x7c, 0xbf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmls z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x7c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmls z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0x7c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmls z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x7c, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmls z0.d, p7/m, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE/fnmsb.s.yaml b/tests/MC/AArch64/SVE/fnmsb.s.yaml new file mode 100644 index 0000000000..9ec87bd977 --- /dev/null +++ b/tests/MC/AArch64/SVE/fnmsb.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xfc, 0x7f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmsb z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xfc, 0xbf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmsb z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xfc, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmsb z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0xfc, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmsb z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xfc, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fnmsb z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0xfc, 0x7f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmsb z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xfc, 0xbf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmsb z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xfc, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmsb z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0xfc, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmsb z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xfc, 0xff, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fnmsb z0.d, p7/m, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE/frecpe.s.yaml b/tests/MC/AArch64/SVE/frecpe.s.yaml new file mode 100644 index 0000000000..fdf4124faa --- /dev/null +++ b/tests/MC/AArch64/SVE/frecpe.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x33, 0x4e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frecpe z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x33, 0x8e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frecpe z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x33, 0xce, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frecpe z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x33, 0x4e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frecpe z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x33, 0x8e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frecpe z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x33, 0xce, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frecpe z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/frecps.s.yaml b/tests/MC/AArch64/SVE/frecps.s.yaml new file mode 100644 index 0000000000..5f55d1e3b1 --- /dev/null +++ b/tests/MC/AArch64/SVE/frecps.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x18, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frecps z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x18, 0x9f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frecps z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x18, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frecps z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x18, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frecps z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x18, 0x9f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frecps z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x18, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frecps z0.d, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE/frecpx.s.yaml b/tests/MC/AArch64/SVE/frecpx.s.yaml new file mode 100644 index 0000000000..44b19f816c --- /dev/null +++ b/tests/MC/AArch64/SVE/frecpx.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x4c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frecpx z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x8c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frecpx z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xcc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frecpx z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xcc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frecpx z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xcc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frecpx z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x4c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frecpx z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x8c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frecpx z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xcc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frecpx z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xcc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frecpx z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xcc, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frecpx z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/frinta.s.yaml b/tests/MC/AArch64/SVE/frinta.s.yaml new file mode 100644 index 0000000000..9a59fabd17 --- /dev/null +++ b/tests/MC/AArch64/SVE/frinta.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x44, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frinta z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x84, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frinta z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xc4, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frinta z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc4, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frinta z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc4, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frinta z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x44, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frinta z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x84, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frinta z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xc4, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frinta z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc4, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frinta z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc4, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frinta z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/frinti.s.yaml b/tests/MC/AArch64/SVE/frinti.s.yaml new file mode 100644 index 0000000000..ada70be261 --- /dev/null +++ b/tests/MC/AArch64/SVE/frinti.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x47, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frinti z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x87, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frinti z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xc7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frinti z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frinti z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frinti z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x47, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frinti z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x87, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frinti z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xc7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frinti z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frinti z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frinti z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/frintm.s.yaml b/tests/MC/AArch64/SVE/frintm.s.yaml new file mode 100644 index 0000000000..79af7c0b1d --- /dev/null +++ b/tests/MC/AArch64/SVE/frintm.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x42, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintm z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x82, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintm z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xc2, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintm z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc2, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintm z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc2, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintm z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x42, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintm z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x82, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintm z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xc2, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintm z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc2, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintm z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc2, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintm z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/frintn.s.yaml b/tests/MC/AArch64/SVE/frintn.s.yaml new file mode 100644 index 0000000000..01107f1799 --- /dev/null +++ b/tests/MC/AArch64/SVE/frintn.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x40, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintn z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x80, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintn z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintn z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintn z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintn z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x40, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintn z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x80, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintn z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintn z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintn z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintn z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/frintp.s.yaml b/tests/MC/AArch64/SVE/frintp.s.yaml new file mode 100644 index 0000000000..11f725b24e --- /dev/null +++ b/tests/MC/AArch64/SVE/frintp.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x41, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintp z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x81, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintp z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintp z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintp z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintp z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x41, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintp z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x81, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintp z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintp z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintp z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintp z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/frintx.s.yaml b/tests/MC/AArch64/SVE/frintx.s.yaml new file mode 100644 index 0000000000..aa0822791f --- /dev/null +++ b/tests/MC/AArch64/SVE/frintx.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x46, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintx z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x86, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintx z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xc6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintx z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintx z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintx z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x46, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintx z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x86, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintx z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xc6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintx z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintx z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintx z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/frintz.s.yaml b/tests/MC/AArch64/SVE/frintz.s.yaml new file mode 100644 index 0000000000..111787b722 --- /dev/null +++ b/tests/MC/AArch64/SVE/frintz.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x43, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintz z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x83, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintz z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xc3, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintz z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc3, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintz z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc3, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frintz z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x43, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintz z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x83, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintz z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xc3, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintz z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc3, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintz z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xc3, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frintz z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/frsqrte.s.yaml b/tests/MC/AArch64/SVE/frsqrte.s.yaml new file mode 100644 index 0000000000..3ce84b3b84 --- /dev/null +++ b/tests/MC/AArch64/SVE/frsqrte.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x33, 0x4f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frsqrte z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x33, 0x8f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frsqrte z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x33, 0xcf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frsqrte z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x33, 0x4f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frsqrte z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x33, 0x8f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frsqrte z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x33, 0xcf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frsqrte z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/frsqrts.s.yaml b/tests/MC/AArch64/SVE/frsqrts.s.yaml new file mode 100644 index 0000000000..5e697b092f --- /dev/null +++ b/tests/MC/AArch64/SVE/frsqrts.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x1c, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frsqrts z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x1c, 0x9f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frsqrts z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x1c, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "frsqrts z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x1c, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frsqrts z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x1c, 0x9f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frsqrts z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x1c, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "frsqrts z0.d, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE/fscale.s.yaml b/tests/MC/AArch64/SVE/fscale.s.yaml new file mode 100644 index 0000000000..7f8a8d5637 --- /dev/null +++ b/tests/MC/AArch64/SVE/fscale.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x9f, 0x49, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fscale z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x89, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fscale z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc9, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fscale z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc9, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fscale z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc9, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fscale z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0x49, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fscale z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x89, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fscale z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc9, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fscale z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc9, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fscale z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc9, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fscale z0.d, p7/m, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/fsqrt.s.yaml b/tests/MC/AArch64/SVE/fsqrt.s.yaml new file mode 100644 index 0000000000..846098c832 --- /dev/null +++ b/tests/MC/AArch64/SVE/fsqrt.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x4d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsqrt z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x8d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsqrt z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xcd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsqrt z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xcd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsqrt z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xcd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsqrt z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x4d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsqrt z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x8d, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsqrt z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xcd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsqrt z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xcd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsqrt z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xcd, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsqrt z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/fsub.s.yaml b/tests/MC/AArch64/SVE/fsub.s.yaml new file mode 100644 index 0000000000..60ea3f0188 --- /dev/null +++ b/tests/MC/AArch64/SVE/fsub.s.yaml @@ -0,0 +1,440 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x59, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsub z0.h, p0/m, z0.h, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0x59, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsub z0.h, p0/m, z0.h, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0x99, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsub z0.s, p0/m, z0.s, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0xd9, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsub z0.d, p0/m, z0.d, #0.5" + + - + input: + bytes: [ 0x3f, 0x9c, 0x59, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsub z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x59, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsub z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x99, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsub z31.s, p7/m, z31.s, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0xd9, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsub z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x9f, 0x41, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsub z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x81, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsub z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsub z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0x20, 0x04, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsub z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x04, 0x9f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsub z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x04, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsub z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p7/z, z6.d" + + - + input: + bytes: [ 0x3f, 0x9c, 0xd9, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsub z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x3f, 0x9c, 0xd9, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsub z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsub z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsub z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0x00, 0x80, 0x59, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsub z0.h, p0/m, z0.h, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0x59, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsub z0.h, p0/m, z0.h, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0x99, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsub z0.s, p0/m, z0.s, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0xd9, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsub z0.d, p0/m, z0.d, #0.5" + + - + input: + bytes: [ 0x3f, 0x9c, 0x59, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsub z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x59, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsub z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x99, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsub z31.s, p7/m, z31.s, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0xd9, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsub z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x9f, 0x41, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsub z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x81, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsub z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsub z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0x20, 0x04, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsub z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x04, 0x9f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsub z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x04, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsub z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p7/z, z6.d" + + - + input: + bytes: [ 0x3f, 0x9c, 0xd9, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsub z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x3f, 0x9c, 0xd9, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsub z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsub z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsub z0.d, p7/m, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/fsubr.s.yaml b/tests/MC/AArch64/SVE/fsubr.s.yaml new file mode 100644 index 0000000000..9d2636d4d4 --- /dev/null +++ b/tests/MC/AArch64/SVE/fsubr.s.yaml @@ -0,0 +1,380 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x5b, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsubr z0.h, p0/m, z0.h, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0x5b, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsubr z0.h, p0/m, z0.h, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0x9b, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsubr z0.s, p0/m, z0.s, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0xdb, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsubr z0.d, p0/m, z0.d, #0.5" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5b, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsubr z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5b, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsubr z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x9b, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsubr z31.s, p7/m, z31.s, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdb, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsubr z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x9f, 0x43, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsubr z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x83, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsubr z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc3, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsubr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p7/z, z6.d" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdb, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsubr z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdb, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsubr z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc3, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsubr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc3, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "fsubr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0x00, 0x80, 0x5b, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsubr z0.h, p0/m, z0.h, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0x5b, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsubr z0.h, p0/m, z0.h, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0x9b, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsubr z0.s, p0/m, z0.s, #0.5" + + - + input: + bytes: [ 0x00, 0x80, 0xdb, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsubr z0.d, p0/m, z0.d, #0.5" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5b, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsubr z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x5b, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsubr z31.h, p7/m, z31.h, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0x9b, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsubr z31.s, p7/m, z31.s, #1.0" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdb, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsubr z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x9f, 0x43, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsubr z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0x83, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsubr z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc3, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsubr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p7/z, z6.d" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdb, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsubr z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x3f, 0x9c, 0xdb, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsubr z31.d, p7/m, z31.d, #1.0" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc3, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsubr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xc3, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fsubr z0.d, p7/m, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/ftmad.s.yaml b/tests/MC/AArch64/SVE/ftmad.s.yaml new file mode 100644 index 0000000000..5b9c74afee --- /dev/null +++ b/tests/MC/AArch64/SVE/ftmad.s.yaml @@ -0,0 +1,50 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x83, 0x57, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ftmad z0.h, z0.h, z31.h, #7" + + - + input: + bytes: [ 0xe0, 0x83, 0x97, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ftmad z0.s, z0.s, z31.s, #7" + + - + input: + bytes: [ 0xe0, 0x83, 0xd7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ftmad z0.d, z0.d, z31.d, #7" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x83, 0xd7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ftmad z0.d, z0.d, z31.d, #7" diff --git a/tests/MC/AArch64/SVE/ftsmul.s.yaml b/tests/MC/AArch64/SVE/ftsmul.s.yaml new file mode 100644 index 0000000000..27545c04b1 --- /dev/null +++ b/tests/MC/AArch64/SVE/ftsmul.s.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x0c, 0x5f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ftsmul z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x0c, 0x9f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ftsmul z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x0c, 0xdf, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ftsmul z0.d, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE/ftssel.s.yaml b/tests/MC/AArch64/SVE/ftssel.s.yaml new file mode 100644 index 0000000000..767039ba82 --- /dev/null +++ b/tests/MC/AArch64/SVE/ftssel.s.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xb0, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ftssel z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xb0, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ftssel z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xb0, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ftssel z0.d, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE/incb.s.yaml b/tests/MC/AArch64/SVE/incb.s.yaml new file mode 100644 index 0000000000..fee45fb9a8 --- /dev/null +++ b/tests/MC/AArch64/SVE/incb.s.yaml @@ -0,0 +1,660 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xe3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, pow2" + + - + input: + bytes: [ 0x20, 0xe0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, vl1" + + - + input: + bytes: [ 0x40, 0xe0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, vl2" + + - + input: + bytes: [ 0x60, 0xe0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, vl3" + + - + input: + bytes: [ 0x80, 0xe0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, vl4" + + - + input: + bytes: [ 0xa0, 0xe0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, vl5" + + - + input: + bytes: [ 0xc0, 0xe0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, vl6" + + - + input: + bytes: [ 0xe0, 0xe0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, vl7" + + - + input: + bytes: [ 0x00, 0xe1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, vl8" + + - + input: + bytes: [ 0x20, 0xe1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, vl16" + + - + input: + bytes: [ 0x40, 0xe1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, vl32" + + - + input: + bytes: [ 0x60, 0xe1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, vl64" + + - + input: + bytes: [ 0x80, 0xe1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, vl128" + + - + input: + bytes: [ 0xa0, 0xe1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, vl256" + + - + input: + bytes: [ 0xc0, 0xe1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, #14" + + - + input: + bytes: [ 0xe0, 0xe1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, #15" + + - + input: + bytes: [ 0x00, 0xe2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, #16" + + - + input: + bytes: [ 0x20, 0xe2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, #17" + + - + input: + bytes: [ 0x40, 0xe2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, #18" + + - + input: + bytes: [ 0x60, 0xe2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, #19" + + - + input: + bytes: [ 0x80, 0xe2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, #20" + + - + input: + bytes: [ 0xa0, 0xe2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, #21" + + - + input: + bytes: [ 0xc0, 0xe2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, #22" + + - + input: + bytes: [ 0xe0, 0xe2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, #23" + + - + input: + bytes: [ 0x00, 0xe3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, #24" + + - + input: + bytes: [ 0x20, 0xe3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, #25" + + - + input: + bytes: [ 0x40, 0xe3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, #26" + + - + input: + bytes: [ 0x60, 0xe3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, #27" + + - + input: + bytes: [ 0x80, 0xe3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incb x0, #28" + + - + input: + bytes: [ 0xe0, 0xe3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, pow2" + + - + input: + bytes: [ 0x20, 0xe0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, vl1" + + - + input: + bytes: [ 0x40, 0xe0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, vl2" + + - + input: + bytes: [ 0x60, 0xe0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, vl3" + + - + input: + bytes: [ 0x80, 0xe0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, vl4" + + - + input: + bytes: [ 0xa0, 0xe0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, vl5" + + - + input: + bytes: [ 0xc0, 0xe0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, vl6" + + - + input: + bytes: [ 0xe0, 0xe0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, vl7" + + - + input: + bytes: [ 0x00, 0xe1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, vl8" + + - + input: + bytes: [ 0x20, 0xe1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, vl16" + + - + input: + bytes: [ 0x40, 0xe1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, vl32" + + - + input: + bytes: [ 0x60, 0xe1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, vl64" + + - + input: + bytes: [ 0x80, 0xe1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, vl128" + + - + input: + bytes: [ 0xa0, 0xe1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, vl256" + + - + input: + bytes: [ 0xc0, 0xe1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, #14" + + - + input: + bytes: [ 0xe0, 0xe1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, #15" + + - + input: + bytes: [ 0x00, 0xe2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, #16" + + - + input: + bytes: [ 0x20, 0xe2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, #17" + + - + input: + bytes: [ 0x40, 0xe2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, #18" + + - + input: + bytes: [ 0x60, 0xe2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, #19" + + - + input: + bytes: [ 0x80, 0xe2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, #20" + + - + input: + bytes: [ 0xa0, 0xe2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, #21" + + - + input: + bytes: [ 0xc0, 0xe2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, #22" + + - + input: + bytes: [ 0xe0, 0xe2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, #23" + + - + input: + bytes: [ 0x00, 0xe3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, #24" + + - + input: + bytes: [ 0x20, 0xe3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, #25" + + - + input: + bytes: [ 0x40, 0xe3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, #26" + + - + input: + bytes: [ 0x60, 0xe3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, #27" + + - + input: + bytes: [ 0x80, 0xe3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incb x0, #28" diff --git a/tests/MC/AArch64/SVE/incd.s.yaml b/tests/MC/AArch64/SVE/incd.s.yaml new file mode 100644 index 0000000000..9645847a07 --- /dev/null +++ b/tests/MC/AArch64/SVE/incd.s.yaml @@ -0,0 +1,600 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd z0.d" + + - + input: + bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd z0.d" + + - + input: + bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd z0.d" + + - + input: + bytes: [ 0xe0, 0xc3, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd z0.d, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xe3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0, pow2" + + - + input: + bytes: [ 0x20, 0xe0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0, vl1" + + - + input: + bytes: [ 0x40, 0xe0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0, vl2" + + - + input: + bytes: [ 0x60, 0xe0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0, vl3" + + - + input: + bytes: [ 0x80, 0xe0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0, vl4" + + - + input: + bytes: [ 0xa0, 0xe0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0, vl5" + + - + input: + bytes: [ 0xc0, 0xe0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0, vl6" + + - + input: + bytes: [ 0xe0, 0xe0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0, vl7" + + - + input: + bytes: [ 0x00, 0xe1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0, vl8" + + - + input: + bytes: [ 0x20, 0xe1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0, vl16" + + - + input: + bytes: [ 0x40, 0xe1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0, vl32" + + - + input: + bytes: [ 0x60, 0xe1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0, vl64" + + - + input: + bytes: [ 0x80, 0xe1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0, vl128" + + - + input: + bytes: [ 0xa0, 0xe1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0, vl256" + + - + input: + bytes: [ 0xc0, 0xe1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0, #14" + + - + input: + bytes: [ 0x80, 0xe3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd z0.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd z0.d, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incd z0.d" + + - + input: + bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd z0.d" + + - + input: + bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd z0.d" + + - + input: + bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd z0.d" + + - + input: + bytes: [ 0xe0, 0xc3, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd z0.d, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xe3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0, pow2" + + - + input: + bytes: [ 0x20, 0xe0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0, vl1" + + - + input: + bytes: [ 0x40, 0xe0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0, vl2" + + - + input: + bytes: [ 0x60, 0xe0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0, vl3" + + - + input: + bytes: [ 0x80, 0xe0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0, vl4" + + - + input: + bytes: [ 0xa0, 0xe0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0, vl5" + + - + input: + bytes: [ 0xc0, 0xe0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0, vl6" + + - + input: + bytes: [ 0xe0, 0xe0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0, vl7" + + - + input: + bytes: [ 0x00, 0xe1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0, vl8" + + - + input: + bytes: [ 0x20, 0xe1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0, vl16" + + - + input: + bytes: [ 0x40, 0xe1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0, vl32" + + - + input: + bytes: [ 0x60, 0xe1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0, vl64" + + - + input: + bytes: [ 0x80, 0xe1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0, vl128" + + - + input: + bytes: [ 0xa0, 0xe1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0, vl256" + + - + input: + bytes: [ 0xc0, 0xe1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0, #14" + + - + input: + bytes: [ 0x80, 0xe3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd z0.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd z0.d, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incd z0.d" diff --git a/tests/MC/AArch64/SVE/inch.s.yaml b/tests/MC/AArch64/SVE/inch.s.yaml new file mode 100644 index 0000000000..a5b87e3504 --- /dev/null +++ b/tests/MC/AArch64/SVE/inch.s.yaml @@ -0,0 +1,600 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xc3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch z0.h" + + - + input: + bytes: [ 0xe0, 0xc3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch z0.h" + + - + input: + bytes: [ 0xe0, 0xc3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch z0.h" + + - + input: + bytes: [ 0xe0, 0xc3, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch z0.h, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xe3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0, pow2" + + - + input: + bytes: [ 0x20, 0xe0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0, vl1" + + - + input: + bytes: [ 0x40, 0xe0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0, vl2" + + - + input: + bytes: [ 0x60, 0xe0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0, vl3" + + - + input: + bytes: [ 0x80, 0xe0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0, vl4" + + - + input: + bytes: [ 0xa0, 0xe0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0, vl5" + + - + input: + bytes: [ 0xc0, 0xe0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0, vl6" + + - + input: + bytes: [ 0xe0, 0xe0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0, vl7" + + - + input: + bytes: [ 0x00, 0xe1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0, vl8" + + - + input: + bytes: [ 0x20, 0xe1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0, vl16" + + - + input: + bytes: [ 0x40, 0xe1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0, vl32" + + - + input: + bytes: [ 0x60, 0xe1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0, vl64" + + - + input: + bytes: [ 0x80, 0xe1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0, vl128" + + - + input: + bytes: [ 0xa0, 0xe1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0, vl256" + + - + input: + bytes: [ 0xc0, 0xe1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0, #14" + + - + input: + bytes: [ 0x80, 0xe3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch z0.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch z0.h, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "inch z0.h" + + - + input: + bytes: [ 0xe0, 0xc3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch z0.h" + + - + input: + bytes: [ 0xe0, 0xc3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch z0.h" + + - + input: + bytes: [ 0xe0, 0xc3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch z0.h" + + - + input: + bytes: [ 0xe0, 0xc3, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch z0.h, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xe3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0, pow2" + + - + input: + bytes: [ 0x20, 0xe0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0, vl1" + + - + input: + bytes: [ 0x40, 0xe0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0, vl2" + + - + input: + bytes: [ 0x60, 0xe0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0, vl3" + + - + input: + bytes: [ 0x80, 0xe0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0, vl4" + + - + input: + bytes: [ 0xa0, 0xe0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0, vl5" + + - + input: + bytes: [ 0xc0, 0xe0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0, vl6" + + - + input: + bytes: [ 0xe0, 0xe0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0, vl7" + + - + input: + bytes: [ 0x00, 0xe1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0, vl8" + + - + input: + bytes: [ 0x20, 0xe1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0, vl16" + + - + input: + bytes: [ 0x40, 0xe1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0, vl32" + + - + input: + bytes: [ 0x60, 0xe1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0, vl64" + + - + input: + bytes: [ 0x80, 0xe1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0, vl128" + + - + input: + bytes: [ 0xa0, 0xe1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0, vl256" + + - + input: + bytes: [ 0xc0, 0xe1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0, #14" + + - + input: + bytes: [ 0x80, 0xe3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch z0.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch z0.h, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "inch z0.h" diff --git a/tests/MC/AArch64/SVE/incp.s.yaml b/tests/MC/AArch64/SVE/incp.s.yaml new file mode 100644 index 0000000000..d2823f8dbd --- /dev/null +++ b/tests/MC/AArch64/SVE/incp.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x88, 0x2c, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incp x0, p0.b" + + - + input: + bytes: [ 0x00, 0x88, 0x6c, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incp x0, p0.h" + + - + input: + bytes: [ 0x00, 0x88, 0xac, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incp x0, p0.s" + + - + input: + bytes: [ 0x00, 0x88, 0xec, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incp x0, p0.d" + + - + input: + bytes: [ 0xff, 0x89, 0x2c, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incp xzr, p15.b" + + - + input: + bytes: [ 0xff, 0x89, 0x6c, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incp xzr, p15.h" + + - + input: + bytes: [ 0xff, 0x89, 0xac, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incp xzr, p15.s" + + - + input: + bytes: [ 0xff, 0x89, 0xec, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incp xzr, p15.d" + + - + input: + bytes: [ 0xff, 0x81, 0x6c, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incp z31.h, p15.h" + + - + input: + bytes: [ 0xff, 0x81, 0x6c, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incp z31.h, p15.h" + + - + input: + bytes: [ 0xff, 0x81, 0xac, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incp z31.s, p15.s" + + - + input: + bytes: [ 0xff, 0x81, 0xac, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incp z31.s, p15.s" + + - + input: + bytes: [ 0xff, 0x81, 0xec, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incp z31.d, p15.d" + + - + input: + bytes: [ 0xff, 0x81, 0xec, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incp z31.d, p15.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0x81, 0xec, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incp z31.d, p15.d" + + - + input: + bytes: [ 0x00, 0x88, 0x2c, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incp x0, p0.b" + + - + input: + bytes: [ 0x00, 0x88, 0x6c, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incp x0, p0.h" + + - + input: + bytes: [ 0x00, 0x88, 0xac, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incp x0, p0.s" + + - + input: + bytes: [ 0x00, 0x88, 0xec, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incp x0, p0.d" + + - + input: + bytes: [ 0xff, 0x89, 0x2c, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incp xzr, p15.b" + + - + input: + bytes: [ 0xff, 0x89, 0x6c, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incp xzr, p15.h" + + - + input: + bytes: [ 0xff, 0x89, 0xac, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incp xzr, p15.s" + + - + input: + bytes: [ 0xff, 0x89, 0xec, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incp xzr, p15.d" + + - + input: + bytes: [ 0xff, 0x81, 0x6c, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incp z31.h, p15.h" + + - + input: + bytes: [ 0xff, 0x81, 0x6c, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incp z31.h, p15.h" + + - + input: + bytes: [ 0xff, 0x81, 0xac, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incp z31.s, p15.s" + + - + input: + bytes: [ 0xff, 0x81, 0xac, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incp z31.s, p15.s" + + - + input: + bytes: [ 0xff, 0x81, 0xec, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incp z31.d, p15.d" + + - + input: + bytes: [ 0xff, 0x81, 0xec, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incp z31.d, p15.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0x81, 0xec, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incp z31.d, p15.d" diff --git a/tests/MC/AArch64/SVE/incw.s.yaml b/tests/MC/AArch64/SVE/incw.s.yaml new file mode 100644 index 0000000000..db47d99660 --- /dev/null +++ b/tests/MC/AArch64/SVE/incw.s.yaml @@ -0,0 +1,600 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw z0.s" + + - + input: + bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw z0.s" + + - + input: + bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw z0.s" + + - + input: + bytes: [ 0xe0, 0xc3, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw z0.s, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xe3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0, pow2" + + - + input: + bytes: [ 0x20, 0xe0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0, vl1" + + - + input: + bytes: [ 0x40, 0xe0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0, vl2" + + - + input: + bytes: [ 0x60, 0xe0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0, vl3" + + - + input: + bytes: [ 0x80, 0xe0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0, vl4" + + - + input: + bytes: [ 0xa0, 0xe0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0, vl5" + + - + input: + bytes: [ 0xc0, 0xe0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0, vl6" + + - + input: + bytes: [ 0xe0, 0xe0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0, vl7" + + - + input: + bytes: [ 0x00, 0xe1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0, vl8" + + - + input: + bytes: [ 0x20, 0xe1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0, vl16" + + - + input: + bytes: [ 0x40, 0xe1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0, vl32" + + - + input: + bytes: [ 0x60, 0xe1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0, vl64" + + - + input: + bytes: [ 0x80, 0xe1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0, vl128" + + - + input: + bytes: [ 0xa0, 0xe1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0, vl256" + + - + input: + bytes: [ 0xc0, 0xe1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0, #14" + + - + input: + bytes: [ 0x80, 0xe3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw z0.s" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw z0.s, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "incw z0.s" + + - + input: + bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw z0.s" + + - + input: + bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw z0.s" + + - + input: + bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw z0.s" + + - + input: + bytes: [ 0xe0, 0xc3, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw z0.s, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xe3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0" + + - + input: + bytes: [ 0xe0, 0xe3, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xe0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0, pow2" + + - + input: + bytes: [ 0x20, 0xe0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0, vl1" + + - + input: + bytes: [ 0x40, 0xe0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0, vl2" + + - + input: + bytes: [ 0x60, 0xe0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0, vl3" + + - + input: + bytes: [ 0x80, 0xe0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0, vl4" + + - + input: + bytes: [ 0xa0, 0xe0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0, vl5" + + - + input: + bytes: [ 0xc0, 0xe0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0, vl6" + + - + input: + bytes: [ 0xe0, 0xe0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0, vl7" + + - + input: + bytes: [ 0x00, 0xe1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0, vl8" + + - + input: + bytes: [ 0x20, 0xe1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0, vl16" + + - + input: + bytes: [ 0x40, 0xe1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0, vl32" + + - + input: + bytes: [ 0x60, 0xe1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0, vl64" + + - + input: + bytes: [ 0x80, 0xe1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0, vl128" + + - + input: + bytes: [ 0xa0, 0xe1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0, vl256" + + - + input: + bytes: [ 0xc0, 0xe1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0, #14" + + - + input: + bytes: [ 0x80, 0xe3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw z0.s" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw z0.s, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "incw z0.s" diff --git a/tests/MC/AArch64/SVE/index.s.yaml b/tests/MC/AArch64/SVE/index.s.yaml new file mode 100644 index 0000000000..503e55273a --- /dev/null +++ b/tests/MC/AArch64/SVE/index.s.yaml @@ -0,0 +1,640 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z0.b, #0, #0" + + - + input: + bytes: [ 0xff, 0x43, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z31.b, #-1, #-1" + + - + input: + bytes: [ 0x00, 0x40, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z0.h, #0, #0" + + - + input: + bytes: [ 0xff, 0x43, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z31.h, #-1, #-1" + + - + input: + bytes: [ 0x00, 0x40, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z0.s, #0, #0" + + - + input: + bytes: [ 0xff, 0x43, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z31.s, #-1, #-1" + + - + input: + bytes: [ 0x00, 0x40, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z0.d, #0, #0" + + - + input: + bytes: [ 0xff, 0x43, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z31.d, #-1, #-1" + + - + input: + bytes: [ 0xff, 0x4b, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z31.b, #-1, wzr" + + - + input: + bytes: [ 0xb7, 0x49, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z23.b, #13, w8" + + - + input: + bytes: [ 0xff, 0x4b, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z31.h, #-1, wzr" + + - + input: + bytes: [ 0xb7, 0x49, 0x68, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z23.h, #13, w8" + + - + input: + bytes: [ 0xff, 0x4b, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z31.s, #-1, wzr" + + - + input: + bytes: [ 0xb7, 0x49, 0xa8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z23.s, #13, w8" + + - + input: + bytes: [ 0xff, 0x4b, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z31.d, #-1, xzr" + + - + input: + bytes: [ 0xb7, 0x49, 0xe8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z23.d, #13, x8" + + - + input: + bytes: [ 0xff, 0x47, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z31.b, wzr, #-1" + + - + input: + bytes: [ 0xb7, 0x45, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z23.b, w13, #8" + + - + input: + bytes: [ 0xff, 0x47, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z31.h, wzr, #-1" + + - + input: + bytes: [ 0xb7, 0x45, 0x68, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z23.h, w13, #8" + + - + input: + bytes: [ 0xff, 0x47, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z31.s, wzr, #-1" + + - + input: + bytes: [ 0xb7, 0x45, 0xa8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z23.s, w13, #8" + + - + input: + bytes: [ 0xff, 0x47, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z31.d, xzr, #-1" + + - + input: + bytes: [ 0xb7, 0x45, 0xe8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z23.d, x13, #8" + + - + input: + bytes: [ 0xff, 0x4f, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z31.b, wzr, wzr" + + - + input: + bytes: [ 0x55, 0x4d, 0x35, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z21.b, w10, w21" + + - + input: + bytes: [ 0xff, 0x4f, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z31.h, wzr, wzr" + + - + input: + bytes: [ 0x00, 0x4c, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z0.h, w0, w0" + + - + input: + bytes: [ 0xff, 0x4f, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z31.s, wzr, wzr" + + - + input: + bytes: [ 0x55, 0x4d, 0xb5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z21.s, w10, w21" + + - + input: + bytes: [ 0xff, 0x4f, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z31.d, xzr, xzr" + + - + input: + bytes: [ 0x55, 0x4d, 0xf5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "index z21.d, x10, x21" + + - + input: + bytes: [ 0x00, 0x40, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z0.b, #0, #0" + + - + input: + bytes: [ 0xff, 0x43, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z31.b, #-1, #-1" + + - + input: + bytes: [ 0x00, 0x40, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z0.h, #0, #0" + + - + input: + bytes: [ 0xff, 0x43, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z31.h, #-1, #-1" + + - + input: + bytes: [ 0x00, 0x40, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z0.s, #0, #0" + + - + input: + bytes: [ 0xff, 0x43, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z31.s, #-1, #-1" + + - + input: + bytes: [ 0x00, 0x40, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z0.d, #0, #0" + + - + input: + bytes: [ 0xff, 0x43, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z31.d, #-1, #-1" + + - + input: + bytes: [ 0xff, 0x4b, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z31.b, #-1, wzr" + + - + input: + bytes: [ 0xb7, 0x49, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z23.b, #13, w8" + + - + input: + bytes: [ 0xff, 0x4b, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z31.h, #-1, wzr" + + - + input: + bytes: [ 0xb7, 0x49, 0x68, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z23.h, #13, w8" + + - + input: + bytes: [ 0xff, 0x4b, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z31.s, #-1, wzr" + + - + input: + bytes: [ 0xb7, 0x49, 0xa8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z23.s, #13, w8" + + - + input: + bytes: [ 0xff, 0x4b, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z31.d, #-1, xzr" + + - + input: + bytes: [ 0xb7, 0x49, 0xe8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z23.d, #13, x8" + + - + input: + bytes: [ 0xff, 0x47, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z31.b, wzr, #-1" + + - + input: + bytes: [ 0xb7, 0x45, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z23.b, w13, #8" + + - + input: + bytes: [ 0xff, 0x47, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z31.h, wzr, #-1" + + - + input: + bytes: [ 0xb7, 0x45, 0x68, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z23.h, w13, #8" + + - + input: + bytes: [ 0xff, 0x47, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z31.s, wzr, #-1" + + - + input: + bytes: [ 0xb7, 0x45, 0xa8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z23.s, w13, #8" + + - + input: + bytes: [ 0xff, 0x47, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z31.d, xzr, #-1" + + - + input: + bytes: [ 0xb7, 0x45, 0xe8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z23.d, x13, #8" + + - + input: + bytes: [ 0xff, 0x4f, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z31.b, wzr, wzr" + + - + input: + bytes: [ 0x55, 0x4d, 0x35, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z21.b, w10, w21" + + - + input: + bytes: [ 0xff, 0x4f, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z31.h, wzr, wzr" + + - + input: + bytes: [ 0x00, 0x4c, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z0.h, w0, w0" + + - + input: + bytes: [ 0xff, 0x4f, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z31.s, wzr, wzr" + + - + input: + bytes: [ 0x55, 0x4d, 0xb5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z21.s, w10, w21" + + - + input: + bytes: [ 0xff, 0x4f, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z31.d, xzr, xzr" + + - + input: + bytes: [ 0x55, 0x4d, 0xf5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "index z21.d, x10, x21" diff --git a/tests/MC/AArch64/SVE/insr.s.yaml b/tests/MC/AArch64/SVE/insr.s.yaml new file mode 100644 index 0000000000..06fa3c4b52 --- /dev/null +++ b/tests/MC/AArch64/SVE/insr.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x38, 0x24, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "insr z0.b, w0" + + - + input: + bytes: [ 0x00, 0x38, 0x64, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "insr z0.h, w0" + + - + input: + bytes: [ 0x00, 0x38, 0xa4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "insr z0.s, w0" + + - + input: + bytes: [ 0x00, 0x38, 0xe4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "insr z0.d, x0" + + - + input: + bytes: [ 0xff, 0x3b, 0x24, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "insr z31.b, wzr" + + - + input: + bytes: [ 0xff, 0x3b, 0x64, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "insr z31.h, wzr" + + - + input: + bytes: [ 0xff, 0x3b, 0xa4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "insr z31.s, wzr" + + - + input: + bytes: [ 0xff, 0x3b, 0xe4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "insr z31.d, xzr" + + - + input: + bytes: [ 0xff, 0x3b, 0x34, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "insr z31.b, b31" + + - + input: + bytes: [ 0xff, 0x3b, 0x74, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "insr z31.h, h31" + + - + input: + bytes: [ 0xff, 0x3b, 0xb4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "insr z31.s, s31" + + - + input: + bytes: [ 0xff, 0x3b, 0xf4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "insr z31.d, d31" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0x3b, 0xe4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "insr z31.d, xzr" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x3b, 0xf4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "insr z4.d, d31" + + - + input: + bytes: [ 0x00, 0x38, 0x24, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "insr z0.b, w0" + + - + input: + bytes: [ 0x00, 0x38, 0x64, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "insr z0.h, w0" + + - + input: + bytes: [ 0x00, 0x38, 0xa4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "insr z0.s, w0" + + - + input: + bytes: [ 0x00, 0x38, 0xe4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "insr z0.d, x0" + + - + input: + bytes: [ 0xff, 0x3b, 0x24, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "insr z31.b, wzr" + + - + input: + bytes: [ 0xff, 0x3b, 0x64, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "insr z31.h, wzr" + + - + input: + bytes: [ 0xff, 0x3b, 0xa4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "insr z31.s, wzr" + + - + input: + bytes: [ 0xff, 0x3b, 0xe4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "insr z31.d, xzr" + + - + input: + bytes: [ 0xff, 0x3b, 0x34, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "insr z31.b, b31" + + - + input: + bytes: [ 0xff, 0x3b, 0x74, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "insr z31.h, h31" + + - + input: + bytes: [ 0xff, 0x3b, 0xb4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "insr z31.s, s31" + + - + input: + bytes: [ 0xff, 0x3b, 0xf4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "insr z31.d, d31" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0x3b, 0xe4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "insr z31.d, xzr" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x3b, 0xf4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "insr z4.d, d31" diff --git a/tests/MC/AArch64/SVE/lasta.s.yaml b/tests/MC/AArch64/SVE/lasta.s.yaml new file mode 100644 index 0000000000..e8d1546861 --- /dev/null +++ b/tests/MC/AArch64/SVE/lasta.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xbf, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lasta w0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0xbf, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lasta w0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0xbf, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lasta w0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0xbf, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lasta x0, p7, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0x22, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lasta b0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x9f, 0x62, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lasta h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0xa2, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lasta s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe2, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lasta d0, p7, z31.d" + + - + input: + bytes: [ 0xe0, 0xbf, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lasta w0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0xbf, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lasta w0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0xbf, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lasta w0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0xbf, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lasta x0, p7, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0x22, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lasta b0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x9f, 0x62, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lasta h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0xa2, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lasta s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe2, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lasta d0, p7, z31.d" diff --git a/tests/MC/AArch64/SVE/lastb.s.yaml b/tests/MC/AArch64/SVE/lastb.s.yaml new file mode 100644 index 0000000000..7f2f0afd25 --- /dev/null +++ b/tests/MC/AArch64/SVE/lastb.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xbf, 0x21, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lastb w0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0xbf, 0x61, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lastb w0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0xbf, 0xa1, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lastb w0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0xbf, 0xe1, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lastb x0, p7, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0x23, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lastb b0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x9f, 0x63, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lastb h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0xa3, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lastb s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe3, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lastb d0, p7, z31.d" + + - + input: + bytes: [ 0xe0, 0xbf, 0x21, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lastb w0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0xbf, 0x61, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lastb w0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0xbf, 0xa1, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lastb w0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0xbf, 0xe1, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lastb x0, p7, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0x23, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lastb b0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x9f, 0x63, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lastb h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0xa3, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lastb s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe3, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lastb d0, p7, z31.d" diff --git a/tests/MC/AArch64/SVE/ld1b-sve-only.s.yaml b/tests/MC/AArch64/SVE/ld1b-sve-only.s.yaml new file mode 100644 index 0000000000..bbb93a96f6 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1b-sve-only.s.yaml @@ -0,0 +1,90 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0x00, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z0.s }, p0/z, [x0, z0.s, uxtw]" + + - + input: + bytes: [ 0x00, 0x40, 0x40, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z0.s }, p0/z, [x0, z0.s, sxtw]" + + - + input: + bytes: [ 0xff, 0xdf, 0x5f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z31.d }, p7/z, [sp, z31.d]" + + - + input: + bytes: [ 0x55, 0x55, 0x15, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z21.d }, p5/z, [x10, z21.d, uxtw]" + + - + input: + bytes: [ 0x55, 0x55, 0x55, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z21.d }, p5/z, [x10, z21.d, sxtw]" + + - + input: + bytes: [ 0xff, 0xdf, 0x3f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z31.s }, p7/z, [z31.s, #31]" + + - + input: + bytes: [ 0x00, 0xc0, 0x20, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z0.s }, p0/z, [z0.s]" + + - + input: + bytes: [ 0xff, 0xdf, 0x3f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z31.d }, p7/z, [z31.d, #31]" + + - + input: + bytes: [ 0x00, 0xc0, 0x20, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z0.d }, p0/z, [z0.d]" diff --git a/tests/MC/AArch64/SVE/ld1b.s.yaml b/tests/MC/AArch64/SVE/ld1b.s.yaml new file mode 100644 index 0000000000..7659eadff2 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1b.s.yaml @@ -0,0 +1,440 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z0.b }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x20, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x60, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z0.b }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x20, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x60, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0x0f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z31.b }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x05, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z21.b }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0x2f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z31.h }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x25, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z21.h }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0x4f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z31.s }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x45, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z21.s }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0x6f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x65, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z21.d }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xe0, 0x43, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z0.b }, p0/z, [sp, x0]" + + - + input: + bytes: [ 0x00, 0x40, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z0.b }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x00, 0x40, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z0.b }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x25, 0x4e, 0x30, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z5.h }, p3/z, [x17, x16]" + + - + input: + bytes: [ 0x55, 0x55, 0x55, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z21.s }, p5/z, [x10, x21]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x68, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1b { z23.d }, p3/z, [x13, x8]" + + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z0.b }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x20, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x60, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z0.b }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x20, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x60, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0x0f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z31.b }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x05, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z21.b }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0x2f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z31.h }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x25, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z21.h }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0x4f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z31.s }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x45, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z21.s }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0x6f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x65, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z21.d }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xe0, 0x43, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z0.b }, p0/z, [sp, x0]" + + - + input: + bytes: [ 0x00, 0x40, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z0.b }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x00, 0x40, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z0.b }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x25, 0x4e, 0x30, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z5.h }, p3/z, [x17, x16]" + + - + input: + bytes: [ 0x55, 0x55, 0x55, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z21.s }, p5/z, [x10, x21]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x68, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1b { z23.d }, p3/z, [x13, x8]" diff --git a/tests/MC/AArch64/SVE/ld1d-sve-only.s.yaml b/tests/MC/AArch64/SVE/ld1d-sve-only.s.yaml new file mode 100644 index 0000000000..7dffb5bdf9 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1d-sve-only.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xdf, 0xdf, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1d { z31.d }, p7/z, [sp, z31.d]" + + - + input: + bytes: [ 0xb7, 0xcd, 0xe8, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1d { z23.d }, p3/z, [x13, z8.d, lsl #3]" + + - + input: + bytes: [ 0x55, 0x55, 0x95, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1d { z21.d }, p5/z, [x10, z21.d, uxtw]" + + - + input: + bytes: [ 0x55, 0x55, 0xd5, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1d { z21.d }, p5/z, [x10, z21.d, sxtw]" + + - + input: + bytes: [ 0x00, 0x40, 0xa0, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]" + + - + input: + bytes: [ 0x00, 0x40, 0xe0, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]" + + - + input: + bytes: [ 0xff, 0xdf, 0xbf, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1d { z31.d }, p7/z, [z31.d, #248]" + + - + input: + bytes: [ 0x00, 0xc0, 0xa0, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1d { z0.d }, p0/z, [z0.d]" diff --git a/tests/MC/AArch64/SVE/ld1d.s.yaml b/tests/MC/AArch64/SVE/ld1d.s.yaml new file mode 100644 index 0000000000..bb40eb74ca --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1d.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0xe0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1d { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xe0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1d { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0xef, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1d { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0xe5, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1d { z21.d }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xf7, 0x4f, 0xe8, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1d { z23.d }, p3/z, [sp, x8, lsl #3]" + + - + input: + bytes: [ 0xb7, 0x4d, 0xe8, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1d { z23.d }, p3/z, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0x00, 0xa0, 0xe0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xe0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0xef, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0xe5, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d { z21.d }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xf7, 0x4f, 0xe8, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d { z23.d }, p3/z, [sp, x8, lsl #3]" + + - + input: + bytes: [ 0xb7, 0x4d, 0xe8, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1d { z23.d }, p3/z, [x13, x8, lsl #3]" diff --git a/tests/MC/AArch64/SVE/ld1h-sve-only.s.yaml b/tests/MC/AArch64/SVE/ld1h-sve-only.s.yaml new file mode 100644 index 0000000000..e0e9889819 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1h-sve-only.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0x80, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z0.s }, p0/z, [x0, z0.s, uxtw]" + + - + input: + bytes: [ 0x00, 0x40, 0xc0, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z0.s }, p0/z, [x0, z0.s, sxtw]" + + - + input: + bytes: [ 0xff, 0x5f, 0xbf, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]" + + - + input: + bytes: [ 0xff, 0x5f, 0xff, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]" + + - + input: + bytes: [ 0xff, 0xdf, 0xdf, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z31.d }, p7/z, [sp, z31.d]" + + - + input: + bytes: [ 0xb7, 0xcd, 0xe8, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z23.d }, p3/z, [x13, z8.d, lsl #1]" + + - + input: + bytes: [ 0x55, 0x55, 0x95, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z21.d }, p5/z, [x10, z21.d, uxtw]" + + - + input: + bytes: [ 0x55, 0x55, 0xd5, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z21.d }, p5/z, [x10, z21.d, sxtw]" + + - + input: + bytes: [ 0x00, 0x40, 0xa0, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]" + + - + input: + bytes: [ 0x00, 0x40, 0xe0, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]" + + - + input: + bytes: [ 0xff, 0xdf, 0xbf, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z31.s }, p7/z, [z31.s, #62]" + + - + input: + bytes: [ 0x00, 0xc0, 0xa0, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z0.s }, p0/z, [z0.s]" + + - + input: + bytes: [ 0xff, 0xdf, 0xbf, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z31.d }, p7/z, [z31.d, #62]" + + - + input: + bytes: [ 0x00, 0xc0, 0xa0, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z0.d }, p0/z, [z0.d]" diff --git a/tests/MC/AArch64/SVE/ld1h.s.yaml b/tests/MC/AArch64/SVE/ld1h.s.yaml new file mode 100644 index 0000000000..2606c1ae9d --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1h.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0xa0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xc0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xe0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xa0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xc0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xe0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0xaf, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z31.h }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0xa5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z21.h }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0xcf, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z31.s }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0xc5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z21.s }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0xef, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0xe5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z21.d }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xe5, 0x4f, 0xb0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z5.h }, p3/z, [sp, x16, lsl #1]" + + - + input: + bytes: [ 0x25, 0x4e, 0xb0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z5.h }, p3/z, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x55, 0x55, 0xd5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z21.s }, p5/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb7, 0x4d, 0xe8, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1h { z23.d }, p3/z, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0x00, 0xa0, 0xa0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xc0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xe0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xa0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xc0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xe0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0xaf, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h { z31.h }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0xa5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h { z21.h }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0xcf, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h { z31.s }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0xc5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h { z21.s }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0xef, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0xe5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h { z21.d }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xe5, 0x4f, 0xb0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h { z5.h }, p3/z, [sp, x16, lsl #1]" + + - + input: + bytes: [ 0x25, 0x4e, 0xb0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h { z5.h }, p3/z, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x55, 0x55, 0xd5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h { z21.s }, p5/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb7, 0x4d, 0xe8, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1h { z23.d }, p3/z, [x13, x8, lsl #1]" diff --git a/tests/MC/AArch64/SVE/ld1rb.s.yaml b/tests/MC/AArch64/SVE/ld1rb.s.yaml new file mode 100644 index 0000000000..1286a793ec --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1rb.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x40, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rb { z0.b }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rb { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xc0, 0x40, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rb { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rb { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0x9f, 0x7f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rb { z31.b }, p7/z, [sp, #63]" + + - + input: + bytes: [ 0xff, 0xbf, 0x7f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rb { z31.h }, p7/z, [sp, #63]" + + - + input: + bytes: [ 0xff, 0xdf, 0x7f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rb { z31.s }, p7/z, [sp, #63]" + + - + input: + bytes: [ 0xff, 0xff, 0x7f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rb { z31.d }, p7/z, [sp, #63]" + + - + input: + bytes: [ 0x00, 0x80, 0x40, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rb { z0.b }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rb { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xc0, 0x40, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rb { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rb { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0x9f, 0x7f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rb { z31.b }, p7/z, [sp, #63]" + + - + input: + bytes: [ 0xff, 0xbf, 0x7f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rb { z31.h }, p7/z, [sp, #63]" + + - + input: + bytes: [ 0xff, 0xdf, 0x7f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rb { z31.s }, p7/z, [sp, #63]" + + - + input: + bytes: [ 0xff, 0xff, 0x7f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rb { z31.d }, p7/z, [sp, #63]" diff --git a/tests/MC/AArch64/SVE/ld1rd.s.yaml b/tests/MC/AArch64/SVE/ld1rd.s.yaml new file mode 100644 index 0000000000..211d429f63 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1rd.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rd { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xff, 0xff, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rd { z31.d }, p7/z, [sp, #504]" + + - + input: + bytes: [ 0x00, 0xe0, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rd { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xff, 0xff, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rd { z31.d }, p7/z, [sp, #504]" diff --git a/tests/MC/AArch64/SVE/ld1rh.s.yaml b/tests/MC/AArch64/SVE/ld1rh.s.yaml new file mode 100644 index 0000000000..83f18de92d --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1rh.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0xc0, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rh { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xc0, 0xc0, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rh { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0xc0, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rh { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0xff, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rh { z31.h }, p7/z, [sp, #126]" + + - + input: + bytes: [ 0xff, 0xdf, 0xff, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rh { z31.s }, p7/z, [sp, #126]" + + - + input: + bytes: [ 0xff, 0xff, 0xff, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rh { z31.d }, p7/z, [sp, #126]" + + - + input: + bytes: [ 0x00, 0xa0, 0xc0, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rh { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xc0, 0xc0, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rh { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0xc0, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rh { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0xff, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rh { z31.h }, p7/z, [sp, #126]" + + - + input: + bytes: [ 0xff, 0xdf, 0xff, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rh { z31.s }, p7/z, [sp, #126]" + + - + input: + bytes: [ 0xff, 0xff, 0xff, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rh { z31.d }, p7/z, [sp, #126]" diff --git a/tests/MC/AArch64/SVE/ld1rqb.s.yaml b/tests/MC/AArch64/SVE/ld1rqb.s.yaml new file mode 100644 index 0000000000..5645e87594 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1rqb.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqb { z0.b }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqb { z0.b }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0xff, 0x3f, 0x0f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqb { z31.b }, p7/z, [sp, #-16]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x08, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqb { z23.b }, p3/z, [x13, #-128]" + + - + input: + bytes: [ 0x55, 0x35, 0x07, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqb { z21.b }, p5/z, [x10, #112]" + + - + input: + bytes: [ 0x00, 0x20, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqb { z0.b }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqb { z0.b }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0xff, 0x3f, 0x0f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqb { z31.b }, p7/z, [sp, #-16]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x08, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqb { z23.b }, p3/z, [x13, #-128]" + + - + input: + bytes: [ 0x55, 0x35, 0x07, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqb { z21.b }, p5/z, [x10, #112]" diff --git a/tests/MC/AArch64/SVE/ld1rqd.s.yaml b/tests/MC/AArch64/SVE/ld1rqd.s.yaml new file mode 100644 index 0000000000..5341610213 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1rqd.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x80, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqd { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqd { z0.d }, p0/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0xff, 0x3f, 0x8f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqd { z31.d }, p7/z, [sp, #-16]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x88, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqd { z23.d }, p3/z, [x13, #-128]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x87, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqd { z23.d }, p3/z, [x13, #112]" + + - + input: + bytes: [ 0x00, 0x20, 0x80, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqd { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqd { z0.d }, p0/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0xff, 0x3f, 0x8f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqd { z31.d }, p7/z, [sp, #-16]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x88, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqd { z23.d }, p3/z, [x13, #-128]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x87, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqd { z23.d }, p3/z, [x13, #112]" diff --git a/tests/MC/AArch64/SVE/ld1rqh.s.yaml b/tests/MC/AArch64/SVE/ld1rqh.s.yaml new file mode 100644 index 0000000000..65a6347b26 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1rqh.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x80, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqh { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqh { z0.h }, p0/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0xff, 0x3f, 0x8f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqh { z31.h }, p7/z, [sp, #-16]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x88, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqh { z23.h }, p3/z, [x13, #-128]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x87, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqh { z23.h }, p3/z, [x13, #112]" + + - + input: + bytes: [ 0x00, 0x20, 0x80, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqh { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqh { z0.h }, p0/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0xff, 0x3f, 0x8f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqh { z31.h }, p7/z, [sp, #-16]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x88, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqh { z23.h }, p3/z, [x13, #-128]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x87, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqh { z23.h }, p3/z, [x13, #112]" diff --git a/tests/MC/AArch64/SVE/ld1rqw.s.yaml b/tests/MC/AArch64/SVE/ld1rqw.s.yaml new file mode 100644 index 0000000000..2dc1b6d0c2 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1rqw.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x00, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqw { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqw { z0.s }, p0/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0xff, 0x3f, 0x0f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqw { z31.s }, p7/z, [sp, #-16]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x08, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqw { z23.s }, p3/z, [x13, #-128]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x07, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rqw { z23.s }, p3/z, [x13, #112]" + + - + input: + bytes: [ 0x00, 0x20, 0x00, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqw { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqw { z0.s }, p0/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0xff, 0x3f, 0x0f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqw { z31.s }, p7/z, [sp, #-16]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x08, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqw { z23.s }, p3/z, [x13, #-128]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x07, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rqw { z23.s }, p3/z, [x13, #112]" diff --git a/tests/MC/AArch64/SVE/ld1rsb.s.yaml b/tests/MC/AArch64/SVE/ld1rsb.s.yaml new file mode 100644 index 0000000000..2cf649571d --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1rsb.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rsb { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rsb { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0x80, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rsb { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xdf, 0xff, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rsb { z31.h }, p7/z, [sp, #63]" + + - + input: + bytes: [ 0xff, 0xbf, 0xff, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rsb { z31.s }, p7/z, [sp, #63]" + + - + input: + bytes: [ 0xff, 0x9f, 0xff, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rsb { z31.d }, p7/z, [sp, #63]" + + - + input: + bytes: [ 0x00, 0xc0, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rsb { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rsb { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0x80, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rsb { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xdf, 0xff, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rsb { z31.h }, p7/z, [sp, #63]" + + - + input: + bytes: [ 0xff, 0xbf, 0xff, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rsb { z31.s }, p7/z, [sp, #63]" + + - + input: + bytes: [ 0xff, 0x9f, 0xff, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rsb { z31.d }, p7/z, [sp, #63]" diff --git a/tests/MC/AArch64/SVE/ld1rsh.s.yaml b/tests/MC/AArch64/SVE/ld1rsh.s.yaml new file mode 100644 index 0000000000..1c0b2a4a2a --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1rsh.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rsh { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0x80, 0x40, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rsh { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0x7f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rsh { z31.s }, p7/z, [sp, #126]" + + - + input: + bytes: [ 0xff, 0x9f, 0x7f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rsh { z31.d }, p7/z, [sp, #126]" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rsh { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0x80, 0x40, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rsh { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0x7f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rsh { z31.s }, p7/z, [sp, #126]" + + - + input: + bytes: [ 0xff, 0x9f, 0x7f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rsh { z31.d }, p7/z, [sp, #126]" diff --git a/tests/MC/AArch64/SVE/ld1rsw.s.yaml b/tests/MC/AArch64/SVE/ld1rsw.s.yaml new file mode 100644 index 0000000000..dd790bdc08 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1rsw.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0xc0, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rsw { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0x9f, 0xff, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rsw { z31.d }, p7/z, [sp, #252]" + + - + input: + bytes: [ 0x00, 0x80, 0xc0, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rsw { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0x9f, 0xff, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rsw { z31.d }, p7/z, [sp, #252]" diff --git a/tests/MC/AArch64/SVE/ld1rw.s.yaml b/tests/MC/AArch64/SVE/ld1rw.s.yaml new file mode 100644 index 0000000000..59e35f3878 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1rw.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0x40, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rw { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rw { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xdf, 0x7f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rw { z31.s }, p7/z, [sp, #252]" + + - + input: + bytes: [ 0xff, 0xff, 0x7f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1rw { z31.d }, p7/z, [sp, #252]" + + - + input: + bytes: [ 0x00, 0xc0, 0x40, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rw { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rw { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xdf, 0x7f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rw { z31.s }, p7/z, [sp, #252]" + + - + input: + bytes: [ 0xff, 0xff, 0x7f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1rw { z31.d }, p7/z, [sp, #252]" diff --git a/tests/MC/AArch64/SVE/ld1sb-sve-only.s.yaml b/tests/MC/AArch64/SVE/ld1sb-sve-only.s.yaml new file mode 100644 index 0000000000..07c65fb8d2 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1sb-sve-only.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x40, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z0.s }, p0/z, [x0, z0.s, sxtw]" + + - + input: + bytes: [ 0xff, 0x9f, 0x5f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z31.d }, p7/z, [sp, z31.d]" + + - + input: + bytes: [ 0x55, 0x15, 0x15, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z21.d }, p5/z, [x10, z21.d, uxtw]" + + - + input: + bytes: [ 0x55, 0x15, 0x55, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z21.d }, p5/z, [x10, z21.d, sxtw]" + + - + input: + bytes: [ 0xff, 0x9f, 0x3f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z31.s }, p7/z, [z31.s, #31]" + + - + input: + bytes: [ 0x00, 0x80, 0x20, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z0.s }, p0/z, [z0.s]" + + - + input: + bytes: [ 0xff, 0x9f, 0x3f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z31.d }, p7/z, [z31.d, #31]" + + - + input: + bytes: [ 0x00, 0x80, 0x20, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z0.d }, p0/z, [z0.d]" diff --git a/tests/MC/AArch64/SVE/ld1sb.s.yaml b/tests/MC/AArch64/SVE/ld1sb.s.yaml new file mode 100644 index 0000000000..daeebb6e71 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1sb.s.yaml @@ -0,0 +1,340 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0xc0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xa0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x80, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xc0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xa0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x80, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0xcf, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z31.h }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0xc5, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z21.h }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0xaf, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z31.s }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0xa5, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z21.s }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0x8f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x85, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z21.d }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xe0, 0x43, 0xc0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z0.h }, p0/z, [sp, x0]" + + - + input: + bytes: [ 0x00, 0x40, 0xc0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z0.h }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x00, 0x40, 0xc0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z0.h }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x55, 0x55, 0xb5, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z21.s }, p5/z, [x10, x21]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x88, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sb { z23.d }, p3/z, [x13, x8]" + + - + input: + bytes: [ 0x00, 0xa0, 0xc0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sb { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xa0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sb { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x80, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sb { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xc0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sb { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xa0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sb { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x80, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sb { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0xcf, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sb { z31.h }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0xc5, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sb { z21.h }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0xaf, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sb { z31.s }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0xa5, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sb { z21.s }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0x8f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sb { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x85, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sb { z21.d }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xe0, 0x43, 0xc0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sb { z0.h }, p0/z, [sp, x0]" + + - + input: + bytes: [ 0x00, 0x40, 0xc0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sb { z0.h }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x00, 0x40, 0xc0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sb { z0.h }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x55, 0x55, 0xb5, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sb { z21.s }, p5/z, [x10, x21]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x88, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sb { z23.d }, p3/z, [x13, x8]" diff --git a/tests/MC/AArch64/SVE/ld1sh-sve-only.s.yaml b/tests/MC/AArch64/SVE/ld1sh-sve-only.s.yaml new file mode 100644 index 0000000000..123b3c2147 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1sh-sve-only.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x80, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z0.s }, p0/z, [x0, z0.s, uxtw]" + + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z0.s }, p0/z, [x0, z0.s, sxtw]" + + - + input: + bytes: [ 0xff, 0x1f, 0xbf, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]" + + - + input: + bytes: [ 0xff, 0x1f, 0xff, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]" + + - + input: + bytes: [ 0xff, 0x9f, 0xdf, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z31.d }, p7/z, [sp, z31.d]" + + - + input: + bytes: [ 0xb7, 0x8d, 0xe8, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]" + + - + input: + bytes: [ 0x55, 0x15, 0x95, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z21.d }, p5/z, [x10, z21.d, uxtw]" + + - + input: + bytes: [ 0x55, 0x15, 0xd5, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z21.d }, p5/z, [x10, z21.d, sxtw]" + + - + input: + bytes: [ 0x00, 0x00, 0xa0, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]" + + - + input: + bytes: [ 0x00, 0x00, 0xe0, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]" + + - + input: + bytes: [ 0xff, 0x9f, 0xbf, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z31.s }, p7/z, [z31.s, #62]" + + - + input: + bytes: [ 0x00, 0x80, 0xa0, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z0.s }, p0/z, [z0.s]" + + - + input: + bytes: [ 0xff, 0x9f, 0xbf, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z31.d }, p7/z, [z31.d, #62]" + + - + input: + bytes: [ 0x00, 0x80, 0xa0, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z0.d }, p0/z, [z0.d]" diff --git a/tests/MC/AArch64/SVE/ld1sh.s.yaml b/tests/MC/AArch64/SVE/ld1sh.s.yaml new file mode 100644 index 0000000000..9c00f9c588 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1sh.s.yaml @@ -0,0 +1,220 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x20, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x20, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0x2f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z31.s }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x25, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z21.s }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0x0f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x05, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z21.d }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xf5, 0x57, 0x35, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z21.s }, p5/z, [sp, x21, lsl #1]" + + - + input: + bytes: [ 0x55, 0x55, 0x35, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z21.s }, p5/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x08, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sh { z23.d }, p3/z, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0x00, 0xa0, 0x20, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sh { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sh { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x20, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sh { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sh { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0x2f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sh { z31.s }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x25, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sh { z21.s }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0x0f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sh { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x05, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sh { z21.d }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xf5, 0x57, 0x35, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sh { z21.s }, p5/z, [sp, x21, lsl #1]" + + - + input: + bytes: [ 0x55, 0x55, 0x35, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sh { z21.s }, p5/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x08, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sh { z23.d }, p3/z, [x13, x8, lsl #1]" diff --git a/tests/MC/AArch64/SVE/ld1sw-sve-only.s.yaml b/tests/MC/AArch64/SVE/ld1sw-sve-only.s.yaml new file mode 100644 index 0000000000..be4491b01c --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1sw-sve-only.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x9f, 0x5f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sw { z31.d }, p7/z, [sp, z31.d]" + + - + input: + bytes: [ 0xb7, 0x8d, 0x68, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]" + + - + input: + bytes: [ 0x55, 0x15, 0x15, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sw { z21.d }, p5/z, [x10, z21.d, uxtw]" + + - + input: + bytes: [ 0x55, 0x15, 0x55, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sw { z21.d }, p5/z, [x10, z21.d, sxtw]" + + - + input: + bytes: [ 0x00, 0x00, 0x20, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]" + + - + input: + bytes: [ 0x00, 0x00, 0x60, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]" + + - + input: + bytes: [ 0xff, 0x9f, 0x3f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sw { z31.d }, p7/z, [z31.d, #124]" + + - + input: + bytes: [ 0x00, 0x80, 0x20, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sw { z0.d }, p0/z, [z0.d]" diff --git a/tests/MC/AArch64/SVE/ld1sw.s.yaml b/tests/MC/AArch64/SVE/ld1sw.s.yaml new file mode 100644 index 0000000000..eaf94cb947 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1sw.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x80, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sw { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x80, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sw { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0x8f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sw { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x85, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sw { z21.d }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xf7, 0x4f, 0x88, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sw { z23.d }, p3/z, [sp, x8, lsl #2]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x88, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1sw { z23.d }, p3/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0x00, 0xa0, 0x80, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sw { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x80, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sw { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0x8f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sw { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x85, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sw { z21.d }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xf7, 0x4f, 0x88, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sw { z23.d }, p3/z, [sp, x8, lsl #2]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x88, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1sw { z23.d }, p3/z, [x13, x8, lsl #2]" diff --git a/tests/MC/AArch64/SVE/ld1w-sve-only.s.yaml b/tests/MC/AArch64/SVE/ld1w-sve-only.s.yaml new file mode 100644 index 0000000000..4e0d521647 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1w-sve-only.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0x00, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z0.s }, p0/z, [x0, z0.s, uxtw]" + + - + input: + bytes: [ 0x00, 0x40, 0x40, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z0.s }, p0/z, [x0, z0.s, sxtw]" + + - + input: + bytes: [ 0xff, 0x5f, 0x3f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]" + + - + input: + bytes: [ 0xff, 0x5f, 0x7f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]" + + - + input: + bytes: [ 0xff, 0xdf, 0x5f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z31.d }, p7/z, [sp, z31.d]" + + - + input: + bytes: [ 0xb7, 0xcd, 0x68, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z23.d }, p3/z, [x13, z8.d, lsl #2]" + + - + input: + bytes: [ 0x55, 0x55, 0x15, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z21.d }, p5/z, [x10, z21.d, uxtw]" + + - + input: + bytes: [ 0x55, 0x55, 0x55, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z21.d }, p5/z, [x10, z21.d, sxtw]" + + - + input: + bytes: [ 0x00, 0x40, 0x20, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]" + + - + input: + bytes: [ 0x00, 0x40, 0x60, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]" + + - + input: + bytes: [ 0xff, 0xdf, 0x3f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z31.s }, p7/z, [z31.s, #124]" + + - + input: + bytes: [ 0x00, 0xc0, 0x20, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z0.s }, p0/z, [z0.s]" + + - + input: + bytes: [ 0xff, 0xdf, 0x3f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z31.d }, p7/z, [z31.d, #124]" + + - + input: + bytes: [ 0x00, 0xc0, 0x20, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z0.d }, p0/z, [z0.d]" diff --git a/tests/MC/AArch64/SVE/ld1w.s.yaml b/tests/MC/AArch64/SVE/ld1w.s.yaml new file mode 100644 index 0000000000..021edeb2fa --- /dev/null +++ b/tests/MC/AArch64/SVE/ld1w.s.yaml @@ -0,0 +1,220 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x60, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x60, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0x4f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z31.s }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x45, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z21.s }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0x6f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x65, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z21.d }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xf5, 0x57, 0x55, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z21.s }, p5/z, [sp, x21, lsl #2]" + + - + input: + bytes: [ 0x55, 0x55, 0x55, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z21.s }, p5/z, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x68, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld1w { z23.d }, p3/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x60, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x60, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0x4f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w { z31.s }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x45, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w { z21.s }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0x6f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x65, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w { z21.d }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xf5, 0x57, 0x55, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w { z21.s }, p5/z, [sp, x21, lsl #2]" + + - + input: + bytes: [ 0x55, 0x55, 0x55, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w { z21.s }, p5/z, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x68, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld1w { z23.d }, p3/z, [x13, x8, lsl #2]" diff --git a/tests/MC/AArch64/SVE/ld2b.s.yaml b/tests/MC/AArch64/SVE/ld2b.s.yaml new file mode 100644 index 0000000000..bb1533b23b --- /dev/null +++ b/tests/MC/AArch64/SVE/ld2b.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0x20, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2b { z0.b, z1.b }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x25, 0xce, 0x30, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2b { z5.b, z6.b }, p3/z, [x17, x16]" + + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2b { z0.b, z1.b }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x28, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2b { z23.b, z24.b }, p3/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x25, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x20, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2b { z0.b, z1.b }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x25, 0xce, 0x30, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2b { z5.b, z6.b }, p3/z, [x17, x16]" + + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2b { z0.b, z1.b }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x28, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2b { z23.b, z24.b }, p3/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x25, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl]" diff --git a/tests/MC/AArch64/SVE/ld2d.s.yaml b/tests/MC/AArch64/SVE/ld2d.s.yaml new file mode 100644 index 0000000000..23202c403f --- /dev/null +++ b/tests/MC/AArch64/SVE/ld2d.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0xa0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2d { z0.d, z1.d }, p0/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x25, 0xce, 0xb0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2d { z5.d, z6.d }, p3/z, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0xa0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2d { z0.d, z1.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xa8, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2d { z23.d, z24.d }, p3/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xa5, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0xa0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2d { z0.d, z1.d }, p0/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x25, 0xce, 0xb0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2d { z5.d, z6.d }, p3/z, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0xa0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2d { z0.d, z1.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xa8, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2d { z23.d, z24.d }, p3/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xa5, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl]" diff --git a/tests/MC/AArch64/SVE/ld2h.s.yaml b/tests/MC/AArch64/SVE/ld2h.s.yaml new file mode 100644 index 0000000000..8996bc2f7c --- /dev/null +++ b/tests/MC/AArch64/SVE/ld2h.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0xa0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x25, 0xce, 0xb0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2h { z5.h, z6.h }, p3/z, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x00, 0xe0, 0xa0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2h { z0.h, z1.h }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xa8, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2h { z23.h, z24.h }, p3/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xa5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0xa0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x25, 0xce, 0xb0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2h { z5.h, z6.h }, p3/z, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x00, 0xe0, 0xa0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2h { z0.h, z1.h }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xa8, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2h { z23.h, z24.h }, p3/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xa5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]" diff --git a/tests/MC/AArch64/SVE/ld2w.s.yaml b/tests/MC/AArch64/SVE/ld2w.s.yaml new file mode 100644 index 0000000000..12f41fb309 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld2w.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0x20, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2w { z0.s, z1.s }, p0/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x25, 0xce, 0x30, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2w { z5.s, z6.s }, p3/z, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2w { z0.s, z1.s }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x28, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2w { z23.s, z24.s }, p3/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x25, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x20, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2w { z0.s, z1.s }, p0/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x25, 0xce, 0x30, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2w { z5.s, z6.s }, p3/z, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2w { z0.s, z1.s }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x28, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2w { z23.s, z24.s }, p3/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x25, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl]" diff --git a/tests/MC/AArch64/SVE/ld3b.s.yaml b/tests/MC/AArch64/SVE/ld3b.s.yaml new file mode 100644 index 0000000000..52f795ed03 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld3b.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0x40, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3b { z0.b - z2.b }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x25, 0xce, 0x50, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3b { z5.b - z7.b }, p3/z, [x17, x16]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3b { z0.b - z2.b }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x48, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3b { z23.b - z25.b }, p3/z, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x45, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3b { z21.b - z23.b }, p5/z, [x10, #15, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x40, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3b { z0.b - z2.b }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x25, 0xce, 0x50, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3b { z5.b - z7.b }, p3/z, [x17, x16]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3b { z0.b - z2.b }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x48, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3b { z23.b - z25.b }, p3/z, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x45, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3b { z21.b - z23.b }, p5/z, [x10, #15, mul vl]" diff --git a/tests/MC/AArch64/SVE/ld3d.s.yaml b/tests/MC/AArch64/SVE/ld3d.s.yaml new file mode 100644 index 0000000000..829865772f --- /dev/null +++ b/tests/MC/AArch64/SVE/ld3d.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0xc0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3d { z0.d - z2.d }, p0/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x25, 0xce, 0xd0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3d { z5.d - z7.d }, p3/z, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0xc0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3d { z0.d - z2.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xc8, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3d { z23.d - z25.d }, p3/z, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xc5, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3d { z21.d - z23.d }, p5/z, [x10, #15, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0xc0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3d { z0.d - z2.d }, p0/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x25, 0xce, 0xd0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3d { z5.d - z7.d }, p3/z, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0xc0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3d { z0.d - z2.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xc8, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3d { z23.d - z25.d }, p3/z, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xc5, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3d { z21.d - z23.d }, p5/z, [x10, #15, mul vl]" diff --git a/tests/MC/AArch64/SVE/ld3h.s.yaml b/tests/MC/AArch64/SVE/ld3h.s.yaml new file mode 100644 index 0000000000..2f44bcb3d5 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld3h.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0xc0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3h { z0.h - z2.h }, p0/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x25, 0xce, 0xd0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3h { z5.h - z7.h }, p3/z, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x00, 0xe0, 0xc0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3h { z0.h - z2.h }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xc8, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3h { z23.h - z25.h }, p3/z, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xc5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3h { z21.h - z23.h }, p5/z, [x10, #15, mul vl]" + + - + input: + bytes: [ 0x5e, 0xf5, 0xc5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3h { z30.h, z31.h, z0.h }, p5/z, [x10, #15, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0xc0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3h { z0.h - z2.h }, p0/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x25, 0xce, 0xd0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3h { z5.h - z7.h }, p3/z, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x00, 0xe0, 0xc0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3h { z0.h - z2.h }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xc8, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3h { z23.h - z25.h }, p3/z, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xc5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3h { z21.h - z23.h }, p5/z, [x10, #15, mul vl]" + + - + input: + bytes: [ 0x5e, 0xf5, 0xc5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3h { z30.h, z31.h, z0.h }, p5/z, [x10, #15, mul vl]" diff --git a/tests/MC/AArch64/SVE/ld3w.s.yaml b/tests/MC/AArch64/SVE/ld3w.s.yaml new file mode 100644 index 0000000000..eb7d1b3549 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld3w.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0x40, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3w { z0.s - z2.s }, p0/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x25, 0xce, 0x50, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3w { z5.s - z7.s }, p3/z, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3w { z0.s - z2.s }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x48, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3w { z23.s - z25.s }, p3/z, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x45, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld3w { z21.s - z23.s }, p5/z, [x10, #15, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x40, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3w { z0.s - z2.s }, p0/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x25, 0xce, 0x50, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3w { z5.s - z7.s }, p3/z, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3w { z0.s - z2.s }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x48, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3w { z23.s - z25.s }, p3/z, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x45, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld3w { z21.s - z23.s }, p5/z, [x10, #15, mul vl]" diff --git a/tests/MC/AArch64/SVE/ld4b.s.yaml b/tests/MC/AArch64/SVE/ld4b.s.yaml new file mode 100644 index 0000000000..e5539b67a3 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld4b.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0x60, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4b { z0.b - z3.b }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x25, 0xce, 0x70, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4b { z5.b - z8.b }, p3/z, [x17, x16]" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4b { z0.b - z3.b }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x68, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4b { z23.b - z26.b }, p3/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x65, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4b { z21.b - z24.b }, p5/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x60, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4b { z0.b - z3.b }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x25, 0xce, 0x70, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4b { z5.b - z8.b }, p3/z, [x17, x16]" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4b { z0.b - z3.b }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x68, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4b { z23.b - z26.b }, p3/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x65, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4b { z21.b - z24.b }, p5/z, [x10, #20, mul vl]" diff --git a/tests/MC/AArch64/SVE/ld4d.s.yaml b/tests/MC/AArch64/SVE/ld4d.s.yaml new file mode 100644 index 0000000000..83a8f76357 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld4d.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0xe0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4d { z0.d - z3.d }, p0/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x25, 0xce, 0xf0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4d { z5.d - z8.d }, p3/z, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0xe0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4d { z0.d - z3.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xe8, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4d { z23.d - z26.d }, p3/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xe5, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4d { z21.d - z24.d }, p5/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0xe0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4d { z0.d - z3.d }, p0/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x25, 0xce, 0xf0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4d { z5.d - z8.d }, p3/z, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0xe0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4d { z0.d - z3.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xe8, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4d { z23.d - z26.d }, p3/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xe5, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4d { z21.d - z24.d }, p5/z, [x10, #20, mul vl]" diff --git a/tests/MC/AArch64/SVE/ld4h.s.yaml b/tests/MC/AArch64/SVE/ld4h.s.yaml new file mode 100644 index 0000000000..3a9012bd87 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld4h.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0xe0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4h { z0.h - z3.h }, p0/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x25, 0xce, 0xf0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4h { z5.h - z8.h }, p3/z, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x00, 0xe0, 0xe0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4h { z0.h - z3.h }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xe8, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4h { z23.h - z26.h }, p3/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xe5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4h { z21.h - z24.h }, p5/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0x5f, 0xf5, 0xe5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4h { z31.h, z0.h, z1.h, z2.h }, p5/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0xe0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4h { z0.h - z3.h }, p0/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x25, 0xce, 0xf0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4h { z5.h - z8.h }, p3/z, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x00, 0xe0, 0xe0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4h { z0.h - z3.h }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xe8, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4h { z23.h - z26.h }, p3/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xe5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4h { z21.h - z24.h }, p5/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0x5f, 0xf5, 0xe5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4h { z31.h, z0.h, z1.h, z2.h }, p5/z, [x10, #20, mul vl]" diff --git a/tests/MC/AArch64/SVE/ld4w.s.yaml b/tests/MC/AArch64/SVE/ld4w.s.yaml new file mode 100644 index 0000000000..dea69b87f1 --- /dev/null +++ b/tests/MC/AArch64/SVE/ld4w.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0x60, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4w { z0.s - z3.s }, p0/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x25, 0xce, 0x70, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4w { z5.s - z8.s }, p3/z, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4w { z0.s - z3.s }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x68, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4w { z23.s - z26.s }, p3/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x65, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ld4w { z21.s - z24.s }, p5/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x60, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4w { z0.s - z3.s }, p0/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x25, 0xce, 0x70, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4w { z5.s - z8.s }, p3/z, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4w { z0.s - z3.s }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x68, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4w { z23.s - z26.s }, p3/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x65, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ld4w { z21.s - z24.s }, p5/z, [x10, #20, mul vl]" diff --git a/tests/MC/AArch64/SVE/ldff1b.s.yaml b/tests/MC/AArch64/SVE/ldff1b.s.yaml new file mode 100644 index 0000000000..41648e0bcc --- /dev/null +++ b/tests/MC/AArch64/SVE/ldff1b.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x7f, 0x1f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z31.b }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0x3f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z31.h }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0x5f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z31.s }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0x7f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z31.d }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0x1f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z31.b }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0x3f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z31.h }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0x5f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z31.s }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0x7f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z31.d }, p7/z, [sp]" + + - + input: + bytes: [ 0x00, 0x60, 0x20, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z0.h }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x00, 0x60, 0x40, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z0.s }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z0.d }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x00, 0x60, 0x00, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z0.s }, p0/z, [x0, z0.s, uxtw]" + + - + input: + bytes: [ 0x00, 0x60, 0x40, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z0.s }, p0/z, [x0, z0.s, sxtw]" + + - + input: + bytes: [ 0xff, 0xff, 0x5f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z31.d }, p7/z, [sp, z31.d]" + + - + input: + bytes: [ 0x55, 0x75, 0x15, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z21.d }, p5/z, [x10, z21.d, uxtw]" + + - + input: + bytes: [ 0x55, 0x75, 0x55, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z21.d }, p5/z, [x10, z21.d, sxtw]" + + - + input: + bytes: [ 0xff, 0xff, 0x3f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z31.s }, p7/z, [z31.s, #31]" + + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z0.s }, p0/z, [z0.s]" + + - + input: + bytes: [ 0xff, 0xff, 0x3f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z31.d }, p7/z, [z31.d, #31]" + + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1b { z0.d }, p0/z, [z0.d]" diff --git a/tests/MC/AArch64/SVE/ldff1d.s.yaml b/tests/MC/AArch64/SVE/ldff1d.s.yaml new file mode 100644 index 0000000000..64ea21371a --- /dev/null +++ b/tests/MC/AArch64/SVE/ldff1d.s.yaml @@ -0,0 +1,110 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x7f, 0xff, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1d { z31.d }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0xff, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1d { z31.d }, p7/z, [sp]" + + - + input: + bytes: [ 0x00, 0x60, 0xe0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1d { z0.d }, p0/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0xff, 0xff, 0xdf, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1d { z31.d }, p7/z, [sp, z31.d]" + + - + input: + bytes: [ 0xb7, 0xed, 0xe8, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1d { z23.d }, p3/z, [x13, z8.d, lsl #3]" + + - + input: + bytes: [ 0x55, 0x75, 0x95, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1d { z21.d }, p5/z, [x10, z21.d, uxtw]" + + - + input: + bytes: [ 0x55, 0x75, 0xd5, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1d { z21.d }, p5/z, [x10, z21.d, sxtw]" + + - + input: + bytes: [ 0x00, 0x60, 0xa0, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]" + + - + input: + bytes: [ 0x00, 0x60, 0xe0, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]" + + - + input: + bytes: [ 0xff, 0xff, 0xbf, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1d { z31.d }, p7/z, [z31.d, #248]" + + - + input: + bytes: [ 0x00, 0xe0, 0xa0, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1d { z0.d }, p0/z, [z0.d]" diff --git a/tests/MC/AArch64/SVE/ldff1h.s.yaml b/tests/MC/AArch64/SVE/ldff1h.s.yaml new file mode 100644 index 0000000000..378caa3fea --- /dev/null +++ b/tests/MC/AArch64/SVE/ldff1h.s.yaml @@ -0,0 +1,230 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x7f, 0xbf, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z31.h }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0xdf, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z31.s }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0xff, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z31.d }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0xbf, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z31.h }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0xdf, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z31.s }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0xff, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z31.d }, p7/z, [sp]" + + - + input: + bytes: [ 0x00, 0x60, 0xa0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z0.h }, p0/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x00, 0x60, 0xc0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z0.s }, p0/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x00, 0x60, 0xe0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z0.d }, p0/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x00, 0x60, 0x80, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z0.s }, p0/z, [x0, z0.s, uxtw]" + + - + input: + bytes: [ 0x00, 0x60, 0xc0, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z0.s }, p0/z, [x0, z0.s, sxtw]" + + - + input: + bytes: [ 0xff, 0x7f, 0xbf, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]" + + - + input: + bytes: [ 0xff, 0x7f, 0xff, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]" + + - + input: + bytes: [ 0xff, 0xff, 0xdf, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z31.d }, p7/z, [sp, z31.d]" + + - + input: + bytes: [ 0xb7, 0xed, 0xe8, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z23.d }, p3/z, [x13, z8.d, lsl #1]" + + - + input: + bytes: [ 0x55, 0x75, 0x95, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z21.d }, p5/z, [x10, z21.d, uxtw]" + + - + input: + bytes: [ 0x55, 0x75, 0xd5, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z21.d }, p5/z, [x10, z21.d, sxtw]" + + - + input: + bytes: [ 0x00, 0x60, 0xa0, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]" + + - + input: + bytes: [ 0x00, 0x60, 0xe0, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]" + + - + input: + bytes: [ 0xff, 0xff, 0xbf, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z31.s }, p7/z, [z31.s, #62]" + + - + input: + bytes: [ 0x00, 0xe0, 0xa0, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z0.s }, p0/z, [z0.s]" + + - + input: + bytes: [ 0xff, 0xff, 0xbf, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z31.d }, p7/z, [z31.d, #62]" + + - + input: + bytes: [ 0x00, 0xe0, 0xa0, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1h { z0.d }, p0/z, [z0.d]" diff --git a/tests/MC/AArch64/SVE/ldff1sb.s.yaml b/tests/MC/AArch64/SVE/ldff1sb.s.yaml new file mode 100644 index 0000000000..031e71d8e3 --- /dev/null +++ b/tests/MC/AArch64/SVE/ldff1sb.s.yaml @@ -0,0 +1,180 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x7f, 0xdf, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sb { z31.h }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0xbf, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sb { z31.s }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0x9f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sb { z31.d }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0xdf, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sb { z31.h }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0xbf, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sb { z31.s }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0x9f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sb { z31.d }, p7/z, [sp]" + + - + input: + bytes: [ 0x00, 0x60, 0xc0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sb { z0.h }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x00, 0x60, 0xa0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sb { z0.s }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x00, 0x60, 0x80, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sb { z0.d }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x00, 0x20, 0x00, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sb { z0.s }, p0/z, [x0, z0.s, uxtw]" + + - + input: + bytes: [ 0x00, 0x20, 0x40, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sb { z0.s }, p0/z, [x0, z0.s, sxtw]" + + - + input: + bytes: [ 0xff, 0xbf, 0x5f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sb { z31.d }, p7/z, [sp, z31.d]" + + - + input: + bytes: [ 0x55, 0x35, 0x15, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sb { z21.d }, p5/z, [x10, z21.d, uxtw]" + + - + input: + bytes: [ 0x55, 0x35, 0x55, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sb { z21.d }, p5/z, [x10, z21.d, sxtw]" + + - + input: + bytes: [ 0xff, 0xbf, 0x3f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sb { z31.s }, p7/z, [z31.s, #31]" + + - + input: + bytes: [ 0x00, 0xa0, 0x20, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sb { z0.s }, p0/z, [z0.s]" + + - + input: + bytes: [ 0xff, 0xbf, 0x3f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sb { z31.d }, p7/z, [z31.d, #31]" + + - + input: + bytes: [ 0x00, 0xa0, 0x20, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sb { z0.d }, p0/z, [z0.d]" diff --git a/tests/MC/AArch64/SVE/ldff1sh.s.yaml b/tests/MC/AArch64/SVE/ldff1sh.s.yaml new file mode 100644 index 0000000000..88336fd351 --- /dev/null +++ b/tests/MC/AArch64/SVE/ldff1sh.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x7f, 0x3f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z31.s }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0x1f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z31.d }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0x3f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z31.s }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0x1f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z31.d }, p7/z, [sp]" + + - + input: + bytes: [ 0x00, 0x60, 0x20, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z0.s }, p0/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x00, 0x60, 0x00, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z0.d }, p0/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x00, 0x20, 0x80, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z0.s }, p0/z, [x0, z0.s, uxtw]" + + - + input: + bytes: [ 0x00, 0x20, 0xc0, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z0.s }, p0/z, [x0, z0.s, sxtw]" + + - + input: + bytes: [ 0xff, 0x3f, 0xbf, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]" + + - + input: + bytes: [ 0xff, 0x3f, 0xff, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]" + + - + input: + bytes: [ 0xff, 0xbf, 0xdf, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z31.d }, p7/z, [sp, z31.d]" + + - + input: + bytes: [ 0xb7, 0xad, 0xe8, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]" + + - + input: + bytes: [ 0x55, 0x35, 0x95, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z21.d }, p5/z, [x10, z21.d, uxtw]" + + - + input: + bytes: [ 0x55, 0x35, 0xd5, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z21.d }, p5/z, [x10, z21.d, sxtw]" + + - + input: + bytes: [ 0x00, 0x20, 0xa0, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]" + + - + input: + bytes: [ 0x00, 0x20, 0xe0, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]" + + - + input: + bytes: [ 0xff, 0xbf, 0xbf, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z31.s }, p7/z, [z31.s, #62]" + + - + input: + bytes: [ 0x00, 0xa0, 0xa0, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z0.s }, p0/z, [z0.s]" + + - + input: + bytes: [ 0xff, 0xbf, 0xbf, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z31.d }, p7/z, [z31.d, #62]" + + - + input: + bytes: [ 0x00, 0xa0, 0xa0, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sh { z0.d }, p0/z, [z0.d]" diff --git a/tests/MC/AArch64/SVE/ldff1sw.s.yaml b/tests/MC/AArch64/SVE/ldff1sw.s.yaml new file mode 100644 index 0000000000..0fff6a5fbb --- /dev/null +++ b/tests/MC/AArch64/SVE/ldff1sw.s.yaml @@ -0,0 +1,110 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x7f, 0x9f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sw { z31.d }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0x9f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sw { z31.d }, p7/z, [sp]" + + - + input: + bytes: [ 0x00, 0x60, 0x80, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sw { z0.d }, p0/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0xff, 0xbf, 0x5f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sw { z31.d }, p7/z, [sp, z31.d]" + + - + input: + bytes: [ 0xb7, 0xad, 0x68, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]" + + - + input: + bytes: [ 0x55, 0x35, 0x15, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sw { z21.d }, p5/z, [x10, z21.d, uxtw]" + + - + input: + bytes: [ 0x55, 0x35, 0x55, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sw { z21.d }, p5/z, [x10, z21.d, sxtw]" + + - + input: + bytes: [ 0x00, 0x20, 0x20, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]" + + - + input: + bytes: [ 0x00, 0x20, 0x60, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]" + + - + input: + bytes: [ 0xff, 0xbf, 0x3f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sw { z31.d }, p7/z, [z31.d, #124]" + + - + input: + bytes: [ 0x00, 0xa0, 0x20, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1sw { z0.d }, p0/z, [z0.d]" diff --git a/tests/MC/AArch64/SVE/ldff1w.s.yaml b/tests/MC/AArch64/SVE/ldff1w.s.yaml new file mode 100644 index 0000000000..90dc3cb370 --- /dev/null +++ b/tests/MC/AArch64/SVE/ldff1w.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x7f, 0x7f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z31.d }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0x5f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z31.s }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0x7f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z31.d }, p7/z, [sp]" + + - + input: + bytes: [ 0xff, 0x7f, 0x5f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z31.s }, p7/z, [sp]" + + - + input: + bytes: [ 0x00, 0x60, 0x40, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z0.s }, p0/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z0.d }, p0/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x00, 0x60, 0x00, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw]" + + - + input: + bytes: [ 0x00, 0x60, 0x40, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw]" + + - + input: + bytes: [ 0xff, 0x7f, 0x3f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]" + + - + input: + bytes: [ 0xff, 0x7f, 0x7f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]" + + - + input: + bytes: [ 0xff, 0xff, 0x5f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z31.d }, p7/z, [sp, z31.d]" + + - + input: + bytes: [ 0xb7, 0xed, 0x68, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z23.d }, p3/z, [x13, z8.d, lsl #2]" + + - + input: + bytes: [ 0x55, 0x75, 0x15, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z21.d }, p5/z, [x10, z21.d, uxtw]" + + - + input: + bytes: [ 0x55, 0x75, 0x55, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z21.d }, p5/z, [x10, z21.d, sxtw]" + + - + input: + bytes: [ 0x00, 0x60, 0x20, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]" + + - + input: + bytes: [ 0xff, 0xff, 0x3f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z31.s }, p7/z, [z31.s, #124]" + + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z0.s }, p0/z, [z0.s]" + + - + input: + bytes: [ 0xff, 0xff, 0x3f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z31.d }, p7/z, [z31.d, #124]" + + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldff1w { z0.d }, p0/z, [z0.d]" diff --git a/tests/MC/AArch64/SVE/ldnf1b.s.yaml b/tests/MC/AArch64/SVE/ldnf1b.s.yaml new file mode 100644 index 0000000000..816545dfca --- /dev/null +++ b/tests/MC/AArch64/SVE/ldnf1b.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x10, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1b { z0.b }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x30, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1b { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x50, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1b { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x70, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1b { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x10, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1b { z0.b }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x30, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1b { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x50, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1b { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x70, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1b { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0x1f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1b { z31.b }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x15, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1b { z21.b }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0x3f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1b { z31.h }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x35, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1b { z21.h }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0x5f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1b { z31.s }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x55, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1b { z21.s }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0x7f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1b { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x75, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1b { z21.d }, p5/z, [x10, #5, mul vl]" diff --git a/tests/MC/AArch64/SVE/ldnf1d.s.yaml b/tests/MC/AArch64/SVE/ldnf1d.s.yaml new file mode 100644 index 0000000000..2673103581 --- /dev/null +++ b/tests/MC/AArch64/SVE/ldnf1d.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0xf0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1d { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xf0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1d { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0xff, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1d { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0xf5, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1d { z21.d }, p5/z, [x10, #5, mul vl]" diff --git a/tests/MC/AArch64/SVE/ldnf1h.s.yaml b/tests/MC/AArch64/SVE/ldnf1h.s.yaml new file mode 100644 index 0000000000..90e241c168 --- /dev/null +++ b/tests/MC/AArch64/SVE/ldnf1h.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0xb0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1h { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xd0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1h { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xf0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1h { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xb0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1h { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xd0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1h { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xf0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1h { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0xbf, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1h { z31.h }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0xb5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1h { z21.h }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0xdf, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1h { z31.s }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0xd5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1h { z21.s }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0xff, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1h { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0xf5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1h { z21.d }, p5/z, [x10, #5, mul vl]" diff --git a/tests/MC/AArch64/SVE/ldnf1sb.s.yaml b/tests/MC/AArch64/SVE/ldnf1sb.s.yaml new file mode 100644 index 0000000000..b17778a73e --- /dev/null +++ b/tests/MC/AArch64/SVE/ldnf1sb.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0xd0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sb { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xb0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sb { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x90, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sb { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xd0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sb { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0xb0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sb { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x90, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sb { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0xdf, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sb { z31.h }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0xd5, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sb { z21.h }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0xbf, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sb { z31.s }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0xb5, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sb { z21.s }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0x9f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sb { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x95, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl]" diff --git a/tests/MC/AArch64/SVE/ldnf1sh.s.yaml b/tests/MC/AArch64/SVE/ldnf1sh.s.yaml new file mode 100644 index 0000000000..2e89aac243 --- /dev/null +++ b/tests/MC/AArch64/SVE/ldnf1sh.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x30, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sh { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x10, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sh { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x30, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sh { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x10, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sh { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0x3f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sh { z31.s }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x35, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sh { z21.s }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0x1f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sh { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x15, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl]" diff --git a/tests/MC/AArch64/SVE/ldnf1sw.s.yaml b/tests/MC/AArch64/SVE/ldnf1sw.s.yaml new file mode 100644 index 0000000000..c1ea10dd9c --- /dev/null +++ b/tests/MC/AArch64/SVE/ldnf1sw.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x90, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sw { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x90, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sw { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0x9f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sw { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x95, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl]" diff --git a/tests/MC/AArch64/SVE/ldnf1w.s.yaml b/tests/MC/AArch64/SVE/ldnf1w.s.yaml new file mode 100644 index 0000000000..8d2c3567af --- /dev/null +++ b/tests/MC/AArch64/SVE/ldnf1w.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x50, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1w { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x70, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1w { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x50, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1w { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x70, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1w { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xff, 0xbf, 0x5f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1w { z31.s }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x55, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1w { z21.s }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xbf, 0x7f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1w { z31.d }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xb5, 0x75, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnf1w { z21.d }, p5/z, [x10, #5, mul vl]" diff --git a/tests/MC/AArch64/SVE/ldnt1b.s.yaml b/tests/MC/AArch64/SVE/ldnt1b.s.yaml new file mode 100644 index 0000000000..61d5354e3e --- /dev/null +++ b/tests/MC/AArch64/SVE/ldnt1b.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.b }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.b }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x08, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1b { z23.b }, p3/z, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x07, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1b { z21.b }, p5/z, [x10, #7, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.b }, p0/z, [x0, x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.b }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.b }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x08, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1b { z23.b }, p3/z, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x07, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1b { z21.b }, p5/z, [x10, #7, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x00, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.b }, p0/z, [x0, x0]" diff --git a/tests/MC/AArch64/SVE/ldnt1d.s.yaml b/tests/MC/AArch64/SVE/ldnt1d.s.yaml new file mode 100644 index 0000000000..4902dedfc4 --- /dev/null +++ b/tests/MC/AArch64/SVE/ldnt1d.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x80, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x80, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x88, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1d { z23.d }, p3/z, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x87, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1d { z21.d }, p5/z, [x10, #7, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x80, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0x80, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x80, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x88, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1d { z23.d }, p3/z, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x87, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1d { z21.d }, p5/z, [x10, #7, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x80, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3]" diff --git a/tests/MC/AArch64/SVE/ldnt1h.s.yaml b/tests/MC/AArch64/SVE/ldnt1h.s.yaml new file mode 100644 index 0000000000..98630dc2d8 --- /dev/null +++ b/tests/MC/AArch64/SVE/ldnt1h.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x80, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x80, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x88, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1h { z23.h }, p3/z, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x87, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1h { z21.h }, p5/z, [x10, #7, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x80, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x00, 0xe0, 0x80, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x80, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.h }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x88, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1h { z23.h }, p3/z, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x87, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1h { z21.h }, p5/z, [x10, #7, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x80, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1]" diff --git a/tests/MC/AArch64/SVE/ldnt1w.s.yaml b/tests/MC/AArch64/SVE/ldnt1w.s.yaml new file mode 100644 index 0000000000..2d8bfa11d9 --- /dev/null +++ b/tests/MC/AArch64/SVE/ldnt1w.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x08, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1w { z23.s }, p3/z, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x07, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1w { z21.s }, p5/z, [x10, #7, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x00, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s }, p0/z, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x08, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1w { z23.s }, p3/z, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x07, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1w { z21.s }, p5/z, [x10, #7, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x00, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2]" diff --git a/tests/MC/AArch64/SVE/ldr.s.yaml b/tests/MC/AArch64/SVE/ldr.s.yaml new file mode 100644 index 0000000000..357cf708ed --- /dev/null +++ b/tests/MC/AArch64/SVE/ldr.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0x80, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldr z0, [x0]" + + - + input: + bytes: [ 0xff, 0x43, 0xa0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldr z31, [sp, #-256, mul vl]" + + - + input: + bytes: [ 0xb7, 0x5d, 0x9f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldr z23, [x13, #255, mul vl]" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldr p0, [x0]" + + - + input: + bytes: [ 0xa7, 0x01, 0xa0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldr p7, [x13, #-256, mul vl]" + + - + input: + bytes: [ 0x45, 0x1d, 0x9f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldr p5, [x10, #255, mul vl]" + + - + input: + bytes: [ 0x00, 0x40, 0x80, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr z0, [x0]" + + - + input: + bytes: [ 0xff, 0x43, 0xa0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr z31, [sp, #-256, mul vl]" + + - + input: + bytes: [ 0xb7, 0x5d, 0x9f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr z23, [x13, #255, mul vl]" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr p0, [x0]" + + - + input: + bytes: [ 0xa7, 0x01, 0xa0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr p7, [x13, #-256, mul vl]" + + - + input: + bytes: [ 0x45, 0x1d, 0x9f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr p5, [x10, #255, mul vl]" diff --git a/tests/MC/AArch64/SVE/lsl.s.yaml b/tests/MC/AArch64/SVE/lsl.s.yaml new file mode 100644 index 0000000000..162f2c6e35 --- /dev/null +++ b/tests/MC/AArch64/SVE/lsl.s.yaml @@ -0,0 +1,680 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x9c, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0x9f, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z31.b, z31.b, #7" + + - + input: + bytes: [ 0x00, 0x9c, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.h, z0.h, #0" + + - + input: + bytes: [ 0xff, 0x9f, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z31.h, z31.h, #15" + + - + input: + bytes: [ 0x00, 0x9c, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.s, z0.s, #0" + + - + input: + bytes: [ 0xff, 0x9f, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z31.s, z31.s, #31" + + - + input: + bytes: [ 0x00, 0x9c, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.d, z0.d, #0" + + - + input: + bytes: [ 0xff, 0x9f, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z31.d, z31.d, #63" + + - + input: + bytes: [ 0x00, 0x81, 0x03, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.b, p0/m, z0.b, #0" + + - + input: + bytes: [ 0xff, 0x81, 0x03, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z31.b, p0/m, z31.b, #7" + + - + input: + bytes: [ 0x00, 0x82, 0x03, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.h, p0/m, z0.h, #0" + + - + input: + bytes: [ 0xff, 0x83, 0x03, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z31.h, p0/m, z31.h, #15" + + - + input: + bytes: [ 0x00, 0x80, 0x43, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.s, p0/m, z0.s, #0" + + - + input: + bytes: [ 0xff, 0x83, 0x43, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z31.s, p0/m, z31.s, #31" + + - + input: + bytes: [ 0x00, 0x80, 0x83, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.d, p0/m, z0.d, #0" + + - + input: + bytes: [ 0xff, 0x83, 0xc3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0x00, 0x80, 0x13, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.b, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x80, 0x53, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x93, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.s, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xd3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.d, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0x20, 0x80, 0x1b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.b, p0/m, z0.b, z1.d" + + - + input: + bytes: [ 0x20, 0x80, 0x5b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.h, p0/m, z0.h, z1.d" + + - + input: + bytes: [ 0x20, 0x80, 0x9b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.s, p0/m, z0.s, z1.d" + + - + input: + bytes: [ 0x20, 0x8c, 0x22, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.b, z1.b, z2.d" + + - + input: + bytes: [ 0x20, 0x8c, 0x62, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.h, z1.h, z2.d" + + - + input: + bytes: [ 0x20, 0x8c, 0xa2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.s, z1.s, z2.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xff, 0x83, 0xc3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0x83, 0xc3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0xe0, 0x20, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.s, p0/z, z7.s" + + - + input: + bytes: [ 0x20, 0x80, 0x9b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.s, p0/m, z0.s, z1.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x80, 0x9b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsl z0.s, p0/m, z0.s, z1.d" + + - + input: + bytes: [ 0x00, 0x9c, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0x9f, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z31.b, z31.b, #7" + + - + input: + bytes: [ 0x00, 0x9c, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.h, z0.h, #0" + + - + input: + bytes: [ 0xff, 0x9f, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z31.h, z31.h, #15" + + - + input: + bytes: [ 0x00, 0x9c, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.s, z0.s, #0" + + - + input: + bytes: [ 0xff, 0x9f, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z31.s, z31.s, #31" + + - + input: + bytes: [ 0x00, 0x9c, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.d, z0.d, #0" + + - + input: + bytes: [ 0xff, 0x9f, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z31.d, z31.d, #63" + + - + input: + bytes: [ 0x00, 0x81, 0x03, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.b, p0/m, z0.b, #0" + + - + input: + bytes: [ 0xff, 0x81, 0x03, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z31.b, p0/m, z31.b, #7" + + - + input: + bytes: [ 0x00, 0x82, 0x03, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.h, p0/m, z0.h, #0" + + - + input: + bytes: [ 0xff, 0x83, 0x03, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z31.h, p0/m, z31.h, #15" + + - + input: + bytes: [ 0x00, 0x80, 0x43, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.s, p0/m, z0.s, #0" + + - + input: + bytes: [ 0xff, 0x83, 0x43, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z31.s, p0/m, z31.s, #31" + + - + input: + bytes: [ 0x00, 0x80, 0x83, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.d, p0/m, z0.d, #0" + + - + input: + bytes: [ 0xff, 0x83, 0xc3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0x00, 0x80, 0x13, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.b, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x80, 0x53, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x93, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.s, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xd3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.d, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0x20, 0x80, 0x1b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.b, p0/m, z0.b, z1.d" + + - + input: + bytes: [ 0x20, 0x80, 0x5b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.h, p0/m, z0.h, z1.d" + + - + input: + bytes: [ 0x20, 0x80, 0x9b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.s, p0/m, z0.s, z1.d" + + - + input: + bytes: [ 0x20, 0x8c, 0x22, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.b, z1.b, z2.d" + + - + input: + bytes: [ 0x20, 0x8c, 0x62, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.h, z1.h, z2.d" + + - + input: + bytes: [ 0x20, 0x8c, 0xa2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.s, z1.s, z2.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xff, 0x83, 0xc3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0x83, 0xc3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0xe0, 0x20, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.s, p0/z, z7.s" + + - + input: + bytes: [ 0x20, 0x80, 0x9b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.s, p0/m, z0.s, z1.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x80, 0x9b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsl z0.s, p0/m, z0.s, z1.d" diff --git a/tests/MC/AArch64/SVE/lslr.s.yaml b/tests/MC/AArch64/SVE/lslr.s.yaml new file mode 100644 index 0000000000..535d904927 --- /dev/null +++ b/tests/MC/AArch64/SVE/lslr.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x17, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lslr z0.b, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x80, 0x57, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lslr z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x97, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lslr z0.s, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lslr z0.d, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0x80, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lslr z5.d, p0/m, z5.d, z0.d" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0x80, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lslr z5.d, p0/m, z5.d, z0.d" + + - + input: + bytes: [ 0x00, 0x80, 0x17, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lslr z0.b, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x80, 0x57, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lslr z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x97, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lslr z0.s, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lslr z0.d, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0x80, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lslr z5.d, p0/m, z5.d, z0.d" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0x80, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lslr z5.d, p0/m, z5.d, z0.d" diff --git a/tests/MC/AArch64/SVE/lsr.s.yaml b/tests/MC/AArch64/SVE/lsr.s.yaml new file mode 100644 index 0000000000..a24fe6bb08 --- /dev/null +++ b/tests/MC/AArch64/SVE/lsr.s.yaml @@ -0,0 +1,680 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x94, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.b, z0.b, #1" + + - + input: + bytes: [ 0xff, 0x97, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z31.b, z31.b, #8" + + - + input: + bytes: [ 0x00, 0x94, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.h, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x97, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z31.h, z31.h, #16" + + - + input: + bytes: [ 0x00, 0x94, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.s, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x97, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z31.s, z31.s, #32" + + - + input: + bytes: [ 0x00, 0x94, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.d, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x97, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z31.d, z31.d, #64" + + - + input: + bytes: [ 0xe0, 0x81, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.b, p0/m, z0.b, #1" + + - + input: + bytes: [ 0x1f, 0x81, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z31.b, p0/m, z31.b, #8" + + - + input: + bytes: [ 0xe0, 0x83, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.h, p0/m, z0.h, #1" + + - + input: + bytes: [ 0x1f, 0x82, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z31.h, p0/m, z31.h, #16" + + - + input: + bytes: [ 0xe0, 0x83, 0x41, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.s, p0/m, z0.s, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x41, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z31.s, p0/m, z31.s, #32" + + - + input: + bytes: [ 0xe0, 0x83, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.d, p0/m, z0.d, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0x00, 0x80, 0x11, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.b, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x80, 0x51, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x91, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.s, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xd1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.d, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0x20, 0x80, 0x19, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.b, p0/m, z0.b, z1.d" + + - + input: + bytes: [ 0x20, 0x80, 0x59, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.h, p0/m, z0.h, z1.d" + + - + input: + bytes: [ 0x20, 0x80, 0x99, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.s, p0/m, z0.s, z1.d" + + - + input: + bytes: [ 0x20, 0x84, 0x22, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.b, z1.b, z2.d" + + - + input: + bytes: [ 0x20, 0x84, 0x62, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.h, z1.h, z2.d" + + - + input: + bytes: [ 0x20, 0x84, 0xa2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.s, z1.s, z2.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0x1f, 0x80, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x1f, 0x80, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xe0, 0x20, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.s, p0/z, z7.s" + + - + input: + bytes: [ 0x20, 0x80, 0x99, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.s, p0/m, z0.s, z1.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x80, 0x99, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsr z0.s, p0/m, z0.s, z1.d" + + - + input: + bytes: [ 0x00, 0x94, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.b, z0.b, #1" + + - + input: + bytes: [ 0xff, 0x97, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z31.b, z31.b, #8" + + - + input: + bytes: [ 0x00, 0x94, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.h, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x97, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z31.h, z31.h, #16" + + - + input: + bytes: [ 0x00, 0x94, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.s, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x97, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z31.s, z31.s, #32" + + - + input: + bytes: [ 0x00, 0x94, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.d, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x97, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z31.d, z31.d, #64" + + - + input: + bytes: [ 0xe0, 0x81, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.b, p0/m, z0.b, #1" + + - + input: + bytes: [ 0x1f, 0x81, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z31.b, p0/m, z31.b, #8" + + - + input: + bytes: [ 0xe0, 0x83, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.h, p0/m, z0.h, #1" + + - + input: + bytes: [ 0x1f, 0x82, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z31.h, p0/m, z31.h, #16" + + - + input: + bytes: [ 0xe0, 0x83, 0x41, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.s, p0/m, z0.s, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x41, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z31.s, p0/m, z31.s, #32" + + - + input: + bytes: [ 0xe0, 0x83, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.d, p0/m, z0.d, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0x00, 0x80, 0x11, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.b, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x80, 0x51, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x91, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.s, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xd1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.d, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0x20, 0x80, 0x19, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.b, p0/m, z0.b, z1.d" + + - + input: + bytes: [ 0x20, 0x80, 0x59, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.h, p0/m, z0.h, z1.d" + + - + input: + bytes: [ 0x20, 0x80, 0x99, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.s, p0/m, z0.s, z1.d" + + - + input: + bytes: [ 0x20, 0x84, 0x22, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.b, z1.b, z2.d" + + - + input: + bytes: [ 0x20, 0x84, 0x62, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.h, z1.h, z2.d" + + - + input: + bytes: [ 0x20, 0x84, 0xa2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.s, z1.s, z2.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0x1f, 0x80, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x1f, 0x80, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xe0, 0x20, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.s, p0/z, z7.s" + + - + input: + bytes: [ 0x20, 0x80, 0x99, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.s, p0/m, z0.s, z1.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x80, 0x99, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsr z0.s, p0/m, z0.s, z1.d" diff --git a/tests/MC/AArch64/SVE/lsrr.s.yaml b/tests/MC/AArch64/SVE/lsrr.s.yaml new file mode 100644 index 0000000000..0ea0f06d47 --- /dev/null +++ b/tests/MC/AArch64/SVE/lsrr.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x15, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsrr z0.b, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x80, 0x55, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsrr z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x95, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsrr z0.s, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsrr z0.d, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0x80, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsrr z5.d, p0/m, z5.d, z0.d" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0x80, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "lsrr z5.d, p0/m, z5.d, z0.d" + + - + input: + bytes: [ 0x00, 0x80, 0x15, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsrr z0.b, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x80, 0x55, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsrr z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x95, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsrr z0.s, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsrr z0.d, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0x80, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsrr z5.d, p0/m, z5.d, z0.d" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0x80, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "lsrr z5.d, p0/m, z5.d, z0.d" diff --git a/tests/MC/AArch64/SVE/mad.s.yaml b/tests/MC/AArch64/SVE/mad.s.yaml new file mode 100644 index 0000000000..75a3c986da --- /dev/null +++ b/tests/MC/AArch64/SVE/mad.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xdf, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mad z0.b, p7/m, z1.b, z31.b" + + - + input: + bytes: [ 0xe0, 0xdf, 0x41, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mad z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0xe0, 0xdf, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mad z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0xe0, 0xdf, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mad z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0xdf, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mad z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xdf, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mad z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xdf, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mad z0.b, p7/m, z1.b, z31.b" + + - + input: + bytes: [ 0xe0, 0xdf, 0x41, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mad z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0xe0, 0xdf, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mad z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0xe0, 0xdf, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mad z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0xdf, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mad z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xdf, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mad z0.d, p7/m, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE/matrix-multiply-fp32.s.yaml b/tests/MC/AArch64/SVE/matrix-multiply-fp32.s.yaml new file mode 100644 index 0000000000..c4b09f55ba --- /dev/null +++ b/tests/MC/AArch64/SVE/matrix-multiply-fp32.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xe4, 0xa2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f32mm" ] + expected: + insns: + - + asm_text: "fmmla z0.s, z1.s, z2.s" diff --git a/tests/MC/AArch64/SVE/matrix-multiply-fp64.s.yaml b/tests/MC/AArch64/SVE/matrix-multiply-fp64.s.yaml new file mode 100644 index 0000000000..3235120c3b --- /dev/null +++ b/tests/MC/AArch64/SVE/matrix-multiply-fp64.s.yaml @@ -0,0 +1,390 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xe4, 0xe2, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "fmmla z0.d, z1.d, z2.d" + + - + input: + bytes: [ 0x40, 0x24, 0x27, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1rob { z0.b }, p1/z, [x2, #224]" + + - + input: + bytes: [ 0x40, 0x24, 0xa7, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1roh { z0.h }, p1/z, [x2, #224]" + + - + input: + bytes: [ 0x40, 0x24, 0x27, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1row { z0.s }, p1/z, [x2, #224]" + + - + input: + bytes: [ 0x40, 0x24, 0xa7, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1rod { z0.d }, p1/z, [x2, #224]" + + - + input: + bytes: [ 0x40, 0x24, 0x28, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1rob { z0.b }, p1/z, [x2, #-256]" + + - + input: + bytes: [ 0x40, 0x24, 0xa8, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1roh { z0.h }, p1/z, [x2, #-256]" + + - + input: + bytes: [ 0x40, 0x24, 0x28, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1row { z0.s }, p1/z, [x2, #-256]" + + - + input: + bytes: [ 0x40, 0x24, 0xa8, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1rod { z0.d }, p1/z, [x2, #-256]" + + - + input: + bytes: [ 0x40, 0x24, 0x20, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1rob { z0.b }, p1/z, [x2]" + + - + input: + bytes: [ 0x40, 0x24, 0xa0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1roh { z0.h }, p1/z, [x2]" + + - + input: + bytes: [ 0x40, 0x24, 0x20, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1row { z0.s }, p1/z, [x2]" + + - + input: + bytes: [ 0x40, 0x24, 0xa0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1rod { z0.d }, p1/z, [x2]" + + - + input: + bytes: [ 0x40, 0x24, 0x20, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1rob { z0.b }, p1/z, [x2]" + + - + input: + bytes: [ 0x40, 0x24, 0xa0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1roh { z0.h }, p1/z, [x2]" + + - + input: + bytes: [ 0x40, 0x24, 0x20, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1row { z0.s }, p1/z, [x2]" + + - + input: + bytes: [ 0x40, 0x24, 0xa0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1rod { z0.d }, p1/z, [x2]" + + - + input: + bytes: [ 0x40, 0x24, 0x27, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1rob { z0.b }, p1/z, [x2, #224]" + + - + input: + bytes: [ 0x40, 0x24, 0xa7, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1roh { z0.h }, p1/z, [x2, #224]" + + - + input: + bytes: [ 0x40, 0x24, 0x27, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1row { z0.s }, p1/z, [x2, #224]" + + - + input: + bytes: [ 0x40, 0x24, 0xa7, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1rod { z0.d }, p1/z, [x2, #224]" + + - + input: + bytes: [ 0x40, 0x24, 0x28, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1rob { z0.b }, p1/z, [x2, #-256]" + + - + input: + bytes: [ 0x40, 0x24, 0xa8, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1roh { z0.h }, p1/z, [x2, #-256]" + + - + input: + bytes: [ 0x40, 0x24, 0x28, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1row { z0.s }, p1/z, [x2, #-256]" + + - + input: + bytes: [ 0x40, 0x24, 0xa8, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1rod { z0.d }, p1/z, [x2, #-256]" + + - + input: + bytes: [ 0x40, 0x04, 0x23, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1rob { z0.b }, p1/z, [x2, x3]" + + - + input: + bytes: [ 0x40, 0x04, 0xa3, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1roh { z0.h }, p1/z, [x2, x3, lsl #1]" + + - + input: + bytes: [ 0x40, 0x04, 0x23, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1row { z0.s }, p1/z, [x2, x3, lsl #2]" + + - + input: + bytes: [ 0x40, 0x04, 0xa3, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1rod { z0.d }, p1/z, [x2, x3, lsl #3]" + + - + input: + bytes: [ 0x40, 0x04, 0x23, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1rob { z0.b }, p1/z, [x2, x3]" + + - + input: + bytes: [ 0x40, 0x04, 0xa3, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1roh { z0.h }, p1/z, [x2, x3, lsl #1]" + + - + input: + bytes: [ 0x40, 0x04, 0x23, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1row { z0.s }, p1/z, [x2, x3, lsl #2]" + + - + input: + bytes: [ 0x40, 0x04, 0xa3, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "ld1rod { z0.d }, p1/z, [x2, x3, lsl #3]" + + - + input: + bytes: [ 0x20, 0x00, 0xa2, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "zip1 z0.q, z1.q, z2.q" + + - + input: + bytes: [ 0x20, 0x04, 0xa2, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "zip2 z0.q, z1.q, z2.q" + + - + input: + bytes: [ 0x20, 0x08, 0xa2, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "uzp1 z0.q, z1.q, z2.q" + + - + input: + bytes: [ 0x20, 0x0c, 0xa2, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "uzp2 z0.q, z1.q, z2.q" + + - + input: + bytes: [ 0x20, 0x18, 0xa2, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "trn1 z0.q, z1.q, z2.q" + + - + input: + bytes: [ 0x20, 0x1c, 0xa2, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ] + expected: + insns: + - + asm_text: "trn2 z0.q, z1.q, z2.q" diff --git a/tests/MC/AArch64/SVE/matrix-multiply-int8.s.yaml b/tests/MC/AArch64/SVE/matrix-multiply-int8.s.yaml new file mode 100644 index 0000000000..729ee96505 --- /dev/null +++ b/tests/MC/AArch64/SVE/matrix-multiply-int8.s.yaml @@ -0,0 +1,180 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x98, 0xc2, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ] + expected: + insns: + - + asm_text: "ummla z0.s, z1.b, z2.b" + + - + input: + bytes: [ 0x20, 0x98, 0x02, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ] + expected: + insns: + - + asm_text: "smmla z0.s, z1.b, z2.b" + + - + input: + bytes: [ 0x20, 0x98, 0x82, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ] + expected: + insns: + - + asm_text: "usmmla z0.s, z1.b, z2.b" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x98, 0xc2, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ] + expected: + insns: + - + asm_text: "ummla z0.s, z1.b, z2.b" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x98, 0x02, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ] + expected: + insns: + - + asm_text: "smmla z0.s, z1.b, z2.b" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x98, 0x82, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ] + expected: + insns: + - + asm_text: "usmmla z0.s, z1.b, z2.b" + + - + input: + bytes: [ 0x20, 0x78, 0x82, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ] + expected: + insns: + - + asm_text: "usdot z0.s, z1.b, z2.b" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x78, 0x82, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ] + expected: + insns: + - + asm_text: "usdot z0.s, z1.b, z2.b" + + - + input: + bytes: [ 0x20, 0x18, 0xa2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ] + expected: + insns: + - + asm_text: "usdot z0.s, z1.b, z2.b[0]" + + - + input: + bytes: [ 0x20, 0x1c, 0xba, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ] + expected: + insns: + - + asm_text: "sudot z0.s, z1.b, z2.b[3]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x18, 0xa2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ] + expected: + insns: + - + asm_text: "usdot z0.s, z1.b, z2.b[0]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x1c, 0xa2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ] + expected: + insns: + - + asm_text: "sudot z0.s, z1.b, z2.b[0]" diff --git a/tests/MC/AArch64/SVE/mla.s.yaml b/tests/MC/AArch64/SVE/mla.s.yaml new file mode 100644 index 0000000000..034a798e41 --- /dev/null +++ b/tests/MC/AArch64/SVE/mla.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x5c, 0x1f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mla z0.b, p7/m, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x5c, 0x5f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mla z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x5c, 0x9f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mla z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x5c, 0xdf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mla z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0x5c, 0xdf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mla z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x5c, 0xdf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mla z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x5c, 0x1f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mla z0.b, p7/m, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x5c, 0x5f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mla z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x5c, 0x9f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mla z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x5c, 0xdf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mla z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0x5c, 0xdf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mla z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x5c, 0xdf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mla z0.d, p7/m, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE/mls.s.yaml b/tests/MC/AArch64/SVE/mls.s.yaml new file mode 100644 index 0000000000..1068ae7e34 --- /dev/null +++ b/tests/MC/AArch64/SVE/mls.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x7c, 0x1f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mls z0.b, p7/m, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x7c, 0x5f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mls z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x7c, 0x9f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mls z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x7c, 0xdf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mls z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0x7c, 0xdf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mls z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x7c, 0xdf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mls z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x7c, 0x1f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mls z0.b, p7/m, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x7c, 0x5f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mls z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x7c, 0x9f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mls z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x7c, 0xdf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mls z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0x20, 0x7c, 0xdf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mls z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x7c, 0xdf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mls z0.d, p7/m, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE/mov.s.yaml b/tests/MC/AArch64/SVE/mov.s.yaml new file mode 100644 index 0000000000..e2ca5060b4 --- /dev/null +++ b/tests/MC/AArch64/SVE/mov.s.yaml @@ -0,0 +1,2580 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x38, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.b, w0" + + - + input: + bytes: [ 0x00, 0x38, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, w0" + + - + input: + bytes: [ 0x00, 0x38, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.s, w0" + + - + input: + bytes: [ 0x00, 0x38, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.d, x0" + + - + input: + bytes: [ 0xff, 0x3b, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.h, wsp" + + - + input: + bytes: [ 0xff, 0x3b, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.s, wsp" + + - + input: + bytes: [ 0xff, 0x3b, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.d, sp" + + - + input: + bytes: [ 0xff, 0x3b, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.b, wsp" + + - + input: + bytes: [ 0x00, 0x30, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.d, z0.d" + + - + input: + bytes: [ 0x1f, 0x30, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.d, z0.d" + + - + input: + bytes: [ 0x05, 0xd0, 0x38, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z5.b, #-128" + + - + input: + bytes: [ 0xe5, 0xcf, 0x38, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z5.b, #127" + + - + input: + bytes: [ 0xe5, 0xdf, 0x38, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z5.b, #-1" + + - + input: + bytes: [ 0x15, 0xd0, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, #-128" + + - + input: + bytes: [ 0x15, 0xf0, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, #-32768" + + - + input: + bytes: [ 0x15, 0xf0, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, #-32768" + + - + input: + bytes: [ 0xf5, 0xcf, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, #127" + + - + input: + bytes: [ 0xf5, 0xef, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, #32512" + + - + input: + bytes: [ 0xf5, 0xef, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, #32512" + + - + input: + bytes: [ 0x15, 0xd0, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, #-128" + + - + input: + bytes: [ 0x15, 0xf0, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, #-32768" + + - + input: + bytes: [ 0x15, 0xf0, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, #-32768" + + - + input: + bytes: [ 0xf5, 0xcf, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, #127" + + - + input: + bytes: [ 0xf5, 0xef, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, #32512" + + - + input: + bytes: [ 0xf5, 0xef, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, #32512" + + - + input: + bytes: [ 0x15, 0xd0, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, #-128" + + - + input: + bytes: [ 0x15, 0xf0, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, #-32768" + + - + input: + bytes: [ 0x15, 0xf0, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, #-32768" + + - + input: + bytes: [ 0xf5, 0xcf, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, #127" + + - + input: + bytes: [ 0xf5, 0xef, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, #32512" + + - + input: + bytes: [ 0xf5, 0xef, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, #32512" + + - + input: + bytes: [ 0x00, 0xf0, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, #-32768" + + - + input: + bytes: [ 0xe0, 0xff, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, #-256" + + - + input: + bytes: [ 0xe0, 0xef, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, #32512" + + - + input: + bytes: [ 0xc0, 0x05, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, #32767" + + - + input: + bytes: [ 0xc0, 0x83, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.s, #0xffff7fff" + + - + input: + bytes: [ 0x00, 0x88, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.s, #32768" + + - + input: + bytes: [ 0xc0, 0x87, 0xc3, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.d, #0xffffffffffff7fff" + + - + input: + bytes: [ 0x00, 0x88, 0xc3, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.d, #32768" + + - + input: + bytes: [ 0x80, 0x19, 0xc2, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.d, #0xe0000000000003ff" + + - + input: + bytes: [ 0x05, 0x10, 0x10, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z5.b, p0/z, #-128" + + - + input: + bytes: [ 0xe5, 0x0f, 0x10, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z5.b, p0/z, #127" + + - + input: + bytes: [ 0xe5, 0x1f, 0x10, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z5.b, p0/z, #-1" + + - + input: + bytes: [ 0x15, 0x10, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #-128" + + - + input: + bytes: [ 0x15, 0x30, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #-32768" + + - + input: + bytes: [ 0x15, 0x30, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #-32768" + + - + input: + bytes: [ 0xf5, 0x0f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #127" + + - + input: + bytes: [ 0xf5, 0x2f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #32512" + + - + input: + bytes: [ 0xf5, 0x2f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #32512" + + - + input: + bytes: [ 0x15, 0x10, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #-128" + + - + input: + bytes: [ 0x15, 0x30, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #-32768" + + - + input: + bytes: [ 0x15, 0x30, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #-32768" + + - + input: + bytes: [ 0xf5, 0x0f, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #127" + + - + input: + bytes: [ 0xf5, 0x2f, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #32512" + + - + input: + bytes: [ 0xf5, 0x2f, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #32512" + + - + input: + bytes: [ 0x15, 0x10, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #-128" + + - + input: + bytes: [ 0x15, 0x30, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #-32768" + + - + input: + bytes: [ 0x15, 0x30, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #-32768" + + - + input: + bytes: [ 0xf5, 0x0f, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #127" + + - + input: + bytes: [ 0xf5, 0x2f, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #32512" + + - + input: + bytes: [ 0xf5, 0x2f, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #32512" + + - + input: + bytes: [ 0xe0, 0xcf, 0x38, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.b, #127" + + - + input: + bytes: [ 0xe0, 0xef, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, #32512" + + - + input: + bytes: [ 0x45, 0xdf, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z5.h, #-6" + + - + input: + bytes: [ 0x45, 0xdf, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z5.s, #-6" + + - + input: + bytes: [ 0x45, 0xdf, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z5.d, #-6" + + - + input: + bytes: [ 0xe0, 0x0f, 0x10, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.b, p0/z, #127" + + - + input: + bytes: [ 0xe0, 0x2f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/z, #32512" + + - + input: + bytes: [ 0xe0, 0x2f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/z, #32512" + + - + input: + bytes: [ 0x05, 0x50, 0x1f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z5.b, p15/m, #-128" + + - + input: + bytes: [ 0x15, 0x50, 0x5f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, p15/m, #-128" + + - + input: + bytes: [ 0x15, 0x70, 0x5f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.h, p15/m, #-32768" + + - + input: + bytes: [ 0x15, 0x50, 0x9f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, p15/m, #-128" + + - + input: + bytes: [ 0x15, 0x70, 0x9f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.s, p15/m, #-32768" + + - + input: + bytes: [ 0x15, 0x50, 0xdf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p15/m, #-128" + + - + input: + bytes: [ 0x15, 0x70, 0xdf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p15/m, #-32768" + + - + input: + bytes: [ 0x00, 0x20, 0x21, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.b, b0" + + - + input: + bytes: [ 0x00, 0x20, 0x22, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, h0" + + - + input: + bytes: [ 0x00, 0x20, 0x24, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.s, s0" + + - + input: + bytes: [ 0x00, 0x20, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.d, d0" + + - + input: + bytes: [ 0x00, 0x20, 0x30, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.q, q0" + + - + input: + bytes: [ 0x00, 0x20, 0x21, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.b, b0" + + - + input: + bytes: [ 0x00, 0x20, 0x22, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, h0" + + - + input: + bytes: [ 0x00, 0x20, 0x24, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.s, s0" + + - + input: + bytes: [ 0x00, 0x20, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.d, d0" + + - + input: + bytes: [ 0x00, 0x20, 0x30, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.q, q0" + + - + input: + bytes: [ 0xff, 0x23, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.b, z31.b[63]" + + - + input: + bytes: [ 0xff, 0x23, 0xfe, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.h, z31.h[31]" + + - + input: + bytes: [ 0xff, 0x23, 0xfc, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.s, z31.s[15]" + + - + input: + bytes: [ 0xff, 0x23, 0xf8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.d, z31.d[7]" + + - + input: + bytes: [ 0x25, 0x22, 0xf0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z5.q, z17.q[3]" + + - + input: + bytes: [ 0x00, 0xa0, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.b, p0/m, w0" + + - + input: + bytes: [ 0x00, 0xa0, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/m, w0" + + - + input: + bytes: [ 0x00, 0xa0, 0xa8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.s, p0/m, w0" + + - + input: + bytes: [ 0x00, 0xa0, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.d, p0/m, x0" + + - + input: + bytes: [ 0xff, 0xbf, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.b, p7/m, wsp" + + - + input: + bytes: [ 0xff, 0xbf, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.h, p7/m, wsp" + + - + input: + bytes: [ 0xff, 0xbf, 0xa8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.s, p7/m, wsp" + + - + input: + bytes: [ 0xff, 0xbf, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, sp" + + - + input: + bytes: [ 0x00, 0x80, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.b, p0/m, b0" + + - + input: + bytes: [ 0xff, 0x9f, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.b, p7/m, b31" + + - + input: + bytes: [ 0x00, 0x80, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/m, h0" + + - + input: + bytes: [ 0xff, 0x9f, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.h, p7/m, h31" + + - + input: + bytes: [ 0x00, 0x80, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.s, p0/m, s0" + + - + input: + bytes: [ 0xff, 0x9f, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.s, p7/m, s31" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.d, p0/m, d0" + + - + input: + bytes: [ 0xff, 0x9f, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, d31" + + - + input: + bytes: [ 0x10, 0x42, 0x00, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov p0.b, p0/m, p0.b" + + - + input: + bytes: [ 0xff, 0x7f, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov p15.b, p15/m, p15.b" + + - + input: + bytes: [ 0xff, 0xff, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.b, p15/m, z31.b" + + - + input: + bytes: [ 0xff, 0xff, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.h, p15/m, z31.h" + + - + input: + bytes: [ 0xff, 0xff, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.s, p15/m, z31.s" + + - + input: + bytes: [ 0xff, 0xff, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.d, p15/m, z31.d" + + - + input: + bytes: [ 0x00, 0x40, 0x80, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov p0.b, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov p15.b, p15.b" + + - + input: + bytes: [ 0x00, 0x40, 0x00, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov p0.b, p0/z, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov p15.b, p15/z, p15.b" + + - + input: + bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p7/z, z6.d" + + - + input: + bytes: [ 0xff, 0xbf, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, sp" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xbf, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, sp" + + - + input: + bytes: [ 0x95, 0x3f, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z21.d, p7/z, z28.d" + + - + input: + bytes: [ 0x15, 0x70, 0xd7, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p7/m, #-32768" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x15, 0x70, 0xdf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z21.d, p15/m, #-32768" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x9f, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z4.d, p7/m, d31" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x9f, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z4.d, p7/m, d31" + + - + input: + bytes: [ 0x00, 0x38, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, w0" + + - + input: + bytes: [ 0x00, 0x38, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, w0" + + - + input: + bytes: [ 0x00, 0x38, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, w0" + + - + input: + bytes: [ 0x00, 0x38, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, x0" + + - + input: + bytes: [ 0xff, 0x3b, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.h, wsp" + + - + input: + bytes: [ 0xff, 0x3b, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.s, wsp" + + - + input: + bytes: [ 0xff, 0x3b, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.d, sp" + + - + input: + bytes: [ 0xff, 0x3b, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.b, wsp" + + - + input: + bytes: [ 0x00, 0x30, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, z0.d" + + - + input: + bytes: [ 0x1f, 0x30, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.d, z0.d" + + - + input: + bytes: [ 0x05, 0xd0, 0x38, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.b, #-128" + + - + input: + bytes: [ 0xe5, 0xcf, 0x38, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.b, #127" + + - + input: + bytes: [ 0xe5, 0xdf, 0x38, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.b, #-1" + + - + input: + bytes: [ 0x15, 0xd0, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, #-128" + + - + input: + bytes: [ 0x15, 0xf0, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, #-32768" + + - + input: + bytes: [ 0x15, 0xf0, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, #-32768" + + - + input: + bytes: [ 0xf5, 0xcf, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, #127" + + - + input: + bytes: [ 0xf5, 0xef, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, #32512" + + - + input: + bytes: [ 0xf5, 0xef, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, #32512" + + - + input: + bytes: [ 0x15, 0xd0, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, #-128" + + - + input: + bytes: [ 0x15, 0xf0, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, #-32768" + + - + input: + bytes: [ 0x15, 0xf0, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, #-32768" + + - + input: + bytes: [ 0xf5, 0xcf, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, #127" + + - + input: + bytes: [ 0xf5, 0xef, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, #32512" + + - + input: + bytes: [ 0xf5, 0xef, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, #32512" + + - + input: + bytes: [ 0x15, 0xd0, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, #-128" + + - + input: + bytes: [ 0x15, 0xf0, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, #-32768" + + - + input: + bytes: [ 0x15, 0xf0, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, #-32768" + + - + input: + bytes: [ 0xf5, 0xcf, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, #127" + + - + input: + bytes: [ 0xf5, 0xef, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, #32512" + + - + input: + bytes: [ 0xf5, 0xef, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, #32512" + + - + input: + bytes: [ 0x00, 0xf0, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, #-32768" + + - + input: + bytes: [ 0xe0, 0xff, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, #-256" + + - + input: + bytes: [ 0xe0, 0xef, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, #32512" + + - + input: + bytes: [ 0xc0, 0x05, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, #32767" + + - + input: + bytes: [ 0xc0, 0x83, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, #0xffff7fff" + + - + input: + bytes: [ 0x00, 0x88, 0xc0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, #32768" + + - + input: + bytes: [ 0xc0, 0x87, 0xc3, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, #0xffffffffffff7fff" + + - + input: + bytes: [ 0x00, 0x88, 0xc3, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, #32768" + + - + input: + bytes: [ 0x80, 0x19, 0xc2, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, #0xe0000000000003ff" + + - + input: + bytes: [ 0x05, 0x10, 0x10, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.b, p0/z, #-128" + + - + input: + bytes: [ 0xe5, 0x0f, 0x10, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.b, p0/z, #127" + + - + input: + bytes: [ 0xe5, 0x1f, 0x10, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.b, p0/z, #-1" + + - + input: + bytes: [ 0x15, 0x10, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #-128" + + - + input: + bytes: [ 0x15, 0x30, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #-32768" + + - + input: + bytes: [ 0x15, 0x30, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #-32768" + + - + input: + bytes: [ 0xf5, 0x0f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #127" + + - + input: + bytes: [ 0xf5, 0x2f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #32512" + + - + input: + bytes: [ 0xf5, 0x2f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p0/z, #32512" + + - + input: + bytes: [ 0x15, 0x10, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #-128" + + - + input: + bytes: [ 0x15, 0x30, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #-32768" + + - + input: + bytes: [ 0x15, 0x30, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #-32768" + + - + input: + bytes: [ 0xf5, 0x0f, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #127" + + - + input: + bytes: [ 0xf5, 0x2f, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #32512" + + - + input: + bytes: [ 0xf5, 0x2f, 0x90, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p0/z, #32512" + + - + input: + bytes: [ 0x15, 0x10, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #-128" + + - + input: + bytes: [ 0x15, 0x30, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #-32768" + + - + input: + bytes: [ 0x15, 0x30, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #-32768" + + - + input: + bytes: [ 0xf5, 0x0f, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #127" + + - + input: + bytes: [ 0xf5, 0x2f, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #32512" + + - + input: + bytes: [ 0xf5, 0x2f, 0xd0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p0/z, #32512" + + - + input: + bytes: [ 0xe0, 0xcf, 0x38, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, #127" + + - + input: + bytes: [ 0xe0, 0xef, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, #32512" + + - + input: + bytes: [ 0x45, 0xdf, 0x78, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.h, #-6" + + - + input: + bytes: [ 0x45, 0xdf, 0xb8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.s, #-6" + + - + input: + bytes: [ 0x45, 0xdf, 0xf8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.d, #-6" + + - + input: + bytes: [ 0xe0, 0x0f, 0x10, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, p0/z, #127" + + - + input: + bytes: [ 0xe0, 0x2f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/z, #32512" + + - + input: + bytes: [ 0xe0, 0x2f, 0x50, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/z, #32512" + + - + input: + bytes: [ 0x05, 0x50, 0x1f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.b, p15/m, #-128" + + - + input: + bytes: [ 0x15, 0x50, 0x5f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p15/m, #-128" + + - + input: + bytes: [ 0x15, 0x70, 0x5f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.h, p15/m, #-32768" + + - + input: + bytes: [ 0x15, 0x50, 0x9f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p15/m, #-128" + + - + input: + bytes: [ 0x15, 0x70, 0x9f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.s, p15/m, #-32768" + + - + input: + bytes: [ 0x15, 0x50, 0xdf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p15/m, #-128" + + - + input: + bytes: [ 0x15, 0x70, 0xdf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p15/m, #-32768" + + - + input: + bytes: [ 0x00, 0x20, 0x21, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, b0" + + - + input: + bytes: [ 0x00, 0x20, 0x22, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, h0" + + - + input: + bytes: [ 0x00, 0x20, 0x24, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, s0" + + - + input: + bytes: [ 0x00, 0x20, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, d0" + + - + input: + bytes: [ 0x00, 0x20, 0x30, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.q, q0" + + - + input: + bytes: [ 0x00, 0x20, 0x21, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, b0" + + - + input: + bytes: [ 0x00, 0x20, 0x22, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, h0" + + - + input: + bytes: [ 0x00, 0x20, 0x24, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, s0" + + - + input: + bytes: [ 0x00, 0x20, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, d0" + + - + input: + bytes: [ 0x00, 0x20, 0x30, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.q, q0" + + - + input: + bytes: [ 0xff, 0x23, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.b, z31.b[63]" + + - + input: + bytes: [ 0xff, 0x23, 0xfe, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.h, z31.h[31]" + + - + input: + bytes: [ 0xff, 0x23, 0xfc, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.s, z31.s[15]" + + - + input: + bytes: [ 0xff, 0x23, 0xf8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.d, z31.d[7]" + + - + input: + bytes: [ 0x25, 0x22, 0xf0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z5.q, z17.q[3]" + + - + input: + bytes: [ 0x00, 0xa0, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, p0/m, w0" + + - + input: + bytes: [ 0x00, 0xa0, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/m, w0" + + - + input: + bytes: [ 0x00, 0xa0, 0xa8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, p0/m, w0" + + - + input: + bytes: [ 0x00, 0xa0, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, p0/m, x0" + + - + input: + bytes: [ 0xff, 0xbf, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.b, p7/m, wsp" + + - + input: + bytes: [ 0xff, 0xbf, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.h, p7/m, wsp" + + - + input: + bytes: [ 0xff, 0xbf, 0xa8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.s, p7/m, wsp" + + - + input: + bytes: [ 0xff, 0xbf, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, sp" + + - + input: + bytes: [ 0x00, 0x80, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.b, p0/m, b0" + + - + input: + bytes: [ 0xff, 0x9f, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.b, p7/m, b31" + + - + input: + bytes: [ 0x00, 0x80, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.h, p0/m, h0" + + - + input: + bytes: [ 0xff, 0x9f, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.h, p7/m, h31" + + - + input: + bytes: [ 0x00, 0x80, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.s, p0/m, s0" + + - + input: + bytes: [ 0xff, 0x9f, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.s, p7/m, s31" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, p0/m, d0" + + - + input: + bytes: [ 0xff, 0x9f, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, d31" + + - + input: + bytes: [ 0x10, 0x42, 0x00, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov p0.b, p0/m, p0.b" + + - + input: + bytes: [ 0xff, 0x7f, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov p15.b, p15/m, p15.b" + + - + input: + bytes: [ 0xff, 0xff, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.b, p15/m, z31.b" + + - + input: + bytes: [ 0xff, 0xff, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.h, p15/m, z31.h" + + - + input: + bytes: [ 0xff, 0xff, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.s, p15/m, z31.s" + + - + input: + bytes: [ 0xff, 0xff, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.d, p15/m, z31.d" + + - + input: + bytes: [ 0x00, 0x40, 0x80, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov p0.b, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov p15.b, p15.b" + + - + input: + bytes: [ 0x00, 0x40, 0x00, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov p0.b, p0/z, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov p15.b, p15/z, p15.b" + + - + input: + bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p7/z, z6.d" + + - + input: + bytes: [ 0xff, 0xbf, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, sp" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xbf, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.d, p7/m, sp" + + - + input: + bytes: [ 0x95, 0x3f, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21.d, p7/z, z28.d" + + - + input: + bytes: [ 0x15, 0x70, 0xd7, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p7/m, #-32768" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x15, 0x70, 0xdf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z21.d, p15/m, #-32768" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x9f, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z4.d, p7/m, d31" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x9f, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z4.d, p7/m, d31" diff --git a/tests/MC/AArch64/SVE/movprfx.s.yaml b/tests/MC/AArch64/SVE/movprfx.s.yaml new file mode 100644 index 0000000000..4be441473d --- /dev/null +++ b/tests/MC/AArch64/SVE/movprfx.s.yaml @@ -0,0 +1,220 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z1" + + - + input: + bytes: [ 0x20, 0x00, 0x40, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "hlt #0x1" + + - + input: + bytes: [ 0x20, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p0/z, z1.d" + + - + input: + bytes: [ 0x20, 0x00, 0x40, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "hlt #0x1" + + - + input: + bytes: [ 0x20, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z1" + + - + input: + bytes: [ 0x20, 0x00, 0x20, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brk #0x1" + + - + input: + bytes: [ 0x20, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p0/z, z1.d" + + - + input: + bytes: [ 0x20, 0x00, 0x20, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "brk #0x1" + + - + input: + bytes: [ 0x20, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z1" + + - + input: + bytes: [ 0x20, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z0.d, p0/m, z0.d, z1.d" + + - + input: + bytes: [ 0x20, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "add z0.d, p0/m, z0.d, z1.d" + + - + input: + bytes: [ 0x20, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z1" + + - + input: + bytes: [ 0x20, 0x00, 0x40, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "hlt #0x1" + + - + input: + bytes: [ 0x20, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p0/z, z1.d" + + - + input: + bytes: [ 0x20, 0x00, 0x40, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "hlt #0x1" + + - + input: + bytes: [ 0x20, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z1" + + - + input: + bytes: [ 0x20, 0x00, 0x20, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brk #0x1" + + - + input: + bytes: [ 0x20, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p0/z, z1.d" + + - + input: + bytes: [ 0x20, 0x00, 0x20, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "brk #0x1" + + - + input: + bytes: [ 0x20, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z1" + + - + input: + bytes: [ 0x20, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z0.d, p0/m, z0.d, z1.d" + + - + input: + bytes: [ 0x20, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "add z0.d, p0/m, z0.d, z1.d" diff --git a/tests/MC/AArch64/SVE/movs.s.yaml b/tests/MC/AArch64/SVE/movs.s.yaml new file mode 100644 index 0000000000..fd777a6a54 --- /dev/null +++ b/tests/MC/AArch64/SVE/movs.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0xc0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movs p0.b, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movs p15.b, p15.b" + + - + input: + bytes: [ 0x00, 0x40, 0x40, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movs p0.b, p0/z, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movs p15.b, p15/z, p15.b" + + - + input: + bytes: [ 0x00, 0x40, 0xc0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movs p0.b, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movs p15.b, p15.b" + + - + input: + bytes: [ 0x00, 0x40, 0x40, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movs p0.b, p0/z, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movs p15.b, p15/z, p15.b" diff --git a/tests/MC/AArch64/SVE/msb.s.yaml b/tests/MC/AArch64/SVE/msb.s.yaml new file mode 100644 index 0000000000..9617957734 --- /dev/null +++ b/tests/MC/AArch64/SVE/msb.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xff, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "msb z0.b, p7/m, z1.b, z31.b" + + - + input: + bytes: [ 0xe0, 0xff, 0x41, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "msb z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0xe0, 0xff, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "msb z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0xe0, 0xff, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "msb z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0xff, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "msb z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xff, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "msb z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xff, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "msb z0.b, p7/m, z1.b, z31.b" + + - + input: + bytes: [ 0xe0, 0xff, 0x41, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "msb z0.h, p7/m, z1.h, z31.h" + + - + input: + bytes: [ 0xe0, 0xff, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "msb z0.s, p7/m, z1.s, z31.s" + + - + input: + bytes: [ 0xe0, 0xff, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "msb z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0xff, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "msb z0.d, p7/m, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xff, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "msb z0.d, p7/m, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE/mul.s.yaml b/tests/MC/AArch64/SVE/mul.s.yaml new file mode 100644 index 0000000000..55ca513a8f --- /dev/null +++ b/tests/MC/AArch64/SVE/mul.s.yaml @@ -0,0 +1,360 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x1f, 0x10, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mul z0.b, p7/m, z0.b, z31.b" + + - + input: + bytes: [ 0xe0, 0x1f, 0x50, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mul z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x1f, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mul z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mul z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0x1f, 0xd0, 0x30, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mul z31.b, z31.b, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0x30, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mul z31.b, z31.b, #127" + + - + input: + bytes: [ 0x1f, 0xd0, 0x70, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mul z31.h, z31.h, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0x70, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mul z31.h, z31.h, #127" + + - + input: + bytes: [ 0x1f, 0xd0, 0xb0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mul z31.s, z31.s, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0xb0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mul z31.s, z31.s, #127" + + - + input: + bytes: [ 0x1f, 0xd0, 0xf0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mul z31.d, z31.d, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0xf0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mul z31.d, z31.d, #127" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mul z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mul z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xcf, 0xf0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mul z31.d, z31.d, #127" + + - + input: + bytes: [ 0xe0, 0x1f, 0x10, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z0.b, p7/m, z0.b, z31.b" + + - + input: + bytes: [ 0xe0, 0x1f, 0x50, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x1f, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0x1f, 0xd0, 0x30, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z31.b, z31.b, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0x30, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z31.b, z31.b, #127" + + - + input: + bytes: [ 0x1f, 0xd0, 0x70, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z31.h, z31.h, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0x70, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z31.h, z31.h, #127" + + - + input: + bytes: [ 0x1f, 0xd0, 0xb0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z31.s, z31.s, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0xb0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z31.s, z31.s, #127" + + - + input: + bytes: [ 0x1f, 0xd0, 0xf0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z31.d, z31.d, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0xf0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z31.d, z31.d, #127" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xcf, 0xf0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z31.d, z31.d, #127" diff --git a/tests/MC/AArch64/SVE/nand.s.yaml b/tests/MC/AArch64/SVE/nand.s.yaml new file mode 100644 index 0000000000..683abfe694 --- /dev/null +++ b/tests/MC/AArch64/SVE/nand.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x42, 0x80, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "nand p0.b, p0/z, p0.b, p0.b" + + - + input: + bytes: [ 0xff, 0x7f, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "nand p15.b, p15/z, p15.b, p15.b" + + - + input: + bytes: [ 0x10, 0x42, 0x80, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "nand p0.b, p0/z, p0.b, p0.b" + + - + input: + bytes: [ 0xff, 0x7f, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "nand p15.b, p15/z, p15.b, p15.b" diff --git a/tests/MC/AArch64/SVE/nands.s.yaml b/tests/MC/AArch64/SVE/nands.s.yaml new file mode 100644 index 0000000000..61b12c9e73 --- /dev/null +++ b/tests/MC/AArch64/SVE/nands.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x42, 0xc0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "nands p0.b, p0/z, p0.b, p0.b" + + - + input: + bytes: [ 0xff, 0x7f, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "nands p15.b, p15/z, p15.b, p15.b" + + - + input: + bytes: [ 0x10, 0x42, 0xc0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "nands p0.b, p0/z, p0.b, p0.b" + + - + input: + bytes: [ 0xff, 0x7f, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "nands p15.b, p15/z, p15.b, p15.b" diff --git a/tests/MC/AArch64/SVE/neg.s.yaml b/tests/MC/AArch64/SVE/neg.s.yaml new file mode 100644 index 0000000000..139ac857f5 --- /dev/null +++ b/tests/MC/AArch64/SVE/neg.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x17, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "neg z0.b, p0/m, z0.b" + + - + input: + bytes: [ 0x00, 0xa0, 0x57, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "neg z0.h, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x97, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "neg z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "neg z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x17, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "neg z31.b, p7/m, z31.b" + + - + input: + bytes: [ 0xff, 0xbf, 0x57, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "neg z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x97, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "neg z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "neg z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "neg z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "neg z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x17, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "neg z0.b, p0/m, z0.b" + + - + input: + bytes: [ 0x00, 0xa0, 0x57, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "neg z0.h, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x97, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "neg z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "neg z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x17, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "neg z31.b, p7/m, z31.b" + + - + input: + bytes: [ 0xff, 0xbf, 0x57, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "neg z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x97, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "neg z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "neg z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "neg z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "neg z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/nor.s.yaml b/tests/MC/AArch64/SVE/nor.s.yaml new file mode 100644 index 0000000000..54f5faff76 --- /dev/null +++ b/tests/MC/AArch64/SVE/nor.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x42, 0x80, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "nor p0.b, p0/z, p0.b, p0.b" + + - + input: + bytes: [ 0xef, 0x7f, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "nor p15.b, p15/z, p15.b, p15.b" + + - + input: + bytes: [ 0x00, 0x42, 0x80, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "nor p0.b, p0/z, p0.b, p0.b" + + - + input: + bytes: [ 0xef, 0x7f, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "nor p15.b, p15/z, p15.b, p15.b" diff --git a/tests/MC/AArch64/SVE/nors.s.yaml b/tests/MC/AArch64/SVE/nors.s.yaml new file mode 100644 index 0000000000..140a2ddbec --- /dev/null +++ b/tests/MC/AArch64/SVE/nors.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x42, 0xc0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "nors p0.b, p0/z, p0.b, p0.b" + + - + input: + bytes: [ 0xef, 0x7f, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "nors p15.b, p15/z, p15.b, p15.b" + + - + input: + bytes: [ 0x00, 0x42, 0xc0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "nors p0.b, p0/z, p0.b, p0.b" + + - + input: + bytes: [ 0xef, 0x7f, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "nors p15.b, p15/z, p15.b, p15.b" diff --git a/tests/MC/AArch64/SVE/not.s.yaml b/tests/MC/AArch64/SVE/not.s.yaml new file mode 100644 index 0000000000..1a6a365f0b --- /dev/null +++ b/tests/MC/AArch64/SVE/not.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x1e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "not z31.b, p7/m, z31.b" + + - + input: + bytes: [ 0xff, 0xbf, 0x5e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "not z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x9e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "not z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xde, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "not z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0x00, 0x42, 0x00, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "not p0.b, p0/z, p0.b" + + - + input: + bytes: [ 0xef, 0x7f, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "not p15.b, p15/z, p15.b" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xde, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "not z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xde, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "not z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x1e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "not z31.b, p7/m, z31.b" + + - + input: + bytes: [ 0xff, 0xbf, 0x5e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "not z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x9e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "not z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xde, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "not z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0x00, 0x42, 0x00, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "not p0.b, p0/z, p0.b" + + - + input: + bytes: [ 0xef, 0x7f, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "not p15.b, p15/z, p15.b" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xde, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "not z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xde, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "not z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/nots.s.yaml b/tests/MC/AArch64/SVE/nots.s.yaml new file mode 100644 index 0000000000..1aa86ad61c --- /dev/null +++ b/tests/MC/AArch64/SVE/nots.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x42, 0x40, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "nots p0.b, p0/z, p0.b" + + - + input: + bytes: [ 0xef, 0x7f, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "nots p15.b, p15/z, p15.b" + + - + input: + bytes: [ 0x00, 0x42, 0x40, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "nots p0.b, p0/z, p0.b" + + - + input: + bytes: [ 0xef, 0x7f, 0x4f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "nots p15.b, p15/z, p15.b" diff --git a/tests/MC/AArch64/SVE/orn.s.yaml b/tests/MC/AArch64/SVE/orn.s.yaml new file mode 100644 index 0000000000..1ea97978f8 --- /dev/null +++ b/tests/MC/AArch64/SVE/orn.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x25, 0x3e, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z5.b, z5.b, #0x6" + + - + input: + bytes: [ 0x37, 0x7c, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z23.h, z23.h, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z0.s, z0.s, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x03, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z0.d, z0.d, #0x6" + + - + input: + bytes: [ 0xa5, 0x2e, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z5.b, z5.b, #0xf9" + + - + input: + bytes: [ 0xb7, 0x6d, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z23.h, z23.h, #0xfff9" + + - + input: + bytes: [ 0xa0, 0xeb, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z0.s, z0.s, #0xfffffff9" + + - + input: + bytes: [ 0xa0, 0xef, 0x03, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z0.d, z0.d, #0xfffffffffffffff9" + + - + input: + bytes: [ 0x10, 0x40, 0x80, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orn p0.b, p0/z, p0.b, p0.b" + + - + input: + bytes: [ 0xff, 0x7d, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orn p15.b, p15/z, p15.b, p15.b" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xa0, 0xef, 0x03, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z0.d, z0.d, #0xfffffffffffffff9" + + - + input: + bytes: [ 0x25, 0x3e, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z5.b, z5.b, #0x6" + + - + input: + bytes: [ 0x37, 0x7c, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z23.h, z23.h, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z0.s, z0.s, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x03, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z0.d, z0.d, #0x6" + + - + input: + bytes: [ 0xa5, 0x2e, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z5.b, z5.b, #0xf9" + + - + input: + bytes: [ 0xb7, 0x6d, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z23.h, z23.h, #0xfff9" + + - + input: + bytes: [ 0xa0, 0xeb, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z0.s, z0.s, #0xfffffff9" + + - + input: + bytes: [ 0xa0, 0xef, 0x03, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z0.d, z0.d, #0xfffffffffffffff9" + + - + input: + bytes: [ 0x10, 0x40, 0x80, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orn p0.b, p0/z, p0.b, p0.b" + + - + input: + bytes: [ 0xff, 0x7d, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orn p15.b, p15/z, p15.b, p15.b" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xa0, 0xef, 0x03, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z0.d, z0.d, #0xfffffffffffffff9" diff --git a/tests/MC/AArch64/SVE/orns.s.yaml b/tests/MC/AArch64/SVE/orns.s.yaml new file mode 100644 index 0000000000..3e9eb1aaf9 --- /dev/null +++ b/tests/MC/AArch64/SVE/orns.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x40, 0xc0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orns p0.b, p0/z, p0.b, p0.b" + + - + input: + bytes: [ 0xff, 0x7d, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orns p15.b, p15/z, p15.b, p15.b" + + - + input: + bytes: [ 0x10, 0x40, 0xc0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orns p0.b, p0/z, p0.b, p0.b" + + - + input: + bytes: [ 0xff, 0x7d, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orns p15.b, p15/z, p15.b, p15.b" diff --git a/tests/MC/AArch64/SVE/orr.s.yaml b/tests/MC/AArch64/SVE/orr.s.yaml new file mode 100644 index 0000000000..a700e1f346 --- /dev/null +++ b/tests/MC/AArch64/SVE/orr.s.yaml @@ -0,0 +1,580 @@ +test_cases: + - + input: + bytes: [ 0xa5, 0x2e, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z5.b, z5.b, #0xf9" + + - + input: + bytes: [ 0xb7, 0x6d, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z23.h, z23.h, #0xfff9" + + - + input: + bytes: [ 0xa0, 0xeb, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z0.s, z0.s, #0xfffffff9" + + - + input: + bytes: [ 0xa0, 0xef, 0x03, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z0.d, z0.d, #0xfffffffffffffff9" + + - + input: + bytes: [ 0x25, 0x3e, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z5.b, z5.b, #0x6" + + - + input: + bytes: [ 0x37, 0x7c, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z23.h, z23.h, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z0.s, z0.s, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x03, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z0.d, z0.d, #0x6" + + - + input: + bytes: [ 0x00, 0x30, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.d, z0.d" + + - + input: + bytes: [ 0xb7, 0x31, 0x68, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0x1f, 0x18, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x1f, 0x58, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x98, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0xd8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0x40, 0x81, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr p0.b, p0/z, p0.b, p1.b" + + - + input: + bytes: [ 0x00, 0x40, 0x80, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov p0.b, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov p15.b, p15.b" + + - + input: + bytes: [ 0x00, 0x30, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x30, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x30, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z0.d, z0.d" + + - + input: + bytes: [ 0xb7, 0x31, 0x68, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xb7, 0x31, 0x68, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xb7, 0x31, 0x68, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x1f, 0xd8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0xd8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xf8, 0x03, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orr z0.d, z0.d, #0x6" + + - + input: + bytes: [ 0xa5, 0x2e, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z5.b, z5.b, #0xf9" + + - + input: + bytes: [ 0xb7, 0x6d, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z23.h, z23.h, #0xfff9" + + - + input: + bytes: [ 0xa0, 0xeb, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z0.s, z0.s, #0xfffffff9" + + - + input: + bytes: [ 0xa0, 0xef, 0x03, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z0.d, z0.d, #0xfffffffffffffff9" + + - + input: + bytes: [ 0x25, 0x3e, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z5.b, z5.b, #0x6" + + - + input: + bytes: [ 0x37, 0x7c, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z23.h, z23.h, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x00, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z0.s, z0.s, #0x6" + + - + input: + bytes: [ 0x20, 0xf8, 0x03, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z0.d, z0.d, #0x6" + + - + input: + bytes: [ 0x00, 0x30, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, z0.d" + + - + input: + bytes: [ 0xb7, 0x31, 0x68, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0x1f, 0x18, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x1f, 0x58, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x98, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0xd8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0x40, 0x81, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr p0.b, p0/z, p0.b, p1.b" + + - + input: + bytes: [ 0x00, 0x40, 0x80, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov p0.b, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0x8f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov p15.b, p15.b" + + - + input: + bytes: [ 0x00, 0x30, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x30, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x30, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z0.d, z0.d" + + - + input: + bytes: [ 0xb7, 0x31, 0x68, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xb7, 0x31, 0x68, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xb7, 0x31, 0x68, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x1f, 0xd8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0xd8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xf8, 0x03, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orr z0.d, z0.d, #0x6" diff --git a/tests/MC/AArch64/SVE/orrs.s.yaml b/tests/MC/AArch64/SVE/orrs.s.yaml new file mode 100644 index 0000000000..27ca418786 --- /dev/null +++ b/tests/MC/AArch64/SVE/orrs.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0xc1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orrs p0.b, p0/z, p0.b, p1.b" + + - + input: + bytes: [ 0x00, 0x40, 0xc0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movs p0.b, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movs p15.b, p15.b" + + - + input: + bytes: [ 0x00, 0x40, 0xc1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orrs p0.b, p0/z, p0.b, p1.b" + + - + input: + bytes: [ 0x00, 0x40, 0xc0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movs p0.b, p0.b" + + - + input: + bytes: [ 0xef, 0x7d, 0xcf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movs p15.b, p15.b" diff --git a/tests/MC/AArch64/SVE/orv.s.yaml b/tests/MC/AArch64/SVE/orv.s.yaml new file mode 100644 index 0000000000..5afb78af5e --- /dev/null +++ b/tests/MC/AArch64/SVE/orv.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x3f, 0x18, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orv b0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x58, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x98, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xd8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "orv d0, p7, z31.d" + + - + input: + bytes: [ 0xe0, 0x3f, 0x18, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orv b0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x58, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x98, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xd8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "orv d0, p7, z31.d" diff --git a/tests/MC/AArch64/SVE/pfalse.s.yaml b/tests/MC/AArch64/SVE/pfalse.s.yaml new file mode 100644 index 0000000000..171c4a64ab --- /dev/null +++ b/tests/MC/AArch64/SVE/pfalse.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x0f, 0xe4, 0x18, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "pfalse p15.b" + + - + input: + bytes: [ 0x0f, 0xe4, 0x18, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "pfalse p15.b" diff --git a/tests/MC/AArch64/SVE/pfirst.s.yaml b/tests/MC/AArch64/SVE/pfirst.s.yaml new file mode 100644 index 0000000000..478d7f65a0 --- /dev/null +++ b/tests/MC/AArch64/SVE/pfirst.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xc1, 0x58, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "pfirst p0.b, p15, p0.b" + + - + input: + bytes: [ 0xef, 0xc1, 0x58, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "pfirst p15.b, p15, p15.b" + + - + input: + bytes: [ 0xe0, 0xc1, 0x58, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "pfirst p0.b, p15, p0.b" + + - + input: + bytes: [ 0xef, 0xc1, 0x58, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "pfirst p15.b, p15, p15.b" diff --git a/tests/MC/AArch64/SVE/pnext.s.yaml b/tests/MC/AArch64/SVE/pnext.s.yaml new file mode 100644 index 0000000000..2375b46265 --- /dev/null +++ b/tests/MC/AArch64/SVE/pnext.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0xef, 0xc5, 0x19, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "pnext p15.b, p15, p15.b" + + - + input: + bytes: [ 0xe0, 0xc5, 0x19, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "pnext p0.b, p15, p0.b" + + - + input: + bytes: [ 0xe0, 0xc5, 0x59, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "pnext p0.h, p15, p0.h" + + - + input: + bytes: [ 0xe0, 0xc5, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "pnext p0.s, p15, p0.s" + + - + input: + bytes: [ 0xe0, 0xc5, 0xd9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "pnext p0.d, p15, p0.d" + + - + input: + bytes: [ 0xef, 0xc5, 0x19, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "pnext p15.b, p15, p15.b" + + - + input: + bytes: [ 0xe0, 0xc5, 0x19, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "pnext p0.b, p15, p0.b" + + - + input: + bytes: [ 0xe0, 0xc5, 0x59, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "pnext p0.h, p15, p0.h" + + - + input: + bytes: [ 0xe0, 0xc5, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "pnext p0.s, p15, p0.s" + + - + input: + bytes: [ 0xe0, 0xc5, 0xd9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "pnext p0.d, p15, p0.d" diff --git a/tests/MC/AArch64/SVE/predicate-as-counter-aliases.s.yaml b/tests/MC/AArch64/SVE/predicate-as-counter-aliases.s.yaml new file mode 100644 index 0000000000..182e38881e --- /dev/null +++ b/tests/MC/AArch64/SVE/predicate-as-counter-aliases.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x80, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldr p0, [x0]" + + - + input: + bytes: [ 0x45, 0x1d, 0x9f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ldr p5, [x10, #255, mul vl]" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "str p0, [x0]" + + - + input: + bytes: [ 0x45, 0x1d, 0x9f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "str p5, [x10, #255, mul vl]" + + - + input: + bytes: [ 0x00, 0x40, 0x80, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov p0.b, p0.b" + + - + input: + bytes: [ 0x0f, 0xe4, 0x18, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "pfalse p15.b" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr p0, [x0]" + + - + input: + bytes: [ 0x45, 0x1d, 0x9f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ldr p5, [x10, #255, mul vl]" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str p0, [x0]" + + - + input: + bytes: [ 0x45, 0x1d, 0x9f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str p5, [x10, #255, mul vl]" + + - + input: + bytes: [ 0x00, 0x40, 0x80, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov p0.b, p0.b" + + - + input: + bytes: [ 0x0f, 0xe4, 0x18, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "pfalse p15.b" diff --git a/tests/MC/AArch64/SVE/prfb-sve-only.s.yaml b/tests/MC/AArch64/SVE/prfb-sve-only.s.yaml new file mode 100644 index 0000000000..fbdd8bdce9 --- /dev/null +++ b/tests/MC/AArch64/SVE/prfb-sve-only.s.yaml @@ -0,0 +1,90 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x20, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl1keep, p0, [x0, z0.s, uxtw]" + + - + input: + bytes: [ 0x45, 0x15, 0x35, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl3strm, p5, [x10, z21.s, uxtw]" + + - + input: + bytes: [ 0x00, 0x00, 0x20, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl1keep, p0, [x0, z0.d, uxtw]" + + - + input: + bytes: [ 0x45, 0x15, 0x75, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl3strm, p5, [x10, z21.d, sxtw]" + + - + input: + bytes: [ 0x00, 0x80, 0x60, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl1keep, p0, [x0, z0.d]" + + - + input: + bytes: [ 0xa7, 0xed, 0x00, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb #7, p3, [z13.s]" + + - + input: + bytes: [ 0xa7, 0xed, 0x1f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb #7, p3, [z13.s, #31]" + + - + input: + bytes: [ 0x45, 0xf5, 0x00, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl3strm, p5, [z10.d]" + + - + input: + bytes: [ 0x45, 0xf5, 0x1f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl3strm, p5, [z10.d, #31]" diff --git a/tests/MC/AArch64/SVE/prfb.s.yaml b/tests/MC/AArch64/SVE/prfb.s.yaml new file mode 100644 index 0000000000..24537c907a --- /dev/null +++ b/tests/MC/AArch64/SVE/prfb.s.yaml @@ -0,0 +1,600 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl1keep, p0, [x0]" + + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl1keep, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl1strm, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl1strm, p0, [x0]" + + - + input: + bytes: [ 0x02, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl2keep, p0, [x0]" + + - + input: + bytes: [ 0x02, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl2keep, p0, [x0]" + + - + input: + bytes: [ 0x03, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl2strm, p0, [x0]" + + - + input: + bytes: [ 0x03, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl2strm, p0, [x0]" + + - + input: + bytes: [ 0x04, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl3keep, p0, [x0]" + + - + input: + bytes: [ 0x04, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl3keep, p0, [x0]" + + - + input: + bytes: [ 0x05, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl3strm, p0, [x0]" + + - + input: + bytes: [ 0x05, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl3strm, p0, [x0]" + + - + input: + bytes: [ 0x06, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb #6, p0, [x0]" + + - + input: + bytes: [ 0x07, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb #7, p0, [x0]" + + - + input: + bytes: [ 0x08, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pstl1keep, p0, [x0]" + + - + input: + bytes: [ 0x08, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pstl1keep, p0, [x0]" + + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pstl1strm, p0, [x0]" + + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pstl1strm, p0, [x0]" + + - + input: + bytes: [ 0x0a, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pstl2keep, p0, [x0]" + + - + input: + bytes: [ 0x0a, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pstl2keep, p0, [x0]" + + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pstl2strm, p0, [x0]" + + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pstl2strm, p0, [x0]" + + - + input: + bytes: [ 0x0c, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pstl3keep, p0, [x0]" + + - + input: + bytes: [ 0x0c, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pstl3keep, p0, [x0]" + + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pstl3strm, p0, [x0]" + + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pstl3strm, p0, [x0]" + + - + input: + bytes: [ 0x0e, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb #14, p0, [x0]" + + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb #15, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x00, 0xe0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl1strm, p0, [x0, #-32, mul vl]" + + - + input: + bytes: [ 0x01, 0x00, 0xdf, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfb pldl1strm, p0, [x0, #31, mul vl]" + + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pldl1keep, p0, [x0]" + + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pldl1keep, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pldl1strm, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pldl1strm, p0, [x0]" + + - + input: + bytes: [ 0x02, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pldl2keep, p0, [x0]" + + - + input: + bytes: [ 0x02, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pldl2keep, p0, [x0]" + + - + input: + bytes: [ 0x03, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pldl2strm, p0, [x0]" + + - + input: + bytes: [ 0x03, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pldl2strm, p0, [x0]" + + - + input: + bytes: [ 0x04, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pldl3keep, p0, [x0]" + + - + input: + bytes: [ 0x04, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pldl3keep, p0, [x0]" + + - + input: + bytes: [ 0x05, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pldl3strm, p0, [x0]" + + - + input: + bytes: [ 0x05, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pldl3strm, p0, [x0]" + + - + input: + bytes: [ 0x06, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb #6, p0, [x0]" + + - + input: + bytes: [ 0x07, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb #7, p0, [x0]" + + - + input: + bytes: [ 0x08, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pstl1keep, p0, [x0]" + + - + input: + bytes: [ 0x08, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pstl1keep, p0, [x0]" + + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pstl1strm, p0, [x0]" + + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pstl1strm, p0, [x0]" + + - + input: + bytes: [ 0x0a, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pstl2keep, p0, [x0]" + + - + input: + bytes: [ 0x0a, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pstl2keep, p0, [x0]" + + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pstl2strm, p0, [x0]" + + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pstl2strm, p0, [x0]" + + - + input: + bytes: [ 0x0c, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pstl3keep, p0, [x0]" + + - + input: + bytes: [ 0x0c, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pstl3keep, p0, [x0]" + + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pstl3strm, p0, [x0]" + + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pstl3strm, p0, [x0]" + + - + input: + bytes: [ 0x0e, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb #14, p0, [x0]" + + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb #15, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x00, 0xe0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pldl1strm, p0, [x0, #-32, mul vl]" + + - + input: + bytes: [ 0x01, 0x00, 0xdf, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfb pldl1strm, p0, [x0, #31, mul vl]" diff --git a/tests/MC/AArch64/SVE/prfd-sve-only.s.yaml b/tests/MC/AArch64/SVE/prfd-sve-only.s.yaml new file mode 100644 index 0000000000..a2a83b3efa --- /dev/null +++ b/tests/MC/AArch64/SVE/prfd-sve-only.s.yaml @@ -0,0 +1,90 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0x20, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pldl1keep, p0, [x0, z0.s, uxtw #3]" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pldl1keep, p0, [x0, z0.s, sxtw #3]" + + - + input: + bytes: [ 0x00, 0x60, 0x20, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pldl1keep, p0, [x0, z0.d, uxtw #3]" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pldl1keep, p0, [x0, z0.d, sxtw #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pldl1keep, p0, [x0, z0.d, lsl #3]" + + - + input: + bytes: [ 0xef, 0xff, 0x80, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd #15, p7, [z31.s]" + + - + input: + bytes: [ 0xef, 0xff, 0x9f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd #15, p7, [z31.s, #248]" + + - + input: + bytes: [ 0xef, 0xff, 0x80, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd #15, p7, [z31.d]" + + - + input: + bytes: [ 0xef, 0xff, 0x9f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd #15, p7, [z31.d, #248]" diff --git a/tests/MC/AArch64/SVE/prfd.s.yaml b/tests/MC/AArch64/SVE/prfd.s.yaml new file mode 100644 index 0000000000..c2b6bd3807 --- /dev/null +++ b/tests/MC/AArch64/SVE/prfd.s.yaml @@ -0,0 +1,600 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pldl1keep, p0, [x0]" + + - + input: + bytes: [ 0x00, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pldl1keep, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pldl1strm, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pldl1strm, p0, [x0]" + + - + input: + bytes: [ 0x02, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pldl2keep, p0, [x0]" + + - + input: + bytes: [ 0x02, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pldl2keep, p0, [x0]" + + - + input: + bytes: [ 0x03, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pldl2strm, p0, [x0]" + + - + input: + bytes: [ 0x03, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pldl2strm, p0, [x0]" + + - + input: + bytes: [ 0x04, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pldl3keep, p0, [x0]" + + - + input: + bytes: [ 0x04, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pldl3keep, p0, [x0]" + + - + input: + bytes: [ 0x05, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pldl3strm, p0, [x0]" + + - + input: + bytes: [ 0x05, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pldl3strm, p0, [x0]" + + - + input: + bytes: [ 0x06, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd #6, p0, [x0]" + + - + input: + bytes: [ 0x07, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd #7, p0, [x0]" + + - + input: + bytes: [ 0x08, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pstl1keep, p0, [x0]" + + - + input: + bytes: [ 0x08, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pstl1keep, p0, [x0]" + + - + input: + bytes: [ 0x09, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pstl1strm, p0, [x0]" + + - + input: + bytes: [ 0x09, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pstl1strm, p0, [x0]" + + - + input: + bytes: [ 0x0a, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pstl2keep, p0, [x0]" + + - + input: + bytes: [ 0x0a, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pstl2keep, p0, [x0]" + + - + input: + bytes: [ 0x0b, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pstl2strm, p0, [x0]" + + - + input: + bytes: [ 0x0b, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pstl2strm, p0, [x0]" + + - + input: + bytes: [ 0x0c, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pstl3keep, p0, [x0]" + + - + input: + bytes: [ 0x0c, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pstl3keep, p0, [x0]" + + - + input: + bytes: [ 0x0d, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pstl3strm, p0, [x0]" + + - + input: + bytes: [ 0x0d, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pstl3strm, p0, [x0]" + + - + input: + bytes: [ 0x0e, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd #14, p0, [x0]" + + - + input: + bytes: [ 0x0f, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd #15, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x60, 0xe0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pldl1strm, p0, [x0, #-32, mul vl]" + + - + input: + bytes: [ 0x01, 0x60, 0xdf, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfd pldl1strm, p0, [x0, #31, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pldl1keep, p0, [x0]" + + - + input: + bytes: [ 0x00, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pldl1keep, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pldl1strm, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pldl1strm, p0, [x0]" + + - + input: + bytes: [ 0x02, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pldl2keep, p0, [x0]" + + - + input: + bytes: [ 0x02, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pldl2keep, p0, [x0]" + + - + input: + bytes: [ 0x03, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pldl2strm, p0, [x0]" + + - + input: + bytes: [ 0x03, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pldl2strm, p0, [x0]" + + - + input: + bytes: [ 0x04, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pldl3keep, p0, [x0]" + + - + input: + bytes: [ 0x04, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pldl3keep, p0, [x0]" + + - + input: + bytes: [ 0x05, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pldl3strm, p0, [x0]" + + - + input: + bytes: [ 0x05, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pldl3strm, p0, [x0]" + + - + input: + bytes: [ 0x06, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd #6, p0, [x0]" + + - + input: + bytes: [ 0x07, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd #7, p0, [x0]" + + - + input: + bytes: [ 0x08, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pstl1keep, p0, [x0]" + + - + input: + bytes: [ 0x08, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pstl1keep, p0, [x0]" + + - + input: + bytes: [ 0x09, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pstl1strm, p0, [x0]" + + - + input: + bytes: [ 0x09, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pstl1strm, p0, [x0]" + + - + input: + bytes: [ 0x0a, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pstl2keep, p0, [x0]" + + - + input: + bytes: [ 0x0a, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pstl2keep, p0, [x0]" + + - + input: + bytes: [ 0x0b, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pstl2strm, p0, [x0]" + + - + input: + bytes: [ 0x0b, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pstl2strm, p0, [x0]" + + - + input: + bytes: [ 0x0c, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pstl3keep, p0, [x0]" + + - + input: + bytes: [ 0x0c, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pstl3keep, p0, [x0]" + + - + input: + bytes: [ 0x0d, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pstl3strm, p0, [x0]" + + - + input: + bytes: [ 0x0d, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pstl3strm, p0, [x0]" + + - + input: + bytes: [ 0x0e, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd #14, p0, [x0]" + + - + input: + bytes: [ 0x0f, 0x60, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd #15, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x60, 0xe0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pldl1strm, p0, [x0, #-32, mul vl]" + + - + input: + bytes: [ 0x01, 0x60, 0xdf, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfd pldl1strm, p0, [x0, #31, mul vl]" diff --git a/tests/MC/AArch64/SVE/prfh-sve-only.s.yaml b/tests/MC/AArch64/SVE/prfh-sve-only.s.yaml new file mode 100644 index 0000000000..cd28e685d5 --- /dev/null +++ b/tests/MC/AArch64/SVE/prfh-sve-only.s.yaml @@ -0,0 +1,90 @@ +test_cases: + - + input: + bytes: [ 0x45, 0x35, 0x35, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pldl3strm, p5, [x10, z21.s, uxtw #1]" + + - + input: + bytes: [ 0x45, 0x35, 0x75, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pldl3strm, p5, [x10, z21.s, sxtw #1]" + + - + input: + bytes: [ 0x45, 0x35, 0x35, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pldl3strm, p5, [x10, z21.d, uxtw #1]" + + - + input: + bytes: [ 0x45, 0x35, 0x75, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pldl3strm, p5, [x10, z21.d, sxtw #1]" + + - + input: + bytes: [ 0x00, 0xa0, 0x60, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pldl1keep, p0, [x0, z0.d, lsl #1]" + + - + input: + bytes: [ 0xef, 0xff, 0x80, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh #15, p7, [z31.s]" + + - + input: + bytes: [ 0xef, 0xff, 0x9f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh #15, p7, [z31.s, #62]" + + - + input: + bytes: [ 0xef, 0xff, 0x80, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh #15, p7, [z31.d]" + + - + input: + bytes: [ 0xef, 0xff, 0x9f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh #15, p7, [z31.d, #62]" diff --git a/tests/MC/AArch64/SVE/prfh.s.yaml b/tests/MC/AArch64/SVE/prfh.s.yaml new file mode 100644 index 0000000000..314fd18112 --- /dev/null +++ b/tests/MC/AArch64/SVE/prfh.s.yaml @@ -0,0 +1,600 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pldl1keep, p0, [x0]" + + - + input: + bytes: [ 0x00, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pldl1keep, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pldl1strm, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pldl1strm, p0, [x0]" + + - + input: + bytes: [ 0x02, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pldl2keep, p0, [x0]" + + - + input: + bytes: [ 0x02, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pldl2keep, p0, [x0]" + + - + input: + bytes: [ 0x03, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pldl2strm, p0, [x0]" + + - + input: + bytes: [ 0x03, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pldl2strm, p0, [x0]" + + - + input: + bytes: [ 0x04, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pldl3keep, p0, [x0]" + + - + input: + bytes: [ 0x04, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pldl3keep, p0, [x0]" + + - + input: + bytes: [ 0x05, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pldl3strm, p0, [x0]" + + - + input: + bytes: [ 0x05, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pldl3strm, p0, [x0]" + + - + input: + bytes: [ 0x06, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh #6, p0, [x0]" + + - + input: + bytes: [ 0x07, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh #7, p0, [x0]" + + - + input: + bytes: [ 0x08, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pstl1keep, p0, [x0]" + + - + input: + bytes: [ 0x08, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pstl1keep, p0, [x0]" + + - + input: + bytes: [ 0x09, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pstl1strm, p0, [x0]" + + - + input: + bytes: [ 0x09, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pstl1strm, p0, [x0]" + + - + input: + bytes: [ 0x0a, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pstl2keep, p0, [x0]" + + - + input: + bytes: [ 0x0a, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pstl2keep, p0, [x0]" + + - + input: + bytes: [ 0x0b, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pstl2strm, p0, [x0]" + + - + input: + bytes: [ 0x0b, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pstl2strm, p0, [x0]" + + - + input: + bytes: [ 0x0c, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pstl3keep, p0, [x0]" + + - + input: + bytes: [ 0x0c, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pstl3keep, p0, [x0]" + + - + input: + bytes: [ 0x0d, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pstl3strm, p0, [x0]" + + - + input: + bytes: [ 0x0d, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pstl3strm, p0, [x0]" + + - + input: + bytes: [ 0x0e, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh #14, p0, [x0]" + + - + input: + bytes: [ 0x0f, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh #15, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x20, 0xe0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pldl1strm, p0, [x0, #-32, mul vl]" + + - + input: + bytes: [ 0x01, 0x20, 0xdf, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfh pldl1strm, p0, [x0, #31, mul vl]" + + - + input: + bytes: [ 0x00, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pldl1keep, p0, [x0]" + + - + input: + bytes: [ 0x00, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pldl1keep, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pldl1strm, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pldl1strm, p0, [x0]" + + - + input: + bytes: [ 0x02, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pldl2keep, p0, [x0]" + + - + input: + bytes: [ 0x02, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pldl2keep, p0, [x0]" + + - + input: + bytes: [ 0x03, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pldl2strm, p0, [x0]" + + - + input: + bytes: [ 0x03, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pldl2strm, p0, [x0]" + + - + input: + bytes: [ 0x04, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pldl3keep, p0, [x0]" + + - + input: + bytes: [ 0x04, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pldl3keep, p0, [x0]" + + - + input: + bytes: [ 0x05, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pldl3strm, p0, [x0]" + + - + input: + bytes: [ 0x05, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pldl3strm, p0, [x0]" + + - + input: + bytes: [ 0x06, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh #6, p0, [x0]" + + - + input: + bytes: [ 0x07, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh #7, p0, [x0]" + + - + input: + bytes: [ 0x08, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pstl1keep, p0, [x0]" + + - + input: + bytes: [ 0x08, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pstl1keep, p0, [x0]" + + - + input: + bytes: [ 0x09, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pstl1strm, p0, [x0]" + + - + input: + bytes: [ 0x09, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pstl1strm, p0, [x0]" + + - + input: + bytes: [ 0x0a, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pstl2keep, p0, [x0]" + + - + input: + bytes: [ 0x0a, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pstl2keep, p0, [x0]" + + - + input: + bytes: [ 0x0b, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pstl2strm, p0, [x0]" + + - + input: + bytes: [ 0x0b, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pstl2strm, p0, [x0]" + + - + input: + bytes: [ 0x0c, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pstl3keep, p0, [x0]" + + - + input: + bytes: [ 0x0c, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pstl3keep, p0, [x0]" + + - + input: + bytes: [ 0x0d, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pstl3strm, p0, [x0]" + + - + input: + bytes: [ 0x0d, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pstl3strm, p0, [x0]" + + - + input: + bytes: [ 0x0e, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh #14, p0, [x0]" + + - + input: + bytes: [ 0x0f, 0x20, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh #15, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x20, 0xe0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pldl1strm, p0, [x0, #-32, mul vl]" + + - + input: + bytes: [ 0x01, 0x20, 0xdf, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfh pldl1strm, p0, [x0, #31, mul vl]" diff --git a/tests/MC/AArch64/SVE/prfw-sve-only.s.yaml b/tests/MC/AArch64/SVE/prfw-sve-only.s.yaml new file mode 100644 index 0000000000..f8fa7a5d48 --- /dev/null +++ b/tests/MC/AArch64/SVE/prfw-sve-only.s.yaml @@ -0,0 +1,90 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0x20, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pldl1keep, p0, [x0, z0.s, uxtw #2]" + + - + input: + bytes: [ 0x45, 0x55, 0x75, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pldl3strm, p5, [x10, z21.s, sxtw #2]" + + - + input: + bytes: [ 0xa7, 0x4d, 0x28, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw #7, p3, [x13, z8.d, uxtw #2]" + + - + input: + bytes: [ 0x00, 0x40, 0x60, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pldl1keep, p0, [x0, z0.d, sxtw #2]" + + - + input: + bytes: [ 0x45, 0xd5, 0x75, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pldl3strm, p5, [x10, z21.d, lsl #2]" + + - + input: + bytes: [ 0xef, 0xff, 0x00, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw #15, p7, [z31.s]" + + - + input: + bytes: [ 0xef, 0xff, 0x1f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw #15, p7, [z31.s, #124]" + + - + input: + bytes: [ 0xef, 0xff, 0x00, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw #15, p7, [z31.d]" + + - + input: + bytes: [ 0xef, 0xff, 0x1f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw #15, p7, [z31.d, #124]" diff --git a/tests/MC/AArch64/SVE/prfw.s.yaml b/tests/MC/AArch64/SVE/prfw.s.yaml new file mode 100644 index 0000000000..5fafbf1c37 --- /dev/null +++ b/tests/MC/AArch64/SVE/prfw.s.yaml @@ -0,0 +1,600 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pldl1keep, p0, [x0]" + + - + input: + bytes: [ 0x00, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pldl1keep, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pldl1strm, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pldl1strm, p0, [x0]" + + - + input: + bytes: [ 0x02, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pldl2keep, p0, [x0]" + + - + input: + bytes: [ 0x02, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pldl2keep, p0, [x0]" + + - + input: + bytes: [ 0x03, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pldl2strm, p0, [x0]" + + - + input: + bytes: [ 0x03, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pldl2strm, p0, [x0]" + + - + input: + bytes: [ 0x04, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pldl3keep, p0, [x0]" + + - + input: + bytes: [ 0x04, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pldl3keep, p0, [x0]" + + - + input: + bytes: [ 0x05, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pldl3strm, p0, [x0]" + + - + input: + bytes: [ 0x05, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pldl3strm, p0, [x0]" + + - + input: + bytes: [ 0x06, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw #6, p0, [x0]" + + - + input: + bytes: [ 0x07, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw #7, p0, [x0]" + + - + input: + bytes: [ 0x08, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pstl1keep, p0, [x0]" + + - + input: + bytes: [ 0x08, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pstl1keep, p0, [x0]" + + - + input: + bytes: [ 0x09, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pstl1strm, p0, [x0]" + + - + input: + bytes: [ 0x09, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pstl1strm, p0, [x0]" + + - + input: + bytes: [ 0x0a, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pstl2keep, p0, [x0]" + + - + input: + bytes: [ 0x0a, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pstl2keep, p0, [x0]" + + - + input: + bytes: [ 0x0b, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pstl2strm, p0, [x0]" + + - + input: + bytes: [ 0x0b, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pstl2strm, p0, [x0]" + + - + input: + bytes: [ 0x0c, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pstl3keep, p0, [x0]" + + - + input: + bytes: [ 0x0c, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pstl3keep, p0, [x0]" + + - + input: + bytes: [ 0x0d, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pstl3strm, p0, [x0]" + + - + input: + bytes: [ 0x0d, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pstl3strm, p0, [x0]" + + - + input: + bytes: [ 0x0e, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw #14, p0, [x0]" + + - + input: + bytes: [ 0x0f, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw #15, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x40, 0xe0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pldl1strm, p0, [x0, #-32, mul vl]" + + - + input: + bytes: [ 0x01, 0x40, 0xdf, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "prfw pldl1strm, p0, [x0, #31, mul vl]" + + - + input: + bytes: [ 0x00, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pldl1keep, p0, [x0]" + + - + input: + bytes: [ 0x00, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pldl1keep, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pldl1strm, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pldl1strm, p0, [x0]" + + - + input: + bytes: [ 0x02, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pldl2keep, p0, [x0]" + + - + input: + bytes: [ 0x02, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pldl2keep, p0, [x0]" + + - + input: + bytes: [ 0x03, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pldl2strm, p0, [x0]" + + - + input: + bytes: [ 0x03, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pldl2strm, p0, [x0]" + + - + input: + bytes: [ 0x04, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pldl3keep, p0, [x0]" + + - + input: + bytes: [ 0x04, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pldl3keep, p0, [x0]" + + - + input: + bytes: [ 0x05, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pldl3strm, p0, [x0]" + + - + input: + bytes: [ 0x05, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pldl3strm, p0, [x0]" + + - + input: + bytes: [ 0x06, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw #6, p0, [x0]" + + - + input: + bytes: [ 0x07, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw #7, p0, [x0]" + + - + input: + bytes: [ 0x08, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pstl1keep, p0, [x0]" + + - + input: + bytes: [ 0x08, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pstl1keep, p0, [x0]" + + - + input: + bytes: [ 0x09, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pstl1strm, p0, [x0]" + + - + input: + bytes: [ 0x09, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pstl1strm, p0, [x0]" + + - + input: + bytes: [ 0x0a, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pstl2keep, p0, [x0]" + + - + input: + bytes: [ 0x0a, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pstl2keep, p0, [x0]" + + - + input: + bytes: [ 0x0b, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pstl2strm, p0, [x0]" + + - + input: + bytes: [ 0x0b, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pstl2strm, p0, [x0]" + + - + input: + bytes: [ 0x0c, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pstl3keep, p0, [x0]" + + - + input: + bytes: [ 0x0c, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pstl3keep, p0, [x0]" + + - + input: + bytes: [ 0x0d, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pstl3strm, p0, [x0]" + + - + input: + bytes: [ 0x0d, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pstl3strm, p0, [x0]" + + - + input: + bytes: [ 0x0e, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw #14, p0, [x0]" + + - + input: + bytes: [ 0x0f, 0x40, 0xc0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw #15, p0, [x0]" + + - + input: + bytes: [ 0x01, 0x40, 0xe0, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pldl1strm, p0, [x0, #-32, mul vl]" + + - + input: + bytes: [ 0x01, 0x40, 0xdf, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "prfw pldl1strm, p0, [x0, #31, mul vl]" diff --git a/tests/MC/AArch64/SVE/ptest.s.yaml b/tests/MC/AArch64/SVE/ptest.s.yaml new file mode 100644 index 0000000000..e866915e95 --- /dev/null +++ b/tests/MC/AArch64/SVE/ptest.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xfc, 0x50, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptest p15, p0.b" + + - + input: + bytes: [ 0xe0, 0xfd, 0x50, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptest p15, p15.b" + + - + input: + bytes: [ 0x00, 0xfc, 0x50, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptest p15, p0.b" + + - + input: + bytes: [ 0xe0, 0xfd, 0x50, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptest p15, p15.b" diff --git a/tests/MC/AArch64/SVE/ptrue.s.yaml b/tests/MC/AArch64/SVE/ptrue.s.yaml new file mode 100644 index 0000000000..ba23ba760f --- /dev/null +++ b/tests/MC/AArch64/SVE/ptrue.s.yaml @@ -0,0 +1,800 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x18, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p0.b, pow2" + + - + input: + bytes: [ 0x00, 0xe0, 0x58, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p0.h, pow2" + + - + input: + bytes: [ 0x00, 0xe0, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p0.s, pow2" + + - + input: + bytes: [ 0x00, 0xe0, 0xd8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p0.d, pow2" + + - + input: + bytes: [ 0xef, 0xe3, 0x18, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p15.b" + + - + input: + bytes: [ 0xef, 0xe3, 0x58, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p15.h" + + - + input: + bytes: [ 0xef, 0xe3, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p15.s" + + - + input: + bytes: [ 0xef, 0xe3, 0xd8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p15.d" + + - + input: + bytes: [ 0x27, 0xe0, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl1" + + - + input: + bytes: [ 0x27, 0xe0, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl1" + + - + input: + bytes: [ 0x47, 0xe0, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl2" + + - + input: + bytes: [ 0x67, 0xe0, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl3" + + - + input: + bytes: [ 0x87, 0xe0, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl4" + + - + input: + bytes: [ 0xa7, 0xe0, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl5" + + - + input: + bytes: [ 0xc7, 0xe0, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl6" + + - + input: + bytes: [ 0xe7, 0xe0, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl7" + + - + input: + bytes: [ 0x07, 0xe1, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl8" + + - + input: + bytes: [ 0x27, 0xe1, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl16" + + - + input: + bytes: [ 0x47, 0xe1, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl32" + + - + input: + bytes: [ 0x67, 0xe1, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl64" + + - + input: + bytes: [ 0x87, 0xe1, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl128" + + - + input: + bytes: [ 0xa7, 0xe1, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl256" + + - + input: + bytes: [ 0xa7, 0xe3, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, mul4" + + - + input: + bytes: [ 0xc7, 0xe3, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, mul3" + + - + input: + bytes: [ 0xe7, 0xe3, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s" + + - + input: + bytes: [ 0xc7, 0xe1, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #14" + + - + input: + bytes: [ 0xe7, 0xe1, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #15" + + - + input: + bytes: [ 0x07, 0xe2, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #16" + + - + input: + bytes: [ 0x27, 0xe2, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #17" + + - + input: + bytes: [ 0x47, 0xe2, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #18" + + - + input: + bytes: [ 0x67, 0xe2, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #19" + + - + input: + bytes: [ 0x87, 0xe2, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #20" + + - + input: + bytes: [ 0xa7, 0xe2, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #21" + + - + input: + bytes: [ 0xc7, 0xe2, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #22" + + - + input: + bytes: [ 0xe7, 0xe2, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #23" + + - + input: + bytes: [ 0x07, 0xe3, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #24" + + - + input: + bytes: [ 0x27, 0xe3, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #25" + + - + input: + bytes: [ 0x47, 0xe3, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #26" + + - + input: + bytes: [ 0x67, 0xe3, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #27" + + - + input: + bytes: [ 0x87, 0xe3, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #28" + + - + input: + bytes: [ 0x00, 0xe0, 0x18, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p0.b, pow2" + + - + input: + bytes: [ 0x00, 0xe0, 0x58, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p0.h, pow2" + + - + input: + bytes: [ 0x00, 0xe0, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p0.s, pow2" + + - + input: + bytes: [ 0x00, 0xe0, 0xd8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p0.d, pow2" + + - + input: + bytes: [ 0xef, 0xe3, 0x18, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p15.b" + + - + input: + bytes: [ 0xef, 0xe3, 0x58, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p15.h" + + - + input: + bytes: [ 0xef, 0xe3, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p15.s" + + - + input: + bytes: [ 0xef, 0xe3, 0xd8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p15.d" + + - + input: + bytes: [ 0x27, 0xe0, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl1" + + - + input: + bytes: [ 0x27, 0xe0, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl1" + + - + input: + bytes: [ 0x47, 0xe0, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl2" + + - + input: + bytes: [ 0x67, 0xe0, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl3" + + - + input: + bytes: [ 0x87, 0xe0, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl4" + + - + input: + bytes: [ 0xa7, 0xe0, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl5" + + - + input: + bytes: [ 0xc7, 0xe0, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl6" + + - + input: + bytes: [ 0xe7, 0xe0, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl7" + + - + input: + bytes: [ 0x07, 0xe1, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl8" + + - + input: + bytes: [ 0x27, 0xe1, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl16" + + - + input: + bytes: [ 0x47, 0xe1, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl32" + + - + input: + bytes: [ 0x67, 0xe1, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl64" + + - + input: + bytes: [ 0x87, 0xe1, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl128" + + - + input: + bytes: [ 0xa7, 0xe1, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, vl256" + + - + input: + bytes: [ 0xa7, 0xe3, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, mul4" + + - + input: + bytes: [ 0xc7, 0xe3, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, mul3" + + - + input: + bytes: [ 0xe7, 0xe3, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s" + + - + input: + bytes: [ 0xc7, 0xe1, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #14" + + - + input: + bytes: [ 0xe7, 0xe1, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #15" + + - + input: + bytes: [ 0x07, 0xe2, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #16" + + - + input: + bytes: [ 0x27, 0xe2, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #17" + + - + input: + bytes: [ 0x47, 0xe2, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #18" + + - + input: + bytes: [ 0x67, 0xe2, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #19" + + - + input: + bytes: [ 0x87, 0xe2, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #20" + + - + input: + bytes: [ 0xa7, 0xe2, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #21" + + - + input: + bytes: [ 0xc7, 0xe2, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #22" + + - + input: + bytes: [ 0xe7, 0xe2, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #23" + + - + input: + bytes: [ 0x07, 0xe3, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #24" + + - + input: + bytes: [ 0x27, 0xe3, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #25" + + - + input: + bytes: [ 0x47, 0xe3, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #26" + + - + input: + bytes: [ 0x67, 0xe3, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #27" + + - + input: + bytes: [ 0x87, 0xe3, 0x98, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrue p7.s, #28" diff --git a/tests/MC/AArch64/SVE/ptrues.s.yaml b/tests/MC/AArch64/SVE/ptrues.s.yaml new file mode 100644 index 0000000000..13583c8c49 --- /dev/null +++ b/tests/MC/AArch64/SVE/ptrues.s.yaml @@ -0,0 +1,800 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x19, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p0.b, pow2" + + - + input: + bytes: [ 0x00, 0xe0, 0x59, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p0.h, pow2" + + - + input: + bytes: [ 0x00, 0xe0, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p0.s, pow2" + + - + input: + bytes: [ 0x00, 0xe0, 0xd9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p0.d, pow2" + + - + input: + bytes: [ 0xef, 0xe3, 0x19, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p15.b" + + - + input: + bytes: [ 0xef, 0xe3, 0x59, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p15.h" + + - + input: + bytes: [ 0xef, 0xe3, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p15.s" + + - + input: + bytes: [ 0xef, 0xe3, 0xd9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p15.d" + + - + input: + bytes: [ 0x27, 0xe0, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl1" + + - + input: + bytes: [ 0x27, 0xe0, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl1" + + - + input: + bytes: [ 0x47, 0xe0, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl2" + + - + input: + bytes: [ 0x67, 0xe0, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl3" + + - + input: + bytes: [ 0x87, 0xe0, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl4" + + - + input: + bytes: [ 0xa7, 0xe0, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl5" + + - + input: + bytes: [ 0xc7, 0xe0, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl6" + + - + input: + bytes: [ 0xe7, 0xe0, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl7" + + - + input: + bytes: [ 0x07, 0xe1, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl8" + + - + input: + bytes: [ 0x27, 0xe1, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl16" + + - + input: + bytes: [ 0x47, 0xe1, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl32" + + - + input: + bytes: [ 0x67, 0xe1, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl64" + + - + input: + bytes: [ 0x87, 0xe1, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl128" + + - + input: + bytes: [ 0xa7, 0xe1, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl256" + + - + input: + bytes: [ 0xa7, 0xe3, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, mul4" + + - + input: + bytes: [ 0xc7, 0xe3, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, mul3" + + - + input: + bytes: [ 0xe7, 0xe3, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s" + + - + input: + bytes: [ 0xc7, 0xe1, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #14" + + - + input: + bytes: [ 0xe7, 0xe1, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #15" + + - + input: + bytes: [ 0x07, 0xe2, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #16" + + - + input: + bytes: [ 0x27, 0xe2, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #17" + + - + input: + bytes: [ 0x47, 0xe2, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #18" + + - + input: + bytes: [ 0x67, 0xe2, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #19" + + - + input: + bytes: [ 0x87, 0xe2, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #20" + + - + input: + bytes: [ 0xa7, 0xe2, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #21" + + - + input: + bytes: [ 0xc7, 0xe2, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #22" + + - + input: + bytes: [ 0xe7, 0xe2, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #23" + + - + input: + bytes: [ 0x07, 0xe3, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #24" + + - + input: + bytes: [ 0x27, 0xe3, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #25" + + - + input: + bytes: [ 0x47, 0xe3, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #26" + + - + input: + bytes: [ 0x67, 0xe3, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #27" + + - + input: + bytes: [ 0x87, 0xe3, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #28" + + - + input: + bytes: [ 0x00, 0xe0, 0x19, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p0.b, pow2" + + - + input: + bytes: [ 0x00, 0xe0, 0x59, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p0.h, pow2" + + - + input: + bytes: [ 0x00, 0xe0, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p0.s, pow2" + + - + input: + bytes: [ 0x00, 0xe0, 0xd9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p0.d, pow2" + + - + input: + bytes: [ 0xef, 0xe3, 0x19, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p15.b" + + - + input: + bytes: [ 0xef, 0xe3, 0x59, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p15.h" + + - + input: + bytes: [ 0xef, 0xe3, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p15.s" + + - + input: + bytes: [ 0xef, 0xe3, 0xd9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p15.d" + + - + input: + bytes: [ 0x27, 0xe0, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl1" + + - + input: + bytes: [ 0x27, 0xe0, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl1" + + - + input: + bytes: [ 0x47, 0xe0, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl2" + + - + input: + bytes: [ 0x67, 0xe0, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl3" + + - + input: + bytes: [ 0x87, 0xe0, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl4" + + - + input: + bytes: [ 0xa7, 0xe0, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl5" + + - + input: + bytes: [ 0xc7, 0xe0, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl6" + + - + input: + bytes: [ 0xe7, 0xe0, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl7" + + - + input: + bytes: [ 0x07, 0xe1, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl8" + + - + input: + bytes: [ 0x27, 0xe1, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl16" + + - + input: + bytes: [ 0x47, 0xe1, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl32" + + - + input: + bytes: [ 0x67, 0xe1, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl64" + + - + input: + bytes: [ 0x87, 0xe1, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl128" + + - + input: + bytes: [ 0xa7, 0xe1, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, vl256" + + - + input: + bytes: [ 0xa7, 0xe3, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, mul4" + + - + input: + bytes: [ 0xc7, 0xe3, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, mul3" + + - + input: + bytes: [ 0xe7, 0xe3, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s" + + - + input: + bytes: [ 0xc7, 0xe1, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #14" + + - + input: + bytes: [ 0xe7, 0xe1, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #15" + + - + input: + bytes: [ 0x07, 0xe2, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #16" + + - + input: + bytes: [ 0x27, 0xe2, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #17" + + - + input: + bytes: [ 0x47, 0xe2, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #18" + + - + input: + bytes: [ 0x67, 0xe2, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #19" + + - + input: + bytes: [ 0x87, 0xe2, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #20" + + - + input: + bytes: [ 0xa7, 0xe2, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #21" + + - + input: + bytes: [ 0xc7, 0xe2, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #22" + + - + input: + bytes: [ 0xe7, 0xe2, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #23" + + - + input: + bytes: [ 0x07, 0xe3, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #24" + + - + input: + bytes: [ 0x27, 0xe3, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #25" + + - + input: + bytes: [ 0x47, 0xe3, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #26" + + - + input: + bytes: [ 0x67, 0xe3, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #27" + + - + input: + bytes: [ 0x87, 0xe3, 0x99, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ptrues p7.s, #28" diff --git a/tests/MC/AArch64/SVE/punpkhi.s.yaml b/tests/MC/AArch64/SVE/punpkhi.s.yaml new file mode 100644 index 0000000000..a36338b2ce --- /dev/null +++ b/tests/MC/AArch64/SVE/punpkhi.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0x31, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "punpkhi p0.h, p0.b" + + - + input: + bytes: [ 0xef, 0x41, 0x31, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "punpkhi p15.h, p15.b" + + - + input: + bytes: [ 0x00, 0x40, 0x31, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "punpkhi p0.h, p0.b" + + - + input: + bytes: [ 0xef, 0x41, 0x31, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "punpkhi p15.h, p15.b" diff --git a/tests/MC/AArch64/SVE/punpklo.s.yaml b/tests/MC/AArch64/SVE/punpklo.s.yaml new file mode 100644 index 0000000000..57d2c99f5f --- /dev/null +++ b/tests/MC/AArch64/SVE/punpklo.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0x30, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "punpklo p0.h, p0.b" + + - + input: + bytes: [ 0xef, 0x41, 0x30, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "punpklo p15.h, p15.b" + + - + input: + bytes: [ 0x00, 0x40, 0x30, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "punpklo p0.h, p0.b" + + - + input: + bytes: [ 0xef, 0x41, 0x30, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "punpklo p15.h, p15.b" diff --git a/tests/MC/AArch64/SVE/rbit.s.yaml b/tests/MC/AArch64/SVE/rbit.s.yaml new file mode 100644 index 0000000000..3f89961150 --- /dev/null +++ b/tests/MC/AArch64/SVE/rbit.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x9f, 0x27, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rbit z0.b, p7/m, z31.b" + + - + input: + bytes: [ 0xe0, 0x9f, 0x67, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rbit z0.h, p7/m, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0xa7, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rbit z0.s, p7/m, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe7, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rbit z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe7, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rbit z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe7, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rbit z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0x27, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rbit z0.b, p7/m, z31.b" + + - + input: + bytes: [ 0xe0, 0x9f, 0x67, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rbit z0.h, p7/m, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0xa7, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rbit z0.s, p7/m, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe7, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rbit z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe7, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rbit z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe7, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rbit z0.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/rdffr.s.yaml b/tests/MC/AArch64/SVE/rdffr.s.yaml new file mode 100644 index 0000000000..9493ff7060 --- /dev/null +++ b/tests/MC/AArch64/SVE/rdffr.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xf0, 0x19, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rdffr p0.b" + + - + input: + bytes: [ 0x0f, 0xf0, 0x19, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rdffr p15.b" + + - + input: + bytes: [ 0x00, 0xf0, 0x18, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rdffr p0.b, p0/z" + + - + input: + bytes: [ 0xef, 0xf1, 0x18, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rdffr p15.b, p15/z" diff --git a/tests/MC/AArch64/SVE/rdffrs.s.yaml b/tests/MC/AArch64/SVE/rdffrs.s.yaml new file mode 100644 index 0000000000..13a0705f3f --- /dev/null +++ b/tests/MC/AArch64/SVE/rdffrs.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xf0, 0x58, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rdffrs p0.b, p0/z" + + - + input: + bytes: [ 0xef, 0xf1, 0x58, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rdffrs p15.b, p15/z" diff --git a/tests/MC/AArch64/SVE/rdvl.s.yaml b/tests/MC/AArch64/SVE/rdvl.s.yaml new file mode 100644 index 0000000000..770fd096ea --- /dev/null +++ b/tests/MC/AArch64/SVE/rdvl.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x50, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rdvl x0, #0" + + - + input: + bytes: [ 0xff, 0x57, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rdvl xzr, #-1" + + - + input: + bytes: [ 0xf7, 0x53, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rdvl x23, #31" + + - + input: + bytes: [ 0x15, 0x54, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rdvl x21, #-32" + + - + input: + bytes: [ 0x00, 0x50, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rdvl x0, #0" + + - + input: + bytes: [ 0xff, 0x57, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rdvl xzr, #-1" + + - + input: + bytes: [ 0xf7, 0x53, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rdvl x23, #31" + + - + input: + bytes: [ 0x15, 0x54, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rdvl x21, #-32" diff --git a/tests/MC/AArch64/SVE/rev.s.yaml b/tests/MC/AArch64/SVE/rev.s.yaml new file mode 100644 index 0000000000..b1ec86e6b4 --- /dev/null +++ b/tests/MC/AArch64/SVE/rev.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x3b, 0x38, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rev z0.b, z31.b" + + - + input: + bytes: [ 0xe0, 0x3b, 0x78, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rev z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x3b, 0xb8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rev z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x3b, 0xf8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "rev z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3b, 0x38, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rev z0.b, z31.b" + + - + input: + bytes: [ 0xe0, 0x3b, 0x78, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rev z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x3b, 0xb8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rev z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x3b, 0xf8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rev z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/revb.s.yaml b/tests/MC/AArch64/SVE/revb.s.yaml new file mode 100644 index 0000000000..94749e2011 --- /dev/null +++ b/tests/MC/AArch64/SVE/revb.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x9f, 0x64, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "revb z0.h, p7/m, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0xa4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "revb z0.s, p7/m, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "revb z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "revb z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "revb z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0x64, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "revb z0.h, p7/m, z31.h" + + - + input: + bytes: [ 0xe0, 0x9f, 0xa4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "revb z0.s, p7/m, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "revb z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "revb z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe4, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "revb z0.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/revh.s.yaml b/tests/MC/AArch64/SVE/revh.s.yaml new file mode 100644 index 0000000000..e1798344f9 --- /dev/null +++ b/tests/MC/AArch64/SVE/revh.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x9f, 0xa5, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "revh z0.s, p7/m, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe5, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "revh z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe5, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "revh z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe5, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "revh z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xa5, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "revh z0.s, p7/m, z31.s" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe5, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "revh z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe5, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "revh z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe5, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "revh z0.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/revw.s.yaml b/tests/MC/AArch64/SVE/revw.s.yaml new file mode 100644 index 0000000000..751fa634c9 --- /dev/null +++ b/tests/MC/AArch64/SVE/revw.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x9f, 0xe6, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "revw z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe6, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "revw z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe6, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "revw z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe6, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "revw z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe6, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "revw z0.d, p7/m, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x9f, 0xe6, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "revw z0.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/sabd.s.yaml b/tests/MC/AArch64/SVE/sabd.s.yaml new file mode 100644 index 0000000000..f740066452 --- /dev/null +++ b/tests/MC/AArch64/SVE/sabd.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x1f, 0x0c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sabd z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x1f, 0x4c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sabd z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x8c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sabd z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0xcc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sabd z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x1f, 0xcc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sabd z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0xcc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sabd z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xff, 0x1f, 0x0c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabd z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x1f, 0x4c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabd z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x8c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabd z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0xcc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabd z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x1f, 0xcc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabd z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0xcc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabd z4.d, p7/m, z4.d, z31.d" diff --git a/tests/MC/AArch64/SVE/saddv.s.yaml b/tests/MC/AArch64/SVE/saddv.s.yaml new file mode 100644 index 0000000000..43d64e9a09 --- /dev/null +++ b/tests/MC/AArch64/SVE/saddv.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x3f, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "saddv d0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x40, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "saddv d0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x80, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "saddv d0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0x00, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saddv d0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x40, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saddv d0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x80, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saddv d0, p7, z31.s" diff --git a/tests/MC/AArch64/SVE/scvtf.s.yaml b/tests/MC/AArch64/SVE/scvtf.s.yaml new file mode 100644 index 0000000000..5f2bc2b2a4 --- /dev/null +++ b/tests/MC/AArch64/SVE/scvtf.s.yaml @@ -0,0 +1,220 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x52, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "scvtf z0.h, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x54, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "scvtf z0.h, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0x56, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "scvtf z0.h, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x94, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "scvtf z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd4, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "scvtf z0.s, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0xd0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "scvtf z0.d, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "scvtf z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0xa0, 0xd6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "scvtf z5.d, p0/m, z0.d" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0xa0, 0xd6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "scvtf z5.d, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x52, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "scvtf z0.h, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x54, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "scvtf z0.h, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0x56, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "scvtf z0.h, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x94, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "scvtf z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd4, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "scvtf z0.s, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0xd0, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "scvtf z0.d, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "scvtf z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0xa0, 0xd6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "scvtf z5.d, p0/m, z0.d" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0xa0, 0xd6, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "scvtf z5.d, p0/m, z0.d" diff --git a/tests/MC/AArch64/SVE/sdiv.s.yaml b/tests/MC/AArch64/SVE/sdiv.s.yaml new file mode 100644 index 0000000000..9132d639a5 --- /dev/null +++ b/tests/MC/AArch64/SVE/sdiv.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x1f, 0x94, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sdiv z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sdiv z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sdiv z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sdiv z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0x94, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sdiv z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sdiv z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sdiv z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sdiv z0.d, p7/m, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/sdivr.s.yaml b/tests/MC/AArch64/SVE/sdivr.s.yaml new file mode 100644 index 0000000000..848cecc8c7 --- /dev/null +++ b/tests/MC/AArch64/SVE/sdivr.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x1f, 0x96, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sdivr z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sdivr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sdivr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sdivr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0x96, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sdivr z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sdivr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sdivr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sdivr z0.d, p7/m, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/sdot.s.yaml b/tests/MC/AArch64/SVE/sdot.s.yaml new file mode 100644 index 0000000000..b9f0659164 --- /dev/null +++ b/tests/MC/AArch64/SVE/sdot.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x00, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sdot z0.s, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x00, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sdot z0.d, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x00, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sdot z0.s, z1.b, z7.b[3]" + + - + input: + bytes: [ 0x20, 0x00, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sdot z0.d, z1.h, z15.h[1]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x00, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sdot z0.d, z1.h, z31.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x00, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sdot z0.d, z1.h, z15.h[1]" + + - + input: + bytes: [ 0x20, 0x00, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sdot z0.s, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x00, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sdot z0.d, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x00, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sdot z0.s, z1.b, z7.b[3]" + + - + input: + bytes: [ 0x20, 0x00, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sdot z0.d, z1.h, z15.h[1]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x00, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sdot z0.d, z1.h, z31.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x00, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sdot z0.d, z1.h, z15.h[1]" diff --git a/tests/MC/AArch64/SVE/sel.s.yaml b/tests/MC/AArch64/SVE/sel.s.yaml new file mode 100644 index 0000000000..9dd075e269 --- /dev/null +++ b/tests/MC/AArch64/SVE/sel.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x42, 0x00, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov p0.b, p0/m, p0.b" + + - + input: + bytes: [ 0xff, 0x7f, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov p15.b, p15/m, p15.b" + + - + input: + bytes: [ 0xff, 0xff, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.b, p15/m, z31.b" + + - + input: + bytes: [ 0xff, 0xff, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.h, p15/m, z31.h" + + - + input: + bytes: [ 0xff, 0xff, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.s, p15/m, z31.s" + + - + input: + bytes: [ 0xff, 0xff, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mov z31.d, p15/m, z31.d" + + - + input: + bytes: [ 0xb7, 0xed, 0xa8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sel z23.s, p11, z13.s, z8.s" + + - + input: + bytes: [ 0xb7, 0xed, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sel z23.d, p11, z13.d, z8.d" + + - + input: + bytes: [ 0xb7, 0xed, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sel z23.h, p11, z13.h, z8.h" + + - + input: + bytes: [ 0xb7, 0xed, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sel z23.b, p11, z13.b, z8.b" + + - + input: + bytes: [ 0x10, 0x42, 0x00, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov p0.b, p0/m, p0.b" + + - + input: + bytes: [ 0xff, 0x7f, 0x0f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov p15.b, p15/m, p15.b" + + - + input: + bytes: [ 0xff, 0xff, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.b, p15/m, z31.b" + + - + input: + bytes: [ 0xff, 0xff, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.h, p15/m, z31.h" + + - + input: + bytes: [ 0xff, 0xff, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.s, p15/m, z31.s" + + - + input: + bytes: [ 0xff, 0xff, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mov z31.d, p15/m, z31.d" + + - + input: + bytes: [ 0xb7, 0xed, 0xa8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sel z23.s, p11, z13.s, z8.s" + + - + input: + bytes: [ 0xb7, 0xed, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sel z23.d, p11, z13.d, z8.d" + + - + input: + bytes: [ 0xb7, 0xed, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sel z23.h, p11, z13.h, z8.h" + + - + input: + bytes: [ 0xb7, 0xed, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sel z23.b, p11, z13.b, z8.b" diff --git a/tests/MC/AArch64/SVE/setffr.s.yaml b/tests/MC/AArch64/SVE/setffr.s.yaml new file mode 100644 index 0000000000..98b9fbb02f --- /dev/null +++ b/tests/MC/AArch64/SVE/setffr.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x90, 0x2c, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "setffr" diff --git a/tests/MC/AArch64/SVE/smax.s.yaml b/tests/MC/AArch64/SVE/smax.s.yaml new file mode 100644 index 0000000000..b331f946af --- /dev/null +++ b/tests/MC/AArch64/SVE/smax.s.yaml @@ -0,0 +1,360 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xd0, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smax z0.b, z0.b, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smax z31.b, z31.b, #127" + + - + input: + bytes: [ 0x00, 0xd0, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smax z0.h, z0.h, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smax z31.h, z31.h, #127" + + - + input: + bytes: [ 0x00, 0xd0, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smax z0.s, z0.s, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smax z31.s, z31.s, #127" + + - + input: + bytes: [ 0x00, 0xd0, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smax z0.d, z0.d, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smax z31.d, z31.d, #127" + + - + input: + bytes: [ 0xff, 0x1f, 0x08, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smax z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x1f, 0x48, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smax z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x88, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smax z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0xc8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smax z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x1f, 0xc8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smax z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0xc8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smax z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xcf, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smax z31.d, z31.d, #127" + + - + input: + bytes: [ 0x00, 0xd0, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smax z0.b, z0.b, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smax z31.b, z31.b, #127" + + - + input: + bytes: [ 0x00, 0xd0, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smax z0.h, z0.h, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smax z31.h, z31.h, #127" + + - + input: + bytes: [ 0x00, 0xd0, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smax z0.s, z0.s, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smax z31.s, z31.s, #127" + + - + input: + bytes: [ 0x00, 0xd0, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smax z0.d, z0.d, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smax z31.d, z31.d, #127" + + - + input: + bytes: [ 0xff, 0x1f, 0x08, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smax z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x1f, 0x48, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smax z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x88, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smax z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0xc8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smax z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x1f, 0xc8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smax z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0xc8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smax z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xcf, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smax z31.d, z31.d, #127" diff --git a/tests/MC/AArch64/SVE/smaxv.s.yaml b/tests/MC/AArch64/SVE/smaxv.s.yaml new file mode 100644 index 0000000000..4256fca55f --- /dev/null +++ b/tests/MC/AArch64/SVE/smaxv.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x3f, 0x08, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smaxv b0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x48, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smaxv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x88, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smaxv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xc8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smaxv d0, p7, z31.d" + + - + input: + bytes: [ 0xe0, 0x3f, 0x08, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smaxv b0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x48, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smaxv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x88, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smaxv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xc8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smaxv d0, p7, z31.d" diff --git a/tests/MC/AArch64/SVE/smin.s.yaml b/tests/MC/AArch64/SVE/smin.s.yaml new file mode 100644 index 0000000000..f9289654d7 --- /dev/null +++ b/tests/MC/AArch64/SVE/smin.s.yaml @@ -0,0 +1,360 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xd0, 0x2a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smin z0.b, z0.b, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0x2a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smin z31.b, z31.b, #127" + + - + input: + bytes: [ 0x00, 0xd0, 0x6a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smin z0.h, z0.h, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0x6a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smin z31.h, z31.h, #127" + + - + input: + bytes: [ 0x00, 0xd0, 0xaa, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smin z0.s, z0.s, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0xaa, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smin z31.s, z31.s, #127" + + - + input: + bytes: [ 0x00, 0xd0, 0xea, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smin z0.d, z0.d, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0xea, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smin z31.d, z31.d, #127" + + - + input: + bytes: [ 0xff, 0x1f, 0x0a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smin z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x1f, 0x4a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smin z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x8a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smin z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0xca, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smin z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x1f, 0xca, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smin z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0xca, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smin z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xcf, 0xea, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smin z31.d, z31.d, #127" + + - + input: + bytes: [ 0x00, 0xd0, 0x2a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smin z0.b, z0.b, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0x2a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smin z31.b, z31.b, #127" + + - + input: + bytes: [ 0x00, 0xd0, 0x6a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smin z0.h, z0.h, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0x6a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smin z31.h, z31.h, #127" + + - + input: + bytes: [ 0x00, 0xd0, 0xaa, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smin z0.s, z0.s, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0xaa, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smin z31.s, z31.s, #127" + + - + input: + bytes: [ 0x00, 0xd0, 0xea, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smin z0.d, z0.d, #-128" + + - + input: + bytes: [ 0xff, 0xcf, 0xea, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smin z31.d, z31.d, #127" + + - + input: + bytes: [ 0xff, 0x1f, 0x0a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smin z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x1f, 0x4a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smin z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x8a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smin z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0xca, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smin z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x1f, 0xca, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smin z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0xca, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smin z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xcf, 0xea, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smin z31.d, z31.d, #127" diff --git a/tests/MC/AArch64/SVE/sminv.s.yaml b/tests/MC/AArch64/SVE/sminv.s.yaml new file mode 100644 index 0000000000..8cec853779 --- /dev/null +++ b/tests/MC/AArch64/SVE/sminv.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x3f, 0x0a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sminv b0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x4a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sminv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x8a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sminv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xca, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sminv d0, p7, z31.d" + + - + input: + bytes: [ 0xe0, 0x3f, 0x0a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sminv b0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x4a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sminv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x8a, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sminv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xca, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sminv d0, p7, z31.d" diff --git a/tests/MC/AArch64/SVE/smulh.s.yaml b/tests/MC/AArch64/SVE/smulh.s.yaml new file mode 100644 index 0000000000..f21e0e5f18 --- /dev/null +++ b/tests/MC/AArch64/SVE/smulh.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x1f, 0x12, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smulh z0.b, p7/m, z0.b, z31.b" + + - + input: + bytes: [ 0xe0, 0x1f, 0x52, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smulh z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x1f, 0x92, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smulh z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smulh z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smulh z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "smulh z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0x12, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smulh z0.b, p7/m, z0.b, z31.b" + + - + input: + bytes: [ 0xe0, 0x1f, 0x52, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smulh z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x1f, 0x92, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smulh z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smulh z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smulh z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smulh z0.d, p7/m, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/splice.s.yaml b/tests/MC/AArch64/SVE/splice.s.yaml new file mode 100644 index 0000000000..8585d45e71 --- /dev/null +++ b/tests/MC/AArch64/SVE/splice.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x9f, 0x2c, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "splice z31.b, p7, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x9f, 0x6c, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "splice z31.h, p7, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x9f, 0xac, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "splice z31.s, p7, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x9f, 0xec, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "splice z31.d, p7, z31.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x9f, 0xec, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "splice z4.d, p7, z4.d, z31.d" + + - + input: + bytes: [ 0xff, 0x9f, 0x2c, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "splice z31.b, p7, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x9f, 0x6c, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "splice z31.h, p7, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x9f, 0xac, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "splice z31.s, p7, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x9f, 0xec, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "splice z31.d, p7, z31.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x9f, 0xec, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "splice z4.d, p7, z4.d, z31.d" diff --git a/tests/MC/AArch64/SVE/sqadd.s.yaml b/tests/MC/AArch64/SVE/sqadd.s.yaml new file mode 100644 index 0000000000..ddc7fbe08d --- /dev/null +++ b/tests/MC/AArch64/SVE/sqadd.s.yaml @@ -0,0 +1,400 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x10, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqadd z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x10, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqadd z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x10, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqadd z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x10, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqadd z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0xc0, 0x24, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqadd z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x24, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqadd z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x64, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqadd z0.h, z0.h, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0x64, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqadd z0.h, z0.h, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0x64, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqadd z31.h, z31.h, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0x64, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqadd z31.h, z31.h, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xa4, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqadd z0.s, z0.s, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xa4, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqadd z0.s, z0.s, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xa4, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqadd z31.s, z31.s, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xa4, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqadd z31.s, z31.s, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xe4, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqadd z0.d, z0.d, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xe4, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqadd z0.d, z0.d, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xe4, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqadd z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xe4, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqadd z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xff, 0xe4, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqadd z31.d, z31.d, #65280" + + - + input: + bytes: [ 0x00, 0x10, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x10, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x10, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x10, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0xc0, 0x24, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x24, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x64, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z0.h, z0.h, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0x64, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z0.h, z0.h, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0x64, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z31.h, z31.h, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0x64, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z31.h, z31.h, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xa4, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z0.s, z0.s, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xa4, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z0.s, z0.s, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xa4, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z31.s, z31.s, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xa4, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z31.s, z31.s, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xe4, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z0.d, z0.d, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xe4, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z0.d, z0.d, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xe4, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xe4, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xff, 0xe4, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z31.d, z31.d, #65280" diff --git a/tests/MC/AArch64/SVE/sqdecb.s.yaml b/tests/MC/AArch64/SVE/sqdecb.s.yaml new file mode 100644 index 0000000000..b7471bed69 --- /dev/null +++ b/tests/MC/AArch64/SVE/sqdecb.s.yaml @@ -0,0 +1,780 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xfb, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xfb, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf8, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, w0, pow2" + + - + input: + bytes: [ 0x00, 0xf8, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, w0, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf8, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, pow2" + + - + input: + bytes: [ 0x20, 0xf8, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl1" + + - + input: + bytes: [ 0x40, 0xf8, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl2" + + - + input: + bytes: [ 0x60, 0xf8, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl3" + + - + input: + bytes: [ 0x80, 0xf8, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf8, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf8, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf8, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl7" + + - + input: + bytes: [ 0x00, 0xf9, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl8" + + - + input: + bytes: [ 0x20, 0xf9, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl16" + + - + input: + bytes: [ 0x40, 0xf9, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl32" + + - + input: + bytes: [ 0x60, 0xf9, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl64" + + - + input: + bytes: [ 0x80, 0xf9, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf9, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf9, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, #14" + + - + input: + bytes: [ 0xe0, 0xf9, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, #15" + + - + input: + bytes: [ 0x00, 0xfa, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, #16" + + - + input: + bytes: [ 0x20, 0xfa, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, #17" + + - + input: + bytes: [ 0x40, 0xfa, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, #18" + + - + input: + bytes: [ 0x60, 0xfa, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, #19" + + - + input: + bytes: [ 0x80, 0xfa, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, #20" + + - + input: + bytes: [ 0xa0, 0xfa, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, #21" + + - + input: + bytes: [ 0xc0, 0xfa, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, #22" + + - + input: + bytes: [ 0xe0, 0xfa, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, #23" + + - + input: + bytes: [ 0x00, 0xfb, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, #24" + + - + input: + bytes: [ 0x20, 0xfb, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, #25" + + - + input: + bytes: [ 0x40, 0xfb, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, #26" + + - + input: + bytes: [ 0x60, 0xfb, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, #27" + + - + input: + bytes: [ 0x80, 0xfb, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecb x0, #28" + + - + input: + bytes: [ 0xe0, 0xfb, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xfb, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf8, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, w0, pow2" + + - + input: + bytes: [ 0x00, 0xf8, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, w0, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf8, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, pow2" + + - + input: + bytes: [ 0x20, 0xf8, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl1" + + - + input: + bytes: [ 0x40, 0xf8, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl2" + + - + input: + bytes: [ 0x60, 0xf8, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl3" + + - + input: + bytes: [ 0x80, 0xf8, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf8, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf8, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf8, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl7" + + - + input: + bytes: [ 0x00, 0xf9, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl8" + + - + input: + bytes: [ 0x20, 0xf9, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl16" + + - + input: + bytes: [ 0x40, 0xf9, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl32" + + - + input: + bytes: [ 0x60, 0xf9, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl64" + + - + input: + bytes: [ 0x80, 0xf9, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf9, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf9, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, #14" + + - + input: + bytes: [ 0xe0, 0xf9, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, #15" + + - + input: + bytes: [ 0x00, 0xfa, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, #16" + + - + input: + bytes: [ 0x20, 0xfa, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, #17" + + - + input: + bytes: [ 0x40, 0xfa, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, #18" + + - + input: + bytes: [ 0x60, 0xfa, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, #19" + + - + input: + bytes: [ 0x80, 0xfa, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, #20" + + - + input: + bytes: [ 0xa0, 0xfa, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, #21" + + - + input: + bytes: [ 0xc0, 0xfa, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, #22" + + - + input: + bytes: [ 0xe0, 0xfa, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, #23" + + - + input: + bytes: [ 0x00, 0xfb, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, #24" + + - + input: + bytes: [ 0x20, 0xfb, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, #25" + + - + input: + bytes: [ 0x40, 0xfb, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, #26" + + - + input: + bytes: [ 0x60, 0xfb, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, #27" + + - + input: + bytes: [ 0x80, 0xfb, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecb x0, #28" diff --git a/tests/MC/AArch64/SVE/sqdecd.s.yaml b/tests/MC/AArch64/SVE/sqdecd.s.yaml new file mode 100644 index 0000000000..54b2df996c --- /dev/null +++ b/tests/MC/AArch64/SVE/sqdecd.s.yaml @@ -0,0 +1,1020 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xfb, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xfb, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf8, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, w0, pow2" + + - + input: + bytes: [ 0x00, 0xf8, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xcb, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd z0.d" + + - + input: + bytes: [ 0xe0, 0xcb, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd z0.d" + + - + input: + bytes: [ 0xe0, 0xcb, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd z0.d" + + - + input: + bytes: [ 0xe0, 0xcb, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd z0.d, all, mul #16" + + - + input: + bytes: [ 0x00, 0xc8, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd z0.d, pow2" + + - + input: + bytes: [ 0x00, 0xc8, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd z0.d, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf8, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, pow2" + + - + input: + bytes: [ 0x20, 0xf8, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl1" + + - + input: + bytes: [ 0x40, 0xf8, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl2" + + - + input: + bytes: [ 0x60, 0xf8, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl3" + + - + input: + bytes: [ 0x80, 0xf8, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf8, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf8, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf8, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl7" + + - + input: + bytes: [ 0x00, 0xf9, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl8" + + - + input: + bytes: [ 0x20, 0xf9, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl16" + + - + input: + bytes: [ 0x40, 0xf9, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl32" + + - + input: + bytes: [ 0x60, 0xf9, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl64" + + - + input: + bytes: [ 0x80, 0xf9, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf9, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf9, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, #14" + + - + input: + bytes: [ 0xe0, 0xf9, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, #15" + + - + input: + bytes: [ 0x00, 0xfa, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, #16" + + - + input: + bytes: [ 0x20, 0xfa, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, #17" + + - + input: + bytes: [ 0x40, 0xfa, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, #18" + + - + input: + bytes: [ 0x60, 0xfa, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, #19" + + - + input: + bytes: [ 0x80, 0xfa, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, #20" + + - + input: + bytes: [ 0xa0, 0xfa, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, #21" + + - + input: + bytes: [ 0xc0, 0xfa, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, #22" + + - + input: + bytes: [ 0xe0, 0xfa, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, #23" + + - + input: + bytes: [ 0x00, 0xfb, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, #24" + + - + input: + bytes: [ 0x20, 0xfb, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, #25" + + - + input: + bytes: [ 0x40, 0xfb, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, #26" + + - + input: + bytes: [ 0x60, 0xfb, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, #27" + + - + input: + bytes: [ 0x80, 0xfb, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xcb, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd z0.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc8, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd z0.d, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc8, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecd z0.d, pow2" + + - + input: + bytes: [ 0xe0, 0xfb, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xfb, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf8, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, w0, pow2" + + - + input: + bytes: [ 0x00, 0xf8, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xcb, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd z0.d" + + - + input: + bytes: [ 0xe0, 0xcb, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd z0.d" + + - + input: + bytes: [ 0xe0, 0xcb, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd z0.d" + + - + input: + bytes: [ 0xe0, 0xcb, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd z0.d, all, mul #16" + + - + input: + bytes: [ 0x00, 0xc8, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd z0.d, pow2" + + - + input: + bytes: [ 0x00, 0xc8, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd z0.d, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf8, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, pow2" + + - + input: + bytes: [ 0x20, 0xf8, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl1" + + - + input: + bytes: [ 0x40, 0xf8, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl2" + + - + input: + bytes: [ 0x60, 0xf8, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl3" + + - + input: + bytes: [ 0x80, 0xf8, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf8, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf8, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf8, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl7" + + - + input: + bytes: [ 0x00, 0xf9, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl8" + + - + input: + bytes: [ 0x20, 0xf9, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl16" + + - + input: + bytes: [ 0x40, 0xf9, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl32" + + - + input: + bytes: [ 0x60, 0xf9, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl64" + + - + input: + bytes: [ 0x80, 0xf9, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf9, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf9, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, #14" + + - + input: + bytes: [ 0xe0, 0xf9, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, #15" + + - + input: + bytes: [ 0x00, 0xfa, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, #16" + + - + input: + bytes: [ 0x20, 0xfa, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, #17" + + - + input: + bytes: [ 0x40, 0xfa, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, #18" + + - + input: + bytes: [ 0x60, 0xfa, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, #19" + + - + input: + bytes: [ 0x80, 0xfa, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, #20" + + - + input: + bytes: [ 0xa0, 0xfa, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, #21" + + - + input: + bytes: [ 0xc0, 0xfa, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, #22" + + - + input: + bytes: [ 0xe0, 0xfa, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, #23" + + - + input: + bytes: [ 0x00, 0xfb, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, #24" + + - + input: + bytes: [ 0x20, 0xfb, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, #25" + + - + input: + bytes: [ 0x40, 0xfb, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, #26" + + - + input: + bytes: [ 0x60, 0xfb, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, #27" + + - + input: + bytes: [ 0x80, 0xfb, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xcb, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd z0.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc8, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd z0.d, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc8, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecd z0.d, pow2" diff --git a/tests/MC/AArch64/SVE/sqdech.s.yaml b/tests/MC/AArch64/SVE/sqdech.s.yaml new file mode 100644 index 0000000000..ec3a80efc0 --- /dev/null +++ b/tests/MC/AArch64/SVE/sqdech.s.yaml @@ -0,0 +1,1020 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xfb, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xfb, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf8, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, w0, pow2" + + - + input: + bytes: [ 0x00, 0xf8, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xcb, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech z0.h" + + - + input: + bytes: [ 0xe0, 0xcb, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech z0.h" + + - + input: + bytes: [ 0xe0, 0xcb, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech z0.h" + + - + input: + bytes: [ 0xe0, 0xcb, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech z0.h, all, mul #16" + + - + input: + bytes: [ 0x00, 0xc8, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech z0.h, pow2" + + - + input: + bytes: [ 0x00, 0xc8, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech z0.h, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf8, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, pow2" + + - + input: + bytes: [ 0x20, 0xf8, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, vl1" + + - + input: + bytes: [ 0x40, 0xf8, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, vl2" + + - + input: + bytes: [ 0x60, 0xf8, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, vl3" + + - + input: + bytes: [ 0x80, 0xf8, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf8, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf8, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf8, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, vl7" + + - + input: + bytes: [ 0x00, 0xf9, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, vl8" + + - + input: + bytes: [ 0x20, 0xf9, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, vl16" + + - + input: + bytes: [ 0x40, 0xf9, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, vl32" + + - + input: + bytes: [ 0x60, 0xf9, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, vl64" + + - + input: + bytes: [ 0x80, 0xf9, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf9, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf9, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, #14" + + - + input: + bytes: [ 0xe0, 0xf9, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, #15" + + - + input: + bytes: [ 0x00, 0xfa, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, #16" + + - + input: + bytes: [ 0x20, 0xfa, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, #17" + + - + input: + bytes: [ 0x40, 0xfa, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, #18" + + - + input: + bytes: [ 0x60, 0xfa, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, #19" + + - + input: + bytes: [ 0x80, 0xfa, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, #20" + + - + input: + bytes: [ 0xa0, 0xfa, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, #21" + + - + input: + bytes: [ 0xc0, 0xfa, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, #22" + + - + input: + bytes: [ 0xe0, 0xfa, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, #23" + + - + input: + bytes: [ 0x00, 0xfb, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, #24" + + - + input: + bytes: [ 0x20, 0xfb, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, #25" + + - + input: + bytes: [ 0x40, 0xfb, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, #26" + + - + input: + bytes: [ 0x60, 0xfb, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, #27" + + - + input: + bytes: [ 0x80, 0xfb, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xcb, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech z0.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc8, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech z0.h, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc8, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdech z0.h, pow2" + + - + input: + bytes: [ 0xe0, 0xfb, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xfb, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf8, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, w0, pow2" + + - + input: + bytes: [ 0x00, 0xf8, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xcb, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech z0.h" + + - + input: + bytes: [ 0xe0, 0xcb, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech z0.h" + + - + input: + bytes: [ 0xe0, 0xcb, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech z0.h" + + - + input: + bytes: [ 0xe0, 0xcb, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech z0.h, all, mul #16" + + - + input: + bytes: [ 0x00, 0xc8, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech z0.h, pow2" + + - + input: + bytes: [ 0x00, 0xc8, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech z0.h, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf8, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, pow2" + + - + input: + bytes: [ 0x20, 0xf8, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, vl1" + + - + input: + bytes: [ 0x40, 0xf8, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, vl2" + + - + input: + bytes: [ 0x60, 0xf8, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, vl3" + + - + input: + bytes: [ 0x80, 0xf8, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf8, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf8, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf8, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, vl7" + + - + input: + bytes: [ 0x00, 0xf9, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, vl8" + + - + input: + bytes: [ 0x20, 0xf9, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, vl16" + + - + input: + bytes: [ 0x40, 0xf9, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, vl32" + + - + input: + bytes: [ 0x60, 0xf9, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, vl64" + + - + input: + bytes: [ 0x80, 0xf9, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf9, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf9, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, #14" + + - + input: + bytes: [ 0xe0, 0xf9, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, #15" + + - + input: + bytes: [ 0x00, 0xfa, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, #16" + + - + input: + bytes: [ 0x20, 0xfa, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, #17" + + - + input: + bytes: [ 0x40, 0xfa, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, #18" + + - + input: + bytes: [ 0x60, 0xfa, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, #19" + + - + input: + bytes: [ 0x80, 0xfa, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, #20" + + - + input: + bytes: [ 0xa0, 0xfa, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, #21" + + - + input: + bytes: [ 0xc0, 0xfa, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, #22" + + - + input: + bytes: [ 0xe0, 0xfa, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, #23" + + - + input: + bytes: [ 0x00, 0xfb, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, #24" + + - + input: + bytes: [ 0x20, 0xfb, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, #25" + + - + input: + bytes: [ 0x40, 0xfb, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, #26" + + - + input: + bytes: [ 0x60, 0xfb, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, #27" + + - + input: + bytes: [ 0x80, 0xfb, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xcb, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech z0.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc8, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech z0.h, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc8, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdech z0.h, pow2" diff --git a/tests/MC/AArch64/SVE/sqdecp.s.yaml b/tests/MC/AArch64/SVE/sqdecp.s.yaml new file mode 100644 index 0000000000..4305c565c7 --- /dev/null +++ b/tests/MC/AArch64/SVE/sqdecp.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x8c, 0x2a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecp x0, p0.b" + + - + input: + bytes: [ 0x00, 0x8c, 0x6a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecp x0, p0.h" + + - + input: + bytes: [ 0x00, 0x8c, 0xaa, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecp x0, p0.s" + + - + input: + bytes: [ 0x00, 0x8c, 0xea, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecp x0, p0.d" + + - + input: + bytes: [ 0xff, 0x89, 0x2a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecp xzr, p15.b, wzr" + + - + input: + bytes: [ 0xff, 0x89, 0x6a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecp xzr, p15.h, wzr" + + - + input: + bytes: [ 0xff, 0x89, 0xaa, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecp xzr, p15.s, wzr" + + - + input: + bytes: [ 0xff, 0x89, 0xea, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecp xzr, p15.d, wzr" + + - + input: + bytes: [ 0x00, 0x80, 0x6a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecp z0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x6a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecp z0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x80, 0xaa, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecp z0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xaa, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecp z0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xea, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecp z0.d, p0.d" + + - + input: + bytes: [ 0x00, 0x80, 0xea, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecp z0.d, p0.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0x80, 0xea, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecp z0.d, p0.d" + + - + input: + bytes: [ 0x00, 0x8c, 0x2a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecp x0, p0.b" + + - + input: + bytes: [ 0x00, 0x8c, 0x6a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecp x0, p0.h" + + - + input: + bytes: [ 0x00, 0x8c, 0xaa, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecp x0, p0.s" + + - + input: + bytes: [ 0x00, 0x8c, 0xea, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecp x0, p0.d" + + - + input: + bytes: [ 0xff, 0x89, 0x2a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecp xzr, p15.b, wzr" + + - + input: + bytes: [ 0xff, 0x89, 0x6a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecp xzr, p15.h, wzr" + + - + input: + bytes: [ 0xff, 0x89, 0xaa, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecp xzr, p15.s, wzr" + + - + input: + bytes: [ 0xff, 0x89, 0xea, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecp xzr, p15.d, wzr" + + - + input: + bytes: [ 0x00, 0x80, 0x6a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecp z0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x6a, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecp z0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x80, 0xaa, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecp z0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xaa, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecp z0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xea, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecp z0.d, p0.d" + + - + input: + bytes: [ 0x00, 0x80, 0xea, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecp z0.d, p0.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0x80, 0xea, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecp z0.d, p0.d" diff --git a/tests/MC/AArch64/SVE/sqdecw.s.yaml b/tests/MC/AArch64/SVE/sqdecw.s.yaml new file mode 100644 index 0000000000..fa2f9c82c5 --- /dev/null +++ b/tests/MC/AArch64/SVE/sqdecw.s.yaml @@ -0,0 +1,1020 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xfb, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xfb, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf8, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, w0, pow2" + + - + input: + bytes: [ 0x00, 0xf8, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xcb, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw z0.s" + + - + input: + bytes: [ 0xe0, 0xcb, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw z0.s" + + - + input: + bytes: [ 0xe0, 0xcb, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw z0.s" + + - + input: + bytes: [ 0xe0, 0xcb, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw z0.s, all, mul #16" + + - + input: + bytes: [ 0x00, 0xc8, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw z0.s, pow2" + + - + input: + bytes: [ 0x00, 0xc8, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw z0.s, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf8, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, pow2" + + - + input: + bytes: [ 0x20, 0xf8, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl1" + + - + input: + bytes: [ 0x40, 0xf8, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl2" + + - + input: + bytes: [ 0x60, 0xf8, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl3" + + - + input: + bytes: [ 0x80, 0xf8, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf8, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf8, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf8, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl7" + + - + input: + bytes: [ 0x00, 0xf9, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl8" + + - + input: + bytes: [ 0x20, 0xf9, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl16" + + - + input: + bytes: [ 0x40, 0xf9, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl32" + + - + input: + bytes: [ 0x60, 0xf9, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl64" + + - + input: + bytes: [ 0x80, 0xf9, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf9, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf9, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, #14" + + - + input: + bytes: [ 0xe0, 0xf9, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, #15" + + - + input: + bytes: [ 0x00, 0xfa, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, #16" + + - + input: + bytes: [ 0x20, 0xfa, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, #17" + + - + input: + bytes: [ 0x40, 0xfa, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, #18" + + - + input: + bytes: [ 0x60, 0xfa, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, #19" + + - + input: + bytes: [ 0x80, 0xfa, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, #20" + + - + input: + bytes: [ 0xa0, 0xfa, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, #21" + + - + input: + bytes: [ 0xc0, 0xfa, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, #22" + + - + input: + bytes: [ 0xe0, 0xfa, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, #23" + + - + input: + bytes: [ 0x00, 0xfb, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, #24" + + - + input: + bytes: [ 0x20, 0xfb, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, #25" + + - + input: + bytes: [ 0x40, 0xfb, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, #26" + + - + input: + bytes: [ 0x60, 0xfb, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, #27" + + - + input: + bytes: [ 0x80, 0xfb, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xcb, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw z0.s" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc8, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw z0.s, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc8, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqdecw z0.s, pow2" + + - + input: + bytes: [ 0xe0, 0xfb, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xfb, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, w0" + + - + input: + bytes: [ 0xe0, 0xfb, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf8, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, w0, pow2" + + - + input: + bytes: [ 0x00, 0xf8, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xcb, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw z0.s" + + - + input: + bytes: [ 0xe0, 0xcb, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw z0.s" + + - + input: + bytes: [ 0xe0, 0xcb, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw z0.s" + + - + input: + bytes: [ 0xe0, 0xcb, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw z0.s, all, mul #16" + + - + input: + bytes: [ 0x00, 0xc8, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw z0.s, pow2" + + - + input: + bytes: [ 0x00, 0xc8, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw z0.s, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf8, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, pow2" + + - + input: + bytes: [ 0x20, 0xf8, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl1" + + - + input: + bytes: [ 0x40, 0xf8, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl2" + + - + input: + bytes: [ 0x60, 0xf8, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl3" + + - + input: + bytes: [ 0x80, 0xf8, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf8, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf8, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf8, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl7" + + - + input: + bytes: [ 0x00, 0xf9, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl8" + + - + input: + bytes: [ 0x20, 0xf9, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl16" + + - + input: + bytes: [ 0x40, 0xf9, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl32" + + - + input: + bytes: [ 0x60, 0xf9, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl64" + + - + input: + bytes: [ 0x80, 0xf9, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf9, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf9, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, #14" + + - + input: + bytes: [ 0xe0, 0xf9, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, #15" + + - + input: + bytes: [ 0x00, 0xfa, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, #16" + + - + input: + bytes: [ 0x20, 0xfa, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, #17" + + - + input: + bytes: [ 0x40, 0xfa, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, #18" + + - + input: + bytes: [ 0x60, 0xfa, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, #19" + + - + input: + bytes: [ 0x80, 0xfa, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, #20" + + - + input: + bytes: [ 0xa0, 0xfa, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, #21" + + - + input: + bytes: [ 0xc0, 0xfa, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, #22" + + - + input: + bytes: [ 0xe0, 0xfa, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, #23" + + - + input: + bytes: [ 0x00, 0xfb, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, #24" + + - + input: + bytes: [ 0x20, 0xfb, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, #25" + + - + input: + bytes: [ 0x40, 0xfb, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, #26" + + - + input: + bytes: [ 0x60, 0xfb, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, #27" + + - + input: + bytes: [ 0x80, 0xfb, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xcb, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw z0.s" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc8, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw z0.s, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc8, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdecw z0.s, pow2" diff --git a/tests/MC/AArch64/SVE/sqincb.s.yaml b/tests/MC/AArch64/SVE/sqincb.s.yaml new file mode 100644 index 0000000000..1d51c91395 --- /dev/null +++ b/tests/MC/AArch64/SVE/sqincb.s.yaml @@ -0,0 +1,780 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xf3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xf3, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf0, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, w0, pow2" + + - + input: + bytes: [ 0x00, 0xf0, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, w0, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, pow2" + + - + input: + bytes: [ 0x20, 0xf0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, vl1" + + - + input: + bytes: [ 0x40, 0xf0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, vl2" + + - + input: + bytes: [ 0x60, 0xf0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, vl3" + + - + input: + bytes: [ 0x80, 0xf0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, vl7" + + - + input: + bytes: [ 0x00, 0xf1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, vl8" + + - + input: + bytes: [ 0x20, 0xf1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, vl16" + + - + input: + bytes: [ 0x40, 0xf1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, vl32" + + - + input: + bytes: [ 0x60, 0xf1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, vl64" + + - + input: + bytes: [ 0x80, 0xf1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, #14" + + - + input: + bytes: [ 0xe0, 0xf1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, #15" + + - + input: + bytes: [ 0x00, 0xf2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, #16" + + - + input: + bytes: [ 0x20, 0xf2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, #17" + + - + input: + bytes: [ 0x40, 0xf2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, #18" + + - + input: + bytes: [ 0x60, 0xf2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, #19" + + - + input: + bytes: [ 0x80, 0xf2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, #20" + + - + input: + bytes: [ 0xa0, 0xf2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, #21" + + - + input: + bytes: [ 0xc0, 0xf2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, #22" + + - + input: + bytes: [ 0xe0, 0xf2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, #23" + + - + input: + bytes: [ 0x00, 0xf3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, #24" + + - + input: + bytes: [ 0x20, 0xf3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, #25" + + - + input: + bytes: [ 0x40, 0xf3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, #26" + + - + input: + bytes: [ 0x60, 0xf3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, #27" + + - + input: + bytes: [ 0x80, 0xf3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincb x0, #28" + + - + input: + bytes: [ 0xe0, 0xf3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xf3, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf0, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, w0, pow2" + + - + input: + bytes: [ 0x00, 0xf0, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, w0, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, pow2" + + - + input: + bytes: [ 0x20, 0xf0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, vl1" + + - + input: + bytes: [ 0x40, 0xf0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, vl2" + + - + input: + bytes: [ 0x60, 0xf0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, vl3" + + - + input: + bytes: [ 0x80, 0xf0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf0, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, vl7" + + - + input: + bytes: [ 0x00, 0xf1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, vl8" + + - + input: + bytes: [ 0x20, 0xf1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, vl16" + + - + input: + bytes: [ 0x40, 0xf1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, vl32" + + - + input: + bytes: [ 0x60, 0xf1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, vl64" + + - + input: + bytes: [ 0x80, 0xf1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, #14" + + - + input: + bytes: [ 0xe0, 0xf1, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, #15" + + - + input: + bytes: [ 0x00, 0xf2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, #16" + + - + input: + bytes: [ 0x20, 0xf2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, #17" + + - + input: + bytes: [ 0x40, 0xf2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, #18" + + - + input: + bytes: [ 0x60, 0xf2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, #19" + + - + input: + bytes: [ 0x80, 0xf2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, #20" + + - + input: + bytes: [ 0xa0, 0xf2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, #21" + + - + input: + bytes: [ 0xc0, 0xf2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, #22" + + - + input: + bytes: [ 0xe0, 0xf2, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, #23" + + - + input: + bytes: [ 0x00, 0xf3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, #24" + + - + input: + bytes: [ 0x20, 0xf3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, #25" + + - + input: + bytes: [ 0x40, 0xf3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, #26" + + - + input: + bytes: [ 0x60, 0xf3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, #27" + + - + input: + bytes: [ 0x80, 0xf3, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincb x0, #28" diff --git a/tests/MC/AArch64/SVE/sqincd.s.yaml b/tests/MC/AArch64/SVE/sqincd.s.yaml new file mode 100644 index 0000000000..199de73278 --- /dev/null +++ b/tests/MC/AArch64/SVE/sqincd.s.yaml @@ -0,0 +1,1020 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xf3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xf3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf0, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, w0, pow2" + + - + input: + bytes: [ 0x00, 0xf0, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xc3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd z0.d" + + - + input: + bytes: [ 0xe0, 0xc3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd z0.d" + + - + input: + bytes: [ 0xe0, 0xc3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd z0.d" + + - + input: + bytes: [ 0xe0, 0xc3, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd z0.d, all, mul #16" + + - + input: + bytes: [ 0x00, 0xc0, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd z0.d, pow2" + + - + input: + bytes: [ 0x00, 0xc0, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd z0.d, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, pow2" + + - + input: + bytes: [ 0x20, 0xf0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, vl1" + + - + input: + bytes: [ 0x40, 0xf0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, vl2" + + - + input: + bytes: [ 0x60, 0xf0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, vl3" + + - + input: + bytes: [ 0x80, 0xf0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, vl7" + + - + input: + bytes: [ 0x00, 0xf1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, vl8" + + - + input: + bytes: [ 0x20, 0xf1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, vl16" + + - + input: + bytes: [ 0x40, 0xf1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, vl32" + + - + input: + bytes: [ 0x60, 0xf1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, vl64" + + - + input: + bytes: [ 0x80, 0xf1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, #14" + + - + input: + bytes: [ 0xe0, 0xf1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, #15" + + - + input: + bytes: [ 0x00, 0xf2, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, #16" + + - + input: + bytes: [ 0x20, 0xf2, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, #17" + + - + input: + bytes: [ 0x40, 0xf2, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, #18" + + - + input: + bytes: [ 0x60, 0xf2, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, #19" + + - + input: + bytes: [ 0x80, 0xf2, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, #20" + + - + input: + bytes: [ 0xa0, 0xf2, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, #21" + + - + input: + bytes: [ 0xc0, 0xf2, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, #22" + + - + input: + bytes: [ 0xe0, 0xf2, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, #23" + + - + input: + bytes: [ 0x00, 0xf3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, #24" + + - + input: + bytes: [ 0x20, 0xf3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, #25" + + - + input: + bytes: [ 0x40, 0xf3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, #26" + + - + input: + bytes: [ 0x60, 0xf3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, #27" + + - + input: + bytes: [ 0x80, 0xf3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd z0.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc0, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd z0.d, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc0, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincd z0.d, pow2" + + - + input: + bytes: [ 0xe0, 0xf3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xf3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf0, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, w0, pow2" + + - + input: + bytes: [ 0x00, 0xf0, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xc3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd z0.d" + + - + input: + bytes: [ 0xe0, 0xc3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd z0.d" + + - + input: + bytes: [ 0xe0, 0xc3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd z0.d" + + - + input: + bytes: [ 0xe0, 0xc3, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd z0.d, all, mul #16" + + - + input: + bytes: [ 0x00, 0xc0, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd z0.d, pow2" + + - + input: + bytes: [ 0x00, 0xc0, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd z0.d, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, pow2" + + - + input: + bytes: [ 0x20, 0xf0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, vl1" + + - + input: + bytes: [ 0x40, 0xf0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, vl2" + + - + input: + bytes: [ 0x60, 0xf0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, vl3" + + - + input: + bytes: [ 0x80, 0xf0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf0, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, vl7" + + - + input: + bytes: [ 0x00, 0xf1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, vl8" + + - + input: + bytes: [ 0x20, 0xf1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, vl16" + + - + input: + bytes: [ 0x40, 0xf1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, vl32" + + - + input: + bytes: [ 0x60, 0xf1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, vl64" + + - + input: + bytes: [ 0x80, 0xf1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, #14" + + - + input: + bytes: [ 0xe0, 0xf1, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, #15" + + - + input: + bytes: [ 0x00, 0xf2, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, #16" + + - + input: + bytes: [ 0x20, 0xf2, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, #17" + + - + input: + bytes: [ 0x40, 0xf2, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, #18" + + - + input: + bytes: [ 0x60, 0xf2, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, #19" + + - + input: + bytes: [ 0x80, 0xf2, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, #20" + + - + input: + bytes: [ 0xa0, 0xf2, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, #21" + + - + input: + bytes: [ 0xc0, 0xf2, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, #22" + + - + input: + bytes: [ 0xe0, 0xf2, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, #23" + + - + input: + bytes: [ 0x00, 0xf3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, #24" + + - + input: + bytes: [ 0x20, 0xf3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, #25" + + - + input: + bytes: [ 0x40, 0xf3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, #26" + + - + input: + bytes: [ 0x60, 0xf3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, #27" + + - + input: + bytes: [ 0x80, 0xf3, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd z0.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc0, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd z0.d, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc0, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincd z0.d, pow2" diff --git a/tests/MC/AArch64/SVE/sqinch.s.yaml b/tests/MC/AArch64/SVE/sqinch.s.yaml new file mode 100644 index 0000000000..ce85abb7f7 --- /dev/null +++ b/tests/MC/AArch64/SVE/sqinch.s.yaml @@ -0,0 +1,1020 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xf3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xf3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf0, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, w0, pow2" + + - + input: + bytes: [ 0x00, 0xf0, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xc3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch z0.h" + + - + input: + bytes: [ 0xe0, 0xc3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch z0.h" + + - + input: + bytes: [ 0xe0, 0xc3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch z0.h" + + - + input: + bytes: [ 0xe0, 0xc3, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch z0.h, all, mul #16" + + - + input: + bytes: [ 0x00, 0xc0, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch z0.h, pow2" + + - + input: + bytes: [ 0x00, 0xc0, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch z0.h, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, pow2" + + - + input: + bytes: [ 0x20, 0xf0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, vl1" + + - + input: + bytes: [ 0x40, 0xf0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, vl2" + + - + input: + bytes: [ 0x60, 0xf0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, vl3" + + - + input: + bytes: [ 0x80, 0xf0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, vl7" + + - + input: + bytes: [ 0x00, 0xf1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, vl8" + + - + input: + bytes: [ 0x20, 0xf1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, vl16" + + - + input: + bytes: [ 0x40, 0xf1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, vl32" + + - + input: + bytes: [ 0x60, 0xf1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, vl64" + + - + input: + bytes: [ 0x80, 0xf1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, #14" + + - + input: + bytes: [ 0xe0, 0xf1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, #15" + + - + input: + bytes: [ 0x00, 0xf2, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, #16" + + - + input: + bytes: [ 0x20, 0xf2, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, #17" + + - + input: + bytes: [ 0x40, 0xf2, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, #18" + + - + input: + bytes: [ 0x60, 0xf2, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, #19" + + - + input: + bytes: [ 0x80, 0xf2, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, #20" + + - + input: + bytes: [ 0xa0, 0xf2, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, #21" + + - + input: + bytes: [ 0xc0, 0xf2, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, #22" + + - + input: + bytes: [ 0xe0, 0xf2, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, #23" + + - + input: + bytes: [ 0x00, 0xf3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, #24" + + - + input: + bytes: [ 0x20, 0xf3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, #25" + + - + input: + bytes: [ 0x40, 0xf3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, #26" + + - + input: + bytes: [ 0x60, 0xf3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, #27" + + - + input: + bytes: [ 0x80, 0xf3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch z0.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc0, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch z0.h, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc0, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqinch z0.h, pow2" + + - + input: + bytes: [ 0xe0, 0xf3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xf3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf0, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, w0, pow2" + + - + input: + bytes: [ 0x00, 0xf0, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xc3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch z0.h" + + - + input: + bytes: [ 0xe0, 0xc3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch z0.h" + + - + input: + bytes: [ 0xe0, 0xc3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch z0.h" + + - + input: + bytes: [ 0xe0, 0xc3, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch z0.h, all, mul #16" + + - + input: + bytes: [ 0x00, 0xc0, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch z0.h, pow2" + + - + input: + bytes: [ 0x00, 0xc0, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch z0.h, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, pow2" + + - + input: + bytes: [ 0x20, 0xf0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, vl1" + + - + input: + bytes: [ 0x40, 0xf0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, vl2" + + - + input: + bytes: [ 0x60, 0xf0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, vl3" + + - + input: + bytes: [ 0x80, 0xf0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf0, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, vl7" + + - + input: + bytes: [ 0x00, 0xf1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, vl8" + + - + input: + bytes: [ 0x20, 0xf1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, vl16" + + - + input: + bytes: [ 0x40, 0xf1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, vl32" + + - + input: + bytes: [ 0x60, 0xf1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, vl64" + + - + input: + bytes: [ 0x80, 0xf1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, #14" + + - + input: + bytes: [ 0xe0, 0xf1, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, #15" + + - + input: + bytes: [ 0x00, 0xf2, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, #16" + + - + input: + bytes: [ 0x20, 0xf2, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, #17" + + - + input: + bytes: [ 0x40, 0xf2, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, #18" + + - + input: + bytes: [ 0x60, 0xf2, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, #19" + + - + input: + bytes: [ 0x80, 0xf2, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, #20" + + - + input: + bytes: [ 0xa0, 0xf2, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, #21" + + - + input: + bytes: [ 0xc0, 0xf2, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, #22" + + - + input: + bytes: [ 0xe0, 0xf2, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, #23" + + - + input: + bytes: [ 0x00, 0xf3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, #24" + + - + input: + bytes: [ 0x20, 0xf3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, #25" + + - + input: + bytes: [ 0x40, 0xf3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, #26" + + - + input: + bytes: [ 0x60, 0xf3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, #27" + + - + input: + bytes: [ 0x80, 0xf3, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch z0.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc0, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch z0.h, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc0, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqinch z0.h, pow2" diff --git a/tests/MC/AArch64/SVE/sqincp.s.yaml b/tests/MC/AArch64/SVE/sqincp.s.yaml new file mode 100644 index 0000000000..d6b011f867 --- /dev/null +++ b/tests/MC/AArch64/SVE/sqincp.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x8c, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincp x0, p0.b" + + - + input: + bytes: [ 0x00, 0x8c, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincp x0, p0.h" + + - + input: + bytes: [ 0x00, 0x8c, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincp x0, p0.s" + + - + input: + bytes: [ 0x00, 0x8c, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincp x0, p0.d" + + - + input: + bytes: [ 0xff, 0x89, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincp xzr, p15.b, wzr" + + - + input: + bytes: [ 0xff, 0x89, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincp xzr, p15.h, wzr" + + - + input: + bytes: [ 0xff, 0x89, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincp xzr, p15.s, wzr" + + - + input: + bytes: [ 0xff, 0x89, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincp xzr, p15.d, wzr" + + - + input: + bytes: [ 0x00, 0x80, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincp z0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincp z0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x80, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincp z0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincp z0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincp z0.d, p0.d" + + - + input: + bytes: [ 0x00, 0x80, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincp z0.d, p0.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0x80, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincp z0.d, p0.d" + + - + input: + bytes: [ 0x00, 0x8c, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincp x0, p0.b" + + - + input: + bytes: [ 0x00, 0x8c, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincp x0, p0.h" + + - + input: + bytes: [ 0x00, 0x8c, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincp x0, p0.s" + + - + input: + bytes: [ 0x00, 0x8c, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincp x0, p0.d" + + - + input: + bytes: [ 0xff, 0x89, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincp xzr, p15.b, wzr" + + - + input: + bytes: [ 0xff, 0x89, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincp xzr, p15.h, wzr" + + - + input: + bytes: [ 0xff, 0x89, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincp xzr, p15.s, wzr" + + - + input: + bytes: [ 0xff, 0x89, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincp xzr, p15.d, wzr" + + - + input: + bytes: [ 0x00, 0x80, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincp z0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincp z0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x80, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincp z0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincp z0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincp z0.d, p0.d" + + - + input: + bytes: [ 0x00, 0x80, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincp z0.d, p0.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0x80, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincp z0.d, p0.d" diff --git a/tests/MC/AArch64/SVE/sqincw.s.yaml b/tests/MC/AArch64/SVE/sqincw.s.yaml new file mode 100644 index 0000000000..3ed69eb05f --- /dev/null +++ b/tests/MC/AArch64/SVE/sqincw.s.yaml @@ -0,0 +1,1020 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xf3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf0, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, w0, pow2" + + - + input: + bytes: [ 0x00, 0xf0, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xc3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw z0.s" + + - + input: + bytes: [ 0xe0, 0xc3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw z0.s" + + - + input: + bytes: [ 0xe0, 0xc3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw z0.s" + + - + input: + bytes: [ 0xe0, 0xc3, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw z0.s, all, mul #16" + + - + input: + bytes: [ 0x00, 0xc0, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw z0.s, pow2" + + - + input: + bytes: [ 0x00, 0xc0, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw z0.s, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, pow2" + + - + input: + bytes: [ 0x20, 0xf0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, vl1" + + - + input: + bytes: [ 0x40, 0xf0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, vl2" + + - + input: + bytes: [ 0x60, 0xf0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, vl3" + + - + input: + bytes: [ 0x80, 0xf0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, vl7" + + - + input: + bytes: [ 0x00, 0xf1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, vl8" + + - + input: + bytes: [ 0x20, 0xf1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, vl16" + + - + input: + bytes: [ 0x40, 0xf1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, vl32" + + - + input: + bytes: [ 0x60, 0xf1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, vl64" + + - + input: + bytes: [ 0x80, 0xf1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, #14" + + - + input: + bytes: [ 0xe0, 0xf1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, #15" + + - + input: + bytes: [ 0x00, 0xf2, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, #16" + + - + input: + bytes: [ 0x20, 0xf2, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, #17" + + - + input: + bytes: [ 0x40, 0xf2, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, #18" + + - + input: + bytes: [ 0x60, 0xf2, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, #19" + + - + input: + bytes: [ 0x80, 0xf2, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, #20" + + - + input: + bytes: [ 0xa0, 0xf2, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, #21" + + - + input: + bytes: [ 0xc0, 0xf2, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, #22" + + - + input: + bytes: [ 0xe0, 0xf2, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, #23" + + - + input: + bytes: [ 0x00, 0xf3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, #24" + + - + input: + bytes: [ 0x20, 0xf3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, #25" + + - + input: + bytes: [ 0x40, 0xf3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, #26" + + - + input: + bytes: [ 0x60, 0xf3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, #27" + + - + input: + bytes: [ 0x80, 0xf3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw z0.s" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc0, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw z0.s, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc0, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqincw z0.s, pow2" + + - + input: + bytes: [ 0xe0, 0xf3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, w0" + + - + input: + bytes: [ 0xe0, 0xf3, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf0, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, w0, pow2" + + - + input: + bytes: [ 0x00, 0xf0, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xc3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw z0.s" + + - + input: + bytes: [ 0xe0, 0xc3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw z0.s" + + - + input: + bytes: [ 0xe0, 0xc3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw z0.s" + + - + input: + bytes: [ 0xe0, 0xc3, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw z0.s, all, mul #16" + + - + input: + bytes: [ 0x00, 0xc0, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw z0.s, pow2" + + - + input: + bytes: [ 0x00, 0xc0, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw z0.s, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, pow2" + + - + input: + bytes: [ 0x20, 0xf0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, vl1" + + - + input: + bytes: [ 0x40, 0xf0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, vl2" + + - + input: + bytes: [ 0x60, 0xf0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, vl3" + + - + input: + bytes: [ 0x80, 0xf0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf0, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, vl7" + + - + input: + bytes: [ 0x00, 0xf1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, vl8" + + - + input: + bytes: [ 0x20, 0xf1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, vl16" + + - + input: + bytes: [ 0x40, 0xf1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, vl32" + + - + input: + bytes: [ 0x60, 0xf1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, vl64" + + - + input: + bytes: [ 0x80, 0xf1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, #14" + + - + input: + bytes: [ 0xe0, 0xf1, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, #15" + + - + input: + bytes: [ 0x00, 0xf2, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, #16" + + - + input: + bytes: [ 0x20, 0xf2, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, #17" + + - + input: + bytes: [ 0x40, 0xf2, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, #18" + + - + input: + bytes: [ 0x60, 0xf2, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, #19" + + - + input: + bytes: [ 0x80, 0xf2, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, #20" + + - + input: + bytes: [ 0xa0, 0xf2, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, #21" + + - + input: + bytes: [ 0xc0, 0xf2, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, #22" + + - + input: + bytes: [ 0xe0, 0xf2, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, #23" + + - + input: + bytes: [ 0x00, 0xf3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, #24" + + - + input: + bytes: [ 0x20, 0xf3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, #25" + + - + input: + bytes: [ 0x40, 0xf3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, #26" + + - + input: + bytes: [ 0x60, 0xf3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, #27" + + - + input: + bytes: [ 0x80, 0xf3, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc3, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw z0.s" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc0, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw z0.s, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc0, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqincw z0.s, pow2" diff --git a/tests/MC/AArch64/SVE/sqsub.s.yaml b/tests/MC/AArch64/SVE/sqsub.s.yaml new file mode 100644 index 0000000000..2a9c7da21f --- /dev/null +++ b/tests/MC/AArch64/SVE/sqsub.s.yaml @@ -0,0 +1,400 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x18, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqsub z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x18, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqsub z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x18, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqsub z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x18, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqsub z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0xc0, 0x26, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqsub z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x26, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqsub z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x66, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqsub z0.h, z0.h, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0x66, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqsub z0.h, z0.h, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0x66, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqsub z31.h, z31.h, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0x66, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqsub z31.h, z31.h, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xa6, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqsub z0.s, z0.s, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xa6, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqsub z0.s, z0.s, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xa6, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqsub z31.s, z31.s, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xa6, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqsub z31.s, z31.s, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xe6, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqsub z0.d, z0.d, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xe6, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqsub z0.d, z0.d, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xe6, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqsub z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xe6, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqsub z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xff, 0xe6, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sqsub z31.d, z31.d, #65280" + + - + input: + bytes: [ 0x00, 0x18, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x18, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x18, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x18, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0xc0, 0x26, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x26, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x66, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z0.h, z0.h, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0x66, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z0.h, z0.h, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0x66, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z31.h, z31.h, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0x66, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z31.h, z31.h, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xa6, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z0.s, z0.s, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xa6, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z0.s, z0.s, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xa6, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z31.s, z31.s, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xa6, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z31.s, z31.s, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xe6, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z0.d, z0.d, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xe6, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z0.d, z0.d, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xe6, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xe6, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xff, 0xe6, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z31.d, z31.d, #65280" diff --git a/tests/MC/AArch64/SVE/st1b-sve-only.s.yaml b/tests/MC/AArch64/SVE/st1b-sve-only.s.yaml new file mode 100644 index 0000000000..9fd4257f15 --- /dev/null +++ b/tests/MC/AArch64/SVE/st1b-sve-only.s.yaml @@ -0,0 +1,110 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x40, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.s }, p0, [x0, z0.s, uxtw]" + + - + input: + bytes: [ 0x00, 0xc0, 0x40, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.s }, p0, [x0, z0.s, sxtw]" + + - + input: + bytes: [ 0x00, 0x80, 0x00, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.d }, p0, [x0, z0.d, uxtw]" + + - + input: + bytes: [ 0x00, 0xc0, 0x00, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.d }, p0, [x0, z0.d, sxtw]" + + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.d }, p0, [x0, z0.d]" + + - + input: + bytes: [ 0xff, 0xbf, 0x7f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z31.s }, p7, [z31.s, #31]" + + - + input: + bytes: [ 0xff, 0xbf, 0x5f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z31.d }, p7, [z31.d, #31]" + + - + input: + bytes: [ 0x00, 0xbc, 0x60, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.s }, p7, [z0.s]" + + - + input: + bytes: [ 0x00, 0xbc, 0x60, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.s }, p7, [z0.s]" + + - + input: + bytes: [ 0x00, 0xbc, 0x40, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.d }, p7, [z0.d]" + + - + input: + bytes: [ 0x00, 0xbc, 0x40, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.d }, p7, [z0.d]" diff --git a/tests/MC/AArch64/SVE/st1b.s.yaml b/tests/MC/AArch64/SVE/st1b.s.yaml new file mode 100644 index 0000000000..8081f2ecb1 --- /dev/null +++ b/tests/MC/AArch64/SVE/st1b.s.yaml @@ -0,0 +1,400 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.b }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.h }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.s }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.b }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.h }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.s }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0xff, 0xff, 0x0f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z31.b }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x05, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z21.b }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0x2f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z31.h }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x25, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z21.h }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0x4f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z31.s }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x45, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z21.s }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0x6f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z31.d }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x65, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z21.d }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0x00, 0x40, 0x00, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.b }, p0, [x0, x0]" + + - + input: + bytes: [ 0x00, 0x40, 0x20, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.h }, p0, [x0, x0]" + + - + input: + bytes: [ 0x00, 0x40, 0x40, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.s }, p0, [x0, x0]" + + - + input: + bytes: [ 0x00, 0x40, 0x60, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1b { z0.d }, p0, [x0, x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z0.b }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z0.h }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z0.s }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z0.b }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z0.h }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z0.s }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0xff, 0xff, 0x0f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z31.b }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x05, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z21.b }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0x2f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z31.h }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x25, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z21.h }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0x4f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z31.s }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x45, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z21.s }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0x6f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z31.d }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x65, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z21.d }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0x00, 0x40, 0x00, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z0.b }, p0, [x0, x0]" + + - + input: + bytes: [ 0x00, 0x40, 0x20, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z0.h }, p0, [x0, x0]" + + - + input: + bytes: [ 0x00, 0x40, 0x40, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z0.s }, p0, [x0, x0]" + + - + input: + bytes: [ 0x00, 0x40, 0x60, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1b { z0.d }, p0, [x0, x0]" diff --git a/tests/MC/AArch64/SVE/st1d-sve-only.s.yaml b/tests/MC/AArch64/SVE/st1d-sve-only.s.yaml new file mode 100644 index 0000000000..13b16a9294 --- /dev/null +++ b/tests/MC/AArch64/SVE/st1d-sve-only.s.yaml @@ -0,0 +1,90 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x80, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1d { z0.d }, p0, [x0, z0.d, uxtw]" + + - + input: + bytes: [ 0x00, 0xc0, 0x80, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1d { z0.d }, p0, [x0, z0.d, sxtw]" + + - + input: + bytes: [ 0x00, 0x80, 0xa0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1d { z0.d }, p0, [x0, z0.d, uxtw #3]" + + - + input: + bytes: [ 0x00, 0xc0, 0xa0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1d { z0.d }, p0, [x0, z0.d, sxtw #3]" + + - + input: + bytes: [ 0x00, 0xa0, 0x80, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1d { z0.d }, p0, [x0, z0.d]" + + - + input: + bytes: [ 0x00, 0xa0, 0xa0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1d { z0.d }, p0, [x0, z0.d, lsl #3]" + + - + input: + bytes: [ 0xff, 0xbf, 0xdf, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1d { z31.d }, p7, [z31.d, #248]" + + - + input: + bytes: [ 0x00, 0xbc, 0xc0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1d { z0.d }, p7, [z0.d]" + + - + input: + bytes: [ 0x00, 0xbc, 0xc0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1d { z0.d }, p7, [z0.d]" diff --git a/tests/MC/AArch64/SVE/st1d.s.yaml b/tests/MC/AArch64/SVE/st1d.s.yaml new file mode 100644 index 0000000000..5e99624e84 --- /dev/null +++ b/tests/MC/AArch64/SVE/st1d.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0xe0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1d { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0xe0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1d { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0xff, 0xff, 0xef, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1d { z31.d }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xe5, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1d { z21.d }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0x00, 0x40, 0xe0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1d { z0.d }, p0, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0xe0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0xe0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0xff, 0xff, 0xef, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d { z31.d }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xe5, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d { z21.d }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0x00, 0x40, 0xe0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1d { z0.d }, p0, [x0, x0, lsl #3]" diff --git a/tests/MC/AArch64/SVE/st1h-sve-only.s.yaml b/tests/MC/AArch64/SVE/st1h-sve-only.s.yaml new file mode 100644 index 0000000000..523c4f6b4c --- /dev/null +++ b/tests/MC/AArch64/SVE/st1h-sve-only.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0xc0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.s }, p0, [x0, z0.s, uxtw]" + + - + input: + bytes: [ 0x00, 0xc0, 0xc0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.s }, p0, [x0, z0.s, sxtw]" + + - + input: + bytes: [ 0x00, 0x80, 0x80, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.d }, p0, [x0, z0.d, uxtw]" + + - + input: + bytes: [ 0x00, 0xc0, 0x80, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.d }, p0, [x0, z0.d, sxtw]" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.s }, p0, [x0, z0.s, uxtw #1]" + + - + input: + bytes: [ 0x00, 0xc0, 0xe0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.s }, p0, [x0, z0.s, sxtw #1]" + + - + input: + bytes: [ 0x00, 0x80, 0xa0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.d }, p0, [x0, z0.d, uxtw #1]" + + - + input: + bytes: [ 0x00, 0xc0, 0xa0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.d }, p0, [x0, z0.d, sxtw #1]" + + - + input: + bytes: [ 0x00, 0xa0, 0x80, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.d }, p0, [x0, z0.d]" + + - + input: + bytes: [ 0x00, 0xa0, 0xa0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.d }, p0, [x0, z0.d, lsl #1]" + + - + input: + bytes: [ 0xff, 0xbf, 0xff, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z31.s }, p7, [z31.s, #62]" + + - + input: + bytes: [ 0xff, 0xbf, 0xdf, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z31.d }, p7, [z31.d, #62]" + + - + input: + bytes: [ 0x00, 0xbc, 0xe0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.s }, p7, [z0.s]" + + - + input: + bytes: [ 0x00, 0xbc, 0xe0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.s }, p7, [z0.s]" + + - + input: + bytes: [ 0x00, 0xbc, 0xc0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.d }, p7, [z0.d]" + + - + input: + bytes: [ 0x00, 0xbc, 0xc0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.d }, p7, [z0.d]" diff --git a/tests/MC/AArch64/SVE/st1h.s.yaml b/tests/MC/AArch64/SVE/st1h.s.yaml new file mode 100644 index 0000000000..09594b6f3a --- /dev/null +++ b/tests/MC/AArch64/SVE/st1h.s.yaml @@ -0,0 +1,300 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0xa0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.h }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0xc0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.s }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0xe0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0xa0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.h }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0xc0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.s }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0xe0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0xff, 0xff, 0xaf, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z31.h }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xa5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z21.h }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0xcf, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z31.s }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xc5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z21.s }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xe5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z21.d }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0xef, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z31.d }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x00, 0x40, 0xa0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.h }, p0, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x00, 0x40, 0xc0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.s }, p0, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x00, 0x40, 0xe0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1h { z0.d }, p0, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x00, 0xe0, 0xa0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h { z0.h }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0xc0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h { z0.s }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0xe0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0xa0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h { z0.h }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0xc0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h { z0.s }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0xe0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0xff, 0xff, 0xaf, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h { z31.h }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xa5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h { z21.h }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0xcf, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h { z31.s }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xc5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h { z21.s }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xe5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h { z21.d }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0xef, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h { z31.d }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x00, 0x40, 0xa0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h { z0.h }, p0, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x00, 0x40, 0xc0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h { z0.s }, p0, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x00, 0x40, 0xe0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1h { z0.d }, p0, [x0, x0, lsl #1]" diff --git a/tests/MC/AArch64/SVE/st1w-sve-only.s.yaml b/tests/MC/AArch64/SVE/st1w-sve-only.s.yaml new file mode 100644 index 0000000000..4f1a8cbbb9 --- /dev/null +++ b/tests/MC/AArch64/SVE/st1w-sve-only.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x40, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.s }, p0, [x0, z0.s, uxtw]" + + - + input: + bytes: [ 0x00, 0xc0, 0x40, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.s }, p0, [x0, z0.s, sxtw]" + + - + input: + bytes: [ 0x00, 0x80, 0x00, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.d }, p0, [x0, z0.d, uxtw]" + + - + input: + bytes: [ 0x00, 0xc0, 0x00, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.d }, p0, [x0, z0.d, sxtw]" + + - + input: + bytes: [ 0x00, 0x80, 0x60, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.s }, p0, [x0, z0.s, uxtw #2]" + + - + input: + bytes: [ 0x00, 0xc0, 0x60, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.s }, p0, [x0, z0.s, sxtw #2]" + + - + input: + bytes: [ 0x00, 0x80, 0x20, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.d }, p0, [x0, z0.d, uxtw #2]" + + - + input: + bytes: [ 0x00, 0xc0, 0x20, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.d }, p0, [x0, z0.d, sxtw #2]" + + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.d }, p0, [x0, z0.d]" + + - + input: + bytes: [ 0x00, 0xa0, 0x20, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.d }, p0, [x0, z0.d, lsl #2]" + + - + input: + bytes: [ 0xff, 0xbf, 0x7f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z31.s }, p7, [z31.s, #124]" + + - + input: + bytes: [ 0xff, 0xbf, 0x5f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z31.d }, p7, [z31.d, #124]" + + - + input: + bytes: [ 0x00, 0xbc, 0x60, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.s }, p7, [z0.s]" + + - + input: + bytes: [ 0x00, 0xbc, 0x60, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.s }, p7, [z0.s]" + + - + input: + bytes: [ 0x00, 0xbc, 0x40, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.d }, p7, [z0.d]" + + - + input: + bytes: [ 0x00, 0xbc, 0x40, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.d }, p7, [z0.d]" diff --git a/tests/MC/AArch64/SVE/st1w.s.yaml b/tests/MC/AArch64/SVE/st1w.s.yaml new file mode 100644 index 0000000000..f9eba6447c --- /dev/null +++ b/tests/MC/AArch64/SVE/st1w.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.s }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.s }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0xff, 0xff, 0x4f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z31.s }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x45, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z21.s }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0x6f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z31.d }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x65, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z21.d }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0x00, 0x40, 0x40, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.s }, p0, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x00, 0x40, 0x60, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st1w { z0.d }, p0, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w { z0.s }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w { z0.s }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0xff, 0xff, 0x4f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w { z31.s }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x45, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w { z21.s }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0x6f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w { z31.d }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x65, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w { z21.d }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0x00, 0x40, 0x40, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w { z0.s }, p0, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x00, 0x40, 0x60, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st1w { z0.d }, p0, [x0, x0, lsl #2]" diff --git a/tests/MC/AArch64/SVE/st2b.s.yaml b/tests/MC/AArch64/SVE/st2b.s.yaml new file mode 100644 index 0000000000..41cd7fa59b --- /dev/null +++ b/tests/MC/AArch64/SVE/st2b.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0x20, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2b { z0.b, z1.b }, p0, [x0, x0]" + + - + input: + bytes: [ 0x25, 0x6e, 0x30, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2b { z5.b, z6.b }, p3, [x17, x16]" + + - + input: + bytes: [ 0x00, 0xe0, 0x30, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2b { z0.b, z1.b }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x38, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2b { z23.b, z24.b }, p3, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x35, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2b { z21.b, z22.b }, p5, [x10, #10, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0x20, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2b { z0.b, z1.b }, p0, [x0, x0]" + + - + input: + bytes: [ 0x25, 0x6e, 0x30, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2b { z5.b, z6.b }, p3, [x17, x16]" + + - + input: + bytes: [ 0x00, 0xe0, 0x30, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2b { z0.b, z1.b }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x38, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2b { z23.b, z24.b }, p3, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x35, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2b { z21.b, z22.b }, p5, [x10, #10, mul vl]" diff --git a/tests/MC/AArch64/SVE/st2d.s.yaml b/tests/MC/AArch64/SVE/st2d.s.yaml new file mode 100644 index 0000000000..db3dd9c05d --- /dev/null +++ b/tests/MC/AArch64/SVE/st2d.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0xa0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2d { z0.d, z1.d }, p0, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x25, 0x6e, 0xb0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2d { z5.d, z6.d }, p3, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0xb0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2d { z0.d, z1.d }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xb8, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2d { z23.d, z24.d }, p3, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xb5, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2d { z21.d, z22.d }, p5, [x10, #10, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0xa0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2d { z0.d, z1.d }, p0, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x25, 0x6e, 0xb0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2d { z5.d, z6.d }, p3, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0xb0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2d { z0.d, z1.d }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xb8, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2d { z23.d, z24.d }, p3, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xb5, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2d { z21.d, z22.d }, p5, [x10, #10, mul vl]" diff --git a/tests/MC/AArch64/SVE/st2h.s.yaml b/tests/MC/AArch64/SVE/st2h.s.yaml new file mode 100644 index 0000000000..a50a3d3965 --- /dev/null +++ b/tests/MC/AArch64/SVE/st2h.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0xa0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2h { z0.h, z1.h }, p0, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x25, 0x6e, 0xb0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2h { z5.h, z6.h }, p3, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x00, 0xe0, 0xb0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2h { z0.h, z1.h }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xb8, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2h { z23.h, z24.h }, p3, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xb5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2h { z21.h, z22.h }, p5, [x10, #10, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0xa0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2h { z0.h, z1.h }, p0, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x25, 0x6e, 0xb0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2h { z5.h, z6.h }, p3, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x00, 0xe0, 0xb0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2h { z0.h, z1.h }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xb8, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2h { z23.h, z24.h }, p3, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xb5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2h { z21.h, z22.h }, p5, [x10, #10, mul vl]" diff --git a/tests/MC/AArch64/SVE/st2w.s.yaml b/tests/MC/AArch64/SVE/st2w.s.yaml new file mode 100644 index 0000000000..86395a0c9b --- /dev/null +++ b/tests/MC/AArch64/SVE/st2w.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0x20, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2w { z0.s, z1.s }, p0, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x25, 0x6e, 0x30, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2w { z5.s, z6.s }, p3, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x00, 0xe0, 0x30, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2w { z0.s, z1.s }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x38, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2w { z23.s, z24.s }, p3, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x35, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st2w { z21.s, z22.s }, p5, [x10, #10, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0x20, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2w { z0.s, z1.s }, p0, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x25, 0x6e, 0x30, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2w { z5.s, z6.s }, p3, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x00, 0xe0, 0x30, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2w { z0.s, z1.s }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x38, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2w { z23.s, z24.s }, p3, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x35, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st2w { z21.s, z22.s }, p5, [x10, #10, mul vl]" diff --git a/tests/MC/AArch64/SVE/st3b.s.yaml b/tests/MC/AArch64/SVE/st3b.s.yaml new file mode 100644 index 0000000000..f23d2d27ae --- /dev/null +++ b/tests/MC/AArch64/SVE/st3b.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0x40, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3b { z0.b - z2.b }, p0, [x0, x0]" + + - + input: + bytes: [ 0x25, 0x6e, 0x50, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3b { z5.b - z7.b }, p3, [x17, x16]" + + - + input: + bytes: [ 0x00, 0xe0, 0x50, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3b { z0.b - z2.b }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x58, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3b { z23.b - z25.b }, p3, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x55, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3b { z21.b - z23.b }, p5, [x10, #15, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0x40, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3b { z0.b - z2.b }, p0, [x0, x0]" + + - + input: + bytes: [ 0x25, 0x6e, 0x50, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3b { z5.b - z7.b }, p3, [x17, x16]" + + - + input: + bytes: [ 0x00, 0xe0, 0x50, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3b { z0.b - z2.b }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x58, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3b { z23.b - z25.b }, p3, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x55, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3b { z21.b - z23.b }, p5, [x10, #15, mul vl]" diff --git a/tests/MC/AArch64/SVE/st3d.s.yaml b/tests/MC/AArch64/SVE/st3d.s.yaml new file mode 100644 index 0000000000..d45593cabb --- /dev/null +++ b/tests/MC/AArch64/SVE/st3d.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0xc0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3d { z0.d - z2.d }, p0, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x25, 0x6e, 0xd0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3d { z5.d - z7.d }, p3, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0xd0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3d { z0.d - z2.d }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xd8, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3d { z23.d - z25.d }, p3, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xd5, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3d { z21.d - z23.d }, p5, [x10, #15, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0xc0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3d { z0.d - z2.d }, p0, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x25, 0x6e, 0xd0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3d { z5.d - z7.d }, p3, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0xd0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3d { z0.d - z2.d }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xd8, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3d { z23.d - z25.d }, p3, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xd5, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3d { z21.d - z23.d }, p5, [x10, #15, mul vl]" diff --git a/tests/MC/AArch64/SVE/st3h.s.yaml b/tests/MC/AArch64/SVE/st3h.s.yaml new file mode 100644 index 0000000000..d642f0c534 --- /dev/null +++ b/tests/MC/AArch64/SVE/st3h.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0xc0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3h { z0.h - z2.h }, p0, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x25, 0x6e, 0xd0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3h { z5.h - z7.h }, p3, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x00, 0xe0, 0xd0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3h { z0.h - z2.h }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xd8, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3h { z23.h - z25.h }, p3, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xd5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3h { z21.h - z23.h }, p5, [x10, #15, mul vl]" + + - + input: + bytes: [ 0x5f, 0xf5, 0xd5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3h { z31.h, z0.h, z1.h }, p5, [x10, #15, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0xc0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3h { z0.h - z2.h }, p0, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x25, 0x6e, 0xd0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3h { z5.h - z7.h }, p3, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x00, 0xe0, 0xd0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3h { z0.h - z2.h }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xd8, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3h { z23.h - z25.h }, p3, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xd5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3h { z21.h - z23.h }, p5, [x10, #15, mul vl]" + + - + input: + bytes: [ 0x5f, 0xf5, 0xd5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3h { z31.h, z0.h, z1.h }, p5, [x10, #15, mul vl]" diff --git a/tests/MC/AArch64/SVE/st3w.s.yaml b/tests/MC/AArch64/SVE/st3w.s.yaml new file mode 100644 index 0000000000..35203ba088 --- /dev/null +++ b/tests/MC/AArch64/SVE/st3w.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0x40, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3w { z0.s - z2.s }, p0, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x25, 0x6e, 0x50, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3w { z5.s - z7.s }, p3, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x00, 0xe0, 0x50, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3w { z0.s - z2.s }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x58, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3w { z23.s - z25.s }, p3, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x55, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st3w { z21.s - z23.s }, p5, [x10, #15, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0x40, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3w { z0.s - z2.s }, p0, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x25, 0x6e, 0x50, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3w { z5.s - z7.s }, p3, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x00, 0xe0, 0x50, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3w { z0.s - z2.s }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x58, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3w { z23.s - z25.s }, p3, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x55, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st3w { z21.s - z23.s }, p5, [x10, #15, mul vl]" diff --git a/tests/MC/AArch64/SVE/st4b.s.yaml b/tests/MC/AArch64/SVE/st4b.s.yaml new file mode 100644 index 0000000000..2afb6cffff --- /dev/null +++ b/tests/MC/AArch64/SVE/st4b.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0x60, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4b { z0.b - z3.b }, p0, [x0, x0]" + + - + input: + bytes: [ 0x25, 0x6e, 0x70, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4b { z5.b - z8.b }, p3, [x17, x16]" + + - + input: + bytes: [ 0x00, 0xe0, 0x70, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4b { z0.b - z3.b }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x78, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4b { z23.b - z26.b }, p3, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x75, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4b { z21.b - z24.b }, p5, [x10, #20, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4b { z0.b - z3.b }, p0, [x0, x0]" + + - + input: + bytes: [ 0x25, 0x6e, 0x70, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4b { z5.b - z8.b }, p3, [x17, x16]" + + - + input: + bytes: [ 0x00, 0xe0, 0x70, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4b { z0.b - z3.b }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x78, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4b { z23.b - z26.b }, p3, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x75, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4b { z21.b - z24.b }, p5, [x10, #20, mul vl]" diff --git a/tests/MC/AArch64/SVE/st4d.s.yaml b/tests/MC/AArch64/SVE/st4d.s.yaml new file mode 100644 index 0000000000..a2378dbdf8 --- /dev/null +++ b/tests/MC/AArch64/SVE/st4d.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0xe0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4d { z0.d - z3.d }, p0, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x25, 0x6e, 0xf0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4d { z5.d - z8.d }, p3, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0xf0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4d { z0.d - z3.d }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xf8, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4d { z23.d - z26.d }, p3, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xf5, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4d { z21.d - z24.d }, p5, [x10, #20, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0xe0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4d { z0.d - z3.d }, p0, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x25, 0x6e, 0xf0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4d { z5.d - z8.d }, p3, [x17, x16, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0xf0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4d { z0.d - z3.d }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xf8, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4d { z23.d - z26.d }, p3, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xf5, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4d { z21.d - z24.d }, p5, [x10, #20, mul vl]" diff --git a/tests/MC/AArch64/SVE/st4h.s.yaml b/tests/MC/AArch64/SVE/st4h.s.yaml new file mode 100644 index 0000000000..ad2737dbbb --- /dev/null +++ b/tests/MC/AArch64/SVE/st4h.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0xe0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4h { z0.h - z3.h }, p0, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x25, 0x6e, 0xf0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4h { z5.h - z8.h }, p3, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x00, 0xe0, 0xf0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4h { z0.h - z3.h }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xf8, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4h { z23.h - z26.h }, p3, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xf5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4h { z21.h - z24.h }, p5, [x10, #20, mul vl]" + + - + input: + bytes: [ 0x5d, 0xf5, 0xf5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4h { z29.h, z30.h, z31.h, z0.h }, p5, [x10, #20, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0xe0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4h { z0.h - z3.h }, p0, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x25, 0x6e, 0xf0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4h { z5.h - z8.h }, p3, [x17, x16, lsl #1]" + + - + input: + bytes: [ 0x00, 0xe0, 0xf0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4h { z0.h - z3.h }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0xf8, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4h { z23.h - z26.h }, p3, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0xf5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4h { z21.h - z24.h }, p5, [x10, #20, mul vl]" + + - + input: + bytes: [ 0x5d, 0xf5, 0xf5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4h { z29.h, z30.h, z31.h, z0.h }, p5, [x10, #20, mul vl]" diff --git a/tests/MC/AArch64/SVE/st4w.s.yaml b/tests/MC/AArch64/SVE/st4w.s.yaml new file mode 100644 index 0000000000..d69426834a --- /dev/null +++ b/tests/MC/AArch64/SVE/st4w.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0x60, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4w { z0.s - z3.s }, p0, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x25, 0x6e, 0x70, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4w { z5.s - z8.s }, p3, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x00, 0xe0, 0x70, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4w { z0.s - z3.s }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x78, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4w { z23.s - z26.s }, p3, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x75, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "st4w { z21.s - z24.s }, p5, [x10, #20, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4w { z0.s - z3.s }, p0, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x25, 0x6e, 0x70, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4w { z5.s - z8.s }, p3, [x17, x16, lsl #2]" + + - + input: + bytes: [ 0x00, 0xe0, 0x70, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4w { z0.s - z3.s }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x78, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4w { z23.s - z26.s }, p3, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x75, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "st4w { z21.s - z24.s }, p5, [x10, #20, mul vl]" diff --git a/tests/MC/AArch64/SVE/stnt1b.s.yaml b/tests/MC/AArch64/SVE/stnt1b.s.yaml new file mode 100644 index 0000000000..f76be54df8 --- /dev/null +++ b/tests/MC/AArch64/SVE/stnt1b.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x10, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1b { z0.b }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x10, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1b { z0.b }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x18, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1b { z23.b }, p3, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x17, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1b { z21.b }, p5, [x10, #7, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0x00, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1b { z0.b }, p0, [x0, x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x10, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1b { z0.b }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x10, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1b { z0.b }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x18, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1b { z23.b }, p3, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x17, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1b { z21.b }, p5, [x10, #7, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0x00, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1b { z0.b }, p0, [x0, x0]" diff --git a/tests/MC/AArch64/SVE/stnt1d.s.yaml b/tests/MC/AArch64/SVE/stnt1d.s.yaml new file mode 100644 index 0000000000..d9b11f6162 --- /dev/null +++ b/tests/MC/AArch64/SVE/stnt1d.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x90, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x90, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x98, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1d { z23.d }, p3, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x97, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1d { z21.d }, p5, [x10, #7, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0x80, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d }, p0, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0x90, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x90, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x98, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1d { z23.d }, p3, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x97, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1d { z21.d }, p5, [x10, #7, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0x80, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d }, p0, [x0, x0, lsl #3]" diff --git a/tests/MC/AArch64/SVE/stnt1h.s.yaml b/tests/MC/AArch64/SVE/stnt1h.s.yaml new file mode 100644 index 0000000000..685b0fc48b --- /dev/null +++ b/tests/MC/AArch64/SVE/stnt1h.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x90, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1h { z0.h }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x90, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1h { z0.h }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x98, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1h { z23.h }, p3, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x97, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1h { z21.h }, p5, [x10, #7, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0x80, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1h { z0.h }, p0, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x00, 0xe0, 0x90, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1h { z0.h }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x90, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1h { z0.h }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x98, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1h { z23.h }, p3, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x97, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1h { z21.h }, p5, [x10, #7, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0x80, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1h { z0.h }, p0, [x0, x0, lsl #1]" diff --git a/tests/MC/AArch64/SVE/stnt1w.s.yaml b/tests/MC/AArch64/SVE/stnt1w.s.yaml new file mode 100644 index 0000000000..89c111e9c8 --- /dev/null +++ b/tests/MC/AArch64/SVE/stnt1w.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x10, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x10, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x18, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1w { z23.s }, p3, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x17, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1w { z21.s }, p5, [x10, #7, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0x00, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s }, p0, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x00, 0xe0, 0x10, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x10, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s }, p0, [x0]" + + - + input: + bytes: [ 0xb7, 0xed, 0x18, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1w { z23.s }, p3, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0x55, 0xf5, 0x17, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1w { z21.s }, p5, [x10, #7, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0x00, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s }, p0, [x0, x0, lsl #2]" diff --git a/tests/MC/AArch64/SVE/str.s.yaml b/tests/MC/AArch64/SVE/str.s.yaml new file mode 100644 index 0000000000..069ccca0a8 --- /dev/null +++ b/tests/MC/AArch64/SVE/str.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0x80, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "str z0, [x0]" + + - + input: + bytes: [ 0x55, 0x41, 0xa0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "str z21, [x10, #-256, mul vl]" + + - + input: + bytes: [ 0xff, 0x5f, 0x9f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "str z31, [sp, #255, mul vl]" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "str p0, [x0]" + + - + input: + bytes: [ 0xef, 0x03, 0xa0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "str p15, [sp, #-256, mul vl]" + + - + input: + bytes: [ 0x45, 0x1d, 0x9f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "str p5, [x10, #255, mul vl]" + + - + input: + bytes: [ 0x00, 0x40, 0x80, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str z0, [x0]" + + - + input: + bytes: [ 0x55, 0x41, 0xa0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str z21, [x10, #-256, mul vl]" + + - + input: + bytes: [ 0xff, 0x5f, 0x9f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str z31, [sp, #255, mul vl]" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str p0, [x0]" + + - + input: + bytes: [ 0xef, 0x03, 0xa0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str p15, [sp, #-256, mul vl]" + + - + input: + bytes: [ 0x45, 0x1d, 0x9f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "str p5, [x10, #255, mul vl]" diff --git a/tests/MC/AArch64/SVE/sub.s.yaml b/tests/MC/AArch64/SVE/sub.s.yaml new file mode 100644 index 0000000000..03c2334722 --- /dev/null +++ b/tests/MC/AArch64/SVE/sub.s.yaml @@ -0,0 +1,1040 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x04, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x05, 0x35, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z21.b, z10.b, z21.b" + + - + input: + bytes: [ 0xff, 0x1f, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0xb7, 0x0d, 0x41, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xff, 0x07, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0x55, 0x05, 0x75, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xff, 0x07, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0x04, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0xb7, 0x0d, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z23.s, p3/m, z23.s, z13.s" + + - + input: + bytes: [ 0xb7, 0x05, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z23.b, z13.b, z8.b" + + - + input: + bytes: [ 0x55, 0x05, 0xf5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z21.d, z10.d, z21.d" + + - + input: + bytes: [ 0x55, 0x05, 0xb5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z21.s, z10.s, z21.s" + + - + input: + bytes: [ 0x55, 0x15, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z21.s, p5/m, z21.s, z10.s" + + - + input: + bytes: [ 0xff, 0x1f, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0x00, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z0.d, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x04, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0xb7, 0x05, 0xe8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xb7, 0x0d, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z23.d, p3/m, z23.d, z13.d" + + - + input: + bytes: [ 0xb7, 0x05, 0xa8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0xff, 0x1f, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0x00, 0x41, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0xff, 0x07, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0xff, 0x1f, 0x41, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xb7, 0x05, 0x68, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0x55, 0x15, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z21.b, p5/m, z21.b, z10.b" + + - + input: + bytes: [ 0x55, 0x15, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z21.d, p5/m, z21.d, z10.d" + + - + input: + bytes: [ 0x00, 0x04, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0xff, 0x07, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z0.b, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x00, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z0.s, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x55, 0x15, 0x41, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z21.h, p5/m, z21.h, z10.h" + + - + input: + bytes: [ 0xb7, 0x0d, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z23.b, p3/m, z23.b, z13.b" + + - + input: + bytes: [ 0x00, 0xc0, 0x21, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x21, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x61, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z0.h, z0.h, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0x61, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z0.h, z0.h, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0x61, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z31.h, z31.h, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0x61, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z31.h, z31.h, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xa1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z0.s, z0.s, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xa1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z0.s, z0.s, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xa1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z31.s, z31.s, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xa1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z31.s, z31.s, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xe1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z0.d, z0.d, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xe1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z0.d, z0.d, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xe1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xe1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xd7, 0x2f, 0x10, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z23.b, p3/z, z30.b" + + - + input: + bytes: [ 0xb7, 0x0d, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z23.b, p3/m, z23.b, z13.b" + + - + input: + bytes: [ 0xd7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z23, z30" + + - + input: + bytes: [ 0xb7, 0x0d, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z23.b, p3/m, z23.b, z13.b" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xff, 0xe1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sub z31.d, z31.d, #65280" + + - + input: + bytes: [ 0x00, 0x04, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x05, 0x35, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z21.b, z10.b, z21.b" + + - + input: + bytes: [ 0xff, 0x1f, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0xb7, 0x0d, 0x41, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xff, 0x07, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0x55, 0x05, 0x75, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xff, 0x07, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0x04, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0xb7, 0x0d, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z23.s, p3/m, z23.s, z13.s" + + - + input: + bytes: [ 0xb7, 0x05, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z23.b, z13.b, z8.b" + + - + input: + bytes: [ 0x55, 0x05, 0xf5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z21.d, z10.d, z21.d" + + - + input: + bytes: [ 0x55, 0x05, 0xb5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z21.s, z10.s, z21.s" + + - + input: + bytes: [ 0x55, 0x15, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z21.s, p5/m, z21.s, z10.s" + + - + input: + bytes: [ 0xff, 0x1f, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0x00, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z0.d, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0x04, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0xb7, 0x05, 0xe8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xb7, 0x0d, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z23.d, p3/m, z23.d, z13.d" + + - + input: + bytes: [ 0xb7, 0x05, 0xa8, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0xff, 0x1f, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0x00, 0x41, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0xff, 0x07, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0xff, 0x1f, 0x41, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xb7, 0x05, 0x68, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0x55, 0x15, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z21.b, p5/m, z21.b, z10.b" + + - + input: + bytes: [ 0x55, 0x15, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z21.d, p5/m, z21.d, z10.d" + + - + input: + bytes: [ 0x00, 0x04, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0xff, 0x07, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z0.b, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x00, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z0.s, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x55, 0x15, 0x41, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z21.h, p5/m, z21.h, z10.h" + + - + input: + bytes: [ 0xb7, 0x0d, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z23.b, p3/m, z23.b, z13.b" + + - + input: + bytes: [ 0x00, 0xc0, 0x21, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x21, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x61, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z0.h, z0.h, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0x61, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z0.h, z0.h, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0x61, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z31.h, z31.h, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0x61, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z31.h, z31.h, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xa1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z0.s, z0.s, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xa1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z0.s, z0.s, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xa1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z31.s, z31.s, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xa1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z31.s, z31.s, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xe1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z0.d, z0.d, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xe1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z0.d, z0.d, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xe1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xe1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xd7, 0x2f, 0x10, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z23.b, p3/z, z30.b" + + - + input: + bytes: [ 0xb7, 0x0d, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z23.b, p3/m, z23.b, z13.b" + + - + input: + bytes: [ 0xd7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z23, z30" + + - + input: + bytes: [ 0xb7, 0x0d, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z23.b, p3/m, z23.b, z13.b" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xff, 0xe1, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sub z31.d, z31.d, #65280" diff --git a/tests/MC/AArch64/SVE/subr.s.yaml b/tests/MC/AArch64/SVE/subr.s.yaml new file mode 100644 index 0000000000..af0727116a --- /dev/null +++ b/tests/MC/AArch64/SVE/subr.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x03, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z0.b, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x00, 0x43, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x00, 0x83, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z0.s, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x00, 0xc3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z0.d, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0xc0, 0x23, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x23, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x63, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z0.h, z0.h, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0x63, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z0.h, z0.h, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0x63, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z31.h, z31.h, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0x63, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z31.h, z31.h, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xa3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z0.s, z0.s, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xa3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z0.s, z0.s, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xa3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z31.s, z31.s, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xa3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z31.s, z31.s, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xe3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z0.d, z0.d, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xe3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z0.d, z0.d, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xe3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xe3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0x00, 0xc3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z5.d, p0/m, z5.d, z0.d" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0x00, 0xc3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z5.d, p0/m, z5.d, z0.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xff, 0xe3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "subr z31.d, z31.d, #65280" + + - + input: + bytes: [ 0x00, 0x00, 0x03, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z0.b, p0/m, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x00, 0x43, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x00, 0x83, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z0.s, p0/m, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x00, 0xc3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z0.d, p0/m, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0xc0, 0x23, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x23, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x63, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z0.h, z0.h, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0x63, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z0.h, z0.h, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0x63, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z31.h, z31.h, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0x63, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z31.h, z31.h, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xa3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z0.s, z0.s, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xa3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z0.s, z0.s, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xa3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z31.s, z31.s, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xa3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z31.s, z31.s, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xe3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z0.d, z0.d, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xe3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z0.d, z0.d, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xe3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xe3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0x00, 0xc3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z5.d, p0/m, z5.d, z0.d" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0x00, 0xc3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z5.d, p0/m, z5.d, z0.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xff, 0xe3, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subr z31.d, z31.d, #65280" diff --git a/tests/MC/AArch64/SVE/sunpkhi.s.yaml b/tests/MC/AArch64/SVE/sunpkhi.s.yaml new file mode 100644 index 0000000000..c11b23cb33 --- /dev/null +++ b/tests/MC/AArch64/SVE/sunpkhi.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x3b, 0x71, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sunpkhi z31.h, z31.b" + + - + input: + bytes: [ 0xff, 0x3b, 0xb1, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sunpkhi z31.s, z31.h" + + - + input: + bytes: [ 0xff, 0x3b, 0xf1, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sunpkhi z31.d, z31.s" + + - + input: + bytes: [ 0xff, 0x3b, 0x71, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sunpkhi z31.h, z31.b" + + - + input: + bytes: [ 0xff, 0x3b, 0xb1, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sunpkhi z31.s, z31.h" + + - + input: + bytes: [ 0xff, 0x3b, 0xf1, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sunpkhi z31.d, z31.s" diff --git a/tests/MC/AArch64/SVE/sunpklo.s.yaml b/tests/MC/AArch64/SVE/sunpklo.s.yaml new file mode 100644 index 0000000000..15c56f8c21 --- /dev/null +++ b/tests/MC/AArch64/SVE/sunpklo.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x3b, 0x70, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sunpklo z31.h, z31.b" + + - + input: + bytes: [ 0xff, 0x3b, 0xb0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sunpklo z31.s, z31.h" + + - + input: + bytes: [ 0xff, 0x3b, 0xf0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sunpklo z31.d, z31.s" + + - + input: + bytes: [ 0xff, 0x3b, 0x70, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sunpklo z31.h, z31.b" + + - + input: + bytes: [ 0xff, 0x3b, 0xb0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sunpklo z31.s, z31.h" + + - + input: + bytes: [ 0xff, 0x3b, 0xf0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sunpklo z31.d, z31.s" diff --git a/tests/MC/AArch64/SVE/sxtb.s.yaml b/tests/MC/AArch64/SVE/sxtb.s.yaml new file mode 100644 index 0000000000..201899f034 --- /dev/null +++ b/tests/MC/AArch64/SVE/sxtb.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x50, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sxtb z0.h, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sxtb z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sxtb z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x50, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sxtb z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sxtb z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sxtb z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sxtb z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sxtb z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x50, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sxtb z0.h, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sxtb z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sxtb z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x50, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sxtb z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sxtb z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sxtb z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sxtb z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sxtb z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/sxth.s.yaml b/tests/MC/AArch64/SVE/sxth.s.yaml new file mode 100644 index 0000000000..d4513c9469 --- /dev/null +++ b/tests/MC/AArch64/SVE/sxth.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x92, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sxth z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sxth z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x92, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sxth z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xd2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sxth z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sxth z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sxth z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x92, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sxth z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sxth z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x92, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sxth z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xd2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sxth z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sxth z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd2, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sxth z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/sxtw.s.yaml b/tests/MC/AArch64/SVE/sxtw.s.yaml new file mode 100644 index 0000000000..299eea6c6a --- /dev/null +++ b/tests/MC/AArch64/SVE/sxtw.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sxtw z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xff, 0xbf, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sxtw z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sxtw z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "sxtw z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0x00, 0xa0, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sxtw z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xff, 0xbf, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sxtw z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sxtw z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd4, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sxtw z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/system-regs.s.yaml b/tests/MC/AArch64/SVE/system-regs.s.yaml new file mode 100644 index 0000000000..8f43ec0247 --- /dev/null +++ b/tests/MC/AArch64/SVE/system-regs.s.yaml @@ -0,0 +1,90 @@ +test_cases: + - + input: + bytes: [ 0x83, 0x04, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mrs x3, ID_AA64ZFR0_EL1" + + - + input: + bytes: [ 0x03, 0x12, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mrs x3, ZCR_EL1" + + - + input: + bytes: [ 0x03, 0x12, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mrs x3, ZCR_EL2" + + - + input: + bytes: [ 0x03, 0x12, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mrs x3, ZCR_EL3" + + - + input: + bytes: [ 0x03, 0x12, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "mrs x3, ZCR_EL12" + + - + input: + bytes: [ 0x03, 0x12, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "msr ZCR_EL1, x3" + + - + input: + bytes: [ 0x03, 0x12, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "msr ZCR_EL2, x3" + + - + input: + bytes: [ 0x03, 0x12, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "msr ZCR_EL3, x3" + + - + input: + bytes: [ 0x03, 0x12, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "msr ZCR_EL12, x3" diff --git a/tests/MC/AArch64/SVE/tbl.s.yaml b/tests/MC/AArch64/SVE/tbl.s.yaml new file mode 100644 index 0000000000..fab13ece2e --- /dev/null +++ b/tests/MC/AArch64/SVE/tbl.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x33, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "tbl z31.b, { z31.b }, z31.b" + + - + input: + bytes: [ 0xff, 0x33, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "tbl z31.h, { z31.h }, z31.h" + + - + input: + bytes: [ 0xff, 0x33, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "tbl z31.s, { z31.s }, z31.s" + + - + input: + bytes: [ 0xff, 0x33, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "tbl z31.d, { z31.d }, z31.d" + + - + input: + bytes: [ 0xff, 0x33, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "tbl z31.b, { z31.b }, z31.b" + + - + input: + bytes: [ 0xff, 0x33, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "tbl z31.h, { z31.h }, z31.h" + + - + input: + bytes: [ 0xff, 0x33, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "tbl z31.s, { z31.s }, z31.s" + + - + input: + bytes: [ 0xff, 0x33, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "tbl z31.d, { z31.d }, z31.d" + + - + input: + bytes: [ 0xff, 0x33, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "tbl z31.b, { z31.b }, z31.b" + + - + input: + bytes: [ 0xff, 0x33, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "tbl z31.h, { z31.h }, z31.h" + + - + input: + bytes: [ 0xff, 0x33, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "tbl z31.s, { z31.s }, z31.s" + + - + input: + bytes: [ 0xff, 0x33, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "tbl z31.d, { z31.d }, z31.d" + + - + input: + bytes: [ 0xff, 0x33, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "tbl z31.b, { z31.b }, z31.b" + + - + input: + bytes: [ 0xff, 0x33, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "tbl z31.h, { z31.h }, z31.h" + + - + input: + bytes: [ 0xff, 0x33, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "tbl z31.s, { z31.s }, z31.s" + + - + input: + bytes: [ 0xff, 0x33, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "tbl z31.d, { z31.d }, z31.d" diff --git a/tests/MC/AArch64/SVE/trn1.s.yaml b/tests/MC/AArch64/SVE/trn1.s.yaml new file mode 100644 index 0000000000..554e6fac58 --- /dev/null +++ b/tests/MC/AArch64/SVE/trn1.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x73, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "trn1 z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x73, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "trn1 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x73, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "trn1 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x73, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "trn1 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0xef, 0x51, 0x2f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "trn1 p15.b, p15.b, p15.b" + + - + input: + bytes: [ 0xef, 0x51, 0xaf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "trn1 p15.s, p15.s, p15.s" + + - + input: + bytes: [ 0xef, 0x51, 0x6f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "trn1 p15.h, p15.h, p15.h" + + - + input: + bytes: [ 0xef, 0x51, 0xef, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "trn1 p15.d, p15.d, p15.d" + + - + input: + bytes: [ 0xff, 0x73, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "trn1 z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x73, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "trn1 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x73, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "trn1 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x73, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "trn1 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0xef, 0x51, 0x2f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "trn1 p15.b, p15.b, p15.b" + + - + input: + bytes: [ 0xef, 0x51, 0xaf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "trn1 p15.s, p15.s, p15.s" + + - + input: + bytes: [ 0xef, 0x51, 0x6f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "trn1 p15.h, p15.h, p15.h" + + - + input: + bytes: [ 0xef, 0x51, 0xef, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "trn1 p15.d, p15.d, p15.d" diff --git a/tests/MC/AArch64/SVE/trn2.s.yaml b/tests/MC/AArch64/SVE/trn2.s.yaml new file mode 100644 index 0000000000..3916ba4fc5 --- /dev/null +++ b/tests/MC/AArch64/SVE/trn2.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x77, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "trn2 z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x77, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "trn2 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x77, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "trn2 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x77, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "trn2 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0xef, 0x55, 0x2f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "trn2 p15.b, p15.b, p15.b" + + - + input: + bytes: [ 0xef, 0x55, 0xaf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "trn2 p15.s, p15.s, p15.s" + + - + input: + bytes: [ 0xef, 0x55, 0x6f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "trn2 p15.h, p15.h, p15.h" + + - + input: + bytes: [ 0xef, 0x55, 0xef, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "trn2 p15.d, p15.d, p15.d" + + - + input: + bytes: [ 0xff, 0x77, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "trn2 z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x77, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "trn2 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x77, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "trn2 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x77, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "trn2 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0xef, 0x55, 0x2f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "trn2 p15.b, p15.b, p15.b" + + - + input: + bytes: [ 0xef, 0x55, 0xaf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "trn2 p15.s, p15.s, p15.s" + + - + input: + bytes: [ 0xef, 0x55, 0x6f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "trn2 p15.h, p15.h, p15.h" + + - + input: + bytes: [ 0xef, 0x55, 0xef, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "trn2 p15.d, p15.d, p15.d" diff --git a/tests/MC/AArch64/SVE/uabd.s.yaml b/tests/MC/AArch64/SVE/uabd.s.yaml new file mode 100644 index 0000000000..ef4da413ff --- /dev/null +++ b/tests/MC/AArch64/SVE/uabd.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x1f, 0x0d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uabd z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x1f, 0x4d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uabd z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x8d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uabd z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0xcd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uabd z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x1f, 0xcd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uabd z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0xcd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uabd z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xff, 0x1f, 0x0d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabd z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x1f, 0x4d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabd z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x8d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabd z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0xcd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabd z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x1f, 0xcd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabd z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0xcd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabd z4.d, p7/m, z4.d, z31.d" diff --git a/tests/MC/AArch64/SVE/uaddv.s.yaml b/tests/MC/AArch64/SVE/uaddv.s.yaml new file mode 100644 index 0000000000..99d4a16e3a --- /dev/null +++ b/tests/MC/AArch64/SVE/uaddv.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x3f, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uaddv d0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x41, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uaddv d0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uaddv d0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uaddv d0, p7, z31.d" + + - + input: + bytes: [ 0xe0, 0x3f, 0x01, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaddv d0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x41, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaddv d0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x81, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaddv d0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xc1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaddv d0, p7, z31.d" diff --git a/tests/MC/AArch64/SVE/ucvtf.s.yaml b/tests/MC/AArch64/SVE/ucvtf.s.yaml new file mode 100644 index 0000000000..22cd34323d --- /dev/null +++ b/tests/MC/AArch64/SVE/ucvtf.s.yaml @@ -0,0 +1,220 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x53, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ucvtf z0.h, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x55, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ucvtf z0.h, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0x57, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ucvtf z0.h, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x95, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ucvtf z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd5, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ucvtf z0.s, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0xd1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ucvtf z0.d, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ucvtf z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0xa0, 0xd7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ucvtf z5.d, p0/m, z0.d" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0xa0, 0xd7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "ucvtf z5.d, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x53, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ucvtf z0.h, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x55, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ucvtf z0.h, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0x57, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ucvtf z0.h, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x95, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ucvtf z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd5, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ucvtf z0.s, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0xd1, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ucvtf z0.d, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ucvtf z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0xa0, 0xd7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ucvtf z5.d, p0/m, z0.d" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0xa0, 0xd7, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ucvtf z5.d, p0/m, z0.d" diff --git a/tests/MC/AArch64/SVE/udiv.s.yaml b/tests/MC/AArch64/SVE/udiv.s.yaml new file mode 100644 index 0000000000..f6c1209dc8 --- /dev/null +++ b/tests/MC/AArch64/SVE/udiv.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x1f, 0x95, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "udiv z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "udiv z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "udiv z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "udiv z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0x95, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "udiv z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "udiv z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "udiv z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "udiv z0.d, p7/m, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/udivr.s.yaml b/tests/MC/AArch64/SVE/udivr.s.yaml new file mode 100644 index 0000000000..91c47265ec --- /dev/null +++ b/tests/MC/AArch64/SVE/udivr.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x1f, 0x97, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "udivr z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "udivr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "udivr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "udivr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0x97, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "udivr z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "udivr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "udivr z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "udivr z0.d, p7/m, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/udot.s.yaml b/tests/MC/AArch64/SVE/udot.s.yaml new file mode 100644 index 0000000000..5e1e21ca59 --- /dev/null +++ b/tests/MC/AArch64/SVE/udot.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x04, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "udot z0.s, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x04, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "udot z0.d, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x04, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "udot z0.s, z1.b, z7.b[3]" + + - + input: + bytes: [ 0x20, 0x04, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "udot z0.d, z1.h, z15.h[1]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x04, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "udot z0.d, z1.h, z31.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x04, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "udot z0.d, z1.h, z15.h[1]" + + - + input: + bytes: [ 0x20, 0x04, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "udot z0.s, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x04, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "udot z0.d, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x04, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "udot z0.s, z1.b, z7.b[3]" + + - + input: + bytes: [ 0x20, 0x04, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "udot z0.d, z1.h, z15.h[1]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x04, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "udot z0.d, z1.h, z31.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x04, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "udot z0.d, z1.h, z15.h[1]" diff --git a/tests/MC/AArch64/SVE/umax.s.yaml b/tests/MC/AArch64/SVE/umax.s.yaml new file mode 100644 index 0000000000..dabc96d712 --- /dev/null +++ b/tests/MC/AArch64/SVE/umax.s.yaml @@ -0,0 +1,360 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umax z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umax z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umax z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umax z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umax z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umax z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umax z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umax z31.b, z31.b, #255" + + - + input: + bytes: [ 0xff, 0x1f, 0x09, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umax z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x1f, 0x49, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umax z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x89, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umax z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0xc9, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umax z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x1f, 0xc9, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umax z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0xc9, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umax z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xdf, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umax z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umax z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umax z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umax z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umax z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umax z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umax z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umax z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umax z31.b, z31.b, #255" + + - + input: + bytes: [ 0xff, 0x1f, 0x09, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umax z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x1f, 0x49, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umax z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x89, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umax z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0xc9, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umax z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x1f, 0xc9, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umax z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0xc9, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umax z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xdf, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umax z31.b, z31.b, #255" diff --git a/tests/MC/AArch64/SVE/umaxv.s.yaml b/tests/MC/AArch64/SVE/umaxv.s.yaml new file mode 100644 index 0000000000..d43352f9fd --- /dev/null +++ b/tests/MC/AArch64/SVE/umaxv.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x3f, 0x09, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umaxv b0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x49, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umaxv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x89, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umaxv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xc9, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umaxv d0, p7, z31.d" + + - + input: + bytes: [ 0xe0, 0x3f, 0x09, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umaxv b0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x49, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umaxv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x89, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umaxv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xc9, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umaxv d0, p7, z31.d" diff --git a/tests/MC/AArch64/SVE/umin.s.yaml b/tests/MC/AArch64/SVE/umin.s.yaml new file mode 100644 index 0000000000..e69e2f97a9 --- /dev/null +++ b/tests/MC/AArch64/SVE/umin.s.yaml @@ -0,0 +1,360 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umin z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umin z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umin z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umin z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umin z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umin z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umin z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umin z31.b, z31.b, #255" + + - + input: + bytes: [ 0xff, 0x1f, 0x0b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umin z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x1f, 0x4b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umin z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x8b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umin z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0xcb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umin z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x1f, 0xcb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umin z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0xcb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umin z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xdf, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umin z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umin z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umin z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umin z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umin z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umin z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umin z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umin z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umin z31.b, z31.b, #255" + + - + input: + bytes: [ 0xff, 0x1f, 0x0b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umin z31.b, p7/m, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x1f, 0x4b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umin z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x8b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umin z31.s, p7/m, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x1f, 0xcb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umin z31.d, p7/m, z31.d, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0x1f, 0xcb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umin z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x1f, 0xcb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umin z4.d, p7/m, z4.d, z31.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xdf, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umin z31.b, z31.b, #255" diff --git a/tests/MC/AArch64/SVE/uminv.s.yaml b/tests/MC/AArch64/SVE/uminv.s.yaml new file mode 100644 index 0000000000..8b2d23a51b --- /dev/null +++ b/tests/MC/AArch64/SVE/uminv.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x3f, 0x0b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uminv b0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x4b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uminv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x8b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uminv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xcb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uminv d0, p7, z31.d" + + - + input: + bytes: [ 0xe0, 0x3f, 0x0b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uminv b0, p7, z31.b" + + - + input: + bytes: [ 0xe0, 0x3f, 0x4b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uminv h0, p7, z31.h" + + - + input: + bytes: [ 0xe0, 0x3f, 0x8b, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uminv s0, p7, z31.s" + + - + input: + bytes: [ 0xe0, 0x3f, 0xcb, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uminv d0, p7, z31.d" diff --git a/tests/MC/AArch64/SVE/umulh.s.yaml b/tests/MC/AArch64/SVE/umulh.s.yaml new file mode 100644 index 0000000000..ad883d4e29 --- /dev/null +++ b/tests/MC/AArch64/SVE/umulh.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x1f, 0x13, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umulh z0.b, p7/m, z0.b, z31.b" + + - + input: + bytes: [ 0xe0, 0x1f, 0x53, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umulh z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x1f, 0x93, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umulh z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umulh z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umulh z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "umulh z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0x13, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umulh z0.b, p7/m, z0.b, z31.b" + + - + input: + bytes: [ 0xe0, 0x1f, 0x53, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umulh z0.h, p7/m, z0.h, z31.h" + + - + input: + bytes: [ 0xe0, 0x1f, 0x93, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umulh z0.s, p7/m, z0.s, z31.s" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umulh z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0.d, p7/z, z7.d" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umulh z0.d, p7/m, z0.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0x1f, 0xd3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umulh z0.d, p7/m, z0.d, z31.d" diff --git a/tests/MC/AArch64/SVE/uqadd.s.yaml b/tests/MC/AArch64/SVE/uqadd.s.yaml new file mode 100644 index 0000000000..50a6f664b6 --- /dev/null +++ b/tests/MC/AArch64/SVE/uqadd.s.yaml @@ -0,0 +1,400 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x14, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqadd z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x14, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqadd z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x14, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqadd z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x14, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqadd z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0xc0, 0x25, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqadd z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x25, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqadd z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x65, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqadd z0.h, z0.h, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0x65, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqadd z0.h, z0.h, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0x65, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqadd z31.h, z31.h, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0x65, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqadd z31.h, z31.h, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xa5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqadd z0.s, z0.s, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xa5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqadd z0.s, z0.s, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xa5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqadd z31.s, z31.s, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xa5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqadd z31.s, z31.s, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xe5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqadd z0.d, z0.d, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xe5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqadd z0.d, z0.d, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xe5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqadd z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xe5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqadd z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xff, 0xe5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqadd z31.d, z31.d, #65280" + + - + input: + bytes: [ 0x00, 0x14, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x14, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x14, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x14, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0xc0, 0x25, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x25, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x65, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z0.h, z0.h, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0x65, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z0.h, z0.h, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0x65, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z31.h, z31.h, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0x65, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z31.h, z31.h, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xa5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z0.s, z0.s, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xa5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z0.s, z0.s, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xa5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z31.s, z31.s, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xa5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z31.s, z31.s, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xe5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z0.d, z0.d, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xe5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z0.d, z0.d, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xe5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xe5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xff, 0xe5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z31.d, z31.d, #65280" diff --git a/tests/MC/AArch64/SVE/uqdecb.s.yaml b/tests/MC/AArch64/SVE/uqdecb.s.yaml new file mode 100644 index 0000000000..d6e6fec074 --- /dev/null +++ b/tests/MC/AArch64/SVE/uqdecb.s.yaml @@ -0,0 +1,780 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xff, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0" + + - + input: + bytes: [ 0xe0, 0xff, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0" + + - + input: + bytes: [ 0xe0, 0xff, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0" + + - + input: + bytes: [ 0xe0, 0xff, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xff, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb w0" + + - + input: + bytes: [ 0xe0, 0xff, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb w0" + + - + input: + bytes: [ 0xe0, 0xff, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb w0" + + - + input: + bytes: [ 0xe0, 0xff, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xfc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb w0, pow2" + + - + input: + bytes: [ 0x00, 0xfc, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb w0, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xfc, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, pow2" + + - + input: + bytes: [ 0x20, 0xfc, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl1" + + - + input: + bytes: [ 0x40, 0xfc, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl2" + + - + input: + bytes: [ 0x60, 0xfc, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl3" + + - + input: + bytes: [ 0x80, 0xfc, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl4" + + - + input: + bytes: [ 0xa0, 0xfc, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl5" + + - + input: + bytes: [ 0xc0, 0xfc, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl6" + + - + input: + bytes: [ 0xe0, 0xfc, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl7" + + - + input: + bytes: [ 0x00, 0xfd, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl8" + + - + input: + bytes: [ 0x20, 0xfd, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl16" + + - + input: + bytes: [ 0x40, 0xfd, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl32" + + - + input: + bytes: [ 0x60, 0xfd, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl64" + + - + input: + bytes: [ 0x80, 0xfd, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl128" + + - + input: + bytes: [ 0xa0, 0xfd, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl256" + + - + input: + bytes: [ 0xc0, 0xfd, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, #14" + + - + input: + bytes: [ 0xe0, 0xfd, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, #15" + + - + input: + bytes: [ 0x00, 0xfe, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, #16" + + - + input: + bytes: [ 0x20, 0xfe, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, #17" + + - + input: + bytes: [ 0x40, 0xfe, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, #18" + + - + input: + bytes: [ 0x60, 0xfe, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, #19" + + - + input: + bytes: [ 0x80, 0xfe, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, #20" + + - + input: + bytes: [ 0xa0, 0xfe, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, #21" + + - + input: + bytes: [ 0xc0, 0xfe, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, #22" + + - + input: + bytes: [ 0xe0, 0xfe, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, #23" + + - + input: + bytes: [ 0x00, 0xff, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, #24" + + - + input: + bytes: [ 0x20, 0xff, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, #25" + + - + input: + bytes: [ 0x40, 0xff, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, #26" + + - + input: + bytes: [ 0x60, 0xff, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, #27" + + - + input: + bytes: [ 0x80, 0xff, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecb x0, #28" + + - + input: + bytes: [ 0xe0, 0xff, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0" + + - + input: + bytes: [ 0xe0, 0xff, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0" + + - + input: + bytes: [ 0xe0, 0xff, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0" + + - + input: + bytes: [ 0xe0, 0xff, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xff, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb w0" + + - + input: + bytes: [ 0xe0, 0xff, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb w0" + + - + input: + bytes: [ 0xe0, 0xff, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb w0" + + - + input: + bytes: [ 0xe0, 0xff, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xfc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb w0, pow2" + + - + input: + bytes: [ 0x00, 0xfc, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb w0, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xfc, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, pow2" + + - + input: + bytes: [ 0x20, 0xfc, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl1" + + - + input: + bytes: [ 0x40, 0xfc, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl2" + + - + input: + bytes: [ 0x60, 0xfc, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl3" + + - + input: + bytes: [ 0x80, 0xfc, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl4" + + - + input: + bytes: [ 0xa0, 0xfc, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl5" + + - + input: + bytes: [ 0xc0, 0xfc, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl6" + + - + input: + bytes: [ 0xe0, 0xfc, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl7" + + - + input: + bytes: [ 0x00, 0xfd, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl8" + + - + input: + bytes: [ 0x20, 0xfd, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl16" + + - + input: + bytes: [ 0x40, 0xfd, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl32" + + - + input: + bytes: [ 0x60, 0xfd, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl64" + + - + input: + bytes: [ 0x80, 0xfd, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl128" + + - + input: + bytes: [ 0xa0, 0xfd, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, vl256" + + - + input: + bytes: [ 0xc0, 0xfd, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, #14" + + - + input: + bytes: [ 0xe0, 0xfd, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, #15" + + - + input: + bytes: [ 0x00, 0xfe, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, #16" + + - + input: + bytes: [ 0x20, 0xfe, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, #17" + + - + input: + bytes: [ 0x40, 0xfe, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, #18" + + - + input: + bytes: [ 0x60, 0xfe, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, #19" + + - + input: + bytes: [ 0x80, 0xfe, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, #20" + + - + input: + bytes: [ 0xa0, 0xfe, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, #21" + + - + input: + bytes: [ 0xc0, 0xfe, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, #22" + + - + input: + bytes: [ 0xe0, 0xfe, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, #23" + + - + input: + bytes: [ 0x00, 0xff, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, #24" + + - + input: + bytes: [ 0x20, 0xff, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, #25" + + - + input: + bytes: [ 0x40, 0xff, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, #26" + + - + input: + bytes: [ 0x60, 0xff, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, #27" + + - + input: + bytes: [ 0x80, 0xff, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecb x0, #28" diff --git a/tests/MC/AArch64/SVE/uqdecd.s.yaml b/tests/MC/AArch64/SVE/uqdecd.s.yaml new file mode 100644 index 0000000000..22acaf0d6a --- /dev/null +++ b/tests/MC/AArch64/SVE/uqdecd.s.yaml @@ -0,0 +1,1020 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xff, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0" + + - + input: + bytes: [ 0xe0, 0xff, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0" + + - + input: + bytes: [ 0xe0, 0xff, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0" + + - + input: + bytes: [ 0xe0, 0xff, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xff, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd w0" + + - + input: + bytes: [ 0xe0, 0xff, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd w0" + + - + input: + bytes: [ 0xe0, 0xff, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd w0" + + - + input: + bytes: [ 0xe0, 0xff, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xfc, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd w0, pow2" + + - + input: + bytes: [ 0x00, 0xfc, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xcf, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd z0.d" + + - + input: + bytes: [ 0xe0, 0xcf, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd z0.d" + + - + input: + bytes: [ 0xe0, 0xcf, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd z0.d" + + - + input: + bytes: [ 0xe0, 0xcf, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd z0.d, all, mul #16" + + - + input: + bytes: [ 0x00, 0xcc, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd z0.d, pow2" + + - + input: + bytes: [ 0x00, 0xcc, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd z0.d, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xfc, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, pow2" + + - + input: + bytes: [ 0x20, 0xfc, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl1" + + - + input: + bytes: [ 0x40, 0xfc, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl2" + + - + input: + bytes: [ 0x60, 0xfc, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl3" + + - + input: + bytes: [ 0x80, 0xfc, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl4" + + - + input: + bytes: [ 0xa0, 0xfc, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl5" + + - + input: + bytes: [ 0xc0, 0xfc, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl6" + + - + input: + bytes: [ 0xe0, 0xfc, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl7" + + - + input: + bytes: [ 0x00, 0xfd, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl8" + + - + input: + bytes: [ 0x20, 0xfd, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl16" + + - + input: + bytes: [ 0x40, 0xfd, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl32" + + - + input: + bytes: [ 0x60, 0xfd, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl64" + + - + input: + bytes: [ 0x80, 0xfd, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl128" + + - + input: + bytes: [ 0xa0, 0xfd, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl256" + + - + input: + bytes: [ 0xc0, 0xfd, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, #14" + + - + input: + bytes: [ 0xe0, 0xfd, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, #15" + + - + input: + bytes: [ 0x00, 0xfe, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, #16" + + - + input: + bytes: [ 0x20, 0xfe, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, #17" + + - + input: + bytes: [ 0x40, 0xfe, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, #18" + + - + input: + bytes: [ 0x60, 0xfe, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, #19" + + - + input: + bytes: [ 0x80, 0xfe, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, #20" + + - + input: + bytes: [ 0xa0, 0xfe, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, #21" + + - + input: + bytes: [ 0xc0, 0xfe, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, #22" + + - + input: + bytes: [ 0xe0, 0xfe, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, #23" + + - + input: + bytes: [ 0x00, 0xff, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, #24" + + - + input: + bytes: [ 0x20, 0xff, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, #25" + + - + input: + bytes: [ 0x40, 0xff, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, #26" + + - + input: + bytes: [ 0x60, 0xff, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, #27" + + - + input: + bytes: [ 0x80, 0xff, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xcf, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd z0.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xcc, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd z0.d, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xcc, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecd z0.d, pow2" + + - + input: + bytes: [ 0xe0, 0xff, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0" + + - + input: + bytes: [ 0xe0, 0xff, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0" + + - + input: + bytes: [ 0xe0, 0xff, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0" + + - + input: + bytes: [ 0xe0, 0xff, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xff, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd w0" + + - + input: + bytes: [ 0xe0, 0xff, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd w0" + + - + input: + bytes: [ 0xe0, 0xff, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd w0" + + - + input: + bytes: [ 0xe0, 0xff, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xfc, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd w0, pow2" + + - + input: + bytes: [ 0x00, 0xfc, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xcf, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd z0.d" + + - + input: + bytes: [ 0xe0, 0xcf, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd z0.d" + + - + input: + bytes: [ 0xe0, 0xcf, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd z0.d" + + - + input: + bytes: [ 0xe0, 0xcf, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd z0.d, all, mul #16" + + - + input: + bytes: [ 0x00, 0xcc, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd z0.d, pow2" + + - + input: + bytes: [ 0x00, 0xcc, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd z0.d, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xfc, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, pow2" + + - + input: + bytes: [ 0x20, 0xfc, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl1" + + - + input: + bytes: [ 0x40, 0xfc, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl2" + + - + input: + bytes: [ 0x60, 0xfc, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl3" + + - + input: + bytes: [ 0x80, 0xfc, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl4" + + - + input: + bytes: [ 0xa0, 0xfc, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl5" + + - + input: + bytes: [ 0xc0, 0xfc, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl6" + + - + input: + bytes: [ 0xe0, 0xfc, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl7" + + - + input: + bytes: [ 0x00, 0xfd, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl8" + + - + input: + bytes: [ 0x20, 0xfd, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl16" + + - + input: + bytes: [ 0x40, 0xfd, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl32" + + - + input: + bytes: [ 0x60, 0xfd, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl64" + + - + input: + bytes: [ 0x80, 0xfd, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl128" + + - + input: + bytes: [ 0xa0, 0xfd, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, vl256" + + - + input: + bytes: [ 0xc0, 0xfd, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, #14" + + - + input: + bytes: [ 0xe0, 0xfd, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, #15" + + - + input: + bytes: [ 0x00, 0xfe, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, #16" + + - + input: + bytes: [ 0x20, 0xfe, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, #17" + + - + input: + bytes: [ 0x40, 0xfe, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, #18" + + - + input: + bytes: [ 0x60, 0xfe, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, #19" + + - + input: + bytes: [ 0x80, 0xfe, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, #20" + + - + input: + bytes: [ 0xa0, 0xfe, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, #21" + + - + input: + bytes: [ 0xc0, 0xfe, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, #22" + + - + input: + bytes: [ 0xe0, 0xfe, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, #23" + + - + input: + bytes: [ 0x00, 0xff, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, #24" + + - + input: + bytes: [ 0x20, 0xff, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, #25" + + - + input: + bytes: [ 0x40, 0xff, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, #26" + + - + input: + bytes: [ 0x60, 0xff, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, #27" + + - + input: + bytes: [ 0x80, 0xff, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xcf, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd z0.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xcc, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd z0.d, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xcc, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecd z0.d, pow2" diff --git a/tests/MC/AArch64/SVE/uqdech.s.yaml b/tests/MC/AArch64/SVE/uqdech.s.yaml new file mode 100644 index 0000000000..90fcd31b4a --- /dev/null +++ b/tests/MC/AArch64/SVE/uqdech.s.yaml @@ -0,0 +1,1020 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xff, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0" + + - + input: + bytes: [ 0xe0, 0xff, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0" + + - + input: + bytes: [ 0xe0, 0xff, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0" + + - + input: + bytes: [ 0xe0, 0xff, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xff, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech w0" + + - + input: + bytes: [ 0xe0, 0xff, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech w0" + + - + input: + bytes: [ 0xe0, 0xff, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech w0" + + - + input: + bytes: [ 0xe0, 0xff, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xfc, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech w0, pow2" + + - + input: + bytes: [ 0x00, 0xfc, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xcf, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech z0.h" + + - + input: + bytes: [ 0xe0, 0xcf, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech z0.h" + + - + input: + bytes: [ 0xe0, 0xcf, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech z0.h" + + - + input: + bytes: [ 0xe0, 0xcf, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech z0.h, all, mul #16" + + - + input: + bytes: [ 0x00, 0xcc, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech z0.h, pow2" + + - + input: + bytes: [ 0x00, 0xcc, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech z0.h, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xfc, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, pow2" + + - + input: + bytes: [ 0x20, 0xfc, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, vl1" + + - + input: + bytes: [ 0x40, 0xfc, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, vl2" + + - + input: + bytes: [ 0x60, 0xfc, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, vl3" + + - + input: + bytes: [ 0x80, 0xfc, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, vl4" + + - + input: + bytes: [ 0xa0, 0xfc, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, vl5" + + - + input: + bytes: [ 0xc0, 0xfc, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, vl6" + + - + input: + bytes: [ 0xe0, 0xfc, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, vl7" + + - + input: + bytes: [ 0x00, 0xfd, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, vl8" + + - + input: + bytes: [ 0x20, 0xfd, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, vl16" + + - + input: + bytes: [ 0x40, 0xfd, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, vl32" + + - + input: + bytes: [ 0x60, 0xfd, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, vl64" + + - + input: + bytes: [ 0x80, 0xfd, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, vl128" + + - + input: + bytes: [ 0xa0, 0xfd, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, vl256" + + - + input: + bytes: [ 0xc0, 0xfd, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, #14" + + - + input: + bytes: [ 0xe0, 0xfd, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, #15" + + - + input: + bytes: [ 0x00, 0xfe, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, #16" + + - + input: + bytes: [ 0x20, 0xfe, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, #17" + + - + input: + bytes: [ 0x40, 0xfe, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, #18" + + - + input: + bytes: [ 0x60, 0xfe, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, #19" + + - + input: + bytes: [ 0x80, 0xfe, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, #20" + + - + input: + bytes: [ 0xa0, 0xfe, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, #21" + + - + input: + bytes: [ 0xc0, 0xfe, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, #22" + + - + input: + bytes: [ 0xe0, 0xfe, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, #23" + + - + input: + bytes: [ 0x00, 0xff, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, #24" + + - + input: + bytes: [ 0x20, 0xff, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, #25" + + - + input: + bytes: [ 0x40, 0xff, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, #26" + + - + input: + bytes: [ 0x60, 0xff, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, #27" + + - + input: + bytes: [ 0x80, 0xff, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xcf, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech z0.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xcc, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech z0.h, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xcc, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdech z0.h, pow2" + + - + input: + bytes: [ 0xe0, 0xff, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0" + + - + input: + bytes: [ 0xe0, 0xff, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0" + + - + input: + bytes: [ 0xe0, 0xff, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0" + + - + input: + bytes: [ 0xe0, 0xff, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xff, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech w0" + + - + input: + bytes: [ 0xe0, 0xff, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech w0" + + - + input: + bytes: [ 0xe0, 0xff, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech w0" + + - + input: + bytes: [ 0xe0, 0xff, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xfc, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech w0, pow2" + + - + input: + bytes: [ 0x00, 0xfc, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xcf, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech z0.h" + + - + input: + bytes: [ 0xe0, 0xcf, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech z0.h" + + - + input: + bytes: [ 0xe0, 0xcf, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech z0.h" + + - + input: + bytes: [ 0xe0, 0xcf, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech z0.h, all, mul #16" + + - + input: + bytes: [ 0x00, 0xcc, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech z0.h, pow2" + + - + input: + bytes: [ 0x00, 0xcc, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech z0.h, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xfc, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, pow2" + + - + input: + bytes: [ 0x20, 0xfc, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, vl1" + + - + input: + bytes: [ 0x40, 0xfc, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, vl2" + + - + input: + bytes: [ 0x60, 0xfc, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, vl3" + + - + input: + bytes: [ 0x80, 0xfc, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, vl4" + + - + input: + bytes: [ 0xa0, 0xfc, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, vl5" + + - + input: + bytes: [ 0xc0, 0xfc, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, vl6" + + - + input: + bytes: [ 0xe0, 0xfc, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, vl7" + + - + input: + bytes: [ 0x00, 0xfd, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, vl8" + + - + input: + bytes: [ 0x20, 0xfd, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, vl16" + + - + input: + bytes: [ 0x40, 0xfd, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, vl32" + + - + input: + bytes: [ 0x60, 0xfd, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, vl64" + + - + input: + bytes: [ 0x80, 0xfd, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, vl128" + + - + input: + bytes: [ 0xa0, 0xfd, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, vl256" + + - + input: + bytes: [ 0xc0, 0xfd, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, #14" + + - + input: + bytes: [ 0xe0, 0xfd, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, #15" + + - + input: + bytes: [ 0x00, 0xfe, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, #16" + + - + input: + bytes: [ 0x20, 0xfe, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, #17" + + - + input: + bytes: [ 0x40, 0xfe, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, #18" + + - + input: + bytes: [ 0x60, 0xfe, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, #19" + + - + input: + bytes: [ 0x80, 0xfe, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, #20" + + - + input: + bytes: [ 0xa0, 0xfe, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, #21" + + - + input: + bytes: [ 0xc0, 0xfe, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, #22" + + - + input: + bytes: [ 0xe0, 0xfe, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, #23" + + - + input: + bytes: [ 0x00, 0xff, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, #24" + + - + input: + bytes: [ 0x20, 0xff, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, #25" + + - + input: + bytes: [ 0x40, 0xff, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, #26" + + - + input: + bytes: [ 0x60, 0xff, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, #27" + + - + input: + bytes: [ 0x80, 0xff, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xcf, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech z0.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xcc, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech z0.h, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xcc, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdech z0.h, pow2" diff --git a/tests/MC/AArch64/SVE/uqdecp.s.yaml b/tests/MC/AArch64/SVE/uqdecp.s.yaml new file mode 100644 index 0000000000..ab0c7c88d6 --- /dev/null +++ b/tests/MC/AArch64/SVE/uqdecp.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x8c, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecp x0, p0.b" + + - + input: + bytes: [ 0x00, 0x8c, 0x6b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecp x0, p0.h" + + - + input: + bytes: [ 0x00, 0x8c, 0xab, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecp x0, p0.s" + + - + input: + bytes: [ 0x00, 0x8c, 0xeb, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecp x0, p0.d" + + - + input: + bytes: [ 0xff, 0x89, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecp wzr, p15.b" + + - + input: + bytes: [ 0xff, 0x89, 0x6b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecp wzr, p15.h" + + - + input: + bytes: [ 0xff, 0x89, 0xab, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecp wzr, p15.s" + + - + input: + bytes: [ 0xff, 0x89, 0xeb, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecp wzr, p15.d" + + - + input: + bytes: [ 0x00, 0x80, 0x6b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecp z0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x6b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecp z0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x80, 0xab, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecp z0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xab, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecp z0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xeb, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecp z0.d, p0.d" + + - + input: + bytes: [ 0x00, 0x80, 0xeb, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecp z0.d, p0.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0x80, 0xeb, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecp z0.d, p0.d" + + - + input: + bytes: [ 0x00, 0x8c, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecp x0, p0.b" + + - + input: + bytes: [ 0x00, 0x8c, 0x6b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecp x0, p0.h" + + - + input: + bytes: [ 0x00, 0x8c, 0xab, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecp x0, p0.s" + + - + input: + bytes: [ 0x00, 0x8c, 0xeb, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecp x0, p0.d" + + - + input: + bytes: [ 0xff, 0x89, 0x2b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecp wzr, p15.b" + + - + input: + bytes: [ 0xff, 0x89, 0x6b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecp wzr, p15.h" + + - + input: + bytes: [ 0xff, 0x89, 0xab, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecp wzr, p15.s" + + - + input: + bytes: [ 0xff, 0x89, 0xeb, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecp wzr, p15.d" + + - + input: + bytes: [ 0x00, 0x80, 0x6b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecp z0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x6b, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecp z0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x80, 0xab, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecp z0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xab, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecp z0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xeb, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecp z0.d, p0.d" + + - + input: + bytes: [ 0x00, 0x80, 0xeb, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecp z0.d, p0.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0x80, 0xeb, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecp z0.d, p0.d" diff --git a/tests/MC/AArch64/SVE/uqdecw.s.yaml b/tests/MC/AArch64/SVE/uqdecw.s.yaml new file mode 100644 index 0000000000..c8e9b6c01a --- /dev/null +++ b/tests/MC/AArch64/SVE/uqdecw.s.yaml @@ -0,0 +1,1020 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xff, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0" + + - + input: + bytes: [ 0xe0, 0xff, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0" + + - + input: + bytes: [ 0xe0, 0xff, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0" + + - + input: + bytes: [ 0xe0, 0xff, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xff, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw w0" + + - + input: + bytes: [ 0xe0, 0xff, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw w0" + + - + input: + bytes: [ 0xe0, 0xff, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw w0" + + - + input: + bytes: [ 0xe0, 0xff, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xfc, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw w0, pow2" + + - + input: + bytes: [ 0x00, 0xfc, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw z0.s" + + - + input: + bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw z0.s" + + - + input: + bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw z0.s" + + - + input: + bytes: [ 0xe0, 0xcf, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw z0.s, all, mul #16" + + - + input: + bytes: [ 0x00, 0xcc, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw z0.s, pow2" + + - + input: + bytes: [ 0x00, 0xcc, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw z0.s, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xfc, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, pow2" + + - + input: + bytes: [ 0x20, 0xfc, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl1" + + - + input: + bytes: [ 0x40, 0xfc, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl2" + + - + input: + bytes: [ 0x60, 0xfc, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl3" + + - + input: + bytes: [ 0x80, 0xfc, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl4" + + - + input: + bytes: [ 0xa0, 0xfc, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl5" + + - + input: + bytes: [ 0xc0, 0xfc, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl6" + + - + input: + bytes: [ 0xe0, 0xfc, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl7" + + - + input: + bytes: [ 0x00, 0xfd, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl8" + + - + input: + bytes: [ 0x20, 0xfd, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl16" + + - + input: + bytes: [ 0x40, 0xfd, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl32" + + - + input: + bytes: [ 0x60, 0xfd, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl64" + + - + input: + bytes: [ 0x80, 0xfd, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl128" + + - + input: + bytes: [ 0xa0, 0xfd, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl256" + + - + input: + bytes: [ 0xc0, 0xfd, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, #14" + + - + input: + bytes: [ 0xe0, 0xfd, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, #15" + + - + input: + bytes: [ 0x00, 0xfe, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, #16" + + - + input: + bytes: [ 0x20, 0xfe, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, #17" + + - + input: + bytes: [ 0x40, 0xfe, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, #18" + + - + input: + bytes: [ 0x60, 0xfe, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, #19" + + - + input: + bytes: [ 0x80, 0xfe, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, #20" + + - + input: + bytes: [ 0xa0, 0xfe, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, #21" + + - + input: + bytes: [ 0xc0, 0xfe, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, #22" + + - + input: + bytes: [ 0xe0, 0xfe, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, #23" + + - + input: + bytes: [ 0x00, 0xff, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, #24" + + - + input: + bytes: [ 0x20, 0xff, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, #25" + + - + input: + bytes: [ 0x40, 0xff, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, #26" + + - + input: + bytes: [ 0x60, 0xff, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, #27" + + - + input: + bytes: [ 0x80, 0xff, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw z0.s" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xcc, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw z0.s, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xcc, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqdecw z0.s, pow2" + + - + input: + bytes: [ 0xe0, 0xff, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0" + + - + input: + bytes: [ 0xe0, 0xff, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0" + + - + input: + bytes: [ 0xe0, 0xff, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0" + + - + input: + bytes: [ 0xe0, 0xff, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xff, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw w0" + + - + input: + bytes: [ 0xe0, 0xff, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw w0" + + - + input: + bytes: [ 0xe0, 0xff, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw w0" + + - + input: + bytes: [ 0xe0, 0xff, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xfc, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw w0, pow2" + + - + input: + bytes: [ 0x00, 0xfc, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw z0.s" + + - + input: + bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw z0.s" + + - + input: + bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw z0.s" + + - + input: + bytes: [ 0xe0, 0xcf, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw z0.s, all, mul #16" + + - + input: + bytes: [ 0x00, 0xcc, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw z0.s, pow2" + + - + input: + bytes: [ 0x00, 0xcc, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw z0.s, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xfc, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, pow2" + + - + input: + bytes: [ 0x20, 0xfc, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl1" + + - + input: + bytes: [ 0x40, 0xfc, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl2" + + - + input: + bytes: [ 0x60, 0xfc, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl3" + + - + input: + bytes: [ 0x80, 0xfc, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl4" + + - + input: + bytes: [ 0xa0, 0xfc, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl5" + + - + input: + bytes: [ 0xc0, 0xfc, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl6" + + - + input: + bytes: [ 0xe0, 0xfc, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl7" + + - + input: + bytes: [ 0x00, 0xfd, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl8" + + - + input: + bytes: [ 0x20, 0xfd, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl16" + + - + input: + bytes: [ 0x40, 0xfd, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl32" + + - + input: + bytes: [ 0x60, 0xfd, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl64" + + - + input: + bytes: [ 0x80, 0xfd, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl128" + + - + input: + bytes: [ 0xa0, 0xfd, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, vl256" + + - + input: + bytes: [ 0xc0, 0xfd, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, #14" + + - + input: + bytes: [ 0xe0, 0xfd, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, #15" + + - + input: + bytes: [ 0x00, 0xfe, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, #16" + + - + input: + bytes: [ 0x20, 0xfe, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, #17" + + - + input: + bytes: [ 0x40, 0xfe, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, #18" + + - + input: + bytes: [ 0x60, 0xfe, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, #19" + + - + input: + bytes: [ 0x80, 0xfe, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, #20" + + - + input: + bytes: [ 0xa0, 0xfe, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, #21" + + - + input: + bytes: [ 0xc0, 0xfe, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, #22" + + - + input: + bytes: [ 0xe0, 0xfe, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, #23" + + - + input: + bytes: [ 0x00, 0xff, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, #24" + + - + input: + bytes: [ 0x20, 0xff, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, #25" + + - + input: + bytes: [ 0x40, 0xff, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, #26" + + - + input: + bytes: [ 0x60, 0xff, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, #27" + + - + input: + bytes: [ 0x80, 0xff, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw z0.s" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xcc, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw z0.s, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xcc, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqdecw z0.s, pow2" diff --git a/tests/MC/AArch64/SVE/uqincb.s.yaml b/tests/MC/AArch64/SVE/uqincb.s.yaml new file mode 100644 index 0000000000..0bdab165f5 --- /dev/null +++ b/tests/MC/AArch64/SVE/uqincb.s.yaml @@ -0,0 +1,780 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xf7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xf7, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf4, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb w0, pow2" + + - + input: + bytes: [ 0x00, 0xf4, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb w0, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, pow2" + + - + input: + bytes: [ 0x20, 0xf4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, vl1" + + - + input: + bytes: [ 0x40, 0xf4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, vl2" + + - + input: + bytes: [ 0x60, 0xf4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, vl3" + + - + input: + bytes: [ 0x80, 0xf4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, vl7" + + - + input: + bytes: [ 0x00, 0xf5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, vl8" + + - + input: + bytes: [ 0x20, 0xf5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, vl16" + + - + input: + bytes: [ 0x40, 0xf5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, vl32" + + - + input: + bytes: [ 0x60, 0xf5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, vl64" + + - + input: + bytes: [ 0x80, 0xf5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, #14" + + - + input: + bytes: [ 0xe0, 0xf5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, #15" + + - + input: + bytes: [ 0x00, 0xf6, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, #16" + + - + input: + bytes: [ 0x20, 0xf6, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, #17" + + - + input: + bytes: [ 0x40, 0xf6, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, #18" + + - + input: + bytes: [ 0x60, 0xf6, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, #19" + + - + input: + bytes: [ 0x80, 0xf6, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, #20" + + - + input: + bytes: [ 0xa0, 0xf6, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, #21" + + - + input: + bytes: [ 0xc0, 0xf6, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, #22" + + - + input: + bytes: [ 0xe0, 0xf6, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, #23" + + - + input: + bytes: [ 0x00, 0xf7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, #24" + + - + input: + bytes: [ 0x20, 0xf7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, #25" + + - + input: + bytes: [ 0x40, 0xf7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, #26" + + - + input: + bytes: [ 0x60, 0xf7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, #27" + + - + input: + bytes: [ 0x80, 0xf7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincb x0, #28" + + - + input: + bytes: [ 0xe0, 0xf7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xf7, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf4, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb w0, pow2" + + - + input: + bytes: [ 0x00, 0xf4, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb w0, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, pow2" + + - + input: + bytes: [ 0x20, 0xf4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, vl1" + + - + input: + bytes: [ 0x40, 0xf4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, vl2" + + - + input: + bytes: [ 0x60, 0xf4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, vl3" + + - + input: + bytes: [ 0x80, 0xf4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf4, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, vl7" + + - + input: + bytes: [ 0x00, 0xf5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, vl8" + + - + input: + bytes: [ 0x20, 0xf5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, vl16" + + - + input: + bytes: [ 0x40, 0xf5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, vl32" + + - + input: + bytes: [ 0x60, 0xf5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, vl64" + + - + input: + bytes: [ 0x80, 0xf5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, #14" + + - + input: + bytes: [ 0xe0, 0xf5, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, #15" + + - + input: + bytes: [ 0x00, 0xf6, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, #16" + + - + input: + bytes: [ 0x20, 0xf6, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, #17" + + - + input: + bytes: [ 0x40, 0xf6, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, #18" + + - + input: + bytes: [ 0x60, 0xf6, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, #19" + + - + input: + bytes: [ 0x80, 0xf6, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, #20" + + - + input: + bytes: [ 0xa0, 0xf6, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, #21" + + - + input: + bytes: [ 0xc0, 0xf6, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, #22" + + - + input: + bytes: [ 0xe0, 0xf6, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, #23" + + - + input: + bytes: [ 0x00, 0xf7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, #24" + + - + input: + bytes: [ 0x20, 0xf7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, #25" + + - + input: + bytes: [ 0x40, 0xf7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, #26" + + - + input: + bytes: [ 0x60, 0xf7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, #27" + + - + input: + bytes: [ 0x80, 0xf7, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincb x0, #28" diff --git a/tests/MC/AArch64/SVE/uqincd.s.yaml b/tests/MC/AArch64/SVE/uqincd.s.yaml new file mode 100644 index 0000000000..dc0c7cc9e5 --- /dev/null +++ b/tests/MC/AArch64/SVE/uqincd.s.yaml @@ -0,0 +1,1020 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xf7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xf7, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf4, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd w0, pow2" + + - + input: + bytes: [ 0x00, 0xf4, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xc7, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd z0.d" + + - + input: + bytes: [ 0xe0, 0xc7, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd z0.d" + + - + input: + bytes: [ 0xe0, 0xc7, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd z0.d" + + - + input: + bytes: [ 0xe0, 0xc7, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd z0.d, all, mul #16" + + - + input: + bytes: [ 0x00, 0xc4, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd z0.d, pow2" + + - + input: + bytes: [ 0x00, 0xc4, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd z0.d, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, pow2" + + - + input: + bytes: [ 0x20, 0xf4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, vl1" + + - + input: + bytes: [ 0x40, 0xf4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, vl2" + + - + input: + bytes: [ 0x60, 0xf4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, vl3" + + - + input: + bytes: [ 0x80, 0xf4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, vl7" + + - + input: + bytes: [ 0x00, 0xf5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, vl8" + + - + input: + bytes: [ 0x20, 0xf5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, vl16" + + - + input: + bytes: [ 0x40, 0xf5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, vl32" + + - + input: + bytes: [ 0x60, 0xf5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, vl64" + + - + input: + bytes: [ 0x80, 0xf5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, #14" + + - + input: + bytes: [ 0xe0, 0xf5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, #15" + + - + input: + bytes: [ 0x00, 0xf6, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, #16" + + - + input: + bytes: [ 0x20, 0xf6, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, #17" + + - + input: + bytes: [ 0x40, 0xf6, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, #18" + + - + input: + bytes: [ 0x60, 0xf6, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, #19" + + - + input: + bytes: [ 0x80, 0xf6, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, #20" + + - + input: + bytes: [ 0xa0, 0xf6, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, #21" + + - + input: + bytes: [ 0xc0, 0xf6, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, #22" + + - + input: + bytes: [ 0xe0, 0xf6, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, #23" + + - + input: + bytes: [ 0x00, 0xf7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, #24" + + - + input: + bytes: [ 0x20, 0xf7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, #25" + + - + input: + bytes: [ 0x40, 0xf7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, #26" + + - + input: + bytes: [ 0x60, 0xf7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, #27" + + - + input: + bytes: [ 0x80, 0xf7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc7, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd z0.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc4, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd z0.d, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc4, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincd z0.d, pow2" + + - + input: + bytes: [ 0xe0, 0xf7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xf7, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf4, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd w0, pow2" + + - + input: + bytes: [ 0x00, 0xf4, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xc7, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd z0.d" + + - + input: + bytes: [ 0xe0, 0xc7, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd z0.d" + + - + input: + bytes: [ 0xe0, 0xc7, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd z0.d" + + - + input: + bytes: [ 0xe0, 0xc7, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd z0.d, all, mul #16" + + - + input: + bytes: [ 0x00, 0xc4, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd z0.d, pow2" + + - + input: + bytes: [ 0x00, 0xc4, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd z0.d, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, pow2" + + - + input: + bytes: [ 0x20, 0xf4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, vl1" + + - + input: + bytes: [ 0x40, 0xf4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, vl2" + + - + input: + bytes: [ 0x60, 0xf4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, vl3" + + - + input: + bytes: [ 0x80, 0xf4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf4, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, vl7" + + - + input: + bytes: [ 0x00, 0xf5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, vl8" + + - + input: + bytes: [ 0x20, 0xf5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, vl16" + + - + input: + bytes: [ 0x40, 0xf5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, vl32" + + - + input: + bytes: [ 0x60, 0xf5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, vl64" + + - + input: + bytes: [ 0x80, 0xf5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, #14" + + - + input: + bytes: [ 0xe0, 0xf5, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, #15" + + - + input: + bytes: [ 0x00, 0xf6, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, #16" + + - + input: + bytes: [ 0x20, 0xf6, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, #17" + + - + input: + bytes: [ 0x40, 0xf6, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, #18" + + - + input: + bytes: [ 0x60, 0xf6, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, #19" + + - + input: + bytes: [ 0x80, 0xf6, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, #20" + + - + input: + bytes: [ 0xa0, 0xf6, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, #21" + + - + input: + bytes: [ 0xc0, 0xf6, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, #22" + + - + input: + bytes: [ 0xe0, 0xf6, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, #23" + + - + input: + bytes: [ 0x00, 0xf7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, #24" + + - + input: + bytes: [ 0x20, 0xf7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, #25" + + - + input: + bytes: [ 0x40, 0xf7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, #26" + + - + input: + bytes: [ 0x60, 0xf7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, #27" + + - + input: + bytes: [ 0x80, 0xf7, 0xf0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc7, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd z0.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc4, 0xef, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd z0.d, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc4, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincd z0.d, pow2" diff --git a/tests/MC/AArch64/SVE/uqinch.s.yaml b/tests/MC/AArch64/SVE/uqinch.s.yaml new file mode 100644 index 0000000000..8a243e4727 --- /dev/null +++ b/tests/MC/AArch64/SVE/uqinch.s.yaml @@ -0,0 +1,1020 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xf7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xf7, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf4, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch w0, pow2" + + - + input: + bytes: [ 0x00, 0xf4, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xc7, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch z0.h" + + - + input: + bytes: [ 0xe0, 0xc7, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch z0.h" + + - + input: + bytes: [ 0xe0, 0xc7, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch z0.h" + + - + input: + bytes: [ 0xe0, 0xc7, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch z0.h, all, mul #16" + + - + input: + bytes: [ 0x00, 0xc4, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch z0.h, pow2" + + - + input: + bytes: [ 0x00, 0xc4, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch z0.h, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, pow2" + + - + input: + bytes: [ 0x20, 0xf4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, vl1" + + - + input: + bytes: [ 0x40, 0xf4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, vl2" + + - + input: + bytes: [ 0x60, 0xf4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, vl3" + + - + input: + bytes: [ 0x80, 0xf4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, vl7" + + - + input: + bytes: [ 0x00, 0xf5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, vl8" + + - + input: + bytes: [ 0x20, 0xf5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, vl16" + + - + input: + bytes: [ 0x40, 0xf5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, vl32" + + - + input: + bytes: [ 0x60, 0xf5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, vl64" + + - + input: + bytes: [ 0x80, 0xf5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, #14" + + - + input: + bytes: [ 0xe0, 0xf5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, #15" + + - + input: + bytes: [ 0x00, 0xf6, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, #16" + + - + input: + bytes: [ 0x20, 0xf6, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, #17" + + - + input: + bytes: [ 0x40, 0xf6, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, #18" + + - + input: + bytes: [ 0x60, 0xf6, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, #19" + + - + input: + bytes: [ 0x80, 0xf6, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, #20" + + - + input: + bytes: [ 0xa0, 0xf6, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, #21" + + - + input: + bytes: [ 0xc0, 0xf6, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, #22" + + - + input: + bytes: [ 0xe0, 0xf6, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, #23" + + - + input: + bytes: [ 0x00, 0xf7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, #24" + + - + input: + bytes: [ 0x20, 0xf7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, #25" + + - + input: + bytes: [ 0x40, 0xf7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, #26" + + - + input: + bytes: [ 0x60, 0xf7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, #27" + + - + input: + bytes: [ 0x80, 0xf7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc7, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch z0.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc4, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch z0.h, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc4, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqinch z0.h, pow2" + + - + input: + bytes: [ 0xe0, 0xf7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xf7, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf4, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch w0, pow2" + + - + input: + bytes: [ 0x00, 0xf4, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xc7, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch z0.h" + + - + input: + bytes: [ 0xe0, 0xc7, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch z0.h" + + - + input: + bytes: [ 0xe0, 0xc7, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch z0.h" + + - + input: + bytes: [ 0xe0, 0xc7, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch z0.h, all, mul #16" + + - + input: + bytes: [ 0x00, 0xc4, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch z0.h, pow2" + + - + input: + bytes: [ 0x00, 0xc4, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch z0.h, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, pow2" + + - + input: + bytes: [ 0x20, 0xf4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, vl1" + + - + input: + bytes: [ 0x40, 0xf4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, vl2" + + - + input: + bytes: [ 0x60, 0xf4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, vl3" + + - + input: + bytes: [ 0x80, 0xf4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf4, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, vl7" + + - + input: + bytes: [ 0x00, 0xf5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, vl8" + + - + input: + bytes: [ 0x20, 0xf5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, vl16" + + - + input: + bytes: [ 0x40, 0xf5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, vl32" + + - + input: + bytes: [ 0x60, 0xf5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, vl64" + + - + input: + bytes: [ 0x80, 0xf5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, #14" + + - + input: + bytes: [ 0xe0, 0xf5, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, #15" + + - + input: + bytes: [ 0x00, 0xf6, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, #16" + + - + input: + bytes: [ 0x20, 0xf6, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, #17" + + - + input: + bytes: [ 0x40, 0xf6, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, #18" + + - + input: + bytes: [ 0x60, 0xf6, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, #19" + + - + input: + bytes: [ 0x80, 0xf6, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, #20" + + - + input: + bytes: [ 0xa0, 0xf6, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, #21" + + - + input: + bytes: [ 0xc0, 0xf6, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, #22" + + - + input: + bytes: [ 0xe0, 0xf6, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, #23" + + - + input: + bytes: [ 0x00, 0xf7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, #24" + + - + input: + bytes: [ 0x20, 0xf7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, #25" + + - + input: + bytes: [ 0x40, 0xf7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, #26" + + - + input: + bytes: [ 0x60, 0xf7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, #27" + + - + input: + bytes: [ 0x80, 0xf7, 0x70, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc7, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch z0.h" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc4, 0x6f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch z0.h, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc4, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqinch z0.h, pow2" diff --git a/tests/MC/AArch64/SVE/uqincp.s.yaml b/tests/MC/AArch64/SVE/uqincp.s.yaml new file mode 100644 index 0000000000..1dcfeb7a77 --- /dev/null +++ b/tests/MC/AArch64/SVE/uqincp.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x8c, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincp x0, p0.b" + + - + input: + bytes: [ 0x00, 0x8c, 0x69, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincp x0, p0.h" + + - + input: + bytes: [ 0x00, 0x8c, 0xa9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincp x0, p0.s" + + - + input: + bytes: [ 0x00, 0x8c, 0xe9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincp x0, p0.d" + + - + input: + bytes: [ 0xff, 0x89, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincp wzr, p15.b" + + - + input: + bytes: [ 0xff, 0x89, 0x69, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincp wzr, p15.h" + + - + input: + bytes: [ 0xff, 0x89, 0xa9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincp wzr, p15.s" + + - + input: + bytes: [ 0xff, 0x89, 0xe9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincp wzr, p15.d" + + - + input: + bytes: [ 0x00, 0x80, 0x69, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincp z0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x69, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincp z0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x80, 0xa9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincp z0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xa9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincp z0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xe9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincp z0.d, p0.d" + + - + input: + bytes: [ 0x00, 0x80, 0xe9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincp z0.d, p0.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0x80, 0xe9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincp z0.d, p0.d" + + - + input: + bytes: [ 0x00, 0x8c, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincp x0, p0.b" + + - + input: + bytes: [ 0x00, 0x8c, 0x69, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincp x0, p0.h" + + - + input: + bytes: [ 0x00, 0x8c, 0xa9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincp x0, p0.s" + + - + input: + bytes: [ 0x00, 0x8c, 0xe9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincp x0, p0.d" + + - + input: + bytes: [ 0xff, 0x89, 0x29, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincp wzr, p15.b" + + - + input: + bytes: [ 0xff, 0x89, 0x69, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincp wzr, p15.h" + + - + input: + bytes: [ 0xff, 0x89, 0xa9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincp wzr, p15.s" + + - + input: + bytes: [ 0xff, 0x89, 0xe9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincp wzr, p15.d" + + - + input: + bytes: [ 0x00, 0x80, 0x69, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincp z0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x80, 0x69, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincp z0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x80, 0xa9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincp z0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xa9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincp z0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x80, 0xe9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincp z0.d, p0.d" + + - + input: + bytes: [ 0x00, 0x80, 0xe9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincp z0.d, p0.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0x80, 0xe9, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincp z0.d, p0.d" diff --git a/tests/MC/AArch64/SVE/uqincw.s.yaml b/tests/MC/AArch64/SVE/uqincw.s.yaml new file mode 100644 index 0000000000..6ff7e4d36b --- /dev/null +++ b/tests/MC/AArch64/SVE/uqincw.s.yaml @@ -0,0 +1,1020 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xf7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xf7, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf4, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw w0, pow2" + + - + input: + bytes: [ 0x00, 0xf4, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xc7, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw z0.s" + + - + input: + bytes: [ 0xe0, 0xc7, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw z0.s" + + - + input: + bytes: [ 0xe0, 0xc7, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw z0.s" + + - + input: + bytes: [ 0xe0, 0xc7, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw z0.s, all, mul #16" + + - + input: + bytes: [ 0x00, 0xc4, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw z0.s, pow2" + + - + input: + bytes: [ 0x00, 0xc4, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw z0.s, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, pow2" + + - + input: + bytes: [ 0x20, 0xf4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, vl1" + + - + input: + bytes: [ 0x40, 0xf4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, vl2" + + - + input: + bytes: [ 0x60, 0xf4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, vl3" + + - + input: + bytes: [ 0x80, 0xf4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, vl7" + + - + input: + bytes: [ 0x00, 0xf5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, vl8" + + - + input: + bytes: [ 0x20, 0xf5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, vl16" + + - + input: + bytes: [ 0x40, 0xf5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, vl32" + + - + input: + bytes: [ 0x60, 0xf5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, vl64" + + - + input: + bytes: [ 0x80, 0xf5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, #14" + + - + input: + bytes: [ 0xe0, 0xf5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, #15" + + - + input: + bytes: [ 0x00, 0xf6, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, #16" + + - + input: + bytes: [ 0x20, 0xf6, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, #17" + + - + input: + bytes: [ 0x40, 0xf6, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, #18" + + - + input: + bytes: [ 0x60, 0xf6, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, #19" + + - + input: + bytes: [ 0x80, 0xf6, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, #20" + + - + input: + bytes: [ 0xa0, 0xf6, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, #21" + + - + input: + bytes: [ 0xc0, 0xf6, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, #22" + + - + input: + bytes: [ 0xe0, 0xf6, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, #23" + + - + input: + bytes: [ 0x00, 0xf7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, #24" + + - + input: + bytes: [ 0x20, 0xf7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, #25" + + - + input: + bytes: [ 0x40, 0xf7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, #26" + + - + input: + bytes: [ 0x60, 0xf7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, #27" + + - + input: + bytes: [ 0x80, 0xf7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc7, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw z0.s" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc4, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw z0.s, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc4, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqincw z0.s, pow2" + + - + input: + bytes: [ 0xe0, 0xf7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, all, mul #16" + + - + input: + bytes: [ 0xe0, 0xf7, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw w0" + + - + input: + bytes: [ 0xe0, 0xf7, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw w0, all, mul #16" + + - + input: + bytes: [ 0x00, 0xf4, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw w0, pow2" + + - + input: + bytes: [ 0x00, 0xf4, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw w0, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xc7, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw z0.s" + + - + input: + bytes: [ 0xe0, 0xc7, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw z0.s" + + - + input: + bytes: [ 0xe0, 0xc7, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw z0.s" + + - + input: + bytes: [ 0xe0, 0xc7, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw z0.s, all, mul #16" + + - + input: + bytes: [ 0x00, 0xc4, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw z0.s, pow2" + + - + input: + bytes: [ 0x00, 0xc4, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw z0.s, pow2, mul #16" + + - + input: + bytes: [ 0x00, 0xf4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, pow2" + + - + input: + bytes: [ 0x20, 0xf4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, vl1" + + - + input: + bytes: [ 0x40, 0xf4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, vl2" + + - + input: + bytes: [ 0x60, 0xf4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, vl3" + + - + input: + bytes: [ 0x80, 0xf4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, vl4" + + - + input: + bytes: [ 0xa0, 0xf4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, vl5" + + - + input: + bytes: [ 0xc0, 0xf4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, vl6" + + - + input: + bytes: [ 0xe0, 0xf4, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, vl7" + + - + input: + bytes: [ 0x00, 0xf5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, vl8" + + - + input: + bytes: [ 0x20, 0xf5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, vl16" + + - + input: + bytes: [ 0x40, 0xf5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, vl32" + + - + input: + bytes: [ 0x60, 0xf5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, vl64" + + - + input: + bytes: [ 0x80, 0xf5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, vl128" + + - + input: + bytes: [ 0xa0, 0xf5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, vl256" + + - + input: + bytes: [ 0xc0, 0xf5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, #14" + + - + input: + bytes: [ 0xe0, 0xf5, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, #15" + + - + input: + bytes: [ 0x00, 0xf6, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, #16" + + - + input: + bytes: [ 0x20, 0xf6, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, #17" + + - + input: + bytes: [ 0x40, 0xf6, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, #18" + + - + input: + bytes: [ 0x60, 0xf6, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, #19" + + - + input: + bytes: [ 0x80, 0xf6, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, #20" + + - + input: + bytes: [ 0xa0, 0xf6, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, #21" + + - + input: + bytes: [ 0xc0, 0xf6, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, #22" + + - + input: + bytes: [ 0xe0, 0xf6, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, #23" + + - + input: + bytes: [ 0x00, 0xf7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, #24" + + - + input: + bytes: [ 0x20, 0xf7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, #25" + + - + input: + bytes: [ 0x40, 0xf7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, #26" + + - + input: + bytes: [ 0x60, 0xf7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, #27" + + - + input: + bytes: [ 0x80, 0xf7, 0xb0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw x0, #28" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0xe0, 0xc7, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw z0.s" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc4, 0xaf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw z0.s, pow2, mul #16" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x00, 0xc4, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqincw z0.s, pow2" diff --git a/tests/MC/AArch64/SVE/uqsub.s.yaml b/tests/MC/AArch64/SVE/uqsub.s.yaml new file mode 100644 index 0000000000..490f6c12e2 --- /dev/null +++ b/tests/MC/AArch64/SVE/uqsub.s.yaml @@ -0,0 +1,400 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x1c, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqsub z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x1c, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqsub z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x1c, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqsub z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x1c, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqsub z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0xc0, 0x27, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqsub z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x27, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqsub z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x67, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqsub z0.h, z0.h, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0x67, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqsub z0.h, z0.h, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0x67, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqsub z31.h, z31.h, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0x67, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqsub z31.h, z31.h, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xa7, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqsub z0.s, z0.s, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xa7, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqsub z0.s, z0.s, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xa7, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqsub z31.s, z31.s, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xa7, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqsub z31.s, z31.s, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xe7, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqsub z0.d, z0.d, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xe7, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqsub z0.d, z0.d, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xe7, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqsub z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xe7, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqsub z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xff, 0xe7, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uqsub z31.d, z31.d, #65280" + + - + input: + bytes: [ 0x00, 0x1c, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x1c, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x1c, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x1c, 0xe0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x00, 0xc0, 0x27, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xdf, 0x27, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z31.b, z31.b, #255" + + - + input: + bytes: [ 0x00, 0xc0, 0x67, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z0.h, z0.h, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0x67, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z0.h, z0.h, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0x67, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z31.h, z31.h, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0x67, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z31.h, z31.h, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xa7, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z0.s, z0.s, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xa7, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z0.s, z0.s, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xa7, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z31.s, z31.s, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xa7, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z31.s, z31.s, #65280" + + - + input: + bytes: [ 0x00, 0xc0, 0xe7, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z0.d, z0.d, #0" + + - + input: + bytes: [ 0x00, 0xe0, 0xe7, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z0.d, z0.d, #0, lsl #8" + + - + input: + bytes: [ 0xff, 0xff, 0xe7, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xff, 0xff, 0xe7, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z31.d, z31.d, #65280" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0xff, 0xe7, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z31.d, z31.d, #65280" diff --git a/tests/MC/AArch64/SVE/uunpkhi.s.yaml b/tests/MC/AArch64/SVE/uunpkhi.s.yaml new file mode 100644 index 0000000000..b3fe265541 --- /dev/null +++ b/tests/MC/AArch64/SVE/uunpkhi.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x3b, 0x73, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uunpkhi z31.h, z31.b" + + - + input: + bytes: [ 0xff, 0x3b, 0xb3, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uunpkhi z31.s, z31.h" + + - + input: + bytes: [ 0xff, 0x3b, 0xf3, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uunpkhi z31.d, z31.s" + + - + input: + bytes: [ 0xff, 0x3b, 0x73, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uunpkhi z31.h, z31.b" + + - + input: + bytes: [ 0xff, 0x3b, 0xb3, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uunpkhi z31.s, z31.h" + + - + input: + bytes: [ 0xff, 0x3b, 0xf3, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uunpkhi z31.d, z31.s" diff --git a/tests/MC/AArch64/SVE/uunpklo.s.yaml b/tests/MC/AArch64/SVE/uunpklo.s.yaml new file mode 100644 index 0000000000..1e2a164131 --- /dev/null +++ b/tests/MC/AArch64/SVE/uunpklo.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x3b, 0x72, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uunpklo z31.h, z31.b" + + - + input: + bytes: [ 0xff, 0x3b, 0xb2, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uunpklo z31.s, z31.h" + + - + input: + bytes: [ 0xff, 0x3b, 0xf2, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uunpklo z31.d, z31.s" + + - + input: + bytes: [ 0xff, 0x3b, 0x72, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uunpklo z31.h, z31.b" + + - + input: + bytes: [ 0xff, 0x3b, 0xb2, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uunpklo z31.s, z31.h" + + - + input: + bytes: [ 0xff, 0x3b, 0xf2, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uunpklo z31.d, z31.s" diff --git a/tests/MC/AArch64/SVE/uxtb.s.yaml b/tests/MC/AArch64/SVE/uxtb.s.yaml new file mode 100644 index 0000000000..fd8ca8d2fe --- /dev/null +++ b/tests/MC/AArch64/SVE/uxtb.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x51, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uxtb z0.h, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x91, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uxtb z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uxtb z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x51, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uxtb z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x91, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uxtb z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xd1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uxtb z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uxtb z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uxtb z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x51, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uxtb z0.h, p0/m, z0.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x91, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uxtb z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uxtb z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x51, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uxtb z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x91, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uxtb z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xd1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uxtb z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uxtb z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uxtb z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/uxth.s.yaml b/tests/MC/AArch64/SVE/uxth.s.yaml new file mode 100644 index 0000000000..695af16cc2 --- /dev/null +++ b/tests/MC/AArch64/SVE/uxth.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x93, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uxth z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uxth z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x93, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uxth z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xd3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uxth z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uxth z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uxth z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x93, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uxth z0.s, p0/m, z0.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uxth z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x93, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uxth z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xd3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uxth z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uxth z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd3, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uxth z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/uxtw.s.yaml b/tests/MC/AArch64/SVE/uxtw.s.yaml new file mode 100644 index 0000000000..2eefa1d0d9 --- /dev/null +++ b/tests/MC/AArch64/SVE/uxtw.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uxtw z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xff, 0xbf, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uxtw z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uxtw z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uxtw z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0x00, 0xa0, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uxtw z0.d, p0/m, z0.d" + + - + input: + bytes: [ 0xff, 0xbf, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uxtw z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uxtw z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0xd5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uxtw z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE/uzp1.s.yaml b/tests/MC/AArch64/SVE/uzp1.s.yaml new file mode 100644 index 0000000000..5458b7ac6c --- /dev/null +++ b/tests/MC/AArch64/SVE/uzp1.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x6b, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uzp1 z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x6b, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uzp1 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x6b, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uzp1 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x6b, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uzp1 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0xef, 0x49, 0x2f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uzp1 p15.b, p15.b, p15.b" + + - + input: + bytes: [ 0xef, 0x49, 0xaf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uzp1 p15.s, p15.s, p15.s" + + - + input: + bytes: [ 0xef, 0x49, 0x6f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uzp1 p15.h, p15.h, p15.h" + + - + input: + bytes: [ 0xef, 0x49, 0xef, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uzp1 p15.d, p15.d, p15.d" + + - + input: + bytes: [ 0xff, 0x6b, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uzp1 z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x6b, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uzp1 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x6b, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uzp1 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x6b, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uzp1 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0xef, 0x49, 0x2f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uzp1 p15.b, p15.b, p15.b" + + - + input: + bytes: [ 0xef, 0x49, 0xaf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uzp1 p15.s, p15.s, p15.s" + + - + input: + bytes: [ 0xef, 0x49, 0x6f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uzp1 p15.h, p15.h, p15.h" + + - + input: + bytes: [ 0xef, 0x49, 0xef, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uzp1 p15.d, p15.d, p15.d" diff --git a/tests/MC/AArch64/SVE/uzp2.s.yaml b/tests/MC/AArch64/SVE/uzp2.s.yaml new file mode 100644 index 0000000000..506121c00b --- /dev/null +++ b/tests/MC/AArch64/SVE/uzp2.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x6f, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uzp2 z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x6f, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uzp2 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x6f, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uzp2 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x6f, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uzp2 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0xef, 0x4d, 0x2f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uzp2 p15.b, p15.b, p15.b" + + - + input: + bytes: [ 0xef, 0x4d, 0xaf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uzp2 p15.s, p15.s, p15.s" + + - + input: + bytes: [ 0xef, 0x4d, 0x6f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uzp2 p15.h, p15.h, p15.h" + + - + input: + bytes: [ 0xef, 0x4d, 0xef, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "uzp2 p15.d, p15.d, p15.d" + + - + input: + bytes: [ 0xff, 0x6f, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uzp2 z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x6f, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uzp2 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x6f, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uzp2 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x6f, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uzp2 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0xef, 0x4d, 0x2f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uzp2 p15.b, p15.b, p15.b" + + - + input: + bytes: [ 0xef, 0x4d, 0xaf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uzp2 p15.s, p15.s, p15.s" + + - + input: + bytes: [ 0xef, 0x4d, 0x6f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uzp2 p15.h, p15.h, p15.h" + + - + input: + bytes: [ 0xef, 0x4d, 0xef, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uzp2 p15.d, p15.d, p15.d" diff --git a/tests/MC/AArch64/SVE/whilele.s.yaml b/tests/MC/AArch64/SVE/whilele.s.yaml new file mode 100644 index 0000000000..ad9f0898a3 --- /dev/null +++ b/tests/MC/AArch64/SVE/whilele.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x17, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilele p15.b, xzr, x0" + + - + input: + bytes: [ 0x1f, 0x14, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilele p15.b, x0, xzr" + + - + input: + bytes: [ 0xff, 0x07, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilele p15.b, wzr, w0" + + - + input: + bytes: [ 0x1f, 0x04, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilele p15.b, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x14, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilele p15.h, x0, xzr" + + - + input: + bytes: [ 0x1f, 0x04, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilele p15.h, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x14, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilele p15.s, x0, xzr" + + - + input: + bytes: [ 0x1f, 0x04, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilele p15.s, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x04, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilele p15.d, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x14, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilele p15.d, x0, xzr" + + - + input: + bytes: [ 0xff, 0x17, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilele p15.b, xzr, x0" + + - + input: + bytes: [ 0x1f, 0x14, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilele p15.b, x0, xzr" + + - + input: + bytes: [ 0xff, 0x07, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilele p15.b, wzr, w0" + + - + input: + bytes: [ 0x1f, 0x04, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilele p15.b, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x14, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilele p15.h, x0, xzr" + + - + input: + bytes: [ 0x1f, 0x04, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilele p15.h, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x14, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilele p15.s, x0, xzr" + + - + input: + bytes: [ 0x1f, 0x04, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilele p15.s, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x04, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilele p15.d, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x14, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilele p15.d, x0, xzr" diff --git a/tests/MC/AArch64/SVE/whilelo.s.yaml b/tests/MC/AArch64/SVE/whilelo.s.yaml new file mode 100644 index 0000000000..fc4c7b68cf --- /dev/null +++ b/tests/MC/AArch64/SVE/whilelo.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0xef, 0x1f, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelo p15.b, xzr, x0" + + - + input: + bytes: [ 0x0f, 0x1c, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelo p15.b, x0, xzr" + + - + input: + bytes: [ 0xef, 0x0f, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelo p15.b, wzr, w0" + + - + input: + bytes: [ 0x0f, 0x0c, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelo p15.b, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x1c, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelo p15.h, x0, xzr" + + - + input: + bytes: [ 0x0f, 0x0c, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelo p15.h, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x1c, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelo p15.s, x0, xzr" + + - + input: + bytes: [ 0x0f, 0x0c, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelo p15.s, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x0c, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelo p15.d, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x1c, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelo p15.d, x0, xzr" + + - + input: + bytes: [ 0xef, 0x1f, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelo p15.b, xzr, x0" + + - + input: + bytes: [ 0x0f, 0x1c, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelo p15.b, x0, xzr" + + - + input: + bytes: [ 0xef, 0x0f, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelo p15.b, wzr, w0" + + - + input: + bytes: [ 0x0f, 0x0c, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelo p15.b, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x1c, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelo p15.h, x0, xzr" + + - + input: + bytes: [ 0x0f, 0x0c, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelo p15.h, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x1c, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelo p15.s, x0, xzr" + + - + input: + bytes: [ 0x0f, 0x0c, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelo p15.s, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x0c, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelo p15.d, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x1c, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelo p15.d, x0, xzr" diff --git a/tests/MC/AArch64/SVE/whilels.s.yaml b/tests/MC/AArch64/SVE/whilels.s.yaml new file mode 100644 index 0000000000..2e86a1f4ad --- /dev/null +++ b/tests/MC/AArch64/SVE/whilels.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x1f, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilels p15.b, xzr, x0" + + - + input: + bytes: [ 0x1f, 0x1c, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilels p15.b, x0, xzr" + + - + input: + bytes: [ 0xff, 0x0f, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilels p15.b, wzr, w0" + + - + input: + bytes: [ 0x1f, 0x0c, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilels p15.b, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x1c, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilels p15.h, x0, xzr" + + - + input: + bytes: [ 0x1f, 0x0c, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilels p15.h, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x1c, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilels p15.s, x0, xzr" + + - + input: + bytes: [ 0x1f, 0x0c, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilels p15.s, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x0c, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilels p15.d, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x1c, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilels p15.d, x0, xzr" + + - + input: + bytes: [ 0xff, 0x1f, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilels p15.b, xzr, x0" + + - + input: + bytes: [ 0x1f, 0x1c, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilels p15.b, x0, xzr" + + - + input: + bytes: [ 0xff, 0x0f, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilels p15.b, wzr, w0" + + - + input: + bytes: [ 0x1f, 0x0c, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilels p15.b, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x1c, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilels p15.h, x0, xzr" + + - + input: + bytes: [ 0x1f, 0x0c, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilels p15.h, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x1c, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilels p15.s, x0, xzr" + + - + input: + bytes: [ 0x1f, 0x0c, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilels p15.s, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x0c, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilels p15.d, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x1c, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilels p15.d, x0, xzr" diff --git a/tests/MC/AArch64/SVE/whilelt.s.yaml b/tests/MC/AArch64/SVE/whilelt.s.yaml new file mode 100644 index 0000000000..ea4cdc1bc8 --- /dev/null +++ b/tests/MC/AArch64/SVE/whilelt.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0xef, 0x17, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelt p15.b, xzr, x0" + + - + input: + bytes: [ 0x0f, 0x14, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelt p15.b, x0, xzr" + + - + input: + bytes: [ 0xef, 0x07, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelt p15.b, wzr, w0" + + - + input: + bytes: [ 0x0f, 0x04, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelt p15.b, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x14, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelt p15.h, x0, xzr" + + - + input: + bytes: [ 0x0f, 0x04, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelt p15.h, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x14, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelt p15.s, x0, xzr" + + - + input: + bytes: [ 0x0f, 0x04, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelt p15.s, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x04, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelt p15.d, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x14, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "whilelt p15.d, x0, xzr" + + - + input: + bytes: [ 0xef, 0x17, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelt p15.b, xzr, x0" + + - + input: + bytes: [ 0x0f, 0x14, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelt p15.b, x0, xzr" + + - + input: + bytes: [ 0xef, 0x07, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelt p15.b, wzr, w0" + + - + input: + bytes: [ 0x0f, 0x04, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelt p15.b, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x14, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelt p15.h, x0, xzr" + + - + input: + bytes: [ 0x0f, 0x04, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelt p15.h, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x14, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelt p15.s, x0, xzr" + + - + input: + bytes: [ 0x0f, 0x04, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelt p15.s, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x04, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelt p15.d, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x14, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilelt p15.d, x0, xzr" diff --git a/tests/MC/AArch64/SVE/wrffr.s.yaml b/tests/MC/AArch64/SVE/wrffr.s.yaml new file mode 100644 index 0000000000..7219e543cf --- /dev/null +++ b/tests/MC/AArch64/SVE/wrffr.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x90, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "wrffr p0.b" + + - + input: + bytes: [ 0xe0, 0x91, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "wrffr p15.b" diff --git a/tests/MC/AArch64/SVE/zip1.s.yaml b/tests/MC/AArch64/SVE/zip1.s.yaml new file mode 100644 index 0000000000..9e823704fe --- /dev/null +++ b/tests/MC/AArch64/SVE/zip1.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip1 z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip1 z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x60, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip1 z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x60, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip1 z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0xff, 0x63, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip1 z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x63, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip1 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x63, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip1 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x63, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip1 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0x40, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip1 p0.b, p0.b, p0.b" + + - + input: + bytes: [ 0x00, 0x40, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip1 p0.h, p0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x40, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip1 p0.s, p0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x40, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip1 p0.d, p0.d, p0.d" + + - + input: + bytes: [ 0xef, 0x41, 0x2f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip1 p15.b, p15.b, p15.b" + + - + input: + bytes: [ 0xef, 0x41, 0xaf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip1 p15.s, p15.s, p15.s" + + - + input: + bytes: [ 0xef, 0x41, 0x6f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip1 p15.h, p15.h, p15.h" + + - + input: + bytes: [ 0xef, 0x41, 0xef, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip1 p15.d, p15.d, p15.d" + + - + input: + bytes: [ 0x00, 0x60, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip1 z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip1 z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x60, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip1 z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x60, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip1 z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0xff, 0x63, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip1 z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x63, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip1 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x63, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip1 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x63, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip1 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0x40, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip1 p0.b, p0.b, p0.b" + + - + input: + bytes: [ 0x00, 0x40, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip1 p0.h, p0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x40, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip1 p0.s, p0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x40, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip1 p0.d, p0.d, p0.d" + + - + input: + bytes: [ 0xef, 0x41, 0x2f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip1 p15.b, p15.b, p15.b" + + - + input: + bytes: [ 0xef, 0x41, 0xaf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip1 p15.s, p15.s, p15.s" + + - + input: + bytes: [ 0xef, 0x41, 0x6f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip1 p15.h, p15.h, p15.h" + + - + input: + bytes: [ 0xef, 0x41, 0xef, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip1 p15.d, p15.d, p15.d" diff --git a/tests/MC/AArch64/SVE/zip2.s.yaml b/tests/MC/AArch64/SVE/zip2.s.yaml new file mode 100644 index 0000000000..0e629d4de5 --- /dev/null +++ b/tests/MC/AArch64/SVE/zip2.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x64, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip2 z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x64, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip2 z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x64, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip2 z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x64, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip2 z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0xff, 0x67, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip2 z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x67, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip2 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x67, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip2 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x67, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip2 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0x44, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip2 p0.b, p0.b, p0.b" + + - + input: + bytes: [ 0x00, 0x44, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip2 p0.h, p0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x44, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip2 p0.s, p0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x44, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip2 p0.d, p0.d, p0.d" + + - + input: + bytes: [ 0xef, 0x45, 0x2f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip2 p15.b, p15.b, p15.b" + + - + input: + bytes: [ 0xef, 0x45, 0x6f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip2 p15.h, p15.h, p15.h" + + - + input: + bytes: [ 0xef, 0x45, 0xaf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip2 p15.s, p15.s, p15.s" + + - + input: + bytes: [ 0xef, 0x45, 0xef, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ] + expected: + insns: + - + asm_text: "zip2 p15.d, p15.d, p15.d" + + - + input: + bytes: [ 0x00, 0x64, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip2 z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x64, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip2 z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x00, 0x64, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip2 z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x00, 0x64, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip2 z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0xff, 0x67, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip2 z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x67, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip2 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x67, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip2 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x67, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip2 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0x44, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip2 p0.b, p0.b, p0.b" + + - + input: + bytes: [ 0x00, 0x44, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip2 p0.h, p0.h, p0.h" + + - + input: + bytes: [ 0x00, 0x44, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip2 p0.s, p0.s, p0.s" + + - + input: + bytes: [ 0x00, 0x44, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip2 p0.d, p0.d, p0.d" + + - + input: + bytes: [ 0xef, 0x45, 0x2f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip2 p15.b, p15.b, p15.b" + + - + input: + bytes: [ 0xef, 0x45, 0x6f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip2 p15.h, p15.h, p15.h" + + - + input: + bytes: [ 0xef, 0x45, 0xaf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip2 p15.s, p15.s, p15.s" + + - + input: + bytes: [ 0xef, 0x45, 0xef, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "zip2 p15.d, p15.d, p15.d" diff --git a/tests/MC/AArch64/SVE2/adclb.s.yaml b/tests/MC/AArch64/SVE2/adclb.s.yaml new file mode 100644 index 0000000000..cb9ca50884 --- /dev/null +++ b/tests/MC/AArch64/SVE2/adclb.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xd0, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "adclb z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xd0, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "adclb z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xd0, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "adclb z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0xd0, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "adclb z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xd0, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "adclb z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xd0, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "adclb z0.d, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/adclt.s.yaml b/tests/MC/AArch64/SVE2/adclt.s.yaml new file mode 100644 index 0000000000..16ea9d0065 --- /dev/null +++ b/tests/MC/AArch64/SVE2/adclt.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xd4, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "adclt z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xd4, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "adclt z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xd4, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "adclt z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0xd4, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "adclt z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xd4, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "adclt z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xd4, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "adclt z0.d, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/addhnb.s.yaml b/tests/MC/AArch64/SVE2/addhnb.s.yaml new file mode 100644 index 0000000000..ba4c6091aa --- /dev/null +++ b/tests/MC/AArch64/SVE2/addhnb.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x60, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "addhnb z0.b, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x60, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "addhnb z0.h, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x60, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "addhnb z0.s, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x60, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addhnb z0.b, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x60, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addhnb z0.h, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x60, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addhnb z0.s, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/addhnt.s.yaml b/tests/MC/AArch64/SVE2/addhnt.s.yaml new file mode 100644 index 0000000000..a226519c83 --- /dev/null +++ b/tests/MC/AArch64/SVE2/addhnt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x64, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "addhnt z0.b, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x64, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "addhnt z0.h, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x64, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "addhnt z0.s, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x64, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addhnt z0.b, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x64, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addhnt z0.h, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x64, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addhnt z0.s, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/addp.s.yaml b/tests/MC/AArch64/SVE2/addp.s.yaml new file mode 100644 index 0000000000..5b11b5bd0f --- /dev/null +++ b/tests/MC/AArch64/SVE2/addp.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa0, 0x11, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "addp z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0xa0, 0x51, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "addp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0xbf, 0x91, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "addp z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd1, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "addp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0xa3, 0xd1, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "addp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd1, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "addp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0xa0, 0x11, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addp z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0xa0, 0x51, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0xbf, 0x91, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addp z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd1, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0xa3, 0xd1, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd1, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "addp z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/aesd.s.yaml b/tests/MC/AArch64/SVE2/aesd.s.yaml new file mode 100644 index 0000000000..e6fc763556 --- /dev/null +++ b/tests/MC/AArch64/SVE2/aesd.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xe7, 0x22, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-aes" ] + expected: + insns: + - + asm_text: "aesd z0.b, z0.b, z31.b" diff --git a/tests/MC/AArch64/SVE2/aese.s.yaml b/tests/MC/AArch64/SVE2/aese.s.yaml new file mode 100644 index 0000000000..16e950ec1e --- /dev/null +++ b/tests/MC/AArch64/SVE2/aese.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xe3, 0x22, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-aes" ] + expected: + insns: + - + asm_text: "aese z0.b, z0.b, z31.b" diff --git a/tests/MC/AArch64/SVE2/aesimc.s.yaml b/tests/MC/AArch64/SVE2/aesimc.s.yaml new file mode 100644 index 0000000000..82b860edae --- /dev/null +++ b/tests/MC/AArch64/SVE2/aesimc.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe4, 0x20, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-aes" ] + expected: + insns: + - + asm_text: "aesimc z0.b, z0.b" + + - + input: + bytes: [ 0x1f, 0xe4, 0x20, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-aes" ] + expected: + insns: + - + asm_text: "aesimc z31.b, z31.b" diff --git a/tests/MC/AArch64/SVE2/aesmc.s.yaml b/tests/MC/AArch64/SVE2/aesmc.s.yaml new file mode 100644 index 0000000000..ed0f8f25e8 --- /dev/null +++ b/tests/MC/AArch64/SVE2/aesmc.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-aes" ] + expected: + insns: + - + asm_text: "aesmc z0.b, z0.b" + + - + input: + bytes: [ 0x1f, 0xe0, 0x20, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-aes" ] + expected: + insns: + - + asm_text: "aesmc z31.b, z31.b" diff --git a/tests/MC/AArch64/SVE2/bcax.s.yaml b/tests/MC/AArch64/SVE2/bcax.s.yaml new file mode 100644 index 0000000000..0e06a84535 --- /dev/null +++ b/tests/MC/AArch64/SVE2/bcax.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0xfd, 0x3b, 0x7e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "bcax z29.d, z29.d, z30.d, z31.d" + + - + input: + bytes: [ 0xfd, 0x3b, 0x7e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "bcax z29.d, z29.d, z30.d, z31.d" + + - + input: + bytes: [ 0xfd, 0x3b, 0x7e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "bcax z29.d, z29.d, z30.d, z31.d" + + - + input: + bytes: [ 0xfd, 0x3b, 0x7e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "bcax z29.d, z29.d, z30.d, z31.d" + + - + input: + bytes: [ 0xff, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z7" + + - + input: + bytes: [ 0xbf, 0x3b, 0x7e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "bcax z31.d, z31.d, z30.d, z29.d" + + - + input: + bytes: [ 0xfd, 0x3b, 0x7e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bcax z29.d, z29.d, z30.d, z31.d" + + - + input: + bytes: [ 0xfd, 0x3b, 0x7e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bcax z29.d, z29.d, z30.d, z31.d" + + - + input: + bytes: [ 0xfd, 0x3b, 0x7e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bcax z29.d, z29.d, z30.d, z31.d" + + - + input: + bytes: [ 0xfd, 0x3b, 0x7e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bcax z29.d, z29.d, z30.d, z31.d" + + - + input: + bytes: [ 0xff, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z7" + + - + input: + bytes: [ 0xbf, 0x3b, 0x7e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bcax z31.d, z31.d, z30.d, z29.d" diff --git a/tests/MC/AArch64/SVE2/bdep.s.yaml b/tests/MC/AArch64/SVE2/bdep.s.yaml new file mode 100644 index 0000000000..47a2c81478 --- /dev/null +++ b/tests/MC/AArch64/SVE2/bdep.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xb4, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ] + expected: + insns: + - + asm_text: "bdep z0.b, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0xb4, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ] + expected: + insns: + - + asm_text: "bdep z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xb4, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ] + expected: + insns: + - + asm_text: "bdep z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xb4, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ] + expected: + insns: + - + asm_text: "bdep z0.d, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/bext.s.yaml b/tests/MC/AArch64/SVE2/bext.s.yaml new file mode 100644 index 0000000000..1e9e00767d --- /dev/null +++ b/tests/MC/AArch64/SVE2/bext.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xb0, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ] + expected: + insns: + - + asm_text: "bext z0.b, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0xb0, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ] + expected: + insns: + - + asm_text: "bext z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xb0, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ] + expected: + insns: + - + asm_text: "bext z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xb0, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ] + expected: + insns: + - + asm_text: "bext z0.d, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/bgrp.s.yaml b/tests/MC/AArch64/SVE2/bgrp.s.yaml new file mode 100644 index 0000000000..313af64983 --- /dev/null +++ b/tests/MC/AArch64/SVE2/bgrp.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xb8, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ] + expected: + insns: + - + asm_text: "bgrp z0.b, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0xb8, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ] + expected: + insns: + - + asm_text: "bgrp z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xb8, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ] + expected: + insns: + - + asm_text: "bgrp z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xb8, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ] + expected: + insns: + - + asm_text: "bgrp z0.d, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/bsl.s.yaml b/tests/MC/AArch64/SVE2/bsl.s.yaml new file mode 100644 index 0000000000..2418e8e0a7 --- /dev/null +++ b/tests/MC/AArch64/SVE2/bsl.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x40, 0x3c, 0x21, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "bsl z0.d, z0.d, z1.d, z2.d" + + - + input: + bytes: [ 0xff, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z7" + + - + input: + bytes: [ 0xbf, 0x3f, 0x3e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "bsl z31.d, z31.d, z30.d, z29.d" + + - + input: + bytes: [ 0x40, 0x3c, 0x21, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bsl z0.d, z0.d, z1.d, z2.d" + + - + input: + bytes: [ 0xff, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z7" + + - + input: + bytes: [ 0xbf, 0x3f, 0x3e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bsl z31.d, z31.d, z30.d, z29.d" diff --git a/tests/MC/AArch64/SVE2/bsl1n.s.yaml b/tests/MC/AArch64/SVE2/bsl1n.s.yaml new file mode 100644 index 0000000000..b26c075e99 --- /dev/null +++ b/tests/MC/AArch64/SVE2/bsl1n.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x40, 0x3c, 0x61, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "bsl1n z0.d, z0.d, z1.d, z2.d" + + - + input: + bytes: [ 0xff, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z7" + + - + input: + bytes: [ 0xbf, 0x3f, 0x7e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "bsl1n z31.d, z31.d, z30.d, z29.d" + + - + input: + bytes: [ 0x40, 0x3c, 0x61, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bsl1n z0.d, z0.d, z1.d, z2.d" + + - + input: + bytes: [ 0xff, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z7" + + - + input: + bytes: [ 0xbf, 0x3f, 0x7e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bsl1n z31.d, z31.d, z30.d, z29.d" diff --git a/tests/MC/AArch64/SVE2/bsl2n.s.yaml b/tests/MC/AArch64/SVE2/bsl2n.s.yaml new file mode 100644 index 0000000000..eeb01b4016 --- /dev/null +++ b/tests/MC/AArch64/SVE2/bsl2n.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x40, 0x3c, 0xa1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "bsl2n z0.d, z0.d, z1.d, z2.d" + + - + input: + bytes: [ 0xff, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z7" + + - + input: + bytes: [ 0xbf, 0x3f, 0xbe, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "bsl2n z31.d, z31.d, z30.d, z29.d" + + - + input: + bytes: [ 0x40, 0x3c, 0xa1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bsl2n z0.d, z0.d, z1.d, z2.d" + + - + input: + bytes: [ 0xff, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z7" + + - + input: + bytes: [ 0xbf, 0x3f, 0xbe, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "bsl2n z31.d, z31.d, z30.d, z29.d" diff --git a/tests/MC/AArch64/SVE2/cadd.s.yaml b/tests/MC/AArch64/SVE2/cadd.s.yaml new file mode 100644 index 0000000000..4e4efbcfb4 --- /dev/null +++ b/tests/MC/AArch64/SVE2/cadd.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xd8, 0x00, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cadd z0.b, z0.b, z0.b, #90" + + - + input: + bytes: [ 0x00, 0xd8, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cadd z0.h, z0.h, z0.h, #90" + + - + input: + bytes: [ 0x00, 0xd8, 0x80, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cadd z0.s, z0.s, z0.s, #90" + + - + input: + bytes: [ 0x00, 0xd8, 0xc0, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cadd z0.d, z0.d, z0.d, #90" + + - + input: + bytes: [ 0xff, 0xdf, 0x00, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cadd z31.b, z31.b, z31.b, #270" + + - + input: + bytes: [ 0xff, 0xdf, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cadd z31.h, z31.h, z31.h, #270" + + - + input: + bytes: [ 0xff, 0xdf, 0x80, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cadd z31.s, z31.s, z31.s, #270" + + - + input: + bytes: [ 0xff, 0xdf, 0xc0, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cadd z31.d, z31.d, z31.d, #270" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xdf, 0xc0, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cadd z4.d, z4.d, z31.d, #270" + + - + input: + bytes: [ 0x00, 0xd8, 0x00, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cadd z0.b, z0.b, z0.b, #90" + + - + input: + bytes: [ 0x00, 0xd8, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cadd z0.h, z0.h, z0.h, #90" + + - + input: + bytes: [ 0x00, 0xd8, 0x80, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cadd z0.s, z0.s, z0.s, #90" + + - + input: + bytes: [ 0x00, 0xd8, 0xc0, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cadd z0.d, z0.d, z0.d, #90" + + - + input: + bytes: [ 0xff, 0xdf, 0x00, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cadd z31.b, z31.b, z31.b, #270" + + - + input: + bytes: [ 0xff, 0xdf, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cadd z31.h, z31.h, z31.h, #270" + + - + input: + bytes: [ 0xff, 0xdf, 0x80, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cadd z31.s, z31.s, z31.s, #270" + + - + input: + bytes: [ 0xff, 0xdf, 0xc0, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cadd z31.d, z31.d, z31.d, #270" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xdf, 0xc0, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cadd z4.d, z4.d, z31.d, #270" diff --git a/tests/MC/AArch64/SVE2/cdot.s.yaml b/tests/MC/AArch64/SVE2/cdot.s.yaml new file mode 100644 index 0000000000..71b0432c1e --- /dev/null +++ b/tests/MC/AArch64/SVE2/cdot.s.yaml @@ -0,0 +1,280 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x10, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cdot z0.s, z1.b, z31.b, #0" + + - + input: + bytes: [ 0x20, 0x10, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cdot z0.d, z1.h, z31.h, #0" + + - + input: + bytes: [ 0x20, 0x14, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cdot z0.d, z1.h, z31.h, #90" + + - + input: + bytes: [ 0x20, 0x18, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cdot z0.d, z1.h, z31.h, #180" + + - + input: + bytes: [ 0x20, 0x1c, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cdot z0.d, z1.h, z31.h, #270" + + - + input: + bytes: [ 0x20, 0x40, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cdot z0.s, z1.b, z7.b[3], #0" + + - + input: + bytes: [ 0x20, 0x40, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cdot z0.d, z1.h, z15.h[1], #0" + + - + input: + bytes: [ 0xc5, 0x44, 0xe3, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cdot z5.d, z6.h, z3.h[0], #90" + + - + input: + bytes: [ 0xdd, 0x4b, 0xe0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cdot z29.d, z30.h, z0.h[0], #180" + + - + input: + bytes: [ 0xdf, 0x4f, 0xf7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cdot z31.d, z30.h, z7.h[1], #270" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x10, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cdot z0.d, z1.h, z31.h, #0" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x40, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cdot z0.d, z1.h, z15.h[1], #0" + + - + input: + bytes: [ 0x20, 0x10, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cdot z0.s, z1.b, z31.b, #0" + + - + input: + bytes: [ 0x20, 0x10, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cdot z0.d, z1.h, z31.h, #0" + + - + input: + bytes: [ 0x20, 0x14, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cdot z0.d, z1.h, z31.h, #90" + + - + input: + bytes: [ 0x20, 0x18, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cdot z0.d, z1.h, z31.h, #180" + + - + input: + bytes: [ 0x20, 0x1c, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cdot z0.d, z1.h, z31.h, #270" + + - + input: + bytes: [ 0x20, 0x40, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cdot z0.s, z1.b, z7.b[3], #0" + + - + input: + bytes: [ 0x20, 0x40, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cdot z0.d, z1.h, z15.h[1], #0" + + - + input: + bytes: [ 0xc5, 0x44, 0xe3, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cdot z5.d, z6.h, z3.h[0], #90" + + - + input: + bytes: [ 0xdd, 0x4b, 0xe0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cdot z29.d, z30.h, z0.h[0], #180" + + - + input: + bytes: [ 0xdf, 0x4f, 0xf7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cdot z31.d, z30.h, z7.h[1], #270" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x10, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cdot z0.d, z1.h, z31.h, #0" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x40, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cdot z0.d, z1.h, z15.h[1], #0" diff --git a/tests/MC/AArch64/SVE2/cmla.s.yaml b/tests/MC/AArch64/SVE2/cmla.s.yaml new file mode 100644 index 0000000000..a89487f4ae --- /dev/null +++ b/tests/MC/AArch64/SVE2/cmla.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x20, 0x02, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z0.b, z1.b, z2.b, #0" + + - + input: + bytes: [ 0x20, 0x20, 0x42, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z0.h, z1.h, z2.h, #0" + + - + input: + bytes: [ 0x20, 0x20, 0x82, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z0.s, z1.s, z2.s, #0" + + - + input: + bytes: [ 0x20, 0x20, 0xc2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z0.d, z1.d, z2.d, #0" + + - + input: + bytes: [ 0xdd, 0x27, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z29.b, z30.b, z31.b, #90" + + - + input: + bytes: [ 0xdd, 0x27, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z29.h, z30.h, z31.h, #90" + + - + input: + bytes: [ 0xdd, 0x27, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z29.s, z30.s, z31.s, #90" + + - + input: + bytes: [ 0xdd, 0x27, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z29.d, z30.d, z31.d, #90" + + - + input: + bytes: [ 0xff, 0x2b, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z31.b, z31.b, z31.b, #180" + + - + input: + bytes: [ 0xff, 0x2b, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z31.h, z31.h, z31.h, #180" + + - + input: + bytes: [ 0xff, 0x2b, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z31.s, z31.s, z31.s, #180" + + - + input: + bytes: [ 0xff, 0x2b, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z31.d, z31.d, z31.d, #180" + + - + input: + bytes: [ 0x0f, 0x2e, 0x11, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z15.b, z16.b, z17.b, #270" + + - + input: + bytes: [ 0x0f, 0x2e, 0x51, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z15.h, z16.h, z17.h, #270" + + - + input: + bytes: [ 0x0f, 0x2e, 0x91, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z15.s, z16.s, z17.s, #270" + + - + input: + bytes: [ 0x0f, 0x2e, 0xd1, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z15.d, z16.d, z17.d, #270" + + - + input: + bytes: [ 0x20, 0x60, 0xa2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z0.h, z1.h, z2.h[0], #0" + + - + input: + bytes: [ 0x20, 0x60, 0xe2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z0.s, z1.s, z2.s[0], #0" + + - + input: + bytes: [ 0xdf, 0x6b, 0xa7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z31.h, z30.h, z7.h[0], #180" + + - + input: + bytes: [ 0xdf, 0x6b, 0xe7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z31.s, z30.s, z7.s[0], #180" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x2f, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z4.d, z31.d, z31.d, #270" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x65, 0xf5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "cmla z21.s, z10.s, z5.s[1], #90" + + - + input: + bytes: [ 0x20, 0x20, 0x02, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z0.b, z1.b, z2.b, #0" + + - + input: + bytes: [ 0x20, 0x20, 0x42, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z0.h, z1.h, z2.h, #0" + + - + input: + bytes: [ 0x20, 0x20, 0x82, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z0.s, z1.s, z2.s, #0" + + - + input: + bytes: [ 0x20, 0x20, 0xc2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z0.d, z1.d, z2.d, #0" + + - + input: + bytes: [ 0xdd, 0x27, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z29.b, z30.b, z31.b, #90" + + - + input: + bytes: [ 0xdd, 0x27, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z29.h, z30.h, z31.h, #90" + + - + input: + bytes: [ 0xdd, 0x27, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z29.s, z30.s, z31.s, #90" + + - + input: + bytes: [ 0xdd, 0x27, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z29.d, z30.d, z31.d, #90" + + - + input: + bytes: [ 0xff, 0x2b, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z31.b, z31.b, z31.b, #180" + + - + input: + bytes: [ 0xff, 0x2b, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z31.h, z31.h, z31.h, #180" + + - + input: + bytes: [ 0xff, 0x2b, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z31.s, z31.s, z31.s, #180" + + - + input: + bytes: [ 0xff, 0x2b, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z31.d, z31.d, z31.d, #180" + + - + input: + bytes: [ 0x0f, 0x2e, 0x11, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z15.b, z16.b, z17.b, #270" + + - + input: + bytes: [ 0x0f, 0x2e, 0x51, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z15.h, z16.h, z17.h, #270" + + - + input: + bytes: [ 0x0f, 0x2e, 0x91, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z15.s, z16.s, z17.s, #270" + + - + input: + bytes: [ 0x0f, 0x2e, 0xd1, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z15.d, z16.d, z17.d, #270" + + - + input: + bytes: [ 0x20, 0x60, 0xa2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z0.h, z1.h, z2.h[0], #0" + + - + input: + bytes: [ 0x20, 0x60, 0xe2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z0.s, z1.s, z2.s[0], #0" + + - + input: + bytes: [ 0xdf, 0x6b, 0xa7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z31.h, z30.h, z7.h[0], #180" + + - + input: + bytes: [ 0xdf, 0x6b, 0xe7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z31.s, z30.s, z7.s[0], #180" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x2f, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z4.d, z31.d, z31.d, #270" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x65, 0xf5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "cmla z21.s, z10.s, z5.s[1], #90" diff --git a/tests/MC/AArch64/SVE2/eor3.s.yaml b/tests/MC/AArch64/SVE2/eor3.s.yaml new file mode 100644 index 0000000000..c964b323aa --- /dev/null +++ b/tests/MC/AArch64/SVE2/eor3.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0xfd, 0x3b, 0x3e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "eor3 z29.d, z29.d, z30.d, z31.d" + + - + input: + bytes: [ 0xfd, 0x3b, 0x3e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "eor3 z29.d, z29.d, z30.d, z31.d" + + - + input: + bytes: [ 0xfd, 0x3b, 0x3e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "eor3 z29.d, z29.d, z30.d, z31.d" + + - + input: + bytes: [ 0xfd, 0x3b, 0x3e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "eor3 z29.d, z29.d, z30.d, z31.d" + + - + input: + bytes: [ 0xff, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z7" + + - + input: + bytes: [ 0xbf, 0x3b, 0x3e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "eor3 z31.d, z31.d, z30.d, z29.d" + + - + input: + bytes: [ 0xfd, 0x3b, 0x3e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor3 z29.d, z29.d, z30.d, z31.d" + + - + input: + bytes: [ 0xfd, 0x3b, 0x3e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor3 z29.d, z29.d, z30.d, z31.d" + + - + input: + bytes: [ 0xfd, 0x3b, 0x3e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor3 z29.d, z29.d, z30.d, z31.d" + + - + input: + bytes: [ 0xfd, 0x3b, 0x3e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor3 z29.d, z29.d, z30.d, z31.d" + + - + input: + bytes: [ 0xff, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z7" + + - + input: + bytes: [ 0xbf, 0x3b, 0x3e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eor3 z31.d, z31.d, z30.d, z29.d" diff --git a/tests/MC/AArch64/SVE2/eorbt.s.yaml b/tests/MC/AArch64/SVE2/eorbt.s.yaml new file mode 100644 index 0000000000..982e68b504 --- /dev/null +++ b/tests/MC/AArch64/SVE2/eorbt.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x90, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "eorbt z0.b, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x90, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "eorbt z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x90, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "eorbt z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x90, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "eorbt z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x90, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "eorbt z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x90, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eorbt z0.b, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x90, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eorbt z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x90, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eorbt z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x90, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eorbt z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x90, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eorbt z0.d, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/eortb.s.yaml b/tests/MC/AArch64/SVE2/eortb.s.yaml new file mode 100644 index 0000000000..a60ee99ec0 --- /dev/null +++ b/tests/MC/AArch64/SVE2/eortb.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x94, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "eortb z0.b, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x94, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "eortb z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x94, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "eortb z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x94, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "eortb z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x94, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "eortb z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x94, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eortb z0.b, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x94, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eortb z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x94, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eortb z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x94, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eortb z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x94, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "eortb z0.d, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/ext.s.yaml b/tests/MC/AArch64/SVE2/ext.s.yaml new file mode 100644 index 0000000000..1a0f647e20 --- /dev/null +++ b/tests/MC/AArch64/SVE2/ext.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x00, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ext z0.b, { z1.b, z2.b }, #0" + + - + input: + bytes: [ 0xdf, 0x1f, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ext z31.b, { z30.b, z31.b }, #255" + + - + input: + bytes: [ 0x20, 0x00, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ext z0.b, { z1.b, z2.b }, #0" + + - + input: + bytes: [ 0xdf, 0x1f, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ext z31.b, { z30.b, z31.b }, #255" diff --git a/tests/MC/AArch64/SVE2/faddp.s.yaml b/tests/MC/AArch64/SVE2/faddp.s.yaml new file mode 100644 index 0000000000..44392e50af --- /dev/null +++ b/tests/MC/AArch64/SVE2/faddp.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x50, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "faddp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x8f, 0x90, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "faddp z29.s, p3/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "faddp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "faddp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "faddp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x50, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "faddp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x8f, 0x90, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "faddp z29.s, p3/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "faddp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "faddp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "faddp z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/fcvtlt.s.yaml b/tests/MC/AArch64/SVE2/fcvtlt.s.yaml new file mode 100644 index 0000000000..43bdb9807b --- /dev/null +++ b/tests/MC/AArch64/SVE2/fcvtlt.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa0, 0x89, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fcvtlt z0.s, p0/m, z1.h" + + - + input: + bytes: [ 0xfe, 0xbf, 0xcb, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fcvtlt z30.d, p7/m, z31.s" + + - + input: + bytes: [ 0x20, 0xa0, 0x89, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtlt z0.s, p0/m, z1.h" + + - + input: + bytes: [ 0xfe, 0xbf, 0xcb, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtlt z30.d, p7/m, z31.s" diff --git a/tests/MC/AArch64/SVE2/fcvtnt.s.yaml b/tests/MC/AArch64/SVE2/fcvtnt.s.yaml new file mode 100644 index 0000000000..d89c1c160b --- /dev/null +++ b/tests/MC/AArch64/SVE2/fcvtnt.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa0, 0x88, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fcvtnt z0.h, p0/m, z1.s" + + - + input: + bytes: [ 0xfe, 0xbf, 0xca, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fcvtnt z30.s, p7/m, z31.d" + + - + input: + bytes: [ 0x20, 0xa0, 0x88, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtnt z0.h, p0/m, z1.s" + + - + input: + bytes: [ 0xfe, 0xbf, 0xca, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtnt z30.s, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE2/fcvtx.s.yaml b/tests/MC/AArch64/SVE2/fcvtx.s.yaml new file mode 100644 index 0000000000..ebdea65637 --- /dev/null +++ b/tests/MC/AArch64/SVE2/fcvtx.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fcvtx z0.s, p0/m, z0.d" + + - + input: + bytes: [ 0xfe, 0xbf, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fcvtx z30.s, p7/m, z31.d" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0xa0, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fcvtx z5.s, p0/m, z0.d" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0xa0, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fcvtx z5.s, p0/m, z0.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtx z0.s, p0/m, z0.d" + + - + input: + bytes: [ 0xfe, 0xbf, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtx z30.s, p7/m, z31.d" + + - + input: + bytes: [ 0xe5, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5.d, p0/z, z7.d" + + - + input: + bytes: [ 0x05, 0xa0, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtx z5.s, p0/m, z0.d" + + - + input: + bytes: [ 0xe5, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z5, z7" + + - + input: + bytes: [ 0x05, 0xa0, 0x0a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtx z5.s, p0/m, z0.d" diff --git a/tests/MC/AArch64/SVE2/fcvtxnt.s.yaml b/tests/MC/AArch64/SVE2/fcvtxnt.s.yaml new file mode 100644 index 0000000000..69be85badf --- /dev/null +++ b/tests/MC/AArch64/SVE2/fcvtxnt.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa0, 0x0a, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fcvtxnt z0.s, p0/m, z1.d" + + - + input: + bytes: [ 0xfe, 0xbf, 0x0a, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fcvtxnt z30.s, p7/m, z31.d" + + - + input: + bytes: [ 0x20, 0xa0, 0x0a, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtxnt z0.s, p0/m, z1.d" + + - + input: + bytes: [ 0xfe, 0xbf, 0x0a, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fcvtxnt z30.s, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE2/flogb.s.yaml b/tests/MC/AArch64/SVE2/flogb.s.yaml new file mode 100644 index 0000000000..a7dd8d5b19 --- /dev/null +++ b/tests/MC/AArch64/SVE2/flogb.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x1a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "flogb z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x1c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "flogb z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0x1e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "flogb z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0x1e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "flogb z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0x1e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "flogb z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xff, 0xbf, 0x1a, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "flogb z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x1c, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "flogb z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0x1e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "flogb z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.d, p7/z, z6.d" + + - + input: + bytes: [ 0xe4, 0xbf, 0x1e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "flogb z4.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0x1e, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "flogb z4.d, p7/m, z31.d" diff --git a/tests/MC/AArch64/SVE2/fmaxnmp.s.yaml b/tests/MC/AArch64/SVE2/fmaxnmp.s.yaml new file mode 100644 index 0000000000..bf027df719 --- /dev/null +++ b/tests/MC/AArch64/SVE2/fmaxnmp.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x54, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmaxnmp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x8f, 0x94, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmaxnmp z29.s, p3/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd4, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmaxnmp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd4, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmaxnmp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd4, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmaxnmp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x54, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnmp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x8f, 0x94, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnmp z29.s, p3/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd4, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnmp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd4, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnmp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd4, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxnmp z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/fmaxp.s.yaml b/tests/MC/AArch64/SVE2/fmaxp.s.yaml new file mode 100644 index 0000000000..7c3d89fa95 --- /dev/null +++ b/tests/MC/AArch64/SVE2/fmaxp.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x56, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmaxp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x8f, 0x96, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmaxp z29.s, p3/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd6, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmaxp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd6, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmaxp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd6, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmaxp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x56, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x8f, 0x96, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxp z29.s, p3/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd6, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd6, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd6, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmaxp z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/fminnmp.s.yaml b/tests/MC/AArch64/SVE2/fminnmp.s.yaml new file mode 100644 index 0000000000..0e17c48876 --- /dev/null +++ b/tests/MC/AArch64/SVE2/fminnmp.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x55, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fminnmp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x8f, 0x95, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fminnmp z29.s, p3/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fminnmp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fminnmp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fminnmp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x55, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnmp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x8f, 0x95, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnmp z29.s, p3/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnmp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnmp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminnmp z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/fminp.s.yaml b/tests/MC/AArch64/SVE2/fminp.s.yaml new file mode 100644 index 0000000000..fac5dda79e --- /dev/null +++ b/tests/MC/AArch64/SVE2/fminp.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x57, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fminp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x8f, 0x97, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fminp z29.s, p3/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fminp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fminp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fminp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x57, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x8f, 0x97, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminp z29.s, p3/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fminp z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/fmlalb.s.yaml b/tests/MC/AArch64/SVE2/fmlalb.s.yaml new file mode 100644 index 0000000000..f4507ee0e0 --- /dev/null +++ b/tests/MC/AArch64/SVE2/fmlalb.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xdd, 0x83, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlalb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0x20, 0x40, 0xa7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlalb z0.s, z1.h, z7.h[0]" + + - + input: + bytes: [ 0xfe, 0x4b, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlalb z30.s, z31.h, z7.h[7]" + + - + input: + bytes: [ 0x9d, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z29, z28" + + - + input: + bytes: [ 0xdd, 0x83, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlalb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x48, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlalb z21.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0xdd, 0x83, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlalb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0x20, 0x40, 0xa7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlalb z0.s, z1.h, z7.h[0]" + + - + input: + bytes: [ 0xfe, 0x4b, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlalb z30.s, z31.h, z7.h[7]" + + - + input: + bytes: [ 0x9d, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z29, z28" + + - + input: + bytes: [ 0xdd, 0x83, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlalb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x48, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlalb z21.s, z1.h, z7.h[7]" diff --git a/tests/MC/AArch64/SVE2/fmlalt.s.yaml b/tests/MC/AArch64/SVE2/fmlalt.s.yaml new file mode 100644 index 0000000000..352c87da57 --- /dev/null +++ b/tests/MC/AArch64/SVE2/fmlalt.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xdd, 0x87, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlalt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0x20, 0x44, 0xa7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlalt z0.s, z1.h, z7.h[0]" + + - + input: + bytes: [ 0xfe, 0x4f, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlalt z30.s, z31.h, z7.h[7]" + + - + input: + bytes: [ 0x9d, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z29, z28" + + - + input: + bytes: [ 0xdd, 0x87, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlalt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x4c, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlalt z21.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0xdd, 0x87, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlalt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0x20, 0x44, 0xa7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlalt z0.s, z1.h, z7.h[0]" + + - + input: + bytes: [ 0xfe, 0x4f, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlalt z30.s, z31.h, z7.h[7]" + + - + input: + bytes: [ 0x9d, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z29, z28" + + - + input: + bytes: [ 0xdd, 0x87, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlalt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x4c, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlalt z21.s, z1.h, z7.h[7]" diff --git a/tests/MC/AArch64/SVE2/fmlslb.s.yaml b/tests/MC/AArch64/SVE2/fmlslb.s.yaml new file mode 100644 index 0000000000..3b43e7c340 --- /dev/null +++ b/tests/MC/AArch64/SVE2/fmlslb.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xdd, 0xa3, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlslb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0x20, 0x60, 0xa7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlslb z0.s, z1.h, z7.h[0]" + + - + input: + bytes: [ 0xfe, 0x6b, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlslb z30.s, z31.h, z7.h[7]" + + - + input: + bytes: [ 0x9d, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z29, z28" + + - + input: + bytes: [ 0xdd, 0xa3, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlslb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x68, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlslb z21.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0xdd, 0xa3, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlslb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0x20, 0x60, 0xa7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlslb z0.s, z1.h, z7.h[0]" + + - + input: + bytes: [ 0xfe, 0x6b, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlslb z30.s, z31.h, z7.h[7]" + + - + input: + bytes: [ 0x9d, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z29, z28" + + - + input: + bytes: [ 0xdd, 0xa3, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlslb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x68, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlslb z21.s, z1.h, z7.h[7]" diff --git a/tests/MC/AArch64/SVE2/fmlslt.s.yaml b/tests/MC/AArch64/SVE2/fmlslt.s.yaml new file mode 100644 index 0000000000..328406a2fb --- /dev/null +++ b/tests/MC/AArch64/SVE2/fmlslt.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xdd, 0xa7, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlslt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0x20, 0x64, 0xa7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlslt z0.s, z1.h, z7.h[0]" + + - + input: + bytes: [ 0xfe, 0x6f, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlslt z30.s, z31.h, z7.h[7]" + + - + input: + bytes: [ 0x9d, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z29, z28" + + - + input: + bytes: [ 0xdd, 0xa7, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlslt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x6c, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "fmlslt z21.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0xdd, 0xa7, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlslt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0x20, 0x64, 0xa7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlslt z0.s, z1.h, z7.h[0]" + + - + input: + bytes: [ 0xfe, 0x6f, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlslt z30.s, z31.h, z7.h[7]" + + - + input: + bytes: [ 0x9d, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z29, z28" + + - + input: + bytes: [ 0xdd, 0xa7, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlslt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x6c, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "fmlslt z21.s, z1.h, z7.h[7]" diff --git a/tests/MC/AArch64/SVE2/histcnt.s.yaml b/tests/MC/AArch64/SVE2/histcnt.s.yaml new file mode 100644 index 0000000000..dc9b9c36cd --- /dev/null +++ b/tests/MC/AArch64/SVE2/histcnt.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xc0, 0xa2, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "histcnt z0.s, p0/z, z1.s, z2.s" + + - + input: + bytes: [ 0xdd, 0xdf, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "histcnt z29.d, p7/z, z30.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/histseg.s.yaml b/tests/MC/AArch64/SVE2/histseg.s.yaml new file mode 100644 index 0000000000..ebb249852d --- /dev/null +++ b/tests/MC/AArch64/SVE2/histseg.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa0, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "histseg z0.b, z1.b, z31.b" diff --git a/tests/MC/AArch64/SVE2/ldnt1b.s.yaml b/tests/MC/AArch64/SVE2/ldnt1b.s.yaml new file mode 100644 index 0000000000..334e404442 --- /dev/null +++ b/tests/MC/AArch64/SVE2/ldnt1b.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa0, 0x1f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.s }, p0/z, [z1.s]" + + - + input: + bytes: [ 0xff, 0xbf, 0x1f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1b { z31.s }, p7/z, [z31.s]" + + - + input: + bytes: [ 0xff, 0xbf, 0x00, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1b { z31.s }, p7/z, [z31.s, x0]" + + - + input: + bytes: [ 0x20, 0xc0, 0x1f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.d }, p0/z, [z1.d]" + + - + input: + bytes: [ 0xff, 0xdf, 0x1f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1b { z31.d }, p7/z, [z31.d]" + + - + input: + bytes: [ 0xff, 0xdf, 0x00, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1b { z31.d }, p7/z, [z31.d, x0]" + + - + input: + bytes: [ 0x20, 0xa0, 0x1f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.s }, p0/z, [z1.s]" + + - + input: + bytes: [ 0xff, 0xbf, 0x1f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1b { z31.s }, p7/z, [z31.s]" + + - + input: + bytes: [ 0xff, 0xbf, 0x00, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1b { z31.s }, p7/z, [z31.s, x0]" + + - + input: + bytes: [ 0x20, 0xc0, 0x1f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.d }, p0/z, [z1.d]" + + - + input: + bytes: [ 0xff, 0xdf, 0x1f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1b { z31.d }, p7/z, [z31.d]" + + - + input: + bytes: [ 0xff, 0xdf, 0x00, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1b { z31.d }, p7/z, [z31.d, x0]" diff --git a/tests/MC/AArch64/SVE2/ldnt1d.s.yaml b/tests/MC/AArch64/SVE2/ldnt1d.s.yaml new file mode 100644 index 0000000000..7b0cfefa21 --- /dev/null +++ b/tests/MC/AArch64/SVE2/ldnt1d.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xc0, 0x9f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d }, p0/z, [z1.d]" + + - + input: + bytes: [ 0xff, 0xdf, 0x9f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1d { z31.d }, p7/z, [z31.d]" + + - + input: + bytes: [ 0xff, 0xdf, 0x80, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1d { z31.d }, p7/z, [z31.d, x0]" + + - + input: + bytes: [ 0x20, 0xc0, 0x9f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d }, p0/z, [z1.d]" + + - + input: + bytes: [ 0xff, 0xdf, 0x9f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1d { z31.d }, p7/z, [z31.d]" + + - + input: + bytes: [ 0xff, 0xdf, 0x80, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1d { z31.d }, p7/z, [z31.d, x0]" diff --git a/tests/MC/AArch64/SVE2/ldnt1h.s.yaml b/tests/MC/AArch64/SVE2/ldnt1h.s.yaml new file mode 100644 index 0000000000..900a32ce94 --- /dev/null +++ b/tests/MC/AArch64/SVE2/ldnt1h.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa0, 0x9f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.s }, p0/z, [z1.s]" + + - + input: + bytes: [ 0xff, 0xbf, 0x9f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1h { z31.s }, p7/z, [z31.s]" + + - + input: + bytes: [ 0xff, 0xbf, 0x80, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1h { z31.s }, p7/z, [z31.s, x0]" + + - + input: + bytes: [ 0x20, 0xc0, 0x9f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.d }, p0/z, [z1.d]" + + - + input: + bytes: [ 0xff, 0xdf, 0x9f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1h { z31.d }, p7/z, [z31.d]" + + - + input: + bytes: [ 0xff, 0xdf, 0x80, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1h { z31.d }, p7/z, [z31.d, x0]" + + - + input: + bytes: [ 0x20, 0xa0, 0x9f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.s }, p0/z, [z1.s]" + + - + input: + bytes: [ 0xff, 0xbf, 0x9f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1h { z31.s }, p7/z, [z31.s]" + + - + input: + bytes: [ 0xff, 0xbf, 0x80, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1h { z31.s }, p7/z, [z31.s, x0]" + + - + input: + bytes: [ 0x20, 0xc0, 0x9f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.d }, p0/z, [z1.d]" + + - + input: + bytes: [ 0xff, 0xdf, 0x9f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1h { z31.d }, p7/z, [z31.d]" + + - + input: + bytes: [ 0xff, 0xdf, 0x80, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1h { z31.d }, p7/z, [z31.d, x0]" diff --git a/tests/MC/AArch64/SVE2/ldnt1sb.s.yaml b/tests/MC/AArch64/SVE2/ldnt1sb.s.yaml new file mode 100644 index 0000000000..3c2db793fe --- /dev/null +++ b/tests/MC/AArch64/SVE2/ldnt1sb.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x1f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sb { z0.s }, p0/z, [z1.s]" + + - + input: + bytes: [ 0xff, 0x9f, 0x1f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sb { z31.s }, p7/z, [z31.s]" + + - + input: + bytes: [ 0xff, 0x9f, 0x00, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sb { z31.s }, p7/z, [z31.s, x0]" + + - + input: + bytes: [ 0x20, 0x80, 0x1f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sb { z0.d }, p0/z, [z1.d]" + + - + input: + bytes: [ 0xff, 0x9f, 0x1f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sb { z31.d }, p7/z, [z31.d]" + + - + input: + bytes: [ 0xff, 0x9f, 0x00, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sb { z31.d }, p7/z, [z31.d, x0]" + + - + input: + bytes: [ 0x20, 0x80, 0x1f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sb { z0.s }, p0/z, [z1.s]" + + - + input: + bytes: [ 0xff, 0x9f, 0x1f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sb { z31.s }, p7/z, [z31.s]" + + - + input: + bytes: [ 0xff, 0x9f, 0x00, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sb { z31.s }, p7/z, [z31.s, x0]" + + - + input: + bytes: [ 0x20, 0x80, 0x1f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sb { z0.d }, p0/z, [z1.d]" + + - + input: + bytes: [ 0xff, 0x9f, 0x1f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sb { z31.d }, p7/z, [z31.d]" + + - + input: + bytes: [ 0xff, 0x9f, 0x00, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sb { z31.d }, p7/z, [z31.d, x0]" diff --git a/tests/MC/AArch64/SVE2/ldnt1sh.s.yaml b/tests/MC/AArch64/SVE2/ldnt1sh.s.yaml new file mode 100644 index 0000000000..4e665de6ea --- /dev/null +++ b/tests/MC/AArch64/SVE2/ldnt1sh.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x9f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sh { z0.s }, p0/z, [z1.s]" + + - + input: + bytes: [ 0xff, 0x9f, 0x9f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sh { z31.s }, p7/z, [z31.s]" + + - + input: + bytes: [ 0xff, 0x9f, 0x80, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sh { z31.s }, p7/z, [z31.s, x0]" + + - + input: + bytes: [ 0x20, 0x80, 0x9f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sh { z0.d }, p0/z, [z1.d]" + + - + input: + bytes: [ 0xff, 0x9f, 0x9f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sh { z31.d }, p7/z, [z31.d]" + + - + input: + bytes: [ 0xff, 0x9f, 0x80, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sh { z31.d }, p7/z, [z31.d, x0]" + + - + input: + bytes: [ 0x20, 0x80, 0x9f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sh { z0.s }, p0/z, [z1.s]" + + - + input: + bytes: [ 0xff, 0x9f, 0x9f, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sh { z31.s }, p7/z, [z31.s]" + + - + input: + bytes: [ 0xff, 0x9f, 0x80, 0x84 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sh { z31.s }, p7/z, [z31.s, x0]" + + - + input: + bytes: [ 0x20, 0x80, 0x9f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sh { z0.d }, p0/z, [z1.d]" + + - + input: + bytes: [ 0xff, 0x9f, 0x9f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sh { z31.d }, p7/z, [z31.d]" + + - + input: + bytes: [ 0xff, 0x9f, 0x80, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sh { z31.d }, p7/z, [z31.d, x0]" diff --git a/tests/MC/AArch64/SVE2/ldnt1sw.s.yaml b/tests/MC/AArch64/SVE2/ldnt1sw.s.yaml new file mode 100644 index 0000000000..aca6b0219a --- /dev/null +++ b/tests/MC/AArch64/SVE2/ldnt1sw.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x1f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sw { z0.d }, p0/z, [z1.d]" + + - + input: + bytes: [ 0xff, 0x9f, 0x1f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sw { z31.d }, p7/z, [z31.d]" + + - + input: + bytes: [ 0xff, 0x9f, 0x00, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sw { z31.d }, p7/z, [z31.d, x0]" + + - + input: + bytes: [ 0x20, 0x80, 0x1f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sw { z0.d }, p0/z, [z1.d]" + + - + input: + bytes: [ 0xff, 0x9f, 0x1f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sw { z31.d }, p7/z, [z31.d]" + + - + input: + bytes: [ 0xff, 0x9f, 0x00, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1sw { z31.d }, p7/z, [z31.d, x0]" diff --git a/tests/MC/AArch64/SVE2/ldnt1w.s.yaml b/tests/MC/AArch64/SVE2/ldnt1w.s.yaml new file mode 100644 index 0000000000..62bcd561eb --- /dev/null +++ b/tests/MC/AArch64/SVE2/ldnt1w.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa0, 0x1f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s }, p0/z, [z1.s]" + + - + input: + bytes: [ 0xff, 0xbf, 0x1f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1w { z31.s }, p7/z, [z31.s]" + + - + input: + bytes: [ 0xff, 0xbf, 0x00, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1w { z31.s }, p7/z, [z31.s, x0]" + + - + input: + bytes: [ 0x20, 0xc0, 0x1f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.d }, p0/z, [z1.d]" + + - + input: + bytes: [ 0xff, 0xdf, 0x1f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1w { z31.d }, p7/z, [z31.d]" + + - + input: + bytes: [ 0xff, 0xdf, 0x00, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1w { z31.d }, p7/z, [z31.d, x0]" + + - + input: + bytes: [ 0x20, 0xa0, 0x1f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s }, p0/z, [z1.s]" + + - + input: + bytes: [ 0xff, 0xbf, 0x1f, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1w { z31.s }, p7/z, [z31.s]" + + - + input: + bytes: [ 0xff, 0xbf, 0x00, 0x85 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1w { z31.s }, p7/z, [z31.s, x0]" + + - + input: + bytes: [ 0x20, 0xc0, 0x1f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.d }, p0/z, [z1.d]" + + - + input: + bytes: [ 0xff, 0xdf, 0x1f, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1w { z31.d }, p7/z, [z31.d]" + + - + input: + bytes: [ 0xff, 0xdf, 0x00, 0xc5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ldnt1w { z31.d }, p7/z, [z31.d, x0]" diff --git a/tests/MC/AArch64/SVE2/match.s.yaml b/tests/MC/AArch64/SVE2/match.s.yaml new file mode 100644 index 0000000000..47746efb54 --- /dev/null +++ b/tests/MC/AArch64/SVE2/match.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x20, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "match p0.b, p0/z, z0.b, z0.b" + + - + input: + bytes: [ 0x00, 0x80, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "match p0.h, p0/z, z0.h, z0.h" + + - + input: + bytes: [ 0xcf, 0x9f, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "match p15.b, p7/z, z30.b, z31.b" + + - + input: + bytes: [ 0xcf, 0x9f, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "match p15.h, p7/z, z30.h, z31.h" diff --git a/tests/MC/AArch64/SVE2/mla.s.yaml b/tests/MC/AArch64/SVE2/mla.s.yaml new file mode 100644 index 0000000000..36bd77cef2 --- /dev/null +++ b/tests/MC/AArch64/SVE2/mla.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x08, 0x7f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "mla z0.h, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x08, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "mla z0.s, z1.s, z7.s[3]" + + - + input: + bytes: [ 0x20, 0x08, 0xf7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "mla z0.d, z1.d, z7.d[1]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x08, 0xf7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "mla z0.d, z1.d, z7.d[1]" + + - + input: + bytes: [ 0x20, 0x08, 0x7f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mla z0.h, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x08, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mla z0.s, z1.s, z7.s[3]" + + - + input: + bytes: [ 0x20, 0x08, 0xf7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mla z0.d, z1.d, z7.d[1]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x08, 0xf7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mla z0.d, z1.d, z7.d[1]" diff --git a/tests/MC/AArch64/SVE2/mls.s.yaml b/tests/MC/AArch64/SVE2/mls.s.yaml new file mode 100644 index 0000000000..c50b569b90 --- /dev/null +++ b/tests/MC/AArch64/SVE2/mls.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x0c, 0x7f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "mls z0.h, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x0c, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "mls z0.s, z1.s, z7.s[3]" + + - + input: + bytes: [ 0x20, 0x0c, 0xf7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "mls z0.d, z1.d, z7.d[1]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x0c, 0xf7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "mls z0.d, z1.d, z7.d[1]" + + - + input: + bytes: [ 0x20, 0x0c, 0x7f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mls z0.h, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x0c, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mls z0.s, z1.s, z7.s[3]" + + - + input: + bytes: [ 0x20, 0x0c, 0xf7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mls z0.d, z1.d, z7.d[1]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x0c, 0xf7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mls z0.d, z1.d, z7.d[1]" diff --git a/tests/MC/AArch64/SVE2/mul.s.yaml b/tests/MC/AArch64/SVE2/mul.s.yaml new file mode 100644 index 0000000000..b0bbba9f7c --- /dev/null +++ b/tests/MC/AArch64/SVE2/mul.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x60, 0x22, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "mul z0.b, z1.b, z2.b" + + - + input: + bytes: [ 0x20, 0x60, 0x62, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "mul z0.h, z1.h, z2.h" + + - + input: + bytes: [ 0xdd, 0x63, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "mul z29.s, z30.s, z31.s" + + - + input: + bytes: [ 0xff, 0x63, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "mul z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x20, 0xf8, 0x7f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "mul z0.h, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xf8, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "mul z0.s, z1.s, z7.s[3]" + + - + input: + bytes: [ 0x20, 0xf8, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "mul z0.d, z1.d, z15.d[1]" + + - + input: + bytes: [ 0x20, 0x60, 0x22, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z0.b, z1.b, z2.b" + + - + input: + bytes: [ 0x20, 0x60, 0x62, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z0.h, z1.h, z2.h" + + - + input: + bytes: [ 0xdd, 0x63, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z29.s, z30.s, z31.s" + + - + input: + bytes: [ 0xff, 0x63, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x20, 0xf8, 0x7f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z0.h, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xf8, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z0.s, z1.s, z7.s[3]" + + - + input: + bytes: [ 0x20, 0xf8, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "mul z0.d, z1.d, z15.d[1]" diff --git a/tests/MC/AArch64/SVE2/nbsl.s.yaml b/tests/MC/AArch64/SVE2/nbsl.s.yaml new file mode 100644 index 0000000000..7d43f74873 --- /dev/null +++ b/tests/MC/AArch64/SVE2/nbsl.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x40, 0x3c, 0xe1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "nbsl z0.d, z0.d, z1.d, z2.d" + + - + input: + bytes: [ 0xff, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z7" + + - + input: + bytes: [ 0xbf, 0x3f, 0xfe, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "nbsl z31.d, z31.d, z30.d, z29.d" + + - + input: + bytes: [ 0x40, 0x3c, 0xe1, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "nbsl z0.d, z0.d, z1.d, z2.d" + + - + input: + bytes: [ 0xff, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z7" + + - + input: + bytes: [ 0xbf, 0x3f, 0xfe, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "nbsl z31.d, z31.d, z30.d, z29.d" diff --git a/tests/MC/AArch64/SVE2/nmatch.s.yaml b/tests/MC/AArch64/SVE2/nmatch.s.yaml new file mode 100644 index 0000000000..e979ac174f --- /dev/null +++ b/tests/MC/AArch64/SVE2/nmatch.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x80, 0x20, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "nmatch p0.b, p0/z, z0.b, z0.b" + + - + input: + bytes: [ 0x10, 0x80, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "nmatch p0.h, p0/z, z0.h, z0.h" + + - + input: + bytes: [ 0xdf, 0x9f, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "nmatch p15.b, p7/z, z30.b, z31.b" + + - + input: + bytes: [ 0xdf, 0x9f, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "nmatch p15.h, p7/z, z30.h, z31.h" diff --git a/tests/MC/AArch64/SVE2/pmul.s.yaml b/tests/MC/AArch64/SVE2/pmul.s.yaml new file mode 100644 index 0000000000..89e1bc0d38 --- /dev/null +++ b/tests/MC/AArch64/SVE2/pmul.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x64, 0x22, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "pmul z0.b, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x67, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "pmul z29.b, z30.b, z31.b" + + - + input: + bytes: [ 0x20, 0x64, 0x22, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "pmul z0.b, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x67, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "pmul z29.b, z30.b, z31.b" diff --git a/tests/MC/AArch64/SVE2/pmullb-128.s.yaml b/tests/MC/AArch64/SVE2/pmullb-128.s.yaml new file mode 100644 index 0000000000..0d57cb0cd5 --- /dev/null +++ b/tests/MC/AArch64/SVE2/pmullb-128.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xdd, 0x6b, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-aes" ] + expected: + insns: + - + asm_text: "pmullb z29.q, z30.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/pmullb.s.yaml b/tests/MC/AArch64/SVE2/pmullb.s.yaml new file mode 100644 index 0000000000..7a3cbe97cc --- /dev/null +++ b/tests/MC/AArch64/SVE2/pmullb.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x68, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "pmullb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xff, 0x6b, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "pmullb z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0x68, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "pmullb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xff, 0x6b, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "pmullb z31.d, z31.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/pmullt-128.s.yaml b/tests/MC/AArch64/SVE2/pmullt-128.s.yaml new file mode 100644 index 0000000000..aa8aa4b5ff --- /dev/null +++ b/tests/MC/AArch64/SVE2/pmullt-128.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xdd, 0x6f, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-aes" ] + expected: + insns: + - + asm_text: "pmullt z29.q, z30.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/pmullt.s.yaml b/tests/MC/AArch64/SVE2/pmullt.s.yaml new file mode 100644 index 0000000000..4155375a60 --- /dev/null +++ b/tests/MC/AArch64/SVE2/pmullt.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x6c, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "pmullt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xff, 0x6f, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "pmullt z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0x6c, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "pmullt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xff, 0x6f, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "pmullt z31.d, z31.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/raddhnb.s.yaml b/tests/MC/AArch64/SVE2/raddhnb.s.yaml new file mode 100644 index 0000000000..a40f41000b --- /dev/null +++ b/tests/MC/AArch64/SVE2/raddhnb.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x68, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "raddhnb z0.b, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x68, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "raddhnb z0.h, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x68, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "raddhnb z0.s, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x68, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "raddhnb z0.b, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x68, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "raddhnb z0.h, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x68, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "raddhnb z0.s, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/raddhnt.s.yaml b/tests/MC/AArch64/SVE2/raddhnt.s.yaml new file mode 100644 index 0000000000..2fb9572a5e --- /dev/null +++ b/tests/MC/AArch64/SVE2/raddhnt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x6c, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "raddhnt z0.b, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x6c, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "raddhnt z0.h, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x6c, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "raddhnt z0.s, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x6c, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "raddhnt z0.b, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x6c, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "raddhnt z0.h, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x6c, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "raddhnt z0.s, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/rax1.s.yaml b/tests/MC/AArch64/SVE2/rax1.s.yaml new file mode 100644 index 0000000000..1b9aea6fd8 --- /dev/null +++ b/tests/MC/AArch64/SVE2/rax1.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xf4, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-sha3" ] + expected: + insns: + - + asm_text: "rax1 z0.d, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/rshrnb.s.yaml b/tests/MC/AArch64/SVE2/rshrnb.s.yaml new file mode 100644 index 0000000000..9a7cfbdb5f --- /dev/null +++ b/tests/MC/AArch64/SVE2/rshrnb.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x18, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "rshrnb z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x1b, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "rshrnb z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x18, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "rshrnb z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x1b, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "rshrnb z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x18, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "rshrnb z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x1b, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "rshrnb z31.s, z31.d, #32" + + - + input: + bytes: [ 0x00, 0x18, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rshrnb z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x1b, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rshrnb z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x18, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rshrnb z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x1b, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rshrnb z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x18, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rshrnb z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x1b, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rshrnb z31.s, z31.d, #32" diff --git a/tests/MC/AArch64/SVE2/rshrnt.s.yaml b/tests/MC/AArch64/SVE2/rshrnt.s.yaml new file mode 100644 index 0000000000..4c30671e7a --- /dev/null +++ b/tests/MC/AArch64/SVE2/rshrnt.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x1c, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "rshrnt z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x1f, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "rshrnt z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x1c, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "rshrnt z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x1f, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "rshrnt z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x1c, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "rshrnt z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x1f, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "rshrnt z31.s, z31.d, #32" + + - + input: + bytes: [ 0x00, 0x1c, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rshrnt z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x1f, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rshrnt z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x1c, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rshrnt z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x1f, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rshrnt z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x1c, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rshrnt z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x1f, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rshrnt z31.s, z31.d, #32" diff --git a/tests/MC/AArch64/SVE2/rsubhnb.s.yaml b/tests/MC/AArch64/SVE2/rsubhnb.s.yaml new file mode 100644 index 0000000000..d25f08218c --- /dev/null +++ b/tests/MC/AArch64/SVE2/rsubhnb.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x78, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "rsubhnb z0.b, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x78, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "rsubhnb z0.h, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x78, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "rsubhnb z0.s, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x78, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rsubhnb z0.b, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x78, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rsubhnb z0.h, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x78, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rsubhnb z0.s, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/rsubhnt.s.yaml b/tests/MC/AArch64/SVE2/rsubhnt.s.yaml new file mode 100644 index 0000000000..9f53791862 --- /dev/null +++ b/tests/MC/AArch64/SVE2/rsubhnt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x7c, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "rsubhnt z0.b, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x7c, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "rsubhnt z0.h, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x7c, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "rsubhnt z0.s, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x7c, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rsubhnt z0.b, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x7c, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rsubhnt z0.h, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x7c, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "rsubhnt z0.s, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/saba.s.yaml b/tests/MC/AArch64/SVE2/saba.s.yaml new file mode 100644 index 0000000000..2ff9942566 --- /dev/null +++ b/tests/MC/AArch64/SVE2/saba.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xf8, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saba z0.b, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0xf8, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saba z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xf8, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saba z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xf8, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saba z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xf8, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saba z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0xf8, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saba z0.b, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0xf8, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saba z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xf8, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saba z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xf8, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saba z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xf8, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saba z0.d, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/sabalb.s.yaml b/tests/MC/AArch64/SVE2/sabalb.s.yaml new file mode 100644 index 0000000000..d29b76d211 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sabalb.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xc0, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sabalb z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0xc0, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sabalb z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xc0, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sabalb z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0xc0, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sabalb z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xc0, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabalb z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0xc0, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabalb z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xc0, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabalb z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0xc0, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabalb z21.d, z1.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/sabalt.s.yaml b/tests/MC/AArch64/SVE2/sabalt.s.yaml new file mode 100644 index 0000000000..33bb7dd118 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sabalt.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xc4, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sabalt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0xc4, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sabalt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xc4, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sabalt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0xc4, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sabalt z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xc4, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabalt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0xc4, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabalt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xc4, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabalt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0xc4, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabalt z21.d, z1.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/sabdlb.s.yaml b/tests/MC/AArch64/SVE2/sabdlb.s.yaml new file mode 100644 index 0000000000..94239dd96a --- /dev/null +++ b/tests/MC/AArch64/SVE2/sabdlb.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x30, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sabdlb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x33, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sabdlb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x33, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sabdlb z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0x30, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabdlb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x33, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabdlb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x33, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabdlb z31.d, z31.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/sabdlt.s.yaml b/tests/MC/AArch64/SVE2/sabdlt.s.yaml new file mode 100644 index 0000000000..f4bcaee25a --- /dev/null +++ b/tests/MC/AArch64/SVE2/sabdlt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x34, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sabdlt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x37, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sabdlt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x37, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sabdlt z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0x34, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabdlt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x37, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabdlt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x37, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sabdlt z31.d, z31.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/sadalp.s.yaml b/tests/MC/AArch64/SVE2/sadalp.s.yaml new file mode 100644 index 0000000000..3045f95bbd --- /dev/null +++ b/tests/MC/AArch64/SVE2/sadalp.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa0, 0x44, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sadalp z0.h, p0/m, z1.b" + + - + input: + bytes: [ 0xdd, 0xa3, 0x84, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sadalp z29.s, p0/m, z30.h" + + - + input: + bytes: [ 0xfe, 0xbf, 0xc4, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sadalp z30.d, p7/m, z31.s" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0xa3, 0xc4, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sadalp z31.d, p0/m, z30.s" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0xa3, 0xc4, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sadalp z31.d, p0/m, z30.s" + + - + input: + bytes: [ 0x20, 0xa0, 0x44, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sadalp z0.h, p0/m, z1.b" + + - + input: + bytes: [ 0xdd, 0xa3, 0x84, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sadalp z29.s, p0/m, z30.h" + + - + input: + bytes: [ 0xfe, 0xbf, 0xc4, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sadalp z30.d, p7/m, z31.s" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0xa3, 0xc4, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sadalp z31.d, p0/m, z30.s" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0xa3, 0xc4, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sadalp z31.d, p0/m, z30.s" diff --git a/tests/MC/AArch64/SVE2/saddlb.s.yaml b/tests/MC/AArch64/SVE2/saddlb.s.yaml new file mode 100644 index 0000000000..9dafe43c5a --- /dev/null +++ b/tests/MC/AArch64/SVE2/saddlb.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x00, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saddlb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x03, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saddlb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x03, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saddlb z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0x00, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saddlb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x03, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saddlb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x03, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saddlb z31.d, z31.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/saddlbt.s.yaml b/tests/MC/AArch64/SVE2/saddlbt.s.yaml new file mode 100644 index 0000000000..6a14a445fa --- /dev/null +++ b/tests/MC/AArch64/SVE2/saddlbt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saddlbt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x80, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saddlbt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x80, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saddlbt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x80, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saddlbt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x80, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saddlbt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x80, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saddlbt z0.d, z1.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/saddlt.s.yaml b/tests/MC/AArch64/SVE2/saddlt.s.yaml new file mode 100644 index 0000000000..f7a8a4a1a6 --- /dev/null +++ b/tests/MC/AArch64/SVE2/saddlt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x04, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saddlt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x07, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saddlt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x07, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saddlt z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0x04, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saddlt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x07, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saddlt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x07, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saddlt z31.d, z31.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/saddwb.s.yaml b/tests/MC/AArch64/SVE2/saddwb.s.yaml new file mode 100644 index 0000000000..4606da802b --- /dev/null +++ b/tests/MC/AArch64/SVE2/saddwb.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x40, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saddwb z0.h, z1.h, z2.b" + + - + input: + bytes: [ 0xdd, 0x43, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saddwb z29.s, z30.s, z31.h" + + - + input: + bytes: [ 0xff, 0x43, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saddwb z31.d, z31.d, z31.s" + + - + input: + bytes: [ 0x20, 0x40, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saddwb z0.h, z1.h, z2.b" + + - + input: + bytes: [ 0xdd, 0x43, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saddwb z29.s, z30.s, z31.h" + + - + input: + bytes: [ 0xff, 0x43, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saddwb z31.d, z31.d, z31.s" diff --git a/tests/MC/AArch64/SVE2/saddwt.s.yaml b/tests/MC/AArch64/SVE2/saddwt.s.yaml new file mode 100644 index 0000000000..a101352347 --- /dev/null +++ b/tests/MC/AArch64/SVE2/saddwt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x44, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saddwt z0.h, z1.h, z2.b" + + - + input: + bytes: [ 0xdd, 0x47, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saddwt z29.s, z30.s, z31.h" + + - + input: + bytes: [ 0xff, 0x47, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "saddwt z31.d, z31.d, z31.s" + + - + input: + bytes: [ 0x20, 0x44, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saddwt z0.h, z1.h, z2.b" + + - + input: + bytes: [ 0xdd, 0x47, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saddwt z29.s, z30.s, z31.h" + + - + input: + bytes: [ 0xff, 0x47, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "saddwt z31.d, z31.d, z31.s" diff --git a/tests/MC/AArch64/SVE2/sbclb.s.yaml b/tests/MC/AArch64/SVE2/sbclb.s.yaml new file mode 100644 index 0000000000..b08f8c7a61 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sbclb.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xd0, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sbclb z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xd0, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sbclb z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xd0, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sbclb z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0xd0, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sbclb z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xd0, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sbclb z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xd0, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sbclb z0.d, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/sbclt.s.yaml b/tests/MC/AArch64/SVE2/sbclt.s.yaml new file mode 100644 index 0000000000..53037e57f4 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sbclt.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xd4, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sbclt z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xd4, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sbclt z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xd4, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sbclt z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0xd4, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sbclt z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xd4, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sbclt z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xd4, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sbclt z0.d, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/shadd.s.yaml b/tests/MC/AArch64/SVE2/shadd.s.yaml new file mode 100644 index 0000000000..022d4ab7b8 --- /dev/null +++ b/tests/MC/AArch64/SVE2/shadd.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x10, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shadd z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x50, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shadd z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x90, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shadd z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shadd z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x10, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shadd z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x50, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shadd z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x90, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shadd z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shadd z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shadd z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/shrnb.s.yaml b/tests/MC/AArch64/SVE2/shrnb.s.yaml new file mode 100644 index 0000000000..395ac7941b --- /dev/null +++ b/tests/MC/AArch64/SVE2/shrnb.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x10, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shrnb z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x13, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shrnb z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x10, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shrnb z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x13, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shrnb z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x10, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shrnb z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x13, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shrnb z31.s, z31.d, #32" + + - + input: + bytes: [ 0x00, 0x10, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shrnb z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x13, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shrnb z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x10, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shrnb z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x13, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shrnb z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x10, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shrnb z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x13, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shrnb z31.s, z31.d, #32" diff --git a/tests/MC/AArch64/SVE2/shrnt.s.yaml b/tests/MC/AArch64/SVE2/shrnt.s.yaml new file mode 100644 index 0000000000..3d24388c90 --- /dev/null +++ b/tests/MC/AArch64/SVE2/shrnt.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x14, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shrnt z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x17, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shrnt z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x14, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shrnt z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x17, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shrnt z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x14, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shrnt z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x17, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shrnt z31.s, z31.d, #32" + + - + input: + bytes: [ 0x00, 0x14, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shrnt z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x17, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shrnt z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x14, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shrnt z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x17, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shrnt z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x14, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shrnt z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x17, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shrnt z31.s, z31.d, #32" diff --git a/tests/MC/AArch64/SVE2/shsub.s.yaml b/tests/MC/AArch64/SVE2/shsub.s.yaml new file mode 100644 index 0000000000..86ede4b9fe --- /dev/null +++ b/tests/MC/AArch64/SVE2/shsub.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x12, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shsub z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x52, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shsub z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x92, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shsub z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shsub z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shsub z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shsub z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x12, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shsub z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x52, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shsub z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x92, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shsub z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shsub z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shsub z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shsub z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/shsubr.s.yaml b/tests/MC/AArch64/SVE2/shsubr.s.yaml new file mode 100644 index 0000000000..2b9170932c --- /dev/null +++ b/tests/MC/AArch64/SVE2/shsubr.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x16, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shsubr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x56, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shsubr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x96, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shsubr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd6, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shsubr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd6, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shsubr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd6, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "shsubr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x16, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shsubr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x56, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shsubr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x96, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shsubr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd6, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shsubr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd6, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shsubr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd6, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "shsubr z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/sli.s.yaml b/tests/MC/AArch64/SVE2/sli.s.yaml new file mode 100644 index 0000000000..06acb33ea3 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sli.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xf4, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sli z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xf7, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sli z31.b, z31.b, #7" + + - + input: + bytes: [ 0x00, 0xf4, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sli z0.h, z0.h, #0" + + - + input: + bytes: [ 0xff, 0xf7, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sli z31.h, z31.h, #15" + + - + input: + bytes: [ 0x00, 0xf4, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sli z0.s, z0.s, #0" + + - + input: + bytes: [ 0xff, 0xf7, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sli z31.s, z31.s, #31" + + - + input: + bytes: [ 0x00, 0xf4, 0x80, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sli z0.d, z0.d, #0" + + - + input: + bytes: [ 0xff, 0xf7, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sli z31.d, z31.d, #63" + + - + input: + bytes: [ 0x00, 0xf4, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sli z0.b, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xf7, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sli z31.b, z31.b, #7" + + - + input: + bytes: [ 0x00, 0xf4, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sli z0.h, z0.h, #0" + + - + input: + bytes: [ 0xff, 0xf7, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sli z31.h, z31.h, #15" + + - + input: + bytes: [ 0x00, 0xf4, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sli z0.s, z0.s, #0" + + - + input: + bytes: [ 0xff, 0xf7, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sli z31.s, z31.s, #31" + + - + input: + bytes: [ 0x00, 0xf4, 0x80, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sli z0.d, z0.d, #0" + + - + input: + bytes: [ 0xff, 0xf7, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sli z31.d, z31.d, #63" diff --git a/tests/MC/AArch64/SVE2/sm4e.s.yaml b/tests/MC/AArch64/SVE2/sm4e.s.yaml new file mode 100644 index 0000000000..64c87a6432 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sm4e.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xe3, 0x23, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-sm4" ] + expected: + insns: + - + asm_text: "sm4e z0.s, z0.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/sm4ekey.s.yaml b/tests/MC/AArch64/SVE2/sm4ekey.s.yaml new file mode 100644 index 0000000000..6ad07d7ad2 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sm4ekey.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xf0, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-sm4" ] + expected: + insns: + - + asm_text: "sm4ekey z0.s, z1.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/smaxp.s.yaml b/tests/MC/AArch64/SVE2/smaxp.s.yaml new file mode 100644 index 0000000000..dd126d3bfa --- /dev/null +++ b/tests/MC/AArch64/SVE2/smaxp.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa0, 0x14, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smaxp z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0xa0, 0x54, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smaxp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0xbf, 0x94, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smaxp z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd4, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smaxp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0xa3, 0xd4, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smaxp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd4, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smaxp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0xa0, 0x14, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smaxp z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0xa0, 0x54, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smaxp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0xbf, 0x94, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smaxp z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd4, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smaxp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0xa3, 0xd4, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smaxp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd4, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smaxp z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/sminp.s.yaml b/tests/MC/AArch64/SVE2/sminp.s.yaml new file mode 100644 index 0000000000..dc612f5edd --- /dev/null +++ b/tests/MC/AArch64/SVE2/sminp.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa0, 0x16, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sminp z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0xa0, 0x56, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sminp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0xbf, 0x96, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sminp z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd6, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sminp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0xa3, 0xd6, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sminp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd6, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sminp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0xa0, 0x16, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sminp z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0xa0, 0x56, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sminp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0xbf, 0x96, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sminp z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd6, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sminp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0xa3, 0xd6, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sminp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd6, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sminp z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/smlalb.s.yaml b/tests/MC/AArch64/SVE2/smlalb.s.yaml new file mode 100644 index 0000000000..1ed103d46d --- /dev/null +++ b/tests/MC/AArch64/SVE2/smlalb.s.yaml @@ -0,0 +1,180 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x40, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlalb z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x40, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlalb z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x40, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlalb z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x88, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlalb z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x88, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlalb z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x40, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlalb z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x89, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlalb z21.d, z10.s, z5.s[1]" + + - + input: + bytes: [ 0x20, 0x40, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlalb z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x40, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlalb z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x40, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlalb z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x88, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlalb z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x88, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlalb z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x40, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlalb z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x89, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlalb z21.d, z10.s, z5.s[1]" diff --git a/tests/MC/AArch64/SVE2/smlalt.s.yaml b/tests/MC/AArch64/SVE2/smlalt.s.yaml new file mode 100644 index 0000000000..6aeb13a01f --- /dev/null +++ b/tests/MC/AArch64/SVE2/smlalt.s.yaml @@ -0,0 +1,180 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x44, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlalt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x44, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlalt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x44, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlalt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x8c, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlalt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x8c, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlalt z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x44, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlalt z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x8d, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlalt z21.d, z10.s, z5.s[1]" + + - + input: + bytes: [ 0x20, 0x44, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlalt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x44, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlalt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x44, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlalt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x8c, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlalt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x8c, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlalt z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x44, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlalt z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x8d, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlalt z21.d, z10.s, z5.s[1]" diff --git a/tests/MC/AArch64/SVE2/smlslb.s.yaml b/tests/MC/AArch64/SVE2/smlslb.s.yaml new file mode 100644 index 0000000000..ce3d050e86 --- /dev/null +++ b/tests/MC/AArch64/SVE2/smlslb.s.yaml @@ -0,0 +1,180 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x50, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlslb z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x50, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlslb z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x50, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlslb z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xa8, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlslb z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xa8, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlslb z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x50, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlslb z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0xa9, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlslb z21.d, z10.s, z5.s[1]" + + - + input: + bytes: [ 0x20, 0x50, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlslb z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x50, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlslb z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x50, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlslb z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xa8, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlslb z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xa8, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlslb z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x50, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlslb z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0xa9, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlslb z21.d, z10.s, z5.s[1]" diff --git a/tests/MC/AArch64/SVE2/smlslt.s.yaml b/tests/MC/AArch64/SVE2/smlslt.s.yaml new file mode 100644 index 0000000000..4ec129b380 --- /dev/null +++ b/tests/MC/AArch64/SVE2/smlslt.s.yaml @@ -0,0 +1,180 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x54, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlslt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x54, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlslt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x54, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlslt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xac, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlslt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xac, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlslt z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x54, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlslt z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0xad, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smlslt z21.d, z10.s, z5.s[1]" + + - + input: + bytes: [ 0x20, 0x54, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlslt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x54, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlslt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x54, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlslt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xac, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlslt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xac, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlslt z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x54, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlslt z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0xad, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smlslt z21.d, z10.s, z5.s[1]" diff --git a/tests/MC/AArch64/SVE2/smulh.s.yaml b/tests/MC/AArch64/SVE2/smulh.s.yaml new file mode 100644 index 0000000000..485a891dcc --- /dev/null +++ b/tests/MC/AArch64/SVE2/smulh.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x68, 0x22, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smulh z0.b, z1.b, z2.b" + + - + input: + bytes: [ 0x20, 0x68, 0x62, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smulh z0.h, z1.h, z2.h" + + - + input: + bytes: [ 0xdd, 0x6b, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smulh z29.s, z30.s, z31.s" + + - + input: + bytes: [ 0xff, 0x6b, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smulh z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x20, 0x68, 0x22, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smulh z0.b, z1.b, z2.b" + + - + input: + bytes: [ 0x20, 0x68, 0x62, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smulh z0.h, z1.h, z2.h" + + - + input: + bytes: [ 0xdd, 0x6b, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smulh z29.s, z30.s, z31.s" + + - + input: + bytes: [ 0xff, 0x6b, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smulh z31.d, z31.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/smullb.s.yaml b/tests/MC/AArch64/SVE2/smullb.s.yaml new file mode 100644 index 0000000000..69f8dca140 --- /dev/null +++ b/tests/MC/AArch64/SVE2/smullb.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x70, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smullb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x73, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smullb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x73, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smullb z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0xc8, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smullb z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xc8, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smullb z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x20, 0x70, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smullb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x73, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smullb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x73, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smullb z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0xc8, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smullb z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xc8, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smullb z0.d, z1.s, z15.s[1]" diff --git a/tests/MC/AArch64/SVE2/smullt.s.yaml b/tests/MC/AArch64/SVE2/smullt.s.yaml new file mode 100644 index 0000000000..1e9d7cfaa1 --- /dev/null +++ b/tests/MC/AArch64/SVE2/smullt.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x74, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smullt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x77, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smullt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x77, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smullt z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0xcc, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smullt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xcc, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "smullt z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x20, 0x74, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smullt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x77, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smullt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x77, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smullt z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0xcc, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smullt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xcc, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "smullt z0.d, z1.s, z15.s[1]" diff --git a/tests/MC/AArch64/SVE2/splice.s.yaml b/tests/MC/AArch64/SVE2/splice.s.yaml new file mode 100644 index 0000000000..c7e6d98af1 --- /dev/null +++ b/tests/MC/AArch64/SVE2/splice.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xdd, 0x9f, 0x2d, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "splice z29.b, p7, { z30.b, z31.b }" + + - + input: + bytes: [ 0xdd, 0x9f, 0x6d, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "splice z29.h, p7, { z30.h, z31.h }" + + - + input: + bytes: [ 0xdd, 0x9f, 0xad, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "splice z29.s, p7, { z30.s, z31.s }" + + - + input: + bytes: [ 0xdd, 0x9f, 0xed, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "splice z29.d, p7, { z30.d, z31.d }" + + - + input: + bytes: [ 0xdd, 0x9f, 0x2d, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "splice z29.b, p7, { z30.b, z31.b }" + + - + input: + bytes: [ 0xdd, 0x9f, 0x6d, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "splice z29.h, p7, { z30.h, z31.h }" + + - + input: + bytes: [ 0xdd, 0x9f, 0xad, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "splice z29.s, p7, { z30.s, z31.s }" + + - + input: + bytes: [ 0xdd, 0x9f, 0xed, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "splice z29.d, p7, { z30.d, z31.d }" diff --git a/tests/MC/AArch64/SVE2/sqabs.s.yaml b/tests/MC/AArch64/SVE2/sqabs.s.yaml new file mode 100644 index 0000000000..25f14a9f0a --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqabs.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqabs z31.b, p7/m, z31.b" + + - + input: + bytes: [ 0xff, 0xbf, 0x48, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqabs z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqabs z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqabs z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z4.s, p7/z, z6.s" + + - + input: + bytes: [ 0xe4, 0xbf, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqabs z4.s, p7/m, z31.s" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqabs z4.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqabs z31.b, p7/m, z31.b" + + - + input: + bytes: [ 0xff, 0xbf, 0x48, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqabs z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqabs z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqabs z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.s, p7/z, z6.s" + + - + input: + bytes: [ 0xe4, 0xbf, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqabs z4.s, p7/m, z31.s" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqabs z4.s, p7/m, z31.s" diff --git a/tests/MC/AArch64/SVE2/sqadd.s.yaml b/tests/MC/AArch64/SVE2/sqadd.s.yaml new file mode 100644 index 0000000000..93f4f9d901 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqadd.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x18, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqadd z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x58, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqadd z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x98, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqadd z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqadd z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x18, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x58, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x98, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqadd z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/sqcadd.s.yaml b/tests/MC/AArch64/SVE2/sqcadd.s.yaml new file mode 100644 index 0000000000..8ea8f3d7bd --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqcadd.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xd8, 0x01, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqcadd z0.b, z0.b, z0.b, #90" + + - + input: + bytes: [ 0x00, 0xd8, 0x41, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqcadd z0.h, z0.h, z0.h, #90" + + - + input: + bytes: [ 0x00, 0xd8, 0x81, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqcadd z0.s, z0.s, z0.s, #90" + + - + input: + bytes: [ 0x00, 0xd8, 0xc1, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqcadd z0.d, z0.d, z0.d, #90" + + - + input: + bytes: [ 0xff, 0xdf, 0x01, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqcadd z31.b, z31.b, z31.b, #270" + + - + input: + bytes: [ 0xff, 0xdf, 0x41, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqcadd z31.h, z31.h, z31.h, #270" + + - + input: + bytes: [ 0xff, 0xdf, 0x81, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqcadd z31.s, z31.s, z31.s, #270" + + - + input: + bytes: [ 0xff, 0xdf, 0xc1, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqcadd z31.d, z31.d, z31.d, #270" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xdf, 0xc1, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqcadd z4.d, z4.d, z31.d, #270" + + - + input: + bytes: [ 0x00, 0xd8, 0x01, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqcadd z0.b, z0.b, z0.b, #90" + + - + input: + bytes: [ 0x00, 0xd8, 0x41, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqcadd z0.h, z0.h, z0.h, #90" + + - + input: + bytes: [ 0x00, 0xd8, 0x81, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqcadd z0.s, z0.s, z0.s, #90" + + - + input: + bytes: [ 0x00, 0xd8, 0xc1, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqcadd z0.d, z0.d, z0.d, #90" + + - + input: + bytes: [ 0xff, 0xdf, 0x01, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqcadd z31.b, z31.b, z31.b, #270" + + - + input: + bytes: [ 0xff, 0xdf, 0x41, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqcadd z31.h, z31.h, z31.h, #270" + + - + input: + bytes: [ 0xff, 0xdf, 0x81, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqcadd z31.s, z31.s, z31.s, #270" + + - + input: + bytes: [ 0xff, 0xdf, 0xc1, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqcadd z31.d, z31.d, z31.d, #270" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xdf, 0xc1, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqcadd z4.d, z4.d, z31.d, #270" diff --git a/tests/MC/AArch64/SVE2/sqdmlalb.s.yaml b/tests/MC/AArch64/SVE2/sqdmlalb.s.yaml new file mode 100644 index 0000000000..264f451863 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqdmlalb.s.yaml @@ -0,0 +1,180 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x60, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlalb z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x60, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlalb z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x60, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlalb z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x28, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlalb z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x28, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlalb z0.d, z1.s, z15.s[3]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x60, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlalb z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x29, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlalb z21.d, z10.s, z5.s[1]" + + - + input: + bytes: [ 0x20, 0x60, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlalb z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x60, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlalb z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x60, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlalb z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x28, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlalb z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x28, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlalb z0.d, z1.s, z15.s[3]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x60, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlalb z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x29, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlalb z21.d, z10.s, z5.s[1]" diff --git a/tests/MC/AArch64/SVE2/sqdmlalbt.s.yaml b/tests/MC/AArch64/SVE2/sqdmlalbt.s.yaml new file mode 100644 index 0000000000..90823c1b60 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqdmlalbt.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x08, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlalbt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x08, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlalbt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x08, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlalbt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x08, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlalbt z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x08, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlalbt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x08, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlalbt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x08, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlalbt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x08, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlalbt z21.d, z1.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/sqdmlalt.s.yaml b/tests/MC/AArch64/SVE2/sqdmlalt.s.yaml new file mode 100644 index 0000000000..76d4b929ee --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqdmlalt.s.yaml @@ -0,0 +1,180 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x64, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlalt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x64, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlalt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x64, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlalt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x2c, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlalt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x2c, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlalt z0.d, z1.s, z15.s[3]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x64, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlalt z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x2d, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlalt z21.d, z10.s, z5.s[1]" + + - + input: + bytes: [ 0x20, 0x64, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlalt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x64, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlalt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x64, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlalt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x2c, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlalt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x2c, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlalt z0.d, z1.s, z15.s[3]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x64, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlalt z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x2d, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlalt z21.d, z10.s, z5.s[1]" diff --git a/tests/MC/AArch64/SVE2/sqdmlslb.s.yaml b/tests/MC/AArch64/SVE2/sqdmlslb.s.yaml new file mode 100644 index 0000000000..c1f942edf6 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqdmlslb.s.yaml @@ -0,0 +1,180 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x68, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlslb z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x68, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlslb z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x68, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlslb z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x38, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlslb z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x38, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlslb z0.d, z1.s, z15.s[3]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x68, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlslb z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x39, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlslb z21.d, z10.s, z5.s[1]" + + - + input: + bytes: [ 0x20, 0x68, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlslb z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x68, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlslb z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x68, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlslb z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x38, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlslb z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x38, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlslb z0.d, z1.s, z15.s[3]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x68, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlslb z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x39, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlslb z21.d, z10.s, z5.s[1]" diff --git a/tests/MC/AArch64/SVE2/sqdmlslbt.s.yaml b/tests/MC/AArch64/SVE2/sqdmlslbt.s.yaml new file mode 100644 index 0000000000..c7d29a3ab2 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqdmlslbt.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x0c, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlslbt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x0c, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlslbt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x0c, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlslbt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x0c, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlslbt z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x0c, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlslbt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x0c, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlslbt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x0c, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlslbt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x0c, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlslbt z21.d, z1.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/sqdmlslt.s.yaml b/tests/MC/AArch64/SVE2/sqdmlslt.s.yaml new file mode 100644 index 0000000000..8575b1fe7c --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqdmlslt.s.yaml @@ -0,0 +1,180 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x6c, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlslt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x6c, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlslt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x6c, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlslt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x3c, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlslt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x3c, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlslt z0.d, z1.s, z15.s[3]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x6c, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlslt z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x3d, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmlslt z21.d, z10.s, z5.s[1]" + + - + input: + bytes: [ 0x20, 0x6c, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlslt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x6c, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlslt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x6c, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlslt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x3c, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlslt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x3c, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlslt z0.d, z1.s, z15.s[3]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x6c, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlslt z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x3d, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmlslt z21.d, z10.s, z5.s[1]" diff --git a/tests/MC/AArch64/SVE2/sqdmulh.s.yaml b/tests/MC/AArch64/SVE2/sqdmulh.s.yaml new file mode 100644 index 0000000000..eb390de1c8 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqdmulh.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x70, 0x22, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmulh z0.b, z1.b, z2.b" + + - + input: + bytes: [ 0x20, 0x70, 0x62, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmulh z0.h, z1.h, z2.h" + + - + input: + bytes: [ 0xdd, 0x73, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmulh z29.s, z30.s, z31.s" + + - + input: + bytes: [ 0xff, 0x73, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmulh z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x20, 0xf0, 0x7f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmulh z0.h, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xf0, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmulh z0.s, z1.s, z7.s[3]" + + - + input: + bytes: [ 0x20, 0xf0, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmulh z0.d, z1.d, z15.d[1]" + + - + input: + bytes: [ 0x20, 0x70, 0x22, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmulh z0.b, z1.b, z2.b" + + - + input: + bytes: [ 0x20, 0x70, 0x62, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmulh z0.h, z1.h, z2.h" + + - + input: + bytes: [ 0xdd, 0x73, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmulh z29.s, z30.s, z31.s" + + - + input: + bytes: [ 0xff, 0x73, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmulh z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x20, 0xf0, 0x7f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmulh z0.h, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xf0, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmulh z0.s, z1.s, z7.s[3]" + + - + input: + bytes: [ 0x20, 0xf0, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmulh z0.d, z1.d, z15.d[1]" diff --git a/tests/MC/AArch64/SVE2/sqdmullb.s.yaml b/tests/MC/AArch64/SVE2/sqdmullb.s.yaml new file mode 100644 index 0000000000..625daa8640 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqdmullb.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x60, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmullb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x63, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmullb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x63, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmullb z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0xe8, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmullb z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xe8, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmullb z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x20, 0x60, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmullb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x63, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmullb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x63, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmullb z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0xe8, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmullb z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xe8, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmullb z0.d, z1.s, z15.s[1]" diff --git a/tests/MC/AArch64/SVE2/sqdmullt.s.yaml b/tests/MC/AArch64/SVE2/sqdmullt.s.yaml new file mode 100644 index 0000000000..bf4a1582a0 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqdmullt.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x64, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmullt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x67, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmullt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x67, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmullt z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0xec, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmullt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xec, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqdmullt z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x20, 0x64, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmullt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x67, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmullt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x67, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmullt z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0xec, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmullt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xec, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqdmullt z0.d, z1.s, z15.s[1]" diff --git a/tests/MC/AArch64/SVE2/sqneg.s.yaml b/tests/MC/AArch64/SVE2/sqneg.s.yaml new file mode 100644 index 0000000000..352bbf4e34 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqneg.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x09, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqneg z31.b, p7/m, z31.b" + + - + input: + bytes: [ 0xff, 0xbf, 0x49, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqneg z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x89, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqneg z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xc9, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqneg z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z4.s, p7/z, z6.s" + + - + input: + bytes: [ 0xe4, 0xbf, 0x89, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqneg z4.s, p7/m, z31.s" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0x89, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqneg z4.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0x09, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqneg z31.b, p7/m, z31.b" + + - + input: + bytes: [ 0xff, 0xbf, 0x49, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqneg z31.h, p7/m, z31.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x89, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqneg z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0xc9, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqneg z31.d, p7/m, z31.d" + + - + input: + bytes: [ 0xc4, 0x3c, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.s, p7/z, z6.s" + + - + input: + bytes: [ 0xe4, 0xbf, 0x89, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqneg z4.s, p7/m, z31.s" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0x89, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqneg z4.s, p7/m, z31.s" diff --git a/tests/MC/AArch64/SVE2/sqrdcmlah.s.yaml b/tests/MC/AArch64/SVE2/sqrdcmlah.s.yaml new file mode 100644 index 0000000000..d585a3f3c7 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqrdcmlah.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x30, 0x02, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z0.b, z1.b, z2.b, #0" + + - + input: + bytes: [ 0x20, 0x30, 0x42, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z0.h, z1.h, z2.h, #0" + + - + input: + bytes: [ 0x20, 0x30, 0x82, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z0.s, z1.s, z2.s, #0" + + - + input: + bytes: [ 0x20, 0x30, 0xc2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z0.d, z1.d, z2.d, #0" + + - + input: + bytes: [ 0xdd, 0x37, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z29.b, z30.b, z31.b, #90" + + - + input: + bytes: [ 0xdd, 0x37, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z29.h, z30.h, z31.h, #90" + + - + input: + bytes: [ 0xdd, 0x37, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z29.s, z30.s, z31.s, #90" + + - + input: + bytes: [ 0xdd, 0x37, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z29.d, z30.d, z31.d, #90" + + - + input: + bytes: [ 0xff, 0x3b, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z31.b, z31.b, z31.b, #180" + + - + input: + bytes: [ 0xff, 0x3b, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z31.h, z31.h, z31.h, #180" + + - + input: + bytes: [ 0xff, 0x3b, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z31.s, z31.s, z31.s, #180" + + - + input: + bytes: [ 0xff, 0x3b, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z31.d, z31.d, z31.d, #180" + + - + input: + bytes: [ 0x0f, 0x3e, 0x11, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z15.b, z16.b, z17.b, #270" + + - + input: + bytes: [ 0x0f, 0x3e, 0x51, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z15.h, z16.h, z17.h, #270" + + - + input: + bytes: [ 0x0f, 0x3e, 0x91, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z15.s, z16.s, z17.s, #270" + + - + input: + bytes: [ 0x0f, 0x3e, 0xd1, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z15.d, z16.d, z17.d, #270" + + - + input: + bytes: [ 0x20, 0x70, 0xa2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z0.h, z1.h, z2.h[0], #0" + + - + input: + bytes: [ 0x20, 0x70, 0xe2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z0.s, z1.s, z2.s[0], #0" + + - + input: + bytes: [ 0xdf, 0x7b, 0xa7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z31.h, z30.h, z7.h[0], #180" + + - + input: + bytes: [ 0xdf, 0x7b, 0xe7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z31.s, z30.s, z7.s[0], #180" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x3f, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z4.d, z31.d, z31.d, #270" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x75, 0xf5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdcmlah z21.s, z10.s, z5.s[1], #90" + + - + input: + bytes: [ 0x20, 0x30, 0x02, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z0.b, z1.b, z2.b, #0" + + - + input: + bytes: [ 0x20, 0x30, 0x42, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z0.h, z1.h, z2.h, #0" + + - + input: + bytes: [ 0x20, 0x30, 0x82, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z0.s, z1.s, z2.s, #0" + + - + input: + bytes: [ 0x20, 0x30, 0xc2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z0.d, z1.d, z2.d, #0" + + - + input: + bytes: [ 0xdd, 0x37, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z29.b, z30.b, z31.b, #90" + + - + input: + bytes: [ 0xdd, 0x37, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z29.h, z30.h, z31.h, #90" + + - + input: + bytes: [ 0xdd, 0x37, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z29.s, z30.s, z31.s, #90" + + - + input: + bytes: [ 0xdd, 0x37, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z29.d, z30.d, z31.d, #90" + + - + input: + bytes: [ 0xff, 0x3b, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z31.b, z31.b, z31.b, #180" + + - + input: + bytes: [ 0xff, 0x3b, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z31.h, z31.h, z31.h, #180" + + - + input: + bytes: [ 0xff, 0x3b, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z31.s, z31.s, z31.s, #180" + + - + input: + bytes: [ 0xff, 0x3b, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z31.d, z31.d, z31.d, #180" + + - + input: + bytes: [ 0x0f, 0x3e, 0x11, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z15.b, z16.b, z17.b, #270" + + - + input: + bytes: [ 0x0f, 0x3e, 0x51, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z15.h, z16.h, z17.h, #270" + + - + input: + bytes: [ 0x0f, 0x3e, 0x91, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z15.s, z16.s, z17.s, #270" + + - + input: + bytes: [ 0x0f, 0x3e, 0xd1, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z15.d, z16.d, z17.d, #270" + + - + input: + bytes: [ 0x20, 0x70, 0xa2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z0.h, z1.h, z2.h[0], #0" + + - + input: + bytes: [ 0x20, 0x70, 0xe2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z0.s, z1.s, z2.s[0], #0" + + - + input: + bytes: [ 0xdf, 0x7b, 0xa7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z31.h, z30.h, z7.h[0], #180" + + - + input: + bytes: [ 0xdf, 0x7b, 0xe7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z31.s, z30.s, z7.s[0], #180" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0x3f, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z4.d, z31.d, z31.d, #270" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x75, 0xf5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdcmlah z21.s, z10.s, z5.s[1], #90" diff --git a/tests/MC/AArch64/SVE2/sqrdmlah.s.yaml b/tests/MC/AArch64/SVE2/sqrdmlah.s.yaml new file mode 100644 index 0000000000..70a46f2840 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqrdmlah.s.yaml @@ -0,0 +1,220 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x70, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmlah z0.b, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x70, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmlah z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x70, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmlah z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x70, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmlah z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x10, 0x7f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmlah z0.h, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x10, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmlah z0.s, z1.s, z7.s[3]" + + - + input: + bytes: [ 0x20, 0x10, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmlah z0.d, z1.d, z15.d[1]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x70, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmlah z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x10, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmlah z0.d, z1.d, z15.d[1]" + + - + input: + bytes: [ 0x20, 0x70, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmlah z0.b, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x70, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmlah z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x70, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmlah z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x70, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmlah z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x10, 0x7f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmlah z0.h, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x10, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmlah z0.s, z1.s, z7.s[3]" + + - + input: + bytes: [ 0x20, 0x10, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmlah z0.d, z1.d, z15.d[1]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x70, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmlah z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x10, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmlah z0.d, z1.d, z15.d[1]" diff --git a/tests/MC/AArch64/SVE2/sqrdmlsh.s.yaml b/tests/MC/AArch64/SVE2/sqrdmlsh.s.yaml new file mode 100644 index 0000000000..8a2b1a202c --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqrdmlsh.s.yaml @@ -0,0 +1,220 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x74, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmlsh z0.b, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x74, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmlsh z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x74, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmlsh z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x74, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmlsh z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x14, 0x7f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmlsh z0.h, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x14, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmlsh z0.s, z1.s, z7.s[3]" + + - + input: + bytes: [ 0x20, 0x14, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmlsh z0.d, z1.d, z15.d[1]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x74, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmlsh z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x14, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmlsh z0.d, z1.d, z15.d[1]" + + - + input: + bytes: [ 0x20, 0x74, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmlsh z0.b, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x74, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmlsh z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x74, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmlsh z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x74, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmlsh z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x14, 0x7f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmlsh z0.h, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x14, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmlsh z0.s, z1.s, z7.s[3]" + + - + input: + bytes: [ 0x20, 0x14, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmlsh z0.d, z1.d, z15.d[1]" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x74, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmlsh z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0x14, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmlsh z0.d, z1.d, z15.d[1]" diff --git a/tests/MC/AArch64/SVE2/sqrdmulh.s.yaml b/tests/MC/AArch64/SVE2/sqrdmulh.s.yaml new file mode 100644 index 0000000000..acd4a3fe35 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqrdmulh.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x74, 0x22, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmulh z0.b, z1.b, z2.b" + + - + input: + bytes: [ 0x20, 0x74, 0x62, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmulh z0.h, z1.h, z2.h" + + - + input: + bytes: [ 0xdd, 0x77, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmulh z29.s, z30.s, z31.s" + + - + input: + bytes: [ 0xff, 0x77, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmulh z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x20, 0xf4, 0x7f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmulh z0.h, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xf4, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmulh z0.s, z1.s, z7.s[3]" + + - + input: + bytes: [ 0x20, 0xf4, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrdmulh z0.d, z1.d, z15.d[1]" + + - + input: + bytes: [ 0x20, 0x74, 0x22, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmulh z0.b, z1.b, z2.b" + + - + input: + bytes: [ 0x20, 0x74, 0x62, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmulh z0.h, z1.h, z2.h" + + - + input: + bytes: [ 0xdd, 0x77, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmulh z29.s, z30.s, z31.s" + + - + input: + bytes: [ 0xff, 0x77, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmulh z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x20, 0xf4, 0x7f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmulh z0.h, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xf4, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmulh z0.s, z1.s, z7.s[3]" + + - + input: + bytes: [ 0x20, 0xf4, 0xff, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrdmulh z0.d, z1.d, z15.d[1]" diff --git a/tests/MC/AArch64/SVE2/sqrshl.s.yaml b/tests/MC/AArch64/SVE2/sqrshl.s.yaml new file mode 100644 index 0000000000..d3727bf380 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqrshl.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x0a, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshl z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x4a, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshl z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x8a, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshl z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xca, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xca, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshl z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xca, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x0a, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshl z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x4a, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshl z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x8a, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshl z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xca, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xca, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshl z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xca, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshl z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/sqrshlr.s.yaml b/tests/MC/AArch64/SVE2/sqrshlr.s.yaml new file mode 100644 index 0000000000..d2f59e2d29 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqrshlr.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x0e, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshlr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x4e, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshlr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x8e, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshlr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xce, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshlr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xce, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshlr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xce, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshlr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x0e, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshlr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x4e, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshlr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x8e, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshlr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xce, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshlr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xce, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshlr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xce, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshlr z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/sqrshrnb.s.yaml b/tests/MC/AArch64/SVE2/sqrshrnb.s.yaml new file mode 100644 index 0000000000..5b3fb2465d --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqrshrnb.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x28, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrnb z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x2b, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrnb z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x28, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrnb z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x2b, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrnb z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x28, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrnb z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x2b, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrnb z31.s, z31.d, #32" + + - + input: + bytes: [ 0x00, 0x28, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrnb z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x2b, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrnb z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x28, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrnb z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x2b, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrnb z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x28, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrnb z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x2b, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrnb z31.s, z31.d, #32" diff --git a/tests/MC/AArch64/SVE2/sqrshrnt.s.yaml b/tests/MC/AArch64/SVE2/sqrshrnt.s.yaml new file mode 100644 index 0000000000..36d532094b --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqrshrnt.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x2c, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrnt z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x2f, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrnt z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x2c, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrnt z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x2f, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrnt z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x2c, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrnt z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x2f, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrnt z31.s, z31.d, #32" + + - + input: + bytes: [ 0x00, 0x2c, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrnt z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x2f, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrnt z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x2c, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrnt z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x2f, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrnt z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x2c, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrnt z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x2f, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrnt z31.s, z31.d, #32" diff --git a/tests/MC/AArch64/SVE2/sqrshrunb.s.yaml b/tests/MC/AArch64/SVE2/sqrshrunb.s.yaml new file mode 100644 index 0000000000..f90899a7cf --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqrshrunb.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x08, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrunb z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x0b, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrunb z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x08, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrunb z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x0b, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrunb z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x08, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrunb z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x0b, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrunb z31.s, z31.d, #32" + + - + input: + bytes: [ 0x00, 0x08, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrunb z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x0b, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrunb z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x08, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrunb z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x0b, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrunb z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x08, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrunb z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x0b, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrunb z31.s, z31.d, #32" diff --git a/tests/MC/AArch64/SVE2/sqrshrunt.s.yaml b/tests/MC/AArch64/SVE2/sqrshrunt.s.yaml new file mode 100644 index 0000000000..e3f5fec292 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqrshrunt.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x0c, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrunt z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x0f, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrunt z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x0c, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrunt z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x0f, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrunt z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x0c, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrunt z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x0f, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqrshrunt z31.s, z31.d, #32" + + - + input: + bytes: [ 0x00, 0x0c, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrunt z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x0f, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrunt z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x0c, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrunt z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x0f, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrunt z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x0c, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrunt z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x0f, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqrshrunt z31.s, z31.d, #32" diff --git a/tests/MC/AArch64/SVE2/sqshl.s.yaml b/tests/MC/AArch64/SVE2/sqshl.s.yaml new file mode 100644 index 0000000000..e22b0a8e80 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqshl.s.yaml @@ -0,0 +1,400 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshl z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x48, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshl z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshl z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x00, 0x81, 0x06, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshl z0.b, p0/m, z0.b, #0" + + - + input: + bytes: [ 0xff, 0x81, 0x06, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshl z31.b, p0/m, z31.b, #7" + + - + input: + bytes: [ 0x00, 0x82, 0x06, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshl z0.h, p0/m, z0.h, #0" + + - + input: + bytes: [ 0xff, 0x83, 0x06, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshl z31.h, p0/m, z31.h, #15" + + - + input: + bytes: [ 0x00, 0x80, 0x46, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshl z0.s, p0/m, z0.s, #0" + + - + input: + bytes: [ 0xff, 0x83, 0x46, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshl z31.s, p0/m, z31.s, #31" + + - + input: + bytes: [ 0x00, 0x80, 0x86, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshl z0.d, p0/m, z0.d, #0" + + - + input: + bytes: [ 0xff, 0x83, 0xc6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshl z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshl z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xff, 0x83, 0xc6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshl z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0x83, 0xc6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshl z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0x20, 0x80, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshl z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x48, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshl z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshl z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x00, 0x81, 0x06, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshl z0.b, p0/m, z0.b, #0" + + - + input: + bytes: [ 0xff, 0x81, 0x06, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshl z31.b, p0/m, z31.b, #7" + + - + input: + bytes: [ 0x00, 0x82, 0x06, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshl z0.h, p0/m, z0.h, #0" + + - + input: + bytes: [ 0xff, 0x83, 0x06, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshl z31.h, p0/m, z31.h, #15" + + - + input: + bytes: [ 0x00, 0x80, 0x46, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshl z0.s, p0/m, z0.s, #0" + + - + input: + bytes: [ 0xff, 0x83, 0x46, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshl z31.s, p0/m, z31.s, #31" + + - + input: + bytes: [ 0x00, 0x80, 0x86, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshl z0.d, p0/m, z0.d, #0" + + - + input: + bytes: [ 0xff, 0x83, 0xc6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshl z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshl z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xff, 0x83, 0xc6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshl z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0x83, 0xc6, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshl z31.d, p0/m, z31.d, #63" diff --git a/tests/MC/AArch64/SVE2/sqshlr.s.yaml b/tests/MC/AArch64/SVE2/sqshlr.s.yaml new file mode 100644 index 0000000000..27e376745c --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqshlr.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x0c, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshlr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x4c, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshlr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x8c, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshlr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xcc, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshlr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xcc, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshlr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xcc, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshlr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x0c, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshlr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x4c, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshlr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x8c, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshlr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xcc, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshlr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xcc, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshlr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xcc, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshlr z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/sqshlu.s.yaml b/tests/MC/AArch64/SVE2/sqshlu.s.yaml new file mode 100644 index 0000000000..bbf876d095 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqshlu.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x81, 0x0f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshlu z0.b, p0/m, z0.b, #0" + + - + input: + bytes: [ 0xff, 0x81, 0x0f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshlu z31.b, p0/m, z31.b, #7" + + - + input: + bytes: [ 0x00, 0x82, 0x0f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshlu z0.h, p0/m, z0.h, #0" + + - + input: + bytes: [ 0xff, 0x83, 0x0f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshlu z31.h, p0/m, z31.h, #15" + + - + input: + bytes: [ 0x00, 0x80, 0x4f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshlu z0.s, p0/m, z0.s, #0" + + - + input: + bytes: [ 0xff, 0x83, 0x4f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshlu z31.s, p0/m, z31.s, #31" + + - + input: + bytes: [ 0x00, 0x80, 0x8f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshlu z0.d, p0/m, z0.d, #0" + + - + input: + bytes: [ 0xff, 0x83, 0xcf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshlu z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xff, 0x83, 0xcf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshlu z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0x83, 0xcf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshlu z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0x00, 0x81, 0x0f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshlu z0.b, p0/m, z0.b, #0" + + - + input: + bytes: [ 0xff, 0x81, 0x0f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshlu z31.b, p0/m, z31.b, #7" + + - + input: + bytes: [ 0x00, 0x82, 0x0f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshlu z0.h, p0/m, z0.h, #0" + + - + input: + bytes: [ 0xff, 0x83, 0x0f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshlu z31.h, p0/m, z31.h, #15" + + - + input: + bytes: [ 0x00, 0x80, 0x4f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshlu z0.s, p0/m, z0.s, #0" + + - + input: + bytes: [ 0xff, 0x83, 0x4f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshlu z31.s, p0/m, z31.s, #31" + + - + input: + bytes: [ 0x00, 0x80, 0x8f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshlu z0.d, p0/m, z0.d, #0" + + - + input: + bytes: [ 0xff, 0x83, 0xcf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshlu z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xff, 0x83, 0xcf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshlu z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0x83, 0xcf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshlu z31.d, p0/m, z31.d, #63" diff --git a/tests/MC/AArch64/SVE2/sqshrnb.s.yaml b/tests/MC/AArch64/SVE2/sqshrnb.s.yaml new file mode 100644 index 0000000000..8955126b43 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqshrnb.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrnb z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x23, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrnb z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x20, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrnb z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x23, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrnb z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x20, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrnb z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x23, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrnb z31.s, z31.d, #32" + + - + input: + bytes: [ 0x00, 0x20, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrnb z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x23, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrnb z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x20, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrnb z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x23, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrnb z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x20, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrnb z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x23, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrnb z31.s, z31.d, #32" diff --git a/tests/MC/AArch64/SVE2/sqshrnt.s.yaml b/tests/MC/AArch64/SVE2/sqshrnt.s.yaml new file mode 100644 index 0000000000..fc2d8daad9 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqshrnt.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x24, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrnt z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x27, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrnt z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x24, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrnt z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x27, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrnt z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x24, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrnt z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x27, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrnt z31.s, z31.d, #32" + + - + input: + bytes: [ 0x00, 0x24, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrnt z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x27, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrnt z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x24, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrnt z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x27, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrnt z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x24, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrnt z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x27, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrnt z31.s, z31.d, #32" diff --git a/tests/MC/AArch64/SVE2/sqshrunb.s.yaml b/tests/MC/AArch64/SVE2/sqshrunb.s.yaml new file mode 100644 index 0000000000..b707d1ca95 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqshrunb.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrunb z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x03, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrunb z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x00, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrunb z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x03, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrunb z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x00, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrunb z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x03, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrunb z31.s, z31.d, #32" + + - + input: + bytes: [ 0x00, 0x00, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrunb z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x03, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrunb z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x00, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrunb z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x03, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrunb z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x00, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrunb z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x03, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrunb z31.s, z31.d, #32" diff --git a/tests/MC/AArch64/SVE2/sqshrunt.s.yaml b/tests/MC/AArch64/SVE2/sqshrunt.s.yaml new file mode 100644 index 0000000000..562785aa51 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqshrunt.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x04, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrunt z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x07, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrunt z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x04, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrunt z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x07, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrunt z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x04, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrunt z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x07, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqshrunt z31.s, z31.d, #32" + + - + input: + bytes: [ 0x00, 0x04, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrunt z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x07, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrunt z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x04, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrunt z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x07, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrunt z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x04, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrunt z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x07, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqshrunt z31.s, z31.d, #32" diff --git a/tests/MC/AArch64/SVE2/sqsub.s.yaml b/tests/MC/AArch64/SVE2/sqsub.s.yaml new file mode 100644 index 0000000000..81bbf64a51 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqsub.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x1a, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqsub z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x5a, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqsub z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x9a, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqsub z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xda, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqsub z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xda, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqsub z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xda, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqsub z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x1a, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x5a, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x9a, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xda, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xda, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xda, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsub z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/sqsubr.s.yaml b/tests/MC/AArch64/SVE2/sqsubr.s.yaml new file mode 100644 index 0000000000..4f3a5fbc6b --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqsubr.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x1e, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqsubr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x5e, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqsubr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x9e, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqsubr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xde, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqsubr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xde, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqsubr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xde, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqsubr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x1e, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsubr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x5e, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsubr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x9e, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsubr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xde, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsubr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xde, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsubr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xde, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqsubr z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/sqxtnb.s.yaml b/tests/MC/AArch64/SVE2/sqxtnb.s.yaml new file mode 100644 index 0000000000..e8496db709 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqxtnb.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x43, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqxtnb z0.b, z31.h" + + - + input: + bytes: [ 0xe0, 0x43, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqxtnb z0.h, z31.s" + + - + input: + bytes: [ 0xe0, 0x43, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqxtnb z0.s, z31.d" + + - + input: + bytes: [ 0xe0, 0x43, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqxtnb z0.b, z31.h" + + - + input: + bytes: [ 0xe0, 0x43, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqxtnb z0.h, z31.s" + + - + input: + bytes: [ 0xe0, 0x43, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqxtnb z0.s, z31.d" diff --git a/tests/MC/AArch64/SVE2/sqxtnt.s.yaml b/tests/MC/AArch64/SVE2/sqxtnt.s.yaml new file mode 100644 index 0000000000..a03bc5a649 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqxtnt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x47, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqxtnt z0.b, z31.h" + + - + input: + bytes: [ 0xe0, 0x47, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqxtnt z0.h, z31.s" + + - + input: + bytes: [ 0xe0, 0x47, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqxtnt z0.s, z31.d" + + - + input: + bytes: [ 0xe0, 0x47, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqxtnt z0.b, z31.h" + + - + input: + bytes: [ 0xe0, 0x47, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqxtnt z0.h, z31.s" + + - + input: + bytes: [ 0xe0, 0x47, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqxtnt z0.s, z31.d" diff --git a/tests/MC/AArch64/SVE2/sqxtunb.s.yaml b/tests/MC/AArch64/SVE2/sqxtunb.s.yaml new file mode 100644 index 0000000000..b7f4e0b049 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqxtunb.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x53, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqxtunb z0.b, z31.h" + + - + input: + bytes: [ 0xe0, 0x53, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqxtunb z0.h, z31.s" + + - + input: + bytes: [ 0xe0, 0x53, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqxtunb z0.s, z31.d" + + - + input: + bytes: [ 0xe0, 0x53, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqxtunb z0.b, z31.h" + + - + input: + bytes: [ 0xe0, 0x53, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqxtunb z0.h, z31.s" + + - + input: + bytes: [ 0xe0, 0x53, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqxtunb z0.s, z31.d" diff --git a/tests/MC/AArch64/SVE2/sqxtunt.s.yaml b/tests/MC/AArch64/SVE2/sqxtunt.s.yaml new file mode 100644 index 0000000000..39d4f40cf6 --- /dev/null +++ b/tests/MC/AArch64/SVE2/sqxtunt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x57, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqxtunt z0.b, z31.h" + + - + input: + bytes: [ 0xe0, 0x57, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqxtunt z0.h, z31.s" + + - + input: + bytes: [ 0xe0, 0x57, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sqxtunt z0.s, z31.d" + + - + input: + bytes: [ 0xe0, 0x57, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqxtunt z0.b, z31.h" + + - + input: + bytes: [ 0xe0, 0x57, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqxtunt z0.h, z31.s" + + - + input: + bytes: [ 0xe0, 0x57, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sqxtunt z0.s, z31.d" diff --git a/tests/MC/AArch64/SVE2/srhadd.s.yaml b/tests/MC/AArch64/SVE2/srhadd.s.yaml new file mode 100644 index 0000000000..d8c9b43910 --- /dev/null +++ b/tests/MC/AArch64/SVE2/srhadd.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x14, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srhadd z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x54, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srhadd z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x94, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srhadd z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd4, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srhadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd4, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srhadd z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd4, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srhadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x14, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srhadd z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x54, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srhadd z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x94, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srhadd z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd4, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srhadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd4, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srhadd z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd4, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srhadd z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/sri.s.yaml b/tests/MC/AArch64/SVE2/sri.s.yaml new file mode 100644 index 0000000000..4d5fcd36cb --- /dev/null +++ b/tests/MC/AArch64/SVE2/sri.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xf0, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sri z0.b, z0.b, #1" + + - + input: + bytes: [ 0xff, 0xf3, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sri z31.b, z31.b, #8" + + - + input: + bytes: [ 0x00, 0xf0, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sri z0.h, z0.h, #1" + + - + input: + bytes: [ 0xff, 0xf3, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sri z31.h, z31.h, #16" + + - + input: + bytes: [ 0x00, 0xf0, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sri z0.s, z0.s, #1" + + - + input: + bytes: [ 0xff, 0xf3, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sri z31.s, z31.s, #32" + + - + input: + bytes: [ 0x00, 0xf0, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sri z0.d, z0.d, #1" + + - + input: + bytes: [ 0xff, 0xf3, 0x80, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sri z31.d, z31.d, #64" + + - + input: + bytes: [ 0x00, 0xf0, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sri z0.b, z0.b, #1" + + - + input: + bytes: [ 0xff, 0xf3, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sri z31.b, z31.b, #8" + + - + input: + bytes: [ 0x00, 0xf0, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sri z0.h, z0.h, #1" + + - + input: + bytes: [ 0xff, 0xf3, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sri z31.h, z31.h, #16" + + - + input: + bytes: [ 0x00, 0xf0, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sri z0.s, z0.s, #1" + + - + input: + bytes: [ 0xff, 0xf3, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sri z31.s, z31.s, #32" + + - + input: + bytes: [ 0x00, 0xf0, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sri z0.d, z0.d, #1" + + - + input: + bytes: [ 0xff, 0xf3, 0x80, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sri z31.d, z31.d, #64" diff --git a/tests/MC/AArch64/SVE2/srshl.s.yaml b/tests/MC/AArch64/SVE2/srshl.s.yaml new file mode 100644 index 0000000000..47b5066c9f --- /dev/null +++ b/tests/MC/AArch64/SVE2/srshl.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x02, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshl z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x42, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshl z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x82, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshl z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xc2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshl z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x02, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshl z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x42, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshl z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x82, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshl z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xc2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshl z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc2, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshl z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/srshlr.s.yaml b/tests/MC/AArch64/SVE2/srshlr.s.yaml new file mode 100644 index 0000000000..f23e18ed09 --- /dev/null +++ b/tests/MC/AArch64/SVE2/srshlr.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x06, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshlr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x46, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshlr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x86, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshlr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc6, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshlr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xc6, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshlr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc6, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshlr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x06, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshlr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x46, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshlr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x86, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshlr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc6, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshlr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xc6, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshlr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc6, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshlr z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/srshr.s.yaml b/tests/MC/AArch64/SVE2/srshr.s.yaml new file mode 100644 index 0000000000..d0e9051cb8 --- /dev/null +++ b/tests/MC/AArch64/SVE2/srshr.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x81, 0x0c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshr z0.b, p0/m, z0.b, #1" + + - + input: + bytes: [ 0x1f, 0x81, 0x0c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshr z31.b, p0/m, z31.b, #8" + + - + input: + bytes: [ 0xe0, 0x83, 0x0c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshr z0.h, p0/m, z0.h, #1" + + - + input: + bytes: [ 0x1f, 0x82, 0x0c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshr z31.h, p0/m, z31.h, #16" + + - + input: + bytes: [ 0xe0, 0x83, 0x4c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshr z0.s, p0/m, z0.s, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x4c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshr z31.s, p0/m, z31.s, #32" + + - + input: + bytes: [ 0xe0, 0x83, 0xcc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshr z0.d, p0/m, z0.d, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x8c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0x1f, 0x80, 0x8c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x1f, 0x80, 0x8c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srshr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xe0, 0x81, 0x0c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshr z0.b, p0/m, z0.b, #1" + + - + input: + bytes: [ 0x1f, 0x81, 0x0c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshr z31.b, p0/m, z31.b, #8" + + - + input: + bytes: [ 0xe0, 0x83, 0x0c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshr z0.h, p0/m, z0.h, #1" + + - + input: + bytes: [ 0x1f, 0x82, 0x0c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshr z31.h, p0/m, z31.h, #16" + + - + input: + bytes: [ 0xe0, 0x83, 0x4c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshr z0.s, p0/m, z0.s, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x4c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshr z31.s, p0/m, z31.s, #32" + + - + input: + bytes: [ 0xe0, 0x83, 0xcc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshr z0.d, p0/m, z0.d, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x8c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0x1f, 0x80, 0x8c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x1f, 0x80, 0x8c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srshr z31.d, p0/m, z31.d, #64" diff --git a/tests/MC/AArch64/SVE2/srsra.s.yaml b/tests/MC/AArch64/SVE2/srsra.s.yaml new file mode 100644 index 0000000000..65c7cb59c9 --- /dev/null +++ b/tests/MC/AArch64/SVE2/srsra.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe8, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srsra z0.b, z0.b, #1" + + - + input: + bytes: [ 0xff, 0xeb, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srsra z31.b, z31.b, #8" + + - + input: + bytes: [ 0x00, 0xe8, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srsra z0.h, z0.h, #1" + + - + input: + bytes: [ 0xff, 0xeb, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srsra z31.h, z31.h, #16" + + - + input: + bytes: [ 0x00, 0xe8, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srsra z0.s, z0.s, #1" + + - + input: + bytes: [ 0xff, 0xeb, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srsra z31.s, z31.s, #32" + + - + input: + bytes: [ 0x00, 0xe8, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srsra z0.d, z0.d, #1" + + - + input: + bytes: [ 0xff, 0xeb, 0x80, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srsra z31.d, z31.d, #64" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xe8, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "srsra z0.d, z1.d, #1" + + - + input: + bytes: [ 0x00, 0xe8, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srsra z0.b, z0.b, #1" + + - + input: + bytes: [ 0xff, 0xeb, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srsra z31.b, z31.b, #8" + + - + input: + bytes: [ 0x00, 0xe8, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srsra z0.h, z0.h, #1" + + - + input: + bytes: [ 0xff, 0xeb, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srsra z31.h, z31.h, #16" + + - + input: + bytes: [ 0x00, 0xe8, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srsra z0.s, z0.s, #1" + + - + input: + bytes: [ 0xff, 0xeb, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srsra z31.s, z31.s, #32" + + - + input: + bytes: [ 0x00, 0xe8, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srsra z0.d, z0.d, #1" + + - + input: + bytes: [ 0xff, 0xeb, 0x80, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srsra z31.d, z31.d, #64" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xe8, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "srsra z0.d, z1.d, #1" diff --git a/tests/MC/AArch64/SVE2/sshllb.s.yaml b/tests/MC/AArch64/SVE2/sshllb.s.yaml new file mode 100644 index 0000000000..a6dc67bb1f --- /dev/null +++ b/tests/MC/AArch64/SVE2/sshllb.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sshllb z0.h, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xa3, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sshllb z31.h, z31.b, #7" + + - + input: + bytes: [ 0x00, 0xa0, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sshllb z0.s, z0.h, #0" + + - + input: + bytes: [ 0xff, 0xa3, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sshllb z31.s, z31.h, #15" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sshllb z0.d, z0.s, #0" + + - + input: + bytes: [ 0xff, 0xa3, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sshllb z31.d, z31.s, #31" + + - + input: + bytes: [ 0x00, 0xa0, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sshllb z0.h, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xa3, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sshllb z31.h, z31.b, #7" + + - + input: + bytes: [ 0x00, 0xa0, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sshllb z0.s, z0.h, #0" + + - + input: + bytes: [ 0xff, 0xa3, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sshllb z31.s, z31.h, #15" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sshllb z0.d, z0.s, #0" + + - + input: + bytes: [ 0xff, 0xa3, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sshllb z31.d, z31.s, #31" diff --git a/tests/MC/AArch64/SVE2/sshllt.s.yaml b/tests/MC/AArch64/SVE2/sshllt.s.yaml new file mode 100644 index 0000000000..b87b0ef91b --- /dev/null +++ b/tests/MC/AArch64/SVE2/sshllt.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa4, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sshllt z0.h, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xa7, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sshllt z31.h, z31.b, #7" + + - + input: + bytes: [ 0x00, 0xa4, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sshllt z0.s, z0.h, #0" + + - + input: + bytes: [ 0xff, 0xa7, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sshllt z31.s, z31.h, #15" + + - + input: + bytes: [ 0x00, 0xa4, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sshllt z0.d, z0.s, #0" + + - + input: + bytes: [ 0xff, 0xa7, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "sshllt z31.d, z31.s, #31" + + - + input: + bytes: [ 0x00, 0xa4, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sshllt z0.h, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xa7, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sshllt z31.h, z31.b, #7" + + - + input: + bytes: [ 0x00, 0xa4, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sshllt z0.s, z0.h, #0" + + - + input: + bytes: [ 0xff, 0xa7, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sshllt z31.s, z31.h, #15" + + - + input: + bytes: [ 0x00, 0xa4, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sshllt z0.d, z0.s, #0" + + - + input: + bytes: [ 0xff, 0xa7, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "sshllt z31.d, z31.s, #31" diff --git a/tests/MC/AArch64/SVE2/ssra.s.yaml b/tests/MC/AArch64/SVE2/ssra.s.yaml new file mode 100644 index 0000000000..3d8c8a58af --- /dev/null +++ b/tests/MC/AArch64/SVE2/ssra.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssra z0.b, z0.b, #1" + + - + input: + bytes: [ 0xff, 0xe3, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssra z31.b, z31.b, #8" + + - + input: + bytes: [ 0x00, 0xe0, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssra z0.h, z0.h, #1" + + - + input: + bytes: [ 0xff, 0xe3, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssra z31.h, z31.h, #16" + + - + input: + bytes: [ 0x00, 0xe0, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssra z0.s, z0.s, #1" + + - + input: + bytes: [ 0xff, 0xe3, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssra z31.s, z31.s, #32" + + - + input: + bytes: [ 0x00, 0xe0, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssra z0.d, z0.d, #1" + + - + input: + bytes: [ 0xff, 0xe3, 0x80, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssra z31.d, z31.d, #64" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xe0, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssra z0.d, z1.d, #1" + + - + input: + bytes: [ 0x00, 0xe0, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssra z0.b, z0.b, #1" + + - + input: + bytes: [ 0xff, 0xe3, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssra z31.b, z31.b, #8" + + - + input: + bytes: [ 0x00, 0xe0, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssra z0.h, z0.h, #1" + + - + input: + bytes: [ 0xff, 0xe3, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssra z31.h, z31.h, #16" + + - + input: + bytes: [ 0x00, 0xe0, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssra z0.s, z0.s, #1" + + - + input: + bytes: [ 0xff, 0xe3, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssra z31.s, z31.s, #32" + + - + input: + bytes: [ 0x00, 0xe0, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssra z0.d, z0.d, #1" + + - + input: + bytes: [ 0xff, 0xe3, 0x80, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssra z31.d, z31.d, #64" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xe0, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssra z0.d, z1.d, #1" diff --git a/tests/MC/AArch64/SVE2/ssublb.s.yaml b/tests/MC/AArch64/SVE2/ssublb.s.yaml new file mode 100644 index 0000000000..2ec0a5e63e --- /dev/null +++ b/tests/MC/AArch64/SVE2/ssublb.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x10, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssublb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x13, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssublb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x13, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssublb z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0x10, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssublb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x13, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssublb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x13, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssublb z31.d, z31.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/ssublbt.s.yaml b/tests/MC/AArch64/SVE2/ssublbt.s.yaml new file mode 100644 index 0000000000..81272feae1 --- /dev/null +++ b/tests/MC/AArch64/SVE2/ssublbt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x88, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssublbt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x88, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssublbt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x88, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssublbt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x88, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssublbt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x88, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssublbt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x88, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssublbt z0.d, z1.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/ssublt.s.yaml b/tests/MC/AArch64/SVE2/ssublt.s.yaml new file mode 100644 index 0000000000..71578eb298 --- /dev/null +++ b/tests/MC/AArch64/SVE2/ssublt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x14, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssublt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x17, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssublt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x17, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssublt z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0x14, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssublt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x17, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssublt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x17, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssublt z31.d, z31.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/ssubltb.s.yaml b/tests/MC/AArch64/SVE2/ssubltb.s.yaml new file mode 100644 index 0000000000..1e60155303 --- /dev/null +++ b/tests/MC/AArch64/SVE2/ssubltb.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x8c, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssubltb z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x8c, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssubltb z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x8c, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssubltb z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x8c, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssubltb z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x8c, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssubltb z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x8c, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssubltb z0.d, z1.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/ssubwb.s.yaml b/tests/MC/AArch64/SVE2/ssubwb.s.yaml new file mode 100644 index 0000000000..8ac090edc8 --- /dev/null +++ b/tests/MC/AArch64/SVE2/ssubwb.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x50, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssubwb z0.h, z1.h, z2.b" + + - + input: + bytes: [ 0xdd, 0x53, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssubwb z29.s, z30.s, z31.h" + + - + input: + bytes: [ 0xff, 0x53, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssubwb z31.d, z31.d, z31.s" + + - + input: + bytes: [ 0x20, 0x50, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssubwb z0.h, z1.h, z2.b" + + - + input: + bytes: [ 0xdd, 0x53, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssubwb z29.s, z30.s, z31.h" + + - + input: + bytes: [ 0xff, 0x53, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssubwb z31.d, z31.d, z31.s" diff --git a/tests/MC/AArch64/SVE2/ssubwt.s.yaml b/tests/MC/AArch64/SVE2/ssubwt.s.yaml new file mode 100644 index 0000000000..35423b7486 --- /dev/null +++ b/tests/MC/AArch64/SVE2/ssubwt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x54, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssubwt z0.h, z1.h, z2.b" + + - + input: + bytes: [ 0xdd, 0x57, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssubwt z29.s, z30.s, z31.h" + + - + input: + bytes: [ 0xff, 0x57, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ssubwt z31.d, z31.d, z31.s" + + - + input: + bytes: [ 0x20, 0x54, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssubwt z0.h, z1.h, z2.b" + + - + input: + bytes: [ 0xdd, 0x57, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssubwt z29.s, z30.s, z31.h" + + - + input: + bytes: [ 0xff, 0x57, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ssubwt z31.d, z31.d, z31.s" diff --git a/tests/MC/AArch64/SVE2/stnt1b.s.yaml b/tests/MC/AArch64/SVE2/stnt1b.s.yaml new file mode 100644 index 0000000000..f3c3ec8a60 --- /dev/null +++ b/tests/MC/AArch64/SVE2/stnt1b.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x20, 0x5f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1b { z0.s }, p0, [z1.s]" + + - + input: + bytes: [ 0xff, 0x3f, 0x5f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1b { z31.s }, p7, [z31.s]" + + - + input: + bytes: [ 0xff, 0x3f, 0x40, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1b { z31.s }, p7, [z31.s, x0]" + + - + input: + bytes: [ 0x20, 0x20, 0x1f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1b { z0.d }, p0, [z1.d]" + + - + input: + bytes: [ 0xff, 0x3f, 0x1f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1b { z31.d }, p7, [z31.d]" + + - + input: + bytes: [ 0xff, 0x3f, 0x00, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1b { z31.d }, p7, [z31.d, x0]" + + - + input: + bytes: [ 0x20, 0x20, 0x5f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1b { z0.s }, p0, [z1.s]" + + - + input: + bytes: [ 0xff, 0x3f, 0x5f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1b { z31.s }, p7, [z31.s]" + + - + input: + bytes: [ 0xff, 0x3f, 0x40, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1b { z31.s }, p7, [z31.s, x0]" + + - + input: + bytes: [ 0x20, 0x20, 0x1f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1b { z0.d }, p0, [z1.d]" + + - + input: + bytes: [ 0xff, 0x3f, 0x1f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1b { z31.d }, p7, [z31.d]" + + - + input: + bytes: [ 0xff, 0x3f, 0x00, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1b { z31.d }, p7, [z31.d, x0]" diff --git a/tests/MC/AArch64/SVE2/stnt1d.s.yaml b/tests/MC/AArch64/SVE2/stnt1d.s.yaml new file mode 100644 index 0000000000..39801b6438 --- /dev/null +++ b/tests/MC/AArch64/SVE2/stnt1d.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x20, 0x9f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d }, p0, [z1.d]" + + - + input: + bytes: [ 0xff, 0x3f, 0x9f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1d { z31.d }, p7, [z31.d]" + + - + input: + bytes: [ 0xff, 0x3f, 0x80, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1d { z31.d }, p7, [z31.d, x0]" + + - + input: + bytes: [ 0x20, 0x20, 0x9f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d }, p0, [z1.d]" + + - + input: + bytes: [ 0xff, 0x3f, 0x9f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1d { z31.d }, p7, [z31.d]" + + - + input: + bytes: [ 0xff, 0x3f, 0x80, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1d { z31.d }, p7, [z31.d, x0]" diff --git a/tests/MC/AArch64/SVE2/stnt1h.s.yaml b/tests/MC/AArch64/SVE2/stnt1h.s.yaml new file mode 100644 index 0000000000..5693d8a534 --- /dev/null +++ b/tests/MC/AArch64/SVE2/stnt1h.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x20, 0xdf, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1h { z0.s }, p0, [z1.s]" + + - + input: + bytes: [ 0xff, 0x3f, 0xdf, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1h { z31.s }, p7, [z31.s]" + + - + input: + bytes: [ 0xff, 0x3f, 0xc0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1h { z31.s }, p7, [z31.s, x0]" + + - + input: + bytes: [ 0x20, 0x20, 0x9f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1h { z0.d }, p0, [z1.d]" + + - + input: + bytes: [ 0xff, 0x3f, 0x9f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1h { z31.d }, p7, [z31.d]" + + - + input: + bytes: [ 0xff, 0x3f, 0x80, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1h { z31.d }, p7, [z31.d, x0]" + + - + input: + bytes: [ 0x20, 0x20, 0xdf, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1h { z0.s }, p0, [z1.s]" + + - + input: + bytes: [ 0xff, 0x3f, 0xdf, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1h { z31.s }, p7, [z31.s]" + + - + input: + bytes: [ 0xff, 0x3f, 0xc0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1h { z31.s }, p7, [z31.s, x0]" + + - + input: + bytes: [ 0x20, 0x20, 0x9f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1h { z0.d }, p0, [z1.d]" + + - + input: + bytes: [ 0xff, 0x3f, 0x9f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1h { z31.d }, p7, [z31.d]" + + - + input: + bytes: [ 0xff, 0x3f, 0x80, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1h { z31.d }, p7, [z31.d, x0]" diff --git a/tests/MC/AArch64/SVE2/stnt1w.s.yaml b/tests/MC/AArch64/SVE2/stnt1w.s.yaml new file mode 100644 index 0000000000..7554bb03c2 --- /dev/null +++ b/tests/MC/AArch64/SVE2/stnt1w.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x20, 0x5f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s }, p0, [z1.s]" + + - + input: + bytes: [ 0xff, 0x3f, 0x5f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1w { z31.s }, p7, [z31.s]" + + - + input: + bytes: [ 0xff, 0x3f, 0x40, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1w { z31.s }, p7, [z31.s, x0]" + + - + input: + bytes: [ 0x20, 0x20, 0x1f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1w { z0.d }, p0, [z1.d]" + + - + input: + bytes: [ 0xff, 0x3f, 0x1f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1w { z31.d }, p7, [z31.d]" + + - + input: + bytes: [ 0xff, 0x3f, 0x00, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1w { z31.d }, p7, [z31.d, x0]" + + - + input: + bytes: [ 0x20, 0x20, 0x5f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s }, p0, [z1.s]" + + - + input: + bytes: [ 0xff, 0x3f, 0x5f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1w { z31.s }, p7, [z31.s]" + + - + input: + bytes: [ 0xff, 0x3f, 0x40, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1w { z31.s }, p7, [z31.s, x0]" + + - + input: + bytes: [ 0x20, 0x20, 0x1f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1w { z0.d }, p0, [z1.d]" + + - + input: + bytes: [ 0xff, 0x3f, 0x1f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1w { z31.d }, p7, [z31.d]" + + - + input: + bytes: [ 0xff, 0x3f, 0x00, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "stnt1w { z31.d }, p7, [z31.d, x0]" diff --git a/tests/MC/AArch64/SVE2/subhnb.s.yaml b/tests/MC/AArch64/SVE2/subhnb.s.yaml new file mode 100644 index 0000000000..a2367e8918 --- /dev/null +++ b/tests/MC/AArch64/SVE2/subhnb.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x70, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "subhnb z0.b, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x70, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "subhnb z0.h, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x70, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "subhnb z0.s, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x70, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subhnb z0.b, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x70, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subhnb z0.h, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x70, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subhnb z0.s, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/subhnt.s.yaml b/tests/MC/AArch64/SVE2/subhnt.s.yaml new file mode 100644 index 0000000000..1de1714a65 --- /dev/null +++ b/tests/MC/AArch64/SVE2/subhnt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x74, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "subhnt z0.b, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x74, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "subhnt z0.h, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x74, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "subhnt z0.s, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0x74, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subhnt z0.b, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x74, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subhnt z0.h, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x74, 0xff, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "subhnt z0.s, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/suqadd.s.yaml b/tests/MC/AArch64/SVE2/suqadd.s.yaml new file mode 100644 index 0000000000..2366fac757 --- /dev/null +++ b/tests/MC/AArch64/SVE2/suqadd.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x1c, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "suqadd z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x5c, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "suqadd z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x9c, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "suqadd z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xdc, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "suqadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xdc, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "suqadd z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xdc, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "suqadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x1c, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "suqadd z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x5c, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "suqadd z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x9c, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "suqadd z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xdc, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "suqadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xdc, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "suqadd z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xdc, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "suqadd z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/tbl.s.yaml b/tests/MC/AArch64/SVE2/tbl.s.yaml new file mode 100644 index 0000000000..4b69f7e06c --- /dev/null +++ b/tests/MC/AArch64/SVE2/tbl.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xbc, 0x2b, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "tbl z28.b, { z29.b, z30.b }, z31.b" + + - + input: + bytes: [ 0xbc, 0x2b, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "tbl z28.h, { z29.h, z30.h }, z31.h" + + - + input: + bytes: [ 0xbc, 0x2b, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "tbl z28.s, { z29.s, z30.s }, z31.s" + + - + input: + bytes: [ 0xbc, 0x2b, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "tbl z28.d, { z29.d, z30.d }, z31.d" + + - + input: + bytes: [ 0xbc, 0x2b, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "tbl z28.b, { z29.b, z30.b }, z31.b" + + - + input: + bytes: [ 0xbc, 0x2b, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "tbl z28.h, { z29.h, z30.h }, z31.h" + + - + input: + bytes: [ 0xbc, 0x2b, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "tbl z28.s, { z29.s, z30.s }, z31.s" + + - + input: + bytes: [ 0xbc, 0x2b, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "tbl z28.d, { z29.d, z30.d }, z31.d" diff --git a/tests/MC/AArch64/SVE2/tbx.s.yaml b/tests/MC/AArch64/SVE2/tbx.s.yaml new file mode 100644 index 0000000000..305c1c2a9e --- /dev/null +++ b/tests/MC/AArch64/SVE2/tbx.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x2f, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "tbx z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x2f, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "tbx z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x2f, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "tbx z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x2f, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "tbx z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0xff, 0x2f, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "tbx z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0xff, 0x2f, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "tbx z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0xff, 0x2f, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "tbx z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0xff, 0x2f, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "tbx z31.d, z31.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/uaba.s.yaml b/tests/MC/AArch64/SVE2/uaba.s.yaml new file mode 100644 index 0000000000..e030597e10 --- /dev/null +++ b/tests/MC/AArch64/SVE2/uaba.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xfc, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uaba z0.b, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0xfc, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uaba z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xfc, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uaba z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xfc, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uaba z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xfc, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uaba z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0x20, 0xfc, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaba z0.b, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0xfc, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaba z0.h, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xfc, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaba z0.s, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xfc, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaba z0.d, z1.d, z31.d" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xfc, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaba z0.d, z1.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/uabalb.s.yaml b/tests/MC/AArch64/SVE2/uabalb.s.yaml new file mode 100644 index 0000000000..b279a81959 --- /dev/null +++ b/tests/MC/AArch64/SVE2/uabalb.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xc8, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uabalb z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0xc8, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uabalb z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xc8, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uabalb z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0xc8, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uabalb z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xc8, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabalb z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0xc8, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabalb z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xc8, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabalb z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0xc8, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabalb z21.d, z1.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/uabalt.s.yaml b/tests/MC/AArch64/SVE2/uabalt.s.yaml new file mode 100644 index 0000000000..a5882df5f4 --- /dev/null +++ b/tests/MC/AArch64/SVE2/uabalt.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xcc, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uabalt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0xcc, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uabalt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xcc, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uabalt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0xcc, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uabalt z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xcc, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabalt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0xcc, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabalt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0xcc, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabalt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0xcc, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabalt z21.d, z1.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/uabdlb.s.yaml b/tests/MC/AArch64/SVE2/uabdlb.s.yaml new file mode 100644 index 0000000000..e0835213d0 --- /dev/null +++ b/tests/MC/AArch64/SVE2/uabdlb.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x38, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uabdlb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x3b, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uabdlb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x3b, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uabdlb z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0x38, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabdlb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x3b, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabdlb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x3b, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabdlb z31.d, z31.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/uabdlt.s.yaml b/tests/MC/AArch64/SVE2/uabdlt.s.yaml new file mode 100644 index 0000000000..90496d2675 --- /dev/null +++ b/tests/MC/AArch64/SVE2/uabdlt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x3c, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uabdlt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x3f, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uabdlt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x3f, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uabdlt z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0x3c, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabdlt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x3f, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabdlt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x3f, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uabdlt z31.d, z31.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/uadalp.s.yaml b/tests/MC/AArch64/SVE2/uadalp.s.yaml new file mode 100644 index 0000000000..6e0d7eab37 --- /dev/null +++ b/tests/MC/AArch64/SVE2/uadalp.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa0, 0x45, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uadalp z0.h, p0/m, z1.b" + + - + input: + bytes: [ 0xdd, 0xa3, 0x85, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uadalp z29.s, p0/m, z30.h" + + - + input: + bytes: [ 0xfe, 0xbf, 0xc5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uadalp z30.d, p7/m, z31.s" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0xa3, 0xc5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uadalp z31.d, p0/m, z30.s" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0xa3, 0xc5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uadalp z31.d, p0/m, z30.s" + + - + input: + bytes: [ 0x20, 0xa0, 0x45, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uadalp z0.h, p0/m, z1.b" + + - + input: + bytes: [ 0xdd, 0xa3, 0x85, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uadalp z29.s, p0/m, z30.h" + + - + input: + bytes: [ 0xfe, 0xbf, 0xc5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uadalp z30.d, p7/m, z31.s" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0xa3, 0xc5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uadalp z31.d, p0/m, z30.s" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0xa3, 0xc5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uadalp z31.d, p0/m, z30.s" diff --git a/tests/MC/AArch64/SVE2/uaddlb.s.yaml b/tests/MC/AArch64/SVE2/uaddlb.s.yaml new file mode 100644 index 0000000000..cabe957fd7 --- /dev/null +++ b/tests/MC/AArch64/SVE2/uaddlb.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x08, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uaddlb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x0b, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uaddlb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x0b, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uaddlb z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0x08, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaddlb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x0b, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaddlb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x0b, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaddlb z31.d, z31.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/uaddlt.s.yaml b/tests/MC/AArch64/SVE2/uaddlt.s.yaml new file mode 100644 index 0000000000..f65753fa0b --- /dev/null +++ b/tests/MC/AArch64/SVE2/uaddlt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x0c, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uaddlt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x0f, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uaddlt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x0f, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uaddlt z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0x0c, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaddlt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x0f, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaddlt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x0f, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaddlt z31.d, z31.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/uaddwb.s.yaml b/tests/MC/AArch64/SVE2/uaddwb.s.yaml new file mode 100644 index 0000000000..b1d392dff6 --- /dev/null +++ b/tests/MC/AArch64/SVE2/uaddwb.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x48, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uaddwb z0.h, z1.h, z2.b" + + - + input: + bytes: [ 0xdd, 0x4b, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uaddwb z29.s, z30.s, z31.h" + + - + input: + bytes: [ 0xff, 0x4b, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uaddwb z31.d, z31.d, z31.s" + + - + input: + bytes: [ 0x20, 0x48, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaddwb z0.h, z1.h, z2.b" + + - + input: + bytes: [ 0xdd, 0x4b, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaddwb z29.s, z30.s, z31.h" + + - + input: + bytes: [ 0xff, 0x4b, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaddwb z31.d, z31.d, z31.s" diff --git a/tests/MC/AArch64/SVE2/uaddwt.s.yaml b/tests/MC/AArch64/SVE2/uaddwt.s.yaml new file mode 100644 index 0000000000..f5a4d906ae --- /dev/null +++ b/tests/MC/AArch64/SVE2/uaddwt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x4c, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uaddwt z0.h, z1.h, z2.b" + + - + input: + bytes: [ 0xdd, 0x4f, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uaddwt z29.s, z30.s, z31.h" + + - + input: + bytes: [ 0xff, 0x4f, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uaddwt z31.d, z31.d, z31.s" + + - + input: + bytes: [ 0x20, 0x4c, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaddwt z0.h, z1.h, z2.b" + + - + input: + bytes: [ 0xdd, 0x4f, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaddwt z29.s, z30.s, z31.h" + + - + input: + bytes: [ 0xff, 0x4f, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uaddwt z31.d, z31.d, z31.s" diff --git a/tests/MC/AArch64/SVE2/uhadd.s.yaml b/tests/MC/AArch64/SVE2/uhadd.s.yaml new file mode 100644 index 0000000000..1db9d9834a --- /dev/null +++ b/tests/MC/AArch64/SVE2/uhadd.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x11, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uhadd z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x51, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uhadd z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x91, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uhadd z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd1, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uhadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd1, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uhadd z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd1, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uhadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x11, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uhadd z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x51, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uhadd z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x91, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uhadd z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd1, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uhadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd1, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uhadd z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd1, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uhadd z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/uhsub.s.yaml b/tests/MC/AArch64/SVE2/uhsub.s.yaml new file mode 100644 index 0000000000..f02ac22d6c --- /dev/null +++ b/tests/MC/AArch64/SVE2/uhsub.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x13, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uhsub z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x53, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uhsub z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x93, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uhsub z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd3, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uhsub z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd3, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uhsub z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd3, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uhsub z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x13, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uhsub z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x53, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uhsub z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x93, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uhsub z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd3, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uhsub z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd3, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uhsub z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd3, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uhsub z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/uhsubr.s.yaml b/tests/MC/AArch64/SVE2/uhsubr.s.yaml new file mode 100644 index 0000000000..fcd864e2fd --- /dev/null +++ b/tests/MC/AArch64/SVE2/uhsubr.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x17, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uhsubr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x57, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uhsubr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x97, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uhsubr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uhsubr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uhsubr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uhsubr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x17, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uhsubr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x57, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uhsubr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x97, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uhsubr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uhsubr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uhsubr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uhsubr z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/umaxp.s.yaml b/tests/MC/AArch64/SVE2/umaxp.s.yaml new file mode 100644 index 0000000000..953c364597 --- /dev/null +++ b/tests/MC/AArch64/SVE2/umaxp.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa0, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umaxp z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0xa0, 0x55, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umaxp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0xbf, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umaxp z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umaxp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0xa3, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umaxp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umaxp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0xa0, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umaxp z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0xa0, 0x55, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umaxp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0xbf, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umaxp z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umaxp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0xa3, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umaxp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umaxp z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/uminp.s.yaml b/tests/MC/AArch64/SVE2/uminp.s.yaml new file mode 100644 index 0000000000..2c704e7bba --- /dev/null +++ b/tests/MC/AArch64/SVE2/uminp.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa0, 0x17, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uminp z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0xa0, 0x57, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uminp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0xbf, 0x97, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uminp z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uminp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0xa3, 0xd7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uminp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uminp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0xa0, 0x17, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uminp z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0xa0, 0x57, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uminp z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0xbf, 0x97, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uminp z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uminp z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0xa3, 0xd7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uminp z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0xbf, 0xd7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uminp z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/umlalb.s.yaml b/tests/MC/AArch64/SVE2/umlalb.s.yaml new file mode 100644 index 0000000000..58e31e65de --- /dev/null +++ b/tests/MC/AArch64/SVE2/umlalb.s.yaml @@ -0,0 +1,180 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x48, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlalb z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x48, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlalb z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x48, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlalb z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x98, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlalb z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x98, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlalb z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x48, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlalb z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x99, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlalb z21.d, z10.s, z5.s[1]" + + - + input: + bytes: [ 0x20, 0x48, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlalb z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x48, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlalb z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x48, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlalb z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x98, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlalb z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x98, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlalb z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x48, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlalb z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x99, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlalb z21.d, z10.s, z5.s[1]" diff --git a/tests/MC/AArch64/SVE2/umlalt.s.yaml b/tests/MC/AArch64/SVE2/umlalt.s.yaml new file mode 100644 index 0000000000..453cc1cbc4 --- /dev/null +++ b/tests/MC/AArch64/SVE2/umlalt.s.yaml @@ -0,0 +1,180 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x4c, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlalt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x4c, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlalt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x4c, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlalt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x9c, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlalt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x9c, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlalt z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x4c, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlalt z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x9d, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlalt z21.d, z10.s, z5.s[1]" + + - + input: + bytes: [ 0x20, 0x4c, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlalt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x4c, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlalt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x4c, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlalt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0x9c, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlalt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0x9c, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlalt z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x4c, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlalt z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0x9d, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlalt z21.d, z10.s, z5.s[1]" diff --git a/tests/MC/AArch64/SVE2/umlslb.s.yaml b/tests/MC/AArch64/SVE2/umlslb.s.yaml new file mode 100644 index 0000000000..86ccec243a --- /dev/null +++ b/tests/MC/AArch64/SVE2/umlslb.s.yaml @@ -0,0 +1,180 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x58, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlslb z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x58, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlslb z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x58, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlslb z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xb8, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlslb z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xb8, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlslb z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x58, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlslb z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0xb9, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlslb z21.d, z10.s, z5.s[1]" + + - + input: + bytes: [ 0x20, 0x58, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlslb z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x58, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlslb z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x58, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlslb z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xb8, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlslb z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xb8, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlslb z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x58, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlslb z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0xb9, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlslb z21.d, z10.s, z5.s[1]" diff --git a/tests/MC/AArch64/SVE2/umlslt.s.yaml b/tests/MC/AArch64/SVE2/umlslt.s.yaml new file mode 100644 index 0000000000..010e840b61 --- /dev/null +++ b/tests/MC/AArch64/SVE2/umlslt.s.yaml @@ -0,0 +1,180 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x5c, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlslt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x5c, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlslt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x5c, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlslt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xbc, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlslt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xbc, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlslt z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x5c, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlslt z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0xbd, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umlslt z21.d, z10.s, z5.s[1]" + + - + input: + bytes: [ 0x20, 0x5c, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlslt z0.h, z1.b, z31.b" + + - + input: + bytes: [ 0x20, 0x5c, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlslt z0.s, z1.h, z31.h" + + - + input: + bytes: [ 0x20, 0x5c, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlslt z0.d, z1.s, z31.s" + + - + input: + bytes: [ 0x20, 0xbc, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlslt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xbc, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlslt z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x35, 0x5c, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlslt z21.d, z1.s, z31.s" + + - + input: + bytes: [ 0x95, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z21, z28" + + - + input: + bytes: [ 0x55, 0xbd, 0xe5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umlslt z21.d, z10.s, z5.s[1]" diff --git a/tests/MC/AArch64/SVE2/umulh.s.yaml b/tests/MC/AArch64/SVE2/umulh.s.yaml new file mode 100644 index 0000000000..248e117c31 --- /dev/null +++ b/tests/MC/AArch64/SVE2/umulh.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x6c, 0x22, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umulh z0.b, z1.b, z2.b" + + - + input: + bytes: [ 0x20, 0x6c, 0x62, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umulh z0.h, z1.h, z2.h" + + - + input: + bytes: [ 0xdd, 0x6f, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umulh z29.s, z30.s, z31.s" + + - + input: + bytes: [ 0xff, 0x6f, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umulh z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x20, 0x6c, 0x22, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umulh z0.b, z1.b, z2.b" + + - + input: + bytes: [ 0x20, 0x6c, 0x62, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umulh z0.h, z1.h, z2.h" + + - + input: + bytes: [ 0xdd, 0x6f, 0xbf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umulh z29.s, z30.s, z31.s" + + - + input: + bytes: [ 0xff, 0x6f, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umulh z31.d, z31.d, z31.d" diff --git a/tests/MC/AArch64/SVE2/umullb.s.yaml b/tests/MC/AArch64/SVE2/umullb.s.yaml new file mode 100644 index 0000000000..6470beee60 --- /dev/null +++ b/tests/MC/AArch64/SVE2/umullb.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x78, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umullb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x7b, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umullb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x7b, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umullb z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0xd8, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umullb z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xd8, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umullb z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x20, 0x78, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umullb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x7b, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umullb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x7b, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umullb z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0xd8, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umullb z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xd8, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umullb z0.d, z1.s, z15.s[1]" diff --git a/tests/MC/AArch64/SVE2/umullt.s.yaml b/tests/MC/AArch64/SVE2/umullt.s.yaml new file mode 100644 index 0000000000..749463dc93 --- /dev/null +++ b/tests/MC/AArch64/SVE2/umullt.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x7c, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umullt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x7f, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umullt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x7f, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umullt z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0xdc, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umullt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xdc, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "umullt z0.d, z1.s, z15.s[1]" + + - + input: + bytes: [ 0x20, 0x7c, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umullt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x7f, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umullt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x7f, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umullt z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0xdc, 0xbf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umullt z0.s, z1.h, z7.h[7]" + + - + input: + bytes: [ 0x20, 0xdc, 0xef, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "umullt z0.d, z1.s, z15.s[1]" diff --git a/tests/MC/AArch64/SVE2/uqadd.s.yaml b/tests/MC/AArch64/SVE2/uqadd.s.yaml new file mode 100644 index 0000000000..95df9fd908 --- /dev/null +++ b/tests/MC/AArch64/SVE2/uqadd.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x19, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqadd z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x59, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqadd z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x99, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqadd z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd9, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd9, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqadd z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd9, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x19, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x59, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x99, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd9, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd9, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd9, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqadd z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/uqrshl.s.yaml b/tests/MC/AArch64/SVE2/uqrshl.s.yaml new file mode 100644 index 0000000000..59a37de4aa --- /dev/null +++ b/tests/MC/AArch64/SVE2/uqrshl.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x0b, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshl z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x4b, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshl z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x8b, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshl z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xcb, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xcb, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshl z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xcb, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x0b, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshl z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x4b, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshl z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x8b, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshl z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xcb, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xcb, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshl z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xcb, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshl z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/uqrshlr.s.yaml b/tests/MC/AArch64/SVE2/uqrshlr.s.yaml new file mode 100644 index 0000000000..f8bfcd4538 --- /dev/null +++ b/tests/MC/AArch64/SVE2/uqrshlr.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x0f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshlr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x4f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshlr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x8f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshlr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xcf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshlr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xcf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshlr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xcf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshlr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x0f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshlr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x4f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshlr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x8f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshlr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xcf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshlr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xcf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshlr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xcf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshlr z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/uqrshrnb.s.yaml b/tests/MC/AArch64/SVE2/uqrshrnb.s.yaml new file mode 100644 index 0000000000..4713ceff6c --- /dev/null +++ b/tests/MC/AArch64/SVE2/uqrshrnb.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x38, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshrnb z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x3b, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshrnb z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x38, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshrnb z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x3b, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshrnb z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x38, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshrnb z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x3b, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshrnb z31.s, z31.d, #32" + + - + input: + bytes: [ 0x00, 0x38, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshrnb z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x3b, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshrnb z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x38, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshrnb z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x3b, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshrnb z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x38, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshrnb z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x3b, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshrnb z31.s, z31.d, #32" diff --git a/tests/MC/AArch64/SVE2/uqrshrnt.s.yaml b/tests/MC/AArch64/SVE2/uqrshrnt.s.yaml new file mode 100644 index 0000000000..a853eefad5 --- /dev/null +++ b/tests/MC/AArch64/SVE2/uqrshrnt.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x3c, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshrnt z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x3f, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshrnt z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x3c, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshrnt z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x3f, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshrnt z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x3c, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshrnt z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x3f, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqrshrnt z31.s, z31.d, #32" + + - + input: + bytes: [ 0x00, 0x3c, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshrnt z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x3f, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshrnt z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x3c, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshrnt z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x3f, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshrnt z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x3c, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshrnt z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x3f, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqrshrnt z31.s, z31.d, #32" diff --git a/tests/MC/AArch64/SVE2/uqshl.s.yaml b/tests/MC/AArch64/SVE2/uqshl.s.yaml new file mode 100644 index 0000000000..4c42334280 --- /dev/null +++ b/tests/MC/AArch64/SVE2/uqshl.s.yaml @@ -0,0 +1,400 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x09, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshl z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x49, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshl z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x89, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshl z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc9, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x00, 0x81, 0x07, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshl z0.b, p0/m, z0.b, #0" + + - + input: + bytes: [ 0xff, 0x81, 0x07, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshl z31.b, p0/m, z31.b, #7" + + - + input: + bytes: [ 0x00, 0x82, 0x07, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshl z0.h, p0/m, z0.h, #0" + + - + input: + bytes: [ 0xff, 0x83, 0x07, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshl z31.h, p0/m, z31.h, #15" + + - + input: + bytes: [ 0x00, 0x80, 0x47, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshl z0.s, p0/m, z0.s, #0" + + - + input: + bytes: [ 0xff, 0x83, 0x47, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshl z31.s, p0/m, z31.s, #31" + + - + input: + bytes: [ 0x00, 0x80, 0x87, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshl z0.d, p0/m, z0.d, #0" + + - + input: + bytes: [ 0xff, 0x83, 0xc7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshl z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xc9, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshl z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc9, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xff, 0x83, 0xc7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshl z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0x83, 0xc7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshl z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0x20, 0x80, 0x09, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshl z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x49, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshl z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x89, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshl z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc9, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x00, 0x81, 0x07, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshl z0.b, p0/m, z0.b, #0" + + - + input: + bytes: [ 0xff, 0x81, 0x07, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshl z31.b, p0/m, z31.b, #7" + + - + input: + bytes: [ 0x00, 0x82, 0x07, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshl z0.h, p0/m, z0.h, #0" + + - + input: + bytes: [ 0xff, 0x83, 0x07, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshl z31.h, p0/m, z31.h, #15" + + - + input: + bytes: [ 0x00, 0x80, 0x47, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshl z0.s, p0/m, z0.s, #0" + + - + input: + bytes: [ 0xff, 0x83, 0x47, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshl z31.s, p0/m, z31.s, #31" + + - + input: + bytes: [ 0x00, 0x80, 0x87, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshl z0.d, p0/m, z0.d, #0" + + - + input: + bytes: [ 0xff, 0x83, 0xc7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshl z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xc9, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshl z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc9, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xff, 0x83, 0xc7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshl z31.d, p0/m, z31.d, #63" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xff, 0x83, 0xc7, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshl z31.d, p0/m, z31.d, #63" diff --git a/tests/MC/AArch64/SVE2/uqshlr.s.yaml b/tests/MC/AArch64/SVE2/uqshlr.s.yaml new file mode 100644 index 0000000000..cf4dbcc1cd --- /dev/null +++ b/tests/MC/AArch64/SVE2/uqshlr.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x0d, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshlr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x4d, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshlr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x8d, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshlr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xcd, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshlr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xcd, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshlr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xcd, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshlr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x0d, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshlr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x4d, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshlr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x8d, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshlr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xcd, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshlr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xcd, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshlr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xcd, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshlr z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/uqshrnb.s.yaml b/tests/MC/AArch64/SVE2/uqshrnb.s.yaml new file mode 100644 index 0000000000..1ab560a0de --- /dev/null +++ b/tests/MC/AArch64/SVE2/uqshrnb.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x30, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshrnb z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x33, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshrnb z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x30, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshrnb z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x33, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshrnb z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x30, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshrnb z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x33, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshrnb z31.s, z31.d, #32" + + - + input: + bytes: [ 0x00, 0x30, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshrnb z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x33, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshrnb z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x30, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshrnb z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x33, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshrnb z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x30, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshrnb z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x33, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshrnb z31.s, z31.d, #32" diff --git a/tests/MC/AArch64/SVE2/uqshrnt.s.yaml b/tests/MC/AArch64/SVE2/uqshrnt.s.yaml new file mode 100644 index 0000000000..99cc10407c --- /dev/null +++ b/tests/MC/AArch64/SVE2/uqshrnt.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x34, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshrnt z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x37, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshrnt z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x34, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshrnt z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x37, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshrnt z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x34, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshrnt z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x37, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqshrnt z31.s, z31.d, #32" + + - + input: + bytes: [ 0x00, 0x34, 0x2f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshrnt z0.b, z0.h, #1" + + - + input: + bytes: [ 0xff, 0x37, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshrnt z31.b, z31.h, #8" + + - + input: + bytes: [ 0x00, 0x34, 0x3f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshrnt z0.h, z0.s, #1" + + - + input: + bytes: [ 0xff, 0x37, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshrnt z31.h, z31.s, #16" + + - + input: + bytes: [ 0x00, 0x34, 0x7f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshrnt z0.s, z0.d, #1" + + - + input: + bytes: [ 0xff, 0x37, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqshrnt z31.s, z31.d, #32" diff --git a/tests/MC/AArch64/SVE2/uqsub.s.yaml b/tests/MC/AArch64/SVE2/uqsub.s.yaml new file mode 100644 index 0000000000..a67b2a9148 --- /dev/null +++ b/tests/MC/AArch64/SVE2/uqsub.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x1b, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqsub z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x5b, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqsub z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x9b, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqsub z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xdb, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqsub z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xdb, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqsub z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xdb, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqsub z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x1b, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x5b, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x9b, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xdb, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xdb, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xdb, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsub z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/uqsubr.s.yaml b/tests/MC/AArch64/SVE2/uqsubr.s.yaml new file mode 100644 index 0000000000..935cfe337e --- /dev/null +++ b/tests/MC/AArch64/SVE2/uqsubr.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqsubr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqsubr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqsubr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqsubr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqsubr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqsubr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsubr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsubr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsubr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsubr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsubr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqsubr z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/uqxtnb.s.yaml b/tests/MC/AArch64/SVE2/uqxtnb.s.yaml new file mode 100644 index 0000000000..b61bf05cd5 --- /dev/null +++ b/tests/MC/AArch64/SVE2/uqxtnb.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x4b, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqxtnb z0.b, z31.h" + + - + input: + bytes: [ 0xe0, 0x4b, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqxtnb z0.h, z31.s" + + - + input: + bytes: [ 0xe0, 0x4b, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqxtnb z0.s, z31.d" + + - + input: + bytes: [ 0xe0, 0x4b, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqxtnb z0.b, z31.h" + + - + input: + bytes: [ 0xe0, 0x4b, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqxtnb z0.h, z31.s" + + - + input: + bytes: [ 0xe0, 0x4b, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqxtnb z0.s, z31.d" diff --git a/tests/MC/AArch64/SVE2/uqxtnt.s.yaml b/tests/MC/AArch64/SVE2/uqxtnt.s.yaml new file mode 100644 index 0000000000..ca90f6600b --- /dev/null +++ b/tests/MC/AArch64/SVE2/uqxtnt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x4f, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqxtnt z0.b, z31.h" + + - + input: + bytes: [ 0xe0, 0x4f, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqxtnt z0.h, z31.s" + + - + input: + bytes: [ 0xe0, 0x4f, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "uqxtnt z0.s, z31.d" + + - + input: + bytes: [ 0xe0, 0x4f, 0x28, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqxtnt z0.b, z31.h" + + - + input: + bytes: [ 0xe0, 0x4f, 0x30, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqxtnt z0.h, z31.s" + + - + input: + bytes: [ 0xe0, 0x4f, 0x60, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "uqxtnt z0.s, z31.d" diff --git a/tests/MC/AArch64/SVE2/urecpe.s.yaml b/tests/MC/AArch64/SVE2/urecpe.s.yaml new file mode 100644 index 0000000000..e56c1a1099 --- /dev/null +++ b/tests/MC/AArch64/SVE2/urecpe.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urecpe z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xc4, 0x3c, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z4.s, p7/z, z6.s" + + - + input: + bytes: [ 0xe4, 0xbf, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urecpe z4.s, p7/m, z31.s" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urecpe z4.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urecpe z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xc4, 0x3c, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.s, p7/z, z6.s" + + - + input: + bytes: [ 0xe4, 0xbf, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urecpe z4.s, p7/m, z31.s" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urecpe z4.s, p7/m, z31.s" diff --git a/tests/MC/AArch64/SVE2/urhadd.s.yaml b/tests/MC/AArch64/SVE2/urhadd.s.yaml new file mode 100644 index 0000000000..7b5a9a7138 --- /dev/null +++ b/tests/MC/AArch64/SVE2/urhadd.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urhadd z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x55, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urhadd z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urhadd z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urhadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urhadd z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urhadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urhadd z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x55, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urhadd z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urhadd z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urhadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urhadd z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urhadd z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/urshl.s.yaml b/tests/MC/AArch64/SVE2/urshl.s.yaml new file mode 100644 index 0000000000..7a3b665660 --- /dev/null +++ b/tests/MC/AArch64/SVE2/urshl.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x03, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshl z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x43, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshl z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x83, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshl z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc3, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xc3, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshl z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc3, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x03, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshl z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x43, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshl z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x83, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshl z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc3, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshl z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xc3, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshl z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc3, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshl z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/urshlr.s.yaml b/tests/MC/AArch64/SVE2/urshlr.s.yaml new file mode 100644 index 0000000000..2c15e4e2f0 --- /dev/null +++ b/tests/MC/AArch64/SVE2/urshlr.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x07, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshlr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x47, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshlr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x87, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshlr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshlr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xc7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshlr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshlr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x07, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshlr z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x47, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshlr z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x87, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshlr z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshlr z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xc7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshlr z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xc7, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshlr z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/urshr.s.yaml b/tests/MC/AArch64/SVE2/urshr.s.yaml new file mode 100644 index 0000000000..4a388c635f --- /dev/null +++ b/tests/MC/AArch64/SVE2/urshr.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x81, 0x0d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshr z0.b, p0/m, z0.b, #1" + + - + input: + bytes: [ 0x1f, 0x81, 0x0d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshr z31.b, p0/m, z31.b, #8" + + - + input: + bytes: [ 0xe0, 0x83, 0x0d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshr z0.h, p0/m, z0.h, #1" + + - + input: + bytes: [ 0x1f, 0x82, 0x0d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshr z31.h, p0/m, z31.h, #16" + + - + input: + bytes: [ 0xe0, 0x83, 0x4d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshr z0.s, p0/m, z0.s, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x4d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshr z31.s, p0/m, z31.s, #32" + + - + input: + bytes: [ 0xe0, 0x83, 0xcd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshr z0.d, p0/m, z0.d, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x8d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0x1f, 0x80, 0x8d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x1f, 0x80, 0x8d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "urshr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xe0, 0x81, 0x0d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshr z0.b, p0/m, z0.b, #1" + + - + input: + bytes: [ 0x1f, 0x81, 0x0d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshr z31.b, p0/m, z31.b, #8" + + - + input: + bytes: [ 0xe0, 0x83, 0x0d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshr z0.h, p0/m, z0.h, #1" + + - + input: + bytes: [ 0x1f, 0x82, 0x0d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshr z31.h, p0/m, z31.h, #16" + + - + input: + bytes: [ 0xe0, 0x83, 0x4d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshr z0.s, p0/m, z0.s, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x4d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshr z31.s, p0/m, z31.s, #32" + + - + input: + bytes: [ 0xe0, 0x83, 0xcd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshr z0.d, p0/m, z0.d, #1" + + - + input: + bytes: [ 0x1f, 0x80, 0x8d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0x1f, 0x80, 0x8d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshr z31.d, p0/m, z31.d, #64" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0x1f, 0x80, 0x8d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "urshr z31.d, p0/m, z31.d, #64" diff --git a/tests/MC/AArch64/SVE2/ursqrte.s.yaml b/tests/MC/AArch64/SVE2/ursqrte.s.yaml new file mode 100644 index 0000000000..b19b4a6ee1 --- /dev/null +++ b/tests/MC/AArch64/SVE2/ursqrte.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xbf, 0x81, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ursqrte z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xc4, 0x3c, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z4.s, p7/z, z6.s" + + - + input: + bytes: [ 0xe4, 0xbf, 0x81, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ursqrte z4.s, p7/m, z31.s" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0x81, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ursqrte z4.s, p7/m, z31.s" + + - + input: + bytes: [ 0xff, 0xbf, 0x81, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ursqrte z31.s, p7/m, z31.s" + + - + input: + bytes: [ 0xc4, 0x3c, 0x90, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4.s, p7/z, z6.s" + + - + input: + bytes: [ 0xe4, 0xbf, 0x81, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ursqrte z4.s, p7/m, z31.s" + + - + input: + bytes: [ 0xc4, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z4, z6" + + - + input: + bytes: [ 0xe4, 0xbf, 0x81, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ursqrte z4.s, p7/m, z31.s" diff --git a/tests/MC/AArch64/SVE2/ursra.s.yaml b/tests/MC/AArch64/SVE2/ursra.s.yaml new file mode 100644 index 0000000000..7d87597b51 --- /dev/null +++ b/tests/MC/AArch64/SVE2/ursra.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xec, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ursra z0.b, z0.b, #1" + + - + input: + bytes: [ 0xff, 0xef, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ursra z31.b, z31.b, #8" + + - + input: + bytes: [ 0x00, 0xec, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ursra z0.h, z0.h, #1" + + - + input: + bytes: [ 0xff, 0xef, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ursra z31.h, z31.h, #16" + + - + input: + bytes: [ 0x00, 0xec, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ursra z0.s, z0.s, #1" + + - + input: + bytes: [ 0xff, 0xef, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ursra z31.s, z31.s, #32" + + - + input: + bytes: [ 0x00, 0xec, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ursra z0.d, z0.d, #1" + + - + input: + bytes: [ 0xff, 0xef, 0x80, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ursra z31.d, z31.d, #64" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xec, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ursra z0.d, z1.d, #1" + + - + input: + bytes: [ 0x00, 0xec, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ursra z0.b, z0.b, #1" + + - + input: + bytes: [ 0xff, 0xef, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ursra z31.b, z31.b, #8" + + - + input: + bytes: [ 0x00, 0xec, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ursra z0.h, z0.h, #1" + + - + input: + bytes: [ 0xff, 0xef, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ursra z31.h, z31.h, #16" + + - + input: + bytes: [ 0x00, 0xec, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ursra z0.s, z0.s, #1" + + - + input: + bytes: [ 0xff, 0xef, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ursra z31.s, z31.s, #32" + + - + input: + bytes: [ 0x00, 0xec, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ursra z0.d, z0.d, #1" + + - + input: + bytes: [ 0xff, 0xef, 0x80, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ursra z31.d, z31.d, #64" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xec, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ursra z0.d, z1.d, #1" diff --git a/tests/MC/AArch64/SVE2/ushllb.s.yaml b/tests/MC/AArch64/SVE2/ushllb.s.yaml new file mode 100644 index 0000000000..b9f0a45fe1 --- /dev/null +++ b/tests/MC/AArch64/SVE2/ushllb.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa8, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ushllb z0.h, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xab, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ushllb z31.h, z31.b, #7" + + - + input: + bytes: [ 0x00, 0xa8, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ushllb z0.s, z0.h, #0" + + - + input: + bytes: [ 0xff, 0xab, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ushllb z31.s, z31.h, #15" + + - + input: + bytes: [ 0x00, 0xa8, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ushllb z0.d, z0.s, #0" + + - + input: + bytes: [ 0xff, 0xab, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ushllb z31.d, z31.s, #31" + + - + input: + bytes: [ 0x00, 0xa8, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ushllb z0.h, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xab, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ushllb z31.h, z31.b, #7" + + - + input: + bytes: [ 0x00, 0xa8, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ushllb z0.s, z0.h, #0" + + - + input: + bytes: [ 0xff, 0xab, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ushllb z31.s, z31.h, #15" + + - + input: + bytes: [ 0x00, 0xa8, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ushllb z0.d, z0.s, #0" + + - + input: + bytes: [ 0xff, 0xab, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ushllb z31.d, z31.s, #31" diff --git a/tests/MC/AArch64/SVE2/ushllt.s.yaml b/tests/MC/AArch64/SVE2/ushllt.s.yaml new file mode 100644 index 0000000000..f65e6891d3 --- /dev/null +++ b/tests/MC/AArch64/SVE2/ushllt.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xac, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ushllt z0.h, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xaf, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ushllt z31.h, z31.b, #7" + + - + input: + bytes: [ 0x00, 0xac, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ushllt z0.s, z0.h, #0" + + - + input: + bytes: [ 0xff, 0xaf, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ushllt z31.s, z31.h, #15" + + - + input: + bytes: [ 0x00, 0xac, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ushllt z0.d, z0.s, #0" + + - + input: + bytes: [ 0xff, 0xaf, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "ushllt z31.d, z31.s, #31" + + - + input: + bytes: [ 0x00, 0xac, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ushllt z0.h, z0.b, #0" + + - + input: + bytes: [ 0xff, 0xaf, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ushllt z31.h, z31.b, #7" + + - + input: + bytes: [ 0x00, 0xac, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ushllt z0.s, z0.h, #0" + + - + input: + bytes: [ 0xff, 0xaf, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ushllt z31.s, z31.h, #15" + + - + input: + bytes: [ 0x00, 0xac, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ushllt z0.d, z0.s, #0" + + - + input: + bytes: [ 0xff, 0xaf, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "ushllt z31.d, z31.s, #31" diff --git a/tests/MC/AArch64/SVE2/usqadd.s.yaml b/tests/MC/AArch64/SVE2/usqadd.s.yaml new file mode 100644 index 0000000000..8802d241b2 --- /dev/null +++ b/tests/MC/AArch64/SVE2/usqadd.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x80, 0x1d, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usqadd z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x5d, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usqadd z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x9d, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usqadd z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xdd, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usqadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xdd, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usqadd z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xdd, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usqadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0x20, 0x80, 0x1d, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usqadd z0.b, p0/m, z0.b, z1.b" + + - + input: + bytes: [ 0x20, 0x80, 0x5d, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usqadd z0.h, p0/m, z0.h, z1.h" + + - + input: + bytes: [ 0xdd, 0x9f, 0x9d, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usqadd z29.s, p7/m, z29.s, z30.s" + + - + input: + bytes: [ 0xdf, 0x9f, 0xdd, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usqadd z31.d, p7/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0x20, 0xd0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31.d, p0/z, z6.d" + + - + input: + bytes: [ 0xdf, 0x83, 0xdd, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usqadd z31.d, p0/m, z31.d, z30.d" + + - + input: + bytes: [ 0xdf, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z6" + + - + input: + bytes: [ 0xdf, 0x9f, 0xdd, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usqadd z31.d, p7/m, z31.d, z30.d" diff --git a/tests/MC/AArch64/SVE2/usra.s.yaml b/tests/MC/AArch64/SVE2/usra.s.yaml new file mode 100644 index 0000000000..8eb1a28a20 --- /dev/null +++ b/tests/MC/AArch64/SVE2/usra.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe4, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usra z0.b, z0.b, #1" + + - + input: + bytes: [ 0xff, 0xe7, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usra z31.b, z31.b, #8" + + - + input: + bytes: [ 0x00, 0xe4, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usra z0.h, z0.h, #1" + + - + input: + bytes: [ 0xff, 0xe7, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usra z31.h, z31.h, #16" + + - + input: + bytes: [ 0x00, 0xe4, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usra z0.s, z0.s, #1" + + - + input: + bytes: [ 0xff, 0xe7, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usra z31.s, z31.s, #32" + + - + input: + bytes: [ 0x00, 0xe4, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usra z0.d, z0.d, #1" + + - + input: + bytes: [ 0xff, 0xe7, 0x80, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usra z31.d, z31.d, #64" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xe4, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usra z0.d, z1.d, #1" + + - + input: + bytes: [ 0x00, 0xe4, 0x0f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usra z0.b, z0.b, #1" + + - + input: + bytes: [ 0xff, 0xe7, 0x08, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usra z31.b, z31.b, #8" + + - + input: + bytes: [ 0x00, 0xe4, 0x1f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usra z0.h, z0.h, #1" + + - + input: + bytes: [ 0xff, 0xe7, 0x10, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usra z31.h, z31.h, #16" + + - + input: + bytes: [ 0x00, 0xe4, 0x5f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usra z0.s, z0.s, #1" + + - + input: + bytes: [ 0xff, 0xe7, 0x40, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usra z31.s, z31.s, #32" + + - + input: + bytes: [ 0x00, 0xe4, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usra z0.d, z0.d, #1" + + - + input: + bytes: [ 0xff, 0xe7, 0x80, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usra z31.d, z31.d, #64" + + - + input: + bytes: [ 0xe0, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z0, z7" + + - + input: + bytes: [ 0x20, 0xe4, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usra z0.d, z1.d, #1" diff --git a/tests/MC/AArch64/SVE2/usublb.s.yaml b/tests/MC/AArch64/SVE2/usublb.s.yaml new file mode 100644 index 0000000000..5aea13583e --- /dev/null +++ b/tests/MC/AArch64/SVE2/usublb.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x18, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usublb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x1b, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usublb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1b, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usublb z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0x18, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usublb z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x1b, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usublb z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1b, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usublb z31.d, z31.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/usublt.s.yaml b/tests/MC/AArch64/SVE2/usublt.s.yaml new file mode 100644 index 0000000000..258a2e52f5 --- /dev/null +++ b/tests/MC/AArch64/SVE2/usublt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x1c, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usublt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x1f, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usublt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usublt z31.d, z31.s, z31.s" + + - + input: + bytes: [ 0x20, 0x1c, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usublt z0.h, z1.b, z2.b" + + - + input: + bytes: [ 0xdd, 0x1f, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usublt z29.s, z30.h, z31.h" + + - + input: + bytes: [ 0xff, 0x1f, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usublt z31.d, z31.s, z31.s" diff --git a/tests/MC/AArch64/SVE2/usubwb.s.yaml b/tests/MC/AArch64/SVE2/usubwb.s.yaml new file mode 100644 index 0000000000..6011daa98e --- /dev/null +++ b/tests/MC/AArch64/SVE2/usubwb.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x58, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usubwb z0.h, z1.h, z2.b" + + - + input: + bytes: [ 0xdd, 0x5b, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usubwb z29.s, z30.s, z31.h" + + - + input: + bytes: [ 0xff, 0x5b, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usubwb z31.d, z31.d, z31.s" + + - + input: + bytes: [ 0x20, 0x58, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usubwb z0.h, z1.h, z2.b" + + - + input: + bytes: [ 0xdd, 0x5b, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usubwb z29.s, z30.s, z31.h" + + - + input: + bytes: [ 0xff, 0x5b, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usubwb z31.d, z31.d, z31.s" diff --git a/tests/MC/AArch64/SVE2/usubwt.s.yaml b/tests/MC/AArch64/SVE2/usubwt.s.yaml new file mode 100644 index 0000000000..02acb83a4f --- /dev/null +++ b/tests/MC/AArch64/SVE2/usubwt.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x5c, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usubwt z0.h, z1.h, z2.b" + + - + input: + bytes: [ 0xdd, 0x5f, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usubwt z29.s, z30.s, z31.h" + + - + input: + bytes: [ 0xff, 0x5f, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "usubwt z31.d, z31.d, z31.s" + + - + input: + bytes: [ 0x20, 0x5c, 0x42, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usubwt z0.h, z1.h, z2.b" + + - + input: + bytes: [ 0xdd, 0x5f, 0x9f, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usubwt z29.s, z30.s, z31.h" + + - + input: + bytes: [ 0xff, 0x5f, 0xdf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "usubwt z31.d, z31.d, z31.s" diff --git a/tests/MC/AArch64/SVE2/whilege.s.yaml b/tests/MC/AArch64/SVE2/whilege.s.yaml new file mode 100644 index 0000000000..6383a5eaea --- /dev/null +++ b/tests/MC/AArch64/SVE2/whilege.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0xef, 0x13, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilege p15.b, xzr, x0" + + - + input: + bytes: [ 0x0f, 0x10, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilege p15.b, x0, xzr" + + - + input: + bytes: [ 0xef, 0x03, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilege p15.b, wzr, w0" + + - + input: + bytes: [ 0x0f, 0x00, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilege p15.b, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x10, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilege p15.h, x0, xzr" + + - + input: + bytes: [ 0x0f, 0x00, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilege p15.h, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x10, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilege p15.s, x0, xzr" + + - + input: + bytes: [ 0x0f, 0x00, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilege p15.s, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x00, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilege p15.d, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x10, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilege p15.d, x0, xzr" + + - + input: + bytes: [ 0xef, 0x13, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilege p15.b, xzr, x0" + + - + input: + bytes: [ 0x0f, 0x10, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilege p15.b, x0, xzr" + + - + input: + bytes: [ 0xef, 0x03, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilege p15.b, wzr, w0" + + - + input: + bytes: [ 0x0f, 0x00, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilege p15.b, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x10, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilege p15.h, x0, xzr" + + - + input: + bytes: [ 0x0f, 0x00, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilege p15.h, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x10, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilege p15.s, x0, xzr" + + - + input: + bytes: [ 0x0f, 0x00, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilege p15.s, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x00, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilege p15.d, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x10, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilege p15.d, x0, xzr" diff --git a/tests/MC/AArch64/SVE2/whilegt.s.yaml b/tests/MC/AArch64/SVE2/whilegt.s.yaml new file mode 100644 index 0000000000..109691a1da --- /dev/null +++ b/tests/MC/AArch64/SVE2/whilegt.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x13, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilegt p15.b, xzr, x0" + + - + input: + bytes: [ 0x1f, 0x10, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilegt p15.b, x0, xzr" + + - + input: + bytes: [ 0xff, 0x03, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilegt p15.b, wzr, w0" + + - + input: + bytes: [ 0x1f, 0x00, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilegt p15.b, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x10, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilegt p15.h, x0, xzr" + + - + input: + bytes: [ 0x1f, 0x00, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilegt p15.h, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x10, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilegt p15.s, x0, xzr" + + - + input: + bytes: [ 0x1f, 0x00, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilegt p15.s, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x00, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilegt p15.d, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x10, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilegt p15.d, x0, xzr" + + - + input: + bytes: [ 0xff, 0x13, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilegt p15.b, xzr, x0" + + - + input: + bytes: [ 0x1f, 0x10, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilegt p15.b, x0, xzr" + + - + input: + bytes: [ 0xff, 0x03, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilegt p15.b, wzr, w0" + + - + input: + bytes: [ 0x1f, 0x00, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilegt p15.b, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x10, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilegt p15.h, x0, xzr" + + - + input: + bytes: [ 0x1f, 0x00, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilegt p15.h, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x10, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilegt p15.s, x0, xzr" + + - + input: + bytes: [ 0x1f, 0x00, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilegt p15.s, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x00, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilegt p15.d, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x10, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilegt p15.d, x0, xzr" diff --git a/tests/MC/AArch64/SVE2/whilehi.s.yaml b/tests/MC/AArch64/SVE2/whilehi.s.yaml new file mode 100644 index 0000000000..ede403181d --- /dev/null +++ b/tests/MC/AArch64/SVE2/whilehi.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x1b, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehi p15.b, xzr, x0" + + - + input: + bytes: [ 0x1f, 0x18, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehi p15.b, x0, xzr" + + - + input: + bytes: [ 0xff, 0x0b, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehi p15.b, wzr, w0" + + - + input: + bytes: [ 0x1f, 0x08, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehi p15.b, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x18, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehi p15.h, x0, xzr" + + - + input: + bytes: [ 0x1f, 0x08, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehi p15.h, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x18, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehi p15.s, x0, xzr" + + - + input: + bytes: [ 0x1f, 0x08, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehi p15.s, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x08, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehi p15.d, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x18, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehi p15.d, x0, xzr" + + - + input: + bytes: [ 0xff, 0x1b, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehi p15.b, xzr, x0" + + - + input: + bytes: [ 0x1f, 0x18, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehi p15.b, x0, xzr" + + - + input: + bytes: [ 0xff, 0x0b, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehi p15.b, wzr, w0" + + - + input: + bytes: [ 0x1f, 0x08, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehi p15.b, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x18, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehi p15.h, x0, xzr" + + - + input: + bytes: [ 0x1f, 0x08, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehi p15.h, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x18, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehi p15.s, x0, xzr" + + - + input: + bytes: [ 0x1f, 0x08, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehi p15.s, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x08, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehi p15.d, w0, wzr" + + - + input: + bytes: [ 0x1f, 0x18, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehi p15.d, x0, xzr" diff --git a/tests/MC/AArch64/SVE2/whilehs.s.yaml b/tests/MC/AArch64/SVE2/whilehs.s.yaml new file mode 100644 index 0000000000..f7761a1ad2 --- /dev/null +++ b/tests/MC/AArch64/SVE2/whilehs.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0xef, 0x1b, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehs p15.b, xzr, x0" + + - + input: + bytes: [ 0x0f, 0x18, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehs p15.b, x0, xzr" + + - + input: + bytes: [ 0xef, 0x0b, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehs p15.b, wzr, w0" + + - + input: + bytes: [ 0x0f, 0x08, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehs p15.b, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x18, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehs p15.h, x0, xzr" + + - + input: + bytes: [ 0x0f, 0x08, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehs p15.h, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x18, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehs p15.s, x0, xzr" + + - + input: + bytes: [ 0x0f, 0x08, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehs p15.s, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x08, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehs p15.d, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x18, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilehs p15.d, x0, xzr" + + - + input: + bytes: [ 0xef, 0x1b, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehs p15.b, xzr, x0" + + - + input: + bytes: [ 0x0f, 0x18, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehs p15.b, x0, xzr" + + - + input: + bytes: [ 0xef, 0x0b, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehs p15.b, wzr, w0" + + - + input: + bytes: [ 0x0f, 0x08, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehs p15.b, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x18, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehs p15.h, x0, xzr" + + - + input: + bytes: [ 0x0f, 0x08, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehs p15.h, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x18, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehs p15.s, x0, xzr" + + - + input: + bytes: [ 0x0f, 0x08, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehs p15.s, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x08, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehs p15.d, w0, wzr" + + - + input: + bytes: [ 0x0f, 0x18, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilehs p15.d, x0, xzr" diff --git a/tests/MC/AArch64/SVE2/whilerw.s.yaml b/tests/MC/AArch64/SVE2/whilerw.s.yaml new file mode 100644 index 0000000000..cbd90e31d3 --- /dev/null +++ b/tests/MC/AArch64/SVE2/whilerw.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xdf, 0x33, 0x3e, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilerw p15.b, x30, x30" + + - + input: + bytes: [ 0xdf, 0x33, 0x7e, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilerw p15.h, x30, x30" + + - + input: + bytes: [ 0xdf, 0x33, 0xbe, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilerw p15.s, x30, x30" + + - + input: + bytes: [ 0xdf, 0x33, 0xfe, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilerw p15.d, x30, x30" + + - + input: + bytes: [ 0xdf, 0x33, 0x3e, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilerw p15.b, x30, x30" + + - + input: + bytes: [ 0xdf, 0x33, 0x7e, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilerw p15.h, x30, x30" + + - + input: + bytes: [ 0xdf, 0x33, 0xbe, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilerw p15.s, x30, x30" + + - + input: + bytes: [ 0xdf, 0x33, 0xfe, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilerw p15.d, x30, x30" diff --git a/tests/MC/AArch64/SVE2/whilewr.s.yaml b/tests/MC/AArch64/SVE2/whilewr.s.yaml new file mode 100644 index 0000000000..79d6809baa --- /dev/null +++ b/tests/MC/AArch64/SVE2/whilewr.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xcf, 0x33, 0x3e, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilewr p15.b, x30, x30" + + - + input: + bytes: [ 0xcf, 0x33, 0x7e, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilewr p15.h, x30, x30" + + - + input: + bytes: [ 0xcf, 0x33, 0xbe, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilewr p15.s, x30, x30" + + - + input: + bytes: [ 0xcf, 0x33, 0xfe, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "whilewr p15.d, x30, x30" + + - + input: + bytes: [ 0xcf, 0x33, 0x3e, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilewr p15.b, x30, x30" + + - + input: + bytes: [ 0xcf, 0x33, 0x7e, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilewr p15.h, x30, x30" + + - + input: + bytes: [ 0xcf, 0x33, 0xbe, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilewr p15.s, x30, x30" + + - + input: + bytes: [ 0xcf, 0x33, 0xfe, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "whilewr p15.d, x30, x30" diff --git a/tests/MC/AArch64/SVE2/xar.s.yaml b/tests/MC/AArch64/SVE2/xar.s.yaml new file mode 100644 index 0000000000..d47563eb1b --- /dev/null +++ b/tests/MC/AArch64/SVE2/xar.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x34, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "xar z0.b, z0.b, z1.b, #1" + + - + input: + bytes: [ 0xdf, 0x37, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "xar z31.b, z31.b, z30.b, #8" + + - + input: + bytes: [ 0x20, 0x34, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "xar z0.h, z0.h, z1.h, #1" + + - + input: + bytes: [ 0xdf, 0x37, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "xar z31.h, z31.h, z30.h, #16" + + - + input: + bytes: [ 0x20, 0x34, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "xar z0.s, z0.s, z1.s, #1" + + - + input: + bytes: [ 0xdf, 0x37, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "xar z31.s, z31.s, z30.s, #32" + + - + input: + bytes: [ 0x20, 0x34, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "xar z0.d, z0.d, z1.d, #1" + + - + input: + bytes: [ 0xdf, 0x37, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "xar z31.d, z31.d, z30.d, #64" + + - + input: + bytes: [ 0xff, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "movprfx z31, z7" + + - + input: + bytes: [ 0xdf, 0x37, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ] + expected: + insns: + - + asm_text: "xar z31.d, z31.d, z30.d, #64" + + - + input: + bytes: [ 0x20, 0x34, 0x2f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "xar z0.b, z0.b, z1.b, #1" + + - + input: + bytes: [ 0xdf, 0x37, 0x28, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "xar z31.b, z31.b, z30.b, #8" + + - + input: + bytes: [ 0x20, 0x34, 0x3f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "xar z0.h, z0.h, z1.h, #1" + + - + input: + bytes: [ 0xdf, 0x37, 0x30, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "xar z31.h, z31.h, z30.h, #16" + + - + input: + bytes: [ 0x20, 0x34, 0x7f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "xar z0.s, z0.s, z1.s, #1" + + - + input: + bytes: [ 0xdf, 0x37, 0x60, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "xar z31.s, z31.s, z30.s, #32" + + - + input: + bytes: [ 0x20, 0x34, 0xff, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "xar z0.d, z0.d, z1.d, #1" + + - + input: + bytes: [ 0xdf, 0x37, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "xar z31.d, z31.d, z30.d, #64" + + - + input: + bytes: [ 0xff, 0xbc, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "movprfx z31, z7" + + - + input: + bytes: [ 0xdf, 0x37, 0xa0, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ] + expected: + insns: + - + asm_text: "xar z31.d, z31.d, z30.d, #64" diff --git a/tests/MC/AArch64/SVE2p1/addqv.s.yaml b/tests/MC/AArch64/SVE2p1/addqv.s.yaml new file mode 100644 index 0000000000..a9b6a69408 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/addqv.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x45, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "addqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0x35, 0x45, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "addqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0x2d, 0x45, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "addqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0x3f, 0x45, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "addqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0x20, 0x85, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "addqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0x35, 0x85, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "addqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0x2d, 0x85, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "addqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0x3f, 0x85, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "addqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0x20, 0xc5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "addqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0x35, 0xc5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "addqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0x2d, 0xc5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "addqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0x3f, 0xc5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "addqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0x20, 0x05, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "addqv v0.16b, p0, z0.b" + + - + input: + bytes: [ 0x55, 0x35, 0x05, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "addqv v21.16b, p5, z10.b" + + - + input: + bytes: [ 0xb7, 0x2d, 0x05, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "addqv v23.16b, p3, z13.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x05, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "addqv v31.16b, p7, z31.b" + + - + input: + bytes: [ 0x00, 0x20, 0x45, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "addqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0x35, 0x45, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "addqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0x2d, 0x45, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "addqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0x3f, 0x45, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "addqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0x20, 0x85, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "addqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0x35, 0x85, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "addqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0x2d, 0x85, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "addqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0x3f, 0x85, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "addqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0x20, 0xc5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "addqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0x35, 0xc5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "addqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0x2d, 0xc5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "addqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0x3f, 0xc5, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "addqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0x20, 0x05, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "addqv v0.16b, p0, z0.b" + + - + input: + bytes: [ 0x55, 0x35, 0x05, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "addqv v21.16b, p5, z10.b" + + - + input: + bytes: [ 0xb7, 0x2d, 0x05, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "addqv v23.16b, p3, z13.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x05, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "addqv v31.16b, p7, z31.b" diff --git a/tests/MC/AArch64/SVE2p1/andqv.s.yaml b/tests/MC/AArch64/SVE2p1/andqv.s.yaml new file mode 100644 index 0000000000..c8f6237416 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/andqv.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x5e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "andqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0x35, 0x5e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "andqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0x2d, 0x5e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "andqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0x3f, 0x5e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "andqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0x20, 0x9e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "andqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0x35, 0x9e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "andqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0x2d, 0x9e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "andqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0x3f, 0x9e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "andqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0x20, 0xde, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "andqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0x35, 0xde, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "andqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0x2d, 0xde, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "andqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0x3f, 0xde, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "andqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0x20, 0x1e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "andqv v0.16b, p0, z0.b" + + - + input: + bytes: [ 0x55, 0x35, 0x1e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "andqv v21.16b, p5, z10.b" + + - + input: + bytes: [ 0xb7, 0x2d, 0x1e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "andqv v23.16b, p3, z13.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x1e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "andqv v31.16b, p7, z31.b" + + - + input: + bytes: [ 0x00, 0x20, 0x5e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "andqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0x35, 0x5e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "andqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0x2d, 0x5e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "andqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0x3f, 0x5e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "andqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0x20, 0x9e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "andqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0x35, 0x9e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "andqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0x2d, 0x9e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "andqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0x3f, 0x9e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "andqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0x20, 0xde, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "andqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0x35, 0xde, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "andqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0x2d, 0xde, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "andqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0x3f, 0xde, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "andqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0x20, 0x1e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "andqv v0.16b, p0, z0.b" + + - + input: + bytes: [ 0x55, 0x35, 0x1e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "andqv v21.16b, p5, z10.b" + + - + input: + bytes: [ 0xb7, 0x2d, 0x1e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "andqv v23.16b, p3, z13.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x1e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "andqv v31.16b, p7, z31.b" diff --git a/tests/MC/AArch64/SVE2p1/bfadd.s.yaml b/tests/MC/AArch64/SVE2p1/bfadd.s.yaml new file mode 100644 index 0000000000..3c58752746 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/bfadd.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0xf7, 0x2f, 0x51, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23.h, p3/m, z31.h" + + - + input: + bytes: [ 0xb7, 0x8d, 0x00, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x8d, 0x00, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0x00, 0x80, 0x00, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x95, 0x00, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd z21.h, p5/m, z21.h, z10.h" + + - + input: + bytes: [ 0xb7, 0x8d, 0x00, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xff, 0x9f, 0x00, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x01, 0x15, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0x01, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0x03, 0x1f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfadd z31.h, z31.h, z31.h" diff --git a/tests/MC/AArch64/SVE2p1/bfclamp.s.yaml b/tests/MC/AArch64/SVE2p1/bfclamp.s.yaml new file mode 100644 index 0000000000..8497365cd7 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/bfclamp.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x25, 0x28, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfclamp z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0x00, 0x24, 0x20, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfclamp z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x25, 0x35, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfclamp z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0x25, 0x28, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfclamp z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0x27, 0x3f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfclamp z31.h, z31.h, z31.h" diff --git a/tests/MC/AArch64/SVE2p1/bfmax.s.yaml b/tests/MC/AArch64/SVE2p1/bfmax.s.yaml new file mode 100644 index 0000000000..5f82cbae1f --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/bfmax.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xf7, 0x2f, 0x51, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23.h, p3/m, z31.h" + + - + input: + bytes: [ 0xb7, 0x8d, 0x06, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x8d, 0x06, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0x00, 0x80, 0x06, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x95, 0x06, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax z21.h, p5/m, z21.h, z10.h" + + - + input: + bytes: [ 0xb7, 0x8d, 0x06, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xff, 0x9f, 0x06, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmax z31.h, p7/m, z31.h, z31.h" diff --git a/tests/MC/AArch64/SVE2p1/bfmaxnm.s.yaml b/tests/MC/AArch64/SVE2p1/bfmaxnm.s.yaml new file mode 100644 index 0000000000..45aac3fce1 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/bfmaxnm.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xf7, 0x2f, 0x51, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23.h, p3/m, z31.h" + + - + input: + bytes: [ 0xb7, 0x8d, 0x04, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x8d, 0x04, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0x00, 0x80, 0x04, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x95, 0x04, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm z21.h, p5/m, z21.h, z10.h" + + - + input: + bytes: [ 0xb7, 0x8d, 0x04, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xff, 0x9f, 0x04, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmaxnm z31.h, p7/m, z31.h, z31.h" diff --git a/tests/MC/AArch64/SVE2p1/bfmin.s.yaml b/tests/MC/AArch64/SVE2p1/bfmin.s.yaml new file mode 100644 index 0000000000..86b6b7b887 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/bfmin.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xf7, 0x2f, 0x51, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23.h, p3/m, z31.h" + + - + input: + bytes: [ 0xb7, 0x8d, 0x07, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x8d, 0x07, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0x00, 0x80, 0x07, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x95, 0x07, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin z21.h, p5/m, z21.h, z10.h" + + - + input: + bytes: [ 0xb7, 0x8d, 0x07, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xff, 0x9f, 0x07, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmin z31.h, p7/m, z31.h, z31.h" diff --git a/tests/MC/AArch64/SVE2p1/bfminnm.s.yaml b/tests/MC/AArch64/SVE2p1/bfminnm.s.yaml new file mode 100644 index 0000000000..c4017d0b38 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/bfminnm.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xf7, 0x2f, 0x51, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23.h, p3/m, z31.h" + + - + input: + bytes: [ 0xb7, 0x8d, 0x05, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x8d, 0x05, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0x00, 0x80, 0x05, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x95, 0x05, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm z21.h, p5/m, z21.h, z10.h" + + - + input: + bytes: [ 0xb7, 0x8d, 0x05, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xff, 0x9f, 0x05, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfminnm z31.h, p7/m, z31.h, z31.h" diff --git a/tests/MC/AArch64/SVE2p1/bfmla.s.yaml b/tests/MC/AArch64/SVE2p1/bfmla.s.yaml new file mode 100644 index 0000000000..10847c77a2 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/bfmla.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x09, 0x68, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla z23.h, z13.h, z0.h[5]" + + - + input: + bytes: [ 0x00, 0x08, 0x20, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla z0.h, z0.h, z0.h[0]" + + - + input: + bytes: [ 0x55, 0x09, 0x75, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla z21.h, z10.h, z5.h[6]" + + - + input: + bytes: [ 0xb7, 0x09, 0x68, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla z23.h, z13.h, z0.h[5]" + + - + input: + bytes: [ 0xff, 0x0b, 0x7f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla z31.h, z31.h, z7.h[7]" + + - + input: + bytes: [ 0xf7, 0x2f, 0x51, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23.h, p3/m, z31.h" + + - + input: + bytes: [ 0xb7, 0x0d, 0x28, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla z23.h, p3/m, z13.h, z8.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x0d, 0x28, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla z23.h, p3/m, z13.h, z8.h" + + - + input: + bytes: [ 0x00, 0x00, 0x20, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x15, 0x35, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla z21.h, p5/m, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0x0d, 0x28, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla z23.h, p3/m, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0x1f, 0x3f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmla z31.h, p7/m, z31.h, z31.h" diff --git a/tests/MC/AArch64/SVE2p1/bfmls.s.yaml b/tests/MC/AArch64/SVE2p1/bfmls.s.yaml new file mode 100644 index 0000000000..0cef7f6eb8 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/bfmls.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x0d, 0x68, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls z23.h, z13.h, z0.h[5]" + + - + input: + bytes: [ 0x00, 0x0c, 0x20, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls z0.h, z0.h, z0.h[0]" + + - + input: + bytes: [ 0x55, 0x0d, 0x75, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls z21.h, z10.h, z5.h[6]" + + - + input: + bytes: [ 0xb7, 0x0d, 0x68, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls z23.h, z13.h, z0.h[5]" + + - + input: + bytes: [ 0xff, 0x0f, 0x7f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls z31.h, z31.h, z7.h[7]" + + - + input: + bytes: [ 0xf7, 0x2f, 0x51, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23.h, p3/m, z31.h" + + - + input: + bytes: [ 0xb7, 0x2d, 0x28, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls z23.h, p3/m, z13.h, z8.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x2d, 0x28, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls z23.h, p3/m, z13.h, z8.h" + + - + input: + bytes: [ 0x00, 0x20, 0x20, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x35, 0x35, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls z21.h, p5/m, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0x2d, 0x28, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls z23.h, p3/m, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0x3f, 0x3f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmls z31.h, p7/m, z31.h, z31.h" diff --git a/tests/MC/AArch64/SVE2p1/bfmlslb.s.yaml b/tests/MC/AArch64/SVE2p1/bfmlslb.s.yaml new file mode 100644 index 0000000000..0f94df496e --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/bfmlslb.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0xa1, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslb z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0x00, 0xa0, 0xe0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslb z0.s, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xa1, 0xf5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslb z21.s, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xa1, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslb z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xa3, 0xff, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslb z31.s, z31.h, z31.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x69, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslb z23.s, z13.h, z0.h[3]" + + - + input: + bytes: [ 0x00, 0x60, 0xe0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslb z0.s, z0.h, z0.h[0]" + + - + input: + bytes: [ 0x55, 0x61, 0xf5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslb z21.s, z10.h, z5.h[4]" + + - + input: + bytes: [ 0xb7, 0x69, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslb z23.s, z13.h, z0.h[3]" + + - + input: + bytes: [ 0xff, 0x6b, 0xff, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslb z31.s, z31.h, z7.h[7]" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0xa1, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslb z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0x00, 0xa0, 0xe0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslb z0.s, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xa1, 0xf5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslb z21.s, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xa1, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslb z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xa3, 0xff, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslb z31.s, z31.h, z31.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x69, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslb z23.s, z13.h, z0.h[3]" + + - + input: + bytes: [ 0x00, 0x60, 0xe0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslb z0.s, z0.h, z0.h[0]" + + - + input: + bytes: [ 0x55, 0x61, 0xf5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslb z21.s, z10.h, z5.h[4]" + + - + input: + bytes: [ 0xb7, 0x69, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslb z23.s, z13.h, z0.h[3]" + + - + input: + bytes: [ 0xff, 0x6b, 0xff, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslb z31.s, z31.h, z7.h[7]" diff --git a/tests/MC/AArch64/SVE2p1/bfmlslt.s.yaml b/tests/MC/AArch64/SVE2p1/bfmlslt.s.yaml new file mode 100644 index 0000000000..86e4cb9234 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/bfmlslt.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0xa5, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslt z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0x00, 0xa4, 0xe0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslt z0.s, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xa5, 0xf5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslt z21.s, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xa5, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslt z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xa7, 0xff, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslt z31.s, z31.h, z31.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x6d, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslt z23.s, z13.h, z0.h[3]" + + - + input: + bytes: [ 0x00, 0x64, 0xe0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslt z0.s, z0.h, z0.h[0]" + + - + input: + bytes: [ 0x55, 0x65, 0xf5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslt z21.s, z10.h, z5.h[4]" + + - + input: + bytes: [ 0xb7, 0x6d, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslt z23.s, z13.h, z0.h[3]" + + - + input: + bytes: [ 0xff, 0x6f, 0xff, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "bfmlslt z31.s, z31.h, z7.h[7]" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0xa5, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslt z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0x00, 0xa4, 0xe0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslt z0.s, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xa5, 0xf5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslt z21.s, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xa5, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslt z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xa7, 0xff, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslt z31.s, z31.h, z31.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x6d, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslt z23.s, z13.h, z0.h[3]" + + - + input: + bytes: [ 0x00, 0x64, 0xe0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslt z0.s, z0.h, z0.h[0]" + + - + input: + bytes: [ 0x55, 0x65, 0xf5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslt z21.s, z10.h, z5.h[4]" + + - + input: + bytes: [ 0xb7, 0x6d, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslt z23.s, z13.h, z0.h[3]" + + - + input: + bytes: [ 0xff, 0x6f, 0xff, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "bfmlslt z31.s, z31.h, z7.h[7]" diff --git a/tests/MC/AArch64/SVE2p1/bfmul.s.yaml b/tests/MC/AArch64/SVE2p1/bfmul.s.yaml new file mode 100644 index 0000000000..fe0eb564a4 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/bfmul.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x28, 0x20, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmul z0.h, z0.h, z0.h[0]" + + - + input: + bytes: [ 0x55, 0x29, 0x75, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmul z21.h, z10.h, z5.h[6]" + + - + input: + bytes: [ 0xb7, 0x29, 0x68, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmul z23.h, z13.h, z0.h[5]" + + - + input: + bytes: [ 0xff, 0x2b, 0x7f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmul z31.h, z31.h, z7.h[7]" + + - + input: + bytes: [ 0xf7, 0x2f, 0x51, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23.h, p3/m, z31.h" + + - + input: + bytes: [ 0xb7, 0x8d, 0x02, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmul z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x8d, 0x02, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmul z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0x00, 0x80, 0x02, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmul z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x95, 0x02, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmul z21.h, p5/m, z21.h, z10.h" + + - + input: + bytes: [ 0xb7, 0x8d, 0x02, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmul z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xff, 0x9f, 0x02, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmul z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0x08, 0x00, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmul z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x09, 0x15, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmul z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0x09, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmul z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0x0b, 0x1f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfmul z31.h, z31.h, z31.h" diff --git a/tests/MC/AArch64/SVE2p1/bfsub.s.yaml b/tests/MC/AArch64/SVE2p1/bfsub.s.yaml new file mode 100644 index 0000000000..b243bb7723 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/bfsub.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0xf7, 0x2f, 0x51, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23.h, p3/m, z31.h" + + - + input: + bytes: [ 0xb7, 0x8d, 0x01, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x8d, 0x01, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0x00, 0x80, 0x01, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub z0.h, p0/m, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x95, 0x01, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub z21.h, p5/m, z21.h, z10.h" + + - + input: + bytes: [ 0xb7, 0x8d, 0x01, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub z23.h, p3/m, z23.h, z13.h" + + - + input: + bytes: [ 0xff, 0x9f, 0x01, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub z31.h, p7/m, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0x04, 0x00, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x05, 0x15, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0x05, 0x08, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0x07, 0x1f, 0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ] + expected: + insns: + - + asm_text: "bfsub z31.h, z31.h, z31.h" diff --git a/tests/MC/AArch64/SVE2p1/cntp.s.yaml b/tests/MC/AArch64/SVE2p1/cntp.s.yaml new file mode 100644 index 0000000000..1975135db5 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/cntp.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x82, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "cntp x0, pn0.h, vlx2" + + - + input: + bytes: [ 0x55, 0x87, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "cntp x21, pn10.h, vlx4" + + - + input: + bytes: [ 0xb7, 0x87, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "cntp x23, pn13.h, vlx4" + + - + input: + bytes: [ 0xff, 0x87, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "cntp xzr, pn15.h, vlx4" + + - + input: + bytes: [ 0x00, 0x82, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "cntp x0, pn0.s, vlx2" + + - + input: + bytes: [ 0x55, 0x87, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "cntp x21, pn10.s, vlx4" + + - + input: + bytes: [ 0xb7, 0x87, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "cntp x23, pn13.s, vlx4" + + - + input: + bytes: [ 0xff, 0x87, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "cntp xzr, pn15.s, vlx4" + + - + input: + bytes: [ 0x00, 0x82, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "cntp x0, pn0.d, vlx2" + + - + input: + bytes: [ 0x55, 0x87, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "cntp x21, pn10.d, vlx4" + + - + input: + bytes: [ 0xb7, 0x87, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "cntp x23, pn13.d, vlx4" + + - + input: + bytes: [ 0xff, 0x87, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "cntp xzr, pn15.d, vlx4" + + - + input: + bytes: [ 0x00, 0x82, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "cntp x0, pn0.b, vlx2" + + - + input: + bytes: [ 0x55, 0x87, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "cntp x21, pn10.b, vlx4" + + - + input: + bytes: [ 0xb7, 0x87, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "cntp x23, pn13.b, vlx4" + + - + input: + bytes: [ 0xff, 0x87, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "cntp xzr, pn15.b, vlx4" + + - + input: + bytes: [ 0x00, 0x82, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "cntp x0, pn0.h, vlx2" + + - + input: + bytes: [ 0x55, 0x87, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "cntp x21, pn10.h, vlx4" + + - + input: + bytes: [ 0xb7, 0x87, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "cntp x23, pn13.h, vlx4" + + - + input: + bytes: [ 0xff, 0x87, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "cntp xzr, pn15.h, vlx4" + + - + input: + bytes: [ 0x00, 0x82, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "cntp x0, pn0.s, vlx2" + + - + input: + bytes: [ 0x55, 0x87, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "cntp x21, pn10.s, vlx4" + + - + input: + bytes: [ 0xb7, 0x87, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "cntp x23, pn13.s, vlx4" + + - + input: + bytes: [ 0xff, 0x87, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "cntp xzr, pn15.s, vlx4" + + - + input: + bytes: [ 0x00, 0x82, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "cntp x0, pn0.d, vlx2" + + - + input: + bytes: [ 0x55, 0x87, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "cntp x21, pn10.d, vlx4" + + - + input: + bytes: [ 0xb7, 0x87, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "cntp x23, pn13.d, vlx4" + + - + input: + bytes: [ 0xff, 0x87, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "cntp xzr, pn15.d, vlx4" + + - + input: + bytes: [ 0x00, 0x82, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "cntp x0, pn0.b, vlx2" + + - + input: + bytes: [ 0x55, 0x87, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "cntp x21, pn10.b, vlx4" + + - + input: + bytes: [ 0xb7, 0x87, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "cntp x23, pn13.b, vlx4" + + - + input: + bytes: [ 0xff, 0x87, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "cntp xzr, pn15.b, vlx4" diff --git a/tests/MC/AArch64/SVE2p1/dupq.s.yaml b/tests/MC/AArch64/SVE2p1/dupq.s.yaml new file mode 100644 index 0000000000..0f8f7c102f --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/dupq.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x24, 0x22, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "dupq z0.h, z0.h[0]" + + - + input: + bytes: [ 0x55, 0x25, 0x36, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "dupq z21.h, z10.h[5]" + + - + input: + bytes: [ 0xb7, 0x25, 0x2a, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "dupq z23.h, z13.h[2]" + + - + input: + bytes: [ 0xff, 0x27, 0x3e, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "dupq z31.h, z31.h[7]" + + - + input: + bytes: [ 0x00, 0x24, 0x24, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "dupq z0.s, z0.s[0]" + + - + input: + bytes: [ 0x55, 0x25, 0x34, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "dupq z21.s, z10.s[2]" + + - + input: + bytes: [ 0xb7, 0x25, 0x2c, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "dupq z23.s, z13.s[1]" + + - + input: + bytes: [ 0xff, 0x27, 0x3c, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "dupq z31.s, z31.s[3]" + + - + input: + bytes: [ 0x00, 0x24, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "dupq z0.d, z0.d[0]" + + - + input: + bytes: [ 0x55, 0x25, 0x38, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "dupq z21.d, z10.d[1]" + + - + input: + bytes: [ 0xb7, 0x25, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "dupq z23.d, z13.d[0]" + + - + input: + bytes: [ 0xff, 0x27, 0x38, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "dupq z31.d, z31.d[1]" + + - + input: + bytes: [ 0x00, 0x24, 0x21, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "dupq z0.b, z0.b[0]" + + - + input: + bytes: [ 0x55, 0x25, 0x35, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "dupq z21.b, z10.b[10]" + + - + input: + bytes: [ 0xb7, 0x25, 0x29, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "dupq z23.b, z13.b[4]" + + - + input: + bytes: [ 0xff, 0x27, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "dupq z31.b, z31.b[15]" + + - + input: + bytes: [ 0x00, 0x24, 0x22, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "dupq z0.h, z0.h[0]" + + - + input: + bytes: [ 0x55, 0x25, 0x36, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "dupq z21.h, z10.h[5]" + + - + input: + bytes: [ 0xb7, 0x25, 0x2a, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "dupq z23.h, z13.h[2]" + + - + input: + bytes: [ 0xff, 0x27, 0x3e, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "dupq z31.h, z31.h[7]" + + - + input: + bytes: [ 0x00, 0x24, 0x24, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "dupq z0.s, z0.s[0]" + + - + input: + bytes: [ 0x55, 0x25, 0x34, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "dupq z21.s, z10.s[2]" + + - + input: + bytes: [ 0xb7, 0x25, 0x2c, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "dupq z23.s, z13.s[1]" + + - + input: + bytes: [ 0xff, 0x27, 0x3c, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "dupq z31.s, z31.s[3]" + + - + input: + bytes: [ 0x00, 0x24, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "dupq z0.d, z0.d[0]" + + - + input: + bytes: [ 0x55, 0x25, 0x38, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "dupq z21.d, z10.d[1]" + + - + input: + bytes: [ 0xb7, 0x25, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "dupq z23.d, z13.d[0]" + + - + input: + bytes: [ 0xff, 0x27, 0x38, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "dupq z31.d, z31.d[1]" + + - + input: + bytes: [ 0x00, 0x24, 0x21, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "dupq z0.b, z0.b[0]" + + - + input: + bytes: [ 0x55, 0x25, 0x35, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "dupq z21.b, z10.b[10]" + + - + input: + bytes: [ 0xb7, 0x25, 0x29, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "dupq z23.b, z13.b[4]" + + - + input: + bytes: [ 0xff, 0x27, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "dupq z31.b, z31.b[15]" diff --git a/tests/MC/AArch64/SVE2p1/eorqv.s.yaml b/tests/MC/AArch64/SVE2p1/eorqv.s.yaml new file mode 100644 index 0000000000..1d413c0c0c --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/eorqv.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x5d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "eorqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0x35, 0x5d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "eorqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0x2d, 0x5d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "eorqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0x3f, 0x5d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "eorqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0x20, 0x9d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "eorqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0x35, 0x9d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "eorqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0x2d, 0x9d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "eorqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0x3f, 0x9d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "eorqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0x20, 0xdd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "eorqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0x35, 0xdd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "eorqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0x2d, 0xdd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "eorqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0x3f, 0xdd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "eorqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0x20, 0x1d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "eorqv v0.16b, p0, z0.b" + + - + input: + bytes: [ 0x55, 0x35, 0x1d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "eorqv v21.16b, p5, z10.b" + + - + input: + bytes: [ 0xb7, 0x2d, 0x1d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "eorqv v23.16b, p3, z13.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x1d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "eorqv v31.16b, p7, z31.b" + + - + input: + bytes: [ 0x00, 0x20, 0x5d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "eorqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0x35, 0x5d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "eorqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0x2d, 0x5d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "eorqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0x3f, 0x5d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "eorqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0x20, 0x9d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "eorqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0x35, 0x9d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "eorqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0x2d, 0x9d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "eorqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0x3f, 0x9d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "eorqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0x20, 0xdd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "eorqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0x35, 0xdd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "eorqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0x2d, 0xdd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "eorqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0x3f, 0xdd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "eorqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0x20, 0x1d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "eorqv v0.16b, p0, z0.b" + + - + input: + bytes: [ 0x55, 0x35, 0x1d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "eorqv v21.16b, p5, z10.b" + + - + input: + bytes: [ 0xb7, 0x2d, 0x1d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "eorqv v23.16b, p3, z13.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x1d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "eorqv v31.16b, p7, z31.b" diff --git a/tests/MC/AArch64/SVE2p1/extq.s.yaml b/tests/MC/AArch64/SVE2p1/extq.s.yaml new file mode 100644 index 0000000000..0195b1462a --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/extq.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x25, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "extq z23.b, z23.b, z13.b, #8" + + - + input: + bytes: [ 0x00, 0x24, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "extq z0.b, z0.b, z0.b, #0" + + - + input: + bytes: [ 0x55, 0x25, 0x65, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "extq z21.b, z21.b, z10.b, #5" + + - + input: + bytes: [ 0xb7, 0x25, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "extq z23.b, z23.b, z13.b, #8" + + - + input: + bytes: [ 0xff, 0x27, 0x6f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "extq z31.b, z31.b, z31.b, #15" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x25, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "extq z23.b, z23.b, z13.b, #8" + + - + input: + bytes: [ 0x00, 0x24, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "extq z0.b, z0.b, z0.b, #0" + + - + input: + bytes: [ 0x55, 0x25, 0x65, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "extq z21.b, z21.b, z10.b, #5" + + - + input: + bytes: [ 0xb7, 0x25, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "extq z23.b, z23.b, z13.b, #8" + + - + input: + bytes: [ 0xff, 0x27, 0x6f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "extq z31.b, z31.b, z31.b, #15" diff --git a/tests/MC/AArch64/SVE2p1/faddqv.s.yaml b/tests/MC/AArch64/SVE2p1/faddqv.s.yaml new file mode 100644 index 0000000000..b0fa9e6c90 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/faddqv.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0xd0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "faddqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0xb5, 0xd0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "faddqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0xad, 0xd0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "faddqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0xbf, 0xd0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "faddqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x50, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "faddqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0xb5, 0x50, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "faddqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0xad, 0x50, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "faddqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x50, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "faddqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x90, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "faddqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0xb5, 0x90, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "faddqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0xad, 0x90, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "faddqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0xbf, 0x90, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "faddqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "faddqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0xb5, 0xd0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "faddqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0xad, 0xd0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "faddqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0xbf, 0xd0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "faddqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x50, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "faddqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0xb5, 0x50, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "faddqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0xad, 0x50, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "faddqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x50, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "faddqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x90, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "faddqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0xb5, 0x90, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "faddqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0xad, 0x90, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "faddqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0xbf, 0x90, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "faddqv v31.4s, p7, z31.s" diff --git a/tests/MC/AArch64/SVE2p1/fclamp.s.yaml b/tests/MC/AArch64/SVE2p1/fclamp.s.yaml new file mode 100644 index 0000000000..a4dad93060 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/fclamp.s.yaml @@ -0,0 +1,360 @@ +test_cases: + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x25, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0x00, 0x24, 0xe0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x55, 0x25, 0xf5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp z21.d, z10.d, z21.d" + + - + input: + bytes: [ 0xb7, 0x25, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0x27, 0xff, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x25, 0x68, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0x00, 0x24, 0x60, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x25, 0x75, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0x25, 0x68, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0x27, 0x7f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x25, 0xa8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0x00, 0x24, 0xa0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x55, 0x25, 0xb5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp z21.s, z10.s, z21.s" + + - + input: + bytes: [ 0xb7, 0x25, 0xa8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0xff, 0x27, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fclamp z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x25, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fclamp z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0x00, 0x24, 0xe0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fclamp z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x55, 0x25, 0xf5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fclamp z21.d, z10.d, z21.d" + + - + input: + bytes: [ 0xb7, 0x25, 0xe8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fclamp z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0x27, 0xff, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fclamp z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x25, 0x68, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fclamp z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0x00, 0x24, 0x60, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fclamp z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x25, 0x75, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fclamp z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0x25, 0x68, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fclamp z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0x27, 0x7f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fclamp z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x25, 0xa8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fclamp z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0x00, 0x24, 0xa0, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fclamp z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x55, 0x25, 0xb5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fclamp z21.s, z10.s, z21.s" + + - + input: + bytes: [ 0xb7, 0x25, 0xa8, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fclamp z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0xff, 0x27, 0xbf, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fclamp z31.s, z31.s, z31.s" diff --git a/tests/MC/AArch64/SVE2p1/fdot.s.yaml b/tests/MC/AArch64/SVE2p1/fdot.s.yaml new file mode 100644 index 0000000000..ef62304bd3 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/fdot.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x81, 0x28, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0x00, 0x80, 0x20, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot z0.s, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x81, 0x35, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot z21.s, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0x81, 0x28, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0x83, 0x3f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot z31.s, z31.h, z31.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x41, 0x28, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot z23.s, z13.h, z0.h[1]" + + - + input: + bytes: [ 0x00, 0x40, 0x20, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot z0.s, z0.h, z0.h[0]" + + - + input: + bytes: [ 0x55, 0x41, 0x35, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot z21.s, z10.h, z5.h[2]" + + - + input: + bytes: [ 0xb7, 0x41, 0x28, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot z23.s, z13.h, z0.h[1]" + + - + input: + bytes: [ 0xff, 0x43, 0x3f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "fdot z31.s, z31.h, z7.h[3]" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x81, 0x28, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fdot z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0x00, 0x80, 0x20, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fdot z0.s, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x81, 0x35, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fdot z21.s, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0x81, 0x28, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fdot z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0x83, 0x3f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fdot z31.s, z31.h, z31.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0x41, 0x28, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fdot z23.s, z13.h, z0.h[1]" + + - + input: + bytes: [ 0x00, 0x40, 0x20, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fdot z0.s, z0.h, z0.h[0]" + + - + input: + bytes: [ 0x55, 0x41, 0x35, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fdot z21.s, z10.h, z5.h[2]" + + - + input: + bytes: [ 0xb7, 0x41, 0x28, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fdot z23.s, z13.h, z0.h[1]" + + - + input: + bytes: [ 0xff, 0x43, 0x3f, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fdot z31.s, z31.h, z7.h[3]" diff --git a/tests/MC/AArch64/SVE2p1/feature-sve2p1-implies-sve2.s.yaml b/tests/MC/AArch64/SVE2p1/feature-sve2p1-implies-sve2.s.yaml new file mode 100644 index 0000000000..f7f5644c5e --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/feature-sve2p1-implies-sve2.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x20, 0x02, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "cmla z0.b, z1.b, z2.b, #0" diff --git a/tests/MC/AArch64/SVE2p1/fmaxnmqv.s.yaml b/tests/MC/AArch64/SVE2p1/fmaxnmqv.s.yaml new file mode 100644 index 0000000000..8de0e1d13b --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/fmaxnmqv.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0xd4, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0xb5, 0xd4, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0xad, 0xd4, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0xbf, 0xd4, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x54, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0xb5, 0x54, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0xad, 0x54, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x54, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x94, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0xb5, 0x94, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0xad, 0x94, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0xbf, 0x94, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd4, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0xb5, 0xd4, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0xad, 0xd4, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0xbf, 0xd4, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x54, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0xb5, 0x54, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0xad, 0x54, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x54, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x94, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0xb5, 0x94, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0xad, 0x94, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0xbf, 0x94, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxnmqv v31.4s, p7, z31.s" diff --git a/tests/MC/AArch64/SVE2p1/fmaxqv.s.yaml b/tests/MC/AArch64/SVE2p1/fmaxqv.s.yaml new file mode 100644 index 0000000000..5039327e43 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/fmaxqv.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0xd6, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0xb5, 0xd6, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0xad, 0xd6, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0xbf, 0xd6, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x56, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0xb5, 0x56, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0xad, 0x56, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x56, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x96, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0xb5, 0x96, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0xad, 0x96, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0xbf, 0x96, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd6, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0xb5, 0xd6, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0xad, 0xd6, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0xbf, 0xd6, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x56, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0xb5, 0x56, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0xad, 0x56, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x56, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x96, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0xb5, 0x96, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0xad, 0x96, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0xbf, 0x96, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fmaxqv v31.4s, p7, z31.s" diff --git a/tests/MC/AArch64/SVE2p1/fminnmqv.s.yaml b/tests/MC/AArch64/SVE2p1/fminnmqv.s.yaml new file mode 100644 index 0000000000..33bbd9a3c9 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/fminnmqv.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0xd5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0xb5, 0xd5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0xad, 0xd5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0xbf, 0xd5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x55, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0xb5, 0x55, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0xad, 0x55, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x55, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x95, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0xb5, 0x95, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0xad, 0x95, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0xbf, 0x95, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0xb5, 0xd5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0xad, 0xd5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0xbf, 0xd5, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x55, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0xb5, 0x55, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0xad, 0x55, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x55, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x95, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0xb5, 0x95, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0xad, 0x95, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0xbf, 0x95, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminnmqv v31.4s, p7, z31.s" diff --git a/tests/MC/AArch64/SVE2p1/fminqv.s.yaml b/tests/MC/AArch64/SVE2p1/fminqv.s.yaml new file mode 100644 index 0000000000..3d35165291 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/fminqv.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0xd7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0xb5, 0xd7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0xad, 0xd7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0xbf, 0xd7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x57, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0xb5, 0x57, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0xad, 0x57, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x57, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x97, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0xb5, 0x97, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0xad, 0x97, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0xbf, 0x97, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "fminqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0xa0, 0xd7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0xb5, 0xd7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0xad, 0xd7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0xbf, 0xd7, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0xa0, 0x57, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0xb5, 0x57, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0xad, 0x57, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0xbf, 0x57, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0xa0, 0x97, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0xb5, 0x97, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0xad, 0x97, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0xbf, 0x97, 0x64 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "fminqv v31.4s, p7, z31.s" diff --git a/tests/MC/AArch64/SVE2p1/ld1b.s.yaml b/tests/MC/AArch64/SVE2p1/ld1b.s.yaml new file mode 100644 index 0000000000..ac07f4c6f0 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/ld1b.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z0.b, z1.b }, pn8/z, [x0, x0]" + + - + input: + bytes: [ 0x54, 0x15, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z20.b, z21.b }, pn13/z, [x10, x21]" + + - + input: + bytes: [ 0xb6, 0x0d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z22.b, z23.b }, pn11/z, [x13, x8]" + + - + input: + bytes: [ 0xfe, 0x1f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z30.b, z31.b }, pn15/z, [sp, xzr]" + + - + input: + bytes: [ 0x00, 0x00, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z0.b, z1.b }, pn8/z, [x0]" + + - + input: + bytes: [ 0x54, 0x15, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z20.b, z21.b }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb6, 0x0d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z22.b, z23.b }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xfe, 0x1f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z30.b, z31.b }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0x80, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z0.b - z3.b }, pn8/z, [x0, x0]" + + - + input: + bytes: [ 0x54, 0x95, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z20.b - z23.b }, pn13/z, [x10, x21]" + + - + input: + bytes: [ 0xb4, 0x8d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z20.b - z23.b }, pn11/z, [x13, x8]" + + - + input: + bytes: [ 0xfc, 0x9f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z28.b - z31.b }, pn15/z, [sp, xzr]" + + - + input: + bytes: [ 0x00, 0x80, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z0.b - z3.b }, pn8/z, [x0]" + + - + input: + bytes: [ 0x54, 0x95, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z20.b - z23.b }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb4, 0x8d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z20.b - z23.b }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfc, 0x9f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1b { z28.b - z31.b }, pn15/z, [sp, #-4, mul vl]" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1b { z0.b, z1.b }, pn8/z, [x0, x0]" + + - + input: + bytes: [ 0x54, 0x15, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1b { z20.b, z21.b }, pn13/z, [x10, x21]" + + - + input: + bytes: [ 0xb6, 0x0d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1b { z22.b, z23.b }, pn11/z, [x13, x8]" + + - + input: + bytes: [ 0xfe, 0x1f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1b { z30.b, z31.b }, pn15/z, [sp, xzr]" + + - + input: + bytes: [ 0x00, 0x00, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1b { z0.b, z1.b }, pn8/z, [x0]" + + - + input: + bytes: [ 0x54, 0x15, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1b { z20.b, z21.b }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb6, 0x0d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1b { z22.b, z23.b }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xfe, 0x1f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1b { z30.b, z31.b }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0x80, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1b { z0.b - z3.b }, pn8/z, [x0, x0]" + + - + input: + bytes: [ 0x54, 0x95, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1b { z20.b - z23.b }, pn13/z, [x10, x21]" + + - + input: + bytes: [ 0xb4, 0x8d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1b { z20.b - z23.b }, pn11/z, [x13, x8]" + + - + input: + bytes: [ 0xfc, 0x9f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1b { z28.b - z31.b }, pn15/z, [sp, xzr]" + + - + input: + bytes: [ 0x00, 0x80, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1b { z0.b - z3.b }, pn8/z, [x0]" + + - + input: + bytes: [ 0x54, 0x95, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1b { z20.b - z23.b }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb4, 0x8d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1b { z20.b - z23.b }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfc, 0x9f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1b { z28.b - z31.b }, pn15/z, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/ld1d.s.yaml b/tests/MC/AArch64/SVE2p1/ld1d.s.yaml new file mode 100644 index 0000000000..79240c6484 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/ld1d.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z0.d, z1.d }, pn8/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x54, 0x75, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z20.d, z21.d }, pn13/z, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb6, 0x6d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z22.d, z23.d }, pn11/z, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xfe, 0x7f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z30.d, z31.d }, pn15/z, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x00, 0x60, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z0.d, z1.d }, pn8/z, [x0]" + + - + input: + bytes: [ 0x54, 0x75, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z20.d, z21.d }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb6, 0x6d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z22.d, z23.d }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xfe, 0x7f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z30.d, z31.d }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z0.d - z3.d }, pn8/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x54, 0xf5, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z20.d - z23.d }, pn13/z, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb4, 0xed, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z20.d - z23.d }, pn11/z, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xfc, 0xff, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z28.d - z31.d }, pn15/z, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z0.d - z3.d }, pn8/z, [x0]" + + - + input: + bytes: [ 0x54, 0xf5, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z20.d - z23.d }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb4, 0xed, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z20.d - z23.d }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfc, 0xff, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1d { z28.d - z31.d }, pn15/z, [sp, #-4, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z0.d, z1.d }, pn8/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x54, 0x75, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z20.d, z21.d }, pn13/z, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb6, 0x6d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z22.d, z23.d }, pn11/z, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xfe, 0x7f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z30.d, z31.d }, pn15/z, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x00, 0x60, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z0.d, z1.d }, pn8/z, [x0]" + + - + input: + bytes: [ 0x54, 0x75, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z20.d, z21.d }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb6, 0x6d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z22.d, z23.d }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xfe, 0x7f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z30.d, z31.d }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z0.d - z3.d }, pn8/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x54, 0xf5, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z20.d - z23.d }, pn13/z, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb4, 0xed, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z20.d - z23.d }, pn11/z, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xfc, 0xff, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z28.d - z31.d }, pn15/z, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z0.d - z3.d }, pn8/z, [x0]" + + - + input: + bytes: [ 0x54, 0xf5, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z20.d - z23.d }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb4, 0xed, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z20.d - z23.d }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfc, 0xff, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z28.d - z31.d }, pn15/z, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/ld1d_q.s.yaml b/tests/MC/AArch64/SVE2p1/ld1d_q.s.yaml new file mode 100644 index 0000000000..78820c6e98 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/ld1d_q.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x80, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z0.q }, p0/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x55, 0x95, 0x95, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z21.q }, p5/z, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb7, 0x8d, 0x88, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z23.q }, p3/z, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xb7, 0x8d, 0x88, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z23.q }, p3/z, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0x00, 0x20, 0x90, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z0.q }, p0/z, [x0]" + + - + input: + bytes: [ 0x00, 0x20, 0x90, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z0.q }, p0/z, [x0]" + + - + input: + bytes: [ 0x55, 0x35, 0x95, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z21.q }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x98, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z23.q }, p3/z, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0xff, 0x3f, 0x9f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z31.q }, p7/z, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0xff, 0x3f, 0x9f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1d { z31.q }, p7/z, [sp, #-1, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/ld1h.s.yaml b/tests/MC/AArch64/SVE2p1/ld1h.s.yaml new file mode 100644 index 0000000000..0c1971565b --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/ld1h.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z0.h, z1.h }, pn8/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x54, 0x35, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z20.h, z21.h }, pn13/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb6, 0x2d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z22.h, z23.h }, pn11/z, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xfe, 0x3f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z30.h, z31.h }, pn15/z, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x00, 0x20, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z0.h, z1.h }, pn8/z, [x0]" + + - + input: + bytes: [ 0x54, 0x35, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z20.h, z21.h }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb6, 0x2d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z22.h, z23.h }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xfe, 0x3f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z30.h, z31.h }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z0.h - z3.h }, pn8/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x54, 0xb5, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z20.h - z23.h }, pn13/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb4, 0xad, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z20.h - z23.h }, pn11/z, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xfc, 0xbf, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z28.h - z31.h }, pn15/z, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z0.h - z3.h }, pn8/z, [x0]" + + - + input: + bytes: [ 0x54, 0xb5, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z20.h - z23.h }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb4, 0xad, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z20.h - z23.h }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfc, 0xbf, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1h { z28.h - z31.h }, pn15/z, [sp, #-4, mul vl]" + + - + input: + bytes: [ 0x00, 0x20, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1h { z0.h, z1.h }, pn8/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x54, 0x35, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1h { z20.h, z21.h }, pn13/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb6, 0x2d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1h { z22.h, z23.h }, pn11/z, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xfe, 0x3f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1h { z30.h, z31.h }, pn15/z, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x00, 0x20, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1h { z0.h, z1.h }, pn8/z, [x0]" + + - + input: + bytes: [ 0x54, 0x35, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1h { z20.h, z21.h }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb6, 0x2d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1h { z22.h, z23.h }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xfe, 0x3f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1h { z30.h, z31.h }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1h { z0.h - z3.h }, pn8/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x54, 0xb5, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1h { z20.h - z23.h }, pn13/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb4, 0xad, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1h { z20.h - z23.h }, pn11/z, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xfc, 0xbf, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1h { z28.h - z31.h }, pn15/z, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1h { z0.h - z3.h }, pn8/z, [x0]" + + - + input: + bytes: [ 0x54, 0xb5, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1h { z20.h - z23.h }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb4, 0xad, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1h { z20.h - z23.h }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfc, 0xbf, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1h { z28.h - z31.h }, pn15/z, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/ld1q.s.yaml b/tests/MC/AArch64/SVE2p1/ld1q.s.yaml new file mode 100644 index 0000000000..de0f6e1cbc --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/ld1q.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1q { z0.q }, p0/z, [z0.d, x0]" + + - + input: + bytes: [ 0x55, 0xb5, 0x15, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1q { z21.q }, p5/z, [z10.d, x21]" + + - + input: + bytes: [ 0xb7, 0xad, 0x08, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1q { z23.q }, p3/z, [z13.d, x8]" + + - + input: + bytes: [ 0xff, 0xbf, 0x1f, 0xc4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1q { z31.q }, p7/z, [z31.d]" diff --git a/tests/MC/AArch64/SVE2p1/ld1w.s.yaml b/tests/MC/AArch64/SVE2p1/ld1w.s.yaml new file mode 100644 index 0000000000..dd4ad3faaa --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/ld1w.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z0.s, z1.s }, pn8/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x54, 0x55, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z20.s, z21.s }, pn13/z, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb6, 0x4d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z22.s, z23.s }, pn11/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xfe, 0x5f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z30.s, z31.s }, pn15/z, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x00, 0x40, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z0.s, z1.s }, pn8/z, [x0]" + + - + input: + bytes: [ 0x54, 0x55, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z20.s, z21.s }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb6, 0x4d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z22.s, z23.s }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xfe, 0x5f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z30.s, z31.s }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z0.s - z3.s }, pn8/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x54, 0xd5, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z20.s - z23.s }, pn13/z, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb4, 0xcd, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z20.s - z23.s }, pn11/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xfc, 0xdf, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z28.s - z31.s }, pn15/z, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x00, 0xc0, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z0.s - z3.s }, pn8/z, [x0]" + + - + input: + bytes: [ 0x54, 0xd5, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z20.s - z23.s }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb4, 0xcd, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z20.s - z23.s }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfc, 0xdf, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ld1w { z28.s - z31.s }, pn15/z, [sp, #-4, mul vl]" + + - + input: + bytes: [ 0x00, 0x40, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z0.s, z1.s }, pn8/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x54, 0x55, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z20.s, z21.s }, pn13/z, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb6, 0x4d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z22.s, z23.s }, pn11/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xfe, 0x5f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z30.s, z31.s }, pn15/z, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x00, 0x40, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z0.s, z1.s }, pn8/z, [x0]" + + - + input: + bytes: [ 0x54, 0x55, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z20.s, z21.s }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb6, 0x4d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z22.s, z23.s }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xfe, 0x5f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z30.s, z31.s }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z0.s - z3.s }, pn8/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x54, 0xd5, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z20.s - z23.s }, pn13/z, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb4, 0xcd, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z20.s - z23.s }, pn11/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xfc, 0xdf, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z28.s - z31.s }, pn15/z, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x00, 0xc0, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z0.s - z3.s }, pn8/z, [x0]" + + - + input: + bytes: [ 0x54, 0xd5, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z20.s - z23.s }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb4, 0xcd, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z20.s - z23.s }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfc, 0xdf, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z28.s - z31.s }, pn15/z, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/ld1w_q.s.yaml b/tests/MC/AArch64/SVE2p1/ld1w_q.s.yaml new file mode 100644 index 0000000000..c93d49259e --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/ld1w_q.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x00, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z0.q }, p0/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x55, 0x95, 0x15, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z21.q }, p5/z, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb7, 0x8d, 0x08, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z23.q }, p3/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xb7, 0x8d, 0x08, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z23.q }, p3/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0x00, 0x20, 0x10, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z0.q }, p0/z, [x0]" + + - + input: + bytes: [ 0x55, 0x35, 0x15, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z21.q }, p5/z, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x18, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z23.q }, p3/z, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0xff, 0x3f, 0x1f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld1w { z31.q }, p7/z, [sp, #-1, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/ld2q.s.yaml b/tests/MC/AArch64/SVE2p1/ld2q.s.yaml new file mode 100644 index 0000000000..0b387bbd59 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/ld2q.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0xa0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld2q { z0.q, z1.q }, p0/z, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x55, 0x95, 0xb5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld2q { z21.q, z22.q }, p5/z, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xb7, 0x8d, 0xa8, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld2q { z23.q, z24.q }, p3/z, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0x00, 0xe0, 0x90, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld2q { z0.q, z1.q }, p0/z, [x0]" + + - + input: + bytes: [ 0x55, 0xf5, 0x95, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld2q { z21.q, z22.q }, p5/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0xed, 0x98, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld2q { z23.q, z24.q }, p3/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0x9f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld2q { z31.q, z0.q }, p7/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0x80, 0xa0, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld2q { z0.q, z1.q }, p0/z, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x55, 0x95, 0xb5, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld2q { z21.q, z22.q }, p5/z, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xb7, 0x8d, 0xa8, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld2q { z23.q, z24.q }, p3/z, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0x00, 0xe0, 0x90, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld2q { z0.q, z1.q }, p0/z, [x0]" + + - + input: + bytes: [ 0x55, 0xf5, 0x95, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld2q { z21.q, z22.q }, p5/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0xed, 0x98, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld2q { z23.q, z24.q }, p3/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0x9f, 0xa4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld2q { z31.q, z0.q }, p7/z, [sp, #-2, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/ld3q.s.yaml b/tests/MC/AArch64/SVE2p1/ld3q.s.yaml new file mode 100644 index 0000000000..0657f697dd --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/ld3q.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0x20, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld3q { z0.q - z2.q }, p0/z, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x55, 0x95, 0x35, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld3q { z21.q - z23.q }, p5/z, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xb7, 0x8d, 0x28, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld3q { z23.q - z25.q }, p3/z, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0x00, 0xe0, 0x10, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld3q { z0.q - z2.q }, p0/z, [x0]" + + - + input: + bytes: [ 0x55, 0xf5, 0x15, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld3q { z21.q - z23.q }, p5/z, [x10, #15, mul vl]" + + - + input: + bytes: [ 0xb7, 0xed, 0x18, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld3q { z23.q - z25.q }, p3/z, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0x1f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld3q { z31.q, z0.q, z1.q }, p7/z, [sp, #-3, mul vl]" + + - + input: + bytes: [ 0x00, 0x80, 0x20, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld3q { z0.q - z2.q }, p0/z, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x55, 0x95, 0x35, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld3q { z21.q - z23.q }, p5/z, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xb7, 0x8d, 0x28, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld3q { z23.q - z25.q }, p3/z, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0x00, 0xe0, 0x10, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld3q { z0.q - z2.q }, p0/z, [x0]" + + - + input: + bytes: [ 0x55, 0xf5, 0x15, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld3q { z21.q - z23.q }, p5/z, [x10, #15, mul vl]" + + - + input: + bytes: [ 0xb7, 0xed, 0x18, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld3q { z23.q - z25.q }, p3/z, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0x1f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld3q { z31.q, z0.q, z1.q }, p7/z, [sp, #-3, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/ld4q.s.yaml b/tests/MC/AArch64/SVE2p1/ld4q.s.yaml new file mode 100644 index 0000000000..5b6eac0374 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/ld4q.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x80, 0xa0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld4q { z0.q - z3.q }, p0/z, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x55, 0x95, 0xb5, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld4q { z21.q - z24.q }, p5/z, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xb7, 0x8d, 0xa8, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld4q { z23.q - z26.q }, p3/z, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0x00, 0xe0, 0x90, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld4q { z0.q - z3.q }, p0/z, [x0]" + + - + input: + bytes: [ 0x55, 0xf5, 0x95, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld4q { z21.q - z24.q }, p5/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb7, 0xed, 0x98, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld4q { z23.q - z26.q }, p3/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0x9f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "ld4q { z31.q, z0.q, z1.q, z2.q }, p7/z, [sp, #-4, mul vl]" + + - + input: + bytes: [ 0x00, 0x80, 0xa0, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld4q { z0.q - z3.q }, p0/z, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x55, 0x95, 0xb5, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld4q { z21.q - z24.q }, p5/z, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xb7, 0x8d, 0xa8, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld4q { z23.q - z26.q }, p3/z, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0x00, 0xe0, 0x90, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld4q { z0.q - z3.q }, p0/z, [x0]" + + - + input: + bytes: [ 0x55, 0xf5, 0x95, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld4q { z21.q - z24.q }, p5/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb7, 0xed, 0x98, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld4q { z23.q - z26.q }, p3/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0x9f, 0xa5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ld4q { z31.q, z0.q, z1.q, z2.q }, p7/z, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/ldnt1b.s.yaml b/tests/MC/AArch64/SVE2p1/ldnt1b.s.yaml new file mode 100644 index 0000000000..e135d5f197 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/ldnt1b.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x00, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.b, z1.b }, pn8/z, [x0, x0]" + + - + input: + bytes: [ 0x55, 0x15, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z20.b, z21.b }, pn13/z, [x10, x21]" + + - + input: + bytes: [ 0xb7, 0x0d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z22.b, z23.b }, pn11/z, [x13, x8]" + + - + input: + bytes: [ 0xff, 0x1f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z30.b, z31.b }, pn15/z, [sp, xzr]" + + - + input: + bytes: [ 0x01, 0x00, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.b, z1.b }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0x15, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z20.b, z21.b }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x0d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z22.b, z23.b }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x1f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z30.b, z31.b }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x01, 0x80, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.b - z3.b }, pn8/z, [x0, x0]" + + - + input: + bytes: [ 0x55, 0x95, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z20.b - z23.b }, pn13/z, [x10, x21]" + + - + input: + bytes: [ 0xb5, 0x8d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z20.b - z23.b }, pn11/z, [x13, x8]" + + - + input: + bytes: [ 0xfd, 0x9f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z28.b - z31.b }, pn15/z, [sp, xzr]" + + - + input: + bytes: [ 0x01, 0x80, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.b - z3.b }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0x95, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z20.b - z23.b }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb5, 0x8d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z20.b - z23.b }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfd, 0x9f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1b { z28.b - z31.b }, pn15/z, [sp, #-4, mul vl]" + + - + input: + bytes: [ 0x01, 0x00, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.b, z1.b }, pn8/z, [x0, x0]" + + - + input: + bytes: [ 0x55, 0x15, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1b { z20.b, z21.b }, pn13/z, [x10, x21]" + + - + input: + bytes: [ 0xb7, 0x0d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1b { z22.b, z23.b }, pn11/z, [x13, x8]" + + - + input: + bytes: [ 0xff, 0x1f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1b { z30.b, z31.b }, pn15/z, [sp, xzr]" + + - + input: + bytes: [ 0x01, 0x00, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.b, z1.b }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0x15, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1b { z20.b, z21.b }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x0d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1b { z22.b, z23.b }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x1f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1b { z30.b, z31.b }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x01, 0x80, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.b - z3.b }, pn8/z, [x0, x0]" + + - + input: + bytes: [ 0x55, 0x95, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1b { z20.b - z23.b }, pn13/z, [x10, x21]" + + - + input: + bytes: [ 0xb5, 0x8d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1b { z20.b - z23.b }, pn11/z, [x13, x8]" + + - + input: + bytes: [ 0xfd, 0x9f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1b { z28.b - z31.b }, pn15/z, [sp, xzr]" + + - + input: + bytes: [ 0x01, 0x80, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1b { z0.b - z3.b }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0x95, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1b { z20.b - z23.b }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb5, 0x8d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1b { z20.b - z23.b }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfd, 0x9f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1b { z28.b - z31.b }, pn15/z, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/ldnt1d.s.yaml b/tests/MC/AArch64/SVE2p1/ldnt1d.s.yaml new file mode 100644 index 0000000000..774115116b --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/ldnt1d.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x60, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d, z1.d }, pn8/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x55, 0x75, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z20.d, z21.d }, pn13/z, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z22.d, z23.d }, pn11/z, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xff, 0x7f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z30.d, z31.d }, pn15/z, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x01, 0x60, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d, z1.d }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0x75, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z20.d, z21.d }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z22.d, z23.d }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x7f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z30.d, z31.d }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x01, 0xe0, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d - z3.d }, pn8/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x55, 0xf5, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z20.d - z23.d }, pn13/z, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb5, 0xed, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z20.d - z23.d }, pn11/z, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xfd, 0xff, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z28.d - z31.d }, pn15/z, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x01, 0xe0, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d - z3.d }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0xf5, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z20.d - z23.d }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb5, 0xed, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z20.d - z23.d }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfd, 0xff, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1d { z28.d - z31.d }, pn15/z, [sp, #-4, mul vl]" + + - + input: + bytes: [ 0x01, 0x60, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d, z1.d }, pn8/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x55, 0x75, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1d { z20.d, z21.d }, pn13/z, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1d { z22.d, z23.d }, pn11/z, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xff, 0x7f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1d { z30.d, z31.d }, pn15/z, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x01, 0x60, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d, z1.d }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0x75, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1d { z20.d, z21.d }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1d { z22.d, z23.d }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x7f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1d { z30.d, z31.d }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x01, 0xe0, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d - z3.d }, pn8/z, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x55, 0xf5, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1d { z20.d - z23.d }, pn13/z, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb5, 0xed, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1d { z20.d - z23.d }, pn11/z, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xfd, 0xff, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1d { z28.d - z31.d }, pn15/z, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x01, 0xe0, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1d { z0.d - z3.d }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0xf5, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1d { z20.d - z23.d }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb5, 0xed, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1d { z20.d - z23.d }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfd, 0xff, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1d { z28.d - z31.d }, pn15/z, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/ldnt1h.s.yaml b/tests/MC/AArch64/SVE2p1/ldnt1h.s.yaml new file mode 100644 index 0000000000..0329153e96 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/ldnt1h.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x20, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.h, z1.h }, pn8/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x55, 0x35, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z20.h, z21.h }, pn13/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z22.h, z23.h }, pn11/z, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xff, 0x3f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z30.h, z31.h }, pn15/z, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x01, 0x20, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.h, z1.h }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0x35, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z20.h, z21.h }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z22.h, z23.h }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x3f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z30.h, z31.h }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x01, 0xa0, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.h - z3.h }, pn8/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x55, 0xb5, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z20.h - z23.h }, pn13/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb5, 0xad, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z20.h - z23.h }, pn11/z, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xfd, 0xbf, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z28.h - z31.h }, pn15/z, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x01, 0xa0, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.h - z3.h }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0xb5, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z20.h - z23.h }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb5, 0xad, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z20.h - z23.h }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfd, 0xbf, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1h { z28.h - z31.h }, pn15/z, [sp, #-4, mul vl]" + + - + input: + bytes: [ 0x01, 0x20, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.h, z1.h }, pn8/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x55, 0x35, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1h { z20.h, z21.h }, pn13/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1h { z22.h, z23.h }, pn11/z, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xff, 0x3f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1h { z30.h, z31.h }, pn15/z, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x01, 0x20, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.h, z1.h }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0x35, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1h { z20.h, z21.h }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1h { z22.h, z23.h }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x3f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1h { z30.h, z31.h }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x01, 0xa0, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.h - z3.h }, pn8/z, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x55, 0xb5, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1h { z20.h - z23.h }, pn13/z, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb5, 0xad, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1h { z20.h - z23.h }, pn11/z, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xfd, 0xbf, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1h { z28.h - z31.h }, pn15/z, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x01, 0xa0, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1h { z0.h - z3.h }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0xb5, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1h { z20.h - z23.h }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb5, 0xad, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1h { z20.h - z23.h }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfd, 0xbf, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1h { z28.h - z31.h }, pn15/z, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/ldnt1w.s.yaml b/tests/MC/AArch64/SVE2p1/ldnt1w.s.yaml new file mode 100644 index 0000000000..d0b6e3bb28 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/ldnt1w.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x40, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s, z1.s }, pn8/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x55, 0x55, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z20.s, z21.s }, pn13/z, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z22.s, z23.s }, pn11/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xff, 0x5f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z30.s, z31.s }, pn15/z, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x01, 0x40, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s, z1.s }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0x55, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z20.s, z21.s }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z22.s, z23.s }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x5f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z30.s, z31.s }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x01, 0xc0, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s - z3.s }, pn8/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x55, 0xd5, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z20.s - z23.s }, pn13/z, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb5, 0xcd, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z20.s - z23.s }, pn11/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xfd, 0xdf, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z28.s - z31.s }, pn15/z, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x01, 0xc0, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s - z3.s }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0xd5, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z20.s - z23.s }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb5, 0xcd, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z20.s - z23.s }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfd, 0xdf, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ldnt1w { z28.s - z31.s }, pn15/z, [sp, #-4, mul vl]" + + - + input: + bytes: [ 0x01, 0x40, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s, z1.s }, pn8/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x55, 0x55, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1w { z20.s, z21.s }, pn13/z, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1w { z22.s, z23.s }, pn11/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xff, 0x5f, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1w { z30.s, z31.s }, pn15/z, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x01, 0x40, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s, z1.s }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0x55, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1w { z20.s, z21.s }, pn13/z, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1w { z22.s, z23.s }, pn11/z, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x5f, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1w { z30.s, z31.s }, pn15/z, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x01, 0xc0, 0x00, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s - z3.s }, pn8/z, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x55, 0xd5, 0x15, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1w { z20.s - z23.s }, pn13/z, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb5, 0xcd, 0x08, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1w { z20.s - z23.s }, pn11/z, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xfd, 0xdf, 0x1f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1w { z28.s - z31.s }, pn15/z, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x01, 0xc0, 0x40, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1w { z0.s - z3.s }, pn8/z, [x0]" + + - + input: + bytes: [ 0x55, 0xd5, 0x45, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1w { z20.s - z23.s }, pn13/z, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb5, 0xcd, 0x48, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1w { z20.s - z23.s }, pn11/z, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfd, 0xdf, 0x4f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ldnt1w { z28.s - z31.s }, pn15/z, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/orqv.s.yaml b/tests/MC/AArch64/SVE2p1/orqv.s.yaml new file mode 100644 index 0000000000..221cdaf523 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/orqv.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x5c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "orqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0x35, 0x5c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "orqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0x2d, 0x5c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "orqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0x3f, 0x5c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "orqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0x20, 0x9c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "orqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0x35, 0x9c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "orqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0x2d, 0x9c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "orqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0x3f, 0x9c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "orqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0x20, 0xdc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "orqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0x35, 0xdc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "orqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0x2d, 0xdc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "orqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0x3f, 0xdc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "orqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0x20, 0x1c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "orqv v0.16b, p0, z0.b" + + - + input: + bytes: [ 0x55, 0x35, 0x1c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "orqv v21.16b, p5, z10.b" + + - + input: + bytes: [ 0xb7, 0x2d, 0x1c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "orqv v23.16b, p3, z13.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x1c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "orqv v31.16b, p7, z31.b" + + - + input: + bytes: [ 0x00, 0x20, 0x5c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "orqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0x35, 0x5c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "orqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0x2d, 0x5c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "orqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0x3f, 0x5c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "orqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0x20, 0x9c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "orqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0x35, 0x9c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "orqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0x2d, 0x9c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "orqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0x3f, 0x9c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "orqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0x20, 0xdc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "orqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0x35, 0xdc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "orqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0x2d, 0xdc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "orqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0x3f, 0xdc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "orqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0x20, 0x1c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "orqv v0.16b, p0, z0.b" + + - + input: + bytes: [ 0x55, 0x35, 0x1c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "orqv v21.16b, p5, z10.b" + + - + input: + bytes: [ 0xb7, 0x2d, 0x1c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "orqv v23.16b, p3, z13.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x1c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "orqv v31.16b, p7, z31.b" diff --git a/tests/MC/AArch64/SVE2p1/pext.s.yaml b/tests/MC/AArch64/SVE2p1/pext.s.yaml new file mode 100644 index 0000000000..96e61a9287 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/pext.s.yaml @@ -0,0 +1,600 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x70, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext p0.h, pn8[0]" + + - + input: + bytes: [ 0x55, 0x71, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext p5.h, pn10[1]" + + - + input: + bytes: [ 0xb7, 0x71, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext p7.h, pn13[1]" + + - + input: + bytes: [ 0xff, 0x73, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext p15.h, pn15[3]" + + - + input: + bytes: [ 0x10, 0x70, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext p0.s, pn8[0]" + + - + input: + bytes: [ 0x55, 0x71, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext p5.s, pn10[1]" + + - + input: + bytes: [ 0xb7, 0x71, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext p7.s, pn13[1]" + + - + input: + bytes: [ 0xff, 0x73, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext p15.s, pn15[3]" + + - + input: + bytes: [ 0x10, 0x70, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext p0.d, pn8[0]" + + - + input: + bytes: [ 0x55, 0x71, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext p5.d, pn10[1]" + + - + input: + bytes: [ 0xb7, 0x71, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext p7.d, pn13[1]" + + - + input: + bytes: [ 0xff, 0x73, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext p15.d, pn15[3]" + + - + input: + bytes: [ 0x10, 0x70, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext p0.b, pn8[0]" + + - + input: + bytes: [ 0x55, 0x71, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext p5.b, pn10[1]" + + - + input: + bytes: [ 0xb7, 0x71, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext p7.b, pn13[1]" + + - + input: + bytes: [ 0xff, 0x73, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext p15.b, pn15[3]" + + - + input: + bytes: [ 0x10, 0x74, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext { p0.h, p1.h }, pn8[0]" + + - + input: + bytes: [ 0x55, 0x75, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext { p5.h, p6.h }, pn10[1]" + + - + input: + bytes: [ 0xb7, 0x75, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext { p7.h, p8.h }, pn13[1]" + + - + input: + bytes: [ 0xff, 0x75, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext { p15.h, p0.h }, pn15[1]" + + - + input: + bytes: [ 0x10, 0x74, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext { p0.s, p1.s }, pn8[0]" + + - + input: + bytes: [ 0x55, 0x75, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext { p5.s, p6.s }, pn10[1]" + + - + input: + bytes: [ 0xb7, 0x75, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext { p7.s, p8.s }, pn13[1]" + + - + input: + bytes: [ 0xff, 0x75, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext { p15.s, p0.s }, pn15[1]" + + - + input: + bytes: [ 0x10, 0x74, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext { p0.d, p1.d }, pn8[0]" + + - + input: + bytes: [ 0x55, 0x75, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext { p5.d, p6.d }, pn10[1]" + + - + input: + bytes: [ 0xb7, 0x75, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext { p7.d, p8.d }, pn13[1]" + + - + input: + bytes: [ 0xff, 0x75, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext { p15.d, p0.d }, pn15[1]" + + - + input: + bytes: [ 0xb7, 0x75, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext { p7.b, p8.b }, pn13[1]" + + - + input: + bytes: [ 0xff, 0x75, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "pext { p15.b, p0.b }, pn15[1]" + + - + input: + bytes: [ 0x10, 0x70, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext p0.h, pn8[0]" + + - + input: + bytes: [ 0x55, 0x71, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext p5.h, pn10[1]" + + - + input: + bytes: [ 0xb7, 0x71, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext p7.h, pn13[1]" + + - + input: + bytes: [ 0xff, 0x73, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext p15.h, pn15[3]" + + - + input: + bytes: [ 0x10, 0x70, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext p0.s, pn8[0]" + + - + input: + bytes: [ 0x55, 0x71, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext p5.s, pn10[1]" + + - + input: + bytes: [ 0xb7, 0x71, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext p7.s, pn13[1]" + + - + input: + bytes: [ 0xff, 0x73, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext p15.s, pn15[3]" + + - + input: + bytes: [ 0x10, 0x70, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext p0.d, pn8[0]" + + - + input: + bytes: [ 0x55, 0x71, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext p5.d, pn10[1]" + + - + input: + bytes: [ 0xb7, 0x71, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext p7.d, pn13[1]" + + - + input: + bytes: [ 0xff, 0x73, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext p15.d, pn15[3]" + + - + input: + bytes: [ 0x10, 0x70, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext p0.b, pn8[0]" + + - + input: + bytes: [ 0x55, 0x71, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext p5.b, pn10[1]" + + - + input: + bytes: [ 0xb7, 0x71, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext p7.b, pn13[1]" + + - + input: + bytes: [ 0xff, 0x73, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext p15.b, pn15[3]" + + - + input: + bytes: [ 0x10, 0x74, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext { p0.h, p1.h }, pn8[0]" + + - + input: + bytes: [ 0x55, 0x75, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext { p5.h, p6.h }, pn10[1]" + + - + input: + bytes: [ 0xb7, 0x75, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext { p7.h, p8.h }, pn13[1]" + + - + input: + bytes: [ 0xff, 0x75, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext { p15.h, p0.h }, pn15[1]" + + - + input: + bytes: [ 0x10, 0x74, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext { p0.s, p1.s }, pn8[0]" + + - + input: + bytes: [ 0x55, 0x75, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext { p5.s, p6.s }, pn10[1]" + + - + input: + bytes: [ 0xb7, 0x75, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext { p7.s, p8.s }, pn13[1]" + + - + input: + bytes: [ 0xff, 0x75, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext { p15.s, p0.s }, pn15[1]" + + - + input: + bytes: [ 0x10, 0x74, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext { p0.d, p1.d }, pn8[0]" + + - + input: + bytes: [ 0x55, 0x75, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext { p5.d, p6.d }, pn10[1]" + + - + input: + bytes: [ 0xb7, 0x75, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext { p7.d, p8.d }, pn13[1]" + + - + input: + bytes: [ 0xff, 0x75, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext { p15.d, p0.d }, pn15[1]" + + - + input: + bytes: [ 0xb7, 0x75, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext { p7.b, p8.b }, pn13[1]" + + - + input: + bytes: [ 0xff, 0x75, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pext { p15.b, p0.b }, pn15[1]" diff --git a/tests/MC/AArch64/SVE2p1/pmov.s.yaml b/tests/MC/AArch64/SVE2p1/pmov.s.yaml new file mode 100644 index 0000000000..69c9919d46 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/pmov.s.yaml @@ -0,0 +1,800 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x38, 0x2c, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p0.h, z0[0]" + + - + input: + bytes: [ 0x00, 0x38, 0x2c, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p0.h, z0[0]" + + - + input: + bytes: [ 0x45, 0x39, 0x2c, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p5.h, z10[0]" + + - + input: + bytes: [ 0xa7, 0x39, 0x2c, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p7.h, z13[0]" + + - + input: + bytes: [ 0xef, 0x3b, 0x2e, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p15.h, z31[1]" + + - + input: + bytes: [ 0x00, 0x38, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p0.s, z0[0]" + + - + input: + bytes: [ 0x00, 0x38, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p0.s, z0[0]" + + - + input: + bytes: [ 0x45, 0x39, 0x6c, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p5.s, z10[2]" + + - + input: + bytes: [ 0xa7, 0x39, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p7.s, z13[0]" + + - + input: + bytes: [ 0xef, 0x3b, 0x6e, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p15.s, z31[3]" + + - + input: + bytes: [ 0x00, 0x38, 0xa8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p0.d, z0[0]" + + - + input: + bytes: [ 0x00, 0x38, 0xa8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p0.d, z0[0]" + + - + input: + bytes: [ 0x45, 0x39, 0xec, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p5.d, z10[6]" + + - + input: + bytes: [ 0xa7, 0x39, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p7.d, z13[4]" + + - + input: + bytes: [ 0xef, 0x3b, 0xee, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p15.d, z31[7]" + + - + input: + bytes: [ 0x00, 0x38, 0x2a, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p0.b, z0" + + - + input: + bytes: [ 0x45, 0x39, 0x2a, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p5.b, z10" + + - + input: + bytes: [ 0xa7, 0x39, 0x2a, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p7.b, z13" + + - + input: + bytes: [ 0xef, 0x3b, 0x2a, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p15.b, z31" + + - + input: + bytes: [ 0x00, 0x38, 0x2a, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov p0.b, z0" + + - + input: + bytes: [ 0x00, 0x38, 0x2d, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z0[0], p0.h" + + - + input: + bytes: [ 0x00, 0x38, 0x2d, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z0[0], p0.h" + + - + input: + bytes: [ 0x55, 0x39, 0x2d, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z21[0], p10.h" + + - + input: + bytes: [ 0xb7, 0x39, 0x2d, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z23[0], p13.h" + + - + input: + bytes: [ 0xff, 0x39, 0x2f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z31[1], p15.h" + + - + input: + bytes: [ 0x00, 0x38, 0x69, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z0[0], p0.s" + + - + input: + bytes: [ 0x00, 0x38, 0x69, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z0[0], p0.s" + + - + input: + bytes: [ 0x55, 0x39, 0x6d, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z21[2], p10.s" + + - + input: + bytes: [ 0xb7, 0x39, 0x69, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z23[0], p13.s" + + - + input: + bytes: [ 0xff, 0x39, 0x6f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z31[3], p15.s" + + - + input: + bytes: [ 0x00, 0x38, 0xa9, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z0[0], p0.d" + + - + input: + bytes: [ 0x00, 0x38, 0xa9, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z0[0], p0.d" + + - + input: + bytes: [ 0x55, 0x39, 0xed, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z21[6], p10.d" + + - + input: + bytes: [ 0xb7, 0x39, 0xe9, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z23[4], p13.d" + + - + input: + bytes: [ 0xff, 0x39, 0xef, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z31[7], p15.d" + + - + input: + bytes: [ 0x00, 0x38, 0x2b, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z0, p0.b" + + - + input: + bytes: [ 0x55, 0x39, 0x2b, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z21, p10.b" + + - + input: + bytes: [ 0xb7, 0x39, 0x2b, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z23, p13.b" + + - + input: + bytes: [ 0xff, 0x39, 0x2b, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z31, p15.b" + + - + input: + bytes: [ 0x00, 0x38, 0x2b, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "pmov z0, p0.b" + + - + input: + bytes: [ 0x00, 0x38, 0x2c, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p0.h, z0[0]" + + - + input: + bytes: [ 0x00, 0x38, 0x2c, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p0.h, z0[0]" + + - + input: + bytes: [ 0x45, 0x39, 0x2c, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p5.h, z10[0]" + + - + input: + bytes: [ 0xa7, 0x39, 0x2c, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p7.h, z13[0]" + + - + input: + bytes: [ 0xef, 0x3b, 0x2e, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p15.h, z31[1]" + + - + input: + bytes: [ 0x00, 0x38, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p0.s, z0[0]" + + - + input: + bytes: [ 0x00, 0x38, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p0.s, z0[0]" + + - + input: + bytes: [ 0x45, 0x39, 0x6c, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p5.s, z10[2]" + + - + input: + bytes: [ 0xa7, 0x39, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p7.s, z13[0]" + + - + input: + bytes: [ 0xef, 0x3b, 0x6e, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p15.s, z31[3]" + + - + input: + bytes: [ 0x00, 0x38, 0xa8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p0.d, z0[0]" + + - + input: + bytes: [ 0x00, 0x38, 0xa8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p0.d, z0[0]" + + - + input: + bytes: [ 0x45, 0x39, 0xec, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p5.d, z10[6]" + + - + input: + bytes: [ 0xa7, 0x39, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p7.d, z13[4]" + + - + input: + bytes: [ 0xef, 0x3b, 0xee, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p15.d, z31[7]" + + - + input: + bytes: [ 0x00, 0x38, 0x2a, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p0.b, z0" + + - + input: + bytes: [ 0x45, 0x39, 0x2a, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p5.b, z10" + + - + input: + bytes: [ 0xa7, 0x39, 0x2a, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p7.b, z13" + + - + input: + bytes: [ 0xef, 0x3b, 0x2a, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p15.b, z31" + + - + input: + bytes: [ 0x00, 0x38, 0x2a, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov p0.b, z0" + + - + input: + bytes: [ 0x00, 0x38, 0x2d, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z0[0], p0.h" + + - + input: + bytes: [ 0x00, 0x38, 0x2d, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z0[0], p0.h" + + - + input: + bytes: [ 0x55, 0x39, 0x2d, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z21[0], p10.h" + + - + input: + bytes: [ 0xb7, 0x39, 0x2d, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z23[0], p13.h" + + - + input: + bytes: [ 0xff, 0x39, 0x2f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z31[1], p15.h" + + - + input: + bytes: [ 0x00, 0x38, 0x69, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z0[0], p0.s" + + - + input: + bytes: [ 0x00, 0x38, 0x69, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z0[0], p0.s" + + - + input: + bytes: [ 0x55, 0x39, 0x6d, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z21[2], p10.s" + + - + input: + bytes: [ 0xb7, 0x39, 0x69, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z23[0], p13.s" + + - + input: + bytes: [ 0xff, 0x39, 0x6f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z31[3], p15.s" + + - + input: + bytes: [ 0x00, 0x38, 0xa9, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z0[0], p0.d" + + - + input: + bytes: [ 0x00, 0x38, 0xa9, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z0[0], p0.d" + + - + input: + bytes: [ 0x55, 0x39, 0xed, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z21[6], p10.d" + + - + input: + bytes: [ 0xb7, 0x39, 0xe9, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z23[4], p13.d" + + - + input: + bytes: [ 0xff, 0x39, 0xef, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z31[7], p15.d" + + - + input: + bytes: [ 0x00, 0x38, 0x2b, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z0, p0.b" + + - + input: + bytes: [ 0x55, 0x39, 0x2b, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z21, p10.b" + + - + input: + bytes: [ 0xb7, 0x39, 0x2b, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z23, p13.b" + + - + input: + bytes: [ 0xff, 0x39, 0x2b, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z31, p15.b" + + - + input: + bytes: [ 0x00, 0x38, 0x2b, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "pmov z0, p0.b" diff --git a/tests/MC/AArch64/SVE2p1/ptrue.s.yaml b/tests/MC/AArch64/SVE2p1/ptrue.s.yaml new file mode 100644 index 0000000000..9b3ca34d6e --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/ptrue.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x78, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ptrue pn8.h" + + - + input: + bytes: [ 0x15, 0x78, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ptrue pn13.h" + + - + input: + bytes: [ 0x17, 0x78, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ptrue pn15.h" + + - + input: + bytes: [ 0x11, 0x78, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ptrue pn9.h" + + - + input: + bytes: [ 0x10, 0x78, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ptrue pn8.s" + + - + input: + bytes: [ 0x15, 0x78, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ptrue pn13.s" + + - + input: + bytes: [ 0x17, 0x78, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ptrue pn15.s" + + - + input: + bytes: [ 0x11, 0x78, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ptrue pn9.s" + + - + input: + bytes: [ 0x10, 0x78, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ptrue pn8.d" + + - + input: + bytes: [ 0x15, 0x78, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ptrue pn13.d" + + - + input: + bytes: [ 0x17, 0x78, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ptrue pn15.d" + + - + input: + bytes: [ 0x11, 0x78, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ptrue pn9.d" + + - + input: + bytes: [ 0x10, 0x78, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ptrue pn8.b" + + - + input: + bytes: [ 0x15, 0x78, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ptrue pn13.b" + + - + input: + bytes: [ 0x17, 0x78, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ptrue pn15.b" + + - + input: + bytes: [ 0x11, 0x78, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "ptrue pn9.b" + + - + input: + bytes: [ 0x10, 0x78, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ptrue pn8.h" + + - + input: + bytes: [ 0x15, 0x78, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ptrue pn13.h" + + - + input: + bytes: [ 0x17, 0x78, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ptrue pn15.h" + + - + input: + bytes: [ 0x11, 0x78, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ptrue pn9.h" + + - + input: + bytes: [ 0x10, 0x78, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ptrue pn8.s" + + - + input: + bytes: [ 0x15, 0x78, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ptrue pn13.s" + + - + input: + bytes: [ 0x17, 0x78, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ptrue pn15.s" + + - + input: + bytes: [ 0x11, 0x78, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ptrue pn9.s" + + - + input: + bytes: [ 0x10, 0x78, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ptrue pn8.d" + + - + input: + bytes: [ 0x15, 0x78, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ptrue pn13.d" + + - + input: + bytes: [ 0x17, 0x78, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ptrue pn15.d" + + - + input: + bytes: [ 0x11, 0x78, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ptrue pn9.d" + + - + input: + bytes: [ 0x10, 0x78, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ptrue pn8.b" + + - + input: + bytes: [ 0x15, 0x78, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ptrue pn13.b" + + - + input: + bytes: [ 0x17, 0x78, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ptrue pn15.b" + + - + input: + bytes: [ 0x11, 0x78, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "ptrue pn9.b" diff --git a/tests/MC/AArch64/SVE2p1/sdot.s.yaml b/tests/MC/AArch64/SVE2p1/sdot.s.yaml new file mode 100644 index 0000000000..f7d9209c76 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/sdot.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0xc9, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sdot z23.s, z13.h, z0.h[1]" + + - + input: + bytes: [ 0x00, 0xc8, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sdot z0.s, z0.h, z0.h[0]" + + - + input: + bytes: [ 0x55, 0xc9, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sdot z21.s, z10.h, z5.h[2]" + + - + input: + bytes: [ 0xb7, 0xc9, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sdot z23.s, z13.h, z0.h[1]" + + - + input: + bytes: [ 0xff, 0xcb, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sdot z31.s, z31.h, z7.h[3]" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0xc9, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sdot z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0x00, 0xc8, 0x00, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sdot z0.s, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xc9, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sdot z21.s, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xc9, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sdot z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xcb, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sdot z31.s, z31.h, z31.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0xc9, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sdot z23.s, z13.h, z0.h[1]" + + - + input: + bytes: [ 0x00, 0xc8, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sdot z0.s, z0.h, z0.h[0]" + + - + input: + bytes: [ 0x55, 0xc9, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sdot z21.s, z10.h, z5.h[2]" + + - + input: + bytes: [ 0xb7, 0xc9, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sdot z23.s, z13.h, z0.h[1]" + + - + input: + bytes: [ 0xff, 0xcb, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sdot z31.s, z31.h, z7.h[3]" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0xc9, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sdot z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0x00, 0xc8, 0x00, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sdot z0.s, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xc9, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sdot z21.s, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xc9, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sdot z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xcb, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sdot z31.s, z31.h, z31.h" diff --git a/tests/MC/AArch64/SVE2p1/smaxqv.s.yaml b/tests/MC/AArch64/SVE2p1/smaxqv.s.yaml new file mode 100644 index 0000000000..1e4579d96d --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/smaxqv.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x4c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "smaxqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0x35, 0x4c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "smaxqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0x2d, 0x4c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "smaxqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0x3f, 0x4c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "smaxqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0x20, 0x8c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "smaxqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0x35, 0x8c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "smaxqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0x2d, 0x8c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "smaxqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0x3f, 0x8c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "smaxqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0x20, 0xcc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "smaxqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0x35, 0xcc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "smaxqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0x2d, 0xcc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "smaxqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0x3f, 0xcc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "smaxqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0x20, 0x0c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "smaxqv v0.16b, p0, z0.b" + + - + input: + bytes: [ 0x55, 0x35, 0x0c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "smaxqv v21.16b, p5, z10.b" + + - + input: + bytes: [ 0xb7, 0x2d, 0x0c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "smaxqv v23.16b, p3, z13.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x0c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "smaxqv v31.16b, p7, z31.b" + + - + input: + bytes: [ 0x00, 0x20, 0x4c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "smaxqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0x35, 0x4c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "smaxqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0x2d, 0x4c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "smaxqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0x3f, 0x4c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "smaxqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0x20, 0x8c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "smaxqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0x35, 0x8c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "smaxqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0x2d, 0x8c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "smaxqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0x3f, 0x8c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "smaxqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0x20, 0xcc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "smaxqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0x35, 0xcc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "smaxqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0x2d, 0xcc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "smaxqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0x3f, 0xcc, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "smaxqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0x20, 0x0c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "smaxqv v0.16b, p0, z0.b" + + - + input: + bytes: [ 0x55, 0x35, 0x0c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "smaxqv v21.16b, p5, z10.b" + + - + input: + bytes: [ 0xb7, 0x2d, 0x0c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "smaxqv v23.16b, p3, z13.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x0c, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "smaxqv v31.16b, p7, z31.b" diff --git a/tests/MC/AArch64/SVE2p1/sminqv.s.yaml b/tests/MC/AArch64/SVE2p1/sminqv.s.yaml new file mode 100644 index 0000000000..88f4db2a26 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/sminqv.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x4e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "sminqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0x35, 0x4e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "sminqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0x2d, 0x4e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "sminqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0x3f, 0x4e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "sminqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0x20, 0x8e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "sminqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0x35, 0x8e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "sminqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0x2d, 0x8e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "sminqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0x3f, 0x8e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "sminqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0x20, 0xce, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "sminqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0x35, 0xce, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "sminqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0x2d, 0xce, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "sminqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0x3f, 0xce, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "sminqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0x20, 0x0e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "sminqv v0.16b, p0, z0.b" + + - + input: + bytes: [ 0x55, 0x35, 0x0e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "sminqv v21.16b, p5, z10.b" + + - + input: + bytes: [ 0xb7, 0x2d, 0x0e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "sminqv v23.16b, p3, z13.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x0e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "sminqv v31.16b, p7, z31.b" + + - + input: + bytes: [ 0x00, 0x20, 0x4e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sminqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0x35, 0x4e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sminqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0x2d, 0x4e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sminqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0x3f, 0x4e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sminqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0x20, 0x8e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sminqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0x35, 0x8e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sminqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0x2d, 0x8e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sminqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0x3f, 0x8e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sminqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0x20, 0xce, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sminqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0x35, 0xce, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sminqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0x2d, 0xce, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sminqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0x3f, 0xce, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sminqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0x20, 0x0e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sminqv v0.16b, p0, z0.b" + + - + input: + bytes: [ 0x55, 0x35, 0x0e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sminqv v21.16b, p5, z10.b" + + - + input: + bytes: [ 0xb7, 0x2d, 0x0e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sminqv v23.16b, p3, z13.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x0e, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sminqv v31.16b, p7, z31.b" diff --git a/tests/MC/AArch64/SVE2p1/sqcvtn.s.yaml b/tests/MC/AArch64/SVE2p1/sqcvtn.s.yaml new file mode 100644 index 0000000000..41c3d38eb2 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/sqcvtn.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtn z0.h, { z0.s, z1.s }" + + - + input: + bytes: [ 0x55, 0x41, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtn z21.h, { z10.s, z11.s }" + + - + input: + bytes: [ 0x97, 0x41, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtn z23.h, { z12.s, z13.s }" + + - + input: + bytes: [ 0xdf, 0x43, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtn z31.h, { z30.s, z31.s }" + + - + input: + bytes: [ 0x00, 0x40, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sqcvtn z0.h, { z0.s, z1.s }" + + - + input: + bytes: [ 0x55, 0x41, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sqcvtn z21.h, { z10.s, z11.s }" + + - + input: + bytes: [ 0x97, 0x41, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sqcvtn z23.h, { z12.s, z13.s }" + + - + input: + bytes: [ 0xdf, 0x43, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sqcvtn z31.h, { z30.s, z31.s }" diff --git a/tests/MC/AArch64/SVE2p1/sqcvtun.s.yaml b/tests/MC/AArch64/SVE2p1/sqcvtun.s.yaml new file mode 100644 index 0000000000..1d4ab6d7b6 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/sqcvtun.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x50, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtun z0.h, { z0.s, z1.s }" + + - + input: + bytes: [ 0x55, 0x51, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtun z21.h, { z10.s, z11.s }" + + - + input: + bytes: [ 0x97, 0x51, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtun z23.h, { z12.s, z13.s }" + + - + input: + bytes: [ 0xdf, 0x53, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqcvtun z31.h, { z30.s, z31.s }" + + - + input: + bytes: [ 0x00, 0x50, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sqcvtun z0.h, { z0.s, z1.s }" + + - + input: + bytes: [ 0x55, 0x51, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sqcvtun z21.h, { z10.s, z11.s }" + + - + input: + bytes: [ 0x97, 0x51, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sqcvtun z23.h, { z12.s, z13.s }" + + - + input: + bytes: [ 0xdf, 0x53, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sqcvtun z31.h, { z30.s, z31.s }" diff --git a/tests/MC/AArch64/SVE2p1/sqrshrn.s.yaml b/tests/MC/AArch64/SVE2p1/sqrshrn.s.yaml new file mode 100644 index 0000000000..fd8a679d3e --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/sqrshrn.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x28, 0xb0, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrn z0.h, { z0.s, z1.s }, #16" + + - + input: + bytes: [ 0x55, 0x29, 0xb5, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrn z21.h, { z10.s, z11.s }, #11" + + - + input: + bytes: [ 0x97, 0x29, 0xb8, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrn z23.h, { z12.s, z13.s }, #8" + + - + input: + bytes: [ 0xdf, 0x2b, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrn z31.h, { z30.s, z31.s }, #1" + + - + input: + bytes: [ 0x00, 0x28, 0xb0, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sqrshrn z0.h, { z0.s, z1.s }, #16" + + - + input: + bytes: [ 0x55, 0x29, 0xb5, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sqrshrn z21.h, { z10.s, z11.s }, #11" + + - + input: + bytes: [ 0x97, 0x29, 0xb8, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sqrshrn z23.h, { z12.s, z13.s }, #8" + + - + input: + bytes: [ 0xdf, 0x2b, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sqrshrn z31.h, { z30.s, z31.s }, #1" diff --git a/tests/MC/AArch64/SVE2p1/sqrshrun.s.yaml b/tests/MC/AArch64/SVE2p1/sqrshrun.s.yaml new file mode 100644 index 0000000000..362ff82f36 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/sqrshrun.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x08, 0xb0, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrun z0.h, { z0.s, z1.s }, #16" + + - + input: + bytes: [ 0x55, 0x09, 0xb5, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrun z21.h, { z10.s, z11.s }, #11" + + - + input: + bytes: [ 0x97, 0x09, 0xb8, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrun z23.h, { z12.s, z13.s }, #8" + + - + input: + bytes: [ 0xdf, 0x0b, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "sqrshrun z31.h, { z30.s, z31.s }, #1" + + - + input: + bytes: [ 0x00, 0x08, 0xb0, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sqrshrun z0.h, { z0.s, z1.s }, #16" + + - + input: + bytes: [ 0x55, 0x09, 0xb5, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sqrshrun z21.h, { z10.s, z11.s }, #11" + + - + input: + bytes: [ 0x97, 0x09, 0xb8, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sqrshrun z23.h, { z12.s, z13.s }, #8" + + - + input: + bytes: [ 0xdf, 0x0b, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "sqrshrun z31.h, { z30.s, z31.s }, #1" diff --git a/tests/MC/AArch64/SVE2p1/st1b.s.yaml b/tests/MC/AArch64/SVE2p1/st1b.s.yaml new file mode 100644 index 0000000000..c445372492 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/st1b.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z0.b, z1.b }, pn8, [x0, x0]" + + - + input: + bytes: [ 0x54, 0x15, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z20.b, z21.b }, pn13, [x10, x21]" + + - + input: + bytes: [ 0xb6, 0x0d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z22.b, z23.b }, pn11, [x13, x8]" + + - + input: + bytes: [ 0xfe, 0x1f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z30.b, z31.b }, pn15, [sp, xzr]" + + - + input: + bytes: [ 0x00, 0x00, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z0.b, z1.b }, pn8, [x0]" + + - + input: + bytes: [ 0x54, 0x15, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z20.b, z21.b }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb6, 0x0d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z22.b, z23.b }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xfe, 0x1f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z30.b, z31.b }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0x80, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z0.b - z3.b }, pn8, [x0, x0]" + + - + input: + bytes: [ 0x54, 0x95, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z20.b - z23.b }, pn13, [x10, x21]" + + - + input: + bytes: [ 0xb4, 0x8d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z20.b - z23.b }, pn11, [x13, x8]" + + - + input: + bytes: [ 0xfc, 0x9f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z28.b - z31.b }, pn15, [sp, xzr]" + + - + input: + bytes: [ 0x00, 0x80, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z0.b - z3.b }, pn8, [x0]" + + - + input: + bytes: [ 0x54, 0x95, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z20.b - z23.b }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb4, 0x8d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z20.b - z23.b }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfc, 0x9f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1b { z28.b - z31.b }, pn15, [sp, #-4, mul vl]" + + - + input: + bytes: [ 0x00, 0x00, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1b { z0.b, z1.b }, pn8, [x0, x0]" + + - + input: + bytes: [ 0x54, 0x15, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1b { z20.b, z21.b }, pn13, [x10, x21]" + + - + input: + bytes: [ 0xb6, 0x0d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1b { z22.b, z23.b }, pn11, [x13, x8]" + + - + input: + bytes: [ 0xfe, 0x1f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1b { z30.b, z31.b }, pn15, [sp, xzr]" + + - + input: + bytes: [ 0x00, 0x00, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1b { z0.b, z1.b }, pn8, [x0]" + + - + input: + bytes: [ 0x54, 0x15, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1b { z20.b, z21.b }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb6, 0x0d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1b { z22.b, z23.b }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xfe, 0x1f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1b { z30.b, z31.b }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0x80, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1b { z0.b - z3.b }, pn8, [x0, x0]" + + - + input: + bytes: [ 0x54, 0x95, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1b { z20.b - z23.b }, pn13, [x10, x21]" + + - + input: + bytes: [ 0xb4, 0x8d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1b { z20.b - z23.b }, pn11, [x13, x8]" + + - + input: + bytes: [ 0xfc, 0x9f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1b { z28.b - z31.b }, pn15, [sp, xzr]" + + - + input: + bytes: [ 0x00, 0x80, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1b { z0.b - z3.b }, pn8, [x0]" + + - + input: + bytes: [ 0x54, 0x95, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1b { z20.b - z23.b }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb4, 0x8d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1b { z20.b - z23.b }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfc, 0x9f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1b { z28.b - z31.b }, pn15, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/st1d.s.yaml b/tests/MC/AArch64/SVE2p1/st1d.s.yaml new file mode 100644 index 0000000000..fbb0af06b6 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/st1d.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x60, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z0.d, z1.d }, pn8, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x54, 0x75, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z20.d, z21.d }, pn13, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb6, 0x6d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z22.d, z23.d }, pn11, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xfe, 0x7f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z30.d, z31.d }, pn15, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z0.d, z1.d }, pn8, [x0]" + + - + input: + bytes: [ 0x54, 0x75, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z20.d, z21.d }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb6, 0x6d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z22.d, z23.d }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xfe, 0x7f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z30.d, z31.d }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z0.d - z3.d }, pn8, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x54, 0xf5, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z20.d - z23.d }, pn13, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb4, 0xed, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z20.d - z23.d }, pn11, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xfc, 0xff, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z28.d - z31.d }, pn15, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z0.d - z3.d }, pn8, [x0]" + + - + input: + bytes: [ 0x54, 0xf5, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z20.d - z23.d }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb4, 0xed, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z20.d - z23.d }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfc, 0xff, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1d { z28.d - z31.d }, pn15, [sp, #-4, mul vl]" + + - + input: + bytes: [ 0x00, 0x60, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z0.d, z1.d }, pn8, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x54, 0x75, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z20.d, z21.d }, pn13, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb6, 0x6d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z22.d, z23.d }, pn11, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xfe, 0x7f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z30.d, z31.d }, pn15, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z0.d, z1.d }, pn8, [x0]" + + - + input: + bytes: [ 0x54, 0x75, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z20.d, z21.d }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb6, 0x6d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z22.d, z23.d }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xfe, 0x7f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z30.d, z31.d }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z0.d - z3.d }, pn8, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x54, 0xf5, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z20.d - z23.d }, pn13, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb4, 0xed, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z20.d - z23.d }, pn11, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xfc, 0xff, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z28.d - z31.d }, pn15, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z0.d - z3.d }, pn8, [x0]" + + - + input: + bytes: [ 0x54, 0xf5, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z20.d - z23.d }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb4, 0xed, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z20.d - z23.d }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfc, 0xff, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z28.d - z31.d }, pn15, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/st1d_q.s.yaml b/tests/MC/AArch64/SVE2p1/st1d_q.s.yaml new file mode 100644 index 0000000000..1ff939d438 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/st1d_q.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0xc0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z0.q }, p0, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x55, 0x55, 0xd5, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z21.q }, p5, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb7, 0x4d, 0xc8, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z23.q }, p3, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xb7, 0x4d, 0xc8, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z23.q }, p3, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0x00, 0xe0, 0xc0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z0.q }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0xc0, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z0.q }, p0, [x0]" + + - + input: + bytes: [ 0x55, 0xf5, 0xc5, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z21.q }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xb7, 0xed, 0xc8, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z23.q }, p3, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0xcf, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z31.q }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0xcf, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1d { z31.q }, p7, [sp, #-1, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/st1h.s.yaml b/tests/MC/AArch64/SVE2p1/st1h.s.yaml new file mode 100644 index 0000000000..444b780f68 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/st1h.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z0.h, z1.h }, pn8, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x54, 0x35, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z20.h, z21.h }, pn13, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb6, 0x2d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z22.h, z23.h }, pn11, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xfe, 0x3f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z30.h, z31.h }, pn15, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x00, 0x20, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z0.h, z1.h }, pn8, [x0]" + + - + input: + bytes: [ 0x54, 0x35, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z20.h, z21.h }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb6, 0x2d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z22.h, z23.h }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xfe, 0x3f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z30.h, z31.h }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0xa0, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z0.h - z3.h }, pn8, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x54, 0xb5, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z20.h - z23.h }, pn13, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb4, 0xad, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z20.h - z23.h }, pn11, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xfc, 0xbf, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z28.h - z31.h }, pn15, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x00, 0xa0, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z0.h - z3.h }, pn8, [x0]" + + - + input: + bytes: [ 0x54, 0xb5, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z20.h - z23.h }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb4, 0xad, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z20.h - z23.h }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfc, 0xbf, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1h { z28.h - z31.h }, pn15, [sp, #-4, mul vl]" + + - + input: + bytes: [ 0x00, 0x20, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1h { z0.h, z1.h }, pn8, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x54, 0x35, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1h { z20.h, z21.h }, pn13, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb6, 0x2d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1h { z22.h, z23.h }, pn11, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xfe, 0x3f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1h { z30.h, z31.h }, pn15, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x00, 0x20, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1h { z0.h, z1.h }, pn8, [x0]" + + - + input: + bytes: [ 0x54, 0x35, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1h { z20.h, z21.h }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb6, 0x2d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1h { z22.h, z23.h }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xfe, 0x3f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1h { z30.h, z31.h }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0xa0, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1h { z0.h - z3.h }, pn8, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x54, 0xb5, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1h { z20.h - z23.h }, pn13, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb4, 0xad, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1h { z20.h - z23.h }, pn11, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xfc, 0xbf, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1h { z28.h - z31.h }, pn15, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x00, 0xa0, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1h { z0.h - z3.h }, pn8, [x0]" + + - + input: + bytes: [ 0x54, 0xb5, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1h { z20.h - z23.h }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb4, 0xad, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1h { z20.h - z23.h }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfc, 0xbf, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1h { z28.h - z31.h }, pn15, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/st1q.s.yaml b/tests/MC/AArch64/SVE2p1/st1q.s.yaml new file mode 100644 index 0000000000..f8c9a90065 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/st1q.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x20, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1q { z0.q }, p0, [z0.d, x0]" + + - + input: + bytes: [ 0x55, 0x35, 0x35, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1q { z21.q }, p5, [z10.d, x21]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x28, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1q { z23.q }, p3, [z13.d, x8]" + + - + input: + bytes: [ 0xff, 0x3f, 0x3f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1q { z31.q }, p7, [z31.d]" diff --git a/tests/MC/AArch64/SVE2p1/st1w.s.yaml b/tests/MC/AArch64/SVE2p1/st1w.s.yaml new file mode 100644 index 0000000000..99f51f46db --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/st1w.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z0.s, z1.s }, pn8, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x54, 0x55, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z20.s, z21.s }, pn13, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb6, 0x4d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z22.s, z23.s }, pn11, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xfe, 0x5f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z30.s, z31.s }, pn15, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x00, 0x40, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z0.s, z1.s }, pn8, [x0]" + + - + input: + bytes: [ 0x54, 0x55, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z20.s, z21.s }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb6, 0x4d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z22.s, z23.s }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xfe, 0x5f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z30.s, z31.s }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z0.s - z3.s }, pn8, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x54, 0xd5, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z20.s - z23.s }, pn13, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb4, 0xcd, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z20.s - z23.s }, pn11, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xfc, 0xdf, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z28.s - z31.s }, pn15, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x00, 0xc0, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z0.s - z3.s }, pn8, [x0]" + + - + input: + bytes: [ 0x54, 0xd5, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z20.s - z23.s }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb4, 0xcd, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z20.s - z23.s }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfc, 0xdf, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "st1w { z28.s - z31.s }, pn15, [sp, #-4, mul vl]" + + - + input: + bytes: [ 0x00, 0x40, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z0.s, z1.s }, pn8, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x54, 0x55, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z20.s, z21.s }, pn13, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb6, 0x4d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z22.s, z23.s }, pn11, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xfe, 0x5f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z30.s, z31.s }, pn15, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x00, 0x40, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z0.s, z1.s }, pn8, [x0]" + + - + input: + bytes: [ 0x54, 0x55, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z20.s, z21.s }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb6, 0x4d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z22.s, z23.s }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xfe, 0x5f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z30.s, z31.s }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0xc0, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z0.s - z3.s }, pn8, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x54, 0xd5, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z20.s - z23.s }, pn13, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb4, 0xcd, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z20.s - z23.s }, pn11, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xfc, 0xdf, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z28.s - z31.s }, pn15, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x00, 0xc0, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z0.s - z3.s }, pn8, [x0]" + + - + input: + bytes: [ 0x54, 0xd5, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z20.s - z23.s }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb4, 0xcd, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z20.s - z23.s }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfc, 0xdf, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z28.s - z31.s }, pn15, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/st1w_q.s.yaml b/tests/MC/AArch64/SVE2p1/st1w_q.s.yaml new file mode 100644 index 0000000000..050f617357 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/st1w_q.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x40, 0x00, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z0.q }, p0, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x55, 0x55, 0x15, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z21.q }, p5, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x08, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z23.q }, p3, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x08, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z23.q }, p3, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z0.q }, p0, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z0.q }, p0, [x0]" + + - + input: + bytes: [ 0x55, 0xf5, 0x05, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z21.q }, p5, [x10, #5, mul vl]" + + - + input: + bytes: [ 0xb7, 0xed, 0x08, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z23.q }, p3, [x13, #-8, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0x0f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z31.q }, p7, [sp, #-1, mul vl]" + + - + input: + bytes: [ 0xff, 0xff, 0x0f, 0xe5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st1w { z31.q }, p7, [sp, #-1, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/st2q.s.yaml b/tests/MC/AArch64/SVE2p1/st2q.s.yaml new file mode 100644 index 0000000000..b199050c5f --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/st2q.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x60, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st2q { z0.q, z1.q }, p0, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x55, 0x15, 0x75, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st2q { z21.q, z22.q }, p5, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xb7, 0x0d, 0x68, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st2q { z23.q, z24.q }, p3, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0x00, 0x00, 0x40, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st2q { z0.q, z1.q }, p0, [x0]" + + - + input: + bytes: [ 0x55, 0x15, 0x45, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st2q { z21.q, z22.q }, p5, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x0d, 0x48, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st2q { z23.q, z24.q }, p3, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x1f, 0x4f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st2q { z31.q, z0.q }, p7, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x00, 0x00, 0x60, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st2q { z0.q, z1.q }, p0, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x55, 0x15, 0x75, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st2q { z21.q, z22.q }, p5, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xb7, 0x0d, 0x68, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st2q { z23.q, z24.q }, p3, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0x00, 0x00, 0x40, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st2q { z0.q, z1.q }, p0, [x0]" + + - + input: + bytes: [ 0x55, 0x15, 0x45, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st2q { z21.q, z22.q }, p5, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x0d, 0x48, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st2q { z23.q, z24.q }, p3, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x1f, 0x4f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st2q { z31.q, z0.q }, p7, [sp, #-2, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/st3q.s.yaml b/tests/MC/AArch64/SVE2p1/st3q.s.yaml new file mode 100644 index 0000000000..533b56c5a6 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/st3q.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xa0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st3q { z0.q - z2.q }, p0, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x55, 0x15, 0xb5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st3q { z21.q - z23.q }, p5, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xb7, 0x0d, 0xa8, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st3q { z23.q - z25.q }, p3, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st3q { z0.q - z2.q }, p0, [x0]" + + - + input: + bytes: [ 0x55, 0x15, 0x85, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st3q { z21.q - z23.q }, p5, [x10, #15, mul vl]" + + - + input: + bytes: [ 0xb7, 0x0d, 0x88, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st3q { z23.q - z25.q }, p3, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0xff, 0x1f, 0x8f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st3q { z31.q, z0.q, z1.q }, p7, [sp, #-3, mul vl]" + + - + input: + bytes: [ 0x00, 0x00, 0xa0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st3q { z0.q - z2.q }, p0, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x55, 0x15, 0xb5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st3q { z21.q - z23.q }, p5, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xb7, 0x0d, 0xa8, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st3q { z23.q - z25.q }, p3, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0x00, 0x00, 0x80, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st3q { z0.q - z2.q }, p0, [x0]" + + - + input: + bytes: [ 0x55, 0x15, 0x85, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st3q { z21.q - z23.q }, p5, [x10, #15, mul vl]" + + - + input: + bytes: [ 0xb7, 0x0d, 0x88, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st3q { z23.q - z25.q }, p3, [x13, #-24, mul vl]" + + - + input: + bytes: [ 0xff, 0x1f, 0x8f, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st3q { z31.q, z0.q, z1.q }, p7, [sp, #-3, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/st4q.s.yaml b/tests/MC/AArch64/SVE2p1/st4q.s.yaml new file mode 100644 index 0000000000..4cec2424ac --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/st4q.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0xe0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st4q { z0.q - z3.q }, p0, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x55, 0x15, 0xf5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st4q { z21.q - z24.q }, p5, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xb7, 0x0d, 0xe8, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st4q { z23.q - z26.q }, p3, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st4q { z0.q - z3.q }, p0, [x0]" + + - + input: + bytes: [ 0x55, 0x15, 0xc5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st4q { z21.q - z24.q }, p5, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb7, 0x0d, 0xc8, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st4q { z23.q - z26.q }, p3, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xff, 0x1f, 0xcf, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "st4q { z31.q, z0.q, z1.q, z2.q }, p7, [sp, #-4, mul vl]" + + - + input: + bytes: [ 0x00, 0x00, 0xe0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st4q { z0.q - z3.q }, p0, [x0, x0, lsl #4]" + + - + input: + bytes: [ 0x55, 0x15, 0xf5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st4q { z21.q - z24.q }, p5, [x10, x21, lsl #4]" + + - + input: + bytes: [ 0xb7, 0x0d, 0xe8, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st4q { z23.q - z26.q }, p3, [x13, x8, lsl #4]" + + - + input: + bytes: [ 0x00, 0x00, 0xc0, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st4q { z0.q - z3.q }, p0, [x0]" + + - + input: + bytes: [ 0x55, 0x15, 0xc5, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st4q { z21.q - z24.q }, p5, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb7, 0x0d, 0xc8, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st4q { z23.q - z26.q }, p3, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xff, 0x1f, 0xcf, 0xe4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "st4q { z31.q, z0.q, z1.q, z2.q }, p7, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/stnt1b.s.yaml b/tests/MC/AArch64/SVE2p1/stnt1b.s.yaml new file mode 100644 index 0000000000..2b69d50661 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/stnt1b.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x00, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z0.b, z1.b }, pn8, [x0, x0]" + + - + input: + bytes: [ 0x55, 0x15, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z20.b, z21.b }, pn13, [x10, x21]" + + - + input: + bytes: [ 0xb7, 0x0d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z22.b, z23.b }, pn11, [x13, x8]" + + - + input: + bytes: [ 0xff, 0x1f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z30.b, z31.b }, pn15, [sp, xzr]" + + - + input: + bytes: [ 0x01, 0x00, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z0.b, z1.b }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0x15, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z20.b, z21.b }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x0d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z22.b, z23.b }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x1f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z30.b, z31.b }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x01, 0x80, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z0.b - z3.b }, pn8, [x0, x0]" + + - + input: + bytes: [ 0x55, 0x95, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z20.b - z23.b }, pn13, [x10, x21]" + + - + input: + bytes: [ 0xb5, 0x8d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z20.b - z23.b }, pn11, [x13, x8]" + + - + input: + bytes: [ 0xfd, 0x9f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z28.b - z31.b }, pn15, [sp, xzr]" + + - + input: + bytes: [ 0x01, 0x80, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z0.b - z3.b }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0x95, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z20.b - z23.b }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb5, 0x8d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z20.b - z23.b }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfd, 0x9f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1b { z28.b - z31.b }, pn15, [sp, #-4, mul vl]" + + - + input: + bytes: [ 0x01, 0x00, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1b { z0.b, z1.b }, pn8, [x0, x0]" + + - + input: + bytes: [ 0x55, 0x15, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1b { z20.b, z21.b }, pn13, [x10, x21]" + + - + input: + bytes: [ 0xb7, 0x0d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1b { z22.b, z23.b }, pn11, [x13, x8]" + + - + input: + bytes: [ 0xff, 0x1f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1b { z30.b, z31.b }, pn15, [sp, xzr]" + + - + input: + bytes: [ 0x01, 0x00, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1b { z0.b, z1.b }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0x15, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1b { z20.b, z21.b }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x0d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1b { z22.b, z23.b }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x1f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1b { z30.b, z31.b }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x01, 0x80, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1b { z0.b - z3.b }, pn8, [x0, x0]" + + - + input: + bytes: [ 0x55, 0x95, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1b { z20.b - z23.b }, pn13, [x10, x21]" + + - + input: + bytes: [ 0xb5, 0x8d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1b { z20.b - z23.b }, pn11, [x13, x8]" + + - + input: + bytes: [ 0xfd, 0x9f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1b { z28.b - z31.b }, pn15, [sp, xzr]" + + - + input: + bytes: [ 0x01, 0x80, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1b { z0.b - z3.b }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0x95, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1b { z20.b - z23.b }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb5, 0x8d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1b { z20.b - z23.b }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfd, 0x9f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1b { z28.b - z31.b }, pn15, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/stnt1d.s.yaml b/tests/MC/AArch64/SVE2p1/stnt1d.s.yaml new file mode 100644 index 0000000000..93b56b9633 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/stnt1d.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x60, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d, z1.d }, pn8, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x55, 0x75, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z20.d, z21.d }, pn13, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z22.d, z23.d }, pn11, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xff, 0x7f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z30.d, z31.d }, pn15, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x01, 0x60, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d, z1.d }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0x75, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z20.d, z21.d }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z22.d, z23.d }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x7f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z30.d, z31.d }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x01, 0xe0, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d - z3.d }, pn8, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x55, 0xf5, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z20.d - z23.d }, pn13, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb5, 0xed, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z20.d - z23.d }, pn11, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xfd, 0xff, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z28.d - z31.d }, pn15, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x01, 0xe0, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d - z3.d }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0xf5, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z20.d - z23.d }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb5, 0xed, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z20.d - z23.d }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfd, 0xff, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1d { z28.d - z31.d }, pn15, [sp, #-4, mul vl]" + + - + input: + bytes: [ 0x01, 0x60, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d, z1.d }, pn8, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x55, 0x75, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1d { z20.d, z21.d }, pn13, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1d { z22.d, z23.d }, pn11, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xff, 0x7f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1d { z30.d, z31.d }, pn15, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x01, 0x60, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d, z1.d }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0x75, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1d { z20.d, z21.d }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x6d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1d { z22.d, z23.d }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x7f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1d { z30.d, z31.d }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x01, 0xe0, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d - z3.d }, pn8, [x0, x0, lsl #3]" + + - + input: + bytes: [ 0x55, 0xf5, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1d { z20.d - z23.d }, pn13, [x10, x21, lsl #3]" + + - + input: + bytes: [ 0xb5, 0xed, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1d { z20.d - z23.d }, pn11, [x13, x8, lsl #3]" + + - + input: + bytes: [ 0xfd, 0xff, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1d { z28.d - z31.d }, pn15, [sp, xzr, lsl #3]" + + - + input: + bytes: [ 0x01, 0xe0, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1d { z0.d - z3.d }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0xf5, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1d { z20.d - z23.d }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb5, 0xed, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1d { z20.d - z23.d }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfd, 0xff, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1d { z28.d - z31.d }, pn15, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/stnt1h.s.yaml b/tests/MC/AArch64/SVE2p1/stnt1h.s.yaml new file mode 100644 index 0000000000..8ce9494305 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/stnt1h.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x20, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z0.h, z1.h }, pn8, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x55, 0x35, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z20.h, z21.h }, pn13, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z22.h, z23.h }, pn11, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xff, 0x3f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z30.h, z31.h }, pn15, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x01, 0x20, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z0.h, z1.h }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0x35, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z20.h, z21.h }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z22.h, z23.h }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x3f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z30.h, z31.h }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x01, 0xa0, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z0.h - z3.h }, pn8, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x55, 0xb5, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z20.h - z23.h }, pn13, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb5, 0xad, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z20.h - z23.h }, pn11, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xfd, 0xbf, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z28.h - z31.h }, pn15, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x01, 0xa0, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z0.h - z3.h }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0xb5, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z20.h - z23.h }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb5, 0xad, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z20.h - z23.h }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfd, 0xbf, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1h { z28.h - z31.h }, pn15, [sp, #-4, mul vl]" + + - + input: + bytes: [ 0x01, 0x20, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1h { z0.h, z1.h }, pn8, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x55, 0x35, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1h { z20.h, z21.h }, pn13, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1h { z22.h, z23.h }, pn11, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xff, 0x3f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1h { z30.h, z31.h }, pn15, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x01, 0x20, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1h { z0.h, z1.h }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0x35, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1h { z20.h, z21.h }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x2d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1h { z22.h, z23.h }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x3f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1h { z30.h, z31.h }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x01, 0xa0, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1h { z0.h - z3.h }, pn8, [x0, x0, lsl #1]" + + - + input: + bytes: [ 0x55, 0xb5, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1h { z20.h - z23.h }, pn13, [x10, x21, lsl #1]" + + - + input: + bytes: [ 0xb5, 0xad, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1h { z20.h - z23.h }, pn11, [x13, x8, lsl #1]" + + - + input: + bytes: [ 0xfd, 0xbf, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1h { z28.h - z31.h }, pn15, [sp, xzr, lsl #1]" + + - + input: + bytes: [ 0x01, 0xa0, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1h { z0.h - z3.h }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0xb5, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1h { z20.h - z23.h }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb5, 0xad, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1h { z20.h - z23.h }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfd, 0xbf, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1h { z28.h - z31.h }, pn15, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/stnt1w.s.yaml b/tests/MC/AArch64/SVE2p1/stnt1w.s.yaml new file mode 100644 index 0000000000..90ca4c7981 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/stnt1w.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x40, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s, z1.s }, pn8, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x55, 0x55, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z20.s, z21.s }, pn13, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z22.s, z23.s }, pn11, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xff, 0x5f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z30.s, z31.s }, pn15, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x01, 0x40, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s, z1.s }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0x55, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z20.s, z21.s }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z22.s, z23.s }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x5f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z30.s, z31.s }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x01, 0xc0, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s - z3.s }, pn8, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x55, 0xd5, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z20.s - z23.s }, pn13, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb5, 0xcd, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z20.s - z23.s }, pn11, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xfd, 0xdf, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z28.s - z31.s }, pn15, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x01, 0xc0, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s - z3.s }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0xd5, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z20.s - z23.s }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb5, 0xcd, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z20.s - z23.s }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfd, 0xdf, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "stnt1w { z28.s - z31.s }, pn15, [sp, #-4, mul vl]" + + - + input: + bytes: [ 0x01, 0x40, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s, z1.s }, pn8, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x55, 0x55, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1w { z20.s, z21.s }, pn13, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1w { z22.s, z23.s }, pn11, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xff, 0x5f, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1w { z30.s, z31.s }, pn15, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x01, 0x40, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s, z1.s }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0x55, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1w { z20.s, z21.s }, pn13, [x10, #10, mul vl]" + + - + input: + bytes: [ 0xb7, 0x4d, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1w { z22.s, z23.s }, pn11, [x13, #-16, mul vl]" + + - + input: + bytes: [ 0xff, 0x5f, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1w { z30.s, z31.s }, pn15, [sp, #-2, mul vl]" + + - + input: + bytes: [ 0x01, 0xc0, 0x20, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s - z3.s }, pn8, [x0, x0, lsl #2]" + + - + input: + bytes: [ 0x55, 0xd5, 0x35, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1w { z20.s - z23.s }, pn13, [x10, x21, lsl #2]" + + - + input: + bytes: [ 0xb5, 0xcd, 0x28, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1w { z20.s - z23.s }, pn11, [x13, x8, lsl #2]" + + - + input: + bytes: [ 0xfd, 0xdf, 0x3f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1w { z28.s - z31.s }, pn15, [sp, xzr, lsl #2]" + + - + input: + bytes: [ 0x01, 0xc0, 0x60, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1w { z0.s - z3.s }, pn8, [x0]" + + - + input: + bytes: [ 0x55, 0xd5, 0x65, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1w { z20.s - z23.s }, pn13, [x10, #20, mul vl]" + + - + input: + bytes: [ 0xb5, 0xcd, 0x68, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1w { z20.s - z23.s }, pn11, [x13, #-32, mul vl]" + + - + input: + bytes: [ 0xfd, 0xdf, 0x6f, 0xa0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "stnt1w { z28.s - z31.s }, pn15, [sp, #-4, mul vl]" diff --git a/tests/MC/AArch64/SVE2p1/tblq.s.yaml b/tests/MC/AArch64/SVE2p1/tblq.s.yaml new file mode 100644 index 0000000000..58911f6a0a --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/tblq.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xf8, 0x40, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tblq z0.h, { z0.h }, z0.h" + + - + input: + bytes: [ 0x55, 0xf9, 0x55, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tblq z21.h, { z10.h }, z21.h" + + - + input: + bytes: [ 0xb7, 0xf9, 0x48, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tblq z23.h, { z13.h }, z8.h" + + - + input: + bytes: [ 0xff, 0xfb, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tblq z31.h, { z31.h }, z31.h" + + - + input: + bytes: [ 0x00, 0xf8, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tblq z0.s, { z0.s }, z0.s" + + - + input: + bytes: [ 0x55, 0xf9, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tblq z21.s, { z10.s }, z21.s" + + - + input: + bytes: [ 0xb7, 0xf9, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tblq z23.s, { z13.s }, z8.s" + + - + input: + bytes: [ 0xff, 0xfb, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tblq z31.s, { z31.s }, z31.s" + + - + input: + bytes: [ 0x00, 0xf8, 0xc0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tblq z0.d, { z0.d }, z0.d" + + - + input: + bytes: [ 0x55, 0xf9, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tblq z21.d, { z10.d }, z21.d" + + - + input: + bytes: [ 0xb7, 0xf9, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tblq z23.d, { z13.d }, z8.d" + + - + input: + bytes: [ 0xff, 0xfb, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tblq z31.d, { z31.d }, z31.d" + + - + input: + bytes: [ 0x00, 0xf8, 0x00, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tblq z0.b, { z0.b }, z0.b" + + - + input: + bytes: [ 0x55, 0xf9, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tblq z21.b, { z10.b }, z21.b" + + - + input: + bytes: [ 0xb7, 0xf9, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tblq z23.b, { z13.b }, z8.b" + + - + input: + bytes: [ 0xff, 0xfb, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tblq z31.b, { z31.b }, z31.b" + + - + input: + bytes: [ 0x00, 0xf8, 0x40, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tblq z0.h, { z0.h }, z0.h" + + - + input: + bytes: [ 0x55, 0xf9, 0x55, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tblq z21.h, { z10.h }, z21.h" + + - + input: + bytes: [ 0xb7, 0xf9, 0x48, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tblq z23.h, { z13.h }, z8.h" + + - + input: + bytes: [ 0xff, 0xfb, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tblq z31.h, { z31.h }, z31.h" + + - + input: + bytes: [ 0x00, 0xf8, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tblq z0.s, { z0.s }, z0.s" + + - + input: + bytes: [ 0x55, 0xf9, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tblq z21.s, { z10.s }, z21.s" + + - + input: + bytes: [ 0xb7, 0xf9, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tblq z23.s, { z13.s }, z8.s" + + - + input: + bytes: [ 0xff, 0xfb, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tblq z31.s, { z31.s }, z31.s" + + - + input: + bytes: [ 0x00, 0xf8, 0xc0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tblq z0.d, { z0.d }, z0.d" + + - + input: + bytes: [ 0x55, 0xf9, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tblq z21.d, { z10.d }, z21.d" + + - + input: + bytes: [ 0xb7, 0xf9, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tblq z23.d, { z13.d }, z8.d" + + - + input: + bytes: [ 0xff, 0xfb, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tblq z31.d, { z31.d }, z31.d" + + - + input: + bytes: [ 0x00, 0xf8, 0x00, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tblq z0.b, { z0.b }, z0.b" + + - + input: + bytes: [ 0x55, 0xf9, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tblq z21.b, { z10.b }, z21.b" + + - + input: + bytes: [ 0xb7, 0xf9, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tblq z23.b, { z13.b }, z8.b" + + - + input: + bytes: [ 0xff, 0xfb, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tblq z31.b, { z31.b }, z31.b" diff --git a/tests/MC/AArch64/SVE2p1/tbxq.s.yaml b/tests/MC/AArch64/SVE2p1/tbxq.s.yaml new file mode 100644 index 0000000000..5136a59d6f --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/tbxq.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x34, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tbxq z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x35, 0x75, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tbxq z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0x35, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tbxq z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0x37, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tbxq z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0x34, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tbxq z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x55, 0x35, 0xb5, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tbxq z21.s, z10.s, z21.s" + + - + input: + bytes: [ 0xb7, 0x35, 0xa8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tbxq z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0xff, 0x37, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tbxq z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0x34, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tbxq z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x55, 0x35, 0xf5, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tbxq z21.d, z10.d, z21.d" + + - + input: + bytes: [ 0xb7, 0x35, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tbxq z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0x37, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tbxq z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0x34, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tbxq z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x55, 0x35, 0x35, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tbxq z21.b, z10.b, z21.b" + + - + input: + bytes: [ 0xb7, 0x35, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tbxq z23.b, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0x37, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "tbxq z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0x34, 0x60, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tbxq z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0x35, 0x75, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tbxq z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0x35, 0x68, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tbxq z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0x37, 0x7f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tbxq z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0x34, 0xa0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tbxq z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x55, 0x35, 0xb5, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tbxq z21.s, z10.s, z21.s" + + - + input: + bytes: [ 0xb7, 0x35, 0xa8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tbxq z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0xff, 0x37, 0xbf, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tbxq z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0x34, 0xe0, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tbxq z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x55, 0x35, 0xf5, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tbxq z21.d, z10.d, z21.d" + + - + input: + bytes: [ 0xb7, 0x35, 0xe8, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tbxq z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0x37, 0xff, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tbxq z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0x34, 0x20, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tbxq z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x55, 0x35, 0x35, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tbxq z21.b, z10.b, z21.b" + + - + input: + bytes: [ 0xb7, 0x35, 0x28, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tbxq z23.b, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0x37, 0x3f, 0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "tbxq z31.b, z31.b, z31.b" diff --git a/tests/MC/AArch64/SVE2p1/udot.s.yaml b/tests/MC/AArch64/SVE2p1/udot.s.yaml new file mode 100644 index 0000000000..7b4fd5161c --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/udot.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0xcd, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "udot z23.s, z13.h, z0.h[1]" + + - + input: + bytes: [ 0x00, 0xcc, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "udot z0.s, z0.h, z0.h[0]" + + - + input: + bytes: [ 0x55, 0xcd, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "udot z21.s, z10.h, z5.h[2]" + + - + input: + bytes: [ 0xb7, 0xcd, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "udot z23.s, z13.h, z0.h[1]" + + - + input: + bytes: [ 0xff, 0xcf, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "udot z31.s, z31.h, z7.h[3]" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0xcd, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "udot z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0x00, 0xcc, 0x00, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "udot z0.s, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xcd, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "udot z21.s, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xcd, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "udot z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xcf, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "udot z31.s, z31.h, z31.h" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0xcd, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "udot z23.s, z13.h, z0.h[1]" + + - + input: + bytes: [ 0x00, 0xcc, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "udot z0.s, z0.h, z0.h[0]" + + - + input: + bytes: [ 0x55, 0xcd, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "udot z21.s, z10.h, z5.h[2]" + + - + input: + bytes: [ 0xb7, 0xcd, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "udot z23.s, z13.h, z0.h[1]" + + - + input: + bytes: [ 0xff, 0xcf, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "udot z31.s, z31.h, z7.h[3]" + + - + input: + bytes: [ 0xf7, 0xbf, 0x20, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "movprfx z23, z31" + + - + input: + bytes: [ 0xb7, 0xcd, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "udot z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0x00, 0xcc, 0x00, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "udot z0.s, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xcd, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "udot z21.s, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xcd, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "udot z23.s, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xcf, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "udot z31.s, z31.h, z31.h" diff --git a/tests/MC/AArch64/SVE2p1/umaxqv.s.yaml b/tests/MC/AArch64/SVE2p1/umaxqv.s.yaml new file mode 100644 index 0000000000..8286c2d086 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/umaxqv.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x4d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "umaxqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0x35, 0x4d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "umaxqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0x2d, 0x4d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "umaxqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0x3f, 0x4d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "umaxqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0x20, 0x8d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "umaxqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0x35, 0x8d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "umaxqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0x2d, 0x8d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "umaxqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0x3f, 0x8d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "umaxqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0x20, 0xcd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "umaxqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0x35, 0xcd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "umaxqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0x2d, 0xcd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "umaxqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0x3f, 0xcd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "umaxqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0x20, 0x0d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "umaxqv v0.16b, p0, z0.b" + + - + input: + bytes: [ 0x55, 0x35, 0x0d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "umaxqv v21.16b, p5, z10.b" + + - + input: + bytes: [ 0xb7, 0x2d, 0x0d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "umaxqv v23.16b, p3, z13.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x0d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "umaxqv v31.16b, p7, z31.b" + + - + input: + bytes: [ 0x00, 0x20, 0x4d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "umaxqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0x35, 0x4d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "umaxqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0x2d, 0x4d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "umaxqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0x3f, 0x4d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "umaxqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0x20, 0x8d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "umaxqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0x35, 0x8d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "umaxqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0x2d, 0x8d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "umaxqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0x3f, 0x8d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "umaxqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0x20, 0xcd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "umaxqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0x35, 0xcd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "umaxqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0x2d, 0xcd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "umaxqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0x3f, 0xcd, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "umaxqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0x20, 0x0d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "umaxqv v0.16b, p0, z0.b" + + - + input: + bytes: [ 0x55, 0x35, 0x0d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "umaxqv v21.16b, p5, z10.b" + + - + input: + bytes: [ 0xb7, 0x2d, 0x0d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "umaxqv v23.16b, p3, z13.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x0d, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "umaxqv v31.16b, p7, z31.b" diff --git a/tests/MC/AArch64/SVE2p1/uminqv.s.yaml b/tests/MC/AArch64/SVE2p1/uminqv.s.yaml new file mode 100644 index 0000000000..5f934f4e5d --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/uminqv.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x4f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uminqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0x35, 0x4f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uminqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0x2d, 0x4f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uminqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0x3f, 0x4f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uminqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0x20, 0x8f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uminqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0x35, 0x8f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uminqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0x2d, 0x8f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uminqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0x3f, 0x8f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uminqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0x20, 0xcf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uminqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0x35, 0xcf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uminqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0x2d, 0xcf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uminqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0x3f, 0xcf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uminqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0x20, 0x0f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uminqv v0.16b, p0, z0.b" + + - + input: + bytes: [ 0x55, 0x35, 0x0f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uminqv v21.16b, p5, z10.b" + + - + input: + bytes: [ 0xb7, 0x2d, 0x0f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uminqv v23.16b, p3, z13.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x0f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uminqv v31.16b, p7, z31.b" + + - + input: + bytes: [ 0x00, 0x20, 0x4f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uminqv v0.8h, p0, z0.h" + + - + input: + bytes: [ 0x55, 0x35, 0x4f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uminqv v21.8h, p5, z10.h" + + - + input: + bytes: [ 0xb7, 0x2d, 0x4f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uminqv v23.8h, p3, z13.h" + + - + input: + bytes: [ 0xff, 0x3f, 0x4f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uminqv v31.8h, p7, z31.h" + + - + input: + bytes: [ 0x00, 0x20, 0x8f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uminqv v0.4s, p0, z0.s" + + - + input: + bytes: [ 0x55, 0x35, 0x8f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uminqv v21.4s, p5, z10.s" + + - + input: + bytes: [ 0xb7, 0x2d, 0x8f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uminqv v23.4s, p3, z13.s" + + - + input: + bytes: [ 0xff, 0x3f, 0x8f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uminqv v31.4s, p7, z31.s" + + - + input: + bytes: [ 0x00, 0x20, 0xcf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uminqv v0.2d, p0, z0.d" + + - + input: + bytes: [ 0x55, 0x35, 0xcf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uminqv v21.2d, p5, z10.d" + + - + input: + bytes: [ 0xb7, 0x2d, 0xcf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uminqv v23.2d, p3, z13.d" + + - + input: + bytes: [ 0xff, 0x3f, 0xcf, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uminqv v31.2d, p7, z31.d" + + - + input: + bytes: [ 0x00, 0x20, 0x0f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uminqv v0.16b, p0, z0.b" + + - + input: + bytes: [ 0x55, 0x35, 0x0f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uminqv v21.16b, p5, z10.b" + + - + input: + bytes: [ 0xb7, 0x2d, 0x0f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uminqv v23.16b, p3, z13.b" + + - + input: + bytes: [ 0xff, 0x3f, 0x0f, 0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uminqv v31.16b, p7, z31.b" diff --git a/tests/MC/AArch64/SVE2p1/uqcvtn.s.yaml b/tests/MC/AArch64/SVE2p1/uqcvtn.s.yaml new file mode 100644 index 0000000000..3ee3adc638 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/uqcvtn.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x48, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvtn z0.h, { z0.s, z1.s }" + + - + input: + bytes: [ 0x55, 0x49, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvtn z21.h, { z10.s, z11.s }" + + - + input: + bytes: [ 0x97, 0x49, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvtn z23.h, { z12.s, z13.s }" + + - + input: + bytes: [ 0xdf, 0x4b, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqcvtn z31.h, { z30.s, z31.s }" + + - + input: + bytes: [ 0x00, 0x48, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uqcvtn z0.h, { z0.s, z1.s }" + + - + input: + bytes: [ 0x55, 0x49, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uqcvtn z21.h, { z10.s, z11.s }" + + - + input: + bytes: [ 0x97, 0x49, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uqcvtn z23.h, { z12.s, z13.s }" + + - + input: + bytes: [ 0xdf, 0x4b, 0x31, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uqcvtn z31.h, { z30.s, z31.s }" diff --git a/tests/MC/AArch64/SVE2p1/uqrshrn.s.yaml b/tests/MC/AArch64/SVE2p1/uqrshrn.s.yaml new file mode 100644 index 0000000000..32393c0e59 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/uqrshrn.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x38, 0xb0, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshrn z0.h, { z0.s, z1.s }, #16" + + - + input: + bytes: [ 0x55, 0x39, 0xb5, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshrn z21.h, { z10.s, z11.s }, #11" + + - + input: + bytes: [ 0x97, 0x39, 0xb8, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshrn z23.h, { z12.s, z13.s }, #8" + + - + input: + bytes: [ 0xdf, 0x3b, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "uqrshrn z31.h, { z30.s, z31.s }, #1" + + - + input: + bytes: [ 0x00, 0x38, 0xb0, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uqrshrn z0.h, { z0.s, z1.s }, #16" + + - + input: + bytes: [ 0x55, 0x39, 0xb5, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uqrshrn z21.h, { z10.s, z11.s }, #11" + + - + input: + bytes: [ 0x97, 0x39, 0xb8, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uqrshrn z23.h, { z12.s, z13.s }, #8" + + - + input: + bytes: [ 0xdf, 0x3b, 0xbf, 0x45 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uqrshrn z31.h, { z30.s, z31.s }, #1" diff --git a/tests/MC/AArch64/SVE2p1/uzpq1.s.yaml b/tests/MC/AArch64/SVE2p1/uzpq1.s.yaml new file mode 100644 index 0000000000..a2822b5429 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/uzpq1.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe8, 0x40, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xe9, 0x55, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xe9, 0x48, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xeb, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0xe8, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x55, 0xe9, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z21.s, z10.s, z21.s" + + - + input: + bytes: [ 0xb7, 0xe9, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0xff, 0xeb, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0xe8, 0xc0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x55, 0xe9, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z21.d, z10.d, z21.d" + + - + input: + bytes: [ 0xb7, 0xe9, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0xeb, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0xe8, 0x00, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x55, 0xe9, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z21.b, z10.b, z21.b" + + - + input: + bytes: [ 0xb7, 0xe9, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z23.b, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0xeb, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0xe8, 0x40, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xe9, 0x55, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xe9, 0x48, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xeb, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0xe8, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x55, 0xe9, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z21.s, z10.s, z21.s" + + - + input: + bytes: [ 0xb7, 0xe9, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0xff, 0xeb, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0xe8, 0xc0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x55, 0xe9, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z21.d, z10.d, z21.d" + + - + input: + bytes: [ 0xb7, 0xe9, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0xeb, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0xe8, 0x00, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x55, 0xe9, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z21.b, z10.b, z21.b" + + - + input: + bytes: [ 0xb7, 0xe9, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z23.b, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0xeb, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq1 z31.b, z31.b, z31.b" diff --git a/tests/MC/AArch64/SVE2p1/uzpq2.s.yaml b/tests/MC/AArch64/SVE2p1/uzpq2.s.yaml new file mode 100644 index 0000000000..cd36b4a525 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/uzpq2.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xec, 0x40, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xed, 0x55, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xed, 0x48, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xef, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0xec, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x55, 0xed, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z21.s, z10.s, z21.s" + + - + input: + bytes: [ 0xb7, 0xed, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0xff, 0xef, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0xec, 0xc0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x55, 0xed, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z21.d, z10.d, z21.d" + + - + input: + bytes: [ 0xb7, 0xed, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0xef, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0xec, 0x00, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x55, 0xed, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z21.b, z10.b, z21.b" + + - + input: + bytes: [ 0xb7, 0xed, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z23.b, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0xef, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0xec, 0x40, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xed, 0x55, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xed, 0x48, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xef, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0xec, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x55, 0xed, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z21.s, z10.s, z21.s" + + - + input: + bytes: [ 0xb7, 0xed, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0xff, 0xef, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0xec, 0xc0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x55, 0xed, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z21.d, z10.d, z21.d" + + - + input: + bytes: [ 0xb7, 0xed, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0xef, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0xec, 0x00, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x55, 0xed, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z21.b, z10.b, z21.b" + + - + input: + bytes: [ 0xb7, 0xed, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z23.b, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0xef, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "uzpq2 z31.b, z31.b, z31.b" diff --git a/tests/MC/AArch64/SVE2p1/whilege.s.yaml b/tests/MC/AArch64/SVE2p1/whilege.s.yaml new file mode 100644 index 0000000000..ada60db904 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/whilege.s.yaml @@ -0,0 +1,640 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x40, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege pn8.h, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x41, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege pn13.h, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x61, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege pn15.h, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x63, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege pn15.h, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x50, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege { p0.h, p1.h }, x0, x0" + + - + input: + bytes: [ 0x54, 0x51, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege { p4.h, p5.h }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x51, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege { p6.h, p7.h }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x53, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege { p14.h, p15.h }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x40, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege pn8.s, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x41, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege pn13.s, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x61, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege pn15.s, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x63, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege pn15.s, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x50, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege { p0.s, p1.s }, x0, x0" + + - + input: + bytes: [ 0x54, 0x51, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege { p4.s, p5.s }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x51, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege { p6.s, p7.s }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x53, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege { p14.s, p15.s }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x40, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege pn8.d, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x41, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege pn13.d, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x61, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege pn15.d, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x63, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege pn15.d, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x50, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege { p0.d, p1.d }, x0, x0" + + - + input: + bytes: [ 0x54, 0x51, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege { p4.d, p5.d }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x51, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege { p6.d, p7.d }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x53, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege { p14.d, p15.d }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x40, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege pn8.b, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x41, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege pn13.b, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x61, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege pn15.b, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x63, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege pn15.b, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x50, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege { p0.b, p1.b }, x0, x0" + + - + input: + bytes: [ 0x54, 0x51, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege { p4.b, p5.b }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x51, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege { p6.b, p7.b }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x53, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilege { p14.b, p15.b }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x40, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege pn8.h, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x41, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege pn13.h, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x61, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege pn15.h, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x63, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege pn15.h, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x50, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege { p0.h, p1.h }, x0, x0" + + - + input: + bytes: [ 0x54, 0x51, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege { p4.h, p5.h }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x51, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege { p6.h, p7.h }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x53, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege { p14.h, p15.h }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x40, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege pn8.s, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x41, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege pn13.s, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x61, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege pn15.s, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x63, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege pn15.s, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x50, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege { p0.s, p1.s }, x0, x0" + + - + input: + bytes: [ 0x54, 0x51, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege { p4.s, p5.s }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x51, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege { p6.s, p7.s }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x53, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege { p14.s, p15.s }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x40, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege pn8.d, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x41, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege pn13.d, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x61, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege pn15.d, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x63, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege pn15.d, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x50, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege { p0.d, p1.d }, x0, x0" + + - + input: + bytes: [ 0x54, 0x51, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege { p4.d, p5.d }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x51, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege { p6.d, p7.d }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x53, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege { p14.d, p15.d }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x40, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege pn8.b, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x41, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege pn13.b, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x61, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege pn15.b, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x63, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege pn15.b, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x50, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege { p0.b, p1.b }, x0, x0" + + - + input: + bytes: [ 0x54, 0x51, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege { p4.b, p5.b }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x51, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege { p6.b, p7.b }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x53, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilege { p14.b, p15.b }, xzr, xzr" diff --git a/tests/MC/AArch64/SVE2p1/whilegt.s.yaml b/tests/MC/AArch64/SVE2p1/whilegt.s.yaml new file mode 100644 index 0000000000..ab15461ac3 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/whilegt.s.yaml @@ -0,0 +1,640 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x40, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt pn8.h, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x41, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt pn13.h, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x61, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt pn15.h, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x63, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt pn15.h, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x50, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt { p0.h, p1.h }, x0, x0" + + - + input: + bytes: [ 0x55, 0x51, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt { p4.h, p5.h }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x51, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt { p6.h, p7.h }, x13, x8" + + - + input: + bytes: [ 0xff, 0x53, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt { p14.h, p15.h }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x40, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt pn8.s, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x41, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt pn13.s, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x61, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt pn15.s, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x63, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt pn15.s, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x50, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt { p0.s, p1.s }, x0, x0" + + - + input: + bytes: [ 0x55, 0x51, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt { p4.s, p5.s }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x51, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt { p6.s, p7.s }, x13, x8" + + - + input: + bytes: [ 0xff, 0x53, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt { p14.s, p15.s }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x40, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt pn8.d, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x41, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt pn13.d, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x61, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt pn15.d, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x63, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt pn15.d, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x50, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt { p0.d, p1.d }, x0, x0" + + - + input: + bytes: [ 0x55, 0x51, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt { p4.d, p5.d }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x51, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt { p6.d, p7.d }, x13, x8" + + - + input: + bytes: [ 0xff, 0x53, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt { p14.d, p15.d }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x40, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt pn8.b, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x41, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt pn13.b, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x61, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt pn15.b, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x63, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt pn15.b, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x50, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt { p0.b, p1.b }, x0, x0" + + - + input: + bytes: [ 0x55, 0x51, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt { p4.b, p5.b }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x51, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt { p6.b, p7.b }, x13, x8" + + - + input: + bytes: [ 0xff, 0x53, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilegt { p14.b, p15.b }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x40, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt pn8.h, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x41, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt pn13.h, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x61, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt pn15.h, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x63, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt pn15.h, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x50, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt { p0.h, p1.h }, x0, x0" + + - + input: + bytes: [ 0x55, 0x51, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt { p4.h, p5.h }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x51, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt { p6.h, p7.h }, x13, x8" + + - + input: + bytes: [ 0xff, 0x53, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt { p14.h, p15.h }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x40, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt pn8.s, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x41, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt pn13.s, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x61, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt pn15.s, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x63, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt pn15.s, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x50, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt { p0.s, p1.s }, x0, x0" + + - + input: + bytes: [ 0x55, 0x51, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt { p4.s, p5.s }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x51, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt { p6.s, p7.s }, x13, x8" + + - + input: + bytes: [ 0xff, 0x53, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt { p14.s, p15.s }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x40, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt pn8.d, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x41, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt pn13.d, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x61, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt pn15.d, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x63, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt pn15.d, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x50, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt { p0.d, p1.d }, x0, x0" + + - + input: + bytes: [ 0x55, 0x51, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt { p4.d, p5.d }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x51, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt { p6.d, p7.d }, x13, x8" + + - + input: + bytes: [ 0xff, 0x53, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt { p14.d, p15.d }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x40, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt pn8.b, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x41, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt pn13.b, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x61, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt pn15.b, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x63, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt pn15.b, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x50, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt { p0.b, p1.b }, x0, x0" + + - + input: + bytes: [ 0x55, 0x51, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt { p4.b, p5.b }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x51, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt { p6.b, p7.b }, x13, x8" + + - + input: + bytes: [ 0xff, 0x53, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilegt { p14.b, p15.b }, xzr, xzr" diff --git a/tests/MC/AArch64/SVE2p1/whilehi.s.yaml b/tests/MC/AArch64/SVE2p1/whilehi.s.yaml new file mode 100644 index 0000000000..063d586b6a --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/whilehi.s.yaml @@ -0,0 +1,640 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x48, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi pn8.h, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x49, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi pn13.h, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x69, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi pn15.h, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x6b, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi pn15.h, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x58, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi { p0.h, p1.h }, x0, x0" + + - + input: + bytes: [ 0x55, 0x59, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi { p4.h, p5.h }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x59, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi { p6.h, p7.h }, x13, x8" + + - + input: + bytes: [ 0xff, 0x5b, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi { p14.h, p15.h }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x48, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi pn8.s, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x49, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi pn13.s, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x69, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi pn15.s, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x6b, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi pn15.s, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x58, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi { p0.s, p1.s }, x0, x0" + + - + input: + bytes: [ 0x55, 0x59, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi { p4.s, p5.s }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x59, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi { p6.s, p7.s }, x13, x8" + + - + input: + bytes: [ 0xff, 0x5b, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi { p14.s, p15.s }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x48, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi pn8.d, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x49, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi pn13.d, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x69, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi pn15.d, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x6b, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi pn15.d, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x58, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi { p0.d, p1.d }, x0, x0" + + - + input: + bytes: [ 0x55, 0x59, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi { p4.d, p5.d }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x59, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi { p6.d, p7.d }, x13, x8" + + - + input: + bytes: [ 0xff, 0x5b, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi { p14.d, p15.d }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x48, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi pn8.b, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x49, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi pn13.b, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x69, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi pn15.b, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x6b, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi pn15.b, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x58, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi { p0.b, p1.b }, x0, x0" + + - + input: + bytes: [ 0x55, 0x59, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi { p4.b, p5.b }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x59, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi { p6.b, p7.b }, x13, x8" + + - + input: + bytes: [ 0xff, 0x5b, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehi { p14.b, p15.b }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x48, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi pn8.h, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x49, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi pn13.h, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x69, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi pn15.h, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x6b, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi pn15.h, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x58, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi { p0.h, p1.h }, x0, x0" + + - + input: + bytes: [ 0x55, 0x59, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi { p4.h, p5.h }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x59, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi { p6.h, p7.h }, x13, x8" + + - + input: + bytes: [ 0xff, 0x5b, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi { p14.h, p15.h }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x48, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi pn8.s, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x49, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi pn13.s, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x69, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi pn15.s, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x6b, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi pn15.s, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x58, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi { p0.s, p1.s }, x0, x0" + + - + input: + bytes: [ 0x55, 0x59, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi { p4.s, p5.s }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x59, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi { p6.s, p7.s }, x13, x8" + + - + input: + bytes: [ 0xff, 0x5b, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi { p14.s, p15.s }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x48, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi pn8.d, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x49, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi pn13.d, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x69, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi pn15.d, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x6b, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi pn15.d, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x58, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi { p0.d, p1.d }, x0, x0" + + - + input: + bytes: [ 0x55, 0x59, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi { p4.d, p5.d }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x59, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi { p6.d, p7.d }, x13, x8" + + - + input: + bytes: [ 0xff, 0x5b, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi { p14.d, p15.d }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x48, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi pn8.b, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x49, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi pn13.b, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x69, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi pn15.b, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x6b, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi pn15.b, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x58, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi { p0.b, p1.b }, x0, x0" + + - + input: + bytes: [ 0x55, 0x59, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi { p4.b, p5.b }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x59, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi { p6.b, p7.b }, x13, x8" + + - + input: + bytes: [ 0xff, 0x5b, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehi { p14.b, p15.b }, xzr, xzr" diff --git a/tests/MC/AArch64/SVE2p1/whilehs.s.yaml b/tests/MC/AArch64/SVE2p1/whilehs.s.yaml new file mode 100644 index 0000000000..ddd5069796 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/whilehs.s.yaml @@ -0,0 +1,640 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x48, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs pn8.h, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x49, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs pn13.h, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x69, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs pn15.h, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x6b, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs pn15.h, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x58, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs { p0.h, p1.h }, x0, x0" + + - + input: + bytes: [ 0x54, 0x59, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs { p4.h, p5.h }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x59, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs { p6.h, p7.h }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x5b, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs { p14.h, p15.h }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x48, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs pn8.s, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x49, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs pn13.s, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x69, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs pn15.s, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x6b, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs pn15.s, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x58, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs { p0.s, p1.s }, x0, x0" + + - + input: + bytes: [ 0x54, 0x59, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs { p4.s, p5.s }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x59, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs { p6.s, p7.s }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x5b, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs { p14.s, p15.s }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x48, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs pn8.d, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x49, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs pn13.d, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x69, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs pn15.d, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x6b, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs pn15.d, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x58, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs { p0.d, p1.d }, x0, x0" + + - + input: + bytes: [ 0x54, 0x59, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs { p4.d, p5.d }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x59, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs { p6.d, p7.d }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x5b, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs { p14.d, p15.d }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x48, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs pn8.b, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x49, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs pn13.b, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x69, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs pn15.b, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x6b, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs pn15.b, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x58, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs { p0.b, p1.b }, x0, x0" + + - + input: + bytes: [ 0x54, 0x59, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs { p4.b, p5.b }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x59, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs { p6.b, p7.b }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x5b, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilehs { p14.b, p15.b }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x48, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs pn8.h, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x49, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs pn13.h, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x69, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs pn15.h, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x6b, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs pn15.h, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x58, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs { p0.h, p1.h }, x0, x0" + + - + input: + bytes: [ 0x54, 0x59, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs { p4.h, p5.h }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x59, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs { p6.h, p7.h }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x5b, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs { p14.h, p15.h }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x48, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs pn8.s, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x49, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs pn13.s, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x69, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs pn15.s, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x6b, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs pn15.s, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x58, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs { p0.s, p1.s }, x0, x0" + + - + input: + bytes: [ 0x54, 0x59, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs { p4.s, p5.s }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x59, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs { p6.s, p7.s }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x5b, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs { p14.s, p15.s }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x48, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs pn8.d, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x49, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs pn13.d, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x69, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs pn15.d, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x6b, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs pn15.d, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x58, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs { p0.d, p1.d }, x0, x0" + + - + input: + bytes: [ 0x54, 0x59, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs { p4.d, p5.d }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x59, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs { p6.d, p7.d }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x5b, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs { p14.d, p15.d }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x48, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs pn8.b, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x49, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs pn13.b, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x69, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs pn15.b, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x6b, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs pn15.b, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x58, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs { p0.b, p1.b }, x0, x0" + + - + input: + bytes: [ 0x54, 0x59, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs { p4.b, p5.b }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x59, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs { p6.b, p7.b }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x5b, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilehs { p14.b, p15.b }, xzr, xzr" diff --git a/tests/MC/AArch64/SVE2p1/whilele.s.yaml b/tests/MC/AArch64/SVE2p1/whilele.s.yaml new file mode 100644 index 0000000000..25db923278 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/whilele.s.yaml @@ -0,0 +1,640 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x44, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele pn8.h, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x45, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele pn13.h, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x65, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele pn15.h, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x67, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele pn15.h, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x54, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele { p0.h, p1.h }, x0, x0" + + - + input: + bytes: [ 0x55, 0x55, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele { p4.h, p5.h }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x55, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele { p6.h, p7.h }, x13, x8" + + - + input: + bytes: [ 0xff, 0x57, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele { p14.h, p15.h }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x44, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele pn8.s, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x45, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele pn13.s, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x65, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele pn15.s, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x67, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele pn15.s, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x54, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele { p0.s, p1.s }, x0, x0" + + - + input: + bytes: [ 0x55, 0x55, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele { p4.s, p5.s }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x55, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele { p6.s, p7.s }, x13, x8" + + - + input: + bytes: [ 0xff, 0x57, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele { p14.s, p15.s }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x44, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele pn8.d, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x45, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele pn13.d, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x65, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele pn15.d, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x67, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele pn15.d, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x54, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele { p0.d, p1.d }, x0, x0" + + - + input: + bytes: [ 0x55, 0x55, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele { p4.d, p5.d }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x55, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele { p6.d, p7.d }, x13, x8" + + - + input: + bytes: [ 0xff, 0x57, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele { p14.d, p15.d }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x44, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele pn8.b, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x45, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele pn13.b, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x65, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele pn15.b, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x67, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele pn15.b, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x54, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele { p0.b, p1.b }, x0, x0" + + - + input: + bytes: [ 0x55, 0x55, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele { p4.b, p5.b }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x55, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele { p6.b, p7.b }, x13, x8" + + - + input: + bytes: [ 0xff, 0x57, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilele { p14.b, p15.b }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x44, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele pn8.h, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x45, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele pn13.h, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x65, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele pn15.h, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x67, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele pn15.h, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x54, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele { p0.h, p1.h }, x0, x0" + + - + input: + bytes: [ 0x55, 0x55, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele { p4.h, p5.h }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x55, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele { p6.h, p7.h }, x13, x8" + + - + input: + bytes: [ 0xff, 0x57, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele { p14.h, p15.h }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x44, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele pn8.s, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x45, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele pn13.s, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x65, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele pn15.s, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x67, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele pn15.s, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x54, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele { p0.s, p1.s }, x0, x0" + + - + input: + bytes: [ 0x55, 0x55, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele { p4.s, p5.s }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x55, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele { p6.s, p7.s }, x13, x8" + + - + input: + bytes: [ 0xff, 0x57, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele { p14.s, p15.s }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x44, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele pn8.d, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x45, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele pn13.d, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x65, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele pn15.d, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x67, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele pn15.d, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x54, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele { p0.d, p1.d }, x0, x0" + + - + input: + bytes: [ 0x55, 0x55, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele { p4.d, p5.d }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x55, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele { p6.d, p7.d }, x13, x8" + + - + input: + bytes: [ 0xff, 0x57, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele { p14.d, p15.d }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x44, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele pn8.b, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x45, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele pn13.b, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x65, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele pn15.b, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x67, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele pn15.b, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x54, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele { p0.b, p1.b }, x0, x0" + + - + input: + bytes: [ 0x55, 0x55, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele { p4.b, p5.b }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x55, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele { p6.b, p7.b }, x13, x8" + + - + input: + bytes: [ 0xff, 0x57, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilele { p14.b, p15.b }, xzr, xzr" diff --git a/tests/MC/AArch64/SVE2p1/whilelo.s.yaml b/tests/MC/AArch64/SVE2p1/whilelo.s.yaml new file mode 100644 index 0000000000..578939c130 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/whilelo.s.yaml @@ -0,0 +1,640 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x4c, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo pn8.h, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x4d, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo pn13.h, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x6d, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo pn15.h, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x6f, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo pn15.h, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x5c, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo { p0.h, p1.h }, x0, x0" + + - + input: + bytes: [ 0x54, 0x5d, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo { p4.h, p5.h }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x5d, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo { p6.h, p7.h }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x5f, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo { p14.h, p15.h }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x4c, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo pn8.s, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x4d, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo pn13.s, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x6d, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo pn15.s, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x6f, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo pn15.s, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x5c, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo { p0.s, p1.s }, x0, x0" + + - + input: + bytes: [ 0x54, 0x5d, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo { p4.s, p5.s }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x5d, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo { p6.s, p7.s }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x5f, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo { p14.s, p15.s }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x4c, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo pn8.d, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x4d, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo pn13.d, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x6d, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo pn15.d, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x6f, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo pn15.d, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x5c, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo { p0.d, p1.d }, x0, x0" + + - + input: + bytes: [ 0x54, 0x5d, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo { p4.d, p5.d }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x5d, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo { p6.d, p7.d }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x5f, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo { p14.d, p15.d }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x4c, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo pn8.b, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x4d, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo pn13.b, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x6d, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo pn15.b, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x6f, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo pn15.b, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x5c, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo { p0.b, p1.b }, x0, x0" + + - + input: + bytes: [ 0x54, 0x5d, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo { p4.b, p5.b }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x5d, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo { p6.b, p7.b }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x5f, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelo { p14.b, p15.b }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x4c, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo pn8.h, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x4d, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo pn13.h, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x6d, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo pn15.h, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x6f, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo pn15.h, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x5c, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo { p0.h, p1.h }, x0, x0" + + - + input: + bytes: [ 0x54, 0x5d, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo { p4.h, p5.h }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x5d, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo { p6.h, p7.h }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x5f, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo { p14.h, p15.h }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x4c, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo pn8.s, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x4d, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo pn13.s, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x6d, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo pn15.s, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x6f, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo pn15.s, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x5c, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo { p0.s, p1.s }, x0, x0" + + - + input: + bytes: [ 0x54, 0x5d, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo { p4.s, p5.s }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x5d, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo { p6.s, p7.s }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x5f, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo { p14.s, p15.s }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x4c, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo pn8.d, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x4d, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo pn13.d, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x6d, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo pn15.d, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x6f, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo pn15.d, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x5c, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo { p0.d, p1.d }, x0, x0" + + - + input: + bytes: [ 0x54, 0x5d, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo { p4.d, p5.d }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x5d, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo { p6.d, p7.d }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x5f, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo { p14.d, p15.d }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x4c, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo pn8.b, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x4d, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo pn13.b, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x6d, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo pn15.b, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x6f, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo pn15.b, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x5c, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo { p0.b, p1.b }, x0, x0" + + - + input: + bytes: [ 0x54, 0x5d, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo { p4.b, p5.b }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x5d, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo { p6.b, p7.b }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x5f, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelo { p14.b, p15.b }, xzr, xzr" diff --git a/tests/MC/AArch64/SVE2p1/whilels.s.yaml b/tests/MC/AArch64/SVE2p1/whilels.s.yaml new file mode 100644 index 0000000000..5ac4b4d3e2 --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/whilels.s.yaml @@ -0,0 +1,640 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x4c, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels pn8.h, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x4d, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels pn13.h, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x6d, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels pn15.h, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x6f, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels pn15.h, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x5c, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels { p0.h, p1.h }, x0, x0" + + - + input: + bytes: [ 0x55, 0x5d, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels { p4.h, p5.h }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x5d, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels { p6.h, p7.h }, x13, x8" + + - + input: + bytes: [ 0xff, 0x5f, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels { p14.h, p15.h }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x4c, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels pn8.s, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x4d, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels pn13.s, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x6d, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels pn15.s, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x6f, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels pn15.s, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x5c, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels { p0.s, p1.s }, x0, x0" + + - + input: + bytes: [ 0x55, 0x5d, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels { p4.s, p5.s }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x5d, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels { p6.s, p7.s }, x13, x8" + + - + input: + bytes: [ 0xff, 0x5f, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels { p14.s, p15.s }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x4c, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels pn8.d, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x4d, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels pn13.d, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x6d, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels pn15.d, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x6f, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels pn15.d, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x5c, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels { p0.d, p1.d }, x0, x0" + + - + input: + bytes: [ 0x55, 0x5d, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels { p4.d, p5.d }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x5d, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels { p6.d, p7.d }, x13, x8" + + - + input: + bytes: [ 0xff, 0x5f, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels { p14.d, p15.d }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x4c, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels pn8.b, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x4d, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels pn13.b, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x6d, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels pn15.b, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x6f, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels pn15.b, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x5c, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels { p0.b, p1.b }, x0, x0" + + - + input: + bytes: [ 0x55, 0x5d, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels { p4.b, p5.b }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x5d, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels { p6.b, p7.b }, x13, x8" + + - + input: + bytes: [ 0xff, 0x5f, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilels { p14.b, p15.b }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x4c, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels pn8.h, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x4d, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels pn13.h, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x6d, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels pn15.h, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x6f, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels pn15.h, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x5c, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels { p0.h, p1.h }, x0, x0" + + - + input: + bytes: [ 0x55, 0x5d, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels { p4.h, p5.h }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x5d, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels { p6.h, p7.h }, x13, x8" + + - + input: + bytes: [ 0xff, 0x5f, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels { p14.h, p15.h }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x4c, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels pn8.s, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x4d, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels pn13.s, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x6d, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels pn15.s, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x6f, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels pn15.s, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x5c, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels { p0.s, p1.s }, x0, x0" + + - + input: + bytes: [ 0x55, 0x5d, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels { p4.s, p5.s }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x5d, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels { p6.s, p7.s }, x13, x8" + + - + input: + bytes: [ 0xff, 0x5f, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels { p14.s, p15.s }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x4c, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels pn8.d, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x4d, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels pn13.d, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x6d, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels pn15.d, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x6f, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels pn15.d, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x5c, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels { p0.d, p1.d }, x0, x0" + + - + input: + bytes: [ 0x55, 0x5d, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels { p4.d, p5.d }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x5d, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels { p6.d, p7.d }, x13, x8" + + - + input: + bytes: [ 0xff, 0x5f, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels { p14.d, p15.d }, xzr, xzr" + + - + input: + bytes: [ 0x18, 0x4c, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels pn8.b, x0, x0, vlx2" + + - + input: + bytes: [ 0x5d, 0x4d, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels pn13.b, x10, x21, vlx2" + + - + input: + bytes: [ 0xbf, 0x6d, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels pn15.b, x13, x8, vlx4" + + - + input: + bytes: [ 0xff, 0x6f, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels pn15.b, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x11, 0x5c, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels { p0.b, p1.b }, x0, x0" + + - + input: + bytes: [ 0x55, 0x5d, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels { p4.b, p5.b }, x10, x21" + + - + input: + bytes: [ 0xb7, 0x5d, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels { p6.b, p7.b }, x13, x8" + + - + input: + bytes: [ 0xff, 0x5f, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilels { p14.b, p15.b }, xzr, xzr" diff --git a/tests/MC/AArch64/SVE2p1/whilelt.s.yaml b/tests/MC/AArch64/SVE2p1/whilelt.s.yaml new file mode 100644 index 0000000000..e5f0d9140b --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/whilelt.s.yaml @@ -0,0 +1,640 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x44, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt pn8.h, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x45, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt pn13.h, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x65, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt pn15.h, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x67, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt pn15.h, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x54, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt { p0.h, p1.h }, x0, x0" + + - + input: + bytes: [ 0x54, 0x55, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt { p4.h, p5.h }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x55, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt { p6.h, p7.h }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x57, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt { p14.h, p15.h }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x44, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt pn8.s, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x45, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt pn13.s, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x65, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt pn15.s, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x67, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt pn15.s, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x54, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt { p0.s, p1.s }, x0, x0" + + - + input: + bytes: [ 0x54, 0x55, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt { p4.s, p5.s }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x55, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt { p6.s, p7.s }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x57, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt { p14.s, p15.s }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x44, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt pn8.d, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x45, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt pn13.d, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x65, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt pn15.d, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x67, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt pn15.d, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x54, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt { p0.d, p1.d }, x0, x0" + + - + input: + bytes: [ 0x54, 0x55, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt { p4.d, p5.d }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x55, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt { p6.d, p7.d }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x57, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt { p14.d, p15.d }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x44, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt pn8.b, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x45, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt pn13.b, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x65, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt pn15.b, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x67, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt pn15.b, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x54, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt { p0.b, p1.b }, x0, x0" + + - + input: + bytes: [ 0x54, 0x55, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt { p4.b, p5.b }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x55, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt { p6.b, p7.b }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x57, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ] + expected: + insns: + - + asm_text: "whilelt { p14.b, p15.b }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x44, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt pn8.h, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x45, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt pn13.h, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x65, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt pn15.h, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x67, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt pn15.h, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x54, 0x60, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt { p0.h, p1.h }, x0, x0" + + - + input: + bytes: [ 0x54, 0x55, 0x75, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt { p4.h, p5.h }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x55, 0x68, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt { p6.h, p7.h }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x57, 0x7f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt { p14.h, p15.h }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x44, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt pn8.s, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x45, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt pn13.s, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x65, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt pn15.s, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x67, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt pn15.s, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x54, 0xa0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt { p0.s, p1.s }, x0, x0" + + - + input: + bytes: [ 0x54, 0x55, 0xb5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt { p4.s, p5.s }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x55, 0xa8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt { p6.s, p7.s }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x57, 0xbf, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt { p14.s, p15.s }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x44, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt pn8.d, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x45, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt pn13.d, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x65, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt pn15.d, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x67, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt pn15.d, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x54, 0xe0, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt { p0.d, p1.d }, x0, x0" + + - + input: + bytes: [ 0x54, 0x55, 0xf5, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt { p4.d, p5.d }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x55, 0xe8, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt { p6.d, p7.d }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x57, 0xff, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt { p14.d, p15.d }, xzr, xzr" + + - + input: + bytes: [ 0x10, 0x44, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt pn8.b, x0, x0, vlx2" + + - + input: + bytes: [ 0x55, 0x45, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt pn13.b, x10, x21, vlx2" + + - + input: + bytes: [ 0xb7, 0x65, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt pn15.b, x13, x8, vlx4" + + - + input: + bytes: [ 0xf7, 0x67, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt pn15.b, xzr, xzr, vlx4" + + - + input: + bytes: [ 0x10, 0x54, 0x20, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt { p0.b, p1.b }, x0, x0" + + - + input: + bytes: [ 0x54, 0x55, 0x35, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt { p4.b, p5.b }, x10, x21" + + - + input: + bytes: [ 0xb6, 0x55, 0x28, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt { p6.b, p7.b }, x13, x8" + + - + input: + bytes: [ 0xfe, 0x57, 0x3f, 0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "whilelt { p14.b, p15.b }, xzr, xzr" diff --git a/tests/MC/AArch64/SVE2p1/zipq1.s.yaml b/tests/MC/AArch64/SVE2p1/zipq1.s.yaml new file mode 100644 index 0000000000..e1122ca48a --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/zipq1.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq1 z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xe1, 0x55, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq1 z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xe1, 0x48, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq1 z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xe3, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq1 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0xe0, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq1 z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x55, 0xe1, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq1 z21.s, z10.s, z21.s" + + - + input: + bytes: [ 0xb7, 0xe1, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq1 z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0xff, 0xe3, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq1 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0xe0, 0xc0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq1 z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x55, 0xe1, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq1 z21.d, z10.d, z21.d" + + - + input: + bytes: [ 0xb7, 0xe1, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq1 z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0xe3, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq1 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq1 z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x55, 0xe1, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq1 z21.b, z10.b, z21.b" + + - + input: + bytes: [ 0xb7, 0xe1, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq1 z23.b, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0xe3, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq1 z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq1 z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xe1, 0x55, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq1 z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xe1, 0x48, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq1 z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xe3, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq1 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0xe0, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq1 z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x55, 0xe1, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq1 z21.s, z10.s, z21.s" + + - + input: + bytes: [ 0xb7, 0xe1, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq1 z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0xff, 0xe3, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq1 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0xe0, 0xc0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq1 z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x55, 0xe1, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq1 z21.d, z10.d, z21.d" + + - + input: + bytes: [ 0xb7, 0xe1, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq1 z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0xe3, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq1 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq1 z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x55, 0xe1, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq1 z21.b, z10.b, z21.b" + + - + input: + bytes: [ 0xb7, 0xe1, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq1 z23.b, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0xe3, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq1 z31.b, z31.b, z31.b" diff --git a/tests/MC/AArch64/SVE2p1/zipq2.s.yaml b/tests/MC/AArch64/SVE2p1/zipq2.s.yaml new file mode 100644 index 0000000000..1850b3c76a --- /dev/null +++ b/tests/MC/AArch64/SVE2p1/zipq2.s.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe4, 0x40, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq2 z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xe5, 0x55, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq2 z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xe5, 0x48, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq2 z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xe7, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq2 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0xe4, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq2 z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x55, 0xe5, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq2 z21.s, z10.s, z21.s" + + - + input: + bytes: [ 0xb7, 0xe5, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq2 z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0xff, 0xe7, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq2 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0xe4, 0xc0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq2 z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x55, 0xe5, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq2 z21.d, z10.d, z21.d" + + - + input: + bytes: [ 0xb7, 0xe5, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq2 z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0xe7, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq2 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0xe4, 0x00, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq2 z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x55, 0xe5, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq2 z21.b, z10.b, z21.b" + + - + input: + bytes: [ 0xb7, 0xe5, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq2 z23.b, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0xe7, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ] + expected: + insns: + - + asm_text: "zipq2 z31.b, z31.b, z31.b" + + - + input: + bytes: [ 0x00, 0xe4, 0x40, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq2 z0.h, z0.h, z0.h" + + - + input: + bytes: [ 0x55, 0xe5, 0x55, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq2 z21.h, z10.h, z21.h" + + - + input: + bytes: [ 0xb7, 0xe5, 0x48, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq2 z23.h, z13.h, z8.h" + + - + input: + bytes: [ 0xff, 0xe7, 0x5f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq2 z31.h, z31.h, z31.h" + + - + input: + bytes: [ 0x00, 0xe4, 0x80, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq2 z0.s, z0.s, z0.s" + + - + input: + bytes: [ 0x55, 0xe5, 0x95, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq2 z21.s, z10.s, z21.s" + + - + input: + bytes: [ 0xb7, 0xe5, 0x88, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq2 z23.s, z13.s, z8.s" + + - + input: + bytes: [ 0xff, 0xe7, 0x9f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq2 z31.s, z31.s, z31.s" + + - + input: + bytes: [ 0x00, 0xe4, 0xc0, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq2 z0.d, z0.d, z0.d" + + - + input: + bytes: [ 0x55, 0xe5, 0xd5, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq2 z21.d, z10.d, z21.d" + + - + input: + bytes: [ 0xb7, 0xe5, 0xc8, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq2 z23.d, z13.d, z8.d" + + - + input: + bytes: [ 0xff, 0xe7, 0xdf, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq2 z31.d, z31.d, z31.d" + + - + input: + bytes: [ 0x00, 0xe4, 0x00, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq2 z0.b, z0.b, z0.b" + + - + input: + bytes: [ 0x55, 0xe5, 0x15, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq2 z21.b, z10.b, z21.b" + + - + input: + bytes: [ 0xb7, 0xe5, 0x08, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq2 z23.b, z13.b, z8.b" + + - + input: + bytes: [ 0xff, 0xe7, 0x1f, 0x44 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ] + expected: + insns: + - + asm_text: "zipq2 z31.b, z31.b, z31.b" diff --git a/tests/MC/AArch64/a64-ignored-fields.txt.yaml b/tests/MC/AArch64/a64-ignored-fields.txt.yaml new file mode 100644 index 0000000000..c9068907d1 --- /dev/null +++ b/tests/MC/AArch64/a64-ignored-fields.txt.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0xe8, 0x23, 0x20, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp-armv8" ] + expected: + insns: + - + asm_text: "fcmp s31, #0.0" + + - + input: + bytes: [ 0xe8, 0x23, 0x20, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "fp-armv8" ] + expected: + insns: + - + asm_text: "fcmp s31, #0.0" diff --git a/tests/MC/AArch64/arm64-basic-a64-instructions.s.yaml b/tests/MC/AArch64/arm64-basic-a64-instructions.s.yaml new file mode 100644 index 0000000000..b75f6d3cc1 --- /dev/null +++ b/tests/MC/AArch64/arm64-basic-a64-instructions.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xe5, 0x40, 0xd4, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crc" ] + expected: + insns: + - + asm_text: "crc32b w5, w7, w20" + + - + input: + bytes: [ 0xfc, 0x47, 0xde, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crc" ] + expected: + insns: + - + asm_text: "crc32h w28, wzr, w30" + + - + input: + bytes: [ 0x20, 0x48, 0xc2, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crc" ] + expected: + insns: + - + asm_text: "crc32w w0, w1, w2" + + - + input: + bytes: [ 0x27, 0x4d, 0xd4, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crc" ] + expected: + insns: + - + asm_text: "crc32x w7, w9, x20" + + - + input: + bytes: [ 0xa9, 0x50, 0xc4, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crc" ] + expected: + insns: + - + asm_text: "crc32cb w9, w5, w4" + + - + input: + bytes: [ 0x2d, 0x56, 0xd9, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crc" ] + expected: + insns: + - + asm_text: "crc32ch w13, w17, w25" + + - + input: + bytes: [ 0x7f, 0x58, 0xc5, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crc" ] + expected: + insns: + - + asm_text: "crc32cw wzr, w3, w5" + + - + input: + bytes: [ 0x12, 0x5e, 0xdf, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crc" ] + expected: + insns: + - + asm_text: "crc32cx w18, w16, xzr" diff --git a/tests/MC/AArch64/arm64-nv-cond.s.yaml b/tests/MC/AArch64/arm64-nv-cond.s.yaml new file mode 100644 index 0000000000..eda662287c --- /dev/null +++ b/tests/MC/AArch64/arm64-nv-cond.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0xfc, 0xff, 0x7f, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "fcsel d28, d31, d31, nv" + + - + input: + bytes: [ 0x00, 0xf0, 0x80, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "csel x0, x0, x0, nv" + + - + input: + bytes: [ 0x00, 0xf0, 0x40, 0xfa ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ccmp x0, x0, #0, nv" + + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "b.nv #0" diff --git a/tests/MC/AArch64/arm64-target-specific-sysreg.s.yaml b/tests/MC/AArch64/arm64-target-specific-sysreg.s.yaml new file mode 100644 index 0000000000..343a5cf3a5 --- /dev/null +++ b/tests/MC/AArch64/arm64-target-specific-sysreg.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xf2, 0x1f, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "cyclone" ] + expected: + insns: + - + asm_text: "msr CPM_IOACC_CTL_EL3, x0" diff --git a/tests/MC/AArch64/arm64-verbose-vector-case.s.yaml b/tests/MC/AArch64/arm64-verbose-vector-case.s.yaml new file mode 100644 index 0000000000..47587b8890 --- /dev/null +++ b/tests/MC/AArch64/arm64-verbose-vector-case.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x08, 0xe1, 0x28, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crypto" ] + expected: + insns: + - + asm_text: "pmull v8.8h, v8.8b, v8.8b" + + - + input: + bytes: [ 0x08, 0xe1, 0x28, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crypto" ] + expected: + insns: + - + asm_text: "pmull2 v8.8h, v8.16b, v8.16b" + + - + input: + bytes: [ 0x08, 0xe1, 0xe8, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crypto" ] + expected: + insns: + - + asm_text: "pmull v8.1q, v8.1d, v8.1d" + + - + input: + bytes: [ 0x08, 0xe1, 0xe8, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crypto" ] + expected: + insns: + - + asm_text: "pmull2 v8.1q, v8.2d, v8.2d" + + - + input: + bytes: [ 0x08, 0xe1, 0x28, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crypto" ] + expected: + insns: + - + asm_text: "pmull v8.8h, v8.8b, v8.8b" + + - + input: + bytes: [ 0x08, 0xe1, 0x28, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crypto" ] + expected: + insns: + - + asm_text: "pmull2 v8.8h, v8.16b, v8.16b" + + - + input: + bytes: [ 0x08, 0xe1, 0xe8, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crypto" ] + expected: + insns: + - + asm_text: "pmull v8.1q, v8.1d, v8.1d" + + - + input: + bytes: [ 0x08, 0xe1, 0xe8, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crypto" ] + expected: + insns: + - + asm_text: "pmull2 v8.1q, v8.2d, v8.2d" diff --git a/tests/MC/AArch64/arm64e.s.yaml b/tests/MC/AArch64/arm64e.s.yaml new file mode 100644 index 0000000000..fd442dcce6 --- /dev/null +++ b/tests/MC/AArch64/arm64e.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x00, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64e--" ] + expected: + insns: + - + asm_text: "pacia x0, x1" diff --git a/tests/MC/AArch64/armv8.1a-vhe.s.yaml b/tests/MC/AArch64/armv8.1a-vhe.s.yaml new file mode 100644 index 0000000000..54da93b4b8 --- /dev/null +++ b/tests/MC/AArch64/armv8.1a-vhe.s.yaml @@ -0,0 +1,270 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x20, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr TTBR1_EL2, x0" + + - + input: + bytes: [ 0x20, 0xd0, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr CONTEXTIDR_EL2, x0" + + - + input: + bytes: [ 0x00, 0xe3, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr CNTHV_TVAL_EL2, x0" + + - + input: + bytes: [ 0x40, 0xe3, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr CNTHV_CVAL_EL2, x0" + + - + input: + bytes: [ 0x20, 0xe3, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr CNTHV_CTL_EL2, x0" + + - + input: + bytes: [ 0x00, 0x10, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr SCTLR_EL12, x0" + + - + input: + bytes: [ 0x40, 0x10, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr CPACR_EL12, x0" + + - + input: + bytes: [ 0x00, 0x20, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr TTBR0_EL12, x0" + + - + input: + bytes: [ 0x20, 0x20, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr TTBR1_EL12, x0" + + - + input: + bytes: [ 0x40, 0x20, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr TCR_EL12, x0" + + - + input: + bytes: [ 0x00, 0x51, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr AFSR0_EL12, x0" + + - + input: + bytes: [ 0x20, 0x51, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr AFSR1_EL12, x0" + + - + input: + bytes: [ 0x00, 0x52, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr ESR_EL12, x0" + + - + input: + bytes: [ 0x00, 0x60, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr FAR_EL12, x0" + + - + input: + bytes: [ 0x00, 0xa2, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr MAIR_EL12, x0" + + - + input: + bytes: [ 0x00, 0xa3, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr AMAIR_EL12, x0" + + - + input: + bytes: [ 0x00, 0xc0, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr VBAR_EL12, x0" + + - + input: + bytes: [ 0x20, 0xd0, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr CONTEXTIDR_EL12, x0" + + - + input: + bytes: [ 0x00, 0xe1, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr CNTKCTL_EL12, x0" + + - + input: + bytes: [ 0x00, 0xe2, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr CNTP_TVAL_EL02, x0" + + - + input: + bytes: [ 0x20, 0xe2, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr CNTP_CTL_EL02, x0" + + - + input: + bytes: [ 0x40, 0xe2, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr CNTP_CVAL_EL02, x0" + + - + input: + bytes: [ 0x00, 0xe3, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr CNTV_TVAL_EL02, x0" + + - + input: + bytes: [ 0x20, 0xe3, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr CNTV_CTL_EL02, x0" + + - + input: + bytes: [ 0x40, 0xe3, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr CNTV_CVAL_EL02, x0" + + - + input: + bytes: [ 0x00, 0x40, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr SPSR_EL12, x0" + + - + input: + bytes: [ 0x20, 0x40, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ] + expected: + insns: + - + asm_text: "msr ELR_EL12, x0" diff --git a/tests/MC/AArch64/armv8.2a-at.s.yaml b/tests/MC/AArch64/armv8.2a-at.s.yaml new file mode 100644 index 0000000000..dc32028eab --- /dev/null +++ b/tests/MC/AArch64/armv8.2a-at.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x79, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.2a" ] + expected: + insns: + - + asm_text: "at s1e1rp, x1" + + - + input: + bytes: [ 0x22, 0x79, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.2a" ] + expected: + insns: + - + asm_text: "at s1e1wp, x2" + + - + input: + bytes: [ 0x01, 0x79, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.2a", "+pan-rwv" ] + expected: + insns: + - + asm_text: "at s1e1rp, x1" + + - + input: + bytes: [ 0x22, 0x79, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.2a", "+pan-rwv" ] + expected: + insns: + - + asm_text: "at s1e1wp, x2" + + - + input: + bytes: [ 0x01, 0x79, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "at s1e1rp, x1" + + - + input: + bytes: [ 0x22, 0x79, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "at s1e1wp, x2" diff --git a/tests/MC/AArch64/armv8.2a-dotprod.s.yaml b/tests/MC/AArch64/armv8.2a-dotprod.s.yaml new file mode 100644 index 0000000000..ca11e9de21 --- /dev/null +++ b/tests/MC/AArch64/armv8.2a-dotprod.s.yaml @@ -0,0 +1,1800 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe0, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.4b[1]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0xe8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe0, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.4b[1]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0xe8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe0, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.4b[1]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0xe8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe0, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.4b[1]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0xe8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe0, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.4b[1]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0xe8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe0, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.4b[1]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0xe8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe0, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.4b[1]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0xe8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe0, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.4b[1]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0xe8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe0, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.4b[1]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0xe8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe0, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.4b[1]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0xe8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe0, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.4b[1]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0xe8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe0, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.4b[1]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0xe8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe0, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.4b[1]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0xe8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe0, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.4b[1]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0xe8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe0, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.4b[1]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0xe8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe0, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.4b[1]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0xe8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe0, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.4b[1]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0xe8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe0, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ] + expected: + insns: + - + asm_text: "sdot v0.2s, v1.8b, v2.4b[1]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" + + - + input: + bytes: [ 0x20, 0xe8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ] + expected: + insns: + - + asm_text: "sdot v0.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x20, 0xe0, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ] + expected: + insns: + - + asm_text: "udot v0.2s, v1.8b, v2.4b[0]" + + - + input: + bytes: [ 0x20, 0xe8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ] + expected: + insns: + - + asm_text: "udot v0.4s, v1.16b, v2.4b[2]" diff --git a/tests/MC/AArch64/armv8.2a-persistent-memory.s.yaml b/tests/MC/AArch64/armv8.2a-persistent-memory.s.yaml new file mode 100644 index 0000000000..ab87f564ab --- /dev/null +++ b/tests/MC/AArch64/armv8.2a-persistent-memory.s.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0x27, 0x7c, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.2a" ] + expected: + insns: + - + asm_text: "dc cvap, x7" + + - + input: + bytes: [ 0x27, 0x7c, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ccpp" ] + expected: + insns: + - + asm_text: "dc cvap, x7" + + - + input: + bytes: [ 0x27, 0x7c, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "dc cvap, x7" diff --git a/tests/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s.yaml b/tests/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s.yaml new file mode 100644 index 0000000000..8c735fc49a --- /dev/null +++ b/tests/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x02, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "mrs x0, ID_ISAR6_EL1" diff --git a/tests/MC/AArch64/armv8.3a-complex.s.yaml b/tests/MC/AArch64/armv8.3a-complex.s.yaml new file mode 100644 index 0000000000..4c4913b717 --- /dev/null +++ b/tests/MC/AArch64/armv8.3a-complex.s.yaml @@ -0,0 +1,500 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xc4, 0x42, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.4h, v1.4h, v2.4h, #0" + + - + input: + bytes: [ 0x20, 0xc4, 0x42, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.8h, v1.8h, v2.8h, #0" + + - + input: + bytes: [ 0x20, 0xc4, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.2s, v1.2s, v2.2s, #0" + + - + input: + bytes: [ 0x20, 0xc4, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.4s, v1.4s, v2.4s, #0" + + - + input: + bytes: [ 0x20, 0xc4, 0xc2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.2d, v1.2d, v2.2d, #0" + + - + input: + bytes: [ 0x20, 0xc4, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.2s, v1.2s, v2.2s, #0" + + - + input: + bytes: [ 0x20, 0xcc, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.2s, v1.2s, v2.2s, #90" + + - + input: + bytes: [ 0x20, 0xd4, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.2s, v1.2s, v2.2s, #180" + + - + input: + bytes: [ 0x20, 0xdc, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.2s, v1.2s, v2.2s, #270" + + - + input: + bytes: [ 0x20, 0xe4, 0x42, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcadd v0.4h, v1.4h, v2.4h, #90" + + - + input: + bytes: [ 0x20, 0xe4, 0x42, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcadd v0.8h, v1.8h, v2.8h, #90" + + - + input: + bytes: [ 0x20, 0xe4, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcadd v0.2s, v1.2s, v2.2s, #90" + + - + input: + bytes: [ 0x20, 0xe4, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcadd v0.4s, v1.4s, v2.4s, #90" + + - + input: + bytes: [ 0x20, 0xe4, 0xc2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcadd v0.2d, v1.2d, v2.2d, #90" + + - + input: + bytes: [ 0x20, 0xe4, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcadd v0.2s, v1.2s, v2.2s, #90" + + - + input: + bytes: [ 0x20, 0xf4, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcadd v0.2s, v1.2s, v2.2s, #270" + + - + input: + bytes: [ 0x20, 0x10, 0x42, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.4h, v1.4h, v2.h[0], #0" + + - + input: + bytes: [ 0x20, 0x10, 0x42, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.8h, v1.8h, v2.h[0], #0" + + - + input: + bytes: [ 0x20, 0x10, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #0" + + - + input: + bytes: [ 0x20, 0x30, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #90" + + - + input: + bytes: [ 0x20, 0x50, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #180" + + - + input: + bytes: [ 0x20, 0x70, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #270" + + - + input: + bytes: [ 0x20, 0x10, 0x62, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.4h, v1.4h, v2.h[1], #0" + + - + input: + bytes: [ 0x20, 0x18, 0x62, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.8h, v1.8h, v2.h[3], #0" + + - + input: + bytes: [ 0x20, 0x18, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.4s, v1.4s, v2.s[1], #0" + + - + input: + bytes: [ 0x20, 0xc4, 0x42, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.4h, v1.4h, v2.4h, #0" + + - + input: + bytes: [ 0x20, 0xc4, 0x42, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.8h, v1.8h, v2.8h, #0" + + - + input: + bytes: [ 0x20, 0xc4, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.2s, v1.2s, v2.2s, #0" + + - + input: + bytes: [ 0x20, 0xc4, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.4s, v1.4s, v2.4s, #0" + + - + input: + bytes: [ 0x20, 0xc4, 0xc2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.2d, v1.2d, v2.2d, #0" + + - + input: + bytes: [ 0x20, 0xc4, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.2s, v1.2s, v2.2s, #0" + + - + input: + bytes: [ 0x20, 0xcc, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.2s, v1.2s, v2.2s, #90" + + - + input: + bytes: [ 0x20, 0xd4, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.2s, v1.2s, v2.2s, #180" + + - + input: + bytes: [ 0x20, 0xdc, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.2s, v1.2s, v2.2s, #270" + + - + input: + bytes: [ 0x20, 0xe4, 0x42, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcadd v0.4h, v1.4h, v2.4h, #90" + + - + input: + bytes: [ 0x20, 0xe4, 0x42, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcadd v0.8h, v1.8h, v2.8h, #90" + + - + input: + bytes: [ 0x20, 0xe4, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcadd v0.2s, v1.2s, v2.2s, #90" + + - + input: + bytes: [ 0x20, 0xe4, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcadd v0.4s, v1.4s, v2.4s, #90" + + - + input: + bytes: [ 0x20, 0xe4, 0xc2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcadd v0.2d, v1.2d, v2.2d, #90" + + - + input: + bytes: [ 0x20, 0xe4, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcadd v0.2s, v1.2s, v2.2s, #90" + + - + input: + bytes: [ 0x20, 0xf4, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcadd v0.2s, v1.2s, v2.2s, #270" + + - + input: + bytes: [ 0x20, 0x10, 0x42, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.4h, v1.4h, v2.h[0], #0" + + - + input: + bytes: [ 0x20, 0x10, 0x42, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.8h, v1.8h, v2.h[0], #0" + + - + input: + bytes: [ 0x20, 0x10, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #0" + + - + input: + bytes: [ 0x20, 0x30, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #90" + + - + input: + bytes: [ 0x20, 0x50, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #180" + + - + input: + bytes: [ 0x20, 0x70, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #270" + + - + input: + bytes: [ 0x20, 0x10, 0x62, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.4h, v1.4h, v2.h[1], #0" + + - + input: + bytes: [ 0x20, 0x18, 0x62, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.8h, v1.8h, v2.h[3], #0" + + - + input: + bytes: [ 0x20, 0x18, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmla v0.4s, v1.4s, v2.s[1], #0" diff --git a/tests/MC/AArch64/armv8.3a-complex_nofp16.s.yaml b/tests/MC/AArch64/armv8.3a-complex_nofp16.s.yaml new file mode 100644 index 0000000000..6e46e2298f --- /dev/null +++ b/tests/MC/AArch64/armv8.3a-complex_nofp16.s.yaml @@ -0,0 +1,170 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xc4, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ] + expected: + insns: + - + asm_text: "fcmla v0.2s, v1.2s, v2.2s, #0" + + - + input: + bytes: [ 0x20, 0xc4, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ] + expected: + insns: + - + asm_text: "fcmla v0.4s, v1.4s, v2.4s, #0" + + - + input: + bytes: [ 0x20, 0xc4, 0xc2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ] + expected: + insns: + - + asm_text: "fcmla v0.2d, v1.2d, v2.2d, #0" + + - + input: + bytes: [ 0x20, 0xc4, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ] + expected: + insns: + - + asm_text: "fcmla v0.2s, v1.2s, v2.2s, #0" + + - + input: + bytes: [ 0x20, 0xcc, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ] + expected: + insns: + - + asm_text: "fcmla v0.2s, v1.2s, v2.2s, #90" + + - + input: + bytes: [ 0x20, 0xd4, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ] + expected: + insns: + - + asm_text: "fcmla v0.2s, v1.2s, v2.2s, #180" + + - + input: + bytes: [ 0x20, 0xdc, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ] + expected: + insns: + - + asm_text: "fcmla v0.2s, v1.2s, v2.2s, #270" + + - + input: + bytes: [ 0x20, 0xe4, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ] + expected: + insns: + - + asm_text: "fcadd v0.2s, v1.2s, v2.2s, #90" + + - + input: + bytes: [ 0x20, 0xe4, 0x82, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ] + expected: + insns: + - + asm_text: "fcadd v0.4s, v1.4s, v2.4s, #90" + + - + input: + bytes: [ 0x20, 0xe4, 0xc2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ] + expected: + insns: + - + asm_text: "fcadd v0.2d, v1.2d, v2.2d, #90" + + - + input: + bytes: [ 0x20, 0xe4, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ] + expected: + insns: + - + asm_text: "fcadd v0.2s, v1.2s, v2.2s, #90" + + - + input: + bytes: [ 0x20, 0xf4, 0x82, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ] + expected: + insns: + - + asm_text: "fcadd v0.2s, v1.2s, v2.2s, #270" + + - + input: + bytes: [ 0x20, 0x10, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ] + expected: + insns: + - + asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #0" + + - + input: + bytes: [ 0x20, 0x30, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ] + expected: + insns: + - + asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #90" + + - + input: + bytes: [ 0x20, 0x50, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ] + expected: + insns: + - + asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #180" + + - + input: + bytes: [ 0x20, 0x70, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ] + expected: + insns: + - + asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #270" + + - + input: + bytes: [ 0x20, 0x18, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ] + expected: + insns: + - + asm_text: "fcmla v0.4s, v1.4s, v2.s[1], #0" diff --git a/tests/MC/AArch64/armv8.3a-js.s.yaml b/tests/MC/AArch64/armv8.3a-js.s.yaml new file mode 100644 index 0000000000..266a29d57d --- /dev/null +++ b/tests/MC/AArch64/armv8.3a-js.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x7e, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "fjcvtzs w0, d0" + + - + input: + bytes: [ 0x00, 0x00, 0x7e, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "jsconv" ] + expected: + insns: + - + asm_text: "fjcvtzs w0, d0" diff --git a/tests/MC/AArch64/armv8.3a-pauth.s.yaml b/tests/MC/AArch64/armv8.3a-pauth.s.yaml new file mode 100644 index 0000000000..e45bfb159c --- /dev/null +++ b/tests/MC/AArch64/armv8.3a-pauth.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x3f, 0x23, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "pauth" ] + expected: + insns: + - + asm_text: "paciasp" diff --git a/tests/MC/AArch64/armv8.3a-rcpc.s.yaml b/tests/MC/AArch64/armv8.3a-rcpc.s.yaml new file mode 100644 index 0000000000..a290e71a0a --- /dev/null +++ b/tests/MC/AArch64/armv8.3a-rcpc.s.yaml @@ -0,0 +1,660 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldaprb w0, [x0]" + + - + input: + bytes: [ 0x20, 0xc2, 0xbf, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldaprh w0, [x17]" + + - + input: + bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldapr w0, [x1]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldapr x0, [x0]" + + - + input: + bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldapr w18, [x0]" + + - + input: + bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldapr x15, [x0]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65" ] + expected: + insns: + - + asm_text: "ldaprb w0, [x0]" + + - + input: + bytes: [ 0x20, 0xc2, 0xbf, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65" ] + expected: + insns: + - + asm_text: "ldaprh w0, [x17]" + + - + input: + bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65" ] + expected: + insns: + - + asm_text: "ldapr w0, [x1]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65" ] + expected: + insns: + - + asm_text: "ldapr x0, [x0]" + + - + input: + bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65" ] + expected: + insns: + - + asm_text: "ldapr w18, [x0]" + + - + input: + bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65" ] + expected: + insns: + - + asm_text: "ldapr x15, [x0]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65ae" ] + expected: + insns: + - + asm_text: "ldaprb w0, [x0]" + + - + input: + bytes: [ 0x20, 0xc2, 0xbf, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65ae" ] + expected: + insns: + - + asm_text: "ldaprh w0, [x17]" + + - + input: + bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65ae" ] + expected: + insns: + - + asm_text: "ldapr w0, [x1]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65ae" ] + expected: + insns: + - + asm_text: "ldapr x0, [x0]" + + - + input: + bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65ae" ] + expected: + insns: + - + asm_text: "ldapr w18, [x0]" + + - + input: + bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65ae" ] + expected: + insns: + - + asm_text: "ldapr x15, [x0]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "ldaprb w0, [x0]" + + - + input: + bytes: [ 0x20, 0xc2, 0xbf, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "ldaprh w0, [x17]" + + - + input: + bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "ldapr w0, [x1]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "ldapr x0, [x0]" + + - + input: + bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "ldapr w18, [x0]" + + - + input: + bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "ldapr x15, [x0]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "ldaprb w0, [x0]" + + - + input: + bytes: [ 0x20, 0xc2, 0xbf, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "ldaprh w0, [x17]" + + - + input: + bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "ldapr w0, [x1]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "ldapr x0, [x0]" + + - + input: + bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "ldapr w18, [x0]" + + - + input: + bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "ldapr x15, [x0]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-e1" ] + expected: + insns: + - + asm_text: "ldaprb w0, [x0]" + + - + input: + bytes: [ 0x20, 0xc2, 0xbf, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-e1" ] + expected: + insns: + - + asm_text: "ldaprh w0, [x17]" + + - + input: + bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-e1" ] + expected: + insns: + - + asm_text: "ldapr w0, [x1]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-e1" ] + expected: + insns: + - + asm_text: "ldapr x0, [x0]" + + - + input: + bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-e1" ] + expected: + insns: + - + asm_text: "ldapr w18, [x0]" + + - + input: + bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-e1" ] + expected: + insns: + - + asm_text: "ldapr x15, [x0]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n1" ] + expected: + insns: + - + asm_text: "ldaprb w0, [x0]" + + - + input: + bytes: [ 0x20, 0xc2, 0xbf, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n1" ] + expected: + insns: + - + asm_text: "ldaprh w0, [x17]" + + - + input: + bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n1" ] + expected: + insns: + - + asm_text: "ldapr w0, [x1]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n1" ] + expected: + insns: + - + asm_text: "ldapr x0, [x0]" + + - + input: + bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n1" ] + expected: + insns: + - + asm_text: "ldapr w18, [x0]" + + - + input: + bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n1" ] + expected: + insns: + - + asm_text: "ldapr x15, [x0]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n2" ] + expected: + insns: + - + asm_text: "ldaprb w0, [x0]" + + - + input: + bytes: [ 0x20, 0xc2, 0xbf, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n2" ] + expected: + insns: + - + asm_text: "ldaprh w0, [x17]" + + - + input: + bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n2" ] + expected: + insns: + - + asm_text: "ldapr w0, [x1]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n2" ] + expected: + insns: + - + asm_text: "ldapr x0, [x0]" + + - + input: + bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n2" ] + expected: + insns: + - + asm_text: "ldapr w18, [x0]" + + - + input: + bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n2" ] + expected: + insns: + - + asm_text: "ldapr x15, [x0]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1" ] + expected: + insns: + - + asm_text: "ldaprb w0, [x0]" + + - + input: + bytes: [ 0x20, 0xc2, 0xbf, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1" ] + expected: + insns: + - + asm_text: "ldaprh w0, [x17]" + + - + input: + bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1" ] + expected: + insns: + - + asm_text: "ldapr w0, [x1]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1" ] + expected: + insns: + - + asm_text: "ldapr x0, [x0]" + + - + input: + bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1" ] + expected: + insns: + - + asm_text: "ldapr w18, [x0]" + + - + input: + bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1" ] + expected: + insns: + - + asm_text: "ldapr x15, [x0]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1a" ] + expected: + insns: + - + asm_text: "ldaprb w0, [x0]" + + - + input: + bytes: [ 0x20, 0xc2, 0xbf, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1a" ] + expected: + insns: + - + asm_text: "ldaprh w0, [x17]" + + - + input: + bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1a" ] + expected: + insns: + - + asm_text: "ldapr w0, [x1]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1a" ] + expected: + insns: + - + asm_text: "ldapr x0, [x0]" + + - + input: + bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1a" ] + expected: + insns: + - + asm_text: "ldapr w18, [x0]" + + - + input: + bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1a" ] + expected: + insns: + - + asm_text: "ldapr x15, [x0]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.2a", "rcpc" ] + expected: + insns: + - + asm_text: "ldaprb w0, [x0]" + + - + input: + bytes: [ 0x20, 0xc2, 0xbf, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.2a", "rcpc" ] + expected: + insns: + - + asm_text: "ldaprh w0, [x17]" + + - + input: + bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.2a", "rcpc" ] + expected: + insns: + - + asm_text: "ldapr w0, [x1]" + + - + input: + bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.2a", "rcpc" ] + expected: + insns: + - + asm_text: "ldapr x0, [x0]" + + - + input: + bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.2a", "rcpc" ] + expected: + insns: + - + asm_text: "ldapr w18, [x0]" + + - + input: + bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.2a", "rcpc" ] + expected: + insns: + - + asm_text: "ldapr x15, [x0]" diff --git a/tests/MC/AArch64/armv8.3a-signed-pointer.s.yaml b/tests/MC/AArch64/armv8.3a-signed-pointer.s.yaml new file mode 100644 index 0000000000..a3e2c6e90c --- /dev/null +++ b/tests/MC/AArch64/armv8.3a-signed-pointer.s.yaml @@ -0,0 +1,910 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x21, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "mrs x0, APIAKeyLo_EL1" + + - + input: + bytes: [ 0x20, 0x21, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "mrs x0, APIAKeyHi_EL1" + + - + input: + bytes: [ 0x40, 0x21, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "mrs x0, APIBKeyLo_EL1" + + - + input: + bytes: [ 0x60, 0x21, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "mrs x0, APIBKeyHi_EL1" + + - + input: + bytes: [ 0x00, 0x22, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "mrs x0, APDAKeyLo_EL1" + + - + input: + bytes: [ 0x20, 0x22, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "mrs x0, APDAKeyHi_EL1" + + - + input: + bytes: [ 0x40, 0x22, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "mrs x0, APDBKeyLo_EL1" + + - + input: + bytes: [ 0x60, 0x22, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "mrs x0, APDBKeyHi_EL1" + + - + input: + bytes: [ 0x00, 0x23, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "mrs x0, APGAKeyLo_EL1" + + - + input: + bytes: [ 0x20, 0x23, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "mrs x0, APGAKeyHi_EL1" + + - + input: + bytes: [ 0x00, 0x21, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "msr APIAKeyLo_EL1, x0" + + - + input: + bytes: [ 0x20, 0x21, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "msr APIAKeyHi_EL1, x0" + + - + input: + bytes: [ 0x40, 0x21, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "msr APIBKeyLo_EL1, x0" + + - + input: + bytes: [ 0x60, 0x21, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "msr APIBKeyHi_EL1, x0" + + - + input: + bytes: [ 0x00, 0x22, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "msr APDAKeyLo_EL1, x0" + + - + input: + bytes: [ 0x20, 0x22, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "msr APDAKeyHi_EL1, x0" + + - + input: + bytes: [ 0x40, 0x22, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "msr APDBKeyLo_EL1, x0" + + - + input: + bytes: [ 0x60, 0x22, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "msr APDBKeyHi_EL1, x0" + + - + input: + bytes: [ 0x00, 0x23, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "msr APGAKeyLo_EL1, x0" + + - + input: + bytes: [ 0x20, 0x23, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "msr APGAKeyHi_EL1, x0" + + - + input: + bytes: [ 0xff, 0x20, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "xpaclri" + + - + input: + bytes: [ 0xff, 0x20, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "xpaclri" + + - + input: + bytes: [ 0x1f, 0x21, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "pacia1716" + + - + input: + bytes: [ 0x1f, 0x21, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "pacia1716" + + - + input: + bytes: [ 0x5f, 0x21, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "pacib1716" + + - + input: + bytes: [ 0x5f, 0x21, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "pacib1716" + + - + input: + bytes: [ 0x9f, 0x21, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autia1716" + + - + input: + bytes: [ 0x9f, 0x21, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autia1716" + + - + input: + bytes: [ 0xdf, 0x21, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autib1716" + + - + input: + bytes: [ 0xdf, 0x21, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autib1716" + + - + input: + bytes: [ 0x1f, 0x23, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "paciaz" + + - + input: + bytes: [ 0x1f, 0x23, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "paciaz" + + - + input: + bytes: [ 0x3f, 0x23, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "paciasp" + + - + input: + bytes: [ 0x3f, 0x23, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "paciasp" + + - + input: + bytes: [ 0x5f, 0x23, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "pacibz" + + - + input: + bytes: [ 0x5f, 0x23, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "pacibz" + + - + input: + bytes: [ 0x7f, 0x23, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "pacibsp" + + - + input: + bytes: [ 0x7f, 0x23, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "pacibsp" + + - + input: + bytes: [ 0x9f, 0x23, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autiaz" + + - + input: + bytes: [ 0x9f, 0x23, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autiaz" + + - + input: + bytes: [ 0xbf, 0x23, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autiasp" + + - + input: + bytes: [ 0xbf, 0x23, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autiasp" + + - + input: + bytes: [ 0xdf, 0x23, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autibz" + + - + input: + bytes: [ 0xdf, 0x23, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autibz" + + - + input: + bytes: [ 0xff, 0x23, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autibsp" + + - + input: + bytes: [ 0xff, 0x23, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autibsp" + + - + input: + bytes: [ 0x20, 0x00, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "pacia x0, x1" + + - + input: + bytes: [ 0x20, 0x10, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autia x0, x1" + + - + input: + bytes: [ 0x20, 0x08, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "pacda x0, x1" + + - + input: + bytes: [ 0x20, 0x18, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autda x0, x1" + + - + input: + bytes: [ 0x20, 0x04, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "pacib x0, x1" + + - + input: + bytes: [ 0x20, 0x14, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autib x0, x1" + + - + input: + bytes: [ 0x20, 0x0c, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "pacdb x0, x1" + + - + input: + bytes: [ 0x20, 0x1c, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autdb x0, x1" + + - + input: + bytes: [ 0x20, 0x30, 0xc2, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "pacga x0, x1, x2" + + - + input: + bytes: [ 0xe0, 0x23, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "paciza x0" + + - + input: + bytes: [ 0xe0, 0x33, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autiza x0" + + - + input: + bytes: [ 0xe0, 0x2b, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "pacdza x0" + + - + input: + bytes: [ 0xe0, 0x3b, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autdza x0" + + - + input: + bytes: [ 0xe0, 0x27, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "pacizb x0" + + - + input: + bytes: [ 0xe0, 0x37, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autizb x0" + + - + input: + bytes: [ 0xe0, 0x2f, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "pacdzb x0" + + - + input: + bytes: [ 0xe0, 0x3f, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "autdzb x0" + + - + input: + bytes: [ 0xe0, 0x43, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "xpaci x0" + + - + input: + bytes: [ 0xe0, 0x47, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "xpacd x0" + + - + input: + bytes: [ 0x01, 0x08, 0x1f, 0xd7 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "braa x0, x1" + + - + input: + bytes: [ 0x01, 0x0c, 0x1f, 0xd7 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "brab x0, x1" + + - + input: + bytes: [ 0x01, 0x08, 0x3f, 0xd7 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "blraa x0, x1" + + - + input: + bytes: [ 0x01, 0x0c, 0x3f, 0xd7 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "blrab x0, x1" + + - + input: + bytes: [ 0x1f, 0x08, 0x1f, 0xd6 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "braaz x0" + + - + input: + bytes: [ 0x1f, 0x0c, 0x1f, 0xd6 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "brabz x0" + + - + input: + bytes: [ 0x1f, 0x08, 0x3f, 0xd6 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "blraaz x0" + + - + input: + bytes: [ 0x1f, 0x0c, 0x3f, 0xd6 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "blrabz x0" + + - + input: + bytes: [ 0xff, 0x0b, 0x5f, 0xd6 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "retaa" + + - + input: + bytes: [ 0xff, 0x0f, 0x5f, 0xd6 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "retab" + + - + input: + bytes: [ 0xff, 0x0b, 0x9f, 0xd6 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "eretaa" + + - + input: + bytes: [ 0xff, 0x0f, 0x9f, 0xd6 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "eretab" + + - + input: + bytes: [ 0x20, 0xf4, 0x3f, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldraa x0, [x1, #4088]" + + - + input: + bytes: [ 0x20, 0x04, 0x60, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldraa x0, [x1, #-4096]" + + - + input: + bytes: [ 0x20, 0xf4, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldrab x0, [x1, #4088]" + + - + input: + bytes: [ 0x20, 0x04, 0xe0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldrab x0, [x1, #-4096]" + + - + input: + bytes: [ 0x20, 0xfc, 0x3f, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldraa x0, [x1, #4088]!" + + - + input: + bytes: [ 0x20, 0x0c, 0x60, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldraa x0, [x1, #-4096]!" + + - + input: + bytes: [ 0x20, 0xfc, 0xbf, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldrab x0, [x1, #4088]!" + + - + input: + bytes: [ 0x20, 0x0c, 0xe0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldrab x0, [x1, #-4096]!" + + - + input: + bytes: [ 0x20, 0x04, 0x20, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldraa x0, [x1]" + + - + input: + bytes: [ 0x20, 0x04, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldrab x0, [x1]" + + - + input: + bytes: [ 0x20, 0x0c, 0x20, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldraa x0, [x1, #0]!" + + - + input: + bytes: [ 0x20, 0x0c, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldrab x0, [x1, #0]!" + + - + input: + bytes: [ 0xff, 0x0f, 0x60, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldraa xzr, [sp, #-4096]!" + + - + input: + bytes: [ 0xff, 0x0f, 0xe0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ] + expected: + insns: + - + asm_text: "ldrab xzr, [sp, #-4096]!" diff --git a/tests/MC/AArch64/armv8.4a-flag.s.yaml b/tests/MC/AArch64/armv8.4a-flag.s.yaml new file mode 100644 index 0000000000..c4335cb3ef --- /dev/null +++ b/tests/MC/AArch64/armv8.4a-flag.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x1f, 0x40, 0x00, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "cfinv" + + - + input: + bytes: [ 0x2d, 0x08, 0x00, 0x3a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "setf8 w1" + + - + input: + bytes: [ 0xed, 0x0b, 0x00, 0x3a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "setf8 wzr" + + - + input: + bytes: [ 0x2d, 0x48, 0x00, 0x3a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "setf16 w1" + + - + input: + bytes: [ 0xed, 0x4b, 0x00, 0x3a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "setf16 wzr" + + - + input: + bytes: [ 0x2f, 0x84, 0x1f, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "rmif x1, #63, #15" + + - + input: + bytes: [ 0xef, 0x87, 0x1f, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "rmif xzr, #63, #15" + + - + input: + bytes: [ 0x1f, 0x40, 0x00, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "flagm" ] + expected: + insns: + - + asm_text: "cfinv" + + - + input: + bytes: [ 0x2d, 0x08, 0x00, 0x3a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "flagm" ] + expected: + insns: + - + asm_text: "setf8 w1" + + - + input: + bytes: [ 0xed, 0x0b, 0x00, 0x3a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "flagm" ] + expected: + insns: + - + asm_text: "setf8 wzr" + + - + input: + bytes: [ 0x2d, 0x48, 0x00, 0x3a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "flagm" ] + expected: + insns: + - + asm_text: "setf16 w1" + + - + input: + bytes: [ 0xed, 0x4b, 0x00, 0x3a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "flagm" ] + expected: + insns: + - + asm_text: "setf16 wzr" + + - + input: + bytes: [ 0x2f, 0x84, 0x1f, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "flagm" ] + expected: + insns: + - + asm_text: "rmif x1, #63, #15" + + - + input: + bytes: [ 0xef, 0x87, 0x1f, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "flagm" ] + expected: + insns: + - + asm_text: "rmif xzr, #63, #15" diff --git a/tests/MC/AArch64/armv8.4a-flagm.s.yaml b/tests/MC/AArch64/armv8.4a-flagm.s.yaml new file mode 100644 index 0000000000..482415b633 --- /dev/null +++ b/tests/MC/AArch64/armv8.4a-flagm.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x1f, 0x40, 0x00, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "flagm" ] + expected: + insns: + - + asm_text: "cfinv" + + - + input: + bytes: [ 0x1f, 0x40, 0x00, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "flagm" ] + expected: + insns: + - + asm_text: "cfinv" diff --git a/tests/MC/AArch64/armv8.4a-ldst.s.yaml b/tests/MC/AArch64/armv8.4a-ldst.s.yaml new file mode 100644 index 0000000000..bfd9f46378 --- /dev/null +++ b/tests/MC/AArch64/armv8.4a-ldst.s.yaml @@ -0,0 +1,1100 @@ +test_cases: + - + input: + bytes: [ 0x5f, 0x01, 0x00, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "stlurb wzr, [x10]" + + - + input: + bytes: [ 0x41, 0x01, 0x00, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "stlurb w1, [x10]" + + - + input: + bytes: [ 0x41, 0x01, 0x10, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "stlurb w1, [x10, #-256]" + + - + input: + bytes: [ 0x62, 0xf1, 0x0f, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "stlurb w2, [x11, #255]" + + - + input: + bytes: [ 0xe3, 0xd3, 0x1f, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "stlurb w3, [sp, #-3]" + + - + input: + bytes: [ 0x9f, 0x01, 0x40, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapurb wzr, [x12]" + + - + input: + bytes: [ 0x84, 0x01, 0x40, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapurb w4, [x12]" + + - + input: + bytes: [ 0x84, 0x01, 0x50, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapurb w4, [x12, #-256]" + + - + input: + bytes: [ 0xa5, 0xf1, 0x4f, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapurb w5, [x13, #255]" + + - + input: + bytes: [ 0xe6, 0xe3, 0x5f, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapurb w6, [sp, #-2]" + + - + input: + bytes: [ 0xc7, 0x01, 0xc0, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursb w7, [x14]" + + - + input: + bytes: [ 0xc7, 0x01, 0xd0, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursb w7, [x14, #-256]" + + - + input: + bytes: [ 0xe8, 0xf1, 0xcf, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursb w8, [x15, #255]" + + - + input: + bytes: [ 0xe9, 0xf3, 0xdf, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursb w9, [sp, #-1]" + + - + input: + bytes: [ 0x00, 0x02, 0x80, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursb x0, [x16]" + + - + input: + bytes: [ 0x00, 0x02, 0x90, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursb x0, [x16, #-256]" + + - + input: + bytes: [ 0x21, 0xf2, 0x8f, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursb x1, [x17, #255]" + + - + input: + bytes: [ 0xe2, 0x03, 0x80, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursb x2, [sp]" + + - + input: + bytes: [ 0xe2, 0x03, 0x80, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursb x2, [sp]" + + - + input: + bytes: [ 0x4a, 0x02, 0x00, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "stlurh w10, [x18]" + + - + input: + bytes: [ 0x4a, 0x02, 0x10, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "stlurh w10, [x18, #-256]" + + - + input: + bytes: [ 0x6b, 0xf2, 0x0f, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "stlurh w11, [x19, #255]" + + - + input: + bytes: [ 0xec, 0x13, 0x00, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "stlurh w12, [sp, #1]" + + - + input: + bytes: [ 0x8d, 0x02, 0x40, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapurh w13, [x20]" + + - + input: + bytes: [ 0x8d, 0x02, 0x50, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapurh w13, [x20, #-256]" + + - + input: + bytes: [ 0xae, 0xf2, 0x4f, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapurh w14, [x21, #255]" + + - + input: + bytes: [ 0xef, 0x23, 0x40, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapurh w15, [sp, #2]" + + - + input: + bytes: [ 0xd0, 0x02, 0xc0, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursh w16, [x22]" + + - + input: + bytes: [ 0xd0, 0x02, 0xd0, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursh w16, [x22, #-256]" + + - + input: + bytes: [ 0xf1, 0xf2, 0xcf, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursh w17, [x23, #255]" + + - + input: + bytes: [ 0xf2, 0x33, 0xc0, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursh w18, [sp, #3]" + + - + input: + bytes: [ 0x03, 0x03, 0x80, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursh x3, [x24]" + + - + input: + bytes: [ 0x03, 0x03, 0x90, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursh x3, [x24, #-256]" + + - + input: + bytes: [ 0x24, 0xf3, 0x8f, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursh x4, [x25, #255]" + + - + input: + bytes: [ 0xe5, 0x43, 0x80, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursh x5, [sp, #4]" + + - + input: + bytes: [ 0x53, 0x03, 0x00, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "stlur w19, [x26]" + + - + input: + bytes: [ 0x53, 0x03, 0x10, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "stlur w19, [x26, #-256]" + + - + input: + bytes: [ 0x74, 0xf3, 0x0f, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "stlur w20, [x27, #255]" + + - + input: + bytes: [ 0xf5, 0x53, 0x00, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "stlur w21, [sp, #5]" + + - + input: + bytes: [ 0x96, 0x03, 0x40, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapur w22, [x28]" + + - + input: + bytes: [ 0x96, 0x03, 0x50, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapur w22, [x28, #-256]" + + - + input: + bytes: [ 0xb7, 0xf3, 0x4f, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapur w23, [x29, #255]" + + - + input: + bytes: [ 0xf8, 0x63, 0x40, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapur w24, [sp, #6]" + + - + input: + bytes: [ 0xc6, 0x03, 0x80, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursw x6, [x30]" + + - + input: + bytes: [ 0xc6, 0x03, 0x90, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursw x6, [x30, #-256]" + + - + input: + bytes: [ 0x07, 0xf0, 0x8f, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursw x7, [x0, #255]" + + - + input: + bytes: [ 0xe8, 0x73, 0x80, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapursw x8, [sp, #7]" + + - + input: + bytes: [ 0x29, 0x00, 0x00, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "stlur x9, [x1]" + + - + input: + bytes: [ 0x29, 0x00, 0x10, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "stlur x9, [x1, #-256]" + + - + input: + bytes: [ 0x4a, 0xf0, 0x0f, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "stlur x10, [x2, #255]" + + - + input: + bytes: [ 0xeb, 0x83, 0x00, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "stlur x11, [sp, #8]" + + - + input: + bytes: [ 0x6c, 0x00, 0x40, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapur x12, [x3]" + + - + input: + bytes: [ 0x6c, 0x00, 0x50, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapur x12, [x3, #-256]" + + - + input: + bytes: [ 0x8d, 0xf0, 0x4f, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapur x13, [x4, #255]" + + - + input: + bytes: [ 0xee, 0x93, 0x40, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "ldapur x14, [sp, #9]" + + - + input: + bytes: [ 0x5f, 0x01, 0x00, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "stlurb wzr, [x10]" + + - + input: + bytes: [ 0x41, 0x01, 0x00, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "stlurb w1, [x10]" + + - + input: + bytes: [ 0x41, 0x01, 0x10, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "stlurb w1, [x10, #-256]" + + - + input: + bytes: [ 0x62, 0xf1, 0x0f, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "stlurb w2, [x11, #255]" + + - + input: + bytes: [ 0xe3, 0xd3, 0x1f, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "stlurb w3, [sp, #-3]" + + - + input: + bytes: [ 0x9f, 0x01, 0x40, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapurb wzr, [x12]" + + - + input: + bytes: [ 0x84, 0x01, 0x40, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapurb w4, [x12]" + + - + input: + bytes: [ 0x84, 0x01, 0x50, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapurb w4, [x12, #-256]" + + - + input: + bytes: [ 0xa5, 0xf1, 0x4f, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapurb w5, [x13, #255]" + + - + input: + bytes: [ 0xe6, 0xe3, 0x5f, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapurb w6, [sp, #-2]" + + - + input: + bytes: [ 0xc7, 0x01, 0xc0, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursb w7, [x14]" + + - + input: + bytes: [ 0xc7, 0x01, 0xd0, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursb w7, [x14, #-256]" + + - + input: + bytes: [ 0xe8, 0xf1, 0xcf, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursb w8, [x15, #255]" + + - + input: + bytes: [ 0xe9, 0xf3, 0xdf, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursb w9, [sp, #-1]" + + - + input: + bytes: [ 0x00, 0x02, 0x80, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursb x0, [x16]" + + - + input: + bytes: [ 0x00, 0x02, 0x90, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursb x0, [x16, #-256]" + + - + input: + bytes: [ 0x21, 0xf2, 0x8f, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursb x1, [x17, #255]" + + - + input: + bytes: [ 0xe2, 0x03, 0x80, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursb x2, [sp]" + + - + input: + bytes: [ 0xe2, 0x03, 0x80, 0x19 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursb x2, [sp]" + + - + input: + bytes: [ 0x4a, 0x02, 0x00, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "stlurh w10, [x18]" + + - + input: + bytes: [ 0x4a, 0x02, 0x10, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "stlurh w10, [x18, #-256]" + + - + input: + bytes: [ 0x6b, 0xf2, 0x0f, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "stlurh w11, [x19, #255]" + + - + input: + bytes: [ 0xec, 0x13, 0x00, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "stlurh w12, [sp, #1]" + + - + input: + bytes: [ 0x8d, 0x02, 0x40, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapurh w13, [x20]" + + - + input: + bytes: [ 0x8d, 0x02, 0x50, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapurh w13, [x20, #-256]" + + - + input: + bytes: [ 0xae, 0xf2, 0x4f, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapurh w14, [x21, #255]" + + - + input: + bytes: [ 0xef, 0x23, 0x40, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapurh w15, [sp, #2]" + + - + input: + bytes: [ 0xd0, 0x02, 0xc0, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursh w16, [x22]" + + - + input: + bytes: [ 0xd0, 0x02, 0xd0, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursh w16, [x22, #-256]" + + - + input: + bytes: [ 0xf1, 0xf2, 0xcf, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursh w17, [x23, #255]" + + - + input: + bytes: [ 0xf2, 0x33, 0xc0, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursh w18, [sp, #3]" + + - + input: + bytes: [ 0x03, 0x03, 0x80, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursh x3, [x24]" + + - + input: + bytes: [ 0x03, 0x03, 0x90, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursh x3, [x24, #-256]" + + - + input: + bytes: [ 0x24, 0xf3, 0x8f, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursh x4, [x25, #255]" + + - + input: + bytes: [ 0xe5, 0x43, 0x80, 0x59 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursh x5, [sp, #4]" + + - + input: + bytes: [ 0x53, 0x03, 0x00, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "stlur w19, [x26]" + + - + input: + bytes: [ 0x53, 0x03, 0x10, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "stlur w19, [x26, #-256]" + + - + input: + bytes: [ 0x74, 0xf3, 0x0f, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "stlur w20, [x27, #255]" + + - + input: + bytes: [ 0xf5, 0x53, 0x00, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "stlur w21, [sp, #5]" + + - + input: + bytes: [ 0x96, 0x03, 0x40, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapur w22, [x28]" + + - + input: + bytes: [ 0x96, 0x03, 0x50, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapur w22, [x28, #-256]" + + - + input: + bytes: [ 0xb7, 0xf3, 0x4f, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapur w23, [x29, #255]" + + - + input: + bytes: [ 0xf8, 0x63, 0x40, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapur w24, [sp, #6]" + + - + input: + bytes: [ 0xc6, 0x03, 0x80, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursw x6, [x30]" + + - + input: + bytes: [ 0xc6, 0x03, 0x90, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursw x6, [x30, #-256]" + + - + input: + bytes: [ 0x07, 0xf0, 0x8f, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursw x7, [x0, #255]" + + - + input: + bytes: [ 0xe8, 0x73, 0x80, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapursw x8, [sp, #7]" + + - + input: + bytes: [ 0x29, 0x00, 0x00, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "stlur x9, [x1]" + + - + input: + bytes: [ 0x29, 0x00, 0x10, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "stlur x9, [x1, #-256]" + + - + input: + bytes: [ 0x4a, 0xf0, 0x0f, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "stlur x10, [x2, #255]" + + - + input: + bytes: [ 0xeb, 0x83, 0x00, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "stlur x11, [sp, #8]" + + - + input: + bytes: [ 0x6c, 0x00, 0x40, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapur x12, [x3]" + + - + input: + bytes: [ 0x6c, 0x00, 0x50, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapur x12, [x3, #-256]" + + - + input: + bytes: [ 0x8d, 0xf0, 0x4f, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapur x13, [x4, #255]" + + - + input: + bytes: [ 0xee, 0x93, 0x40, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ] + expected: + insns: + - + asm_text: "ldapur x14, [sp, #9]" diff --git a/tests/MC/AArch64/armv8.4a-trace.s.yaml b/tests/MC/AArch64/armv8.4a-trace.s.yaml new file mode 100644 index 0000000000..fbfdd5ca80 --- /dev/null +++ b/tests/MC/AArch64/armv8.4a-trace.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x12, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "msr TRFCR_EL1, x0" + + - + input: + bytes: [ 0x20, 0x12, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "msr TRFCR_EL2, x0" + + - + input: + bytes: [ 0x20, 0x12, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "msr TRFCR_EL12, x0" + + - + input: + bytes: [ 0x20, 0x12, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "mrs x0, TRFCR_EL1" + + - + input: + bytes: [ 0x20, 0x12, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "mrs x0, TRFCR_EL2" + + - + input: + bytes: [ 0x20, 0x12, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "mrs x0, TRFCR_EL12" + + - + input: + bytes: [ 0x5f, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "tsb csync" + + - + input: + bytes: [ 0x20, 0x12, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tracev8.4" ] + expected: + insns: + - + asm_text: "msr TRFCR_EL1, x0" + + - + input: + bytes: [ 0x20, 0x12, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tracev8.4" ] + expected: + insns: + - + asm_text: "msr TRFCR_EL2, x0" + + - + input: + bytes: [ 0x20, 0x12, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tracev8.4" ] + expected: + insns: + - + asm_text: "msr TRFCR_EL12, x0" + + - + input: + bytes: [ 0x20, 0x12, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tracev8.4" ] + expected: + insns: + - + asm_text: "mrs x0, TRFCR_EL1" + + - + input: + bytes: [ 0x20, 0x12, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tracev8.4" ] + expected: + insns: + - + asm_text: "mrs x0, TRFCR_EL2" + + - + input: + bytes: [ 0x20, 0x12, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tracev8.4" ] + expected: + insns: + - + asm_text: "mrs x0, TRFCR_EL12" + + - + input: + bytes: [ 0x5f, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tracev8.4" ] + expected: + insns: + - + asm_text: "tsb csync" diff --git a/tests/MC/AArch64/armv8.4a-virt.s.yaml b/tests/MC/AArch64/armv8.4a-virt.s.yaml new file mode 100644 index 0000000000..97345dfff2 --- /dev/null +++ b/tests/MC/AArch64/armv8.4a-virt.s.yaml @@ -0,0 +1,90 @@ +test_cases: + - + input: + bytes: [ 0x40, 0x26, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "msr VSTCR_EL2, x0" + + - + input: + bytes: [ 0x00, 0x26, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "msr VSTTBR_EL2, x0" + + - + input: + bytes: [ 0x2c, 0x13, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "msr SDER32_EL2, x12" + + - + input: + bytes: [ 0x00, 0xe4, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "msr CNTHVS_TVAL_EL2, x0" + + - + input: + bytes: [ 0x40, 0xe4, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "msr CNTHVS_CVAL_EL2, x0" + + - + input: + bytes: [ 0x20, 0xe4, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "msr CNTHVS_CTL_EL2, x0" + + - + input: + bytes: [ 0x00, 0xe5, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "msr CNTHPS_TVAL_EL2, x0" + + - + input: + bytes: [ 0x40, 0xe5, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "msr CNTHPS_CVAL_EL2, x0" + + - + input: + bytes: [ 0x20, 0xe5, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "msr CNTHPS_CTL_EL2, x0" diff --git a/tests/MC/AArch64/armv8.4a-vncr.s.yaml b/tests/MC/AArch64/armv8.4a-vncr.s.yaml new file mode 100644 index 0000000000..8566f7c413 --- /dev/null +++ b/tests/MC/AArch64/armv8.4a-vncr.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x22, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "mrs x0, VNCR_EL2" + + - + input: + bytes: [ 0x00, 0x22, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ] + expected: + insns: + - + asm_text: "msr VNCR_EL2, x0" diff --git a/tests/MC/AArch64/armv8.5a-altnzcv.s.yaml b/tests/MC/AArch64/armv8.5a-altnzcv.s.yaml new file mode 100644 index 0000000000..cefd7c6016 --- /dev/null +++ b/tests/MC/AArch64/armv8.5a-altnzcv.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x3f, 0x40, 0x00, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "xaflag" + + - + input: + bytes: [ 0x5f, 0x40, 0x00, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "axflag" + + - + input: + bytes: [ 0x3f, 0x40, 0x00, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+altnzcv" ] + expected: + insns: + - + asm_text: "xaflag" + + - + input: + bytes: [ 0x5f, 0x40, 0x00, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+altnzcv" ] + expected: + insns: + - + asm_text: "axflag" diff --git a/tests/MC/AArch64/armv8.5a-bti.s.yaml b/tests/MC/AArch64/armv8.5a-bti.s.yaml new file mode 100644 index 0000000000..940fbd7303 --- /dev/null +++ b/tests/MC/AArch64/armv8.5a-bti.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x1f, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "bti" ] + expected: + insns: + - + asm_text: "bti" + + - + input: + bytes: [ 0x5f, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "bti" ] + expected: + insns: + - + asm_text: "bti c" + + - + input: + bytes: [ 0x9f, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "bti" ] + expected: + insns: + - + asm_text: "bti j" + + - + input: + bytes: [ 0xdf, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "bti" ] + expected: + insns: + - + asm_text: "bti jc" + + - + input: + bytes: [ 0x1f, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "bti" ] + expected: + insns: + - + asm_text: "bti" + + - + input: + bytes: [ 0x5f, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "bti" ] + expected: + insns: + - + asm_text: "bti c" + + - + input: + bytes: [ 0x9f, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "bti" ] + expected: + insns: + - + asm_text: "bti j" + + - + input: + bytes: [ 0xdf, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "bti" ] + expected: + insns: + - + asm_text: "bti jc" + + - + input: + bytes: [ 0x1f, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "bti" + + - + input: + bytes: [ 0x5f, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "bti c" + + - + input: + bytes: [ 0x9f, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "bti j" + + - + input: + bytes: [ 0xdf, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "bti jc" + + - + input: + bytes: [ 0x1f, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "bti" + + - + input: + bytes: [ 0x5f, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "bti c" + + - + input: + bytes: [ 0x9f, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "bti j" + + - + input: + bytes: [ 0xdf, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "bti jc" + + - + input: + bytes: [ 0x1f, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-bti" ] + expected: + insns: + - + asm_text: "bti" + + - + input: + bytes: [ 0x5f, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-bti" ] + expected: + insns: + - + asm_text: "bti c" + + - + input: + bytes: [ 0x9f, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-bti" ] + expected: + insns: + - + asm_text: "bti j" + + - + input: + bytes: [ 0xdf, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-bti" ] + expected: + insns: + - + asm_text: "bti jc" + + - + input: + bytes: [ 0x1f, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-bti" ] + expected: + insns: + - + asm_text: "bti" + + - + input: + bytes: [ 0x5f, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-bti" ] + expected: + insns: + - + asm_text: "bti c" + + - + input: + bytes: [ 0x9f, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-bti" ] + expected: + insns: + - + asm_text: "bti j" + + - + input: + bytes: [ 0xdf, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-bti" ] + expected: + insns: + - + asm_text: "bti jc" diff --git a/tests/MC/AArch64/armv8.5a-frint.s.yaml b/tests/MC/AArch64/armv8.5a-frint.s.yaml new file mode 100644 index 0000000000..d4d7553dd6 --- /dev/null +++ b/tests/MC/AArch64/armv8.5a-frint.s.yaml @@ -0,0 +1,400 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x40, 0x28, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint32z s0, s1" + + - + input: + bytes: [ 0x20, 0x40, 0x68, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint32z d0, d1" + + - + input: + bytes: [ 0x62, 0x40, 0x29, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint64z s2, s3" + + - + input: + bytes: [ 0x62, 0x40, 0x69, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint64z d2, d3" + + - + input: + bytes: [ 0xa4, 0xc0, 0x28, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint32x s4, s5" + + - + input: + bytes: [ 0xa4, 0xc0, 0x68, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint32x d4, d5" + + - + input: + bytes: [ 0xe6, 0xc0, 0x29, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint64x s6, s7" + + - + input: + bytes: [ 0xe6, 0xc0, 0x69, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint64x d6, d7" + + - + input: + bytes: [ 0x20, 0xe8, 0x21, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint32z v0.2s, v1.2s" + + - + input: + bytes: [ 0x20, 0xe8, 0x61, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint32z v0.2d, v1.2d" + + - + input: + bytes: [ 0x20, 0xe8, 0x21, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint32z v0.4s, v1.4s" + + - + input: + bytes: [ 0x62, 0xf8, 0x21, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint64z v2.2s, v3.2s" + + - + input: + bytes: [ 0x62, 0xf8, 0x61, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint64z v2.2d, v3.2d" + + - + input: + bytes: [ 0x62, 0xf8, 0x21, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint64z v2.4s, v3.4s" + + - + input: + bytes: [ 0xa4, 0xe8, 0x21, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint32x v4.2s, v5.2s" + + - + input: + bytes: [ 0xa4, 0xe8, 0x61, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint32x v4.2d, v5.2d" + + - + input: + bytes: [ 0xa4, 0xe8, 0x21, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint32x v4.4s, v5.4s" + + - + input: + bytes: [ 0xe6, 0xf8, 0x21, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint64x v6.2s, v7.2s" + + - + input: + bytes: [ 0xe6, 0xf8, 0x61, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint64x v6.2d, v7.2d" + + - + input: + bytes: [ 0xe6, 0xf8, 0x21, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "frint64x v6.4s, v7.4s" + + - + input: + bytes: [ 0x20, 0x40, 0x28, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint32z s0, s1" + + - + input: + bytes: [ 0x20, 0x40, 0x68, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint32z d0, d1" + + - + input: + bytes: [ 0x62, 0x40, 0x29, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint64z s2, s3" + + - + input: + bytes: [ 0x62, 0x40, 0x69, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint64z d2, d3" + + - + input: + bytes: [ 0xa4, 0xc0, 0x28, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint32x s4, s5" + + - + input: + bytes: [ 0xa4, 0xc0, 0x68, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint32x d4, d5" + + - + input: + bytes: [ 0xe6, 0xc0, 0x29, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint64x s6, s7" + + - + input: + bytes: [ 0xe6, 0xc0, 0x69, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint64x d6, d7" + + - + input: + bytes: [ 0x20, 0xe8, 0x21, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint32z v0.2s, v1.2s" + + - + input: + bytes: [ 0x20, 0xe8, 0x61, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint32z v0.2d, v1.2d" + + - + input: + bytes: [ 0x20, 0xe8, 0x21, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint32z v0.4s, v1.4s" + + - + input: + bytes: [ 0x62, 0xf8, 0x21, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint64z v2.2s, v3.2s" + + - + input: + bytes: [ 0x62, 0xf8, 0x61, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint64z v2.2d, v3.2d" + + - + input: + bytes: [ 0x62, 0xf8, 0x21, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint64z v2.4s, v3.4s" + + - + input: + bytes: [ 0xa4, 0xe8, 0x21, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint32x v4.2s, v5.2s" + + - + input: + bytes: [ 0xa4, 0xe8, 0x61, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint32x v4.2d, v5.2d" + + - + input: + bytes: [ 0xa4, 0xe8, 0x21, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint32x v4.4s, v5.4s" + + - + input: + bytes: [ 0xe6, 0xf8, 0x21, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint64x v6.2s, v7.2s" + + - + input: + bytes: [ 0xe6, 0xf8, 0x61, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint64x v6.2d, v7.2d" + + - + input: + bytes: [ 0xe6, 0xf8, 0x21, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ] + expected: + insns: + - + asm_text: "frint64x v6.4s, v7.4s" diff --git a/tests/MC/AArch64/armv8.5a-mte.s.yaml b/tests/MC/AArch64/armv8.5a-mte.s.yaml new file mode 100644 index 0000000000..b4796e8019 --- /dev/null +++ b/tests/MC/AArch64/armv8.5a-mte.s.yaml @@ -0,0 +1,1430 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x10, 0xdf, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "irg x0, x1" + + - + input: + bytes: [ 0x3f, 0x10, 0xdf, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "irg sp, x1" + + - + input: + bytes: [ 0xe0, 0x13, 0xdf, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "irg x0, sp" + + - + input: + bytes: [ 0x20, 0x10, 0xc2, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "irg x0, x1, x2" + + - + input: + bytes: [ 0x3f, 0x10, 0xc2, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "irg sp, x1, x2" + + - + input: + bytes: [ 0x20, 0x04, 0x80, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "addg x0, x1, #0, #1" + + - + input: + bytes: [ 0x5f, 0x0c, 0x82, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "addg sp, x2, #32, #3" + + - + input: + bytes: [ 0xe0, 0x17, 0x84, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "addg x0, sp, #64, #5" + + - + input: + bytes: [ 0x83, 0x18, 0xbf, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "addg x3, x4, #1008, #6" + + - + input: + bytes: [ 0xc5, 0x3c, 0x87, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "addg x5, x6, #112, #15" + + - + input: + bytes: [ 0x20, 0x04, 0x80, 0xd1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "subg x0, x1, #0, #1" + + - + input: + bytes: [ 0x5f, 0x0c, 0x82, 0xd1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "subg sp, x2, #32, #3" + + - + input: + bytes: [ 0xe0, 0x17, 0x84, 0xd1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "subg x0, sp, #64, #5" + + - + input: + bytes: [ 0x83, 0x18, 0xbf, 0xd1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "subg x3, x4, #1008, #6" + + - + input: + bytes: [ 0xc5, 0x3c, 0x87, 0xd1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "subg x5, x6, #112, #15" + + - + input: + bytes: [ 0x20, 0x14, 0xc2, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "gmi x0, x1, x2" + + - + input: + bytes: [ 0xe3, 0x17, 0xc4, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "gmi x3, sp, x4" + + - + input: + bytes: [ 0x1f, 0x14, 0xde, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "gmi xzr, x0, x30" + + - + input: + bytes: [ 0x1e, 0x14, 0xdf, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "gmi x30, x0, xzr" + + - + input: + bytes: [ 0x20, 0x08, 0x20, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stg x0, [x1]" + + - + input: + bytes: [ 0x21, 0x08, 0x30, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stg x1, [x1, #-4096]" + + - + input: + bytes: [ 0x42, 0xf8, 0x2f, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stg x2, [x2, #4080]" + + - + input: + bytes: [ 0xe3, 0x1b, 0x20, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stg x3, [sp, #16]" + + - + input: + bytes: [ 0xff, 0x1b, 0x20, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stg sp, [sp, #16]" + + - + input: + bytes: [ 0x20, 0x08, 0x60, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stzg x0, [x1]" + + - + input: + bytes: [ 0x21, 0x08, 0x70, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stzg x1, [x1, #-4096]" + + - + input: + bytes: [ 0x42, 0xf8, 0x6f, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stzg x2, [x2, #4080]" + + - + input: + bytes: [ 0xe3, 0x1b, 0x60, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stzg x3, [sp, #16]" + + - + input: + bytes: [ 0xff, 0x1b, 0x60, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stzg sp, [sp, #16]" + + - + input: + bytes: [ 0x20, 0x0c, 0x30, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stg x0, [x1, #-4096]!" + + - + input: + bytes: [ 0x41, 0xfc, 0x2f, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stg x1, [x2, #4080]!" + + - + input: + bytes: [ 0xe2, 0x1f, 0x20, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stg x2, [sp, #16]!" + + - + input: + bytes: [ 0xff, 0x1f, 0x20, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stg sp, [sp, #16]!" + + - + input: + bytes: [ 0x20, 0x0c, 0x70, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stzg x0, [x1, #-4096]!" + + - + input: + bytes: [ 0x41, 0xfc, 0x6f, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stzg x1, [x2, #4080]!" + + - + input: + bytes: [ 0xe2, 0x1f, 0x60, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stzg x2, [sp, #16]!" + + - + input: + bytes: [ 0xff, 0x1f, 0x60, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stzg sp, [sp, #16]!" + + - + input: + bytes: [ 0x20, 0x04, 0x30, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stg x0, [x1], #-4096" + + - + input: + bytes: [ 0x41, 0xf4, 0x2f, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stg x1, [x2], #4080" + + - + input: + bytes: [ 0xe2, 0x17, 0x20, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stg x2, [sp], #16" + + - + input: + bytes: [ 0xff, 0x17, 0x20, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stg sp, [sp], #16" + + - + input: + bytes: [ 0x20, 0x04, 0x70, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stzg x0, [x1], #-4096" + + - + input: + bytes: [ 0x41, 0xf4, 0x6f, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stzg x1, [x2], #4080" + + - + input: + bytes: [ 0xe2, 0x17, 0x60, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stzg x2, [sp], #16" + + - + input: + bytes: [ 0xff, 0x17, 0x60, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stzg sp, [sp], #16" + + - + input: + bytes: [ 0x20, 0x08, 0xa0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "st2g x0, [x1]" + + - + input: + bytes: [ 0x21, 0x08, 0xb0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "st2g x1, [x1, #-4096]" + + - + input: + bytes: [ 0x42, 0xf8, 0xaf, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "st2g x2, [x2, #4080]" + + - + input: + bytes: [ 0xe3, 0x1b, 0xa0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "st2g x3, [sp, #16]" + + - + input: + bytes: [ 0xff, 0x1b, 0xa0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "st2g sp, [sp, #16]" + + - + input: + bytes: [ 0x20, 0x08, 0xe0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stz2g x0, [x1]" + + - + input: + bytes: [ 0x21, 0x08, 0xf0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stz2g x1, [x1, #-4096]" + + - + input: + bytes: [ 0x42, 0xf8, 0xef, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stz2g x2, [x2, #4080]" + + - + input: + bytes: [ 0xe3, 0x1b, 0xe0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stz2g x3, [sp, #16]" + + - + input: + bytes: [ 0xff, 0x1b, 0xe0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stz2g sp, [sp, #16]" + + - + input: + bytes: [ 0x20, 0x0c, 0xb0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "st2g x0, [x1, #-4096]!" + + - + input: + bytes: [ 0x41, 0xfc, 0xaf, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "st2g x1, [x2, #4080]!" + + - + input: + bytes: [ 0xe2, 0x1f, 0xa0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "st2g x2, [sp, #16]!" + + - + input: + bytes: [ 0xff, 0x1f, 0xa0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "st2g sp, [sp, #16]!" + + - + input: + bytes: [ 0x20, 0x0c, 0xf0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stz2g x0, [x1, #-4096]!" + + - + input: + bytes: [ 0x41, 0xfc, 0xef, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stz2g x1, [x2, #4080]!" + + - + input: + bytes: [ 0xe2, 0x1f, 0xe0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stz2g x2, [sp, #16]!" + + - + input: + bytes: [ 0xff, 0x1f, 0xe0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stz2g sp, [sp, #16]!" + + - + input: + bytes: [ 0x20, 0x04, 0xb0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "st2g x0, [x1], #-4096" + + - + input: + bytes: [ 0x41, 0xf4, 0xaf, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "st2g x1, [x2], #4080" + + - + input: + bytes: [ 0xe2, 0x17, 0xa0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "st2g x2, [sp], #16" + + - + input: + bytes: [ 0xff, 0x17, 0xa0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "st2g sp, [sp], #16" + + - + input: + bytes: [ 0x20, 0x04, 0xf0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stz2g x0, [x1], #-4096" + + - + input: + bytes: [ 0x41, 0xf4, 0xef, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stz2g x1, [x2], #4080" + + - + input: + bytes: [ 0xe2, 0x17, 0xe0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stz2g x2, [sp], #16" + + - + input: + bytes: [ 0xff, 0x17, 0xe0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stz2g sp, [sp], #16" + + - + input: + bytes: [ 0x40, 0x04, 0x00, 0x69 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stgp x0, x1, [x2]" + + - + input: + bytes: [ 0x40, 0x04, 0x20, 0x69 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stgp x0, x1, [x2, #-1024]" + + - + input: + bytes: [ 0x40, 0x84, 0x1f, 0x69 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stgp x0, x1, [x2, #1008]" + + - + input: + bytes: [ 0xe0, 0x87, 0x00, 0x69 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stgp x0, x1, [sp, #16]" + + - + input: + bytes: [ 0x5f, 0x84, 0x00, 0x69 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stgp xzr, x1, [x2, #16]" + + - + input: + bytes: [ 0x40, 0xfc, 0x00, 0x69 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stgp x0, xzr, [x2, #16]" + + - + input: + bytes: [ 0x40, 0x04, 0xa0, 0x69 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stgp x0, x1, [x2, #-1024]!" + + - + input: + bytes: [ 0x40, 0x84, 0x9f, 0x69 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stgp x0, x1, [x2, #1008]!" + + - + input: + bytes: [ 0xe0, 0x87, 0x80, 0x69 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stgp x0, x1, [sp, #16]!" + + - + input: + bytes: [ 0x5f, 0x84, 0x80, 0x69 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stgp xzr, x1, [x2, #16]!" + + - + input: + bytes: [ 0x40, 0xfc, 0x80, 0x69 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stgp x0, xzr, [x2, #16]!" + + - + input: + bytes: [ 0x40, 0x04, 0xa0, 0x68 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stgp x0, x1, [x2], #-1024" + + - + input: + bytes: [ 0x40, 0x84, 0x9f, 0x68 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stgp x0, x1, [x2], #1008" + + - + input: + bytes: [ 0xe0, 0x87, 0x80, 0x68 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stgp x0, x1, [sp], #16" + + - + input: + bytes: [ 0x5f, 0x84, 0x80, 0x68 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stgp xzr, x1, [x2], #16" + + - + input: + bytes: [ 0x40, 0xfc, 0x80, 0x68 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stgp x0, xzr, [x2], #16" + + - + input: + bytes: [ 0x60, 0x76, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "dc igvac, x0" + + - + input: + bytes: [ 0x81, 0x76, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "dc igsw, x1" + + - + input: + bytes: [ 0x82, 0x7a, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "dc cgsw, x2" + + - + input: + bytes: [ 0x83, 0x7e, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "dc cigsw, x3" + + - + input: + bytes: [ 0x64, 0x7a, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "dc cgvac, x4" + + - + input: + bytes: [ 0x65, 0x7c, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "dc cgvap, x5" + + - + input: + bytes: [ 0x66, 0x7d, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "dc cgvadp, x6" + + - + input: + bytes: [ 0x67, 0x7e, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "dc cigvac, x7" + + - + input: + bytes: [ 0x68, 0x74, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "dc gva, x8" + + - + input: + bytes: [ 0xa9, 0x76, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "dc igdvac, x9" + + - + input: + bytes: [ 0xca, 0x76, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "dc igdsw, x10" + + - + input: + bytes: [ 0xcb, 0x7a, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "dc cgdsw, x11" + + - + input: + bytes: [ 0xcc, 0x7e, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "dc cigdsw, x12" + + - + input: + bytes: [ 0xad, 0x7a, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "dc cgdvac, x13" + + - + input: + bytes: [ 0xae, 0x7c, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "dc cgdvap, x14" + + - + input: + bytes: [ 0xaf, 0x7d, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "dc cgdvadp, x15" + + - + input: + bytes: [ 0xb0, 0x7e, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "dc cigdvac, x16" + + - + input: + bytes: [ 0x91, 0x74, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "dc gzva, x17" + + - + input: + bytes: [ 0xe0, 0x42, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "mrs x0, TCO" + + - + input: + bytes: [ 0xc1, 0x10, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "mrs x1, GCR_EL1" + + - + input: + bytes: [ 0xa2, 0x10, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "mrs x2, RGSR_EL1" + + - + input: + bytes: [ 0x03, 0x56, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "mrs x3, TFSR_EL1" + + - + input: + bytes: [ 0x04, 0x56, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "mrs x4, TFSR_EL2" + + - + input: + bytes: [ 0x05, 0x56, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "mrs x5, TFSR_EL3" + + - + input: + bytes: [ 0x06, 0x56, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "mrs x6, TFSR_EL12" + + - + input: + bytes: [ 0x27, 0x56, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "mrs x7, TFSRE0_EL1" + + - + input: + bytes: [ 0x87, 0x00, 0x39, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "mrs x7, GMID_EL1" + + - + input: + bytes: [ 0x9f, 0x40, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "msr TCO, #0" + + - + input: + bytes: [ 0xe0, 0x42, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "msr TCO, x0" + + - + input: + bytes: [ 0xc1, 0x10, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "msr GCR_EL1, x1" + + - + input: + bytes: [ 0xa2, 0x10, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "msr RGSR_EL1, x2" + + - + input: + bytes: [ 0x03, 0x56, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "msr TFSR_EL1, x3" + + - + input: + bytes: [ 0x04, 0x56, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "msr TFSR_EL2, x4" + + - + input: + bytes: [ 0x05, 0x56, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "msr TFSR_EL3, x5" + + - + input: + bytes: [ 0x06, 0x56, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "msr TFSR_EL12, x6" + + - + input: + bytes: [ 0x27, 0x56, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "msr TFSRE0_EL1, x7" + + - + input: + bytes: [ 0x20, 0x00, 0xc2, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "subp x0, x1, x2" + + - + input: + bytes: [ 0xe0, 0x03, 0xdf, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "subp x0, sp, sp" + + - + input: + bytes: [ 0x20, 0x00, 0xc2, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "subps x0, x1, x2" + + - + input: + bytes: [ 0xe0, 0x03, 0xdf, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "subps x0, sp, sp" + + - + input: + bytes: [ 0x1f, 0x00, 0xc1, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "subps xzr, x0, x1" + + - + input: + bytes: [ 0x1f, 0x00, 0xc1, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "subps xzr, x0, x1" + + - + input: + bytes: [ 0xff, 0x03, 0xdf, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "subps xzr, sp, sp" + + - + input: + bytes: [ 0xff, 0x03, 0xdf, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "subps xzr, sp, sp" + + - + input: + bytes: [ 0x20, 0x00, 0x60, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "ldg x0, [x1]" + + - + input: + bytes: [ 0xe2, 0x03, 0x70, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "ldg x2, [sp, #-4096]" + + - + input: + bytes: [ 0x83, 0xf0, 0x6f, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "ldg x3, [x4, #4080]" + + - + input: + bytes: [ 0x20, 0x00, 0xe0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "ldgm x0, [x1]" + + - + input: + bytes: [ 0xe1, 0x03, 0xe0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "ldgm x1, [sp]" + + - + input: + bytes: [ 0x5f, 0x00, 0xe0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "ldgm xzr, [x2]" + + - + input: + bytes: [ 0x20, 0x00, 0xa0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stgm x0, [x1]" + + - + input: + bytes: [ 0xe1, 0x03, 0xa0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stgm x1, [sp]" + + - + input: + bytes: [ 0x5f, 0x00, 0xa0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stgm xzr, [x2]" + + - + input: + bytes: [ 0x20, 0x00, 0x20, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stzgm x0, [x1]" + + - + input: + bytes: [ 0xe1, 0x03, 0x20, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stzgm x1, [sp]" + + - + input: + bytes: [ 0x5f, 0x00, 0x20, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ] + expected: + insns: + - + asm_text: "stzgm xzr, [x2]" diff --git a/tests/MC/AArch64/armv8.5a-persistent-memory.s.yaml b/tests/MC/AArch64/armv8.5a-persistent-memory.s.yaml new file mode 100644 index 0000000000..63be0f267c --- /dev/null +++ b/tests/MC/AArch64/armv8.5a-persistent-memory.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x27, 0x7d, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ccdp" ] + expected: + insns: + - + asm_text: "dc cvadp, x7" + + - + input: + bytes: [ 0x27, 0x7d, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "dc cvadp, x7" diff --git a/tests/MC/AArch64/armv8.5a-predres.s.yaml b/tests/MC/AArch64/armv8.5a-predres.s.yaml new file mode 100644 index 0000000000..b0d4585d9a --- /dev/null +++ b/tests/MC/AArch64/armv8.5a-predres.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x80, 0x73, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "predres" ] + expected: + insns: + - + asm_text: "cfp rctx, x0" + + - + input: + bytes: [ 0xa1, 0x73, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "predres" ] + expected: + insns: + - + asm_text: "dvp rctx, x1" + + - + input: + bytes: [ 0xe2, 0x73, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "predres" ] + expected: + insns: + - + asm_text: "cpp rctx, x2" + + - + input: + bytes: [ 0x80, 0x73, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "cfp rctx, x0" + + - + input: + bytes: [ 0xa1, 0x73, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "dvp rctx, x1" + + - + input: + bytes: [ 0xe2, 0x73, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "cpp rctx, x2" diff --git a/tests/MC/AArch64/armv8.5a-rand.s.yaml b/tests/MC/AArch64/armv8.5a-rand.s.yaml new file mode 100644 index 0000000000..64d81621f3 --- /dev/null +++ b/tests/MC/AArch64/armv8.5a-rand.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x24, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "rand" ] + expected: + insns: + - + asm_text: "mrs x0, RNDR" + + - + input: + bytes: [ 0x21, 0x24, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "rand" ] + expected: + insns: + - + asm_text: "mrs x1, RNDRRS" diff --git a/tests/MC/AArch64/armv8.5a-sb.s.yaml b/tests/MC/AArch64/armv8.5a-sb.s.yaml new file mode 100644 index 0000000000..455376688d --- /dev/null +++ b/tests/MC/AArch64/armv8.5a-sb.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0xff, 0x30, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "sb" ] + expected: + insns: + - + asm_text: "sb" + + - + input: + bytes: [ 0xff, 0x30, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ] + expected: + insns: + - + asm_text: "sb" diff --git a/tests/MC/AArch64/armv8.5a-specrestrict.s.yaml b/tests/MC/AArch64/armv8.5a-specrestrict.s.yaml new file mode 100644 index 0000000000..10460d2741 --- /dev/null +++ b/tests/MC/AArch64/armv8.5a-specrestrict.s.yaml @@ -0,0 +1,220 @@ +test_cases: + - + input: + bytes: [ 0x89, 0x03, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ] + expected: + insns: + - + asm_text: "mrs x9, ID_PFR2_EL1" + + - + input: + bytes: [ 0xe8, 0xd0, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ] + expected: + insns: + - + asm_text: "mrs x8, SCXTNUM_EL0" + + - + input: + bytes: [ 0xe7, 0xd0, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ] + expected: + insns: + - + asm_text: "mrs x7, SCXTNUM_EL1" + + - + input: + bytes: [ 0xe6, 0xd0, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ] + expected: + insns: + - + asm_text: "mrs x6, SCXTNUM_EL2" + + - + input: + bytes: [ 0xe5, 0xd0, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ] + expected: + insns: + - + asm_text: "mrs x5, SCXTNUM_EL3" + + - + input: + bytes: [ 0xe4, 0xd0, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ] + expected: + insns: + - + asm_text: "mrs x4, SCXTNUM_EL12" + + - + input: + bytes: [ 0xe8, 0xd0, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ] + expected: + insns: + - + asm_text: "msr SCXTNUM_EL0, x8" + + - + input: + bytes: [ 0xe7, 0xd0, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ] + expected: + insns: + - + asm_text: "msr SCXTNUM_EL1, x7" + + - + input: + bytes: [ 0xe6, 0xd0, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ] + expected: + insns: + - + asm_text: "msr SCXTNUM_EL2, x6" + + - + input: + bytes: [ 0xe5, 0xd0, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ] + expected: + insns: + - + asm_text: "msr SCXTNUM_EL3, x5" + + - + input: + bytes: [ 0xe4, 0xd0, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ] + expected: + insns: + - + asm_text: "msr SCXTNUM_EL12, x4" + + - + input: + bytes: [ 0x89, 0x03, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ] + expected: + insns: + - + asm_text: "mrs x9, ID_PFR2_EL1" + + - + input: + bytes: [ 0xe8, 0xd0, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ] + expected: + insns: + - + asm_text: "mrs x8, SCXTNUM_EL0" + + - + input: + bytes: [ 0xe7, 0xd0, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ] + expected: + insns: + - + asm_text: "mrs x7, SCXTNUM_EL1" + + - + input: + bytes: [ 0xe6, 0xd0, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ] + expected: + insns: + - + asm_text: "mrs x6, SCXTNUM_EL2" + + - + input: + bytes: [ 0xe5, 0xd0, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ] + expected: + insns: + - + asm_text: "mrs x5, SCXTNUM_EL3" + + - + input: + bytes: [ 0xe4, 0xd0, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ] + expected: + insns: + - + asm_text: "mrs x4, SCXTNUM_EL12" + + - + input: + bytes: [ 0xe8, 0xd0, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ] + expected: + insns: + - + asm_text: "msr SCXTNUM_EL0, x8" + + - + input: + bytes: [ 0xe7, 0xd0, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ] + expected: + insns: + - + asm_text: "msr SCXTNUM_EL1, x7" + + - + input: + bytes: [ 0xe6, 0xd0, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ] + expected: + insns: + - + asm_text: "msr SCXTNUM_EL2, x6" + + - + input: + bytes: [ 0xe5, 0xd0, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ] + expected: + insns: + - + asm_text: "msr SCXTNUM_EL3, x5" + + - + input: + bytes: [ 0xe4, 0xd0, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ] + expected: + insns: + - + asm_text: "msr SCXTNUM_EL12, x4" diff --git a/tests/MC/AArch64/armv8.5a-ssbs.s.yaml b/tests/MC/AArch64/armv8.5a-ssbs.s.yaml new file mode 100644 index 0000000000..a9df26d14a --- /dev/null +++ b/tests/MC/AArch64/armv8.5a-ssbs.s.yaml @@ -0,0 +1,270 @@ +test_cases: + - + input: + bytes: [ 0xc2, 0x42, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssbs" ] + expected: + insns: + - + asm_text: "mrs x2, SSBS" + + - + input: + bytes: [ 0xc3, 0x42, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssbs" ] + expected: + insns: + - + asm_text: "msr SSBS, x3" + + - + input: + bytes: [ 0x3f, 0x41, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssbs" ] + expected: + insns: + - + asm_text: "msr SSBS, #1" + + - + input: + bytes: [ 0xc2, 0x42, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ] + expected: + insns: + - + asm_text: "mrs x2, SSBS" + + - + input: + bytes: [ 0xc3, 0x42, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ] + expected: + insns: + - + asm_text: "msr SSBS, x3" + + - + input: + bytes: [ 0x3f, 0x41, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ] + expected: + insns: + - + asm_text: "msr SSBS, #1" + + - + input: + bytes: [ 0xc2, 0x42, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ] + expected: + insns: + - + asm_text: "mrs x2, SSBS" + + - + input: + bytes: [ 0xc3, 0x42, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ] + expected: + insns: + - + asm_text: "msr SSBS, x3" + + - + input: + bytes: [ 0x3f, 0x41, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ] + expected: + insns: + - + asm_text: "msr SSBS, #1" + + - + input: + bytes: [ 0xc2, 0x42, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ] + expected: + insns: + - + asm_text: "mrs x2, SSBS" + + - + input: + bytes: [ 0xc3, 0x42, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ] + expected: + insns: + - + asm_text: "msr SSBS, x3" + + - + input: + bytes: [ 0x3f, 0x41, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ] + expected: + insns: + - + asm_text: "msr SSBS, #1" + + - + input: + bytes: [ 0xc2, 0x42, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ] + expected: + insns: + - + asm_text: "mrs x2, SSBS" + + - + input: + bytes: [ 0xc3, 0x42, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ] + expected: + insns: + - + asm_text: "msr SSBS, x3" + + - + input: + bytes: [ 0x3f, 0x41, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ] + expected: + insns: + - + asm_text: "msr SSBS, #1" + + - + input: + bytes: [ 0xc2, 0x42, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76ae" ] + expected: + insns: + - + asm_text: "mrs x2, SSBS" + + - + input: + bytes: [ 0xc3, 0x42, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76ae" ] + expected: + insns: + - + asm_text: "msr SSBS, x3" + + - + input: + bytes: [ 0x3f, 0x41, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76ae" ] + expected: + insns: + - + asm_text: "msr SSBS, #1" + + - + input: + bytes: [ 0xc2, 0x42, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ] + expected: + insns: + - + asm_text: "mrs x2, SSBS" + + - + input: + bytes: [ 0xc3, 0x42, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ] + expected: + insns: + - + asm_text: "msr SSBS, x3" + + - + input: + bytes: [ 0x3f, 0x41, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ] + expected: + insns: + - + asm_text: "msr SSBS, #1" + + - + input: + bytes: [ 0xc2, 0x42, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ] + expected: + insns: + - + asm_text: "mrs x2, SSBS" + + - + input: + bytes: [ 0xc3, 0x42, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ] + expected: + insns: + - + asm_text: "msr SSBS, x3" + + - + input: + bytes: [ 0x3f, 0x41, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ] + expected: + insns: + - + asm_text: "msr SSBS, #1" + + - + input: + bytes: [ 0xc2, 0x42, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ] + expected: + insns: + - + asm_text: "mrs x2, SSBS" + + - + input: + bytes: [ 0xc3, 0x42, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ] + expected: + insns: + - + asm_text: "msr SSBS, x3" + + - + input: + bytes: [ 0x3f, 0x41, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ] + expected: + insns: + - + asm_text: "msr SSBS, #1" diff --git a/tests/MC/AArch64/armv8.6a-amvs.s.yaml b/tests/MC/AArch64/armv8.6a-amvs.s.yaml new file mode 100644 index 0000000000..f9732a1638 --- /dev/null +++ b/tests/MC/AArch64/armv8.6a-amvs.s.yaml @@ -0,0 +1,3280 @@ +test_cases: + - + input: + bytes: [ 0xc0, 0xd2, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr S3_3_C13_C2_6, x0" + + - + input: + bytes: [ 0xc0, 0xd2, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMCG1IDR_EL0" + + - + input: + bytes: [ 0x00, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF00_EL2, x0" + + - + input: + bytes: [ 0x20, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF01_EL2, x0" + + - + input: + bytes: [ 0x40, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF02_EL2, x0" + + - + input: + bytes: [ 0x60, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF03_EL2, x0" + + - + input: + bytes: [ 0x80, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF04_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF05_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF06_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF07_EL2, x0" + + - + input: + bytes: [ 0x00, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF08_EL2, x0" + + - + input: + bytes: [ 0x20, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF09_EL2, x0" + + - + input: + bytes: [ 0x40, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF010_EL2, x0" + + - + input: + bytes: [ 0x60, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF011_EL2, x0" + + - + input: + bytes: [ 0x80, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF012_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF013_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF014_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF015_EL2, x0" + + - + input: + bytes: [ 0x00, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF00_EL2" + + - + input: + bytes: [ 0x20, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF01_EL2" + + - + input: + bytes: [ 0x40, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF02_EL2" + + - + input: + bytes: [ 0x60, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF03_EL2" + + - + input: + bytes: [ 0x80, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF04_EL2" + + - + input: + bytes: [ 0xa0, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF05_EL2" + + - + input: + bytes: [ 0xc0, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF06_EL2" + + - + input: + bytes: [ 0xe0, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF07_EL2" + + - + input: + bytes: [ 0x00, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF08_EL2" + + - + input: + bytes: [ 0x20, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF09_EL2" + + - + input: + bytes: [ 0x40, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF010_EL2" + + - + input: + bytes: [ 0x60, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF011_EL2" + + - + input: + bytes: [ 0x80, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF012_EL2" + + - + input: + bytes: [ 0xa0, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF013_EL2" + + - + input: + bytes: [ 0xc0, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF014_EL2" + + - + input: + bytes: [ 0xe0, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF015_EL2" + + - + input: + bytes: [ 0x00, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF10_EL2, x0" + + - + input: + bytes: [ 0x20, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF11_EL2, x0" + + - + input: + bytes: [ 0x40, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF12_EL2, x0" + + - + input: + bytes: [ 0x60, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF13_EL2, x0" + + - + input: + bytes: [ 0x80, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF14_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF15_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF16_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF17_EL2, x0" + + - + input: + bytes: [ 0x00, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF18_EL2, x0" + + - + input: + bytes: [ 0x20, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF19_EL2, x0" + + - + input: + bytes: [ 0x40, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF110_EL2, x0" + + - + input: + bytes: [ 0x60, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF111_EL2, x0" + + - + input: + bytes: [ 0x80, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF112_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF113_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF114_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF115_EL2, x0" + + - + input: + bytes: [ 0x00, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF10_EL2" + + - + input: + bytes: [ 0x20, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF11_EL2" + + - + input: + bytes: [ 0x40, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF12_EL2" + + - + input: + bytes: [ 0x60, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF13_EL2" + + - + input: + bytes: [ 0x80, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF14_EL2" + + - + input: + bytes: [ 0xa0, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF15_EL2" + + - + input: + bytes: [ 0xc0, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF16_EL2" + + - + input: + bytes: [ 0xe0, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF17_EL2" + + - + input: + bytes: [ 0x00, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF18_EL2" + + - + input: + bytes: [ 0x20, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF19_EL2" + + - + input: + bytes: [ 0x40, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF110_EL2" + + - + input: + bytes: [ 0x60, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF111_EL2" + + - + input: + bytes: [ 0x80, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF112_EL2" + + - + input: + bytes: [ 0xa0, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF113_EL2" + + - + input: + bytes: [ 0xc0, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF114_EL2" + + - + input: + bytes: [ 0xe0, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF115_EL2" + + - + input: + bytes: [ 0xc0, 0xd2, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr S3_3_C13_C2_6, x0" + + - + input: + bytes: [ 0xc0, 0xd2, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMCG1IDR_EL0" + + - + input: + bytes: [ 0x00, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF00_EL2, x0" + + - + input: + bytes: [ 0x20, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF01_EL2, x0" + + - + input: + bytes: [ 0x40, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF02_EL2, x0" + + - + input: + bytes: [ 0x60, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF03_EL2, x0" + + - + input: + bytes: [ 0x80, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF04_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF05_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF06_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF07_EL2, x0" + + - + input: + bytes: [ 0x00, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF08_EL2, x0" + + - + input: + bytes: [ 0x20, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF09_EL2, x0" + + - + input: + bytes: [ 0x40, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF010_EL2, x0" + + - + input: + bytes: [ 0x60, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF011_EL2, x0" + + - + input: + bytes: [ 0x80, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF012_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF013_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF014_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF015_EL2, x0" + + - + input: + bytes: [ 0x00, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF00_EL2" + + - + input: + bytes: [ 0x20, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF01_EL2" + + - + input: + bytes: [ 0x40, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF02_EL2" + + - + input: + bytes: [ 0x60, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF03_EL2" + + - + input: + bytes: [ 0x80, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF04_EL2" + + - + input: + bytes: [ 0xa0, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF05_EL2" + + - + input: + bytes: [ 0xc0, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF06_EL2" + + - + input: + bytes: [ 0xe0, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF07_EL2" + + - + input: + bytes: [ 0x00, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF08_EL2" + + - + input: + bytes: [ 0x20, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF09_EL2" + + - + input: + bytes: [ 0x40, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF010_EL2" + + - + input: + bytes: [ 0x60, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF011_EL2" + + - + input: + bytes: [ 0x80, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF012_EL2" + + - + input: + bytes: [ 0xa0, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF013_EL2" + + - + input: + bytes: [ 0xc0, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF014_EL2" + + - + input: + bytes: [ 0xe0, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF015_EL2" + + - + input: + bytes: [ 0x00, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF10_EL2, x0" + + - + input: + bytes: [ 0x20, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF11_EL2, x0" + + - + input: + bytes: [ 0x40, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF12_EL2, x0" + + - + input: + bytes: [ 0x60, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF13_EL2, x0" + + - + input: + bytes: [ 0x80, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF14_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF15_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF16_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF17_EL2, x0" + + - + input: + bytes: [ 0x00, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF18_EL2, x0" + + - + input: + bytes: [ 0x20, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF19_EL2, x0" + + - + input: + bytes: [ 0x40, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF110_EL2, x0" + + - + input: + bytes: [ 0x60, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF111_EL2, x0" + + - + input: + bytes: [ 0x80, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF112_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF113_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF114_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF115_EL2, x0" + + - + input: + bytes: [ 0x00, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF10_EL2" + + - + input: + bytes: [ 0x20, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF11_EL2" + + - + input: + bytes: [ 0x40, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF12_EL2" + + - + input: + bytes: [ 0x60, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF13_EL2" + + - + input: + bytes: [ 0x80, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF14_EL2" + + - + input: + bytes: [ 0xa0, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF15_EL2" + + - + input: + bytes: [ 0xc0, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF16_EL2" + + - + input: + bytes: [ 0xe0, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF17_EL2" + + - + input: + bytes: [ 0x00, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF18_EL2" + + - + input: + bytes: [ 0x20, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF19_EL2" + + - + input: + bytes: [ 0x40, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF110_EL2" + + - + input: + bytes: [ 0x60, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF111_EL2" + + - + input: + bytes: [ 0x80, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF112_EL2" + + - + input: + bytes: [ 0xa0, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF113_EL2" + + - + input: + bytes: [ 0xc0, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF114_EL2" + + - + input: + bytes: [ 0xe0, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF115_EL2" + + - + input: + bytes: [ 0xc0, 0xd2, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr S3_3_C13_C2_6, x0" + + - + input: + bytes: [ 0xc0, 0xd2, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMCG1IDR_EL0" + + - + input: + bytes: [ 0x00, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF00_EL2, x0" + + - + input: + bytes: [ 0x20, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF01_EL2, x0" + + - + input: + bytes: [ 0x40, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF02_EL2, x0" + + - + input: + bytes: [ 0x60, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF03_EL2, x0" + + - + input: + bytes: [ 0x80, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF04_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF05_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF06_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF07_EL2, x0" + + - + input: + bytes: [ 0x00, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF08_EL2, x0" + + - + input: + bytes: [ 0x20, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF09_EL2, x0" + + - + input: + bytes: [ 0x40, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF010_EL2, x0" + + - + input: + bytes: [ 0x60, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF011_EL2, x0" + + - + input: + bytes: [ 0x80, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF012_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF013_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF014_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF015_EL2, x0" + + - + input: + bytes: [ 0x00, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF00_EL2" + + - + input: + bytes: [ 0x20, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF01_EL2" + + - + input: + bytes: [ 0x40, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF02_EL2" + + - + input: + bytes: [ 0x60, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF03_EL2" + + - + input: + bytes: [ 0x80, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF04_EL2" + + - + input: + bytes: [ 0xa0, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF05_EL2" + + - + input: + bytes: [ 0xc0, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF06_EL2" + + - + input: + bytes: [ 0xe0, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF07_EL2" + + - + input: + bytes: [ 0x00, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF08_EL2" + + - + input: + bytes: [ 0x20, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF09_EL2" + + - + input: + bytes: [ 0x40, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF010_EL2" + + - + input: + bytes: [ 0x60, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF011_EL2" + + - + input: + bytes: [ 0x80, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF012_EL2" + + - + input: + bytes: [ 0xa0, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF013_EL2" + + - + input: + bytes: [ 0xc0, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF014_EL2" + + - + input: + bytes: [ 0xe0, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF015_EL2" + + - + input: + bytes: [ 0x00, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF10_EL2, x0" + + - + input: + bytes: [ 0x20, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF11_EL2, x0" + + - + input: + bytes: [ 0x40, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF12_EL2, x0" + + - + input: + bytes: [ 0x60, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF13_EL2, x0" + + - + input: + bytes: [ 0x80, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF14_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF15_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF16_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF17_EL2, x0" + + - + input: + bytes: [ 0x00, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF18_EL2, x0" + + - + input: + bytes: [ 0x20, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF19_EL2, x0" + + - + input: + bytes: [ 0x40, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF110_EL2, x0" + + - + input: + bytes: [ 0x60, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF111_EL2, x0" + + - + input: + bytes: [ 0x80, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF112_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF113_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF114_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF115_EL2, x0" + + - + input: + bytes: [ 0x00, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF10_EL2" + + - + input: + bytes: [ 0x20, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF11_EL2" + + - + input: + bytes: [ 0x40, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF12_EL2" + + - + input: + bytes: [ 0x60, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF13_EL2" + + - + input: + bytes: [ 0x80, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF14_EL2" + + - + input: + bytes: [ 0xa0, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF15_EL2" + + - + input: + bytes: [ 0xc0, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF16_EL2" + + - + input: + bytes: [ 0xe0, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF17_EL2" + + - + input: + bytes: [ 0x00, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF18_EL2" + + - + input: + bytes: [ 0x20, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF19_EL2" + + - + input: + bytes: [ 0x40, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF110_EL2" + + - + input: + bytes: [ 0x60, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF111_EL2" + + - + input: + bytes: [ 0x80, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF112_EL2" + + - + input: + bytes: [ 0xa0, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF113_EL2" + + - + input: + bytes: [ 0xc0, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF114_EL2" + + - + input: + bytes: [ 0xe0, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF115_EL2" + + - + input: + bytes: [ 0xc0, 0xd2, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMCG1IDR_EL0" + + - + input: + bytes: [ 0x00, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF00_EL2, x0" + + - + input: + bytes: [ 0x20, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF01_EL2, x0" + + - + input: + bytes: [ 0x40, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF02_EL2, x0" + + - + input: + bytes: [ 0x60, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF03_EL2, x0" + + - + input: + bytes: [ 0x80, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF04_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF05_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF06_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF07_EL2, x0" + + - + input: + bytes: [ 0x00, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF08_EL2, x0" + + - + input: + bytes: [ 0x20, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF09_EL2, x0" + + - + input: + bytes: [ 0x40, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF010_EL2, x0" + + - + input: + bytes: [ 0x60, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF011_EL2, x0" + + - + input: + bytes: [ 0x80, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF012_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF013_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF014_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF015_EL2, x0" + + - + input: + bytes: [ 0x00, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF00_EL2" + + - + input: + bytes: [ 0x20, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF01_EL2" + + - + input: + bytes: [ 0x40, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF02_EL2" + + - + input: + bytes: [ 0x60, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF03_EL2" + + - + input: + bytes: [ 0x80, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF04_EL2" + + - + input: + bytes: [ 0xa0, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF05_EL2" + + - + input: + bytes: [ 0xc0, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF06_EL2" + + - + input: + bytes: [ 0xe0, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF07_EL2" + + - + input: + bytes: [ 0x00, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF08_EL2" + + - + input: + bytes: [ 0x20, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF09_EL2" + + - + input: + bytes: [ 0x40, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF010_EL2" + + - + input: + bytes: [ 0x60, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF011_EL2" + + - + input: + bytes: [ 0x80, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF012_EL2" + + - + input: + bytes: [ 0xa0, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF013_EL2" + + - + input: + bytes: [ 0xc0, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF014_EL2" + + - + input: + bytes: [ 0xe0, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF015_EL2" + + - + input: + bytes: [ 0x00, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF10_EL2, x0" + + - + input: + bytes: [ 0x20, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF11_EL2, x0" + + - + input: + bytes: [ 0x40, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF12_EL2, x0" + + - + input: + bytes: [ 0x60, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF13_EL2, x0" + + - + input: + bytes: [ 0x80, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF14_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF15_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF16_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF17_EL2, x0" + + - + input: + bytes: [ 0x00, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF18_EL2, x0" + + - + input: + bytes: [ 0x20, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF19_EL2, x0" + + - + input: + bytes: [ 0x40, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF110_EL2, x0" + + - + input: + bytes: [ 0x60, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF111_EL2, x0" + + - + input: + bytes: [ 0x80, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF112_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF113_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF114_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF115_EL2, x0" + + - + input: + bytes: [ 0x00, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF10_EL2" + + - + input: + bytes: [ 0x20, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF11_EL2" + + - + input: + bytes: [ 0x40, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF12_EL2" + + - + input: + bytes: [ 0x60, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF13_EL2" + + - + input: + bytes: [ 0x80, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF14_EL2" + + - + input: + bytes: [ 0xa0, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF15_EL2" + + - + input: + bytes: [ 0xc0, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF16_EL2" + + - + input: + bytes: [ 0xe0, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF17_EL2" + + - + input: + bytes: [ 0x00, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF18_EL2" + + - + input: + bytes: [ 0x20, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF19_EL2" + + - + input: + bytes: [ 0x40, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF110_EL2" + + - + input: + bytes: [ 0x60, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF111_EL2" + + - + input: + bytes: [ 0x80, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF112_EL2" + + - + input: + bytes: [ 0xa0, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF113_EL2" + + - + input: + bytes: [ 0xc0, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF114_EL2" + + - + input: + bytes: [ 0xe0, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF115_EL2" + + - + input: + bytes: [ 0xc0, 0xd2, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMCG1IDR_EL0" + + - + input: + bytes: [ 0x00, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF00_EL2, x0" + + - + input: + bytes: [ 0x20, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF01_EL2, x0" + + - + input: + bytes: [ 0x40, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF02_EL2, x0" + + - + input: + bytes: [ 0x60, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF03_EL2, x0" + + - + input: + bytes: [ 0x80, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF04_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF05_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF06_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xd8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF07_EL2, x0" + + - + input: + bytes: [ 0x00, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF08_EL2, x0" + + - + input: + bytes: [ 0x20, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF09_EL2, x0" + + - + input: + bytes: [ 0x40, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF010_EL2, x0" + + - + input: + bytes: [ 0x60, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF011_EL2, x0" + + - + input: + bytes: [ 0x80, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF012_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF013_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF014_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xd9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF015_EL2, x0" + + - + input: + bytes: [ 0x00, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF00_EL2" + + - + input: + bytes: [ 0x20, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF01_EL2" + + - + input: + bytes: [ 0x40, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF02_EL2" + + - + input: + bytes: [ 0x60, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF03_EL2" + + - + input: + bytes: [ 0x80, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF04_EL2" + + - + input: + bytes: [ 0xa0, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF05_EL2" + + - + input: + bytes: [ 0xc0, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF06_EL2" + + - + input: + bytes: [ 0xe0, 0xd8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF07_EL2" + + - + input: + bytes: [ 0x00, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF08_EL2" + + - + input: + bytes: [ 0x20, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF09_EL2" + + - + input: + bytes: [ 0x40, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF010_EL2" + + - + input: + bytes: [ 0x60, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF011_EL2" + + - + input: + bytes: [ 0x80, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF012_EL2" + + - + input: + bytes: [ 0xa0, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF013_EL2" + + - + input: + bytes: [ 0xc0, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF014_EL2" + + - + input: + bytes: [ 0xe0, 0xd9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF015_EL2" + + - + input: + bytes: [ 0x00, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF10_EL2, x0" + + - + input: + bytes: [ 0x20, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF11_EL2, x0" + + - + input: + bytes: [ 0x40, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF12_EL2, x0" + + - + input: + bytes: [ 0x60, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF13_EL2, x0" + + - + input: + bytes: [ 0x80, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF14_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF15_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF16_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xda, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF17_EL2, x0" + + - + input: + bytes: [ 0x00, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF18_EL2, x0" + + - + input: + bytes: [ 0x20, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF19_EL2, x0" + + - + input: + bytes: [ 0x40, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF110_EL2, x0" + + - + input: + bytes: [ 0x60, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF111_EL2, x0" + + - + input: + bytes: [ 0x80, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF112_EL2, x0" + + - + input: + bytes: [ 0xa0, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF113_EL2, x0" + + - + input: + bytes: [ 0xc0, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF114_EL2, x0" + + - + input: + bytes: [ 0xe0, 0xdb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr AMEVCNTVOFF115_EL2, x0" + + - + input: + bytes: [ 0x00, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF10_EL2" + + - + input: + bytes: [ 0x20, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF11_EL2" + + - + input: + bytes: [ 0x40, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF12_EL2" + + - + input: + bytes: [ 0x60, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF13_EL2" + + - + input: + bytes: [ 0x80, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF14_EL2" + + - + input: + bytes: [ 0xa0, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF15_EL2" + + - + input: + bytes: [ 0xc0, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF16_EL2" + + - + input: + bytes: [ 0xe0, 0xda, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF17_EL2" + + - + input: + bytes: [ 0x00, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF18_EL2" + + - + input: + bytes: [ 0x20, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF19_EL2" + + - + input: + bytes: [ 0x40, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF110_EL2" + + - + input: + bytes: [ 0x60, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF111_EL2" + + - + input: + bytes: [ 0x80, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF112_EL2" + + - + input: + bytes: [ 0xa0, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF113_EL2" + + - + input: + bytes: [ 0xc0, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF114_EL2" + + - + input: + bytes: [ 0xe0, 0xdb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x0, AMEVCNTVOFF115_EL2" diff --git a/tests/MC/AArch64/armv8.6a-bf16.s.yaml b/tests/MC/AArch64/armv8.6a-bf16.s.yaml new file mode 100644 index 0000000000..a94d431ad2 --- /dev/null +++ b/tests/MC/AArch64/armv8.6a-bf16.s.yaml @@ -0,0 +1,690 @@ +test_cases: + - + input: + bytes: [ 0x62, 0xfc, 0x44, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfdot v2.2s, v3.4h, v4.4h" + + - + input: + bytes: [ 0x62, 0xfc, 0x44, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfdot v2.4s, v3.8h, v4.8h" + + - + input: + bytes: [ 0x62, 0xf0, 0x44, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfdot v2.2s, v3.4h, v4.2h[0]" + + - + input: + bytes: [ 0x62, 0xf0, 0x64, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfdot v2.2s, v3.4h, v4.2h[1]" + + - + input: + bytes: [ 0x62, 0xf8, 0x44, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfdot v2.2s, v3.4h, v4.2h[2]" + + - + input: + bytes: [ 0x62, 0xf8, 0x64, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfdot v2.2s, v3.4h, v4.2h[3]" + + - + input: + bytes: [ 0x62, 0xf0, 0x44, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfdot v2.4s, v3.8h, v4.2h[0]" + + - + input: + bytes: [ 0x62, 0xf0, 0x64, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfdot v2.4s, v3.8h, v4.2h[1]" + + - + input: + bytes: [ 0x62, 0xf8, 0x44, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfdot v2.4s, v3.8h, v4.2h[2]" + + - + input: + bytes: [ 0x62, 0xf8, 0x64, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfdot v2.4s, v3.8h, v4.2h[3]" + + - + input: + bytes: [ 0x62, 0xec, 0x44, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfmmla v2.4s, v3.8h, v4.8h" + + - + input: + bytes: [ 0x83, 0xec, 0x45, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfmmla v3.4s, v4.8h, v5.8h" + + - + input: + bytes: [ 0xa5, 0x68, 0xa1, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfcvtn v5.4h, v5.4s" + + - + input: + bytes: [ 0xa5, 0x68, 0xa1, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfcvtn2 v5.8h, v5.4s" + + - + input: + bytes: [ 0x65, 0x40, 0x63, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfcvt h5, s3" + + - + input: + bytes: [ 0xaa, 0xfe, 0xce, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfmlalb v10.4s, v21.8h, v14.8h" + + - + input: + bytes: [ 0xd5, 0xfd, 0xca, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfmlalt v21.4s, v14.8h, v10.8h" + + - + input: + bytes: [ 0xae, 0xf2, 0xda, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfmlalb v14.4s, v21.8h, v10.h[1]" + + - + input: + bytes: [ 0xae, 0xf2, 0xea, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfmlalb v14.4s, v21.8h, v10.h[2]" + + - + input: + bytes: [ 0xae, 0xfa, 0xfa, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfmlalb v14.4s, v21.8h, v10.h[7]" + + - + input: + bytes: [ 0x55, 0xf1, 0xde, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfmlalt v21.4s, v10.8h, v14.h[1]" + + - + input: + bytes: [ 0x55, 0xf1, 0xee, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfmlalt v21.4s, v10.8h, v14.h[2]" + + - + input: + bytes: [ 0x55, 0xf9, 0xfe, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ] + expected: + insns: + - + asm_text: "bfmlalt v21.4s, v10.8h, v14.h[7]" + + - + input: + bytes: [ 0x62, 0xfc, 0x44, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfdot v2.2s, v3.4h, v4.4h" + + - + input: + bytes: [ 0x62, 0xfc, 0x44, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfdot v2.4s, v3.8h, v4.8h" + + - + input: + bytes: [ 0x62, 0xf0, 0x44, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfdot v2.2s, v3.4h, v4.2h[0]" + + - + input: + bytes: [ 0x62, 0xf0, 0x64, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfdot v2.2s, v3.4h, v4.2h[1]" + + - + input: + bytes: [ 0x62, 0xf8, 0x44, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfdot v2.2s, v3.4h, v4.2h[2]" + + - + input: + bytes: [ 0x62, 0xf8, 0x64, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfdot v2.2s, v3.4h, v4.2h[3]" + + - + input: + bytes: [ 0x62, 0xf0, 0x44, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfdot v2.4s, v3.8h, v4.2h[0]" + + - + input: + bytes: [ 0x62, 0xf0, 0x64, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfdot v2.4s, v3.8h, v4.2h[1]" + + - + input: + bytes: [ 0x62, 0xf8, 0x44, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfdot v2.4s, v3.8h, v4.2h[2]" + + - + input: + bytes: [ 0x62, 0xf8, 0x64, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfdot v2.4s, v3.8h, v4.2h[3]" + + - + input: + bytes: [ 0x62, 0xec, 0x44, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfmmla v2.4s, v3.8h, v4.8h" + + - + input: + bytes: [ 0x83, 0xec, 0x45, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfmmla v3.4s, v4.8h, v5.8h" + + - + input: + bytes: [ 0xa5, 0x68, 0xa1, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfcvtn v5.4h, v5.4s" + + - + input: + bytes: [ 0xa5, 0x68, 0xa1, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfcvtn2 v5.8h, v5.4s" + + - + input: + bytes: [ 0x65, 0x40, 0x63, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfcvt h5, s3" + + - + input: + bytes: [ 0xaa, 0xfe, 0xce, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfmlalb v10.4s, v21.8h, v14.8h" + + - + input: + bytes: [ 0xd5, 0xfd, 0xca, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfmlalt v21.4s, v14.8h, v10.8h" + + - + input: + bytes: [ 0xae, 0xf2, 0xda, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfmlalb v14.4s, v21.8h, v10.h[1]" + + - + input: + bytes: [ 0xae, 0xf2, 0xea, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfmlalb v14.4s, v21.8h, v10.h[2]" + + - + input: + bytes: [ 0xae, 0xfa, 0xfa, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfmlalb v14.4s, v21.8h, v10.h[7]" + + - + input: + bytes: [ 0x55, 0xf1, 0xde, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfmlalt v21.4s, v10.8h, v14.h[1]" + + - + input: + bytes: [ 0x55, 0xf1, 0xee, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfmlalt v21.4s, v10.8h, v14.h[2]" + + - + input: + bytes: [ 0x55, 0xf9, 0xfe, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "bfmlalt v21.4s, v10.8h, v14.h[7]" + + - + input: + bytes: [ 0x62, 0xfc, 0x44, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfdot v2.2s, v3.4h, v4.4h" + + - + input: + bytes: [ 0x62, 0xfc, 0x44, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfdot v2.4s, v3.8h, v4.8h" + + - + input: + bytes: [ 0x62, 0xf0, 0x44, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfdot v2.2s, v3.4h, v4.2h[0]" + + - + input: + bytes: [ 0x62, 0xf0, 0x64, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfdot v2.2s, v3.4h, v4.2h[1]" + + - + input: + bytes: [ 0x62, 0xf8, 0x44, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfdot v2.2s, v3.4h, v4.2h[2]" + + - + input: + bytes: [ 0x62, 0xf8, 0x64, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfdot v2.2s, v3.4h, v4.2h[3]" + + - + input: + bytes: [ 0x62, 0xf0, 0x44, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfdot v2.4s, v3.8h, v4.2h[0]" + + - + input: + bytes: [ 0x62, 0xf0, 0x64, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfdot v2.4s, v3.8h, v4.2h[1]" + + - + input: + bytes: [ 0x62, 0xf8, 0x44, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfdot v2.4s, v3.8h, v4.2h[2]" + + - + input: + bytes: [ 0x62, 0xf8, 0x64, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfdot v2.4s, v3.8h, v4.2h[3]" + + - + input: + bytes: [ 0x62, 0xec, 0x44, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfmmla v2.4s, v3.8h, v4.8h" + + - + input: + bytes: [ 0x83, 0xec, 0x45, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfmmla v3.4s, v4.8h, v5.8h" + + - + input: + bytes: [ 0xa5, 0x68, 0xa1, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfcvtn v5.4h, v5.4s" + + - + input: + bytes: [ 0xa5, 0x68, 0xa1, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfcvtn2 v5.8h, v5.4s" + + - + input: + bytes: [ 0x65, 0x40, 0x63, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfcvt h5, s3" + + - + input: + bytes: [ 0xaa, 0xfe, 0xce, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfmlalb v10.4s, v21.8h, v14.8h" + + - + input: + bytes: [ 0xd5, 0xfd, 0xca, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfmlalt v21.4s, v14.8h, v10.8h" + + - + input: + bytes: [ 0xae, 0xf2, 0xda, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfmlalb v14.4s, v21.8h, v10.h[1]" + + - + input: + bytes: [ 0xae, 0xf2, 0xea, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfmlalb v14.4s, v21.8h, v10.h[2]" + + - + input: + bytes: [ 0xae, 0xfa, 0xfa, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfmlalb v14.4s, v21.8h, v10.h[7]" + + - + input: + bytes: [ 0x55, 0xf1, 0xde, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfmlalt v21.4s, v10.8h, v14.h[1]" + + - + input: + bytes: [ 0x55, 0xf1, 0xee, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfmlalt v21.4s, v10.8h, v14.h[2]" + + - + input: + bytes: [ 0x55, 0xf9, 0xfe, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ] + expected: + insns: + - + asm_text: "bfmlalt v21.4s, v10.8h, v14.h[7]" diff --git a/tests/MC/AArch64/armv8.6a-fgt.s.yaml b/tests/MC/AArch64/armv8.6a-fgt.s.yaml new file mode 100644 index 0000000000..58c94d1780 --- /dev/null +++ b/tests/MC/AArch64/armv8.6a-fgt.s.yaml @@ -0,0 +1,440 @@ +test_cases: + - + input: + bytes: [ 0x80, 0x11, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "msr HFGRTR_EL2, x0" + + - + input: + bytes: [ 0xa5, 0x11, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "msr HFGWTR_EL2, x5" + + - + input: + bytes: [ 0xca, 0x11, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "msr HFGITR_EL2, x10" + + - + input: + bytes: [ 0x8f, 0x31, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "msr HDFGRTR_EL2, x15" + + - + input: + bytes: [ 0xb4, 0x31, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "msr HDFGWTR_EL2, x20" + + - + input: + bytes: [ 0xd9, 0x31, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "msr HAFGRTR_EL2, x25" + + - + input: + bytes: [ 0x9e, 0x11, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "mrs x30, HFGRTR_EL2" + + - + input: + bytes: [ 0xb9, 0x11, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "mrs x25, HFGWTR_EL2" + + - + input: + bytes: [ 0xd4, 0x11, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "mrs x20, HFGITR_EL2" + + - + input: + bytes: [ 0x8f, 0x31, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "mrs x15, HDFGRTR_EL2" + + - + input: + bytes: [ 0xaa, 0x31, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "mrs x10, HDFGWTR_EL2" + + - + input: + bytes: [ 0xc5, 0x31, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "mrs x5, HAFGRTR_EL2" + + - + input: + bytes: [ 0x03, 0x31, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "mrs x3, HDFGRTR2_EL2" + + - + input: + bytes: [ 0x23, 0x31, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "mrs x3, HDFGWTR2_EL2" + + - + input: + bytes: [ 0x43, 0x31, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "mrs x3, HFGRTR2_EL2" + + - + input: + bytes: [ 0x63, 0x31, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "mrs x3, HFGWTR2_EL2" + + - + input: + bytes: [ 0xe3, 0x31, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "mrs x3, HFGITR2_EL2" + + - + input: + bytes: [ 0x03, 0x31, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "msr HDFGRTR2_EL2, x3" + + - + input: + bytes: [ 0x23, 0x31, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "msr HDFGWTR2_EL2, x3" + + - + input: + bytes: [ 0x43, 0x31, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "msr HFGRTR2_EL2, x3" + + - + input: + bytes: [ 0x63, 0x31, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "msr HFGWTR2_EL2, x3" + + - + input: + bytes: [ 0xe3, 0x31, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ] + expected: + insns: + - + asm_text: "msr HFGITR2_EL2, x3" + + - + input: + bytes: [ 0x80, 0x11, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr HFGRTR_EL2, x0" + + - + input: + bytes: [ 0xa5, 0x11, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr HFGWTR_EL2, x5" + + - + input: + bytes: [ 0xca, 0x11, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr HFGITR_EL2, x10" + + - + input: + bytes: [ 0x8f, 0x31, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr HDFGRTR_EL2, x15" + + - + input: + bytes: [ 0xb4, 0x31, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr HDFGWTR_EL2, x20" + + - + input: + bytes: [ 0xd9, 0x31, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr HAFGRTR_EL2, x25" + + - + input: + bytes: [ 0x9e, 0x11, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x30, HFGRTR_EL2" + + - + input: + bytes: [ 0xb9, 0x11, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x25, HFGWTR_EL2" + + - + input: + bytes: [ 0xd4, 0x11, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x20, HFGITR_EL2" + + - + input: + bytes: [ 0x8f, 0x31, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x15, HDFGRTR_EL2" + + - + input: + bytes: [ 0xaa, 0x31, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x10, HDFGWTR_EL2" + + - + input: + bytes: [ 0xc5, 0x31, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x5, HAFGRTR_EL2" + + - + input: + bytes: [ 0x03, 0x31, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x3, HDFGRTR2_EL2" + + - + input: + bytes: [ 0x23, 0x31, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x3, HDFGWTR2_EL2" + + - + input: + bytes: [ 0x43, 0x31, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x3, HFGRTR2_EL2" + + - + input: + bytes: [ 0x63, 0x31, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x3, HFGWTR2_EL2" + + - + input: + bytes: [ 0xe3, 0x31, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "mrs x3, HFGITR2_EL2" + + - + input: + bytes: [ 0x03, 0x31, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr HDFGRTR2_EL2, x3" + + - + input: + bytes: [ 0x23, 0x31, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr HDFGWTR2_EL2, x3" + + - + input: + bytes: [ 0x43, 0x31, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr HFGRTR2_EL2, x3" + + - + input: + bytes: [ 0x63, 0x31, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr HFGWTR2_EL2, x3" + + - + input: + bytes: [ 0xe3, 0x31, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "msr HFGITR2_EL2, x3" diff --git a/tests/MC/AArch64/armv8.6a-simd-matmul.s.yaml b/tests/MC/AArch64/armv8.6a-simd-matmul.s.yaml new file mode 100644 index 0000000000..9906268d1d --- /dev/null +++ b/tests/MC/AArch64/armv8.6a-simd-matmul.s.yaml @@ -0,0 +1,180 @@ +test_cases: + - + input: + bytes: [ 0x01, 0xa6, 0x9f, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "i8mm" ] + expected: + insns: + - + asm_text: "smmla v1.4s, v16.16b, v31.16b" + + - + input: + bytes: [ 0x01, 0xa6, 0x9f, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "i8mm" ] + expected: + insns: + - + asm_text: "ummla v1.4s, v16.16b, v31.16b" + + - + input: + bytes: [ 0x01, 0xae, 0x9f, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "i8mm" ] + expected: + insns: + - + asm_text: "usmmla v1.4s, v16.16b, v31.16b" + + - + input: + bytes: [ 0xe3, 0x9d, 0x9e, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "i8mm" ] + expected: + insns: + - + asm_text: "usdot v3.2s, v15.8b, v30.8b" + + - + input: + bytes: [ 0xe3, 0x9d, 0x9e, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "i8mm" ] + expected: + insns: + - + asm_text: "usdot v3.4s, v15.16b, v30.16b" + + - + input: + bytes: [ 0x3f, 0xf8, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "i8mm" ] + expected: + insns: + - + asm_text: "usdot v31.2s, v1.8b, v2.4b[3]" + + - + input: + bytes: [ 0x3f, 0xf8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "i8mm" ] + expected: + insns: + - + asm_text: "usdot v31.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x3f, 0xf8, 0x22, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "i8mm" ] + expected: + insns: + - + asm_text: "sudot v31.2s, v1.8b, v2.4b[3]" + + - + input: + bytes: [ 0x3f, 0xf8, 0x22, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "i8mm" ] + expected: + insns: + - + asm_text: "sudot v31.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x01, 0xa6, 0x9f, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "smmla v1.4s, v16.16b, v31.16b" + + - + input: + bytes: [ 0x01, 0xa6, 0x9f, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "ummla v1.4s, v16.16b, v31.16b" + + - + input: + bytes: [ 0x01, 0xae, 0x9f, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "usmmla v1.4s, v16.16b, v31.16b" + + - + input: + bytes: [ 0xe3, 0x9d, 0x9e, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "usdot v3.2s, v15.8b, v30.8b" + + - + input: + bytes: [ 0xe3, 0x9d, 0x9e, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "usdot v3.4s, v15.16b, v30.16b" + + - + input: + bytes: [ 0x3f, 0xf8, 0xa2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "usdot v31.2s, v1.8b, v2.4b[3]" + + - + input: + bytes: [ 0x3f, 0xf8, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "usdot v31.4s, v1.16b, v2.4b[3]" + + - + input: + bytes: [ 0x3f, 0xf8, 0x22, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "sudot v31.2s, v1.8b, v2.4b[3]" + + - + input: + bytes: [ 0x3f, 0xf8, 0x22, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ] + expected: + insns: + - + asm_text: "sudot v31.4s, v1.16b, v2.4b[3]" diff --git a/tests/MC/AArch64/armv8.7a-hcx.s.yaml b/tests/MC/AArch64/armv8.7a-hcx.s.yaml new file mode 100644 index 0000000000..d6ba83674b --- /dev/null +++ b/tests/MC/AArch64/armv8.7a-hcx.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x42, 0x12, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "hcx" ] + expected: + insns: + - + asm_text: "mrs x2, HCRX_EL2" + + - + input: + bytes: [ 0x43, 0x12, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "hcx" ] + expected: + insns: + - + asm_text: "msr HCRX_EL2, x3" + + - + input: + bytes: [ 0x42, 0x12, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.7a" ] + expected: + insns: + - + asm_text: "mrs x2, HCRX_EL2" + + - + input: + bytes: [ 0x43, 0x12, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.7a" ] + expected: + insns: + - + asm_text: "msr HCRX_EL2, x3" diff --git a/tests/MC/AArch64/armv8.7a-wfxt.s.yaml b/tests/MC/AArch64/armv8.7a-wfxt.s.yaml new file mode 100644 index 0000000000..93d8bcfd09 --- /dev/null +++ b/tests/MC/AArch64/armv8.7a-wfxt.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x11, 0x10, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "wfxt" ] + expected: + insns: + - + asm_text: "wfet x17" + + - + input: + bytes: [ 0x23, 0x10, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "wfxt" ] + expected: + insns: + - + asm_text: "wfit x3" + + - + input: + bytes: [ 0x11, 0x10, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.7a" ] + expected: + insns: + - + asm_text: "wfet x17" + + - + input: + bytes: [ 0x23, 0x10, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.7a" ] + expected: + insns: + - + asm_text: "wfit x3" diff --git a/tests/MC/AArch64/armv8.8a-nmi.s.yaml b/tests/MC/AArch64/armv8.8a-nmi.s.yaml new file mode 100644 index 0000000000..14af955c76 --- /dev/null +++ b/tests/MC/AArch64/armv8.8a-nmi.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x02, 0x43, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "nmi" ] + expected: + insns: + - + asm_text: "mrs x2, ALLINT" + + - + input: + bytes: [ 0x03, 0x43, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "nmi" ] + expected: + insns: + - + asm_text: "msr ALLINT, x3" + + - + input: + bytes: [ 0x1f, 0x41, 0x01, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "nmi" ] + expected: + insns: + - + asm_text: "msr ALLINT, #1" + + - + input: + bytes: [ 0xa7, 0xc9, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "nmi" ] + expected: + insns: + - + asm_text: "mrs x7, ICC_NMIAR1_EL1" + + - + input: + bytes: [ 0x02, 0x43, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.8a" ] + expected: + insns: + - + asm_text: "mrs x2, ALLINT" + + - + input: + bytes: [ 0x03, 0x43, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.8a" ] + expected: + insns: + - + asm_text: "msr ALLINT, x3" + + - + input: + bytes: [ 0x1f, 0x41, 0x01, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.8a" ] + expected: + insns: + - + asm_text: "msr ALLINT, #1" + + - + input: + bytes: [ 0xa7, 0xc9, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.8a" ] + expected: + insns: + - + asm_text: "mrs x7, ICC_NMIAR1_EL1" diff --git a/tests/MC/AArch64/armv8.9a-ats1a.s.yaml b/tests/MC/AArch64/armv8.9a-ats1a.s.yaml new file mode 100644 index 0000000000..a2950c53c8 --- /dev/null +++ b/tests/MC/AArch64/armv8.9a-ats1a.s.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0x41, 0x79, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "at s1e1a, x1" + + - + input: + bytes: [ 0x41, 0x79, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "at s1e2a, x1" + + - + input: + bytes: [ 0x41, 0x79, 0x0e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "at s1e3a, x1" diff --git a/tests/MC/AArch64/armv8.9a-clrbhb.s.yaml b/tests/MC/AArch64/armv8.9a-clrbhb.s.yaml new file mode 100644 index 0000000000..0ec8475fc0 --- /dev/null +++ b/tests/MC/AArch64/armv8.9a-clrbhb.s.yaml @@ -0,0 +1,420 @@ +test_cases: + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8a" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8a" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.8a" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.8a" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9a" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9a" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.3a" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.3a" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "-clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "-clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8a", "-clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8a", "-clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.8a", "-clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.8a", "-clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9a", "-clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9a", "-clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.3a", "-clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.3a", "-clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8a", "+clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8a", "+clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.8a", "+clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.8a", "+clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9a", "+clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9a", "+clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.3a", "+clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.3a", "+clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.9a" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.9a" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.4a" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.4a" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.9a", "+clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.9a", "+clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.4a", "+clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.4a", "+clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.9a", "-clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.9a", "-clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.4a", "-clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" + + - + input: + bytes: [ 0xdf, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.4a", "-clrbhb" ] + expected: + insns: + - + asm_text: "clrbhb" diff --git a/tests/MC/AArch64/armv8.9a-cssc.s.yaml b/tests/MC/AArch64/armv8.9a-cssc.s.yaml new file mode 100644 index 0000000000..4d8889dab0 --- /dev/null +++ b/tests/MC/AArch64/armv8.9a-cssc.s.yaml @@ -0,0 +1,600 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x20, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "abs x0, x1" + + - + input: + bytes: [ 0x20, 0x20, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "abs w0, w1" + + - + input: + bytes: [ 0x20, 0x1c, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "cnt x0, x1" + + - + input: + bytes: [ 0x20, 0x1c, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "cnt w0, w1" + + - + input: + bytes: [ 0x20, 0x18, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "ctz x0, x1" + + - + input: + bytes: [ 0x20, 0x18, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "ctz w0, w1" + + - + input: + bytes: [ 0x41, 0x60, 0xc3, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "smax x1, x2, x3" + + - + input: + bytes: [ 0x41, 0x0c, 0xc0, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "smax x1, x2, #3" + + - + input: + bytes: [ 0x41, 0x60, 0xc3, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "smax w1, w2, w3" + + - + input: + bytes: [ 0x41, 0x0c, 0xc0, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "smax w1, w2, #3" + + - + input: + bytes: [ 0x41, 0x68, 0xc3, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "smin x1, x2, x3" + + - + input: + bytes: [ 0x41, 0x0c, 0xc8, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "smin x1, x2, #3" + + - + input: + bytes: [ 0x41, 0x68, 0xc3, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "smin w1, w2, w3" + + - + input: + bytes: [ 0x41, 0x0c, 0xc8, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "smin w1, w2, #3" + + - + input: + bytes: [ 0x41, 0x64, 0xc3, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "umax x1, x2, x3" + + - + input: + bytes: [ 0x41, 0x0c, 0xc4, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "umax x1, x2, #3" + + - + input: + bytes: [ 0x41, 0x64, 0xc3, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "umax w1, w2, w3" + + - + input: + bytes: [ 0x41, 0x0c, 0xc4, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "umax w1, w2, #3" + + - + input: + bytes: [ 0x41, 0x6c, 0xc3, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "umin x1, x2, x3" + + - + input: + bytes: [ 0x41, 0x0c, 0xcc, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "umin x1, x2, #3" + + - + input: + bytes: [ 0x41, 0x6c, 0xc3, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "umin w1, w2, w3" + + - + input: + bytes: [ 0x41, 0x0c, 0xcc, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "umin w1, w2, #3" + + - + input: + bytes: [ 0xff, 0xff, 0xc7, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "umax wzr, wzr, #255" + + - + input: + bytes: [ 0xff, 0xff, 0xc7, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "umax xzr, xzr, #255" + + - + input: + bytes: [ 0xff, 0xff, 0xcf, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "umin xzr, xzr, #255" + + - + input: + bytes: [ 0xff, 0xff, 0xcf, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "umin wzr, wzr, #255" + + - + input: + bytes: [ 0xff, 0xff, 0xc3, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "smax xzr, xzr, #-1" + + - + input: + bytes: [ 0xff, 0xff, 0xc3, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "smax wzr, wzr, #-1" + + - + input: + bytes: [ 0xff, 0xff, 0xcb, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "smin xzr, xzr, #-1" + + - + input: + bytes: [ 0xff, 0xff, 0xcb, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "smin wzr, wzr, #-1" + + - + input: + bytes: [ 0x20, 0x20, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "abs x0, x1" + + - + input: + bytes: [ 0x20, 0x20, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "abs w0, w1" + + - + input: + bytes: [ 0x20, 0x1c, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "cnt x0, x1" + + - + input: + bytes: [ 0x20, 0x1c, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "cnt w0, w1" + + - + input: + bytes: [ 0x20, 0x18, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "ctz x0, x1" + + - + input: + bytes: [ 0x20, 0x18, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "ctz w0, w1" + + - + input: + bytes: [ 0x41, 0x60, 0xc3, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "smax x1, x2, x3" + + - + input: + bytes: [ 0x41, 0x0c, 0xc0, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "smax x1, x2, #3" + + - + input: + bytes: [ 0x41, 0x60, 0xc3, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "smax w1, w2, w3" + + - + input: + bytes: [ 0x41, 0x0c, 0xc0, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "smax w1, w2, #3" + + - + input: + bytes: [ 0x41, 0x68, 0xc3, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "smin x1, x2, x3" + + - + input: + bytes: [ 0x41, 0x0c, 0xc8, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "smin x1, x2, #3" + + - + input: + bytes: [ 0x41, 0x68, 0xc3, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "smin w1, w2, w3" + + - + input: + bytes: [ 0x41, 0x0c, 0xc8, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "smin w1, w2, #3" + + - + input: + bytes: [ 0x41, 0x64, 0xc3, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "umax x1, x2, x3" + + - + input: + bytes: [ 0x41, 0x0c, 0xc4, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "umax x1, x2, #3" + + - + input: + bytes: [ 0x41, 0x64, 0xc3, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "umax w1, w2, w3" + + - + input: + bytes: [ 0x41, 0x0c, 0xc4, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "umax w1, w2, #3" + + - + input: + bytes: [ 0x41, 0x6c, 0xc3, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "umin x1, x2, x3" + + - + input: + bytes: [ 0x41, 0x0c, 0xcc, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "umin x1, x2, #3" + + - + input: + bytes: [ 0x41, 0x6c, 0xc3, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "umin w1, w2, w3" + + - + input: + bytes: [ 0x41, 0x0c, 0xcc, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "umin w1, w2, #3" + + - + input: + bytes: [ 0xff, 0xff, 0xc7, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "umax wzr, wzr, #255" + + - + input: + bytes: [ 0xff, 0xff, 0xc7, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "umax xzr, xzr, #255" + + - + input: + bytes: [ 0xff, 0xff, 0xcf, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "umin xzr, xzr, #255" + + - + input: + bytes: [ 0xff, 0xff, 0xcf, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "umin wzr, wzr, #255" + + - + input: + bytes: [ 0xff, 0xff, 0xc3, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "smax xzr, xzr, #-1" + + - + input: + bytes: [ 0xff, 0xff, 0xc3, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "smax wzr, wzr, #-1" + + - + input: + bytes: [ 0xff, 0xff, 0xcb, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "smin xzr, xzr, #-1" + + - + input: + bytes: [ 0xff, 0xff, 0xcb, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "smin wzr, wzr, #-1" diff --git a/tests/MC/AArch64/armv8.9a-debug-pmu.s.yaml b/tests/MC/AArch64/armv8.9a-debug-pmu.s.yaml new file mode 100644 index 0000000000..4152b0c1de --- /dev/null +++ b/tests/MC/AArch64/armv8.9a-debug-pmu.s.yaml @@ -0,0 +1,11050 @@ +test_cases: + - + input: + bytes: [ 0x43, 0x04, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, MDSELR_EL1" + + - + input: + bytes: [ 0x41, 0x04, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr MDSELR_EL1, x1" + + - + input: + bytes: [ 0x83, 0x9e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMUACR_EL1" + + - + input: + bytes: [ 0x81, 0x9e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr PMUACR_EL1, x1" + + - + input: + bytes: [ 0xe3, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMCCNTSVR_EL1" + + - + input: + bytes: [ 0x03, 0xec, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMICNTSVR_EL1" + + - + input: + bytes: [ 0x63, 0x9d, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMSSCR_EL1" + + - + input: + bytes: [ 0x61, 0x9d, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr PMSSCR_EL1, x1" + + - + input: + bytes: [ 0x03, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR0_EL1" + + - + input: + bytes: [ 0x23, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR1_EL1" + + - + input: + bytes: [ 0x43, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR2_EL1" + + - + input: + bytes: [ 0x63, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR3_EL1" + + - + input: + bytes: [ 0x83, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR4_EL1" + + - + input: + bytes: [ 0xa3, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR5_EL1" + + - + input: + bytes: [ 0xc3, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR6_EL1" + + - + input: + bytes: [ 0xe3, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR7_EL1" + + - + input: + bytes: [ 0x03, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR8_EL1" + + - + input: + bytes: [ 0x23, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR9_EL1" + + - + input: + bytes: [ 0x43, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR10_EL1" + + - + input: + bytes: [ 0x63, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR11_EL1" + + - + input: + bytes: [ 0x83, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR12_EL1" + + - + input: + bytes: [ 0xa3, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR13_EL1" + + - + input: + bytes: [ 0xc3, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR14_EL1" + + - + input: + bytes: [ 0xe3, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR15_EL1" + + - + input: + bytes: [ 0x03, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR16_EL1" + + - + input: + bytes: [ 0x23, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR17_EL1" + + - + input: + bytes: [ 0x43, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR18_EL1" + + - + input: + bytes: [ 0x63, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR19_EL1" + + - + input: + bytes: [ 0x83, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR20_EL1" + + - + input: + bytes: [ 0xa3, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR21_EL1" + + - + input: + bytes: [ 0xc3, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR22_EL1" + + - + input: + bytes: [ 0xe3, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR23_EL1" + + - + input: + bytes: [ 0x03, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR24_EL1" + + - + input: + bytes: [ 0x23, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR25_EL1" + + - + input: + bytes: [ 0x43, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR26_EL1" + + - + input: + bytes: [ 0x63, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR27_EL1" + + - + input: + bytes: [ 0x83, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR28_EL1" + + - + input: + bytes: [ 0xa3, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR29_EL1" + + - + input: + bytes: [ 0xc3, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR30_EL1" + + - + input: + bytes: [ 0x03, 0x94, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMICNTR_EL0" + + - + input: + bytes: [ 0x03, 0x94, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr PMICNTR_EL0, x3" + + - + input: + bytes: [ 0x03, 0x96, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMICFILTR_EL0" + + - + input: + bytes: [ 0x03, 0x96, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr PMICFILTR_EL0, x3" + + - + input: + bytes: [ 0x83, 0x9d, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr PMZR_EL0, x3" + + - + input: + bytes: [ 0xa3, 0x9e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMECR_EL1" + + - + input: + bytes: [ 0xa1, 0x9e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr PMECR_EL1, x1" + + - + input: + bytes: [ 0xe3, 0x9e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMIAR_EL1" + + - + input: + bytes: [ 0xe1, 0x9e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr PMIAR_EL1, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL1" + + - + input: + bytes: [ 0x61, 0x9d, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL1, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x35, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL12" + + - + input: + bytes: [ 0x61, 0x9d, 0x15, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL12, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x34, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL2" + + - + input: + bytes: [ 0x61, 0x9d, 0x14, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL2, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x36, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL3" + + - + input: + bytes: [ 0x61, 0x9d, 0x16, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL3, x1" + + - + input: + bytes: [ 0x43, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCNTENCLR_EL0" + + - + input: + bytes: [ 0x41, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMCNTENCLR_EL0, x1" + + - + input: + bytes: [ 0x23, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCNTENSET_EL0" + + - + input: + bytes: [ 0x21, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMCNTENSET_EL0, x1" + + - + input: + bytes: [ 0x03, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCR_EL0" + + - + input: + bytes: [ 0x01, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMCR_EL0, x1" + + - + input: + bytes: [ 0xc3, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMDEVAFF_EL1" + + - + input: + bytes: [ 0xa3, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMDEVARCH_EL1" + + - + input: + bytes: [ 0x03, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR0_EL0" + + - + input: + bytes: [ 0x01, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR1_EL0" + + - + input: + bytes: [ 0x21, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR2_EL0" + + - + input: + bytes: [ 0x41, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR3_EL0" + + - + input: + bytes: [ 0x61, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR4_EL0" + + - + input: + bytes: [ 0x81, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR5_EL0" + + - + input: + bytes: [ 0xa1, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR6_EL0" + + - + input: + bytes: [ 0xc1, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR7_EL0" + + - + input: + bytes: [ 0xe1, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR8_EL0" + + - + input: + bytes: [ 0x01, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR9_EL0" + + - + input: + bytes: [ 0x21, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR10_EL0" + + - + input: + bytes: [ 0x41, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR11_EL0" + + - + input: + bytes: [ 0x61, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR12_EL0" + + - + input: + bytes: [ 0x81, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR13_EL0" + + - + input: + bytes: [ 0xa1, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR14_EL0" + + - + input: + bytes: [ 0xc1, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR15_EL0" + + - + input: + bytes: [ 0xe1, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR15_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R0_EL0" + + - + input: + bytes: [ 0x01, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R1_EL0" + + - + input: + bytes: [ 0x21, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R2_EL0" + + - + input: + bytes: [ 0x41, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R3_EL0" + + - + input: + bytes: [ 0x61, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R4_EL0" + + - + input: + bytes: [ 0x81, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R5_EL0" + + - + input: + bytes: [ 0xa1, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R6_EL0" + + - + input: + bytes: [ 0xc1, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R7_EL0" + + - + input: + bytes: [ 0xe1, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R8_EL0" + + - + input: + bytes: [ 0x01, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R9_EL0" + + - + input: + bytes: [ 0x21, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R10_EL0" + + - + input: + bytes: [ 0x41, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R11_EL0" + + - + input: + bytes: [ 0x61, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R12_EL0" + + - + input: + bytes: [ 0x81, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R13_EL0" + + - + input: + bytes: [ 0xa1, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R14_EL0" + + - + input: + bytes: [ 0xc1, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R15_EL0" + + - + input: + bytes: [ 0xe1, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R15_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR0_EL0" + + - + input: + bytes: [ 0x01, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR1_EL0" + + - + input: + bytes: [ 0x21, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR2_EL0" + + - + input: + bytes: [ 0x41, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR3_EL0" + + - + input: + bytes: [ 0x61, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR4_EL0" + + - + input: + bytes: [ 0x81, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR5_EL0" + + - + input: + bytes: [ 0xa1, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR6_EL0" + + - + input: + bytes: [ 0xc1, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR7_EL0" + + - + input: + bytes: [ 0xe1, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR8_EL0" + + - + input: + bytes: [ 0x01, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR9_EL0" + + - + input: + bytes: [ 0x21, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR10_EL0" + + - + input: + bytes: [ 0x41, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR11_EL0" + + - + input: + bytes: [ 0x61, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR12_EL0" + + - + input: + bytes: [ 0x81, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR13_EL0" + + - + input: + bytes: [ 0xa1, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR14_EL0" + + - + input: + bytes: [ 0xc1, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR15_EL0" + + - + input: + bytes: [ 0xe1, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR15_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER0_EL0" + + - + input: + bytes: [ 0x01, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER1_EL0" + + - + input: + bytes: [ 0x21, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER2_EL0" + + - + input: + bytes: [ 0x41, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER3_EL0" + + - + input: + bytes: [ 0x61, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER4_EL0" + + - + input: + bytes: [ 0x81, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER5_EL0" + + - + input: + bytes: [ 0xa1, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER6_EL0" + + - + input: + bytes: [ 0xc1, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER7_EL0" + + - + input: + bytes: [ 0xe1, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER8_EL0" + + - + input: + bytes: [ 0x01, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER9_EL0" + + - + input: + bytes: [ 0x21, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER10_EL0" + + - + input: + bytes: [ 0x41, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER11_EL0" + + - + input: + bytes: [ 0x61, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER12_EL0" + + - + input: + bytes: [ 0x81, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER13_EL0" + + - + input: + bytes: [ 0xa1, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER14_EL0" + + - + input: + bytes: [ 0xc1, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER15_EL0" + + - + input: + bytes: [ 0xe1, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER15_EL0, x1" + + - + input: + bytes: [ 0x83, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMIIDR_EL1" + + - + input: + bytes: [ 0x43, 0x9e, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMINTENCLR_EL1" + + - + input: + bytes: [ 0x41, 0x9e, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMINTENCLR_EL1, x1" + + - + input: + bytes: [ 0x23, 0x9e, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMINTENSET_EL1" + + - + input: + bytes: [ 0x21, 0x9e, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMINTENSET_EL1, x1" + + - + input: + bytes: [ 0x63, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMOVSCLR_EL0" + + - + input: + bytes: [ 0x61, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMOVSCLR_EL0, x1" + + - + input: + bytes: [ 0x63, 0x9e, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMOVSSET_EL0" + + - + input: + bytes: [ 0x61, 0x9e, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMOVSSET_EL0, x1" + + - + input: + bytes: [ 0xa3, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMSELR_EL0" + + - + input: + bytes: [ 0xa1, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMSELR_EL0, x1" + + - + input: + bytes: [ 0x03, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCGCR0_EL1" + + - + input: + bytes: [ 0x23, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCGCR1_EL1" + + - + input: + bytes: [ 0xe3, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCFGR_EL1" + + - + input: + bytes: [ 0xe3, 0x9e, 0x36, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMROOTCR_EL3" + + - + input: + bytes: [ 0xe3, 0x9e, 0x16, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMROOTCR_EL3, x3" + + - + input: + bytes: [ 0xe3, 0x9e, 0x37, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMSCR_EL1" + + - + input: + bytes: [ 0xe3, 0x9e, 0x17, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr SPMSCR_EL1, x3" + + - + input: + bytes: [ 0x23, 0x02, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITEEDCR" + + - + input: + bytes: [ 0x23, 0x02, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITEEDCR, x3" + + - + input: + bytes: [ 0x63, 0x12, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITECR_EL1" + + - + input: + bytes: [ 0x61, 0x12, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITECR_EL1, x1" + + - + input: + bytes: [ 0x63, 0x12, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITECR_EL12" + + - + input: + bytes: [ 0x61, 0x12, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITECR_EL12, x1" + + - + input: + bytes: [ 0x63, 0x12, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITECR_EL2" + + - + input: + bytes: [ 0x61, 0x12, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITECR_EL2, x1" + + - + input: + bytes: [ 0xe1, 0x72, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "trcit x1" + + - + input: + bytes: [ 0x83, 0x9a, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMSDSFR_EL1" + + - + input: + bytes: [ 0x83, 0x9a, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ] + expected: + insns: + - + asm_text: "msr PMSDSFR_EL1, x3" + + - + input: + bytes: [ 0x43, 0x04, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, MDSELR_EL1" + + - + input: + bytes: [ 0x41, 0x04, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr MDSELR_EL1, x1" + + - + input: + bytes: [ 0x83, 0x9e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMUACR_EL1" + + - + input: + bytes: [ 0x81, 0x9e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr PMUACR_EL1, x1" + + - + input: + bytes: [ 0xe3, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMCCNTSVR_EL1" + + - + input: + bytes: [ 0x03, 0xec, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMICNTSVR_EL1" + + - + input: + bytes: [ 0x63, 0x9d, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMSSCR_EL1" + + - + input: + bytes: [ 0x61, 0x9d, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr PMSSCR_EL1, x1" + + - + input: + bytes: [ 0x03, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR0_EL1" + + - + input: + bytes: [ 0x23, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR1_EL1" + + - + input: + bytes: [ 0x43, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR2_EL1" + + - + input: + bytes: [ 0x63, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR3_EL1" + + - + input: + bytes: [ 0x83, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR4_EL1" + + - + input: + bytes: [ 0xa3, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR5_EL1" + + - + input: + bytes: [ 0xc3, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR6_EL1" + + - + input: + bytes: [ 0xe3, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR7_EL1" + + - + input: + bytes: [ 0x03, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR8_EL1" + + - + input: + bytes: [ 0x23, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR9_EL1" + + - + input: + bytes: [ 0x43, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR10_EL1" + + - + input: + bytes: [ 0x63, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR11_EL1" + + - + input: + bytes: [ 0x83, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR12_EL1" + + - + input: + bytes: [ 0xa3, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR13_EL1" + + - + input: + bytes: [ 0xc3, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR14_EL1" + + - + input: + bytes: [ 0xe3, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR15_EL1" + + - + input: + bytes: [ 0x03, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR16_EL1" + + - + input: + bytes: [ 0x23, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR17_EL1" + + - + input: + bytes: [ 0x43, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR18_EL1" + + - + input: + bytes: [ 0x63, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR19_EL1" + + - + input: + bytes: [ 0x83, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR20_EL1" + + - + input: + bytes: [ 0xa3, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR21_EL1" + + - + input: + bytes: [ 0xc3, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR22_EL1" + + - + input: + bytes: [ 0xe3, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR23_EL1" + + - + input: + bytes: [ 0x03, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR24_EL1" + + - + input: + bytes: [ 0x23, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR25_EL1" + + - + input: + bytes: [ 0x43, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR26_EL1" + + - + input: + bytes: [ 0x63, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR27_EL1" + + - + input: + bytes: [ 0x83, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR28_EL1" + + - + input: + bytes: [ 0xa3, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR29_EL1" + + - + input: + bytes: [ 0xc3, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR30_EL1" + + - + input: + bytes: [ 0x03, 0x94, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMICNTR_EL0" + + - + input: + bytes: [ 0x03, 0x94, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr PMICNTR_EL0, x3" + + - + input: + bytes: [ 0x03, 0x96, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMICFILTR_EL0" + + - + input: + bytes: [ 0x03, 0x96, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr PMICFILTR_EL0, x3" + + - + input: + bytes: [ 0x83, 0x9d, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr PMZR_EL0, x3" + + - + input: + bytes: [ 0xa3, 0x9e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMECR_EL1" + + - + input: + bytes: [ 0xa1, 0x9e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr PMECR_EL1, x1" + + - + input: + bytes: [ 0xe3, 0x9e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMIAR_EL1" + + - + input: + bytes: [ 0xe1, 0x9e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr PMIAR_EL1, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL1" + + - + input: + bytes: [ 0x61, 0x9d, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL1, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x35, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL12" + + - + input: + bytes: [ 0x61, 0x9d, 0x15, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL12, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x34, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL2" + + - + input: + bytes: [ 0x61, 0x9d, 0x14, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL2, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x36, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL3" + + - + input: + bytes: [ 0x61, 0x9d, 0x16, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL3, x1" + + - + input: + bytes: [ 0x43, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCNTENCLR_EL0" + + - + input: + bytes: [ 0x41, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMCNTENCLR_EL0, x1" + + - + input: + bytes: [ 0x23, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCNTENSET_EL0" + + - + input: + bytes: [ 0x21, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMCNTENSET_EL0, x1" + + - + input: + bytes: [ 0x03, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCR_EL0" + + - + input: + bytes: [ 0x01, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMCR_EL0, x1" + + - + input: + bytes: [ 0xc3, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMDEVAFF_EL1" + + - + input: + bytes: [ 0xa3, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMDEVARCH_EL1" + + - + input: + bytes: [ 0x03, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR0_EL0" + + - + input: + bytes: [ 0x01, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR1_EL0" + + - + input: + bytes: [ 0x21, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR2_EL0" + + - + input: + bytes: [ 0x41, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR3_EL0" + + - + input: + bytes: [ 0x61, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR4_EL0" + + - + input: + bytes: [ 0x81, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR5_EL0" + + - + input: + bytes: [ 0xa1, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR6_EL0" + + - + input: + bytes: [ 0xc1, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR7_EL0" + + - + input: + bytes: [ 0xe1, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR8_EL0" + + - + input: + bytes: [ 0x01, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR9_EL0" + + - + input: + bytes: [ 0x21, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR10_EL0" + + - + input: + bytes: [ 0x41, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR11_EL0" + + - + input: + bytes: [ 0x61, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR12_EL0" + + - + input: + bytes: [ 0x81, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR13_EL0" + + - + input: + bytes: [ 0xa1, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR14_EL0" + + - + input: + bytes: [ 0xc1, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR15_EL0" + + - + input: + bytes: [ 0xe1, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR15_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R0_EL0" + + - + input: + bytes: [ 0x01, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R1_EL0" + + - + input: + bytes: [ 0x21, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R2_EL0" + + - + input: + bytes: [ 0x41, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R3_EL0" + + - + input: + bytes: [ 0x61, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R4_EL0" + + - + input: + bytes: [ 0x81, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R5_EL0" + + - + input: + bytes: [ 0xa1, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R6_EL0" + + - + input: + bytes: [ 0xc1, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R7_EL0" + + - + input: + bytes: [ 0xe1, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R8_EL0" + + - + input: + bytes: [ 0x01, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R9_EL0" + + - + input: + bytes: [ 0x21, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R10_EL0" + + - + input: + bytes: [ 0x41, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R11_EL0" + + - + input: + bytes: [ 0x61, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R12_EL0" + + - + input: + bytes: [ 0x81, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R13_EL0" + + - + input: + bytes: [ 0xa1, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R14_EL0" + + - + input: + bytes: [ 0xc1, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R15_EL0" + + - + input: + bytes: [ 0xe1, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R15_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR0_EL0" + + - + input: + bytes: [ 0x01, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR1_EL0" + + - + input: + bytes: [ 0x21, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR2_EL0" + + - + input: + bytes: [ 0x41, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR3_EL0" + + - + input: + bytes: [ 0x61, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR4_EL0" + + - + input: + bytes: [ 0x81, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR5_EL0" + + - + input: + bytes: [ 0xa1, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR6_EL0" + + - + input: + bytes: [ 0xc1, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR7_EL0" + + - + input: + bytes: [ 0xe1, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR8_EL0" + + - + input: + bytes: [ 0x01, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR9_EL0" + + - + input: + bytes: [ 0x21, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR10_EL0" + + - + input: + bytes: [ 0x41, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR11_EL0" + + - + input: + bytes: [ 0x61, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR12_EL0" + + - + input: + bytes: [ 0x81, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR13_EL0" + + - + input: + bytes: [ 0xa1, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR14_EL0" + + - + input: + bytes: [ 0xc1, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR15_EL0" + + - + input: + bytes: [ 0xe1, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR15_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER0_EL0" + + - + input: + bytes: [ 0x01, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER1_EL0" + + - + input: + bytes: [ 0x21, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER2_EL0" + + - + input: + bytes: [ 0x41, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER3_EL0" + + - + input: + bytes: [ 0x61, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER4_EL0" + + - + input: + bytes: [ 0x81, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER5_EL0" + + - + input: + bytes: [ 0xa1, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER6_EL0" + + - + input: + bytes: [ 0xc1, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER7_EL0" + + - + input: + bytes: [ 0xe1, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER8_EL0" + + - + input: + bytes: [ 0x01, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER9_EL0" + + - + input: + bytes: [ 0x21, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER10_EL0" + + - + input: + bytes: [ 0x41, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER11_EL0" + + - + input: + bytes: [ 0x61, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER12_EL0" + + - + input: + bytes: [ 0x81, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER13_EL0" + + - + input: + bytes: [ 0xa1, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER14_EL0" + + - + input: + bytes: [ 0xc1, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER15_EL0" + + - + input: + bytes: [ 0xe1, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER15_EL0, x1" + + - + input: + bytes: [ 0x83, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMIIDR_EL1" + + - + input: + bytes: [ 0x43, 0x9e, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMINTENCLR_EL1" + + - + input: + bytes: [ 0x41, 0x9e, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMINTENCLR_EL1, x1" + + - + input: + bytes: [ 0x23, 0x9e, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMINTENSET_EL1" + + - + input: + bytes: [ 0x21, 0x9e, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMINTENSET_EL1, x1" + + - + input: + bytes: [ 0x63, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMOVSCLR_EL0" + + - + input: + bytes: [ 0x61, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMOVSCLR_EL0, x1" + + - + input: + bytes: [ 0x63, 0x9e, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMOVSSET_EL0" + + - + input: + bytes: [ 0x61, 0x9e, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMOVSSET_EL0, x1" + + - + input: + bytes: [ 0xa3, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMSELR_EL0" + + - + input: + bytes: [ 0xa1, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMSELR_EL0, x1" + + - + input: + bytes: [ 0x03, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCGCR0_EL1" + + - + input: + bytes: [ 0x23, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCGCR1_EL1" + + - + input: + bytes: [ 0xe3, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCFGR_EL1" + + - + input: + bytes: [ 0xe3, 0x9e, 0x36, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMROOTCR_EL3" + + - + input: + bytes: [ 0xe3, 0x9e, 0x16, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMROOTCR_EL3, x3" + + - + input: + bytes: [ 0xe3, 0x9e, 0x37, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMSCR_EL1" + + - + input: + bytes: [ 0xe3, 0x9e, 0x17, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMSCR_EL1, x3" + + - + input: + bytes: [ 0x23, 0x02, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITEEDCR" + + - + input: + bytes: [ 0x23, 0x02, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITEEDCR, x3" + + - + input: + bytes: [ 0x63, 0x12, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITECR_EL1" + + - + input: + bytes: [ 0x61, 0x12, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITECR_EL1, x1" + + - + input: + bytes: [ 0x63, 0x12, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITECR_EL12" + + - + input: + bytes: [ 0x61, 0x12, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITECR_EL12, x1" + + - + input: + bytes: [ 0x63, 0x12, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITECR_EL2" + + - + input: + bytes: [ 0x61, 0x12, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITECR_EL2, x1" + + - + input: + bytes: [ 0xe1, 0x72, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "trcit x1" + + - + input: + bytes: [ 0x83, 0x9a, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMSDSFR_EL1" + + - + input: + bytes: [ 0x83, 0x9a, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ] + expected: + insns: + - + asm_text: "msr PMSDSFR_EL1, x3" + + - + input: + bytes: [ 0x43, 0x04, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, MDSELR_EL1" + + - + input: + bytes: [ 0x41, 0x04, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr MDSELR_EL1, x1" + + - + input: + bytes: [ 0x83, 0x9e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMUACR_EL1" + + - + input: + bytes: [ 0x81, 0x9e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr PMUACR_EL1, x1" + + - + input: + bytes: [ 0xe3, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMCCNTSVR_EL1" + + - + input: + bytes: [ 0x03, 0xec, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMICNTSVR_EL1" + + - + input: + bytes: [ 0x63, 0x9d, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMSSCR_EL1" + + - + input: + bytes: [ 0x61, 0x9d, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr PMSSCR_EL1, x1" + + - + input: + bytes: [ 0x03, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR0_EL1" + + - + input: + bytes: [ 0x23, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR1_EL1" + + - + input: + bytes: [ 0x43, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR2_EL1" + + - + input: + bytes: [ 0x63, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR3_EL1" + + - + input: + bytes: [ 0x83, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR4_EL1" + + - + input: + bytes: [ 0xa3, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR5_EL1" + + - + input: + bytes: [ 0xc3, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR6_EL1" + + - + input: + bytes: [ 0xe3, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR7_EL1" + + - + input: + bytes: [ 0x03, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR8_EL1" + + - + input: + bytes: [ 0x23, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR9_EL1" + + - + input: + bytes: [ 0x43, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR10_EL1" + + - + input: + bytes: [ 0x63, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR11_EL1" + + - + input: + bytes: [ 0x83, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR12_EL1" + + - + input: + bytes: [ 0xa3, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR13_EL1" + + - + input: + bytes: [ 0xc3, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR14_EL1" + + - + input: + bytes: [ 0xe3, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR15_EL1" + + - + input: + bytes: [ 0x03, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR16_EL1" + + - + input: + bytes: [ 0x23, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR17_EL1" + + - + input: + bytes: [ 0x43, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR18_EL1" + + - + input: + bytes: [ 0x63, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR19_EL1" + + - + input: + bytes: [ 0x83, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR20_EL1" + + - + input: + bytes: [ 0xa3, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR21_EL1" + + - + input: + bytes: [ 0xc3, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR22_EL1" + + - + input: + bytes: [ 0xe3, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR23_EL1" + + - + input: + bytes: [ 0x03, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR24_EL1" + + - + input: + bytes: [ 0x23, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR25_EL1" + + - + input: + bytes: [ 0x43, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR26_EL1" + + - + input: + bytes: [ 0x63, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR27_EL1" + + - + input: + bytes: [ 0x83, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR28_EL1" + + - + input: + bytes: [ 0xa3, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR29_EL1" + + - + input: + bytes: [ 0xc3, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR30_EL1" + + - + input: + bytes: [ 0x03, 0x94, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMICNTR_EL0" + + - + input: + bytes: [ 0x03, 0x94, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr PMICNTR_EL0, x3" + + - + input: + bytes: [ 0x03, 0x96, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMICFILTR_EL0" + + - + input: + bytes: [ 0x03, 0x96, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr PMICFILTR_EL0, x3" + + - + input: + bytes: [ 0x83, 0x9d, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr PMZR_EL0, x3" + + - + input: + bytes: [ 0xa3, 0x9e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMECR_EL1" + + - + input: + bytes: [ 0xa1, 0x9e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr PMECR_EL1, x1" + + - + input: + bytes: [ 0xe3, 0x9e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMIAR_EL1" + + - + input: + bytes: [ 0xe1, 0x9e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr PMIAR_EL1, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL1" + + - + input: + bytes: [ 0x61, 0x9d, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL1, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x35, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL12" + + - + input: + bytes: [ 0x61, 0x9d, 0x15, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL12, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x34, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL2" + + - + input: + bytes: [ 0x61, 0x9d, 0x14, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL2, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x36, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL3" + + - + input: + bytes: [ 0x61, 0x9d, 0x16, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL3, x1" + + - + input: + bytes: [ 0x43, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCNTENCLR_EL0" + + - + input: + bytes: [ 0x41, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMCNTENCLR_EL0, x1" + + - + input: + bytes: [ 0x23, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCNTENSET_EL0" + + - + input: + bytes: [ 0x21, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMCNTENSET_EL0, x1" + + - + input: + bytes: [ 0x03, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCR_EL0" + + - + input: + bytes: [ 0x01, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMCR_EL0, x1" + + - + input: + bytes: [ 0xc3, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMDEVAFF_EL1" + + - + input: + bytes: [ 0xa3, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMDEVARCH_EL1" + + - + input: + bytes: [ 0x03, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR0_EL0" + + - + input: + bytes: [ 0x01, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR1_EL0" + + - + input: + bytes: [ 0x21, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR2_EL0" + + - + input: + bytes: [ 0x41, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR3_EL0" + + - + input: + bytes: [ 0x61, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR4_EL0" + + - + input: + bytes: [ 0x81, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR5_EL0" + + - + input: + bytes: [ 0xa1, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR6_EL0" + + - + input: + bytes: [ 0xc1, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR7_EL0" + + - + input: + bytes: [ 0xe1, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR8_EL0" + + - + input: + bytes: [ 0x01, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR9_EL0" + + - + input: + bytes: [ 0x21, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR10_EL0" + + - + input: + bytes: [ 0x41, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR11_EL0" + + - + input: + bytes: [ 0x61, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR12_EL0" + + - + input: + bytes: [ 0x81, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR13_EL0" + + - + input: + bytes: [ 0xa1, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR14_EL0" + + - + input: + bytes: [ 0xc1, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR15_EL0" + + - + input: + bytes: [ 0xe1, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR15_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R0_EL0" + + - + input: + bytes: [ 0x01, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R1_EL0" + + - + input: + bytes: [ 0x21, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R2_EL0" + + - + input: + bytes: [ 0x41, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R3_EL0" + + - + input: + bytes: [ 0x61, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R4_EL0" + + - + input: + bytes: [ 0x81, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R5_EL0" + + - + input: + bytes: [ 0xa1, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R6_EL0" + + - + input: + bytes: [ 0xc1, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R7_EL0" + + - + input: + bytes: [ 0xe1, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R8_EL0" + + - + input: + bytes: [ 0x01, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R9_EL0" + + - + input: + bytes: [ 0x21, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R10_EL0" + + - + input: + bytes: [ 0x41, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R11_EL0" + + - + input: + bytes: [ 0x61, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R12_EL0" + + - + input: + bytes: [ 0x81, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R13_EL0" + + - + input: + bytes: [ 0xa1, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R14_EL0" + + - + input: + bytes: [ 0xc1, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R15_EL0" + + - + input: + bytes: [ 0xe1, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R15_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR0_EL0" + + - + input: + bytes: [ 0x01, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR1_EL0" + + - + input: + bytes: [ 0x21, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR2_EL0" + + - + input: + bytes: [ 0x41, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR3_EL0" + + - + input: + bytes: [ 0x61, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR4_EL0" + + - + input: + bytes: [ 0x81, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR5_EL0" + + - + input: + bytes: [ 0xa1, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR6_EL0" + + - + input: + bytes: [ 0xc1, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR7_EL0" + + - + input: + bytes: [ 0xe1, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR8_EL0" + + - + input: + bytes: [ 0x01, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR9_EL0" + + - + input: + bytes: [ 0x21, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR10_EL0" + + - + input: + bytes: [ 0x41, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR11_EL0" + + - + input: + bytes: [ 0x61, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR12_EL0" + + - + input: + bytes: [ 0x81, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR13_EL0" + + - + input: + bytes: [ 0xa1, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR14_EL0" + + - + input: + bytes: [ 0xc1, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR15_EL0" + + - + input: + bytes: [ 0xe1, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR15_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER0_EL0" + + - + input: + bytes: [ 0x01, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER1_EL0" + + - + input: + bytes: [ 0x21, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER2_EL0" + + - + input: + bytes: [ 0x41, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER3_EL0" + + - + input: + bytes: [ 0x61, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER4_EL0" + + - + input: + bytes: [ 0x81, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER5_EL0" + + - + input: + bytes: [ 0xa1, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER6_EL0" + + - + input: + bytes: [ 0xc1, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER7_EL0" + + - + input: + bytes: [ 0xe1, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER8_EL0" + + - + input: + bytes: [ 0x01, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER9_EL0" + + - + input: + bytes: [ 0x21, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER10_EL0" + + - + input: + bytes: [ 0x41, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER11_EL0" + + - + input: + bytes: [ 0x61, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER12_EL0" + + - + input: + bytes: [ 0x81, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER13_EL0" + + - + input: + bytes: [ 0xa1, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER14_EL0" + + - + input: + bytes: [ 0xc1, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER15_EL0" + + - + input: + bytes: [ 0xe1, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER15_EL0, x1" + + - + input: + bytes: [ 0x83, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMIIDR_EL1" + + - + input: + bytes: [ 0x43, 0x9e, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMINTENCLR_EL1" + + - + input: + bytes: [ 0x41, 0x9e, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMINTENCLR_EL1, x1" + + - + input: + bytes: [ 0x23, 0x9e, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMINTENSET_EL1" + + - + input: + bytes: [ 0x21, 0x9e, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMINTENSET_EL1, x1" + + - + input: + bytes: [ 0x63, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMOVSCLR_EL0" + + - + input: + bytes: [ 0x61, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMOVSCLR_EL0, x1" + + - + input: + bytes: [ 0x63, 0x9e, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMOVSSET_EL0" + + - + input: + bytes: [ 0x61, 0x9e, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMOVSSET_EL0, x1" + + - + input: + bytes: [ 0xa3, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMSELR_EL0" + + - + input: + bytes: [ 0xa1, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMSELR_EL0, x1" + + - + input: + bytes: [ 0x03, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCGCR0_EL1" + + - + input: + bytes: [ 0x23, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCGCR1_EL1" + + - + input: + bytes: [ 0xe3, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCFGR_EL1" + + - + input: + bytes: [ 0xe3, 0x9e, 0x36, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMROOTCR_EL3" + + - + input: + bytes: [ 0xe3, 0x9e, 0x16, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMROOTCR_EL3, x3" + + - + input: + bytes: [ 0xe3, 0x9e, 0x37, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMSCR_EL1" + + - + input: + bytes: [ 0xe3, 0x9e, 0x17, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMSCR_EL1, x3" + + - + input: + bytes: [ 0x23, 0x02, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITEEDCR" + + - + input: + bytes: [ 0x23, 0x02, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITEEDCR, x3" + + - + input: + bytes: [ 0x63, 0x12, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITECR_EL1" + + - + input: + bytes: [ 0x61, 0x12, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITECR_EL1, x1" + + - + input: + bytes: [ 0x63, 0x12, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITECR_EL12" + + - + input: + bytes: [ 0x61, 0x12, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITECR_EL12, x1" + + - + input: + bytes: [ 0x63, 0x12, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITECR_EL2" + + - + input: + bytes: [ 0x61, 0x12, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITECR_EL2, x1" + + - + input: + bytes: [ 0xe1, 0x72, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "trcit x1" + + - + input: + bytes: [ 0x83, 0x9a, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMSDSFR_EL1" + + - + input: + bytes: [ 0x83, 0x9a, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ] + expected: + insns: + - + asm_text: "msr PMSDSFR_EL1, x3" + + - + input: + bytes: [ 0x43, 0x04, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, MDSELR_EL1" + + - + input: + bytes: [ 0x41, 0x04, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr MDSELR_EL1, x1" + + - + input: + bytes: [ 0x83, 0x9e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMUACR_EL1" + + - + input: + bytes: [ 0x81, 0x9e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr PMUACR_EL1, x1" + + - + input: + bytes: [ 0xe3, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMCCNTSVR_EL1" + + - + input: + bytes: [ 0x03, 0xec, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMICNTSVR_EL1" + + - + input: + bytes: [ 0x63, 0x9d, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMSSCR_EL1" + + - + input: + bytes: [ 0x61, 0x9d, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr PMSSCR_EL1, x1" + + - + input: + bytes: [ 0x03, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR0_EL1" + + - + input: + bytes: [ 0x23, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR1_EL1" + + - + input: + bytes: [ 0x43, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR2_EL1" + + - + input: + bytes: [ 0x63, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR3_EL1" + + - + input: + bytes: [ 0x83, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR4_EL1" + + - + input: + bytes: [ 0xa3, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR5_EL1" + + - + input: + bytes: [ 0xc3, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR6_EL1" + + - + input: + bytes: [ 0xe3, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR7_EL1" + + - + input: + bytes: [ 0x03, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR8_EL1" + + - + input: + bytes: [ 0x23, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR9_EL1" + + - + input: + bytes: [ 0x43, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR10_EL1" + + - + input: + bytes: [ 0x63, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR11_EL1" + + - + input: + bytes: [ 0x83, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR12_EL1" + + - + input: + bytes: [ 0xa3, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR13_EL1" + + - + input: + bytes: [ 0xc3, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR14_EL1" + + - + input: + bytes: [ 0xe3, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR15_EL1" + + - + input: + bytes: [ 0x03, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR16_EL1" + + - + input: + bytes: [ 0x23, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR17_EL1" + + - + input: + bytes: [ 0x43, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR18_EL1" + + - + input: + bytes: [ 0x63, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR19_EL1" + + - + input: + bytes: [ 0x83, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR20_EL1" + + - + input: + bytes: [ 0xa3, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR21_EL1" + + - + input: + bytes: [ 0xc3, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR22_EL1" + + - + input: + bytes: [ 0xe3, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR23_EL1" + + - + input: + bytes: [ 0x03, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR24_EL1" + + - + input: + bytes: [ 0x23, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR25_EL1" + + - + input: + bytes: [ 0x43, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR26_EL1" + + - + input: + bytes: [ 0x63, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR27_EL1" + + - + input: + bytes: [ 0x83, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR28_EL1" + + - + input: + bytes: [ 0xa3, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR29_EL1" + + - + input: + bytes: [ 0xc3, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR30_EL1" + + - + input: + bytes: [ 0x03, 0x94, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMICNTR_EL0" + + - + input: + bytes: [ 0x03, 0x94, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr PMICNTR_EL0, x3" + + - + input: + bytes: [ 0x03, 0x96, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMICFILTR_EL0" + + - + input: + bytes: [ 0x03, 0x96, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr PMICFILTR_EL0, x3" + + - + input: + bytes: [ 0x83, 0x9d, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr PMZR_EL0, x3" + + - + input: + bytes: [ 0xa3, 0x9e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMECR_EL1" + + - + input: + bytes: [ 0xa1, 0x9e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr PMECR_EL1, x1" + + - + input: + bytes: [ 0xe3, 0x9e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMIAR_EL1" + + - + input: + bytes: [ 0xe1, 0x9e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr PMIAR_EL1, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL1" + + - + input: + bytes: [ 0x61, 0x9d, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL1, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x35, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL12" + + - + input: + bytes: [ 0x61, 0x9d, 0x15, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL12, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x34, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL2" + + - + input: + bytes: [ 0x61, 0x9d, 0x14, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL2, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x36, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL3" + + - + input: + bytes: [ 0x61, 0x9d, 0x16, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL3, x1" + + - + input: + bytes: [ 0x43, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCNTENCLR_EL0" + + - + input: + bytes: [ 0x41, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMCNTENCLR_EL0, x1" + + - + input: + bytes: [ 0x23, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCNTENSET_EL0" + + - + input: + bytes: [ 0x21, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMCNTENSET_EL0, x1" + + - + input: + bytes: [ 0x03, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCR_EL0" + + - + input: + bytes: [ 0x01, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMCR_EL0, x1" + + - + input: + bytes: [ 0xc3, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMDEVAFF_EL1" + + - + input: + bytes: [ 0xa3, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMDEVARCH_EL1" + + - + input: + bytes: [ 0x03, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR0_EL0" + + - + input: + bytes: [ 0x01, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR1_EL0" + + - + input: + bytes: [ 0x21, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR2_EL0" + + - + input: + bytes: [ 0x41, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR3_EL0" + + - + input: + bytes: [ 0x61, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR4_EL0" + + - + input: + bytes: [ 0x81, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR5_EL0" + + - + input: + bytes: [ 0xa1, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR6_EL0" + + - + input: + bytes: [ 0xc1, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR7_EL0" + + - + input: + bytes: [ 0xe1, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR8_EL0" + + - + input: + bytes: [ 0x01, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR9_EL0" + + - + input: + bytes: [ 0x21, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR10_EL0" + + - + input: + bytes: [ 0x41, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR11_EL0" + + - + input: + bytes: [ 0x61, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR12_EL0" + + - + input: + bytes: [ 0x81, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR13_EL0" + + - + input: + bytes: [ 0xa1, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR14_EL0" + + - + input: + bytes: [ 0xc1, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR15_EL0" + + - + input: + bytes: [ 0xe1, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR15_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R0_EL0" + + - + input: + bytes: [ 0x01, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R1_EL0" + + - + input: + bytes: [ 0x21, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R2_EL0" + + - + input: + bytes: [ 0x41, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R3_EL0" + + - + input: + bytes: [ 0x61, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R4_EL0" + + - + input: + bytes: [ 0x81, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R5_EL0" + + - + input: + bytes: [ 0xa1, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R6_EL0" + + - + input: + bytes: [ 0xc1, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R7_EL0" + + - + input: + bytes: [ 0xe1, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R8_EL0" + + - + input: + bytes: [ 0x01, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R9_EL0" + + - + input: + bytes: [ 0x21, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R10_EL0" + + - + input: + bytes: [ 0x41, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R11_EL0" + + - + input: + bytes: [ 0x61, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R12_EL0" + + - + input: + bytes: [ 0x81, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R13_EL0" + + - + input: + bytes: [ 0xa1, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R14_EL0" + + - + input: + bytes: [ 0xc1, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R15_EL0" + + - + input: + bytes: [ 0xe1, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R15_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR0_EL0" + + - + input: + bytes: [ 0x01, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR1_EL0" + + - + input: + bytes: [ 0x21, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR2_EL0" + + - + input: + bytes: [ 0x41, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR3_EL0" + + - + input: + bytes: [ 0x61, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR4_EL0" + + - + input: + bytes: [ 0x81, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR5_EL0" + + - + input: + bytes: [ 0xa1, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR6_EL0" + + - + input: + bytes: [ 0xc1, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR7_EL0" + + - + input: + bytes: [ 0xe1, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR8_EL0" + + - + input: + bytes: [ 0x01, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR9_EL0" + + - + input: + bytes: [ 0x21, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR10_EL0" + + - + input: + bytes: [ 0x41, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR11_EL0" + + - + input: + bytes: [ 0x61, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR12_EL0" + + - + input: + bytes: [ 0x81, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR13_EL0" + + - + input: + bytes: [ 0xa1, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR14_EL0" + + - + input: + bytes: [ 0xc1, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR15_EL0" + + - + input: + bytes: [ 0xe1, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR15_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER0_EL0" + + - + input: + bytes: [ 0x01, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER1_EL0" + + - + input: + bytes: [ 0x21, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER2_EL0" + + - + input: + bytes: [ 0x41, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER3_EL0" + + - + input: + bytes: [ 0x61, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER4_EL0" + + - + input: + bytes: [ 0x81, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER5_EL0" + + - + input: + bytes: [ 0xa1, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER6_EL0" + + - + input: + bytes: [ 0xc1, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER7_EL0" + + - + input: + bytes: [ 0xe1, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER8_EL0" + + - + input: + bytes: [ 0x01, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER9_EL0" + + - + input: + bytes: [ 0x21, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER10_EL0" + + - + input: + bytes: [ 0x41, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER11_EL0" + + - + input: + bytes: [ 0x61, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER12_EL0" + + - + input: + bytes: [ 0x81, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER13_EL0" + + - + input: + bytes: [ 0xa1, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER14_EL0" + + - + input: + bytes: [ 0xc1, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER15_EL0" + + - + input: + bytes: [ 0xe1, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER15_EL0, x1" + + - + input: + bytes: [ 0x83, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMIIDR_EL1" + + - + input: + bytes: [ 0x43, 0x9e, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMINTENCLR_EL1" + + - + input: + bytes: [ 0x41, 0x9e, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMINTENCLR_EL1, x1" + + - + input: + bytes: [ 0x23, 0x9e, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMINTENSET_EL1" + + - + input: + bytes: [ 0x21, 0x9e, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMINTENSET_EL1, x1" + + - + input: + bytes: [ 0x63, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMOVSCLR_EL0" + + - + input: + bytes: [ 0x61, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMOVSCLR_EL0, x1" + + - + input: + bytes: [ 0x63, 0x9e, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMOVSSET_EL0" + + - + input: + bytes: [ 0x61, 0x9e, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMOVSSET_EL0, x1" + + - + input: + bytes: [ 0xa3, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMSELR_EL0" + + - + input: + bytes: [ 0xa1, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMSELR_EL0, x1" + + - + input: + bytes: [ 0x03, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCGCR0_EL1" + + - + input: + bytes: [ 0x23, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCGCR1_EL1" + + - + input: + bytes: [ 0xe3, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCFGR_EL1" + + - + input: + bytes: [ 0xe3, 0x9e, 0x36, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMROOTCR_EL3" + + - + input: + bytes: [ 0xe3, 0x9e, 0x16, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMROOTCR_EL3, x3" + + - + input: + bytes: [ 0xe3, 0x9e, 0x37, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMSCR_EL1" + + - + input: + bytes: [ 0xe3, 0x9e, 0x17, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMSCR_EL1, x3" + + - + input: + bytes: [ 0x23, 0x02, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITEEDCR" + + - + input: + bytes: [ 0x23, 0x02, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITEEDCR, x3" + + - + input: + bytes: [ 0x63, 0x12, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITECR_EL1" + + - + input: + bytes: [ 0x61, 0x12, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITECR_EL1, x1" + + - + input: + bytes: [ 0x63, 0x12, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITECR_EL12" + + - + input: + bytes: [ 0x61, 0x12, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITECR_EL12, x1" + + - + input: + bytes: [ 0x63, 0x12, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITECR_EL2" + + - + input: + bytes: [ 0x61, 0x12, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITECR_EL2, x1" + + - + input: + bytes: [ 0xe1, 0x72, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "trcit x1" + + - + input: + bytes: [ 0x83, 0x9a, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMSDSFR_EL1" + + - + input: + bytes: [ 0x83, 0x9a, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ] + expected: + insns: + - + asm_text: "msr PMSDSFR_EL1, x3" + + - + input: + bytes: [ 0x43, 0x04, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, MDSELR_EL1" + + - + input: + bytes: [ 0x41, 0x04, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr MDSELR_EL1, x1" + + - + input: + bytes: [ 0x83, 0x9e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMUACR_EL1" + + - + input: + bytes: [ 0x81, 0x9e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr PMUACR_EL1, x1" + + - + input: + bytes: [ 0xe3, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMCCNTSVR_EL1" + + - + input: + bytes: [ 0x03, 0xec, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMICNTSVR_EL1" + + - + input: + bytes: [ 0x63, 0x9d, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMSSCR_EL1" + + - + input: + bytes: [ 0x61, 0x9d, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr PMSSCR_EL1, x1" + + - + input: + bytes: [ 0x03, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR0_EL1" + + - + input: + bytes: [ 0x23, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR1_EL1" + + - + input: + bytes: [ 0x43, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR2_EL1" + + - + input: + bytes: [ 0x63, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR3_EL1" + + - + input: + bytes: [ 0x83, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR4_EL1" + + - + input: + bytes: [ 0xa3, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR5_EL1" + + - + input: + bytes: [ 0xc3, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR6_EL1" + + - + input: + bytes: [ 0xe3, 0xe8, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR7_EL1" + + - + input: + bytes: [ 0x03, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR8_EL1" + + - + input: + bytes: [ 0x23, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR9_EL1" + + - + input: + bytes: [ 0x43, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR10_EL1" + + - + input: + bytes: [ 0x63, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR11_EL1" + + - + input: + bytes: [ 0x83, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR12_EL1" + + - + input: + bytes: [ 0xa3, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR13_EL1" + + - + input: + bytes: [ 0xc3, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR14_EL1" + + - + input: + bytes: [ 0xe3, 0xe9, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR15_EL1" + + - + input: + bytes: [ 0x03, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR16_EL1" + + - + input: + bytes: [ 0x23, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR17_EL1" + + - + input: + bytes: [ 0x43, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR18_EL1" + + - + input: + bytes: [ 0x63, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR19_EL1" + + - + input: + bytes: [ 0x83, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR20_EL1" + + - + input: + bytes: [ 0xa3, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR21_EL1" + + - + input: + bytes: [ 0xc3, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR22_EL1" + + - + input: + bytes: [ 0xe3, 0xea, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR23_EL1" + + - + input: + bytes: [ 0x03, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR24_EL1" + + - + input: + bytes: [ 0x23, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR25_EL1" + + - + input: + bytes: [ 0x43, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR26_EL1" + + - + input: + bytes: [ 0x63, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR27_EL1" + + - + input: + bytes: [ 0x83, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR28_EL1" + + - + input: + bytes: [ 0xa3, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR29_EL1" + + - + input: + bytes: [ 0xc3, 0xeb, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMEVCNTSVR30_EL1" + + - + input: + bytes: [ 0x03, 0x94, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMICNTR_EL0" + + - + input: + bytes: [ 0x03, 0x94, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr PMICNTR_EL0, x3" + + - + input: + bytes: [ 0x03, 0x96, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMICFILTR_EL0" + + - + input: + bytes: [ 0x03, 0x96, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr PMICFILTR_EL0, x3" + + - + input: + bytes: [ 0x83, 0x9d, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr PMZR_EL0, x3" + + - + input: + bytes: [ 0xa3, 0x9e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMECR_EL1" + + - + input: + bytes: [ 0xa1, 0x9e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr PMECR_EL1, x1" + + - + input: + bytes: [ 0xe3, 0x9e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMIAR_EL1" + + - + input: + bytes: [ 0xe1, 0x9e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr PMIAR_EL1, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL1" + + - + input: + bytes: [ 0x61, 0x9d, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL1, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x35, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL12" + + - + input: + bytes: [ 0x61, 0x9d, 0x15, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL12, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x34, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL2" + + - + input: + bytes: [ 0x61, 0x9d, 0x14, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL2, x1" + + - + input: + bytes: [ 0x63, 0x9d, 0x36, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMACCESSR_EL3" + + - + input: + bytes: [ 0x61, 0x9d, 0x16, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMACCESSR_EL3, x1" + + - + input: + bytes: [ 0x43, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCNTENCLR_EL0" + + - + input: + bytes: [ 0x41, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMCNTENCLR_EL0, x1" + + - + input: + bytes: [ 0x23, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCNTENSET_EL0" + + - + input: + bytes: [ 0x21, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMCNTENSET_EL0, x1" + + - + input: + bytes: [ 0x03, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCR_EL0" + + - + input: + bytes: [ 0x01, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMCR_EL0, x1" + + - + input: + bytes: [ 0xc3, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMDEVAFF_EL1" + + - + input: + bytes: [ 0xa3, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMDEVARCH_EL1" + + - + input: + bytes: [ 0x03, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR0_EL0" + + - + input: + bytes: [ 0x01, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR1_EL0" + + - + input: + bytes: [ 0x21, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR2_EL0" + + - + input: + bytes: [ 0x41, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR3_EL0" + + - + input: + bytes: [ 0x61, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR4_EL0" + + - + input: + bytes: [ 0x81, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR5_EL0" + + - + input: + bytes: [ 0xa1, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR6_EL0" + + - + input: + bytes: [ 0xc1, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe0, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR7_EL0" + + - + input: + bytes: [ 0xe1, 0xe0, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR8_EL0" + + - + input: + bytes: [ 0x01, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR9_EL0" + + - + input: + bytes: [ 0x21, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR10_EL0" + + - + input: + bytes: [ 0x41, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR11_EL0" + + - + input: + bytes: [ 0x61, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR12_EL0" + + - + input: + bytes: [ 0x81, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR13_EL0" + + - + input: + bytes: [ 0xa1, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR14_EL0" + + - + input: + bytes: [ 0xc1, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe1, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVCNTR15_EL0" + + - + input: + bytes: [ 0xe1, 0xe1, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVCNTR15_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R0_EL0" + + - + input: + bytes: [ 0x01, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R1_EL0" + + - + input: + bytes: [ 0x21, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R2_EL0" + + - + input: + bytes: [ 0x41, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R3_EL0" + + - + input: + bytes: [ 0x61, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R4_EL0" + + - + input: + bytes: [ 0x81, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R5_EL0" + + - + input: + bytes: [ 0xa1, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R6_EL0" + + - + input: + bytes: [ 0xc1, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe6, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R7_EL0" + + - + input: + bytes: [ 0xe1, 0xe6, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R8_EL0" + + - + input: + bytes: [ 0x01, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R9_EL0" + + - + input: + bytes: [ 0x21, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R10_EL0" + + - + input: + bytes: [ 0x41, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R11_EL0" + + - + input: + bytes: [ 0x61, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R12_EL0" + + - + input: + bytes: [ 0x81, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R13_EL0" + + - + input: + bytes: [ 0xa1, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R14_EL0" + + - + input: + bytes: [ 0xc1, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe7, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILT2R15_EL0" + + - + input: + bytes: [ 0xe1, 0xe7, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILT2R15_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR0_EL0" + + - + input: + bytes: [ 0x01, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR1_EL0" + + - + input: + bytes: [ 0x21, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR2_EL0" + + - + input: + bytes: [ 0x41, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR3_EL0" + + - + input: + bytes: [ 0x61, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR4_EL0" + + - + input: + bytes: [ 0x81, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR5_EL0" + + - + input: + bytes: [ 0xa1, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR6_EL0" + + - + input: + bytes: [ 0xc1, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe4, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR7_EL0" + + - + input: + bytes: [ 0xe1, 0xe4, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR8_EL0" + + - + input: + bytes: [ 0x01, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR9_EL0" + + - + input: + bytes: [ 0x21, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR10_EL0" + + - + input: + bytes: [ 0x41, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR11_EL0" + + - + input: + bytes: [ 0x61, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR12_EL0" + + - + input: + bytes: [ 0x81, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR13_EL0" + + - + input: + bytes: [ 0xa1, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR14_EL0" + + - + input: + bytes: [ 0xc1, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe5, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVFILTR15_EL0" + + - + input: + bytes: [ 0xe1, 0xe5, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVFILTR15_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER0_EL0" + + - + input: + bytes: [ 0x01, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER0_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER1_EL0" + + - + input: + bytes: [ 0x21, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER1_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER2_EL0" + + - + input: + bytes: [ 0x41, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER2_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER3_EL0" + + - + input: + bytes: [ 0x61, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER3_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER4_EL0" + + - + input: + bytes: [ 0x81, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER4_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER5_EL0" + + - + input: + bytes: [ 0xa1, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER5_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER6_EL0" + + - + input: + bytes: [ 0xc1, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER6_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe2, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER7_EL0" + + - + input: + bytes: [ 0xe1, 0xe2, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER7_EL0, x1" + + - + input: + bytes: [ 0x03, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER8_EL0" + + - + input: + bytes: [ 0x01, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER8_EL0, x1" + + - + input: + bytes: [ 0x23, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER9_EL0" + + - + input: + bytes: [ 0x21, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER9_EL0, x1" + + - + input: + bytes: [ 0x43, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER10_EL0" + + - + input: + bytes: [ 0x41, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER10_EL0, x1" + + - + input: + bytes: [ 0x63, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER11_EL0" + + - + input: + bytes: [ 0x61, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER11_EL0, x1" + + - + input: + bytes: [ 0x83, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER12_EL0" + + - + input: + bytes: [ 0x81, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER12_EL0, x1" + + - + input: + bytes: [ 0xa3, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER13_EL0" + + - + input: + bytes: [ 0xa1, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER13_EL0, x1" + + - + input: + bytes: [ 0xc3, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER14_EL0" + + - + input: + bytes: [ 0xc1, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER14_EL0, x1" + + - + input: + bytes: [ 0xe3, 0xe3, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMEVTYPER15_EL0" + + - + input: + bytes: [ 0xe1, 0xe3, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMEVTYPER15_EL0, x1" + + - + input: + bytes: [ 0x83, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMIIDR_EL1" + + - + input: + bytes: [ 0x43, 0x9e, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMINTENCLR_EL1" + + - + input: + bytes: [ 0x41, 0x9e, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMINTENCLR_EL1, x1" + + - + input: + bytes: [ 0x23, 0x9e, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMINTENSET_EL1" + + - + input: + bytes: [ 0x21, 0x9e, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMINTENSET_EL1, x1" + + - + input: + bytes: [ 0x63, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMOVSCLR_EL0" + + - + input: + bytes: [ 0x61, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMOVSCLR_EL0, x1" + + - + input: + bytes: [ 0x63, 0x9e, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMOVSSET_EL0" + + - + input: + bytes: [ 0x61, 0x9e, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMOVSSET_EL0, x1" + + - + input: + bytes: [ 0xa3, 0x9c, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMSELR_EL0" + + - + input: + bytes: [ 0xa1, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMSELR_EL0, x1" + + - + input: + bytes: [ 0x03, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCGCR0_EL1" + + - + input: + bytes: [ 0x23, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCGCR1_EL1" + + - + input: + bytes: [ 0xe3, 0x9d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMCFGR_EL1" + + - + input: + bytes: [ 0xe3, 0x9e, 0x36, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMROOTCR_EL3" + + - + input: + bytes: [ 0xe3, 0x9e, 0x16, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMROOTCR_EL3, x3" + + - + input: + bytes: [ 0xe3, 0x9e, 0x37, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, SPMSCR_EL1" + + - + input: + bytes: [ 0xe3, 0x9e, 0x17, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr SPMSCR_EL1, x3" + + - + input: + bytes: [ 0x23, 0x02, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITEEDCR" + + - + input: + bytes: [ 0x23, 0x02, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITEEDCR, x3" + + - + input: + bytes: [ 0x63, 0x12, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITECR_EL1" + + - + input: + bytes: [ 0x61, 0x12, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITECR_EL1, x1" + + - + input: + bytes: [ 0x63, 0x12, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITECR_EL12" + + - + input: + bytes: [ 0x61, 0x12, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITECR_EL12, x1" + + - + input: + bytes: [ 0x63, 0x12, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, TRCITECR_EL2" + + - + input: + bytes: [ 0x61, 0x12, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr TRCITECR_EL2, x1" + + - + input: + bytes: [ 0xe1, 0x72, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "trcit x1" + + - + input: + bytes: [ 0x83, 0x9a, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "mrs x3, PMSDSFR_EL1" + + - + input: + bytes: [ 0x83, 0x9a, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ] + expected: + insns: + - + asm_text: "msr PMSDSFR_EL1, x3" diff --git a/tests/MC/AArch64/armv8.9a-lrcpc3.s.yaml b/tests/MC/AArch64/armv8.9a-lrcpc3.s.yaml new file mode 100644 index 0000000000..77843303eb --- /dev/null +++ b/tests/MC/AArch64/armv8.9a-lrcpc3.s.yaml @@ -0,0 +1,1320 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x0a, 0x00, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w24, w0, [x16, #-8]!" + + - + input: + bytes: [ 0x18, 0x0a, 0x00, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w24, w0, [x16, #-8]!" + + - + input: + bytes: [ 0x39, 0x0a, 0x01, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x25, x1, [x17, #-16]!" + + - + input: + bytes: [ 0x39, 0x0a, 0x01, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x25, x1, [x17, #-16]!" + + - + input: + bytes: [ 0x5a, 0x1a, 0x02, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w26, w2, [x18]" + + - + input: + bytes: [ 0x5a, 0x1a, 0x02, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w26, w2, [x18]" + + - + input: + bytes: [ 0xfb, 0x1b, 0x03, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x27, x3, [sp]" + + - + input: + bytes: [ 0xfb, 0x1b, 0x03, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x27, x3, [sp]" + + - + input: + bytes: [ 0x9c, 0x0a, 0x44, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w28, w4, [x20], #8" + + - + input: + bytes: [ 0x9c, 0x0a, 0x44, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w28, w4, [x20], #8" + + - + input: + bytes: [ 0x9c, 0x0a, 0x44, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w28, w4, [x20], #8" + + - + input: + bytes: [ 0x9c, 0x0a, 0x44, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w28, w4, [x20], #8" + + - + input: + bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp x29, x5, [x21], #16" + + - + input: + bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp x29, x5, [x21], #16" + + - + input: + bytes: [ 0xfe, 0x1b, 0x46, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w30, w6, [sp]" + + - + input: + bytes: [ 0xfe, 0x1b, 0x46, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w30, w6, [sp]" + + - + input: + bytes: [ 0xff, 0x1a, 0x47, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp xzr, x7, [x23]" + + - + input: + bytes: [ 0xff, 0x1a, 0x47, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp xzr, x7, [x23]" + + - + input: + bytes: [ 0xe3, 0x09, 0x80, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr w3, [x15, #-4]!" + + - + input: + bytes: [ 0xe3, 0x09, 0x80, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr w3, [x15, #-4]!" + + - + input: + bytes: [ 0xe3, 0x09, 0x80, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr x3, [x15, #-8]!" + + - + input: + bytes: [ 0xe3, 0x0b, 0x80, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr x3, [sp, #-8]!" + + - + input: + bytes: [ 0xe3, 0x0b, 0xc0, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr w3, [sp], #4" + + - + input: + bytes: [ 0xe3, 0x09, 0xc0, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr w3, [x15], #4" + + - + input: + bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr x3, [x15], #8" + + - + input: + bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr x3, [x15], #8" + + - + input: + bytes: [ 0xe3, 0xf9, 0x1f, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur b3, [x15, #-1]" + + - + input: + bytes: [ 0xe3, 0x29, 0x00, 0x5d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur h3, [x15, #2]" + + - + input: + bytes: [ 0xe3, 0xd9, 0x1f, 0x9d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur s3, [x15, #-3]" + + - + input: + bytes: [ 0xe3, 0x4b, 0x00, 0xdd ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur d3, [sp, #4]" + + - + input: + bytes: [ 0xe3, 0xb9, 0x9f, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur q3, [x15, #-5]" + + - + input: + bytes: [ 0xe3, 0x69, 0x40, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur b3, [x15, #6]" + + - + input: + bytes: [ 0xe3, 0x99, 0x5f, 0x5d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur h3, [x15, #-7]" + + - + input: + bytes: [ 0xe3, 0x89, 0x40, 0x9d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur s3, [x15, #8]" + + - + input: + bytes: [ 0xe3, 0x79, 0x5f, 0xdd ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur d3, [x15, #-9]" + + - + input: + bytes: [ 0xe3, 0xab, 0xc0, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur q3, [sp, #10]" + + - + input: + bytes: [ 0xe3, 0x85, 0x01, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stl1 { v3.d }[0], [x15]" + + - + input: + bytes: [ 0xe3, 0x85, 0x01, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stl1 { v3.d }[0], [x15]" + + - + input: + bytes: [ 0xe3, 0x87, 0x01, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stl1 { v3.d }[1], [sp]" + + - + input: + bytes: [ 0xe3, 0x87, 0x01, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stl1 { v3.d }[1], [sp]" + + - + input: + bytes: [ 0xe3, 0x87, 0x41, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldap1 { v3.d }[0], [sp]" + + - + input: + bytes: [ 0xe3, 0x87, 0x41, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldap1 { v3.d }[0], [sp]" + + - + input: + bytes: [ 0xe3, 0x85, 0x41, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldap1 { v3.d }[1], [x15]" + + - + input: + bytes: [ 0xe3, 0x85, 0x41, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldap1 { v3.d }[1], [x15]" + + - + input: + bytes: [ 0x18, 0x0a, 0x00, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w24, w0, [x16, #-8]!" + + - + input: + bytes: [ 0x18, 0x0a, 0x00, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w24, w0, [x16, #-8]!" + + - + input: + bytes: [ 0x39, 0x0a, 0x01, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x25, x1, [x17, #-16]!" + + - + input: + bytes: [ 0x39, 0x0a, 0x01, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x25, x1, [x17, #-16]!" + + - + input: + bytes: [ 0x5a, 0x1a, 0x02, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w26, w2, [x18]" + + - + input: + bytes: [ 0x5a, 0x1a, 0x02, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w26, w2, [x18]" + + - + input: + bytes: [ 0xfb, 0x1b, 0x03, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x27, x3, [sp]" + + - + input: + bytes: [ 0xfb, 0x1b, 0x03, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x27, x3, [sp]" + + - + input: + bytes: [ 0x9c, 0x0a, 0x44, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w28, w4, [x20], #8" + + - + input: + bytes: [ 0x9c, 0x0a, 0x44, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w28, w4, [x20], #8" + + - + input: + bytes: [ 0x9c, 0x0a, 0x44, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w28, w4, [x20], #8" + + - + input: + bytes: [ 0x9c, 0x0a, 0x44, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w28, w4, [x20], #8" + + - + input: + bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp x29, x5, [x21], #16" + + - + input: + bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp x29, x5, [x21], #16" + + - + input: + bytes: [ 0xfe, 0x1b, 0x46, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w30, w6, [sp]" + + - + input: + bytes: [ 0xfe, 0x1b, 0x46, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w30, w6, [sp]" + + - + input: + bytes: [ 0xff, 0x1a, 0x47, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp xzr, x7, [x23]" + + - + input: + bytes: [ 0xff, 0x1a, 0x47, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp xzr, x7, [x23]" + + - + input: + bytes: [ 0xe3, 0x09, 0x80, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr w3, [x15, #-4]!" + + - + input: + bytes: [ 0xe3, 0x09, 0x80, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr w3, [x15, #-4]!" + + - + input: + bytes: [ 0xe3, 0x09, 0x80, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr x3, [x15, #-8]!" + + - + input: + bytes: [ 0xe3, 0x0b, 0x80, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr x3, [sp, #-8]!" + + - + input: + bytes: [ 0xe3, 0x0b, 0xc0, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr w3, [sp], #4" + + - + input: + bytes: [ 0xe3, 0x09, 0xc0, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr w3, [x15], #4" + + - + input: + bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr x3, [x15], #8" + + - + input: + bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr x3, [x15], #8" + + - + input: + bytes: [ 0xe3, 0xf9, 0x1f, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur b3, [x15, #-1]" + + - + input: + bytes: [ 0xe3, 0x29, 0x00, 0x5d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur h3, [x15, #2]" + + - + input: + bytes: [ 0xe3, 0xd9, 0x1f, 0x9d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur s3, [x15, #-3]" + + - + input: + bytes: [ 0xe3, 0x4b, 0x00, 0xdd ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur d3, [sp, #4]" + + - + input: + bytes: [ 0xe3, 0xb9, 0x9f, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur q3, [x15, #-5]" + + - + input: + bytes: [ 0xe3, 0x69, 0x40, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur b3, [x15, #6]" + + - + input: + bytes: [ 0xe3, 0x99, 0x5f, 0x5d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur h3, [x15, #-7]" + + - + input: + bytes: [ 0xe3, 0x89, 0x40, 0x9d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur s3, [x15, #8]" + + - + input: + bytes: [ 0xe3, 0x79, 0x5f, 0xdd ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur d3, [x15, #-9]" + + - + input: + bytes: [ 0xe3, 0xab, 0xc0, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur q3, [sp, #10]" + + - + input: + bytes: [ 0xe3, 0x85, 0x01, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stl1 { v3.d }[0], [x15]" + + - + input: + bytes: [ 0xe3, 0x85, 0x01, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stl1 { v3.d }[0], [x15]" + + - + input: + bytes: [ 0xe3, 0x87, 0x01, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stl1 { v3.d }[1], [sp]" + + - + input: + bytes: [ 0xe3, 0x87, 0x01, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stl1 { v3.d }[1], [sp]" + + - + input: + bytes: [ 0xe3, 0x87, 0x41, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldap1 { v3.d }[0], [sp]" + + - + input: + bytes: [ 0xe3, 0x87, 0x41, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldap1 { v3.d }[0], [sp]" + + - + input: + bytes: [ 0xe3, 0x85, 0x41, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldap1 { v3.d }[1], [x15]" + + - + input: + bytes: [ 0xe3, 0x85, 0x41, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldap1 { v3.d }[1], [x15]" + + - + input: + bytes: [ 0x18, 0x0a, 0x00, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w24, w0, [x16, #-8]!" + + - + input: + bytes: [ 0x18, 0x0a, 0x00, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w24, w0, [x16, #-8]!" + + - + input: + bytes: [ 0x39, 0x0a, 0x01, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x25, x1, [x17, #-16]!" + + - + input: + bytes: [ 0x39, 0x0a, 0x01, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x25, x1, [x17, #-16]!" + + - + input: + bytes: [ 0x5a, 0x1a, 0x02, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w26, w2, [x18]" + + - + input: + bytes: [ 0x5a, 0x1a, 0x02, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w26, w2, [x18]" + + - + input: + bytes: [ 0xfb, 0x1b, 0x03, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x27, x3, [sp]" + + - + input: + bytes: [ 0xfb, 0x1b, 0x03, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x27, x3, [sp]" + + - + input: + bytes: [ 0x9c, 0x0a, 0x44, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w28, w4, [x20], #8" + + - + input: + bytes: [ 0x9c, 0x0a, 0x44, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w28, w4, [x20], #8" + + - + input: + bytes: [ 0x9c, 0x0a, 0x44, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w28, w4, [x20], #8" + + - + input: + bytes: [ 0x9c, 0x0a, 0x44, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w28, w4, [x20], #8" + + - + input: + bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp x29, x5, [x21], #16" + + - + input: + bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp x29, x5, [x21], #16" + + - + input: + bytes: [ 0xfe, 0x1b, 0x46, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w30, w6, [sp]" + + - + input: + bytes: [ 0xfe, 0x1b, 0x46, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w30, w6, [sp]" + + - + input: + bytes: [ 0xff, 0x1a, 0x47, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp xzr, x7, [x23]" + + - + input: + bytes: [ 0xff, 0x1a, 0x47, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp xzr, x7, [x23]" + + - + input: + bytes: [ 0xe3, 0x09, 0x80, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr w3, [x15, #-4]!" + + - + input: + bytes: [ 0xe3, 0x09, 0x80, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr w3, [x15, #-4]!" + + - + input: + bytes: [ 0xe3, 0x09, 0x80, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr x3, [x15, #-8]!" + + - + input: + bytes: [ 0xe3, 0x0b, 0x80, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr x3, [sp, #-8]!" + + - + input: + bytes: [ 0xe3, 0x0b, 0xc0, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr w3, [sp], #4" + + - + input: + bytes: [ 0xe3, 0x09, 0xc0, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr w3, [x15], #4" + + - + input: + bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr x3, [x15], #8" + + - + input: + bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr x3, [x15], #8" + + - + input: + bytes: [ 0xe3, 0xf9, 0x1f, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur b3, [x15, #-1]" + + - + input: + bytes: [ 0xe3, 0x29, 0x00, 0x5d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur h3, [x15, #2]" + + - + input: + bytes: [ 0xe3, 0xd9, 0x1f, 0x9d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur s3, [x15, #-3]" + + - + input: + bytes: [ 0xe3, 0x4b, 0x00, 0xdd ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur d3, [sp, #4]" + + - + input: + bytes: [ 0xe3, 0xb9, 0x9f, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur q3, [x15, #-5]" + + - + input: + bytes: [ 0xe3, 0x69, 0x40, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur b3, [x15, #6]" + + - + input: + bytes: [ 0xe3, 0x99, 0x5f, 0x5d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur h3, [x15, #-7]" + + - + input: + bytes: [ 0xe3, 0x89, 0x40, 0x9d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur s3, [x15, #8]" + + - + input: + bytes: [ 0xe3, 0x79, 0x5f, 0xdd ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur d3, [x15, #-9]" + + - + input: + bytes: [ 0xe3, 0xab, 0xc0, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur q3, [sp, #10]" + + - + input: + bytes: [ 0xe3, 0x85, 0x01, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stl1 { v3.d }[0], [x15]" + + - + input: + bytes: [ 0xe3, 0x85, 0x01, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stl1 { v3.d }[0], [x15]" + + - + input: + bytes: [ 0xe3, 0x87, 0x01, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stl1 { v3.d }[1], [sp]" + + - + input: + bytes: [ 0xe3, 0x87, 0x01, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stl1 { v3.d }[1], [sp]" + + - + input: + bytes: [ 0xe3, 0x87, 0x41, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldap1 { v3.d }[0], [sp]" + + - + input: + bytes: [ 0xe3, 0x87, 0x41, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldap1 { v3.d }[0], [sp]" + + - + input: + bytes: [ 0xe3, 0x85, 0x41, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldap1 { v3.d }[1], [x15]" + + - + input: + bytes: [ 0xe3, 0x85, 0x41, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldap1 { v3.d }[1], [x15]" diff --git a/tests/MC/AArch64/armv8.9a-lrcpc3.txt.yaml b/tests/MC/AArch64/armv8.9a-lrcpc3.txt.yaml new file mode 100644 index 0000000000..75f2f246d4 --- /dev/null +++ b/tests/MC/AArch64/armv8.9a-lrcpc3.txt.yaml @@ -0,0 +1,1020 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x0a, 0x00, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w24, w0, [x16, #-8]!" + + - + input: + bytes: [ 0x18, 0x0a, 0x00, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w24, w0, [x16, #-8]!" + + - + input: + bytes: [ 0x39, 0x0a, 0x01, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x25, x1, [x17, #-16]!" + + - + input: + bytes: [ 0x39, 0x0a, 0x01, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x25, x1, [x17, #-16]!" + + - + input: + bytes: [ 0x5a, 0x1a, 0x02, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w26, w2, [x18]" + + - + input: + bytes: [ 0xfb, 0x1b, 0x03, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x27, x3, [sp]" + + - + input: + bytes: [ 0x9c, 0x0a, 0x44, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w28, w4, [x20], #8" + + - + input: + bytes: [ 0x9c, 0x0a, 0x44, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w28, w4, [x20], #8" + + - + input: + bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp x29, x5, [x21], #16" + + - + input: + bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp x29, x5, [x21], #16" + + - + input: + bytes: [ 0xfe, 0x1b, 0x46, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w30, w6, [sp]" + + - + input: + bytes: [ 0xff, 0x1a, 0x47, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp xzr, x7, [x23]" + + - + input: + bytes: [ 0xe3, 0x09, 0x80, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr w3, [x15, #-4]!" + + - + input: + bytes: [ 0xe3, 0x09, 0x80, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr w3, [x15, #-4]!" + + - + input: + bytes: [ 0xe3, 0x09, 0x80, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr x3, [x15, #-8]!" + + - + input: + bytes: [ 0xe3, 0x0b, 0x80, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr x3, [sp, #-8]!" + + - + input: + bytes: [ 0xe3, 0x0b, 0xc0, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr w3, [sp], #4" + + - + input: + bytes: [ 0xe3, 0x09, 0xc0, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr w3, [x15], #4" + + - + input: + bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr x3, [x15], #8" + + - + input: + bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr x3, [x15], #8" + + - + input: + bytes: [ 0xe3, 0xf9, 0x1f, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur b3, [x15, #-1]" + + - + input: + bytes: [ 0xe3, 0x29, 0x00, 0x5d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur h3, [x15, #2]" + + - + input: + bytes: [ 0xe3, 0xd9, 0x1f, 0x9d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur s3, [x15, #-3]" + + - + input: + bytes: [ 0xe3, 0x4b, 0x00, 0xdd ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur d3, [sp, #4]" + + - + input: + bytes: [ 0xe3, 0xb9, 0x9f, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur q3, [x15, #-5]" + + - + input: + bytes: [ 0xe3, 0x69, 0x40, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur b3, [x15, #6]" + + - + input: + bytes: [ 0xe3, 0x99, 0x5f, 0x5d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur h3, [x15, #-7]" + + - + input: + bytes: [ 0xe3, 0x89, 0x40, 0x9d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur s3, [x15, #8]" + + - + input: + bytes: [ 0xe3, 0x79, 0x5f, 0xdd ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur d3, [x15, #-9]" + + - + input: + bytes: [ 0xe3, 0xab, 0xc0, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur q3, [sp, #10]" + + - + input: + bytes: [ 0xe3, 0x85, 0x01, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stl1 { v3.d }[0], [x15]" + + - + input: + bytes: [ 0xe3, 0x87, 0x01, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "stl1 { v3.d }[1], [sp]" + + - + input: + bytes: [ 0xe3, 0x87, 0x41, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldap1 { v3.d }[0], [sp]" + + - + input: + bytes: [ 0xe3, 0x85, 0x41, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ] + expected: + insns: + - + asm_text: "ldap1 { v3.d }[1], [x15]" + + - + input: + bytes: [ 0x18, 0x0a, 0x00, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w24, w0, [x16, #-8]!" + + - + input: + bytes: [ 0x18, 0x0a, 0x00, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w24, w0, [x16, #-8]!" + + - + input: + bytes: [ 0x39, 0x0a, 0x01, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x25, x1, [x17, #-16]!" + + - + input: + bytes: [ 0x39, 0x0a, 0x01, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x25, x1, [x17, #-16]!" + + - + input: + bytes: [ 0x5a, 0x1a, 0x02, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w26, w2, [x18]" + + - + input: + bytes: [ 0xfb, 0x1b, 0x03, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x27, x3, [sp]" + + - + input: + bytes: [ 0x9c, 0x0a, 0x44, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w28, w4, [x20], #8" + + - + input: + bytes: [ 0x9c, 0x0a, 0x44, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w28, w4, [x20], #8" + + - + input: + bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp x29, x5, [x21], #16" + + - + input: + bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp x29, x5, [x21], #16" + + - + input: + bytes: [ 0xfe, 0x1b, 0x46, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w30, w6, [sp]" + + - + input: + bytes: [ 0xff, 0x1a, 0x47, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp xzr, x7, [x23]" + + - + input: + bytes: [ 0xe3, 0x09, 0x80, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr w3, [x15, #-4]!" + + - + input: + bytes: [ 0xe3, 0x09, 0x80, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr w3, [x15, #-4]!" + + - + input: + bytes: [ 0xe3, 0x09, 0x80, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr x3, [x15, #-8]!" + + - + input: + bytes: [ 0xe3, 0x0b, 0x80, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr x3, [sp, #-8]!" + + - + input: + bytes: [ 0xe3, 0x0b, 0xc0, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr w3, [sp], #4" + + - + input: + bytes: [ 0xe3, 0x09, 0xc0, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr w3, [x15], #4" + + - + input: + bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr x3, [x15], #8" + + - + input: + bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr x3, [x15], #8" + + - + input: + bytes: [ 0xe3, 0xf9, 0x1f, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur b3, [x15, #-1]" + + - + input: + bytes: [ 0xe3, 0x29, 0x00, 0x5d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur h3, [x15, #2]" + + - + input: + bytes: [ 0xe3, 0xd9, 0x1f, 0x9d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur s3, [x15, #-3]" + + - + input: + bytes: [ 0xe3, 0x4b, 0x00, 0xdd ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur d3, [sp, #4]" + + - + input: + bytes: [ 0xe3, 0xb9, 0x9f, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur q3, [x15, #-5]" + + - + input: + bytes: [ 0xe3, 0x69, 0x40, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur b3, [x15, #6]" + + - + input: + bytes: [ 0xe3, 0x99, 0x5f, 0x5d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur h3, [x15, #-7]" + + - + input: + bytes: [ 0xe3, 0x89, 0x40, 0x9d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur s3, [x15, #8]" + + - + input: + bytes: [ 0xe3, 0x79, 0x5f, 0xdd ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur d3, [x15, #-9]" + + - + input: + bytes: [ 0xe3, 0xab, 0xc0, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur q3, [sp, #10]" + + - + input: + bytes: [ 0xe3, 0x85, 0x01, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stl1 { v3.d }[0], [x15]" + + - + input: + bytes: [ 0xe3, 0x87, 0x01, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "stl1 { v3.d }[1], [sp]" + + - + input: + bytes: [ 0xe3, 0x87, 0x41, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldap1 { v3.d }[0], [sp]" + + - + input: + bytes: [ 0xe3, 0x85, 0x41, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldap1 { v3.d }[1], [x15]" + + - + input: + bytes: [ 0x18, 0x0a, 0x00, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w24, w0, [x16, #-8]!" + + - + input: + bytes: [ 0x18, 0x0a, 0x00, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w24, w0, [x16, #-8]!" + + - + input: + bytes: [ 0x39, 0x0a, 0x01, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x25, x1, [x17, #-16]!" + + - + input: + bytes: [ 0x39, 0x0a, 0x01, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x25, x1, [x17, #-16]!" + + - + input: + bytes: [ 0x5a, 0x1a, 0x02, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp w26, w2, [x18]" + + - + input: + bytes: [ 0xfb, 0x1b, 0x03, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stilp x27, x3, [sp]" + + - + input: + bytes: [ 0x9c, 0x0a, 0x44, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w28, w4, [x20], #8" + + - + input: + bytes: [ 0x9c, 0x0a, 0x44, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w28, w4, [x20], #8" + + - + input: + bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp x29, x5, [x21], #16" + + - + input: + bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp x29, x5, [x21], #16" + + - + input: + bytes: [ 0xfe, 0x1b, 0x46, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp w30, w6, [sp]" + + - + input: + bytes: [ 0xff, 0x1a, 0x47, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldiapp xzr, x7, [x23]" + + - + input: + bytes: [ 0xe3, 0x09, 0x80, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr w3, [x15, #-4]!" + + - + input: + bytes: [ 0xe3, 0x09, 0x80, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr w3, [x15, #-4]!" + + - + input: + bytes: [ 0xe3, 0x09, 0x80, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr x3, [x15, #-8]!" + + - + input: + bytes: [ 0xe3, 0x0b, 0x80, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlr x3, [sp, #-8]!" + + - + input: + bytes: [ 0xe3, 0x0b, 0xc0, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr w3, [sp], #4" + + - + input: + bytes: [ 0xe3, 0x09, 0xc0, 0x99 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr w3, [x15], #4" + + - + input: + bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr x3, [x15], #8" + + - + input: + bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapr x3, [x15], #8" + + - + input: + bytes: [ 0xe3, 0xf9, 0x1f, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur b3, [x15, #-1]" + + - + input: + bytes: [ 0xe3, 0x29, 0x00, 0x5d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur h3, [x15, #2]" + + - + input: + bytes: [ 0xe3, 0xd9, 0x1f, 0x9d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur s3, [x15, #-3]" + + - + input: + bytes: [ 0xe3, 0x4b, 0x00, 0xdd ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur d3, [sp, #4]" + + - + input: + bytes: [ 0xe3, 0xb9, 0x9f, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stlur q3, [x15, #-5]" + + - + input: + bytes: [ 0xe3, 0x69, 0x40, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur b3, [x15, #6]" + + - + input: + bytes: [ 0xe3, 0x99, 0x5f, 0x5d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur h3, [x15, #-7]" + + - + input: + bytes: [ 0xe3, 0x89, 0x40, 0x9d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur s3, [x15, #8]" + + - + input: + bytes: [ 0xe3, 0x79, 0x5f, 0xdd ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur d3, [x15, #-9]" + + - + input: + bytes: [ 0xe3, 0xab, 0xc0, 0x1d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldapur q3, [sp, #10]" + + - + input: + bytes: [ 0xe3, 0x85, 0x01, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stl1 { v3.d }[0], [x15]" + + - + input: + bytes: [ 0xe3, 0x87, 0x01, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "stl1 { v3.d }[1], [sp]" + + - + input: + bytes: [ 0xe3, 0x87, 0x41, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldap1 { v3.d }[0], [sp]" + + - + input: + bytes: [ 0xe3, 0x85, 0x41, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ] + expected: + insns: + - + asm_text: "ldap1 { v3.d }[1], [x15]" diff --git a/tests/MC/AArch64/armv8.9a-pfar.s.yaml b/tests/MC/AArch64/armv8.9a-pfar.s.yaml new file mode 100644 index 0000000000..cacd31866f --- /dev/null +++ b/tests/MC/AArch64/armv8.9a-pfar.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xa0, 0x60, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, PFAR_EL1" + + - + input: + bytes: [ 0xa0, 0x60, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr PFAR_EL1, x0" + + - + input: + bytes: [ 0xa0, 0x60, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, PFAR_EL2" + + - + input: + bytes: [ 0xa0, 0x60, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr PFAR_EL2, x0" + + - + input: + bytes: [ 0xa0, 0x60, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, PFAR_EL12" + + - + input: + bytes: [ 0xa0, 0x60, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr PFAR_EL12, x0" + + - + input: + bytes: [ 0xa0, 0x60, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, MFAR_EL3" + + - + input: + bytes: [ 0xa0, 0x60, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr MFAR_EL3, x0" diff --git a/tests/MC/AArch64/armv8.9a-prfm-slc.s.yaml b/tests/MC/AArch64/armv8.9a-prfm-slc.s.yaml new file mode 100644 index 0000000000..28b863fb18 --- /dev/null +++ b/tests/MC/AArch64/armv8.9a-prfm-slc.s.yaml @@ -0,0 +1,210 @@ +test_cases: + - + input: + bytes: [ 0x66, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "prfm pldslckeep, [x3]" + + - + input: + bytes: [ 0x67, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "prfm pldslcstrm, [x3]" + + - + input: + bytes: [ 0x6e, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "prfm plislckeep, [x3]" + + - + input: + bytes: [ 0x6f, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "prfm plislcstrm, [x3]" + + - + input: + bytes: [ 0x76, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "prfm pstslckeep, [x3]" + + - + input: + bytes: [ 0x77, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "prfm pstslcstrm, [x3]" + + - + input: + bytes: [ 0x66, 0x68, 0xa5, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "prfm pldslckeep, [x3, x5]" + + - + input: + bytes: [ 0x66, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ] + expected: + insns: + - + asm_text: "prfm pldslckeep, [x3]" + + - + input: + bytes: [ 0x67, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ] + expected: + insns: + - + asm_text: "prfm pldslcstrm, [x3]" + + - + input: + bytes: [ 0x6e, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ] + expected: + insns: + - + asm_text: "prfm plislckeep, [x3]" + + - + input: + bytes: [ 0x6f, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ] + expected: + insns: + - + asm_text: "prfm plislcstrm, [x3]" + + - + input: + bytes: [ 0x76, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ] + expected: + insns: + - + asm_text: "prfm pstslckeep, [x3]" + + - + input: + bytes: [ 0x77, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ] + expected: + insns: + - + asm_text: "prfm pstslcstrm, [x3]" + + - + input: + bytes: [ 0x66, 0x68, 0xa5, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ] + expected: + insns: + - + asm_text: "prfm pldslckeep, [x3, x5]" + + - + input: + bytes: [ 0x66, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "prfm pldslckeep, [x3]" + + - + input: + bytes: [ 0x67, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "prfm pldslcstrm, [x3]" + + - + input: + bytes: [ 0x6e, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "prfm plislckeep, [x3]" + + - + input: + bytes: [ 0x6f, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "prfm plislcstrm, [x3]" + + - + input: + bytes: [ 0x76, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "prfm pstslckeep, [x3]" + + - + input: + bytes: [ 0x77, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "prfm pstslcstrm, [x3]" + + - + input: + bytes: [ 0x66, 0x68, 0xa5, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "prfm pldslckeep, [x3, x5]" diff --git a/tests/MC/AArch64/armv8.9a-rasv2.s.yaml b/tests/MC/AArch64/armv8.9a-rasv2.s.yaml new file mode 100644 index 0000000000..b9f2e75401 --- /dev/null +++ b/tests/MC/AArch64/armv8.9a-rasv2.s.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0x40, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "rasv2" ] + expected: + insns: + - + asm_text: "mrs x0, ERXGSR_EL1" + + - + input: + bytes: [ 0x40, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ] + expected: + insns: + - + asm_text: "mrs x0, ERXGSR_EL1" + + - + input: + bytes: [ 0x40, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "mrs x0, ERXGSR_EL1" diff --git a/tests/MC/AArch64/armv8.9a-specres2.s.yaml b/tests/MC/AArch64/armv8.9a-specres2.s.yaml new file mode 100644 index 0000000000..d15a8b55c4 --- /dev/null +++ b/tests/MC/AArch64/armv8.9a-specres2.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0xc0, 0x73, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "specres2" ] + expected: + insns: + - + asm_text: "cosp rctx, x0" + + - + input: + bytes: [ 0xc0, 0x73, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "specres2" ] + expected: + insns: + - + asm_text: "cosp rctx, x0" + + - + input: + bytes: [ 0xc0, 0x73, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "cosp rctx, x0" + + - + input: + bytes: [ 0xc0, 0x73, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ] + expected: + insns: + - + asm_text: "cosp rctx, x0" + + - + input: + bytes: [ 0xc0, 0x73, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "cosp rctx, x0" + + - + input: + bytes: [ 0xc0, 0x73, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ] + expected: + insns: + - + asm_text: "cosp rctx, x0" diff --git a/tests/MC/AArch64/armv8a-fpmul.s.yaml b/tests/MC/AArch64/armv8a-fpmul.s.yaml new file mode 100644 index 0000000000..7708e20d71 --- /dev/null +++ b/tests/MC/AArch64/armv8a-fpmul.s.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xec, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlal v0.2s, v1.2h, v2.2h" + + - + input: + bytes: [ 0x20, 0xec, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl v0.2s, v1.2h, v2.2h" + + - + input: + bytes: [ 0x20, 0xec, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlal v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0xec, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0xcc, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlal2 v0.2s, v1.2h, v2.2h" + + - + input: + bytes: [ 0x20, 0xcc, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl2 v0.2s, v1.2h, v2.2h" + + - + input: + bytes: [ 0x20, 0xcc, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlal2 v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0xcc, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl2 v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x08, 0xb2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlal v0.2s, v1.2h, v2.h[7]" + + - + input: + bytes: [ 0x20, 0x48, 0xb2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl v0.2s, v1.2h, v2.h[7]" + + - + input: + bytes: [ 0x20, 0x08, 0xb2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlal v0.4s, v1.4h, v2.h[7]" + + - + input: + bytes: [ 0x20, 0x48, 0xb2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl v0.4s, v1.4h, v2.h[7]" + + - + input: + bytes: [ 0x20, 0x88, 0xb2, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlal2 v0.2s, v1.2h, v2.h[7]" + + - + input: + bytes: [ 0x20, 0xc8, 0xb2, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl2 v0.2s, v1.2h, v2.h[7]" + + - + input: + bytes: [ 0x20, 0x88, 0xb2, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlal2 v0.4s, v1.4h, v2.h[7]" + + - + input: + bytes: [ 0x20, 0xc8, 0xb2, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl2 v0.4s, v1.4h, v2.h[7]" + + - + input: + bytes: [ 0x20, 0x08, 0x92, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlal v0.2s, v1.2h, v2.h[5]" + + - + input: + bytes: [ 0x20, 0x48, 0x92, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl v0.2s, v1.2h, v2.h[5]" + + - + input: + bytes: [ 0x20, 0x08, 0x92, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlal v0.4s, v1.4h, v2.h[5]" + + - + input: + bytes: [ 0x20, 0x48, 0x92, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl v0.4s, v1.4h, v2.h[5]" + + - + input: + bytes: [ 0x20, 0x88, 0x92, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlal2 v0.2s, v1.2h, v2.h[5]" + + - + input: + bytes: [ 0x20, 0xc8, 0x92, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl2 v0.2s, v1.2h, v2.h[5]" + + - + input: + bytes: [ 0x20, 0x88, 0x92, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlal2 v0.4s, v1.4h, v2.h[5]" + + - + input: + bytes: [ 0x20, 0xc8, 0x92, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl2 v0.4s, v1.4h, v2.h[5]" + + - + input: + bytes: [ 0x20, 0xec, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlal v0.2s, v1.2h, v2.2h" + + - + input: + bytes: [ 0x20, 0xec, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl v0.2s, v1.2h, v2.2h" + + - + input: + bytes: [ 0x20, 0xec, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlal v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0xec, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0xcc, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlal2 v0.2s, v1.2h, v2.2h" + + - + input: + bytes: [ 0x20, 0xcc, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl2 v0.2s, v1.2h, v2.2h" + + - + input: + bytes: [ 0x20, 0xcc, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlal2 v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0xcc, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl2 v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x08, 0xb2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlal v0.2s, v1.2h, v2.h[7]" + + - + input: + bytes: [ 0x20, 0x48, 0xb2, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl v0.2s, v1.2h, v2.h[7]" + + - + input: + bytes: [ 0x20, 0x08, 0xb2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlal v0.4s, v1.4h, v2.h[7]" + + - + input: + bytes: [ 0x20, 0x48, 0xb2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl v0.4s, v1.4h, v2.h[7]" + + - + input: + bytes: [ 0x20, 0x88, 0xb2, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlal2 v0.2s, v1.2h, v2.h[7]" + + - + input: + bytes: [ 0x20, 0xc8, 0xb2, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl2 v0.2s, v1.2h, v2.h[7]" + + - + input: + bytes: [ 0x20, 0x88, 0xb2, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlal2 v0.4s, v1.4h, v2.h[7]" + + - + input: + bytes: [ 0x20, 0xc8, 0xb2, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl2 v0.4s, v1.4h, v2.h[7]" + + - + input: + bytes: [ 0x20, 0x08, 0x92, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlal v0.2s, v1.2h, v2.h[5]" + + - + input: + bytes: [ 0x20, 0x48, 0x92, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl v0.2s, v1.2h, v2.h[5]" + + - + input: + bytes: [ 0x20, 0x08, 0x92, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlal v0.4s, v1.4h, v2.h[5]" + + - + input: + bytes: [ 0x20, 0x48, 0x92, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl v0.4s, v1.4h, v2.h[5]" + + - + input: + bytes: [ 0x20, 0x88, 0x92, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlal2 v0.2s, v1.2h, v2.h[5]" + + - + input: + bytes: [ 0x20, 0xc8, 0x92, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl2 v0.2s, v1.2h, v2.h[5]" + + - + input: + bytes: [ 0x20, 0x88, 0x92, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlal2 v0.4s, v1.4h, v2.h[5]" + + - + input: + bytes: [ 0x20, 0xc8, 0x92, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ] + expected: + insns: + - + asm_text: "fmlsl2 v0.4s, v1.4h, v2.h[5]" diff --git a/tests/MC/AArch64/armv8r-inst.s.yaml b/tests/MC/AArch64/armv8r-inst.s.yaml new file mode 100644 index 0000000000..6040858210 --- /dev/null +++ b/tests/MC/AArch64/armv8r-inst.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x9f, 0x3c, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "dfb" diff --git a/tests/MC/AArch64/armv8r-sysreg.s.yaml b/tests/MC/AArch64/armv8r-sysreg.s.yaml new file mode 100644 index 0000000000..d593ffb092 --- /dev/null +++ b/tests/MC/AArch64/armv8r-sysreg.s.yaml @@ -0,0 +1,2850 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, TTBR0_EL2" + + - + input: + bytes: [ 0x80, 0x00, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, MPUIR_EL1" + + - + input: + bytes: [ 0x80, 0x00, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, MPUIR_EL2" + + - + input: + bytes: [ 0x20, 0x61, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRENR_EL1" + + - + input: + bytes: [ 0x20, 0x61, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRENR_EL2" + + - + input: + bytes: [ 0x20, 0x62, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRSELR_EL1" + + - + input: + bytes: [ 0x20, 0x62, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRSELR_EL2" + + - + input: + bytes: [ 0x00, 0x68, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR_EL1" + + - + input: + bytes: [ 0x00, 0x68, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR_EL2" + + - + input: + bytes: [ 0x20, 0x68, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR_EL1" + + - + input: + bytes: [ 0x20, 0x68, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR_EL2" + + - + input: + bytes: [ 0x80, 0x68, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR1_EL1" + + - + input: + bytes: [ 0x00, 0x69, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR2_EL1" + + - + input: + bytes: [ 0x80, 0x69, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR3_EL1" + + - + input: + bytes: [ 0x00, 0x6a, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR4_EL1" + + - + input: + bytes: [ 0x80, 0x6a, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR5_EL1" + + - + input: + bytes: [ 0x00, 0x6b, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR6_EL1" + + - + input: + bytes: [ 0x80, 0x6b, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR7_EL1" + + - + input: + bytes: [ 0x00, 0x6c, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR8_EL1" + + - + input: + bytes: [ 0x80, 0x6c, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR9_EL1" + + - + input: + bytes: [ 0x00, 0x6d, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR10_EL1" + + - + input: + bytes: [ 0x80, 0x6d, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR11_EL1" + + - + input: + bytes: [ 0x00, 0x6e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR12_EL1" + + - + input: + bytes: [ 0x80, 0x6e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR13_EL1" + + - + input: + bytes: [ 0x00, 0x6f, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR14_EL1" + + - + input: + bytes: [ 0x80, 0x6f, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR15_EL1" + + - + input: + bytes: [ 0xa0, 0x68, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR1_EL1" + + - + input: + bytes: [ 0x20, 0x69, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR2_EL1" + + - + input: + bytes: [ 0xa0, 0x69, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR3_EL1" + + - + input: + bytes: [ 0x20, 0x6a, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR4_EL1" + + - + input: + bytes: [ 0xa0, 0x6a, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR5_EL1" + + - + input: + bytes: [ 0x20, 0x6b, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR6_EL1" + + - + input: + bytes: [ 0xa0, 0x6b, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR7_EL1" + + - + input: + bytes: [ 0x20, 0x6c, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR8_EL1" + + - + input: + bytes: [ 0xa0, 0x6c, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR9_EL1" + + - + input: + bytes: [ 0x20, 0x6d, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR10_EL1" + + - + input: + bytes: [ 0xa0, 0x6d, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR11_EL1" + + - + input: + bytes: [ 0x20, 0x6e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR12_EL1" + + - + input: + bytes: [ 0xa0, 0x6e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR13_EL1" + + - + input: + bytes: [ 0x20, 0x6f, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR14_EL1" + + - + input: + bytes: [ 0xa0, 0x6f, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR15_EL1" + + - + input: + bytes: [ 0x80, 0x68, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR1_EL2" + + - + input: + bytes: [ 0x00, 0x69, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR2_EL2" + + - + input: + bytes: [ 0x80, 0x69, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR3_EL2" + + - + input: + bytes: [ 0x00, 0x6a, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR4_EL2" + + - + input: + bytes: [ 0x80, 0x6a, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR5_EL2" + + - + input: + bytes: [ 0x00, 0x6b, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR6_EL2" + + - + input: + bytes: [ 0x80, 0x6b, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR7_EL2" + + - + input: + bytes: [ 0x00, 0x6c, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR8_EL2" + + - + input: + bytes: [ 0x80, 0x6c, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR9_EL2" + + - + input: + bytes: [ 0x00, 0x6d, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR10_EL2" + + - + input: + bytes: [ 0x80, 0x6d, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR11_EL2" + + - + input: + bytes: [ 0x00, 0x6e, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR12_EL2" + + - + input: + bytes: [ 0x80, 0x6e, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR13_EL2" + + - + input: + bytes: [ 0x00, 0x6f, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR14_EL2" + + - + input: + bytes: [ 0x80, 0x6f, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRBAR15_EL2" + + - + input: + bytes: [ 0xa0, 0x68, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR1_EL2" + + - + input: + bytes: [ 0x20, 0x69, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR2_EL2" + + - + input: + bytes: [ 0xa0, 0x69, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR3_EL2" + + - + input: + bytes: [ 0x20, 0x6a, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR4_EL2" + + - + input: + bytes: [ 0xa0, 0x6a, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR5_EL2" + + - + input: + bytes: [ 0x20, 0x6b, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR6_EL2" + + - + input: + bytes: [ 0xa0, 0x6b, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR7_EL2" + + - + input: + bytes: [ 0x20, 0x6c, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR8_EL2" + + - + input: + bytes: [ 0xa0, 0x6c, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR9_EL2" + + - + input: + bytes: [ 0x20, 0x6d, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR10_EL2" + + - + input: + bytes: [ 0xa0, 0x6d, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR11_EL2" + + - + input: + bytes: [ 0x20, 0x6e, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR12_EL2" + + - + input: + bytes: [ 0xa0, 0x6e, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR13_EL2" + + - + input: + bytes: [ 0x20, 0x6f, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR14_EL2" + + - + input: + bytes: [ 0xa0, 0x6f, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, PRLAR15_EL2" + + - + input: + bytes: [ 0x1e, 0x20, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, TTBR0_EL2" + + - + input: + bytes: [ 0x9e, 0x00, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, MPUIR_EL1" + + - + input: + bytes: [ 0x9e, 0x00, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, MPUIR_EL2" + + - + input: + bytes: [ 0x3e, 0x61, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRENR_EL1" + + - + input: + bytes: [ 0x3e, 0x61, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRENR_EL2" + + - + input: + bytes: [ 0x3e, 0x62, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRSELR_EL1" + + - + input: + bytes: [ 0x3e, 0x62, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRSELR_EL2" + + - + input: + bytes: [ 0x1e, 0x68, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR_EL1" + + - + input: + bytes: [ 0x1e, 0x68, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR_EL2" + + - + input: + bytes: [ 0x3e, 0x68, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR_EL1" + + - + input: + bytes: [ 0x3e, 0x68, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR_EL2" + + - + input: + bytes: [ 0x9e, 0x68, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR1_EL1" + + - + input: + bytes: [ 0x1e, 0x69, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR2_EL1" + + - + input: + bytes: [ 0x9e, 0x69, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR3_EL1" + + - + input: + bytes: [ 0x1e, 0x6a, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR4_EL1" + + - + input: + bytes: [ 0x9e, 0x6a, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR5_EL1" + + - + input: + bytes: [ 0x1e, 0x6b, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR6_EL1" + + - + input: + bytes: [ 0x9e, 0x6b, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR7_EL1" + + - + input: + bytes: [ 0x1e, 0x6c, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR8_EL1" + + - + input: + bytes: [ 0x9e, 0x6c, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR9_EL1" + + - + input: + bytes: [ 0x1e, 0x6d, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR10_EL1" + + - + input: + bytes: [ 0x9e, 0x6d, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR11_EL1" + + - + input: + bytes: [ 0x1e, 0x6e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR12_EL1" + + - + input: + bytes: [ 0x9e, 0x6e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR13_EL1" + + - + input: + bytes: [ 0x1e, 0x6f, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR14_EL1" + + - + input: + bytes: [ 0x9e, 0x6f, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR15_EL1" + + - + input: + bytes: [ 0xbe, 0x68, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR1_EL1" + + - + input: + bytes: [ 0x3e, 0x69, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR2_EL1" + + - + input: + bytes: [ 0xbe, 0x69, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR3_EL1" + + - + input: + bytes: [ 0x3e, 0x6a, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR4_EL1" + + - + input: + bytes: [ 0xbe, 0x6a, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR5_EL1" + + - + input: + bytes: [ 0x3e, 0x6b, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR6_EL1" + + - + input: + bytes: [ 0xbe, 0x6b, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR7_EL1" + + - + input: + bytes: [ 0x3e, 0x6c, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR8_EL1" + + - + input: + bytes: [ 0xbe, 0x6c, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR9_EL1" + + - + input: + bytes: [ 0x3e, 0x6d, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR10_EL1" + + - + input: + bytes: [ 0xbe, 0x6d, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR11_EL1" + + - + input: + bytes: [ 0x3e, 0x6e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR12_EL1" + + - + input: + bytes: [ 0xbe, 0x6e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR13_EL1" + + - + input: + bytes: [ 0x3e, 0x6f, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR14_EL1" + + - + input: + bytes: [ 0xbe, 0x6f, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR15_EL1" + + - + input: + bytes: [ 0x9e, 0x68, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR1_EL2" + + - + input: + bytes: [ 0x1e, 0x69, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR2_EL2" + + - + input: + bytes: [ 0x9e, 0x69, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR3_EL2" + + - + input: + bytes: [ 0x1e, 0x6a, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR4_EL2" + + - + input: + bytes: [ 0x9e, 0x6a, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR5_EL2" + + - + input: + bytes: [ 0x1e, 0x6b, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR6_EL2" + + - + input: + bytes: [ 0x9e, 0x6b, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR7_EL2" + + - + input: + bytes: [ 0x1e, 0x6c, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR8_EL2" + + - + input: + bytes: [ 0x9e, 0x6c, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR9_EL2" + + - + input: + bytes: [ 0x1e, 0x6d, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR10_EL2" + + - + input: + bytes: [ 0x9e, 0x6d, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR11_EL2" + + - + input: + bytes: [ 0x1e, 0x6e, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR12_EL2" + + - + input: + bytes: [ 0x9e, 0x6e, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR13_EL2" + + - + input: + bytes: [ 0x1e, 0x6f, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR14_EL2" + + - + input: + bytes: [ 0x9e, 0x6f, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRBAR15_EL2" + + - + input: + bytes: [ 0xbe, 0x68, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR1_EL2" + + - + input: + bytes: [ 0x3e, 0x69, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR2_EL2" + + - + input: + bytes: [ 0xbe, 0x69, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR3_EL2" + + - + input: + bytes: [ 0x3e, 0x6a, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR4_EL2" + + - + input: + bytes: [ 0xbe, 0x6a, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR5_EL2" + + - + input: + bytes: [ 0x3e, 0x6b, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR6_EL2" + + - + input: + bytes: [ 0xbe, 0x6b, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR7_EL2" + + - + input: + bytes: [ 0x3e, 0x6c, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR8_EL2" + + - + input: + bytes: [ 0xbe, 0x6c, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR9_EL2" + + - + input: + bytes: [ 0x3e, 0x6d, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR10_EL2" + + - + input: + bytes: [ 0xbe, 0x6d, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR11_EL2" + + - + input: + bytes: [ 0x3e, 0x6e, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR12_EL2" + + - + input: + bytes: [ 0xbe, 0x6e, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR13_EL2" + + - + input: + bytes: [ 0x3e, 0x6f, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR14_EL2" + + - + input: + bytes: [ 0xbe, 0x6f, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "mrs x30, PRLAR15_EL2" + + - + input: + bytes: [ 0x00, 0x20, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr TTBR0_EL2, x0" + + - + input: + bytes: [ 0x80, 0x00, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr MPUIR_EL1, x0" + + - + input: + bytes: [ 0x80, 0x00, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr MPUIR_EL2, x0" + + - + input: + bytes: [ 0x20, 0x61, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRENR_EL1, x0" + + - + input: + bytes: [ 0x20, 0x61, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRENR_EL2, x0" + + - + input: + bytes: [ 0x20, 0x62, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRSELR_EL1, x0" + + - + input: + bytes: [ 0x20, 0x62, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRSELR_EL2, x0" + + - + input: + bytes: [ 0x00, 0x68, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR_EL1, x0" + + - + input: + bytes: [ 0x00, 0x68, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR_EL2, x0" + + - + input: + bytes: [ 0x20, 0x68, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR_EL1, x0" + + - + input: + bytes: [ 0x20, 0x68, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR_EL2, x0" + + - + input: + bytes: [ 0x80, 0x68, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR1_EL1, x0" + + - + input: + bytes: [ 0x00, 0x69, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR2_EL1, x0" + + - + input: + bytes: [ 0x80, 0x69, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR3_EL1, x0" + + - + input: + bytes: [ 0x00, 0x6a, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR4_EL1, x0" + + - + input: + bytes: [ 0x80, 0x6a, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR5_EL1, x0" + + - + input: + bytes: [ 0x00, 0x6b, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR6_EL1, x0" + + - + input: + bytes: [ 0x80, 0x6b, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR7_EL1, x0" + + - + input: + bytes: [ 0x00, 0x6c, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR8_EL1, x0" + + - + input: + bytes: [ 0x80, 0x6c, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR9_EL1, x0" + + - + input: + bytes: [ 0x00, 0x6d, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR10_EL1, x0" + + - + input: + bytes: [ 0x80, 0x6d, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR11_EL1, x0" + + - + input: + bytes: [ 0x00, 0x6e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR12_EL1, x0" + + - + input: + bytes: [ 0x80, 0x6e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR13_EL1, x0" + + - + input: + bytes: [ 0x00, 0x6f, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR14_EL1, x0" + + - + input: + bytes: [ 0x80, 0x6f, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR15_EL1, x0" + + - + input: + bytes: [ 0xa0, 0x68, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR1_EL1, x0" + + - + input: + bytes: [ 0x20, 0x69, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR2_EL1, x0" + + - + input: + bytes: [ 0xa0, 0x69, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR3_EL1, x0" + + - + input: + bytes: [ 0x20, 0x6a, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR4_EL1, x0" + + - + input: + bytes: [ 0xa0, 0x6a, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR5_EL1, x0" + + - + input: + bytes: [ 0x20, 0x6b, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR6_EL1, x0" + + - + input: + bytes: [ 0xa0, 0x6b, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR7_EL1, x0" + + - + input: + bytes: [ 0x20, 0x6c, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR8_EL1, x0" + + - + input: + bytes: [ 0xa0, 0x6c, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR9_EL1, x0" + + - + input: + bytes: [ 0x20, 0x6d, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR10_EL1, x0" + + - + input: + bytes: [ 0xa0, 0x6d, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR11_EL1, x0" + + - + input: + bytes: [ 0x20, 0x6e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR12_EL1, x0" + + - + input: + bytes: [ 0xa0, 0x6e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR13_EL1, x0" + + - + input: + bytes: [ 0x20, 0x6f, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR14_EL1, x0" + + - + input: + bytes: [ 0xa0, 0x6f, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR15_EL1, x0" + + - + input: + bytes: [ 0x80, 0x68, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR1_EL2, x0" + + - + input: + bytes: [ 0x00, 0x69, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR2_EL2, x0" + + - + input: + bytes: [ 0x80, 0x69, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR3_EL2, x0" + + - + input: + bytes: [ 0x00, 0x6a, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR4_EL2, x0" + + - + input: + bytes: [ 0x80, 0x6a, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR5_EL2, x0" + + - + input: + bytes: [ 0x00, 0x6b, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR6_EL2, x0" + + - + input: + bytes: [ 0x80, 0x6b, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR7_EL2, x0" + + - + input: + bytes: [ 0x00, 0x6c, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR8_EL2, x0" + + - + input: + bytes: [ 0x80, 0x6c, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR9_EL2, x0" + + - + input: + bytes: [ 0x00, 0x6d, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR10_EL2, x0" + + - + input: + bytes: [ 0x80, 0x6d, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR11_EL2, x0" + + - + input: + bytes: [ 0x00, 0x6e, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR12_EL2, x0" + + - + input: + bytes: [ 0x80, 0x6e, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR13_EL2, x0" + + - + input: + bytes: [ 0x00, 0x6f, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR14_EL2, x0" + + - + input: + bytes: [ 0x80, 0x6f, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR15_EL2, x0" + + - + input: + bytes: [ 0xa0, 0x68, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR1_EL2, x0" + + - + input: + bytes: [ 0x20, 0x69, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR2_EL2, x0" + + - + input: + bytes: [ 0xa0, 0x69, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR3_EL2, x0" + + - + input: + bytes: [ 0x20, 0x6a, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR4_EL2, x0" + + - + input: + bytes: [ 0xa0, 0x6a, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR5_EL2, x0" + + - + input: + bytes: [ 0x20, 0x6b, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR6_EL2, x0" + + - + input: + bytes: [ 0xa0, 0x6b, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR7_EL2, x0" + + - + input: + bytes: [ 0x20, 0x6c, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR8_EL2, x0" + + - + input: + bytes: [ 0xa0, 0x6c, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR9_EL2, x0" + + - + input: + bytes: [ 0x20, 0x6d, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR10_EL2, x0" + + - + input: + bytes: [ 0xa0, 0x6d, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR11_EL2, x0" + + - + input: + bytes: [ 0x20, 0x6e, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR12_EL2, x0" + + - + input: + bytes: [ 0xa0, 0x6e, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR13_EL2, x0" + + - + input: + bytes: [ 0x20, 0x6f, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR14_EL2, x0" + + - + input: + bytes: [ 0xa0, 0x6f, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR15_EL2, x0" + + - + input: + bytes: [ 0x1e, 0x20, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr TTBR0_EL2, x30" + + - + input: + bytes: [ 0x9e, 0x00, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr MPUIR_EL1, x30" + + - + input: + bytes: [ 0x9e, 0x00, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr MPUIR_EL2, x30" + + - + input: + bytes: [ 0x3e, 0x61, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRENR_EL1, x30" + + - + input: + bytes: [ 0x3e, 0x61, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRENR_EL2, x30" + + - + input: + bytes: [ 0x3e, 0x62, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRSELR_EL1, x30" + + - + input: + bytes: [ 0x3e, 0x62, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRSELR_EL2, x30" + + - + input: + bytes: [ 0x1e, 0x68, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR_EL1, x30" + + - + input: + bytes: [ 0x1e, 0x68, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR_EL2, x30" + + - + input: + bytes: [ 0x3e, 0x68, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR_EL1, x30" + + - + input: + bytes: [ 0x3e, 0x68, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR_EL2, x30" + + - + input: + bytes: [ 0x9e, 0x68, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR1_EL1, x30" + + - + input: + bytes: [ 0x1e, 0x69, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR2_EL1, x30" + + - + input: + bytes: [ 0x9e, 0x69, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR3_EL1, x30" + + - + input: + bytes: [ 0x1e, 0x6a, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR4_EL1, x30" + + - + input: + bytes: [ 0x9e, 0x6a, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR5_EL1, x30" + + - + input: + bytes: [ 0x1e, 0x6b, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR6_EL1, x30" + + - + input: + bytes: [ 0x9e, 0x6b, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR7_EL1, x30" + + - + input: + bytes: [ 0x1e, 0x6c, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR8_EL1, x30" + + - + input: + bytes: [ 0x9e, 0x6c, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR9_EL1, x30" + + - + input: + bytes: [ 0x1e, 0x6d, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR10_EL1, x30" + + - + input: + bytes: [ 0x9e, 0x6d, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR11_EL1, x30" + + - + input: + bytes: [ 0x1e, 0x6e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR12_EL1, x30" + + - + input: + bytes: [ 0x9e, 0x6e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR13_EL1, x30" + + - + input: + bytes: [ 0x1e, 0x6f, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR14_EL1, x30" + + - + input: + bytes: [ 0x9e, 0x6f, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR15_EL1, x30" + + - + input: + bytes: [ 0xbe, 0x68, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR1_EL1, x30" + + - + input: + bytes: [ 0x3e, 0x69, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR2_EL1, x30" + + - + input: + bytes: [ 0xbe, 0x69, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR3_EL1, x30" + + - + input: + bytes: [ 0x3e, 0x6a, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR4_EL1, x30" + + - + input: + bytes: [ 0xbe, 0x6a, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR5_EL1, x30" + + - + input: + bytes: [ 0x3e, 0x6b, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR6_EL1, x30" + + - + input: + bytes: [ 0xbe, 0x6b, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR7_EL1, x30" + + - + input: + bytes: [ 0x3e, 0x6c, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR8_EL1, x30" + + - + input: + bytes: [ 0xbe, 0x6c, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR9_EL1, x30" + + - + input: + bytes: [ 0x3e, 0x6d, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR10_EL1, x30" + + - + input: + bytes: [ 0xbe, 0x6d, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR11_EL1, x30" + + - + input: + bytes: [ 0x3e, 0x6e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR12_EL1, x30" + + - + input: + bytes: [ 0xbe, 0x6e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR13_EL1, x30" + + - + input: + bytes: [ 0x3e, 0x6f, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR14_EL1, x30" + + - + input: + bytes: [ 0xbe, 0x6f, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR15_EL1, x30" + + - + input: + bytes: [ 0x9e, 0x68, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR1_EL2, x30" + + - + input: + bytes: [ 0x1e, 0x69, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR2_EL2, x30" + + - + input: + bytes: [ 0x9e, 0x69, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR3_EL2, x30" + + - + input: + bytes: [ 0x1e, 0x6a, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR4_EL2, x30" + + - + input: + bytes: [ 0x9e, 0x6a, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR5_EL2, x30" + + - + input: + bytes: [ 0x1e, 0x6b, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR6_EL2, x30" + + - + input: + bytes: [ 0x9e, 0x6b, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR7_EL2, x30" + + - + input: + bytes: [ 0x1e, 0x6c, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR8_EL2, x30" + + - + input: + bytes: [ 0x9e, 0x6c, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR9_EL2, x30" + + - + input: + bytes: [ 0x1e, 0x6d, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR10_EL2, x30" + + - + input: + bytes: [ 0x9e, 0x6d, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR11_EL2, x30" + + - + input: + bytes: [ 0x1e, 0x6e, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR12_EL2, x30" + + - + input: + bytes: [ 0x9e, 0x6e, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR13_EL2, x30" + + - + input: + bytes: [ 0x1e, 0x6f, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR14_EL2, x30" + + - + input: + bytes: [ 0x9e, 0x6f, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRBAR15_EL2, x30" + + - + input: + bytes: [ 0xbe, 0x68, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR1_EL2, x30" + + - + input: + bytes: [ 0x3e, 0x69, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR2_EL2, x30" + + - + input: + bytes: [ 0xbe, 0x69, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR3_EL2, x30" + + - + input: + bytes: [ 0x3e, 0x6a, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR4_EL2, x30" + + - + input: + bytes: [ 0xbe, 0x6a, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR5_EL2, x30" + + - + input: + bytes: [ 0x3e, 0x6b, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR6_EL2, x30" + + - + input: + bytes: [ 0xbe, 0x6b, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR7_EL2, x30" + + - + input: + bytes: [ 0x3e, 0x6c, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR8_EL2, x30" + + - + input: + bytes: [ 0xbe, 0x6c, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR9_EL2, x30" + + - + input: + bytes: [ 0x3e, 0x6d, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR10_EL2, x30" + + - + input: + bytes: [ 0xbe, 0x6d, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR11_EL2, x30" + + - + input: + bytes: [ 0x3e, 0x6e, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR12_EL2, x30" + + - + input: + bytes: [ 0xbe, 0x6e, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR13_EL2, x30" + + - + input: + bytes: [ 0x3e, 0x6f, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR14_EL2, x30" + + - + input: + bytes: [ 0xbe, 0x6f, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr PRLAR15_EL2, x30" + + - + input: + bytes: [ 0x20, 0xd0, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ] + expected: + insns: + - + asm_text: "msr CONTEXTIDR_EL2, x0" diff --git a/tests/MC/AArch64/armv8r-unsupported-inst.s.yaml b/tests/MC/AArch64/armv8r-unsupported-inst.s.yaml new file mode 100644 index 0000000000..4e7b7357e1 --- /dev/null +++ b/tests/MC/AArch64/armv8r-unsupported-inst.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x03, 0x00, 0xa0, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "el3" ] + expected: + insns: + - + asm_text: "dcps3" + + - + input: + bytes: [ 0x83, 0x00, 0xa0, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "el3" ] + expected: + insns: + - + asm_text: "dcps3 #0x4" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "el3" ] + expected: + insns: + - + asm_text: "smc #0x7" + + - + input: + bytes: [ 0x03, 0x00, 0xa0, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ] + expected: + insns: + - + asm_text: "dcps3" + + - + input: + bytes: [ 0x83, 0x00, 0xa0, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ] + expected: + insns: + - + asm_text: "dcps3 #0x4" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ] + expected: + insns: + - + asm_text: "smc #0x7" diff --git a/tests/MC/AArch64/armv8r-unsupported-sysreg.s.yaml b/tests/MC/AArch64/armv8r-unsupported-sysreg.s.yaml new file mode 100644 index 0000000000..f4b126a8f2 --- /dev/null +++ b/tests/MC/AArch64/armv8r-unsupported-sysreg.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x03, 0x20, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ] + expected: + insns: + - + asm_text: "msr TTBR0_EL2, x3" + + - + input: + bytes: [ 0x03, 0x20, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ] + expected: + insns: + - + asm_text: "mrs x3, TTBR0_EL2" + + - + input: + bytes: [ 0x03, 0x21, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ] + expected: + insns: + - + asm_text: "msr VTTBR_EL2, x3" + + - + input: + bytes: [ 0x03, 0x21, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ] + expected: + insns: + - + asm_text: "mrs x3, VTTBR_EL2" + + - + input: + bytes: [ 0x03, 0x26, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ] + expected: + insns: + - + asm_text: "msr VSTTBR_EL2, x3" + + - + input: + bytes: [ 0x03, 0x26, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ] + expected: + insns: + - + asm_text: "mrs x3, VSTTBR_EL2" diff --git a/tests/MC/AArch64/armv9-sysreg128.txt.yaml b/tests/MC/AArch64/armv9-sysreg128.txt.yaml new file mode 100644 index 0000000000..675717a82d --- /dev/null +++ b/tests/MC/AArch64/armv9-sysreg128.txt.yaml @@ -0,0 +1,1320 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x78, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, TTBR0_EL1" + + - + input: + bytes: [ 0x20, 0x20, 0x78, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, TTBR1_EL1" + + - + input: + bytes: [ 0x00, 0x74, 0x78, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, PAR_EL1" + + - + input: + bytes: [ 0x60, 0xd0, 0x78, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, RCWSMASK_EL1" + + - + input: + bytes: [ 0xc0, 0xd0, 0x78, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, RCWMASK_EL1" + + - + input: + bytes: [ 0x00, 0x20, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, TTBR0_EL2" + + - + input: + bytes: [ 0x20, 0x20, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, TTBR1_EL2" + + - + input: + bytes: [ 0x00, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, VTTBR_EL2" + + - + input: + bytes: [ 0x00, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, VTTBR_EL2" + + - + input: + bytes: [ 0x02, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x2, x3, VTTBR_EL2" + + - + input: + bytes: [ 0x04, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x4, x5, VTTBR_EL2" + + - + input: + bytes: [ 0x06, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x6, x7, VTTBR_EL2" + + - + input: + bytes: [ 0x08, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x8, x9, VTTBR_EL2" + + - + input: + bytes: [ 0x0a, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x10, x11, VTTBR_EL2" + + - + input: + bytes: [ 0x0c, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x12, x13, VTTBR_EL2" + + - + input: + bytes: [ 0x0e, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x14, x15, VTTBR_EL2" + + - + input: + bytes: [ 0x10, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x16, x17, VTTBR_EL2" + + - + input: + bytes: [ 0x12, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x18, x19, VTTBR_EL2" + + - + input: + bytes: [ 0x14, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x20, x21, VTTBR_EL2" + + - + input: + bytes: [ 0x16, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x22, x23, VTTBR_EL2" + + - + input: + bytes: [ 0x18, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x24, x25, VTTBR_EL2" + + - + input: + bytes: [ 0x1a, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "mrrs x26, x27, VTTBR_EL2" + + - + input: + bytes: [ 0x00, 0x20, 0x58, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr TTBR0_EL1, x0, x1" + + - + input: + bytes: [ 0x20, 0x20, 0x58, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr TTBR1_EL1, x0, x1" + + - + input: + bytes: [ 0x00, 0x74, 0x58, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr PAR_EL1, x0, x1" + + - + input: + bytes: [ 0x60, 0xd0, 0x58, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr RCWSMASK_EL1, x0, x1" + + - + input: + bytes: [ 0xc0, 0xd0, 0x58, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr RCWMASK_EL1, x0, x1" + + - + input: + bytes: [ 0x00, 0x20, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr TTBR0_EL2, x0, x1" + + - + input: + bytes: [ 0x20, 0x20, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr TTBR1_EL2, x0, x1" + + - + input: + bytes: [ 0x00, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x0, x1" + + - + input: + bytes: [ 0x00, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x0, x1" + + - + input: + bytes: [ 0x02, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x2, x3" + + - + input: + bytes: [ 0x04, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x4, x5" + + - + input: + bytes: [ 0x06, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x6, x7" + + - + input: + bytes: [ 0x08, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x8, x9" + + - + input: + bytes: [ 0x0a, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x10, x11" + + - + input: + bytes: [ 0x0c, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x12, x13" + + - + input: + bytes: [ 0x0e, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x14, x15" + + - + input: + bytes: [ 0x10, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x16, x17" + + - + input: + bytes: [ 0x12, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x18, x19" + + - + input: + bytes: [ 0x14, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x20, x21" + + - + input: + bytes: [ 0x16, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x22, x23" + + - + input: + bytes: [ 0x18, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x24, x25" + + - + input: + bytes: [ 0x1a, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x26, x27" + + - + input: + bytes: [ 0x00, 0x20, 0x78, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, TTBR0_EL1" + + - + input: + bytes: [ 0x20, 0x20, 0x78, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, TTBR1_EL1" + + - + input: + bytes: [ 0x00, 0x74, 0x78, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, PAR_EL1" + + - + input: + bytes: [ 0x60, 0xd0, 0x78, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, RCWSMASK_EL1" + + - + input: + bytes: [ 0xc0, 0xd0, 0x78, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, RCWMASK_EL1" + + - + input: + bytes: [ 0x00, 0x20, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, TTBR0_EL2" + + - + input: + bytes: [ 0x20, 0x20, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, TTBR1_EL2" + + - + input: + bytes: [ 0x00, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, VTTBR_EL2" + + - + input: + bytes: [ 0x00, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, VTTBR_EL2" + + - + input: + bytes: [ 0x02, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x2, x3, VTTBR_EL2" + + - + input: + bytes: [ 0x04, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x4, x5, VTTBR_EL2" + + - + input: + bytes: [ 0x06, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x6, x7, VTTBR_EL2" + + - + input: + bytes: [ 0x08, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x8, x9, VTTBR_EL2" + + - + input: + bytes: [ 0x0a, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x10, x11, VTTBR_EL2" + + - + input: + bytes: [ 0x0c, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x12, x13, VTTBR_EL2" + + - + input: + bytes: [ 0x0e, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x14, x15, VTTBR_EL2" + + - + input: + bytes: [ 0x10, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x16, x17, VTTBR_EL2" + + - + input: + bytes: [ 0x12, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x18, x19, VTTBR_EL2" + + - + input: + bytes: [ 0x14, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x20, x21, VTTBR_EL2" + + - + input: + bytes: [ 0x16, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x22, x23, VTTBR_EL2" + + - + input: + bytes: [ 0x18, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x24, x25, VTTBR_EL2" + + - + input: + bytes: [ 0x1a, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "mrrs x26, x27, VTTBR_EL2" + + - + input: + bytes: [ 0x00, 0x20, 0x58, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr TTBR0_EL1, x0, x1" + + - + input: + bytes: [ 0x20, 0x20, 0x58, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr TTBR1_EL1, x0, x1" + + - + input: + bytes: [ 0x00, 0x74, 0x58, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr PAR_EL1, x0, x1" + + - + input: + bytes: [ 0x60, 0xd0, 0x58, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr RCWSMASK_EL1, x0, x1" + + - + input: + bytes: [ 0xc0, 0xd0, 0x58, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr RCWMASK_EL1, x0, x1" + + - + input: + bytes: [ 0x00, 0x20, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr TTBR0_EL2, x0, x1" + + - + input: + bytes: [ 0x20, 0x20, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr TTBR1_EL2, x0, x1" + + - + input: + bytes: [ 0x00, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x0, x1" + + - + input: + bytes: [ 0x00, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x0, x1" + + - + input: + bytes: [ 0x02, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x2, x3" + + - + input: + bytes: [ 0x04, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x4, x5" + + - + input: + bytes: [ 0x06, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x6, x7" + + - + input: + bytes: [ 0x08, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x8, x9" + + - + input: + bytes: [ 0x0a, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x10, x11" + + - + input: + bytes: [ 0x0c, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x12, x13" + + - + input: + bytes: [ 0x0e, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x14, x15" + + - + input: + bytes: [ 0x10, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x16, x17" + + - + input: + bytes: [ 0x12, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x18, x19" + + - + input: + bytes: [ 0x14, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x20, x21" + + - + input: + bytes: [ 0x16, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x22, x23" + + - + input: + bytes: [ 0x18, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x24, x25" + + - + input: + bytes: [ 0x1a, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x26, x27" + + - + input: + bytes: [ 0x00, 0x20, 0x78, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, TTBR0_EL1" + + - + input: + bytes: [ 0x20, 0x20, 0x78, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, TTBR1_EL1" + + - + input: + bytes: [ 0x00, 0x74, 0x78, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, PAR_EL1" + + - + input: + bytes: [ 0x60, 0xd0, 0x78, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, RCWSMASK_EL1" + + - + input: + bytes: [ 0xc0, 0xd0, 0x78, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, RCWMASK_EL1" + + - + input: + bytes: [ 0x00, 0x20, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, TTBR0_EL2" + + - + input: + bytes: [ 0x20, 0x20, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, TTBR1_EL2" + + - + input: + bytes: [ 0x00, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, VTTBR_EL2" + + - + input: + bytes: [ 0x00, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x0, x1, VTTBR_EL2" + + - + input: + bytes: [ 0x02, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x2, x3, VTTBR_EL2" + + - + input: + bytes: [ 0x04, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x4, x5, VTTBR_EL2" + + - + input: + bytes: [ 0x06, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x6, x7, VTTBR_EL2" + + - + input: + bytes: [ 0x08, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x8, x9, VTTBR_EL2" + + - + input: + bytes: [ 0x0a, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x10, x11, VTTBR_EL2" + + - + input: + bytes: [ 0x0c, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x12, x13, VTTBR_EL2" + + - + input: + bytes: [ 0x0e, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x14, x15, VTTBR_EL2" + + - + input: + bytes: [ 0x10, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x16, x17, VTTBR_EL2" + + - + input: + bytes: [ 0x12, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x18, x19, VTTBR_EL2" + + - + input: + bytes: [ 0x14, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x20, x21, VTTBR_EL2" + + - + input: + bytes: [ 0x16, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x22, x23, VTTBR_EL2" + + - + input: + bytes: [ 0x18, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x24, x25, VTTBR_EL2" + + - + input: + bytes: [ 0x1a, 0x21, 0x7c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrrs x26, x27, VTTBR_EL2" + + - + input: + bytes: [ 0x00, 0x20, 0x58, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr TTBR0_EL1, x0, x1" + + - + input: + bytes: [ 0x20, 0x20, 0x58, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr TTBR1_EL1, x0, x1" + + - + input: + bytes: [ 0x00, 0x74, 0x58, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr PAR_EL1, x0, x1" + + - + input: + bytes: [ 0x60, 0xd0, 0x58, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr RCWSMASK_EL1, x0, x1" + + - + input: + bytes: [ 0xc0, 0xd0, 0x58, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr RCWMASK_EL1, x0, x1" + + - + input: + bytes: [ 0x00, 0x20, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr TTBR0_EL2, x0, x1" + + - + input: + bytes: [ 0x20, 0x20, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr TTBR1_EL2, x0, x1" + + - + input: + bytes: [ 0x00, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x0, x1" + + - + input: + bytes: [ 0x00, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x0, x1" + + - + input: + bytes: [ 0x02, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x2, x3" + + - + input: + bytes: [ 0x04, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x4, x5" + + - + input: + bytes: [ 0x06, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x6, x7" + + - + input: + bytes: [ 0x08, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x8, x9" + + - + input: + bytes: [ 0x0a, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x10, x11" + + - + input: + bytes: [ 0x0c, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x12, x13" + + - + input: + bytes: [ 0x0e, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x14, x15" + + - + input: + bytes: [ 0x10, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x16, x17" + + - + input: + bytes: [ 0x12, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x18, x19" + + - + input: + bytes: [ 0x14, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x20, x21" + + - + input: + bytes: [ 0x16, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x22, x23" + + - + input: + bytes: [ 0x18, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x24, x25" + + - + input: + bytes: [ 0x1a, 0x21, 0x5c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msrr VTTBR_EL2, x26, x27" diff --git a/tests/MC/AArch64/armv9.4a-chk.s.yaml b/tests/MC/AArch64/armv9.4a-chk.s.yaml new file mode 100644 index 0000000000..afd02c2cdf --- /dev/null +++ b/tests/MC/AArch64/armv9.4a-chk.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x1f, 0x25, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "chk" ] + expected: + insns: + - + asm_text: "chkfeat x16" + + - + input: + bytes: [ 0x1f, 0x25, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "chk" ] + expected: + insns: + - + asm_text: "chkfeat x16" + + - + input: + bytes: [ 0x1f, 0x25, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ] + expected: + insns: + - + asm_text: "chkfeat x16" + + - + input: + bytes: [ 0x1f, 0x25, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ] + expected: + insns: + - + asm_text: "chkfeat x16" + + - + input: + bytes: [ 0x1f, 0x25, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "chkfeat x16" + + - + input: + bytes: [ 0x1f, 0x25, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ] + expected: + insns: + - + asm_text: "chkfeat x16" + + - + input: + bytes: [ 0x1f, 0x25, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ] + expected: + insns: + - + asm_text: "chkfeat x16" + + - + input: + bytes: [ 0x1f, 0x25, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ] + expected: + insns: + - + asm_text: "chkfeat x16" diff --git a/tests/MC/AArch64/armv9.4a-ebep.s.yaml b/tests/MC/AArch64/armv9.4a-ebep.s.yaml new file mode 100644 index 0000000000..76cba36c68 --- /dev/null +++ b/tests/MC/AArch64/armv9.4a-ebep.s.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0x22, 0x43, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x2, PM" + + - + input: + bytes: [ 0x23, 0x43, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr PM, x3" + + - + input: + bytes: [ 0x1f, 0x43, 0x01, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr PM, #1" diff --git a/tests/MC/AArch64/armv9.4a-gcs.s.yaml b/tests/MC/AArch64/armv9.4a-gcs.s.yaml new file mode 100644 index 0000000000..512306f562 --- /dev/null +++ b/tests/MC/AArch64/armv9.4a-gcs.s.yaml @@ -0,0 +1,350 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x25, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "msr GCSCR_EL1, x0" + + - + input: + bytes: [ 0x01, 0x25, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "mrs x1, GCSCR_EL1" + + - + input: + bytes: [ 0x22, 0x25, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "msr GCSPR_EL1, x2" + + - + input: + bytes: [ 0x23, 0x25, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "mrs x3, GCSPR_EL1" + + - + input: + bytes: [ 0x44, 0x25, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "msr GCSCRE0_EL1, x4" + + - + input: + bytes: [ 0x45, 0x25, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "mrs x5, GCSCRE0_EL1" + + - + input: + bytes: [ 0x26, 0x25, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "msr GCSPR_EL0, x6" + + - + input: + bytes: [ 0x27, 0x25, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "mrs x7, GCSPR_EL0" + + - + input: + bytes: [ 0x0a, 0x25, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "msr GCSCR_EL2, x10" + + - + input: + bytes: [ 0x0b, 0x25, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "mrs x11, GCSCR_EL2" + + - + input: + bytes: [ 0x2c, 0x25, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "msr GCSPR_EL2, x12" + + - + input: + bytes: [ 0x2d, 0x25, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "mrs x13, GCSPR_EL2" + + - + input: + bytes: [ 0x0e, 0x25, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "msr GCSCR_EL12, x14" + + - + input: + bytes: [ 0x0f, 0x25, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "mrs x15, GCSCR_EL12" + + - + input: + bytes: [ 0x30, 0x25, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "msr GCSPR_EL12, x16" + + - + input: + bytes: [ 0x31, 0x25, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "mrs x17, GCSPR_EL12" + + - + input: + bytes: [ 0x12, 0x25, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "msr GCSCR_EL3, x18" + + - + input: + bytes: [ 0x13, 0x25, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "mrs x19, GCSCR_EL3" + + - + input: + bytes: [ 0x34, 0x25, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "msr GCSPR_EL3, x20" + + - + input: + bytes: [ 0x35, 0x25, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "mrs x21, GCSPR_EL3" + + - + input: + bytes: [ 0x55, 0x77, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "gcsss1 x21" + + - + input: + bytes: [ 0x76, 0x77, 0x2b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "gcsss2 x22" + + - + input: + bytes: [ 0x19, 0x77, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "gcspushm x25" + + - + input: + bytes: [ 0x3f, 0x77, 0x2b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "gcspopm" + + - + input: + bytes: [ 0x3f, 0x77, 0x2b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "gcspopm" + + - + input: + bytes: [ 0x39, 0x77, 0x2b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "gcspopm x25" + + - + input: + bytes: [ 0x7f, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "gcsb dsync" + + - + input: + bytes: [ 0x7f, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "gcsb dsync" + + - + input: + bytes: [ 0x7a, 0x0f, 0x1f, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "gcsstr x26, x27" + + - + input: + bytes: [ 0xfa, 0x0f, 0x1f, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "gcsstr x26, sp" + + - + input: + bytes: [ 0x7a, 0x1f, 0x1f, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "gcssttr x26, x27" + + - + input: + bytes: [ 0xfa, 0x1f, 0x1f, 0xd9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "gcssttr x26, sp" + + - + input: + bytes: [ 0x9f, 0x77, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "gcspushx" + + - + input: + bytes: [ 0xbf, 0x77, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "gcspopcx" + + - + input: + bytes: [ 0xdf, 0x77, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ] + expected: + insns: + - + asm_text: "gcspopx" diff --git a/tests/MC/AArch64/armv9.5a-cpa.s.yaml b/tests/MC/AArch64/armv9.5a-cpa.s.yaml new file mode 100644 index 0000000000..4960b6a477 --- /dev/null +++ b/tests/MC/AArch64/armv9.5a-cpa.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x20, 0x02, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ] + expected: + insns: + - + asm_text: "addpt x0, x1, x2" + + - + input: + bytes: [ 0xff, 0x23, 0x02, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ] + expected: + insns: + - + asm_text: "addpt sp, sp, x2" + + - + input: + bytes: [ 0x20, 0x20, 0x02, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ] + expected: + insns: + - + asm_text: "addpt x0, x1, x2" + + - + input: + bytes: [ 0x20, 0x3c, 0x02, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ] + expected: + insns: + - + asm_text: "addpt x0, x1, x2, lsl #7" + + - + input: + bytes: [ 0xff, 0x3f, 0x02, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ] + expected: + insns: + - + asm_text: "addpt sp, sp, x2, lsl #7" + + - + input: + bytes: [ 0x20, 0x20, 0x02, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ] + expected: + insns: + - + asm_text: "subpt x0, x1, x2" + + - + input: + bytes: [ 0xff, 0x23, 0x02, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ] + expected: + insns: + - + asm_text: "subpt sp, sp, x2" + + - + input: + bytes: [ 0x20, 0x20, 0x02, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ] + expected: + insns: + - + asm_text: "subpt x0, x1, x2" + + - + input: + bytes: [ 0x20, 0x3c, 0x02, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ] + expected: + insns: + - + asm_text: "subpt x0, x1, x2, lsl #7" + + - + input: + bytes: [ 0xff, 0x3f, 0x02, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ] + expected: + insns: + - + asm_text: "subpt sp, sp, x2, lsl #7" + + - + input: + bytes: [ 0x20, 0x0c, 0x62, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ] + expected: + insns: + - + asm_text: "maddpt x0, x1, x2, x3" + + - + input: + bytes: [ 0x20, 0x8c, 0x62, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ] + expected: + insns: + - + asm_text: "msubpt x0, x1, x2, x3" diff --git a/tests/MC/AArch64/armv9.5a-e3dse.s.yaml b/tests/MC/AArch64/armv9.5a-e3dse.s.yaml new file mode 100644 index 0000000000..3f0da942aa --- /dev/null +++ b/tests/MC/AArch64/armv9.5a-e3dse.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xc1, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, VDISR_EL3" + + - + input: + bytes: [ 0x20, 0xc1, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr VDISR_EL3, x0" + + - + input: + bytes: [ 0x60, 0x52, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, VSESR_EL3" + + - + input: + bytes: [ 0x60, 0x52, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr VSESR_EL3, x0" diff --git a/tests/MC/AArch64/armv9.5a-fgwte3.s.yaml b/tests/MC/AArch64/armv9.5a-fgwte3.s.yaml new file mode 100644 index 0000000000..f590567d93 --- /dev/null +++ b/tests/MC/AArch64/armv9.5a-fgwte3.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0xa0, 0x11, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, FGWTE3_EL3" + + - + input: + bytes: [ 0xa0, 0x11, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr FGWTE3_EL3, x0" diff --git a/tests/MC/AArch64/armv9.5a-hacdbs.s.yaml b/tests/MC/AArch64/armv9.5a-hacdbs.s.yaml new file mode 100644 index 0000000000..d14d41e546 --- /dev/null +++ b/tests/MC/AArch64/armv9.5a-hacdbs.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x80, 0x23, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, HACDBSBR_EL2" + + - + input: + bytes: [ 0x80, 0x23, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr HACDBSBR_EL2, x0" + + - + input: + bytes: [ 0xa0, 0x23, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, HACDBSCONS_EL2" + + - + input: + bytes: [ 0xa0, 0x23, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr HACDBSCONS_EL2, x0" diff --git a/tests/MC/AArch64/armv9.5a-hdbss.s.yaml b/tests/MC/AArch64/armv9.5a-hdbss.s.yaml new file mode 100644 index 0000000000..f7cc6019f1 --- /dev/null +++ b/tests/MC/AArch64/armv9.5a-hdbss.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x40, 0x23, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, HDBSSBR_EL2" + + - + input: + bytes: [ 0x40, 0x23, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr HDBSSBR_EL2, x0" + + - + input: + bytes: [ 0x60, 0x23, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, HDBSSPROD_EL2" + + - + input: + bytes: [ 0x60, 0x23, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr HDBSSPROD_EL2, x0" diff --git a/tests/MC/AArch64/armv9.5a-pauthlr.s.yaml b/tests/MC/AArch64/armv9.5a-pauthlr.s.yaml new file mode 100644 index 0000000000..0446d20035 --- /dev/null +++ b/tests/MC/AArch64/armv9.5a-pauthlr.s.yaml @@ -0,0 +1,204 @@ +test_cases: + - + input: + bytes: [ 0x1f, 0x20, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0xfe, 0xa3, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "paciasppc" + + - + input: + bytes: [ 0xfe, 0xa7, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "pacibsppc" + + - + input: + bytes: [ 0xfe, 0x83, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "pacnbiasppc" + + - + input: + bytes: [ 0xfe, 0x87, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "pacnbibsppc" + + - + input: + bytes: [ 0x1f, 0x00, 0xa0, 0xf3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "autibsppc #0" + + - + input: + bytes: [ 0xff, 0xff, 0xbf, 0xf3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "autibsppc #-262140" + skip: true + skip_reason: "Capstone does not handle expressions." + + - + input: + bytes: [ 0x1e, 0x90, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "autiasppc x0" + + - + input: + bytes: [ 0x3e, 0x94, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "autibsppc x1" + + - + input: + bytes: [ 0xfe, 0x93, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "autiasppc xzr" + + - + input: + bytes: [ 0xfe, 0x97, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "autibsppc xzr" + + - + input: + bytes: [ 0xfe, 0x8b, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "pacia171615" + + - + input: + bytes: [ 0xfe, 0x8f, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "pacib171615" + + - + input: + bytes: [ 0xfe, 0xbb, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "autia171615" + + - + input: + bytes: [ 0xfe, 0xbf, 0xc1, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "autib171615" + + - + input: + bytes: [ 0x1f, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "retaasppc #0" + + - + input: + bytes: [ 0xff, 0xff, 0x1f, 0x55 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "retaasppc #-262140" + skip: true + skip_reason: "Capstone does not handle expressions." + + - + input: + bytes: [ 0xe2, 0x0b, 0x5f, 0xd6 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "retaasppc x2" + + - + input: + bytes: [ 0xe3, 0x0f, 0x5f, 0xd6 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "retabsppc x3" + + - + input: + bytes: [ 0xff, 0x24, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ] + expected: + insns: + - + asm_text: "pacm" diff --git a/tests/MC/AArch64/armv9.5a-spmu2.s.yaml b/tests/MC/AArch64/armv9.5a-spmu2.s.yaml new file mode 100644 index 0000000000..8c87a881c6 --- /dev/null +++ b/tests/MC/AArch64/armv9.5a-spmu2.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x80, 0x9c, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr SPMZR_EL0, x0" diff --git a/tests/MC/AArch64/armv9.5a-step2.s.yaml b/tests/MC/AArch64/armv9.5a-step2.s.yaml new file mode 100644 index 0000000000..00da2b54a2 --- /dev/null +++ b/tests/MC/AArch64/armv9.5a-step2.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x40, 0x05, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, MDSTEPOP_EL1" + + - + input: + bytes: [ 0x40, 0x05, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr MDSTEPOP_EL1, x0" diff --git a/tests/MC/AArch64/armv9.5a-tlbiw.s.yaml b/tests/MC/AArch64/armv9.5a-tlbiw.s.yaml new file mode 100644 index 0000000000..e3d4525260 --- /dev/null +++ b/tests/MC/AArch64/armv9.5a-tlbiw.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x5f, 0x86, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tlbiw", "xs" ] + expected: + insns: + - + asm_text: "tlbi vmallws2e1" + + - + input: + bytes: [ 0x5f, 0x82, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tlbiw", "xs" ] + expected: + insns: + - + asm_text: "tlbi vmallws2e1is" + + - + input: + bytes: [ 0x5f, 0x85, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tlbiw", "xs" ] + expected: + insns: + - + asm_text: "tlbi vmallws2e1os" + + - + input: + bytes: [ 0x5f, 0x96, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tlbiw", "xs" ] + expected: + insns: + - + asm_text: "tlbi vmallws2e1nxs" + + - + input: + bytes: [ 0x5f, 0x92, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tlbiw", "xs" ] + expected: + insns: + - + asm_text: "tlbi vmallws2e1isnxs" + + - + input: + bytes: [ 0x5f, 0x95, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tlbiw", "xs" ] + expected: + insns: + - + asm_text: "tlbi vmallws2e1osnxs" diff --git a/tests/MC/AArch64/armv9a-mec.s.yaml b/tests/MC/AArch64/armv9a-mec.s.yaml new file mode 100644 index 0000000000..e7a59c10a7 --- /dev/null +++ b/tests/MC/AArch64/armv9a-mec.s.yaml @@ -0,0 +1,340 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0xa8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ] + expected: + insns: + - + asm_text: "mrs x0, MECIDR_EL2" + + - + input: + bytes: [ 0x00, 0xa8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ] + expected: + insns: + - + asm_text: "mrs x0, MECID_P0_EL2" + + - + input: + bytes: [ 0x20, 0xa8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ] + expected: + insns: + - + asm_text: "mrs x0, MECID_A0_EL2" + + - + input: + bytes: [ 0x40, 0xa8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ] + expected: + insns: + - + asm_text: "mrs x0, MECID_P1_EL2" + + - + input: + bytes: [ 0x60, 0xa8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ] + expected: + insns: + - + asm_text: "mrs x0, MECID_A1_EL2" + + - + input: + bytes: [ 0x00, 0xa9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ] + expected: + insns: + - + asm_text: "mrs x0, VMECID_P_EL2" + + - + input: + bytes: [ 0x20, 0xa9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ] + expected: + insns: + - + asm_text: "mrs x0, VMECID_A_EL2" + + - + input: + bytes: [ 0x20, 0xaa, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ] + expected: + insns: + - + asm_text: "mrs x0, MECID_RL_A_EL3" + + - + input: + bytes: [ 0x00, 0xa8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ] + expected: + insns: + - + asm_text: "msr MECID_P0_EL2, x0" + + - + input: + bytes: [ 0x20, 0xa8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ] + expected: + insns: + - + asm_text: "msr MECID_A0_EL2, x0" + + - + input: + bytes: [ 0x40, 0xa8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ] + expected: + insns: + - + asm_text: "msr MECID_P1_EL2, x0" + + - + input: + bytes: [ 0x60, 0xa8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ] + expected: + insns: + - + asm_text: "msr MECID_A1_EL2, x0" + + - + input: + bytes: [ 0x00, 0xa9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ] + expected: + insns: + - + asm_text: "msr VMECID_P_EL2, x0" + + - + input: + bytes: [ 0x20, 0xa9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ] + expected: + insns: + - + asm_text: "msr VMECID_A_EL2, x0" + + - + input: + bytes: [ 0x20, 0xaa, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ] + expected: + insns: + - + asm_text: "msr MECID_RL_A_EL3, x0" + + - + input: + bytes: [ 0xe0, 0x7e, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ] + expected: + insns: + - + asm_text: "dc cigdpae, x0" + + - + input: + bytes: [ 0x00, 0x7e, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ] + expected: + insns: + - + asm_text: "dc cipae, x0" + + - + input: + bytes: [ 0xe0, 0xa8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ] + expected: + insns: + - + asm_text: "mrs x0, MECIDR_EL2" + + - + input: + bytes: [ 0x00, 0xa8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ] + expected: + insns: + - + asm_text: "mrs x0, MECID_P0_EL2" + + - + input: + bytes: [ 0x20, 0xa8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ] + expected: + insns: + - + asm_text: "mrs x0, MECID_A0_EL2" + + - + input: + bytes: [ 0x40, 0xa8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ] + expected: + insns: + - + asm_text: "mrs x0, MECID_P1_EL2" + + - + input: + bytes: [ 0x60, 0xa8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ] + expected: + insns: + - + asm_text: "mrs x0, MECID_A1_EL2" + + - + input: + bytes: [ 0x00, 0xa9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ] + expected: + insns: + - + asm_text: "mrs x0, VMECID_P_EL2" + + - + input: + bytes: [ 0x20, 0xa9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ] + expected: + insns: + - + asm_text: "mrs x0, VMECID_A_EL2" + + - + input: + bytes: [ 0x20, 0xaa, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ] + expected: + insns: + - + asm_text: "mrs x0, MECID_RL_A_EL3" + + - + input: + bytes: [ 0x00, 0xa8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ] + expected: + insns: + - + asm_text: "msr MECID_P0_EL2, x0" + + - + input: + bytes: [ 0x20, 0xa8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ] + expected: + insns: + - + asm_text: "msr MECID_A0_EL2, x0" + + - + input: + bytes: [ 0x40, 0xa8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ] + expected: + insns: + - + asm_text: "msr MECID_P1_EL2, x0" + + - + input: + bytes: [ 0x60, 0xa8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ] + expected: + insns: + - + asm_text: "msr MECID_A1_EL2, x0" + + - + input: + bytes: [ 0x00, 0xa9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ] + expected: + insns: + - + asm_text: "msr VMECID_P_EL2, x0" + + - + input: + bytes: [ 0x20, 0xa9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ] + expected: + insns: + - + asm_text: "msr VMECID_A_EL2, x0" + + - + input: + bytes: [ 0x20, 0xaa, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ] + expected: + insns: + - + asm_text: "msr MECID_RL_A_EL3, x0" + + - + input: + bytes: [ 0xe0, 0x7e, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ] + expected: + insns: + - + asm_text: "dc cigdpae, x0" + + - + input: + bytes: [ 0x00, 0x7e, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ] + expected: + insns: + - + asm_text: "dc cipae, x0" diff --git a/tests/MC/AArch64/basic-a64-instructions.s.yaml b/tests/MC/AArch64/basic-a64-instructions.s.yaml new file mode 100644 index 0000000000..a2893ae2f9 --- /dev/null +++ b/tests/MC/AArch64/basic-a64-instructions.s.yaml @@ -0,0 +1,20904 @@ +test_cases: + - + input: + bytes: [ 0x82, 0x00, 0x25, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x2, x4, w5, uxtb" + + - + input: + bytes: [ 0xf4, 0x23, 0x33, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x20, sp, w19, uxth" + + - + input: + bytes: [ 0x2c, 0x40, 0x34, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x12, x1, w20, uxtw" + + - + input: + bytes: [ 0x74, 0x60, 0x2d, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x20, x3, x13, uxtx" + + - + input: + bytes: [ 0x31, 0x83, 0x34, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x17, x25, w20, sxtb" + + - + input: + bytes: [ 0xb2, 0xa1, 0x33, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x18, x13, w19, sxth" + + - + input: + bytes: [ 0x5f, 0xc0, 0x23, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add sp, x2, w3, sxtw" + + - + input: + bytes: [ 0xa3, 0xe0, 0x29, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x3, x5, x9, sxtx" + + - + input: + bytes: [ 0xa2, 0x00, 0x27, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w2, w5, w7, uxtb" + + - + input: + bytes: [ 0xf5, 0x21, 0x31, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w21, w15, w17, uxth" + + - + input: + bytes: [ 0xbe, 0x43, 0x3f, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w30, w29, wzr, uxtw" + + - + input: + bytes: [ 0x33, 0x62, 0x21, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w19, w17, w1, uxtx" + + - + input: + bytes: [ 0xa2, 0x80, 0x21, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w2, w5, w1, sxtb" + + - + input: + bytes: [ 0x3a, 0xa2, 0x33, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w26, w17, w19, sxth" + + - + input: + bytes: [ 0x40, 0xc0, 0x23, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w0, w2, w3, sxtw" + + - + input: + bytes: [ 0x62, 0xe0, 0x25, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w2, w3, w5, sxtx" + + - + input: + bytes: [ 0x62, 0x80, 0x25, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x2, x3, w5, sxtb" + + - + input: + bytes: [ 0x67, 0x31, 0x2d, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x7, x11, w13, uxth #4" + + - + input: + bytes: [ 0x71, 0x4a, 0x37, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w17, w19, w23, uxtw #2" + + - + input: + bytes: [ 0xfd, 0x66, 0x31, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w29, w23, w17, uxtx #1" + + - + input: + bytes: [ 0x82, 0x08, 0x25, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub x2, x4, w5, uxtb #2" + + - + input: + bytes: [ 0xf4, 0x33, 0x33, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub x20, sp, w19, uxth #4" + + - + input: + bytes: [ 0x2c, 0x40, 0x34, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub x12, x1, w20, uxtw" + + - + input: + bytes: [ 0x74, 0x60, 0x2d, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub x20, x3, x13, uxtx" + + - + input: + bytes: [ 0x31, 0x83, 0x34, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub x17, x25, w20, sxtb" + + - + input: + bytes: [ 0xb2, 0xa1, 0x33, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub x18, x13, w19, sxth" + + - + input: + bytes: [ 0x5f, 0xc0, 0x23, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub sp, x2, w3, sxtw" + + - + input: + bytes: [ 0xa3, 0xe0, 0x29, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub x3, x5, x9, sxtx" + + - + input: + bytes: [ 0xa2, 0x00, 0x27, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w2, w5, w7, uxtb" + + - + input: + bytes: [ 0xf5, 0x21, 0x31, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w21, w15, w17, uxth" + + - + input: + bytes: [ 0xbe, 0x43, 0x3f, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w30, w29, wzr, uxtw" + + - + input: + bytes: [ 0x33, 0x62, 0x21, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w19, w17, w1, uxtx" + + - + input: + bytes: [ 0xa2, 0x80, 0x21, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w2, w5, w1, sxtb" + + - + input: + bytes: [ 0xfa, 0xa3, 0x33, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w26, wsp, w19, sxth" + + - + input: + bytes: [ 0x5f, 0xc0, 0x23, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub wsp, w2, w3, sxtw" + + - + input: + bytes: [ 0x62, 0xe0, 0x25, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w2, w3, w5, sxtx" + + - + input: + bytes: [ 0x82, 0x08, 0x25, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds x2, x4, w5, uxtb #2" + + - + input: + bytes: [ 0xf4, 0x33, 0x33, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds x20, sp, w19, uxth #4" + + - + input: + bytes: [ 0x2c, 0x40, 0x34, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds x12, x1, w20, uxtw" + + - + input: + bytes: [ 0x74, 0x60, 0x2d, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds x20, x3, x13, uxtx" + + - + input: + bytes: [ 0x3f, 0x8f, 0x34, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x25, w20, sxtb #3" + + - + input: + bytes: [ 0xf2, 0xa3, 0x33, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds x18, sp, w19, sxth" + + - + input: + bytes: [ 0x5f, 0xc0, 0x23, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x2, w3, sxtw" + + - + input: + bytes: [ 0xa3, 0xe8, 0x29, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds x3, x5, x9, sxtx #2" + + - + input: + bytes: [ 0xa2, 0x00, 0x27, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w2, w5, w7, uxtb" + + - + input: + bytes: [ 0xf5, 0x21, 0x31, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w21, w15, w17, uxth" + + - + input: + bytes: [ 0xbe, 0x43, 0x3f, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w30, w29, wzr, uxtw" + + - + input: + bytes: [ 0x33, 0x62, 0x21, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w19, w17, w1, uxtx" + + - + input: + bytes: [ 0xa2, 0x84, 0x21, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w2, w5, w1, sxtb #1" + + - + input: + bytes: [ 0xfa, 0xa3, 0x33, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w26, wsp, w19, sxth" + + - + input: + bytes: [ 0x5f, 0xc0, 0x23, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w2, w3, sxtw" + + - + input: + bytes: [ 0x62, 0xe0, 0x25, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w2, w3, w5, sxtx" + + - + input: + bytes: [ 0x82, 0x08, 0x25, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs x2, x4, w5, uxtb #2" + + - + input: + bytes: [ 0xf4, 0x33, 0x33, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs x20, sp, w19, uxth #4" + + - + input: + bytes: [ 0x2c, 0x40, 0x34, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs x12, x1, w20, uxtw" + + - + input: + bytes: [ 0x74, 0x60, 0x2d, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs x20, x3, x13, uxtx" + + - + input: + bytes: [ 0x3f, 0x8f, 0x34, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x25, w20, sxtb #3" + + - + input: + bytes: [ 0xf2, 0xa3, 0x33, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs x18, sp, w19, sxth" + + - + input: + bytes: [ 0x5f, 0xc0, 0x23, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x2, w3, sxtw" + + - + input: + bytes: [ 0xa3, 0xe8, 0x29, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs x3, x5, x9, sxtx #2" + + - + input: + bytes: [ 0xa2, 0x00, 0x27, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs w2, w5, w7, uxtb" + + - + input: + bytes: [ 0xf5, 0x21, 0x31, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs w21, w15, w17, uxth" + + - + input: + bytes: [ 0xbe, 0x43, 0x3f, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs w30, w29, wzr, uxtw" + + - + input: + bytes: [ 0x33, 0x62, 0x21, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs w19, w17, w1, uxtx" + + - + input: + bytes: [ 0xa2, 0x84, 0x21, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs w2, w5, w1, sxtb #1" + + - + input: + bytes: [ 0xfa, 0xa3, 0x33, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs w26, wsp, w19, sxth" + + - + input: + bytes: [ 0x5f, 0xc0, 0x23, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w2, w3, sxtw" + + - + input: + bytes: [ 0x62, 0xe0, 0x25, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs w2, w3, w5, sxtx" + + - + input: + bytes: [ 0x9f, 0x08, 0x25, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x4, w5, uxtb #2" + + - + input: + bytes: [ 0xff, 0x33, 0x33, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp sp, w19, uxth #4" + + - + input: + bytes: [ 0x3f, 0x40, 0x34, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x1, w20, uxtw" + + - + input: + bytes: [ 0x7f, 0x60, 0x2d, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x3, x13, uxtx" + + - + input: + bytes: [ 0x3f, 0x8f, 0x34, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x25, w20, sxtb #3" + + - + input: + bytes: [ 0xff, 0xa3, 0x33, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp sp, w19, sxth" + + - + input: + bytes: [ 0x5f, 0xc0, 0x23, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x2, w3, sxtw" + + - + input: + bytes: [ 0xbf, 0xe8, 0x29, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x5, x9, sxtx #2" + + - + input: + bytes: [ 0xbf, 0x00, 0x27, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w5, w7, uxtb" + + - + input: + bytes: [ 0xff, 0x21, 0x31, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w15, w17, uxth" + + - + input: + bytes: [ 0xbf, 0x43, 0x3f, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w29, wzr, uxtw" + + - + input: + bytes: [ 0x3f, 0x62, 0x21, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w17, w1, uxtx" + + - + input: + bytes: [ 0xbf, 0x84, 0x21, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w5, w1, sxtb #1" + + - + input: + bytes: [ 0xff, 0xa3, 0x33, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp wsp, w19, sxth" + + - + input: + bytes: [ 0x5f, 0xc0, 0x23, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w2, w3, sxtw" + + - + input: + bytes: [ 0x7f, 0xe0, 0x25, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w3, w5, sxtx" + + - + input: + bytes: [ 0x9f, 0x08, 0x25, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x4, w5, uxtb #2" + + - + input: + bytes: [ 0xff, 0x33, 0x33, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn sp, w19, uxth #4" + + - + input: + bytes: [ 0x3f, 0x40, 0x34, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x1, w20, uxtw" + + - + input: + bytes: [ 0x7f, 0x60, 0x2d, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x3, x13, uxtx" + + - + input: + bytes: [ 0x3f, 0x8f, 0x34, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x25, w20, sxtb #3" + + - + input: + bytes: [ 0xff, 0xa3, 0x33, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn sp, w19, sxth" + + - + input: + bytes: [ 0x5f, 0xc0, 0x23, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x2, w3, sxtw" + + - + input: + bytes: [ 0xbf, 0xe8, 0x29, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x5, x9, sxtx #2" + + - + input: + bytes: [ 0xbf, 0x00, 0x27, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w5, w7, uxtb" + + - + input: + bytes: [ 0xff, 0x21, 0x31, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w15, w17, uxth" + + - + input: + bytes: [ 0xbf, 0x43, 0x3f, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w29, wzr, uxtw" + + - + input: + bytes: [ 0x3f, 0x62, 0x21, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w17, w1, uxtx" + + - + input: + bytes: [ 0xbf, 0x84, 0x21, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w5, w1, sxtb #1" + + - + input: + bytes: [ 0xff, 0xa3, 0x33, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn wsp, w19, sxth" + + - + input: + bytes: [ 0x5f, 0xc0, 0x23, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w2, w3, sxtw" + + - + input: + bytes: [ 0x7f, 0xe0, 0x25, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w3, w5, sxtx" + + - + input: + bytes: [ 0x9f, 0x0e, 0x3d, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x20, w29, uxtb #3" + + - + input: + bytes: [ 0x9f, 0x71, 0x2d, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x12, x13, uxtx #4" + + - + input: + bytes: [ 0xff, 0x03, 0x21, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp wsp, w1, uxtb" + + - + input: + bytes: [ 0xff, 0xc3, 0x3f, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn wsp, wzr, sxtw" + + - + input: + bytes: [ 0x7f, 0x70, 0x27, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub sp, x3, x7, lsl #4" + + - + input: + bytes: [ 0xe2, 0x47, 0x23, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w2, wsp, w3, lsl #1" + + - + input: + bytes: [ 0xff, 0x43, 0x29, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp wsp, w9" + + - + input: + bytes: [ 0xff, 0x53, 0x23, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn wsp, w3, lsl #4" + + - + input: + bytes: [ 0xe3, 0x6b, 0x29, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs x3, sp, x9, lsl #2" + + - + input: + bytes: [ 0xa4, 0x00, 0x00, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w4, w5, #0" + + - + input: + bytes: [ 0x62, 0xfc, 0x3f, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w2, w3, #4095" + + - + input: + bytes: [ 0xbe, 0x07, 0x40, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w30, w29, #1, lsl #12" + + - + input: + bytes: [ 0xad, 0xfc, 0x7f, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w13, w5, #4095, lsl #12" + + - + input: + bytes: [ 0xe5, 0x98, 0x19, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x5, x7, #1638" + + - + input: + bytes: [ 0xf4, 0x87, 0x0c, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w20, wsp, #801" + + - + input: + bytes: [ 0xff, 0x43, 0x11, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add wsp, wsp, #1104" + + - + input: + bytes: [ 0xdf, 0xd3, 0x3f, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add wsp, w30, #4084" + + - + input: + bytes: [ 0x00, 0x8f, 0x04, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x0, x24, #291" + + - + input: + bytes: [ 0x03, 0xff, 0x7f, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x3, x24, #4095, lsl #12" + + - + input: + bytes: [ 0xe8, 0xcb, 0x10, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x8, sp, #1074" + + - + input: + bytes: [ 0xbf, 0xa3, 0x3b, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add sp, x29, #3816" + + - + input: + bytes: [ 0xe0, 0xb7, 0x3f, 0x51 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w0, wsp, #4077" + + - + input: + bytes: [ 0x84, 0x8a, 0x48, 0x51 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w4, w20, #546, lsl #12" + + - + input: + bytes: [ 0xff, 0x83, 0x04, 0xd1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub sp, sp, #288" + + - + input: + bytes: [ 0x7f, 0x42, 0x00, 0x51 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub wsp, w19, #16" + + - + input: + bytes: [ 0xed, 0x8e, 0x44, 0x31 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w13, w23, #291, lsl #12" + + - + input: + bytes: [ 0x5f, 0xfc, 0x3f, 0x31 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w2, #4095" + + - + input: + bytes: [ 0xf4, 0x03, 0x00, 0x31 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w20, wsp, #0" + + - + input: + bytes: [ 0x7f, 0x04, 0x40, 0xb1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x3, #1, lsl #12" + + - + input: + bytes: [ 0xff, 0x53, 0x40, 0xf1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp sp, #20, lsl #12" + + - + input: + bytes: [ 0xdf, 0xff, 0x3f, 0xf1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x30, #4095" + + - + input: + bytes: [ 0xe4, 0xbb, 0x3b, 0xf1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs x4, sp, #3822" + + - + input: + bytes: [ 0x7f, 0x8c, 0x44, 0x31 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w3, #291, lsl #12" + + - + input: + bytes: [ 0xff, 0x57, 0x15, 0x31 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn wsp, #1365" + + - + input: + bytes: [ 0xff, 0x13, 0x51, 0xb1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn sp, #1092, lsl #12" + + - + input: + bytes: [ 0x9f, 0xb0, 0x44, 0xf1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x4, #300, lsl #12" + + - + input: + bytes: [ 0xff, 0xd3, 0x07, 0x71 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp wsp, #500" + + - + input: + bytes: [ 0xff, 0x23, 0x03, 0xf1 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp sp, #200" + + - + input: + bytes: [ 0xdf, 0x03, 0x00, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mov sp, x30" + + - + input: + bytes: [ 0x9f, 0x02, 0x00, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mov wsp, w20" + + - + input: + bytes: [ 0xeb, 0x03, 0x00, 0x91 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mov x11, sp" + + - + input: + bytes: [ 0xf8, 0x03, 0x00, 0x11 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mov w24, wsp" + + - + input: + bytes: [ 0xa3, 0x00, 0x07, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w3, w5, w7" + + - + input: + bytes: [ 0x7f, 0x00, 0x05, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add wzr, w3, w5" + + - + input: + bytes: [ 0xf4, 0x03, 0x04, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w20, wzr, w4" + + - + input: + bytes: [ 0xc4, 0x00, 0x1f, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w4, w6, wzr" + + - + input: + bytes: [ 0xab, 0x01, 0x0f, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w11, w13, w15" + + - + input: + bytes: [ 0x69, 0x28, 0x1f, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w9, w3, wzr, lsl #10" + + - + input: + bytes: [ 0xb1, 0x7f, 0x14, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w17, w29, w20, lsl #31" + + - + input: + bytes: [ 0xb1, 0x77, 0x14, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w17, w29, w20, lsl #29" + + - + input: + bytes: [ 0xd5, 0x02, 0x57, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w21, w22, w23, lsr #0" + + - + input: + bytes: [ 0x38, 0x4b, 0x5a, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w24, w25, w26, lsr #18" + + - + input: + bytes: [ 0x9b, 0x7f, 0x5d, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w27, w28, w29, lsr #31" + + - + input: + bytes: [ 0x9b, 0x77, 0x5d, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w27, w28, w29, lsr #29" + + - + input: + bytes: [ 0x62, 0x00, 0x84, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w2, w3, w4, asr #0" + + - + input: + bytes: [ 0xc5, 0x54, 0x87, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w5, w6, w7, asr #21" + + - + input: + bytes: [ 0x28, 0x7d, 0x8a, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w8, w9, w10, asr #31" + + - + input: + bytes: [ 0x28, 0x75, 0x8a, 0x0b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add w8, w9, w10, asr #29" + + - + input: + bytes: [ 0xa3, 0x00, 0x07, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x3, x5, x7" + + - + input: + bytes: [ 0x7f, 0x00, 0x05, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add xzr, x3, x5" + + - + input: + bytes: [ 0xf4, 0x03, 0x04, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x20, xzr, x4" + + - + input: + bytes: [ 0xc4, 0x00, 0x1f, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x4, x6, xzr" + + - + input: + bytes: [ 0xab, 0x01, 0x0f, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x11, x13, x15" + + - + input: + bytes: [ 0x69, 0x28, 0x1f, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x9, x3, xzr, lsl #10" + + - + input: + bytes: [ 0xb1, 0xff, 0x14, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x17, x29, x20, lsl #63" + + - + input: + bytes: [ 0xb1, 0xeb, 0x14, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x17, x29, x20, lsl #58" + + - + input: + bytes: [ 0xd5, 0x02, 0x57, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x21, x22, x23, lsr #0" + + - + input: + bytes: [ 0x38, 0x4b, 0x5a, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x24, x25, x26, lsr #18" + + - + input: + bytes: [ 0x9b, 0xff, 0x5d, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x27, x28, x29, lsr #63" + + - + input: + bytes: [ 0xb1, 0xeb, 0x54, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x17, x29, x20, lsr #58" + + - + input: + bytes: [ 0x62, 0x00, 0x84, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x2, x3, x4, asr #0" + + - + input: + bytes: [ 0xc5, 0x54, 0x87, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x5, x6, x7, asr #21" + + - + input: + bytes: [ 0x28, 0xfd, 0x8a, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x8, x9, x10, asr #63" + + - + input: + bytes: [ 0xb1, 0xeb, 0x94, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "add x17, x29, x20, asr #58" + + - + input: + bytes: [ 0xa3, 0x00, 0x07, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w3, w5, w7" + + - + input: + bytes: [ 0x7f, 0x00, 0x05, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w3, w5" + + - + input: + bytes: [ 0xf4, 0x03, 0x04, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w20, wzr, w4" + + - + input: + bytes: [ 0xc4, 0x00, 0x1f, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w4, w6, wzr" + + - + input: + bytes: [ 0xab, 0x01, 0x0f, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w11, w13, w15" + + - + input: + bytes: [ 0x69, 0x28, 0x1f, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w9, w3, wzr, lsl #10" + + - + input: + bytes: [ 0xb1, 0x7f, 0x14, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w17, w29, w20, lsl #31" + + - + input: + bytes: [ 0xd5, 0x02, 0x57, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w21, w22, w23, lsr #0" + + - + input: + bytes: [ 0x38, 0x4b, 0x5a, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w24, w25, w26, lsr #18" + + - + input: + bytes: [ 0x9b, 0x7f, 0x5d, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w27, w28, w29, lsr #31" + + - + input: + bytes: [ 0x62, 0x00, 0x84, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w2, w3, w4, asr #0" + + - + input: + bytes: [ 0xc5, 0x54, 0x87, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w5, w6, w7, asr #21" + + - + input: + bytes: [ 0x28, 0x7d, 0x8a, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds w8, w9, w10, asr #31" + + - + input: + bytes: [ 0xa3, 0x00, 0x07, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds x3, x5, x7" + + - + input: + bytes: [ 0x7f, 0x00, 0x05, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x3, x5" + + - + input: + bytes: [ 0xf4, 0x03, 0x04, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds x20, xzr, x4" + + - + input: + bytes: [ 0xc4, 0x00, 0x1f, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds x4, x6, xzr" + + - + input: + bytes: [ 0xab, 0x01, 0x0f, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds x11, x13, x15" + + - + input: + bytes: [ 0x69, 0x28, 0x1f, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds x9, x3, xzr, lsl #10" + + - + input: + bytes: [ 0xb1, 0xff, 0x14, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds x17, x29, x20, lsl #63" + + - + input: + bytes: [ 0xd5, 0x02, 0x57, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds x21, x22, x23, lsr #0" + + - + input: + bytes: [ 0x38, 0x4b, 0x5a, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds x24, x25, x26, lsr #18" + + - + input: + bytes: [ 0x9b, 0xff, 0x5d, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds x27, x28, x29, lsr #63" + + - + input: + bytes: [ 0x62, 0x00, 0x84, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds x2, x3, x4, asr #0" + + - + input: + bytes: [ 0xc5, 0x54, 0x87, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds x5, x6, x7, asr #21" + + - + input: + bytes: [ 0x28, 0xfd, 0x8a, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adds x8, x9, x10, asr #63" + + - + input: + bytes: [ 0xa3, 0x00, 0x07, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w3, w5, w7" + + - + input: + bytes: [ 0x7f, 0x00, 0x05, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub wzr, w3, w5" + + - + input: + bytes: [ 0xf4, 0x03, 0x04, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg w20, w4" + + - + input: + bytes: [ 0xc4, 0x00, 0x1f, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w4, w6, wzr" + + - + input: + bytes: [ 0xab, 0x01, 0x0f, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w11, w13, w15" + + - + input: + bytes: [ 0x69, 0x28, 0x1f, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w9, w3, wzr, lsl #10" + + - + input: + bytes: [ 0xb1, 0x7f, 0x14, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w17, w29, w20, lsl #31" + + - + input: + bytes: [ 0xd5, 0x02, 0x57, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w21, w22, w23, lsr #0" + + - + input: + bytes: [ 0x38, 0x4b, 0x5a, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w24, w25, w26, lsr #18" + + - + input: + bytes: [ 0x9b, 0x7f, 0x5d, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w27, w28, w29, lsr #31" + + - + input: + bytes: [ 0x62, 0x00, 0x84, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w2, w3, w4, asr #0" + + - + input: + bytes: [ 0xc5, 0x54, 0x87, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w5, w6, w7, asr #21" + + - + input: + bytes: [ 0x28, 0x7d, 0x8a, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub w8, w9, w10, asr #31" + + - + input: + bytes: [ 0xa3, 0x00, 0x07, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub x3, x5, x7" + + - + input: + bytes: [ 0x7f, 0x00, 0x05, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub xzr, x3, x5" + + - + input: + bytes: [ 0xf4, 0x03, 0x04, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg x20, x4" + + - + input: + bytes: [ 0xc4, 0x00, 0x1f, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub x4, x6, xzr" + + - + input: + bytes: [ 0xab, 0x01, 0x0f, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub x11, x13, x15" + + - + input: + bytes: [ 0x69, 0x28, 0x1f, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub x9, x3, xzr, lsl #10" + + - + input: + bytes: [ 0xb1, 0xff, 0x14, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub x17, x29, x20, lsl #63" + + - + input: + bytes: [ 0xd5, 0x02, 0x57, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub x21, x22, x23, lsr #0" + + - + input: + bytes: [ 0x38, 0x4b, 0x5a, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub x24, x25, x26, lsr #18" + + - + input: + bytes: [ 0x9b, 0xff, 0x5d, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub x27, x28, x29, lsr #63" + + - + input: + bytes: [ 0x62, 0x00, 0x84, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub x2, x3, x4, asr #0" + + - + input: + bytes: [ 0xc5, 0x54, 0x87, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub x5, x6, x7, asr #21" + + - + input: + bytes: [ 0x28, 0xfd, 0x8a, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sub x8, x9, x10, asr #63" + + - + input: + bytes: [ 0xa3, 0x00, 0x07, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs w3, w5, w7" + + - + input: + bytes: [ 0x7f, 0x00, 0x05, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w3, w5" + + - + input: + bytes: [ 0xf4, 0x03, 0x04, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs w20, w4" + + - + input: + bytes: [ 0xc4, 0x00, 0x1f, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs w4, w6, wzr" + + - + input: + bytes: [ 0xab, 0x01, 0x0f, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs w11, w13, w15" + + - + input: + bytes: [ 0x69, 0x28, 0x1f, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs w9, w3, wzr, lsl #10" + + - + input: + bytes: [ 0xb1, 0x7f, 0x14, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs w17, w29, w20, lsl #31" + + - + input: + bytes: [ 0xd5, 0x02, 0x57, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs w21, w22, w23, lsr #0" + + - + input: + bytes: [ 0x38, 0x4b, 0x5a, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs w24, w25, w26, lsr #18" + + - + input: + bytes: [ 0x9b, 0x7f, 0x5d, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs w27, w28, w29, lsr #31" + + - + input: + bytes: [ 0x62, 0x00, 0x84, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs w2, w3, w4, asr #0" + + - + input: + bytes: [ 0xc5, 0x54, 0x87, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs w5, w6, w7, asr #21" + + - + input: + bytes: [ 0x28, 0x7d, 0x8a, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs w8, w9, w10, asr #31" + + - + input: + bytes: [ 0xa3, 0x00, 0x07, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs x3, x5, x7" + + - + input: + bytes: [ 0x7f, 0x00, 0x05, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x3, x5" + + - + input: + bytes: [ 0xf4, 0x03, 0x04, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs x20, x4" + + - + input: + bytes: [ 0xc4, 0x00, 0x1f, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs x4, x6, xzr" + + - + input: + bytes: [ 0xab, 0x01, 0x0f, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs x11, x13, x15" + + - + input: + bytes: [ 0x69, 0x28, 0x1f, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs x9, x3, xzr, lsl #10" + + - + input: + bytes: [ 0xb1, 0xff, 0x14, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs x17, x29, x20, lsl #63" + + - + input: + bytes: [ 0xd5, 0x02, 0x57, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs x21, x22, x23, lsr #0" + + - + input: + bytes: [ 0x38, 0x4b, 0x5a, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs x24, x25, x26, lsr #18" + + - + input: + bytes: [ 0x9b, 0xff, 0x5d, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs x27, x28, x29, lsr #63" + + - + input: + bytes: [ 0x62, 0x00, 0x84, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs x2, x3, x4, asr #0" + + - + input: + bytes: [ 0xc5, 0x54, 0x87, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs x5, x6, x7, asr #21" + + - + input: + bytes: [ 0x28, 0xfd, 0x8a, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "subs x8, x9, x10, asr #63" + + - + input: + bytes: [ 0x1f, 0x00, 0x03, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w0, w3" + + - + input: + bytes: [ 0xff, 0x03, 0x04, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn wzr, w4" + + - + input: + bytes: [ 0xbf, 0x00, 0x1f, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w5, wzr" + + - + input: + bytes: [ 0xff, 0x43, 0x26, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn wsp, w6" + + - + input: + bytes: [ 0xdf, 0x00, 0x07, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w6, w7" + + - + input: + bytes: [ 0x1f, 0x3d, 0x09, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w8, w9, lsl #15" + + - + input: + bytes: [ 0x5f, 0x7d, 0x0b, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w10, w11, lsl #31" + + - + input: + bytes: [ 0x9f, 0x01, 0x4d, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w12, w13, lsr #0" + + - + input: + bytes: [ 0xdf, 0x55, 0x4f, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w14, w15, lsr #21" + + - + input: + bytes: [ 0x1f, 0x7e, 0x51, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w16, w17, lsr #31" + + - + input: + bytes: [ 0x5f, 0x02, 0x93, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w18, w19, asr #0" + + - + input: + bytes: [ 0x9f, 0x5a, 0x95, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w20, w21, asr #22" + + - + input: + bytes: [ 0xdf, 0x7e, 0x97, 0x2b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn w22, w23, asr #31" + + - + input: + bytes: [ 0x1f, 0x00, 0x03, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x0, x3" + + - + input: + bytes: [ 0xff, 0x03, 0x04, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn xzr, x4" + + - + input: + bytes: [ 0xbf, 0x00, 0x1f, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x5, xzr" + + - + input: + bytes: [ 0xff, 0x63, 0x26, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn sp, x6" + + - + input: + bytes: [ 0xdf, 0x00, 0x07, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x6, x7" + + - + input: + bytes: [ 0x1f, 0x3d, 0x09, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x8, x9, lsl #15" + + - + input: + bytes: [ 0x5f, 0xfd, 0x0b, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x10, x11, lsl #63" + + - + input: + bytes: [ 0x9f, 0x01, 0x4d, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x12, x13, lsr #0" + + - + input: + bytes: [ 0xdf, 0xa5, 0x4f, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x14, x15, lsr #41" + + - + input: + bytes: [ 0x1f, 0xfe, 0x51, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x16, x17, lsr #63" + + - + input: + bytes: [ 0x5f, 0x02, 0x93, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x18, x19, asr #0" + + - + input: + bytes: [ 0x9f, 0xde, 0x95, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x20, x21, asr #55" + + - + input: + bytes: [ 0xdf, 0xfe, 0x97, 0xab ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmn x22, x23, asr #63" + + - + input: + bytes: [ 0x1f, 0x00, 0x03, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w0, w3" + + - + input: + bytes: [ 0xff, 0x03, 0x04, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp wzr, w4" + + - + input: + bytes: [ 0xbf, 0x00, 0x1f, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w5, wzr" + + - + input: + bytes: [ 0xff, 0x43, 0x26, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp wsp, w6" + + - + input: + bytes: [ 0xdf, 0x00, 0x07, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w6, w7" + + - + input: + bytes: [ 0x1f, 0x3d, 0x09, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w8, w9, lsl #15" + + - + input: + bytes: [ 0x5f, 0x7d, 0x0b, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w10, w11, lsl #31" + + - + input: + bytes: [ 0x9f, 0x01, 0x4d, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w12, w13, lsr #0" + + - + input: + bytes: [ 0xdf, 0x55, 0x4f, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w14, w15, lsr #21" + + - + input: + bytes: [ 0x1f, 0x7e, 0x51, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w16, w17, lsr #31" + + - + input: + bytes: [ 0x5f, 0x02, 0x93, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w18, w19, asr #0" + + - + input: + bytes: [ 0x9f, 0x5a, 0x95, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w20, w21, asr #22" + + - + input: + bytes: [ 0xdf, 0x7e, 0x97, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp w22, w23, asr #31" + + - + input: + bytes: [ 0x1f, 0x00, 0x03, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x0, x3" + + - + input: + bytes: [ 0xff, 0x03, 0x04, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp xzr, x4" + + - + input: + bytes: [ 0xbf, 0x00, 0x1f, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x5, xzr" + + - + input: + bytes: [ 0xff, 0x63, 0x26, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp sp, x6" + + - + input: + bytes: [ 0xdf, 0x00, 0x07, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x6, x7" + + - + input: + bytes: [ 0x1f, 0x3d, 0x09, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x8, x9, lsl #15" + + - + input: + bytes: [ 0x5f, 0xfd, 0x0b, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x10, x11, lsl #63" + + - + input: + bytes: [ 0x9f, 0x01, 0x4d, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x12, x13, lsr #0" + + - + input: + bytes: [ 0xdf, 0xa5, 0x4f, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x14, x15, lsr #41" + + - + input: + bytes: [ 0x1f, 0xfe, 0x51, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x16, x17, lsr #63" + + - + input: + bytes: [ 0x5f, 0x02, 0x93, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x18, x19, asr #0" + + - + input: + bytes: [ 0x9f, 0xde, 0x95, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x20, x21, asr #55" + + - + input: + bytes: [ 0xdf, 0xfe, 0x97, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp x22, x23, asr #63" + + - + input: + bytes: [ 0xfd, 0x03, 0x1e, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg w29, w30" + + - + input: + bytes: [ 0xfe, 0x03, 0x1f, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg w30, wzr" + + - + input: + bytes: [ 0xff, 0x03, 0x00, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg wzr, w0" + + - + input: + bytes: [ 0xfc, 0x03, 0x1b, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg w28, w27" + + - + input: + bytes: [ 0xfa, 0x77, 0x19, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg w26, w25, lsl #29" + + - + input: + bytes: [ 0xf8, 0x7f, 0x17, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg w24, w23, lsl #31" + + - + input: + bytes: [ 0xf6, 0x03, 0x55, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg w22, w21, lsr #0" + + - + input: + bytes: [ 0xf4, 0x07, 0x53, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg w20, w19, lsr #1" + + - + input: + bytes: [ 0xf2, 0x7f, 0x51, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg w18, w17, lsr #31" + + - + input: + bytes: [ 0xf0, 0x03, 0x8f, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg w16, w15, asr #0" + + - + input: + bytes: [ 0xee, 0x33, 0x8d, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg w14, w13, asr #12" + + - + input: + bytes: [ 0xec, 0x7f, 0x8b, 0x4b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg w12, w11, asr #31" + + - + input: + bytes: [ 0xfd, 0x03, 0x1e, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg x29, x30" + + - + input: + bytes: [ 0xfe, 0x03, 0x1f, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg x30, xzr" + + - + input: + bytes: [ 0xff, 0x03, 0x00, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg xzr, x0" + + - + input: + bytes: [ 0xfc, 0x03, 0x1b, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg x28, x27" + + - + input: + bytes: [ 0xfa, 0x77, 0x19, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg x26, x25, lsl #29" + + - + input: + bytes: [ 0xf8, 0x7f, 0x17, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg x24, x23, lsl #31" + + - + input: + bytes: [ 0xf6, 0x03, 0x55, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg x22, x21, lsr #0" + + - + input: + bytes: [ 0xf4, 0x07, 0x53, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg x20, x19, lsr #1" + + - + input: + bytes: [ 0xf2, 0x7f, 0x51, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg x18, x17, lsr #31" + + - + input: + bytes: [ 0xf0, 0x03, 0x8f, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg x16, x15, asr #0" + + - + input: + bytes: [ 0xee, 0x33, 0x8d, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg x14, x13, asr #12" + + - + input: + bytes: [ 0xec, 0x7f, 0x8b, 0xcb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "neg x12, x11, asr #31" + + - + input: + bytes: [ 0xfd, 0x03, 0x1e, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs w29, w30" + + - + input: + bytes: [ 0xfe, 0x03, 0x1f, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs w30, wzr" + + - + input: + bytes: [ 0xff, 0x03, 0x00, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp wzr, w0" + + - + input: + bytes: [ 0xfc, 0x03, 0x1b, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs w28, w27" + + - + input: + bytes: [ 0xfa, 0x77, 0x19, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs w26, w25, lsl #29" + + - + input: + bytes: [ 0xf8, 0x7f, 0x17, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs w24, w23, lsl #31" + + - + input: + bytes: [ 0xf6, 0x03, 0x55, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs w22, w21, lsr #0" + + - + input: + bytes: [ 0xf4, 0x07, 0x53, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs w20, w19, lsr #1" + + - + input: + bytes: [ 0xf2, 0x7f, 0x51, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs w18, w17, lsr #31" + + - + input: + bytes: [ 0xf0, 0x03, 0x8f, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs w16, w15, asr #0" + + - + input: + bytes: [ 0xee, 0x33, 0x8d, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs w14, w13, asr #12" + + - + input: + bytes: [ 0xec, 0x7f, 0x8b, 0x6b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs w12, w11, asr #31" + + - + input: + bytes: [ 0xfd, 0x03, 0x1e, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs x29, x30" + + - + input: + bytes: [ 0xfe, 0x03, 0x1f, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs x30, xzr" + + - + input: + bytes: [ 0xff, 0x03, 0x00, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cmp xzr, x0" + + - + input: + bytes: [ 0xfc, 0x03, 0x1b, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs x28, x27" + + - + input: + bytes: [ 0xfa, 0x77, 0x19, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs x26, x25, lsl #29" + + - + input: + bytes: [ 0xf8, 0x7f, 0x17, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs x24, x23, lsl #31" + + - + input: + bytes: [ 0xf6, 0x03, 0x55, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs x22, x21, lsr #0" + + - + input: + bytes: [ 0xf4, 0x07, 0x53, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs x20, x19, lsr #1" + + - + input: + bytes: [ 0xf2, 0x7f, 0x51, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs x18, x17, lsr #31" + + - + input: + bytes: [ 0xf0, 0x03, 0x8f, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs x16, x15, asr #0" + + - + input: + bytes: [ 0xee, 0x33, 0x8d, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs x14, x13, asr #12" + + - + input: + bytes: [ 0xec, 0x7f, 0x8b, 0xeb ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "negs x12, x11, asr #31" + + - + input: + bytes: [ 0x7d, 0x03, 0x19, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adc w29, w27, w25" + + - + input: + bytes: [ 0x7f, 0x00, 0x04, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adc wzr, w3, w4" + + - + input: + bytes: [ 0xe9, 0x03, 0x0a, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adc w9, wzr, w10" + + - + input: + bytes: [ 0x14, 0x00, 0x1f, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adc w20, w0, wzr" + + - + input: + bytes: [ 0x7d, 0x03, 0x19, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adc x29, x27, x25" + + - + input: + bytes: [ 0x7f, 0x00, 0x04, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adc xzr, x3, x4" + + - + input: + bytes: [ 0xe9, 0x03, 0x0a, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adc x9, xzr, x10" + + - + input: + bytes: [ 0x14, 0x00, 0x1f, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adc x20, x0, xzr" + + - + input: + bytes: [ 0x7d, 0x03, 0x19, 0x3a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adcs w29, w27, w25" + + - + input: + bytes: [ 0x7f, 0x00, 0x04, 0x3a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adcs wzr, w3, w4" + + - + input: + bytes: [ 0xe9, 0x03, 0x0a, 0x3a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adcs w9, wzr, w10" + + - + input: + bytes: [ 0x14, 0x00, 0x1f, 0x3a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adcs w20, w0, wzr" + + - + input: + bytes: [ 0x7d, 0x03, 0x19, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adcs x29, x27, x25" + + - + input: + bytes: [ 0x7f, 0x00, 0x04, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adcs xzr, x3, x4" + + - + input: + bytes: [ 0xe9, 0x03, 0x0a, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adcs x9, xzr, x10" + + - + input: + bytes: [ 0x14, 0x00, 0x1f, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adcs x20, x0, xzr" + + - + input: + bytes: [ 0x7d, 0x03, 0x19, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbc w29, w27, w25" + + - + input: + bytes: [ 0x7f, 0x00, 0x04, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbc wzr, w3, w4" + + - + input: + bytes: [ 0xe9, 0x03, 0x0a, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ngc w9, w10" + + - + input: + bytes: [ 0x14, 0x00, 0x1f, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbc w20, w0, wzr" + + - + input: + bytes: [ 0x7d, 0x03, 0x19, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbc x29, x27, x25" + + - + input: + bytes: [ 0x7f, 0x00, 0x04, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbc xzr, x3, x4" + + - + input: + bytes: [ 0xe9, 0x03, 0x0a, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ngc x9, x10" + + - + input: + bytes: [ 0x14, 0x00, 0x1f, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbc x20, x0, xzr" + + - + input: + bytes: [ 0x7d, 0x03, 0x19, 0x7a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbcs w29, w27, w25" + + - + input: + bytes: [ 0x7f, 0x00, 0x04, 0x7a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbcs wzr, w3, w4" + + - + input: + bytes: [ 0xe9, 0x03, 0x0a, 0x7a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ngcs w9, w10" + + - + input: + bytes: [ 0x14, 0x00, 0x1f, 0x7a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbcs w20, w0, wzr" + + - + input: + bytes: [ 0x7d, 0x03, 0x19, 0xfa ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbcs x29, x27, x25" + + - + input: + bytes: [ 0x7f, 0x00, 0x04, 0xfa ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbcs xzr, x3, x4" + + - + input: + bytes: [ 0xe9, 0x03, 0x0a, 0xfa ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ngcs x9, x10" + + - + input: + bytes: [ 0x14, 0x00, 0x1f, 0xfa ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbcs x20, x0, xzr" + + - + input: + bytes: [ 0xe3, 0x03, 0x0c, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ngc w3, w12" + + - + input: + bytes: [ 0xff, 0x03, 0x09, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ngc wzr, w9" + + - + input: + bytes: [ 0xf7, 0x03, 0x1f, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ngc w23, wzr" + + - + input: + bytes: [ 0xfd, 0x03, 0x1e, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ngc x29, x30" + + - + input: + bytes: [ 0xff, 0x03, 0x00, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ngc xzr, x0" + + - + input: + bytes: [ 0xe0, 0x03, 0x1f, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ngc x0, xzr" + + - + input: + bytes: [ 0xe3, 0x03, 0x0c, 0x7a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ngcs w3, w12" + + - + input: + bytes: [ 0xff, 0x03, 0x09, 0x7a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ngcs wzr, w9" + + - + input: + bytes: [ 0xf7, 0x03, 0x1f, 0x7a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ngcs w23, wzr" + + - + input: + bytes: [ 0xfd, 0x03, 0x1e, 0xfa ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ngcs x29, x30" + + - + input: + bytes: [ 0xff, 0x03, 0x00, 0xfa ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ngcs xzr, x0" + + - + input: + bytes: [ 0xe0, 0x03, 0x1f, 0xfa ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ngcs x0, xzr" + + - + input: + bytes: [ 0x41, 0x10, 0x43, 0x93 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbfx x1, x2, #3, #2" + + - + input: + bytes: [ 0x83, 0xfc, 0x7f, 0x93 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr x3, x4, #63" + + - + input: + bytes: [ 0xff, 0x7f, 0x1f, 0x13 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr wzr, wzr, #31" + + - + input: + bytes: [ 0x2c, 0x01, 0x00, 0x13 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbfx w12, w9, #0, #1" + + - + input: + bytes: [ 0xa4, 0x28, 0x4c, 0xd3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ubfiz x4, x5, #52, #11" + + - + input: + bytes: [ 0x9f, 0x00, 0x40, 0xd3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ubfx xzr, x4, #0, #1" + + - + input: + bytes: [ 0xe4, 0x17, 0x7f, 0xd3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ubfiz x4, xzr, #1, #6" + + - + input: + bytes: [ 0xc5, 0xfc, 0x4c, 0xd3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr x5, x6, #12" + + - + input: + bytes: [ 0xa4, 0x28, 0x4c, 0xb3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfi x4, x5, #52, #11" + + - + input: + bytes: [ 0x9f, 0x00, 0x40, 0xb3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfxil xzr, x4, #0, #1" + + - + input: + bytes: [ 0xe4, 0x17, 0x7f, 0xb3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfi x4, xzr, #1, #6" + skip: true + skip_reason: "Requires to disable the HasV8_2aOps feature. Which is not possible without adding unnecessary bloat." + + - + input: + bytes: [ 0xc5, 0xfc, 0x4c, 0xb3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfxil x5, x6, #12, #52" + + - + input: + bytes: [ 0x41, 0x1c, 0x00, 0x13 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sxtb w1, w2" + + - + input: + bytes: [ 0x7f, 0x1c, 0x40, 0x93 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sxtb xzr, w3" + + - + input: + bytes: [ 0x49, 0x3d, 0x00, 0x13 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sxth w9, w10" + + - + input: + bytes: [ 0x20, 0x3c, 0x40, 0x93 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sxth x0, w1" + + - + input: + bytes: [ 0xc3, 0x7f, 0x40, 0x93 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sxtw x3, w30" + + - + input: + bytes: [ 0x41, 0x1c, 0x00, 0x53 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "uxtb w1, w2" + + - + input: + bytes: [ 0x7f, 0x1c, 0x00, 0x53 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "uxtb wzr, w3" + + - + input: + bytes: [ 0x49, 0x3d, 0x00, 0x53 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "uxth w9, w10" + + - + input: + bytes: [ 0x20, 0x3c, 0x00, 0x53 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "uxth w0, w1" + + - + input: + bytes: [ 0x43, 0x7c, 0x00, 0x13 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr w3, w2, #0" + + - + input: + bytes: [ 0x49, 0x7d, 0x1f, 0x13 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr w9, w10, #31" + + - + input: + bytes: [ 0xb4, 0xfe, 0x7f, 0x93 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr x20, x21, #63" + + - + input: + bytes: [ 0xe1, 0x7f, 0x03, 0x13 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr w1, wzr, #3" + + - + input: + bytes: [ 0x43, 0x7c, 0x00, 0x53 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr w3, w2, #0" + + - + input: + bytes: [ 0x49, 0x7d, 0x1f, 0x53 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr w9, w10, #31" + + - + input: + bytes: [ 0xb4, 0xfe, 0x7f, 0xd3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr x20, x21, #63" + + - + input: + bytes: [ 0xff, 0x7f, 0x03, 0x53 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr wzr, wzr, #3" + + - + input: + bytes: [ 0x43, 0x7c, 0x00, 0x53 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr w3, w2, #0" + + - + input: + bytes: [ 0x49, 0x01, 0x01, 0x53 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsl w9, w10, #31" + + - + input: + bytes: [ 0xb4, 0x02, 0x41, 0xd3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsl x20, x21, #63" + + - + input: + bytes: [ 0xe1, 0x73, 0x1d, 0x53 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsl w1, wzr, #3" + + - + input: + bytes: [ 0x49, 0x01, 0x00, 0x13 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbfx w9, w10, #0, #1" + + - + input: + bytes: [ 0x62, 0x00, 0x41, 0x93 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbfiz x2, x3, #63, #1" + + - + input: + bytes: [ 0x93, 0xfe, 0x40, 0x93 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr x19, x20, #0" + + - + input: + bytes: [ 0x49, 0xe9, 0x7b, 0x93 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbfiz x9, x10, #5, #59" + + - + input: + bytes: [ 0x49, 0x7d, 0x00, 0x13 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr w9, w10, #0" + + - + input: + bytes: [ 0x8b, 0x01, 0x01, 0x13 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbfiz w11, w12, #31, #1" + + - + input: + bytes: [ 0xcd, 0x09, 0x03, 0x13 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbfiz w13, w14, #29, #3" + + - + input: + bytes: [ 0xff, 0x2b, 0x76, 0x93 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbfiz xzr, xzr, #10, #11" + + - + input: + bytes: [ 0x49, 0x01, 0x00, 0x13 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbfx w9, w10, #0, #1" + + - + input: + bytes: [ 0x62, 0xfc, 0x7f, 0x93 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr x2, x3, #63" + + - + input: + bytes: [ 0x93, 0xfe, 0x40, 0x93 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr x19, x20, #0" + + - + input: + bytes: [ 0x49, 0xfd, 0x45, 0x93 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr x9, x10, #5" + + - + input: + bytes: [ 0x49, 0x7d, 0x00, 0x13 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr w9, w10, #0" + + - + input: + bytes: [ 0x8b, 0x7d, 0x1f, 0x13 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr w11, w12, #31" + + - + input: + bytes: [ 0xcd, 0x7d, 0x1d, 0x13 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr w13, w14, #29" + + - + input: + bytes: [ 0xff, 0x53, 0x4a, 0x93 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sbfx xzr, xzr, #10, #11" + + - + input: + bytes: [ 0x49, 0x01, 0x00, 0x33 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfxil w9, w10, #0, #1" + + - + input: + bytes: [ 0x62, 0x00, 0x41, 0xb3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfi x2, x3, #63, #1" + + - + input: + bytes: [ 0x93, 0xfe, 0x40, 0xb3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfxil x19, x20, #0, #64" + + - + input: + bytes: [ 0x49, 0xe9, 0x7b, 0xb3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfi x9, x10, #5, #59" + + - + input: + bytes: [ 0x49, 0x7d, 0x00, 0x33 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfxil w9, w10, #0, #32" + + - + input: + bytes: [ 0x8b, 0x01, 0x01, 0x33 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfi w11, w12, #31, #1" + + - + input: + bytes: [ 0xcd, 0x09, 0x03, 0x33 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfi w13, w14, #29, #3" + + - + input: + bytes: [ 0xff, 0x2b, 0x76, 0xb3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfi xzr, xzr, #10, #11" + skip: true + skip_reason: "Requires to disable the HasV8_2aOps feature. Which is not possible without adding unnecessary bloat." + + - + input: + bytes: [ 0x49, 0x01, 0x00, 0x33 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfxil w9, w10, #0, #1" + + - + input: + bytes: [ 0x62, 0xfc, 0x7f, 0xb3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfxil x2, x3, #63, #1" + + - + input: + bytes: [ 0x93, 0xfe, 0x40, 0xb3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfxil x19, x20, #0, #64" + + - + input: + bytes: [ 0x49, 0xfd, 0x45, 0xb3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfxil x9, x10, #5, #59" + + - + input: + bytes: [ 0x49, 0x7d, 0x00, 0x33 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfxil w9, w10, #0, #32" + + - + input: + bytes: [ 0x8b, 0x7d, 0x1f, 0x33 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfxil w11, w12, #31, #1" + + - + input: + bytes: [ 0xcd, 0x7d, 0x1d, 0x33 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfxil w13, w14, #29, #3" + + - + input: + bytes: [ 0xff, 0x53, 0x4a, 0xb3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfxil xzr, xzr, #10, #11" + + - + input: + bytes: [ 0x49, 0x01, 0x00, 0x53 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ubfx w9, w10, #0, #1" + + - + input: + bytes: [ 0x62, 0x00, 0x41, 0xd3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsl x2, x3, #63" + + - + input: + bytes: [ 0x93, 0xfe, 0x40, 0xd3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr x19, x20, #0" + + - + input: + bytes: [ 0x49, 0xe9, 0x7b, 0xd3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsl x9, x10, #5" + + - + input: + bytes: [ 0x49, 0x7d, 0x00, 0x53 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr w9, w10, #0" + + - + input: + bytes: [ 0x8b, 0x01, 0x01, 0x53 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsl w11, w12, #31" + + - + input: + bytes: [ 0xcd, 0x09, 0x03, 0x53 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsl w13, w14, #29" + + - + input: + bytes: [ 0xff, 0x2b, 0x76, 0xd3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ubfiz xzr, xzr, #10, #11" + + - + input: + bytes: [ 0x49, 0x01, 0x00, 0x53 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ubfx w9, w10, #0, #1" + + - + input: + bytes: [ 0x62, 0xfc, 0x7f, 0xd3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr x2, x3, #63" + + - + input: + bytes: [ 0x93, 0xfe, 0x40, 0xd3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr x19, x20, #0" + + - + input: + bytes: [ 0x49, 0xfd, 0x45, 0xd3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr x9, x10, #5" + + - + input: + bytes: [ 0x49, 0x7d, 0x00, 0x53 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr w9, w10, #0" + + - + input: + bytes: [ 0x8b, 0x7d, 0x1f, 0x53 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr w11, w12, #31" + + - + input: + bytes: [ 0xcd, 0x7d, 0x1d, 0x53 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr w13, w14, #29" + + - + input: + bytes: [ 0xff, 0x53, 0x4a, 0xd3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ubfx xzr, xzr, #10, #11" + + - + input: + bytes: [ 0xe3, 0x7f, 0x00, 0x33 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfxil w3, wzr, #0, #32" + skip: true + skip_reason: "Requires to disable the HasV8_2aOps feature. Which is not possible without adding unnecessary bloat." + + - + input: + bytes: [ 0xff, 0x03, 0x01, 0x33 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfi wzr, wzr, #31, #1" + skip: true + skip_reason: "Requires to disable the HasV8_2aOps feature. Which is not possible without adding unnecessary bloat." + + - + input: + bytes: [ 0xe0, 0x23, 0x7b, 0xb3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfi x0, xzr, #5, #9" + skip: true + skip_reason: "Requires to disable the HasV8_2aOps feature. Which is not possible without adding unnecessary bloat." + + - + input: + bytes: [ 0xff, 0x03, 0x41, 0xb3 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bfi xzr, xzr, #63, #1" + skip: true + skip_reason: "Requires to disable the HasV8_2aOps feature. Which is not possible without adding unnecessary bloat." + + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x34 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cbz w5, #0" + + - + input: + bytes: [ 0xe3, 0xff, 0xff, 0xb5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cbnz x3, #-4" + + - + input: + bytes: [ 0xf4, 0xff, 0x7f, 0x34 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cbz w20, #1048572" + + - + input: + bytes: [ 0x1f, 0x00, 0x80, 0xb5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cbnz xzr, #-1048576" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "b.eq #0" + + - + input: + bytes: [ 0xeb, 0xff, 0xff, 0x54 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "b.lt #-4" + + - + input: + bytes: [ 0xe3, 0xff, 0x7f, 0x54 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "b.lo #1048572" + + - + input: + bytes: [ 0x20, 0x08, 0x5f, 0x7a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmp w1, #31, #0, eq" + + - + input: + bytes: [ 0x6f, 0x28, 0x40, 0x7a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmp w3, #0, #15, hs" + + - + input: + bytes: [ 0xed, 0x2b, 0x4f, 0x7a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmp wzr, #15, #13, hs" + + - + input: + bytes: [ 0x20, 0xd9, 0x5f, 0xfa ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmp x9, #31, #0, le" + + - + input: + bytes: [ 0x6f, 0xc8, 0x40, 0xfa ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmp x3, #0, #15, gt" + + - + input: + bytes: [ 0xe7, 0x1b, 0x45, 0xfa ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmp xzr, #5, #7, ne" + + - + input: + bytes: [ 0x20, 0x08, 0x5f, 0x3a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmn w1, #31, #0, eq" + + - + input: + bytes: [ 0x6f, 0x28, 0x40, 0x3a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmn w3, #0, #15, hs" + + - + input: + bytes: [ 0xed, 0x2b, 0x4f, 0x3a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmn wzr, #15, #13, hs" + + - + input: + bytes: [ 0x20, 0xd9, 0x5f, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmn x9, #31, #0, le" + + - + input: + bytes: [ 0x6f, 0xc8, 0x40, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmn x3, #0, #15, gt" + + - + input: + bytes: [ 0xe7, 0x1b, 0x45, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmn xzr, #5, #7, ne" + + - + input: + bytes: [ 0x20, 0x00, 0x5f, 0x7a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmp w1, wzr, #0, eq" + + - + input: + bytes: [ 0x6f, 0x20, 0x40, 0x7a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmp w3, w0, #15, hs" + + - + input: + bytes: [ 0xed, 0x23, 0x4f, 0x7a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmp wzr, w15, #13, hs" + + - + input: + bytes: [ 0x20, 0xd1, 0x5f, 0xfa ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmp x9, xzr, #0, le" + + - + input: + bytes: [ 0x6f, 0xc0, 0x40, 0xfa ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmp x3, x0, #15, gt" + + - + input: + bytes: [ 0xe7, 0x13, 0x45, 0xfa ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmp xzr, x5, #7, ne" + + - + input: + bytes: [ 0x20, 0x00, 0x5f, 0x3a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmn w1, wzr, #0, eq" + + - + input: + bytes: [ 0x6f, 0x20, 0x40, 0x3a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmn w3, w0, #15, hs" + + - + input: + bytes: [ 0xed, 0x23, 0x4f, 0x3a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmn wzr, w15, #13, hs" + + - + input: + bytes: [ 0x20, 0xd1, 0x5f, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmn x9, xzr, #0, le" + + - + input: + bytes: [ 0x6f, 0xc0, 0x40, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmn x3, x0, #15, gt" + + - + input: + bytes: [ 0xe7, 0x13, 0x45, 0xba ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ccmn xzr, x5, #7, ne" + + - + input: + bytes: [ 0x01, 0x10, 0x93, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csel w1, w0, w19, ne" + + - + input: + bytes: [ 0xbf, 0x00, 0x89, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csel wzr, w5, w9, eq" + + - + input: + bytes: [ 0xe9, 0xc3, 0x9e, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csel w9, wzr, w30, gt" + + - + input: + bytes: [ 0x81, 0x43, 0x9f, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csel w1, w28, wzr, mi" + + - + input: + bytes: [ 0xf3, 0xb2, 0x9d, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csel x19, x23, x29, lt" + + - + input: + bytes: [ 0x7f, 0xa0, 0x84, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csel xzr, x3, x4, ge" + + - + input: + bytes: [ 0xe5, 0x23, 0x86, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csel x5, xzr, x6, hs" + + - + input: + bytes: [ 0x07, 0x31, 0x9f, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csel x7, x8, xzr, lo" + + - + input: + bytes: [ 0x01, 0x14, 0x93, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csinc w1, w0, w19, ne" + + - + input: + bytes: [ 0xbf, 0x04, 0x89, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csinc wzr, w5, w9, eq" + + - + input: + bytes: [ 0xe9, 0xc7, 0x9e, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csinc w9, wzr, w30, gt" + + - + input: + bytes: [ 0x81, 0x47, 0x9f, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csinc w1, w28, wzr, mi" + + - + input: + bytes: [ 0xf3, 0xb6, 0x9d, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csinc x19, x23, x29, lt" + + - + input: + bytes: [ 0x7f, 0xa4, 0x84, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csinc xzr, x3, x4, ge" + + - + input: + bytes: [ 0xe5, 0x27, 0x86, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csinc x5, xzr, x6, hs" + + - + input: + bytes: [ 0x07, 0x35, 0x9f, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csinc x7, x8, xzr, lo" + + - + input: + bytes: [ 0x01, 0x10, 0x93, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csinv w1, w0, w19, ne" + + - + input: + bytes: [ 0xbf, 0x00, 0x89, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csinv wzr, w5, w9, eq" + + - + input: + bytes: [ 0xe9, 0xc3, 0x9e, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csinv w9, wzr, w30, gt" + + - + input: + bytes: [ 0x81, 0x43, 0x9f, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csinv w1, w28, wzr, mi" + + - + input: + bytes: [ 0xf3, 0xb2, 0x9d, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csinv x19, x23, x29, lt" + + - + input: + bytes: [ 0x7f, 0xa0, 0x84, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csinv xzr, x3, x4, ge" + + - + input: + bytes: [ 0xe5, 0x23, 0x86, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csinv x5, xzr, x6, hs" + + - + input: + bytes: [ 0x07, 0x31, 0x9f, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csinv x7, x8, xzr, lo" + + - + input: + bytes: [ 0x01, 0x14, 0x93, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csneg w1, w0, w19, ne" + + - + input: + bytes: [ 0xbf, 0x04, 0x89, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csneg wzr, w5, w9, eq" + + - + input: + bytes: [ 0xe9, 0xc7, 0x9e, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csneg w9, wzr, w30, gt" + + - + input: + bytes: [ 0x81, 0x47, 0x9f, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csneg w1, w28, wzr, mi" + + - + input: + bytes: [ 0xf3, 0xb6, 0x9d, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csneg x19, x23, x29, lt" + + - + input: + bytes: [ 0x7f, 0xa4, 0x84, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csneg xzr, x3, x4, ge" + + - + input: + bytes: [ 0xe5, 0x27, 0x86, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csneg x5, xzr, x6, hs" + + - + input: + bytes: [ 0x07, 0x35, 0x9f, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csneg x7, x8, xzr, lo" + + - + input: + bytes: [ 0xe3, 0x17, 0x9f, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cset w3, eq" + + - + input: + bytes: [ 0xe9, 0x47, 0x9f, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cset x9, pl" + + - + input: + bytes: [ 0xf4, 0x03, 0x9f, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csetm w20, ne" + + - + input: + bytes: [ 0xfe, 0xb3, 0x9f, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csetm x30, ge" + + - + input: + bytes: [ 0xa3, 0xd4, 0x85, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cinc w3, w5, gt" + + - + input: + bytes: [ 0x9f, 0xc4, 0x84, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cinc wzr, w4, le" + + - + input: + bytes: [ 0xe9, 0xa7, 0x9f, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cset w9, lt" + + - + input: + bytes: [ 0xa3, 0xd4, 0x85, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cinc x3, x5, gt" + + - + input: + bytes: [ 0x9f, 0xc4, 0x84, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cinc xzr, x4, le" + + - + input: + bytes: [ 0xe9, 0xa7, 0x9f, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cset x9, lt" + + - + input: + bytes: [ 0xa3, 0xd0, 0x85, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cinv w3, w5, gt" + + - + input: + bytes: [ 0x9f, 0xc0, 0x84, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cinv wzr, w4, le" + + - + input: + bytes: [ 0xe9, 0xa3, 0x9f, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csetm w9, lt" + + - + input: + bytes: [ 0xa3, 0xd0, 0x85, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cinv x3, x5, gt" + + - + input: + bytes: [ 0x9f, 0xc0, 0x84, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cinv xzr, x4, le" + + - + input: + bytes: [ 0xe9, 0xa3, 0x9f, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "csetm x9, lt" + + - + input: + bytes: [ 0xa3, 0xd4, 0x85, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cneg w3, w5, gt" + + - + input: + bytes: [ 0x9f, 0xc4, 0x84, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cneg wzr, w4, le" + + - + input: + bytes: [ 0xe9, 0xa7, 0x9f, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cneg w9, wzr, lt" + + - + input: + bytes: [ 0xa3, 0xd4, 0x85, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cneg x3, x5, gt" + + - + input: + bytes: [ 0x9f, 0xc4, 0x84, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cneg xzr, x4, le" + + - + input: + bytes: [ 0xe9, 0xa7, 0x9f, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cneg x9, xzr, lt" + + - + input: + bytes: [ 0xe0, 0x00, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "rbit w0, w7" + + - + input: + bytes: [ 0x72, 0x00, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "rbit x18, x3" + + - + input: + bytes: [ 0x31, 0x04, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "rev16 w17, w1" + + - + input: + bytes: [ 0x45, 0x04, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "rev16 x5, x2" + + - + input: + bytes: [ 0x12, 0x08, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "rev w18, w0" + + - + input: + bytes: [ 0x34, 0x08, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "rev32 x20, x1" + + - + input: + bytes: [ 0xf4, 0x0b, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "rev32 x20, xzr" + + - + input: + bytes: [ 0x56, 0x0c, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "rev x22, x2" + + - + input: + bytes: [ 0xf2, 0x0f, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "rev x18, xzr" + + - + input: + bytes: [ 0xe7, 0x0b, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "rev w7, wzr" + + - + input: + bytes: [ 0x78, 0x10, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "clz w24, w3" + + - + input: + bytes: [ 0x9a, 0x10, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "clz x26, x4" + + - + input: + bytes: [ 0xa3, 0x14, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cls w3, w5" + + - + input: + bytes: [ 0xb4, 0x14, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "cls x20, x5" + + - + input: + bytes: [ 0xf8, 0x13, 0xc0, 0x5a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "clz w24, wzr" + + - + input: + bytes: [ 0xf6, 0x0f, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "rev x22, xzr" + + - + input: + bytes: [ 0x8d, 0x0d, 0xc0, 0xda ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "rev x13, x12" + + - + input: + bytes: [ 0xe0, 0x08, 0xca, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "udiv w0, w7, w10" + + - + input: + bytes: [ 0xc9, 0x0a, 0xc4, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "udiv x9, x22, x4" + + - + input: + bytes: [ 0xac, 0x0e, 0xc0, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sdiv w12, w21, w0" + + - + input: + bytes: [ 0x4d, 0x0c, 0xc1, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sdiv x13, x2, x1" + + - + input: + bytes: [ 0x8b, 0x21, 0xcd, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsl w11, w12, w13" + + - + input: + bytes: [ 0xee, 0x21, 0xd0, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsl x14, x15, x16" + + - + input: + bytes: [ 0x51, 0x26, 0xd3, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr w17, w18, w19" + + - + input: + bytes: [ 0xb4, 0x26, 0xd6, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr x20, x21, x22" + + - + input: + bytes: [ 0x17, 0x2b, 0xd9, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr w23, w24, w25" + + - + input: + bytes: [ 0x7a, 0x2b, 0xdc, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr x26, x27, x28" + + - + input: + bytes: [ 0x20, 0x2c, 0xc2, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ror w0, w1, w2" + + - + input: + bytes: [ 0x83, 0x2c, 0xc5, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ror x3, x4, x5" + + - + input: + bytes: [ 0xe6, 0x20, 0xc8, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsl w6, w7, w8" + + - + input: + bytes: [ 0x49, 0x21, 0xcb, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsl x9, x10, x11" + + - + input: + bytes: [ 0xac, 0x25, 0xce, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr w12, w13, w14" + + - + input: + bytes: [ 0x0f, 0x26, 0xd1, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "lsr x15, x16, x17" + + - + input: + bytes: [ 0x72, 0x2a, 0xd4, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr w18, w19, w20" + + - + input: + bytes: [ 0xd5, 0x2a, 0xd7, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "asr x21, x22, x23" + + - + input: + bytes: [ 0x38, 0x2f, 0xda, 0x1a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ror w24, w25, w26" + + - + input: + bytes: [ 0x9b, 0x2f, 0xdd, 0x9a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ror x27, x28, x29" + + - + input: + bytes: [ 0x61, 0x10, 0x07, 0x1b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "madd w1, w3, w7, w4" + + - + input: + bytes: [ 0x1f, 0x2c, 0x09, 0x1b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "madd wzr, w0, w9, w11" + + - + input: + bytes: [ 0xed, 0x13, 0x04, 0x1b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "madd w13, wzr, w4, w4" + + - + input: + bytes: [ 0xd3, 0x77, 0x1f, 0x1b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "madd w19, w30, wzr, w29" + + - + input: + bytes: [ 0xa4, 0x7c, 0x06, 0x1b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mul w4, w5, w6" + + - + input: + bytes: [ 0x61, 0x10, 0x07, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "madd x1, x3, x7, x4" + + - + input: + bytes: [ 0x1f, 0x2c, 0x09, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "madd xzr, x0, x9, x11" + + - + input: + bytes: [ 0xed, 0x13, 0x04, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "madd x13, xzr, x4, x4" + + - + input: + bytes: [ 0xd3, 0x77, 0x1f, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "madd x19, x30, xzr, x29" + + - + input: + bytes: [ 0xa4, 0x7c, 0x06, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mul x4, x5, x6" + + - + input: + bytes: [ 0x61, 0x90, 0x07, 0x1b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msub w1, w3, w7, w4" + + - + input: + bytes: [ 0x1f, 0xac, 0x09, 0x1b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msub wzr, w0, w9, w11" + + - + input: + bytes: [ 0xed, 0x93, 0x04, 0x1b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msub w13, wzr, w4, w4" + + - + input: + bytes: [ 0xd3, 0xf7, 0x1f, 0x1b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msub w19, w30, wzr, w29" + + - + input: + bytes: [ 0xa4, 0xfc, 0x06, 0x1b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mneg w4, w5, w6" + + - + input: + bytes: [ 0x61, 0x90, 0x07, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msub x1, x3, x7, x4" + + - + input: + bytes: [ 0x1f, 0xac, 0x09, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msub xzr, x0, x9, x11" + + - + input: + bytes: [ 0xed, 0x93, 0x04, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msub x13, xzr, x4, x4" + + - + input: + bytes: [ 0xd3, 0xf7, 0x1f, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msub x19, x30, xzr, x29" + + - + input: + bytes: [ 0xa4, 0xfc, 0x06, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mneg x4, x5, x6" + + - + input: + bytes: [ 0xa3, 0x24, 0x22, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "smaddl x3, w5, w2, x9" + + - + input: + bytes: [ 0x5f, 0x31, 0x2b, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "smaddl xzr, w10, w11, x12" + + - + input: + bytes: [ 0xed, 0x3f, 0x2e, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "smaddl x13, wzr, w14, x15" + + - + input: + bytes: [ 0x30, 0x4a, 0x3f, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "smaddl x16, w17, wzr, x18" + + - + input: + bytes: [ 0x93, 0x7e, 0x35, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "smull x19, w20, w21" + + - + input: + bytes: [ 0xa3, 0xa4, 0x22, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "smsubl x3, w5, w2, x9" + + - + input: + bytes: [ 0x5f, 0xb1, 0x2b, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "smsubl xzr, w10, w11, x12" + + - + input: + bytes: [ 0xed, 0xbf, 0x2e, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "smsubl x13, wzr, w14, x15" + + - + input: + bytes: [ 0x30, 0xca, 0x3f, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "smsubl x16, w17, wzr, x18" + + - + input: + bytes: [ 0x93, 0xfe, 0x35, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "smnegl x19, w20, w21" + + - + input: + bytes: [ 0xa3, 0x24, 0xa2, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "umaddl x3, w5, w2, x9" + + - + input: + bytes: [ 0x5f, 0x31, 0xab, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "umaddl xzr, w10, w11, x12" + + - + input: + bytes: [ 0xed, 0x3f, 0xae, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "umaddl x13, wzr, w14, x15" + + - + input: + bytes: [ 0x30, 0x4a, 0xbf, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "umaddl x16, w17, wzr, x18" + + - + input: + bytes: [ 0x93, 0x7e, 0xb5, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "umull x19, w20, w21" + + - + input: + bytes: [ 0xa3, 0xa4, 0xa2, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "umsubl x3, w5, w2, x9" + + - + input: + bytes: [ 0x5f, 0xb1, 0xab, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "umsubl xzr, w10, w11, x12" + + - + input: + bytes: [ 0xed, 0xbf, 0xae, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "umsubl x13, wzr, w14, x15" + + - + input: + bytes: [ 0x30, 0xca, 0xbf, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "umsubl x16, w17, wzr, x18" + + - + input: + bytes: [ 0x93, 0xfe, 0xb5, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "umnegl x19, w20, w21" + + - + input: + bytes: [ 0xbe, 0x7f, 0x5c, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "smulh x30, x29, x28" + + - + input: + bytes: [ 0x7f, 0x7f, 0x5a, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "smulh xzr, x27, x26" + + - + input: + bytes: [ 0xf9, 0x7f, 0x58, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "smulh x25, xzr, x24" + + - + input: + bytes: [ 0xd7, 0x7e, 0x5f, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "smulh x23, x22, xzr" + + - + input: + bytes: [ 0xbe, 0x7f, 0xdc, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "umulh x30, x29, x28" + + - + input: + bytes: [ 0x7f, 0x7f, 0xda, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "umulh xzr, x27, x26" + + - + input: + bytes: [ 0xf9, 0x7f, 0xd8, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "umulh x25, xzr, x24" + + - + input: + bytes: [ 0xd7, 0x7e, 0xdf, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "umulh x23, x22, xzr" + + - + input: + bytes: [ 0x83, 0x7c, 0x05, 0x1b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mul w3, w4, w5" + + - + input: + bytes: [ 0xdf, 0x7c, 0x07, 0x1b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mul wzr, w6, w7" + + - + input: + bytes: [ 0xe8, 0x7f, 0x09, 0x1b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mul w8, wzr, w9" + + - + input: + bytes: [ 0x6a, 0x7d, 0x1f, 0x1b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mul w10, w11, wzr" + + - + input: + bytes: [ 0xac, 0x7d, 0x0e, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mul x12, x13, x14" + + - + input: + bytes: [ 0xff, 0x7d, 0x10, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mul xzr, x15, x16" + + - + input: + bytes: [ 0xf1, 0x7f, 0x12, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mul x17, xzr, x18" + + - + input: + bytes: [ 0x93, 0x7e, 0x1f, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mul x19, x20, xzr" + + - + input: + bytes: [ 0xd5, 0xfe, 0x17, 0x1b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mneg w21, w22, w23" + + - + input: + bytes: [ 0x1f, 0xff, 0x19, 0x1b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mneg wzr, w24, w25" + + - + input: + bytes: [ 0xfa, 0xff, 0x1b, 0x1b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mneg w26, wzr, w27" + + - + input: + bytes: [ 0xbc, 0xff, 0x1f, 0x1b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mneg w28, w29, wzr" + + - + input: + bytes: [ 0xab, 0x7d, 0x31, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "smull x11, w13, w17" + + - + input: + bytes: [ 0xab, 0x7d, 0xb1, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "umull x11, w13, w17" + + - + input: + bytes: [ 0xab, 0xfd, 0x31, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "smnegl x11, w13, w17" + + - + input: + bytes: [ 0xab, 0xfd, 0xb1, 0x9b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "umnegl x11, w13, w17" + + - + input: + bytes: [ 0x01, 0x00, 0x00, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "svc #0" + + - + input: + bytes: [ 0xe1, 0xff, 0x1f, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "svc #0xffff" + + - + input: + bytes: [ 0x22, 0x00, 0x00, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "hvc #0x1" + + - + input: + bytes: [ 0x03, 0xdc, 0x05, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "smc #0x2ee0" + + - + input: + bytes: [ 0x80, 0x01, 0x20, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "brk #0xc" + + - + input: + bytes: [ 0x60, 0x0f, 0x40, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "hlt #0x7b" + + - + input: + bytes: [ 0x41, 0x05, 0xa0, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dcps1 #0x2a" + + - + input: + bytes: [ 0x22, 0x01, 0xa0, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dcps2 #0x9" + + - + input: + bytes: [ 0x03, 0x7d, 0xa0, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dcps3 #0x3e8" + + - + input: + bytes: [ 0x01, 0x00, 0xa0, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dcps1" + + - + input: + bytes: [ 0x02, 0x00, 0xa0, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dcps2" + + - + input: + bytes: [ 0x03, 0x00, 0xa0, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dcps3" + + - + input: + bytes: [ 0xa3, 0x00, 0x87, 0x13 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "extr w3, w5, w7, #0" + + - + input: + bytes: [ 0xab, 0x7d, 0x91, 0x13 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "extr w11, w13, w17, #31" + + - + input: + bytes: [ 0xa3, 0x3c, 0xc7, 0x93 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "extr x3, x5, x7, #15" + + - + input: + bytes: [ 0xab, 0xfd, 0xd1, 0x93 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "extr x11, x13, x17, #63" + + - + input: + bytes: [ 0xf3, 0x62, 0xd7, 0x93 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ror x19, x23, #24" + + - + input: + bytes: [ 0xfd, 0xff, 0xdf, 0x93 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ror x29, xzr, #63" + + - + input: + bytes: [ 0xa9, 0x7d, 0x8d, 0x13 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ror w9, w13, #31" + + - + input: + bytes: [ 0x60, 0x20, 0x25, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcmp s3, s5" + + - + input: + bytes: [ 0xe8, 0x23, 0x20, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcmp s31, #0.0" + + - + input: + bytes: [ 0xb0, 0x23, 0x3e, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcmpe s29, s30" + + - + input: + bytes: [ 0xf8, 0x21, 0x20, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcmpe s15, #0.0" + + - + input: + bytes: [ 0x80, 0x20, 0x6c, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcmp d4, d12" + + - + input: + bytes: [ 0xe8, 0x22, 0x60, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcmp d23, #0.0" + + - + input: + bytes: [ 0x50, 0x23, 0x76, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcmpe d26, d22" + + - + input: + bytes: [ 0xb8, 0x23, 0x60, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcmpe d29, #0.0" + + - + input: + bytes: [ 0x20, 0x04, 0x3f, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fccmp s1, s31, #0, eq" + + - + input: + bytes: [ 0x6f, 0x24, 0x20, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fccmp s3, s0, #15, hs" + + - + input: + bytes: [ 0xed, 0x27, 0x2f, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fccmp s31, s15, #13, hs" + + - + input: + bytes: [ 0x20, 0xd5, 0x7f, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fccmp d9, d31, #0, le" + + - + input: + bytes: [ 0x6f, 0xc4, 0x60, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fccmp d3, d0, #15, gt" + + - + input: + bytes: [ 0xe7, 0x17, 0x65, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fccmp d31, d5, #7, ne" + + - + input: + bytes: [ 0x30, 0x04, 0x3f, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fccmpe s1, s31, #0, eq" + + - + input: + bytes: [ 0x7f, 0x24, 0x20, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fccmpe s3, s0, #15, hs" + + - + input: + bytes: [ 0xfd, 0x27, 0x2f, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fccmpe s31, s15, #13, hs" + + - + input: + bytes: [ 0x30, 0xd5, 0x7f, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fccmpe d9, d31, #0, le" + + - + input: + bytes: [ 0x7f, 0xc4, 0x60, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fccmpe d3, d0, #15, gt" + + - + input: + bytes: [ 0xf7, 0x17, 0x65, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fccmpe d31, d5, #7, ne" + + - + input: + bytes: [ 0x83, 0x5e, 0x29, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcsel s3, s20, s9, pl" + + - + input: + bytes: [ 0x49, 0x4d, 0x6b, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcsel d9, d10, d11, mi" + + - + input: + bytes: [ 0x20, 0x40, 0x20, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmov s0, s1" + + - + input: + bytes: [ 0x62, 0xc0, 0x20, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fabs s2, s3" + + - + input: + bytes: [ 0xa4, 0x40, 0x21, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fneg s4, s5" + + - + input: + bytes: [ 0xe6, 0xc0, 0x21, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fsqrt s6, s7" + + - + input: + bytes: [ 0x28, 0xc1, 0x22, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvt d8, s9" + + - + input: + bytes: [ 0x6a, 0xc1, 0x23, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvt h10, s11" + + - + input: + bytes: [ 0xac, 0x41, 0x24, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "frintn s12, s13" + + - + input: + bytes: [ 0xee, 0xc1, 0x24, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "frintp s14, s15" + + - + input: + bytes: [ 0x30, 0x42, 0x25, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "frintm s16, s17" + + - + input: + bytes: [ 0x72, 0xc2, 0x25, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "frintz s18, s19" + + - + input: + bytes: [ 0xb4, 0x42, 0x26, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "frinta s20, s21" + + - + input: + bytes: [ 0xf6, 0x42, 0x27, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "frintx s22, s23" + + - + input: + bytes: [ 0x38, 0xc3, 0x27, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "frinti s24, s25" + + - + input: + bytes: [ 0x20, 0x40, 0x60, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmov d0, d1" + + - + input: + bytes: [ 0x62, 0xc0, 0x60, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fabs d2, d3" + + - + input: + bytes: [ 0xa4, 0x40, 0x61, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fneg d4, d5" + + - + input: + bytes: [ 0xe6, 0xc0, 0x61, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fsqrt d6, d7" + + - + input: + bytes: [ 0x28, 0x41, 0x62, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvt s8, d9" + + - + input: + bytes: [ 0x6a, 0xc1, 0x63, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvt h10, d11" + + - + input: + bytes: [ 0xac, 0x41, 0x64, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "frintn d12, d13" + + - + input: + bytes: [ 0xee, 0xc1, 0x64, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "frintp d14, d15" + + - + input: + bytes: [ 0x30, 0x42, 0x65, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "frintm d16, d17" + + - + input: + bytes: [ 0x72, 0xc2, 0x65, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "frintz d18, d19" + + - + input: + bytes: [ 0xb4, 0x42, 0x66, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "frinta d20, d21" + + - + input: + bytes: [ 0xf6, 0x42, 0x67, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "frintx d22, d23" + + - + input: + bytes: [ 0x38, 0xc3, 0x67, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "frinti d24, d25" + + - + input: + bytes: [ 0x7a, 0x43, 0xe2, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvt s26, h27" + + - + input: + bytes: [ 0xbc, 0xc3, 0xe2, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvt d28, h29" + + - + input: + bytes: [ 0x74, 0x0a, 0x31, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmul s20, s19, s17" + + - + input: + bytes: [ 0x41, 0x18, 0x23, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fdiv s1, s2, s3" + + - + input: + bytes: [ 0xa4, 0x28, 0x26, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fadd s4, s5, s6" + + - + input: + bytes: [ 0x07, 0x39, 0x29, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fsub s7, s8, s9" + + - + input: + bytes: [ 0x6a, 0x49, 0x2c, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmax s10, s11, s12" + + - + input: + bytes: [ 0xcd, 0x59, 0x2f, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmin s13, s14, s15" + + - + input: + bytes: [ 0x30, 0x6a, 0x32, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmaxnm s16, s17, s18" + + - + input: + bytes: [ 0x93, 0x7a, 0x35, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fminnm s19, s20, s21" + + - + input: + bytes: [ 0xf6, 0x8a, 0x38, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fnmul s22, s23, s24" + + - + input: + bytes: [ 0x74, 0x0a, 0x71, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmul d20, d19, d17" + + - + input: + bytes: [ 0x41, 0x18, 0x63, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fdiv d1, d2, d3" + + - + input: + bytes: [ 0xa4, 0x28, 0x66, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fadd d4, d5, d6" + + - + input: + bytes: [ 0x07, 0x39, 0x69, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fsub d7, d8, d9" + + - + input: + bytes: [ 0x6a, 0x49, 0x6c, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmax d10, d11, d12" + + - + input: + bytes: [ 0xcd, 0x59, 0x6f, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmin d13, d14, d15" + + - + input: + bytes: [ 0x30, 0x6a, 0x72, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmaxnm d16, d17, d18" + + - + input: + bytes: [ 0x93, 0x7a, 0x75, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fminnm d19, d20, d21" + + - + input: + bytes: [ 0xf6, 0x8a, 0x78, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fnmul d22, d23, d24" + + - + input: + bytes: [ 0xa3, 0x7c, 0x06, 0x1f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmadd s3, s5, s6, s31" + + - + input: + bytes: [ 0xa3, 0x5d, 0x40, 0x1f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmadd d3, d13, d0, d23" + + - + input: + bytes: [ 0xa3, 0xfc, 0x06, 0x1f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmsub s3, s5, s6, s31" + + - + input: + bytes: [ 0xa3, 0xdd, 0x40, 0x1f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmsub d3, d13, d0, d23" + + - + input: + bytes: [ 0xa3, 0x7c, 0x26, 0x1f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fnmadd s3, s5, s6, s31" + + - + input: + bytes: [ 0xa3, 0x5d, 0x60, 0x1f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fnmadd d3, d13, d0, d23" + + - + input: + bytes: [ 0xa3, 0xfc, 0x26, 0x1f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fnmsub s3, s5, s6, s31" + + - + input: + bytes: [ 0xa3, 0xdd, 0x60, 0x1f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fnmsub d3, d13, d0, d23" + + - + input: + bytes: [ 0xa3, 0xfc, 0x18, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzs w3, s5, #1" + + - + input: + bytes: [ 0x9f, 0xce, 0x18, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzs wzr, s20, #13" + + - + input: + bytes: [ 0x13, 0x80, 0x18, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzs w19, s0, #32" + + - + input: + bytes: [ 0xa3, 0xfc, 0x18, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzs x3, s5, #1" + + - + input: + bytes: [ 0xcc, 0x4f, 0x18, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzs x12, s30, #45" + + - + input: + bytes: [ 0x13, 0x00, 0x18, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzs x19, s0, #64" + + - + input: + bytes: [ 0xa3, 0xfc, 0x58, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzs w3, d5, #1" + + - + input: + bytes: [ 0x9f, 0xce, 0x58, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzs wzr, d20, #13" + + - + input: + bytes: [ 0x13, 0x80, 0x58, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzs w19, d0, #32" + + - + input: + bytes: [ 0xa3, 0xfc, 0x58, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzs x3, d5, #1" + + - + input: + bytes: [ 0xcc, 0x4f, 0x58, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzs x12, d30, #45" + + - + input: + bytes: [ 0x13, 0x00, 0x58, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzs x19, d0, #64" + + - + input: + bytes: [ 0xa3, 0xfc, 0x19, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzu w3, s5, #1" + + - + input: + bytes: [ 0x9f, 0xce, 0x19, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzu wzr, s20, #13" + + - + input: + bytes: [ 0x13, 0x80, 0x19, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzu w19, s0, #32" + + - + input: + bytes: [ 0xa3, 0xfc, 0x19, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzu x3, s5, #1" + + - + input: + bytes: [ 0xcc, 0x4f, 0x19, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzu x12, s30, #45" + + - + input: + bytes: [ 0x13, 0x00, 0x19, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzu x19, s0, #64" + + - + input: + bytes: [ 0xa3, 0xfc, 0x59, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzu w3, d5, #1" + + - + input: + bytes: [ 0x9f, 0xce, 0x59, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzu wzr, d20, #13" + + - + input: + bytes: [ 0x13, 0x80, 0x59, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzu w19, d0, #32" + + - + input: + bytes: [ 0xa3, 0xfc, 0x59, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzu x3, d5, #1" + + - + input: + bytes: [ 0xcc, 0x4f, 0x59, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzu x12, d30, #45" + + - + input: + bytes: [ 0x13, 0x00, 0x59, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzu x19, d0, #64" + + - + input: + bytes: [ 0x77, 0xfe, 0x02, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "scvtf s23, w19, #1" + + - + input: + bytes: [ 0xff, 0xb3, 0x02, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "scvtf s31, wzr, #20" + + - + input: + bytes: [ 0x0e, 0x80, 0x02, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "scvtf s14, w0, #32" + + - + input: + bytes: [ 0x77, 0xfe, 0x02, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "scvtf s23, x19, #1" + + - + input: + bytes: [ 0xff, 0xb3, 0x02, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "scvtf s31, xzr, #20" + + - + input: + bytes: [ 0x0e, 0x00, 0x02, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "scvtf s14, x0, #64" + + - + input: + bytes: [ 0x77, 0xfe, 0x42, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "scvtf d23, w19, #1" + + - + input: + bytes: [ 0xff, 0xb3, 0x42, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "scvtf d31, wzr, #20" + + - + input: + bytes: [ 0x0e, 0x80, 0x42, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "scvtf d14, w0, #32" + + - + input: + bytes: [ 0x77, 0xfe, 0x42, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "scvtf d23, x19, #1" + + - + input: + bytes: [ 0xff, 0xb3, 0x42, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "scvtf d31, xzr, #20" + + - + input: + bytes: [ 0x0e, 0x00, 0x42, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "scvtf d14, x0, #64" + + - + input: + bytes: [ 0x77, 0xfe, 0x03, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ucvtf s23, w19, #1" + + - + input: + bytes: [ 0xff, 0xb3, 0x03, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ucvtf s31, wzr, #20" + + - + input: + bytes: [ 0x0e, 0x80, 0x03, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ucvtf s14, w0, #32" + + - + input: + bytes: [ 0x77, 0xfe, 0x03, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ucvtf s23, x19, #1" + + - + input: + bytes: [ 0xff, 0xb3, 0x03, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ucvtf s31, xzr, #20" + + - + input: + bytes: [ 0x0e, 0x00, 0x03, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ucvtf s14, x0, #64" + + - + input: + bytes: [ 0x77, 0xfe, 0x43, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ucvtf d23, w19, #1" + + - + input: + bytes: [ 0xff, 0xb3, 0x43, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ucvtf d31, wzr, #20" + + - + input: + bytes: [ 0x0e, 0x80, 0x43, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ucvtf d14, w0, #32" + + - + input: + bytes: [ 0x77, 0xfe, 0x43, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ucvtf d23, x19, #1" + + - + input: + bytes: [ 0xff, 0xb3, 0x43, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ucvtf d31, xzr, #20" + + - + input: + bytes: [ 0x0e, 0x00, 0x43, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ucvtf d14, x0, #64" + + - + input: + bytes: [ 0xe3, 0x03, 0x20, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtns w3, s31" + + - + input: + bytes: [ 0x9f, 0x01, 0x20, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtns xzr, s12" + + - + input: + bytes: [ 0x9f, 0x01, 0x21, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtnu wzr, s12" + + - + input: + bytes: [ 0x00, 0x00, 0x21, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtnu x0, s0" + + - + input: + bytes: [ 0x3f, 0x01, 0x28, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtps wzr, s9" + + - + input: + bytes: [ 0x8c, 0x02, 0x28, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtps x12, s20" + + - + input: + bytes: [ 0xfe, 0x02, 0x29, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtpu w30, s23" + + - + input: + bytes: [ 0x7d, 0x00, 0x29, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtpu x29, s3" + + - + input: + bytes: [ 0x62, 0x00, 0x30, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtms w2, s3" + + - + input: + bytes: [ 0xa4, 0x00, 0x30, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtms x4, s5" + + - + input: + bytes: [ 0xe6, 0x00, 0x31, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtmu w6, s7" + + - + input: + bytes: [ 0x28, 0x01, 0x31, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtmu x8, s9" + + - + input: + bytes: [ 0x6a, 0x01, 0x38, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzs w10, s11" + + - + input: + bytes: [ 0xac, 0x01, 0x38, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzs x12, s13" + + - + input: + bytes: [ 0xee, 0x01, 0x39, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzu w14, s15" + + - + input: + bytes: [ 0x0f, 0x02, 0x39, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzu x15, s16" + + - + input: + bytes: [ 0x51, 0x02, 0x22, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "scvtf s17, w18" + + - + input: + bytes: [ 0x93, 0x02, 0x22, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "scvtf s19, x20" + + - + input: + bytes: [ 0xd5, 0x02, 0x23, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ucvtf s21, w22" + + - + input: + bytes: [ 0x17, 0x03, 0x22, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "scvtf s23, x24" + + - + input: + bytes: [ 0x59, 0x03, 0x24, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtas w25, s26" + + - + input: + bytes: [ 0x9b, 0x03, 0x24, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtas x27, s28" + + - + input: + bytes: [ 0xdd, 0x03, 0x25, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtau w29, s30" + + - + input: + bytes: [ 0x1f, 0x00, 0x25, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtau xzr, s0" + + - + input: + bytes: [ 0xe3, 0x03, 0x60, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtns w3, d31" + + - + input: + bytes: [ 0x9f, 0x01, 0x60, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtns xzr, d12" + + - + input: + bytes: [ 0x9f, 0x01, 0x61, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtnu wzr, d12" + + - + input: + bytes: [ 0x00, 0x00, 0x61, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtnu x0, d0" + + - + input: + bytes: [ 0x3f, 0x01, 0x68, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtps wzr, d9" + + - + input: + bytes: [ 0x8c, 0x02, 0x68, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtps x12, d20" + + - + input: + bytes: [ 0xfe, 0x02, 0x69, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtpu w30, d23" + + - + input: + bytes: [ 0x7d, 0x00, 0x69, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtpu x29, d3" + + - + input: + bytes: [ 0x62, 0x00, 0x70, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtms w2, d3" + + - + input: + bytes: [ 0xa4, 0x00, 0x70, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtms x4, d5" + + - + input: + bytes: [ 0xe6, 0x00, 0x71, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtmu w6, d7" + + - + input: + bytes: [ 0x28, 0x01, 0x71, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtmu x8, d9" + + - + input: + bytes: [ 0x6a, 0x01, 0x78, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzs w10, d11" + + - + input: + bytes: [ 0xac, 0x01, 0x78, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzs x12, d13" + + - + input: + bytes: [ 0xee, 0x01, 0x79, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzu w14, d15" + + - + input: + bytes: [ 0x0f, 0x02, 0x79, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtzu x15, d16" + + - + input: + bytes: [ 0x51, 0x02, 0x62, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "scvtf d17, w18" + + - + input: + bytes: [ 0x93, 0x02, 0x62, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "scvtf d19, x20" + + - + input: + bytes: [ 0xd5, 0x02, 0x63, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ucvtf d21, w22" + + - + input: + bytes: [ 0x17, 0x03, 0x63, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ucvtf d23, x24" + + - + input: + bytes: [ 0x59, 0x03, 0x64, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtas w25, d26" + + - + input: + bytes: [ 0x9b, 0x03, 0x64, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtas x27, d28" + + - + input: + bytes: [ 0xdd, 0x03, 0x65, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtau w29, d30" + + - + input: + bytes: [ 0x1f, 0x00, 0x65, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fcvtau xzr, d0" + + - + input: + bytes: [ 0x23, 0x01, 0x26, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmov w3, s9" + + - + input: + bytes: [ 0x69, 0x00, 0x27, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmov s9, w3" + + - + input: + bytes: [ 0xf4, 0x03, 0x66, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmov x20, d31" + + - + input: + bytes: [ 0xe1, 0x01, 0x67, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmov d1, x15" + + - + input: + bytes: [ 0x83, 0x01, 0xae, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmov x3, v12.d[1]" + + - + input: + bytes: [ 0x61, 0x02, 0xaf, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmov v1.d[1], x19" + + - + input: + bytes: [ 0xe3, 0x03, 0xaf, 0x9e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmov v3.d[1], xzr" + + - + input: + bytes: [ 0x02, 0x10, 0x28, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmov s2, #0.12500000" + + - + input: + bytes: [ 0x03, 0x10, 0x2e, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmov s3, #1.00000000" + + - + input: + bytes: [ 0x1e, 0x10, 0x66, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmov d30, #16.00000000" + + - + input: + bytes: [ 0x04, 0x30, 0x2e, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmov s4, #1.06250000" + + - + input: + bytes: [ 0x0a, 0xf0, 0x6f, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmov d10, #1.93750000" + + - + input: + bytes: [ 0x0c, 0x10, 0x3e, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmov s12, #-1.00000000" + + - + input: + bytes: [ 0x10, 0x30, 0x64, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "fmov d16, #8.50000000" + + - + input: + bytes: [ 0xe0, 0xff, 0x7f, 0x18 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr w0, #1048572" + + - + input: + bytes: [ 0x0a, 0x00, 0x80, 0x58 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr x10, #-1048576" + + - + input: + bytes: [ 0x62, 0x7c, 0x01, 0x08 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stxrb w1, w2, [x3]" + + - + input: + bytes: [ 0x83, 0x7c, 0x02, 0x48 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stxrh w2, w3, [x4]" + + - + input: + bytes: [ 0xe4, 0x7f, 0x1f, 0x88 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stxr wzr, w4, [sp]" + + - + input: + bytes: [ 0xe6, 0x7c, 0x05, 0xc8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stxr w5, x6, [x7]" + + - + input: + bytes: [ 0x27, 0x7d, 0x5f, 0x08 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldxrb w7, [x9]" + + - + input: + bytes: [ 0x5f, 0x7d, 0x5f, 0x48 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldxrh wzr, [x10]" + + - + input: + bytes: [ 0xe9, 0x7f, 0x5f, 0x88 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldxr w9, [sp]" + + - + input: + bytes: [ 0x6a, 0x7d, 0x5f, 0xc8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldxr x10, [x11]" + + - + input: + bytes: [ 0xcc, 0x35, 0x2b, 0x88 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stxp w11, w12, w13, [x14]" + + - + input: + bytes: [ 0xf7, 0x39, 0x3f, 0xc8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stxp wzr, x23, x14, [x15]" + + - + input: + bytes: [ 0xec, 0x7f, 0x7f, 0x88 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldxp w12, wzr, [sp]" + + - + input: + bytes: [ 0xed, 0x39, 0x7f, 0xc8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldxp x13, x14, [x15]" + + - + input: + bytes: [ 0x0f, 0xfe, 0x0e, 0x08 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stlxrb w14, w15, [x16]" + + - + input: + bytes: [ 0x30, 0xfe, 0x0f, 0x48 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stlxrh w15, w16, [x17]" + + - + input: + bytes: [ 0xf1, 0xff, 0x1f, 0x88 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stlxr wzr, w17, [sp]" + + - + input: + bytes: [ 0x93, 0xfe, 0x12, 0xc8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stlxr w18, x19, [x20]" + + - + input: + bytes: [ 0xb3, 0xfe, 0x5f, 0x08 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldaxrb w19, [x21]" + + - + input: + bytes: [ 0xf4, 0xff, 0x5f, 0x48 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldaxrh w20, [sp]" + + - + input: + bytes: [ 0xdf, 0xfe, 0x5f, 0x88 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldaxr wzr, [x22]" + + - + input: + bytes: [ 0xf5, 0xfe, 0x5f, 0xc8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldaxr x21, [x23]" + + - + input: + bytes: [ 0x16, 0xdf, 0x3f, 0x88 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stlxp wzr, w22, w23, [x24]" + + - + input: + bytes: [ 0xfa, 0xef, 0x39, 0xc8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stlxp w25, x26, x27, [sp]" + + - + input: + bytes: [ 0xfa, 0xff, 0x7f, 0x88 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldaxp w26, wzr, [sp]" + + - + input: + bytes: [ 0xdb, 0xf3, 0x7f, 0xc8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldaxp x27, x28, [x30]" + + - + input: + bytes: [ 0xfb, 0xff, 0x9f, 0x08 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stlrb w27, [sp]" + + - + input: + bytes: [ 0x1c, 0xfc, 0x9f, 0x48 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stlrh w28, [x0]" + + - + input: + bytes: [ 0x3f, 0xfc, 0x9f, 0x88 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stlr wzr, [x1]" + + - + input: + bytes: [ 0x5e, 0xfc, 0x9f, 0xc8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stlr x30, [x2]" + + - + input: + bytes: [ 0xfd, 0xff, 0xdf, 0x08 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldarb w29, [sp]" + + - + input: + bytes: [ 0x1e, 0xfc, 0xdf, 0x48 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldarh w30, [x0]" + + - + input: + bytes: [ 0x3f, 0xfc, 0xdf, 0x88 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldar wzr, [x1]" + + - + input: + bytes: [ 0x41, 0xfc, 0xdf, 0xc8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldar x1, [x2]" + + - + input: + bytes: [ 0x16, 0xdf, 0x3f, 0x88 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stlxp wzr, w22, w23, [x24]" + + - + input: + bytes: [ 0xe9, 0x03, 0x00, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sturb w9, [sp]" + + - + input: + bytes: [ 0x9f, 0xf1, 0x0f, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sturh wzr, [x12, #255]" + + - + input: + bytes: [ 0x10, 0x00, 0x10, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stur w16, [x0, #-256]" + + - + input: + bytes: [ 0xdc, 0x11, 0x00, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stur x28, [x14, #1]" + + - + input: + bytes: [ 0x81, 0xf2, 0x4f, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldurb w1, [x20, #255]" + + - + input: + bytes: [ 0x34, 0xf0, 0x4f, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldurh w20, [x1, #255]" + + - + input: + bytes: [ 0xec, 0xf3, 0x4f, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldur w12, [sp, #255]" + + - + input: + bytes: [ 0x9f, 0xf1, 0x4f, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldur xzr, [x12, #255]" + + - + input: + bytes: [ 0xe9, 0x00, 0x90, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldursb x9, [x7, #-256]" + + - + input: + bytes: [ 0x71, 0x02, 0x90, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldursh x17, [x19, #-256]" + + - + input: + bytes: [ 0xf4, 0x01, 0x90, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldursw x20, [x15, #-256]" + + - + input: + bytes: [ 0x4d, 0x00, 0x80, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldursw x13, [x2]" + + - + input: + bytes: [ 0xe2, 0x03, 0x90, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfum pldl2keep, [sp, #-256]" + + - + input: + bytes: [ 0x33, 0x00, 0xd0, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldursb w19, [x1, #-256]" + + - + input: + bytes: [ 0xaf, 0x02, 0xd0, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldursh w15, [x21, #-256]" + + - + input: + bytes: [ 0xe0, 0x13, 0x00, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stur b0, [sp, #1]" + + - + input: + bytes: [ 0x8c, 0xf1, 0x1f, 0x7c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stur h12, [x12, #-1]" + + - + input: + bytes: [ 0x0f, 0xf0, 0x0f, 0xbc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stur s15, [x0, #255]" + + - + input: + bytes: [ 0xbf, 0x90, 0x01, 0xfc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stur d31, [x5, #25]" + + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stur q9, [x5]" + + - + input: + bytes: [ 0xe3, 0x03, 0x40, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldur b3, [sp]" + + - + input: + bytes: [ 0x85, 0x00, 0x50, 0x7c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldur h5, [x4, #-256]" + + - + input: + bytes: [ 0x87, 0xf1, 0x5f, 0xbc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldur s7, [x12, #-1]" + + - + input: + bytes: [ 0x6b, 0x42, 0x40, 0xfc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldur d11, [x19, #4]" + + - + input: + bytes: [ 0x2d, 0x20, 0xc0, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldur q13, [x1, #2]" + + - + input: + bytes: [ 0x00, 0x00, 0x40, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr x0, [x0]" + + - + input: + bytes: [ 0xa4, 0x03, 0x40, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr x4, [x29]" + + - + input: + bytes: [ 0x9e, 0xfd, 0x7f, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr x30, [x12, #32760]" + + - + input: + bytes: [ 0xf4, 0x07, 0x40, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr x20, [sp, #8]" + + - + input: + bytes: [ 0xff, 0x03, 0x40, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr xzr, [sp]" + + - + input: + bytes: [ 0xe2, 0x03, 0x40, 0xb9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr w2, [sp]" + + - + input: + bytes: [ 0xf1, 0xff, 0x7f, 0xb9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr w17, [sp, #16380]" + + - + input: + bytes: [ 0x4d, 0x04, 0x40, 0xb9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr w13, [x2, #4]" + + - + input: + bytes: [ 0xa2, 0x04, 0x80, 0xb9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsw x2, [x5, #4]" + + - + input: + bytes: [ 0xf7, 0xff, 0xbf, 0xb9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsw x23, [sp, #16380]" + + - + input: + bytes: [ 0x82, 0x00, 0x40, 0x79 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrh w2, [x4]" + + - + input: + bytes: [ 0xd7, 0xfc, 0xff, 0x79 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsh w23, [x6, #8190]" + + - + input: + bytes: [ 0xff, 0x07, 0xc0, 0x79 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsh wzr, [sp, #2]" + + - + input: + bytes: [ 0x5d, 0x04, 0x80, 0x79 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsh x29, [x2, #2]" + + - + input: + bytes: [ 0x7a, 0xe4, 0x41, 0x39 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrb w26, [x3, #121]" + + - + input: + bytes: [ 0x4c, 0x00, 0x40, 0x39 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrb w12, [x2]" + + - + input: + bytes: [ 0xfb, 0xff, 0xff, 0x39 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsb w27, [sp, #4095]" + + - + input: + bytes: [ 0xff, 0x01, 0x80, 0x39 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsb xzr, [x15]" + + - + input: + bytes: [ 0xfe, 0x03, 0x00, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str x30, [sp]" + + - + input: + bytes: [ 0x94, 0xfc, 0x3f, 0xb9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str w20, [x4, #16380]" + + - + input: + bytes: [ 0x54, 0x1d, 0x00, 0x79 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "strh w20, [x10, #14]" + + - + input: + bytes: [ 0xf1, 0xff, 0x3f, 0x79 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "strh w17, [sp, #8190]" + + - + input: + bytes: [ 0x77, 0xfc, 0x3f, 0x39 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "strb w23, [x3, #4095]" + + - + input: + bytes: [ 0x5f, 0x00, 0x00, 0x39 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "strb wzr, [x2]" + + - + input: + bytes: [ 0xe0, 0x07, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm pldl1keep, [sp, #8]" + + - + input: + bytes: [ 0x61, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm pldl1strm, [x3]" + + - + input: + bytes: [ 0xa2, 0x08, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm pldl2keep, [x5, #16]" + + - + input: + bytes: [ 0x43, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm pldl2strm, [x2]" + + - + input: + bytes: [ 0xa4, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm pldl3keep, [x5]" + + - + input: + bytes: [ 0xc5, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm pldl3strm, [x6]" + + - + input: + bytes: [ 0xe8, 0x07, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm plil1keep, [sp, #8]" + + - + input: + bytes: [ 0x69, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm plil1strm, [x3]" + + - + input: + bytes: [ 0xaa, 0x08, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm plil2keep, [x5, #16]" + + - + input: + bytes: [ 0x4b, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm plil2strm, [x2]" + + - + input: + bytes: [ 0xac, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm plil3keep, [x5]" + + - + input: + bytes: [ 0xcd, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm plil3strm, [x6]" + + - + input: + bytes: [ 0xf0, 0x07, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm pstl1keep, [sp, #8]" + + - + input: + bytes: [ 0x71, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm pstl1strm, [x3]" + + - + input: + bytes: [ 0xb2, 0x08, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm pstl2keep, [x5, #16]" + + - + input: + bytes: [ 0x53, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm pstl2strm, [x2]" + + - + input: + bytes: [ 0xb4, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm pstl3keep, [x5]" + + - + input: + bytes: [ 0xd5, 0x00, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm pstl3strm, [x6]" + + - + input: + bytes: [ 0xef, 0x03, 0x80, 0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm plislcstrm, [sp]" + + - + input: + bytes: [ 0xff, 0xff, 0x7f, 0x3d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr b31, [sp, #4095]" + + - + input: + bytes: [ 0x54, 0xfc, 0x7f, 0x7d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr h20, [x2, #8190]" + + - + input: + bytes: [ 0x6a, 0xfe, 0x7f, 0xbd ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr s10, [x19, #16380]" + + - + input: + bytes: [ 0x43, 0xfd, 0x7f, 0xfd ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr d3, [x10, #32760]" + + - + input: + bytes: [ 0xec, 0xff, 0xbf, 0x3d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str q12, [sp, #65520]" + + - + input: + bytes: [ 0xe3, 0x6b, 0x65, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrb w3, [sp, x5]" + + - + input: + bytes: [ 0x69, 0x7b, 0x66, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrb w9, [x27, x6, lsl #0]" + + - + input: + bytes: [ 0xca, 0x6b, 0xe7, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsb w10, [x30, x7]" + + - + input: + bytes: [ 0xab, 0xeb, 0x63, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrb w11, [x29, x3, sxtx]" + + - + input: + bytes: [ 0x8c, 0xfb, 0x3f, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "strb w12, [x28, xzr, sxtx #0]" + + - + input: + bytes: [ 0x4e, 0x4b, 0x66, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrb w14, [x26, w6, uxtw]" + + - + input: + bytes: [ 0x2f, 0x5b, 0xe7, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsb w15, [x25, w7, uxtw #0]" + + - + input: + bytes: [ 0xf1, 0xca, 0x69, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrb w17, [x23, w9, sxtw]" + + - + input: + bytes: [ 0xd2, 0xda, 0xaa, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsb x18, [x22, w10, sxtw #0]" + + - + input: + bytes: [ 0xe3, 0x6b, 0xe5, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsh w3, [sp, x5]" + + - + input: + bytes: [ 0x69, 0x6b, 0xe6, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsh w9, [x27, x6]" + + - + input: + bytes: [ 0xca, 0x7b, 0x67, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrh w10, [x30, x7, lsl #1]" + + - + input: + bytes: [ 0xab, 0xeb, 0x23, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "strh w11, [x29, x3, sxtx]" + + - + input: + bytes: [ 0x8c, 0xeb, 0x7f, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrh w12, [x28, xzr, sxtx]" + + - + input: + bytes: [ 0x6d, 0xfb, 0xa5, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsh x13, [x27, x5, sxtx #1]" + + - + input: + bytes: [ 0x4e, 0x4b, 0x66, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrh w14, [x26, w6, uxtw]" + + - + input: + bytes: [ 0x2f, 0x4b, 0x67, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrh w15, [x25, w7, uxtw]" + + - + input: + bytes: [ 0x10, 0x5b, 0xe8, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsh w16, [x24, w8, uxtw #1]" + + - + input: + bytes: [ 0xf1, 0xca, 0x69, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrh w17, [x23, w9, sxtw]" + + - + input: + bytes: [ 0xd2, 0xca, 0x6a, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrh w18, [x22, w10, sxtw]" + + - + input: + bytes: [ 0xb3, 0xda, 0x3f, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "strh w19, [x21, wzr, sxtw #1]" + + - + input: + bytes: [ 0xe3, 0x6b, 0x65, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr w3, [sp, x5]" + + - + input: + bytes: [ 0x69, 0x6b, 0x66, 0xbc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr s9, [x27, x6]" + + - + input: + bytes: [ 0xca, 0x7b, 0x67, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr w10, [x30, x7, lsl #2]" + + - + input: + bytes: [ 0xab, 0xeb, 0x63, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr w11, [x29, x3, sxtx]" + + - + input: + bytes: [ 0x8c, 0xeb, 0x3f, 0xbc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str s12, [x28, xzr, sxtx]" + + - + input: + bytes: [ 0x6d, 0xfb, 0x25, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str w13, [x27, x5, sxtx #2]" + + - + input: + bytes: [ 0x4e, 0x4b, 0x26, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str w14, [x26, w6, uxtw]" + + - + input: + bytes: [ 0x2f, 0x4b, 0x67, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr w15, [x25, w7, uxtw]" + + - + input: + bytes: [ 0x10, 0x5b, 0x68, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr w16, [x24, w8, uxtw #2]" + + - + input: + bytes: [ 0xf1, 0xca, 0xa9, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsw x17, [x23, w9, sxtw]" + + - + input: + bytes: [ 0xd2, 0xca, 0x6a, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr w18, [x22, w10, sxtw]" + + - + input: + bytes: [ 0xb3, 0xda, 0xbf, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsw x19, [x21, wzr, sxtw #2]" + + - + input: + bytes: [ 0xe3, 0x6b, 0x65, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr x3, [sp, x5]" + + - + input: + bytes: [ 0x69, 0x6b, 0x26, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str x9, [x27, x6]" + + - + input: + bytes: [ 0xca, 0x7b, 0x67, 0xfc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr d10, [x30, x7, lsl #3]" + + - + input: + bytes: [ 0xab, 0xeb, 0x23, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str x11, [x29, x3, sxtx]" + + - + input: + bytes: [ 0x8c, 0xeb, 0x7f, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr x12, [x28, xzr, sxtx]" + + - + input: + bytes: [ 0x6d, 0xfb, 0x65, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr x13, [x27, x5, sxtx #3]" + + - + input: + bytes: [ 0x40, 0x4b, 0xa6, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm pldl1keep, [x26, w6, uxtw]" + + - + input: + bytes: [ 0x2f, 0x4b, 0x67, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr x15, [x25, w7, uxtw]" + + - + input: + bytes: [ 0x10, 0x5b, 0x68, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr x16, [x24, w8, uxtw #3]" + + - + input: + bytes: [ 0xf1, 0xca, 0x69, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr x17, [x23, w9, sxtw]" + + - + input: + bytes: [ 0xd2, 0xca, 0x6a, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr x18, [x22, w10, sxtw]" + + - + input: + bytes: [ 0xb3, 0xda, 0x3f, 0xfc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str d19, [x21, wzr, sxtw #3]" + + - + input: + bytes: [ 0x06, 0x68, 0xa5, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "prfm pldslckeep, [x0, x5]" + + - + input: + bytes: [ 0xe3, 0x6b, 0xe5, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr q3, [sp, x5]" + + - + input: + bytes: [ 0x69, 0x6b, 0xe6, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr q9, [x27, x6]" + + - + input: + bytes: [ 0xca, 0x7b, 0xe7, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr q10, [x30, x7, lsl #4]" + + - + input: + bytes: [ 0xab, 0xeb, 0xa3, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str q11, [x29, x3, sxtx]" + + - + input: + bytes: [ 0x8c, 0xeb, 0xbf, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str q12, [x28, xzr, sxtx]" + + - + input: + bytes: [ 0x6d, 0xfb, 0xa5, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str q13, [x27, x5, sxtx #4]" + + - + input: + bytes: [ 0x4e, 0x4b, 0xe6, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr q14, [x26, w6, uxtw]" + + - + input: + bytes: [ 0x2f, 0x4b, 0xe7, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr q15, [x25, w7, uxtw]" + + - + input: + bytes: [ 0x10, 0x5b, 0xe8, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr q16, [x24, w8, uxtw #4]" + + - + input: + bytes: [ 0xf1, 0xca, 0xe9, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr q17, [x23, w9, sxtw]" + + - + input: + bytes: [ 0xd2, 0xca, 0xaa, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str q18, [x22, w10, sxtw]" + + - + input: + bytes: [ 0xb3, 0xda, 0xff, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr q19, [x21, wzr, sxtw #4]" + + - + input: + bytes: [ 0x49, 0xf4, 0x0f, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "strb w9, [x2], #255" + + - + input: + bytes: [ 0x6a, 0x14, 0x00, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "strb w10, [x3], #1" + + - + input: + bytes: [ 0x6a, 0x04, 0x10, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "strb w10, [x3], #-256" + + - + input: + bytes: [ 0x49, 0xf4, 0x0f, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "strh w9, [x2], #255" + + - + input: + bytes: [ 0x49, 0x14, 0x00, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "strh w9, [x2], #1" + + - + input: + bytes: [ 0x6a, 0x04, 0x10, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "strh w10, [x3], #-256" + + - + input: + bytes: [ 0xf3, 0xf7, 0x0f, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str w19, [sp], #255" + + - + input: + bytes: [ 0xd4, 0x17, 0x00, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str w20, [x30], #1" + + - + input: + bytes: [ 0x95, 0x05, 0x10, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str w21, [x12], #-256" + + - + input: + bytes: [ 0x3f, 0xf5, 0x0f, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str xzr, [x9], #255" + + - + input: + bytes: [ 0x62, 0x14, 0x00, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str x2, [x3], #1" + + - + input: + bytes: [ 0x93, 0x05, 0x10, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str x19, [x12], #-256" + + - + input: + bytes: [ 0x49, 0xf4, 0x4f, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrb w9, [x2], #255" + + - + input: + bytes: [ 0x6a, 0x14, 0x40, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrb w10, [x3], #1" + + - + input: + bytes: [ 0x6a, 0x04, 0x50, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrb w10, [x3], #-256" + + - + input: + bytes: [ 0x49, 0xf4, 0x4f, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrh w9, [x2], #255" + + - + input: + bytes: [ 0x49, 0x14, 0x40, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrh w9, [x2], #1" + + - + input: + bytes: [ 0x6a, 0x04, 0x50, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrh w10, [x3], #-256" + + - + input: + bytes: [ 0xf3, 0xf7, 0x4f, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr w19, [sp], #255" + + - + input: + bytes: [ 0xd4, 0x17, 0x40, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr w20, [x30], #1" + + - + input: + bytes: [ 0x95, 0x05, 0x50, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr w21, [x12], #-256" + + - + input: + bytes: [ 0x3f, 0xf5, 0x4f, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr xzr, [x9], #255" + + - + input: + bytes: [ 0x62, 0x14, 0x40, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr x2, [x3], #1" + + - + input: + bytes: [ 0x93, 0x05, 0x50, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr x19, [x12], #-256" + + - + input: + bytes: [ 0x3f, 0xf5, 0x8f, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsb xzr, [x9], #255" + + - + input: + bytes: [ 0x62, 0x14, 0x80, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsb x2, [x3], #1" + + - + input: + bytes: [ 0x93, 0x05, 0x90, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsb x19, [x12], #-256" + + - + input: + bytes: [ 0x3f, 0xf5, 0x8f, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsh xzr, [x9], #255" + + - + input: + bytes: [ 0x62, 0x14, 0x80, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsh x2, [x3], #1" + + - + input: + bytes: [ 0x93, 0x05, 0x90, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsh x19, [x12], #-256" + + - + input: + bytes: [ 0x3f, 0xf5, 0x8f, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsw xzr, [x9], #255" + + - + input: + bytes: [ 0x62, 0x14, 0x80, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsw x2, [x3], #1" + + - + input: + bytes: [ 0x93, 0x05, 0x90, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsw x19, [x12], #-256" + + - + input: + bytes: [ 0x3f, 0xf5, 0xcf, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsb wzr, [x9], #255" + + - + input: + bytes: [ 0x62, 0x14, 0xc0, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsb w2, [x3], #1" + + - + input: + bytes: [ 0x93, 0x05, 0xd0, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsb w19, [x12], #-256" + + - + input: + bytes: [ 0x3f, 0xf5, 0xcf, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsh wzr, [x9], #255" + + - + input: + bytes: [ 0x62, 0x14, 0xc0, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsh w2, [x3], #1" + + - + input: + bytes: [ 0x93, 0x05, 0xd0, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsh w19, [x12], #-256" + + - + input: + bytes: [ 0x00, 0xf4, 0x0f, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str b0, [x0], #255" + + - + input: + bytes: [ 0x63, 0x14, 0x00, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str b3, [x3], #1" + + - + input: + bytes: [ 0xe5, 0x07, 0x10, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str b5, [sp], #-256" + + - + input: + bytes: [ 0x4a, 0xf5, 0x0f, 0x7c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str h10, [x10], #255" + + - + input: + bytes: [ 0xed, 0x16, 0x00, 0x7c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str h13, [x23], #1" + + - + input: + bytes: [ 0xef, 0x07, 0x10, 0x7c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str h15, [sp], #-256" + + - + input: + bytes: [ 0x94, 0xf6, 0x0f, 0xbc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str s20, [x20], #255" + + - + input: + bytes: [ 0xf7, 0x16, 0x00, 0xbc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str s23, [x23], #1" + + - + input: + bytes: [ 0x19, 0x04, 0x10, 0xbc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str s25, [x0], #-256" + + - + input: + bytes: [ 0x94, 0xf6, 0x0f, 0xfc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str d20, [x20], #255" + + - + input: + bytes: [ 0xf7, 0x16, 0x00, 0xfc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str d23, [x23], #1" + + - + input: + bytes: [ 0x19, 0x04, 0x10, 0xfc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str d25, [x0], #-256" + + - + input: + bytes: [ 0x00, 0xf4, 0x4f, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr b0, [x0], #255" + + - + input: + bytes: [ 0x63, 0x14, 0x40, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr b3, [x3], #1" + + - + input: + bytes: [ 0xe5, 0x07, 0x50, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr b5, [sp], #-256" + + - + input: + bytes: [ 0x4a, 0xf5, 0x4f, 0x7c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr h10, [x10], #255" + + - + input: + bytes: [ 0xed, 0x16, 0x40, 0x7c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr h13, [x23], #1" + + - + input: + bytes: [ 0xef, 0x07, 0x50, 0x7c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr h15, [sp], #-256" + + - + input: + bytes: [ 0x94, 0xf6, 0x4f, 0xbc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr s20, [x20], #255" + + - + input: + bytes: [ 0xf7, 0x16, 0x40, 0xbc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr s23, [x23], #1" + + - + input: + bytes: [ 0x19, 0x04, 0x50, 0xbc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr s25, [x0], #-256" + + - + input: + bytes: [ 0x94, 0xf6, 0x4f, 0xfc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr d20, [x20], #255" + + - + input: + bytes: [ 0xf7, 0x16, 0x40, 0xfc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr d23, [x23], #1" + + - + input: + bytes: [ 0x19, 0x04, 0x50, 0xfc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr d25, [x0], #-256" + + - + input: + bytes: [ 0x34, 0xf4, 0xcf, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr q20, [x1], #255" + + - + input: + bytes: [ 0x37, 0x15, 0xc0, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr q23, [x9], #1" + + - + input: + bytes: [ 0x99, 0x06, 0xd0, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr q25, [x20], #-256" + + - + input: + bytes: [ 0x2a, 0xf4, 0x8f, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str q10, [x1], #255" + + - + input: + bytes: [ 0xf6, 0x17, 0x80, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str q22, [sp], #1" + + - + input: + bytes: [ 0x95, 0x06, 0x90, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str q21, [x20], #-256" + + - + input: + bytes: [ 0x83, 0x0c, 0x40, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr x3, [x4, #0]!" + + - + input: + bytes: [ 0xff, 0x0f, 0x40, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr xzr, [sp, #0]!" + + - + input: + bytes: [ 0x49, 0xfc, 0x0f, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "strb w9, [x2, #255]!" + + - + input: + bytes: [ 0x6a, 0x1c, 0x00, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "strb w10, [x3, #1]!" + + - + input: + bytes: [ 0x6a, 0x0c, 0x10, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "strb w10, [x3, #-256]!" + + - + input: + bytes: [ 0x49, 0xfc, 0x0f, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "strh w9, [x2, #255]!" + + - + input: + bytes: [ 0x49, 0x1c, 0x00, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "strh w9, [x2, #1]!" + + - + input: + bytes: [ 0x6a, 0x0c, 0x10, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "strh w10, [x3, #-256]!" + + - + input: + bytes: [ 0xf3, 0xff, 0x0f, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str w19, [sp, #255]!" + + - + input: + bytes: [ 0xd4, 0x1f, 0x00, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str w20, [x30, #1]!" + + - + input: + bytes: [ 0x95, 0x0d, 0x10, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str w21, [x12, #-256]!" + + - + input: + bytes: [ 0x3f, 0xfd, 0x0f, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str xzr, [x9, #255]!" + + - + input: + bytes: [ 0x62, 0x1c, 0x00, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str x2, [x3, #1]!" + + - + input: + bytes: [ 0x93, 0x0d, 0x10, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str x19, [x12, #-256]!" + + - + input: + bytes: [ 0x49, 0xfc, 0x4f, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrb w9, [x2, #255]!" + + - + input: + bytes: [ 0x6a, 0x1c, 0x40, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrb w10, [x3, #1]!" + + - + input: + bytes: [ 0x6a, 0x0c, 0x50, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrb w10, [x3, #-256]!" + + - + input: + bytes: [ 0x49, 0xfc, 0x4f, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrh w9, [x2, #255]!" + + - + input: + bytes: [ 0x49, 0x1c, 0x40, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrh w9, [x2, #1]!" + + - + input: + bytes: [ 0x6a, 0x0c, 0x50, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrh w10, [x3, #-256]!" + + - + input: + bytes: [ 0xf3, 0xff, 0x4f, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr w19, [sp, #255]!" + + - + input: + bytes: [ 0xd4, 0x1f, 0x40, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr w20, [x30, #1]!" + + - + input: + bytes: [ 0x95, 0x0d, 0x50, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr w21, [x12, #-256]!" + + - + input: + bytes: [ 0x3f, 0xfd, 0x4f, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr xzr, [x9, #255]!" + + - + input: + bytes: [ 0x62, 0x1c, 0x40, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr x2, [x3, #1]!" + + - + input: + bytes: [ 0x93, 0x0d, 0x50, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr x19, [x12, #-256]!" + + - + input: + bytes: [ 0x3f, 0xfd, 0x8f, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsb xzr, [x9, #255]!" + + - + input: + bytes: [ 0x62, 0x1c, 0x80, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsb x2, [x3, #1]!" + + - + input: + bytes: [ 0x93, 0x0d, 0x90, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsb x19, [x12, #-256]!" + + - + input: + bytes: [ 0x3f, 0xfd, 0x8f, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsh xzr, [x9, #255]!" + + - + input: + bytes: [ 0x62, 0x1c, 0x80, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsh x2, [x3, #1]!" + + - + input: + bytes: [ 0x93, 0x0d, 0x90, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsh x19, [x12, #-256]!" + + - + input: + bytes: [ 0x3f, 0xfd, 0x8f, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsw xzr, [x9, #255]!" + + - + input: + bytes: [ 0x62, 0x1c, 0x80, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsw x2, [x3, #1]!" + + - + input: + bytes: [ 0x93, 0x0d, 0x90, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsw x19, [x12, #-256]!" + + - + input: + bytes: [ 0x3f, 0xfd, 0xcf, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsb wzr, [x9, #255]!" + + - + input: + bytes: [ 0x62, 0x1c, 0xc0, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsb w2, [x3, #1]!" + + - + input: + bytes: [ 0x93, 0x0d, 0xd0, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsb w19, [x12, #-256]!" + + - + input: + bytes: [ 0x3f, 0xfd, 0xcf, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsh wzr, [x9, #255]!" + + - + input: + bytes: [ 0x62, 0x1c, 0xc0, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsh w2, [x3, #1]!" + + - + input: + bytes: [ 0x93, 0x0d, 0xd0, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldrsh w19, [x12, #-256]!" + + - + input: + bytes: [ 0x00, 0xfc, 0x0f, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str b0, [x0, #255]!" + + - + input: + bytes: [ 0x63, 0x1c, 0x00, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str b3, [x3, #1]!" + + - + input: + bytes: [ 0xe5, 0x0f, 0x10, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str b5, [sp, #-256]!" + + - + input: + bytes: [ 0x4a, 0xfd, 0x0f, 0x7c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str h10, [x10, #255]!" + + - + input: + bytes: [ 0xed, 0x1e, 0x00, 0x7c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str h13, [x23, #1]!" + + - + input: + bytes: [ 0xef, 0x0f, 0x10, 0x7c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str h15, [sp, #-256]!" + + - + input: + bytes: [ 0x94, 0xfe, 0x0f, 0xbc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str s20, [x20, #255]!" + + - + input: + bytes: [ 0xf7, 0x1e, 0x00, 0xbc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str s23, [x23, #1]!" + + - + input: + bytes: [ 0x19, 0x0c, 0x10, 0xbc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str s25, [x0, #-256]!" + + - + input: + bytes: [ 0x94, 0xfe, 0x0f, 0xfc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str d20, [x20, #255]!" + + - + input: + bytes: [ 0xf7, 0x1e, 0x00, 0xfc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str d23, [x23, #1]!" + + - + input: + bytes: [ 0x19, 0x0c, 0x10, 0xfc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str d25, [x0, #-256]!" + + - + input: + bytes: [ 0x00, 0xfc, 0x4f, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr b0, [x0, #255]!" + + - + input: + bytes: [ 0x63, 0x1c, 0x40, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr b3, [x3, #1]!" + + - + input: + bytes: [ 0xe5, 0x0f, 0x50, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr b5, [sp, #-256]!" + + - + input: + bytes: [ 0x4a, 0xfd, 0x4f, 0x7c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr h10, [x10, #255]!" + + - + input: + bytes: [ 0xed, 0x1e, 0x40, 0x7c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr h13, [x23, #1]!" + + - + input: + bytes: [ 0xef, 0x0f, 0x50, 0x7c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr h15, [sp, #-256]!" + + - + input: + bytes: [ 0x94, 0xfe, 0x4f, 0xbc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr s20, [x20, #255]!" + + - + input: + bytes: [ 0xf7, 0x1e, 0x40, 0xbc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr s23, [x23, #1]!" + + - + input: + bytes: [ 0x19, 0x0c, 0x50, 0xbc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr s25, [x0, #-256]!" + + - + input: + bytes: [ 0x94, 0xfe, 0x4f, 0xfc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr d20, [x20, #255]!" + + - + input: + bytes: [ 0xf7, 0x1e, 0x40, 0xfc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr d23, [x23, #1]!" + + - + input: + bytes: [ 0x19, 0x0c, 0x50, 0xfc ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr d25, [x0, #-256]!" + + - + input: + bytes: [ 0x34, 0xfc, 0xcf, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr q20, [x1, #255]!" + + - + input: + bytes: [ 0x37, 0x1d, 0xc0, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr q23, [x9, #1]!" + + - + input: + bytes: [ 0x99, 0x0e, 0xd0, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldr q25, [x20, #-256]!" + + - + input: + bytes: [ 0x2a, 0xfc, 0x8f, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str q10, [x1, #255]!" + + - + input: + bytes: [ 0xf6, 0x1f, 0x80, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str q22, [sp, #1]!" + + - + input: + bytes: [ 0x95, 0x0e, 0x90, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "str q21, [x20, #-256]!" + + - + input: + bytes: [ 0xe9, 0x0b, 0x00, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sttrb w9, [sp]" + + - + input: + bytes: [ 0x9f, 0xf9, 0x0f, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sttrh wzr, [x12, #255]" + + - + input: + bytes: [ 0x10, 0x08, 0x10, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sttr w16, [x0, #-256]" + + - + input: + bytes: [ 0xdc, 0x19, 0x00, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sttr x28, [x14, #1]" + + - + input: + bytes: [ 0x81, 0xfa, 0x4f, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldtrb w1, [x20, #255]" + + - + input: + bytes: [ 0x34, 0xf8, 0x4f, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldtrh w20, [x1, #255]" + + - + input: + bytes: [ 0xec, 0xfb, 0x4f, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldtr w12, [sp, #255]" + + - + input: + bytes: [ 0x9f, 0xf9, 0x4f, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldtr xzr, [x12, #255]" + + - + input: + bytes: [ 0xe9, 0x08, 0x90, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldtrsb x9, [x7, #-256]" + + - + input: + bytes: [ 0x71, 0x0a, 0x90, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldtrsh x17, [x19, #-256]" + + - + input: + bytes: [ 0xf4, 0x09, 0x90, 0xb8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldtrsw x20, [x15, #-256]" + + - + input: + bytes: [ 0x33, 0x08, 0xd0, 0x38 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldtrsb w19, [x1, #-256]" + + - + input: + bytes: [ 0xaf, 0x0a, 0xd0, 0x78 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldtrsh w15, [x21, #-256]" + + - + input: + bytes: [ 0xe3, 0x17, 0x40, 0x29 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp w3, w5, [sp]" + + - + input: + bytes: [ 0xff, 0xa7, 0x1f, 0x29 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stp wzr, w9, [sp, #252]" + + - + input: + bytes: [ 0xe2, 0x7f, 0x60, 0x29 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp w2, wzr, [sp, #-256]" + + - + input: + bytes: [ 0xe9, 0xab, 0x40, 0x29 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp w9, w10, [sp, #4]" + + - + input: + bytes: [ 0xe9, 0xab, 0x40, 0x69 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldpsw x9, x10, [sp, #4]" + + - + input: + bytes: [ 0x49, 0x28, 0x60, 0x69 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldpsw x9, x10, [x2, #-256]" + + - + input: + bytes: [ 0xf4, 0xfb, 0x5f, 0x69 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldpsw x20, x30, [sp, #252]" + + - + input: + bytes: [ 0x55, 0xf4, 0x5f, 0xa9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp x21, x29, [x2, #504]" + + - + input: + bytes: [ 0x76, 0x5c, 0x60, 0xa9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp x22, x23, [x3, #-512]" + + - + input: + bytes: [ 0x98, 0xe4, 0x40, 0xa9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp x24, x25, [x4, #8]" + + - + input: + bytes: [ 0xfd, 0xf3, 0x5f, 0x2d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp s29, s28, [sp, #252]" + + - + input: + bytes: [ 0xfb, 0x6b, 0x20, 0x2d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stp s27, s26, [sp, #-256]" + + - + input: + bytes: [ 0x61, 0x88, 0x45, 0x2d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp s1, s2, [x3, #44]" + + - + input: + bytes: [ 0x23, 0x95, 0x1f, 0x6d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stp d3, d5, [x9, #504]" + + - + input: + bytes: [ 0x47, 0x2d, 0x20, 0x6d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stp d7, d11, [x10, #-512]" + + - + input: + bytes: [ 0xc2, 0x8f, 0x7f, 0x6d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp d2, d3, [x30, #-8]" + + - + input: + bytes: [ 0xe3, 0x17, 0x00, 0xad ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stp q3, q5, [sp]" + + - + input: + bytes: [ 0xf1, 0xcf, 0x1f, 0xad ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stp q17, q19, [sp, #1008]" + + - + input: + bytes: [ 0x37, 0x74, 0x60, 0xad ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp q23, q29, [x1, #-1024]" + + - + input: + bytes: [ 0xe3, 0x17, 0xc0, 0x28 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp w3, w5, [sp], #0" + + - + input: + bytes: [ 0xff, 0xa7, 0x9f, 0x28 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stp wzr, w9, [sp], #252" + + - + input: + bytes: [ 0xe2, 0x7f, 0xe0, 0x28 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp w2, wzr, [sp], #-256" + + - + input: + bytes: [ 0xe9, 0xab, 0xc0, 0x28 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp w9, w10, [sp], #4" + + - + input: + bytes: [ 0xe9, 0xab, 0xc0, 0x68 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldpsw x9, x10, [sp], #4" + + - + input: + bytes: [ 0x49, 0x28, 0xe0, 0x68 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldpsw x9, x10, [x2], #-256" + + - + input: + bytes: [ 0xf4, 0xfb, 0xdf, 0x68 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldpsw x20, x30, [sp], #252" + + - + input: + bytes: [ 0x55, 0xf4, 0xdf, 0xa8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp x21, x29, [x2], #504" + + - + input: + bytes: [ 0x76, 0x5c, 0xe0, 0xa8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp x22, x23, [x3], #-512" + + - + input: + bytes: [ 0x98, 0xe4, 0xc0, 0xa8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp x24, x25, [x4], #8" + + - + input: + bytes: [ 0xfd, 0xf3, 0xdf, 0x2c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp s29, s28, [sp], #252" + + - + input: + bytes: [ 0xfb, 0x6b, 0xa0, 0x2c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stp s27, s26, [sp], #-256" + + - + input: + bytes: [ 0x61, 0x88, 0xc5, 0x2c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp s1, s2, [x3], #44" + + - + input: + bytes: [ 0x23, 0x95, 0x9f, 0x6c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stp d3, d5, [x9], #504" + + - + input: + bytes: [ 0x47, 0x2d, 0xa0, 0x6c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stp d7, d11, [x10], #-512" + + - + input: + bytes: [ 0xc2, 0x8f, 0xff, 0x6c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp d2, d3, [x30], #-8" + + - + input: + bytes: [ 0xe3, 0x17, 0x80, 0xac ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stp q3, q5, [sp], #0" + + - + input: + bytes: [ 0xf1, 0xcf, 0x9f, 0xac ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stp q17, q19, [sp], #1008" + + - + input: + bytes: [ 0x37, 0x74, 0xe0, 0xac ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp q23, q29, [x1], #-1024" + + - + input: + bytes: [ 0xe3, 0x17, 0xc0, 0x29 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp w3, w5, [sp, #0]!" + + - + input: + bytes: [ 0xff, 0xa7, 0x9f, 0x29 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stp wzr, w9, [sp, #252]!" + + - + input: + bytes: [ 0xe2, 0x7f, 0xe0, 0x29 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp w2, wzr, [sp, #-256]!" + + - + input: + bytes: [ 0xe9, 0xab, 0xc0, 0x29 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp w9, w10, [sp, #4]!" + + - + input: + bytes: [ 0xe9, 0xab, 0xc0, 0x69 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldpsw x9, x10, [sp, #4]!" + + - + input: + bytes: [ 0x49, 0x28, 0xe0, 0x69 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldpsw x9, x10, [x2, #-256]!" + + - + input: + bytes: [ 0xf4, 0xfb, 0xdf, 0x69 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldpsw x20, x30, [sp, #252]!" + + - + input: + bytes: [ 0x55, 0xf4, 0xdf, 0xa9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp x21, x29, [x2, #504]!" + + - + input: + bytes: [ 0x76, 0x5c, 0xe0, 0xa9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp x22, x23, [x3, #-512]!" + + - + input: + bytes: [ 0x98, 0xe4, 0xc0, 0xa9 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp x24, x25, [x4, #8]!" + + - + input: + bytes: [ 0xfd, 0xf3, 0xdf, 0x2d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp s29, s28, [sp, #252]!" + + - + input: + bytes: [ 0xfb, 0x6b, 0xa0, 0x2d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stp s27, s26, [sp, #-256]!" + + - + input: + bytes: [ 0x61, 0x88, 0xc5, 0x2d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp s1, s2, [x3, #44]!" + + - + input: + bytes: [ 0x23, 0x95, 0x9f, 0x6d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stp d3, d5, [x9, #504]!" + + - + input: + bytes: [ 0x47, 0x2d, 0xa0, 0x6d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stp d7, d11, [x10, #-512]!" + + - + input: + bytes: [ 0xc2, 0x8f, 0xff, 0x6d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp d2, d3, [x30, #-8]!" + + - + input: + bytes: [ 0xe3, 0x17, 0x80, 0xad ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stp q3, q5, [sp, #0]!" + + - + input: + bytes: [ 0xf1, 0xcf, 0x9f, 0xad ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stp q17, q19, [sp, #1008]!" + + - + input: + bytes: [ 0x37, 0x74, 0xe0, 0xad ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldp q23, q29, [x1, #-1024]!" + + - + input: + bytes: [ 0xe3, 0x17, 0x40, 0x28 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldnp w3, w5, [sp]" + + - + input: + bytes: [ 0xff, 0xa7, 0x1f, 0x28 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stnp wzr, w9, [sp, #252]" + + - + input: + bytes: [ 0xe2, 0x7f, 0x60, 0x28 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldnp w2, wzr, [sp, #-256]" + + - + input: + bytes: [ 0xe9, 0xab, 0x40, 0x28 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldnp w9, w10, [sp, #4]" + + - + input: + bytes: [ 0x55, 0xf4, 0x5f, 0xa8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldnp x21, x29, [x2, #504]" + + - + input: + bytes: [ 0x76, 0x5c, 0x60, 0xa8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldnp x22, x23, [x3, #-512]" + + - + input: + bytes: [ 0x98, 0xe4, 0x40, 0xa8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldnp x24, x25, [x4, #8]" + + - + input: + bytes: [ 0xfd, 0xf3, 0x5f, 0x2c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldnp s29, s28, [sp, #252]" + + - + input: + bytes: [ 0xfb, 0x6b, 0x20, 0x2c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stnp s27, s26, [sp, #-256]" + + - + input: + bytes: [ 0x61, 0x88, 0x45, 0x2c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldnp s1, s2, [x3, #44]" + + - + input: + bytes: [ 0x23, 0x95, 0x1f, 0x6c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stnp d3, d5, [x9, #504]" + + - + input: + bytes: [ 0x47, 0x2d, 0x20, 0x6c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stnp d7, d11, [x10, #-512]" + + - + input: + bytes: [ 0xc2, 0x8f, 0x7f, 0x6c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldnp d2, d3, [x30, #-8]" + + - + input: + bytes: [ 0xe3, 0x17, 0x00, 0xac ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stnp q3, q5, [sp]" + + - + input: + bytes: [ 0xf1, 0xcf, 0x1f, 0xac ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "stnp q17, q19, [sp, #1008]" + + - + input: + bytes: [ 0x37, 0x74, 0x60, 0xac ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ldnp q23, q29, [x1, #-1024]" + + - + input: + bytes: [ 0x23, 0x3d, 0x10, 0x32 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "orr w3, w9, #0xffff0000" + + - + input: + bytes: [ 0x5f, 0x29, 0x03, 0x32 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "orr wsp, w10, #0xe00000ff" + + - + input: + bytes: [ 0x49, 0x25, 0x00, 0x32 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "orr w9, w10, #0x3ff" + + - + input: + bytes: [ 0xee, 0x81, 0x01, 0x12 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and w14, w15, #0x80008000" + + - + input: + bytes: [ 0xac, 0xad, 0x0a, 0x12 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and w12, w13, #0xffc3ffc3" + + - + input: + bytes: [ 0xeb, 0x87, 0x00, 0x12 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and w11, wzr, #0x30003" + + - + input: + bytes: [ 0xc3, 0xc8, 0x03, 0x52 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "eor w3, w6, #0xe0e0e0e0" + + - + input: + bytes: [ 0xff, 0xc7, 0x00, 0x52 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "eor wsp, wzr, #0x3030303" + + - + input: + bytes: [ 0x30, 0xc6, 0x01, 0x52 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "eor w16, w17, #0x81818181" + + - + input: + bytes: [ 0x5f, 0xe6, 0x02, 0x72 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tst w18, #0xcccccccc" + + - + input: + bytes: [ 0x93, 0xe6, 0x00, 0x72 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ands w19, w20, #0x33333333" + + - + input: + bytes: [ 0xd5, 0xe6, 0x01, 0x72 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ands w21, w22, #0x99999999" + + - + input: + bytes: [ 0x7f, 0xf0, 0x01, 0x72 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tst w3, #0xaaaaaaaa" + + - + input: + bytes: [ 0xff, 0xf3, 0x00, 0x72 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tst wzr, #0x55555555" + + - + input: + bytes: [ 0xa3, 0x84, 0x66, 0xd2 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "eor x3, x5, #0xffffffffc000000" + + - + input: + bytes: [ 0x49, 0xb9, 0x40, 0x92 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and x9, x10, #0x7fffffffffff" + + - + input: + bytes: [ 0x8b, 0x31, 0x41, 0xb2 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "orr x11, x12, #0x8000000000000fff" + + - + input: + bytes: [ 0x23, 0x3d, 0x10, 0xb2 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "orr x3, x9, #0xffff0000ffff0000" + + - + input: + bytes: [ 0x5f, 0x29, 0x03, 0xb2 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "orr sp, x10, #0xe00000ffe00000ff" + + - + input: + bytes: [ 0x49, 0x25, 0x00, 0xb2 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "orr x9, x10, #0x3ff000003ff" + + - + input: + bytes: [ 0xee, 0x81, 0x01, 0x92 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and x14, x15, #0x8000800080008000" + + - + input: + bytes: [ 0xac, 0xad, 0x0a, 0x92 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and x12, x13, #0xffc3ffc3ffc3ffc3" + + - + input: + bytes: [ 0xeb, 0x87, 0x00, 0x92 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and x11, xzr, #0x3000300030003" + + - + input: + bytes: [ 0xc3, 0xc8, 0x03, 0xd2 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "eor x3, x6, #0xe0e0e0e0e0e0e0e0" + + - + input: + bytes: [ 0xff, 0xc7, 0x00, 0xd2 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "eor sp, xzr, #0x303030303030303" + + - + input: + bytes: [ 0x30, 0xc6, 0x01, 0xd2 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "eor x16, x17, #0x8181818181818181" + + - + input: + bytes: [ 0x5f, 0xe6, 0x02, 0xf2 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tst x18, #0xcccccccccccccccc" + + - + input: + bytes: [ 0x93, 0xe6, 0x00, 0xf2 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ands x19, x20, #0x3333333333333333" + + - + input: + bytes: [ 0xd5, 0xe6, 0x01, 0xf2 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ands x21, x22, #0x9999999999999999" + + - + input: + bytes: [ 0x7f, 0xf0, 0x01, 0xf2 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tst x3, #0xaaaaaaaaaaaaaaaa" + + - + input: + bytes: [ 0xff, 0xf3, 0x00, 0xf2 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tst xzr, #0x5555555555555555" + + - + input: + bytes: [ 0xe3, 0x8f, 0x00, 0x32 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mov w3, #983055" + + - + input: + bytes: [ 0xea, 0xf3, 0x01, 0xb2 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mov x10, #-6148914691236517206" + + - + input: + bytes: [ 0x62, 0x78, 0x1e, 0x12 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and w2, w3, #0xfffffffd" + + - + input: + bytes: [ 0x20, 0x78, 0x1e, 0x32 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "orr w0, w1, #0xfffffffd" + + - + input: + bytes: [ 0x30, 0x76, 0x1d, 0x52 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "eor w16, w17, #0xfffffff9" + + - + input: + bytes: [ 0x93, 0x6e, 0x1c, 0x72 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ands w19, w20, #0xfffffff0" + + - + input: + bytes: [ 0xec, 0x02, 0x15, 0x0a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and w12, w23, w21" + + - + input: + bytes: [ 0xf0, 0x05, 0x01, 0x0a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and w16, w15, w1, lsl #1" + + - + input: + bytes: [ 0x89, 0x7c, 0x0a, 0x0a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and w9, w4, w10, lsl #31" + + - + input: + bytes: [ 0xc3, 0x03, 0x0b, 0x0a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and w3, w30, w11" + + - + input: + bytes: [ 0xa3, 0xfc, 0x07, 0x8a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and x3, x5, x7, lsl #63" + + - + input: + bytes: [ 0xc5, 0x11, 0x93, 0x8a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and x5, x14, x19, asr #4" + + - + input: + bytes: [ 0x23, 0x7e, 0xd3, 0x0a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and w3, w17, w19, ror #31" + + - + input: + bytes: [ 0x40, 0x44, 0x5f, 0x0a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and w0, w2, wzr, lsr #17" + + - + input: + bytes: [ 0xc3, 0x03, 0x8b, 0x0a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and w3, w30, w11, asr #0" + + - + input: + bytes: [ 0x9f, 0x00, 0x1a, 0x8a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and xzr, x4, x26" + + - + input: + bytes: [ 0xe3, 0x03, 0xd4, 0x0a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and w3, wzr, w20, ror #0" + + - + input: + bytes: [ 0x87, 0xfe, 0x9f, 0x8a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "and x7, x20, xzr, asr #63" + + - + input: + bytes: [ 0x8d, 0xbe, 0x2e, 0x8a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bic x13, x20, x14, lsl #47" + + - + input: + bytes: [ 0xe2, 0x00, 0x29, 0x0a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bic w2, w7, w9" + + - + input: + bytes: [ 0xe2, 0x7c, 0x80, 0x2a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "orr w2, w7, w0, asr #31" + + - + input: + bytes: [ 0x28, 0x31, 0x0a, 0xaa ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "orr x8, x9, x10, lsl #12" + + - + input: + bytes: [ 0xa3, 0x00, 0xa7, 0xaa ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "orn x3, x5, x7, asr #0" + + - + input: + bytes: [ 0xa2, 0x00, 0x3d, 0x2a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "orn w2, w5, w29" + + - + input: + bytes: [ 0xe7, 0x07, 0x09, 0x6a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ands w7, wzr, w9, lsl #1" + + - + input: + bytes: [ 0xa3, 0xfc, 0xd4, 0xea ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ands x3, x5, x20, ror #63" + + - + input: + bytes: [ 0xa3, 0x00, 0x27, 0x6a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bics w3, w5, w7" + + - + input: + bytes: [ 0xe3, 0x07, 0x23, 0xea ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bics x3, xzr, x3, lsl #1" + + - + input: + bytes: [ 0x7f, 0x7c, 0x07, 0x6a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tst w3, w7, lsl #31" + + - + input: + bytes: [ 0x5f, 0x00, 0x94, 0xea ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tst x2, x20, asr #0" + + - + input: + bytes: [ 0xe3, 0x03, 0x06, 0xaa ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mov x3, x6" + + - + input: + bytes: [ 0xe3, 0x03, 0x1f, 0xaa ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mov x3, xzr" + + - + input: + bytes: [ 0xff, 0x03, 0x02, 0x2a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mov wzr, w2" + + - + input: + bytes: [ 0xe3, 0x03, 0x05, 0x2a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mov w3, w5" + + - + input: + bytes: [ 0xe1, 0xff, 0x9f, 0x52 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mov w1, #65535" + + - + input: + bytes: [ 0x02, 0x00, 0xa0, 0x52 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "movz w2, #0, lsl #16" + + - + input: + bytes: [ 0x42, 0x9a, 0x80, 0x12 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mov w2, #-1235" + + - + input: + bytes: [ 0x42, 0x9a, 0xc0, 0xd2 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mov x2, #5299989643264" + + - + input: + bytes: [ 0x3f, 0x1c, 0xe2, 0xf2 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "movk xzr, #4321, lsl #48" + + - + input: + bytes: [ 0x1e, 0x00, 0x00, 0xb0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adrp x30, #4096" + + - + input: + bytes: [ 0x14, 0x00, 0x00, 0x10 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adr x20, #0" + + - + input: + bytes: [ 0xe9, 0xff, 0xff, 0x70 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adr x9, #-1" + + - + input: + bytes: [ 0xe5, 0xff, 0x7f, 0x70 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adr x5, #1048575" + + - + input: + bytes: [ 0xe9, 0xff, 0x7f, 0x70 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adr x9, #1048575" + + - + input: + bytes: [ 0x02, 0x00, 0x80, 0x10 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adr x2, #-1048576" + + - + input: + bytes: [ 0xe9, 0xff, 0x7f, 0xf0 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adrp x9, #4294963200" + + - + input: + bytes: [ 0x14, 0x00, 0x80, 0x90 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "adrp x20, #-4294967296" + + - + input: + bytes: [ 0x1f, 0x20, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0xff, 0x2f, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "hint #127" + + - + input: + bytes: [ 0x1f, 0x20, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x3f, 0x20, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "yield" + + - + input: + bytes: [ 0x5f, 0x20, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "wfe" + + - + input: + bytes: [ 0x7f, 0x20, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "wfi" + + - + input: + bytes: [ 0x9f, 0x20, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sev" + + - + input: + bytes: [ 0xbf, 0x20, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sevl" + + - + input: + bytes: [ 0xdf, 0x20, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dgh" + + - + input: + bytes: [ 0x5f, 0x3f, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "clrex" + + - + input: + bytes: [ 0x5f, 0x30, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "clrex #0" + + - + input: + bytes: [ 0x5f, 0x37, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "clrex #7" + + - + input: + bytes: [ 0x5f, 0x3f, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "clrex" + + - + input: + bytes: [ 0x9f, 0x30, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ssbb" + + - + input: + bytes: [ 0x9f, 0x34, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "pssbb" + + - + input: + bytes: [ 0x9f, 0x3c, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dfb" + + - + input: + bytes: [ 0x9f, 0x3f, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dsb sy" + + - + input: + bytes: [ 0x9f, 0x31, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dsb oshld" + + - + input: + bytes: [ 0x9f, 0x32, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dsb oshst" + + - + input: + bytes: [ 0x9f, 0x33, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dsb osh" + + - + input: + bytes: [ 0x9f, 0x35, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dsb nshld" + + - + input: + bytes: [ 0x9f, 0x36, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dsb nshst" + + - + input: + bytes: [ 0x9f, 0x37, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dsb nsh" + + - + input: + bytes: [ 0x9f, 0x39, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dsb ishld" + + - + input: + bytes: [ 0x9f, 0x3a, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dsb ishst" + + - + input: + bytes: [ 0x9f, 0x3b, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dsb ish" + + - + input: + bytes: [ 0x9f, 0x3d, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dsb ld" + + - + input: + bytes: [ 0x9f, 0x3e, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dsb st" + + - + input: + bytes: [ 0x9f, 0x3f, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dsb sy" + + - + input: + bytes: [ 0xbf, 0x30, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dmb #0" + + - + input: + bytes: [ 0xbf, 0x3c, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dmb #12" + + - + input: + bytes: [ 0xbf, 0x3f, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dmb sy" + + - + input: + bytes: [ 0xbf, 0x31, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dmb oshld" + + - + input: + bytes: [ 0xbf, 0x32, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dmb oshst" + + - + input: + bytes: [ 0xbf, 0x33, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dmb osh" + + - + input: + bytes: [ 0xbf, 0x35, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dmb nshld" + + - + input: + bytes: [ 0xbf, 0x36, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dmb nshst" + + - + input: + bytes: [ 0xbf, 0x37, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dmb nsh" + + - + input: + bytes: [ 0xbf, 0x39, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dmb ishld" + + - + input: + bytes: [ 0xbf, 0x3a, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dmb ishst" + + - + input: + bytes: [ 0xbf, 0x3b, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dmb ish" + + - + input: + bytes: [ 0xbf, 0x3d, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dmb ld" + + - + input: + bytes: [ 0xbf, 0x3e, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dmb st" + + - + input: + bytes: [ 0xbf, 0x3f, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dmb sy" + + - + input: + bytes: [ 0xdf, 0x3f, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "isb" + + - + input: + bytes: [ 0xdf, 0x3f, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "isb" + + - + input: + bytes: [ 0xdf, 0x3c, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "isb #12" + + - + input: + bytes: [ 0xbf, 0x40, 0x00, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SPSel, #0" + + - + input: + bytes: [ 0xdf, 0x4f, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DAIFSet, #15" + + - + input: + bytes: [ 0xff, 0x4c, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DAIFClr, #12" + + - + input: + bytes: [ 0xe5, 0x59, 0x0f, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sys #7, c5, c9, #7, x5" + + - + input: + bytes: [ 0x5f, 0xff, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sys #0, c15, c15, #2" + + - + input: + bytes: [ 0xe9, 0x59, 0x2f, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sysl x9, #7, c5, c9, #7" + + - + input: + bytes: [ 0x41, 0xff, 0x28, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sysl x1, #0, c15, c15, #2" + + - + input: + bytes: [ 0x1f, 0x71, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ic ialluis" + + - + input: + bytes: [ 0x1f, 0x75, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ic iallu" + + - + input: + bytes: [ 0x29, 0x75, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ic ivau, x9" + + - + input: + bytes: [ 0x2c, 0x74, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dc zva, x12" + + - + input: + bytes: [ 0x3f, 0x76, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dc ivac, xzr" + + - + input: + bytes: [ 0x42, 0x76, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dc isw, x2" + + - + input: + bytes: [ 0x29, 0x7a, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dc cvac, x9" + + - + input: + bytes: [ 0x4a, 0x7a, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dc csw, x10" + + - + input: + bytes: [ 0x20, 0x7b, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dc cvau, x0" + + - + input: + bytes: [ 0x23, 0x7e, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dc civac, x3" + + - + input: + bytes: [ 0x5e, 0x7e, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "dc cisw, x30" + + - + input: + bytes: [ 0x13, 0x78, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "at s1e1r, x19" + + - + input: + bytes: [ 0x13, 0x78, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "at s1e2r, x19" + + - + input: + bytes: [ 0x13, 0x78, 0x0e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "at s1e3r, x19" + + - + input: + bytes: [ 0x33, 0x78, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "at s1e1w, x19" + + - + input: + bytes: [ 0x33, 0x78, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "at s1e2w, x19" + + - + input: + bytes: [ 0x33, 0x78, 0x0e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "at s1e3w, x19" + + - + input: + bytes: [ 0x53, 0x78, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "at s1e0r, x19" + + - + input: + bytes: [ 0x73, 0x78, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "at s1e0w, x19" + + - + input: + bytes: [ 0x94, 0x78, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "at s12e1r, x20" + + - + input: + bytes: [ 0xb4, 0x78, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "at s12e1w, x20" + + - + input: + bytes: [ 0xd4, 0x78, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "at s12e0r, x20" + + - + input: + bytes: [ 0xf4, 0x78, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "at s12e0w, x20" + + - + input: + bytes: [ 0x24, 0x80, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi ipas2e1is, x4" + + - + input: + bytes: [ 0xa9, 0x80, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi ipas2le1is, x9" + + - + input: + bytes: [ 0x1f, 0x83, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vmalle1is" + + - + input: + bytes: [ 0x1f, 0x83, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi alle2is" + + - + input: + bytes: [ 0x1f, 0x83, 0x0e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi alle3is" + + - + input: + bytes: [ 0x21, 0x83, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vae1is, x1" + + - + input: + bytes: [ 0x22, 0x83, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vae2is, x2" + + - + input: + bytes: [ 0x23, 0x83, 0x0e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vae3is, x3" + + - + input: + bytes: [ 0x45, 0x83, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi aside1is, x5" + + - + input: + bytes: [ 0x69, 0x83, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vaae1is, x9" + + - + input: + bytes: [ 0x9f, 0x83, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi alle1is" + + - + input: + bytes: [ 0xaa, 0x83, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vale1is, x10" + + - + input: + bytes: [ 0xab, 0x83, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vale2is, x11" + + - + input: + bytes: [ 0xad, 0x83, 0x0e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vale3is, x13" + + - + input: + bytes: [ 0xdf, 0x83, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vmalls12e1is" + + - + input: + bytes: [ 0xee, 0x83, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vaale1is, x14" + + - + input: + bytes: [ 0x2f, 0x84, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi ipas2e1, x15" + + - + input: + bytes: [ 0xb0, 0x84, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi ipas2le1, x16" + + - + input: + bytes: [ 0x1f, 0x87, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vmalle1" + + - + input: + bytes: [ 0x1f, 0x87, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi alle2" + + - + input: + bytes: [ 0x1f, 0x87, 0x0e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi alle3" + + - + input: + bytes: [ 0x31, 0x87, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vae1, x17" + + - + input: + bytes: [ 0x32, 0x87, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vae2, x18" + + - + input: + bytes: [ 0x33, 0x87, 0x0e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vae3, x19" + + - + input: + bytes: [ 0x54, 0x87, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi aside1, x20" + + - + input: + bytes: [ 0x75, 0x87, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vaae1, x21" + + - + input: + bytes: [ 0x9f, 0x87, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi alle1" + + - + input: + bytes: [ 0xb6, 0x87, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vale1, x22" + + - + input: + bytes: [ 0xb7, 0x87, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vale2, x23" + + - + input: + bytes: [ 0xb8, 0x87, 0x0e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vale3, x24" + + - + input: + bytes: [ 0xdf, 0x87, 0x0c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vmalls12e1" + + - + input: + bytes: [ 0xf9, 0x87, 0x08, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "tlbi vaale1, x25" + + - + input: + bytes: [ 0x0c, 0x00, 0x12, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr TEECR32_EL1, x12" + + - + input: + bytes: [ 0x4c, 0x00, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr OSDTRRX_EL1, x12" + + - + input: + bytes: [ 0x0c, 0x02, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr MDCCINT_EL1, x12" + + - + input: + bytes: [ 0x4c, 0x02, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr MDSCR_EL1, x12" + + - + input: + bytes: [ 0x4c, 0x03, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr OSDTRTX_EL1, x12" + + - + input: + bytes: [ 0x0c, 0x04, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGDTR_EL0, x12" + + - + input: + bytes: [ 0x0c, 0x05, 0x13, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGDTRTX_EL0, x12" + + - + input: + bytes: [ 0x4c, 0x06, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr OSECCR_EL1, x12" + + - + input: + bytes: [ 0x0c, 0x07, 0x14, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGVCR32_EL2, x12" + + - + input: + bytes: [ 0x8c, 0x00, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBVR0_EL1, x12" + + - + input: + bytes: [ 0x8c, 0x01, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBVR1_EL1, x12" + + - + input: + bytes: [ 0x8c, 0x02, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBVR2_EL1, x12" + + - + input: + bytes: [ 0x8c, 0x03, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBVR3_EL1, x12" + + - + input: + bytes: [ 0x8c, 0x04, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBVR4_EL1, x12" + + - + input: + bytes: [ 0x8c, 0x05, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBVR5_EL1, x12" + + - + input: + bytes: [ 0x8c, 0x06, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBVR6_EL1, x12" + + - + input: + bytes: [ 0x8c, 0x07, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBVR7_EL1, x12" + + - + input: + bytes: [ 0x8c, 0x08, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBVR8_EL1, x12" + + - + input: + bytes: [ 0x8c, 0x09, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBVR9_EL1, x12" + + - + input: + bytes: [ 0x8c, 0x0a, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBVR10_EL1, x12" + + - + input: + bytes: [ 0x8c, 0x0b, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBVR11_EL1, x12" + + - + input: + bytes: [ 0x8c, 0x0c, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBVR12_EL1, x12" + + - + input: + bytes: [ 0x8c, 0x0d, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBVR13_EL1, x12" + + - + input: + bytes: [ 0x8c, 0x0e, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBVR14_EL1, x12" + + - + input: + bytes: [ 0x8c, 0x0f, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBVR15_EL1, x12" + + - + input: + bytes: [ 0xac, 0x00, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBCR0_EL1, x12" + + - + input: + bytes: [ 0xac, 0x01, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBCR1_EL1, x12" + + - + input: + bytes: [ 0xac, 0x02, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBCR2_EL1, x12" + + - + input: + bytes: [ 0xac, 0x03, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBCR3_EL1, x12" + + - + input: + bytes: [ 0xac, 0x04, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBCR4_EL1, x12" + + - + input: + bytes: [ 0xac, 0x05, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBCR5_EL1, x12" + + - + input: + bytes: [ 0xac, 0x06, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBCR6_EL1, x12" + + - + input: + bytes: [ 0xac, 0x07, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBCR7_EL1, x12" + + - + input: + bytes: [ 0xac, 0x08, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBCR8_EL1, x12" + + - + input: + bytes: [ 0xac, 0x09, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBCR9_EL1, x12" + + - + input: + bytes: [ 0xac, 0x0a, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBCR10_EL1, x12" + + - + input: + bytes: [ 0xac, 0x0b, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBCR11_EL1, x12" + + - + input: + bytes: [ 0xac, 0x0c, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBCR12_EL1, x12" + + - + input: + bytes: [ 0xac, 0x0d, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBCR13_EL1, x12" + + - + input: + bytes: [ 0xac, 0x0e, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBCR14_EL1, x12" + + - + input: + bytes: [ 0xac, 0x0f, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGBCR15_EL1, x12" + + - + input: + bytes: [ 0xcc, 0x00, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWVR0_EL1, x12" + + - + input: + bytes: [ 0xcc, 0x01, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWVR1_EL1, x12" + + - + input: + bytes: [ 0xcc, 0x02, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWVR2_EL1, x12" + + - + input: + bytes: [ 0xcc, 0x03, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWVR3_EL1, x12" + + - + input: + bytes: [ 0xcc, 0x04, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWVR4_EL1, x12" + + - + input: + bytes: [ 0xcc, 0x05, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWVR5_EL1, x12" + + - + input: + bytes: [ 0xcc, 0x06, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWVR6_EL1, x12" + + - + input: + bytes: [ 0xcc, 0x07, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWVR7_EL1, x12" + + - + input: + bytes: [ 0xcc, 0x08, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWVR8_EL1, x12" + + - + input: + bytes: [ 0xcc, 0x09, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWVR9_EL1, x12" + + - + input: + bytes: [ 0xcc, 0x0a, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWVR10_EL1, x12" + + - + input: + bytes: [ 0xcc, 0x0b, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWVR11_EL1, x12" + + - + input: + bytes: [ 0xcc, 0x0c, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWVR12_EL1, x12" + + - + input: + bytes: [ 0xcc, 0x0d, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWVR13_EL1, x12" + + - + input: + bytes: [ 0xcc, 0x0e, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWVR14_EL1, x12" + + - + input: + bytes: [ 0xcc, 0x0f, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWVR15_EL1, x12" + + - + input: + bytes: [ 0xec, 0x00, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWCR0_EL1, x12" + + - + input: + bytes: [ 0xec, 0x01, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWCR1_EL1, x12" + + - + input: + bytes: [ 0xec, 0x02, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWCR2_EL1, x12" + + - + input: + bytes: [ 0xec, 0x03, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWCR3_EL1, x12" + + - + input: + bytes: [ 0xec, 0x04, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWCR4_EL1, x12" + + - + input: + bytes: [ 0xec, 0x05, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWCR5_EL1, x12" + + - + input: + bytes: [ 0xec, 0x06, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWCR6_EL1, x12" + + - + input: + bytes: [ 0xec, 0x07, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWCR7_EL1, x12" + + - + input: + bytes: [ 0xec, 0x08, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWCR8_EL1, x12" + + - + input: + bytes: [ 0xec, 0x09, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWCR9_EL1, x12" + + - + input: + bytes: [ 0xec, 0x0a, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWCR10_EL1, x12" + + - + input: + bytes: [ 0xec, 0x0b, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWCR11_EL1, x12" + + - + input: + bytes: [ 0xec, 0x0c, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWCR12_EL1, x12" + + - + input: + bytes: [ 0xec, 0x0d, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWCR13_EL1, x12" + + - + input: + bytes: [ 0xec, 0x0e, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWCR14_EL1, x12" + + - + input: + bytes: [ 0xec, 0x0f, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGWCR15_EL1, x12" + + - + input: + bytes: [ 0x0c, 0x10, 0x12, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr TEEHBR32_EL1, x12" + + - + input: + bytes: [ 0x8c, 0x10, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr OSLAR_EL1, x12" + + - + input: + bytes: [ 0x8c, 0x13, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr OSDLR_EL1, x12" + + - + input: + bytes: [ 0x8c, 0x14, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGPRCR_EL1, x12" + + - + input: + bytes: [ 0xcc, 0x78, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGCLAIMSET_EL1, x12" + + - + input: + bytes: [ 0xcc, 0x79, 0x10, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DBGCLAIMCLR_EL1, x12" + + - + input: + bytes: [ 0x0c, 0x00, 0x1a, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CSSELR_EL1, x12" + + - + input: + bytes: [ 0x0c, 0x00, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr VPIDR_EL2, x12" + + - + input: + bytes: [ 0xac, 0x00, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr VMPIDR_EL2, x12" + + - + input: + bytes: [ 0x0c, 0x10, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SCTLR_EL1, x12" + + - + input: + bytes: [ 0x0c, 0x10, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SCTLR_EL2, x12" + + - + input: + bytes: [ 0x0c, 0x10, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SCTLR_EL3, x12" + + - + input: + bytes: [ 0x2c, 0x10, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr ACTLR_EL1, x12" + + - + input: + bytes: [ 0x2c, 0x10, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr ACTLR_EL2, x12" + + - + input: + bytes: [ 0x2c, 0x10, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr ACTLR_EL3, x12" + + - + input: + bytes: [ 0x4c, 0x10, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CPACR_EL1, x12" + + - + input: + bytes: [ 0x0c, 0x11, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr HCR_EL2, x12" + + - + input: + bytes: [ 0x0c, 0x11, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SCR_EL3, x12" + + - + input: + bytes: [ 0x2c, 0x11, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr MDCR_EL2, x12" + + - + input: + bytes: [ 0x2c, 0x11, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SDER32_EL3, x12" + + - + input: + bytes: [ 0x4c, 0x11, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CPTR_EL2, x12" + + - + input: + bytes: [ 0x4c, 0x11, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CPTR_EL3, x12" + + - + input: + bytes: [ 0x6c, 0x11, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr HSTR_EL2, x12" + + - + input: + bytes: [ 0xec, 0x11, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr HACR_EL2, x12" + + - + input: + bytes: [ 0x2c, 0x13, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr MDCR_EL3, x12" + + - + input: + bytes: [ 0x0c, 0x20, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr TTBR0_EL1, x12" + + - + input: + bytes: [ 0x0c, 0x20, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr TTBR0_EL2, x12" + + - + input: + bytes: [ 0x0c, 0x20, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr TTBR0_EL3, x12" + + - + input: + bytes: [ 0x2c, 0x20, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr TTBR1_EL1, x12" + + - + input: + bytes: [ 0x4c, 0x20, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr TCR_EL1, x12" + + - + input: + bytes: [ 0x4c, 0x20, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr TCR_EL2, x12" + + - + input: + bytes: [ 0x4c, 0x20, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr TCR_EL3, x12" + + - + input: + bytes: [ 0x0c, 0x21, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr VTTBR_EL2, x12" + + - + input: + bytes: [ 0x4c, 0x21, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr VTCR_EL2, x12" + + - + input: + bytes: [ 0x0c, 0x30, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DACR32_EL2, x12" + + - + input: + bytes: [ 0x0c, 0x40, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SPSR_EL1, x12" + + - + input: + bytes: [ 0x0c, 0x40, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SPSR_EL2, x12" + + - + input: + bytes: [ 0x0c, 0x40, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SPSR_EL3, x12" + + - + input: + bytes: [ 0x2c, 0x40, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr ELR_EL1, x12" + + - + input: + bytes: [ 0x2c, 0x40, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr ELR_EL2, x12" + + - + input: + bytes: [ 0x2c, 0x40, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr ELR_EL3, x12" + + - + input: + bytes: [ 0x0c, 0x41, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SP_EL0, x12" + + - + input: + bytes: [ 0x0c, 0x41, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SP_EL1, x12" + + - + input: + bytes: [ 0x0c, 0x41, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SP_EL2, x12" + + - + input: + bytes: [ 0x0c, 0x42, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SPSel, x12" + + - + input: + bytes: [ 0x0c, 0x42, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr NZCV, x12" + + - + input: + bytes: [ 0x2c, 0x42, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DAIF, x12" + + - + input: + bytes: [ 0x0c, 0x43, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SPSR_irq, x12" + + - + input: + bytes: [ 0x2c, 0x43, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SPSR_abt, x12" + + - + input: + bytes: [ 0x4c, 0x43, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SPSR_und, x12" + + - + input: + bytes: [ 0x6c, 0x43, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SPSR_fiq, x12" + + - + input: + bytes: [ 0x0c, 0x44, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr FPCR, x12" + + - + input: + bytes: [ 0x2c, 0x44, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr FPSR, x12" + + - + input: + bytes: [ 0x0c, 0x45, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DSPSR_EL0, x12" + + - + input: + bytes: [ 0x2c, 0x45, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr DLR_EL0, x12" + + - + input: + bytes: [ 0x2c, 0x50, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr IFSR32_EL2, x12" + + - + input: + bytes: [ 0x0c, 0x51, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr AFSR0_EL1, x12" + + - + input: + bytes: [ 0x0c, 0x51, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr AFSR0_EL2, x12" + + - + input: + bytes: [ 0x0c, 0x51, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr AFSR0_EL3, x12" + + - + input: + bytes: [ 0x2c, 0x51, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr AFSR1_EL1, x12" + + - + input: + bytes: [ 0x2c, 0x51, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr AFSR1_EL2, x12" + + - + input: + bytes: [ 0x2c, 0x51, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr AFSR1_EL3, x12" + + - + input: + bytes: [ 0x0c, 0x52, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr ESR_EL1, x12" + + - + input: + bytes: [ 0x0c, 0x52, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr ESR_EL2, x12" + + - + input: + bytes: [ 0x0c, 0x52, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr ESR_EL3, x12" + + - + input: + bytes: [ 0x0c, 0x53, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr FPEXC32_EL2, x12" + + - + input: + bytes: [ 0x0c, 0x60, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr FAR_EL1, x12" + + - + input: + bytes: [ 0x0c, 0x60, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr FAR_EL2, x12" + + - + input: + bytes: [ 0x0c, 0x60, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr FAR_EL3, x12" + + - + input: + bytes: [ 0x8c, 0x60, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr HPFAR_EL2, x12" + + - + input: + bytes: [ 0x0c, 0x74, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PAR_EL1, x12" + + - + input: + bytes: [ 0x0c, 0x9c, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMCR_EL0, x12" + + - + input: + bytes: [ 0x2c, 0x9c, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMCNTENSET_EL0, x12" + + - + input: + bytes: [ 0x4c, 0x9c, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMCNTENCLR_EL0, x12" + + - + input: + bytes: [ 0x6c, 0x9c, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMOVSCLR_EL0, x12" + + - + input: + bytes: [ 0xac, 0x9c, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMSELR_EL0, x12" + + - + input: + bytes: [ 0x0c, 0x9d, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMCCNTR_EL0, x12" + + - + input: + bytes: [ 0x2c, 0x9d, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMXEVTYPER_EL0, x12" + + - + input: + bytes: [ 0x4c, 0x9d, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMXEVCNTR_EL0, x12" + + - + input: + bytes: [ 0x0c, 0x9e, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMUSERENR_EL0, x12" + + - + input: + bytes: [ 0x2c, 0x9e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMINTENSET_EL1, x12" + + - + input: + bytes: [ 0x4c, 0x9e, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMINTENCLR_EL1, x12" + + - + input: + bytes: [ 0x6c, 0x9e, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMOVSSET_EL0, x12" + + - + input: + bytes: [ 0x0c, 0xa2, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr MAIR_EL1, x12" + + - + input: + bytes: [ 0x0c, 0xa2, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr MAIR_EL2, x12" + + - + input: + bytes: [ 0x0c, 0xa2, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr MAIR_EL3, x12" + + - + input: + bytes: [ 0x0c, 0xa3, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr AMAIR_EL1, x12" + + - + input: + bytes: [ 0x0c, 0xa3, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr AMAIR_EL2, x12" + + - + input: + bytes: [ 0x0c, 0xa3, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr AMAIR_EL3, x12" + + - + input: + bytes: [ 0x0c, 0xc0, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr VBAR_EL1, x12" + + - + input: + bytes: [ 0x0c, 0xc0, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr VBAR_EL2, x12" + + - + input: + bytes: [ 0x0c, 0xc0, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr VBAR_EL3, x12" + + - + input: + bytes: [ 0x4c, 0xc0, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr RMR_EL1, x12" + + - + input: + bytes: [ 0x4c, 0xc0, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr RMR_EL2, x12" + + - + input: + bytes: [ 0x4c, 0xc0, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr RMR_EL3, x12" + + - + input: + bytes: [ 0x2c, 0xd0, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CONTEXTIDR_EL1, x12" + + - + input: + bytes: [ 0x4c, 0xd0, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr TPIDR_EL0, x12" + + - + input: + bytes: [ 0x4c, 0xd0, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr TPIDR_EL2, x12" + + - + input: + bytes: [ 0x4c, 0xd0, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr TPIDR_EL3, x12" + + - + input: + bytes: [ 0x6c, 0xd0, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr TPIDRRO_EL0, x12" + + - + input: + bytes: [ 0x8c, 0xd0, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr TPIDR_EL1, x12" + + - + input: + bytes: [ 0x0c, 0xe0, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CNTFRQ_EL0, x12" + + - + input: + bytes: [ 0x6c, 0xe0, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CNTVOFF_EL2, x12" + + - + input: + bytes: [ 0x0c, 0xe1, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CNTKCTL_EL1, x12" + + - + input: + bytes: [ 0x0c, 0xe1, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CNTHCTL_EL2, x12" + + - + input: + bytes: [ 0x0c, 0xe2, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CNTP_TVAL_EL0, x12" + + - + input: + bytes: [ 0x0c, 0xe2, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CNTHP_TVAL_EL2, x12" + + - + input: + bytes: [ 0x0c, 0xe2, 0x1f, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CNTPS_TVAL_EL1, x12" + + - + input: + bytes: [ 0x2c, 0xe2, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CNTP_CTL_EL0, x12" + + - + input: + bytes: [ 0x2c, 0xe2, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CNTHP_CTL_EL2, x12" + + - + input: + bytes: [ 0x2c, 0xe2, 0x1f, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CNTPS_CTL_EL1, x12" + + - + input: + bytes: [ 0x4c, 0xe2, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CNTP_CVAL_EL0, x12" + + - + input: + bytes: [ 0x4c, 0xe2, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CNTHP_CVAL_EL2, x12" + + - + input: + bytes: [ 0x4c, 0xe2, 0x1f, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CNTPS_CVAL_EL1, x12" + + - + input: + bytes: [ 0x0c, 0xe3, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CNTV_TVAL_EL0, x12" + + - + input: + bytes: [ 0x2c, 0xe3, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CNTV_CTL_EL0, x12" + + - + input: + bytes: [ 0x4c, 0xe3, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr CNTV_CVAL_EL0, x12" + + - + input: + bytes: [ 0x0c, 0xe8, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR0_EL0, x12" + + - + input: + bytes: [ 0x2c, 0xe8, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR1_EL0, x12" + + - + input: + bytes: [ 0x4c, 0xe8, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR2_EL0, x12" + + - + input: + bytes: [ 0x6c, 0xe8, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR3_EL0, x12" + + - + input: + bytes: [ 0x8c, 0xe8, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR4_EL0, x12" + + - + input: + bytes: [ 0xac, 0xe8, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR5_EL0, x12" + + - + input: + bytes: [ 0xcc, 0xe8, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR6_EL0, x12" + + - + input: + bytes: [ 0xec, 0xe8, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR7_EL0, x12" + + - + input: + bytes: [ 0x0c, 0xe9, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR8_EL0, x12" + + - + input: + bytes: [ 0x2c, 0xe9, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR9_EL0, x12" + + - + input: + bytes: [ 0x4c, 0xe9, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR10_EL0, x12" + + - + input: + bytes: [ 0x6c, 0xe9, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR11_EL0, x12" + + - + input: + bytes: [ 0x8c, 0xe9, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR12_EL0, x12" + + - + input: + bytes: [ 0xac, 0xe9, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR13_EL0, x12" + + - + input: + bytes: [ 0xcc, 0xe9, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR14_EL0, x12" + + - + input: + bytes: [ 0xec, 0xe9, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR15_EL0, x12" + + - + input: + bytes: [ 0x0c, 0xea, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR16_EL0, x12" + + - + input: + bytes: [ 0x2c, 0xea, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR17_EL0, x12" + + - + input: + bytes: [ 0x4c, 0xea, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR18_EL0, x12" + + - + input: + bytes: [ 0x6c, 0xea, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR19_EL0, x12" + + - + input: + bytes: [ 0x8c, 0xea, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR20_EL0, x12" + + - + input: + bytes: [ 0xac, 0xea, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR21_EL0, x12" + + - + input: + bytes: [ 0xcc, 0xea, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR22_EL0, x12" + + - + input: + bytes: [ 0xec, 0xea, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR23_EL0, x12" + + - + input: + bytes: [ 0x0c, 0xeb, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR24_EL0, x12" + + - + input: + bytes: [ 0x2c, 0xeb, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR25_EL0, x12" + + - + input: + bytes: [ 0x4c, 0xeb, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR26_EL0, x12" + + - + input: + bytes: [ 0x6c, 0xeb, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR27_EL0, x12" + + - + input: + bytes: [ 0x8c, 0xeb, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR28_EL0, x12" + + - + input: + bytes: [ 0xac, 0xeb, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR29_EL0, x12" + + - + input: + bytes: [ 0xcc, 0xeb, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVCNTR30_EL0, x12" + + - + input: + bytes: [ 0xec, 0xef, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMCCFILTR_EL0, x12" + + - + input: + bytes: [ 0x0c, 0xec, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER0_EL0, x12" + + - + input: + bytes: [ 0x2c, 0xec, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER1_EL0, x12" + + - + input: + bytes: [ 0x4c, 0xec, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER2_EL0, x12" + + - + input: + bytes: [ 0x6c, 0xec, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER3_EL0, x12" + + - + input: + bytes: [ 0x8c, 0xec, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER4_EL0, x12" + + - + input: + bytes: [ 0xac, 0xec, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER5_EL0, x12" + + - + input: + bytes: [ 0xcc, 0xec, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER6_EL0, x12" + + - + input: + bytes: [ 0xec, 0xec, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER7_EL0, x12" + + - + input: + bytes: [ 0x0c, 0xed, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER8_EL0, x12" + + - + input: + bytes: [ 0x2c, 0xed, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER9_EL0, x12" + + - + input: + bytes: [ 0x4c, 0xed, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER10_EL0, x12" + + - + input: + bytes: [ 0x6c, 0xed, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER11_EL0, x12" + + - + input: + bytes: [ 0x8c, 0xed, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER12_EL0, x12" + + - + input: + bytes: [ 0xac, 0xed, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER13_EL0, x12" + + - + input: + bytes: [ 0xcc, 0xed, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER14_EL0, x12" + + - + input: + bytes: [ 0xec, 0xed, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER15_EL0, x12" + + - + input: + bytes: [ 0x0c, 0xee, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER16_EL0, x12" + + - + input: + bytes: [ 0x2c, 0xee, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER17_EL0, x12" + + - + input: + bytes: [ 0x4c, 0xee, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER18_EL0, x12" + + - + input: + bytes: [ 0x6c, 0xee, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER19_EL0, x12" + + - + input: + bytes: [ 0x8c, 0xee, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER20_EL0, x12" + + - + input: + bytes: [ 0xac, 0xee, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER21_EL0, x12" + + - + input: + bytes: [ 0xcc, 0xee, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER22_EL0, x12" + + - + input: + bytes: [ 0xec, 0xee, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER23_EL0, x12" + + - + input: + bytes: [ 0x0c, 0xef, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER24_EL0, x12" + + - + input: + bytes: [ 0x2c, 0xef, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER25_EL0, x12" + + - + input: + bytes: [ 0x4c, 0xef, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER26_EL0, x12" + + - + input: + bytes: [ 0x6c, 0xef, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER27_EL0, x12" + + - + input: + bytes: [ 0x8c, 0xef, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER28_EL0, x12" + + - + input: + bytes: [ 0xac, 0xef, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER29_EL0, x12" + + - + input: + bytes: [ 0xcc, 0xef, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PMEVTYPER30_EL0, x12" + + - + input: + bytes: [ 0x2c, 0xa3, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr AMAIR2_EL1, x12" + + - + input: + bytes: [ 0x2c, 0xa3, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr AMAIR2_EL12, x12" + + - + input: + bytes: [ 0x2c, 0xa3, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr AMAIR2_EL2, x12" + + - + input: + bytes: [ 0x2c, 0xa3, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr AMAIR2_EL3, x12" + + - + input: + bytes: [ 0x2c, 0xa2, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr MAIR2_EL1, x12" + + - + input: + bytes: [ 0x2c, 0xa2, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr MAIR2_EL12, x12" + + - + input: + bytes: [ 0x2c, 0xa1, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr MAIR2_EL2, x12" + + - + input: + bytes: [ 0x2c, 0xa1, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr MAIR2_EL3, x12" + + - + input: + bytes: [ 0x4c, 0xa2, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PIRE0_EL1, x12" + + - + input: + bytes: [ 0x4c, 0xa2, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PIRE0_EL12, x12" + + - + input: + bytes: [ 0x4c, 0xa2, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PIRE0_EL2, x12" + + - + input: + bytes: [ 0x6c, 0xa2, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PIR_EL1, x12" + + - + input: + bytes: [ 0x6c, 0xa2, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PIR_EL12, x12" + + - + input: + bytes: [ 0x6c, 0xa2, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PIR_EL2, x12" + + - + input: + bytes: [ 0x6c, 0xa2, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr PIR_EL3, x12" + + - + input: + bytes: [ 0xac, 0xa2, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr S2PIR_EL2, x12" + + - + input: + bytes: [ 0x8c, 0xa2, 0x1b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr POR_EL0, x12" + + - + input: + bytes: [ 0x8c, 0xa2, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr POR_EL1, x12" + + - + input: + bytes: [ 0x8c, 0xa2, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr POR_EL12, x12" + + - + input: + bytes: [ 0x8c, 0xa2, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr POR_EL2, x12" + + - + input: + bytes: [ 0x8c, 0xa2, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr POR_EL3, x12" + + - + input: + bytes: [ 0xac, 0xa2, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr S2POR_EL1, x12" + + - + input: + bytes: [ 0x6c, 0x10, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SCTLR2_EL1, x12" + + - + input: + bytes: [ 0x6c, 0x10, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SCTLR2_EL12, x12" + + - + input: + bytes: [ 0x6c, 0x10, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SCTLR2_EL2, x12" + + - + input: + bytes: [ 0x6c, 0x10, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr SCTLR2_EL3, x12" + + - + input: + bytes: [ 0x6c, 0x20, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr TCR2_EL1, x12" + + - + input: + bytes: [ 0x6c, 0x20, 0x1d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr TCR2_EL12, x12" + + - + input: + bytes: [ 0x6c, 0x20, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr TCR2_EL2, x12" + + - + input: + bytes: [ 0x09, 0x00, 0x32, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, TEECR32_EL1" + + - + input: + bytes: [ 0x49, 0x00, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, OSDTRRX_EL1" + + - + input: + bytes: [ 0x09, 0x01, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, MDCCSR_EL0" + + - + input: + bytes: [ 0x09, 0x02, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, MDCCINT_EL1" + + - + input: + bytes: [ 0x49, 0x02, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, MDSCR_EL1" + + - + input: + bytes: [ 0x49, 0x03, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, OSDTRTX_EL1" + + - + input: + bytes: [ 0x09, 0x04, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGDTR_EL0" + + - + input: + bytes: [ 0x09, 0x05, 0x33, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGDTRRX_EL0" + + - + input: + bytes: [ 0x49, 0x06, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, OSECCR_EL1" + + - + input: + bytes: [ 0x09, 0x07, 0x34, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGVCR32_EL2" + + - + input: + bytes: [ 0x89, 0x00, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBVR0_EL1" + + - + input: + bytes: [ 0x89, 0x01, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBVR1_EL1" + + - + input: + bytes: [ 0x89, 0x02, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBVR2_EL1" + + - + input: + bytes: [ 0x89, 0x03, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBVR3_EL1" + + - + input: + bytes: [ 0x89, 0x04, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBVR4_EL1" + + - + input: + bytes: [ 0x89, 0x05, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBVR5_EL1" + + - + input: + bytes: [ 0x89, 0x06, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBVR6_EL1" + + - + input: + bytes: [ 0x89, 0x07, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBVR7_EL1" + + - + input: + bytes: [ 0x89, 0x08, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBVR8_EL1" + + - + input: + bytes: [ 0x89, 0x09, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBVR9_EL1" + + - + input: + bytes: [ 0x89, 0x0a, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBVR10_EL1" + + - + input: + bytes: [ 0x89, 0x0b, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBVR11_EL1" + + - + input: + bytes: [ 0x89, 0x0c, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBVR12_EL1" + + - + input: + bytes: [ 0x89, 0x0d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBVR13_EL1" + + - + input: + bytes: [ 0x89, 0x0e, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBVR14_EL1" + + - + input: + bytes: [ 0x89, 0x0f, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBVR15_EL1" + + - + input: + bytes: [ 0xa9, 0x00, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBCR0_EL1" + + - + input: + bytes: [ 0xa9, 0x01, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBCR1_EL1" + + - + input: + bytes: [ 0xa9, 0x02, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBCR2_EL1" + + - + input: + bytes: [ 0xa9, 0x03, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBCR3_EL1" + + - + input: + bytes: [ 0xa9, 0x04, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBCR4_EL1" + + - + input: + bytes: [ 0xa9, 0x05, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBCR5_EL1" + + - + input: + bytes: [ 0xa9, 0x06, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBCR6_EL1" + + - + input: + bytes: [ 0xa9, 0x07, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBCR7_EL1" + + - + input: + bytes: [ 0xa9, 0x08, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBCR8_EL1" + + - + input: + bytes: [ 0xa9, 0x09, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBCR9_EL1" + + - + input: + bytes: [ 0xa9, 0x0a, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBCR10_EL1" + + - + input: + bytes: [ 0xa9, 0x0b, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBCR11_EL1" + + - + input: + bytes: [ 0xa9, 0x0c, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBCR12_EL1" + + - + input: + bytes: [ 0xa9, 0x0d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBCR13_EL1" + + - + input: + bytes: [ 0xa9, 0x0e, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBCR14_EL1" + + - + input: + bytes: [ 0xa9, 0x0f, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGBCR15_EL1" + + - + input: + bytes: [ 0xc9, 0x00, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWVR0_EL1" + + - + input: + bytes: [ 0xc9, 0x01, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWVR1_EL1" + + - + input: + bytes: [ 0xc9, 0x02, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWVR2_EL1" + + - + input: + bytes: [ 0xc9, 0x03, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWVR3_EL1" + + - + input: + bytes: [ 0xc9, 0x04, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWVR4_EL1" + + - + input: + bytes: [ 0xc9, 0x05, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWVR5_EL1" + + - + input: + bytes: [ 0xc9, 0x06, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWVR6_EL1" + + - + input: + bytes: [ 0xc9, 0x07, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWVR7_EL1" + + - + input: + bytes: [ 0xc9, 0x08, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWVR8_EL1" + + - + input: + bytes: [ 0xc9, 0x09, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWVR9_EL1" + + - + input: + bytes: [ 0xc9, 0x0a, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWVR10_EL1" + + - + input: + bytes: [ 0xc9, 0x0b, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWVR11_EL1" + + - + input: + bytes: [ 0xc9, 0x0c, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWVR12_EL1" + + - + input: + bytes: [ 0xc9, 0x0d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWVR13_EL1" + + - + input: + bytes: [ 0xc9, 0x0e, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWVR14_EL1" + + - + input: + bytes: [ 0xc9, 0x0f, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWVR15_EL1" + + - + input: + bytes: [ 0xe9, 0x00, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWCR0_EL1" + + - + input: + bytes: [ 0xe9, 0x01, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWCR1_EL1" + + - + input: + bytes: [ 0xe9, 0x02, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWCR2_EL1" + + - + input: + bytes: [ 0xe9, 0x03, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWCR3_EL1" + + - + input: + bytes: [ 0xe9, 0x04, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWCR4_EL1" + + - + input: + bytes: [ 0xe9, 0x05, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWCR5_EL1" + + - + input: + bytes: [ 0xe9, 0x06, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWCR6_EL1" + + - + input: + bytes: [ 0xe9, 0x07, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWCR7_EL1" + + - + input: + bytes: [ 0xe9, 0x08, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWCR8_EL1" + + - + input: + bytes: [ 0xe9, 0x09, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWCR9_EL1" + + - + input: + bytes: [ 0xe9, 0x0a, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWCR10_EL1" + + - + input: + bytes: [ 0xe9, 0x0b, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWCR11_EL1" + + - + input: + bytes: [ 0xe9, 0x0c, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWCR12_EL1" + + - + input: + bytes: [ 0xe9, 0x0d, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWCR13_EL1" + + - + input: + bytes: [ 0xe9, 0x0e, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWCR14_EL1" + + - + input: + bytes: [ 0xe9, 0x0f, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGWCR15_EL1" + + - + input: + bytes: [ 0x09, 0x10, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, MDRAR_EL1" + + - + input: + bytes: [ 0x09, 0x10, 0x32, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, TEEHBR32_EL1" + + - + input: + bytes: [ 0x89, 0x11, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, OSLSR_EL1" + + - + input: + bytes: [ 0x89, 0x13, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, OSDLR_EL1" + + - + input: + bytes: [ 0x89, 0x14, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGPRCR_EL1" + + - + input: + bytes: [ 0xc9, 0x78, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGCLAIMSET_EL1" + + - + input: + bytes: [ 0xc9, 0x79, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGCLAIMCLR_EL1" + + - + input: + bytes: [ 0xc9, 0x7e, 0x30, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DBGAUTHSTATUS_EL1" + + - + input: + bytes: [ 0x09, 0x00, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, MIDR_EL1" + + - + input: + bytes: [ 0x09, 0x00, 0x39, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CCSIDR_EL1" + + - + input: + bytes: [ 0x09, 0x00, 0x3a, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CSSELR_EL1" + + - + input: + bytes: [ 0x09, 0x00, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, VPIDR_EL2" + + - + input: + bytes: [ 0x29, 0x00, 0x39, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CLIDR_EL1" + + - + input: + bytes: [ 0x29, 0x00, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CTR_EL0" + + - + input: + bytes: [ 0xa9, 0x00, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, MPIDR_EL1" + + - + input: + bytes: [ 0xa9, 0x00, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, VMPIDR_EL2" + + - + input: + bytes: [ 0xc9, 0x00, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, REVIDR_EL1" + + - + input: + bytes: [ 0xe9, 0x00, 0x39, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, AIDR_EL1" + + - + input: + bytes: [ 0xe9, 0x00, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DCZID_EL0" + + - + input: + bytes: [ 0x09, 0x01, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_PFR0_EL1" + + - + input: + bytes: [ 0x29, 0x01, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_PFR1_EL1" + + - + input: + bytes: [ 0x49, 0x01, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_DFR0_EL1" + + - + input: + bytes: [ 0xa9, 0x03, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_DFR1_EL1" + + - + input: + bytes: [ 0x69, 0x01, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_AFR0_EL1" + + - + input: + bytes: [ 0x89, 0x01, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_MMFR0_EL1" + + - + input: + bytes: [ 0xa9, 0x01, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_MMFR1_EL1" + + - + input: + bytes: [ 0xc9, 0x01, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_MMFR2_EL1" + + - + input: + bytes: [ 0xe9, 0x01, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_MMFR3_EL1" + + - + input: + bytes: [ 0xc9, 0x02, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_MMFR4_EL1" + + - + input: + bytes: [ 0xc9, 0x03, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_MMFR5_EL1" + + - + input: + bytes: [ 0x09, 0x02, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_ISAR0_EL1" + + - + input: + bytes: [ 0x29, 0x02, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_ISAR1_EL1" + + - + input: + bytes: [ 0x49, 0x02, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_ISAR2_EL1" + + - + input: + bytes: [ 0x69, 0x02, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_ISAR3_EL1" + + - + input: + bytes: [ 0x89, 0x02, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_ISAR4_EL1" + + - + input: + bytes: [ 0xa9, 0x02, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_ISAR5_EL1" + + - + input: + bytes: [ 0x09, 0x03, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, MVFR0_EL1" + + - + input: + bytes: [ 0x29, 0x03, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, MVFR1_EL1" + + - + input: + bytes: [ 0x49, 0x03, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, MVFR2_EL1" + + - + input: + bytes: [ 0x09, 0x04, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_AA64PFR0_EL1" + + - + input: + bytes: [ 0x29, 0x04, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_AA64PFR1_EL1" + + - + input: + bytes: [ 0x49, 0x04, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_AA64PFR2_EL1" + + - + input: + bytes: [ 0x09, 0x05, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_AA64DFR0_EL1" + + - + input: + bytes: [ 0x29, 0x05, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_AA64DFR1_EL1" + + - + input: + bytes: [ 0x49, 0x05, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_AA64DFR2_EL1" + + - + input: + bytes: [ 0x89, 0x05, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_AA64AFR0_EL1" + + - + input: + bytes: [ 0xa9, 0x05, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_AA64AFR1_EL1" + + - + input: + bytes: [ 0x09, 0x06, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_AA64ISAR0_EL1" + + - + input: + bytes: [ 0x29, 0x06, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_AA64ISAR1_EL1" + + - + input: + bytes: [ 0x49, 0x06, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_AA64ISAR2_EL1" + + - + input: + bytes: [ 0x69, 0x06, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_AA64ISAR3_EL1" + + - + input: + bytes: [ 0x09, 0x07, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_AA64MMFR0_EL1" + + - + input: + bytes: [ 0x29, 0x07, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_AA64MMFR1_EL1" + + - + input: + bytes: [ 0x49, 0x07, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_AA64MMFR2_EL1" + + - + input: + bytes: [ 0x69, 0x07, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_AA64MMFR3_EL1" + + - + input: + bytes: [ 0x89, 0x07, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ID_AA64MMFR4_EL1" + + - + input: + bytes: [ 0x09, 0x10, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SCTLR_EL1" + + - + input: + bytes: [ 0x09, 0x10, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SCTLR_EL2" + + - + input: + bytes: [ 0x09, 0x10, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SCTLR_EL3" + + - + input: + bytes: [ 0x29, 0x10, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ACTLR_EL1" + + - + input: + bytes: [ 0x29, 0x10, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ACTLR_EL2" + + - + input: + bytes: [ 0x29, 0x10, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ACTLR_EL3" + + - + input: + bytes: [ 0x49, 0x10, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CPACR_EL1" + + - + input: + bytes: [ 0x09, 0x11, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, HCR_EL2" + + - + input: + bytes: [ 0x09, 0x11, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SCR_EL3" + + - + input: + bytes: [ 0x29, 0x11, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, MDCR_EL2" + + - + input: + bytes: [ 0x29, 0x11, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SDER32_EL3" + + - + input: + bytes: [ 0x49, 0x11, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CPTR_EL2" + + - + input: + bytes: [ 0x49, 0x11, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CPTR_EL3" + + - + input: + bytes: [ 0x69, 0x11, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, HSTR_EL2" + + - + input: + bytes: [ 0xe9, 0x11, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, HACR_EL2" + + - + input: + bytes: [ 0x29, 0x13, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, MDCR_EL3" + + - + input: + bytes: [ 0x09, 0x20, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, TTBR0_EL1" + + - + input: + bytes: [ 0x09, 0x20, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, TTBR0_EL2" + + - + input: + bytes: [ 0x09, 0x20, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, TTBR0_EL3" + + - + input: + bytes: [ 0x29, 0x20, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, TTBR1_EL1" + + - + input: + bytes: [ 0x49, 0x20, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, TCR_EL1" + + - + input: + bytes: [ 0x49, 0x20, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, TCR_EL2" + + - + input: + bytes: [ 0x49, 0x20, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, TCR_EL3" + + - + input: + bytes: [ 0x09, 0x21, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, VTTBR_EL2" + + - + input: + bytes: [ 0x49, 0x21, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, VTCR_EL2" + + - + input: + bytes: [ 0x09, 0x30, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DACR32_EL2" + + - + input: + bytes: [ 0x09, 0x40, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SPSR_EL1" + + - + input: + bytes: [ 0x09, 0x40, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SPSR_EL2" + + - + input: + bytes: [ 0x09, 0x40, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SPSR_EL3" + + - + input: + bytes: [ 0x29, 0x40, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ELR_EL1" + + - + input: + bytes: [ 0x29, 0x40, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ELR_EL2" + + - + input: + bytes: [ 0x29, 0x40, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ELR_EL3" + + - + input: + bytes: [ 0x09, 0x41, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SP_EL0" + + - + input: + bytes: [ 0x09, 0x41, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SP_EL1" + + - + input: + bytes: [ 0x09, 0x41, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SP_EL2" + + - + input: + bytes: [ 0x09, 0x42, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SPSel" + + - + input: + bytes: [ 0x09, 0x42, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, NZCV" + + - + input: + bytes: [ 0x29, 0x42, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DAIF" + + - + input: + bytes: [ 0x49, 0x42, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CurrentEL" + + - + input: + bytes: [ 0x09, 0x43, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SPSR_irq" + + - + input: + bytes: [ 0x29, 0x43, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SPSR_abt" + + - + input: + bytes: [ 0x49, 0x43, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SPSR_und" + + - + input: + bytes: [ 0x69, 0x43, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SPSR_fiq" + + - + input: + bytes: [ 0x09, 0x44, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, FPCR" + + - + input: + bytes: [ 0x29, 0x44, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, FPSR" + + - + input: + bytes: [ 0x09, 0x45, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DSPSR_EL0" + + - + input: + bytes: [ 0x29, 0x45, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, DLR_EL0" + + - + input: + bytes: [ 0x29, 0x50, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, IFSR32_EL2" + + - + input: + bytes: [ 0x09, 0x51, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, AFSR0_EL1" + + - + input: + bytes: [ 0x09, 0x51, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, AFSR0_EL2" + + - + input: + bytes: [ 0x09, 0x51, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, AFSR0_EL3" + + - + input: + bytes: [ 0x29, 0x51, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, AFSR1_EL1" + + - + input: + bytes: [ 0x29, 0x51, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, AFSR1_EL2" + + - + input: + bytes: [ 0x29, 0x51, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, AFSR1_EL3" + + - + input: + bytes: [ 0x09, 0x52, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ESR_EL1" + + - + input: + bytes: [ 0x09, 0x52, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ESR_EL2" + + - + input: + bytes: [ 0x09, 0x52, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ESR_EL3" + + - + input: + bytes: [ 0x09, 0x53, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, FPEXC32_EL2" + + - + input: + bytes: [ 0x09, 0x60, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, FAR_EL1" + + - + input: + bytes: [ 0x09, 0x60, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, FAR_EL2" + + - + input: + bytes: [ 0x09, 0x60, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, FAR_EL3" + + - + input: + bytes: [ 0x89, 0x60, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, HPFAR_EL2" + + - + input: + bytes: [ 0x09, 0x74, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PAR_EL1" + + - + input: + bytes: [ 0x09, 0x9c, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMCR_EL0" + + - + input: + bytes: [ 0x29, 0x9c, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMCNTENSET_EL0" + + - + input: + bytes: [ 0x49, 0x9c, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMCNTENCLR_EL0" + + - + input: + bytes: [ 0x69, 0x9c, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMOVSCLR_EL0" + + - + input: + bytes: [ 0xa9, 0x9c, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMSELR_EL0" + + - + input: + bytes: [ 0xc9, 0x9c, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMCEID0_EL0" + + - + input: + bytes: [ 0xe9, 0x9c, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMCEID1_EL0" + + - + input: + bytes: [ 0x09, 0x9d, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMCCNTR_EL0" + + - + input: + bytes: [ 0x29, 0x9d, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMXEVTYPER_EL0" + + - + input: + bytes: [ 0x49, 0x9d, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMXEVCNTR_EL0" + + - + input: + bytes: [ 0x09, 0x9e, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMUSERENR_EL0" + + - + input: + bytes: [ 0x29, 0x9e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMINTENSET_EL1" + + - + input: + bytes: [ 0x49, 0x9e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMINTENCLR_EL1" + + - + input: + bytes: [ 0x69, 0x9e, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMOVSSET_EL0" + + - + input: + bytes: [ 0xc9, 0x9e, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMMIR_EL1" + + - + input: + bytes: [ 0x09, 0xa2, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, MAIR_EL1" + + - + input: + bytes: [ 0x09, 0xa2, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, MAIR_EL2" + + - + input: + bytes: [ 0x09, 0xa2, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, MAIR_EL3" + + - + input: + bytes: [ 0x09, 0xa3, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, AMAIR_EL1" + + - + input: + bytes: [ 0x09, 0xa3, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, AMAIR_EL2" + + - + input: + bytes: [ 0x09, 0xa3, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, AMAIR_EL3" + + - + input: + bytes: [ 0x09, 0xc0, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, VBAR_EL1" + + - + input: + bytes: [ 0x09, 0xc0, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, VBAR_EL2" + + - + input: + bytes: [ 0x09, 0xc0, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, VBAR_EL3" + + - + input: + bytes: [ 0x29, 0xc0, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, RVBAR_EL1" + + - + input: + bytes: [ 0x29, 0xc0, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, RVBAR_EL2" + + - + input: + bytes: [ 0x29, 0xc0, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, RVBAR_EL3" + + - + input: + bytes: [ 0x49, 0xc0, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, RMR_EL1" + + - + input: + bytes: [ 0x49, 0xc0, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, RMR_EL2" + + - + input: + bytes: [ 0x49, 0xc0, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, RMR_EL3" + + - + input: + bytes: [ 0x09, 0xc1, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, ISR_EL1" + + - + input: + bytes: [ 0x29, 0xd0, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CONTEXTIDR_EL1" + + - + input: + bytes: [ 0x49, 0xd0, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, TPIDR_EL0" + + - + input: + bytes: [ 0x49, 0xd0, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, TPIDR_EL2" + + - + input: + bytes: [ 0x49, 0xd0, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, TPIDR_EL3" + + - + input: + bytes: [ 0x69, 0xd0, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, TPIDRRO_EL0" + + - + input: + bytes: [ 0x89, 0xd0, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, TPIDR_EL1" + + - + input: + bytes: [ 0x09, 0xe0, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CNTFRQ_EL0" + + - + input: + bytes: [ 0x29, 0xe0, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CNTPCT_EL0" + + - + input: + bytes: [ 0x49, 0xe0, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CNTVCT_EL0" + + - + input: + bytes: [ 0x69, 0xe0, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CNTVOFF_EL2" + + - + input: + bytes: [ 0x09, 0xe1, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CNTKCTL_EL1" + + - + input: + bytes: [ 0x09, 0xe1, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CNTHCTL_EL2" + + - + input: + bytes: [ 0x09, 0xe2, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CNTP_TVAL_EL0" + + - + input: + bytes: [ 0x09, 0xe2, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CNTHP_TVAL_EL2" + + - + input: + bytes: [ 0x09, 0xe2, 0x3f, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CNTPS_TVAL_EL1" + + - + input: + bytes: [ 0x29, 0xe2, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CNTP_CTL_EL0" + + - + input: + bytes: [ 0x29, 0xe2, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CNTHP_CTL_EL2" + + - + input: + bytes: [ 0x29, 0xe2, 0x3f, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CNTPS_CTL_EL1" + + - + input: + bytes: [ 0x49, 0xe2, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CNTP_CVAL_EL0" + + - + input: + bytes: [ 0x49, 0xe2, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CNTHP_CVAL_EL2" + + - + input: + bytes: [ 0x49, 0xe2, 0x3f, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CNTPS_CVAL_EL1" + + - + input: + bytes: [ 0x09, 0xe3, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CNTV_TVAL_EL0" + + - + input: + bytes: [ 0x29, 0xe3, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CNTV_CTL_EL0" + + - + input: + bytes: [ 0x49, 0xe3, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, CNTV_CVAL_EL0" + + - + input: + bytes: [ 0x09, 0xe8, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR0_EL0" + + - + input: + bytes: [ 0x29, 0xe8, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR1_EL0" + + - + input: + bytes: [ 0x49, 0xe8, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR2_EL0" + + - + input: + bytes: [ 0x69, 0xe8, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR3_EL0" + + - + input: + bytes: [ 0x89, 0xe8, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR4_EL0" + + - + input: + bytes: [ 0xa9, 0xe8, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR5_EL0" + + - + input: + bytes: [ 0xc9, 0xe8, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR6_EL0" + + - + input: + bytes: [ 0xe9, 0xe8, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR7_EL0" + + - + input: + bytes: [ 0x09, 0xe9, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR8_EL0" + + - + input: + bytes: [ 0x29, 0xe9, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR9_EL0" + + - + input: + bytes: [ 0x49, 0xe9, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR10_EL0" + + - + input: + bytes: [ 0x69, 0xe9, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR11_EL0" + + - + input: + bytes: [ 0x89, 0xe9, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR12_EL0" + + - + input: + bytes: [ 0xa9, 0xe9, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR13_EL0" + + - + input: + bytes: [ 0xc9, 0xe9, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR14_EL0" + + - + input: + bytes: [ 0xe9, 0xe9, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR15_EL0" + + - + input: + bytes: [ 0x09, 0xea, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR16_EL0" + + - + input: + bytes: [ 0x29, 0xea, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR17_EL0" + + - + input: + bytes: [ 0x49, 0xea, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR18_EL0" + + - + input: + bytes: [ 0x69, 0xea, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR19_EL0" + + - + input: + bytes: [ 0x89, 0xea, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR20_EL0" + + - + input: + bytes: [ 0xa9, 0xea, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR21_EL0" + + - + input: + bytes: [ 0xc9, 0xea, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR22_EL0" + + - + input: + bytes: [ 0xe9, 0xea, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR23_EL0" + + - + input: + bytes: [ 0x09, 0xeb, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR24_EL0" + + - + input: + bytes: [ 0x29, 0xeb, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR25_EL0" + + - + input: + bytes: [ 0x49, 0xeb, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR26_EL0" + + - + input: + bytes: [ 0x69, 0xeb, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR27_EL0" + + - + input: + bytes: [ 0x89, 0xeb, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR28_EL0" + + - + input: + bytes: [ 0xa9, 0xeb, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR29_EL0" + + - + input: + bytes: [ 0xc9, 0xeb, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVCNTR30_EL0" + + - + input: + bytes: [ 0xe9, 0xef, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMCCFILTR_EL0" + + - + input: + bytes: [ 0x09, 0xec, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER0_EL0" + + - + input: + bytes: [ 0x29, 0xec, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER1_EL0" + + - + input: + bytes: [ 0x49, 0xec, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER2_EL0" + + - + input: + bytes: [ 0x69, 0xec, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER3_EL0" + + - + input: + bytes: [ 0x89, 0xec, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER4_EL0" + + - + input: + bytes: [ 0xa9, 0xec, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER5_EL0" + + - + input: + bytes: [ 0xc9, 0xec, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER6_EL0" + + - + input: + bytes: [ 0xe9, 0xec, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER7_EL0" + + - + input: + bytes: [ 0x09, 0xed, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER8_EL0" + + - + input: + bytes: [ 0x29, 0xed, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER9_EL0" + + - + input: + bytes: [ 0x49, 0xed, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER10_EL0" + + - + input: + bytes: [ 0x69, 0xed, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER11_EL0" + + - + input: + bytes: [ 0x89, 0xed, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER12_EL0" + + - + input: + bytes: [ 0xa9, 0xed, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER13_EL0" + + - + input: + bytes: [ 0xc9, 0xed, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER14_EL0" + + - + input: + bytes: [ 0xe9, 0xed, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER15_EL0" + + - + input: + bytes: [ 0x09, 0xee, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER16_EL0" + + - + input: + bytes: [ 0x29, 0xee, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER17_EL0" + + - + input: + bytes: [ 0x49, 0xee, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER18_EL0" + + - + input: + bytes: [ 0x69, 0xee, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER19_EL0" + + - + input: + bytes: [ 0x89, 0xee, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER20_EL0" + + - + input: + bytes: [ 0xa9, 0xee, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER21_EL0" + + - + input: + bytes: [ 0xc9, 0xee, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER22_EL0" + + - + input: + bytes: [ 0xe9, 0xee, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER23_EL0" + + - + input: + bytes: [ 0x09, 0xef, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER24_EL0" + + - + input: + bytes: [ 0x29, 0xef, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER25_EL0" + + - + input: + bytes: [ 0x49, 0xef, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER26_EL0" + + - + input: + bytes: [ 0x69, 0xef, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER27_EL0" + + - + input: + bytes: [ 0x89, 0xef, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER28_EL0" + + - + input: + bytes: [ 0xa9, 0xef, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER29_EL0" + + - + input: + bytes: [ 0xc9, 0xef, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PMEVTYPER30_EL0" + + - + input: + bytes: [ 0x29, 0xa3, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, AMAIR2_EL1" + + - + input: + bytes: [ 0x29, 0xa3, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, AMAIR2_EL12" + + - + input: + bytes: [ 0x29, 0xa3, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, AMAIR2_EL2" + + - + input: + bytes: [ 0x29, 0xa3, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, AMAIR2_EL3" + + - + input: + bytes: [ 0x29, 0xa2, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, MAIR2_EL1" + + - + input: + bytes: [ 0x29, 0xa2, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, MAIR2_EL12" + + - + input: + bytes: [ 0x29, 0xa1, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, MAIR2_EL2" + + - + input: + bytes: [ 0x29, 0xa1, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, MAIR2_EL3" + + - + input: + bytes: [ 0x49, 0xa2, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PIRE0_EL1" + + - + input: + bytes: [ 0x49, 0xa2, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PIRE0_EL12" + + - + input: + bytes: [ 0x49, 0xa2, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PIRE0_EL2" + + - + input: + bytes: [ 0x69, 0xa2, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PIR_EL1" + + - + input: + bytes: [ 0x69, 0xa2, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PIR_EL12" + + - + input: + bytes: [ 0x69, 0xa2, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PIR_EL2" + + - + input: + bytes: [ 0x69, 0xa2, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, PIR_EL3" + + - + input: + bytes: [ 0xa9, 0xa2, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, S2PIR_EL2" + + - + input: + bytes: [ 0x89, 0xa2, 0x3b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, POR_EL0" + + - + input: + bytes: [ 0x89, 0xa2, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, POR_EL1" + + - + input: + bytes: [ 0x89, 0xa2, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, POR_EL12" + + - + input: + bytes: [ 0x89, 0xa2, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, POR_EL2" + + - + input: + bytes: [ 0x89, 0xa2, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, POR_EL3" + + - + input: + bytes: [ 0xa9, 0xa2, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, S2POR_EL1" + + - + input: + bytes: [ 0x69, 0x10, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SCTLR2_EL1" + + - + input: + bytes: [ 0x69, 0x10, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SCTLR2_EL12" + + - + input: + bytes: [ 0x69, 0x10, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SCTLR2_EL2" + + - + input: + bytes: [ 0x69, 0x10, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, SCTLR2_EL3" + + - + input: + bytes: [ 0x69, 0x20, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, TCR2_EL1" + + - + input: + bytes: [ 0x69, 0x20, 0x3d, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, TCR2_EL12" + + - + input: + bytes: [ 0x69, 0x20, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x9, TCR2_EL2" + + - + input: + bytes: [ 0xac, 0xf1, 0x3f, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x12, S3_7_C15_C1_5" + + - + input: + bytes: [ 0xed, 0xbf, 0x3a, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "mrs x13, S3_2_C11_C15_7" + + - + input: + bytes: [ 0x2e, 0x92, 0x2b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sysl x14, #3, c9, c2, #1" + skip_reason: "Just a note: This test is correct, llvm-mc emits the msr variant, when it assembles. Disassembly only matches." + + - + input: + bytes: [ 0x0c, 0xf0, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr S3_0_C15_C0_0, x12" + + - + input: + bytes: [ 0xe5, 0xbd, 0x1f, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "msr S3_7_C11_C13_7, x5" + + - + input: + bytes: [ 0x24, 0x92, 0x0b, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "sys #3, c9, c2, #1, x4" + skip_reason: "Just a note: This test is correct, llvm-mc emits the msr variant, when it assembles. Disassembly only matches." + + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "b #4" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x94 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bl #0" + + - + input: + bytes: [ 0xff, 0xff, 0xff, 0x15 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "b #134217724" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x96 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "bl #-134217728" + + - + input: + bytes: [ 0x80, 0x02, 0x1f, 0xd6 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "br x20" + + - + input: + bytes: [ 0xe0, 0x03, 0x3f, 0xd6 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "blr xzr" + + - + input: + bytes: [ 0x40, 0x01, 0x5f, 0xd6 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ret x10" + + - + input: + bytes: [ 0xc0, 0x03, 0x5f, 0xd6 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "ret" + + - + input: + bytes: [ 0xe0, 0x03, 0x9f, 0xd6 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0xe0, 0x03, 0xbf, 0xd6 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ] + expected: + insns: + - + asm_text: "drps" diff --git a/tests/MC/AArch64/case-insen-reg-names.s.yaml b/tests/MC/AArch64/case-insen-reg-names.s.yaml new file mode 100644 index 0000000000..36792f519a --- /dev/null +++ b/tests/MC/AArch64/case-insen-reg-names.s.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0xa0, 0xd4, 0x66, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "fadd v0.2d, v5.2d, v6.2d" + + - + input: + bytes: [ 0xa0, 0xd4, 0x66, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "fadd v0.2d, v5.2d, v6.2d" + + - + input: + bytes: [ 0xa0, 0xd4, 0x66, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "fadd v0.2d, v5.2d, v6.2d" diff --git a/tests/MC/AArch64/dot-req.s.yaml b/tests/MC/AArch64/dot-req.s.yaml new file mode 100644 index 0000000000..83b9694aae --- /dev/null +++ b/tests/MC/AArch64/dot-req.s.yaml @@ -0,0 +1,110 @@ +test_cases: + - + input: + bytes: [ 0xe5, 0x03, 0x0b, 0xaa ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mov x5, x11" + + - + input: + bytes: [ 0xe1, 0x03, 0x06, 0x2a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mov w1, w6" + + - + input: + bytes: [ 0xe1, 0x03, 0x06, 0x2a ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mov w1, w6" + + - + input: + bytes: [ 0x06, 0xb8, 0x31, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "addv b6, v0.8b" + + - + input: + bytes: [ 0x85, 0x04, 0x0e, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mov h5, v4.h[3]" + + - + input: + bytes: [ 0x80, 0x28, 0x24, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "fadd s0, s4, s4" + + - + input: + bytes: [ 0x62, 0x40, 0x60, 0x1e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "fmov d2, d3" + + - + input: + bytes: [ 0xe2, 0x03, 0xc0, 0x3d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "ldr q2, [sp]" + + - + input: + bytes: [ 0x20, 0x1c, 0xa1, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mov v0.8b, v1.8b" + + - + input: + bytes: [ 0x06, 0x00, 0x00, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "add x6, x0, x0" + + - + input: + bytes: [ 0x06, 0x00, 0x00, 0x8b ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "add x6, x0, x0" diff --git a/tests/MC/AArch64/ete-sysregs.s.yaml b/tests/MC/AArch64/ete-sysregs.s.yaml new file mode 100644 index 0000000000..661d8e3f60 --- /dev/null +++ b/tests/MC/AArch64/ete-sysregs.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x0a, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, TRCRSR" + + - + input: + bytes: [ 0x80, 0x08, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, TRCEXTINSELR" + + - + input: + bytes: [ 0x80, 0x08, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, TRCEXTINSELR" + + - + input: + bytes: [ 0x80, 0x09, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, TRCEXTINSELR1" + + - + input: + bytes: [ 0x80, 0x0a, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, TRCEXTINSELR2" + + - + input: + bytes: [ 0x80, 0x0b, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, TRCEXTINSELR3" + + - + input: + bytes: [ 0x00, 0x0a, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr TRCRSR, x0" + + - + input: + bytes: [ 0x80, 0x08, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr TRCEXTINSELR, x0" + + - + input: + bytes: [ 0x80, 0x08, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr TRCEXTINSELR, x0" + + - + input: + bytes: [ 0x80, 0x09, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr TRCEXTINSELR1, x0" + + - + input: + bytes: [ 0x80, 0x0a, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr TRCEXTINSELR2, x0" + + - + input: + bytes: [ 0x80, 0x0b, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr TRCEXTINSELR3, x0" diff --git a/tests/MC/AArch64/gicv3-regs.s.yaml b/tests/MC/AArch64/gicv3-regs.s.yaml new file mode 100644 index 0000000000..2df4d85942 --- /dev/null +++ b/tests/MC/AArch64/gicv3-regs.s.yaml @@ -0,0 +1,1050 @@ +test_cases: + - + input: + bytes: [ 0x08, 0xcc, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x8, ICC_IAR1_EL1" + + - + input: + bytes: [ 0x1a, 0xc8, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x26, ICC_IAR0_EL1" + + - + input: + bytes: [ 0x42, 0xcc, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x2, ICC_HPPIR1_EL1" + + - + input: + bytes: [ 0x51, 0xc8, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x17, ICC_HPPIR0_EL1" + + - + input: + bytes: [ 0x7d, 0xcb, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x29, ICC_RPR_EL1" + + - + input: + bytes: [ 0x24, 0xcb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x4, ICH_VTR_EL2" + + - + input: + bytes: [ 0x78, 0xcb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x24, ICH_EISR_EL2" + + - + input: + bytes: [ 0xa9, 0xcb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x9, ICH_ELRSR_EL2" + + - + input: + bytes: [ 0x78, 0xcc, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x24, ICC_BPR1_EL1" + + - + input: + bytes: [ 0x6e, 0xc8, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x14, ICC_BPR0_EL1" + + - + input: + bytes: [ 0x13, 0x46, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x19, ICC_PMR_EL1" + + - + input: + bytes: [ 0x97, 0xcc, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x23, ICC_CTLR_EL1" + + - + input: + bytes: [ 0x94, 0xcc, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x20, ICC_CTLR_EL3" + + - + input: + bytes: [ 0xbc, 0xcc, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x28, ICC_SRE_EL1" + + - + input: + bytes: [ 0xb9, 0xc9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x25, ICC_SRE_EL2" + + - + input: + bytes: [ 0xa8, 0xcc, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x8, ICC_SRE_EL3" + + - + input: + bytes: [ 0xd6, 0xcc, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x22, ICC_IGRPEN0_EL1" + + - + input: + bytes: [ 0xe5, 0xcc, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x5, ICC_IGRPEN1_EL1" + + - + input: + bytes: [ 0xe7, 0xcc, 0x3e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x7, ICC_IGRPEN1_EL3" + + - + input: + bytes: [ 0x84, 0xc8, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x4, ICC_AP0R0_EL1" + + - + input: + bytes: [ 0xab, 0xc8, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x11, ICC_AP0R1_EL1" + + - + input: + bytes: [ 0xdb, 0xc8, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x27, ICC_AP0R2_EL1" + + - + input: + bytes: [ 0xf5, 0xc8, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x21, ICC_AP0R3_EL1" + + - + input: + bytes: [ 0x02, 0xc9, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x2, ICC_AP1R0_EL1" + + - + input: + bytes: [ 0x35, 0xc9, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x21, ICC_AP1R1_EL1" + + - + input: + bytes: [ 0x4a, 0xc9, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x10, ICC_AP1R2_EL1" + + - + input: + bytes: [ 0x7b, 0xc9, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x27, ICC_AP1R3_EL1" + + - + input: + bytes: [ 0x14, 0xc8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x20, ICH_AP0R0_EL2" + + - + input: + bytes: [ 0x35, 0xc8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x21, ICH_AP0R1_EL2" + + - + input: + bytes: [ 0x45, 0xc8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x5, ICH_AP0R2_EL2" + + - + input: + bytes: [ 0x64, 0xc8, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x4, ICH_AP0R3_EL2" + + - + input: + bytes: [ 0x0f, 0xc9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x15, ICH_AP1R0_EL2" + + - + input: + bytes: [ 0x2c, 0xc9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x12, ICH_AP1R1_EL2" + + - + input: + bytes: [ 0x5b, 0xc9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x27, ICH_AP1R2_EL2" + + - + input: + bytes: [ 0x74, 0xc9, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x20, ICH_AP1R3_EL2" + + - + input: + bytes: [ 0x0a, 0xcb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x10, ICH_HCR_EL2" + + - + input: + bytes: [ 0x5b, 0xcb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x27, ICH_MISR_EL2" + + - + input: + bytes: [ 0xe6, 0xcb, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x6, ICH_VMCR_EL2" + + - + input: + bytes: [ 0x03, 0xcc, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x3, ICH_LR0_EL2" + + - + input: + bytes: [ 0x21, 0xcc, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x1, ICH_LR1_EL2" + + - + input: + bytes: [ 0x56, 0xcc, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x22, ICH_LR2_EL2" + + - + input: + bytes: [ 0x75, 0xcc, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x21, ICH_LR3_EL2" + + - + input: + bytes: [ 0x86, 0xcc, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x6, ICH_LR4_EL2" + + - + input: + bytes: [ 0xaa, 0xcc, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x10, ICH_LR5_EL2" + + - + input: + bytes: [ 0xcb, 0xcc, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x11, ICH_LR6_EL2" + + - + input: + bytes: [ 0xec, 0xcc, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x12, ICH_LR7_EL2" + + - + input: + bytes: [ 0x00, 0xcd, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x0, ICH_LR8_EL2" + + - + input: + bytes: [ 0x35, 0xcd, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x21, ICH_LR9_EL2" + + - + input: + bytes: [ 0x4d, 0xcd, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x13, ICH_LR10_EL2" + + - + input: + bytes: [ 0x7a, 0xcd, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x26, ICH_LR11_EL2" + + - + input: + bytes: [ 0x81, 0xcd, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x1, ICH_LR12_EL2" + + - + input: + bytes: [ 0xa8, 0xcd, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x8, ICH_LR13_EL2" + + - + input: + bytes: [ 0xc2, 0xcd, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x2, ICH_LR14_EL2" + + - + input: + bytes: [ 0xe8, 0xcd, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x8, ICH_LR15_EL2" + + - + input: + bytes: [ 0x3b, 0xcc, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_EOIR1_EL1, x27" + + - + input: + bytes: [ 0x25, 0xc8, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_EOIR0_EL1, x5" + + - + input: + bytes: [ 0x2d, 0xcb, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_DIR_EL1, x13" + + - + input: + bytes: [ 0xb5, 0xcb, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_SGI1R_EL1, x21" + + - + input: + bytes: [ 0xd9, 0xcb, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_ASGI1R_EL1, x25" + + - + input: + bytes: [ 0xfc, 0xcb, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_SGI0R_EL1, x28" + + - + input: + bytes: [ 0x67, 0xcc, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_BPR1_EL1, x7" + + - + input: + bytes: [ 0x69, 0xc8, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_BPR0_EL1, x9" + + - + input: + bytes: [ 0x1d, 0x46, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_PMR_EL1, x29" + + - + input: + bytes: [ 0x98, 0xcc, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_CTLR_EL1, x24" + + - + input: + bytes: [ 0x80, 0xcc, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_CTLR_EL3, x0" + + - + input: + bytes: [ 0xa2, 0xcc, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_SRE_EL1, x2" + + - + input: + bytes: [ 0xa5, 0xc9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_SRE_EL2, x5" + + - + input: + bytes: [ 0xaa, 0xcc, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_SRE_EL3, x10" + + - + input: + bytes: [ 0xd6, 0xcc, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_IGRPEN0_EL1, x22" + + - + input: + bytes: [ 0xeb, 0xcc, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_IGRPEN1_EL1, x11" + + - + input: + bytes: [ 0xe8, 0xcc, 0x1e, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_IGRPEN1_EL3, x8" + + - + input: + bytes: [ 0x9b, 0xc8, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_AP0R0_EL1, x27" + + - + input: + bytes: [ 0xa5, 0xc8, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_AP0R1_EL1, x5" + + - + input: + bytes: [ 0xd4, 0xc8, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_AP0R2_EL1, x20" + + - + input: + bytes: [ 0xe0, 0xc8, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_AP0R3_EL1, x0" + + - + input: + bytes: [ 0x02, 0xc9, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_AP1R0_EL1, x2" + + - + input: + bytes: [ 0x3d, 0xc9, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_AP1R1_EL1, x29" + + - + input: + bytes: [ 0x57, 0xc9, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_AP1R2_EL1, x23" + + - + input: + bytes: [ 0x6b, 0xc9, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICC_AP1R3_EL1, x11" + + - + input: + bytes: [ 0x02, 0xc8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_AP0R0_EL2, x2" + + - + input: + bytes: [ 0x3b, 0xc8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_AP0R1_EL2, x27" + + - + input: + bytes: [ 0x47, 0xc8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_AP0R2_EL2, x7" + + - + input: + bytes: [ 0x61, 0xc8, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_AP0R3_EL2, x1" + + - + input: + bytes: [ 0x07, 0xc9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_AP1R0_EL2, x7" + + - + input: + bytes: [ 0x2c, 0xc9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_AP1R1_EL2, x12" + + - + input: + bytes: [ 0x4e, 0xc9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_AP1R2_EL2, x14" + + - + input: + bytes: [ 0x6d, 0xc9, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_AP1R3_EL2, x13" + + - + input: + bytes: [ 0x01, 0xcb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_HCR_EL2, x1" + + - + input: + bytes: [ 0xf8, 0xcb, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_VMCR_EL2, x24" + + - + input: + bytes: [ 0x1a, 0xcc, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_LR0_EL2, x26" + + - + input: + bytes: [ 0x29, 0xcc, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_LR1_EL2, x9" + + - + input: + bytes: [ 0x52, 0xcc, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_LR2_EL2, x18" + + - + input: + bytes: [ 0x7a, 0xcc, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_LR3_EL2, x26" + + - + input: + bytes: [ 0x96, 0xcc, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_LR4_EL2, x22" + + - + input: + bytes: [ 0xba, 0xcc, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_LR5_EL2, x26" + + - + input: + bytes: [ 0xdb, 0xcc, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_LR6_EL2, x27" + + - + input: + bytes: [ 0xe8, 0xcc, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_LR7_EL2, x8" + + - + input: + bytes: [ 0x11, 0xcd, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_LR8_EL2, x17" + + - + input: + bytes: [ 0x33, 0xcd, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_LR9_EL2, x19" + + - + input: + bytes: [ 0x51, 0xcd, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_LR10_EL2, x17" + + - + input: + bytes: [ 0x65, 0xcd, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_LR11_EL2, x5" + + - + input: + bytes: [ 0x9d, 0xcd, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_LR12_EL2, x29" + + - + input: + bytes: [ 0xa2, 0xcd, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_LR13_EL2, x2" + + - + input: + bytes: [ 0xcd, 0xcd, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_LR14_EL2, x13" + + - + input: + bytes: [ 0xfb, 0xcd, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr ICH_LR15_EL2, x27" diff --git a/tests/MC/AArch64/neon-2velem.s.yaml b/tests/MC/AArch64/neon-2velem.s.yaml new file mode 100644 index 0000000000..042b628112 --- /dev/null +++ b/tests/MC/AArch64/neon-2velem.s.yaml @@ -0,0 +1,1200 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x08, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mla v0.2s, v1.2s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0x08, 0x96, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mla v0.2s, v1.2s, v22.s[2]" + + - + input: + bytes: [ 0x03, 0x01, 0xa2, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mla v3.4s, v8.4s, v2.s[1]" + + - + input: + bytes: [ 0x03, 0x09, 0xb6, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mla v3.4s, v8.4s, v22.s[3]" + + - + input: + bytes: [ 0x20, 0x00, 0x62, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mla v0.4h, v1.4h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0x00, 0x6f, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mla v0.4h, v1.4h, v15.h[2]" + + - + input: + bytes: [ 0x20, 0x08, 0x72, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mla v0.8h, v1.8h, v2.h[7]" + + - + input: + bytes: [ 0x20, 0x08, 0x6e, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mla v0.8h, v1.8h, v14.h[6]" + + - + input: + bytes: [ 0x20, 0x48, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mls v0.2s, v1.2s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0x48, 0x96, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mls v0.2s, v1.2s, v22.s[2]" + + - + input: + bytes: [ 0x03, 0x41, 0xa2, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mls v3.4s, v8.4s, v2.s[1]" + + - + input: + bytes: [ 0x03, 0x49, 0xb6, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mls v3.4s, v8.4s, v22.s[3]" + + - + input: + bytes: [ 0x20, 0x40, 0x62, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mls v0.4h, v1.4h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0x40, 0x6f, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mls v0.4h, v1.4h, v15.h[2]" + + - + input: + bytes: [ 0x20, 0x48, 0x72, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mls v0.8h, v1.8h, v2.h[7]" + + - + input: + bytes: [ 0x20, 0x48, 0x6e, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mls v0.8h, v1.8h, v14.h[6]" + + - + input: + bytes: [ 0x20, 0x10, 0x22, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla v0.4h, v1.4h, v2.h[2]" + + - + input: + bytes: [ 0x03, 0x11, 0x12, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla v3.8h, v8.8h, v2.h[1]" + + - + input: + bytes: [ 0x20, 0x18, 0x82, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla v0.2s, v1.2s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0x18, 0x96, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla v0.2s, v1.2s, v22.s[2]" + + - + input: + bytes: [ 0x03, 0x11, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla v3.4s, v8.4s, v2.s[1]" + + - + input: + bytes: [ 0x03, 0x19, 0xb6, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla v3.4s, v8.4s, v22.s[3]" + + - + input: + bytes: [ 0x20, 0x18, 0xc2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla v0.2d, v1.2d, v2.d[1]" + + - + input: + bytes: [ 0x20, 0x18, 0xd6, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla v0.2d, v1.2d, v22.d[1]" + + - + input: + bytes: [ 0x20, 0x50, 0x22, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls v0.4h, v1.4h, v2.h[2]" + + - + input: + bytes: [ 0x03, 0x51, 0x12, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls v3.8h, v8.8h, v2.h[1]" + + - + input: + bytes: [ 0x20, 0x58, 0x82, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls v0.2s, v1.2s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0x58, 0x96, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls v0.2s, v1.2s, v22.s[2]" + + - + input: + bytes: [ 0x03, 0x51, 0xa2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls v3.4s, v8.4s, v2.s[1]" + + - + input: + bytes: [ 0x03, 0x59, 0xb6, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls v3.4s, v8.4s, v22.s[3]" + + - + input: + bytes: [ 0x20, 0x58, 0xc2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls v0.2d, v1.2d, v2.d[1]" + + - + input: + bytes: [ 0x20, 0x58, 0xd6, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls v0.2d, v1.2d, v22.d[1]" + + - + input: + bytes: [ 0x20, 0x20, 0x62, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smlal v0.4s, v1.4h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0x28, 0x82, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smlal v0.2d, v1.2s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0x28, 0x96, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smlal v0.2d, v1.2s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0x20, 0x61, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smlal2 v0.4s, v1.8h, v1.h[2]" + + - + input: + bytes: [ 0x20, 0x28, 0x81, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smlal2 v0.2d, v1.4s, v1.s[2]" + + - + input: + bytes: [ 0x20, 0x28, 0x96, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smlal2 v0.2d, v1.4s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0x60, 0x62, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smlsl v0.4s, v1.4h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0x68, 0x82, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smlsl v0.2d, v1.2s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0x68, 0x96, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smlsl v0.2d, v1.2s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0x60, 0x61, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smlsl2 v0.4s, v1.8h, v1.h[2]" + + - + input: + bytes: [ 0x20, 0x68, 0x81, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smlsl2 v0.2d, v1.4s, v1.s[2]" + + - + input: + bytes: [ 0x20, 0x68, 0x96, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smlsl2 v0.2d, v1.4s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0x30, 0x62, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmlal v0.4s, v1.4h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0x38, 0x82, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmlal v0.2d, v1.2s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0x38, 0x96, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmlal v0.2d, v1.2s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0x30, 0x61, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmlal2 v0.4s, v1.8h, v1.h[2]" + + - + input: + bytes: [ 0x20, 0x38, 0x81, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmlal2 v0.2d, v1.4s, v1.s[2]" + + - + input: + bytes: [ 0x20, 0x38, 0x96, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmlal2 v0.2d, v1.4s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0x20, 0x62, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umlal v0.4s, v1.4h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0x28, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umlal v0.2d, v1.2s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0x28, 0x96, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umlal v0.2d, v1.2s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0x20, 0x61, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umlal2 v0.4s, v1.8h, v1.h[2]" + + - + input: + bytes: [ 0x20, 0x28, 0x81, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umlal2 v0.2d, v1.4s, v1.s[2]" + + - + input: + bytes: [ 0x20, 0x28, 0x96, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umlal2 v0.2d, v1.4s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0x60, 0x62, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umlsl v0.4s, v1.4h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0x68, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umlsl v0.2d, v1.2s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0x68, 0x96, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umlsl v0.2d, v1.2s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0x60, 0x61, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umlsl2 v0.4s, v1.8h, v1.h[2]" + + - + input: + bytes: [ 0x20, 0x68, 0x81, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umlsl2 v0.2d, v1.4s, v1.s[2]" + + - + input: + bytes: [ 0x20, 0x68, 0x96, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umlsl2 v0.2d, v1.4s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0x70, 0x62, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmlsl v0.4s, v1.4h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0x78, 0x82, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmlsl v0.2d, v1.2s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0x78, 0x96, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmlsl v0.2d, v1.2s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0x70, 0x61, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmlsl2 v0.4s, v1.8h, v1.h[2]" + + - + input: + bytes: [ 0x20, 0x78, 0x81, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmlsl2 v0.2d, v1.4s, v1.s[2]" + + - + input: + bytes: [ 0x20, 0x78, 0x96, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmlsl2 v0.2d, v1.4s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0x80, 0x62, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mul v0.4h, v1.4h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0x80, 0x62, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mul v0.8h, v1.8h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0x88, 0x82, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mul v0.2s, v1.2s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0x88, 0x96, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mul v0.2s, v1.2s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0x88, 0x82, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mul v0.4s, v1.4s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0x88, 0x96, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mul v0.4s, v1.4s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0x90, 0x22, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmul v0.4h, v1.4h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0x90, 0x22, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmul v0.8h, v1.8h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0x98, 0x82, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmul v0.2s, v1.2s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0x98, 0x96, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmul v0.2s, v1.2s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0x98, 0x82, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmul v0.4s, v1.4s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0x98, 0x96, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmul v0.4s, v1.4s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0x98, 0xc2, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmul v0.2d, v1.2d, v2.d[1]" + + - + input: + bytes: [ 0x20, 0x98, 0xd6, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmul v0.2d, v1.2d, v22.d[1]" + + - + input: + bytes: [ 0x20, 0x90, 0x22, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmulx v0.4h, v1.4h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0x90, 0x22, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmulx v0.8h, v1.8h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0x98, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmulx v0.2s, v1.2s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0x98, 0x96, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmulx v0.2s, v1.2s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0x98, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmulx v0.4s, v1.4s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0x98, 0x96, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmulx v0.4s, v1.4s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0x98, 0xc2, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmulx v0.2d, v1.2d, v2.d[1]" + + - + input: + bytes: [ 0x20, 0x98, 0xd6, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmulx v0.2d, v1.2d, v22.d[1]" + + - + input: + bytes: [ 0x20, 0xa0, 0x62, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smull v0.4s, v1.4h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0xa8, 0x82, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smull v0.2d, v1.2s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0xa8, 0x96, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smull v0.2d, v1.2s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0xa0, 0x62, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smull2 v0.4s, v1.8h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0xa8, 0x82, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smull2 v0.2d, v1.4s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0xa8, 0x96, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smull2 v0.2d, v1.4s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0xa0, 0x62, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umull v0.4s, v1.4h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0xa8, 0x82, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umull v0.2d, v1.2s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0xa8, 0x96, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umull v0.2d, v1.2s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0xa0, 0x62, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umull2 v0.4s, v1.8h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0xa8, 0x82, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umull2 v0.2d, v1.4s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0xa8, 0x96, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umull2 v0.2d, v1.4s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0xb0, 0x62, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmull v0.4s, v1.4h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0xb8, 0x82, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmull v0.2d, v1.2s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0xb8, 0x96, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmull v0.2d, v1.2s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0xb0, 0x62, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmull2 v0.4s, v1.8h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0xb8, 0x82, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmull2 v0.2d, v1.4s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0xb8, 0x96, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmull2 v0.2d, v1.4s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0xc0, 0x62, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmulh v0.4h, v1.4h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0xc0, 0x62, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmulh v0.8h, v1.8h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0xc8, 0x82, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmulh v0.2s, v1.2s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0xc8, 0x96, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmulh v0.2s, v1.2s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0xc8, 0x82, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmulh v0.4s, v1.4s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0xc8, 0x96, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmulh v0.4s, v1.4s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0xd0, 0x62, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrdmulh v0.4h, v1.4h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0xd0, 0x62, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrdmulh v0.8h, v1.8h, v2.h[2]" + + - + input: + bytes: [ 0x20, 0xd8, 0x82, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrdmulh v0.2s, v1.2s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0xd8, 0x96, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrdmulh v0.2s, v1.2s, v22.s[2]" + + - + input: + bytes: [ 0x20, 0xd8, 0x82, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrdmulh v0.4s, v1.4s, v2.s[2]" + + - + input: + bytes: [ 0x20, 0xd8, 0x96, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrdmulh v0.4s, v1.4s, v22.s[2]" diff --git a/tests/MC/AArch64/neon-3vdiff.s.yaml b/tests/MC/AArch64/neon-3vdiff.s.yaml new file mode 100644 index 0000000000..5c7d3c0d70 --- /dev/null +++ b/tests/MC/AArch64/neon-3vdiff.s.yaml @@ -0,0 +1,1420 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x00, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "saddl v0.8h, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x00, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "saddl v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x00, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "saddl v0.2d, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x00, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "saddl2 v0.4s, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x00, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "saddl2 v0.8h, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x00, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "saddl2 v0.2d, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x00, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uaddl v0.8h, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x00, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uaddl v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x00, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uaddl v0.2d, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x00, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uaddl2 v0.8h, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x00, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uaddl2 v0.4s, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x00, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uaddl2 v0.2d, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x20, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "ssubl v0.8h, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x20, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "ssubl v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x20, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "ssubl v0.2d, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x20, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "ssubl2 v0.8h, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x20, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "ssubl2 v0.4s, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x20, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "ssubl2 v0.2d, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x20, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "usubl v0.8h, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x20, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "usubl v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x20, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "usubl v0.2d, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x20, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "usubl2 v0.8h, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x20, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "usubl2 v0.4s, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x20, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "usubl2 v0.2d, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x50, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sabal v0.8h, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x50, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sabal v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x50, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sabal v0.2d, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x50, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sabal2 v0.8h, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x50, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sabal2 v0.4s, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x50, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sabal2 v0.2d, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x50, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uabal v0.8h, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x50, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uabal v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x50, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uabal v0.2d, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x50, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uabal2 v0.8h, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x50, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uabal2 v0.4s, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x50, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uabal2 v0.2d, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x70, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sabdl v0.8h, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x70, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sabdl v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x70, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sabdl v0.2d, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x70, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sabdl2 v0.8h, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x70, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sabdl2 v0.4s, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x70, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sabdl2 v0.2d, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x70, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uabdl v0.8h, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x70, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uabdl v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x70, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uabdl v0.2d, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x70, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uabdl2 v0.8h, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x70, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uabdl2 v0.4s, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x70, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uabdl2 v0.2d, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x80, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "smlal v0.8h, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x80, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "smlal v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x80, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "smlal v0.2d, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x80, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "smlal2 v0.8h, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x80, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "smlal2 v0.4s, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x80, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "smlal2 v0.2d, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x80, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "umlal v0.8h, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x80, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "umlal v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x80, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "umlal v0.2d, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x80, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "umlal2 v0.8h, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x80, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "umlal2 v0.4s, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x80, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "umlal2 v0.2d, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0xa0, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "smlsl v0.8h, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0xa0, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "smlsl v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0xa0, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "smlsl v0.2d, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0xa0, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "smlsl2 v0.8h, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xa0, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "smlsl2 v0.4s, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0xa0, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "smlsl2 v0.2d, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0xa0, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "umlsl v0.8h, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0xa0, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "umlsl v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0xa0, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "umlsl v0.2d, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0xa0, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "umlsl2 v0.8h, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xa0, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "umlsl2 v0.4s, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0xa0, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "umlsl2 v0.2d, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0xc0, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "smull v0.8h, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0xc0, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "smull v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0xc0, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "smull v0.2d, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0xc0, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "smull2 v0.8h, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xc0, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "smull2 v0.4s, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0xc0, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "smull2 v0.2d, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0xc0, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "umull v0.8h, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0xc0, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "umull v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0xc0, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "umull v0.2d, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0xc0, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "umull2 v0.8h, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xc0, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "umull2 v0.4s, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0xc0, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "umull2 v0.2d, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x90, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sqdmlal v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x90, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sqdmlal v0.2d, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x90, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sqdmlal2 v0.4s, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x90, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sqdmlal2 v0.2d, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0xb0, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sqdmlsl v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0xb0, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sqdmlsl v0.2d, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0xb0, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sqdmlsl2 v0.4s, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0xb0, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sqdmlsl2 v0.2d, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0xd0, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sqdmull v0.4s, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0xd0, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sqdmull v0.2d, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0xd0, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sqdmull2 v0.4s, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0xd0, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "sqdmull2 v0.2d, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0xe0, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "pmull v0.8h, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0xe0, 0xe2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "pmull v0.1q, v1.1d, v2.1d" + + - + input: + bytes: [ 0x20, 0xe0, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "pmull2 v0.8h, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xe0, 0xe2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "pmull2 v0.1q, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x10, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "saddw v0.8h, v1.8h, v2.8b" + + - + input: + bytes: [ 0x20, 0x10, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "saddw v0.4s, v1.4s, v2.4h" + + - + input: + bytes: [ 0x20, 0x10, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "saddw v0.2d, v1.2d, v2.2s" + + - + input: + bytes: [ 0x20, 0x10, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "saddw2 v0.8h, v1.8h, v2.16b" + + - + input: + bytes: [ 0x20, 0x10, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "saddw2 v0.4s, v1.4s, v2.8h" + + - + input: + bytes: [ 0x20, 0x10, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "saddw2 v0.2d, v1.2d, v2.4s" + + - + input: + bytes: [ 0x20, 0x10, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uaddw v0.8h, v1.8h, v2.8b" + + - + input: + bytes: [ 0x20, 0x10, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uaddw v0.4s, v1.4s, v2.4h" + + - + input: + bytes: [ 0x20, 0x10, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uaddw v0.2d, v1.2d, v2.2s" + + - + input: + bytes: [ 0x20, 0x10, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uaddw2 v0.8h, v1.8h, v2.16b" + + - + input: + bytes: [ 0x20, 0x10, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uaddw2 v0.4s, v1.4s, v2.8h" + + - + input: + bytes: [ 0x20, 0x10, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "uaddw2 v0.2d, v1.2d, v2.4s" + + - + input: + bytes: [ 0x20, 0x30, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "ssubw v0.8h, v1.8h, v2.8b" + + - + input: + bytes: [ 0x20, 0x30, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "ssubw v0.4s, v1.4s, v2.4h" + + - + input: + bytes: [ 0x20, 0x30, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "ssubw v0.2d, v1.2d, v2.2s" + + - + input: + bytes: [ 0x20, 0x30, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "ssubw2 v0.8h, v1.8h, v2.16b" + + - + input: + bytes: [ 0x20, 0x30, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "ssubw2 v0.4s, v1.4s, v2.8h" + + - + input: + bytes: [ 0x20, 0x30, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "ssubw2 v0.2d, v1.2d, v2.4s" + + - + input: + bytes: [ 0x20, 0x30, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "usubw v0.8h, v1.8h, v2.8b" + + - + input: + bytes: [ 0x20, 0x30, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "usubw v0.4s, v1.4s, v2.4h" + + - + input: + bytes: [ 0x20, 0x30, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "usubw v0.2d, v1.2d, v2.2s" + + - + input: + bytes: [ 0x20, 0x30, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "usubw2 v0.8h, v1.8h, v2.16b" + + - + input: + bytes: [ 0x20, 0x30, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "usubw2 v0.4s, v1.4s, v2.8h" + + - + input: + bytes: [ 0x20, 0x30, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "usubw2 v0.2d, v1.2d, v2.4s" + + - + input: + bytes: [ 0x20, 0x40, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "addhn v0.8b, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x40, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "addhn v0.4h, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x40, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "addhn v0.2s, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x40, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "addhn2 v0.16b, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x40, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "addhn2 v0.8h, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x40, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "addhn2 v0.4s, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x40, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "raddhn v0.8b, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x40, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "raddhn v0.4h, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x40, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "raddhn v0.2s, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x40, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "raddhn2 v0.16b, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x40, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "raddhn2 v0.8h, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x40, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "raddhn2 v0.4s, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x60, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "rsubhn v0.8b, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x60, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "rsubhn v0.4h, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x60, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "rsubhn v0.2s, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x60, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "rsubhn2 v0.16b, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x60, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "rsubhn2 v0.8h, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x60, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ] + expected: + insns: + - + asm_text: "rsubhn2 v0.4s, v1.2d, v2.2d" diff --git a/tests/MC/AArch64/neon-aba-abd.s.yaml b/tests/MC/AArch64/neon-aba-abd.s.yaml new file mode 100644 index 0000000000..4f9eedc7a3 --- /dev/null +++ b/tests/MC/AArch64/neon-aba-abd.s.yaml @@ -0,0 +1,280 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x7c, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uaba v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x7c, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uaba v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x7c, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uaba v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x7c, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uaba v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x7c, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uaba v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x7c, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uaba v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x7c, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "saba v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x7c, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "saba v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x7c, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "saba v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x7c, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "saba v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x7c, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "saba v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x7c, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "saba v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x74, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uabd v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x74, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uabd v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x74, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uabd v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x74, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uabd v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x74, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uabd v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x74, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uabd v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x74, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sabd v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x74, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sabd v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x74, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sabd v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x74, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sabd v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x74, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sabd v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x74, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sabd v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x14, 0xc2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fabd v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0xd4, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fabd v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0xff, 0xd5, 0xb0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fabd v31.4s, v15.4s, v16.4s" + + - + input: + bytes: [ 0x07, 0xd5, 0xf9, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fabd v7.2d, v8.2d, v25.2d" diff --git a/tests/MC/AArch64/neon-across.s.yaml b/tests/MC/AArch64/neon-across.s.yaml new file mode 100644 index 0000000000..8631d6b091 --- /dev/null +++ b/tests/MC/AArch64/neon-across.s.yaml @@ -0,0 +1,470 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x38, 0x30, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "saddlv h0, v1.8b" + + - + input: + bytes: [ 0x20, 0x38, 0x30, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "saddlv h0, v1.16b" + + - + input: + bytes: [ 0x20, 0x38, 0x70, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "saddlv s0, v1.4h" + + - + input: + bytes: [ 0x20, 0x38, 0x70, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "saddlv s0, v1.8h" + + - + input: + bytes: [ 0x20, 0x38, 0xb0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "saddlv d0, v1.4s" + + - + input: + bytes: [ 0x20, 0x38, 0x30, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uaddlv h0, v1.8b" + + - + input: + bytes: [ 0x20, 0x38, 0x30, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uaddlv h0, v1.16b" + + - + input: + bytes: [ 0x20, 0x38, 0x70, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uaddlv s0, v1.4h" + + - + input: + bytes: [ 0x20, 0x38, 0x70, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uaddlv s0, v1.8h" + + - + input: + bytes: [ 0x20, 0x38, 0xb0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uaddlv d0, v1.4s" + + - + input: + bytes: [ 0x20, 0xa8, 0x30, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smaxv b0, v1.8b" + + - + input: + bytes: [ 0x20, 0xa8, 0x30, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smaxv b0, v1.16b" + + - + input: + bytes: [ 0x20, 0xa8, 0x70, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smaxv h0, v1.4h" + + - + input: + bytes: [ 0x20, 0xa8, 0x70, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smaxv h0, v1.8h" + + - + input: + bytes: [ 0x20, 0xa8, 0xb0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smaxv s0, v1.4s" + + - + input: + bytes: [ 0x20, 0xa8, 0x31, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sminv b0, v1.8b" + + - + input: + bytes: [ 0x20, 0xa8, 0x31, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sminv b0, v1.16b" + + - + input: + bytes: [ 0x20, 0xa8, 0x71, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sminv h0, v1.4h" + + - + input: + bytes: [ 0x20, 0xa8, 0x71, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sminv h0, v1.8h" + + - + input: + bytes: [ 0x20, 0xa8, 0xb1, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sminv s0, v1.4s" + + - + input: + bytes: [ 0x20, 0xa8, 0x30, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umaxv b0, v1.8b" + + - + input: + bytes: [ 0x20, 0xa8, 0x30, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umaxv b0, v1.16b" + + - + input: + bytes: [ 0x20, 0xa8, 0x70, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umaxv h0, v1.4h" + + - + input: + bytes: [ 0x20, 0xa8, 0x70, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umaxv h0, v1.8h" + + - + input: + bytes: [ 0x20, 0xa8, 0xb0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umaxv s0, v1.4s" + + - + input: + bytes: [ 0x20, 0xa8, 0x31, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uminv b0, v1.8b" + + - + input: + bytes: [ 0x20, 0xa8, 0x31, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uminv b0, v1.16b" + + - + input: + bytes: [ 0x20, 0xa8, 0x71, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uminv h0, v1.4h" + + - + input: + bytes: [ 0x20, 0xa8, 0x71, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uminv h0, v1.8h" + + - + input: + bytes: [ 0x20, 0xa8, 0xb1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uminv s0, v1.4s" + + - + input: + bytes: [ 0x20, 0xb8, 0x31, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "addv b0, v1.8b" + + - + input: + bytes: [ 0x20, 0xb8, 0x31, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "addv b0, v1.16b" + + - + input: + bytes: [ 0x20, 0xb8, 0x71, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "addv h0, v1.4h" + + - + input: + bytes: [ 0x20, 0xb8, 0x71, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "addv h0, v1.8h" + + - + input: + bytes: [ 0x20, 0xb8, 0xb1, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "addv s0, v1.4s" + + - + input: + bytes: [ 0x20, 0xc8, 0x30, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxnmv h0, v1.4h" + + - + input: + bytes: [ 0x20, 0xc8, 0xb0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminnmv h0, v1.4h" + + - + input: + bytes: [ 0x20, 0xf8, 0x30, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxv h0, v1.4h" + + - + input: + bytes: [ 0x20, 0xf8, 0xb0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminv h0, v1.4h" + + - + input: + bytes: [ 0x20, 0xc8, 0x30, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxnmv h0, v1.8h" + + - + input: + bytes: [ 0x20, 0xc8, 0xb0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminnmv h0, v1.8h" + + - + input: + bytes: [ 0x20, 0xf8, 0x30, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxv h0, v1.8h" + + - + input: + bytes: [ 0x20, 0xf8, 0xb0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminv h0, v1.8h" + + - + input: + bytes: [ 0x20, 0xc8, 0x30, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxnmv s0, v1.4s" + + - + input: + bytes: [ 0x20, 0xc8, 0xb0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminnmv s0, v1.4s" + + - + input: + bytes: [ 0x20, 0xf8, 0x30, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxv s0, v1.4s" + + - + input: + bytes: [ 0x20, 0xf8, 0xb0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminv s0, v1.4s" diff --git a/tests/MC/AArch64/neon-add-pairwise.s.yaml b/tests/MC/AArch64/neon-add-pairwise.s.yaml new file mode 100644 index 0000000000..18988c6fba --- /dev/null +++ b/tests/MC/AArch64/neon-add-pairwise.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xbc, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "addp v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0xbc, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "addp v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xbc, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "addp v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0xbc, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "addp v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0xbc, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "addp v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0xbc, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "addp v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0xbc, 0xe2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "addp v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x14, 0x42, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "faddp v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x14, 0x42, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "faddp v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0xd4, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "faddp v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0xd4, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "faddp v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0xd4, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "faddp v0.2d, v1.2d, v2.2d" diff --git a/tests/MC/AArch64/neon-add-sub-instructions.s.yaml b/tests/MC/AArch64/neon-add-sub-instructions.s.yaml new file mode 100644 index 0000000000..b90a7f005a --- /dev/null +++ b/tests/MC/AArch64/neon-add-sub-instructions.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x84, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "add v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x84, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "add v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x84, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "add v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x84, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "add v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x84, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "add v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x84, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "add v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x84, 0xe2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "add v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x84, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sub v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x84, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sub v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x84, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sub v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x84, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sub v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x84, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sub v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x84, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sub v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x84, 0xe2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sub v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x14, 0x42, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fadd v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x14, 0x42, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fadd v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0xd4, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fadd v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0xd4, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fadd v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0xd4, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fadd v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x14, 0xc2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fsub v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x14, 0xc2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fsub v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0xd4, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fsub v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0xd4, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fsub v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0xd4, 0xe2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fsub v0.2d, v1.2d, v2.2d" diff --git a/tests/MC/AArch64/neon-bitwise-instructions.s.yaml b/tests/MC/AArch64/neon-bitwise-instructions.s.yaml new file mode 100644 index 0000000000..145c163136 --- /dev/null +++ b/tests/MC/AArch64/neon-bitwise-instructions.s.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x1c, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "and v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x1c, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "and v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x1c, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "orr v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x1c, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "orr v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x1c, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "eor v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x1c, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "eor v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x1c, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bit v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x1c, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bit v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x1c, 0xe2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bif v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x1c, 0xe2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bif v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x1c, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bsl v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x1c, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bsl v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x1c, 0xe2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "orn v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x1c, 0xe2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "orn v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x1c, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bic v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x1c, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bic v0.16b, v1.16b, v2.16b" diff --git a/tests/MC/AArch64/neon-compare-instructions.s.yaml b/tests/MC/AArch64/neon-compare-instructions.s.yaml new file mode 100644 index 0000000000..5cc2ae0323 --- /dev/null +++ b/tests/MC/AArch64/neon-compare-instructions.s.yaml @@ -0,0 +1,1800 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x8d, 0x31, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmeq v0.8b, v15.8b, v17.8b" + + - + input: + bytes: [ 0xe1, 0x8f, 0x28, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmeq v1.16b, v31.16b, v8.16b" + + - + input: + bytes: [ 0x0f, 0x8e, 0x71, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmeq v15.4h, v16.4h, v17.4h" + + - + input: + bytes: [ 0xc5, 0x8c, 0x67, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmeq v5.8h, v6.8h, v7.8h" + + - + input: + bytes: [ 0x7d, 0x8f, 0xbc, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmeq v29.2s, v27.2s, v28.2s" + + - + input: + bytes: [ 0xe9, 0x8c, 0xa8, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmeq v9.4s, v7.4s, v8.4s" + + - + input: + bytes: [ 0xe3, 0x8f, 0xf5, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmeq v3.2d, v31.2d, v21.2d" + + - + input: + bytes: [ 0xe0, 0x3d, 0x31, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhs v0.8b, v15.8b, v17.8b" + + - + input: + bytes: [ 0xe1, 0x3f, 0x28, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhs v1.16b, v31.16b, v8.16b" + + - + input: + bytes: [ 0x0f, 0x3e, 0x71, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhs v15.4h, v16.4h, v17.4h" + + - + input: + bytes: [ 0xc5, 0x3c, 0x67, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhs v5.8h, v6.8h, v7.8h" + + - + input: + bytes: [ 0x7d, 0x3f, 0xbc, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhs v29.2s, v27.2s, v28.2s" + + - + input: + bytes: [ 0xe9, 0x3c, 0xa8, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhs v9.4s, v7.4s, v8.4s" + + - + input: + bytes: [ 0xe3, 0x3f, 0xf5, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhs v3.2d, v31.2d, v21.2d" + + - + input: + bytes: [ 0xe0, 0x3d, 0x31, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhs v0.8b, v15.8b, v17.8b" + + - + input: + bytes: [ 0xe1, 0x3f, 0x28, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhs v1.16b, v31.16b, v8.16b" + + - + input: + bytes: [ 0x0f, 0x3e, 0x71, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhs v15.4h, v16.4h, v17.4h" + + - + input: + bytes: [ 0xc5, 0x3c, 0x67, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhs v5.8h, v6.8h, v7.8h" + + - + input: + bytes: [ 0x7d, 0x3f, 0xbc, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhs v29.2s, v27.2s, v28.2s" + + - + input: + bytes: [ 0xe9, 0x3c, 0xa8, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhs v9.4s, v7.4s, v8.4s" + + - + input: + bytes: [ 0xe3, 0x3f, 0xf5, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhs v3.2d, v31.2d, v21.2d" + + - + input: + bytes: [ 0xe0, 0x3d, 0x31, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v0.8b, v15.8b, v17.8b" + + - + input: + bytes: [ 0xe1, 0x3f, 0x28, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v1.16b, v31.16b, v8.16b" + + - + input: + bytes: [ 0x0f, 0x3e, 0x71, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v15.4h, v16.4h, v17.4h" + + - + input: + bytes: [ 0xc5, 0x3c, 0x67, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v5.8h, v6.8h, v7.8h" + + - + input: + bytes: [ 0x7d, 0x3f, 0xbc, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v29.2s, v27.2s, v28.2s" + + - + input: + bytes: [ 0xe9, 0x3c, 0xa8, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v9.4s, v7.4s, v8.4s" + + - + input: + bytes: [ 0xe3, 0x3f, 0xf5, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v3.2d, v31.2d, v21.2d" + + - + input: + bytes: [ 0xe0, 0x3d, 0x31, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v0.8b, v15.8b, v17.8b" + + - + input: + bytes: [ 0xe1, 0x3f, 0x28, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v1.16b, v31.16b, v8.16b" + + - + input: + bytes: [ 0x0f, 0x3e, 0x71, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v15.4h, v16.4h, v17.4h" + + - + input: + bytes: [ 0xc5, 0x3c, 0x67, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v5.8h, v6.8h, v7.8h" + + - + input: + bytes: [ 0x7d, 0x3f, 0xbc, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v29.2s, v27.2s, v28.2s" + + - + input: + bytes: [ 0xe9, 0x3c, 0xa8, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v9.4s, v7.4s, v8.4s" + + - + input: + bytes: [ 0xe3, 0x3f, 0xf5, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v3.2d, v31.2d, v21.2d" + + - + input: + bytes: [ 0xe0, 0x35, 0x31, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhi v0.8b, v15.8b, v17.8b" + + - + input: + bytes: [ 0xe1, 0x37, 0x28, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhi v1.16b, v31.16b, v8.16b" + + - + input: + bytes: [ 0x0f, 0x36, 0x71, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhi v15.4h, v16.4h, v17.4h" + + - + input: + bytes: [ 0xc5, 0x34, 0x67, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhi v5.8h, v6.8h, v7.8h" + + - + input: + bytes: [ 0x7d, 0x37, 0xbc, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhi v29.2s, v27.2s, v28.2s" + + - + input: + bytes: [ 0xe9, 0x34, 0xa8, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhi v9.4s, v7.4s, v8.4s" + + - + input: + bytes: [ 0xe3, 0x37, 0xf5, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhi v3.2d, v31.2d, v21.2d" + + - + input: + bytes: [ 0xe0, 0x35, 0x31, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhi v0.8b, v15.8b, v17.8b" + + - + input: + bytes: [ 0xe1, 0x37, 0x28, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhi v1.16b, v31.16b, v8.16b" + + - + input: + bytes: [ 0x0f, 0x36, 0x71, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhi v15.4h, v16.4h, v17.4h" + + - + input: + bytes: [ 0xc5, 0x34, 0x67, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhi v5.8h, v6.8h, v7.8h" + + - + input: + bytes: [ 0x7d, 0x37, 0xbc, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhi v29.2s, v27.2s, v28.2s" + + - + input: + bytes: [ 0xe9, 0x34, 0xa8, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhi v9.4s, v7.4s, v8.4s" + + - + input: + bytes: [ 0xe3, 0x37, 0xf5, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmhi v3.2d, v31.2d, v21.2d" + + - + input: + bytes: [ 0xe0, 0x35, 0x31, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v0.8b, v15.8b, v17.8b" + + - + input: + bytes: [ 0xe1, 0x37, 0x28, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v1.16b, v31.16b, v8.16b" + + - + input: + bytes: [ 0x0f, 0x36, 0x71, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v15.4h, v16.4h, v17.4h" + + - + input: + bytes: [ 0xc5, 0x34, 0x67, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v5.8h, v6.8h, v7.8h" + + - + input: + bytes: [ 0x7d, 0x37, 0xbc, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v29.2s, v27.2s, v28.2s" + + - + input: + bytes: [ 0xe9, 0x34, 0xa8, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v9.4s, v7.4s, v8.4s" + + - + input: + bytes: [ 0xe3, 0x37, 0xf5, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v3.2d, v31.2d, v21.2d" + + - + input: + bytes: [ 0xe0, 0x35, 0x31, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v0.8b, v15.8b, v17.8b" + + - + input: + bytes: [ 0xe1, 0x37, 0x28, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v1.16b, v31.16b, v8.16b" + + - + input: + bytes: [ 0x0f, 0x36, 0x71, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v15.4h, v16.4h, v17.4h" + + - + input: + bytes: [ 0xc5, 0x34, 0x67, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v5.8h, v6.8h, v7.8h" + + - + input: + bytes: [ 0x7d, 0x37, 0xbc, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v29.2s, v27.2s, v28.2s" + + - + input: + bytes: [ 0xe9, 0x34, 0xa8, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v9.4s, v7.4s, v8.4s" + + - + input: + bytes: [ 0xe3, 0x37, 0xf5, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v3.2d, v31.2d, v21.2d" + + - + input: + bytes: [ 0xe0, 0x8d, 0x31, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmtst v0.8b, v15.8b, v17.8b" + + - + input: + bytes: [ 0xe1, 0x8f, 0x28, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmtst v1.16b, v31.16b, v8.16b" + + - + input: + bytes: [ 0x0f, 0x8e, 0x71, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmtst v15.4h, v16.4h, v17.4h" + + - + input: + bytes: [ 0xc5, 0x8c, 0x67, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmtst v5.8h, v6.8h, v7.8h" + + - + input: + bytes: [ 0x7d, 0x8f, 0xbc, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmtst v29.2s, v27.2s, v28.2s" + + - + input: + bytes: [ 0xe9, 0x8c, 0xa8, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmtst v9.4s, v7.4s, v8.4s" + + - + input: + bytes: [ 0xe3, 0x8f, 0xf5, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmtst v3.2d, v31.2d, v21.2d" + + - + input: + bytes: [ 0xe0, 0x27, 0x50, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq v0.4h, v31.4h, v16.4h" + + - + input: + bytes: [ 0xe4, 0x24, 0x4f, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq v4.8h, v7.8h, v15.8h" + + - + input: + bytes: [ 0xe0, 0xe7, 0x30, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq v0.2s, v31.2s, v16.2s" + + - + input: + bytes: [ 0xe4, 0xe4, 0x2f, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq v4.4s, v7.4s, v15.4s" + + - + input: + bytes: [ 0x5d, 0xe4, 0x65, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq v29.2d, v2.2d, v5.2d" + + - + input: + bytes: [ 0x03, 0x25, 0x4c, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v3.4h, v8.4h, v12.4h" + + - + input: + bytes: [ 0xbf, 0x27, 0x5c, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v31.8h, v29.8h, v28.8h" + + - + input: + bytes: [ 0x03, 0x25, 0x4c, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v3.4h, v8.4h, v12.4h" + + - + input: + bytes: [ 0xbf, 0x27, 0x5c, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v31.8h, v29.8h, v28.8h" + + - + input: + bytes: [ 0xbf, 0xe7, 0x3c, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v31.4s, v29.4s, v28.4s" + + - + input: + bytes: [ 0x03, 0xe5, 0x2c, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v3.2s, v8.2s, v12.2s" + + - + input: + bytes: [ 0xf1, 0xe5, 0x6d, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v17.2d, v15.2d, v13.2d" + + - + input: + bytes: [ 0xbf, 0xe7, 0x3c, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v31.4s, v29.4s, v28.4s" + + - + input: + bytes: [ 0x03, 0xe5, 0x2c, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v3.2s, v8.2s, v12.2s" + + - + input: + bytes: [ 0xf1, 0xe5, 0x6d, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v17.2d, v15.2d, v13.2d" + + - + input: + bytes: [ 0xe0, 0x27, 0xd0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v0.4h, v31.4h, v16.4h" + + - + input: + bytes: [ 0xe4, 0x24, 0xcf, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v4.8h, v7.8h, v15.8h" + + - + input: + bytes: [ 0xe0, 0x27, 0xd0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v0.4h, v31.4h, v16.4h" + + - + input: + bytes: [ 0xe4, 0x24, 0xcf, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v4.8h, v7.8h, v15.8h" + + - + input: + bytes: [ 0xe0, 0xe7, 0xb0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v0.2s, v31.2s, v16.2s" + + - + input: + bytes: [ 0xe4, 0xe4, 0xaf, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v4.4s, v7.4s, v15.4s" + + - + input: + bytes: [ 0x5d, 0xe4, 0xe5, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v29.2d, v2.2d, v5.2d" + + - + input: + bytes: [ 0xe0, 0xe7, 0xb0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v0.2s, v31.2s, v16.2s" + + - + input: + bytes: [ 0xe4, 0xe4, 0xaf, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v4.4s, v7.4s, v15.4s" + + - + input: + bytes: [ 0x5d, 0xe4, 0xe5, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v29.2d, v2.2d, v5.2d" + + - + input: + bytes: [ 0xe0, 0x99, 0x20, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmeq v0.8b, v15.8b, #0" + + - + input: + bytes: [ 0xe1, 0x9b, 0x20, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmeq v1.16b, v31.16b, #0" + + - + input: + bytes: [ 0x0f, 0x9a, 0x60, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmeq v15.4h, v16.4h, #0" + + - + input: + bytes: [ 0xc5, 0x98, 0x60, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmeq v5.8h, v6.8h, #0" + + - + input: + bytes: [ 0x7d, 0x9b, 0xa0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmeq v29.2s, v27.2s, #0" + + - + input: + bytes: [ 0xe9, 0x98, 0xa0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmeq v9.4s, v7.4s, #0" + + - + input: + bytes: [ 0xe3, 0x9b, 0xe0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmeq v3.2d, v31.2d, #0" + + - + input: + bytes: [ 0xe0, 0x89, 0x20, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v0.8b, v15.8b, #0" + + - + input: + bytes: [ 0xe1, 0x8b, 0x20, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v1.16b, v31.16b, #0" + + - + input: + bytes: [ 0x0f, 0x8a, 0x60, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v15.4h, v16.4h, #0" + + - + input: + bytes: [ 0xc5, 0x88, 0x60, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v5.8h, v6.8h, #0" + + - + input: + bytes: [ 0x7d, 0x8b, 0xa0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v29.2s, v27.2s, #0" + + - + input: + bytes: [ 0x91, 0x8a, 0xa0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v17.4s, v20.4s, #0" + + - + input: + bytes: [ 0xe3, 0x8b, 0xe0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmge v3.2d, v31.2d, #0" + + - + input: + bytes: [ 0xe0, 0x89, 0x20, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v0.8b, v15.8b, #0" + + - + input: + bytes: [ 0xe1, 0x8b, 0x20, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v1.16b, v31.16b, #0" + + - + input: + bytes: [ 0x0f, 0x8a, 0x60, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v15.4h, v16.4h, #0" + + - + input: + bytes: [ 0xc5, 0x88, 0x60, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v5.8h, v6.8h, #0" + + - + input: + bytes: [ 0x7d, 0x8b, 0xa0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v29.2s, v27.2s, #0" + + - + input: + bytes: [ 0xe9, 0x88, 0xa0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v9.4s, v7.4s, #0" + + - + input: + bytes: [ 0xe3, 0x8b, 0xe0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmgt v3.2d, v31.2d, #0" + + - + input: + bytes: [ 0xe0, 0x99, 0x20, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmle v0.8b, v15.8b, #0" + + - + input: + bytes: [ 0xe1, 0x9b, 0x20, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmle v1.16b, v31.16b, #0" + + - + input: + bytes: [ 0x0f, 0x9a, 0x60, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmle v15.4h, v16.4h, #0" + + - + input: + bytes: [ 0xc5, 0x98, 0x60, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmle v5.8h, v6.8h, #0" + + - + input: + bytes: [ 0x7d, 0x9b, 0xa0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmle v29.2s, v27.2s, #0" + + - + input: + bytes: [ 0xe9, 0x98, 0xa0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmle v9.4s, v7.4s, #0" + + - + input: + bytes: [ 0xe3, 0x9b, 0xe0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmle v3.2d, v31.2d, #0" + + - + input: + bytes: [ 0xe0, 0xa9, 0x20, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmlt v0.8b, v15.8b, #0" + + - + input: + bytes: [ 0xe1, 0xab, 0x20, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmlt v1.16b, v31.16b, #0" + + - + input: + bytes: [ 0x0f, 0xaa, 0x60, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmlt v15.4h, v16.4h, #0" + + - + input: + bytes: [ 0xc5, 0xa8, 0x60, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmlt v5.8h, v6.8h, #0" + + - + input: + bytes: [ 0x7d, 0xab, 0xa0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmlt v29.2s, v27.2s, #0" + + - + input: + bytes: [ 0xe9, 0xa8, 0xa0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmlt v9.4s, v7.4s, #0" + + - + input: + bytes: [ 0xe3, 0xab, 0xe0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cmlt v3.2d, v31.2d, #0" + + - + input: + bytes: [ 0xe0, 0xdb, 0xf8, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq v0.4h, v31.4h, #0.0" + + - + input: + bytes: [ 0xe4, 0xd8, 0xf8, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq v4.8h, v7.8h, #0.0" + + - + input: + bytes: [ 0xe0, 0xdb, 0xa0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq v0.2s, v31.2s, #0.0" + + - + input: + bytes: [ 0xe4, 0xd8, 0xa0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq v4.4s, v7.4s, #0.0" + + - + input: + bytes: [ 0x5d, 0xd8, 0xe0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq v29.2d, v2.2d, #0.0" + + - + input: + bytes: [ 0xe0, 0xdb, 0xf8, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq v0.4h, v31.4h, #0.0" + + - + input: + bytes: [ 0xe4, 0xd8, 0xf8, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq v4.8h, v7.8h, #0.0" + + - + input: + bytes: [ 0xe0, 0xdb, 0xa0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq v0.2s, v31.2s, #0.0" + + - + input: + bytes: [ 0xe4, 0xd8, 0xa0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq v4.4s, v7.4s, #0.0" + + - + input: + bytes: [ 0x5d, 0xd8, 0xe0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq v29.2d, v2.2d, #0.0" + + - + input: + bytes: [ 0x03, 0xc9, 0xf8, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v3.4h, v8.4h, #0.0" + + - + input: + bytes: [ 0xbf, 0xcb, 0xf8, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v31.8h, v29.8h, #0.0" + + - + input: + bytes: [ 0xbf, 0xcb, 0xa0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v31.4s, v29.4s, #0.0" + + - + input: + bytes: [ 0x03, 0xc9, 0xa0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v3.2s, v8.2s, #0.0" + + - + input: + bytes: [ 0xf1, 0xc9, 0xe0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v17.2d, v15.2d, #0.0" + + - + input: + bytes: [ 0x03, 0xc9, 0xf8, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v3.4h, v8.4h, #0.0" + + - + input: + bytes: [ 0xbf, 0xcb, 0xf8, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v31.8h, v29.8h, #0.0" + + - + input: + bytes: [ 0xbf, 0xcb, 0xa0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v31.4s, v29.4s, #0.0" + + - + input: + bytes: [ 0x03, 0xc9, 0xa0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v3.2s, v8.2s, #0.0" + + - + input: + bytes: [ 0xf1, 0xc9, 0xe0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge v17.2d, v15.2d, #0.0" + + - + input: + bytes: [ 0xe0, 0xcb, 0xf8, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v0.4h, v31.4h, #0.0" + + - + input: + bytes: [ 0xe4, 0xc8, 0xf8, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v4.8h, v7.8h, #0.0" + + - + input: + bytes: [ 0xe0, 0xcb, 0xa0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v0.2s, v31.2s, #0.0" + + - + input: + bytes: [ 0xe4, 0xc8, 0xa0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v4.4s, v7.4s, #0.0" + + - + input: + bytes: [ 0x5d, 0xc8, 0xe0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v29.2d, v2.2d, #0.0" + + - + input: + bytes: [ 0xe0, 0xcb, 0xf8, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v0.4h, v31.4h, #0.0" + + - + input: + bytes: [ 0xe4, 0xc8, 0xf8, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v4.8h, v7.8h, #0.0" + + - + input: + bytes: [ 0xe0, 0xcb, 0xa0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v0.2s, v31.2s, #0.0" + + - + input: + bytes: [ 0xe4, 0xc8, 0xa0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v4.4s, v7.4s, #0.0" + + - + input: + bytes: [ 0x5d, 0xc8, 0xe0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt v29.2d, v2.2d, #0.0" + + - + input: + bytes: [ 0x83, 0xda, 0xf8, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmle v3.4h, v20.4h, #0.0" + + - + input: + bytes: [ 0x01, 0xd9, 0xf8, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmle v1.8h, v8.8h, #0.0" + + - + input: + bytes: [ 0x01, 0xd9, 0xa0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmle v1.4s, v8.4s, #0.0" + + - + input: + bytes: [ 0x83, 0xda, 0xa0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmle v3.2s, v20.2s, #0.0" + + - + input: + bytes: [ 0xa7, 0xd9, 0xe0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmle v7.2d, v13.2d, #0.0" + + - + input: + bytes: [ 0x83, 0xda, 0xf8, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmle v3.4h, v20.4h, #0.0" + + - + input: + bytes: [ 0x01, 0xd9, 0xf8, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmle v1.8h, v8.8h, #0.0" + + - + input: + bytes: [ 0x01, 0xd9, 0xa0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmle v1.4s, v8.4s, #0.0" + + - + input: + bytes: [ 0x83, 0xda, 0xa0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmle v3.2s, v20.2s, #0.0" + + - + input: + bytes: [ 0xa7, 0xd9, 0xe0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmle v7.2d, v13.2d, #0.0" + + - + input: + bytes: [ 0x50, 0xe8, 0xf8, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmlt v16.4h, v2.4h, #0.0" + + - + input: + bytes: [ 0x8f, 0xe8, 0xf8, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmlt v15.8h, v4.8h, #0.0" + + - + input: + bytes: [ 0x50, 0xe8, 0xa0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmlt v16.2s, v2.2s, #0.0" + + - + input: + bytes: [ 0x8f, 0xe8, 0xa0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmlt v15.4s, v4.4s, #0.0" + + - + input: + bytes: [ 0xa5, 0xeb, 0xe0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmlt v5.2d, v29.2d, #0.0" + + - + input: + bytes: [ 0x50, 0xe8, 0xf8, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmlt v16.4h, v2.4h, #0.0" + + - + input: + bytes: [ 0x8f, 0xe8, 0xf8, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmlt v15.8h, v4.8h, #0.0" + + - + input: + bytes: [ 0x50, 0xe8, 0xa0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmlt v16.2s, v2.2s, #0.0" + + - + input: + bytes: [ 0x8f, 0xe8, 0xa0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmlt v15.4s, v4.4s, #0.0" + + - + input: + bytes: [ 0xa5, 0xeb, 0xe0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmlt v5.2d, v29.2d, #0.0" diff --git a/tests/MC/AArch64/neon-crypto.s.yaml b/tests/MC/AArch64/neon-crypto.s.yaml new file mode 100644 index 0000000000..421882ae67 --- /dev/null +++ b/tests/MC/AArch64/neon-crypto.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x48, 0x28, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ] + expected: + insns: + - + asm_text: "aese v0.16b, v1.16b" + + - + input: + bytes: [ 0x20, 0x58, 0x28, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ] + expected: + insns: + - + asm_text: "aesd v0.16b, v1.16b" + + - + input: + bytes: [ 0x20, 0x68, 0x28, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ] + expected: + insns: + - + asm_text: "aesmc v0.16b, v1.16b" + + - + input: + bytes: [ 0x20, 0x78, 0x28, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ] + expected: + insns: + - + asm_text: "aesimc v0.16b, v1.16b" + + - + input: + bytes: [ 0x20, 0x08, 0x28, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ] + expected: + insns: + - + asm_text: "sha1h s0, s1" + + - + input: + bytes: [ 0x20, 0x18, 0x28, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ] + expected: + insns: + - + asm_text: "sha1su1 v0.4s, v1.4s" + + - + input: + bytes: [ 0x20, 0x28, 0x28, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ] + expected: + insns: + - + asm_text: "sha256su0 v0.4s, v1.4s" + + - + input: + bytes: [ 0x20, 0x00, 0x02, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ] + expected: + insns: + - + asm_text: "sha1c q0, s1, v2.4s" + + - + input: + bytes: [ 0x20, 0x10, 0x02, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ] + expected: + insns: + - + asm_text: "sha1p q0, s1, v2.4s" + + - + input: + bytes: [ 0x20, 0x20, 0x02, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ] + expected: + insns: + - + asm_text: "sha1m q0, s1, v2.4s" + + - + input: + bytes: [ 0x20, 0x30, 0x02, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ] + expected: + insns: + - + asm_text: "sha1su0 v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x40, 0x02, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ] + expected: + insns: + - + asm_text: "sha256h q0, q1, v2.4s" + + - + input: + bytes: [ 0x20, 0x50, 0x02, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ] + expected: + insns: + - + asm_text: "sha256h2 q0, q1, v2.4s" + + - + input: + bytes: [ 0x20, 0x60, 0x02, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ] + expected: + insns: + - + asm_text: "sha256su1 v0.4s, v1.4s, v2.4s" diff --git a/tests/MC/AArch64/neon-extract.s.yaml b/tests/MC/AArch64/neon-extract.s.yaml new file mode 100644 index 0000000000..bbf8c4b494 --- /dev/null +++ b/tests/MC/AArch64/neon-extract.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x18, 0x02, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ext v0.8b, v1.8b, v2.8b, #3" + + - + input: + bytes: [ 0x20, 0x18, 0x02, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ext v0.16b, v1.16b, v2.16b, #3" diff --git a/tests/MC/AArch64/neon-facge-facgt.s.yaml b/tests/MC/AArch64/neon-facge-facgt.s.yaml new file mode 100644 index 0000000000..465335f8fd --- /dev/null +++ b/tests/MC/AArch64/neon-facge-facgt.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x2f, 0x50, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facge v0.4h, v31.4h, v16.4h" + + - + input: + bytes: [ 0xe4, 0x2c, 0x4f, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facge v4.8h, v7.8h, v15.8h" + + - + input: + bytes: [ 0xe0, 0xef, 0x30, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facge v0.2s, v31.2s, v16.2s" + + - + input: + bytes: [ 0xe4, 0xec, 0x2f, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facge v4.4s, v7.4s, v15.4s" + + - + input: + bytes: [ 0x5d, 0xec, 0x65, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facge v29.2d, v2.2d, v5.2d" + + - + input: + bytes: [ 0xe0, 0x2f, 0x50, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facge v0.4h, v31.4h, v16.4h" + + - + input: + bytes: [ 0xe4, 0x2c, 0x4f, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facge v4.8h, v7.8h, v15.8h" + + - + input: + bytes: [ 0xe0, 0xef, 0x30, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facge v0.2s, v31.2s, v16.2s" + + - + input: + bytes: [ 0xe4, 0xec, 0x2f, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facge v4.4s, v7.4s, v15.4s" + + - + input: + bytes: [ 0x5d, 0xec, 0x65, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facge v29.2d, v2.2d, v5.2d" + + - + input: + bytes: [ 0x03, 0x2d, 0xcc, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facgt v3.4h, v8.4h, v12.4h" + + - + input: + bytes: [ 0xbf, 0x2f, 0xdc, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facgt v31.8h, v29.8h, v28.8h" + + - + input: + bytes: [ 0xbf, 0xef, 0xbc, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facgt v31.4s, v29.4s, v28.4s" + + - + input: + bytes: [ 0x03, 0xed, 0xac, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facgt v3.2s, v8.2s, v12.2s" + + - + input: + bytes: [ 0xf1, 0xed, 0xed, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facgt v17.2d, v15.2d, v13.2d" + + - + input: + bytes: [ 0x03, 0x2d, 0xcc, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facgt v3.4h, v8.4h, v12.4h" + + - + input: + bytes: [ 0xbf, 0x2f, 0xdc, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facgt v31.8h, v29.8h, v28.8h" + + - + input: + bytes: [ 0xbf, 0xef, 0xbc, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facgt v31.4s, v29.4s, v28.4s" + + - + input: + bytes: [ 0x03, 0xed, 0xac, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facgt v3.2s, v8.2s, v12.2s" + + - + input: + bytes: [ 0xf1, 0xed, 0xed, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facgt v17.2d, v15.2d, v13.2d" diff --git a/tests/MC/AArch64/neon-frsqrt-frecp.s.yaml b/tests/MC/AArch64/neon-frsqrt-frecp.s.yaml new file mode 100644 index 0000000000..45e36b5f71 --- /dev/null +++ b/tests/MC/AArch64/neon-frsqrt-frecp.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x3f, 0xd0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frsqrts v0.4h, v31.4h, v16.4h" + + - + input: + bytes: [ 0xe4, 0x3c, 0xcf, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frsqrts v4.8h, v7.8h, v15.8h" + + - + input: + bytes: [ 0xe0, 0xff, 0xb0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frsqrts v0.2s, v31.2s, v16.2s" + + - + input: + bytes: [ 0xe4, 0xfc, 0xaf, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frsqrts v4.4s, v7.4s, v15.4s" + + - + input: + bytes: [ 0x5d, 0xfc, 0xe5, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frsqrts v29.2d, v2.2d, v5.2d" + + - + input: + bytes: [ 0x03, 0x3d, 0x4c, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecps v3.4h, v8.4h, v12.4h" + + - + input: + bytes: [ 0xbf, 0x3f, 0x5c, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecps v31.8h, v29.8h, v28.8h" + + - + input: + bytes: [ 0xbf, 0xff, 0x3c, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecps v31.4s, v29.4s, v28.4s" + + - + input: + bytes: [ 0x03, 0xfd, 0x2c, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecps v3.2s, v8.2s, v12.2s" + + - + input: + bytes: [ 0xf1, 0xfd, 0x6d, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecps v17.2d, v15.2d, v13.2d" diff --git a/tests/MC/AArch64/neon-halving-add-sub.s.yaml b/tests/MC/AArch64/neon-halving-add-sub.s.yaml new file mode 100644 index 0000000000..1cfe9cf6b5 --- /dev/null +++ b/tests/MC/AArch64/neon-halving-add-sub.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x04, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shadd v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x04, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shadd v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x04, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shadd v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x04, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shadd v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x04, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shadd v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x04, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shadd v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x04, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uhadd v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x04, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uhadd v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x04, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uhadd v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x04, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uhadd v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x04, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uhadd v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x04, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uhadd v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x24, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shsub v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x24, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shsub v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x24, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shsub v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x24, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shsub v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x24, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shsub v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x24, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shsub v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x24, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uhsub v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x24, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uhsub v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x24, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uhsub v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x24, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uhsub v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x24, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uhsub v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x24, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uhsub v0.4s, v1.4s, v2.4s" diff --git a/tests/MC/AArch64/neon-max-min-pairwise.s.yaml b/tests/MC/AArch64/neon-max-min-pairwise.s.yaml new file mode 100644 index 0000000000..768467ddd1 --- /dev/null +++ b/tests/MC/AArch64/neon-max-min-pairwise.s.yaml @@ -0,0 +1,440 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa4, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smaxp v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0xa4, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smaxp v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xa4, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smaxp v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0xa4, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smaxp v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0xa4, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smaxp v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0xa4, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smaxp v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0xa4, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umaxp v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0xa4, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umaxp v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xa4, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umaxp v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0xa4, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umaxp v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0xa4, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umaxp v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0xa4, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umaxp v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0xac, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sminp v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0xac, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sminp v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xac, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sminp v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0xac, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sminp v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0xac, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sminp v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0xac, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sminp v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0xac, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uminp v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0xac, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uminp v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0xac, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uminp v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0xac, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uminp v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0xac, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uminp v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0xac, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uminp v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x34, 0x42, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxp v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0xff, 0x35, 0x50, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxp v31.8h, v15.8h, v16.8h" + + - + input: + bytes: [ 0x20, 0xf4, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxp v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0xff, 0xf5, 0x30, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxp v31.4s, v15.4s, v16.4s" + + - + input: + bytes: [ 0x07, 0xf5, 0x79, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxp v7.2d, v8.2d, v25.2d" + + - + input: + bytes: [ 0xea, 0x35, 0xd6, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminp v10.4h, v15.4h, v22.4h" + + - + input: + bytes: [ 0xa3, 0x34, 0xc6, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminp v3.8h, v5.8h, v6.8h" + + - + input: + bytes: [ 0xea, 0xf5, 0xb6, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminp v10.2s, v15.2s, v22.2s" + + - + input: + bytes: [ 0xa3, 0xf4, 0xa6, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminp v3.4s, v5.4s, v6.4s" + + - + input: + bytes: [ 0xb1, 0xf5, 0xe2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminp v17.2d, v13.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x04, 0x42, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxnmp v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0xff, 0x05, 0x50, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxnmp v31.8h, v15.8h, v16.8h" + + - + input: + bytes: [ 0x20, 0xc4, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxnmp v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0xff, 0xc5, 0x30, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxnmp v31.4s, v15.4s, v16.4s" + + - + input: + bytes: [ 0x07, 0xc5, 0x79, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxnmp v7.2d, v8.2d, v25.2d" + + - + input: + bytes: [ 0xea, 0x05, 0xd6, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminnmp v10.4h, v15.4h, v22.4h" + + - + input: + bytes: [ 0xa3, 0x04, 0xc6, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminnmp v3.8h, v5.8h, v6.8h" + + - + input: + bytes: [ 0xea, 0xc5, 0xb6, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminnmp v10.2s, v15.2s, v22.2s" + + - + input: + bytes: [ 0xa3, 0xc4, 0xa6, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminnmp v3.4s, v5.4s, v6.4s" + + - + input: + bytes: [ 0xb1, 0xc5, 0xe2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminnmp v17.2d, v13.2d, v2.2d" diff --git a/tests/MC/AArch64/neon-max-min.s.yaml b/tests/MC/AArch64/neon-max-min.s.yaml new file mode 100644 index 0000000000..a7b373ca05 --- /dev/null +++ b/tests/MC/AArch64/neon-max-min.s.yaml @@ -0,0 +1,440 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x64, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smax v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x64, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smax v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x64, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smax v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x64, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smax v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x64, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smax v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x64, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smax v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x64, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umax v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x64, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umax v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x64, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umax v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x64, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umax v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x64, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umax v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x64, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umax v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x6c, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smin v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x6c, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smin v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x6c, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smin v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x6c, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smin v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x6c, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smin v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x6c, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "smin v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x6c, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umin v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x6c, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umin v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x6c, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umin v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x6c, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umin v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x6c, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umin v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x6c, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "umin v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x34, 0x42, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmax v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x34, 0x42, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmax v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0xf4, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmax v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0xff, 0xf5, 0x30, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmax v31.4s, v15.4s, v16.4s" + + - + input: + bytes: [ 0x07, 0xf5, 0x79, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmax v7.2d, v8.2d, v25.2d" + + - + input: + bytes: [ 0xea, 0x35, 0xd6, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmin v10.4h, v15.4h, v22.4h" + + - + input: + bytes: [ 0xea, 0x35, 0xd6, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmin v10.8h, v15.8h, v22.8h" + + - + input: + bytes: [ 0xea, 0xf5, 0xb6, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmin v10.2s, v15.2s, v22.2s" + + - + input: + bytes: [ 0xa3, 0xf4, 0xa6, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmin v3.4s, v5.4s, v6.4s" + + - + input: + bytes: [ 0xb1, 0xf5, 0xe2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmin v17.2d, v13.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x04, 0x42, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxnm v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x04, 0x42, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxnm v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0xc4, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxnm v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0xff, 0xc5, 0x30, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxnm v31.4s, v15.4s, v16.4s" + + - + input: + bytes: [ 0x07, 0xc5, 0x79, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmaxnm v7.2d, v8.2d, v25.2d" + + - + input: + bytes: [ 0xea, 0x05, 0xd6, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminnm v10.4h, v15.4h, v22.4h" + + - + input: + bytes: [ 0xea, 0x05, 0xd6, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminnm v10.8h, v15.8h, v22.8h" + + - + input: + bytes: [ 0xea, 0xc5, 0xb6, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminnm v10.2s, v15.2s, v22.2s" + + - + input: + bytes: [ 0xa3, 0xc4, 0xa6, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminnm v3.4s, v5.4s, v6.4s" + + - + input: + bytes: [ 0xb1, 0xc5, 0xe2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fminnm v17.2d, v13.2d, v2.2d" diff --git a/tests/MC/AArch64/neon-mla-mls-instructions.s.yaml b/tests/MC/AArch64/neon-mla-mls-instructions.s.yaml new file mode 100644 index 0000000000..647c1e4d00 --- /dev/null +++ b/tests/MC/AArch64/neon-mla-mls-instructions.s.yaml @@ -0,0 +1,220 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x94, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mla v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mla v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mla v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x94, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mla v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x94, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mla v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x94, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mla v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x94, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mls v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x94, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mls v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x94, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mls v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x94, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mls v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x94, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mls v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x94, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mls v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x0c, 0x42, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x0c, 0x42, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0xcc, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0xcc, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0xcc, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x0c, 0xc2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x0c, 0xc2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0xcc, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0xcc, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0xcc, 0xe2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls v0.2d, v1.2d, v2.2d" diff --git a/tests/MC/AArch64/neon-mov.s.yaml b/tests/MC/AArch64/neon-mov.s.yaml new file mode 100644 index 0000000000..5bb1c9b410 --- /dev/null +++ b/tests/MC/AArch64/neon-mov.s.yaml @@ -0,0 +1,730 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x04, 0x00, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v0.2s, #1" + + - + input: + bytes: [ 0x01, 0x04, 0x00, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v1.2s, #0" + + - + input: + bytes: [ 0x2f, 0x24, 0x00, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v15.2s, #1, lsl #8" + + - + input: + bytes: [ 0x30, 0x44, 0x00, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v16.2s, #1, lsl #16" + + - + input: + bytes: [ 0x3f, 0x64, 0x00, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v31.2s, #1, lsl #24" + + - + input: + bytes: [ 0x20, 0x04, 0x00, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v0.4s, #1" + + - + input: + bytes: [ 0x20, 0x24, 0x00, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v0.4s, #1, lsl #8" + + - + input: + bytes: [ 0x20, 0x44, 0x00, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v0.4s, #1, lsl #16" + + - + input: + bytes: [ 0x20, 0x64, 0x00, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v0.4s, #1, lsl #24" + + - + input: + bytes: [ 0x20, 0x84, 0x00, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v0.4h, #1" + + - + input: + bytes: [ 0x20, 0xa4, 0x00, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v0.4h, #1, lsl #8" + + - + input: + bytes: [ 0x20, 0x84, 0x00, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v0.8h, #1" + + - + input: + bytes: [ 0x20, 0xa4, 0x00, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v0.8h, #1, lsl #8" + + - + input: + bytes: [ 0x20, 0x04, 0x00, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mvni v0.2s, #1" + + - + input: + bytes: [ 0x01, 0x04, 0x00, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mvni v1.2s, #0" + + - + input: + bytes: [ 0x20, 0x24, 0x00, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mvni v0.2s, #1, lsl #8" + + - + input: + bytes: [ 0x20, 0x44, 0x00, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mvni v0.2s, #1, lsl #16" + + - + input: + bytes: [ 0x20, 0x64, 0x00, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mvni v0.2s, #1, lsl #24" + + - + input: + bytes: [ 0x20, 0x04, 0x00, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mvni v0.4s, #1" + + - + input: + bytes: [ 0x2f, 0x24, 0x00, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mvni v15.4s, #1, lsl #8" + + - + input: + bytes: [ 0x30, 0x44, 0x00, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mvni v16.4s, #1, lsl #16" + + - + input: + bytes: [ 0x3f, 0x64, 0x00, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mvni v31.4s, #1, lsl #24" + + - + input: + bytes: [ 0x20, 0x84, 0x00, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mvni v0.4h, #1" + + - + input: + bytes: [ 0x20, 0xa4, 0x00, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mvni v0.4h, #1, lsl #8" + + - + input: + bytes: [ 0x20, 0x84, 0x00, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mvni v0.8h, #1" + + - + input: + bytes: [ 0x20, 0xa4, 0x00, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mvni v0.8h, #1, lsl #8" + + - + input: + bytes: [ 0x20, 0x14, 0x00, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bic v0.2s, #1" + + - + input: + bytes: [ 0x01, 0x14, 0x00, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bic v1.2s, #0" + + - + input: + bytes: [ 0x20, 0x34, 0x00, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bic v0.2s, #1, lsl #8" + + - + input: + bytes: [ 0x20, 0x54, 0x00, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bic v0.2s, #1, lsl #16" + + - + input: + bytes: [ 0x20, 0x74, 0x00, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bic v0.2s, #1, lsl #24" + + - + input: + bytes: [ 0x20, 0x14, 0x00, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bic v0.4s, #1" + + - + input: + bytes: [ 0x20, 0x34, 0x00, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bic v0.4s, #1, lsl #8" + + - + input: + bytes: [ 0x20, 0x54, 0x00, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bic v0.4s, #1, lsl #16" + + - + input: + bytes: [ 0x20, 0x74, 0x00, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bic v0.4s, #1, lsl #24" + + - + input: + bytes: [ 0x2f, 0x94, 0x00, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bic v15.4h, #1" + + - + input: + bytes: [ 0x30, 0xb4, 0x00, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bic v16.4h, #1, lsl #8" + + - + input: + bytes: [ 0x20, 0x94, 0x00, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bic v0.8h, #1" + + - + input: + bytes: [ 0x3f, 0xb4, 0x00, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "bic v31.8h, #1, lsl #8" + + - + input: + bytes: [ 0x20, 0x14, 0x00, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "orr v0.2s, #1" + + - + input: + bytes: [ 0x01, 0x14, 0x00, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "orr v1.2s, #0" + + - + input: + bytes: [ 0x20, 0x34, 0x00, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "orr v0.2s, #1, lsl #8" + + - + input: + bytes: [ 0x20, 0x54, 0x00, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "orr v0.2s, #1, lsl #16" + + - + input: + bytes: [ 0x20, 0x74, 0x00, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "orr v0.2s, #1, lsl #24" + + - + input: + bytes: [ 0x20, 0x14, 0x00, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "orr v0.4s, #1" + + - + input: + bytes: [ 0x20, 0x34, 0x00, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "orr v0.4s, #1, lsl #8" + + - + input: + bytes: [ 0x20, 0x54, 0x00, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "orr v0.4s, #1, lsl #16" + + - + input: + bytes: [ 0x20, 0x74, 0x00, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "orr v0.4s, #1, lsl #24" + + - + input: + bytes: [ 0x3f, 0x94, 0x00, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "orr v31.4h, #1" + + - + input: + bytes: [ 0x2f, 0xb4, 0x00, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "orr v15.4h, #1, lsl #8" + + - + input: + bytes: [ 0x20, 0x94, 0x00, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "orr v0.8h, #1" + + - + input: + bytes: [ 0x30, 0xb4, 0x00, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "orr v16.8h, #1, lsl #8" + + - + input: + bytes: [ 0x20, 0xc4, 0x00, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v0.2s, #1, msl #8" + + - + input: + bytes: [ 0x21, 0xd4, 0x00, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v1.2s, #1, msl #16" + + - + input: + bytes: [ 0x20, 0xc4, 0x00, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v0.4s, #1, msl #8" + + - + input: + bytes: [ 0x3f, 0xd4, 0x00, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v31.4s, #1, msl #16" + + - + input: + bytes: [ 0x21, 0xc4, 0x00, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mvni v1.2s, #1, msl #8" + + - + input: + bytes: [ 0x20, 0xd4, 0x00, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mvni v0.2s, #1, msl #16" + + - + input: + bytes: [ 0x3f, 0xc4, 0x00, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mvni v31.4s, #1, msl #8" + + - + input: + bytes: [ 0x20, 0xd4, 0x00, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mvni v0.4s, #1, msl #16" + + - + input: + bytes: [ 0x00, 0xe4, 0x00, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v0.8b, #0" + + - + input: + bytes: [ 0xff, 0xe7, 0x07, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v31.8b, #255" + + - + input: + bytes: [ 0xef, 0xe5, 0x00, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v15.16b, #15" + + - + input: + bytes: [ 0xff, 0xe7, 0x00, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v31.16b, #31" + + - + input: + bytes: [ 0x40, 0xe5, 0x05, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi v0.2d, #0xff00ff00ff00ff00" + + - + input: + bytes: [ 0x40, 0xe5, 0x05, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "movi d0, #0xff00ff00ff00ff00" + + - + input: + bytes: [ 0x01, 0xf6, 0x03, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "fmov v1.2s, #1.00000000" + + - + input: + bytes: [ 0x0f, 0xf6, 0x03, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "fmov v15.4s, #1.00000000" + + - + input: + bytes: [ 0x1f, 0xf6, 0x03, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "fmov v31.2d, #1.00000000" + + - + input: + bytes: [ 0xe0, 0x1f, 0xbf, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v0.8b, v31.8b" + + - + input: + bytes: [ 0x0f, 0x1e, 0xb0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v15.16b, v16.16b" + + - + input: + bytes: [ 0xe0, 0x1f, 0xbf, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v0.8b, v31.8b" + + - + input: + bytes: [ 0x0f, 0x1e, 0xb0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v15.16b, v16.16b" diff --git a/tests/MC/AArch64/neon-mul-div-instructions.s.yaml b/tests/MC/AArch64/neon-mul-div-instructions.s.yaml new file mode 100644 index 0000000000..9e3e4c5791 --- /dev/null +++ b/tests/MC/AArch64/neon-mul-div-instructions.s.yaml @@ -0,0 +1,230 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x9c, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mul v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x9c, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mul v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x9c, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mul v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x9c, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mul v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x9c, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mul v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x9c, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mul v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0xdc, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "fmul v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0xdc, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "fmul v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0xdc, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "fmul v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0xfc, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "fdiv v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0xfc, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "fdiv v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0xfc, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "fdiv v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0xf1, 0x9f, 0x30, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "pmul v17.8b, v31.8b, v16.8b" + + - + input: + bytes: [ 0x20, 0x9c, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "pmul v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x22, 0xb7, 0x63, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmulh v2.4h, v25.4h, v3.4h" + + - + input: + bytes: [ 0xac, 0xb4, 0x6d, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmulh v12.8h, v5.8h, v13.8h" + + - + input: + bytes: [ 0x23, 0xb4, 0xbe, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmulh v3.2s, v1.2s, v30.2s" + + - + input: + bytes: [ 0x22, 0xb7, 0x63, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrdmulh v2.4h, v25.4h, v3.4h" + + - + input: + bytes: [ 0xac, 0xb4, 0x6d, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrdmulh v12.8h, v5.8h, v13.8h" + + - + input: + bytes: [ 0x23, 0xb4, 0xbe, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrdmulh v3.2s, v1.2s, v30.2s" + + - + input: + bytes: [ 0xb5, 0xdc, 0x2d, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "fmulx v21.2s, v5.2s, v13.2s" + + - + input: + bytes: [ 0x21, 0xdf, 0x23, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "fmulx v1.4s, v25.4s, v3.4s" + + - + input: + bytes: [ 0xdf, 0xde, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "fmulx v31.2d, v22.2d, v2.2d" diff --git a/tests/MC/AArch64/neon-perm.s.yaml b/tests/MC/AArch64/neon-perm.s.yaml new file mode 100644 index 0000000000..989341c356 --- /dev/null +++ b/tests/MC/AArch64/neon-perm.s.yaml @@ -0,0 +1,420 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x18, 0x02, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "uzp1 v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x18, 0x02, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "uzp1 v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x18, 0x42, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "uzp1 v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x18, 0x42, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "uzp1 v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x18, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "uzp1 v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x18, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "uzp1 v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x18, 0xc2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "uzp1 v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x28, 0x02, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "trn1 v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x28, 0x02, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "trn1 v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x28, 0x42, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "trn1 v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x28, 0x42, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "trn1 v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x28, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "trn1 v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x28, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "trn1 v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x28, 0xc2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "trn1 v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x38, 0x02, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "zip1 v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x38, 0x02, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "zip1 v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x38, 0x42, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "zip1 v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x38, 0x42, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "zip1 v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x38, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "zip1 v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x38, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "zip1 v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x38, 0xc2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "zip1 v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x58, 0x02, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "uzp2 v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x58, 0x02, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "uzp2 v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x58, 0x42, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "uzp2 v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x58, 0x42, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "uzp2 v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x58, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "uzp2 v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x58, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "uzp2 v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x58, 0xc2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "uzp2 v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x68, 0x02, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "trn2 v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x68, 0x02, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "trn2 v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x68, 0x42, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "trn2 v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x68, 0x42, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "trn2 v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x68, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "trn2 v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x68, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "trn2 v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x68, 0xc2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "trn2 v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x78, 0x02, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "zip2 v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x78, 0x02, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "zip2 v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x78, 0x42, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "zip2 v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x78, 0x42, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "zip2 v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x78, 0x82, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "zip2 v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x78, 0x82, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "zip2 v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x78, 0xc2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "zip2 v0.2d, v1.2d, v2.2d" diff --git a/tests/MC/AArch64/neon-rounding-halving-add.s.yaml b/tests/MC/AArch64/neon-rounding-halving-add.s.yaml new file mode 100644 index 0000000000..45430adc8b --- /dev/null +++ b/tests/MC/AArch64/neon-rounding-halving-add.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x14, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "srhadd v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x14, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "srhadd v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x14, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "srhadd v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x14, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "srhadd v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x14, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "srhadd v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x14, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "srhadd v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x14, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "urhadd v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x14, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "urhadd v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x14, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "urhadd v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x14, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "urhadd v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x14, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "urhadd v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x14, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "urhadd v0.4s, v1.4s, v2.4s" diff --git a/tests/MC/AArch64/neon-rounding-shift.s.yaml b/tests/MC/AArch64/neon-rounding-shift.s.yaml new file mode 100644 index 0000000000..8b15af0727 --- /dev/null +++ b/tests/MC/AArch64/neon-rounding-shift.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x54, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "srshl v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x54, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "srshl v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x54, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "srshl v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x54, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "srshl v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x54, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "srshl v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x54, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "srshl v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x54, 0xe2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "srshl v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x54, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "urshl v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x54, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "urshl v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x54, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "urshl v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x54, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "urshl v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x54, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "urshl v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x54, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "urshl v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x54, 0xe2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "urshl v0.2d, v1.2d, v2.2d" diff --git a/tests/MC/AArch64/neon-saturating-add-sub.s.yaml b/tests/MC/AArch64/neon-saturating-add-sub.s.yaml new file mode 100644 index 0000000000..df44702a6f --- /dev/null +++ b/tests/MC/AArch64/neon-saturating-add-sub.s.yaml @@ -0,0 +1,280 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x0c, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqadd v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x0c, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqadd v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x0c, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqadd v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x0c, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqadd v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x0c, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqadd v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x0c, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqadd v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x0c, 0xe2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqadd v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x0c, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqadd v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x0c, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqadd v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x0c, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqadd v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x0c, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqadd v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x0c, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqadd v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x0c, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqadd v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x0c, 0xe2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqadd v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x2c, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqsub v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x2c, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqsub v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x2c, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqsub v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x2c, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqsub v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x2c, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqsub v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x2c, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqsub v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x2c, 0xe2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqsub v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x2c, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqsub v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x2c, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqsub v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x2c, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqsub v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x2c, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqsub v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x2c, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqsub v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x2c, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqsub v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x2c, 0xe2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqsub v0.2d, v1.2d, v2.2d" diff --git a/tests/MC/AArch64/neon-saturating-rounding-shift.s.yaml b/tests/MC/AArch64/neon-saturating-rounding-shift.s.yaml new file mode 100644 index 0000000000..b8a9b7bb7c --- /dev/null +++ b/tests/MC/AArch64/neon-saturating-rounding-shift.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x5c, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrshl v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x5c, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrshl v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x5c, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrshl v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x5c, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrshl v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x5c, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrshl v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x5c, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrshl v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x5c, 0xe2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrshl v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x5c, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqrshl v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x5c, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqrshl v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x5c, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqrshl v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x5c, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqrshl v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x5c, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqrshl v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x5c, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqrshl v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x5c, 0xe2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqrshl v0.2d, v1.2d, v2.2d" diff --git a/tests/MC/AArch64/neon-saturating-shift.s.yaml b/tests/MC/AArch64/neon-saturating-shift.s.yaml new file mode 100644 index 0000000000..589d7b3d2d --- /dev/null +++ b/tests/MC/AArch64/neon-saturating-shift.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x4c, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshl v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x4c, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshl v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x4c, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshl v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x4c, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshl v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x4c, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshl v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x4c, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshl v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x4c, 0xe2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshl v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x4c, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqshl v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x4c, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqshl v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x4c, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqshl v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x4c, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqshl v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x4c, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqshl v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x4c, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqshl v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x4c, 0xe2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqshl v0.2d, v1.2d, v2.2d" diff --git a/tests/MC/AArch64/neon-scalar-abs.s.yaml b/tests/MC/AArch64/neon-scalar-abs.s.yaml new file mode 100644 index 0000000000..ca92632a86 --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-abs.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x1d, 0xbb, 0xe0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "abs d29, d24" + + - + input: + bytes: [ 0x1d, 0x17, 0xd4, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fabd h29, h24, h20" + + - + input: + bytes: [ 0x1d, 0xd7, 0xb4, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fabd s29, s24, s20" + + - + input: + bytes: [ 0x1d, 0xd7, 0xf4, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fabd d29, d24, d20" + + - + input: + bytes: [ 0xd3, 0x79, 0x20, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqabs b19, b14" + + - + input: + bytes: [ 0xf5, 0x79, 0x60, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqabs h21, h15" + + - + input: + bytes: [ 0x94, 0x79, 0xa0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqabs s20, s12" + + - + input: + bytes: [ 0x92, 0x79, 0xe0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqabs d18, d12" diff --git a/tests/MC/AArch64/neon-scalar-add-sub.s.yaml b/tests/MC/AArch64/neon-scalar-add-sub.s.yaml new file mode 100644 index 0000000000..eff424950f --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-add-sub.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x1f, 0x84, 0xf0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "add d31, d0, d16" + + - + input: + bytes: [ 0xe1, 0x84, 0xe8, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sub d1, d7, d8" diff --git a/tests/MC/AArch64/neon-scalar-by-elem-mla.s.yaml b/tests/MC/AArch64/neon-scalar-by-elem-mla.s.yaml new file mode 100644 index 0000000000..9c3103c993 --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-by-elem-mla.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x18, 0x11, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla h0, h1, v1.h[5]" + + - + input: + bytes: [ 0x20, 0x10, 0x81, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla s0, s1, v1.s[0]" + + - + input: + bytes: [ 0x7e, 0x11, 0xa1, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla s30, s11, v1.s[1]" + + - + input: + bytes: [ 0xa4, 0x18, 0x87, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla s4, s5, v7.s[2]" + + - + input: + bytes: [ 0xd0, 0x1a, 0xb0, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla s16, s22, v16.s[3]" + + - + input: + bytes: [ 0x20, 0x10, 0xc1, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla d0, d1, v1.d[0]" + + - + input: + bytes: [ 0x7e, 0x19, 0xc1, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmla d30, d11, v1.d[1]" + + - + input: + bytes: [ 0x62, 0x58, 0x14, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls h2, h3, v4.h[5]" + + - + input: + bytes: [ 0x62, 0x50, 0x84, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls s2, s3, v4.s[0]" + + - + input: + bytes: [ 0x5d, 0x51, 0xbc, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls s29, s10, v28.s[1]" + + - + input: + bytes: [ 0x85, 0x59, 0x97, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls s5, s12, v23.s[2]" + + - + input: + bytes: [ 0x27, 0x5a, 0xba, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls s7, s17, v26.s[3]" + + - + input: + bytes: [ 0x20, 0x50, 0xc1, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls d0, d1, v1.d[0]" + + - + input: + bytes: [ 0x7e, 0x59, 0xc1, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmls d30, d11, v1.d[1]" diff --git a/tests/MC/AArch64/neon-scalar-by-elem-mul.s.yaml b/tests/MC/AArch64/neon-scalar-by-elem-mul.s.yaml new file mode 100644 index 0000000000..248de73b93 --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-by-elem-mul.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x98, 0x11, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmul h0, h1, v1.h[5]" + + - + input: + bytes: [ 0x20, 0x90, 0x81, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmul s0, s1, v1.s[0]" + + - + input: + bytes: [ 0x7e, 0x91, 0xa1, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmul s30, s11, v1.s[1]" + + - + input: + bytes: [ 0xa4, 0x98, 0x87, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmul s4, s5, v7.s[2]" + + - + input: + bytes: [ 0xd0, 0x9a, 0xb0, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmul s16, s22, v16.s[3]" + + - + input: + bytes: [ 0x20, 0x90, 0xc1, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmul d0, d1, v1.d[0]" + + - + input: + bytes: [ 0x7e, 0x99, 0xc1, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmul d30, d11, v1.d[1]" + + - + input: + bytes: [ 0x46, 0x98, 0x18, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmulx h6, h2, v8.h[5]" + + - + input: + bytes: [ 0x46, 0x90, 0x88, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmulx s6, s2, v8.s[0]" + + - + input: + bytes: [ 0x67, 0x90, 0xad, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmulx s7, s3, v13.s[1]" + + - + input: + bytes: [ 0xe9, 0x98, 0x89, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmulx s9, s7, v9.s[2]" + + - + input: + bytes: [ 0xad, 0x9a, 0xaa, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmulx s13, s21, v10.s[3]" + + - + input: + bytes: [ 0x2f, 0x91, 0xc7, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmulx d15, d9, v7.d[0]" + + - + input: + bytes: [ 0x8d, 0x99, 0xcb, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmulx d13, d12, v11.d[1]" diff --git a/tests/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.yaml b/tests/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.yaml new file mode 100644 index 0000000000..11319c5445 --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x30, 0x40, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmlal s0, h0, v0.h[0]" + + - + input: + bytes: [ 0x27, 0x30, 0x74, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmlal s7, h1, v4.h[3]" + + - + input: + bytes: [ 0x0b, 0x3a, 0x48, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmlal s11, h16, v8.h[4]" + + - + input: + bytes: [ 0xde, 0x3b, 0x7f, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmlal s30, h30, v15.h[7]" + + - + input: + bytes: [ 0x00, 0x30, 0x83, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmlal d0, s0, v3.s[0]" + + - + input: + bytes: [ 0xde, 0x3b, 0xbe, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmlal d30, s30, v30.s[3]" + + - + input: + bytes: [ 0x28, 0x31, 0xae, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmlal d8, s9, v14.s[1]" + + - + input: + bytes: [ 0x21, 0x70, 0x41, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmlsl s1, h1, v1.h[0]" + + - + input: + bytes: [ 0x48, 0x70, 0x55, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmlsl s8, h2, v5.h[1]" + + - + input: + bytes: [ 0xac, 0x71, 0x6e, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmlsl s12, h13, v14.h[2]" + + - + input: + bytes: [ 0x9d, 0x7b, 0x7b, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmlsl s29, h28, v11.h[7]" + + - + input: + bytes: [ 0x21, 0x70, 0x8d, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmlsl d1, s1, v13.s[0]" + + - + input: + bytes: [ 0xff, 0x7b, 0x9f, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmlsl d31, s31, v31.s[2]" + + - + input: + bytes: [ 0x50, 0x7a, 0xbc, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmlsl d16, s18, v28.s[3]" diff --git a/tests/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.yaml b/tests/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.yaml new file mode 100644 index 0000000000..4cafebde7f --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.yaml @@ -0,0 +1,170 @@ +test_cases: + - + input: + bytes: [ 0x21, 0xb0, 0x51, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmull s1, h1, v1.h[1]" + + - + input: + bytes: [ 0x48, 0xb0, 0x65, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmull s8, h2, v5.h[2]" + + - + input: + bytes: [ 0x2c, 0xb2, 0x79, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmull s12, h17, v9.h[3]" + + - + input: + bytes: [ 0xff, 0xbb, 0x7f, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmull s31, h31, v15.h[7]" + + - + input: + bytes: [ 0x21, 0xb0, 0x84, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmull d1, s1, v4.s[0]" + + - + input: + bytes: [ 0xff, 0xbb, 0xbf, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmull d31, s31, v31.s[3]" + + - + input: + bytes: [ 0x49, 0xb1, 0x8f, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmull d9, s10, v15.s[0]" + + - + input: + bytes: [ 0x20, 0xc0, 0x40, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmulh h0, h1, v0.h[0]" + + - + input: + bytes: [ 0x6a, 0xc9, 0x4a, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmulh h10, h11, v10.h[4]" + + - + input: + bytes: [ 0xb4, 0xca, 0x7f, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmulh h20, h21, v15.h[7]" + + - + input: + bytes: [ 0x59, 0xcb, 0xbb, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmulh s25, s26, v27.s[3]" + + - + input: + bytes: [ 0xc2, 0xc0, 0x87, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqdmulh s2, s6, v7.s[0]" + + - + input: + bytes: [ 0xdf, 0xd3, 0x6e, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrdmulh h31, h30, v14.h[2]" + + - + input: + bytes: [ 0x21, 0xd8, 0x41, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrdmulh h1, h1, v1.h[4]" + + - + input: + bytes: [ 0xd5, 0xda, 0x7f, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrdmulh h21, h22, v15.h[7]" + + - + input: + bytes: [ 0xc5, 0xd8, 0x87, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrdmulh s5, s6, v7.s[2]" + + - + input: + bytes: [ 0x54, 0xd3, 0xbb, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrdmulh s20, s26, v27.s[1]" diff --git a/tests/MC/AArch64/neon-scalar-compare.s.yaml b/tests/MC/AArch64/neon-scalar-compare.s.yaml new file mode 100644 index 0000000000..ad71b7d671 --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-compare.s.yaml @@ -0,0 +1,110 @@ +test_cases: + - + input: + bytes: [ 0xb4, 0x8e, 0xf6, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "cmeq d20, d21, d22" + + - + input: + bytes: [ 0xb4, 0x9a, 0xe0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "cmeq d20, d21, #0" + + - + input: + bytes: [ 0xb4, 0x3e, 0xf6, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "cmhs d20, d21, d22" + + - + input: + bytes: [ 0xb4, 0x3e, 0xf6, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "cmge d20, d21, d22" + + - + input: + bytes: [ 0xb4, 0x8a, 0xe0, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "cmge d20, d21, #0" + + - + input: + bytes: [ 0xb4, 0x36, 0xf6, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "cmhi d20, d21, d22" + + - + input: + bytes: [ 0xb4, 0x36, 0xf6, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "cmgt d20, d21, d22" + + - + input: + bytes: [ 0xb4, 0x8a, 0xe0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "cmgt d20, d21, #0" + + - + input: + bytes: [ 0xb4, 0x9a, 0xe0, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "cmle d20, d21, #0" + + - + input: + bytes: [ 0xb4, 0xaa, 0xe0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "cmlt d20, d21, #0" + + - + input: + bytes: [ 0xb4, 0x8e, 0xf6, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "cmtst d20, d21, d22" diff --git a/tests/MC/AArch64/neon-scalar-cvt.s.yaml b/tests/MC/AArch64/neon-scalar-cvt.s.yaml new file mode 100644 index 0000000000..8d8c06e5a6 --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-cvt.s.yaml @@ -0,0 +1,490 @@ +test_cases: + - + input: + bytes: [ 0xd7, 0xd9, 0x79, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "scvtf h23, h14" + + - + input: + bytes: [ 0xb6, 0xd9, 0x21, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "scvtf s22, s13" + + - + input: + bytes: [ 0x95, 0xd9, 0x61, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "scvtf d21, d12" + + - + input: + bytes: [ 0x94, 0xd9, 0x79, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ucvtf h20, h12" + + - + input: + bytes: [ 0xb6, 0xd9, 0x21, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ucvtf s22, s13" + + - + input: + bytes: [ 0xd5, 0xd9, 0x61, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ucvtf d21, d14" + + - + input: + bytes: [ 0xb6, 0xe5, 0x10, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "scvtf h22, h13, #16" + + - + input: + bytes: [ 0xb6, 0xe5, 0x20, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "scvtf s22, s13, #32" + + - + input: + bytes: [ 0x95, 0xe5, 0x40, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "scvtf d21, d12, #64" + + - + input: + bytes: [ 0xb6, 0xe5, 0x10, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ucvtf h22, h13, #16" + + - + input: + bytes: [ 0xb6, 0xe5, 0x20, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ucvtf s22, s13, #32" + + - + input: + bytes: [ 0xd5, 0xe5, 0x40, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ucvtf d21, d14, #64" + + - + input: + bytes: [ 0x95, 0xfd, 0x1f, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzs h21, h12, #1" + + - + input: + bytes: [ 0x95, 0xfd, 0x3f, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzs s21, s12, #1" + + - + input: + bytes: [ 0x95, 0xfd, 0x7f, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzs d21, d12, #1" + + - + input: + bytes: [ 0x95, 0xfd, 0x1f, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzu h21, h12, #1" + + - + input: + bytes: [ 0x95, 0xfd, 0x3f, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzu s21, s12, #1" + + - + input: + bytes: [ 0x95, 0xfd, 0x7f, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzu d21, d12, #1" + + - + input: + bytes: [ 0xb6, 0x69, 0x61, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtxn s22, d13" + + - + input: + bytes: [ 0xac, 0xc9, 0x79, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtas h12, h13" + + - + input: + bytes: [ 0xac, 0xc9, 0x21, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtas s12, s13" + + - + input: + bytes: [ 0xd5, 0xc9, 0x61, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtas d21, d14" + + - + input: + bytes: [ 0xac, 0xc9, 0x79, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtau h12, h13" + + - + input: + bytes: [ 0xac, 0xc9, 0x21, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtau s12, s13" + + - + input: + bytes: [ 0xd5, 0xc9, 0x61, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtau d21, d14" + + - + input: + bytes: [ 0xb6, 0xb9, 0x79, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtms h22, h13" + + - + input: + bytes: [ 0xb6, 0xb9, 0x21, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtms s22, s13" + + - + input: + bytes: [ 0xd5, 0xb9, 0x61, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtms d21, d14" + + - + input: + bytes: [ 0xac, 0xb9, 0x79, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtmu h12, h13" + + - + input: + bytes: [ 0xac, 0xb9, 0x21, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtmu s12, s13" + + - + input: + bytes: [ 0xd5, 0xb9, 0x61, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtmu d21, d14" + + - + input: + bytes: [ 0xb6, 0xa9, 0x79, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtns h22, h13" + + - + input: + bytes: [ 0xb6, 0xa9, 0x21, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtns s22, s13" + + - + input: + bytes: [ 0xd5, 0xa9, 0x61, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtns d21, d14" + + - + input: + bytes: [ 0xac, 0xa9, 0x79, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtnu h12, h13" + + - + input: + bytes: [ 0xac, 0xa9, 0x21, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtnu s12, s13" + + - + input: + bytes: [ 0xd5, 0xa9, 0x61, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtnu d21, d14" + + - + input: + bytes: [ 0xb6, 0xa9, 0xf9, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtps h22, h13" + + - + input: + bytes: [ 0xb6, 0xa9, 0xa1, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtps s22, s13" + + - + input: + bytes: [ 0xd5, 0xa9, 0xe1, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtps d21, d14" + + - + input: + bytes: [ 0xac, 0xa9, 0xf9, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtpu h12, h13" + + - + input: + bytes: [ 0xac, 0xa9, 0xa1, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtpu s12, s13" + + - + input: + bytes: [ 0xd5, 0xa9, 0xe1, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtpu d21, d14" + + - + input: + bytes: [ 0xac, 0xb9, 0xf9, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzs h12, h13" + + - + input: + bytes: [ 0xac, 0xb9, 0xa1, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzs s12, s13" + + - + input: + bytes: [ 0xd5, 0xb9, 0xe1, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzs d21, d14" + + - + input: + bytes: [ 0xac, 0xb9, 0xf9, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzu h12, h13" + + - + input: + bytes: [ 0xac, 0xb9, 0xa1, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzu s12, s13" + + - + input: + bytes: [ 0xd5, 0xb9, 0xe1, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzu d21, d14" diff --git a/tests/MC/AArch64/neon-scalar-dup.s.yaml b/tests/MC/AArch64/neon-scalar-dup.s.yaml new file mode 100644 index 0000000000..f9f4630568 --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-dup.s.yaml @@ -0,0 +1,220 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x04, 0x1f, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov b0, v0.b[15]" + + - + input: + bytes: [ 0x01, 0x04, 0x0f, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov b1, v0.b[7]" + + - + input: + bytes: [ 0x11, 0x04, 0x01, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov b17, v0.b[0]" + + - + input: + bytes: [ 0xe5, 0x07, 0x1e, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov h5, v31.h[7]" + + - + input: + bytes: [ 0x29, 0x04, 0x12, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov h9, v1.h[4]" + + - + input: + bytes: [ 0x2b, 0x06, 0x02, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov h11, v17.h[0]" + + - + input: + bytes: [ 0x42, 0x04, 0x1c, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov s2, v2.s[3]" + + - + input: + bytes: [ 0xa4, 0x06, 0x04, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov s4, v21.s[0]" + + - + input: + bytes: [ 0xbf, 0x06, 0x14, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov s31, v21.s[2]" + + - + input: + bytes: [ 0xa3, 0x04, 0x08, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov d3, v5.d[0]" + + - + input: + bytes: [ 0xa6, 0x04, 0x18, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov d6, v5.d[1]" + + - + input: + bytes: [ 0x00, 0x04, 0x1f, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov b0, v0.b[15]" + + - + input: + bytes: [ 0x01, 0x04, 0x0f, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov b1, v0.b[7]" + + - + input: + bytes: [ 0x11, 0x04, 0x01, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov b17, v0.b[0]" + + - + input: + bytes: [ 0xe5, 0x07, 0x1e, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov h5, v31.h[7]" + + - + input: + bytes: [ 0x29, 0x04, 0x12, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov h9, v1.h[4]" + + - + input: + bytes: [ 0x2b, 0x06, 0x02, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov h11, v17.h[0]" + + - + input: + bytes: [ 0x42, 0x04, 0x1c, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov s2, v2.s[3]" + + - + input: + bytes: [ 0xa4, 0x06, 0x04, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov s4, v21.s[0]" + + - + input: + bytes: [ 0xbf, 0x06, 0x14, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov s31, v21.s[2]" + + - + input: + bytes: [ 0xa3, 0x04, 0x08, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov d3, v5.d[0]" + + - + input: + bytes: [ 0xa6, 0x04, 0x18, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov d6, v5.d[1]" diff --git a/tests/MC/AArch64/neon-scalar-extract-narrow.s.yaml b/tests/MC/AArch64/neon-scalar-extract-narrow.s.yaml new file mode 100644 index 0000000000..4eefeac155 --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-extract-narrow.s.yaml @@ -0,0 +1,90 @@ +test_cases: + - + input: + bytes: [ 0xd3, 0x29, 0x21, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqxtun b19, h14" + + - + input: + bytes: [ 0xf5, 0x29, 0x61, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqxtun h21, s15" + + - + input: + bytes: [ 0x94, 0x29, 0xa1, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqxtun s20, d12" + + - + input: + bytes: [ 0x52, 0x4a, 0x21, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqxtn b18, h18" + + - + input: + bytes: [ 0x34, 0x4a, 0x61, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqxtn h20, s17" + + - + input: + bytes: [ 0xd3, 0x49, 0xa1, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqxtn s19, d14" + + - + input: + bytes: [ 0x52, 0x4a, 0x21, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqxtn b18, h18" + + - + input: + bytes: [ 0x34, 0x4a, 0x61, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqxtn h20, s17" + + - + input: + bytes: [ 0xd3, 0x49, 0xa1, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqxtn s19, d14" diff --git a/tests/MC/AArch64/neon-scalar-fp-compare.s.yaml b/tests/MC/AArch64/neon-scalar-fp-compare.s.yaml new file mode 100644 index 0000000000..e4373d85fc --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-fp-compare.s.yaml @@ -0,0 +1,450 @@ +test_cases: + - + input: + bytes: [ 0x6a, 0x25, 0x4c, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq h10, h11, h12" + + - + input: + bytes: [ 0x6a, 0xe5, 0x2c, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq s10, s11, s12" + + - + input: + bytes: [ 0xb4, 0xe6, 0x76, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq d20, d21, d22" + + - + input: + bytes: [ 0x6a, 0xd9, 0xf8, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq h10, h11, #0.0" + + - + input: + bytes: [ 0x6a, 0xd9, 0xa0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq s10, s11, #0.0" + + - + input: + bytes: [ 0xb4, 0xda, 0xe0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq d20, d21, #0.0" + + - + input: + bytes: [ 0x6a, 0xd9, 0xf8, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq h10, h11, #0.0" + + - + input: + bytes: [ 0x6a, 0xd9, 0xa0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq s10, s11, #0.0" + + - + input: + bytes: [ 0xb4, 0xda, 0xe0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmeq d20, d21, #0.0" + + - + input: + bytes: [ 0x6a, 0x25, 0x4c, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge h10, h11, h12" + + - + input: + bytes: [ 0x6a, 0xe5, 0x2c, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge s10, s11, s12" + + - + input: + bytes: [ 0xb4, 0xe6, 0x76, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge d20, d21, d22" + + - + input: + bytes: [ 0x6a, 0xc9, 0xf8, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge h10, h11, #0.0" + + - + input: + bytes: [ 0x6a, 0xc9, 0xa0, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge s10, s11, #0.0" + + - + input: + bytes: [ 0xb4, 0xca, 0xe0, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge d20, d21, #0.0" + + - + input: + bytes: [ 0x6a, 0xc9, 0xf8, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge h10, h11, #0.0" + + - + input: + bytes: [ 0x6a, 0xc9, 0xa0, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge s10, s11, #0.0" + + - + input: + bytes: [ 0xb4, 0xca, 0xe0, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmge d20, d21, #0.0" + + - + input: + bytes: [ 0x6a, 0x25, 0xcc, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt h10, h11, h12" + + - + input: + bytes: [ 0x6a, 0xe5, 0xac, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt s10, s11, s12" + + - + input: + bytes: [ 0xb4, 0xe6, 0xf6, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt d20, d21, d22" + + - + input: + bytes: [ 0x6a, 0xc9, 0xf8, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt h10, h11, #0.0" + + - + input: + bytes: [ 0x6a, 0xc9, 0xa0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt s10, s11, #0.0" + + - + input: + bytes: [ 0xb4, 0xca, 0xe0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt d20, d21, #0.0" + + - + input: + bytes: [ 0x6a, 0xc9, 0xf8, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt h10, h11, #0.0" + + - + input: + bytes: [ 0x6a, 0xc9, 0xa0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt s10, s11, #0.0" + + - + input: + bytes: [ 0xb4, 0xca, 0xe0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmgt d20, d21, #0.0" + + - + input: + bytes: [ 0x6a, 0xd9, 0xf8, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmle h10, h11, #0.0" + + - + input: + bytes: [ 0x6a, 0xd9, 0xa0, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmle s10, s11, #0.0" + + - + input: + bytes: [ 0xb4, 0xda, 0xe0, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmle d20, d21, #0.0" + + - + input: + bytes: [ 0x6a, 0xd9, 0xf8, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmle h10, h11, #0.0" + + - + input: + bytes: [ 0x6a, 0xd9, 0xa0, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmle s10, s11, #0.0" + + - + input: + bytes: [ 0xb4, 0xda, 0xe0, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmle d20, d21, #0.0" + + - + input: + bytes: [ 0x6a, 0xe9, 0xf8, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmlt h10, h11, #0.0" + + - + input: + bytes: [ 0x6a, 0xe9, 0xa0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmlt s10, s11, #0.0" + + - + input: + bytes: [ 0xb4, 0xea, 0xe0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmlt d20, d21, #0.0" + + - + input: + bytes: [ 0x6a, 0xe9, 0xf8, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmlt h10, h11, #0.0" + + - + input: + bytes: [ 0x6a, 0xe9, 0xa0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmlt s10, s11, #0.0" + + - + input: + bytes: [ 0xb4, 0xea, 0xe0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcmlt d20, d21, #0.0" + + - + input: + bytes: [ 0x6a, 0x2d, 0x4c, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facge h10, h11, h12" + + - + input: + bytes: [ 0x6a, 0xed, 0x2c, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facge s10, s11, s12" + + - + input: + bytes: [ 0xb4, 0xee, 0x76, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facge d20, d21, d22" + + - + input: + bytes: [ 0x6a, 0x2d, 0xcc, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facgt h10, h11, h12" + + - + input: + bytes: [ 0x6a, 0xed, 0xac, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facgt s10, s11, s12" + + - + input: + bytes: [ 0xb4, 0xee, 0xf6, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "facgt d20, d21, d22" diff --git a/tests/MC/AArch64/neon-scalar-mul.s.yaml b/tests/MC/AArch64/neon-scalar-mul.s.yaml new file mode 100644 index 0000000000..0444466990 --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-mul.s.yaml @@ -0,0 +1,130 @@ +test_cases: + - + input: + bytes: [ 0x6a, 0xb5, 0x6c, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmulh h10, h11, h12" + + - + input: + bytes: [ 0xb4, 0xb6, 0xa2, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmulh s20, s21, s2" + + - + input: + bytes: [ 0x6a, 0xb5, 0x6c, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrdmulh h10, h11, h12" + + - + input: + bytes: [ 0xb4, 0xb6, 0xa2, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrdmulh s20, s21, s2" + + - + input: + bytes: [ 0xd4, 0x1e, 0x4f, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmulx h20, h22, h15" + + - + input: + bytes: [ 0xd4, 0xde, 0x2f, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmulx s20, s22, s15" + + - + input: + bytes: [ 0x77, 0xdd, 0x61, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fmulx d23, d11, d1" + + - + input: + bytes: [ 0x71, 0x93, 0x6c, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmlal s17, h27, h12" + + - + input: + bytes: [ 0x13, 0x93, 0xac, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmlal d19, s24, s12" + + - + input: + bytes: [ 0x8e, 0xb1, 0x79, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmlsl s14, h12, h25" + + - + input: + bytes: [ 0xec, 0xb2, 0xad, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmlsl d12, s23, s13" + + - + input: + bytes: [ 0xcc, 0xd2, 0x6c, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmull s12, h22, h12" + + - + input: + bytes: [ 0xcf, 0xd2, 0xac, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqdmull d15, s22, s12" diff --git a/tests/MC/AArch64/neon-scalar-neg.s.yaml b/tests/MC/AArch64/neon-scalar-neg.s.yaml new file mode 100644 index 0000000000..832b9b6e76 --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-neg.s.yaml @@ -0,0 +1,50 @@ +test_cases: + - + input: + bytes: [ 0x1d, 0xbb, 0xe0, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "neg d29, d24" + + - + input: + bytes: [ 0xd3, 0x79, 0x20, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqneg b19, b14" + + - + input: + bytes: [ 0xf5, 0x79, 0x60, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqneg h21, h15" + + - + input: + bytes: [ 0x94, 0x79, 0xa0, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqneg s20, s12" + + - + input: + bytes: [ 0x92, 0x79, 0xe0, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqneg d18, d12" diff --git a/tests/MC/AArch64/neon-scalar-recip.s.yaml b/tests/MC/AArch64/neon-scalar-recip.s.yaml new file mode 100644 index 0000000000..ef6d651b53 --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-recip.s.yaml @@ -0,0 +1,150 @@ +test_cases: + - + input: + bytes: [ 0x15, 0x3e, 0x4d, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecps h21, h16, h13" + + - + input: + bytes: [ 0x15, 0xfe, 0x2d, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecps s21, s16, s13" + + - + input: + bytes: [ 0xd6, 0xff, 0x75, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecps d22, d30, d21" + + - + input: + bytes: [ 0xb5, 0x3c, 0xcc, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frsqrts h21, h5, h12" + + - + input: + bytes: [ 0xb5, 0xfc, 0xac, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frsqrts s21, s5, s12" + + - + input: + bytes: [ 0xc8, 0xfe, 0xf2, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frsqrts d8, d22, d18" + + - + input: + bytes: [ 0xd3, 0xd9, 0xf9, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecpe h19, h14" + + - + input: + bytes: [ 0xd3, 0xd9, 0xa1, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecpe s19, s14" + + - + input: + bytes: [ 0xad, 0xd9, 0xe1, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecpe d13, d13" + + - + input: + bytes: [ 0x52, 0xf9, 0xf9, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecpx h18, h10" + + - + input: + bytes: [ 0x52, 0xf9, 0xa1, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecpx s18, s10" + + - + input: + bytes: [ 0x70, 0xfa, 0xe1, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecpx d16, d19" + + - + input: + bytes: [ 0xb6, 0xd9, 0xf9, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frsqrte h22, h13" + + - + input: + bytes: [ 0xb6, 0xd9, 0xa1, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frsqrte s22, s13" + + - + input: + bytes: [ 0x95, 0xd9, 0xe1, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frsqrte d21, d12" diff --git a/tests/MC/AArch64/neon-scalar-reduce-pairwise.s.yaml b/tests/MC/AArch64/neon-scalar-reduce-pairwise.s.yaml new file mode 100644 index 0000000000..0e5195424e --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-reduce-pairwise.s.yaml @@ -0,0 +1,50 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xb8, 0xf1, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "addp d0, v1.2d" + + - + input: + bytes: [ 0x72, 0xd8, 0x30, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "faddp h18, v3.2h" + + - + input: + bytes: [ 0x72, 0xd8, 0x30, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "faddp h18, v3.2h" + + - + input: + bytes: [ 0x53, 0xd8, 0x30, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "faddp s19, v2.2s" + + - + input: + bytes: [ 0x34, 0xd8, 0x70, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "faddp d20, v1.2d" diff --git a/tests/MC/AArch64/neon-scalar-rounding-shift.s.yaml b/tests/MC/AArch64/neon-scalar-rounding-shift.s.yaml new file mode 100644 index 0000000000..7c038ba02e --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-rounding-shift.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0xf1, 0x57, 0xe8, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "srshl d17, d31, d8" + + - + input: + bytes: [ 0xf1, 0x57, 0xe8, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "urshl d17, d31, d8" diff --git a/tests/MC/AArch64/neon-scalar-saturating-add-sub.s.yaml b/tests/MC/AArch64/neon-scalar-saturating-add-sub.s.yaml new file mode 100644 index 0000000000..223b47d9a1 --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-saturating-add-sub.s.yaml @@ -0,0 +1,240 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x0c, 0x22, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqadd b0, b1, b2" + + - + input: + bytes: [ 0x6a, 0x0d, 0x6c, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqadd h10, h11, h12" + + - + input: + bytes: [ 0xb4, 0x0e, 0xa2, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqadd s20, s21, s2" + + - + input: + bytes: [ 0xf1, 0x0f, 0xe8, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqadd d17, d31, d8" + + - + input: + bytes: [ 0x20, 0x0c, 0x22, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqadd b0, b1, b2" + + - + input: + bytes: [ 0x6a, 0x0d, 0x6c, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqadd h10, h11, h12" + + - + input: + bytes: [ 0xb4, 0x0e, 0xa2, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqadd s20, s21, s2" + + - + input: + bytes: [ 0xf1, 0x0f, 0xe8, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqadd d17, d31, d8" + + - + input: + bytes: [ 0x20, 0x2c, 0x22, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqsub b0, b1, b2" + + - + input: + bytes: [ 0x6a, 0x2d, 0x6c, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqsub h10, h11, h12" + + - + input: + bytes: [ 0xb4, 0x2e, 0xa2, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqsub s20, s21, s2" + + - + input: + bytes: [ 0xf1, 0x2f, 0xe8, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqsub d17, d31, d8" + + - + input: + bytes: [ 0x20, 0x2c, 0x22, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqsub b0, b1, b2" + + - + input: + bytes: [ 0x6a, 0x2d, 0x6c, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqsub h10, h11, h12" + + - + input: + bytes: [ 0xb4, 0x2e, 0xa2, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqsub s20, s21, s2" + + - + input: + bytes: [ 0xf1, 0x2f, 0xe8, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqsub d17, d31, d8" + + - + input: + bytes: [ 0xd3, 0x39, 0x20, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "suqadd b19, b14" + + - + input: + bytes: [ 0xf4, 0x39, 0x60, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "suqadd h20, h15" + + - + input: + bytes: [ 0x95, 0x39, 0xa0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "suqadd s21, s12" + + - + input: + bytes: [ 0xd2, 0x3a, 0xe0, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "suqadd d18, d22" + + - + input: + bytes: [ 0xd3, 0x39, 0x20, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "usqadd b19, b14" + + - + input: + bytes: [ 0xf4, 0x39, 0x60, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "usqadd h20, h15" + + - + input: + bytes: [ 0x95, 0x39, 0xa0, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "usqadd s21, s12" + + - + input: + bytes: [ 0xd2, 0x3a, 0xe0, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "usqadd d18, d22" diff --git a/tests/MC/AArch64/neon-scalar-saturating-rounding-shift.s.yaml b/tests/MC/AArch64/neon-scalar-saturating-rounding-shift.s.yaml new file mode 100644 index 0000000000..aa6da494ec --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-saturating-rounding-shift.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x5c, 0x22, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrshl b0, b1, b2" + + - + input: + bytes: [ 0x6a, 0x5d, 0x6c, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrshl h10, h11, h12" + + - + input: + bytes: [ 0xb4, 0x5e, 0xa2, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrshl s20, s21, s2" + + - + input: + bytes: [ 0xf1, 0x5f, 0xe8, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrshl d17, d31, d8" + + - + input: + bytes: [ 0x20, 0x5c, 0x22, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqrshl b0, b1, b2" + + - + input: + bytes: [ 0x6a, 0x5d, 0x6c, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqrshl h10, h11, h12" + + - + input: + bytes: [ 0xb4, 0x5e, 0xa2, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqrshl s20, s21, s2" + + - + input: + bytes: [ 0xf1, 0x5f, 0xe8, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqrshl d17, d31, d8" diff --git a/tests/MC/AArch64/neon-scalar-saturating-shift.s.yaml b/tests/MC/AArch64/neon-scalar-saturating-shift.s.yaml new file mode 100644 index 0000000000..1030056073 --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-saturating-shift.s.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x4c, 0x22, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshl b0, b1, b2" + + - + input: + bytes: [ 0x6a, 0x4d, 0x6c, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshl h10, h11, h12" + + - + input: + bytes: [ 0xb4, 0x4e, 0xa2, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshl s20, s21, s2" + + - + input: + bytes: [ 0xf1, 0x4f, 0xe8, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshl d17, d31, d8" + + - + input: + bytes: [ 0x20, 0x4c, 0x22, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqshl b0, b1, b2" + + - + input: + bytes: [ 0x6a, 0x4d, 0x6c, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqshl h10, h11, h12" + + - + input: + bytes: [ 0xb4, 0x4e, 0xa2, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqshl s20, s21, s2" + + - + input: + bytes: [ 0xf1, 0x4f, 0xe8, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqshl d17, d31, d8" diff --git a/tests/MC/AArch64/neon-scalar-shift-imm.s.yaml b/tests/MC/AArch64/neon-scalar-shift-imm.s.yaml new file mode 100644 index 0000000000..c5aac3a699 --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-shift-imm.s.yaml @@ -0,0 +1,410 @@ +test_cases: + - + input: + bytes: [ 0x0f, 0x06, 0x74, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshr d15, d16, #12" + + - + input: + bytes: [ 0x2a, 0x06, 0x6e, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushr d10, d17, #18" + + - + input: + bytes: [ 0x53, 0x26, 0x79, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "srshr d19, d18, #7" + + - + input: + bytes: [ 0xf4, 0x26, 0x61, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "urshr d20, d23, #31" + + - + input: + bytes: [ 0x92, 0x15, 0x6b, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ssra d18, d12, #21" + + - + input: + bytes: [ 0xb4, 0x15, 0x43, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "usra d20, d13, #61" + + - + input: + bytes: [ 0x6f, 0x35, 0x6d, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "srsra d15, d11, #19" + + - + input: + bytes: [ 0x52, 0x35, 0x73, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ursra d18, d10, #13" + + - + input: + bytes: [ 0x47, 0x55, 0x4c, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shl d7, d10, #12" + + - + input: + bytes: [ 0x6b, 0x76, 0x0f, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshl b11, b19, #7" + + - + input: + bytes: [ 0x4d, 0x76, 0x1b, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshl h13, h18, #11" + + - + input: + bytes: [ 0x2e, 0x76, 0x36, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshl s14, s17, #22" + + - + input: + bytes: [ 0x0f, 0x76, 0x73, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshl d15, d16, #51" + + - + input: + bytes: [ 0xf2, 0x75, 0x0e, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqshl b18, b15, #6" + + - + input: + bytes: [ 0x4b, 0x76, 0x17, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqshl h11, h18, #7" + + - + input: + bytes: [ 0x6e, 0x76, 0x32, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqshl s14, s19, #18" + + - + input: + bytes: [ 0x8f, 0x75, 0x53, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqshl d15, d12, #19" + + - + input: + bytes: [ 0x4f, 0x66, 0x0e, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshlu b15, b18, #6" + + - + input: + bytes: [ 0x33, 0x66, 0x16, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshlu h19, h17, #6" + + - + input: + bytes: [ 0xd0, 0x65, 0x39, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshlu s16, s14, #25" + + - + input: + bytes: [ 0xab, 0x65, 0x60, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshlu d11, d13, #32" + + - + input: + bytes: [ 0x8a, 0x45, 0x72, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sri d10, d12, #14" + + - + input: + bytes: [ 0xca, 0x55, 0x4c, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sli d10, d14, #12" + + - + input: + bytes: [ 0xea, 0x95, 0x0b, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshrn b10, h15, #5" + + - + input: + bytes: [ 0x51, 0x95, 0x1c, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshrn h17, s10, #4" + + - + input: + bytes: [ 0x52, 0x95, 0x21, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshrn s18, d10, #31" + + - + input: + bytes: [ 0x4c, 0x95, 0x09, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqshrn b12, h10, #7" + + - + input: + bytes: [ 0xca, 0x95, 0x1b, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqshrn h10, s14, #5" + + - + input: + bytes: [ 0x8a, 0x95, 0x33, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqshrn s10, d12, #13" + + - + input: + bytes: [ 0xaa, 0x9d, 0x0e, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrshrn b10, h13, #2" + + - + input: + bytes: [ 0x4f, 0x9d, 0x1a, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrshrn h15, s10, #6" + + - + input: + bytes: [ 0x8f, 0x9d, 0x37, 0x5f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrshrn s15, d12, #9" + + - + input: + bytes: [ 0x8a, 0x9d, 0x0b, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqrshrn b10, h12, #5" + + - + input: + bytes: [ 0x4c, 0x9d, 0x12, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqrshrn h12, s10, #14" + + - + input: + bytes: [ 0x4a, 0x9d, 0x27, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "uqrshrn s10, d10, #25" + + - + input: + bytes: [ 0x4f, 0x85, 0x09, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshrun b15, h10, #7" + + - + input: + bytes: [ 0xd4, 0x85, 0x1d, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshrun h20, s14, #3" + + - + input: + bytes: [ 0xea, 0x85, 0x31, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqshrun s10, d15, #15" + + - + input: + bytes: [ 0x51, 0x8d, 0x0a, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrshrun b17, h10, #6" + + - + input: + bytes: [ 0xaa, 0x8d, 0x11, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrshrun h10, s13, #15" + + - + input: + bytes: [ 0x16, 0x8e, 0x21, 0x7f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sqrshrun s22, d16, #31" diff --git a/tests/MC/AArch64/neon-scalar-shift.s.yaml b/tests/MC/AArch64/neon-scalar-shift.s.yaml new file mode 100644 index 0000000000..1550b58767 --- /dev/null +++ b/tests/MC/AArch64/neon-scalar-shift.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0xf1, 0x47, 0xe8, 0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshl d17, d31, d8" + + - + input: + bytes: [ 0xf1, 0x47, 0xe8, 0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushl d17, d31, d8" diff --git a/tests/MC/AArch64/neon-shift-left-long.s.yaml b/tests/MC/AArch64/neon-shift-left-long.s.yaml new file mode 100644 index 0000000000..f73fee2acc --- /dev/null +++ b/tests/MC/AArch64/neon-shift-left-long.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa4, 0x0b, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshll v0.8h, v1.8b, #3" + + - + input: + bytes: [ 0x20, 0xa4, 0x13, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshll v0.4s, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0xa4, 0x23, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshll v0.2d, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0xa4, 0x0b, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshll2 v0.8h, v1.16b, #3" + + - + input: + bytes: [ 0x20, 0xa4, 0x13, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshll2 v0.4s, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0xa4, 0x23, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshll2 v0.2d, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0xa4, 0x0b, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushll v0.8h, v1.8b, #3" + + - + input: + bytes: [ 0x20, 0xa4, 0x13, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushll v0.4s, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0xa4, 0x23, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushll v0.2d, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0xa4, 0x0b, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushll2 v0.8h, v1.16b, #3" + + - + input: + bytes: [ 0x20, 0xa4, 0x13, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushll2 v0.4s, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0xa4, 0x23, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushll2 v0.2d, v1.4s, #3" diff --git a/tests/MC/AArch64/neon-shift.s.yaml b/tests/MC/AArch64/neon-shift.s.yaml new file mode 100644 index 0000000000..a66e644d42 --- /dev/null +++ b/tests/MC/AArch64/neon-shift.s.yaml @@ -0,0 +1,210 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x44, 0x22, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshl v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x44, 0x22, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshl v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x44, 0x62, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshl v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x44, 0x62, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshl v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x44, 0xa2, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshl v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x44, 0xa2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshl v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x44, 0xe2, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshl v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x44, 0x22, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushl v0.8b, v1.8b, v2.8b" + + - + input: + bytes: [ 0x20, 0x44, 0x22, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushl v0.16b, v1.16b, v2.16b" + + - + input: + bytes: [ 0x20, 0x44, 0x62, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushl v0.4h, v1.4h, v2.4h" + + - + input: + bytes: [ 0x20, 0x44, 0x62, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushl v0.8h, v1.8h, v2.8h" + + - + input: + bytes: [ 0x20, 0x44, 0xa2, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushl v0.2s, v1.2s, v2.2s" + + - + input: + bytes: [ 0x20, 0x44, 0xa2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushl v0.4s, v1.4s, v2.4s" + + - + input: + bytes: [ 0x20, 0x44, 0xe2, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushl v0.2d, v1.2d, v2.2d" + + - + input: + bytes: [ 0x20, 0x54, 0x0b, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shl v0.8b, v1.8b, #3" + + - + input: + bytes: [ 0x20, 0x54, 0x13, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shl v0.4h, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0x54, 0x23, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shl v0.2s, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0x54, 0x0b, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shl v0.16b, v1.16b, #3" + + - + input: + bytes: [ 0x20, 0x54, 0x13, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shl v0.8h, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x54, 0x23, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shl v0.4s, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x54, 0x43, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "shl v0.2d, v1.2d, #3" diff --git a/tests/MC/AArch64/neon-simd-copy.s.yaml b/tests/MC/AArch64/neon-simd-copy.s.yaml new file mode 100644 index 0000000000..ff731d1f58 --- /dev/null +++ b/tests/MC/AArch64/neon-simd-copy.s.yaml @@ -0,0 +1,410 @@ +test_cases: + - + input: + bytes: [ 0x22, 0x1c, 0x05, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v2.b[2], w1" + + - + input: + bytes: [ 0xc7, 0x1d, 0x1e, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v7.h[7], w14" + + - + input: + bytes: [ 0xd4, 0x1f, 0x04, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v20.s[0], w30" + + - + input: + bytes: [ 0xe1, 0x1c, 0x18, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v1.d[1], x7" + + - + input: + bytes: [ 0x22, 0x1c, 0x05, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v2.b[2], w1" + + - + input: + bytes: [ 0xc7, 0x1d, 0x1e, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v7.h[7], w14" + + - + input: + bytes: [ 0xd4, 0x1f, 0x04, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v20.s[0], w30" + + - + input: + bytes: [ 0xe1, 0x1c, 0x18, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v1.d[1], x7" + + - + input: + bytes: [ 0x01, 0x2c, 0x1f, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "smov w1, v0.b[15]" + + - + input: + bytes: [ 0xce, 0x2c, 0x12, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "smov w14, v6.h[4]" + + - + input: + bytes: [ 0x01, 0x2c, 0x1f, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "smov x1, v0.b[15]" + + - + input: + bytes: [ 0xce, 0x2c, 0x12, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "smov x14, v6.h[4]" + + - + input: + bytes: [ 0x34, 0x2d, 0x14, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "smov x20, v9.s[2]" + + - + input: + bytes: [ 0x01, 0x3c, 0x1f, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "umov w1, v0.b[15]" + + - + input: + bytes: [ 0xce, 0x3c, 0x12, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "umov w14, v6.h[4]" + + - + input: + bytes: [ 0x34, 0x3d, 0x14, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov w20, v9.s[2]" + + - + input: + bytes: [ 0x47, 0x3e, 0x18, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov x7, v18.d[1]" + + - + input: + bytes: [ 0x34, 0x3d, 0x14, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov w20, v9.s[2]" + + - + input: + bytes: [ 0x47, 0x3e, 0x18, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov x7, v18.d[1]" + + - + input: + bytes: [ 0x61, 0x34, 0x1d, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v1.b[14], v3.b[6]" + + - + input: + bytes: [ 0xe6, 0x54, 0x1e, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v6.h[7], v7.h[5]" + + - + input: + bytes: [ 0xcf, 0x46, 0x1c, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v15.s[3], v22.s[2]" + + - + input: + bytes: [ 0x80, 0x44, 0x08, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v0.d[0], v4.d[1]" + + - + input: + bytes: [ 0x61, 0x34, 0x1d, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v1.b[14], v3.b[6]" + + - + input: + bytes: [ 0xe6, 0x54, 0x1e, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v6.h[7], v7.h[5]" + + - + input: + bytes: [ 0xcf, 0x46, 0x1c, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v15.s[3], v22.s[2]" + + - + input: + bytes: [ 0x80, 0x44, 0x08, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "mov v0.d[0], v4.d[1]" + + - + input: + bytes: [ 0x41, 0x04, 0x05, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "dup v1.8b, v2.b[2]" + + - + input: + bytes: [ 0xeb, 0x04, 0x1e, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "dup v11.4h, v7.h[7]" + + - + input: + bytes: [ 0x91, 0x06, 0x04, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "dup v17.2s, v20.s[0]" + + - + input: + bytes: [ 0x41, 0x04, 0x05, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "dup v1.16b, v2.b[2]" + + - + input: + bytes: [ 0xeb, 0x04, 0x1e, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "dup v11.8h, v7.h[7]" + + - + input: + bytes: [ 0x91, 0x06, 0x04, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "dup v17.4s, v20.s[0]" + + - + input: + bytes: [ 0x25, 0x04, 0x18, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "dup v5.2d, v1.d[1]" + + - + input: + bytes: [ 0x21, 0x0c, 0x01, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "dup v1.8b, w1" + + - + input: + bytes: [ 0xcb, 0x0d, 0x02, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "dup v11.4h, w14" + + - + input: + bytes: [ 0xd1, 0x0f, 0x04, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "dup v17.2s, w30" + + - + input: + bytes: [ 0x41, 0x0c, 0x01, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "dup v1.16b, w2" + + - + input: + bytes: [ 0x0b, 0x0e, 0x02, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "dup v11.8h, w16" + + - + input: + bytes: [ 0x91, 0x0f, 0x04, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "dup v17.4s, w28" + + - + input: + bytes: [ 0x05, 0x0c, 0x08, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "dup v5.2d, x0" diff --git a/tests/MC/AArch64/neon-simd-ldst-multi-elem.s.yaml b/tests/MC/AArch64/neon-simd-ldst-multi-elem.s.yaml new file mode 100644 index 0000000000..9b2b75e81a --- /dev/null +++ b/tests/MC/AArch64/neon-simd-ldst-multi-elem.s.yaml @@ -0,0 +1,1960 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x70, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x75, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x7b, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x7c, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x70, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x75, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x7b, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x7c, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.1d }, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.16b, v1.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0xa5, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.8h, v16.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0xab, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.4s, v0.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0xac, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.2d, v1.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.8b, v1.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0xa5, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.4h, v16.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0xab, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.2s, v0.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0xac, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.1d, v1.1d }, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.16b, v1.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0xa5, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.8h, v16.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0xab, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.4s, v0.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0xac, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.2d, v1.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.8b, v1.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0xa5, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.4h, v16.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0xab, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.2s, v0.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0xac, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.1d, v1.1d }, [x0]" + + - + input: + bytes: [ 0x00, 0x60, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.16b, v1.16b, v2.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x65, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.8h, v16.8h, v17.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x6b, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.4s, v0.4s, v1.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x6c, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.2d, v1.2d, v2.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x60, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.8b, v1.8b, v2.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x65, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.4h, v16.4h, v17.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x6b, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.2s, v0.2s, v1.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x6c, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.1d, v1.1d, v2.1d }, [x0]" + + - + input: + bytes: [ 0x00, 0x60, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.16b, v1.16b, v2.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x65, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.8h, v16.8h, v17.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x6b, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.4s, v0.4s, v1.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x6c, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.2d, v1.2d, v2.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x60, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.8b, v1.8b, v2.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x65, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.4h, v16.4h, v17.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x6b, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.2s, v0.2s, v1.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x6c, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.1d, v1.1d, v2.1d }, [x0]" + + - + input: + bytes: [ 0x00, 0x20, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x25, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x2b, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x2c, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x20, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x25, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x2b, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x2c, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0]" + + - + input: + bytes: [ 0x00, 0x20, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x25, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x2b, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x2c, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x20, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x25, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x2b, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x2c, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0]" + + - + input: + bytes: [ 0x00, 0x80, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v0.16b, v1.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x85, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v15.8h, v16.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x8b, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v31.4s, v0.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x8c, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v0.2d, v1.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x80, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v0.8b, v1.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x85, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v15.4h, v16.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x8b, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v31.2s, v0.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x80, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v0.16b, v1.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x85, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v15.8h, v16.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x8b, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v31.4s, v0.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x8c, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v0.2d, v1.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x80, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v0.8b, v1.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x85, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v15.4h, v16.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x8b, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v31.2s, v0.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x40, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v0.16b, v1.16b, v2.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x45, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v15.8h, v16.8h, v17.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x4b, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v31.4s, v0.4s, v1.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x4c, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v0.2d, v1.2d, v2.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x40, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v0.8b, v1.8b, v2.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x45, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v15.4h, v16.4h, v17.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x4b, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v31.2s, v0.2s, v1.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x40, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v0.16b, v1.16b, v2.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x45, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v15.8h, v16.8h, v17.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x4b, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v31.4s, v0.4s, v1.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x4c, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v0.2d, v1.2d, v2.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x40, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v0.8b, v1.8b, v2.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x45, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v15.4h, v16.4h, v17.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x4b, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v31.2s, v0.2s, v1.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x05, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x0b, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x0c, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x05, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x0b, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x05, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x0b, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x0c, 0x00, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x05, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x0b, 0x00, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x70, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x75, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x7b, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x7c, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x70, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x75, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x7b, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x7c, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.1d }, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.16b, v1.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0xa5, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.8h, v16.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0xab, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.4s, v0.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0xac, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.2d, v1.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.8b, v1.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0xa5, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.4h, v16.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0xab, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.2s, v0.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0xac, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.1d, v1.1d }, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.16b, v1.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0xa5, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.8h, v16.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0xab, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.4s, v0.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0xac, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.2d, v1.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0xa0, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.8b, v1.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0xa5, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.4h, v16.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0xab, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.2s, v0.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0xac, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.1d, v1.1d }, [x0]" + + - + input: + bytes: [ 0x00, 0x60, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.16b, v1.16b, v2.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x65, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.8h, v16.8h, v17.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x6b, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.4s, v0.4s, v1.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x6c, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.2d, v1.2d, v2.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x60, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.8b, v1.8b, v2.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x65, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.4h, v16.4h, v17.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x6b, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.2s, v0.2s, v1.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x6c, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.1d, v1.1d, v2.1d }, [x0]" + + - + input: + bytes: [ 0x00, 0x60, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.16b, v1.16b, v2.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x65, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.8h, v16.8h, v17.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x6b, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.4s, v0.4s, v1.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x6c, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.2d, v1.2d, v2.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x60, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.8b, v1.8b, v2.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x65, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.4h, v16.4h, v17.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x6b, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.2s, v0.2s, v1.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x6c, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.1d, v1.1d, v2.1d }, [x0]" + + - + input: + bytes: [ 0x00, 0x20, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x25, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x2b, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x2c, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x20, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x25, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x2b, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x2c, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0]" + + - + input: + bytes: [ 0x00, 0x20, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x25, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x2b, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x2c, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x20, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x25, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x2b, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x2c, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0]" + + - + input: + bytes: [ 0x00, 0x80, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v0.16b, v1.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x85, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v15.8h, v16.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x8b, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v31.4s, v0.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x8c, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v0.2d, v1.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x80, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v0.8b, v1.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x85, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v15.4h, v16.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x8b, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v31.2s, v0.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x80, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v0.16b, v1.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x85, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v15.8h, v16.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x8b, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v31.4s, v0.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x8c, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v0.2d, v1.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x80, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v0.8b, v1.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x85, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v15.4h, v16.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x8b, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v31.2s, v0.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x40, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v0.16b, v1.16b, v2.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x45, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v15.8h, v16.8h, v17.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x4b, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v31.4s, v0.4s, v1.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x4c, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v0.2d, v1.2d, v2.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x40, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v0.8b, v1.8b, v2.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x45, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v15.4h, v16.4h, v17.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x4b, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v31.2s, v0.2s, v1.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x40, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v0.16b, v1.16b, v2.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x45, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v15.8h, v16.8h, v17.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x4b, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v31.4s, v0.4s, v1.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x4c, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v0.2d, v1.2d, v2.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x40, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v0.8b, v1.8b, v2.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x45, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v15.4h, v16.4h, v17.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x4b, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v31.2s, v0.2s, v1.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x00, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x05, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x0b, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x0c, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x00, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x05, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x0b, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0x00, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0x05, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0x0b, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0x0c, 0x40, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0x00, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0x05, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0x0b, 0x40, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]" diff --git a/tests/MC/AArch64/neon-simd-ldst-one-elem.s.yaml b/tests/MC/AArch64/neon-simd-ldst-one-elem.s.yaml new file mode 100644 index 0000000000..8f3d115e34 --- /dev/null +++ b/tests/MC/AArch64/neon-simd-ldst-one-elem.s.yaml @@ -0,0 +1,1280 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xc0, 0x40, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1r { v0.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0xc5, 0x40, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1r { v15.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0xcb, 0x40, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1r { v31.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0xcc, 0x40, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1r { v0.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0xc0, 0x40, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1r { v0.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0xc5, 0x40, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1r { v15.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0xcb, 0x40, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1r { v31.2s }, [sp]" + + - + input: + bytes: [ 0x00, 0xcc, 0x40, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1r { v0.1d }, [x0]" + + - + input: + bytes: [ 0x00, 0xc0, 0x60, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2r { v0.16b, v1.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0xc5, 0x60, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2r { v15.8h, v16.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0xcb, 0x60, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2r { v31.4s, v0.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0xcc, 0x60, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2r { v0.2d, v1.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0xc0, 0x60, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2r { v0.8b, v1.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0xc5, 0x60, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2r { v15.4h, v16.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0xcb, 0x60, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2r { v31.2s, v0.2s }, [sp]" + + - + input: + bytes: [ 0xff, 0xcf, 0x60, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2r { v31.1d, v0.1d }, [sp]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3r { v0.16b, v1.16b, v2.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0xe5, 0x40, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3r { v15.8h, v16.8h, v17.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0xeb, 0x40, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3r { v31.4s, v0.4s, v1.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0xec, 0x40, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3r { v0.2d, v1.2d, v2.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x40, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3r { v0.8b, v1.8b, v2.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0xe5, 0x40, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3r { v15.4h, v16.4h, v17.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0xeb, 0x40, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3r { v31.2s, v0.2s, v1.2s }, [sp]" + + - + input: + bytes: [ 0xff, 0xef, 0x40, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3r { v31.1d, v0.1d, v1.1d }, [sp]" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]" + + - + input: + bytes: [ 0xef, 0xe5, 0x60, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]" + + - + input: + bytes: [ 0xff, 0xeb, 0x60, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]" + + - + input: + bytes: [ 0x00, 0xec, 0x60, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]" + + - + input: + bytes: [ 0x00, 0xe0, 0x60, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]" + + - + input: + bytes: [ 0xef, 0xe5, 0x60, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]" + + - + input: + bytes: [ 0xff, 0xeb, 0x60, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]" + + - + input: + bytes: [ 0xff, 0xef, 0x60, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp]" + + - + input: + bytes: [ 0x00, 0x04, 0x40, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.b }[9], [x0]" + + - + input: + bytes: [ 0xef, 0x59, 0x40, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.h }[7], [x15]" + + - + input: + bytes: [ 0xff, 0x93, 0x40, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.s }[3], [sp]" + + - + input: + bytes: [ 0x00, 0x84, 0x40, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.d }[1], [x0]" + + - + input: + bytes: [ 0x00, 0x04, 0x60, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v0.b, v1.b }[9], [x0]" + + - + input: + bytes: [ 0xef, 0x59, 0x60, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v15.h, v16.h }[7], [x15]" + + - + input: + bytes: [ 0xff, 0x93, 0x60, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v31.s, v0.s }[3], [sp]" + + - + input: + bytes: [ 0x00, 0x84, 0x60, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v0.d, v1.d }[1], [x0]" + + - + input: + bytes: [ 0x00, 0x24, 0x40, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v0.b, v1.b, v2.b }[9], [x0]" + + - + input: + bytes: [ 0xef, 0x79, 0x40, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v15.h, v16.h, v17.h }[7], [x15]" + + - + input: + bytes: [ 0xff, 0xb3, 0x40, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v31.s, v0.s, v1.s }[3], [sp]" + + - + input: + bytes: [ 0x00, 0xa4, 0x40, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v0.d, v1.d, v2.d }[1], [x0]" + + - + input: + bytes: [ 0x00, 0x24, 0x60, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0]" + + - + input: + bytes: [ 0xef, 0x79, 0x60, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15]" + + - + input: + bytes: [ 0xff, 0xb3, 0x60, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp]" + + - + input: + bytes: [ 0x00, 0xa4, 0x60, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]" + + - + input: + bytes: [ 0x00, 0x04, 0x00, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.b }[9], [x0]" + + - + input: + bytes: [ 0xef, 0x59, 0x00, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.h }[7], [x15]" + + - + input: + bytes: [ 0xff, 0x93, 0x00, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.s }[3], [sp]" + + - + input: + bytes: [ 0x00, 0x84, 0x00, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.d }[1], [x0]" + + - + input: + bytes: [ 0x00, 0x04, 0x20, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v0.b, v1.b }[9], [x0]" + + - + input: + bytes: [ 0xef, 0x59, 0x20, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v15.h, v16.h }[7], [x15]" + + - + input: + bytes: [ 0xff, 0x93, 0x20, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v31.s, v0.s }[3], [sp]" + + - + input: + bytes: [ 0x00, 0x84, 0x20, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v0.d, v1.d }[1], [x0]" + + - + input: + bytes: [ 0x00, 0x24, 0x00, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v0.b, v1.b, v2.b }[9], [x0]" + + - + input: + bytes: [ 0xef, 0x79, 0x00, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v15.h, v16.h, v17.h }[7], [x15]" + + - + input: + bytes: [ 0xff, 0xb3, 0x00, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v31.s, v0.s, v1.s }[3], [sp]" + + - + input: + bytes: [ 0x00, 0xa4, 0x00, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v0.d, v1.d, v2.d }[1], [x0]" + + - + input: + bytes: [ 0x00, 0x24, 0x20, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0]" + + - + input: + bytes: [ 0xef, 0x79, 0x20, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15]" + + - + input: + bytes: [ 0xff, 0xb3, 0x20, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp]" + + - + input: + bytes: [ 0x00, 0xa4, 0x20, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]" + + - + input: + bytes: [ 0x00, 0xc0, 0xdf, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1r { v0.16b }, [x0], #1" + + - + input: + bytes: [ 0xef, 0xc5, 0xdf, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1r { v15.8h }, [x15], #2" + + - + input: + bytes: [ 0xff, 0xcb, 0xdf, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1r { v31.4s }, [sp], #4" + + - + input: + bytes: [ 0x00, 0xcc, 0xdf, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1r { v0.2d }, [x0], #8" + + - + input: + bytes: [ 0x00, 0xc0, 0xc0, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1r { v0.8b }, [x0], x0" + + - + input: + bytes: [ 0xef, 0xc5, 0xc1, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1r { v15.4h }, [x15], x1" + + - + input: + bytes: [ 0xff, 0xcb, 0xc2, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1r { v31.2s }, [sp], x2" + + - + input: + bytes: [ 0x00, 0xcc, 0xc3, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1r { v0.1d }, [x0], x3" + + - + input: + bytes: [ 0x00, 0xc0, 0xff, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2r { v0.16b, v1.16b }, [x0], #2" + + - + input: + bytes: [ 0xef, 0xc5, 0xff, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2r { v15.8h, v16.8h }, [x15], #4" + + - + input: + bytes: [ 0xff, 0xcb, 0xff, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2r { v31.4s, v0.4s }, [sp], #8" + + - + input: + bytes: [ 0x00, 0xcc, 0xff, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2r { v0.2d, v1.2d }, [x0], #16" + + - + input: + bytes: [ 0x00, 0xc0, 0xe6, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2r { v0.8b, v1.8b }, [x0], x6" + + - + input: + bytes: [ 0xef, 0xc5, 0xe7, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2r { v15.4h, v16.4h }, [x15], x7" + + - + input: + bytes: [ 0xff, 0xcb, 0xe9, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2r { v31.2s, v0.2s }, [sp], x9" + + - + input: + bytes: [ 0x1f, 0xcc, 0xe5, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2r { v31.1d, v0.1d }, [x0], x5" + + - + input: + bytes: [ 0x00, 0xe0, 0xc9, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3r { v0.16b, v1.16b, v2.16b }, [x0], x9" + + - + input: + bytes: [ 0xef, 0xe5, 0xc6, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3r { v15.8h, v16.8h, v17.8h }, [x15], x6" + + - + input: + bytes: [ 0xff, 0xeb, 0xc7, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3r { v31.4s, v0.4s, v1.4s }, [sp], x7" + + - + input: + bytes: [ 0x00, 0xec, 0xc5, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3r { v0.2d, v1.2d, v2.2d }, [x0], x5" + + - + input: + bytes: [ 0x00, 0xe0, 0xdf, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3" + + - + input: + bytes: [ 0xef, 0xe5, 0xdf, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6" + + - + input: + bytes: [ 0xff, 0xeb, 0xdf, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3r { v31.2s, v0.2s, v1.2s }, [sp], #12" + + - + input: + bytes: [ 0xff, 0xef, 0xdf, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3r { v31.1d, v0.1d, v1.1d }, [sp], #24" + + - + input: + bytes: [ 0x00, 0xe0, 0xff, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], #4" + + - + input: + bytes: [ 0xef, 0xe5, 0xff, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], #8" + + - + input: + bytes: [ 0xff, 0xeb, 0xff, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #16" + + - + input: + bytes: [ 0x00, 0xec, 0xff, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #32" + + - + input: + bytes: [ 0x00, 0xe0, 0xe5, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x5" + + - + input: + bytes: [ 0xef, 0xe5, 0xe9, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x9" + + - + input: + bytes: [ 0xff, 0xeb, 0xfe, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], x30" + + - + input: + bytes: [ 0xff, 0xef, 0xe7, 0x0d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp], x7" + + - + input: + bytes: [ 0x00, 0x04, 0xdf, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.b }[9], [x0], #1" + + - + input: + bytes: [ 0xef, 0x59, 0xc9, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.h }[7], [x15], x9" + + - + input: + bytes: [ 0xff, 0x93, 0xc6, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.s }[3], [sp], x6" + + - + input: + bytes: [ 0x00, 0x84, 0xdf, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.d }[1], [x0], #8" + + - + input: + bytes: [ 0x00, 0x04, 0xe3, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v0.b, v1.b }[9], [x0], x3" + + - + input: + bytes: [ 0xef, 0x59, 0xff, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v15.h, v16.h }[7], [x15], #4" + + - + input: + bytes: [ 0xff, 0x93, 0xff, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v31.s, v0.s }[3], [sp], #8" + + - + input: + bytes: [ 0x00, 0x84, 0xe0, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v0.d, v1.d }[1], [x0], x0" + + - + input: + bytes: [ 0x00, 0x24, 0xdf, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v0.b, v1.b, v2.b }[9], [x0], #3" + + - + input: + bytes: [ 0xef, 0x79, 0xdf, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v15.h, v16.h, v17.h }[7], [x15], #6" + + - + input: + bytes: [ 0xff, 0xb3, 0xc3, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v31.s, v0.s, v1.s }[3], [sp], x3" + + - + input: + bytes: [ 0x00, 0xa4, 0xc6, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v0.d, v1.d, v2.d }[1], [x0], x6" + + - + input: + bytes: [ 0x00, 0x24, 0xe5, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5" + + - + input: + bytes: [ 0xef, 0x79, 0xe7, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7" + + - + input: + bytes: [ 0xff, 0xb3, 0xff, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16" + + - + input: + bytes: [ 0x00, 0xa4, 0xff, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32" + + - + input: + bytes: [ 0x00, 0x04, 0x9f, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.b }[9], [x0], #1" + + - + input: + bytes: [ 0xef, 0x59, 0x89, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.h }[7], [x15], x9" + + - + input: + bytes: [ 0xff, 0x93, 0x86, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.s }[3], [sp], x6" + + - + input: + bytes: [ 0x00, 0x84, 0x9f, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.d }[1], [x0], #8" + + - + input: + bytes: [ 0x00, 0x04, 0xa3, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v0.b, v1.b }[9], [x0], x3" + + - + input: + bytes: [ 0xef, 0x59, 0xbf, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v15.h, v16.h }[7], [x15], #4" + + - + input: + bytes: [ 0xff, 0x93, 0xbf, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v31.s, v0.s }[3], [sp], #8" + + - + input: + bytes: [ 0x00, 0x84, 0xa0, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v0.d, v1.d }[1], [x0], x0" + + - + input: + bytes: [ 0x00, 0x24, 0x9f, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v0.b, v1.b, v2.b }[9], [x0], #3" + + - + input: + bytes: [ 0xef, 0x79, 0x9f, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v15.h, v16.h, v17.h }[7], [x15], #6" + + - + input: + bytes: [ 0xff, 0xb3, 0x83, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v31.s, v0.s, v1.s }[3], [sp], x3" + + - + input: + bytes: [ 0x00, 0xa4, 0x86, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v0.d, v1.d, v2.d }[1], [x0], x6" + + - + input: + bytes: [ 0x00, 0x24, 0xa5, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5" + + - + input: + bytes: [ 0xef, 0x79, 0xa7, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7" + + - + input: + bytes: [ 0xff, 0xb3, 0xbf, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16" + + - + input: + bytes: [ 0x00, 0xa4, 0xbf, 0x4d ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32" diff --git a/tests/MC/AArch64/neon-simd-misc.s.yaml b/tests/MC/AArch64/neon-simd-misc.s.yaml new file mode 100644 index 0000000000..d099696ffb --- /dev/null +++ b/tests/MC/AArch64/neon-simd-misc.s.yaml @@ -0,0 +1,2600 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x0b, 0x20, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rev64 v0.16b, v31.16b" + + - + input: + bytes: [ 0x82, 0x08, 0x60, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rev64 v2.8h, v4.8h" + + - + input: + bytes: [ 0x06, 0x09, 0xa0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rev64 v6.4s, v8.4s" + + - + input: + bytes: [ 0x21, 0x09, 0x20, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rev64 v1.8b, v9.8b" + + - + input: + bytes: [ 0xad, 0x0a, 0x60, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rev64 v13.4h, v21.4h" + + - + input: + bytes: [ 0x04, 0x08, 0xa0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rev64 v4.2s, v0.2s" + + - + input: + bytes: [ 0xfe, 0x0b, 0x20, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rev32 v30.16b, v31.16b" + + - + input: + bytes: [ 0xe4, 0x08, 0x60, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rev32 v4.8h, v7.8h" + + - + input: + bytes: [ 0x35, 0x08, 0x20, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rev32 v21.8b, v1.8b" + + - + input: + bytes: [ 0x20, 0x09, 0x60, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rev32 v0.4h, v9.4h" + + - + input: + bytes: [ 0xfe, 0x1b, 0x20, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rev16 v30.16b, v31.16b" + + - + input: + bytes: [ 0x35, 0x18, 0x20, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rev16 v21.8b, v1.8b" + + - + input: + bytes: [ 0xa3, 0x2a, 0x20, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "saddlp v3.8h, v21.16b" + + - + input: + bytes: [ 0xa8, 0x28, 0x20, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "saddlp v8.4h, v5.8b" + + - + input: + bytes: [ 0x29, 0x28, 0x60, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "saddlp v9.4s, v1.8h" + + - + input: + bytes: [ 0x20, 0x28, 0x60, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "saddlp v0.2s, v1.4h" + + - + input: + bytes: [ 0x8c, 0x28, 0xa0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "saddlp v12.2d, v4.4s" + + - + input: + bytes: [ 0x91, 0x2b, 0xa0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "saddlp v17.1d, v28.2s" + + - + input: + bytes: [ 0xa3, 0x2a, 0x20, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uaddlp v3.8h, v21.16b" + + - + input: + bytes: [ 0xa8, 0x28, 0x20, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uaddlp v8.4h, v5.8b" + + - + input: + bytes: [ 0x29, 0x28, 0x60, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uaddlp v9.4s, v1.8h" + + - + input: + bytes: [ 0x20, 0x28, 0x60, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uaddlp v0.2s, v1.4h" + + - + input: + bytes: [ 0x8c, 0x28, 0xa0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uaddlp v12.2d, v4.4s" + + - + input: + bytes: [ 0x91, 0x2b, 0xa0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uaddlp v17.1d, v28.2s" + + - + input: + bytes: [ 0xa3, 0x6a, 0x20, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sadalp v3.8h, v21.16b" + + - + input: + bytes: [ 0xa8, 0x68, 0x20, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sadalp v8.4h, v5.8b" + + - + input: + bytes: [ 0x29, 0x68, 0x60, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sadalp v9.4s, v1.8h" + + - + input: + bytes: [ 0x20, 0x68, 0x60, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sadalp v0.2s, v1.4h" + + - + input: + bytes: [ 0x8c, 0x68, 0xa0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sadalp v12.2d, v4.4s" + + - + input: + bytes: [ 0x91, 0x6b, 0xa0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sadalp v17.1d, v28.2s" + + - + input: + bytes: [ 0xa3, 0x6a, 0x20, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uadalp v3.8h, v21.16b" + + - + input: + bytes: [ 0xa8, 0x68, 0x20, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uadalp v8.4h, v5.8b" + + - + input: + bytes: [ 0x29, 0x68, 0x60, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uadalp v9.4s, v1.8h" + + - + input: + bytes: [ 0x20, 0x68, 0x60, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uadalp v0.2s, v1.4h" + + - + input: + bytes: [ 0x8c, 0x68, 0xa0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uadalp v12.2d, v4.4s" + + - + input: + bytes: [ 0x91, 0x6b, 0xa0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uadalp v17.1d, v28.2s" + + - + input: + bytes: [ 0xe0, 0x3b, 0x20, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "suqadd v0.16b, v31.16b" + + - + input: + bytes: [ 0x82, 0x38, 0x60, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "suqadd v2.8h, v4.8h" + + - + input: + bytes: [ 0x06, 0x39, 0xa0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "suqadd v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0x39, 0xe0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "suqadd v6.2d, v8.2d" + + - + input: + bytes: [ 0x21, 0x39, 0x20, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "suqadd v1.8b, v9.8b" + + - + input: + bytes: [ 0xad, 0x3a, 0x60, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "suqadd v13.4h, v21.4h" + + - + input: + bytes: [ 0x04, 0x38, 0xa0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "suqadd v4.2s, v0.2s" + + - + input: + bytes: [ 0xe0, 0x3b, 0x20, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "usqadd v0.16b, v31.16b" + + - + input: + bytes: [ 0x82, 0x38, 0x60, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "usqadd v2.8h, v4.8h" + + - + input: + bytes: [ 0x06, 0x39, 0xa0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "usqadd v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0x39, 0xe0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "usqadd v6.2d, v8.2d" + + - + input: + bytes: [ 0x21, 0x39, 0x20, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "usqadd v1.8b, v9.8b" + + - + input: + bytes: [ 0xad, 0x3a, 0x60, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "usqadd v13.4h, v21.4h" + + - + input: + bytes: [ 0x04, 0x38, 0xa0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "usqadd v4.2s, v0.2s" + + - + input: + bytes: [ 0xe0, 0x7b, 0x20, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqabs v0.16b, v31.16b" + + - + input: + bytes: [ 0x82, 0x78, 0x60, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqabs v2.8h, v4.8h" + + - + input: + bytes: [ 0x06, 0x79, 0xa0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqabs v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0x79, 0xe0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqabs v6.2d, v8.2d" + + - + input: + bytes: [ 0x21, 0x79, 0x20, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqabs v1.8b, v9.8b" + + - + input: + bytes: [ 0xad, 0x7a, 0x60, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqabs v13.4h, v21.4h" + + - + input: + bytes: [ 0x04, 0x78, 0xa0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqabs v4.2s, v0.2s" + + - + input: + bytes: [ 0xe0, 0x7b, 0x20, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqneg v0.16b, v31.16b" + + - + input: + bytes: [ 0x82, 0x78, 0x60, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqneg v2.8h, v4.8h" + + - + input: + bytes: [ 0x06, 0x79, 0xa0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqneg v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0x79, 0xe0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqneg v6.2d, v8.2d" + + - + input: + bytes: [ 0x21, 0x79, 0x20, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqneg v1.8b, v9.8b" + + - + input: + bytes: [ 0xad, 0x7a, 0x60, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqneg v13.4h, v21.4h" + + - + input: + bytes: [ 0x04, 0x78, 0xa0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqneg v4.2s, v0.2s" + + - + input: + bytes: [ 0xe0, 0xbb, 0x20, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "abs v0.16b, v31.16b" + + - + input: + bytes: [ 0x82, 0xb8, 0x60, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "abs v2.8h, v4.8h" + + - + input: + bytes: [ 0x06, 0xb9, 0xa0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "abs v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0xb9, 0xe0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "abs v6.2d, v8.2d" + + - + input: + bytes: [ 0x21, 0xb9, 0x20, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "abs v1.8b, v9.8b" + + - + input: + bytes: [ 0xad, 0xba, 0x60, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "abs v13.4h, v21.4h" + + - + input: + bytes: [ 0x04, 0xb8, 0xa0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "abs v4.2s, v0.2s" + + - + input: + bytes: [ 0xe0, 0xbb, 0x20, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "neg v0.16b, v31.16b" + + - + input: + bytes: [ 0x82, 0xb8, 0x60, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "neg v2.8h, v4.8h" + + - + input: + bytes: [ 0x06, 0xb9, 0xa0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "neg v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0xb9, 0xe0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "neg v6.2d, v8.2d" + + - + input: + bytes: [ 0x21, 0xb9, 0x20, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "neg v1.8b, v9.8b" + + - + input: + bytes: [ 0xad, 0xba, 0x60, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "neg v13.4h, v21.4h" + + - + input: + bytes: [ 0x04, 0xb8, 0xa0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "neg v4.2s, v0.2s" + + - + input: + bytes: [ 0xe0, 0x4b, 0x20, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cls v0.16b, v31.16b" + + - + input: + bytes: [ 0x82, 0x48, 0x60, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cls v2.8h, v4.8h" + + - + input: + bytes: [ 0x06, 0x49, 0xa0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cls v6.4s, v8.4s" + + - + input: + bytes: [ 0x21, 0x49, 0x20, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cls v1.8b, v9.8b" + + - + input: + bytes: [ 0xad, 0x4a, 0x60, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cls v13.4h, v21.4h" + + - + input: + bytes: [ 0x04, 0x48, 0xa0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cls v4.2s, v0.2s" + + - + input: + bytes: [ 0xe0, 0x4b, 0x20, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "clz v0.16b, v31.16b" + + - + input: + bytes: [ 0x82, 0x48, 0x60, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "clz v2.8h, v4.8h" + + - + input: + bytes: [ 0x06, 0x49, 0xa0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "clz v6.4s, v8.4s" + + - + input: + bytes: [ 0x21, 0x49, 0x20, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "clz v1.8b, v9.8b" + + - + input: + bytes: [ 0xad, 0x4a, 0x60, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "clz v13.4h, v21.4h" + + - + input: + bytes: [ 0x04, 0x48, 0xa0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "clz v4.2s, v0.2s" + + - + input: + bytes: [ 0xe0, 0x5b, 0x20, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cnt v0.16b, v31.16b" + + - + input: + bytes: [ 0x21, 0x59, 0x20, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "cnt v1.8b, v9.8b" + + - + input: + bytes: [ 0xe0, 0x5b, 0x20, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mvn v0.16b, v31.16b" + + - + input: + bytes: [ 0x21, 0x59, 0x20, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "mvn v1.8b, v9.8b" + + - + input: + bytes: [ 0xe0, 0x5b, 0x60, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rbit v0.16b, v31.16b" + + - + input: + bytes: [ 0x21, 0x59, 0x60, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rbit v1.8b, v9.8b" + + - + input: + bytes: [ 0x04, 0xf8, 0xf8, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fabs v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0xf9, 0xf8, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fabs v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0xf9, 0xa0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fabs v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0xf9, 0xe0, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fabs v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0xf8, 0xa0, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fabs v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0xf8, 0xf8, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fneg v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0xf9, 0xf8, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fneg v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0xf9, 0xa0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fneg v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0xf9, 0xe0, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fneg v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0xf8, 0xa0, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fneg v4.2s, v0.2s" + + - + input: + bytes: [ 0xe0, 0x2b, 0x21, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "xtn2 v0.16b, v31.8h" + + - + input: + bytes: [ 0x82, 0x28, 0x61, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "xtn2 v2.8h, v4.4s" + + - + input: + bytes: [ 0x06, 0x29, 0xa1, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "xtn2 v6.4s, v8.2d" + + - + input: + bytes: [ 0x21, 0x29, 0x21, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "xtn v1.8b, v9.8h" + + - + input: + bytes: [ 0xad, 0x2a, 0x61, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "xtn v13.4h, v21.4s" + + - + input: + bytes: [ 0x04, 0x28, 0xa1, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "xtn v4.2s, v0.2d" + + - + input: + bytes: [ 0xe0, 0x2b, 0x21, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqxtun2 v0.16b, v31.8h" + + - + input: + bytes: [ 0x82, 0x28, 0x61, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqxtun2 v2.8h, v4.4s" + + - + input: + bytes: [ 0x06, 0x29, 0xa1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqxtun2 v6.4s, v8.2d" + + - + input: + bytes: [ 0x21, 0x29, 0x21, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqxtun v1.8b, v9.8h" + + - + input: + bytes: [ 0xad, 0x2a, 0x61, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqxtun v13.4h, v21.4s" + + - + input: + bytes: [ 0x04, 0x28, 0xa1, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqxtun v4.2s, v0.2d" + + - + input: + bytes: [ 0xe0, 0x4b, 0x21, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqxtn2 v0.16b, v31.8h" + + - + input: + bytes: [ 0x82, 0x48, 0x61, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqxtn2 v2.8h, v4.4s" + + - + input: + bytes: [ 0x06, 0x49, 0xa1, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqxtn2 v6.4s, v8.2d" + + - + input: + bytes: [ 0x21, 0x49, 0x21, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqxtn v1.8b, v9.8h" + + - + input: + bytes: [ 0xad, 0x4a, 0x61, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqxtn v13.4h, v21.4s" + + - + input: + bytes: [ 0x04, 0x48, 0xa1, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqxtn v4.2s, v0.2d" + + - + input: + bytes: [ 0xe0, 0x4b, 0x21, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqxtn2 v0.16b, v31.8h" + + - + input: + bytes: [ 0x82, 0x48, 0x61, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqxtn2 v2.8h, v4.4s" + + - + input: + bytes: [ 0x06, 0x49, 0xa1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqxtn2 v6.4s, v8.2d" + + - + input: + bytes: [ 0x21, 0x49, 0x21, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqxtn v1.8b, v9.8h" + + - + input: + bytes: [ 0xad, 0x4a, 0x61, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqxtn v13.4h, v21.4s" + + - + input: + bytes: [ 0x04, 0x48, 0xa1, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqxtn v4.2s, v0.2d" + + - + input: + bytes: [ 0x82, 0x38, 0x21, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "shll2 v2.8h, v4.16b, #8" + + - + input: + bytes: [ 0x06, 0x39, 0x61, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "shll2 v6.4s, v8.8h, #16" + + - + input: + bytes: [ 0x06, 0x39, 0xa1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "shll2 v6.2d, v8.4s, #32" + + - + input: + bytes: [ 0x82, 0x38, 0x21, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "shll v2.8h, v4.8b, #8" + + - + input: + bytes: [ 0x06, 0x39, 0x61, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "shll v6.4s, v8.4h, #16" + + - + input: + bytes: [ 0x06, 0x39, 0xa1, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "shll v6.2d, v8.2s, #32" + + - + input: + bytes: [ 0x82, 0x68, 0x21, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtn2 v2.8h, v4.4s" + + - + input: + bytes: [ 0x06, 0x69, 0x61, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtn2 v6.4s, v8.2d" + + - + input: + bytes: [ 0xad, 0x6a, 0x21, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtn v13.4h, v21.4s" + + - + input: + bytes: [ 0x04, 0x68, 0x61, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtn v4.2s, v0.2d" + + - + input: + bytes: [ 0x06, 0x69, 0x61, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtxn2 v6.4s, v8.2d" + + - + input: + bytes: [ 0x04, 0x68, 0x61, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtxn v4.2s, v0.2d" + + - + input: + bytes: [ 0x29, 0x78, 0x21, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtl v9.4s, v1.4h" + + - + input: + bytes: [ 0x20, 0x78, 0x61, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtl v0.2d, v1.2s" + + - + input: + bytes: [ 0x8c, 0x78, 0x21, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtl2 v12.4s, v4.8h" + + - + input: + bytes: [ 0x91, 0x7b, 0x61, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtl2 v17.2d, v28.4s" + + - + input: + bytes: [ 0x04, 0x88, 0x79, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintn v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0x89, 0x79, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintn v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0x89, 0x21, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintn v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0x89, 0x61, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintn v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0x88, 0x21, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintn v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0x88, 0x79, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frinta v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0x89, 0x79, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frinta v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0x89, 0x21, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frinta v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0x89, 0x61, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frinta v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0x88, 0x21, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frinta v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0x88, 0xf9, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintp v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0x89, 0xf9, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintp v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0x89, 0xa1, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintp v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0x89, 0xe1, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintp v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0x88, 0xa1, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintp v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0x98, 0x79, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintm v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0x99, 0x79, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintm v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0x99, 0x21, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintm v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0x99, 0x61, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintm v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0x98, 0x21, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintm v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0x98, 0x79, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintx v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0x99, 0x79, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintx v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0x99, 0x21, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintx v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0x99, 0x61, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintx v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0x98, 0x21, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintx v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0x98, 0xf9, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintz v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0x99, 0xf9, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintz v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0x99, 0xa1, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintz v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0x99, 0xe1, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintz v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0x98, 0xa1, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frintz v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0x98, 0xf9, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frinti v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0x99, 0xf9, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frinti v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0x99, 0xa1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frinti v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0x99, 0xe1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frinti v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0x98, 0xa1, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frinti v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0xa8, 0x79, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtns v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0xa9, 0x79, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtns v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0xa9, 0x21, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtns v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0xa9, 0x61, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtns v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0xa8, 0x21, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtns v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0xa8, 0x79, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtnu v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0xa9, 0x79, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtnu v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0xa9, 0x21, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtnu v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0xa9, 0x61, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtnu v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0xa8, 0x21, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtnu v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0xa8, 0xf9, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtps v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0xa9, 0xf9, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtps v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0xa9, 0xa1, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtps v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0xa9, 0xe1, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtps v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0xa8, 0xa1, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtps v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0xa8, 0xf9, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtpu v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0xa9, 0xf9, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtpu v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0xa9, 0xa1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtpu v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0xa9, 0xe1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtpu v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0xa8, 0xa1, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtpu v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0xb8, 0x79, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtms v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0xb9, 0x79, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtms v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0xb9, 0x21, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtms v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0xb9, 0x61, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtms v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0xb8, 0x21, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtms v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0xb8, 0x79, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtmu v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0xb9, 0x79, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtmu v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0xb9, 0x21, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtmu v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0xb9, 0x61, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtmu v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0xb8, 0x21, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtmu v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0xb8, 0xf9, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzs v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0xb9, 0xf9, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzs v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0xb9, 0xa1, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzs v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0xb9, 0xe1, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzs v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0xb8, 0xa1, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzs v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0xb8, 0xf9, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzu v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0xb9, 0xf9, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzu v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0xb9, 0xa1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzu v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0xb9, 0xe1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzu v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0xb8, 0xa1, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzu v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0xc8, 0x79, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtas v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0xc9, 0x79, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtas v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0xc9, 0x21, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtas v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0xc9, 0x61, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtas v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0xc8, 0x21, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtas v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0xc8, 0x79, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtau v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0xc9, 0x79, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtau v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0xc9, 0x21, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtau v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0xc9, 0x61, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtau v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0xc8, 0x21, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtau v4.2s, v0.2s" + + - + input: + bytes: [ 0x06, 0xc9, 0xa1, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "urecpe v6.4s, v8.4s" + + - + input: + bytes: [ 0x04, 0xc8, 0xa1, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "urecpe v4.2s, v0.2s" + + - + input: + bytes: [ 0x06, 0xc9, 0xa1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ursqrte v6.4s, v8.4s" + + - + input: + bytes: [ 0x04, 0xc8, 0xa1, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ursqrte v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0xd8, 0x79, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "scvtf v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0xd9, 0x79, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "scvtf v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0xd9, 0x21, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "scvtf v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0xd9, 0x61, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "scvtf v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0xd8, 0x21, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "scvtf v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0xd8, 0x79, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ucvtf v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0xd9, 0x79, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ucvtf v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0xd9, 0x21, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ucvtf v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0xd9, 0x61, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ucvtf v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0xd8, 0x21, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ucvtf v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0xd8, 0xf9, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecpe v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0xd9, 0xf9, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecpe v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0xd9, 0xa1, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecpe v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0xd9, 0xe1, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecpe v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0xd8, 0xa1, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frecpe v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0xd8, 0xf9, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frsqrte v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0xd9, 0xf9, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frsqrte v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0xd9, 0xa1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frsqrte v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0xd9, 0xe1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frsqrte v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0xd8, 0xa1, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "frsqrte v4.2s, v0.2s" + + - + input: + bytes: [ 0x04, 0xf8, 0xf9, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fsqrt v4.4h, v0.4h" + + - + input: + bytes: [ 0x06, 0xf9, 0xf9, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fsqrt v6.8h, v8.8h" + + - + input: + bytes: [ 0x06, 0xf9, 0xa1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fsqrt v6.4s, v8.4s" + + - + input: + bytes: [ 0x06, 0xf9, 0xe1, 0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fsqrt v6.2d, v8.2d" + + - + input: + bytes: [ 0x04, 0xf8, 0xa1, 0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fsqrt v4.2s, v0.2s" diff --git a/tests/MC/AArch64/neon-simd-post-ldst-multi-elem.s.yaml b/tests/MC/AArch64/neon-simd-post-ldst-multi-elem.s.yaml new file mode 100644 index 0000000000..79857b2e9c --- /dev/null +++ b/tests/MC/AArch64/neon-simd-post-ldst-multi-elem.s.yaml @@ -0,0 +1,1060 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x70, 0xc1, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.16b }, [x0], x1" + + - + input: + bytes: [ 0xef, 0x75, 0xc2, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.8h }, [x15], x2" + + - + input: + bytes: [ 0xff, 0x7b, 0xdf, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.4s }, [sp], #16" + + - + input: + bytes: [ 0x00, 0x7c, 0xdf, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.2d }, [x0], #16" + + - + input: + bytes: [ 0x00, 0x70, 0xc2, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.8b }, [x0], x2" + + - + input: + bytes: [ 0xef, 0x75, 0xc3, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.4h }, [x15], x3" + + - + input: + bytes: [ 0xff, 0x7b, 0xdf, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.2s }, [sp], #8" + + - + input: + bytes: [ 0x00, 0x7c, 0xdf, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.1d }, [x0], #8" + + - + input: + bytes: [ 0x00, 0xa0, 0xc1, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.16b, v1.16b }, [x0], x1" + + - + input: + bytes: [ 0xef, 0xa5, 0xc2, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.8h, v16.8h }, [x15], x2" + + - + input: + bytes: [ 0xff, 0xab, 0xdf, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.4s, v0.4s }, [sp], #32" + + - + input: + bytes: [ 0x00, 0xac, 0xdf, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.2d, v1.2d }, [x0], #32" + + - + input: + bytes: [ 0x00, 0xa0, 0xc2, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.8b, v1.8b }, [x0], x2" + + - + input: + bytes: [ 0xef, 0xa5, 0xc3, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.4h, v16.4h }, [x15], x3" + + - + input: + bytes: [ 0xff, 0xab, 0xdf, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.2s, v0.2s }, [sp], #16" + + - + input: + bytes: [ 0x00, 0xac, 0xdf, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.1d, v1.1d }, [x0], #16" + + - + input: + bytes: [ 0x00, 0x60, 0xc1, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.16b, v1.16b, v2.16b }, [x0], x1" + + - + input: + bytes: [ 0xef, 0x65, 0xc2, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.8h, v16.8h, v17.8h }, [x15], x2" + + - + input: + bytes: [ 0xff, 0x6b, 0xdf, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.4s, v0.4s, v1.4s }, [sp], #48" + + - + input: + bytes: [ 0x00, 0x6c, 0xdf, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48" + + - + input: + bytes: [ 0x00, 0x60, 0xc2, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.8b, v1.8b, v2.8b }, [x0], x2" + + - + input: + bytes: [ 0xef, 0x65, 0xc3, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.4h, v16.4h, v17.4h }, [x15], x3" + + - + input: + bytes: [ 0xff, 0x6b, 0xdf, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.2s, v0.2s, v1.2s }, [sp], #24" + + - + input: + bytes: [ 0x00, 0x6c, 0xdf, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.1d, v1.1d, v2.1d }, [x0], #24" + + - + input: + bytes: [ 0x00, 0x20, 0xc1, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1" + + - + input: + bytes: [ 0xef, 0x25, 0xc2, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2" + + - + input: + bytes: [ 0xff, 0x2b, 0xdf, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64" + + - + input: + bytes: [ 0x00, 0x2c, 0xdf, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64" + + - + input: + bytes: [ 0x00, 0x20, 0xc3, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3" + + - + input: + bytes: [ 0xef, 0x25, 0xc4, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4" + + - + input: + bytes: [ 0xff, 0x2b, 0xdf, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32" + + - + input: + bytes: [ 0x00, 0x2c, 0xdf, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32" + + - + input: + bytes: [ 0x00, 0x80, 0xc1, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v0.16b, v1.16b }, [x0], x1" + + - + input: + bytes: [ 0xef, 0x85, 0xc2, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v15.8h, v16.8h }, [x15], x2" + + - + input: + bytes: [ 0xff, 0x8b, 0xdf, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v31.4s, v0.4s }, [sp], #32" + + - + input: + bytes: [ 0x00, 0x8c, 0xdf, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v0.2d, v1.2d }, [x0], #32" + + - + input: + bytes: [ 0x00, 0x80, 0xc2, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v0.8b, v1.8b }, [x0], x2" + + - + input: + bytes: [ 0xef, 0x85, 0xc3, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v15.4h, v16.4h }, [x15], x3" + + - + input: + bytes: [ 0xff, 0x8b, 0xdf, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld2 { v31.2s, v0.2s }, [sp], #16" + + - + input: + bytes: [ 0x00, 0x40, 0xc1, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v0.16b, v1.16b, v2.16b }, [x0], x1" + + - + input: + bytes: [ 0xef, 0x45, 0xc2, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2" + + - + input: + bytes: [ 0xff, 0x4b, 0xdf, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v31.4s, v0.4s, v1.4s }, [sp], #48" + + - + input: + bytes: [ 0x00, 0x4c, 0xdf, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v0.2d, v1.2d, v2.2d }, [x0], #48" + + - + input: + bytes: [ 0x00, 0x40, 0xc2, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v0.8b, v1.8b, v2.8b }, [x0], x2" + + - + input: + bytes: [ 0xef, 0x45, 0xc3, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v15.4h, v16.4h, v17.4h }, [x15], x3" + + - + input: + bytes: [ 0xff, 0x4b, 0xdf, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld3 { v31.2s, v0.2s, v1.2s }, [sp], #24" + + - + input: + bytes: [ 0x00, 0x00, 0xc1, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1" + + - + input: + bytes: [ 0xef, 0x05, 0xc2, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2" + + - + input: + bytes: [ 0xff, 0x0b, 0xdf, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64" + + - + input: + bytes: [ 0x00, 0x0c, 0xdf, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64" + + - + input: + bytes: [ 0x00, 0x00, 0xc3, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3" + + - + input: + bytes: [ 0xef, 0x05, 0xc4, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4" + + - + input: + bytes: [ 0xff, 0x0b, 0xdf, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32" + + - + input: + bytes: [ 0x00, 0x70, 0x81, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.16b }, [x0], x1" + + - + input: + bytes: [ 0xef, 0x75, 0x82, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.8h }, [x15], x2" + + - + input: + bytes: [ 0xff, 0x7b, 0x9f, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.4s }, [sp], #16" + + - + input: + bytes: [ 0x00, 0x7c, 0x9f, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.2d }, [x0], #16" + + - + input: + bytes: [ 0x00, 0x70, 0x82, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.8b }, [x0], x2" + + - + input: + bytes: [ 0xef, 0x75, 0x83, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.4h }, [x15], x3" + + - + input: + bytes: [ 0xff, 0x7b, 0x9f, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.2s }, [sp], #8" + + - + input: + bytes: [ 0x00, 0x7c, 0x9f, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.1d }, [x0], #8" + + - + input: + bytes: [ 0x00, 0xa0, 0x81, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.16b, v1.16b }, [x0], x1" + + - + input: + bytes: [ 0xef, 0xa5, 0x82, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.8h, v16.8h }, [x15], x2" + + - + input: + bytes: [ 0xff, 0xab, 0x9f, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.4s, v0.4s }, [sp], #32" + + - + input: + bytes: [ 0x00, 0xac, 0x9f, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.2d, v1.2d }, [x0], #32" + + - + input: + bytes: [ 0x00, 0xa0, 0x82, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.8b, v1.8b }, [x0], x2" + + - + input: + bytes: [ 0xef, 0xa5, 0x83, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.4h, v16.4h }, [x15], x3" + + - + input: + bytes: [ 0xff, 0xab, 0x9f, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.2s, v0.2s }, [sp], #16" + + - + input: + bytes: [ 0x00, 0xac, 0x9f, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.1d, v1.1d }, [x0], #16" + + - + input: + bytes: [ 0x00, 0x60, 0x81, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.16b, v1.16b, v2.16b }, [x0], x1" + + - + input: + bytes: [ 0xef, 0x65, 0x82, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.8h, v16.8h, v17.8h }, [x15], x2" + + - + input: + bytes: [ 0xff, 0x6b, 0x9f, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.4s, v0.4s, v1.4s }, [sp], #48" + + - + input: + bytes: [ 0x00, 0x6c, 0x9f, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.2d, v1.2d, v2.2d }, [x0], #48" + + - + input: + bytes: [ 0x00, 0x60, 0x82, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.8b, v1.8b, v2.8b }, [x0], x2" + + - + input: + bytes: [ 0xef, 0x65, 0x83, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.4h, v16.4h, v17.4h }, [x15], x3" + + - + input: + bytes: [ 0xff, 0x6b, 0x9f, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.2s, v0.2s, v1.2s }, [sp], #24" + + - + input: + bytes: [ 0x00, 0x6c, 0x9f, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.1d, v1.1d, v2.1d }, [x0], #24" + + - + input: + bytes: [ 0x00, 0x20, 0x81, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1" + + - + input: + bytes: [ 0xef, 0x25, 0x82, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2" + + - + input: + bytes: [ 0xff, 0x2b, 0x9f, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64" + + - + input: + bytes: [ 0x00, 0x2c, 0x9f, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64" + + - + input: + bytes: [ 0x00, 0x20, 0x83, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3" + + - + input: + bytes: [ 0xef, 0x25, 0x84, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4" + + - + input: + bytes: [ 0xff, 0x2b, 0x9f, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32" + + - + input: + bytes: [ 0x00, 0x2c, 0x9f, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32" + + - + input: + bytes: [ 0x00, 0x80, 0x81, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v0.16b, v1.16b }, [x0], x1" + + - + input: + bytes: [ 0xef, 0x85, 0x82, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v15.8h, v16.8h }, [x15], x2" + + - + input: + bytes: [ 0xff, 0x8b, 0x9f, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v31.4s, v0.4s }, [sp], #32" + + - + input: + bytes: [ 0x00, 0x8c, 0x9f, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v0.2d, v1.2d }, [x0], #32" + + - + input: + bytes: [ 0x00, 0x80, 0x82, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v0.8b, v1.8b }, [x0], x2" + + - + input: + bytes: [ 0xef, 0x85, 0x83, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v15.4h, v16.4h }, [x15], x3" + + - + input: + bytes: [ 0xff, 0x8b, 0x9f, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st2 { v31.2s, v0.2s }, [sp], #16" + + - + input: + bytes: [ 0x00, 0x40, 0x81, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v0.16b, v1.16b, v2.16b }, [x0], x1" + + - + input: + bytes: [ 0xef, 0x45, 0x82, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v15.8h, v16.8h, v17.8h }, [x15], x2" + + - + input: + bytes: [ 0xff, 0x4b, 0x9f, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v31.4s, v0.4s, v1.4s }, [sp], #48" + + - + input: + bytes: [ 0x00, 0x4c, 0x9f, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v0.2d, v1.2d, v2.2d }, [x0], #48" + + - + input: + bytes: [ 0x00, 0x40, 0x82, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v0.8b, v1.8b, v2.8b }, [x0], x2" + + - + input: + bytes: [ 0xef, 0x45, 0x83, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v15.4h, v16.4h, v17.4h }, [x15], x3" + + - + input: + bytes: [ 0xff, 0x4b, 0x9f, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st3 { v31.2s, v0.2s, v1.2s }, [sp], #24" + + - + input: + bytes: [ 0x00, 0x00, 0x81, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1" + + - + input: + bytes: [ 0xef, 0x05, 0x82, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2" + + - + input: + bytes: [ 0xff, 0x0b, 0x9f, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64" + + - + input: + bytes: [ 0x00, 0x0c, 0x9f, 0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64" + + - + input: + bytes: [ 0x00, 0x00, 0x83, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3" + + - + input: + bytes: [ 0xef, 0x05, 0x84, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4" + + - + input: + bytes: [ 0xff, 0x0b, 0x9f, 0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32" diff --git a/tests/MC/AArch64/neon-simd-shift.s.yaml b/tests/MC/AArch64/neon-simd-shift.s.yaml new file mode 100644 index 0000000000..709a678223 --- /dev/null +++ b/tests/MC/AArch64/neon-simd-shift.s.yaml @@ -0,0 +1,1590 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x04, 0x0d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sshr v0.8b, v1.8b, #3" + + - + input: + bytes: [ 0x20, 0x04, 0x1d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sshr v0.4h, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0x04, 0x3d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sshr v0.2s, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0x04, 0x0d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sshr v0.16b, v1.16b, #3" + + - + input: + bytes: [ 0x20, 0x04, 0x1d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sshr v0.8h, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x04, 0x3d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sshr v0.4s, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x04, 0x7d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sshr v0.2d, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x04, 0x0d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ushr v0.8b, v1.8b, #3" + + - + input: + bytes: [ 0x20, 0x04, 0x1d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ushr v0.4h, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0x04, 0x3d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ushr v0.2s, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0x04, 0x0d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ushr v0.16b, v1.16b, #3" + + - + input: + bytes: [ 0x20, 0x04, 0x1d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ushr v0.8h, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x04, 0x3d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ushr v0.4s, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x04, 0x7d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ushr v0.2d, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x14, 0x0d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ssra v0.8b, v1.8b, #3" + + - + input: + bytes: [ 0x20, 0x14, 0x1d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ssra v0.4h, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0x14, 0x3d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ssra v0.2s, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0x14, 0x0d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ssra v0.16b, v1.16b, #3" + + - + input: + bytes: [ 0x20, 0x14, 0x1d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ssra v0.8h, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x14, 0x3d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ssra v0.4s, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x14, 0x7d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ssra v0.2d, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x14, 0x0d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "usra v0.8b, v1.8b, #3" + + - + input: + bytes: [ 0x20, 0x14, 0x1d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "usra v0.4h, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0x14, 0x3d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "usra v0.2s, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0x14, 0x0d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "usra v0.16b, v1.16b, #3" + + - + input: + bytes: [ 0x20, 0x14, 0x1d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "usra v0.8h, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x14, 0x3d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "usra v0.4s, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x14, 0x7d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "usra v0.2d, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x24, 0x0d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "srshr v0.8b, v1.8b, #3" + + - + input: + bytes: [ 0x20, 0x24, 0x1d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "srshr v0.4h, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0x24, 0x3d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "srshr v0.2s, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0x24, 0x0d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "srshr v0.16b, v1.16b, #3" + + - + input: + bytes: [ 0x20, 0x24, 0x1d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "srshr v0.8h, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x24, 0x3d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "srshr v0.4s, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x24, 0x7d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "srshr v0.2d, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x24, 0x0d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "urshr v0.8b, v1.8b, #3" + + - + input: + bytes: [ 0x20, 0x24, 0x1d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "urshr v0.4h, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0x24, 0x3d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "urshr v0.2s, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0x24, 0x0d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "urshr v0.16b, v1.16b, #3" + + - + input: + bytes: [ 0x20, 0x24, 0x1d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "urshr v0.8h, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x24, 0x3d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "urshr v0.4s, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x24, 0x7d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "urshr v0.2d, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x34, 0x0d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "srsra v0.8b, v1.8b, #3" + + - + input: + bytes: [ 0x20, 0x34, 0x1d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "srsra v0.4h, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0x34, 0x3d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "srsra v0.2s, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0x34, 0x0d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "srsra v0.16b, v1.16b, #3" + + - + input: + bytes: [ 0x20, 0x34, 0x1d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "srsra v0.8h, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x34, 0x3d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "srsra v0.4s, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x34, 0x7d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "srsra v0.2d, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x34, 0x0d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ursra v0.8b, v1.8b, #3" + + - + input: + bytes: [ 0x20, 0x34, 0x1d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ursra v0.4h, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0x34, 0x3d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ursra v0.2s, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0x34, 0x0d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ursra v0.16b, v1.16b, #3" + + - + input: + bytes: [ 0x20, 0x34, 0x1d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ursra v0.8h, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x34, 0x3d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ursra v0.4s, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x34, 0x7d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ursra v0.2d, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x44, 0x0d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sri v0.8b, v1.8b, #3" + + - + input: + bytes: [ 0x20, 0x44, 0x1d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sri v0.4h, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0x44, 0x3d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sri v0.2s, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0x44, 0x0d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sri v0.16b, v1.16b, #3" + + - + input: + bytes: [ 0x20, 0x44, 0x1d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sri v0.8h, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x44, 0x3d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sri v0.4s, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x44, 0x7d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sri v0.2d, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x54, 0x0b, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sli v0.8b, v1.8b, #3" + + - + input: + bytes: [ 0x20, 0x54, 0x13, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sli v0.4h, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0x54, 0x23, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sli v0.2s, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0x54, 0x0b, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sli v0.16b, v1.16b, #3" + + - + input: + bytes: [ 0x20, 0x54, 0x13, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sli v0.8h, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x54, 0x23, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sli v0.4s, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x54, 0x43, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sli v0.2d, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x64, 0x0b, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshlu v0.8b, v1.8b, #3" + + - + input: + bytes: [ 0x20, 0x64, 0x13, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshlu v0.4h, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0x64, 0x23, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshlu v0.2s, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0x64, 0x0b, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshlu v0.16b, v1.16b, #3" + + - + input: + bytes: [ 0x20, 0x64, 0x13, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshlu v0.8h, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x64, 0x23, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshlu v0.4s, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x64, 0x43, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshlu v0.2d, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x74, 0x0b, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshl v0.8b, v1.8b, #3" + + - + input: + bytes: [ 0x20, 0x74, 0x13, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshl v0.4h, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0x74, 0x23, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshl v0.2s, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0x74, 0x0b, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshl v0.16b, v1.16b, #3" + + - + input: + bytes: [ 0x20, 0x74, 0x13, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshl v0.8h, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x74, 0x23, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshl v0.4s, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x74, 0x43, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshl v0.2d, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x74, 0x0b, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqshl v0.8b, v1.8b, #3" + + - + input: + bytes: [ 0x20, 0x74, 0x13, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqshl v0.4h, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0x74, 0x23, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqshl v0.2s, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0x74, 0x0b, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqshl v0.16b, v1.16b, #3" + + - + input: + bytes: [ 0x20, 0x74, 0x13, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqshl v0.8h, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x74, 0x23, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqshl v0.4s, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x74, 0x43, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqshl v0.2d, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x84, 0x0d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "shrn v0.8b, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x84, 0x1d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "shrn v0.4h, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x84, 0x3d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "shrn v0.2s, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x84, 0x0d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "shrn2 v0.16b, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x84, 0x1d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "shrn2 v0.8h, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x84, 0x3d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "shrn2 v0.4s, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x84, 0x0d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshrun v0.8b, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x84, 0x1d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshrun v0.4h, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x84, 0x3d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshrun v0.2s, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x84, 0x0d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshrun2 v0.16b, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x84, 0x1d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshrun2 v0.8h, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x84, 0x3d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshrun2 v0.4s, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x8c, 0x0d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rshrn v0.8b, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x8c, 0x1d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rshrn v0.4h, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x8c, 0x3d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rshrn v0.2s, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x8c, 0x0d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rshrn2 v0.16b, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x8c, 0x1d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rshrn2 v0.8h, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x8c, 0x3d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "rshrn2 v0.4s, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x8c, 0x0d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrshrun v0.8b, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x8c, 0x1d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrshrun v0.4h, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x8c, 0x3d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrshrun v0.2s, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x8c, 0x0d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrshrun2 v0.16b, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x8c, 0x1d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrshrun2 v0.8h, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x8c, 0x3d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrshrun2 v0.4s, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x94, 0x0d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshrn v0.8b, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x94, 0x1d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshrn v0.4h, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x94, 0x3d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshrn v0.2s, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x94, 0x0d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshrn2 v0.16b, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x94, 0x1d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshrn2 v0.8h, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x94, 0x3d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqshrn2 v0.4s, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x94, 0x0d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqshrn v0.8b, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x94, 0x1d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqshrn v0.4h, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x94, 0x3d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqshrn v0.2s, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x94, 0x0d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqshrn2 v0.16b, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x94, 0x1d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqshrn2 v0.8h, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x94, 0x3d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqshrn2 v0.4s, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x9c, 0x0d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrshrn v0.8b, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x9c, 0x1d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrshrn v0.4h, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x9c, 0x3d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrshrn v0.2s, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x9c, 0x0d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrshrn2 v0.16b, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x9c, 0x1d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrshrn2 v0.8h, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x9c, 0x3d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "sqrshrn2 v0.4s, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x9c, 0x0d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqrshrn v0.8b, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x9c, 0x1d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqrshrn v0.4h, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x9c, 0x3d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqrshrn v0.2s, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0x9c, 0x0d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqrshrn2 v0.16b, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0x9c, 0x1d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqrshrn2 v0.8h, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0x9c, 0x3d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "uqrshrn2 v0.4s, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0xe4, 0x1d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "scvtf v0.4h, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0xe4, 0x1d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "scvtf v0.8h, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0xe4, 0x3d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "scvtf v0.2s, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0xe4, 0x3d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "scvtf v0.4s, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0xe4, 0x7d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "scvtf v0.2d, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0xe4, 0x1d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ucvtf v0.4h, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0xe4, 0x1d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ucvtf v0.8h, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0xe4, 0x3d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ucvtf v0.2s, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0xe4, 0x3d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ucvtf v0.4s, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0xe4, 0x7d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "ucvtf v0.2d, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0xfc, 0x1d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzs v0.4h, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0xfc, 0x1d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzs v0.8h, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0xfc, 0x3d, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzs v0.2s, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0xfc, 0x3d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzs v0.4s, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0xfc, 0x7d, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzs v0.2d, v1.2d, #3" + + - + input: + bytes: [ 0x20, 0xfc, 0x1d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzu v0.4h, v1.4h, #3" + + - + input: + bytes: [ 0x20, 0xfc, 0x1d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzu v0.8h, v1.8h, #3" + + - + input: + bytes: [ 0x20, 0xfc, 0x3d, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzu v0.2s, v1.2s, #3" + + - + input: + bytes: [ 0x20, 0xfc, 0x3d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzu v0.4s, v1.4s, #3" + + - + input: + bytes: [ 0x20, 0xfc, 0x7d, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ] + expected: + insns: + - + asm_text: "fcvtzu v0.2d, v1.2d, #3" diff --git a/tests/MC/AArch64/neon-sxtl.s.yaml b/tests/MC/AArch64/neon-sxtl.s.yaml new file mode 100644 index 0000000000..0b931666ef --- /dev/null +++ b/tests/MC/AArch64/neon-sxtl.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa4, 0x08, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshll v0.8h, v1.8b, #0" + + - + input: + bytes: [ 0x20, 0xa4, 0x10, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshll v0.4s, v1.4h, #0" + + - + input: + bytes: [ 0x20, 0xa4, 0x20, 0x0f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshll v0.2d, v1.2s, #0" + + - + input: + bytes: [ 0x20, 0xa4, 0x08, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshll2 v0.8h, v1.16b, #0" + + - + input: + bytes: [ 0x20, 0xa4, 0x10, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshll2 v0.4s, v1.8h, #0" + + - + input: + bytes: [ 0x20, 0xa4, 0x20, 0x4f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "sshll2 v0.2d, v1.4s, #0" diff --git a/tests/MC/AArch64/neon-tbl.s.yaml b/tests/MC/AArch64/neon-tbl.s.yaml new file mode 100644 index 0000000000..f82bd0d241 --- /dev/null +++ b/tests/MC/AArch64/neon-tbl.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x00, 0x02, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbl v0.8b, { v1.16b }, v2.8b" + + - + input: + bytes: [ 0x20, 0x20, 0x02, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbl v0.8b, { v1.16b, v2.16b }, v2.8b" + + - + input: + bytes: [ 0x20, 0x40, 0x02, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b" + + - + input: + bytes: [ 0x20, 0x60, 0x02, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b" + + - + input: + bytes: [ 0xe0, 0x63, 0x02, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbl v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b" + + - + input: + bytes: [ 0x20, 0x00, 0x02, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbl v0.16b, { v1.16b }, v2.16b" + + - + input: + bytes: [ 0x20, 0x20, 0x02, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbl v0.16b, { v1.16b, v2.16b }, v2.16b" + + - + input: + bytes: [ 0x20, 0x40, 0x02, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b" + + - + input: + bytes: [ 0x20, 0x60, 0x02, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbl v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b" + + - + input: + bytes: [ 0xc0, 0x63, 0x02, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbl v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b" + + - + input: + bytes: [ 0x20, 0x10, 0x02, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbx v0.8b, { v1.16b }, v2.8b" + + - + input: + bytes: [ 0x20, 0x30, 0x02, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbx v0.8b, { v1.16b, v2.16b }, v2.8b" + + - + input: + bytes: [ 0x20, 0x50, 0x02, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b" + + - + input: + bytes: [ 0x20, 0x70, 0x02, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b" + + - + input: + bytes: [ 0xe0, 0x73, 0x02, 0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbx v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b" + + - + input: + bytes: [ 0x20, 0x10, 0x02, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbx v0.16b, { v1.16b }, v2.16b" + + - + input: + bytes: [ 0x20, 0x30, 0x02, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbx v0.16b, { v1.16b, v2.16b }, v2.16b" + + - + input: + bytes: [ 0x20, 0x50, 0x02, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b" + + - + input: + bytes: [ 0x20, 0x70, 0x02, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b" + + - + input: + bytes: [ 0xc0, 0x73, 0x02, 0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ] + expected: + insns: + - + asm_text: "tbx v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b" diff --git a/tests/MC/AArch64/neon-uxtl.s.yaml b/tests/MC/AArch64/neon-uxtl.s.yaml new file mode 100644 index 0000000000..bb490cf824 --- /dev/null +++ b/tests/MC/AArch64/neon-uxtl.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0xa4, 0x08, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushll v0.8h, v1.8b, #0" + + - + input: + bytes: [ 0x20, 0xa4, 0x10, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushll v0.4s, v1.4h, #0" + + - + input: + bytes: [ 0x20, 0xa4, 0x20, 0x2f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushll v0.2d, v1.2s, #0" + + - + input: + bytes: [ 0x20, 0xa4, 0x08, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushll2 v0.8h, v1.16b, #0" + + - + input: + bytes: [ 0x20, 0xa4, 0x10, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushll2 v0.4s, v1.8h, #0" + + - + input: + bytes: [ 0x20, 0xa4, 0x20, 0x6f ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ] + expected: + insns: + - + asm_text: "ushll2 v0.2d, v1.4s, #0" diff --git a/tests/MC/AArch64/ras-extension.s.yaml b/tests/MC/AArch64/ras-extension.s.yaml new file mode 100644 index 0000000000..c682d8088d --- /dev/null +++ b/tests/MC/AArch64/ras-extension.s.yaml @@ -0,0 +1,1500 @@ +test_cases: + - + input: + bytes: [ 0x1f, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "esb" + + - + input: + bytes: [ 0x20, 0x53, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "msr ERRSELR_EL1, x0" + + - + input: + bytes: [ 0x2f, 0x53, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "msr ERRSELR_EL1, x15" + + - + input: + bytes: [ 0x39, 0x53, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "msr ERRSELR_EL1, x25" + + - + input: + bytes: [ 0x21, 0x54, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "msr ERXCTLR_EL1, x1" + + - + input: + bytes: [ 0x42, 0x54, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "msr ERXSTATUS_EL1, x2" + + - + input: + bytes: [ 0x63, 0x54, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "msr ERXADDR_EL1, x3" + + - + input: + bytes: [ 0x04, 0x55, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "msr ERXMISC0_EL1, x4" + + - + input: + bytes: [ 0x25, 0x55, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "msr ERXMISC1_EL1, x5" + + - + input: + bytes: [ 0x26, 0xc1, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "msr DISR_EL1, x6" + + - + input: + bytes: [ 0x27, 0xc1, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "msr VDISR_EL2, x7" + + - + input: + bytes: [ 0x68, 0x52, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "msr VSESR_EL2, x8" + + - + input: + bytes: [ 0x20, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "mrs x0, ERRSELR_EL1" + + - + input: + bytes: [ 0x2f, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "mrs x15, ERRSELR_EL1" + + - + input: + bytes: [ 0x39, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "mrs x25, ERRSELR_EL1" + + - + input: + bytes: [ 0x21, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "mrs x1, ERXCTLR_EL1" + + - + input: + bytes: [ 0x42, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "mrs x2, ERXSTATUS_EL1" + + - + input: + bytes: [ 0x63, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "mrs x3, ERXADDR_EL1" + + - + input: + bytes: [ 0x04, 0x55, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "mrs x4, ERXMISC0_EL1" + + - + input: + bytes: [ 0x25, 0x55, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "mrs x5, ERXMISC1_EL1" + + - + input: + bytes: [ 0x26, 0xc1, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "mrs x6, DISR_EL1" + + - + input: + bytes: [ 0x27, 0xc1, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "mrs x7, VDISR_EL2" + + - + input: + bytes: [ 0x68, 0x52, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "mrs x8, VSESR_EL2" + + - + input: + bytes: [ 0x00, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "mrs x0, ERRIDR_EL1" + + - + input: + bytes: [ 0x01, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ] + expected: + insns: + - + asm_text: "mrs x1, ERXFR_EL1" + + - + input: + bytes: [ 0x1f, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "esb" + + - + input: + bytes: [ 0x20, 0x53, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "msr ERRSELR_EL1, x0" + + - + input: + bytes: [ 0x2f, 0x53, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "msr ERRSELR_EL1, x15" + + - + input: + bytes: [ 0x39, 0x53, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "msr ERRSELR_EL1, x25" + + - + input: + bytes: [ 0x21, 0x54, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "msr ERXCTLR_EL1, x1" + + - + input: + bytes: [ 0x42, 0x54, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "msr ERXSTATUS_EL1, x2" + + - + input: + bytes: [ 0x63, 0x54, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "msr ERXADDR_EL1, x3" + + - + input: + bytes: [ 0x04, 0x55, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "msr ERXMISC0_EL1, x4" + + - + input: + bytes: [ 0x25, 0x55, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "msr ERXMISC1_EL1, x5" + + - + input: + bytes: [ 0x26, 0xc1, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "msr DISR_EL1, x6" + + - + input: + bytes: [ 0x27, 0xc1, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "msr VDISR_EL2, x7" + + - + input: + bytes: [ 0x68, 0x52, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "msr VSESR_EL2, x8" + + - + input: + bytes: [ 0x20, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "mrs x0, ERRSELR_EL1" + + - + input: + bytes: [ 0x2f, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "mrs x15, ERRSELR_EL1" + + - + input: + bytes: [ 0x39, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "mrs x25, ERRSELR_EL1" + + - + input: + bytes: [ 0x21, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "mrs x1, ERXCTLR_EL1" + + - + input: + bytes: [ 0x42, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "mrs x2, ERXSTATUS_EL1" + + - + input: + bytes: [ 0x63, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "mrs x3, ERXADDR_EL1" + + - + input: + bytes: [ 0x04, 0x55, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "mrs x4, ERXMISC0_EL1" + + - + input: + bytes: [ 0x25, 0x55, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "mrs x5, ERXMISC1_EL1" + + - + input: + bytes: [ 0x26, 0xc1, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "mrs x6, DISR_EL1" + + - + input: + bytes: [ 0x27, 0xc1, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "mrs x7, VDISR_EL2" + + - + input: + bytes: [ 0x68, 0x52, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "mrs x8, VSESR_EL2" + + - + input: + bytes: [ 0x00, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "mrs x0, ERRIDR_EL1" + + - + input: + bytes: [ 0x01, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ] + expected: + insns: + - + asm_text: "mrs x1, ERXFR_EL1" + + - + input: + bytes: [ 0x1f, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "esb" + + - + input: + bytes: [ 0x20, 0x53, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "msr ERRSELR_EL1, x0" + + - + input: + bytes: [ 0x2f, 0x53, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "msr ERRSELR_EL1, x15" + + - + input: + bytes: [ 0x39, 0x53, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "msr ERRSELR_EL1, x25" + + - + input: + bytes: [ 0x21, 0x54, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "msr ERXCTLR_EL1, x1" + + - + input: + bytes: [ 0x42, 0x54, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "msr ERXSTATUS_EL1, x2" + + - + input: + bytes: [ 0x63, 0x54, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "msr ERXADDR_EL1, x3" + + - + input: + bytes: [ 0x04, 0x55, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "msr ERXMISC0_EL1, x4" + + - + input: + bytes: [ 0x25, 0x55, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "msr ERXMISC1_EL1, x5" + + - + input: + bytes: [ 0x26, 0xc1, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "msr DISR_EL1, x6" + + - + input: + bytes: [ 0x27, 0xc1, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "msr VDISR_EL2, x7" + + - + input: + bytes: [ 0x68, 0x52, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "msr VSESR_EL2, x8" + + - + input: + bytes: [ 0x20, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "mrs x0, ERRSELR_EL1" + + - + input: + bytes: [ 0x2f, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "mrs x15, ERRSELR_EL1" + + - + input: + bytes: [ 0x39, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "mrs x25, ERRSELR_EL1" + + - + input: + bytes: [ 0x21, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "mrs x1, ERXCTLR_EL1" + + - + input: + bytes: [ 0x42, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "mrs x2, ERXSTATUS_EL1" + + - + input: + bytes: [ 0x63, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "mrs x3, ERXADDR_EL1" + + - + input: + bytes: [ 0x04, 0x55, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "mrs x4, ERXMISC0_EL1" + + - + input: + bytes: [ 0x25, 0x55, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "mrs x5, ERXMISC1_EL1" + + - + input: + bytes: [ 0x26, 0xc1, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "mrs x6, DISR_EL1" + + - + input: + bytes: [ 0x27, 0xc1, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "mrs x7, VDISR_EL2" + + - + input: + bytes: [ 0x68, 0x52, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "mrs x8, VSESR_EL2" + + - + input: + bytes: [ 0x00, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "mrs x0, ERRIDR_EL1" + + - + input: + bytes: [ 0x01, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ] + expected: + insns: + - + asm_text: "mrs x1, ERXFR_EL1" + + - + input: + bytes: [ 0x1f, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "esb" + + - + input: + bytes: [ 0x20, 0x53, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "msr ERRSELR_EL1, x0" + + - + input: + bytes: [ 0x2f, 0x53, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "msr ERRSELR_EL1, x15" + + - + input: + bytes: [ 0x39, 0x53, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "msr ERRSELR_EL1, x25" + + - + input: + bytes: [ 0x21, 0x54, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "msr ERXCTLR_EL1, x1" + + - + input: + bytes: [ 0x42, 0x54, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "msr ERXSTATUS_EL1, x2" + + - + input: + bytes: [ 0x63, 0x54, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "msr ERXADDR_EL1, x3" + + - + input: + bytes: [ 0x04, 0x55, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "msr ERXMISC0_EL1, x4" + + - + input: + bytes: [ 0x25, 0x55, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "msr ERXMISC1_EL1, x5" + + - + input: + bytes: [ 0x26, 0xc1, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "msr DISR_EL1, x6" + + - + input: + bytes: [ 0x27, 0xc1, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "msr VDISR_EL2, x7" + + - + input: + bytes: [ 0x68, 0x52, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "msr VSESR_EL2, x8" + + - + input: + bytes: [ 0x20, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "mrs x0, ERRSELR_EL1" + + - + input: + bytes: [ 0x2f, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "mrs x15, ERRSELR_EL1" + + - + input: + bytes: [ 0x39, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "mrs x25, ERRSELR_EL1" + + - + input: + bytes: [ 0x21, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "mrs x1, ERXCTLR_EL1" + + - + input: + bytes: [ 0x42, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "mrs x2, ERXSTATUS_EL1" + + - + input: + bytes: [ 0x63, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "mrs x3, ERXADDR_EL1" + + - + input: + bytes: [ 0x04, 0x55, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "mrs x4, ERXMISC0_EL1" + + - + input: + bytes: [ 0x25, 0x55, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "mrs x5, ERXMISC1_EL1" + + - + input: + bytes: [ 0x26, 0xc1, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "mrs x6, DISR_EL1" + + - + input: + bytes: [ 0x27, 0xc1, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "mrs x7, VDISR_EL2" + + - + input: + bytes: [ 0x68, 0x52, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "mrs x8, VSESR_EL2" + + - + input: + bytes: [ 0x00, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "mrs x0, ERRIDR_EL1" + + - + input: + bytes: [ 0x01, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ] + expected: + insns: + - + asm_text: "mrs x1, ERXFR_EL1" + + - + input: + bytes: [ 0x1f, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "esb" + + - + input: + bytes: [ 0x20, 0x53, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "msr ERRSELR_EL1, x0" + + - + input: + bytes: [ 0x2f, 0x53, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "msr ERRSELR_EL1, x15" + + - + input: + bytes: [ 0x39, 0x53, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "msr ERRSELR_EL1, x25" + + - + input: + bytes: [ 0x21, 0x54, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "msr ERXCTLR_EL1, x1" + + - + input: + bytes: [ 0x42, 0x54, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "msr ERXSTATUS_EL1, x2" + + - + input: + bytes: [ 0x63, 0x54, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "msr ERXADDR_EL1, x3" + + - + input: + bytes: [ 0x04, 0x55, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "msr ERXMISC0_EL1, x4" + + - + input: + bytes: [ 0x25, 0x55, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "msr ERXMISC1_EL1, x5" + + - + input: + bytes: [ 0x26, 0xc1, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "msr DISR_EL1, x6" + + - + input: + bytes: [ 0x27, 0xc1, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "msr VDISR_EL2, x7" + + - + input: + bytes: [ 0x68, 0x52, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "msr VSESR_EL2, x8" + + - + input: + bytes: [ 0x20, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "mrs x0, ERRSELR_EL1" + + - + input: + bytes: [ 0x2f, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "mrs x15, ERRSELR_EL1" + + - + input: + bytes: [ 0x39, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "mrs x25, ERRSELR_EL1" + + - + input: + bytes: [ 0x21, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "mrs x1, ERXCTLR_EL1" + + - + input: + bytes: [ 0x42, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "mrs x2, ERXSTATUS_EL1" + + - + input: + bytes: [ 0x63, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "mrs x3, ERXADDR_EL1" + + - + input: + bytes: [ 0x04, 0x55, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "mrs x4, ERXMISC0_EL1" + + - + input: + bytes: [ 0x25, 0x55, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "mrs x5, ERXMISC1_EL1" + + - + input: + bytes: [ 0x26, 0xc1, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "mrs x6, DISR_EL1" + + - + input: + bytes: [ 0x27, 0xc1, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "mrs x7, VDISR_EL2" + + - + input: + bytes: [ 0x68, 0x52, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "mrs x8, VSESR_EL2" + + - + input: + bytes: [ 0x00, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "mrs x0, ERRIDR_EL1" + + - + input: + bytes: [ 0x01, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ] + expected: + insns: + - + asm_text: "mrs x1, ERXFR_EL1" + + - + input: + bytes: [ 0x1f, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "esb" + + - + input: + bytes: [ 0x20, 0x53, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "msr ERRSELR_EL1, x0" + + - + input: + bytes: [ 0x2f, 0x53, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "msr ERRSELR_EL1, x15" + + - + input: + bytes: [ 0x39, 0x53, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "msr ERRSELR_EL1, x25" + + - + input: + bytes: [ 0x21, 0x54, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "msr ERXCTLR_EL1, x1" + + - + input: + bytes: [ 0x42, 0x54, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "msr ERXSTATUS_EL1, x2" + + - + input: + bytes: [ 0x63, 0x54, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "msr ERXADDR_EL1, x3" + + - + input: + bytes: [ 0x04, 0x55, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "msr ERXMISC0_EL1, x4" + + - + input: + bytes: [ 0x25, 0x55, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "msr ERXMISC1_EL1, x5" + + - + input: + bytes: [ 0x26, 0xc1, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "msr DISR_EL1, x6" + + - + input: + bytes: [ 0x27, 0xc1, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "msr VDISR_EL2, x7" + + - + input: + bytes: [ 0x68, 0x52, 0x1c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "msr VSESR_EL2, x8" + + - + input: + bytes: [ 0x20, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, ERRSELR_EL1" + + - + input: + bytes: [ 0x2f, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "mrs x15, ERRSELR_EL1" + + - + input: + bytes: [ 0x39, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "mrs x25, ERRSELR_EL1" + + - + input: + bytes: [ 0x21, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "mrs x1, ERXCTLR_EL1" + + - + input: + bytes: [ 0x42, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "mrs x2, ERXSTATUS_EL1" + + - + input: + bytes: [ 0x63, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "mrs x3, ERXADDR_EL1" + + - + input: + bytes: [ 0x04, 0x55, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "mrs x4, ERXMISC0_EL1" + + - + input: + bytes: [ 0x25, 0x55, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "mrs x5, ERXMISC1_EL1" + + - + input: + bytes: [ 0x26, 0xc1, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "mrs x6, DISR_EL1" + + - + input: + bytes: [ 0x27, 0xc1, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "mrs x7, VDISR_EL2" + + - + input: + bytes: [ 0x68, 0x52, 0x3c, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "mrs x8, VSESR_EL2" + + - + input: + bytes: [ 0x00, 0x53, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "mrs x0, ERRIDR_EL1" + + - + input: + bytes: [ 0x01, 0x54, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ] + expected: + insns: + - + asm_text: "mrs x1, ERXFR_EL1" diff --git a/tests/MC/AArch64/rprfm.s.yaml b/tests/MC/AArch64/rprfm.s.yaml new file mode 100644 index 0000000000..63cdc6f2f1 --- /dev/null +++ b/tests/MC/AArch64/rprfm.s.yaml @@ -0,0 +1,1280 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x48, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm pldkeep, x0, [x0]" + + - + input: + bytes: [ 0x19, 0x48, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm pstkeep, x0, [x0]" + + - + input: + bytes: [ 0x1a, 0x48, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #2, x0, [x0]" + + - + input: + bytes: [ 0x1b, 0x48, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #3, x0, [x0]" + + - + input: + bytes: [ 0x1c, 0x48, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm pldstrm, x0, [x0]" + + - + input: + bytes: [ 0x1d, 0x48, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm pststrm, x0, [x0]" + + - + input: + bytes: [ 0x1e, 0x48, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #6, x0, [x0]" + + - + input: + bytes: [ 0x1f, 0x48, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #7, x0, [x0]" + + - + input: + bytes: [ 0x18, 0x58, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #8, x0, [x0]" + + - + input: + bytes: [ 0x19, 0x58, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #9, x0, [x0]" + + - + input: + bytes: [ 0x1a, 0x58, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #10, x0, [x0]" + + - + input: + bytes: [ 0x1b, 0x58, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #11, x0, [x0]" + + - + input: + bytes: [ 0x1c, 0x58, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #12, x0, [x0]" + + - + input: + bytes: [ 0x1d, 0x58, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #13, x0, [x0]" + + - + input: + bytes: [ 0x1e, 0x58, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #14, x0, [x0]" + + - + input: + bytes: [ 0x1f, 0x58, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #15, x0, [x0]" + + - + input: + bytes: [ 0x18, 0x68, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #16, x0, [x0]" + + - + input: + bytes: [ 0x19, 0x68, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #17, x0, [x0]" + + - + input: + bytes: [ 0x1a, 0x68, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #18, x0, [x0]" + + - + input: + bytes: [ 0x1b, 0x68, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #19, x0, [x0]" + + - + input: + bytes: [ 0x1c, 0x68, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #20, x0, [x0]" + + - + input: + bytes: [ 0x1d, 0x68, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #21, x0, [x0]" + + - + input: + bytes: [ 0x1e, 0x68, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #22, x0, [x0]" + + - + input: + bytes: [ 0x1f, 0x68, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #23, x0, [x0]" + + - + input: + bytes: [ 0x18, 0x78, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #24, x0, [x0]" + + - + input: + bytes: [ 0x19, 0x78, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #25, x0, [x0]" + + - + input: + bytes: [ 0x1a, 0x78, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #26, x0, [x0]" + + - + input: + bytes: [ 0x1b, 0x78, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #27, x0, [x0]" + + - + input: + bytes: [ 0x1c, 0x78, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #28, x0, [x0]" + + - + input: + bytes: [ 0x1d, 0x78, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #29, x0, [x0]" + + - + input: + bytes: [ 0x1e, 0x78, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #30, x0, [x0]" + + - + input: + bytes: [ 0x1f, 0x78, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #31, x0, [x0]" + + - + input: + bytes: [ 0x18, 0xc8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #32, x0, [x0]" + + - + input: + bytes: [ 0x19, 0xc8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #33, x0, [x0]" + + - + input: + bytes: [ 0x1a, 0xc8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #34, x0, [x0]" + + - + input: + bytes: [ 0x1b, 0xc8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #35, x0, [x0]" + + - + input: + bytes: [ 0x1c, 0xc8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #36, x0, [x0]" + + - + input: + bytes: [ 0x1d, 0xc8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #37, x0, [x0]" + + - + input: + bytes: [ 0x1e, 0xc8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #38, x0, [x0]" + + - + input: + bytes: [ 0x1f, 0xc8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #39, x0, [x0]" + + - + input: + bytes: [ 0x18, 0xd8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #40, x0, [x0]" + + - + input: + bytes: [ 0x19, 0xd8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #41, x0, [x0]" + + - + input: + bytes: [ 0x1a, 0xd8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #42, x0, [x0]" + + - + input: + bytes: [ 0x1b, 0xd8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #43, x0, [x0]" + + - + input: + bytes: [ 0x1c, 0xd8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #44, x0, [x0]" + + - + input: + bytes: [ 0x1d, 0xd8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #45, x0, [x0]" + + - + input: + bytes: [ 0x1e, 0xd8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #46, x0, [x0]" + + - + input: + bytes: [ 0x1f, 0xd8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #47, x0, [x0]" + + - + input: + bytes: [ 0x18, 0xe8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #48, x0, [x0]" + + - + input: + bytes: [ 0x19, 0xe8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #49, x0, [x0]" + + - + input: + bytes: [ 0x1a, 0xe8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #50, x0, [x0]" + + - + input: + bytes: [ 0x1b, 0xe8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #51, x0, [x0]" + + - + input: + bytes: [ 0x1c, 0xe8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #52, x0, [x0]" + + - + input: + bytes: [ 0x1d, 0xe8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #53, x0, [x0]" + + - + input: + bytes: [ 0x1e, 0xe8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #54, x0, [x0]" + + - + input: + bytes: [ 0x1f, 0xe8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #55, x0, [x0]" + + - + input: + bytes: [ 0x18, 0xf8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #56, x0, [x0]" + + - + input: + bytes: [ 0x19, 0xf8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #57, x0, [x0]" + + - + input: + bytes: [ 0x1a, 0xf8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #58, x0, [x0]" + + - + input: + bytes: [ 0x1b, 0xf8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #59, x0, [x0]" + + - + input: + bytes: [ 0x1c, 0xf8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #60, x0, [x0]" + + - + input: + bytes: [ 0x1d, 0xf8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #61, x0, [x0]" + + - + input: + bytes: [ 0x1e, 0xf8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #62, x0, [x0]" + + - + input: + bytes: [ 0x1f, 0xf8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #63, x0, [x0]" + + - + input: + bytes: [ 0x18, 0x48, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm pldkeep, x0, [x0]" + + - + input: + bytes: [ 0x19, 0x48, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm pstkeep, x0, [x0]" + + - + input: + bytes: [ 0x1a, 0x48, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #2, x0, [x0]" + + - + input: + bytes: [ 0x1b, 0x48, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #3, x0, [x0]" + + - + input: + bytes: [ 0x1c, 0x48, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm pldstrm, x0, [x0]" + + - + input: + bytes: [ 0x1d, 0x48, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm pststrm, x0, [x0]" + + - + input: + bytes: [ 0x1e, 0x48, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #6, x0, [x0]" + + - + input: + bytes: [ 0x1f, 0x48, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #7, x0, [x0]" + + - + input: + bytes: [ 0x18, 0x58, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #8, x0, [x0]" + + - + input: + bytes: [ 0x19, 0x58, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #9, x0, [x0]" + + - + input: + bytes: [ 0x1a, 0x58, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #10, x0, [x0]" + + - + input: + bytes: [ 0x1b, 0x58, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #11, x0, [x0]" + + - + input: + bytes: [ 0x1c, 0x58, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #12, x0, [x0]" + + - + input: + bytes: [ 0x1d, 0x58, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #13, x0, [x0]" + + - + input: + bytes: [ 0x1e, 0x58, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #14, x0, [x0]" + + - + input: + bytes: [ 0x1f, 0x58, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #15, x0, [x0]" + + - + input: + bytes: [ 0x18, 0x68, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #16, x0, [x0]" + + - + input: + bytes: [ 0x19, 0x68, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #17, x0, [x0]" + + - + input: + bytes: [ 0x1a, 0x68, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #18, x0, [x0]" + + - + input: + bytes: [ 0x1b, 0x68, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #19, x0, [x0]" + + - + input: + bytes: [ 0x1c, 0x68, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #20, x0, [x0]" + + - + input: + bytes: [ 0x1d, 0x68, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #21, x0, [x0]" + + - + input: + bytes: [ 0x1e, 0x68, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #22, x0, [x0]" + + - + input: + bytes: [ 0x1f, 0x68, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #23, x0, [x0]" + + - + input: + bytes: [ 0x18, 0x78, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #24, x0, [x0]" + + - + input: + bytes: [ 0x19, 0x78, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #25, x0, [x0]" + + - + input: + bytes: [ 0x1a, 0x78, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #26, x0, [x0]" + + - + input: + bytes: [ 0x1b, 0x78, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #27, x0, [x0]" + + - + input: + bytes: [ 0x1c, 0x78, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #28, x0, [x0]" + + - + input: + bytes: [ 0x1d, 0x78, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #29, x0, [x0]" + + - + input: + bytes: [ 0x1e, 0x78, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #30, x0, [x0]" + + - + input: + bytes: [ 0x1f, 0x78, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #31, x0, [x0]" + + - + input: + bytes: [ 0x18, 0xc8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #32, x0, [x0]" + + - + input: + bytes: [ 0x19, 0xc8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #33, x0, [x0]" + + - + input: + bytes: [ 0x1a, 0xc8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #34, x0, [x0]" + + - + input: + bytes: [ 0x1b, 0xc8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #35, x0, [x0]" + + - + input: + bytes: [ 0x1c, 0xc8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #36, x0, [x0]" + + - + input: + bytes: [ 0x1d, 0xc8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #37, x0, [x0]" + + - + input: + bytes: [ 0x1e, 0xc8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #38, x0, [x0]" + + - + input: + bytes: [ 0x1f, 0xc8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #39, x0, [x0]" + + - + input: + bytes: [ 0x18, 0xd8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #40, x0, [x0]" + + - + input: + bytes: [ 0x19, 0xd8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #41, x0, [x0]" + + - + input: + bytes: [ 0x1a, 0xd8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #42, x0, [x0]" + + - + input: + bytes: [ 0x1b, 0xd8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #43, x0, [x0]" + + - + input: + bytes: [ 0x1c, 0xd8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #44, x0, [x0]" + + - + input: + bytes: [ 0x1d, 0xd8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #45, x0, [x0]" + + - + input: + bytes: [ 0x1e, 0xd8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #46, x0, [x0]" + + - + input: + bytes: [ 0x1f, 0xd8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #47, x0, [x0]" + + - + input: + bytes: [ 0x18, 0xe8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #48, x0, [x0]" + + - + input: + bytes: [ 0x19, 0xe8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #49, x0, [x0]" + + - + input: + bytes: [ 0x1a, 0xe8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #50, x0, [x0]" + + - + input: + bytes: [ 0x1b, 0xe8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #51, x0, [x0]" + + - + input: + bytes: [ 0x1c, 0xe8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #52, x0, [x0]" + + - + input: + bytes: [ 0x1d, 0xe8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #53, x0, [x0]" + + - + input: + bytes: [ 0x1e, 0xe8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #54, x0, [x0]" + + - + input: + bytes: [ 0x1f, 0xe8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #55, x0, [x0]" + + - + input: + bytes: [ 0x18, 0xf8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #56, x0, [x0]" + + - + input: + bytes: [ 0x19, 0xf8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #57, x0, [x0]" + + - + input: + bytes: [ 0x1a, 0xf8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #58, x0, [x0]" + + - + input: + bytes: [ 0x1b, 0xf8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #59, x0, [x0]" + + - + input: + bytes: [ 0x1c, 0xf8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #60, x0, [x0]" + + - + input: + bytes: [ 0x1d, 0xf8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #61, x0, [x0]" + + - + input: + bytes: [ 0x1e, 0xf8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #62, x0, [x0]" + + - + input: + bytes: [ 0x1f, 0xf8, 0xa0, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "rprfm #63, x0, [x0]" diff --git a/tests/MC/AArch64/spe.s.yaml b/tests/MC/AArch64/spe.s.yaml new file mode 100644 index 0000000000..e1d854f76e --- /dev/null +++ b/tests/MC/AArch64/spe.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x99, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "spe-eef" ] + expected: + insns: + - + asm_text: "msr PMSNEVFR_EL1, x0" + + - + input: + bytes: [ 0x21, 0x99, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "spe-eef" ] + expected: + insns: + - + asm_text: "mrs x1, PMSNEVFR_EL1" diff --git a/tests/MC/AArch64/speculation-barriers.s.yaml b/tests/MC/AArch64/speculation-barriers.s.yaml new file mode 100644 index 0000000000..fbeff14668 --- /dev/null +++ b/tests/MC/AArch64/speculation-barriers.s.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0x9f, 0x22, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "csdb" + + - + input: + bytes: [ 0x9f, 0x30, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "ssbb" + + - + input: + bytes: [ 0x9f, 0x34, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "pssbb" diff --git a/tests/MC/AArch64/tme.s.yaml b/tests/MC/AArch64/tme.s.yaml new file mode 100644 index 0000000000..8bb03bbda5 --- /dev/null +++ b/tests/MC/AArch64/tme.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x63, 0x30, 0x23, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tme" ] + expected: + insns: + - + asm_text: "tstart x3" + + - + input: + bytes: [ 0x64, 0x31, 0x23, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tme" ] + expected: + insns: + - + asm_text: "ttest x4" + + - + input: + bytes: [ 0x7f, 0x30, 0x03, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tme" ] + expected: + insns: + - + asm_text: "tcommit" + + - + input: + bytes: [ 0x80, 0x46, 0x62, 0xd4 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tme" ] + expected: + insns: + - + asm_text: "tcancel #0x1234" diff --git a/tests/MC/AArch64/trace-regs.s.yaml b/tests/MC/AArch64/trace-regs.s.yaml new file mode 100644 index 0000000000..07b7335420 --- /dev/null +++ b/tests/MC/AArch64/trace-regs.s.yaml @@ -0,0 +1,3820 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x03, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x8, TRCSTATR" + + - + input: + bytes: [ 0xc9, 0x00, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x9, TRCIDR8" + + - + input: + bytes: [ 0xcb, 0x01, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x11, TRCIDR9" + + - + input: + bytes: [ 0xd9, 0x02, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x25, TRCIDR10" + + - + input: + bytes: [ 0xc7, 0x03, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x7, TRCIDR11" + + - + input: + bytes: [ 0xc7, 0x04, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x7, TRCIDR12" + + - + input: + bytes: [ 0xc6, 0x05, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x6, TRCIDR13" + + - + input: + bytes: [ 0xfb, 0x08, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x27, TRCIDR0" + + - + input: + bytes: [ 0xfd, 0x09, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x29, TRCIDR1" + + - + input: + bytes: [ 0xe4, 0x0a, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x4, TRCIDR2" + + - + input: + bytes: [ 0xe8, 0x0b, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x8, TRCIDR3" + + - + input: + bytes: [ 0xef, 0x0c, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x15, TRCIDR4" + + - + input: + bytes: [ 0xf4, 0x0d, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x20, TRCIDR5" + + - + input: + bytes: [ 0xe6, 0x0e, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x6, TRCIDR6" + + - + input: + bytes: [ 0xe6, 0x0f, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x6, TRCIDR7" + + - + input: + bytes: [ 0x98, 0x11, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x24, TRCOSLSR" + + - + input: + bytes: [ 0x92, 0x15, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x18, TRCPDSR" + + - + input: + bytes: [ 0xdc, 0x7a, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x28, TRCDEVAFF0" + + - + input: + bytes: [ 0xc5, 0x7b, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x5, TRCDEVAFF1" + + - + input: + bytes: [ 0xc5, 0x7d, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x5, TRCLSR" + + - + input: + bytes: [ 0xcb, 0x7e, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x11, TRCAUTHSTATUS" + + - + input: + bytes: [ 0xcd, 0x7f, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x13, TRCDEVARCH" + + - + input: + bytes: [ 0xf2, 0x72, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x18, TRCDEVID" + + - + input: + bytes: [ 0xf6, 0x73, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x22, TRCDEVTYPE" + + - + input: + bytes: [ 0xee, 0x74, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x14, TRCPIDR4" + + - + input: + bytes: [ 0xe5, 0x75, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x5, TRCPIDR5" + + - + input: + bytes: [ 0xe5, 0x76, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x5, TRCPIDR6" + + - + input: + bytes: [ 0xe9, 0x77, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x9, TRCPIDR7" + + - + input: + bytes: [ 0xef, 0x78, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x15, TRCPIDR0" + + - + input: + bytes: [ 0xe6, 0x79, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x6, TRCPIDR1" + + - + input: + bytes: [ 0xeb, 0x7a, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x11, TRCPIDR2" + + - + input: + bytes: [ 0xf4, 0x7b, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x20, TRCPIDR3" + + - + input: + bytes: [ 0xf1, 0x7c, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x17, TRCCIDR0" + + - + input: + bytes: [ 0xe2, 0x7d, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x2, TRCCIDR1" + + - + input: + bytes: [ 0xf4, 0x7e, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x20, TRCCIDR2" + + - + input: + bytes: [ 0xe4, 0x7f, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x4, TRCCIDR3" + + - + input: + bytes: [ 0x0b, 0x01, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x11, TRCPRGCTLR" + + - + input: + bytes: [ 0x17, 0x02, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x23, TRCPROCSELR" + + - + input: + bytes: [ 0x0d, 0x04, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x13, TRCCONFIGR" + + - + input: + bytes: [ 0x17, 0x06, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x23, TRCAUXCTLR" + + - + input: + bytes: [ 0x09, 0x08, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x9, TRCEVENTCTL0R" + + - + input: + bytes: [ 0x10, 0x09, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x16, TRCEVENTCTL1R" + + - + input: + bytes: [ 0x04, 0x0b, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x4, TRCSTALLCTLR" + + - + input: + bytes: [ 0x0e, 0x0c, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x14, TRCTSCTLR" + + - + input: + bytes: [ 0x18, 0x0d, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x24, TRCSYNCPR" + + - + input: + bytes: [ 0x1c, 0x0e, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x28, TRCCCCTLR" + + - + input: + bytes: [ 0x0f, 0x0f, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x15, TRCBBCTLR" + + - + input: + bytes: [ 0x21, 0x00, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x1, TRCTRACEIDR" + + - + input: + bytes: [ 0x34, 0x01, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x20, TRCQCTLR" + + - + input: + bytes: [ 0x42, 0x00, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x2, TRCVICTLR" + + - + input: + bytes: [ 0x4c, 0x01, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x12, TRCVIIECTLR" + + - + input: + bytes: [ 0x50, 0x02, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x16, TRCVISSCTLR" + + - + input: + bytes: [ 0x48, 0x03, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x8, TRCVIPCSSCTLR" + + - + input: + bytes: [ 0x5b, 0x08, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x27, TRCVDCTLR" + + - + input: + bytes: [ 0x49, 0x09, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x9, TRCVDSACCTLR" + + - + input: + bytes: [ 0x40, 0x0a, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x0, TRCVDARCCTLR" + + - + input: + bytes: [ 0x8d, 0x00, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x13, TRCSEQEVR0" + + - + input: + bytes: [ 0x8b, 0x01, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x11, TRCSEQEVR1" + + - + input: + bytes: [ 0x9a, 0x02, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x26, TRCSEQEVR2" + + - + input: + bytes: [ 0x8e, 0x06, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x14, TRCSEQRSTEVR" + + - + input: + bytes: [ 0x84, 0x07, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x4, TRCSEQSTR" + + - + input: + bytes: [ 0x91, 0x08, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x17, TRCEXTINSELR" + + - + input: + bytes: [ 0xb5, 0x00, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x21, TRCCNTRLDVR0" + + - + input: + bytes: [ 0xaa, 0x01, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x10, TRCCNTRLDVR1" + + - + input: + bytes: [ 0xb4, 0x02, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x20, TRCCNTRLDVR2" + + - + input: + bytes: [ 0xa5, 0x03, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x5, TRCCNTRLDVR3" + + - + input: + bytes: [ 0xb1, 0x04, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x17, TRCCNTCTLR0" + + - + input: + bytes: [ 0xa1, 0x05, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x1, TRCCNTCTLR1" + + - + input: + bytes: [ 0xb1, 0x06, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x17, TRCCNTCTLR2" + + - + input: + bytes: [ 0xa6, 0x07, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x6, TRCCNTCTLR3" + + - + input: + bytes: [ 0xbc, 0x08, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x28, TRCCNTVR0" + + - + input: + bytes: [ 0xb7, 0x09, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x23, TRCCNTVR1" + + - + input: + bytes: [ 0xa9, 0x0a, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x9, TRCCNTVR2" + + - + input: + bytes: [ 0xa6, 0x0b, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x6, TRCCNTVR3" + + - + input: + bytes: [ 0xf8, 0x00, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x24, TRCIMSPEC0" + + - + input: + bytes: [ 0xf8, 0x01, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x24, TRCIMSPEC1" + + - + input: + bytes: [ 0xef, 0x02, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x15, TRCIMSPEC2" + + - + input: + bytes: [ 0xea, 0x03, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x10, TRCIMSPEC3" + + - + input: + bytes: [ 0xfd, 0x04, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x29, TRCIMSPEC4" + + - + input: + bytes: [ 0xf2, 0x05, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x18, TRCIMSPEC5" + + - + input: + bytes: [ 0xfd, 0x06, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x29, TRCIMSPEC6" + + - + input: + bytes: [ 0xe2, 0x07, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x2, TRCIMSPEC7" + + - + input: + bytes: [ 0x08, 0x12, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x8, TRCRSCTLR2" + + - + input: + bytes: [ 0x00, 0x13, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x0, TRCRSCTLR3" + + - + input: + bytes: [ 0x0c, 0x14, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x12, TRCRSCTLR4" + + - + input: + bytes: [ 0x1a, 0x15, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x26, TRCRSCTLR5" + + - + input: + bytes: [ 0x1d, 0x16, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x29, TRCRSCTLR6" + + - + input: + bytes: [ 0x11, 0x17, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x17, TRCRSCTLR7" + + - + input: + bytes: [ 0x00, 0x18, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x0, TRCRSCTLR8" + + - + input: + bytes: [ 0x01, 0x19, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x1, TRCRSCTLR9" + + - + input: + bytes: [ 0x11, 0x1a, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x17, TRCRSCTLR10" + + - + input: + bytes: [ 0x15, 0x1b, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x21, TRCRSCTLR11" + + - + input: + bytes: [ 0x01, 0x1c, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x1, TRCRSCTLR12" + + - + input: + bytes: [ 0x08, 0x1d, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x8, TRCRSCTLR13" + + - + input: + bytes: [ 0x18, 0x1e, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x24, TRCRSCTLR14" + + - + input: + bytes: [ 0x00, 0x1f, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x0, TRCRSCTLR15" + + - + input: + bytes: [ 0x22, 0x10, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x2, TRCRSCTLR16" + + - + input: + bytes: [ 0x3d, 0x11, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x29, TRCRSCTLR17" + + - + input: + bytes: [ 0x36, 0x12, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x22, TRCRSCTLR18" + + - + input: + bytes: [ 0x26, 0x13, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x6, TRCRSCTLR19" + + - + input: + bytes: [ 0x3a, 0x14, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x26, TRCRSCTLR20" + + - + input: + bytes: [ 0x3a, 0x15, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x26, TRCRSCTLR21" + + - + input: + bytes: [ 0x24, 0x16, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x4, TRCRSCTLR22" + + - + input: + bytes: [ 0x2c, 0x17, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x12, TRCRSCTLR23" + + - + input: + bytes: [ 0x21, 0x18, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x1, TRCRSCTLR24" + + - + input: + bytes: [ 0x20, 0x19, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x0, TRCRSCTLR25" + + - + input: + bytes: [ 0x31, 0x1a, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x17, TRCRSCTLR26" + + - + input: + bytes: [ 0x28, 0x1b, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x8, TRCRSCTLR27" + + - + input: + bytes: [ 0x2a, 0x1c, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x10, TRCRSCTLR28" + + - + input: + bytes: [ 0x39, 0x1d, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x25, TRCRSCTLR29" + + - + input: + bytes: [ 0x2c, 0x1e, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x12, TRCRSCTLR30" + + - + input: + bytes: [ 0x2b, 0x1f, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x11, TRCRSCTLR31" + + - + input: + bytes: [ 0x52, 0x10, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x18, TRCSSCCR0" + + - + input: + bytes: [ 0x4c, 0x11, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x12, TRCSSCCR1" + + - + input: + bytes: [ 0x43, 0x12, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x3, TRCSSCCR2" + + - + input: + bytes: [ 0x42, 0x13, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x2, TRCSSCCR3" + + - + input: + bytes: [ 0x55, 0x14, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x21, TRCSSCCR4" + + - + input: + bytes: [ 0x4a, 0x15, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x10, TRCSSCCR5" + + - + input: + bytes: [ 0x56, 0x16, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x22, TRCSSCCR6" + + - + input: + bytes: [ 0x57, 0x17, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x23, TRCSSCCR7" + + - + input: + bytes: [ 0x57, 0x18, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x23, TRCSSCSR0" + + - + input: + bytes: [ 0x53, 0x19, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x19, TRCSSCSR1" + + - + input: + bytes: [ 0x59, 0x1a, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x25, TRCSSCSR2" + + - + input: + bytes: [ 0x51, 0x1b, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x17, TRCSSCSR3" + + - + input: + bytes: [ 0x53, 0x1c, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x19, TRCSSCSR4" + + - + input: + bytes: [ 0x4b, 0x1d, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x11, TRCSSCSR5" + + - + input: + bytes: [ 0x45, 0x1e, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x5, TRCSSCSR6" + + - + input: + bytes: [ 0x49, 0x1f, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x9, TRCSSCSR7" + + - + input: + bytes: [ 0x61, 0x10, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x1, TRCSSPCICR0" + + - + input: + bytes: [ 0x6c, 0x11, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x12, TRCSSPCICR1" + + - + input: + bytes: [ 0x75, 0x12, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x21, TRCSSPCICR2" + + - + input: + bytes: [ 0x6b, 0x13, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x11, TRCSSPCICR3" + + - + input: + bytes: [ 0x63, 0x14, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x3, TRCSSPCICR4" + + - + input: + bytes: [ 0x69, 0x15, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x9, TRCSSPCICR5" + + - + input: + bytes: [ 0x65, 0x16, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x5, TRCSSPCICR6" + + - + input: + bytes: [ 0x62, 0x17, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x2, TRCSSPCICR7" + + - + input: + bytes: [ 0x9a, 0x14, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x26, TRCPDCR" + + - + input: + bytes: [ 0x08, 0x20, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x8, TRCACVR0" + + - + input: + bytes: [ 0x0f, 0x22, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x15, TRCACVR1" + + - + input: + bytes: [ 0x13, 0x24, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x19, TRCACVR2" + + - + input: + bytes: [ 0x08, 0x26, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x8, TRCACVR3" + + - + input: + bytes: [ 0x1c, 0x28, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x28, TRCACVR4" + + - + input: + bytes: [ 0x03, 0x2a, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x3, TRCACVR5" + + - + input: + bytes: [ 0x19, 0x2c, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x25, TRCACVR6" + + - + input: + bytes: [ 0x18, 0x2e, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x24, TRCACVR7" + + - + input: + bytes: [ 0x26, 0x20, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x6, TRCACVR8" + + - + input: + bytes: [ 0x23, 0x22, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x3, TRCACVR9" + + - + input: + bytes: [ 0x38, 0x24, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x24, TRCACVR10" + + - + input: + bytes: [ 0x23, 0x26, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x3, TRCACVR11" + + - + input: + bytes: [ 0x2c, 0x28, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x12, TRCACVR12" + + - + input: + bytes: [ 0x29, 0x2a, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x9, TRCACVR13" + + - + input: + bytes: [ 0x2e, 0x2c, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x14, TRCACVR14" + + - + input: + bytes: [ 0x23, 0x2e, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x3, TRCACVR15" + + - + input: + bytes: [ 0x55, 0x20, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x21, TRCACATR0" + + - + input: + bytes: [ 0x5a, 0x22, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x26, TRCACATR1" + + - + input: + bytes: [ 0x48, 0x24, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x8, TRCACATR2" + + - + input: + bytes: [ 0x56, 0x26, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x22, TRCACATR3" + + - + input: + bytes: [ 0x46, 0x28, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x6, TRCACATR4" + + - + input: + bytes: [ 0x5d, 0x2a, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x29, TRCACATR5" + + - + input: + bytes: [ 0x45, 0x2c, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x5, TRCACATR6" + + - + input: + bytes: [ 0x52, 0x2e, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x18, TRCACATR7" + + - + input: + bytes: [ 0x62, 0x20, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x2, TRCACATR8" + + - + input: + bytes: [ 0x73, 0x22, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x19, TRCACATR9" + + - + input: + bytes: [ 0x6d, 0x24, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x13, TRCACATR10" + + - + input: + bytes: [ 0x79, 0x26, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x25, TRCACATR11" + + - + input: + bytes: [ 0x72, 0x28, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x18, TRCACATR12" + + - + input: + bytes: [ 0x7d, 0x2a, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x29, TRCACATR13" + + - + input: + bytes: [ 0x69, 0x2c, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x9, TRCACATR14" + + - + input: + bytes: [ 0x72, 0x2e, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x18, TRCACATR15" + + - + input: + bytes: [ 0x9d, 0x20, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x29, TRCDVCVR0" + + - + input: + bytes: [ 0x8f, 0x24, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x15, TRCDVCVR1" + + - + input: + bytes: [ 0x8f, 0x28, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x15, TRCDVCVR2" + + - + input: + bytes: [ 0x8f, 0x2c, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x15, TRCDVCVR3" + + - + input: + bytes: [ 0xb3, 0x20, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x19, TRCDVCVR4" + + - + input: + bytes: [ 0xb6, 0x24, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x22, TRCDVCVR5" + + - + input: + bytes: [ 0xbb, 0x28, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x27, TRCDVCVR6" + + - + input: + bytes: [ 0xa1, 0x2c, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x1, TRCDVCVR7" + + - + input: + bytes: [ 0xdd, 0x20, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x29, TRCDVCMR0" + + - + input: + bytes: [ 0xc9, 0x24, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x9, TRCDVCMR1" + + - + input: + bytes: [ 0xc1, 0x28, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x1, TRCDVCMR2" + + - + input: + bytes: [ 0xc2, 0x2c, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x2, TRCDVCMR3" + + - + input: + bytes: [ 0xe5, 0x20, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x5, TRCDVCMR4" + + - + input: + bytes: [ 0xf5, 0x24, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x21, TRCDVCMR5" + + - + input: + bytes: [ 0xe5, 0x28, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x5, TRCDVCMR6" + + - + input: + bytes: [ 0xe1, 0x2c, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x1, TRCDVCMR7" + + - + input: + bytes: [ 0x15, 0x30, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x21, TRCCIDCVR0" + + - + input: + bytes: [ 0x18, 0x32, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x24, TRCCIDCVR1" + + - + input: + bytes: [ 0x18, 0x34, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x24, TRCCIDCVR2" + + - + input: + bytes: [ 0x0c, 0x36, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x12, TRCCIDCVR3" + + - + input: + bytes: [ 0x0a, 0x38, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x10, TRCCIDCVR4" + + - + input: + bytes: [ 0x09, 0x3a, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x9, TRCCIDCVR5" + + - + input: + bytes: [ 0x06, 0x3c, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x6, TRCCIDCVR6" + + - + input: + bytes: [ 0x14, 0x3e, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x20, TRCCIDCVR7" + + - + input: + bytes: [ 0x34, 0x30, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x20, TRCVMIDCVR0" + + - + input: + bytes: [ 0x34, 0x32, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x20, TRCVMIDCVR1" + + - + input: + bytes: [ 0x3a, 0x34, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x26, TRCVMIDCVR2" + + - + input: + bytes: [ 0x21, 0x36, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x1, TRCVMIDCVR3" + + - + input: + bytes: [ 0x2e, 0x38, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x14, TRCVMIDCVR4" + + - + input: + bytes: [ 0x3b, 0x3a, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x27, TRCVMIDCVR5" + + - + input: + bytes: [ 0x3d, 0x3c, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x29, TRCVMIDCVR6" + + - + input: + bytes: [ 0x31, 0x3e, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x17, TRCVMIDCVR7" + + - + input: + bytes: [ 0x4a, 0x30, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x10, TRCCIDCCTLR0" + + - + input: + bytes: [ 0x44, 0x31, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x4, TRCCIDCCTLR1" + + - + input: + bytes: [ 0x49, 0x32, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x9, TRCVMIDCCTLR0" + + - + input: + bytes: [ 0x4b, 0x33, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x11, TRCVMIDCCTLR1" + + - + input: + bytes: [ 0x96, 0x70, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x22, TRCITCTRL" + + - + input: + bytes: [ 0xd7, 0x78, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x23, TRCCLAIMSET" + + - + input: + bytes: [ 0xce, 0x79, 0x31, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "mrs x14, TRCCLAIMCLR" + + - + input: + bytes: [ 0x9c, 0x10, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCOSLAR, x28" + + - + input: + bytes: [ 0xce, 0x7c, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCLAR, x14" + + - + input: + bytes: [ 0x0a, 0x01, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCPRGCTLR, x10" + + - + input: + bytes: [ 0x1b, 0x02, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCPROCSELR, x27" + + - + input: + bytes: [ 0x18, 0x04, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCONFIGR, x24" + + - + input: + bytes: [ 0x08, 0x06, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCAUXCTLR, x8" + + - + input: + bytes: [ 0x10, 0x08, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCEVENTCTL0R, x16" + + - + input: + bytes: [ 0x1b, 0x09, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCEVENTCTL1R, x27" + + - + input: + bytes: [ 0x1a, 0x0b, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSTALLCTLR, x26" + + - + input: + bytes: [ 0x00, 0x0c, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCTSCTLR, x0" + + - + input: + bytes: [ 0x0e, 0x0d, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSYNCPR, x14" + + - + input: + bytes: [ 0x08, 0x0e, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCCCTLR, x8" + + - + input: + bytes: [ 0x06, 0x0f, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCBBCTLR, x6" + + - + input: + bytes: [ 0x37, 0x00, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCTRACEIDR, x23" + + - + input: + bytes: [ 0x25, 0x01, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCQCTLR, x5" + + - + input: + bytes: [ 0x40, 0x00, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCVICTLR, x0" + + - + input: + bytes: [ 0x40, 0x01, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCVIIECTLR, x0" + + - + input: + bytes: [ 0x41, 0x02, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCVISSCTLR, x1" + + - + input: + bytes: [ 0x40, 0x03, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCVIPCSSCTLR, x0" + + - + input: + bytes: [ 0x47, 0x08, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCVDCTLR, x7" + + - + input: + bytes: [ 0x52, 0x09, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCVDSACCTLR, x18" + + - + input: + bytes: [ 0x58, 0x0a, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCVDARCCTLR, x24" + + - + input: + bytes: [ 0x9c, 0x00, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSEQEVR0, x28" + + - + input: + bytes: [ 0x95, 0x01, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSEQEVR1, x21" + + - + input: + bytes: [ 0x90, 0x02, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSEQEVR2, x16" + + - + input: + bytes: [ 0x90, 0x06, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSEQRSTEVR, x16" + + - + input: + bytes: [ 0x99, 0x07, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSEQSTR, x25" + + - + input: + bytes: [ 0x9d, 0x08, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCEXTINSELR, x29" + + - + input: + bytes: [ 0xb4, 0x00, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCNTRLDVR0, x20" + + - + input: + bytes: [ 0xb4, 0x01, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCNTRLDVR1, x20" + + - + input: + bytes: [ 0xb6, 0x02, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCNTRLDVR2, x22" + + - + input: + bytes: [ 0xac, 0x03, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCNTRLDVR3, x12" + + - + input: + bytes: [ 0xb4, 0x04, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCNTCTLR0, x20" + + - + input: + bytes: [ 0xa4, 0x05, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCNTCTLR1, x4" + + - + input: + bytes: [ 0xa8, 0x06, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCNTCTLR2, x8" + + - + input: + bytes: [ 0xb0, 0x07, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCNTCTLR3, x16" + + - + input: + bytes: [ 0xa5, 0x08, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCNTVR0, x5" + + - + input: + bytes: [ 0xbb, 0x09, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCNTVR1, x27" + + - + input: + bytes: [ 0xb5, 0x0a, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCNTVR2, x21" + + - + input: + bytes: [ 0xa8, 0x0b, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCNTVR3, x8" + + - + input: + bytes: [ 0xe6, 0x00, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCIMSPEC0, x6" + + - + input: + bytes: [ 0xfb, 0x01, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCIMSPEC1, x27" + + - + input: + bytes: [ 0xf7, 0x02, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCIMSPEC2, x23" + + - + input: + bytes: [ 0xef, 0x03, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCIMSPEC3, x15" + + - + input: + bytes: [ 0xed, 0x04, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCIMSPEC4, x13" + + - + input: + bytes: [ 0xf9, 0x05, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCIMSPEC5, x25" + + - + input: + bytes: [ 0xf3, 0x06, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCIMSPEC6, x19" + + - + input: + bytes: [ 0xfb, 0x07, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCIMSPEC7, x27" + + - + input: + bytes: [ 0x04, 0x12, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR2, x4" + + - + input: + bytes: [ 0x00, 0x13, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR3, x0" + + - + input: + bytes: [ 0x15, 0x14, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR4, x21" + + - + input: + bytes: [ 0x08, 0x15, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR5, x8" + + - + input: + bytes: [ 0x14, 0x16, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR6, x20" + + - + input: + bytes: [ 0x0b, 0x17, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR7, x11" + + - + input: + bytes: [ 0x12, 0x18, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR8, x18" + + - + input: + bytes: [ 0x18, 0x19, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR9, x24" + + - + input: + bytes: [ 0x0f, 0x1a, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR10, x15" + + - + input: + bytes: [ 0x15, 0x1b, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR11, x21" + + - + input: + bytes: [ 0x04, 0x1c, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR12, x4" + + - + input: + bytes: [ 0x1c, 0x1d, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR13, x28" + + - + input: + bytes: [ 0x03, 0x1e, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR14, x3" + + - + input: + bytes: [ 0x14, 0x1f, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR15, x20" + + - + input: + bytes: [ 0x2c, 0x10, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR16, x12" + + - + input: + bytes: [ 0x31, 0x11, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR17, x17" + + - + input: + bytes: [ 0x2a, 0x12, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR18, x10" + + - + input: + bytes: [ 0x2b, 0x13, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR19, x11" + + - + input: + bytes: [ 0x23, 0x14, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR20, x3" + + - + input: + bytes: [ 0x32, 0x15, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR21, x18" + + - + input: + bytes: [ 0x3a, 0x16, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR22, x26" + + - + input: + bytes: [ 0x25, 0x17, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR23, x5" + + - + input: + bytes: [ 0x39, 0x18, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR24, x25" + + - + input: + bytes: [ 0x25, 0x19, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR25, x5" + + - + input: + bytes: [ 0x24, 0x1a, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR26, x4" + + - + input: + bytes: [ 0x34, 0x1b, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR27, x20" + + - + input: + bytes: [ 0x25, 0x1c, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR28, x5" + + - + input: + bytes: [ 0x2a, 0x1d, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR29, x10" + + - + input: + bytes: [ 0x38, 0x1e, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR30, x24" + + - + input: + bytes: [ 0x34, 0x1f, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCRSCTLR31, x20" + + - + input: + bytes: [ 0x57, 0x10, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSCCR0, x23" + + - + input: + bytes: [ 0x5b, 0x11, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSCCR1, x27" + + - + input: + bytes: [ 0x5b, 0x12, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSCCR2, x27" + + - + input: + bytes: [ 0x46, 0x13, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSCCR3, x6" + + - + input: + bytes: [ 0x43, 0x14, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSCCR4, x3" + + - + input: + bytes: [ 0x4c, 0x15, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSCCR5, x12" + + - + input: + bytes: [ 0x47, 0x16, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSCCR6, x7" + + - + input: + bytes: [ 0x46, 0x17, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSCCR7, x6" + + - + input: + bytes: [ 0x54, 0x18, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSCSR0, x20" + + - + input: + bytes: [ 0x51, 0x19, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSCSR1, x17" + + - + input: + bytes: [ 0x4b, 0x1a, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSCSR2, x11" + + - + input: + bytes: [ 0x44, 0x1b, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSCSR3, x4" + + - + input: + bytes: [ 0x4e, 0x1c, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSCSR4, x14" + + - + input: + bytes: [ 0x56, 0x1d, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSCSR5, x22" + + - + input: + bytes: [ 0x43, 0x1e, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSCSR6, x3" + + - + input: + bytes: [ 0x4b, 0x1f, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSCSR7, x11" + + - + input: + bytes: [ 0x62, 0x10, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSPCICR0, x2" + + - + input: + bytes: [ 0x63, 0x11, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSPCICR1, x3" + + - + input: + bytes: [ 0x65, 0x12, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSPCICR2, x5" + + - + input: + bytes: [ 0x67, 0x13, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSPCICR3, x7" + + - + input: + bytes: [ 0x6b, 0x14, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSPCICR4, x11" + + - + input: + bytes: [ 0x6d, 0x15, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSPCICR5, x13" + + - + input: + bytes: [ 0x71, 0x16, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSPCICR6, x17" + + - + input: + bytes: [ 0x77, 0x17, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCSSPCICR7, x23" + + - + input: + bytes: [ 0x83, 0x14, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCPDCR, x3" + + - + input: + bytes: [ 0x06, 0x20, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACVR0, x6" + + - + input: + bytes: [ 0x14, 0x22, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACVR1, x20" + + - + input: + bytes: [ 0x19, 0x24, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACVR2, x25" + + - + input: + bytes: [ 0x01, 0x26, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACVR3, x1" + + - + input: + bytes: [ 0x1c, 0x28, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACVR4, x28" + + - + input: + bytes: [ 0x0f, 0x2a, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACVR5, x15" + + - + input: + bytes: [ 0x19, 0x2c, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACVR6, x25" + + - + input: + bytes: [ 0x0c, 0x2e, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACVR7, x12" + + - + input: + bytes: [ 0x25, 0x20, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACVR8, x5" + + - + input: + bytes: [ 0x39, 0x22, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACVR9, x25" + + - + input: + bytes: [ 0x2d, 0x24, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACVR10, x13" + + - + input: + bytes: [ 0x2a, 0x26, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACVR11, x10" + + - + input: + bytes: [ 0x33, 0x28, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACVR12, x19" + + - + input: + bytes: [ 0x2a, 0x2a, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACVR13, x10" + + - + input: + bytes: [ 0x33, 0x2c, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACVR14, x19" + + - + input: + bytes: [ 0x22, 0x2e, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACVR15, x2" + + - + input: + bytes: [ 0x4f, 0x20, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACATR0, x15" + + - + input: + bytes: [ 0x4d, 0x22, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACATR1, x13" + + - + input: + bytes: [ 0x48, 0x24, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACATR2, x8" + + - + input: + bytes: [ 0x41, 0x26, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACATR3, x1" + + - + input: + bytes: [ 0x4b, 0x28, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACATR4, x11" + + - + input: + bytes: [ 0x48, 0x2a, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACATR5, x8" + + - + input: + bytes: [ 0x58, 0x2c, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACATR6, x24" + + - + input: + bytes: [ 0x46, 0x2e, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACATR7, x6" + + - + input: + bytes: [ 0x77, 0x20, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACATR8, x23" + + - + input: + bytes: [ 0x65, 0x22, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACATR9, x5" + + - + input: + bytes: [ 0x6b, 0x24, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACATR10, x11" + + - + input: + bytes: [ 0x6b, 0x26, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACATR11, x11" + + - + input: + bytes: [ 0x63, 0x28, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACATR12, x3" + + - + input: + bytes: [ 0x7c, 0x2a, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACATR13, x28" + + - + input: + bytes: [ 0x79, 0x2c, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACATR14, x25" + + - + input: + bytes: [ 0x64, 0x2e, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCACATR15, x4" + + - + input: + bytes: [ 0x86, 0x20, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCDVCVR0, x6" + + - + input: + bytes: [ 0x83, 0x24, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCDVCVR1, x3" + + - + input: + bytes: [ 0x85, 0x28, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCDVCVR2, x5" + + - + input: + bytes: [ 0x8b, 0x2c, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCDVCVR3, x11" + + - + input: + bytes: [ 0xa9, 0x20, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCDVCVR4, x9" + + - + input: + bytes: [ 0xae, 0x24, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCDVCVR5, x14" + + - + input: + bytes: [ 0xaa, 0x28, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCDVCVR6, x10" + + - + input: + bytes: [ 0xac, 0x2c, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCDVCVR7, x12" + + - + input: + bytes: [ 0xc8, 0x20, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCDVCMR0, x8" + + - + input: + bytes: [ 0xc8, 0x24, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCDVCMR1, x8" + + - + input: + bytes: [ 0xd6, 0x28, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCDVCMR2, x22" + + - + input: + bytes: [ 0xd6, 0x2c, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCDVCMR3, x22" + + - + input: + bytes: [ 0xe5, 0x20, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCDVCMR4, x5" + + - + input: + bytes: [ 0xf0, 0x24, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCDVCMR5, x16" + + - + input: + bytes: [ 0xfb, 0x28, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCDVCMR6, x27" + + - + input: + bytes: [ 0xf5, 0x2c, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCDVCMR7, x21" + + - + input: + bytes: [ 0x08, 0x30, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCIDCVR0, x8" + + - + input: + bytes: [ 0x06, 0x32, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCIDCVR1, x6" + + - + input: + bytes: [ 0x09, 0x34, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCIDCVR2, x9" + + - + input: + bytes: [ 0x08, 0x36, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCIDCVR3, x8" + + - + input: + bytes: [ 0x03, 0x38, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCIDCVR4, x3" + + - + input: + bytes: [ 0x15, 0x3a, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCIDCVR5, x21" + + - + input: + bytes: [ 0x0c, 0x3c, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCIDCVR6, x12" + + - + input: + bytes: [ 0x07, 0x3e, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCIDCVR7, x7" + + - + input: + bytes: [ 0x24, 0x30, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCVMIDCVR0, x4" + + - + input: + bytes: [ 0x23, 0x32, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCVMIDCVR1, x3" + + - + input: + bytes: [ 0x29, 0x34, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCVMIDCVR2, x9" + + - + input: + bytes: [ 0x31, 0x36, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCVMIDCVR3, x17" + + - + input: + bytes: [ 0x2e, 0x38, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCVMIDCVR4, x14" + + - + input: + bytes: [ 0x2c, 0x3a, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCVMIDCVR5, x12" + + - + input: + bytes: [ 0x2a, 0x3c, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCVMIDCVR6, x10" + + - + input: + bytes: [ 0x23, 0x3e, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCVMIDCVR7, x3" + + - + input: + bytes: [ 0x4e, 0x30, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCIDCCTLR0, x14" + + - + input: + bytes: [ 0x56, 0x31, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCIDCCTLR1, x22" + + - + input: + bytes: [ 0x48, 0x32, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCVMIDCCTLR0, x8" + + - + input: + bytes: [ 0x4f, 0x33, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCVMIDCCTLR1, x15" + + - + input: + bytes: [ 0x81, 0x70, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCITCTRL, x1" + + - + input: + bytes: [ 0xc7, 0x78, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCLAIMSET, x7" + + - + input: + bytes: [ 0xdd, 0x79, 0x11, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ] + expected: + insns: + - + asm_text: "msr TRCCLAIMCLR, x29" diff --git a/tests/MC/AArch64/trbe-sysreg.s.yaml b/tests/MC/AArch64/trbe-sysreg.s.yaml new file mode 100644 index 0000000000..4da8487612 --- /dev/null +++ b/tests/MC/AArch64/trbe-sysreg.s.yaml @@ -0,0 +1,130 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x9b, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, TRBLIMITR_EL1" + + - + input: + bytes: [ 0x20, 0x9b, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, TRBPTR_EL1" + + - + input: + bytes: [ 0x40, 0x9b, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, TRBBASER_EL1" + + - + input: + bytes: [ 0x60, 0x9b, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, TRBSR_EL1" + + - + input: + bytes: [ 0x80, 0x9b, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, TRBMAR_EL1" + + - + input: + bytes: [ 0xc0, 0x9b, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, TRBTRG_EL1" + + - + input: + bytes: [ 0xe0, 0x9b, 0x38, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "mrs x0, TRBIDR_EL1" + + - + input: + bytes: [ 0x00, 0x9b, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr TRBLIMITR_EL1, x0" + + - + input: + bytes: [ 0x20, 0x9b, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr TRBPTR_EL1, x0" + + - + input: + bytes: [ 0x40, 0x9b, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr TRBBASER_EL1, x0" + + - + input: + bytes: [ 0x60, 0x9b, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr TRBSR_EL1, x0" + + - + input: + bytes: [ 0x80, 0x9b, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr TRBMAR_EL1, x0" + + - + input: + bytes: [ 0xc0, 0x9b, 0x18, 0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ] + expected: + insns: + - + asm_text: "msr TRBTRG_EL1, x0" diff --git a/tests/MC/AArch64/udf.s.yaml b/tests/MC/AArch64/udf.s.yaml new file mode 100644 index 0000000000..018649e416 --- /dev/null +++ b/tests/MC/AArch64/udf.s.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-" ] + expected: + insns: + - + asm_text: "udf #0" + + - + input: + bytes: [ 0x01, 0x02, 0x00, 0x00 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-" ] + expected: + insns: + - + asm_text: "udf #513" + + - + input: + bytes: [ 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-" ] + expected: + insns: + - + asm_text: "udf #65535" diff --git a/tests/MC/ARM/arm-aliases.s.yaml b/tests/MC/ARM/arm-aliases.s.yaml new file mode 100644 index 0000000000..5338902d5e --- /dev/null +++ b/tests/MC/ARM/arm-aliases.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x03, 0x10, 0x82, 0xe0, 0x03, 0x10, 0x42, 0xe0, 0x03, 0x10, 0x22, 0xe0, 0x03, 0x10, 0x82, 0xe1, 0x03, 0x10, 0x02, 0xe0, 0x03, 0x10, 0xc2, 0xe1 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "add r1, r2, r3" + - + asm_text: "sub r1, r2, r3" + - + asm_text: "eor r1, r2, r3" + - + asm_text: "orr r1, r2, r3" + - + asm_text: "and r1, r2, r3" + - + asm_text: "bic r1, r2, r3" diff --git a/tests/MC/ARM/arm-arithmetic-aliases.s.yaml b/tests/MC/ARM/arm-arithmetic-aliases.s.yaml new file mode 100644 index 0000000000..a1788540c6 --- /dev/null +++ b/tests/MC/ARM/arm-arithmetic-aliases.s.yaml @@ -0,0 +1,106 @@ +test_cases: + - + input: + bytes: [ 0x06, 0x20, 0x42, 0xe2, 0x06, 0x20, 0x42, 0xe2, 0x03, 0x20, 0x42, 0xe0, 0x03, 0x20, 0x42, 0xe0, 0x06, 0x20, 0x82, 0xe2, 0x06, 0x20, 0x82, 0xe2, 0x03, 0x20, 0x82, 0xe0, 0x03, 0x20, 0x82, 0xe0, 0x06, 0x20, 0x02, 0xe2, 0x06, 0x20, 0x02, 0xe2, 0x03, 0x20, 0x02, 0xe0, 0x03, 0x20, 0x02, 0xe0, 0x06, 0x20, 0x82, 0xe3, 0x06, 0x20, 0x82, 0xe3, 0x03, 0x20, 0x82, 0xe1, 0x03, 0x20, 0x82, 0xe1, 0x06, 0x20, 0x22, 0xe2, 0x06, 0x20, 0x22, 0xe2, 0x03, 0x20, 0x22, 0xe0, 0x03, 0x20, 0x22, 0xe0, 0x06, 0x20, 0xc2, 0xe3, 0x06, 0x20, 0xc2, 0xe3, 0x03, 0x20, 0xc2, 0xe1, 0x03, 0x20, 0xc2, 0xe1, 0x06, 0x20, 0x52, 0x02, 0x06, 0x20, 0x52, 0x02, 0x03, 0x20, 0x52, 0x00, 0x03, 0x20, 0x52, 0x00, 0x06, 0x20, 0x92, 0x02, 0x06, 0x20, 0x92, 0x02, 0x03, 0x20, 0x92, 0x00, 0x03, 0x20, 0x92, 0x00, 0x06, 0x20, 0x12, 0x02, 0x06, 0x20, 0x12, 0x02, 0x03, 0x20, 0x12, 0x00, 0x03, 0x20, 0x12, 0x00, 0x06, 0x20, 0x92, 0x03, 0x06, 0x20, 0x92, 0x03, 0x03, 0x20, 0x92, 0x01, 0x03, 0x20, 0x92, 0x01, 0x06, 0x20, 0x32, 0x02, 0x06, 0x20, 0x32, 0x02, 0x03, 0x20, 0x32, 0x00, 0x03, 0x20, 0x32, 0x00, 0x06, 0x20, 0xd2, 0x03, 0x06, 0x20, 0xd2, 0x03, 0x03, 0x20, 0xd2, 0x01, 0x03, 0x20, 0xd2, 0x01, 0x7b, 0x00, 0x8f, 0xe2 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "sub r2, r2, #6" + - + asm_text: "sub r2, r2, #6" + - + asm_text: "sub r2, r2, r3" + - + asm_text: "sub r2, r2, r3" + - + asm_text: "add r2, r2, #6" + - + asm_text: "add r2, r2, #6" + - + asm_text: "add r2, r2, r3" + - + asm_text: "add r2, r2, r3" + - + asm_text: "and r2, r2, #6" + - + asm_text: "and r2, r2, #6" + - + asm_text: "and r2, r2, r3" + - + asm_text: "and r2, r2, r3" + - + asm_text: "orr r2, r2, #6" + - + asm_text: "orr r2, r2, #6" + - + asm_text: "orr r2, r2, r3" + - + asm_text: "orr r2, r2, r3" + - + asm_text: "eor r2, r2, #6" + - + asm_text: "eor r2, r2, #6" + - + asm_text: "eor r2, r2, r3" + - + asm_text: "eor r2, r2, r3" + - + asm_text: "bic r2, r2, #6" + - + asm_text: "bic r2, r2, #6" + - + asm_text: "bic r2, r2, r3" + - + asm_text: "bic r2, r2, r3" + - + asm_text: "subseq r2, r2, #6" + - + asm_text: "subseq r2, r2, #6" + - + asm_text: "subseq r2, r2, r3" + - + asm_text: "subseq r2, r2, r3" + - + asm_text: "addseq r2, r2, #6" + - + asm_text: "addseq r2, r2, #6" + - + asm_text: "addseq r2, r2, r3" + - + asm_text: "addseq r2, r2, r3" + - + asm_text: "andseq r2, r2, #6" + - + asm_text: "andseq r2, r2, #6" + - + asm_text: "andseq r2, r2, r3" + - + asm_text: "andseq r2, r2, r3" + - + asm_text: "orrseq r2, r2, #6" + - + asm_text: "orrseq r2, r2, #6" + - + asm_text: "orrseq r2, r2, r3" + - + asm_text: "orrseq r2, r2, r3" + - + asm_text: "eorseq r2, r2, #6" + - + asm_text: "eorseq r2, r2, #6" + - + asm_text: "eorseq r2, r2, r3" + - + asm_text: "eorseq r2, r2, r3" + - + asm_text: "bicseq r2, r2, #6" + - + asm_text: "bicseq r2, r2, #6" + - + asm_text: "bicseq r2, r2, r3" + - + asm_text: "bicseq r2, r2, r3" + - + asm_text: "add r0, pc, #0x7b" diff --git a/tests/MC/ARM/arm-branches.s.yaml b/tests/MC/ARM/arm-branches.s.yaml new file mode 100644 index 0000000000..b443756c81 --- /dev/null +++ b/tests/MC/ARM/arm-branches.s.yaml @@ -0,0 +1,18 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x00, 0x00, 0xea, 0x01, 0x00, 0x00, 0xeb, 0x01, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0xfb, 0x01, 0x00, 0x00, 0xea ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "b #4" + - + asm_text: "bl #4" + - + asm_text: "beq #4" + - + asm_text: "blx #2" + - + asm_text: "b #4" diff --git a/tests/MC/ARM/arm-it-block.s.yaml b/tests/MC/ARM/arm-it-block.s.yaml new file mode 100644 index 0000000000..252fb18742 --- /dev/null +++ b/tests/MC/ARM/arm-it-block.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x03, 0x20, 0xa0, 0x01 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "moveq r2, r3" diff --git a/tests/MC/ARM/arm-memory-instructions.s.yaml b/tests/MC/ARM/arm-memory-instructions.s.yaml new file mode 100644 index 0000000000..8a3d1a40d4 --- /dev/null +++ b/tests/MC/ARM/arm-memory-instructions.s.yaml @@ -0,0 +1,292 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x50, 0x97, 0xe5, 0x3f, 0x60, 0x93, 0xe5, 0xff, 0x2f, 0xb4, 0xe5, 0x1e, 0x10, 0x92, 0xe4, 0x1e, 0x30, 0x11, 0xe4, 0x00, 0x90, 0x12, 0xe4, 0x01, 0x30, 0x98, 0xe7, 0x03, 0x20, 0x15, 0xe7, 0x09, 0x10, 0xb5, 0xe7, 0x08, 0x60, 0x37, 0xe7, 0xa2, 0x11, 0xb0, 0xe7, 0x02, 0x50, 0x99, 0xe6, 0x06, 0x40, 0x13, 0xe6, 0x82, 0x37, 0x18, 0xe7, 0xc3, 0x17, 0x95, 0xe6, 0x00, 0x30, 0xd8, 0xe5, 0x3f, 0x10, 0xdd, 0xe5, 0xff, 0x9f, 0xf3, 0xe5, 0x16, 0x80, 0xd1, 0xe4, 0x13, 0x20, 0x57, 0xe4, 0x05, 0x90, 0xd8, 0xe7, 0x01, 0x10, 0x55, 0xe7, 0x02, 0x30, 0xf5, 0xe7, 0x03, 0x60, 0x79, 0xe7, 0x04, 0x20, 0xd1, 0xe6, 0x05, 0x80, 0x54, 0xe6, 0x81, 0x77, 0x5c, 0xe7, 0xc9, 0x57, 0xd2, 0xe6, 0x04, 0x30, 0xf1, 0xe4, 0x08, 0x20, 0x78, 0xe4, 0x06, 0x80, 0xf7, 0xe6, 0x06, 0x16, 0x72, 0xe6, 0xd0, 0x20, 0xc5, 0xe1, 0xdf, 0x60, 0xc2, 0xe1, 0xd0, 0x02, 0xe9, 0xe1, 0xd8, 0x60, 0xc1, 0xe0, 0xd0, 0x00, 0xc8, 0xe0, 0xd0, 0x00, 0xc8, 0xe0, 0xd0, 0x00, 0x48, 0xe0, 0xd3, 0x40, 0x81, 0xe1, 0xd2, 0x40, 0xa7, 0xe1, 0xdc, 0x00, 0x88, 0xe0, 0xdc, 0x00, 0x08, 0xe0, 0xb0, 0x30, 0xd4, 0xe1, 0xb4, 0x20, 0xd7, 0xe1, 0xb0, 0x14, 0xf8, 0xe1, 0xb4, 0xc0, 0xdd, 0xe0, 0xb4, 0x60, 0x95, 0xe1, 0xbb, 0x30, 0xb8, 0xe1, 0xb1, 0x10, 0x32, 0xe1, 0xb2, 0x90, 0x97, 0xe0, 0xb2, 0x40, 0x13, 0xe0, 0xb0, 0x98, 0xf7, 0xe0, 0xbb, 0x44, 0x73, 0xe0, 0xb0, 0x40, 0xf3, 0xe0, 0xb2, 0x90, 0xb7, 0xe0, 0xb2, 0x40, 0x33, 0xe0, 0xd0, 0x30, 0xd4, 0xe1, 0xd1, 0x21, 0xd7, 0xe1, 0xdf, 0x1f, 0xf8, 0xe1, 0xd9, 0xc0, 0xdd, 0xe0, 0xd4, 0x60, 0x95, 0xe1, 0xdb, 0x30, 0xb8, 0xe1, 0xd1, 0x10, 0x32, 0xe1, 0xd2, 0x90, 0x97, 0xe0, 0xd2, 0x40, 0x13, 0xe0, 0xd1, 0x50, 0xf6, 0xe0, 0xdc, 0x30, 0x78, 0xe0, 0xd0, 0x50, 0xf6, 0xe0, 0xd5, 0x80, 0xb9, 0xe0, 0xd4, 0x20, 0x31, 0xe0, 0xf0, 0x50, 0xd9, 0xe1, 0xf7, 0x40, 0xd5, 0xe1, 0xf7, 0x33, 0xf6, 0xe1, 0xf9, 0x20, 0x57, 0xe0, 0xf5, 0x30, 0x91, 0xe1, 0xf1, 0x40, 0xb6, 0xe1, 0xf6, 0x50, 0x33, 0xe1, 0xf8, 0x60, 0x99, 0xe0, 0xf3, 0x70, 0x18, 0xe0, 0xf1, 0x50, 0xf6, 0xe0, 0xfc, 0x30, 0x78, 0xe0, 0xf0, 0x50, 0xf6, 0xe0, 0xf5, 0x80, 0xb9, 0xe0, 0xf4, 0x20, 0x31, 0xe0, 0x00, 0x80, 0x8c, 0xe5, 0x0c, 0x70, 0x81, 0xe5, 0x28, 0x30, 0xa5, 0xe5, 0xff, 0x9f, 0x8d, 0xe4, 0x80, 0x10, 0x07, 0xe4, 0x00, 0x10, 0x00, 0xe4, 0x03, 0x90, 0x86, 0xe7, 0x02, 0x80, 0x00, 0xe7, 0x06, 0x70, 0xa1, 0xe7, 0x01, 0x60, 0x2d, 0xe7, 0x09, 0x50, 0x83, 0xe6, 0x05, 0x40, 0x02, 0xe6, 0x02, 0x31, 0x04, 0xe7, 0x43, 0x2c, 0x87, 0xe6, 0x00, 0x90, 0xc2, 0xe5, 0x03, 0x70, 0xc1, 0xe5, 0x95, 0x61, 0xe4, 0xe5, 0x48, 0x50, 0xc7, 0xe4, 0x01, 0x10, 0x4d, 0xe4, 0x09, 0x10, 0xc2, 0xe7, 0x08, 0x20, 0x43, 0xe7, 0x07, 0x30, 0xe4, 0xe7, 0x06, 0x40, 0x65, 0xe7, 0x05, 0x50, 0xc6, 0xe6, 0x04, 0x60, 0x42, 0xe6, 0x83, 0x72, 0x4c, 0xe7, 0x42, 0xd6, 0xc7, 0xe6, 0x0c, 0x60, 0xe2, 0xe4, 0x0d, 0x50, 0x66, 0xe4, 0x05, 0x40, 0xe9, 0xe6, 0x82, 0x31, 0x68, 0xe6, 0xf0, 0x20, 0xc4, 0xe1, 0xf1, 0x20, 0xc6, 0xe1, 0xf6, 0x01, 0xe7, 0xe1, 0xf7, 0x40, 0xc8, 0xe0, 0xf0, 0x40, 0xcd, 0xe0, 0xf0, 0x60, 0xce, 0xe0, 0xf0, 0xa0, 0x49, 0xe0, 0xf1, 0x80, 0x84, 0xe1, 0xf9, 0x60, 0xa3, 0xe1, 0xf8, 0x60, 0x85, 0xe0, 0xfa, 0x40, 0x0c, 0xe0, 0xb0, 0x30, 0xc4, 0xe1, 0xb4, 0x20, 0xc7, 0xe1, 0xb0, 0x14, 0xe8, 0xe1, 0xb4, 0xc0, 0xcd, 0xe0, 0xb4, 0x60, 0x85, 0xe1, 0xbb, 0x30, 0xa8, 0xe1, 0xb1, 0x10, 0x22, 0xe1, 0xb2, 0x90, 0x87, 0xe0, 0xb2, 0x40, 0x03, 0xe0, 0xbc, 0x24, 0xe5, 0xe0, 0xb9, 0x81, 0x61, 0xe0, 0xb4, 0x50, 0xa3, 0xe0, 0xb0, 0x60, 0x28, 0xe0, 0xd0, 0x00, 0xcd, 0xe1, 0xf0, 0x00, 0xcd, 0xe1 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "ldr r5, [r7]" + - + asm_text: "ldr r6, [r3, #0x3f]" + - + asm_text: "ldr r2, [r4, #0xfff]!" + - + asm_text: "ldr r1, [r2], #0x1e" + - + asm_text: "ldr r3, [r1], #-0x1e" + - + asm_text: "ldr r9, [r2], #-0" + - + asm_text: "ldr r3, [r8, r1]" + - + asm_text: "ldr r2, [r5, -r3]" + - + asm_text: "ldr r1, [r5, r9]!" + - + asm_text: "ldr r6, [r7, -r8]!" + - + asm_text: "ldr r1, [r0, r2, lsr #3]!" + - + asm_text: "ldr r5, [r9], r2" + - + asm_text: "ldr r4, [r3], -r6" + - + asm_text: "ldr r3, [r8, -r2, lsl #0xf]" + - + asm_text: "ldr r1, [r5], r3, asr #0xf" + - + asm_text: "ldrb r3, [r8]" + - + asm_text: "ldrb r1, [sp, #0x3f]" + - + asm_text: "ldrb r9, [r3, #0xfff]!" + - + asm_text: "ldrb r8, [r1], #0x16" + - + asm_text: "ldrb r2, [r7], #-0x13" + - + asm_text: "ldrb r9, [r8, r5]" + - + asm_text: "ldrb r1, [r5, -r1]" + - + asm_text: "ldrb r3, [r5, r2]!" + - + asm_text: "ldrb r6, [r9, -r3]!" + - + asm_text: "ldrb r2, [r1], r4" + - + asm_text: "ldrb r8, [r4], -r5" + - + asm_text: "ldrb r7, [r12, -r1, lsl #0xf]" + - + asm_text: "ldrb r5, [r2], r9, asr #0xf" + - + asm_text: "ldrbt r3, [r1], #4" + - + asm_text: "ldrbt r2, [r8], #-8" + - + asm_text: "ldrbt r8, [r7], r6" + - + asm_text: "ldrbt r1, [r2], -r6, lsl #0xc" + - + asm_text: "ldrd r2, r3, [r5]" + - + asm_text: "ldrd r6, r7, [r2, #0xf]" + - + asm_text: "ldrd r0, r1, [r9, #0x20]!" + - + asm_text: "ldrd r6, r7, [r1], #8" + - + asm_text: "ldrd r0, r1, [r8], #0" + - + asm_text: "ldrd r0, r1, [r8], #0" + - + asm_text: "ldrd r0, r1, [r8], #-0" + - + asm_text: "ldrd r4, r5, [r1, r3]" + - + asm_text: "ldrd r4, r5, [r7, r2]!" + - + asm_text: "ldrd r0, r1, [r8], r12" + - + asm_text: "ldrd r0, r1, [r8], -r12" + - + asm_text: "ldrh r3, [r4]" + - + asm_text: "ldrh r2, [r7, #4]" + - + asm_text: "ldrh r1, [r8, #0x40]!" + - + asm_text: "ldrh r12, [sp], #4" + - + asm_text: "ldrh r6, [r5, r4]" + - + asm_text: "ldrh r3, [r8, r11]!" + - + asm_text: "ldrh r1, [r2, -r1]!" + - + asm_text: "ldrh r9, [r7], r2" + - + asm_text: "ldrh r4, [r3], -r2" + - + asm_text: "ldrht r9, [r7], #0x80" + - + asm_text: "ldrht r4, [r3], #-0x4b" + - + asm_text: "ldrht r4, [r3], #0" + - + asm_text: "ldrht r9, [r7], r2" + - + asm_text: "ldrht r4, [r3], -r2" + - + asm_text: "ldrsb r3, [r4]" + - + asm_text: "ldrsb r2, [r7, #0x11]" + - + asm_text: "ldrsb r1, [r8, #0xff]!" + - + asm_text: "ldrsb r12, [sp], #0x9" + - + asm_text: "ldrsb r6, [r5, r4]" + - + asm_text: "ldrsb r3, [r8, r11]!" + - + asm_text: "ldrsb r1, [r2, -r1]!" + - + asm_text: "ldrsb r9, [r7], r2" + - + asm_text: "ldrsb r4, [r3], -r2" + - + asm_text: "ldrsbt r5, [r6], #1" + - + asm_text: "ldrsbt r3, [r8], #-0xc" + - + asm_text: "ldrsbt r5, [r6], #0" + - + asm_text: "ldrsbt r8, [r9], r5" + - + asm_text: "ldrsbt r2, [r1], -r4" + - + asm_text: "ldrsh r5, [r9]" + - + asm_text: "ldrsh r4, [r5, #7]" + - + asm_text: "ldrsh r3, [r6, #0x37]!" + - + asm_text: "ldrsh r2, [r7], #-0x9" + - + asm_text: "ldrsh r3, [r1, r5]" + - + asm_text: "ldrsh r4, [r6, r1]!" + - + asm_text: "ldrsh r5, [r3, -r6]!" + - + asm_text: "ldrsh r6, [r9], r8" + - + asm_text: "ldrsh r7, [r8], -r3" + - + asm_text: "ldrsht r5, [r6], #1" + - + asm_text: "ldrsht r3, [r8], #-0xc" + - + asm_text: "ldrsht r5, [r6], #0" + - + asm_text: "ldrsht r8, [r9], r5" + - + asm_text: "ldrsht r2, [r1], -r4" + - + asm_text: "str r8, [r12]" + - + asm_text: "str r7, [r1, #0xc]" + - + asm_text: "str r3, [r5, #0x28]!" + - + asm_text: "str r9, [sp], #0xfff" + - + asm_text: "str r1, [r7], #-0x80" + - + asm_text: "str r1, [r0], #-0" + - + asm_text: "str r9, [r6, r3]" + - + asm_text: "str r8, [r0, -r2]" + - + asm_text: "str r7, [r1, r6]!" + - + asm_text: "str r6, [sp, -r1]!" + - + asm_text: "str r5, [r3], r9" + - + asm_text: "str r4, [r2], -r5" + - + asm_text: "str r3, [r4, -r2, lsl #2]" + - + asm_text: "str r2, [r7], r3, asr #0x18" + - + asm_text: "strb r9, [r2]" + - + asm_text: "strb r7, [r1, #3]" + - + asm_text: "strb r6, [r4, #0x195]!" + - + asm_text: "strb r5, [r7], #0x48" + - + asm_text: "strb r1, [sp], #-1" + - + asm_text: "strb r1, [r2, r9]" + - + asm_text: "strb r2, [r3, -r8]" + - + asm_text: "strb r3, [r4, r7]!" + - + asm_text: "strb r4, [r5, -r6]!" + - + asm_text: "strb r5, [r6], r5" + - + asm_text: "strb r6, [r2], -r4" + - + asm_text: "strb r7, [r12, -r3, lsl #5]" + - + asm_text: "strb sp, [r7], r2, asr #0xc" + - + asm_text: "strbt r6, [r2], #0xc" + - + asm_text: "strbt r5, [r6], #-0xd" + - + asm_text: "strbt r4, [r9], r5" + - + asm_text: "strbt r3, [r8], -r2, lsl #3" + - + asm_text: "strd r2, r3, [r4]" + - + asm_text: "strd r2, r3, [r6, #1]" + - + asm_text: "strd r0, r1, [r7, #0x16]!" + - + asm_text: "strd r4, r5, [r8], #7" + - + asm_text: "strd r4, r5, [sp], #0" + - + asm_text: "strd r6, r7, [lr], #0" + - + asm_text: "strd r10, r11, [r9], #-0" + - + asm_text: "strd r8, r9, [r4, r1]" + - + asm_text: "strd r6, r7, [r3, r9]!" + - + asm_text: "strd r6, r7, [r5], r8" + - + asm_text: "strd r4, r5, [r12], -r10" + - + asm_text: "strh r3, [r4]" + - + asm_text: "strh r2, [r7, #4]" + - + asm_text: "strh r1, [r8, #0x40]!" + - + asm_text: "strh r12, [sp], #4" + - + asm_text: "strh r6, [r5, r4]" + - + asm_text: "strh r3, [r8, r11]!" + - + asm_text: "strh r1, [r2, -r1]!" + - + asm_text: "strh r9, [r7], r2" + - + asm_text: "strh r4, [r3], -r2" + - + asm_text: "strht r2, [r5], #0x4c" + - + asm_text: "strht r8, [r1], #-0x19" + - + asm_text: "strht r5, [r3], r4" + - + asm_text: "strht r6, [r8], -r0" + - + asm_text: "ldrd r0, r1, [sp]" + - + asm_text: "strd r0, r1, [sp]" diff --git a/tests/MC/ARM/arm-shift-encoding.s.yaml b/tests/MC/ARM/arm-shift-encoding.s.yaml new file mode 100644 index 0000000000..4258d2f126 --- /dev/null +++ b/tests/MC/ARM/arm-shift-encoding.s.yaml @@ -0,0 +1,106 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x90, 0xe7, 0x20, 0x00, 0x90, 0xe7, 0x20, 0x08, 0x90, 0xe7, 0x00, 0x00, 0x90, 0xe7, 0x00, 0x08, 0x90, 0xe7, 0x40, 0x00, 0x90, 0xe7, 0x40, 0x08, 0x90, 0xe7, 0x60, 0x00, 0x90, 0xe7, 0x60, 0x08, 0x90, 0xe7, 0x00, 0xf0, 0xd0, 0xf7, 0x20, 0xf0, 0xd0, 0xf7, 0x20, 0xf8, 0xd0, 0xf7, 0x00, 0xf0, 0xd0, 0xf7, 0x00, 0xf8, 0xd0, 0xf7, 0x40, 0xf0, 0xd0, 0xf7, 0x40, 0xf8, 0xd0, 0xf7, 0x60, 0xf0, 0xd0, 0xf7, 0x60, 0xf8, 0xd0, 0xf7, 0x00, 0x00, 0x80, 0xe7, 0x20, 0x00, 0x80, 0xe7, 0x20, 0x08, 0x80, 0xe7, 0x00, 0x00, 0x80, 0xe7, 0x00, 0x08, 0x80, 0xe7, 0x40, 0x00, 0x80, 0xe7, 0x40, 0x08, 0x80, 0xe7, 0x60, 0x00, 0x80, 0xe7, 0x60, 0x08, 0x80, 0xe7, 0x62, 0x00, 0x91, 0xe6, 0x05, 0x30, 0x94, 0xe6, 0x08, 0x60, 0x87, 0xe6, 0x0b, 0x90, 0x8a, 0xe6, 0x0f, 0xd0, 0xae, 0xe0, 0x29, 0x10, 0xa8, 0xe0, 0x2f, 0x28, 0xa7, 0xe0, 0x0a, 0x30, 0xa6, 0xe0, 0x0e, 0x48, 0xa5, 0xe0, 0x4b, 0x50, 0xa4, 0xe0, 0x4d, 0x68, 0xa3, 0xe0, 0x6c, 0x70, 0xa2, 0xe0, 0x60, 0x88, 0xa1, 0xe0, 0x0e, 0x00, 0x5d, 0xe1, 0x28, 0x00, 0x51, 0xe1, 0x27, 0x08, 0x52, 0xe1, 0x06, 0x00, 0x53, 0xe1, 0x05, 0x08, 0x54, 0xe1, 0x44, 0x00, 0x55, 0xe1, 0x43, 0x08, 0x56, 0xe1, 0x62, 0x00, 0x57, 0xe1, 0x61, 0x08, 0x58, 0xe1 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "ldr r0, [r0, r0]" + - + asm_text: "ldr r0, [r0, r0, lsr #0x20]" + - + asm_text: "ldr r0, [r0, r0, lsr #0x10]" + - + asm_text: "ldr r0, [r0, r0]" + - + asm_text: "ldr r0, [r0, r0, lsl #0x10]" + - + asm_text: "ldr r0, [r0, r0, asr #0x20]" + - + asm_text: "ldr r0, [r0, r0, asr #0x10]" + - + asm_text: "ldr r0, [r0, r0, rrx]" + - + asm_text: "ldr r0, [r0, r0, ror #0x10]" + - + asm_text: "pld [r0, r0]" + - + asm_text: "pld [r0, r0, lsr #0x20]" + - + asm_text: "pld [r0, r0, lsr #0x10]" + - + asm_text: "pld [r0, r0]" + - + asm_text: "pld [r0, r0, lsl #0x10]" + - + asm_text: "pld [r0, r0, asr #0x20]" + - + asm_text: "pld [r0, r0, asr #0x10]" + - + asm_text: "pld [r0, r0, rrx]" + - + asm_text: "pld [r0, r0, ror #0x10]" + - + asm_text: "str r0, [r0, r0]" + - + asm_text: "str r0, [r0, r0, lsr #0x20]" + - + asm_text: "str r0, [r0, r0, lsr #0x10]" + - + asm_text: "str r0, [r0, r0]" + - + asm_text: "str r0, [r0, r0, lsl #0x10]" + - + asm_text: "str r0, [r0, r0, asr #0x20]" + - + asm_text: "str r0, [r0, r0, asr #0x10]" + - + asm_text: "str r0, [r0, r0, rrx]" + - + asm_text: "str r0, [r0, r0, ror #0x10]" + - + asm_text: "ldr r0, [r1], r2, rrx" + - + asm_text: "ldr r3, [r4], r5" + - + asm_text: "str r6, [r7], r8" + - + asm_text: "str r9, [r10], r11" + - + asm_text: "adc sp, lr, pc" + - + asm_text: "adc r1, r8, r9, lsr #0x20" + - + asm_text: "adc r2, r7, pc, lsr #0x10" + - + asm_text: "adc r3, r6, r10" + - + asm_text: "adc r4, r5, lr, lsl #0x10" + - + asm_text: "adc r5, r4, r11, asr #0x20" + - + asm_text: "adc r6, r3, sp, asr #0x10" + - + asm_text: "adc r7, r2, r12, rrx" + - + asm_text: "adc r8, r1, r0, ror #0x10" + - + asm_text: "cmp sp, lr" + - + asm_text: "cmp r1, r8, lsr #0x20" + - + asm_text: "cmp r2, r7, lsr #0x10" + - + asm_text: "cmp r3, r6" + - + asm_text: "cmp r4, r5, lsl #0x10" + - + asm_text: "cmp r5, r4, asr #0x20" + - + asm_text: "cmp r6, r3, asr #0x10" + - + asm_text: "cmp r7, r2, rrx" + - + asm_text: "cmp r8, r1, ror #0x10" diff --git a/tests/MC/ARM/arm-thumb-trustzone.s.yaml b/tests/MC/ARM/arm-thumb-trustzone.s.yaml new file mode 100644 index 0000000000..5ce7956b28 --- /dev/null +++ b/tests/MC/ARM/arm-thumb-trustzone.s.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0xff, 0xf7, 0x00, 0x80, 0x0c, 0xbf ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "smc #15" + - + asm_text: "ite eq" diff --git a/tests/MC/ARM/arm-trustzone.s.yaml b/tests/MC/ARM/arm-trustzone.s.yaml new file mode 100644 index 0000000000..09f1141323 --- /dev/null +++ b/tests/MC/ARM/arm-trustzone.s.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0x7f, 0x00, 0x60, 0xe1, 0x70, 0x00, 0x60, 0x01 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "smc #15" + - + asm_text: "smceq #0" diff --git a/tests/MC/ARM/arm_addrmode2.s.yaml b/tests/MC/ARM/arm_addrmode2.s.yaml new file mode 100644 index 0000000000..0d55f5526e --- /dev/null +++ b/tests/MC/ARM/arm_addrmode2.s.yaml @@ -0,0 +1,44 @@ +test_cases: + - + input: + bytes: [ 0x02, 0x10, 0xb0, 0xe6, 0xa2, 0x11, 0xb0, 0xe6, 0x04, 0x10, 0xb0, 0xe4, 0x00, 0x10, 0xb0, 0xe4, 0x02, 0x10, 0xf0, 0xe6, 0xa2, 0x11, 0xf0, 0xe6, 0x04, 0x10, 0xf0, 0xe4, 0x00, 0x10, 0xf0, 0xe4, 0x02, 0x10, 0xa0, 0xe6, 0xa2, 0x11, 0xa0, 0xe6, 0x04, 0x10, 0xa0, 0xe4, 0x00, 0x10, 0xa0, 0xe4, 0x02, 0x10, 0xe0, 0xe6, 0xa2, 0x11, 0xe0, 0xe6, 0x04, 0x10, 0xe0, 0xe4, 0x00, 0x10, 0xe0, 0xe4, 0xa2, 0x11, 0xb0, 0xe7, 0xa2, 0x11, 0xf0, 0xe7 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "ldrt r1, [r0], r2" + - + asm_text: "ldrt r1, [r0], r2, lsr #3" + - + asm_text: "ldrt r1, [r0], #4" + - + asm_text: "ldrt r1, [r0], #0" + - + asm_text: "ldrbt r1, [r0], r2" + - + asm_text: "ldrbt r1, [r0], r2, lsr #3" + - + asm_text: "ldrbt r1, [r0], #4" + - + asm_text: "ldrbt r1, [r0], #0" + - + asm_text: "strt r1, [r0], r2" + - + asm_text: "strt r1, [r0], r2, lsr #3" + - + asm_text: "strt r1, [r0], #4" + - + asm_text: "strt r1, [r0], #0" + - + asm_text: "strbt r1, [r0], r2" + - + asm_text: "strbt r1, [r0], r2, lsr #3" + - + asm_text: "strbt r1, [r0], #4" + - + asm_text: "strbt r1, [r0], #0" + - + asm_text: "ldr r1, [r0, r2, lsr #3]!" + - + asm_text: "ldrb r1, [r0, r2, lsr #3]!" diff --git a/tests/MC/ARM/arm_addrmode3.s.yaml b/tests/MC/ARM/arm_addrmode3.s.yaml new file mode 100644 index 0000000000..2a6a95de0e --- /dev/null +++ b/tests/MC/ARM/arm_addrmode3.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0xd2, 0x10, 0xb0, 0xe0, 0xd4, 0x10, 0xf0, 0xe0, 0xf2, 0x10, 0xb0, 0xe0, 0xf4, 0x10, 0xf0, 0xe0, 0xb2, 0x10, 0xb0, 0xe0, 0xb4, 0x10, 0xf0, 0xe0, 0xb2, 0x10, 0xa0, 0xe0, 0xb4, 0x10, 0xe0, 0xe0 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "ldrsbt r1, [r0], r2" + - + asm_text: "ldrsbt r1, [r0], #4" + - + asm_text: "ldrsht r1, [r0], r2" + - + asm_text: "ldrsht r1, [r0], #4" + - + asm_text: "ldrht r1, [r0], r2" + - + asm_text: "ldrht r1, [r0], #4" + - + asm_text: "strht r1, [r0], r2" + - + asm_text: "strht r1, [r0], #4" diff --git a/tests/MC/ARM/arm_instructions.s.yaml b/tests/MC/ARM/arm_instructions.s.yaml new file mode 100644 index 0000000000..72559b88ed --- /dev/null +++ b/tests/MC/ARM/arm_instructions.s.yaml @@ -0,0 +1,52 @@ +test_cases: + - + input: + bytes: [ 0x03, 0x10, 0x02, 0xe0, 0x03, 0x10, 0x12, 0xe0, 0x03, 0x10, 0x22, 0xe0, 0x03, 0x10, 0x32, 0xe0, 0x03, 0x10, 0x42, 0xe0, 0x03, 0x10, 0x52, 0xe0, 0x03, 0x10, 0x82, 0xe0, 0x03, 0x10, 0x92, 0xe0, 0x03, 0x10, 0xa2, 0xe0, 0x03, 0x10, 0xc2, 0xe1, 0x03, 0x10, 0xd2, 0xe1, 0x02, 0x10, 0xa0, 0xe1, 0x02, 0x10, 0xe0, 0xe1, 0x02, 0x10, 0xf0, 0xe1, 0x90, 0x02, 0xcb, 0xe7, 0x7a, 0x00, 0x20, 0xe1, 0x81, 0x17, 0x11, 0xee, 0x81, 0x17, 0x11, 0xfe, 0x13, 0x14, 0x82, 0xe0, 0x30, 0x0f, 0xa6, 0xe6, 0x00, 0x00, 0x0a, 0xf1, 0xb0, 0x30, 0x42, 0xe1 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "and r1, r2, r3" + - + asm_text: "ands r1, r2, r3" + - + asm_text: "eor r1, r2, r3" + - + asm_text: "eors r1, r2, r3" + - + asm_text: "sub r1, r2, r3" + - + asm_text: "subs r1, r2, r3" + - + asm_text: "add r1, r2, r3" + - + asm_text: "adds r1, r2, r3" + - + asm_text: "adc r1, r2, r3" + - + asm_text: "bic r1, r2, r3" + - + asm_text: "bics r1, r2, r3" + - + asm_text: "mov r1, r2" + - + asm_text: "mvn r1, r2" + - + asm_text: "mvns r1, r2" + - + asm_text: "bfi r0, r0, #5, #7" + - + asm_text: "bkpt #0xa" + - + asm_text: "cdp p7, #1, c1, c1, c1, #4" + - + asm_text: "cdp2 p7, #1, c1, c1, c1, #4" + - + asm_text: "add r1, r2, r3, lsl r4" + - + asm_text: "ssat16 r0, #7, r0" + - + asm_text: "cpsie none, #0" + - + asm_text: "strh r3, [r2, #-0]" diff --git a/tests/MC/ARM/armv8.1m-pacbti.s.yaml b/tests/MC/ARM/armv8.1m-pacbti.s.yaml new file mode 100644 index 0000000000..c0b5282082 --- /dev/null +++ b/tests/MC/ARM/armv8.1m-pacbti.s.yaml @@ -0,0 +1,18 @@ +test_cases: + - + input: + bytes: [ 0xaf, 0xf3, 0x2d, 0x80, 0xaf, 0xf3, 0x0f, 0x80, 0xaf, 0xf3, 0x0f, 0x80, 0xaf, 0xf3, 0x1d, 0x80, 0xaf, 0xf3, 0x0d, 0x80 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "aut r12, lr, sp" + - + asm_text: "bti" + - + asm_text: "bti" + - + asm_text: "pac r12, lr, sp" + - + asm_text: "pacbti r12, lr, sp" diff --git a/tests/MC/ARM/armv8.2a-dotprod-a32.s.yaml b/tests/MC/ARM/armv8.2a-dotprod-a32.s.yaml new file mode 100644 index 0000000000..5ae5ce21d8 --- /dev/null +++ b/tests/MC/ARM/armv8.2a-dotprod-a32.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0x12, 0x0d, 0x21, 0xfc, 0x02, 0x0d, 0x21, 0xfc, 0x58, 0x0d, 0x22, 0xfc, 0x48, 0x0d, 0x22, 0xfc, 0x12, 0x0d, 0x21, 0xfe, 0x22, 0x0d, 0x21, 0xfe, 0x54, 0x0d, 0x22, 0xfe, 0x64, 0x0d, 0x22, 0xfe ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vudot.u8 d0, d1, d2" + - + asm_text: "vsdot.s8 d0, d1, d2" + - + asm_text: "vudot.u8 q0, q1, q4" + - + asm_text: "vsdot.s8 q0, q1, q4" + - + asm_text: "vudot.u8 d0, d1, d2[0]" + - + asm_text: "vsdot.s8 d0, d1, d2[1]" + - + asm_text: "vudot.u8 q0, q1, d4[0]" + - + asm_text: "vsdot.s8 q0, q1, d4[1]" diff --git a/tests/MC/ARM/armv8.2a-dotprod-t32.s.yaml b/tests/MC/ARM/armv8.2a-dotprod-t32.s.yaml new file mode 100644 index 0000000000..218c43f676 --- /dev/null +++ b/tests/MC/ARM/armv8.2a-dotprod-t32.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0x21, 0xfc, 0x12, 0x0d, 0x21, 0xfc, 0x02, 0x0d, 0x22, 0xfc, 0x58, 0x0d, 0x22, 0xfc, 0x48, 0x0d, 0x21, 0xfe, 0x12, 0x0d, 0x21, 0xfe, 0x22, 0x0d, 0x22, 0xfe, 0x54, 0x0d, 0x22, 0xfe, 0x64, 0x0d ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vudot.u8 d0, d1, d2" + - + asm_text: "vsdot.s8 d0, d1, d2" + - + asm_text: "vudot.u8 q0, q1, q4" + - + asm_text: "vsdot.s8 q0, q1, q4" + - + asm_text: "vudot.u8 d0, d1, d2[0]" + - + asm_text: "vsdot.s8 d0, d1, d2[1]" + - + asm_text: "vudot.u8 q0, q1, d4[0]" + - + asm_text: "vsdot.s8 q0, q1, d4[1]" diff --git a/tests/MC/ARM/armv8.5a-sb.s.yaml b/tests/MC/ARM/armv8.5a-sb.s.yaml new file mode 100644 index 0000000000..63e3e7151f --- /dev/null +++ b/tests/MC/ARM/armv8.5a-sb.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x70, 0xf0, 0x7f, 0xf5 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "sb" diff --git a/tests/MC/ARM/armv8a-fpmul.s.yaml b/tests/MC/ARM/armv8a-fpmul.s.yaml new file mode 100644 index 0000000000..901d69fa17 --- /dev/null +++ b/tests/MC/ARM/armv8a-fpmul.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0x91, 0x08, 0x20, 0xfc, 0x91, 0x08, 0xa0, 0xfc, 0x52, 0x08, 0x21, 0xfc, 0x52, 0x08, 0xa1, 0xfc, 0x99, 0x08, 0x00, 0xfe, 0x99, 0x08, 0x10, 0xfe, 0x7a, 0x08, 0x01, 0xfe, 0x7a, 0x08, 0x11, 0xfe ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vfmal.f16 d0, s1, s2" + - + asm_text: "vfmsl.f16 d0, s1, s2" + - + asm_text: "vfmal.f16 q0, d1, d2" + - + asm_text: "vfmsl.f16 q0, d1, d2" + - + asm_text: "vfmal.f16 d0, s1, s2[1]" + - + asm_text: "vfmsl.f16 d0, s1, s2[1]" + - + asm_text: "vfmal.f16 q0, d1, d2[3]" + - + asm_text: "vfmsl.f16 q0, d1, d2[3]" diff --git a/tests/MC/ARM/basic-arm-instructions-v8.s.yaml b/tests/MC/ARM/basic-arm-instructions-v8.s.yaml new file mode 100644 index 0000000000..8a92264d61 --- /dev/null +++ b/tests/MC/ARM/basic-arm-instructions-v8.s.yaml @@ -0,0 +1,26 @@ +test_cases: + - + input: + bytes: [ 0x59, 0xf0, 0x7f, 0xf5, 0x51, 0xf0, 0x7f, 0xf5, 0x55, 0xf0, 0x7f, 0xf5, 0x5d, 0xf0, 0x7f, 0xf5, 0x49, 0xf0, 0x7f, 0xf5, 0x41, 0xf0, 0x7f, 0xf5, 0x45, 0xf0, 0x7f, 0xf5, 0x4d, 0xf0, 0x7f, 0xf5, 0x05, 0xf0, 0x20, 0xe3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "dmb ishld" + - + asm_text: "dmb oshld" + - + asm_text: "dmb nshld" + - + asm_text: "dmb ld" + - + asm_text: "dsb ishld" + - + asm_text: "dsb oshld" + - + asm_text: "dsb nshld" + - + asm_text: "dsb ld" + - + asm_text: "sevl" diff --git a/tests/MC/ARM/basic-arm-instructions.s.yaml b/tests/MC/ARM/basic-arm-instructions.s.yaml new file mode 100644 index 0000000000..ed1fbc05ee --- /dev/null +++ b/tests/MC/ARM/basic-arm-instructions.s.yaml @@ -0,0 +1,2616 @@ +test_cases: + - + input: + bytes: [ 0x0f, 0x10, 0xa2, 0xe2, 0x0f, 0x10, 0xa2, 0xe2, 0x0f, 0x10, 0xa2, 0xe2, 0xff, 0x78, 0xa8, 0xe2, 0x2a, 0x71, 0xa8, 0xe2, 0x2a, 0x71, 0xa8, 0xe2, 0x28, 0x71, 0xa8, 0xe2, 0x28, 0x71, 0xa8, 0xe2, 0x28, 0x71, 0xa8, 0xe2, 0x28, 0x71, 0xa8, 0xe2, 0xf0, 0x10, 0xa2, 0xe2, 0x0f, 0x1c, 0xa2, 0xe2, 0x0f, 0x1a, 0xa2, 0xe2, 0x0f, 0x18, 0xa2, 0xe2, 0x0f, 0x16, 0xa2, 0xe2, 0x0f, 0x14, 0xa2, 0xe2, 0x0f, 0x12, 0xa2, 0xe2, 0xff, 0x12, 0xa2, 0xe2, 0x0f, 0x1c, 0xb2, 0xe2, 0x28, 0x71, 0xb8, 0xe2, 0x0f, 0x1c, 0xb2, 0x02, 0x0f, 0x1c, 0xa2, 0x02, 0x06, 0x40, 0xa5, 0xe0, 0x86, 0x40, 0xa5, 0xe0, 0x86, 0x4f, 0xa5, 0xe0, 0xa6, 0x40, 0xa5, 0xe0, 0xa6, 0x4f, 0xa5, 0xe0, 0x26, 0x40, 0xa5, 0xe0, 0xc6, 0x40, 0xa5, 0xe0, 0xc6, 0x4f, 0xa5, 0xe0, 0x46, 0x40, 0xa5, 0xe0, 0xe6, 0x40, 0xa5, 0xe0, 0xe6, 0x4f, 0xa5, 0xe0, 0x18, 0x69, 0xa7, 0xe0, 0x38, 0x69, 0xa7, 0xe0, 0x58, 0x69, 0xa7, 0xe0, 0x78, 0x69, 0xa7, 0xe0, 0x66, 0x40, 0xa5, 0xe0, 0x06, 0x50, 0xa5, 0xe0, 0x85, 0x40, 0xa4, 0xe0, 0x85, 0x4f, 0xa4, 0xe0, 0xa5, 0x40, 0xa4, 0xe0, 0xa5, 0x4f, 0xa4, 0xe0, 0x25, 0x40, 0xa4, 0xe0, 0xc5, 0x40, 0xa4, 0xe0, 0xc5, 0x4f, 0xa4, 0xe0, 0x45, 0x40, 0xa4, 0xe0, 0xe5, 0x40, 0xa4, 0xe0, 0xe5, 0x4f, 0xa4, 0xe0, 0x65, 0x40, 0xa4, 0xe0, 0x17, 0x69, 0xa6, 0xe0, 0x37, 0x69, 0xa6, 0xe0, 0x57, 0x69, 0xa6, 0xe0, 0x77, 0x69, 0xa6, 0xe0, 0x65, 0x40, 0xa4, 0xe0, 0x03, 0x20, 0x8f, 0xe2, 0x03, 0x20, 0x4f, 0xe2, 0x00, 0x10, 0x4f, 0xe2, 0x12, 0x14, 0x4f, 0xe2, 0x06, 0x11, 0x4f, 0xe2, 0x12, 0x14, 0x8f, 0xe2, 0x06, 0x11, 0x8f, 0xe2, 0x0f, 0x4a, 0x85, 0xe2, 0x0f, 0x4a, 0x85, 0xe2, 0x0f, 0x4a, 0x85, 0xe2, 0x0f, 0x4a, 0x45, 0xe2, 0xff, 0x78, 0x88, 0xe2, 0x2a, 0x71, 0x88, 0xe2, 0x2a, 0x71, 0x88, 0xe2, 0x28, 0x71, 0x88, 0xe2, 0x28, 0x71, 0x88, 0xe2, 0x28, 0x71, 0x88, 0xe2, 0x28, 0x71, 0x88, 0xe2, 0x06, 0x40, 0x85, 0xe0, 0x86, 0x42, 0x85, 0xe0, 0xa6, 0x42, 0x85, 0xe0, 0xa6, 0x42, 0x85, 0xe0, 0xc6, 0x42, 0x85, 0xe0, 0xe6, 0x42, 0x85, 0xe0, 0x18, 0x69, 0x87, 0xe0, 0x13, 0x49, 0x84, 0xe0, 0x38, 0x69, 0x87, 0xe0, 0x58, 0x69, 0x87, 0xe0, 0x78, 0x69, 0x87, 0xe0, 0x66, 0x40, 0x85, 0xe0, 0x0f, 0x5a, 0x85, 0xe2, 0x0f, 0x5a, 0x85, 0xe2, 0x0f, 0x5a, 0x85, 0xe2, 0x0f, 0x5a, 0x45, 0xe2, 0xff, 0x78, 0x87, 0xe2, 0x2a, 0x71, 0x87, 0xe2, 0x2a, 0x71, 0x87, 0xe2, 0x28, 0x71, 0x87, 0xe2, 0x28, 0x71, 0x87, 0xe2, 0x28, 0x71, 0x87, 0xe2, 0x28, 0x71, 0x87, 0xe2, 0x05, 0x40, 0x84, 0xe0, 0x85, 0x42, 0x84, 0xe0, 0xa5, 0x42, 0x84, 0xe0, 0xa5, 0x42, 0x84, 0xe0, 0xc5, 0x42, 0x84, 0xe0, 0xe5, 0x42, 0x84, 0xe0, 0x17, 0x69, 0x86, 0xe0, 0x37, 0x69, 0x86, 0xe0, 0x57, 0x69, 0x86, 0xe0, 0x77, 0x69, 0x86, 0xe0, 0x65, 0x40, 0x84, 0xe0, 0x04, 0x00, 0x40, 0xe2, 0x15, 0x40, 0x45, 0xe2, 0x03, 0x01, 0x8f, 0xe2, 0x03, 0x01, 0x9f, 0x02, 0x22, 0x30, 0x81, 0xe0, 0x42, 0x30, 0x81, 0xe0, 0xff, 0x78, 0x98, 0xe2, 0xff, 0x78, 0x98, 0xe2, 0xff, 0x78, 0x98, 0xe2, 0xff, 0x78, 0x98, 0xe2, 0x2a, 0x71, 0x98, 0xe2, 0x2a, 0x71, 0x98, 0xe2, 0x28, 0x71, 0x98, 0xe2, 0x28, 0x71, 0x98, 0xe2, 0x28, 0x71, 0x98, 0xe2, 0x28, 0x71, 0x98, 0xe2, 0x0f, 0xa0, 0x01, 0xe2, 0x0f, 0xa0, 0x01, 0xe2, 0x0f, 0xa0, 0x01, 0xe2, 0x0e, 0xa0, 0xc1, 0xe3, 0xff, 0x78, 0x08, 0xe2, 0x2a, 0x71, 0x08, 0xe2, 0x2a, 0x71, 0x08, 0xe2, 0x28, 0x71, 0x08, 0xe2, 0x28, 0x71, 0x08, 0xe2, 0x28, 0x71, 0x08, 0xe2, 0x28, 0x71, 0x08, 0xe2, 0x06, 0xa0, 0x01, 0xe0, 0x06, 0xa5, 0x01, 0xe0, 0x26, 0xa5, 0x01, 0xe0, 0x26, 0xa5, 0x01, 0xe0, 0x46, 0xa5, 0x01, 0xe0, 0x66, 0xa5, 0x01, 0xe0, 0x18, 0x62, 0x07, 0xe0, 0x38, 0x62, 0x07, 0xe0, 0x58, 0x62, 0x07, 0xe0, 0x78, 0x62, 0x07, 0xe0, 0x66, 0xa0, 0x01, 0xe0, 0x02, 0x21, 0xc3, 0xe3, 0x02, 0xd1, 0xcd, 0xe3, 0x02, 0xf1, 0xcf, 0xe3, 0x0f, 0x10, 0x01, 0xe2, 0x0f, 0x10, 0x01, 0xe2, 0x0f, 0x10, 0x01, 0xe2, 0x0e, 0x10, 0xc1, 0xe3, 0xff, 0x78, 0x07, 0xe2, 0x2a, 0x71, 0x07, 0xe2, 0x2a, 0x71, 0x07, 0xe2, 0x28, 0x71, 0x07, 0xe2, 0x28, 0x71, 0x07, 0xe2, 0x28, 0x71, 0x07, 0xe2, 0x28, 0x71, 0x07, 0xe2, 0x01, 0xa0, 0x0a, 0xe0, 0x01, 0xa5, 0x0a, 0xe0, 0x21, 0xa5, 0x0a, 0xe0, 0x21, 0xa5, 0x0a, 0xe0, 0x41, 0xa5, 0x0a, 0xe0, 0x61, 0xa5, 0x0a, 0xe0, 0x17, 0x62, 0x06, 0xe0, 0x37, 0x62, 0x06, 0xe0, 0x57, 0x62, 0x06, 0xe0, 0x77, 0x62, 0x06, 0xe0, 0x61, 0xa0, 0x0a, 0xe0, 0x22, 0x30, 0x01, 0xe0, 0x42, 0x30, 0x01, 0xe0, 0x44, 0x20, 0xa0, 0xe1, 0x44, 0x21, 0xa0, 0xe1, 0x04, 0x20, 0xa0, 0xe1, 0x44, 0x41, 0xa0, 0xe1, 0x9f, 0x51, 0xd3, 0xe7, 0x9f, 0x51, 0xd3, 0x37, 0x92, 0x51, 0xd3, 0xe7, 0x92, 0x51, 0xd3, 0x17, 0x0f, 0xa0, 0xc1, 0xe3, 0x0f, 0xa0, 0xc1, 0xe3, 0x0f, 0xa0, 0xc1, 0xe3, 0x0e, 0xa0, 0x01, 0xe2, 0xff, 0x78, 0xc8, 0xe3, 0x2a, 0x71, 0xc8, 0xe3, 0x2a, 0x71, 0xc8, 0xe3, 0x28, 0x71, 0xc8, 0xe3, 0x28, 0x71, 0xc8, 0xe3, 0x28, 0x71, 0xc8, 0xe3, 0x06, 0xa0, 0xc1, 0xe1, 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0x71, 0x38, 0xc2, 0xe6, 0x73, 0x1c, 0xc2, 0x06, 0x79, 0x10, 0xf3, 0xe6, 0x76, 0x60, 0xf1, 0x86, 0x73, 0x34, 0xf8, 0xe6, 0x74, 0x28, 0xf2, 0x36, 0x73, 0x9c, 0xf3, 0xe6, 0x74, 0x20, 0xef, 0xa6, 0x76, 0x50, 0xef, 0xe6, 0x79, 0x64, 0xef, 0xe6, 0x71, 0x58, 0xef, 0x36, 0x73, 0x8c, 0xef, 0xe6, 0x74, 0x10, 0xcf, 0xe6, 0x77, 0x60, 0xcf, 0xe6, 0x75, 0x34, 0xcf, 0x26, 0x71, 0x38, 0xcf, 0xe6, 0x73, 0x2c, 0xcf, 0xa6, 0x79, 0x30, 0xff, 0x16, 0x76, 0x10, 0xff, 0xe6, 0x78, 0x34, 0xff, 0xe6, 0x72, 0x28, 0xff, 0xd6, 0x73, 0x9c, 0xff, 0xe6, 0x02, 0xf0, 0x20, 0xe3, 0x02, 0xf0, 0x20, 0x83, 0x03, 0xf0, 0x20, 0xe3, 0x03, 0xf0, 0x20, 0xb3, 0x01, 0xf0, 0x20, 0xe3, 0x01, 0xf0, 0x20, 0x13, 0x04, 0xf0, 0x20, 0xe3, 0x03, 0xf0, 0x20, 0xe3, 0x02, 0xf0, 0x20, 0xe3, 0x01, 0xf0, 0x20, 0xe3, 0x00, 0xf0, 0x20, 0xe3, 0xef, 0xf0, 0x20, 0xc3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "adc r1, r2, #0xf" + - + asm_text: "adc r1, r2, #0xf" + - + asm_text: "adc r1, r2, #0xf" + - + asm_text: "adc r7, r8, #0xff0000" + - + asm_text: "adc r7, r8, #-0x7ffffff6" + - + asm_text: "adc r7, r8, #-0x7ffffff6" + - + asm_text: "adc r7, r8, #0x28, #2" + - + asm_text: "adc r7, r8, #0x28, #2" + - + asm_text: "adc r7, r8, #0x28, #2" + - + asm_text: "adc r7, r8, #0x28, #2" + - + asm_text: "adc r1, r2, #0xf0" + - + asm_text: "adc r1, r2, #0xf00" + - + asm_text: "adc r1, r2, #0xf000" + - + asm_text: "adc r1, r2, #0xf0000" + - + asm_text: "adc r1, r2, #0xf00000" + - + asm_text: "adc r1, r2, #0xf000000" + - + asm_text: "adc r1, r2, #-0x10000000" + - + asm_text: "adc r1, r2, #-0xffffff1" + - + asm_text: "adcs r1, r2, #0xf00" + - + asm_text: "adcs r7, r8, #0x28, #2" + - + asm_text: "adcseq r1, r2, #0xf00" + - + asm_text: "adceq r1, r2, #0xf00" + - + asm_text: "adc r4, r5, r6" + - + asm_text: "adc r4, r5, r6, lsl #1" + - + asm_text: "adc r4, r5, r6, lsl #0x1f" + - + asm_text: "adc r4, r5, r6, lsr #1" + - + asm_text: "adc r4, r5, r6, lsr #0x1f" + - + asm_text: "adc r4, r5, r6, lsr #0x20" + - + asm_text: "adc r4, r5, r6, asr #1" + - + asm_text: "adc r4, r5, r6, asr #0x1f" + - + asm_text: "adc r4, r5, r6, asr #0x20" + - + asm_text: "adc r4, r5, r6, ror #1" + - + asm_text: "adc r4, r5, r6, ror #0x1f" + - + asm_text: "adc r6, r7, r8, lsl r9" + - + asm_text: "adc r6, r7, r8, lsr r9" + - + asm_text: "adc r6, r7, r8, asr r9" + - + asm_text: "adc r6, r7, r8, ror r9" + - + asm_text: "adc r4, r5, r6, rrx" + - + asm_text: "adc r5, r5, r6" + - + asm_text: "adc r4, r4, r5, lsl #1" + - + asm_text: "adc r4, r4, r5, lsl #0x1f" + - + asm_text: "adc r4, r4, r5, lsr #1" + - + asm_text: "adc r4, r4, r5, lsr #0x1f" + - + asm_text: "adc r4, r4, r5, lsr #0x20" + - + asm_text: "adc r4, r4, r5, asr #1" + - + asm_text: "adc r4, r4, r5, asr #0x1f" + - + asm_text: "adc r4, r4, r5, asr #0x20" + - + asm_text: "adc r4, r4, r5, ror #1" + - + asm_text: "adc r4, r4, r5, ror #0x1f" + - + asm_text: "adc r4, r4, r5, rrx" + - + asm_text: "adc r6, r6, r7, lsl r9" + - + asm_text: "adc r6, r6, r7, lsr r9" + - + asm_text: "adc r6, r6, r7, asr r9" + - + asm_text: "adc r6, r6, r7, ror r9" + - + asm_text: "adc r4, r4, r5, rrx" + - + asm_text: "add r2, pc, #3" + - + asm_text: "sub r2, pc, #3" + - + asm_text: "sub r1, pc, #0" + - + asm_text: "sub r1, pc, #301989888" + - + asm_text: "sub r1, pc, #-2147483647" + - + asm_text: "add r1, pc, #301989888" + - + asm_text: "add r1, pc, #-2147483647" + - + asm_text: "add r4, r5, #0xf000" + - + asm_text: "add r4, r5, #0xf000" + - + asm_text: "add r4, r5, #0xf000" + - + asm_text: "sub r4, r5, #0xf000" + - + asm_text: "add r7, r8, #0xff0000" + - + asm_text: "add r7, r8, #-0x7ffffff6" + - + asm_text: "add r7, r8, #-0x7ffffff6" + - + asm_text: "add r7, r8, #0x28, #2" + - + asm_text: "add r7, r8, #0x28, #2" + - + asm_text: "add r7, r8, #0x28, #2" + - + asm_text: "add r7, r8, #0x28, #2" + - + asm_text: "add r4, r5, r6" + - + asm_text: "add r4, r5, r6, lsl #5" + - + asm_text: "add r4, r5, r6, lsr #5" + - + asm_text: "add r4, r5, r6, lsr #5" + - + asm_text: "add r4, r5, r6, asr #5" + - + asm_text: "add r4, r5, r6, ror #5" + - + asm_text: "add r6, r7, r8, lsl r9" + - + asm_text: "add r4, r4, r3, lsl r9" + - + asm_text: "add r6, r7, r8, lsr r9" + - + asm_text: "add r6, r7, r8, asr r9" + - + asm_text: "add r6, r7, r8, ror r9" + - + asm_text: "add r4, r5, r6, rrx" + - + asm_text: "add r5, r5, #0xf000" + - + asm_text: "add r5, r5, #0xf000" + - + asm_text: "add r5, r5, #0xf000" + - + asm_text: "sub r5, r5, #0xf000" + - + asm_text: "add r7, r7, #0xff0000" + - + asm_text: "add r7, r7, #-0x7ffffff6" + - + asm_text: "add r7, r7, #-0x7ffffff6" + - + asm_text: "add r7, r7, #0x28, #2" + - + asm_text: "add r7, r7, #0x28, #2" + - + asm_text: "add r7, r7, #0x28, #2" + - + asm_text: "add r7, r7, #0x28, #2" + - + asm_text: "add r4, r4, r5" + - + asm_text: "add r4, r4, r5, lsl #5" + - + asm_text: "add r4, r4, r5, lsr #5" + - + asm_text: "add r4, r4, r5, lsr #5" + - + asm_text: "add r4, r4, r5, asr #5" + - + asm_text: "add r4, r4, r5, ror #5" + - + asm_text: "add r6, r6, r7, lsl r9" + - + asm_text: "add r6, r6, r7, lsr r9" + - + asm_text: "add r6, r6, r7, asr r9" + - + asm_text: "add r6, r6, r7, ror r9" + - + asm_text: "add r4, r4, r5, rrx" + - + asm_text: "sub r0, r0, #4" + - + asm_text: "sub r4, r5, #0x15" + - + asm_text: "add r0, pc, #-1073741824" + - + asm_text: "addseq r0, pc, #-0x40000000" + - + asm_text: "add r3, r1, r2, lsr #0x20" + - + asm_text: "add r3, r1, r2, asr #0x20" + - + asm_text: "adds r7, r8, #0xff0000" + - + asm_text: "adds r7, r8, #0xff0000" + - + asm_text: "adds r7, r8, #0xff0000" + - + asm_text: "adds r7, r8, #0xff0000" + - + asm_text: "adds r7, r8, #-0x7ffffff6" + - + asm_text: "adds r7, r8, #-0x7ffffff6" + - + asm_text: "adds r7, r8, #0x28, #2" + - + asm_text: "adds r7, r8, #0x28, #2" + - + asm_text: "adds r7, r8, #0x28, #2" + - + asm_text: "adds r7, r8, #0x28, #2" + - + asm_text: "and r10, r1, #0xf" + - + asm_text: "and r10, r1, #0xf" + - + asm_text: "and r10, r1, #0xf" + - + asm_text: "bic r10, r1, #0xe" + - + asm_text: "and r7, r8, #0xff0000" + - + asm_text: "and r7, r8, #-0x7ffffff6" + - + asm_text: "and r7, r8, #-0x7ffffff6" + - + asm_text: "and r7, r8, #0x28, #2" + - + asm_text: "and r7, r8, #0x28, #2" + - + asm_text: "and r7, r8, #0x28, #2" + - + asm_text: "and r7, r8, #0x28, #2" + - + asm_text: "and r10, r1, r6" + - + asm_text: "and r10, r1, r6, lsl #0xa" + - + asm_text: "and r10, r1, r6, lsr #0xa" + - + asm_text: "and r10, r1, r6, lsr #0xa" + - + asm_text: "and r10, r1, r6, asr #0xa" + - + asm_text: "and r10, r1, r6, ror #0xa" + - + asm_text: "and r6, r7, r8, lsl r2" + - + asm_text: "and r6, r7, r8, lsr r2" + - + asm_text: "and r6, r7, r8, asr r2" + - + asm_text: "and r6, r7, r8, ror r2" + - + asm_text: "and r10, r1, r6, rrx" + - + asm_text: "bic r2, r3, #-0x80000000" + - + asm_text: "bic sp, sp, #-0x80000000" + - + asm_text: "bic pc, pc, #-0x80000000" + - + asm_text: "and r1, r1, #0xf" + - + asm_text: "and r1, r1, #0xf" + - + asm_text: "and r1, r1, #0xf" + - + asm_text: "bic r1, r1, #0xe" + - + asm_text: "and r7, r7, #0xff0000" + - + asm_text: "and r7, r7, #-0x7ffffff6" + - + asm_text: "and r7, r7, #-0x7ffffff6" + - + asm_text: "and r7, r7, #0x28, #2" + - + asm_text: "and r7, r7, #0x28, #2" + - + asm_text: "and r7, r7, #0x28, #2" + - + asm_text: "and r7, r7, #0x28, #2" + - + asm_text: "and r10, r10, r1" + - + asm_text: "and r10, r10, r1, lsl #0xa" + - + asm_text: "and r10, r10, r1, lsr #0xa" + - + asm_text: "and r10, r10, r1, lsr #0xa" + - + asm_text: "and r10, r10, r1, asr #0xa" + - + asm_text: "and r10, r10, r1, ror #0xa" + - + asm_text: "and r6, r6, r7, lsl r2" + - + asm_text: "and r6, r6, r7, lsr r2" + - + asm_text: "and r6, r6, r7, asr r2" + - + asm_text: "and r6, r6, r7, ror r2" + - + asm_text: "and r10, r10, r1, rrx" + - + asm_text: "and r3, r1, r2, lsr #0x20" + - + asm_text: "and r3, r1, r2, asr #0x20" + - + asm_text: "asr r2, r4, #0x20" + - + asm_text: "asr r2, r4, #2" + - + asm_text: "mov r2, r4" + - + asm_text: "asr r4, r4, #2" + - + asm_text: "bfc r5, #3, #0x11" + - + asm_text: "bfclo r5, #3, #0x11" + - + asm_text: "bfi r5, r2, #3, #0x11" + - + asm_text: "bfine r5, r2, #3, #0x11" + - + asm_text: "bic r10, r1, #0xf" + - + asm_text: "bic r10, r1, #0xf" + - + asm_text: "bic r10, r1, #0xf" + - + asm_text: "and r10, r1, #0xe" + - + asm_text: "bic r7, r8, #0xff0000" + - + asm_text: "bic r7, r8, #-0x7ffffff6" + - + asm_text: "bic r7, r8, #-0x7ffffff6" + - + asm_text: "bic r7, r8, #0x28, #2" + - + asm_text: "bic r7, r8, #0x28, #2" + - + asm_text: "bic r7, r8, #0x28, #2" + - + asm_text: "bic r10, r1, r6" + - + asm_text: "bic r10, r1, r6, lsl #0xa" + - + asm_text: "bic r10, r1, r6, lsr #0xa" + - + asm_text: "bic r10, r1, r6, lsr #0xa" + - + asm_text: "bic r10, r1, r6, asr #0xa" + - + asm_text: "bic r10, r1, r6, ror #0xa" + - + asm_text: "bic r6, r7, r8, lsl r2" + - + asm_text: "bic r6, r7, r8, lsr r2" + - + asm_text: "bic r6, r7, r8, asr r2" + - + asm_text: "bic r6, r7, r8, ror r2" + - + asm_text: "bic r10, r1, r6, rrx" + - + asm_text: "and r2, r3, #-0x80000000" + - + asm_text: "and sp, sp, #-0x80000000" + - + asm_text: "and pc, pc, #-0x80000000" + - + asm_text: "bic r1, r1, #0xf" + - + asm_text: "bic r1, r1, #0xf" + - + asm_text: "bic r1, r1, #0xf" + - + asm_text: "and r1, r1, #0xe" + - + asm_text: "bic r7, r7, #0xff0000" + - + asm_text: "bic r7, r7, #-0x7ffffff6" + - + asm_text: "bic r7, r7, #-0x7ffffff6" + - + asm_text: "bic r7, r7, #0x28, #2" + - + asm_text: "bic r7, r7, #0x28, #2" + - + asm_text: "bic r7, r7, #0x28, #2" + - + asm_text: "bic r7, r7, #0x28, #2" + - + asm_text: "bic r10, r10, r1" + - + asm_text: "bic r10, r10, r1, lsl #0xa" + - + asm_text: "bic r10, r10, r1, lsr #0xa" + - + asm_text: "bic r10, r10, r1, lsr #0xa" + - + asm_text: "bic r10, r10, r1, asr #0xa" + - + asm_text: "bic r10, r10, r1, ror #0xa" + - + asm_text: "bic r6, r6, r7, lsl r2" + - + asm_text: "bic r6, r6, r7, lsr r2" + - + asm_text: "bic r6, r6, r7, asr r2" + - + asm_text: "bic r6, r6, r7, ror r2" + - + asm_text: "bic r10, r10, r1, rrx" + - + asm_text: "bic r3, r1, r2, lsr #0x20" + - + asm_text: "bic r3, r1, r2, asr #0x20" + - + asm_text: "bkpt #0xa" + - + asm_text: "bkpt #0xffff" + - + asm_text: "blls #0x1b4ec9c" + - + asm_text: "blx #0x1eec280" + - + asm_text: "blx #0xf76140" + - + asm_text: "blx r2" + - + asm_text: "blxne r2" + - + asm_text: "bx r2" + - + asm_text: "bxne r2" + - + asm_text: "bxj r2" + - + asm_text: "bxjne r2" + - + asm_text: "cdp p7, #1, c1, c1, c1, #4" + - + asm_text: "cdp2 p7, #1, c1, c1, c1, #4" + - + asm_text: "cdp2 p12, #0, c6, c12, c0, #7" + - + asm_text: "cdpne p7, #1, c1, c1, c1, #4" + - + asm_text: "clrex" + - + asm_text: "clz r1, r2" + - + asm_text: "clzeq r1, r2" + - + asm_text: "cmn r1, #0xf" + - + asm_text: "cmn r1, #0xf" + - + asm_text: "cmn r1, #0xf" + - + asm_text: "cmp r1, #0xf" + - + asm_text: "cmn r7, #0xff0000" + - + asm_text: "cmn r7, #-0x7ffffff6" + - + asm_text: "cmn r7, #-0x7ffffff6" + - + asm_text: "cmn r7, #0x28, #2" + - + asm_text: "cmn r7, #0x28, #2" + - + asm_text: "cmn r7, #0x28, #2" + - + asm_text: "cmn r7, #0x28, #2" + - + asm_text: "cmn r1, r6" + - + asm_text: "cmn r1, r6, lsl #0xa" + - + asm_text: "cmn r1, r6, lsr #0xa" + - + asm_text: "cmn sp, r6, lsr #0xa" + - + asm_text: "cmn r1, r6, asr #0xa" + - + asm_text: "cmn r1, r6, ror #0xa" + - + asm_text: "cmn r7, r8, lsl r2" + - + asm_text: "cmn sp, r8, lsr r2" + - + asm_text: "cmn r7, r8, asr r2" + - + asm_text: "cmn r7, r8, ror r2" + - + asm_text: "cmn r1, r6, rrx" + - + asm_text: "cmp r1, #0xf" + - + asm_text: "cmp r1, #0xf" + - + asm_text: "cmp r1, #0xf" + - + asm_text: "cmn r1, #0xf" + - + asm_text: "cmp r7, #0xff0000" + - + asm_text: "cmp r7, #-0x7ffffff6" + - + asm_text: "cmp r7, #-0x7ffffff6" + - + asm_text: "cmp r7, #0x28, #2" + - + asm_text: "cmp r7, #0x28, #2" + - + asm_text: "cmp r7, #0x28, #2" + - + asm_text: "cmp r7, #0x28, #2" + - + asm_text: "cmp r1, r6" + - + asm_text: "cmp r1, r6, lsl #0xa" + - + asm_text: "cmp r1, r6, lsr #0xa" + - + asm_text: "cmp sp, r6, lsr #0xa" + - + asm_text: "cmp r1, r6, asr #0xa" + - + asm_text: "cmp r1, r6, ror #0xa" + - + asm_text: "cmp r7, r8, lsl r2" + - + asm_text: "cmp sp, r8, lsr r2" + - + asm_text: "cmp r7, r8, asr r2" + - + asm_text: "cmp r7, r8, ror r2" + - + asm_text: "cmp r1, r6, rrx" + - + asm_text: "cmn r0, #2" + - + asm_text: "cmp lr, #0" + - + asm_text: "cpsie aif" + - + asm_text: "cpsie aif" + - + asm_text: "cps #0xf" + - + asm_text: "cpsid if, #0xa" + - + asm_text: "dbg #0" + - + asm_text: "dbg #5" + - + asm_text: "dbg #0xf" + - + asm_text: "dmb sy" + - + asm_text: "dmb st" + - + asm_text: "dmb #0xd" + - + asm_text: "dmb #0xc" + - + asm_text: "dmb ish" + - + asm_text: "dmb ishst" + - + asm_text: "dmb #0x9" + - + asm_text: "dmb #0x8" + - + asm_text: "dmb nsh" + - + asm_text: "dmb nshst" + - + asm_text: "dmb #0x5" + - + asm_text: "dmb #0x4" + - + asm_text: "dmb osh" + - + asm_text: "dmb oshst" + - + asm_text: "dmb #0x1" + - + asm_text: "dmb #0x0" + - + asm_text: "dmb sy" + - + asm_text: "dmb st" + - + asm_text: "dmb ish" + - + asm_text: "dmb ish" + - + asm_text: "dmb ishst" + - + asm_text: "dmb ishst" + - + asm_text: "dmb nsh" + - + asm_text: "dmb nsh" + - + asm_text: "dmb nshst" + - + asm_text: "dmb nshst" + - + asm_text: "dmb osh" + - + asm_text: "dmb oshst" + - + asm_text: "dmb sy" + - + asm_text: "dsb sy" + - + asm_text: "dsb st" + - + asm_text: "dsb #0xd" + - + asm_text: "dsb #0xc" + - + asm_text: "dsb ish" + - + asm_text: "dsb ishst" + - + asm_text: "dsb #0x9" + - + asm_text: "dsb #0x8" + - + asm_text: "dsb nsh" + - + asm_text: "dsb nshst" + - + asm_text: "dsb #0x5" + - + asm_text: "pssbb" + - + asm_text: "dsb osh" + - + asm_text: "dsb oshst" + - + asm_text: "dsb #0x1" + - + asm_text: "ssbb" + - + asm_text: "dsb #0x8" + - + asm_text: "dsb nsh" + - + asm_text: "dsb sy" + - + asm_text: "dsb st" + - + asm_text: "dsb ish" + - + asm_text: "dsb ish" + - + asm_text: "dsb ishst" + - + asm_text: "dsb ishst" + - + asm_text: "dsb nsh" + - + asm_text: "dsb nsh" + - + asm_text: "dsb nshst" + - + asm_text: "dsb nshst" + - + asm_text: "dsb osh" + - + asm_text: "dsb oshst" + - + asm_text: "dsb sy" + - + asm_text: "dsb sy" + - + asm_text: "dsb oshst" + - + asm_text: "eor r4, r5, #0xf000" + - + asm_text: "eor r4, r5, #0xf000" + - + asm_text: "eor r4, r5, #0xf000" + - + asm_text: "eor r7, r8, #0xff0000" + - + asm_text: "eor r7, r8, #-0x7ffffff6" + - + asm_text: "eor r7, r8, #-0x7ffffff6" + - + asm_text: "eor r7, r8, #0x28, #2" + - + asm_text: "eor r7, r8, #0x28, #2" + - + asm_text: "eor r7, r8, #0x28, #2" + - + asm_text: "eor r7, r8, #0x28, #2" + - + asm_text: "eor r4, r5, r6" + - + asm_text: "eor r4, r5, r6, lsl #5" + - + asm_text: "eor r4, r5, r6, lsr #5" + - + asm_text: "eor r4, r5, r6, lsr #5" + - + asm_text: "eor r4, r5, r6, asr #5" + - + asm_text: "eor r4, r5, r6, ror #5" + - + asm_text: "eor r6, r7, r8, lsl r9" + - + asm_text: "eor r6, r7, r8, lsr r9" + - + asm_text: "eor r6, r7, r8, asr r9" + - + asm_text: "eor r6, r7, r8, ror r9" + - + asm_text: "eor r4, r5, r6, rrx" + - + asm_text: "eor r5, r5, #0xf000" + - + asm_text: "eor r5, r5, #0xf000" + - + asm_text: "eor r5, r5, #0xf000" + - + asm_text: "eor r7, r7, #0xff0000" + - + asm_text: "eor r7, r7, #-0x7ffffff6" + - + asm_text: "eor r7, r7, #-0x7ffffff6" + - + asm_text: "eor r7, r7, #0x28, #2" + - + asm_text: "eor r7, r7, #0x28, #2" + - + asm_text: "eor r7, r7, #0x28, #2" + - + asm_text: "eor r7, r7, #0x28, #2" + - + asm_text: "eor r4, r4, r5" + - + asm_text: "eor r4, r4, r5, lsl #5" + - + asm_text: "eor r4, r4, r5, lsr #5" + - + asm_text: "eor r4, r4, r5, lsr #5" + - + asm_text: "eor r4, r4, r5, asr #5" + - + asm_text: "eor r4, r4, r5, ror #5" + - + asm_text: "eor r6, r6, r7, lsl r9" + - + asm_text: "eor r6, r6, r7, lsr r9" + - + asm_text: "eor r6, r6, r7, asr r9" + - + asm_text: "eor r6, r6, r7, ror r9" + - + asm_text: "eor r4, r4, r5, rrx" + - + asm_text: "eor r3, r1, r2, lsr #0x20" + - + asm_text: "eor r3, r1, r2, asr #0x20" + - + asm_text: "isb sy" + - + asm_text: "isb sy" + - + asm_text: "isb sy" + - + asm_text: "isb #0x1" + - + asm_text: "ldc2 p0, c8, [r1, #4]" + - + asm_text: "ldc2 p1, c7, [r2]" + - + asm_text: "ldc2 p2, c6, [r3, #-0xe0]" + - + asm_text: "ldc2 p3, c5, [r4, #-0x78]!" + - + asm_text: "ldc2 p4, c4, [r5], #0x10" + - + asm_text: "ldc2 p5, c3, [r6], #-0x48" + - + asm_text: "ldc2l p6, c2, [r7, #4]" + - + asm_text: "ldc2l p7, c1, [r8]" + - + asm_text: "ldc2l p8, c0, [r9, #-0xe0]" + - + asm_text: "ldc2l p9, c1, [r10, #-0x78]!" + - + asm_text: "ldc2l p0, c2, [r11], #0x10" + - + asm_text: "ldc2l p1, c3, [r12], #-0x48" + - + asm_text: "ldc p12, c4, [r0, #4]" + - + asm_text: "ldc p13, c5, [r1]" + - + asm_text: "ldc p14, c6, [r2, #-0xe0]" + - + asm_text: "ldc p15, c7, [r3, #-0x78]!" + - + asm_text: "ldc p5, c8, [r4], #0x10" + - + asm_text: "ldc p4, c9, [r5], #-0x48" + - + asm_text: "ldcl p3, c10, [r6, #4]" + - + asm_text: "ldcl p2, c11, [r7]" + - + asm_text: "ldcl p1, c12, [r8, #-0xe0]" + - + asm_text: "ldcl p0, c13, [r9, #-0x78]!" + - + asm_text: "ldcl p6, c14, [r10], #0x10" + - + asm_text: "ldcl p7, c15, [r11], #-0x48" + - + asm_text: "ldclo p12, c4, [r0, #4]" + - + asm_text: "ldchi p13, c5, [r1]" + - + asm_text: "ldchs p14, c6, [r2, #-0xe0]" + - + asm_text: "ldclo p15, c7, [r3, #-0x78]!" + - + asm_text: "ldceq p5, c8, [r4], #0x10" + - + asm_text: "ldcgt p4, c9, [r5], #-0x48" + - + asm_text: "ldcllt p3, c10, [r6, #4]" + - + asm_text: "ldclge p2, c11, [r7]" + - + asm_text: "ldclle p1, c12, [r8, #-0xe0]" + - + asm_text: "ldclne p0, c13, [r9, #-0x78]!" + - + asm_text: "ldcleq p6, c14, [r10], #0x10" + - + asm_text: "ldclhi p7, c15, [r11], #-0x48" + - + asm_text: "ldc2 p2, c8, [r1], {25}" + - + asm_text: "ldm r2, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldm r2, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldmib r2, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldmda r2, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldmdb r2, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldm r2, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldm r2!, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldmib r2!, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldmda r2!, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldmdb r2!, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "ldm r0, {r0, r2, lr} ^" + - + asm_text: "ldm sp!, {r0, r1, r2, r3, pc} ^" + - + asm_text: "ldrexb r3, [r4]" + - + asm_text: "ldrexh r2, [r5]" + - + asm_text: "ldrex r1, [r7]" + - + asm_text: "ldrexd r6, r7, [r8]" + - + asm_text: "ldrhthi r8, [r11], #-0" + - + asm_text: "ldrhthi r8, [r11], #0" + - + asm_text: "lsl r2, r4, #0x1f" + - + asm_text: "lsl r2, r4, #1" + - + asm_text: "mov r2, r4" + - + asm_text: "lsl r4, r4, #1" + - + asm_text: "lsr r2, r4, #0x20" + - + asm_text: "lsr r2, r4, #2" + - + asm_text: "mov r2, r4" + - + asm_text: "lsr r4, r4, #2" + - + asm_text: "mcr p7, #1, r5, c1, c1, #4" + - + asm_text: "mcr2 p7, #1, r5, c1, c1, #4" + - + asm_text: "mcr p7, #1, r5, c1, c1, #4" + - + asm_text: "mcr2 p7, #1, r5, c1, c1, #4" + - + asm_text: "mcrls p7, #1, r5, c1, c1, #4" + - + asm_text: "mcrls p7, #1, r5, c1, c1, #4" + - + asm_text: "mcrr p7, #0xf, r5, r4, c1" + - + asm_text: "mcrr2 p7, #0xf, r5, r4, c1" + - + asm_text: "mcrr p7, #0xf, r5, r4, c1" + - + asm_text: "mcrr2 p7, #0xf, r5, r4, c1" + - + asm_text: "mcrrgt p7, #0xf, r5, r4, c1" + - + asm_text: "mcrrgt p7, #0xf, r5, r4, c1" + - + asm_text: "mla r1, r2, r3, r4" + - + asm_text: "mlas r1, r2, r3, r4" + - + asm_text: "mlane r1, r2, r3, r4" + - + asm_text: "mlasne r1, r2, r3, r4" + - + asm_text: "mls r2, r5, r6, r3" + - + asm_text: "mlsne r2, r5, r6, r3" + - + asm_text: "mov r3, #7" + - + asm_text: "mov r3, #7" + - + asm_text: "mov r3, #7" + - + asm_text: "mvn r3, #6" + - + asm_text: "mov r4, #0xff0" + - + asm_text: "mov r5, #0xff0000" + - + asm_text: "mov r7, #0x2a" + - + asm_text: "mov r7, #0xa800000" + - + asm_text: "mov r7, #0xff0000" + - + asm_text: "mov r7, #-0x7ffffff6" + - + asm_text: "mov r7, #-0x7ffffff6" + - + asm_text: "mov pc, #0x8000000a" + - + asm_text: "mov r7, #0, #2" + - + asm_text: "mov r7, #0x28, #2" + - + asm_text: "mov r7, #0x28, #2" + - + asm_text: "mov r7, #0x28, #2" + - + asm_text: "mov r7, #0x28, #2" + - + asm_text: "mov r7, #0x2a, #0x1e" + - + asm_text: "movw r6, #0xffff" + - + asm_text: "movw r9, #0xffff" + - + asm_text: "movs r3, #7" + - + asm_text: "moveq r4, #0xff0" + - + asm_text: "movseq r5, #0xff0000" + - + asm_text: "mov r2, r3" + - + asm_text: "movs r2, r3" + - + asm_text: "moveq r2, r3" + - + asm_text: "movseq r2, r3" + - + asm_text: "mov r12, r8" + - + asm_text: "mov r2, r3" + - + asm_text: "mov r12, r8" + - + asm_text: "mov r2, r3" + - + asm_text: "mov r12, r8" + - + asm_text: "mov r2, r3" + - + asm_text: "mov r12, r8" + - + asm_text: "mov r2, r3" + - + asm_text: "movt r3, #7" + - + asm_text: "movt r6, #0xffff" + - + asm_text: "movteq r4, #0xff0" + - + asm_text: "mrc p14, #0, r1, c1, c2, #4" + - + asm_text: "mrc p15, #7, apsr_nzcv, c15, c6, #6" + - + asm_text: "mrc2 p14, #0, r1, c1, c2, #4" + - + asm_text: "mrc2 p9, #7, apsr_nzcv, c15, c0, #1" + - + asm_text: "mrc p14, #0, r1, c1, c2, #4" + - + asm_text: "mrc p15, #7, apsr_nzcv, c15, c6, #6" + - + asm_text: "mrc2 p14, #0, r1, c1, c2, #4" + - + asm_text: "mrc2 p9, #7, apsr_nzcv, c15, c0, #1" + - + asm_text: "mrceq p15, #7, apsr_nzcv, c15, c6, #6" + - + asm_text: "mrceq p15, #7, apsr_nzcv, c15, c6, #6" + - + asm_text: "mrrc p7, #1, r5, r4, c1" + - + asm_text: "mrrc2 p7, #1, r5, r4, c1" + - + asm_text: "mrrc p7, #1, r5, r4, c1" + - + asm_text: "mrrc2 p7, #1, r5, r4, c1" + - + asm_text: "mrrclo p7, #1, r5, r4, c1" + - + asm_text: "mrrclo p7, #1, r5, r4, c1" + - + asm_text: "mrs r8, apsr" + - + asm_text: "mrs r8, apsr" + - + asm_text: "mrs r8, spsr" + - + asm_text: "msr apsr_nzcvq, #5" + - + asm_text: "msr apsr_nzcvq, #5" + - + asm_text: "msr apsr_nzcvq, #5" + - + asm_text: "msr apsr_g, #5" + - + asm_text: "msr apsr_nzcvq, #5" + - + asm_text: "msr apsr_nzcvq, #5" + - + asm_text: "msr apsr_nzcvqg, #5" + - + asm_text: "msr cpsr_fc, #5" + - + asm_text: "msr cpsr_c, #5" + - + asm_text: "msr cpsr_x, #5" + - + asm_text: "msr cpsr_fc, #5" + - + asm_text: "msr cpsr_fc, #5" + - + asm_text: "msr cpsr_fsx, #5" + - + asm_text: "msr spsr_fc, #5" + - + asm_text: "msr spsr_fsxc, #5" + - + asm_text: "msr cpsr_fsxc, #5" + - + asm_text: "msr apsr_nzcvqg, #0xff0000" + - + asm_text: "msr apsr_nzcvq, #0x8000000a" + - + asm_text: "msr apsr_nzcvqg, #0x8000000a" + - + asm_text: "msr spsr_fsxc, #0x28, #2" + - + asm_text: "msr spsr_fsxc, #0x28, #2" + - + asm_text: "msr spsr_fsxc, #0x28, #2" + - + asm_text: "msr spsr_fsxc, #0x28, #2" + - + asm_text: "msr apsr_nzcvq, r0" + - + asm_text: "msr apsr_g, r0" + - + asm_text: "msr apsr_nzcvq, r0" + - + asm_text: "msr apsr_nzcvq, r0" + - + asm_text: "msr apsr_nzcvqg, r0" + - + asm_text: "msr cpsr_fc, r0" + - + asm_text: "msr cpsr_c, r0" + - + asm_text: "msr cpsr_x, r0" + - + asm_text: "msr cpsr_fc, r0" + - + asm_text: "msr cpsr_fc, r0" + - + asm_text: "msr cpsr_fsx, r0" + - + asm_text: "msr spsr_fc, r0" + - + asm_text: "msr spsr_fsxc, r0" + - + asm_text: "msr cpsr_fsxc, r0" + - + asm_text: "mul r5, r6, r7" + - + asm_text: "muls r5, r6, r7" + - + asm_text: "mulgt r5, r6, r7" + - + asm_text: "mulsle r5, r6, r7" + - + asm_text: "mvn r3, #7" + - + asm_text: "mvn r3, #7" + - + asm_text: "mvn r3, #7" + - + asm_text: "mov r3, #6" + - + asm_text: "mvn r7, #0xff" + - + asm_text: "mvn r4, #0xff0" + - + asm_text: "mvn r5, #0xff0000" + - + asm_text: "mvn r7, #0xff0000" + - + asm_text: "mvn r7, #-0x7ffffff6" + - + asm_text: "mvn r7, #-0x7ffffff6" + - + asm_text: "mvn r7, #0x28, #2" + - + asm_text: "mvn r7, #0x28, #2" + - + asm_text: "mvn r7, #0x28, #2" + - + asm_text: "mvn r7, #0x28, #2" + - + asm_text: "mvns r3, #7" + - + asm_text: "mvneq r4, #0xff0" + - + asm_text: "mvnseq r5, #0xff0000" + - + asm_text: "mvn r2, r3" + - + asm_text: "mvns r2, r3" + - + asm_text: "mvn r5, r6, lsl #0x13" + - + asm_text: "mvn r5, r6, lsr #0x9" + - + asm_text: "mvn r5, r6, asr #4" + - + asm_text: "mvn r5, r6, ror #6" + - + asm_text: "mvn r5, r6, rrx" + - + asm_text: "mvneq r2, r3" + - + asm_text: "mvnseq r2, r3, lsl #0xa" + - + asm_text: "mvn r5, r6, lsl r7" + - + asm_text: "mvns r5, r6, lsr r7" + - + asm_text: "mvngt r5, r6, asr r7" + - + asm_text: "mvnslt r5, r6, ror r7" + - + asm_text: "rsb r5, r8, #0" + - + asm_text: "nop" + - + asm_text: "nop" + - + asm_text: "nopgt" + - + asm_text: "orr r4, r5, #0xf000" + - + asm_text: "orr r4, r5, #0xf000" + - + asm_text: "orr r4, r5, #0xf000" + - + asm_text: "orr r7, r8, #0xff0000" + - + asm_text: "orr r7, r8, #-0x7ffffff6" + - + asm_text: "orr r7, r8, #-0x7ffffff6" + - + asm_text: "orr r7, r8, #0x28, #2" + - + asm_text: "orr r7, r8, #0x28, #2" + - + asm_text: "orr r7, r8, #0x28, #2" + - + asm_text: "orr r7, r8, #0x28, #2" + - + asm_text: "orr r4, r5, r6" + - + asm_text: "orr r4, r5, r6, lsl #5" + - + asm_text: "orr r4, r5, r6, lsr #5" + - + asm_text: "orr r4, r5, r6, lsr #5" + - + asm_text: "orr r4, r5, r6, asr #5" + - + asm_text: "orr r4, r5, r6, ror #5" + - + asm_text: "orr r6, r7, r8, lsl r9" + - + asm_text: "orr r6, r7, r8, lsr r9" + - + asm_text: "orr r6, r7, r8, asr r9" + - + asm_text: "orr r6, r7, r8, ror r9" + - + asm_text: "orr r4, r5, r6, rrx" + - + asm_text: "orr r5, r5, #0xf000" + - + asm_text: "orr r5, r5, #0xf000" + - + asm_text: "orr r5, r5, #0xf000" + - + asm_text: "orr r7, r7, #0xff0000" + - + asm_text: "orr r7, r7, #-0x7ffffff6" + - + asm_text: "orr r7, r7, #-0x7ffffff6" + - + asm_text: "orr r7, r7, #0x28, #2" + - + asm_text: "orr r7, r7, #0x28, #2" + - + asm_text: "orr r7, r7, #0x28, #2" + - + asm_text: "orr r7, r7, #0x28, #2" + - + asm_text: "orr r4, r4, r5" + - + asm_text: "orr r4, r4, r5, lsl #5" + - + asm_text: "orr r4, r4, r5, lsr #5" + - + asm_text: "orr r4, r4, r5, lsr #5" + - + asm_text: "orr r4, r4, r5, asr #5" + - + asm_text: "orr r4, r4, r5, ror #5" + - + asm_text: "orr r6, r6, r7, lsl r9" + - + asm_text: "orr r6, r6, r7, lsr r9" + - + asm_text: "orr r6, r6, r7, asr r9" + - + asm_text: "orr r6, r6, r7, ror r9" + - + asm_text: "orr r4, r4, r5, rrx" + - + asm_text: "orrseq r4, r5, #0xf000" + - + asm_text: "orrne r4, r5, r6" + - + asm_text: "orrseq r4, r5, r6, lsl #5" + - + asm_text: "orrlo r6, r7, r8, ror r9" + - + asm_text: "orrshi r4, r5, r6, rrx" + - + asm_text: "orrhs r5, r5, #0xf000" + - + asm_text: "orrseq r4, r4, r5" + - + asm_text: "orrne r6, r6, r7, asr r9" + - + asm_text: "orrslt r6, r6, r7, ror r9" + - + asm_text: "orrsgt r4, r4, r5, rrx" + - + asm_text: "orr r3, r1, r2, lsr #0x20" + - + asm_text: "orr r3, r1, r2, asr #0x20" + - + asm_text: "pkhbt r2, r2, r3" + - + asm_text: "pkhbt r2, r2, r3, lsl #0x1f" + - + asm_text: "pkhbt r2, r2, r3" + - + asm_text: "pkhbt r2, r2, r3, lsl #0xf" + - + asm_text: "pkhbt r2, r3, r2" + - + asm_text: "pkhtb r2, r2, r3, asr #0x1f" + - + asm_text: "pkhtb r2, r2, r3, asr #0xf" + - + asm_text: "pop {r7}" + - + asm_text: "pop {r7, r8, r9, r10}" + - + asm_text: "str r7, [sp, #-0x4]!" + - + asm_text: "push {r7, r8, r9, r10}" + - + asm_text: "qadd r1, r2, r3" + - + asm_text: "qaddne r1, r2, r3" + - + asm_text: "qadd16 r1, r2, r3" + - + asm_text: "qadd16gt r1, r2, r3" + - + asm_text: "qadd8 r1, r2, r3" + - + asm_text: "qadd8le r1, r2, r3" + - + asm_text: "qdadd r6, r7, r8" + - + asm_text: "qdaddhi r6, r7, r8" + - + asm_text: "qdsub r6, r7, r8" + - + asm_text: "qdsubhi r6, r7, r8" + - + asm_text: "qsax r9, r12, r0" + - + asm_text: "qsaxeq r9, r12, r0" + - + asm_text: "qsub r1, r2, r3" + - + asm_text: "qsubne r1, r2, r3" + - + asm_text: "qsub16 r1, r2, r3" + - + asm_text: "qsub16gt r1, r2, r3" + - + asm_text: "qsub8 r1, r2, r3" + - + asm_text: "qsub8le r1, r2, r3" + - + asm_text: "rbit r1, r2" + - + asm_text: "rbitne r1, r2" + - + asm_text: "rev r1, r9" + - + asm_text: "revne r1, r5" + - + asm_text: "rev16 r8, r3" + - + asm_text: "rev16ne r12, r4" + - + asm_text: "revsh r4, r9" + - + asm_text: "revshne r9, r1" + - + asm_text: "rfeda r2" + - + asm_text: "rfedb r3" + - + asm_text: "rfeia r5" + - + asm_text: "rfeib r6" + - + asm_text: "rfeda r4!" + - + asm_text: "rfedb r7!" + - + asm_text: "rfeia r9!" + - + asm_text: "rfeib r8!" + - + asm_text: "rfeda r2" + - + asm_text: "rfedb r3" + - + asm_text: "rfeia r5" + - + asm_text: "rfeib r6" + - + asm_text: "rfeda r4!" + - + asm_text: "rfedb r7!" + - + asm_text: "rfeia r9!" + - + asm_text: "rfeib r8!" + - + asm_text: "rfeia r1" + - + asm_text: "rfeia r1!" + - + asm_text: "ror r2, r4, #0x1f" + - + asm_text: "ror r2, r4, #1" + - + asm_text: "mov r2, r4" + - + asm_text: "ror r4, r4, #1" + - + asm_text: "rsb r4, r5, #0xf000" + - + asm_text: "rsb r4, r5, #0xf000" + - + asm_text: "rsb r4, r5, #0xf000" + - + asm_text: "rsb r7, r8, #0xff0000" + - + asm_text: "rsb r7, r8, #-0x7ffffff6" + - + asm_text: "rsb r7, r8, #-0x7ffffff6" + - + asm_text: "rsb r7, r8, #0x28, #2" + - + asm_text: "rsb r7, r8, #0x28, #2" + - + asm_text: "rsb r7, r8, #0x28, #2" + - + asm_text: "rsb r7, r8, #0x28, #2" + - + asm_text: "rsb r4, r5, r6" + - + asm_text: "rsb r4, r5, r6, lsl #5" + - + asm_text: "rsblo r4, r5, r6, lsr #5" + - + asm_text: "rsb r4, r5, r6, lsr #5" + - + asm_text: "rsb r4, r5, r6, asr #5" + - + asm_text: "rsb r4, r5, r6, ror #5" + - + asm_text: "rsb r6, r7, r8, lsl r9" + - + asm_text: "rsb r6, r7, r8, lsr r9" + - + asm_text: "rsb r6, r7, r8, asr r9" + - + asm_text: "rsble r6, r7, r8, ror r9" + - + asm_text: "rsb r4, r5, r6, rrx" + - + asm_text: "rsb r5, r5, #0xf000" + - + asm_text: "rsb r5, r5, #0xf000" + - + asm_text: "rsb r5, r5, #0xf000" + - + asm_text: "rsb r7, r7, #0xff0000" + - + asm_text: "rsb r7, r7, #-0x7ffffff6" + - + asm_text: "rsb r7, r7, #-0x7ffffff6" + - + asm_text: "rsb r7, r7, #0x28, #2" + - + asm_text: "rsb r7, r7, #0x28, #2" + - + asm_text: "rsb r7, r7, #0x28, #2" + - + asm_text: "rsb r7, r7, #0x28, #2" + - + asm_text: "rsb r4, r4, r5" + - + asm_text: "rsb r4, r4, r5, lsl #5" + - + asm_text: "rsb r4, r4, r5, lsr #5" + - + asm_text: "rsbne r4, r4, r5, lsr #5" + - + asm_text: "rsb r4, r4, r5, asr #5" + - + asm_text: "rsb r4, r4, r5, ror #5" + - + asm_text: "rsbgt r6, r6, r7, lsl r9" + - + asm_text: "rsb r6, r6, r7, lsr r9" + - + asm_text: "rsb r6, r6, r7, asr r9" + - + asm_text: "rsb r6, r6, r7, ror r9" + - + asm_text: "rsb r4, r4, r5, rrx" + - + asm_text: "rsbs r7, r7, #0xff0000" + - + asm_text: "rsbs r7, r7, #0xff0000" + - + asm_text: "rsbs r7, r7, #0xff0000" + - + asm_text: "rsbs r7, r7, #0xff0000" + - + asm_text: "rsbs r7, r8, #-0x7ffffff6" + - + asm_text: "rsbs r7, r8, #-0x7ffffff6" + - + asm_text: "rsbs r7, r8, #0x28, #2" + - + asm_text: "rsbs r7, r8, #0x28, #2" + - + asm_text: "rsbs r7, r8, #0x28, #2" + - + asm_text: "rsbs r7, r8, #0x28, #2" + - + asm_text: "rsc r4, r5, #0xf000" + - + asm_text: "rsc r4, r5, #0xf000" + - + asm_text: "rsc r4, r5, #0xf000" + - + asm_text: "rsc r7, r8, #0xff0000" + - + asm_text: "rsc r7, r8, #-0x7ffffff6" + - + asm_text: "rsc r7, r8, #-0x7ffffff6" + - + asm_text: "rsc r7, r8, #0x28, #2" + - + asm_text: "rsc r7, r8, #0x28, #2" + - + asm_text: "rsc r7, r8, #0x28, #2" + - + asm_text: "rsc r7, r8, #0x28, #2" + - + asm_text: "rsc r4, r5, r6" + - + asm_text: "rsc r4, r5, r6, lsl #5" + - + asm_text: "rsclo r4, r5, r6, lsr #5" + - + asm_text: "rsc r4, r5, r6, lsr #5" + - + asm_text: "rsc r4, r5, r6, asr #5" + - + asm_text: "rsc r4, r5, r6, ror #5" + - + asm_text: "rsc r6, r7, r8, lsl r9" + - + asm_text: "rsc r6, r7, r8, lsr r9" + - + asm_text: "rsc r6, r7, r8, asr r9" + - + asm_text: "rscle r6, r7, r8, ror r9" + - + asm_text: "rscs r1, r8, #0xfe0" + - + asm_text: "rsc r5, r5, #0xf000" + - + asm_text: "rsc r5, r5, #0xf000" + - + asm_text: "rsc r5, r5, #0xf000" + - + asm_text: "rsc r7, r7, #0xff0000" + - + asm_text: "rsc r7, r7, #-0x7ffffff6" + - + asm_text: "rsc r7, r7, #-0x7ffffff6" + - + asm_text: "rsc r7, r7, #0x28, #2" + - + asm_text: "rsc r7, r7, #0x28, #2" + - + asm_text: "rsc r7, r7, #0x28, #2" + - + asm_text: "rsc r7, r7, #0x28, #2" + - + asm_text: "rsc r4, r4, r5" + - + asm_text: "rsc r4, r4, r5, lsl #5" + - + asm_text: "rsc r4, r4, r5, lsr #5" + - + asm_text: "rscne r4, r4, r5, lsr #5" + - + asm_text: "rsc r4, r4, r5, asr #5" + - + asm_text: "rsc r4, r4, r5, ror #5" + - + asm_text: "rscgt r6, r6, r7, lsl r9" + - + asm_text: "rsc r6, r6, r7, lsr r9" + - + asm_text: "rsc r6, r6, r7, asr r9" + - + asm_text: "rsc r6, r6, r7, ror r9" + - + asm_text: "rrx r0, r1" + - + asm_text: "rrx sp, pc" + - + asm_text: "rrx pc, lr" + - + asm_text: "rrx lr, sp" + - + asm_text: "rrxs r0, r1" + - + asm_text: "rrxs sp, pc" + - + asm_text: "rrxs pc, lr" + - + asm_text: "rrxs lr, sp" + - + asm_text: "sadd16 r1, r2, r3" + - + asm_text: "sadd16gt r1, r2, r3" + - + asm_text: "sadd8 r1, r2, r3" + - + asm_text: "sadd8le r1, r2, r3" + - + asm_text: "sasx r9, r12, r0" + - + asm_text: "sasxeq r9, r12, r0" + - + asm_text: "sbc r4, r5, #0xf000" + - + asm_text: "sbc r4, r5, #0xf000" + - + asm_text: "sbc r4, r5, #0xf000" + - + asm_text: "sbc r7, r8, #0xff0000" + - + asm_text: "sbc r7, r8, #-0x7ffffff6" + - + asm_text: "sbc r7, r8, #-0x7ffffff6" + - + asm_text: "sbc r7, r8, #0x28, #2" + - + asm_text: "sbc r7, r8, #0x28, #2" + - + asm_text: "sbc r7, r8, #0x28, #2" + - + asm_text: "sbc r7, r8, #0x28, #2" + - + asm_text: "sbc r4, r5, r6" + - + asm_text: "sbc r4, r5, r6, lsl #5" + - + asm_text: "sbc r4, r5, r6, lsr #5" + - + asm_text: "sbc r4, r5, r6, lsr #5" + - + asm_text: "sbc r4, r5, r6, asr #5" + - + asm_text: "sbc r4, r5, r6, ror #5" + - + asm_text: "sbc r6, r7, r8, lsl r9" + - + asm_text: "sbc r6, r7, r8, lsr r9" + - + asm_text: "sbc r6, r7, r8, asr r9" + - + asm_text: "sbc r6, r7, r8, ror r9" + - + asm_text: "sbc r5, r5, #0xf000" + - + asm_text: "sbc r5, r5, #0xf000" + - + asm_text: "sbc r5, r5, #0xf000" + - + asm_text: "sbc r7, r7, #0xff0000" + - + asm_text: "sbc r7, r7, #-0x7ffffff6" + - + asm_text: "sbc r7, r7, #-0x7ffffff6" + - + asm_text: "sbc r7, r7, #0x28, #2" + - + asm_text: "sbc r7, r7, #0x28, #2" + - + asm_text: "sbc r7, r7, #0x28, #2" + - + asm_text: "sbc r7, r7, #0x28, #2" + - + asm_text: "sbc r4, r4, r5" + - + asm_text: "sbc r4, r4, r5, lsl #5" + - + asm_text: "sbc r4, r4, r5, lsr #5" + - + asm_text: "sbc r4, r4, r5, lsr #5" + - + asm_text: "sbc r4, r4, r5, asr #5" + - + asm_text: "sbc r4, r4, r5, ror #5" + - + asm_text: "sbc r6, r6, r7, lsl r9" + - + asm_text: "sbc r6, r6, r7, lsr r9" + - + asm_text: "sbc r6, r6, r7, asr r9" + - + asm_text: "sbc r6, r6, r7, ror r9" + - + asm_text: "sbfx r4, r5, #0x10, #1" + - + asm_text: "sbfxgt r4, r5, #0x10, #0x10" + - + asm_text: "sel r9, r2, r1" + - + asm_text: "selne r9, r2, r1" + - + asm_text: "setend be" + - + asm_text: "setend be" + - + asm_text: "setend le" + - + asm_text: "setend le" + - + asm_text: "sev" + - + asm_text: "seveq" + - + asm_text: "shadd16 r4, r8, r2" + - + asm_text: "shadd16gt r4, r8, r2" + - + asm_text: "shadd8 r4, r8, r2" + - + asm_text: "shadd8gt r4, r8, r2" + - + asm_text: "shasx r4, r8, r2" + - + asm_text: "shasxgt r4, r8, r2" + - + asm_text: "shsub16 r4, r8, r2" + - + asm_text: "shsub16gt r4, r8, r2" + - + asm_text: "shsub8 r4, r8, r2" + - + asm_text: "shsub8gt r4, r8, r2" + - + asm_text: "smlabb r3, r1, r9, r0" + - + asm_text: "smlabt r5, r6, r4, r1" + - + asm_text: "smlatb r4, r2, r3, r2" + - + asm_text: "smlatt r8, r3, r8, r4" + - + asm_text: "smlabbge r3, r1, r9, r0" + - + asm_text: "smlabtle r5, r6, r4, r1" + - + asm_text: "smlatbne r4, r2, r3, r2" + - + asm_text: "smlatteq r8, r3, r8, r4" + - + asm_text: "smlad r2, r3, r5, r8" + - + asm_text: "smladx r2, r3, r5, r8" + - + asm_text: "smladeq r2, r3, r5, r8" + - + asm_text: "smladxhi r2, r3, r5, r8" + - + asm_text: "smlal r2, r3, r5, r8" + - + asm_text: "smlals r2, r3, r5, r8" + - + asm_text: "smlaleq r2, r3, r5, r8" + - + asm_text: "smlalshi r2, r3, r5, r8" + - + asm_text: "smlalbb r3, r1, r9, r0" + - + asm_text: "smlalbt r5, r6, r4, r1" + - + asm_text: "smlaltb r4, r2, r3, r2" + - + asm_text: "smlaltt r8, r3, r8, r4" + - + asm_text: "smlalbbge r3, r1, r9, r0" + - + asm_text: "smlalbtle r5, r6, r4, r1" + - + asm_text: "smlaltbne r4, r2, r3, r2" + - + asm_text: "smlaltteq r8, r3, r8, r4" + - + asm_text: "smlald r2, r3, r5, r8" + - + asm_text: "smlaldx r2, r3, r5, r8" + - + asm_text: "smlaldeq r2, r3, r5, r8" + - + asm_text: "smlaldxhi r2, r3, r5, r8" + - + asm_text: "smlawb r2, r3, r10, r8" + - + asm_text: "smlawt r8, r3, r5, r9" + - + asm_text: "smlawbeq r2, r7, r5, r8" + - + asm_text: "smlawthi r1, r3, r0, r8" + - + asm_text: "smlsd r2, r3, r5, r8" + - + asm_text: "smlsdx r2, r3, r5, r8" + - + asm_text: "smlsdeq r2, r3, r5, r8" + - + asm_text: "smlsdxhi r2, r3, r5, r8" + - + asm_text: "smlsld r2, r9, r5, r1" + - + asm_text: "smlsldx r4, r11, r2, r8" + - + asm_text: "smlsldeq r8, r2, r5, r6" + - + asm_text: "smlsldxhi r1, r0, r3, r8" + - + asm_text: "smmla r1, r2, r3, r4" + - + asm_text: "smmlar r4, r3, r2, r1" + - + asm_text: "smmlalo r1, r2, r3, r4" + - + asm_text: "smmlarhs r4, r3, r2, r1" + - + asm_text: "smmls r1, r2, r3, r4" + - + asm_text: "smmlsr r4, r3, r2, r1" + - + asm_text: "smmlslo r1, r2, r3, r4" + - + asm_text: "smmlsrhs r4, r3, r2, r1" + - + asm_text: "smmul r2, r3, r4" + - + asm_text: "smmulr r3, r2, r1" + - + asm_text: "smmullo r2, r3, r4" + - + asm_text: "smmulrhs r3, r2, r1" + - + asm_text: "smuad r2, r3, r4" + - + asm_text: "smuadx r3, r2, r1" + - + asm_text: "smuadlt r2, r3, r4" + - + asm_text: "smuadxge r3, r2, r1" + - + asm_text: "smulbb r3, r9, r0" + - + asm_text: "smulbt r5, r4, r1" + - + asm_text: "smultb r4, r2, r2" + - + asm_text: "smultt r8, r3, r4" + - + asm_text: "smulbbge r1, r9, r0" + - + asm_text: "smulbtle r5, r6, r4" + - + asm_text: "smultbne r2, r3, r2" + - + asm_text: "smultteq r8, r3, r4" + - + asm_text: "smull r3, r9, r0, r1" + - + asm_text: "smulls r3, r9, r0, r2" + - + asm_text: "smulleq r8, r3, r4, r5" + - + asm_text: "smullseq r8, r3, r4, r3" + - + asm_text: "smulwb r3, r9, r0" + - + asm_text: "smulwt r3, r9, r2" + - + asm_text: "smusd r3, r0, r1" + - + asm_text: "smusdx r3, r9, r2" + - + asm_text: "smusdeq r8, r3, r2" + - + asm_text: "smusdxne r7, r4, r3" + - + asm_text: "srsda sp, #5" + - + asm_text: "srsdb sp, #1" + - + asm_text: "srsia sp, #0" + - + asm_text: "srsib sp, #0xf" + - + asm_text: "srsda sp!, #0x1f" + - + asm_text: "srsdb sp!, #0x13" + - + asm_text: "srsia sp!, #2" + - + asm_text: "srsib sp!, #0xe" + - + asm_text: "srsib sp, #0xb" + - + asm_text: "srsia sp, #0xa" + - + asm_text: "srsdb sp, #0x9" + - + asm_text: "srsda sp, #5" + - + asm_text: "srsib sp!, #5" + - + asm_text: "srsia sp!, #5" + - + asm_text: "srsdb sp!, #5" + - + asm_text: "srsda sp!, #5" + - + asm_text: "srsia sp, #5" + - + asm_text: "srsia sp!, #5" + - + asm_text: "srsda sp, #5" + - + asm_text: "srsdb sp, #1" + - + asm_text: "srsia sp, #0" + - + asm_text: "srsib sp, #0xf" + - + asm_text: "srsda sp!, #0x1f" + - + asm_text: "srsdb sp!, #0x13" + - + asm_text: "srsia sp!, #2" + - + asm_text: "srsib sp!, #0xe" + - + asm_text: "srsib sp, #0xb" + - + asm_text: "srsia sp, #0xa" + - + asm_text: "srsdb sp, #0x9" + - + asm_text: "srsda sp, #5" + - + asm_text: "srsib sp!, #5" + - + asm_text: "srsia sp!, #5" + - + asm_text: "srsdb sp!, #5" + - + asm_text: "srsda sp!, #5" + - + asm_text: "srsia sp, #5" + - + asm_text: "srsia sp!, #5" + - + asm_text: "ssat r8, #1, r10" + - + asm_text: "ssat r8, #1, r10" + - + asm_text: "ssat r8, #1, r10, lsl #0x1f" + - + asm_text: "ssat r8, #1, r10, asr #0x20" + - + asm_text: "ssat r8, #1, r10, asr #1" + - + asm_text: "ssat16 r2, #1, r7" + - + asm_text: "ssat16 r3, #0x10, r5" + - + asm_text: "ssax r2, r3, r4" + - + asm_text: "ssaxlt r2, r3, r4" + - + asm_text: "ssub16 r1, r0, r6" + - + asm_text: "ssub16ne r5, r3, r2" + - + asm_text: "ssub8 r9, r2, r4" + - + asm_text: "ssub8eq r5, r1, r2" + - + asm_text: "stc2 p0, c8, [r1, #4]" + - + asm_text: "stc2 p1, c7, [r2]" + - + asm_text: "stc2 p2, c6, [r3, #-0xe0]" + - + asm_text: "stc2 p3, c5, [r4, #-0x78]!" + - + asm_text: "stc2 p4, c4, [r5], #0x10" + - + asm_text: "stc2 p5, c3, [r6], #-0x48" + - + asm_text: "stc2l p6, c2, [r7, #4]" + - + asm_text: "stc2l p7, c1, [r8]" + - + asm_text: "stc2l p8, c0, [r9, #-0xe0]" + - + asm_text: "stc2l p9, c1, [r10, #-0x78]!" + - + asm_text: "stc2l p0, c2, [r11], #0x10" + - + asm_text: "stc2l p1, c3, [r12], #-0x48" + - + asm_text: "stc p12, c4, [r0, #4]" + - + asm_text: "stc p13, c5, [r1]" + - + asm_text: "stc p14, c6, [r2, #-0xe0]" + - + asm_text: "stc p15, c7, [r3, #-0x78]!" + - + asm_text: "stc p5, c8, [r4], #0x10" + - + asm_text: "stc p4, c9, [r5], #-0x48" + - + asm_text: "stcl p3, c10, [r6, #4]" + - + asm_text: "stcl p2, c11, [r7]" + - + asm_text: "stcl p1, c12, [r8, #-0xe0]" + - + asm_text: "stcl p0, c13, [r9, #-0x78]!" + - + asm_text: "stcl p6, c14, [r10], #0x10" + - + asm_text: "stcl p7, c15, [r11], #-0x48" + - + asm_text: "stclo p12, c4, [r0, #4]" + - + asm_text: "stchi p13, c5, [r1]" + - + asm_text: "stchs p14, c6, [r2, #-0xe0]" + - + asm_text: "stclo p15, c7, [r3, #-0x78]!" + - + asm_text: "stceq p5, c8, [r4], #0x10" + - + asm_text: "stcgt p4, c9, [r5], #-0x48" + - + asm_text: "stcllt p3, c10, [r6, #4]" + - + asm_text: "stclge p2, c11, [r7]" + - + asm_text: "stclle p1, c12, [r8, #-0xe0]" + - + asm_text: "stclne p0, c13, [r9, #-0x78]!" + - + asm_text: "stcleq p6, c14, [r10], #0x10" + - + asm_text: "stclhi p7, c15, [r11], #-0x48" + - + asm_text: "stc2 p2, c8, [r1], {25}" + - + asm_text: "stm r2, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "stm r3, {r1, r3, r4, r5, r6, lr}" + - + asm_text: "stmib r4, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "stmda r5, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "stmdb r6, {r1, r3, r4, r5, r6, r8}" + - + asm_text: "stmdb sp, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "stm r8!, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "stmib r9!, {r1, r3, r4, r5, r6, sp}" + - + asm_text: "stmda sp!, {r1, r3, r4, r5, r6}" + - + asm_text: "stmdb r0!, {r1, r5, r7, sp}" + - + asm_text: "strexb r1, r3, [r4]" + - + asm_text: "strexh r4, r2, [r5]" + - + asm_text: "strex r2, r1, [r7]" + - + asm_text: "strexd r6, r2, r3, [r8]" + - + asm_text: "strpl r3, [r10, #-0]!" + - + asm_text: "strpl r3, [r10, #0]!" + - + asm_text: "sub r4, r5, #0xf000" + - + asm_text: "sub r4, r5, #0xf000" + - + asm_text: "sub r4, r5, #0xf000" + - + asm_text: "sub r7, r8, #0xff0000" + - + asm_text: "sub r7, r8, #-0x7ffffff6" + - + asm_text: "sub r7, r8, #-0x7ffffff6" + - + asm_text: "sub r7, r8, #0x28, #2" + - + asm_text: "sub r7, r8, #0x28, #2" + - + asm_text: "sub r7, r8, #0x28, #2" + - + asm_text: "sub r7, r8, #0x28, #2" + - + asm_text: "sub r4, r5, r6" + - + asm_text: "sub r4, r5, r6, lsl #5" + - + asm_text: "sub r4, r5, r6, lsr #5" + - + asm_text: "sub r4, r5, r6, lsr #5" + - + asm_text: "sub r4, r5, r6, asr #5" + - + asm_text: "sub r4, r5, r6, ror #5" + - + asm_text: "sub r6, r7, r8, lsl r9" + - + asm_text: "sub r6, r7, r8, lsr r9" + - + asm_text: "sub r6, r7, r8, asr r9" + - + asm_text: "sub r6, r7, r8, ror r9" + - + asm_text: "sub r5, r5, #0xf000" + - + asm_text: "sub r5, r5, #0xf000" + - + asm_text: "sub r5, r5, #0xf000" + - + asm_text: "sub r7, r7, #0xff0000" + - + asm_text: "sub r7, r7, #-0x7ffffff6" + - + asm_text: "sub r7, r7, #-0x7ffffff6" + - + asm_text: "sub r7, r7, #0x28, #2" + - + asm_text: "sub r7, r7, #0x28, #2" + - + asm_text: "sub r7, r7, #0x28, #2" + - + asm_text: "sub r4, r4, r5" + - + asm_text: "sub r4, r4, r5, lsl #5" + - + asm_text: "sub r4, r4, r5, lsr #5" + - + asm_text: "sub r4, r4, r5, lsr #5" + - + asm_text: "sub r4, r4, r5, asr #5" + - + asm_text: "sub r4, r4, r5, ror #5" + - + asm_text: "sub r6, r6, r7, lsl r9" + - + asm_text: "sub r6, r6, r7, lsr r9" + - + asm_text: "sub r6, r6, r7, asr r9" + - + asm_text: "sub r6, r6, r7, ror r9" + - + asm_text: "sub r3, r1, r2, lsr #0x20" + - + asm_text: "sub r3, r1, r2, asr #0x20" + - + asm_text: "subs r7, r8, #0xff0000" + - + asm_text: "subs r7, r8, #0xff0000" + - + asm_text: "subs r7, r8, #0xff0000" + - + asm_text: "subs r7, r8, #0xff0000" + - + asm_text: "subs r7, r8, #-0x7ffffff6" + - + asm_text: "subs r7, r8, #-0x7ffffff6" + - + asm_text: "subs r7, r8, #0x28, #2" + - + asm_text: "subs r7, r8, #0x28, #2" + - + asm_text: "subs r7, r8, #0x28, #2" + - + asm_text: "subs r7, r8, #0x28, #2" + - + asm_text: "svc #0x10" + - + asm_text: "svc #0" + - + asm_text: "svc #0xffffff" + - + asm_text: "swp r1, r2, [r3]" + - + asm_text: "swp r4, r4, [r6]" + - + asm_text: "swpb r5, r1, [r9]" + - + asm_text: "sxtab r2, r3, r4" + - + asm_text: "sxtab r4, r5, r6" + - + asm_text: "sxtablt r6, r2, r9, ror #8" + - + asm_text: "sxtab r5, r1, r4, ror #0x10" + - + asm_text: "sxtab r7, r8, r3, ror #0x18" + - + asm_text: "sxtab16ge r0, r1, r4" + - + asm_text: "sxtab16 r6, r2, r7" + - + asm_text: "sxtab16 r3, r5, r8, ror #8" + - + asm_text: "sxtab16 r3, r2, r1, ror #0x10" + - + asm_text: "sxtab16eq r1, r2, r3, ror #0x18" + - + asm_text: "sxtah r1, r3, r9" + - + asm_text: "sxtahhi r6, r1, r6" + - + asm_text: "sxtah r3, r8, r3, ror #8" + - + asm_text: "sxtahlo r2, r2, r4, ror #0x10" + - + asm_text: "sxtah r9, r3, r3, ror #0x18" + - + asm_text: "sxtbge r2, r4" + - + asm_text: "sxtb r5, r6" + - + asm_text: "sxtb r6, r9, ror #8" + - + asm_text: "sxtblo r5, r1, ror #0x10" + - + asm_text: "sxtb r8, r3, ror #0x18" + - + asm_text: "sxtb16 r1, r4" + - + asm_text: "sxtb16 r6, r7" + - + asm_text: "sxtb16hs r3, r5, ror #8" + - + asm_text: "sxtb16 r3, r1, ror #0x10" + - + asm_text: "sxtb16ge r2, r3, ror #0x18" + - + asm_text: "sxthne r3, r9" + - + asm_text: "sxth r1, r6" + - + asm_text: "sxth r3, r8, ror #8" + - + asm_text: "sxthle r2, r2, ror #0x10" + - + asm_text: "sxth r9, r3, ror #0x18" + - + asm_text: "teq r5, #0xf000" + - + asm_text: "teq r5, #0xf000" + - + asm_text: "teq r5, #0xf000" + - + asm_text: "teq r7, #0xff0000" + - + asm_text: "teq r7, #-0x7ffffff6" + - + asm_text: "teq r7, #-0x7ffffff6" + - + asm_text: "teq r7, #0x28, #2" + - + asm_text: "teq r7, #0x28, #2" + - + asm_text: "teq r7, #0x28, #2" + - + asm_text: "teq r7, #0x28, #2" + - + asm_text: "teq r4, r5" + - + asm_text: "teq r4, r5, lsl #5" + - + asm_text: "teq r4, r5, lsr #5" + - + asm_text: "teq r4, r5, lsr #5" + - + asm_text: "teq r4, r5, asr #5" + - + asm_text: "teq r4, r5, ror #5" + - + asm_text: "teq r6, r7, lsl r9" + - + asm_text: "teq r6, r7, lsr r9" + - + asm_text: "teq r6, r7, asr r9" + - + asm_text: "teq r6, r7, ror r9" + - + asm_text: "tst r5, #0xf000" + - + asm_text: "tst r5, #0xf000" + - + asm_text: "tst r5, #0xf000" + - + asm_text: "tst r7, #0xff0000" + - + asm_text: "tst r7, #-0x7ffffff6" + - + asm_text: "tst r7, #-0x7ffffff6" + - + asm_text: "tst r7, #0x28, #2" + - + asm_text: "tst r7, #0x28, #2" + - + asm_text: "tst r7, #0x28, #2" + - + asm_text: "tst r7, #0x28, #2" + - + asm_text: "tst r4, r5" + - + asm_text: "tst r4, r5, lsl #5" + - + asm_text: "tst r4, r5, lsr #5" + - + asm_text: "tst r4, r5, lsr #5" + - + asm_text: "tst r4, r5, asr #5" + - + asm_text: "tst r4, r5, ror #5" + - + asm_text: "tst r6, r7, lsl r9" + - + asm_text: "tst r6, r7, lsr r9" + - + asm_text: "tst r6, r7, asr r9" + - + asm_text: "tst r6, r7, ror r9" + - + asm_text: "uadd16 r1, r2, r3" + - + asm_text: "uadd16gt r1, r2, r3" + - + asm_text: "uadd8 r1, r2, r3" + - + asm_text: "uadd8le r1, r2, r3" + - + asm_text: "uasx r9, r12, r0" + - + asm_text: "uasxeq r9, r12, r0" + - + asm_text: "ubfx r4, r5, #0x10, #1" + - + asm_text: "ubfxgt r4, r5, #0x10, #0x10" + - + asm_text: "uhadd16 r4, r8, r2" + - + asm_text: "uhadd16gt r4, r8, r2" + - + asm_text: "uhadd8 r4, r8, r2" + - + asm_text: "uhadd8gt r4, r8, r2" + - + asm_text: "uhasx r4, r8, r2" + - + asm_text: "uhasxgt r4, r8, r2" + - + asm_text: "uhsub16 r4, r8, r2" + - + asm_text: "uhsub16gt r4, r8, r2" + - + asm_text: "uhsub8 r4, r8, r2" + - + asm_text: "uhsub8gt r4, r8, r2" + - + asm_text: "umaal r3, r4, r5, r6" + - + asm_text: "umaallt r3, r4, r5, r6" + - + asm_text: "umlal r2, r4, r6, r8" + - + asm_text: "umlalgt r6, r1, r2, r6" + - + asm_text: "umlals r2, r9, r2, r3" + - + asm_text: "umlalseq r3, r5, r1, r2" + - + asm_text: "umull r2, r4, r6, r8" + - + asm_text: "umullgt r6, r1, r2, r6" + - + asm_text: "umulls r2, r9, r2, r3" + - + asm_text: "umullseq r3, r5, r1, r2" + - + asm_text: "uqadd16 r1, r2, r3" + - + asm_text: "uqadd16gt r4, r7, r9" + - + asm_text: "uqadd8 r3, r4, r8" + - + asm_text: "uqadd8le r8, r1, r2" + - + asm_text: "uqasx r2, r4, r1" + - + asm_text: "uqasxhi r5, r2, r9" + - + asm_text: "uqsax r1, r3, r7" + - + asm_text: "uqsax r3, r6, r2" + - + asm_text: "uqsub16 r1, r5, r3" + - + asm_text: "uqsub16gt r3, r2, r5" + - + asm_text: "uqsub8 r2, r1, r4" + - + asm_text: "uqsub8le r4, r6, r9" + - + asm_text: "usad8 r2, r1, r4" + - + asm_text: "usad8le r4, r6, r9" + - + asm_text: "usada8 r1, r5, r3, r7" + - + asm_text: "usada8gt r3, r2, r5, r1" + - + asm_text: "usat r8, #1, r10" + - + asm_text: "usat r8, #4, r10" + - + asm_text: "usat r8, #5, r10, lsl #0x1f" + - + asm_text: "usat r8, #0x1f, r10, asr #0x20" + - + asm_text: "usat r8, #0x10, r10, asr #1" + - + asm_text: "usat16 r2, #2, r7" + - + asm_text: "usat16 r3, #0xf, r5" + - + asm_text: "usax r2, r3, r4" + - + asm_text: "usaxne r2, r3, r4" + - + asm_text: "usub16 r4, r2, r7" + - + asm_text: "usub16hi r1, r1, r3" + - + asm_text: "usub8 r1, r8, r5" + - + asm_text: "usub8le r9, r2, r3" + - + asm_text: "uxtab r2, r3, r4" + - + asm_text: "uxtab r4, r5, r6" + - + asm_text: "uxtablt r6, r2, r9, ror #8" + - + asm_text: "uxtab r5, r1, r4, ror #0x10" + - + asm_text: "uxtab r7, r8, r3, ror #0x18" + - + asm_text: "uxtab16ge r0, r1, r4" + - + asm_text: "uxtab16 r6, r2, r7" + - + asm_text: "uxtab16 r3, r5, r8, ror #8" + - + asm_text: "uxtab16 r3, r2, r1, ror #0x10" + - + asm_text: "uxtab16eq r1, r2, r3, ror #0x18" + - + asm_text: "uxtah r1, r3, r9" + - + asm_text: "uxtahhi r6, r1, r6" + - + asm_text: "uxtah r3, r8, r3, ror #8" + - + asm_text: "uxtahlo r2, r2, r4, ror #0x10" + - + asm_text: "uxtah r9, r3, r3, ror #0x18" + - + asm_text: "uxtbge r2, r4" + - + asm_text: "uxtb r5, r6" + - + asm_text: "uxtb r6, r9, ror #8" + - + asm_text: "uxtblo r5, r1, ror #0x10" + - + asm_text: "uxtb r8, r3, ror #0x18" + - + asm_text: "uxtb16 r1, r4" + - + asm_text: "uxtb16 r6, r7" + - + asm_text: "uxtb16hs r3, r5, ror #8" + - + asm_text: "uxtb16 r3, r1, ror #0x10" + - + asm_text: "uxtb16ge r2, r3, ror #0x18" + - + asm_text: "uxthne r3, r9" + - + asm_text: "uxth r1, r6" + - + asm_text: "uxth r3, r8, ror #8" + - + asm_text: "uxthle r2, r2, ror #0x10" + - + asm_text: "uxth r9, r3, ror #0x18" + - + asm_text: "wfe" + - + asm_text: "wfehi" + - + asm_text: "wfi" + - + asm_text: "wfilt" + - + asm_text: "yield" + - + asm_text: "yieldne" + - + asm_text: "sev" + - + asm_text: "wfi" + - + asm_text: "wfe" + - + asm_text: "yield" + - + asm_text: "nop" + - + asm_text: "hintgt #0xef" diff --git a/tests/MC/ARM/basic-thumb-instructions.s.yaml b/tests/MC/ARM/basic-thumb-instructions.s.yaml new file mode 100644 index 0000000000..83e7b0f5cb --- /dev/null +++ b/tests/MC/ARM/basic-thumb-instructions.s.yaml @@ -0,0 +1,266 @@ +test_cases: + - + input: + bytes: [ 0x74, 0x41, 0xd1, 0x1c, 0x03, 0x32, 0x08, 0x32, 0xd1, 0x18, 0x42, 0x44, 0x01, 0xb0, 0x7f, 0xb0, 0x01, 0xb0, 0x02, 0xaa, 0xff, 0xaa, 0x82, 0xb0, 0x82, 0xb0, 0x9d, 0x44, 0x6a, 0x44, 0x00, 0xa5, 0x01, 0xa2, 0xff, 0xa3, 0x1a, 0x10, 0x5a, 0x11, 0x5a, 0x10, 0x6d, 0x15, 0x6d, 0x15, 0x6b, 0x15, 0x15, 0x41, 0x97, 0xe3, 0x2e, 0xe7, 0x80, 0xd0, 0x50, 0xd0, 0xd8, 0xf0, 0x20, 0xe8, 0xb0, 0xf1, 0x40, 0xe8, 0xb1, 0x43, 0x00, 0xbe, 0xff, 0xbe, 0xa0, 0x47, 0x10, 0x47, 0xcd, 0x42, 0x20, 0x2e, 0xa3, 0x42, 0x88, 0x45, 0x61, 0xb6, 0x74, 0xb6, 0x6c, 0x40, 0xff, 0xcb, 0xba, 0xca, 0x02, 0xc9, 0x29, 0x68, 0x32, 0x6a, 0xfb, 0x6f, 0x00, 0x99, 0x06, 0x9a, 0xff, 0x9b, 0x97, 0x4b, 0x5c, 0x4b, 0xd1, 0x58, 0x1c, 0x78, 0x35, 0x78, 0xfe, 0x7f, 0x66, 0x5d, 0x1b, 0x88, 0x74, 0x88, 0xfd, 0x8f, 0x96, 0x5b, 0x96, 0x57, 0x7b, 0x5e, 0x2c, 0x00, 0x2c, 0x01, 0x1b, 0x03, 0x1b, 0x03, 0x19, 0x03, 0xb2, 0x40, 0x59, 0x08, 0x19, 0x08, 0x24, 0x0d, 0x24, 0x0d, 0x22, 0x0d, 0xf2, 0x40, 0x00, 0x22, 0xff, 0x22, 0x17, 0x22, 0x23, 0x46, 0x19, 0x00, 0x51, 0x43, 0x5a, 0x43, 0x63, 0x43, 0xde, 0x43, 0x63, 0x42, 0x4c, 0xbc, 0x86, 0xb4, 0x1e, 0xba, 0x57, 0xba, 0xcd, 0xba, 0xfa, 0x41, 0x59, 0x42, 0x9c, 0x41, 0x58, 0xb6, 0x50, 0xb6, 0x44, 0xc1, 0x8e, 0xc1, 0x3a, 0x60, 0x3a, 0x60, 0x4d, 0x60, 0xfb, 0x67, 0x00, 0x92, 0x00, 0x93, 0x05, 0x94, 0xff, 0x95, 0xfa, 0x50, 0x1c, 0x70, 0x35, 0x70, 0xfe, 0x77, 0x66, 0x55, 0x1b, 0x80, 0x74, 0x80, 0xfd, 0x87, 0x96, 0x53, 0xd1, 0x1e, 0x03, 0x3a, 0x08, 0x3a, 0x83, 0xb0, 0xff, 0xb0, 0xd1, 0x1a, 0x00, 0xdf, 0xff, 0xdf, 0x6b, 0xb2, 0x2b, 0xb2, 0x0e, 0x42, 0xd7, 0xb2, 0xa1, 0xb2 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "adcs r4, r6" + - + asm_text: "adds r1, r2, #3" + - + asm_text: "adds r2, #3" + - + asm_text: "adds r2, #8" + - + asm_text: "adds r1, r2, r3" + - + asm_text: "add r2, r8" + - + asm_text: "add sp, #4" + - + asm_text: "add sp, #0x1fc" + - + asm_text: "add sp, #4" + - + asm_text: "add r2, sp, #8" + - + asm_text: "add r2, sp, #0x3fc" + - + asm_text: "sub sp, #8" + - + asm_text: "sub sp, #8" + - + asm_text: "add sp, r3" + - + asm_text: "add r2, sp, r2" + - + asm_text: "adr r5, #0" + - + asm_text: "adr r2, #4" + - + asm_text: "adr r3, #0x3fc" + - + asm_text: "asrs r2, r3, #0x20" + - + asm_text: "asrs r2, r3, #5" + - + asm_text: "asrs r2, r3, #1" + - + asm_text: "asrs r5, r5, #0x15" + - + asm_text: "asrs r5, r5, #0x15" + - + asm_text: "asrs r3, r5, #0x15" + - + asm_text: "asrs r5, r2" + - + asm_text: "b #0x72e" + - + asm_text: "b #-0x1a4" + - + asm_text: "beq #-0x100" + - + asm_text: "beq #0xa0" + - + asm_text: "blx #0xd8040" + - + asm_text: "blx #0x1b0080" + - + asm_text: "bics r1, r6" + - + asm_text: "bkpt #0" + - + asm_text: "bkpt #0xff" + - + asm_text: "blx r4" + - + asm_text: "bx r2" + - + asm_text: "cmn r5, r1" + - + asm_text: "cmp r6, #0x20" + - + asm_text: "cmp r3, r4" + - + asm_text: "cmp r8, r1" + - + asm_text: "cpsie f" + - + asm_text: "cpsid a" + - + asm_text: "eors r4, r5" + - + asm_text: "ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7}" + - + asm_text: "ldm r2!, {r1, r3, r4, r5, r7}" + - + asm_text: "ldm r1, {r1}" + - + asm_text: "ldr r1, [r5]" + - + asm_text: "ldr r2, [r6, #0x20]" + - + asm_text: "ldr r3, [r7, #0x7c]" + - + asm_text: "ldr r1, [sp]" + - + asm_text: "ldr r2, [sp, #0x18]" + - + asm_text: "ldr r3, [sp, #0x3fc]" + - + asm_text: "ldr r3, [pc, #0x25c]" + - + asm_text: "ldr r3, [pc, #0x170]" + - + asm_text: "ldr r1, [r2, r3]" + - + asm_text: "ldrb r4, [r3]" + - + asm_text: "ldrb r5, [r6]" + - + asm_text: "ldrb r6, [r7, #0x1f]" + - + asm_text: "ldrb r6, [r4, r5]" + - + asm_text: "ldrh r3, [r3]" + - + asm_text: "ldrh r4, [r6, #2]" + - + asm_text: "ldrh r5, [r7, #0x3e]" + - + asm_text: "ldrh r6, [r2, r6]" + - + asm_text: "ldrsb r6, [r2, r6]" + - + asm_text: "ldrsh r3, [r7, r1]" + - + asm_text: "movs r4, r5" + - + asm_text: "lsls r4, r5, #4" + - + asm_text: "lsls r3, r3, #0xc" + - + asm_text: "lsls r3, r3, #0xc" + - + asm_text: "lsls r1, r3, #0xc" + - + asm_text: "lsls r2, r6" + - + asm_text: "lsrs r1, r3, #1" + - + asm_text: "lsrs r1, r3, #0x20" + - + asm_text: "lsrs r4, r4, #0x14" + - + asm_text: "lsrs r4, r4, #0x14" + - + asm_text: "lsrs r2, r4, #0x14" + - + asm_text: "lsrs r2, r6" + - + asm_text: "movs r2, #0" + - + asm_text: "movs r2, #0xff" + - + asm_text: "movs r2, #0x17" + - + asm_text: "mov r3, r4" + - + asm_text: "movs r1, r3" + - + asm_text: "muls r1, r2, r1" + - + asm_text: "muls r2, r3, r2" + - + asm_text: "muls r3, r4, r3" + - + asm_text: "mvns r6, r3" + - + asm_text: "rsbs r3, r4, #0" + - + asm_text: "pop {r2, r3, r6}" + - + asm_text: "push {r1, r2, r7}" + - + asm_text: "rev r6, r3" + - + asm_text: "rev16 r7, r2" + - + asm_text: "revsh r5, r1" + - + asm_text: "rors r2, r7" + - + asm_text: "rsbs r1, r3, #0" + - + asm_text: "sbcs r4, r3" + - + asm_text: "setend be" + - + asm_text: "setend le" + - + asm_text: "stm r1!, {r2, r6}" + - + asm_text: "stm r1!, {r1, r2, r3, r7}" + - + asm_text: "str r2, [r7]" + - + asm_text: "str r2, [r7]" + - + asm_text: "str r5, [r1, #4]" + - + asm_text: "str r3, [r7, #0x7c]" + - + asm_text: "str r2, [sp]" + - + asm_text: "str r3, [sp]" + - + asm_text: "str r4, [sp, #0x14]" + - + asm_text: "str r5, [sp, #0x3fc]" + - + asm_text: "str r2, [r7, r3]" + - + asm_text: "strb r4, [r3]" + - + asm_text: "strb r5, [r6]" + - + asm_text: "strb r6, [r7, #0x1f]" + - + asm_text: "strb r6, [r4, r5]" + - + asm_text: "strh r3, [r3]" + - + asm_text: "strh r4, [r6, #2]" + - + asm_text: "strh r5, [r7, #0x3e]" + - + asm_text: "strh r6, [r2, r6]" + - + asm_text: "subs r1, r2, #3" + - + asm_text: "subs r2, #3" + - + asm_text: "subs r2, #8" + - + asm_text: "sub sp, #0xc" + - + asm_text: "sub sp, #0x1fc" + - + asm_text: "subs r1, r2, r3" + - + asm_text: "svc #0" + - + asm_text: "svc #0xff" + - + asm_text: "sxtb r3, r5" + - + asm_text: "sxth r3, r5" + - + asm_text: "tst r6, r1" + - + asm_text: "uxtb r7, r2" + - + asm_text: "uxth r1, r4" diff --git a/tests/MC/ARM/basic-thumb2-instructions.s.yaml b/tests/MC/ARM/basic-thumb2-instructions.s.yaml new file mode 100644 index 0000000000..634286b5b6 --- /dev/null +++ b/tests/MC/ARM/basic-thumb2-instructions.s.yaml @@ -0,0 +1,2688 @@ +test_cases: + - + input: + bytes: [ 0x41, 0xf1, 0x04, 0x00, 0x51, 0xf1, 0x00, 0x00, 0x42, 0xf1, 0xff, 0x01, 0x47, 0xf1, 0x55, 0x13, 0x4c, 0xf1, 0xaa, 0x28, 0x47, 0xf1, 0xa5, 0x39, 0x43, 0xf1, 0x07, 0x45, 0x42, 0xf1, 0xff, 0x44, 0x42, 0xf5, 0xd0, 0x64, 0x45, 0xeb, 0x06, 0x04, 0x55, 0xeb, 0x06, 0x04, 0x41, 0xeb, 0x03, 0x09, 0x51, 0xeb, 0x03, 0x09, 0x41, 0xeb, 0x33, 0x10, 0x51, 0xeb, 0xc3, 0x10, 0x41, 0xeb, 0xd3, 0x70, 0x51, 0xeb, 0x23, 0x00, 0x0a, 0xbf, 0x11, 0x1d, 0x03, 0xf2, 0xff, 0x35, 0x05, 0xf2, 0x25, 0x14, 0x0d, 0xf5, 0x80, 0x62, 0x08, 0xf5, 0x7f, 0x42, 0x03, 0xf2, 0x01, 0x12, 0x03, 0xf2, 0x01, 0x12, 0x06, 0xf5, 0x80, 0x7c, 0x06, 0xf2, 0x00, 0x1c, 0x12, 0xf5, 0xf8, 0x71, 0x02, 0xf1, 0x01, 0x02, 0x00, 0xf1, 0x20, 0x00, 0x38, 0x32, 0x38, 0x32, 0x07, 0xf1, 0xcb, 0x31, 0xb2, 0xf1, 0x10, 0x02, 0xb2, 0xf1, 0x10, 0x02, 0xa2, 0xf2, 0x10, 0x02, 0xa2, 0xf2, 0x10, 0x02, 0xa2, 0xf2, 0x10, 0x02, 0x02, 0xeb, 0x08, 0x01, 0x09, 0xeb, 0x22, 0x05, 0x13, 0xeb, 0xc1, 0x77, 0x13, 0xeb, 0x56, 0x60, 0x08, 0xeb, 0x31, 0x34, 0xc9, 0x19, 0x08, 0xbf, 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0xaf, 0xf3, 0x00, 0x80, 0x40, 0xbf, 0x30, 0xbf, 0x20, 0xbf, 0x10, 0xbf, 0x00, 0xbf, 0xb6, 0xbf, 0xf0, 0xbf, 0xaf, 0xf3, 0x10, 0x80, 0xaf, 0xf3, 0xef, 0x80, 0x70, 0xbf, 0xaf, 0xf3, 0x07, 0x80, 0x9f, 0xf8, 0x16, 0xb0, 0xbf, 0xf8, 0x16, 0xb0, 0x9f, 0xf9, 0x16, 0xb0, 0xbf, 0xf9, 0x16, 0xb0, 0xdf, 0xf8, 0x16, 0xb0, 0x9f, 0xf8, 0x16, 0xb0, 0xbf, 0xf8, 0x16, 0xb0, 0x9f, 0xf9, 0x16, 0xb0, 0xbf, 0xf9, 0x16, 0xb0, 0x5f, 0xf8, 0x16, 0xb0, 0x1f, 0xf8, 0x16, 0xb0, 0x3f, 0xf8, 0x16, 0xb0, 0x1f, 0xf9, 0x16, 0xb0, 0x3f, 0xf9, 0x16, 0xb0, 0x5f, 0xf8, 0x16, 0xb0, 0x1f, 0xf8, 0x16, 0xb0, 0x3f, 0xf8, 0x16, 0xb0, 0x1f, 0xf9, 0x16, 0xb0, 0x3f, 0xf9, 0x16, 0xb0, 0x03, 0x49, 0xde, 0xf3, 0x04, 0x8f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "adc r0, r1, #4" + - + asm_text: "adcs r0, r1, #0" + - + asm_text: "adc r1, r2, #0xff" + - + asm_text: "adc r3, r7, #0x550055" + - + asm_text: "adc r8, r12, #0xaa00aa00" + - + asm_text: "adc r9, r7, #0xa5a5a5a5" + - + asm_text: "adc r5, r3, #0x87000000" + - + asm_text: "adc r4, r2, #0x7f800000" + - + asm_text: "adc r4, r2, #0x680" + - + asm_text: "adc.w r4, r5, r6" + - + asm_text: "adcs.w r4, r5, r6" + - + asm_text: "adc.w r9, r1, r3" + - + asm_text: "adcs.w r9, r1, r3" + - + asm_text: "adc.w r0, r1, r3, ror #4" + - + asm_text: "adcs.w r0, r1, r3, lsl #7" + - + asm_text: "adc.w r0, r1, r3, lsr #0x1f" + - + asm_text: "adcs.w r0, r1, r3, asr #0x20" + - + asm_text: "itet eq" + - + asm_text: "addeq r1, r2, #4" + - + asm_text: "addwne r5, r3, #0x3ff" + - + asm_text: "addweq r4, r5, #0x125" + - + asm_text: "add.w r2, sp, #0x400" + - + asm_text: "add.w r2, r8, #0xff00" + - + asm_text: "addw r2, r3, #0x101" + - + asm_text: "addw r2, r3, #0x101" + - + asm_text: "add.w r12, r6, #0x100" + - + asm_text: "addw r12, r6, #0x100" + - + asm_text: "adds.w r1, r2, #0x1f0" + - + asm_text: "add.w r2, r2, #1" + - + asm_text: "add.w r0, r0, #0x20" + - + asm_text: "adds r2, #0x38" + - + asm_text: "adds r2, #0x38" + - + asm_text: "add.w r1, r7, #0xcbcbcbcb" + - + asm_text: "subs.w r2, r2, #0x10" + - + asm_text: "subs.w r2, r2, #0x10" + - + asm_text: "subw r2, r2, #0x10" + - + asm_text: "subw r2, r2, #0x10" + - + asm_text: "subw r2, r2, #0x10" + - + asm_text: "add.w r1, r2, r8" + - + asm_text: "add.w r5, r9, r2, asr #0x20" + - + asm_text: "adds.w r7, r3, r1, lsl #0x1f" + - + asm_text: "adds.w r0, r3, r6, lsr #0x19" + - + asm_text: "add.w r4, r8, r1, ror #0xc" + - + asm_text: "adds r1, r1, r7" + - + asm_text: "it eq" + - + asm_text: "addeq r1, r3, r5" + - + asm_text: "it eq" + - + asm_text: "addeq r1, r1, r5" + - + asm_text: "it eq" + - + asm_text: "addseq.w r1, r3, r5" + - + asm_text: "it eq" + - + asm_text: "addseq.w r1, r1, r5" + - + asm_text: "add r10, r8" + - + asm_text: "add r10, r8" + - + asm_text: "it eq" + - + asm_text: "addeq r1, r10" + - + asm_text: "it eq" + - + asm_text: "addseq.w r1, r1, r10" + - + asm_text: "it eq" + - + asm_text: "addeq r7, sp, #0x3fc" + - + asm_text: "it eq" + - + asm_text: "addeq sp, #0x1fc" + - + asm_text: "add.w r7, sp, #0xf" + - + asm_text: "adds.w r7, sp, #0x10" + - + asm_text: "add.w r8, sp, #0x10" + - + asm_text: "addw r6, sp, #0x3fc" + - + asm_text: "addw r6, sp, #0x3fb" + - + asm_text: "it eq" + - + asm_text: "addeq r8, sp, r8" + - + asm_text: "it eq" + - + asm_text: "addeq sp, r9" + - + asm_text: "add.w r2, sp, r12" + - + asm_text: "it eq" + - + asm_text: "addeq.w r2, sp, r12" + - + asm_text: "adr.w r11, #4294964026" + - + asm_text: "adr.w r2, #3" + - + asm_text: "adr.w r11, #-0x33a" + - + asm_text: "subw r1, pc, #0" + - + asm_text: "and r2, r5, #0xff000" + - + asm_text: "ands r3, r12, #0xf" + - + asm_text: "and r1, r1, #0xff" + - + asm_text: "and r1, r1, #0xff" + - + asm_text: "and r5, r4, #0xffffffff" + - + asm_text: "ands r1, r9, #0xffffffff" + - + asm_text: "and.w r4, r9, r8" + - + asm_text: "and.w r1, r4, r8, asr #3" + - + asm_text: "ands.w r2, r1, r7, lsl #1" + - + asm_text: "ands.w r4, r5, r2, lsr #0x14" + - + asm_text: "and.w r9, r12, r1, ror #0x11" + - + asm_text: "asr.w r2, r3, #0xc" + - + asm_text: "asrs.w r8, r3, #0x20" + - + asm_text: "asrs.w r2, r3, #1" + - + asm_text: "asr.w r2, r3, #4" + - + asm_text: "asrs.w r2, r12, #0xf" + - + asm_text: "asr.w r3, r3, #0x13" + - + asm_text: "asrs.w r8, r8, #2" + - + asm_text: "asrs.w r7, r7, #5" + - + asm_text: "asr.w r12, r12, #0x15" + - + asm_text: "asrs r1, r2, #1" + - + asm_text: "itt eq" + - + asm_text: "asrseq.w r1, r2, #1" + - + asm_text: "asreq r1, r2, #1" + - + asm_text: "asr.w r3, r4, r2" + - + asm_text: "asr.w r1, r1, r2" + - + asm_text: "asrs.w r3, r4, r8" + - + asm_text: "it eq" + - + asm_text: "beq.w #-0x2cc64" + - + asm_text: "bfc r5, #3, #0x11" + - + asm_text: "it lo" + - + asm_text: "bfclo r5, #3, #0x11" + - + asm_text: "bfi r5, r2, #3, #0x11" + - + asm_text: "it ne" + - + asm_text: "bfine r5, r2, #3, #0x11" + - + asm_text: "bic r10, r1, #0xf" + - + asm_text: "bic r5, r2, #0xffffffff" + - + asm_text: "bics r11, r10, #0xffffffff" + - + asm_text: "bic.w r12, r3, r6" + - + asm_text: "bic.w r11, r2, r6, lsl #0xc" + - + asm_text: "bic.w r8, r4, r1, lsr #0xb" + - + asm_text: "bic.w r7, r5, r7, lsr #0xf" + - + asm_text: "bic.w r6, r7, r9, asr #0x20" + - + asm_text: "bic.w r5, r6, r8, ror #1" + - + asm_text: "bic r1, r1, #0xf" + - + asm_text: "bic.w r1, r1, r1" + - + asm_text: "bic.w r4, r4, r2, lsl #0x1f" + - + asm_text: "bic.w r6, r6, r3, lsr #0xc" + - + asm_text: "bic.w r7, r7, r4, lsr #7" + - + asm_text: "bic.w r8, r8, r5, asr #0xf" + - + asm_text: "bic.w r12, r12, r6, ror #0x1d" + - + asm_text: "it pl" + - + asm_text: "bkpt #0xea" + - + asm_text: "bxj r5" + - + asm_text: "it ne" + - + asm_text: "bxjne r7" + - + asm_text: "cbnz r7, #6" + - + asm_text: "cbnz r7, #0xc" + - + asm_text: "cdp p7, #1, c1, c1, c1, #4" + - + asm_text: "cdp2 p7, #1, c1, c1, c1, #4" + - + asm_text: "clrex" + - + asm_text: "it ne" + - + asm_text: "clrexne" + - + asm_text: "clz r1, r2" + - + asm_text: "it eq" + - + asm_text: "clzeq r1, r2" + - + asm_text: "cmn.w r1, #0xf" + - + asm_text: "cmn.w r8, r6" + - + asm_text: "cmn.w r1, r6, lsl #0xa" + - + asm_text: "cmn.w r1, r6, lsr #0xa" + - + asm_text: "cmn.w sp, r6, lsr #0xa" + - + asm_text: "cmn.w r1, r6, asr #0xa" + - + asm_text: "cmn.w r1, r6, ror #0xa" + - + asm_text: "cmp.w r5, #0xff00" + - + asm_text: "cmp.w r4, r12" + - + asm_text: "cmp.w r9, r6, lsl #0xc" + - + asm_text: "cmp.w r3, r7, lsr #0x1f" + - + asm_text: "cmp.w sp, r6, lsr #1" + - + asm_text: "cmp.w r2, r5, asr #0x18" + - + asm_text: "cmp.w r1, r4, ror #0xf" + - + asm_text: "cmn.w r2, #2" + - + asm_text: "cmp.w r9, #1" + - + asm_text: "cpsie f" + - + asm_text: "cpsid a" + - + asm_text: "cpsie.w f" + - + asm_text: "cpsid.w a" + - + asm_text: "cpsie i, #3" + - + asm_text: "cpsie i, #3" + - + asm_text: "cpsid f, #0x9" + - + asm_text: "cpsid f, #0x9" + - + asm_text: "cps #0" + - + asm_text: "cps #0" + - + asm_text: "dbg #5" + - + asm_text: "dbg #0" + - + asm_text: "dbg #0xf" + - + asm_text: "dbg #0" + - + asm_text: "it ne" + - + asm_text: "dbgne #0" + - + asm_text: "dmb sy" + - + asm_text: "dmb st" + - + asm_text: "dmb #0xd" + - + asm_text: "dmb #0xc" + - + asm_text: "dmb ish" + - + asm_text: "dmb ishst" + - + asm_text: "dmb #0x9" + - + asm_text: "dmb #0x8" + - + asm_text: "dmb nsh" + - + asm_text: "dmb nshst" + - + asm_text: "dmb #0x5" + - + asm_text: "dmb #0x4" + - + asm_text: "dmb osh" + - + asm_text: "dmb oshst" + - + asm_text: "dmb #0x1" + - + asm_text: "dmb #0x0" + - + asm_text: "dmb sy" + - + asm_text: "dmb sy" + - + asm_text: "dmb st" + - + asm_text: "dmb ish" + - + asm_text: "dmb ish" + - + asm_text: "dmb ishst" + - + asm_text: "dmb ishst" + - + asm_text: "dmb nsh" + - + asm_text: "dmb nsh" + - + asm_text: "dmb nshst" + - + asm_text: "dmb nshst" + - + asm_text: "dmb osh" + - + asm_text: "dmb oshst" + - + asm_text: "dmb sy" + - + asm_text: "dmb sy" + - + asm_text: "dsb sy" + - + asm_text: "dsb st" + - + asm_text: "dsb #0xd" + - + asm_text: "dsb #0xc" + - + asm_text: "dsb ish" + - + asm_text: "dsb ishst" + - + asm_text: "dsb #0x9" + - + asm_text: "dsb #0x8" + - + asm_text: "dsb nsh" + - + asm_text: "dsb nshst" + - + asm_text: "dsb #0x5" + - + asm_text: "pssbb" + - + asm_text: "dsb osh" + - + asm_text: "dsb oshst" + - + asm_text: "dsb #0x1" + - + asm_text: "ssbb" + - + asm_text: "dsb sy" + - + asm_text: "dsb sy" + - + asm_text: "dsb st" + - + asm_text: "dsb ish" + - + asm_text: "dsb ish" + - + asm_text: "dsb ishst" + - + asm_text: "dsb ishst" + - + asm_text: "dsb nsh" + - + asm_text: "dsb nsh" + - + asm_text: "dsb nshst" + - + asm_text: "dsb nshst" + - + asm_text: "dsb osh" + - + asm_text: "dsb oshst" + - + asm_text: "dsb sy" + - + asm_text: "dsb sy" + - + asm_text: "eor r4, r5, #0xf000" + - + asm_text: "eor.w r4, r5, r6" + - + asm_text: "eor.w r4, r5, r6, lsl #5" + - + asm_text: "eor.w r4, r5, r6, lsr #5" + - + asm_text: "eor.w r4, r5, r6, lsr #5" + - + asm_text: "eor.w r4, r5, r6, asr #5" + - + asm_text: "eor.w r4, r5, r6, ror #5" + - + asm_text: "isb sy" + - + asm_text: "isb sy" + - + asm_text: "isb sy" + - + asm_text: "isb sy" + - + asm_text: "isb sy" + - + asm_text: "isb #0x1" + - + asm_text: "iteet eq" + - + asm_text: "addeq r0, r1, r2" + - + asm_text: "nopne" + - + asm_text: "subne r5, r6, r7" + - + asm_text: "addeq r1, r2, #4" + - + asm_text: "iteet eq" + - + asm_text: "addeq r0, r1, r2" + - + asm_text: "nopne" + - + asm_text: "subne r5, r6, r7" + - + asm_text: "addeq r1, r2, #4" + - + asm_text: "ldc2 p0, c8, [r1, #4]" + - + asm_text: "ldc2 p1, c7, [r2]" + - + asm_text: "ldc2 p2, c6, [r3, #-0xe0]" + - + asm_text: "ldc2 p3, c5, [r4, #-0x78]!" + - + asm_text: "ldc2 p4, c4, [r5], #0x10" + - + asm_text: "ldc2 p5, c3, [r6], #-0x48" + - + asm_text: "ldc2l p6, c2, [r7, #4]" + - + asm_text: "ldc2l p7, c1, [r8]" + - + asm_text: "ldc2l p8, c0, [r9, #-0xe0]" + - + asm_text: "ldc2l p9, c1, [r10, #-0x78]!" + - + asm_text: "ldc2l p0, c2, [r11], #0x10" + - + asm_text: "ldc2l p1, c3, [r12], #-0x48" + - + asm_text: "ldc p12, c4, [r0, #4]" + - + asm_text: "ldc p13, c5, [r1]" + - + asm_text: "ldc p14, c6, [r2, #-0xe0]" + - + asm_text: "ldc p15, c7, [r3, #-0x78]!" + - + asm_text: "ldc p5, c8, [r4], #0x10" + - + asm_text: "ldc p4, c9, [r5], #-0x48" + - + asm_text: "ldcl p3, c10, [r6, #4]" + - + asm_text: "ldcl p2, c11, [r7]" + - + asm_text: "ldcl p1, c12, [r8, #-0xe0]" + - + asm_text: "ldcl p0, c13, [r9, #-0x78]!" + - + asm_text: "ldcl p6, c14, [r10], #0x10" + - + asm_text: "ldcl p7, c15, [r11], #-0x48" + - + asm_text: "ldc2 p2, c8, [r1], {25}" + - + asm_text: "ldm.w r4, {r4, r5, r8, r9}" + - + asm_text: "ldm.w r4, {r5, r6}" + - + asm_text: "ldm.w r5!, {r3, r8}" + - + asm_text: "ldm.w r4, {r4, r5, r8, r9}" + - + asm_text: "ldm.w r4, {r5, r6}" + - + asm_text: "ldm.w r5!, {r3, r8}" + - + asm_text: "ldm.w r5!, {r1, r2}" + - + asm_text: "ldm.w r2, {r1, r2}" + - + asm_text: "ldm.w r4, {r4, r5, r8, r9}" + - + asm_text: "ldm.w r4, {r5, r6}" + - + asm_text: "ldm.w r5!, {r3, r8}" + - + asm_text: "ldm.w r4, {r4, r5, r8, r9}" + - + asm_text: "ldm.w r4, {r5, r6}" + - + asm_text: "ldm.w r5!, {r3, r8}" + - + asm_text: "ldm.w r5!, {r3, r8}" + - + asm_text: "pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}" + - + asm_text: "ldmdb r4, {r4, r5, r8, r9}" + - + asm_text: "ldmdb r4, {r5, r6}" + - + asm_text: "ldmdb r5!, {r3, r8}" + - + asm_text: "ldmdb r5!, {r3, r8}" + - + asm_text: "ldmdb r4, {r5, r6}" + - + asm_text: "ldmdb r5!, {r3, r8}" + - + asm_text: "ldr r5, [r5, #-4]" + - + asm_text: "ldr r5, [r6, #0x20]" + - + asm_text: "ldr.w r5, [r6, #0x21]" + - + asm_text: "ldr.w r5, [r6, #0x101]" + - + asm_text: "ldr.w pc, [r7, #0x101]" + - + asm_text: "ldr r2, [r4, #0xff]!" + - + asm_text: "ldr r8, [sp, #4]!" + - + asm_text: "ldr lr, [sp, #-4]!" + - + asm_text: "ldr r2, [r4], #0xff" + - + asm_text: "pop {r8}" + - + asm_text: "ldr lr, [sp], #-4" + - + asm_text: "ldr r7, [pc, #8]" + - + asm_text: "ldr r7, [pc, #8]" + - + asm_text: "ldr.w r7, [pc, #8]" + - + asm_text: "ldr r4, [pc, #0x3fc]" + - + asm_text: "ldr.w r3, [pc, #-0x3fc]" + - + asm_text: "ldr.w r6, [pc, #0x400]" + - + asm_text: "ldr.w r0, [pc, #-0x400]" + - + asm_text: "ldr.w r2, [pc, #0xfff]" + - + asm_text: "ldr.w r1, [pc, #-0xfff]" + - + asm_text: "ldr.w r8, [pc, #0x84]" + - + asm_text: "ldr.w pc, [pc, #0x100]" + - + asm_text: "ldr.w pc, [pc, #-0x190]" + - + asm_text: "ldr.w sp, [pc, #4]" + - + asm_text: "ldrb.w r9, [pc, #-0]" + - + asm_text: "ldrsb.w r11, [pc, #-0]" + - + asm_text: "ldrh.w r10, [pc, #-0]" + - + asm_text: "ldrsh.w r1, [pc, #-0]" + - + asm_text: "ldr.w r5, [pc, #-0]" + - + asm_text: "ldr.w r1, [r8, r1]" + - + asm_text: "ldr.w r4, [r5, r2]" + - + asm_text: "ldr.w r6, [r0, r2, lsl #3]" + - + asm_text: "ldr.w r8, [r8, r2, lsl #2]" + - + asm_text: "ldr.w r7, [sp, r2, lsl #1]" + - + asm_text: "ldr.w r7, [sp, r2]" + - + asm_text: "ldrb r5, [r5, #-4]" + - + asm_text: "ldrb.w r5, [r6, #0x20]" + - + asm_text: "ldrb.w r5, [r6, #0x21]" + - + asm_text: "ldrb.w r5, [r6, #0x101]" + - + asm_text: "ldrb.w lr, [r7, #0x101]" + - + asm_text: "ldrb r5, [r8, #0xff]!" + - + asm_text: "ldrb r2, [r5, #4]!" + - + asm_text: "ldrb r1, [r4, #-4]!" + - + asm_text: "ldrb lr, [r3], #0xff" + - + asm_text: "ldrb r9, [r2], #4" + - + asm_text: "ldrb r3, [sp], #-4" + - + asm_text: "ldrb.w r1, [r8, r1]" + - + asm_text: "ldrb.w r4, [r5, r2]" + - + asm_text: "ldrb.w r6, [r0, r2, lsl #3]" + - + asm_text: "ldrb.w r8, [r8, r2, lsl #2]" + - + asm_text: "ldrb.w r7, [sp, r2, lsl #1]" + - + asm_text: "ldrb.w r7, [sp, r2]" + - + asm_text: "ldrbt r1, [r2]" + - + asm_text: "ldrbt r1, [r8]" + - + asm_text: "ldrbt r1, [r8, #3]" + - + asm_text: "ldrbt r1, [r8, #0xff]" + - + asm_text: "ldrd r3, r5, [r6, #0x18]" + - + asm_text: "ldrd r3, r5, [r6, #0x18]!" + - + asm_text: "ldrd r3, r5, [r6], #4" + - + asm_text: "ldrd r3, r5, [r6], #-8" + - + asm_text: "ldrd r3, r5, [r6]" + - + asm_text: "ldrd r8, r1, [r3]" + - + asm_text: "ldrd r0, r1, [r2, #-0]" + - + asm_text: "ldrd r0, r1, [r2, #-0]!" + - + asm_text: "ldrd r0, r1, [r2], #-0" + - + asm_text: "ldrex r1, [r4]" + - + asm_text: "ldrex r8, [r4]" + - + asm_text: "ldrex r2, [sp, #0x80]" + - + asm_text: "ldrexb r5, [r7]" + - + asm_text: "ldrexh r9, [r12]" + - + asm_text: "ldrexd r9, r3, [r4]" + - + asm_text: "ldrh r5, [r5, #-4]" + - + asm_text: "ldrh r5, [r6, #0x20]" + - + asm_text: "ldrh.w r5, [r6, #0x21]" + - + asm_text: "ldrh.w r5, [r6, #0x101]" + - + asm_text: "ldrh.w lr, [r7, #0x101]" + - + asm_text: "ldrh r5, [r8, #0xff]!" + - + asm_text: "ldrh r2, [r5, #4]!" + - + asm_text: "ldrh r1, [r4, #-4]!" + - + asm_text: "ldrh lr, [r3], #0xff" + - + asm_text: "ldrh r9, [r2], #4" + - + asm_text: "ldrh r3, [sp], #-4" + - + asm_text: "ldrh.w r1, [r8, r1]" + - + asm_text: "ldrh.w r4, [r5, r2]" + - + asm_text: "ldrh.w r6, [r0, r2, lsl #3]" + - + asm_text: "ldrh.w r8, [r8, r2, lsl #2]" + - + asm_text: "ldrh.w r7, [sp, r2, lsl #1]" + - + asm_text: "ldrh.w r7, [sp, r2]" + - + asm_text: "ldrht r1, [r2]" + - + asm_text: "ldrht r1, [r8]" + - + asm_text: "ldrht r1, [r8, #3]" + - + asm_text: "ldrht r1, [r8, #0xff]" + - + asm_text: "ldrsb r5, [r5, #-4]" + - + asm_text: "ldrsb.w r5, [r6, #0x20]" + - + asm_text: "ldrsb.w r5, [r6, #0x21]" + - + asm_text: "ldrsb.w r5, [r6, #0x101]" + - + asm_text: "ldrsb.w lr, [r7, #0x101]" + - + asm_text: "ldrsb.w r1, [r8, r1]" + - + asm_text: "ldrsb.w r4, [r5, r2]" + - + asm_text: "ldrsb.w r6, [r0, r2, lsl #3]" + - + asm_text: "ldrsb.w r8, [r8, r2, lsl #2]" + - + asm_text: "ldrsb.w r7, [sp, r2, lsl #1]" + - + asm_text: "ldrsb.w r7, [sp, r2]" + - + asm_text: "ldrsb r5, [r8, #0xff]!" + - + asm_text: "ldrsb r2, [r5, #4]!" + - + asm_text: "ldrsb r1, [r4, #-4]!" + - + asm_text: "ldrsb lr, [r3], #0xff" + - + asm_text: "ldrsb r9, [r2], #4" + - + asm_text: "ldrsb r3, [sp], #-4" + - + asm_text: "ldrsbt r1, [r2]" + - + asm_text: "ldrsbt r1, [r8]" + - + asm_text: "ldrsbt r1, [r8, #3]" + - + asm_text: "ldrsbt r1, [r8, #0xff]" + - + asm_text: "ldrsh r5, [r5, #-4]" + - + asm_text: "ldrsh.w r5, [r6, #0x20]" + - + asm_text: "ldrsh.w r5, [r6, #0x21]" + - + asm_text: "ldrsh.w r5, [r6, #0x101]" + - + asm_text: "ldrsh.w lr, [r7, #0x101]" + - + asm_text: "ldrsh.w r1, [r8, r1]" + - + asm_text: "ldrsh.w r4, [r5, r2]" + - + asm_text: "ldrsh.w r6, [r0, r2, lsl #3]" + - + asm_text: "ldrsh.w r8, [r8, r2, lsl #2]" + - + asm_text: "ldrsh.w r7, [sp, r2, lsl #1]" + - + asm_text: "ldrsh.w r7, [sp, r2]" + - + asm_text: "ldrsh r5, [r8, #0xff]!" + - + asm_text: "ldrsh r2, [r5, #4]!" + - + asm_text: "ldrsh r1, [r4, #-4]!" + - + asm_text: "ldrsh lr, [r3], #0xff" + - + asm_text: "ldrsh r9, [r2], #4" + - + asm_text: "ldrsh r3, [sp], #-4" + - + asm_text: "ldrsht r1, [r2]" + - + asm_text: "ldrsht r1, [r8]" + - + asm_text: "ldrsht r1, [r8, #3]" + - + asm_text: "ldrsht r1, [r8, #0xff]" + - + asm_text: "ldrt r1, [r2]" + - + asm_text: "ldrt r2, [r6]" + - + asm_text: "ldrt r3, [r7, #3]" + - + asm_text: "ldrt r4, [r9, #0xff]" + - + asm_text: "lsl.w r2, r3, #0xc" + - + asm_text: "lsls.w r8, r3, #0x1f" + - + asm_text: "lsls.w r2, r3, #1" + - + asm_text: "lsl.w r2, r3, #4" + - + asm_text: "lsls.w r2, r12, #0xf" + - + asm_text: "lsl.w r3, r3, #0x13" + - + asm_text: "lsls.w r8, r8, #2" + - + asm_text: "lsls.w r7, r7, #5" + - + asm_text: "lsl.w r12, r12, #0x15" + - + asm_text: "lsls r1, r2, #1" + - + asm_text: "itt eq" + - + asm_text: "lslseq.w r1, r2, #1" + - + asm_text: "lsleq r1, r2, #1" + - + asm_text: "lsl.w r3, r4, r2" + - + asm_text: "lsl.w r1, r1, r2" + - + asm_text: "lsls.w r3, r4, r8" + - + asm_text: "lsr.w r2, r3, #0xc" + - + asm_text: "lsrs.w r8, r3, #0x20" + - + asm_text: "lsrs.w r2, r3, #1" + - + asm_text: "lsr.w r2, r3, #4" + - + asm_text: "lsrs.w r2, r12, #0xf" + - + asm_text: "lsr.w r3, r3, #0x13" + - + asm_text: "lsrs.w r8, r8, #2" + - + asm_text: "lsrs.w r7, r7, #5" + - + asm_text: "lsr.w r12, r12, #0x15" + - + asm_text: "lsrs r1, r2, #1" + - + asm_text: "itt eq" + - + asm_text: "lsrseq.w r1, r2, #1" + - + asm_text: "lsreq r1, r2, #1" + - + asm_text: "lsr.w r3, r4, r2" + - + asm_text: "lsr.w r1, r1, r2" + - + asm_text: "lsrs.w r3, r4, r8" + - + asm_text: "mcr p7, #1, r5, c1, c1, #4" + - + asm_text: "mcr2 p7, #1, r5, c1, c1, #4" + - + asm_text: "mcr p14, #0, r4, c0, c5, #0" + - + asm_text: "mcr2 p4, #2, r2, c1, c3, #0" + - + asm_text: "mcr p7, #1, r5, c1, c1, #4" + - + asm_text: "mcr2 p7, #1, r5, c1, c1, #4" + - + asm_text: "mcr p14, #0, r4, c0, c5, #0" + - + asm_text: "mcr2 p4, #2, r2, c1, c3, #0" + - + asm_text: "mcrr p7, #0xf, r5, r4, c1" + - + asm_text: "mcrr2 p7, #0xf, r5, r4, c1" + - + asm_text: "mcrr p7, #0xf, r5, r4, c1" + - + asm_text: "mcrr2 p7, #0xf, r5, r4, c1" + - + asm_text: "mla r1, r2, r3, r4" + - + asm_text: "mls r1, r2, r3, r4" + - + asm_text: "movs r1, #0x15" + - + asm_text: "movs.w r1, #0x15" + - + asm_text: "movs.w r8, #0x15" + - + asm_text: "movw r0, #0xffff" + - + asm_text: "movw r1, #0xab01" + - + asm_text: "movw r1, #0xab10" + - + asm_text: "mov.w r0, #0x3fc0000" + - + asm_text: "mov.w r0, #0x3fc0000" + - + asm_text: "movs.w r0, #0x3fc0000" + - + asm_text: "itte eq" + - + asm_text: "movseq.w r1, #0xc" + - + asm_text: "moveq r1, #0xc" + - + asm_text: "movne.w r1, #0xc" + - + asm_text: "mov.w r6, #0x1c2" + - + asm_text: "it lo" + - + asm_text: "movlo.w r1, #-1" + - + asm_text: "mvn r3, #2" + - + asm_text: "movw r11, #0xabcd" + - + asm_text: "movs r0, #1" + - + asm_text: "it ne" + - + asm_text: "movne r3, #0xf" + - + asm_text: "itt eq" + - + asm_text: "moveq r0, #0xff" + - + asm_text: "movweq r1, #0x100" + - + asm_text: "lsl.w r6, r2, #0x10" + - + asm_text: "lsl.w r6, r2, #0x10" + - + asm_text: "lsr.w r6, r2, #0x10" + - + asm_text: "lsr.w r6, r2, #0x10" + - + asm_text: "asrs r6, r2, #0x20" + - + asm_text: "asrs.w r6, r2, #0x20" + - + asm_text: "rors.w r6, r2, #5" + - + asm_text: "rors.w r6, r2, #5" + - + asm_text: "lsls r4, r5" + - + asm_text: "lsls.w r4, r4, r5" + - + asm_text: "lsrs r4, r5" + - + asm_text: "lsrs.w r4, r4, r5" + - + asm_text: "asrs r4, r5" + - + asm_text: "asrs.w r4, r4, r5" + - + asm_text: "rors r4, r5" + - + asm_text: "rors.w r4, r4, r5" + - + asm_text: "lsl.w r4, r4, r5" + - + asm_text: "rors.w r4, r4, r8" + - + asm_text: "lsrs.w r4, r5, r6" + - + asm_text: "itttt eq" + - + asm_text: "lsleq r4, r5" + - + asm_text: "lsreq r4, r5" + - + asm_text: "asreq r4, r5" + - + asm_text: "roreq r4, r5" + - + asm_text: "rrx r4, r4" + - + asm_text: "movt r3, #7" + - + asm_text: "movt r6, #0xffff" + - + asm_text: "it eq" + - + asm_text: "movteq r4, #0xff0" + - + asm_text: "mrc p14, #0, r1, c1, c2, #4" + - + asm_text: "mrc p15, #7, apsr_nzcv, c15, c6, #6" + - + asm_text: "mrc p9, #1, r1, c2, c2, #0" + - + asm_text: "mrc2 p12, #3, r3, c3, c4, #0" + - + asm_text: "mrc2 p14, #0, r1, c1, c2, #4" + - + asm_text: "mrc2 p8, #7, apsr_nzcv, c15, c0, #1" + - + asm_text: "mrc p14, #0, r1, c1, c2, #4" + - + asm_text: "mrc p15, #7, apsr_nzcv, c15, c6, #6" + - + asm_text: "mrc p9, #1, r1, c2, c2, #0" + - + asm_text: "mrc2 p12, #3, r3, c3, c4, #0" + - + asm_text: "mrc2 p14, #0, r1, c1, c2, #4" + - + asm_text: "mrc2 p8, #7, apsr_nzcv, c15, c0, #1" + - + asm_text: "mrrc p7, #1, r5, r4, c1" + - + asm_text: "mrrc2 p7, #1, r5, r4, c1" + - + asm_text: "mrrc p7, #1, r5, r4, c1" + - + asm_text: "mrrc2 p7, #1, r5, r4, c1" + - + asm_text: "mrs r8, apsr" + - + asm_text: "mrs r8, apsr" + - + asm_text: "mrs r8, spsr" + - + asm_text: "msr apsr_nzcvq, r1" + - + asm_text: "msr apsr_g, r2" + - + asm_text: "msr apsr_nzcvq, r3" + - + asm_text: "msr apsr_nzcvq, r4" + - + asm_text: "msr apsr_nzcvqg, r5" + - + asm_text: "msr cpsr_fc, r6" + - + asm_text: "msr cpsr_c, r7" + - + asm_text: "msr cpsr_x, r8" + - + asm_text: "msr cpsr_fc, r9" + - + asm_text: "msr cpsr_fc, r11" + - + asm_text: "msr cpsr_fsx, r12" + - + asm_text: "msr spsr_fc, r0" + - + asm_text: "msr spsr_fsxc, r5" + - + asm_text: "msr cpsr_fsxc, r8" + - + asm_text: "msr cpsr_fc, r3" + - + asm_text: "muls r3, r4, r3" + - + asm_text: "mul r3, r4, r3" + - + asm_text: "mul r3, r4, r6" + - + asm_text: "it eq" + - + asm_text: "muleq r3, r4, r5" + - + asm_text: "it le" + - + asm_text: "mulle r4, r4, r8" + - + asm_text: "mul r5, r6, r5" + - + asm_text: "mvns r8, #0x15" + - + asm_text: "mvn r0, #0x3fc0000" + - + asm_text: "mvns r0, #0x3fc0000" + - + asm_text: "itte eq" + - + asm_text: "mvnseq r1, #0xc" + - + asm_text: "mvneq r1, #0xc" + - + asm_text: "mvnne r1, #0xc" + - + asm_text: "mvn.w r2, r3" + - + asm_text: "mvns r2, r3" + - + asm_text: "mvn.w r5, r6, lsl #0x13" + - + asm_text: "mvn.w r5, r6, lsr #0x9" + - + asm_text: "mvn.w r5, r6, asr #4" + - + asm_text: "mvn.w r5, r6, ror #6" + - + asm_text: "mvn.w r5, r6, rrx" + - + asm_text: "it eq" + - + asm_text: "mvneq r2, r3" + - + asm_text: "rsb.w r5, r2, #0" + - + asm_text: "rsb.w r5, r8, #0" + - + asm_text: "nop.w" + - + asm_text: "orn r4, r5, #0xf000" + - + asm_text: "orn r4, r5, #0xf000" + - + asm_text: "orn r4, r5, r6" + - + asm_text: "orn r4, r5, r6" + - + asm_text: "orns r4, r5, r6" + - + asm_text: "orns r4, r5, r6" + - + asm_text: "orn r4, r5, r6, lsl #5" + - + asm_text: "orn r4, r5, r6, lsl #5" + - + asm_text: "orns r4, r5, r6, lsr #5" + - + asm_text: "orn r4, r5, r6, lsr #5" + - + asm_text: "orns r4, r5, r6, asr #5" + - + asm_text: "orn r4, r5, r6, ror #5" + - + asm_text: "orr r4, r5, #0xf000" + - + asm_text: "orr.w r4, r5, r6" + - + asm_text: "orr.w r4, r5, r6, lsl #5" + - + asm_text: "orrs.w r4, r5, r6, lsr #5" + - + asm_text: "orr.w r4, r5, r6, lsr #5" + - + asm_text: "orrs.w r4, r5, r6, asr #5" + - + asm_text: "orr.w r4, r5, r6, ror #5" + - + asm_text: "pkhbt r2, r2, r3" + - + asm_text: "pkhbt r2, r2, r3, lsl #0x1f" + - + asm_text: "pkhbt r2, r2, r3" + - + asm_text: "pkhbt r2, r2, r3, lsl #0xf" + - + asm_text: "pkhbt r2, r3, r2" + - + asm_text: "pkhtb r2, r2, r3, asr #0x1f" + - + asm_text: "pkhtb r2, r2, r3, asr #0xf" + - + asm_text: "pld [r5, #-4]" + - + asm_text: "pld [r6, #0x20]" + - + asm_text: "pld [r6, #0x21]" + - + asm_text: "pld [r6, #0x101]" + - + asm_text: "pld [r7, #0x101]" + - + asm_text: "pld [r1]" + - + asm_text: "pld [r1, #-0]" + - + asm_text: "pld [r1, #-0]" + - + asm_text: "pld [pc, #-0xfff]" + - + asm_text: "pld [pc, #-0xfff]" + - + asm_text: "pld [r8, r1]" + - + asm_text: "pld [r5, r2]" + - + asm_text: "pld [r5, r2]" + - + asm_text: "pld [r0, r2, lsl #3]" + - + asm_text: "pld [r8, r2, lsl #2]" + - + asm_text: "pld [sp, r2, lsl #1]" + - + asm_text: "pld [sp, r2]" + - + asm_text: "pld [sp, r2, lsl #1]" + - + asm_text: "pli [r5, #-4]" + - + asm_text: "pli [r6, #0x20]" + - + asm_text: "pli [r6, #0x21]" + - + asm_text: "pli [r6, #0x101]" + - + asm_text: "pli [r7, #0x101]" + - + asm_text: "pli [pc, #0xfff]" + - + asm_text: "pli [pc, #-0xfff]" + - + asm_text: "pli [pc, #-0xfff]" + - + asm_text: "pli [r8, r1]" + - + asm_text: "pli [r5, r2]" + - + asm_text: "pli [r5, r2]" + - + asm_text: "pli [r0, r2, lsl #3]" + - + asm_text: "pli [r8, r2, lsl #2]" + - + asm_text: "pli [sp, r2, lsl #1]" + - + asm_text: "pli [sp, r2]" + - + asm_text: "pli [sp, r2, lsl #1]" + - + asm_text: "pop.w {r2, r9}" + - + asm_text: "push.w {r2, r9}" + - + asm_text: "qadd r1, r2, r3" + - + asm_text: "qadd16 r1, r2, r3" + - + asm_text: "qadd8 r1, r2, r3" + - + asm_text: "itte gt" + - + asm_text: "qaddgt r1, r2, r3" + - + asm_text: "qadd16gt r1, r2, r3" + - + asm_text: "qadd8le r1, r2, r3" + - + asm_text: "qdadd r6, r7, r8" + - + asm_text: "qdsub r6, r7, r8" + - + asm_text: "itt hi" + - + asm_text: "qdaddhi r6, r7, r8" + - + asm_text: "qdsubhi r6, r7, r8" + - + asm_text: "qsax r9, r12, r0" + - + asm_text: "it eq" + - + asm_text: "qsaxeq r9, r12, r0" + - + asm_text: "qsub r1, r2, r3" + - + asm_text: "qsub16 r1, r2, r3" + - + asm_text: "qsub8 r1, r2, r3" + - + asm_text: "itet le" + - + asm_text: "qsuble r1, r2, r3" + - + asm_text: "qsub16gt r1, r2, r3" + - + asm_text: "qsub8le r1, r2, r3" + - + asm_text: "rbit r1, r2" + - + asm_text: "it ne" + - + asm_text: "rbitne r1, r2" + - + asm_text: "rev.w r1, r2" + - + asm_text: "rev.w r2, r8" + - + asm_text: "itt ne" + - + asm_text: "revne r1, r2" + - + asm_text: "revne.w r1, r8" + - + asm_text: "rev16.w r1, r2" + - + asm_text: "rev16.w r2, r8" + - + asm_text: "itt ne" + - + asm_text: "rev16ne r1, r2" + - + asm_text: "rev16ne.w r1, r8" + - + asm_text: "revsh.w r1, r2" + - + asm_text: "revsh.w r2, r8" + - + asm_text: "itt ne" + - + asm_text: "revshne r1, r2" + - + asm_text: "revshne.w r1, r8" + - + asm_text: "ror.w r2, r3, #0xc" + - + asm_text: "rors.w r8, r3, #0x1f" + - + asm_text: "rors.w r2, r3, #1" + - + asm_text: "ror.w r2, r3, #4" + - + asm_text: "rors.w r2, r12, #0xf" + - + asm_text: "ror.w r3, r3, #0x13" + - + asm_text: "rors.w r8, r8, #2" + - + asm_text: "rors.w r7, r7, #5" + - + asm_text: "ror.w r12, r12, #0x15" + - + asm_text: "ror.w r3, r4, r2" + - + asm_text: "ror.w r1, r1, r2" + - + asm_text: "rors.w r3, r4, r8" + - + asm_text: "rrx r1, r2" + - + asm_text: "rrxs r1, r2" + - + asm_text: "ite lt" + - + asm_text: "rrxlt r9, r12" + - + asm_text: "rrxsge r8, r3" + - + asm_text: "rsb.w r2, r5, #0xff000" + - + asm_text: "rsbs.w r3, r12, #0xf" + - + asm_text: "rsb.w r1, r1, #0xff" + - + asm_text: "rsb.w r1, r1, #0xff" + - + asm_text: "rsb.w r11, r11, #0" + - + asm_text: "rsb.w r9, r9, #0" + - + asm_text: "rsbs r3, r1, #0" + - + asm_text: "rsb.w r3, r1, #0" + - + asm_text: "rsb r4, r4, r8" + - + asm_text: "rsb r4, r4, r8" + - + asm_text: "rsb r4, r9, r8" + - + asm_text: "rsb r4, r9, r8" + - + asm_text: "rsb r1, r4, r8, asr #3" + - + asm_text: "rsb r1, r4, r8, asr #3" + - + asm_text: "rsbs r2, r1, r7, lsl #1" + - + asm_text: "rsbs r2, r1, r7, lsl #1" + - + asm_text: "rsbs r0, r1, r2" + - + asm_text: "rsbs r0, r1, r2" + - + asm_text: "sadd16 r3, r4, r8" + - + asm_text: "it ne" + - + asm_text: "sadd16ne r3, r4, r8" + - + asm_text: "sadd8 r3, r4, r8" + - + asm_text: "it ne" + - + asm_text: "sadd8ne r3, r4, r8" + - + asm_text: "sasx r9, r2, r7" + - + asm_text: "it ne" + - + asm_text: "sasxne r2, r5, r6" + - + asm_text: "sasx r9, r2, r7" + - + asm_text: "it ne" + - + asm_text: "sasxne r2, r5, r6" + - + asm_text: "sbc r0, r1, #4" + - + asm_text: "sbcs r0, r1, #0" + - + asm_text: "sbc r1, r2, #0xff" + - + asm_text: "sbc r3, r7, #0x550055" + - + asm_text: "sbc r8, r12, #0xaa00aa00" + - + asm_text: "sbc r9, r7, #0xa5a5a5a5" + - + asm_text: "sbc r5, r3, #0x87000000" + - + asm_text: "sbc r4, r2, #0x7f800000" + - + asm_text: "sbc r4, r2, #0x680" + - + asm_text: "sbc.w r4, r5, r6" + - + asm_text: "sbcs.w r4, r5, r6" + - + asm_text: "sbc.w r9, r1, r3" + - + asm_text: "sbcs.w r9, r1, r3" + - + asm_text: "sbc.w r0, r1, r3, ror #4" + - + asm_text: "sbcs.w r0, r1, r3, lsl #7" + - + asm_text: "sbc.w r0, r1, r3, lsr #0x1f" + - + asm_text: "sbcs.w r0, r1, r3, asr #0x20" + - + asm_text: "sbfx r4, r5, #0x10, #1" + - + asm_text: "it gt" + - + asm_text: "sbfxgt r4, r5, #0x10, #0x10" + - + asm_text: "sel r5, r9, r2" + - + asm_text: "it le" + - + asm_text: "selle r5, r9, r2" + - + asm_text: "sev.w" + - + asm_text: "it eq" + - + asm_text: "seveq.w" + - + asm_text: "sadd16 r1, r2, r3" + - + asm_text: "sadd8 r1, r2, r3" + - + asm_text: "ite gt" + - + asm_text: "sadd16gt r1, r2, r3" + - + asm_text: "sadd8le r1, r2, r3" + - + asm_text: "shasx r4, r8, r2" + - + asm_text: "it gt" + - + asm_text: "shasxgt r4, r8, r2" + - + asm_text: "shasx r4, r8, r2" + - + asm_text: "it gt" + - + asm_text: "shasxgt r4, r8, r2" + - + asm_text: "shsax r4, r8, r2" + - + asm_text: "it gt" + - + asm_text: "shsaxgt r4, r8, r2" + - + asm_text: "shsax r4, r8, r2" + - + asm_text: "it gt" + - + asm_text: "shsaxgt r4, r8, r2" + - + asm_text: "shsub16 r4, r8, r2" + - + asm_text: "shsub8 r4, r8, r2" + - + asm_text: "itt gt" + - + asm_text: "shsub16gt r4, r8, r2" + - + asm_text: "shsub8gt r4, r8, r2" + - + asm_text: "smlabb r3, r1, r9, r0" + - + asm_text: "smlabt r5, r6, r4, r1" + - + asm_text: "smlatb r4, r2, r3, r2" + - + asm_text: "smlatt r8, r3, r8, r4" + - + asm_text: "itete gt" + - + asm_text: "smlabbgt r3, r1, r9, r0" + - + asm_text: "smlabtle r5, r6, r4, r1" + - + asm_text: "smlatbgt r4, r2, r3, r2" + - + asm_text: "smlattle r8, r3, r8, r4" + - + asm_text: "smlad r2, r3, r5, r8" + - + asm_text: "smladx r2, r3, r5, r8" + - + asm_text: "itt hi" + - + asm_text: "smladhi r2, r3, r5, r8" + - + asm_text: "smladxhi r2, r3, r5, r8" + - + asm_text: "smlal r2, r3, r5, r8" + - + asm_text: "it eq" + - + asm_text: "smlaleq r2, r3, r5, r8" + - + asm_text: "smlalbb r3, r1, r9, r0" + - + asm_text: "smlalbt r5, r6, r4, r1" + - + asm_text: "smlaltb r4, r2, r3, r2" + - + asm_text: "smlaltt r8, r3, r8, r4" + - + asm_text: "iteet ge" + - + asm_text: "smlalbbge r3, r1, r9, r0" + - + asm_text: "smlalbtlt r5, r6, r4, r1" + - + asm_text: "smlaltblt r4, r2, r3, r2" + - + asm_text: "smlalttge r8, r3, r8, r4" + - + asm_text: "smlald r2, r3, r5, r8" + - + asm_text: "smlaldx r2, r3, r5, r8" + - + asm_text: "ite eq" + - + asm_text: "smlaldeq r2, r3, r5, r8" + - + asm_text: "smlaldxne r2, r3, r5, r8" + - + asm_text: "smlawb r2, r3, r10, r8" + - + asm_text: "smlawt r8, r3, r5, r9" + - + asm_text: "ite eq" + - + asm_text: "smlawbeq r2, r7, r5, r8" + - + asm_text: "smlawtne r1, r3, r0, r8" + - + asm_text: "smlsd r2, r3, r5, r8" + - + asm_text: "smlsdx r2, r3, r5, r8" + - + asm_text: "ite le" + - + asm_text: "smlsdle r2, r3, r5, r8" + - + asm_text: "smlsdxgt r2, r3, r5, r8" + - + asm_text: "smlsld r2, r9, r5, r1" + - + asm_text: "smlsldx r4, r11, r2, r8" + - + asm_text: "ite ge" + - + asm_text: "smlsldge r8, r2, r5, r6" + - + asm_text: "smlsldxlt r1, r0, r3, r8" + - + asm_text: "smmla r1, r2, r3, r4" + - + asm_text: "smmlar r4, r3, r2, r1" + - + asm_text: "ite lo" + - + asm_text: "smmlalo r1, r2, r3, r4" + - + asm_text: "smmlarhs r4, r3, r2, r1" + - + asm_text: "smmls r1, r2, r3, r4" + - + asm_text: "smmlsr r4, r3, r2, r1" + - + asm_text: "ite lo" + - + asm_text: "smmlslo r1, r2, r3, r4" + - + asm_text: "smmlsrhs r4, r3, r2, r1" + - + asm_text: "smmul r2, r3, r4" + - + asm_text: "smmulr r3, r2, r1" + - + asm_text: "ite lo" + - + asm_text: "smmullo r2, r3, r4" + - + asm_text: "smmulrhs r3, r2, r1" + - + asm_text: "smuad r2, r3, r4" + - + asm_text: "smuadx r3, r2, r1" + - + asm_text: "ite lt" + - + asm_text: "smuadlt r2, r3, r4" + - + asm_text: "smuadxge r3, r2, r1" + - + asm_text: "smulbb r3, r9, r0" + - + asm_text: "smulbt r5, r4, r1" + - + asm_text: "smultb r4, r2, r2" + - + asm_text: "smultt r8, r3, r4" + - + asm_text: "itete ge" + - + asm_text: "smulbbge r1, r9, r0" + - + asm_text: "smulbtlt r5, r6, r4" + - + asm_text: "smultbge r2, r3, r2" + - + asm_text: "smulttlt r8, r3, r4" + - + asm_text: "smull r3, r9, r0, r1" + - + asm_text: "it eq" + - + asm_text: "smulleq r8, r3, r4, r5" + - + asm_text: "smulwb r3, r9, r0" + - + asm_text: "smulwt r3, r9, r2" + - + asm_text: "ite gt" + - + asm_text: "smulwbgt r3, r9, r0" + - + asm_text: "smulwtle r3, r9, r2" + - + asm_text: "smusd r3, r0, r1" + - + asm_text: "smusdx r3, r9, r2" + - + asm_text: "ite eq" + - + asm_text: "smusdeq r8, r3, r2" + - + asm_text: "smusdxne r7, r4, r3" + - + asm_text: "srsdb sp, #1" + - + asm_text: "srsia sp, #0" + - + asm_text: "srsdb sp!, #0x13" + - + asm_text: "srsia sp!, #2" + - + asm_text: "srsia sp, #0xa" + - + asm_text: "srsdb sp, #0x9" + - + asm_text: "srsia sp!, #5" + - + asm_text: "srsdb sp!, #5" + - + asm_text: "srsia sp, #5" + - + asm_text: "srsia sp!, #5" + - + asm_text: "srsdb sp, #1" + - + asm_text: "srsia sp, #0" + - + asm_text: "srsdb sp!, #0x13" + - + asm_text: "srsia sp!, #2" + - + asm_text: "srsia sp, #0xa" + - + asm_text: "srsdb sp, #0x9" + - + asm_text: "srsia sp!, #5" + - + asm_text: "srsdb sp!, #5" + - + asm_text: "srsia sp, #5" + - + asm_text: "srsia sp!, #5" + - + asm_text: "ssat r8, #1, r10" + - + asm_text: "ssat r8, #1, r10" + - + asm_text: "ssat r8, #1, r10, lsl #0x1f" + - + asm_text: "ssat r8, #1, r10, asr #1" + - + asm_text: "ssat16 r2, #1, r7" + - + asm_text: "ssat16 r3, #0x10, r5" + - + asm_text: "ssax r2, r3, r4" + - + asm_text: "it lt" + - + asm_text: "ssaxlt r2, r3, r4" + - + asm_text: "ssax r2, r3, r4" + - + asm_text: "it lt" + - + asm_text: "ssaxlt r2, r3, r4" + - + asm_text: "ssub16 r1, r0, r6" + - + asm_text: "ssub8 r9, r2, r4" + - + asm_text: "ite ne" + - + asm_text: "ssub16ne r5, r3, r2" + - + asm_text: "ssub8eq r5, r1, r2" + - + asm_text: "stc2 p0, c8, [r1, #4]" + - + asm_text: "stc2 p1, c7, [r2]" + - + asm_text: "stc2 p2, c6, [r3, #-0xe0]" + - + asm_text: "stc2 p3, c5, [r4, #-0x78]!" + - + asm_text: "stc2 p4, c4, [r5], #0x10" + - + asm_text: "stc2 p5, c3, [r6], #-0x48" + - + asm_text: "stc2l p6, c2, [r7, #4]" + - + asm_text: "stc2l p7, c1, [r8]" + - + asm_text: "stc2l p8, c0, [r9, #-0xe0]" + - + asm_text: "stc2l p9, c1, [r10, #-0x78]!" + - + asm_text: "stc2l p0, c2, [r11], #0x10" + - + asm_text: "stc2l p1, c3, [r12], #-0x48" + - + asm_text: "stc p12, c4, [r0, #4]" + - + asm_text: "stc p13, c5, [r1]" + - + asm_text: "stc p14, c6, [r2, #-0xe0]" + - + asm_text: "stc p15, c7, [r3, #-0x78]!" + - + asm_text: "stc p5, c8, [r4], #0x10" + - + asm_text: "stc p4, c9, [r5], #-0x48" + - + asm_text: "stcl p3, c10, [r6, #4]" + - + asm_text: "stcl p2, c11, [r7]" + - + asm_text: "stcl p1, c12, [r8, #-0xe0]" + - + asm_text: "stcl p0, c13, [r9, #-0x78]!" + - + asm_text: "stcl p6, c14, [r10], #0x10" + - + asm_text: "stcl p7, c15, [r11], #-0x48" + - + asm_text: "stc2 p2, c8, [r1], {25}" + - + asm_text: "stm.w r4, {r4, r5, r8, r9}" + - + asm_text: "stm.w r4, {r5, r6}" + - + asm_text: "stm.w r5!, {r3, r8}" + - + asm_text: "stm.w r4, {r4, r5, r8, r9}" + - + asm_text: "stm.w r4, {r5, r6}" + - + asm_text: "stm.w r5!, {r3, r8}" + - + asm_text: "stm.w r5!, {r1, r2}" + - + asm_text: "stm.w r2, {r1, r2}" + - + asm_text: "stm.w r4, {r4, r5, r8, r9}" + - + asm_text: "stm.w r4, {r5, r6}" + - + asm_text: "stm.w r5!, {r3, r8}" + - + asm_text: "stm.w r4, {r4, r5, r8, r9}" + - + asm_text: "stm.w r4, {r5, r6}" + - + asm_text: "stm.w r5!, {r3, r8}" + - + asm_text: "stm.w r5!, {r3, r8}" + - + asm_text: "stmdb r4, {r4, r5, r8, r9}" + - + asm_text: "stmdb r4, {r5, r6}" + - + asm_text: "stmdb r5!, {r3, r8}" + - + asm_text: "stm.w r5!, {r3, r8}" + - + asm_text: "stmdb r5, {r0, r1}" + - + asm_text: "str r5, [r5, #-4]" + - + asm_text: "str r5, [r6, #0x20]" + - + asm_text: "str.w r5, [r6, #0x21]" + - + asm_text: "str.w r5, [r6, #0x101]" + - + asm_text: "str.w pc, [r7, #0x101]" + - + asm_text: "str r2, [r4, #0xff]!" + - + asm_text: "str r8, [sp, #4]!" + - + asm_text: "str lr, [sp, #-4]!" + - + asm_text: "str r2, [r4], #0xff" + - + asm_text: "str r8, [sp], #4" + - + asm_text: "str lr, [sp], #-4" + - + asm_text: "str.w r1, [r8, r1]" + - + asm_text: "str.w r4, [r5, r2]" + - + asm_text: "str.w r6, [r0, r2, lsl #3]" + - + asm_text: "str.w r8, [r8, r2, lsl #2]" + - + asm_text: "str.w r7, [sp, r2, lsl #1]" + - + asm_text: "str.w r7, [sp, r2]" + - + asm_text: "strb r5, [r5, #-4]" + - + asm_text: "strb.w r5, [r6, #0x20]" + - + asm_text: "strb.w r5, [r6, #0x21]" + - + asm_text: "strb.w r5, [r6, #0x101]" + - + asm_text: "strb.w lr, [r7, #0x101]" + - + asm_text: "strb r5, [r8, #0xff]!" + - + asm_text: "strb r2, [r5, #4]!" + - + asm_text: "strb r1, [r4, #-4]!" + - + asm_text: "strb lr, [r3], #0xff" + - + asm_text: "strb r9, [r2], #4" + - + asm_text: "strb r3, [sp], #-4" + - + asm_text: "strb r4, [r8, #-0]!" + - + asm_text: "strb r1, [r0], #-0" + - + asm_text: "strb.w r1, [r8, r1]" + - + asm_text: "strb.w r4, [r5, r2]" + - + asm_text: "strb.w r6, [r0, r2, lsl #3]" + - + asm_text: "strb.w r8, [r8, r2, lsl #2]" + - + asm_text: "strb.w r7, [sp, r2, lsl #1]" + - + asm_text: "strb.w r7, [sp, r2]" + - + asm_text: "strbt r1, [r2]" + - + asm_text: "strbt r1, [r8]" + - + asm_text: "strbt r1, [r8, #3]" + - + asm_text: "strbt r1, [r8, #0xff]" + - + asm_text: "strd r3, r5, [r6, #0x18]" + - + asm_text: "strd r3, r5, [r6, #0x18]!" + - + asm_text: "strd r3, r5, [r6], #4" + - + asm_text: "strd r3, r5, [r6], #-8" + - + asm_text: "strd r3, r5, [r6]" + - + asm_text: "strd r8, r1, [r3]" + - + asm_text: "strd r0, r1, [r2, #-0]" + - + asm_text: "strd r0, r1, [r2, #-0]!" + - + asm_text: "strd r0, r1, [r2], #-0" + - + asm_text: "strd r0, r1, [r2, #0x100]" + - + asm_text: "strd r0, r1, [r2, #0x100]!" + - + asm_text: "strd r0, r1, [r2], #0x100" + - + asm_text: "strex r1, r8, [r4]" + - + asm_text: "strex r8, r2, [r4]" + - + asm_text: "strex r2, r12, [sp, #0x80]" + - + asm_text: "strexb r5, r1, [r7]" + - + asm_text: "strexh r9, r7, [r12]" + - + asm_text: "strexd r9, r3, r6, [r4]" + - + asm_text: "strh r5, [r5, #-4]" + - + asm_text: "strh r5, [r6, #0x20]" + - + asm_text: "strh.w r5, [r6, #0x21]" + - + asm_text: "strh.w r5, [r6, #0x101]" + - + asm_text: "strh.w lr, [r7, #0x101]" + - + asm_text: "strh r5, [r8, #0xff]!" + - + asm_text: "strh r2, [r5, #4]!" + - + asm_text: "strh r1, [r4, #-4]!" + - + asm_text: "strh lr, [r3], #0xff" + - + asm_text: "strh r9, [r2], #4" + - + asm_text: "strh r3, [sp], #-4" + - + asm_text: "strh.w r1, [r8, r1]" + - + asm_text: "strh.w r4, [r5, r2]" + - + asm_text: "strh.w r6, [r0, r2, lsl #3]" + - + asm_text: "strh.w r8, [r8, r2, lsl #2]" + - + asm_text: "strh.w r7, [sp, r2, lsl #1]" + - + asm_text: "strh.w r7, [sp, r2]" + - + asm_text: "strht r1, [r2]" + - + asm_text: "strht r1, [r8]" + - + asm_text: "strht r1, [r8, #3]" + - + asm_text: "strht r1, [r8, #0xff]" + - + asm_text: "strt r1, [r2]" + - + asm_text: "strt r1, [r8]" + - + asm_text: "strt r1, [r8, #3]" + - + asm_text: "strt r1, [r8, #0xff]" + - + asm_text: "itet eq" + - + asm_text: "subeq r1, r2, #4" + - + asm_text: "subwne r5, r3, #0x3ff" + - + asm_text: "subweq r4, r5, #0x125" + - + asm_text: "sub.w r2, sp, #0x400" + - + asm_text: "sub.w r2, r8, #0xff00" + - + asm_text: "subw r2, r3, #0x101" + - + asm_text: "subw r2, r3, #0x101" + - + asm_text: "sub.w r12, r6, #0x100" + - + asm_text: "subw r12, r6, #0x100" + - + asm_text: "subs.w r1, r2, #0x1f0" + - + asm_text: "sub.w r2, r2, #1" + - + asm_text: "sub.w r0, r0, #0x20" + - + asm_text: "subs r2, #0x38" + - + asm_text: "subs r2, #0x38" + - + asm_text: "sub.w r4, r5, r6" + - + asm_text: "sub.w r4, r5, r6, lsl #5" + - + asm_text: "sub.w r4, r5, r6, lsr #5" + - + asm_text: "sub.w r4, r5, r6, lsr #5" + - + asm_text: "sub.w r4, r5, r6, asr #5" + - + asm_text: "sub.w r4, r5, r6, ror #5" + - + asm_text: "sub.w r5, r2, r12, rrx" + - + asm_text: "sub.w r2, sp, r12" + - + asm_text: "sub.w sp, sp, r12" + - + asm_text: "sub.w sp, sp, r12" + - + asm_text: "sub.w r2, sp, r12" + - + asm_text: "sub.w sp, sp, r12" + - + asm_text: "sub.w sp, sp, r12" + - + asm_text: "svc #0" + - + asm_text: "it eq" + - + asm_text: "svceq #0xff" + - + asm_text: "it ne" + - + asm_text: "svcne #0x21" + - + asm_text: "itt eq" + - + asm_text: "svceq #0" + - + asm_text: "svceq #1" + - + asm_text: "sxtab r2, r3, r4" + - + asm_text: "sxtab r4, r5, r6" + - + asm_text: "it lt" + - + asm_text: "sxtablt r6, r2, r9, ror #8" + - + asm_text: "sxtab r5, r1, r4, ror #0x10" + - + asm_text: "sxtab r7, r8, r3, ror #0x18" + - + asm_text: "sxtab16 r6, r2, r7" + - + asm_text: "sxtab16 r3, r5, r8, ror #8" + - + asm_text: "sxtab16 r3, r2, r1, ror #0x10" + - + asm_text: "ite ne" + - + asm_text: "sxtab16ne r0, r1, r4" + - + asm_text: "sxtab16eq r1, r2, r3, ror #0x18" + - + asm_text: "sxtah r1, r3, r9" + - + asm_text: "sxtah r3, r8, r3, ror #8" + - + asm_text: "sxtah r9, r3, r3, ror #0x18" + - + asm_text: "ite hi" + - + asm_text: "sxtahhi r6, r1, r6" + - + asm_text: "sxtahls r2, r2, r4, ror #0x10" + - + asm_text: "sxtb r5, r6" + - + asm_text: "sxtb.w r6, r9, ror #8" + - + asm_text: "sxtb.w r8, r3, ror #0x18" + - + asm_text: "ite ge" + - + asm_text: "sxtbge r2, r4" + - + asm_text: "sxtblt.w r5, r1, ror #0x10" + - + asm_text: "sxtb.w r7, r8" + - + asm_text: "sxtb16 r1, r4" + - + asm_text: "sxtb16 r6, r7" + - + asm_text: "sxtb16 r3, r1, ror #0x10" + - + asm_text: "ite hs" + - + asm_text: "sxtb16hs r3, r5, ror #8" + - + asm_text: "sxtb16lo r2, r3, ror #0x18" + - + asm_text: "sxth r1, r6" + - + asm_text: "sxth.w r3, r8, ror #8" + - + asm_text: "sxth.w r9, r3, ror #0x18" + - + asm_text: "itt ne" + - + asm_text: "sxthne.w r3, r9" + - + asm_text: "sxthne.w r2, r2, ror #0x10" + - + asm_text: "sxth.w r7, r8" + - + asm_text: "sxtb r5, r6" + - + asm_text: "sxtb.w r6, r9, ror #8" + - + asm_text: "sxtb.w r8, r3, ror #0x18" + - + asm_text: "ite ge" + - + asm_text: "sxtbge r2, r4" + - + asm_text: "sxtblt.w r5, r1, ror #0x10" + - + asm_text: "sxtb16 r1, r4" + - + asm_text: "sxtb16 r6, r7" + - + asm_text: "sxtb16 r3, r1, ror #0x10" + - + asm_text: "ite hs" + - + asm_text: "sxtb16hs r3, r5, ror #8" + - + asm_text: "sxtb16lo r2, r3, ror #0x18" + - + asm_text: "sxth r1, r6" + - + asm_text: "sxth.w r3, r8, ror #8" + - + asm_text: "sxth.w r9, r3, ror #0x18" + - + asm_text: "itt ne" + - + asm_text: "sxthne.w r3, r9" + - + asm_text: "sxthne.w r2, r2, ror #0x10" + - + asm_text: "tbb [r3, r8]" + - + asm_text: "tbh [r3, r8, lsl #1]" + - + asm_text: "it eq" + - + asm_text: "tbbeq [r3, r8]" + - + asm_text: "it hs" + - + asm_text: "tbhhs [r3, r8, lsl #1]" + - + asm_text: "teq.w r5, #0xf000" + - + asm_text: "teq.w r4, r5" + - + asm_text: "teq.w r4, r5, lsl #5" + - + asm_text: "teq.w r4, r5, lsr #5" + - + asm_text: "teq.w r4, r5, lsr #5" + - + asm_text: "teq.w r4, r5, asr #5" + - + asm_text: "teq.w r4, r5, ror #5" + - + asm_text: "tst.w r5, #0xf000" + - + asm_text: "tst r2, r5" + - + asm_text: "tst.w r3, r12, lsl #5" + - + asm_text: "tst.w r4, r11, lsr #4" + - + asm_text: "tst.w r5, r10, lsr #0xc" + - + asm_text: "tst.w r6, r9, asr #0x1e" + - + asm_text: "tst.w r7, r8, ror #2" + - + asm_text: "uadd16 r1, r2, r3" + - + asm_text: "uadd8 r1, r2, r3" + - + asm_text: "ite gt" + - + asm_text: "uadd16gt r1, r2, r3" + - + asm_text: "uadd8le r1, r2, r3" + - + asm_text: "uasx r9, r12, r0" + - + asm_text: "it eq" + - + asm_text: "uasxeq r9, r12, r0" + - + asm_text: "uasx r9, r12, r0" + - + asm_text: "it eq" + - + asm_text: "uasxeq r9, r12, r0" + - + asm_text: "ubfx r4, r5, #0x10, #1" + - + asm_text: "it gt" + - + asm_text: "ubfxgt r4, r5, #0x10, #0x10" + - + asm_text: "uhadd16 r4, r8, r2" + - + asm_text: "uhadd8 r4, r8, r2" + - + asm_text: "itt gt" + - + asm_text: "uhadd16gt r4, r8, r2" + - + asm_text: "uhadd8gt r4, r8, r2" + - + asm_text: "uhasx r4, r1, r5" + - + asm_text: "uhsax r5, r6, r6" + - + asm_text: "itt gt" + - + asm_text: "uhasxgt r6, r9, r8" + - + asm_text: "uhsaxgt r7, r8, r12" + - + asm_text: "uhasx r4, r1, r5" + - + asm_text: "uhsax r5, r6, r6" + - + asm_text: "itt gt" + - + asm_text: "uhasxgt r6, r9, r8" + - + asm_text: "uhsaxgt r7, r8, r12" + - + asm_text: "uhsub16 r5, r8, r3" + - + asm_text: "uhsub8 r1, r7, r6" + - + asm_text: "itt lt" + - + asm_text: "uhsub16lt r4, r9, r12" + - + asm_text: "uhsub8lt r3, r1, r5" + - + asm_text: "umaal r3, r4, r5, r6" + - + asm_text: "it lt" + - + asm_text: "umaallt r3, r4, r5, r6" + - + asm_text: "umlal r2, r4, r6, r8" + - + asm_text: "it gt" + - + asm_text: "umlalgt r6, r1, r2, r6" + - + asm_text: "umull r2, r4, r6, r8" + - + asm_text: "it gt" + - + asm_text: "umullgt r6, r1, r2, r6" + - + asm_text: "uqadd16 r1, r2, r3" + - + asm_text: "uqadd8 r3, r4, r8" + - + asm_text: "ite gt" + - + asm_text: "uqadd16gt r4, r7, r9" + - + asm_text: "uqadd8le r8, r1, r2" + - + asm_text: "uqasx r1, r2, r3" + - + asm_text: "uqsax r3, r4, r8" + - + asm_text: "ite gt" + - + asm_text: "uqasxgt r4, r7, r9" + - + asm_text: "uqsaxle r8, r1, r2" + - + asm_text: "uqasx r1, r2, r3" + - + asm_text: "uqsax r3, r4, r8" + - + asm_text: "ite gt" + - + asm_text: "uqasxgt r4, r7, r9" + - + asm_text: "uqsaxle r8, r1, r2" + - + asm_text: "uqsub8 r8, r2, r9" + - + asm_text: "uqsub16 r1, r9, r7" + - + asm_text: "ite gt" + - + asm_text: "uqsub8gt r3, r1, r6" + - + asm_text: "uqsub16le r4, r6, r4" + - + asm_text: "usad8 r1, r9, r7" + - + asm_text: "usada8 r8, r2, r9, r12" + - + asm_text: "ite gt" + - + asm_text: "usada8gt r3, r1, r6, r9" + - + asm_text: "usad8le r4, r6, r4" + - + asm_text: "usat r8, #1, r10" + - + asm_text: "usat r8, #4, r10" + - + asm_text: "usat r8, #5, r10, lsl #0x1f" + - + asm_text: "usat r8, #0x10, r10, asr #1" + - + asm_text: "usat16 r2, #2, r7" + - + asm_text: "usat16 r3, #0xf, r5" + - + asm_text: "usax r2, r3, r4" + - + asm_text: "it ne" + - + asm_text: "usaxne r6, r1, r9" + - + asm_text: "usax r2, r3, r4" + - + asm_text: "it ne" + - + asm_text: "usaxne r6, r1, r9" + - + asm_text: "usub16 r4, r2, r7" + - + asm_text: "usub8 r1, r8, r5" + - + asm_text: "ite hi" + - + asm_text: "usub16hi r1, r1, r3" + - + asm_text: "usub8ls r9, r2, r3" + - + asm_text: "uxtab r2, r3, r4" + - + asm_text: "uxtab r4, r5, r6" + - + asm_text: "it lt" + - + asm_text: "uxtablt r6, r2, r9, ror #8" + - + asm_text: "uxtab r5, r1, r4, ror #0x10" + - + asm_text: "uxtab r7, r8, r3, ror #0x18" + - + asm_text: "it ge" + - + asm_text: "uxtab16ge r0, r1, r4" + - + asm_text: "uxtab16 r6, r2, r7" + - + asm_text: "uxtab16 r3, r5, r8, ror #8" + - + asm_text: "uxtab16 r3, r2, r1, ror #0x10" + - + asm_text: "it eq" + - + asm_text: "uxtab16eq r1, r2, r3, ror #0x18" + - + asm_text: "uxtah r1, r3, r9" + - + asm_text: "it hi" + - + asm_text: "uxtahhi r6, r1, r6" + - + asm_text: "uxtah r3, r8, r3, ror #8" + - + asm_text: "it lo" + - + asm_text: "uxtahlo r2, r2, r4, ror #0x10" + - + asm_text: "uxtah r9, r3, r3, ror #0x18" + - + asm_text: "it ge" + - + asm_text: "uxtbge r2, r4" + - + asm_text: "uxtb r5, r6" + - + asm_text: "uxtb.w r6, r9, ror #8" + - + asm_text: "it lo" + - + asm_text: "uxtblo.w r5, r1, ror #0x10" + - + asm_text: "uxtb.w r8, r3, ror #0x18" + - + asm_text: "uxtb.w r7, r8" + - + asm_text: "uxtb16 r1, r4" + - + asm_text: "uxtb16 r6, r7" + - + asm_text: "it hs" + - + asm_text: "uxtb16hs r3, r5, ror #8" + - + asm_text: "uxtb16 r3, r1, ror #0x10" + - + asm_text: "it ge" + - + asm_text: "uxtb16ge r2, r3, ror #0x18" + - + asm_text: "it ne" + - + asm_text: "uxthne.w r3, r9" + - + asm_text: "uxth r1, r6" + - + asm_text: "uxth.w r3, r8, ror #8" + - + asm_text: "it le" + - + asm_text: "uxthle.w r2, r2, ror #0x10" + - + asm_text: "uxth.w r9, r3, ror #0x18" + - + asm_text: "uxth.w r7, r8" + - + asm_text: "wfe" + - + asm_text: "wfi" + - + asm_text: "yield" + - + asm_text: "itet lt" + - + asm_text: "wfelt" + - + asm_text: "wfige" + - + asm_text: "yieldlt" + - + asm_text: "sev.w" + - + asm_text: "wfi.w" + - + asm_text: "wfe.w" + - + asm_text: "yield.w" + - + asm_text: "nop.w" + - + asm_text: "sev" + - + asm_text: "wfi" + - + asm_text: "wfe" + - + asm_text: "yield" + - + asm_text: "nop" + - + asm_text: "itet lt" + - + asm_text: "hintlt #0xf" + - + asm_text: "hintge.w #0x10" + - + asm_text: "hintlt.w #0xef" + - + asm_text: "hint #7" + - + asm_text: "hint.w #7" + - + asm_text: "ldrb.w r11, [pc, #0x16]" + - + asm_text: "ldrh.w r11, [pc, #0x16]" + - + asm_text: "ldrsb.w r11, [pc, #0x16]" + - + asm_text: "ldrsh.w r11, [pc, #0x16]" + - + asm_text: "ldr.w r11, [pc, #0x16]" + - + asm_text: "ldrb.w r11, [pc, #0x16]" + - + asm_text: "ldrh.w r11, [pc, #0x16]" + - + asm_text: "ldrsb.w r11, [pc, #0x16]" + - + asm_text: "ldrsh.w r11, [pc, #0x16]" + - + asm_text: "ldr.w r11, [pc, #-0x16]" + - + asm_text: "ldrb.w r11, [pc, #-0x16]" + - + asm_text: "ldrh.w r11, [pc, #-0x16]" + - + asm_text: "ldrsb.w r11, [pc, #-0x16]" + - + asm_text: "ldrsh.w r11, [pc, #-0x16]" + - + asm_text: "ldr.w r11, [pc, #-0x16]" + - + asm_text: "ldrb.w r11, [pc, #-0x16]" + - + asm_text: "ldrh.w r11, [pc, #-0x16]" + - + asm_text: "ldrsb.w r11, [pc, #-0x16]" + - + asm_text: "ldrsh.w r11, [pc, #-0x16]" + - + asm_text: "ldr r1, [pc, #0xc]" + - + asm_text: "subs pc, lr, #4" diff --git a/tests/MC/ARM/bfloat16-a32.s.yaml b/tests/MC/ARM/bfloat16-a32.s.yaml new file mode 100644 index 0000000000..4acde4f856 --- /dev/null +++ b/tests/MC/ARM/bfloat16-a32.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x3d, 0x04, 0xfc ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vdot.bf16 d3, d4, d5" diff --git a/tests/MC/ARM/bfloat16-t32.s.yaml b/tests/MC/ARM/bfloat16-t32.s.yaml new file mode 100644 index 0000000000..08354ff3d6 --- /dev/null +++ b/tests/MC/ARM/bfloat16-t32.s.yaml @@ -0,0 +1,14 @@ +test_cases: + - + input: + bytes: [ 0xb6, 0xff, 0x46, 0x16, 0x18, 0xbf, 0xf3, 0xee, 0xe1, 0x09 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vcvt.bf16.f32 d1, q3" + - + asm_text: "it ne" + - + asm_text: "vcvtt.bf16.f32 s1, s3" diff --git a/tests/MC/ARM/cde-integer.s.yaml b/tests/MC/ARM/cde-integer.s.yaml new file mode 100644 index 0000000000..2a9016b4b0 --- /dev/null +++ b/tests/MC/ARM/cde-integer.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x06, 0xbf ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "itte eq" diff --git a/tests/MC/ARM/cde-vec-pred.s.yaml b/tests/MC/ARM/cde-vec-pred.s.yaml new file mode 100644 index 0000000000..79161f7fdd --- /dev/null +++ b/tests/MC/ARM/cde-vec-pred.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x41, 0xfe, 0x00, 0xef ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vptete.i8 eq, q0, q0" diff --git a/tests/MC/ARM/clrm-asm.s.yaml b/tests/MC/ARM/clrm-asm.s.yaml new file mode 100644 index 0000000000..3f07e55a7b --- /dev/null +++ b/tests/MC/ARM/clrm-asm.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x9f, 0xe8, 0x0f, 0x00, 0x9f, 0xe8, 0x1e, 0x00, 0x9f, 0xe8, 0xff, 0xdf, 0x9f, 0xe8, 0x00, 0xc0, 0x9f, 0xe8, 0x03, 0x80, 0x9f, 0xe8, 0x1f, 0xc0 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "clrm {r0, r1, r2, r3}" + - + asm_text: "clrm {r1, r2, r3, r4}" + - + asm_text: "clrm {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr, apsr}" + - + asm_text: "clrm {lr, apsr}" + - + asm_text: "clrm {r0, r1, apsr}" + - + asm_text: "clrm {r0, r1, r2, r3, r4, lr, apsr}" diff --git a/tests/MC/ARM/cps.s.yaml b/tests/MC/ARM/cps.s.yaml new file mode 100644 index 0000000000..0ea21d9639 --- /dev/null +++ b/tests/MC/ARM/cps.s.yaml @@ -0,0 +1,14 @@ +test_cases: + - + input: + bytes: [ 0x61, 0xb6, 0xaf, 0xf3, 0x43, 0x85, 0xaf, 0xf3, 0x00, 0x81 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "cpsie f" + - + asm_text: "cpsie i, #3" + - + asm_text: "cps #0" diff --git a/tests/MC/ARM/crc32-thumb.s.yaml b/tests/MC/ARM/crc32-thumb.s.yaml new file mode 100644 index 0000000000..782489e325 --- /dev/null +++ b/tests/MC/ARM/crc32-thumb.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0xc1, 0xfa, 0x82, 0xf0, 0xc1, 0xfa, 0x92, 0xf0, 0xc1, 0xfa, 0xa2, 0xf0, 0xd1, 0xfa, 0x82, 0xf0, 0xd1, 0xfa, 0x92, 0xf0, 0xd1, 0xfa, 0xa2, 0xf0 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "crc32b r0, r1, r2" + - + asm_text: "crc32h r0, r1, r2" + - + asm_text: "crc32w r0, r1, r2" + - + asm_text: "crc32cb r0, r1, r2" + - + asm_text: "crc32ch r0, r1, r2" + - + asm_text: "crc32cw r0, r1, r2" diff --git a/tests/MC/ARM/crc32.s.yaml b/tests/MC/ARM/crc32.s.yaml new file mode 100644 index 0000000000..4b630d1c9c --- /dev/null +++ b/tests/MC/ARM/crc32.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0x42, 0x00, 0x01, 0xe1, 0x42, 0x00, 0x21, 0xe1, 0x42, 0x00, 0x41, 0xe1, 0x42, 0x02, 0x01, 0xe1, 0x42, 0x02, 0x21, 0xe1, 0x42, 0x02, 0x41, 0xe1 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "crc32b r0, r1, r2" + - + asm_text: "crc32h r0, r1, r2" + - + asm_text: "crc32w r0, r1, r2" + - + asm_text: "crc32cb r0, r1, r2" + - + asm_text: "crc32ch r0, r1, r2" + - + asm_text: "crc32cw r0, r1, r2" diff --git a/tests/MC/ARM/dot-req.s.yaml b/tests/MC/ARM/dot-req.s.yaml new file mode 100644 index 0000000000..f9be9d9e7f --- /dev/null +++ b/tests/MC/ARM/dot-req.s.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0x05, 0xb0, 0xa0, 0xe1, 0x06, 0x10, 0xa0, 0xe1 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "mov r11, r5" + - + asm_text: "mov r1, r6" diff --git a/tests/MC/ARM/fconst.s.yaml b/tests/MC/ARM/fconst.s.yaml new file mode 100644 index 0000000000..430f726e46 --- /dev/null +++ b/tests/MC/ARM/fconst.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x2a, 0xb0, 0xee, 0x00, 0x2a, 0xb7, 0xee, 0x00, 0x3b, 0xb0, 0xee, 0x00, 0x3b, 0xb7, 0xee, 0x01, 0x2a, 0xf0, 0x1e, 0x00, 0x2a, 0xf2, 0xce, 0x03, 0x2b, 0xb0, 0xbe, 0x00, 0x2b, 0xb4, 0xae ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vmov.f32 s4, #2.000000e+00" + - + asm_text: "vmov.f32 s4, #1.000000e+00" + - + asm_text: "vmov.f64 d3, #2.000000e+00" + - + asm_text: "vmov.f64 d3, #1.000000e+00" + - + asm_text: "vmovne.f32 s5, #2.125000e+00" + - + asm_text: "vmovgt.f32 s5, #8.000000e+00" + - + asm_text: "vmovlt.f64 d2, #2.375000e+00" + - + asm_text: "vmovge.f64 d2, #1.250000e-01" diff --git a/tests/MC/ARM/fp-armv8.s.yaml b/tests/MC/ARM/fp-armv8.s.yaml new file mode 100644 index 0000000000..0da54dbb70 --- /dev/null +++ b/tests/MC/ARM/fp-armv8.s.yaml @@ -0,0 +1,110 @@ +test_cases: + - + input: + bytes: [ 0xe0, 0x3b, 0xb2, 0xee, 0xcc, 0x2b, 0xf3, 0xee, 0x60, 0x3b, 0xb2, 0xee, 0x41, 0x2b, 0xb3, 0xee, 0xe0, 0x3b, 0xb2, 0xae, 0xcc, 0x2b, 0xf3, 0xce, 0x60, 0x3b, 0xb2, 0x0e, 0x41, 0x2b, 0xb3, 0xbe, 0xe1, 0x1a, 0xbc, 0xfe, 0xc3, 0x1b, 0xbc, 0xfe, 0xeb, 0x3a, 0xbd, 0xfe, 0xe7, 0x3b, 0xbd, 0xfe, 0xc2, 0x0a, 0xbe, 0xfe, 0xc4, 0x0b, 0xbe, 0xfe, 0xc4, 0x8a, 0xff, 0xfe, 0xc8, 0x8b, 0xff, 0xfe, 0x61, 0x1a, 0xbc, 0xfe, 0x43, 0x1b, 0xbc, 0xfe, 0x6b, 0x3a, 0xbd, 0xfe, 0x67, 0x3b, 0xbd, 0xfe, 0x42, 0x0a, 0xbe, 0xfe, 0x44, 0x0b, 0xbe, 0xfe, 0x44, 0x8a, 0xff, 0xfe, 0x48, 0x8b, 0xff, 0xfe, 0xab, 0x2a, 0x20, 0xfe, 0xa7, 0xeb, 0x6f, 0xfe, 0x80, 0x0a, 0x30, 0xfe, 0x24, 0x5b, 0x3a, 0xfe, 0x2b, 0xfa, 0x0e, 0xfe, 0x08, 0x2b, 0x04, 0xfe, 0x07, 0xaa, 0x58, 0xfe, 0x2f, 0x0b, 0x11, 0xfe, 0x00, 0x2a, 0xc6, 0xfe, 0xae, 0x5b, 0x86, 0xfe, 0x46, 0x0a, 0x80, 0xfe, 0x49, 0x4b, 0x86, 0xfe, 0xcc, 0x3b, 0xb6, 0xae, 0xcc, 0x1a, 0xf6, 0xee, 0x40, 0x5b, 0xb6, 0xbe, 0x64, 0x0a, 0xb6, 0xee, 0x6e, 0xcb, 0xf7, 0x0e, 0x47, 0x5a, 0xb7, 0x6e, 0x44, 0x3b, 0xb8, 0xfe, 0x60, 0x6a, 0xb8, 0xfe, 0x44, 0x3b, 0xb9, 0xfe, 0x60, 0x6a, 0xb9, 0xfe, 0x44, 0x3b, 0xba, 0xfe, 0x60, 0x6a, 0xba, 0xfe, 0x44, 0x3b, 0xbb, 0xfe, 0x60, 0x6a, 0xbb, 0xfe, 0x10, 0xda, 0xf5, 0xee ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vcvtt.f64.f16 d3, s1" + - + asm_text: "vcvtt.f16.f64 s5, d12" + - + asm_text: "vcvtb.f64.f16 d3, s1" + - + asm_text: "vcvtb.f16.f64 s4, d1" + - + asm_text: "vcvttge.f64.f16 d3, s1" + - + asm_text: "vcvttgt.f16.f64 s5, d12" + - + asm_text: "vcvtbeq.f64.f16 d3, s1" + - + asm_text: "vcvtblt.f16.f64 s4, d1" + - + asm_text: "vcvta.s32.f32 s2, s3" + - + asm_text: "vcvta.s32.f64 s2, d3" + - + asm_text: "vcvtn.s32.f32 s6, s23" + - + asm_text: "vcvtn.s32.f64 s6, d23" + - + asm_text: "vcvtp.s32.f32 s0, s4" + - + asm_text: "vcvtp.s32.f64 s0, d4" + - + asm_text: "vcvtm.s32.f32 s17, s8" + - + asm_text: "vcvtm.s32.f64 s17, d8" + - + asm_text: "vcvta.u32.f32 s2, s3" + - + asm_text: "vcvta.u32.f64 s2, d3" + - + asm_text: "vcvtn.u32.f32 s6, s23" + - + asm_text: "vcvtn.u32.f64 s6, d23" + - + asm_text: "vcvtp.u32.f32 s0, s4" + - + asm_text: "vcvtp.u32.f64 s0, d4" + - + asm_text: "vcvtm.u32.f32 s17, s8" + - + asm_text: "vcvtm.u32.f64 s17, d8" + - + asm_text: "vselge.f32 s4, s1, s23" + - + asm_text: "vselge.f64 d30, d31, d23" + - + asm_text: "vselgt.f32 s0, s1, s0" + - + asm_text: "vselgt.f64 d5, d10, d20" + - + asm_text: "vseleq.f32 s30, s28, s23" + - + asm_text: "vseleq.f64 d2, d4, d8" + - + asm_text: "vselvs.f32 s21, s16, s14" + - + asm_text: "vselvs.f64 d0, d1, d31" + - + asm_text: "vmaxnm.f32 s5, s12, s0" + - + asm_text: "vmaxnm.f64 d5, d22, d30" + - + asm_text: "vminnm.f32 s0, s0, s12" + - + asm_text: "vminnm.f64 d4, d6, d9" + - + asm_text: "vrintzge.f64 d3, d12" + - + asm_text: "vrintz.f32 s3, s24" + - + asm_text: "vrintrlt.f64 d5, d0" + - + asm_text: "vrintr.f32 s0, s9" + - + asm_text: "vrintxeq.f64 d28, d30" + - + asm_text: "vrintxvs.f32 s10, s14" + - + asm_text: "vrinta.f64 d3, d4" + - + asm_text: "vrinta.f32 s12, s1" + - + asm_text: "vrintn.f64 d3, d4" + - + asm_text: "vrintn.f32 s12, s1" + - + asm_text: "vrintp.f64 d3, d4" + - + asm_text: "vrintp.f32 s12, s1" + - + asm_text: "vrintm.f64 d3, d4" + - + asm_text: "vrintm.f32 s12, s1" + - + asm_text: "vmrs sp, mvfr2" diff --git a/tests/MC/ARM/fpv8.s.yaml b/tests/MC/ARM/fpv8.s.yaml new file mode 100644 index 0000000000..ad0e685056 --- /dev/null +++ b/tests/MC/ARM/fpv8.s.yaml @@ -0,0 +1,78 @@ +test_cases: + - + input: + bytes: [ 0xa0, 0x0b, 0x71, 0xee, 0xe0, 0x0b, 0x71, 0xee, 0xa0, 0x0b, 0xc1, 0xee, 0x07, 0x5b, 0x85, 0xee, 0xa0, 0x0b, 0x61, 0xee, 0xa1, 0x4b, 0x64, 0xee, 0xe0, 0x0b, 0x61, 0xee, 0xe0, 0x1b, 0xf4, 0xee, 0xc0, 0x0b, 0xf5, 0xee, 0xe0, 0x0b, 0xf0, 0xee, 0xe0, 0x0b, 0xb7, 0xee, 0xc0, 0x0a, 0xf7, 0xee, 0x60, 0x0b, 0xf1, 0xee, 0xe0, 0x0b, 0xf1, 0xee, 0xc0, 0x0b, 0xf8, 0xee, 0x40, 0x0b, 0xf8, 0xee, 0xe0, 0x0b, 0xbd, 0xee, 0xe0, 0x0b, 0xbc, 0xee, 0xa1, 0x0b, 0x42, 0xee, 0xe1, 0x0b, 0x42, 0xee, 0xe1, 0x0b, 0x52, 0xee, 0xa1, 0x0b, 0x52, 0xee, 0x60, 0x0b, 0xf1, 0x1e, 0x08, 0x0b, 0xf0, 0xee, 0x08, 0x0b, 0xf8, 0xee, 0x40, 0x0b, 0xbd, 0xee, 0x40, 0x0b, 0xbc, 0xee, 0xc0, 0x0b, 0xba, 0xee, 0x40, 0x0b, 0xba, 0xee, 0xc0, 0x4b, 0xfb, 0xee, 0x40, 0x7b, 0xfb, 0xee, 0xc0, 0x2b, 0xbe, 0xee, 0x40, 0xfb, 0xbe, 0xee, 0xc0, 0x4b, 0xff, 0xee, 0x40, 0x7b, 0xff, 0xee ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vadd.f64 d16, d17, d16" + - + asm_text: "vsub.f64 d16, d17, d16" + - + asm_text: "vdiv.f64 d16, d17, d16" + - + asm_text: "vdiv.f64 d5, d5, d7" + - + asm_text: "vmul.f64 d16, d17, d16" + - + asm_text: "vmul.f64 d20, d20, d17" + - + asm_text: "vnmul.f64 d16, d17, d16" + - + asm_text: "vcmpe.f64 d17, d16" + - + asm_text: "vcmpe.f64 d16, #0" + - + asm_text: "vabs.f64 d16, d16" + - + asm_text: "vcvt.f32.f64 s0, d16" + - + asm_text: "vcvt.f64.f32 d16, s0" + - + asm_text: "vneg.f64 d16, d16" + - + asm_text: "vsqrt.f64 d16, d16" + - + asm_text: "vcvt.f64.s32 d16, s0" + - + asm_text: "vcvt.f64.u32 d16, s0" + - + asm_text: "vcvt.s32.f64 s0, d16" + - + asm_text: "vcvt.u32.f64 s0, d16" + - + asm_text: "vmla.f64 d16, d18, d17" + - + asm_text: "vmls.f64 d16, d18, d17" + - + asm_text: "vnmla.f64 d16, d18, d17" + - + asm_text: "vnmls.f64 d16, d18, d17" + - + asm_text: "vnegne.f64 d16, d16" + - + asm_text: "vmov.f64 d16, #3.000000e+00" + - + asm_text: "vmov.f64 d16, #-3.000000e+00" + - + asm_text: "vcvtr.s32.f64 s0, d0" + - + asm_text: "vcvtr.u32.f64 s0, d0" + - + asm_text: "vcvt.f64.s32 d0, d0, #32" + - + asm_text: "vcvt.f64.s16 d0, d0, #16" + - + asm_text: "vcvt.f64.u32 d20, d20, #32" + - + asm_text: "vcvt.f64.u16 d23, d23, #16" + - + asm_text: "vcvt.s32.f64 d2, d2, #32" + - + asm_text: "vcvt.s16.f64 d15, d15, #16" + - + asm_text: "vcvt.u32.f64 d20, d20, #32" + - + asm_text: "vcvt.u16.f64 d23, d23, #16" diff --git a/tests/MC/ARM/gas-compl-copr-reg.s.yaml b/tests/MC/ARM/gas-compl-copr-reg.s.yaml new file mode 100644 index 0000000000..7b77861f68 --- /dev/null +++ b/tests/MC/ARM/gas-compl-copr-reg.s.yaml @@ -0,0 +1,16 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x4c, 0x90, 0xed, 0x38, 0x6e, 0x02, 0xed, 0x01, 0x4c, 0x90, 0xed, 0x38, 0x6e, 0x02, 0xed ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "ldc p12, c4, [r0, #4]" + - + asm_text: "stc p14, c6, [r2, #-0xe0]" + - + asm_text: "ldc p12, c4, [r0, #4]" + - + asm_text: "stc p14, c6, [r2, #-0xe0]" diff --git a/tests/MC/ARM/idiv-thumb.s.yaml b/tests/MC/ARM/idiv-thumb.s.yaml new file mode 100644 index 0000000000..6e2933b8ef --- /dev/null +++ b/tests/MC/ARM/idiv-thumb.s.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0x92, 0xfb, 0xf3, 0xf1, 0xb4, 0xfb, 0xf5, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "sdiv r1, r2, r3" + - + asm_text: "udiv r3, r4, r5" diff --git a/tests/MC/ARM/idiv.s.yaml b/tests/MC/ARM/idiv.s.yaml new file mode 100644 index 0000000000..6cc10c7b6a --- /dev/null +++ b/tests/MC/ARM/idiv.s.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0x12, 0xf3, 0x11, 0xe7, 0x14, 0xf5, 0x33, 0xe7 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "sdiv r1, r2, r3" + - + asm_text: "udiv r3, r4, r5" diff --git a/tests/MC/ARM/implicit-it-generation.s.yaml b/tests/MC/ARM/implicit-it-generation.s.yaml new file mode 100644 index 0000000000..6ddc9738f7 --- /dev/null +++ b/tests/MC/ARM/implicit-it-generation.s.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x30, 0x10, 0xf1, 0x01, 0x00, 0x80, 0xe0, 0x00, 0xf0, 0x00, 0xbc, 0x02, 0xd0, 0x00, 0xf0, 0x80, 0x80, 0x02, 0xe0, 0x80, 0xe0, 0x00, 0xf0, 0x00, 0xbc, 0x02, 0xdc, 0x00, 0xf3, 0x80, 0x80 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "adds r0, #1" + - + asm_text: "adds.w r0, r0, #1" + - + asm_text: "b #0x100" + - + asm_text: "b.w #0x800" + - + asm_text: "beq #4" + - + asm_text: "beq.w #0x100" + - + asm_text: "b #4" + - + asm_text: "b #0x100" + - + asm_text: "b.w #0x800" + - + asm_text: "bgt #4" + - + asm_text: "bgt.w #0x100" diff --git a/tests/MC/ARM/ldrd-strd-gnu-arm.s.yaml b/tests/MC/ARM/ldrd-strd-gnu-arm.s.yaml new file mode 100644 index 0000000000..230eabd5ed --- /dev/null +++ b/tests/MC/ARM/ldrd-strd-gnu-arm.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0xd0, 0x02, 0xea, 0xe1, 0xd0, 0x02, 0xca, 0xe0, 0xd0, 0x02, 0xca, 0xe1, 0xf0, 0x02, 0xea, 0xe1, 0xf0, 0x02, 0xca, 0xe0, 0xf0, 0x02, 0xca, 0xe1 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "ldrd r0, r1, [r10, #0x20]!" + - + asm_text: "ldrd r0, r1, [r10], #0x20" + - + asm_text: "ldrd r0, r1, [r10, #0x20]" + - + asm_text: "strd r0, r1, [r10, #0x20]!" + - + asm_text: "strd r0, r1, [r10], #0x20" + - + asm_text: "strd r0, r1, [r10, #0x20]" diff --git a/tests/MC/ARM/ldrd-strd-gnu-thumb.s.yaml b/tests/MC/ARM/ldrd-strd-gnu-thumb.s.yaml new file mode 100644 index 0000000000..076ae91541 --- /dev/null +++ b/tests/MC/ARM/ldrd-strd-gnu-thumb.s.yaml @@ -0,0 +1,32 @@ +test_cases: + - + input: + bytes: [ 0xfa, 0xe9, 0x80, 0x01, 0xfa, 0xe8, 0x80, 0x01, 0xda, 0xe9, 0x80, 0x01, 0xea, 0xe9, 0x80, 0x01, 0xea, 0xe8, 0x80, 0x01, 0xca, 0xe9, 0x80, 0x01, 0xfa, 0xe9, 0x80, 0x12, 0xfa, 0xe8, 0x80, 0x12, 0xda, 0xe9, 0x80, 0x12, 0xea, 0xe9, 0x80, 0x12, 0xea, 0xe8, 0x80, 0x12, 0xca, 0xe9, 0x80, 0x12 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "ldrd r0, r1, [r10, #0x200]!" + - + asm_text: "ldrd r0, r1, [r10], #0x200" + - + asm_text: "ldrd r0, r1, [r10, #0x200]" + - + asm_text: "strd r0, r1, [r10, #0x200]!" + - + asm_text: "strd r0, r1, [r10], #0x200" + - + asm_text: "strd r0, r1, [r10, #0x200]" + - + asm_text: "ldrd r1, r2, [r10, #0x200]!" + - + asm_text: "ldrd r1, r2, [r10], #0x200" + - + asm_text: "ldrd r1, r2, [r10, #0x200]" + - + asm_text: "strd r1, r2, [r10, #0x200]!" + - + asm_text: "strd r1, r2, [r10], #0x200" + - + asm_text: "strd r1, r2, [r10, #0x200]" diff --git a/tests/MC/ARM/load-store-acquire-release-v8-thumb.s.yaml b/tests/MC/ARM/load-store-acquire-release-v8-thumb.s.yaml new file mode 100644 index 0000000000..6f376cc260 --- /dev/null +++ b/tests/MC/ARM/load-store-acquire-release-v8-thumb.s.yaml @@ -0,0 +1,36 @@ +test_cases: + - + input: + bytes: [ 0xd4, 0xe8, 0xcf, 0x3f, 0xd5, 0xe8, 0xdf, 0x2f, 0xd7, 0xe8, 0xef, 0x1f, 0xd8, 0xe8, 0xff, 0x67, 0xc4, 0xe8, 0xc1, 0x3f, 0xc5, 0xe8, 0xd4, 0x2f, 0xc7, 0xe8, 0xe2, 0x1f, 0xc8, 0xe8, 0xf6, 0x23, 0xd6, 0xe8, 0xaf, 0x5f, 0xd6, 0xe8, 0x8f, 0x5f, 0xd9, 0xe8, 0x9f, 0xcf, 0xc0, 0xe8, 0xaf, 0x3f, 0xc1, 0xe8, 0x8f, 0x2f, 0xc3, 0xe8, 0x9f, 0x2f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "ldaexb r3, [r4]" + - + asm_text: "ldaexh r2, [r5]" + - + asm_text: "ldaex r1, [r7]" + - + asm_text: "ldaexd r6, r7, [r8]" + - + asm_text: "stlexb r1, r3, [r4]" + - + asm_text: "stlexh r4, r2, [r5]" + - + asm_text: "stlex r2, r1, [r7]" + - + asm_text: "stlexd r6, r2, r3, [r8]" + - + asm_text: "lda r5, [r6]" + - + asm_text: "ldab r5, [r6]" + - + asm_text: "ldah r12, [r9]" + - + asm_text: "stl r3, [r0]" + - + asm_text: "stlb r2, [r1]" + - + asm_text: "stlh r2, [r3]" diff --git a/tests/MC/ARM/load-store-acquire-release-v8.s.yaml b/tests/MC/ARM/load-store-acquire-release-v8.s.yaml new file mode 100644 index 0000000000..de9f4b00d4 --- /dev/null +++ b/tests/MC/ARM/load-store-acquire-release-v8.s.yaml @@ -0,0 +1,36 @@ +test_cases: + - + input: + bytes: [ 0x9f, 0x3e, 0xd4, 0xe1, 0x9f, 0x2e, 0xf5, 0xe1, 0x9f, 0x1e, 0x97, 0xe1, 0x9f, 0x6e, 0xb8, 0xe1, 0x93, 0x1e, 0xc4, 0xe1, 0x92, 0x4e, 0xe5, 0xe1, 0x91, 0x2e, 0x87, 0xe1, 0x92, 0x6e, 0xa8, 0xe1, 0x9f, 0x5c, 0x96, 0xe1, 0x9f, 0x5c, 0xd6, 0xe1, 0x9f, 0xcc, 0xf9, 0xe1, 0x93, 0xfc, 0x80, 0xe1, 0x92, 0xfc, 0xc1, 0xe1, 0x92, 0xfc, 0xe3, 0xe1 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "ldaexb r3, [r4]" + - + asm_text: "ldaexh r2, [r5]" + - + asm_text: "ldaex r1, [r7]" + - + asm_text: "ldaexd r6, r7, [r8]" + - + asm_text: "stlexb r1, r3, [r4]" + - + asm_text: "stlexh r4, r2, [r5]" + - + asm_text: "stlex r2, r1, [r7]" + - + asm_text: "stlexd r6, r2, r3, [r8]" + - + asm_text: "lda r5, [r6]" + - + asm_text: "ldab r5, [r6]" + - + asm_text: "ldah r12, [r9]" + - + asm_text: "stl r3, [r0]" + - + asm_text: "stlb r2, [r1]" + - + asm_text: "stlh r2, [r3]" diff --git a/tests/MC/ARM/mve-bitops.s.yaml b/tests/MC/ARM/mve-bitops.s.yaml new file mode 100644 index 0000000000..e61a502d15 --- /dev/null +++ b/tests/MC/ARM/mve-bitops.s.yaml @@ -0,0 +1,198 @@ +test_cases: + - + input: + bytes: [ 0x81, 0xef, 0x52, 0x09, 0x81, 0xef, 0x52, 0x03, 0x86, 0xff, 0x5d, 0x09, 0x86, 0xff, 0x5d, 0x03, 0x86, 0xff, 0x5d, 0x05, 0x86, 0xff, 0x5d, 0x07, 0x82, 0xef, 0x72, 0x09, 0x81, 0xef, 0x71, 0x03, 0x85, 0xff, 0x7d, 0x09, 0x85, 0xff, 0x7d, 0x0b, 0x86, 0xff, 0x7e, 0x01, 0x86, 0xff, 0x7e, 0x03, 0x86, 0xff, 0x7e, 0x05, 0x86, 0xff, 0x7e, 0x07, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0xb0, 0xff, 0x48, 0x00, 0xb4, 0xff, 0x46, 0x20, 0xb8, 0xff, 0x44, 0x00, 0xb0, 0xff, 0xc2, 0x00, 0xb4, 0xff, 0xca, 0x00, 0xb0, 0xff, 0x44, 0x01, 0xb0, 0xff, 0xc4, 0x05, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x40, 0xee, 0x30, 0x8b, 0x20, 0xee, 0x30, 0x5b, 0x2d, 0xee, 0x10, 0xbb, 0x12, 0xee, 0x10, 0x0b, 0x35, 0xee, 0x70, 0x1b, 0x79, 0xee, 0x30, 0x0b, 0x93, 0xee, 0x30, 0x0b, 0xfa, 0xee, 0x70, 0x0b, 0x71, 0xfe, 0x4d, 0x8f, 0xb0, 0xff, 0xc2, 0x05, 0xb0, 0xff, 0xc2, 0x05, 0x71, 0xfe, 0x4d, 0x8f, 0x32, 0xef, 0x54, 0x01, 0x32, 0xef, 0x54, 0x01 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vorr.i16 q0, #0x12" + - + asm_text: "vorr.i32 q0, #0x1200" + - + asm_text: "vorr.i16 q0, #0xed" + - + asm_text: "vorr.i32 q0, #0xed00" + - + asm_text: "vorr.i32 q0, #0xed0000" + - + asm_text: "vorr.i32 q0, #0xed000000" + - + asm_text: "vbic.i16 q0, #0x22" + - + asm_text: "vbic.i32 q0, #0x1100" + - + asm_text: "vbic.i16 q0, #0xdd" + - + asm_text: "vbic.i16 q0, #0xdd00" + - + asm_text: "vbic.i32 q0, #0xee" + - + asm_text: "vbic.i32 q0, #0xee00" + - + asm_text: "vbic.i32 q0, #0xee0000" + - + asm_text: "vbic.i32 q0, #0xee000000" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vbic q0, q1, q7" + - + asm_text: "vrev64.8 q0, q4" + - + asm_text: "vrev64.16 q1, q3" + - + asm_text: "vrev64.32 q0, q2" + - + asm_text: "vrev32.8 q0, q1" + - + asm_text: "vrev32.16 q0, q5" + - + asm_text: "vrev16.8 q0, q2" + - + asm_text: "vmvn q0, q2" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "veor q2, q1, q7" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorn q0, q3, q2" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vorr q1, q2, q1" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vand q0, q2, q0" + - + asm_text: "vmov.8 q0[1], r8" + - + asm_text: "vmov.16 q0[2], r5" + - + asm_text: "vmov.32 q6[3], r11" + - + asm_text: "vmov.32 r0, q1[0]" + - + asm_text: "vmov.s16 r1, q2[7]" + - + asm_text: "vmov.s8 r0, q4[13]" + - + asm_text: "vmov.u16 r0, q1[4]" + - + asm_text: "vmov.u8 r0, q5[7]" + - + asm_text: "vpste" + - + asm_text: "vmvnt q0, q1" + - + asm_text: "vmvne q0, q1" + - + asm_text: "vpste" + - + asm_text: "vornt q0, q1, q2" + - + asm_text: "vorne q0, q1, q2" diff --git a/tests/MC/ARM/mve-float.s.yaml b/tests/MC/ARM/mve-float.s.yaml new file mode 100644 index 0000000000..c2b9188c5d --- /dev/null +++ b/tests/MC/ARM/mve-float.s.yaml @@ -0,0 +1,212 @@ +test_cases: + - + input: + bytes: [ 0xb6, 0xff, 0x40, 0x24, 0xba, 0xff, 0x48, 0x04, 0xb6, 0xff, 0x42, 0x05, 0xba, 0xff, 0x46, 0x25, 0xb6, 0xff, 0xca, 0x06, 0xba, 0xff, 0xc8, 0x06, 0xb6, 0xff, 0xc0, 0x27, 0xba, 0xff, 0xc2, 0x07, 0xb6, 0xff, 0xc4, 0x24, 0xba, 0xff, 0xc2, 0x24, 0xb6, 0xff, 0xcc, 0x25, 0xba, 0xff, 0xc0, 0x25, 0xb6, 0xee, 0x60, 0x0a, 0xb6, 0xee, 0x41, 0x0b, 0x12, 0xff, 0x56, 0x4d, 0x00, 0xff, 0x5a, 0x0d, 0x24, 0xfc, 0x42, 0x68, 0xa0, 0xfc, 0x4a, 0x08, 0x2e, 0xfd, 0x44, 0x68, 0xae, 0xfd, 0x4c, 0x48, 0x3c, 0xfc, 0x4c, 0x48, 0xb2, 0xfc, 0x46, 0xe8, 0x3a, 0xfd, 0x46, 0x88, 0xb4, 0xfd, 0x4e, 0x68, 0x14, 0xef, 0x56, 0x0c, 0x06, 0xef, 0x5e, 0x0c, 0x34, 0xef, 0x5a, 0x0c, 0x22, 0xef, 0x54, 0x2c, 0x10, 0xef, 0x4a, 0x0d, 0x06, 0xef, 0x40, 0x2d, 0x02, 0xef, 0x44, 0x0d, 0x82, 0xfc, 0x4e, 0x48, 0x8a, 0xfd, 0x4e, 0x48, 0x98, 0xfc, 0x4e, 0x08, 0x94, 0xfd, 0x46, 0x48, 0x30, 0xff, 0x4c, 0x0d, 0x22, 0xff, 0x48, 0x0d, 0xbf, 0xef, 0x5e, 0x2c, 0xb0, 0xef, 0x5e, 0x2c, 0xb5, 0xef, 0x5e, 0x2c, 0xbd, 0xef, 0x52, 0x2d, 0xb6, 0xff, 0x52, 0x4c, 0xbd, 0xff, 0x50, 0x0d, 0xbf, 0xef, 0x5e, 0x2e, 0xa0, 0xef, 0x5e, 0x2e, 0xba, 0xef, 0x5e, 0x2e, 0xab, 0xef, 0x50, 0x2f, 0xbc, 0xff, 0x58, 0x2e, 0xb8, 0xff, 0x5a, 0x2f, 0xb7, 0xff, 0x42, 0x06, 0xb7, 0xff, 0xc8, 0x06, 0xb7, 0xff, 0x40, 0x07, 0xb7, 0xff, 0xc0, 0x07, 0xbb, 0xff, 0x40, 0x06, 0xbb, 0xff, 0xc0, 0x06, 0xbb, 0xff, 0x40, 0x07, 0xbb, 0xff, 0xc4, 0x07, 0xb7, 0xff, 0x4e, 0x00, 0xbc, 0xfe, 0xe1, 0x1a, 0xb7, 0xff, 0x4e, 0x00, 0xbb, 0xff, 0xcc, 0xe1, 0xbb, 0xff, 0x4e, 0x02, 0xbb, 0xff, 0xc8, 0x23, 0xb5, 0xff, 0xce, 0x07, 0xb9, 0xff, 0xc4, 0x07, 0xb5, 0xff, 0x44, 0x07, 0xb9, 0xff, 0x40, 0x07, 0x3f, 0xfe, 0x83, 0x2e, 0x3f, 0xee, 0x8d, 0x4e, 0x3f, 0xfe, 0x85, 0x1e, 0x3f, 0xee, 0x83, 0x1e, 0x08, 0xbf, 0x30, 0xee, 0x20, 0x0a, 0x71, 0xfe, 0x4d, 0x0f, 0x12, 0xef, 0x44, 0x0d, 0x71, 0xfe, 0x4d, 0x8f, 0xbb, 0xff, 0xc2, 0x03, 0xbb, 0xff, 0x42, 0x01, 0x18, 0xbf, 0xbd, 0xee, 0xe0, 0x0a, 0xa8, 0xbf, 0xb2, 0xee, 0xe0, 0x3b, 0x77, 0xee, 0xc1, 0x9f, 0xbb, 0xff, 0xc0, 0x47, 0xbb, 0xff, 0xc0, 0x27, 0x0c, 0xbf, 0xbc, 0xee, 0xe0, 0x0a, 0xb8, 0xee, 0x60, 0x0a, 0x71, 0xfe, 0x4d, 0x8f, 0x12, 0xff, 0x54, 0x0d, 0x12, 0xff, 0x54, 0x0d, 0x0c, 0xbf, 0x20, 0xee, 0x01, 0x0b, 0x20, 0xee, 0x02, 0x1b, 0x08, 0xbf, 0xb1, 0xee, 0x60, 0x0a, 0x04, 0xbf, 0x20, 0xee, 0xc1, 0x0a, 0x20, 0xee, 0x81, 0x0a, 0x71, 0xfe, 0x4d, 0x8f, 0xb6, 0xff, 0x42, 0x04, 0xba, 0xff, 0x42, 0x04 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vrintn.f16 q1, q0" + - + asm_text: "vrintn.f32 q0, q4" + - + asm_text: "vrinta.f16 q0, q1" + - + asm_text: "vrinta.f32 q1, q3" + - + asm_text: "vrintm.f16 q0, q5" + - + asm_text: "vrintm.f32 q0, q4" + - + asm_text: "vrintp.f16 q1, q0" + - + asm_text: "vrintp.f32 q0, q1" + - + asm_text: "vrintx.f16 q1, q2" + - + asm_text: "vrintx.f32 q1, q1" + - + asm_text: "vrintz.f16 q1, q6" + - + asm_text: "vrintz.f32 q1, q0" + - + asm_text: "vrintr.f32 s0, s1" + - + asm_text: "vrintr.f64 d0, d1" + - + asm_text: "vmul.f16 q2, q1, q3" + - + asm_text: "vmul.f32 q0, q0, q5" + - + asm_text: "vcmla.f16 q3, q2, q1, #0" + - + asm_text: "vcmla.f16 q0, q0, q5, #0x5a" + - + asm_text: "vcmla.f16 q3, q7, q2, #0xb4" + - + asm_text: "vcmla.f16 q2, q7, q6, #0x10e" + - + asm_text: "vcmla.f32 q2, q6, q6, #0" + - + asm_text: "vcmla.f32 q7, q1, q3, #0x5a" + - + asm_text: "vcmla.f32 q4, q5, q3, #0xb4" + - + asm_text: "vcmla.f32 q3, q2, q7, #0x10e" + - + asm_text: "vfma.f16 q0, q2, q3" + - + asm_text: "vfma.f32 q0, q3, q7" + - + asm_text: "vfms.f16 q0, q2, q5" + - + asm_text: "vfms.f32 q1, q1, q2" + - + asm_text: "vadd.f16 q0, q0, q5" + - + asm_text: "vadd.f32 q1, q3, q0" + - + asm_text: "vadd.f32 q0, q1, q2" + - + asm_text: "vcadd.f16 q2, q1, q7, #0x5a" + - + asm_text: "vcadd.f16 q2, q5, q7, #0x10e" + - + asm_text: "vcadd.f32 q0, q4, q7, #0x5a" + - + asm_text: "vcadd.f32 q2, q2, q3, #0x10e" + - + asm_text: "vabd.f16 q0, q0, q6" + - + asm_text: "vabd.f32 q0, q1, q4" + - + asm_text: "vcvt.f16.s16 q1, q7, #1" + - + asm_text: "vcvt.f16.s16 q1, q7, #0x10" + - + asm_text: "vcvt.f16.s16 q1, q7, #0xb" + - + asm_text: "vcvt.s16.f16 q1, q1, #3" + - + asm_text: "vcvt.f16.u16 q2, q1, #0xa" + - + asm_text: "vcvt.u16.f16 q0, q0, #3" + - + asm_text: "vcvt.f32.s32 q1, q7, #1" + - + asm_text: "vcvt.f32.s32 q1, q7, #0x20" + - + asm_text: "vcvt.f32.s32 q1, q7, #6" + - + asm_text: "vcvt.s32.f32 q1, q0, #0x15" + - + asm_text: "vcvt.f32.u32 q1, q4, #4" + - + asm_text: "vcvt.u32.f32 q1, q5, #8" + - + asm_text: "vcvt.f16.s16 q0, q1" + - + asm_text: "vcvt.f16.u16 q0, q4" + - + asm_text: "vcvt.s16.f16 q0, q0" + - + asm_text: "vcvt.u16.f16 q0, q0" + - + asm_text: "vcvt.f32.s32 q0, q0" + - + asm_text: "vcvt.f32.u32 q0, q0" + - + asm_text: "vcvt.s32.f32 q0, q0" + - + asm_text: "vcvt.u32.f32 q0, q2" + - + asm_text: "vcvta.s16.f16 q0, q7" + - + asm_text: "vcvta.s32.f32 s2, s3" + - + asm_text: "vcvta.s16.f16 q0, q7" + - + asm_text: "vcvtn.u32.f32 q7, q6" + - + asm_text: "vcvtp.s32.f32 q0, q7" + - + asm_text: "vcvtm.u32.f32 q1, q4" + - + asm_text: "vneg.f16 q0, q7" + - + asm_text: "vneg.f32 q0, q2" + - + asm_text: "vabs.f16 q0, q2" + - + asm_text: "vabs.f32 q0, q0" + - + asm_text: "vmaxnma.f16 q1, q1" + - + asm_text: "vmaxnma.f32 q2, q6" + - + asm_text: "vminnma.f16 q0, q2" + - + asm_text: "vminnma.f32 q0, q1" + - + asm_text: "it eq" + - + asm_text: "vaddeq.f32 s0, s0, s1" + - + asm_text: "vpst" + - + asm_text: "vaddt.f16 q0, q1, q2" + - + asm_text: "vpste" + - + asm_text: "vcvtmt.u32.f32 q0, q1" + - + asm_text: "vcvtne.s32.f32 q0, q1" + - + asm_text: "it ne" + - + asm_text: "vcvtne.s32.f32 s0, s1" + - + asm_text: "it ge" + - + asm_text: "vcvttge.f64.f16 d3, s1" + - + asm_text: "vpte.f32 lt, q3, r1" + - + asm_text: "vcvtt.u32.f32 q2, q0" + - + asm_text: "vcvte.u32.f32 q1, q0" + - + asm_text: "ite eq" + - + asm_text: "vcvteq.u32.f32 s0, s1" + - + asm_text: "vcvtne.f32.u32 s0, s1" + - + asm_text: "vpste" + - + asm_text: "vmult.f16 q0, q1, q2" + - + asm_text: "vmule.f16 q0, q1, q2" + - + asm_text: "ite eq" + - + asm_text: "vmuleq.f64 d0, d0, d1" + - + asm_text: "vmulne.f64 d1, d0, d2" + - + asm_text: "it eq" + - + asm_text: "vnegeq.f32 s0, s1" + - + asm_text: "itt eq" + - + asm_text: "vnmuleq.f32 s0, s1, s2" + - + asm_text: "vmuleq.f32 s0, s1, s2" + - + asm_text: "vpste" + - + asm_text: "vrintnt.f16 q0, q1" + - + asm_text: "vrintne.f32 q0, q1" diff --git a/tests/MC/ARM/mve-integer.s.yaml b/tests/MC/ARM/mve-integer.s.yaml new file mode 100644 index 0000000000..fcc984d1a3 --- /dev/null +++ b/tests/MC/ARM/mve-integer.s.yaml @@ -0,0 +1,206 @@ +test_cases: + - + input: + bytes: [ 0x81, 0xef, 0x5b, 0x0c, 0x85, 0xef, 0x5c, 0x08, 0x84, 0xef, 0x5c, 0x0e, 0x80, 0xff, 0x5d, 0x0f, 0x84, 0xef, 0x50, 0x0f, 0x84, 0xef, 0x51, 0x0f, 0x83, 0xef, 0x5f, 0x0f, 0xb0, 0xee, 0x60, 0x8a, 0xb0, 0xee, 0x41, 0x0b, 0x81, 0xff, 0x7f, 0x0e, 0x00, 0xef, 0x56, 0x09, 0x10, 0xef, 0x56, 0xc9, 0x26, 0xef, 0x5c, 0xe9, 0x0a, 0xff, 0x4a, 0x0b, 0x18, 0xff, 0x44, 0x2b, 0x2a, 0xff, 0x40, 0x0b, 0x08, 0xef, 0x4a, 0x0b, 0x18, 0xef, 0x40, 0xcb, 0x20, 0xef, 0x4c, 0xab, 0x04, 0xff, 0x4a, 0x68, 0x16, 0xff, 0x4c, 0x08, 0x20, 0xff, 0x4c, 0x08, 0x04, 0xef, 0x44, 0x08, 0x14, 0xef, 0x42, 0x48, 0x20, 0xef, 0x4c, 0x08, 0x0c, 0xef, 0x50, 0x22, 0x1c, 0xef, 0x52, 0x02, 0x20, 0xef, 0x5a, 0x02, 0x04, 0xff, 0x5c, 0x02, 0x1e, 0xff, 0x52, 0x02, 0x28, 0xff, 0x5e, 0x22, 0x02, 0xef, 0x54, 0x00, 0x08, 0xef, 0x5c, 0x00, 0x1a, 0xef, 0x5a, 0x00, 0x20, 0xef, 0x58, 0x00, 0x08, 0xff, 0x54, 0x00, 0x1c, 0xff, 0x5c, 0x80, 0x22, 0xff, 0x54, 0x00, 0x00, 0xef, 0x44, 0x07, 0x1a, 0xef, 0x48, 0x27, 0x26, 0xef, 0x44, 0x47, 0x0c, 0xff, 0x48, 0x27, 0x1c, 0xff, 0x44, 0x07, 0x2e, 0xff, 0x48, 0x07, 0x02, 0xef, 0x42, 0x01, 0x12, 0xef, 0x40, 0x01, 0x28, 0xef, 0x42, 0x01, 0x00, 0xff, 0x4c, 0x21, 0x14, 0xff, 0x4a, 0x41, 0x26, 0xff, 0x40, 0x41, 0x00, 0xef, 0x44, 0x02, 0x16, 0xef, 0x42, 0x22, 0x24, 0xef, 0x4a, 0x02, 0x08, 0xff, 0x44, 0x02, 0x1e, 0xff, 0x4a, 0x02, 0x2c, 0xff, 0x48, 0x42, 0x0e, 0xef, 0x40, 0x00, 0x10, 0xef, 0x44, 0x80, 0x26, 0xef, 0x42, 0x00, 0x00, 0xff, 0x46, 0x60, 0x12, 0xff, 0x46, 0x00, 0x22, 0xff, 0x46, 0x00, 0xec, 0xee, 0x10, 0x8b, 0xae, 0xee, 0x30, 0xeb, 0xa2, 0xee, 0x10, 0x9b, 0xa0, 0xee, 0x30, 0x1b, 0xa0, 0xee, 0x30, 0x1b, 0xb0, 0xff, 0x42, 0x44, 0xb4, 0xff, 0x48, 0x04, 0xb8, 0xff, 0x40, 0x04, 0xb0, 0xff, 0xce, 0x04, 0xb4, 0xff, 0xce, 0x84, 0xb8, 0xff, 0xca, 0xe4, 0xb1, 0xff, 0xc0, 0x23, 0xb5, 0xff, 0xc2, 0x03, 0xb9, 0xff, 0xc4, 0xe3, 0xb1, 0xff, 0x42, 0x23, 0xb5, 0xff, 0x44, 0x03, 0xb9, 0xff, 0x4e, 0x03, 0xb0, 0xff, 0xc0, 0x07, 0xb4, 0xff, 0xc4, 0xc7, 0xb8, 0xff, 0xc4, 0xe7, 0xb0, 0xff, 0x48, 0x47, 0xb4, 0xff, 0x44, 0x07, 0xb8, 0xff, 0x4a, 0x07, 0x71, 0xfe, 0x4d, 0x8f, 0xb1, 0xff, 0xc2, 0x03, 0xb1, 0xff, 0xc2, 0x03, 0x71, 0xfe, 0x4d, 0x0f, 0x12, 0xef, 0x54, 0x00, 0x71, 0xfe, 0x4d, 0x8f, 0xb0, 0xff, 0xc2, 0x07, 0xb4, 0xff, 0xc2, 0x07, 0x33, 0xee, 0x8f, 0x3e, 0x37, 0xee, 0x89, 0x3e, 0x3b, 0xee, 0x8f, 0x1e, 0x33, 0xee, 0x8f, 0x0e, 0x37, 0xee, 0x81, 0x2e, 0x3b, 0xee, 0x81, 0x2e ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmov.i32 q0, #0x1bff" + - + asm_text: "vmov.i16 q0, #0x5c" + - + asm_text: "vmov.i8 q0, #0x4c" + - + asm_text: "vmov.f32 q0, #-3.625000e+00" + - + asm_text: "vmov.f32 q0, #1.250000e-01" + - + asm_text: "vmov.f32 q0, #1.328125e-01" + - + asm_text: "vmov.f32 q0, #3.100000e+01" + - + asm_text: "vmov.f32 s16, s1" + - + asm_text: "vmov.f64 d0, d1" + - + asm_text: "vmov.i64 q0, #0xff0000ffffffffff" + - + asm_text: "vmul.i8 q0, q0, q3" + - + asm_text: "vmul.i16 q6, q0, q3" + - + asm_text: "vmul.i32 q7, q3, q6" + - + asm_text: "vqrdmulh.s8 q0, q5, q5" + - + asm_text: "vqrdmulh.s16 q1, q4, q2" + - + asm_text: "vqrdmulh.s32 q0, q5, q0" + - + asm_text: "vqdmulh.s8 q0, q4, q5" + - + asm_text: "vqdmulh.s16 q6, q4, q0" + - + asm_text: "vqdmulh.s32 q5, q0, q6" + - + asm_text: "vsub.i8 q3, q2, q5" + - + asm_text: "vsub.i16 q0, q3, q6" + - + asm_text: "vsub.i32 q0, q0, q6" + - + asm_text: "vadd.i8 q0, q2, q2" + - + asm_text: "vadd.i16 q2, q2, q1" + - + asm_text: "vadd.i32 q0, q0, q6" + - + asm_text: "vqsub.s8 q1, q6, q0" + - + asm_text: "vqsub.s16 q0, q6, q1" + - + asm_text: "vqsub.s32 q0, q0, q5" + - + asm_text: "vqsub.u8 q0, q2, q6" + - + asm_text: "vqsub.u16 q0, q7, q1" + - + asm_text: "vqsub.u32 q1, q4, q7" + - + asm_text: "vqadd.s8 q0, q1, q2" + - + asm_text: "vqadd.s8 q0, q4, q6" + - + asm_text: "vqadd.s16 q0, q5, q5" + - + asm_text: "vqadd.s32 q0, q0, q4" + - + asm_text: "vqadd.u8 q0, q4, q2" + - + asm_text: "vqadd.u16 q4, q6, q6" + - + asm_text: "vqadd.u32 q0, q1, q2" + - + asm_text: "vabd.s8 q0, q0, q2" + - + asm_text: "vabd.s16 q1, q5, q4" + - + asm_text: "vabd.s32 q2, q3, q2" + - + asm_text: "vabd.u8 q1, q6, q4" + - + asm_text: "vabd.u16 q0, q6, q2" + - + asm_text: "vabd.u32 q0, q7, q4" + - + asm_text: "vrhadd.s8 q0, q1, q1" + - + asm_text: "vrhadd.s16 q0, q1, q0" + - + asm_text: "vrhadd.s32 q0, q4, q1" + - + asm_text: "vrhadd.u8 q1, q0, q6" + - + asm_text: "vrhadd.u16 q2, q2, q5" + - + asm_text: "vrhadd.u32 q2, q3, q0" + - + asm_text: "vhsub.s8 q0, q0, q2" + - + asm_text: "vhsub.s16 q1, q3, q1" + - + asm_text: "vhsub.s32 q0, q2, q5" + - + asm_text: "vhsub.u8 q0, q4, q2" + - + asm_text: "vhsub.u16 q0, q7, q5" + - + asm_text: "vhsub.u32 q2, q6, q4" + - + asm_text: "vhadd.s8 q0, q7, q0" + - + asm_text: "vhadd.s16 q4, q0, q2" + - + asm_text: "vhadd.s32 q0, q3, q1" + - + asm_text: "vhadd.u8 q3, q0, q3" + - + asm_text: "vhadd.u16 q0, q1, q3" + - + asm_text: "vhadd.u32 q0, q1, q3" + - + asm_text: "vdup.8 q6, r8" + - + asm_text: "vdup.16 q7, lr" + - + asm_text: "vdup.32 q1, r9" + - + asm_text: "vdup.16 q0, r1" + - + asm_text: "vdup.16 q0, r1" + - + asm_text: "vcls.s8 q2, q1" + - + asm_text: "vcls.s16 q0, q4" + - + asm_text: "vcls.s32 q0, q0" + - + asm_text: "vclz.i8 q0, q7" + - + asm_text: "vclz.i16 q4, q7" + - + asm_text: "vclz.i32 q7, q5" + - + asm_text: "vneg.s8 q1, q0" + - + asm_text: "vneg.s16 q0, q1" + - + asm_text: "vneg.s32 q7, q2" + - + asm_text: "vabs.s8 q1, q1" + - + asm_text: "vabs.s16 q0, q2" + - + asm_text: "vabs.s32 q0, q7" + - + asm_text: "vqneg.s8 q0, q0" + - + asm_text: "vqneg.s16 q6, q2" + - + asm_text: "vqneg.s32 q7, q2" + - + asm_text: "vqabs.s8 q2, q4" + - + asm_text: "vqabs.s16 q0, q2" + - + asm_text: "vqabs.s32 q0, q5" + - + asm_text: "vpste" + - + asm_text: "vnegt.s8 q0, q1" + - + asm_text: "vnege.s8 q0, q1" + - + asm_text: "vpst" + - + asm_text: "vqaddt.s16 q0, q1, q2" + - + asm_text: "vpste" + - + asm_text: "vqnegt.s8 q0, q1" + - + asm_text: "vqnege.s16 q0, q1" + - + asm_text: "vmina.s8 q1, q7" + - + asm_text: "vmina.s16 q1, q4" + - + asm_text: "vmina.s32 q0, q7" + - + asm_text: "vmaxa.s8 q0, q7" + - + asm_text: "vmaxa.s16 q1, q0" + - + asm_text: "vmaxa.s32 q1, q0" diff --git a/tests/MC/ARM/mve-interleave.s.yaml b/tests/MC/ARM/mve-interleave.s.yaml new file mode 100644 index 0000000000..d73d934d97 --- /dev/null +++ b/tests/MC/ARM/mve-interleave.s.yaml @@ -0,0 +1,142 @@ +test_cases: + - + input: + bytes: [ 0x9d, 0xfc, 0x00, 0x1e, 0x90, 0xfc, 0x00, 0x1e, 0xb0, 0xfc, 0x00, 0x1e, 0x9b, 0xfc, 0x00, 0x1e, 0xb0, 0xfc, 0x00, 0xbe, 0x90, 0xfc, 0x20, 0x1e, 0xb0, 0xfc, 0x20, 0x7e, 0x90, 0xfc, 0x80, 0x1e, 0xb0, 0xfc, 0x80, 0x1e, 0x9b, 0xfc, 0x80, 0x1e, 0xb0, 0xfc, 0x80, 0xbe, 0x90, 0xfc, 0xa0, 0x1e, 0xb0, 0xfc, 0xa0, 0x7e, 0x90, 0xfc, 0x00, 0x1f, 0xb0, 0xfc, 0x00, 0x1f, 0x9b, 0xfc, 0x00, 0x1f, 0xb0, 0xfc, 0x00, 0xbf, 0x90, 0xfc, 0x20, 0x1f, 0xb0, 0xfc, 0x20, 0x7f, 0x80, 0xfc, 0x00, 0x1e, 0xa0, 0xfc, 0x00, 0x1e, 0x8b, 0xfc, 0x00, 0x1e, 0xa0, 0xfc, 0x00, 0xbe, 0x80, 0xfc, 0x20, 0x1e, 0xa0, 0xfc, 0x20, 0x7e, 0x80, 0xfc, 0x80, 0x1e, 0xa0, 0xfc, 0x80, 0x1e, 0x8b, 0xfc, 0x80, 0x1e, 0xa0, 0xfc, 0x80, 0xbe, 0x80, 0xfc, 0xa0, 0x1e, 0xa0, 0xfc, 0xa0, 0x7e, 0x80, 0xfc, 0x00, 0x1f, 0xa0, 0xfc, 0x00, 0x1f, 0x8b, 0xfc, 0x00, 0x1f, 0xa0, 0xfc, 0x00, 0xbf, 0x80, 0xfc, 0x20, 0x1f, 0xa0, 0xfc, 0x20, 0x7f, 0x90, 0xfc, 0x01, 0x1e, 0xb0, 0xfc, 0x01, 0x1e, 0x9b, 0xfc, 0x01, 0x1e, 0xb0, 0xfc, 0x01, 0x7e, 0x90, 0xfc, 0x21, 0x1e, 0xb0, 0xfc, 0x21, 0x9e, 0x90, 0xfc, 0x41, 0x1e, 0xb0, 0xfc, 0x41, 0x1e, 0x90, 0xfc, 0x61, 0x1e, 0xb0, 0xfc, 0x61, 0x9e, 0x90, 0xfc, 0x81, 0x1e, 0xb0, 0xfc, 0x81, 0x1e, 0x9b, 0xfc, 0x81, 0x1e, 0xb0, 0xfc, 0x81, 0x7e, 0x90, 0xfc, 0xa1, 0x1e, 0xb0, 0xfc, 0xa1, 0x9e, 0x90, 0xfc, 0xc1, 0x1e, 0xb0, 0xfc, 0xc1, 0x1e, 0x90, 0xfc, 0xe1, 0x1e, 0xb0, 0xfc, 0xe1, 0x9e, 0x90, 0xfc, 0x01, 0x1f, 0xb0, 0xfc, 0x01, 0x1f, 0x9b, 0xfc, 0x01, 0x1f, 0xb0, 0xfc, 0x01, 0x7f, 0x90, 0xfc, 0x21, 0x1f, 0xb0, 0xfc, 0x21, 0x9f, 0x90, 0xfc, 0x41, 0x1f, 0xb0, 0xfc, 0x41, 0x1f, 0x90, 0xfc, 0x61, 0x1f, 0xb0, 0xfc, 0x61, 0x9f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vld20.8 {q0, q1}, [sp]" + - + asm_text: "vld20.8 {q0, q1}, [r0]" + - + asm_text: "vld20.8 {q0, q1}, [r0]!" + - + asm_text: "vld20.8 {q0, q1}, [r11]" + - + asm_text: "vld20.8 {q5, q6}, [r0]!" + - + asm_text: "vld21.8 {q0, q1}, [r0]" + - + asm_text: "vld21.8 {q3, q4}, [r0]!" + - + asm_text: "vld20.16 {q0, q1}, [r0]" + - + asm_text: "vld20.16 {q0, q1}, [r0]!" + - + asm_text: "vld20.16 {q0, q1}, [r11]" + - + asm_text: "vld20.16 {q5, q6}, [r0]!" + - + asm_text: "vld21.16 {q0, q1}, [r0]" + - + asm_text: "vld21.16 {q3, q4}, [r0]!" + - + asm_text: "vld20.32 {q0, q1}, [r0]" + - + asm_text: "vld20.32 {q0, q1}, [r0]!" + - + asm_text: "vld20.32 {q0, q1}, [r11]" + - + asm_text: "vld20.32 {q5, q6}, [r0]!" + - + asm_text: "vld21.32 {q0, q1}, [r0]" + - + asm_text: "vld21.32 {q3, q4}, [r0]!" + - + asm_text: "vst20.8 {q0, q1}, [r0]" + - + asm_text: "vst20.8 {q0, q1}, [r0]!" + - + asm_text: "vst20.8 {q0, q1}, [r11]" + - + asm_text: "vst20.8 {q5, q6}, [r0]!" + - + asm_text: "vst21.8 {q0, q1}, [r0]" + - + asm_text: "vst21.8 {q3, q4}, [r0]!" + - + asm_text: "vst20.16 {q0, q1}, [r0]" + - + asm_text: "vst20.16 {q0, q1}, [r0]!" + - + asm_text: "vst20.16 {q0, q1}, [r11]" + - + asm_text: "vst20.16 {q5, q6}, [r0]!" + - + asm_text: "vst21.16 {q0, q1}, [r0]" + - + asm_text: "vst21.16 {q3, q4}, [r0]!" + - + asm_text: "vst20.32 {q0, q1}, [r0]" + - + asm_text: "vst20.32 {q0, q1}, [r0]!" + - + asm_text: "vst20.32 {q0, q1}, [r11]" + - + asm_text: "vst20.32 {q5, q6}, [r0]!" + - + asm_text: "vst21.32 {q0, q1}, [r0]" + - + asm_text: "vst21.32 {q3, q4}, [r0]!" + - + asm_text: "vld40.8 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld40.8 {q0, q1, q2, q3}, [r0]!" + - + asm_text: "vld40.8 {q0, q1, q2, q3}, [r11]" + - + asm_text: "vld40.8 {q3, q4, q5, q6}, [r0]!" + - + asm_text: "vld41.8 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld41.8 {q4, q5, q6, q7}, [r0]!" + - + asm_text: "vld42.8 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld42.8 {q0, q1, q2, q3}, [r0]!" + - + asm_text: "vld43.8 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld43.8 {q4, q5, q6, q7}, [r0]!" + - + asm_text: "vld40.16 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld40.16 {q0, q1, q2, q3}, [r0]!" + - + asm_text: "vld40.16 {q0, q1, q2, q3}, [r11]" + - + asm_text: "vld40.16 {q3, q4, q5, q6}, [r0]!" + - + asm_text: "vld41.16 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld41.16 {q4, q5, q6, q7}, [r0]!" + - + asm_text: "vld42.16 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld42.16 {q0, q1, q2, q3}, [r0]!" + - + asm_text: "vld43.16 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld43.16 {q4, q5, q6, q7}, [r0]!" + - + asm_text: "vld40.32 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld40.32 {q0, q1, q2, q3}, [r0]!" + - + asm_text: "vld40.32 {q0, q1, q2, q3}, [r11]" + - + asm_text: "vld40.32 {q3, q4, q5, q6}, [r0]!" + - + asm_text: "vld41.32 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld41.32 {q4, q5, q6, q7}, [r0]!" + - + asm_text: "vld42.32 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld42.32 {q0, q1, q2, q3}, [r0]!" + - + asm_text: "vld43.32 {q0, q1, q2, q3}, [r0]" + - + asm_text: "vld43.32 {q4, q5, q6, q7}, [r0]!" diff --git a/tests/MC/ARM/mve-load-store.s.yaml b/tests/MC/ARM/mve-load-store.s.yaml new file mode 100644 index 0000000000..363333fcb6 --- /dev/null +++ b/tests/MC/ARM/mve-load-store.s.yaml @@ -0,0 +1,892 @@ +test_cases: + - + input: + bytes: [ 0x90, 0xed, 0x00, 0x1e, 0x90, 0xed, 0x00, 0x3e, 0x9b, 0xed, 0x00, 0x1e, 0x9b, 0xed, 0x00, 0x7e, 0x94, 0xed, 0x38, 0x1e, 0x94, 0xed, 0x38, 0x9e, 0x98, 0xed, 0x38, 0x1e, 0xb4, 0xed, 0x38, 0xbe, 0xb4, 0xed, 0x38, 0xbe, 0x34, 0xec, 0x19, 0xbe, 0x3a, 0xec, 0x19, 0xbe, 0x1d, 0xed, 0x19, 0xbe, 0x1d, 0xed, 0x7f, 0xbe, 0x80, 0xed, 0x00, 0x1e, 0x80, 0xed, 0x00, 0x3e, 0x8b, 0xed, 0x00, 0x1e, 0x8b, 0xed, 0x00, 0x7e, 0x84, 0xed, 0x38, 0x1e, 0x84, 0xed, 0x38, 0x9e, 0x88, 0xed, 0x38, 0x1e, 0xa4, 0xed, 0x38, 0xbe, 0xa4, 0xed, 0x38, 0xbe, 0x24, 0xec, 0x19, 0xbe, 0x2a, 0xec, 0x19, 0xbe, 0x0d, 0xed, 0x19, 0xbe, 0x8d, 0xed, 0x7f, 0xbe, 0x90, 0xfd, 0x80, 0x0e, 0x90, 0xfd, 0x80, 0x2e, 0x97, 0xfd, 0x80, 0x0e, 0x97, 0xfd, 0x80, 0x6e, 0x94, 0xfd, 0xb8, 0x0e, 0x94, 0xfd, 0xb8, 0x8e, 0x92, 0xfd, 0xb8, 0x0e, 0xb4, 0xfd, 0xb8, 0xae, 0xb4, 0xfd, 0xb8, 0xae, 0x34, 0xfc, 0x81, 0xae, 0x33, 0xfc, 0x99, 0xae, 0x16, 0xfd, 0x99, 0xae, 0x16, 0xfd, 0xc0, 0xae, 0x90, 0xed, 0x80, 0x0e, 0x90, 0xed, 0x80, 0x2e, 0x97, 0xed, 0x80, 0x0e, 0x97, 0xed, 0x80, 0x6e, 0x94, 0xed, 0xb8, 0x0e, 0x94, 0xed, 0xb8, 0x8e, 0x92, 0xed, 0xb8, 0x0e, 0xb4, 0xed, 0xb8, 0xae, 0xb4, 0xed, 0xb8, 0xae, 0x34, 0xec, 0x99, 0xae, 0x33, 0xec, 0x99, 0xae, 0x16, 0xed, 0x99, 0xae, 0x16, 0xed, 0xc0, 0xae, 0x80, 0xed, 0x80, 0x0e, 0x80, 0xed, 0x80, 0x2e, 0x87, 0xed, 0x80, 0x0e, 0x87, 0xed, 0x80, 0x6e, 0x84, 0xed, 0xb8, 0x0e, 0x84, 0xed, 0xb8, 0x8e, 0x85, 0xed, 0xb8, 0x0e, 0xa4, 0xed, 0xb8, 0xae, 0xa4, 0xed, 0xb8, 0xae, 0x24, 0xec, 0x99, 0xae, 0x23, 0xec, 0x99, 0xae, 0x02, 0xed, 0x99, 0xae, 0x02, 0xed, 0xc0, 0xae, 0x90, 0xfd, 0x00, 0x0f, 0x90, 0xfd, 0x00, 0x2f, 0x97, 0xfd, 0x00, 0x0f, 0x97, 0xfd, 0x00, 0x6f, 0x94, 0xfd, 0x38, 0x0f, 0x94, 0xfd, 0x38, 0x8f, 0x92, 0xfd, 0x38, 0x0f, 0xb4, 0xfd, 0x38, 0xaf, 0xb4, 0xfd, 0x38, 0xaf, 0x34, 0xfc, 0x19, 0xaf, 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0xd2, 0x0f, 0x90, 0xfc, 0xd2, 0x0f, 0x90, 0xfc, 0xd2, 0x0f, 0x90, 0xfc, 0xd3, 0x0f, 0x90, 0xfc, 0xd3, 0x0f, 0x90, 0xfc, 0xd3, 0x0f, 0x80, 0xec, 0x02, 0x0e, 0x80, 0xec, 0x02, 0x0e, 0x80, 0xec, 0x92, 0x6e, 0x80, 0xec, 0x92, 0x6e, 0x80, 0xec, 0x92, 0x6e, 0x80, 0xec, 0x93, 0x0e, 0x80, 0xec, 0x93, 0x0e, 0x80, 0xec, 0x93, 0x0e, 0x80, 0xec, 0x42, 0x0f, 0x80, 0xec, 0x42, 0x0f, 0x80, 0xec, 0x42, 0x0f, 0x80, 0xec, 0x43, 0x0f, 0x80, 0xec, 0x43, 0x0f, 0x80, 0xec, 0x43, 0x0f, 0x80, 0xec, 0xd2, 0x6f, 0x80, 0xec, 0xd2, 0x6f, 0x80, 0xec, 0xd2, 0x6f, 0x80, 0xec, 0xd3, 0x0f, 0x80, 0xec, 0xd3, 0x0f, 0x80, 0xec, 0xd3, 0x0f, 0x92, 0xfd, 0x00, 0x1e, 0x92, 0xfd, 0x00, 0x1e, 0x92, 0xfd, 0x00, 0x1e, 0xb2, 0xfd, 0x00, 0xfe, 0xb2, 0xfd, 0x00, 0xfe, 0xb2, 0xfd, 0x00, 0xfe, 0x92, 0xfd, 0x01, 0xfe, 0x92, 0xfd, 0x01, 0xfe, 0x92, 0xfd, 0x01, 0xfe, 0xb2, 0xfd, 0x01, 0xfe, 0xb2, 0xfd, 0x01, 0xfe, 0xb2, 0xfd, 0x01, 0xfe, 0x82, 0xfd, 0x00, 0x1e, 0x82, 0xfd, 0x00, 0x1e, 0x82, 0xfd, 0x00, 0x1e, 0xa2, 0xfd, 0x00, 0xfe, 0xa2, 0xfd, 0x00, 0xfe, 0xa2, 0xfd, 0x00, 0xfe, 0x82, 0xfd, 0x7f, 0xfe, 0x82, 0xfd, 0x7f, 0xfe, 0x82, 0xfd, 0x7f, 0xfe, 0xa2, 0xfd, 0x42, 0xfe, 0xa2, 0xfd, 0x42, 0xfe, 0xa2, 0xfd, 0x42, 0xfe, 0x92, 0xfd, 0x00, 0x1f, 0x92, 0xfd, 0x00, 0x1f, 0x92, 0xfd, 0x00, 0x1f, 0xb2, 0xfd, 0x00, 0xff, 0xb2, 0xfd, 0x00, 0xff, 0xb2, 0xfd, 0x00, 0xff, 0x92, 0xfd, 0x01, 0xff, 0x92, 0xfd, 0x01, 0xff, 0x92, 0xfd, 0x01, 0xff, 0x32, 0xfd, 0x7f, 0xff, 0x32, 0xfd, 0x7f, 0xff, 0x32, 0xfd, 0x7f, 0xff, 0x82, 0xfd, 0x00, 0x1f, 0x82, 0xfd, 0x00, 0x1f, 0x82, 0xfd, 0x00, 0x1f, 0xa2, 0xfd, 0x00, 0xff, 0xa2, 0xfd, 0x00, 0xff, 0xa2, 0xfd, 0x00, 0xff, 0x82, 0xfd, 0x7f, 0xff, 0x82, 0xfd, 0x7f, 0xff, 0x82, 0xfd, 0x7f, 0xff, 0x22, 0xfd, 0x01, 0xff, 0x22, 0xfd, 0x01, 0xff, 0x22, 0xfd, 0x01, 0xff, 0x71, 0xfe, 0x4d, 0x8f, 0xa2, 0xfd, 0x42, 0xfe, 0x92, 0xfd, 0x01, 0xff ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vldrb.u8 q0, [r0]" + - + asm_text: "vldrb.u8 q1, [r0]" + - + asm_text: "vldrb.u8 q0, [r11]" + - + asm_text: "vldrb.u8 q3, [r11]" + - + asm_text: "vldrb.u8 q0, [r4, #0x38]" + - + asm_text: "vldrb.u8 q4, [r4, #0x38]" + - + asm_text: "vldrb.u8 q0, [r8, #0x38]" + - + asm_text: "vldrb.u8 q5, [r4, #0x38]!" + - + asm_text: "vldrb.u8 q5, [r4, #0x38]!" + - + asm_text: "vldrb.u8 q5, [r4], #-0x19" + - + asm_text: "vldrb.u8 q5, [r10], #-0x19" + - + asm_text: "vldrb.u8 q5, [sp, #-0x19]" + - + asm_text: "vldrb.u8 q5, [sp, #-0x7f]" + - + asm_text: "vstrb.8 q0, [r0]" + - + asm_text: "vstrb.8 q1, [r0]" + - + asm_text: "vstrb.8 q0, [r11]" + - + asm_text: "vstrb.8 q3, [r11]" + - + asm_text: "vstrb.8 q0, [r4, #0x38]" + - + asm_text: "vstrb.8 q4, [r4, #0x38]" + - + asm_text: "vstrb.8 q0, [r8, #0x38]" + - + asm_text: "vstrb.8 q5, [r4, #0x38]!" + - + asm_text: "vstrb.8 q5, [r4, #0x38]!" + - + asm_text: "vstrb.8 q5, [r4], #-0x19" + - + asm_text: "vstrb.8 q5, [r10], #-0x19" + - + asm_text: "vstrb.8 q5, [sp, #-0x19]" + - + asm_text: "vstrb.8 q5, [sp, #0x7f]" + - + asm_text: "vldrb.u16 q0, [r0]" + - + asm_text: "vldrb.u16 q1, [r0]" + - + asm_text: "vldrb.u16 q0, [r7]" + - + asm_text: "vldrb.u16 q3, [r7]" + - + asm_text: "vldrb.u16 q0, [r4, #0x38]" + - + asm_text: "vldrb.u16 q4, [r4, #0x38]" + - + asm_text: "vldrb.u16 q0, [r2, #0x38]" + - + asm_text: "vldrb.u16 q5, [r4, #0x38]!" + - + asm_text: "vldrb.u16 q5, [r4, #0x38]!" + - + asm_text: "vldrb.u16 q5, [r4], #-1" + - + asm_text: "vldrb.u16 q5, [r3], #-0x19" + - + asm_text: "vldrb.u16 q5, [r6, #-0x19]" + - + asm_text: "vldrb.u16 q5, [r6, #-0x40]" + - + asm_text: "vldrb.s16 q0, [r0]" + - + asm_text: "vldrb.s16 q1, [r0]" + - + asm_text: "vldrb.s16 q0, [r7]" + - + asm_text: "vldrb.s16 q3, [r7]" + - + asm_text: "vldrb.s16 q0, [r4, #0x38]" + - + asm_text: "vldrb.s16 q4, [r4, #0x38]" + - + asm_text: "vldrb.s16 q0, [r2, #0x38]" + - + asm_text: "vldrb.s16 q5, [r4, #0x38]!" + - + asm_text: "vldrb.s16 q5, [r4, #0x38]!" + - + asm_text: "vldrb.s16 q5, [r4], #-0x19" + - + asm_text: "vldrb.s16 q5, [r3], #-0x19" + - + asm_text: "vldrb.s16 q5, [r6, #-0x19]" + - + asm_text: "vldrb.s16 q5, [r6, #-0x40]" + - + asm_text: "vstrb.16 q0, [r0]" + - + asm_text: "vstrb.16 q1, [r0]" + - + asm_text: "vstrb.16 q0, [r7]" + - + asm_text: "vstrb.16 q3, [r7]" + - + asm_text: "vstrb.16 q0, [r4, #0x38]" + - + asm_text: "vstrb.16 q4, [r4, #0x38]" + - + asm_text: "vstrb.16 q0, [r5, #0x38]" + - + asm_text: "vstrb.16 q5, [r4, #0x38]!" + - + asm_text: "vstrb.16 q5, [r4, #0x38]!" + - + asm_text: "vstrb.16 q5, [r4], #-0x19" + - + asm_text: "vstrb.16 q5, [r3], #-0x19" + - + asm_text: "vstrb.16 q5, [r2, #-0x19]" + - + asm_text: "vstrb.16 q5, [r2, #-0x40]" + - + asm_text: "vldrb.u32 q0, [r0]" + - + asm_text: "vldrb.u32 q1, [r0]" + - + asm_text: "vldrb.u32 q0, [r7]" + - + asm_text: "vldrb.u32 q3, [r7]" + - + asm_text: "vldrb.u32 q0, [r4, #0x38]" + - + asm_text: "vldrb.u32 q4, [r4, #0x38]" + - + asm_text: "vldrb.u32 q0, [r2, #0x38]" + - + asm_text: "vldrb.u32 q5, [r4, #0x38]!" + - + asm_text: "vldrb.u32 q5, [r4, #0x38]!" + - + asm_text: "vldrb.u32 q5, [r4], #-0x19" + - + asm_text: "vldrb.u32 q5, [r3], #-0x19" + - + asm_text: "vldrb.u32 q5, [r6, #-0x19]" + - + asm_text: "vldrb.u32 q5, [r6, #-0x40]" + - + asm_text: "vldrb.s32 q0, [r0]" + - + asm_text: "vldrb.s32 q1, [r0]" + - + asm_text: "vldrb.s32 q0, [r7]" + - + asm_text: "vldrb.s32 q3, [r7]" + - + asm_text: "vldrb.s32 q0, [r4, #0x38]" + - + asm_text: "vldrb.s32 q4, [r4, #0x38]" + - + asm_text: "vldrb.s32 q0, [r2, #0x38]" + - + asm_text: "vldrb.s32 q5, [r4, #0x38]!" + - + asm_text: "vldrb.s32 q5, [r4, #0x38]!" + - + asm_text: "vldrb.s32 q5, [r4], #-0x19" + - + asm_text: "vldrb.s32 q5, [r3], #-0x19" + - + asm_text: "vldrb.s32 q5, [r6, #-0x19]" + - + asm_text: "vldrb.s32 q5, [r6, #-0x40]" + - + asm_text: "vstrb.32 q0, [r0]" + - + asm_text: "vstrb.32 q1, [r0]" + - + asm_text: "vstrb.32 q0, [r7]" + - + asm_text: "vstrb.32 q3, [r7]" + - + asm_text: "vstrb.32 q0, [r4, #0x38]" + - + asm_text: "vstrb.32 q4, [r4, #0x38]" + - + asm_text: "vstrb.32 q0, [r5, #0x38]" + - + asm_text: "vstrb.32 q5, [r4, #0x38]!" + - + asm_text: "vstrb.32 q5, [r4, #0x38]!" + - + asm_text: "vstrb.32 q5, [r4], #-0x19" + - + asm_text: "vstrb.32 q5, [r3], #-0x19" + - + asm_text: "vstrb.32 q5, [r2, #-0x19]" + - + asm_text: "vstrb.32 q5, [r2, #-0x40]" + - + asm_text: "vldrh.u16 q0, [r0]" + - + asm_text: "vldrh.u16 q1, [r0]" + - + asm_text: "vldrh.u16 q0, [r11]" + - + asm_text: "vldrh.u16 q3, [r11]" + - + asm_text: "vldrh.u16 q0, [r4, #0x38]" + - + asm_text: "vldrh.u16 q4, [r4, #0x38]" + - + asm_text: "vldrh.u16 q0, [r8, #0x38]" + - + asm_text: "vldrh.u16 q5, [r4, #0x38]!" + - + asm_text: "vldrh.u16 q5, [r4, #0x38]!" + - + asm_text: "vldrh.u16 q5, [r4], #-0x1a" + - + asm_text: "vldrh.u16 q5, [r10], #-0x1a" + - + asm_text: "vldrh.u16 q5, [sp, #-0x1a]" + - + asm_text: "vldrh.u16 q5, [sp, #-0x40]" + - + asm_text: "vldrh.u16 q5, [sp, #-0xfe]" + - + asm_text: "vldrh.u16 q5, [r10], #0xfe" + - + asm_text: "vstrh.16 q0, [r0]" + - + asm_text: "vstrh.16 q1, [r0]" + - + asm_text: "vstrh.16 q0, [r11]" + - + asm_text: "vstrh.16 q3, [r11]" + - + asm_text: "vstrh.16 q0, [r4, #0x38]" + - + asm_text: "vstrh.16 q4, [r4, #0x38]" + - + asm_text: "vstrh.16 q0, [r8, #0x38]" + - + asm_text: "vstrh.16 q5, [r4, #0x38]!" + - + asm_text: "vstrh.16 q5, [r4, #0x38]!" + - + asm_text: "vstrh.16 q5, [r4], #-0x1a" + - + asm_text: "vstrh.16 q5, [r10], #-0x1a" + - + asm_text: "vstrh.16 q5, [sp, #-0x1a]" + - + asm_text: "vstrh.16 q5, [sp, #-0x40]" + - + asm_text: "vstrh.16 q5, [sp, #-0xfe]" + - + asm_text: "vstrh.16 q5, [r10], #0xfe" + - + asm_text: "vldrh.u32 q0, [r0]" + - + asm_text: "vldrh.u32 q1, [r0]" + - + asm_text: "vldrh.u32 q0, [r7]" + - + asm_text: "vldrh.u32 q3, [r7]" + - + asm_text: "vldrh.u32 q0, [r4, #0x38]" + - + asm_text: "vldrh.u32 q4, [r4, #0x38]" + - + asm_text: "vldrh.u32 q0, [r2, #0x38]" + - + asm_text: "vldrh.u32 q5, [r4, #0x38]!" + - + asm_text: "vldrh.u32 q5, [r4, #0x38]!" + - + asm_text: "vldrh.u32 q5, [r4], #-0x1a" + - + asm_text: "vldrh.u32 q5, [r3], #-0x1a" + - + asm_text: "vldrh.u32 q5, [r6, #-0x1a]" + - + asm_text: "vldrh.u32 q5, [r6, #-0x40]" + - + asm_text: "vldrh.u32 q5, [r6, #-0xfe]" + - + asm_text: "vldrh.u32 q5, [r4, #0xfe]!" + - + asm_text: "vldrh.s32 q0, [r0]" + - + asm_text: "vldrh.s32 q1, [r0]" + - + asm_text: "vldrh.s32 q0, [r7]" + - + asm_text: "vldrh.s32 q3, [r7]" + - + asm_text: "vldrh.s32 q0, [r4, #0x38]" + - + asm_text: "vldrh.s32 q4, [r4, #0x38]" + - + asm_text: "vldrh.s32 q0, [r2, #0x38]" + - + asm_text: "vldrh.s32 q5, [r4, #0x38]!" + - + asm_text: "vldrh.s32 q5, [r4, #0x38]!" + - + asm_text: "vldrh.s32 q5, [r4], #-0x1a" + - + asm_text: "vldrh.s32 q5, [r3], #-0x1a" + - + asm_text: "vldrh.s32 q5, [r6, #-0x1a]" + - + asm_text: "vldrh.s32 q5, [r6, #-0x40]" + - + asm_text: "vldrh.s32 q5, [r6, #-0xfe]" + - + asm_text: "vldrh.s32 q5, [r4, #0xfe]!" + - + asm_text: "vstrh.32 q0, [r0]" + - + asm_text: "vstrh.32 q1, [r0]" + - + asm_text: "vstrh.32 q0, [r7]" + - + asm_text: "vstrh.32 q3, [r7]" + - + asm_text: "vstrh.32 q0, [r4, #0x38]" + - + asm_text: "vstrh.32 q4, [r4, #0x38]" + - + asm_text: "vstrh.32 q0, [r5, #0x38]" + - + asm_text: "vstrh.32 q5, [r4, #0x38]!" + - + asm_text: "vstrh.32 q5, [r4, #0x38]!" + - + asm_text: "vstrh.32 q5, [r4], #-0x1a" + - + asm_text: "vstrh.32 q5, [r3], #-0x1a" + - + asm_text: "vstrh.32 q5, [r2, #-0x1a]" + - + asm_text: "vstrh.32 q5, [r2, #-0x40]" + - + asm_text: "vstrh.32 q5, [r2, #-0xfe]" + - + asm_text: "vstrh.32 q5, [r4, #0xfe]!" + - + asm_text: "vldrw.u32 q0, [r0]" + - + asm_text: "vldrw.u32 q1, [r0]" + - + asm_text: "vldrw.u32 q0, [r11]" + - + asm_text: "vldrw.u32 q3, [r11]" + - + asm_text: "vldrw.u32 q0, [r4, #0x38]" + - + asm_text: "vldrw.u32 q4, [r4, #0x38]" + - + asm_text: "vldrw.u32 q0, [r8, #0x38]" + - + asm_text: "vldrw.u32 q5, [r4, #0x38]!" + - + asm_text: "vldrw.u32 q5, [r4, #0x38]!" + - + asm_text: "vldrw.u32 q5, [r4], #-0x1c" + - + asm_text: "vldrw.u32 q5, [r10], #-0x1c" + - + asm_text: "vldrw.u32 q5, [sp, #-0x1c]" + - + asm_text: "vldrw.u32 q5, [sp, #-0x40]" + - + asm_text: "vldrw.u32 q5, [sp, #-0x1fc]" + - + asm_text: "vldrw.u32 q5, [r4, #0x1fc]!" + - + asm_text: "vstrw.32 q0, [r0]" + - + asm_text: "vstrw.32 q1, [r0]" + - + asm_text: "vstrw.32 q0, [r11]" + - + asm_text: "vstrw.32 q3, [r11]" + - + asm_text: "vstrw.32 q0, [r4, #0x38]" + - + asm_text: "vstrw.32 q4, [r4, #0x38]" + - + asm_text: "vstrw.32 q0, [r8, #0x38]" + - + asm_text: "vstrw.32 q5, [r4, #0x38]!" + - + asm_text: "vstrw.32 q5, [r4, #0x38]!" + - + asm_text: "vstrw.32 q5, [r4], #-0x1c" + - + asm_text: "vstrw.32 q5, [r10], #-0x1c" + - + asm_text: "vstrw.32 q5, [sp, #-0x1c]" + - + asm_text: "vstrw.32 q5, [sp, #-0x40]" + - + asm_text: "vstrw.32 q5, [sp, #-0x1fc]" + - + asm_text: "vstrw.32 q5, [r4, #0x1fc]!" + - + asm_text: "vldrb.u8 q0, [r0, q1]" + - + asm_text: "vldrb.u8 q3, [r10, q1]" + - + asm_text: "vldrb.u16 q0, [r0, q1]" + - + asm_text: "vldrb.u16 q3, [r9, q1]" + - + asm_text: "vldrb.s16 q0, [r0, q1]" + - + asm_text: "vldrb.s16 q3, [sp, q1]" + - + asm_text: "vldrb.u32 q0, [r0, q1]" + - + asm_text: "vldrb.u32 q3, [r0, q1]" + - + asm_text: "vldrb.s32 q0, [r0, q1]" + - + asm_text: "vldrb.s32 q3, [r0, q1]" + - + asm_text: "vldrh.u16 q0, [r0, q1]" + - + asm_text: "vldrh.u16 q3, [r0, q1]" + - + asm_text: "vldrh.u32 q0, [r0, q1]" + - + asm_text: "vldrh.u32 q3, [r0, q1]" + - + asm_text: "vldrh.s32 q0, [r0, q1]" + - + asm_text: "vldrh.s32 q3, [r0, q1]" + - + asm_text: "vldrh.u16 q0, [r0, q1, uxtw #1]" + - + asm_text: "vldrw.u32 q0, [r0, q1]" + - + asm_text: "vldrw.u32 q3, [r0, q1]" + - + asm_text: "vldrw.u32 q0, [r0, q1, uxtw #2]" + - + asm_text: "vldrw.u32 q0, [sp, q1, uxtw #2]" + - + asm_text: "vldrd.u64 q0, [r0, q1]" + - + asm_text: "vldrd.u64 q3, [r0, q1]" + - + asm_text: "vldrd.u64 q0, [r0, q1, uxtw #3]" + - + asm_text: "vldrd.u64 q0, [sp, q1, uxtw #3]" + - + asm_text: "vstrb.8 q0, [r0, q1]" + - + asm_text: "vstrb.8 q3, [r10, q1]" + - + asm_text: "vstrb.8 q3, [r0, q3]" + - + asm_text: "vstrb.16 q0, [r0, q1]" + - + asm_text: "vstrb.16 q3, [sp, q1]" + - + asm_text: "vstrb.16 q3, [r0, q3]" + - + asm_text: "vstrb.32 q0, [r0, q1]" + - + asm_text: "vstrb.32 q3, [r0, q1]" + - + asm_text: "vstrb.32 q3, [r0, q3]" + - + asm_text: "vstrh.16 q0, [r0, q1]" + - + asm_text: "vstrh.16 q3, [r0, q1]" + - + asm_text: "vstrh.16 q3, [r0, q3]" + - + asm_text: "vstrh.32 q0, [r0, q1]" + - + asm_text: "vstrh.32 q3, [r0, q1]" + - + asm_text: "vstrh.32 q3, [r0, q3]" + - + asm_text: "vstrh.16 q0, [r0, q1, uxtw #1]" + - + asm_text: "vstrh.32 q3, [r8, q3, uxtw #1]" + - + asm_text: "vstrw.32 q0, [r0, q1]" + - + asm_text: "vstrw.32 q3, [r0, q1]" + - + asm_text: "vstrw.32 q3, [r0, q3]" + - + asm_text: "vstrw.32 q0, [r0, q1, uxtw #2]" + - + asm_text: "vstrw.32 q0, [sp, q1, uxtw #2]" + - + asm_text: "vstrd.64 q0, [r0, q1]" + - + asm_text: "vstrd.64 q3, [r0, q1]" + - + asm_text: "vstrd.64 q3, [r0, q3]" + - + asm_text: "vstrd.64 q0, [r0, q1, uxtw #3]" + - + asm_text: "vstrd.64 q0, [sp, q1, uxtw #3]" + - + asm_text: "vldrw.u32 q0, [q1]" + - + asm_text: "vldrw.u32 q7, [q1]" + - + asm_text: "vldrw.u32 q7, [q1]!" + - + asm_text: "vldrw.u32 q7, [q1, #4]" + - + asm_text: "vldrw.u32 q7, [q1, #-4]" + - + asm_text: "vldrw.u32 q7, [q1, #0x1fc]" + - + asm_text: "vldrw.u32 q7, [q1, #-0x1fc]" + - + asm_text: "vldrw.u32 q7, [q1, #0x108]" + - + asm_text: "vldrw.u32 q7, [q1, #4]!" + - + asm_text: "vstrw.32 q0, [q1]" + - + asm_text: "vstrw.32 q1, [q1]" + - + asm_text: "vstrw.32 q7, [q1]" + - + asm_text: "vstrw.32 q7, [q1]!" + - + asm_text: "vstrw.32 q7, [q7]" + - + asm_text: "vstrw.32 q7, [q1, #4]" + - + asm_text: "vstrw.32 q7, [q1, #-4]" + - + asm_text: "vstrw.32 q7, [q1, #0x1fc]" + - + asm_text: "vstrw.32 q7, [q1, #-0x1fc]" + - + asm_text: "vstrw.32 q7, [q1, #0x108]!" + - + asm_text: "vldrd.u64 q0, [q1]" + - + asm_text: "vldrd.u64 q7, [q1]" + - + asm_text: "vldrd.u64 q7, [q1]!" + - + asm_text: "vldrd.u64 q7, [q1, #8]" + - + asm_text: "vldrd.u64 q7, [q1, #-8]" + - + asm_text: "vldrd.u64 q7, [q1, #0x3f8]" + - + asm_text: "vldrd.u64 q7, [q1, #-0x3f8]" + - + asm_text: "vldrd.u64 q7, [q1, #0x108]" + - + asm_text: "vldrd.u64 q7, [q1, #0x270]" + - + asm_text: "vldrd.u64 q7, [q1, #0x108]" + - + asm_text: "vldrd.u64 q7, [q1, #-0x3f8]!" + - + asm_text: "vstrd.64 q0, [q1]" + - + asm_text: "vstrd.64 q1, [q1]" + - + asm_text: "vstrd.64 q7, [q1]" + - + asm_text: "vstrd.64 q7, [q1]!" + - + asm_text: "vstrd.64 q7, [q7]" + - + asm_text: "vstrd.64 q7, [q1, #8]" + - + asm_text: "vstrd.64 q7, [q1, #-8]!" + - + asm_text: "vstrd.64 q7, [q1, #0x3f8]" + - + asm_text: "vstrd.64 q7, [q1, #-0x3f8]" + - + asm_text: "vstrd.64 q7, [q1, #0x108]" + - + asm_text: "vstrd.64 q7, [q1, #0x270]" + - + asm_text: "vstrd.64 q7, [q1, #0x108]" + - + asm_text: "vldrb.u8 q0, [r0]" + - + asm_text: "vldrb.u8 q0, [r0]" + - + asm_text: "vldrb.u8 q0, [r8, #0x38]" + - + asm_text: "vldrb.u8 q0, [r8, #0x38]" + - + asm_text: "vldrb.u8 q5, [r4, #0x38]!" + - + asm_text: "vldrb.u8 q5, [r4, #0x38]!" + - + asm_text: "vstrb.8 q0, [r0]" + - + asm_text: "vstrb.8 q0, [r0]" + - + asm_text: "vstrb.8 q4, [r4, #0x38]" + - + asm_text: "vstrb.8 q4, [r4, #0x38]" + - + asm_text: "vstrb.8 q5, [r4, #0x38]!" + - + asm_text: "vstrb.8 q5, [r4, #0x38]!" + - + asm_text: "vldrh.u16 q0, [r0]" + - + asm_text: "vldrh.u16 q0, [r0]" + - + asm_text: "vldrh.u16 q0, [r0]" + - + asm_text: "vldrh.u16 q0, [r4, #0x38]" + - + asm_text: "vldrh.u16 q0, [r4, #0x38]" + - + asm_text: "vldrh.u16 q0, [r4, #0x38]" + - + asm_text: "vldrh.u16 q5, [r4, #0x38]!" + - + asm_text: "vldrh.u16 q5, [r4, #0x38]!" + - + asm_text: "vldrh.u16 q5, [r4, #0x38]!" + - + asm_text: "vstrh.16 q0, [r0]" + - + asm_text: "vstrh.16 q0, [r0]" + - + asm_text: "vstrh.16 q0, [r0]" + - + asm_text: "vstrh.16 q0, [r4, #0x38]" + - + asm_text: "vstrh.16 q0, [r4, #0x38]" + - + asm_text: "vstrh.16 q0, [r4, #0x38]" + - + asm_text: "vstrh.16 q5, [r4, #0x38]!" + - + asm_text: "vstrh.16 q5, [r4, #0x38]!" + - + asm_text: "vstrh.16 q5, [r4, #0x38]!" + - + asm_text: "vldrw.u32 q0, [r0]" + - + asm_text: "vldrw.u32 q0, [r0]" + - + asm_text: "vldrw.u32 q0, [r0]" + - + asm_text: "vldrw.u32 q0, [r4, #0x38]" + - + asm_text: "vldrw.u32 q0, [r4, #0x38]" + - + asm_text: "vldrw.u32 q0, [r4, #0x38]" + - + asm_text: "vldrw.u32 q5, [r4, #0x38]!" + - + asm_text: "vldrw.u32 q5, [r4, #0x38]!" + - + asm_text: "vldrw.u32 q5, [r4, #0x38]!" + - + asm_text: "vstrw.32 q0, [r0]" + - + asm_text: "vstrw.32 q0, [r0]" + - + asm_text: "vstrw.32 q0, [r0]" + - + asm_text: "vstrw.32 q0, [r4, #0x38]" + - + asm_text: "vstrw.32 q0, [r4, #0x38]" + - + asm_text: "vstrw.32 q0, [r4, #0x38]" + - + asm_text: "vstrw.32 q5, [r4, #0x38]!" + - + asm_text: "vstrw.32 q5, [r4, #0x38]!" + - + asm_text: "vstrw.32 q5, [r4, #0x38]!" + - + asm_text: "vldrb.u8 q0, [r0, q1]" + - + asm_text: "vldrb.u8 q0, [r0, q1]" + - + asm_text: "vldrh.u16 q3, [r0, q1]" + - + asm_text: "vldrh.u16 q3, [r0, q1]" + - + asm_text: "vldrh.u16 q3, [r0, q1]" + - + asm_text: "vldrh.u16 q0, [r0, q1, uxtw #1]" + - + asm_text: "vldrh.u16 q0, [r0, q1, uxtw #1]" + - + asm_text: "vldrh.u16 q0, [r0, q1, uxtw #1]" + - + asm_text: "vldrw.u32 q0, [r0, q1]" + - + asm_text: "vldrw.u32 q0, [r0, q1]" + - + asm_text: "vldrw.u32 q0, [r0, q1]" + - + asm_text: "vldrw.u32 q0, [r0, q1, uxtw #2]" + - + asm_text: "vldrw.u32 q0, [r0, q1, uxtw #2]" + - + asm_text: "vldrw.u32 q0, [r0, q1, uxtw #2]" + - + asm_text: "vldrd.u64 q0, [r0, q1]" + - + asm_text: "vldrd.u64 q0, [r0, q1]" + - + asm_text: "vldrd.u64 q0, [r0, q1]" + - + asm_text: "vldrd.u64 q0, [r0, q1, uxtw #3]" + - + asm_text: "vldrd.u64 q0, [r0, q1, uxtw #3]" + - + asm_text: "vldrd.u64 q0, [r0, q1, uxtw #3]" + - + asm_text: "vstrb.8 q0, [r0, q1]" + - + asm_text: "vstrb.8 q0, [r0, q1]" + - + asm_text: "vstrh.16 q3, [r0, q1]" + - + asm_text: "vstrh.16 q3, [r0, q1]" + - + asm_text: "vstrh.16 q3, [r0, q1]" + - + asm_text: "vstrh.16 q0, [r0, q1, uxtw #1]" + - + asm_text: "vstrh.16 q0, [r0, q1, uxtw #1]" + - + asm_text: "vstrh.16 q0, [r0, q1, uxtw #1]" + - + asm_text: "vstrw.32 q0, [r0, q1]" + - + asm_text: "vstrw.32 q0, [r0, q1]" + - + asm_text: "vstrw.32 q0, [r0, q1]" + - + asm_text: "vstrw.32 q0, [r0, q1, uxtw #2]" + - + asm_text: "vstrw.32 q0, [r0, q1, uxtw #2]" + - + asm_text: "vstrw.32 q0, [r0, q1, uxtw #2]" + - + asm_text: "vstrd.64 q3, [r0, q1]" + - + asm_text: "vstrd.64 q3, [r0, q1]" + - + asm_text: "vstrd.64 q3, [r0, q1]" + - + asm_text: "vstrd.64 q0, [r0, q1, uxtw #3]" + - + asm_text: "vstrd.64 q0, [r0, q1, uxtw #3]" + - + asm_text: "vstrd.64 q0, [r0, q1, uxtw #3]" + - + asm_text: "vldrw.u32 q0, [q1]" + - + asm_text: "vldrw.u32 q0, [q1]" + - + asm_text: "vldrw.u32 q0, [q1]" + - + asm_text: "vldrw.u32 q7, [q1]!" + - + asm_text: "vldrw.u32 q7, [q1]!" + - + asm_text: "vldrw.u32 q7, [q1]!" + - + asm_text: "vldrw.u32 q7, [q1, #4]" + - + asm_text: "vldrw.u32 q7, [q1, #4]" + - + asm_text: "vldrw.u32 q7, [q1, #4]" + - + asm_text: "vldrw.u32 q7, [q1, #4]!" + - + asm_text: "vldrw.u32 q7, [q1, #4]!" + - + asm_text: "vldrw.u32 q7, [q1, #4]!" + - + asm_text: "vstrw.32 q0, [q1]" + - + asm_text: "vstrw.32 q0, [q1]" + - + asm_text: "vstrw.32 q0, [q1]" + - + asm_text: "vstrw.32 q7, [q1]!" + - + asm_text: "vstrw.32 q7, [q1]!" + - + asm_text: "vstrw.32 q7, [q1]!" + - + asm_text: "vstrw.32 q7, [q1, #0x1fc]" + - + asm_text: "vstrw.32 q7, [q1, #0x1fc]" + - + asm_text: "vstrw.32 q7, [q1, #0x1fc]" + - + asm_text: "vstrw.32 q7, [q1, #0x108]!" + - + asm_text: "vstrw.32 q7, [q1, #0x108]!" + - + asm_text: "vstrw.32 q7, [q1, #0x108]!" + - + asm_text: "vldrd.u64 q0, [q1]" + - + asm_text: "vldrd.u64 q0, [q1]" + - + asm_text: "vldrd.u64 q0, [q1]" + - + asm_text: "vldrd.u64 q7, [q1]!" + - + asm_text: "vldrd.u64 q7, [q1]!" + - + asm_text: "vldrd.u64 q7, [q1]!" + - + asm_text: "vldrd.u64 q7, [q1, #8]" + - + asm_text: "vldrd.u64 q7, [q1, #8]" + - + asm_text: "vldrd.u64 q7, [q1, #8]" + - + asm_text: "vldrd.u64 q7, [q1, #-0x3f8]!" + - + asm_text: "vldrd.u64 q7, [q1, #-0x3f8]!" + - + asm_text: "vldrd.u64 q7, [q1, #-0x3f8]!" + - + asm_text: "vstrd.64 q0, [q1]" + - + asm_text: "vstrd.64 q0, [q1]" + - + asm_text: "vstrd.64 q0, [q1]" + - + asm_text: "vstrd.64 q7, [q1]!" + - + asm_text: "vstrd.64 q7, [q1]!" + - + asm_text: "vstrd.64 q7, [q1]!" + - + asm_text: "vstrd.64 q7, [q1, #0x3f8]" + - + asm_text: "vstrd.64 q7, [q1, #0x3f8]" + - + asm_text: "vstrd.64 q7, [q1, #0x3f8]" + - + asm_text: "vstrd.64 q7, [q1, #-8]!" + - + asm_text: "vstrd.64 q7, [q1, #-8]!" + - + asm_text: "vstrd.64 q7, [q1, #-8]!" + - + asm_text: "vpste" + - + asm_text: "vstrwt.32 q7, [q1, #0x108]!" + - + asm_text: "vldrde.u64 q7, [q1, #8]" diff --git a/tests/MC/ARM/mve-minmax.s.yaml b/tests/MC/ARM/mve-minmax.s.yaml new file mode 100644 index 0000000000..53d8e241b3 --- /dev/null +++ b/tests/MC/ARM/mve-minmax.s.yaml @@ -0,0 +1,42 @@ +test_cases: + - + input: + bytes: [ 0x02, 0xff, 0x58, 0x0f, 0x30, 0xff, 0x52, 0x6f, 0x00, 0xef, 0x5e, 0x66, 0x12, 0xef, 0x54, 0x06, 0x22, 0xef, 0x54, 0x06, 0x02, 0xff, 0x54, 0x06, 0x12, 0xff, 0x54, 0x06, 0x22, 0xff, 0x54, 0x06, 0x00, 0xef, 0x4e, 0x66, 0x12, 0xef, 0x44, 0x06, 0x22, 0xef, 0x44, 0x06, 0x02, 0xff, 0x44, 0x06, 0x12, 0xff, 0x44, 0x06, 0x22, 0xff, 0x44, 0x06, 0x71, 0xfe, 0x4d, 0x8f, 0x02, 0xef, 0x54, 0x06, 0x12, 0xef, 0x54, 0x06 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmaxnm.f32 q0, q1, q4" + - + asm_text: "vminnm.f16 q3, q0, q1" + - + asm_text: "vmin.s8 q3, q0, q7" + - + asm_text: "vmin.s16 q0, q1, q2" + - + asm_text: "vmin.s32 q0, q1, q2" + - + asm_text: "vmin.u8 q0, q1, q2" + - + asm_text: "vmin.u16 q0, q1, q2" + - + asm_text: "vmin.u32 q0, q1, q2" + - + asm_text: "vmax.s8 q3, q0, q7" + - + asm_text: "vmax.s16 q0, q1, q2" + - + asm_text: "vmax.s32 q0, q1, q2" + - + asm_text: "vmax.u8 q0, q1, q2" + - + asm_text: "vmax.u16 q0, q1, q2" + - + asm_text: "vmax.u32 q0, q1, q2" + - + asm_text: "vpste" + - + asm_text: "vmint.s8 q0, q1, q2" + - + asm_text: "vmine.s16 q0, q1, q2" diff --git a/tests/MC/ARM/mve-misc.s.yaml b/tests/MC/ARM/mve-misc.s.yaml new file mode 100644 index 0000000000..ed291285a8 --- /dev/null +++ b/tests/MC/ARM/mve-misc.s.yaml @@ -0,0 +1,66 @@ +test_cases: + - + input: + bytes: [ 0x3b, 0xfe, 0x05, 0x0f, 0x31, 0xfe, 0x4d, 0x0f, 0x00, 0xf0, 0x43, 0xc3, 0x10, 0xf0, 0x43, 0xc3, 0x24, 0xf0, 0x49, 0xcd, 0x3e, 0xf0, 0xe9, 0xcd, 0x05, 0xf0, 0xb7, 0xc6, 0x11, 0xf0, 0x13, 0xc2, 0x27, 0xf0, 0xe3, 0xc7, 0x01, 0xf0, 0x0d, 0xc9, 0x0a, 0xf0, 0xbf, 0xc2, 0x0a, 0xf0, 0xc1, 0xc2, 0x0a, 0xf0, 0x9b, 0xcc, 0x0a, 0xf0, 0xfb, 0xcf, 0x0b, 0xf0, 0xd1, 0xca, 0x35, 0xf0, 0x01, 0xc0, 0x05, 0xf0, 0x01, 0xe0, 0x15, 0xf0, 0x01, 0xe0, 0x27, 0xf0, 0x01, 0xe0, 0x32, 0xf0, 0x01, 0xe0, 0x1f, 0xf0, 0x01, 0xc8, 0x1f, 0xf0, 0x05, 0xc0, 0x1f, 0xf0, 0xff, 0xcf, 0x0f, 0xf0, 0x01, 0xe0, 0x08, 0xbf, 0x0f, 0xf0, 0x01, 0xe0, 0x71, 0xfe, 0x4d, 0x8f, 0x33, 0xfe, 0x05, 0x0f, 0x33, 0xfe, 0x05, 0x0f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vpsel q0, q5, q2" + - + asm_text: "vpnot" + - + asm_text: "wlstp.8 lr, r0, #0x684" + - + asm_text: "wlstp.16 lr, r0, #0x684" + - + asm_text: "wlstp.32 lr, r4, #0xa92" + - + asm_text: "wlstp.64 lr, lr, #0xbd2" + - + asm_text: "wlstp.8 lr, r5, #0xd6c" + - + asm_text: "wlstp.16 lr, r1, #0x424" + - + asm_text: "wlstp.32 lr, r7, #0xfc4" + - + asm_text: "wlstp.8 lr, r1, #0x21a" + - + asm_text: "wlstp.8 lr, r10, #0x57c" + - + asm_text: "wlstp.8 lr, r10, #0x580" + - + asm_text: "wlstp.8 lr, r10, #0x936" + - + asm_text: "wlstp.8 lr, r10, #0xff6" + - + asm_text: "wlstp.8 lr, r11, #0x5a2" + - + asm_text: "wlstp.64 lr, r5, #0" + - + asm_text: "dlstp.8 lr, r5" + - + asm_text: "dlstp.16 lr, r5" + - + asm_text: "dlstp.32 lr, r7" + - + asm_text: "dlstp.64 lr, r2" + - + asm_text: "letp lr, #-2" + - + asm_text: "letp lr, #-8" + - + asm_text: "letp lr, #-0xffe" + - + asm_text: "lctp" + - + asm_text: "it eq" + - + asm_text: "lctpeq" + - + asm_text: "vpste" + - + asm_text: "vpselt q0, q1, q2" + - + asm_text: "vpsele q0, q1, q2" diff --git a/tests/MC/ARM/mve-qdest-qsrc.s.yaml b/tests/MC/ARM/mve-qdest-qsrc.s.yaml new file mode 100644 index 0000000000..98ecfc2efd --- /dev/null +++ b/tests/MC/ARM/mve-qdest-qsrc.s.yaml @@ -0,0 +1,276 @@ +test_cases: + - + input: + bytes: [ 0x3f, 0xee, 0x09, 0x2e, 0x3f, 0xfe, 0x03, 0x1e, 0xb2, 0xee, 0xc0, 0x0b, 0xf3, 0xee, 0xc2, 0x0b, 0x3f, 0xee, 0x09, 0x3e, 0x0c, 0xee, 0x0c, 0x3e, 0x12, 0xee, 0x08, 0x1e, 0x26, 0xee, 0x0e, 0x1e, 0x02, 0xee, 0x02, 0x0e, 0x14, 0xee, 0x04, 0x0e, 0x2a, 0xee, 0x0e, 0x2e, 0x0e, 0xee, 0x01, 0x1e, 0x10, 0xee, 0x03, 0x1e, 0x20, 0xee, 0x09, 0x3e, 0x22, 0xee, 0x01, 0x3e, 0x20, 0xee, 0x03, 0x3e, 0x0c, 0xee, 0x05, 0x0e, 0x1a, 0xee, 0x09, 0x2e, 0x24, 0xee, 0x05, 0x0e, 0x08, 0xfe, 0x0e, 0x3e, 0x14, 0xfe, 0x0a, 0x1e, 0x28, 0xfe, 0x0c, 0x7e, 0x06, 0xfe, 0x0c, 0x0e, 0x18, 0xfe, 0x02, 0x0e, 0x2a, 0xfe, 0x00, 0x4e, 0x06, 0xfe, 0x03, 0x1e, 0x12, 0xfe, 0x09, 0x1e, 0x2c, 0xfe, 0x07, 0x3e, 0x06, 0xfe, 0x01, 0x6e, 0x1e, 0xfe, 0x09, 0x0e, 0x2c, 0xfe, 0x0f, 0x0e, 0x20, 0xfe, 0x0f, 0x0e, 0x2c, 0xfe, 0x01, 0x0e, 0x32, 0xee, 0x05, 0x0e, 0x34, 0xee, 0x0a, 0xce, 0x30, 0xee, 0x0b, 0x2e, 0x30, 0xee, 0x0a, 0x3e, 0x30, 0xee, 0x0b, 0x3e, 0x30, 0xee, 0x03, 0x3e, 0x3e, 0xfe, 0x0a, 0x2e, 0x38, 0xfe, 0x05, 0x6e, 0x32, 0xfe, 0x06, 0xbe, 0x3e, 0xfe, 0x09, 0x1e, 0x0d, 0xee, 0x00, 0x4e, 0x19, 0xee, 0x06, 0x6e, 0x2b, 0xee, 0x0c, 0x6e, 0x0d, 0xee, 0x04, 0x1e, 0x11, 0xee, 0x04, 0x1e, 0x29, 0xee, 0x08, 0x5e, 0x37, 0xee, 0x0e, 0x4e, 0x33, 0xfe, 0x06, 0x0e, 0x33, 0xee, 0x0e, 0x3e, 0x3f, 0xfe, 0x0e, 0x1e, 0x09, 0xee, 0x0b, 0x0e, 0x1f, 0xee, 0x09, 0x0e, 0x2f, 0xee, 0x09, 0x0e, 0x0b, 0xfe, 0x05, 0x6e, 0x1f, 0xfe, 0x09, 0x4e, 0x27, 0xfe, 0x05, 0x2e, 0x03, 0xee, 0x05, 0x3e, 0x13, 0xee, 0x05, 0x3e, 0x23, 0xee, 0x01, 0x7e, 0x0d, 0xfe, 0x01, 0x3e, 0x17, 0xfe, 0x0d, 0x9e, 0x25, 0xfe, 0x05, 0x3e, 0x33, 0xee, 0x03, 0x0e, 0x33, 0xee, 0x01, 0x5e, 0x37, 0xee, 0x0b, 0x0e, 0x37, 0xee, 0x03, 0x1e, 0x33, 0xfe, 0x09, 0x0e, 0x33, 0xfe, 0x0f, 0x1e, 0x37, 0xfe, 0x09, 0x0e, 0x37, 0xfe, 0x05, 0x1e, 0x3f, 0xee, 0x09, 0x2e, 0x3f, 0xee, 0x09, 0x3e, 0x3f, 0xfe, 0x07, 0x0e, 0x3f, 0xfe, 0x03, 0x1e, 0x31, 0xee, 0x87, 0x0e, 0x31, 0xee, 0x83, 0x9e, 0x35, 0xee, 0x8f, 0x2e, 0x35, 0xee, 0x85, 0x1e, 0x31, 0xfe, 0x8b, 0x2e, 0x31, 0xfe, 0x81, 0x1e, 0x35, 0xfe, 0x81, 0x2e, 0x35, 0xfe, 0x87, 0x7e, 0x0e, 0xee, 0x0a, 0x6f, 0x10, 0xee, 0x0c, 0x0f, 0x10, 0xee, 0x0c, 0x0f, 0x12, 0xee, 0x00, 0x7f, 0x28, 0xee, 0x0a, 0x6f, 0x2e, 0xee, 0x04, 0xdf, 0x30, 0xee, 0x04, 0x2f, 0x32, 0xee, 0x02, 0x1f, 0x00, 0xfe, 0x04, 0x2f, 0x14, 0xfe, 0x06, 0x0f, 0x1a, 0xfe, 0x0a, 0x1f, 0x24, 0xfe, 0x0a, 0x8f, 0x2a, 0xfe, 0x00, 0xbf, 0x32, 0xfe, 0x02, 0x6f, 0x3c, 0xfe, 0x04, 0x5f, 0x38, 0xee, 0x0b, 0x0f, 0x3c, 0xee, 0x0b, 0x1f, 0x36, 0xfe, 0x0f, 0x0f, 0x3e, 0xfe, 0x0b, 0x1f, 0x32, 0xee, 0x01, 0x0f, 0x30, 0xee, 0x0b, 0x1f, 0x32, 0xee, 0x05, 0x1f, 0x30, 0xee, 0x60, 0x0f, 0x20, 0xfe, 0x02, 0x1f, 0x90, 0xfd, 0x42, 0x08, 0x20, 0xee, 0x02, 0x1f, 0x10, 0xee, 0x02, 0x1f, 0xb0, 0xff, 0xc0, 0x00, 0x71, 0xfe, 0x4d, 0x8f, 0x32, 0xfe, 0x05, 0x1f, 0x32, 0xee, 0x05, 0x0f, 0x71, 0xfe, 0x4d, 0x8f, 0x33, 0xee, 0x04, 0x1e, 0x33, 0xfe, 0x04, 0x0e, 0x71, 0xfe, 0x4d, 0x8f, 0x32, 0xee, 0x04, 0x1e, 0x32, 0xee, 0x04, 0x1e, 0x71, 0xfe, 0x4d, 0xcf, 0x3f, 0xee, 0x03, 0x0e, 0xb7, 0xff, 0x42, 0x01, 0x77, 0xee, 0xc1, 0x9f, 0x3f, 0xee, 0x01, 0x5e, 0x3f, 0xfe, 0x01, 0x3e, 0x77, 0xee, 0xc1, 0x9f, 0x3f, 0xee, 0x01, 0x4e, 0x3f, 0xfe, 0x01, 0x2e, 0x0c, 0xbf, 0xb3, 0xee, 0xe0, 0x0a, 0xb3, 0xee, 0xe0, 0x0a ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vcvtb.f16.f32 q1, q4" + - + asm_text: "vcvtt.f32.f16 q0, q1" + - + asm_text: "vcvtt.f64.f16 d0, s0" + - + asm_text: "vcvtt.f16.f64 s1, d2" + - + asm_text: "vcvtt.f16.f32 q1, q4" + - + asm_text: "vqdmladhx.s8 q1, q6, q6" + - + asm_text: "vqdmladhx.s16 q0, q1, q4" + - + asm_text: "vqdmladhx.s32 q0, q3, q7" + - + asm_text: "vqdmladh.s8 q0, q1, q1" + - + asm_text: "vqdmladh.s16 q0, q2, q2" + - + asm_text: "vqdmladh.s32 q1, q5, q7" + - + asm_text: "vqrdmladhx.s8 q0, q7, q0" + - + asm_text: "vqrdmladhx.s16 q0, q0, q1" + - + asm_text: "vqrdmladhx.s32 q1, q0, q4" + - + asm_text: "vqrdmladhx.s32 q1, q1, q0" + - + asm_text: "vqrdmladhx.s32 q1, q0, q1" + - + asm_text: "vqrdmladh.s8 q0, q6, q2" + - + asm_text: "vqrdmladh.s16 q1, q5, q4" + - + asm_text: "vqrdmladh.s32 q0, q2, q2" + - + asm_text: "vqdmlsdhx.s8 q1, q4, q7" + - + asm_text: "vqdmlsdhx.s16 q0, q2, q5" + - + asm_text: "vqdmlsdhx.s32 q3, q4, q6" + - + asm_text: "vqdmlsdh.s8 q0, q3, q6" + - + asm_text: "vqdmlsdh.s16 q0, q4, q1" + - + asm_text: "vqdmlsdh.s32 q2, q5, q0" + - + asm_text: "vqrdmlsdhx.s8 q0, q3, q1" + - + asm_text: "vqrdmlsdhx.s16 q0, q1, q4" + - + asm_text: "vqrdmlsdhx.s32 q1, q6, q3" + - + asm_text: "vqrdmlsdh.s8 q3, q3, q0" + - + asm_text: "vqrdmlsdh.s16 q0, q7, q4" + - + asm_text: "vqrdmlsdh.s32 q0, q6, q7" + - + asm_text: "vqrdmlsdh.s32 q0, q0, q7" + - + asm_text: "vqrdmlsdh.s32 q0, q6, q0" + - + asm_text: "vcmul.f16 q0, q1, q2, #0x5a" + - + asm_text: "vcmul.f16 q6, q2, q5, #0" + - + asm_text: "vcmul.f16 q1, q0, q5, #0x5a" + - + asm_text: "vcmul.f16 q1, q0, q5, #0xb4" + - + asm_text: "vcmul.f16 q1, q0, q5, #0x10e" + - + asm_text: "vcmul.f16 q1, q0, q1, #0x10e" + - + asm_text: "vcmul.f32 q1, q7, q5, #0" + - + asm_text: "vcmul.f32 q3, q4, q2, #0x5a" + - + asm_text: "vcmul.f32 q5, q1, q3, #0xb4" + - + asm_text: "vcmul.f32 q0, q7, q4, #0x10e" + - + asm_text: "vmullb.s8 q2, q6, q0" + - + asm_text: "vmullb.s16 q3, q4, q3" + - + asm_text: "vmullb.s32 q3, q5, q6" + - + asm_text: "vmullt.s8 q0, q6, q2" + - + asm_text: "vmullt.s16 q0, q0, q2" + - + asm_text: "vmullt.s32 q2, q4, q4" + - + asm_text: "vmullb.p8 q2, q3, q7" + - + asm_text: "vmullb.p16 q0, q1, q3" + - + asm_text: "vmullt.p8 q1, q1, q7" + - + asm_text: "vmullt.p16 q0, q7, q7" + - + asm_text: "vmulh.s8 q0, q4, q5" + - + asm_text: "vmulh.s16 q0, q7, q4" + - + asm_text: "vmulh.s32 q0, q7, q4" + - + asm_text: "vmulh.u8 q3, q5, q2" + - + asm_text: "vmulh.u16 q2, q7, q4" + - + asm_text: "vmulh.u32 q1, q3, q2" + - + asm_text: "vrmulh.s8 q1, q1, q2" + - + asm_text: "vrmulh.s16 q1, q1, q2" + - + asm_text: "vrmulh.s32 q3, q1, q0" + - + asm_text: "vrmulh.u8 q1, q6, q0" + - + asm_text: "vrmulh.u16 q4, q3, q6" + - + asm_text: "vrmulh.u32 q1, q2, q2" + - + asm_text: "vqmovnb.s16 q0, q1" + - + asm_text: "vqmovnt.s16 q2, q0" + - + asm_text: "vqmovnb.s32 q0, q5" + - + asm_text: "vqmovnt.s32 q0, q1" + - + asm_text: "vqmovnb.u16 q0, q4" + - + asm_text: "vqmovnt.u16 q0, q7" + - + asm_text: "vqmovnb.u32 q0, q4" + - + asm_text: "vqmovnt.u32 q0, q2" + - + asm_text: "vcvtb.f16.f32 q1, q4" + - + asm_text: "vcvtt.f16.f32 q1, q4" + - + asm_text: "vcvtb.f32.f16 q0, q3" + - + asm_text: "vcvtt.f32.f16 q0, q1" + - + asm_text: "vqmovunb.s16 q0, q3" + - + asm_text: "vqmovunt.s16 q4, q1" + - + asm_text: "vqmovunb.s32 q1, q7" + - + asm_text: "vqmovunt.s32 q0, q2" + - + asm_text: "vmovnb.i16 q1, q5" + - + asm_text: "vmovnt.i16 q0, q0" + - + asm_text: "vmovnb.i32 q1, q0" + - + asm_text: "vmovnt.i32 q3, q3" + - + asm_text: "vhcadd.s8 q3, q7, q5, #0x5a" + - + asm_text: "vhcadd.s16 q0, q0, q6, #0x5a" + - + asm_text: "vhcadd.s16 q0, q0, q6, #0x5a" + - + asm_text: "vhcadd.s16 q3, q1, q0, #0x10e" + - + asm_text: "vhcadd.s32 q3, q4, q5, #0x5a" + - + asm_text: "vhcadd.s32 q6, q7, q2, #0x10e" + - + asm_text: "vadc.i32 q1, q0, q2" + - + asm_text: "vadci.i32 q0, q1, q1" + - + asm_text: "vcadd.i8 q1, q0, q2, #0x5a" + - + asm_text: "vcadd.i16 q0, q2, q3, #0x5a" + - + asm_text: "vcadd.i16 q0, q5, q5, #0x10e" + - + asm_text: "vcadd.i32 q4, q2, q5, #0x5a" + - + asm_text: "vcadd.i32 q5, q5, q0, #0x10e" + - + asm_text: "vsbc.i32 q3, q1, q1" + - + asm_text: "vsbci.i32 q2, q6, q2" + - + asm_text: "vqdmullb.s16 q0, q4, q5" + - + asm_text: "vqdmullt.s16 q0, q6, q5" + - + asm_text: "vqdmullb.s32 q0, q3, q7" + - + asm_text: "vqdmullt.s32 q0, q7, q5" + - + asm_text: "vqdmullb.s16 q0, q1, q0" + - + asm_text: "vqdmullt.s16 q0, q0, q5" + - + asm_text: "vqdmullt.s16 q0, q1, q2" + - + asm_text: "vqdmullb.s16 q0, q0, r0" + - + asm_text: "vcadd.i32 q0, q0, q1, #0x10e" + - + asm_text: "vcadd.f32 q0, q0, q1, #0x10e" + - + asm_text: "vhcadd.s32 q0, q0, q1, #0x10e" + - + asm_text: "vhcadd.s16 q0, q0, q1, #0x10e" + - + asm_text: "vrev32.8 q0, q0" + - + asm_text: "vpste" + - + asm_text: "vqdmulltt.s32 q0, q1, q2" + - + asm_text: "vqdmullbe.s16 q0, q1, q2" + - + asm_text: "vpste" + - + asm_text: "vmulltt.p8 q0, q1, q2" + - + asm_text: "vmullbe.p16 q0, q1, q2" + - + asm_text: "vpste" + - + asm_text: "vcmult.f16 q0, q1, q2, #0xb4" + - + asm_text: "vcmule.f16 q0, q1, q2, #0xb4" + - + asm_text: "vpstet" + - + asm_text: "vcvtbt.f16.f32 q0, q1" + - + asm_text: "vcvtne.s16.f16 q0, q1" + - + asm_text: "vpte.f32 lt, q3, r1" + - + asm_text: "vcvttt.f16.f32 q2, q0" + - + asm_text: "vcvtte.f32.f16 q1, q0" + - + asm_text: "vpte.f32 lt, q3, r1" + - + asm_text: "vcvtbt.f16.f32 q2, q0" + - + asm_text: "vcvtbe.f32.f16 q1, q0" + - + asm_text: "ite eq" + - + asm_text: "vcvtteq.f16.f32 s0, s1" + - + asm_text: "vcvttne.f16.f32 s0, s1" diff --git a/tests/MC/ARM/mve-qdest-rsrc.s.yaml b/tests/MC/ARM/mve-qdest-rsrc.s.yaml new file mode 100644 index 0000000000..8e23f31dbc --- /dev/null +++ b/tests/MC/ARM/mve-qdest-rsrc.s.yaml @@ -0,0 +1,292 @@ +test_cases: + - + input: + bytes: [ 0x07, 0xee, 0x43, 0x1f, 0x1f, 0xee, 0x4e, 0x1f, 0x2b, 0xee, 0x4a, 0x3f, 0x09, 0xee, 0x47, 0x2f, 0x1d, 0xee, 0x4b, 0x0f, 0x23, 0xee, 0x46, 0x0f, 0x04, 0xee, 0x68, 0x5f, 0x18, 0xee, 0x60, 0x3f, 0x24, 0xee, 0x60, 0x1f, 0x02, 0xfe, 0x62, 0x1f, 0x14, 0xfe, 0x66, 0x1f, 0x24, 0xfe, 0x62, 0x1f, 0x0c, 0xee, 0x61, 0x0f, 0x18, 0xee, 0x62, 0x6f, 0x2a, 0xee, 0x6b, 0x0f, 0x02, 0xfe, 0x68, 0x0f, 0x1a, 0xfe, 0x69, 0x0f, 0x20, 0xfe, 0x67, 0x0f, 0x32, 0xee, 0x66, 0x0f, 0x36, 0xfe, 0x0f, 0x0f, 0x32, 0xee, 0x60, 0x1f, 0x38, 0xfe, 0x65, 0x1f, 0x36, 0xfe, 0x47, 0x1f, 0x32, 0xee, 0x4a, 0x3f, 0x32, 0xfe, 0x4e, 0x0f, 0x38, 0xee, 0x44, 0x2f, 0x06, 0xee, 0x4e, 0x1f, 0x10, 0xee, 0x46, 0x1f, 0x24, 0xee, 0x47, 0x3f, 0x0c, 0xfe, 0x45, 0x3f, 0x18, 0xfe, 0x4a, 0x1f, 0x28, 0xfe, 0x4c, 0x1f, 0x04, 0xee, 0x41, 0x0f, 0x14, 0xee, 0x41, 0x0f, 0x20, 0xee, 0x4a, 0x0f, 0x0a, 0xfe, 0x4e, 0x0f, 0x14, 0xfe, 0x42, 0x2f, 0x24, 0xfe, 0x4b, 0x0f, 0x33, 0xee, 0xe0, 0x1e, 0x37, 0xee, 0xe3, 0x1e, 0x3b, 0xee, 0xee, 0x1e, 0x33, 0xfe, 0xe0, 0x1e, 0x37, 0xfe, 0xe2, 0x1e, 0x3b, 0xfe, 0xe3, 0x1e, 0x31, 0xee, 0xe0, 0x1e, 0x35, 0xee, 0xe1, 0x3e, 0x39, 0xee, 0xe3, 0x1e, 0x31, 0xfe, 0xe1, 0x1e, 0x35, 0xfe, 0xeb, 0x1e, 0x39, 0xfe, 0xee, 0x1e, 0x33, 0xee, 0x66, 0x1e, 0x37, 0xee, 0x6e, 0x1e, 0x3b, 0xee, 0x64, 0x1e, 0x33, 0xfe, 0x60, 0x1e, 0x37, 0xfe, 0x6a, 0x1e, 0x3b, 0xfe, 0x61, 0x1e, 0x31, 0xee, 0x6e, 0x1e, 0x35, 0xee, 0x6e, 0x1e, 0x39, 0xee, 0x61, 0x1e, 0x31, 0xfe, 0x6a, 0x1e, 0x35, 0xfe, 0x6a, 0x3e, 0x39, 0xfe, 0x6c, 0x1e, 0x09, 0xfe, 0x68, 0x1e, 0x13, 0xfe, 0x61, 0x1e, 0x2d, 0xfe, 0x60, 0x1e, 0x01, 0xee, 0x6c, 0x1e, 0x19, 0xee, 0x67, 0x1e, 0x23, 0xee, 0x6b, 0x1e, 0x31, 0xfe, 0x6a, 0x0e, 0x33, 0xee, 0x67, 0x0e, 0x03, 0xee, 0x66, 0x0e, 0x15, 0xee, 0x62, 0x0e, 0x27, 0xee, 0x68, 0x2e, 0x05, 0xfe, 0x66, 0x0e, 0x11, 0xfe, 0x62, 0x0e, 0x21, 0xfe, 0x62, 0x0e, 0x31, 0xfe, 0x4c, 0x1e, 0x37, 0xee, 0x4e, 0x1e, 0x01, 0xee, 0x46, 0x1e, 0x15, 0xee, 0x49, 0x1e, 0x2f, 0xee, 0x46, 0x1e, 0x01, 0xee, 0x46, 0x1e, 0x15, 0xee, 0x49, 0x1e, 0x2f, 0xee, 0x46, 0x1e, 0x0b, 0xee, 0x4e, 0x1e, 0x17, 0xee, 0x4c, 0x1e, 0x23, 0xee, 0x4b, 0x3e, 0x33, 0xfe, 0x46, 0x2e, 0x39, 0xee, 0x46, 0xfe, 0x07, 0xee, 0x48, 0x0e, 0x17, 0xee, 0x4a, 0x2e, 0x27, 0xee, 0x41, 0x2e, 0x07, 0xee, 0x48, 0x0e, 0x17, 0xee, 0x4a, 0x2e, 0x27, 0xee, 0x41, 0x2e, 0x0f, 0xee, 0x4a, 0x0e, 0x11, 0xee, 0x47, 0x0e, 0x2d, 0xee, 0x4a, 0x2e, 0x00, 0xee, 0x65, 0x1e, 0x1a, 0xee, 0x6e, 0x1e, 0x24, 0xee, 0x63, 0x1e, 0x06, 0xee, 0x63, 0x0e, 0x16, 0xee, 0x69, 0xae, 0x22, 0xee, 0x6b, 0x0e, 0x0a, 0xee, 0x4a, 0x1e, 0x16, 0xee, 0x42, 0x1e, 0x20, 0xee, 0x44, 0x1e, 0x0a, 0xee, 0x4b, 0x0e, 0x14, 0xee, 0x4a, 0x0e, 0x28, 0xee, 0x4b, 0x0e, 0x0f, 0xee, 0x60, 0x0f, 0x1b, 0xee, 0xe1, 0x2f, 0x2b, 0xee, 0xe4, 0xcf, 0x0d, 0xee, 0xeb, 0x1f, 0x1d, 0xee, 0x61, 0x1f, 0x21, 0xee, 0xe7, 0x1f, 0x0f, 0xee, 0x6f, 0x0f, 0x1f, 0xee, 0xee, 0x0f, 0x2d, 0xee, 0x6e, 0x0f, 0x05, 0xee, 0xee, 0x1f, 0x1b, 0xee, 0xee, 0x1f, 0x21, 0xee, 0xef, 0x5f, 0x0e, 0xf0, 0x01, 0xe8, 0x10, 0xf0, 0x01, 0xe8, 0x2a, 0xf0, 0x01, 0xe8, 0x31, 0xf0, 0x01, 0xe8, 0x71, 0xfe, 0x4d, 0x8f, 0x02, 0xef, 0x54, 0x09, 0x12, 0xef, 0x54, 0x09, 0x71, 0xfe, 0x4d, 0x8f, 0x12, 0xef, 0x54, 0x09, 0x14, 0xef, 0x56, 0x29, 0x3b, 0xfe, 0xe0, 0x1e, 0x71, 0xfe, 0x4d, 0x8f, 0x37, 0xfe, 0xe0, 0x1e, 0x14, 0xef, 0x52, 0x05, 0x71, 0xfe, 0x4d, 0x8f, 0x14, 0xff, 0x42, 0x05, 0x3b, 0xee, 0x60, 0x1e, 0x71, 0xfe, 0x4d, 0x8f, 0x31, 0xee, 0x60, 0x1e, 0x39, 0xfe, 0x60, 0x1e ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vsub.i8 q0, q3, r3" + - + asm_text: "vsub.i16 q0, q7, lr" + - + asm_text: "vsub.i32 q1, q5, r10" + - + asm_text: "vadd.i8 q1, q4, r7" + - + asm_text: "vadd.i16 q0, q6, r11" + - + asm_text: "vadd.i32 q0, q1, r6" + - + asm_text: "vqsub.s8 q2, q2, r8" + - + asm_text: "vqsub.s16 q1, q4, r0" + - + asm_text: "vqsub.s32 q0, q2, r0" + - + asm_text: "vqsub.u8 q0, q1, r2" + - + asm_text: "vqsub.u16 q0, q2, r6" + - + asm_text: "vqsub.u32 q0, q2, r2" + - + asm_text: "vqadd.s8 q0, q6, r1" + - + asm_text: "vqadd.s16 q3, q4, r2" + - + asm_text: "vqadd.s32 q0, q5, r11" + - + asm_text: "vqadd.u8 q0, q1, r8" + - + asm_text: "vqadd.u16 q0, q5, r9" + - + asm_text: "vqadd.u32 q0, q0, r7" + - + asm_text: "vqdmullb.s16 q0, q1, r6" + - + asm_text: "vqdmullb.s32 q0, q3, q7" + - + asm_text: "vqdmullt.s16 q0, q1, r0" + - + asm_text: "vqdmullt.s32 q0, q4, r5" + - + asm_text: "vsub.f16 q0, q3, r7" + - + asm_text: "vsub.f32 q1, q1, r10" + - + asm_text: "vadd.f16 q0, q1, lr" + - + asm_text: "vadd.f32 q1, q4, r4" + - + asm_text: "vhsub.s8 q0, q3, lr" + - + asm_text: "vhsub.s16 q0, q0, r6" + - + asm_text: "vhsub.s32 q1, q2, r7" + - + asm_text: "vhsub.u8 q1, q6, r5" + - + asm_text: "vhsub.u16 q0, q4, r10" + - + asm_text: "vhsub.u32 q0, q4, r12" + - + asm_text: "vhadd.s8 q0, q2, r1" + - + asm_text: "vhadd.s16 q0, q2, r1" + - + asm_text: "vhadd.s32 q0, q0, r10" + - + asm_text: "vhadd.u8 q0, q5, lr" + - + asm_text: "vhadd.u16 q1, q2, r2" + - + asm_text: "vhadd.u32 q0, q2, r11" + - + asm_text: "vqrshl.s8 q0, r0" + - + asm_text: "vqrshl.s16 q0, r3" + - + asm_text: "vqrshl.s32 q0, lr" + - + asm_text: "vqrshl.u8 q0, r0" + - + asm_text: "vqrshl.u16 q0, r2" + - + asm_text: "vqrshl.u32 q0, r3" + - + asm_text: "vqshl.s8 q0, r0" + - + asm_text: "vqshl.s16 q1, r1" + - + asm_text: "vqshl.s32 q0, r3" + - + asm_text: "vqshl.u8 q0, r1" + - + asm_text: "vqshl.u16 q0, r11" + - + asm_text: "vqshl.u32 q0, lr" + - + asm_text: "vrshl.s8 q0, r6" + - + asm_text: "vrshl.s16 q0, lr" + - + asm_text: "vrshl.s32 q0, r4" + - + asm_text: "vrshl.u8 q0, r0" + - + asm_text: "vrshl.u16 q0, r10" + - + asm_text: "vrshl.u32 q0, r1" + - + asm_text: "vshl.s8 q0, lr" + - + asm_text: "vshl.s16 q0, lr" + - + asm_text: "vshl.s32 q0, r1" + - + asm_text: "vshl.u8 q0, r10" + - + asm_text: "vshl.u16 q1, r10" + - + asm_text: "vshl.u32 q0, r12" + - + asm_text: "vbrsr.8 q0, q4, r8" + - + asm_text: "vbrsr.16 q0, q1, r1" + - + asm_text: "vbrsr.32 q0, q6, r0" + - + asm_text: "vmul.i8 q0, q0, r12" + - + asm_text: "vmul.i16 q0, q4, r7" + - + asm_text: "vmul.i32 q0, q1, r11" + - + asm_text: "vmul.f16 q0, q0, r10" + - + asm_text: "vmul.f32 q0, q1, r7" + - + asm_text: "vqdmulh.s8 q0, q1, r6" + - + asm_text: "vqdmulh.s16 q0, q2, r2" + - + asm_text: "vqdmulh.s32 q1, q3, r8" + - + asm_text: "vqrdmulh.s8 q0, q2, r6" + - + asm_text: "vqrdmulh.s16 q0, q0, r2" + - + asm_text: "vqrdmulh.s32 q0, q0, r2" + - + asm_text: "vfmas.f16 q0, q0, r12" + - + asm_text: "vfmas.f32 q0, q3, lr" + - + asm_text: "vmlas.i8 q0, q0, r6" + - + asm_text: "vmlas.i16 q0, q2, r9" + - + asm_text: "vmlas.i32 q0, q7, r6" + - + asm_text: "vmlas.i8 q0, q0, r6" + - + asm_text: "vmlas.i16 q0, q2, r9" + - + asm_text: "vmlas.i32 q0, q7, r6" + - + asm_text: "vmlas.i8 q0, q5, lr" + - + asm_text: "vmlas.i16 q0, q3, r12" + - + asm_text: "vmlas.i32 q1, q1, r11" + - + asm_text: "vfma.f16 q1, q1, r6" + - + asm_text: "vfmas.f32 q7, q4, r6" + - + asm_text: "vmla.i8 q0, q3, r8" + - + asm_text: "vmla.i16 q1, q3, r10" + - + asm_text: "vmla.i32 q1, q3, r1" + - + asm_text: "vmla.i8 q0, q3, r8" + - + asm_text: "vmla.i16 q1, q3, r10" + - + asm_text: "vmla.i32 q1, q3, r1" + - + asm_text: "vmla.i8 q0, q7, r10" + - + asm_text: "vmla.i16 q0, q0, r7" + - + asm_text: "vmla.i32 q1, q6, r10" + - + asm_text: "vqdmlash.s8 q0, q0, r5" + - + asm_text: "vqdmlash.s16 q0, q5, lr" + - + asm_text: "vqdmlash.s32 q0, q2, r3" + - + asm_text: "vqdmlah.s8 q0, q3, r3" + - + asm_text: "vqdmlah.s16 q5, q3, r9" + - + asm_text: "vqdmlah.s32 q0, q1, r11" + - + asm_text: "vqrdmlash.s8 q0, q5, r10" + - + asm_text: "vqrdmlash.s16 q0, q3, r2" + - + asm_text: "vqrdmlash.s32 q0, q0, r4" + - + asm_text: "vqrdmlah.s8 q0, q5, r11" + - + asm_text: "vqrdmlah.s16 q0, q2, r10" + - + asm_text: "vqrdmlah.s32 q0, q4, r11" + - + asm_text: "viwdup.u8 q0, lr, r1, #1" + - + asm_text: "viwdup.u16 q1, r10, r1, #8" + - + asm_text: "viwdup.u32 q6, r10, r5, #4" + - + asm_text: "vdwdup.u8 q0, r12, r11, #8" + - + asm_text: "vdwdup.u16 q0, r12, r1, #2" + - + asm_text: "vdwdup.u32 q0, r0, r7, #8" + - + asm_text: "vidup.u8 q0, lr, #2" + - + asm_text: "vidup.u16 q0, lr, #4" + - + asm_text: "vidup.u32 q0, r12, #1" + - + asm_text: "vddup.u8 q0, r4, #4" + - + asm_text: "vddup.u16 q0, r10, #4" + - + asm_text: "vddup.u32 q2, r0, #8" + - + asm_text: "vctp.8 lr" + - + asm_text: "vctp.16 r0" + - + asm_text: "vctp.32 r10" + - + asm_text: "vctp.64 r1" + - + asm_text: "vpste" + - + asm_text: "vmult.i8 q0, q1, q2" + - + asm_text: "vmule.i16 q0, q1, q2" + - + asm_text: "vpste" + - + asm_text: "vmult.i16 q0, q1, q2" + - + asm_text: "vmule.i16 q1, q2, q3" + - + asm_text: "vqrshl.u32 q0, r0" + - + asm_text: "vpste" + - + asm_text: "vqrshlt.u16 q0, r0" + - + asm_text: "vqrshle.s16 q0, q1, q2" + - + asm_text: "vpste" + - + asm_text: "vrshlt.u16 q0, q1, q2" + - + asm_text: "vrshle.s32 q0, r0" + - + asm_text: "vpste" + - + asm_text: "vshlt.s8 q0, r0" + - + asm_text: "vshle.u32 q0, r0" diff --git a/tests/MC/ARM/mve-reductions-fp.s.yaml b/tests/MC/ARM/mve-reductions-fp.s.yaml new file mode 100644 index 0000000000..192574b7c4 --- /dev/null +++ b/tests/MC/ARM/mve-reductions-fp.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0xee, 0xfe, 0x86, 0xef, 0xee, 0xee, 0x82, 0xef, 0xec, 0xfe, 0x80, 0xef, 0xec, 0xee, 0x86, 0xef, 0xee, 0xfe, 0x02, 0xef, 0xee, 0xee, 0x02, 0xaf, 0xec, 0xfe, 0x0c, 0x0f, 0xec, 0xee, 0x0e, 0xef ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vminnmv.f16 lr, q3" + - + asm_text: "vminnmv.f32 lr, q1" + - + asm_text: "vminnmav.f16 lr, q0" + - + asm_text: "vminnmav.f32 lr, q3" + - + asm_text: "vmaxnmv.f16 lr, q1" + - + asm_text: "vmaxnmv.f32 r10, q1" + - + asm_text: "vmaxnmav.f16 r0, q6" + - + asm_text: "vmaxnmav.f32 lr, q7" diff --git a/tests/MC/ARM/mve-reductions.s.yaml b/tests/MC/ARM/mve-reductions.s.yaml new file mode 100644 index 0000000000..989b9fd4bc --- /dev/null +++ b/tests/MC/ARM/mve-reductions.s.yaml @@ -0,0 +1,118 @@ +test_cases: + - + input: + bytes: [ 0x82, 0xee, 0x07, 0x0f, 0x92, 0xee, 0x07, 0x0f, 0xa2, 0xee, 0x07, 0x0f, 0x82, 0xfe, 0x07, 0x0f, 0x92, 0xfe, 0x07, 0x0f, 0xa2, 0xfe, 0x07, 0x0f, 0xf5, 0xee, 0x00, 0xef, 0xf5, 0xee, 0x0c, 0x0f, 0xf5, 0xee, 0x20, 0xef, 0xc9, 0xee, 0x04, 0x0f, 0x89, 0xfe, 0x02, 0x0f, 0xe2, 0xee, 0x80, 0xef, 0xe6, 0xee, 0x80, 0xef, 0xea, 0xee, 0x84, 0xef, 0xe2, 0xfe, 0x80, 0x0f, 0xea, 0xfe, 0x86, 0xaf, 0xe4, 0xee, 0x80, 0x0f, 0xe0, 0xee, 0x82, 0x0f, 0xe8, 0xee, 0x82, 0xef, 0xe2, 0xee, 0x08, 0xef, 0xe6, 0xee, 0x00, 0xef, 0xea, 0xee, 0x02, 0x1f, 0xe2, 0xfe, 0x08, 0x0f, 0xe6, 0xfe, 0x02, 0x0f, 0xea, 0xfe, 0x00, 0x1f, 0xe0, 0xee, 0x0c, 0xef, 0xe4, 0xee, 0x0c, 0x0f, 0xe8, 0xee, 0x0e, 0xaf, 0xf0, 0xee, 0x0e, 0xee, 0xf1, 0xee, 0x08, 0xee, 0xf0, 0xfe, 0x0e, 0xee, 0xf1, 0xfe, 0x00, 0xee, 0xf0, 0xee, 0x28, 0xee, 0xf0, 0xee, 0x0e, 0x1e, 0xf0, 0xee, 0x2e, 0xfe, 0xf6, 0xee, 0x00, 0xef, 0xf2, 0xfe, 0x0e, 0xef, 0x8c, 0xee, 0x04, 0xef, 0x8a, 0xfe, 0x04, 0xef, 0x8a, 0xfe, 0x04, 0xef, 0x86, 0xee, 0x20, 0xff, 0xdc, 0xfe, 0x0b, 0xee, 0xf0, 0xee, 0x07, 0xee, 0x8c, 0xee, 0x04, 0xef, 0x8a, 0xfe, 0x04, 0xef, 0x86, 0xee, 0x2c, 0xef, 0x8e, 0xfe, 0x22, 0xef, 0xf0, 0xee, 0x07, 0xee, 0xf5, 0xee, 0x0d, 0xee, 0xf2, 0xee, 0x29, 0xfe, 0xf0, 0xee, 0x0e, 0xee, 0x88, 0xee, 0x02, 0xee, 0xd9, 0xee, 0x02, 0xee, 0x8f, 0xee, 0x0c, 0x0e, 0xda, 0xfe, 0x08, 0xee ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vabav.s8 r0, q1, q3" + - + asm_text: "vabav.s16 r0, q1, q3" + - + asm_text: "vabav.s32 r0, q1, q3" + - + asm_text: "vabav.u8 r0, q1, q3" + - + asm_text: "vabav.u16 r0, q1, q3" + - + asm_text: "vabav.u32 r0, q1, q3" + - + asm_text: "vaddv.s16 lr, q0" + - + asm_text: "vaddv.s16 r0, q6" + - + asm_text: "vaddva.s16 lr, q0" + - + asm_text: "vaddlv.s32 r0, r9, q2" + - + asm_text: "vaddlv.u32 r0, r1, q1" + - + asm_text: "vminv.s8 lr, q0" + - + asm_text: "vminv.s16 lr, q0" + - + asm_text: "vminv.s32 lr, q2" + - + asm_text: "vminv.u8 r0, q0" + - + asm_text: "vminv.u32 r10, q3" + - + asm_text: "vminav.s16 r0, q0" + - + asm_text: "vminav.s8 r0, q1" + - + asm_text: "vminav.s32 lr, q1" + - + asm_text: "vmaxv.s8 lr, q4" + - + asm_text: "vmaxv.s16 lr, q0" + - + asm_text: "vmaxv.s32 r1, q1" + - + asm_text: "vmaxv.u8 r0, q4" + - + asm_text: "vmaxv.u16 r0, q1" + - + asm_text: "vmaxv.u32 r1, q0" + - + asm_text: "vmaxav.s8 lr, q6" + - + asm_text: "vmaxav.s16 r0, q6" + - + asm_text: "vmaxav.s32 r10, q7" + - + asm_text: "vmlav.s16 lr, q0, q7" + - + asm_text: "vmlav.s32 lr, q0, q4" + - + asm_text: "vmlav.u16 lr, q0, q7" + - + asm_text: "vmlav.u32 lr, q0, q0" + - + asm_text: "vmlava.s16 lr, q0, q4" + - + asm_text: "vmladavx.s16 r0, q0, q7" + - + asm_text: "vmladavax.s16 lr, q0, q7" + - + asm_text: "vmlav.s8 lr, q3, q0" + - + asm_text: "vmlav.u8 lr, q1, q7" + - + asm_text: "vrmlalvh.s32 lr, r1, q6, q2" + - + asm_text: "vrmlalvh.u32 lr, r1, q5, q2" + - + asm_text: "vrmlalvh.u32 lr, r1, q5, q2" + - + asm_text: "vrmlaldavhax.s32 lr, r1, q3, q0" + - + asm_text: "vrmlsldavh.s32 lr, r11, q6, q5" + - + asm_text: "vmlsdav.s16 lr, q0, q3" + - + asm_text: "vrmlalvh.s32 lr, r1, q6, q2" + - + asm_text: "vrmlalvh.u32 lr, r1, q5, q2" + - + asm_text: "vrmlalvha.s32 lr, r1, q3, q6" + - + asm_text: "vrmlalvha.u32 lr, r1, q7, q1" + - + asm_text: "vmlsdav.s16 lr, q0, q3" + - + asm_text: "vmlsdav.s32 lr, q2, q6" + - + asm_text: "vmlsdavax.s16 lr, q1, q4" + - + asm_text: "vmlav.s16 lr, q0, q7" + - + asm_text: "vmlalv.s16 lr, r1, q4, q1" + - + asm_text: "vmlalv.s32 lr, r11, q4, q1" + - + asm_text: "vmlalv.s32 r0, r1, q7, q6" + - + asm_text: "vmlalv.u16 lr, r11, q5, q4" diff --git a/tests/MC/ARM/mve-scalar-shift.s.yaml b/tests/MC/ARM/mve-scalar-shift.s.yaml new file mode 100644 index 0000000000..44ad6d761a --- /dev/null +++ b/tests/MC/ARM/mve-scalar-shift.s.yaml @@ -0,0 +1,68 @@ +test_cases: + - + input: + bytes: [ 0x50, 0xea, 0xef, 0x51, 0x5e, 0xea, 0xef, 0x61, 0x50, 0xea, 0x2d, 0x41, 0x52, 0xea, 0x22, 0x9e, 0x57, 0xea, 0x47, 0x9e, 0x5c, 0xea, 0x3c, 0xae, 0x5a, 0xea, 0x3a, 0xbe, 0x59, 0xea, 0x7b, 0x89, 0x5f, 0xea, 0x1f, 0x9e, 0x5f, 0xea, 0x3f, 0xae, 0x5a, 0xea, 0xd7, 0x9e, 0x55, 0xea, 0x2f, 0xae, 0x52, 0xea, 0x42, 0xae, 0x51, 0xea, 0x7b, 0xbe, 0x5e, 0xea, 0xcf, 0x21, 0x5e, 0xea, 0x0d, 0x41, 0x5e, 0xea, 0x1f, 0x31, 0x5e, 0xea, 0x2d, 0xcf, 0x5b, 0xea, 0x2d, 0xcf, 0x5f, 0xea, 0x2d, 0x83, 0x5e, 0xea, 0x7f, 0x4f, 0x5f, 0xea, 0x3f, 0x7b, 0x5e, 0xea, 0xef, 0x2f, 0x5f, 0xea, 0xef, 0x5b, 0x5e, 0xea, 0x0d, 0x1f, 0x5f, 0xea, 0x8d, 0x41, 0x50, 0xea, 0x4f, 0x0f, 0x5f, 0xea, 0xcf, 0x17, 0x50, 0xea, 0x9f, 0x2f, 0x51, 0xea, 0x5f, 0x79 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "asrl r0, r1, #0x17" + - + asm_text: "asrl lr, r1, #0x1b" + - + asm_text: "asrl r0, r1, r4" + - + asm_text: "cinc lr, r2, lo" + - + asm_text: "cinc lr, r7, pl" + - + asm_text: "cinv lr, r12, hs" + - + asm_text: "cneg lr, r10, hs" + - + asm_text: "csel r9, r9, r11, vc" + - + asm_text: "cset lr, eq" + - + asm_text: "csetm lr, hs" + - + asm_text: "csinc lr, r10, r7, le" + - + asm_text: "csinv lr, r5, zr, hs" + - + asm_text: "cinv lr, r2, pl" + - + asm_text: "csneg lr, r1, r11, vc" + - + asm_text: "lsll lr, r1, #0xb" + - + asm_text: "lsll lr, r1, r4" + - + asm_text: "lsrl lr, r1, #0xc" + - + asm_text: "sqrshr lr, r12" + - + asm_text: "sqrshr r11, r12" + - + asm_text: "sqrshrl lr, r3, #0x40, r8" + - + asm_text: "sqshl lr, #0x11" + - + asm_text: "sqshll lr, r11, #0x1c" + - + asm_text: "srshr lr, #0xb" + - + asm_text: "srshrl lr, r11, #0x17" + - + asm_text: "uqrshl lr, r1" + - + asm_text: "uqrshll lr, r1, #0x30, r4" + - + asm_text: "uqshl r0, #1" + - + asm_text: "uqshll lr, r7, #7" + - + asm_text: "urshr r0, #0xa" + - + asm_text: "urshrl r0, r9, #0x1d" diff --git a/tests/MC/ARM/mve-shifts.s.yaml b/tests/MC/ARM/mve-shifts.s.yaml new file mode 100644 index 0000000000..edb26b6703 --- /dev/null +++ b/tests/MC/ARM/mve-shifts.s.yaml @@ -0,0 +1,218 @@ +test_cases: + - + input: + bytes: [ 0xa8, 0xee, 0xce, 0x0f, 0xa8, 0xee, 0x4c, 0x0f, 0xa8, 0xee, 0x48, 0x1f, 0x41, 0xfe, 0x00, 0x0f, 0xa8, 0xee, 0x48, 0x1f, 0xa8, 0xfe, 0x40, 0x0f, 0xa8, 0xfe, 0x44, 0x1f, 0xb0, 0xfe, 0x40, 0x2f, 0xb0, 0xfe, 0x44, 0x1f, 0x31, 0xee, 0x05, 0x0e, 0x31, 0xee, 0x0b, 0x3e, 0xaf, 0xee, 0x40, 0x0f, 0x31, 0xfe, 0x03, 0x2e, 0x31, 0xfe, 0x01, 0x1e, 0xab, 0xfe, 0x40, 0x0f, 0x35, 0xfe, 0x0b, 0x0e, 0x35, 0xfe, 0x07, 0x1e, 0x35, 0xee, 0x01, 0x1e, 0xbe, 0xee, 0x40, 0x1f, 0xbb, 0xee, 0x40, 0x1f, 0xb4, 0xfe, 0x44, 0x0f, 0x8f, 0xfe, 0xc7, 0x0f, 0x8b, 0xfe, 0xc5, 0x1f, 0x98, 0xfe, 0xc9, 0x0f, 0x99, 0xfe, 0xc5, 0x1f, 0x8f, 0xee, 0xc5, 0x2f, 0x8f, 0xee, 0xc3, 0x1f, 0x94, 0xee, 0xc1, 0x0f, 0x9c, 0xee, 0xc5, 0x1f, 0x88, 0xfe, 0xc4, 0x0f, 0x8a, 0xfe, 0xc0, 0x1f, 0x98, 0xfe, 0xc2, 0x1f, 0x93, 0xfe, 0xce, 0x0f, 0x8b, 0xee, 0xce, 0x0f, 0x89, 0xee, 0xc2, 0x1f, 0x9c, 0xee, 0xcc, 0x0f, 0x96, 0xee, 0xc4, 0x1f, 0x88, 0xee, 0x4f, 0x0f, 0x8c, 0xfe, 0x47, 0x3f, 0x99, 0xfe, 0x43, 0x0f, 0x95, 0xee, 0x43, 0x1f, 0x8b, 0xee, 0x4c, 0x0f, 0x8c, 0xee, 0x42, 0x1f, 0x89, 0xfe, 0x46, 0x0f, 0x88, 0xfe, 0x44, 0x1f, 0x9d, 0xee, 0x48, 0x3f, 0x92, 0xfe, 0x44, 0x0f, 0x0c, 0xef, 0x4c, 0xc4, 0x14, 0xef, 0x48, 0x04, 0x2a, 0xef, 0x42, 0x24, 0x04, 0xff, 0x4e, 0x24, 0x10, 0xff, 0x48, 0x04, 0x28, 0xff, 0x44, 0x44, 0x0c, 0xef, 0x52, 0x04, 0x1e, 0xef, 0x56, 0x84, 0x2a, 0xef, 0x5a, 0x04, 0x0c, 0xff, 0x50, 0x04, 0x18, 0xff, 0x5a, 0x04, 0x28, 0xff, 0x50, 0x24, 0x02, 0xef, 0x5c, 0x25, 0x1c, 0xef, 0x58, 0x45, 0x2a, 0xef, 0x50, 0x05, 0x02, 0xff, 0x54, 0x05, 0x10, 0xff, 0x5c, 0x25, 0x20, 0xff, 0x50, 0x05, 0x08, 0xef, 0x4c, 0x05, 0x1e, 0xef, 0x48, 0x25, 0x28, 0xef, 0x48, 0x25, 0x0a, 0xff, 0x46, 0x05, 0x1a, 0xff, 0x4c, 0xa5, 0x26, 0xff, 0x4e, 0x25, 0x8d, 0xff, 0x54, 0x04, 0x9b, 0xff, 0x54, 0x04, 0xb1, 0xff, 0x52, 0x04, 0x8b, 0xff, 0x56, 0x05, 0x9c, 0xff, 0x52, 0x05, 0xa8, 0xff, 0x52, 0x05, 0x8e, 0xef, 0x58, 0x07, 0x8e, 0xff, 0x5c, 0x07, 0x95, 0xef, 0x54, 0x27, 0x93, 0xff, 0x5a, 0x07, 0xbd, 0xef, 0x56, 0x27, 0xb3, 0xff, 0x54, 0x07, 0x88, 0xff, 0x52, 0x06, 0x9c, 0xff, 0x52, 0x46, 0xba, 0xff, 0x58, 0x06, 0x89, 0xef, 0x56, 0x22, 0x8e, 0xff, 0x56, 0x22, 0x96, 0xef, 0x52, 0x02, 0x94, 0xff, 0x5a, 0x02, 0xa9, 0xef, 0x5a, 0x02, 0xa2, 0xff, 0x52, 0x02, 0x8c, 0xef, 0x5e, 0x00, 0x8b, 0xff, 0x54, 0x00, 0x90, 0xef, 0x56, 0x00, 0x98, 0xff, 0x5c, 0xe0, 0xa8, 0xef, 0x5c, 0x00, 0xa2, 0xff, 0x5a, 0x40, 0x8e, 0xef, 0x5c, 0x05, 0x9c, 0xef, 0x50, 0x25, 0xba, 0xef, 0x54, 0x45, 0xa9, 0xee, 0x42, 0x1f, 0x71, 0xfe, 0x4d, 0x8f, 0xb4, 0xee, 0x42, 0x1f, 0xb8, 0xfe, 0x42, 0x0f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vshlc q0, lr, #8" + - + asm_text: "vmovlb.s8 q0, q6" + - + asm_text: "vmovlt.s8 q0, q4" + - + asm_text: "vpt.i8 eq, q0, q0" + - + asm_text: "vmovltt.s8 q0, q4" + - + asm_text: "vmovlb.u8 q0, q0" + - + asm_text: "vmovlt.u8 q0, q2" + - + asm_text: "vmovlb.u16 q1, q0" + - + asm_text: "vmovlt.u16 q0, q2" + - + asm_text: "vshllb.s8 q0, q2, #8" + - + asm_text: "vshllt.s8 q1, q5, #8" + - + asm_text: "vshllb.s8 q0, q0, #7" + - + asm_text: "vshllb.u8 q1, q1, #8" + - + asm_text: "vshllt.u8 q0, q0, #8" + - + asm_text: "vshllb.u8 q0, q0, #3" + - + asm_text: "vshllb.u16 q0, q5, #0x10" + - + asm_text: "vshllt.u16 q0, q3, #0x10" + - + asm_text: "vshllt.s16 q0, q0, #0x10" + - + asm_text: "vshllt.s16 q0, q0, #0xe" + - + asm_text: "vshllt.s16 q0, q0, #0xb" + - + asm_text: "vshllb.u16 q0, q2, #4" + - + asm_text: "vrshrnb.i16 q0, q3, #1" + - + asm_text: "vrshrnt.i16 q0, q2, #5" + - + asm_text: "vrshrnb.i32 q0, q4, #8" + - + asm_text: "vrshrnt.i32 q0, q2, #7" + - + asm_text: "vshrnb.i16 q1, q2, #1" + - + asm_text: "vshrnt.i16 q0, q1, #1" + - + asm_text: "vshrnb.i32 q0, q0, #0xc" + - + asm_text: "vshrnt.i32 q0, q2, #4" + - + asm_text: "vqrshrunb.s16 q0, q2, #8" + - + asm_text: "vqrshrunt.s16 q0, q0, #6" + - + asm_text: "vqrshrunt.s32 q0, q1, #8" + - + asm_text: "vqrshrunb.s32 q0, q7, #0xd" + - + asm_text: "vqshrunb.s16 q0, q7, #5" + - + asm_text: "vqshrunt.s16 q0, q1, #7" + - + asm_text: "vqshrunb.s32 q0, q6, #4" + - + asm_text: "vqshrunt.s32 q0, q2, #0xa" + - + asm_text: "vqrshrnb.s16 q0, q7, #8" + - + asm_text: "vqrshrnt.u16 q1, q3, #4" + - + asm_text: "vqrshrnb.u32 q0, q1, #7" + - + asm_text: "vqrshrnt.s32 q0, q1, #0xb" + - + asm_text: "vqshrnb.s16 q0, q6, #5" + - + asm_text: "vqshrnt.s16 q0, q1, #4" + - + asm_text: "vqshrnb.u16 q0, q3, #7" + - + asm_text: "vqshrnt.u16 q0, q2, #8" + - + asm_text: "vqshrnt.s32 q1, q4, #3" + - + asm_text: "vqshrnb.u32 q0, q2, #0xe" + - + asm_text: "vshl.s8 q6, q6, q6" + - + asm_text: "vshl.s16 q0, q4, q2" + - + asm_text: "vshl.s32 q1, q1, q5" + - + asm_text: "vshl.u8 q1, q7, q2" + - + asm_text: "vshl.u16 q0, q4, q0" + - + asm_text: "vshl.u32 q2, q2, q4" + - + asm_text: "vqshl.s8 q0, q1, q6" + - + asm_text: "vqshl.s16 q4, q3, q7" + - + asm_text: "vqshl.s32 q0, q5, q5" + - + asm_text: "vqshl.u8 q0, q0, q6" + - + asm_text: "vqshl.u16 q0, q5, q4" + - + asm_text: "vqshl.u32 q1, q0, q4" + - + asm_text: "vqrshl.s8 q1, q6, q1" + - + asm_text: "vqrshl.s16 q2, q4, q6" + - + asm_text: "vqrshl.s32 q0, q0, q5" + - + asm_text: "vqrshl.u8 q0, q2, q1" + - + asm_text: "vqrshl.u16 q1, q6, q0" + - + asm_text: "vqrshl.u32 q0, q0, q0" + - + asm_text: "vrshl.s8 q0, q6, q4" + - + asm_text: "vrshl.s16 q1, q4, q7" + - + asm_text: "vrshl.s32 q1, q4, q4" + - + asm_text: "vrshl.u8 q0, q3, q5" + - + asm_text: "vrshl.u16 q5, q6, q5" + - + asm_text: "vrshl.u32 q1, q7, q3" + - + asm_text: "vsri.8 q0, q2, #3" + - + asm_text: "vsri.16 q0, q2, #5" + - + asm_text: "vsri.32 q0, q1, #0xf" + - + asm_text: "vsli.8 q0, q3, #3" + - + asm_text: "vsli.16 q0, q1, #0xc" + - + asm_text: "vsli.32 q0, q1, #8" + - + asm_text: "vqshl.s8 q0, q4, #6" + - + asm_text: "vqshl.u8 q0, q6, #6" + - + asm_text: "vqshl.s16 q1, q2, #5" + - + asm_text: "vqshl.u16 q0, q5, #3" + - + asm_text: "vqshl.s32 q1, q3, #0x1d" + - + asm_text: "vqshl.u32 q0, q2, #0x13" + - + asm_text: "vqshlu.s8 q0, q1, #0" + - + asm_text: "vqshlu.s16 q2, q1, #0xc" + - + asm_text: "vqshlu.s32 q0, q4, #0x1a" + - + asm_text: "vrshr.s8 q1, q3, #7" + - + asm_text: "vrshr.u8 q1, q3, #2" + - + asm_text: "vrshr.s16 q0, q1, #0xa" + - + asm_text: "vrshr.u16 q0, q5, #0xc" + - + asm_text: "vrshr.s32 q0, q5, #0x17" + - + asm_text: "vrshr.u32 q0, q1, #0x1e" + - + asm_text: "vshr.s8 q0, q7, #4" + - + asm_text: "vshr.u8 q0, q2, #5" + - + asm_text: "vshr.s16 q0, q3, #0x10" + - + asm_text: "vshr.u16 q7, q6, #8" + - + asm_text: "vshr.s32 q0, q6, #0x18" + - + asm_text: "vshr.u32 q2, q5, #0x1e" + - + asm_text: "vshl.i8 q0, q6, #6" + - + asm_text: "vshl.i16 q1, q0, #0xc" + - + asm_text: "vshl.i32 q2, q2, #0x1a" + - + asm_text: "vshllt.s8 q0, q1, #1" + - + asm_text: "vpste" + - + asm_text: "vshlltt.s16 q0, q1, #4" + - + asm_text: "vshllbe.u16 q0, q1, #8" diff --git a/tests/MC/ARM/mve-vcmp.s.yaml b/tests/MC/ARM/mve-vcmp.s.yaml new file mode 100644 index 0000000000..5b3fdd8ebd --- /dev/null +++ b/tests/MC/ARM/mve-vcmp.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x31, 0xfe, 0x08, 0x0f, 0x35, 0xfe, 0x8e, 0x0f, 0x31, 0xfe, 0x00, 0x1f, 0x31, 0xfe, 0x82, 0x1f, 0x33, 0xfe, 0x09, 0x1f, 0x35, 0xfe, 0x8d, 0x1f, 0x35, 0xee, 0x0a, 0x0f, 0x37, 0xee, 0x88, 0x0f, 0x31, 0xee, 0x0e, 0x1f, 0x3b, 0xee, 0x84, 0x1f, 0x35, 0xee, 0x0f, 0x1f, 0x35, 0xee, 0x89, 0x1f, 0x09, 0xfe, 0x0c, 0x0f, 0x05, 0xfe, 0x84, 0x0f, 0x09, 0xfe, 0x0c, 0x0f, 0x05, 0xfe, 0x84, 0x0f, 0x09, 0xfe, 0x0c, 0x0f, 0x05, 0xfe, 0x84, 0x0f, 0x01, 0xfe, 0x00, 0x1f, 0x05, 0xfe, 0x8e, 0x1f, 0x09, 0xfe, 0x07, 0x1f, 0x0f, 0xfe, 0x87, 0x1f, 0x03, 0xfe, 0x89, 0x0f, 0x03, 0xfe, 0x09, 0x0f, 0x19, 0xfe, 0x0e, 0x0f, 0x15, 0xfe, 0x82, 0x0f, 0x13, 0xfe, 0x0e, 0x1f, 0x11, 0xfe, 0x82, 0x1f, 0x13, 0xfe, 0x0f, 0x1f, 0x15, 0xfe, 0x83, 0x1f, 0x13, 0xfe, 0x89, 0x0f, 0x13, 0xfe, 0x09, 0x0f, 0x25, 0xfe, 0x0e, 0x0f, 0x25, 0xfe, 0x88, 0x0f, 0x2b, 0xfe, 0x0a, 0x1f, 0x25, 0xfe, 0x84, 0x1f, 0x21, 0xfe, 0x03, 0x1f, 0x2b, 0xfe, 0x89, 0x1f, 0x23, 0xfe, 0x89, 0x0f, 0x23, 0xfe, 0x09, 0x0f, 0x39, 0xfe, 0x6f, 0x1f, 0x39, 0xfe, 0x4c, 0x0f, 0x37, 0xee, 0xc0, 0x0f, 0x03, 0xfe, 0x40, 0x0f, 0x03, 0xfe, 0xe0, 0x1f, 0x03, 0xfe, 0x60, 0x0f, 0x1b, 0xfe, 0x4a, 0x0f, 0x23, 0xfe, 0x44, 0x0f, 0x71, 0xfe, 0x4d, 0x8f, 0x01, 0xfe, 0x40, 0x0f, 0x11, 0xfe, 0xc0, 0x0f, 0xb4, 0xee, 0x60, 0x09, 0xb4, 0xee, 0xe0, 0x09, 0x04, 0xbf, 0xb4, 0xee, 0x60, 0x0a, 0xb4, 0xee, 0xe0, 0x0a ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vcmp.f16 eq, q0, q4" + - + asm_text: "vcmp.f16 ne, q2, q7" + - + asm_text: "vcmp.f16 ge, q0, q0" + - + asm_text: "vcmp.f16 lt, q0, q1" + - + asm_text: "vcmp.f16 gt, q1, q4" + - + asm_text: "vcmp.f16 le, q2, q6" + - + asm_text: "vcmp.f32 eq, q2, q5" + - + asm_text: "vcmp.f32 ne, q3, q4" + - + asm_text: "vcmp.f32 ge, q0, q7" + - + asm_text: "vcmp.f32 lt, q5, q2" + - + asm_text: "vcmp.f32 gt, q2, q7" + - + asm_text: "vcmp.f32 le, q2, q4" + - + asm_text: "vcmp.i8 eq, q4, q6" + - + asm_text: "vcmp.i8 ne, q2, q2" + - + asm_text: "vcmp.i8 eq, q4, q6" + - + asm_text: "vcmp.i8 ne, q2, q2" + - + asm_text: "vcmp.i8 eq, q4, q6" + - + asm_text: "vcmp.i8 ne, q2, q2" + - + asm_text: "vcmp.s8 ge, q0, q0" + - + asm_text: "vcmp.s8 lt, q2, q7" + - + asm_text: "vcmp.s8 gt, q4, q3" + - + asm_text: "vcmp.s8 le, q7, q3" + - + asm_text: "vcmp.u8 hi, q1, q4" + - + asm_text: "vcmp.u8 cs, q1, q4" + - + asm_text: "vcmp.i16 eq, q4, q7" + - + asm_text: "vcmp.i16 ne, q2, q1" + - + asm_text: "vcmp.s16 ge, q1, q7" + - + asm_text: "vcmp.s16 lt, q0, q1" + - + asm_text: "vcmp.s16 gt, q1, q7" + - + asm_text: "vcmp.s16 le, q2, q1" + - + asm_text: "vcmp.u16 hi, q1, q4" + - + asm_text: "vcmp.u16 cs, q1, q4" + - + asm_text: "vcmp.i32 eq, q2, q7" + - + asm_text: "vcmp.i32 ne, q2, q4" + - + asm_text: "vcmp.s32 ge, q5, q5" + - + asm_text: "vcmp.s32 lt, q2, q2" + - + asm_text: "vcmp.s32 gt, q0, q1" + - + asm_text: "vcmp.s32 le, q5, q4" + - + asm_text: "vcmp.u32 hi, q1, q4" + - + asm_text: "vcmp.u32 cs, q1, q4" + - + asm_text: "vcmp.f16 gt, q4, zr" + - + asm_text: "vcmp.f16 eq, q4, r12" + - + asm_text: "vcmp.f32 ne, q3, r0" + - + asm_text: "vcmp.i8 eq, q1, r0" + - + asm_text: "vcmp.s8 le, q1, r0" + - + asm_text: "vcmp.u8 cs, q1, r0" + - + asm_text: "vcmp.i16 eq, q5, r10" + - + asm_text: "vcmp.i32 eq, q1, r4" + - + asm_text: "vpste" + - + asm_text: "vcmpt.i8 eq, q0, r0" + - + asm_text: "vcmpe.i16 ne, q0, r0" + - + asm_text: "vcmp.f16 s0, s1" + - + asm_text: "vcmpe.f16 s0, s1" + - + asm_text: "itt eq" + - + asm_text: "vcmpeq.f32 s0, s1" + - + asm_text: "vcmpeeq.f32 s0, s1" diff --git a/tests/MC/ARM/mve-vmov-pair.s.yaml b/tests/MC/ARM/mve-vmov-pair.s.yaml new file mode 100644 index 0000000000..957e55d579 --- /dev/null +++ b/tests/MC/ARM/mve-vmov-pair.s.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0x07, 0xec, 0x0e, 0x8f, 0x11, 0xec, 0x14, 0x6f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmov lr, r7, q4[2], q4[0]" + - + asm_text: "vmov q3[3], q3[1], r4, r1" diff --git a/tests/MC/ARM/mve-vpt.s.yaml b/tests/MC/ARM/mve-vpt.s.yaml new file mode 100644 index 0000000000..c49bc1987b --- /dev/null +++ b/tests/MC/ARM/mve-vpt.s.yaml @@ -0,0 +1,16 @@ +test_cases: + - + input: + bytes: [ 0x41, 0xfe, 0x02, 0x2f, 0x21, 0xfe, 0x03, 0x3f, 0x71, 0xfe, 0x82, 0xef, 0x1c, 0xff, 0x54, 0x2f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vpteee.i8 eq, q0, q1" + - + asm_text: "vptttt.s32 gt, q0, q1" + - + asm_text: "vptete.f16 ne, q0, q1" + - + asm_text: "vmaxnmt.f16 q1, q6, q2" diff --git a/tests/MC/ARM/negative-immediates.s.yaml b/tests/MC/ARM/negative-immediates.s.yaml new file mode 100644 index 0000000000..c530b98cb3 --- /dev/null +++ b/tests/MC/ARM/negative-immediates.s.yaml @@ -0,0 +1,26 @@ +test_cases: + - + input: + bytes: [ 0x61, 0xf1, 0x01, 0x10, 0x61, 0xf1, 0x01, 0x20, 0xa0, 0xf1, 0xfe, 0x10, 0xa1, 0xf2, 0xff, 0x00, 0xa1, 0xf1, 0xff, 0x00, 0x21, 0xf0, 0x01, 0x20, 0x01, 0xf0, 0x01, 0x20, 0x61, 0xf0, 0x01, 0x20, 0x41, 0xf0, 0x01, 0x20 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "sbc r0, r1, #0x10001" + - + asm_text: "sbc r0, r1, #0x1000100" + - + asm_text: "sub.w r0, r0, #0xfe00fe" + - + asm_text: "subw r0, r1, #0xff" + - + asm_text: "sub.w r0, r1, #0xff" + - + asm_text: "bic r0, r1, #0x1000100" + - + asm_text: "and r0, r1, #0x1000100" + - + asm_text: "orn r0, r1, #0x1000100" + - + asm_text: "orr r0, r1, #0x1000100" diff --git a/tests/MC/ARM/neon-abs-encoding.s.yaml b/tests/MC/ARM/neon-abs-encoding.s.yaml new file mode 100644 index 0000000000..0dabf261b6 --- /dev/null +++ b/tests/MC/ARM/neon-abs-encoding.s.yaml @@ -0,0 +1,36 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x03, 0xf1, 0xf3, 0x20, 0x03, 0xf5, 0xf3, 0x20, 0x03, 0xf9, 0xf3, 0x20, 0x07, 0xf9, 0xf3, 0x60, 0x03, 0xf1, 0xf3, 0x60, 0x03, 0xf5, 0xf3, 0x60, 0x03, 0xf9, 0xf3, 0x60, 0x07, 0xf9, 0xf3, 0x20, 0x07, 0xf0, 0xf3, 0x20, 0x07, 0xf4, 0xf3, 0x20, 0x07, 0xf8, 0xf3, 0x60, 0x07, 0xf0, 0xf3, 0x60, 0x07, 0xf4, 0xf3, 0x60, 0x07, 0xf8, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vabs.s8 d16, d16" + - + asm_text: "vabs.s16 d16, d16" + - + asm_text: "vabs.s32 d16, d16" + - + asm_text: "vabs.f32 d16, d16" + - + asm_text: "vabs.s8 q8, q8" + - + asm_text: "vabs.s16 q8, q8" + - + asm_text: "vabs.s32 q8, q8" + - + asm_text: "vabs.f32 q8, q8" + - + asm_text: "vqabs.s8 d16, d16" + - + asm_text: "vqabs.s16 d16, d16" + - + asm_text: "vqabs.s32 d16, d16" + - + asm_text: "vqabs.s8 q8, q8" + - + asm_text: "vqabs.s16 q8, q8" + - + asm_text: "vqabs.s32 q8, q8" diff --git a/tests/MC/ARM/neon-absdiff-encoding.s.yaml b/tests/MC/ARM/neon-absdiff-encoding.s.yaml new file mode 100644 index 0000000000..11b03d4194 --- /dev/null +++ b/tests/MC/ARM/neon-absdiff-encoding.s.yaml @@ -0,0 +1,84 @@ +test_cases: + - + input: + bytes: [ 0xa1, 0x07, 0x40, 0xf2, 0xa1, 0x07, 0x50, 0xf2, 0xa1, 0x07, 0x60, 0xf2, 0xa1, 0x07, 0x40, 0xf3, 0xa1, 0x07, 0x50, 0xf3, 0xa1, 0x07, 0x60, 0xf3, 0xa1, 0x0d, 0x60, 0xf3, 0xe2, 0x07, 0x40, 0xf2, 0xe2, 0x07, 0x50, 0xf2, 0xe2, 0x07, 0x60, 0xf2, 0xe2, 0x07, 0x40, 0xf3, 0xe2, 0x07, 0x50, 0xf3, 0xe2, 0x07, 0x60, 0xf3, 0xe2, 0x0d, 0x60, 0xf3, 0xa1, 0x07, 0xc0, 0xf2, 0xa1, 0x07, 0xd0, 0xf2, 0xa1, 0x07, 0xe0, 0xf2, 0xa1, 0x07, 0xc0, 0xf3, 0xa1, 0x07, 0xd0, 0xf3, 0xa1, 0x07, 0xe0, 0xf3, 0xb1, 0x07, 0x42, 0xf2, 0xb1, 0x07, 0x52, 0xf2, 0xb1, 0x07, 0x62, 0xf2, 0xb1, 0x07, 0x42, 0xf3, 0xb1, 0x07, 0x52, 0xf3, 0xb1, 0x07, 0x62, 0xf3, 0xf4, 0x27, 0x40, 0xf2, 0xf4, 0x27, 0x50, 0xf2, 0xf4, 0x27, 0x60, 0xf2, 0xf4, 0x27, 0x40, 0xf3, 0xf4, 0x27, 0x50, 0xf3, 0xf4, 0x27, 0x60, 0xf3, 0xa2, 0x05, 0xc3, 0xf2, 0xa2, 0x05, 0xd3, 0xf2, 0xa2, 0x05, 0xe3, 0xf2, 0xa2, 0x05, 0xc3, 0xf3, 0xa2, 0x05, 0xd3, 0xf3, 0xa2, 0x05, 0xe3, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vabd.s8 d16, d16, d17" + - + asm_text: "vabd.s16 d16, d16, d17" + - + asm_text: "vabd.s32 d16, d16, d17" + - + asm_text: "vabd.u8 d16, d16, d17" + - + asm_text: "vabd.u16 d16, d16, d17" + - + asm_text: "vabd.u32 d16, d16, d17" + - + asm_text: "vabd.f32 d16, d16, d17" + - + asm_text: "vabd.s8 q8, q8, q9" + - + asm_text: "vabd.s16 q8, q8, q9" + - + asm_text: "vabd.s32 q8, q8, q9" + - + asm_text: "vabd.u8 q8, q8, q9" + - + asm_text: "vabd.u16 q8, q8, q9" + - + asm_text: "vabd.u32 q8, q8, q9" + - + asm_text: "vabd.f32 q8, q8, q9" + - + asm_text: "vabdl.s8 q8, d16, d17" + - + asm_text: "vabdl.s16 q8, d16, d17" + - + asm_text: "vabdl.s32 q8, d16, d17" + - + asm_text: "vabdl.u8 q8, d16, d17" + - + asm_text: "vabdl.u16 q8, d16, d17" + - + asm_text: "vabdl.u32 q8, d16, d17" + - + asm_text: "vaba.s8 d16, d18, d17" + - + asm_text: "vaba.s16 d16, d18, d17" + - + asm_text: "vaba.s32 d16, d18, d17" + - + asm_text: "vaba.u8 d16, d18, d17" + - + asm_text: "vaba.u16 d16, d18, d17" + - + asm_text: "vaba.u32 d16, d18, d17" + - + asm_text: "vaba.s8 q9, q8, q10" + - + asm_text: "vaba.s16 q9, q8, q10" + - + asm_text: "vaba.s32 q9, q8, q10" + - + asm_text: "vaba.u8 q9, q8, q10" + - + asm_text: "vaba.u16 q9, q8, q10" + - + asm_text: "vaba.u32 q9, q8, q10" + - + asm_text: "vabal.s8 q8, d19, d18" + - + asm_text: "vabal.s16 q8, d19, d18" + - + asm_text: "vabal.s32 q8, d19, d18" + - + asm_text: "vabal.u8 q8, d19, d18" + - + asm_text: "vabal.u16 q8, d19, d18" + - + asm_text: "vabal.u32 q8, d19, d18" diff --git a/tests/MC/ARM/neon-add-encoding.s.yaml b/tests/MC/ARM/neon-add-encoding.s.yaml new file mode 100644 index 0000000000..682dd4792e --- /dev/null +++ b/tests/MC/ARM/neon-add-encoding.s.yaml @@ -0,0 +1,244 @@ +test_cases: + - + input: + bytes: [ 0xa0, 0x08, 0x41, 0xf2, 0xa0, 0x08, 0x51, 0xf2, 0xa0, 0x08, 0x71, 0xf2, 0xa0, 0x08, 0x61, 0xf2, 0xa1, 0x0d, 0x40, 0xf2, 0xe2, 0x0d, 0x40, 0xf2, 0xa0, 0x00, 0xc1, 0xf2, 0xa0, 0x00, 0xd1, 0xf2, 0xa0, 0x00, 0xe1, 0xf2, 0xa0, 0x00, 0xc1, 0xf3, 0xa0, 0x00, 0xd1, 0xf3, 0xa0, 0x00, 0xe1, 0xf3, 0xa2, 0x01, 0xc0, 0xf2, 0xa2, 0x01, 0xd0, 0xf2, 0xa2, 0x01, 0xe0, 0xf2, 0xa2, 0x01, 0xc0, 0xf3, 0xa2, 0x01, 0xd0, 0xf3, 0xa2, 0x01, 0xe0, 0xf3, 0xa1, 0x00, 0x40, 0xf2, 0xa1, 0x00, 0x50, 0xf2, 0xa1, 0x00, 0x60, 0xf2, 0xa1, 0x00, 0x40, 0xf3, 0xa1, 0x00, 0x50, 0xf3, 0xa1, 0x00, 0x60, 0xf3, 0xe2, 0x00, 0x40, 0xf2, 0xe2, 0x00, 0x50, 0xf2, 0xe2, 0x00, 0x60, 0xf2, 0xe2, 0x00, 0x40, 0xf3, 0xe2, 0x00, 0x50, 0xf3, 0xe2, 0x00, 0x60, 0xf3, 0x28, 0xb0, 0x0b, 0xf2, 0x27, 0xc0, 0x1c, 0xf2, 0x26, 0xd0, 0x2d, 0xf2, 0x25, 0xe0, 0x0e, 0xf3, 0x24, 0xf0, 0x1f, 0xf3, 0xa3, 0x00, 0x60, 0xf3, 0x68, 0x20, 0x02, 0xf2, 0x66, 0x40, 0x14, 0xf2, 0x64, 0x60, 0x26, 0xf2, 0x62, 0x80, 0x08, 0xf3, 0x60, 0xa0, 0x1a, 0xf3, 0x4e, 0xc0, 0x2c, 0xf3, 0xa1, 0x01, 0x40, 0xf2, 0xa1, 0x01, 0x50, 0xf2, 0xa1, 0x01, 0x60, 0xf2, 0xa1, 0x01, 0x40, 0xf3, 0xa1, 0x01, 0x50, 0xf3, 0xa1, 0x01, 0x60, 0xf3, 0xe2, 0x01, 0x40, 0xf2, 0xe2, 0x01, 0x50, 0xf2, 0xe2, 0x01, 0x60, 0xf2, 0xe2, 0x01, 0x40, 0xf3, 0xe2, 0x01, 0x50, 0xf3, 0xe2, 0x01, 0x60, 0xf3, 0xa1, 0x01, 0x40, 0xf2, 0xa1, 0x01, 0x50, 0xf2, 0xa1, 0x01, 0x60, 0xf2, 0xa1, 0x01, 0x40, 0xf3, 0xa1, 0x01, 0x50, 0xf3, 0xa1, 0x01, 0x60, 0xf3, 0xe2, 0x01, 0x40, 0xf2, 0xe2, 0x01, 0x50, 0xf2, 0xe2, 0x01, 0x60, 0xf2, 0xe2, 0x01, 0x40, 0xf3, 0xe2, 0x01, 0x50, 0xf3, 0xe2, 0x01, 0x60, 0xf3, 0xb1, 0x00, 0x40, 0xf2, 0xb1, 0x00, 0x50, 0xf2, 0xb1, 0x00, 0x60, 0xf2, 0xb1, 0x00, 0x70, 0xf2, 0xb1, 0x00, 0x40, 0xf3, 0xb1, 0x00, 0x50, 0xf3, 0xb1, 0x00, 0x60, 0xf3, 0xb1, 0x00, 0x70, 0xf3, 0xf2, 0x00, 0x40, 0xf2, 0xf2, 0x00, 0x50, 0xf2, 0xf2, 0x00, 0x60, 0xf2, 0xf2, 0x00, 0x70, 0xf2, 0xf2, 0x00, 0x40, 0xf3, 0xf2, 0x00, 0x50, 0xf3, 0xf2, 0x00, 0x60, 0xf3, 0xf2, 0x00, 0x70, 0xf3, 0xb1, 0x00, 0x40, 0xf2, 0xb1, 0x00, 0x50, 0xf2, 0xb1, 0x00, 0x60, 0xf2, 0xb1, 0x00, 0x70, 0xf2, 0xb1, 0x00, 0x40, 0xf3, 0xb1, 0x00, 0x50, 0xf3, 0xb1, 0x00, 0x60, 0xf3, 0xb1, 0x00, 0x70, 0xf3, 0xf2, 0x00, 0x40, 0xf2, 0xf2, 0x00, 0x50, 0xf2, 0xf2, 0x00, 0x60, 0xf2, 0xf2, 0x00, 0x70, 0xf2, 0xf2, 0x00, 0x40, 0xf3, 0xf2, 0x00, 0x50, 0xf3, 0xf2, 0x00, 0x60, 0xf3, 0xf2, 0x00, 0x70, 0xf3, 0xa2, 0x04, 0xc0, 0xf2, 0xa2, 0x04, 0xd0, 0xf2, 0xa2, 0x04, 0xe0, 0xf2, 0xa2, 0x04, 0xc0, 0xf3, 0xa2, 0x04, 0xd0, 0xf3, 0xa2, 0x04, 0xe0, 0xf3, 0x05, 0x68, 0x06, 0xf2, 0x01, 0x78, 0x17, 0xf2, 0x02, 0x88, 0x28, 0xf2, 0x03, 0x98, 0x39, 0xf2, 0x4a, 0xc8, 0x0c, 0xf2, 0x42, 0xe8, 0x1e, 0xf2, 0xc4, 0x08, 0x60, 0xf2, 0xc6, 0x28, 0x72, 0xf2, 0x05, 0xc1, 0x8c, 0xf2, 0x01, 0xe1, 0x9e, 0xf2, 0x82, 0x01, 0xe0, 0xf2, 0x05, 0xc1, 0x8c, 0xf3, 0x01, 0xe1, 0x9e, 0xf3, 0x82, 0x01, 0xe0, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vadd.i8 d16, d17, d16" + - + asm_text: "vadd.i16 d16, d17, d16" + - + asm_text: "vadd.i64 d16, d17, d16" + - + asm_text: "vadd.i32 d16, d17, d16" + - + asm_text: "vadd.f32 d16, d16, d17" + - + asm_text: "vadd.f32 q8, q8, q9" + - + asm_text: "vaddl.s8 q8, d17, d16" + - + asm_text: "vaddl.s16 q8, d17, d16" + - + asm_text: "vaddl.s32 q8, d17, d16" + - + asm_text: "vaddl.u8 q8, d17, d16" + - + asm_text: "vaddl.u16 q8, d17, d16" + - + asm_text: "vaddl.u32 q8, d17, d16" + - + asm_text: "vaddw.s8 q8, q8, d18" + - + asm_text: "vaddw.s16 q8, q8, d18" + - + asm_text: "vaddw.s32 q8, q8, d18" + - + asm_text: "vaddw.u8 q8, q8, d18" + - + asm_text: "vaddw.u16 q8, q8, d18" + - + asm_text: "vaddw.u32 q8, q8, d18" + - + asm_text: "vhadd.s8 d16, d16, d17" + - + asm_text: "vhadd.s16 d16, d16, d17" + - + asm_text: "vhadd.s32 d16, d16, d17" + - + asm_text: "vhadd.u8 d16, d16, d17" + - + asm_text: "vhadd.u16 d16, d16, d17" + - + asm_text: "vhadd.u32 d16, d16, d17" + - + asm_text: "vhadd.s8 q8, q8, q9" + - + asm_text: "vhadd.s16 q8, q8, q9" + - + asm_text: "vhadd.s32 q8, q8, q9" + - + asm_text: "vhadd.u8 q8, q8, q9" + - + asm_text: "vhadd.u16 q8, q8, q9" + - + asm_text: "vhadd.u32 q8, q8, q9" + - + asm_text: "vhadd.s8 d11, d11, d24" + - + asm_text: "vhadd.s16 d12, d12, d23" + - + asm_text: "vhadd.s32 d13, d13, d22" + - + asm_text: "vhadd.u8 d14, d14, d21" + - + asm_text: "vhadd.u16 d15, d15, d20" + - + asm_text: "vhadd.u32 d16, d16, d19" + - + asm_text: "vhadd.s8 q1, q1, q12" + - + asm_text: "vhadd.s16 q2, q2, q11" + - + asm_text: "vhadd.s32 q3, q3, q10" + - + asm_text: "vhadd.u8 q4, q4, q9" + - + asm_text: "vhadd.u16 q5, q5, q8" + - + asm_text: "vhadd.u32 q6, q6, q7" + - + asm_text: "vrhadd.s8 d16, d16, d17" + - + asm_text: "vrhadd.s16 d16, d16, d17" + - + asm_text: "vrhadd.s32 d16, d16, d17" + - + asm_text: "vrhadd.u8 d16, d16, d17" + - + asm_text: "vrhadd.u16 d16, d16, d17" + - + asm_text: "vrhadd.u32 d16, d16, d17" + - + asm_text: "vrhadd.s8 q8, q8, q9" + - + asm_text: "vrhadd.s16 q8, q8, q9" + - + asm_text: "vrhadd.s32 q8, q8, q9" + - + asm_text: "vrhadd.u8 q8, q8, q9" + - + asm_text: "vrhadd.u16 q8, q8, q9" + - + asm_text: "vrhadd.u32 q8, q8, q9" + - + asm_text: "vrhadd.s8 d16, d16, d17" + - + asm_text: "vrhadd.s16 d16, d16, d17" + - + asm_text: "vrhadd.s32 d16, d16, d17" + - + asm_text: "vrhadd.u8 d16, d16, d17" + - + asm_text: "vrhadd.u16 d16, d16, d17" + - + asm_text: "vrhadd.u32 d16, d16, d17" + - + asm_text: "vrhadd.s8 q8, q8, q9" + - + asm_text: "vrhadd.s16 q8, q8, q9" + - + asm_text: "vrhadd.s32 q8, q8, q9" + - + asm_text: "vrhadd.u8 q8, q8, q9" + - + asm_text: "vrhadd.u16 q8, q8, q9" + - + asm_text: "vrhadd.u32 q8, q8, q9" + - + asm_text: "vqadd.s8 d16, d16, d17" + - + asm_text: "vqadd.s16 d16, d16, d17" + - + asm_text: "vqadd.s32 d16, d16, d17" + - + asm_text: "vqadd.s64 d16, d16, d17" + - + asm_text: "vqadd.u8 d16, d16, d17" + - + asm_text: "vqadd.u16 d16, d16, d17" + - + asm_text: "vqadd.u32 d16, d16, d17" + - + asm_text: "vqadd.u64 d16, d16, d17" + - + asm_text: "vqadd.s8 q8, q8, q9" + - + asm_text: "vqadd.s16 q8, q8, q9" + - + asm_text: "vqadd.s32 q8, q8, q9" + - + asm_text: "vqadd.s64 q8, q8, q9" + - + asm_text: "vqadd.u8 q8, q8, q9" + - + asm_text: "vqadd.u16 q8, q8, q9" + - + asm_text: "vqadd.u32 q8, q8, q9" + - + asm_text: "vqadd.u64 q8, q8, q9" + - + asm_text: "vqadd.s8 d16, d16, d17" + - + asm_text: "vqadd.s16 d16, d16, d17" + - + asm_text: "vqadd.s32 d16, d16, d17" + - + asm_text: "vqadd.s64 d16, d16, d17" + - + asm_text: "vqadd.u8 d16, d16, d17" + - + asm_text: "vqadd.u16 d16, d16, d17" + - + asm_text: "vqadd.u32 d16, d16, d17" + - + asm_text: "vqadd.u64 d16, d16, d17" + - + asm_text: "vqadd.s8 q8, q8, q9" + - + asm_text: "vqadd.s16 q8, q8, q9" + - + asm_text: "vqadd.s32 q8, q8, q9" + - + asm_text: "vqadd.s64 q8, q8, q9" + - + asm_text: "vqadd.u8 q8, q8, q9" + - + asm_text: "vqadd.u16 q8, q8, q9" + - + asm_text: "vqadd.u32 q8, q8, q9" + - + asm_text: "vqadd.u64 q8, q8, q9" + - + asm_text: "vaddhn.i16 d16, q8, q9" + - + asm_text: "vaddhn.i32 d16, q8, q9" + - + asm_text: "vaddhn.i64 d16, q8, q9" + - + asm_text: "vraddhn.i16 d16, q8, q9" + - + asm_text: "vraddhn.i32 d16, q8, q9" + - + asm_text: "vraddhn.i64 d16, q8, q9" + - + asm_text: "vadd.i8 d6, d6, d5" + - + asm_text: "vadd.i16 d7, d7, d1" + - + asm_text: "vadd.i32 d8, d8, d2" + - + asm_text: "vadd.i64 d9, d9, d3" + - + asm_text: "vadd.i8 q6, q6, q5" + - + asm_text: "vadd.i16 q7, q7, q1" + - + asm_text: "vadd.i32 q8, q8, q2" + - + asm_text: "vadd.i64 q9, q9, q3" + - + asm_text: "vaddw.s8 q6, q6, d5" + - + asm_text: "vaddw.s16 q7, q7, d1" + - + asm_text: "vaddw.s32 q8, q8, d2" + - + asm_text: "vaddw.u8 q6, q6, d5" + - + asm_text: "vaddw.u16 q7, q7, d1" + - + asm_text: "vaddw.u32 q8, q8, d2" diff --git a/tests/MC/ARM/neon-bitcount-encoding.s.yaml b/tests/MC/ARM/neon-bitcount-encoding.s.yaml new file mode 100644 index 0000000000..44fcb1bcce --- /dev/null +++ b/tests/MC/ARM/neon-bitcount-encoding.s.yaml @@ -0,0 +1,36 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x05, 0xf0, 0xf3, 0x60, 0x05, 0xf0, 0xf3, 0xa0, 0x04, 0xf0, 0xf3, 0xa0, 0x04, 0xf4, 0xf3, 0xa0, 0x04, 0xf8, 0xf3, 0xe0, 0x04, 0xf0, 0xf3, 0xe0, 0x04, 0xf4, 0xf3, 0xe0, 0x04, 0xf8, 0xf3, 0x20, 0x04, 0xf0, 0xf3, 0x20, 0x04, 0xf4, 0xf3, 0x20, 0x04, 0xf8, 0xf3, 0x60, 0x04, 0xf0, 0xf3, 0x60, 0x04, 0xf4, 0xf3, 0x60, 0x04, 0xf8, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vcnt.8 d16, d16" + - + asm_text: "vcnt.8 q8, q8" + - + asm_text: "vclz.i8 d16, d16" + - + asm_text: "vclz.i16 d16, d16" + - + asm_text: "vclz.i32 d16, d16" + - + asm_text: "vclz.i8 q8, q8" + - + asm_text: "vclz.i16 q8, q8" + - + asm_text: "vclz.i32 q8, q8" + - + asm_text: "vcls.s8 d16, d16" + - + asm_text: "vcls.s16 d16, d16" + - + asm_text: "vcls.s32 d16, d16" + - + asm_text: "vcls.s8 q8, q8" + - + asm_text: "vcls.s16 q8, q8" + - + asm_text: "vcls.s32 q8, q8" diff --git a/tests/MC/ARM/neon-bitwise-encoding.s.yaml b/tests/MC/ARM/neon-bitwise-encoding.s.yaml new file mode 100644 index 0000000000..df1ee145f5 --- /dev/null +++ b/tests/MC/ARM/neon-bitwise-encoding.s.yaml @@ -0,0 +1,310 @@ +test_cases: + - + input: + bytes: [ 0xb0, 0x01, 0x41, 0xf2, 0xf2, 0x01, 0x40, 0xf2, 0xb0, 0x01, 0x41, 0xf3, 0xf2, 0x01, 0x40, 0xf3, 0xb0, 0x01, 0x61, 0xf2, 0xf2, 0x01, 0x60, 0xf2, 0x11, 0x07, 0xc0, 0xf2, 0x51, 0x07, 0xc0, 0xf2, 0x50, 0x01, 0xc0, 0xf2, 0xb0, 0x01, 0x51, 0xf2, 0xf2, 0x01, 0x50, 0xf2, 0xf6, 0x41, 0x54, 0xf2, 0x11, 0x91, 0x19, 0xf2, 0x3f, 0x0b, 0xc7, 0xf3, 0x7f, 0x0b, 0xc7, 0xf3, 0x3f, 0x09, 0xc7, 0xf3, 0x7f, 0x09, 0xc7, 0xf3, 0x3f, 0x07, 0xc7, 0xf3, 0x7f, 0x07, 0xc7, 0xf3, 0x3f, 0x05, 0xc7, 0xf3, 0x7f, 0x05, 0xc7, 0xf3, 0x3f, 0x03, 0xc7, 0xf3, 0x7f, 0x03, 0xc7, 0xf3, 0x3f, 0x01, 0xc7, 0xf3, 0x7f, 0x01, 0xc7, 0xf3, 0x3c, 0xa9, 0x87, 0xf3, 0x7c, 0x49, 0xc7, 0xf3, 0x3c, 0xab, 0x87, 0xf3, 0x7c, 0x4b, 0xc7, 0xf3, 0x3c, 0xa7, 0x87, 0xf3, 0x7c, 0x47, 0xc7, 0xf3, 0x3c, 0xa5, 0x87, 0xf3, 0x7c, 0x45, 0xc7, 0xf3, 0x3c, 0xa3, 0x87, 0xf3, 0x7c, 0x43, 0xc7, 0xf3, 0x3c, 0xa1, 0x87, 0xf3, 0x7c, 0x41, 0xc7, 0xf3, 0xb0, 0x01, 0x71, 0xf2, 0xf2, 0x01, 0x70, 0xf2, 0xa0, 0x05, 0xf0, 0xf3, 0xe0, 0x05, 0xf0, 0xf3, 0xb0, 0x21, 0x51, 0xf3, 0xf2, 0x01, 0x54, 0xf3, 0xb0, 0x21, 0x61, 0xf3, 0xf2, 0x01, 0x64, 0xf3, 0xb0, 0x21, 0x71, 0xf3, 0xf2, 0x01, 0x74, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x5a, 0xc1, 0x0c, 0xf2, 0x5a, 0xc1, 0x0c, 0xf2, 0x52, 0xe1, 0x0e, 0xf2, 0xd4, 0x01, 0x40, 0xf2, 0xd4, 0x01, 0x40, 0xf2, 0x5a, 0xc1, 0x0c, 0xf3, 0x5a, 0xc1, 0x0c, 0xf3, 0x52, 0xe1, 0x0e, 0xf3, 0xd4, 0x01, 0x40, 0xf3, 0xd4, 0x01, 0x40, 0xf3, 0x5a, 0xc1, 0x0c, 0xf3, 0x5a, 0xc1, 0x0c, 0xf3, 0x52, 0xe1, 0x0e, 0xf3, 0xd4, 0x01, 0x40, 0xf3, 0xd4, 0x01, 0x40, 0xf3, 0x4a, 0xa2, 0xb5, 0xf3, 0x05, 0x52, 0xb5, 0xf3, 0x56, 0xa8, 0x1a, 0xf3, 0x13, 0x58, 0x15, 0xf3, 0x46, 0xa3, 0x1a, 0xf2, 0x03, 0x53, 0x15, 0xf2, 0x56, 0xa3, 0x1a, 0xf2, 0x13, 0x53, 0x15, 0xf2, 0x4a, 0xa0, 0xb5, 0xf3, 0x05, 0x50, 0xb5, 0xf3, 0xca, 0xa0, 0xb5, 0xf3, 0x85, 0x50, 0xb5, 0xf3, 0x4a, 0xa1, 0xb5, 0xf3, 0x05, 0x51, 0xb5, 0xf3, 0xca, 0xa1, 0xb5, 0xf3, 0x85, 0x51, 0xb5, 0xf3, 0x3e, 0x5e, 0x05, 0xf3, 0x56, 0xae, 0x0a, 0xf3, 0x3e, 0x5e, 0x25, 0xf3, 0x56, 0xae, 0x2a, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vand d16, d17, d16" + - + asm_text: "vand q8, q8, q9" + - + asm_text: "veor d16, d17, d16" + - + asm_text: "veor q8, q8, q9" + - + asm_text: "vorr d16, d17, d16" + - + asm_text: "vorr q8, q8, q9" + - + asm_text: "vorr.i32 d16, #0x1000000" + - + asm_text: "vorr.i32 q8, #0x1000000" + - + asm_text: "vorr.i32 q8, #0x0" + - + asm_text: "vbic d16, d17, d16" + - + asm_text: "vbic q8, q8, q9" + - + asm_text: "vbic q10, q10, q11" + - + asm_text: "vbic d9, d9, d1" + - + asm_text: "vbic.i16 d16, #0xff00" + - + asm_text: "vbic.i16 q8, #0xff00" + - + asm_text: "vbic.i16 d16, #0xff" + - + asm_text: "vbic.i16 q8, #0xff" + - + asm_text: "vbic.i32 d16, #0xff000000" + - + asm_text: "vbic.i32 q8, #0xff000000" + - + asm_text: "vbic.i32 d16, #0xff0000" + - + asm_text: "vbic.i32 q8, #0xff0000" + - + asm_text: "vbic.i32 d16, #0xff00" + - + asm_text: "vbic.i32 q8, #0xff00" + - + asm_text: "vbic.i32 d16, #0xff" + - + asm_text: "vbic.i32 q8, #0xff" + - + asm_text: "vbic.i16 d10, #0xfc" + - + asm_text: "vbic.i16 q10, #0xfc" + - + asm_text: "vbic.i16 d10, #0xfc00" + - + asm_text: "vbic.i16 q10, #0xfc00" + - + asm_text: "vbic.i32 d10, #0xfc000000" + - + asm_text: "vbic.i32 q10, #0xfc000000" + - + asm_text: "vbic.i32 d10, #0xfc0000" + - + asm_text: "vbic.i32 q10, #0xfc0000" + - + asm_text: "vbic.i32 d10, #0xfc00" + - + asm_text: "vbic.i32 q10, #0xfc00" + - + asm_text: "vbic.i32 d10, #0xfc" + - + asm_text: "vbic.i32 q10, #0xfc" + - + asm_text: "vorn d16, d17, d16" + - + asm_text: "vorn q8, q8, q9" + - + asm_text: "vmvn d16, d16" + - + asm_text: "vmvn q8, q8" + - + asm_text: "vbsl d18, d17, d16" + - + asm_text: "vbsl q8, q10, q9" + - + asm_text: "vbit d18, d17, d16" + - + asm_text: "vbit q8, q10, q9" + - + asm_text: "vbif d18, d17, d16" + - + asm_text: "vbif q8, q10, q9" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "veor q4, q7, q3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vand d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr d4, d7, d3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vorr q4, q7, q3" + - + asm_text: "vand q6, q6, q5" + - + asm_text: "vand q6, q6, q5" + - + asm_text: "vand q7, q7, q1" + - + asm_text: "vand q8, q8, q2" + - + asm_text: "vand q8, q8, q2" + - + asm_text: "veor q6, q6, q5" + - + asm_text: "veor q6, q6, q5" + - + asm_text: "veor q7, q7, q1" + - + asm_text: "veor q8, q8, q2" + - + asm_text: "veor q8, q8, q2" + - + asm_text: "veor q6, q6, q5" + - + asm_text: "veor q6, q6, q5" + - + asm_text: "veor q7, q7, q1" + - + asm_text: "veor q8, q8, q2" + - + asm_text: "veor q8, q8, q2" + - + asm_text: "vclt.s16 q5, q5, #0" + - + asm_text: "vclt.s16 d5, d5, #0" + - + asm_text: "vceq.i16 q5, q5, q3" + - + asm_text: "vceq.i16 d5, d5, d3" + - + asm_text: "vcgt.s16 q5, q5, q3" + - + asm_text: "vcgt.s16 d5, d5, d3" + - + asm_text: "vcge.s16 q5, q5, q3" + - + asm_text: "vcge.s16 d5, d5, d3" + - + asm_text: "vcgt.s16 q5, q5, #0" + - + asm_text: "vcgt.s16 d5, d5, #0" + - + asm_text: "vcge.s16 q5, q5, #0" + - + asm_text: "vcge.s16 d5, d5, #0" + - + asm_text: "vceq.i16 q5, q5, #0" + - + asm_text: "vceq.i16 d5, d5, #0" + - + asm_text: "vcle.s16 q5, q5, #0" + - + asm_text: "vcle.s16 d5, d5, #0" + - + asm_text: "vacge.f32 d5, d5, d30" + - + asm_text: "vacge.f32 q5, q5, q3" + - + asm_text: "vacgt.f32 d5, d5, d30" + - + asm_text: "vacgt.f32 q5, q5, q3" diff --git a/tests/MC/ARM/neon-cmp-encoding.s.yaml b/tests/MC/ARM/neon-cmp-encoding.s.yaml new file mode 100644 index 0000000000..8a72f2fce8 --- /dev/null +++ b/tests/MC/ARM/neon-cmp-encoding.s.yaml @@ -0,0 +1,182 @@ +test_cases: + - + input: + bytes: [ 0xb1, 0x08, 0x40, 0xf3, 0xb1, 0x08, 0x50, 0xf3, 0xb1, 0x08, 0x60, 0xf3, 0xa1, 0x0e, 0x40, 0xf2, 0xf2, 0x08, 0x40, 0xf3, 0xf2, 0x08, 0x50, 0xf3, 0xf2, 0x08, 0x60, 0xf3, 0xe2, 0x0e, 0x40, 0xf2, 0xb1, 0x03, 0x40, 0xf2, 0xb1, 0x03, 0x50, 0xf2, 0xb1, 0x03, 0x60, 0xf2, 0xb1, 0x03, 0x40, 0xf3, 0xb1, 0x03, 0x50, 0xf3, 0xb1, 0x03, 0x60, 0xf3, 0xa1, 0x0e, 0x40, 0xf3, 0xf2, 0x03, 0x40, 0xf2, 0xf2, 0x03, 0x50, 0xf2, 0xf2, 0x03, 0x60, 0xf2, 0xf2, 0x03, 0x40, 0xf3, 0xf2, 0x03, 0x50, 0xf3, 0xf2, 0x03, 0x60, 0xf3, 0xe2, 0x0e, 0x40, 0xf3, 0xb1, 0x0e, 0x40, 0xf3, 0xf2, 0x0e, 0x40, 0xf3, 0xa1, 0x03, 0x40, 0xf2, 0xa1, 0x03, 0x50, 0xf2, 0xa1, 0x03, 0x60, 0xf2, 0xa1, 0x03, 0x40, 0xf3, 0xa1, 0x03, 0x50, 0xf3, 0xa1, 0x03, 0x60, 0xf3, 0xa1, 0x0e, 0x60, 0xf3, 0xe2, 0x03, 0x40, 0xf2, 0xe2, 0x03, 0x50, 0xf2, 0xe2, 0x03, 0x60, 0xf2, 0xe2, 0x03, 0x40, 0xf3, 0xe2, 0x03, 0x50, 0xf3, 0xe2, 0x03, 0x60, 0xf3, 0xe2, 0x0e, 0x60, 0xf3, 0xb1, 0x0e, 0x60, 0xf3, 0xf2, 0x0e, 0x60, 0xf3, 0xb1, 0x08, 0x40, 0xf2, 0xb1, 0x08, 0x50, 0xf2, 0xb1, 0x08, 0x60, 0xf2, 0xf2, 0x08, 0x40, 0xf2, 0xf2, 0x08, 0x50, 0xf2, 0xf2, 0x08, 0x60, 0xf2, 0x20, 0x01, 0xf1, 0xf3, 0xa0, 0x00, 0xf1, 0xf3, 0xa0, 0x01, 0xf1, 0xf3, 0x20, 0x00, 0xf1, 0xf3, 0x20, 0x02, 0xf1, 0xf3, 0x6a, 0x83, 0x46, 0xf2, 0x6a, 0x83, 0x56, 0xf2, 0x6a, 0x83, 0x66, 0xf2, 0x6a, 0x83, 0x46, 0xf3, 0x6a, 0x83, 0x56, 0xf3, 0x6a, 0x83, 0x66, 0xf3, 0x6a, 0x8e, 0x66, 0xf3, 0x0d, 0xc3, 0x03, 0xf2, 0x0d, 0xc3, 0x13, 0xf2, 0x0d, 0xc3, 0x23, 0xf2, 0x0d, 0xc3, 0x03, 0xf3, 0x0d, 0xc3, 0x13, 0xf3, 0x0d, 0xc3, 0x23, 0xf3, 0x0d, 0xce, 0x23, 0xf3, 0xb0, 0x03, 0x41, 0xf2, 0xb0, 0x03, 0x51, 0xf2, 0xb0, 0x03, 0x61, 0xf2, 0xb0, 0x03, 0x41, 0xf3, 0xb0, 0x03, 0x51, 0xf3, 0xb0, 0x03, 0x61, 0xf3, 0xa0, 0x0e, 0x41, 0xf3, 0xf0, 0x03, 0x42, 0xf2, 0xf0, 0x03, 0x52, 0xf2, 0xf0, 0x03, 0x62, 0xf2, 0xf0, 0x03, 0x42, 0xf3, 0xf0, 0x03, 0x52, 0xf3, 0xf0, 0x03, 0x62, 0xf3, 0xe0, 0x0e, 0x42, 0xf3, 0xf6, 0x2e, 0x68, 0xf3, 0x1b, 0x9e, 0x2c, 0xf3, 0xf6, 0x6e, 0x68, 0xf3, 0x1b, 0xbe, 0x2c, 0xf3, 0xf6, 0x2e, 0x48, 0xf3, 0x1b, 0x9e, 0x0c, 0xf3, 0xf6, 0x6e, 0x48, 0xf3, 0x1b, 0xbe, 0x0c, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vceq.i8 d16, d16, d17" + - + asm_text: "vceq.i16 d16, d16, d17" + - + asm_text: "vceq.i32 d16, d16, d17" + - + asm_text: "vceq.f32 d16, d16, d17" + - + asm_text: "vceq.i8 q8, q8, q9" + - + asm_text: "vceq.i16 q8, q8, q9" + - + asm_text: "vceq.i32 q8, q8, q9" + - + asm_text: "vceq.f32 q8, q8, q9" + - + asm_text: "vcge.s8 d16, d16, d17" + - + asm_text: "vcge.s16 d16, d16, d17" + - + asm_text: "vcge.s32 d16, d16, d17" + - + asm_text: "vcge.u8 d16, d16, d17" + - + asm_text: "vcge.u16 d16, d16, d17" + - + asm_text: "vcge.u32 d16, d16, d17" + - + asm_text: "vcge.f32 d16, d16, d17" + - + asm_text: "vcge.s8 q8, q8, q9" + - + asm_text: "vcge.s16 q8, q8, q9" + - + asm_text: "vcge.s32 q8, q8, q9" + - + asm_text: "vcge.u8 q8, q8, q9" + - + asm_text: "vcge.u16 q8, q8, q9" + - + asm_text: "vcge.u32 q8, q8, q9" + - + asm_text: "vcge.f32 q8, q8, q9" + - + asm_text: "vacge.f32 d16, d16, d17" + - + asm_text: "vacge.f32 q8, q8, q9" + - + asm_text: "vcgt.s8 d16, d16, d17" + - + asm_text: "vcgt.s16 d16, d16, d17" + - + asm_text: "vcgt.s32 d16, d16, d17" + - + asm_text: "vcgt.u8 d16, d16, d17" + - + asm_text: "vcgt.u16 d16, d16, d17" + - + asm_text: "vcgt.u32 d16, d16, d17" + - + asm_text: "vcgt.f32 d16, d16, d17" + - + asm_text: "vcgt.s8 q8, q8, q9" + - + asm_text: "vcgt.s16 q8, q8, q9" + - + asm_text: "vcgt.s32 q8, q8, q9" + - + asm_text: "vcgt.u8 q8, q8, q9" + - + asm_text: "vcgt.u16 q8, q8, q9" + - + asm_text: "vcgt.u32 q8, q8, q9" + - + asm_text: "vcgt.f32 q8, q8, q9" + - + asm_text: "vacgt.f32 d16, d16, d17" + - + asm_text: "vacgt.f32 q8, q8, q9" + - + asm_text: "vtst.8 d16, d16, d17" + - + asm_text: "vtst.16 d16, d16, d17" + - + asm_text: "vtst.32 d16, d16, d17" + - + asm_text: "vtst.8 q8, q8, q9" + - + asm_text: "vtst.16 q8, q8, q9" + - + asm_text: "vtst.32 q8, q8, q9" + - + asm_text: "vceq.i8 d16, d16, #0" + - + asm_text: "vcge.s8 d16, d16, #0" + - + asm_text: "vcle.s8 d16, d16, #0" + - + asm_text: "vcgt.s8 d16, d16, #0" + - + asm_text: "vclt.s8 d16, d16, #0" + - + asm_text: "vcgt.s8 q12, q3, q13" + - + asm_text: "vcgt.s16 q12, q3, q13" + - + asm_text: "vcgt.s32 q12, q3, q13" + - + asm_text: "vcgt.u8 q12, q3, q13" + - + asm_text: "vcgt.u16 q12, q3, q13" + - + asm_text: "vcgt.u32 q12, q3, q13" + - + asm_text: "vcgt.f32 q12, q3, q13" + - + asm_text: "vcgt.s8 d12, d3, d13" + - + asm_text: "vcgt.s16 d12, d3, d13" + - + asm_text: "vcgt.s32 d12, d3, d13" + - + asm_text: "vcgt.u8 d12, d3, d13" + - + asm_text: "vcgt.u16 d12, d3, d13" + - + asm_text: "vcgt.u32 d12, d3, d13" + - + asm_text: "vcgt.f32 d12, d3, d13" + - + asm_text: "vcge.s8 d16, d17, d16" + - + asm_text: "vcge.s16 d16, d17, d16" + - + asm_text: "vcge.s32 d16, d17, d16" + - + asm_text: "vcge.u8 d16, d17, d16" + - + asm_text: "vcge.u16 d16, d17, d16" + - + asm_text: "vcge.u32 d16, d17, d16" + - + asm_text: "vcge.f32 d16, d17, d16" + - + asm_text: "vcge.s8 q8, q9, q8" + - + asm_text: "vcge.s16 q8, q9, q8" + - + asm_text: "vcge.s32 q8, q9, q8" + - + asm_text: "vcge.u8 q8, q9, q8" + - + asm_text: "vcge.u16 q8, q9, q8" + - + asm_text: "vcge.u32 q8, q9, q8" + - + asm_text: "vcge.f32 q8, q9, q8" + - + asm_text: "vacgt.f32 q9, q12, q11" + - + asm_text: "vacgt.f32 d9, d12, d11" + - + asm_text: "vacgt.f32 q11, q12, q11" + - + asm_text: "vacgt.f32 d11, d12, d11" + - + asm_text: "vacge.f32 q9, q12, q11" + - + asm_text: "vacge.f32 d9, d12, d11" + - + asm_text: "vacge.f32 q11, q12, q11" + - + asm_text: "vacge.f32 d11, d12, d11" diff --git a/tests/MC/ARM/neon-convert-encoding.s.yaml b/tests/MC/ARM/neon-convert-encoding.s.yaml new file mode 100644 index 0000000000..dd1a7b4f38 --- /dev/null +++ b/tests/MC/ARM/neon-convert-encoding.s.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x07, 0xfb, 0xf3, 0xa0, 0x07, 0xfb, 0xf3, 0x20, 0x06, 0xfb, 0xf3, 0xa0, 0x06, 0xfb, 0xf3, 0x60, 0x07, 0xfb, 0xf3, 0xe0, 0x07, 0xfb, 0xf3, 0x60, 0x06, 0xfb, 0xf3, 0xe0, 0x06, 0xfb, 0xf3, 0x30, 0x0f, 0xff, 0xf2, 0x20, 0x07, 0xfb, 0xf3, 0x30, 0x0f, 0xff, 0xf3, 0xa0, 0x07, 0xfb, 0xf3, 0x30, 0x0e, 0xff, 0xf2, 0x20, 0x06, 0xfb, 0xf3, 0x30, 0x0e, 0xff, 0xf3, 0xa0, 0x06, 0xfb, 0xf3, 0x70, 0x0f, 0xff, 0xf2, 0x60, 0x07, 0xfb, 0xf3, 0x70, 0x0f, 0xff, 0xf3, 0xe0, 0x07, 0xfb, 0xf3, 0x70, 0x0e, 0xff, 0xf2, 0x60, 0x06, 0xfb, 0xf3, 0x70, 0x0e, 0xff, 0xf3, 0xe0, 0x06, 0xfb, 0xf3, 0x20, 0x07, 0xf6, 0xf3, 0x20, 0x06, 0xf6, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vcvt.s32.f32 d16, d16" + - + asm_text: "vcvt.u32.f32 d16, d16" + - + asm_text: "vcvt.f32.s32 d16, d16" + - + asm_text: "vcvt.f32.u32 d16, d16" + - + asm_text: "vcvt.s32.f32 q8, q8" + - + asm_text: "vcvt.u32.f32 q8, q8" + - + asm_text: "vcvt.f32.s32 q8, q8" + - + asm_text: "vcvt.f32.u32 q8, q8" + - + asm_text: "vcvt.s32.f32 d16, d16, #1" + - + asm_text: "vcvt.s32.f32 d16, d16" + - + asm_text: "vcvt.u32.f32 d16, d16, #1" + - + asm_text: "vcvt.u32.f32 d16, d16" + - + asm_text: "vcvt.f32.s32 d16, d16, #1" + - + asm_text: "vcvt.f32.s32 d16, d16" + - + asm_text: "vcvt.f32.u32 d16, d16, #1" + - + asm_text: "vcvt.f32.u32 d16, d16" + - + asm_text: "vcvt.s32.f32 q8, q8, #1" + - + asm_text: "vcvt.s32.f32 q8, q8" + - + asm_text: "vcvt.u32.f32 q8, q8, #1" + - + asm_text: "vcvt.u32.f32 q8, q8" + - + asm_text: "vcvt.f32.s32 q8, q8, #1" + - + asm_text: "vcvt.f32.s32 q8, q8" + - + asm_text: "vcvt.f32.u32 q8, q8, #1" + - + asm_text: "vcvt.f32.u32 q8, q8" + - + asm_text: "vcvt.f32.f16 q8, d16" + - + asm_text: "vcvt.f16.f32 d16, q8" diff --git a/tests/MC/ARM/neon-crypto.s.yaml b/tests/MC/ARM/neon-crypto.s.yaml new file mode 100644 index 0000000000..bcabb88d52 --- /dev/null +++ b/tests/MC/ARM/neon-crypto.s.yaml @@ -0,0 +1,38 @@ +test_cases: + - + input: + bytes: [ 0x42, 0x03, 0xb0, 0xf3, 0x02, 0x03, 0xb0, 0xf3, 0xc2, 0x03, 0xb0, 0xf3, 0x82, 0x03, 0xb0, 0xf3, 0xc2, 0x02, 0xb9, 0xf3, 0x82, 0x03, 0xba, 0xf3, 0xc2, 0x03, 0xba, 0xf3, 0x44, 0x0c, 0x02, 0xf2, 0x44, 0x0c, 0x22, 0xf2, 0x44, 0x0c, 0x12, 0xf2, 0x44, 0x0c, 0x32, 0xf2, 0x44, 0x0c, 0x02, 0xf3, 0x44, 0x0c, 0x12, 0xf3, 0x44, 0x0c, 0x22, 0xf3, 0xa1, 0x0e, 0xe0, 0xf2 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "aesd.8 q0, q1" + - + asm_text: "aese.8 q0, q1" + - + asm_text: "aesimc.8 q0, q1" + - + asm_text: "aesmc.8 q0, q1" + - + asm_text: "sha1h.32 q0, q1" + - + asm_text: "sha1su1.32 q0, q1" + - + asm_text: "sha256su0.32 q0, q1" + - + asm_text: "sha1c.32 q0, q1, q2" + - + asm_text: "sha1m.32 q0, q1, q2" + - + asm_text: "sha1p.32 q0, q1, q2" + - + asm_text: "sha1su0.32 q0, q1, q2" + - + asm_text: "sha256h.32 q0, q1, q2" + - + asm_text: "sha256h2.32 q0, q1, q2" + - + asm_text: "sha256su1.32 q0, q1, q2" + - + asm_text: "vmull.p64 q8, d16, d17" diff --git a/tests/MC/ARM/neon-dup-encoding.s.yaml b/tests/MC/ARM/neon-dup-encoding.s.yaml new file mode 100644 index 0000000000..00c93e4bb7 --- /dev/null +++ b/tests/MC/ARM/neon-dup-encoding.s.yaml @@ -0,0 +1,32 @@ +test_cases: + - + input: + bytes: [ 0x90, 0x0b, 0xc0, 0xee, 0xb0, 0x0b, 0x80, 0xee, 0x90, 0x0b, 0x80, 0xee, 0x90, 0x0b, 0xe0, 0xee, 0xb0, 0x0b, 0xa0, 0xee, 0x90, 0x0b, 0xa0, 0xee, 0x20, 0x0c, 0xf3, 0xf3, 0x20, 0x0c, 0xf6, 0xf3, 0x20, 0x0c, 0xfc, 0xf3, 0x60, 0x0c, 0xf3, 0xf3, 0x60, 0x0c, 0xf6, 0xf3, 0x60, 0x0c, 0xfc, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vdup.8 d16, r0" + - + asm_text: "vdup.16 d16, r0" + - + asm_text: "vdup.32 d16, r0" + - + asm_text: "vdup.8 q8, r0" + - + asm_text: "vdup.16 q8, r0" + - + asm_text: "vdup.32 q8, r0" + - + asm_text: "vdup.8 d16, d16[1]" + - + asm_text: "vdup.16 d16, d16[1]" + - + asm_text: "vdup.32 d16, d16[1]" + - + asm_text: "vdup.8 q8, d16[1]" + - + asm_text: "vdup.16 q8, d16[1]" + - + asm_text: "vdup.32 q8, d16[1]" diff --git a/tests/MC/ARM/neon-minmax-encoding.s.yaml b/tests/MC/ARM/neon-minmax-encoding.s.yaml new file mode 100644 index 0000000000..83bb5e2288 --- /dev/null +++ b/tests/MC/ARM/neon-minmax-encoding.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x03, 0x16, 0x02, 0xf2, 0x06, 0x46, 0x15, 0xf2, 0x09, 0x76, 0x28, 0xf2, 0x0c, 0xa6, 0x0b, 0xf3, 0x0f, 0xd6, 0x1e, 0xf3, 0xa2, 0x06, 0x61, 0xf3, 0xa5, 0x3f, 0x44, 0xf2, 0x03, 0x26, 0x02, 0xf2, 0x06, 0x56, 0x15, 0xf2, 0x09, 0x86, 0x28, 0xf2, 0x0c, 0xb6, 0x0b, 0xf3, 0x0f, 0xe6, 0x1e, 0xf3, 0xa2, 0x16, 0x61, 0xf3, 0xa5, 0x4f, 0x44, 0xf2, 0x46, 0x26, 0x04, 0xf2, 0x4c, 0x86, 0x1a, 0xf2, 0xe2, 0xe6, 0x20, 0xf2, 0xe8, 0x46, 0x46, 0xf3, 0xee, 0xa6, 0x5c, 0xf3, 0x60, 0xc6, 0x2e, 0xf3, 0x42, 0x2f, 0x4a, 0xf2, 0x46, 0x46, 0x04, 0xf2, 0x4c, 0xa6, 0x1a, 0xf2, 0xe2, 0x06, 0x60, 0xf2, 0xc4, 0x66, 0x46, 0xf3, 0x4a, 0x86, 0x18, 0xf3, 0x60, 0xe6, 0x2e, 0xf3, 0x42, 0x4f, 0x04, 0xf2, 0x13, 0x16, 0x02, 0xf2, 0x16, 0x46, 0x15, 0xf2, 0x19, 0x76, 0x28, 0xf2, 0x1c, 0xa6, 0x0b, 0xf3, 0x1f, 0xd6, 0x1e, 0xf3, 0xb2, 0x06, 0x61, 0xf3, 0xa5, 0x3f, 0x64, 0xf2, 0x13, 0x26, 0x02, 0xf2, 0x16, 0x56, 0x15, 0xf2, 0x19, 0x86, 0x28, 0xf2, 0x1c, 0xb6, 0x0b, 0xf3, 0x1f, 0xe6, 0x1e, 0xf3, 0xb2, 0x16, 0x61, 0xf3, 0xa5, 0x4f, 0x64, 0xf2, 0x56, 0x26, 0x04, 0xf2, 0x5c, 0x86, 0x1a, 0xf2, 0xf2, 0xe6, 0x20, 0xf2, 0xf8, 0x46, 0x46, 0xf3, 0xfe, 0xa6, 0x5c, 0xf3, 0x70, 0xc6, 0x2e, 0xf3, 0x42, 0x2f, 0x6a, 0xf2, 0x56, 0x46, 0x04, 0xf2, 0x5c, 0xa6, 0x1a, 0xf2, 0xf2, 0x06, 0x60, 0xf2, 0xd4, 0x66, 0x46, 0xf3, 0x5a, 0x86, 0x18, 0xf3, 0x70, 0xe6, 0x2e, 0xf3, 0x42, 0x4f, 0x24, 0xf2 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vmax.s8 d1, d2, d3" + - + asm_text: "vmax.s16 d4, d5, d6" + - + asm_text: "vmax.s32 d7, d8, d9" + - + asm_text: "vmax.u8 d10, d11, d12" + - + asm_text: "vmax.u16 d13, d14, d15" + - + asm_text: "vmax.u32 d16, d17, d18" + - + asm_text: "vmax.f32 d19, d20, d21" + - + asm_text: "vmax.s8 d2, d2, d3" + - + asm_text: "vmax.s16 d5, d5, d6" + - + asm_text: "vmax.s32 d8, d8, d9" + - + asm_text: "vmax.u8 d11, d11, d12" + - + asm_text: "vmax.u16 d14, d14, d15" + - + asm_text: "vmax.u32 d17, d17, d18" + - + asm_text: "vmax.f32 d20, d20, d21" + - + asm_text: "vmax.s8 q1, q2, q3" + - + asm_text: "vmax.s16 q4, q5, q6" + - + asm_text: "vmax.s32 q7, q8, q9" + - + asm_text: "vmax.u8 q10, q11, q12" + - + asm_text: "vmax.u16 q13, q14, q15" + - + asm_text: "vmax.u32 q6, q7, q8" + - + asm_text: "vmax.f32 q9, q5, q1" + - + asm_text: "vmax.s8 q2, q2, q3" + - + asm_text: "vmax.s16 q5, q5, q6" + - + asm_text: "vmax.s32 q8, q8, q9" + - + asm_text: "vmax.u8 q11, q11, q2" + - + asm_text: "vmax.u16 q4, q4, q5" + - + asm_text: "vmax.u32 q7, q7, q8" + - + asm_text: "vmax.f32 q2, q2, q1" + - + asm_text: "vmin.s8 d1, d2, d3" + - + asm_text: "vmin.s16 d4, d5, d6" + - + asm_text: "vmin.s32 d7, d8, d9" + - + asm_text: "vmin.u8 d10, d11, d12" + - + asm_text: "vmin.u16 d13, d14, d15" + - + asm_text: "vmin.u32 d16, d17, d18" + - + asm_text: "vmin.f32 d19, d20, d21" + - + asm_text: "vmin.s8 d2, d2, d3" + - + asm_text: "vmin.s16 d5, d5, d6" + - + asm_text: "vmin.s32 d8, d8, d9" + - + asm_text: "vmin.u8 d11, d11, d12" + - + asm_text: "vmin.u16 d14, d14, d15" + - + asm_text: "vmin.u32 d17, d17, d18" + - + asm_text: "vmin.f32 d20, d20, d21" + - + asm_text: "vmin.s8 q1, q2, q3" + - + asm_text: "vmin.s16 q4, q5, q6" + - + asm_text: "vmin.s32 q7, q8, q9" + - + asm_text: "vmin.u8 q10, q11, q12" + - + asm_text: "vmin.u16 q13, q14, q15" + - + asm_text: "vmin.u32 q6, q7, q8" + - + asm_text: "vmin.f32 q9, q5, q1" + - + asm_text: "vmin.s8 q2, q2, q3" + - + asm_text: "vmin.s16 q5, q5, q6" + - + asm_text: "vmin.s32 q8, q8, q9" + - + asm_text: "vmin.u8 q11, q11, q2" + - + asm_text: "vmin.u16 q4, q4, q5" + - + asm_text: "vmin.u32 q7, q7, q8" + - + asm_text: "vmin.f32 q2, q2, q1" diff --git a/tests/MC/ARM/neon-mov-encoding.s.yaml b/tests/MC/ARM/neon-mov-encoding.s.yaml new file mode 100644 index 0000000000..52866b2080 --- /dev/null +++ b/tests/MC/ARM/neon-mov-encoding.s.yaml @@ -0,0 +1,158 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x0e, 0xc0, 0xf2, 0x10, 0x08, 0xc1, 0xf2, 0x10, 0x0a, 0xc1, 0xf2, 0x10, 0x00, 0xc2, 0xf2, 0x10, 0x02, 0xc2, 0xf2, 0x10, 0x04, 0xc2, 0xf2, 0x10, 0x06, 0xc2, 0xf2, 0x10, 0x0c, 0xc2, 0xf2, 0x10, 0x0d, 0xc2, 0xf2, 0x33, 0x0e, 0xc1, 0xf3, 0x58, 0x0e, 0xc0, 0xf2, 0x50, 0x08, 0xc1, 0xf2, 0x50, 0x0a, 0xc1, 0xf2, 0x50, 0x00, 0xc2, 0xf2, 0x50, 0x02, 0xc2, 0xf2, 0x50, 0x04, 0xc2, 0xf2, 0x50, 0x06, 0xc2, 0xf2, 0x50, 0x0c, 0xc2, 0xf2, 0x50, 0x0d, 0xc2, 0xf2, 0x73, 0x0e, 0xc1, 0xf3, 0x30, 0x08, 0xc1, 0xf2, 0x30, 0x0a, 0xc1, 0xf2, 0x30, 0x00, 0xc2, 0xf2, 0x30, 0x02, 0xc2, 0xf2, 0x30, 0x04, 0xc2, 0xf2, 0x30, 0x06, 0xc2, 0xf2, 0x30, 0x0c, 0xc2, 0xf2, 0x30, 0x0d, 0xc2, 0xf2, 0x30, 0x0a, 0xc8, 0xf2, 0x30, 0x0a, 0xd0, 0xf2, 0x30, 0x0a, 0xe0, 0xf2, 0x30, 0x0a, 0xc8, 0xf3, 0x30, 0x0a, 0xd0, 0xf3, 0x30, 0x0a, 0xe0, 0xf3, 0x20, 0x02, 0xf2, 0xf3, 0x20, 0x02, 0xf6, 0xf3, 0x20, 0x02, 0xfa, 0xf3, 0xa0, 0x02, 0xf2, 0xf3, 0xa0, 0x02, 0xf6, 0xf3, 0xa0, 0x02, 0xfa, 0xf3, 0xe0, 0x02, 0xf2, 0xf3, 0xe0, 0x02, 0xf6, 0xf3, 0xe0, 0x02, 0xfa, 0xf3, 0x60, 0x02, 0xf2, 0xf3, 0x60, 0x02, 0xf6, 0xf3, 0x60, 0x02, 0xfa, 0xf3, 0xb0, 0x0b, 0x50, 0xee, 0xf0, 0x0b, 0x10, 0xee, 0xb0, 0x0b, 0xd0, 0xee, 0xf0, 0x0b, 0x90, 0xee, 0x90, 0x0b, 0x30, 0xee, 0xb0, 0x1b, 0x40, 0xee, 0xf0, 0x1b, 0x00, 0xee, 0x90, 0x1b, 0x20, 0xee, 0xb0, 0x1b, 0x42, 0xee, 0xf0, 0x1b, 0x02, 0xee, 0x90, 0x1b, 0x22, 0xee, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vmov.i8 d16, #0x8" + - + asm_text: "vmov.i16 d16, #0x10" + - + asm_text: "vmov.i16 d16, #0x1000" + - + asm_text: "vmov.i32 d16, #0x20" + - + asm_text: "vmov.i32 d16, #0x2000" + - + asm_text: "vmov.i32 d16, #0x200000" + - + asm_text: "vmov.i32 d16, #0x20000000" + - + asm_text: "vmov.i32 d16, #0x20ff" + - + asm_text: "vmov.i32 d16, #0x20ffff" + - + asm_text: "vmov.i64 d16, #0xff0000ff0000ffff" + - + asm_text: "vmov.i8 q8, #0x8" + - + asm_text: "vmov.i16 q8, #0x10" + - + asm_text: "vmov.i16 q8, #0x1000" + - + asm_text: "vmov.i32 q8, #0x20" + - + asm_text: "vmov.i32 q8, #0x2000" + - + asm_text: "vmov.i32 q8, #0x200000" + - + asm_text: "vmov.i32 q8, #0x20000000" + - + asm_text: "vmov.i32 q8, #0x20ff" + - + asm_text: "vmov.i32 q8, #0x20ffff" + - + asm_text: "vmov.i64 q8, #0xff0000ff0000ffff" + - + asm_text: "vmvn.i16 d16, #0x10" + - + asm_text: "vmvn.i16 d16, #0x1000" + - + asm_text: "vmvn.i32 d16, #0x20" + - + asm_text: "vmvn.i32 d16, #0x2000" + - + asm_text: "vmvn.i32 d16, #0x200000" + - + asm_text: "vmvn.i32 d16, #0x20000000" + - + asm_text: "vmvn.i32 d16, #0x20ff" + - + asm_text: "vmvn.i32 d16, #0x20ffff" + - + asm_text: "vmovl.s8 q8, d16" + - + asm_text: "vmovl.s16 q8, d16" + - + asm_text: "vmovl.s32 q8, d16" + - + asm_text: "vmovl.u8 q8, d16" + - + asm_text: "vmovl.u16 q8, d16" + - + asm_text: "vmovl.u32 q8, d16" + - + asm_text: "vmovn.i16 d16, q8" + - + asm_text: "vmovn.i32 d16, q8" + - + asm_text: "vmovn.i64 d16, q8" + - + asm_text: "vqmovn.s16 d16, q8" + - + asm_text: "vqmovn.s32 d16, q8" + - + asm_text: "vqmovn.s64 d16, q8" + - + asm_text: "vqmovn.u16 d16, q8" + - + asm_text: "vqmovn.u32 d16, q8" + - + asm_text: "vqmovn.u64 d16, q8" + - + asm_text: "vqmovun.s16 d16, q8" + - + asm_text: "vqmovun.s32 d16, q8" + - + asm_text: "vqmovun.s64 d16, q8" + - + asm_text: "vmov.s8 r0, d16[1]" + - + asm_text: "vmov.s16 r0, d16[1]" + - + asm_text: "vmov.u8 r0, d16[1]" + - + asm_text: "vmov.u16 r0, d16[1]" + - + asm_text: "vmov.32 r0, d16[1]" + - + asm_text: "vmov.8 d16[1], r1" + - + asm_text: "vmov.16 d16[1], r1" + - + asm_text: "vmov.32 d16[1], r1" + - + asm_text: "vmov.8 d18[1], r1" + - + asm_text: "vmov.16 d18[1], r1" + - + asm_text: "vmov.32 d18[1], r1" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" + - + asm_text: "vmvn d1, d2" diff --git a/tests/MC/ARM/neon-mul-accum-encoding.s.yaml b/tests/MC/ARM/neon-mul-accum-encoding.s.yaml new file mode 100644 index 0000000000..023b3df0c0 --- /dev/null +++ b/tests/MC/ARM/neon-mul-accum-encoding.s.yaml @@ -0,0 +1,84 @@ +test_cases: + - + input: + bytes: [ 0xa1, 0x09, 0x42, 0xf2, 0xa1, 0x09, 0x52, 0xf2, 0xa1, 0x09, 0x62, 0xf2, 0xb1, 0x0d, 0x42, 0xf2, 0xe4, 0x29, 0x40, 0xf2, 0xe4, 0x29, 0x50, 0xf2, 0xe4, 0x29, 0x60, 0xf2, 0xf4, 0x2d, 0x40, 0xf2, 0xc3, 0x80, 0xe0, 0xf3, 0xa2, 0x08, 0xc3, 0xf2, 0xa2, 0x08, 0xd3, 0xf2, 0xa2, 0x08, 0xe3, 0xf2, 0xa2, 0x08, 0xc3, 0xf3, 0xa2, 0x08, 0xd3, 0xf3, 0xa2, 0x08, 0xe3, 0xf3, 0xa2, 0x09, 0xd3, 0xf2, 0xa2, 0x09, 0xe3, 0xf2, 0x47, 0x63, 0xdb, 0xf2, 0x4f, 0x63, 0xdb, 0xf2, 0x67, 0x63, 0xdb, 0xf2, 0x6f, 0x63, 0xdb, 0xf2, 0xa1, 0x09, 0x42, 0xf3, 0xa1, 0x09, 0x52, 0xf3, 0xa1, 0x09, 0x62, 0xf3, 0xb1, 0x0d, 0x62, 0xf2, 0xe4, 0x29, 0x40, 0xf3, 0xe4, 0x29, 0x50, 0xf3, 0xe4, 0x29, 0x60, 0xf3, 0xf4, 0x2d, 0x60, 0xf2, 0xe6, 0x84, 0x98, 0xf3, 0xa2, 0x0a, 0xc3, 0xf2, 0xa2, 0x0a, 0xd3, 0xf2, 0xa2, 0x0a, 0xe3, 0xf2, 0xa2, 0x0a, 0xc3, 0xf3, 0xa2, 0x0a, 0xd3, 0xf3, 0xa2, 0x0a, 0xe3, 0xf3, 0xa2, 0x0b, 0xd3, 0xf2, 0xa2, 0x0b, 0xe3, 0xf2 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vmla.i8 d16, d18, d17" + - + asm_text: "vmla.i16 d16, d18, d17" + - + asm_text: "vmla.i32 d16, d18, d17" + - + asm_text: "vmla.f32 d16, d18, d17" + - + asm_text: "vmla.i8 q9, q8, q10" + - + asm_text: "vmla.i16 q9, q8, q10" + - + asm_text: "vmla.i32 q9, q8, q10" + - + asm_text: "vmla.f32 q9, q8, q10" + - + asm_text: "vmla.i32 q12, q8, d3[0]" + - + asm_text: "vmlal.s8 q8, d19, d18" + - + asm_text: "vmlal.s16 q8, d19, d18" + - + asm_text: "vmlal.s32 q8, d19, d18" + - + asm_text: "vmlal.u8 q8, d19, d18" + - + asm_text: "vmlal.u16 q8, d19, d18" + - + asm_text: "vmlal.u32 q8, d19, d18" + - + asm_text: "vqdmlal.s16 q8, d19, d18" + - + asm_text: "vqdmlal.s32 q8, d19, d18" + - + asm_text: "vqdmlal.s16 q11, d11, d7[0]" + - + asm_text: "vqdmlal.s16 q11, d11, d7[1]" + - + asm_text: "vqdmlal.s16 q11, d11, d7[2]" + - + asm_text: "vqdmlal.s16 q11, d11, d7[3]" + - + asm_text: "vmls.i8 d16, d18, d17" + - + asm_text: "vmls.i16 d16, d18, d17" + - + asm_text: "vmls.i32 d16, d18, d17" + - + asm_text: "vmls.f32 d16, d18, d17" + - + asm_text: "vmls.i8 q9, q8, q10" + - + asm_text: "vmls.i16 q9, q8, q10" + - + asm_text: "vmls.i32 q9, q8, q10" + - + asm_text: "vmls.f32 q9, q8, q10" + - + asm_text: "vmls.i16 q4, q12, d6[2]" + - + asm_text: "vmlsl.s8 q8, d19, d18" + - + asm_text: "vmlsl.s16 q8, d19, d18" + - + asm_text: "vmlsl.s32 q8, d19, d18" + - + asm_text: "vmlsl.u8 q8, d19, d18" + - + asm_text: "vmlsl.u16 q8, d19, d18" + - + asm_text: "vmlsl.u32 q8, d19, d18" + - + asm_text: "vqdmlsl.s16 q8, d19, d18" + - + asm_text: "vqdmlsl.s32 q8, d19, d18" diff --git a/tests/MC/ARM/neon-mul-encoding.s.yaml b/tests/MC/ARM/neon-mul-encoding.s.yaml new file mode 100644 index 0000000000..9d31fcd860 --- /dev/null +++ b/tests/MC/ARM/neon-mul-encoding.s.yaml @@ -0,0 +1,150 @@ +test_cases: + - + input: + bytes: [ 0xb1, 0x09, 0x40, 0xf2, 0xb1, 0x09, 0x50, 0xf2, 0xb1, 0x09, 0x60, 0xf2, 0xb1, 0x0d, 0x40, 0xf3, 0xf2, 0x09, 0x40, 0xf2, 0xf2, 0x09, 0x50, 0xf2, 0xf2, 0x09, 0x60, 0xf2, 0xf2, 0x0d, 0x40, 0xf3, 0xb1, 0x09, 0x40, 0xf3, 0xf2, 0x09, 0x40, 0xf3, 0x68, 0x28, 0xd8, 0xf2, 0xb1, 0x09, 0x40, 0xf2, 0xb1, 0x09, 0x50, 0xf2, 0xb1, 0x09, 0x60, 0xf2, 0xb1, 0x0d, 0x40, 0xf3, 0xf2, 0x09, 0x40, 0xf2, 0xf2, 0x09, 0x50, 0xf2, 0xf2, 0x09, 0x60, 0xf2, 0xf2, 0x0d, 0x40, 0xf3, 0xb1, 0x09, 0x40, 0xf3, 0xf2, 0x09, 0x40, 0xf3, 0xa1, 0x0b, 0x50, 0xf2, 0xa1, 0x0b, 0x60, 0xf2, 0xe2, 0x0b, 0x50, 0xf2, 0xe2, 0x0b, 0x60, 0xf2, 0xa1, 0x0b, 0x50, 0xf2, 0xa1, 0x0b, 0x60, 0xf2, 0xe2, 0x0b, 0x50, 0xf2, 0xe2, 0x0b, 0x60, 0xf2, 0x43, 0xbc, 0x92, 0xf2, 0xa1, 0x0b, 0x50, 0xf3, 0xa1, 0x0b, 0x60, 0xf3, 0xe2, 0x0b, 0x50, 0xf3, 0xe2, 0x0b, 0x60, 0xf3, 0xa1, 0x0c, 0xc0, 0xf2, 0xa1, 0x0c, 0xd0, 0xf2, 0xa1, 0x0c, 0xe0, 0xf2, 0xa1, 0x0c, 0xc0, 0xf3, 0xa1, 0x0c, 0xd0, 0xf3, 0xa1, 0x0c, 0xe0, 0xf3, 0xa1, 0x0e, 0xc0, 0xf2, 0xa1, 0x0d, 0xd0, 0xf2, 0xa1, 0x0d, 0xe0, 0xf2, 0x64, 0x08, 0x90, 0xf2, 0x6f, 0x18, 0x91, 0xf2, 0x49, 0x28, 0x92, 0xf2, 0x42, 0x38, 0xa3, 0xf2, 0x63, 0x48, 0xa4, 0xf2, 0x44, 0x58, 0xa5, 0xf2, 0x65, 0x69, 0xa6, 0xf2, 0x64, 0x08, 0x90, 0xf3, 0x6f, 0x28, 0x92, 0xf3, 0x49, 0x48, 0x94, 0xf3, 0x42, 0x68, 0xa6, 0xf3, 0x63, 0x88, 0xa8, 0xf3, 0x44, 0xa8, 0xaa, 0xf3, 0x65, 0xc9, 0xac, 0xf3, 0x64, 0x98, 0x90, 0xf2, 0x6f, 0x88, 0x91, 0xf2, 0x49, 0x78, 0x92, 0xf2, 0x42, 0x68, 0xa3, 0xf2, 0x63, 0x58, 0xa4, 0xf2, 0x44, 0x48, 0xa5, 0xf2, 0x65, 0x39, 0xa6, 0xf2, 0x64, 0x28, 0xd0, 0xf3, 0x6f, 0x08, 0xd2, 0xf3, 0x49, 0xe8, 0x94, 0xf3, 0x42, 0xc8, 0xa6, 0xf3, 0x63, 0xa8, 0xa8, 0xf3, 0x44, 0x88, 0xaa, 0xf3, 0x65, 0x69, 0xac, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vmul.i8 d16, d16, d17" + - + asm_text: "vmul.i16 d16, d16, d17" + - + asm_text: "vmul.i32 d16, d16, d17" + - + asm_text: "vmul.f32 d16, d16, d17" + - + asm_text: "vmul.i8 q8, q8, q9" + - + asm_text: "vmul.i16 q8, q8, q9" + - + asm_text: "vmul.i32 q8, q8, q9" + - + asm_text: "vmul.f32 q8, q8, q9" + - + asm_text: "vmul.p8 d16, d16, d17" + - + asm_text: "vmul.p8 q8, q8, q9" + - + asm_text: "vmul.i16 d18, d8, d0[3]" + - + asm_text: "vmul.i8 d16, d16, d17" + - + asm_text: "vmul.i16 d16, d16, d17" + - + asm_text: "vmul.i32 d16, d16, d17" + - + asm_text: "vmul.f32 d16, d16, d17" + - + asm_text: "vmul.i8 q8, q8, q9" + - + asm_text: "vmul.i16 q8, q8, q9" + - + asm_text: "vmul.i32 q8, q8, q9" + - + asm_text: "vmul.f32 q8, q8, q9" + - + asm_text: "vmul.p8 d16, d16, d17" + - + asm_text: "vmul.p8 q8, q8, q9" + - + asm_text: "vqdmulh.s16 d16, d16, d17" + - + asm_text: "vqdmulh.s32 d16, d16, d17" + - + asm_text: "vqdmulh.s16 q8, q8, q9" + - + asm_text: "vqdmulh.s32 q8, q8, q9" + - + asm_text: "vqdmulh.s16 d16, d16, d17" + - + asm_text: "vqdmulh.s32 d16, d16, d17" + - + asm_text: "vqdmulh.s16 q8, q8, q9" + - + asm_text: "vqdmulh.s32 q8, q8, q9" + - + asm_text: "vqdmulh.s16 d11, d2, d3[0]" + - + asm_text: "vqrdmulh.s16 d16, d16, d17" + - + asm_text: "vqrdmulh.s32 d16, d16, d17" + - + asm_text: "vqrdmulh.s16 q8, q8, q9" + - + asm_text: "vqrdmulh.s32 q8, q8, q9" + - + asm_text: "vmull.s8 q8, d16, d17" + - + asm_text: "vmull.s16 q8, d16, d17" + - + asm_text: "vmull.s32 q8, d16, d17" + - + asm_text: "vmull.u8 q8, d16, d17" + - + asm_text: "vmull.u16 q8, d16, d17" + - + asm_text: "vmull.u32 q8, d16, d17" + - + asm_text: "vmull.p8 q8, d16, d17" + - + asm_text: "vqdmull.s16 q8, d16, d17" + - + asm_text: "vqdmull.s32 q8, d16, d17" + - + asm_text: "vmul.i16 d0, d0, d4[2]" + - + asm_text: "vmul.i16 d1, d1, d7[3]" + - + asm_text: "vmul.i16 d2, d2, d1[1]" + - + asm_text: "vmul.i32 d3, d3, d2[0]" + - + asm_text: "vmul.i32 d4, d4, d3[1]" + - + asm_text: "vmul.i32 d5, d5, d4[0]" + - + asm_text: "vmul.f32 d6, d6, d5[1]" + - + asm_text: "vmul.i16 q0, q0, d4[2]" + - + asm_text: "vmul.i16 q1, q1, d7[3]" + - + asm_text: "vmul.i16 q2, q2, d1[1]" + - + asm_text: "vmul.i32 q3, q3, d2[0]" + - + asm_text: "vmul.i32 q4, q4, d3[1]" + - + asm_text: "vmul.i32 q5, q5, d4[0]" + - + asm_text: "vmul.f32 q6, q6, d5[1]" + - + asm_text: "vmul.i16 d9, d0, d4[2]" + - + asm_text: "vmul.i16 d8, d1, d7[3]" + - + asm_text: "vmul.i16 d7, d2, d1[1]" + - + asm_text: "vmul.i32 d6, d3, d2[0]" + - + asm_text: "vmul.i32 d5, d4, d3[1]" + - + asm_text: "vmul.i32 d4, d5, d4[0]" + - + asm_text: "vmul.f32 d3, d6, d5[1]" + - + asm_text: "vmul.i16 q9, q0, d4[2]" + - + asm_text: "vmul.i16 q8, q1, d7[3]" + - + asm_text: "vmul.i16 q7, q2, d1[1]" + - + asm_text: "vmul.i32 q6, q3, d2[0]" + - + asm_text: "vmul.i32 q5, q4, d3[1]" + - + asm_text: "vmul.i32 q4, q5, d4[0]" + - + asm_text: "vmul.f32 q3, q6, d5[1]" diff --git a/tests/MC/ARM/neon-neg-encoding.s.yaml b/tests/MC/ARM/neon-neg-encoding.s.yaml new file mode 100644 index 0000000000..c80c070236 --- /dev/null +++ b/tests/MC/ARM/neon-neg-encoding.s.yaml @@ -0,0 +1,36 @@ +test_cases: + - + input: + bytes: [ 0xa0, 0x03, 0xf1, 0xf3, 0xa0, 0x03, 0xf5, 0xf3, 0xa0, 0x03, 0xf9, 0xf3, 0xa0, 0x07, 0xf9, 0xf3, 0xe0, 0x03, 0xf1, 0xf3, 0xe0, 0x03, 0xf5, 0xf3, 0xe0, 0x03, 0xf9, 0xf3, 0xe0, 0x07, 0xf9, 0xf3, 0xa0, 0x07, 0xf0, 0xf3, 0xa0, 0x07, 0xf4, 0xf3, 0xa0, 0x07, 0xf8, 0xf3, 0xe0, 0x07, 0xf0, 0xf3, 0xe0, 0x07, 0xf4, 0xf3, 0xe0, 0x07, 0xf8, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vneg.s8 d16, d16" + - + asm_text: "vneg.s16 d16, d16" + - + asm_text: "vneg.s32 d16, d16" + - + asm_text: "vneg.f32 d16, d16" + - + asm_text: "vneg.s8 q8, q8" + - + asm_text: "vneg.s16 q8, q8" + - + asm_text: "vneg.s32 q8, q8" + - + asm_text: "vneg.f32 q8, q8" + - + asm_text: "vqneg.s8 d16, d16" + - + asm_text: "vqneg.s16 d16, d16" + - + asm_text: "vqneg.s32 d16, d16" + - + asm_text: "vqneg.s8 q8, q8" + - + asm_text: "vqneg.s16 q8, q8" + - + asm_text: "vqneg.s32 q8, q8" diff --git a/tests/MC/ARM/neon-pairwise-encoding.s.yaml b/tests/MC/ARM/neon-pairwise-encoding.s.yaml new file mode 100644 index 0000000000..771b395039 --- /dev/null +++ b/tests/MC/ARM/neon-pairwise-encoding.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0xb0, 0x0b, 0x41, 0xf2, 0xb0, 0x0b, 0x51, 0xf2, 0xb0, 0x0b, 0x61, 0xf2, 0xa1, 0x0d, 0x40, 0xf3, 0xb0, 0x1b, 0x41, 0xf2, 0xb0, 0x1b, 0x51, 0xf2, 0xb0, 0x1b, 0x61, 0xf2, 0xa1, 0x0d, 0x40, 0xf3, 0x20, 0x02, 0xf0, 0xf3, 0x20, 0x02, 0xf4, 0xf3, 0x20, 0x02, 0xf8, 0xf3, 0xa0, 0x02, 0xf0, 0xf3, 0xa0, 0x02, 0xf4, 0xf3, 0xa0, 0x02, 0xf8, 0xf3, 0x60, 0x02, 0xf0, 0xf3, 0x60, 0x02, 0xf4, 0xf3, 0x60, 0x02, 0xf8, 0xf3, 0xe0, 0x02, 0xf0, 0xf3, 0xe0, 0x02, 0xf4, 0xf3, 0xe0, 0x02, 0xf8, 0xf3, 0x21, 0x06, 0xf0, 0xf3, 0x21, 0x06, 0xf4, 0xf3, 0x21, 0x06, 0xf8, 0xf3, 0xa1, 0x06, 0xf0, 0xf3, 0xa1, 0x06, 0xf4, 0xf3, 0xa1, 0x06, 0xf8, 0xf3, 0x60, 0x26, 0xf0, 0xf3, 0x60, 0x26, 0xf4, 0xf3, 0x60, 0x26, 0xf8, 0xf3, 0xe0, 0x26, 0xf0, 0xf3, 0xe0, 0x26, 0xf4, 0xf3, 0xe0, 0x26, 0xf8, 0xf3, 0xb1, 0x0a, 0x40, 0xf2, 0xb1, 0x0a, 0x50, 0xf2, 0xb1, 0x0a, 0x60, 0xf2, 0xb1, 0x0a, 0x40, 0xf3, 0xb1, 0x0a, 0x50, 0xf3, 0xb1, 0x0a, 0x60, 0xf3, 0xa1, 0x0f, 0x60, 0xf3, 0xa1, 0x0a, 0x40, 0xf2, 0xa1, 0x0a, 0x50, 0xf2, 0xa1, 0x0a, 0x60, 0xf2, 0xa1, 0x0a, 0x40, 0xf3, 0xa1, 0x0a, 0x50, 0xf3, 0xa1, 0x0a, 0x60, 0xf3, 0xa1, 0x0f, 0x40, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vpadd.i8 d16, d17, d16" + - + asm_text: "vpadd.i16 d16, d17, d16" + - + asm_text: "vpadd.i32 d16, d17, d16" + - + asm_text: "vpadd.f32 d16, d16, d17" + - + asm_text: "vpadd.i8 d17, d17, d16" + - + asm_text: "vpadd.i16 d17, d17, d16" + - + asm_text: "vpadd.i32 d17, d17, d16" + - + asm_text: "vpadd.f32 d16, d16, d17" + - + asm_text: "vpaddl.s8 d16, d16" + - + asm_text: "vpaddl.s16 d16, d16" + - + asm_text: "vpaddl.s32 d16, d16" + - + asm_text: "vpaddl.u8 d16, d16" + - + asm_text: "vpaddl.u16 d16, d16" + - + asm_text: "vpaddl.u32 d16, d16" + - + asm_text: "vpaddl.s8 q8, q8" + - + asm_text: "vpaddl.s16 q8, q8" + - + asm_text: "vpaddl.s32 q8, q8" + - + asm_text: "vpaddl.u8 q8, q8" + - + asm_text: "vpaddl.u16 q8, q8" + - + asm_text: "vpaddl.u32 q8, q8" + - + asm_text: "vpadal.s8 d16, d17" + - + asm_text: "vpadal.s16 d16, d17" + - + asm_text: "vpadal.s32 d16, d17" + - + asm_text: "vpadal.u8 d16, d17" + - + asm_text: "vpadal.u16 d16, d17" + - + asm_text: "vpadal.u32 d16, d17" + - + asm_text: "vpadal.s8 q9, q8" + - + asm_text: "vpadal.s16 q9, q8" + - + asm_text: "vpadal.s32 q9, q8" + - + asm_text: "vpadal.u8 q9, q8" + - + asm_text: "vpadal.u16 q9, q8" + - + asm_text: "vpadal.u32 q9, q8" + - + asm_text: "vpmin.s8 d16, d16, d17" + - + asm_text: "vpmin.s16 d16, d16, d17" + - + asm_text: "vpmin.s32 d16, d16, d17" + - + asm_text: "vpmin.u8 d16, d16, d17" + - + asm_text: "vpmin.u16 d16, d16, d17" + - + asm_text: "vpmin.u32 d16, d16, d17" + - + asm_text: "vpmin.f32 d16, d16, d17" + - + asm_text: "vpmax.s8 d16, d16, d17" + - + asm_text: "vpmax.s16 d16, d16, d17" + - + asm_text: "vpmax.s32 d16, d16, d17" + - + asm_text: "vpmax.u8 d16, d16, d17" + - + asm_text: "vpmax.u16 d16, d16, d17" + - + asm_text: "vpmax.u32 d16, d16, d17" + - + asm_text: "vpmax.f32 d16, d16, d17" diff --git a/tests/MC/ARM/neon-reciprocal-encoding.s.yaml b/tests/MC/ARM/neon-reciprocal-encoding.s.yaml new file mode 100644 index 0000000000..d83492b668 --- /dev/null +++ b/tests/MC/ARM/neon-reciprocal-encoding.s.yaml @@ -0,0 +1,32 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x04, 0xfb, 0xf3, 0x60, 0x04, 0xfb, 0xf3, 0x20, 0x05, 0xfb, 0xf3, 0x60, 0x05, 0xfb, 0xf3, 0xb1, 0x0f, 0x40, 0xf2, 0xf2, 0x0f, 0x40, 0xf2, 0xa0, 0x04, 0xfb, 0xf3, 0xe0, 0x04, 0xfb, 0xf3, 0xa0, 0x05, 0xfb, 0xf3, 0xe0, 0x05, 0xfb, 0xf3, 0xb1, 0x0f, 0x60, 0xf2, 0xf2, 0x0f, 0x60, 0xf2 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vrecpe.u32 d16, d16" + - + asm_text: "vrecpe.u32 q8, q8" + - + asm_text: "vrecpe.f32 d16, d16" + - + asm_text: "vrecpe.f32 q8, q8" + - + asm_text: "vrecps.f32 d16, d16, d17" + - + asm_text: "vrecps.f32 q8, q8, q9" + - + asm_text: "vrsqrte.u32 d16, d16" + - + asm_text: "vrsqrte.u32 q8, q8" + - + asm_text: "vrsqrte.f32 d16, d16" + - + asm_text: "vrsqrte.f32 q8, q8" + - + asm_text: "vrsqrts.f32 d16, d16, d17" + - + asm_text: "vrsqrts.f32 q8, q8, q9" diff --git a/tests/MC/ARM/neon-reverse-encoding.s.yaml b/tests/MC/ARM/neon-reverse-encoding.s.yaml new file mode 100644 index 0000000000..4493caae33 --- /dev/null +++ b/tests/MC/ARM/neon-reverse-encoding.s.yaml @@ -0,0 +1,32 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x00, 0xf0, 0xf3, 0x20, 0x00, 0xf4, 0xf3, 0x20, 0x00, 0xf8, 0xf3, 0x60, 0x00, 0xf0, 0xf3, 0x60, 0x00, 0xf4, 0xf3, 0x60, 0x00, 0xf8, 0xf3, 0xa0, 0x00, 0xf0, 0xf3, 0xa0, 0x00, 0xf4, 0xf3, 0xe0, 0x00, 0xf0, 0xf3, 0xe0, 0x00, 0xf4, 0xf3, 0x20, 0x01, 0xf0, 0xf3, 0x60, 0x01, 0xf0, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vrev64.8 d16, d16" + - + asm_text: "vrev64.16 d16, d16" + - + asm_text: "vrev64.32 d16, d16" + - + asm_text: "vrev64.8 q8, q8" + - + asm_text: "vrev64.16 q8, q8" + - + asm_text: "vrev64.32 q8, q8" + - + asm_text: "vrev32.8 d16, d16" + - + asm_text: "vrev32.16 d16, d16" + - + asm_text: "vrev32.8 q8, q8" + - + asm_text: "vrev32.16 q8, q8" + - + asm_text: "vrev16.8 d16, d16" + - + asm_text: "vrev16.8 q8, q8" diff --git a/tests/MC/ARM/neon-satshift-encoding.s.yaml b/tests/MC/ARM/neon-satshift-encoding.s.yaml new file mode 100644 index 0000000000..36148b71e5 --- /dev/null +++ b/tests/MC/ARM/neon-satshift-encoding.s.yaml @@ -0,0 +1,156 @@ +test_cases: + - + input: + bytes: [ 0xb0, 0x04, 0x41, 0xf2, 0xb0, 0x04, 0x51, 0xf2, 0xb0, 0x04, 0x61, 0xf2, 0xb0, 0x04, 0x71, 0xf2, 0xb0, 0x04, 0x41, 0xf3, 0xb0, 0x04, 0x51, 0xf3, 0xb0, 0x04, 0x61, 0xf3, 0xb0, 0x04, 0x71, 0xf3, 0xf0, 0x04, 0x42, 0xf2, 0xf0, 0x04, 0x52, 0xf2, 0xf0, 0x04, 0x62, 0xf2, 0xf0, 0x04, 0x72, 0xf2, 0xf0, 0x04, 0x42, 0xf3, 0xf0, 0x04, 0x52, 0xf3, 0xf0, 0x04, 0x62, 0xf3, 0xf0, 0x04, 0x72, 0xf3, 0x30, 0x07, 0xcf, 0xf2, 0x30, 0x07, 0xdf, 0xf2, 0x30, 0x07, 0xff, 0xf2, 0xb0, 0x07, 0xff, 0xf2, 0x30, 0x07, 0xcf, 0xf3, 0x30, 0x07, 0xdf, 0xf3, 0x30, 0x07, 0xff, 0xf3, 0xb0, 0x07, 0xff, 0xf3, 0x30, 0x06, 0xcf, 0xf3, 0x30, 0x06, 0xdf, 0xf3, 0x30, 0x06, 0xff, 0xf3, 0xb0, 0x06, 0xff, 0xf3, 0x70, 0x07, 0xcf, 0xf2, 0x70, 0x07, 0xdf, 0xf2, 0x70, 0x07, 0xff, 0xf2, 0xf0, 0x07, 0xff, 0xf2, 0x70, 0x07, 0xcf, 0xf3, 0x70, 0x07, 0xdf, 0xf3, 0x70, 0x07, 0xff, 0xf3, 0xf0, 0x07, 0xff, 0xf3, 0x70, 0x06, 0xcf, 0xf3, 0x70, 0x06, 0xdf, 0xf3, 0x70, 0x06, 0xff, 0xf3, 0xf0, 0x06, 0xff, 0xf3, 0xb0, 0x05, 0x41, 0xf2, 0xb0, 0x05, 0x51, 0xf2, 0xb0, 0x05, 0x61, 0xf2, 0xb0, 0x05, 0x71, 0xf2, 0xb0, 0x05, 0x41, 0xf3, 0xb0, 0x05, 0x51, 0xf3, 0xb0, 0x05, 0x61, 0xf3, 0xb0, 0x05, 0x71, 0xf3, 0xf0, 0x05, 0x42, 0xf2, 0xf0, 0x05, 0x52, 0xf2, 0xf0, 0x05, 0x62, 0xf2, 0xf0, 0x05, 0x72, 0xf2, 0xf0, 0x05, 0x42, 0xf3, 0xf0, 0x05, 0x52, 0xf3, 0xf0, 0x05, 0x62, 0xf3, 0xf0, 0x05, 0x72, 0xf3, 0x30, 0x09, 0xc8, 0xf2, 0x30, 0x09, 0xd0, 0xf2, 0x30, 0x09, 0xe0, 0xf2, 0x30, 0x09, 0xc8, 0xf3, 0x30, 0x09, 0xd0, 0xf3, 0x30, 0x09, 0xe0, 0xf3, 0x30, 0x08, 0xc8, 0xf3, 0x30, 0x08, 0xd0, 0xf3, 0x30, 0x08, 0xe0, 0xf3, 0x70, 0x09, 0xc8, 0xf2, 0x70, 0x09, 0xd0, 0xf2, 0x70, 0x09, 0xe0, 0xf2, 0x70, 0x09, 0xc8, 0xf3, 0x70, 0x09, 0xd0, 0xf3, 0x70, 0x09, 0xe0, 0xf3, 0x70, 0x08, 0xc8, 0xf3, 0x70, 0x08, 0xd0, 0xf3, 0x70, 0x08, 0xe0, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vqshl.s8 d16, d16, d17" + - + asm_text: "vqshl.s16 d16, d16, d17" + - + asm_text: "vqshl.s32 d16, d16, d17" + - + asm_text: "vqshl.s64 d16, d16, d17" + - + asm_text: "vqshl.u8 d16, d16, d17" + - + asm_text: "vqshl.u16 d16, d16, d17" + - + asm_text: "vqshl.u32 d16, d16, d17" + - + asm_text: "vqshl.u64 d16, d16, d17" + - + asm_text: "vqshl.s8 q8, q8, q9" + - + asm_text: "vqshl.s16 q8, q8, q9" + - + asm_text: "vqshl.s32 q8, q8, q9" + - + asm_text: "vqshl.s64 q8, q8, q9" + - + asm_text: "vqshl.u8 q8, q8, q9" + - + asm_text: "vqshl.u16 q8, q8, q9" + - + asm_text: "vqshl.u32 q8, q8, q9" + - + asm_text: "vqshl.u64 q8, q8, q9" + - + asm_text: "vqshl.s8 d16, d16, #7" + - + asm_text: "vqshl.s16 d16, d16, #0xf" + - + asm_text: "vqshl.s32 d16, d16, #0x1f" + - + asm_text: "vqshl.s64 d16, d16, #0x3f" + - + asm_text: "vqshl.u8 d16, d16, #7" + - + asm_text: "vqshl.u16 d16, d16, #0xf" + - + asm_text: "vqshl.u32 d16, d16, #0x1f" + - + asm_text: "vqshl.u64 d16, d16, #0x3f" + - + asm_text: "vqshlu.s8 d16, d16, #7" + - + asm_text: "vqshlu.s16 d16, d16, #0xf" + - + asm_text: "vqshlu.s32 d16, d16, #0x1f" + - + asm_text: "vqshlu.s64 d16, d16, #0x3f" + - + asm_text: "vqshl.s8 q8, q8, #7" + - + asm_text: "vqshl.s16 q8, q8, #0xf" + - + asm_text: "vqshl.s32 q8, q8, #0x1f" + - + asm_text: "vqshl.s64 q8, q8, #0x3f" + - + asm_text: "vqshl.u8 q8, q8, #7" + - + asm_text: "vqshl.u16 q8, q8, #0xf" + - + asm_text: "vqshl.u32 q8, q8, #0x1f" + - + asm_text: "vqshl.u64 q8, q8, #0x3f" + - + asm_text: "vqshlu.s8 q8, q8, #7" + - + asm_text: "vqshlu.s16 q8, q8, #0xf" + - + asm_text: "vqshlu.s32 q8, q8, #0x1f" + - + asm_text: "vqshlu.s64 q8, q8, #0x3f" + - + asm_text: "vqrshl.s8 d16, d16, d17" + - + asm_text: "vqrshl.s16 d16, d16, d17" + - + asm_text: "vqrshl.s32 d16, d16, d17" + - + asm_text: "vqrshl.s64 d16, d16, d17" + - + asm_text: "vqrshl.u8 d16, d16, d17" + - + asm_text: "vqrshl.u16 d16, d16, d17" + - + asm_text: "vqrshl.u32 d16, d16, d17" + - + asm_text: "vqrshl.u64 d16, d16, d17" + - + asm_text: "vqrshl.s8 q8, q8, q9" + - + asm_text: "vqrshl.s16 q8, q8, q9" + - + asm_text: "vqrshl.s32 q8, q8, q9" + - + asm_text: "vqrshl.s64 q8, q8, q9" + - + asm_text: "vqrshl.u8 q8, q8, q9" + - + asm_text: "vqrshl.u16 q8, q8, q9" + - + asm_text: "vqrshl.u32 q8, q8, q9" + - + asm_text: "vqrshl.u64 q8, q8, q9" + - + asm_text: "vqshrn.s16 d16, q8, #8" + - + asm_text: "vqshrn.s32 d16, q8, #0x10" + - + asm_text: "vqshrn.s64 d16, q8, #0x20" + - + asm_text: "vqshrn.u16 d16, q8, #8" + - + asm_text: "vqshrn.u32 d16, q8, #0x10" + - + asm_text: "vqshrn.u64 d16, q8, #0x20" + - + asm_text: "vqshrun.s16 d16, q8, #8" + - + asm_text: "vqshrun.s32 d16, q8, #0x10" + - + asm_text: "vqshrun.s64 d16, q8, #0x20" + - + asm_text: "vqrshrn.s16 d16, q8, #8" + - + asm_text: "vqrshrn.s32 d16, q8, #0x10" + - + asm_text: "vqrshrn.s64 d16, q8, #0x20" + - + asm_text: "vqrshrn.u16 d16, q8, #8" + - + asm_text: "vqrshrn.u32 d16, q8, #0x10" + - + asm_text: "vqrshrn.u64 d16, q8, #0x20" + - + asm_text: "vqrshrun.s16 d16, q8, #8" + - + asm_text: "vqrshrun.s32 d16, q8, #0x10" + - + asm_text: "vqrshrun.s64 d16, q8, #0x20" diff --git a/tests/MC/ARM/neon-shift-encoding.s.yaml b/tests/MC/ARM/neon-shift-encoding.s.yaml new file mode 100644 index 0000000000..4296dbd95c --- /dev/null +++ b/tests/MC/ARM/neon-shift-encoding.s.yaml @@ -0,0 +1,482 @@ +test_cases: + - + input: + bytes: [ 0xa1, 0x04, 0x40, 0xf3, 0xa1, 0x04, 0x50, 0xf3, 0xa1, 0x04, 0x60, 0xf3, 0xa1, 0x04, 0x70, 0xf3, 0x30, 0x05, 0xcf, 0xf2, 0x30, 0x05, 0xdf, 0xf2, 0x30, 0x05, 0xff, 0xf2, 0xb0, 0x05, 0xff, 0xf2, 0xe2, 0x04, 0x40, 0xf3, 0xe2, 0x04, 0x50, 0xf3, 0xe2, 0x04, 0x60, 0xf3, 0xe2, 0x04, 0x70, 0xf3, 0x70, 0x05, 0xcf, 0xf2, 0x70, 0x05, 0xdf, 0xf2, 0x70, 0x05, 0xff, 0xf2, 0xf0, 0x05, 0xff, 0xf2, 0x30, 0x00, 0xc9, 0xf3, 0x30, 0x00, 0xd1, 0xf3, 0x30, 0x00, 0xe1, 0xf3, 0xb0, 0x00, 0xc1, 0xf3, 0x70, 0x00, 0xc9, 0xf3, 0x70, 0x00, 0xd1, 0xf3, 0x70, 0x00, 0xe1, 0xf3, 0xf0, 0x00, 0xc1, 0xf3, 0x30, 0x00, 0xc9, 0xf2, 0x30, 0x00, 0xd1, 0xf2, 0x30, 0x00, 0xe1, 0xf2, 0xb0, 0x00, 0xc1, 0xf2, 0x70, 0x00, 0xc9, 0xf2, 0x70, 0x00, 0xd1, 0xf2, 0x70, 0x00, 0xe1, 0xf2, 0xf0, 0x00, 0xc1, 0xf2, 0x30, 0x00, 0xc9, 0xf3, 0x30, 0x00, 0xd1, 0xf3, 0x30, 0x00, 0xe1, 0xf3, 0xb0, 0x00, 0xc1, 0xf3, 0x70, 0x00, 0xc9, 0xf3, 0x70, 0x00, 0xd1, 0xf3, 0x70, 0x00, 0xe1, 0xf3, 0xf0, 0x00, 0xc1, 0xf3, 0x30, 0x00, 0xc9, 0xf2, 0x30, 0x00, 0xd1, 0xf2, 0x30, 0x00, 0xe1, 0xf2, 0xb0, 0x00, 0xc1, 0xf2, 0x70, 0x00, 0xc9, 0xf2, 0x70, 0x00, 0xd1, 0xf2, 0x70, 0x00, 0xe1, 0xf2, 0xf0, 0x00, 0xc1, 0xf2, 0x16, 0x01, 0xc9, 0xf2, 0x32, 0xa1, 0xd1, 0xf2, 0x1a, 0xb1, 0xa1, 0xf2, 0xb3, 0xc1, 0x81, 0xf2, 0x70, 0x21, 0x89, 0xf2, 0x5e, 0x41, 0x91, 0xf2, 0x5c, 0x61, 0xa1, 0xf2, 0xda, 0x81, 0x81, 0xf2, 0x30, 0x01, 0xc9, 0xf2, 0x1f, 0xf1, 0x91, 0xf2, 0x1e, 0xe1, 0xa1, 0xf2, 0x9d, 0xd1, 0x81, 0xf2, 0x58, 0x81, 0x89, 0xf2, 0x5a, 0xa1, 0x91, 0xf2, 0x5c, 0xc1, 0xa1, 0xf2, 0xde, 0xe1, 0x81, 0xf2, 0x16, 0x01, 0xc9, 0xf3, 0x32, 0xa1, 0xd1, 0xf3, 0x1a, 0xb1, 0xa1, 0xf3, 0xb3, 0xc1, 0x81, 0xf3, 0x70, 0x21, 0x89, 0xf3, 0x5e, 0x41, 0x91, 0xf3, 0x5c, 0x61, 0xa1, 0xf3, 0xda, 0x81, 0x81, 0xf3, 0x30, 0x01, 0xc9, 0xf3, 0x1f, 0xf1, 0x91, 0xf3, 0x1e, 0xe1, 0xa1, 0xf3, 0x9d, 0xd1, 0x81, 0xf3, 0x58, 0x81, 0x89, 0xf3, 0x5a, 0xa1, 0x91, 0xf3, 0x5c, 0xc1, 0xa1, 0xf3, 0xde, 0xe1, 0x81, 0xf3, 0x16, 0x04, 0xc9, 0xf3, 0x32, 0xa4, 0xd1, 0xf3, 0x1a, 0xb4, 0xa1, 0xf3, 0xb3, 0xc4, 0x81, 0xf3, 0x70, 0x24, 0x89, 0xf3, 0x5e, 0x44, 0x91, 0xf3, 0x5c, 0x64, 0xa1, 0xf3, 0xda, 0x84, 0x81, 0xf3, 0x30, 0x04, 0xc9, 0xf3, 0x1f, 0xf4, 0x91, 0xf3, 0x1e, 0xe4, 0xa1, 0xf3, 0x9d, 0xd4, 0x81, 0xf3, 0x58, 0x84, 0x89, 0xf3, 0x5a, 0xa4, 0x91, 0xf3, 0x5c, 0xc4, 0xa1, 0xf3, 0xde, 0xe4, 0x81, 0xf3, 0x16, 0x05, 0xcf, 0xf3, 0x32, 0xa5, 0xdf, 0xf3, 0x1a, 0xb5, 0xbf, 0xf3, 0xb3, 0xc5, 0xbf, 0xf3, 0x70, 0x25, 0x8f, 0xf3, 0x5e, 0x45, 0x9f, 0xf3, 0x5c, 0x65, 0xbf, 0xf3, 0xda, 0x85, 0xbf, 0xf3, 0x30, 0x05, 0xcf, 0xf3, 0x1f, 0xf5, 0x9f, 0xf3, 0x1e, 0xe5, 0xbf, 0xf3, 0x9d, 0xd5, 0xbf, 0xf3, 0x58, 0x85, 0x8f, 0xf3, 0x5a, 0xa5, 0x9f, 0xf3, 0x5c, 0xc5, 0xbf, 0xf3, 0xde, 0xe5, 0xbf, 0xf3, 0x30, 0x0a, 0xcf, 0xf2, 0x30, 0x0a, 0xdf, 0xf2, 0x30, 0x0a, 0xff, 0xf2, 0x30, 0x0a, 0xcf, 0xf3, 0x30, 0x0a, 0xdf, 0xf3, 0x30, 0x0a, 0xff, 0xf3, 0x20, 0x03, 0xf2, 0xf3, 0x20, 0x03, 0xf6, 0xf3, 0x20, 0x03, 0xfa, 0xf3, 0x30, 0x08, 0xc8, 0xf2, 0x30, 0x08, 0xd0, 0xf2, 0x30, 0x08, 0xe0, 0xf2, 0xa1, 0x05, 0x40, 0xf2, 0xa1, 0x05, 0x50, 0xf2, 0xa1, 0x05, 0x60, 0xf2, 0xa1, 0x05, 0x70, 0xf2, 0xa1, 0x05, 0x40, 0xf3, 0xa1, 0x05, 0x50, 0xf3, 0xa1, 0x05, 0x60, 0xf3, 0xa1, 0x05, 0x70, 0xf3, 0xe2, 0x05, 0x40, 0xf2, 0xe2, 0x05, 0x50, 0xf2, 0xe2, 0x05, 0x60, 0xf2, 0xe2, 0x05, 0x70, 0xf2, 0xe2, 0x05, 0x40, 0xf3, 0xe2, 0x05, 0x50, 0xf3, 0xe2, 0x05, 0x60, 0xf3, 0xe2, 0x05, 0x70, 0xf3, 0x30, 0x02, 0xc8, 0xf2, 0x30, 0x02, 0xd0, 0xf2, 0x30, 0x02, 0xe0, 0xf2, 0xb0, 0x02, 0xc0, 0xf2, 0x30, 0x02, 0xc8, 0xf3, 0x30, 0x02, 0xd0, 0xf3, 0x30, 0x02, 0xe0, 0xf3, 0xb0, 0x02, 0xc0, 0xf3, 0x70, 0x02, 0xc8, 0xf2, 0x70, 0x02, 0xd0, 0xf2, 0x70, 0x02, 0xe0, 0xf2, 0xf0, 0x02, 0xc0, 0xf2, 0x70, 0x02, 0xc8, 0xf3, 0x70, 0x02, 0xd0, 0xf3, 0x70, 0x02, 0xe0, 0xf3, 0xf0, 0x02, 0xc0, 0xf3, 0x70, 0x08, 0xc8, 0xf2, 0x70, 0x08, 0xd0, 0xf2, 0x70, 0x08, 0xe0, 0xf2, 0x70, 0x09, 0xcc, 0xf2, 0x70, 0x09, 0xd3, 0xf2, 0x70, 0x09, 0xf3, 0xf2, 0x70, 0x09, 0xcc, 0xf3, 0x70, 0x09, 0xd3, 0xf3, 0x70, 0x09, 0xf3, 0xf3, 0x48, 0x84, 0x0a, 0xf2, 0x48, 0x84, 0x1a, 0xf2, 0x48, 0x84, 0x2a, 0xf2, 0x48, 0x84, 0x3a, 0xf2, 0x48, 0x84, 0x0a, 0xf3, 0x48, 0x84, 0x1a, 0xf3, 0x48, 0x84, 0x2a, 0xf3, 0x48, 0x84, 0x3a, 0xf3, 0x04, 0x44, 0x05, 0xf2, 0x04, 0x44, 0x15, 0xf2, 0x04, 0x44, 0x25, 0xf2, 0x04, 0x44, 0x35, 0xf2, 0x04, 0x44, 0x05, 0xf3, 0x04, 0x44, 0x15, 0xf3, 0x04, 0x44, 0x25, 0xf3, 0x04, 0x44, 0x35, 0xf3, 0x58, 0x85, 0x8a, 0xf2, 0x58, 0x85, 0x9e, 0xf2, 0x58, 0x85, 0xbb, 0xf2, 0xd8, 0x85, 0xa3, 0xf2, 0x14, 0x45, 0x8e, 0xf2, 0x14, 0x45, 0x9a, 0xf2, 0x14, 0x45, 0xb1, 0xf2, 0x94, 0x45, 0xab, 0xf2, 0x0b, 0xb5, 0x04, 0xf2, 0x0c, 0xc5, 0x15, 0xf2, 0x0d, 0xd5, 0x26, 0xf2, 0x0e, 0xe5, 0x37, 0xf2, 0x0f, 0xf5, 0x08, 0xf3, 0x20, 0x05, 0x59, 0xf3, 0x21, 0x15, 0x6a, 0xf3, 0x22, 0x25, 0x7b, 0xf3, 0xc2, 0x25, 0x00, 0xf2, 0xc4, 0x45, 0x1e, 0xf2, 0xc6, 0x65, 0x2c, 0xf2, 0xc8, 0x85, 0x3a, 0xf2, 0xca, 0xa5, 0x08, 0xf3, 0xcc, 0xc5, 0x16, 0xf3, 0xce, 0xe5, 0x24, 0xf3, 0xe0, 0x05, 0x72, 0xf3, 0x1f, 0xf0, 0x88, 0xf2, 0x1c, 0xc0, 0x90, 0xf2, 0x1d, 0xd0, 0xa0, 0xf2, 0x9e, 0xe0, 0x80, 0xf2, 0x30, 0x00, 0xc8, 0xf3, 0x31, 0x10, 0xd0, 0xf3, 0x16, 0x60, 0xa0, 0xf3, 0x9a, 0xa0, 0x80, 0xf3, 0x52, 0x20, 0x88, 0xf2, 0x54, 0x40, 0x90, 0xf2, 0x56, 0x60, 0xa0, 0xf2, 0xd8, 0x80, 0x80, 0xf2, 0x5a, 0xa0, 0x88, 0xf3, 0x5c, 0xc0, 0x90, 0xf3, 0x5e, 0xe0, 0xa0, 0xf3, 0xf0, 0x00, 0xc0, 0xf3, 0x1f, 0xf2, 0x88, 0xf2, 0x1c, 0xc2, 0x90, 0xf2, 0x1d, 0xd2, 0xa0, 0xf2, 0x9e, 0xe2, 0x80, 0xf2, 0x30, 0x02, 0xc8, 0xf3, 0x31, 0x12, 0xd0, 0xf3, 0x16, 0x62, 0xa0, 0xf3, 0x9a, 0xa2, 0x80, 0xf3, 0x52, 0x22, 0x88, 0xf2, 0x54, 0x42, 0x90, 0xf2, 0x56, 0x62, 0xa0, 0xf2, 0xd8, 0x82, 0x80, 0xf2, 0x5a, 0xa2, 0x88, 0xf3, 0x5c, 0xc2, 0x90, 0xf3, 0x5e, 0xe2, 0xa0, 0xf3, 0xf0, 0x02, 0xc0, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vshl.u8 d16, d17, d16" + - + asm_text: "vshl.u16 d16, d17, d16" + - + asm_text: "vshl.u32 d16, d17, d16" + - + asm_text: "vshl.u64 d16, d17, d16" + - + asm_text: "vshl.i8 d16, d16, #7" + - + asm_text: "vshl.i16 d16, d16, #0xf" + - + asm_text: "vshl.i32 d16, d16, #0x1f" + - + asm_text: "vshl.i64 d16, d16, #0x3f" + - + asm_text: "vshl.u8 q8, q9, q8" + - + asm_text: "vshl.u16 q8, q9, q8" + - + asm_text: "vshl.u32 q8, q9, q8" + - + asm_text: "vshl.u64 q8, q9, q8" + - + asm_text: "vshl.i8 q8, q8, #7" + - + asm_text: "vshl.i16 q8, q8, #0xf" + - + asm_text: "vshl.i32 q8, q8, #0x1f" + - + asm_text: "vshl.i64 q8, q8, #0x3f" + - + asm_text: "vshr.u8 d16, d16, #7" + - + asm_text: "vshr.u16 d16, d16, #0xf" + - + asm_text: "vshr.u32 d16, d16, #0x1f" + - + asm_text: "vshr.u64 d16, d16, #0x3f" + - + asm_text: "vshr.u8 q8, q8, #7" + - + asm_text: "vshr.u16 q8, q8, #0xf" + - + asm_text: "vshr.u32 q8, q8, #0x1f" + - + asm_text: "vshr.u64 q8, q8, #0x3f" + - + asm_text: "vshr.s8 d16, d16, #7" + - + asm_text: "vshr.s16 d16, d16, #0xf" + - + asm_text: "vshr.s32 d16, d16, #0x1f" + - + asm_text: "vshr.s64 d16, d16, #0x3f" + - + asm_text: "vshr.s8 q8, q8, #7" + - + asm_text: "vshr.s16 q8, q8, #0xf" + - + asm_text: "vshr.s32 q8, q8, #0x1f" + - + asm_text: "vshr.s64 q8, q8, #0x3f" + - + asm_text: "vshr.u8 d16, d16, #7" + - + asm_text: "vshr.u16 d16, d16, #0xf" + - + asm_text: "vshr.u32 d16, d16, #0x1f" + - + asm_text: "vshr.u64 d16, d16, #0x3f" + - + asm_text: "vshr.u8 q8, q8, #7" + - + asm_text: "vshr.u16 q8, q8, #0xf" + - + asm_text: "vshr.u32 q8, q8, #0x1f" + - + asm_text: "vshr.u64 q8, q8, #0x3f" + - + asm_text: "vshr.s8 d16, d16, #7" + - + asm_text: "vshr.s16 d16, d16, #0xf" + - + asm_text: "vshr.s32 d16, d16, #0x1f" + - + asm_text: "vshr.s64 d16, d16, #0x3f" + - + asm_text: "vshr.s8 q8, q8, #7" + - + asm_text: "vshr.s16 q8, q8, #0xf" + - + asm_text: "vshr.s32 q8, q8, #0x1f" + - + asm_text: "vshr.s64 q8, q8, #0x3f" + - + asm_text: "vsra.s8 d16, d6, #7" + - + asm_text: "vsra.s16 d26, d18, #0xf" + - + asm_text: "vsra.s32 d11, d10, #0x1f" + - + asm_text: "vsra.s64 d12, d19, #0x3f" + - + asm_text: "vsra.s8 q1, q8, #7" + - + asm_text: "vsra.s16 q2, q7, #0xf" + - + asm_text: "vsra.s32 q3, q6, #0x1f" + - + asm_text: "vsra.s64 q4, q5, #0x3f" + - + asm_text: "vsra.s8 d16, d16, #7" + - + asm_text: "vsra.s16 d15, d15, #0xf" + - + asm_text: "vsra.s32 d14, d14, #0x1f" + - + asm_text: "vsra.s64 d13, d13, #0x3f" + - + asm_text: "vsra.s8 q4, q4, #7" + - + asm_text: "vsra.s16 q5, q5, #0xf" + - + asm_text: "vsra.s32 q6, q6, #0x1f" + - + asm_text: "vsra.s64 q7, q7, #0x3f" + - + asm_text: "vsra.u8 d16, d6, #7" + - + asm_text: "vsra.u16 d26, d18, #0xf" + - + asm_text: "vsra.u32 d11, d10, #0x1f" + - + asm_text: "vsra.u64 d12, d19, #0x3f" + - + asm_text: "vsra.u8 q1, q8, #7" + - + asm_text: "vsra.u16 q2, q7, #0xf" + - + asm_text: "vsra.u32 q3, q6, #0x1f" + - + asm_text: "vsra.u64 q4, q5, #0x3f" + - + asm_text: "vsra.u8 d16, d16, #7" + - + asm_text: "vsra.u16 d15, d15, #0xf" + - + asm_text: "vsra.u32 d14, d14, #0x1f" + - + asm_text: "vsra.u64 d13, d13, #0x3f" + - + asm_text: "vsra.u8 q4, q4, #7" + - + asm_text: "vsra.u16 q5, q5, #0xf" + - + asm_text: "vsra.u32 q6, q6, #0x1f" + - + asm_text: "vsra.u64 q7, q7, #0x3f" + - + asm_text: "vsri.8 d16, d6, #7" + - + asm_text: "vsri.16 d26, d18, #0xf" + - + asm_text: "vsri.32 d11, d10, #0x1f" + - + asm_text: "vsri.64 d12, d19, #0x3f" + - + asm_text: "vsri.8 q1, q8, #7" + - + asm_text: "vsri.16 q2, q7, #0xf" + - + asm_text: "vsri.32 q3, q6, #0x1f" + - + asm_text: "vsri.64 q4, q5, #0x3f" + - + asm_text: "vsri.8 d16, d16, #7" + - + asm_text: "vsri.16 d15, d15, #0xf" + - + asm_text: "vsri.32 d14, d14, #0x1f" + - + asm_text: "vsri.64 d13, d13, #0x3f" + - + asm_text: "vsri.8 q4, q4, #7" + - + asm_text: "vsri.16 q5, q5, #0xf" + - + asm_text: "vsri.32 q6, q6, #0x1f" + - + asm_text: "vsri.64 q7, q7, #0x3f" + - + asm_text: "vsli.8 d16, d6, #7" + - + asm_text: "vsli.16 d26, d18, #0xf" + - + asm_text: "vsli.32 d11, d10, #0x1f" + - + asm_text: "vsli.64 d12, d19, #0x3f" + - + asm_text: "vsli.8 q1, q8, #7" + - + asm_text: "vsli.16 q2, q7, #0xf" + - + asm_text: "vsli.32 q3, q6, #0x1f" + - + asm_text: "vsli.64 q4, q5, #0x3f" + - + asm_text: "vsli.8 d16, d16, #7" + - + asm_text: "vsli.16 d15, d15, #0xf" + - + asm_text: "vsli.32 d14, d14, #0x1f" + - + asm_text: "vsli.64 d13, d13, #0x3f" + - + asm_text: "vsli.8 q4, q4, #7" + - + asm_text: "vsli.16 q5, q5, #0xf" + - + asm_text: "vsli.32 q6, q6, #0x1f" + - + asm_text: "vsli.64 q7, q7, #0x3f" + - + asm_text: "vshll.s8 q8, d16, #7" + - + asm_text: "vshll.s16 q8, d16, #0xf" + - + asm_text: "vshll.s32 q8, d16, #0x1f" + - + asm_text: "vshll.u8 q8, d16, #7" + - + asm_text: "vshll.u16 q8, d16, #0xf" + - + asm_text: "vshll.u32 q8, d16, #0x1f" + - + asm_text: "vshll.i8 q8, d16, #8" + - + asm_text: "vshll.i16 q8, d16, #0x10" + - + asm_text: "vshll.i32 q8, d16, #0x20" + - + asm_text: "vshrn.i16 d16, q8, #8" + - + asm_text: "vshrn.i32 d16, q8, #0x10" + - + asm_text: "vshrn.i64 d16, q8, #0x20" + - + asm_text: "vrshl.s8 d16, d17, d16" + - + asm_text: "vrshl.s16 d16, d17, d16" + - + asm_text: "vrshl.s32 d16, d17, d16" + - + asm_text: "vrshl.s64 d16, d17, d16" + - + asm_text: "vrshl.u8 d16, d17, d16" + - + asm_text: "vrshl.u16 d16, d17, d16" + - + asm_text: "vrshl.u32 d16, d17, d16" + - + asm_text: "vrshl.u64 d16, d17, d16" + - + asm_text: "vrshl.s8 q8, q9, q8" + - + asm_text: "vrshl.s16 q8, q9, q8" + - + asm_text: "vrshl.s32 q8, q9, q8" + - + asm_text: "vrshl.s64 q8, q9, q8" + - + asm_text: "vrshl.u8 q8, q9, q8" + - + asm_text: "vrshl.u16 q8, q9, q8" + - + asm_text: "vrshl.u32 q8, q9, q8" + - + asm_text: "vrshl.u64 q8, q9, q8" + - + asm_text: "vrshr.s8 d16, d16, #8" + - + asm_text: "vrshr.s16 d16, d16, #0x10" + - + asm_text: "vrshr.s32 d16, d16, #0x20" + - + asm_text: "vrshr.s64 d16, d16, #0x40" + - + asm_text: "vrshr.u8 d16, d16, #8" + - + asm_text: "vrshr.u16 d16, d16, #0x10" + - + asm_text: "vrshr.u32 d16, d16, #0x20" + - + asm_text: "vrshr.u64 d16, d16, #0x40" + - + asm_text: "vrshr.s8 q8, q8, #8" + - + asm_text: "vrshr.s16 q8, q8, #0x10" + - + asm_text: "vrshr.s32 q8, q8, #0x20" + - + asm_text: "vrshr.s64 q8, q8, #0x40" + - + asm_text: "vrshr.u8 q8, q8, #8" + - + asm_text: "vrshr.u16 q8, q8, #0x10" + - + asm_text: "vrshr.u32 q8, q8, #0x20" + - + asm_text: "vrshr.u64 q8, q8, #0x40" + - + asm_text: "vrshrn.i16 d16, q8, #8" + - + asm_text: "vrshrn.i32 d16, q8, #0x10" + - + asm_text: "vrshrn.i64 d16, q8, #0x20" + - + asm_text: "vqrshrn.s16 d16, q8, #4" + - + asm_text: "vqrshrn.s32 d16, q8, #0xd" + - + asm_text: "vqrshrn.s64 d16, q8, #0xd" + - + asm_text: "vqrshrn.u16 d16, q8, #4" + - + asm_text: "vqrshrn.u32 d16, q8, #0xd" + - + asm_text: "vqrshrn.u64 d16, q8, #0xd" + - + asm_text: "vshl.s8 q4, q4, q5" + - + asm_text: "vshl.s16 q4, q4, q5" + - + asm_text: "vshl.s32 q4, q4, q5" + - + asm_text: "vshl.s64 q4, q4, q5" + - + asm_text: "vshl.u8 q4, q4, q5" + - + asm_text: "vshl.u16 q4, q4, q5" + - + asm_text: "vshl.u32 q4, q4, q5" + - + asm_text: "vshl.u64 q4, q4, q5" + - + asm_text: "vshl.s8 d4, d4, d5" + - + asm_text: "vshl.s16 d4, d4, d5" + - + asm_text: "vshl.s32 d4, d4, d5" + - + asm_text: "vshl.s64 d4, d4, d5" + - + asm_text: "vshl.u8 d4, d4, d5" + - + asm_text: "vshl.u16 d4, d4, d5" + - + asm_text: "vshl.u32 d4, d4, d5" + - + asm_text: "vshl.u64 d4, d4, d5" + - + asm_text: "vshl.i8 q4, q4, #2" + - + asm_text: "vshl.i16 q4, q4, #0xe" + - + asm_text: "vshl.i32 q4, q4, #0x1b" + - + asm_text: "vshl.i64 q4, q4, #0x23" + - + asm_text: "vshl.i8 d4, d4, #6" + - + asm_text: "vshl.i16 d4, d4, #0xa" + - + asm_text: "vshl.i32 d4, d4, #0x11" + - + asm_text: "vshl.i64 d4, d4, #0x2b" + - + asm_text: "vrshl.s8 d11, d11, d4" + - + asm_text: "vrshl.s16 d12, d12, d5" + - + asm_text: "vrshl.s32 d13, d13, d6" + - + asm_text: "vrshl.s64 d14, d14, d7" + - + asm_text: "vrshl.u8 d15, d15, d8" + - + asm_text: "vrshl.u16 d16, d16, d9" + - + asm_text: "vrshl.u32 d17, d17, d10" + - + asm_text: "vrshl.u64 d18, d18, d11" + - + asm_text: "vrshl.s8 q1, q1, q8" + - + asm_text: "vrshl.s16 q2, q2, q15" + - + asm_text: "vrshl.s32 q3, q3, q14" + - + asm_text: "vrshl.s64 q4, q4, q13" + - + asm_text: "vrshl.u8 q5, q5, q12" + - + asm_text: "vrshl.u16 q6, q6, q11" + - + asm_text: "vrshl.u32 q7, q7, q10" + - + asm_text: "vrshl.u64 q8, q8, q9" + - + asm_text: "vshr.s8 d15, d15, #8" + - + asm_text: "vshr.s16 d12, d12, #0x10" + - + asm_text: "vshr.s32 d13, d13, #0x20" + - + asm_text: "vshr.s64 d14, d14, #0x40" + - + asm_text: "vshr.u8 d16, d16, #8" + - + asm_text: "vshr.u16 d17, d17, #0x10" + - + asm_text: "vshr.u32 d6, d6, #0x20" + - + asm_text: "vshr.u64 d10, d10, #0x40" + - + asm_text: "vshr.s8 q1, q1, #8" + - + asm_text: "vshr.s16 q2, q2, #0x10" + - + asm_text: "vshr.s32 q3, q3, #0x20" + - + asm_text: "vshr.s64 q4, q4, #0x40" + - + asm_text: "vshr.u8 q5, q5, #8" + - + asm_text: "vshr.u16 q6, q6, #0x10" + - + asm_text: "vshr.u32 q7, q7, #0x20" + - + asm_text: "vshr.u64 q8, q8, #0x40" + - + asm_text: "vrshr.s8 d15, d15, #8" + - + asm_text: "vrshr.s16 d12, d12, #0x10" + - + asm_text: "vrshr.s32 d13, d13, #0x20" + - + asm_text: "vrshr.s64 d14, d14, #0x40" + - + asm_text: "vrshr.u8 d16, d16, #8" + - + asm_text: "vrshr.u16 d17, d17, #0x10" + - + asm_text: "vrshr.u32 d6, d6, #0x20" + - + asm_text: "vrshr.u64 d10, d10, #0x40" + - + asm_text: "vrshr.s8 q1, q1, #8" + - + asm_text: "vrshr.s16 q2, q2, #0x10" + - + asm_text: "vrshr.s32 q3, q3, #0x20" + - + asm_text: "vrshr.s64 q4, q4, #0x40" + - + asm_text: "vrshr.u8 q5, q5, #8" + - + asm_text: "vrshr.u16 q6, q6, #0x10" + - + asm_text: "vrshr.u32 q7, q7, #0x20" + - + asm_text: "vrshr.u64 q8, q8, #0x40" diff --git a/tests/MC/ARM/neon-shiftaccum-encoding.s.yaml b/tests/MC/ARM/neon-shiftaccum-encoding.s.yaml new file mode 100644 index 0000000000..9f81e38cbe --- /dev/null +++ b/tests/MC/ARM/neon-shiftaccum-encoding.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0x30, 0x11, 0xc8, 0xf2, 0x1e, 0xf1, 0x90, 0xf2, 0x1c, 0xd1, 0xa0, 0xf2, 0x9a, 0xb1, 0x80, 0xf2, 0x54, 0xe1, 0x88, 0xf2, 0x5c, 0x61, 0x90, 0xf2, 0x5a, 0x21, 0xe0, 0xf2, 0xd8, 0x01, 0xc0, 0xf2, 0x30, 0x11, 0xc8, 0xf3, 0x1e, 0xb1, 0x95, 0xf3, 0x1f, 0xc1, 0xaa, 0xf3, 0xb0, 0xd1, 0x8a, 0xf3, 0x5e, 0x21, 0x88, 0xf3, 0x5e, 0x41, 0x9a, 0xf3, 0x5c, 0x61, 0xab, 0xf3, 0xda, 0x81, 0xa7, 0xf3, 0x30, 0x01, 0xc8, 0xf2, 0x1e, 0xe1, 0x90, 0xf2, 0x1c, 0xc1, 0xa0, 0xf2, 0x9a, 0xa1, 0x80, 0xf2, 0x54, 0x41, 0x88, 0xf2, 0x5c, 0xc1, 0x90, 0xf2, 0x5a, 0xa1, 0xa0, 0xf2, 0xd8, 0x81, 0x80, 0xf2, 0x30, 0x01, 0xc8, 0xf3, 0x1e, 0xe1, 0x95, 0xf3, 0x1f, 0xf1, 0xaa, 0xf3, 0xb0, 0x01, 0xca, 0xf3, 0x5e, 0xe1, 0x88, 0xf3, 0x5e, 0xe1, 0x9a, 0xf3, 0x5c, 0xc1, 0xab, 0xf3, 0xda, 0xa1, 0xa7, 0xf3, 0x3a, 0x53, 0x88, 0xf2, 0x39, 0x63, 0x90, 0xf2, 0x38, 0x73, 0xa0, 0xf2, 0xb7, 0xe3, 0x80, 0xf2, 0x36, 0xf3, 0x88, 0xf3, 0x35, 0x03, 0xd0, 0xf3, 0x34, 0x13, 0xe0, 0xf3, 0xb3, 0x23, 0xc0, 0xf3, 0x54, 0x23, 0x88, 0xf2, 0x56, 0x43, 0x90, 0xf2, 0x58, 0x63, 0xa0, 0xf2, 0xda, 0x83, 0x80, 0xf2, 0x5c, 0xa3, 0x88, 0xf3, 0x5e, 0xc3, 0x90, 0xf3, 0x70, 0xe3, 0xa0, 0xf3, 0xf2, 0x03, 0xc0, 0xf3, 0x3a, 0xa3, 0xc8, 0xf2, 0x39, 0x93, 0xd0, 0xf2, 0x38, 0x83, 0xe0, 0xf2, 0xb7, 0x73, 0xc0, 0xf2, 0x36, 0x63, 0xc8, 0xf3, 0x35, 0x53, 0xd0, 0xf3, 0x34, 0x43, 0xe0, 0xf3, 0xb3, 0x33, 0xc0, 0xf3, 0x54, 0x43, 0x88, 0xf2, 0x56, 0x63, 0x90, 0xf2, 0x58, 0x83, 0xa0, 0xf2, 0xda, 0xa3, 0x80, 0xf2, 0x5c, 0xc3, 0x88, 0xf3, 0x5e, 0xe3, 0x90, 0xf3, 0x70, 0x03, 0xe0, 0xf3, 0xf2, 0x23, 0xc0, 0xf3, 0x1c, 0xb5, 0x8f, 0xf3, 0x1d, 0xc5, 0x9f, 0xf3, 0x1e, 0xd5, 0xbf, 0xf3, 0x9f, 0xe5, 0xbf, 0xf3, 0x70, 0x25, 0x8f, 0xf3, 0x5e, 0x45, 0x9f, 0xf3, 0x58, 0x65, 0xbf, 0xf3, 0xda, 0x85, 0xbf, 0xf3, 0x1b, 0xc4, 0xc8, 0xf3, 0x1c, 0xa4, 0xd0, 0xf3, 0x1d, 0x84, 0xe0, 0xf3, 0x9e, 0x54, 0xc0, 0xf3, 0x70, 0x24, 0x88, 0xf3, 0x54, 0xa4, 0x90, 0xf3, 0x58, 0xe4, 0xa0, 0xf3, 0xdc, 0x24, 0xc0, 0xf3, 0x1c, 0xc5, 0x8f, 0xf3, 0x1d, 0xd5, 0x9f, 0xf3, 0x1e, 0xe5, 0xbf, 0xf3, 0x9f, 0xf5, 0xbf, 0xf3, 0x70, 0x05, 0xcf, 0xf3, 0x5e, 0xe5, 0x9f, 0xf3, 0x58, 0x85, 0xbf, 0xf3, 0xda, 0xa5, 0xbf, 0xf3, 0x1b, 0xb4, 0x88, 0xf3, 0x1c, 0xc4, 0x90, 0xf3, 0x1d, 0xd4, 0xa0, 0xf3, 0x9e, 0xe4, 0x80, 0xf3, 0x70, 0x04, 0xc8, 0xf3, 0x54, 0x44, 0x90, 0xf3, 0x58, 0x84, 0xa0, 0xf3, 0xdc, 0xc4, 0x80, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vsra.s8 d17, d16, #8" + - + asm_text: "vsra.s16 d15, d14, #0x10" + - + asm_text: "vsra.s32 d13, d12, #0x20" + - + asm_text: "vsra.s64 d11, d10, #0x40" + - + asm_text: "vsra.s8 q7, q2, #8" + - + asm_text: "vsra.s16 q3, q6, #0x10" + - + asm_text: "vsra.s32 q9, q5, #0x20" + - + asm_text: "vsra.s64 q8, q4, #0x40" + - + asm_text: "vsra.u8 d17, d16, #8" + - + asm_text: "vsra.u16 d11, d14, #0xb" + - + asm_text: "vsra.u32 d12, d15, #0x16" + - + asm_text: "vsra.u64 d13, d16, #0x36" + - + asm_text: "vsra.u8 q1, q7, #8" + - + asm_text: "vsra.u16 q2, q7, #6" + - + asm_text: "vsra.u32 q3, q6, #0x15" + - + asm_text: "vsra.u64 q4, q5, #0x19" + - + asm_text: "vsra.s8 d16, d16, #8" + - + asm_text: "vsra.s16 d14, d14, #0x10" + - + asm_text: "vsra.s32 d12, d12, #0x20" + - + asm_text: "vsra.s64 d10, d10, #0x40" + - + asm_text: "vsra.s8 q2, q2, #8" + - + asm_text: "vsra.s16 q6, q6, #0x10" + - + asm_text: "vsra.s32 q5, q5, #0x20" + - + asm_text: "vsra.s64 q4, q4, #0x40" + - + asm_text: "vsra.u8 d16, d16, #8" + - + asm_text: "vsra.u16 d14, d14, #0xb" + - + asm_text: "vsra.u32 d15, d15, #0x16" + - + asm_text: "vsra.u64 d16, d16, #0x36" + - + asm_text: "vsra.u8 q7, q7, #8" + - + asm_text: "vsra.u16 q7, q7, #6" + - + asm_text: "vsra.u32 q6, q6, #0x15" + - + asm_text: "vsra.u64 q5, q5, #0x19" + - + asm_text: "vrsra.s8 d5, d26, #8" + - + asm_text: "vrsra.s16 d6, d25, #0x10" + - + asm_text: "vrsra.s32 d7, d24, #0x20" + - + asm_text: "vrsra.s64 d14, d23, #0x40" + - + asm_text: "vrsra.u8 d15, d22, #8" + - + asm_text: "vrsra.u16 d16, d21, #0x10" + - + asm_text: "vrsra.u32 d17, d20, #0x20" + - + asm_text: "vrsra.u64 d18, d19, #0x40" + - + asm_text: "vrsra.s8 q1, q2, #8" + - + asm_text: "vrsra.s16 q2, q3, #0x10" + - + asm_text: "vrsra.s32 q3, q4, #0x20" + - + asm_text: "vrsra.s64 q4, q5, #0x40" + - + asm_text: "vrsra.u8 q5, q6, #8" + - + asm_text: "vrsra.u16 q6, q7, #0x10" + - + asm_text: "vrsra.u32 q7, q8, #0x20" + - + asm_text: "vrsra.u64 q8, q9, #0x40" + - + asm_text: "vrsra.s8 d26, d26, #8" + - + asm_text: "vrsra.s16 d25, d25, #0x10" + - + asm_text: "vrsra.s32 d24, d24, #0x20" + - + asm_text: "vrsra.s64 d23, d23, #0x40" + - + asm_text: "vrsra.u8 d22, d22, #8" + - + asm_text: "vrsra.u16 d21, d21, #0x10" + - + asm_text: "vrsra.u32 d20, d20, #0x20" + - + asm_text: "vrsra.u64 d19, d19, #0x40" + - + asm_text: "vrsra.s8 q2, q2, #8" + - + asm_text: "vrsra.s16 q3, q3, #0x10" + - + asm_text: "vrsra.s32 q4, q4, #0x20" + - + asm_text: "vrsra.s64 q5, q5, #0x40" + - + asm_text: "vrsra.u8 q6, q6, #8" + - + asm_text: "vrsra.u16 q7, q7, #0x10" + - + asm_text: "vrsra.u32 q8, q8, #0x20" + - + asm_text: "vrsra.u64 q9, q9, #0x40" + - + asm_text: "vsli.8 d11, d12, #7" + - + asm_text: "vsli.16 d12, d13, #0xf" + - + asm_text: "vsli.32 d13, d14, #0x1f" + - + asm_text: "vsli.64 d14, d15, #0x3f" + - + asm_text: "vsli.8 q1, q8, #7" + - + asm_text: "vsli.16 q2, q7, #0xf" + - + asm_text: "vsli.32 q3, q4, #0x1f" + - + asm_text: "vsli.64 q4, q5, #0x3f" + - + asm_text: "vsri.8 d28, d11, #8" + - + asm_text: "vsri.16 d26, d12, #0x10" + - + asm_text: "vsri.32 d24, d13, #0x20" + - + asm_text: "vsri.64 d21, d14, #0x40" + - + asm_text: "vsri.8 q1, q8, #8" + - + asm_text: "vsri.16 q5, q2, #0x10" + - + asm_text: "vsri.32 q7, q4, #0x20" + - + asm_text: "vsri.64 q9, q6, #0x40" + - + asm_text: "vsli.8 d12, d12, #7" + - + asm_text: "vsli.16 d13, d13, #0xf" + - + asm_text: "vsli.32 d14, d14, #0x1f" + - + asm_text: "vsli.64 d15, d15, #0x3f" + - + asm_text: "vsli.8 q8, q8, #7" + - + asm_text: "vsli.16 q7, q7, #0xf" + - + asm_text: "vsli.32 q4, q4, #0x1f" + - + asm_text: "vsli.64 q5, q5, #0x3f" + - + asm_text: "vsri.8 d11, d11, #8" + - + asm_text: "vsri.16 d12, d12, #0x10" + - + asm_text: "vsri.32 d13, d13, #0x20" + - + asm_text: "vsri.64 d14, d14, #0x40" + - + asm_text: "vsri.8 q8, q8, #8" + - + asm_text: "vsri.16 q2, q2, #0x10" + - + asm_text: "vsri.32 q4, q4, #0x20" + - + asm_text: "vsri.64 q6, q6, #0x40" diff --git a/tests/MC/ARM/neon-shuffle-encoding.s.yaml b/tests/MC/ARM/neon-shuffle-encoding.s.yaml new file mode 100644 index 0000000000..d88d80cbe9 --- /dev/null +++ b/tests/MC/ARM/neon-shuffle-encoding.s.yaml @@ -0,0 +1,124 @@ +test_cases: + - + input: + bytes: [ 0xa0, 0x03, 0xf1, 0xf2, 0xa0, 0x05, 0xf1, 0xf2, 0xe0, 0x03, 0xf2, 0xf2, 0xe0, 0x07, 0xf2, 0xf2, 0xa0, 0x06, 0xf1, 0xf2, 0xe0, 0x0c, 0xf2, 0xf2, 0xe0, 0x08, 0xf2, 0xf2, 0xa0, 0x13, 0xf1, 0xf2, 0x0b, 0x75, 0xb7, 0xf2, 0x60, 0x63, 0xb6, 0xf2, 0xc8, 0x27, 0xf2, 0xf2, 0x2a, 0x16, 0xb1, 0xf2, 0x60, 0xac, 0xba, 0xf2, 0x60, 0xa8, 0xba, 0xf2, 0xa0, 0x10, 0xf2, 0xf3, 0xa0, 0x10, 0xf6, 0xf3, 0xa0, 0x10, 0xfa, 0xf3, 0xe0, 0x20, 0xf2, 0xf3, 0xe0, 0x20, 0xf6, 0xf3, 0xe0, 0x20, 0xfa, 0xf3, 0x20, 0x11, 0xf2, 0xf3, 0x20, 0x11, 0xf6, 0xf3, 0x60, 0x21, 0xf2, 0xf3, 0x60, 0x21, 0xf6, 0xf3, 0x60, 0x21, 0xfa, 0xf3, 0xa0, 0x11, 0xf2, 0xf3, 0xa0, 0x11, 0xf6, 0xf3, 0xe0, 0x21, 0xf2, 0xf3, 0xe0, 0x21, 0xf6, 0xf3, 0xe0, 0x21, 0xfa, 0xf3, 0x83, 0x20, 0xba, 0xf3, 0x83, 0x20, 0xba, 0xf3, 0x89, 0x30, 0xb2, 0xf3, 0x89, 0x30, 0xb2, 0xf3, 0x89, 0x30, 0xb2, 0xf3, 0x89, 0x30, 0xb2, 0xf3, 0x89, 0x30, 0xb6, 0xf3, 0x89, 0x30, 0xb6, 0xf3, 0x89, 0x30, 0xb6, 0xf3, 0x89, 0x30, 0xb6, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0xcc, 0xc0, 0xf2, 0xf3, 0xcc, 0xc0, 0xf2, 0xf3, 0xcc, 0xc0, 0xf2, 0xf3, 0xcc, 0xc0, 0xf2, 0xf3, 0xcc, 0xc0, 0xf6, 0xf3, 0xcc, 0xc0, 0xf6, 0xf3, 0xcc, 0xc0, 0xf6, 0xf3, 0xcc, 0xc0, 0xf6, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vext.8 d16, d17, d16, #3" + - + asm_text: "vext.8 d16, d17, d16, #5" + - + asm_text: "vext.8 q8, q9, q8, #3" + - + asm_text: "vext.8 q8, q9, q8, #7" + - + asm_text: "vext.16 d16, d17, d16, #3" + - + asm_text: "vext.32 q8, q9, q8, #3" + - + asm_text: "vext.64 q8, q9, q8, #1" + - + asm_text: "vext.8 d17, d17, d16, #3" + - + asm_text: "vext.8 d7, d7, d11, #5" + - + asm_text: "vext.8 q3, q3, q8, #3" + - + asm_text: "vext.8 q9, q9, q4, #7" + - + asm_text: "vext.16 d1, d1, d26, #3" + - + asm_text: "vext.32 q5, q5, q8, #3" + - + asm_text: "vext.64 q5, q5, q8, #1" + - + asm_text: "vtrn.8 d17, d16" + - + asm_text: "vtrn.16 d17, d16" + - + asm_text: "vtrn.32 d17, d16" + - + asm_text: "vtrn.8 q9, q8" + - + asm_text: "vtrn.16 q9, q8" + - + asm_text: "vtrn.32 q9, q8" + - + asm_text: "vuzp.8 d17, d16" + - + asm_text: "vuzp.16 d17, d16" + - + asm_text: "vuzp.8 q9, q8" + - + asm_text: "vuzp.16 q9, q8" + - + asm_text: "vuzp.32 q9, q8" + - + asm_text: "vzip.8 d17, d16" + - + asm_text: "vzip.16 d17, d16" + - + asm_text: "vzip.8 q9, q8" + - + asm_text: "vzip.16 q9, q8" + - + asm_text: "vzip.32 q9, q8" + - + asm_text: "vtrn.32 d2, d3" + - + asm_text: "vtrn.32 d2, d3" + - + asm_text: "vtrn.8 d3, d9" + - + asm_text: "vtrn.8 d3, d9" + - + asm_text: "vtrn.8 d3, d9" + - + asm_text: "vtrn.8 d3, d9" + - + asm_text: "vtrn.16 d3, d9" + - + asm_text: "vtrn.16 d3, d9" + - + asm_text: "vtrn.16 d3, d9" + - + asm_text: "vtrn.16 d3, d9" + - + asm_text: "vtrn.32 d3, d9" + - + asm_text: "vtrn.32 d3, d9" + - + asm_text: "vtrn.32 d3, d9" + - + asm_text: "vtrn.32 d3, d9" + - + asm_text: "vtrn.32 d3, d9" + - + asm_text: "vtrn.8 q14, q6" + - + asm_text: "vtrn.8 q14, q6" + - + asm_text: "vtrn.8 q14, q6" + - + asm_text: "vtrn.8 q14, q6" + - + asm_text: "vtrn.16 q14, q6" + - + asm_text: "vtrn.16 q14, q6" + - + asm_text: "vtrn.16 q14, q6" + - + asm_text: "vtrn.16 q14, q6" + - + asm_text: "vtrn.32 q14, q6" + - + asm_text: "vtrn.32 q14, q6" + - + asm_text: "vtrn.32 q14, q6" + - + asm_text: "vtrn.32 q14, q6" + - + asm_text: "vtrn.32 q14, q6" diff --git a/tests/MC/ARM/neon-sub-encoding.s.yaml b/tests/MC/ARM/neon-sub-encoding.s.yaml new file mode 100644 index 0000000000..91e179fe13 --- /dev/null +++ b/tests/MC/ARM/neon-sub-encoding.s.yaml @@ -0,0 +1,170 @@ +test_cases: + - + input: + bytes: [ 0xa0, 0x08, 0x41, 0xf3, 0xa0, 0x08, 0x51, 0xf3, 0xa0, 0x08, 0x61, 0xf3, 0xa0, 0x08, 0x71, 0xf3, 0xa1, 0x0d, 0x60, 0xf2, 0xe2, 0x08, 0x40, 0xf3, 0xe2, 0x08, 0x50, 0xf3, 0xe2, 0x08, 0x60, 0xf3, 0xe2, 0x08, 0x70, 0xf3, 0xe2, 0x0d, 0x60, 0xf2, 0x25, 0xd8, 0x0d, 0xf3, 0x26, 0xe8, 0x1e, 0xf3, 0x27, 0xf8, 0x2f, 0xf3, 0xa8, 0x08, 0x70, 0xf3, 0xa9, 0x1d, 0x61, 0xf2, 0x64, 0x28, 0x02, 0xf3, 0x62, 0x48, 0x14, 0xf3, 0x60, 0x68, 0x26, 0xf3, 0x4e, 0x88, 0x38, 0xf3, 0x4c, 0xad, 0x2a, 0xf2, 0xa0, 0x02, 0xc1, 0xf2, 0xa0, 0x02, 0xd1, 0xf2, 0xa0, 0x02, 0xe1, 0xf2, 0xa0, 0x02, 0xc1, 0xf3, 0xa0, 0x02, 0xd1, 0xf3, 0xa0, 0x02, 0xe1, 0xf3, 0xa2, 0x03, 0xc0, 0xf2, 0xa2, 0x03, 0xd0, 0xf2, 0xa2, 0x03, 0xe0, 0xf2, 0xa2, 0x03, 0xc0, 0xf3, 0xa2, 0x03, 0xd0, 0xf3, 0xa2, 0x03, 0xe0, 0xf3, 0xa1, 0x02, 0x40, 0xf2, 0xa1, 0x02, 0x50, 0xf2, 0xa1, 0x02, 0x60, 0xf2, 0xa1, 0x02, 0x40, 0xf3, 0xa1, 0x02, 0x50, 0xf3, 0xa1, 0x02, 0x60, 0xf3, 0xe2, 0x02, 0x40, 0xf2, 0xe2, 0x02, 0x50, 0xf2, 0xe2, 0x02, 0x60, 0xf2, 0xb1, 0x02, 0x40, 0xf2, 0xb1, 0x02, 0x50, 0xf2, 0xb1, 0x02, 0x60, 0xf2, 0xb1, 0x02, 0x70, 0xf2, 0xb1, 0x02, 0x40, 0xf3, 0xb1, 0x02, 0x50, 0xf3, 0xb1, 0x02, 0x60, 0xf3, 0xb1, 0x02, 0x70, 0xf3, 0xf2, 0x02, 0x40, 0xf2, 0xf2, 0x02, 0x50, 0xf2, 0xf2, 0x02, 0x60, 0xf2, 0xf2, 0x02, 0x70, 0xf2, 0xf2, 0x02, 0x40, 0xf3, 0xf2, 0x02, 0x50, 0xf3, 0xf2, 0x02, 0x60, 0xf3, 0xf2, 0x02, 0x70, 0xf3, 0xa2, 0x06, 0xc0, 0xf2, 0xa2, 0x06, 0xd0, 0xf2, 0xa2, 0x06, 0xe0, 0xf2, 0xa2, 0x06, 0xc0, 0xf3, 0xa2, 0x06, 0xd0, 0xf3, 0xa2, 0x06, 0xe0, 0xf3, 0x28, 0xb2, 0x0b, 0xf2, 0x27, 0xc2, 0x1c, 0xf2, 0x26, 0xd2, 0x2d, 0xf2, 0x25, 0xe2, 0x0e, 0xf3, 0x24, 0xf2, 0x1f, 0xf3, 0xa3, 0x02, 0x60, 0xf3, 0x68, 0x22, 0x02, 0xf2, 0x66, 0x42, 0x14, 0xf2, 0x64, 0x62, 0x26, 0xf2, 0x62, 0x82, 0x08, 0xf3, 0x60, 0xa2, 0x1a, 0xf3, 0x4e, 0xc2, 0x2c, 0xf3, 0x05, 0xc3, 0x8c, 0xf2, 0x01, 0xe3, 0x9e, 0xf2, 0x82, 0x03, 0xe0, 0xf2, 0x05, 0xc3, 0x8c, 0xf3, 0x01, 0xe3, 0x9e, 0xf3, 0x82, 0x03, 0xe0, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vsub.i8 d16, d17, d16" + - + asm_text: "vsub.i16 d16, d17, d16" + - + asm_text: "vsub.i32 d16, d17, d16" + - + asm_text: "vsub.i64 d16, d17, d16" + - + asm_text: "vsub.f32 d16, d16, d17" + - + asm_text: "vsub.i8 q8, q8, q9" + - + asm_text: "vsub.i16 q8, q8, q9" + - + asm_text: "vsub.i32 q8, q8, q9" + - + asm_text: "vsub.i64 q8, q8, q9" + - + asm_text: "vsub.f32 q8, q8, q9" + - + asm_text: "vsub.i8 d13, d13, d21" + - + asm_text: "vsub.i16 d14, d14, d22" + - + asm_text: "vsub.i32 d15, d15, d23" + - + asm_text: "vsub.i64 d16, d16, d24" + - + asm_text: "vsub.f32 d17, d17, d25" + - + asm_text: "vsub.i8 q1, q1, q10" + - + asm_text: "vsub.i16 q2, q2, q9" + - + asm_text: "vsub.i32 q3, q3, q8" + - + asm_text: "vsub.i64 q4, q4, q7" + - + asm_text: "vsub.f32 q5, q5, q6" + - + asm_text: "vsubl.s8 q8, d17, d16" + - + asm_text: "vsubl.s16 q8, d17, d16" + - + asm_text: "vsubl.s32 q8, d17, d16" + - + asm_text: "vsubl.u8 q8, d17, d16" + - + asm_text: "vsubl.u16 q8, d17, d16" + - + asm_text: "vsubl.u32 q8, d17, d16" + - + asm_text: "vsubw.s8 q8, q8, d18" + - + asm_text: "vsubw.s16 q8, q8, d18" + - + asm_text: "vsubw.s32 q8, q8, d18" + - + asm_text: "vsubw.u8 q8, q8, d18" + - + asm_text: "vsubw.u16 q8, q8, d18" + - + asm_text: "vsubw.u32 q8, q8, d18" + - + asm_text: "vhsub.s8 d16, d16, d17" + - + asm_text: "vhsub.s16 d16, d16, d17" + - + asm_text: "vhsub.s32 d16, d16, d17" + - + asm_text: "vhsub.u8 d16, d16, d17" + - + asm_text: "vhsub.u16 d16, d16, d17" + - + asm_text: "vhsub.u32 d16, d16, d17" + - + asm_text: "vhsub.s8 q8, q8, q9" + - + asm_text: "vhsub.s16 q8, q8, q9" + - + asm_text: "vhsub.s32 q8, q8, q9" + - + asm_text: "vqsub.s8 d16, d16, d17" + - + asm_text: "vqsub.s16 d16, d16, d17" + - + asm_text: "vqsub.s32 d16, d16, d17" + - + asm_text: "vqsub.s64 d16, d16, d17" + - + asm_text: "vqsub.u8 d16, d16, d17" + - + asm_text: "vqsub.u16 d16, d16, d17" + - + asm_text: "vqsub.u32 d16, d16, d17" + - + asm_text: "vqsub.u64 d16, d16, d17" + - + asm_text: "vqsub.s8 q8, q8, q9" + - + asm_text: "vqsub.s16 q8, q8, q9" + - + asm_text: "vqsub.s32 q8, q8, q9" + - + asm_text: "vqsub.s64 q8, q8, q9" + - + asm_text: "vqsub.u8 q8, q8, q9" + - + asm_text: "vqsub.u16 q8, q8, q9" + - + asm_text: "vqsub.u32 q8, q8, q9" + - + asm_text: "vqsub.u64 q8, q8, q9" + - + asm_text: "vsubhn.i16 d16, q8, q9" + - + asm_text: "vsubhn.i32 d16, q8, q9" + - + asm_text: "vsubhn.i64 d16, q8, q9" + - + asm_text: "vrsubhn.i16 d16, q8, q9" + - + asm_text: "vrsubhn.i32 d16, q8, q9" + - + asm_text: "vrsubhn.i64 d16, q8, q9" + - + asm_text: "vhsub.s8 d11, d11, d24" + - + asm_text: "vhsub.s16 d12, d12, d23" + - + asm_text: "vhsub.s32 d13, d13, d22" + - + asm_text: "vhsub.u8 d14, d14, d21" + - + asm_text: "vhsub.u16 d15, d15, d20" + - + asm_text: "vhsub.u32 d16, d16, d19" + - + asm_text: "vhsub.s8 q1, q1, q12" + - + asm_text: "vhsub.s16 q2, q2, q11" + - + asm_text: "vhsub.s32 q3, q3, q10" + - + asm_text: "vhsub.u8 q4, q4, q9" + - + asm_text: "vhsub.u16 q5, q5, q8" + - + asm_text: "vhsub.u32 q6, q6, q7" + - + asm_text: "vsubw.s8 q6, q6, d5" + - + asm_text: "vsubw.s16 q7, q7, d1" + - + asm_text: "vsubw.s32 q8, q8, d2" + - + asm_text: "vsubw.u8 q6, q6, d5" + - + asm_text: "vsubw.u16 q7, q7, d1" + - + asm_text: "vsubw.u32 q8, q8, d2" diff --git a/tests/MC/ARM/neon-table-encoding.s.yaml b/tests/MC/ARM/neon-table-encoding.s.yaml new file mode 100644 index 0000000000..7f2e0732d5 --- /dev/null +++ b/tests/MC/ARM/neon-table-encoding.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0xa0, 0x08, 0xf1, 0xf3, 0xa2, 0x09, 0xf0, 0xf3, 0xa4, 0x0a, 0xf0, 0xf3, 0xa4, 0x0b, 0xf0, 0xf3, 0xe1, 0x28, 0xf0, 0xf3, 0xe2, 0x39, 0xf0, 0xf3, 0xe5, 0x4a, 0xf0, 0xf3, 0xe5, 0x4b, 0xf0, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vtbl.8 d16, {d17}, d16" + - + asm_text: "vtbl.8 d16, {d16, d17}, d18" + - + asm_text: "vtbl.8 d16, {d16, d17, d18}, d20" + - + asm_text: "vtbl.8 d16, {d16, d17, d18, d19}, d20" + - + asm_text: "vtbx.8 d18, {d16}, d17" + - + asm_text: "vtbx.8 d19, {d16, d17}, d18" + - + asm_text: "vtbx.8 d20, {d16, d17, d18}, d21" + - + asm_text: "vtbx.8 d20, {d16, d17, d18, d19}, d21" diff --git a/tests/MC/ARM/neon-v8.s.yaml b/tests/MC/ARM/neon-v8.s.yaml new file mode 100644 index 0000000000..217c03f05f --- /dev/null +++ b/tests/MC/ARM/neon-v8.s.yaml @@ -0,0 +1,82 @@ +test_cases: + - + input: + bytes: [ 0x11, 0x4f, 0x05, 0xf3, 0x5c, 0x4f, 0x08, 0xf3, 0x3e, 0x5f, 0x24, 0xf3, 0xd4, 0x0f, 0x2a, 0xf3, 0x06, 0x40, 0xbb, 0xf3, 0x8a, 0xc0, 0xbb, 0xf3, 0x4c, 0x80, 0xbb, 0xf3, 0xe4, 0x80, 0xbb, 0xf3, 0x2e, 0x13, 0xbb, 0xf3, 0x8a, 0xc3, 0xbb, 0xf3, 0x64, 0x23, 0xbb, 0xf3, 0xc2, 0xa3, 0xfb, 0xf3, 0x21, 0xf1, 0xbb, 0xf3, 0x83, 0x51, 0xbb, 0xf3, 0x60, 0x61, 0xbb, 0xf3, 0xc6, 0xa1, 0xbb, 0xf3, 0x25, 0xb2, 0xbb, 0xf3, 0xa7, 0xe2, 0xbb, 0xf3, 0x6e, 0x82, 0xbb, 0xf3, 0xe0, 0x22, 0xfb, 0xf3, 0x00, 0x34, 0xba, 0xf3, 0x48, 0x24, 0xba, 0xf3, 0x8c, 0x54, 0xba, 0xf3, 0xc6, 0x04, 0xba, 0xf3, 0x00, 0x35, 0xba, 0xf3, 0x44, 0x05, 0xfa, 0xf3, 0xa2, 0xc5, 0xba, 0xf3, 0xc8, 0x25, 0xfa, 0xf3, 0x80, 0x36, 0xba, 0xf3, 0xc8, 0x26, 0xba, 0xf3, 0x80, 0x37, 0xba, 0xf3, 0xc8, 0x27, 0xba, 0xf3, 0x00, 0x34, 0xba, 0xf3, 0xc6, 0x04, 0xba, 0xf3, 0x00, 0x35, 0xba, 0xf3, 0xc8, 0x25, 0xfa, 0xf3, 0xc8, 0x27, 0xba, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vmaxnm.f32 d4, d5, d1" + - + asm_text: "vmaxnm.f32 q2, q4, q6" + - + asm_text: "vminnm.f32 d5, d4, d30" + - + asm_text: "vminnm.f32 q0, q13, q2" + - + asm_text: "vcvta.s32.f32 d4, d6" + - + asm_text: "vcvta.u32.f32 d12, d10" + - + asm_text: "vcvta.s32.f32 q4, q6" + - + asm_text: "vcvta.u32.f32 q4, q10" + - + asm_text: "vcvtm.s32.f32 d1, d30" + - + asm_text: "vcvtm.u32.f32 d12, d10" + - + asm_text: "vcvtm.s32.f32 q1, q10" + - + asm_text: "vcvtm.u32.f32 q13, q1" + - + asm_text: "vcvtn.s32.f32 d15, d17" + - + asm_text: "vcvtn.u32.f32 d5, d3" + - + asm_text: "vcvtn.s32.f32 q3, q8" + - + asm_text: "vcvtn.u32.f32 q5, q3" + - + asm_text: "vcvtp.s32.f32 d11, d21" + - + asm_text: "vcvtp.u32.f32 d14, d23" + - + asm_text: "vcvtp.s32.f32 q4, q15" + - + asm_text: "vcvtp.u32.f32 q9, q8" + - + asm_text: "vrintn.f32 d3, d0" + - + asm_text: "vrintn.f32 q1, q4" + - + asm_text: "vrintx.f32 d5, d12" + - + asm_text: "vrintx.f32 q0, q3" + - + asm_text: "vrinta.f32 d3, d0" + - + asm_text: "vrinta.f32 q8, q2" + - + asm_text: "vrintz.f32 d12, d18" + - + asm_text: "vrintz.f32 q9, q4" + - + asm_text: "vrintm.f32 d3, d0" + - + asm_text: "vrintm.f32 q1, q4" + - + asm_text: "vrintp.f32 d3, d0" + - + asm_text: "vrintp.f32 q1, q4" + - + asm_text: "vrintn.f32 d3, d0" + - + asm_text: "vrintx.f32 q0, q3" + - + asm_text: "vrinta.f32 d3, d0" + - + asm_text: "vrintz.f32 q9, q4" + - + asm_text: "vrintp.f32 q1, q4" diff --git a/tests/MC/ARM/neon-vld-encoding.s.yaml b/tests/MC/ARM/neon-vld-encoding.s.yaml new file mode 100644 index 0000000000..a6af6c6284 --- /dev/null +++ b/tests/MC/ARM/neon-vld-encoding.s.yaml @@ -0,0 +1,432 @@ +test_cases: + - + input: + bytes: [ 0x1f, 0x07, 0x60, 0xf4, 0x4f, 0x07, 0x60, 0xf4, 0x8f, 0x07, 0x60, 0xf4, 0xcf, 0x07, 0x60, 0xf4, 0x1f, 0x0a, 0x60, 0xf4, 0x6f, 0x0a, 0x60, 0xf4, 0x8f, 0x0a, 0x60, 0xf4, 0xcf, 0x0a, 0x60, 0xf4, 0x0f, 0x16, 0x23, 0xf4, 0x5f, 0x46, 0x23, 0xf4, 0x8f, 0x56, 0x23, 0xf4, 0xdf, 0x66, 0x23, 0xf4, 0x0f, 0x12, 0x23, 0xf4, 0x5f, 0x42, 0x23, 0xf4, 0x8f, 0x52, 0x23, 0xf4, 0xdf, 0x62, 0x23, 0xf4, 0x1d, 0x07, 0x60, 0xf4, 0x4d, 0x07, 0x60, 0xf4, 0x8d, 0x07, 0x60, 0xf4, 0xcd, 0x07, 0x60, 0xf4, 0x1d, 0x0a, 0x60, 0xf4, 0x6d, 0x0a, 0x60, 0xf4, 0x8d, 0x0a, 0x60, 0xf4, 0xcd, 0x0a, 0x60, 0xf4, 0x15, 0x07, 0x60, 0xf4, 0x45, 0x07, 0x60, 0xf4, 0x85, 0x07, 0x60, 0xf4, 0xc5, 0x07, 0x60, 0xf4, 0x15, 0x0a, 0x60, 0xf4, 0x65, 0x0a, 0x60, 0xf4, 0x85, 0x0a, 0x60, 0xf4, 0xc5, 0x0a, 0x60, 0xf4, 0x0d, 0x16, 0x23, 0xf4, 0x5d, 0x46, 0x23, 0xf4, 0x8d, 0x56, 0x23, 0xf4, 0xdd, 0x66, 0x23, 0xf4, 0x06, 0x16, 0x23, 0xf4, 0x56, 0x46, 0x23, 0xf4, 0x86, 0x56, 0x23, 0xf4, 0xd6, 0x66, 0x23, 0xf4, 0x0d, 0x12, 0x23, 0xf4, 0x5d, 0x42, 0x23, 0xf4, 0x8d, 0x52, 0x23, 0xf4, 0xdd, 0x62, 0x23, 0xf4, 0x08, 0x12, 0x23, 0xf4, 0x58, 0x42, 0x23, 0xf4, 0x88, 0x52, 0x23, 0xf4, 0xd8, 0x62, 0x23, 0xf4, 0x1f, 0x08, 0x60, 0xf4, 0x6f, 0x08, 0x60, 0xf4, 0x8f, 0x08, 0x60, 0xf4, 0x1f, 0x03, 0x60, 0xf4, 0x6f, 0x03, 0x60, 0xf4, 0xbf, 0x03, 0x60, 0xf4, 0x1d, 0x38, 0x60, 0xf4, 0x6d, 0x08, 0x60, 0xf4, 0x8d, 0x48, 0x60, 0xf4, 0x1d, 0x43, 0x20, 0xf4, 0x6d, 0x13, 0x20, 0xf4, 0xbd, 0xe3, 0x20, 0xf4, 0x16, 0x38, 0x60, 0xf4, 0x66, 0x08, 0x60, 0xf4, 0x86, 0x48, 0x60, 0xf4, 0x16, 0x43, 0x20, 0xf4, 0x66, 0x13, 0x20, 0xf4, 0xb6, 0xe3, 0x20, 0xf4, 0x0f, 0x04, 0x61, 0xf4, 0x4f, 0x64, 0x22, 0xf4, 0x8f, 0x14, 0x23, 0xf4, 0x1f, 0x05, 0x60, 0xf4, 0x4f, 0xb5, 0x64, 0xf4, 0x8f, 0x65, 0x25, 0xf4, 0x01, 0xc4, 0x26, 0xf4, 0x42, 0xb4, 0x27, 0xf4, 0x83, 0x24, 0x28, 0xf4, 0x04, 0x45, 0x29, 0xf4, 0x44, 0xe5, 0x29, 0xf4, 0x85, 0x05, 0x6a, 0xf4, 0x0d, 0x64, 0x28, 0xf4, 0x4d, 0x94, 0x27, 0xf4, 0x8d, 0x14, 0x26, 0xf4, 0x1d, 0x05, 0x60, 0xf4, 0x4d, 0x45, 0x65, 0xf4, 0x8d, 0x55, 0x24, 0xf4, 0x1f, 0x00, 0x61, 0xf4, 0x6f, 0x00, 0x62, 0xf4, 0xbf, 0x00, 0x63, 0xf4, 0x3f, 0x11, 0x65, 0xf4, 0x4f, 0x11, 0x67, 0xf4, 0x8f, 0x01, 0x68, 0xf4, 0x1d, 0x00, 0x61, 0xf4, 0x6d, 0x00, 0x62, 0xf4, 0xbd, 0x00, 0x63, 0xf4, 0x3d, 0x11, 0x65, 0xf4, 0x4d, 0x11, 0x67, 0xf4, 0x8d, 0x01, 0x68, 0xf4, 0x18, 0x00, 0x61, 0xf4, 0x47, 0x00, 0x62, 0xf4, 0x95, 0x00, 0x63, 0xf4, 0x32, 0x01, 0x64, 0xf4, 0x43, 0x01, 0x66, 0xf4, 0x84, 0x11, 0x69, 0xf4, 0x0f, 0x4c, 0xa1, 0xf4, 0x0d, 0x4c, 0xa1, 0xf4, 0x03, 0x4c, 0xa1, 0xf4, 0x2f, 0x4c, 0xa1, 0xf4, 0x2d, 0x4c, 0xa1, 0xf4, 0x23, 0x4c, 0xa1, 0xf4, 0x6f, 0x00, 0xe0, 0xf4, 0x9f, 0x04, 0xe0, 0xf4, 0xbf, 0x08, 0xe0, 0xf4, 0xcd, 0xc0, 0xa2, 0xf4, 0xc2, 0xc0, 0xa2, 0xf4, 0xcd, 0xc4, 0xa2, 0xf4, 0x82, 0xc4, 0xa2, 0xf4, 0x3f, 0x01, 0xe0, 0xf4, 0x5f, 0x05, 0xe0, 0xf4, 0x8f, 0x09, 0xe0, 0xf4, 0x6f, 0x15, 0xe0, 0xf4, 0x5f, 0x19, 0xe0, 0xf4, 0x5d, 0x19, 0xe0, 0xf4, 0x83, 0x21, 0xa2, 0xf4, 0x8d, 0x21, 0xa2, 0xf4, 0x8f, 0x21, 0xa2, 0xf4, 0x8f, 0x6d, 0xe1, 0xf4, 0xaf, 0x6d, 0xe1, 0xf4, 0x8d, 0xad, 0xa3, 0xf4, 0xad, 0xed, 0xa4, 0xf4, 0x84, 0x6d, 0xe5, 0xf4, 0xa4, 0x6d, 0xe6, 0xf4, 0x2f, 0x02, 0xe1, 0xf4, 0x4f, 0x66, 0xa2, 0xf4, 0x8f, 0x1a, 0xa3, 0xf4, 0xaf, 0xb6, 0xe4, 0xf4, 0x4f, 0x6a, 0xa5, 0xf4, 0x61, 0xc2, 0xa6, 0xf4, 0x82, 0xb6, 0xa7, 0xf4, 0x83, 0x2a, 0xa8, 0xf4, 0xa4, 0xe6, 0xa9, 0xf4, 0x45, 0x0a, 0xea, 0xf4, 0xcd, 0x62, 0xa8, 0xf4, 0x8d, 0x96, 0xa7, 0xf4, 0x8d, 0x1a, 0xa6, 0xf4, 0xad, 0x46, 0xe5, 0xf4, 0x4d, 0x5a, 0xa4, 0xf4, 0x0f, 0x0e, 0xe1, 0xf4, 0x4f, 0x0e, 0xe2, 0xf4, 0x8f, 0x0e, 0xe3, 0xf4, 0x2f, 0x1e, 0xe7, 0xf4, 0x6f, 0x1e, 0xe7, 0xf4, 0xaf, 0x0e, 0xe8, 0xf4, 0x0d, 0x0e, 0xe1, 0xf4, 0x4d, 0x0e, 0xe2, 0xf4, 0x8d, 0x0e, 0xe3, 0xf4, 0x2d, 0x1e, 0xe7, 0xf4, 0x6d, 0x1e, 0xe7, 0xf4, 0xad, 0x0e, 0xe8, 0xf4, 0x08, 0x0e, 0xe1, 0xf4, 0x47, 0x0e, 0xe2, 0xf4, 0x85, 0x0e, 0xe3, 0xf4, 0x23, 0x0e, 0xe6, 0xf4, 0x63, 0x0e, 0xe6, 0xf4, 0xa4, 0x1e, 0xe9, 0xf4, 0x2f, 0x03, 0xe1, 0xf4, 0x4f, 0x07, 0xe2, 0xf4, 0x8f, 0x0b, 0xe3, 0xf4, 0x6f, 0x17, 0xe7, 0xf4, 0xcf, 0x0b, 0xe8, 0xf4, 0x3d, 0x03, 0xe1, 0xf4, 0x5d, 0x07, 0xe2, 0xf4, 0xad, 0x0b, 0xe3, 0xf4, 0x6d, 0x17, 0xe7, 0xf4, 0xcd, 0x0b, 0xe8, 0xf4, 0x38, 0x03, 0xe1, 0xf4, 0x47, 0x07, 0xe2, 0xf4, 0x95, 0x0b, 0xe3, 0xf4, 0x63, 0x07, 0xe6, 0xf4, 0xc4, 0x1b, 0xe9, 0xf4, 0x0f, 0x0f, 0xe1, 0xf4, 0x4f, 0x0f, 0xe2, 0xf4, 0x8f, 0x0f, 0xe3, 0xf4, 0x2f, 0x1f, 0xe7, 0xf4, 0x6f, 0x1f, 0xe7, 0xf4, 0xaf, 0x0f, 0xe8, 0xf4, 0x0d, 0x0f, 0xe1, 0xf4, 0x4d, 0x0f, 0xe2, 0xf4, 0x8d, 0x0f, 0xe3, 0xf4, 0x2d, 0x1f, 0xe7, 0xf4, 0x6d, 0x1f, 0xe7, 0xf4, 0xad, 0x0f, 0xe8, 0xf4, 0x08, 0x0f, 0xe1, 0xf4, 0x47, 0x0f, 0xe2, 0xf4, 0x85, 0x0f, 0xe3, 0xf4, 0x23, 0x0f, 0xe6, 0xf4, 0x63, 0x0f, 0xe6, 0xf4, 0xa4, 0x1f, 0xe9, 0xf4, 0x0f, 0x6a, 0x29, 0xf4, 0x0f, 0x62, 0x29, 0xf4, 0x0f, 0x27, 0x22, 0xf4, 0x0f, 0x27, 0x22, 0xf4, 0x0f, 0x27, 0x22, 0xf4, 0x0f, 0x4a, 0x22, 0xf4, 0x0f, 0x4a, 0x22, 0xf4, 0x0f, 0x4a, 0x22, 0xf4, 0x8f, 0x4a, 0x22, 0xf4, 0x0f, 0x26, 0x22, 0xf4, 0x8f, 0x26, 0x22, 0xf4, 0xcf, 0x26, 0x22, 0xf4, 0xed, 0x22, 0x22, 0xf4, 0xed, 0x22, 0x22, 0xf4, 0x1f, 0x08, 0x60, 0xf4, 0x6f, 0x08, 0x60, 0xf4 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vld1.8 {d16}, [r0:64]" + - + asm_text: "vld1.16 {d16}, [r0]" + - + asm_text: "vld1.32 {d16}, [r0]" + - + asm_text: "vld1.64 {d16}, [r0]" + - + asm_text: "vld1.8 {d16, d17}, [r0:64]" + - + asm_text: "vld1.16 {d16, d17}, [r0:128]" + - + asm_text: "vld1.32 {d16, d17}, [r0]" + - + asm_text: "vld1.64 {d16, d17}, [r0]" + - + asm_text: "vld1.8 {d1, d2, d3}, [r3]" + - + asm_text: "vld1.16 {d4, d5, d6}, [r3:64]" + - + asm_text: "vld1.32 {d5, d6, d7}, [r3]" + - + asm_text: "vld1.64 {d6, d7, d8}, [r3:64]" + - + asm_text: "vld1.8 {d1, d2, d3, d4}, [r3]" + - + asm_text: "vld1.16 {d4, d5, d6, d7}, [r3:64]" + - + asm_text: "vld1.32 {d5, d6, d7, d8}, [r3]" + - + asm_text: "vld1.64 {d6, d7, d8, d9}, [r3:64]" + - + asm_text: "vld1.8 {d16}, [r0:64]!" + - + asm_text: "vld1.16 {d16}, [r0]!" + - + asm_text: "vld1.32 {d16}, [r0]!" + - + asm_text: "vld1.64 {d16}, [r0]!" + - + asm_text: "vld1.8 {d16, d17}, [r0:64]!" + - + asm_text: "vld1.16 {d16, d17}, [r0:128]!" + - + asm_text: "vld1.32 {d16, d17}, [r0]!" + - + asm_text: "vld1.64 {d16, d17}, [r0]!" + - + asm_text: "vld1.8 {d16}, [r0:64], r5" + - + asm_text: "vld1.16 {d16}, [r0], r5" + - + asm_text: "vld1.32 {d16}, [r0], r5" + - + asm_text: "vld1.64 {d16}, [r0], r5" + - + asm_text: "vld1.8 {d16, d17}, [r0:64], r5" + - + asm_text: "vld1.16 {d16, d17}, [r0:128], r5" + - + asm_text: "vld1.32 {d16, d17}, [r0], r5" + - + asm_text: "vld1.64 {d16, d17}, [r0], r5" + - + asm_text: "vld1.8 {d1, d2, d3}, [r3]!" + - + asm_text: "vld1.16 {d4, d5, d6}, [r3:64]!" + - + asm_text: "vld1.32 {d5, d6, d7}, [r3]!" + - + asm_text: "vld1.64 {d6, d7, d8}, [r3:64]!" + - + asm_text: "vld1.8 {d1, d2, d3}, [r3], r6" + - + asm_text: "vld1.16 {d4, d5, d6}, [r3:64], r6" + - + asm_text: "vld1.32 {d5, d6, d7}, [r3], r6" + - + asm_text: "vld1.64 {d6, d7, d8}, [r3:64], r6" + - + asm_text: "vld1.8 {d1, d2, d3, d4}, [r3]!" + - + asm_text: "vld1.16 {d4, d5, d6, d7}, [r3:64]!" + - + asm_text: "vld1.32 {d5, d6, d7, d8}, [r3]!" + - + asm_text: "vld1.64 {d6, d7, d8, d9}, [r3:64]!" + - + asm_text: "vld1.8 {d1, d2, d3, d4}, [r3], r8" + - + asm_text: "vld1.16 {d4, d5, d6, d7}, [r3:64], r8" + - + asm_text: "vld1.32 {d5, d6, d7, d8}, [r3], r8" + - + asm_text: "vld1.64 {d6, d7, d8, d9}, [r3:64], r8" + - + asm_text: "vld2.8 {d16, d17}, [r0:64]" + - + asm_text: "vld2.16 {d16, d17}, [r0:128]" + - + asm_text: "vld2.32 {d16, d17}, [r0]" + - + asm_text: "vld2.8 {d16, d17, d18, d19}, [r0:64]" + - + asm_text: "vld2.16 {d16, d17, d18, d19}, [r0:128]" + - + asm_text: "vld2.32 {d16, d17, d18, d19}, [r0:256]" + - + asm_text: "vld2.8 {d19, d20}, [r0:64]!" + - + asm_text: "vld2.16 {d16, d17}, [r0:128]!" + - + asm_text: "vld2.32 {d20, d21}, [r0]!" + - + asm_text: "vld2.8 {d4, d5, d6, d7}, [r0:64]!" + - + asm_text: "vld2.16 {d1, d2, d3, d4}, [r0:128]!" + - + asm_text: "vld2.32 {d14, d15, d16, d17}, [r0:256]!" + - + asm_text: "vld2.8 {d19, d20}, [r0:64], r6" + - + asm_text: "vld2.16 {d16, d17}, [r0:128], r6" + - + asm_text: "vld2.32 {d20, d21}, [r0], r6" + - + asm_text: "vld2.8 {d4, d5, d6, d7}, [r0:64], r6" + - + asm_text: "vld2.16 {d1, d2, d3, d4}, [r0:128], r6" + - + asm_text: "vld2.32 {d14, d15, d16, d17}, [r0:256], r6" + - + asm_text: "vld3.8 {d16, d17, d18}, [r1]" + - + asm_text: "vld3.16 {d6, d7, d8}, [r2]" + - + asm_text: "vld3.32 {d1, d2, d3}, [r3]" + - + asm_text: "vld3.8 {d16, d18, d20}, [r0:64]" + - + asm_text: "vld3.16 {d27, d29, d31}, [r4]" + - + asm_text: "vld3.32 {d6, d8, d10}, [r5]" + - + asm_text: "vld3.8 {d12, d13, d14}, [r6], r1" + - + asm_text: "vld3.16 {d11, d12, d13}, [r7], r2" + - + asm_text: "vld3.32 {d2, d3, d4}, [r8], r3" + - + asm_text: "vld3.8 {d4, d6, d8}, [r9], r4" + - + asm_text: "vld3.16 {d14, d16, d18}, [r9], r4" + - + asm_text: "vld3.32 {d16, d18, d20}, [r10], r5" + - + asm_text: "vld3.8 {d6, d7, d8}, [r8]!" + - + asm_text: "vld3.16 {d9, d10, d11}, [r7]!" + - + asm_text: "vld3.32 {d1, d2, d3}, [r6]!" + - + asm_text: "vld3.8 {d16, d18, d20}, [r0:64]!" + - + asm_text: "vld3.16 {d20, d22, d24}, [r5]!" + - + asm_text: "vld3.32 {d5, d7, d9}, [r4]!" + - + asm_text: "vld4.8 {d16, d17, d18, d19}, [r1:64]" + - + asm_text: "vld4.16 {d16, d17, d18, d19}, [r2:128]" + - + asm_text: "vld4.32 {d16, d17, d18, d19}, [r3:256]" + - + asm_text: "vld4.8 {d17, d19, d21, d23}, [r5:256]" + - + asm_text: "vld4.16 {d17, d19, d21, d23}, [r7]" + - + asm_text: "vld4.32 {d16, d18, d20, d22}, [r8]" + - + asm_text: "vld4.8 {d16, d17, d18, d19}, [r1:64]!" + - + asm_text: "vld4.16 {d16, d17, d18, d19}, [r2:128]!" + - + asm_text: "vld4.32 {d16, d17, d18, d19}, [r3:256]!" + - + asm_text: "vld4.8 {d17, d19, d21, d23}, [r5:256]!" + - + asm_text: "vld4.16 {d17, d19, d21, d23}, [r7]!" + - + asm_text: "vld4.32 {d16, d18, d20, d22}, [r8]!" + - + asm_text: "vld4.8 {d16, d17, d18, d19}, [r1:64], r8" + - + asm_text: "vld4.16 {d16, d17, d18, d19}, [r2], r7" + - + asm_text: "vld4.32 {d16, d17, d18, d19}, [r3:64], r5" + - + asm_text: "vld4.8 {d16, d18, d20, d22}, [r4:256], r2" + - + asm_text: "vld4.16 {d16, d18, d20, d22}, [r6], r3" + - + asm_text: "vld4.32 {d17, d19, d21, d23}, [r9], r4" + - + asm_text: "vld1.8 {d4[]}, [r1]" + - + asm_text: "vld1.8 {d4[]}, [r1]!" + - + asm_text: "vld1.8 {d4[]}, [r1], r3" + - + asm_text: "vld1.8 {d4[], d5[]}, [r1]" + - + asm_text: "vld1.8 {d4[], d5[]}, [r1]!" + - + asm_text: "vld1.8 {d4[], d5[]}, [r1], r3" + - + asm_text: "vld1.8 {d16[3]}, [r0]" + - + asm_text: "vld1.16 {d16[2]}, [r0:16]" + - + asm_text: "vld1.32 {d16[1]}, [r0:32]" + - + asm_text: "vld1.8 {d12[6]}, [r2]!" + - + asm_text: "vld1.8 {d12[6]}, [r2], r2" + - + asm_text: "vld1.16 {d12[3]}, [r2]!" + - + asm_text: "vld1.16 {d12[2]}, [r2], r2" + - + asm_text: "vld2.8 {d16[1], d17[1]}, [r0:16]" + - + asm_text: "vld2.16 {d16[1], d17[1]}, [r0:32]" + - + asm_text: "vld2.32 {d16[1], d17[1]}, [r0]" + - + asm_text: "vld2.16 {d17[1], d19[1]}, [r0]" + - + asm_text: "vld2.32 {d17[0], d19[0]}, [r0:64]" + - + asm_text: "vld2.32 {d17[0], d19[0]}, [r0:64]!" + - + asm_text: "vld2.8 {d2[4], d3[4]}, [r2], r3" + - + asm_text: "vld2.8 {d2[4], d3[4]}, [r2]!" + - + asm_text: "vld2.8 {d2[4], d3[4]}, [r2]" + - + asm_text: "vld2.32 {d22[], d23[]}, [r1]" + - + asm_text: "vld2.32 {d22[], d24[]}, [r1]" + - + asm_text: "vld2.32 {d10[], d11[]}, [r3]!" + - + asm_text: "vld2.32 {d14[], d16[]}, [r4]!" + - + asm_text: "vld2.32 {d22[], d23[]}, [r5], r4" + - + asm_text: "vld2.32 {d22[], d24[]}, [r6], r4" + - + asm_text: "vld3.8 {d16[1], d17[1], d18[1]}, [r1]" + - + asm_text: "vld3.16 {d6[1], d7[1], d8[1]}, [r2]" + - + asm_text: "vld3.32 {d1[1], d2[1], d3[1]}, [r3]" + - + asm_text: "vld3.16 {d27[2], d29[2], d31[2]}, [r4]" + - + asm_text: "vld3.32 {d6[0], d8[0], d10[0]}, [r5]" + - + asm_text: "vld3.8 {d12[3], d13[3], d14[3]}, [r6], r1" + - + asm_text: "vld3.16 {d11[2], d12[2], d13[2]}, [r7], r2" + - + asm_text: "vld3.32 {d2[1], d3[1], d4[1]}, [r8], r3" + - + asm_text: "vld3.16 {d14[2], d16[2], d18[2]}, [r9], r4" + - + asm_text: "vld3.32 {d16[0], d18[0], d20[0]}, [r10], r5" + - + asm_text: "vld3.8 {d6[6], d7[6], d8[6]}, [r8]!" + - + asm_text: "vld3.16 {d9[2], d10[2], d11[2]}, [r7]!" + - + asm_text: "vld3.32 {d1[1], d2[1], d3[1]}, [r6]!" + - + asm_text: "vld3.16 {d20[2], d22[2], d24[2]}, [r5]!" + - + asm_text: "vld3.32 {d5[0], d7[0], d9[0]}, [r4]!" + - + asm_text: "vld3.8 {d16[], d17[], d18[]}, [r1]" + - + asm_text: "vld3.16 {d16[], d17[], d18[]}, [r2]" + - + asm_text: "vld3.32 {d16[], d17[], d18[]}, [r3]" + - + asm_text: "vld3.8 {d17[], d19[], d21[]}, [r7]" + - + asm_text: "vld3.16 {d17[], d19[], d21[]}, [r7]" + - + asm_text: "vld3.32 {d16[], d18[], d20[]}, [r8]" + - + asm_text: "vld3.8 {d16[], d17[], d18[]}, [r1]!" + - + asm_text: "vld3.16 {d16[], d17[], d18[]}, [r2]!" + - + asm_text: "vld3.32 {d16[], d17[], d18[]}, [r3]!" + - + asm_text: "vld3.8 {d17[], d19[], d21[]}, [r7]!" + - + asm_text: "vld3.16 {d17[], d19[], d21[]}, [r7]!" + - + asm_text: "vld3.32 {d16[], d18[], d20[]}, [r8]!" + - + asm_text: "vld3.8 {d16[], d17[], d18[]}, [r1], r8" + - + asm_text: "vld3.16 {d16[], d17[], d18[]}, [r2], r7" + - + asm_text: "vld3.32 {d16[], d17[], d18[]}, [r3], r5" + - + asm_text: "vld3.8 {d16[], d18[], d20[]}, [r6], r3" + - + asm_text: "vld3.16 {d16[], d18[], d20[]}, [r6], r3" + - + asm_text: "vld3.32 {d17[], d19[], d21[]}, [r9], r4" + - + asm_text: "vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1]" + - + asm_text: "vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2]" + - + asm_text: "vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3]" + - + asm_text: "vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]" + - + asm_text: "vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]" + - + asm_text: "vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]!" + - + asm_text: "vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2:64]!" + - + asm_text: "vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:128]!" + - + asm_text: "vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]!" + - + asm_text: "vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]!" + - + asm_text: "vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32], r8" + - + asm_text: "vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7" + - + asm_text: "vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:64], r5" + - + asm_text: "vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3" + - + asm_text: "vld4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4" + - + asm_text: "vld4.8 {d16[], d17[], d18[], d19[]}, [r1]" + - + asm_text: "vld4.16 {d16[], d17[], d18[], d19[]}, [r2]" + - + asm_text: "vld4.32 {d16[], d17[], d18[], d19[]}, [r3]" + - + asm_text: "vld4.8 {d17[], d19[], d21[], d23[]}, [r7]" + - + asm_text: "vld4.16 {d17[], d19[], d21[], d23[]}, [r7]" + - + asm_text: "vld4.32 {d16[], d18[], d20[], d22[]}, [r8]" + - + asm_text: "vld4.8 {d16[], d17[], d18[], d19[]}, [r1]!" + - + asm_text: "vld4.16 {d16[], d17[], d18[], d19[]}, [r2]!" + - + asm_text: "vld4.32 {d16[], d17[], d18[], d19[]}, [r3]!" + - + asm_text: "vld4.8 {d17[], d19[], d21[], d23[]}, [r7]!" + - + asm_text: "vld4.16 {d17[], d19[], d21[], d23[]}, [r7]!" + - + asm_text: "vld4.32 {d16[], d18[], d20[], d22[]}, [r8]!" + - + asm_text: "vld4.8 {d16[], d17[], d18[], d19[]}, [r1], r8" + - + asm_text: "vld4.16 {d16[], d17[], d18[], d19[]}, [r2], r7" + - + asm_text: "vld4.32 {d16[], d17[], d18[], d19[]}, [r3], r5" + - + asm_text: "vld4.8 {d16[], d18[], d20[], d22[]}, [r6], r3" + - + asm_text: "vld4.16 {d16[], d18[], d20[], d22[]}, [r6], r3" + - + asm_text: "vld4.32 {d17[], d19[], d21[], d23[]}, [r9], r4" + - + asm_text: "vld1.8 {d6, d7}, [r9]" + - + asm_text: "vld1.8 {d6, d7, d8, d9}, [r9]" + - + asm_text: "vld1.8 {d2}, [r2]" + - + asm_text: "vld1.8 {d2}, [r2]" + - + asm_text: "vld1.8 {d2}, [r2]" + - + asm_text: "vld1.8 {d4, d5}, [r2]" + - + asm_text: "vld1.8 {d4, d5}, [r2]" + - + asm_text: "vld1.8 {d4, d5}, [r2]" + - + asm_text: "vld1.32 {d4, d5}, [r2]" + - + asm_text: "vld1.8 {d2, d3, d4}, [r2]" + - + asm_text: "vld1.32 {d2, d3, d4}, [r2]" + - + asm_text: "vld1.64 {d2, d3, d4}, [r2]" + - + asm_text: "vld1.64 {d2, d3, d4, d5}, [r2:128]!" + - + asm_text: "vld1.64 {d2, d3, d4, d5}, [r2:128]!" + - + asm_text: "vld2.8 {d16, d17}, [r0:64]" + - + asm_text: "vld2.16 {d16, d17}, [r0:128]" diff --git a/tests/MC/ARM/neon-vld-vst-align.s.yaml b/tests/MC/ARM/neon-vld-vst-align.s.yaml new file mode 100644 index 0000000000..d5a1486f1b --- /dev/null +++ b/tests/MC/ARM/neon-vld-vst-align.s.yaml @@ -0,0 +1,1922 @@ +test_cases: + - + input: + bytes: [ 0x24, 0xf9, 0x0f, 0x07, 0x24, 0xf9, 0x1f, 0x07, 0x24, 0xf9, 0x0d, 0x07, 0x24, 0xf9, 0x1d, 0x07, 0x24, 0xf9, 0x06, 0x07, 0x24, 0xf9, 0x16, 0x07, 0x24, 0xf9, 0x0f, 0x0a, 0x24, 0xf9, 0x1f, 0x0a, 0x24, 0xf9, 0x2f, 0x0a, 0x24, 0xf9, 0x0d, 0x0a, 0x24, 0xf9, 0x1d, 0x0a, 0x24, 0xf9, 0x2d, 0x0a, 0x24, 0xf9, 0x06, 0x0a, 0x24, 0xf9, 0x16, 0x0a, 0x24, 0xf9, 0x26, 0x0a, 0x24, 0xf9, 0x0f, 0x06, 0x24, 0xf9, 0x1f, 0x06, 0x24, 0xf9, 0x0d, 0x06, 0x24, 0xf9, 0x1d, 0x06, 0x24, 0xf9, 0x06, 0x06, 0x24, 0xf9, 0x16, 0x06, 0x24, 0xf9, 0x0f, 0x02, 0x24, 0xf9, 0x1f, 0x02, 0x24, 0xf9, 0x2f, 0x02, 0x24, 0xf9, 0x3f, 0x02, 0x24, 0xf9, 0x0d, 0x02, 0x24, 0xf9, 0x1d, 0x02, 0x24, 0xf9, 0x2d, 0x02, 0x24, 0xf9, 0x3d, 0x02, 0x24, 0xf9, 0x06, 0x02, 0x24, 0xf9, 0x16, 0x02, 0x24, 0xf9, 0x26, 0x02, 0x24, 0xf9, 0x36, 0x02, 0xa4, 0xf9, 0x4f, 0x00, 0xa4, 0xf9, 0x4d, 0x00, 0xa4, 0xf9, 0x46, 0x00, 0xa4, 0xf9, 0x0f, 0x0c, 0xa4, 0xf9, 0x0d, 0x0c, 0xa4, 0xf9, 0x06, 0x0c, 0xa4, 0xf9, 0x2f, 0x0c, 0xa4, 0xf9, 0x2d, 0x0c, 0xa4, 0xf9, 0x26, 0x0c, 0x24, 0xf9, 0x4f, 0x07, 0x24, 0xf9, 0x5f, 0x07, 0x24, 0xf9, 0x4d, 0x07, 0x24, 0xf9, 0x5d, 0x07, 0x24, 0xf9, 0x46, 0x07, 0x24, 0xf9, 0x56, 0x07, 0x24, 0xf9, 0x4f, 0x0a, 0x24, 0xf9, 0x5f, 0x0a, 0x24, 0xf9, 0x6f, 0x0a, 0x24, 0xf9, 0x4d, 0x0a, 0x24, 0xf9, 0x5d, 0x0a, 0x24, 0xf9, 0x6d, 0x0a, 0x24, 0xf9, 0x46, 0x0a, 0x24, 0xf9, 0x56, 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0xf9, 0x8d, 0x0b, 0x84, 0xf9, 0x9d, 0x0b, 0x84, 0xf9, 0xad, 0x0b, 0x84, 0xf9, 0x86, 0x0b, 0x84, 0xf9, 0x96, 0x0b, 0x84, 0xf9, 0xa6, 0x0b, 0x84, 0xf9, 0xcf, 0x0b, 0x84, 0xf9, 0xdf, 0x0b, 0x84, 0xf9, 0xef, 0x0b, 0x84, 0xf9, 0xcd, 0x0b, 0x84, 0xf9, 0xdd, 0x0b, 0x84, 0xf9, 0xed, 0x0b, 0x84, 0xf9, 0xc6, 0x0b, 0x84, 0xf9, 0xd6, 0x0b, 0x84, 0xf9, 0xe6, 0x0b, 0x84, 0xf9, 0x8d, 0x0b, 0x84, 0xf9, 0x9d, 0x0b, 0x84, 0xf9, 0xad, 0x0b, 0x84, 0xf9, 0x86, 0x0b, 0x84, 0xf9, 0x96, 0x0b, 0x84, 0xf9, 0xa6, 0x0b, 0x84, 0xf9, 0xcf, 0x0b, 0x84, 0xf9, 0xdf, 0x0b, 0x84, 0xf9, 0xef, 0x0b, 0x84, 0xf9, 0xcd, 0x0b, 0x84, 0xf9, 0xdd, 0x0b, 0x84, 0xf9, 0xed, 0x0b, 0x84, 0xf9, 0xc6, 0x0b, 0x84, 0xf9, 0xd6, 0x0b, 0x84, 0xf9, 0xe6, 0x0b ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vld1.8 {d0}, [r4]" + - + asm_text: "vld1.8 {d0}, [r4:64]" + - + asm_text: "vld1.8 {d0}, [r4]!" + - + asm_text: "vld1.8 {d0}, [r4:64]!" + - + asm_text: "vld1.8 {d0}, [r4], r6" + - + asm_text: "vld1.8 {d0}, [r4:64], r6" + - + asm_text: "vld1.8 {d0, d1}, [r4]" + - + asm_text: "vld1.8 {d0, d1}, [r4:64]" + - + asm_text: "vld1.8 {d0, d1}, [r4:128]" + - + asm_text: "vld1.8 {d0, d1}, [r4]!" + - + asm_text: "vld1.8 {d0, d1}, [r4:64]!" + - + asm_text: "vld1.8 {d0, d1}, [r4:128]!" + - + asm_text: "vld1.8 {d0, d1}, [r4], r6" + - + asm_text: "vld1.8 {d0, d1}, [r4:64], r6" + - + asm_text: "vld1.8 {d0, d1}, [r4:128], r6" + - + asm_text: "vld1.8 {d0, d1, d2}, [r4]" + - + asm_text: "vld1.8 {d0, d1, d2}, [r4:64]" + - + asm_text: "vld1.8 {d0, d1, d2}, [r4]!" + - + asm_text: "vld1.8 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vld1.8 {d0, d1, d2}, [r4], r6" + - + asm_text: "vld1.8 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld1.8 {d0[2]}, [r4]" + - + asm_text: "vld1.8 {d0[2]}, [r4]!" + - + asm_text: "vld1.8 {d0[2]}, [r4], r6" + - + asm_text: "vld1.8 {d0[]}, [r4]" + - + asm_text: "vld1.8 {d0[]}, [r4]!" + - + asm_text: "vld1.8 {d0[]}, [r4], r6" + - + asm_text: "vld1.8 {d0[], d1[]}, [r4]" + - + asm_text: "vld1.8 {d0[], d1[]}, [r4]!" + - + asm_text: "vld1.8 {d0[], d1[]}, [r4], r6" + - + asm_text: "vld1.16 {d0}, [r4]" + - + asm_text: "vld1.16 {d0}, [r4:64]" + - + asm_text: "vld1.16 {d0}, [r4]!" + - + asm_text: "vld1.16 {d0}, [r4:64]!" + - + asm_text: "vld1.16 {d0}, [r4], r6" + - + asm_text: "vld1.16 {d0}, [r4:64], r6" + - + asm_text: "vld1.16 {d0, d1}, [r4]" + - + asm_text: "vld1.16 {d0, d1}, [r4:64]" + - + asm_text: "vld1.16 {d0, d1}, [r4:128]" + - + asm_text: "vld1.16 {d0, d1}, [r4]!" + - + asm_text: "vld1.16 {d0, d1}, [r4:64]!" + - + asm_text: "vld1.16 {d0, d1}, [r4:128]!" + - + asm_text: "vld1.16 {d0, d1}, [r4], r6" + - + asm_text: "vld1.16 {d0, d1}, [r4:64], r6" + - + asm_text: "vld1.16 {d0, d1}, [r4:128], r6" + - + asm_text: "vld1.16 {d0, d1, d2}, [r4]" + - + asm_text: "vld1.16 {d0, d1, d2}, [r4:64]" + - + asm_text: "vld1.16 {d0, d1, d2}, [r4]!" + - + asm_text: "vld1.16 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vld1.16 {d0, d1, d2}, [r4], r6" + - + asm_text: "vld1.16 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld1.16 {d0[2]}, [r4]" + - + asm_text: "vld1.16 {d0[2]}, [r4:16]" + - + asm_text: "vld1.16 {d0[2]}, [r4]!" + - + asm_text: "vld1.16 {d0[2]}, [r4:16]!" + - + asm_text: "vld1.16 {d0[2]}, [r4], r6" + - + asm_text: "vld1.16 {d0[2]}, [r4:16], r6" + - + asm_text: "vld1.16 {d0[]}, [r4]" + - + asm_text: "vld1.16 {d0[]}, [r4:16]" + - + asm_text: "vld1.16 {d0[]}, [r4]!" + - + asm_text: "vld1.16 {d0[]}, [r4:16]!" + - + asm_text: "vld1.16 {d0[]}, [r4], r6" + - + asm_text: "vld1.16 {d0[]}, [r4:16], r6" + - + asm_text: "vld1.16 {d0[], d1[]}, [r4]" + - + asm_text: "vld1.16 {d0[], d1[]}, [r4:16]" + - + asm_text: "vld1.16 {d0[], d1[]}, [r4]!" + - + asm_text: "vld1.16 {d0[], d1[]}, [r4:16]!" + - + asm_text: "vld1.16 {d0[], d1[]}, [r4], r6" + - + asm_text: "vld1.16 {d0[], d1[]}, [r4:16], r6" + - + asm_text: "vld1.32 {d0}, [r4]" + - + asm_text: "vld1.32 {d0}, [r4:64]" + - + asm_text: "vld1.32 {d0}, [r4]!" + - + asm_text: "vld1.32 {d0}, [r4:64]!" + - + asm_text: "vld1.32 {d0}, [r4], r6" + - + asm_text: "vld1.32 {d0}, [r4:64], r6" + - + asm_text: "vld1.32 {d0, d1}, [r4]" + - + asm_text: "vld1.32 {d0, d1}, [r4:64]" + - + asm_text: "vld1.32 {d0, d1}, [r4:128]" + - + asm_text: "vld1.32 {d0, d1}, [r4]!" + - + asm_text: "vld1.32 {d0, d1}, [r4:64]!" + - + asm_text: "vld1.32 {d0, d1}, [r4:128]!" + - + asm_text: "vld1.32 {d0, d1}, [r4], r6" + - + asm_text: "vld1.32 {d0, d1}, [r4:64], r6" + - + asm_text: "vld1.32 {d0, d1}, [r4:128], r6" + - + asm_text: "vld1.32 {d0, d1, d2}, [r4]" + - + asm_text: "vld1.32 {d0, d1, d2}, [r4:64]" + - + asm_text: "vld1.32 {d0, d1, d2}, [r4]!" + - + asm_text: "vld1.32 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vld1.32 {d0, d1, d2}, [r4], r6" + - + asm_text: "vld1.32 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld1.32 {d0[1]}, [r4]" + - + asm_text: "vld1.32 {d0[1]}, [r4:32]" + - + asm_text: "vld1.32 {d0[1]}, [r4]!" + - + asm_text: "vld1.32 {d0[1]}, [r4:32]!" + - + asm_text: "vld1.32 {d0[1]}, [r4], r6" + - + asm_text: "vld1.32 {d0[1]}, [r4:32], r6" + - + asm_text: "vld1.32 {d0[]}, [r4]" + - + asm_text: "vld1.32 {d0[]}, [r4:32]" + - + asm_text: "vld1.32 {d0[]}, [r4]!" + - + asm_text: "vld1.32 {d0[]}, [r4:32]!" + - + asm_text: "vld1.32 {d0[]}, [r4], r6" + - + asm_text: "vld1.32 {d0[]}, [r4:32], r6" + - + asm_text: "vld1.32 {d0[], d1[]}, [r4]" + - + asm_text: "vld1.32 {d0[], d1[]}, [r4:32]" + - + asm_text: "vld1.32 {d0[], d1[]}, [r4]!" + - + asm_text: "vld1.32 {d0[], d1[]}, [r4:32]!" + - + asm_text: "vld1.32 {d0[], d1[]}, [r4], r6" + - + asm_text: "vld1.32 {d0[], d1[]}, [r4:32], r6" + - + asm_text: "vld1.32 {d0[1]}, [r4]" + - + asm_text: "vld1.32 {d0[1]}, [r4:32]" + - + asm_text: "vld1.32 {d0[1]}, [r4]!" + - + asm_text: "vld1.32 {d0[1]}, [r4:32]!" + - + asm_text: "vld1.32 {d0[1]}, [r4], r6" + - + asm_text: "vld1.32 {d0[1]}, [r4:32], r6" + - + asm_text: "vld1.64 {d0}, [r4]" + - + asm_text: "vld1.64 {d0}, [r4:64]" + - + asm_text: "vld1.64 {d0}, [r4]!" + - + asm_text: "vld1.64 {d0}, [r4:64]!" + - + asm_text: "vld1.64 {d0}, [r4], r6" + - + asm_text: "vld1.64 {d0}, [r4:64], r6" + - + asm_text: "vld1.64 {d0, d1}, [r4]" + - + asm_text: "vld1.64 {d0, d1}, [r4:64]" + - + asm_text: "vld1.64 {d0, d1}, [r4:128]" + - + asm_text: "vld1.64 {d0, d1}, [r4]!" + - + asm_text: "vld1.64 {d0, d1}, [r4:64]!" + - + asm_text: "vld1.64 {d0, d1}, [r4:128]!" + - + asm_text: "vld1.64 {d0, d1}, [r4], r6" + - + asm_text: "vld1.64 {d0, d1}, [r4:64], r6" + - + asm_text: "vld1.64 {d0, d1}, [r4:128], r6" + - + asm_text: "vld1.64 {d0, d1, d2}, [r4]" + - + asm_text: "vld1.64 {d0, d1, d2}, [r4:64]" + - + asm_text: "vld1.64 {d0, d1, d2}, [r4]!" + - + asm_text: "vld1.64 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vld1.64 {d0, d1, d2}, [r4], r6" + - + asm_text: "vld1.64 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld2.8 {d0, d1}, [r4]" + - + asm_text: "vld2.8 {d0, d1}, [r4:64]" + - + asm_text: "vld2.8 {d0, d1}, [r4:128]" + - + asm_text: "vld2.8 {d0, d1}, [r4]!" + - + asm_text: "vld2.8 {d0, d1}, [r4:64]!" + - + asm_text: "vld2.8 {d0, d1}, [r4:128]!" + - + asm_text: "vld2.8 {d0, d1}, [r4], r6" + - + asm_text: "vld2.8 {d0, d1}, [r4:64], r6" + - + asm_text: "vld2.8 {d0, d1}, [r4:128], r6" + - + asm_text: "vld2.8 {d0, d2}, [r4]" + - + asm_text: "vld2.8 {d0, d2}, [r4:64]" + - + asm_text: "vld2.8 {d0, d2}, [r4:128]" + - + asm_text: "vld2.8 {d0, d2}, [r4]!" + - + asm_text: "vld2.8 {d0, d2}, [r4:64]!" + - + asm_text: "vld2.8 {d0, d2}, [r4:128]!" + - + asm_text: "vld2.8 {d0, d2}, [r4], r6" + - + asm_text: "vld2.8 {d0, d2}, [r4:64], r6" + - + asm_text: "vld2.8 {d0, d2}, [r4:128], r6" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld2.8 {d0[2], d1[2]}, [r4]" + - + asm_text: "vld2.8 {d0[2], d1[2]}, [r4:16]" + - + asm_text: "vld2.8 {d0[2], d1[2]}, [r4]!" + - + asm_text: "vld2.8 {d0[2], d1[2]}, [r4:16]!" + - + asm_text: "vld2.8 {d0[2], d1[2]}, [r4], r6" + - + asm_text: "vld2.8 {d0[2], d1[2]}, [r4:16], r6" + - + asm_text: "vld2.8 {d0[], d1[]}, [r4]" + - + asm_text: "vld2.8 {d0[], d1[]}, [r4:16]" + - + asm_text: "vld2.8 {d0[], d1[]}, [r4]!" + - + asm_text: "vld2.8 {d0[], d1[]}, [r4:16]!" + - + asm_text: "vld2.8 {d0[], d1[]}, [r4], r6" + - + asm_text: "vld2.8 {d0[], d1[]}, [r4:16], r6" + - + asm_text: "vld2.8 {d0[], d2[]}, [r4]" + - + asm_text: "vld2.8 {d0[], d2[]}, [r4:16]" + - + asm_text: "vld2.8 {d0[], d2[]}, [r4]!" + - + asm_text: "vld2.8 {d0[], d2[]}, [r4:16]!" + - + asm_text: "vld2.8 {d0[], d2[]}, [r4], r6" + - + asm_text: "vld2.8 {d0[], d2[]}, [r4:16], r6" + - + asm_text: "vld2.16 {d0, d1}, [r4]" + - + asm_text: "vld2.16 {d0, d1}, [r4:64]" + - + asm_text: "vld2.16 {d0, d1}, [r4:128]" + - + asm_text: "vld2.16 {d0, d1}, [r4]!" + - + asm_text: "vld2.16 {d0, d1}, [r4:64]!" + - + asm_text: "vld2.16 {d0, d1}, [r4:128]!" + - + asm_text: "vld2.16 {d0, d1}, [r4], r6" + - + asm_text: "vld2.16 {d0, d1}, [r4:64], r6" + - + asm_text: "vld2.16 {d0, d1}, [r4:128], r6" + - + asm_text: "vld2.16 {d0, d2}, [r4]" + - + asm_text: "vld2.16 {d0, d2}, [r4:64]" + - + asm_text: "vld2.16 {d0, d2}, [r4:128]" + - + asm_text: "vld2.16 {d0, d2}, [r4]!" + - + asm_text: "vld2.16 {d0, d2}, [r4:64]!" + - + asm_text: "vld2.16 {d0, d2}, [r4:128]!" + - + asm_text: "vld2.16 {d0, d2}, [r4], r6" + - + asm_text: "vld2.16 {d0, d2}, [r4:64], r6" + - + asm_text: "vld2.16 {d0, d2}, [r4:128], r6" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld2.16 {d0[2], d1[2]}, [r4]" + - + asm_text: "vld2.16 {d0[2], d1[2]}, [r4:32]" + - + asm_text: "vld2.16 {d0[2], d1[2]}, [r4]!" + - + asm_text: "vld2.16 {d0[2], d1[2]}, [r4:32]!" + - + asm_text: "vld2.16 {d0[2], d1[2]}, [r4], r6" + - + asm_text: "vld2.16 {d0[2], d1[2]}, [r4:32], r6" + - + asm_text: "vld2.16 {d0[2], d2[2]}, [r4]" + - + asm_text: "vld2.16 {d0[2], d2[2]}, [r4:32]" + - + asm_text: "vld2.16 {d0[2], d2[2]}, [r4]!" + - + asm_text: "vld2.16 {d0[2], d2[2]}, [r4:32]!" + - + asm_text: "vld2.16 {d0[2], d2[2]}, [r4], r6" + - + asm_text: "vld2.16 {d0[2], d2[2]}, [r4:32], r6" + - + asm_text: "vld2.16 {d0[], d1[]}, [r4]" + - + asm_text: "vld2.16 {d0[], d1[]}, [r4:32]" + - + asm_text: "vld2.16 {d0[], d1[]}, [r4]!" + - + asm_text: "vld2.16 {d0[], d1[]}, [r4:32]!" + - + asm_text: "vld2.16 {d0[], d1[]}, [r4], r6" + - + asm_text: "vld2.16 {d0[], d1[]}, [r4:32], r6" + - + asm_text: "vld2.16 {d0[], d2[]}, [r4]" + - + asm_text: "vld2.16 {d0[], d2[]}, [r4:32]" + - + asm_text: "vld2.16 {d0[], d2[]}, [r4]!" + - + asm_text: "vld2.16 {d0[], d2[]}, [r4:32]!" + - + asm_text: "vld2.16 {d0[], d2[]}, [r4], r6" + - + asm_text: "vld2.16 {d0[], d2[]}, [r4:32], r6" + - + asm_text: "vld2.32 {d0, d1}, [r4]" + - + asm_text: "vld2.32 {d0, d1}, [r4:64]" + - + asm_text: "vld2.32 {d0, d1}, [r4:128]" + - + asm_text: "vld2.32 {d0, d1}, [r4]!" + - + asm_text: "vld2.32 {d0, d1}, [r4:64]!" + - + asm_text: "vld2.32 {d0, d1}, [r4:128]!" + - + asm_text: "vld2.32 {d0, d1}, [r4], r6" + - + asm_text: "vld2.32 {d0, d1}, [r4:64], r6" + - + asm_text: "vld2.32 {d0, d1}, [r4:128], r6" + - + asm_text: "vld2.32 {d0, d2}, [r4]" + - + asm_text: "vld2.32 {d0, d2}, [r4:64]" + - + asm_text: "vld2.32 {d0, d2}, [r4:128]" + - + asm_text: "vld2.32 {d0, d2}, [r4]!" + - + asm_text: "vld2.32 {d0, d2}, [r4:64]!" + - + asm_text: "vld2.32 {d0, d2}, [r4:128]!" + - + asm_text: "vld2.32 {d0, d2}, [r4], r6" + - + asm_text: "vld2.32 {d0, d2}, [r4:64], r6" + - + asm_text: "vld2.32 {d0, d2}, [r4:128], r6" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld2.32 {d0[1], d1[1]}, [r4]" + - + asm_text: "vld2.32 {d0[1], d1[1]}, [r4:64]" + - + asm_text: "vld2.32 {d0[1], d1[1]}, [r4]!" + - + asm_text: "vld2.32 {d0[1], d1[1]}, [r4:64]!" + - + asm_text: "vld2.32 {d0[1], d1[1]}, [r4], r6" + - + asm_text: "vld2.32 {d0[1], d1[1]}, [r4:64], r6" + - + asm_text: "vld2.32 {d0[1], d2[1]}, [r4]" + - + asm_text: "vld2.32 {d0[1], d2[1]}, [r4:64]" + - + asm_text: "vld2.32 {d0[1], d2[1]}, [r4]!" + - + asm_text: "vld2.32 {d0[1], d2[1]}, [r4:64]!" + - + asm_text: "vld2.32 {d0[1], d2[1]}, [r4], r6" + - + asm_text: "vld2.32 {d0[1], d2[1]}, [r4:64], r6" + - + asm_text: "vld2.32 {d0[], d1[]}, [r4]" + - + asm_text: "vld2.32 {d0[], d1[]}, [r4:64]" + - + asm_text: "vld2.32 {d0[], d1[]}, [r4]!" + - + asm_text: "vld2.32 {d0[], d1[]}, [r4:64]!" + - + asm_text: "vld2.32 {d0[], d1[]}, [r4], r6" + - + asm_text: "vld2.32 {d0[], d1[]}, [r4:64], r6" + - + asm_text: "vld2.32 {d0[], d2[]}, [r4]" + - + asm_text: "vld2.32 {d0[], d2[]}, [r4:64]" + - + asm_text: "vld2.32 {d0[], d2[]}, [r4]!" + - + asm_text: "vld2.32 {d0[], d2[]}, [r4:64]!" + - + asm_text: "vld2.32 {d0[], d2[]}, [r4], r6" + - + asm_text: "vld2.32 {d0[], d2[]}, [r4:64], r6" + - + asm_text: "vld3.8 {d0, d1, d2}, [r4]" + - + asm_text: "vld3.8 {d0, d1, d2}, [r4:64]" + - + asm_text: "vld3.8 {d0, d1, d2}, [r4]!" + - + asm_text: "vld3.8 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vld3.8 {d0, d1, d2}, [r4], r6" + - + asm_text: "vld3.8 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vld3.8 {d0, d2, d4}, [r4]" + - + asm_text: "vld3.8 {d0, d2, d4}, [r4:64]" + - + asm_text: "vld3.8 {d0, d2, d4}, [r4]!" + - + asm_text: "vld3.8 {d0, d2, d4}, [r4:64]!" + - + asm_text: "vld3.8 {d0, d2, d4}, [r4], r6" + - + asm_text: "vld3.8 {d0, d2, d4}, [r4:64], r6" + - + asm_text: "vld3.8 {d0[1], d1[1], d2[1]}, [r4]" + - + asm_text: "vld3.8 {d0[1], d1[1], d2[1]}, [r4]!" + - + asm_text: "vld3.8 {d0[1], d1[1], d2[1]}, [r4], r6" + - + asm_text: "vld3.8 {d0[], d1[], d2[]}, [r4]" + - + asm_text: "vld3.8 {d0[], d1[], d2[]}, [r4]!" + - + asm_text: "vld3.8 {d0[], d1[], d2[]}, [r4], r6" + - + asm_text: "vld3.8 {d0[], d2[], d4[]}, [r4]" + - + asm_text: "vld3.8 {d0[], d2[], d4[]}, [r4]!" + - + asm_text: "vld3.8 {d0[], d2[], d4[]}, [r4], r6" + - + asm_text: "vld3.16 {d0, d1, d2}, [r4]" + - + asm_text: "vld3.16 {d0, d1, d2}, [r4:64]" + - + asm_text: "vld3.16 {d0, d1, d2}, [r4]!" + - + asm_text: "vld3.16 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vld3.16 {d0, d1, d2}, [r4], r6" + - + asm_text: "vld3.16 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vld3.16 {d0, d2, d4}, [r4]" + - + asm_text: "vld3.16 {d0, d2, d4}, [r4:64]" + - + asm_text: "vld3.16 {d0, d2, d4}, [r4]!" + - + asm_text: "vld3.16 {d0, d2, d4}, [r4:64]!" + - + asm_text: "vld3.16 {d0, d2, d4}, [r4], r6" + - + asm_text: "vld3.16 {d0, d2, d4}, [r4:64], r6" + - + asm_text: "vld3.16 {d0[1], d1[1], d2[1]}, [r4]" + - + asm_text: "vld3.16 {d0[1], d1[1], d2[1]}, [r4]!" + - + asm_text: "vld3.16 {d0[1], d1[1], d2[1]}, [r4], r6" + - + asm_text: "vld3.16 {d0[1], d2[1], d4[1]}, [r4]" + - + asm_text: "vld3.16 {d0[1], d2[1], d4[1]}, [r4]!" + - + asm_text: "vld3.16 {d0[1], d2[1], d4[1]}, [r4], r6" + - + asm_text: "vld3.16 {d0[], d1[], d2[]}, [r4]" + - + asm_text: "vld3.16 {d0[], d1[], d2[]}, [r4]!" + - + asm_text: "vld3.16 {d0[], d1[], d2[]}, [r4], r6" + - + asm_text: "vld3.16 {d0[], d2[], d4[]}, [r4]" + - + asm_text: "vld3.16 {d0[], d2[], d4[]}, [r4]!" + - + asm_text: "vld3.16 {d0[], d2[], d4[]}, [r4], r6" + - + asm_text: "vld3.32 {d0, d1, d2}, [r4]" + - + asm_text: "vld3.32 {d0, d1, d2}, [r4:64]" + - + asm_text: "vld3.32 {d0, d1, d2}, [r4]!" + - + asm_text: "vld3.32 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vld3.32 {d0, d1, d2}, [r4], r6" + - + asm_text: "vld3.32 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vld3.32 {d0, d2, d4}, [r4]" + - + asm_text: "vld3.32 {d0, d2, d4}, [r4:64]" + - + asm_text: "vld3.32 {d0, d2, d4}, [r4]!" + - + asm_text: "vld3.32 {d0, d2, d4}, [r4:64]!" + - + asm_text: "vld3.32 {d0, d2, d4}, [r4], r6" + - + asm_text: "vld3.32 {d0, d2, d4}, [r4:64], r6" + - + asm_text: "vld3.32 {d0[1], d1[1], d2[1]}, [r4]" + - + asm_text: "vld3.32 {d0[1], d1[1], d2[1]}, [r4]!" + - + asm_text: "vld3.32 {d0[1], d1[1], d2[1]}, [r4], r6" + - + asm_text: "vld3.32 {d0[1], d2[1], d4[1]}, [r4]" + - + asm_text: "vld3.32 {d0[1], d2[1], d4[1]}, [r4]!" + - + asm_text: "vld3.32 {d0[1], d2[1], d4[1]}, [r4], r6" + - + asm_text: "vld3.32 {d0[], d1[], d2[]}, [r4]" + - + asm_text: "vld3.32 {d0[], d1[], d2[]}, [r4]!" + - + asm_text: "vld3.32 {d0[], d1[], d2[]}, [r4], r6" + - + asm_text: "vld3.32 {d0[], d2[], d4[]}, [r4]" + - + asm_text: "vld3.32 {d0[], d2[], d4[]}, [r4]!" + - + asm_text: "vld3.32 {d0[], d2[], d4[]}, [r4], r6" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4]" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:64]" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:128]" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:256]" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4]!" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:64]!" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:128]!" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:256]!" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4], r6" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:64], r6" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:128], r6" + - + asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:256], r6" + - + asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]" + - + asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]" + - + asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]!" + - + asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!" + - + asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6" + - + asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6" + - + asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4]" + - + asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]" + - + asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4]!" + - + asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]!" + - + asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4], r6" + - + asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32], r6" + - + asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4]" + - + asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32]" + - + asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4]!" + - + asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32]!" + - + asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4], r6" + - + asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r6" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4]" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:64]" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:128]" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:256]" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4]!" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:64]!" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:128]!" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:256]!" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4], r6" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:64], r6" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:128], r6" + - + asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:256], r6" + - + asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]" + - + asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]" + - + asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]!" + - + asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!" + - + asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6" + - + asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6" + - + asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]" + - + asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]" + - + asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]!" + - + asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!" + - + asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6" + - + asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6" + - + asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4]" + - + asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]" + - + asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4]!" + - + asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]!" + - + asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4], r6" + - + asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64], r6" + - + asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4]" + - + asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64]" + - + asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4]!" + - + asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64]!" + - + asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4], r6" + - + asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r6" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4]" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:64]" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:128]" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:256]" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4]!" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:64]!" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:128]!" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:256]!" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4], r6" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:64], r6" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:128], r6" + - + asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:256], r6" + - + asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]" + - + asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]" + - + asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]" + - + asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]!" + - + asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!" + - + asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!" + - + asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6" + - + asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6" + - + asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6" + - + asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]" + - + asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]" + - + asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]" + - + asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]!" + - + asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!" + - + asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!" + - + asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6" + - + asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6" + - + asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6" + - + asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4]" + - + asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64]" + - + asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]" + - + asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4]!" + - + asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64]!" + - + asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]!" + - + asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4], r6" + - + asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64], r6" + - + asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128], r6" + - + asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4]" + - + asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64]" + - + asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128]" + - + asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4]!" + - + asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64]!" + - + asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128]!" + - + asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4], r6" + - + asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64], r6" + - + asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r6" + - + asm_text: "vst1.8 {d0}, [r4]" + - + asm_text: "vst1.8 {d0}, [r4:64]" + - + asm_text: "vst1.8 {d0}, [r4]!" + - + asm_text: "vst1.8 {d0}, [r4:64]!" + - + asm_text: "vst1.8 {d0}, [r4], r6" + - + asm_text: "vst1.8 {d0}, [r4:64], r6" + - + asm_text: "vst1.8 {d0, d1}, [r4]" + - + asm_text: "vst1.8 {d0, d1}, [r4:64]" + - + asm_text: "vst1.8 {d0, d1}, [r4:128]" + - + asm_text: "vst1.8 {d0, d1}, [r4]!" + - + asm_text: "vst1.8 {d0, d1}, [r4:64]!" + - + asm_text: "vst1.8 {d0, d1}, [r4:128]!" + - + asm_text: "vst1.8 {d0, d1}, [r4], r6" + - + asm_text: "vst1.8 {d0, d1}, [r4:64], r6" + - + asm_text: "vst1.8 {d0, d1}, [r4:128], r6" + - + asm_text: "vst1.8 {d0, d1, d2}, [r4]" + - + asm_text: "vst1.8 {d0, d1, d2}, [r4:64]" + - + asm_text: "vst1.8 {d0, d1, d2}, [r4]!" + - + asm_text: "vst1.8 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vst1.8 {d0, d1, d2}, [r4], r6" + - + asm_text: "vst1.8 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vst1.8 {d0[2]}, [r4]" + - + asm_text: "vst1.8 {d0[2]}, [r4]!" + - + asm_text: "vst1.8 {d0[2]}, [r4], r6" + - + asm_text: "vst1.16 {d0}, [r4]" + - + asm_text: "vst1.16 {d0}, [r4:64]" + - + asm_text: "vst1.16 {d0}, [r4]!" + - + asm_text: "vst1.16 {d0}, [r4:64]!" + - + asm_text: "vst1.16 {d0}, [r4], r6" + - + asm_text: "vst1.16 {d0}, [r4:64], r6" + - + asm_text: "vst1.16 {d0, d1}, [r4]" + - + asm_text: "vst1.16 {d0, d1}, [r4:64]" + - + asm_text: "vst1.16 {d0, d1}, [r4:128]" + - + asm_text: "vst1.16 {d0, d1}, [r4]!" + - + asm_text: "vst1.16 {d0, d1}, [r4:64]!" + - + asm_text: "vst1.16 {d0, d1}, [r4:128]!" + - + asm_text: "vst1.16 {d0, d1}, [r4], r6" + - + asm_text: "vst1.16 {d0, d1}, [r4:64], r6" + - + asm_text: "vst1.16 {d0, d1}, [r4:128], r6" + - + asm_text: "vst1.16 {d0, d1, d2}, [r4]" + - + asm_text: "vst1.16 {d0, d1, d2}, [r4:64]" + - + asm_text: "vst1.16 {d0, d1, d2}, [r4]!" + - + asm_text: "vst1.16 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vst1.16 {d0, d1, d2}, [r4], r6" + - + asm_text: "vst1.16 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vst1.16 {d0[2]}, [r4]" + - + asm_text: "vst1.16 {d0[2]}, [r4:16]" + - + asm_text: "vst1.16 {d0[2]}, [r4]!" + - + asm_text: "vst1.16 {d0[2]}, [r4:16]!" + - + asm_text: "vst1.16 {d0[2]}, [r4], r6" + - + asm_text: "vst1.16 {d0[2]}, [r4:16], r6" + - + asm_text: "vst1.32 {d0}, [r4]" + - + asm_text: "vst1.32 {d0}, [r4:64]" + - + asm_text: "vst1.32 {d0}, [r4]!" + - + asm_text: "vst1.32 {d0}, [r4:64]!" + - + asm_text: "vst1.32 {d0}, [r4], r6" + - + asm_text: "vst1.32 {d0}, [r4:64], r6" + - + asm_text: "vst1.32 {d0, d1}, [r4]" + - + asm_text: "vst1.32 {d0, d1}, [r4:64]" + - + asm_text: "vst1.32 {d0, d1}, [r4:128]" + - + asm_text: "vst1.32 {d0, d1}, [r4]!" + - + asm_text: "vst1.32 {d0, d1}, [r4:64]!" + - + asm_text: "vst1.32 {d0, d1}, [r4:128]!" + - + asm_text: "vst1.32 {d0, d1}, [r4], r6" + - + asm_text: "vst1.32 {d0, d1}, [r4:64], r6" + - + asm_text: "vst1.32 {d0, d1}, [r4:128], r6" + - + asm_text: "vst1.32 {d0, d1, d2}, [r4]" + - + asm_text: "vst1.32 {d0, d1, d2}, [r4:64]" + - + asm_text: "vst1.32 {d0, d1, d2}, [r4]!" + - + asm_text: "vst1.32 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vst1.32 {d0, d1, d2}, [r4], r6" + - + asm_text: "vst1.32 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vst1.32 {d0[1]}, [r4]" + - + asm_text: "vst1.32 {d0[1]}, [r4:32]" + - + asm_text: "vst1.32 {d0[1]}, [r4]!" + - + asm_text: "vst1.32 {d0[1]}, [r4:32]!" + - + asm_text: "vst1.32 {d0[1]}, [r4], r6" + - + asm_text: "vst1.32 {d0[1]}, [r4:32], r6" + - + asm_text: "vst1.64 {d0}, [r4]" + - + asm_text: "vst1.64 {d0}, [r4:64]" + - + asm_text: "vst1.64 {d0}, [r4]!" + - + asm_text: "vst1.64 {d0}, [r4:64]!" + - + asm_text: "vst1.64 {d0}, [r4], r6" + - + asm_text: "vst1.64 {d0}, [r4:64], r6" + - + asm_text: "vst1.64 {d0, d1}, [r4]" + - + asm_text: "vst1.64 {d0, d1}, [r4:64]" + - + asm_text: "vst1.64 {d0, d1}, [r4:128]" + - + asm_text: "vst1.64 {d0, d1}, [r4]!" + - + asm_text: "vst1.64 {d0, d1}, [r4:64]!" + - + asm_text: "vst1.64 {d0, d1}, [r4:128]!" + - + asm_text: "vst1.64 {d0, d1}, [r4], r6" + - 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d2, d3}, [r4:256], r6" + - + asm_text: "vst2.8 {d0, d1}, [r4]" + - + asm_text: "vst2.8 {d0, d1}, [r4:64]" + - + asm_text: "vst2.8 {d0, d1}, [r4:128]" + - + asm_text: "vst2.8 {d0, d1}, [r4]!" + - + asm_text: "vst2.8 {d0, d1}, [r4:64]!" + - + asm_text: "vst2.8 {d0, d1}, [r4:128]!" + - + asm_text: "vst2.8 {d0, d1}, [r4], r6" + - + asm_text: "vst2.8 {d0, d1}, [r4:64], r6" + - + asm_text: "vst2.8 {d0, d1}, [r4:128], r6" + - + asm_text: "vst2.8 {d0, d2}, [r4]" + - + asm_text: "vst2.8 {d0, d2}, [r4:64]" + - + asm_text: "vst2.8 {d0, d2}, [r4:128]" + - + asm_text: "vst2.8 {d0, d2}, [r4]!" + - + asm_text: "vst2.8 {d0, d2}, [r4:64]!" + - + asm_text: "vst2.8 {d0, d2}, [r4:128]!" + - + asm_text: "vst2.8 {d0, d2}, [r4], r6" + - + asm_text: "vst2.8 {d0, d2}, [r4:64], r6" + - + asm_text: "vst2.8 {d0, d2}, [r4:128], r6" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vst2.8 {d0[2], d1[2]}, [r4]" + - + asm_text: "vst2.8 {d0[2], d1[2]}, [r4:16]" + - + asm_text: "vst2.8 {d0[2], d1[2]}, [r4]!" + - + asm_text: "vst2.8 {d0[2], d1[2]}, [r4:16]!" + - + asm_text: "vst2.8 {d0[2], d1[2]}, [r4], r6" + - + asm_text: "vst2.8 {d0[2], d1[2]}, [r4:16], r6" + - + asm_text: "vst2.32 {d0, d1}, [r4]" + - + asm_text: "vst2.32 {d0, d1}, [r4:64]" + - + asm_text: "vst2.32 {d0, d1}, [r4:128]" + - + asm_text: "vst2.32 {d0, d1}, [r4]!" + - + asm_text: "vst2.32 {d0, d1}, [r4:64]!" + - + asm_text: "vst2.32 {d0, d1}, [r4:128]!" + - + asm_text: "vst2.32 {d0, d1}, [r4], r6" + - + asm_text: "vst2.32 {d0, d1}, [r4:64], r6" + - + asm_text: "vst2.32 {d0, d1}, [r4:128], r6" + - + asm_text: "vst2.32 {d0, d2}, [r4]" + - + asm_text: "vst2.32 {d0, d2}, [r4:64]" + - + asm_text: "vst2.32 {d0, d2}, [r4:128]" + - + asm_text: "vst2.32 {d0, d2}, [r4]!" + - + asm_text: "vst2.32 {d0, d2}, [r4:64]!" + - + asm_text: "vst2.32 {d0, d2}, [r4:128]!" + - + asm_text: "vst2.32 {d0, d2}, [r4], r6" + - + asm_text: "vst2.32 {d0, d2}, [r4:64], r6" + - + asm_text: "vst2.32 {d0, d2}, [r4:128], r6" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vst2.32 {d0[1], d1[1]}, [r4]" + - + asm_text: "vst2.32 {d0[1], d1[1]}, [r4:64]" + - + asm_text: "vst2.32 {d0[1], d1[1]}, [r4]!" + - + asm_text: "vst2.32 {d0[1], d1[1]}, [r4:64]!" + - + asm_text: "vst2.32 {d0[1], d1[1]}, [r4], r6" + - + asm_text: "vst2.32 {d0[1], d1[1]}, [r4:64], r6" + - + asm_text: "vst2.32 {d0[1], d2[1]}, [r4]" + - + asm_text: "vst2.32 {d0[1], d2[1]}, [r4:64]" + - + asm_text: "vst2.32 {d0[1], d2[1]}, [r4]!" + - + asm_text: "vst2.32 {d0[1], d2[1]}, [r4:64]!" + - + asm_text: "vst2.32 {d0[1], d2[1]}, [r4], r6" + - + asm_text: "vst2.32 {d0[1], d2[1]}, [r4:64], r6" + - + asm_text: "vst3.8 {d0, d1, d2}, [r4]" + - + asm_text: "vst3.8 {d0, d1, d2}, [r4:64]" + - + asm_text: "vst3.8 {d0, d1, d2}, [r4]!" + - + asm_text: "vst3.8 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vst3.8 {d0, d1, d2}, [r4], r6" + - + asm_text: "vst3.8 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vst3.8 {d0, d2, d4}, [r4]" + - + asm_text: "vst3.8 {d0, d2, d4}, [r4:64]" + - + asm_text: "vst3.8 {d0, d2, d4}, [r4]!" + - + asm_text: "vst3.8 {d0, d2, d4}, [r4:64]!" + - + asm_text: "vst3.8 {d0, d2, d4}, [r4], r6" + - + asm_text: "vst3.8 {d0, d2, d4}, [r4:64], r6" + - + asm_text: "vst3.8 {d0[1], d1[1], d2[1]}, [r4]" + - + asm_text: "vst3.8 {d0[1], d1[1], d2[1]}, [r4]!" + - + asm_text: "vst3.8 {d0[1], d1[1], d2[1]}, [r4], r6" + - + asm_text: "vst3.16 {d0, d1, d2}, [r4]" + - + asm_text: "vst3.16 {d0, d1, d2}, [r4:64]" + - + asm_text: "vst3.16 {d0, d1, d2}, [r4]!" + - + asm_text: "vst3.16 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vst3.16 {d0, d1, d2}, [r4], r6" + - + asm_text: "vst3.16 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vst3.16 {d0, d2, d4}, [r4]" + - + asm_text: "vst3.16 {d0, d2, d4}, [r4:64]" + - + asm_text: "vst3.16 {d0, d2, d4}, [r4]!" + - + asm_text: "vst3.16 {d0, d2, d4}, [r4:64]!" + - + asm_text: "vst3.16 {d0, d2, d4}, [r4], r6" + - + asm_text: "vst3.16 {d0, d2, d4}, [r4:64], r6" + - + asm_text: "vst3.16 {d0[1], d1[1], d2[1]}, [r4]" + - + asm_text: "vst3.16 {d0[1], d1[1], d2[1]}, [r4]!" + - + asm_text: "vst3.16 {d0[1], d1[1], d2[1]}, [r4], r6" + - + asm_text: "vst3.16 {d0[1], d2[1], d4[1]}, [r4]" + - + asm_text: "vst3.16 {d0[1], d2[1], d4[1]}, [r4]!" + - + asm_text: "vst3.16 {d0[1], d2[1], d4[1]}, [r4], r6" + - + asm_text: "vst3.32 {d0, d1, d2}, [r4]" + - + asm_text: "vst3.32 {d0, d1, d2}, [r4:64]" + - + asm_text: "vst3.32 {d0, d1, d2}, [r4]!" + - + asm_text: "vst3.32 {d0, d1, d2}, [r4:64]!" + - + asm_text: "vst3.32 {d0, d1, d2}, [r4], r6" + - + asm_text: "vst3.32 {d0, d1, d2}, [r4:64], r6" + - + asm_text: "vst3.32 {d0, d2, d4}, [r4]" + - + asm_text: "vst3.32 {d0, d2, d4}, [r4:64]" + - + asm_text: "vst3.32 {d0, d2, d4}, [r4]!" + - + asm_text: "vst3.32 {d0, d2, d4}, [r4:64]!" + - + asm_text: "vst3.32 {d0, d2, d4}, [r4], r6" + - + asm_text: "vst3.32 {d0, d2, d4}, [r4:64], r6" + - + asm_text: "vst3.32 {d0[1], d1[1], d2[1]}, [r4]" + - + asm_text: "vst3.32 {d0[1], d1[1], d2[1]}, [r4]!" + - + asm_text: "vst3.32 {d0[1], d1[1], d2[1]}, [r4], r6" + - + asm_text: "vst3.32 {d0[1], d2[1], d4[1]}, [r4]" + - + asm_text: "vst3.32 {d0[1], d2[1], d4[1]}, [r4]!" + - + asm_text: "vst3.32 {d0[1], d2[1], d4[1]}, [r4], r6" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4]" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:64]" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:128]" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:256]" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4]!" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:64]!" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:128]!" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:256]!" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4], r6" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:64], r6" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:128], r6" + - + asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:256], r6" + - + asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]" + - + asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]" + - + asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]!" + - + asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!" + - + asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6" + - + asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4]" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:64]" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:128]" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:256]" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4]!" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:64]!" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:128]!" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:256]!" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4], r6" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:64], r6" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:128], r6" + - + asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:256], r6" + - + asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]" + - + asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]" + - + asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]!" + - + asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!" + - + asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6" + - + asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6" + - + asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]" + - + asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]" + - + asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]!" + - + asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!" + - + asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6" + - + asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4]" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:64]" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:128]" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:256]" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4]!" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:64]!" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:128]!" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:256]!" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4], r6" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:64], r6" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:128], r6" + - + asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:256], r6" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4]" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:64]" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:128]" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:256]" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4]!" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:64]!" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:128]!" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:256]!" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4], r6" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:64], r6" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:128], r6" + - + asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:256], r6" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]!" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]!" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]!" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6" + - + asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]!" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6" + - + asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6" diff --git a/tests/MC/ARM/neon-vst-encoding.s.yaml b/tests/MC/ARM/neon-vst-encoding.s.yaml new file mode 100644 index 0000000000..7988717f70 --- /dev/null +++ b/tests/MC/ARM/neon-vst-encoding.s.yaml @@ -0,0 +1,246 @@ +test_cases: + - + input: + bytes: [ 0x1f, 0x07, 0x40, 0xf4, 0x4f, 0x07, 0x40, 0xf4, 0x8f, 0x07, 0x40, 0xf4, 0xcf, 0x07, 0x40, 0xf4, 0x1f, 0x0a, 0x40, 0xf4, 0x6f, 0x0a, 0x40, 0xf4, 0x8f, 0x0a, 0x40, 0xf4, 0xcf, 0x0a, 0x40, 0xf4, 0x1f, 0x06, 0x40, 0xf4, 0x1d, 0x06, 0x40, 0xf4, 0x03, 0x06, 0x40, 0xf4, 0x1f, 0x02, 0x40, 0xf4, 0x5d, 0x02, 0x41, 0xf4, 0xc2, 0x02, 0x43, 0xf4, 0x1f, 0x08, 0x40, 0xf4, 0x6f, 0x08, 0x40, 0xf4, 0x8f, 0x08, 0x40, 0xf4, 0x1f, 0x03, 0x40, 0xf4, 0x6f, 0x03, 0x40, 0xf4, 0xbf, 0x03, 0x40, 0xf4, 0x1d, 0x08, 0x40, 0xf4, 0x6d, 0xe8, 0x40, 0xf4, 0x8d, 0xe8, 0x00, 0xf4, 0x1d, 0x03, 0x40, 0xf4, 0x6d, 0x23, 0x40, 0xf4, 0xbd, 0x83, 0x00, 0xf4, 0x0f, 0x04, 0x41, 0xf4, 0x4f, 0x64, 0x02, 0xf4, 0x8f, 0x14, 0x03, 0xf4, 0x1f, 0x05, 0x40, 0xf4, 0x4f, 0xb5, 0x44, 0xf4, 0x8f, 0x65, 0x05, 0xf4, 0x01, 0xc4, 0x06, 0xf4, 0x42, 0xb4, 0x07, 0xf4, 0x83, 0x24, 0x08, 0xf4, 0x04, 0x45, 0x09, 0xf4, 0x44, 0xe5, 0x09, 0xf4, 0x85, 0x05, 0x4a, 0xf4, 0x0d, 0x64, 0x08, 0xf4, 0x4d, 0x94, 0x07, 0xf4, 0x8d, 0x14, 0x06, 0xf4, 0x1d, 0x05, 0x40, 0xf4, 0x4d, 0x45, 0x45, 0xf4, 0x8d, 0x55, 0x04, 0xf4, 0x1f, 0x00, 0x41, 0xf4, 0x6f, 0x00, 0x42, 0xf4, 0xbf, 0x00, 0x43, 0xf4, 0x3f, 0x11, 0x45, 0xf4, 0x4f, 0x11, 0x47, 0xf4, 0x8f, 0x01, 0x48, 0xf4, 0x1d, 0x00, 0x41, 0xf4, 0x6d, 0x00, 0x42, 0xf4, 0xbd, 0x00, 0x43, 0xf4, 0x3d, 0x11, 0x45, 0xf4, 0x4d, 0x11, 0x47, 0xf4, 0x8d, 0x01, 0x48, 0xf4, 0x18, 0x00, 0x41, 0xf4, 0x47, 0x00, 0x42, 0xf4, 0x95, 0x00, 0x43, 0xf4, 0x32, 0x01, 0x44, 0xf4, 0x43, 0x01, 0x46, 0xf4, 0x84, 0x11, 0x49, 0xf4, 0x3f, 0x01, 0xc0, 0xf4, 0x5f, 0x05, 0xc0, 0xf4, 0x8f, 0x09, 0xc0, 0xf4, 0x6f, 0x15, 0xc0, 0xf4, 0x5f, 0x19, 0xc0, 0xf4, 0x83, 0x21, 0x82, 0xf4, 0x8d, 0x21, 0x82, 0xf4, 0x8f, 0x21, 0x82, 0xf4, 0x6f, 0x15, 0xc0, 0xf4, 0x5f, 0x19, 0xc0, 0xf4, 0x6d, 0x75, 0x81, 0xf4, 0x5d, 0x69, 0x82, 0xf4, 0x65, 0x25, 0x83, 0xf4, 0x57, 0x59, 0x84, 0xf4, 0x2f, 0x02, 0xc1, 0xf4, 0x4f, 0x66, 0x82, 0xf4, 0x8f, 0x1a, 0x83, 0xf4, 0x6f, 0xb6, 0xc4, 0xf4, 0xcf, 0x6a, 0x85, 0xf4, 0x21, 0xc2, 0x86, 0xf4, 0x42, 0xb6, 0x87, 0xf4, 0x83, 0x2a, 0x88, 0xf4, 0x64, 0xe6, 0x89, 0xf4, 0xc5, 0x0a, 0xca, 0xf4, 0x2d, 0x62, 0x88, 0xf4, 0x4d, 0x96, 0x87, 0xf4, 0x8d, 0x1a, 0x86, 0xf4, 0x6d, 0x46, 0xc5, 0xf4, 0xcd, 0x5a, 0x84, 0xf4, 0x2f, 0x03, 0xc1, 0xf4, 0x4f, 0x07, 0xc2, 0xf4, 0x8f, 0x0b, 0xc3, 0xf4, 0x6f, 0x17, 0xc7, 0xf4, 0xcf, 0x0b, 0xc8, 0xf4, 0x3d, 0x03, 0xc1, 0xf4, 0x5d, 0x07, 0xc2, 0xf4, 0xad, 0x0b, 0xc3, 0xf4, 0x6d, 0x17, 0xc7, 0xf4, 0xcd, 0x0b, 0xc8, 0xf4, 0x38, 0x03, 0xc1, 0xf4, 0x47, 0x07, 0xc2, 0xf4, 0x95, 0x0b, 0xc3, 0xf4, 0x63, 0x07, 0xc6, 0xf4, 0xc4, 0x1b, 0xc9, 0xf4, 0x0f, 0x27, 0x02, 0xf4, 0x0f, 0x27, 0x02, 0xf4, 0x0f, 0x27, 0x02, 0xf4, 0x0f, 0x4a, 0x02, 0xf4, 0x0f, 0x4a, 0x02, 0xf4, 0x0f, 0x4a, 0x02, 0xf4, 0x8f, 0x4a, 0x02, 0xf4, 0x0f, 0x89, 0x04, 0xf4, 0xbf, 0x98, 0x83, 0xf4, 0xbd, 0xb8, 0xc9, 0xf4, 0xb5, 0xb8, 0xc3, 0xf4, 0x1f, 0x08, 0x40, 0xf4, 0x6f, 0x08, 0x40, 0xf4 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vst1.8 {d16}, [r0:64]" + - + asm_text: "vst1.16 {d16}, [r0]" + - + asm_text: "vst1.32 {d16}, [r0]" + - + asm_text: "vst1.64 {d16}, [r0]" + - + asm_text: "vst1.8 {d16, d17}, [r0:64]" + - + asm_text: "vst1.16 {d16, d17}, [r0:128]" + - + asm_text: "vst1.32 {d16, d17}, [r0]" + - + asm_text: "vst1.64 {d16, d17}, [r0]" + - + asm_text: "vst1.8 {d16, d17, d18}, [r0:64]" + - + asm_text: "vst1.8 {d16, d17, d18}, [r0:64]!" + - + asm_text: "vst1.8 {d16, d17, d18}, [r0], r3" + - + asm_text: "vst1.8 {d16, d17, d18, d19}, [r0:64]" + - + asm_text: "vst1.16 {d16, d17, d18, d19}, [r1:64]!" + - + asm_text: "vst1.64 {d16, d17, d18, d19}, [r3], r2" + - + asm_text: "vst2.8 {d16, d17}, [r0:64]" + - + asm_text: "vst2.16 {d16, d17}, [r0:128]" + - + asm_text: "vst2.32 {d16, d17}, [r0]" + - + asm_text: "vst2.8 {d16, d17, d18, d19}, [r0:64]" + - + asm_text: "vst2.16 {d16, d17, d18, d19}, [r0:128]" + - + asm_text: "vst2.32 {d16, d17, d18, d19}, [r0:256]" + - + asm_text: "vst2.8 {d16, d17}, [r0:64]!" + - + asm_text: "vst2.16 {d30, d31}, [r0:128]!" + - + asm_text: "vst2.32 {d14, d15}, [r0]!" + - + asm_text: "vst2.8 {d16, d17, d18, d19}, [r0:64]!" + - + asm_text: "vst2.16 {d18, d19, d20, d21}, [r0:128]!" + - + asm_text: "vst2.32 {d8, d9, d10, d11}, [r0:256]!" + - + asm_text: "vst3.8 {d16, d17, d18}, [r1]" + - + asm_text: "vst3.16 {d6, d7, d8}, [r2]" + - + asm_text: "vst3.32 {d1, d2, d3}, [r3]" + - + asm_text: "vst3.8 {d16, d18, d20}, [r0:64]" + - + asm_text: "vst3.16 {d27, d29, d31}, [r4]" + - + asm_text: "vst3.32 {d6, d8, d10}, [r5]" + - + asm_text: "vst3.8 {d12, d13, d14}, [r6], r1" + - + asm_text: "vst3.16 {d11, d12, d13}, [r7], r2" + - + asm_text: "vst3.32 {d2, d3, d4}, [r8], r3" + - + asm_text: "vst3.8 {d4, d6, d8}, [r9], r4" + - + asm_text: "vst3.16 {d14, d16, d18}, [r9], r4" + - + asm_text: "vst3.32 {d16, d18, d20}, [r10], r5" + - + asm_text: "vst3.8 {d6, d7, d8}, [r8]!" + - + asm_text: "vst3.16 {d9, d10, d11}, [r7]!" + - + asm_text: "vst3.32 {d1, d2, d3}, [r6]!" + - + asm_text: "vst3.8 {d16, d18, d20}, [r0:64]!" + - + asm_text: "vst3.16 {d20, d22, d24}, [r5]!" + - + asm_text: "vst3.32 {d5, d7, d9}, [r4]!" + - + asm_text: "vst4.8 {d16, d17, d18, d19}, [r1:64]" + - + asm_text: "vst4.16 {d16, d17, d18, d19}, [r2:128]" + - + asm_text: "vst4.32 {d16, d17, d18, d19}, [r3:256]" + - + asm_text: "vst4.8 {d17, d19, d21, d23}, [r5:256]" + - + asm_text: "vst4.16 {d17, d19, d21, d23}, [r7]" + - + asm_text: "vst4.32 {d16, d18, d20, d22}, [r8]" + - + asm_text: "vst4.8 {d16, d17, d18, d19}, [r1:64]!" + - + asm_text: "vst4.16 {d16, d17, d18, d19}, [r2:128]!" + - + asm_text: "vst4.32 {d16, d17, d18, d19}, [r3:256]!" + - + asm_text: "vst4.8 {d17, d19, d21, d23}, [r5:256]!" + - + asm_text: "vst4.16 {d17, d19, d21, d23}, [r7]!" + - + asm_text: "vst4.32 {d16, d18, d20, d22}, [r8]!" + - + asm_text: "vst4.8 {d16, d17, d18, d19}, [r1:64], r8" + - + asm_text: "vst4.16 {d16, d17, d18, d19}, [r2], r7" + - + asm_text: "vst4.32 {d16, d17, d18, d19}, [r3:64], r5" + - + asm_text: "vst4.8 {d16, d18, d20, d22}, [r4:256], r2" + - + asm_text: "vst4.16 {d16, d18, d20, d22}, [r6], r3" + - + asm_text: "vst4.32 {d17, d19, d21, d23}, [r9], r4" + - + asm_text: "vst2.8 {d16[1], d17[1]}, [r0:16]" + - + asm_text: "vst2.16 {d16[1], d17[1]}, [r0:32]" + - + asm_text: "vst2.32 {d16[1], d17[1]}, [r0]" + - + asm_text: "vst2.16 {d17[1], d19[1]}, [r0]" + - + asm_text: "vst2.32 {d17[0], d19[0]}, [r0:64]" + - + asm_text: "vst2.8 {d2[4], d3[4]}, [r2], r3" + - + asm_text: "vst2.8 {d2[4], d3[4]}, [r2]!" + - + asm_text: "vst2.8 {d2[4], d3[4]}, [r2]" + - + asm_text: "vst2.16 {d17[1], d19[1]}, [r0]" + - + asm_text: "vst2.32 {d17[0], d19[0]}, [r0:64]" + - + asm_text: "vst2.16 {d7[1], d9[1]}, [r1]!" + - + asm_text: "vst2.32 {d6[0], d8[0]}, [r2:64]!" + - + asm_text: "vst2.16 {d2[1], d4[1]}, [r3], r5" + - + asm_text: "vst2.32 {d5[0], d7[0]}, [r4:64], r7" + - + asm_text: "vst3.8 {d16[1], d17[1], d18[1]}, [r1]" + - + asm_text: "vst3.16 {d6[1], d7[1], d8[1]}, [r2]" + - + asm_text: "vst3.32 {d1[1], d2[1], d3[1]}, [r3]" + - + asm_text: "vst3.16 {d27[1], d29[1], d31[1]}, [r4]" + - + asm_text: "vst3.32 {d6[1], d8[1], d10[1]}, [r5]" + - + asm_text: "vst3.8 {d12[1], d13[1], d14[1]}, [r6], r1" + - + asm_text: "vst3.16 {d11[1], d12[1], d13[1]}, [r7], r2" + - + asm_text: "vst3.32 {d2[1], d3[1], d4[1]}, [r8], r3" + - + asm_text: "vst3.16 {d14[1], d16[1], d18[1]}, [r9], r4" + - + asm_text: "vst3.32 {d16[1], d18[1], d20[1]}, [r10], r5" + - + asm_text: "vst3.8 {d6[1], d7[1], d8[1]}, [r8]!" + - + asm_text: "vst3.16 {d9[1], d10[1], d11[1]}, [r7]!" + - + asm_text: "vst3.32 {d1[1], d2[1], d3[1]}, [r6]!" + - + asm_text: "vst3.16 {d20[1], d22[1], d24[1]}, [r5]!" + - + asm_text: "vst3.32 {d5[1], d7[1], d9[1]}, [r4]!" + - + asm_text: "vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1]" + - + asm_text: "vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2]" + - + asm_text: "vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3]" + - + asm_text: "vst4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]" + - + asm_text: "vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]" + - + asm_text: "vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]!" + - + asm_text: "vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2:64]!" + - + asm_text: "vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:128]!" + - + asm_text: "vst4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]!" + - + asm_text: "vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]!" + - + asm_text: "vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32], r8" + - + asm_text: "vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7" + - + asm_text: "vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:64], r5" + - + asm_text: "vst4.16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3" + - + asm_text: "vst4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4" + - + asm_text: "vst1.8 {d2}, [r2]" + - + asm_text: "vst1.8 {d2}, [r2]" + - + asm_text: "vst1.8 {d2}, [r2]" + - + asm_text: "vst1.8 {d4, d5}, [r2]" + - + asm_text: "vst1.8 {d4, d5}, [r2]" + - + asm_text: "vst1.8 {d4, d5}, [r2]" + - + asm_text: "vst1.32 {d4, d5}, [r2]" + - + asm_text: "vst2.8 {d8, d10}, [r4]" + - + asm_text: "vst1.32 {d9[1]}, [r3:32]" + - + asm_text: "vst1.32 {d27[1]}, [r9:32]!" + - + asm_text: "vst1.32 {d27[1]}, [r3:32], r5" + - + asm_text: "vst2.8 {d16, d17}, [r0:64]" + - + asm_text: "vst2.16 {d16, d17}, [r0:128]" diff --git a/tests/MC/ARM/neon-vswp.s.yaml b/tests/MC/ARM/neon-vswp.s.yaml new file mode 100644 index 0000000000..56acf945bb --- /dev/null +++ b/tests/MC/ARM/neon-vswp.s.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0x02, 0x10, 0xb2, 0xf3, 0x44, 0x20, 0xb2, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vswp d1, d2" + - + asm_text: "vswp q1, q2" diff --git a/tests/MC/ARM/neont2-abs-encoding.s.yaml b/tests/MC/ARM/neont2-abs-encoding.s.yaml new file mode 100644 index 0000000000..7fa31d7750 --- /dev/null +++ b/tests/MC/ARM/neont2-abs-encoding.s.yaml @@ -0,0 +1,36 @@ +test_cases: + - + input: + bytes: [ 0xf1, 0xff, 0x20, 0x03, 0xf5, 0xff, 0x20, 0x03, 0xf9, 0xff, 0x20, 0x03, 0xf9, 0xff, 0x20, 0x07, 0xf1, 0xff, 0x60, 0x03, 0xf5, 0xff, 0x60, 0x03, 0xf9, 0xff, 0x60, 0x03, 0xf9, 0xff, 0x60, 0x07, 0xf0, 0xff, 0x20, 0x07, 0xf4, 0xff, 0x20, 0x07, 0xf8, 0xff, 0x20, 0x07, 0xf0, 0xff, 0x60, 0x07, 0xf4, 0xff, 0x60, 0x07, 0xf8, 0xff, 0x60, 0x07 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vabs.s8 d16, d16" + - + asm_text: "vabs.s16 d16, d16" + - + asm_text: "vabs.s32 d16, d16" + - + asm_text: "vabs.f32 d16, d16" + - + asm_text: "vabs.s8 q8, q8" + - + asm_text: "vabs.s16 q8, q8" + - + asm_text: "vabs.s32 q8, q8" + - + asm_text: "vabs.f32 q8, q8" + - + asm_text: "vqabs.s8 d16, d16" + - + asm_text: "vqabs.s16 d16, d16" + - + asm_text: "vqabs.s32 d16, d16" + - + asm_text: "vqabs.s8 q8, q8" + - + asm_text: "vqabs.s16 q8, q8" + - + asm_text: "vqabs.s32 q8, q8" diff --git a/tests/MC/ARM/neont2-absdiff-encoding.s.yaml b/tests/MC/ARM/neont2-absdiff-encoding.s.yaml new file mode 100644 index 0000000000..7f70dda48f --- /dev/null +++ b/tests/MC/ARM/neont2-absdiff-encoding.s.yaml @@ -0,0 +1,84 @@ +test_cases: + - + input: + bytes: [ 0x40, 0xef, 0xa1, 0x07, 0x50, 0xef, 0xa1, 0x07, 0x60, 0xef, 0xa1, 0x07, 0x40, 0xff, 0xa1, 0x07, 0x50, 0xff, 0xa1, 0x07, 0x60, 0xff, 0xa1, 0x07, 0x60, 0xff, 0xa1, 0x0d, 0x40, 0xef, 0xe2, 0x07, 0x50, 0xef, 0xe2, 0x07, 0x60, 0xef, 0xe2, 0x07, 0x40, 0xff, 0xe2, 0x07, 0x50, 0xff, 0xe2, 0x07, 0x60, 0xff, 0xe2, 0x07, 0x60, 0xff, 0xe2, 0x0d, 0xc0, 0xef, 0xa1, 0x07, 0xd0, 0xef, 0xa1, 0x07, 0xe0, 0xef, 0xa1, 0x07, 0xc0, 0xff, 0xa1, 0x07, 0xd0, 0xff, 0xa1, 0x07, 0xe0, 0xff, 0xa1, 0x07, 0x42, 0xef, 0xb1, 0x07, 0x52, 0xef, 0xb1, 0x07, 0x62, 0xef, 0xb1, 0x07, 0x42, 0xff, 0xb1, 0x07, 0x52, 0xff, 0xb1, 0x07, 0x62, 0xff, 0xb1, 0x07, 0x40, 0xef, 0xf4, 0x27, 0x50, 0xef, 0xf4, 0x27, 0x60, 0xef, 0xf4, 0x27, 0x40, 0xff, 0xf4, 0x27, 0x50, 0xff, 0xf4, 0x27, 0x60, 0xff, 0xf4, 0x27, 0xc3, 0xef, 0xa2, 0x05, 0xd3, 0xef, 0xa2, 0x05, 0xe3, 0xef, 0xa2, 0x05, 0xc3, 0xff, 0xa2, 0x05, 0xd3, 0xff, 0xa2, 0x05, 0xe3, 0xff, 0xa2, 0x05 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vabd.s8 d16, d16, d17" + - + asm_text: "vabd.s16 d16, d16, d17" + - + asm_text: "vabd.s32 d16, d16, d17" + - + asm_text: "vabd.u8 d16, d16, d17" + - + asm_text: "vabd.u16 d16, d16, d17" + - + asm_text: "vabd.u32 d16, d16, d17" + - + asm_text: "vabd.f32 d16, d16, d17" + - + asm_text: "vabd.s8 q8, q8, q9" + - + asm_text: "vabd.s16 q8, q8, q9" + - + asm_text: "vabd.s32 q8, q8, q9" + - + asm_text: "vabd.u8 q8, q8, q9" + - + asm_text: "vabd.u16 q8, q8, q9" + - + asm_text: "vabd.u32 q8, q8, q9" + - + asm_text: "vabd.f32 q8, q8, q9" + - + asm_text: "vabdl.s8 q8, d16, d17" + - + asm_text: "vabdl.s16 q8, d16, d17" + - + asm_text: "vabdl.s32 q8, d16, d17" + - + asm_text: "vabdl.u8 q8, d16, d17" + - + asm_text: "vabdl.u16 q8, d16, d17" + - + asm_text: "vabdl.u32 q8, d16, d17" + - + asm_text: "vaba.s8 d16, d18, d17" + - + asm_text: "vaba.s16 d16, d18, d17" + - + asm_text: "vaba.s32 d16, d18, d17" + - + asm_text: "vaba.u8 d16, d18, d17" + - + asm_text: "vaba.u16 d16, d18, d17" + - + asm_text: "vaba.u32 d16, d18, d17" + - + asm_text: "vaba.s8 q9, q8, q10" + - + asm_text: "vaba.s16 q9, q8, q10" + - + asm_text: "vaba.s32 q9, q8, q10" + - + asm_text: "vaba.u8 q9, q8, q10" + - + asm_text: "vaba.u16 q9, q8, q10" + - + asm_text: "vaba.u32 q9, q8, q10" + - + asm_text: "vabal.s8 q8, d19, d18" + - + asm_text: "vabal.s16 q8, d19, d18" + - + asm_text: "vabal.s32 q8, d19, d18" + - + asm_text: "vabal.u8 q8, d19, d18" + - + asm_text: "vabal.u16 q8, d19, d18" + - + asm_text: "vabal.u32 q8, d19, d18" diff --git a/tests/MC/ARM/neont2-add-encoding.s.yaml b/tests/MC/ARM/neont2-add-encoding.s.yaml new file mode 100644 index 0000000000..b61dc0cfe3 --- /dev/null +++ b/tests/MC/ARM/neont2-add-encoding.s.yaml @@ -0,0 +1,136 @@ +test_cases: + - + input: + bytes: [ 0x41, 0xef, 0xa0, 0x08, 0x51, 0xef, 0xa0, 0x08, 0x71, 0xef, 0xa0, 0x08, 0x61, 0xef, 0xa0, 0x08, 0x40, 0xef, 0xa1, 0x0d, 0x40, 0xef, 0xe2, 0x0d, 0xc1, 0xef, 0xa0, 0x00, 0xd1, 0xef, 0xa0, 0x00, 0xe1, 0xef, 0xa0, 0x00, 0xc1, 0xff, 0xa0, 0x00, 0xd1, 0xff, 0xa0, 0x00, 0xe1, 0xff, 0xa0, 0x00, 0xc0, 0xef, 0xa2, 0x01, 0xd0, 0xef, 0xa2, 0x01, 0xe0, 0xef, 0xa2, 0x01, 0xc0, 0xff, 0xa2, 0x01, 0xd0, 0xff, 0xa2, 0x01, 0xe0, 0xff, 0xa2, 0x01, 0x40, 0xef, 0xa1, 0x00, 0x50, 0xef, 0xa1, 0x00, 0x60, 0xef, 0xa1, 0x00, 0x40, 0xff, 0xa1, 0x00, 0x50, 0xff, 0xa1, 0x00, 0x60, 0xff, 0xa1, 0x00, 0x40, 0xef, 0xe2, 0x00, 0x50, 0xef, 0xe2, 0x00, 0x60, 0xef, 0xe2, 0x00, 0x40, 0xff, 0xe2, 0x00, 0x50, 0xff, 0xe2, 0x00, 0x60, 0xff, 0xe2, 0x00, 0x40, 0xef, 0xa1, 0x01, 0x50, 0xef, 0xa1, 0x01, 0x60, 0xef, 0xa1, 0x01, 0x40, 0xff, 0xa1, 0x01, 0x50, 0xff, 0xa1, 0x01, 0x60, 0xff, 0xa1, 0x01, 0x40, 0xef, 0xe2, 0x01, 0x50, 0xef, 0xe2, 0x01, 0x60, 0xef, 0xe2, 0x01, 0x40, 0xff, 0xe2, 0x01, 0x50, 0xff, 0xe2, 0x01, 0x60, 0xff, 0xe2, 0x01, 0x40, 0xef, 0xb1, 0x00, 0x50, 0xef, 0xb1, 0x00, 0x60, 0xef, 0xb1, 0x00, 0x70, 0xef, 0xb1, 0x00, 0x40, 0xff, 0xb1, 0x00, 0x50, 0xff, 0xb1, 0x00, 0x60, 0xff, 0xb1, 0x00, 0x70, 0xff, 0xb1, 0x00, 0x40, 0xef, 0xf2, 0x00, 0x50, 0xef, 0xf2, 0x00, 0x60, 0xef, 0xf2, 0x00, 0x70, 0xef, 0xf2, 0x00, 0x40, 0xff, 0xf2, 0x00, 0x50, 0xff, 0xf2, 0x00, 0x60, 0xff, 0xf2, 0x00, 0x70, 0xff, 0xf2, 0x00, 0xc0, 0xef, 0xa2, 0x04, 0xd0, 0xef, 0xa2, 0x04, 0xe0, 0xef, 0xa2, 0x04, 0xc0, 0xff, 0xa2, 0x04, 0xd0, 0xff, 0xa2, 0x04, 0xe0, 0xff, 0xa2, 0x04 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vadd.i8 d16, d17, d16" + - + asm_text: "vadd.i16 d16, d17, d16" + - + asm_text: "vadd.i64 d16, d17, d16" + - + asm_text: "vadd.i32 d16, d17, d16" + - + asm_text: "vadd.f32 d16, d16, d17" + - + asm_text: "vadd.f32 q8, q8, q9" + - + asm_text: "vaddl.s8 q8, d17, d16" + - + asm_text: "vaddl.s16 q8, d17, d16" + - + asm_text: "vaddl.s32 q8, d17, d16" + - + asm_text: "vaddl.u8 q8, d17, d16" + - + asm_text: "vaddl.u16 q8, d17, d16" + - + asm_text: "vaddl.u32 q8, d17, d16" + - + asm_text: "vaddw.s8 q8, q8, d18" + - + asm_text: "vaddw.s16 q8, q8, d18" + - + asm_text: "vaddw.s32 q8, q8, d18" + - + asm_text: "vaddw.u8 q8, q8, d18" + - + asm_text: "vaddw.u16 q8, q8, d18" + - + asm_text: "vaddw.u32 q8, q8, d18" + - + asm_text: "vhadd.s8 d16, d16, d17" + - + asm_text: "vhadd.s16 d16, d16, d17" + - + asm_text: "vhadd.s32 d16, d16, d17" + - + asm_text: "vhadd.u8 d16, d16, d17" + - + asm_text: "vhadd.u16 d16, d16, d17" + - + asm_text: "vhadd.u32 d16, d16, d17" + - + asm_text: "vhadd.s8 q8, q8, q9" + - + asm_text: "vhadd.s16 q8, q8, q9" + - + asm_text: "vhadd.s32 q8, q8, q9" + - + asm_text: "vhadd.u8 q8, q8, q9" + - + asm_text: "vhadd.u16 q8, q8, q9" + - + asm_text: "vhadd.u32 q8, q8, q9" + - + asm_text: "vrhadd.s8 d16, d16, d17" + - + asm_text: "vrhadd.s16 d16, d16, d17" + - + asm_text: "vrhadd.s32 d16, d16, d17" + - + asm_text: "vrhadd.u8 d16, d16, d17" + - + asm_text: "vrhadd.u16 d16, d16, d17" + - + asm_text: "vrhadd.u32 d16, d16, d17" + - + asm_text: "vrhadd.s8 q8, q8, q9" + - + asm_text: "vrhadd.s16 q8, q8, q9" + - + asm_text: "vrhadd.s32 q8, q8, q9" + - + asm_text: "vrhadd.u8 q8, q8, q9" + - + asm_text: "vrhadd.u16 q8, q8, q9" + - + asm_text: "vrhadd.u32 q8, q8, q9" + - + asm_text: "vqadd.s8 d16, d16, d17" + - + asm_text: "vqadd.s16 d16, d16, d17" + - + asm_text: "vqadd.s32 d16, d16, d17" + - + asm_text: "vqadd.s64 d16, d16, d17" + - + asm_text: "vqadd.u8 d16, d16, d17" + - + asm_text: "vqadd.u16 d16, d16, d17" + - + asm_text: "vqadd.u32 d16, d16, d17" + - + asm_text: "vqadd.u64 d16, d16, d17" + - + asm_text: "vqadd.s8 q8, q8, q9" + - + asm_text: "vqadd.s16 q8, q8, q9" + - + asm_text: "vqadd.s32 q8, q8, q9" + - + asm_text: "vqadd.s64 q8, q8, q9" + - + asm_text: "vqadd.u8 q8, q8, q9" + - + asm_text: "vqadd.u16 q8, q8, q9" + - + asm_text: "vqadd.u32 q8, q8, q9" + - + asm_text: "vqadd.u64 q8, q8, q9" + - + asm_text: "vaddhn.i16 d16, q8, q9" + - + asm_text: "vaddhn.i32 d16, q8, q9" + - + asm_text: "vaddhn.i64 d16, q8, q9" + - + asm_text: "vraddhn.i16 d16, q8, q9" + - + asm_text: "vraddhn.i32 d16, q8, q9" + - + asm_text: "vraddhn.i64 d16, q8, q9" diff --git a/tests/MC/ARM/neont2-bitcount-encoding.s.yaml b/tests/MC/ARM/neont2-bitcount-encoding.s.yaml new file mode 100644 index 0000000000..446c5fe347 --- /dev/null +++ b/tests/MC/ARM/neont2-bitcount-encoding.s.yaml @@ -0,0 +1,36 @@ +test_cases: + - + input: + bytes: [ 0xf0, 0xff, 0x20, 0x05, 0xf0, 0xff, 0x60, 0x05, 0xf0, 0xff, 0xa0, 0x04, 0xf4, 0xff, 0xa0, 0x04, 0xf8, 0xff, 0xa0, 0x04, 0xf0, 0xff, 0xe0, 0x04, 0xf4, 0xff, 0xe0, 0x04, 0xf8, 0xff, 0xe0, 0x04, 0xf0, 0xff, 0x20, 0x04, 0xf4, 0xff, 0x20, 0x04, 0xf8, 0xff, 0x20, 0x04, 0xf0, 0xff, 0x60, 0x04, 0xf4, 0xff, 0x60, 0x04, 0xf8, 0xff, 0x60, 0x04 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vcnt.8 d16, d16" + - + asm_text: "vcnt.8 q8, q8" + - + asm_text: "vclz.i8 d16, d16" + - + asm_text: "vclz.i16 d16, d16" + - + asm_text: "vclz.i32 d16, d16" + - + asm_text: "vclz.i8 q8, q8" + - + asm_text: "vclz.i16 q8, q8" + - + asm_text: "vclz.i32 q8, q8" + - + asm_text: "vcls.s8 d16, d16" + - + asm_text: "vcls.s16 d16, d16" + - + asm_text: "vcls.s32 d16, d16" + - + asm_text: "vcls.s8 q8, q8" + - + asm_text: "vcls.s16 q8, q8" + - + asm_text: "vcls.s32 q8, q8" diff --git a/tests/MC/ARM/neont2-bitwise-encoding.s.yaml b/tests/MC/ARM/neont2-bitwise-encoding.s.yaml new file mode 100644 index 0000000000..ade8ef8c93 --- /dev/null +++ b/tests/MC/ARM/neont2-bitwise-encoding.s.yaml @@ -0,0 +1,44 @@ +test_cases: + - + input: + bytes: [ 0x41, 0xef, 0xb0, 0x01, 0x40, 0xef, 0xf2, 0x01, 0x41, 0xff, 0xb0, 0x01, 0x40, 0xff, 0xf2, 0x01, 0x61, 0xef, 0xb0, 0x01, 0x60, 0xef, 0xf2, 0x01, 0x51, 0xef, 0xb0, 0x01, 0x50, 0xef, 0xf2, 0x01, 0x71, 0xef, 0xb0, 0x01, 0x70, 0xef, 0xf2, 0x01, 0xf0, 0xff, 0xa0, 0x05, 0xf0, 0xff, 0xe0, 0x05, 0x51, 0xff, 0xb0, 0x21, 0x54, 0xff, 0xf2, 0x01, 0x61, 0xff, 0xb0, 0x21, 0x64, 0xff, 0xf2, 0x01, 0x71, 0xff, 0xb0, 0x21, 0x74, 0xff, 0xf2, 0x01 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vand d16, d17, d16" + - + asm_text: "vand q8, q8, q9" + - + asm_text: "veor d16, d17, d16" + - + asm_text: "veor q8, q8, q9" + - + asm_text: "vorr d16, d17, d16" + - + asm_text: "vorr q8, q8, q9" + - + asm_text: "vbic d16, d17, d16" + - + asm_text: "vbic q8, q8, q9" + - + asm_text: "vorn d16, d17, d16" + - + asm_text: "vorn q8, q8, q9" + - + asm_text: "vmvn d16, d16" + - + asm_text: "vmvn q8, q8" + - + asm_text: "vbsl d18, d17, d16" + - + asm_text: "vbsl q8, q10, q9" + - + asm_text: "vbit d18, d17, d16" + - + asm_text: "vbit q8, q10, q9" + - + asm_text: "vbif d18, d17, d16" + - + asm_text: "vbif q8, q10, q9" diff --git a/tests/MC/ARM/neont2-cmp-encoding.s.yaml b/tests/MC/ARM/neont2-cmp-encoding.s.yaml new file mode 100644 index 0000000000..b83a7f6337 --- /dev/null +++ b/tests/MC/ARM/neont2-cmp-encoding.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0xfb, 0xff, 0x20, 0x07, 0xfb, 0xff, 0xa0, 0x07, 0xfb, 0xff, 0x20, 0x06, 0xfb, 0xff, 0xa0, 0x06, 0xfb, 0xff, 0x60, 0x07, 0xfb, 0xff, 0xe0, 0x07, 0xfb, 0xff, 0x60, 0x06, 0xfb, 0xff, 0xe0, 0x06, 0xff, 0xef, 0x30, 0x0f, 0xff, 0xff, 0x30, 0x0f, 0xff, 0xef, 0x30, 0x0e, 0xff, 0xff, 0x30, 0x0e, 0xff, 0xef, 0x70, 0x0f, 0xff, 0xff, 0x70, 0x0f, 0xff, 0xef, 0x70, 0x0e, 0xff, 0xff, 0x70, 0x0e ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vcvt.s32.f32 d16, d16" + - + asm_text: "vcvt.u32.f32 d16, d16" + - + asm_text: "vcvt.f32.s32 d16, d16" + - + asm_text: "vcvt.f32.u32 d16, d16" + - + asm_text: "vcvt.s32.f32 q8, q8" + - + asm_text: "vcvt.u32.f32 q8, q8" + - + asm_text: "vcvt.f32.s32 q8, q8" + - + asm_text: "vcvt.f32.u32 q8, q8" + - + asm_text: "vcvt.s32.f32 d16, d16, #1" + - + asm_text: "vcvt.u32.f32 d16, d16, #1" + - + asm_text: "vcvt.f32.s32 d16, d16, #1" + - + asm_text: "vcvt.f32.u32 d16, d16, #1" + - + asm_text: "vcvt.s32.f32 q8, q8, #1" + - + asm_text: "vcvt.u32.f32 q8, q8, #1" + - + asm_text: "vcvt.f32.s32 q8, q8, #1" + - + asm_text: "vcvt.f32.u32 q8, q8, #1" diff --git a/tests/MC/ARM/neont2-convert-encoding.s.yaml b/tests/MC/ARM/neont2-convert-encoding.s.yaml new file mode 100644 index 0000000000..e2450a03d7 --- /dev/null +++ b/tests/MC/ARM/neont2-convert-encoding.s.yaml @@ -0,0 +1,44 @@ +test_cases: + - + input: + bytes: [ 0xfb, 0xff, 0x20, 0x07, 0xfb, 0xff, 0xa0, 0x07, 0xfb, 0xff, 0x20, 0x06, 0xfb, 0xff, 0xa0, 0x06, 0xfb, 0xff, 0x60, 0x07, 0xfb, 0xff, 0xe0, 0x07, 0xfb, 0xff, 0x60, 0x06, 0xfb, 0xff, 0xe0, 0x06, 0xff, 0xef, 0x30, 0x0f, 0xff, 0xff, 0x30, 0x0f, 0xff, 0xef, 0x30, 0x0e, 0xff, 0xff, 0x30, 0x0e, 0xff, 0xef, 0x70, 0x0f, 0xff, 0xff, 0x70, 0x0f, 0xff, 0xef, 0x70, 0x0e, 0xff, 0xff, 0x70, 0x0e, 0xf6, 0xff, 0x20, 0x07, 0xf6, 0xff, 0x20, 0x06 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vcvt.s32.f32 d16, d16" + - + asm_text: "vcvt.u32.f32 d16, d16" + - + asm_text: "vcvt.f32.s32 d16, d16" + - + asm_text: "vcvt.f32.u32 d16, d16" + - + asm_text: "vcvt.s32.f32 q8, q8" + - + asm_text: "vcvt.u32.f32 q8, q8" + - + asm_text: "vcvt.f32.s32 q8, q8" + - + asm_text: "vcvt.f32.u32 q8, q8" + - + asm_text: "vcvt.s32.f32 d16, d16, #1" + - + asm_text: "vcvt.u32.f32 d16, d16, #1" + - + asm_text: "vcvt.f32.s32 d16, d16, #1" + - + asm_text: "vcvt.f32.u32 d16, d16, #1" + - + asm_text: "vcvt.s32.f32 q8, q8, #1" + - + asm_text: "vcvt.u32.f32 q8, q8, #1" + - + asm_text: "vcvt.f32.s32 q8, q8, #1" + - + asm_text: "vcvt.f32.u32 q8, q8, #1" + - + asm_text: "vcvt.f32.f16 q8, d16" + - + asm_text: "vcvt.f16.f32 d16, q8" diff --git a/tests/MC/ARM/neont2-dup-encoding.s.yaml b/tests/MC/ARM/neont2-dup-encoding.s.yaml new file mode 100644 index 0000000000..10ecb49973 --- /dev/null +++ b/tests/MC/ARM/neont2-dup-encoding.s.yaml @@ -0,0 +1,44 @@ +test_cases: + - + input: + bytes: [ 0xc0, 0xee, 0x90, 0x1b, 0x8f, 0xee, 0x30, 0x2b, 0x8e, 0xee, 0x10, 0x3b, 0xe2, 0xee, 0x90, 0x4b, 0xa0, 0xee, 0xb0, 0x5b, 0xae, 0xee, 0x10, 0x6b, 0xf1, 0xff, 0x0b, 0x0c, 0xf2, 0xff, 0x0c, 0x1c, 0xf4, 0xff, 0x0d, 0x2c, 0xb1, 0xff, 0x4a, 0x6c, 0xf2, 0xff, 0x49, 0x2c, 0xf4, 0xff, 0x48, 0x0c, 0xf3, 0xff, 0x0b, 0x0c, 0xf6, 0xff, 0x0c, 0x1c, 0xfc, 0xff, 0x0d, 0x2c, 0xb3, 0xff, 0x4a, 0x6c, 0xf6, 0xff, 0x49, 0x2c, 0xfc, 0xff, 0x48, 0x0c ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vdup.8 d16, r1" + - + asm_text: "vdup.16 d15, r2" + - + asm_text: "vdup.32 d14, r3" + - + asm_text: "vdup.8 q9, r4" + - + asm_text: "vdup.16 q8, r5" + - + asm_text: "vdup.32 q7, r6" + - + asm_text: "vdup.8 d16, d11[0]" + - + asm_text: "vdup.16 d17, d12[0]" + - + asm_text: "vdup.32 d18, d13[0]" + - + asm_text: "vdup.8 q3, d10[0]" + - + asm_text: "vdup.16 q9, d9[0]" + - + asm_text: "vdup.32 q8, d8[0]" + - + asm_text: "vdup.8 d16, d11[1]" + - + asm_text: "vdup.16 d17, d12[1]" + - + asm_text: "vdup.32 d18, d13[1]" + - + asm_text: "vdup.8 q3, d10[1]" + - + asm_text: "vdup.16 q9, d9[1]" + - + asm_text: "vdup.32 q8, d8[1]" diff --git a/tests/MC/ARM/neont2-minmax-encoding.s.yaml b/tests/MC/ARM/neont2-minmax-encoding.s.yaml new file mode 100644 index 0000000000..b78bb41643 --- /dev/null +++ b/tests/MC/ARM/neont2-minmax-encoding.s.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x02, 0xef, 0x03, 0x16, 0x15, 0xef, 0x06, 0x46, 0x28, 0xef, 0x09, 0x76, 0x0b, 0xff, 0x0c, 0xa6, 0x1e, 0xff, 0x0f, 0xd6, 0x61, 0xff, 0xa2, 0x06, 0x44, 0xef, 0xa5, 0x3f, 0x02, 0xef, 0x03, 0x26, 0x15, 0xef, 0x06, 0x56, 0x28, 0xef, 0x09, 0x86, 0x0b, 0xff, 0x0c, 0xb6, 0x1e, 0xff, 0x0f, 0xe6, 0x61, 0xff, 0xa2, 0x16, 0x44, 0xef, 0xa5, 0x4f, 0x04, 0xef, 0x46, 0x26, 0x1a, 0xef, 0x4c, 0x86, 0x20, 0xef, 0xe2, 0xe6, 0x46, 0xff, 0xe8, 0x46, 0x5c, 0xff, 0xee, 0xa6, 0x2e, 0xff, 0x60, 0xc6, 0x4a, 0xef, 0x42, 0x2f, 0x04, 0xef, 0x46, 0x46, 0x1a, 0xef, 0x4c, 0xa6, 0x60, 0xef, 0xe2, 0x06, 0x46, 0xff, 0xc4, 0x66, 0x18, 0xff, 0x4a, 0x86, 0x2e, 0xff, 0x60, 0xe6, 0x04, 0xef, 0x42, 0x4f, 0x02, 0xef, 0x13, 0x16, 0x15, 0xef, 0x16, 0x46, 0x28, 0xef, 0x19, 0x76, 0x0b, 0xff, 0x1c, 0xa6, 0x1e, 0xff, 0x1f, 0xd6, 0x61, 0xff, 0xb2, 0x06, 0x64, 0xef, 0xa5, 0x3f, 0x02, 0xef, 0x13, 0x26, 0x15, 0xef, 0x16, 0x56, 0x28, 0xef, 0x19, 0x86, 0x0b, 0xff, 0x1c, 0xb6, 0x1e, 0xff, 0x1f, 0xe6, 0x61, 0xff, 0xb2, 0x16, 0x64, 0xef, 0xa5, 0x4f, 0x04, 0xef, 0x56, 0x26, 0x1a, 0xef, 0x5c, 0x86, 0x20, 0xef, 0xf2, 0xe6, 0x46, 0xff, 0xf8, 0x46, 0x5c, 0xff, 0xfe, 0xa6, 0x2e, 0xff, 0x70, 0xc6, 0x6a, 0xef, 0x42, 0x2f, 0x04, 0xef, 0x56, 0x46, 0x1a, 0xef, 0x5c, 0xa6, 0x60, 0xef, 0xf2, 0x06, 0x46, 0xff, 0xd4, 0x66, 0x18, 0xff, 0x5a, 0x86, 0x2e, 0xff, 0x70, 0xe6, 0x24, 0xef, 0x42, 0x4f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmax.s8 d1, d2, d3" + - + asm_text: "vmax.s16 d4, d5, d6" + - + asm_text: "vmax.s32 d7, d8, d9" + - + asm_text: "vmax.u8 d10, d11, d12" + - + asm_text: "vmax.u16 d13, d14, d15" + - + asm_text: "vmax.u32 d16, d17, d18" + - + asm_text: "vmax.f32 d19, d20, d21" + - + asm_text: "vmax.s8 d2, d2, d3" + - + asm_text: "vmax.s16 d5, d5, d6" + - + asm_text: "vmax.s32 d8, d8, d9" + - + asm_text: "vmax.u8 d11, d11, d12" + - + asm_text: "vmax.u16 d14, d14, d15" + - + asm_text: "vmax.u32 d17, d17, d18" + - + asm_text: "vmax.f32 d20, d20, d21" + - + asm_text: "vmax.s8 q1, q2, q3" + - + asm_text: "vmax.s16 q4, q5, q6" + - + asm_text: "vmax.s32 q7, q8, q9" + - + asm_text: "vmax.u8 q10, q11, q12" + - + asm_text: "vmax.u16 q13, q14, q15" + - + asm_text: "vmax.u32 q6, q7, q8" + - + asm_text: "vmax.f32 q9, q5, q1" + - + asm_text: "vmax.s8 q2, q2, q3" + - + asm_text: "vmax.s16 q5, q5, q6" + - + asm_text: "vmax.s32 q8, q8, q9" + - + asm_text: "vmax.u8 q11, q11, q2" + - + asm_text: "vmax.u16 q4, q4, q5" + - + asm_text: "vmax.u32 q7, q7, q8" + - + asm_text: "vmax.f32 q2, q2, q1" + - + asm_text: "vmin.s8 d1, d2, d3" + - + asm_text: "vmin.s16 d4, d5, d6" + - + asm_text: "vmin.s32 d7, d8, d9" + - + asm_text: "vmin.u8 d10, d11, d12" + - + asm_text: "vmin.u16 d13, d14, d15" + - + asm_text: "vmin.u32 d16, d17, d18" + - + asm_text: "vmin.f32 d19, d20, d21" + - + asm_text: "vmin.s8 d2, d2, d3" + - + asm_text: "vmin.s16 d5, d5, d6" + - + asm_text: "vmin.s32 d8, d8, d9" + - + asm_text: "vmin.u8 d11, d11, d12" + - + asm_text: "vmin.u16 d14, d14, d15" + - + asm_text: "vmin.u32 d17, d17, d18" + - + asm_text: "vmin.f32 d20, d20, d21" + - + asm_text: "vmin.s8 q1, q2, q3" + - + asm_text: "vmin.s16 q4, q5, q6" + - + asm_text: "vmin.s32 q7, q8, q9" + - + asm_text: "vmin.u8 q10, q11, q12" + - + asm_text: "vmin.u16 q13, q14, q15" + - + asm_text: "vmin.u32 q6, q7, q8" + - + asm_text: "vmin.f32 q9, q5, q1" + - + asm_text: "vmin.s8 q2, q2, q3" + - + asm_text: "vmin.s16 q5, q5, q6" + - + asm_text: "vmin.s32 q8, q8, q9" + - + asm_text: "vmin.u8 q11, q11, q2" + - + asm_text: "vmin.u16 q4, q4, q5" + - + asm_text: "vmin.u32 q7, q7, q8" + - + asm_text: "vmin.f32 q2, q2, q1" diff --git a/tests/MC/ARM/neont2-mov-encoding.s.yaml b/tests/MC/ARM/neont2-mov-encoding.s.yaml new file mode 100644 index 0000000000..c0b06abc1d --- /dev/null +++ b/tests/MC/ARM/neont2-mov-encoding.s.yaml @@ -0,0 +1,122 @@ +test_cases: + - + input: + bytes: [ 0xc0, 0xef, 0x18, 0x0e, 0xc1, 0xef, 0x10, 0x08, 0xc1, 0xef, 0x10, 0x0a, 0xc2, 0xef, 0x10, 0x00, 0xc2, 0xef, 0x10, 0x02, 0xc2, 0xef, 0x10, 0x04, 0xc2, 0xef, 0x10, 0x06, 0xc2, 0xef, 0x10, 0x0c, 0xc2, 0xef, 0x10, 0x0d, 0xc1, 0xff, 0x33, 0x0e, 0xc0, 0xef, 0x58, 0x0e, 0xc1, 0xef, 0x50, 0x08, 0xc1, 0xef, 0x50, 0x0a, 0xc2, 0xef, 0x50, 0x00, 0xc2, 0xef, 0x50, 0x02, 0xc2, 0xef, 0x50, 0x04, 0xc2, 0xef, 0x50, 0x06, 0xc2, 0xef, 0x50, 0x0c, 0xc2, 0xef, 0x50, 0x0d, 0xc1, 0xff, 0x73, 0x0e, 0xc1, 0xef, 0x30, 0x08, 0xc1, 0xef, 0x30, 0x0a, 0xc2, 0xef, 0x30, 0x00, 0xc2, 0xef, 0x30, 0x02, 0xc2, 0xef, 0x30, 0x04, 0xc2, 0xef, 0x30, 0x06, 0xc2, 0xef, 0x30, 0x0c, 0xc2, 0xef, 0x30, 0x0d, 0xc8, 0xef, 0x30, 0x0a, 0xd0, 0xef, 0x30, 0x0a, 0xe0, 0xef, 0x30, 0x0a, 0xc8, 0xff, 0x30, 0x0a, 0xd0, 0xff, 0x30, 0x0a, 0xe0, 0xff, 0x30, 0x0a, 0xf2, 0xff, 0x20, 0x02, 0xf6, 0xff, 0x20, 0x02, 0xfa, 0xff, 0x20, 0x02, 0xf2, 0xff, 0xa0, 0x02, 0xf6, 0xff, 0xa0, 0x02, 0xfa, 0xff, 0xa0, 0x02, 0xf2, 0xff, 0xe0, 0x02, 0xf6, 0xff, 0xe0, 0x02, 0xfa, 0xff, 0xe0, 0x02, 0xf2, 0xff, 0x60, 0x02, 0xf6, 0xff, 0x60, 0x02, 0xfa, 0xff, 0x60, 0x02, 0x50, 0xee, 0xb0, 0x0b, 0x10, 0xee, 0xf0, 0x0b, 0xd0, 0xee, 0xb0, 0x0b, 0x90, 0xee, 0xf0, 0x0b, 0x30, 0xee, 0x90, 0x0b, 0x40, 0xee, 0xb0, 0x1b, 0x00, 0xee, 0xf0, 0x1b, 0x20, 0xee, 0x90, 0x1b, 0x42, 0xee, 0xb0, 0x1b, 0x02, 0xee, 0xf0, 0x1b, 0x22, 0xee, 0x90, 0x1b ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmov.i8 d16, #0x8" + - + asm_text: "vmov.i16 d16, #0x10" + - + asm_text: "vmov.i16 d16, #0x1000" + - + asm_text: "vmov.i32 d16, #0x20" + - + asm_text: "vmov.i32 d16, #0x2000" + - + asm_text: "vmov.i32 d16, #0x200000" + - + asm_text: "vmov.i32 d16, #0x20000000" + - + asm_text: "vmov.i32 d16, #0x20ff" + - + asm_text: "vmov.i32 d16, #0x20ffff" + - + asm_text: "vmov.i64 d16, #0xff0000ff0000ffff" + - + asm_text: "vmov.i8 q8, #0x8" + - + asm_text: "vmov.i16 q8, #0x10" + - + asm_text: "vmov.i16 q8, #0x1000" + - + asm_text: "vmov.i32 q8, #0x20" + - + asm_text: "vmov.i32 q8, #0x2000" + - + asm_text: "vmov.i32 q8, #0x200000" + - + asm_text: "vmov.i32 q8, #0x20000000" + - + asm_text: "vmov.i32 q8, #0x20ff" + - + asm_text: "vmov.i32 q8, #0x20ffff" + - + asm_text: "vmov.i64 q8, #0xff0000ff0000ffff" + - + asm_text: "vmvn.i16 d16, #0x10" + - + asm_text: "vmvn.i16 d16, #0x1000" + - + asm_text: "vmvn.i32 d16, #0x20" + - + asm_text: "vmvn.i32 d16, #0x2000" + - + asm_text: "vmvn.i32 d16, #0x200000" + - + asm_text: "vmvn.i32 d16, #0x20000000" + - + asm_text: "vmvn.i32 d16, #0x20ff" + - + asm_text: "vmvn.i32 d16, #0x20ffff" + - + asm_text: "vmovl.s8 q8, d16" + - + asm_text: "vmovl.s16 q8, d16" + - + asm_text: "vmovl.s32 q8, d16" + - + asm_text: "vmovl.u8 q8, d16" + - + asm_text: "vmovl.u16 q8, d16" + - + asm_text: "vmovl.u32 q8, d16" + - + asm_text: "vmovn.i16 d16, q8" + - + asm_text: "vmovn.i32 d16, q8" + - + asm_text: "vmovn.i64 d16, q8" + - + asm_text: "vqmovn.s16 d16, q8" + - + asm_text: "vqmovn.s32 d16, q8" + - + asm_text: "vqmovn.s64 d16, q8" + - + asm_text: "vqmovn.u16 d16, q8" + - + asm_text: "vqmovn.u32 d16, q8" + - + asm_text: "vqmovn.u64 d16, q8" + - + asm_text: "vqmovun.s16 d16, q8" + - + asm_text: "vqmovun.s32 d16, q8" + - + asm_text: "vqmovun.s64 d16, q8" + - + asm_text: "vmov.s8 r0, d16[1]" + - + asm_text: "vmov.s16 r0, d16[1]" + - + asm_text: "vmov.u8 r0, d16[1]" + - + asm_text: "vmov.u16 r0, d16[1]" + - + asm_text: "vmov.32 r0, d16[1]" + - + asm_text: "vmov.8 d16[1], r1" + - + asm_text: "vmov.16 d16[1], r1" + - + asm_text: "vmov.32 d16[1], r1" + - + asm_text: "vmov.8 d18[1], r1" + - + asm_text: "vmov.16 d18[1], r1" + - + asm_text: "vmov.32 d18[1], r1" diff --git a/tests/MC/ARM/neont2-mul-accum-encoding.s.yaml b/tests/MC/ARM/neont2-mul-accum-encoding.s.yaml new file mode 100644 index 0000000000..d861d51a98 --- /dev/null +++ b/tests/MC/ARM/neont2-mul-accum-encoding.s.yaml @@ -0,0 +1,88 @@ +test_cases: + - + input: + bytes: [ 0x42, 0xef, 0xa1, 0x09, 0x52, 0xef, 0xa1, 0x09, 0x62, 0xef, 0xa1, 0x09, 0x42, 0xef, 0xb1, 0x0d, 0x40, 0xef, 0xe4, 0x29, 0x50, 0xef, 0xe4, 0x29, 0x60, 0xef, 0xe4, 0x29, 0x40, 0xef, 0xf4, 0x2d, 0xe0, 0xff, 0xc3, 0x80, 0xc3, 0xef, 0xa2, 0x08, 0xd3, 0xef, 0xa2, 0x08, 0xe3, 0xef, 0xa2, 0x08, 0xc3, 0xff, 0xa2, 0x08, 0xd3, 0xff, 0xa2, 0x08, 0xe3, 0xff, 0xa2, 0x08, 0xa5, 0xef, 0x4a, 0x02, 0xd3, 0xef, 0xa2, 0x09, 0xe3, 0xef, 0xa2, 0x09, 0xdb, 0xef, 0x47, 0x63, 0xdb, 0xef, 0x4f, 0x63, 0xdb, 0xef, 0x67, 0x63, 0xdb, 0xef, 0x6f, 0x63, 0x42, 0xff, 0xa1, 0x09, 0x52, 0xff, 0xa1, 0x09, 0x62, 0xff, 0xa1, 0x09, 0x62, 0xef, 0xb1, 0x0d, 0x40, 0xff, 0xe4, 0x29, 0x50, 0xff, 0xe4, 0x29, 0x60, 0xff, 0xe4, 0x29, 0x60, 0xef, 0xf4, 0x2d, 0x98, 0xff, 0xe6, 0x84, 0xc3, 0xef, 0xa2, 0x0a, 0xd3, 0xef, 0xa2, 0x0a, 0xe3, 0xef, 0xa2, 0x0a, 0xc3, 0xff, 0xa2, 0x0a, 0xd3, 0xff, 0xa2, 0x0a, 0xe3, 0xff, 0xa2, 0x0a, 0xd9, 0xff, 0xe9, 0x66, 0xd3, 0xef, 0xa2, 0x0b, 0xe3, 0xef, 0xa2, 0x0b ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmla.i8 d16, d18, d17" + - + asm_text: "vmla.i16 d16, d18, d17" + - + asm_text: "vmla.i32 d16, d18, d17" + - + asm_text: "vmla.f32 d16, d18, d17" + - + asm_text: "vmla.i8 q9, q8, q10" + - + asm_text: "vmla.i16 q9, q8, q10" + - + asm_text: "vmla.i32 q9, q8, q10" + - + asm_text: "vmla.f32 q9, q8, q10" + - + asm_text: "vmla.i32 q12, q8, d3[0]" + - + asm_text: "vmlal.s8 q8, d19, d18" + - + asm_text: "vmlal.s16 q8, d19, d18" + - + asm_text: "vmlal.s32 q8, d19, d18" + - + asm_text: "vmlal.u8 q8, d19, d18" + - + asm_text: "vmlal.u16 q8, d19, d18" + - + asm_text: "vmlal.u32 q8, d19, d18" + - + asm_text: "vmlal.s32 q0, d5, d10[0]" + - + asm_text: "vqdmlal.s16 q8, d19, d18" + - + asm_text: "vqdmlal.s32 q8, d19, d18" + - + asm_text: "vqdmlal.s16 q11, d11, d7[0]" + - + asm_text: "vqdmlal.s16 q11, d11, d7[1]" + - + asm_text: "vqdmlal.s16 q11, d11, d7[2]" + - + asm_text: "vqdmlal.s16 q11, d11, d7[3]" + - + asm_text: "vmls.i8 d16, d18, d17" + - + asm_text: "vmls.i16 d16, d18, d17" + - + asm_text: "vmls.i32 d16, d18, d17" + - + asm_text: "vmls.f32 d16, d18, d17" + - + asm_text: "vmls.i8 q9, q8, q10" + - + asm_text: "vmls.i16 q9, q8, q10" + - + asm_text: "vmls.i32 q9, q8, q10" + - + asm_text: "vmls.f32 q9, q8, q10" + - + asm_text: "vmls.i16 q4, q12, d6[2]" + - + asm_text: "vmlsl.s8 q8, d19, d18" + - + asm_text: "vmlsl.s16 q8, d19, d18" + - + asm_text: "vmlsl.s32 q8, d19, d18" + - + asm_text: "vmlsl.u8 q8, d19, d18" + - + asm_text: "vmlsl.u16 q8, d19, d18" + - + asm_text: "vmlsl.u32 q8, d19, d18" + - + asm_text: "vmlsl.u16 q11, d25, d1[3]" + - + asm_text: "vqdmlsl.s16 q8, d19, d18" + - + asm_text: "vqdmlsl.s32 q8, d19, d18" diff --git a/tests/MC/ARM/neont2-mul-encoding.s.yaml b/tests/MC/ARM/neont2-mul-encoding.s.yaml new file mode 100644 index 0000000000..eb2b66b619 --- /dev/null +++ b/tests/MC/ARM/neont2-mul-encoding.s.yaml @@ -0,0 +1,68 @@ +test_cases: + - + input: + bytes: [ 0x40, 0xef, 0xb1, 0x09, 0x50, 0xef, 0xb1, 0x09, 0x60, 0xef, 0xb1, 0x09, 0x40, 0xff, 0xb1, 0x0d, 0x40, 0xef, 0xf2, 0x09, 0x50, 0xef, 0xf2, 0x09, 0x60, 0xef, 0xf2, 0x09, 0x40, 0xff, 0xf2, 0x0d, 0x40, 0xff, 0xb1, 0x09, 0x40, 0xff, 0xf2, 0x09, 0xd8, 0xef, 0x68, 0x28, 0x50, 0xef, 0xa1, 0x0b, 0x60, 0xef, 0xa1, 0x0b, 0x50, 0xef, 0xe2, 0x0b, 0x60, 0xef, 0xe2, 0x0b, 0x92, 0xef, 0x43, 0xbc, 0x50, 0xff, 0xa1, 0x0b, 0x60, 0xff, 0xa1, 0x0b, 0x50, 0xff, 0xe2, 0x0b, 0x60, 0xff, 0xe2, 0x0b, 0xc0, 0xef, 0xa1, 0x0c, 0xd0, 0xef, 0xa1, 0x0c, 0xe0, 0xef, 0xa1, 0x0c, 0xc0, 0xff, 0xa1, 0x0c, 0xd0, 0xff, 0xa1, 0x0c, 0xe0, 0xff, 0xa1, 0x0c, 0xc0, 0xef, 0xa1, 0x0e, 0xd0, 0xef, 0xa1, 0x0d, 0xe0, 0xef, 0xa1, 0x0d, 0x97, 0xef, 0x49, 0x2b ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmul.i8 d16, d16, d17" + - + asm_text: "vmul.i16 d16, d16, d17" + - + asm_text: "vmul.i32 d16, d16, d17" + - + asm_text: "vmul.f32 d16, d16, d17" + - + asm_text: "vmul.i8 q8, q8, q9" + - + asm_text: "vmul.i16 q8, q8, q9" + - + asm_text: "vmul.i32 q8, q8, q9" + - + asm_text: "vmul.f32 q8, q8, q9" + - + asm_text: "vmul.p8 d16, d16, d17" + - + asm_text: "vmul.p8 q8, q8, q9" + - + asm_text: "vmul.i16 d18, d8, d0[3]" + - + asm_text: "vqdmulh.s16 d16, d16, d17" + - + asm_text: "vqdmulh.s32 d16, d16, d17" + - + asm_text: "vqdmulh.s16 q8, q8, q9" + - + asm_text: "vqdmulh.s32 q8, q8, q9" + - + asm_text: "vqdmulh.s16 d11, d2, d3[0]" + - + asm_text: "vqrdmulh.s16 d16, d16, d17" + - + asm_text: "vqrdmulh.s32 d16, d16, d17" + - + asm_text: "vqrdmulh.s16 q8, q8, q9" + - + asm_text: "vqrdmulh.s32 q8, q8, q9" + - + asm_text: "vmull.s8 q8, d16, d17" + - + asm_text: "vmull.s16 q8, d16, d17" + - + asm_text: "vmull.s32 q8, d16, d17" + - + asm_text: "vmull.u8 q8, d16, d17" + - + asm_text: "vmull.u16 q8, d16, d17" + - + asm_text: "vmull.u32 q8, d16, d17" + - + asm_text: "vmull.p8 q8, d16, d17" + - + asm_text: "vqdmull.s16 q8, d16, d17" + - + asm_text: "vqdmull.s32 q8, d16, d17" + - + asm_text: "vqdmull.s16 q1, d7, d1[1]" diff --git a/tests/MC/ARM/neont2-neg-encoding.s.yaml b/tests/MC/ARM/neont2-neg-encoding.s.yaml new file mode 100644 index 0000000000..0e303dd5e2 --- /dev/null +++ b/tests/MC/ARM/neont2-neg-encoding.s.yaml @@ -0,0 +1,36 @@ +test_cases: + - + input: + bytes: [ 0xf1, 0xff, 0xa0, 0x03, 0xf5, 0xff, 0xa0, 0x03, 0xf9, 0xff, 0xa0, 0x03, 0xf9, 0xff, 0xa0, 0x07, 0xf1, 0xff, 0xe0, 0x03, 0xf5, 0xff, 0xe0, 0x03, 0xf9, 0xff, 0xe0, 0x03, 0xf9, 0xff, 0xe0, 0x07, 0xf0, 0xff, 0xa0, 0x07, 0xf4, 0xff, 0xa0, 0x07, 0xf8, 0xff, 0xa0, 0x07, 0xf0, 0xff, 0xe0, 0x07, 0xf4, 0xff, 0xe0, 0x07, 0xf8, 0xff, 0xe0, 0x07 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vneg.s8 d16, d16" + - + asm_text: "vneg.s16 d16, d16" + - + asm_text: "vneg.s32 d16, d16" + - + asm_text: "vneg.f32 d16, d16" + - + asm_text: "vneg.s8 q8, q8" + - + asm_text: "vneg.s16 q8, q8" + - + asm_text: "vneg.s32 q8, q8" + - + asm_text: "vneg.f32 q8, q8" + - + asm_text: "vqneg.s8 d16, d16" + - + asm_text: "vqneg.s16 d16, d16" + - + asm_text: "vqneg.s32 d16, d16" + - + asm_text: "vqneg.s8 q8, q8" + - + asm_text: "vqneg.s16 q8, q8" + - + asm_text: "vqneg.s32 q8, q8" diff --git a/tests/MC/ARM/neont2-pairwise-encoding.s.yaml b/tests/MC/ARM/neont2-pairwise-encoding.s.yaml new file mode 100644 index 0000000000..b7fb1c8e58 --- /dev/null +++ b/tests/MC/ARM/neont2-pairwise-encoding.s.yaml @@ -0,0 +1,92 @@ +test_cases: + - + input: + bytes: [ 0x05, 0xef, 0x1b, 0x1b, 0x12, 0xef, 0x1c, 0xdb, 0x21, 0xef, 0x1d, 0xeb, 0x40, 0xff, 0x8e, 0x3d, 0xb0, 0xff, 0x0a, 0x72, 0xb4, 0xff, 0x0b, 0x82, 0xb8, 0xff, 0x0c, 0x92, 0xb0, 0xff, 0x8d, 0x02, 0xb4, 0xff, 0x8e, 0x52, 0xb8, 0xff, 0x8f, 0x62, 0xb0, 0xff, 0x4e, 0x82, 0xb4, 0xff, 0x4c, 0xa2, 0xb8, 0xff, 0x4a, 0xc2, 0xb0, 0xff, 0xc8, 0xe2, 0xf4, 0xff, 0xc6, 0x02, 0xf8, 0xff, 0xc4, 0x22, 0xf0, 0xff, 0x04, 0x06, 0xf4, 0xff, 0x09, 0x46, 0xf8, 0xff, 0x01, 0x26, 0xb0, 0xff, 0xa9, 0xe6, 0xb4, 0xff, 0x86, 0xc6, 0xb8, 0xff, 0x87, 0xb6, 0xb0, 0xff, 0x64, 0x86, 0xb4, 0xff, 0x66, 0xa6, 0xb8, 0xff, 0x68, 0xc6, 0xb0, 0xff, 0xea, 0xe6, 0xf4, 0xff, 0xec, 0x06, 0xf8, 0xff, 0xee, 0x26, 0x4d, 0xef, 0x9a, 0x0a, 0x5c, 0xef, 0x9b, 0x1a, 0x6b, 0xef, 0x9c, 0x2a, 0x4a, 0xff, 0x9d, 0x3a, 0x59, 0xff, 0x9e, 0x4a, 0x68, 0xff, 0x9f, 0x5a, 0x67, 0xff, 0xa0, 0x6f, 0x04, 0xef, 0xa1, 0x3a, 0x15, 0xef, 0xa0, 0x4a, 0x26, 0xef, 0x8f, 0x5a, 0x07, 0xff, 0x8e, 0x6a, 0x18, 0xff, 0x8d, 0x7a, 0x29, 0xff, 0x8c, 0x8a, 0x0a, 0xff, 0x8b, 0x9f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vpadd.i8 d1, d5, d11" + - + asm_text: "vpadd.i16 d13, d2, d12" + - + asm_text: "vpadd.i32 d14, d1, d13" + - + asm_text: "vpadd.f32 d19, d16, d14" + - + asm_text: "vpaddl.s8 d7, d10" + - + asm_text: "vpaddl.s16 d8, d11" + - + asm_text: "vpaddl.s32 d9, d12" + - + asm_text: "vpaddl.u8 d0, d13" + - + asm_text: "vpaddl.u16 d5, d14" + - + asm_text: "vpaddl.u32 d6, d15" + - + asm_text: "vpaddl.s8 q4, q7" + - + asm_text: "vpaddl.s16 q5, q6" + - + asm_text: "vpaddl.s32 q6, q5" + - + asm_text: "vpaddl.u8 q7, q4" + - + asm_text: "vpaddl.u16 q8, q3" + - + asm_text: "vpaddl.u32 q9, q2" + - + asm_text: "vpadal.s8 d16, d4" + - + asm_text: "vpadal.s16 d20, d9" + - + asm_text: "vpadal.s32 d18, d1" + - + asm_text: "vpadal.u8 d14, d25" + - + asm_text: "vpadal.u16 d12, d6" + - + asm_text: "vpadal.u32 d11, d7" + - + asm_text: "vpadal.s8 q4, q10" + - + asm_text: "vpadal.s16 q5, q11" + - + asm_text: "vpadal.s32 q6, q12" + - + asm_text: "vpadal.u8 q7, q13" + - + asm_text: "vpadal.u16 q8, q14" + - + asm_text: "vpadal.u32 q9, q15" + - + asm_text: "vpmin.s8 d16, d29, d10" + - + asm_text: "vpmin.s16 d17, d28, d11" + - + asm_text: "vpmin.s32 d18, d27, d12" + - + asm_text: "vpmin.u8 d19, d26, d13" + - + asm_text: "vpmin.u16 d20, d25, d14" + - + asm_text: "vpmin.u32 d21, d24, d15" + - + asm_text: "vpmin.f32 d22, d23, d16" + - + asm_text: "vpmax.s8 d3, d20, d17" + - + asm_text: "vpmax.s16 d4, d21, d16" + - + asm_text: "vpmax.s32 d5, d22, d15" + - + asm_text: "vpmax.u8 d6, d23, d14" + - + asm_text: "vpmax.u16 d7, d24, d13" + - + asm_text: "vpmax.u32 d8, d25, d12" + - + asm_text: "vpmax.f32 d9, d26, d11" diff --git a/tests/MC/ARM/neont2-reciprocal-encoding.s.yaml b/tests/MC/ARM/neont2-reciprocal-encoding.s.yaml new file mode 100644 index 0000000000..b44836b58e --- /dev/null +++ b/tests/MC/ARM/neont2-reciprocal-encoding.s.yaml @@ -0,0 +1,32 @@ +test_cases: + - + input: + bytes: [ 0xfb, 0xff, 0x20, 0x04, 0xfb, 0xff, 0x60, 0x04, 0xfb, 0xff, 0x20, 0x05, 0xfb, 0xff, 0x60, 0x05, 0x40, 0xef, 0xb1, 0x0f, 0x40, 0xef, 0xf2, 0x0f, 0xfb, 0xff, 0xa0, 0x04, 0xfb, 0xff, 0xe0, 0x04, 0xfb, 0xff, 0xa0, 0x05, 0xfb, 0xff, 0xe0, 0x05, 0x60, 0xef, 0xb1, 0x0f, 0x60, 0xef, 0xf2, 0x0f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vrecpe.u32 d16, d16" + - + asm_text: "vrecpe.u32 q8, q8" + - + asm_text: "vrecpe.f32 d16, d16" + - + asm_text: "vrecpe.f32 q8, q8" + - + asm_text: "vrecps.f32 d16, d16, d17" + - + asm_text: "vrecps.f32 q8, q8, q9" + - + asm_text: "vrsqrte.u32 d16, d16" + - + asm_text: "vrsqrte.u32 q8, q8" + - + asm_text: "vrsqrte.f32 d16, d16" + - + asm_text: "vrsqrte.f32 q8, q8" + - + asm_text: "vrsqrts.f32 d16, d16, d17" + - + asm_text: "vrsqrts.f32 q8, q8, q9" diff --git a/tests/MC/ARM/neont2-reverse-encoding.s.yaml b/tests/MC/ARM/neont2-reverse-encoding.s.yaml new file mode 100644 index 0000000000..d02f9b107b --- /dev/null +++ b/tests/MC/ARM/neont2-reverse-encoding.s.yaml @@ -0,0 +1,32 @@ +test_cases: + - + input: + bytes: [ 0xf0, 0xff, 0x20, 0x00, 0xf4, 0xff, 0x20, 0x00, 0xf8, 0xff, 0x20, 0x00, 0xf0, 0xff, 0x60, 0x00, 0xf4, 0xff, 0x60, 0x00, 0xf8, 0xff, 0x60, 0x00, 0xf0, 0xff, 0xa0, 0x00, 0xf4, 0xff, 0xa0, 0x00, 0xf0, 0xff, 0xe0, 0x00, 0xf4, 0xff, 0xe0, 0x00, 0xf0, 0xff, 0x20, 0x01, 0xf0, 0xff, 0x60, 0x01 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vrev64.8 d16, d16" + - + asm_text: "vrev64.16 d16, d16" + - + asm_text: "vrev64.32 d16, d16" + - + asm_text: "vrev64.8 q8, q8" + - + asm_text: "vrev64.16 q8, q8" + - + asm_text: "vrev64.32 q8, q8" + - + asm_text: "vrev32.8 d16, d16" + - + asm_text: "vrev32.16 d16, d16" + - + asm_text: "vrev32.8 q8, q8" + - + asm_text: "vrev32.16 q8, q8" + - + asm_text: "vrev16.8 d16, d16" + - + asm_text: "vrev16.8 q8, q8" diff --git a/tests/MC/ARM/neont2-satshift-encoding.s.yaml b/tests/MC/ARM/neont2-satshift-encoding.s.yaml new file mode 100644 index 0000000000..8fb2e124f7 --- /dev/null +++ b/tests/MC/ARM/neont2-satshift-encoding.s.yaml @@ -0,0 +1,156 @@ +test_cases: + - + input: + bytes: [ 0x41, 0xef, 0xb0, 0x04, 0x51, 0xef, 0xb0, 0x04, 0x61, 0xef, 0xb0, 0x04, 0x71, 0xef, 0xb0, 0x04, 0x41, 0xff, 0xb0, 0x04, 0x51, 0xff, 0xb0, 0x04, 0x61, 0xff, 0xb0, 0x04, 0x71, 0xff, 0xb0, 0x04, 0x42, 0xef, 0xf0, 0x04, 0x52, 0xef, 0xf0, 0x04, 0x62, 0xef, 0xf0, 0x04, 0x72, 0xef, 0xf0, 0x04, 0x42, 0xff, 0xf0, 0x04, 0x52, 0xff, 0xf0, 0x04, 0x62, 0xff, 0xf0, 0x04, 0x72, 0xff, 0xf0, 0x04, 0xcf, 0xef, 0x30, 0x07, 0xdf, 0xef, 0x30, 0x07, 0xff, 0xef, 0x30, 0x07, 0xff, 0xef, 0xb0, 0x07, 0xcf, 0xff, 0x30, 0x07, 0xdf, 0xff, 0x30, 0x07, 0xff, 0xff, 0x30, 0x07, 0xff, 0xff, 0xb0, 0x07, 0xcf, 0xff, 0x30, 0x06, 0xdf, 0xff, 0x30, 0x06, 0xff, 0xff, 0x30, 0x06, 0xff, 0xff, 0xb0, 0x06, 0xcf, 0xef, 0x70, 0x07, 0xdf, 0xef, 0x70, 0x07, 0xff, 0xef, 0x70, 0x07, 0xff, 0xef, 0xf0, 0x07, 0xcf, 0xff, 0x70, 0x07, 0xdf, 0xff, 0x70, 0x07, 0xff, 0xff, 0x70, 0x07, 0xff, 0xff, 0xf0, 0x07, 0xcf, 0xff, 0x70, 0x06, 0xdf, 0xff, 0x70, 0x06, 0xff, 0xff, 0x70, 0x06, 0xff, 0xff, 0xf0, 0x06, 0x41, 0xef, 0xb0, 0x05, 0x51, 0xef, 0xb0, 0x05, 0x61, 0xef, 0xb0, 0x05, 0x71, 0xef, 0xb0, 0x05, 0x41, 0xff, 0xb0, 0x05, 0x51, 0xff, 0xb0, 0x05, 0x61, 0xff, 0xb0, 0x05, 0x71, 0xff, 0xb0, 0x05, 0x42, 0xef, 0xf0, 0x05, 0x52, 0xef, 0xf0, 0x05, 0x62, 0xef, 0xf0, 0x05, 0x72, 0xef, 0xf0, 0x05, 0x42, 0xff, 0xf0, 0x05, 0x52, 0xff, 0xf0, 0x05, 0x62, 0xff, 0xf0, 0x05, 0x72, 0xff, 0xf0, 0x05, 0xc8, 0xef, 0x30, 0x09, 0xd0, 0xef, 0x30, 0x09, 0xe0, 0xef, 0x30, 0x09, 0xc8, 0xff, 0x30, 0x09, 0xd0, 0xff, 0x30, 0x09, 0xe0, 0xff, 0x30, 0x09, 0xc8, 0xff, 0x30, 0x08, 0xd0, 0xff, 0x30, 0x08, 0xe0, 0xff, 0x30, 0x08, 0xc8, 0xef, 0x70, 0x09, 0xd0, 0xef, 0x70, 0x09, 0xe0, 0xef, 0x70, 0x09, 0xc8, 0xff, 0x70, 0x09, 0xd0, 0xff, 0x70, 0x09, 0xe0, 0xff, 0x70, 0x09, 0xc8, 0xff, 0x70, 0x08, 0xd0, 0xff, 0x70, 0x08, 0xe0, 0xff, 0x70, 0x08 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vqshl.s8 d16, d16, d17" + - + asm_text: "vqshl.s16 d16, d16, d17" + - + asm_text: "vqshl.s32 d16, d16, d17" + - + asm_text: "vqshl.s64 d16, d16, d17" + - + asm_text: "vqshl.u8 d16, d16, d17" + - + asm_text: "vqshl.u16 d16, d16, d17" + - + asm_text: "vqshl.u32 d16, d16, d17" + - + asm_text: "vqshl.u64 d16, d16, d17" + - + asm_text: "vqshl.s8 q8, q8, q9" + - + asm_text: "vqshl.s16 q8, q8, q9" + - + asm_text: "vqshl.s32 q8, q8, q9" + - + asm_text: "vqshl.s64 q8, q8, q9" + - + asm_text: "vqshl.u8 q8, q8, q9" + - + asm_text: "vqshl.u16 q8, q8, q9" + - + asm_text: "vqshl.u32 q8, q8, q9" + - + asm_text: "vqshl.u64 q8, q8, q9" + - + asm_text: "vqshl.s8 d16, d16, #7" + - + asm_text: "vqshl.s16 d16, d16, #0xf" + - + asm_text: "vqshl.s32 d16, d16, #0x1f" + - + asm_text: "vqshl.s64 d16, d16, #0x3f" + - + asm_text: "vqshl.u8 d16, d16, #7" + - + asm_text: "vqshl.u16 d16, d16, #0xf" + - + asm_text: "vqshl.u32 d16, d16, #0x1f" + - + asm_text: "vqshl.u64 d16, d16, #0x3f" + - + asm_text: "vqshlu.s8 d16, d16, #7" + - + asm_text: "vqshlu.s16 d16, d16, #0xf" + - + asm_text: "vqshlu.s32 d16, d16, #0x1f" + - + asm_text: "vqshlu.s64 d16, d16, #0x3f" + - + asm_text: "vqshl.s8 q8, q8, #7" + - + asm_text: "vqshl.s16 q8, q8, #0xf" + - + asm_text: "vqshl.s32 q8, q8, #0x1f" + - + asm_text: "vqshl.s64 q8, q8, #0x3f" + - + asm_text: "vqshl.u8 q8, q8, #7" + - + asm_text: "vqshl.u16 q8, q8, #0xf" + - + asm_text: "vqshl.u32 q8, q8, #0x1f" + - + asm_text: "vqshl.u64 q8, q8, #0x3f" + - + asm_text: "vqshlu.s8 q8, q8, #7" + - + asm_text: "vqshlu.s16 q8, q8, #0xf" + - + asm_text: "vqshlu.s32 q8, q8, #0x1f" + - + asm_text: "vqshlu.s64 q8, q8, #0x3f" + - + asm_text: "vqrshl.s8 d16, d16, d17" + - + asm_text: "vqrshl.s16 d16, d16, d17" + - + asm_text: "vqrshl.s32 d16, d16, d17" + - + asm_text: "vqrshl.s64 d16, d16, d17" + - + asm_text: "vqrshl.u8 d16, d16, d17" + - + asm_text: "vqrshl.u16 d16, d16, d17" + - + asm_text: "vqrshl.u32 d16, d16, d17" + - + asm_text: "vqrshl.u64 d16, d16, d17" + - + asm_text: "vqrshl.s8 q8, q8, q9" + - + asm_text: "vqrshl.s16 q8, q8, q9" + - + asm_text: "vqrshl.s32 q8, q8, q9" + - + asm_text: "vqrshl.s64 q8, q8, q9" + - + asm_text: "vqrshl.u8 q8, q8, q9" + - + asm_text: "vqrshl.u16 q8, q8, q9" + - + asm_text: "vqrshl.u32 q8, q8, q9" + - + asm_text: "vqrshl.u64 q8, q8, q9" + - + asm_text: "vqshrn.s16 d16, q8, #8" + - + asm_text: "vqshrn.s32 d16, q8, #0x10" + - + asm_text: "vqshrn.s64 d16, q8, #0x20" + - + asm_text: "vqshrn.u16 d16, q8, #8" + - + asm_text: "vqshrn.u32 d16, q8, #0x10" + - + asm_text: "vqshrn.u64 d16, q8, #0x20" + - + asm_text: "vqshrun.s16 d16, q8, #8" + - + asm_text: "vqshrun.s32 d16, q8, #0x10" + - + asm_text: "vqshrun.s64 d16, q8, #0x20" + - + asm_text: "vqrshrn.s16 d16, q8, #8" + - + asm_text: "vqrshrn.s32 d16, q8, #0x10" + - + asm_text: "vqrshrn.s64 d16, q8, #0x20" + - + asm_text: "vqrshrn.u16 d16, q8, #8" + - + asm_text: "vqrshrn.u32 d16, q8, #0x10" + - + asm_text: "vqrshrn.u64 d16, q8, #0x20" + - + asm_text: "vqrshrun.s16 d16, q8, #8" + - + asm_text: "vqrshrun.s32 d16, q8, #0x10" + - + asm_text: "vqrshrun.s64 d16, q8, #0x20" diff --git a/tests/MC/ARM/neont2-shift-encoding.s.yaml b/tests/MC/ARM/neont2-shift-encoding.s.yaml new file mode 100644 index 0000000000..e3643a401c --- /dev/null +++ b/tests/MC/ARM/neont2-shift-encoding.s.yaml @@ -0,0 +1,166 @@ +test_cases: + - + input: + bytes: [ 0x40, 0xff, 0xa1, 0x04, 0x50, 0xff, 0xa1, 0x04, 0x60, 0xff, 0xa1, 0x04, 0x70, 0xff, 0xa1, 0x04, 0xcf, 0xef, 0x30, 0x05, 0xdf, 0xef, 0x30, 0x05, 0xff, 0xef, 0x30, 0x05, 0xff, 0xef, 0xb0, 0x05, 0x40, 0xff, 0xe2, 0x04, 0x50, 0xff, 0xe2, 0x04, 0x60, 0xff, 0xe2, 0x04, 0x70, 0xff, 0xe2, 0x04, 0xcf, 0xef, 0x70, 0x05, 0xdf, 0xef, 0x70, 0x05, 0xff, 0xef, 0x70, 0x05, 0xff, 0xef, 0xf0, 0x05, 0xc8, 0xff, 0x30, 0x00, 0xd0, 0xff, 0x30, 0x00, 0xe0, 0xff, 0x30, 0x00, 0xc0, 0xff, 0xb0, 0x00, 0xc8, 0xff, 0x70, 0x00, 0xd0, 0xff, 0x70, 0x00, 0xe0, 0xff, 0x70, 0x00, 0xc0, 0xff, 0xf0, 0x00, 0xc8, 0xef, 0x30, 0x00, 0xd0, 0xef, 0x30, 0x00, 0xe0, 0xef, 0x30, 0x00, 0xc0, 0xef, 0xb0, 0x00, 0xc8, 0xef, 0x70, 0x00, 0xd0, 0xef, 0x70, 0x00, 0xe0, 0xef, 0x70, 0x00, 0xc0, 0xef, 0xf0, 0x00, 0xcf, 0xef, 0x30, 0x0a, 0xdf, 0xef, 0x30, 0x0a, 0xff, 0xef, 0x30, 0x0a, 0xcf, 0xff, 0x30, 0x0a, 0xdf, 0xff, 0x30, 0x0a, 0xff, 0xff, 0x30, 0x0a, 0xf2, 0xff, 0x20, 0x03, 0xf6, 0xff, 0x20, 0x03, 0xfa, 0xff, 0x20, 0x03, 0xc8, 0xef, 0x30, 0x08, 0xd0, 0xef, 0x30, 0x08, 0xe0, 0xef, 0x30, 0x08, 0x40, 0xef, 0xa1, 0x05, 0x50, 0xef, 0xa1, 0x05, 0x60, 0xef, 0xa1, 0x05, 0x70, 0xef, 0xa1, 0x05, 0x40, 0xff, 0xa1, 0x05, 0x50, 0xff, 0xa1, 0x05, 0x60, 0xff, 0xa1, 0x05, 0x70, 0xff, 0xa1, 0x05, 0x40, 0xef, 0xe2, 0x05, 0x50, 0xef, 0xe2, 0x05, 0x60, 0xef, 0xe2, 0x05, 0x70, 0xef, 0xe2, 0x05, 0x40, 0xff, 0xe2, 0x05, 0x50, 0xff, 0xe2, 0x05, 0x60, 0xff, 0xe2, 0x05, 0x70, 0xff, 0xe2, 0x05, 0xc8, 0xef, 0x30, 0x02, 0xd0, 0xef, 0x30, 0x02, 0xe0, 0xef, 0x30, 0x02, 0xc0, 0xef, 0xb0, 0x02, 0xc8, 0xff, 0x30, 0x02, 0xd0, 0xff, 0x30, 0x02, 0xe0, 0xff, 0x30, 0x02, 0xc0, 0xff, 0xb0, 0x02, 0xc8, 0xef, 0x70, 0x02, 0xd0, 0xef, 0x70, 0x02, 0xe0, 0xef, 0x70, 0x02, 0xc0, 0xef, 0xf0, 0x02, 0xc8, 0xff, 0x70, 0x02, 0xd0, 0xff, 0x70, 0x02, 0xe0, 0xff, 0x70, 0x02, 0xc0, 0xff, 0xf0, 0x02, 0xc8, 0xef, 0x70, 0x08, 0xd0, 0xef, 0x70, 0x08, 0xe0, 0xef, 0x70, 0x08 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vshl.u8 d16, d17, d16" + - + asm_text: "vshl.u16 d16, d17, d16" + - + asm_text: "vshl.u32 d16, d17, d16" + - + asm_text: "vshl.u64 d16, d17, d16" + - + asm_text: "vshl.i8 d16, d16, #7" + - + asm_text: "vshl.i16 d16, d16, #0xf" + - + asm_text: "vshl.i32 d16, d16, #0x1f" + - + asm_text: "vshl.i64 d16, d16, #0x3f" + - + asm_text: "vshl.u8 q8, q9, q8" + - + asm_text: "vshl.u16 q8, q9, q8" + - + asm_text: "vshl.u32 q8, q9, q8" + - + asm_text: "vshl.u64 q8, q9, q8" + - + asm_text: "vshl.i8 q8, q8, #7" + - + asm_text: "vshl.i16 q8, q8, #0xf" + - + asm_text: "vshl.i32 q8, q8, #0x1f" + - + asm_text: "vshl.i64 q8, q8, #0x3f" + - + asm_text: "vshr.u8 d16, d16, #8" + - + asm_text: "vshr.u16 d16, d16, #0x10" + - + asm_text: "vshr.u32 d16, d16, #0x20" + - + asm_text: "vshr.u64 d16, d16, #0x40" + - + asm_text: "vshr.u8 q8, q8, #8" + - + asm_text: "vshr.u16 q8, q8, #0x10" + - + asm_text: "vshr.u32 q8, q8, #0x20" + - + asm_text: "vshr.u64 q8, q8, #0x40" + - + asm_text: "vshr.s8 d16, d16, #8" + - + asm_text: "vshr.s16 d16, d16, #0x10" + - + asm_text: "vshr.s32 d16, d16, #0x20" + - + asm_text: "vshr.s64 d16, d16, #0x40" + - + asm_text: "vshr.s8 q8, q8, #8" + - + asm_text: "vshr.s16 q8, q8, #0x10" + - + asm_text: "vshr.s32 q8, q8, #0x20" + - + asm_text: "vshr.s64 q8, q8, #0x40" + - + asm_text: "vshll.s8 q8, d16, #7" + - + asm_text: "vshll.s16 q8, d16, #0xf" + - + asm_text: "vshll.s32 q8, d16, #0x1f" + - + asm_text: "vshll.u8 q8, d16, #7" + - + asm_text: "vshll.u16 q8, d16, #0xf" + - + asm_text: "vshll.u32 q8, d16, #0x1f" + - + asm_text: "vshll.i8 q8, d16, #8" + - + asm_text: "vshll.i16 q8, d16, #0x10" + - + asm_text: "vshll.i32 q8, d16, #0x20" + - + asm_text: "vshrn.i16 d16, q8, #8" + - + asm_text: "vshrn.i32 d16, q8, #0x10" + - + asm_text: "vshrn.i64 d16, q8, #0x20" + - + asm_text: "vrshl.s8 d16, d17, d16" + - + asm_text: "vrshl.s16 d16, d17, d16" + - + asm_text: "vrshl.s32 d16, d17, d16" + - + asm_text: "vrshl.s64 d16, d17, d16" + - + asm_text: "vrshl.u8 d16, d17, d16" + - + asm_text: "vrshl.u16 d16, d17, d16" + - + asm_text: "vrshl.u32 d16, d17, d16" + - + asm_text: "vrshl.u64 d16, d17, d16" + - + asm_text: "vrshl.s8 q8, q9, q8" + - + asm_text: "vrshl.s16 q8, q9, q8" + - + asm_text: "vrshl.s32 q8, q9, q8" + - + asm_text: "vrshl.s64 q8, q9, q8" + - + asm_text: "vrshl.u8 q8, q9, q8" + - + asm_text: "vrshl.u16 q8, q9, q8" + - + asm_text: "vrshl.u32 q8, q9, q8" + - + asm_text: "vrshl.u64 q8, q9, q8" + - + asm_text: "vrshr.s8 d16, d16, #8" + - + asm_text: "vrshr.s16 d16, d16, #0x10" + - + asm_text: "vrshr.s32 d16, d16, #0x20" + - + asm_text: "vrshr.s64 d16, d16, #0x40" + - + asm_text: "vrshr.u8 d16, d16, #8" + - + asm_text: "vrshr.u16 d16, d16, #0x10" + - + asm_text: "vrshr.u32 d16, d16, #0x20" + - + asm_text: "vrshr.u64 d16, d16, #0x40" + - + asm_text: "vrshr.s8 q8, q8, #8" + - + asm_text: "vrshr.s16 q8, q8, #0x10" + - + asm_text: "vrshr.s32 q8, q8, #0x20" + - + asm_text: "vrshr.s64 q8, q8, #0x40" + - + asm_text: "vrshr.u8 q8, q8, #8" + - + asm_text: "vrshr.u16 q8, q8, #0x10" + - + asm_text: "vrshr.u32 q8, q8, #0x20" + - + asm_text: "vrshr.u64 q8, q8, #0x40" + - + asm_text: "vrshrn.i16 d16, q8, #8" + - + asm_text: "vrshrn.i32 d16, q8, #0x10" + - + asm_text: "vrshrn.i64 d16, q8, #0x20" diff --git a/tests/MC/ARM/neont2-shiftaccum-encoding.s.yaml b/tests/MC/ARM/neont2-shiftaccum-encoding.s.yaml new file mode 100644 index 0000000000..79c71a7c32 --- /dev/null +++ b/tests/MC/ARM/neont2-shiftaccum-encoding.s.yaml @@ -0,0 +1,200 @@ +test_cases: + - + input: + bytes: [ 0xc8, 0xef, 0x30, 0x11, 0x90, 0xef, 0x1e, 0xf1, 0xa0, 0xef, 0x1c, 0xd1, 0x80, 0xef, 0x9a, 0xb1, 0x88, 0xef, 0x54, 0xe1, 0x90, 0xef, 0x5c, 0x61, 0xe0, 0xef, 0x5a, 0x21, 0xc0, 0xef, 0xd8, 0x01, 0xc8, 0xff, 0x30, 0x11, 0x95, 0xff, 0x1e, 0xb1, 0xaa, 0xff, 0x1f, 0xc1, 0x8a, 0xff, 0xb0, 0xd1, 0x88, 0xff, 0x5e, 0x21, 0x9a, 0xff, 0x5e, 0x41, 0xab, 0xff, 0x5c, 0x61, 0xa7, 0xff, 0xda, 0x81, 0xc8, 0xef, 0x30, 0x01, 0x90, 0xef, 0x1e, 0xe1, 0xa0, 0xef, 0x1c, 0xc1, 0x80, 0xef, 0x9a, 0xa1, 0x88, 0xef, 0x54, 0x41, 0x90, 0xef, 0x5c, 0xc1, 0xa0, 0xef, 0x5a, 0xa1, 0x80, 0xef, 0xd8, 0x81, 0xc8, 0xff, 0x30, 0x01, 0x95, 0xff, 0x1e, 0xe1, 0xaa, 0xff, 0x1f, 0xf1, 0xca, 0xff, 0xb0, 0x01, 0x88, 0xff, 0x5e, 0xe1, 0x9a, 0xff, 0x5e, 0xe1, 0xab, 0xff, 0x5c, 0xc1, 0xa7, 0xff, 0xda, 0xa1, 0x88, 0xef, 0x3a, 0x53, 0x90, 0xef, 0x39, 0x63, 0xa0, 0xef, 0x38, 0x73, 0x80, 0xef, 0xb7, 0xe3, 0x88, 0xff, 0x36, 0xf3, 0xd0, 0xff, 0x35, 0x03, 0xe0, 0xff, 0x34, 0x13, 0xc0, 0xff, 0xb3, 0x23, 0x88, 0xef, 0x54, 0x23, 0x90, 0xef, 0x56, 0x43, 0xa0, 0xef, 0x58, 0x63, 0x80, 0xef, 0xda, 0x83, 0x88, 0xff, 0x5c, 0xa3, 0x90, 0xff, 0x5e, 0xc3, 0xa0, 0xff, 0x70, 0xe3, 0xc0, 0xff, 0xf2, 0x03, 0xc8, 0xef, 0x3a, 0xa3, 0xd0, 0xef, 0x39, 0x93, 0xe0, 0xef, 0x38, 0x83, 0xc0, 0xef, 0xb7, 0x73, 0xc8, 0xff, 0x36, 0x63, 0xd0, 0xff, 0x35, 0x53, 0xe0, 0xff, 0x34, 0x43, 0xc0, 0xff, 0xb3, 0x33, 0x88, 0xef, 0x54, 0x43, 0x90, 0xef, 0x56, 0x63, 0xa0, 0xef, 0x58, 0x83, 0x80, 0xef, 0xda, 0xa3, 0x88, 0xff, 0x5c, 0xc3, 0x90, 0xff, 0x5e, 0xe3, 0xe0, 0xff, 0x70, 0x03, 0xc0, 0xff, 0xf2, 0x23, 0x8f, 0xff, 0x1c, 0xb5, 0x9f, 0xff, 0x1d, 0xc5, 0xbf, 0xff, 0x1e, 0xd5, 0xbf, 0xff, 0x9f, 0xe5, 0x8f, 0xff, 0x70, 0x25, 0x9f, 0xff, 0x5e, 0x45, 0xbf, 0xff, 0x58, 0x65, 0xbf, 0xff, 0xda, 0x85, 0xc8, 0xff, 0x1b, 0xc4, 0xd0, 0xff, 0x1c, 0xa4, 0xe0, 0xff, 0x1d, 0x84, 0xc0, 0xff, 0x9e, 0x54, 0x88, 0xff, 0x70, 0x24, 0x90, 0xff, 0x54, 0xa4, 0xa0, 0xff, 0x58, 0xe4, 0xc0, 0xff, 0xdc, 0x24, 0x8f, 0xff, 0x1c, 0xc5, 0x9f, 0xff, 0x1d, 0xd5, 0xbf, 0xff, 0x1e, 0xe5, 0xbf, 0xff, 0x9f, 0xf5, 0xcf, 0xff, 0x70, 0x05, 0x9f, 0xff, 0x5e, 0xe5, 0xbf, 0xff, 0x58, 0x85, 0xbf, 0xff, 0xda, 0xa5, 0x88, 0xff, 0x1b, 0xb4, 0x90, 0xff, 0x1c, 0xc4, 0xa0, 0xff, 0x1d, 0xd4, 0x80, 0xff, 0x9e, 0xe4, 0xc8, 0xff, 0x70, 0x04, 0x90, 0xff, 0x54, 0x44, 0xa0, 0xff, 0x58, 0x84, 0x80, 0xff, 0xdc, 0xc4 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vsra.s8 d17, d16, #8" + - + asm_text: "vsra.s16 d15, d14, #0x10" + - + asm_text: "vsra.s32 d13, d12, #0x20" + - + asm_text: "vsra.s64 d11, d10, #0x40" + - + asm_text: "vsra.s8 q7, q2, #8" + - + asm_text: "vsra.s16 q3, q6, #0x10" + - + asm_text: "vsra.s32 q9, q5, #0x20" + - + asm_text: "vsra.s64 q8, q4, #0x40" + - + asm_text: "vsra.u8 d17, d16, #8" + - + asm_text: "vsra.u16 d11, d14, #0xb" + - + asm_text: "vsra.u32 d12, d15, #0x16" + - + asm_text: "vsra.u64 d13, d16, #0x36" + - + asm_text: "vsra.u8 q1, q7, #8" + - + asm_text: "vsra.u16 q2, q7, #6" + - + asm_text: "vsra.u32 q3, q6, #0x15" + - + asm_text: "vsra.u64 q4, q5, #0x19" + - + asm_text: "vsra.s8 d16, d16, #8" + - + asm_text: "vsra.s16 d14, d14, #0x10" + - + asm_text: "vsra.s32 d12, d12, #0x20" + - + asm_text: "vsra.s64 d10, d10, #0x40" + - + asm_text: "vsra.s8 q2, q2, #8" + - + asm_text: "vsra.s16 q6, q6, #0x10" + - + asm_text: "vsra.s32 q5, q5, #0x20" + - + asm_text: "vsra.s64 q4, q4, #0x40" + - + asm_text: "vsra.u8 d16, d16, #8" + - + asm_text: "vsra.u16 d14, d14, #0xb" + - + asm_text: "vsra.u32 d15, d15, #0x16" + - + asm_text: "vsra.u64 d16, d16, #0x36" + - + asm_text: "vsra.u8 q7, q7, #8" + - + asm_text: "vsra.u16 q7, q7, #6" + - + asm_text: "vsra.u32 q6, q6, #0x15" + - + asm_text: "vsra.u64 q5, q5, #0x19" + - + asm_text: "vrsra.s8 d5, d26, #8" + - + asm_text: "vrsra.s16 d6, d25, #0x10" + - + asm_text: "vrsra.s32 d7, d24, #0x20" + - + asm_text: "vrsra.s64 d14, d23, #0x40" + - + asm_text: "vrsra.u8 d15, d22, #8" + - + asm_text: "vrsra.u16 d16, d21, #0x10" + - + asm_text: "vrsra.u32 d17, d20, #0x20" + - + asm_text: "vrsra.u64 d18, d19, #0x40" + - + asm_text: "vrsra.s8 q1, q2, #8" + - + asm_text: "vrsra.s16 q2, q3, #0x10" + - + asm_text: "vrsra.s32 q3, q4, #0x20" + - + asm_text: "vrsra.s64 q4, q5, #0x40" + - + asm_text: "vrsra.u8 q5, q6, #8" + - + asm_text: "vrsra.u16 q6, q7, #0x10" + - + asm_text: "vrsra.u32 q7, q8, #0x20" + - + asm_text: "vrsra.u64 q8, q9, #0x40" + - + asm_text: "vrsra.s8 d26, d26, #8" + - + asm_text: "vrsra.s16 d25, d25, #0x10" + - + asm_text: "vrsra.s32 d24, d24, #0x20" + - + asm_text: "vrsra.s64 d23, d23, #0x40" + - + asm_text: "vrsra.u8 d22, d22, #8" + - + asm_text: "vrsra.u16 d21, d21, #0x10" + - + asm_text: "vrsra.u32 d20, d20, #0x20" + - + asm_text: "vrsra.u64 d19, d19, #0x40" + - + asm_text: "vrsra.s8 q2, q2, #8" + - + asm_text: "vrsra.s16 q3, q3, #0x10" + - + asm_text: "vrsra.s32 q4, q4, #0x20" + - + asm_text: "vrsra.s64 q5, q5, #0x40" + - + asm_text: "vrsra.u8 q6, q6, #8" + - + asm_text: "vrsra.u16 q7, q7, #0x10" + - + asm_text: "vrsra.u32 q8, q8, #0x20" + - + asm_text: "vrsra.u64 q9, q9, #0x40" + - + asm_text: "vsli.8 d11, d12, #7" + - + asm_text: "vsli.16 d12, d13, #0xf" + - + asm_text: "vsli.32 d13, d14, #0x1f" + - + asm_text: "vsli.64 d14, d15, #0x3f" + - + asm_text: "vsli.8 q1, q8, #7" + - + asm_text: "vsli.16 q2, q7, #0xf" + - + asm_text: "vsli.32 q3, q4, #0x1f" + - + asm_text: "vsli.64 q4, q5, #0x3f" + - + asm_text: "vsri.8 d28, d11, #8" + - + asm_text: "vsri.16 d26, d12, #0x10" + - + asm_text: "vsri.32 d24, d13, #0x20" + - + asm_text: "vsri.64 d21, d14, #0x40" + - + asm_text: "vsri.8 q1, q8, #8" + - + asm_text: "vsri.16 q5, q2, #0x10" + - + asm_text: "vsri.32 q7, q4, #0x20" + - + asm_text: "vsri.64 q9, q6, #0x40" + - + asm_text: "vsli.8 d12, d12, #7" + - + asm_text: "vsli.16 d13, d13, #0xf" + - + asm_text: "vsli.32 d14, d14, #0x1f" + - + asm_text: "vsli.64 d15, d15, #0x3f" + - + asm_text: "vsli.8 q8, q8, #7" + - + asm_text: "vsli.16 q7, q7, #0xf" + - + asm_text: "vsli.32 q4, q4, #0x1f" + - + asm_text: "vsli.64 q5, q5, #0x3f" + - + asm_text: "vsri.8 d11, d11, #8" + - + asm_text: "vsri.16 d12, d12, #0x10" + - + asm_text: "vsri.32 d13, d13, #0x20" + - + asm_text: "vsri.64 d14, d14, #0x40" + - + asm_text: "vsri.8 q8, q8, #8" + - + asm_text: "vsri.16 q2, q2, #0x10" + - + asm_text: "vsri.32 q4, q4, #0x20" + - + asm_text: "vsri.64 q6, q6, #0x40" diff --git a/tests/MC/ARM/neont2-shuffle-encoding.s.yaml b/tests/MC/ARM/neont2-shuffle-encoding.s.yaml new file mode 100644 index 0000000000..f4c00ebd31 --- /dev/null +++ b/tests/MC/ARM/neont2-shuffle-encoding.s.yaml @@ -0,0 +1,52 @@ +test_cases: + - + input: + bytes: [ 0xf1, 0xef, 0xa0, 0x03, 0xf1, 0xef, 0xa0, 0x05, 0xf2, 0xef, 0xe0, 0x03, 0xf2, 0xef, 0xe0, 0x07, 0xf1, 0xef, 0xa0, 0x06, 0xf2, 0xef, 0xe0, 0x0c, 0xf2, 0xff, 0xa0, 0x10, 0xf6, 0xff, 0xa0, 0x10, 0xfa, 0xff, 0xa0, 0x10, 0xf2, 0xff, 0xe0, 0x20, 0xf6, 0xff, 0xe0, 0x20, 0xfa, 0xff, 0xe0, 0x20, 0xf2, 0xff, 0x20, 0x11, 0xf6, 0xff, 0x20, 0x11, 0xf2, 0xff, 0x60, 0x21, 0xf6, 0xff, 0x60, 0x21, 0xfa, 0xff, 0x60, 0x21, 0xf2, 0xff, 0xa0, 0x11, 0xf6, 0xff, 0xa0, 0x11, 0xf2, 0xff, 0xe0, 0x21, 0xf6, 0xff, 0xe0, 0x21, 0xfa, 0xff, 0xe0, 0x21 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vext.8 d16, d17, d16, #3" + - + asm_text: "vext.8 d16, d17, d16, #5" + - + asm_text: "vext.8 q8, q9, q8, #3" + - + asm_text: "vext.8 q8, q9, q8, #7" + - + asm_text: "vext.16 d16, d17, d16, #3" + - + asm_text: "vext.32 q8, q9, q8, #3" + - + asm_text: "vtrn.8 d17, d16" + - + asm_text: "vtrn.16 d17, d16" + - + asm_text: "vtrn.32 d17, d16" + - + asm_text: "vtrn.8 q9, q8" + - + asm_text: "vtrn.16 q9, q8" + - + asm_text: "vtrn.32 q9, q8" + - + asm_text: "vuzp.8 d17, d16" + - + asm_text: "vuzp.16 d17, d16" + - + asm_text: "vuzp.8 q9, q8" + - + asm_text: "vuzp.16 q9, q8" + - + asm_text: "vuzp.32 q9, q8" + - + asm_text: "vzip.8 d17, d16" + - + asm_text: "vzip.16 d17, d16" + - + asm_text: "vzip.8 q9, q8" + - + asm_text: "vzip.16 q9, q8" + - + asm_text: "vzip.32 q9, q8" diff --git a/tests/MC/ARM/neont2-sub-encoding.s.yaml b/tests/MC/ARM/neont2-sub-encoding.s.yaml new file mode 100644 index 0000000000..f4c00ebd31 --- /dev/null +++ b/tests/MC/ARM/neont2-sub-encoding.s.yaml @@ -0,0 +1,52 @@ +test_cases: + - + input: + bytes: [ 0xf1, 0xef, 0xa0, 0x03, 0xf1, 0xef, 0xa0, 0x05, 0xf2, 0xef, 0xe0, 0x03, 0xf2, 0xef, 0xe0, 0x07, 0xf1, 0xef, 0xa0, 0x06, 0xf2, 0xef, 0xe0, 0x0c, 0xf2, 0xff, 0xa0, 0x10, 0xf6, 0xff, 0xa0, 0x10, 0xfa, 0xff, 0xa0, 0x10, 0xf2, 0xff, 0xe0, 0x20, 0xf6, 0xff, 0xe0, 0x20, 0xfa, 0xff, 0xe0, 0x20, 0xf2, 0xff, 0x20, 0x11, 0xf6, 0xff, 0x20, 0x11, 0xf2, 0xff, 0x60, 0x21, 0xf6, 0xff, 0x60, 0x21, 0xfa, 0xff, 0x60, 0x21, 0xf2, 0xff, 0xa0, 0x11, 0xf6, 0xff, 0xa0, 0x11, 0xf2, 0xff, 0xe0, 0x21, 0xf6, 0xff, 0xe0, 0x21, 0xfa, 0xff, 0xe0, 0x21 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vext.8 d16, d17, d16, #3" + - + asm_text: "vext.8 d16, d17, d16, #5" + - + asm_text: "vext.8 q8, q9, q8, #3" + - + asm_text: "vext.8 q8, q9, q8, #7" + - + asm_text: "vext.16 d16, d17, d16, #3" + - + asm_text: "vext.32 q8, q9, q8, #3" + - + asm_text: "vtrn.8 d17, d16" + - + asm_text: "vtrn.16 d17, d16" + - + asm_text: "vtrn.32 d17, d16" + - + asm_text: "vtrn.8 q9, q8" + - + asm_text: "vtrn.16 q9, q8" + - + asm_text: "vtrn.32 q9, q8" + - + asm_text: "vuzp.8 d17, d16" + - + asm_text: "vuzp.16 d17, d16" + - + asm_text: "vuzp.8 q9, q8" + - + asm_text: "vuzp.16 q9, q8" + - + asm_text: "vuzp.32 q9, q8" + - + asm_text: "vzip.8 d17, d16" + - + asm_text: "vzip.16 d17, d16" + - + asm_text: "vzip.8 q9, q8" + - + asm_text: "vzip.16 q9, q8" + - + asm_text: "vzip.32 q9, q8" diff --git a/tests/MC/ARM/neont2-table-encoding.s.yaml b/tests/MC/ARM/neont2-table-encoding.s.yaml new file mode 100644 index 0000000000..11fbd48974 --- /dev/null +++ b/tests/MC/ARM/neont2-table-encoding.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0xf1, 0xff, 0xa0, 0x08, 0xf0, 0xff, 0xa2, 0x09, 0xf0, 0xff, 0xa4, 0x0a, 0xf0, 0xff, 0xa4, 0x0b, 0xf0, 0xff, 0xe1, 0x28, 0xf0, 0xff, 0xe2, 0x39, 0xf0, 0xff, 0xe5, 0x4a, 0xf0, 0xff, 0xe5, 0x4b ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vtbl.8 d16, {d17}, d16" + - + asm_text: "vtbl.8 d16, {d16, d17}, d18" + - + asm_text: "vtbl.8 d16, {d16, d17, d18}, d20" + - + asm_text: "vtbl.8 d16, {d16, d17, d18, d19}, d20" + - + asm_text: "vtbx.8 d18, {d16}, d17" + - + asm_text: "vtbx.8 d19, {d16, d17}, d18" + - + asm_text: "vtbx.8 d20, {d16, d17, d18}, d21" + - + asm_text: "vtbx.8 d20, {d16, d17, d18, d19}, d21" diff --git a/tests/MC/ARM/neont2-vld-encoding.s.yaml b/tests/MC/ARM/neont2-vld-encoding.s.yaml new file mode 100644 index 0000000000..78ded52c08 --- /dev/null +++ b/tests/MC/ARM/neont2-vld-encoding.s.yaml @@ -0,0 +1,108 @@ +test_cases: + - + input: + bytes: [ 0x60, 0xf9, 0x1f, 0x07, 0x60, 0xf9, 0x4f, 0x07, 0x60, 0xf9, 0x8f, 0x07, 0x60, 0xf9, 0xcf, 0x07, 0x60, 0xf9, 0x1f, 0x0a, 0x60, 0xf9, 0x6f, 0x0a, 0x60, 0xf9, 0x8f, 0x0a, 0x60, 0xf9, 0xcf, 0x0a, 0x60, 0xf9, 0x1f, 0x08, 0x60, 0xf9, 0x6f, 0x08, 0x60, 0xf9, 0x8f, 0x08, 0x60, 0xf9, 0x1f, 0x03, 0x60, 0xf9, 0x6f, 0x03, 0x60, 0xf9, 0xbf, 0x03, 0x60, 0xf9, 0x1f, 0x04, 0x60, 0xf9, 0x4f, 0x04, 0x60, 0xf9, 0x8f, 0x04, 0x60, 0xf9, 0x1d, 0x05, 0x60, 0xf9, 0x1d, 0x15, 0x60, 0xf9, 0x4d, 0x05, 0x60, 0xf9, 0x4d, 0x15, 0x60, 0xf9, 0x8d, 0x05, 0x60, 0xf9, 0x8d, 0x15, 0x60, 0xf9, 0x1f, 0x00, 0x60, 0xf9, 0x6f, 0x00, 0x60, 0xf9, 0xbf, 0x00, 0x60, 0xf9, 0x3d, 0x01, 0x60, 0xf9, 0x3d, 0x11, 0x60, 0xf9, 0x4d, 0x01, 0x60, 0xf9, 0x4d, 0x11, 0x60, 0xf9, 0x8d, 0x01, 0x60, 0xf9, 0x8d, 0x11, 0xe0, 0xf9, 0x6f, 0x00, 0xe0, 0xf9, 0x9f, 0x04, 0xe0, 0xf9, 0xbf, 0x08, 0xe0, 0xf9, 0x3f, 0x01, 0xe0, 0xf9, 0x5f, 0x05, 0xe0, 0xf9, 0x8f, 0x09, 0xe0, 0xf9, 0x6f, 0x15, 0xe0, 0xf9, 0x5f, 0x19, 0xe0, 0xf9, 0x2f, 0x02, 0xe0, 0xf9, 0x4f, 0x06, 0xe0, 0xf9, 0x8f, 0x0a, 0xe0, 0xf9, 0x6f, 0x06, 0xe0, 0xf9, 0xcf, 0x1a, 0xe0, 0xf9, 0x3f, 0x03, 0xe0, 0xf9, 0x4f, 0x07, 0xe0, 0xf9, 0xaf, 0x0b, 0xe0, 0xf9, 0x7f, 0x07, 0xe0, 0xf9, 0x4f, 0x1b ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vld1.8 {d16}, [r0:64]" + - + asm_text: "vld1.16 {d16}, [r0]" + - + asm_text: "vld1.32 {d16}, [r0]" + - + asm_text: "vld1.64 {d16}, [r0]" + - + asm_text: "vld1.8 {d16, d17}, [r0:64]" + - + asm_text: "vld1.16 {d16, d17}, [r0:128]" + - + asm_text: "vld1.32 {d16, d17}, [r0]" + - + asm_text: "vld1.64 {d16, d17}, [r0]" + - + asm_text: "vld2.8 {d16, d17}, [r0:64]" + - + asm_text: "vld2.16 {d16, d17}, [r0:128]" + - + asm_text: "vld2.32 {d16, d17}, [r0]" + - + asm_text: "vld2.8 {d16, d17, d18, d19}, [r0:64]" + - + asm_text: "vld2.16 {d16, d17, d18, d19}, [r0:128]" + - + asm_text: "vld2.32 {d16, d17, d18, d19}, [r0:256]" + - + asm_text: "vld3.8 {d16, d17, d18}, [r0:64]" + - + asm_text: "vld3.16 {d16, d17, d18}, [r0]" + - + asm_text: "vld3.32 {d16, d17, d18}, [r0]" + - + asm_text: "vld3.8 {d16, d18, d20}, [r0:64]!" + - + asm_text: "vld3.8 {d17, d19, d21}, [r0:64]!" + - + asm_text: "vld3.16 {d16, d18, d20}, [r0]!" + - + asm_text: "vld3.16 {d17, d19, d21}, [r0]!" + - + asm_text: "vld3.32 {d16, d18, d20}, [r0]!" + - + asm_text: "vld3.32 {d17, d19, d21}, [r0]!" + - + asm_text: "vld4.8 {d16, d17, d18, d19}, [r0:64]" + - + asm_text: "vld4.16 {d16, d17, d18, d19}, [r0:128]" + - + asm_text: "vld4.32 {d16, d17, d18, d19}, [r0:256]" + - + asm_text: "vld4.8 {d16, d18, d20, d22}, [r0:256]!" + - + asm_text: "vld4.8 {d17, d19, d21, d23}, [r0:256]!" + - + asm_text: "vld4.16 {d16, d18, d20, d22}, [r0]!" + - + asm_text: "vld4.16 {d17, d19, d21, d23}, [r0]!" + - + asm_text: "vld4.32 {d16, d18, d20, d22}, [r0]!" + - + asm_text: "vld4.32 {d17, d19, d21, d23}, [r0]!" + - + asm_text: "vld1.8 {d16[3]}, [r0]" + - + asm_text: "vld1.16 {d16[2]}, [r0:16]" + - + asm_text: "vld1.32 {d16[1]}, [r0:32]" + - + asm_text: "vld2.8 {d16[1], d17[1]}, [r0:16]" + - + asm_text: "vld2.16 {d16[1], d17[1]}, [r0:32]" + - + asm_text: "vld2.32 {d16[1], d17[1]}, [r0]" + - + asm_text: "vld2.16 {d17[1], d19[1]}, [r0]" + - + asm_text: "vld2.32 {d17[0], d19[0]}, [r0:64]" + - + asm_text: "vld3.8 {d16[1], d17[1], d18[1]}, [r0]" + - + asm_text: "vld3.16 {d16[1], d17[1], d18[1]}, [r0]" + - + asm_text: "vld3.32 {d16[1], d17[1], d18[1]}, [r0]" + - + asm_text: "vld3.16 {d16[1], d18[1], d20[1]}, [r0]" + - + asm_text: "vld3.32 {d17[1], d19[1], d21[1]}, [r0]" + - + asm_text: "vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]" + - + asm_text: "vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]" + - + asm_text: "vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]" + - + asm_text: "vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0:64]" + - + asm_text: "vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]" diff --git a/tests/MC/ARM/neont2-vst-encoding.s.yaml b/tests/MC/ARM/neont2-vst-encoding.s.yaml new file mode 100644 index 0000000000..91ffb02e25 --- /dev/null +++ b/tests/MC/ARM/neont2-vst-encoding.s.yaml @@ -0,0 +1,102 @@ +test_cases: + - + input: + bytes: [ 0x40, 0xf9, 0x1f, 0x07, 0x40, 0xf9, 0x4f, 0x07, 0x40, 0xf9, 0x8f, 0x07, 0x40, 0xf9, 0xcf, 0x07, 0x40, 0xf9, 0x1f, 0x0a, 0x40, 0xf9, 0x6f, 0x0a, 0x40, 0xf9, 0x8f, 0x0a, 0x40, 0xf9, 0xcf, 0x0a, 0x40, 0xf9, 0x1f, 0x08, 0x40, 0xf9, 0x6f, 0x08, 0x40, 0xf9, 0x8f, 0x08, 0x40, 0xf9, 0x1f, 0x03, 0x40, 0xf9, 0x6f, 0x03, 0x40, 0xf9, 0xbf, 0x03, 0x40, 0xf9, 0x1f, 0x04, 0x40, 0xf9, 0x4f, 0x04, 0x40, 0xf9, 0x8f, 0x04, 0x40, 0xf9, 0x1d, 0x05, 0x40, 0xf9, 0x1d, 0x15, 0x40, 0xf9, 0x4d, 0x05, 0x40, 0xf9, 0x4d, 0x15, 0x40, 0xf9, 0x8d, 0x05, 0x40, 0xf9, 0x8d, 0x15, 0x40, 0xf9, 0x1f, 0x00, 0x40, 0xf9, 0x6f, 0x00, 0x40, 0xf9, 0x3d, 0x01, 0x40, 0xf9, 0x3d, 0x11, 0x40, 0xf9, 0x4d, 0x01, 0x40, 0xf9, 0x4d, 0x11, 0x40, 0xf9, 0x8d, 0x01, 0x40, 0xf9, 0x8d, 0x11, 0xc0, 0xf9, 0x3f, 0x01, 0xc0, 0xf9, 0x5f, 0x05, 0xc0, 0xf9, 0x8f, 0x09, 0xc0, 0xf9, 0x6f, 0x15, 0xc0, 0xf9, 0x5f, 0x19, 0xc0, 0xf9, 0x2f, 0x02, 0xc0, 0xf9, 0x4f, 0x06, 0xc0, 0xf9, 0x8f, 0x0a, 0xc0, 0xf9, 0xaf, 0x16, 0xc0, 0xf9, 0x4f, 0x0a, 0xc0, 0xf9, 0x3f, 0x03, 0xc0, 0xf9, 0x4f, 0x07, 0xc0, 0xf9, 0xaf, 0x0b, 0xc0, 0xf9, 0xff, 0x17, 0xc0, 0xf9, 0x4f, 0x1b, 0x04, 0xf9, 0x0f, 0x89 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vst1.8 {d16}, [r0:64]" + - + asm_text: "vst1.16 {d16}, [r0]" + - + asm_text: "vst1.32 {d16}, [r0]" + - + asm_text: "vst1.64 {d16}, [r0]" + - + asm_text: "vst1.8 {d16, d17}, [r0:64]" + - + asm_text: "vst1.16 {d16, d17}, [r0:128]" + - + asm_text: "vst1.32 {d16, d17}, [r0]" + - + asm_text: "vst1.64 {d16, d17}, [r0]" + - + asm_text: "vst2.8 {d16, d17}, [r0:64]" + - + asm_text: "vst2.16 {d16, d17}, [r0:128]" + - + asm_text: "vst2.32 {d16, d17}, [r0]" + - + asm_text: "vst2.8 {d16, d17, d18, d19}, [r0:64]" + - + asm_text: "vst2.16 {d16, d17, d18, d19}, [r0:128]" + - + asm_text: "vst2.32 {d16, d17, d18, d19}, [r0:256]" + - + asm_text: "vst3.8 {d16, d17, d18}, [r0:64]" + - + asm_text: "vst3.16 {d16, d17, d18}, [r0]" + - + asm_text: "vst3.32 {d16, d17, d18}, [r0]" + - + asm_text: "vst3.8 {d16, d18, d20}, [r0:64]!" + - + asm_text: "vst3.8 {d17, d19, d21}, [r0:64]!" + - + asm_text: "vst3.16 {d16, d18, d20}, [r0]!" + - + asm_text: "vst3.16 {d17, d19, d21}, [r0]!" + - + asm_text: "vst3.32 {d16, d18, d20}, [r0]!" + - + asm_text: "vst3.32 {d17, d19, d21}, [r0]!" + - + asm_text: "vst4.8 {d16, d17, d18, d19}, [r0:64]" + - + asm_text: "vst4.16 {d16, d17, d18, d19}, [r0:128]" + - + asm_text: "vst4.8 {d16, d18, d20, d22}, [r0:256]!" + - + asm_text: "vst4.8 {d17, d19, d21, d23}, [r0:256]!" + - + asm_text: "vst4.16 {d16, d18, d20, d22}, [r0]!" + - + asm_text: "vst4.16 {d17, d19, d21, d23}, [r0]!" + - + asm_text: "vst4.32 {d16, d18, d20, d22}, [r0]!" + - + asm_text: "vst4.32 {d17, d19, d21, d23}, [r0]!" + - + asm_text: "vst2.8 {d16[1], d17[1]}, [r0:16]" + - + asm_text: "vst2.16 {d16[1], d17[1]}, [r0:32]" + - + asm_text: "vst2.32 {d16[1], d17[1]}, [r0]" + - + asm_text: "vst2.16 {d17[1], d19[1]}, [r0]" + - + asm_text: "vst2.32 {d17[0], d19[0]}, [r0:64]" + - + asm_text: "vst3.8 {d16[1], d17[1], d18[1]}, [r0]" + - + asm_text: "vst3.16 {d16[1], d17[1], d18[1]}, [r0]" + - + asm_text: "vst3.32 {d16[1], d17[1], d18[1]}, [r0]" + - + asm_text: "vst3.16 {d17[2], d19[2], d21[2]}, [r0]" + - + asm_text: "vst3.32 {d16[0], d18[0], d20[0]}, [r0]" + - + asm_text: "vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]" + - + asm_text: "vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]" + - + asm_text: "vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]" + - + asm_text: "vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64]" + - + asm_text: "vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]" + - + asm_text: "vst2.8 {d8, d10}, [r4]" diff --git a/tests/MC/ARM/simple-fp-encoding.s.yaml b/tests/MC/ARM/simple-fp-encoding.s.yaml new file mode 100644 index 0000000000..0775016d4b --- /dev/null +++ b/tests/MC/ARM/simple-fp-encoding.s.yaml @@ -0,0 +1,360 @@ +test_cases: + - + input: + bytes: [ 0xa0, 0x0b, 0x71, 0xee, 0x80, 0x0a, 0x30, 0xee, 0xe0, 0x0b, 0x71, 0xee, 0xc0, 0x0a, 0x30, 0xee, 0xa0, 0x0b, 0xc1, 0xee, 0x80, 0x0a, 0x80, 0xee, 0xa3, 0x2a, 0xc2, 0xee, 0x07, 0x5b, 0x85, 0xee, 0xa0, 0x0b, 0x61, 0xee, 0xa1, 0x4b, 0x64, 0xee, 0x80, 0x0a, 0x20, 0xee, 0xaa, 0x5a, 0x65, 0xee, 0xe0, 0x0b, 0x61, 0xee, 0xc0, 0x0a, 0x20, 0xee, 0x60, 0x1b, 0xf4, 0xee, 0x40, 0x0a, 0xf4, 0xee, 0x40, 0x1b, 0xf5, 0xee, 0x40, 0x0a, 0xf5, 0xee, 0xe0, 0x1b, 0xf4, 0xee, 0xc0, 0x0a, 0xf4, 0xee, 0xc0, 0x0b, 0xf5, 0xee, 0xc0, 0x0a, 0xb5, 0xee, 0xe0, 0x0b, 0xf0, 0xee, 0xc0, 0x0a, 0xb0, 0xee, 0xe0, 0x0b, 0xb7, 0xee, 0xc0, 0x0a, 0xf7, 0xee, 0x60, 0x0b, 0xf1, 0xee, 0x40, 0x0a, 0xb1, 0xee, 0xe0, 0x0b, 0xf1, 0xee, 0xc0, 0x0a, 0xb1, 0xee, 0xc0, 0x0b, 0xf8, 0xee, 0xc0, 0x0a, 0xb8, 0xee, 0x40, 0x0b, 0xf8, 0xee, 0x40, 0x0a, 0xb8, 0xee, 0xe0, 0x0b, 0xbd, 0xee, 0xc0, 0x0a, 0xbd, 0xee, 0xe0, 0x0b, 0xbc, 0xee, 0xc0, 0x0a, 0xbc, 0xee, 0xa1, 0x0b, 0x42, 0xee, 0x00, 0x0a, 0x41, 0xee, 0xe1, 0x0b, 0x42, 0xee, 0x40, 0x0a, 0x41, 0xee, 0xe1, 0x0b, 0x52, 0xee, 0x40, 0x0a, 0x51, 0xee, 0xa1, 0x0b, 0x52, 0xee, 0x00, 0x0a, 0x51, 0xee, 0x10, 0xfa, 0xf1, 0xee, 0x10, 0xfa, 0xf1, 0xee, 0x10, 0xfa, 0xf1, 0xee, 0x10, 0x2a, 0xf0, 0xee, 0x10, 0x3a, 0xf0, 0xee, 0x10, 0x4a, 0xf7, 0xee, 0x10, 0x5a, 0xf6, 0xee, 0x60, 0x0b, 0xf1, 0x1e, 0x10, 0x0a, 0x00, 0x1e, 0x10, 0x1a, 0x00, 0x0e, 0x10, 0x1a, 0x11, 0xee, 0x10, 0x3a, 0x02, 0xee, 0x12, 0x1b, 0x55, 0xec, 0x14, 0x3b, 0x49, 0xec, 0x10, 0x0a, 0xf1, 0xee, 0x10, 0x0a, 0xf8, 0xee, 0x10, 0x0a, 0xf0, 0xee, 0x10, 0x1a, 0xf9, 0xee, 0x10, 0x8a, 0xfa, 0xee, 0x10, 0x0a, 0xe1, 0xee, 0x10, 0x0a, 0xe8, 0xee, 0x10, 0x0a, 0xe0, 0xee, 0x10, 0x3a, 0xe9, 0xee, 0x10, 0x4a, 0xea, 0xee, 0x08, 0x0b, 0xf0, 0xee, 0x08, 0x0a, 0xb0, 0xee, 0x08, 0x0b, 0xf8, 0xee, 0x08, 0x0a, 0xb8, 0xee, 0x10, 0x0a, 0x00, 0xee, 0x90, 0x1a, 0x00, 0xee, 0x10, 0x2a, 0x01, 0xee, 0x90, 0x3a, 0x01, 0xee, 0x10, 0x0a, 0x10, 0xee, 0x90, 0x1a, 0x10, 0xee, 0x10, 0x2a, 0x11, 0xee, 0x90, 0x3a, 0x11, 0xee, 0x30, 0x0b, 0x51, 0xec, 0x31, 0x1a, 0x42, 0xec, 0x11, 0x1a, 0x42, 0xec, 0x31, 0x1a, 0x52, 0xec, 0x11, 0x1a, 0x52, 0xec, 0x1f, 0x1b, 0x42, 0xec, 0x30, 0x1b, 0x42, 0xec, 0x1f, 0x1b, 0x52, 0xec, 0x30, 0x1b, 0x52, 0xec, 0x00, 0x1b, 0xd0, 0xed, 0x00, 0x0a, 0x9e, 0xed, 0x00, 0x0b, 0x9e, 0xed, 0x08, 0x1b, 0x92, 0xed, 0x08, 0x1b, 0x12, 0xed, 0x00, 0x2b, 0x93, 0xed, 0x00, 0x3b, 0x9f, 0xed, 0x00, 0x3b, 0x9f, 0xed, 0x00, 0x3b, 0x1f, 0xed, 0x00, 0x6a, 0xd0, 0xed, 0x08, 0x0a, 0xd2, 0xed, 0x08, 0x0a, 0x52, 0xed, 0x00, 0x1a, 0x93, 0xed, 0x00, 0x2a, 0xdf, 0xed, 0x00, 0x2a, 0xdf, 0xed, 0x00, 0x2a, 0x5f, 0xed, 0x00, 0x4b, 0x81, 0xed, 0x06, 0x4b, 0x81, 0xed, 0x06, 0x4b, 0x01, 0xed, 0x00, 0x0a, 0x8e, 0xed, 0x00, 0x0b, 0x8e, 0xed, 0x00, 0x2a, 0x81, 0xed, 0x06, 0x2a, 0x81, 0xed, 0x06, 0x2a, 0x01, 0xed, 0x0c, 0x2b, 0x91, 0xec, 0x06, 0x1a, 0x91, 0xec, 0x0c, 0x2b, 0x81, 0xec, 0x06, 0x1a, 0x81, 0xec, 0x10, 0x8b, 0x2d, 0xed, 0x07, 0x0b, 0xb5, 0xec, 0x05, 0x4b, 0x90, 0x0c, 0x07, 0x4b, 0x35, 0x1d, 0x11, 0x0b, 0xa5, 0xec, 0x05, 0x8b, 0x84, 0x0c, 0x07, 0x2b, 0x27, 0x1d, 0x40, 0x0b, 0xbd, 0xee, 0x60, 0x0a, 0xbd, 0xee, 0x40, 0x0b, 0xbc, 0xee, 0x60, 0x0a, 0xbc, 0xee, 0x90, 0x8a, 0x00, 0xee, 0x10, 0x4a, 0x01, 0xee, 0x90, 0x6a, 0x01, 0xee, 0x10, 0x1a, 0x02, 0xee, 0x90, 0x2a, 0x02, 0xee, 0x10, 0x3a, 0x03, 0xee, 0x10, 0x1a, 0x14, 0xee, 0x10, 0x2a, 0x12, 0xee, 0x10, 0x3a, 0x13, 0xee, 0x90, 0x4a, 0x10, 0xee, 0x10, 0x5a, 0x11, 0xee, 0x90, 0x6a, 0x11, 0xee, 0xc6, 0x0a, 0xbb, 0xee, 0xc0, 0x0b, 0xba, 0xee, 0x67, 0x0a, 0xbb, 0xee, 0x40, 0x0b, 0xba, 0xee, 0xc6, 0x0a, 0xfa, 0xee, 0xc0, 0x4b, 0xfb, 0xee, 0x67, 0x8a, 0xfa, 0xee, 0x40, 0x7b, 0xfb, 0xee, 0xc6, 0x6a, 0xbf, 0xee, 0xc0, 0x2b, 0xbe, 0xee, 0x67, 0xea, 0xbf, 0xee, 0x40, 0xfb, 0xbe, 0xee, 0xc6, 0x0a, 0xfe, 0xee, 0xc0, 0x4b, 0xff, 0xee, 0x67, 0x8a, 0xfe, 0xee, 0x40, 0x7b, 0xff, 0xee, 0x10, 0x40, 0x80, 0xf2, 0x12, 0x46, 0x84, 0xf2, 0x00, 0x2a, 0xf7, 0xee, 0x00, 0x2a, 0xf4, 0xee, 0x0e, 0x2a, 0xff, 0xee, 0x03, 0x2a, 0xfe, 0xee, 0x00, 0x6b, 0xb7, 0xee, 0x00, 0x6b, 0xb4, 0xee, 0x0e, 0x6b, 0xbf, 0xee, 0x03, 0x6b, 0xbe, 0xee, 0x10, 0x7f, 0x87, 0xf2, 0x10, 0x7f, 0x84, 0xf2, 0x1e, 0x7f, 0x87, 0xf3, 0x13, 0x7f, 0x86, 0xf3, 0x50, 0x0f, 0xc7, 0xf2, 0x50, 0x0f, 0xc4, 0xf2, 0x5e, 0x0f, 0xc7, 0xf3, 0x53, 0x0f, 0xc6, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vadd.f64 d16, d17, d16" + - + asm_text: "vadd.f32 s0, s1, s0" + - + asm_text: "vsub.f64 d16, d17, d16" + - + asm_text: "vsub.f32 s0, s1, s0" + - + asm_text: "vdiv.f64 d16, d17, d16" + - + asm_text: "vdiv.f32 s0, s1, s0" + - + asm_text: "vdiv.f32 s5, s5, s7" + - + asm_text: "vdiv.f64 d5, d5, d7" + - + asm_text: "vmul.f64 d16, d17, d16" + - + asm_text: "vmul.f64 d20, d20, d17" + - + asm_text: "vmul.f32 s0, s1, s0" + - + asm_text: "vmul.f32 s11, s11, s21" + - + asm_text: "vnmul.f64 d16, d17, d16" + - + asm_text: "vnmul.f32 s0, s1, s0" + - + asm_text: "vcmp.f64 d17, d16" + - + asm_text: "vcmp.f32 s1, s0" + - + asm_text: "vcmp.f64 d17, #0" + - + asm_text: "vcmp.f32 s1, #0" + - + asm_text: "vcmpe.f64 d17, d16" + - + asm_text: "vcmpe.f32 s1, s0" + - + asm_text: "vcmpe.f64 d16, #0" + - + asm_text: "vcmpe.f32 s0, #0" + - + asm_text: "vabs.f64 d16, d16" + - + asm_text: "vabs.f32 s0, s0" + - + asm_text: "vcvt.f32.f64 s0, d16" + - + asm_text: "vcvt.f64.f32 d16, s0" + - + asm_text: "vneg.f64 d16, d16" + - + asm_text: "vneg.f32 s0, s0" + - + asm_text: "vsqrt.f64 d16, d16" + - + asm_text: "vsqrt.f32 s0, s0" + - + asm_text: "vcvt.f64.s32 d16, s0" + - + asm_text: "vcvt.f32.s32 s0, s0" + - + asm_text: "vcvt.f64.u32 d16, s0" + - + asm_text: "vcvt.f32.u32 s0, s0" + - + asm_text: "vcvt.s32.f64 s0, d16" + - + asm_text: "vcvt.s32.f32 s0, s0" + - + asm_text: "vcvt.u32.f64 s0, d16" + - + asm_text: "vcvt.u32.f32 s0, s0" + - + asm_text: "vmla.f64 d16, d18, d17" + - + asm_text: "vmla.f32 s1, s2, s0" + - + asm_text: "vmls.f64 d16, d18, d17" + - + asm_text: "vmls.f32 s1, s2, s0" + - + asm_text: "vnmla.f64 d16, d18, d17" + - + asm_text: "vnmla.f32 s1, s2, s0" + - + asm_text: "vnmls.f64 d16, d18, d17" + - + asm_text: "vnmls.f32 s1, s2, s0" + - + asm_text: "vmrs APSR_nzcv, fpscr" + - + asm_text: "vmrs APSR_nzcv, fpscr" + - + asm_text: "vmrs APSR_nzcv, fpscr" + - + asm_text: "vmrs r2, fpsid" + - + asm_text: "vmrs r3, fpsid" + - + asm_text: "vmrs r4, mvfr0" + - + asm_text: "vmrs r5, mvfr1" + - + asm_text: "vnegne.f64 d16, d16" + - + asm_text: "vmovne s0, r0" + - + asm_text: "vmoveq s0, r1" + - + asm_text: "vmov r1, s2" + - + asm_text: "vmov s4, r3" + - + asm_text: "vmov r1, r5, d2" + - + asm_text: "vmov d4, r3, r9" + - + asm_text: "vmrs r0, fpscr" + - + asm_text: "vmrs r0, fpexc" + - + asm_text: "vmrs r0, fpsid" + - + asm_text: "vmrs r1, fpinst" + - + asm_text: "vmrs r8, fpinst2" + - + asm_text: "vmsr fpscr, r0" + - + asm_text: "vmsr fpexc, r0" + - + asm_text: "vmsr fpsid, r0" + - + asm_text: "vmsr fpinst, r3" + - + asm_text: "vmsr fpinst2, r4" + - + asm_text: "vmov.f64 d16, #3.000000e+00" + - + asm_text: "vmov.f32 s0, #3.000000e+00" + - + asm_text: "vmov.f64 d16, #-3.000000e+00" + - + asm_text: "vmov.f32 s0, #-3.000000e+00" + - + asm_text: "vmov s0, r0" + - + asm_text: "vmov s1, r1" + - + asm_text: "vmov s2, r2" + - + asm_text: "vmov s3, r3" + - + asm_text: "vmov r0, s0" + - + asm_text: "vmov r1, s1" + - + asm_text: "vmov r2, s2" + - + asm_text: "vmov r3, s3" + - + asm_text: "vmov r0, r1, d16" + - + asm_text: "vmov s3, s4, r1, r2" + - + asm_text: "vmov s2, s3, r1, r2" + - + asm_text: "vmov r1, r2, s3, s4" + - + asm_text: "vmov r1, r2, s2, s3" + - + asm_text: "vmov d15, r1, r2" + - + asm_text: "vmov d16, r1, r2" + - + asm_text: "vmov r1, r2, d15" + - + asm_text: "vmov r1, r2, d16" + - + asm_text: "vldr d17, [r0]" + - + asm_text: "vldr s0, [lr]" + - + asm_text: "vldr d0, [lr]" + - + asm_text: "vldr d1, [r2, #0x20]" + - + asm_text: "vldr d1, [r2, #-0x20]" + - + asm_text: "vldr d2, [r3]" + - + asm_text: "vldr d3, [pc]" + - + asm_text: "vldr d3, [pc]" + - + asm_text: "vldr d3, [pc, #-0]" + - + asm_text: "vldr s13, [r0]" + - + asm_text: "vldr s1, [r2, #0x20]" + - + asm_text: "vldr s1, [r2, #-0x20]" + - + asm_text: "vldr s2, [r3]" + - + asm_text: "vldr s5, [pc]" + - + asm_text: "vldr s5, [pc]" + - + asm_text: "vldr s5, [pc, #-0]" + - + asm_text: "vstr d4, [r1]" + - + asm_text: "vstr d4, [r1, #0x18]" + - + asm_text: "vstr d4, [r1, #-0x18]" + - + asm_text: "vstr s0, [lr]" + - + asm_text: "vstr d0, [lr]" + - + asm_text: "vstr s4, [r1]" + - + asm_text: "vstr s4, [r1, #0x18]" + - + asm_text: "vstr s4, [r1, #-0x18]" + - + asm_text: "vldmia r1, {d2, d3, d4, d5, d6, d7}" + - + asm_text: "vldmia r1, {s2, s3, s4, s5, s6, s7}" + - + asm_text: "vstmia r1, {d2, d3, d4, d5, d6, d7}" + - + asm_text: "vstmia r1, {s2, s3, s4, s5, s6, s7}" + - + asm_text: "vpush {d8, d9, d10, d11, d12, d13, d14, d15}" + - + asm_text: "fldmiax r5!, {d0, d1, d2}" + - + asm_text: "fldmiaxeq r0, {d4, d5}" + - + asm_text: "fldmdbxne r5!, {d4, d5, d6}" + - + asm_text: "fstmiax r5!, {d0, d1, d2, d3, d4, d5, d6, d7}" + - + asm_text: "fstmiaxeq r4, {d8, d9}" + - + asm_text: "fstmdbxne r7!, {d2, d3, d4}" + - + asm_text: "vcvtr.s32.f64 s0, d0" + - + asm_text: "vcvtr.s32.f32 s0, s1" + - + asm_text: "vcvtr.u32.f64 s0, d0" + - + asm_text: "vcvtr.u32.f32 s0, s1" + - + asm_text: "vmov s1, r8" + - + asm_text: "vmov s2, r4" + - + asm_text: "vmov s3, r6" + - + asm_text: "vmov s4, r1" + - + asm_text: "vmov s5, r2" + - + asm_text: "vmov s6, r3" + - + asm_text: "vmov r1, s8" + - + asm_text: "vmov r2, s4" + - + asm_text: "vmov r3, s6" + - + asm_text: "vmov r4, s1" + - + asm_text: "vmov r5, s2" + - + asm_text: "vmov r6, s3" + - + asm_text: "vcvt.f32.u32 s0, s0, #0x14" + - + asm_text: "vcvt.f64.s32 d0, d0, #0x20" + - + asm_text: "vcvt.f32.u16 s0, s0, #1" + - + asm_text: "vcvt.f64.s16 d0, d0, #0x10" + - + asm_text: "vcvt.f32.s32 s1, s1, #0x14" + - + asm_text: "vcvt.f64.u32 d20, d20, #0x20" + - + asm_text: "vcvt.f32.s16 s17, s17, #1" + - + asm_text: "vcvt.f64.u16 d23, d23, #0x10" + - + asm_text: "vcvt.u32.f32 s12, s12, #0x14" + - + asm_text: "vcvt.s32.f64 d2, d2, #0x20" + - + asm_text: "vcvt.u16.f32 s28, s28, #1" + - + asm_text: "vcvt.s16.f64 d15, d15, #0x10" + - + asm_text: "vcvt.s32.f32 s1, s1, #0x14" + - + asm_text: "vcvt.u32.f64 d20, d20, #0x20" + - + asm_text: "vcvt.s16.f32 s17, s17, #1" + - + asm_text: "vcvt.u16.f64 d23, d23, #0x10" + - + asm_text: "vmov.i32 d4, #0x0" + - + asm_text: "vmov.i32 d4, #0x42000000" + - + asm_text: "vmov.f32 s5, #1.000000e+00" + - + asm_text: "vmov.f32 s5, #1.250000e-01" + - + asm_text: "vmov.f32 s5, #-1.875000e+00" + - + asm_text: "vmov.f32 s5, #-5.937500e-01" + - + asm_text: "vmov.f64 d6, #1.000000e+00" + - + asm_text: "vmov.f64 d6, #1.250000e-01" + - + asm_text: "vmov.f64 d6, #-1.875000e+00" + - + asm_text: "vmov.f64 d6, #-5.937500e-01" + - + asm_text: "vmov.f32 d7, #1.000000e+00" + - + asm_text: "vmov.f32 d7, #1.250000e-01" + - + asm_text: "vmov.f32 d7, #-1.875000e+00" + - + asm_text: "vmov.f32 d7, #-5.937500e-01" + - + asm_text: "vmov.f32 q8, #1.000000e+00" + - + asm_text: "vmov.f32 q8, #1.250000e-01" + - + asm_text: "vmov.f32 q8, #-1.875000e+00" + - + asm_text: "vmov.f32 q8, #-5.937500e-01" diff --git a/tests/MC/ARM/thumb-add-sub-width.s.yaml b/tests/MC/ARM/thumb-add-sub-width.s.yaml new file mode 100644 index 0000000000..5c235b7daf --- /dev/null +++ b/tests/MC/ARM/thumb-add-sub-width.s.yaml @@ -0,0 +1,56 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x44, 0x08, 0x44, 0x40, 0x18, 0x40, 0x18, 0x08, 0x44, 0x08, 0x44, 0x40, 0x18, 0x40, 0x18, 0x01, 0xbf, 0x40, 0x18, 0x08, 0x44, 0x10, 0xeb, 0x01, 0x00, 0x10, 0xeb, 0x01, 0x00, 0x40, 0x1a, 0x40, 0x1a, 0xa0, 0xeb, 0x01, 0x00, 0xa0, 0xeb, 0x01, 0x00, 0x40, 0x1a, 0x40, 0x1a, 0x01, 0xbf, 0x40, 0x1a, 0x40, 0x1a, 0xb0, 0xeb, 0x01, 0x00, 0xb0, 0xeb, 0x01, 0x00 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "add r0, r1" + - + asm_text: "add r0, r1" + - + asm_text: "adds r0, r0, r1" + - + asm_text: "adds r0, r0, r1" + - + asm_text: "add r0, r1" + - + asm_text: "add r0, r1" + - + asm_text: "adds r0, r0, r1" + - + asm_text: "adds r0, r0, r1" + - + asm_text: "itttt eq" + - + asm_text: "addeq r0, r0, r1" + - + asm_text: "addeq r0, r1" + - + asm_text: "addseq.w r0, r0, r1" + - + asm_text: "addseq.w r0, r0, r1" + - + asm_text: "subs r0, r0, r1" + - + asm_text: "subs r0, r0, r1" + - + asm_text: "sub.w r0, r0, r1" + - + asm_text: "sub.w r0, r0, r1" + - + asm_text: "subs r0, r0, r1" + - + asm_text: "subs r0, r0, r1" + - + asm_text: "itttt eq" + - + asm_text: "subeq r0, r0, r1" + - + asm_text: "subeq r0, r0, r1" + - + asm_text: "subseq.w r0, r0, r1" + - + asm_text: "subseq.w r0, r0, r1" diff --git a/tests/MC/ARM/thumb-fp-armv8.s.yaml b/tests/MC/ARM/thumb-fp-armv8.s.yaml new file mode 100644 index 0000000000..304c64c364 --- /dev/null +++ b/tests/MC/ARM/thumb-fp-armv8.s.yaml @@ -0,0 +1,92 @@ +test_cases: + - + input: + bytes: [ 0xb2, 0xee, 0xe0, 0x3b, 0xf3, 0xee, 0xcc, 0x2b, 0xb2, 0xee, 0x60, 0x3b, 0xb3, 0xee, 0x41, 0x2b, 0xbc, 0xfe, 0xe1, 0x1a, 0xbc, 0xfe, 0xc3, 0x1b, 0xbd, 0xfe, 0xeb, 0x3a, 0xbd, 0xfe, 0xe7, 0x3b, 0xbe, 0xfe, 0xc2, 0x0a, 0xbe, 0xfe, 0xc4, 0x0b, 0xff, 0xfe, 0xc4, 0x8a, 0xff, 0xfe, 0xc8, 0x8b, 0xbc, 0xfe, 0x61, 0x1a, 0xbc, 0xfe, 0x43, 0x1b, 0xbd, 0xfe, 0x6b, 0x3a, 0xbd, 0xfe, 0x67, 0x3b, 0xbe, 0xfe, 0x42, 0x0a, 0xbe, 0xfe, 0x44, 0x0b, 0xff, 0xfe, 0x44, 0x8a, 0xff, 0xfe, 0x48, 0x8b, 0x20, 0xfe, 0xab, 0x2a, 0x6f, 0xfe, 0xa7, 0xeb, 0x30, 0xfe, 0x80, 0x0a, 0x3a, 0xfe, 0x24, 0x5b, 0x0e, 0xfe, 0x2b, 0xfa, 0x04, 0xfe, 0x08, 0x2b, 0x58, 0xfe, 0x07, 0xaa, 0x11, 0xfe, 0x2f, 0x0b, 0xc6, 0xfe, 0x00, 0x2a, 0x86, 0xfe, 0xae, 0x5b, 0x80, 0xfe, 0x46, 0x0a, 0x86, 0xfe, 0x49, 0x4b, 0xf6, 0xee, 0xcc, 0x1a, 0xb6, 0xee, 0x64, 0x0a, 0xb8, 0xfe, 0x44, 0x3b, 0xb8, 0xfe, 0x60, 0x6a, 0xb9, 0xfe, 0x44, 0x3b, 0xb9, 0xfe, 0x60, 0x6a, 0xba, 0xfe, 0x44, 0x3b, 0xba, 0xfe, 0x60, 0x6a, 0xbb, 0xfe, 0x44, 0x3b, 0xbb, 0xfe, 0x60, 0x6a ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vcvtt.f64.f16 d3, s1" + - + asm_text: "vcvtt.f16.f64 s5, d12" + - + asm_text: "vcvtb.f64.f16 d3, s1" + - + asm_text: "vcvtb.f16.f64 s4, d1" + - + asm_text: "vcvta.s32.f32 s2, s3" + - + asm_text: "vcvta.s32.f64 s2, d3" + - + asm_text: "vcvtn.s32.f32 s6, s23" + - + asm_text: "vcvtn.s32.f64 s6, d23" + - + asm_text: "vcvtp.s32.f32 s0, s4" + - + asm_text: "vcvtp.s32.f64 s0, d4" + - + asm_text: "vcvtm.s32.f32 s17, s8" + - + asm_text: "vcvtm.s32.f64 s17, d8" + - + asm_text: "vcvta.u32.f32 s2, s3" + - + asm_text: "vcvta.u32.f64 s2, d3" + - + asm_text: "vcvtn.u32.f32 s6, s23" + - + asm_text: "vcvtn.u32.f64 s6, d23" + - + asm_text: "vcvtp.u32.f32 s0, s4" + - + asm_text: "vcvtp.u32.f64 s0, d4" + - + asm_text: "vcvtm.u32.f32 s17, s8" + - + asm_text: "vcvtm.u32.f64 s17, d8" + - + asm_text: "vselge.f32 s4, s1, s23" + - + asm_text: "vselge.f64 d30, d31, d23" + - + asm_text: "vselgt.f32 s0, s1, s0" + - + asm_text: "vselgt.f64 d5, d10, d20" + - + asm_text: "vseleq.f32 s30, s28, s23" + - + asm_text: "vseleq.f64 d2, d4, d8" + - + asm_text: "vselvs.f32 s21, s16, s14" + - + asm_text: "vselvs.f64 d0, d1, d31" + - + asm_text: "vmaxnm.f32 s5, s12, s0" + - + asm_text: "vmaxnm.f64 d5, d22, d30" + - + asm_text: "vminnm.f32 s0, s0, s12" + - + asm_text: "vminnm.f64 d4, d6, d9" + - + asm_text: "vrintz.f32 s3, s24" + - + asm_text: "vrintr.f32 s0, s9" + - + asm_text: "vrinta.f64 d3, d4" + - + asm_text: "vrinta.f32 s12, s1" + - + asm_text: "vrintn.f64 d3, d4" + - + asm_text: "vrintn.f32 s12, s1" + - + asm_text: "vrintp.f64 d3, d4" + - + asm_text: "vrintp.f32 s12, s1" + - + asm_text: "vrintm.f64 d3, d4" + - + asm_text: "vrintm.f32 s12, s1" diff --git a/tests/MC/ARM/thumb-hints.s.yaml b/tests/MC/ARM/thumb-hints.s.yaml new file mode 100644 index 0000000000..a9df28249e --- /dev/null +++ b/tests/MC/ARM/thumb-hints.s.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xbf, 0x10, 0xbf, 0x20, 0xbf, 0x30, 0xbf, 0x40, 0xbf, 0xbf, 0xf3, 0x5f, 0x8f, 0xbf, 0xf3, 0x5f, 0x8f, 0xbf, 0xf3, 0x4f, 0x8f, 0xbf, 0xf3, 0x4f, 0x8f, 0xbf, 0xf3, 0x6f, 0x8f, 0xbf, 0xf3, 0x6f, 0x8f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "nop" + - + asm_text: "yield" + - + asm_text: "wfe" + - + asm_text: "wfi" + - + asm_text: "sev" + - + asm_text: "dmb sy" + - + asm_text: "dmb sy" + - + asm_text: "dsb sy" + - + asm_text: "dsb sy" + - + asm_text: "isb sy" + - + asm_text: "isb sy" diff --git a/tests/MC/ARM/thumb-mov.s.yaml b/tests/MC/ARM/thumb-mov.s.yaml new file mode 100644 index 0000000000..5ea3a9ab44 --- /dev/null +++ b/tests/MC/ARM/thumb-mov.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0x85, 0x46, 0x68, 0x46, 0xed, 0x46, 0x87, 0x46, 0x78, 0x46, 0xff, 0x46, 0x4f, 0xea, 0x00, 0x0d, 0x4f, 0xea, 0x0d, 0x00 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "mov sp, r0" + - + asm_text: "mov r0, sp" + - + asm_text: "mov sp, sp" + - + asm_text: "mov pc, r0" + - + asm_text: "mov r0, pc" + - + asm_text: "mov pc, pc" + - + asm_text: "mov.w sp, r0" + - + asm_text: "mov.w r0, sp" diff --git a/tests/MC/ARM/thumb-neon-crypto.s.yaml b/tests/MC/ARM/thumb-neon-crypto.s.yaml new file mode 100644 index 0000000000..d0091047b0 --- /dev/null +++ b/tests/MC/ARM/thumb-neon-crypto.s.yaml @@ -0,0 +1,38 @@ +test_cases: + - + input: + bytes: [ 0xb0, 0xff, 0x42, 0x03, 0xb0, 0xff, 0x02, 0x03, 0xb0, 0xff, 0xc2, 0x03, 0xb0, 0xff, 0x82, 0x03, 0xb9, 0xff, 0xc2, 0x02, 0xba, 0xff, 0x82, 0x03, 0xba, 0xff, 0xc2, 0x03, 0x02, 0xef, 0x44, 0x0c, 0x22, 0xef, 0x44, 0x0c, 0x12, 0xef, 0x44, 0x0c, 0x32, 0xef, 0x44, 0x0c, 0x02, 0xff, 0x44, 0x0c, 0x12, 0xff, 0x44, 0x0c, 0x22, 0xff, 0x44, 0x0c, 0xe0, 0xef, 0xa1, 0x0e ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "aesd.8 q0, q1" + - + asm_text: "aese.8 q0, q1" + - + asm_text: "aesimc.8 q0, q1" + - + asm_text: "aesmc.8 q0, q1" + - + asm_text: "sha1h.32 q0, q1" + - + asm_text: "sha1su1.32 q0, q1" + - + asm_text: "sha256su0.32 q0, q1" + - + asm_text: "sha1c.32 q0, q1, q2" + - + asm_text: "sha1m.32 q0, q1, q2" + - + asm_text: "sha1p.32 q0, q1, q2" + - + asm_text: "sha1su0.32 q0, q1, q2" + - + asm_text: "sha256h.32 q0, q1, q2" + - + asm_text: "sha256h2.32 q0, q1, q2" + - + asm_text: "sha256su1.32 q0, q1, q2" + - + asm_text: "vmull.p64 q8, d16, d17" diff --git a/tests/MC/ARM/thumb-neon-v8.s.yaml b/tests/MC/ARM/thumb-neon-v8.s.yaml new file mode 100644 index 0000000000..6d8fe53db3 --- /dev/null +++ b/tests/MC/ARM/thumb-neon-v8.s.yaml @@ -0,0 +1,82 @@ +test_cases: + - + input: + bytes: [ 0x05, 0xff, 0x11, 0x4f, 0x08, 0xff, 0x5c, 0x4f, 0x24, 0xff, 0x3e, 0x5f, 0x2a, 0xff, 0xd4, 0x0f, 0xbb, 0xff, 0x06, 0x40, 0xbb, 0xff, 0x8a, 0xc0, 0xbb, 0xff, 0x4c, 0x80, 0xbb, 0xff, 0xe4, 0x80, 0xbb, 0xff, 0x2e, 0x13, 0xbb, 0xff, 0x8a, 0xc3, 0xbb, 0xff, 0x64, 0x23, 0xfb, 0xff, 0xc2, 0xa3, 0xbb, 0xff, 0x21, 0xf1, 0xbb, 0xff, 0x83, 0x51, 0xbb, 0xff, 0x60, 0x61, 0xbb, 0xff, 0xc6, 0xa1, 0xbb, 0xff, 0x25, 0xb2, 0xbb, 0xff, 0xa7, 0xe2, 0xbb, 0xff, 0x6e, 0x82, 0xfb, 0xff, 0xe0, 0x22, 0xba, 0xff, 0x00, 0x34, 0xba, 0xff, 0x48, 0x24, 0xba, 0xff, 0x8c, 0x54, 0xba, 0xff, 0xc6, 0x04, 0xba, 0xff, 0x00, 0x35, 0xfa, 0xff, 0x44, 0x05, 0xba, 0xff, 0xa2, 0xc5, 0xfa, 0xff, 0xc8, 0x25, 0xba, 0xff, 0x80, 0x36, 0xba, 0xff, 0xc8, 0x26, 0xba, 0xff, 0x80, 0x37, 0xba, 0xff, 0xc8, 0x27, 0xba, 0xff, 0x00, 0x34, 0xba, 0xff, 0xc6, 0x04, 0xba, 0xff, 0x00, 0x35, 0xfa, 0xff, 0xc8, 0x25, 0xba, 0xff, 0xc8, 0x27 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmaxnm.f32 d4, d5, d1" + - + asm_text: "vmaxnm.f32 q2, q4, q6" + - + asm_text: "vminnm.f32 d5, d4, d30" + - + asm_text: "vminnm.f32 q0, q13, q2" + - + asm_text: "vcvta.s32.f32 d4, d6" + - + asm_text: "vcvta.u32.f32 d12, d10" + - + asm_text: "vcvta.s32.f32 q4, q6" + - + asm_text: "vcvta.u32.f32 q4, q10" + - + asm_text: "vcvtm.s32.f32 d1, d30" + - + asm_text: "vcvtm.u32.f32 d12, d10" + - + asm_text: "vcvtm.s32.f32 q1, q10" + - + asm_text: "vcvtm.u32.f32 q13, q1" + - + asm_text: "vcvtn.s32.f32 d15, d17" + - + asm_text: "vcvtn.u32.f32 d5, d3" + - + asm_text: "vcvtn.s32.f32 q3, q8" + - + asm_text: "vcvtn.u32.f32 q5, q3" + - + asm_text: "vcvtp.s32.f32 d11, d21" + - + asm_text: "vcvtp.u32.f32 d14, d23" + - + asm_text: "vcvtp.s32.f32 q4, q15" + - + asm_text: "vcvtp.u32.f32 q9, q8" + - + asm_text: "vrintn.f32 d3, d0" + - + asm_text: "vrintn.f32 q1, q4" + - + asm_text: "vrintx.f32 d5, d12" + - + asm_text: "vrintx.f32 q0, q3" + - + asm_text: "vrinta.f32 d3, d0" + - + asm_text: "vrinta.f32 q8, q2" + - + asm_text: "vrintz.f32 d12, d18" + - + asm_text: "vrintz.f32 q9, q4" + - + asm_text: "vrintm.f32 d3, d0" + - + asm_text: "vrintm.f32 q1, q4" + - + asm_text: "vrintp.f32 d3, d0" + - + asm_text: "vrintp.f32 q1, q4" + - + asm_text: "vrintn.f32 d3, d0" + - + asm_text: "vrintx.f32 q0, q3" + - + asm_text: "vrinta.f32 d3, d0" + - + asm_text: "vrintz.f32 q9, q4" + - + asm_text: "vrintp.f32 q1, q4" diff --git a/tests/MC/ARM/thumb-shift-encoding.s.yaml b/tests/MC/ARM/thumb-shift-encoding.s.yaml new file mode 100644 index 0000000000..4909702ff3 --- /dev/null +++ b/tests/MC/ARM/thumb-shift-encoding.s.yaml @@ -0,0 +1,44 @@ +test_cases: + - + input: + bytes: [ 0x6e, 0xeb, 0x00, 0x0c, 0x68, 0xeb, 0x19, 0x01, 0x67, 0xeb, 0x1a, 0x42, 0x66, 0xeb, 0x0a, 0x03, 0x65, 0xeb, 0x0e, 0x44, 0x64, 0xeb, 0x2b, 0x05, 0x63, 0xeb, 0x2c, 0x46, 0x62, 0xeb, 0x3c, 0x07, 0x61, 0xeb, 0x30, 0x48, 0x0e, 0xea, 0x00, 0x0c, 0x08, 0xea, 0x19, 0x01, 0x07, 0xea, 0x1a, 0x42, 0x06, 0xea, 0x0a, 0x03, 0x05, 0xea, 0x0e, 0x44, 0x04, 0xea, 0x2b, 0x05, 0x03, 0xea, 0x2c, 0x46, 0x02, 0xea, 0x3c, 0x07, 0x01, 0xea, 0x30, 0x48 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "sbc.w r12, lr, r0" + - + asm_text: "sbc.w r1, r8, r9, lsr #0x20" + - + asm_text: "sbc.w r2, r7, r10, lsr #0x10" + - + asm_text: "sbc.w r3, r6, r10" + - + asm_text: "sbc.w r4, r5, lr, lsl #0x10" + - + asm_text: "sbc.w r5, r4, r11, asr #0x20" + - + asm_text: "sbc.w r6, r3, r12, asr #0x10" + - + asm_text: "sbc.w r7, r2, r12, rrx" + - + asm_text: "sbc.w r8, r1, r0, ror #0x10" + - + asm_text: "and.w r12, lr, r0" + - + asm_text: "and.w r1, r8, r9, lsr #0x20" + - + asm_text: "and.w r2, r7, r10, lsr #0x10" + - + asm_text: "and.w r3, r6, r10" + - + asm_text: "and.w r4, r5, lr, lsl #0x10" + - + asm_text: "and.w r5, r4, r11, asr #0x20" + - + asm_text: "and.w r6, r3, r12, asr #0x10" + - + asm_text: "and.w r7, r2, r12, rrx" + - + asm_text: "and.w r8, r1, r0, ror #0x10" diff --git a/tests/MC/ARM/thumb.s.yaml b/tests/MC/ARM/thumb.s.yaml new file mode 100644 index 0000000000..8bff9f5236 --- /dev/null +++ b/tests/MC/ARM/thumb.s.yaml @@ -0,0 +1,44 @@ +test_cases: + - + input: + bytes: [ 0x91, 0x42, 0x16, 0xbc, 0xfe, 0xde, 0xc8, 0x47, 0xd0, 0x47, 0x1a, 0xba, 0x63, 0xba, 0xf5, 0xba, 0x5a, 0xb2, 0x1a, 0xb2, 0x2c, 0x42, 0xf3, 0xb2, 0xb3, 0xb2, 0x8b, 0x58, 0x02, 0xbe, 0xc0, 0x46, 0x67, 0xb6, 0x78, 0x46 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "cmp r1, r2" + - + asm_text: "pop {r1, r2, r4}" + - + asm_text: "trap" + - + asm_text: "blx r9" + - + asm_text: "blx r10" + - + asm_text: "rev r2, r3" + - + asm_text: "rev16 r3, r4" + - + asm_text: "revsh r5, r6" + - + asm_text: "sxtb r2, r3" + - + asm_text: "sxth r2, r3" + - + asm_text: "tst r4, r5" + - + asm_text: "uxtb r3, r6" + - + asm_text: "uxth r3, r6" + - + asm_text: "ldr r3, [r1, r2]" + - + asm_text: "bkpt #2" + - + asm_text: "mov r8, r8" + - + asm_text: "cpsie aif" + - + asm_text: "mov r0, pc" diff --git a/tests/MC/ARM/thumb2-b.w-encodingT4.s.yaml b/tests/MC/ARM/thumb2-b.w-encodingT4.s.yaml new file mode 100644 index 0000000000..6f5e220882 --- /dev/null +++ b/tests/MC/ARM/thumb2-b.w-encodingT4.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x36, 0xf0, 0x06, 0xbc ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "b.w #0x3680c" diff --git a/tests/MC/ARM/thumb2-branches.s.yaml b/tests/MC/ARM/thumb2-branches.s.yaml new file mode 100644 index 0000000000..b700f2ae15 --- /dev/null +++ b/tests/MC/ARM/thumb2-branches.s.yaml @@ -0,0 +1,192 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe4, 0xff, 0xe3, 0xff, 0xf7, 0x00, 0xbc, 0x00, 0xf0, 0xff, 0xbb, 0x66, 0xf6, 0x30, 0xbc, 0x99, 0xf1, 0xcf, 0xbb, 0x00, 0xe4, 0xff, 0xe3, 0xff, 0xf7, 0xff, 0xbb, 0x00, 0xf0, 0x00, 0xbc, 0x66, 0xf6, 0x30, 0xbc, 0x99, 0xf1, 0xcf, 0xbb, 0x08, 0xbf, 0x00, 0xe4, 0x18, 0xbf, 0x01, 0xe4, 0xc8, 0xbf, 0xff, 0xf7, 0x00, 0xbc, 0xd8, 0xbf, 0x00, 0xf0, 0xff, 0xbb, 0xa8, 0xbf, 0x66, 0xf6, 0x30, 0xbc, 0xb8, 0xbf, 0x99, 0xf1, 0xcf, 0xbb, 0x80, 0xd0, 0x7f, 0xd1, 0x00, 0xf0, 0x80, 0xf8, 0x18, 0xbf, 0x00, 0xf0, 0x80, 0xf8, 0x3f, 0xf5, 0x80, 0xaf, 0x40, 0xf0, 0x7f, 0x80, 0xc0, 0xf6, 0x00, 0x80, 0xbf, 0xf2, 0xff, 0xaf, 0x80, 0xd1, 0x7f, 0xdc, 0x7f, 0xf4, 0x7f, 0xaf, 0x00, 0xf3, 0x80, 0x80, 0x40, 0xf4, 0x00, 0x80, 0x3f, 0xf3, 0xff, 0xaf, 0x08, 0xbf, 0x08, 0x44, 0x40, 0xd1, 0x0c, 0xbf, 0x08, 0x44, 0x40, 0xe0, 0x00, 0xe4, 0xff, 0xe3, 0xff, 0xf7, 0x00, 0xbc, 0x00, 0xf0, 0xff, 0xbb, 0x66, 0xf6, 0x30, 0xbc, 0x99, 0xf1, 0xcf, 0xbb, 0x00, 0xe4, 0xff, 0xe3, 0xff, 0xf7, 0xff, 0xbb, 0x00, 0xf0, 0x00, 0xbc, 0x66, 0xf6, 0x30, 0xbc, 0x99, 0xf1, 0xcf, 0xbb, 0x08, 0xbf, 0x00, 0xe4, 0x18, 0xbf, 0x01, 0xe4, 0xc8, 0xbf, 0xff, 0xf7, 0x00, 0xbc, 0xd8, 0xbf, 0x00, 0xf0, 0xff, 0xbb, 0xa8, 0xbf, 0x66, 0xf6, 0x30, 0xbc, 0xb8, 0xbf, 0x99, 0xf1, 0xcf, 0xbb, 0x80, 0xd0, 0x7f, 0xd1, 0x3f, 0xf5, 0x80, 0xaf, 0x40, 0xf0, 0x7f, 0x80, 0xc0, 0xf6, 0x00, 0x80, 0xbf, 0xf2, 0xff, 0xaf, 0x80, 0xd1, 0x7f, 0xdc, 0x7f, 0xf4, 0x7f, 0xaf, 0x00, 0xf3, 0x80, 0x80, 0x40, 0xf4, 0x00, 0x80, 0x3f, 0xf3, 0xff, 0xaf, 0x08, 0xbf, 0x08, 0x44, 0x40, 0xd1, 0x0c, 0xbf, 0x08, 0x44, 0x40, 0xe0, 0x01, 0xe0, 0x00, 0xf0, 0x01, 0xf8, 0x01, 0xd0, 0x08, 0xb1, 0x00, 0xf0, 0x02, 0xe8 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "b #-0x800" + - + asm_text: "b #0x7fe" + - + asm_text: "b.w #-0x800" + - + asm_text: "b.w #0x7fe" + - + asm_text: "b.w #-0x1997a0" + - + asm_text: "b.w #0x19979e" + - + asm_text: "b #-0x800" + - + asm_text: "b #0x7fe" + - + asm_text: "b.w #-0x802" + - + asm_text: "b.w #0x800" + - + asm_text: "b.w #-0x1997a0" + - + asm_text: "b.w #0x19979e" + - + asm_text: "it eq" + - + asm_text: "beq #-0x800" + - + asm_text: "it ne" + - + asm_text: "bne #-0x7fe" + - + asm_text: "it gt" + - + asm_text: "bgt.w #-0x800" + - + asm_text: "it le" + - + asm_text: "ble.w #0x7fe" + - + asm_text: "it ge" + - + asm_text: "bge.w #-0x1997a0" + - + asm_text: "it lt" + - + asm_text: "blt.w #0x19979e" + - + asm_text: "beq #-0x100" + - + asm_text: "bne #0xfe" + - + asm_text: "bl #0x100" + - + asm_text: "it ne" + - + asm_text: "blne #0x100" + - + asm_text: "bmi.w #-0x100" + - + asm_text: "bne.w #0xfe" + - + asm_text: "blt.w #-0x100000" + - + asm_text: "bge.w #0xffffe" + - + asm_text: "bne #-0x100" + - + asm_text: "bgt #0xfe" + - + asm_text: "bne.w #-0x102" + - + asm_text: "bgt.w #0x100" + - + asm_text: "bne.w #-0x100000" + - + asm_text: "bgt.w #0xffffe" + - + asm_text: "it eq" + - + asm_text: "addeq r0, r1" + - + asm_text: "bne #0x80" + - + asm_text: "ite eq" + - + asm_text: "addeq r0, r1" + - + asm_text: "bne #0x80" + - + asm_text: "b #-0x800" + - + asm_text: "b #0x7fe" + - + asm_text: "b.w #-0x800" + - + asm_text: "b.w #0x7fe" + - + asm_text: "b.w #-0x1997a0" + - + asm_text: "b.w #0x19979e" + - + asm_text: "b #-0x800" + - + asm_text: "b #0x7fe" + - + asm_text: "b.w #-0x802" + - + asm_text: "b.w #0x800" + - + asm_text: "b.w #-0x1997a0" + - + asm_text: "b.w #0x19979e" + - + asm_text: "it eq" + - + asm_text: "beq #-0x800" + - + asm_text: "it ne" + - + asm_text: "bne #-0x7fe" + - + asm_text: "it gt" + - + asm_text: "bgt.w #-0x800" + - + asm_text: "it le" + - + asm_text: "ble.w #0x7fe" + - + asm_text: "it ge" + - + asm_text: "bge.w #-0x1997a0" + - + asm_text: "it lt" + - + asm_text: "blt.w #0x19979e" + - + asm_text: "beq #-0x100" + - + asm_text: "bne #0xfe" + - + asm_text: "bmi.w #-0x100" + - + asm_text: "bne.w #0xfe" + - + asm_text: "blt.w #-0x100000" + - + asm_text: "bge.w #0xffffe" + - + asm_text: "bne #-0x100" + - + asm_text: "bgt #0xfe" + - + asm_text: "bne.w #-0x102" + - + asm_text: "bgt.w #0x100" + - + asm_text: "bne.w #-0x100000" + - + asm_text: "bgt.w #0xffffe" + - + asm_text: "it eq" + - + asm_text: "addeq r0, r1" + - + asm_text: "bne #0x80" + - + asm_text: "ite eq" + - + asm_text: "addeq r0, r1" + - + asm_text: "bne #0x80" + - + asm_text: "b #2" + - + asm_text: "bl #2" + - + asm_text: "beq #2" + - + asm_text: "cbz r0, #2" + - + asm_text: "blx #4" diff --git a/tests/MC/ARM/thumb2-bxj-v8.s.yaml b/tests/MC/ARM/thumb2-bxj-v8.s.yaml new file mode 100644 index 0000000000..280932a4d3 --- /dev/null +++ b/tests/MC/ARM/thumb2-bxj-v8.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xcd, 0xf3, 0x00, 0x8f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "bxj sp" diff --git a/tests/MC/ARM/thumb2-bxj.s.yaml b/tests/MC/ARM/thumb2-bxj.s.yaml new file mode 100644 index 0000000000..51e7838627 --- /dev/null +++ b/tests/MC/ARM/thumb2-bxj.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xc2, 0xf3, 0x00, 0x8f ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "bxj r2" diff --git a/tests/MC/ARM/thumb2-ldr.w-str.w.s.yaml b/tests/MC/ARM/thumb2-ldr.w-str.w.s.yaml new file mode 100644 index 0000000000..baf6f7437a --- /dev/null +++ b/tests/MC/ARM/thumb2-ldr.w-str.w.s.yaml @@ -0,0 +1,118 @@ +test_cases: + - + input: + bytes: [ 0x51, 0xf8, 0x04, 0x3b, 0x51, 0xf8, 0x04, 0x3b, 0x40, 0xf8, 0x04, 0x3b, 0x40, 0xf8, 0x04, 0x3b, 0x51, 0xf8, 0x04, 0x3d, 0x51, 0xf8, 0x04, 0x3d, 0x40, 0xf8, 0x04, 0x3d, 0x40, 0xf8, 0x04, 0x3d, 0x51, 0xf8, 0x04, 0x0d, 0x51, 0xf8, 0x04, 0xdd, 0x51, 0xf8, 0x04, 0xfd, 0x50, 0xf8, 0x04, 0x1d, 0x5d, 0xf8, 0x04, 0x1d, 0x50, 0xf8, 0xff, 0x1f, 0x50, 0xf8, 0xff, 0x1d, 0x50, 0xf8, 0x00, 0x1f, 0x08, 0xbf, 0x50, 0xf8, 0xff, 0x1f, 0xd8, 0xbf, 0x50, 0xf8, 0xff, 0x1f, 0x51, 0xf8, 0x04, 0x0b, 0x51, 0xf8, 0x04, 0xdb, 0x51, 0xf8, 0x04, 0xfb, 0x51, 0xf8, 0x04, 0x0b, 0x5d, 0xf8, 0x04, 0x0b, 0x5f, 0xf8, 0x04, 0x0b, 0x51, 0xf8, 0xff, 0x0b, 0x51, 0xf8, 0x00, 0x0b, 0x51, 0xf8, 0xff, 0x09, 0x08, 0xbf, 0x51, 0xf8, 0xff, 0x0b, 0xd8, 0xbf, 0x51, 0xf8, 0xff, 0x0b, 0x40, 0xf8, 0x04, 0x1d, 0x40, 0xf8, 0x04, 0xdd, 0x42, 0xf8, 0x04, 0x1d, 0x4d, 0xf8, 0x04, 0x1d, 0x42, 0xf8, 0xff, 0x1f, 0x42, 0xf8, 0x00, 0x1f, 0x42, 0xf8, 0xff, 0x1d, 0x08, 0xbf, 0x42, 0xf8, 0xff, 0x1f, 0xd8, 0xbf, 0x42, 0xf8, 0xff, 0x1f, 0x40, 0xf8, 0x04, 0x1b, 0x40, 0xf8, 0x04, 0xdb, 0x41, 0xf8, 0x04, 0x0b, 0x4d, 0xf8, 0x04, 0x0b, 0x40, 0xf8, 0xff, 0x1b, 0x40, 0xf8, 0x00, 0x1b, 0x40, 0xf8, 0xff, 0x19, 0x08, 0xbf, 0x40, 0xf8, 0xff, 0x1b, 0xd8, 0xbf, 0x40, 0xf8, 0xff, 0x1b ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "ldr r3, [r1], #4" + - + asm_text: "ldr r3, [r1], #4" + - + asm_text: "str r3, [r0], #4" + - + asm_text: "str r3, [r0], #4" + - + asm_text: "ldr r3, [r1, #-4]!" + - + asm_text: "ldr r3, [r1, #-4]!" + - + asm_text: "str r3, [r0, #-4]!" + - + asm_text: "str r3, [r0, #-4]!" + - + asm_text: "ldr r0, [r1, #-4]!" + - + asm_text: "ldr sp, [r1, #-4]!" + - + asm_text: "ldr pc, [r1, #-4]!" + - + asm_text: "ldr r1, [r0, #-4]!" + - + asm_text: "ldr r1, [sp, #-4]!" + - + asm_text: "ldr r1, [r0, #0xff]!" + - + asm_text: "ldr r1, [r0, #-0xff]!" + - + asm_text: "ldr r1, [r0, #0]!" + - + asm_text: "it eq" + - + asm_text: "ldreq r1, [r0, #0xff]!" + - + asm_text: "it le" + - + asm_text: "ldrle r1, [r0, #0xff]!" + - + asm_text: "ldr r0, [r1], #4" + - + asm_text: "ldr sp, [r1], #4" + - + asm_text: "ldr pc, [r1], #4" + - + asm_text: "ldr r0, [r1], #4" + - + asm_text: "pop {r0}" + - + asm_text: "ldr.w r0, [pc, #-0xb04]" + - + asm_text: "ldr r0, [r1], #0xff" + - + asm_text: "ldr r0, [r1], #0" + - + asm_text: "ldr r0, [r1], #-0xff" + - + asm_text: "it eq" + - + asm_text: "ldreq r0, [r1], #0xff" + - + asm_text: "it le" + - + asm_text: "ldrle r0, [r1], #0xff" + - + asm_text: "str r1, [r0, #-4]!" + - + asm_text: "str sp, [r0, #-4]!" + - + asm_text: "str r1, [r2, #-4]!" + - + asm_text: "str r1, [sp, #-4]!" + - + asm_text: "str r1, [r2, #0xff]!" + - + asm_text: "str r1, [r2, #0]!" + - + asm_text: "str r1, [r2, #-0xff]!" + - + asm_text: "it eq" + - + asm_text: "streq r1, [r2, #0xff]!" + - + asm_text: "it le" + - + asm_text: "strle r1, [r2, #0xff]!" + - + asm_text: "str r1, [r0], #4" + - + asm_text: "str sp, [r0], #4" + - + asm_text: "str r0, [r1], #4" + - + asm_text: "str r0, [sp], #4" + - + asm_text: "str r1, [r0], #0xff" + - + asm_text: "str r1, [r0], #0" + - + asm_text: "str r1, [r0], #-0xff" + - + asm_text: "it eq" + - + asm_text: "streq r1, [r0], #0xff" + - + asm_text: "it le" + - + asm_text: "strle r1, [r0], #0xff" diff --git a/tests/MC/ARM/thumb2-ldrexd-strexd.s.yaml b/tests/MC/ARM/thumb2-ldrexd-strexd.s.yaml new file mode 100644 index 0000000000..044932efb2 --- /dev/null +++ b/tests/MC/ARM/thumb2-ldrexd-strexd.s.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0xd2, 0xe8, 0x7f, 0x01, 0xc6, 0xe8, 0x73, 0x45 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "ldrexd r0, r1, [r2]" + - + asm_text: "strexd r3, r4, r5, [r6]" diff --git a/tests/MC/ARM/thumb2-mclass.s.yaml b/tests/MC/ARM/thumb2-mclass.s.yaml new file mode 100644 index 0000000000..fa7c524bc5 --- /dev/null +++ b/tests/MC/ARM/thumb2-mclass.s.yaml @@ -0,0 +1,44 @@ +test_cases: + - + input: + bytes: [ 0xef, 0xf3, 0x00, 0x80, 0xef, 0xf3, 0x01, 0x80, 0xef, 0xf3, 0x02, 0x80, 0xef, 0xf3, 0x03, 0x80, 0xef, 0xf3, 0x05, 0x80, 0xef, 0xf3, 0x06, 0x80, 0xef, 0xf3, 0x07, 0x80, 0xef, 0xf3, 0x08, 0x80, 0xef, 0xf3, 0x09, 0x80, 0xef, 0xf3, 0x10, 0x80, 0xef, 0xf3, 0x14, 0x80, 0x80, 0xf3, 0x05, 0x88, 0x80, 0xf3, 0x06, 0x88, 0x80, 0xf3, 0x07, 0x88, 0x80, 0xf3, 0x08, 0x88, 0x80, 0xf3, 0x09, 0x88, 0x80, 0xf3, 0x10, 0x88, 0x80, 0xf3, 0x14, 0x88 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "mrs r0, apsr" + - + asm_text: "mrs r0, iapsr" + - + asm_text: "mrs r0, eapsr" + - + asm_text: "mrs r0, xpsr" + - + asm_text: "mrs r0, ipsr" + - + asm_text: "mrs r0, epsr" + - + asm_text: "mrs r0, iepsr" + - + asm_text: "mrs r0, msp" + - + asm_text: "mrs r0, psp" + - + asm_text: "mrs r0, primask" + - + asm_text: "mrs r0, control" + - + asm_text: "msr ipsr, r0" + - + asm_text: "msr epsr, r0" + - + asm_text: "msr iepsr, r0" + - + asm_text: "msr msp, r0" + - + asm_text: "msr psp, r0" + - + asm_text: "msr primask, r0" + - + asm_text: "msr control, r0" diff --git a/tests/MC/ARM/thumb2-narrow-dp.ll.yaml b/tests/MC/ARM/thumb2-narrow-dp.ll.yaml new file mode 100644 index 0000000000..5cdb15dd08 --- /dev/null +++ b/tests/MC/ARM/thumb2-narrow-dp.ll.yaml @@ -0,0 +1,836 @@ +test_cases: + - + input: + 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0x43, 0x54, 0xea, 0x01, 0x04, 0x51, 0xea, 0x05, 0x05, 0x41, 0xea, 0x02, 0x02, 0x0f, 0x43, 0x0f, 0x43, 0x51, 0xea, 0x08, 0x08, 0x58, 0xea, 0x01, 0x08, 0x58, 0xea, 0x01, 0x01, 0x50, 0xea, 0x08, 0x00, 0x51, 0xea, 0x41, 0x01, 0x51, 0xea, 0x50, 0x00, 0x08, 0xbf, 0x42, 0xea, 0x01, 0x00, 0x08, 0xbf, 0x0d, 0x43, 0x08, 0xbf, 0x0d, 0x43, 0x08, 0xbf, 0x42, 0xea, 0x01, 0x02, 0x08, 0xbf, 0x41, 0xea, 0x03, 0x03, 0x08, 0xbf, 0x51, 0xea, 0x04, 0x04, 0x08, 0xbf, 0x0f, 0x43, 0x08, 0xbf, 0x0f, 0x43, 0x08, 0xbf, 0x41, 0xea, 0x08, 0x08, 0x08, 0xbf, 0x48, 0xea, 0x01, 0x08, 0x08, 0xbf, 0x48, 0xea, 0x00, 0x00, 0x08, 0xbf, 0x40, 0xea, 0x08, 0x00, 0x08, 0xbf, 0x42, 0xea, 0x41, 0x02, 0x08, 0xbf, 0x41, 0xea, 0x52, 0x02, 0x32, 0xea, 0x01, 0x03, 0x8a, 0x43, 0x32, 0xea, 0x01, 0x01, 0x32, 0xea, 0x01, 0x02, 0x31, 0xea, 0x00, 0x00, 0x21, 0xea, 0x00, 0x00, 0x8f, 0x43, 0x31, 0xea, 0x08, 0x08, 0x38, 0xea, 0x01, 0x08, 0x38, 0xea, 0x07, 0x07, 0x35, 0xea, 0x08, 0x05, 0x33, 0xea, 0x41, 0x03, 0x31, 0xea, 0x54, 0x04, 0x08, 0xbf, 0x22, 0xea, 0x01, 0x00, 0x08, 0xbf, 0x8d, 0x43, 0x08, 0xbf, 0x25, 0xea, 0x01, 0x01, 0x08, 0xbf, 0x24, 0xea, 0x01, 0x04, 0x08, 0xbf, 0x21, 0xea, 0x02, 0x02, 0x08, 0xbf, 0x31, 0xea, 0x05, 0x05, 0x08, 0xbf, 0x8f, 0x43, 0x08, 0xbf, 0x21, 0xea, 0x08, 0x08, 0x08, 0xbf, 0x28, 0xea, 0x01, 0x08, 0x08, 0xbf, 0x28, 0xea, 0x00, 0x00, 0x08, 0xbf, 0x22, 0xea, 0x08, 0x02, 0x08, 0xbf, 0x24, 0xea, 0x41, 0x04, 0x08, 0xbf, 0x21, 0xea, 0x55, 0x05 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "adds r0, r0, #5" + - + asm_text: "adds r1, #8" + - + asm_text: "adds.w r1, r1, #8" + - + asm_text: "adds.w r8, r8, #8" + - + asm_text: "it eq" + - + asm_text: "addeq r0, r0, #5" + - + asm_text: "it eq" + - + asm_text: "addeq r1, #8" + - + asm_text: "it eq" + - + asm_text: "addseq.w r0, r0, #5" + - + asm_text: "it eq" + - + asm_text: "addseq.w r1, r1, #8" + - + asm_text: "adds r0, r2, r1" + - + asm_text: "adds r2, r2, r1" + - + asm_text: "add r3, r1" + - + asm_text: "it eq" + - + asm_text: "addeq r0, r2, r1" + - + asm_text: "it eq" + - + asm_text: "addeq r2, r2, r1" + - + asm_text: "it eq" + - + asm_text: "addseq.w r0, r2, r1" + - + asm_text: "it eq" + - + asm_text: "addseq.w r2, r2, r1" + - + asm_text: "add r3, r1" + - + asm_text: "add r4, pc" + - + asm_text: "add r4, pc" + - + asm_text: "add pc, r2" + - + asm_text: "add pc, r2" + - + asm_text: "add pc, sp, pc" + - + asm_text: "add sp, #0x14" + - + asm_text: "add sp, #0x1fc" + - + asm_text: "add.w sp, sp, #0x200" + - + asm_text: "add r9, sp, r9" + - + asm_text: "add sp, r10" + - + asm_text: "add sp, r10" + - + asm_text: "add sp, pc" + - + asm_text: "ands.w r0, r2, r1" + - + asm_text: "ands r2, r1" + - + asm_text: "ands r2, r1" + - + asm_text: "ands.w r0, r0, r1" + - + asm_text: "ands.w r3, r1, r3" + - + asm_text: "and.w r0, r1, r0" + - + asm_text: "ands r7, r1" + - + asm_text: "ands r7, r1" + - + asm_text: "ands.w r8, r1, r8" + - + asm_text: "ands.w r8, r8, r1" + - + asm_text: "ands.w r0, r8, r0" + - + asm_text: "ands.w r1, r1, r8" + - + asm_text: "ands.w r2, r2, r1, lsl #1" + - + asm_text: "ands.w r0, r1, r0, lsr #1" + - + asm_text: "it eq" + - + asm_text: "andeq.w r0, r2, r1" + - + asm_text: "it eq" + - + asm_text: "andeq r3, r1" + - + asm_text: "it eq" + - + asm_text: "andeq r3, r1" + - + asm_text: "it eq" + - + asm_text: "andeq.w r0, r0, r1" + - + asm_text: "it eq" + - + asm_text: "andeq.w r2, r1, r2" + - + asm_text: "it eq" + - + asm_text: "andseq.w r0, r1, r0" + - + asm_text: "it eq" + - + asm_text: "andeq r7, r1" + - + asm_text: "it eq" + - + asm_text: "andeq r7, r1" + - + asm_text: "it eq" + - + asm_text: "andeq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "andeq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "andeq.w r4, r8, r4" + - + asm_text: "it eq" + - + asm_text: "andeq.w r4, r4, r8" + - + asm_text: "it eq" + - + asm_text: "andeq.w r0, r0, r1, lsl #1" + - + asm_text: "it eq" + - + asm_text: "andeq.w r5, r1, r5, lsr #1" + - + asm_text: "eors.w r0, r2, r1" + - + asm_text: "eors r5, r1" + - + asm_text: "eors r5, r1" + - + asm_text: "eors.w r0, r0, r1" + - + asm_text: "eors.w r2, r1, r2" + - + asm_text: "eor.w r1, r1, r1" + - + asm_text: "eors r7, r1" + - + asm_text: "eors r7, r1" + - + asm_text: "eors.w r8, r1, r8" + - + asm_text: "eors.w r8, r8, r1" + - + asm_text: "eors.w r6, r8, r6" + - + asm_text: "eors.w r0, r0, r8" + - + asm_text: "eors.w r2, r2, r1, lsl #1" + - + asm_text: "eors.w r0, r1, r0, lsr #1" + - + asm_text: "it eq" + - + asm_text: "eoreq.w r3, r2, r1" + - + asm_text: "it eq" + - + asm_text: "eoreq r0, r1" + - + asm_text: "it eq" + - + asm_text: "eoreq r2, r1" + - + asm_text: "it eq" + - + asm_text: "eoreq.w r3, r3, r1" + - + asm_text: "it eq" + - + asm_text: "eoreq.w r0, r1, r0" + - + asm_text: "it eq" + - + asm_text: "eorseq.w r1, r1, r1" + - + asm_text: "it eq" + - + asm_text: "eoreq r7, r1" + - + asm_text: "it eq" + - + asm_text: "eoreq r7, r1" + - + asm_text: "it eq" + - + asm_text: "eoreq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "eoreq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "eoreq.w r0, r8, r0" + - + asm_text: "it eq" + - + asm_text: "eoreq.w r3, r3, r8" + - + asm_text: "it eq" + - + asm_text: "eoreq.w r4, r4, r1, lsl #1" + - + asm_text: "it eq" + - + asm_text: "eoreq.w r0, r1, r0, lsr #1" + - + asm_text: "lsls.w r0, r2, r1" + - + asm_text: "lsls r2, r1" + - + asm_text: "lsls.w r2, r1, r2" + - + asm_text: "lsls.w r0, r0, r1" + - + asm_text: "lsls.w r4, r1, r4" + - + asm_text: "lsl.w r4, r1, r4" + - + asm_text: "lsls r7, r1" + - + asm_text: "lsls.w r8, r1, r8" + - + asm_text: "lsls.w r8, r8, r1" + - + asm_text: "lsls.w r3, r8, r3" + - + asm_text: "lsls.w r5, r5, r8" + - + asm_text: "it eq" + - + asm_text: "lsleq.w r0, r2, r1" + - + asm_text: "it eq" + - + asm_text: "lsleq r2, r1" + - + asm_text: "it eq" + - + asm_text: "lsleq.w r2, r1, r2" + - + asm_text: "it eq" + - + asm_text: "lsleq.w r0, r0, r1" + - + asm_text: "it eq" + - + asm_text: "lsleq.w r3, r1, r3" + - + asm_text: "it eq" + - + asm_text: "lslseq.w r4, r1, r4" + - + asm_text: "it eq" + - + asm_text: "lsleq r7, r1" + - + asm_text: "it eq" + - + asm_text: "lsleq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "lsleq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "lsleq.w r0, r8, r0" + - + asm_text: "it eq" + - + asm_text: "lsleq.w r3, r3, r8" + - + asm_text: "lsrs.w r6, r2, r1" + - + asm_text: "lsrs r2, r1" + - + asm_text: "lsrs.w r2, r1, r2" + - + asm_text: "lsrs.w r2, r2, r1" + - + asm_text: "lsrs.w r3, r1, r3" + - + asm_text: "lsr.w r4, r1, r4" + - + asm_text: "lsrs r7, r1" + - + asm_text: "lsrs.w r8, r1, r8" + - + asm_text: "lsrs.w r8, r8, r1" + - + asm_text: "lsrs.w r2, r8, r2" + - + asm_text: "lsrs.w r5, r5, r8" + - + asm_text: "it eq" + - + asm_text: "lsreq.w r6, r2, r1" + - + asm_text: "it eq" + - + asm_text: "lsreq r7, r1" + - + asm_text: "it eq" + - + asm_text: "lsreq.w r7, r1, r7" + - + asm_text: "it eq" + - + asm_text: "lsreq.w r7, r7, r1" + - + asm_text: "it eq" + - + asm_text: "lsreq.w r2, r1, r2" + - + asm_text: "it eq" + - + asm_text: "lsrseq.w r0, r1, r0" + - + asm_text: "it eq" + - + asm_text: "lsreq r7, r1" + - + asm_text: "it eq" + - + asm_text: "lsreq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "lsreq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "lsreq.w r1, r8, r1" + - + asm_text: "it eq" + - + asm_text: "lsreq.w r4, r4, r8" + - + asm_text: "asrs.w r7, r6, r5" + - + asm_text: "asrs r0, r1" + - + asm_text: "asrs.w r0, r1, r0" + - + asm_text: "asrs.w r3, r3, r1" + - + asm_text: "asrs.w r1, r1, r1" + - + asm_text: "asr.w r0, r1, r0" + - + asm_text: "asrs r7, r1" + - + asm_text: "asrs.w r8, r1, r8" + - + asm_text: "asrs.w r8, r8, r1" + - + asm_text: "asrs.w r5, r8, r5" + - + asm_text: "asrs.w r5, r5, r8" + - + asm_text: "it eq" + - + asm_text: "asreq.w r0, r2, r1" + - + asm_text: "it eq" + - + asm_text: "asreq r2, r1" + - + asm_text: "it eq" + - + asm_text: "asreq.w r1, r2, r1" + - + asm_text: "it eq" + - + asm_text: "asreq.w r4, r4, r1" + - + asm_text: "it eq" + - + asm_text: "asreq.w r6, r1, r6" + - + asm_text: "it eq" + - + asm_text: "asrseq.w r3, r1, r3" + - + asm_text: "it eq" + - + asm_text: "asreq r7, r1" + - + asm_text: "it eq" + - + asm_text: "asreq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "asreq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "asreq.w r1, r8, r1" + - + asm_text: "it eq" + - + asm_text: "asreq.w r3, r3, r8" + - + asm_text: "adcs.w r5, r2, r1" + - + asm_text: "adcs r5, r1" + - + asm_text: "adcs r3, r1" + - + asm_text: "adcs.w r2, r2, r1" + - + asm_text: "adcs.w r3, r1, r3" + - + asm_text: "adc.w r0, r1, r0" + - + asm_text: "adcs r7, r1" + - + asm_text: "adcs r7, r1" + - + asm_text: "adcs.w r8, r1, r8" + - + asm_text: "adcs.w r8, r8, r1" + - + asm_text: "adcs.w r5, r8, r5" + - + asm_text: "adcs.w r2, r2, r8" + - + asm_text: "adcs.w r3, r3, r1, lsl #1" + - + asm_text: "adcs.w r4, r1, r4, lsr #1" + - + asm_text: "it eq" + - + asm_text: "adceq.w r1, r2, r3" + - + asm_text: "it eq" + - + asm_text: "adceq r1, r1" + - + asm_text: "it eq" + - + asm_text: "adceq r3, r1" + - + asm_text: "it eq" + - + asm_text: "adceq.w r3, r3, r1" + - + asm_text: "it eq" + - + asm_text: "adceq.w r0, r1, r0" + - + asm_text: "it eq" + - + asm_text: "adcseq.w r3, r1, r3" + - + asm_text: "it eq" + - + asm_text: "adceq r7, r1" + - + asm_text: "it eq" + - + asm_text: "adceq r7, r1" + - + asm_text: "it eq" + - + asm_text: "adceq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "adceq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "adceq.w r3, r8, r3" + - + asm_text: "it eq" + - + asm_text: "adceq.w r1, r1, r8" + - + asm_text: "it eq" + - + asm_text: "adceq.w r2, r2, r1, lsl #1" + - + asm_text: "it eq" + - + asm_text: "adceq.w r1, r1, r1, lsr #1" + - + asm_text: "sbcs.w r3, r2, r1" + - + asm_text: "sbcs r4, r1" + - + asm_text: "sbcs.w r1, r4, r1" + - + asm_text: "sbcs.w r4, r4, r1" + - + asm_text: "sbcs.w r2, r1, r2" + - + asm_text: "sbc.w r0, r1, r0" + - + asm_text: "sbcs r7, r1" + - + asm_text: "sbcs.w r8, r1, r8" + - + asm_text: "sbcs.w r8, r8, r1" + - + asm_text: "sbcs.w r4, r8, r4" + - + asm_text: "sbcs.w r3, r3, r8" + - + asm_text: "sbcs.w r2, r2, r1, lsl #1" + - + asm_text: "sbcs.w r5, r1, r5, lsr #1" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r5, r2, r1" + - + asm_text: "it eq" + - + asm_text: "sbceq r5, r1" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r1, r5, r1" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r5, r5, r1" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r0, r1, r0" + - + asm_text: "it eq" + - + asm_text: "sbcseq.w r2, r1, r2" + - + asm_text: "it eq" + - + asm_text: "sbceq r7, r1" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r7, r8, r7" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r7, r7, r8" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r2, r2, r1, lsl #1" + - + asm_text: "it eq" + - + asm_text: "sbceq.w r5, r1, r5, lsr #1" + - + asm_text: "rors.w r3, r2, r1" + - + asm_text: "rors r0, r1" + - + asm_text: "rors.w r1, r0, r1" + - + asm_text: "rors.w r2, r2, r1" + - + asm_text: "rors.w r2, r1, r2" + - + asm_text: "ror.w r5, r1, r5" + - + asm_text: "rors r7, r1" + - + asm_text: "rors.w r8, r1, r8" + - + asm_text: "rors.w r8, r8, r1" + - + asm_text: "rors.w r6, r8, r6" + - + asm_text: "rors.w r6, r6, r8" + - + asm_text: "it eq" + - + asm_text: "roreq.w r4, r2, r1" + - + asm_text: "it eq" + - + asm_text: "roreq r4, r1" + - + asm_text: "it eq" + - + asm_text: "roreq.w r1, r4, r1" + - + asm_text: "it eq" + - + asm_text: "roreq.w r4, r4, r1" + - + asm_text: "it eq" + - + asm_text: "roreq.w r0, r1, r0" + - + asm_text: "it eq" + - + asm_text: "rorseq.w r0, r1, r0" + - + asm_text: "it eq" + - + asm_text: "roreq r7, r1" + - + asm_text: "it eq" + - + asm_text: "roreq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "roreq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "roreq.w r3, r8, r3" + - + asm_text: "it eq" + - + asm_text: "roreq.w r1, r1, r8" + - + asm_text: "orrs.w r7, r2, r1" + - + asm_text: "orrs r2, r1" + - + asm_text: "orrs r3, r1" + - + asm_text: "orrs.w r4, r4, r1" + - + asm_text: "orrs.w r5, r1, r5" + - + asm_text: "orr.w r2, r1, r2" + - + asm_text: "orrs r7, r1" + - + asm_text: "orrs r7, r1" + - + asm_text: "orrs.w r8, r1, r8" + - + asm_text: "orrs.w r8, r8, r1" + - + asm_text: "orrs.w r1, r8, r1" + - + asm_text: "orrs.w r0, r0, r8" + - + asm_text: "orrs.w r1, r1, r1, lsl #1" + - + asm_text: "orrs.w r0, r1, r0, lsr #1" + - + asm_text: "it eq" + - + asm_text: "orreq.w r0, r2, r1" + - + asm_text: "it eq" + - + asm_text: "orreq r5, r1" + - + asm_text: "it eq" + - + asm_text: "orreq r5, r1" + - + asm_text: "it eq" + - + asm_text: "orreq.w r2, r2, r1" + - + asm_text: "it eq" + - + asm_text: "orreq.w r3, r1, r3" + - + asm_text: "it eq" + - + asm_text: "orrseq.w r4, r1, r4" + - + asm_text: "it eq" + - + asm_text: "orreq r7, r1" + - + asm_text: "it eq" + - + asm_text: "orreq r7, r1" + - + asm_text: "it eq" + - + asm_text: "orreq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "orreq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "orreq.w r0, r8, r0" + - + asm_text: "it eq" + - + asm_text: "orreq.w r0, r0, r8" + - + asm_text: "it eq" + - + asm_text: "orreq.w r2, r2, r1, lsl #1" + - + asm_text: "it eq" + - + asm_text: "orreq.w r2, r1, r2, lsr #1" + - + asm_text: "bics.w r3, r2, r1" + - + asm_text: "bics r2, r1" + - + asm_text: "bics.w r1, r2, r1" + - + asm_text: "bics.w r2, r2, r1" + - + asm_text: "bics.w r0, r1, r0" + - + asm_text: "bic.w r0, r1, r0" + - + asm_text: "bics r7, r1" + - + asm_text: "bics.w r8, r1, r8" + - + asm_text: "bics.w r8, r8, r1" + - + asm_text: "bics.w r7, r8, r7" + - + asm_text: "bics.w r5, r5, r8" + - + asm_text: "bics.w r3, r3, r1, lsl #1" + - + asm_text: "bics.w r4, r1, r4, lsr #1" + - + asm_text: "it eq" + - + asm_text: "biceq.w r0, r2, r1" + - + asm_text: "it eq" + - + asm_text: "biceq r5, r1" + - + asm_text: "it eq" + - + asm_text: "biceq.w r1, r5, r1" + - + asm_text: "it eq" + - + asm_text: "biceq.w r4, r4, r1" + - + asm_text: "it eq" + - + asm_text: "biceq.w r2, r1, r2" + - + asm_text: "it eq" + - + asm_text: "bicseq.w r5, r1, r5" + - + asm_text: "it eq" + - + asm_text: "biceq r7, r1" + - + asm_text: "it eq" + - + asm_text: "biceq.w r8, r1, r8" + - + asm_text: "it eq" + - + asm_text: "biceq.w r8, r8, r1" + - + asm_text: "it eq" + - + asm_text: "biceq.w r0, r8, r0" + - + asm_text: "it eq" + - + asm_text: "biceq.w r2, r2, r8" + - + asm_text: "it eq" + - + asm_text: "biceq.w r4, r4, r1, lsl #1" + - + asm_text: "it eq" + - + asm_text: "biceq.w r5, r1, r5, lsr #1" diff --git a/tests/MC/ARM/thumb2-pldw.s.yaml b/tests/MC/ARM/thumb2-pldw.s.yaml new file mode 100644 index 0000000000..5604eb4d61 --- /dev/null +++ b/tests/MC/ARM/thumb2-pldw.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xb0, 0xf8, 0x01, 0xf1 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "pldw [r0, #0x101]" diff --git a/tests/MC/ARM/thumb_rewrites.s.yaml b/tests/MC/ARM/thumb_rewrites.s.yaml new file mode 100644 index 0000000000..7b27020061 --- /dev/null +++ b/tests/MC/ARM/thumb_rewrites.s.yaml @@ -0,0 +1,70 @@ +test_cases: + - + input: + bytes: [ 0xc9, 0x1c, 0x03, 0x31, 0x08, 0x30, 0x00, 0x18, 0x40, 0x44, 0x41, 0x44, 0x85, 0x44, 0x6c, 0x44, 0x08, 0xb0, 0xfe, 0xad, 0x08, 0x44, 0x1a, 0x44, 0x00, 0x1a, 0x5b, 0x1f, 0x05, 0x3b, 0x08, 0x3a, 0x84, 0xb0, 0x08, 0x40, 0x08, 0x40, 0x48, 0x40, 0x48, 0x40, 0x88, 0x40, 0xc8, 0x40, 0x08, 0x41, 0x48, 0x41, 0x48, 0x41, 0x88, 0x41, 0xc8, 0x41, 0x08, 0x43, 0x08, 0x43, 0x88, 0x43 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "adds r1, r1, #3" + - + asm_text: "adds r1, #3" + - + asm_text: "adds r0, #8" + - + asm_text: "adds r0, r0, r0" + - + asm_text: "add r0, r8" + - + asm_text: "add r1, r8" + - + asm_text: "add sp, r0" + - + asm_text: "add r4, sp, r4" + - + asm_text: "add sp, #0x20" + - + asm_text: "add r5, sp, #0x3f8" + - + asm_text: "add r0, r1" + - + asm_text: "add r2, r3" + - + asm_text: "subs r0, r0, r0" + - + asm_text: "subs r3, r3, #5" + - + asm_text: "subs r3, #5" + - + asm_text: "subs r2, #8" + - + asm_text: "sub sp, #0x10" + - + asm_text: "ands r0, r1" + - + asm_text: "ands r0, r1" + - + asm_text: "eors r0, r1" + - + asm_text: "eors r0, r1" + - + asm_text: "lsls r0, r1" + - + asm_text: "lsrs r0, r1" + - + asm_text: "asrs r0, r1" + - + asm_text: "adcs r0, r1" + - + asm_text: "adcs r0, r1" + - + asm_text: "sbcs r0, r1" + - + asm_text: "rors r0, r1" + - + asm_text: "orrs r0, r1" + - + asm_text: "orrs r0, r1" + - + asm_text: "bics r0, r1" diff --git a/tests/MC/ARM/thumbv7em.s.yaml b/tests/MC/ARM/thumbv7em.s.yaml new file mode 100644 index 0000000000..e35517f4eb --- /dev/null +++ b/tests/MC/ARM/thumbv7em.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0x80, 0xf3, 0x00, 0x84, 0x80, 0xf3, 0x00, 0x8c, 0x80, 0xf3, 0x01, 0x84, 0x80, 0xf3, 0x01, 0x8c, 0x80, 0xf3, 0x02, 0x84, 0x80, 0xf3, 0x02, 0x8c, 0x80, 0xf3, 0x03, 0x84, 0x80, 0xf3, 0x03, 0x8c ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "msr apsr_g, r0" + - + asm_text: "msr apsr_nzcvqg, r0" + - + asm_text: "msr iapsr_g, r0" + - + asm_text: "msr iapsr_nzcvqg, r0" + - + asm_text: "msr eapsr_g, r0" + - + asm_text: "msr eapsr_nzcvqg, r0" + - + asm_text: "msr xpsr_g, r0" + - + asm_text: "msr xpsr_nzcvqg, r0" diff --git a/tests/MC/ARM/thumbv7m.s.yaml b/tests/MC/ARM/thumbv7m.s.yaml new file mode 100644 index 0000000000..c31e3d2396 --- /dev/null +++ b/tests/MC/ARM/thumbv7m.s.yaml @@ -0,0 +1,20 @@ +test_cases: + - + input: + bytes: [ 0xef, 0xf3, 0x11, 0x80, 0xef, 0xf3, 0x12, 0x80, 0xef, 0xf3, 0x13, 0x80, 0x80, 0xf3, 0x11, 0x88, 0x80, 0xf3, 0x12, 0x88, 0x80, 0xf3, 0x13, 0x88 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "mrs r0, basepri" + - + asm_text: "mrs r0, basepri_max" + - + asm_text: "mrs r0, faultmask" + - + asm_text: "msr basepri, r0" + - + asm_text: "msr basepri_max, r0" + - + asm_text: "msr faultmask, r0" diff --git a/tests/MC/ARM/thumbv8.1m-vmrs-vmsr.s.yaml b/tests/MC/ARM/thumbv8.1m-vmrs-vmsr.s.yaml new file mode 100644 index 0000000000..bc3bb690ad --- /dev/null +++ b/tests/MC/ARM/thumbv8.1m-vmrs-vmsr.s.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0xe2, 0xee, 0x10, 0x0a, 0xf2, 0xee, 0x10, 0xaa, 0xfe, 0xee, 0x10, 0x0a, 0xee, 0xee, 0x10, 0xaa, 0xef, 0xee, 0x10, 0x5a, 0xfe, 0xee, 0x10, 0x3a, 0xff, 0xee, 0x10, 0x0a, 0xfc, 0xee, 0x10, 0x0a, 0xfd, 0xee, 0x10, 0x4a, 0xec, 0xee, 0x10, 0x0a, 0xed, 0xee, 0x10, 0x4a ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmsr fpscr_nzcvqc, r0" + - + asm_text: "vmrs r10, fpscr_nzcvqc" + - + asm_text: "vmrs r0, fpcxtns" + - + asm_text: "vmsr fpcxtns, r10" + - + asm_text: "vmsr fpcxts, r5" + - + asm_text: "vmrs r3, fpcxtns" + - + asm_text: "vmrs r0, fpcxts" + - + asm_text: "vmrs r0, vpr" + - + asm_text: "vmrs r4, p0" + - + asm_text: "vmsr vpr, r0" + - + asm_text: "vmsr p0, r4" diff --git a/tests/MC/ARM/thumbv8.1m.s.yaml b/tests/MC/ARM/thumbv8.1m.s.yaml new file mode 100644 index 0000000000..d3f18fe079 --- /dev/null +++ b/tests/MC/ARM/thumbv8.1m.s.yaml @@ -0,0 +1,338 @@ +test_cases: + - + input: + bytes: [ 0x42, 0xf0, 0x01, 0xe0, 0x4e, 0xf0, 0x01, 0xe0, 0x40, 0xf0, 0x01, 0xe0, 0x41, 0xf0, 0x01, 0xe0, 0x4a, 0xf0, 0x01, 0xe0, 0x4b, 0xf0, 0x01, 0xe0, 0x4c, 0xf0, 0x01, 0xe0, 0x42, 0xf0, 0x01, 0xe0, 0x43, 0xf0, 0x01, 0xe0, 0x45, 0xf0, 0x01, 0xe0, 0x46, 0xf0, 0x01, 0xe0, 0x47, 0xf0, 0x01, 0xe0, 0x48, 0xf0, 0x01, 0xe0, 0x49, 0xf0, 0x01, 0xe0, 0x2f, 0xf0, 0x35, 0xc8, 0x2f, 0xf0, 0x4b, 0xc2, 0x2f, 0xf0, 0x5d, 0xca, 0x2f, 0xf0, 0x77, 0xc2, 0x2f, 0xf0, 0x77, 0xca, 0x2f, 0xf0, 0x83, 0xc2, 0x2f, 0xf0, 0x83, 0xca, 0x2f, 0xf0, 0x0b, 0xc3, 0x2f, 0xf0, 0x59, 0xc8, 0x2f, 0xf0, 0xad, 0xcb, 0x2f, 0xf0, 0xb7, 0xc3, 0x2f, 0xf0, 0xbb, 0xcb, 0x2f, 0xf0, 0x0f, 0xc4, 0x2f, 0xf0, 0x6d, 0xcc, 0x2f, 0xf0, 0x8b, 0xc4, 0x2f, 0xf0, 0x8d, 0xc4, 0x2f, 0xf0, 0xcd, 0xc4, 0x2f, 0xf0, 0x7b, 0xc8, 0x2f, 0xf0, 0xd7, 0xc4, 0x2f, 0xf0, 0x09, 0xcd, 0x2f, 0xf0, 0x83, 0xc8, 0x2f, 0xf0, 0x33, 0xc5, 0x2f, 0xf0, 0x51, 0xcd, 0x2f, 0xf0, 0x9b, 0xc5, 0x2f, 0xf0, 0xa1, 0xcd, 0x2f, 0xf0, 0x29, 0xce, 0x2f, 0xf0, 0x65, 0xce, 0x2f, 0xf0, 0x8d, 0xc6, 0x2f, 0xf0, 0xa9, 0xc8, 0x2f, 0xf0, 0xc1, 0xce, 0x2f, 0xf0, 0xcd, 0xc6, 0x2f, 0xf0, 0xeb, 0xce, 0x2f, 0xf0, 0x1f, 0xc7, 0x2f, 0xf0, 0x2f, 0xc7, 0x2f, 0xf0, 0x37, 0xc7, 0x2f, 0xf0, 0x8b, 0xc7, 0x2f, 0xf0, 0xc9, 0xcf, 0x2f, 0xf0, 0xd3, 0xcf, 0x2f, 0xf0, 0xe1, 0xcf, 0x2f, 0xf0, 0xef, 0xc7, 0x2f, 0xf0, 0xf3, 0xc7, 0x2f, 0xf0, 0xef, 0xc8, 0x2f, 0xf0, 0x11, 0xc1, 0x2f, 0xf0, 0x25, 0xc9, 0x2f, 0xf0, 0x2f, 0xc9, 0x2f, 0xf0, 0x49, 0xc1, 0x2f, 0xf0, 0x73, 0xc1, 0x2f, 0xf0, 0x7d, 0xc9, 0x2f, 0xf0, 0xaf, 0xc9, 0x2f, 0xf0, 0xb3, 0xc9, 0x0f, 0xf0, 0x1d, 0xc2, 0x0f, 0xf0, 0x29, 0xc2, 0x0f, 0xf0, 0x41, 0xc2, 0x0f, 0xf0, 0xdb, 0xca, 0x0f, 0xf0, 0xdf, 0xca, 0x0f, 0xf0, 0x27, 0xc3, 0x0f, 0xf0, 0x31, 0xc3, 0x0f, 0xf0, 0x4f, 0xcb, 0x0f, 0xf0, 0x59, 0xcb, 0x0f, 0xf0, 0x9d, 0xcb, 0x0f, 0xf0, 0xab, 0xcb, 0x0f, 0xf0, 0xb5, 0xc3, 0x0f, 0xf0, 0xc1, 0xcb, 0x0f, 0xf0, 0xc3, 0xcb, 0x0f, 0xf0, 0x01, 0xc8, 0x0f, 0xf0, 0x1d, 0xc4, 0x0f, 0xf0, 0x23, 0xc4, 0x0f, 0xf0, 0x31, 0xc4, 0x0f, 0xf0, 0x47, 0xc4, 0x0f, 0xf0, 0x95, 0xc4, 0x0f, 0xf0, 0xcd, 0xc4, 0x0f, 0xf0, 0x19, 0xc5, 0x0f, 0xf0, 0x1d, 0xc5, 0x0f, 0xf0, 0x1f, 0xcd, 0x0f, 0xf0, 0x3d, 0xc5, 0x0f, 0xf0, 0x43, 0xcd, 0x0f, 0xf0, 0x91, 0xcd, 0x0f, 0xf0, 0x97, 0xc5, 0x0f, 0xf0, 0xdf, 0xc5, 0x0f, 0xf0, 0xe5, 0xcd, 0x0f, 0xf0, 0x99, 0xc0, 0x0f, 0xf0, 0x0d, 0xce, 0x0f, 0xf0, 0x4f, 0xc6, 0x0f, 0xf0, 0x7b, 0xc6, 0x0f, 0xf0, 0x83, 0xc6, 0x0f, 0xf0, 0x8d, 0xce, 0x0f, 0xf0, 0xbd, 0xcf, 0x0f, 0xf0, 0xe5, 0xcf, 0x0f, 0xf0, 0xeb, 0xc7, 0x0f, 0xf0, 0xe5, 0xc8, 0x0f, 0xf0, 0x1d, 0xc0, 0x0f, 0xf0, 0x23, 0xc9, 0x0f, 0xf0, 0x53, 0xc1, 0x0f, 0xf0, 0x79, 0xc1, 0x0f, 0xf0, 0x27, 0xc0, 0x0f, 0xf0, 0x91, 0xc9, 0x0f, 0xf0, 0xaf, 0xc9, 0x0f, 0xf0, 0xc3, 0xc9, 0x0f, 0xf0, 0xe5, 0xc1, 0x4e, 0xf0, 0x55, 0xc2, 0x4e, 0xf0, 0x2b, 0xcc, 0x4e, 0xf0, 0xe1, 0xc9, 0x40, 0xf0, 0x43, 0xc3, 0x40, 0xf0, 0x49, 0xcd, 0x40, 0xf0, 0xe9, 0xcd, 0x40, 0xf0, 0xb7, 0xc6, 0x41, 0xf0, 0x13, 0xc2, 0x41, 0xf0, 0xe3, 0xc7, 0x41, 0xf0, 0x0d, 0xc9, 0x4a, 0xf0, 0xbf, 0xc2, 0x4a, 0xf0, 0xc1, 0xc2, 0x4a, 0xf0, 0x9b, 0xcc, 0x4a, 0xf0, 0xfb, 0xcf, 0x4b, 0xf0, 0xd1, 0xca, 0x4b, 0xf0, 0x3b, 0xcd, 0x4b, 0xf0, 0x0d, 0xcf, 0x4c, 0xf0, 0x67, 0xc8, 0x4c, 0xf0, 0xa9, 0xc5, 0x4c, 0xf0, 0x5d, 0xce, 0x42, 0xf0, 0x55, 0xce, 0x42, 0xf0, 0x7d, 0xc7, 0x42, 0xf0, 0xb5, 0xc1, 0x43, 0xf0, 0xdd, 0xce, 0x43, 0xf0, 0x1b, 0xc7, 0x43, 0xf0, 0xb3, 0xcf, 0x43, 0xf0, 0x65, 0xc1, 0x44, 0xf0, 0x31, 0xcc, 0x44, 0xf0, 0xdb, 0xcc, 0x45, 0xf0, 0xb9, 0xcb, 0x45, 0xf0, 0xa3, 0xc6, 0x46, 0xf0, 0x7f, 0xce, 0x46, 0xf0, 0xd1, 0xc0, 0x46, 0xf0, 0xd3, 0xc8, 0x47, 0xf0, 0xc9, 0xce, 0x47, 0xf0, 0x1d, 0xc7, 0x48, 0xf0, 0x47, 0xc5, 0x49, 0xf0, 0x2d, 0xca, 0x49, 0xf0, 0xe1, 0xc3, 0x49, 0xf0, 0x57, 0xcf, 0x49, 0xf0, 0x6b, 0xc7, 0x52, 0xea, 0x22, 0x9e, 0x57, 0xea, 0x47, 0x9e, 0x5c, 0xea, 0x3c, 0xae, 0x5a, 0xea, 0x3a, 0xbe, 0x59, 0xea, 0x7b, 0x89, 0x5f, 0xea, 0x1f, 0x9e, 0x5f, 0xea, 0x3f, 0xae, 0x5a, 0xea, 0xd7, 0x9e, 0x55, 0xea, 0x2f, 0xae, 0x52, 0xea, 0x42, 0xae, 0x50, 0xea, 0x01, 0x80 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "dls lr, r2" + - + asm_text: "dls lr, lr" + - + asm_text: "dls lr, r0" + - + asm_text: "dls lr, r1" + - + asm_text: "dls lr, r10" + - + asm_text: "dls lr, r11" + - + asm_text: "dls lr, r12" + - + asm_text: "dls lr, r2" + - + asm_text: "dls lr, r3" + - + asm_text: "dls lr, r5" + - + asm_text: "dls lr, r6" + - + asm_text: "dls lr, r7" + - + asm_text: "dls lr, r8" + - + asm_text: "dls lr, r9" + - + asm_text: "le #-0x6a" + - + asm_text: "le #-0x494" + - + asm_text: "le #-0x4ba" + - + asm_text: "le #-0x4ec" + - + asm_text: "le #-0x4ee" + - + asm_text: "le #-0x504" + - + asm_text: "le #-0x506" + - + asm_text: "le #-0x614" + - + asm_text: "le #-0xb2" + - + asm_text: "le #-0x75a" + - + asm_text: "le #-0x76c" + - + asm_text: "le #-0x776" + - + asm_text: "le #-0x81c" + - + asm_text: "le #-0x8da" + - + asm_text: "le #-0x914" + - + asm_text: "le #-0x918" + - + asm_text: "le #-0x998" + - + asm_text: "le #-0xf6" + - + asm_text: "le #-0x9ac" + - + asm_text: "le #-0xa12" + - + asm_text: "le #-0x106" + - + asm_text: "le #-0xa64" + - + asm_text: "le #-0xaa2" + - + asm_text: "le #-0xb34" + - + asm_text: "le #-0xb42" + - + asm_text: "le #-0xc52" + - + asm_text: "le #-0xcca" + - + asm_text: "le #-0xd18" + - + asm_text: "le #-0x152" + - + asm_text: "le #-0xd82" + - + asm_text: "le #-0xd98" + - + asm_text: "le #-0xdd6" + - + asm_text: "le #-0xe3c" + - + asm_text: "le #-0xe5c" + - + asm_text: "le #-0xe6c" + - + asm_text: "le #-0xf14" + - + asm_text: "le #-0xf92" + - + asm_text: "le #-0xfa6" + - + asm_text: "le #-0xfc2" + - + asm_text: "le #-0xfdc" + - + asm_text: "le #-0xfe4" + - + asm_text: "le #-0x1de" + - + asm_text: "le #-0x220" + - + asm_text: "le #-0x24a" + - + asm_text: "le #-0x25e" + - + asm_text: "le #-0x290" + - + asm_text: "le #-0x2e4" + - + asm_text: "le #-0x2fa" + - + asm_text: "le #-0x35e" + - + asm_text: "le #-0x366" + - + asm_text: "le lr, #-0x438" + - + asm_text: "le lr, #-0x450" + - + asm_text: "le lr, #-0x480" + - + asm_text: "le lr, #-0x5b6" + - + asm_text: "le lr, #-0x5be" + - + asm_text: "le lr, #-0x64c" + - + asm_text: "le lr, #-0x660" + - + asm_text: "le lr, #-0x69e" + - + asm_text: "le lr, #-0x6b2" + - + asm_text: "le lr, #-0x73a" + - + asm_text: "le lr, #-0x756" + - + asm_text: "le lr, #-0x768" + - + asm_text: "le lr, #-0x782" + - + asm_text: "le lr, #-0x786" + - + asm_text: "le lr, #-2" + - + asm_text: "le lr, #-0x838" + - + asm_text: "le lr, #-0x844" + - + asm_text: "le lr, #-0x860" + - + asm_text: "le lr, #-0x88c" + - + asm_text: "le lr, #-0x928" + - + asm_text: "le lr, #-0x998" + - + asm_text: "le lr, #-0xa30" + - + asm_text: "le lr, #-0xa38" + - + asm_text: "le lr, #-0xa3e" + - + asm_text: "le lr, #-0xa78" + - + asm_text: "le lr, #-0xa86" + - + asm_text: "le lr, #-0xb22" + - + asm_text: "le lr, #-0xb2c" + - + asm_text: "le lr, #-0xbbc" + - + asm_text: "le lr, #-0xbca" + - + asm_text: "le lr, #-0x130" + - + asm_text: "le lr, #-0xc1a" + - + asm_text: "le lr, #-0xc9c" + - + asm_text: "le lr, #-0xcf4" + - + asm_text: "le lr, #-0xd04" + - + asm_text: "le lr, #-0xd1a" + - + asm_text: "le lr, #-0xf7a" + - + asm_text: "le lr, #-0xfca" + - + asm_text: "le lr, #-0xfd4" + - + asm_text: "le lr, #-0x1ca" + - + asm_text: "le lr, #-0x38" + - + asm_text: "le lr, #-0x246" + - + asm_text: "le lr, #-0x2a4" + - + asm_text: "le lr, #-0x2f0" + - + asm_text: "le lr, #-0x4c" + - + asm_text: "le lr, #-0x322" + - + asm_text: "le lr, #-0x35e" + - + asm_text: "le lr, #-0x386" + - + asm_text: "le lr, #-0x3c8" + - + asm_text: "wls lr, lr, #0x4a8" + - + asm_text: "wls lr, lr, #0x856" + - + asm_text: "wls lr, lr, #0x3c2" + - + asm_text: "wls lr, r0, #0x684" + - + asm_text: "wls lr, r0, #0xa92" + - + asm_text: "wls lr, r0, #0xbd2" + - + asm_text: "wls lr, r0, #0xd6c" + - + asm_text: "wls lr, r1, #0x424" + - + asm_text: "wls lr, r1, #0xfc4" + - + asm_text: "wls lr, r1, #0x21a" + - + asm_text: "wls lr, r10, #0x57c" + - + asm_text: "wls lr, r10, #0x580" + - + asm_text: "wls lr, r10, #0x936" + - + asm_text: "wls lr, r10, #0xff6" + - + asm_text: "wls lr, r11, #0x5a2" + - + asm_text: "wls lr, r11, #0xa76" + - + asm_text: "wls lr, r11, #0xe1a" + - + asm_text: "wls lr, r12, #0xce" + - + asm_text: "wls lr, r12, #0xb50" + - + asm_text: "wls lr, r12, #0xcba" + - + asm_text: "wls lr, r2, #0xcaa" + - + asm_text: "wls lr, r2, #0xef8" + - + asm_text: "wls lr, r2, #0x368" + - + asm_text: "wls lr, r3, #0xdba" + - + asm_text: "wls lr, r3, #0xe34" + - + asm_text: "wls lr, r3, #0xf66" + - + asm_text: "wls lr, r3, #0x2c8" + - + asm_text: "wls lr, r4, #0x862" + - + asm_text: "wls lr, r4, #0x9b6" + - + asm_text: "wls lr, r5, #0x772" + - + asm_text: "wls lr, r5, #0xd44" + - + asm_text: "wls lr, r6, #0xcfe" + - + asm_text: "wls lr, r6, #0x1a0" + - + asm_text: "wls lr, r6, #0x1a6" + - + asm_text: "wls lr, r7, #0xd92" + - + asm_text: "wls lr, r7, #0xe38" + - + asm_text: "wls lr, r8, #0xa8c" + - + asm_text: "wls lr, r9, #0x45a" + - + asm_text: "wls lr, r9, #0x7c0" + - + asm_text: "wls lr, r9, #0xeae" + - + asm_text: "wls lr, r9, #0xed4" + - + asm_text: "cinc lr, r2, lo" + - + asm_text: "cinc lr, r7, pl" + - + asm_text: "cinv lr, r12, hs" + - + asm_text: "cneg lr, r10, hs" + - + asm_text: "csel r9, r9, r11, vc" + - + asm_text: "cset lr, eq" + - + asm_text: "csetm lr, hs" + - + asm_text: "csinc lr, r10, r7, le" + - + asm_text: "csinv lr, r5, zr, hs" + - + asm_text: "cinv lr, r2, pl" + - + asm_text: "csel r0, r0, r1, eq" diff --git a/tests/MC/ARM/thumbv8m.s.yaml b/tests/MC/ARM/thumbv8m.s.yaml new file mode 100644 index 0000000000..bbec48ec2c --- /dev/null +++ b/tests/MC/ARM/thumbv8m.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0xbf, 0xf3, 0x6f, 0x8f, 0x92, 0xfb, 0xf3, 0xf1, 0xb2, 0xfb, 0xf3, 0xf1, 0xbf, 0xf3, 0x2f, 0x8f, 0x52, 0xe8, 0x01, 0x1f, 0xd2, 0xe8, 0x4f, 0x1f, 0xd2, 0xe8, 0x5f, 0x1f, 0x43, 0xe8, 0x01, 0x21, 0xc3, 0xe8, 0x41, 0x2f, 0xc3, 0xe8, 0x51, 0x2f, 0x4f, 0xf6, 0xff, 0x71, 0xcf, 0xf6, 0xff, 0x71, 0xd2, 0xe8, 0xaf, 0x1f, 0xd2, 0xe8, 0x8f, 0x1f, 0xd2, 0xe8, 0x9f, 0x1f, 0xc3, 0xe8, 0xaf, 0x1f, 0xc3, 0xe8, 0x8f, 0x1f, 0xc3, 0xe8, 0x9f, 0x1f, 0xd2, 0xe8, 0xef, 0x1f, 0xd2, 0xe8, 0xcf, 0x1f, 0xd2, 0xe8, 0xdf, 0x1f, 0xc3, 0xe8, 0xe1, 0x2f, 0xc3, 0xe8, 0xc1, 0x2f, 0xc3, 0xe8, 0xd1, 0x2f, 0x7f, 0xe9, 0x7f, 0xe9, 0x04, 0x47, 0x74, 0x47, 0x84, 0x47, 0x41, 0xe8, 0x00, 0xf0, 0x4d, 0xe8, 0x00, 0xf0, 0x41, 0xe8, 0x80, 0xf0, 0x41, 0xe8, 0x40, 0xf0, 0x41, 0xe8, 0xc0, 0xf0, 0xef, 0xf3, 0x88, 0x81, 0x82, 0xf3, 0x89, 0x88, 0xef, 0xf3, 0x90, 0x83, 0x84, 0xf3, 0x94, 0x88, 0xef, 0xf3, 0x98, 0x85, 0xef, 0xf3, 0x0a, 0x86, 0xef, 0xf3, 0x0b, 0x87, 0x88, 0xf3, 0x0a, 0x88, 0x89, 0xf3, 0x0b, 0x88, 0xef, 0xf3, 0x8a, 0x8a, 0x8b, 0xf3, 0x8b, 0x88, 0xef, 0xf3, 0x92, 0x88, 0x88, 0xf3, 0x92, 0x80 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "isb sy" + - + asm_text: "sdiv r1, r2, r3" + - + asm_text: "udiv r1, r2, r3" + - + asm_text: "clrex" + - + asm_text: "ldrex r1, [r2, #4]" + - + asm_text: "ldrexb r1, [r2]" + - + asm_text: "ldrexh r1, [r2]" + - + asm_text: "strex r1, r2, [r3, #4]" + - + asm_text: "strexb r1, r2, [r3]" + - + asm_text: "strexh r1, r2, [r3]" + - + asm_text: "movw r1, #0xffff" + - + asm_text: "movt r1, #0xffff" + - + asm_text: "lda r1, [r2]" + - + asm_text: "ldab r1, [r2]" + - + asm_text: "ldah r1, [r2]" + - + asm_text: "stl r1, [r3]" + - + asm_text: "stlb r1, [r3]" + - + asm_text: "stlh r1, [r3]" + - + asm_text: "ldaex r1, [r2]" + - + asm_text: "ldaexb r1, [r2]" + - + asm_text: "ldaexh r1, [r2]" + - + asm_text: "stlex r1, r2, [r3]" + - + asm_text: "stlexb r1, r2, [r3]" + - + asm_text: "stlexh r1, r2, [r3]" + - + asm_text: "sg" + - + asm_text: "bxns r0" + - + asm_text: "bxns lr" + - + asm_text: "blxns r0" + - + asm_text: "tt r0, r1" + - + asm_text: "tt r0, sp" + - + asm_text: "tta r0, r1" + - + asm_text: "ttt r0, r1" + - + asm_text: "ttat r0, r1" + - + asm_text: "mrs r1, msp_ns" + - + asm_text: "msr psp_ns, r2" + - + asm_text: "mrs r3, primask_ns" + - + asm_text: "msr control_ns, r4" + - + asm_text: "mrs r5, sp_ns" + - + asm_text: "mrs r6, msplim" + - + asm_text: "mrs r7, psplim" + - + asm_text: "msr msplim, r8" + - + asm_text: "msr psplim, r9" + - + asm_text: "mrs r10, msplim_ns" + - + asm_text: "msr psplim_ns, r11" + - + asm_text: "mrs r8, 0x92" + - + asm_text: "msr 0x92, r8" diff --git a/tests/MC/ARM/udf-arm.s.yaml b/tests/MC/ARM/udf-arm.s.yaml new file mode 100644 index 0000000000..2a4769d35e --- /dev/null +++ b/tests/MC/ARM/udf-arm.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xf0, 0x00, 0xf0, 0xe7 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "udf #0" diff --git a/tests/MC/ARM/udf-thumb-2.s.yaml b/tests/MC/ARM/udf-thumb-2.s.yaml new file mode 100644 index 0000000000..1ca8f42dde --- /dev/null +++ b/tests/MC/ARM/udf-thumb-2.s.yaml @@ -0,0 +1,12 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xde, 0xf0, 0xf7, 0x00, 0xa0 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "udf #0" + - + asm_text: "udf.w #0" diff --git a/tests/MC/ARM/udf-thumb.s.yaml b/tests/MC/ARM/udf-thumb.s.yaml new file mode 100644 index 0000000000..49b994366a --- /dev/null +++ b/tests/MC/ARM/udf-thumb.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xde ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "udf #0" diff --git a/tests/MC/ARM/vfp4-thumb.s.yaml b/tests/MC/ARM/vfp4-thumb.s.yaml new file mode 100644 index 0000000000..498c32b4ce --- /dev/null +++ b/tests/MC/ARM/vfp4-thumb.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0xa2, 0xee, 0x00, 0x1a, 0x42, 0xef, 0xb1, 0x0c, 0x08, 0xef, 0x50, 0x4c, 0x92, 0xee, 0x40, 0x1a, 0xa2, 0xee, 0x40, 0x1a, 0x62, 0xef, 0xb1, 0x0c, 0x28, 0xef, 0x50, 0x4c, 0x92, 0xee, 0x00, 0x1a ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vfma.f32 s2, s4, s0" + - + asm_text: "vfma.f32 d16, d18, d17" + - + asm_text: "vfma.f32 q2, q4, q0" + - + asm_text: "vfnma.f32 s2, s4, s0" + - + asm_text: "vfms.f32 s2, s4, s0" + - + asm_text: "vfms.f32 d16, d18, d17" + - + asm_text: "vfms.f32 q2, q4, q0" + - + asm_text: "vfnms.f32 s2, s4, s0" diff --git a/tests/MC/ARM/vfp4.s.yaml b/tests/MC/ARM/vfp4.s.yaml new file mode 100644 index 0000000000..82700c7d6b --- /dev/null +++ b/tests/MC/ARM/vfp4.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x1a, 0xa2, 0xee, 0xb1, 0x0c, 0x42, 0xf2, 0x50, 0x4c, 0x08, 0xf2, 0x40, 0x1a, 0x92, 0xee, 0x40, 0x1a, 0xa2, 0xee, 0xb1, 0x0c, 0x62, 0xf2, 0x50, 0x4c, 0x28, 0xf2, 0x00, 0x1a, 0x92, 0xee ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vfma.f32 s2, s4, s0" + - + asm_text: "vfma.f32 d16, d18, d17" + - + asm_text: "vfma.f32 q2, q4, q0" + - + asm_text: "vfnma.f32 s2, s4, s0" + - + asm_text: "vfms.f32 s2, s4, s0" + - + asm_text: "vfms.f32 d16, d18, d17" + - + asm_text: "vfms.f32 q2, q4, q0" + - + asm_text: "vfnms.f32 s2, s4, s0" diff --git a/tests/MC/ARM/vmov-vmvn-replicate.s.yaml b/tests/MC/ARM/vmov-vmvn-replicate.s.yaml new file mode 100644 index 0000000000..3a5b627a25 --- /dev/null +++ b/tests/MC/ARM/vmov-vmvn-replicate.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x3f, 0x2e, 0x87, 0xf3, 0x7f, 0x4e, 0x87, 0xf3, 0x1f, 0x2e, 0x87, 0xf3, 0x5f, 0x4e, 0x87, 0xf3, 0x1b, 0x2e, 0x82, 0xf3, 0x5b, 0x4e, 0x82, 0xf3, 0x1b, 0x2e, 0x82, 0xf3, 0x5b, 0x4e, 0x82, 0xf3, 0x5b, 0x4e, 0x82, 0xf3, 0x5b, 0x4e, 0x82, 0xf3, 0x3a, 0x2e, 0x82, 0xf3, 0x7a, 0x4e, 0x82, 0xf3, 0x15, 0x28, 0x82, 0xf3, 0x55, 0x48, 0x82, 0xf3, 0x15, 0x28, 0x82, 0xf3, 0x55, 0x48, 0x82, 0xf3, 0x15, 0x2a, 0x82, 0xf3, 0x55, 0x4a, 0x82, 0xf3, 0x15, 0x2a, 0x82, 0xf3, 0x55, 0x4a, 0x82, 0xf3, 0x15, 0x20, 0x82, 0xf3, 0x55, 0x40, 0x82, 0xf3, 0x15, 0x2d, 0x82, 0xf3, 0x55, 0x4d, 0x82, 0xf3, 0x10, 0x2e, 0x80, 0xf2, 0x50, 0x4e, 0x80, 0xf2, 0x10, 0x2e, 0x80, 0xf2, 0x50, 0x4e, 0x80, 0xf2, 0x14, 0x2e, 0x85, 0xf2, 0x54, 0x4e, 0x85, 0xf2, 0x14, 0x2e, 0x85, 0xf2, 0x54, 0x4e, 0x85, 0xf2, 0x14, 0x2e, 0x85, 0xf2, 0x54, 0x4e, 0x85, 0xf2, 0x35, 0x28, 0x82, 0xf3, 0x75, 0x48, 0x82, 0xf3, 0x35, 0x28, 0x82, 0xf3, 0x75, 0x48, 0x82, 0xf3, 0x35, 0x2a, 0x82, 0xf3, 0x75, 0x4a, 0x82, 0xf3, 0x35, 0x2a, 0x82, 0xf3, 0x75, 0x4a, 0x82, 0xf3, 0x35, 0x20, 0x82, 0xf3, 0x75, 0x40, 0x82, 0xf3, 0x35, 0x2d, 0x82, 0xf3, 0x75, 0x4d, 0x82, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vmov.i64 d2, #0xffffffffffffffff" + - + asm_text: "vmov.i64 q2, #0xffffffffffffffff" + - + asm_text: "vmov.i8 d2, #0xff" + - + asm_text: "vmov.i8 q2, #0xff" + - + asm_text: "vmov.i8 d2, #0xab" + - + asm_text: "vmov.i8 q2, #0xab" + - + asm_text: "vmov.i8 d2, #0xab" + - + asm_text: "vmov.i8 q2, #0xab" + - + asm_text: "vmov.i8 q2, #0xab" + - + asm_text: "vmov.i8 q2, #0xab" + - + asm_text: "vmov.i64 d2, #0xff00ff00ff00ff00" + - + asm_text: "vmov.i64 q2, #0xff00ff00ff00ff00" + - + asm_text: "vmov.i16 d2, #0xa5" + - + asm_text: "vmov.i16 q2, #0xa5" + - + asm_text: "vmov.i16 d2, #0xa5" + - + asm_text: "vmov.i16 q2, #0xa5" + - + asm_text: "vmov.i16 d2, #0xa500" + - + asm_text: "vmov.i16 q2, #0xa500" + - + asm_text: "vmov.i16 d2, #0xa500" + - + asm_text: "vmov.i16 q2, #0xa500" + - + asm_text: "vmov.i32 d2, #0xa5" + - + asm_text: "vmov.i32 q2, #0xa5" + - + asm_text: "vmov.i32 d2, #0xa5ffff" + - + asm_text: "vmov.i32 q2, #0xa5ffff" + - + asm_text: "vmov.i8 d2, #0x0" + - + asm_text: "vmov.i8 q2, #0x0" + - + asm_text: "vmov.i8 d2, #0x0" + - + asm_text: "vmov.i8 q2, #0x0" + - + asm_text: "vmov.i8 d2, #0x54" + - + asm_text: "vmov.i8 q2, #0x54" + - + asm_text: "vmov.i8 d2, #0x54" + - + asm_text: "vmov.i8 q2, #0x54" + - + asm_text: "vmov.i8 d2, #0x54" + - + asm_text: "vmov.i8 q2, #0x54" + - + asm_text: "vmvn.i16 d2, #0xa5" + - + asm_text: "vmvn.i16 q2, #0xa5" + - + asm_text: "vmvn.i16 d2, #0xa5" + - + asm_text: "vmvn.i16 q2, #0xa5" + - + asm_text: "vmvn.i16 d2, #0xa500" + - + asm_text: "vmvn.i16 q2, #0xa500" + - + asm_text: "vmvn.i16 d2, #0xa500" + - + asm_text: "vmvn.i16 q2, #0xa500" + - + asm_text: "vmvn.i32 d2, #0xa5" + - + asm_text: "vmvn.i32 q2, #0xa5" + - + asm_text: "vmvn.i32 d2, #0xa5ffff" + - + asm_text: "vmvn.i32 q2, #0xa5ffff" diff --git a/tests/MC/ARM/vmovhr.s.yaml b/tests/MC/ARM/vmovhr.s.yaml new file mode 100644 index 0000000000..d9997f6503 --- /dev/null +++ b/tests/MC/ARM/vmovhr.s.yaml @@ -0,0 +1,16 @@ +test_cases: + - + input: + bytes: [ 0x16, 0xee, 0x90, 0x09, 0x0a, 0xee, 0x90, 0x19, 0x01, 0xee, 0x10, 0xd9, 0x12, 0xee, 0x90, 0xd9 ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vmov.f16 r0, s13" + - + asm_text: "vmov.f16 s21, r1" + - + asm_text: "vmov.f16 s2, sp" + - + asm_text: "vmov.f16 sp, s5" diff --git a/tests/MC/ARM/vpush-vpop-thumb.s.yaml b/tests/MC/ARM/vpush-vpop-thumb.s.yaml new file mode 100644 index 0000000000..3aede96406 --- /dev/null +++ b/tests/MC/ARM/vpush-vpop-thumb.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0x2d, 0xed, 0x0a, 0x8b, 0x2d, 0xed, 0x05, 0x4a, 0xbd, 0xec, 0x0a, 0x8b, 0xbd, 0xec, 0x05, 0x4a, 0x2d, 0xed, 0x0a, 0x8b, 0x2d, 0xed, 0x05, 0x4a, 0xbd, 0xec, 0x0a, 0x8b, 0xbd, 0xec, 0x05, 0x4a ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vpush {d8, d9, d10, d11, d12}" + - + asm_text: "vpush {s8, s9, s10, s11, s12}" + - + asm_text: "vpop {d8, d9, d10, d11, d12}" + - + asm_text: "vpop {s8, s9, s10, s11, s12}" + - + asm_text: "vpush {d8, d9, d10, d11, d12}" + - + asm_text: "vpush {s8, s9, s10, s11, s12}" + - + asm_text: "vpop {d8, d9, d10, d11, d12}" + - + asm_text: "vpop {s8, s9, s10, s11, s12}" diff --git a/tests/MC/ARM/vpush-vpop.s.yaml b/tests/MC/ARM/vpush-vpop.s.yaml new file mode 100644 index 0000000000..4a6edad022 --- /dev/null +++ b/tests/MC/ARM/vpush-vpop.s.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0x0a, 0x8b, 0x2d, 0xed, 0x05, 0x4a, 0x2d, 0xed, 0x0a, 0x8b, 0xbd, 0xec, 0x05, 0x4a, 0xbd, 0xec, 0x0a, 0x8b, 0x2d, 0xed, 0x05, 0x4a, 0x2d, 0xed, 0x0a, 0x8b, 0xbd, 0xec, 0x05, 0x4a, 0xbd, 0xec ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ] + expected: + insns: + - + asm_text: "vpush {d8, d9, d10, d11, d12}" + - + asm_text: "vpush {s8, s9, s10, s11, s12}" + - + asm_text: "vpop {d8, d9, d10, d11, d12}" + - + asm_text: "vpop {s8, s9, s10, s11, s12}" + - + asm_text: "vpush {d8, d9, d10, d11, d12}" + - + asm_text: "vpush {s8, s9, s10, s11, s12}" + - + asm_text: "vpop {d8, d9, d10, d11, d12}" + - + asm_text: "vpop {s8, s9, s10, s11, s12}" diff --git a/tests/MC/ARM/vscclrm-asm.s.yaml b/tests/MC/ARM/vscclrm-asm.s.yaml new file mode 100644 index 0000000000..b4163355af --- /dev/null +++ b/tests/MC/ARM/vscclrm-asm.s.yaml @@ -0,0 +1,26 @@ +test_cases: + - + input: + bytes: [ 0x9f, 0xec, 0x04, 0x0a, 0xdf, 0xec, 0x06, 0x1a, 0x9f, 0xec, 0x0c, 0x9a, 0xdf, 0xec, 0x01, 0xfa, 0x9f, 0xec, 0x04, 0x0b, 0x9f, 0xec, 0x08, 0x0b, 0x9f, 0xec, 0x06, 0x5b, 0x88, 0xbf, 0xdf, 0xec, 0x1d, 0x1a ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vscclrm {s0, s1, s2, s3, vpr}" + - + asm_text: "vscclrm {s3, s4, s5, s6, s7, s8, vpr}" + - + asm_text: "vscclrm {s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, vpr}" + - + asm_text: "vscclrm {s31, vpr}" + - + asm_text: "vscclrm {d0, d1, vpr}" + - + asm_text: "vscclrm {d0, d1, d2, d3, vpr}" + - + asm_text: "vscclrm {d5, d6, d7, vpr}" + - + asm_text: "it hi" + - + asm_text: "vscclrmhi {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}" diff --git a/tests/MC/ARM/vstrldr_sys.s.yaml b/tests/MC/ARM/vstrldr_sys.s.yaml new file mode 100644 index 0000000000..9d0aff5d2b --- /dev/null +++ b/tests/MC/ARM/vstrldr_sys.s.yaml @@ -0,0 +1,102 @@ +test_cases: + - + input: + bytes: [ 0x80, 0xed, 0x80, 0x2f, 0x09, 0xed, 0x86, 0x4f, 0x29, 0xed, 0x86, 0x4f, 0x29, 0xec, 0x86, 0x4f, 0x88, 0xbf, 0x80, 0xed, 0x80, 0x2f, 0x90, 0xed, 0x80, 0x2f, 0x19, 0xed, 0x86, 0x4f, 0x39, 0xed, 0x86, 0x4f, 0x39, 0xec, 0x86, 0x4f, 0x3d, 0xec, 0x8d, 0x4f, 0x88, 0xbf, 0x90, 0xed, 0x80, 0x2f, 0xcc, 0xed, 0xff, 0xef, 0xec, 0xed, 0xff, 0xef, 0xec, 0xec, 0xff, 0xef, 0x6d, 0xec, 0x86, 0xef, 0xdc, 0xed, 0xff, 0xef, 0xfc, 0xed, 0xff, 0xef, 0xfc, 0xec, 0xff, 0xef, 0x7d, 0xec, 0x86, 0xef, 0xc0, 0xed, 0x80, 0xcf, 0x49, 0xed, 0x86, 0xcf, 0xc6, 0xed, 0xfd, 0xcf, 0x4e, 0xed, 0xff, 0xcf, 0xcc, 0xed, 0xff, 0xcf, 0x6d, 0xec, 0x86, 0xcf, 0xd0, 0xed, 0x80, 0xcf, 0x59, 0xed, 0x86, 0xcf, 0xd6, 0xed, 0xfd, 0xcf, 0x5e, 0xed, 0xff, 0xcf, 0xdc, 0xed, 0xff, 0xcf, 0x7d, 0xec, 0x86, 0xcf, 0xc6, 0xed, 0xfd, 0x8f, 0x4e, 0xed, 0xff, 0xaf, 0xe6, 0xed, 0xfd, 0x8f, 0x6e, 0xed, 0xff, 0xaf, 0xe6, 0xec, 0xfd, 0x8f, 0x6e, 0xec, 0xff, 0xaf, 0x6d, 0xec, 0x86, 0xaf, 0xd6, 0xed, 0xfd, 0x8f, 0x5e, 0xed, 0xff, 0xaf, 0xf6, 0xed, 0xfd, 0x8f, 0x7e, 0xed, 0xff, 0xaf, 0xf6, 0xec, 0xfd, 0x8f, 0x7e, 0xec, 0xff, 0xaf, 0x7d, 0xec, 0x86, 0xaf ] + arch: "CS_ARCH_ARM" + options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ] + expected: + insns: + - + asm_text: "vstr fpscr, [r0]" + - + asm_text: "vstr fpscr_nzcvqc, [r9, #-0x18]" + - + asm_text: "vstr fpscr_nzcvqc, [r9, #-0x18]!" + - + asm_text: "vstr fpscr_nzcvqc, [r9], #-0x18" + - + asm_text: "it hi" + - + asm_text: "vstrhi fpscr, [r0]" + - + asm_text: "vldr fpscr, [r0]" + - + asm_text: "vldr fpscr_nzcvqc, [r9, #-0x18]" + - + asm_text: "vldr fpscr_nzcvqc, [r9, #-0x18]!" + - + asm_text: "vldr fpscr_nzcvqc, [r9], #-0x18" + - + asm_text: "vldr fpscr_nzcvqc, [sp], #-0x34" + - + asm_text: "it hi" + - + asm_text: "vldrhi fpscr, [r0]" + - + asm_text: "vstr fpcxts, [r12, #0x1fc]" + - + asm_text: "vstr fpcxts, [r12, #0x1fc]!" + - + asm_text: "vstr fpcxts, [r12], #0x1fc" + - + asm_text: "vstr fpcxts, [sp], #-0x18" + - + asm_text: "vldr fpcxts, [r12, #0x1fc]" + - + asm_text: "vldr fpcxts, [r12, #0x1fc]!" + - + asm_text: "vldr fpcxts, [r12], #0x1fc" + - + asm_text: "vldr fpcxts, [sp], #-0x18" + - + asm_text: "vstr fpcxtns, [r0]" + - + asm_text: "vstr fpcxtns, [r9, #-0x18]" + - + asm_text: "vstr fpcxtns, [r6, #0x1f4]" + - + asm_text: "vstr fpcxtns, [lr, #-0x1fc]" + - + asm_text: "vstr fpcxtns, [r12, #0x1fc]" + - + asm_text: "vstr fpcxtns, [sp], #-0x18" + - + asm_text: "vldr fpcxtns, [r0]" + - + asm_text: "vldr fpcxtns, [r9, #-0x18]" + - + asm_text: "vldr fpcxtns, [r6, #0x1f4]" + - + asm_text: "vldr fpcxtns, [lr, #-0x1fc]" + - + asm_text: "vldr fpcxtns, [r12, #0x1fc]" + - + asm_text: "vldr fpcxtns, [sp], #-0x18" + - + asm_text: "vstr vpr, [r6, #0x1f4]" + - + asm_text: "vstr p0, [lr, #-0x1fc]" + - + asm_text: "vstr vpr, [r6, #0x1f4]!" + - + asm_text: "vstr p0, [lr, #-0x1fc]!" + - + asm_text: "vstr vpr, [r6], #0x1f4" + - + asm_text: "vstr p0, [lr], #-0x1fc" + - + asm_text: "vstr p0, [sp], #-0x18" + - + asm_text: "vldr vpr, [r6, #0x1f4]" + - + asm_text: "vldr p0, [lr, #-0x1fc]" + - + asm_text: "vldr vpr, [r6, #0x1f4]!" + - + asm_text: "vldr p0, [lr, #-0x1fc]!" + - + asm_text: "vldr vpr, [r6], #0x1f4" + - + asm_text: "vldr p0, [lr], #-0x1fc" + - + asm_text: "vldr p0, [sp], #-0x18" diff --git a/tests/MC/Alpha/insn-alpha-be.s.yaml b/tests/MC/Alpha/insn-alpha-be.s.yaml new file mode 100644 index 0000000000..96fb54010e --- /dev/null +++ b/tests/MC/Alpha/insn-alpha-be.s.yaml @@ -0,0 +1,1783 @@ +test_cases: + - + input: + bytes: [ 0x40, 0x22, 0x00, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addl $1,$2,$3" + - + input: + bytes: [ 0x40, 0x3b, 0xd0, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addl $1,0xde,$3" + - + input: + bytes: [ 0x40, 0x22, 0x04, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addq $1,$2,$3" + - + input: + bytes: [ 0x40, 0x3b, 0xd4, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addq $1,0xde,$3" + - + input: + bytes: [ 0x58, 0x22, 0xb0, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adds/su $f1,$f10,$f11" + - + input: + bytes: [ 0x58, 0x22, 0xb4, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addt/su $f1,$f10,$f11" + - + input: + bytes: [ 0x44, 0x22, 0x00, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "and $1,$2,$3" + - + input: + bytes: [ 0x44, 0x3b, 0xd0, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "and $1,0xde,$3" + - + input: + bytes: [ 0xe4, 0x20, 0x3f, 0xfc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "beq $1,0xfffffffffffffff4" + - + input: + bytes: [ 0xf8, 0x20, 0x3f, 0xfc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bge $1,0xfffffffffffffff4" + - + input: + bytes: [ 0xfc, 0x20, 0x3f, 0xfc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bgt $1,0xfffffffffffffff4" + - + input: + bytes: [ 0x44, 0x22, 0x01, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bic $1,$2,$3" + - + input: + bytes: [ 0x44, 0x3b, 0xd1, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bic $1,0xde,$3" + - + input: + bytes: [ 0x44, 0x22, 0x04, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bis $1,$2,$3" + - + input: + bytes: [ 0x44, 0x3b, 0xd4, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bis $1,0xde,$3" + - + input: + bytes: [ 0xe0, 0x20, 0x3f, 0xfc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "blbc $1,0xfffffffffffffff4" + - + input: + bytes: [ 0xf0, 0x20, 0x3f, 0xfc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "blbs $1,0xfffffffffffffff4" + - + input: + bytes: [ 0xec, 0x20, 0x3f, 0xfc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ble $1,0xfffffffffffffff4" + - + input: + bytes: [ 0xe8, 0x20, 0x3f, 0xfc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "blt $1,0xfffffffffffffff4" + - + input: + bytes: [ 0xf4, 0x20, 0x3f, 0xfc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bne $1,0xfffffffffffffff4" + - + input: + bytes: [ 0xc3, 0xe0, 0x3f, 0xfc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "br $31,0xfffffffffffffff4" + - + input: + bytes: [ 0xd3, 0x40, 0x3f, 0xfc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bsr $26,$0xfffffffffffffff4 ..ng" + - + input: + bytes: [ 0x44, 0x22, 0x04, 0x83 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmoveq $1,$2,$3" + - + input: + bytes: [ 0x44, 0x22, 0x08, 0xc3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmovge $1,$2,$3" + - + input: + bytes: [ 0x44, 0x22, 0x0c, 0xc3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmovgt $1,$2,$3" + - + input: + bytes: [ 0x44, 0x22, 0x02, 0xc3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmovlbc $1,$2,$3" + - + input: + bytes: [ 0x44, 0x22, 0x02, 0x83 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmovlbs $1,$2,$3" + - + input: + bytes: [ 0x44, 0x22, 0x0c, 0x83 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmovle $1,$2,$3" + - + input: + bytes: [ 0x44, 0x22, 0x08, 0x83 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmovlt $1,$2,$3" + - + input: + bytes: [ 0x44, 0x22, 0x04, 0xc3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmovne $1,$2,$3" + - + input: + bytes: [ 0x40, 0x22, 0x01, 0xe3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpbge $1,$2,$3" + - + input: + bytes: [ 0x40, 0x3b, 0xd1, 0xe3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpbge $1,0xde,$3" + - + input: + bytes: [ 0x40, 0x22, 0x05, 0xa3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpeq $1,$2,$3" + - + input: + bytes: [ 0x40, 0x3b, 0xd5, 0xa3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpeq $1,0xde,$3" + - + input: + bytes: [ 0x40, 0x22, 0x0d, 0xa3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmple $1,$2,$3" + - + input: + bytes: [ 0x40, 0x3b, 0xdd, 0xa3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmple $1,0xde,$3" + - + input: + bytes: [ 0x40, 0x22, 0x09, 0xa3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmplt $1,$2,$3" + - + input: + bytes: [ 0x40, 0x3b, 0xd9, 0xa3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmplt $1,0xde,$3" + - + input: + bytes: [ 0x58, 0x22, 0xb4, 0xa3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpteq/su $f1,$f10,$f11" + - + input: + bytes: [ 0x58, 0x22, 0xb4, 0xe3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmptle/su $f1,$f10,$f11" + - + input: + bytes: [ 0x58, 0x22, 0xb4, 0xc3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmptlt/su $f1,$f10,$f11" + - + input: + bytes: [ 0x58, 0x22, 0xb4, 0x83 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmptun/su $f1,$f10,$f11" + - + input: + bytes: [ 0x40, 0x22, 0x07, 0xa3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpule $1,$2,$3" + - + input: + bytes: [ 0x40, 0x3b, 0xd7, 0xa3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpule $1,0xde,$3" + - + input: + bytes: [ 0x40, 0x22, 0x03, 0xa3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpult $1,$2,$3" + - + input: + bytes: [ 0x40, 0x3b, 0xd3, 0xa3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpult $1,0xde,$3" + - + input: + bytes: [ 0x5c, 0x22, 0x04, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpyse $f1,$f10,$f11" + - + input: + bytes: [ 0x5c, 0x22, 0x04, 0x23 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpysn $f1,$f10,$f11" + - + input: + bytes: [ 0x5c, 0x22, 0x04, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpys $f1,$f10,$f11" + - + input: + bytes: [ 0x73, 0xe1, 0x06, 0x42 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ctlz $1,$2" + - + input: + bytes: [ 0x73, 0xe1, 0x06, 0x02 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ctpop $1,$2" + - + input: + bytes: [ 0x73, 0xe1, 0x06, 0x62 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cttz $1,$2" + - + input: + bytes: [ 0x5b, 0xe1, 0xf7, 0x82 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvtqs/sui $f1,$f10" + - + input: + bytes: [ 0x5b, 0xe1, 0xf7, 0xc2 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvtqt/sui $f1,$f10" + - + input: + bytes: [ 0x5b, 0xe1, 0xd5, 0x82 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvtst/s $f1,$f10" + - + input: + bytes: [ 0x5b, 0xe1, 0xa5, 0xe2 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvttq/svc $f1,$f10" + - + input: + bytes: [ 0x5b, 0xe1, 0xf5, 0x82 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvtts/sui $f1,$f10" + - + input: + bytes: [ 0x58, 0x22, 0xb0, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "divs/su $f1,$f10,$f11" + - + input: + bytes: [ 0x58, 0x22, 0xb4, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "divt/su $f1,$f10,$f11" + - + input: + bytes: [ 0x63, 0xe1, 0xe8, 0x00 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecb ($1)" + - + input: + bytes: [ 0x44, 0x22, 0x09, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "eqv $1,$2,$3" + - + input: + bytes: [ 0x44, 0x3b, 0xd9, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "eqv $1,0xde,$3" + - + input: + bytes: [ 0x60, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "excb" + - + input: + bytes: [ 0x48, 0x22, 0x00, 0xc3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extbl $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xd0, 0xc3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extbl $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x22, 0x0d, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extlh $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xdd, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extlh $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x22, 0x04, 0xc3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extll $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xd4, 0xc3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extll $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x22, 0x0f, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extqh $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xdf, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extqh $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x22, 0x06, 0xc3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extql $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xd6, 0xc3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extql $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x22, 0x0b, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extwh $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xdb, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extwh $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x22, 0x02, 0xc3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extwl $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xd2, 0xc3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extwl $1,0xde,$3" + - + input: + bytes: [ 0xc4, 0x20, 0x3f, 0xfc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fbeq $f1,0xfffffffffffffff4" + - + input: + bytes: [ 0xd8, 0x20, 0x3f, 0xfc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fbge $f1,0xfffffffffffffff4" + - + input: + bytes: [ 0xdc, 0x20, 0x3f, 0xfc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fbgt $f1,0xfffffffffffffff4" + - + input: + bytes: [ 0xcc, 0x20, 0x3f, 0xfc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fble $f1,0xfffffffffffffff4" + - + input: + bytes: [ 0xc8, 0x20, 0x3f, 0xfc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fblt $f1,0xfffffffffffffff4" + - + input: + bytes: [ 0xd4, 0x20, 0x3f, 0xfc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fbne $f1,0xfffffffffffffff4" + - + input: + bytes: [ 0x5c, 0x22, 0x05, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmoveq ,$f10,$f11" + - + input: + bytes: [ 0x5c, 0x22, 0x05, 0xa3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmovge ,$f10,$f11" + - + input: + bytes: [ 0x5c, 0x22, 0x05, 0xe3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmovgt ,$f10,$f11" + - + input: + bytes: [ 0x5c, 0x22, 0x05, 0xc3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmovle ,$f10,$f11" + - + input: + bytes: [ 0x5c, 0x22, 0x05, 0x83 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmovlt ,$f10,$f11" + - + input: + bytes: [ 0x5c, 0x22, 0x05, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmovne ,$f10,$f11" + - + input: + bytes: [ 0x63, 0xe1, 0x80, 0x00 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fetch ($1)" + - + input: + bytes: [ 0x63, 0xe1, 0xa0, 0x00 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fetch_m ($1)" + - + input: + bytes: [ 0x70, 0x3f, 0x0f, 0x01 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ftois $f1,$1" + - + input: + bytes: [ 0x70, 0x3f, 0x0e, 0x01 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ftoit $f1,$1" + - + input: + bytes: [ 0x48, 0x22, 0x01, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "insbl $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xd1, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "insbl $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x22, 0x0c, 0xe3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "inslh $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xdc, 0xe3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "inslh $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x22, 0x05, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "insll $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xd5, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "insll $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x22, 0x0e, 0xe3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "insqh $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xde, 0xe3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "insqh $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x22, 0x07, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "insql $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xd7, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "insql $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x22, 0x0a, 0xe3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "inswh $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xda, 0xe3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "inswh $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x22, 0x03, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "inswl $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xd3, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "inswl $1,0xde,$3" + - + input: + bytes: [ 0x50, 0x3f, 0x00, 0x81 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "itofs $1,$f1" + - + input: + bytes: [ 0x50, 0x3f, 0x04, 0x81 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "itoft $1,$f1" + - + input: + bytes: [ 0x6b, 0xfa, 0x00, 0x00 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "jmp $31,$12,0" + - + input: + bytes: [ 0x6b, 0x5b, 0x40, 0x00 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "jsr $26,($27),0" + - + input: + bytes: [ 0x68, 0x22, 0xcf, 0xff ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "jsr_coroutine $1,($2),0xfff" + - + input: + bytes: [ 0x20, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lda $1,0x10($2)" + - + input: + bytes: [ 0x24, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldah $1,0x10($2)" + - + input: + bytes: [ 0x28, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldbu $1,0x10($2)" + - + input: + bytes: [ 0xa0, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldl $1,0x10($2)" + - + input: + bytes: [ 0xa8, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldl_l $1,0x10($2)" + - + input: + bytes: [ 0xa4, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldq $1,0x10($2)" + - + input: + bytes: [ 0xac, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldq_l $1,0x10($2)" + - + input: + bytes: [ 0x2c, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldq_u $1,0x10($2)" + - + input: + bytes: [ 0x88, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lds $f1,0x10($2)" + - + input: + bytes: [ 0x8c, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldt $f1,0x10($2)" + - + input: + bytes: [ 0x30, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldwu $1,0x10($2)" + - + input: + bytes: [ 0x60, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mb" + - + input: + bytes: [ 0x48, 0x22, 0x00, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mskbl $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xd0, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mskbl $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x22, 0x0c, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msklh $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xdc, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msklh $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x22, 0x04, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mskll $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xd4, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mskll $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x22, 0x0e, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mskqh $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xde, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mskqh $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x22, 0x06, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mskql $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xd6, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mskql $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x22, 0x0a, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mskwh $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xda, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mskwh $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x22, 0x02, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mskwl $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xd2, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mskwl $1,0xde,$3" + - + input: + bytes: [ 0x4c, 0x22, 0x00, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mull $1,$2,$3" + - + input: + bytes: [ 0x4c, 0x3b, 0xd0, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mull $1,0xde,$3" + - + input: + bytes: [ 0x4c, 0x22, 0x04, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulq $1,$2,$3" + - + input: + bytes: [ 0x4c, 0x3b, 0xd4, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulq $1,0xde,$3" + - + input: + bytes: [ 0x58, 0x22, 0xb0, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "muls/su $f1,$f10,$f11" + - + input: + bytes: [ 0x58, 0x22, 0xb4, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mult/su $f1,$f10,$f11" + - + input: + bytes: [ 0x44, 0x22, 0x05, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ornot $1,$2,$3" + - + input: + bytes: [ 0x44, 0x3b, 0xd5, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ornot $1,0xde,$3" + - + input: + bytes: [ 0x60, 0x20, 0xe0, 0x00 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rc $1" + - + input: + bytes: [ 0x6b, 0xfa, 0x80, 0x01 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ret $31,($26),1" + - + input: + bytes: [ 0x60, 0x1f, 0xc0, 0x00 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rpcc $0" + - + input: + bytes: [ 0x60, 0x20, 0xf0, 0x00 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rs $1" + - + input: + bytes: [ 0x40, 0x22, 0x00, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s4addl $1,$2,$3" + - + input: + bytes: [ 0x40, 0x3b, 0xd0, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s4addl $1,0xde,$3" + - + input: + bytes: [ 0x40, 0x22, 0x01, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s4subl $1,$2,$3" + - + input: + bytes: [ 0x40, 0x3b, 0xd1, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s4subl $1,0xde,$3" + - + input: + bytes: [ 0x40, 0x22, 0x05, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s4subq $1,$2,$3" + - + input: + bytes: [ 0x40, 0x3b, 0xd5, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s4subq $1,0xde,$3" + - + input: + bytes: [ 0x40, 0x22, 0x02, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s8addl $1,$2,$3" + - + input: + bytes: [ 0x40, 0x3b, 0xd2, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s8addl $1,0xde,$3" + - + input: + bytes: [ 0x40, 0x22, 0x06, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s8addq $1,$2,$3" + - + input: + bytes: [ 0x40, 0x3b, 0xd6, 0x43 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s8addq $1,0xde,$3" + - + input: + bytes: [ 0x40, 0x22, 0x03, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s8subl $1,$2,$3" + - + input: + bytes: [ 0x40, 0x3b, 0xd3, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s8subl $1,0xde,$3" + - + input: + bytes: [ 0x40, 0x22, 0x07, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s8subq $1,$2,$3" + - + input: + bytes: [ 0x40, 0x3b, 0xd7, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s8subq $1,0xde,$3" + - + input: + bytes: [ 0x73, 0xe1, 0x00, 0x02 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sextb $1,$2" + - + input: + bytes: [ 0x73, 0xe1, 0x00, 0x22 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sextw $1,$2" + - + input: + bytes: [ 0x48, 0x22, 0x07, 0x23 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sll $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xd7, 0x23 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sll $1,0xde,$3" + - + input: + bytes: [ 0x53, 0xe1, 0xb1, 0x62 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqrts/su $f1,$f10" + - + input: + bytes: [ 0x53, 0xe1, 0xb5, 0x62 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqrtt/su $f1,$f10" + - + input: + bytes: [ 0x48, 0x22, 0x07, 0x83 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sra $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xd7, 0x83 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sra $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x22, 0x06, 0x83 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srl $1,$2,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xd6, 0x83 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srl $1,0xde,$3" + - + input: + bytes: [ 0x38, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stb $1, 0x10($2)" + - + input: + bytes: [ 0xb0, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stl $1,0x10($2)" + - + input: + bytes: [ 0xb8, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stl_c $1,0x10($2)" + - + input: + bytes: [ 0xb4, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stq $1,0x10($2)" + - + input: + bytes: [ 0xbc, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stq_c $1,0x10($2)" + - + input: + bytes: [ 0x3c, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stq_u $1, 0x10($2)" + - + input: + bytes: [ 0x98, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sts $f1,0x10($2)" + - + input: + bytes: [ 0x9c, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stt $f1,0x10($2)" + - + input: + bytes: [ 0x34, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stw $1,0x10($2)" + - + input: + bytes: [ 0x40, 0x22, 0x01, 0x23 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subl $1,$2,$3" + - + input: + bytes: [ 0x40, 0x3b, 0xd1, 0x23 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subl $1,0xde,$3" + - + input: + bytes: [ 0x40, 0x22, 0x05, 0x23 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subq $1,$2,$3" + - + input: + bytes: [ 0x40, 0x3b, 0xd5, 0x23 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subq $1,0xde,$3" + - + input: + bytes: [ 0x58, 0x22, 0xb0, 0x23 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subs/su $f1,$f10,$f11" + - + input: + bytes: [ 0x58, 0x22, 0xb4, 0x23 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subt/su $f1,$f10,$f11" + - + input: + bytes: [ 0x60, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trapb" + - + input: + bytes: [ 0x4c, 0x22, 0x06, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "umulh $1,$2,$3" + - + input: + bytes: [ 0x4c, 0x3b, 0xd6, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "umulh $1,0xde,$3" + - + input: + bytes: [ 0x63, 0xe1, 0xf8, 0x00 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wh64 ($1)" + - + input: + bytes: [ 0x63, 0xe1, 0xfc, 0x00 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wh64en ($1)" + - + input: + bytes: [ 0x60, 0x00, 0x44, 0x00 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wmb" + - + input: + bytes: [ 0x44, 0x22, 0x08, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xor $1,$2,$3" + - + input: + bytes: [ 0x44, 0x3b, 0xd8, 0x03 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xor $1,0xde,$3" + - + input: + bytes: [ 0x48, 0x3b, 0xd6, 0x23 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "zapnot $1,0xde,$3" diff --git a/tests/MC/Alpha/insn-alpha.s.yaml b/tests/MC/Alpha/insn-alpha.s.yaml new file mode 100644 index 0000000000..54fcbb4c33 --- /dev/null +++ b/tests/MC/Alpha/insn-alpha.s.yaml @@ -0,0 +1,1783 @@ +test_cases: + - + input: + bytes: [ 0x03, 0x00, 0x22, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "addl $1,$2,$3" + - + input: + bytes: [ 0x03, 0xd0, 0x3b, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "addl $1,0xde,$3" + - + input: + bytes: [ 0x03, 0x04, 0x22, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "addq $1,$2,$3" + - + input: + bytes: [ 0x03, 0xd4, 0x3b, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "addq $1,0xde,$3" + - + input: + bytes: [ 0x03, 0xb0, 0x22, 0x58 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "adds/su $f1,$f10,$f11" + - + input: + bytes: [ 0x03, 0xb4, 0x22, 0x58 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "addt/su $f1,$f10,$f11" + - + input: + bytes: [ 0x03, 0x00, 0x22, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "and $1,$2,$3" + - + input: + bytes: [ 0x03, 0xd0, 0x3b, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "and $1,0xde,$3" + - + input: + bytes: [ 0xfc, 0x3f, 0x20, 0xe4 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "beq $1,0xfffffffffffffff4" + - + input: + bytes: [ 0xfc, 0x3f, 0x20, 0xf8 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "bge $1,0xfffffffffffffff4" + - + input: + bytes: [ 0xfc, 0x3f, 0x20, 0xfc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "bgt $1,0xfffffffffffffff4" + - + input: + bytes: [ 0x03, 0x01, 0x22, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "bic $1,$2,$3" + - + input: + bytes: [ 0x03, 0xd1, 0x3b, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "bic $1,0xde,$3" + - + input: + bytes: [ 0x03, 0x04, 0x22, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "bis $1,$2,$3" + - + input: + bytes: [ 0x03, 0xd4, 0x3b, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "bis $1,0xde,$3" + - + input: + bytes: [ 0xfc, 0x3f, 0x20, 0xe0 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "blbc $1,0xfffffffffffffff4" + - + input: + bytes: [ 0xfc, 0x3f, 0x20, 0xf0 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "blbs $1,0xfffffffffffffff4" + - + input: + bytes: [ 0xfc, 0x3f, 0x20, 0xec ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ble $1,0xfffffffffffffff4" + - + input: + bytes: [ 0xfc, 0x3f, 0x20, 0xe8 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "blt $1,0xfffffffffffffff4" + - + input: + bytes: [ 0xfc, 0x3f, 0x20, 0xf4 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "bne $1,0xfffffffffffffff4" + - + input: + bytes: [ 0xfc, 0x3f, 0xe0, 0xc3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "br $31,0xfffffffffffffff4" + - + input: + bytes: [ 0xfc, 0x3f, 0x40, 0xd3 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "bsr $26,$0xfffffffffffffff4 ..ng" + - + input: + bytes: [ 0x83, 0x04, 0x22, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmoveq $1,$2,$3" + - + input: + bytes: [ 0xc3, 0x08, 0x22, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmovge $1,$2,$3" + - + input: + bytes: [ 0xc3, 0x0c, 0x22, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmovgt $1,$2,$3" + - + input: + bytes: [ 0xc3, 0x02, 0x22, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmovlbc $1,$2,$3" + - + input: + bytes: [ 0x83, 0x02, 0x22, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmovlbs $1,$2,$3" + - + input: + bytes: [ 0x83, 0x0c, 0x22, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmovle $1,$2,$3" + - + input: + bytes: [ 0x83, 0x08, 0x22, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmovlt $1,$2,$3" + - + input: + bytes: [ 0xc3, 0x04, 0x22, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmovne $1,$2,$3" + - + input: + bytes: [ 0xe3, 0x01, 0x22, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpbge $1,$2,$3" + - + input: + bytes: [ 0xe3, 0xd1, 0x3b, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpbge $1,0xde,$3" + - + input: + bytes: [ 0xa3, 0x05, 0x22, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpeq $1,$2,$3" + - + input: + bytes: [ 0xa3, 0xd5, 0x3b, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpeq $1,0xde,$3" + - + input: + bytes: [ 0xa3, 0x0d, 0x22, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmple $1,$2,$3" + - + input: + bytes: [ 0xa3, 0xdd, 0x3b, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmple $1,0xde,$3" + - + input: + bytes: [ 0xa3, 0x09, 0x22, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmplt $1,$2,$3" + - + input: + bytes: [ 0xa3, 0xd9, 0x3b, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmplt $1,0xde,$3" + - + input: + bytes: [ 0xa3, 0xb4, 0x22, 0x58 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpteq/su $f1,$f10,$f11" + - + input: + bytes: [ 0xe3, 0xb4, 0x22, 0x58 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmptle/su $f1,$f10,$f11" + - + input: + bytes: [ 0xc3, 0xb4, 0x22, 0x58 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmptlt/su $f1,$f10,$f11" + - + input: + bytes: [ 0x83, 0xb4, 0x22, 0x58 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmptun/su $f1,$f10,$f11" + - + input: + bytes: [ 0xa3, 0x07, 0x22, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpule $1,$2,$3" + - + input: + bytes: [ 0xa3, 0xd7, 0x3b, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpule $1,0xde,$3" + - + input: + bytes: [ 0xa3, 0x03, 0x22, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpult $1,$2,$3" + - + input: + bytes: [ 0xa3, 0xd3, 0x3b, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpult $1,0xde,$3" + - + input: + bytes: [ 0x43, 0x04, 0x22, 0x5c ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cpyse $f1,$f10,$f11" + - + input: + bytes: [ 0x23, 0x04, 0x22, 0x5c ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cpysn $f1,$f10,$f11" + - + input: + bytes: [ 0x03, 0x04, 0x22, 0x5c ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cpys $f1,$f10,$f11" + - + input: + bytes: [ 0x42, 0x06, 0xe1, 0x73 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ctlz $1,$2" + - + input: + bytes: [ 0x02, 0x06, 0xe1, 0x73 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ctpop $1,$2" + - + input: + bytes: [ 0x62, 0x06, 0xe1, 0x73 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cttz $1,$2" + - + input: + bytes: [ 0x82, 0xf7, 0xe1, 0x5b ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cvtqs/sui $f1,$f10" + - + input: + bytes: [ 0xc2, 0xf7, 0xe1, 0x5b ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cvtqt/sui $f1,$f10" + - + input: + bytes: [ 0x82, 0xd5, 0xe1, 0x5b ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cvtst/s $f1,$f10" + - + input: + bytes: [ 0xe2, 0xa5, 0xe1, 0x5b ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cvttq/svc $f1,$f10" + - + input: + bytes: [ 0x82, 0xf5, 0xe1, 0x5b ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "cvtts/sui $f1,$f10" + - + input: + bytes: [ 0x63, 0xb0, 0x22, 0x58 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "divs/su $f1,$f10,$f11" + - + input: + bytes: [ 0x63, 0xb4, 0x22, 0x58 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "divt/su $f1,$f10,$f11" + - + input: + bytes: [ 0x00, 0xe8, 0xe1, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ecb ($1)" + - + input: + bytes: [ 0x03, 0x09, 0x22, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "eqv $1,$2,$3" + - + input: + bytes: [ 0x03, 0xd9, 0x3b, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "eqv $1,0xde,$3" + - + input: + bytes: [ 0x00, 0x04, 0x00, 0x60 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "excb" + - + input: + bytes: [ 0xc3, 0x00, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "extbl $1,$2,$3" + - + input: + bytes: [ 0xc3, 0xd0, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "extbl $1,0xde,$3" + - + input: + bytes: [ 0x43, 0x0d, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "extlh $1,$2,$3" + - + input: + bytes: [ 0x43, 0xdd, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "extlh $1,0xde,$3" + - + input: + bytes: [ 0xc3, 0x04, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "extll $1,$2,$3" + - + input: + bytes: [ 0xc3, 0xd4, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "extll $1,0xde,$3" + - + input: + bytes: [ 0x43, 0x0f, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "extqh $1,$2,$3" + - + input: + bytes: [ 0x43, 0xdf, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "extqh $1,0xde,$3" + - + input: + bytes: [ 0xc3, 0x06, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "extql $1,$2,$3" + - + input: + bytes: [ 0xc3, 0xd6, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "extql $1,0xde,$3" + - + input: + bytes: [ 0x43, 0x0b, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "extwh $1,$2,$3" + - + input: + bytes: [ 0x43, 0xdb, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "extwh $1,0xde,$3" + - + input: + bytes: [ 0xc3, 0x02, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "extwl $1,$2,$3" + - + input: + bytes: [ 0xc3, 0xd2, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "extwl $1,0xde,$3" + - + input: + bytes: [ 0xfc, 0x3f, 0x20, 0xc4 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "fbeq $f1,0xfffffffffffffff4" + - + input: + bytes: [ 0xfc, 0x3f, 0x20, 0xd8 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "fbge $f1,0xfffffffffffffff4" + - + input: + bytes: [ 0xfc, 0x3f, 0x20, 0xdc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "fbgt $f1,0xfffffffffffffff4" + - + input: + bytes: [ 0xfc, 0x3f, 0x20, 0xcc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "fble $f1,0xfffffffffffffff4" + - + input: + bytes: [ 0xfc, 0x3f, 0x20, 0xc8 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "fblt $f1,0xfffffffffffffff4" + - + input: + bytes: [ 0xfc, 0x3f, 0x20, 0xd4 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "fbne $f1,0xfffffffffffffff4" + - + input: + bytes: [ 0x43, 0x05, 0x22, 0x5c ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmoveq ,$f10,$f11" + - + input: + bytes: [ 0xa3, 0x05, 0x22, 0x5c ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmovge ,$f10,$f11" + - + input: + bytes: [ 0xe3, 0x05, 0x22, 0x5c ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmovgt ,$f10,$f11" + - + input: + bytes: [ 0xc3, 0x05, 0x22, 0x5c ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmovle ,$f10,$f11" + - + input: + bytes: [ 0x83, 0x05, 0x22, 0x5c ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmovlt ,$f10,$f11" + - + input: + bytes: [ 0x63, 0x05, 0x22, 0x5c ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmovne ,$f10,$f11" + - + input: + bytes: [ 0x00, 0x80, 0xe1, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "fetch ($1)" + - + input: + bytes: [ 0x00, 0xa0, 0xe1, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "fetch_m ($1)" + - + input: + bytes: [ 0x01, 0x0f, 0x3f, 0x70 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ftois $f1,$1" + - + input: + bytes: [ 0x01, 0x0e, 0x3f, 0x70 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ftoit $f1,$1" + - + input: + bytes: [ 0x63, 0x01, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "insbl $1,$2,$3" + - + input: + bytes: [ 0x63, 0xd1, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "insbl $1,0xde,$3" + - + input: + bytes: [ 0xe3, 0x0c, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "inslh $1,$2,$3" + - + input: + bytes: [ 0xe3, 0xdc, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "inslh $1,0xde,$3" + - + input: + bytes: [ 0x63, 0x05, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "insll $1,$2,$3" + - + input: + bytes: [ 0x63, 0xd5, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "insll $1,0xde,$3" + - + input: + bytes: [ 0xe3, 0x0e, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "insqh $1,$2,$3" + - + input: + bytes: [ 0xe3, 0xde, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "insqh $1,0xde,$3" + - + input: + bytes: [ 0x63, 0x07, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "insql $1,$2,$3" + - + input: + bytes: [ 0x63, 0xd7, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "insql $1,0xde,$3" + - + input: + bytes: [ 0xe3, 0x0a, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "inswh $1,$2,$3" + - + input: + bytes: [ 0xe3, 0xda, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "inswh $1,0xde,$3" + - + input: + bytes: [ 0x63, 0x03, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "inswl $1,$2,$3" + - + input: + bytes: [ 0x63, 0xd3, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "inswl $1,0xde,$3" + - + input: + bytes: [ 0x81, 0x00, 0x3f, 0x50 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "itofs $1,$f1" + - + input: + bytes: [ 0x81, 0x04, 0x3f, 0x50 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "itoft $1,$f1" + - + input: + bytes: [ 0x00, 0x00, 0xfa, 0x6b ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jmp $31,$12,0" + - + input: + bytes: [ 0x00, 0x40, 0x5b, 0x6b ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jsr $26,($27),0" + - + input: + bytes: [ 0xff, 0xcf, 0x22, 0x68 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jsr_coroutine $1,($2),0xfff" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0x20 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "lda $1,0x10($2)" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0x24 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ldah $1,0x10($2)" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0x28 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ldbu $1,0x10($2)" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0xa0 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ldl $1,0x10($2)" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0xa8 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ldl_l $1,0x10($2)" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0xa4 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ldq $1,0x10($2)" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0xac ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ldq_l $1,0x10($2)" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0x2c ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ldq_u $1,0x10($2)" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0x88 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "lds $f1,0x10($2)" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0x8c ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ldt $f1,0x10($2)" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0x30 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ldwu $1,0x10($2)" + - + input: + bytes: [ 0x00, 0x40, 0x00, 0x60 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mb" + - + input: + bytes: [ 0x43, 0x00, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mskbl $1,$2,$3" + - + input: + bytes: [ 0x43, 0xd0, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mskbl $1,0xde,$3" + - + input: + bytes: [ 0x43, 0x0c, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "msklh $1,$2,$3" + - + input: + bytes: [ 0x43, 0xdc, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "msklh $1,0xde,$3" + - + input: + bytes: [ 0x43, 0x04, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mskll $1,$2,$3" + - + input: + bytes: [ 0x43, 0xd4, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mskll $1,0xde,$3" + - + input: + bytes: [ 0x43, 0x0e, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mskqh $1,$2,$3" + - + input: + bytes: [ 0x43, 0xde, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mskqh $1,0xde,$3" + - + input: + bytes: [ 0x43, 0x06, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mskql $1,$2,$3" + - + input: + bytes: [ 0x43, 0xd6, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mskql $1,0xde,$3" + - + input: + bytes: [ 0x43, 0x0a, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mskwh $1,$2,$3" + - + input: + bytes: [ 0x43, 0xda, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mskwh $1,0xde,$3" + - + input: + bytes: [ 0x43, 0x02, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mskwl $1,$2,$3" + - + input: + bytes: [ 0x43, 0xd2, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mskwl $1,0xde,$3" + - + input: + bytes: [ 0x03, 0x00, 0x22, 0x4c ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mull $1,$2,$3" + - + input: + bytes: [ 0x03, 0xd0, 0x3b, 0x4c ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mull $1,0xde,$3" + - + input: + bytes: [ 0x03, 0x04, 0x22, 0x4c ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mulq $1,$2,$3" + - + input: + bytes: [ 0x03, 0xd4, 0x3b, 0x4c ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mulq $1,0xde,$3" + - + input: + bytes: [ 0x43, 0xb0, 0x22, 0x58 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "muls/su $f1,$f10,$f11" + - + input: + bytes: [ 0x43, 0xb4, 0x22, 0x58 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mult/su $f1,$f10,$f11" + - + input: + bytes: [ 0x03, 0x05, 0x22, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ornot $1,$2,$3" + - + input: + bytes: [ 0x03, 0xd5, 0x3b, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ornot $1,0xde,$3" + - + input: + bytes: [ 0x00, 0xe0, 0x20, 0x60 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "rc $1" + - + input: + bytes: [ 0x01, 0x80, 0xfa, 0x6b ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ret $31,($26),1" + - + input: + bytes: [ 0x00, 0xc0, 0x1f, 0x60 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "rpcc $0" + - + input: + bytes: [ 0x00, 0xf0, 0x20, 0x60 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "rs $1" + - + input: + bytes: [ 0x43, 0x00, 0x22, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "s4addl $1,$2,$3" + - + input: + bytes: [ 0x43, 0xd0, 0x3b, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "s4addl $1,0xde,$3" + - + input: + bytes: [ 0x63, 0x01, 0x22, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "s4subl $1,$2,$3" + - + input: + bytes: [ 0x63, 0xd1, 0x3b, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "s4subl $1,0xde,$3" + - + input: + bytes: [ 0x63, 0x05, 0x22, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "s4subq $1,$2,$3" + - + input: + bytes: [ 0x63, 0xd5, 0x3b, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "s4subq $1,0xde,$3" + - + input: + bytes: [ 0x43, 0x02, 0x22, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "s8addl $1,$2,$3" + - + input: + bytes: [ 0x43, 0xd2, 0x3b, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "s8addl $1,0xde,$3" + - + input: + bytes: [ 0x43, 0x06, 0x22, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "s8addq $1,$2,$3" + - + input: + bytes: [ 0x43, 0xd6, 0x3b, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "s8addq $1,0xde,$3" + - + input: + bytes: [ 0x63, 0x03, 0x22, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "s8subl $1,$2,$3" + - + input: + bytes: [ 0x63, 0xd3, 0x3b, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "s8subl $1,0xde,$3" + - + input: + bytes: [ 0x63, 0x07, 0x22, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "s8subq $1,$2,$3" + - + input: + bytes: [ 0x63, 0xd7, 0x3b, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "s8subq $1,0xde,$3" + - + input: + bytes: [ 0x02, 0x00, 0xe1, 0x73 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "sextb $1,$2" + - + input: + bytes: [ 0x22, 0x00, 0xe1, 0x73 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "sextw $1,$2" + - + input: + bytes: [ 0x23, 0x07, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "sll $1,$2,$3" + - + input: + bytes: [ 0x23, 0xd7, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "sll $1,0xde,$3" + - + input: + bytes: [ 0x62, 0xb1, 0xe1, 0x53 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "sqrts/su $f1,$f10" + - + input: + bytes: [ 0x62, 0xb5, 0xe1, 0x53 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "sqrtt/su $f1,$f10" + - + input: + bytes: [ 0x83, 0x07, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "sra $1,$2,$3" + - + input: + bytes: [ 0x83, 0xd7, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "sra $1,0xde,$3" + - + input: + bytes: [ 0x83, 0x06, 0x22, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "srl $1,$2,$3" + - + input: + bytes: [ 0x83, 0xd6, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "srl $1,0xde,$3" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0x38 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "stb $1, 0x10($2)" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0xb0 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "stl $1,0x10($2)" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0xb8 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "stl_c $1,0x10($2)" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0xb4 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "stq $1,0x10($2)" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0xbc ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "stq_c $1,0x10($2)" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0x3c ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "stq_u $1, 0x10($2)" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0x98 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "sts $f1,0x10($2)" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0x9c ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "stt $f1,0x10($2)" + - + input: + bytes: [ 0x10, 0x00, 0x22, 0x34 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "stw $1,0x10($2)" + - + input: + bytes: [ 0x23, 0x01, 0x22, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "subl $1,$2,$3" + - + input: + bytes: [ 0x23, 0xd1, 0x3b, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "subl $1,0xde,$3" + - + input: + bytes: [ 0x23, 0x05, 0x22, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "subq $1,$2,$3" + - + input: + bytes: [ 0x23, 0xd5, 0x3b, 0x40 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "subq $1,0xde,$3" + - + input: + bytes: [ 0x23, 0xb0, 0x22, 0x58 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "subs/su $f1,$f10,$f11" + - + input: + bytes: [ 0x23, 0xb4, 0x22, 0x58 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "subt/su $f1,$f10,$f11" + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x60 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "trapb" + - + input: + bytes: [ 0x03, 0x06, 0x22, 0x4c ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "umulh $1,$2,$3" + - + input: + bytes: [ 0x03, 0xd6, 0x3b, 0x4c ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "umulh $1,0xde,$3" + - + input: + bytes: [ 0x00, 0xf8, 0xe1, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "wh64 ($1)" + - + input: + bytes: [ 0x00, 0xfc, 0xe1, 0x63 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "wh64en ($1)" + - + input: + bytes: [ 0x00, 0x44, 0x00, 0x60 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "wmb" + - + input: + bytes: [ 0x03, 0x08, 0x22, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "xor $1,$2,$3" + - + input: + bytes: [ 0x03, 0xd8, 0x3b, 0x44 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "xor $1,0xde,$3" + - + input: + bytes: [ 0x23, 0xd6, 0x3b, 0x48 ] + arch: "CS_ARCH_ALPHA" + options: [ "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "zapnot $1,0xde,$3" diff --git a/tests/MC/BPF/classic-all.yaml b/tests/MC/BPF/classic-all.yaml new file mode 100644 index 0000000000..6502492e51 --- /dev/null +++ b/tests/MC/BPF/classic-all.yaml @@ -0,0 +1,451 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x98, 0xab, 0x08, 0x02, 0x0e, 0x45 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ld 0x450e0208" + - + input: + bytes: [ 0x01, 0x00, 0x44, 0x49, 0x1f, 0xfe, 0xd3, 0x93 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ldx 0x93d3fe1f" + - + input: + bytes: [ 0x04, 0x00, 0xda, 0x23, 0x71, 0xc5, 0x51, 0x42 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "add 0x4251c571" + - + input: + bytes: [ 0x05, 0x00, 0xd4, 0xbd, 0x37, 0xc8, 0x2c, 0xd5 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "jmp +0xd52cc837" + - + input: + bytes: [ 0x06, 0x00, 0xa7, 0x84, 0x25, 0x40, 0x28, 0x1c ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ret 0x1c284025" + - + input: + bytes: [ 0x07, 0x00, 0xe8, 0xe8, 0x48, 0xe2, 0x84, 0x2a ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "tax" + - + input: + bytes: [ 0x0c, 0x00, 0x55, 0x8c, 0x32, 0xd8, 0x21, 0xe8 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "add x" + - + input: + bytes: [ 0x0e, 0x00, 0xd4, 0x24, 0x96, 0xf7, 0xa1, 0x49 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ret x" + - + input: + bytes: [ 0x14, 0x00, 0x6a, 0xc8, 0x14, 0x50, 0x2d, 0x69 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "sub 0x692d5014" + - + input: + bytes: [ 0x15, 0x00, 0xc3, 0x39, 0x6e, 0x4f, 0x37, 0x18 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "jeq 0x18374f6e, +0xc3, +0x39" + - + input: + bytes: [ 0x16, 0x00, 0x57, 0xd2, 0xc4, 0xd4, 0x8a, 0x51 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ret a" + - + input: + bytes: [ 0x1c, 0x00, 0xd1, 0x51, 0x90, 0x8a, 0x8d, 0xea ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "sub x" + - + input: + bytes: [ 0x1d, 0x00, 0x2e, 0xa8, 0xbc, 0xa7, 0xd5, 0x3a ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "jeq x, +0x2e, +0xa8" + - + input: + bytes: [ 0x20, 0x00, 0x9a, 0x43, 0x93, 0x27, 0xec, 0xf7 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ld [0xf7ec2793]" + - + input: + bytes: [ 0x24, 0x00, 0x0f, 0x46, 0xbe, 0xe5, 0xd2, 0x4a ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "mul 0x4ad2e5be" + - + input: + bytes: [ 0x25, 0x00, 0x8c, 0x80, 0xc1, 0x03, 0x38, 0x61 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "jgt 0x613803c1, +0x8c, +0x80" + - + input: + bytes: [ 0x28, 0x00, 0xc3, 0x05, 0x73, 0x01, 0x39, 0xbd ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ldh [0xbd390173]" + - + input: + bytes: [ 0x2c, 0x00, 0x7a, 0x3d, 0xad, 0x19, 0xe7, 0xcc ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "mul x" + - + input: + bytes: [ 0x2d, 0x00, 0xd9, 0xc6, 0xf7, 0x72, 0x9a, 0x9d ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "jgt x, +0xd9, +0xc6" + - + input: + bytes: [ 0x30, 0x00, 0x22, 0x29, 0x29, 0x5b, 0xb5, 0x87 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ldb [0x87b55b29]" + - + input: + bytes: [ 0x34, 0x00, 0xa8, 0xfa, 0x6a, 0x92, 0xa2, 0xa8 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "div 0xa8a2926a" + - + input: + bytes: [ 0x35, 0x00, 0x24, 0xdb, 0x58, 0x41, 0xa8, 0x58 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "jge 0x58a84158, +0x24, +0xdb" + - + input: + bytes: [ 0x3c, 0x00, 0x41, 0xa6, 0xd5, 0x66, 0x8a, 0xdd ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "div x" + - + input: + bytes: [ 0x3d, 0x00, 0xe4, 0xbc, 0x40, 0xb3, 0x4d, 0x84 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "jge x, +0xe4, +0xbc" + - + input: + bytes: [ 0x40, 0x00, 0xf1, 0xa0, 0xd9, 0x89, 0x72, 0x25 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ld [x+0x257289d9]" + - + input: + bytes: [ 0x44, 0x00, 0x8d, 0xf8, 0x49, 0xdb, 0x10, 0x82 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "or 0x8210db49" + - + input: + bytes: [ 0x45, 0x00, 0x43, 0xfc, 0x7d, 0xa1, 0x34, 0xed ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "jset 0xed34a17d, +0x43, +0xfc" + - + input: + bytes: [ 0x48, 0x00, 0x6b, 0x89, 0x0b, 0xca, 0xfb, 0x1b ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ldh [x+0x1bfbca0b]" + - + input: + bytes: [ 0x4c, 0x00, 0xc9, 0xff, 0x36, 0xe9, 0x2a, 0xe7 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "or x" + - + input: + bytes: [ 0x4d, 0x00, 0x0d, 0xaa, 0xc3, 0x50, 0xea, 0x40 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "jset x, +0xd, +0xaa" + - + input: + bytes: [ 0x50, 0x00, 0xd9, 0xf3, 0xda, 0xa7, 0xd9, 0xb1 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ldb [x+0xb1d9a7da]" + - + input: + bytes: [ 0x54, 0x00, 0x14, 0x82, 0x29, 0x82, 0x6c, 0x06 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "and 0x66c8229" + - + input: + bytes: [ 0x5c, 0x00, 0x80, 0x37, 0x5f, 0x52, 0xc0, 0x84 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "and x" + - + input: + bytes: [ 0x60, 0x00, 0xba, 0x4e, 0xb5, 0x3f, 0xdc, 0xd8 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ld m[0xd8dc3fb5]" + - + input: + bytes: [ 0x61, 0x00, 0x06, 0xd9, 0xcd, 0x84, 0x58, 0x94 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ldx m[0x945884cd]" + - + input: + bytes: [ 0x62, 0x00, 0x2c, 0x44, 0xdf, 0x71, 0x48, 0x1b ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "st m[0x1b4871df]" + - + input: + bytes: [ 0x63, 0x00, 0xc9, 0x53, 0x7f, 0x80, 0x89, 0x2d ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "stx m[0x2d89807f]" + - + input: + bytes: [ 0x64, 0x00, 0x8a, 0xe5, 0xf0, 0x0c, 0xca, 0xfd ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "lsh 0xfdca0cf0" + - + input: + bytes: [ 0x6c, 0x00, 0xd3, 0x85, 0xc1, 0x96, 0xb1, 0x48 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "lsh x" + - + input: + bytes: [ 0x74, 0x00, 0xfa, 0x6f, 0xe9, 0xbe, 0xde, 0x7e ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "rsh 0x7edebee9" + - + input: + bytes: [ 0x7c, 0x00, 0x0d, 0x89, 0xed, 0x17, 0x7d, 0xcd ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "rsh x" + - + input: + bytes: [ 0x80, 0x00, 0x70, 0x62, 0x0e, 0x61, 0x1b, 0x94 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ld #len" + - + input: + bytes: [ 0x81, 0x00, 0xa0, 0x03, 0xa2, 0x5c, 0x1f, 0x2a ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ldx #len" + - + input: + bytes: [ 0x84, 0x00, 0x4f, 0x0f, 0xc9, 0x4a, 0x72, 0xff ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "neg" + - + input: + bytes: [ 0x87, 0x00, 0x17, 0x2a, 0x9a, 0xd6, 0xb6, 0x8f ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "txa" + - + input: + bytes: [ 0x94, 0x00, 0x85, 0x0c, 0x29, 0xb2, 0xbe, 0x83 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "mod 0x83beb229" + - + input: + bytes: [ 0x9c, 0x00, 0x30, 0x3f, 0x9d, 0x33, 0x89, 0x50 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "mod x" + - + input: + bytes: [ 0xa1, 0x00, 0x53, 0x03, 0xdd, 0xdf, 0xd4, 0xe3 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ldx 4*([0xe3d4dfdd]&0xf)" + - + input: + bytes: [ 0xa4, 0x00, 0x66, 0x8f, 0x3c, 0xde, 0xe2, 0x4d ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "xor 0x4de2de3c" + - + input: + bytes: [ 0xac, 0x00, 0x02, 0x2f, 0x1e, 0xe3, 0x2e, 0x84 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "xor x" diff --git a/tests/MC/BPF/classic-be.yaml b/tests/MC/BPF/classic-be.yaml new file mode 100644 index 0000000000..f62627b2ca --- /dev/null +++ b/tests/MC/BPF/classic-be.yaml @@ -0,0 +1,64 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x01, 0x00, 0x00, 0x33, 0x00, 0x0c, 0x11 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ldx 0x33000c11" + - + input: + bytes: [ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ld #len" + - + input: + bytes: [ 0x00, 0xa1, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ldx 4*([0x10000000]&0xf)" + - + input: + bytes: [ 0x00, 0x60, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ld m[0x9000000]" + - + input: + bytes: [ 0x00, 0x30, 0x00, 0x00, 0x37, 0x13, 0x03, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "ldb [0x37130300]" + - + input: + bytes: [ 0x00, 0x63, 0x00, 0x00, 0x0f, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "stx m[0xf003000]" + - + input: + bytes: [ 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_BPF_CLASSIC" ] + expected: + insns: + - + asm_text: "neg" diff --git a/tests/MC/BPF/extended-all.yaml b/tests/MC/BPF/extended-all.yaml new file mode 100644 index 0000000000..8140cac332 --- /dev/null +++ b/tests/MC/BPF/extended-all.yaml @@ -0,0 +1,874 @@ +test_cases: + - + input: + bytes: [ 0x04, 0xb4, 0x97, 0xa8, 0xe8, 0x60, 0x56, 0xe1 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "add r4, 0xe15660e8" + - + input: + bytes: [ 0x05, 0xc7, 0x71, 0xb0, 0x43, 0x1f, 0xb9, 0xf5 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jmp +0xb071" + - + input: + bytes: [ 0x07, 0x76, 0x01, 0x28, 0xc4, 0x09, 0xfe, 0x8b ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "add64 r6, 0x8bfe09c4" + - + input: + bytes: [ 0x0c, 0x42, 0x0a, 0x48, 0x58, 0xc4, 0xef, 0x37 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "add r2, r4" + - + input: + bytes: [ 0x0f, 0x09, 0x40, 0x54, 0x67, 0x24, 0x2f, 0x88 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "add64 r9, r0" + - + input: + bytes: [ 0x14, 0xd9, 0xba, 0xb8, 0x6f, 0x07, 0x93, 0x2a ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "sub r9, 0x2a93076f" + - + input: + bytes: [ 0x15, 0x6a, 0x9f, 0x38, 0x1a, 0x9d, 0xb7, 0x4d ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jeq r10, 0x4db79d1a, +0x389f" + - + input: + bytes: [ 0x17, 0xc5, 0x60, 0xed, 0x0b, 0xdc, 0xe6, 0x22 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "sub64 r5, 0x22e6dc0b" + - + input: + bytes: [ 0x18, 0xa3, 0x5c, 0x14, 0xde, 0xf0, 0xa5, 0xff, 0x9a, 0x7e, 0x10, 0xee, 0xd8, 0xa4, 0x2b, 0x2f ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "lddw r3, 0x2f2ba4d8ffa5f0de" + - + input: + bytes: [ 0x1c, 0x73, 0x68, 0xa4, 0x8b, 0x5b, 0x93, 0x1f ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "sub r3, r7" + - + input: + bytes: [ 0x1d, 0x21, 0x20, 0x4d, 0xe3, 0x47, 0xaf, 0x1b ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jeq r1, r2, +0x4d20" + - + input: + bytes: [ 0x1f, 0x06, 0x51, 0x5a, 0x39, 0xb2, 0x10, 0x10 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "sub64 r6, r0" + - + input: + bytes: [ 0x20, 0xc7, 0x0c, 0x70, 0xda, 0x41, 0x1a, 0xca ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ldw [0xca1a41da]" + - + input: + bytes: [ 0x24, 0xb6, 0x69, 0x66, 0xe3, 0xef, 0xec, 0x25 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mul r6, 0x25ecefe3" + - + input: + bytes: [ 0x25, 0x89, 0xda, 0x53, 0x19, 0x73, 0x8a, 0xc0 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jgt r9, 0xc08a7319, +0x53da" + - + input: + bytes: [ 0x27, 0xb1, 0x96, 0x1d, 0xd4, 0xab, 0x2c, 0x8c ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mul64 r1, 0x8c2cabd4" + - + input: + bytes: [ 0x28, 0x4e, 0xb0, 0x62, 0xe8, 0x48, 0x0b, 0x0d ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ldh [0xd0b48e8]" + - + input: + bytes: [ 0x2c, 0x78, 0x03, 0xf6, 0x29, 0x29, 0x15, 0xfc ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mul r8, r7" + - + input: + bytes: [ 0x2d, 0x18, 0x5b, 0xfd, 0x8f, 0x53, 0x3b, 0xf0 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jgt r8, r1, +0xfd5b" + - + input: + bytes: [ 0x2f, 0x77, 0xc7, 0xa4, 0x4c, 0x32, 0x73, 0x2a ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mul64 r7, r7" + - + input: + bytes: [ 0x30, 0x5f, 0xfe, 0xfc, 0x85, 0x66, 0x7c, 0x4b ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ldb [0x4b7c6685]" + - + input: + bytes: [ 0x34, 0x46, 0x49, 0x33, 0xe1, 0x72, 0xd4, 0xcb ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "div r6, 0xcbd472e1" + - + input: + bytes: [ 0x35, 0xa5, 0x42, 0xb9, 0x5b, 0x37, 0xa1, 0x3d ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jge r5, 0x3da1375b, +0xb942" + - + input: + bytes: [ 0x37, 0x84, 0xd8, 0xba, 0x3b, 0x84, 0x55, 0x1f ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "div64 r4, 0x1f55843b" + - + input: + bytes: [ 0x38, 0x8e, 0x3f, 0xd7, 0x1c, 0x3e, 0x3a, 0x7b ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "lddw [0x7b3a3e1c]" + - + input: + bytes: [ 0x3d, 0x1a, 0xc3, 0x9b, 0x88, 0xa2, 0x3f, 0x65 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jge r10, r1, +0x9bc3" + - + input: + bytes: [ 0x3f, 0x36, 0x99, 0x32, 0x7e, 0x07, 0x59, 0x7a ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "div64 r6, r3" + - + input: + bytes: [ 0x40, 0x95, 0xc2, 0x39, 0x6b, 0xe7, 0xd7, 0xc4 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ldw [r9+0xc4d7e76b]" + - + input: + bytes: [ 0x44, 0x16, 0xf7, 0x98, 0xf7, 0x02, 0x92, 0x94 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "or r6, 0x949202f7" + - + input: + bytes: [ 0x45, 0x12, 0xa2, 0xf2, 0x14, 0xe7, 0x2d, 0x1e ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jset r2, 0x1e2de714, +0xf2a2" + - + input: + bytes: [ 0x47, 0x36, 0xf4, 0xd5, 0xbe, 0x04, 0x58, 0x4d ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "or64 r6, 0x4d5804be" + - + input: + bytes: [ 0x48, 0x7e, 0xfb, 0x77, 0xeb, 0x0e, 0x5a, 0x0d ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ldh [r7+0xd5a0eeb]" + - + input: + bytes: [ 0x4c, 0x81, 0x0a, 0x66, 0xfc, 0x32, 0x61, 0xc4 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "or r1, r8" + - + input: + bytes: [ 0x4d, 0x10, 0x67, 0x44, 0x4d, 0x3f, 0x4d, 0x8b ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jset r0, r1, +0x4467" + - + input: + bytes: [ 0x4f, 0x81, 0xeb, 0x6b, 0xde, 0x98, 0x87, 0x64 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "or64 r1, r8" + - + input: + bytes: [ 0x50, 0x38, 0x80, 0xf8, 0x04, 0x70, 0xd1, 0x6c ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ldb [r3+0x6cd17004]" + - + input: + bytes: [ 0x54, 0x40, 0x0a, 0x6a, 0x4a, 0xe8, 0xab, 0xfb ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "and r0, 0xfbabe84a" + - + input: + bytes: [ 0x55, 0xb9, 0xa3, 0x80, 0x90, 0xbc, 0xc8, 0x96 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jne r9, 0x96c8bc90, +0x80a3" + - + input: + bytes: [ 0x57, 0x30, 0x12, 0xe9, 0x7c, 0x06, 0x82, 0x27 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "and64 r0, 0x2782067c" + - + input: + bytes: [ 0x58, 0x6d, 0xf1, 0x05, 0xd3, 0x50, 0x4b, 0xc0 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "lddw [r6+0xc04b50d3]" + - + input: + bytes: [ 0x5c, 0x02, 0x95, 0xb2, 0xbd, 0x3f, 0x38, 0x37 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "and r2, r0" + - + input: + bytes: [ 0x5d, 0x56, 0xa3, 0x4c, 0x2a, 0xc8, 0x4a, 0xc5 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jne r6, r5, +0x4ca3" + - + input: + bytes: [ 0x5f, 0x59, 0xf6, 0xaa, 0x5d, 0xeb, 0x27, 0xdd ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "and64 r9, r5" + - + input: + bytes: [ 0x61, 0x28, 0xb2, 0xed, 0xb8, 0xcf, 0xb5, 0xe4 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxw r8, [r2+0xedb2]" + - + input: + bytes: [ 0x62, 0xa5, 0xdf, 0xe0, 0x14, 0x7d, 0x95, 0x78 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "stw [r5+0xe0df], 0x78957d14" + - + input: + bytes: [ 0x63, 0x77, 0x2f, 0xcf, 0x76, 0xb7, 0xd3, 0xfa ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "stxw [r7+0xcf2f], r7" + - + input: + bytes: [ 0x64, 0x68, 0xc1, 0xf4, 0x88, 0x92, 0xd2, 0xeb ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "lsh r8, 0xebd29288" + - + input: + bytes: [ 0x65, 0xe8, 0x97, 0xe1, 0x87, 0xbe, 0x8f, 0xf8 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jsgt r8, 0xf88fbe87, +0xe197" + - + input: + bytes: [ 0x67, 0x00, 0xd7, 0xc0, 0x05, 0xb0, 0xf6, 0x74 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "lsh64 r0, 0x74f6b005" + - + input: + bytes: [ 0x69, 0x14, 0xc7, 0x8e, 0x0b, 0xc1, 0xad, 0x69 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxh r4, [r1+0x8ec7]" + - + input: + bytes: [ 0x6a, 0xb5, 0xbc, 0x8c, 0x4f, 0x5c, 0x94, 0x01 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "sth [r5+0x8cbc], 0x1945c4f" + - + input: + bytes: [ 0x6b, 0x34, 0x58, 0xf5, 0xc8, 0x27, 0x9e, 0x14 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "stxh [r4+0xf558], r3" + - + input: + bytes: [ 0x6c, 0x21, 0x10, 0x48, 0x01, 0x3e, 0x6e, 0xf8 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "lsh r1, r2" + - + input: + bytes: [ 0x6d, 0x38, 0x69, 0xe3, 0xc9, 0xac, 0x3c, 0xdb ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jsgt r8, r3, +0xe369" + - + input: + bytes: [ 0x6f, 0x64, 0x49, 0xd6, 0x07, 0xa9, 0x93, 0x13 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "lsh64 r4, r6" + - + input: + bytes: [ 0x71, 0xa0, 0xeb, 0xfb, 0x3d, 0x6b, 0x58, 0x45 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxb r0, [r10+0xfbeb]" + - + input: + bytes: [ 0x72, 0xe2, 0xc1, 0x1b, 0x25, 0x2f, 0x4a, 0xdc ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "stb [r2+0x1bc1], 0xdc4a2f25" + - + input: + bytes: [ 0x73, 0x44, 0x09, 0x0f, 0xc1, 0x07, 0xa8, 0xf4 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "stxb [r4+0xf09], r4" + - + input: + bytes: [ 0x74, 0xe0, 0x23, 0x23, 0x2f, 0x04, 0x15, 0x35 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "rsh r0, 0x3515042f" + - + input: + bytes: [ 0x75, 0x04, 0x8e, 0x18, 0x6a, 0xcc, 0x3c, 0x09 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jsge r4, 0x93ccc6a, +0x188e" + - + input: + bytes: [ 0x77, 0x09, 0x3a, 0xa7, 0x3c, 0x6e, 0xfa, 0x23 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "rsh64 r9, 0x23fa6e3c" + - + input: + bytes: [ 0x79, 0xa9, 0x5c, 0x7b, 0x16, 0x1f, 0xfb, 0x01 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxdw r9, [r10+0x7b5c]" + - + input: + bytes: [ 0x7a, 0xd8, 0x6b, 0x04, 0x76, 0xf0, 0x51, 0x75 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "stdw [r8+0x46b], 0x7551f076" + - + input: + bytes: [ 0x7b, 0x72, 0x0f, 0x30, 0x51, 0x78, 0xd2, 0x9a ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "stxdw [r2+0x300f], r7" + - + input: + bytes: [ 0x7c, 0x13, 0x12, 0x73, 0x5a, 0x20, 0x65, 0xdb ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "rsh r3, r1" + - + input: + bytes: [ 0x7d, 0x58, 0x52, 0x01, 0x90, 0xf9, 0x30, 0x9a ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jsge r8, r5, +0x152" + - + input: + bytes: [ 0x7f, 0x98, 0xea, 0xff, 0xcf, 0x5d, 0x5f, 0xa3 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "rsh64 r8, r9" + - + input: + bytes: [ 0x84, 0x14, 0xd4, 0xaf, 0x60, 0xe1, 0x41, 0x18 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "neg r4" + - + input: + bytes: [ 0x85, 0xd3, 0xa5, 0xe2, 0x83, 0x3d, 0xbd, 0x5d ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "call 0x5dbd3d83" + - + input: + bytes: [ 0x87, 0xf5, 0x2b, 0xbe, 0xa9, 0xc7, 0x31, 0xa3 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "neg64 r5" + - + input: + bytes: [ 0x94, 0x39, 0x0d, 0xdc, 0x0b, 0xd2, 0xd1, 0xc9 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mod r9, 0xc9d1d20b" + - + input: + bytes: [ 0x95, 0xf2, 0xd1, 0x83, 0x53, 0xa9, 0x09, 0x9f ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "exit" + - + input: + bytes: [ 0x97, 0xc8, 0xa6, 0x75, 0xd2, 0x09, 0x98, 0x09 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mod64 r8, 0x99809d2" + - + input: + bytes: [ 0x9c, 0x96, 0xe7, 0x16, 0x0f, 0x69, 0x13, 0x90 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mod r6, r9" + - + input: + bytes: [ 0x9f, 0x35, 0x5a, 0x59, 0xd6, 0x70, 0xd9, 0x5e ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mod64 r5, r3" + - + input: + bytes: [ 0xa4, 0x89, 0x6b, 0x5f, 0x0d, 0xbf, 0x90, 0xf7 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "xor r9, 0xf790bf0d" + - + input: + bytes: [ 0xa5, 0xd4, 0xef, 0x79, 0xd3, 0xbb, 0xde, 0xfd ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jlt r4, 0xfddebbd3, +0x79ef" + - + input: + bytes: [ 0xa7, 0x80, 0x8b, 0x18, 0xa9, 0x34, 0x74, 0x45 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "xor64 r0, 0x457434a9" + - + input: + bytes: [ 0xac, 0x36, 0x16, 0xe0, 0x0f, 0x52, 0x30, 0x65 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "xor r6, r3" + - + input: + bytes: [ 0xaf, 0x41, 0x04, 0xc2, 0x2e, 0xc9, 0xf7, 0x84 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "xor64 r1, r4" + - + input: + bytes: [ 0xb4, 0xa1, 0x9c, 0x78, 0xf9, 0x3f, 0x77, 0x1f ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mov r1, 0x1f773ff9" + - + input: + bytes: [ 0xb5, 0x92, 0x5d, 0x5a, 0x49, 0x33, 0xfc, 0x33 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jle r2, 0x33fc3349, +0x5a5d" + - + input: + bytes: [ 0xb7, 0x70, 0x59, 0x4d, 0x5b, 0x52, 0x2a, 0x99 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mov64 r0, 0x992a525b" + - + input: + bytes: [ 0xbc, 0x72, 0x3e, 0x6c, 0xc9, 0x8a, 0x56, 0xd6 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mov r2, r7" + - + input: + bytes: [ 0xbd, 0x19, 0x80, 0xe8, 0x29, 0x85, 0xcf, 0x51 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jle r9, r1, +0xe880" + - + input: + bytes: [ 0xbf, 0x86, 0x55, 0x58, 0xb2, 0x6d, 0x14, 0x03 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "mov64 r6, r8" + - + input: + bytes: [ 0xc4, 0xb6, 0xe2, 0xe0, 0x7c, 0x68, 0xc5, 0x2b ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "arsh r6, 0x2bc5687c" + - + input: + bytes: [ 0xc5, 0xf2, 0xeb, 0xe4, 0xba, 0xc0, 0xce, 0x4f ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jslt r2, 0x4fcec0ba, +0xe4eb" + - + input: + bytes: [ 0xc7, 0xe8, 0xba, 0xff, 0x1f, 0xef, 0xc0, 0x88 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "arsh64 r8, 0x88c0ef1f" + - + input: + bytes: [ 0xcc, 0x38, 0xc5, 0x37, 0x13, 0xc0, 0xe7, 0x27 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "arsh r8, r3" + - + input: + bytes: [ 0xcd, 0x90, 0x67, 0x88, 0x6b, 0xd0, 0x27, 0xf4 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jslt r0, r9, +0x8867" + - + input: + bytes: [ 0xcf, 0x82, 0xe1, 0xcd, 0xbe, 0xc3, 0x2d, 0x7c ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "arsh64 r2, r8" + - + input: + bytes: [ 0xd4, 0x53, 0x3f, 0x0c, 0x40, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "le64 r3" + - + input: + bytes: [ 0xd5, 0xe9, 0xf6, 0xb2, 0x50, 0xfd, 0xb0, 0xe5 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jsle r9, 0xe5b0fd50, +0xb2f6" + - + input: + bytes: [ 0xdc, 0xb2, 0xa3, 0x50, 0x20, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "be32 r2" + - + input: + bytes: [ 0xdd, 0x95, 0xbf, 0xb1, 0xf2, 0x5f, 0x7b, 0xc4 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "jsle r5, r9, +0xb1bf" + - + input: + bytes: [ 0x8d, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ] + expected: + insns: + - + asm_text: "callx r2" diff --git a/tests/MC/BPF/extended-be.yaml b/tests/MC/BPF/extended-be.yaml new file mode 100644 index 0000000000..423ff70ad3 --- /dev/null +++ b/tests/MC/BPF/extended-be.yaml @@ -0,0 +1,136 @@ +test_cases: + - + input: + bytes: [ 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldb [0x0]" + - + input: + bytes: [ 0x28, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldh [0xfa0000ff]" + - + input: + bytes: [ 0x40, 0x10, 0x00, 0x00, 0xcc, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldw [r1+0xcc000000]" + - + input: + bytes: [ 0x18, 0x00, 0x00, 0x00, 0x0c, 0xb0, 0xce, 0xfa, 0x00, 0x00, 0x00, 0x00, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lddw r0, 0xefbeadde0cb0cefa" + - + input: + bytes: [ 0x71, 0x13, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxb r3, [r1+0x1100]" + - + input: + bytes: [ 0x94, 0x09, 0x00, 0x00, 0x37, 0x13, 0x03, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mod r9, 0x37130300" + - + input: + bytes: [ 0x84, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "neg r3" + - + input: + bytes: [ 0x87, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "neg64 r0" + - + input: + bytes: [ 0xdc, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "be32 r2" + - + input: + bytes: [ 0x05, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "jmp +0x800" + - + input: + bytes: [ 0xdd, 0x35, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "jsle r5, r3, +0x3000" + - + input: + bytes: [ 0xa5, 0x35, 0x30, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "jlt r5, 0x10000000, +0x3000" + - + input: + bytes: [ 0xc3, 0x12, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xaddw [r2+0x10], r1" + - + input: + bytes: [ 0xdb, 0xa9, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xadddw [r9+0x1], r10" + - + input: + bytes: [ 0x8d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_BPF" + options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "callx r2" diff --git a/tests/MC/HPPA/alu11.s.yaml b/tests/MC/HPPA/alu11.s.yaml new file mode 100644 index 0000000000..f34e0c3809 --- /dev/null +++ b/tests/MC/HPPA/alu11.s.yaml @@ -0,0 +1,3889 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x41, 0x06, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "add r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x26, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "add,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x46, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "add,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x66, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "add,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x86, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "add,nuv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xa6, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "add,znv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xc6, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "add,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xe6, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "add,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x16, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "add,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x36, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "add,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x56, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "add,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x76, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "add,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x96, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "add,uv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xb6, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "add,vnz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xd6, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "add,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xf6, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "add,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addo r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x2e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addo,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x4e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addo,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x6e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addo,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x8e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addo,nuv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xae, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addo,znv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xce, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addo,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xee, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addo,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x1e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addo,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x3e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addo,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x5e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addo,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x7e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addo,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x9e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addo,uv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xbe, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addo,vnz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xde, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addo,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xfe, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addo,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x07, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addc r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x27, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addc,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x47, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addc,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x67, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addc,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x87, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addc,nuv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xa7, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addc,znv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xc7, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addc,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xe7, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addc,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x17, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addc,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x37, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addc,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x57, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addc,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x77, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addc,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x97, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addc,uv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xb7, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addc,vnz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xd7, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addc,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xf7, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addc,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0f, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addco r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x2f, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addco,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x4f, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addco,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x6f, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addco,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x8f, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addco,nuv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xaf, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addco,znv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xcf, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addco,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xef, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addco,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x1f, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addco,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x3f, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addco,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x5f, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addco,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x7f, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addco,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x9f, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addco,uv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xbf, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addco,vnz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xdf, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addco,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xff, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addco,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x06, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1add r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x26, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1add,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x46, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1add,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x66, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1add,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x86, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1add,nuv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xa6, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1add,znv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xc6, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1add,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xe6, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1add,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x16, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1add,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x36, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1add,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x56, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1add,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x76, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1add,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x96, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1add,uv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xb6, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1add,vnz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xd6, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1add,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xf6, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1add,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0e, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addo r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x2e, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addo,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x4e, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addo,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x6e, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addo,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x8e, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addo,nuv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xae, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addo,znv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xce, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addo,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xee, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addo,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x1e, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addo,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x3e, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addo,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x5e, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addo,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x7e, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addo,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x9e, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addo,uv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xbe, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addo,vnz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xde, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addo,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xfe, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addo,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x06, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2add r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x26, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2add,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x46, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2add,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x66, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2add,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x86, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2add,nuv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xa6, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2add,znv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xc6, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2add,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xe6, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2add,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x16, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2add,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x36, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2add,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x56, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2add,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x76, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2add,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x96, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2add,uv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xb6, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2add,vnz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xd6, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2add,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xf6, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2add,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0e, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addo r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x2e, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addo,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x4e, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addo,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x6e, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addo,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x8e, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addo,nuv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xae, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addo,znv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xce, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addo,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xee, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addo,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x1e, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addo,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x3e, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addo,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x5e, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addo,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x7e, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addo,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x9e, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addo,uv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xbe, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addo,vnz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xde, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addo,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xfe, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addo,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x06, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3add r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x26, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3add r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x46, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3add r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x66, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3add r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x86, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3add r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xa6, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3add r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xc6, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3add r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xe6, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3add r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x16, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3add r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x36, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3add r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x56, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3add r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x76, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3add r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x96, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3add r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xb6, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3add r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xd6, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3add r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xf6, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3add r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0e, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addo r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x2e, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addo,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x4e, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addo,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x6e, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addo,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x8e, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addo,nuv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xae, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addo,znv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xce, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addo,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xee, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addo,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x1e, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addo,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x3e, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addo,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x5e, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addo,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x7e, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addo,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x9e, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addo,uv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xbe, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addo,vnz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xde, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addo,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xfe, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addo,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x04, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sub r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x24, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sub,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x44, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sub,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x64, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sub,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x84, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sub,<< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xa4, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sub,<<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xc4, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sub,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xe4, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sub,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x14, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sub,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x34, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sub,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x54, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sub,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x74, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sub,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x94, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sub,>>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xb4, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sub,>> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xd4, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sub,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xf4, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sub,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0c, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subo r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x2c, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subo,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x4c, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subo,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x6c, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subo,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x8c, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subo,<< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xac, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subo,<<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xcc, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subo,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xec, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subo,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x1c, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subo,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x3c, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subo,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x5c, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subo,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x7c, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subo,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x9c, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subo,>>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xbc, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subo,>> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xdc, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subo,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xfc, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subo,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x04, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subt r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x24, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subt,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x44, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subt,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x64, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subt,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x84, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subt,<< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xa4, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subt,<<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xc4, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subt,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xe4, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subt,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x14, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subt,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x34, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subt,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x54, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subt,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x74, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subt,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x94, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subt,>>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xb4, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subt,>> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xd4, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subt,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xf4, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subt,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0c, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subto r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x2c, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subto,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x4c, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subto,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x6c, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subto,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x8c, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subto,<< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xac, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subto,<<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xcc, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subto,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xec, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subto,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x1c, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subto,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x3c, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subto,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x5c, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subto,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x7c, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subto,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x9c, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subto,>>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xbc, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subto,>> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xdc, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subto,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xfc, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subto,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x05, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subb r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x25, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subb,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x45, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subb,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x65, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subb,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x85, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subb,<< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xa5, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subb,<<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xc5, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subb,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xe5, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subb,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x15, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subb,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x35, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subb,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x55, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subb,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x75, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subb,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x95, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subb,>>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xb5, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subb,>> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xd5, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subb,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xf5, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subb,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0d, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subbo r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x2d, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subbo,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x4d, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subbo,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x6d, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subbo,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x8d, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subbo,<< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xad, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subbo,<<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xcd, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subbo,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xed, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subbo,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x1d, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subbo,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x3d, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subbo,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x5d, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subbo,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x7d, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subbo,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x9d, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subbo,>>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xbd, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subbo,>> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xdd, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subbo,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xfd, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subbo,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x04, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ds r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x24, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ds,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x44, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ds,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x64, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ds,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x84, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ds,<< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xa4, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ds,<<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xc4, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ds,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xe4, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ds,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x14, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ds,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x34, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ds,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x54, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ds,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x74, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ds,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x94, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ds,>>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xb4, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ds,>> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xd4, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ds,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xf4, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ds,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x00, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "andcm r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x20, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "andcm,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x40, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "andcm,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x60, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "andcm,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xe0, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "andcm,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x10, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "andcm,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x30, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "andcm,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x50, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "andcm,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x70, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "andcm,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xf0, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "andcm,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x02, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "and r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x22, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "and,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x42, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "and,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x62, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "and,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xe2, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "and,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x12, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "and,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x32, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "and,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x52, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "and,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x72, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "and,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xf2, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "and,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x02, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "or r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x22, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "or,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x42, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "or,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x62, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "or,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xe2, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "or,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x12, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "or,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x32, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "or,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x52, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "or,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x72, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "or,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xf2, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "or,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x02, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "xor r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x22, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "xor,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x42, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "xor,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x62, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "xor,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xe2, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "xor,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x12, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "xor,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x32, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "xor,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x52, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "xor,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x72, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "xor,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xf2, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "xor,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x03, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uxor r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x23, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uxor,swz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x43, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uxor,sbz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x63, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uxor,shz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x13, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uxor,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x33, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uxor,nwz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x53, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uxor,nbz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x73, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uxor,nhz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x08, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comclr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x28, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comclr,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x48, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comclr,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x68, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comclr,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x88, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comclr,<< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xa8, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comclr,<<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xc8, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comclr,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xe8, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comclr,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x18, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comclr,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x38, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comclr,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x58, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comclr,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x78, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comclr,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x98, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comclr,>>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xb8, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comclr,>> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xd8, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comclr,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xf8, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comclr,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x09, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uaddcm r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x29, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uaddcm,swz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x49, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uaddcm,sbz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x69, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uaddcm,shz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x19, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uaddcm,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x39, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uaddcm,nwz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x59, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uaddcm,nbz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x79, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uaddcm,nhz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x09, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uaddcmt r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x29, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uaddcmt,swz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x49, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uaddcmt,sbz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x69, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uaddcmt,shz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x19, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uaddcmt,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x39, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uaddcmt,nwz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x59, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uaddcmt,nbz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x79, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "uaddcmt,nhz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0a, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addl r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x2a, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addl,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x4a, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addl,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x6a, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addl,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x8a, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addl,nuv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xaa, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addl,znv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xca, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addl,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xea, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addl,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x1a, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addl,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x3a, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addl,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x5a, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addl,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x7a, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addl,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x9a, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addl,uv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xba, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addl,vnz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xda, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addl,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xfa, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addl,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0a, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addl r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x2a, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addl,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x4a, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addl,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x6a, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addl,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x8a, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addl,nuv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xaa, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addl,znv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xca, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addl,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xea, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addl,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x1a, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addl,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x3a, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addl,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x5a, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addl,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x7a, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addl,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x9a, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addl,uv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xba, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addl,vnz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xda, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addl,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xfa, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh1addl,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0a, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addl r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x2a, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addl,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x4a, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addl,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x6a, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addl,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x8a, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addl,nuv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xaa, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addl,znv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xca, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addl,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xea, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addl,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x1a, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addl,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x3a, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addl,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x5a, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addl,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x7a, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addl,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x9a, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addl,uv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xba, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addl,vnz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xda, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addl,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xfa, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh2addl,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0a, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addl r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x2a, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addl,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x4a, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addl,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x6a, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addl,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x8a, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addl,nuv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xaa, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addl,znv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xca, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addl,sv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xea, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addl,od r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x1a, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addl,tr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x3a, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addl,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x5a, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addl,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x7a, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addl,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x9a, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addl,uv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xba, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addl,vnz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xda, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addl,nsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xfa, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sh3addl,ev r1,rp,r3" + - + input: + bytes: [ 0x08, 0x20, 0x0b, 0x82 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "dcor r1,rp" + - + input: + bytes: [ 0x08, 0x20, 0x2b, 0x82 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "dcor,swz r1,rp" + - + input: + bytes: [ 0x08, 0x20, 0x4b, 0x82 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "dcor,sbz r1,rp" + - + input: + bytes: [ 0x08, 0x20, 0x6b, 0x82 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "dcor,shz r1,rp" + - + input: + bytes: [ 0x08, 0x20, 0x1b, 0x82 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "dcor,tr r1,rp" + - + input: + bytes: [ 0x08, 0x20, 0x3b, 0x82 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "dcor,nwz r1,rp" + - + input: + bytes: [ 0x08, 0x20, 0x5b, 0x82 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "dcor,nbz r1,rp" + - + input: + bytes: [ 0x08, 0x20, 0x7b, 0x82 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "dcor,nhz r1,rp" + - + input: + bytes: [ 0x08, 0x20, 0x0b, 0xc2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "idcor r1,rp" + - + input: + bytes: [ 0x08, 0x20, 0x2b, 0xc2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "idcor,swz r1,rp" + - + input: + bytes: [ 0x08, 0x20, 0x4b, 0xc2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "idcor,sbz r1,rp" + - + input: + bytes: [ 0x08, 0x20, 0x6b, 0xc2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "idcor,shz r1,rp" + - + input: + bytes: [ 0x08, 0x20, 0x1b, 0xc2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "idcor,tr r1,rp" + - + input: + bytes: [ 0x08, 0x20, 0x3b, 0xc2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "idcor,nwz r1,rp" + - + input: + bytes: [ 0x08, 0x20, 0x5b, 0xc2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "idcor,nbz r1,rp" + - + input: + bytes: [ 0x08, 0x20, 0x7b, 0xc2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "idcor,nhz r1,rp" diff --git a/tests/MC/HPPA/arith_imm11.s.yaml b/tests/MC/HPPA/arith_imm11.s.yaml new file mode 100644 index 0000000000..708aca183a --- /dev/null +++ b/tests/MC/HPPA/arith_imm11.s.yaml @@ -0,0 +1,865 @@ +test_cases: + - + input: + bytes: [ 0xb4, 0x22, 0x00, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addi 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x20, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addi,= 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x40, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addi,< 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x60, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addi,<= 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x80, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addi,nuv 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0xa0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addi,znv 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0xc0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addi,sv 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0xe0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addi,od 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x10, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addi,tr 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x30, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addi,<> 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x50, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addi,>= 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x70, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addi,> 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x90, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addi,uv 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0xb0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addi,vnz 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0xd0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addi,nsv 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0xf0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addi,ev 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x00, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addit 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x20, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addit,= 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x40, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addit,< 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x60, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addit,<= 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x80, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addit,nuv 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0xa0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addit,znv 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0xc0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addit,sv 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0xe0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addit,od 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x10, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addit,tr 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x30, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addit,<> 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x50, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addit,>= 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x70, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addit,> 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x90, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addit,uv 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0xb0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addit,vnz 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0xd0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addit,nsv 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0xf0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addit,ev 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x00, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subi 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x20, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subi,= 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x40, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subi,< 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x60, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subi,<= 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x80, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subi,<< 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0xa0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subi,<<= 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0xc0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subi,sv 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0xe0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subi,od 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x10, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subi,tr 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x30, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subi,<> 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x50, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subi,>= 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x70, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subi,> 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x90, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subi,>>= 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0xb0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subi,>> 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0xd0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subi,nsv 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0xf0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subi,ev 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x08, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addio 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x28, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addio,= 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x48, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addio,< 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x68, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addio,<= 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x88, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addio,nuv 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0xa8, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addio,znv 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0xc8, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addio,sv 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0xe8, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addio,od 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x18, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addio,tr 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x38, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addio,<> 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x58, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addio,>= 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x78, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addio,> 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x98, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addio,uv 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0xb8, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addio,vnz 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0xd8, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addio,nsv 0xf,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0xf8, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addio,ev 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x08, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addito 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x28, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addito,= 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x48, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addito,< 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x68, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addito,<= 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x88, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addito,nuv 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0xa8, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addito,znv 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0xc8, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addito,sv 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0xe8, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addito,od 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x18, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addito,tr 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x38, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addito,<> 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x58, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addito,>= 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x78, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addito,> 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x98, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addito,uv 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0xb8, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addito,vnz 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0xd8, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addito,nsv 0xf,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0xf8, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addito,ev 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x08, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subio 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x28, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subio,= 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x48, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subio,< 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x68, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subio,<= 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x88, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subio,<< 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0xa8, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subio,<<= 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0xc8, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subio,sv 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0xe8, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subio,od 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x18, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subio,tr 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x38, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subio,<> 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x58, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subio,>= 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x78, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subio,> 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x98, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subio,>>= 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0xb8, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subio,>> 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0xd8, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subio,nsv 0xf,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0xf8, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "subio,ev 0xf,r1,rp" diff --git a/tests/MC/HPPA/assist20.s.yaml b/tests/MC/HPPA/assist20.s.yaml new file mode 100644 index 0000000000..95d83df064 --- /dev/null +++ b/tests/MC/HPPA/assist20.s.yaml @@ -0,0 +1,280 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x00, 0x00, 0x61 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "spop0,1,1,n" + - + input: + bytes: [ 0x10, 0x00, 0x0a, 0x61 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "spop1,1,1,n r1" + - + input: + bytes: [ 0x10, 0x20, 0x04, 0x61 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "spop2,1,1,n r1" + - + input: + bytes: [ 0x10, 0x41, 0x06, 0x61 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "spop3,1,1,n r1,rp" + - + input: + bytes: [ 0x30, 0x00, 0x01, 0x61 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "copr,5,1,n" + - + input: + bytes: [ 0x2c, 0x5e, 0x59, 0x41 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cldd,5,sl 0xf(sr1,rp),r1" + - + input: + bytes: [ 0x2c, 0x5e, 0x79, 0x61 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cldd,5,mb,sl 0xf(sr1,rp),r1" + - + input: + bytes: [ 0x2c, 0x5e, 0x59, 0x61 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cldd,5,ma,sl 0xf(sr1,rp),r1" + - + input: + bytes: [ 0x2c, 0x41, 0x49, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cldd,5,sl 2(sr1,rp),r3" + - + input: + bytes: [ 0x2c, 0x41, 0x69, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cldd,5,s,sl 2(sr1,rp),r3" + - + input: + bytes: [ 0x2c, 0x41, 0x69, 0x63 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cldd,5,sm,sl 2(sr1,rp),r3" + - + input: + bytes: [ 0x2c, 0x41, 0x49, 0x63 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cldd,5,m,sl 2(sr1,rp),r3" + - + input: + bytes: [ 0x24, 0x5e, 0x59, 0x41 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cldw,5,sl 0xf(sr1,rp),r1" + - + input: + bytes: [ 0x24, 0x5e, 0x79, 0x61 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cldw,5,mb,sl 0xf(sr1,rp),r1" + - + input: + bytes: [ 0x24, 0x5e, 0x59, 0x61 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cldw,5,ma,sl 0xf(sr1,rp),r1" + - + input: + bytes: [ 0x24, 0x41, 0x49, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cldw,5,sl r1(sr1,rp),r3" + - + input: + bytes: [ 0x24, 0x41, 0x69, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cldw,5,s,sl r1(sr1,rp),r3" + - + input: + bytes: [ 0x24, 0x41, 0x69, 0x63 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cldw,5,sm,sl r1(sr1,rp),r3" + - + input: + bytes: [ 0x24, 0x41, 0x49, 0x63 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cldw,5,m,sl r1(sr1,rp),r3" + - + input: + bytes: [ 0x2c, 0x5e, 0x17, 0x41 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cstd,5,bc r1,0xf(rp)" + - + input: + bytes: [ 0x2c, 0x5e, 0x37, 0x61 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cstd,5,mb,bc r1,0xf(rp)" + - + input: + bytes: [ 0x2c, 0x5e, 0x17, 0x61 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cstd,5,ma,bc r1,0xf(rp)" + - + input: + bytes: [ 0x2c, 0x43, 0x07, 0x41 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cstd,5,bc r1,r3(rp)" + - + input: + bytes: [ 0x2c, 0x43, 0x27, 0x41 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cstd,5,s,bc r1,r3(rp)" + - + input: + bytes: [ 0x2c, 0x43, 0x27, 0x61 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cstd,5,sm,bc r1,r3(rp)" + - + input: + bytes: [ 0x24, 0x5e, 0x17, 0x41 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cstw,5,bc r1,0xf(rp)" + - + input: + bytes: [ 0x24, 0x5e, 0x37, 0x61 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cstw,5,mb,bc r1,0xf(rp)" + - + input: + bytes: [ 0x24, 0x5e, 0x17, 0x61 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cstw,5,ma,bc r1,0xf(rp)" + - + input: + bytes: [ 0x24, 0x43, 0x07, 0x41 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cstw,5,bc r1,r3(rp)" + - + input: + bytes: [ 0x24, 0x43, 0x27, 0x41 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cstw,5,s,bc r1,r3(rp)" + - + input: + bytes: [ 0x24, 0x43, 0x27, 0x61 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cstw,5,sm,bc r1,r3(rp)" diff --git a/tests/MC/HPPA/branch11.s.yaml b/tests/MC/HPPA/branch11.s.yaml new file mode 100644 index 0000000000..b520dcb78a --- /dev/null +++ b/tests/MC/HPPA/branch11.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0xe8, 0x3f, 0x1f, 0x75 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "bl 0xffffffffffffffc0,r1" + - + input: + bytes: [ 0xe8, 0x3f, 0x1f, 0x6f ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "bl,n 0xffffffffffffffbc,r1" + - + input: + bytes: [ 0xe8, 0x41, 0x40, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "blr r1,rp" + - + input: + bytes: [ 0xe8, 0x41, 0x40, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "blr,n r1,rp" + - + input: + bytes: [ 0xe8, 0x41, 0xc0, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "bv r1(rp)" + - + input: + bytes: [ 0xe8, 0x41, 0xc0, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "bv,n r1(rp)" + - + input: + bytes: [ 0xe8, 0x5f, 0x3f, 0x45 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "gate 0xffffffffffffffa8,rp" + - + input: + bytes: [ 0xe8, 0x5f, 0x3f, 0x3f ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "gate,n 0xffffffffffffffa4,rp" diff --git a/tests/MC/HPPA/branch20.s.yaml b/tests/MC/HPPA/branch20.s.yaml new file mode 100644 index 0000000000..603b6b5ca9 --- /dev/null +++ b/tests/MC/HPPA/branch20.s.yaml @@ -0,0 +1,379 @@ +test_cases: + - + input: + bytes: [ 0xeb, 0xff, 0xb8, 0x9d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "b,l 0xfffffffffffffc54,r31" + - + input: + bytes: [ 0xeb, 0xff, 0xb8, 0x97 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "b,l,n 0xfffffffffffffc50,r31" + - + input: + bytes: [ 0xeb, 0x9f, 0x38, 0x8d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "b,gate 0xfffffffffffffc4c,ret0" + - + input: + bytes: [ 0xeb, 0x9f, 0x38, 0x87 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "b,gate,n 0xfffffffffffffc48,ret0" + - + input: + bytes: [ 0xeb, 0xff, 0x98, 0x7d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "b,l,push 0xfffffffffffffc44,r31" + - + input: + bytes: [ 0xeb, 0xff, 0x98, 0x77 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "b,l,push,n 0xfffffffffffffc40,r31" + - + input: + bytes: [ 0xe8, 0x41, 0x40, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "blr r1,rp" + - + input: + bytes: [ 0xe8, 0x41, 0x40, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "blr,n r1,rp" + - + input: + bytes: [ 0xe8, 0x41, 0xc0, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "bv r1(rp)" + - + input: + bytes: [ 0xe8, 0x41, 0xc0, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "bv,n r1(rp)" + - + input: + bytes: [ 0xe0, 0x20, 0x40, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "be 0(sr1,r1)" + - + input: + bytes: [ 0xe0, 0x20, 0x40, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "be,n 0(sr1,r1)" + - + input: + bytes: [ 0xe4, 0x20, 0x40, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "be,l 0(sr1,r1),sr0,r31" + - + input: + bytes: [ 0xe4, 0x20, 0x40, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "be,l,n 0(sr1,r1),sr0,r31" + - + input: + bytes: [ 0xe8, 0x40, 0xd0, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "bve (rp)" + - + input: + bytes: [ 0xe8, 0x40, 0xd0, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "bve,n (rp)" + - + input: + bytes: [ 0xe8, 0x40, 0xd0, 0x01 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "bve,pop (rp)" + - + input: + bytes: [ 0xe8, 0x40, 0xd0, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "bve,pop,n (rp)" + - + input: + bytes: [ 0xe8, 0x20, 0xf0, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "bve,l (r1),rp" + - + input: + bytes: [ 0xe8, 0x20, 0xf0, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "bve,l,n (r1),rp" + - + input: + bytes: [ 0xe8, 0x20, 0xf0, 0x01 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "bve,l,push (r1),rp" + - + input: + bytes: [ 0xe8, 0x20, 0xf0, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "bve,l,push,n (r1),rp" + - + input: + bytes: [ 0xa0, 0x41, 0x17, 0xed ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "addb r1,rp,0xfffffffffffffbfc" + - + input: + bytes: [ 0xa0, 0x41, 0x37, 0xe5 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "addb,= r1,rp,0xfffffffffffffbf8" + - + input: + bytes: [ 0xa0, 0x41, 0x37, 0xdf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "addb,=,n r1,rp,0xfffffffffffffbf4" + - + input: + bytes: [ 0xa4, 0x5e, 0x17, 0xd5 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "addib 0xf,rp,0xfffffffffffffbf0" + - + input: + bytes: [ 0xa4, 0x5e, 0x37, 0xcd ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "addib,= 0xf,rp,0xfffffffffffffbec" + - + input: + bytes: [ 0xa4, 0x5e, 0x37, 0xc7 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "addib,=,n 0xf,rp,0xfffffffffffffbe8" + - + input: + bytes: [ 0xc5, 0xe1, 0xd7, 0xbd ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "bb,>= r1,0xf,0xfffffffffffffbe4" + - + input: + bytes: [ 0xc5, 0xe1, 0xd7, 0xb7 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "bb,>=,n r1,0xf,0xfffffffffffffbe0" + - + input: + bytes: [ 0x80, 0x41, 0x17, 0xad ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cmpb r1,rp,0xfffffffffffffbdc" + - + input: + bytes: [ 0x80, 0x41, 0x37, 0xa5 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cmpb,= r1,rp,0xfffffffffffffbd8" + - + input: + bytes: [ 0x80, 0x41, 0x37, 0x9f ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cmpb,=,n r1,rp,0xfffffffffffffbd4" + - + input: + bytes: [ 0x84, 0x5e, 0x17, 0x95 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cmpib 0xf,rp,0xfffffffffffffbd0" + - + input: + bytes: [ 0x84, 0x5e, 0x37, 0x8d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cmpib,= 0xf,rp,0xfffffffffffffbcc" + - + input: + bytes: [ 0x84, 0x5e, 0x37, 0x87 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cmpib,=,n 0xf,rp,0xfffffffffffffbc8" + - + input: + bytes: [ 0xc8, 0x41, 0x17, 0x7d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "movb r1,rp,0xfffffffffffffbc4" + - + input: + bytes: [ 0xc8, 0x41, 0x37, 0x75 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "movb,= r1,rp,0xfffffffffffffbc0" + - + input: + bytes: [ 0xc8, 0x41, 0x37, 0x6f ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "movb,=,n r1,rp,0xfffffffffffffbbc" + - + input: + bytes: [ 0xcc, 0x5e, 0x17, 0x65 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "movib 0xf,rp,0xfffffffffffffbb8" + - + input: + bytes: [ 0xcc, 0x5e, 0x37, 0x5d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "movib,= 0xf,rp,0xfffffffffffffbb4" + - + input: + bytes: [ 0xcc, 0x5e, 0x37, 0x57 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "movib,=,n 0xf,rp,0xfffffffffffffbb0" diff --git a/tests/MC/HPPA/computation20.s.yaml b/tests/MC/HPPA/computation20.s.yaml new file mode 100644 index 0000000000..65bec6f04d --- /dev/null +++ b/tests/MC/HPPA/computation20.s.yaml @@ -0,0 +1,559 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x41, 0x66, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "add,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x07, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "add,c r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x57, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "add,c,>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x07, 0x23 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "add,dc,* r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x27, 0x23 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "add,dc,*= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0a, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "add,l r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x4a, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "add,l,< r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "add,tsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x7e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "add,tsv,> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0f, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "add,c,tsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x3f, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "add,c,tsv,<> r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0f, 0x23 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "add,dc,tsv,* r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x5f, 0x23 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "add,dc,tsv,*>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x06, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "shladd r1,3,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0a, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "shladd,l r1,3,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0e, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "shladd,tsv r1,3,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xce, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "shladd,tsv,sv r1,3,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x04, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "sub r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x04, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "sub,tc r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x05, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "sub,b r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0c, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "sub,tsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0c, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "sub,tsv,tc r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x0d, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "sub,b,tsv r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x6d, 0x23 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "sub,db,tsv,*<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x02, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "or r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x22, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "or,= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x02, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "xor r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x62, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "xor,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x02, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "and r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x62, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "and,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x00, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "andcm r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x60, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "andcm,<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x09, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "uaddcm r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x49, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "uaddcm,sbz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x09, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "uaddcm,tc r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x03, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "uxor r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x43, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "uxor,sbz r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x04, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ds r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0xa4, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ds,<<= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x08, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cmpclr r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x98, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cmpclr,>>= r1,rp,r3" + - + input: + bytes: [ 0x08, 0x20, 0x0b, 0x82 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "dcor r1,rp" + - + input: + bytes: [ 0x08, 0x20, 0x0b, 0xc2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "dcor,i r1,rp" + - + input: + bytes: [ 0x08, 0x20, 0x4b, 0xc2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "dcor,i,sbz r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x01, 0xbc ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "addi 0xde,r1,rp" + - + input: + bytes: [ 0xb4, 0x22, 0x09, 0xbc ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "addi,tsv 0xde,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x01, 0xbc ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "addi,tc 0xde,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x09, 0xbc ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "addi,tsv,tc 0xde,r1,rp" + - + input: + bytes: [ 0xb0, 0x22, 0x69, 0xbc ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "addi,tsv,tc,<= 0xde,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x01, 0xbc ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "subi 0xde,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x09, 0xbc ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "subi,tsv 0xde,r1,rp" + - + input: + bytes: [ 0x94, 0x22, 0x29, 0xbc ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "subi,tsv,= 0xde,r1,rp" + - + input: + bytes: [ 0x90, 0x43, 0x01, 0xbc ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cmpiclr 0xde,rp,r3" + - + input: + bytes: [ 0x90, 0x43, 0x91, 0xbc ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "cmpiclr,>>= 0xde,rp,r3" + - + input: + bytes: [ 0xd0, 0x41, 0x0f, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "shrpd,* r1,rp,3,r3" + - + input: + bytes: [ 0xd0, 0x41, 0x4f, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "shrpd,*< r1,rp,3,r3" + - + input: + bytes: [ 0xd0, 0x41, 0x0b, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "shrpw r1,rp,3,r3" + - + input: + bytes: [ 0xd0, 0x41, 0x4b, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "shrpw,< r1,rp,3,r3" + - + input: + bytes: [ 0xd0, 0x22, 0x16, 0x1c ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "extrd,s,* r1,sar,4,rp" + - + input: + bytes: [ 0xd8, 0x22, 0x07, 0xdc ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "extrd,s,* r1,0x1e,4,rp" + - + input: + bytes: [ 0xd8, 0x22, 0x03, 0xdc ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "extrd,u,* r1,0x1e,4,rp" + - + input: + bytes: [ 0xd8, 0x22, 0xc3, 0xdc ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "extrd,u,*>= r1,0x1e,4,rp" diff --git a/tests/MC/HPPA/copr_dw11.s.yaml b/tests/MC/HPPA/copr_dw11.s.yaml new file mode 100644 index 0000000000..80ae937352 --- /dev/null +++ b/tests/MC/HPPA/copr_dw11.s.yaml @@ -0,0 +1,361 @@ +test_cases: + - + input: + bytes: [ 0x24, 0x41, 0x40, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cldwx,3 r1(sr1,rp),r3" + - + input: + bytes: [ 0x24, 0x41, 0x60, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cldwx,3,s r1(sr1,rp),r3" + - + input: + bytes: [ 0x24, 0x41, 0x40, 0xe3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cldwx,3,m r1(sr1,rp),r3" + - + input: + bytes: [ 0x24, 0x41, 0x60, 0xe3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cldwx,3,sm r1(sr1,rp),r3" + - + input: + bytes: [ 0x24, 0x41, 0x68, 0xe3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cldwx,3,sm,sl r1(sr1,rp),r3" + - + input: + bytes: [ 0x2c, 0x41, 0x40, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "clddx,3 r1(sr1,rp),r3" + - + input: + bytes: [ 0x2c, 0x41, 0x60, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "clddx,3,s r1(sr1,rp),r3" + - + input: + bytes: [ 0x2c, 0x41, 0x40, 0xe3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "clddx,3,m r1(sr1,rp),r3" + - + input: + bytes: [ 0x2c, 0x41, 0x60, 0xe3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "clddx,3,sm r1(sr1,rp),r3" + - + input: + bytes: [ 0x2c, 0x41, 0x68, 0xe3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "clddx,3,sm,sl r1(sr1,rp),r3" + - + input: + bytes: [ 0x24, 0x62, 0x42, 0xc1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstwx,3 r1,rp(sr1,r3)" + - + input: + bytes: [ 0x24, 0x62, 0x62, 0xc1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstwx,3,s r1,rp(sr1,r3)" + - + input: + bytes: [ 0x24, 0x62, 0x42, 0xe1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstwx,3,m r1,rp(sr1,r3)" + - + input: + bytes: [ 0x24, 0x62, 0x46, 0xe1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstwx,3,m,bc r1,rp(sr1,r3)" + - + input: + bytes: [ 0x24, 0x62, 0x62, 0xe1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstwx,3,sm r1,rp(sr1,r3)" + - + input: + bytes: [ 0x24, 0x62, 0x6a, 0xe1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstwx,3,sm,sl r1,rp(sr1,r3)" + - + input: + bytes: [ 0x2c, 0x62, 0x42, 0xc1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstdx,3 r1,rp(sr1,r3)" + - + input: + bytes: [ 0x2c, 0x62, 0x62, 0xc1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstdx,3,s r1,rp(sr1,r3)" + - + input: + bytes: [ 0x2c, 0x62, 0x42, 0xe1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstdx,3,m r1,rp(sr1,r3)" + - + input: + bytes: [ 0x2c, 0x62, 0x46, 0xe1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstdx,3,m,bc r1,rp(sr1,r3)" + - + input: + bytes: [ 0x2c, 0x62, 0x62, 0xe1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstdx,3,sm r1,rp(sr1,r3)" + - + input: + bytes: [ 0x2c, 0x62, 0x6a, 0xe1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstdx,3,sm,sl r1,rp(sr1,r3)" + - + input: + bytes: [ 0x24, 0x3e, 0x50, 0xc2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cldws,3 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x24, 0x3e, 0x50, 0xe2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cldws,3,ma 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x24, 0x3e, 0x70, 0xe2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cldws,3,mb 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x24, 0x3e, 0x78, 0xe2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cldws,3,mb,sl 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x2c, 0x3e, 0x50, 0xc2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cldds,3 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x2c, 0x3e, 0x50, 0xe2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cldds,3,ma 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x2c, 0x3e, 0x70, 0xe2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cldds,3,mb 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x2c, 0x3e, 0x78, 0xe2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cldds,3,mb,sl 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x24, 0x5e, 0x52, 0xc1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstws,3 r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x24, 0x5e, 0x52, 0xe1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstws,3,ma r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x24, 0x5e, 0x56, 0xe1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstws,3,ma,bc r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x24, 0x5e, 0x72, 0xe1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstws,3,mb r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x24, 0x5e, 0x7a, 0xe1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstws,3,mb,sl r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x2c, 0x5e, 0x52, 0xc1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstds,3 r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x2c, 0x5e, 0x52, 0xe1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstds,3,ma r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x2c, 0x5e, 0x56, 0xe1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstds,3,ma,bc r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x2c, 0x5e, 0x72, 0xe1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstds,3,mb r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x2c, 0x5e, 0x7a, 0xe1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "cstds,3,mb,sl r1,0xf(sr1,rp)" diff --git a/tests/MC/HPPA/float11.s.yaml b/tests/MC/HPPA/float11.s.yaml new file mode 100644 index 0000000000..d475cd21f2 --- /dev/null +++ b/tests/MC/HPPA/float11.s.yaml @@ -0,0 +1,793 @@ +test_cases: + - + input: + bytes: [ 0x30, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "copr,0,0,n" + - + input: + bytes: [ 0x30, 0x00, 0x00, 0x62 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "copr,1,2,n" + - + input: + bytes: [ 0x30, 0x20, 0x40, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcpy,sgl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0x48, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcpy,dbl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0x58, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcpy,quad fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0x60, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fabs,sgl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0x68, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fabs,dbl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0x78, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fabs,quad fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0x80, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fsqrt,sgl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0x88, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fsqrt,dbl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0x98, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fsqrt,quad fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0xa0, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "frnd,sgl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0xa8, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "frnd,dbl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0xb8, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "frnd,quad fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0x22, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvff,sgl,dbl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0x62, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvff,sgl,quad fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0x0a, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvff,dbl,sgl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0x6a, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvff,dbl,quad fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0x02, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvff,sgl,sgl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0x2a, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvff,dbl,dbl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0x7a, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvff,quad,quad fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0xa2, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvxf,sgl,dbl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0xe2, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvxf,sgl,quad fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0x8a, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvxf,dbl,sgl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0xea, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvxf,dbl,quad fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0x82, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvxf,sgl,sgl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0xaa, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvxf,dbl,dbl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x20, 0xfa, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvxf,quad,quad fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x21, 0x22, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvfx,sgl,dbl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x21, 0x62, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvfx,sgl,quad fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x21, 0x0a, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvfx,dbl,sgl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x21, 0x6a, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvfx,dbl,quad fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x21, 0x02, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvfx,sgl,sgl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x21, 0x2a, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvfx,dbl,dbl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x21, 0x7a, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvfx,quad,quad fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x21, 0xa2, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvfxt,sgl,dbl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x21, 0xe2, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvfxt,sgl,quad fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x21, 0x8a, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvfxt,dbl,sgl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x21, 0xea, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvfxt,dbl,quad fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x21, 0x82, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvfxt,sgl,sgl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x21, 0xaa, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvfxt,dbl,dbl fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x21, 0xfa, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcnvfxt,quad,quad fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,false? fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x01 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,false fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,? fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,!<=> fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x04 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,= fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x05 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,=t fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x06 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,?= fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x07 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,!<> fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x08 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,!?>= fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x09 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,< fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x0a ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,?< fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x0b ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,!>= fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x0c ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,!?> fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x0d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,<= fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x0e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,?<= fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x0f ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,!> fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x10 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,!?<= fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,> fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x12 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,?> fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x13 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,!<= fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x14 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,!?< fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x15 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,>= fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x16 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,?>= fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x17 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,!< fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x18 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,!?= fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x19 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,<> fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x1a ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,!= fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x1b ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,!=t fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x1c ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,!? fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x1d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,<=> fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,true? fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x22, 0x04, 0x1f ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fcmp,sgl,true fpe2,fpe4" + - + input: + bytes: [ 0x30, 0x00, 0x24, 0x20 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ftest" + - + input: + bytes: [ 0x30, 0x22, 0x06, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fadd,sgl fpe2,fpe4,fpe6" + - + input: + bytes: [ 0x30, 0x22, 0x0e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fadd,dbl fpe2,fpe4,fpe6" + - + input: + bytes: [ 0x30, 0x22, 0x1e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fadd,quad fpe2,fpe4,fpe6" + - + input: + bytes: [ 0x30, 0x22, 0x26, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fsub,sgl fpe2,fpe4,fpe6" + - + input: + bytes: [ 0x30, 0x22, 0x2e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fsub,dbl fpe2,fpe4,fpe6" + - + input: + bytes: [ 0x30, 0x22, 0x3e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fsub,quad fpe2,fpe4,fpe6" + - + input: + bytes: [ 0x30, 0x22, 0x46, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fmpy,sgl fpe2,fpe4,fpe6" + - + input: + bytes: [ 0x30, 0x22, 0x4e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fmpy,dbl fpe2,fpe4,fpe6" + - + input: + bytes: [ 0x30, 0x22, 0x5e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fmpy,quad fpe2,fpe4,fpe6" + - + input: + bytes: [ 0x30, 0x22, 0x66, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fdiv,sgl fpe2,fpe4,fpe6" + - + input: + bytes: [ 0x30, 0x22, 0x6e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fdiv,dbl fpe2,fpe4,fpe6" + - + input: + bytes: [ 0x30, 0x22, 0x7e, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fdiv,quad fpe2,fpe4,fpe6" + - + input: + bytes: [ 0x38, 0x22, 0x47, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "xmpyu fpe2,fpe4,fpe6" diff --git a/tests/MC/HPPA/float20.s.yaml b/tests/MC/HPPA/float20.s.yaml new file mode 100644 index 0000000000..744b03acd8 --- /dev/null +++ b/tests/MC/HPPA/float20.s.yaml @@ -0,0 +1,505 @@ +test_cases: + - + input: + bytes: [ 0x24, 0x2a, 0x10, 0x14 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fldw 5(r1),fr20" + - + input: + bytes: [ 0x24, 0x2a, 0x30, 0x34 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fldw,mb 5(r1),fr20" + - + input: + bytes: [ 0x24, 0x2a, 0x10, 0x34 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fldw,ma 5(r1),fr20" + - + input: + bytes: [ 0x24, 0x22, 0x00, 0x14 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fldw rp(r1),fr20" + - + input: + bytes: [ 0x24, 0x22, 0x20, 0x14 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fldw,s rp(r1),fr20" + - + input: + bytes: [ 0x24, 0x22, 0x20, 0x34 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fldw,sm rp(r1),fr20" + - + input: + bytes: [ 0x24, 0x22, 0x00, 0x34 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fldw,m rp(r1),fr20" + - + input: + bytes: [ 0x2c, 0x2a, 0x10, 0x14 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fldd 5(r1),fr20" + - + input: + bytes: [ 0x2c, 0x2a, 0x30, 0x34 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fldd,mb 5(r1),fr20" + - + input: + bytes: [ 0x2c, 0x2a, 0x10, 0x34 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fldd,ma 5(r1),fr20" + - + input: + bytes: [ 0x2c, 0x22, 0x00, 0x14 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fldd rp(r1),fr20" + - + input: + bytes: [ 0x2c, 0x22, 0x20, 0x14 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fldd,s rp(r1),fr20" + - + input: + bytes: [ 0x2c, 0x22, 0x20, 0x34 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fldd,sm rp(r1),fr20" + - + input: + bytes: [ 0x2c, 0x22, 0x00, 0x34 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fldd,m rp(r1),fr20" + - + input: + bytes: [ 0x24, 0x5e, 0x12, 0x14 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fstw fr20,0xf(rp)" + - + input: + bytes: [ 0x24, 0x5e, 0x32, 0x34 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fstw,mb fr20,0xf(rp)" + - + input: + bytes: [ 0x24, 0x5e, 0x12, 0x34 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fstw,ma fr20,0xf(rp)" + - + input: + bytes: [ 0x24, 0x41, 0x06, 0x14 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fstw,bc fr20,r1(rp)" + - + input: + bytes: [ 0x24, 0x41, 0x26, 0x14 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fstw,s,bc fr20,r1(rp)" + - + input: + bytes: [ 0x24, 0x41, 0x26, 0x34 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fstw,sm,bc fr20,r1(rp)" + - + input: + bytes: [ 0x24, 0x41, 0x06, 0x34 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fstw,m,bc fr20,r1(rp)" + - + input: + bytes: [ 0x2c, 0x5e, 0x12, 0x14 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fstd fr20,0xf(rp)" + - + input: + bytes: [ 0x2c, 0x5e, 0x32, 0x34 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fstd,mb fr20,0xf(rp)" + - + input: + bytes: [ 0x2c, 0x5e, 0x12, 0x34 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fstd,ma fr20,0xf(rp)" + - + input: + bytes: [ 0x2c, 0x41, 0x06, 0x14 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fstd,bc fr20,r1(rp)" + - + input: + bytes: [ 0x2c, 0x41, 0x26, 0x14 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fstd,s,bc fr20,r1(rp)" + - + input: + bytes: [ 0x2c, 0x41, 0x26, 0x34 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fstd,sm,bc fr20,r1(rp)" + - + input: + bytes: [ 0x2c, 0x41, 0x06, 0x34 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fstd,m,bc fr20,r1(rp)" + - + input: + bytes: [ 0x30, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fid" + - + input: + bytes: [ 0x32, 0x80, 0x40, 0x15 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fcpy,sgl fr20,fr21" + - + input: + bytes: [ 0x32, 0x80, 0x60, 0x15 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fabs,sgl fr20,fr21" + - + input: + bytes: [ 0x32, 0x80, 0x80, 0x15 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fsqrt,sgl fr20,fr21" + - + input: + bytes: [ 0x32, 0x80, 0xa0, 0x15 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "frnd,sgl fr20,fr21" + - + input: + bytes: [ 0x32, 0x80, 0xc0, 0x15 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fneg,sgl fr20,fr21" + - + input: + bytes: [ 0x32, 0x80, 0xe0, 0x15 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fnegabs,sgl fr20,fr21" + - + input: + bytes: [ 0x32, 0x80, 0x22, 0x15 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fcnv,sgl,dbl fr20,fr21" + - + input: + bytes: [ 0x32, 0x80, 0xa2, 0x15 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fcnv,w,dbl fr20,fr21" + - + input: + bytes: [ 0x32, 0x95, 0x04, 0x04 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fcmp,sgl,= fr20,fr21" + - + input: + bytes: [ 0x32, 0x95, 0x44, 0x04 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fcmp,sgl,= fr20,fr21,1" + - + input: + bytes: [ 0x30, 0x00, 0x64, 0x20 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ftest 1" + - + input: + bytes: [ 0x30, 0x00, 0x24, 0x21 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ftest,acc" + - + input: + bytes: [ 0x30, 0x00, 0x24, 0x25 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ftest,acc8" + - + input: + bytes: [ 0x30, 0x00, 0x24, 0x29 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ftest,acc6" + - + input: + bytes: [ 0x30, 0x00, 0x24, 0x2d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ftest,acc4" + - + input: + bytes: [ 0x30, 0x00, 0x24, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ftest,acc2" + - + input: + bytes: [ 0x30, 0x00, 0x24, 0x22 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ftest,rej" + - + input: + bytes: [ 0x30, 0x00, 0x24, 0x26 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ftest,rej8" + - + input: + bytes: [ 0x32, 0x95, 0x06, 0x16 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fadd,sgl fr20,fr21,fr22" + - + input: + bytes: [ 0x32, 0x95, 0x26, 0x16 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fsub,sgl fr20,fr21,fr22" + - + input: + bytes: [ 0x32, 0x95, 0x46, 0x16 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fmpy,sgl fr20,fr21,fr22" + - + input: + bytes: [ 0x32, 0x95, 0x66, 0x16 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fdiv,sgl fr20,fr21,fr22" + - + input: + bytes: [ 0x3a, 0x95, 0x47, 0x16 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "xmpyu fr20,fr21,fr22" + - + input: + bytes: [ 0x18, 0x85, 0x41, 0xe6 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fmpyadd,sgl fr20L,fr21L,fr22L,fr23L,fr24L" + - + input: + bytes: [ 0x98, 0x85, 0x41, 0xe6 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fmpysub,sgl fr20L,fr21L,fr22L,fr23L,fr24L" + - + input: + bytes: [ 0xba, 0x95, 0xa4, 0x17 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fmpyfadd,sgl fr20,fr21,fr22,fr23" + - + input: + bytes: [ 0xba, 0x95, 0xa4, 0x37 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fmpynfadd,sgl fr20,fr21,fr22,fr23" diff --git a/tests/MC/HPPA/index_mem11.s.yaml b/tests/MC/HPPA/index_mem11.s.yaml new file mode 100644 index 0000000000..72c71b1b06 --- /dev/null +++ b/tests/MC/HPPA/index_mem11.s.yaml @@ -0,0 +1,784 @@ +test_cases: + - + input: + bytes: [ 0x0c, 0x20, 0x40, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldbx flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x60, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldbx,s flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x40, 0x22 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldbx,m flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x60, 0x22 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldbx,sm flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x68, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldbx,s,sl flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x48, 0x22 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldbx,m,sl flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x68, 0x22 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldbx,sm,sl flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x40, 0x42 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldhx flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x60, 0x42 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldhx,s flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x40, 0x62 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldhx,m flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x60, 0x62 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldhx,sm flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x68, 0x42 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldhx,s,sl flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x48, 0x62 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldhx,m,sl flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x68, 0x62 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldhx,sm,sl flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x40, 0x82 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwx flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x60, 0x82 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwx,s flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x40, 0xa2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwx,m flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x60, 0xa2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwx,sm flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x68, 0x82 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwx,s,sl flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x48, 0xa2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwx,m,sl flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x68, 0xa2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwx,sm,sl flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x01, 0x82 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwax flags(r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x21, 0x82 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwax,s flags(r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x01, 0xa2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwax,m flags(r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x21, 0xa2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwax,sm flags(r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x29, 0x82 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwax,s,sl flags(r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x09, 0xa2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwax,m,sl flags(r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x29, 0xa2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwax,sm,sl flags(r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x41, 0xc2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldcwx flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x61, 0xc2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldcwx,s flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x41, 0xe2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldcwx,m flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x61, 0xe2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldcwx,sm flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x65, 0xc2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldcwx,s,co flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x45, 0xe2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldcwx,m,co flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x20, 0x65, 0xe2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldcwx,sm,co flags(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x50, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldbs 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x50, 0x22 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldbs,ma 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x70, 0x22 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldbs,mb 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x58, 0x22 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldbs,ma,sl 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x78, 0x22 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldbs,mb,sl 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x50, 0x42 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldhs 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x50, 0x62 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldhs,ma 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x70, 0x62 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldhs,mb 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x58, 0x62 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldhs,ma,sl 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x78, 0x62 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldhs,mb,sl 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x50, 0x82 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldws 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x50, 0xa2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldws,ma 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x70, 0xa2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldws,mb 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x58, 0xa2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldws,ma,sl 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x78, 0xa2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldws,mb,sl 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x11, 0x82 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwas 0xf(r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x11, 0xa2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwas,ma 0xf(r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x31, 0xa2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwas,mb 0xf(r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x19, 0xa2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwas,ma,sl 0xf(r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x39, 0xa2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwas,mb,sl 0xf(r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x51, 0xc2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldcws 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x51, 0xe2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldcws,ma 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x71, 0xe2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldcws,mb 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x55, 0xe2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldcws,ma,co 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x75, 0xe2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldcws,mb,co 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x41, 0x52, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stbs r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x52, 0x3e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stbs,ma r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x72, 0x3e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stbs,mb r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x56, 0x3e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stbs,ma,bc r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x7a, 0x3e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stbs,mb,sl r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x52, 0x5e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sths r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x52, 0x7e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sths,ma r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x72, 0x7e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sths,mb r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x56, 0x7e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sths,ma,bc r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x7a, 0x7e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sths,mb,sl r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x52, 0x9e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stws r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x52, 0xbe ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stws,ma r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x72, 0xbe ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stws,mb r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x56, 0xbe ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stws,ma,bc r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x7a, 0xbe ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stws,mb,sl r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x53, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stbys r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x53, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stbys r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x73, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stbys,e r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x53, 0x3e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stbys,b,m r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x73, 0x3e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stbys,e,m r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x57, 0x3e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stbys,b,m,bc r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x7b, 0x3e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stbys,e,m,sl r1,0xf(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x13, 0x9e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stwas r1,0xf(rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x33, 0xbe ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stwas,mb r1,0xf(rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x13, 0xbe ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stwas,ma r1,0xf(rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x37, 0xbe ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stwas,mb,bc r1,0xf(rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x1b, 0xbe ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stwas,ma,sl r1,0xf(rp)" diff --git a/tests/MC/HPPA/longimm20.s.yaml b/tests/MC/HPPA/longimm20.s.yaml new file mode 100644 index 0000000000..b5aea6734d --- /dev/null +++ b/tests/MC/HPPA/longimm20.s.yaml @@ -0,0 +1,28 @@ +test_cases: + - + input: + bytes: [ 0x34, 0x22, 0x3f, 0xf1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldo -8(r1),rp" + - + input: + bytes: [ 0x23, 0x98, 0xc5, 0x4f ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldil -0x55810000,ret0" + - + input: + bytes: [ 0x2b, 0x98, 0xc5, 0x4f ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "addil -0x55810000,ret0" diff --git a/tests/MC/HPPA/mem_mgmt11.s.yaml b/tests/MC/HPPA/mem_mgmt11.s.yaml new file mode 100644 index 0000000000..c635b11bd8 --- /dev/null +++ b/tests/MC/HPPA/mem_mgmt11.s.yaml @@ -0,0 +1,217 @@ +test_cases: + - + input: + bytes: [ 0x04, 0x41, 0x40, 0x40 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "iitlba r1,(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x40, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "iitlbp r1,(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x42, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "pitlb r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x42, 0x40 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "pitlbe r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x42, 0x80 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fic r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x42, 0xa0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fic,m r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x42, 0xc0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fice r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x42, 0xe0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fice,m r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x50, 0x40 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "idtlba r1,(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x50, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "idtlbp r1,(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x52, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "pdtlb r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x52, 0x40 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "pdtlbe r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x52, 0x80 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fdc r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x52, 0xa0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fdc,m r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x52, 0xc0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fdce r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x52, 0xe0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fdce,m r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x53, 0x80 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "pdc r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x53, 0xa0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "pdc,m r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x22, 0x51, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "prober (sr1,r1),rp,r3" + - + input: + bytes: [ 0x04, 0x30, 0x71, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "proberi (sr1,r1),0x10,r3" + - + input: + bytes: [ 0x04, 0x22, 0x51, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "probew (sr1,r1),rp,r3" + - + input: + bytes: [ 0x04, 0x30, 0x71, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "probewi (sr1,r1),0x10,r3" + - + input: + bytes: [ 0x04, 0x41, 0x53, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "lpa r1(sr1,rp),r3" + - + input: + bytes: [ 0x04, 0x41, 0x53, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "lci r1(sr1,rp),r3" diff --git a/tests/MC/HPPA/memory_reference20.s.yaml b/tests/MC/HPPA/memory_reference20.s.yaml new file mode 100644 index 0000000000..6ace3bdc3c --- /dev/null +++ b/tests/MC/HPPA/memory_reference20.s.yaml @@ -0,0 +1,883 @@ +test_cases: + - + input: + bytes: [ 0x0c, 0x41, 0x40, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldb r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x60, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldb,s r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x60, 0x23 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldb,sm r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x40, 0x23 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldb,m r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x50, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldb -8(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x50, 0x23 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldb,ma -8(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x70, 0x23 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldb,mb -8(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x50, 0x58, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldb,sl 8(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x40, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldh r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x60, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldh,s r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x60, 0x63 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldh,sm r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x40, 0x63 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldh,m r1(sr1,rp),r3" + - + input: + bytes: [ 0x44, 0x43, 0x41, 0xbc ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldh 0xde(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x50, 0x63 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldh,ma -8(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x70, 0x63 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldh,mb -8(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x50, 0x58, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldh,sl 8(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x40, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldw r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x60, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldw,s r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x60, 0xa3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldw,sm r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x40, 0xa3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldw,m r1(sr1,rp),r3" + - + input: + bytes: [ 0x48, 0x43, 0x41, 0xbc ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldw 0xde(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x50, 0xa3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldw,ma -8(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x70, 0xa3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldw,mb -8(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x50, 0x58, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldw,sl 8(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x40, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldd r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x60, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldd,s r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x60, 0xe3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldd,sm r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x40, 0xe3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldd,m r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x50, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldd -8(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x50, 0xe3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldd,ma -8(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x70, 0xe3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldd,mb -8(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x50, 0x58, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldd,sl 8(sr1,rp),r3" + - + input: + bytes: [ 0x60, 0x21, 0xbf, 0xb1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stb r1,-0x28(sr2,r1)" + - + input: + bytes: [ 0x0c, 0x21, 0x92, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stb,ma r1,-8(sr2,r1)" + - + input: + bytes: [ 0x0c, 0x21, 0xb2, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stb,mb r1,-8(sr2,r1)" + - + input: + bytes: [ 0x0c, 0x21, 0x92, 0x20 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stb,o r1,0(sr2,r1)" + - + input: + bytes: [ 0x64, 0x21, 0xbf, 0xb1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "sth r1,-0x28(sr2,r1)" + - + input: + bytes: [ 0x0c, 0x21, 0x92, 0x71 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "sth,ma r1,-8(sr2,r1)" + - + input: + bytes: [ 0x0c, 0x21, 0xb2, 0x71 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "sth,mb r1,-8(sr2,r1)" + - + input: + bytes: [ 0x0c, 0x21, 0x92, 0x60 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "sth,o r1,0(sr2,r1)" + - + input: + bytes: [ 0x68, 0x21, 0xbf, 0xb1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stw r1,-0x28(sr2,r1)" + - + input: + bytes: [ 0x0c, 0x21, 0x92, 0xb1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stw,ma r1,-8(sr2,r1)" + - + input: + bytes: [ 0x0c, 0x21, 0xb2, 0xb1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stw,mb r1,-8(sr2,r1)" + - + input: + bytes: [ 0x0c, 0x21, 0x92, 0xa0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stw,o r1,0(sr2,r1)" + - + input: + bytes: [ 0x70, 0x21, 0xbf, 0xb1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "std r1,-0x28(sr2,r1)" + - + input: + bytes: [ 0x0c, 0x21, 0x92, 0xf1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "std,ma r1,-8(sr2,r1)" + - + input: + bytes: [ 0x0c, 0x21, 0xb2, 0xf1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "std,mb r1,-8(sr2,r1)" + - + input: + bytes: [ 0x0c, 0x21, 0x92, 0xe0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "std,o r1,0(sr2,r1)" + - + input: + bytes: [ 0x0c, 0x41, 0x01, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldwa r1(rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x21, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldwa,s r1(rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x21, 0xa3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldwa,sm r1(rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x01, 0xa3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldwa,m r1(rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x11, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldwa -8(rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x11, 0xa3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldwa,ma -8(rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x31, 0xa3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldwa,mb -8(rp),r3" + - + input: + bytes: [ 0x0c, 0x50, 0x19, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldwa,sl 8(rp),r3" + - + input: + bytes: [ 0x0c, 0x40, 0x11, 0xa3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldwa,o 0(rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x01, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldda r1(rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x21, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldda,s r1(rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x21, 0x23 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldda,sm r1(rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x01, 0x23 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldda,m r1(rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x11, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldda -8(rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x11, 0x23 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldda,ma -8(rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x31, 0x23 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldda,mb -8(rp),r3" + - + input: + bytes: [ 0x0c, 0x50, 0x19, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldda,sl 8(rp),r3" + - + input: + bytes: [ 0x0c, 0x40, 0x11, 0x23 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldda,o 0(rp),r3" + - + input: + bytes: [ 0x0c, 0x21, 0x13, 0x91 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stwa r1,-8(r1)" + - + input: + bytes: [ 0x0c, 0x21, 0x13, 0xb1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stwa,ma r1,-8(r1)" + - + input: + bytes: [ 0x0c, 0x21, 0x33, 0xb1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stwa,mb r1,-8(r1)" + - + input: + bytes: [ 0x0c, 0x21, 0x13, 0xa0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stwa,o r1,0(r1)" + - + input: + bytes: [ 0x0c, 0x21, 0x13, 0xd1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stda r1,-8(r1)" + - + input: + bytes: [ 0x0c, 0x21, 0x13, 0xf1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stda,ma r1,-8(r1)" + - + input: + bytes: [ 0x0c, 0x21, 0x33, 0xf1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stda,mb r1,-8(r1)" + - + input: + bytes: [ 0x0c, 0x21, 0x13, 0xe0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stda,o r1,0(r1)" + - + input: + bytes: [ 0x0c, 0x41, 0x41, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldcw r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x61, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldcw,s r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x61, 0xe3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldcw,sm r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x41, 0xe3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldcw,m r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x51, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldcw -8(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x51, 0xe3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldcw,ma -8(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x71, 0xe3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldcw,mb -8(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x40, 0x55, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldcw,co 0(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x41, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldcd r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x61, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldcd,s r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x61, 0x63 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldcd,sm r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x41, 0x63 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldcd,m r1(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x51, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldcd -8(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x51, 0x63 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldcd,ma -8(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x51, 0x71, 0x63 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldcd,mb -8(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x40, 0x55, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldcd,co 0(sr1,rp),r3" + - + input: + bytes: [ 0x0c, 0x41, 0x53, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stby r1,-8(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x53, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stby,b,m r1,-8(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x73, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stby,e r1,-8(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x73, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stby,e,m r1,-8(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x53, 0x51 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stdby r1,-8(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x53, 0x71 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stdby,b,m r1,-8(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x73, 0x51 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stdby,e r1,-8(sr1,rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x73, 0x71 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "stdby,e,m r1,-8(sr1,rp)" diff --git a/tests/MC/HPPA/multimedia20.s.yaml b/tests/MC/HPPA/multimedia20.s.yaml new file mode 100644 index 0000000000..41b14e8a07 --- /dev/null +++ b/tests/MC/HPPA/multimedia20.s.yaml @@ -0,0 +1,118 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x41, 0x03, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "hadd r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x03, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "hadd,ss r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x03, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "hadd,us r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x01, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "hsub r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x01, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "hsub,ss r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x01, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "hsub,us r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x02, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "havg r1,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x07, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "hshladd r1,3,rp,r3" + - + input: + bytes: [ 0x08, 0x41, 0x05, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "hshradd r1,3,rp,r3" + - + input: + bytes: [ 0xf8, 0x01, 0x88, 0xc2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "hshl r1,3,rp" + - + input: + bytes: [ 0xf8, 0x20, 0xcc, 0xc2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "hshr,s r1,3,rp" + - + input: + bytes: [ 0xf8, 0x21, 0x00, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "permh,0000 r1,rp" + - + input: + bytes: [ 0xf8, 0x21, 0x06, 0xc2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "permh,0123 r1,rp" diff --git a/tests/MC/HPPA/no_grp11.s.yaml b/tests/MC/HPPA/no_grp11.s.yaml new file mode 100644 index 0000000000..8fc7bfe069 --- /dev/null +++ b/tests/MC/HPPA/no_grp11.s.yaml @@ -0,0 +1,973 @@ +test_cases: + - + input: + bytes: [ 0x14, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "diag 1" + - + input: + bytes: [ 0x18, 0x22, 0x29, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fmpyadd,dbl fpe2,fpe4,fpe6,fr4,fr5" + - + input: + bytes: [ 0x20, 0x39, 0x00, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldil 0x32000,r1" + - + input: + bytes: [ 0x28, 0x39, 0x00, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addil 0x32000,r1" + - + input: + bytes: [ 0x34, 0x22, 0x00, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldo 0xf(r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x50, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldbs 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x50, 0x42 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldhs 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x3e, 0x50, 0x82 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldws 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x4c, 0x22, 0x40, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldwm 0xf(sr1,r1),rp" + - + input: + bytes: [ 0x0c, 0x41, 0x12, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stbs r1,0xf(rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x12, 0x5e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sths r1,0xf(rp)" + - + input: + bytes: [ 0x0c, 0x41, 0x12, 0x9e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stws r1,0xf(rp)" + - + input: + bytes: [ 0x6c, 0x41, 0x00, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "stwm r1,0xf(rp)" + - + input: + bytes: [ 0x80, 0x41, 0x1f, 0x0d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "combt r1,rp,0xffffffffffffff8c" + - + input: + bytes: [ 0x80, 0x41, 0x3f, 0x05 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "combt,= r1,rp,0xffffffffffffff88" + - + input: + bytes: [ 0x80, 0x41, 0x5e, 0xfd ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "combt,< r1,rp,0xffffffffffffff84" + - + input: + bytes: [ 0x80, 0x41, 0x7e, 0xf5 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "combt,<= r1,rp,0xffffffffffffff80" + - + input: + bytes: [ 0x80, 0x41, 0x9e, 0xed ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "combt,<< r1,rp,0xffffffffffffff7c" + - + input: + bytes: [ 0x80, 0x41, 0xbe, 0xe5 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "combt,<<= r1,rp,0xffffffffffffff78" + - + input: + bytes: [ 0x80, 0x41, 0xde, 0xdd ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "combt,sv r1,rp,0xffffffffffffff74" + - + input: + bytes: [ 0x80, 0x41, 0xfe, 0xd5 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "combt,od r1,rp,0xffffffffffffff70" + - + input: + bytes: [ 0x84, 0x5e, 0x1e, 0xcd ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comibt 0xf,rp,0xffffffffffffff6c" + - + input: + bytes: [ 0x84, 0x5e, 0x3e, 0xc5 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comibt,= 0xf,rp,0xffffffffffffff68" + - + input: + bytes: [ 0x84, 0x5e, 0x5e, 0xbd ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comibt,< 0xf,rp,0xffffffffffffff64" + - + input: + bytes: [ 0x84, 0x5e, 0x7e, 0xb5 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comibt,<= 0xf,rp,0xffffffffffffff60" + - + input: + bytes: [ 0x84, 0x5e, 0x9e, 0xad ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comibt,<< 0xf,rp,0xffffffffffffff5c" + - + input: + bytes: [ 0x84, 0x5e, 0xbe, 0xa5 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comibt,<<= 0xf,rp,0xffffffffffffff58" + - + input: + bytes: [ 0x84, 0x5e, 0xde, 0x9d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comibt,sv 0xf,rp,0xffffffffffffff54" + - + input: + bytes: [ 0x84, 0x5e, 0xfe, 0x95 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comibt,od 0xf,rp,0xffffffffffffff50" + - + input: + bytes: [ 0x88, 0x41, 0x1e, 0x8d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "combf r1,rp,0xffffffffffffff4c" + - + input: + bytes: [ 0x88, 0x41, 0x3e, 0x85 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "combf,= r1,rp,0xffffffffffffff48" + - + input: + bytes: [ 0x88, 0x41, 0x5e, 0x7d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "combf,< r1,rp,0xffffffffffffff44" + - + input: + bytes: [ 0x88, 0x41, 0x7e, 0x75 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "combf,<= r1,rp,0xffffffffffffff40" + - + input: + bytes: [ 0x88, 0x41, 0x9e, 0x6d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "combf,<< r1,rp,0xffffffffffffff3c" + - + input: + bytes: [ 0x88, 0x41, 0xbe, 0x65 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "combf,<<= r1,rp,0xffffffffffffff38" + - + input: + bytes: [ 0x88, 0x41, 0xde, 0x5d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "combf,sv r1,rp,0xffffffffffffff34" + - + input: + bytes: [ 0x88, 0x41, 0xfe, 0x55 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "combf,od r1,rp,0xffffffffffffff30" + - + input: + bytes: [ 0x8c, 0x5e, 0x1e, 0x4d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comibf 0xf,rp,0xffffffffffffff2c" + - + input: + bytes: [ 0x8c, 0x5e, 0x3e, 0x45 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comibf,= 0xf,rp,0xffffffffffffff28" + - + input: + bytes: [ 0x8c, 0x5e, 0x5e, 0x3d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comibf,< 0xf,rp,0xffffffffffffff24" + - + input: + bytes: [ 0x8c, 0x5e, 0x7e, 0x35 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comibf,<= 0xf,rp,0xffffffffffffff20" + - + input: + bytes: [ 0x8c, 0x5e, 0x9e, 0x2d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comibf,<< 0xf,rp,0xffffffffffffff1c" + - + input: + bytes: [ 0x8c, 0x5e, 0xbe, 0x25 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comibf,<<= 0xf,rp,0xffffffffffffff18" + - + input: + bytes: [ 0x8c, 0x5e, 0xde, 0x1d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comibf,sv 0xf,rp,0xffffffffffffff14" + - + input: + bytes: [ 0x8c, 0x5e, 0xfe, 0x15 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comibf,od 0xf,rp,0xffffffffffffff10" + - + input: + bytes: [ 0x90, 0x41, 0x00, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comiclr 0xf,rp,r1" + - + input: + bytes: [ 0x90, 0x41, 0x20, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comiclr,= 0xf,rp,r1" + - + input: + bytes: [ 0x90, 0x41, 0x40, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comiclr,< 0xf,rp,r1" + - + input: + bytes: [ 0x90, 0x41, 0x60, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comiclr,<= 0xf,rp,r1" + - + input: + bytes: [ 0x90, 0x41, 0x80, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comiclr,<< 0xf,rp,r1" + - + input: + bytes: [ 0x90, 0x41, 0xa0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comiclr,<<= 0xf,rp,r1" + - + input: + bytes: [ 0x90, 0x41, 0xc0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comiclr,sv 0xf,rp,r1" + - + input: + bytes: [ 0x90, 0x41, 0xe0, 0x1e ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "comiclr,od 0xf,rp,r1" + - + input: + bytes: [ 0x98, 0x22, 0x29, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "fmpysub,dbl fpe2,fpe4,fpe6,fr4,fr5" + - + input: + bytes: [ 0xa0, 0x41, 0x1d, 0xc5 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addbt r1,rp,0xfffffffffffffee8" + - + input: + bytes: [ 0xa0, 0x41, 0x3d, 0xbd ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addbt,= r1,rp,0xfffffffffffffee4" + - + input: + bytes: [ 0xa0, 0x41, 0x5d, 0xb5 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addbt,< r1,rp,0xfffffffffffffee0" + - + input: + bytes: [ 0xa0, 0x41, 0x7d, 0xad ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addbt,<= r1,rp,0xfffffffffffffedc" + - + input: + bytes: [ 0xa0, 0x41, 0x9d, 0xa7 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addbt,nuv,n r1,rp,0xfffffffffffffed8" + - + input: + bytes: [ 0xa0, 0x41, 0xbd, 0x9f ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addbt,znv,n r1,rp,0xfffffffffffffed4" + - + input: + bytes: [ 0xa0, 0x41, 0xdd, 0x95 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addbt,sv r1,rp,0xfffffffffffffed0" + - + input: + bytes: [ 0xa0, 0x41, 0xfd, 0x8d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addbt,od r1,rp,0xfffffffffffffecc" + - + input: + bytes: [ 0xa4, 0x5e, 0x1d, 0x85 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addibt 0xf,rp,0xfffffffffffffec8" + - + input: + bytes: [ 0xa4, 0x5e, 0x3d, 0x7d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addibt,= 0xf,rp,0xfffffffffffffec4" + - + input: + bytes: [ 0xa4, 0x5e, 0x5d, 0x75 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addibt,< 0xf,rp,0xfffffffffffffec0" + - + input: + bytes: [ 0xa4, 0x5e, 0x7d, 0x6d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addibt,<= 0xf,rp,0xfffffffffffffebc" + - + input: + bytes: [ 0xa4, 0x5e, 0x9d, 0x67 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addibt,nuv,n 0xf,rp,0xfffffffffffffeb8" + - + input: + bytes: [ 0xa4, 0x5e, 0xbd, 0x5f ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addibt,znv,n 0xf,rp,0xfffffffffffffeb4" + - + input: + bytes: [ 0xa4, 0x5e, 0xdd, 0x55 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addibt,sv 0xf,rp,0xfffffffffffffeb0" + - + input: + bytes: [ 0xa4, 0x5e, 0xfd, 0x4d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addibt,od 0xf,rp,0xfffffffffffffeac" + - + input: + bytes: [ 0xa8, 0x41, 0x1d, 0x45 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addbf r1,rp,0xfffffffffffffea8" + - + input: + bytes: [ 0xa8, 0x41, 0x3d, 0x3d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addbf,= r1,rp,0xfffffffffffffea4" + - + input: + bytes: [ 0xa8, 0x41, 0x5d, 0x35 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addbf,< r1,rp,0xfffffffffffffea0" + - + input: + bytes: [ 0xa8, 0x41, 0x7d, 0x2d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addbf,<= r1,rp,0xfffffffffffffe9c" + - + input: + bytes: [ 0xa8, 0x41, 0x9d, 0x27 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addbf,nuv,n r1,rp,0xfffffffffffffe98" + - + input: + bytes: [ 0xa8, 0x41, 0xbd, 0x1f ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addbf,znv,n r1,rp,0xfffffffffffffe94" + - + input: + bytes: [ 0xa8, 0x41, 0xdd, 0x15 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addbf,sv r1,rp,0xfffffffffffffe90" + - + input: + bytes: [ 0xa8, 0x41, 0xfd, 0x0d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addbf,od r1,rp,0xfffffffffffffe8c" + - + input: + bytes: [ 0xac, 0x5e, 0x1d, 0x05 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addibf 0xf,rp,0xfffffffffffffe88" + - + input: + bytes: [ 0xac, 0x5e, 0x3c, 0xfd ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addibf,= 0xf,rp,0xfffffffffffffe84" + - + input: + bytes: [ 0xac, 0x5e, 0x5c, 0xf5 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addibf,< 0xf,rp,0xfffffffffffffe80" + - + input: + bytes: [ 0xac, 0x5e, 0x7c, 0xed ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addibf,<= 0xf,rp,0xfffffffffffffe7c" + - + input: + bytes: [ 0xac, 0x5e, 0x9c, 0xe7 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addibf,nuv,n 0xf,rp,0xfffffffffffffe78" + - + input: + bytes: [ 0xac, 0x5e, 0xbc, 0xdf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addibf,znv,n 0xf,rp,0xfffffffffffffe74" + - + input: + bytes: [ 0xac, 0x5e, 0xdc, 0xd5 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addibf,sv 0xf,rp,0xfffffffffffffe70" + - + input: + bytes: [ 0xac, 0x5e, 0xfc, 0xcd ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "addibf,od 0xf,rp,0xfffffffffffffe6c" + - + input: + bytes: [ 0xc0, 0x01, 0x5c, 0xc7 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "bvb,<,n r1,0xfffffffffffffe68" + - + input: + bytes: [ 0xc0, 0x01, 0xdc, 0xbf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "bvb,>=,n r1,0xfffffffffffffe64" + - + input: + bytes: [ 0xc4, 0x61, 0x5c, 0xb7 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "bb,<,n r1,3,0xfffffffffffffe60" + - + input: + bytes: [ 0xc4, 0x61, 0xdc, 0xaf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "bb,>=,n r1,3,0xfffffffffffffe5c" + - + input: + bytes: [ 0xc8, 0x41, 0x1c, 0xa7 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "movb,n r1,rp,0xfffffffffffffe58" + - + input: + bytes: [ 0xc8, 0x41, 0x3c, 0x9d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "movb,= r1,rp,0xfffffffffffffe54" + - + input: + bytes: [ 0xc8, 0x41, 0x5c, 0x95 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "movb,< r1,rp,0xfffffffffffffe50" + - + input: + bytes: [ 0xc8, 0x41, 0x7c, 0x8d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "movb,od r1,rp,0xfffffffffffffe4c" + - + input: + bytes: [ 0xc8, 0x41, 0x9c, 0x85 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "movb,tr r1,rp,0xfffffffffffffe48" + - + input: + bytes: [ 0xc8, 0x41, 0xbc, 0x7d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "movb,<> r1,rp,0xfffffffffffffe44" + - + input: + bytes: [ 0xc8, 0x41, 0xdc, 0x75 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "movb,>= r1,rp,0xfffffffffffffe40" + - + input: + bytes: [ 0xc8, 0x41, 0xfc, 0x6d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "movb,ev r1,rp,0xfffffffffffffe3c" + - + input: + bytes: [ 0xcc, 0x5e, 0x1c, 0x67 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "movib,n 0xf,rp,0xfffffffffffffe38" + - + input: + bytes: [ 0xcc, 0x5e, 0x3c, 0x5d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "movib,= 0xf,rp,0xfffffffffffffe34" + - + input: + bytes: [ 0xcc, 0x5e, 0x5c, 0x55 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "movib,< 0xf,rp,0xfffffffffffffe30" + - + input: + bytes: [ 0xcc, 0x5e, 0x7c, 0x4d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "movib,od 0xf,rp,0xfffffffffffffe2c" + - + input: + bytes: [ 0xcc, 0x5e, 0x9c, 0x45 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "movib,tr 0xf,rp,0xfffffffffffffe28" + - + input: + bytes: [ 0xcc, 0x5e, 0xbc, 0x3d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "movib,<> 0xf,rp,0xfffffffffffffe24" + - + input: + bytes: [ 0xcc, 0x5e, 0xdc, 0x35 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "movib,>= 0xf,rp,0xfffffffffffffe20" + - + input: + bytes: [ 0xcc, 0x5e, 0xfc, 0x2d ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "movib,ev 0xf,rp,0xfffffffffffffe1c" + - + input: + bytes: [ 0xe0, 0x20, 0x42, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "be,n 0x100(sr1,r1)" + - + input: + bytes: [ 0xe4, 0x20, 0x42, 0x02 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ble,n 0x100(sr1,r1)" diff --git a/tests/MC/HPPA/sfu11.s.yaml b/tests/MC/HPPA/sfu11.s.yaml new file mode 100644 index 0000000000..568d56e4f5 --- /dev/null +++ b/tests/MC/HPPA/sfu11.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x00, 0x00, 0xa3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "spop0,2,3,n" + - + input: + bytes: [ 0x10, 0x00, 0x1a, 0xa1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "spop1,2,3,n r1" + - + input: + bytes: [ 0x10, 0x20, 0x04, 0xa3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "spop2,2,3,n r1" + - + input: + bytes: [ 0x10, 0x41, 0x06, 0xa3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "spop3,2,3,n r1,rp" diff --git a/tests/MC/HPPA/shexdep11.s.yaml b/tests/MC/HPPA/shexdep11.s.yaml new file mode 100644 index 0000000000..66ecf88bc3 --- /dev/null +++ b/tests/MC/HPPA/shexdep11.s.yaml @@ -0,0 +1,1009 @@ +test_cases: + - + input: + bytes: [ 0xd0, 0x41, 0x00, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vshd r1,rp,r3" + - + input: + bytes: [ 0xd0, 0x41, 0x20, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vshd,= r1,rp,r3" + - + input: + bytes: [ 0xd0, 0x41, 0x40, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vshd,< r1,rp,r3" + - + input: + bytes: [ 0xd0, 0x41, 0x60, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vshd,od r1,rp,r3" + - + input: + bytes: [ 0xd0, 0x41, 0x80, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vshd,tr r1,rp,r3" + - + input: + bytes: [ 0xd0, 0x41, 0xa0, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vshd,<> r1,rp,r3" + - + input: + bytes: [ 0xd0, 0x41, 0xc0, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vshd,>= r1,rp,r3" + - + input: + bytes: [ 0xd0, 0x41, 0xe0, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vshd,ev r1,rp,r3" + - + input: + bytes: [ 0xd0, 0x41, 0x0a, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "shd r1,rp,0xf,r3" + - + input: + bytes: [ 0xd0, 0x41, 0x2a, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "shd,= r1,rp,0xf,r3" + - + input: + bytes: [ 0xd0, 0x41, 0x4a, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "shd,< r1,rp,0xf,r3" + - + input: + bytes: [ 0xd0, 0x41, 0x6a, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "shd,od r1,rp,0xf,r3" + - + input: + bytes: [ 0xd0, 0x41, 0x8a, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "shd,tr r1,rp,0xf,r3" + - + input: + bytes: [ 0xd0, 0x41, 0xaa, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "shd,<> r1,rp,0xf,r3" + - + input: + bytes: [ 0xd0, 0x41, 0xca, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "shd,>= r1,rp,0xf,r3" + - + input: + bytes: [ 0xd0, 0x41, 0xea, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "shd,ev r1,rp,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x10, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vextru r1,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x30, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vextru,= r1,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x50, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vextru,< r1,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x70, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vextru,od r1,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x90, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vextru,tr r1,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0xb0, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vextru,<> r1,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0xd0, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vextru,>= r1,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0xf0, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vextru,ev r1,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x14, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vextrs r1,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x34, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vextrs,= r1,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x54, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vextrs,< r1,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x74, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vextrs,od r1,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x94, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vextrs,tr r1,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0xb4, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vextrs,<> r1,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0xd4, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vextrs,>= r1,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0xf4, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vextrs,ev r1,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x19, 0xd1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "extru r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x39, 0xd1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "extru,= r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x59, 0xd1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "extru,< r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x79, 0xd1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "extru,od r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x99, 0xd1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "extru,tr r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0xb9, 0xd1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "extru,<> r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0xd9, 0xd1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "extru,>= r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0xf9, 0xd1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "extru,ev r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x1d, 0xd1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "extrs r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x3d, 0xd1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "extrs,= r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x5d, 0xd1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "extrs,< r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x7d, 0xd1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "extrs,od r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0x9d, 0xd1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "extrs,tr r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0xbd, 0xd1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "extrs,<> r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0xdd, 0xd1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "extrs,>= r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd0, 0x23, 0xfd, 0xd1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "extrs,ev r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x00, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zvdep r1,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x20, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zvdep,= r1,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x40, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zvdep,< r1,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x60, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zvdep,od r1,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x80, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zvdep,tr r1,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0xa0, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zvdep,<> r1,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0xc0, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zvdep,>= r1,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0xe0, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zvdep,ev r1,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x04, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vdep r1,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x24, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vdep,= r1,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x44, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vdep,< r1,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x64, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vdep,od r1,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x84, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vdep,tr r1,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0xa4, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vdep,<> r1,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0xc4, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vdep,>= r1,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0xe4, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vdep,ev r1,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x0a, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zdep r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x2a, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zdep,= r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x4a, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zdep,< r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x6a, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zdep,od r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x8a, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zdep,tr r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0xaa, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zdep,<> r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0xca, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zdep,>= r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0xea, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zdep,ev r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x0e, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "dep r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x2e, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "dep,= r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x4e, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "dep,< r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x6e, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "dep,od r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0x8e, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "dep,tr r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0xae, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "dep,<> r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0xce, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "dep,>= r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x61, 0xee, 0x31 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "dep,ev r1,0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x7c, 0x10, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zvdepi 0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x7c, 0x30, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zvdepi,= 0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x7c, 0x50, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zvdepi,< 0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x7c, 0x70, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zvdepi,od 0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x7c, 0x90, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zvdepi,tr 0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x7c, 0xb0, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zvdepi,<> 0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x7c, 0xd0, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zvdepi,>= 0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x7c, 0xf0, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zvdepi,ev 0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x7c, 0x14, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vdepi 0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x7c, 0x34, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vdepi,= 0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x7c, 0x54, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vdepi,< 0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x7c, 0x74, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vdepi,od 0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x7c, 0x94, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vdepi,tr 0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x7c, 0xb4, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vdepi,<> 0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x7c, 0xd4, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vdepi,>= 0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x7c, 0xf4, 0x11 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "vdepi,ev 0xe,0xf,r3" + - + input: + bytes: [ 0xd4, 0x66, 0x1b, 0xbf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zdepi 3,2,1,r3" + - + input: + bytes: [ 0xd4, 0x66, 0x3b, 0xbf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zdepi,= 3,2,1,r3" + - + input: + bytes: [ 0xd4, 0x66, 0x5b, 0xbf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zdepi,< 3,2,1,r3" + - + input: + bytes: [ 0xd4, 0x66, 0x7b, 0xbf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zdepi,od 3,2,1,r3" + - + input: + bytes: [ 0xd4, 0x66, 0x9b, 0xbf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zdepi,tr 3,2,1,r3" + - + input: + bytes: [ 0xd4, 0x66, 0xbb, 0xbf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zdepi,<> 3,2,1,r3" + - + input: + bytes: [ 0xd4, 0x66, 0xdb, 0xbf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zdepi,>= 3,2,1,r3" + - + input: + bytes: [ 0xd4, 0x66, 0xfb, 0xbf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "zdepi,ev 3,2,1,r3" + - + input: + bytes: [ 0xd4, 0x66, 0x1f, 0xbf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "depi 3,2,1,r3" + - + input: + bytes: [ 0xd4, 0x66, 0x3f, 0xbf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "depi,= 3,2,1,r3" + - + input: + bytes: [ 0xd4, 0x66, 0x5f, 0xbf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "depi,< 3,2,1,r3" + - + input: + bytes: [ 0xd4, 0x66, 0x7f, 0xbf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "depi,od 3,2,1,r3" + - + input: + bytes: [ 0xd4, 0x66, 0x9f, 0xbf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "depi,tr 3,2,1,r3" + - + input: + bytes: [ 0xd4, 0x66, 0xbf, 0xbf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "depi,<> 3,2,1,r3" + - + input: + bytes: [ 0xd4, 0x66, 0xdf, 0xbf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "depi,>= 3,2,1,r3" + - + input: + bytes: [ 0xd4, 0x66, 0xff, 0xbf ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "depi,ev 3,2,1,r3" diff --git a/tests/MC/HPPA/sysctrl20.s.yaml b/tests/MC/HPPA/sysctrl20.s.yaml new file mode 100644 index 0000000000..e8405d407b --- /dev/null +++ b/tests/MC/HPPA/sysctrl20.s.yaml @@ -0,0 +1,433 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x50, 0xa2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ldsid (sr1,r1),rp" + - + input: + bytes: [ 0x00, 0x01, 0x58, 0x20 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "mtsp r1,sr1" + - + input: + bytes: [ 0x00, 0x00, 0x44, 0xa1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "mfsp sr1,r1" + - + input: + bytes: [ 0x00, 0x41, 0x18, 0x40 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "mtctl r1,cr2" + - + input: + bytes: [ 0x00, 0x20, 0x08, 0xa2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "mfctl cr1,rp" + - + input: + bytes: [ 0x01, 0x60, 0x48, 0xa1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "mfctl,w sar,r1" + - + input: + bytes: [ 0x01, 0x61, 0x18, 0xc0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "mtsarcm r1" + - + input: + bytes: [ 0x00, 0x00, 0x14, 0xa1 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "mfia r1" + - + input: + bytes: [ 0x00, 0x0f, 0x0d, 0x61 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "ssm 0xf,r1" + - + input: + bytes: [ 0x00, 0x0f, 0x0e, 0x61 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "rsm 0xf,r1" + - + input: + bytes: [ 0x00, 0x01, 0x18, 0x60 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "mtsm r1" + - + input: + bytes: [ 0x00, 0x00, 0x0c, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "rfi" + - + input: + bytes: [ 0x00, 0x00, 0x0c, 0xa0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "rfi,r" + - + input: + bytes: [ 0x03, 0xff, 0xc0, 0x1f ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "break 0x1f,0x1ffe" + - + input: + bytes: [ 0x00, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "sync" + - + input: + bytes: [ 0x00, 0x10, 0x04, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "syncdma" + - + input: + bytes: [ 0x04, 0x22, 0x51, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "probe,r (sr1,r1),rp,r3" + - + input: + bytes: [ 0x04, 0x22, 0x51, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "probe,w (sr1,r1),rp,r3" + - + input: + bytes: [ 0x04, 0x22, 0x51, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "probe,r (sr1,r1),rp,r3" + - + input: + bytes: [ 0x04, 0x2f, 0x71, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "probei,r (sr1,r1),0xf,r3" + - + input: + bytes: [ 0x04, 0x2f, 0x71, 0xc3 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "probei,w (sr1,r1),0xf,r3" + - + input: + bytes: [ 0x04, 0x2f, 0x71, 0x83 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "probei,r (sr1,r1),0xf,r3" + - + input: + bytes: [ 0x04, 0x41, 0x53, 0x43 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "lpa r1(sr1,rp),r3" + - + input: + bytes: [ 0x04, 0x41, 0x53, 0x63 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "lpa,m r1(sr1,rp),r3" + - + input: + bytes: [ 0x04, 0x41, 0x53, 0x03 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "lci r1(sr1,rp),r3" + - + input: + bytes: [ 0x04, 0x41, 0x12, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "pdtlb r1(rp)" + - + input: + bytes: [ 0x04, 0x41, 0x16, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "pdtlb,l r1(rp)" + - + input: + bytes: [ 0x04, 0x41, 0x16, 0x20 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "pdtlb,l,m r1(rp)" + - + input: + bytes: [ 0x04, 0x41, 0x42, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "pitlb r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x46, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "pitlb,l r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x46, 0x20 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "pitlb,l,m r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x12, 0x40 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "pdtlbe r1(rp)" + - + input: + bytes: [ 0x04, 0x41, 0x12, 0x60 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "pdtlbe,m r1(rp)" + - + input: + bytes: [ 0x04, 0x41, 0x42, 0x40 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "pitlbe r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x42, 0x60 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "pitlbe,m r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x18, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "idtlbt r1,rp" + - + input: + bytes: [ 0x04, 0x41, 0x08, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "iitlbt r1,rp" + - + input: + bytes: [ 0x04, 0x41, 0x13, 0x80 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "pdc r1(rp)" + - + input: + bytes: [ 0x04, 0x41, 0x13, 0xa0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "pdc,m r1(rp)" + - + input: + bytes: [ 0x04, 0x41, 0x52, 0x80 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fdc r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x52, 0xa0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fdc,m r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x5e, 0x72, 0x80 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fdc 0xf(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x42, 0x80 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fic r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x52, 0xc0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fdce r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x52, 0xe0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fdce,m r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x42, 0xc0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fice r1(sr1,rp)" + - + input: + bytes: [ 0x04, 0x41, 0x42, 0xe0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "fice,m r1(sr1,rp)" + - + input: + bytes: [ 0x14, 0x00, 0xde, 0xad ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ] + expected: + insns: + - + asm_text: "diag 0xdead" diff --git a/tests/MC/HPPA/system_op11.s.yaml b/tests/MC/HPPA/system_op11.s.yaml new file mode 100644 index 0000000000..745a5e664e --- /dev/null +++ b/tests/MC/HPPA/system_op11.s.yaml @@ -0,0 +1,118 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x20, 0x01 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "break 1,1" + - + input: + bytes: [ 0x00, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "sync" + - + input: + bytes: [ 0x00, 0x10, 0x04, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "syncdma" + - + input: + bytes: [ 0x00, 0x00, 0x0c, 0x00 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "rfi" + - + input: + bytes: [ 0x00, 0x00, 0x0c, 0xa0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "rfir" + - + input: + bytes: [ 0x00, 0x1e, 0x0d, 0x61 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ssm 0x1e,r1" + - + input: + bytes: [ 0x00, 0x1e, 0x0e, 0x61 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "rsm 0x1e,r1" + - + input: + bytes: [ 0x00, 0x01, 0x18, 0x60 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "mtsm r1" + - + input: + bytes: [ 0x00, 0x20, 0x50, 0xa2 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "ldsid (sr1,r1),rp" + - + input: + bytes: [ 0x00, 0x00, 0x58, 0x20 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "mtsp flags,sr1" + - + input: + bytes: [ 0x00, 0x00, 0x44, 0xa0 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "mfsp sr1,flags" + - + input: + bytes: [ 0x00, 0x00, 0x18, 0x40 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "mtctl flags,rctr" + - + input: + bytes: [ 0x00, 0x00, 0x18, 0x40 ] + arch: "CS_ARCH_HPPA" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ] + expected: + insns: + - + asm_text: "mtctl flags,rctr" diff --git a/tests/MC/LoongArch/absd.s.yaml b/tests/MC/LoongArch/absd.s.yaml new file mode 100644 index 0000000000..9de4e1d115 --- /dev/null +++ b/tests/MC/LoongArch/absd.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x36, 0x44, 0x60, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvabsd.b $xr22, $xr1, $xr17" + - + input: + bytes: [ 0x11, 0xa7, 0x60, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvabsd.h $xr17, $xr24, $xr9" + - + input: + bytes: [ 0x3c, 0x75, 0x61, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvabsd.w $xr28, $xr9, $xr29" + - + input: + bytes: [ 0xfe, 0xce, 0x61, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvabsd.d $xr30, $xr23, $xr19" + - + input: + bytes: [ 0x90, 0x3c, 0x62, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvabsd.bu $xr16, $xr4, $xr15" + - + input: + bytes: [ 0xed, 0xee, 0x62, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvabsd.hu $xr13, $xr23, $xr27" + - + input: + bytes: [ 0x5f, 0x3e, 0x63, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvabsd.wu $xr31, $xr18, $xr15" + - + input: + bytes: [ 0x5a, 0x91, 0x63, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvabsd.du $xr26, $xr10, $xr4" diff --git a/tests/MC/LoongArch/add.s.yaml b/tests/MC/LoongArch/add.s.yaml new file mode 100644 index 0000000000..a415317466 --- /dev/null +++ b/tests/MC/LoongArch/add.s.yaml @@ -0,0 +1,46 @@ +test_cases: + - + input: + bytes: [ 0x74, 0x16, 0x0a, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvadd.b $xr20, $xr19, $xr5" + - + input: + bytes: [ 0xf8, 0xb8, 0x0a, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvadd.h $xr24, $xr7, $xr14" + - + input: + bytes: [ 0x33, 0x54, 0x0b, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvadd.w $xr19, $xr1, $xr21" + - + input: + bytes: [ 0xd3, 0xb4, 0x0b, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvadd.d $xr19, $xr6, $xr13" + - + input: + bytes: [ 0x84, 0x1b, 0x2d, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvadd.q $xr4, $xr28, $xr6" diff --git a/tests/MC/LoongArch/adda.s.yaml b/tests/MC/LoongArch/adda.s.yaml new file mode 100644 index 0000000000..1aba39cab0 --- /dev/null +++ b/tests/MC/LoongArch/adda.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x0a, 0x6f, 0x5c, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvadda.b $xr10, $xr24, $xr27" + - + input: + bytes: [ 0x80, 0xf7, 0x5c, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvadda.h $xr0, $xr28, $xr29" + - + input: + bytes: [ 0x3f, 0x25, 0x5d, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvadda.w $xr31, $xr9, $xr9" + - + input: + bytes: [ 0x2a, 0xe4, 0x5d, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvadda.d $xr10, $xr1, $xr25" diff --git a/tests/MC/LoongArch/addi.s.yaml b/tests/MC/LoongArch/addi.s.yaml new file mode 100644 index 0000000000..2492161c40 --- /dev/null +++ b/tests/MC/LoongArch/addi.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0xc1, 0x0a, 0x8a, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddi.bu $xr1, $xr22, 2" + - + input: + bytes: [ 0x43, 0xf5, 0x8a, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddi.hu $xr3, $xr10, 0x1d" + - + input: + bytes: [ 0x65, 0x0d, 0x8b, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddi.wu $xr5, $xr11, 3" + - + input: + bytes: [ 0x06, 0x9c, 0x8b, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddi.du $xr6, $xr0, 7" diff --git a/tests/MC/LoongArch/addw.s.yaml b/tests/MC/LoongArch/addw.s.yaml new file mode 100644 index 0000000000..bb7e0286ae --- /dev/null +++ b/tests/MC/LoongArch/addw.s.yaml @@ -0,0 +1,217 @@ +test_cases: + - + input: + bytes: [ 0xd7, 0x13, 0x1e, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwev.h.b $xr23, $xr30, $xr4" + - + input: + bytes: [ 0x74, 0xfe, 0x1e, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwev.w.h $xr20, $xr19, $xr31" + - + input: + bytes: [ 0x28, 0x65, 0x1f, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwev.d.w $xr8, $xr9, $xr25" + - + input: + bytes: [ 0xdd, 0xf6, 0x1f, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwev.q.d $xr29, $xr22, $xr29" + - + input: + bytes: [ 0xbe, 0x69, 0x2e, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwev.h.bu $xr30, $xr13, $xr26" + - + input: + bytes: [ 0xef, 0xc3, 0x2e, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwev.w.hu $xr15, $xr31, $xr16" + - + input: + bytes: [ 0x10, 0x52, 0x2f, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwev.d.wu $xr16, $xr16, $xr20" + - + input: + bytes: [ 0x4a, 0xca, 0x2f, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwev.q.du $xr10, $xr18, $xr18" + - + input: + bytes: [ 0xe3, 0x24, 0x3e, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwev.h.bu.b $xr3, $xr7, $xr9" + - + input: + bytes: [ 0x1a, 0xee, 0x3e, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwev.w.hu.h $xr26, $xr16, $xr27" + - + input: + bytes: [ 0xa0, 0x21, 0x3f, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwev.d.wu.w $xr0, $xr13, $xr8" + - + input: + bytes: [ 0x53, 0x8d, 0x3f, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwev.q.du.d $xr19, $xr10, $xr3" + - + input: + bytes: [ 0xae, 0x62, 0x22, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwod.h.b $xr14, $xr21, $xr24" + - + input: + bytes: [ 0x53, 0xdf, 0x22, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwod.w.h $xr19, $xr26, $xr23" + - + input: + bytes: [ 0x2c, 0x51, 0x23, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwod.d.w $xr12, $xr9, $xr20" + - + input: + bytes: [ 0x4b, 0xa0, 0x23, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwod.q.d $xr11, $xr2, $xr8" + - + input: + bytes: [ 0xc6, 0x24, 0x32, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwod.h.bu $xr6, $xr6, $xr9" + - + input: + bytes: [ 0x61, 0xe7, 0x32, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwod.w.hu $xr1, $xr27, $xr25" + - + input: + bytes: [ 0x7a, 0x2e, 0x33, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwod.d.wu $xr26, $xr19, $xr11" + - + input: + bytes: [ 0xd5, 0xa2, 0x33, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwod.q.du $xr21, $xr22, $xr8" + - + input: + bytes: [ 0x55, 0x63, 0x40, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwod.h.bu.b $xr21, $xr26, $xr24" + - + input: + bytes: [ 0xdf, 0xc0, 0x40, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwod.w.hu.h $xr31, $xr6, $xr16" + - + input: + bytes: [ 0x8c, 0x7f, 0x41, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwod.d.wu.w $xr12, $xr28, $xr31" + - + input: + bytes: [ 0x9d, 0xb0, 0x41, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvaddwod.q.du.d $xr29, $xr4, $xr12" diff --git a/tests/MC/LoongArch/and.s.yaml b/tests/MC/LoongArch/and.s.yaml new file mode 100644 index 0000000000..4cc12c527d --- /dev/null +++ b/tests/MC/LoongArch/and.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xee, 0x4e, 0x26, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvand.v $xr14, $xr23, $xr19" diff --git a/tests/MC/LoongArch/andi.s.yaml b/tests/MC/LoongArch/andi.s.yaml new file mode 100644 index 0000000000..923b577788 --- /dev/null +++ b/tests/MC/LoongArch/andi.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xeb, 0x08, 0xd1, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvandi.b $xr11, $xr7, 0x42" diff --git a/tests/MC/LoongArch/andn.s.yaml b/tests/MC/LoongArch/andn.s.yaml new file mode 100644 index 0000000000..79ca97e3f4 --- /dev/null +++ b/tests/MC/LoongArch/andn.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xe3, 0x0d, 0x28, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvandn.v $xr3, $xr15, $xr3" diff --git a/tests/MC/LoongArch/arith.s.yaml b/tests/MC/LoongArch/arith.s.yaml new file mode 100644 index 0000000000..f970b44e5d --- /dev/null +++ b/tests/MC/LoongArch/arith.s.yaml @@ -0,0 +1,262 @@ +test_cases: + - + input: + bytes: [ 0x29, 0x7c, 0x10, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "add.w $a5, $ra, $s8" + - + input: + bytes: [ 0x35, 0x4f, 0x11, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "sub.w $r21, $s2, $t7" + - + input: + bytes: [ 0xe5, 0xd8, 0x83, 0x02 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "addi.w $a1, $a3, 0xf6" + - + input: + bytes: [ 0x22, 0x8a, 0x05, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "alsl.w $tp, $t5, $tp, 4" + - + input: + bytes: [ 0x30, 0x06, 0x00, 0x14 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "lu12i.w $t4, 0x31" + - + input: + bytes: [ 0xe4, 0xff, 0xff, 0x15 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "lu12i.w $a0, -1" + - + input: + bytes: [ 0x5d, 0x0b, 0x12, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "slt $s6, $s3, $tp" + - + input: + bytes: [ 0xab, 0xf6, 0x12, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "sltu $a7, $r21, $s6" + - + input: + bytes: [ 0x3b, 0xac, 0x03, 0x02 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "slti $s4, $ra, 0xeb" + - + input: + bytes: [ 0x00, 0x89, 0x42, 0x02 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "sltui $zero, $a4, 0xa2" + - + input: + bytes: [ 0x69, 0x17, 0x00, 0x18 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "pcaddi $a5, 0xbb" + - + input: + bytes: [ 0xa0, 0x04, 0x00, 0x1c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "pcaddu12i $zero, 0x25" + - + input: + bytes: [ 0x2a, 0x0b, 0x00, 0x1a ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "pcalau12i $a6, 0x59" + - + input: + bytes: [ 0xf3, 0x87, 0x14, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "and $t7, $s8, $ra" + - + input: + bytes: [ 0x11, 0x7a, 0x15, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "or $t5, $t4, $s7" + - + input: + bytes: [ 0x45, 0x16, 0x14, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "nor $a1, $t6, $a1" + - + input: + bytes: [ 0x6f, 0xa2, 0x15, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xor $t3, $t7, $a4" + - + input: + bytes: [ 0x3c, 0x97, 0x16, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "andn $s5, $s2, $a1" + - + input: + bytes: [ 0x62, 0x64, 0x16, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "orn $tp, $sp, $s2" + - + input: + bytes: [ 0x19, 0xa8, 0x41, 0x03 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "andi $s2, $zero, 0x6a" + - + input: + bytes: [ 0xb1, 0xbc, 0x80, 0x03 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ori $t5, $a1, 0x2f" + - + input: + bytes: [ 0xf2, 0x8e, 0xc1, 0x03 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xori $t6, $s0, 0x63" + - + input: + bytes: [ 0x44, 0x0e, 0x1c, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "mul.w $a0, $t6, $sp" + - + input: + bytes: [ 0xfb, 0x82, 0x1c, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "mulh.w $s4, $s0, $zero" + - + input: + bytes: [ 0x2a, 0x62, 0x1d, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "mulh.wu $a6, $t5, $s1" + - + input: + bytes: [ 0xbe, 0x65, 0x20, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "div.w $s7, $t1, $s2" + - + input: + bytes: [ 0x41, 0xab, 0x20, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "mod.w $ra, $s3, $a6" + - + input: + bytes: [ 0xf3, 0x02, 0x21, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "div.wu $t7, $s0, $zero" + - + input: + bytes: [ 0x3b, 0xc5, 0x21, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "mod.wu $s4, $a5, $t5" diff --git a/tests/MC/LoongArch/arm-alu.s.yaml b/tests/MC/LoongArch/arm-alu.s.yaml new file mode 100644 index 0000000000..94a8e2d288 --- /dev/null +++ b/tests/MC/LoongArch/arm-alu.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x91, 0x14, 0x37, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armadd.w $a0, $a1, 1" + - + input: + bytes: [ 0x91, 0x94, 0x37, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armsub.w $a0, $a1, 1" + - + input: + bytes: [ 0x91, 0x14, 0x38, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armadc.w $a0, $a1, 1" + - + input: + bytes: [ 0x91, 0x94, 0x38, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armsbc.w $a0, $a1, 1" + - + input: + bytes: [ 0x91, 0x14, 0x39, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armand.w $a0, $a1, 1" + - + input: + bytes: [ 0x91, 0x94, 0x39, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armor.w $a0, $a1, 1" + - + input: + bytes: [ 0x91, 0x14, 0x3a, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armxor.w $a0, $a1, 1" + - + input: + bytes: [ 0x9c, 0xc4, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armnot.w $a0, 1" diff --git a/tests/MC/LoongArch/arm-jump.s.yaml b/tests/MC/LoongArch/arm-jump.s.yaml new file mode 100644 index 0000000000..d10ca4dafb --- /dev/null +++ b/tests/MC/LoongArch/arm-jump.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x04, 0xc4, 0x36, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "setarmj $a0, 1" diff --git a/tests/MC/LoongArch/arm-mov.s.yaml b/tests/MC/LoongArch/arm-mov.s.yaml new file mode 100644 index 0000000000..5ba08cb23e --- /dev/null +++ b/tests/MC/LoongArch/arm-mov.s.yaml @@ -0,0 +1,46 @@ +test_cases: + - + input: + bytes: [ 0xa4, 0x44, 0x36, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armmove $a0, $a1, 1" + - + input: + bytes: [ 0x9d, 0xc4, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armmov.w $a0, 1" + - + input: + bytes: [ 0x9e, 0xc4, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armmov.d $a0, 1" + - + input: + bytes: [ 0x44, 0x04, 0x5c, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armmfflag $a0, 1" + - + input: + bytes: [ 0x64, 0x04, 0x5c, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armmtflag $a0, 1" diff --git a/tests/MC/LoongArch/arm-shift.s.yaml b/tests/MC/LoongArch/arm-shift.s.yaml new file mode 100644 index 0000000000..35f4e232cf --- /dev/null +++ b/tests/MC/LoongArch/arm-shift.s.yaml @@ -0,0 +1,82 @@ +test_cases: + - + input: + bytes: [ 0x91, 0x94, 0x3a, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armsll.w $a0, $a1, 1" + - + input: + bytes: [ 0x91, 0x14, 0x3b, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armsrl.w $a0, $a1, 1" + - + input: + bytes: [ 0x91, 0x94, 0x3b, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armsra.w $a0, $a1, 1" + - + input: + bytes: [ 0x91, 0x14, 0x3c, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armrotr.w $a0, $a1, 1" + - + input: + bytes: [ 0x91, 0x84, 0x3c, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armslli.w $a0, 1, 1" + - + input: + bytes: [ 0x91, 0x04, 0x3d, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armsrli.w $a0, 1, 1" + - + input: + bytes: [ 0x91, 0x84, 0x3d, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armsrai.w $a0, 1, 1" + - + input: + bytes: [ 0x91, 0x04, 0x3e, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armrotri.w $a0, 1, 1" + - + input: + bytes: [ 0x9f, 0xc4, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "armrrx.w $a0, 1" diff --git a/tests/MC/LoongArch/atomic.s.yaml b/tests/MC/LoongArch/atomic.s.yaml new file mode 100644 index 0000000000..31dfcdc5b5 --- /dev/null +++ b/tests/MC/LoongArch/atomic.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x62, 0xdf, 0x00, 0x20 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ll.w $tp, $s4, 0xdc" + - + input: + bytes: [ 0xd3, 0x39, 0x00, 0x21 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "sc.w $t7, $t2, 0x38" + - + input: + bytes: [ 0xcd, 0x81, 0x57, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "llacq.w $t1, $t2" + - + input: + bytes: [ 0xcd, 0x85, 0x57, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "screl.w $t1, $t2" diff --git a/tests/MC/LoongArch/avg.s.yaml b/tests/MC/LoongArch/avg.s.yaml new file mode 100644 index 0000000000..5c1ec770f9 --- /dev/null +++ b/tests/MC/LoongArch/avg.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0xc5, 0x57, 0x64, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvavg.b $xr5, $xr30, $xr21" + - + input: + bytes: [ 0x32, 0xd6, 0x64, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvavg.h $xr18, $xr17, $xr21" + - + input: + bytes: [ 0xe3, 0x52, 0x65, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvavg.w $xr3, $xr23, $xr20" + - + input: + bytes: [ 0x1b, 0xec, 0x65, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvavg.d $xr27, $xr0, $xr27" + - + input: + bytes: [ 0x8b, 0x40, 0x66, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvavg.bu $xr11, $xr4, $xr16" + - + input: + bytes: [ 0x22, 0xcc, 0x66, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvavg.hu $xr2, $xr1, $xr19" + - + input: + bytes: [ 0x9b, 0x6e, 0x67, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvavg.wu $xr27, $xr20, $xr27" + - + input: + bytes: [ 0x97, 0xf6, 0x67, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvavg.du $xr23, $xr20, $xr29" diff --git a/tests/MC/LoongArch/avgr.s.yaml b/tests/MC/LoongArch/avgr.s.yaml new file mode 100644 index 0000000000..49b30f14a9 --- /dev/null +++ b/tests/MC/LoongArch/avgr.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0xfd, 0x1d, 0x68, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvavgr.b $xr29, $xr15, $xr7" + - + input: + bytes: [ 0x40, 0xbf, 0x68, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvavgr.h $xr0, $xr26, $xr15" + - + input: + bytes: [ 0x17, 0x00, 0x69, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvavgr.w $xr23, $xr0, $xr0" + - + input: + bytes: [ 0xfd, 0x82, 0x69, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvavgr.d $xr29, $xr23, $xr0" + - + input: + bytes: [ 0x56, 0x64, 0x6a, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvavgr.bu $xr22, $xr2, $xr25" + - + input: + bytes: [ 0x59, 0xd5, 0x6a, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvavgr.hu $xr25, $xr10, $xr21" + - + input: + bytes: [ 0xd1, 0x0d, 0x6b, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvavgr.wu $xr17, $xr14, $xr3" + - + input: + bytes: [ 0x62, 0xb5, 0x6b, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvavgr.du $xr2, $xr11, $xr13" diff --git a/tests/MC/LoongArch/barrier.s.yaml b/tests/MC/LoongArch/barrier.s.yaml new file mode 100644 index 0000000000..3c57629f28 --- /dev/null +++ b/tests/MC/LoongArch/barrier.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "dbar 0" + - + input: + bytes: [ 0x00, 0x80, 0x72, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ibar 0" diff --git a/tests/MC/LoongArch/base.s.yaml b/tests/MC/LoongArch/base.s.yaml new file mode 100644 index 0000000000..7e59d559b7 --- /dev/null +++ b/tests/MC/LoongArch/base.s.yaml @@ -0,0 +1,298 @@ +test_cases: + - + input: + bytes: [ 0xa4, 0x04, 0x29, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "addu12i.w $a0, $a1, 1" + - + input: + bytes: [ 0xa4, 0x84, 0x29, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "addu12i.d $a0, $a1, 1" + - + input: + bytes: [ 0xa4, 0x18, 0x30, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "adc.b $a0, $a1, $a2" + - + input: + bytes: [ 0xa4, 0x98, 0x30, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "adc.h $a0, $a1, $a2" + - + input: + bytes: [ 0xa4, 0x18, 0x31, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "adc.w $a0, $a1, $a2" + - + input: + bytes: [ 0xa4, 0x98, 0x31, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "adc.d $a0, $a1, $a2" + - + input: + bytes: [ 0xa4, 0x18, 0x32, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "sbc.b $a0, $a1, $a2" + - + input: + bytes: [ 0xa4, 0x98, 0x32, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "sbc.h $a0, $a1, $a2" + - + input: + bytes: [ 0xa4, 0x18, 0x33, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "sbc.w $a0, $a1, $a2" + - + input: + bytes: [ 0xa4, 0x98, 0x33, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "sbc.d $a0, $a1, $a2" + - + input: + bytes: [ 0xa4, 0x18, 0x1a, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "rotr.b $a0, $a1, $a2" + - + input: + bytes: [ 0xa4, 0x98, 0x1a, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "rotr.h $a0, $a1, $a2" + - + input: + bytes: [ 0xa4, 0x24, 0x4c, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "rotri.b $a0, $a1, 1" + - + input: + bytes: [ 0xa4, 0x44, 0x4c, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "rotri.h $a0, $a1, 1" + - + input: + bytes: [ 0xa4, 0x18, 0x34, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "rcr.b $a0, $a1, $a2" + - + input: + bytes: [ 0xa4, 0x98, 0x34, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "rcr.h $a0, $a1, $a2" + - + input: + bytes: [ 0xa4, 0x18, 0x35, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "rcr.w $a0, $a1, $a2" + - + input: + bytes: [ 0xa4, 0x98, 0x35, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "rcr.d $a0, $a1, $a2" + - + input: + bytes: [ 0xa4, 0x24, 0x50, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "rcri.b $a0, $a1, 1" + - + input: + bytes: [ 0xa4, 0x44, 0x50, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "rcri.h $a0, $a1, 1" + - + input: + bytes: [ 0xa4, 0x84, 0x50, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "rcri.w $a0, $a1, 1" + - + input: + bytes: [ 0xa4, 0x04, 0x51, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "rcri.d $a0, $a1, 1" + - + input: + bytes: [ 0x20, 0xe4, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcvt.ud.d $fa0, $fa1" + - + input: + bytes: [ 0x20, 0xe0, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcvt.ld.d $fa0, $fa1" + - + input: + bytes: [ 0x20, 0x08, 0x15, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcvt.d.ld $fa0, $fa1, $fa2" + - + input: + bytes: [ 0xa4, 0x04, 0x80, 0x2e ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ldl.d $a0, $a1, 1" + - + input: + bytes: [ 0xa4, 0x04, 0x00, 0x2e ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ldl.w $a0, $a1, 1" + - + input: + bytes: [ 0xa4, 0x04, 0x40, 0x2e ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ldr.w $a0, $a1, 1" + - + input: + bytes: [ 0xa4, 0x04, 0xc0, 0x2e ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ldr.d $a0, $a1, 1" + - + input: + bytes: [ 0xa4, 0x04, 0x00, 0x2f ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "stl.w $a0, $a1, 1" + - + input: + bytes: [ 0xa4, 0x04, 0x80, 0x2f ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "stl.d $a0, $a1, 1" + - + input: + bytes: [ 0xa4, 0x04, 0x40, 0x2f ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "str.w $a0, $a1, 1" + - + input: + bytes: [ 0xa4, 0x04, 0xc0, 0x2f ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "str.d $a0, $a1, 1" diff --git a/tests/MC/LoongArch/bit-manipu.s.yaml b/tests/MC/LoongArch/bit-manipu.s.yaml new file mode 100644 index 0000000000..f71335e0a7 --- /dev/null +++ b/tests/MC/LoongArch/bit-manipu.s.yaml @@ -0,0 +1,109 @@ +test_cases: + - + input: + bytes: [ 0x61, 0x10, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "clo.w $ra, $sp" + - + input: + bytes: [ 0x47, 0x15, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "clz.w $a3, $a6" + - + input: + bytes: [ 0xc2, 0x18, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "cto.w $tp, $a2" + - + input: + bytes: [ 0xc5, 0x1e, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ctz.w $a1, $fp" + - + input: + bytes: [ 0x1d, 0x40, 0x08, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "bytepick.w $s6, $zero, $t4, 0" + - + input: + bytes: [ 0x74, 0x31, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "revb.2h $t8, $a7" + - + input: + bytes: [ 0x75, 0x4b, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "bitrev.4b $r21, $s4" + - + input: + bytes: [ 0xb9, 0x50, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "bitrev.w $s2, $a1" + - + input: + bytes: [ 0x68, 0x09, 0x67, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "bstrins.w $a4, $a7, 7, 2" + - + input: + bytes: [ 0x21, 0x91, 0x6a, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "bstrpick.w $ra, $a5, 0xa, 4" + - + input: + bytes: [ 0x74, 0x49, 0x13, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "maskeqz $t8, $a7, $t6" + - + input: + bytes: [ 0xb4, 0xe9, 0x13, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "masknez $t8, $t1, $s3" diff --git a/tests/MC/LoongArch/bit-shift.s.yaml b/tests/MC/LoongArch/bit-shift.s.yaml new file mode 100644 index 0000000000..bef713646f --- /dev/null +++ b/tests/MC/LoongArch/bit-shift.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x5f, 0x17, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "sll.w $s1, $s4, $s0" + - + input: + bytes: [ 0x3f, 0x9e, 0x17, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "srl.w $s8, $t5, $a3" + - + input: + bytes: [ 0x8c, 0x2b, 0x18, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "sra.w $t0, $s5, $a6" + - + input: + bytes: [ 0x41, 0x4b, 0x1b, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "rotr.w $ra, $s3, $t6" + - + input: + bytes: [ 0x5a, 0x82, 0x40, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "slli.w $s3, $t6, 0" + - + input: + bytes: [ 0xca, 0xf9, 0x44, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "srli.w $a6, $t2, 0x1e" + - + input: + bytes: [ 0x28, 0xe2, 0x48, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "srai.w $a4, $t5, 0x18" + - + input: + bytes: [ 0x97, 0xde, 0x4c, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "rotri.w $s0, $t8, 0x17" diff --git a/tests/MC/LoongArch/bitclr.s.yaml b/tests/MC/LoongArch/bitclr.s.yaml new file mode 100644 index 0000000000..bcec288506 --- /dev/null +++ b/tests/MC/LoongArch/bitclr.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0xb8, 0x38, 0x0c, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitclr.b $xr24, $xr5, $xr14" + - + input: + bytes: [ 0x3e, 0xb5, 0x0c, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitclr.h $xr30, $xr9, $xr13" + - + input: + bytes: [ 0x62, 0x1c, 0x0d, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitclr.w $xr2, $xr3, $xr7" + - + input: + bytes: [ 0xae, 0xe4, 0x0d, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitclr.d $xr14, $xr5, $xr25" + - + input: + bytes: [ 0x56, 0x3f, 0x10, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitclri.b $xr22, $xr26, 7" + - + input: + bytes: [ 0xc2, 0x75, 0x10, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitclri.h $xr2, $xr14, 0xd" + - + input: + bytes: [ 0x43, 0x80, 0x10, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitclri.w $xr3, $xr2, 0" + - + input: + bytes: [ 0x8a, 0x1d, 0x11, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitclri.d $xr10, $xr12, 7" diff --git a/tests/MC/LoongArch/bitrev.s.yaml b/tests/MC/LoongArch/bitrev.s.yaml new file mode 100644 index 0000000000..649419716f --- /dev/null +++ b/tests/MC/LoongArch/bitrev.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x90, 0x0e, 0x10, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitrev.b $xr16, $xr20, $xr3" + - + input: + bytes: [ 0x70, 0xd0, 0x10, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitrev.h $xr16, $xr3, $xr20" + - + input: + bytes: [ 0x58, 0x5f, 0x11, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitrev.w $xr24, $xr26, $xr23" + - + input: + bytes: [ 0x2d, 0xec, 0x11, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitrev.d $xr13, $xr1, $xr27" + - + input: + bytes: [ 0x67, 0x35, 0x18, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitrevi.b $xr7, $xr11, 5" + - + input: + bytes: [ 0xa1, 0x7c, 0x18, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitrevi.h $xr1, $xr5, 0xf" + - + input: + bytes: [ 0xad, 0xca, 0x18, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitrevi.w $xr13, $xr21, 0x12" + - + input: + bytes: [ 0x61, 0x24, 0x19, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitrevi.d $xr1, $xr3, 0x9" diff --git a/tests/MC/LoongArch/bitsel.s.yaml b/tests/MC/LoongArch/bitsel.s.yaml new file mode 100644 index 0000000000..dfb2e4c7bf --- /dev/null +++ b/tests/MC/LoongArch/bitsel.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xb2, 0xbf, 0x2a, 0x0d ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitsel.v $xr18, $xr29, $xr15, $xr21" diff --git a/tests/MC/LoongArch/bitseli.s.yaml b/tests/MC/LoongArch/bitseli.s.yaml new file mode 100644 index 0000000000..08e790f412 --- /dev/null +++ b/tests/MC/LoongArch/bitseli.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xad, 0xe6, 0xc5, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitseli.b $xr13, $xr21, 0x79" diff --git a/tests/MC/LoongArch/bitset.s.yaml b/tests/MC/LoongArch/bitset.s.yaml new file mode 100644 index 0000000000..335f99bfeb --- /dev/null +++ b/tests/MC/LoongArch/bitset.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x06, 0x72, 0x0e, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitset.b $xr6, $xr16, $xr28" + - + input: + bytes: [ 0xa5, 0xfd, 0x0e, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitset.h $xr5, $xr13, $xr31" + - + input: + bytes: [ 0x87, 0x23, 0x0f, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitset.w $xr7, $xr28, $xr8" + - + input: + bytes: [ 0x04, 0xb2, 0x0f, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitset.d $xr4, $xr16, $xr12" + - + input: + bytes: [ 0x7a, 0x20, 0x14, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitseti.b $xr26, $xr3, 0" + - + input: + bytes: [ 0x69, 0x66, 0x14, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitseti.h $xr9, $xr19, 0x9" + - + input: + bytes: [ 0x6c, 0x8a, 0x14, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitseti.w $xr12, $xr19, 2" + - + input: + bytes: [ 0xf4, 0x08, 0x15, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbitseti.d $xr20, $xr7, 2" diff --git a/tests/MC/LoongArch/bound-check.s.yaml b/tests/MC/LoongArch/bound-check.s.yaml new file mode 100644 index 0000000000..b39054319b --- /dev/null +++ b/tests/MC/LoongArch/bound-check.s.yaml @@ -0,0 +1,145 @@ +test_cases: + - + input: + bytes: [ 0xc6, 0x74, 0x78, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ldgt.b $a2, $a2, $s6" + - + input: + bytes: [ 0xe5, 0x87, 0x78, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ldgt.h $a1, $s8, $ra" + - + input: + bytes: [ 0x4f, 0x23, 0x79, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ldgt.w $t3, $s3, $a4" + - + input: + bytes: [ 0x37, 0xff, 0x79, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ldgt.d $s0, $s2, $s8" + - + input: + bytes: [ 0x89, 0x3d, 0x7a, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ldle.b $a5, $t0, $t3" + - + input: + bytes: [ 0x6b, 0xdd, 0x7a, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ldle.h $a7, $a7, $s0" + - + input: + bytes: [ 0x58, 0x08, 0x7b, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ldle.w $s1, $tp, $tp" + - + input: + bytes: [ 0xf4, 0xc1, 0x7b, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ldle.d $t8, $t3, $t4" + - + input: + bytes: [ 0x7b, 0x52, 0x7c, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "stgt.b $s4, $t7, $t8" + - + input: + bytes: [ 0x90, 0x98, 0x7c, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "stgt.h $t4, $a0, $a2" + - + input: + bytes: [ 0x9f, 0x3b, 0x7d, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "stgt.w $s8, $s5, $t2" + - + input: + bytes: [ 0xbe, 0xe2, 0x7d, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "stgt.d $s7, $r21, $s1" + - + input: + bytes: [ 0x8a, 0x40, 0x7e, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "stle.b $a6, $a0, $t4" + - + input: + bytes: [ 0x31, 0xd6, 0x7e, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "stle.h $t5, $t5, $r21" + - + input: + bytes: [ 0x97, 0x77, 0x7f, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "stle.w $s0, $s5, $s6" + - + input: + bytes: [ 0x19, 0xf7, 0x7f, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "stle.d $s2, $s1, $s6" diff --git a/tests/MC/LoongArch/branch.s.yaml b/tests/MC/LoongArch/branch.s.yaml new file mode 100644 index 0000000000..a025774184 --- /dev/null +++ b/tests/MC/LoongArch/branch.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x47, 0xb1, 0x00, 0x58 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "beq $a6, $a3, 0xb0" + - + input: + bytes: [ 0x21, 0x8b, 0x00, 0x5c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "bne $s2, $ra, 0x88" + - + input: + bytes: [ 0xfe, 0xa9, 0x00, 0x60 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "blt $t3, $s7, 0xa8" + - + input: + bytes: [ 0x8f, 0x95, 0x00, 0x64 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "bge $t0, $t3, 0x94" + - + input: + bytes: [ 0x25, 0x06, 0x00, 0x68 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "bltu $t5, $a1, 4" + - + input: + bytes: [ 0xd7, 0x8c, 0x00, 0x6c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "bgeu $a2, $s0, 0x8c" + - + input: + bytes: [ 0x20, 0x61, 0x00, 0x40 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "beqz $a5, 0x60" + - + input: + bytes: [ 0x60, 0xd4, 0x00, 0x44 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "bnez $sp, 0xd4" + - + input: + bytes: [ 0x00, 0xf8, 0x00, 0x50 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "b 0xf8" + - + input: + bytes: [ 0x00, 0xec, 0x00, 0x54 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "bl 0xec" + - + input: + bytes: [ 0x81, 0x04, 0x00, 0x4c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "jirl $ra, $a0, 4" diff --git a/tests/MC/LoongArch/bsll.s.yaml b/tests/MC/LoongArch/bsll.s.yaml new file mode 100644 index 0000000000..6396b2a3bd --- /dev/null +++ b/tests/MC/LoongArch/bsll.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xae, 0x52, 0x8e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbsll.v $xr14, $xr21, 0x14" diff --git a/tests/MC/LoongArch/bsrl.s.yaml b/tests/MC/LoongArch/bsrl.s.yaml new file mode 100644 index 0000000000..2d909d5a32 --- /dev/null +++ b/tests/MC/LoongArch/bsrl.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xa4, 0xf4, 0x8e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvbsrl.v $xr4, $xr5, 0x1d" diff --git a/tests/MC/LoongArch/clo.s.yaml b/tests/MC/LoongArch/clo.s.yaml new file mode 100644 index 0000000000..647ad20fbb --- /dev/null +++ b/tests/MC/LoongArch/clo.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x89, 0x01, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvclo.b $xr9, $xr12" + - + input: + bytes: [ 0xd0, 0x05, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvclo.h $xr16, $xr14" + - + input: + bytes: [ 0x5e, 0x0a, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvclo.w $xr30, $xr18" + - + input: + bytes: [ 0xbf, 0x0c, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvclo.d $xr31, $xr5" diff --git a/tests/MC/LoongArch/clz.s.yaml b/tests/MC/LoongArch/clz.s.yaml new file mode 100644 index 0000000000..20d216da8d --- /dev/null +++ b/tests/MC/LoongArch/clz.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0xc5, 0x10, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvclz.b $xr5, $xr6" + - + input: + bytes: [ 0xe4, 0x14, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvclz.h $xr4, $xr7" + - + input: + bytes: [ 0x0c, 0x18, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvclz.w $xr12, $xr0" + - + input: + bytes: [ 0x01, 0x1c, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvclz.d $xr1, $xr0" diff --git a/tests/MC/LoongArch/crc.s.yaml b/tests/MC/LoongArch/crc.s.yaml new file mode 100644 index 0000000000..328928f37c --- /dev/null +++ b/tests/MC/LoongArch/crc.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0xf8, 0x08, 0x24, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "crc.w.b.w $s1, $a3, $tp" + - + input: + bytes: [ 0x5f, 0xc9, 0x24, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "crc.w.h.w $s8, $a6, $t6" + - + input: + bytes: [ 0xdc, 0x28, 0x25, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "crc.w.w.w $s5, $a2, $a6" + - + input: + bytes: [ 0x7c, 0xfd, 0x25, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "crc.w.d.w $s5, $a7, $s8" + - + input: + bytes: [ 0x4f, 0x0e, 0x26, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "crcc.w.b.w $t3, $t6, $sp" + - + input: + bytes: [ 0xb5, 0xcb, 0x26, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "crcc.w.h.w $r21, $s6, $t6" + - + input: + bytes: [ 0xd1, 0x35, 0x27, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "crcc.w.w.w $t5, $t2, $t1" + - + input: + bytes: [ 0xbe, 0xee, 0x27, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "crcc.w.d.w $s7, $r21, $s4" diff --git a/tests/MC/LoongArch/d-arith.s.yaml b/tests/MC/LoongArch/d-arith.s.yaml new file mode 100644 index 0000000000..16471ded99 --- /dev/null +++ b/tests/MC/LoongArch/d-arith.s.yaml @@ -0,0 +1,217 @@ +test_cases: + - + input: + bytes: [ 0xfd, 0xe5, 0x00, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fadd.s $fs5, $ft7, $fs1" + - + input: + bytes: [ 0xf9, 0x34, 0x01, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fadd.d $fs1, $fa7, $ft5" + - + input: + bytes: [ 0x3d, 0x48, 0x03, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fsub.d $fs5, $fa1, $ft10" + - + input: + bytes: [ 0xc4, 0x1f, 0x05, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fmul.d $fa4, $fs6, $fa7" + - + input: + bytes: [ 0x23, 0x73, 0x07, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fdiv.d $fa3, $fs1, $fs4" + - + input: + bytes: [ 0x15, 0x73, 0x2c, 0x08 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fmadd.d $ft13, $fs0, $fs4, $fs0" + - + input: + bytes: [ 0x46, 0xd2, 0x6d, 0x08 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fmsub.d $fa6, $ft10, $ft12, $fs3" + - + input: + bytes: [ 0xb9, 0x4d, 0xaf, 0x08 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fnmadd.d $fs1, $ft5, $ft11, $fs6" + - + input: + bytes: [ 0x5e, 0x1f, 0xec, 0x08 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fnmsub.d $fs6, $fs2, $fa7, $fs0" + - + input: + bytes: [ 0x4b, 0x37, 0x09, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fmax.d $ft3, $fs2, $ft5" + - + input: + bytes: [ 0xa1, 0x6d, 0x0b, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fmin.d $fa1, $ft5, $fs3" + - + input: + bytes: [ 0xb8, 0x11, 0x0d, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fmaxa.d $fs0, $ft5, $fa4" + - + input: + bytes: [ 0x52, 0x01, 0x0f, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fmina.d $ft10, $ft2, $fa0" + - + input: + bytes: [ 0x77, 0x08, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fabs.d $ft15, $fa3" + - + input: + bytes: [ 0x4b, 0x1b, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fneg.d $ft3, $fs2" + - + input: + bytes: [ 0x62, 0x49, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fsqrt.d $fa2, $ft3" + - + input: + bytes: [ 0x7b, 0x5b, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "frecip.d $fs3, $fs3" + - + input: + bytes: [ 0x00, 0x78, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "frecipe.d $fa0, $fa0" + - + input: + bytes: [ 0x76, 0x68, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "frsqrt.d $ft14, $fa3" + - + input: + bytes: [ 0x21, 0x88, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "frsqrte.d $fa1, $fa1" + - + input: + bytes: [ 0xcc, 0x69, 0x11, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fscaleb.d $ft4, $ft6, $fs2" + - + input: + bytes: [ 0xb5, 0x2b, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "flogb.d $ft13, $fs5" + - + input: + bytes: [ 0x50, 0x1b, 0x13, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcopysign.d $ft8, $fs2, $fa6" + - + input: + bytes: [ 0x53, 0x38, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fclass.d $ft11, $fa2" diff --git a/tests/MC/LoongArch/d-bound-check.s.yaml b/tests/MC/LoongArch/d-bound-check.s.yaml new file mode 100644 index 0000000000..216e0c56d6 --- /dev/null +++ b/tests/MC/LoongArch/d-bound-check.s.yaml @@ -0,0 +1,46 @@ +test_cases: + - + input: + bytes: [ 0x63, 0x37, 0x74, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fldgt.s $fa3, $s4, $t1" + - + input: + bytes: [ 0xba, 0xfc, 0x74, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fldgt.d $fs2, $a1, $s8" + - + input: + bytes: [ 0xe3, 0xd9, 0x75, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fldle.d $fa3, $t3, $fp" + - + input: + bytes: [ 0x6d, 0xe9, 0x76, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fstgt.d $ft5, $a7, $s3" + - + input: + bytes: [ 0x32, 0xb5, 0x77, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fstle.d $ft10, $a5, $t1" diff --git a/tests/MC/LoongArch/d-branch.s.yaml b/tests/MC/LoongArch/d-branch.s.yaml new file mode 100644 index 0000000000..de6f91ffcc --- /dev/null +++ b/tests/MC/LoongArch/d-branch.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xc0, 0x0c, 0x00, 0x48 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "bceqz $fcc6, 0xc" diff --git a/tests/MC/LoongArch/d-comp.s.yaml b/tests/MC/LoongArch/d-comp.s.yaml new file mode 100644 index 0000000000..2ac4d2a83e --- /dev/null +++ b/tests/MC/LoongArch/d-comp.s.yaml @@ -0,0 +1,208 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x04, 0x10, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.caf.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x20, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.caf.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x24, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.cun.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x22, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.ceq.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x26, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.cueq.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x21, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.clt.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x25, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.cult.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x23, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.cle.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x27, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.cule.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x28, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.cne.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x2a, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.cor.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x2c, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.cune.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x20, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.saf.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x24, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.sun.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x22, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.seq.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x26, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.sueq.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x21, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.slt.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x25, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.sult.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x23, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.sle.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x27, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.sule.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x28, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.sne.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x2a, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.sor.d $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x2c, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.sune.d $fcc0, $fa0, $fa1" diff --git a/tests/MC/LoongArch/d-conv.s.yaml b/tests/MC/LoongArch/d-conv.s.yaml new file mode 100644 index 0000000000..1d6f35190c --- /dev/null +++ b/tests/MC/LoongArch/d-conv.s.yaml @@ -0,0 +1,199 @@ +test_cases: + - + input: + bytes: [ 0x25, 0x46, 0x1e, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "frint.s $fa5, $ft9" + - + input: + bytes: [ 0x6c, 0x1a, 0x19, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcvt.s.d $ft4, $ft11" + - + input: + bytes: [ 0xca, 0x24, 0x19, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcvt.d.s $ft2, $fa6" + - + input: + bytes: [ 0xa6, 0x18, 0x1d, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ffint.s.l $fa6, $fa5" + - + input: + bytes: [ 0x58, 0x22, 0x1d, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ffint.d.w $fs0, $ft10" + - + input: + bytes: [ 0x57, 0x2b, 0x1d, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ffint.d.l $ft15, $fs2" + - + input: + bytes: [ 0xc3, 0x09, 0x1b, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftint.w.d $fa3, $ft6" + - + input: + bytes: [ 0x1f, 0x27, 0x1b, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftint.l.s $fs7, $fs0" + - + input: + bytes: [ 0x10, 0x2b, 0x1b, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftint.l.d $ft8, $fs0" + - + input: + bytes: [ 0x07, 0x09, 0x1a, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftintrm.w.d $fa7, $ft0" + - + input: + bytes: [ 0x58, 0x25, 0x1a, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftintrm.l.s $fs0, $ft2" + - + input: + bytes: [ 0x29, 0x29, 0x1a, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftintrm.l.d $ft1, $ft1" + - + input: + bytes: [ 0x6c, 0x48, 0x1a, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftintrp.w.d $ft4, $fa3" + - + input: + bytes: [ 0x00, 0x66, 0x1a, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftintrp.l.s $fa0, $ft8" + - + input: + bytes: [ 0xa4, 0x6b, 0x1a, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftintrp.l.d $fa4, $fs5" + - + input: + bytes: [ 0x19, 0x8b, 0x1a, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftintrz.w.d $fs1, $fs0" + - + input: + bytes: [ 0xb7, 0xa4, 0x1a, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftintrz.l.s $ft15, $fa5" + - + input: + bytes: [ 0x43, 0xa9, 0x1a, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftintrz.l.d $fa3, $ft2" + - + input: + bytes: [ 0x9f, 0xc9, 0x1a, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftintrne.w.d $fs7, $ft4" + - + input: + bytes: [ 0x76, 0xe7, 0x1a, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftintrne.l.s $ft14, $fs3" + - + input: + bytes: [ 0xdc, 0xe8, 0x1a, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftintrne.l.d $fs4, $fa6" + - + input: + bytes: [ 0x5d, 0x48, 0x1e, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "frint.d $fs5, $fa2" diff --git a/tests/MC/LoongArch/d-memory.s.yaml b/tests/MC/LoongArch/d-memory.s.yaml new file mode 100644 index 0000000000..a1eeb5027c --- /dev/null +++ b/tests/MC/LoongArch/d-memory.s.yaml @@ -0,0 +1,46 @@ +test_cases: + - + input: + bytes: [ 0xf7, 0xe9, 0x03, 0x2b ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fld.s $ft15, $t3, 0xfa" + - + input: + bytes: [ 0x36, 0xca, 0x81, 0x2b ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fld.d $ft14, $t5, 0x72" + - + input: + bytes: [ 0xfc, 0x18, 0xc3, 0x2b ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fst.d $fs4, $a3, 0xc6" + - + input: + bytes: [ 0xbb, 0x7d, 0x34, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fldx.d $fs3, $t1, $s8" + - + input: + bytes: [ 0xe6, 0x45, 0x3c, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fstx.d $fa6, $t3, $t5" diff --git a/tests/MC/LoongArch/d-move.s.yaml b/tests/MC/LoongArch/d-move.s.yaml new file mode 100644 index 0000000000..e137286844 --- /dev/null +++ b/tests/MC/LoongArch/d-move.s.yaml @@ -0,0 +1,28 @@ +test_cases: + - + input: + bytes: [ 0xed, 0x96, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fmov.s $ft5, $ft15" + - + input: + bytes: [ 0x3e, 0x99, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fmov.d $fs6, $ft1" + - + input: + bytes: [ 0x92, 0x56, 0x02, 0x0d ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fsel $ft10, $ft12, $ft13, $fcc4" diff --git a/tests/MC/LoongArch/div.s.yaml b/tests/MC/LoongArch/div.s.yaml new file mode 100644 index 0000000000..fce252bcec --- /dev/null +++ b/tests/MC/LoongArch/div.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x29, 0x23, 0xe0, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvdiv.b $xr9, $xr25, $xr8" + - + input: + bytes: [ 0x32, 0xec, 0xe0, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvdiv.h $xr18, $xr1, $xr27" + - + input: + bytes: [ 0x45, 0x6f, 0xe1, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvdiv.w $xr5, $xr26, $xr27" + - + input: + bytes: [ 0x5b, 0xb3, 0xe1, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvdiv.d $xr27, $xr26, $xr12" + - + input: + bytes: [ 0xc0, 0x7a, 0xe4, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvdiv.bu $xr0, $xr22, $xr30" + - + input: + bytes: [ 0xff, 0xe6, 0xe4, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvdiv.hu $xr31, $xr23, $xr25" + - + input: + bytes: [ 0x21, 0x1f, 0xe5, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvdiv.wu $xr1, $xr25, $xr7" + - + input: + bytes: [ 0x27, 0x9f, 0xe5, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvdiv.du $xr7, $xr25, $xr7" diff --git a/tests/MC/LoongArch/ext2xv.s.yaml b/tests/MC/LoongArch/ext2xv.s.yaml new file mode 100644 index 0000000000..2a2adc8133 --- /dev/null +++ b/tests/MC/LoongArch/ext2xv.s.yaml @@ -0,0 +1,109 @@ +test_cases: + - + input: + bytes: [ 0x7e, 0x12, 0x9f, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "vext2xv.h.b $xr30, $xr19" + - + input: + bytes: [ 0xbb, 0x14, 0x9f, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "vext2xv.w.b $xr27, $xr5" + - + input: + bytes: [ 0x39, 0x1b, 0x9f, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "vext2xv.d.b $xr25, $xr25" + - + input: + bytes: [ 0x94, 0x1e, 0x9f, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "vext2xv.w.h $xr20, $xr20" + - + input: + bytes: [ 0x68, 0x22, 0x9f, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "vext2xv.d.h $xr8, $xr19" + - + input: + bytes: [ 0x24, 0x27, 0x9f, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "vext2xv.d.w $xr4, $xr25" + - + input: + bytes: [ 0x99, 0x29, 0x9f, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "vext2xv.hu.bu $xr25, $xr12" + - + input: + bytes: [ 0xbf, 0x2d, 0x9f, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "vext2xv.wu.bu $xr31, $xr13" + - + input: + bytes: [ 0x2c, 0x33, 0x9f, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "vext2xv.du.bu $xr12, $xr25" + - + input: + bytes: [ 0x97, 0x35, 0x9f, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "vext2xv.wu.hu $xr23, $xr12" + - + input: + bytes: [ 0xd2, 0x38, 0x9f, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "vext2xv.du.hu $xr18, $xr6" + - + input: + bytes: [ 0xaa, 0x3e, 0x9f, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "vext2xv.du.wu $xr10, $xr21" diff --git a/tests/MC/LoongArch/exth.s.yaml b/tests/MC/LoongArch/exth.s.yaml new file mode 100644 index 0000000000..24dadb7e10 --- /dev/null +++ b/tests/MC/LoongArch/exth.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x4f, 0xe1, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvexth.h.b $xr15, $xr10" + - + input: + bytes: [ 0x7a, 0xe5, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvexth.w.h $xr26, $xr11" + - + input: + bytes: [ 0x62, 0xeb, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvexth.d.w $xr2, $xr27" + - + input: + bytes: [ 0x36, 0xef, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvexth.q.d $xr22, $xr25" + - + input: + bytes: [ 0xd5, 0xf3, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvexth.hu.bu $xr21, $xr30" + - + input: + bytes: [ 0x7c, 0xf5, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvexth.wu.hu $xr28, $xr11" + - + input: + bytes: [ 0x3b, 0xfb, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvexth.du.wu $xr27, $xr25" + - + input: + bytes: [ 0x90, 0xff, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvexth.qu.du $xr16, $xr28" diff --git a/tests/MC/LoongArch/extl.s.yaml b/tests/MC/LoongArch/extl.s.yaml new file mode 100644 index 0000000000..0aa2aa8f68 --- /dev/null +++ b/tests/MC/LoongArch/extl.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0x9d, 0x01, 0x09, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvextl.q.d $xr29, $xr12" + - + input: + bytes: [ 0x9b, 0x02, 0x0d, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvextl.qu.du $xr27, $xr20" diff --git a/tests/MC/LoongArch/extrins.s.yaml b/tests/MC/LoongArch/extrins.s.yaml new file mode 100644 index 0000000000..181d5e94f9 --- /dev/null +++ b/tests/MC/LoongArch/extrins.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0xfe, 0xf2, 0x8f, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvextrins.b $xr30, $xr23, 0xfc" + - + input: + bytes: [ 0xa0, 0x21, 0x8b, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvextrins.h $xr0, $xr13, 0xc8" + - + input: + bytes: [ 0xae, 0x62, 0x86, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvextrins.w $xr14, $xr21, 0x98" + - + input: + bytes: [ 0xdf, 0x1f, 0x82, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvextrins.d $xr31, $xr30, 0x87" diff --git a/tests/MC/LoongArch/f-arith.s.yaml b/tests/MC/LoongArch/f-arith.s.yaml new file mode 100644 index 0000000000..08247b72bd --- /dev/null +++ b/tests/MC/LoongArch/f-arith.s.yaml @@ -0,0 +1,208 @@ +test_cases: + - + input: + bytes: [ 0xfd, 0xe5, 0x00, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fadd.s $fs5, $ft7, $fs1" + - + input: + bytes: [ 0xce, 0xfc, 0x02, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fsub.s $ft6, $fa6, $fs7" + - + input: + bytes: [ 0xe0, 0xc4, 0x04, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fmul.s $fa0, $fa7, $ft9" + - + input: + bytes: [ 0x14, 0xcf, 0x06, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fdiv.s $ft12, $fs0, $ft11" + - + input: + bytes: [ 0x03, 0x8e, 0x17, 0x08 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fmadd.s $fa3, $ft8, $fa3, $ft7" + - + input: + bytes: [ 0x77, 0x55, 0x52, 0x08 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fmsub.s $ft15, $ft3, $ft13, $fa4" + - + input: + bytes: [ 0x3d, 0x60, 0x9a, 0x08 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fnmadd.s $fs5, $fa1, $fs0, $ft12" + - + input: + bytes: [ 0x88, 0xe0, 0xdc, 0x08 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fnmsub.s $ft0, $fa4, $fs0, $fs1" + - + input: + bytes: [ 0xd6, 0xec, 0x08, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fmax.s $ft14, $fa6, $fs3" + - + input: + bytes: [ 0x4e, 0xcd, 0x0a, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fmin.s $ft6, $ft2, $ft11" + - + input: + bytes: [ 0x69, 0xff, 0x0c, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fmaxa.s $ft1, $fs3, $fs7" + - + input: + bytes: [ 0x4f, 0x86, 0x0e, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fmina.s $ft7, $ft10, $fa1" + - + input: + bytes: [ 0x9c, 0x05, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fabs.s $fs4, $ft4" + - + input: + bytes: [ 0x15, 0x17, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fneg.s $ft13, $fs0" + - + input: + bytes: [ 0x5b, 0x46, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fsqrt.s $fs3, $ft10" + - + input: + bytes: [ 0x71, 0x57, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "frecip.s $ft9, $fs3" + - + input: + bytes: [ 0x00, 0x74, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "frecipe.s $fa0, $fa0" + - + input: + bytes: [ 0x99, 0x65, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "frsqrt.s $fs1, $ft4" + - + input: + bytes: [ 0x21, 0x84, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "frsqrte.s $fa1, $fa1" + - + input: + bytes: [ 0xf5, 0x9a, 0x10, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fscaleb.s $ft13, $ft15, $fa6" + - + input: + bytes: [ 0xff, 0x26, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "flogb.s $fs7, $ft15" + - + input: + bytes: [ 0x0d, 0xdf, 0x12, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcopysign.s $ft5, $fs0, $ft15" + - + input: + bytes: [ 0x34, 0x35, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fclass.s $ft12, $ft1" diff --git a/tests/MC/LoongArch/f-bound-check.s.yaml b/tests/MC/LoongArch/f-bound-check.s.yaml new file mode 100644 index 0000000000..e973c3b9ac --- /dev/null +++ b/tests/MC/LoongArch/f-bound-check.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x63, 0x37, 0x74, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fldgt.s $fa3, $s4, $t1" + - + input: + bytes: [ 0xb8, 0x47, 0x75, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fldle.s $fs0, $s6, $t5" + - + input: + bytes: [ 0xbf, 0x79, 0x76, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fstgt.s $fs7, $t1, $s7" + - + input: + bytes: [ 0xad, 0x1d, 0x77, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fstle.s $ft5, $t1, $a3" diff --git a/tests/MC/LoongArch/f-branch.s.yaml b/tests/MC/LoongArch/f-branch.s.yaml new file mode 100644 index 0000000000..da87d45edb --- /dev/null +++ b/tests/MC/LoongArch/f-branch.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0xc0, 0x0c, 0x00, 0x48 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "bceqz $fcc6, 0xc" + - + input: + bytes: [ 0xc0, 0x49, 0x00, 0x48 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "bcnez $fcc6, 0x48" diff --git a/tests/MC/LoongArch/f-comp.s.yaml b/tests/MC/LoongArch/f-comp.s.yaml new file mode 100644 index 0000000000..8a01684fe7 --- /dev/null +++ b/tests/MC/LoongArch/f-comp.s.yaml @@ -0,0 +1,199 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x04, 0x10, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.caf.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x14, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.cun.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x12, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.ceq.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x16, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.cueq.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x11, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.clt.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x15, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.cult.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x13, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.cle.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x17, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.cule.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x18, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.cne.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x1a, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.cor.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x04, 0x1c, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.cune.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x10, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.saf.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x14, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.sun.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x12, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.seq.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x16, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.sueq.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x11, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.slt.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x15, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.sult.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x13, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.sle.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x17, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.sule.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x18, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.sne.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x1a, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.sor.s $fcc0, $fa0, $fa1" + - + input: + bytes: [ 0x00, 0x84, 0x1c, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fcmp.sune.s $fcc0, $fa0, $fa1" diff --git a/tests/MC/LoongArch/f-conv.s.yaml b/tests/MC/LoongArch/f-conv.s.yaml new file mode 100644 index 0000000000..3b3e5aa090 --- /dev/null +++ b/tests/MC/LoongArch/f-conv.s.yaml @@ -0,0 +1,64 @@ +test_cases: + - + input: + bytes: [ 0xbe, 0x10, 0x1d, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ffint.s.w $fs6, $fa5" + - + input: + bytes: [ 0xb5, 0x05, 0x1b, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftint.w.s $ft13, $ft5" + - + input: + bytes: [ 0x10, 0x06, 0x1a, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftintrm.w.s $ft8, $ft8" + - + input: + bytes: [ 0xee, 0x47, 0x1a, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftintrp.w.s $ft6, $fs7" + - + input: + bytes: [ 0xa4, 0x87, 0x1a, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftintrz.w.s $fa4, $fs5" + - + input: + bytes: [ 0x24, 0xc6, 0x1a, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ftintrne.w.s $fa4, $ft9" + - + input: + bytes: [ 0x25, 0x46, 0x1e, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "frint.s $fa5, $ft9" diff --git a/tests/MC/LoongArch/f-memory.s.yaml b/tests/MC/LoongArch/f-memory.s.yaml new file mode 100644 index 0000000000..82d799bd09 --- /dev/null +++ b/tests/MC/LoongArch/f-memory.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0xf7, 0xe9, 0x03, 0x2b ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fld.s $ft15, $t3, 0xfa" + - + input: + bytes: [ 0x7e, 0x9a, 0x43, 0x2b ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fst.s $fs6, $t7, 0xe6" + - + input: + bytes: [ 0xe1, 0x4d, 0x30, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fldx.s $fa1, $t3, $t7" + - + input: + bytes: [ 0x7a, 0x58, 0x38, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fstx.s $fs2, $sp, $fp" diff --git a/tests/MC/LoongArch/f-move.s.yaml b/tests/MC/LoongArch/f-move.s.yaml new file mode 100644 index 0000000000..c6d0904d04 --- /dev/null +++ b/tests/MC/LoongArch/f-move.s.yaml @@ -0,0 +1,145 @@ +test_cases: + - + input: + bytes: [ 0xed, 0x96, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fmov.s $ft5, $ft15" + - + input: + bytes: [ 0x92, 0x56, 0x02, 0x0d ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "fsel $ft10, $ft12, $ft13, $fcc4" + - + input: + bytes: [ 0x46, 0xa4, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "movgr2fr.w $fa6, $tp" + - + input: + bytes: [ 0xca, 0xb6, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "movfr2gr.s $a6, $ft14" + - + input: + bytes: [ 0x80, 0xc0, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "movgr2fcsr $fcsr0, $a0" + - + input: + bytes: [ 0x04, 0xc8, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "movfcsr2gr $a0, $fcsr0" + - + input: + bytes: [ 0x81, 0xc0, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "movgr2fcsr $fcsr1, $a0" + - + input: + bytes: [ 0x24, 0xc8, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "movfcsr2gr $a0, $fcsr1" + - + input: + bytes: [ 0x82, 0xc0, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "movgr2fcsr $fcsr2, $a0" + - + input: + bytes: [ 0x44, 0xc8, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "movfcsr2gr $a0, $fcsr2" + - + input: + bytes: [ 0x83, 0xc0, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "movgr2fcsr $fcsr3, $a0" + - + input: + bytes: [ 0x64, 0xc8, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "movfcsr2gr $a0, $fcsr3" + - + input: + bytes: [ 0x64, 0xd1, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "movfr2cf $fcc4, $ft3" + - + input: + bytes: [ 0x10, 0xd4, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "movcf2fr $ft8, $fcc0" + - + input: + bytes: [ 0x25, 0xd8, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "movgr2cf $fcc5, $ra" + - + input: + bytes: [ 0xf5, 0xdc, 0x14, 0x01 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "movcf2gr $r21, $fcc7" diff --git a/tests/MC/LoongArch/fadd.s.yaml b/tests/MC/LoongArch/fadd.s.yaml new file mode 100644 index 0000000000..f0ec82215c --- /dev/null +++ b/tests/MC/LoongArch/fadd.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0xa6, 0xbe, 0x30, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfadd.s $xr6, $xr21, $xr15" + - + input: + bytes: [ 0x1b, 0x05, 0x31, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfadd.d $xr27, $xr8, $xr1" diff --git a/tests/MC/LoongArch/fclass.s.yaml b/tests/MC/LoongArch/fclass.s.yaml new file mode 100644 index 0000000000..9c6ca38484 --- /dev/null +++ b/tests/MC/LoongArch/fclass.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0xe3, 0xd4, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfclass.s $xr3, $xr7" + - + input: + bytes: [ 0x56, 0xd9, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfclass.d $xr22, $xr10" diff --git a/tests/MC/LoongArch/fcmp.s.yaml b/tests/MC/LoongArch/fcmp.s.yaml new file mode 100644 index 0000000000..72c744f400 --- /dev/null +++ b/tests/MC/LoongArch/fcmp.s.yaml @@ -0,0 +1,397 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x7d, 0x90, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.caf.s $xr1, $xr8, $xr31" + - + input: + bytes: [ 0xf3, 0x53, 0xa0, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.caf.d $xr19, $xr31, $xr20" + - + input: + bytes: [ 0x28, 0x75, 0x94, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.cun.s $xr8, $xr9, $xr29" + - + input: + bytes: [ 0xd3, 0x72, 0xa4, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.cun.d $xr19, $xr22, $xr28" + - + input: + bytes: [ 0x20, 0x00, 0x92, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.ceq.s $xr0, $xr1, $xr0" + - + input: + bytes: [ 0xfd, 0x52, 0xa2, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.ceq.d $xr29, $xr23, $xr20" + - + input: + bytes: [ 0xa5, 0x7d, 0x96, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.cueq.s $xr5, $xr13, $xr31" + - + input: + bytes: [ 0xc4, 0x1e, 0xa6, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.cueq.d $xr4, $xr22, $xr7" + - + input: + bytes: [ 0x24, 0x05, 0x91, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.clt.s $xr4, $xr9, $xr1" + - + input: + bytes: [ 0x93, 0x54, 0xa1, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.clt.d $xr19, $xr4, $xr21" + - + input: + bytes: [ 0x2f, 0x0e, 0x95, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.cult.s $xr15, $xr17, $xr3" + - + input: + bytes: [ 0x34, 0x1a, 0xa5, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.cult.d $xr20, $xr17, $xr6" + - + input: + bytes: [ 0xd6, 0x3e, 0x93, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.cle.s $xr22, $xr22, $xr15" + - + input: + bytes: [ 0x35, 0x33, 0xa3, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.cle.d $xr21, $xr25, $xr12" + - + input: + bytes: [ 0x41, 0x74, 0x97, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.cule.s $xr1, $xr2, $xr29" + - + input: + bytes: [ 0xa0, 0x2c, 0xa7, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.cule.d $xr0, $xr5, $xr11" + - + input: + bytes: [ 0x27, 0x6a, 0x98, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.cne.s $xr7, $xr17, $xr26" + - + input: + bytes: [ 0x32, 0x03, 0xa8, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.cne.d $xr18, $xr25, $xr0" + - + input: + bytes: [ 0x41, 0x38, 0x9a, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.cor.s $xr1, $xr2, $xr14" + - + input: + bytes: [ 0x6c, 0x5e, 0xaa, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.cor.d $xr12, $xr19, $xr23" + - + input: + bytes: [ 0x35, 0x12, 0x9c, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.cune.s $xr21, $xr17, $xr4" + - + input: + bytes: [ 0xd4, 0x33, 0xac, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.cune.d $xr20, $xr30, $xr12" + - + input: + bytes: [ 0x77, 0x89, 0x90, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.saf.s $xr23, $xr11, $xr2" + - + input: + bytes: [ 0x87, 0x9d, 0xa0, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.saf.d $xr7, $xr12, $xr7" + - + input: + bytes: [ 0xe0, 0xf8, 0x94, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.sun.s $xr0, $xr7, $xr30" + - + input: + bytes: [ 0x64, 0xf9, 0xa4, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.sun.d $xr4, $xr11, $xr30" + - + input: + bytes: [ 0xef, 0xee, 0x92, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.seq.s $xr15, $xr23, $xr27" + - + input: + bytes: [ 0xcf, 0x8e, 0xa2, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.seq.d $xr15, $xr22, $xr3" + - + input: + bytes: [ 0x4c, 0xa7, 0x96, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.sueq.s $xr12, $xr26, $xr9" + - + input: + bytes: [ 0x45, 0xc6, 0xa6, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.sueq.d $xr5, $xr18, $xr17" + - + input: + bytes: [ 0x59, 0xfe, 0x91, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.slt.s $xr25, $xr18, $xr31" + - + input: + bytes: [ 0x51, 0xe3, 0xa1, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.slt.d $xr17, $xr26, $xr24" + - + input: + bytes: [ 0xe8, 0xc9, 0x95, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.sult.s $xr8, $xr15, $xr18" + - + input: + bytes: [ 0x84, 0x94, 0xa5, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.sult.d $xr4, $xr4, $xr5" + - + input: + bytes: [ 0xa1, 0xc0, 0x93, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.sle.s $xr1, $xr5, $xr16" + - + input: + bytes: [ 0x23, 0xdc, 0xa3, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.sle.d $xr3, $xr1, $xr23" + - + input: + bytes: [ 0x77, 0x85, 0x97, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.sule.s $xr23, $xr11, $xr1" + - + input: + bytes: [ 0x4b, 0xc5, 0xa7, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.sule.d $xr11, $xr10, $xr17" + - + input: + bytes: [ 0x9b, 0xf9, 0x98, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.sne.s $xr27, $xr12, $xr30" + - + input: + bytes: [ 0x94, 0xc6, 0xa8, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.sne.d $xr20, $xr20, $xr17" + - + input: + bytes: [ 0xab, 0x89, 0x9a, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.sor.s $xr11, $xr13, $xr2" + - + input: + bytes: [ 0x86, 0x9b, 0xaa, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.sor.d $xr6, $xr28, $xr6" + - + input: + bytes: [ 0x0b, 0xa2, 0x9c, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.sune.s $xr11, $xr16, $xr8" + - + input: + bytes: [ 0xbe, 0xec, 0xac, 0x0c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcmp.sune.d $xr30, $xr5, $xr27" diff --git a/tests/MC/LoongArch/fcvt.s.yaml b/tests/MC/LoongArch/fcvt.s.yaml new file mode 100644 index 0000000000..2316aa0948 --- /dev/null +++ b/tests/MC/LoongArch/fcvt.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0x29, 0x5e, 0x46, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcvt.h.s $xr9, $xr17, $xr23" + - + input: + bytes: [ 0x5b, 0xf5, 0x46, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcvt.s.d $xr27, $xr10, $xr29" diff --git a/tests/MC/LoongArch/fcvth.s.yaml b/tests/MC/LoongArch/fcvth.s.yaml new file mode 100644 index 0000000000..16c6d239f6 --- /dev/null +++ b/tests/MC/LoongArch/fcvth.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0x29, 0xef, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcvth.s.h $xr9, $xr25" + - + input: + bytes: [ 0x3d, 0xf6, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcvth.d.s $xr29, $xr17" diff --git a/tests/MC/LoongArch/fcvtl.s.yaml b/tests/MC/LoongArch/fcvtl.s.yaml new file mode 100644 index 0000000000..98a21d70ba --- /dev/null +++ b/tests/MC/LoongArch/fcvtl.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0xd0, 0xe9, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcvtl.s.h $xr16, $xr14" + - + input: + bytes: [ 0xb8, 0xf0, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfcvtl.d.s $xr24, $xr5" diff --git a/tests/MC/LoongArch/fdiv.s.yaml b/tests/MC/LoongArch/fdiv.s.yaml new file mode 100644 index 0000000000..1b90e55e44 --- /dev/null +++ b/tests/MC/LoongArch/fdiv.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0xbd, 0xb0, 0x3a, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfdiv.s $xr29, $xr5, $xr12" + - + input: + bytes: [ 0x5f, 0x79, 0x3b, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfdiv.d $xr31, $xr10, $xr30" diff --git a/tests/MC/LoongArch/ffint.s.yaml b/tests/MC/LoongArch/ffint.s.yaml new file mode 100644 index 0000000000..28a421a810 --- /dev/null +++ b/tests/MC/LoongArch/ffint.s.yaml @@ -0,0 +1,64 @@ +test_cases: + - + input: + bytes: [ 0xa3, 0x00, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvffint.s.w $xr3, $xr5" + - + input: + bytes: [ 0x65, 0x0a, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvffint.d.l $xr5, $xr19" + - + input: + bytes: [ 0x83, 0x07, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvffint.s.wu $xr3, $xr28" + - + input: + bytes: [ 0xbf, 0x0f, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvffint.d.lu $xr31, $xr29" + - + input: + bytes: [ 0xe2, 0x10, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvffintl.d.w $xr2, $xr7" + - + input: + bytes: [ 0x87, 0x17, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvffinth.d.w $xr7, $xr28" + - + input: + bytes: [ 0x6a, 0x0f, 0x48, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvffint.s.l $xr10, $xr27, $xr3" diff --git a/tests/MC/LoongArch/flogb.s.yaml b/tests/MC/LoongArch/flogb.s.yaml new file mode 100644 index 0000000000..77dd2a16a9 --- /dev/null +++ b/tests/MC/LoongArch/flogb.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0x91, 0xc5, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvflogb.s $xr17, $xr12" + - + input: + bytes: [ 0x3a, 0xc8, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvflogb.d $xr26, $xr1" diff --git a/tests/MC/LoongArch/fmadd.s.yaml b/tests/MC/LoongArch/fmadd.s.yaml new file mode 100644 index 0000000000..a1d79bc117 --- /dev/null +++ b/tests/MC/LoongArch/fmadd.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0xe5, 0xff, 0x1d, 0x0a ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfmadd.s $xr5, $xr31, $xr31, $xr27" + - + input: + bytes: [ 0x09, 0xfe, 0x2c, 0x0a ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfmadd.d $xr9, $xr16, $xr31, $xr25" diff --git a/tests/MC/LoongArch/fmax.s.yaml b/tests/MC/LoongArch/fmax.s.yaml new file mode 100644 index 0000000000..cb526db712 --- /dev/null +++ b/tests/MC/LoongArch/fmax.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0x1d, 0xa3, 0x3c, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfmax.s $xr29, $xr24, $xr8" + - + input: + bytes: [ 0x3f, 0x5f, 0x3d, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfmax.d $xr31, $xr25, $xr23" diff --git a/tests/MC/LoongArch/fmaxa.s.yaml b/tests/MC/LoongArch/fmaxa.s.yaml new file mode 100644 index 0000000000..a97029a1b8 --- /dev/null +++ b/tests/MC/LoongArch/fmaxa.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0x4f, 0x96, 0x40, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfmaxa.s $xr15, $xr18, $xr5" + - + input: + bytes: [ 0x82, 0x76, 0x41, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfmaxa.d $xr2, $xr20, $xr29" diff --git a/tests/MC/LoongArch/fmin.s.yaml b/tests/MC/LoongArch/fmin.s.yaml new file mode 100644 index 0000000000..d268dbca16 --- /dev/null +++ b/tests/MC/LoongArch/fmin.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0xbf, 0xc0, 0x3e, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfmin.s $xr31, $xr5, $xr16" + - + input: + bytes: [ 0xcd, 0x67, 0x3f, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfmin.d $xr13, $xr30, $xr25" diff --git a/tests/MC/LoongArch/fmina.s.yaml b/tests/MC/LoongArch/fmina.s.yaml new file mode 100644 index 0000000000..fb4c78211b --- /dev/null +++ b/tests/MC/LoongArch/fmina.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0x7d, 0xc7, 0x42, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfmina.s $xr29, $xr27, $xr17" + - + input: + bytes: [ 0x8c, 0x4a, 0x43, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfmina.d $xr12, $xr20, $xr18" diff --git a/tests/MC/LoongArch/fmsub.s.yaml b/tests/MC/LoongArch/fmsub.s.yaml new file mode 100644 index 0000000000..ad5d3ad311 --- /dev/null +++ b/tests/MC/LoongArch/fmsub.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0x71, 0x8c, 0x5b, 0x0a ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfmsub.s $xr17, $xr3, $xr3, $xr23" + - + input: + bytes: [ 0xfe, 0x41, 0x67, 0x0a ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfmsub.d $xr30, $xr15, $xr16, $xr14" diff --git a/tests/MC/LoongArch/fmul.s.yaml b/tests/MC/LoongArch/fmul.s.yaml new file mode 100644 index 0000000000..1f9a2ac3be --- /dev/null +++ b/tests/MC/LoongArch/fmul.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0xc9, 0xf9, 0x38, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfmul.s $xr9, $xr14, $xr30" + - + input: + bytes: [ 0x5c, 0x4f, 0x39, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfmul.d $xr28, $xr26, $xr19" diff --git a/tests/MC/LoongArch/fnmadd.s.yaml b/tests/MC/LoongArch/fnmadd.s.yaml new file mode 100644 index 0000000000..b5cc18bd4d --- /dev/null +++ b/tests/MC/LoongArch/fnmadd.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0xce, 0x5e, 0x9c, 0x0a ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfnmadd.s $xr14, $xr22, $xr23, $xr24" + - + input: + bytes: [ 0xc1, 0x5f, 0xa6, 0x0a ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfnmadd.d $xr1, $xr30, $xr23, $xr12" diff --git a/tests/MC/LoongArch/fnmsub.s.yaml b/tests/MC/LoongArch/fnmsub.s.yaml new file mode 100644 index 0000000000..88f6cfd99d --- /dev/null +++ b/tests/MC/LoongArch/fnmsub.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0xb6, 0x90, 0xd5, 0x0a ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfnmsub.s $xr22, $xr5, $xr4, $xr11" + - + input: + bytes: [ 0x08, 0x74, 0xee, 0x0a ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfnmsub.d $xr8, $xr0, $xr29, $xr28" diff --git a/tests/MC/LoongArch/frecip.s.yaml b/tests/MC/LoongArch/frecip.s.yaml new file mode 100644 index 0000000000..b3993750ae --- /dev/null +++ b/tests/MC/LoongArch/frecip.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x03, 0xf6, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrecip.s $xr3, $xr16" + - + input: + bytes: [ 0x11, 0xfb, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrecip.d $xr17, $xr24" + - + input: + bytes: [ 0x03, 0x16, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrecipe.s $xr3, $xr16" + - + input: + bytes: [ 0x11, 0x1b, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrecipe.d $xr17, $xr24" diff --git a/tests/MC/LoongArch/frint.s.yaml b/tests/MC/LoongArch/frint.s.yaml new file mode 100644 index 0000000000..6fa276013b --- /dev/null +++ b/tests/MC/LoongArch/frint.s.yaml @@ -0,0 +1,91 @@ +test_cases: + - + input: + bytes: [ 0x33, 0x76, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrintrne.s $xr19, $xr17" + - + input: + bytes: [ 0xac, 0x7b, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrintrne.d $xr12, $xr29" + - + input: + bytes: [ 0x2a, 0x65, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrintrz.s $xr10, $xr9" + - + input: + bytes: [ 0xbd, 0x68, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrintrz.d $xr29, $xr5" + - + input: + bytes: [ 0x1a, 0x56, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrintrp.s $xr26, $xr16" + - + input: + bytes: [ 0x81, 0x5b, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrintrp.d $xr1, $xr28" + - + input: + bytes: [ 0xbb, 0x45, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrintrm.s $xr27, $xr13" + - + input: + bytes: [ 0x6e, 0x4b, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrintrm.d $xr14, $xr27" + - + input: + bytes: [ 0x15, 0x37, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrint.s $xr21, $xr24" + - + input: + bytes: [ 0x5f, 0x3a, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrint.d $xr31, $xr18" diff --git a/tests/MC/LoongArch/frsqrt.s.yaml b/tests/MC/LoongArch/frsqrt.s.yaml new file mode 100644 index 0000000000..246b1dd5ec --- /dev/null +++ b/tests/MC/LoongArch/frsqrt.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x3f, 0x07, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrsqrt.s $xr31, $xr25" + - + input: + bytes: [ 0xce, 0x0a, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrsqrt.d $xr14, $xr22" + - + input: + bytes: [ 0x3f, 0x27, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrsqrte.s $xr31, $xr25" + - + input: + bytes: [ 0xce, 0x2a, 0x9d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrsqrte.d $xr14, $xr22" diff --git a/tests/MC/LoongArch/frstp.s.yaml b/tests/MC/LoongArch/frstp.s.yaml new file mode 100644 index 0000000000..5f9f31ca6c --- /dev/null +++ b/tests/MC/LoongArch/frstp.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x57, 0x4a, 0x2b, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrstp.b $xr23, $xr18, $xr18" + - + input: + bytes: [ 0xcd, 0x9b, 0x2b, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrstp.h $xr13, $xr30, $xr6" + - + input: + bytes: [ 0x98, 0x7f, 0x9a, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrstpi.b $xr24, $xr28, 0x1f" + - + input: + bytes: [ 0x16, 0xcb, 0x9a, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfrstpi.h $xr22, $xr24, 0x12" diff --git a/tests/MC/LoongArch/fsqrt.s.yaml b/tests/MC/LoongArch/fsqrt.s.yaml new file mode 100644 index 0000000000..5c21a00a55 --- /dev/null +++ b/tests/MC/LoongArch/fsqrt.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0x64, 0xe7, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfsqrt.s $xr4, $xr27" + - + input: + bytes: [ 0x5a, 0xe8, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfsqrt.d $xr26, $xr2" diff --git a/tests/MC/LoongArch/fsub.s.yaml b/tests/MC/LoongArch/fsub.s.yaml new file mode 100644 index 0000000000..7f8e3aef8c --- /dev/null +++ b/tests/MC/LoongArch/fsub.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0x16, 0x8c, 0x32, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfsub.s $xr22, $xr0, $xr3" + - + input: + bytes: [ 0x24, 0x3f, 0x33, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvfsub.d $xr4, $xr25, $xr15" diff --git a/tests/MC/LoongArch/ftint.s.yaml b/tests/MC/LoongArch/ftint.s.yaml new file mode 100644 index 0000000000..7f8714ed80 --- /dev/null +++ b/tests/MC/LoongArch/ftint.s.yaml @@ -0,0 +1,262 @@ +test_cases: + - + input: + bytes: [ 0xb4, 0x51, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrne.w.s $xr20, $xr13" + - + input: + bytes: [ 0xde, 0x55, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrne.l.d $xr30, $xr14" + - + input: + bytes: [ 0xae, 0x48, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrz.w.s $xr14, $xr5" + - + input: + bytes: [ 0x41, 0x4f, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrz.l.d $xr1, $xr26" + - + input: + bytes: [ 0x32, 0x40, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrp.w.s $xr18, $xr1" + - + input: + bytes: [ 0x0a, 0x47, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrp.l.d $xr10, $xr24" + - + input: + bytes: [ 0xe8, 0x3a, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrm.w.s $xr8, $xr23" + - + input: + bytes: [ 0x2c, 0x3e, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrm.l.d $xr12, $xr17" + - + input: + bytes: [ 0x2b, 0x33, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftint.w.s $xr11, $xr25" + - + input: + bytes: [ 0xc7, 0x36, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftint.l.d $xr7, $xr22" + - + input: + bytes: [ 0x6d, 0x72, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrz.wu.s $xr13, $xr19" + - + input: + bytes: [ 0x78, 0x74, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrz.lu.d $xr24, $xr3" + - + input: + bytes: [ 0xce, 0x58, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftint.wu.s $xr14, $xr6" + - + input: + bytes: [ 0x42, 0x5c, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftint.lu.d $xr2, $xr2" + - + input: + bytes: [ 0x8d, 0x96, 0x4b, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrne.w.d $xr13, $xr20, $xr5" + - + input: + bytes: [ 0x0d, 0x6d, 0x4b, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrz.w.d $xr13, $xr8, $xr27" + - + input: + bytes: [ 0x4e, 0xff, 0x4a, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrp.w.d $xr14, $xr26, $xr31" + - + input: + bytes: [ 0xfd, 0x1e, 0x4a, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrm.w.d $xr29, $xr23, $xr7" + - + input: + bytes: [ 0xc7, 0xf6, 0x49, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftint.w.d $xr7, $xr22, $xr29" + - + input: + bytes: [ 0x9f, 0xa3, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrnel.l.s $xr31, $xr28" + - + input: + bytes: [ 0xb0, 0xa7, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrneh.l.s $xr16, $xr29" + - + input: + bytes: [ 0xbb, 0x9b, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrzl.l.s $xr27, $xr29" + - + input: + bytes: [ 0x4e, 0x9d, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrzh.l.s $xr14, $xr10" + - + input: + bytes: [ 0x0e, 0x90, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrpl.l.s $xr14, $xr0" + - + input: + bytes: [ 0x17, 0x94, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrph.l.s $xr23, $xr0" + - + input: + bytes: [ 0xf6, 0x89, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrml.l.s $xr22, $xr15" + - + input: + bytes: [ 0x6a, 0x8e, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintrmh.l.s $xr10, $xr19" + - + input: + bytes: [ 0x7f, 0x81, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftintl.l.s $xr31, $xr11" + - + input: + bytes: [ 0xaf, 0x84, 0x9e, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvftinth.l.s $xr15, $xr5" diff --git a/tests/MC/LoongArch/haddw.s.yaml b/tests/MC/LoongArch/haddw.s.yaml new file mode 100644 index 0000000000..a039cf3ea6 --- /dev/null +++ b/tests/MC/LoongArch/haddw.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x7f, 0x76, 0x54, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvhaddw.h.b $xr31, $xr19, $xr29" + - + input: + bytes: [ 0x1f, 0xde, 0x54, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvhaddw.w.h $xr31, $xr16, $xr23" + - + input: + bytes: [ 0x3e, 0x60, 0x55, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvhaddw.d.w $xr30, $xr1, $xr24" + - + input: + bytes: [ 0xf0, 0xc5, 0x55, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvhaddw.q.d $xr16, $xr15, $xr17" + - + input: + bytes: [ 0x2e, 0x0a, 0x58, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvhaddw.hu.bu $xr14, $xr17, $xr2" + - + input: + bytes: [ 0x55, 0xa0, 0x58, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvhaddw.wu.hu $xr21, $xr2, $xr8" + - + input: + bytes: [ 0x06, 0x4f, 0x59, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvhaddw.du.wu $xr6, $xr24, $xr19" + - + input: + bytes: [ 0x8a, 0xb5, 0x59, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvhaddw.qu.du $xr10, $xr12, $xr13" diff --git a/tests/MC/LoongArch/hsubw.s.yaml b/tests/MC/LoongArch/hsubw.s.yaml new file mode 100644 index 0000000000..9cc827f3f0 --- /dev/null +++ b/tests/MC/LoongArch/hsubw.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0xf6, 0x40, 0x56, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvhsubw.h.b $xr22, $xr7, $xr16" + - + input: + bytes: [ 0x13, 0xbd, 0x56, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvhsubw.w.h $xr19, $xr8, $xr15" + - + input: + bytes: [ 0xfe, 0x4e, 0x57, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvhsubw.d.w $xr30, $xr23, $xr19" + - + input: + bytes: [ 0xb4, 0xf1, 0x57, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvhsubw.q.d $xr20, $xr13, $xr28" + - + input: + bytes: [ 0x4a, 0x40, 0x5a, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvhsubw.hu.bu $xr10, $xr2, $xr16" + - + input: + bytes: [ 0x41, 0xcb, 0x5a, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvhsubw.wu.hu $xr1, $xr26, $xr18" + - + input: + bytes: [ 0xe5, 0x52, 0x5b, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvhsubw.du.wu $xr5, $xr23, $xr20" + - + input: + bytes: [ 0x9f, 0xa0, 0x5b, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvhsubw.qu.du $xr31, $xr4, $xr8" diff --git a/tests/MC/LoongArch/ilv.s.yaml b/tests/MC/LoongArch/ilv.s.yaml new file mode 100644 index 0000000000..efcdff01db --- /dev/null +++ b/tests/MC/LoongArch/ilv.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0xdd, 0x01, 0x1a, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvilvl.b $xr29, $xr14, $xr0" + - + input: + bytes: [ 0x3e, 0xd5, 0x1a, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvilvl.h $xr30, $xr9, $xr21" + - + input: + bytes: [ 0xd8, 0x26, 0x1b, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvilvl.w $xr24, $xr22, $xr9" + - + input: + bytes: [ 0x99, 0xaa, 0x1b, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvilvl.d $xr25, $xr20, $xr10" + - + input: + bytes: [ 0xd3, 0x6a, 0x1c, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvilvh.b $xr19, $xr22, $xr26" + - + input: + bytes: [ 0xea, 0x9e, 0x1c, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvilvh.h $xr10, $xr23, $xr7" + - + input: + bytes: [ 0x05, 0x78, 0x1d, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvilvh.w $xr5, $xr0, $xr30" + - + input: + bytes: [ 0x58, 0x88, 0x1d, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvilvh.d $xr24, $xr2, $xr2" diff --git a/tests/MC/LoongArch/insgr2vr.s.yaml b/tests/MC/LoongArch/insgr2vr.s.yaml new file mode 100644 index 0000000000..ddbade5a0a --- /dev/null +++ b/tests/MC/LoongArch/insgr2vr.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0xd9, 0xdf, 0xeb, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvinsgr2vr.w $xr25, $s7, 7" + - + input: + bytes: [ 0xbb, 0xe6, 0xeb, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvinsgr2vr.d $xr27, $r21, 1" diff --git a/tests/MC/LoongArch/insve0.s.yaml b/tests/MC/LoongArch/insve0.s.yaml new file mode 100644 index 0000000000..3ae0564be9 --- /dev/null +++ b/tests/MC/LoongArch/insve0.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0x26, 0xdc, 0xff, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvinsve0.w $xr6, $xr1, 7" + - + input: + bytes: [ 0x3c, 0xe0, 0xff, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvinsve0.d $xr28, $xr1, 0" diff --git a/tests/MC/LoongArch/ld.s.yaml b/tests/MC/LoongArch/ld.s.yaml new file mode 100644 index 0000000000..0d95912ab7 --- /dev/null +++ b/tests/MC/LoongArch/ld.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0x63, 0xb8, 0xb5, 0x2c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvld $xr3, $sp, -0x292" + - + input: + bytes: [ 0x37, 0x39, 0x48, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvldx $xr23, $a5, $t2" diff --git a/tests/MC/LoongArch/ldrepl.s.yaml b/tests/MC/LoongArch/ldrepl.s.yaml new file mode 100644 index 0000000000..1fda523601 --- /dev/null +++ b/tests/MC/LoongArch/ldrepl.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0xb3, 0x92, 0x9d, 0x32 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvldrepl.b $xr19, $r21, 0x764" + - + input: + bytes: [ 0x20, 0xc6, 0x4d, 0x32 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvldrepl.h $xr0, $t5, 0x6e2" + - + input: + bytes: [ 0x4b, 0x0f, 0x2a, 0x32 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvldrepl.w $xr11, $s3, -0x5f4" + - + input: + bytes: [ 0x9c, 0xdd, 0x13, 0x32 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvldrepl.d $xr28, $t0, 0x7b8" diff --git a/tests/MC/LoongArch/lvz.s.yaml b/tests/MC/LoongArch/lvz.s.yaml new file mode 100644 index 0000000000..17aea18941 --- /dev/null +++ b/tests/MC/LoongArch/lvz.s.yaml @@ -0,0 +1,46 @@ +test_cases: + - + input: + bytes: [ 0x04, 0x04, 0x00, 0x05 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "gcsrrd $a0, 1" + - + input: + bytes: [ 0x24, 0x04, 0x00, 0x05 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "gcsrwr $a0, 1" + - + input: + bytes: [ 0xa4, 0x04, 0x00, 0x05 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "gcsrxchg $a0, $a1, 1" + - + input: + bytes: [ 0x01, 0x24, 0x48, 0x06 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "gtlbflush" + - + input: + bytes: [ 0x01, 0x80, 0x2b, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "hvcl 1" diff --git a/tests/MC/LoongArch/madd.s.yaml b/tests/MC/LoongArch/madd.s.yaml new file mode 100644 index 0000000000..7e59ae43b7 --- /dev/null +++ b/tests/MC/LoongArch/madd.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0xe5, 0x23, 0xa8, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmadd.b $xr5, $xr31, $xr8" + - + input: + bytes: [ 0x04, 0xf0, 0xa8, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmadd.h $xr4, $xr0, $xr28" + - + input: + bytes: [ 0xa2, 0x61, 0xa9, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmadd.w $xr2, $xr13, $xr24" + - + input: + bytes: [ 0x13, 0xc9, 0xa9, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmadd.d $xr19, $xr8, $xr18" diff --git a/tests/MC/LoongArch/maddw.s.yaml b/tests/MC/LoongArch/maddw.s.yaml new file mode 100644 index 0000000000..e3b1cbe9a8 --- /dev/null +++ b/tests/MC/LoongArch/maddw.s.yaml @@ -0,0 +1,217 @@ +test_cases: + - + input: + bytes: [ 0xf9, 0x25, 0xac, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwev.h.b $xr25, $xr15, $xr9" + - + input: + bytes: [ 0x3a, 0x80, 0xac, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwev.w.h $xr26, $xr1, $xr0" + - + input: + bytes: [ 0x17, 0x63, 0xad, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwev.d.w $xr23, $xr24, $xr24" + - + input: + bytes: [ 0x27, 0xd9, 0xad, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwev.q.d $xr7, $xr9, $xr22" + - + input: + bytes: [ 0xb7, 0x69, 0xb4, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwev.h.bu $xr23, $xr13, $xr26" + - + input: + bytes: [ 0x6d, 0x8c, 0xb4, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwev.w.hu $xr13, $xr3, $xr3" + - + input: + bytes: [ 0x7d, 0x73, 0xb5, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwev.d.wu $xr29, $xr27, $xr28" + - + input: + bytes: [ 0x5d, 0xa9, 0xb5, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwev.q.du $xr29, $xr10, $xr10" + - + input: + bytes: [ 0x5e, 0x7f, 0xbc, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwev.h.bu.b $xr30, $xr26, $xr31" + - + input: + bytes: [ 0x26, 0xfe, 0xbc, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwev.w.hu.h $xr6, $xr17, $xr31" + - + input: + bytes: [ 0x8a, 0x0b, 0xbd, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwev.d.wu.w $xr10, $xr28, $xr2" + - + input: + bytes: [ 0x90, 0xe2, 0xbd, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwev.q.du.d $xr16, $xr20, $xr24" + - + input: + bytes: [ 0x10, 0x49, 0xae, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwod.h.b $xr16, $xr8, $xr18" + - + input: + bytes: [ 0x0b, 0xbb, 0xae, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwod.w.h $xr11, $xr24, $xr14" + - + input: + bytes: [ 0x80, 0x36, 0xaf, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwod.d.w $xr0, $xr20, $xr13" + - + input: + bytes: [ 0xef, 0xca, 0xaf, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwod.q.d $xr15, $xr23, $xr18" + - + input: + bytes: [ 0xff, 0x1e, 0xb6, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwod.h.bu $xr31, $xr23, $xr7" + - + input: + bytes: [ 0x1d, 0xa2, 0xb6, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwod.w.hu $xr29, $xr16, $xr8" + - + input: + bytes: [ 0x17, 0x2e, 0xb7, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwod.d.wu $xr23, $xr16, $xr11" + - + input: + bytes: [ 0x49, 0xcd, 0xb7, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwod.q.du $xr9, $xr10, $xr19" + - + input: + bytes: [ 0x5b, 0x2c, 0xbe, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwod.h.bu.b $xr27, $xr2, $xr11" + - + input: + bytes: [ 0x0c, 0xcf, 0xbe, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwod.w.hu.h $xr12, $xr24, $xr19" + - + input: + bytes: [ 0x0b, 0x38, 0xbf, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwod.d.wu.w $xr11, $xr0, $xr14" + - + input: + bytes: [ 0x7d, 0xfe, 0xbf, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaddwod.q.du.d $xr29, $xr19, $xr31" diff --git a/tests/MC/LoongArch/max.s.yaml b/tests/MC/LoongArch/max.s.yaml new file mode 100644 index 0000000000..cfeef1a8db --- /dev/null +++ b/tests/MC/LoongArch/max.s.yaml @@ -0,0 +1,145 @@ +test_cases: + - + input: + bytes: [ 0x17, 0x35, 0x70, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmax.b $xr23, $xr8, $xr13" + - + input: + bytes: [ 0x4d, 0xf2, 0x70, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmax.h $xr13, $xr18, $xr28" + - + input: + bytes: [ 0x3a, 0x08, 0x71, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmax.w $xr26, $xr1, $xr2" + - + input: + bytes: [ 0x22, 0xb6, 0x71, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmax.d $xr2, $xr17, $xr13" + - + input: + bytes: [ 0xe6, 0x04, 0x90, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaxi.b $xr6, $xr7, 1" + - + input: + bytes: [ 0x58, 0xe5, 0x90, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaxi.h $xr24, $xr10, -7" + - + input: + bytes: [ 0x58, 0x62, 0x91, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaxi.w $xr24, $xr18, -8" + - + input: + bytes: [ 0xb5, 0xd4, 0x91, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaxi.d $xr21, $xr5, -0xb" + - + input: + bytes: [ 0xdd, 0x2f, 0x74, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmax.bu $xr29, $xr30, $xr11" + - + input: + bytes: [ 0xe4, 0xee, 0x74, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmax.hu $xr4, $xr23, $xr27" + - + input: + bytes: [ 0x1f, 0x00, 0x75, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmax.wu $xr31, $xr0, $xr0" + - + input: + bytes: [ 0xc5, 0xa6, 0x75, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmax.du $xr5, $xr22, $xr9" + - + input: + bytes: [ 0x6c, 0x73, 0x94, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaxi.bu $xr12, $xr27, 0x1c" + - + input: + bytes: [ 0x99, 0xc0, 0x94, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaxi.hu $xr25, $xr4, 0x10" + - + input: + bytes: [ 0xfb, 0x54, 0x95, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaxi.wu $xr27, $xr7, 0x15" + - + input: + bytes: [ 0xbf, 0xa5, 0x95, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmaxi.du $xr31, $xr13, 0x9" diff --git a/tests/MC/LoongArch/memory.s.yaml b/tests/MC/LoongArch/memory.s.yaml new file mode 100644 index 0000000000..0b99c88e3e --- /dev/null +++ b/tests/MC/LoongArch/memory.s.yaml @@ -0,0 +1,82 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x55, 0x00, 0x28 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ld.b $s1, $a4, 0x15" + - + input: + bytes: [ 0x47, 0x42, 0x41, 0x28 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ld.h $a3, $t6, 0x50" + - + input: + bytes: [ 0x52, 0x73, 0x81, 0x28 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ld.w $t6, $s3, 0x5c" + - + input: + bytes: [ 0xad, 0x59, 0x02, 0x2a ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ld.bu $t1, $t1, 0x96" + - + input: + bytes: [ 0xb2, 0x1b, 0x43, 0x2a ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ld.hu $t6, $s6, 0xc6" + - + input: + bytes: [ 0xe3, 0x7c, 0x01, 0x29 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "st.b $sp, $a3, 0x5f" + - + input: + bytes: [ 0x19, 0xea, 0x41, 0x29 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "st.h $s2, $t4, 0x7a" + - + input: + bytes: [ 0xad, 0xbd, 0x82, 0x29 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "st.w $t1, $t1, 0xaf" + - + input: + bytes: [ 0x0a, 0x5c, 0xc0, 0x2a ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "preld 0xa, $zero, 0x17" diff --git a/tests/MC/LoongArch/min.s.yaml b/tests/MC/LoongArch/min.s.yaml new file mode 100644 index 0000000000..9a94cacb58 --- /dev/null +++ b/tests/MC/LoongArch/min.s.yaml @@ -0,0 +1,145 @@ +test_cases: + - + input: + bytes: [ 0x55, 0x1f, 0x72, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmin.b $xr21, $xr26, $xr7" + - + input: + bytes: [ 0xbd, 0xa4, 0x72, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmin.h $xr29, $xr5, $xr9" + - + input: + bytes: [ 0x1f, 0x53, 0x73, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmin.w $xr31, $xr24, $xr20" + - + input: + bytes: [ 0x7b, 0x8b, 0x73, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmin.d $xr27, $xr27, $xr2" + - + input: + bytes: [ 0x36, 0x26, 0x92, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmini.b $xr22, $xr17, 0x9" + - + input: + bytes: [ 0xec, 0xc6, 0x92, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmini.h $xr12, $xr23, -0xf" + - + input: + bytes: [ 0x21, 0x4e, 0x93, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmini.w $xr1, $xr17, -0xd" + - + input: + bytes: [ 0xea, 0xaf, 0x93, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmini.d $xr10, $xr31, 0xb" + - + input: + bytes: [ 0x0f, 0x0e, 0x76, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmin.bu $xr15, $xr16, $xr3" + - + input: + bytes: [ 0xe4, 0xef, 0x76, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmin.hu $xr4, $xr31, $xr27" + - + input: + bytes: [ 0xaf, 0x71, 0x77, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmin.wu $xr15, $xr13, $xr28" + - + input: + bytes: [ 0x7b, 0x94, 0x77, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmin.du $xr27, $xr3, $xr5" + - + input: + bytes: [ 0x06, 0x1f, 0x96, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmini.bu $xr6, $xr24, 7" + - + input: + bytes: [ 0xa8, 0xf4, 0x96, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmini.hu $xr8, $xr5, 0x1d" + - + input: + bytes: [ 0xb1, 0x4d, 0x97, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmini.wu $xr17, $xr13, 0x13" + - + input: + bytes: [ 0xf0, 0xfa, 0x97, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmini.du $xr16, $xr23, 0x1e" diff --git a/tests/MC/LoongArch/misc.s.yaml b/tests/MC/LoongArch/misc.s.yaml new file mode 100644 index 0000000000..5e798ba9f6 --- /dev/null +++ b/tests/MC/LoongArch/misc.s.yaml @@ -0,0 +1,46 @@ +test_cases: + - + input: + bytes: [ 0x64, 0x00, 0x2b, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "syscall 0x64" + - + input: + bytes: [ 0xc7, 0x00, 0x2a, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "break 0xc7" + - + input: + bytes: [ 0x98, 0x60, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "rdtimel.w $s1, $a0" + - + input: + bytes: [ 0xab, 0x64, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "rdtimeh.w $a7, $a1" + - + input: + bytes: [ 0x03, 0x6d, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "cpucfg $sp, $a4" diff --git a/tests/MC/LoongArch/mod.s.yaml b/tests/MC/LoongArch/mod.s.yaml new file mode 100644 index 0000000000..bd2910edc5 --- /dev/null +++ b/tests/MC/LoongArch/mod.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x68, 0x00, 0xe2, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmod.b $xr8, $xr3, $xr0" + - + input: + bytes: [ 0x22, 0xf2, 0xe2, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmod.h $xr2, $xr17, $xr28" + - + input: + bytes: [ 0x0e, 0x35, 0xe3, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmod.w $xr14, $xr8, $xr13" + - + input: + bytes: [ 0x4b, 0xc9, 0xe3, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmod.d $xr11, $xr10, $xr18" + - + input: + bytes: [ 0x30, 0x68, 0xe6, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmod.bu $xr16, $xr1, $xr26" + - + input: + bytes: [ 0xaf, 0x81, 0xe6, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmod.hu $xr15, $xr13, $xr0" + - + input: + bytes: [ 0x6b, 0x52, 0xe7, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmod.wu $xr11, $xr19, $xr20" + - + input: + bytes: [ 0x6e, 0x98, 0xe7, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmod.du $xr14, $xr3, $xr6" diff --git a/tests/MC/LoongArch/mskgez.s.yaml b/tests/MC/LoongArch/mskgez.s.yaml new file mode 100644 index 0000000000..4087103efa --- /dev/null +++ b/tests/MC/LoongArch/mskgez.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xbe, 0x50, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmskgez.b $xr30, $xr5" diff --git a/tests/MC/LoongArch/mskltz.s.yaml b/tests/MC/LoongArch/mskltz.s.yaml new file mode 100644 index 0000000000..a171348ff2 --- /dev/null +++ b/tests/MC/LoongArch/mskltz.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0xae, 0x40, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmskltz.b $xr14, $xr5" + - + input: + bytes: [ 0x2b, 0x47, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmskltz.h $xr11, $xr25" + - + input: + bytes: [ 0x6e, 0x4b, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmskltz.w $xr14, $xr27" + - + input: + bytes: [ 0xe7, 0x4e, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmskltz.d $xr7, $xr23" diff --git a/tests/MC/LoongArch/msknz.s.yaml b/tests/MC/LoongArch/msknz.s.yaml new file mode 100644 index 0000000000..c78cf32494 --- /dev/null +++ b/tests/MC/LoongArch/msknz.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xd6, 0x62, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmsknz.b $xr22, $xr22" diff --git a/tests/MC/LoongArch/msub.s.yaml b/tests/MC/LoongArch/msub.s.yaml new file mode 100644 index 0000000000..033691c37e --- /dev/null +++ b/tests/MC/LoongArch/msub.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x96, 0x1e, 0xaa, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmsub.b $xr22, $xr20, $xr7" + - + input: + bytes: [ 0x40, 0xb2, 0xaa, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmsub.h $xr0, $xr18, $xr12" + - + input: + bytes: [ 0xc3, 0x76, 0xab, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmsub.w $xr3, $xr22, $xr29" + - + input: + bytes: [ 0x4b, 0x8b, 0xab, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmsub.d $xr11, $xr26, $xr2" diff --git a/tests/MC/LoongArch/muh.s.yaml b/tests/MC/LoongArch/muh.s.yaml new file mode 100644 index 0000000000..1393272de8 --- /dev/null +++ b/tests/MC/LoongArch/muh.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x04, 0x11, 0x86, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmuh.b $xr4, $xr8, $xr4" + - + input: + bytes: [ 0xe5, 0xea, 0x86, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmuh.h $xr5, $xr23, $xr26" + - + input: + bytes: [ 0x7c, 0x64, 0x87, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmuh.w $xr28, $xr3, $xr25" + - + input: + bytes: [ 0x06, 0xa4, 0x87, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmuh.d $xr6, $xr0, $xr9" + - + input: + bytes: [ 0x8f, 0x62, 0x88, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmuh.bu $xr15, $xr20, $xr24" + - + input: + bytes: [ 0x9c, 0xed, 0x88, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmuh.hu $xr28, $xr12, $xr27" + - + input: + bytes: [ 0xd9, 0x28, 0x89, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmuh.wu $xr25, $xr6, $xr10" + - + input: + bytes: [ 0x13, 0xfd, 0x89, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmuh.du $xr19, $xr8, $xr31" diff --git a/tests/MC/LoongArch/mul.s.yaml b/tests/MC/LoongArch/mul.s.yaml new file mode 100644 index 0000000000..03b0be4346 --- /dev/null +++ b/tests/MC/LoongArch/mul.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0xf2, 0x6c, 0x84, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmul.b $xr18, $xr7, $xr27" + - + input: + bytes: [ 0xe9, 0xca, 0x84, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmul.h $xr9, $xr23, $xr18" + - + input: + bytes: [ 0x15, 0x6d, 0x85, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmul.w $xr21, $xr8, $xr27" + - + input: + bytes: [ 0xe0, 0xa1, 0x85, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmul.d $xr0, $xr15, $xr8" diff --git a/tests/MC/LoongArch/mulw.s.yaml b/tests/MC/LoongArch/mulw.s.yaml new file mode 100644 index 0000000000..95a32ade74 --- /dev/null +++ b/tests/MC/LoongArch/mulw.s.yaml @@ -0,0 +1,217 @@ +test_cases: + - + input: + bytes: [ 0xe2, 0x40, 0x90, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwev.h.b $xr2, $xr7, $xr16" + - + input: + bytes: [ 0x6c, 0x99, 0x90, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwev.w.h $xr12, $xr11, $xr6" + - + input: + bytes: [ 0x10, 0x3f, 0x91, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwev.d.w $xr16, $xr24, $xr15" + - + input: + bytes: [ 0x11, 0x92, 0x91, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwev.q.d $xr17, $xr16, $xr4" + - + input: + bytes: [ 0xf4, 0x74, 0x98, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwev.h.bu $xr20, $xr7, $xr29" + - + input: + bytes: [ 0x0d, 0xc7, 0x98, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwev.w.hu $xr13, $xr24, $xr17" + - + input: + bytes: [ 0x01, 0x7b, 0x99, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwev.d.wu $xr1, $xr24, $xr30" + - + input: + bytes: [ 0xc1, 0xee, 0x99, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwev.q.du $xr1, $xr22, $xr27" + - + input: + bytes: [ 0x8d, 0x33, 0xa0, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwev.h.bu.b $xr13, $xr28, $xr12" + - + input: + bytes: [ 0x1b, 0x9e, 0xa0, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwev.w.hu.h $xr27, $xr16, $xr7" + - + input: + bytes: [ 0xed, 0x44, 0xa1, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwev.d.wu.w $xr13, $xr7, $xr17" + - + input: + bytes: [ 0x89, 0xbe, 0xa1, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwev.q.du.d $xr9, $xr20, $xr15" + - + input: + bytes: [ 0x50, 0x0a, 0x92, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwod.h.b $xr16, $xr18, $xr2" + - + input: + bytes: [ 0x5e, 0xdc, 0x92, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwod.w.h $xr30, $xr2, $xr23" + - + input: + bytes: [ 0x7e, 0x23, 0x93, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwod.d.w $xr30, $xr27, $xr8" + - + input: + bytes: [ 0xb4, 0xbe, 0x93, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwod.q.d $xr20, $xr21, $xr15" + - + input: + bytes: [ 0x53, 0x1f, 0x9a, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwod.h.bu $xr19, $xr26, $xr7" + - + input: + bytes: [ 0x2e, 0x9a, 0x9a, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwod.w.hu $xr14, $xr17, $xr6" + - + input: + bytes: [ 0xd8, 0x52, 0x9b, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwod.d.wu $xr24, $xr22, $xr20" + - + input: + bytes: [ 0xfc, 0x9f, 0x9b, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwod.q.du $xr28, $xr31, $xr7" + - + input: + bytes: [ 0xf8, 0x71, 0xa2, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwod.h.bu.b $xr24, $xr15, $xr28" + - + input: + bytes: [ 0x18, 0x85, 0xa2, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwod.w.hu.h $xr24, $xr8, $xr1" + - + input: + bytes: [ 0x6a, 0x04, 0xa3, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwod.d.wu.w $xr10, $xr3, $xr1" + - + input: + bytes: [ 0xef, 0x89, 0xa3, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvmulwod.q.du.d $xr15, $xr15, $xr2" diff --git a/tests/MC/LoongArch/neg.s.yaml b/tests/MC/LoongArch/neg.s.yaml new file mode 100644 index 0000000000..caa0fc59e1 --- /dev/null +++ b/tests/MC/LoongArch/neg.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x97, 0x30, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvneg.b $xr23, $xr4" + - + input: + bytes: [ 0xc8, 0x35, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvneg.h $xr8, $xr14" + - + input: + bytes: [ 0xd7, 0x39, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvneg.w $xr23, $xr14" + - + input: + bytes: [ 0x34, 0x3e, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvneg.d $xr20, $xr17" diff --git a/tests/MC/LoongArch/nor.s.yaml b/tests/MC/LoongArch/nor.s.yaml new file mode 100644 index 0000000000..243c22b1c7 --- /dev/null +++ b/tests/MC/LoongArch/nor.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xe4, 0x8e, 0x27, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvnor.v $xr4, $xr23, $xr3" diff --git a/tests/MC/LoongArch/nori.s.yaml b/tests/MC/LoongArch/nori.s.yaml new file mode 100644 index 0000000000..0db9dbd661 --- /dev/null +++ b/tests/MC/LoongArch/nori.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x27, 0x44, 0xdf, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvnori.b $xr7, $xr1, 0xd1" diff --git a/tests/MC/LoongArch/or.s.yaml b/tests/MC/LoongArch/or.s.yaml new file mode 100644 index 0000000000..8b3648c288 --- /dev/null +++ b/tests/MC/LoongArch/or.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xa6, 0xd7, 0x26, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvor.v $xr6, $xr29, $xr21" diff --git a/tests/MC/LoongArch/ori.s.yaml b/tests/MC/LoongArch/ori.s.yaml new file mode 100644 index 0000000000..e4cb314491 --- /dev/null +++ b/tests/MC/LoongArch/ori.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x46, 0xbc, 0xd7, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvori.b $xr6, $xr2, 0xef" diff --git a/tests/MC/LoongArch/orn.s.yaml b/tests/MC/LoongArch/orn.s.yaml new file mode 100644 index 0000000000..b8a527a037 --- /dev/null +++ b/tests/MC/LoongArch/orn.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xb1, 0x97, 0x28, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvorn.v $xr17, $xr29, $xr5" diff --git a/tests/MC/LoongArch/pack.s.yaml b/tests/MC/LoongArch/pack.s.yaml new file mode 100644 index 0000000000..1eb1697045 --- /dev/null +++ b/tests/MC/LoongArch/pack.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x55, 0x20, 0x16, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpackev.b $xr21, $xr2, $xr8" + - + input: + bytes: [ 0x48, 0x9a, 0x16, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpackev.h $xr8, $xr18, $xr6" + - + input: + bytes: [ 0xc0, 0x78, 0x17, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpackev.w $xr0, $xr6, $xr30" + - + input: + bytes: [ 0x20, 0x91, 0x17, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpackev.d $xr0, $xr9, $xr4" + - + input: + bytes: [ 0xbc, 0x7f, 0x18, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpackod.b $xr28, $xr29, $xr31" + - + input: + bytes: [ 0x4e, 0x99, 0x18, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpackod.h $xr14, $xr10, $xr6" + - + input: + bytes: [ 0xb6, 0x0a, 0x19, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpackod.w $xr22, $xr21, $xr2" + - + input: + bytes: [ 0x32, 0x89, 0x19, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpackod.d $xr18, $xr9, $xr2" diff --git a/tests/MC/LoongArch/pcnt.s.yaml b/tests/MC/LoongArch/pcnt.s.yaml new file mode 100644 index 0000000000..b2cb8e77ee --- /dev/null +++ b/tests/MC/LoongArch/pcnt.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x68, 0x23, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpcnt.b $xr8, $xr27" + - + input: + bytes: [ 0x8c, 0x24, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpcnt.h $xr12, $xr4" + - + input: + bytes: [ 0xff, 0x2a, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpcnt.w $xr31, $xr23" + - + input: + bytes: [ 0x9a, 0x2d, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpcnt.d $xr26, $xr12" diff --git a/tests/MC/LoongArch/perm.s.yaml b/tests/MC/LoongArch/perm.s.yaml new file mode 100644 index 0000000000..d5c8f3a590 --- /dev/null +++ b/tests/MC/LoongArch/perm.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xf8, 0x42, 0x7d, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvperm.w $xr24, $xr23, $xr16" diff --git a/tests/MC/LoongArch/permi.s.yaml b/tests/MC/LoongArch/permi.s.yaml new file mode 100644 index 0000000000..ee04cf4801 --- /dev/null +++ b/tests/MC/LoongArch/permi.s.yaml @@ -0,0 +1,28 @@ +test_cases: + - + input: + bytes: [ 0x87, 0x95, 0xe5, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpermi.w $xr7, $xr12, 0x65" + - + input: + bytes: [ 0xd1, 0x0c, 0xea, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpermi.d $xr17, $xr6, 0x83" + - + input: + bytes: [ 0xea, 0xe1, 0xee, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpermi.q $xr10, $xr15, 0xb8" diff --git a/tests/MC/LoongArch/pick.s.yaml b/tests/MC/LoongArch/pick.s.yaml new file mode 100644 index 0000000000..3edb7d2cab --- /dev/null +++ b/tests/MC/LoongArch/pick.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x76, 0x1b, 0x1e, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpickev.b $xr22, $xr27, $xr6" + - + input: + bytes: [ 0x6e, 0x8d, 0x1e, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpickev.h $xr14, $xr11, $xr3" + - + input: + bytes: [ 0x9e, 0x37, 0x1f, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpickev.w $xr30, $xr28, $xr13" + - + input: + bytes: [ 0x01, 0xa7, 0x1f, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpickev.d $xr1, $xr24, $xr9" + - + input: + bytes: [ 0xce, 0x3e, 0x20, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpickod.b $xr14, $xr22, $xr15" + - + input: + bytes: [ 0xbf, 0xb2, 0x20, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpickod.h $xr31, $xr21, $xr12" + - + input: + bytes: [ 0x1f, 0x78, 0x21, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpickod.w $xr31, $xr0, $xr30" + - + input: + bytes: [ 0xaa, 0xc0, 0x21, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpickod.d $xr10, $xr5, $xr16" diff --git a/tests/MC/LoongArch/pickve.s.yaml b/tests/MC/LoongArch/pickve.s.yaml new file mode 100644 index 0000000000..2d538fcb18 --- /dev/null +++ b/tests/MC/LoongArch/pickve.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0x99, 0xc7, 0x03, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpickve.w $xr25, $xr28, 1" + - + input: + bytes: [ 0x2d, 0xe0, 0x03, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpickve.d $xr13, $xr1, 0" diff --git a/tests/MC/LoongArch/pickve2gr.s.yaml b/tests/MC/LoongArch/pickve2gr.s.yaml new file mode 100644 index 0000000000..f12c084ea1 --- /dev/null +++ b/tests/MC/LoongArch/pickve2gr.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x6e, 0xd9, 0xef, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpickve2gr.w $t2, $xr11, 6" + - + input: + bytes: [ 0xc8, 0xe0, 0xef, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpickve2gr.d $a4, $xr6, 0" + - + input: + bytes: [ 0x2c, 0xd0, 0xf3, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpickve2gr.wu $t0, $xr1, 4" + - + input: + bytes: [ 0x0a, 0xe1, 0xf3, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvpickve2gr.du $a6, $xr8, 0" diff --git a/tests/MC/LoongArch/pseudos.s.yaml b/tests/MC/LoongArch/pseudos.s.yaml new file mode 100644 index 0000000000..ddfba27287 --- /dev/null +++ b/tests/MC/LoongArch/pseudos.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x28, 0x01, 0x15, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "move $a4, $a5" diff --git a/tests/MC/LoongArch/repl128vei.s.yaml b/tests/MC/LoongArch/repl128vei.s.yaml new file mode 100644 index 0000000000..ded5f1c297 --- /dev/null +++ b/tests/MC/LoongArch/repl128vei.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x6a, 0x8a, 0xf7, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvrepl128vei.b $xr10, $xr19, 2" + - + input: + bytes: [ 0x66, 0xca, 0xf7, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvrepl128vei.h $xr6, $xr19, 2" + - + input: + bytes: [ 0xab, 0xe5, 0xf7, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvrepl128vei.w $xr11, $xr13, 1" + - + input: + bytes: [ 0xff, 0xf2, 0xf7, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvrepl128vei.d $xr31, $xr23, 0" diff --git a/tests/MC/LoongArch/replgr2vr.s.yaml b/tests/MC/LoongArch/replgr2vr.s.yaml new file mode 100644 index 0000000000..9b5ca41c70 --- /dev/null +++ b/tests/MC/LoongArch/replgr2vr.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x02, 0x9f, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvreplgr2vr.b $xr16, $t4" + - + input: + bytes: [ 0xc7, 0x06, 0x9f, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvreplgr2vr.h $xr7, $fp" + - + input: + bytes: [ 0xe4, 0x09, 0x9f, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvreplgr2vr.w $xr4, $t3" + - + input: + bytes: [ 0x10, 0x0f, 0x9f, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvreplgr2vr.d $xr16, $s1" diff --git a/tests/MC/LoongArch/replve.s.yaml b/tests/MC/LoongArch/replve.s.yaml new file mode 100644 index 0000000000..501c2a2b79 --- /dev/null +++ b/tests/MC/LoongArch/replve.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x14, 0x2e, 0x22, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvreplve.b $xr20, $xr16, $a7" + - + input: + bytes: [ 0xa0, 0xe2, 0x22, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvreplve.h $xr0, $xr21, $s1" + - + input: + bytes: [ 0x54, 0x4a, 0x23, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvreplve.w $xr20, $xr18, $t6" + - + input: + bytes: [ 0x64, 0xdc, 0x23, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvreplve.d $xr4, $xr3, $s0" diff --git a/tests/MC/LoongArch/replve0.s.yaml b/tests/MC/LoongArch/replve0.s.yaml new file mode 100644 index 0000000000..fa826a2359 --- /dev/null +++ b/tests/MC/LoongArch/replve0.s.yaml @@ -0,0 +1,46 @@ +test_cases: + - + input: + bytes: [ 0x8b, 0x02, 0x07, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvreplve0.b $xr11, $xr20" + - + input: + bytes: [ 0x4d, 0x83, 0x07, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvreplve0.h $xr13, $xr26" + - + input: + bytes: [ 0x88, 0xc1, 0x07, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvreplve0.w $xr8, $xr12" + - + input: + bytes: [ 0x94, 0xe0, 0x07, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvreplve0.d $xr20, $xr4" + - + input: + bytes: [ 0x91, 0xf2, 0x07, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvreplve0.q $xr17, $xr20" diff --git a/tests/MC/LoongArch/replvei.s.yaml b/tests/MC/LoongArch/replvei.s.yaml new file mode 100644 index 0000000000..f39904fabb --- /dev/null +++ b/tests/MC/LoongArch/replvei.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x77, 0x8c, 0xf7, 0x72 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "vreplvei.b $vr23, $vr3, 3" + - + input: + bytes: [ 0x1b, 0xc2, 0xf7, 0x72 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "vreplvei.h $vr27, $vr16, 0" + - + input: + bytes: [ 0xf2, 0xee, 0xf7, 0x72 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "vreplvei.w $vr18, $vr23, 3" + - + input: + bytes: [ 0x8f, 0xf5, 0xf7, 0x72 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "vreplvei.d $vr15, $vr12, 1" diff --git a/tests/MC/LoongArch/rotr.s.yaml b/tests/MC/LoongArch/rotr.s.yaml new file mode 100644 index 0000000000..00dd20aa77 --- /dev/null +++ b/tests/MC/LoongArch/rotr.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0xc0, 0x78, 0xee, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvrotr.b $xr0, $xr6, $xr30" + - + input: + bytes: [ 0x33, 0xaa, 0xee, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvrotr.h $xr19, $xr17, $xr10" + - + input: + bytes: [ 0x52, 0x1c, 0xef, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvrotr.w $xr18, $xr2, $xr7" + - + input: + bytes: [ 0xeb, 0xae, 0xef, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvrotr.d $xr11, $xr23, $xr11" + - + input: + bytes: [ 0xa1, 0x2c, 0xa0, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvrotri.b $xr1, $xr5, 3" + - + input: + bytes: [ 0x21, 0x4e, 0xa0, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvrotri.h $xr1, $xr17, 3" + - + input: + bytes: [ 0xf9, 0xce, 0xa0, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvrotri.w $xr25, $xr23, 0x13" + - + input: + bytes: [ 0x07, 0x97, 0xa1, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvrotri.d $xr7, $xr24, 0x25" diff --git a/tests/MC/LoongArch/sadd.s.yaml b/tests/MC/LoongArch/sadd.s.yaml new file mode 100644 index 0000000000..bf6d0457ac --- /dev/null +++ b/tests/MC/LoongArch/sadd.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0xdb, 0x5b, 0x46, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsadd.b $xr27, $xr30, $xr22" + - + input: + bytes: [ 0x1d, 0x84, 0x46, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsadd.h $xr29, $xr0, $xr1" + - + input: + bytes: [ 0x96, 0x7f, 0x47, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsadd.w $xr22, $xr28, $xr31" + - + input: + bytes: [ 0x45, 0xea, 0x47, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsadd.d $xr5, $xr18, $xr26" + - + input: + bytes: [ 0x9d, 0x72, 0x4a, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsadd.bu $xr29, $xr20, $xr28" + - + input: + bytes: [ 0x07, 0x9a, 0x4a, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsadd.hu $xr7, $xr16, $xr6" + - + input: + bytes: [ 0x42, 0x3d, 0x4b, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsadd.wu $xr2, $xr10, $xr15" + - + input: + bytes: [ 0x12, 0xbb, 0x4b, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsadd.du $xr18, $xr24, $xr14" diff --git a/tests/MC/LoongArch/sat.s.yaml b/tests/MC/LoongArch/sat.s.yaml new file mode 100644 index 0000000000..ec1826df8b --- /dev/null +++ b/tests/MC/LoongArch/sat.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0xf6, 0x28, 0x24, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsat.b $xr22, $xr7, 2" + - + input: + bytes: [ 0x03, 0x54, 0x24, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsat.h $xr3, $xr0, 5" + - + input: + bytes: [ 0x09, 0x82, 0x24, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsat.w $xr9, $xr16, 0" + - + input: + bytes: [ 0x03, 0x05, 0x25, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsat.d $xr3, $xr8, 1" + - + input: + bytes: [ 0xc6, 0x30, 0x28, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsat.bu $xr6, $xr6, 4" + - + input: + bytes: [ 0x2c, 0x73, 0x28, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsat.hu $xr12, $xr25, 0xc" + - + input: + bytes: [ 0x34, 0x8c, 0x28, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsat.wu $xr20, $xr1, 3" + - + input: + bytes: [ 0x85, 0x1e, 0x29, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsat.du $xr5, $xr20, 7" diff --git a/tests/MC/LoongArch/scr.s.yaml b/tests/MC/LoongArch/scr.s.yaml new file mode 100644 index 0000000000..6ed0db59f1 --- /dev/null +++ b/tests/MC/LoongArch/scr.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0xa0, 0x08, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "movgr2scr $scr0, $a1" + - + input: + bytes: [ 0x24, 0x0c, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "movscr2gr $a0, $scr1" + - + input: + bytes: [ 0x00, 0x66, 0x00, 0x48 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "jiscr0 0x64" + - + input: + bytes: [ 0x00, 0x67, 0x00, 0x48 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "jiscr1 0x64" diff --git a/tests/MC/LoongArch/seq.s.yaml b/tests/MC/LoongArch/seq.s.yaml new file mode 100644 index 0000000000..a947109ac9 --- /dev/null +++ b/tests/MC/LoongArch/seq.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x83, 0x4c, 0x00, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvseq.b $xr3, $xr4, $xr19" + - + input: + bytes: [ 0xa0, 0x96, 0x00, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvseq.h $xr0, $xr21, $xr5" + - + input: + bytes: [ 0x06, 0x4e, 0x01, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvseq.w $xr6, $xr16, $xr19" + - + input: + bytes: [ 0xa8, 0xb5, 0x01, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvseq.d $xr8, $xr13, $xr13" + - + input: + bytes: [ 0x2c, 0x03, 0x80, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvseqi.b $xr12, $xr25, 0" + - + input: + bytes: [ 0x89, 0xa8, 0x80, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvseqi.h $xr9, $xr4, 0xa" + - + input: + bytes: [ 0x99, 0x50, 0x81, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvseqi.w $xr25, $xr4, -0xc" + - + input: + bytes: [ 0xeb, 0x9c, 0x81, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvseqi.d $xr11, $xr7, 7" diff --git a/tests/MC/LoongArch/set.s.yaml b/tests/MC/LoongArch/set.s.yaml new file mode 100644 index 0000000000..9346ffbc60 --- /dev/null +++ b/tests/MC/LoongArch/set.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0x27, 0x98, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvseteqz.v $fcc7, $xr1" + - + input: + bytes: [ 0xa7, 0x9d, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsetnez.v $fcc7, $xr13" diff --git a/tests/MC/LoongArch/setallnez.s.yaml b/tests/MC/LoongArch/setallnez.s.yaml new file mode 100644 index 0000000000..c90655bd4f --- /dev/null +++ b/tests/MC/LoongArch/setallnez.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0xa5, 0xb3, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsetallnez.b $fcc5, $xr29" + - + input: + bytes: [ 0x85, 0xb4, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsetallnez.h $fcc5, $xr4" + - + input: + bytes: [ 0xa4, 0xb8, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsetallnez.w $fcc4, $xr5" + - + input: + bytes: [ 0x87, 0xbe, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsetallnez.d $fcc7, $xr20" diff --git a/tests/MC/LoongArch/setanyeqz.s.yaml b/tests/MC/LoongArch/setanyeqz.s.yaml new file mode 100644 index 0000000000..fbd7656ff0 --- /dev/null +++ b/tests/MC/LoongArch/setanyeqz.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x05, 0xa1, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsetanyeqz.b $fcc5, $xr8" + - + input: + bytes: [ 0x85, 0xa6, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsetanyeqz.h $fcc5, $xr20" + - + input: + bytes: [ 0xc7, 0xa8, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsetanyeqz.w $fcc7, $xr6" + - + input: + bytes: [ 0x26, 0xae, 0x9c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsetanyeqz.d $fcc6, $xr17" diff --git a/tests/MC/LoongArch/shuf.s.yaml b/tests/MC/LoongArch/shuf.s.yaml new file mode 100644 index 0000000000..2d77d9bd46 --- /dev/null +++ b/tests/MC/LoongArch/shuf.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0xd4, 0xac, 0x67, 0x0d ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvshuf.b $xr20, $xr6, $xr11, $xr15" + - + input: + bytes: [ 0x1d, 0x87, 0x7a, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvshuf.h $xr29, $xr24, $xr1" + - + input: + bytes: [ 0x0f, 0x77, 0x7b, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvshuf.w $xr15, $xr24, $xr29" + - + input: + bytes: [ 0x5b, 0xbe, 0x7b, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvshuf.d $xr27, $xr18, $xr15" diff --git a/tests/MC/LoongArch/shuf4i.s.yaml b/tests/MC/LoongArch/shuf4i.s.yaml new file mode 100644 index 0000000000..f8ede46e4e --- /dev/null +++ b/tests/MC/LoongArch/shuf4i.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x95, 0xa3, 0x92, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvshuf4i.b $xr21, $xr28, 0xa8" + - + input: + bytes: [ 0x72, 0x58, 0x94, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvshuf4i.h $xr18, $xr3, 0x16" + - + input: + bytes: [ 0x20, 0x4b, 0x99, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvshuf4i.w $xr0, $xr25, 0x52" + - + input: + bytes: [ 0x98, 0x8c, 0x9d, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvshuf4i.d $xr24, $xr4, 0x63" diff --git a/tests/MC/LoongArch/signcov.s.yaml b/tests/MC/LoongArch/signcov.s.yaml new file mode 100644 index 0000000000..61568091ef --- /dev/null +++ b/tests/MC/LoongArch/signcov.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x37, 0x2e, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsigncov.b $xr1, $xr24, $xr13" + - + input: + bytes: [ 0xe8, 0xba, 0x2e, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsigncov.h $xr8, $xr23, $xr14" + - + input: + bytes: [ 0x23, 0x2b, 0x2f, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsigncov.w $xr3, $xr25, $xr10" + - + input: + bytes: [ 0x3a, 0xfe, 0x2f, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsigncov.d $xr26, $xr17, $xr31" diff --git a/tests/MC/LoongArch/sle.s.yaml b/tests/MC/LoongArch/sle.s.yaml new file mode 100644 index 0000000000..3de94835bf --- /dev/null +++ b/tests/MC/LoongArch/sle.s.yaml @@ -0,0 +1,145 @@ +test_cases: + - + input: + bytes: [ 0xd8, 0x77, 0x02, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsle.b $xr24, $xr30, $xr29" + - + input: + bytes: [ 0xb7, 0xd1, 0x02, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsle.h $xr23, $xr13, $xr20" + - + input: + bytes: [ 0xea, 0x63, 0x03, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsle.w $xr10, $xr31, $xr24" + - + input: + bytes: [ 0x4d, 0xa3, 0x03, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsle.d $xr13, $xr26, $xr8" + - + input: + bytes: [ 0x6e, 0x59, 0x82, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslei.b $xr14, $xr11, -0xa" + - + input: + bytes: [ 0xc2, 0xbe, 0x82, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslei.h $xr2, $xr22, 0xf" + - + input: + bytes: [ 0xc3, 0x31, 0x83, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslei.w $xr3, $xr14, 0xc" + - + input: + bytes: [ 0xd3, 0xab, 0x83, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslei.d $xr19, $xr30, 0xa" + - + input: + bytes: [ 0x69, 0x0b, 0x04, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsle.bu $xr9, $xr27, $xr2" + - + input: + bytes: [ 0x3d, 0xdb, 0x04, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsle.hu $xr29, $xr25, $xr22" + - + input: + bytes: [ 0x30, 0x3b, 0x05, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsle.wu $xr16, $xr25, $xr14" + - + input: + bytes: [ 0xc5, 0xc8, 0x05, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsle.du $xr5, $xr6, $xr18" + - + input: + bytes: [ 0x51, 0x2b, 0x84, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslei.bu $xr17, $xr26, 0xa" + - + input: + bytes: [ 0x74, 0xc9, 0x84, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslei.hu $xr20, $xr11, 0x12" + - + input: + bytes: [ 0xa1, 0x2b, 0x85, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslei.wu $xr1, $xr29, 0xa" + - + input: + bytes: [ 0xf9, 0xe3, 0x85, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslei.du $xr25, $xr31, 0x18" diff --git a/tests/MC/LoongArch/sll.s.yaml b/tests/MC/LoongArch/sll.s.yaml new file mode 100644 index 0000000000..da6231665f --- /dev/null +++ b/tests/MC/LoongArch/sll.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0xa8, 0x27, 0xe8, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsll.b $xr8, $xr29, $xr9" + - + input: + bytes: [ 0x95, 0xf7, 0xe8, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsll.h $xr21, $xr28, $xr29" + - + input: + bytes: [ 0xd1, 0x2b, 0xe9, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsll.w $xr17, $xr30, $xr10" + - + input: + bytes: [ 0xd3, 0xe8, 0xe9, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsll.d $xr19, $xr6, $xr26" + - + input: + bytes: [ 0x59, 0x27, 0x2c, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslli.b $xr25, $xr26, 1" + - + input: + bytes: [ 0x91, 0x7b, 0x2c, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslli.h $xr17, $xr28, 0xe" + - + input: + bytes: [ 0xfa, 0xf7, 0x2c, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslli.w $xr26, $xr31, 0x1d" + - + input: + bytes: [ 0x8a, 0xbb, 0x2d, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslli.d $xr10, $xr28, 0x2e" diff --git a/tests/MC/LoongArch/sllwil.s.yaml b/tests/MC/LoongArch/sllwil.s.yaml new file mode 100644 index 0000000000..168587baca --- /dev/null +++ b/tests/MC/LoongArch/sllwil.s.yaml @@ -0,0 +1,55 @@ +test_cases: + - + input: + bytes: [ 0xad, 0x3a, 0x08, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsllwil.h.b $xr13, $xr21, 6" + - + input: + bytes: [ 0xb4, 0x43, 0x08, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsllwil.w.h $xr20, $xr29, 0" + - + input: + bytes: [ 0x83, 0xe2, 0x08, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsllwil.d.w $xr3, $xr20, 0x18" + - + input: + bytes: [ 0xef, 0x39, 0x0c, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsllwil.hu.bu $xr15, $xr15, 6" + - + input: + bytes: [ 0xb6, 0x43, 0x0c, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsllwil.wu.hu $xr22, $xr29, 0" + - + input: + bytes: [ 0xa3, 0xfc, 0x0c, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsllwil.du.wu $xr3, $xr5, 0x1f" diff --git a/tests/MC/LoongArch/slt.s.yaml b/tests/MC/LoongArch/slt.s.yaml new file mode 100644 index 0000000000..4f173ee3c1 --- /dev/null +++ b/tests/MC/LoongArch/slt.s.yaml @@ -0,0 +1,145 @@ +test_cases: + - + input: + bytes: [ 0xfe, 0x37, 0x06, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslt.b $xr30, $xr31, $xr13" + - + input: + bytes: [ 0xf3, 0x82, 0x06, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslt.h $xr19, $xr23, $xr0" + - + input: + bytes: [ 0x57, 0x0f, 0x07, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslt.w $xr23, $xr26, $xr3" + - + input: + bytes: [ 0x43, 0xfd, 0x07, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslt.d $xr3, $xr10, $xr31" + - + input: + bytes: [ 0x7f, 0x1b, 0x86, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslti.b $xr31, $xr27, 6" + - + input: + bytes: [ 0x65, 0x9a, 0x86, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslti.h $xr5, $xr19, 6" + - + input: + bytes: [ 0x14, 0x2d, 0x87, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslti.w $xr20, $xr8, 0xb" + - + input: + bytes: [ 0x4d, 0x8a, 0x87, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslti.d $xr13, $xr18, 2" + - + input: + bytes: [ 0xb4, 0x75, 0x08, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslt.bu $xr20, $xr13, $xr29" + - + input: + bytes: [ 0xac, 0xeb, 0x08, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslt.hu $xr12, $xr29, $xr26" + - + input: + bytes: [ 0x3a, 0x7f, 0x09, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslt.wu $xr26, $xr25, $xr31" + - + input: + bytes: [ 0x9e, 0x8e, 0x09, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslt.du $xr30, $xr20, $xr3" + - + input: + bytes: [ 0x81, 0x08, 0x88, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslti.bu $xr1, $xr4, 2" + - + input: + bytes: [ 0xa0, 0xd0, 0x88, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslti.hu $xr0, $xr5, 0x14" + - + input: + bytes: [ 0x20, 0x63, 0x89, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslti.wu $xr0, $xr25, 0x18" + - + input: + bytes: [ 0xaa, 0xf4, 0x89, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvslti.du $xr10, $xr5, 0x1d" diff --git a/tests/MC/LoongArch/sra.s.yaml b/tests/MC/LoongArch/sra.s.yaml new file mode 100644 index 0000000000..3ba38d4beb --- /dev/null +++ b/tests/MC/LoongArch/sra.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x4b, 0x00, 0xec, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsra.b $xr11, $xr2, $xr0" + - + input: + bytes: [ 0x71, 0x9b, 0xec, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsra.h $xr17, $xr27, $xr6" + - + input: + bytes: [ 0x8d, 0x31, 0xed, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsra.w $xr13, $xr12, $xr12" + - + input: + bytes: [ 0xe6, 0x85, 0xed, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsra.d $xr6, $xr15, $xr1" + - + input: + bytes: [ 0x50, 0x2c, 0x34, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrai.b $xr16, $xr2, 3" + - + input: + bytes: [ 0x6e, 0x70, 0x34, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrai.h $xr14, $xr3, 0xc" + - + input: + bytes: [ 0x51, 0xd6, 0x34, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrai.w $xr17, $xr18, 0x15" + - + input: + bytes: [ 0x8a, 0x12, 0x35, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrai.d $xr10, $xr20, 4" diff --git a/tests/MC/LoongArch/sran.s.yaml b/tests/MC/LoongArch/sran.s.yaml new file mode 100644 index 0000000000..068d765337 --- /dev/null +++ b/tests/MC/LoongArch/sran.s.yaml @@ -0,0 +1,28 @@ +test_cases: + - + input: + bytes: [ 0xbe, 0x8d, 0xf6, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsran.b.h $xr30, $xr13, $xr3" + - + input: + bytes: [ 0x52, 0x13, 0xf7, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsran.h.w $xr18, $xr26, $xr4" + - + input: + bytes: [ 0x7b, 0xd6, 0xf7, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsran.w.d $xr27, $xr19, $xr21" diff --git a/tests/MC/LoongArch/srani.s.yaml b/tests/MC/LoongArch/srani.s.yaml new file mode 100644 index 0000000000..ff13fafa84 --- /dev/null +++ b/tests/MC/LoongArch/srani.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0xee, 0x7e, 0x58, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrani.b.h $xr14, $xr23, 0xf" + - + input: + bytes: [ 0x02, 0x95, 0x58, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrani.h.w $xr2, $xr8, 5" + - + input: + bytes: [ 0x65, 0x39, 0x59, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrani.w.d $xr5, $xr11, 0xe" + - + input: + bytes: [ 0xf1, 0xc4, 0x5b, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrani.d.q $xr17, $xr7, 0x71" diff --git a/tests/MC/LoongArch/srar.s.yaml b/tests/MC/LoongArch/srar.s.yaml new file mode 100644 index 0000000000..a3d0b2d5d8 --- /dev/null +++ b/tests/MC/LoongArch/srar.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x49, 0x2e, 0xf2, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrar.b $xr9, $xr18, $xr11" + - + input: + bytes: [ 0x4f, 0x87, 0xf2, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrar.h $xr15, $xr26, $xr1" + - + input: + bytes: [ 0x71, 0x3a, 0xf3, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrar.w $xr17, $xr19, $xr14" + - + input: + bytes: [ 0xf3, 0x99, 0xf3, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrar.d $xr19, $xr15, $xr6" + - + input: + bytes: [ 0x8a, 0x2f, 0xa8, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrari.b $xr10, $xr28, 3" + - + input: + bytes: [ 0x3c, 0x78, 0xa8, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrari.h $xr28, $xr1, 0xe" + - + input: + bytes: [ 0xed, 0xb0, 0xa8, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrari.w $xr13, $xr7, 0xc" + - + input: + bytes: [ 0x3d, 0x21, 0xa9, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrari.d $xr29, $xr9, 8" diff --git a/tests/MC/LoongArch/srarn.s.yaml b/tests/MC/LoongArch/srarn.s.yaml new file mode 100644 index 0000000000..222843dc15 --- /dev/null +++ b/tests/MC/LoongArch/srarn.s.yaml @@ -0,0 +1,28 @@ +test_cases: + - + input: + bytes: [ 0x92, 0xbe, 0xfa, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrarn.b.h $xr18, $xr20, $xr15" + - + input: + bytes: [ 0x2c, 0x10, 0xfb, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrarn.h.w $xr12, $xr1, $xr4" + - + input: + bytes: [ 0x49, 0xea, 0xfb, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrarn.w.d $xr9, $xr18, $xr26" diff --git a/tests/MC/LoongArch/srarni.s.yaml b/tests/MC/LoongArch/srarni.s.yaml new file mode 100644 index 0000000000..0ce5da5ab5 --- /dev/null +++ b/tests/MC/LoongArch/srarni.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0xf5, 0x7f, 0x5c, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrarni.b.h $xr21, $xr31, 0xf" + - + input: + bytes: [ 0xc4, 0xe6, 0x5c, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrarni.h.w $xr4, $xr22, 0x19" + - + input: + bytes: [ 0x18, 0xa5, 0x5d, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrarni.w.d $xr24, $xr8, 0x29" + - + input: + bytes: [ 0xa7, 0x1c, 0x5e, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrarni.d.q $xr7, $xr5, 7" diff --git a/tests/MC/LoongArch/srl.s.yaml b/tests/MC/LoongArch/srl.s.yaml new file mode 100644 index 0000000000..443573e045 --- /dev/null +++ b/tests/MC/LoongArch/srl.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x14, 0x77, 0xea, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrl.b $xr20, $xr24, $xr29" + - + input: + bytes: [ 0x2b, 0xfe, 0xea, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrl.h $xr11, $xr17, $xr31" + - + input: + bytes: [ 0x42, 0x21, 0xeb, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrl.w $xr2, $xr10, $xr8" + - + input: + bytes: [ 0xcd, 0xeb, 0xeb, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrl.d $xr13, $xr30, $xr26" + - + input: + bytes: [ 0x9d, 0x2c, 0x30, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrli.b $xr29, $xr4, 3" + - + input: + bytes: [ 0xdc, 0x71, 0x30, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrli.h $xr28, $xr14, 0xc" + - + input: + bytes: [ 0x4c, 0x9e, 0x30, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrli.w $xr12, $xr18, 7" + - + input: + bytes: [ 0x80, 0xb8, 0x31, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrli.d $xr0, $xr4, 0x2e" diff --git a/tests/MC/LoongArch/srln.s.yaml b/tests/MC/LoongArch/srln.s.yaml new file mode 100644 index 0000000000..56f2ba3f8e --- /dev/null +++ b/tests/MC/LoongArch/srln.s.yaml @@ -0,0 +1,28 @@ +test_cases: + - + input: + bytes: [ 0xa7, 0x95, 0xf4, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrln.b.h $xr7, $xr13, $xr5" + - + input: + bytes: [ 0x46, 0x16, 0xf5, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrln.h.w $xr6, $xr18, $xr5" + - + input: + bytes: [ 0x8c, 0xf1, 0xf5, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrln.w.d $xr12, $xr12, $xr28" diff --git a/tests/MC/LoongArch/srlni.s.yaml b/tests/MC/LoongArch/srlni.s.yaml new file mode 100644 index 0000000000..964f4585b2 --- /dev/null +++ b/tests/MC/LoongArch/srlni.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x49, 0x40, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrlni.b.h $xr5, $xr8, 2" + - + input: + bytes: [ 0x87, 0xd0, 0x40, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrlni.h.w $xr7, $xr4, 0x14" + - + input: + bytes: [ 0xfe, 0x45, 0x41, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrlni.w.d $xr30, $xr15, 0x11" + - + input: + bytes: [ 0x8f, 0x7f, 0x43, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrlni.d.q $xr15, $xr28, 0x5f" diff --git a/tests/MC/LoongArch/srlr.s.yaml b/tests/MC/LoongArch/srlr.s.yaml new file mode 100644 index 0000000000..7d36eb0df4 --- /dev/null +++ b/tests/MC/LoongArch/srlr.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x72, 0x15, 0xf0, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrlr.b $xr18, $xr11, $xr5" + - + input: + bytes: [ 0xbf, 0xd4, 0xf0, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrlr.h $xr31, $xr5, $xr21" + - + input: + bytes: [ 0xa7, 0x04, 0xf1, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrlr.w $xr7, $xr5, $xr1" + - + input: + bytes: [ 0x64, 0x9f, 0xf1, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrlr.d $xr4, $xr27, $xr7" + - + input: + bytes: [ 0xdd, 0x33, 0xa4, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrlri.b $xr29, $xr30, 4" + - + input: + bytes: [ 0xd0, 0x78, 0xa4, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrlri.h $xr16, $xr6, 0xe" + - + input: + bytes: [ 0x58, 0xf1, 0xa4, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrlri.w $xr24, $xr10, 0x1c" + - + input: + bytes: [ 0x94, 0xd2, 0xa5, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrlri.d $xr20, $xr20, 0x34" diff --git a/tests/MC/LoongArch/srlrn.s.yaml b/tests/MC/LoongArch/srlrn.s.yaml new file mode 100644 index 0000000000..9e0b9871da --- /dev/null +++ b/tests/MC/LoongArch/srlrn.s.yaml @@ -0,0 +1,28 @@ +test_cases: + - + input: + bytes: [ 0x24, 0xeb, 0xf8, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrlrn.b.h $xr4, $xr25, $xr26" + - + input: + bytes: [ 0xb1, 0x04, 0xf9, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrlrn.h.w $xr17, $xr5, $xr1" + - + input: + bytes: [ 0x3d, 0xc4, 0xf9, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrlrn.w.d $xr29, $xr1, $xr17" diff --git a/tests/MC/LoongArch/srlrni.s.yaml b/tests/MC/LoongArch/srlrni.s.yaml new file mode 100644 index 0000000000..180a0ab667 --- /dev/null +++ b/tests/MC/LoongArch/srlrni.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x2a, 0x72, 0x44, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrlrni.b.h $xr10, $xr17, 0xc" + - + input: + bytes: [ 0xf6, 0xb6, 0x44, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrlrni.h.w $xr22, $xr23, 0xd" + - + input: + bytes: [ 0xd2, 0xea, 0x45, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrlrni.w.d $xr18, $xr22, 0x3a" + - + input: + bytes: [ 0x19, 0xa9, 0x46, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsrlrni.d.q $xr25, $xr8, 0x2a" diff --git a/tests/MC/LoongArch/ssran.s.yaml b/tests/MC/LoongArch/ssran.s.yaml new file mode 100644 index 0000000000..202bac488d --- /dev/null +++ b/tests/MC/LoongArch/ssran.s.yaml @@ -0,0 +1,55 @@ +test_cases: + - + input: + bytes: [ 0x91, 0x84, 0xfe, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssran.b.h $xr17, $xr4, $xr1" + - + input: + bytes: [ 0x9c, 0x37, 0xff, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssran.h.w $xr28, $xr28, $xr13" + - + input: + bytes: [ 0x35, 0xfc, 0xff, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssran.w.d $xr21, $xr1, $xr31" + - + input: + bytes: [ 0x83, 0xe1, 0x06, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssran.bu.h $xr3, $xr12, $xr24" + - + input: + bytes: [ 0x19, 0x07, 0x07, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssran.hu.w $xr25, $xr24, $xr1" + - + input: + bytes: [ 0xde, 0xa9, 0x07, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssran.wu.d $xr30, $xr14, $xr10" diff --git a/tests/MC/LoongArch/ssrani.s.yaml b/tests/MC/LoongArch/ssrani.s.yaml new file mode 100644 index 0000000000..324ec4f86e --- /dev/null +++ b/tests/MC/LoongArch/ssrani.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0xda, 0x7a, 0x60, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrani.b.h $xr26, $xr22, 0xe" + - + input: + bytes: [ 0xd3, 0xe9, 0x60, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrani.h.w $xr19, $xr14, 0x1a" + - + input: + bytes: [ 0x61, 0x6f, 0x61, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrani.w.d $xr1, $xr27, 0x1b" + - + input: + bytes: [ 0x49, 0xed, 0x62, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrani.d.q $xr9, $xr10, 0x3b" + - + input: + bytes: [ 0x66, 0x68, 0x64, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrani.bu.h $xr6, $xr3, 0xa" + - + input: + bytes: [ 0x34, 0x99, 0x64, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrani.hu.w $xr20, $xr9, 6" + - + input: + bytes: [ 0x78, 0x21, 0x65, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrani.wu.d $xr24, $xr11, 8" + - + input: + bytes: [ 0x50, 0x3c, 0x66, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrani.du.q $xr16, $xr2, 0xf" diff --git a/tests/MC/LoongArch/ssrarn.s.yaml b/tests/MC/LoongArch/ssrarn.s.yaml new file mode 100644 index 0000000000..d653177749 --- /dev/null +++ b/tests/MC/LoongArch/ssrarn.s.yaml @@ -0,0 +1,55 @@ +test_cases: + - + input: + bytes: [ 0xa7, 0x81, 0x02, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrarn.b.h $xr7, $xr13, $xr0" + - + input: + bytes: [ 0x56, 0x38, 0x03, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrarn.h.w $xr22, $xr2, $xr14" + - + input: + bytes: [ 0xed, 0xc0, 0x03, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrarn.w.d $xr13, $xr7, $xr16" + - + input: + bytes: [ 0x84, 0x89, 0x0a, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrarn.bu.h $xr4, $xr12, $xr2" + - + input: + bytes: [ 0x0f, 0x0f, 0x0b, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrarn.hu.w $xr15, $xr24, $xr3" + - + input: + bytes: [ 0x3e, 0xa1, 0x0b, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrarn.wu.d $xr30, $xr9, $xr8" diff --git a/tests/MC/LoongArch/ssrarni.s.yaml b/tests/MC/LoongArch/ssrarni.s.yaml new file mode 100644 index 0000000000..93e5ce4f15 --- /dev/null +++ b/tests/MC/LoongArch/ssrarni.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x80, 0x74, 0x68, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrarni.b.h $xr0, $xr4, 0xd" + - + input: + bytes: [ 0x08, 0xa4, 0x68, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrarni.h.w $xr8, $xr0, 0x9" + - + input: + bytes: [ 0xa5, 0xa8, 0x69, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrarni.w.d $xr5, $xr5, 0x2a" + - + input: + bytes: [ 0xe8, 0x4f, 0x6b, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrarni.d.q $xr8, $xr31, 0x53" + - + input: + bytes: [ 0x75, 0x42, 0x6c, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrarni.bu.h $xr21, $xr19, 0" + - + input: + bytes: [ 0xb6, 0x85, 0x6c, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrarni.hu.w $xr22, $xr13, 1" + - + input: + bytes: [ 0xb5, 0x68, 0x6d, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrarni.wu.d $xr21, $xr5, 0x1a" + - + input: + bytes: [ 0xcf, 0x79, 0x6f, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrarni.du.q $xr15, $xr14, 0x5e" diff --git a/tests/MC/LoongArch/ssrln.s.yaml b/tests/MC/LoongArch/ssrln.s.yaml new file mode 100644 index 0000000000..9f89f155d8 --- /dev/null +++ b/tests/MC/LoongArch/ssrln.s.yaml @@ -0,0 +1,55 @@ +test_cases: + - + input: + bytes: [ 0x98, 0x90, 0xfc, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrln.b.h $xr24, $xr4, $xr4" + - + input: + bytes: [ 0xe5, 0x01, 0xfd, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrln.h.w $xr5, $xr15, $xr0" + - + input: + bytes: [ 0x20, 0xfb, 0xfd, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrln.w.d $xr0, $xr25, $xr30" + - + input: + bytes: [ 0x3a, 0xe9, 0x04, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrln.bu.h $xr26, $xr9, $xr26" + - + input: + bytes: [ 0x87, 0x06, 0x05, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrln.hu.w $xr7, $xr20, $xr1" + - + input: + bytes: [ 0xaf, 0xd1, 0x05, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrln.wu.d $xr15, $xr13, $xr20" diff --git a/tests/MC/LoongArch/ssrlni.s.yaml b/tests/MC/LoongArch/ssrlni.s.yaml new file mode 100644 index 0000000000..9cd00bfae1 --- /dev/null +++ b/tests/MC/LoongArch/ssrlni.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x53, 0x66, 0x48, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlni.b.h $xr19, $xr18, 0x9" + - + input: + bytes: [ 0xbd, 0x8f, 0x48, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlni.h.w $xr29, $xr29, 3" + - + input: + bytes: [ 0xe9, 0xad, 0x49, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlni.w.d $xr9, $xr15, 0x2b" + - + input: + bytes: [ 0x68, 0xe5, 0x4b, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlni.d.q $xr8, $xr11, 0x79" + - + input: + bytes: [ 0x59, 0x55, 0x4c, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlni.bu.h $xr25, $xr10, 5" + - + input: + bytes: [ 0x49, 0xea, 0x4c, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlni.hu.w $xr9, $xr18, 0x1a" + - + input: + bytes: [ 0xd4, 0x36, 0x4d, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlni.wu.d $xr20, $xr22, 0xd" + - + input: + bytes: [ 0x88, 0xac, 0x4e, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlni.du.q $xr8, $xr4, 0x2b" diff --git a/tests/MC/LoongArch/ssrlrn.s.yaml b/tests/MC/LoongArch/ssrlrn.s.yaml new file mode 100644 index 0000000000..d399958980 --- /dev/null +++ b/tests/MC/LoongArch/ssrlrn.s.yaml @@ -0,0 +1,55 @@ +test_cases: + - + input: + bytes: [ 0x88, 0xca, 0x00, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlrn.b.h $xr8, $xr20, $xr18" + - + input: + bytes: [ 0xa2, 0x4d, 0x01, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlrn.h.w $xr2, $xr13, $xr19" + - + input: + bytes: [ 0xf8, 0x94, 0x01, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlrn.w.d $xr24, $xr7, $xr5" + - + input: + bytes: [ 0xef, 0xca, 0x08, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlrn.bu.h $xr15, $xr23, $xr18" + - + input: + bytes: [ 0xd6, 0x41, 0x09, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlrn.hu.w $xr22, $xr14, $xr16" + - + input: + bytes: [ 0x94, 0x97, 0x09, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlrn.wu.d $xr20, $xr28, $xr5" diff --git a/tests/MC/LoongArch/ssrlrni.s.yaml b/tests/MC/LoongArch/ssrlrni.s.yaml new file mode 100644 index 0000000000..c8be555728 --- /dev/null +++ b/tests/MC/LoongArch/ssrlrni.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x5a, 0x63, 0x50, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlrni.b.h $xr26, $xr26, 8" + - + input: + bytes: [ 0x06, 0xcc, 0x50, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlrni.h.w $xr6, $xr0, 0x13" + - + input: + bytes: [ 0xfc, 0xdd, 0x51, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlrni.w.d $xr28, $xr15, 0x37" + - + input: + bytes: [ 0x08, 0x02, 0x53, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlrni.d.q $xr8, $xr16, 0x40" + - + input: + bytes: [ 0x97, 0x4f, 0x54, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlrni.bu.h $xr23, $xr28, 3" + - + input: + bytes: [ 0x59, 0xc9, 0x54, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlrni.hu.w $xr25, $xr10, 0x12" + - + input: + bytes: [ 0x90, 0x3f, 0x55, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlrni.wu.d $xr16, $xr28, 0xf" + - + input: + bytes: [ 0x32, 0xb1, 0x56, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssrlrni.du.q $xr18, $xr9, 0x2c" diff --git a/tests/MC/LoongArch/ssub.s.yaml b/tests/MC/LoongArch/ssub.s.yaml new file mode 100644 index 0000000000..d091d236f7 --- /dev/null +++ b/tests/MC/LoongArch/ssub.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x6e, 0x62, 0x48, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssub.b $xr14, $xr19, $xr24" + - + input: + bytes: [ 0x0d, 0xcd, 0x48, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssub.h $xr13, $xr8, $xr19" + - + input: + bytes: [ 0x7c, 0x73, 0x49, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssub.w $xr28, $xr27, $xr28" + - + input: + bytes: [ 0x1c, 0x8a, 0x49, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssub.d $xr28, $xr16, $xr2" + - + input: + bytes: [ 0xab, 0x45, 0x4c, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssub.bu $xr11, $xr13, $xr17" + - + input: + bytes: [ 0x50, 0xf1, 0x4c, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssub.hu $xr16, $xr10, $xr28" + - + input: + bytes: [ 0x15, 0x34, 0x4d, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssub.wu $xr21, $xr0, $xr13" + - + input: + bytes: [ 0x52, 0xef, 0x4d, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvssub.du $xr18, $xr26, $xr27" diff --git a/tests/MC/LoongArch/st.s.yaml b/tests/MC/LoongArch/st.s.yaml new file mode 100644 index 0000000000..138d14e1d8 --- /dev/null +++ b/tests/MC/LoongArch/st.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0x8e, 0xbd, 0xce, 0x2c ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvst $xr14, $t0, 0x3af" + - + input: + bytes: [ 0x27, 0x55, 0x4c, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvstx $xr7, $a5, $r21" diff --git a/tests/MC/LoongArch/stelm.s.yaml b/tests/MC/LoongArch/stelm.s.yaml new file mode 100644 index 0000000000..06984b0008 --- /dev/null +++ b/tests/MC/LoongArch/stelm.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x54, 0x5c, 0xaa, 0x33 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvstelm.b $xr20, $tp, -0x69, 0xa" + - + input: + bytes: [ 0x28, 0x40, 0x51, 0x33 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvstelm.h $xr8, $ra, 0xa0, 4" + - + input: + bytes: [ 0x53, 0x9e, 0x21, 0x33 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvstelm.w $xr19, $t6, 0x19c, 0" + - + input: + bytes: [ 0xd6, 0xe3, 0x1d, 0x33 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvstelm.d $xr22, $s7, 0x3c0, 3" diff --git a/tests/MC/LoongArch/sub.s.yaml b/tests/MC/LoongArch/sub.s.yaml new file mode 100644 index 0000000000..62989d73c4 --- /dev/null +++ b/tests/MC/LoongArch/sub.s.yaml @@ -0,0 +1,46 @@ +test_cases: + - + input: + bytes: [ 0x8b, 0x43, 0x0c, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsub.b $xr11, $xr28, $xr16" + - + input: + bytes: [ 0x6b, 0xe0, 0x0c, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsub.h $xr11, $xr3, $xr24" + - + input: + bytes: [ 0xee, 0x1a, 0x0d, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsub.w $xr14, $xr23, $xr6" + - + input: + bytes: [ 0xa5, 0x9d, 0x0d, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsub.d $xr5, $xr13, $xr7" + - + input: + bytes: [ 0x4d, 0xff, 0x2d, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsub.q $xr13, $xr26, $xr31" diff --git a/tests/MC/LoongArch/subi.s.yaml b/tests/MC/LoongArch/subi.s.yaml new file mode 100644 index 0000000000..2bc3080b27 --- /dev/null +++ b/tests/MC/LoongArch/subi.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x72, 0x07, 0x8c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubi.bu $xr18, $xr27, 1" + - + input: + bytes: [ 0xe6, 0xce, 0x8c, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubi.hu $xr6, $xr23, 0x13" + - + input: + bytes: [ 0x6d, 0x14, 0x8d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubi.wu $xr13, $xr3, 5" + - + input: + bytes: [ 0x9a, 0xbb, 0x8d, 0x76 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubi.du $xr26, $xr28, 0xe" diff --git a/tests/MC/LoongArch/subw.s.yaml b/tests/MC/LoongArch/subw.s.yaml new file mode 100644 index 0000000000..b71b741c29 --- /dev/null +++ b/tests/MC/LoongArch/subw.s.yaml @@ -0,0 +1,145 @@ +test_cases: + - + input: + bytes: [ 0x3d, 0x70, 0x20, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubwev.h.b $xr29, $xr1, $xr28" + - + input: + bytes: [ 0x98, 0xfe, 0x20, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubwev.w.h $xr24, $xr20, $xr31" + - + input: + bytes: [ 0x86, 0x2c, 0x21, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubwev.d.w $xr6, $xr4, $xr11" + - + input: + bytes: [ 0xfb, 0xb7, 0x21, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubwev.q.d $xr27, $xr31, $xr13" + - + input: + bytes: [ 0x81, 0x0a, 0x30, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubwev.h.bu $xr1, $xr20, $xr2" + - + input: + bytes: [ 0xd3, 0xb0, 0x30, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubwev.w.hu $xr19, $xr6, $xr12" + - + input: + bytes: [ 0x3f, 0x5c, 0x31, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubwev.d.wu $xr31, $xr1, $xr23" + - + input: + bytes: [ 0x9f, 0xc7, 0x31, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubwev.q.du $xr31, $xr28, $xr17" + - + input: + bytes: [ 0x23, 0x45, 0x24, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubwod.h.b $xr3, $xr9, $xr17" + - + input: + bytes: [ 0xae, 0xd4, 0x24, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubwod.w.h $xr14, $xr5, $xr21" + - + input: + bytes: [ 0xc8, 0x0d, 0x25, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubwod.d.w $xr8, $xr14, $xr3" + - + input: + bytes: [ 0xf8, 0xc9, 0x25, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubwod.q.d $xr24, $xr15, $xr18" + - + input: + bytes: [ 0x5b, 0x04, 0x34, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubwod.h.bu $xr27, $xr2, $xr1" + - + input: + bytes: [ 0xf3, 0xd8, 0x34, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubwod.w.hu $xr19, $xr7, $xr22" + - + input: + bytes: [ 0x01, 0x6b, 0x35, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubwod.d.wu $xr1, $xr24, $xr26" + - + input: + bytes: [ 0x5d, 0x9f, 0x35, 0x74 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvsubwod.q.du $xr29, $xr26, $xr7" diff --git a/tests/MC/LoongArch/valid.s.yaml b/tests/MC/LoongArch/valid.s.yaml new file mode 100644 index 0000000000..ad7d0f8b87 --- /dev/null +++ b/tests/MC/LoongArch/valid.s.yaml @@ -0,0 +1,199 @@ +test_cases: + - + input: + bytes: [ 0x1a, 0x78, 0x00, 0x04 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "csrrd $s3, 0x1e" + - + input: + bytes: [ 0x38, 0x08, 0x03, 0x04 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "csrwr $s1, 0xc2" + - + input: + bytes: [ 0x66, 0x5b, 0x03, 0x04 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "csrxchg $a2, $s4, 0xd6" + - + input: + bytes: [ 0x1a, 0x03, 0x48, 0x06 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "iocsrrd.b $s3, $s1" + - + input: + bytes: [ 0x65, 0x07, 0x48, 0x06 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "iocsrrd.h $a1, $s4" + - + input: + bytes: [ 0x8a, 0x0a, 0x48, 0x06 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "iocsrrd.w $a6, $t8" + - + input: + bytes: [ 0xe4, 0x12, 0x48, 0x06 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "iocsrwr.b $a0, $s0" + - + input: + bytes: [ 0x0b, 0x14, 0x48, 0x06 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "iocsrwr.h $a7, $zero" + - + input: + bytes: [ 0x54, 0x1b, 0x48, 0x06 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "iocsrwr.w $t8, $s3" + - + input: + bytes: [ 0x40, 0x6d, 0x00, 0x06 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "cacop 0, $a6, 0x1b" + - + input: + bytes: [ 0x00, 0x20, 0x48, 0x06 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "tlbclr" + - + input: + bytes: [ 0x00, 0x24, 0x48, 0x06 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "tlbflush" + - + input: + bytes: [ 0x00, 0x28, 0x48, 0x06 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "tlbsrch" + - + input: + bytes: [ 0x00, 0x2c, 0x48, 0x06 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "tlbrd" + - + input: + bytes: [ 0x00, 0x30, 0x48, 0x06 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "tlbwr" + - + input: + bytes: [ 0x00, 0x34, 0x48, 0x06 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "tlbfill" + - + input: + bytes: [ 0xb0, 0xe7, 0x49, 0x06 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "invtlb 0x10, $s6, $s2" + - + input: + bytes: [ 0xcc, 0x73, 0x41, 0x06 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "lddir $t0, $s7, 0x5c" + - + input: + bytes: [ 0x40, 0x22, 0x47, 0x06 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ldpte $t6, 0xc8" + - + input: + bytes: [ 0x00, 0x38, 0x48, 0x06 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "ertn" + - + input: + bytes: [ 0xc9, 0x80, 0x2a, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "dbcl 0xc9" + - + input: + bytes: [ 0xcc, 0x80, 0x48, 0x06 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "idle 0xcc" diff --git a/tests/MC/LoongArch/x86-alu.s.yaml b/tests/MC/LoongArch/x86-alu.s.yaml new file mode 100644 index 0000000000..d7ee2a838f --- /dev/null +++ b/tests/MC/LoongArch/x86-alu.s.yaml @@ -0,0 +1,433 @@ +test_cases: + - + input: + bytes: [ 0x8c, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86adc.b $a0, $a1" + - + input: + bytes: [ 0x8d, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86adc.h $a0, $a1" + - + input: + bytes: [ 0x8e, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86adc.w $a0, $a1" + - + input: + bytes: [ 0x8f, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86adc.d $a0, $a1" + - + input: + bytes: [ 0x84, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86add.b $a0, $a1" + - + input: + bytes: [ 0x85, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86add.h $a0, $a1" + - + input: + bytes: [ 0x86, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86add.w $a0, $a1" + - + input: + bytes: [ 0x87, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86add.d $a0, $a1" + - + input: + bytes: [ 0x80, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86add.wu $a0, $a1" + - + input: + bytes: [ 0x81, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86add.du $a0, $a1" + - + input: + bytes: [ 0x80, 0x80, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86inc.b $a0" + - + input: + bytes: [ 0x81, 0x80, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86inc.h $a0" + - + input: + bytes: [ 0x82, 0x80, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86inc.w $a0" + - + input: + bytes: [ 0x83, 0x80, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86inc.d $a0" + - + input: + bytes: [ 0x90, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86sbc.b $a0, $a1" + - + input: + bytes: [ 0x91, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86sbc.h $a0, $a1" + - + input: + bytes: [ 0x92, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86sbc.w $a0, $a1" + - + input: + bytes: [ 0x93, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86sbc.d $a0, $a1" + - + input: + bytes: [ 0x88, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86sub.b $a0, $a1" + - + input: + bytes: [ 0x89, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86sub.h $a0, $a1" + - + input: + bytes: [ 0x8a, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86sub.w $a0, $a1" + - + input: + bytes: [ 0x8b, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86sub.d $a0, $a1" + - + input: + bytes: [ 0x82, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86sub.wu $a0, $a1" + - + input: + bytes: [ 0x83, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86sub.du $a0, $a1" + - + input: + bytes: [ 0x84, 0x80, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86dec.b $a0" + - + input: + bytes: [ 0x85, 0x80, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86dec.h $a0" + - + input: + bytes: [ 0x86, 0x80, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86dec.w $a0" + - + input: + bytes: [ 0x87, 0x80, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86dec.d $a0" + - + input: + bytes: [ 0x90, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86and.b $a0, $a1" + - + input: + bytes: [ 0x91, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86and.h $a0, $a1" + - + input: + bytes: [ 0x92, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86and.w $a0, $a1" + - + input: + bytes: [ 0x93, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86and.d $a0, $a1" + - + input: + bytes: [ 0x94, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86or.b $a0, $a1" + - + input: + bytes: [ 0x95, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86or.h $a0, $a1" + - + input: + bytes: [ 0x96, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86or.w $a0, $a1" + - + input: + bytes: [ 0x97, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86or.d $a0, $a1" + - + input: + bytes: [ 0x98, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86xor.b $a0, $a1" + - + input: + bytes: [ 0x99, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86xor.h $a0, $a1" + - + input: + bytes: [ 0x9a, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86xor.w $a0, $a1" + - + input: + bytes: [ 0x9b, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86xor.d $a0, $a1" + - + input: + bytes: [ 0x80, 0x94, 0x3e, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86mul.b $a0, $a1" + - + input: + bytes: [ 0x81, 0x94, 0x3e, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86mul.h $a0, $a1" + - + input: + bytes: [ 0x82, 0x94, 0x3e, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86mul.w $a0, $a1" + - + input: + bytes: [ 0x83, 0x94, 0x3e, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86mul.d $a0, $a1" + - + input: + bytes: [ 0x84, 0x94, 0x3e, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86mul.bu $a0, $a1" + - + input: + bytes: [ 0x85, 0x94, 0x3e, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86mul.hu $a0, $a1" + - + input: + bytes: [ 0x86, 0x94, 0x3e, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86mul.wu $a0, $a1" + - + input: + bytes: [ 0x87, 0x94, 0x3e, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86mul.du $a0, $a1" diff --git a/tests/MC/LoongArch/x86-jump.s.yaml b/tests/MC/LoongArch/x86-jump.s.yaml new file mode 100644 index 0000000000..8f81927382 --- /dev/null +++ b/tests/MC/LoongArch/x86-jump.s.yaml @@ -0,0 +1,28 @@ +test_cases: + - + input: + bytes: [ 0x04, 0x84, 0x36, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "setx86j $a0, 1" + - + input: + bytes: [ 0xa4, 0x78, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "setx86loope $a0, $a1" + - + input: + bytes: [ 0xa4, 0x7c, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "setx86loopne $a0, $a1" diff --git a/tests/MC/LoongArch/x86-misc.s.yaml b/tests/MC/LoongArch/x86-misc.s.yaml new file mode 100644 index 0000000000..29d8787109 --- /dev/null +++ b/tests/MC/LoongArch/x86-misc.s.yaml @@ -0,0 +1,82 @@ +test_cases: + - + input: + bytes: [ 0x04, 0x04, 0x5c, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86mfflag $a0, 1" + - + input: + bytes: [ 0x24, 0x04, 0x5c, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86mtflag $a0, 1" + - + input: + bytes: [ 0x04, 0x74, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86mftop $a0" + - + input: + bytes: [ 0x20, 0x70, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86mttop 1" + - + input: + bytes: [ 0x09, 0x80, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86inctop" + - + input: + bytes: [ 0x29, 0x80, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86dectop" + - + input: + bytes: [ 0x08, 0x80, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86settm" + - + input: + bytes: [ 0x28, 0x80, 0x00, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86clrtm" + - + input: + bytes: [ 0x24, 0x04, 0x58, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86settag $a0, 1, 1" diff --git a/tests/MC/LoongArch/x86-shift.s.yaml b/tests/MC/LoongArch/x86-shift.s.yaml new file mode 100644 index 0000000000..e972d6b227 --- /dev/null +++ b/tests/MC/LoongArch/x86-shift.s.yaml @@ -0,0 +1,505 @@ +test_cases: + - + input: + bytes: [ 0x8c, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rcl.b $a0, $a1" + - + input: + bytes: [ 0x8d, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rcl.h $a0, $a1" + - + input: + bytes: [ 0x8e, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rcl.w $a0, $a1" + - + input: + bytes: [ 0x8f, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rcl.d $a0, $a1" + - + input: + bytes: [ 0x98, 0x24, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rcli.b $a0, 1" + - + input: + bytes: [ 0x99, 0x44, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rcli.h $a0, 1" + - + input: + bytes: [ 0x9a, 0x84, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rcli.w $a0, 1" + - + input: + bytes: [ 0x9b, 0x04, 0x55, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rcli.d $a0, 1" + - + input: + bytes: [ 0x88, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rcr.b $a0, $a1" + - + input: + bytes: [ 0x89, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rcr.h $a0, $a1" + - + input: + bytes: [ 0x8a, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rcr.w $a0, $a1" + - + input: + bytes: [ 0x8b, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rcr.d $a0, $a1" + - + input: + bytes: [ 0x90, 0x24, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rcri.b $a0, 1" + - + input: + bytes: [ 0x91, 0x44, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rcri.h $a0, 1" + - + input: + bytes: [ 0x92, 0x84, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rcri.w $a0, 1" + - + input: + bytes: [ 0x93, 0x04, 0x55, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rcri.d $a0, 1" + - + input: + bytes: [ 0x84, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rotl.b $a0, $a1" + - + input: + bytes: [ 0x85, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rotl.h $a0, $a1" + - + input: + bytes: [ 0x86, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rotl.w $a0, $a1" + - + input: + bytes: [ 0x87, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rotl.d $a0, $a1" + - + input: + bytes: [ 0x94, 0x24, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rotli.b $a0, 1" + - + input: + bytes: [ 0x95, 0x44, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rotli.h $a0, 1" + - + input: + bytes: [ 0x96, 0x84, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rotli.w $a0, 1" + - + input: + bytes: [ 0x97, 0x04, 0x55, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rotli.d $a0, 1" + - + input: + bytes: [ 0x80, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rotr.b $a0, $a1" + - + input: + bytes: [ 0x81, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rotr.h $a0, $a1" + - + input: + bytes: [ 0x82, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rotr.d $a0, $a1" + - + input: + bytes: [ 0x83, 0x94, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rotr.w $a0, $a1" + - + input: + bytes: [ 0x8c, 0x24, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rotri.b $a0, 1" + - + input: + bytes: [ 0x8d, 0x44, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rotri.h $a0, 1" + - + input: + bytes: [ 0x8e, 0x84, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rotri.w $a0, 1" + - + input: + bytes: [ 0x8f, 0x04, 0x55, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86rotri.d $a0, 1" + - + input: + bytes: [ 0x94, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86sll.b $a0, $a1" + - + input: + bytes: [ 0x95, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86sll.h $a0, $a1" + - + input: + bytes: [ 0x96, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86sll.w $a0, $a1" + - + input: + bytes: [ 0x97, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86sll.d $a0, $a1" + - + input: + bytes: [ 0x80, 0x24, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86slli.b $a0, 1" + - + input: + bytes: [ 0x81, 0x44, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86slli.h $a0, 1" + - + input: + bytes: [ 0x82, 0x84, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86slli.w $a0, 1" + - + input: + bytes: [ 0x83, 0x04, 0x55, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86slli.d $a0, 1" + - + input: + bytes: [ 0x98, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86srl.b $a0, $a1" + - + input: + bytes: [ 0x99, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86srl.h $a0, $a1" + - + input: + bytes: [ 0x9a, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86srl.w $a0, $a1" + - + input: + bytes: [ 0x9b, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86srl.d $a0, $a1" + - + input: + bytes: [ 0x84, 0x24, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86srli.b $a0, 1" + - + input: + bytes: [ 0x85, 0x44, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86srli.h $a0, 1" + - + input: + bytes: [ 0x86, 0x84, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86srli.w $a0, 1" + - + input: + bytes: [ 0x87, 0x04, 0x55, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86srli.d $a0, 1" + - + input: + bytes: [ 0x9c, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86sra.b $a0, $a1" + - + input: + bytes: [ 0x9d, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86sra.h $a0, $a1" + - + input: + bytes: [ 0x9e, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86sra.w $a0, $a1" + - + input: + bytes: [ 0x9f, 0x14, 0x3f, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86sra.d $a0, $a1" + - + input: + bytes: [ 0x88, 0x24, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86srai.b $a0, 1" + - + input: + bytes: [ 0x89, 0x44, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86srai.h $a0, 1" + - + input: + bytes: [ 0x8a, 0x84, 0x54, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86srai.w $a0, 1" + - + input: + bytes: [ 0x8b, 0x04, 0x55, 0x00 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "x86srai.d $a0, 1" diff --git a/tests/MC/LoongArch/xor.s.yaml b/tests/MC/LoongArch/xor.s.yaml new file mode 100644 index 0000000000..e56ca3bc7c --- /dev/null +++ b/tests/MC/LoongArch/xor.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x4e, 0x2b, 0x27, 0x75 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvxor.v $xr14, $xr26, $xr10" diff --git a/tests/MC/LoongArch/xori.s.yaml b/tests/MC/LoongArch/xori.s.yaml new file mode 100644 index 0000000000..e5668eec07 --- /dev/null +++ b/tests/MC/LoongArch/xori.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x1a, 0x55, 0xda, 0x77 ] + arch: "CS_ARCH_LOONGARCH" + options: [ "CS_MODE_LOONGARCH64" ] + expected: + insns: + - + asm_text: "xvxori.b $xr26, $xr8, 0x95" diff --git a/tests/MC/Mips/hilo-addressing.s.yaml b/tests/MC/Mips/hilo-addressing.s.yaml new file mode 100644 index 0000000000..db654d99e1 --- /dev/null +++ b/tests/MC/Mips/hilo-addressing.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x03, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "jr $ra" diff --git a/tests/MC/Mips/micromips-alu-instructions-EB.s.yaml b/tests/MC/Mips/micromips-alu-instructions-EB.s.yaml new file mode 100644 index 0000000000..352ff3e9aa --- /dev/null +++ b/tests/MC/Mips/micromips-alu-instructions-EB.s.yaml @@ -0,0 +1,289 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe6, 0x49, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "add $t1, $a2, $a3" + - + input: + bytes: [ 0x11, 0x26, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addi $t1, $a2, 17767" + - + input: + bytes: [ 0x31, 0x26, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addiu $t1, $a2, -15001" + - + input: + bytes: [ 0x11, 0x26, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addi $t1, $a2, 17767" + - + input: + bytes: [ 0x31, 0x26, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addiu $t1, $a2, -15001" + - + input: + bytes: [ 0x00, 0xe6, 0x49, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addu $t1, $a2, $a3" + - + input: + bytes: [ 0x00, 0xe6, 0x49, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sub $t1, $a2, $a3" + - + input: + bytes: [ 0x00, 0xa3, 0x21, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "subu $a0, $v1, $a1" + - + input: + bytes: [ 0x00, 0xe0, 0x31, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sub $a2, $zero, $a3" + - + input: + bytes: [ 0x00, 0xe0, 0x31, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "subu $a2, $zero, $a3" + - + input: + bytes: [ 0x00, 0x08, 0x39, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addu $a3, $t0, $zero" + - + input: + bytes: [ 0x00, 0xa3, 0x1b, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "slt $v1, $v1, $a1" + - + input: + bytes: [ 0x90, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "slti $v1, $v1, 103" + - + input: + bytes: [ 0x90, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "slti $v1, $v1, 103" + - + input: + bytes: [ 0xb0, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sltiu $v1, $v1, 103" + - + input: + bytes: [ 0x00, 0xa3, 0x1b, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sltu $v1, $v1, $a1" + - + input: + bytes: [ 0x41, 0xa9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lui $t1, 17767" + - + input: + bytes: [ 0x00, 0xe6, 0x4a, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "and $t1, $a2, $a3" + - + input: + bytes: [ 0xd1, 0x26, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "andi $t1, $a2, 17767" + - + input: + bytes: [ 0xd1, 0x26, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "andi $t1, $a2, 17767" + - + input: + bytes: [ 0x00, 0xa4, 0x1a, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "or $v1, $a0, $a1" + - + input: + bytes: [ 0x51, 0x26, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "ori $t1, $a2, 17767" + - + input: + bytes: [ 0x00, 0xa3, 0x1b, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "xor $v1, $v1, $a1" + - + input: + bytes: [ 0x71, 0x26, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "xori $t1, $a2, 17767" + - + input: + bytes: [ 0x71, 0x26, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "xori $t1, $a2, 17767" + - + input: + bytes: [ 0x00, 0xe6, 0x4a, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "nor $t1, $a2, $a3" + - + input: + bytes: [ 0x00, 0x08, 0x3a, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "not $a3, $t0" + - + input: + bytes: [ 0x00, 0xe6, 0x4a, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mul $t1, $a2, $a3" + - + input: + bytes: [ 0x00, 0xe9, 0x8b, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mult $t1, $a3" + - + input: + bytes: [ 0x00, 0xe9, 0x9b, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "multu $t1, $a3" + - + input: + bytes: [ 0x00, 0xe9, 0xab, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "div $zero, $t1, $a3" + - + input: + bytes: [ 0x00, 0xe9, 0xbb, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "divu $zero, $t1, $a3" diff --git a/tests/MC/Mips/micromips-alu-instructions.s.yaml b/tests/MC/Mips/micromips-alu-instructions.s.yaml new file mode 100644 index 0000000000..116479a58c --- /dev/null +++ b/tests/MC/Mips/micromips-alu-instructions.s.yaml @@ -0,0 +1,289 @@ +test_cases: + - + input: + bytes: [ 0xe6, 0x00, 0x10, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "add $t1, $a2, $a3" + - + input: + bytes: [ 0x26, 0x11, 0x67, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addi $t1, $a2, 17767" + - + input: + bytes: [ 0x26, 0x31, 0x67, 0xc5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addiu $t1, $a2, -15001" + - + input: + bytes: [ 0x26, 0x11, 0x67, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addi $t1, $a2, 17767" + - + input: + bytes: [ 0x26, 0x31, 0x67, 0xc5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addiu $t1, $a2, -15001" + - + input: + bytes: [ 0xe6, 0x00, 0x50, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addu $t1, $a2, $a3" + - + input: + bytes: [ 0xe6, 0x00, 0x90, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sub $t1, $a2, $a3" + - + input: + bytes: [ 0xa3, 0x00, 0xd0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "subu $a0, $v1, $a1" + - + input: + bytes: [ 0xe0, 0x00, 0x90, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sub $a2, $zero, $a3" + - + input: + bytes: [ 0xe0, 0x00, 0xd0, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "subu $a2, $zero, $a3" + - + input: + bytes: [ 0x08, 0x00, 0x50, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addu $a3, $t0, $zero" + - + input: + bytes: [ 0xa3, 0x00, 0x50, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "slt $v1, $v1, $a1" + - + input: + bytes: [ 0x63, 0x90, 0x67, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "slti $v1, $v1, 103" + - + input: + bytes: [ 0x63, 0x90, 0x67, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "slti $v1, $v1, 103" + - + input: + bytes: [ 0x63, 0xb0, 0x67, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sltiu $v1, $v1, 103" + - + input: + bytes: [ 0xa3, 0x00, 0x90, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sltu $v1, $v1, $a1" + - + input: + bytes: [ 0xa9, 0x41, 0x67, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lui $t1, 17767" + - + input: + bytes: [ 0xe6, 0x00, 0x50, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "and $t1, $a2, $a3" + - + input: + bytes: [ 0x26, 0xd1, 0x67, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "andi $t1, $a2, 17767" + - + input: + bytes: [ 0x26, 0xd1, 0x67, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "andi $t1, $a2, 17767" + - + input: + bytes: [ 0xa4, 0x00, 0x90, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "or $v1, $a0, $a1" + - + input: + bytes: [ 0x26, 0x51, 0x67, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "ori $t1, $a2, 17767" + - + input: + bytes: [ 0xa3, 0x00, 0x10, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "xor $v1, $v1, $a1" + - + input: + bytes: [ 0x26, 0x71, 0x67, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "xori $t1, $a2, 17767" + - + input: + bytes: [ 0x26, 0x71, 0x67, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "xori $t1, $a2, 17767" + - + input: + bytes: [ 0xe6, 0x00, 0xd0, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "nor $t1, $a2, $a3" + - + input: + bytes: [ 0x08, 0x00, 0xd0, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "not $a3, $t0" + - + input: + bytes: [ 0xe6, 0x00, 0x10, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mul $t1, $a2, $a3" + - + input: + bytes: [ 0xe9, 0x00, 0x3c, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mult $t1, $a3" + - + input: + bytes: [ 0xe9, 0x00, 0x3c, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "multu $t1, $a3" + - + input: + bytes: [ 0xe9, 0x00, 0x3c, 0xab ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "div $zero, $t1, $a3" + - + input: + bytes: [ 0xe9, 0x00, 0x3c, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "divu $zero, $t1, $a3" diff --git a/tests/MC/Mips/micromips-branch-instructions-EB.s.yaml b/tests/MC/Mips/micromips-branch-instructions-EB.s.yaml new file mode 100644 index 0000000000..019ad62292 --- /dev/null +++ b/tests/MC/Mips/micromips-branch-instructions-EB.s.yaml @@ -0,0 +1,82 @@ +test_cases: + - + input: + bytes: [ 0x94, 0x00, 0x02, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "b 1332" + - + input: + bytes: [ 0x94, 0xc9, 0x02, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "beq $t1, $a2, 1332" + - + input: + bytes: [ 0x40, 0x46, 0x02, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "bgez $a2, 1332" + - + input: + bytes: [ 0x40, 0x66, 0x02, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "bgezal $a2, 1332" + - + input: + bytes: [ 0x40, 0x26, 0x02, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "bltzal $a2, 1332" + - + input: + bytes: [ 0x40, 0xc6, 0x02, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "bgtz $a2, 1332" + - + input: + bytes: [ 0x40, 0x86, 0x02, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "blez $a2, 1332" + - + input: + bytes: [ 0xb4, 0xc9, 0x02, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "bne $t1, $a2, 1332" + - + input: + bytes: [ 0x40, 0x06, 0x02, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "bltz $a2, 1332" diff --git a/tests/MC/Mips/micromips-branch-instructions.s.yaml b/tests/MC/Mips/micromips-branch-instructions.s.yaml new file mode 100644 index 0000000000..7da1059436 --- /dev/null +++ b/tests/MC/Mips/micromips-branch-instructions.s.yaml @@ -0,0 +1,82 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x94, 0x9a, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "b 1332" + - + input: + bytes: [ 0xc9, 0x94, 0x9a, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "beq $t1, $a2, 1332" + - + input: + bytes: [ 0x46, 0x40, 0x9a, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "bgez $a2, 1332" + - + input: + bytes: [ 0x66, 0x40, 0x9a, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "bgezal $a2, 1332" + - + input: + bytes: [ 0x26, 0x40, 0x9a, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "bltzal $a2, 1332" + - + input: + bytes: [ 0xc6, 0x40, 0x9a, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "bgtz $a2, 1332" + - + input: + bytes: [ 0x86, 0x40, 0x9a, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "blez $a2, 1332" + - + input: + bytes: [ 0xc9, 0xb4, 0x9a, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "bne $t1, $a2, 1332" + - + input: + bytes: [ 0x06, 0x40, 0x9a, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "bltz $a2, 1332" diff --git a/tests/MC/Mips/micromips-expansions.s.yaml b/tests/MC/Mips/micromips-expansions.s.yaml new file mode 100644 index 0000000000..e28a7024d5 --- /dev/null +++ b/tests/MC/Mips/micromips-expansions.s.yaml @@ -0,0 +1,163 @@ +test_cases: + - + input: + bytes: [ 0xa0, 0x50, 0x7b, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "ori $a1, $zero, 123" + - + input: + bytes: [ 0xc0, 0x30, 0xd7, 0xf6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addiu $a2, $zero, -2345" + - + input: + bytes: [ 0xa7, 0x41, 0x01, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lui $a3, 1" + - + input: + bytes: [ 0xe7, 0x50, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "ori $a3, $a3, 2" + - + input: + bytes: [ 0x80, 0x30, 0x14, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addiu $a0, $zero, 20" + - + input: + bytes: [ 0xa7, 0x41, 0x01, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lui $a3, 1" + - + input: + bytes: [ 0xe7, 0x50, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "ori $a3, $a3, 2" + - + input: + bytes: [ 0x85, 0x30, 0x14, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addiu $a0, $a1, 20" + - + input: + bytes: [ 0xa7, 0x41, 0x01, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lui $a3, 1" + - + input: + bytes: [ 0xe7, 0x50, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "ori $a3, $a3, 2" + - + input: + bytes: [ 0x07, 0x01, 0x50, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addu $a3, $a3, $t0" + - + input: + bytes: [ 0x8a, 0x00, 0x50, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addu $t2, $t2, $a0" + - + input: + bytes: [ 0x21, 0x01, 0x50, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addu $at, $at, $t1" + - + input: + bytes: [ 0xaa, 0x41, 0x0a, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lui $t2, 10" + - + input: + bytes: [ 0x8a, 0x00, 0x50, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addu $t2, $t2, $a0" + - + input: + bytes: [ 0x4a, 0xfd, 0x7b, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lw $t2, 123($t2)" + - + input: + bytes: [ 0xa1, 0x41, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lui $at, 2" + - + input: + bytes: [ 0x21, 0x01, 0x50, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "addu $at, $at, $t1" diff --git a/tests/MC/Mips/micromips-jump-instructions-EB.s.yaml b/tests/MC/Mips/micromips-jump-instructions-EB.s.yaml new file mode 100644 index 0000000000..b709a41cc0 --- /dev/null +++ b/tests/MC/Mips/micromips-jump-instructions-EB.s.yaml @@ -0,0 +1,28 @@ +test_cases: + - + input: + bytes: [ 0xd4, 0x00, 0x02, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "j 1328" + - + input: + bytes: [ 0xf4, 0x00, 0x02, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "jal 1328" + - + input: + bytes: [ 0x00, 0x07, 0x0f, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "jr $a3" diff --git a/tests/MC/Mips/micromips-jump-instructions.s.yaml b/tests/MC/Mips/micromips-jump-instructions.s.yaml new file mode 100644 index 0000000000..ed3eb4cf68 --- /dev/null +++ b/tests/MC/Mips/micromips-jump-instructions.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xd4, 0x98, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "j 1328" + - + input: + bytes: [ 0x00, 0xf4, 0x98, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "jal 1328" + - + input: + bytes: [ 0x07, 0x00, 0x3c, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "jr $a3" + - + input: + bytes: [ 0x07, 0x00, 0x3c, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "jr $a3" diff --git a/tests/MC/Mips/micromips-loadstore-instructions-EB.s.yaml b/tests/MC/Mips/micromips-loadstore-instructions-EB.s.yaml new file mode 100644 index 0000000000..2040ea000b --- /dev/null +++ b/tests/MC/Mips/micromips-loadstore-instructions-EB.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x1c, 0xa4, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lb $a1, 8($a0)" + - + input: + bytes: [ 0x14, 0xc4, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lbu $a2, 8($a0)" + - + input: + bytes: [ 0x3c, 0x44, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lh $v0, 8($a0)" + - + input: + bytes: [ 0x34, 0x82, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lhu $a0, 8($v0)" + - + input: + bytes: [ 0xfc, 0xc5, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lw $a2, 4($a1)" + - + input: + bytes: [ 0x18, 0xa4, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sb $a1, 8($a0)" + - + input: + bytes: [ 0x38, 0x44, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sh $v0, 8($a0)" + - + input: + bytes: [ 0xf8, 0xa6, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sw $a1, 4($a2)" diff --git a/tests/MC/Mips/micromips-loadstore-instructions.s.yaml b/tests/MC/Mips/micromips-loadstore-instructions.s.yaml new file mode 100644 index 0000000000..f87d7c9905 --- /dev/null +++ b/tests/MC/Mips/micromips-loadstore-instructions.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0xa4, 0x1c, 0x08, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lb $a1, 8($a0)" + - + input: + bytes: [ 0xc4, 0x14, 0x08, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lbu $a2, 8($a0)" + - + input: + bytes: [ 0x44, 0x3c, 0x08, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lh $v0, 8($a0)" + - + input: + bytes: [ 0x82, 0x34, 0x08, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lhu $a0, 8($v0)" + - + input: + bytes: [ 0xc5, 0xfc, 0x04, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lw $a2, 4($a1)" + - + input: + bytes: [ 0xa4, 0x18, 0x08, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sb $a1, 8($a0)" + - + input: + bytes: [ 0x44, 0x38, 0x08, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sh $v0, 8($a0)" + - + input: + bytes: [ 0xa6, 0xf8, 0x04, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sw $a1, 4($a2)" diff --git a/tests/MC/Mips/micromips-loadstore-unaligned-EB.s.yaml b/tests/MC/Mips/micromips-loadstore-unaligned-EB.s.yaml new file mode 100644 index 0000000000..897c1d18db --- /dev/null +++ b/tests/MC/Mips/micromips-loadstore-unaligned-EB.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x60, 0x85, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lwl $a0, 16($a1)" + - + input: + bytes: [ 0x60, 0x85, 0x10, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lwr $a0, 16($a1)" + - + input: + bytes: [ 0x60, 0x85, 0x80, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "swl $a0, 16($a1)" + - + input: + bytes: [ 0x60, 0x85, 0x90, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "swr $a0, 16($a1)" diff --git a/tests/MC/Mips/micromips-loadstore-unaligned.s.yaml b/tests/MC/Mips/micromips-loadstore-unaligned.s.yaml new file mode 100644 index 0000000000..b16e00f75e --- /dev/null +++ b/tests/MC/Mips/micromips-loadstore-unaligned.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x85, 0x60, 0x10, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lwl $a0, 16($a1)" + - + input: + bytes: [ 0x85, 0x60, 0x10, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "lwr $a0, 16($a1)" + - + input: + bytes: [ 0x85, 0x60, 0x10, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "swl $a0, 16($a1)" + - + input: + bytes: [ 0x85, 0x60, 0x10, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "swr $a0, 16($a1)" diff --git a/tests/MC/Mips/micromips-movcond-instructions-EB.s.yaml b/tests/MC/Mips/micromips-movcond-instructions-EB.s.yaml new file mode 100644 index 0000000000..7559e35598 --- /dev/null +++ b/tests/MC/Mips/micromips-movcond-instructions-EB.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "movz $t1, $a2, $a3" + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "movn $t1, $a2, $a3" + - + input: + bytes: [ 0x55, 0x26, 0x09, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "movt $t1, $a2, $fcc0" + - + input: + bytes: [ 0x55, 0x26, 0x01, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "movf $t1, $a2, $fcc0" diff --git a/tests/MC/Mips/micromips-movcond-instructions.s.yaml b/tests/MC/Mips/micromips-movcond-instructions.s.yaml new file mode 100644 index 0000000000..4f091f156f --- /dev/null +++ b/tests/MC/Mips/micromips-movcond-instructions.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0xe6, 0x00, 0x58, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "movz $t1, $a2, $a3" + - + input: + bytes: [ 0xe6, 0x00, 0x18, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "movn $t1, $a2, $a3" + - + input: + bytes: [ 0x26, 0x55, 0x7b, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "movt $t1, $a2, $fcc0" + - + input: + bytes: [ 0x26, 0x55, 0x7b, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "movf $t1, $a2, $fcc0" diff --git a/tests/MC/Mips/micromips-multiply-instructions-EB.s.yaml b/tests/MC/Mips/micromips-multiply-instructions-EB.s.yaml new file mode 100644 index 0000000000..f5d5e1ebd0 --- /dev/null +++ b/tests/MC/Mips/micromips-multiply-instructions-EB.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x00, 0xa4, 0xcb, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "madd $a0, $a1" + - + input: + bytes: [ 0x00, 0xa4, 0xdb, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "maddu $a0, $a1" + - + input: + bytes: [ 0x00, 0xa4, 0xeb, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "msub $a0, $a1" + - + input: + bytes: [ 0x00, 0xa4, 0xfb, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "msubu $a0, $a1" diff --git a/tests/MC/Mips/micromips-multiply-instructions.s.yaml b/tests/MC/Mips/micromips-multiply-instructions.s.yaml new file mode 100644 index 0000000000..743106a289 --- /dev/null +++ b/tests/MC/Mips/micromips-multiply-instructions.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0xa4, 0x00, 0x3c, 0xcb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "madd $a0, $a1" + - + input: + bytes: [ 0xa4, 0x00, 0x3c, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "maddu $a0, $a1" + - + input: + bytes: [ 0xa4, 0x00, 0x3c, 0xeb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "msub $a0, $a1" + - + input: + bytes: [ 0xa4, 0x00, 0x3c, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "msubu $a0, $a1" diff --git a/tests/MC/Mips/micromips-shift-instructions-EB.s.yaml b/tests/MC/Mips/micromips-shift-instructions-EB.s.yaml new file mode 100644 index 0000000000..c833369cfe --- /dev/null +++ b/tests/MC/Mips/micromips-shift-instructions-EB.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x83, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sll $a0, $v1, 7" + - + input: + bytes: [ 0x00, 0x65, 0x10, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sllv $v0, $v1, $a1" + - + input: + bytes: [ 0x00, 0x83, 0x38, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sra $a0, $v1, 7" + - + input: + bytes: [ 0x00, 0x65, 0x10, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "srav $v0, $v1, $a1" + - + input: + bytes: [ 0x00, 0x83, 0x38, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "srl $a0, $v1, 7" + - + input: + bytes: [ 0x00, 0x65, 0x10, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "srlv $v0, $v1, $a1" + - + input: + bytes: [ 0x01, 0x26, 0x38, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "rotr $t1, $a2, 7" + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "rotrv $t1, $a2, $a3" diff --git a/tests/MC/Mips/micromips-shift-instructions.s.yaml b/tests/MC/Mips/micromips-shift-instructions.s.yaml new file mode 100644 index 0000000000..cc8e0d4b16 --- /dev/null +++ b/tests/MC/Mips/micromips-shift-instructions.s.yaml @@ -0,0 +1,73 @@ +test_cases: + - + input: + bytes: [ 0x83, 0x00, 0x00, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sll $a0, $v1, 7" + - + input: + bytes: [ 0x65, 0x00, 0x10, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sllv $v0, $v1, $a1" + - + input: + bytes: [ 0x83, 0x00, 0x80, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "sra $a0, $v1, 7" + - + input: + bytes: [ 0x65, 0x00, 0x90, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "srav $v0, $v1, $a1" + - + input: + bytes: [ 0x83, 0x00, 0x40, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "srl $a0, $v1, 7" + - + input: + bytes: [ 0x65, 0x00, 0x50, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "srlv $v0, $v1, $a1" + - + input: + bytes: [ 0x26, 0x01, 0xc0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "rotr $t1, $a2, 7" + - + input: + bytes: [ 0xc7, 0x00, 0xd0, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "rotrv $t1, $a2, $a3" diff --git a/tests/MC/Mips/micromips-trap-instructions-EB.s.yaml b/tests/MC/Mips/micromips-trap-instructions-EB.s.yaml new file mode 100644 index 0000000000..9f83c760df --- /dev/null +++ b/tests/MC/Mips/micromips-trap-instructions-EB.s.yaml @@ -0,0 +1,55 @@ +test_cases: + - + input: + bytes: [ 0x41, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "teqi $t1, 17767" + - + input: + bytes: [ 0x41, 0x29, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tgei $t1, 17767" + - + input: + bytes: [ 0x41, 0x69, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tgeiu $t1, 17767" + - + input: + bytes: [ 0x41, 0x09, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlti $t1, 17767" + - + input: + bytes: [ 0x41, 0x49, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tltiu $t1, 17767" + - + input: + bytes: [ 0x41, 0x89, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tnei $t1, 17767" diff --git a/tests/MC/Mips/micromips-trap-instructions.s.yaml b/tests/MC/Mips/micromips-trap-instructions.s.yaml new file mode 100644 index 0000000000..7b6cb8c7c9 --- /dev/null +++ b/tests/MC/Mips/micromips-trap-instructions.s.yaml @@ -0,0 +1,55 @@ +test_cases: + - + input: + bytes: [ 0xc9, 0x41, 0x67, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "teqi $t1, 17767" + - + input: + bytes: [ 0x29, 0x41, 0x67, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tgei $t1, 17767" + - + input: + bytes: [ 0x69, 0x41, 0x67, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tgeiu $t1, 17767" + - + input: + bytes: [ 0x09, 0x41, 0x67, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlti $t1, 17767" + - + input: + bytes: [ 0x49, 0x41, 0x67, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tltiu $t1, 17767" + - + input: + bytes: [ 0x89, 0x41, 0x67, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tnei $t1, 17767" diff --git a/tests/MC/Mips/mips-alu-instructions.s.yaml b/tests/MC/Mips/mips-alu-instructions.s.yaml new file mode 100644 index 0000000000..bf9dbc82c5 --- /dev/null +++ b/tests/MC/Mips/mips-alu-instructions.s.yaml @@ -0,0 +1,469 @@ +test_cases: + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "and $t1, $a2, $a3" + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "andi $t1, $a2, 17767" + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "andi $t1, $a2, 17767" + - + input: + bytes: [ 0x67, 0x45, 0x29, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "andi $t1, $t1, 17767" + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clo $a2, $a3" + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clz $a2, $a3" + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ins $s3, $t1, 6, 7" + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "nor $t1, $a2, $a3" + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "or $v1, $v1, $a1" + - + input: + bytes: [ 0x67, 0x45, 0xa4, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ori $a0, $a1, 17767" + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ori $t1, $a2, 17767" + - + input: + bytes: [ 0x80, 0x00, 0x6b, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ori $t3, $t3, 128" + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "rotr $t1, $a2, 7" + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "rotrv $t1, $a2, $a3" + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sll $a0, $v1, 7" + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sllv $v0, $v1, $a1" + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "slt $v1, $v1, $a1" + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "slti $v1, $v1, 103" + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "slti $v1, $v1, 103" + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sltiu $v1, $v1, 103" + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sltu $v1, $v1, $a1" + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sra $a0, $v1, 7" + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srav $v0, $v1, $a1" + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srl $a0, $v1, 7" + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srlv $v0, $v1, $a1" + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "xor $v1, $v1, $a1" + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "xori $t1, $a2, 17767" + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "xori $t1, $a2, 17767" + - + input: + bytes: [ 0x0c, 0x00, 0x6b, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "xori $t3, $t3, 12" + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "wsbh $a2, $a3" + - + input: + bytes: [ 0x27, 0x38, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "not $a3, $t0" + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add $t1, $a2, $a3" + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $t1, $a2, 17767" + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addiu $t1, $a2, -15001" + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $t1, $a2, 17767" + - + input: + bytes: [ 0x67, 0x45, 0x29, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $t1, $t1, 17767" + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addiu $t1, $a2, -15001" + - + input: + bytes: [ 0x28, 0x00, 0x6b, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addiu $t3, $t3, 40" + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addu $t1, $a2, $a3" + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "madd $a2, $a3" + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maddu $a2, $a3" + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "msub $a2, $a3" + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "msubu $a2, $a3" + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mult $v1, $a1" + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "multu $v1, $a1" + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub $t1, $a2, $a3" + - + input: + bytes: [ 0xc8, 0xff, 0xbd, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $sp, $sp, -56" + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "subu $a0, $v1, $a1" + - + input: + bytes: [ 0xd8, 0xff, 0xbd, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addiu $sp, $sp, -40" + - + input: + bytes: [ 0x22, 0x30, 0x07, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "neg $a2, $a3" + - + input: + bytes: [ 0x23, 0x30, 0x07, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "negu $a2, $a3" + - + input: + bytes: [ 0x21, 0x38, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "move $a3, $t0" diff --git a/tests/MC/Mips/mips-control-instructions-64.s.yaml b/tests/MC/Mips/mips-control-instructions-64.s.yaml new file mode 100644 index 0000000000..4986ca48b1 --- /dev/null +++ b/tests/MC/Mips/mips-control-instructions-64.s.yaml @@ -0,0 +1,280 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "break" + - + input: + bytes: [ 0x00, 0x07, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "break 7, 5" + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "syscall" + - + input: + bytes: [ 0x00, 0x0d, 0x15, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "syscall 13396" + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "eret" + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "deret" + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "di" + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "di" + - + input: + bytes: [ 0x41, 0x6a, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "di $t2" + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ei" + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ei" + - + input: + bytes: [ 0x41, 0x6a, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ei $t2" + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "wait" + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "teq $zero, $v1" + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "teq $zero, $v1, 1" + - + input: + bytes: [ 0x04, 0x6c, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "teqi $v1, 1" + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tge $zero, $v1" + - + input: + bytes: [ 0x00, 0x03, 0x00, 0xf0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tge $zero, $v1, 3" + - + input: + bytes: [ 0x04, 0x68, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tgei $v1, 3" + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tgeu $zero, $v1" + - + input: + bytes: [ 0x00, 0x03, 0x01, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tgeu $zero, $v1, 7" + - + input: + bytes: [ 0x04, 0x69, 0x00, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tgeiu $v1, 7" + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tlt $zero, $v1" + - + input: + bytes: [ 0x00, 0x03, 0x07, 0xf2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tlt $zero, $v1, 31" + - + input: + bytes: [ 0x04, 0x6a, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tlti $v1, 31" + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tltu $zero, $v1" + - + input: + bytes: [ 0x00, 0x03, 0x3f, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tltu $zero, $v1, 255" + - + input: + bytes: [ 0x04, 0x6b, 0x00, 0xff ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tltiu $v1, 255" + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tne $zero, $v1" + - + input: + bytes: [ 0x00, 0x03, 0xff, 0xf6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tne $zero, $v1, 1023" + - + input: + bytes: [ 0x04, 0x6e, 0x03, 0xff ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tnei $v1, 1023" diff --git a/tests/MC/Mips/mips-control-instructions.s.yaml b/tests/MC/Mips/mips-control-instructions.s.yaml new file mode 100644 index 0000000000..b526a98334 --- /dev/null +++ b/tests/MC/Mips/mips-control-instructions.s.yaml @@ -0,0 +1,280 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "break" + - + input: + bytes: [ 0x00, 0x07, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "break 7, 5" + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "syscall" + - + input: + bytes: [ 0x00, 0x0d, 0x15, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "syscall 13396" + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "eret" + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "deret" + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "di" + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "di" + - + input: + bytes: [ 0x41, 0x6a, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "di $t2" + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ei" + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ei" + - + input: + bytes: [ 0x41, 0x6a, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ei $t2" + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wait" + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "teq $zero, $v1" + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "teq $zero, $v1, 1" + - + input: + bytes: [ 0x04, 0x6c, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "teqi $v1, 1" + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tge $zero, $v1" + - + input: + bytes: [ 0x00, 0x03, 0x00, 0xf0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tge $zero, $v1, 3" + - + input: + bytes: [ 0x04, 0x68, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tgei $v1, 3" + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tgeu $zero, $v1" + - + input: + bytes: [ 0x00, 0x03, 0x01, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tgeu $zero, $v1, 7" + - + input: + bytes: [ 0x04, 0x69, 0x00, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tgeiu $v1, 7" + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tlt $zero, $v1" + - + input: + bytes: [ 0x00, 0x03, 0x07, 0xf2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tlt $zero, $v1, 31" + - + input: + bytes: [ 0x04, 0x6a, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tlti $v1, 31" + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tltu $zero, $v1" + - + input: + bytes: [ 0x00, 0x03, 0x3f, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tltu $zero, $v1, 255" + - + input: + bytes: [ 0x04, 0x6b, 0x00, 0xff ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tltiu $v1, 255" + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tne $zero, $v1" + - + input: + bytes: [ 0x00, 0x03, 0xff, 0xf6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tne $zero, $v1, 1023" + - + input: + bytes: [ 0x04, 0x6e, 0x03, 0xff ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tnei $v1, 1023" diff --git a/tests/MC/Mips/mips-coprocessor-encodings.s.yaml b/tests/MC/Mips/mips-coprocessor-encodings.s.yaml new file mode 100644 index 0000000000..805d490ac5 --- /dev/null +++ b/tests/MC/Mips/mips-coprocessor-encodings.s.yaml @@ -0,0 +1,145 @@ +test_cases: + - + input: + bytes: [ 0x40, 0xac, 0x80, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmtc0 $t4, $s0, 2" + - + input: + bytes: [ 0x40, 0xac, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmtc0 $t4, $s0, 0" + - + input: + bytes: [ 0x40, 0x8c, 0x80, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtc0 $t4, $s0, 2" + - + input: + bytes: [ 0x40, 0x8c, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtc0 $t4, $s0, 0" + - + input: + bytes: [ 0x40, 0x2c, 0x80, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmfc0 $t4, $s0, 2" + - + input: + bytes: [ 0x40, 0x2c, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmfc0 $t4, $s0, 0" + - + input: + bytes: [ 0x40, 0x0c, 0x80, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfc0 $t4, $s0, 2" + - + input: + bytes: [ 0x40, 0x0c, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfc0 $t4, $s0, 0" + - + input: + bytes: [ 0x48, 0xac, 0x80, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmtc2 $t4, $s0, 2" + - + input: + bytes: [ 0x48, 0xac, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmtc2 $t4, $s0, 0" + - + input: + bytes: [ 0x48, 0x8c, 0x80, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtc2 $t4, $s0, 2" + - + input: + bytes: [ 0x48, 0x8c, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtc2 $t4, $s0, 0" + - + input: + bytes: [ 0x48, 0x2c, 0x80, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmfc2 $t4, $s0, 2" + - + input: + bytes: [ 0x48, 0x2c, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmfc2 $t4, $s0, 0" + - + input: + bytes: [ 0x48, 0x0c, 0x80, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfc2 $t4, $s0, 2" + - + input: + bytes: [ 0x48, 0x0c, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfc2 $t4, $s0, 0" diff --git a/tests/MC/Mips/mips-dsp-instructions.s.yaml b/tests/MC/Mips/mips-dsp-instructions.s.yaml new file mode 100644 index 0000000000..e986d707b6 --- /dev/null +++ b/tests/MC/Mips/mips-dsp-instructions.s.yaml @@ -0,0 +1,343 @@ +test_cases: + - + input: + bytes: [ 0x7e, 0x32, 0x83, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "precrq.qb.ph $s0, $s1, $s2" + - + input: + bytes: [ 0x7e, 0x53, 0x8d, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "precrq.ph.w $s1, $s2, $s3" + - + input: + bytes: [ 0x7e, 0x74, 0x95, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "precrq_rs.ph.w $s2, $s3, $s4" + - + input: + bytes: [ 0x7e, 0x95, 0x9b, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "precrqu_s.qb.ph $s3, $s4, $s5" + - + input: + bytes: [ 0x7c, 0x15, 0xa3, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "preceq.w.phl $s4, $s5" + - + input: + bytes: [ 0x7c, 0x16, 0xab, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "preceq.w.phr $s5, $s6" + - + input: + bytes: [ 0x7c, 0x17, 0xb1, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "precequ.ph.qbl $s6, $s7" + - + input: + bytes: [ 0x7c, 0x18, 0xb9, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "precequ.ph.qbr $s7, $t8" + - + input: + bytes: [ 0x7c, 0x19, 0xc1, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "precequ.ph.qbla $t8, $t9" + - + input: + bytes: [ 0x7c, 0x1a, 0xc9, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "precequ.ph.qbra $t9, $k0" + - + input: + bytes: [ 0x7c, 0x1b, 0xd7, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "preceu.ph.qbl $k0, $k1" + - + input: + bytes: [ 0x7c, 0x1c, 0xdf, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "preceu.ph.qbr $k1, $gp" + - + input: + bytes: [ 0x7c, 0x1d, 0xe7, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "preceu.ph.qbla $gp, $sp" + - + input: + bytes: [ 0x7c, 0x1e, 0xef, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "preceu.ph.qbra $sp, $fp" + - + input: + bytes: [ 0x7f, 0x19, 0xbb, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "precr.qb.ph $s7, $t8, $t9" + - + input: + bytes: [ 0x7f, 0x38, 0x07, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "precr_sra.ph.w $t8, $t9, 0" + - + input: + bytes: [ 0x7f, 0x38, 0xff, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "precr_sra.ph.w $t8, $t9, 31" + - + input: + bytes: [ 0x7f, 0x59, 0x07, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "precr_sra_r.ph.w $t9, $k0, 0" + - + input: + bytes: [ 0x7f, 0x59, 0xff, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "precr_sra_r.ph.w $t9, $k0, 31" + - + input: + bytes: [ 0x7f, 0x54, 0x51, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbux $t2, $s4($k0)" + - + input: + bytes: [ 0x7f, 0x75, 0x59, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhx $t3, $s5($k1)" + - + input: + bytes: [ 0x7f, 0x96, 0x60, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lwx $t4, $s6($gp)" + - + input: + bytes: [ 0x00, 0x43, 0x18, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mult $ac3, $v0, $v1" + - + input: + bytes: [ 0x00, 0x85, 0x10, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "multu $ac2, $a0, $a1" + - + input: + bytes: [ 0x70, 0xc7, 0x08, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madd $ac1, $a2, $a3" + - + input: + bytes: [ 0x71, 0x4b, 0x18, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msub $ac3, $t2, $t3" + - + input: + bytes: [ 0x71, 0x8d, 0x10, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msubu $ac2, $t4, $t5" + - + input: + bytes: [ 0x00, 0x20, 0x70, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfhi $t6, $ac1" + - + input: + bytes: [ 0x02, 0x00, 0x18, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mthi $s0, $ac3" + - + input: + bytes: [ 0x02, 0x20, 0x10, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtlo $s1, $ac2" + - + input: + bytes: [ 0x00, 0x43, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mult $v0, $v1" + - + input: + bytes: [ 0x00, 0x85, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "multu $a0, $a1" + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madd $a2, $a3" + - + input: + bytes: [ 0x71, 0x4b, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msub $t2, $t3" + - + input: + bytes: [ 0x71, 0x8d, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msubu $t4, $t5" + - + input: + bytes: [ 0x00, 0x00, 0x70, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfhi $t6" + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mthi $s0" + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtlo $s1" diff --git a/tests/MC/Mips/mips-expansions.s.yaml b/tests/MC/Mips/mips-expansions.s.yaml new file mode 100644 index 0000000000..b52e9eba52 --- /dev/null +++ b/tests/MC/Mips/mips-expansions.s.yaml @@ -0,0 +1,154 @@ +test_cases: + - + input: + bytes: [ 0x7b, 0x00, 0x05, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ori $a1, $zero, 123" + - + input: + bytes: [ 0xd7, 0xf6, 0x06, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addiu $a2, $zero, -2345" + - + input: + bytes: [ 0x01, 0x00, 0x07, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lui $a3, 1" + - + input: + bytes: [ 0x02, 0x00, 0xe7, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ori $a3, $a3, 2" + - + input: + bytes: [ 0x14, 0x00, 0x04, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addiu $a0, $zero, 20" + - + input: + bytes: [ 0x01, 0x00, 0x07, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lui $a3, 1" + - + input: + bytes: [ 0x02, 0x00, 0xe7, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ori $a3, $a3, 2" + - + input: + bytes: [ 0x14, 0x00, 0xa4, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addiu $a0, $a1, 20" + - + input: + bytes: [ 0x01, 0x00, 0x07, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lui $a3, 1" + - + input: + bytes: [ 0x02, 0x00, 0xe7, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ori $a3, $a3, 2" + - + input: + bytes: [ 0x21, 0x38, 0xe8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addu $a3, $a3, $t0" + - + input: + bytes: [ 0x21, 0x50, 0x44, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addu $t2, $t2, $a0" + - + input: + bytes: [ 0x21, 0x08, 0x29, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addu $at, $at, $t1" + - + input: + bytes: [ 0x0a, 0x00, 0x0a, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lui $t2, 10" + - + input: + bytes: [ 0x7b, 0x00, 0x4a, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lw $t2, 123($t2)" + - + input: + bytes: [ 0x02, 0x00, 0x01, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lui $at, 2" + - + input: + bytes: [ 0x21, 0x08, 0x29, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addu $at, $at, $t1" diff --git a/tests/MC/Mips/mips-fpu-instructions.s.yaml b/tests/MC/Mips/mips-fpu-instructions.s.yaml new file mode 100644 index 0000000000..0ff331ea6f --- /dev/null +++ b/tests/MC/Mips/mips-fpu-instructions.s.yaml @@ -0,0 +1,829 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + - + input: + bytes: [ 0x00, 0x00, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cfc1 $a2, $0" + - + input: + bytes: [ 0x00, 0xf8, 0xca, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ctc1 $t2, $31" + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfc1 $a2, $f7" + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfhi $a1" + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mflo $a1" + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtc1 $a2, $f7" + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mthi $a3" + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtlo $a3" + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($a3)" + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfc0 $a2, $a3, 0" + - + input: + bytes: [ 0x00, 0x40, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtc0 $t1, $t0, 0" + - + input: + bytes: [ 0x00, 0x38, 0x05, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfc2 $a1, $a3, 0" + - + input: + bytes: [ 0x00, 0x20, 0x89, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtc2 $t1, $a0, 0" + - + input: + bytes: [ 0x02, 0x38, 0x06, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfc0 $a2, $a3, 2" + - + input: + bytes: [ 0x03, 0x40, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtc0 $t1, $t0, 3" + - + input: + bytes: [ 0x04, 0x38, 0x05, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfc2 $a1, $a3, 4" + - + input: + bytes: [ 0x05, 0x20, 0x89, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtc2 $t1, $a0, 5" + - + input: + bytes: [ 0x01, 0x10, 0x20, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movf $v0, $at, $fcc0" + - + input: + bytes: [ 0x01, 0x10, 0x21, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movt $v0, $at, $fcc0" + - + input: + bytes: [ 0x01, 0x20, 0xb1, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movt $a0, $a1, $fcc4" + - + input: + bytes: [ 0x11, 0x31, 0x28, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f6, $fcc2" + - + input: + bytes: [ 0x11, 0x31, 0x14, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f6, $fcc5" + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $a2($a1)" + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $t8($a1)" + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $t4($t6)" + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $s2($s6)" + - + input: + bytes: [ 0x00, 0x20, 0x71, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfhc1 $s1, $f4" + - + input: + bytes: [ 0x00, 0x30, 0xf1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mthc1 $s1, $f6" + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xeb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swc2 $4, 16($sp)" + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sdc2 $4, 16($sp)" + - + input: + bytes: [ 0x0c, 0x00, 0xeb, 0xcb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwc2 $11, 12($ra)" + - + input: + bytes: [ 0x0c, 0x00, 0xeb, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ldc2 $11, 12($ra)" diff --git a/tests/MC/Mips/mips-memory-instructions.s.yaml b/tests/MC/Mips/mips-memory-instructions.s.yaml new file mode 100644 index 0000000000..ab3997e12b --- /dev/null +++ b/tests/MC/Mips/mips-memory-instructions.s.yaml @@ -0,0 +1,145 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sb $a0, 16($a1)" + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sc $a0, 16($a1)" + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sh $a0, 16($a1)" + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sw $a0, 16($a1)" + - + input: + bytes: [ 0x00, 0x00, 0xa7, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sw $a3, ($a1)" + - + input: + bytes: [ 0x10, 0x00, 0xa2, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swc1 $f2, 16($a1)" + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swl $a0, 16($a1)" + - + input: + bytes: [ 0x04, 0x00, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lb $a0, 4($a1)" + - + input: + bytes: [ 0x04, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lw $a0, 4($a1)" + - + input: + bytes: [ 0x04, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lbu $a0, 4($a1)" + - + input: + bytes: [ 0x04, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lh $a0, 4($a1)" + - + input: + bytes: [ 0x04, 0x00, 0xa4, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lhu $a0, 4($a1)" + - + input: + bytes: [ 0x04, 0x00, 0xa4, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ll $a0, 4($a1)" + - + input: + bytes: [ 0x04, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lw $a0, 4($a1)" + - + input: + bytes: [ 0x00, 0x00, 0xe7, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lw $a3, ($a3)" + - + input: + bytes: [ 0x10, 0x00, 0xa2, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lw $v0, 16($sp)" diff --git a/tests/MC/Mips/mips-register-names.s.yaml b/tests/MC/Mips/mips-register-names.s.yaml new file mode 100644 index 0000000000..03b6feb309 --- /dev/null +++ b/tests/MC/Mips/mips-register-names.s.yaml @@ -0,0 +1,280 @@ +test_cases: + - + input: + bytes: [ 0x24, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, 0" + - + input: + bytes: [ 0x24, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $at, $zero, 0" + - + input: + bytes: [ 0x24, 0x02, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $v0, $zero, 0" + - + input: + bytes: [ 0x24, 0x03, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $v1, $zero, 0" + - + input: + bytes: [ 0x24, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $a0, $zero, 0" + - + input: + bytes: [ 0x24, 0x05, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $a1, $zero, 0" + - + input: + bytes: [ 0x24, 0x06, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $a2, $zero, 0" + - + input: + bytes: [ 0x24, 0x07, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $a3, $zero, 0" + - + input: + bytes: [ 0x24, 0x08, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $t0, $zero, 0" + - + input: + bytes: [ 0x24, 0x09, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $t1, $zero, 0" + - + input: + bytes: [ 0x24, 0x0a, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $t2, $zero, 0" + - + input: + bytes: [ 0x24, 0x0b, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $t3, $zero, 0" + - + input: + bytes: [ 0x24, 0x0c, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $t4, $zero, 0" + - + input: + bytes: [ 0x24, 0x0d, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $t5, $zero, 0" + - + input: + bytes: [ 0x24, 0x0e, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $t6, $zero, 0" + - + input: + bytes: [ 0x24, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $t7, $zero, 0" + - + input: + bytes: [ 0x24, 0x10, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $s0, $zero, 0" + - + input: + bytes: [ 0x24, 0x11, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $s1, $zero, 0" + - + input: + bytes: [ 0x24, 0x12, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $s2, $zero, 0" + - + input: + bytes: [ 0x24, 0x13, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $s3, $zero, 0" + - + input: + bytes: [ 0x24, 0x14, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $s4, $zero, 0" + - + input: + bytes: [ 0x24, 0x15, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $s5, $zero, 0" + - + input: + bytes: [ 0x24, 0x16, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $s6, $zero, 0" + - + input: + bytes: [ 0x24, 0x17, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $s7, $zero, 0" + - + input: + bytes: [ 0x24, 0x18, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $t8, $zero, 0" + - + input: + bytes: [ 0x24, 0x19, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $t9, $zero, 0" + - + input: + bytes: [ 0x24, 0x1a, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $k0, $zero, 0" + - + input: + bytes: [ 0x24, 0x1b, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $k1, $zero, 0" + - + input: + bytes: [ 0x24, 0x1c, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $gp, $zero, 0" + - + input: + bytes: [ 0x24, 0x1d, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $sp, $zero, 0" + - + input: + bytes: [ 0x24, 0x1e, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addiu $fp, $zero, 0" diff --git a/tests/MC/Mips/mips64-alu-instructions.s.yaml b/tests/MC/Mips/mips64-alu-instructions.s.yaml new file mode 100644 index 0000000000..258f568304 --- /dev/null +++ b/tests/MC/Mips/mips64-alu-instructions.s.yaml @@ -0,0 +1,406 @@ +test_cases: + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "and $t1, $a2, $a3" + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "andi $t1, $a2, 17767" + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "andi $t1, $a2, 17767" + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "clo $a2, $a3" + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "clz $a2, $a3" + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ins $s3, $t1, 6, 7" + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "nor $t1, $a2, $a3" + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "or $v1, $v1, $a1" + - + input: + bytes: [ 0x67, 0x45, 0xa4, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ori $a0, $a1, 17767" + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ori $t1, $a2, 17767" + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "rotr $t1, $a2, 7" + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "rotrv $t1, $a2, $a3" + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sll $a0, $v1, 7" + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sllv $v0, $v1, $a1" + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "slt $v1, $v1, $a1" + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "slti $v1, $v1, 103" + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "slti $v1, $v1, 103" + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sltiu $v1, $v1, 103" + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sltu $v1, $v1, $a1" + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sra $a0, $v1, 7" + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srav $v0, $v1, $a1" + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srl $a0, $v1, 7" + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srlv $v0, $v1, $a1" + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "xor $v1, $v1, $a1" + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "xori $t1, $a2, 17767" + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "xori $t1, $a2, 17767" + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "wsbh $a2, $a3" + - + input: + bytes: [ 0x27, 0x38, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "not $a3, $t0" + - + input: + bytes: [ 0x2c, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dadd $t1, $a2, $a3" + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddi $t1, $a2, 17767" + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $t1, $a2, -15001" + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddi $t1, $a2, 17767" + - + input: + bytes: [ 0x67, 0x45, 0x29, 0x61 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddi $t1, $t1, 17767" + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $t1, $a2, -15001" + - + input: + bytes: [ 0x67, 0xc5, 0x29, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $t1, $t1, -15001" + - + input: + bytes: [ 0x2d, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddu $t1, $a2, $a3" + - + input: + bytes: [ 0x3a, 0x4d, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "drotr $t1, $a2, 20" + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "madd $a2, $a3" + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "maddu $a2, $a3" + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "msub $a2, $a3" + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "msubu $a2, $a3" + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mult $v1, $a1" + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "multu $v1, $a1" + - + input: + bytes: [ 0x2f, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsubu $a0, $v1, $a1" + - + input: + bytes: [ 0x2d, 0x38, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "move $a3, $t0" diff --git a/tests/MC/Mips/mips64-instructions.s.yaml b/tests/MC/Mips/mips64-instructions.s.yaml new file mode 100644 index 0000000000..082a3d4043 --- /dev/null +++ b/tests/MC/Mips/mips64-instructions.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0x81, 0x00, 0x42, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldxc1 $f2, $v0($t2)" + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $a0($t9)" diff --git a/tests/MC/Mips/mips64-register-names.s.yaml b/tests/MC/Mips/mips64-register-names.s.yaml new file mode 100644 index 0000000000..659bfb3c72 --- /dev/null +++ b/tests/MC/Mips/mips64-register-names.s.yaml @@ -0,0 +1,217 @@ +test_cases: + - + input: + bytes: [ 0x64, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $zero, $zero, 0" + - + input: + bytes: [ 0x64, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $at, $zero, 0" + - + input: + bytes: [ 0x64, 0x02, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $v0, $zero, 0" + - + input: + bytes: [ 0x64, 0x03, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $v1, $zero, 0" + - + input: + bytes: [ 0x64, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $a0, $zero, 0" + - + input: + bytes: [ 0x64, 0x05, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $a1, $zero, 0" + - + input: + bytes: [ 0x64, 0x06, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $a2, $zero, 0" + - + input: + bytes: [ 0x64, 0x0c, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $t4, $zero, 0" + - + input: + bytes: [ 0x64, 0x0d, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $t5, $zero, 0" + - + input: + bytes: [ 0x64, 0x0e, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $t6, $zero, 0" + - + input: + bytes: [ 0x64, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $t7, $zero, 0" + - + input: + bytes: [ 0x64, 0x10, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $s0, $zero, 0" + - + input: + bytes: [ 0x64, 0x11, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $s1, $zero, 0" + - + input: + bytes: [ 0x64, 0x12, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $s2, $zero, 0" + - + input: + bytes: [ 0x64, 0x13, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $s3, $zero, 0" + - + input: + bytes: [ 0x64, 0x14, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $s4, $zero, 0" + - + input: + bytes: [ 0x64, 0x15, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $s5, $zero, 0" + - + input: + bytes: [ 0x64, 0x16, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $s6, $zero, 0" + - + input: + bytes: [ 0x64, 0x17, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $s7, $zero, 0" + - + input: + bytes: [ 0x64, 0x18, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $t8, $zero, 0" + - + input: + bytes: [ 0x64, 0x19, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $t9, $zero, 0" + - + input: + bytes: [ 0x64, 0x1c, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $gp, $zero, 0" + - + input: + bytes: [ 0x64, 0x1d, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $sp, $zero, 0" + - + input: + bytes: [ 0x64, 0x1f, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $ra, $zero, 0" diff --git a/tests/MC/Mips/mips_directives.s.yaml b/tests/MC/Mips/mips_directives.s.yaml new file mode 100644 index 0000000000..32f6c4d36a --- /dev/null +++ b/tests/MC/Mips/mips_directives.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "b 1336" + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "j 1328" + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "jal 1328" + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "b 1336" + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "j 1328" + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "jal 1328" + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + - + input: + bytes: [ 0x01, 0xef, 0x18, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "and $v1, $t7, $t7" diff --git a/tests/MC/Mips/nabi-regs.s.yaml b/tests/MC/Mips/nabi-regs.s.yaml new file mode 100644 index 0000000000..1a6c62346d --- /dev/null +++ b/tests/MC/Mips/nabi-regs.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x02, 0x04, 0x80, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add $s0, $s0, $a0" + - + input: + bytes: [ 0x02, 0x06, 0x80, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add $s0, $s0, $a2" + - + input: + bytes: [ 0x02, 0x07, 0x80, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add $s0, $s0, $a3" + - + input: + bytes: [ 0x02, 0x08, 0x80, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add $s0, $s0, $t0" + - + input: + bytes: [ 0x02, 0x09, 0x80, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add $s0, $s0, $t1" + - + input: + bytes: [ 0x02, 0x0a, 0x80, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add $s0, $s0, $t2" + - + input: + bytes: [ 0x02, 0x0b, 0x80, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add $s0, $s0, $t3" + - + input: + bytes: [ 0x02, 0x0c, 0x80, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add $s0, $s0, $t4" + - + input: + bytes: [ 0x02, 0x0d, 0x80, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add $s0, $s0, $t5" + - + input: + bytes: [ 0x02, 0x0e, 0x80, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add $s0, $s0, $t6" + - + input: + bytes: [ 0x02, 0x0f, 0x80, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add $s0, $s0, $t7" diff --git a/tests/MC/Mips/set-at-directive.s.yaml b/tests/MC/Mips/set-at-directive.s.yaml new file mode 100644 index 0000000000..422a55854c --- /dev/null +++ b/tests/MC/Mips/set-at-directive.s.yaml @@ -0,0 +1,46 @@ +test_cases: + - + input: + bytes: [ 0x08, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jr $v1" + - + input: + bytes: [ 0x08, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jr $gp" + - + input: + bytes: [ 0x08, 0x00, 0xc0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jr $fp" + - + input: + bytes: [ 0x08, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jr $sp" + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jr $ra" diff --git a/tests/MC/Mips/test_2r.s.yaml b/tests/MC/Mips/test_2r.s.yaml new file mode 100644 index 0000000000..ee3216f957 --- /dev/null +++ b/tests/MC/Mips/test_2r.s.yaml @@ -0,0 +1,136 @@ +test_cases: + - + input: + bytes: [ 0x7b, 0x00, 0x4f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fill.b $w30, $t1" + - + input: + bytes: [ 0x7b, 0x01, 0xbf, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fill.h $w31, $s7" + - + input: + bytes: [ 0x7b, 0x02, 0xc4, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fill.w $w16, $t8" + - + input: + bytes: [ 0x7b, 0x08, 0x05, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nloc.b $w21, $w0" + - + input: + bytes: [ 0x7b, 0x09, 0xfc, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nloc.h $w18, $w31" + - + input: + bytes: [ 0x7b, 0x0a, 0xb8, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nloc.w $w2, $w23" + - + input: + bytes: [ 0x7b, 0x0b, 0x51, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nloc.d $w4, $w10" + - + input: + bytes: [ 0x7b, 0x0c, 0x17, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nlzc.b $w31, $w2" + - + input: + bytes: [ 0x7b, 0x0d, 0xb6, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nlzc.h $w27, $w22" + - + input: + bytes: [ 0x7b, 0x0e, 0xea, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nlzc.w $w10, $w29" + - + input: + bytes: [ 0x7b, 0x0f, 0x4e, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nlzc.d $w25, $w9" + - + input: + bytes: [ 0x7b, 0x04, 0x95, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pcnt.b $w20, $w18" + - + input: + bytes: [ 0x7b, 0x05, 0x40, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pcnt.h $w0, $w8" + - + input: + bytes: [ 0x7b, 0x06, 0x4d, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pcnt.w $w23, $w9" + - + input: + bytes: [ 0x7b, 0x07, 0xc5, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pcnt.d $w21, $w24" diff --git a/tests/MC/Mips/test_2rf.s.yaml b/tests/MC/Mips/test_2rf.s.yaml new file mode 100644 index 0000000000..14e13eb112 --- /dev/null +++ b/tests/MC/Mips/test_2rf.s.yaml @@ -0,0 +1,289 @@ +test_cases: + - + input: + bytes: [ 0x7b, 0x20, 0x66, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fclass.w $w26, $w12" + - + input: + bytes: [ 0x7b, 0x21, 0x8e, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fclass.d $w24, $w17" + - + input: + bytes: [ 0x7b, 0x30, 0x02, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fexupl.w $w8, $w0" + - + input: + bytes: [ 0x7b, 0x31, 0xec, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fexupl.d $w17, $w29" + - + input: + bytes: [ 0x7b, 0x32, 0x23, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fexupr.w $w13, $w4" + - + input: + bytes: [ 0x7b, 0x33, 0x11, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fexupr.d $w5, $w2" + - + input: + bytes: [ 0x7b, 0x3c, 0xed, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ffint_s.w $w20, $w29" + - + input: + bytes: [ 0x7b, 0x3d, 0x7b, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ffint_s.d $w12, $w15" + - + input: + bytes: [ 0x7b, 0x3e, 0xd9, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ffint_u.w $w7, $w27" + - + input: + bytes: [ 0x7b, 0x3f, 0x84, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ffint_u.d $w19, $w16" + - + input: + bytes: [ 0x7b, 0x34, 0x6f, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ffql.w $w31, $w13" + - + input: + bytes: [ 0x7b, 0x35, 0x6b, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ffql.d $w12, $w13" + - + input: + bytes: [ 0x7b, 0x36, 0xf6, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ffqr.w $w27, $w30" + - + input: + bytes: [ 0x7b, 0x37, 0x7f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ffqr.d $w30, $w15" + - + input: + bytes: [ 0x7b, 0x2e, 0xfe, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "flog2.w $w25, $w31" + - + input: + bytes: [ 0x7b, 0x2f, 0x54, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "flog2.d $w18, $w10" + - + input: + bytes: [ 0x7b, 0x2c, 0x79, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "frint.w $w7, $w15" + - + input: + bytes: [ 0x7b, 0x2d, 0xb5, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "frint.d $w21, $w22" + - + input: + bytes: [ 0x7b, 0x2a, 0x04, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "frcp.w $w19, $w0" + - + input: + bytes: [ 0x7b, 0x2b, 0x71, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "frcp.d $w4, $w14" + - + input: + bytes: [ 0x7b, 0x28, 0x8b, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "frsqrt.w $w12, $w17" + - + input: + bytes: [ 0x7b, 0x29, 0x5d, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "frsqrt.d $w23, $w11" + - + input: + bytes: [ 0x7b, 0x26, 0x58, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsqrt.w $w0, $w11" + - + input: + bytes: [ 0x7b, 0x27, 0x63, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsqrt.d $w15, $w12" + - + input: + bytes: [ 0x7b, 0x38, 0x2f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ftint_s.w $w30, $w5" + - + input: + bytes: [ 0x7b, 0x39, 0xb9, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ftint_s.d $w5, $w23" + - + input: + bytes: [ 0x7b, 0x3a, 0x75, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ftint_u.w $w20, $w14" + - + input: + bytes: [ 0x7b, 0x3b, 0xad, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ftint_u.d $w23, $w21" + - + input: + bytes: [ 0x7b, 0x22, 0x8f, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ftrunc_s.w $w29, $w17" + - + input: + bytes: [ 0x7b, 0x23, 0xdb, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ftrunc_s.d $w12, $w27" + - + input: + bytes: [ 0x7b, 0x24, 0x7c, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ftrunc_u.w $w17, $w15" + - + input: + bytes: [ 0x7b, 0x25, 0xd9, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ftrunc_u.d $w5, $w27" diff --git a/tests/MC/Mips/test_3r.s.yaml b/tests/MC/Mips/test_3r.s.yaml new file mode 100644 index 0000000000..bbee76575c --- /dev/null +++ b/tests/MC/Mips/test_3r.s.yaml @@ -0,0 +1,2179 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x04, 0x4e, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "add_a.b $w26, $w9, $w4" + - + input: + bytes: [ 0x78, 0x3f, 0xdd, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "add_a.h $w23, $w27, $w31" + - + input: + bytes: [ 0x78, 0x56, 0x32, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "add_a.w $w11, $w6, $w22" + - + input: + bytes: [ 0x78, 0x60, 0x51, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "add_a.d $w6, $w10, $w0" + - + input: + bytes: [ 0x78, 0x93, 0xc4, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adds_a.b $w19, $w24, $w19" + - + input: + bytes: [ 0x78, 0xa4, 0x36, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adds_a.h $w25, $w6, $w4" + - + input: + bytes: [ 0x78, 0xdb, 0x8e, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adds_a.w $w25, $w17, $w27" + - + input: + bytes: [ 0x78, 0xfa, 0x93, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adds_a.d $w15, $w18, $w26" + - + input: + bytes: [ 0x79, 0x13, 0x5f, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adds_s.b $w29, $w11, $w19" + - + input: + bytes: [ 0x79, 0x3a, 0xb9, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adds_s.h $w5, $w23, $w26" + - + input: + bytes: [ 0x79, 0x4d, 0x74, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adds_s.w $w16, $w14, $w13" + - + input: + bytes: [ 0x79, 0x7c, 0x70, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adds_s.d $w2, $w14, $w28" + - + input: + bytes: [ 0x79, 0x8e, 0x88, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adds_u.b $w3, $w17, $w14" + - + input: + bytes: [ 0x79, 0xa4, 0xf2, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adds_u.h $w10, $w30, $w4" + - + input: + bytes: [ 0x79, 0xd4, 0x93, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adds_u.w $w15, $w18, $w20" + - + input: + bytes: [ 0x79, 0xe9, 0x57, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adds_u.d $w30, $w10, $w9" + - + input: + bytes: [ 0x78, 0x15, 0xa6, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addv.b $w24, $w20, $w21" + - + input: + bytes: [ 0x78, 0x3b, 0x69, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addv.h $w4, $w13, $w27" + - + input: + bytes: [ 0x78, 0x4e, 0x5c, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addv.w $w19, $w11, $w14" + - + input: + bytes: [ 0x78, 0x7f, 0xa8, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addv.d $w2, $w21, $w31" + - + input: + bytes: [ 0x7a, 0x03, 0x85, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asub_s.b $w23, $w16, $w3" + - + input: + bytes: [ 0x7a, 0x39, 0x8d, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asub_s.h $w22, $w17, $w25" + - + input: + bytes: [ 0x7a, 0x49, 0x0e, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asub_s.w $w24, $w1, $w9" + - + input: + bytes: [ 0x7a, 0x6c, 0x63, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asub_s.d $w13, $w12, $w12" + - + input: + bytes: [ 0x7a, 0x8b, 0xea, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asub_u.b $w10, $w29, $w11" + - + input: + bytes: [ 0x7a, 0xaf, 0x4c, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asub_u.h $w18, $w9, $w15" + - + input: + bytes: [ 0x7a, 0xdf, 0x9a, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asub_u.w $w10, $w19, $w31" + - + input: + bytes: [ 0x7a, 0xe0, 0x54, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asub_u.d $w17, $w10, $w0" + - + input: + bytes: [ 0x7a, 0x01, 0x28, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ave_s.b $w2, $w5, $w1" + - + input: + bytes: [ 0x7a, 0x29, 0x9c, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ave_s.h $w16, $w19, $w9" + - + input: + bytes: [ 0x7a, 0x45, 0xfc, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ave_s.w $w17, $w31, $w5" + - + input: + bytes: [ 0x7a, 0x6a, 0xce, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ave_s.d $w27, $w25, $w10" + - + input: + bytes: [ 0x7a, 0x89, 0x9c, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ave_u.b $w16, $w19, $w9" + - + input: + bytes: [ 0x7a, 0xab, 0xe7, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ave_u.h $w28, $w28, $w11" + - + input: + bytes: [ 0x7a, 0xcb, 0x62, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ave_u.w $w11, $w12, $w11" + - + input: + bytes: [ 0x7a, 0xfc, 0x9f, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ave_u.d $w30, $w19, $w28" + - + input: + bytes: [ 0x7b, 0x02, 0x86, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aver_s.b $w26, $w16, $w2" + - + input: + bytes: [ 0x7b, 0x3b, 0xdf, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aver_s.h $w31, $w27, $w27" + - + input: + bytes: [ 0x7b, 0x59, 0x97, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aver_s.w $w28, $w18, $w25" + - + input: + bytes: [ 0x7b, 0x7b, 0xaf, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aver_s.d $w29, $w21, $w27" + - + input: + bytes: [ 0x7b, 0x83, 0xd7, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aver_u.b $w29, $w26, $w3" + - + input: + bytes: [ 0x7b, 0xa9, 0x94, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aver_u.h $w18, $w18, $w9" + - + input: + bytes: [ 0x7b, 0xdd, 0xcc, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aver_u.w $w17, $w25, $w29" + - + input: + bytes: [ 0x7b, 0xf3, 0xb5, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aver_u.d $w22, $w22, $w19" + - + input: + bytes: [ 0x79, 0x9d, 0x78, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bclr.b $w2, $w15, $w29" + - + input: + bytes: [ 0x79, 0xbc, 0xac, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bclr.h $w16, $w21, $w28" + - + input: + bytes: [ 0x79, 0xc9, 0x14, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bclr.w $w19, $w2, $w9" + - + input: + bytes: [ 0x79, 0xe4, 0xfe, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bclr.d $w27, $w31, $w4" + - + input: + bytes: [ 0x7b, 0x18, 0x81, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binsl.b $w5, $w16, $w24" + - + input: + bytes: [ 0x7b, 0x2a, 0x2f, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binsl.h $w30, $w5, $w10" + - + input: + bytes: [ 0x7b, 0x4d, 0x7b, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binsl.w $w14, $w15, $w13" + - + input: + bytes: [ 0x7b, 0x6c, 0xa5, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binsl.d $w23, $w20, $w12" + - + input: + bytes: [ 0x7b, 0x82, 0x5d, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binsr.b $w22, $w11, $w2" + - + input: + bytes: [ 0x7b, 0xa6, 0xd0, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binsr.h $w0, $w26, $w6" + - + input: + bytes: [ 0x7b, 0xdc, 0x1e, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binsr.w $w26, $w3, $w28" + - + input: + bytes: [ 0x7b, 0xf5, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binsr.d $w0, $w0, $w21" + - + input: + bytes: [ 0x7a, 0x98, 0x58, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bneg.b $w0, $w11, $w24" + - + input: + bytes: [ 0x7a, 0xa4, 0x87, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bneg.h $w28, $w16, $w4" + - + input: + bytes: [ 0x7a, 0xd3, 0xd0, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bneg.w $w3, $w26, $w19" + - + input: + bytes: [ 0x7a, 0xef, 0xeb, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bneg.d $w13, $w29, $w15" + - + input: + bytes: [ 0x7a, 0x1f, 0x2f, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bset.b $w31, $w5, $w31" + - + input: + bytes: [ 0x7a, 0x26, 0x63, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bset.h $w14, $w12, $w6" + - + input: + bytes: [ 0x7a, 0x4c, 0x4f, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bset.w $w31, $w9, $w12" + - + input: + bytes: [ 0x7a, 0x65, 0xb1, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bset.d $w5, $w22, $w5" + - + input: + bytes: [ 0x78, 0x12, 0xff, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ceq.b $w31, $w31, $w18" + - + input: + bytes: [ 0x78, 0x29, 0xda, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ceq.h $w10, $w27, $w9" + - + input: + bytes: [ 0x78, 0x4e, 0x2a, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ceq.w $w9, $w5, $w14" + - + input: + bytes: [ 0x78, 0x60, 0x89, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ceq.d $w5, $w17, $w0" + - + input: + bytes: [ 0x7a, 0x09, 0x25, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cle_s.b $w23, $w4, $w9" + - + input: + bytes: [ 0x7a, 0x33, 0xdd, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cle_s.h $w22, $w27, $w19" + - + input: + bytes: [ 0x7a, 0x4a, 0xd7, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cle_s.w $w30, $w26, $w10" + - + input: + bytes: [ 0x7a, 0x6a, 0x2c, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cle_s.d $w18, $w5, $w10" + - + input: + bytes: [ 0x7a, 0x80, 0xc8, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cle_u.b $w1, $w25, $w0" + - + input: + bytes: [ 0x7a, 0xbd, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cle_u.h $w7, $w0, $w29" + - + input: + bytes: [ 0x7a, 0xc1, 0x96, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cle_u.w $w25, $w18, $w1" + - + input: + bytes: [ 0x7a, 0xfe, 0x01, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cle_u.d $w6, $w0, $w30" + - + input: + bytes: [ 0x79, 0x15, 0x16, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clt_s.b $w25, $w2, $w21" + - + input: + bytes: [ 0x79, 0x29, 0x98, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clt_s.h $w2, $w19, $w9" + - + input: + bytes: [ 0x79, 0x50, 0x45, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clt_s.w $w23, $w8, $w16" + - + input: + bytes: [ 0x79, 0x6c, 0xf1, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clt_s.d $w7, $w30, $w12" + - + input: + bytes: [ 0x79, 0x8d, 0xf8, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clt_u.b $w2, $w31, $w13" + - + input: + bytes: [ 0x79, 0xb7, 0xfc, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clt_u.h $w16, $w31, $w23" + - + input: + bytes: [ 0x79, 0xc9, 0xc0, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clt_u.w $w3, $w24, $w9" + - + input: + bytes: [ 0x79, 0xe1, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clt_u.d $w7, $w0, $w1" + - + input: + bytes: [ 0x7a, 0x12, 0x1f, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "div_s.b $w29, $w3, $w18" + - + input: + bytes: [ 0x7a, 0x2d, 0x84, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "div_s.h $w17, $w16, $w13" + - + input: + bytes: [ 0x7a, 0x5e, 0xc9, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "div_s.w $w4, $w25, $w30" + - + input: + bytes: [ 0x7a, 0x74, 0x4f, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "div_s.d $w31, $w9, $w20" + - + input: + bytes: [ 0x7a, 0x8a, 0xe9, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "div_u.b $w6, $w29, $w10" + - + input: + bytes: [ 0x7a, 0xae, 0xae, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "div_u.h $w24, $w21, $w14" + - + input: + bytes: [ 0x7a, 0xd9, 0x77, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "div_u.w $w29, $w14, $w25" + - + input: + bytes: [ 0x7a, 0xf5, 0x0f, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "div_u.d $w31, $w1, $w21" + - + input: + bytes: [ 0x78, 0x39, 0xb5, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dotp_s.h $w23, $w22, $w25" + - + input: + bytes: [ 0x78, 0x45, 0x75, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dotp_s.w $w20, $w14, $w5" + - + input: + bytes: [ 0x78, 0x76, 0x14, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dotp_s.d $w17, $w2, $w22" + - + input: + bytes: [ 0x78, 0xa6, 0x13, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dotp_u.h $w13, $w2, $w6" + - + input: + bytes: [ 0x78, 0xd5, 0xb3, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dotp_u.w $w15, $w22, $w21" + - + input: + bytes: [ 0x78, 0xfa, 0x81, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dotp_u.d $w4, $w16, $w26" + - + input: + bytes: [ 0x79, 0x36, 0xe0, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dpadd_s.h $w1, $w28, $w22" + - + input: + bytes: [ 0x79, 0x4c, 0x0a, 0x93 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dpadd_s.w $w10, $w1, $w12" + - + input: + bytes: [ 0x79, 0x7b, 0xa8, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dpadd_s.d $w3, $w21, $w27" + - + input: + bytes: [ 0x79, 0xb4, 0x2c, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dpadd_u.h $w17, $w5, $w20" + - + input: + bytes: [ 0x79, 0xd0, 0x46, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dpadd_u.w $w24, $w8, $w16" + - + input: + bytes: [ 0x79, 0xf0, 0xeb, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dpadd_u.d $w15, $w29, $w16" + - + input: + bytes: [ 0x7a, 0x2c, 0x59, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dpsub_s.h $w4, $w11, $w12" + - + input: + bytes: [ 0x7a, 0x46, 0x39, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dpsub_s.w $w4, $w7, $w6" + - + input: + bytes: [ 0x7a, 0x7c, 0x67, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dpsub_s.d $w31, $w12, $w28" + - + input: + bytes: [ 0x7a, 0xb1, 0xc9, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dpsub_u.h $w4, $w25, $w17" + - + input: + bytes: [ 0x7a, 0xd0, 0xcc, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dpsub_u.w $w19, $w25, $w16" + - + input: + bytes: [ 0x7a, 0xfa, 0x51, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dpsub_u.d $w7, $w10, $w26" + - + input: + bytes: [ 0x7a, 0x22, 0xc7, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "hadd_s.h $w28, $w24, $w2" + - + input: + bytes: [ 0x7a, 0x4b, 0x8e, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "hadd_s.w $w24, $w17, $w11" + - + input: + bytes: [ 0x7a, 0x74, 0x7c, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "hadd_s.d $w17, $w15, $w20" + - + input: + bytes: [ 0x7a, 0xb1, 0xeb, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "hadd_u.h $w12, $w29, $w17" + - + input: + bytes: [ 0x7a, 0xc6, 0x2a, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "hadd_u.w $w9, $w5, $w6" + - + input: + bytes: [ 0x7a, 0xe6, 0xa0, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "hadd_u.d $w1, $w20, $w6" + - + input: + bytes: [ 0x7b, 0x3d, 0x74, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "hsub_s.h $w16, $w14, $w29" + - + input: + bytes: [ 0x7b, 0x4b, 0x6a, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "hsub_s.w $w9, $w13, $w11" + - + input: + bytes: [ 0x7b, 0x6e, 0x97, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "hsub_s.d $w30, $w18, $w14" + - + input: + bytes: [ 0x7b, 0xae, 0x61, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "hsub_u.h $w7, $w12, $w14" + - + input: + bytes: [ 0x7b, 0xc5, 0x2d, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "hsub_u.w $w21, $w5, $w5" + - + input: + bytes: [ 0x7b, 0xff, 0x62, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "hsub_u.d $w11, $w12, $w31" + - + input: + bytes: [ 0x7b, 0x1e, 0x84, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ilvev.b $w18, $w16, $w30" + - + input: + bytes: [ 0x7b, 0x2d, 0x03, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ilvev.h $w14, $w0, $w13" + - + input: + bytes: [ 0x7b, 0x56, 0xcb, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ilvev.w $w12, $w25, $w22" + - + input: + bytes: [ 0x7b, 0x63, 0xdf, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ilvev.d $w30, $w27, $w3" + - + input: + bytes: [ 0x7a, 0x15, 0x1f, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ilvl.b $w29, $w3, $w21" + - + input: + bytes: [ 0x7a, 0x31, 0x56, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ilvl.h $w27, $w10, $w17" + - + input: + bytes: [ 0x7a, 0x40, 0x09, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ilvl.w $w6, $w1, $w0" + - + input: + bytes: [ 0x7a, 0x78, 0x80, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ilvl.d $w3, $w16, $w24" + - + input: + bytes: [ 0x7b, 0x94, 0x2a, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ilvod.b $w11, $w5, $w20" + - + input: + bytes: [ 0x7b, 0xbf, 0x6c, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ilvod.h $w18, $w13, $w31" + - + input: + bytes: [ 0x7b, 0xd8, 0x87, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ilvod.w $w29, $w16, $w24" + - + input: + bytes: [ 0x7b, 0xfd, 0x65, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ilvod.d $w22, $w12, $w29" + - + input: + bytes: [ 0x7a, 0x86, 0xf1, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ilvr.b $w4, $w30, $w6" + - + input: + bytes: [ 0x7a, 0xbd, 0x9f, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ilvr.h $w28, $w19, $w29" + - + input: + bytes: [ 0x7a, 0xd5, 0xa4, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ilvr.w $w18, $w20, $w21" + - + input: + bytes: [ 0x7a, 0xec, 0xf5, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ilvr.d $w23, $w30, $w12" + - + input: + bytes: [ 0x78, 0x9d, 0xfc, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maddv.b $w17, $w31, $w29" + - + input: + bytes: [ 0x78, 0xa9, 0xc1, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maddv.h $w7, $w24, $w9" + - + input: + bytes: [ 0x78, 0xd4, 0xb5, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maddv.w $w22, $w22, $w20" + - + input: + bytes: [ 0x78, 0xf4, 0xd7, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maddv.d $w30, $w26, $w20" + - + input: + bytes: [ 0x7b, 0x17, 0x5d, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "max_a.b $w23, $w11, $w23" + - + input: + bytes: [ 0x7b, 0x3e, 0x2d, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "max_a.h $w20, $w5, $w30" + - + input: + bytes: [ 0x7b, 0x5e, 0x91, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "max_a.w $w7, $w18, $w30" + - + input: + bytes: [ 0x7b, 0x7f, 0x42, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "max_a.d $w8, $w8, $w31" + - + input: + bytes: [ 0x79, 0x13, 0x0a, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "max_s.b $w10, $w1, $w19" + - + input: + bytes: [ 0x79, 0x31, 0xeb, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "max_s.h $w15, $w29, $w17" + - + input: + bytes: [ 0x79, 0x4e, 0xeb, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "max_s.w $w15, $w29, $w14" + - + input: + bytes: [ 0x79, 0x63, 0xc6, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "max_s.d $w25, $w24, $w3" + - + input: + bytes: [ 0x79, 0x85, 0xc3, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "max_u.b $w12, $w24, $w5" + - + input: + bytes: [ 0x79, 0xa7, 0x31, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "max_u.h $w5, $w6, $w7" + - + input: + bytes: [ 0x79, 0xc7, 0x24, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "max_u.w $w16, $w4, $w7" + - + input: + bytes: [ 0x79, 0xf8, 0x66, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "max_u.d $w26, $w12, $w24" + - + input: + bytes: [ 0x7b, 0x81, 0xd1, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "min_a.b $w4, $w26, $w1" + - + input: + bytes: [ 0x7b, 0xbf, 0x6b, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "min_a.h $w12, $w13, $w31" + - + input: + bytes: [ 0x7b, 0xc0, 0xa7, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "min_a.w $w28, $w20, $w0" + - + input: + bytes: [ 0x7b, 0xf3, 0xa3, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "min_a.d $w12, $w20, $w19" + - + input: + bytes: [ 0x7a, 0x0e, 0x1c, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "min_s.b $w19, $w3, $w14" + - + input: + bytes: [ 0x7a, 0x28, 0xae, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "min_s.h $w27, $w21, $w8" + - + input: + bytes: [ 0x7a, 0x5e, 0x70, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "min_s.w $w0, $w14, $w30" + - + input: + bytes: [ 0x7a, 0x75, 0x41, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "min_s.d $w6, $w8, $w21" + - + input: + bytes: [ 0x7a, 0x88, 0xd5, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "min_u.b $w22, $w26, $w8" + - + input: + bytes: [ 0x7a, 0xac, 0xd9, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "min_u.h $w7, $w27, $w12" + - + input: + bytes: [ 0x7a, 0xce, 0xa2, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "min_u.w $w8, $w20, $w14" + - + input: + bytes: [ 0x7a, 0xef, 0x76, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "min_u.d $w26, $w14, $w15" + - + input: + bytes: [ 0x7b, 0x1a, 0x0c, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mod_s.b $w18, $w1, $w26" + - + input: + bytes: [ 0x7b, 0x3c, 0xf7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mod_s.h $w31, $w30, $w28" + - + input: + bytes: [ 0x7b, 0x4d, 0x30, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mod_s.w $w2, $w6, $w13" + - + input: + bytes: [ 0x7b, 0x76, 0xdd, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mod_s.d $w21, $w27, $w22" + - + input: + bytes: [ 0x7b, 0x8d, 0x3c, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mod_u.b $w16, $w7, $w13" + - + input: + bytes: [ 0x7b, 0xa7, 0x46, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mod_u.h $w24, $w8, $w7" + - + input: + bytes: [ 0x7b, 0xd1, 0x17, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mod_u.w $w30, $w2, $w17" + - + input: + bytes: [ 0x7b, 0xf9, 0x17, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mod_u.d $w31, $w2, $w25" + - + input: + bytes: [ 0x79, 0x0c, 0x2b, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msubv.b $w14, $w5, $w12" + - + input: + bytes: [ 0x79, 0x3e, 0x39, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msubv.h $w6, $w7, $w30" + - + input: + bytes: [ 0x79, 0x55, 0x13, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msubv.w $w13, $w2, $w21" + - + input: + bytes: [ 0x79, 0x7b, 0x74, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msubv.d $w16, $w14, $w27" + - + input: + bytes: [ 0x78, 0x0d, 0x1d, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulv.b $w20, $w3, $w13" + - + input: + bytes: [ 0x78, 0x2e, 0xd6, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulv.h $w27, $w26, $w14" + - + input: + bytes: [ 0x78, 0x43, 0xea, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulv.w $w10, $w29, $w3" + - + input: + bytes: [ 0x78, 0x7d, 0x99, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulv.d $w7, $w19, $w29" + - + input: + bytes: [ 0x79, 0x07, 0xd9, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pckev.b $w5, $w27, $w7" + - + input: + bytes: [ 0x79, 0x3b, 0x20, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pckev.h $w1, $w4, $w27" + - + input: + bytes: [ 0x79, 0x40, 0xa7, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pckev.w $w30, $w20, $w0" + - + input: + bytes: [ 0x79, 0x6f, 0x09, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pckev.d $w6, $w1, $w15" + - + input: + bytes: [ 0x79, 0x9e, 0xe4, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pckod.b $w18, $w28, $w30" + - + input: + bytes: [ 0x79, 0xa8, 0x2e, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pckod.h $w26, $w5, $w8" + - + input: + bytes: [ 0x79, 0xc2, 0x22, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pckod.w $w9, $w4, $w2" + - + input: + bytes: [ 0x79, 0xf4, 0xb7, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pckod.d $w30, $w22, $w20" + - + input: + bytes: [ 0x78, 0x0c, 0xb9, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sld.b $w5, $w23[$t4]" + - + input: + bytes: [ 0x78, 0x23, 0xb8, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sld.h $w1, $w23[$v1]" + - + input: + bytes: [ 0x78, 0x49, 0x45, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sld.w $w20, $w8[$t1]" + - + input: + bytes: [ 0x78, 0x7e, 0xb9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sld.d $w7, $w23[$fp]" + - + input: + bytes: [ 0x78, 0x11, 0x00, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sll.b $w3, $w0, $w17" + - + input: + bytes: [ 0x78, 0x23, 0xdc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sll.h $w17, $w27, $w3" + - + input: + bytes: [ 0x78, 0x46, 0x3c, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sll.w $w16, $w7, $w6" + - + input: + bytes: [ 0x78, 0x7a, 0x02, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sll.d $w9, $w0, $w26" + - + input: + bytes: [ 0x78, 0x81, 0x0f, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "splat.b $w28, $w1[$at]" + - + input: + bytes: [ 0x78, 0xab, 0x58, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "splat.h $w2, $w11[$t3]" + - + input: + bytes: [ 0x78, 0xcb, 0x05, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "splat.w $w22, $w0[$t3]" + - + input: + bytes: [ 0x78, 0xe2, 0x00, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "splat.d $w0, $w0[$v0]" + - + input: + bytes: [ 0x78, 0x91, 0x27, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sra.b $w28, $w4, $w17" + - + input: + bytes: [ 0x78, 0xa3, 0x4b, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sra.h $w13, $w9, $w3" + - + input: + bytes: [ 0x78, 0xd3, 0xae, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sra.w $w27, $w21, $w19" + - + input: + bytes: [ 0x78, 0xf7, 0x47, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sra.d $w30, $w8, $w23" + - + input: + bytes: [ 0x78, 0x92, 0x94, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srar.b $w19, $w18, $w18" + - + input: + bytes: [ 0x78, 0xa8, 0xb9, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srar.h $w7, $w23, $w8" + - + input: + bytes: [ 0x78, 0xc2, 0x60, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srar.w $w1, $w12, $w2" + - + input: + bytes: [ 0x78, 0xee, 0x3d, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srar.d $w21, $w7, $w14" + - + input: + bytes: [ 0x79, 0x13, 0x1b, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srl.b $w12, $w3, $w19" + - + input: + bytes: [ 0x79, 0x34, 0xfd, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srl.h $w23, $w31, $w20" + - + input: + bytes: [ 0x79, 0x4b, 0xdc, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srl.w $w18, $w27, $w11" + - + input: + bytes: [ 0x79, 0x7a, 0x60, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srl.d $w3, $w12, $w26" + - + input: + bytes: [ 0x79, 0x0b, 0xab, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlr.b $w15, $w21, $w11" + - + input: + bytes: [ 0x79, 0x33, 0x6d, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlr.h $w21, $w13, $w19" + - + input: + bytes: [ 0x79, 0x43, 0xf1, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlr.w $w6, $w30, $w3" + - + input: + bytes: [ 0x79, 0x6e, 0x10, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlr.d $w1, $w2, $w14" + - + input: + bytes: [ 0x78, 0x01, 0x7e, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subs_s.b $w25, $w15, $w1" + - + input: + bytes: [ 0x78, 0x36, 0xcf, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subs_s.h $w28, $w25, $w22" + - + input: + bytes: [ 0x78, 0x55, 0x62, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subs_s.w $w10, $w12, $w21" + - + input: + bytes: [ 0x78, 0x72, 0xa1, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subs_s.d $w4, $w20, $w18" + - + input: + bytes: [ 0x78, 0x99, 0x35, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subs_u.b $w21, $w6, $w25" + - + input: + bytes: [ 0x78, 0xa7, 0x50, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subs_u.h $w3, $w10, $w7" + - + input: + bytes: [ 0x78, 0xca, 0x7a, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subs_u.w $w9, $w15, $w10" + - + input: + bytes: [ 0x78, 0xea, 0x99, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subs_u.d $w7, $w19, $w10" + - + input: + bytes: [ 0x79, 0x0c, 0x39, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subsus_u.b $w6, $w7, $w12" + - + input: + bytes: [ 0x79, 0x33, 0xe9, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subsus_u.h $w6, $w29, $w19" + - + input: + bytes: [ 0x79, 0x47, 0x79, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subsus_u.w $w7, $w15, $w7" + - + input: + bytes: [ 0x79, 0x6f, 0x1a, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subsus_u.d $w9, $w3, $w15" + - + input: + bytes: [ 0x79, 0x9f, 0x1d, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subsuu_s.b $w22, $w3, $w31" + - + input: + bytes: [ 0x79, 0xb6, 0xbc, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subsuu_s.h $w19, $w23, $w22" + - + input: + bytes: [ 0x79, 0xcd, 0x52, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subsuu_s.w $w9, $w10, $w13" + - + input: + bytes: [ 0x79, 0xe0, 0x31, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subsuu_s.d $w5, $w6, $w0" + - + input: + bytes: [ 0x78, 0x93, 0x69, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subv.b $w6, $w13, $w19" + - + input: + bytes: [ 0x78, 0xac, 0xc9, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subv.h $w4, $w25, $w12" + - + input: + bytes: [ 0x78, 0xcb, 0xde, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subv.w $w27, $w27, $w11" + - + input: + bytes: [ 0x78, 0xea, 0xc2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subv.d $w9, $w24, $w10" + - + input: + bytes: [ 0x78, 0x05, 0x80, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vshf.b $w3, $w16, $w5" + - + input: + bytes: [ 0x78, 0x28, 0x9d, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vshf.h $w20, $w19, $w8" + - + input: + bytes: [ 0x78, 0x59, 0xf4, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vshf.w $w16, $w30, $w25" + - + input: + bytes: [ 0x78, 0x6f, 0x5c, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vshf.d $w19, $w11, $w15" diff --git a/tests/MC/Mips/test_3rf.s.yaml b/tests/MC/Mips/test_3rf.s.yaml new file mode 100644 index 0000000000..31464d86a2 --- /dev/null +++ b/tests/MC/Mips/test_3rf.s.yaml @@ -0,0 +1,739 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x1c, 0x9f, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fadd.w $w28, $w19, $w28" + - + input: + bytes: [ 0x78, 0x3d, 0x13, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fadd.d $w13, $w2, $w29" + - + input: + bytes: [ 0x78, 0x19, 0x5b, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcaf.w $w14, $w11, $w25" + - + input: + bytes: [ 0x78, 0x33, 0x08, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcaf.d $w1, $w1, $w19" + - + input: + bytes: [ 0x78, 0x90, 0xb8, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fceq.w $w1, $w23, $w16" + - + input: + bytes: [ 0x78, 0xb0, 0x40, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fceq.d $w0, $w8, $w16" + - + input: + bytes: [ 0x79, 0x98, 0x4c, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcle.w $w16, $w9, $w24" + - + input: + bytes: [ 0x79, 0xa1, 0x76, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcle.d $w27, $w14, $w1" + - + input: + bytes: [ 0x79, 0x08, 0x47, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fclt.w $w28, $w8, $w8" + - + input: + bytes: [ 0x79, 0x2b, 0xcf, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fclt.d $w30, $w25, $w11" + - + input: + bytes: [ 0x78, 0xd7, 0x90, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcne.w $w2, $w18, $w23" + - + input: + bytes: [ 0x78, 0xef, 0xa3, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcne.d $w14, $w20, $w15" + - + input: + bytes: [ 0x78, 0x59, 0x92, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcor.w $w10, $w18, $w25" + - + input: + bytes: [ 0x78, 0x6b, 0xcc, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcor.d $w17, $w25, $w11" + - + input: + bytes: [ 0x78, 0xd5, 0x13, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcueq.w $w14, $w2, $w21" + - + input: + bytes: [ 0x78, 0xe7, 0x1f, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcueq.d $w29, $w3, $w7" + - + input: + bytes: [ 0x79, 0xc3, 0x2c, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcule.w $w17, $w5, $w3" + - + input: + bytes: [ 0x79, 0xfe, 0x0f, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcule.d $w31, $w1, $w30" + - + input: + bytes: [ 0x79, 0x49, 0xc9, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcult.w $w6, $w25, $w9" + - + input: + bytes: [ 0x79, 0x71, 0x46, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcult.d $w27, $w8, $w17" + - + input: + bytes: [ 0x78, 0x48, 0xa1, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcun.w $w4, $w20, $w8" + - + input: + bytes: [ 0x78, 0x63, 0x5f, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcun.d $w29, $w11, $w3" + - + input: + bytes: [ 0x78, 0x93, 0x93, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcune.w $w13, $w18, $w19" + - + input: + bytes: [ 0x78, 0xb5, 0xd4, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcune.d $w16, $w26, $w21" + - + input: + bytes: [ 0x78, 0xc2, 0xc3, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fdiv.w $w13, $w24, $w2" + - + input: + bytes: [ 0x78, 0xf9, 0x24, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fdiv.d $w19, $w4, $w25" + - + input: + bytes: [ 0x7a, 0x10, 0x02, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fexdo.h $w8, $w0, $w16" + - + input: + bytes: [ 0x7a, 0x3b, 0x68, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fexdo.w $w0, $w13, $w27" + - + input: + bytes: [ 0x79, 0xc3, 0x04, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fexp2.w $w17, $w0, $w3" + - + input: + bytes: [ 0x79, 0xea, 0x05, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fexp2.d $w22, $w0, $w10" + - + input: + bytes: [ 0x79, 0x17, 0x37, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmadd.w $w29, $w6, $w23" + - + input: + bytes: [ 0x79, 0x35, 0xe2, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmadd.d $w11, $w28, $w21" + - + input: + bytes: [ 0x7b, 0x8d, 0xb8, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmax.w $w0, $w23, $w13" + - + input: + bytes: [ 0x7b, 0xa8, 0x96, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmax.d $w26, $w18, $w8" + - + input: + bytes: [ 0x7b, 0xca, 0x82, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmax_a.w $w10, $w16, $w10" + - + input: + bytes: [ 0x7b, 0xf6, 0x4f, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmax_a.d $w30, $w9, $w22" + - + input: + bytes: [ 0x7b, 0x1e, 0x0e, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmin.w $w24, $w1, $w30" + - + input: + bytes: [ 0x7b, 0x2a, 0xde, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmin.d $w27, $w27, $w10" + - + input: + bytes: [ 0x7b, 0x54, 0xea, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmin_a.w $w10, $w29, $w20" + - + input: + bytes: [ 0x7b, 0x78, 0xf3, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmin_a.d $w13, $w30, $w24" + - + input: + bytes: [ 0x79, 0x40, 0xcc, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmsub.w $w17, $w25, $w0" + - + input: + bytes: [ 0x79, 0x70, 0x92, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmsub.d $w8, $w18, $w16" + - + input: + bytes: [ 0x78, 0x8f, 0x78, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmul.w $w3, $w15, $w15" + - + input: + bytes: [ 0x78, 0xaa, 0xf2, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmul.d $w9, $w30, $w10" + - + input: + bytes: [ 0x7a, 0x0a, 0x2e, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsaf.w $w25, $w5, $w10" + - + input: + bytes: [ 0x7a, 0x3d, 0x1e, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsaf.d $w25, $w3, $w29" + - + input: + bytes: [ 0x7a, 0x8d, 0x8a, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fseq.w $w11, $w17, $w13" + - + input: + bytes: [ 0x7a, 0xbf, 0x07, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fseq.d $w29, $w0, $w31" + - + input: + bytes: [ 0x7b, 0x9f, 0xff, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsle.w $w30, $w31, $w31" + - + input: + bytes: [ 0x7b, 0xb8, 0xbc, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsle.d $w18, $w23, $w24" + - + input: + bytes: [ 0x7b, 0x06, 0x2b, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fslt.w $w12, $w5, $w6" + - + input: + bytes: [ 0x7b, 0x35, 0xd4, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fslt.d $w16, $w26, $w21" + - + input: + bytes: [ 0x7a, 0xcc, 0x0f, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsne.w $w30, $w1, $w12" + - + input: + bytes: [ 0x7a, 0xf7, 0x6b, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsne.d $w14, $w13, $w23" + - + input: + bytes: [ 0x7a, 0x5b, 0x6e, 0xdc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsor.w $w27, $w13, $w27" + - + input: + bytes: [ 0x7a, 0x6b, 0xc3, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsor.d $w12, $w24, $w11" + - + input: + bytes: [ 0x78, 0x41, 0xd7, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsub.w $w31, $w26, $w1" + - + input: + bytes: [ 0x78, 0x7b, 0x8c, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsub.d $w19, $w17, $w27" + - + input: + bytes: [ 0x7a, 0xd9, 0xc4, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsueq.w $w16, $w24, $w25" + - + input: + bytes: [ 0x7a, 0xee, 0x74, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsueq.d $w18, $w14, $w14" + - + input: + bytes: [ 0x7b, 0xcd, 0xf5, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsule.w $w23, $w30, $w13" + - + input: + bytes: [ 0x7b, 0xfa, 0x58, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsule.d $w2, $w11, $w26" + - + input: + bytes: [ 0x7b, 0x56, 0xd2, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsult.w $w11, $w26, $w22" + - + input: + bytes: [ 0x7b, 0x7e, 0xb9, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsult.d $w6, $w23, $w30" + - + input: + bytes: [ 0x7a, 0x5c, 0x90, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsun.w $w3, $w18, $w28" + - + input: + bytes: [ 0x7a, 0x73, 0x5c, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsun.d $w18, $w11, $w19" + - + input: + bytes: [ 0x7a, 0x82, 0xfc, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsune.w $w16, $w31, $w2" + - + input: + bytes: [ 0x7a, 0xb1, 0xd0, 0xdc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsune.d $w3, $w26, $w17" + - + input: + bytes: [ 0x7a, 0x98, 0x24, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ftq.h $w16, $w4, $w24" + - + input: + bytes: [ 0x7a, 0xb9, 0x29, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ftq.w $w5, $w5, $w25" + - + input: + bytes: [ 0x79, 0x4a, 0xa4, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madd_q.h $w16, $w20, $w10" + - + input: + bytes: [ 0x79, 0x69, 0x17, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madd_q.w $w28, $w2, $w9" + - + input: + bytes: [ 0x7b, 0x49, 0x92, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maddr_q.h $w8, $w18, $w9" + - + input: + bytes: [ 0x7b, 0x70, 0x67, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maddr_q.w $w29, $w12, $w16" + - + input: + bytes: [ 0x79, 0x8a, 0xd6, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msub_q.h $w24, $w26, $w10" + - + input: + bytes: [ 0x79, 0xbc, 0xf3, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msub_q.w $w13, $w30, $w28" + - + input: + bytes: [ 0x7b, 0x8b, 0xab, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msubr_q.h $w12, $w21, $w11" + - + input: + bytes: [ 0x7b, 0xb4, 0x70, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msubr_q.w $w1, $w14, $w20" + - + input: + bytes: [ 0x79, 0x1e, 0x81, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mul_q.h $w6, $w16, $w30" + - + input: + bytes: [ 0x79, 0x24, 0x0c, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mul_q.w $w16, $w1, $w4" + - + input: + bytes: [ 0x7b, 0x13, 0xa1, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulr_q.h $w6, $w20, $w19" + - + input: + bytes: [ 0x7b, 0x34, 0x0e, 0xdc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulr_q.w $w27, $w1, $w20" diff --git a/tests/MC/Mips/test_bit.s.yaml b/tests/MC/Mips/test_bit.s.yaml new file mode 100644 index 0000000000..e650c7bdb7 --- /dev/null +++ b/tests/MC/Mips/test_bit.s.yaml @@ -0,0 +1,433 @@ +test_cases: + - + input: + bytes: [ 0x79, 0xf2, 0xf5, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bclri.b $w21, $w30, 2" + - + input: + bytes: [ 0x79, 0xe0, 0xae, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bclri.h $w24, $w21, 0" + - + input: + bytes: [ 0x79, 0xc3, 0xf5, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bclri.w $w23, $w30, 3" + - + input: + bytes: [ 0x79, 0x80, 0x5a, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bclri.d $w9, $w11, 0" + - + input: + bytes: [ 0x7b, 0x71, 0x66, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binsli.b $w25, $w12, 1" + - + input: + bytes: [ 0x7b, 0x60, 0xb5, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binsli.h $w21, $w22, 0" + - + input: + bytes: [ 0x7b, 0x40, 0x25, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binsli.w $w22, $w4, 0" + - + input: + bytes: [ 0x7b, 0x06, 0x11, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binsli.d $w6, $w2, 6" + - + input: + bytes: [ 0x7b, 0xf0, 0x9b, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binsri.b $w15, $w19, 0" + - + input: + bytes: [ 0x7b, 0xe1, 0xf2, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binsri.h $w8, $w30, 1" + - + input: + bytes: [ 0x7b, 0xc5, 0x98, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binsri.w $w2, $w19, 5" + - + input: + bytes: [ 0x7b, 0x81, 0xa4, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binsri.d $w18, $w20, 1" + - + input: + bytes: [ 0x7a, 0xf0, 0x9e, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bnegi.b $w24, $w19, 0" + - + input: + bytes: [ 0x7a, 0xe3, 0x5f, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bnegi.h $w28, $w11, 3" + - + input: + bytes: [ 0x7a, 0xc5, 0xd8, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bnegi.w $w1, $w27, 5" + - + input: + bytes: [ 0x7a, 0x81, 0xa9, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bnegi.d $w4, $w21, 1" + - + input: + bytes: [ 0x7a, 0x70, 0x44, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bseti.b $w18, $w8, 0" + - + input: + bytes: [ 0x7a, 0x62, 0x76, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bseti.h $w24, $w14, 2" + - + input: + bytes: [ 0x7a, 0x44, 0x92, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bseti.w $w9, $w18, 4" + - + input: + bytes: [ 0x7a, 0x01, 0x79, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bseti.d $w7, $w15, 1" + - + input: + bytes: [ 0x78, 0x72, 0xff, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sat_s.b $w31, $w31, 2" + - + input: + bytes: [ 0x78, 0x60, 0x9c, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sat_s.h $w19, $w19, 0" + - + input: + bytes: [ 0x78, 0x40, 0xec, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sat_s.w $w19, $w29, 0" + - + input: + bytes: [ 0x78, 0x00, 0xb2, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sat_s.d $w11, $w22, 0" + - + input: + bytes: [ 0x78, 0xf3, 0x68, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sat_u.b $w1, $w13, 3" + - + input: + bytes: [ 0x78, 0xe4, 0xc7, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sat_u.h $w30, $w24, 4" + - + input: + bytes: [ 0x78, 0xc0, 0x6f, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sat_u.w $w31, $w13, 0" + - + input: + bytes: [ 0x78, 0x85, 0x87, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sat_u.d $w29, $w16, 5" + - + input: + bytes: [ 0x78, 0x71, 0x55, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slli.b $w23, $w10, 1" + - + input: + bytes: [ 0x78, 0x61, 0x92, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slli.h $w9, $w18, 1" + - + input: + bytes: [ 0x78, 0x44, 0xea, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slli.w $w11, $w29, 4" + - + input: + bytes: [ 0x78, 0x01, 0xa6, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slli.d $w25, $w20, 1" + - + input: + bytes: [ 0x78, 0xf1, 0xee, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srai.b $w24, $w29, 1" + - + input: + bytes: [ 0x78, 0xe0, 0x30, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srai.h $w1, $w6, 0" + - + input: + bytes: [ 0x78, 0xc1, 0xd1, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srai.w $w7, $w26, 1" + - + input: + bytes: [ 0x78, 0x83, 0xcd, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srai.d $w20, $w25, 3" + - + input: + bytes: [ 0x79, 0x70, 0xc9, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srari.b $w5, $w25, 0" + - + input: + bytes: [ 0x79, 0x64, 0x31, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srari.h $w7, $w6, 4" + - + input: + bytes: [ 0x79, 0x45, 0x5c, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srari.w $w17, $w11, 5" + - + input: + bytes: [ 0x79, 0x05, 0xcd, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srari.d $w21, $w25, 5" + - + input: + bytes: [ 0x79, 0x72, 0x00, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srli.b $w2, $w0, 2" + - + input: + bytes: [ 0x79, 0x62, 0xff, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srli.h $w31, $w31, 2" + - + input: + bytes: [ 0x79, 0x44, 0x49, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srli.w $w5, $w9, 4" + - + input: + bytes: [ 0x79, 0x05, 0xd6, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srli.d $w27, $w26, 5" + - + input: + bytes: [ 0x79, 0xf0, 0x1c, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlri.b $w18, $w3, 0" + - + input: + bytes: [ 0x79, 0xe3, 0x10, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlri.h $w1, $w2, 3" + - + input: + bytes: [ 0x79, 0xc2, 0xb2, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlri.w $w11, $w22, 2" + - + input: + bytes: [ 0x79, 0x86, 0x56, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlri.d $w24, $w10, 6" diff --git a/tests/MC/Mips/test_ctrlregs.s.yaml b/tests/MC/Mips/test_ctrlregs.s.yaml new file mode 100644 index 0000000000..4f051220b4 --- /dev/null +++ b/tests/MC/Mips/test_ctrlregs.s.yaml @@ -0,0 +1,289 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x7e, 0x00, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfcmsa $at, $0" + - + input: + bytes: [ 0x78, 0x7e, 0x00, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfcmsa $at, $0" + - + input: + bytes: [ 0x78, 0x7e, 0x08, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfcmsa $v0, $1" + - + input: + bytes: [ 0x78, 0x7e, 0x08, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfcmsa $v0, $1" + - + input: + bytes: [ 0x78, 0x7e, 0x10, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfcmsa $v1, $2" + - + input: + bytes: [ 0x78, 0x7e, 0x10, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfcmsa $v1, $2" + - + input: + bytes: [ 0x78, 0x7e, 0x19, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfcmsa $a0, $3" + - + input: + bytes: [ 0x78, 0x7e, 0x19, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfcmsa $a0, $3" + - + input: + bytes: [ 0x78, 0x7e, 0x21, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfcmsa $a1, $4" + - + input: + bytes: [ 0x78, 0x7e, 0x21, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfcmsa $a1, $4" + - + input: + bytes: [ 0x78, 0x7e, 0x29, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfcmsa $a2, $5" + - + input: + bytes: [ 0x78, 0x7e, 0x29, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfcmsa $a2, $5" + - + input: + bytes: [ 0x78, 0x7e, 0x31, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfcmsa $a3, $6" + - + input: + bytes: [ 0x78, 0x7e, 0x31, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfcmsa $a3, $6" + - + input: + bytes: [ 0x78, 0x7e, 0x3a, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfcmsa $t0, $7" + - + input: + bytes: [ 0x78, 0x7e, 0x3a, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfcmsa $t0, $7" + - + input: + bytes: [ 0x78, 0x3e, 0x08, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ctcmsa $0, $at" + - + input: + bytes: [ 0x78, 0x3e, 0x08, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ctcmsa $0, $at" + - + input: + bytes: [ 0x78, 0x3e, 0x10, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ctcmsa $1, $v0" + - + input: + bytes: [ 0x78, 0x3e, 0x10, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ctcmsa $1, $v0" + - + input: + bytes: [ 0x78, 0x3e, 0x18, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ctcmsa $2, $v1" + - + input: + bytes: [ 0x78, 0x3e, 0x18, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ctcmsa $2, $v1" + - + input: + bytes: [ 0x78, 0x3e, 0x20, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ctcmsa $3, $a0" + - + input: + bytes: [ 0x78, 0x3e, 0x20, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ctcmsa $3, $a0" + - + input: + bytes: [ 0x78, 0x3e, 0x29, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ctcmsa $4, $a1" + - + input: + bytes: [ 0x78, 0x3e, 0x29, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ctcmsa $4, $a1" + - + input: + bytes: [ 0x78, 0x3e, 0x31, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ctcmsa $5, $a2" + - + input: + bytes: [ 0x78, 0x3e, 0x31, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ctcmsa $5, $a2" + - + input: + bytes: [ 0x78, 0x3e, 0x39, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ctcmsa $6, $a3" + - + input: + bytes: [ 0x78, 0x3e, 0x39, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ctcmsa $6, $a3" + - + input: + bytes: [ 0x78, 0x3e, 0x41, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ctcmsa $7, $t0" + - + input: + bytes: [ 0x78, 0x3e, 0x41, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ctcmsa $7, $t0" diff --git a/tests/MC/Mips/test_elm.s.yaml b/tests/MC/Mips/test_elm.s.yaml new file mode 100644 index 0000000000..9ad7c3d497 --- /dev/null +++ b/tests/MC/Mips/test_elm.s.yaml @@ -0,0 +1,136 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x82, 0x43, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "copy_s.b $t5, $w8[2]" + - + input: + bytes: [ 0x78, 0xa0, 0xc8, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "copy_s.h $at, $w25[0]" + - + input: + bytes: [ 0x78, 0xb1, 0x2d, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "copy_s.w $s6, $w5[1]" + - + input: + bytes: [ 0x78, 0xc4, 0xa5, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "copy_u.b $s6, $w20[4]" + - + input: + bytes: [ 0x78, 0xe0, 0x25, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "copy_u.h $s4, $w4[0]" + - + input: + bytes: [ 0x78, 0xf2, 0x6f, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "copy_u.w $fp, $w13[2]" + - + input: + bytes: [ 0x78, 0x04, 0xe8, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldi.b $w0, $w29[4]" + - + input: + bytes: [ 0x78, 0x20, 0x8a, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldi.h $w8, $w17[0]" + - + input: + bytes: [ 0x78, 0x32, 0xdd, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldi.w $w20, $w27[2]" + - + input: + bytes: [ 0x78, 0x38, 0x61, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldi.d $w4, $w12[0]" + - + input: + bytes: [ 0x78, 0x42, 0x1e, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "splati.b $w25, $w3[2]" + - + input: + bytes: [ 0x78, 0x61, 0xe6, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "splati.h $w24, $w28[1]" + - + input: + bytes: [ 0x78, 0x70, 0x93, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "splati.w $w13, $w18[0]" + - + input: + bytes: [ 0x78, 0x78, 0x0f, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "splati.d $w28, $w1[0]" + - + input: + bytes: [ 0x78, 0xbe, 0xc5, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "move.v $w23, $w24" diff --git a/tests/MC/Mips/test_elm_insert.s.yaml b/tests/MC/Mips/test_elm_insert.s.yaml new file mode 100644 index 0000000000..71820d17ad --- /dev/null +++ b/tests/MC/Mips/test_elm_insert.s.yaml @@ -0,0 +1,28 @@ +test_cases: + - + input: + bytes: [ 0x79, 0x03, 0xed, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "insert.b $w23[3], $sp" + - + input: + bytes: [ 0x79, 0x22, 0x2d, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "insert.h $w20[2], $a1" + - + input: + bytes: [ 0x79, 0x32, 0x7a, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "insert.w $w8[2], $t7" diff --git a/tests/MC/Mips/test_elm_insve.s.yaml b/tests/MC/Mips/test_elm_insve.s.yaml new file mode 100644 index 0000000000..6943ea8698 --- /dev/null +++ b/tests/MC/Mips/test_elm_insve.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x79, 0x43, 0x4e, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "insve.b $w25[3], $w9[0]" + - + input: + bytes: [ 0x79, 0x62, 0x16, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "insve.h $w24[2], $w2[0]" + - + input: + bytes: [ 0x79, 0x72, 0x68, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "insve.w $w0[2], $w13[0]" + - + input: + bytes: [ 0x79, 0x78, 0x90, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "insve.d $w3[0], $w18[0]" diff --git a/tests/MC/Mips/test_i10.s.yaml b/tests/MC/Mips/test_i10.s.yaml new file mode 100644 index 0000000000..a49decba23 --- /dev/null +++ b/tests/MC/Mips/test_i10.s.yaml @@ -0,0 +1,28 @@ +test_cases: + - + input: + bytes: [ 0x7b, 0x06, 0x32, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldi.b $w8, 198" + - + input: + bytes: [ 0x7b, 0x29, 0xcd, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldi.h $w20, 313" + - + input: + bytes: [ 0x7b, 0x4f, 0x66, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldi.w $w24, 492" diff --git a/tests/MC/Mips/test_i5.s.yaml b/tests/MC/Mips/test_i5.s.yaml new file mode 100644 index 0000000000..bcc32a6379 --- /dev/null +++ b/tests/MC/Mips/test_i5.s.yaml @@ -0,0 +1,289 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x1e, 0xf8, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addvi.b $w3, $w31, 30" + - + input: + bytes: [ 0x78, 0x3a, 0x6e, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addvi.h $w24, $w13, 26" + - + input: + bytes: [ 0x78, 0x5a, 0xa6, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addvi.w $w26, $w20, 26" + - + input: + bytes: [ 0x78, 0x75, 0x0c, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addvi.d $w16, $w1, 21" + - + input: + bytes: [ 0x78, 0x22, 0x7f, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ceqi.h $w31, $w15, 2" + - + input: + bytes: [ 0x78, 0x67, 0xb6, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ceqi.d $w24, $w22, 7" + - + input: + bytes: [ 0x7a, 0x01, 0x83, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clei_s.b $w12, $w16, 1" + - + input: + bytes: [ 0x7a, 0x83, 0x8d, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clei_u.b $w21, $w17, 3" + - + input: + bytes: [ 0x7a, 0xb1, 0x3f, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clei_u.h $w29, $w7, 17" + - + input: + bytes: [ 0x7a, 0xc2, 0x08, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clei_u.w $w1, $w1, 2" + - + input: + bytes: [ 0x7a, 0xfd, 0xde, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clei_u.d $w27, $w27, 29" + - + input: + bytes: [ 0x79, 0x4b, 0x63, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clti_s.w $w12, $w12, 11" + - + input: + bytes: [ 0x79, 0x9d, 0x4b, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clti_u.b $w14, $w9, 29" + - + input: + bytes: [ 0x79, 0xb9, 0xce, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clti_u.h $w24, $w25, 25" + - + input: + bytes: [ 0x79, 0xd6, 0x08, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clti_u.w $w1, $w1, 22" + - + input: + bytes: [ 0x79, 0xe1, 0xcd, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clti_u.d $w21, $w25, 1" + - + input: + bytes: [ 0x79, 0x01, 0xad, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maxi_s.b $w22, $w21, 1" + - + input: + bytes: [ 0x79, 0x8c, 0x05, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maxi_u.b $w20, $w0, 12" + - + input: + bytes: [ 0x79, 0xa3, 0x70, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maxi_u.h $w1, $w14, 3" + - + input: + bytes: [ 0x79, 0xcb, 0xb6, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maxi_u.w $w27, $w22, 11" + - + input: + bytes: [ 0x79, 0xe4, 0x36, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maxi_u.d $w26, $w6, 4" + - + input: + bytes: [ 0x7a, 0x01, 0x09, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mini_s.b $w4, $w1, 1" + - + input: + bytes: [ 0x7a, 0x49, 0x5f, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mini_s.w $w28, $w11, 9" + - + input: + bytes: [ 0x7a, 0x6a, 0x52, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mini_s.d $w11, $w10, 10" + - + input: + bytes: [ 0x7a, 0x9b, 0xbc, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mini_u.b $w18, $w23, 27" + - + input: + bytes: [ 0x7a, 0xb2, 0xd1, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mini_u.h $w7, $w26, 18" + - + input: + bytes: [ 0x7a, 0xda, 0x62, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mini_u.w $w11, $w12, 26" + - + input: + bytes: [ 0x7a, 0xe2, 0x7a, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mini_u.d $w11, $w15, 2" + - + input: + bytes: [ 0x78, 0x93, 0xa6, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subvi.b $w24, $w20, 19" + - + input: + bytes: [ 0x78, 0xa4, 0x9a, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subvi.h $w11, $w19, 4" + - + input: + bytes: [ 0x78, 0xcb, 0x53, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subvi.w $w12, $w10, 11" + - + input: + bytes: [ 0x78, 0xe7, 0x84, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subvi.d $w19, $w16, 7" diff --git a/tests/MC/Mips/test_i8.s.yaml b/tests/MC/Mips/test_i8.s.yaml new file mode 100644 index 0000000000..7b54352176 --- /dev/null +++ b/tests/MC/Mips/test_i8.s.yaml @@ -0,0 +1,91 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x30, 0xe8, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "andi.b $w2, $w29, 48" + - + input: + bytes: [ 0x78, 0x7e, 0xb1, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bmnzi.b $w6, $w22, 126" + - + input: + bytes: [ 0x79, 0x58, 0x0e, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bmzi.b $w27, $w1, 88" + - + input: + bytes: [ 0x7a, 0xbd, 0x1f, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bseli.b $w29, $w3, 189" + - + input: + bytes: [ 0x7a, 0x38, 0x88, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nori.b $w1, $w17, 56" + - + input: + bytes: [ 0x79, 0x87, 0xa6, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ori.b $w26, $w20, 135" + - + input: + bytes: [ 0x78, 0x69, 0xf4, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shf.b $w19, $w30, 105" + - + input: + bytes: [ 0x79, 0x4c, 0x44, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shf.h $w17, $w8, 76" + - + input: + bytes: [ 0x7a, 0x5d, 0x1b, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shf.w $w14, $w3, 93" + - + input: + bytes: [ 0x7b, 0x14, 0x54, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xori.b $w16, $w10, 20" diff --git a/tests/MC/Mips/test_lsa.s.yaml b/tests/MC/Mips/test_lsa.s.yaml new file mode 100644 index 0000000000..002c4dc2d9 --- /dev/null +++ b/tests/MC/Mips/test_lsa.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lsa $t0, $t1, $t2, 1" + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lsa $t0, $t1, $t2, 2" + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lsa $t0, $t1, $t2, 3" + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0xc5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lsa $t0, $t1, $t2, 4" diff --git a/tests/MC/Mips/test_mi10.s.yaml b/tests/MC/Mips/test_mi10.s.yaml new file mode 100644 index 0000000000..83aeb82f7f --- /dev/null +++ b/tests/MC/Mips/test_mi10.s.yaml @@ -0,0 +1,208 @@ +test_cases: + - + input: + bytes: [ 0x7a, 0x00, 0x08, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.b $w0, -512($at)" + - + input: + bytes: [ 0x78, 0x00, 0x10, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.b $w1, ($v0)" + - + input: + bytes: [ 0x79, 0xff, 0x18, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.b $w2, 511($v1)" + - + input: + bytes: [ 0x7a, 0x00, 0x20, 0xe1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.h $w3, -1024($a0)" + - + input: + bytes: [ 0x7b, 0x00, 0x29, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.h $w4, -512($a1)" + - + input: + bytes: [ 0x78, 0x00, 0x31, 0x61 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.h $w5, ($a2)" + - + input: + bytes: [ 0x79, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.h $w6, 512($a3)" + - + input: + bytes: [ 0x79, 0xff, 0x41, 0xe1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.h $w7, 1022($t0)" + - + input: + bytes: [ 0x7a, 0x00, 0x4a, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.w $w8, -2048($t1)" + - + input: + bytes: [ 0x7b, 0x00, 0x52, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.w $w9, -1024($t2)" + - + input: + bytes: [ 0x7b, 0x80, 0x5a, 0xa2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.w $w10, -512($t3)" + - + input: + bytes: [ 0x78, 0x80, 0x62, 0xe2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.w $w11, 512($t4)" + - + input: + bytes: [ 0x79, 0x00, 0x6b, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.w $w12, 1024($t5)" + - + input: + bytes: [ 0x79, 0xff, 0x73, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.w $w13, 2044($t6)" + - + input: + bytes: [ 0x7a, 0x00, 0x7b, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.d $w14, -4096($t7)" + - + input: + bytes: [ 0x7b, 0x00, 0x83, 0xe3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.d $w15, -2048($s0)" + - + input: + bytes: [ 0x7b, 0x80, 0x8c, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.d $w16, -1024($s1)" + - + input: + bytes: [ 0x7b, 0xc0, 0x94, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.d $w17, -512($s2)" + - + input: + bytes: [ 0x78, 0x00, 0x9c, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.d $w18, ($s3)" + - + input: + bytes: [ 0x78, 0x40, 0xa4, 0xe3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.d $w19, 512($s4)" + - + input: + bytes: [ 0x78, 0x80, 0xad, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.d $w20, 1024($s5)" + - + input: + bytes: [ 0x79, 0x00, 0xb5, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.d $w21, 2048($s6)" + - + input: + bytes: [ 0x79, 0xff, 0xbd, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld.d $w22, 4088($s7)" diff --git a/tests/MC/Mips/test_vec.s.yaml b/tests/MC/Mips/test_vec.s.yaml new file mode 100644 index 0000000000..34c4d2c688 --- /dev/null +++ b/tests/MC/Mips/test_vec.s.yaml @@ -0,0 +1,64 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x1b, 0xa6, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "and.v $w25, $w20, $w27" + - + input: + bytes: [ 0x78, 0x87, 0x34, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bmnz.v $w17, $w6, $w7" + - + input: + bytes: [ 0x78, 0xa9, 0x88, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bmz.v $w3, $w17, $w9" + - + input: + bytes: [ 0x78, 0xce, 0x02, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bsel.v $w8, $w0, $w14" + - + input: + bytes: [ 0x78, 0x40, 0xf9, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nor.v $w7, $w31, $w0" + - + input: + bytes: [ 0x78, 0x3e, 0xd6, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "or.v $w24, $w26, $w30" + - + input: + bytes: [ 0x78, 0x6f, 0xd9, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xor.v $w7, $w27, $w15" diff --git a/tests/MC/PowerPC/ppc64-encoding-bookII.s.yaml b/tests/MC/PowerPC/ppc64-encoding-bookII.s.yaml new file mode 100644 index 0000000000..0aac7c46c1 --- /dev/null +++ b/tests/MC/PowerPC/ppc64-encoding-bookII.s.yaml @@ -0,0 +1,163 @@ +test_cases: + - + input: + bytes: [ 0x7c, 0x02, 0x1f, 0xac ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icbi 2, 3" + - + input: + bytes: [ 0x7c, 0x02, 0x1a, 0x2c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dcbt 2, 3" + - + input: + bytes: [ 0x7c, 0x02, 0x19, 0xec ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dcbtst 2, 3" + - + input: + bytes: [ 0x7c, 0x02, 0x1f, 0xec ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dcbz 2, 3" + - + input: + bytes: [ 0x7c, 0x02, 0x18, 0x6c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dcbst 2, 3" + - + input: + bytes: [ 0x4c, 0x00, 0x01, 0x2c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "isync" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0x2d ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stwcx. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0xad ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stdcx. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x00, 0x06, 0xac ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "eieio" + - + input: + bytes: [ 0x7c, 0x02, 0x18, 0xac ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dcbf 2, 3" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x28 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lwarx 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0xa8 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldarx 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x00, 0x04, 0xac ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sync" + - + input: + bytes: [ 0x7c, 0x20, 0x04, 0xac ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lwsync" + - + input: + bytes: [ 0x7c, 0x40, 0x04, 0xac ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ptesync" + - + input: + bytes: [ 0x7c, 0x5b, 0x1a, 0xe6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mftb 2, 123" + - + input: + bytes: [ 0x7c, 0x4c, 0x42, 0xe6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mftb 2, 268" + - + input: + bytes: [ 0x7c, 0x4d, 0x42, 0xe6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mftbu 2" diff --git a/tests/MC/PowerPC/ppc64-encoding-bookIII.s.yaml b/tests/MC/PowerPC/ppc64-encoding-bookIII.s.yaml new file mode 100644 index 0000000000..4552729fa8 --- /dev/null +++ b/tests/MC/PowerPC/ppc64-encoding-bookIII.s.yaml @@ -0,0 +1,505 @@ +test_cases: + - + input: + bytes: [ 0x4c, 0x00, 0x02, 0x24 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "hrfid" + - + input: + bytes: [ 0x4c, 0x00, 0x03, 0x64 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nap" + - + input: + bytes: [ 0x7c, 0x80, 0x01, 0x24 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtmsr 4" + - + input: + bytes: [ 0x7c, 0x81, 0x01, 0x24 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtmsr 4, 1" + - + input: + bytes: [ 0x7c, 0x80, 0x00, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfmsr 4" + - + input: + bytes: [ 0x7c, 0x80, 0x01, 0x64 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtmsrd 4" + - + input: + bytes: [ 0x7c, 0x81, 0x01, 0x64 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtmsrd 4, 1" + - + input: + bytes: [ 0x7c, 0x84, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfspr 4, 260" + - + input: + bytes: [ 0x7c, 0x85, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfspr 4, 261" + - + input: + bytes: [ 0x7c, 0x86, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfspr 4, 262" + - + input: + bytes: [ 0x7c, 0x87, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfspr 4, 263" + - + input: + bytes: [ 0x7c, 0x44, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfspr 2, 260" + - + input: + bytes: [ 0x7c, 0x45, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfspr 2, 261" + - + input: + bytes: [ 0x7c, 0x46, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfspr 2, 262" + - + input: + bytes: [ 0x7c, 0x47, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfspr 2, 263" + - + input: + bytes: [ 0x7c, 0x90, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtspr 272, 4" + - + input: + bytes: [ 0x7c, 0x91, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtspr 273, 4" + - + input: + bytes: [ 0x7c, 0x92, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtspr 274, 4" + - + input: + bytes: [ 0x7c, 0x93, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtspr 275, 4" + - + input: + bytes: [ 0x7c, 0x84, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtspr 260, 4" + - + input: + bytes: [ 0x7c, 0x85, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtspr 261, 4" + - + input: + bytes: [ 0x7c, 0x86, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtspr 262, 4" + - + input: + bytes: [ 0x7c, 0x87, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtspr 263, 4" + - + input: + bytes: [ 0x7c, 0x98, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtasr 4" + - + input: + bytes: [ 0x7c, 0x96, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfdec 4" + - + input: + bytes: [ 0x7c, 0x96, 0x03, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtdec 4" + - + input: + bytes: [ 0x7c, 0x9f, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfpvr 4" + - + input: + bytes: [ 0x7c, 0x99, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfsdr1 4" + - + input: + bytes: [ 0x7c, 0x99, 0x03, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtsdr1 4" + - + input: + bytes: [ 0x7c, 0x9a, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfsrr0 4" + - + input: + bytes: [ 0x7c, 0x9a, 0x03, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtsrr0 4" + - + input: + bytes: [ 0x7c, 0x9b, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfsrr1 4" + - + input: + bytes: [ 0x7c, 0x9b, 0x03, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtsrr1 4" + - + input: + bytes: [ 0x7c, 0x00, 0x23, 0x64 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbie 4" + - + input: + bytes: [ 0x7c, 0x80, 0x2b, 0x24 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbmte 4, 5" + - + input: + bytes: [ 0x7c, 0x80, 0x2f, 0x26 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbmfee 4, 5" + - + input: + bytes: [ 0x7c, 0x40, 0x1e, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbmfev 2, 3" + - + input: + bytes: [ 0x7c, 0x00, 0x03, 0xe4 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbia" + - + input: + bytes: [ 0x7c, 0x80, 0x2f, 0xa7 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbfee. 4, 5" + - + input: + bytes: [ 0x7c, 0x00, 0x04, 0x6c ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tlbsync" + - + input: + bytes: [ 0x7c, 0x00, 0x22, 0x24 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tlbiel 4" + - + input: + bytes: [ 0x7c, 0x00, 0x22, 0x64 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tlbie 4" + - + input: + bytes: [ 0x7c, 0x00, 0x22, 0x64 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tlbie 4" + - + input: + bytes: [ 0x4c, 0x00, 0x00, 0x64 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rfi" + - + input: + bytes: [ 0x4c, 0x00, 0x00, 0x66 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rfci" + - + input: + bytes: [ 0x7d, 0x80, 0x01, 0x06 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wrtee 12" + - + input: + bytes: [ 0x7c, 0x00, 0x01, 0x46 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wrteei 0" + - + input: + bytes: [ 0x7c, 0x00, 0x81, 0x46 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wrteei 1" + - + input: + bytes: [ 0x7c, 0x00, 0x07, 0x64 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tlbre" + - + input: + bytes: [ 0x7c, 0x00, 0x07, 0xa4 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tlbwe" + - + input: + bytes: [ 0x7c, 0x0b, 0x66, 0x24 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tlbivax 11, 12" + - + input: + bytes: [ 0x7c, 0x0b, 0x67, 0x24 ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tlbsx 11, 12" + - + input: + bytes: [ 0x7c, 0xb0, 0x62, 0x9c ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfpmr 5, 400" + - + input: + bytes: [ 0x7c, 0xd0, 0x63, 0x9c ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtpmr 400, 6" + - + input: + bytes: [ 0x7c, 0x00, 0x41, 0xcc ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icblc 0, 0, 8" + - + input: + bytes: [ 0x7c, 0x00, 0x4b, 0xcc ] + arch: "CS_ARCH_PPC" + options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icbtls 0, 0, 9" diff --git a/tests/MC/PowerPC/ppc64-encoding-ext.s.yaml b/tests/MC/PowerPC/ppc64-encoding-ext.s.yaml new file mode 100644 index 0000000000..23152c22fe --- /dev/null +++ b/tests/MC/PowerPC/ppc64-encoding-ext.s.yaml @@ -0,0 +1,5356 @@ +test_cases: + - + input: + bytes: [ 0x4d, 0x82, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 2" + - + input: + bytes: [ 0x4d, 0x86, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 6" + - + input: + bytes: [ 0x4d, 0x8a, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 10" + - + input: + bytes: [ 0x4d, 0x8e, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 14" + - + input: + bytes: [ 0x4d, 0x92, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 18" + - + input: + bytes: [ 0x4d, 0x96, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 22" + - + input: + bytes: [ 0x4d, 0x9a, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 26" + - + input: + bytes: [ 0x4d, 0x9e, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 30" + - + input: + bytes: [ 0x4d, 0x80, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 0" + - + input: + bytes: [ 0x4d, 0x81, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 1" + - + input: + bytes: [ 0x4d, 0x82, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 2" + - + input: + bytes: [ 0x4d, 0x83, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 3" + - + input: + bytes: [ 0x4d, 0x83, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 3" + - + input: + bytes: [ 0x4d, 0x84, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 4" + - + input: + bytes: [ 0x4d, 0x85, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 5" + - + input: + bytes: [ 0x4d, 0x86, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 6" + - + input: + bytes: [ 0x4d, 0x87, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 7" + - + input: + bytes: [ 0x4d, 0x87, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 7" + - + input: + bytes: [ 0x4d, 0x88, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 8" + - + input: + bytes: [ 0x4d, 0x89, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 9" + - + input: + bytes: [ 0x4d, 0x8a, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 10" + - + input: + bytes: [ 0x4d, 0x8b, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 11" + - + input: + bytes: [ 0x4d, 0x8b, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 11" + - + input: + bytes: [ 0x4d, 0x8c, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 12" + - + input: + bytes: [ 0x4d, 0x8d, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 13" + - + input: + bytes: [ 0x4d, 0x8e, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 14" + - + input: + bytes: [ 0x4d, 0x8f, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 15" + - + input: + bytes: [ 0x4d, 0x8f, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 15" + - + input: + bytes: [ 0x4d, 0x90, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 16" + - + input: + bytes: [ 0x4d, 0x91, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 17" + - + input: + bytes: [ 0x4d, 0x92, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 18" + - + input: + bytes: [ 0x4d, 0x93, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 19" + - + input: + bytes: [ 0x4d, 0x93, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 19" + - + input: + bytes: [ 0x4d, 0x94, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 20" + - + input: + bytes: [ 0x4d, 0x95, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 21" + - + input: + bytes: [ 0x4d, 0x96, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 22" + - + input: + bytes: [ 0x4d, 0x97, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 23" + - + input: + bytes: [ 0x4d, 0x97, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 23" + - + input: + bytes: [ 0x4d, 0x98, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 24" + - + input: + bytes: [ 0x4d, 0x99, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 25" + - + input: + bytes: [ 0x4d, 0x9a, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 26" + - + input: + bytes: [ 0x4d, 0x9b, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 27" + - + input: + bytes: [ 0x4d, 0x9b, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 27" + - + input: + bytes: [ 0x4d, 0x9c, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 28" + - + input: + bytes: [ 0x4d, 0x9d, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 29" + - + input: + bytes: [ 0x4d, 0x9e, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 30" + - + input: + bytes: [ 0x4d, 0x9f, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 31" + - + input: + bytes: [ 0x4d, 0x9f, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 31" + - + input: + bytes: [ 0x4e, 0x80, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "blr" + - + input: + bytes: [ 0x4e, 0x80, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bctrl" + - + input: + bytes: [ 0x4d, 0x82, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 2" + - + input: + bytes: [ 0x4d, 0x82, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr 2" + - + input: + bytes: [ 0x4d, 0x82, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl 2" + - + input: + bytes: [ 0x4d, 0x82, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl 2" + - + input: + bytes: [ 0x4d, 0xe2, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr+ 2" + - + input: + bytes: [ 0x4d, 0xe2, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr+ 2" + - + input: + bytes: [ 0x4d, 0xe2, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl+ 2" + - + input: + bytes: [ 0x4d, 0xe2, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl+ 2" + - + input: + bytes: [ 0x4d, 0xc2, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr- 2" + - + input: + bytes: [ 0x4d, 0xc2, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr- 2" + - + input: + bytes: [ 0x4d, 0xc2, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl- 2" + - + input: + bytes: [ 0x4d, 0xc2, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl- 2" + - + input: + bytes: [ 0x4c, 0x82, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr 2" + - + input: + bytes: [ 0x4c, 0x82, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr 2" + - + input: + bytes: [ 0x4c, 0x82, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl 2" + - + input: + bytes: [ 0x4c, 0x82, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl 2" + - + input: + bytes: [ 0x4c, 0xe2, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr+ 2" + - + input: + bytes: [ 0x4c, 0xe2, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr+ 2" + - + input: + bytes: [ 0x4c, 0xe2, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl+ 2" + - + input: + bytes: [ 0x4c, 0xe2, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl+ 2" + - + input: + bytes: [ 0x4c, 0xc2, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr- 2" + - + input: + bytes: [ 0x4c, 0xc2, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr- 2" + - + input: + bytes: [ 0x4c, 0xc2, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl- 2" + - + input: + bytes: [ 0x4c, 0xc2, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl- 2" + - + input: + bytes: [ 0x4d, 0x02, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bdnztlr 2" + - + input: + bytes: [ 0x4d, 0x02, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bdnztlrl 2" + - + input: + bytes: [ 0x4c, 0x02, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bdnzflr 2" + - + input: + bytes: [ 0x4c, 0x02, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bdnzflrl 2" + - + input: + bytes: [ 0x4d, 0x42, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bdztlr 2" + - + input: + bytes: [ 0x4d, 0x42, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bdztlrl 2" + - + input: + bytes: [ 0x4c, 0x42, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bdzflr 2" + - + input: + bytes: [ 0x4c, 0x42, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bdzflrl 2" + - + input: + bytes: [ 0x4d, 0x88, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 8" + - + input: + bytes: [ 0x4d, 0x80, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 0" + - + input: + bytes: [ 0x4d, 0x88, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr 8" + - + input: + bytes: [ 0x4d, 0x80, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr 0" + - + input: + bytes: [ 0x4d, 0x88, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl 8" + - + input: + bytes: [ 0x4d, 0x80, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl 0" + - + input: + bytes: [ 0x4d, 0x88, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl 8" + - + input: + bytes: [ 0x4d, 0x80, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl 0" + - + input: + bytes: [ 0x4d, 0xe8, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr+ 8" + - + input: + bytes: [ 0x4d, 0xe0, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr+ 0" + - + input: + bytes: [ 0x4d, 0xe8, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr+ 8" + - + input: + bytes: [ 0x4d, 0xe0, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr+ 0" + - + input: + bytes: [ 0x4d, 0xe8, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl+ 8" + - + input: + bytes: [ 0x4d, 0xe0, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl+ 0" + - + input: + bytes: [ 0x4d, 0xe8, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl+ 8" + - + input: + bytes: [ 0x4d, 0xe0, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl+ 0" + - + input: + bytes: [ 0x4d, 0xc8, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr- 8" + - + input: + bytes: [ 0x4d, 0xc0, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr- 0" + - + input: + bytes: [ 0x4d, 0xc8, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr- 8" + - + input: + bytes: [ 0x4d, 0xc0, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr- 0" + - + input: + bytes: [ 0x4d, 0xc8, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl- 8" + - + input: + bytes: [ 0x4d, 0xc0, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl- 0" + - + input: + bytes: [ 0x4d, 0xc8, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl- 8" + - + input: + bytes: [ 0x4d, 0xc0, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl- 0" + - + input: + bytes: [ 0x4c, 0x89, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr 9" + - + input: + bytes: [ 0x4c, 0x81, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr 1" + - + input: + bytes: [ 0x4c, 0x89, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr 9" + - + input: + bytes: [ 0x4c, 0x81, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr 1" + - + input: + bytes: [ 0x4c, 0x89, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl 9" + - + input: + bytes: [ 0x4c, 0x81, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl 1" + - + input: + bytes: [ 0x4c, 0x89, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl 9" + - + input: + bytes: [ 0x4c, 0x81, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl 1" + - + input: + bytes: [ 0x4c, 0xe9, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr+ 9" + - + input: + bytes: [ 0x4c, 0xe1, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr+ 1" + - + input: + bytes: [ 0x4c, 0xe9, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr+ 9" + - + input: + bytes: [ 0x4c, 0xe1, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr+ 1" + - + input: + bytes: [ 0x4c, 0xe9, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl+ 9" + - + input: + bytes: [ 0x4c, 0xe1, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl+ 1" + - + input: + bytes: [ 0x4c, 0xe9, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl+ 9" + - + input: + bytes: [ 0x4c, 0xe1, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl+ 1" + - + input: + bytes: [ 0x4c, 0xc9, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr- 9" + - + input: + bytes: [ 0x4c, 0xc1, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr- 1" + - + input: + bytes: [ 0x4c, 0xc9, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr- 9" + - + input: + bytes: [ 0x4c, 0xc1, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr- 1" + - + input: + bytes: [ 0x4c, 0xc9, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl- 9" + - + input: + bytes: [ 0x4c, 0xc1, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl- 1" + - + input: + bytes: [ 0x4c, 0xc9, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl- 9" + - + input: + bytes: [ 0x4c, 0xc1, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl- 1" + - + input: + bytes: [ 0x4d, 0x8a, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 10" + - + input: + bytes: [ 0x4d, 0x82, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 2" + - + input: + bytes: [ 0x4d, 0x8a, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr 10" + - + input: + bytes: [ 0x4d, 0x82, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr 2" + - + input: + bytes: [ 0x4d, 0x8a, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl 10" + - + input: + bytes: [ 0x4d, 0x82, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl 2" + - + input: + bytes: [ 0x4d, 0x8a, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl 10" + - + input: + bytes: [ 0x4d, 0x82, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl 2" + - + input: + bytes: [ 0x4d, 0xea, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr+ 10" + - + input: + bytes: [ 0x4d, 0xe2, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr+ 2" + - + input: + bytes: [ 0x4d, 0xea, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr+ 10" + - + input: + bytes: [ 0x4d, 0xe2, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr+ 2" + - + input: + bytes: [ 0x4d, 0xea, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl+ 10" + - + input: + bytes: [ 0x4d, 0xe2, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl+ 2" + - + input: + bytes: [ 0x4d, 0xea, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl+ 10" + - + input: + bytes: [ 0x4d, 0xe2, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl+ 2" + - + input: + bytes: [ 0x4d, 0xca, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr- 10" + - + input: + bytes: [ 0x4d, 0xc2, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr- 2" + - + input: + bytes: [ 0x4d, 0xca, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr- 10" + - + input: + bytes: [ 0x4d, 0xc2, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr- 2" + - + input: + bytes: [ 0x4d, 0xca, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl- 10" + - + input: + bytes: [ 0x4d, 0xc2, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl- 2" + - + input: + bytes: [ 0x4d, 0xca, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl- 10" + - + input: + bytes: [ 0x4d, 0xc2, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl- 2" + - + input: + bytes: [ 0x4c, 0x88, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr 8" + - + input: + bytes: [ 0x4c, 0x80, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr 0" + - + input: + bytes: [ 0x4c, 0x88, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr 8" + - + input: + bytes: [ 0x4c, 0x80, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr 0" + - + input: + bytes: [ 0x4c, 0x88, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl 8" + - + input: + bytes: [ 0x4c, 0x80, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl 0" + - + input: + bytes: [ 0x4c, 0x88, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl 8" + - + input: + bytes: [ 0x4c, 0x80, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl 0" + - + input: + bytes: [ 0x4c, 0xe8, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr+ 8" + - + input: + bytes: [ 0x4c, 0xe0, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr+ 0" + - + input: + bytes: [ 0x4c, 0xe8, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr+ 8" + - + input: + bytes: [ 0x4c, 0xe0, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr+ 0" + - + input: + bytes: [ 0x4c, 0xe8, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl+ 8" + - + input: + bytes: [ 0x4c, 0xe0, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl+ 0" + - + input: + bytes: [ 0x4c, 0xe8, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl+ 8" + - + input: + bytes: [ 0x4c, 0xe0, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl+ 0" + - + input: + bytes: [ 0x4c, 0xc8, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr- 8" + - + input: + bytes: [ 0x4c, 0xc0, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr- 0" + - + input: + bytes: [ 0x4c, 0xc8, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr- 8" + - + input: + bytes: [ 0x4c, 0xc0, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr- 0" + - + input: + bytes: [ 0x4c, 0xc8, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl- 8" + - + input: + bytes: [ 0x4c, 0xc0, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl- 0" + - + input: + bytes: [ 0x4c, 0xc8, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl- 8" + - + input: + bytes: [ 0x4c, 0xc0, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl- 0" + - + input: + bytes: [ 0x4d, 0x89, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 9" + - + input: + bytes: [ 0x4d, 0x81, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 1" + - + input: + bytes: [ 0x4d, 0x89, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr 9" + - + input: + bytes: [ 0x4d, 0x81, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr 1" + - + input: + bytes: [ 0x4d, 0x89, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl 9" + - + input: + bytes: [ 0x4d, 0x81, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl 1" + - + input: + bytes: [ 0x4d, 0x89, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl 9" + - + input: + bytes: [ 0x4d, 0x81, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl 1" + - + input: + bytes: [ 0x4d, 0xe9, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr+ 9" + - + input: + bytes: [ 0x4d, 0xe1, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr+ 1" + - + input: + bytes: [ 0x4d, 0xe9, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr+ 9" + - + input: + bytes: [ 0x4d, 0xe1, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr+ 1" + - + input: + bytes: [ 0x4d, 0xe9, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl+ 9" + - + input: + bytes: [ 0x4d, 0xe1, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl+ 1" + - + input: + bytes: [ 0x4d, 0xe9, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl+ 9" + - + input: + bytes: [ 0x4d, 0xe1, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl+ 1" + - + input: + bytes: [ 0x4d, 0xc9, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr- 9" + - + input: + bytes: [ 0x4d, 0xc1, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr- 1" + - + input: + bytes: [ 0x4d, 0xc9, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr- 9" + - + input: + bytes: [ 0x4d, 0xc1, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr- 1" + - + input: + bytes: [ 0x4d, 0xc9, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl- 9" + - + input: + bytes: [ 0x4d, 0xc1, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl- 1" + - + input: + bytes: [ 0x4d, 0xc9, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl- 9" + - + input: + bytes: [ 0x4d, 0xc1, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl- 1" + - + input: + bytes: [ 0x4c, 0x88, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr 8" + - + input: + bytes: [ 0x4c, 0x80, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr 0" + - + input: + bytes: [ 0x4c, 0x88, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr 8" + - + input: + bytes: [ 0x4c, 0x80, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr 0" + - + input: + bytes: [ 0x4c, 0x88, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl 8" + - + input: + bytes: [ 0x4c, 0x80, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl 0" + - + input: + bytes: [ 0x4c, 0x88, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl 8" + - + input: + bytes: [ 0x4c, 0x80, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl 0" + - + input: + bytes: [ 0x4c, 0xe8, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr+ 8" + - + input: + bytes: [ 0x4c, 0xe0, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr+ 0" + - + input: + bytes: [ 0x4c, 0xe8, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr+ 8" + - + input: + bytes: [ 0x4c, 0xe0, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr+ 0" + - + input: + bytes: [ 0x4c, 0xe8, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl+ 8" + - + input: + bytes: [ 0x4c, 0xe0, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl+ 0" + - + input: + bytes: [ 0x4c, 0xe8, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl+ 8" + - + input: + bytes: [ 0x4c, 0xe0, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl+ 0" + - + input: + bytes: [ 0x4c, 0xc8, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr- 8" + - + input: + bytes: [ 0x4c, 0xc0, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr- 0" + - + input: + bytes: [ 0x4c, 0xc8, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr- 8" + - + input: + bytes: [ 0x4c, 0xc0, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr- 0" + - + input: + bytes: [ 0x4c, 0xc8, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl- 8" + - + input: + bytes: [ 0x4c, 0xc0, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl- 0" + - + input: + bytes: [ 0x4c, 0xc8, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl- 8" + - + input: + bytes: [ 0x4c, 0xc0, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl- 0" + - + input: + bytes: [ 0x4c, 0x8a, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr 10" + - + input: + bytes: [ 0x4c, 0x82, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr 2" + - + input: + bytes: [ 0x4c, 0x8a, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr 10" + - + input: + bytes: [ 0x4c, 0x82, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr 2" + - + input: + bytes: [ 0x4c, 0x8a, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl 10" + - + input: + bytes: [ 0x4c, 0x82, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl 2" + - + input: + bytes: [ 0x4c, 0x8a, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl 10" + - + input: + bytes: [ 0x4c, 0x82, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl 2" + - + input: + bytes: [ 0x4c, 0xea, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr+ 10" + - + input: + bytes: [ 0x4c, 0xe2, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr+ 2" + - + input: + bytes: [ 0x4c, 0xea, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr+ 10" + - + input: + bytes: [ 0x4c, 0xe2, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr+ 2" + - + input: + bytes: [ 0x4c, 0xea, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl+ 10" + - + input: + bytes: [ 0x4c, 0xe2, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl+ 2" + - + input: + bytes: [ 0x4c, 0xea, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl+ 10" + - + input: + bytes: [ 0x4c, 0xe2, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl+ 2" + - + input: + bytes: [ 0x4c, 0xca, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr- 10" + - + input: + bytes: [ 0x4c, 0xc2, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr- 2" + - + input: + bytes: [ 0x4c, 0xca, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr- 10" + - + input: + bytes: [ 0x4c, 0xc2, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr- 2" + - + input: + bytes: [ 0x4c, 0xca, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl- 10" + - + input: + bytes: [ 0x4c, 0xc2, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl- 2" + - + input: + bytes: [ 0x4c, 0xca, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl- 10" + - + input: + bytes: [ 0x4c, 0xc2, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl- 2" + - + input: + bytes: [ 0x4c, 0x89, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr 9" + - + input: + bytes: [ 0x4c, 0x81, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr 1" + - + input: + bytes: [ 0x4c, 0x89, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr 9" + - + input: + bytes: [ 0x4c, 0x81, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr 1" + - + input: + bytes: [ 0x4c, 0x89, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl 9" + - + input: + bytes: [ 0x4c, 0x81, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl 1" + - + input: + bytes: [ 0x4c, 0x89, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl 9" + - + input: + bytes: [ 0x4c, 0x81, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl 1" + - + input: + bytes: [ 0x4c, 0xe9, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr+ 9" + - + input: + bytes: [ 0x4c, 0xe1, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr+ 1" + - + input: + bytes: [ 0x4c, 0xe9, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr+ 9" + - + input: + bytes: [ 0x4c, 0xe1, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr+ 1" + - + input: + bytes: [ 0x4c, 0xe9, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl+ 9" + - + input: + bytes: [ 0x4c, 0xe1, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl+ 1" + - + input: + bytes: [ 0x4c, 0xe9, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl+ 9" + - + input: + bytes: [ 0x4c, 0xe1, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl+ 1" + - + input: + bytes: [ 0x4c, 0xc9, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr- 9" + - + input: + bytes: [ 0x4c, 0xc1, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr- 1" + - + input: + bytes: [ 0x4c, 0xc9, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr- 9" + - + input: + bytes: [ 0x4c, 0xc1, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr- 1" + - + input: + bytes: [ 0x4c, 0xc9, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl- 9" + - + input: + bytes: [ 0x4c, 0xc1, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl- 1" + - + input: + bytes: [ 0x4c, 0xc9, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl- 9" + - + input: + bytes: [ 0x4c, 0xc1, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl- 1" + - + input: + bytes: [ 0x4d, 0x8b, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 11" + - + input: + bytes: [ 0x4d, 0x83, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 3" + - + input: + bytes: [ 0x4d, 0x8b, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr 11" + - + input: + bytes: [ 0x4d, 0x83, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr 3" + - + input: + bytes: [ 0x4d, 0x8b, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl 11" + - + input: + bytes: [ 0x4d, 0x83, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl 3" + - + input: + bytes: [ 0x4d, 0x8b, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl 11" + - + input: + bytes: [ 0x4d, 0x83, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl 3" + - + input: + bytes: [ 0x4d, 0xeb, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr+ 11" + - + input: + bytes: [ 0x4d, 0xe3, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr+ 3" + - + input: + bytes: [ 0x4d, 0xeb, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr+ 11" + - + input: + bytes: [ 0x4d, 0xe3, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr+ 3" + - + input: + bytes: [ 0x4d, 0xeb, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl+ 11" + - + input: + bytes: [ 0x4d, 0xe3, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl+ 3" + - + input: + bytes: [ 0x4d, 0xeb, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl+ 11" + - + input: + bytes: [ 0x4d, 0xe3, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl+ 3" + - + input: + bytes: [ 0x4d, 0xcb, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr- 11" + - + input: + bytes: [ 0x4d, 0xc3, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr- 3" + - + input: + bytes: [ 0x4d, 0xcb, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr- 11" + - + input: + bytes: [ 0x4d, 0xc3, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr- 3" + - + input: + bytes: [ 0x4d, 0xcb, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl- 11" + - + input: + bytes: [ 0x4d, 0xc3, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl- 3" + - + input: + bytes: [ 0x4d, 0xcb, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl- 11" + - + input: + bytes: [ 0x4d, 0xc3, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl- 3" + - + input: + bytes: [ 0x4c, 0x8b, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr 11" + - + input: + bytes: [ 0x4c, 0x83, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr 3" + - + input: + bytes: [ 0x4c, 0x8b, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr 11" + - + input: + bytes: [ 0x4c, 0x83, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr 3" + - + input: + bytes: [ 0x4c, 0x8b, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl 11" + - + input: + bytes: [ 0x4c, 0x83, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl 3" + - + input: + bytes: [ 0x4c, 0x8b, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl 11" + - + input: + bytes: [ 0x4c, 0x83, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl 3" + - + input: + bytes: [ 0x4c, 0xeb, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr+ 11" + - + input: + bytes: [ 0x4c, 0xe3, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr+ 3" + - + input: + bytes: [ 0x4c, 0xeb, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr+ 11" + - + input: + bytes: [ 0x4c, 0xe3, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr+ 3" + - + input: + bytes: [ 0x4c, 0xeb, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl+ 11" + - + input: + bytes: [ 0x4c, 0xe3, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl+ 3" + - + input: + bytes: [ 0x4c, 0xeb, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl+ 11" + - + input: + bytes: [ 0x4c, 0xe3, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl+ 3" + - + input: + bytes: [ 0x4c, 0xcb, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr- 11" + - + input: + bytes: [ 0x4c, 0xc3, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr- 3" + - + input: + bytes: [ 0x4c, 0xcb, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr- 11" + - + input: + bytes: [ 0x4c, 0xc3, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr- 3" + - + input: + bytes: [ 0x4c, 0xcb, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl- 11" + - + input: + bytes: [ 0x4c, 0xc3, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl- 3" + - + input: + bytes: [ 0x4c, 0xcb, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl- 11" + - + input: + bytes: [ 0x4c, 0xc3, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl- 3" + - + input: + bytes: [ 0x4d, 0x8b, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 11" + - + input: + bytes: [ 0x4d, 0x83, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr 3" + - + input: + bytes: [ 0x4d, 0x8b, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr 11" + - + input: + bytes: [ 0x4d, 0x83, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr 3" + - + input: + bytes: [ 0x4d, 0x8b, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl 11" + - + input: + bytes: [ 0x4d, 0x83, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl 3" + - + input: + bytes: [ 0x4d, 0x8b, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl 11" + - + input: + bytes: [ 0x4d, 0x83, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl 3" + - + input: + bytes: [ 0x4d, 0xeb, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr+ 11" + - + input: + bytes: [ 0x4d, 0xe3, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr+ 3" + - + input: + bytes: [ 0x4d, 0xeb, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr+ 11" + - + input: + bytes: [ 0x4d, 0xe3, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr+ 3" + - + input: + bytes: [ 0x4d, 0xeb, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl+ 11" + - + input: + bytes: [ 0x4d, 0xe3, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl+ 3" + - + input: + bytes: [ 0x4d, 0xeb, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl+ 11" + - + input: + bytes: [ 0x4d, 0xe3, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl+ 3" + - + input: + bytes: [ 0x4d, 0xcb, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr- 11" + - + input: + bytes: [ 0x4d, 0xc3, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlr- 3" + - + input: + bytes: [ 0x4d, 0xcb, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr- 11" + - + input: + bytes: [ 0x4d, 0xc3, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctr- 3" + - + input: + bytes: [ 0x4d, 0xcb, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl- 11" + - + input: + bytes: [ 0x4d, 0xc3, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btlrl- 3" + - + input: + bytes: [ 0x4d, 0xcb, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl- 11" + - + input: + bytes: [ 0x4d, 0xc3, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "btctrl- 3" + - + input: + bytes: [ 0x4c, 0x8b, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr 11" + - + input: + bytes: [ 0x4c, 0x83, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr 3" + - + input: + bytes: [ 0x4c, 0x8b, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr 11" + - + input: + bytes: [ 0x4c, 0x83, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr 3" + - + input: + bytes: [ 0x4c, 0x8b, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl 11" + - + input: + bytes: [ 0x4c, 0x83, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl 3" + - + input: + bytes: [ 0x4c, 0x8b, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl 11" + - + input: + bytes: [ 0x4c, 0x83, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl 3" + - + input: + bytes: [ 0x4c, 0xeb, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr+ 11" + - + input: + bytes: [ 0x4c, 0xe3, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr+ 3" + - + input: + bytes: [ 0x4c, 0xeb, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr+ 11" + - + input: + bytes: [ 0x4c, 0xe3, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr+ 3" + - + input: + bytes: [ 0x4c, 0xeb, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl+ 11" + - + input: + bytes: [ 0x4c, 0xe3, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl+ 3" + - + input: + bytes: [ 0x4c, 0xeb, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl+ 11" + - + input: + bytes: [ 0x4c, 0xe3, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl+ 3" + - + input: + bytes: [ 0x4c, 0xcb, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr- 11" + - + input: + bytes: [ 0x4c, 0xc3, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr- 3" + - + input: + bytes: [ 0x4c, 0xcb, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr- 11" + - + input: + bytes: [ 0x4c, 0xc3, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr- 3" + - + input: + bytes: [ 0x4c, 0xcb, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl- 11" + - + input: + bytes: [ 0x4c, 0xc3, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl- 3" + - + input: + bytes: [ 0x4c, 0xcb, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl- 11" + - + input: + bytes: [ 0x4c, 0xc3, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl- 3" + - + input: + bytes: [ 0x4c, 0x42, 0x12, 0x42 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crset 2" + - + input: + bytes: [ 0x4c, 0x42, 0x11, 0x82 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crclr 2" + - + input: + bytes: [ 0x4c, 0x43, 0x1b, 0x82 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crmove 2, 3" + - + input: + bytes: [ 0x4c, 0x43, 0x18, 0x42 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crnot 2, 3" + - + input: + bytes: [ 0x38, 0x43, 0xff, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addi 2, 3, -128" + - + input: + bytes: [ 0x3c, 0x43, 0xff, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addis 2, 3, -128" + - + input: + bytes: [ 0x30, 0x43, 0xff, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addic 2, 3, -128" + - + input: + bytes: [ 0x34, 0x43, 0xff, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addic. 2, 3, -128" + - + input: + bytes: [ 0x7c, 0x44, 0x18, 0x50 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sub 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x44, 0x18, 0x51 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sub. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x44, 0x18, 0x10 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subc 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x44, 0x18, 0x11 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subc. 2, 3, 4" + - + input: + bytes: [ 0x2d, 0x23, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpdi 2, 3, 128" + - + input: + bytes: [ 0x2c, 0x23, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpdi 3, 128" + - + input: + bytes: [ 0x7d, 0x23, 0x20, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpd 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x23, 0x20, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpd 3, 4" + - + input: + bytes: [ 0x29, 0x23, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpldi 2, 3, 128" + - + input: + bytes: [ 0x28, 0x23, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpldi 3, 128" + - + input: + bytes: [ 0x7d, 0x23, 0x20, 0x40 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpld 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x23, 0x20, 0x40 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpld 3, 4" + - + input: + bytes: [ 0x2d, 0x03, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpwi 2, 3, 128" + - + input: + bytes: [ 0x2c, 0x03, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpwi 3, 128" + - + input: + bytes: [ 0x7d, 0x03, 0x20, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpw 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x03, 0x20, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpw 3, 4" + - + input: + bytes: [ 0x29, 0x03, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmplwi 2, 3, 128" + - + input: + bytes: [ 0x28, 0x03, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmplwi 3, 128" + - + input: + bytes: [ 0x7d, 0x03, 0x20, 0x40 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmplw 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x03, 0x20, 0x40 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmplw 3, 4" + - + input: + bytes: [ 0x0e, 0x03, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twlti 3, 4" + - + input: + bytes: [ 0x7e, 0x03, 0x20, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twlt 3, 4" + - + input: + bytes: [ 0x0a, 0x03, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdlti 3, 4" + - + input: + bytes: [ 0x7e, 0x03, 0x20, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdlt 3, 4" + - + input: + bytes: [ 0x0e, 0x83, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twi 20, 3, 4" + - + input: + bytes: [ 0x7e, 0x83, 0x20, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tw 20, 3, 4" + - + input: + bytes: [ 0x0a, 0x83, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdi 20, 3, 4" + - + input: + bytes: [ 0x7e, 0x83, 0x20, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "td 20, 3, 4" + - + input: + bytes: [ 0x0c, 0x83, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tweqi 3, 4" + - + input: + bytes: [ 0x7c, 0x83, 0x20, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tweq 3, 4" + - + input: + bytes: [ 0x08, 0x83, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdeqi 3, 4" + - + input: + bytes: [ 0x7c, 0x83, 0x20, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdeq 3, 4" + - + input: + bytes: [ 0x0d, 0x83, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twi 12, 3, 4" + - + input: + bytes: [ 0x7d, 0x83, 0x20, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tw 12, 3, 4" + - + input: + bytes: [ 0x09, 0x83, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdi 12, 3, 4" + - + input: + bytes: [ 0x7d, 0x83, 0x20, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "td 12, 3, 4" + - + input: + bytes: [ 0x0d, 0x03, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twgti 3, 4" + - + input: + bytes: [ 0x7d, 0x03, 0x20, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twgt 3, 4" + - + input: + bytes: [ 0x09, 0x03, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdgti 3, 4" + - + input: + bytes: [ 0x7d, 0x03, 0x20, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdgt 3, 4" + - + input: + bytes: [ 0x0d, 0x83, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twi 12, 3, 4" + - + input: + bytes: [ 0x7d, 0x83, 0x20, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tw 12, 3, 4" + - + input: + bytes: [ 0x09, 0x83, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdi 12, 3, 4" + - + input: + bytes: [ 0x7d, 0x83, 0x20, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "td 12, 3, 4" + - + input: + bytes: [ 0x0f, 0x03, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twnei 3, 4" + - + input: + bytes: [ 0x7f, 0x03, 0x20, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twne 3, 4" + - + input: + bytes: [ 0x0b, 0x03, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdnei 3, 4" + - + input: + bytes: [ 0x7f, 0x03, 0x20, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdne 3, 4" + - + input: + bytes: [ 0x0e, 0x83, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twi 20, 3, 4" + - + input: + bytes: [ 0x7e, 0x83, 0x20, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tw 20, 3, 4" + - + input: + bytes: [ 0x0a, 0x83, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdi 20, 3, 4" + - + input: + bytes: [ 0x7e, 0x83, 0x20, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "td 20, 3, 4" + - + input: + bytes: [ 0x0c, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twllti 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twllt 3, 4" + - + input: + bytes: [ 0x08, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdllti 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdllt 3, 4" + - + input: + bytes: [ 0x0c, 0xc3, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twi 6, 3, 4" + - + input: + bytes: [ 0x7c, 0xc3, 0x20, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tw 6, 3, 4" + - + input: + bytes: [ 0x08, 0xc3, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdi 6, 3, 4" + - + input: + bytes: [ 0x7c, 0xc3, 0x20, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "td 6, 3, 4" + - + input: + bytes: [ 0x0c, 0xa3, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twi 5, 3, 4" + - + input: + bytes: [ 0x7c, 0xa3, 0x20, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tw 5, 3, 4" + - + input: + bytes: [ 0x08, 0xa3, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdi 5, 3, 4" + - + input: + bytes: [ 0x7c, 0xa3, 0x20, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "td 5, 3, 4" + - + input: + bytes: [ 0x0c, 0x23, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twlgti 3, 4" + - + input: + bytes: [ 0x7c, 0x23, 0x20, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twlgt 3, 4" + - + input: + bytes: [ 0x08, 0x23, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdlgti 3, 4" + - + input: + bytes: [ 0x7c, 0x23, 0x20, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdlgt 3, 4" + - + input: + bytes: [ 0x0c, 0xa3, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twi 5, 3, 4" + - + input: + bytes: [ 0x7c, 0xa3, 0x20, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tw 5, 3, 4" + - + input: + bytes: [ 0x08, 0xa3, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdi 5, 3, 4" + - + input: + bytes: [ 0x7c, 0xa3, 0x20, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "td 5, 3, 4" + - + input: + bytes: [ 0x0c, 0xc3, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twi 6, 3, 4" + - + input: + bytes: [ 0x7c, 0xc3, 0x20, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tw 6, 3, 4" + - + input: + bytes: [ 0x08, 0xc3, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdi 6, 3, 4" + - + input: + bytes: [ 0x7c, 0xc3, 0x20, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "td 6, 3, 4" + - + input: + bytes: [ 0x0f, 0xe3, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twui 3, 4" + - + input: + bytes: [ 0x7f, 0xe3, 0x20, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twu 3, 4" + - + input: + bytes: [ 0x0b, 0xe3, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdui 3, 4" + - + input: + bytes: [ 0x7f, 0xe3, 0x20, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdu 3, 4" + - + input: + bytes: [ 0x7f, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trap" + - + input: + bytes: [ 0x78, 0x62, 0x28, 0xc4 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldicr 2, 3, 5, 3" + - + input: + bytes: [ 0x78, 0x62, 0x28, 0xc5 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldicr. 2, 3, 5, 3" + - + input: + bytes: [ 0x78, 0x62, 0x4f, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldicl 2, 3, 9, 60" + - + input: + bytes: [ 0x78, 0x62, 0x4f, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldicl. 2, 3, 9, 60" + - + input: + bytes: [ 0x78, 0x62, 0xb9, 0x4e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldimi 2, 3, 55, 5" + - + input: + bytes: [ 0x78, 0x62, 0xb9, 0x4f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldimi. 2, 3, 55, 5" + - + input: + bytes: [ 0x78, 0x62, 0x20, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rotldi 2, 3, 4" + - + input: + bytes: [ 0x78, 0x62, 0x20, 0x01 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rotldi. 2, 3, 4" + - + input: + bytes: [ 0x78, 0x62, 0xe0, 0x02 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rotldi 2, 3, 60" + - + input: + bytes: [ 0x78, 0x62, 0xe0, 0x03 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rotldi. 2, 3, 60" + - + input: + bytes: [ 0x78, 0x62, 0x20, 0x10 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rotld 2, 3, 4" + - + input: + bytes: [ 0x78, 0x62, 0x20, 0x11 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rotld. 2, 3, 4" + - + input: + bytes: [ 0x78, 0x62, 0x26, 0xe4 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldi 2, 3, 4" + - + input: + bytes: [ 0x78, 0x62, 0x26, 0xe5 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldicr. 2, 3, 4, 59" + - + input: + bytes: [ 0x78, 0x62, 0xe1, 0x02 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldicl 2, 3, 60, 4" + - + input: + bytes: [ 0x78, 0x62, 0xe1, 0x03 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldicl. 2, 3, 60, 4" + - + input: + bytes: [ 0x78, 0x62, 0x01, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrldi 2, 3, 4" + - + input: + bytes: [ 0x78, 0x62, 0x01, 0x01 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrldi. 2, 3, 4" + - + input: + bytes: [ 0x78, 0x62, 0x06, 0xe4 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldicr 2, 3, 0, 59" + - + input: + bytes: [ 0x78, 0x62, 0x06, 0xe5 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldicr. 2, 3, 0, 59" + - + input: + bytes: [ 0x78, 0x62, 0x20, 0x48 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldic 2, 3, 4, 1" + - + input: + bytes: [ 0x78, 0x62, 0x20, 0x49 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldic. 2, 3, 4, 1" + - + input: + bytes: [ 0x54, 0x62, 0x28, 0x06 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwinm 2, 3, 5, 0, 3" + - + input: + bytes: [ 0x54, 0x62, 0x28, 0x07 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwinm. 2, 3, 5, 0, 3" + - + input: + bytes: [ 0x54, 0x62, 0x4f, 0x3e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwinm 2, 3, 9, 28, 31" + - + input: + bytes: [ 0x54, 0x62, 0x4f, 0x3f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwinm. 2, 3, 9, 28, 31" + - + input: + bytes: [ 0x50, 0x62, 0xd9, 0x50 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwimi 2, 3, 27, 5, 8" + - + input: + bytes: [ 0x50, 0x62, 0xd9, 0x51 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwimi. 2, 3, 27, 5, 8" + - + input: + bytes: [ 0x50, 0x62, 0xb9, 0x50 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwimi 2, 3, 23, 5, 8" + - + input: + bytes: [ 0x50, 0x62, 0xb9, 0x51 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwimi. 2, 3, 23, 5, 8" + - + input: + bytes: [ 0x54, 0x62, 0x20, 0x3e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rotlwi 2, 3, 4" + - + input: + bytes: [ 0x54, 0x62, 0x20, 0x3f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rotlwi. 2, 3, 4" + - + input: + bytes: [ 0x54, 0x62, 0xe0, 0x3e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rotlwi 2, 3, 28" + - + input: + bytes: [ 0x54, 0x62, 0xe0, 0x3f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rotlwi. 2, 3, 28" + - + input: + bytes: [ 0x5c, 0x62, 0x20, 0x3e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rotlw 2, 3, 4" + - + input: + bytes: [ 0x5c, 0x62, 0x20, 0x3f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rotlw. 2, 3, 4" + - + input: + bytes: [ 0x54, 0x62, 0x20, 0x36 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slwi 2, 3, 4" + - + input: + bytes: [ 0x54, 0x62, 0x20, 0x37 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwinm. 2, 3, 4, 0, 27" + - + input: + bytes: [ 0x54, 0x62, 0xe1, 0x3e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srwi 2, 3, 4" + - + input: + bytes: [ 0x54, 0x62, 0xe1, 0x3f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwinm. 2, 3, 28, 4, 31" + - + input: + bytes: [ 0x54, 0x62, 0x01, 0x3e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrlwi 2, 3, 4" + - + input: + bytes: [ 0x54, 0x62, 0x01, 0x3f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrlwi. 2, 3, 4" + - + input: + bytes: [ 0x54, 0x62, 0x00, 0x36 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwinm 2, 3, 0, 0, 27" + - + input: + bytes: [ 0x54, 0x62, 0x00, 0x37 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwinm. 2, 3, 0, 0, 27" + - + input: + bytes: [ 0x54, 0x62, 0x20, 0x76 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwinm 2, 3, 4, 1, 27" + - + input: + bytes: [ 0x54, 0x62, 0x20, 0x77 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwinm. 2, 3, 4, 1, 27" + - + input: + bytes: [ 0x7c, 0x41, 0x03, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtxer 2" + - + input: + bytes: [ 0x7c, 0x41, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfxer 2" + - + input: + bytes: [ 0x7c, 0x43, 0x03, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtudscr 2" + - + input: + bytes: [ 0x7c, 0x43, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfudscr 2" + - + input: + bytes: [ 0x7c, 0x44, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfrtcu 2" + - + input: + bytes: [ 0x7c, 0x45, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfrtcl 2" + - + input: + bytes: [ 0x7c, 0x43, 0x03, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtudscr 2" + - + input: + bytes: [ 0x7c, 0x43, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfudscr 2" + - + input: + bytes: [ 0x7c, 0x51, 0x03, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtdscr 2" + - + input: + bytes: [ 0x7c, 0x51, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfdscr 2" + - + input: + bytes: [ 0x7c, 0x52, 0x03, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtdsisr 2" + - + input: + bytes: [ 0x7c, 0x52, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfdsisr 2" + - + input: + bytes: [ 0x7c, 0x53, 0x03, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtdar 2" + - + input: + bytes: [ 0x7c, 0x53, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfdar 2" + - + input: + bytes: [ 0x7c, 0x56, 0x03, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtdec 2" + - + input: + bytes: [ 0x7c, 0x56, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfdec 2" + - + input: + bytes: [ 0x7c, 0x59, 0x03, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtsdr1 2" + - + input: + bytes: [ 0x7c, 0x59, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfsdr1 2" + - + input: + bytes: [ 0x7c, 0x5a, 0x03, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtsrr0 2" + - + input: + bytes: [ 0x7c, 0x5a, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfsrr0 2" + - + input: + bytes: [ 0x7c, 0x5b, 0x03, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtsrr1 2" + - + input: + bytes: [ 0x7c, 0x5b, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfsrr1 2" + - + input: + bytes: [ 0x7c, 0x5c, 0x03, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtcfar 2" + - + input: + bytes: [ 0x7c, 0x5c, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfcfar 2" + - + input: + bytes: [ 0x7c, 0x5d, 0x03, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtamr 2" + - + input: + bytes: [ 0x7c, 0x5d, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfamr 2" + - + input: + bytes: [ 0x7c, 0x50, 0x0b, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtpid 2" + - + input: + bytes: [ 0x7c, 0x50, 0x0a, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfpid 2" + - + input: + bytes: [ 0x7c, 0x48, 0x03, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtlr 2" + - + input: + bytes: [ 0x7c, 0x48, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mflr 2" + - + input: + bytes: [ 0x7c, 0x49, 0x03, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtctr 2" + - + input: + bytes: [ 0x7c, 0x49, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfctr 2" + - + input: + bytes: [ 0x7c, 0x4d, 0x03, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtuamr 2" + - + input: + bytes: [ 0x7c, 0x4d, 0x02, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfuamr 2" + - + input: + bytes: [ 0x7c, 0x40, 0xe3, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtppr 2" + - + input: + bytes: [ 0x7c, 0x40, 0xe2, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfppr 2" + - + input: + bytes: [ 0x7c, 0x40, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfspr 2, 256" + - + input: + bytes: [ 0x7c, 0x40, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtspr 256, 2" + - + input: + bytes: [ 0x60, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x68, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xnop" + - + input: + bytes: [ 0x38, 0x40, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "li 2, 128" + - + input: + bytes: [ 0x3c, 0x40, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lis 2, 128" + - + input: + bytes: [ 0x7c, 0x62, 0x1b, 0x78 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mr 2, 3" + - + input: + bytes: [ 0x7c, 0x62, 0x1b, 0x79 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mr. 2, 3" + - + input: + bytes: [ 0x7c, 0x62, 0x18, 0xf8 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "not 2, 3" + - + input: + bytes: [ 0x7c, 0x62, 0x18, 0xf9 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "not. 2, 3" + - + input: + bytes: [ 0x7c, 0x4f, 0xf1, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtcr 2" + - + input: + bytes: [ 0x7c, 0x90, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfspr 4, 272" + - + input: + bytes: [ 0x7c, 0x91, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfspr 4, 273" + - + input: + bytes: [ 0x7c, 0x92, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfspr 4, 274" + - + input: + bytes: [ 0x7c, 0x93, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfspr 4, 275" + - + input: + bytes: [ 0x7c, 0x52, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfspr 2, 274" + - + input: + bytes: [ 0x7c, 0x50, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfspr 2, 272" + - + input: + bytes: [ 0x7c, 0x51, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfspr 2, 273" + - + input: + bytes: [ 0x7c, 0x52, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfspr 2, 274" + - + input: + bytes: [ 0x7c, 0x53, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfspr 2, 275" + - + input: + bytes: [ 0x7c, 0x90, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtspr 272, 4" + - + input: + bytes: [ 0x7c, 0x91, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtspr 273, 4" + - + input: + bytes: [ 0x7c, 0x92, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtspr 274, 4" + - + input: + bytes: [ 0x7c, 0x93, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtspr 275, 4" + - + input: + bytes: [ 0x7c, 0x52, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtspr 274, 2" + - + input: + bytes: [ 0x7c, 0x90, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtspr 272, 4" + - + input: + bytes: [ 0x7c, 0x91, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtspr 273, 4" + - + input: + bytes: [ 0x7c, 0x92, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtspr 274, 4" + - + input: + bytes: [ 0x7c, 0x93, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtspr 275, 4" + - + input: + bytes: [ 0x7c, 0x60, 0x06, 0x6c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dss 3" + - + input: + bytes: [ 0x7e, 0x00, 0x06, 0x6c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dssall" + - + input: + bytes: [ 0x7c, 0x6c, 0x5a, 0xac ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dst 12, 11, 3" + - + input: + bytes: [ 0x7e, 0x6c, 0x5a, 0xac ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dstt 12, 11, 3" + - + input: + bytes: [ 0x7c, 0x6c, 0x5a, 0xec ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dstst 12, 11, 3" + - + input: + bytes: [ 0x7e, 0x6c, 0x5a, 0xec ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dststt 12, 11, 3" + - + input: + bytes: [ 0x7c, 0x00, 0x02, 0xe4 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tlbia" + - + input: + bytes: [ 0x7d, 0x06, 0x3c, 0xaa ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lswi 8, 6, 7" + - + input: + bytes: [ 0x7d, 0x06, 0x3d, 0xaa ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stswi 8, 6, 7" + - + input: + bytes: [ 0x4c, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rfid" + - + input: + bytes: [ 0x7c, 0x58, 0x42, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfasr 2" + - + input: + bytes: [ 0x7c, 0x58, 0x43, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtasr 2" + - + input: + bytes: [ 0x7e, 0xa5, 0x3e, 0xaa ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbzcix 21, 5, 7" + - + input: + bytes: [ 0x7e, 0xa5, 0x3e, 0x6a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhzcix 21, 5, 7" + - + input: + bytes: [ 0x7e, 0xa5, 0x3e, 0x2a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lwzcix 21, 5, 7" + - + input: + bytes: [ 0x7e, 0xa5, 0x3e, 0xea ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldcix 21, 5, 7" + - + input: + bytes: [ 0x7e, 0xa5, 0x3f, 0xaa ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stbcix 21, 5, 7" + - + input: + bytes: [ 0x7e, 0xa5, 0x3f, 0x6a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthcix 21, 5, 7" + - + input: + bytes: [ 0x7e, 0xa5, 0x3f, 0x2a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stwcix 21, 5, 7" + - + input: + bytes: [ 0x7e, 0xa5, 0x3f, 0xea ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stdcix 21, 5, 7" + - + input: + bytes: [ 0x00, 0x00, 0x02, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "attn" + - + input: + bytes: [ 0x7c, 0x22, 0x9e, 0x0c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "copy 2, 19" + - + input: + bytes: [ 0x7c, 0x11, 0x0f, 0x0d ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "paste. 17, 1, 0" + - + input: + bytes: [ 0x7c, 0x31, 0x0f, 0x0d ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "paste. 17, 1" + - + input: + bytes: [ 0x7c, 0x31, 0x0f, 0x0d ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "paste. 17, 1" diff --git a/tests/MC/PowerPC/ppc64-encoding-fp.s.yaml b/tests/MC/PowerPC/ppc64-encoding-fp.s.yaml new file mode 100644 index 0000000000..bb8a1184d3 --- /dev/null +++ b/tests/MC/PowerPC/ppc64-encoding-fp.s.yaml @@ -0,0 +1,982 @@ +test_cases: + - + input: + bytes: [ 0xc0, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfs 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x24, 0x2e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfsx 2, 3, 4" + - + input: + bytes: [ 0xc4, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfsu 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x24, 0x6e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfsux 2, 3, 4" + - + input: + bytes: [ 0xc8, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfd 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x24, 0xae ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfdx 2, 3, 4" + - + input: + bytes: [ 0xcc, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfdu 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x24, 0xee ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfdux 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x26, 0xae ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfiwax 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x26, 0xee ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfiwzx 2, 3, 4" + - + input: + bytes: [ 0xd0, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfs 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x25, 0x2e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfsx 2, 3, 4" + - + input: + bytes: [ 0xd4, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfsu 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x25, 0x6e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfsux 2, 3, 4" + - + input: + bytes: [ 0xd8, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfd 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x25, 0xae ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfdx 2, 3, 4" + - + input: + bytes: [ 0xdc, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfdu 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x25, 0xee ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfdux 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x27, 0xae ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfiwx 2, 3, 4" + - + input: + bytes: [ 0xfc, 0x40, 0x18, 0x90 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmr 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x18, 0x91 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmr. 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x18, 0x50 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fneg 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x18, 0x51 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fneg. 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1a, 0x10 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fabs 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1a, 0x11 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fabs. 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x19, 0x10 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fnabs 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x19, 0x11 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fnabs. 2, 3" + - + input: + bytes: [ 0xfc, 0x43, 0x20, 0x10 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcpsgn 2, 3, 4" + - + input: + bytes: [ 0xfc, 0x43, 0x20, 0x11 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcpsgn. 2, 3, 4" + - + input: + bytes: [ 0xfc, 0x43, 0x20, 0x2a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fadd 2, 3, 4" + - + input: + bytes: [ 0xfc, 0x43, 0x20, 0x2b ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fadd. 2, 3, 4" + - + input: + bytes: [ 0xec, 0x43, 0x20, 0x2a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fadds 2, 3, 4" + - + input: + bytes: [ 0xec, 0x43, 0x20, 0x2b ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fadds. 2, 3, 4" + - + input: + bytes: [ 0xfc, 0x43, 0x20, 0x28 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsub 2, 3, 4" + - + input: + bytes: [ 0xfc, 0x43, 0x20, 0x29 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsub. 2, 3, 4" + - + input: + bytes: [ 0xec, 0x43, 0x20, 0x28 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsubs 2, 3, 4" + - + input: + bytes: [ 0xec, 0x43, 0x20, 0x29 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsubs. 2, 3, 4" + - + input: + bytes: [ 0xfc, 0x43, 0x01, 0x32 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmul 2, 3, 4" + - + input: + bytes: [ 0xfc, 0x43, 0x01, 0x33 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmul. 2, 3, 4" + - + input: + bytes: [ 0xec, 0x43, 0x01, 0x32 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmuls 2, 3, 4" + - + input: + bytes: [ 0xec, 0x43, 0x01, 0x33 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmuls. 2, 3, 4" + - + input: + bytes: [ 0xfc, 0x43, 0x20, 0x24 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fdiv 2, 3, 4" + - + input: + bytes: [ 0xfc, 0x43, 0x20, 0x25 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fdiv. 2, 3, 4" + - + input: + bytes: [ 0xec, 0x43, 0x20, 0x24 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fdivs 2, 3, 4" + - + input: + bytes: [ 0xec, 0x43, 0x20, 0x25 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fdivs. 2, 3, 4" + - + input: + bytes: [ 0xfc, 0x40, 0x18, 0x2c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsqrt 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x18, 0x2d ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsqrt. 2, 3" + - + input: + bytes: [ 0xec, 0x40, 0x18, 0x2c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsqrts 2, 3" + - + input: + bytes: [ 0xec, 0x40, 0x18, 0x2d ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsqrts. 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x18, 0x30 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fre 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x18, 0x31 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fre. 2, 3" + - + input: + bytes: [ 0xec, 0x40, 0x18, 0x30 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fres 2, 3" + - + input: + bytes: [ 0xec, 0x40, 0x18, 0x31 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fres. 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x18, 0x34 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "frsqrte 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x18, 0x35 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "frsqrte. 2, 3" + - + input: + bytes: [ 0xec, 0x40, 0x18, 0x34 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "frsqrtes 2, 3" + - + input: + bytes: [ 0xec, 0x40, 0x18, 0x35 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "frsqrtes. 2, 3" + - + input: + bytes: [ 0xfc, 0x43, 0x29, 0x3a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmadd 2, 3, 4, 5" + - + input: + bytes: [ 0xfc, 0x43, 0x29, 0x3b ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmadd. 2, 3, 4, 5" + - + input: + bytes: [ 0xec, 0x43, 0x29, 0x3a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmadds 2, 3, 4, 5" + - + input: + bytes: [ 0xec, 0x43, 0x29, 0x3b ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmadds. 2, 3, 4, 5" + - + input: + bytes: [ 0xfc, 0x43, 0x29, 0x38 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmsub 2, 3, 4, 5" + - + input: + bytes: [ 0xfc, 0x43, 0x29, 0x39 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmsub. 2, 3, 4, 5" + - + input: + bytes: [ 0xec, 0x43, 0x29, 0x38 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmsubs 2, 3, 4, 5" + - + input: + bytes: [ 0xec, 0x43, 0x29, 0x39 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmsubs. 2, 3, 4, 5" + - + input: + bytes: [ 0xfc, 0x43, 0x29, 0x3e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fnmadd 2, 3, 4, 5" + - + input: + bytes: [ 0xfc, 0x43, 0x29, 0x3f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fnmadd. 2, 3, 4, 5" + - + input: + bytes: [ 0xec, 0x43, 0x29, 0x3e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fnmadds 2, 3, 4, 5" + - + input: + bytes: [ 0xec, 0x43, 0x29, 0x3f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fnmadds. 2, 3, 4, 5" + - + input: + bytes: [ 0xfc, 0x43, 0x29, 0x3c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fnmsub 2, 3, 4, 5" + - + input: + bytes: [ 0xfc, 0x43, 0x29, 0x3d ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fnmsub. 2, 3, 4, 5" + - + input: + bytes: [ 0xec, 0x43, 0x29, 0x3c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fnmsubs 2, 3, 4, 5" + - + input: + bytes: [ 0xec, 0x43, 0x29, 0x3d ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fnmsubs. 2, 3, 4, 5" + - + input: + bytes: [ 0xfc, 0x40, 0x18, 0x18 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "frsp 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x18, 0x19 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "frsp. 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1e, 0x5c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fctid 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1e, 0x5d ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fctid. 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1e, 0x5e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fctidz 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1e, 0x5f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fctidz. 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1f, 0x5e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fctiduz 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1f, 0x5f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fctiduz. 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x18, 0x1c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fctiw 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x18, 0x1d ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fctiw. 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x18, 0x1e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fctiwz 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x18, 0x1f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fctiwz. 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x19, 0x1e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fctiwuz 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x19, 0x1f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fctiwuz. 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1e, 0x9c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcfid 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1e, 0x9d ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcfid. 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1f, 0x9c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcfidu 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1f, 0x9d ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcfidu. 2, 3" + - + input: + bytes: [ 0xec, 0x40, 0x1e, 0x9c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcfids 2, 3" + - + input: + bytes: [ 0xec, 0x40, 0x1e, 0x9d ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcfids. 2, 3" + - + input: + bytes: [ 0xec, 0x40, 0x1f, 0x9c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcfidus 2, 3" + - + input: + bytes: [ 0xec, 0x40, 0x1f, 0x9d ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcfidus. 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1b, 0x10 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "frin 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1b, 0x11 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "frin. 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1b, 0x90 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "frip 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1b, 0x91 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "frip. 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1b, 0x50 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "friz 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1b, 0x51 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "friz. 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1b, 0xd0 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "frim 2, 3" + - + input: + bytes: [ 0xfc, 0x40, 0x1b, 0xd1 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "frim. 2, 3" + - + input: + bytes: [ 0xfd, 0x03, 0x20, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmpu 2, 3, 4" + - + input: + bytes: [ 0xfc, 0x43, 0x29, 0x2e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsel 2, 3, 4, 5" + - + input: + bytes: [ 0xfc, 0x43, 0x29, 0x2f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsel. 2, 3, 4, 5" + - + input: + bytes: [ 0xfc, 0x40, 0x04, 0x8e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mffs 2" + - + input: + bytes: [ 0xff, 0xe0, 0x00, 0x8c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtfsb0 31" + - + input: + bytes: [ 0xff, 0xe0, 0x00, 0x4c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtfsb1 31" diff --git a/tests/MC/PowerPC/ppc64-encoding-vmx.s.yaml b/tests/MC/PowerPC/ppc64-encoding-vmx.s.yaml new file mode 100644 index 0000000000..b3df327526 --- /dev/null +++ b/tests/MC/PowerPC/ppc64-encoding-vmx.s.yaml @@ -0,0 +1,1522 @@ +test_cases: + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x0e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lvebx 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x4e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lvehx 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x8e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lvewx 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0xce ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lvx 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x22, 0xce ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lvxl 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0x0e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stvebx 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0x4e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stvehx 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0x8e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stvewx 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0xce ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stvx 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x23, 0xce ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stvxl 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x0c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lvsl 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x4c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lvsr 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x23, 0x0e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkpx 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x8e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkshss 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x0e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkshus 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0xce ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkswss 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x4e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkswus 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x0e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkuhum 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x8e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkuhus 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x4e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkuwum 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0xce ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkuwus 2, 3, 4" + - + input: + bytes: [ 0x10, 0x40, 0x1b, 0x4e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkhpx 2, 3" + - + input: + bytes: [ 0x10, 0x40, 0x1a, 0x0e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkhsb 2, 3" + - + input: + bytes: [ 0x10, 0x40, 0x1a, 0x4e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkhsh 2, 3" + - + input: + bytes: [ 0x10, 0x40, 0x1b, 0xce ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupklpx 2, 3" + - + input: + bytes: [ 0x10, 0x40, 0x1a, 0x8e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupklsb 2, 3" + - + input: + bytes: [ 0x10, 0x40, 0x1a, 0xce ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupklsh 2, 3" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x0c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrghb 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x4c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrghh 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x8c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrghw 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x0c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrglb 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x4c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrglh 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x8c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrglw 2, 3, 4" + - + input: + bytes: [ 0x10, 0x41, 0x1a, 0x0c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vspltb 2, 3, 1" + - + input: + bytes: [ 0x10, 0x41, 0x1a, 0x4c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsplth 2, 3, 1" + - + input: + bytes: [ 0x10, 0x41, 0x1a, 0x8c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vspltw 2, 3, 1" + - + input: + bytes: [ 0x10, 0x43, 0x03, 0x0c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vspltisb 2, 3" + - + input: + bytes: [ 0x10, 0x43, 0x03, 0x4c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vspltish 2, 3" + - + input: + bytes: [ 0x10, 0x43, 0x03, 0x8c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vspltisw 2, 3" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x6b ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vperm 2, 3, 4, 5" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x6a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsel 2, 3, 4, 5" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0xc4 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsl 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x6c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsldoi 2, 3, 4, 5" + - + input: + bytes: [ 0x10, 0x43, 0x24, 0x0c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vslo 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x22, 0xc4 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsr 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x24, 0x4c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsro 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaddcuw 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x23, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaddsbs 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x23, 0x40 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaddshs 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x23, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaddsws 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaddubm 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x40 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vadduhm 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vadduwm 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x22, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaddubs 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x22, 0x40 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vadduhs 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x22, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vadduws 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x25, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsubcuw 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x27, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsubsbs 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x27, 0x40 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsubshs 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x27, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsubsws 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x24, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsububm 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x24, 0x40 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsubuhm 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x24, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsubuwm 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x26, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsububs 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x26, 0x40 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsubuhs 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x26, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsubuws 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x23, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmulesb 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x23, 0x48 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmulesh 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x22, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmuleub 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x22, 0x48 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmuleuh 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmulosb 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x48 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmulosh 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmuloub 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x48 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmulouh 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x60 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmhaddshs 2, 3, 4, 5" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x61 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmhraddshs 2, 3, 4, 5" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x62 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmladduhm 2, 3, 4, 5" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x64 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsumubm 2, 3, 4, 5" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x65 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsummbm 2, 3, 4, 5" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x68 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsumshm 2, 3, 4, 5" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x69 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsumshs 2, 3, 4, 5" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x66 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsumuhm 2, 3, 4, 5" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x67 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsumuhs 2, 3, 4, 5" + - + input: + bytes: [ 0x10, 0x43, 0x27, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumsws 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x26, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsum2sws 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x27, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsum4sbs 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x26, 0x48 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsum4shs 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x26, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsum4ubs 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x25, 0x02 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavgsb 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x25, 0x42 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavgsh 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x25, 0x82 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavgsw 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x24, 0x02 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavgub 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x24, 0x42 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavguh 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x24, 0x82 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavguw 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x02 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaxsb 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x42 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaxsh 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x82 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaxsw 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x02 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaxub 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x42 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaxuh 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x82 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaxuw 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x23, 0x02 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vminsb 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x23, 0x42 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vminsh 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x23, 0x82 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vminsw 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x22, 0x02 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vminub 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x22, 0x42 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vminuh 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x22, 0x82 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vminuw 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x06 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpequb 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x24, 0x06 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpequb. 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x46 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpequh 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x24, 0x46 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpequh. 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x86 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpequw 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x24, 0x86 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpequw. 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x23, 0x06 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpgtsb 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x27, 0x06 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpgtsb. 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x23, 0x46 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpgtsh 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x27, 0x46 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpgtsh. 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x23, 0x86 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpgtsw 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x27, 0x86 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpgtsw. 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x22, 0x06 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpgtub 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x26, 0x06 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpgtub. 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x22, 0x46 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpgtuh 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x26, 0x46 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpgtuh. 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x22, 0x86 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpgtuw 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x26, 0x86 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpgtuw. 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x24, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vand 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x24, 0x44 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vandc 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x25, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vnor 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x24, 0x84 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vor 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x24, 0xc4 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vxor 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrlb 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x44 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrlh 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x84 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrlw 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vslb 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x44 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vslh 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0x84 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vslw 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x22, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrb 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x22, 0x44 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrh 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x22, 0x84 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrw 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x23, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrab 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x23, 0x44 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrah 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x23, 0x84 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsraw 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x0a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaddfp 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0x4a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsubfp 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x29, 0x2e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaddfp 2, 3, 4, 5" + - + input: + bytes: [ 0x10, 0x43, 0x29, 0x2f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vnmsubfp 2, 3, 4, 5" + - + input: + bytes: [ 0x10, 0x43, 0x24, 0x0a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaxfp 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x24, 0x4a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vminfp 2, 3, 4" + - + input: + bytes: [ 0x10, 0x44, 0x1b, 0xca ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vctsxs 2, 3, 4" + - + input: + bytes: [ 0x10, 0x44, 0x1b, 0x8a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vctuxs 2, 3, 4" + - + input: + bytes: [ 0x10, 0x44, 0x1b, 0x4a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcfsx 2, 3, 4" + - + input: + bytes: [ 0x10, 0x44, 0x1b, 0x0a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcfux 2, 3, 4" + - + input: + bytes: [ 0x10, 0x40, 0x1a, 0xca ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrfim 2, 3" + - + input: + bytes: [ 0x10, 0x40, 0x1a, 0x0a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrfin 2, 3" + - + input: + bytes: [ 0x10, 0x40, 0x1a, 0x8a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrfip 2, 3" + - + input: + bytes: [ 0x10, 0x40, 0x1a, 0x4a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrfiz 2, 3" + - + input: + bytes: [ 0x10, 0x43, 0x23, 0xc6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpbfp 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x27, 0xc6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpbfp. 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x20, 0xc6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpeqfp 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x24, 0xc6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpeqfp. 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x21, 0xc6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpgefp 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x25, 0xc6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpgefp. 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x22, 0xc6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpgtfp 2, 3, 4" + - + input: + bytes: [ 0x10, 0x43, 0x26, 0xc6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcmpgtfp. 2, 3, 4" + - + input: + bytes: [ 0x10, 0x40, 0x19, 0x8a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vexptefp 2, 3" + - + input: + bytes: [ 0x10, 0x40, 0x19, 0xca ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlogefp 2, 3" + - + input: + bytes: [ 0x10, 0x40, 0x19, 0x0a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrefp 2, 3" + - + input: + bytes: [ 0x10, 0x40, 0x19, 0x4a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrsqrtefp 2, 3" + - + input: + bytes: [ 0x10, 0x00, 0x16, 0x44 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtvscr 2" + - + input: + bytes: [ 0x10, 0x40, 0x06, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfvscr 2" diff --git a/tests/MC/PowerPC/ppc64-encoding.s.yaml b/tests/MC/PowerPC/ppc64-encoding.s.yaml new file mode 100644 index 0000000000..803ae48364 --- /dev/null +++ b/tests/MC/PowerPC/ppc64-encoding.s.yaml @@ -0,0 +1,1801 @@ +test_cases: + - + input: + bytes: [ 0x4c, 0x8a, 0x18, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bclr 4, 10, 3" + - + input: + bytes: [ 0x4c, 0x8a, 0x00, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflr 10" + - + input: + bytes: [ 0x4c, 0x8a, 0x18, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bclrl 4, 10, 3" + - + input: + bytes: [ 0x4c, 0x8a, 0x00, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bflrl 10" + - + input: + bytes: [ 0x4c, 0x8a, 0x1c, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bcctr 4, 10, 3" + - + input: + bytes: [ 0x4c, 0x8a, 0x04, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctr 10" + - + input: + bytes: [ 0x4c, 0x8a, 0x1c, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bcctrl 4, 10, 3" + - + input: + bytes: [ 0x4c, 0x8a, 0x04, 0x21 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bfctrl 10" + - + input: + bytes: [ 0x4c, 0x43, 0x22, 0x02 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crand 2, 3, 4" + - + input: + bytes: [ 0x4c, 0x43, 0x21, 0xc2 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crnand 2, 3, 4" + - + input: + bytes: [ 0x4c, 0x43, 0x23, 0x82 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cror 2, 3, 4" + - + input: + bytes: [ 0x4c, 0x43, 0x21, 0x82 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crxor 2, 3, 4" + - + input: + bytes: [ 0x4c, 0x43, 0x20, 0x42 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crnor 2, 3, 4" + - + input: + bytes: [ 0x4c, 0x43, 0x22, 0x42 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "creqv 2, 3, 4" + - + input: + bytes: [ 0x4c, 0x43, 0x21, 0x02 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crandc 2, 3, 4" + - + input: + bytes: [ 0x4c, 0x43, 0x23, 0x42 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crorc 2, 3, 4" + - + input: + bytes: [ 0x4d, 0x0c, 0x00, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mcrf 2, 3" + - + input: + bytes: [ 0x44, 0x00, 0x00, 0x22 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sc 1" + - + input: + bytes: [ 0x44, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sc" + - + input: + bytes: [ 0x88, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbz 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0xae ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbzx 2, 3, 4" + - + input: + bytes: [ 0x8c, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbzu 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0xee ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbzux 2, 3, 4" + - + input: + bytes: [ 0xa0, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhz 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x22, 0x2e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhzx 2, 3, 4" + - + input: + bytes: [ 0xa4, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhzu 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x22, 0x6e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhzux 2, 3, 4" + - + input: + bytes: [ 0xa8, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lha 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x22, 0xae ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhax 2, 3, 4" + - + input: + bytes: [ 0xac, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhau 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x22, 0xee ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhaux 2, 3, 4" + - + input: + bytes: [ 0x80, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lwz 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x2e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lwzx 2, 3, 4" + - + input: + bytes: [ 0x84, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lwzu 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x6e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lwzux 2, 3, 4" + - + input: + bytes: [ 0xe8, 0x44, 0x00, 0x82 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lwa 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x22, 0xaa ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lwax 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x22, 0xea ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lwaux 2, 3, 4" + - + input: + bytes: [ 0xe8, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x2a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldx 2, 3, 4" + - + input: + bytes: [ 0xe8, 0x44, 0x00, 0x81 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldu 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x6a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldux 2, 3, 4" + - + input: + bytes: [ 0x98, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stb 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0xae ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stbx 2, 3, 4" + - + input: + bytes: [ 0x9c, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stbu 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0xee ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stbux 2, 3, 4" + - + input: + bytes: [ 0xb0, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sth 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x23, 0x2e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthx 2, 3, 4" + - + input: + bytes: [ 0xb4, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthu 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x23, 0x6e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthux 2, 3, 4" + - + input: + bytes: [ 0x90, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stw 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0x2e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stwx 2, 3, 4" + - + input: + bytes: [ 0x94, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stwu 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0x6e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stwux 2, 3, 4" + - + input: + bytes: [ 0xf8, 0x44, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "std 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0x2a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stdx 2, 3, 4" + - + input: + bytes: [ 0xf8, 0x44, 0x00, 0x81 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stdu 2, 128(4)" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0x6a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stdux 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x26, 0x2c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhbrx 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x27, 0x2c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthbrx 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x24, 0x2c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lwbrx 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x25, 0x2c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stwbrx 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x24, 0x28 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldbrx 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x25, 0x28 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stdbrx 2, 3, 4" + - + input: + bytes: [ 0xb8, 0x41, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmw 2, 128(1)" + - + input: + bytes: [ 0xbc, 0x41, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmw 2, 128(1)" + - + input: + bytes: [ 0x38, 0x43, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addi 2, 3, 128" + - + input: + bytes: [ 0x3c, 0x43, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addis 2, 3, 128" + - + input: + bytes: [ 0x7c, 0x43, 0x22, 0x14 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "add 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x22, 0x15 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "add. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x50 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sub 2, 4, 3" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x51 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sub. 2, 4, 3" + - + input: + bytes: [ 0x30, 0x43, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addic 2, 3, 128" + - + input: + bytes: [ 0x34, 0x43, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addic. 2, 3, 128" + - + input: + bytes: [ 0x20, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subfic 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x14 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addc 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x15 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addc. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x10 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subc 2, 4, 3" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0x14 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adde 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0x15 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adde. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0x10 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subfe 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0x11 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subfe. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x01, 0xd4 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addme 2, 3" + - + input: + bytes: [ 0x7c, 0x43, 0x01, 0xd5 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addme. 2, 3" + - + input: + bytes: [ 0x7c, 0x43, 0x01, 0xd0 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subfme 2, 3" + - + input: + bytes: [ 0x7c, 0x43, 0x01, 0xd1 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subfme. 2, 3" + - + input: + bytes: [ 0x7c, 0x43, 0x01, 0x94 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addze 2, 3" + - + input: + bytes: [ 0x7c, 0x43, 0x01, 0x95 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addze. 2, 3" + - + input: + bytes: [ 0x7c, 0x43, 0x01, 0x90 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subfze 2, 3" + - + input: + bytes: [ 0x7c, 0x43, 0x01, 0x91 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subfze. 2, 3" + - + input: + bytes: [ 0x7c, 0x43, 0x00, 0xd0 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "neg 2, 3" + - + input: + bytes: [ 0x7c, 0x43, 0x00, 0xd1 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "neg. 2, 3" + - + input: + bytes: [ 0x1c, 0x43, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulli 2, 3, 128" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x96 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulhw 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x97 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulhw. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0xd6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mullw 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0xd7 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mullw. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x16 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulhwu 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x17 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulhwu. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x23, 0xd6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "divw 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x23, 0xd7 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "divw. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x23, 0x96 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "divwu 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x23, 0x97 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "divwu. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0xd2 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulld 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0xd3 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulld. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x92 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulhd 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x93 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulhd. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x12 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulhdu 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x13 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulhdu. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x23, 0xd2 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "divd 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x23, 0xd3 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "divd. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x23, 0x92 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "divdu 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x23, 0x93 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "divdu. 2, 3, 4" + - + input: + bytes: [ 0x2d, 0x23, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpdi 2, 3, 128" + - + input: + bytes: [ 0x7d, 0x23, 0x20, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpd 2, 3, 4" + - + input: + bytes: [ 0x29, 0x23, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpldi 2, 3, 128" + - + input: + bytes: [ 0x7d, 0x23, 0x20, 0x40 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpld 2, 3, 4" + - + input: + bytes: [ 0x2d, 0x03, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpwi 2, 3, 128" + - + input: + bytes: [ 0x7d, 0x03, 0x20, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpw 2, 3, 4" + - + input: + bytes: [ 0x29, 0x03, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmplwi 2, 3, 128" + - + input: + bytes: [ 0x7d, 0x03, 0x20, 0x40 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmplw 2, 3, 4" + - + input: + bytes: [ 0x0c, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twllti 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "twllt 3, 4" + - + input: + bytes: [ 0x08, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdllti 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x20, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdllt 3, 4" + - + input: + bytes: [ 0x7c, 0x43, 0x21, 0x5e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "isel 2, 3, 4, 5" + - + input: + bytes: [ 0x70, 0x62, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "andi. 2, 3, 128" + - + input: + bytes: [ 0x74, 0x62, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "andis. 2, 3, 128" + - + input: + bytes: [ 0x60, 0x62, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ori 2, 3, 128" + - + input: + bytes: [ 0x64, 0x62, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oris 2, 3, 128" + - + input: + bytes: [ 0x68, 0x62, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xori 2, 3, 128" + - + input: + bytes: [ 0x6c, 0x62, 0x00, 0x80 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xoris 2, 3, 128" + - + input: + bytes: [ 0x7c, 0x62, 0x20, 0x38 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "and 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x20, 0x39 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "and. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x22, 0x78 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xor 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x22, 0x79 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xor. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x23, 0xb8 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nand 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x23, 0xb9 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nand. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x23, 0x78 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "or 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x23, 0x79 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "or. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x20, 0xf8 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nor 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x20, 0xf9 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nor. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x22, 0x38 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "eqv 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x22, 0x39 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "eqv. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x20, 0x78 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "andc 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x20, 0x79 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "andc. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x23, 0x38 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "orc 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x23, 0x39 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "orc. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x07, 0x74 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extsb 2, 3" + - + input: + bytes: [ 0x7c, 0x62, 0x07, 0x75 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extsb. 2, 3" + - + input: + bytes: [ 0x7c, 0x62, 0x07, 0x34 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extsh 2, 3" + - + input: + bytes: [ 0x7c, 0x62, 0x07, 0x35 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extsh. 2, 3" + - + input: + bytes: [ 0x7c, 0x62, 0x00, 0x34 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cntlzw 2, 3" + - + input: + bytes: [ 0x7c, 0x62, 0x00, 0x35 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cntlzw. 2, 3" + - + input: + bytes: [ 0x7c, 0x62, 0x02, 0xf4 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "popcntw 2, 3" + - + input: + bytes: [ 0x7c, 0x62, 0x07, 0xb4 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extsw 2, 3" + - + input: + bytes: [ 0x7c, 0x62, 0x07, 0xb5 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "extsw. 2, 3" + - + input: + bytes: [ 0x7c, 0x62, 0x00, 0x74 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cntlzd 2, 3" + - + input: + bytes: [ 0x7c, 0x62, 0x00, 0x75 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cntlzd. 2, 3" + - + input: + bytes: [ 0x7c, 0x62, 0x03, 0xf4 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "popcntd 2, 3" + - + input: + bytes: [ 0x54, 0x62, 0x21, 0x4c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwinm 2, 3, 4, 5, 6" + - + input: + bytes: [ 0x54, 0x62, 0x21, 0x4d ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwinm. 2, 3, 4, 5, 6" + - + input: + bytes: [ 0x5c, 0x62, 0x21, 0x4c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwnm 2, 3, 4, 5, 6" + - + input: + bytes: [ 0x5c, 0x62, 0x21, 0x4d ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwnm. 2, 3, 4, 5, 6" + - + input: + bytes: [ 0x50, 0x62, 0x21, 0x4c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwimi 2, 3, 4, 5, 6" + - + input: + bytes: [ 0x50, 0x62, 0x21, 0x4d ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rlwimi. 2, 3, 4, 5, 6" + - + input: + bytes: [ 0x78, 0x62, 0x21, 0x40 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldicl 2, 3, 4, 5" + - + input: + bytes: [ 0x78, 0x62, 0x21, 0x41 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldicl. 2, 3, 4, 5" + - + input: + bytes: [ 0x78, 0x62, 0x21, 0x44 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldicr 2, 3, 4, 5" + - + input: + bytes: [ 0x78, 0x62, 0x21, 0x45 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldicr. 2, 3, 4, 5" + - + input: + bytes: [ 0x78, 0x62, 0x21, 0x48 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldic 2, 3, 4, 5" + - + input: + bytes: [ 0x78, 0x62, 0x21, 0x49 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldic. 2, 3, 4, 5" + - + input: + bytes: [ 0x78, 0x62, 0x21, 0x50 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldcl 2, 3, 4, 5" + - + input: + bytes: [ 0x78, 0x62, 0x21, 0x51 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldcl. 2, 3, 4, 5" + - + input: + bytes: [ 0x78, 0x62, 0x21, 0x52 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldcr 2, 3, 4, 5" + - + input: + bytes: [ 0x78, 0x62, 0x21, 0x53 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldcr. 2, 3, 4, 5" + - + input: + bytes: [ 0x78, 0x62, 0x21, 0x4c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldimi 2, 3, 4, 5" + - + input: + bytes: [ 0x78, 0x62, 0x21, 0x4d ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rldimi. 2, 3, 4, 5" + - + input: + bytes: [ 0x7c, 0x62, 0x20, 0x30 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slw 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x20, 0x31 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slw. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x24, 0x30 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srw 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x24, 0x31 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srw. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x26, 0x70 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srawi 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x26, 0x71 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srawi. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x26, 0x30 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sraw 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x26, 0x31 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sraw. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x20, 0x36 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sld 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x20, 0x37 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sld. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x24, 0x36 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srd 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x24, 0x37 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srd. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x26, 0x74 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sradi 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x26, 0x75 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sradi. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x26, 0x34 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srad 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x62, 0x26, 0x35 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srad. 2, 3, 4" + - + input: + bytes: [ 0x7c, 0x58, 0x93, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtspr 600, 2" + - + input: + bytes: [ 0x7c, 0x58, 0x92, 0xa6 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfspr 2, 600" + - + input: + bytes: [ 0x7c, 0x47, 0xb1, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtcrf 123, 2" + - + input: + bytes: [ 0x7c, 0x40, 0x00, 0x26 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfcr 2" + - + input: + bytes: [ 0x7c, 0x51, 0x01, 0x20 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mtocrf 16, 2" + - + input: + bytes: [ 0x7e, 0x10, 0x80, 0x26 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfocrf 16, 8" diff --git a/tests/MC/PowerPC/ppc64-operands.s.yaml b/tests/MC/PowerPC/ppc64-operands.s.yaml new file mode 100644 index 0000000000..d85e7ba1a2 --- /dev/null +++ b/tests/MC/PowerPC/ppc64-operands.s.yaml @@ -0,0 +1,275 @@ +test_cases: + - + input: + bytes: [ 0x7c, 0x22, 0x1a, 0x14 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "add 1, 2, 3" + - + input: + bytes: [ 0x7c, 0x22, 0x1a, 0x14 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "add 1, 2, 3" + - + input: + bytes: [ 0x7c, 0x00, 0x02, 0x14 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "add 0, 0, 0" + - + input: + bytes: [ 0x7f, 0xff, 0xfa, 0x14 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "add 31, 31, 31" + - + input: + bytes: [ 0x38, 0x20, 0x00, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "li 1, 0" + - + input: + bytes: [ 0x38, 0x22, 0x00, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addi 1, 2, 0" + - + input: + bytes: [ 0x38, 0x20, 0x80, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "li 1, -0x8000" + - + input: + bytes: [ 0x38, 0x20, 0x7f, 0xff ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "li 1, 0x7fff" + - + input: + bytes: [ 0x60, 0x41, 0x00, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ori 1, 2, 0" + - + input: + bytes: [ 0x60, 0x41, 0xff, 0xff ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ori 1, 2, 65535" + - + input: + bytes: [ 0x3c, 0x20, 0x00, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lis 1, 0" + - + input: + bytes: [ 0x3c, 0x20, 0xff, 0xff ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lis 1, -1" + - + input: + bytes: [ 0x80, 0x20, 0x00, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lwz 1, 0(0)" + - + input: + bytes: [ 0x80, 0x20, 0x00, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lwz 1, 0(0)" + - + input: + bytes: [ 0x80, 0x3f, 0x00, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lwz 1, 0(31)" + - + input: + bytes: [ 0x80, 0x3f, 0x00, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lwz 1, 0(31)" + - + input: + bytes: [ 0x80, 0x22, 0x80, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lwz 1, -32768(2)" + - + input: + bytes: [ 0x80, 0x22, 0x7f, 0xff ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lwz 1, 32767(2)" + - + input: + bytes: [ 0xe8, 0x20, 0x00, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld 1, 0(0)" + - + input: + bytes: [ 0xe8, 0x20, 0x00, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld 1, 0(0)" + - + input: + bytes: [ 0xe8, 0x3f, 0x00, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld 1, 0(31)" + - + input: + bytes: [ 0xe8, 0x3f, 0x00, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld 1, 0(31)" + - + input: + bytes: [ 0xe8, 0x22, 0x80, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld 1, -32768(2)" + - + input: + bytes: [ 0xe8, 0x22, 0x7f, 0xfc ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld 1, 32764(2)" + - + input: + bytes: [ 0xe8, 0x22, 0x00, 0x04 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld 1, 4(2)" + - + input: + bytes: [ 0xe8, 0x22, 0xff, 0xfc ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld 1, -4(2)" + - + input: + bytes: [ 0x48, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "b 1024" + skip_reason: "Note: The assemble accepts it with .+. But the disassembler just returns the scalar." + + - + input: + bytes: [ 0x48, 0x00, 0x04, 0x02 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ba 1024" + - + input: + bytes: [ 0x41, 0x82, 0x04, 0x00 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bt 2, 1024" + skip_reason: "Note: The assemble accepts it with .+. But the disassembler just returns the scalar." + + - + input: + bytes: [ 0x41, 0x82, 0x04, 0x02 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bta 2, 1024" diff --git a/tests/MC/PowerPC/qpx.s.yaml b/tests/MC/PowerPC/qpx.s.yaml new file mode 100644 index 0000000000..a3d99f02b4 --- /dev/null +++ b/tests/MC/PowerPC/qpx.s.yaml @@ -0,0 +1,1117 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x60, 0x2a, 0x10 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfabs q3, q5" + - + input: + bytes: [ 0x10, 0x60, 0x2a, 0x10 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfabs q3, q5" + - + input: + bytes: [ 0x10, 0x64, 0x28, 0x2a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfadd q3, q4, q5" + - + input: + bytes: [ 0x00, 0x64, 0x28, 0x2a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfadds q3, q4, q5" + - + input: + bytes: [ 0x10, 0x64, 0x2a, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfandc q3, q4, q5" + - + input: + bytes: [ 0x10, 0x64, 0x28, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfand q3, q4, q5" + - + input: + bytes: [ 0x10, 0x60, 0x2e, 0x9c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfcfid q3, q5" + - + input: + bytes: [ 0x00, 0x60, 0x2e, 0x9c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfcfids q3, q5" + - + input: + bytes: [ 0x10, 0x60, 0x2f, 0x9c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfcfidu q3, q5" + - + input: + bytes: [ 0x00, 0x60, 0x2f, 0x9c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfcfidus q3, q5" + - + input: + bytes: [ 0x10, 0x63, 0x18, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfclr q3" + - + input: + bytes: [ 0x10, 0x64, 0x28, 0x10 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfcpsgn q3, q4, q5" + - + input: + bytes: [ 0x10, 0x64, 0x22, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfctfb q3, q4" + - + input: + bytes: [ 0x10, 0x60, 0x2e, 0x5c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfctid q3, q5" + - + input: + bytes: [ 0x10, 0x60, 0x2f, 0x5c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfctidu q3, q5" + - + input: + bytes: [ 0x10, 0x60, 0x2f, 0x5e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfctiduz q3, q5" + - + input: + bytes: [ 0x10, 0x60, 0x2e, 0x5e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfctidz q3, q5" + - + input: + bytes: [ 0x10, 0x60, 0x28, 0x1c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfctiw q3, q5" + - + input: + bytes: [ 0x10, 0x60, 0x29, 0x1c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfctiwu q3, q5" + - + input: + bytes: [ 0x10, 0x60, 0x29, 0x1e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfctiwuz q3, q5" + - + input: + bytes: [ 0x10, 0x60, 0x28, 0x1e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfctiwz q3, q5" + - + input: + bytes: [ 0x10, 0x64, 0x2c, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfequ q3, q4, q5" + - + input: + bytes: [ 0x10, 0x64, 0x2e, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvflogical q3, q4, q5, 12" + - + input: + bytes: [ 0x10, 0x64, 0x29, 0xba ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfmadd q3, q4, q6, q5" + - + input: + bytes: [ 0x00, 0x64, 0x29, 0xba ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfmadds q3, q4, q6, q5" + - + input: + bytes: [ 0x10, 0x60, 0x28, 0x90 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfmr q3, q5" + - + input: + bytes: [ 0x10, 0x64, 0x29, 0xb8 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfmsub q3, q4, q6, q5" + - + input: + bytes: [ 0x00, 0x64, 0x29, 0xb8 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfmsubs q3, q4, q6, q5" + - + input: + bytes: [ 0x10, 0x64, 0x01, 0xb2 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfmul q3, q4, q6" + - + input: + bytes: [ 0x00, 0x64, 0x01, 0xb2 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfmuls q3, q4, q6" + - + input: + bytes: [ 0x10, 0x60, 0x29, 0x10 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfnabs q3, q5" + - + input: + bytes: [ 0x10, 0x64, 0x2f, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfnand q3, q4, q5" + - + input: + bytes: [ 0x10, 0x60, 0x28, 0x50 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfneg q3, q5" + - + input: + bytes: [ 0x10, 0x64, 0x29, 0xbe ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfnmadd q3, q4, q6, q5" + - + input: + bytes: [ 0x00, 0x64, 0x29, 0xbe ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfnmadds q3, q4, q6, q5" + - + input: + bytes: [ 0x10, 0x64, 0x29, 0xbc ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfnmsub q3, q4, q6, q5" + - + input: + bytes: [ 0x00, 0x64, 0x29, 0xbc ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfnmsubs q3, q4, q6, q5" + - + input: + bytes: [ 0x10, 0x64, 0x2c, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfnor q3, q4, q5" + - + input: + bytes: [ 0x10, 0x64, 0x25, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfnot q3, q4" + - + input: + bytes: [ 0x10, 0x64, 0x2e, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvforc q3, q4, q5" + - + input: + bytes: [ 0x10, 0x64, 0x2b, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfor q3, q4, q5" + - + input: + bytes: [ 0x10, 0x64, 0x29, 0x8c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfperm q3, q4, q5, q6" + - + input: + bytes: [ 0x10, 0x60, 0x28, 0x30 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfre q3, q5" + - + input: + bytes: [ 0x00, 0x60, 0x28, 0x30 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfres q3, q5" + - + input: + bytes: [ 0x10, 0x60, 0x2b, 0xd0 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfrim q3, q5" + - + input: + bytes: [ 0x10, 0x60, 0x2b, 0x10 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfrin q3, q5" + - + input: + bytes: [ 0x10, 0x60, 0x2b, 0x90 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfrip q3, q5" + - + input: + bytes: [ 0x10, 0x60, 0x2b, 0x50 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfriz q3, q5" + - + input: + bytes: [ 0x10, 0x60, 0x28, 0x18 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfrsp q3, q5" + - + input: + bytes: [ 0x10, 0x60, 0x28, 0x34 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfrsqrte q3, q5" + - + input: + bytes: [ 0x00, 0x60, 0x28, 0x34 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfrsqrtes q3, q5" + - + input: + bytes: [ 0x10, 0x64, 0x29, 0xae ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfsel q3, q4, q6, q5" + - + input: + bytes: [ 0x10, 0x63, 0x1f, 0x88 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfset q3" + - + input: + bytes: [ 0x10, 0x64, 0x28, 0x28 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfsub q3, q4, q5" + - + input: + bytes: [ 0x00, 0x64, 0x28, 0x28 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfsubs q3, q4, q5" + - + input: + bytes: [ 0x10, 0x64, 0x29, 0x92 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfxmadd q3, q4, q6, q5" + - + input: + bytes: [ 0x00, 0x64, 0x29, 0x92 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfxmadds q3, q4, q6, q5" + - + input: + bytes: [ 0x10, 0x64, 0x01, 0xa2 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfxmul q3, q4, q6" + - + input: + bytes: [ 0x00, 0x64, 0x01, 0xa2 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfxmuls q3, q4, q6" + - + input: + bytes: [ 0x10, 0x64, 0x2b, 0x08 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfxor q3, q4, q5" + - + input: + bytes: [ 0x10, 0x64, 0x29, 0x86 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfxxcpnmadd q3, q4, q6, q5" + - + input: + bytes: [ 0x00, 0x64, 0x29, 0x86 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfxxcpnmadds q3, q4, q6, q5" + - + input: + bytes: [ 0x10, 0x64, 0x29, 0x82 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfxxmadd q3, q4, q6, q5" + - + input: + bytes: [ 0x00, 0x64, 0x29, 0x82 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfxxmadds q3, q4, q6, q5" + - + input: + bytes: [ 0x10, 0x64, 0x29, 0x96 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfxxnpmadd q3, q4, q6, q5" + - + input: + bytes: [ 0x00, 0x64, 0x29, 0x96 ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvfxxnpmadds q3, q4, q6, q5" + - + input: + bytes: [ 0x7c, 0x69, 0x58, 0xcf ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfcduxa q3, r9, r11" + - + input: + bytes: [ 0x7c, 0x69, 0x58, 0xce ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfcdux q3, r9, r11" + - + input: + bytes: [ 0x7c, 0x6a, 0x58, 0x8f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfcdxa q3, r10, r11" + - + input: + bytes: [ 0x7c, 0x6a, 0x58, 0x8e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfcdx q3, r10, r11" + - + input: + bytes: [ 0x7c, 0x69, 0x58, 0x4f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfcsuxa q3, r9, r11" + - + input: + bytes: [ 0x7c, 0x69, 0x58, 0x4e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfcsux q3, r9, r11" + - + input: + bytes: [ 0x7c, 0x6a, 0x58, 0x0f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfcsxa q3, r10, r11" + - + input: + bytes: [ 0x7c, 0x6a, 0x58, 0x0e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfcsx q3, r10, r11" + - + input: + bytes: [ 0x7c, 0x69, 0x5c, 0xcf ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfduxa q3, r9, r11" + - + input: + bytes: [ 0x7c, 0x69, 0x5c, 0xce ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfdux q3, r9, r11" + - + input: + bytes: [ 0x7c, 0x6a, 0x5c, 0x8f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfdxa q3, r10, r11" + - + input: + bytes: [ 0x7c, 0x6a, 0x5c, 0x8e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfdx q3, r10, r11" + - + input: + bytes: [ 0x7c, 0x6a, 0x5e, 0xcf ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfiwaxa q3, r10, r11" + - + input: + bytes: [ 0x7c, 0x6a, 0x5e, 0xce ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfiwax q3, r10, r11" + - + input: + bytes: [ 0x7c, 0x6a, 0x5e, 0x8f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfiwzxa q3, r10, r11" + - + input: + bytes: [ 0x7c, 0x6a, 0x5e, 0x8e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfiwzx q3, r10, r11" + - + input: + bytes: [ 0x7c, 0x69, 0x5c, 0x4f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfsuxa q3, r9, r11" + - + input: + bytes: [ 0x7c, 0x69, 0x5c, 0x4e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfsux q3, r9, r11" + - + input: + bytes: [ 0x7c, 0x6a, 0x5c, 0x0f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfsxa q3, r10, r11" + - + input: + bytes: [ 0x7c, 0x6a, 0x5c, 0x0e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlfsx q3, r10, r11" + - + input: + bytes: [ 0x7c, 0x6a, 0x5c, 0x8c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlpcldx q3, r10, r11" + - + input: + bytes: [ 0x7c, 0x6a, 0x5c, 0x0c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlpclsx q3, r10, r11" + - + input: + bytes: [ 0x7c, 0x6a, 0x58, 0x8c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlpcrdx q3, r10, r11" + - + input: + bytes: [ 0x7c, 0x6a, 0x58, 0x0c ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvlpcrsx q3, r10, r11" + - + input: + bytes: [ 0x7c, 0x49, 0x59, 0xcf ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfcduxa q2, r9, r11" + - + input: + bytes: [ 0x7c, 0x49, 0x59, 0xcb ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfcduxia q2, r9, r11" + - + input: + bytes: [ 0x7c, 0x49, 0x59, 0xca ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfcduxi q2, r9, r11" + - + input: + bytes: [ 0x7c, 0x49, 0x59, 0xce ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfcdux q2, r9, r11" + - + input: + bytes: [ 0x7c, 0x4a, 0x59, 0x8f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfcdxa q2, r10, r11" + - + input: + bytes: [ 0x7c, 0x4a, 0x59, 0x8b ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfcdxia q2, r10, r11" + - + input: + bytes: [ 0x7c, 0x4a, 0x59, 0x8a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfcdxi q2, r10, r11" + - + input: + bytes: [ 0x7c, 0x4a, 0x59, 0x8e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfcdx q2, r10, r11" + - + input: + bytes: [ 0x7c, 0x49, 0x59, 0x4f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfcsuxa q2, r9, r11" + - + input: + bytes: [ 0x7c, 0x49, 0x59, 0x4b ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfcsuxia q2, r9, r11" + - + input: + bytes: [ 0x7c, 0x49, 0x59, 0x4a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfcsuxi q2, r9, r11" + - + input: + bytes: [ 0x7c, 0x49, 0x59, 0x4e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfcsux q2, r9, r11" + - + input: + bytes: [ 0x7c, 0x4a, 0x59, 0x0f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfcsxa q2, r10, r11" + - + input: + bytes: [ 0x7c, 0x4a, 0x59, 0x0b ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfcsxia q2, r10, r11" + - + input: + bytes: [ 0x7c, 0x4a, 0x59, 0x0a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfcsxi q2, r10, r11" + - + input: + bytes: [ 0x7c, 0x4a, 0x59, 0x0e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfcsx q2, r10, r11" + - + input: + bytes: [ 0x7c, 0x49, 0x5d, 0xcf ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfduxa q2, r9, r11" + - + input: + bytes: [ 0x7c, 0x49, 0x5d, 0xcb ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfduxia q2, r9, r11" + - + input: + bytes: [ 0x7c, 0x49, 0x5d, 0xca ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfduxi q2, r9, r11" + - + input: + bytes: [ 0x7c, 0x49, 0x5d, 0xce ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfdux q2, r9, r11" + - + input: + bytes: [ 0x7c, 0x4a, 0x5d, 0x8f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfdxa q2, r10, r11" + - + input: + bytes: [ 0x7c, 0x4a, 0x5d, 0x8b ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfdxia q2, r10, r11" + - + input: + bytes: [ 0x7c, 0x4a, 0x5d, 0x8a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfdxi q2, r10, r11" + - + input: + bytes: [ 0x7c, 0x4a, 0x5d, 0x8e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfdx q2, r10, r11" + - + input: + bytes: [ 0x7c, 0x4a, 0x5f, 0x8f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfiwxa q2, r10, r11" + - + input: + bytes: [ 0x7c, 0x4a, 0x5f, 0x8e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfiwx q2, r10, r11" + - + input: + bytes: [ 0x7c, 0x49, 0x5d, 0x4f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfsuxa q2, r9, r11" + - + input: + bytes: [ 0x7c, 0x49, 0x5d, 0x4b ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfsuxia q2, r9, r11" + - + input: + bytes: [ 0x7c, 0x49, 0x5d, 0x4a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfsuxi q2, r9, r11" + - + input: + bytes: [ 0x7c, 0x49, 0x5d, 0x4e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfsux q2, r9, r11" + - + input: + bytes: [ 0x7c, 0x4a, 0x5d, 0x0f ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfsxa q2, r10, r11" + - + input: + bytes: [ 0x7c, 0x4a, 0x5d, 0x0b ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfsxia q2, r10, r11" + - + input: + bytes: [ 0x7c, 0x4a, 0x5d, 0x0a ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfsxi q2, r10, r11" + - + input: + bytes: [ 0x7c, 0x4a, 0x5d, 0x0e ] + arch: "CS_ARCH_PPC" + options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qvstfsx q2, r10, r11" diff --git a/tests/MC/RISCV/insn-riscv32.s.yaml b/tests/MC/RISCV/insn-riscv32.s.yaml new file mode 100644 index 0000000000..b425cea48c --- /dev/null +++ b/tests/MC/RISCV/insn-riscv32.s.yaml @@ -0,0 +1,91 @@ +test_cases: + - + input: + bytes: [ 0x37, 0x34, 0x00, 0x00 ] + arch: "CS_ARCH_RISCV" + options: [ "CS_MODE_RISCV32" ] + expected: + insns: + - + asm_text: "lui s0, 3" + - + input: + bytes: [ 0x97, 0x82, 0x00, 0x00 ] + arch: "CS_ARCH_RISCV" + options: [ "CS_MODE_RISCV32" ] + expected: + insns: + - + asm_text: "auipc t0, 8" + - + input: + bytes: [ 0x2f, 0xae, 0xaa, 0x0a ] + arch: "CS_ARCH_RISCV" + options: [ "CS_MODE_RISCV32" ] + expected: + insns: + - + asm_text: "amoswap.w.rl t3, a0, (s5)" + - + input: + bytes: [ 0xe3, 0x1f, 0x31, 0x5e ] + arch: "CS_ARCH_RISCV" + options: [ "CS_MODE_RISCV32" ] + expected: + insns: + - + asm_text: "bne sp, gp, 0xdfe" + - + input: + bytes: [ 0x73, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_RISCV" + options: [ "CS_MODE_RISCV32" ] + expected: + insns: + - + asm_text: "ecall" + - + input: + bytes: [ 0x33, 0x00, 0x31, 0x02 ] + arch: "CS_ARCH_RISCV" + options: [ "CS_MODE_RISCV32" ] + expected: + insns: + - + asm_text: "mul zero, sp, gp" + - + input: + bytes: [ 0x53, 0x00, 0x31, 0x28 ] + arch: "CS_ARCH_RISCV" + options: [ "CS_MODE_RISCV32" ] + expected: + insns: + - + asm_text: "fmin.s ft0, ft2, ft3" + - + input: + bytes: [ 0x53, 0x10, 0x31, 0x2a ] + arch: "CS_ARCH_RISCV" + options: [ "CS_MODE_RISCV32" ] + expected: + insns: + - + asm_text: "fmax.d ft0, ft2, ft3" + - + input: + bytes: [ 0x27, 0xaa, 0x6a, 0x00 ] + arch: "CS_ARCH_RISCV" + options: [ "CS_MODE_RISCV32" ] + expected: + insns: + - + asm_text: "fsw ft6, 0x14(s5)" + - + input: + bytes: [ 0xef, 0xf0, 0x1f, 0xff ] + arch: "CS_ARCH_RISCV" + options: [ "CS_MODE_RISCV32" ] + expected: + insns: + - + asm_text: "jal -0x10" diff --git a/tests/MC/RISCV/insn-riscv64.s.yaml b/tests/MC/RISCV/insn-riscv64.s.yaml new file mode 100644 index 0000000000..9fdbb19363 --- /dev/null +++ b/tests/MC/RISCV/insn-riscv64.s.yaml @@ -0,0 +1,55 @@ +test_cases: + - + input: + bytes: [ 0x13, 0x04, 0xa8, 0x7a ] + arch: "CS_ARCH_RISCV" + options: [ "CS_MODE_RISCV64" ] + expected: + insns: + - + asm_text: "addi s0, a6, 0x7aa" + - + input: + bytes: [ 0x1b, 0x8e, 0xaa, 0x2a ] + arch: "CS_ARCH_RISCV" + options: [ "CS_MODE_RISCV64" ] + expected: + insns: + - + asm_text: "addiw t3, s5, 0x2aa" + - + input: + bytes: [ 0x2f, 0xbe, 0xaa, 0x0a ] + arch: "CS_ARCH_RISCV" + options: [ "CS_MODE_RISCV64" ] + expected: + insns: + - + asm_text: "amoswap.d.rl t3, a0, (s5)" + - + input: + bytes: [ 0x3b, 0x00, 0x31, 0x02 ] + arch: "CS_ARCH_RISCV" + options: [ "CS_MODE_RISCV64" ] + expected: + insns: + - + asm_text: "mulw zero, sp, gp" + - + input: + bytes: [ 0x53, 0xa0, 0x31, 0xd0 ] + arch: "CS_ARCH_RISCV" + options: [ "CS_MODE_RISCV64" ] + expected: + insns: + - + asm_text: "fcvt.s.lu ft0, gp, rdn" + - + input: + bytes: [ 0x53, 0x81, 0x01, 0xf2 ] + arch: "CS_ARCH_RISCV" + options: [ "CS_MODE_RISCV64" ] + expected: + insns: + - + asm_text: "fmv.d.x ft2, gp" diff --git a/tests/MC/Sparc/sparc-alu-instructions.s.yaml b/tests/MC/Sparc/sparc-alu-instructions.s.yaml new file mode 100644 index 0000000000..7e777e3c20 --- /dev/null +++ b/tests/MC/Sparc/sparc-alu-instructions.s.yaml @@ -0,0 +1,415 @@ +test_cases: + - + input: + bytes: [ 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "add %g0, %g0, %g0" + - + input: + bytes: [ 0x86, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "add %g1, %g2, %g3" + - + input: + bytes: [ 0xa0, 0x02, 0x00, 0x09 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "add %o0, %o1, %l0" + - + input: + bytes: [ 0xa0, 0x02, 0x20, 0x0a ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "add %o0, 10, %l0" + - + input: + bytes: [ 0x86, 0x80, 0x40, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addcc %g1, %g2, %g3" + - + input: + bytes: [ 0x86, 0xc0, 0x40, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addxcc %g1, %g2, %g3" + - + input: + bytes: [ 0x86, 0x70, 0x40, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "udiv %g1, %g2, %g3" + - + input: + bytes: [ 0x86, 0x78, 0x40, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdiv %g1, %g2, %g3" + - + input: + bytes: [ 0x86, 0x08, 0x40, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "and %g1, %g2, %g3" + - + input: + bytes: [ 0x86, 0x28, 0x40, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "andn %g1, %g2, %g3" + - + input: + bytes: [ 0x86, 0x10, 0x40, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "or %g1, %g2, %g3" + - + input: + bytes: [ 0x86, 0x30, 0x40, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "orn %g1, %g2, %g3" + - + input: + bytes: [ 0x86, 0x18, 0x40, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xor %g1, %g2, %g3" + - + input: + bytes: [ 0x86, 0x38, 0x40, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xnor %g1, %g2, %g3" + - + input: + bytes: [ 0x86, 0x50, 0x40, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "umul %g1, %g2, %g3" + - + input: + bytes: [ 0x86, 0x58, 0x40, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "smul %g1, %g2, %g3" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x21, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sethi 10, %l0" + - + input: + bytes: [ 0x87, 0x28, 0x40, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sll %g1, %g2, %g3" + - + input: + bytes: [ 0x87, 0x28, 0x60, 0x1f ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sll %g1, 31, %g3" + - + input: + bytes: [ 0x87, 0x30, 0x40, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srl %g1, %g2, %g3" + - + input: + bytes: [ 0x87, 0x30, 0x60, 0x1f ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srl %g1, 31, %g3" + - + input: + bytes: [ 0x87, 0x38, 0x40, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sra %g1, %g2, %g3" + - + input: + bytes: [ 0x87, 0x38, 0x60, 0x1f ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sra %g1, 31, %g3" + - + input: + bytes: [ 0x86, 0x20, 0x40, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sub %g1, %g2, %g3" + - + input: + bytes: [ 0x86, 0xa0, 0x40, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subcc %g1, %g2, %g3" + - + input: + bytes: [ 0x86, 0xe0, 0x40, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subxcc %g1, %g2, %g3" + - + input: + bytes: [ 0x86, 0x10, 0x00, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mov %g1, %g3" + - + input: + bytes: [ 0x86, 0x10, 0x20, 0xff ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mov 0xff, %g3" + - + input: + bytes: [ 0x81, 0xe8, 0x00, 0x00 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "restore" + - + input: + bytes: [ 0x86, 0x40, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "addx %g2, %g1, %g3" + - + input: + bytes: [ 0x86, 0x60, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "subx %g2, %g1, %g3" + - + input: + bytes: [ 0x86, 0xd0, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "umulcc %g2, %g1, %g3" + - + input: + bytes: [ 0x86, 0xd8, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "smulcc %g2, %g1, %g3" + - + input: + bytes: [ 0x86, 0xf0, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "udivcc %g2, %g1, %g3" + - + input: + bytes: [ 0x86, 0xf8, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdivcc %g2, %g1, %g3" + - + input: + bytes: [ 0x86, 0x88, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "andcc %g2, %g1, %g3" + - + input: + bytes: [ 0x86, 0xa8, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "andncc %g2, %g1, %g3" + - + input: + bytes: [ 0x86, 0x90, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "orcc %g2, %g1, %g3" + - + input: + bytes: [ 0x86, 0xb0, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "orncc %g2, %g1, %g3" + - + input: + bytes: [ 0x86, 0x98, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xorcc %g2, %g1, %g3" + - + input: + bytes: [ 0x86, 0xb8, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xnorcc %g2, %g1, %g3" + - + input: + bytes: [ 0x87, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "taddcc %g2, %g1, %g3" + - + input: + bytes: [ 0x87, 0x08, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tsubcc %g2, %g1, %g3" + - + input: + bytes: [ 0x87, 0x10, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "taddcctv %g2, %g1, %g3" + - + input: + bytes: [ 0x87, 0x18, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tsubcctv %g2, %g1, %g3" diff --git a/tests/MC/Sparc/sparc-atomic-instructions.s.yaml b/tests/MC/Sparc/sparc-atomic-instructions.s.yaml new file mode 100644 index 0000000000..44a1c97212 --- /dev/null +++ b/tests/MC/Sparc/sparc-atomic-instructions.s.yaml @@ -0,0 +1,55 @@ +test_cases: + - + input: + bytes: [ 0x81, 0x43, 0xe0, 0x0f ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "membar 15" + - + input: + bytes: [ 0x81, 0x43, 0xc0, 0x00 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stbar" + - + input: + bytes: [ 0xd4, 0x7e, 0x00, 0x16 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "swap [%i0+%l6], %o2" + - + input: + bytes: [ 0xd4, 0x7e, 0x20, 0x20 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "swap [%i0+32], %o2" + - + input: + bytes: [ 0xd5, 0xe6, 0x10, 0x16 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cas [%i0], %l6, %o2" + - + input: + bytes: [ 0xd5, 0xf6, 0x10, 0x16 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "casx [%i0], %l6, %o2" diff --git a/tests/MC/Sparc/sparc-ctrl-instructions.s.yaml b/tests/MC/Sparc/sparc-ctrl-instructions.s.yaml new file mode 100644 index 0000000000..f99104a8d6 --- /dev/null +++ b/tests/MC/Sparc/sparc-ctrl-instructions.s.yaml @@ -0,0 +1,91 @@ +test_cases: + - + input: + bytes: [ 0x9f, 0xc0, 0x40, 0x1a ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "call %g1+%i2" + - + input: + bytes: [ 0x9f, 0xc2, 0x60, 0x08 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "call %o1+8" + - + input: + bytes: [ 0x9f, 0xc0, 0x60, 0x00 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "call %g1" + - + input: + bytes: [ 0x81, 0xc0, 0x40, 0x1a ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "jmp %g1+%i2" + - + input: + bytes: [ 0x81, 0xc2, 0x60, 0x08 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "jmp %o1+8" + - + input: + bytes: [ 0x81, 0xc0, 0x60, 0x00 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "jmp %g1" + - + input: + bytes: [ 0x85, 0xc0, 0x40, 0x1a ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "jmpl %g1+%i2, %g2" + - + input: + bytes: [ 0x85, 0xc2, 0x60, 0x08 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "jmpl %o1+8, %g2" + - + input: + bytes: [ 0x85, 0xc0, 0x60, 0x00 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "jmpl %g1, %g2" + - + input: + bytes: [ 0x81, 0xcf, 0xe0, 0x08 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rett %i7+8" diff --git a/tests/MC/Sparc/sparc-fp-instructions.s.yaml b/tests/MC/Sparc/sparc-fp-instructions.s.yaml new file mode 100644 index 0000000000..fbd0a2419c --- /dev/null +++ b/tests/MC/Sparc/sparc-fp-instructions.s.yaml @@ -0,0 +1,469 @@ +test_cases: + - + input: + bytes: [ 0x89, 0xa0, 0x18, 0x80 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fitos %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x19, 0x00 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fitod %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x19, 0x80 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fitoq %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x1a, 0x20 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fstoi %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x1a, 0x40 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fdtoi %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x1a, 0x60 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fqtoi %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x19, 0x20 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fstod %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x19, 0xa0 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fstoq %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x18, 0xc0 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fdtos %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x19, 0xc0 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fdtoq %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x18, 0xe0 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fqtos %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x19, 0x60 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fqtod %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x00, 0x20 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovs %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x00, 0x40 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovd %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x00, 0x60 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovq %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x00, 0xa0 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fnegs %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x00, 0xc0 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fnegd %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x00, 0xe0 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fnegq %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x01, 0x20 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fabss %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x01, 0x40 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fabsd %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x01, 0x60 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fabsq %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x05, 0x20 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsqrts %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x05, 0x40 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsqrtd %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x05, 0x60 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsqrtq %f0, %f4" + - + input: + bytes: [ 0x91, 0xa0, 0x08, 0x24 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fadds %f0, %f4, %f8" + - + input: + bytes: [ 0x91, 0xa0, 0x08, 0x44 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "faddd %f0, %f4, %f8" + - + input: + bytes: [ 0x91, 0xa0, 0x08, 0x64 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "faddq %f0, %f4, %f8" + - + input: + bytes: [ 0xbf, 0xa0, 0x48, 0x43 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "faddd %f32, %f34, %f62" + - + input: + bytes: [ 0xbb, 0xa0, 0x48, 0x65 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "faddq %f32, %f36, %f60" + - + input: + bytes: [ 0x91, 0xa0, 0x08, 0xa4 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsubs %f0, %f4, %f8" + - + input: + bytes: [ 0x91, 0xa0, 0x08, 0xc4 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsubd %f0, %f4, %f8" + - + input: + bytes: [ 0x91, 0xa0, 0x08, 0xe4 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsubq %f0, %f4, %f8" + - + input: + bytes: [ 0x91, 0xa0, 0x09, 0x24 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmuls %f0, %f4, %f8" + - + input: + bytes: [ 0x91, 0xa0, 0x09, 0x44 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmuld %f0, %f4, %f8" + - + input: + bytes: [ 0x91, 0xa0, 0x09, 0x64 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmulq %f0, %f4, %f8" + - + input: + bytes: [ 0x91, 0xa0, 0x0d, 0x24 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fsmuld %f0, %f4, %f8" + - + input: + bytes: [ 0x91, 0xa0, 0x0d, 0xc4 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fdmulq %f0, %f4, %f8" + - + input: + bytes: [ 0x91, 0xa0, 0x09, 0xa4 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fdivs %f0, %f4, %f8" + - + input: + bytes: [ 0x91, 0xa0, 0x09, 0xc4 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fdivd %f0, %f4, %f8" + - + input: + bytes: [ 0x91, 0xa0, 0x09, 0xe4 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fdivq %f0, %f4, %f8" + - + input: + bytes: [ 0x85, 0xa8, 0x0a, 0x24 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmps %fcc2, %f0, %f4" + - + input: + bytes: [ 0x85, 0xa8, 0x0a, 0x44 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmpd %fcc2, %f0, %f4" + - + input: + bytes: [ 0x85, 0xa8, 0x0a, 0x64 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmpq %fcc2, %f0, %f4" + - + input: + bytes: [ 0x85, 0xa8, 0x0a, 0xa4 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmpes %fcc2, %f0, %f4" + - + input: + bytes: [ 0x85, 0xa8, 0x0a, 0xc4 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmped %fcc2, %f0, %f4" + - + input: + bytes: [ 0x85, 0xa8, 0x0a, 0xe4 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmpeq %fcc2, %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x10, 0x80 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fxtos %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x11, 0x00 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fxtod %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x11, 0x80 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fxtoq %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x10, 0x20 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fstox %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x10, 0x40 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fdtox %f0, %f4" + - + input: + bytes: [ 0x89, 0xa0, 0x10, 0x60 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fqtox %f0, %f4" diff --git a/tests/MC/Sparc/sparc-mem-instructions.s.yaml b/tests/MC/Sparc/sparc-mem-instructions.s.yaml new file mode 100644 index 0000000000..e05445418f --- /dev/null +++ b/tests/MC/Sparc/sparc-mem-instructions.s.yaml @@ -0,0 +1,217 @@ +test_cases: + - + input: + bytes: [ 0xd4, 0x4e, 0x00, 0x16 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldsb [%i0+%l6], %o2" + - + input: + bytes: [ 0xd4, 0x4e, 0x20, 0x20 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldsb [%i0+32], %o2" + - + input: + bytes: [ 0xd8, 0x48, 0x60, 0x00 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldsb [%g1], %o4" + - + input: + bytes: [ 0xd4, 0x56, 0x00, 0x16 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldsh [%i0+%l6], %o2" + - + input: + bytes: [ 0xd4, 0x56, 0x20, 0x20 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldsh [%i0+32], %o2" + - + input: + bytes: [ 0xd8, 0x50, 0x60, 0x00 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldsh [%g1], %o4" + - + input: + bytes: [ 0xd4, 0x0e, 0x00, 0x16 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldub [%i0+%l6], %o2" + - + input: + bytes: [ 0xd4, 0x0e, 0x20, 0x20 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldub [%i0+32], %o2" + - + input: + bytes: [ 0xd4, 0x08, 0x60, 0x00 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldub [%g1], %o2" + - + input: + bytes: [ 0xd4, 0x16, 0x00, 0x16 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lduh [%i0+%l6], %o2" + - + input: + bytes: [ 0xd4, 0x16, 0x20, 0x20 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lduh [%i0+32], %o2" + - + input: + bytes: [ 0xd4, 0x10, 0x60, 0x00 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lduh [%g1], %o2" + - + input: + bytes: [ 0xd4, 0x06, 0x00, 0x16 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld [%i0+%l6], %o2" + - + input: + bytes: [ 0xd4, 0x06, 0x20, 0x20 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld [%i0+32], %o2" + - + input: + bytes: [ 0xd4, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld [%g1], %o2" + - + input: + bytes: [ 0xd4, 0x2e, 0x00, 0x16 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stb %o2, [%i0+%l6]" + - + input: + bytes: [ 0xd4, 0x2e, 0x20, 0x20 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stb %o2, [%i0+32]" + - + input: + bytes: [ 0xd4, 0x28, 0x60, 0x00 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stb %o2, [%g1]" + - + input: + bytes: [ 0xd4, 0x36, 0x00, 0x16 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sth %o2, [%i0+%l6]" + - + input: + bytes: [ 0xd4, 0x36, 0x20, 0x20 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sth %o2, [%i0+32]" + - + input: + bytes: [ 0xd4, 0x30, 0x60, 0x00 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sth %o2, [%g1]" + - + input: + bytes: [ 0xd4, 0x26, 0x00, 0x16 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "st %o2, [%i0+%l6]" + - + input: + bytes: [ 0xd4, 0x26, 0x20, 0x20 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "st %o2, [%i0+32]" + - + input: + bytes: [ 0xd4, 0x20, 0x60, 0x00 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "st %o2, [%g1]" diff --git a/tests/MC/Sparc/sparc-vis.s.yaml b/tests/MC/Sparc/sparc-vis.s.yaml new file mode 100644 index 0000000000..617945899a --- /dev/null +++ b/tests/MC/Sparc/sparc-vis.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0xbf, 0xb0, 0x0c, 0x20 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fzeros %f31" diff --git a/tests/MC/Sparc/sparc64-alu-instructions.s.yaml b/tests/MC/Sparc/sparc64-alu-instructions.s.yaml new file mode 100644 index 0000000000..f0a107fcb9 --- /dev/null +++ b/tests/MC/Sparc/sparc64-alu-instructions.s.yaml @@ -0,0 +1,109 @@ +test_cases: + - + input: + bytes: [ 0xb1, 0x28, 0x50, 0x1a ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllx %g1, %i2, %i0" + - + input: + bytes: [ 0xb1, 0x28, 0x70, 0x3f ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllx %g1, 63, %i0" + - + input: + bytes: [ 0xb1, 0x30, 0x50, 0x1a ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlx %g1, %i2, %i0" + - + input: + bytes: [ 0xb1, 0x30, 0x70, 0x3f ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlx %g1, 63, %i0" + - + input: + bytes: [ 0xb1, 0x38, 0x50, 0x1a ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srax %g1, %i2, %i0" + - + input: + bytes: [ 0xb1, 0x38, 0x70, 0x3f ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srax %g1, 63, %i0" + - + input: + bytes: [ 0xb0, 0x48, 0x40, 0x1a ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulx %g1, %i2, %i0" + - + input: + bytes: [ 0xb0, 0x48, 0x60, 0x3f ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mulx %g1, 63, %i0" + - + input: + bytes: [ 0xb1, 0x68, 0x40, 0x1a ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdivx %g1, %i2, %i0" + - + input: + bytes: [ 0xb1, 0x68, 0x60, 0x3f ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdivx %g1, 63, %i0" + - + input: + bytes: [ 0xb0, 0x68, 0x40, 0x1a ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "udivx %g1, %i2, %i0" + - + input: + bytes: [ 0xb0, 0x68, 0x60, 0x3f ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "udivx %g1, 63, %i0" diff --git a/tests/MC/Sparc/sparc64-ctrl-instructions.s.yaml b/tests/MC/Sparc/sparc64-ctrl-instructions.s.yaml new file mode 100644 index 0000000000..846de9602b --- /dev/null +++ b/tests/MC/Sparc/sparc64-ctrl-instructions.s.yaml @@ -0,0 +1,901 @@ +test_cases: + - + input: + bytes: [ 0x85, 0x66, 0x40, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movne %icc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x64, 0x40, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "move %icc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x66, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movg %icc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x64, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movle %icc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x66, 0xc0, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movge %icc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x64, 0xc0, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movl %icc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x67, 0x00, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movgu %icc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x65, 0x00, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movleu %icc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x67, 0x40, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movcc %icc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x65, 0x40, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movcs %icc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x67, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movpos %icc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x65, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movneg %icc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x67, 0xc0, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movvc %icc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x65, 0xc0, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movvs %icc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x66, 0x50, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movne %xcc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x64, 0x50, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "move %xcc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x66, 0x90, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movg %xcc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x64, 0x90, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movle %xcc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x66, 0xd0, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movge %xcc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x64, 0xd0, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movl %xcc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x67, 0x10, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movgu %xcc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x65, 0x10, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movleu %xcc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x67, 0x50, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movcc %xcc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x65, 0x50, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movcs %xcc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x67, 0x90, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movpos %xcc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x65, 0x90, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movneg %xcc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x67, 0xd0, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movvc %xcc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x65, 0xd0, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movvs %xcc, %g1, %g2" + - + input: + bytes: [ 0x85, 0x61, 0xc0, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movu %fcc0, %g1, %g2" + - + input: + bytes: [ 0x85, 0x61, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movg %fcc0, %g1, %g2" + - + input: + bytes: [ 0x85, 0x61, 0x40, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movug %fcc0, %g1, %g2" + - + input: + bytes: [ 0x85, 0x61, 0x00, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movl %fcc0, %g1, %g2" + - + input: + bytes: [ 0x85, 0x60, 0xc0, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movul %fcc0, %g1, %g2" + - + input: + bytes: [ 0x85, 0x60, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movlg %fcc0, %g1, %g2" + - + input: + bytes: [ 0x85, 0x60, 0x40, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movne %fcc0, %g1, %g2" + - + input: + bytes: [ 0x85, 0x62, 0x40, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "move %fcc0, %g1, %g2" + - + input: + bytes: [ 0x85, 0x62, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movue %fcc0, %g1, %g2" + - + input: + bytes: [ 0x85, 0x62, 0xc0, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movge %fcc0, %g1, %g2" + - + input: + bytes: [ 0x85, 0x63, 0x00, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movuge %fcc0, %g1, %g2" + - + input: + bytes: [ 0x85, 0x63, 0x40, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movle %fcc0, %g1, %g2" + - + input: + bytes: [ 0x85, 0x63, 0x80, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movule %fcc0, %g1, %g2" + - + input: + bytes: [ 0x85, 0x63, 0xc0, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movo %fcc0, %g1, %g2" + - + input: + bytes: [ 0x85, 0xaa, 0x60, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsne %icc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa8, 0x60, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovse %icc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xaa, 0xa0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsg %icc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa8, 0xa0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsle %icc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xaa, 0xe0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsge %icc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa8, 0xe0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsl %icc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xab, 0x20, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsgu %icc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa9, 0x20, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsleu %icc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xab, 0x60, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovscc %icc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa9, 0x60, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovscs %icc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xab, 0xa0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovspos %icc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa9, 0xa0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsneg %icc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xab, 0xe0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsvc %icc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa9, 0xe0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsvs %icc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xaa, 0x70, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsne %xcc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa8, 0x70, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovse %xcc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xaa, 0xb0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsg %xcc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa8, 0xb0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsle %xcc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xaa, 0xf0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsge %xcc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa8, 0xf0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsl %xcc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xab, 0x30, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsgu %xcc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa9, 0x30, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsleu %xcc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xab, 0x70, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovscc %xcc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa9, 0x70, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovscs %xcc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xab, 0xb0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovspos %xcc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa9, 0xb0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsneg %xcc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xab, 0xf0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsvc %xcc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa9, 0xf0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsvs %xcc, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa9, 0xc0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsu %fcc0, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa9, 0x80, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsg %fcc0, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa9, 0x40, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsug %fcc0, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa9, 0x00, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsl %fcc0, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa8, 0xc0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsul %fcc0, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa8, 0x80, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovslg %fcc0, %f1, %f2" + - + input: + bytes: [ 0x85, 0xa8, 0x40, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsne %fcc0, %f1, %f2" + - + input: + bytes: [ 0x85, 0xaa, 0x40, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovse %fcc0, %f1, %f2" + - + input: + bytes: [ 0x85, 0xaa, 0x80, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsue %fcc0, %f1, %f2" + - + input: + bytes: [ 0x85, 0xaa, 0xc0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsge %fcc0, %f1, %f2" + - + input: + bytes: [ 0x85, 0xab, 0x00, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsuge %fcc0, %f1, %f2" + - + input: + bytes: [ 0x85, 0xab, 0x40, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsle %fcc0, %f1, %f2" + - + input: + bytes: [ 0x85, 0xab, 0x80, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsule %fcc0, %f1, %f2" + - + input: + bytes: [ 0x85, 0xab, 0xc0, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovso %fcc0, %f1, %f2" + - + input: + bytes: [ 0x85, 0x61, 0xc8, 0x01 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movu %fcc1, %g1, %g2" + - + input: + bytes: [ 0x85, 0xa9, 0x90, 0x21 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovsg %fcc2, %f1, %f2" + - + input: + bytes: [ 0x87, 0x78, 0x44, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movrz %g1, %g2, %g3" + - + input: + bytes: [ 0x87, 0x78, 0x48, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movrlez %g1, %g2, %g3" + - + input: + bytes: [ 0x87, 0x78, 0x4c, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movrlz %g1, %g2, %g3" + - + input: + bytes: [ 0x87, 0x78, 0x54, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movrnz %g1, %g2, %g3" + - + input: + bytes: [ 0x87, 0x78, 0x58, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movrgz %g1, %g2, %g3" + - + input: + bytes: [ 0x87, 0x78, 0x5c, 0x02 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "movrgez %g1, %g2, %g3" + - + input: + bytes: [ 0x87, 0xa8, 0x44, 0xa2 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovrsz %g1, %f2, %f3" + - + input: + bytes: [ 0x87, 0xa8, 0x48, 0xa2 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovrslez %g1, %f2, %f3" + - + input: + bytes: [ 0x87, 0xa8, 0x4c, 0xa2 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovrslz %g1, %f2, %f3" + - + input: + bytes: [ 0x87, 0xa8, 0x54, 0xa2 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovrsnz %g1, %f2, %f3" + - + input: + bytes: [ 0x87, 0xa8, 0x58, 0xa2 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovrsgz %g1, %f2, %f3" + - + input: + bytes: [ 0x87, 0xa8, 0x5c, 0xa2 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fmovrsgez %g1, %f2, %f3" + - + input: + bytes: [ 0x81, 0xcf, 0xe0, 0x08 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rett %i7+8" + - + input: + bytes: [ 0x83, 0xd0, 0x30, 0x03 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "te %xcc, %g0 + 3" diff --git a/tests/MC/Sparc/sparcv8-instructions.s.yaml b/tests/MC/Sparc/sparcv8-instructions.s.yaml new file mode 100644 index 0000000000..c233c93862 --- /dev/null +++ b/tests/MC/Sparc/sparcv8-instructions.s.yaml @@ -0,0 +1,55 @@ +test_cases: + - + input: + bytes: [ 0x81, 0xa8, 0x0a, 0x24 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmps %f0, %f4" + - + input: + bytes: [ 0x81, 0xa8, 0x0a, 0x44 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmpd %f0, %f4" + - + input: + bytes: [ 0x81, 0xa8, 0x0a, 0x64 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmpq %f0, %f4" + - + input: + bytes: [ 0x81, 0xa8, 0x0a, 0xa4 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmpes %f0, %f4" + - + input: + bytes: [ 0x81, 0xa8, 0x0a, 0xc4 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmped %f0, %f4" + - + input: + bytes: [ 0x81, 0xa8, 0x0a, 0xe4 ] + arch: "CS_ARCH_SPARC" + options: [ "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fcmpeq %f0, %f4" diff --git a/tests/MC/SystemZ/insn-good-z196.s.yaml b/tests/MC/SystemZ/insn-good-z196.s.yaml new file mode 100644 index 0000000000..036a7344af --- /dev/null +++ b/tests/MC/SystemZ/insn-good-z196.s.yaml @@ -0,0 +1,5149 @@ +test_cases: + - + input: + bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aghik %r0, %r0, -32768" + - + input: + bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aghik %r0, %r0, -1" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aghik %r0, %r0, 0" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x01, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aghik %r0, %r0, 1" + - + input: + bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aghik %r0, %r0, 32767" + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aghik %r0, %r15, 0" + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aghik %r15, %r0, 0" + - + input: + bytes: [ 0xec, 0x78, 0xff, 0xf0, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aghik %r7, %r8, -16" + - + input: + bytes: [ 0xb9, 0xe8, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agrk %r0, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xe8, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agrk %r0, %r0, %r15" + - + input: + bytes: [ 0xb9, 0xe8, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agrk %r0, %r15, %r0" + - + input: + bytes: [ 0xb9, 0xe8, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agrk %r15, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xe8, 0x90, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agrk %r7, %r8, %r9" + - + input: + bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xd8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahik %r0, %r0, -32768" + - + input: + bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xd8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahik %r0, %r0, -1" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xd8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahik %r0, %r0, 0" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x01, 0x00, 0xd8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahik %r0, %r0, 1" + - + input: + bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xd8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahik %r0, %r0, 32767" + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xd8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahik %r0, %r15, 0" + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xd8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahik %r15, %r0, 0" + - + input: + bytes: [ 0xec, 0x78, 0xff, 0xf0, 0x00, 0xd8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahik %r7, %r8, -16" + - + input: + bytes: [ 0xcc, 0x08, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aih %r0, -2147483648" + - + input: + bytes: [ 0xcc, 0x08, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aih %r0, -1" + - + input: + bytes: [ 0xcc, 0x08, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aih %r0, 0" + - + input: + bytes: [ 0xcc, 0x08, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aih %r0, 1" + - + input: + bytes: [ 0xcc, 0x08, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aih %r0, 2147483647" + - + input: + bytes: [ 0xcc, 0xf8, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aih %r15, 0" + - + input: + bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xdb ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alghsik %r0, %r0, -32768" + - + input: + bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xdb ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alghsik %r0, %r0, -1" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xdb ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alghsik %r0, %r0, 0" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x01, 0x00, 0xdb ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alghsik %r0, %r0, 1" + - + input: + bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xdb ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alghsik %r0, %r0, 32767" + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xdb ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alghsik %r0, %r15, 0" + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xdb ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alghsik %r15, %r0, 0" + - + input: + bytes: [ 0xec, 0x78, 0xff, 0xf0, 0x00, 0xdb ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alghsik %r7, %r8, -16" + - + input: + bytes: [ 0xb9, 0xea, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algrk %r0, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xea, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algrk %r0, %r0, %r15" + - + input: + bytes: [ 0xb9, 0xea, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algrk %r0, %r15, %r0" + - + input: + bytes: [ 0xb9, 0xea, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algrk %r15, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xea, 0x90, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algrk %r7, %r8, %r9" + - + input: + bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xda ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alhsik %r0, %r0, -32768" + - + input: + bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xda ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alhsik %r0, %r0, -1" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xda ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alhsik %r0, %r0, 0" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x01, 0x00, 0xda ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alhsik %r0, %r0, 1" + - + input: + bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xda ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alhsik %r0, %r0, 32767" + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xda ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alhsik %r0, %r15, 0" + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xda ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alhsik %r15, %r0, 0" + - + input: + bytes: [ 0xec, 0x78, 0xff, 0xf0, 0x00, 0xda ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alhsik %r7, %r8, -16" + - + input: + bytes: [ 0xb9, 0xfa, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alrk %r0, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xfa, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alrk %r0, %r0, %r15" + - + input: + bytes: [ 0xb9, 0xfa, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alrk %r0, %r15, %r0" + - + input: + bytes: [ 0xb9, 0xfa, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alrk %r15, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xfa, 0x90, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alrk %r7, %r8, %r9" + - + input: + bytes: [ 0xb9, 0xf8, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ark %r0, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xf8, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ark %r0, %r0, %r15" + - + input: + bytes: [ 0xb9, 0xf8, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ark %r0, %r15, %r0" + - + input: + bytes: [ 0xb9, 0xf8, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ark %r15, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xf8, 0x90, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ark %r7, %r8, %r9" + - + input: + bytes: [ 0xb3, 0x91, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdlfbr %f0, 0, %r0, 0" + - + input: + bytes: [ 0xb3, 0x91, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdlfbr %f0, 0, %r0, 15" + - + input: + bytes: [ 0xb3, 0x91, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdlfbr %f0, 0, %r15, 0" + - + input: + bytes: [ 0xb3, 0x91, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdlfbr %f0, 15, %r0, 0" + - + input: + bytes: [ 0xb3, 0x91, 0x57, 0x46 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdlfbr %f4, 5, %r6, 7" + - + input: + bytes: [ 0xb3, 0x91, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdlfbr %f15, 0, %r0, 0" + - + input: + bytes: [ 0xb3, 0xa1, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdlgbr %f0, 0, %r0, 0" + - + input: + bytes: [ 0xb3, 0xa1, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdlgbr %f0, 0, %r0, 15" + - + input: + bytes: [ 0xb3, 0xa1, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdlgbr %f0, 0, %r15, 0" + - + input: + bytes: [ 0xb3, 0xa1, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdlgbr %f0, 15, %r0, 0" + - + input: + bytes: [ 0xb3, 0xa1, 0x57, 0x46 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdlgbr %f4, 5, %r6, 7" + - + input: + bytes: [ 0xb3, 0xa1, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdlgbr %f15, 0, %r0, 0" + - + input: + bytes: [ 0xb3, 0x90, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "celfbr %f0, 0, %r0, 0" + - + input: + bytes: [ 0xb3, 0x90, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "celfbr %f0, 0, %r0, 15" + - + input: + bytes: [ 0xb3, 0x90, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "celfbr %f0, 0, %r15, 0" + - + input: + bytes: [ 0xb3, 0x90, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "celfbr %f0, 15, %r0, 0" + - + input: + bytes: [ 0xb3, 0x90, 0x57, 0x46 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "celfbr %f4, 5, %r6, 7" + - + input: + bytes: [ 0xb3, 0x90, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "celfbr %f15, 0, %r0, 0" + - + input: + bytes: [ 0xb3, 0xa0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "celgbr %f0, 0, %r0, 0" + - + input: + bytes: [ 0xb3, 0xa0, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "celgbr %f0, 0, %r0, 15" + - + input: + bytes: [ 0xb3, 0xa0, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "celgbr %f0, 0, %r15, 0" + - + input: + bytes: [ 0xb3, 0xa0, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "celgbr %f0, 15, %r0, 0" + - + input: + bytes: [ 0xb3, 0xa0, 0x57, 0x46 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "celgbr %f4, 5, %r6, 7" + - + input: + bytes: [ 0xb3, 0xa0, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "celgbr %f15, 0, %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xcd ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chf %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xcd ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chf %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xcd ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chf %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xcd ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chf %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xcd ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chf %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xcd ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chf %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xcd ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chf %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xcd ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chf %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xcd ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chf %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xcd ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chf %r15, 0" + - + input: + bytes: [ 0xcc, 0x0d, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cih %r0, -2147483648" + - + input: + bytes: [ 0xcc, 0x0d, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cih %r0, -1" + - + input: + bytes: [ 0xcc, 0x0d, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cih %r0, 0" + - + input: + bytes: [ 0xcc, 0x0d, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cih %r0, 1" + - + input: + bytes: [ 0xcc, 0x0d, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cih %r0, 2147483647" + - + input: + bytes: [ 0xcc, 0xfd, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cih %r15, 0" + - + input: + bytes: [ 0xb3, 0x9d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfdbr %r0, 0, %f0, 0" + - + input: + bytes: [ 0xb3, 0x9d, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfdbr %r0, 0, %f0, 15" + - + input: + bytes: [ 0xb3, 0x9d, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfdbr %r0, 0, %f15, 0" + - + input: + bytes: [ 0xb3, 0x9d, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfdbr %r0, 15, %f0, 0" + - + input: + bytes: [ 0xb3, 0x9d, 0x57, 0x46 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfdbr %r4, 5, %f6, 7" + - + input: + bytes: [ 0xb3, 0x9d, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfdbr %r15, 0, %f0, 0" + - + input: + bytes: [ 0xb3, 0x9c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfebr %r0, 0, %f0, 0" + - + input: + bytes: [ 0xb3, 0x9c, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfebr %r0, 0, %f0, 15" + - + input: + bytes: [ 0xb3, 0x9c, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfebr %r0, 0, %f15, 0" + - + input: + bytes: [ 0xb3, 0x9c, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfebr %r0, 15, %f0, 0" + - + input: + bytes: [ 0xb3, 0x9c, 0x57, 0x46 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfebr %r4, 5, %f6, 7" + - + input: + bytes: [ 0xb3, 0x9c, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfebr %r15, 0, %f0, 0" + - + input: + bytes: [ 0xb3, 0x9e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfxbr %r0, 0, %f0, 0" + - + input: + bytes: [ 0xb3, 0x9e, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfxbr %r0, 0, %f0, 15" + - + input: + bytes: [ 0xb3, 0x9e, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfxbr %r0, 0, %f13, 0" + - + input: + bytes: [ 0xb3, 0x9e, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfxbr %r0, 15, %f0, 0" + - + input: + bytes: [ 0xb3, 0x9e, 0x59, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfxbr %r7, 5, %f8, 9" + - + input: + bytes: [ 0xb3, 0x9e, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfxbr %r15, 0, %f0, 0" + - + input: + bytes: [ 0xb3, 0xad, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgdbr %r0, 0, %f0, 0" + - + input: + bytes: [ 0xb3, 0xad, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgdbr %r0, 0, %f0, 15" + - + input: + bytes: [ 0xb3, 0xad, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgdbr %r0, 0, %f15, 0" + - + input: + bytes: [ 0xb3, 0xad, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgdbr %r0, 15, %f0, 0" + - + input: + bytes: [ 0xb3, 0xad, 0x57, 0x46 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgdbr %r4, 5, %f6, 7" + - + input: + bytes: [ 0xb3, 0xad, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgdbr %r15, 0, %f0, 0" + - + input: + bytes: [ 0xb3, 0xac, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgebr %r0, 0, %f0, 0" + - + input: + bytes: [ 0xb3, 0xac, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgebr %r0, 0, %f0, 15" + - + input: + bytes: [ 0xb3, 0xac, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgebr %r0, 0, %f15, 0" + - + input: + bytes: [ 0xb3, 0xac, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgebr %r0, 15, %f0, 0" + - + input: + bytes: [ 0xb3, 0xac, 0x57, 0x46 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgebr %r4, 5, %f6, 7" + - + input: + bytes: [ 0xb3, 0xac, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgebr %r15, 0, %f0, 0" + - + input: + bytes: [ 0xb3, 0xae, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgxbr %r0, 0, %f0, 0" + - + input: + bytes: [ 0xb3, 0xae, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgxbr %r0, 0, %f0, 15" + - + input: + bytes: [ 0xb3, 0xae, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgxbr %r0, 0, %f13, 0" + - + input: + bytes: [ 0xb3, 0xae, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgxbr %r0, 15, %f0, 0" + - + input: + bytes: [ 0xb3, 0xae, 0x59, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgxbr %r7, 5, %f8, 9" + - + input: + bytes: [ 0xb3, 0xae, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgxbr %r15, 0, %f0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xcf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clhf %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xcf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clhf %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xcf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clhf %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xcf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clhf %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xcf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clhf %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xcf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clhf %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xcf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clhf %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xcf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clhf %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xcf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clhf %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xcf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clhf %r15, 0" + - + input: + bytes: [ 0xcc, 0x0f, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clih %r0, 0" + - + input: + bytes: [ 0xcc, 0x0f, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clih %r0, 1" + - + input: + bytes: [ 0xcc, 0x0f, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clih %r0, 4294967295" + - + input: + bytes: [ 0xcc, 0xff, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clih %r15, 0" + - + input: + bytes: [ 0xb3, 0x92, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxlfbr %f0, 0, %r0, 0" + - + input: + bytes: [ 0xb3, 0x92, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxlfbr %f0, 0, %r0, 15" + - + input: + bytes: [ 0xb3, 0x92, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxlfbr %f0, 0, %r15, 0" + - + input: + bytes: [ 0xb3, 0x92, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxlfbr %f0, 15, %r0, 0" + - + input: + bytes: [ 0xb3, 0x92, 0x5a, 0x49 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxlfbr %f4, 5, %r9, 10" + - + input: + bytes: [ 0xb3, 0x92, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxlfbr %f13, 0, %r0, 0" + - + input: + bytes: [ 0xb3, 0xa2, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxlgbr %f0, 0, %r0, 0" + - + input: + bytes: [ 0xb3, 0xa2, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxlgbr %f0, 0, %r0, 15" + - + input: + bytes: [ 0xb3, 0xa2, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxlgbr %f0, 0, %r15, 0" + - + input: + bytes: [ 0xb3, 0xa2, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxlgbr %f0, 15, %r0, 0" + - + input: + bytes: [ 0xb3, 0xa2, 0x5a, 0x49 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxlgbr %f4, 5, %r9, 10" + - + input: + bytes: [ 0xb3, 0xa2, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxlgbr %f13, 0, %r0, 0" + - + input: + bytes: [ 0xb3, 0x5f, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fidbra %f0, 0, %f0, 15" + - + input: + bytes: [ 0xb3, 0x5f, 0x57, 0x46 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fidbra %f4, 5, %f6, 7" + - + input: + bytes: [ 0xb3, 0x57, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fiebra %f0, 0, %f0, 15" + - + input: + bytes: [ 0xb3, 0x57, 0x57, 0x46 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fiebra %f4, 5, %f6, 7" + - + input: + bytes: [ 0xb3, 0x47, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fixbra %f0, 0, %f0, 15" + - + input: + bytes: [ 0xb3, 0x47, 0x59, 0x48 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fixbra %f4, 5, %f8, 9" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laa %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xf8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laa %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laa %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xf8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laa %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laa %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laa %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laa %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xf8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laa %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xf8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laa %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laa %r0, %r15, 0" + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laa %r15, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laag %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xe8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laag %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laag %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xe8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laag %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laag %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laag %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laag %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xe8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laag %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xe8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laag %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laag %r0, %r15, 0" + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe8 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laag %r15, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xfa ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laal %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xfa ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laal %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xfa ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laal %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xfa ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laal %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xfa ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laal %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xfa ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laal %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xfa ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laal %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xfa ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laal %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xfa ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laal %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xfa ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laal %r0, %r15, 0" + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xfa ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laal %r15, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xea ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laalg %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xea ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laalg %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xea ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laalg %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xea ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laalg %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xea ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laalg %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xea ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laalg %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xea ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laalg %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xea ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laalg %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xea ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laalg %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xea ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laalg %r0, %r15, 0" + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xea ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laalg %r15, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lan %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xf4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lan %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lan %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xf4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lan %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lan %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lan %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lan %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xf4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lan %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xf4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lan %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lan %r0, %r15, 0" + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lan %r15, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lang %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xe4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lang %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lang %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xe4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lang %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lang %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lang %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lang %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xe4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lang %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xe4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lang %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lang %r0, %r15, 0" + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lang %r15, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lao %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xf6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lao %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lao %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xf6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lao %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lao %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lao %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lao %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xf6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lao %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xf6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lao %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lao %r0, %r15, 0" + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lao %r15, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laog %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xe6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laog %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laog %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xe6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laog %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laog %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laog %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laog %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xe6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laog %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xe6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laog %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laog %r0, %r15, 0" + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laog %r15, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lax %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xf7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lax %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lax %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lax %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lax %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lax %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lax %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xf7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lax %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xf7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lax %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lax %r0, %r15, 0" + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lax %r15, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laxg %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xe7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laxg %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laxg %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xe7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laxg %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laxg %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laxg %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laxg %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xe7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laxg %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xe7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laxg %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laxg %r0, %r15, 0" + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "laxg %r15, %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lbh %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lbh %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lbh %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lbh %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lbh %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lbh %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lbh %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lbh %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lbh %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lbh %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xca ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lfh %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xca ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lfh %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xca ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lfh %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xca ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lfh %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xca ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lfh %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xca ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lfh %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xca ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lfh %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xca ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lfh %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xca ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lfh %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xca ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lfh %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhh %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhh %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhh %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhh %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhh %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhh %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhh %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhh %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhh %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc4 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhh %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llch %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llch %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llch %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llch %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llch %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llch %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llch %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llch %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llch %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llch %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llhh %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llhh %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llhh %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llhh %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llhh %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llhh %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llhh %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llhh %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llhh %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc6 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llhh %r15, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "loc %r0, 0, 0" + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "loc %r0, 0, 15" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "loc %r0, -524288, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "loc %r0, 524287, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "loc %r0, 0(%r1), 0" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "loc %r0, 0(%r15), 0" + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "loc %r15, 0, 0" + - + input: + bytes: [ 0xeb, 0x11, 0x30, 0x02, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "loco %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x12, 0x30, 0x02, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "loch %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x13, 0x30, 0x02, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locnle %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x14, 0x30, 0x02, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locl %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x15, 0x30, 0x02, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locnhe %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x16, 0x30, 0x02, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "loclh %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x17, 0x30, 0x02, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locne %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x18, 0x30, 0x02, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "loce %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x19, 0x30, 0x02, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locnlh %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1a, 0x30, 0x02, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "loche %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1b, 0x30, 0x02, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locnl %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1c, 0x30, 0x02, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locle %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1d, 0x30, 0x02, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locnh %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1e, 0x30, 0x02, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locno %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locg %r0, 0, 0" + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locg %r0, 0, 15" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locg %r0, -524288, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locg %r0, 524287, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locg %r0, 0(%r1), 0" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locg %r0, 0(%r15), 0" + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locg %r15, 0, 0" + - + input: + bytes: [ 0xeb, 0x11, 0x30, 0x02, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgo %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x12, 0x30, 0x02, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgh %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x13, 0x30, 0x02, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgnle %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x14, 0x30, 0x02, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgl %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x15, 0x30, 0x02, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgnhe %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x16, 0x30, 0x02, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locglh %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x17, 0x30, 0x02, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgne %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x18, 0x30, 0x02, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locge %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x19, 0x30, 0x02, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgnlh %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1a, 0x30, 0x02, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locghe %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1b, 0x30, 0x02, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgnl %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1c, 0x30, 0x02, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgle %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1d, 0x30, 0x02, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgnh %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1e, 0x30, 0x02, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgno %r1, 2(%r3)" + - + input: + bytes: [ 0xb9, 0xe2, 0x00, 0x12 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgr %r1, %r2, 0" + - + input: + bytes: [ 0xb9, 0xe2, 0xf0, 0x12 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgr %r1, %r2, 15" + - + input: + bytes: [ 0xb9, 0xe2, 0x10, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgro %r1, %r3" + - + input: + bytes: [ 0xb9, 0xe2, 0x20, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgrh %r1, %r3" + - + input: + bytes: [ 0xb9, 0xe2, 0x30, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgrnle %r1, %r3" + - + input: + bytes: [ 0xb9, 0xe2, 0x40, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgrl %r1, %r3" + - + input: + bytes: [ 0xb9, 0xe2, 0x50, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgrnhe %r1, %r3" + - + input: + bytes: [ 0xb9, 0xe2, 0x60, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgrlh %r1, %r3" + - + input: + bytes: [ 0xb9, 0xe2, 0x70, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgrne %r1, %r3" + - + input: + bytes: [ 0xb9, 0xe2, 0x80, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgre %r1, %r3" + - + input: + bytes: [ 0xb9, 0xe2, 0x90, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgrnlh %r1, %r3" + - + input: + bytes: [ 0xb9, 0xe2, 0xa0, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgrhe %r1, %r3" + - + input: + bytes: [ 0xb9, 0xe2, 0xb0, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgrnl %r1, %r3" + - + input: + bytes: [ 0xb9, 0xe2, 0xc0, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgrle %r1, %r3" + - + input: + bytes: [ 0xb9, 0xe2, 0xd0, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgrnh %r1, %r3" + - + input: + bytes: [ 0xb9, 0xe2, 0xe0, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locgrno %r1, %r3" + - + input: + bytes: [ 0xb9, 0xf2, 0x00, 0x12 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locr %r1, %r2, 0" + - + input: + bytes: [ 0xb9, 0xf2, 0xf0, 0x12 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locr %r1, %r2, 15" + - + input: + bytes: [ 0xb9, 0xf2, 0x10, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locro %r1, %r3" + - + input: + bytes: [ 0xb9, 0xf2, 0x20, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locrh %r1, %r3" + - + input: + bytes: [ 0xb9, 0xf2, 0x30, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locrnle %r1, %r3" + - + input: + bytes: [ 0xb9, 0xf2, 0x40, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locrl %r1, %r3" + - + input: + bytes: [ 0xb9, 0xf2, 0x50, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locrnhe %r1, %r3" + - + input: + bytes: [ 0xb9, 0xf2, 0x60, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locrlh %r1, %r3" + - + input: + bytes: [ 0xb9, 0xf2, 0x70, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locrne %r1, %r3" + - + input: + bytes: [ 0xb9, 0xf2, 0x80, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locre %r1, %r3" + - + input: + bytes: [ 0xb9, 0xf2, 0x90, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locrnlh %r1, %r3" + - + input: + bytes: [ 0xb9, 0xf2, 0xa0, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locrhe %r1, %r3" + - + input: + bytes: [ 0xb9, 0xf2, 0xb0, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locrnl %r1, %r3" + - + input: + bytes: [ 0xb9, 0xf2, 0xc0, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locrle %r1, %r3" + - + input: + bytes: [ 0xb9, 0xf2, 0xd0, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locrnh %r1, %r3" + - + input: + bytes: [ 0xb9, 0xf2, 0xe0, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "locrno %r1, %r3" + - + input: + bytes: [ 0xb9, 0xe4, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ngrk %r0, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xe4, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ngrk %r0, %r0, %r15" + - + input: + bytes: [ 0xb9, 0xe4, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ngrk %r0, %r15, %r0" + - + input: + bytes: [ 0xb9, 0xe4, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ngrk %r15, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xe4, 0x90, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ngrk %r7, %r8, %r9" + - + input: + bytes: [ 0xb9, 0xf4, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nrk %r0, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xf4, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nrk %r0, %r0, %r15" + - + input: + bytes: [ 0xb9, 0xf4, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nrk %r0, %r15, %r0" + - + input: + bytes: [ 0xb9, 0xf4, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nrk %r15, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xf4, 0x90, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nrk %r7, %r8, %r9" + - + input: + bytes: [ 0xb9, 0xe6, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ogrk %r0, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xe6, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ogrk %r0, %r0, %r15" + - + input: + bytes: [ 0xb9, 0xe6, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ogrk %r0, %r15, %r0" + - + input: + bytes: [ 0xb9, 0xe6, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ogrk %r15, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xe6, 0x90, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ogrk %r7, %r8, %r9" + - + input: + bytes: [ 0xb9, 0xf6, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ork %r0, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xf6, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ork %r0, %r0, %r15" + - + input: + bytes: [ 0xb9, 0xf6, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ork %r0, %r15, %r0" + - + input: + bytes: [ 0xb9, 0xf6, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ork %r15, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xf6, 0x90, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ork %r7, %r8, %r9" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x5d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risbhg %r0, %r0, 0, 0, 0" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x5d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risbhg %r0, %r0, 0, 0, 63" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x5d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risbhg %r0, %r0, 0, 255, 0" + - + input: + bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x5d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risbhg %r0, %r0, 255, 0, 0" + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x5d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risbhg %r0, %r15, 0, 0, 0" + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x5d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risbhg %r15, %r0, 0, 0, 0" + - + input: + bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x5d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risbhg %r4, %r5, 6, 7, 8" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risblg %r0, %r0, 0, 0, 0" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risblg %r0, %r0, 0, 0, 63" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risblg %r0, %r0, 0, 255, 0" + - + input: + bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risblg %r0, %r0, 255, 0, 0" + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risblg %r0, %r15, 0, 0, 0" + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risblg %r15, %r0, 0, 0, 0" + - + input: + bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risblg %r4, %r5, 6, 7, 8" + - + input: + bytes: [ 0xb9, 0xe9, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgrk %r0, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xe9, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgrk %r0, %r0, %r15" + - + input: + bytes: [ 0xb9, 0xe9, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgrk %r0, %r15, %r0" + - + input: + bytes: [ 0xb9, 0xe9, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgrk %r15, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xe9, 0x90, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgrk %r7, %r8, %r9" + - + input: + bytes: [ 0xb9, 0xeb, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgrk %r0, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xeb, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgrk %r0, %r0, %r15" + - + input: + bytes: [ 0xb9, 0xeb, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgrk %r0, %r15, %r0" + - + input: + bytes: [ 0xb9, 0xeb, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgrk %r15, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xeb, 0x90, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgrk %r7, %r8, %r9" + - + input: + bytes: [ 0xb9, 0xfb, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slrk %r0, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xfb, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slrk %r0, %r0, %r15" + - + input: + bytes: [ 0xb9, 0xfb, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slrk %r0, %r15, %r0" + - + input: + bytes: [ 0xb9, 0xfb, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slrk %r15, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xfb, 0x90, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slrk %r7, %r8, %r9" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xdf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllk %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0xdf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllk %r15, %r1, 0" + - + input: + bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0xdf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllk %r1, %r15, 0" + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0xdf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllk %r15, %r15, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xdf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllk %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xdf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllk %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xdf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllk %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xdf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllk %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xdf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllk %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xdf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllk %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xdf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllk %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xdf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllk %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xdc ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srak %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0xdc ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srak %r15, %r1, 0" + - + input: + bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0xdc ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srak %r1, %r15, 0" + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0xdc ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srak %r15, %r15, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xdc ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srak %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xdc ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srak %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xdc ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srak %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xdc ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srak %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xdc ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srak %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xdc ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srak %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xdc ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srak %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xdc ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srak %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0xb9, 0xf9, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srk %r0, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xf9, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srk %r0, %r0, %r15" + - + input: + bytes: [ 0xb9, 0xf9, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srk %r0, %r15, %r0" + - + input: + bytes: [ 0xb9, 0xf9, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srk %r15, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xf9, 0x90, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srk %r7, %r8, %r9" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xde ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlk %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0xde ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlk %r15, %r1, 0" + - + input: + bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0xde ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlk %r1, %r15, 0" + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0xde ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlk %r15, %r15, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xde ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlk %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xde ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlk %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xde ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlk %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xde ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlk %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xde ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlk %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xde ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlk %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xde ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlk %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xde ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlk %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stch %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stch %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stch %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stch %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stch %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stch %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stch %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stch %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stch %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stch %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthh %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthh %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthh %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthh %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthh %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthh %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthh %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthh %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthh %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc7 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthh %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xcb ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stfh %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xcb ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stfh %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xcb ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stfh %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xcb ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stfh %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xcb ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stfh %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xcb ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stfh %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xcb ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stfh %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xcb ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stfh %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xcb ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stfh %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xcb ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stfh %r15, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stoc %r0, 0, 0" + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stoc %r0, 0, 15" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stoc %r0, -524288, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stoc %r0, 524287, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stoc %r0, 0(%r1), 0" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stoc %r0, 0(%r15), 0" + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stoc %r15, 0, 0" + - + input: + bytes: [ 0xeb, 0x11, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stoco %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x12, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stoch %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x13, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocnle %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x14, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocl %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x15, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocnhe %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x16, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stoclh %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x17, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocne %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x18, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stoce %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x19, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocnlh %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1a, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stoche %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1b, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocnl %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1c, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocle %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1d, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocnh %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1e, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocno %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocg %r0, 0, 0" + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocg %r0, 0, 15" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocg %r0, -524288, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocg %r0, 524287, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocg %r0, 0(%r1), 0" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocg %r0, 0(%r15), 0" + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocg %r15, 0, 0" + - + input: + bytes: [ 0xeb, 0x11, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocgo %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x12, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocgh %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x13, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocgnle %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x14, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocgl %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x15, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocgnhe %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x16, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocglh %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x17, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocgne %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x18, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocge %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x19, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocgnlh %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1a, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocghe %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1b, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocgnl %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1c, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocgle %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1d, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocgnh %r1, 2(%r3)" + - + input: + bytes: [ 0xeb, 0x1e, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stocgno %r1, 2(%r3)" + - + input: + bytes: [ 0xb9, 0xe7, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xgrk %r0, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xe7, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xgrk %r0, %r0, %r15" + - + input: + bytes: [ 0xb9, 0xe7, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xgrk %r0, %r15, %r0" + - + input: + bytes: [ 0xb9, 0xe7, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xgrk %r15, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xe7, 0x90, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xgrk %r7, %r8, %r9" + - + input: + bytes: [ 0xb9, 0xf7, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xrk %r0, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xf7, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xrk %r0, %r0, %r15" + - + input: + bytes: [ 0xb9, 0xf7, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xrk %r0, %r15, %r0" + - + input: + bytes: [ 0xb9, 0xf7, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xrk %r15, %r0, %r0" + - + input: + bytes: [ 0xb9, 0xf7, 0x90, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xrk %r7, %r8, %r9" diff --git a/tests/MC/SystemZ/insn-good.s.yaml b/tests/MC/SystemZ/insn-good.s.yaml new file mode 100644 index 0000000000..8afc270aca --- /dev/null +++ b/tests/MC/SystemZ/insn-good.s.yaml @@ -0,0 +1,20242 @@ +test_cases: + - + input: + bytes: [ 0x5a, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "a %r0, 0" + - + input: + bytes: [ 0x5a, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "a %r0, 4095" + - + input: + bytes: [ 0x5a, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "a %r0, 0(%r1)" + - + input: + bytes: [ 0x5a, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "a %r0, 0(%r15)" + - + input: + bytes: [ 0x5a, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "a %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x5a, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "a %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x5a, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "a %r15, 0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "adb %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "adb %f0, 4095" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "adb %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "adb %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "adb %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "adb %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "adb %f15, 0" + - + input: + bytes: [ 0xb3, 0x1a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "adbr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x1a, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "adbr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x1a, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "adbr %f7, %f8" + - + input: + bytes: [ 0xb3, 0x1a, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "adbr %f15, %f0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aeb %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aeb %f0, 4095" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aeb %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aeb %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aeb %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aeb %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aeb %f15, 0" + - + input: + bytes: [ 0xb3, 0x0a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aebr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x0a, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aebr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x0a, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aebr %f7, %f8" + - + input: + bytes: [ 0xb3, 0x0a, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aebr %f15, %f0" + - + input: + bytes: [ 0xc2, 0x09, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "afi %r0, -2147483648" + - + input: + bytes: [ 0xc2, 0x09, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "afi %r0, -1" + - + input: + bytes: [ 0xc2, 0x09, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "afi %r0, 0" + - + input: + bytes: [ 0xc2, 0x09, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "afi %r0, 1" + - + input: + bytes: [ 0xc2, 0x09, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "afi %r0, 2147483647" + - + input: + bytes: [ 0xc2, 0xf9, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "afi %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ag %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x08 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ag %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ag %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ag %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x08 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ag %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ag %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ag %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x08 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ag %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x08 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ag %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ag %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x18 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agf %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x18 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agf %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agf %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x18 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agf %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x18 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agf %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agf %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agf %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x18 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agf %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x18 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agf %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agf %r15, 0" + - + input: + bytes: [ 0xc2, 0x08, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agfi %r0, -2147483648" + - + input: + bytes: [ 0xc2, 0x08, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agfi %r0, -1" + - + input: + bytes: [ 0xc2, 0x08, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agfi %r0, 0" + - + input: + bytes: [ 0xc2, 0x08, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agfi %r0, 1" + - + input: + bytes: [ 0xc2, 0x08, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agfi %r0, 2147483647" + - + input: + bytes: [ 0xc2, 0xf8, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agfi %r15, 0" + - + input: + bytes: [ 0xb9, 0x18, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agfr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x18, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agfr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x18, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agfr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x18, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agfr %r7, %r8" + - + input: + bytes: [ 0xa7, 0x0b, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aghi %r0, -32768" + - + input: + bytes: [ 0xa7, 0x0b, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aghi %r0, -1" + - + input: + bytes: [ 0xa7, 0x0b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aghi %r0, 0" + - + input: + bytes: [ 0xa7, 0x0b, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aghi %r0, 1" + - + input: + bytes: [ 0xa7, 0x0b, 0x7f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aghi %r0, 32767" + - + input: + bytes: [ 0xa7, 0xfb, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aghi %r15, 0" + - + input: + bytes: [ 0xb9, 0x08, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x08, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x08, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x08, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agr %r7, %r8" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agsi -524288, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agsi -1, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agsi 0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agsi 1, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agsi 524287, 0" + - + input: + bytes: [ 0xeb, 0x80, 0x00, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agsi 0, -128" + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agsi 0, -1" + - + input: + bytes: [ 0xeb, 0x01, 0x00, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agsi 0, 1" + - + input: + bytes: [ 0xeb, 0x7f, 0x00, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agsi 0, 127" + - + input: + bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agsi 0(%r1), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agsi 0(%r15), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agsi 524287(%r1), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "agsi 524287(%r15), 42" + - + input: + bytes: [ 0x4a, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ah %r0, 0" + - + input: + bytes: [ 0x4a, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ah %r0, 4095" + - + input: + bytes: [ 0x4a, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ah %r0, 0(%r1)" + - + input: + bytes: [ 0x4a, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ah %r0, 0(%r15)" + - + input: + bytes: [ 0x4a, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ah %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x4a, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ah %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x4a, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ah %r15, 0" + - + input: + bytes: [ 0xa7, 0x0a, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahi %r0, -32768" + - + input: + bytes: [ 0xa7, 0x0a, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahi %r0, -1" + - + input: + bytes: [ 0xa7, 0x0a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahi %r0, 0" + - + input: + bytes: [ 0xa7, 0x0a, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahi %r0, 1" + - + input: + bytes: [ 0xa7, 0x0a, 0x7f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahi %r0, 32767" + - + input: + bytes: [ 0xa7, 0xfa, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahi %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahy %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahy %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahy %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahy %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahy %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahy %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahy %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahy %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahy %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ahy %r15, 0" + - + input: + bytes: [ 0x5e, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "al %r0, 0" + - + input: + bytes: [ 0x5e, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "al %r0, 4095" + - + input: + bytes: [ 0x5e, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "al %r0, 0(%r1)" + - + input: + bytes: [ 0x5e, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "al %r0, 0(%r15)" + - + input: + bytes: [ 0x5e, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "al %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x5e, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "al %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x5e, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "al %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x98 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alc %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x98 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alc %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x98 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alc %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x98 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alc %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x98 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alc %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x98 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alc %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x98 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alc %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x98 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alc %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x98 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alc %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x98 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alc %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x88 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alcg %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x88 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alcg %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x88 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alcg %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x88 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alcg %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x88 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alcg %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x88 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alcg %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x88 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alcg %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x88 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alcg %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x88 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alcg %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x88 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alcg %r15, 0" + - + input: + bytes: [ 0xb9, 0x88, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alcgr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x88, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alcgr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x88, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alcgr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x88, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alcgr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x98, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alcr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x98, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alcr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x98, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alcr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x98, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alcr %r7, %r8" + - + input: + bytes: [ 0xc2, 0x0b, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alfi %r0, 0" + - + input: + bytes: [ 0xc2, 0x0b, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alfi %r0, 4294967295" + - + input: + bytes: [ 0xc2, 0xfb, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alfi %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alg %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alg %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alg %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alg %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alg %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alg %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alg %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alg %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alg %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alg %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algf %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algf %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algf %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algf %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algf %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algf %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algf %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algf %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algf %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x1a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algf %r15, 0" + - + input: + bytes: [ 0xc2, 0x0a, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algfi %r0, 0" + - + input: + bytes: [ 0xc2, 0x0a, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algfi %r0, 4294967295" + - + input: + bytes: [ 0xc2, 0xfa, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algfi %r15, 0" + - + input: + bytes: [ 0xb9, 0x1a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algfr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x1a, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algfr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x1a, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algfr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x1a, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algfr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x0a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x0a, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x0a, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x0a, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "algr %r7, %r8" + - + input: + bytes: [ 0x1e, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alr %r0, %r0" + - + input: + bytes: [ 0x1e, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alr %r0, %r15" + - + input: + bytes: [ 0x1e, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alr %r15, %r0" + - + input: + bytes: [ 0x1e, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "alr %r7, %r8" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x5e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aly %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x5e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aly %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x5e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aly %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x5e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aly %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x5e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aly %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x5e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aly %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x5e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aly %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x5e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aly %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x5e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aly %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x5e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "aly %r15, 0" + - + input: + bytes: [ 0x1a, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ar %r0, %r0" + - + input: + bytes: [ 0x1a, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ar %r0, %r15" + - + input: + bytes: [ 0x1a, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ar %r15, %r0" + - + input: + bytes: [ 0x1a, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ar %r7, %r8" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x6a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "asi -524288, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x6a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "asi -1, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x6a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "asi 0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x6a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "asi 1, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x6a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "asi 524287, 0" + - + input: + bytes: [ 0xeb, 0x80, 0x00, 0x00, 0x00, 0x6a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "asi 0, -128" + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x6a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "asi 0, -1" + - + input: + bytes: [ 0xeb, 0x01, 0x00, 0x00, 0x00, 0x6a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "asi 0, 1" + - + input: + bytes: [ 0xeb, 0x7f, 0x00, 0x00, 0x00, 0x6a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "asi 0, 127" + - + input: + bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x6a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "asi 0(%r1), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x6a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "asi 0(%r15), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x6a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "asi 524287(%r1), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x6a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "asi 524287(%r15), 42" + - + input: + bytes: [ 0xb3, 0x4a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "axbr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x4a, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "axbr %f0, %f13" + - + input: + bytes: [ 0xb3, 0x4a, 0x00, 0x88 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "axbr %f8, %f8" + - + input: + bytes: [ 0xb3, 0x4a, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "axbr %f13, %f0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x5a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ay %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x5a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ay %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x5a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ay %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x5a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ay %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x5a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ay %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x5a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ay %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x5a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ay %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x5a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ay %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x5a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ay %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x5a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ay %r15, 0" + - + input: + bytes: [ 0x0d, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "basr %r0, %r1" + - + input: + bytes: [ 0x0d, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "basr %r0, %r15" + - + input: + bytes: [ 0x0d, 0xe9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "basr %r14, %r9" + - + input: + bytes: [ 0x0d, 0xf1 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "basr %r15, %r1" + - + input: + bytes: [ 0x07, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "bcr 0, %r0" + - + input: + bytes: [ 0x07, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "bcr 0, %r15" + - + input: + bytes: [ 0x07, 0x1f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "bor %r15" + - + input: + bytes: [ 0x07, 0x2f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "bhr %r15" + - + input: + bytes: [ 0x07, 0x3f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "bnler %r15" + - + input: + bytes: [ 0x07, 0x4f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "blr %r15" + - + input: + bytes: [ 0x07, 0x5f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "bnher %r15" + - + input: + bytes: [ 0x07, 0x6f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "blhr %r15" + - + input: + bytes: [ 0x07, 0x7f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "bner %r15" + - + input: + bytes: [ 0x07, 0x8f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ber %r15" + - + input: + bytes: [ 0x07, 0x9f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "bnlhr %r15" + - + input: + bytes: [ 0x07, 0xaf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "bher %r15" + - + input: + bytes: [ 0x07, 0xbf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "bnlr %r15" + - + input: + bytes: [ 0x07, 0xcf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "bler %r15" + - + input: + bytes: [ 0x07, 0xdf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "bnhr %r15" + - + input: + bytes: [ 0x07, 0xef ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "bnor %r15" + - + input: + bytes: [ 0x07, 0xf1 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "br %r1" + - + input: + bytes: [ 0x07, 0xfe ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "br %r14" + - + input: + bytes: [ 0x07, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "br %r15" + - + input: + bytes: [ 0x59, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "c %r0, 0" + - + input: + bytes: [ 0x59, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "c %r0, 4095" + - + input: + bytes: [ 0x59, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "c %r0, 0(%r1)" + - + input: + bytes: [ 0x59, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "c %r0, 0(%r15)" + - + input: + bytes: [ 0x59, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "c %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x59, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "c %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x59, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "c %r15, 0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x19 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdb %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x19 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdb %f0, 4095" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x19 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdb %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x19 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdb %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x19 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdb %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x19 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdb %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x19 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdb %f15, 0" + - + input: + bytes: [ 0xb3, 0x19, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdbr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x19, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdbr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x19, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdbr %f7, %f8" + - + input: + bytes: [ 0xb3, 0x19, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdbr %f15, %f0" + - + input: + bytes: [ 0xb3, 0x95, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdfbr %f0, %r0" + - + input: + bytes: [ 0xb3, 0x95, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdfbr %f0, %r15" + - + input: + bytes: [ 0xb3, 0x95, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdfbr %f15, %r0" + - + input: + bytes: [ 0xb3, 0x95, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdfbr %f7, %r8" + - + input: + bytes: [ 0xb3, 0x95, 0x00, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdfbr %f15, %r15" + - + input: + bytes: [ 0xb3, 0xa5, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdgbr %f0, %r0" + - + input: + bytes: [ 0xb3, 0xa5, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdgbr %f0, %r15" + - + input: + bytes: [ 0xb3, 0xa5, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdgbr %f15, %r0" + - + input: + bytes: [ 0xb3, 0xa5, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdgbr %f7, %r8" + - + input: + bytes: [ 0xb3, 0xa5, 0x00, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cdgbr %f15, %r15" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ceb %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ceb %f0, 4095" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ceb %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ceb %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ceb %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ceb %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ceb %f15, 0" + - + input: + bytes: [ 0xb3, 0x09, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cebr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x09, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cebr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x09, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cebr %f7, %f8" + - + input: + bytes: [ 0xb3, 0x09, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cebr %f15, %f0" + - + input: + bytes: [ 0xb3, 0x94, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cefbr %f0, %r0" + - + input: + bytes: [ 0xb3, 0x94, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cefbr %f0, %r15" + - + input: + bytes: [ 0xb3, 0x94, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cefbr %f15, %r0" + - + input: + bytes: [ 0xb3, 0x94, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cefbr %f7, %r8" + - + input: + bytes: [ 0xb3, 0x94, 0x00, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cefbr %f15, %r15" + - + input: + bytes: [ 0xb3, 0xa4, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cegbr %f0, %r0" + - + input: + bytes: [ 0xb3, 0xa4, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cegbr %f0, %r15" + - + input: + bytes: [ 0xb3, 0xa4, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cegbr %f15, %r0" + - + input: + bytes: [ 0xb3, 0xa4, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cegbr %f7, %r8" + - + input: + bytes: [ 0xb3, 0xa4, 0x00, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cegbr %f15, %r15" + - + input: + bytes: [ 0xb3, 0x99, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfdbr %r0, 0, %f0" + - + input: + bytes: [ 0xb3, 0x99, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfdbr %r0, 0, %f15" + - + input: + bytes: [ 0xb3, 0x99, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfdbr %r0, 15, %f0" + - + input: + bytes: [ 0xb3, 0x99, 0x50, 0x46 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfdbr %r4, 5, %f6" + - + input: + bytes: [ 0xb3, 0x99, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfdbr %r15, 0, %f0" + - + input: + bytes: [ 0xb3, 0x98, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfebr %r0, 0, %f0" + - + input: + bytes: [ 0xb3, 0x98, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfebr %r0, 0, %f15" + - + input: + bytes: [ 0xb3, 0x98, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfebr %r0, 15, %f0" + - + input: + bytes: [ 0xb3, 0x98, 0x50, 0x46 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfebr %r4, 5, %f6" + - + input: + bytes: [ 0xb3, 0x98, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfebr %r15, 0, %f0" + - + input: + bytes: [ 0xc2, 0x0d, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfi %r0, -2147483648" + - + input: + bytes: [ 0xc2, 0x0d, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfi %r0, -1" + - + input: + bytes: [ 0xc2, 0x0d, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfi %r0, 0" + - + input: + bytes: [ 0xc2, 0x0d, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfi %r0, 1" + - + input: + bytes: [ 0xc2, 0x0d, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfi %r0, 2147483647" + - + input: + bytes: [ 0xc2, 0xfd, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfi %r15, 0" + - + input: + bytes: [ 0xb3, 0x9a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfxbr %r0, 0, %f0" + - + input: + bytes: [ 0xb3, 0x9a, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfxbr %r0, 0, %f13" + - + input: + bytes: [ 0xb3, 0x9a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfxbr %r0, 15, %f0" + - + input: + bytes: [ 0xb3, 0x9a, 0x50, 0x48 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfxbr %r4, 5, %f8" + - + input: + bytes: [ 0xb3, 0x9a, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cfxbr %r15, 0, %f0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x20 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cg %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x20 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cg %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cg %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x20 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cg %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x20 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cg %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cg %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cg %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x20 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cg %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x20 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cg %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cg %r15, 0" + - + input: + bytes: [ 0xb3, 0xa9, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgdbr %r0, 0, %f0" + - + input: + bytes: [ 0xb3, 0xa9, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgdbr %r0, 0, %f15" + - + input: + bytes: [ 0xb3, 0xa9, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgdbr %r0, 15, %f0" + - + input: + bytes: [ 0xb3, 0xa9, 0x50, 0x46 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgdbr %r4, 5, %f6" + - + input: + bytes: [ 0xb3, 0xa9, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgdbr %r15, 0, %f0" + - + input: + bytes: [ 0xb3, 0xa8, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgebr %r0, 0, %f0" + - + input: + bytes: [ 0xb3, 0xa8, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgebr %r0, 0, %f15" + - + input: + bytes: [ 0xb3, 0xa8, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgebr %r0, 15, %f0" + - + input: + bytes: [ 0xb3, 0xa8, 0x50, 0x46 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgebr %r4, 5, %f6" + - + input: + bytes: [ 0xb3, 0xa8, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgebr %r15, 0, %f0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgf %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgf %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgf %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgf %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgf %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgf %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgf %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgf %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgf %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgf %r15, 0" + - + input: + bytes: [ 0xc2, 0x0c, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgfi %r0, -2147483648" + - + input: + bytes: [ 0xc2, 0x0c, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgfi %r0, -1" + - + input: + bytes: [ 0xc2, 0x0c, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgfi %r0, 0" + - + input: + bytes: [ 0xc2, 0x0c, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgfi %r0, 1" + - + input: + bytes: [ 0xc2, 0x0c, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgfi %r0, 2147483647" + - + input: + bytes: [ 0xc2, 0xfc, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgfi %r15, 0" + - + input: + bytes: [ 0xb9, 0x30, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgfr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x30, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgfr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x30, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgfr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x30, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgfr %r7, %r8" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x34 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgh %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x34 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgh %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x34 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgh %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x34 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgh %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x34 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgh %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x34 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgh %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x34 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgh %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x34 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgh %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x34 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgh %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x34 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgh %r15, 0" + - + input: + bytes: [ 0xa7, 0x0f, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cghi %r0, -32768" + - + input: + bytes: [ 0xa7, 0x0f, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cghi %r0, -1" + - + input: + bytes: [ 0xa7, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cghi %r0, 0" + - + input: + bytes: [ 0xa7, 0x0f, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cghi %r0, 1" + - + input: + bytes: [ 0xa7, 0x0f, 0x7f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cghi %r0, 32767" + - + input: + bytes: [ 0xa7, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cghi %r15, 0" + - + input: + bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cghsi 0, 0" + - + input: + bytes: [ 0xe5, 0x58, 0x0f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cghsi 4095, 0" + - + input: + bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cghsi 0, -32768" + - + input: + bytes: [ 0xe5, 0x58, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cghsi 0, -1" + - + input: + bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cghsi 0, 0" + - + input: + bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cghsi 0, 1" + - + input: + bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x7f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cghsi 0, 32767" + - + input: + bytes: [ 0xe5, 0x58, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cghsi 0(%r1), 42" + - + input: + bytes: [ 0xe5, 0x58, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cghsi 0(%r15), 42" + - + input: + bytes: [ 0xe5, 0x58, 0x1f, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cghsi 4095(%r1), 42" + - + input: + bytes: [ 0xe5, 0x58, 0xff, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cghsi 4095(%r15), 42" + - + input: + bytes: [ 0xb9, 0x20, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x20, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x20, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x20, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgr %r7, %r8" + - + input: + bytes: [ 0xb3, 0xaa, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgxbr %r0, 0, %f0" + - + input: + bytes: [ 0xb3, 0xaa, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgxbr %r0, 0, %f13" + - + input: + bytes: [ 0xb3, 0xaa, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgxbr %r0, 15, %f0" + - + input: + bytes: [ 0xb3, 0xaa, 0x50, 0x48 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgxbr %r4, 5, %f8" + - + input: + bytes: [ 0xb3, 0xaa, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cgxbr %r15, 0, %f0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ch %r0, 0" + - + input: + bytes: [ 0x49, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ch %r0, 4095" + - + input: + bytes: [ 0x49, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ch %r0, 0(%r1)" + - + input: + bytes: [ 0x49, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ch %r0, 0(%r15)" + - + input: + bytes: [ 0x49, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ch %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x49, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ch %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x49, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ch %r15, 0" + - + input: + bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chhsi 0, 0" + - + input: + bytes: [ 0xe5, 0x54, 0x0f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chhsi 4095, 0" + - + input: + bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chhsi 0, -32768" + - + input: + bytes: [ 0xe5, 0x54, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chhsi 0, -1" + - + input: + bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chhsi 0, 0" + - + input: + bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chhsi 0, 1" + - + input: + bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x7f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chhsi 0, 32767" + - + input: + bytes: [ 0xe5, 0x54, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chhsi 0(%r1), 42" + - + input: + bytes: [ 0xe5, 0x54, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chhsi 0(%r15), 42" + - + input: + bytes: [ 0xe5, 0x54, 0x1f, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chhsi 4095(%r1), 42" + - + input: + bytes: [ 0xe5, 0x54, 0xff, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chhsi 4095(%r15), 42" + - + input: + bytes: [ 0xa7, 0x0e, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chi %r0, -32768" + - + input: + bytes: [ 0xa7, 0x0e, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chi %r0, -1" + - + input: + bytes: [ 0xa7, 0x0e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chi %r0, 0" + - + input: + bytes: [ 0xa7, 0x0e, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chi %r0, 1" + - + input: + bytes: [ 0xa7, 0x0e, 0x7f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chi %r0, 32767" + - + input: + bytes: [ 0xa7, 0xfe, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chi %r15, 0" + - + input: + bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chsi 0, 0" + - + input: + bytes: [ 0xe5, 0x5c, 0x0f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chsi 4095, 0" + - + input: + bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chsi 0, -32768" + - + input: + bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chsi 0, -1" + - + input: + bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chsi 0, 0" + - + input: + bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chsi 0, 1" + - + input: + bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x7f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chsi 0, 32767" + - + input: + bytes: [ 0xe5, 0x5c, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chsi 0(%r1), 42" + - + input: + bytes: [ 0xe5, 0x5c, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chsi 0(%r15), 42" + - + input: + bytes: [ 0xe5, 0x5c, 0x1f, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chsi 4095(%r1), 42" + - + input: + bytes: [ 0xe5, 0x5c, 0xff, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chsi 4095(%r15), 42" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x79 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chy %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x79 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chy %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x79 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chy %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x79 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chy %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x79 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chy %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x79 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chy %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x79 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chy %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x79 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chy %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x79 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chy %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x79 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "chy %r15, 0" + - + input: + bytes: [ 0x55, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cl %r0, 0" + - + input: + bytes: [ 0x55, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cl %r0, 4095" + - + input: + bytes: [ 0x55, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cl %r0, 0(%r1)" + - + input: + bytes: [ 0x55, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cl %r0, 0(%r15)" + - + input: + bytes: [ 0x55, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cl %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x55, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cl %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x55, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cl %r15, 0" + - + input: + bytes: [ 0xd5, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clc 0(1), 0" + - + input: + bytes: [ 0xd5, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clc 0(1), 0(%r1)" + - + input: + bytes: [ 0xd5, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clc 0(1), 0(%r15)" + - + input: + bytes: [ 0xd5, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clc 0(1), 4095" + - + input: + bytes: [ 0xd5, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clc 0(1), 4095(%r1)" + - + input: + bytes: [ 0xd5, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clc 0(1), 4095(%r15)" + - + input: + bytes: [ 0xd5, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clc 0(1, %r1), 0" + - + input: + bytes: [ 0xd5, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clc 0(1, %r15), 0" + - + input: + bytes: [ 0xd5, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clc 4095(1, %r1), 0" + - + input: + bytes: [ 0xd5, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clc 4095(1, %r15), 0" + - + input: + bytes: [ 0xd5, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clc 0(256, %r1), 0" + - + input: + bytes: [ 0xd5, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clc 0(256, %r15), 0" + - + input: + bytes: [ 0xe5, 0x5d, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfhsi 0, 0" + - + input: + bytes: [ 0xe5, 0x5d, 0x0f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfhsi 4095, 0" + - + input: + bytes: [ 0xe5, 0x5d, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfhsi 0, 65535" + - + input: + bytes: [ 0xe5, 0x5d, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfhsi 0(%r1), 42" + - + input: + bytes: [ 0xe5, 0x5d, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfhsi 0(%r15), 42" + - + input: + bytes: [ 0xe5, 0x5d, 0x1f, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfhsi 4095(%r1), 42" + - + input: + bytes: [ 0xe5, 0x5d, 0xff, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfhsi 4095(%r15), 42" + - + input: + bytes: [ 0xc2, 0x0f, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfi %r0, 0" + - + input: + bytes: [ 0xc2, 0x0f, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfi %r0, 4294967295" + - + input: + bytes: [ 0xc2, 0xff, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clfi %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x21 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clg %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x21 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clg %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x21 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clg %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x21 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clg %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x21 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clg %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x21 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clg %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x21 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clg %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x21 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clg %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x21 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clg %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x21 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clg %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x31 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgf %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x31 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgf %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x31 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgf %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x31 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgf %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x31 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgf %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x31 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgf %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x31 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgf %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x31 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgf %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x31 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgf %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x31 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgf %r15, 0" + - + input: + bytes: [ 0xc2, 0x0e, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgfi %r0, 0" + - + input: + bytes: [ 0xc2, 0x0e, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgfi %r0, 4294967295" + - + input: + bytes: [ 0xc2, 0xfe, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgfi %r15, 0" + - + input: + bytes: [ 0xb9, 0x31, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgfr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x31, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgfr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x31, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgfr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x31, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgfr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x21, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x21, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x21, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x21, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clgr %r7, %r8" + - + input: + bytes: [ 0xe5, 0x55, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clhhsi 0, 0" + - + input: + bytes: [ 0xe5, 0x55, 0x0f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clhhsi 4095, 0" + - + input: + bytes: [ 0xe5, 0x55, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clhhsi 0, 65535" + - + input: + bytes: [ 0xe5, 0x55, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clhhsi 0(%r1), 42" + - + input: + bytes: [ 0xe5, 0x55, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clhhsi 0(%r15), 42" + - + input: + bytes: [ 0xe5, 0x55, 0x1f, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clhhsi 4095(%r1), 42" + - + input: + bytes: [ 0xe5, 0x55, 0xff, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clhhsi 4095(%r15), 42" + - + input: + bytes: [ 0x95, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cli 0, 0" + - + input: + bytes: [ 0x95, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cli 4095, 0" + - + input: + bytes: [ 0x95, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cli 0, 255" + - + input: + bytes: [ 0x95, 0x2a, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cli 0(%r1), 42" + - + input: + bytes: [ 0x95, 0x2a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cli 0(%r15), 42" + - + input: + bytes: [ 0x95, 0x2a, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cli 4095(%r1), 42" + - + input: + bytes: [ 0x95, 0x2a, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cli 4095(%r15), 42" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cliy -524288, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cliy -1, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cliy 0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cliy 1, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cliy 524287, 0" + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cliy 0, 255" + - + input: + bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cliy 0(%r1), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cliy 0(%r15), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cliy 524287(%r1), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cliy 524287(%r15), 42" + - + input: + bytes: [ 0x15, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clr %r0, %r0" + - + input: + bytes: [ 0x15, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clr %r0, %r15" + - + input: + bytes: [ 0x15, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clr %r15, %r0" + - + input: + bytes: [ 0x15, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clr %r7, %r8" + - + input: + bytes: [ 0xb2, 0x5d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clst %r0, %r0" + - + input: + bytes: [ 0xb2, 0x5d, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clst %r0, %r15" + - + input: + bytes: [ 0xb2, 0x5d, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clst %r15, %r0" + - + input: + bytes: [ 0xb2, 0x5d, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "clst %r7, %r8" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cly %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cly %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cly %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cly %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cly %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cly %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cly %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cly %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cly %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cly %r15, 0" + - + input: + bytes: [ 0xb3, 0x72, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cpsdr %f0, %f0, %f0" + - + input: + bytes: [ 0xb3, 0x72, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cpsdr %f0, %f0, %f15" + - + input: + bytes: [ 0xb3, 0x72, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cpsdr %f0, %f15, %f0" + - + input: + bytes: [ 0xb3, 0x72, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cpsdr %f15, %f0, %f0" + - + input: + bytes: [ 0xb3, 0x72, 0x20, 0x13 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cpsdr %f1, %f2, %f3" + - + input: + bytes: [ 0xb3, 0x72, 0xf0, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cpsdr %f15, %f15, %f15" + - + input: + bytes: [ 0x19, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cr %r0, %r0" + - + input: + bytes: [ 0x19, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cr %r0, %r15" + - + input: + bytes: [ 0x19, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cr %r15, %r0" + - + input: + bytes: [ 0x19, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cr %r7, %r8" + - + input: + bytes: [ 0xba, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cs %r0, %r0, 0" + - + input: + bytes: [ 0xba, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cs %r0, %r0, 4095" + - + input: + bytes: [ 0xba, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cs %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xba, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cs %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xba, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cs %r0, %r0, 4095(%r1)" + - + input: + bytes: [ 0xba, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cs %r0, %r0, 4095(%r15)" + - + input: + bytes: [ 0xba, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cs %r0, %r15, 0" + - + input: + bytes: [ 0xba, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cs %r15, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csg %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csg %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csg %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csg %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csg %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csg %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csg %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csg %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csg %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csg %r0, %r15, 0" + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0x30 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csg %r15, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csy %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csy %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csy %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csy %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csy %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csy %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csy %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csy %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csy %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csy %r0, %r15, 0" + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "csy %r15, %r0, 0" + - + input: + bytes: [ 0xb3, 0x49, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxbr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x49, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxbr %f0, %f13" + - + input: + bytes: [ 0xb3, 0x49, 0x00, 0x88 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxbr %f8, %f8" + - + input: + bytes: [ 0xb3, 0x49, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxbr %f13, %f0" + - + input: + bytes: [ 0xb3, 0x96, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxfbr %f0, %r0" + - + input: + bytes: [ 0xb3, 0x96, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxfbr %f0, %r15" + - + input: + bytes: [ 0xb3, 0x96, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxfbr %f13, %r0" + - + input: + bytes: [ 0xb3, 0x96, 0x00, 0x87 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxfbr %f8, %r7" + - + input: + bytes: [ 0xb3, 0x96, 0x00, 0xdf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxfbr %f13, %r15" + - + input: + bytes: [ 0xb3, 0xa6, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxgbr %f0, %r0" + - + input: + bytes: [ 0xb3, 0xa6, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxgbr %f0, %r15" + - + input: + bytes: [ 0xb3, 0xa6, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxgbr %f13, %r0" + - + input: + bytes: [ 0xb3, 0xa6, 0x00, 0x87 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxgbr %f8, %r7" + - + input: + bytes: [ 0xb3, 0xa6, 0x00, 0xdf ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cxgbr %f13, %r15" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x59 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cy %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x59 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cy %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x59 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cy %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x59 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cy %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x59 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cy %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x59 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cy %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x59 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cy %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x59 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cy %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x59 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cy %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x59 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "cy %r15, 0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ddb %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ddb %f0, 4095" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ddb %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ddb %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ddb %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ddb %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ddb %f15, 0" + - + input: + bytes: [ 0xb3, 0x1d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ddbr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x1d, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ddbr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x1d, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ddbr %f7, %f8" + - + input: + bytes: [ 0xb3, 0x1d, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ddbr %f15, %f0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "deb %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "deb %f0, 4095" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "deb %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "deb %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "deb %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "deb %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "deb %f15, 0" + - + input: + bytes: [ 0xb3, 0x0d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "debr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x0d, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "debr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x0d, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "debr %f7, %f8" + - + input: + bytes: [ 0xb3, 0x0d, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "debr %f15, %f0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x97 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dl %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x97 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dl %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x97 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dl %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x97 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dl %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x97 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dl %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x97 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dl %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x97 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dl %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x97 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dl %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x97 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dl %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x97 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dl %r14, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x87 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlg %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x87 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlg %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x87 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlg %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x87 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlg %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x87 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlg %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x87 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlg %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x87 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlg %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x87 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlg %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x87 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlg %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x87 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlg %r14, 0" + - + input: + bytes: [ 0xb9, 0x87, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlgr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x87, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlgr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x87, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlgr %r14, %r0" + - + input: + bytes: [ 0xb9, 0x87, 0x00, 0x69 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlgr %r6, %r9" + - + input: + bytes: [ 0xb9, 0x97, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x97, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x97, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlr %r14, %r0" + - + input: + bytes: [ 0xb9, 0x97, 0x00, 0x69 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlr %r6, %r9" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsg %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsg %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsg %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsg %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsg %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsg %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsg %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsg %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsg %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsg %r14, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsgf %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsgf %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsgf %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsgf %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsgf %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsgf %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsgf %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsgf %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsgf %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsgf %r14, 0" + - + input: + bytes: [ 0xb9, 0x1d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsgfr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x1d, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsgfr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x1d, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsgfr %r14, %r0" + - + input: + bytes: [ 0xb9, 0x1d, 0x00, 0x69 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsgfr %r6, %r9" + - + input: + bytes: [ 0xb9, 0x0d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsgr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x0d, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsgr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x0d, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsgr %r14, %r0" + - + input: + bytes: [ 0xb9, 0x0d, 0x00, 0x69 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dsgr %r6, %r9" + - + input: + bytes: [ 0xb3, 0x4d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dxbr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x4d, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dxbr %f0, %f13" + - + input: + bytes: [ 0xb3, 0x4d, 0x00, 0x88 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dxbr %f8, %f8" + - + input: + bytes: [ 0xb3, 0x4d, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dxbr %f13, %f0" + - + input: + bytes: [ 0xb2, 0x4f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ear %r0, %a0" + - + input: + bytes: [ 0xb2, 0x4f, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ear %r0, %a15" + - + input: + bytes: [ 0xb2, 0x4f, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ear %r15, %a0" + - + input: + bytes: [ 0xb2, 0x4f, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ear %r7, %a8" + - + input: + bytes: [ 0xb2, 0x4f, 0x00, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ear %r15, %a15" + - + input: + bytes: [ 0xb3, 0x5f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fidbr %f0, 0, %f0" + - + input: + bytes: [ 0xb3, 0x5f, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fidbr %f0, 0, %f15" + - + input: + bytes: [ 0xb3, 0x5f, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fidbr %f0, 15, %f0" + - + input: + bytes: [ 0xb3, 0x5f, 0x50, 0x46 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fidbr %f4, 5, %f6" + - + input: + bytes: [ 0xb3, 0x5f, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fidbr %f15, 0, %f0" + - + input: + bytes: [ 0xb3, 0x57, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fiebr %f0, 0, %f0" + - + input: + bytes: [ 0xb3, 0x57, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fiebr %f0, 0, %f15" + - + input: + bytes: [ 0xb3, 0x57, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fiebr %f0, 15, %f0" + - + input: + bytes: [ 0xb3, 0x57, 0x50, 0x46 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fiebr %f4, 5, %f6" + - + input: + bytes: [ 0xb3, 0x57, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fiebr %f15, 0, %f0" + - + input: + bytes: [ 0xb3, 0x47, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fixbr %f0, 0, %f0" + - + input: + bytes: [ 0xb3, 0x47, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fixbr %f0, 0, %f13" + - + input: + bytes: [ 0xb3, 0x47, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fixbr %f0, 15, %f0" + - + input: + bytes: [ 0xb3, 0x47, 0x50, 0x48 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fixbr %f4, 5, %f8" + - + input: + bytes: [ 0xb3, 0x47, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "fixbr %f13, 0, %f0" + - + input: + bytes: [ 0xb9, 0x83, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "flogr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x83, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "flogr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x83, 0x00, 0xa9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "flogr %r10, %r9" + - + input: + bytes: [ 0xb9, 0x83, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "flogr %r14, %r0" + - + input: + bytes: [ 0x43, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ic %r0, 0" + - + input: + bytes: [ 0x43, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ic %r0, 4095" + - + input: + bytes: [ 0x43, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ic %r0, 0(%r1)" + - + input: + bytes: [ 0x43, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ic %r0, 0(%r15)" + - + input: + bytes: [ 0x43, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ic %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x43, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ic %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x43, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ic %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x73 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "icy %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x73 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "icy %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x73 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "icy %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x73 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "icy %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x73 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "icy %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x73 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "icy %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x73 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "icy %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x73 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "icy %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x73 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "icy %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x73 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "icy %r15, 0" + - + input: + bytes: [ 0xc0, 0x08, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iihf %r0, 0" + - + input: + bytes: [ 0xc0, 0x08, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iihf %r0, 4294967295" + - + input: + bytes: [ 0xc0, 0xf8, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iihf %r15, 0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iihh %r0, 0" + - + input: + bytes: [ 0xa5, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iihh %r0, 32768" + - + input: + bytes: [ 0xa5, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iihh %r0, 65535" + - + input: + bytes: [ 0xa5, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iihh %r15, 0" + - + input: + bytes: [ 0xa5, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iihl %r0, 0" + - + input: + bytes: [ 0xa5, 0x01, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iihl %r0, 32768" + - + input: + bytes: [ 0xa5, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iihl %r0, 65535" + - + input: + bytes: [ 0xa5, 0xf1, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iihl %r15, 0" + - + input: + bytes: [ 0xc0, 0x09, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iilf %r0, 0" + - + input: + bytes: [ 0xc0, 0x09, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iilf %r0, 4294967295" + - + input: + bytes: [ 0xc0, 0xf9, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iilf %r15, 0" + - + input: + bytes: [ 0xa5, 0x02, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iilh %r0, 0" + - + input: + bytes: [ 0xa5, 0x02, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iilh %r0, 32768" + - + input: + bytes: [ 0xa5, 0x02, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iilh %r0, 65535" + - + input: + bytes: [ 0xa5, 0xf2, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iilh %r15, 0" + - + input: + bytes: [ 0xa5, 0x03, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iill %r0, 0" + - + input: + bytes: [ 0xa5, 0x03, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iill %r0, 32768" + - + input: + bytes: [ 0xa5, 0x03, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iill %r0, 65535" + - + input: + bytes: [ 0xa5, 0xf3, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "iill %r15, 0" + - + input: + bytes: [ 0xb2, 0x22, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ipm %r0" + - + input: + bytes: [ 0xb2, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ipm %r1" + - + input: + bytes: [ 0xb2, 0x22, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ipm %r15" + - + input: + bytes: [ 0x58, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "l %r0, 0" + - + input: + bytes: [ 0x58, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "l %r0, 4095" + - + input: + bytes: [ 0x58, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "l %r0, 0(%r1)" + - + input: + bytes: [ 0x58, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "l %r0, 0(%r15)" + - + input: + bytes: [ 0x58, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "l %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x58, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "l %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x58, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "l %r15, 0" + - + input: + bytes: [ 0x41, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "la %r0, 0" + - + input: + bytes: [ 0x41, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "la %r0, 4095" + - + input: + bytes: [ 0x41, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "la %r0, 0(%r1)" + - + input: + bytes: [ 0x41, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "la %r0, 0(%r15)" + - + input: + bytes: [ 0x41, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "la %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x41, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "la %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x41, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "la %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x71 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lay %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x71 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lay %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x71 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lay %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x71 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lay %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x71 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lay %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x71 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lay %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x71 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lay %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x71 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lay %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x71 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lay %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x71 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lay %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x76 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lb %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x76 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lb %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x76 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lb %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x76 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lb %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x76 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lb %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x76 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lb %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x76 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lb %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x76 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lb %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x76 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lb %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x76 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lb %r15, 0" + - + input: + bytes: [ 0xb9, 0x26, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lbr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x26, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lbr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x26, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lbr %r15, %r0" + - + input: + bytes: [ 0xb3, 0x13, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcdbr %f0, %f9" + - + input: + bytes: [ 0xb3, 0x13, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcdbr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x13, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcdbr %f15, %f0" + - + input: + bytes: [ 0xb3, 0x13, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcdbr %f15, %f9" + - + input: + bytes: [ 0xb3, 0x03, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcebr %f0, %f9" + - + input: + bytes: [ 0xb3, 0x03, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcebr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x03, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcebr %f15, %f0" + - + input: + bytes: [ 0xb3, 0x03, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcebr %f15, %f9" + - + input: + bytes: [ 0xb9, 0x13, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcgfr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x13, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcgfr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x13, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcgfr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x13, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcgfr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x03, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcgr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x03, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcgr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x03, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcgr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x03, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcgr %r7, %r8" + - + input: + bytes: [ 0x13, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcr %r0, %r0" + - + input: + bytes: [ 0x13, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcr %r0, %r15" + - + input: + bytes: [ 0x13, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcr %r15, %r0" + - + input: + bytes: [ 0x13, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcr %r7, %r8" + - + input: + bytes: [ 0xb3, 0x43, 0x00, 0x08 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcxbr %f0, %f8" + - + input: + bytes: [ 0xb3, 0x43, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcxbr %f0, %f13" + - + input: + bytes: [ 0xb3, 0x43, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcxbr %f13, %f0" + - + input: + bytes: [ 0xb3, 0x43, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lcxbr %f13, %f9" + - + input: + bytes: [ 0x68, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ld %f0, 0" + - + input: + bytes: [ 0x68, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ld %f0, 4095" + - + input: + bytes: [ 0x68, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ld %f0, 0(%r1)" + - + input: + bytes: [ 0x68, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ld %f0, 0(%r15)" + - + input: + bytes: [ 0x68, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ld %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x68, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ld %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x68, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ld %f15, 0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldeb %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldeb %f0, 4095" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldeb %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldeb %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldeb %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldeb %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldeb %f15, 0" + - + input: + bytes: [ 0xb3, 0x04, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldebr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x04, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldebr %f7, %f8" + - + input: + bytes: [ 0xb3, 0x04, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldebr %f15, %f0" + - + input: + bytes: [ 0xb3, 0xc1, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldgr %f0, %r0" + - + input: + bytes: [ 0xb3, 0xc1, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldgr %f0, %r15" + - + input: + bytes: [ 0xb3, 0xc1, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldgr %f15, %r0" + - + input: + bytes: [ 0xb3, 0xc1, 0x00, 0x79 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldgr %f7, %r9" + - + input: + bytes: [ 0xb3, 0xc1, 0x00, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldgr %f15, %r15" + - + input: + bytes: [ 0x28, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldr %f0, %f9" + - + input: + bytes: [ 0x28, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldr %f0, %f15" + - + input: + bytes: [ 0x28, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldr %f15, %f0" + - + input: + bytes: [ 0x28, 0xf9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldr %f15, %f9" + - + input: + bytes: [ 0xb3, 0x45, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldxbr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x45, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldxbr %f0, %f13" + - + input: + bytes: [ 0xb3, 0x45, 0x00, 0x8c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldxbr %f8, %f12" + - + input: + bytes: [ 0xb3, 0x45, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldxbr %f13, %f0" + - + input: + bytes: [ 0xb3, 0x45, 0x00, 0xdd ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldxbr %f13, %f13" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x80, 0x65 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldy %f0, -524288" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0xff, 0x65 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldy %f0, -1" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x65 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldy %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x01, 0x00, 0x65 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldy %f0, 1" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x7f, 0x65 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldy %f0, 524287" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x65 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldy %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x65 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldy %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x7f, 0x65 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldy %f0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x7f, 0x65 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldy %f0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x65 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldy %f15, 0" + - + input: + bytes: [ 0x78, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "le %f0, 0" + - + input: + bytes: [ 0x78, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "le %f0, 4095" + - + input: + bytes: [ 0x78, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "le %f0, 0(%r1)" + - + input: + bytes: [ 0x78, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "le %f0, 0(%r15)" + - + input: + bytes: [ 0x78, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "le %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x78, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "le %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x78, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "le %f15, 0" + - + input: + bytes: [ 0xb3, 0x44, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ledbr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x44, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ledbr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x44, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ledbr %f7, %f8" + - + input: + bytes: [ 0xb3, 0x44, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ledbr %f15, %f0" + - + input: + bytes: [ 0xb3, 0x44, 0x00, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ledbr %f15, %f15" + - + input: + bytes: [ 0x38, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ler %f0, %f9" + - + input: + bytes: [ 0x38, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ler %f0, %f15" + - + input: + bytes: [ 0x38, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ler %f15, %f0" + - + input: + bytes: [ 0x38, 0xf9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ler %f15, %f9" + - + input: + bytes: [ 0xb3, 0x46, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lexbr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x46, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lexbr %f0, %f13" + - + input: + bytes: [ 0xb3, 0x46, 0x00, 0x8c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lexbr %f8, %f12" + - + input: + bytes: [ 0xb3, 0x46, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lexbr %f13, %f0" + - + input: + bytes: [ 0xb3, 0x46, 0x00, 0xdd ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lexbr %f13, %f13" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x80, 0x64 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ley %f0, -524288" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0xff, 0x64 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ley %f0, -1" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x64 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ley %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x01, 0x00, 0x64 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ley %f0, 1" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x7f, 0x64 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ley %f0, 524287" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x64 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ley %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x64 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ley %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x7f, 0x64 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ley %f0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x7f, 0x64 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ley %f0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x64 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ley %f15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lg %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lg %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lg %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lg %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lg %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lg %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lg %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lg %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lg %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lg %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x77 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgb %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x77 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgb %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x77 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgb %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x77 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgb %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x77 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgb %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x77 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgb %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x77 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgb %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x77 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgb %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x77 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgb %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x77 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgb %r15, 0" + - + input: + bytes: [ 0xb9, 0x06, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgbr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x06, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgbr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x06, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgbr %r15, %r0" + - + input: + bytes: [ 0xb3, 0xcd, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgdr %r0, %f0" + - + input: + bytes: [ 0xb3, 0xcd, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgdr %r0, %f15" + - + input: + bytes: [ 0xb3, 0xcd, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgdr %r15, %f0" + - + input: + bytes: [ 0xb3, 0xcd, 0x00, 0x88 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgdr %r8, %f8" + - + input: + bytes: [ 0xb3, 0xcd, 0x00, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgdr %r15, %f15" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgf %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgf %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgf %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgf %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgf %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgf %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgf %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgf %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgf %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgf %r15, 0" + - + input: + bytes: [ 0xc0, 0x01, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgfi %r0, -2147483648" + - + input: + bytes: [ 0xc0, 0x01, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgfi %r0, -1" + - + input: + bytes: [ 0xc0, 0x01, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgfi %r0, 0" + - + input: + bytes: [ 0xc0, 0x01, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgfi %r0, 1" + - + input: + bytes: [ 0xc0, 0x01, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgfi %r0, 2147483647" + - + input: + bytes: [ 0xc0, 0xf1, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgfi %r15, 0" + - + input: + bytes: [ 0xb9, 0x14, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgfr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x14, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgfr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x14, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgfr %r15, %r0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x15 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgh %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x15 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgh %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x15 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgh %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x15 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgh %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x15 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgh %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x15 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgh %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x15 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgh %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x15 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgh %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x15 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgh %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x15 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgh %r15, 0" + - + input: + bytes: [ 0xa7, 0x09, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lghi %r0, -32768" + - + input: + bytes: [ 0xa7, 0x09, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lghi %r0, -1" + - + input: + bytes: [ 0xa7, 0x09, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lghi %r0, 0" + - + input: + bytes: [ 0xa7, 0x09, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lghi %r0, 1" + - + input: + bytes: [ 0xa7, 0x09, 0x7f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lghi %r0, 32767" + - + input: + bytes: [ 0xa7, 0xf9, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lghi %r15, 0" + - + input: + bytes: [ 0xb9, 0x07, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lghr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x07, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lghr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x07, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lghr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x04, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgr %r0, %r9" + - + input: + bytes: [ 0xb9, 0x04, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x04, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x04, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgr %r15, %r9" + - + input: + bytes: [ 0x48, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lh %r0, 0" + - + input: + bytes: [ 0x48, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lh %r0, 4095" + - + input: + bytes: [ 0x48, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lh %r0, 0(%r1)" + - + input: + bytes: [ 0x48, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lh %r0, 0(%r15)" + - + input: + bytes: [ 0x48, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lh %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x48, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lh %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x48, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lh %r15, 0" + - + input: + bytes: [ 0xa7, 0x08, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhi %r0, -32768" + - + input: + bytes: [ 0xa7, 0x08, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhi %r0, -1" + - + input: + bytes: [ 0xa7, 0x08, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhi %r0, 0" + - + input: + bytes: [ 0xa7, 0x08, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhi %r0, 1" + - + input: + bytes: [ 0xa7, 0x08, 0x7f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhi %r0, 32767" + - + input: + bytes: [ 0xa7, 0xf8, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhi %r15, 0" + - + input: + bytes: [ 0xb9, 0x27, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x27, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x27, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhr %r15, %r0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhy %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhy %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhy %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhy %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhy %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhy %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhy %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhy %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhy %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lhy %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x94 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llc %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x94 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llc %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x94 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llc %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x94 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llc %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x94 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llc %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x94 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llc %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x94 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llc %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x94 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llc %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x94 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llc %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x94 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llc %r15, 0" + - + input: + bytes: [ 0xb9, 0x94, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llcr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x94, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llcr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x94, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llcr %r15, %r0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x90 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgc %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x90 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgc %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x90 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgc %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x90 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgc %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x90 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgc %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x90 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgc %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x90 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgc %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x90 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgc %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x90 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgc %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x90 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgc %r15, 0" + - + input: + bytes: [ 0xb9, 0x84, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgcr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x84, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgcr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x84, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgcr %r15, %r0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x16 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgf %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x16 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgf %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x16 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgf %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x16 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgf %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x16 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgf %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x16 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgf %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x16 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgf %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x16 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgf %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x16 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgf %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x16 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgf %r15, 0" + - + input: + bytes: [ 0xb9, 0x16, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgfr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x16, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgfr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x16, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgfr %r15, %r0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x91 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgh %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x91 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgh %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x91 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgh %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x91 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgh %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x91 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgh %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x91 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgh %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x91 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgh %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x91 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgh %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x91 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgh %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x91 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llgh %r15, 0" + - + input: + bytes: [ 0xb9, 0x85, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llghr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x85, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llghr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x85, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llghr %r15, %r0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x95 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llh %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x95 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llh %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x95 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llh %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x95 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llh %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x95 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llh %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x95 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llh %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x95 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llh %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x95 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llh %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x95 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llh %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x95 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llh %r15, 0" + - + input: + bytes: [ 0xb9, 0x95, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llhr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x95, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llhr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x95, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llhr %r15, %r0" + - + input: + bytes: [ 0xc0, 0x0e, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llihf %r0, 0" + - + input: + bytes: [ 0xc0, 0x0e, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llihf %r0, 4294967295" + - + input: + bytes: [ 0xc0, 0xfe, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llihf %r15, 0" + - + input: + bytes: [ 0xa5, 0x0c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llihh %r0, 0" + - + input: + bytes: [ 0xa5, 0x0c, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llihh %r0, 32768" + - + input: + bytes: [ 0xa5, 0x0c, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llihh %r0, 65535" + - + input: + bytes: [ 0xa5, 0xfc, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llihh %r15, 0" + - + input: + bytes: [ 0xa5, 0x0d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llihl %r0, 0" + - + input: + bytes: [ 0xa5, 0x0d, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llihl %r0, 32768" + - + input: + bytes: [ 0xa5, 0x0d, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llihl %r0, 65535" + - + input: + bytes: [ 0xa5, 0xfd, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llihl %r15, 0" + - + input: + bytes: [ 0xc0, 0x0f, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llilf %r0, 0" + - + input: + bytes: [ 0xc0, 0x0f, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llilf %r0, 4294967295" + - + input: + bytes: [ 0xc0, 0xff, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llilf %r15, 0" + - + input: + bytes: [ 0xa5, 0x0e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llilh %r0, 0" + - + input: + bytes: [ 0xa5, 0x0e, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llilh %r0, 32768" + - + input: + bytes: [ 0xa5, 0x0e, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llilh %r0, 65535" + - + input: + bytes: [ 0xa5, 0xfe, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llilh %r15, 0" + - + input: + bytes: [ 0xa5, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llill %r0, 0" + - + input: + bytes: [ 0xa5, 0x0f, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llill %r0, 32768" + - + input: + bytes: [ 0xa5, 0x0f, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llill %r0, 65535" + - + input: + bytes: [ 0xa5, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "llill %r15, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lmg %r0, %r15, 0" + - + input: + bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lmg %r14, %r15, 0" + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lmg %r15, %r15, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x04 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0xb3, 0x11, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lndbr %f0, %f9" + - + input: + bytes: [ 0xb3, 0x11, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lndbr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x11, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lndbr %f15, %f0" + - + input: + bytes: [ 0xb3, 0x11, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lndbr %f15, %f9" + - + input: + bytes: [ 0xb3, 0x01, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lnebr %f0, %f9" + - + input: + bytes: [ 0xb3, 0x01, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lnebr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x01, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lnebr %f15, %f0" + - + input: + bytes: [ 0xb3, 0x01, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lnebr %f15, %f9" + - + input: + bytes: [ 0xb9, 0x11, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lngfr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x11, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lngfr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x11, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lngfr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x11, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lngfr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lngr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x01, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lngr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x01, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lngr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x01, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lngr %r7, %r8" + - + input: + bytes: [ 0x11, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lnr %r0, %r0" + - + input: + bytes: [ 0x11, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lnr %r0, %r15" + - + input: + bytes: [ 0x11, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lnr %r15, %r0" + - + input: + bytes: [ 0x11, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lnr %r7, %r8" + - + input: + bytes: [ 0xb3, 0x41, 0x00, 0x08 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lnxbr %f0, %f8" + - + input: + bytes: [ 0xb3, 0x41, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lnxbr %f0, %f13" + - + input: + bytes: [ 0xb3, 0x41, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lnxbr %f13, %f0" + - + input: + bytes: [ 0xb3, 0x41, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lnxbr %f13, %f9" + - + input: + bytes: [ 0xb3, 0x10, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpdbr %f0, %f9" + - + input: + bytes: [ 0xb3, 0x10, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpdbr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x10, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpdbr %f15, %f0" + - + input: + bytes: [ 0xb3, 0x10, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpdbr %f15, %f9" + - + input: + bytes: [ 0xb3, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpebr %f0, %f9" + - + input: + bytes: [ 0xb3, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpebr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x00, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpebr %f15, %f0" + - + input: + bytes: [ 0xb3, 0x00, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpebr %f15, %f9" + - + input: + bytes: [ 0xb9, 0x10, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpgfr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x10, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpgfr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x10, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpgfr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x10, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpgfr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpgr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpgr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x00, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpgr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x00, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpgr %r7, %r8" + - + input: + bytes: [ 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpr %r0, %r0" + - + input: + bytes: [ 0x10, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpr %r0, %r15" + - + input: + bytes: [ 0x10, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpr %r15, %r0" + - + input: + bytes: [ 0x10, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpr %r7, %r8" + - + input: + bytes: [ 0xb3, 0x40, 0x00, 0x08 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpxbr %f0, %f8" + - + input: + bytes: [ 0xb3, 0x40, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpxbr %f0, %f13" + - + input: + bytes: [ 0xb3, 0x40, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpxbr %f13, %f0" + - + input: + bytes: [ 0xb3, 0x40, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lpxbr %f13, %f9" + - + input: + bytes: [ 0x18, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lr %r0, %r9" + - + input: + bytes: [ 0x18, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lr %r0, %r15" + - + input: + bytes: [ 0x18, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lr %r15, %r0" + - + input: + bytes: [ 0x18, 0xf9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lr %r15, %r9" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrv %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrv %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrv %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrv %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrv %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrv %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrv %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrv %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrv %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x1e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrv %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvg %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvg %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvg %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvg %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvg %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvg %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvg %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvg %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvg %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvg %r15, 0" + - + input: + bytes: [ 0xb9, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvgr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x0f, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvgr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x0f, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvgr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x0f, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvgr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x0f, 0x00, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvgr %r15, %r15" + - + input: + bytes: [ 0xb9, 0x1f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x1f, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x1f, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x1f, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x1f, 0x00, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lrvr %r15, %r15" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x12 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lt %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x12 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lt %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x12 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lt %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x12 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lt %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x12 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lt %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x12 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lt %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x12 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lt %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x12 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lt %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x12 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lt %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x12 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lt %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x02 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltg %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x02 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltg %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltg %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltg %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x02 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltg %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltg %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltg %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x02 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltg %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x02 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltg %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltg %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x32 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltgf %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x32 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltgf %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x32 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltgf %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x32 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltgf %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x32 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltgf %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x32 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltgf %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x32 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltgf %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x32 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltgf %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x32 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltgf %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x32 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltgf %r15, 0" + - + input: + bytes: [ 0xb3, 0x12, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltdbr %f0, %f9" + - + input: + bytes: [ 0xb3, 0x12, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltdbr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x12, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltdbr %f15, %f0" + - + input: + bytes: [ 0xb3, 0x12, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltdbr %f15, %f9" + - + input: + bytes: [ 0xb3, 0x02, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltebr %f0, %f9" + - + input: + bytes: [ 0xb3, 0x02, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltebr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x02, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltebr %f15, %f0" + - + input: + bytes: [ 0xb3, 0x02, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltebr %f15, %f9" + - + input: + bytes: [ 0xb9, 0x12, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltgfr %r0, %r9" + - + input: + bytes: [ 0xb9, 0x12, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltgfr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x12, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltgfr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x12, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltgfr %r15, %r9" + - + input: + bytes: [ 0xb9, 0x02, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltgr %r0, %r9" + - + input: + bytes: [ 0xb9, 0x02, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltgr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x02, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltgr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x02, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltgr %r15, %r9" + - + input: + bytes: [ 0x12, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltr %r0, %r9" + - + input: + bytes: [ 0x12, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltr %r0, %r15" + - + input: + bytes: [ 0x12, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltr %r15, %r0" + - + input: + bytes: [ 0x12, 0xf9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltr %r15, %r9" + - + input: + bytes: [ 0xb3, 0x42, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltxbr %f0, %f9" + - + input: + bytes: [ 0xb3, 0x42, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltxbr %f0, %f13" + - + input: + bytes: [ 0xb3, 0x42, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltxbr %f13, %f0" + - + input: + bytes: [ 0xb3, 0x42, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ltxbr %f13, %f9" + - + input: + bytes: [ 0xb3, 0x65, 0x00, 0x08 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lxr %f0, %f8" + - + input: + bytes: [ 0xb3, 0x65, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lxr %f0, %f13" + - + input: + bytes: [ 0xb3, 0x65, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lxr %f13, %f0" + - + input: + bytes: [ 0xb3, 0x65, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lxr %f13, %f9" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x58 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ly %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x58 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ly %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ly %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x58 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ly %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x58 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ly %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ly %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ly %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x58 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ly %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x58 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ly %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ly %r15, 0" + - + input: + bytes: [ 0xb3, 0x75, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lzdr %f0" + - + input: + bytes: [ 0xb3, 0x75, 0x00, 0x70 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lzdr %f7" + - + input: + bytes: [ 0xb3, 0x75, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lzdr %f15" + - + input: + bytes: [ 0xb3, 0x74, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lzer %f0" + - + input: + bytes: [ 0xb3, 0x74, 0x00, 0x70 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lzer %f7" + - + input: + bytes: [ 0xb3, 0x74, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lzer %f15" + - + input: + bytes: [ 0xb3, 0x76, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lzxr %f0" + - + input: + bytes: [ 0xb3, 0x76, 0x00, 0x80 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lzxr %f8" + - + input: + bytes: [ 0xb3, 0x76, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lzxr %f13" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "madb %f0, %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "madb %f0, %f0, 4095" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "madb %f0, %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "madb %f0, %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "madb %f0, %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "madb %f0, %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "madb %f0, %f15, 0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x1e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "madb %f15, %f0, 0" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x1e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "madb %f15, %f15, 0" + - + input: + bytes: [ 0xb3, 0x1e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "madbr %f0, %f0, %f0" + - + input: + bytes: [ 0xb3, 0x1e, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "madbr %f0, %f0, %f15" + - + input: + bytes: [ 0xb3, 0x1e, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "madbr %f0, %f15, %f0" + - + input: + bytes: [ 0xb3, 0x1e, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "madbr %f15, %f0, %f0" + - + input: + bytes: [ 0xb3, 0x1e, 0x70, 0x89 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "madbr %f7, %f8, %f9" + - + input: + bytes: [ 0xb3, 0x1e, 0xf0, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "madbr %f15, %f15, %f15" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "maeb %f0, %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "maeb %f0, %f0, 4095" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "maeb %f0, %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "maeb %f0, %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "maeb %f0, %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "maeb %f0, %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "maeb %f0, %f15, 0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x0e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "maeb %f15, %f0, 0" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x0e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "maeb %f15, %f15, 0" + - + input: + bytes: [ 0xb3, 0x0e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "maebr %f0, %f0, %f0" + - + input: + bytes: [ 0xb3, 0x0e, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "maebr %f0, %f0, %f15" + - + input: + bytes: [ 0xb3, 0x0e, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "maebr %f0, %f15, %f0" + - + input: + bytes: [ 0xb3, 0x0e, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "maebr %f15, %f0, %f0" + - + input: + bytes: [ 0xb3, 0x0e, 0x70, 0x89 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "maebr %f7, %f8, %f9" + - + input: + bytes: [ 0xb3, 0x0e, 0xf0, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "maebr %f15, %f15, %f15" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdb %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdb %f0, 4095" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdb %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdb %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdb %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdb %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdb %f15, 0" + - + input: + bytes: [ 0xb3, 0x1c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdbr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x1c, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdbr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x1c, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdbr %f7, %f8" + - + input: + bytes: [ 0xb3, 0x1c, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdbr %f15, %f0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdeb %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdeb %f0, 4095" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdeb %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdeb %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdeb %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdeb %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdeb %f15, 0" + - + input: + bytes: [ 0xb3, 0x0c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdebr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x0c, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdebr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x0c, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdebr %f7, %f8" + - + input: + bytes: [ 0xb3, 0x0c, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mdebr %f15, %f0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x17 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "meeb %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x17 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "meeb %f0, 4095" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x17 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "meeb %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x17 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "meeb %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x17 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "meeb %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x17 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "meeb %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x17 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "meeb %f15, 0" + - + input: + bytes: [ 0xb3, 0x17, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "meebr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x17, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "meebr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x17, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "meebr %f7, %f8" + - + input: + bytes: [ 0xb3, 0x17, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "meebr %f15, %f0" + - + input: + bytes: [ 0xa7, 0x0d, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mghi %r0, -32768" + - + input: + bytes: [ 0xa7, 0x0d, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mghi %r0, -1" + - + input: + bytes: [ 0xa7, 0x0d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mghi %r0, 0" + - + input: + bytes: [ 0xa7, 0x0d, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mghi %r0, 1" + - + input: + bytes: [ 0xa7, 0x0d, 0x7f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mghi %r0, 32767" + - + input: + bytes: [ 0xa7, 0xfd, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mghi %r15, 0" + - + input: + bytes: [ 0x4c, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mh %r0, 0" + - + input: + bytes: [ 0x4c, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mh %r0, 4095" + - + input: + bytes: [ 0x4c, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mh %r0, 0(%r1)" + - + input: + bytes: [ 0x4c, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mh %r0, 0(%r15)" + - + input: + bytes: [ 0x4c, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mh %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x4c, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mh %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x4c, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mh %r15, 0" + - + input: + bytes: [ 0xa7, 0x0c, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mhi %r0, -32768" + - + input: + bytes: [ 0xa7, 0x0c, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mhi %r0, -1" + - + input: + bytes: [ 0xa7, 0x0c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mhi %r0, 0" + - + input: + bytes: [ 0xa7, 0x0c, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mhi %r0, 1" + - + input: + bytes: [ 0xa7, 0x0c, 0x7f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mhi %r0, 32767" + - + input: + bytes: [ 0xa7, 0xfc, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mhi %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x7c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mhy %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x7c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mhy %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x7c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mhy %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x7c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mhy %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x7c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mhy %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x7c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mhy %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x7c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mhy %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x7c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mhy %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x7c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mhy %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x7c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mhy %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x86 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mlg %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x86 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mlg %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x86 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mlg %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x86 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mlg %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x86 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mlg %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x86 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mlg %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x86 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mlg %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x86 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mlg %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x86 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mlg %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x86 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mlg %r14, 0" + - + input: + bytes: [ 0xb9, 0x86, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mlgr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x86, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mlgr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x86, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mlgr %r14, %r0" + - + input: + bytes: [ 0xb9, 0x86, 0x00, 0x69 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mlgr %r6, %r9" + - + input: + bytes: [ 0x71, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ms %r0, 0" + - + input: + bytes: [ 0x71, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ms %r0, 4095" + - + input: + bytes: [ 0x71, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ms %r0, 0(%r1)" + - + input: + bytes: [ 0x71, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ms %r0, 0(%r15)" + - + input: + bytes: [ 0x71, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ms %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x71, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ms %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x71, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ms %r15, 0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msdb %f0, %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msdb %f0, %f0, 4095" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msdb %f0, %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msdb %f0, %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msdb %f0, %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msdb %f0, %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msdb %f0, %f15, 0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x1f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msdb %f15, %f0, 0" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x1f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msdb %f15, %f15, 0" + - + input: + bytes: [ 0xb3, 0x1f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msdbr %f0, %f0, %f0" + - + input: + bytes: [ 0xb3, 0x1f, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msdbr %f0, %f0, %f15" + - + input: + bytes: [ 0xb3, 0x1f, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msdbr %f0, %f15, %f0" + - + input: + bytes: [ 0xb3, 0x1f, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msdbr %f15, %f0, %f0" + - + input: + bytes: [ 0xb3, 0x1f, 0x70, 0x89 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msdbr %f7, %f8, %f9" + - + input: + bytes: [ 0xb3, 0x1f, 0xf0, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msdbr %f15, %f15, %f15" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mseb %f0, %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mseb %f0, %f0, 4095" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mseb %f0, %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mseb %f0, %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mseb %f0, %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mseb %f0, %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mseb %f0, %f15, 0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mseb %f15, %f0, 0" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mseb %f15, %f15, 0" + - + input: + bytes: [ 0xb3, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msebr %f0, %f0, %f0" + - + input: + bytes: [ 0xb3, 0x0f, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msebr %f0, %f0, %f15" + - + input: + bytes: [ 0xb3, 0x0f, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msebr %f0, %f15, %f0" + - + input: + bytes: [ 0xb3, 0x0f, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msebr %f15, %f0, %f0" + - + input: + bytes: [ 0xb3, 0x0f, 0x70, 0x89 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msebr %f7, %f8, %f9" + - + input: + bytes: [ 0xb3, 0x0f, 0xf0, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msebr %f15, %f15, %f15" + - + input: + bytes: [ 0xc2, 0x01, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msfi %r0, -2147483648" + - + input: + bytes: [ 0xc2, 0x01, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msfi %r0, -1" + - + input: + bytes: [ 0xc2, 0x01, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msfi %r0, 0" + - + input: + bytes: [ 0xc2, 0x01, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msfi %r0, 1" + - + input: + bytes: [ 0xc2, 0x01, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msfi %r0, 2147483647" + - + input: + bytes: [ 0xc2, 0xf1, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msfi %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msg %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msg %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msg %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msg %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msg %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msg %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msg %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msg %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msg %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msg %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgf %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgf %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgf %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgf %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgf %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgf %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgf %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgf %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgf %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgf %r15, 0" + - + input: + bytes: [ 0xc2, 0x00, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgfi %r0, -2147483648" + - + input: + bytes: [ 0xc2, 0x00, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgfi %r0, -1" + - + input: + bytes: [ 0xc2, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgfi %r0, 0" + - + input: + bytes: [ 0xc2, 0x00, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgfi %r0, 1" + - + input: + bytes: [ 0xc2, 0x00, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgfi %r0, 2147483647" + - + input: + bytes: [ 0xc2, 0xf0, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgfi %r15, 0" + - + input: + bytes: [ 0xb9, 0x1c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgfr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x1c, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgfr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x1c, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgfr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x1c, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgfr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x0c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x0c, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x0c, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x0c, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msgr %r7, %r8" + - + input: + bytes: [ 0xb2, 0x52, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msr %r0, %r0" + - + input: + bytes: [ 0xb2, 0x52, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msr %r0, %r15" + - + input: + bytes: [ 0xb2, 0x52, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msr %r15, %r0" + - + input: + bytes: [ 0xb2, 0x52, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msr %r7, %r8" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msy %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msy %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msy %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msy %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msy %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msy %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msy %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msy %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msy %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "msy %r15, 0" + - + input: + bytes: [ 0xd2, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvc 0(1), 0" + - + input: + bytes: [ 0xd2, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvc 0(1), 0(%r1)" + - + input: + bytes: [ 0xd2, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvc 0(1), 0(%r15)" + - + input: + bytes: [ 0xd2, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvc 0(1), 4095" + - + input: + bytes: [ 0xd2, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvc 0(1), 4095(%r1)" + - + input: + bytes: [ 0xd2, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvc 0(1), 4095(%r15)" + - + input: + bytes: [ 0xd2, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvc 0(1, %r1), 0" + - + input: + bytes: [ 0xd2, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvc 0(1, %r15), 0" + - + input: + bytes: [ 0xd2, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvc 4095(1, %r1), 0" + - + input: + bytes: [ 0xd2, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvc 4095(1, %r15), 0" + - + input: + bytes: [ 0xd2, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvc 0(256, %r1), 0" + - + input: + bytes: [ 0xd2, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvc 0(256, %r15), 0" + - + input: + bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvghi 0, 0" + - + input: + bytes: [ 0xe5, 0x48, 0x0f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvghi 4095, 0" + - + input: + bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvghi 0, -32768" + - + input: + bytes: [ 0xe5, 0x48, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvghi 0, -1" + - + input: + bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvghi 0, 0" + - + input: + bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvghi 0, 1" + - + input: + bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x7f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvghi 0, 32767" + - + input: + bytes: [ 0xe5, 0x48, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvghi 0(%r1), 42" + - + input: + bytes: [ 0xe5, 0x48, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvghi 0(%r15), 42" + - + input: + bytes: [ 0xe5, 0x48, 0x1f, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvghi 4095(%r1), 42" + - + input: + bytes: [ 0xe5, 0x48, 0xff, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvghi 4095(%r15), 42" + - + input: + bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhhi 0, 0" + - + input: + bytes: [ 0xe5, 0x44, 0x0f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhhi 4095, 0" + - + input: + bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhhi 0, -32768" + - + input: + bytes: [ 0xe5, 0x44, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhhi 0, -1" + - + input: + bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhhi 0, 0" + - + input: + bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhhi 0, 1" + - + input: + bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x7f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhhi 0, 32767" + - + input: + bytes: [ 0xe5, 0x44, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhhi 0(%r1), 42" + - + input: + bytes: [ 0xe5, 0x44, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhhi 0(%r15), 42" + - + input: + bytes: [ 0xe5, 0x44, 0x1f, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhhi 4095(%r1), 42" + - + input: + bytes: [ 0xe5, 0x44, 0xff, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhhi 4095(%r15), 42" + - + input: + bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhi 0, 0" + - + input: + bytes: [ 0xe5, 0x4c, 0x0f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhi 4095, 0" + - + input: + bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhi 0, -32768" + - + input: + bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhi 0, -1" + - + input: + bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhi 0, 0" + - + input: + bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhi 0, 1" + - + input: + bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x7f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhi 0, 32767" + - + input: + bytes: [ 0xe5, 0x4c, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhi 0(%r1), 42" + - + input: + bytes: [ 0xe5, 0x4c, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhi 0(%r15), 42" + - + input: + bytes: [ 0xe5, 0x4c, 0x1f, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhi 4095(%r1), 42" + - + input: + bytes: [ 0xe5, 0x4c, 0xff, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvhi 4095(%r15), 42" + - + input: + bytes: [ 0x92, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvi 0, 0" + - + input: + bytes: [ 0x92, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvi 4095, 0" + - + input: + bytes: [ 0x92, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvi 0, 255" + - + input: + bytes: [ 0x92, 0x2a, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvi 0(%r1), 42" + - + input: + bytes: [ 0x92, 0x2a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvi 0(%r15), 42" + - + input: + bytes: [ 0x92, 0x2a, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvi 4095(%r1), 42" + - + input: + bytes: [ 0x92, 0x2a, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvi 4095(%r15), 42" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x52 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mviy -524288, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x52 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mviy -1, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x52 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mviy 0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x52 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mviy 1, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x52 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mviy 524287, 0" + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x52 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mviy 0, 255" + - + input: + bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x52 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mviy 0(%r1), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x52 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mviy 0(%r15), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x52 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mviy 524287(%r1), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x52 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mviy 524287(%r15), 42" + - + input: + bytes: [ 0xb2, 0x55, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvst %r0, %r0" + - + input: + bytes: [ 0xb2, 0x55, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvst %r0, %r15" + - + input: + bytes: [ 0xb2, 0x55, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvst %r15, %r0" + - + input: + bytes: [ 0xb2, 0x55, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mvst %r7, %r8" + - + input: + bytes: [ 0xb3, 0x4c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mxbr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x4c, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mxbr %f0, %f13" + - + input: + bytes: [ 0xb3, 0x4c, 0x00, 0x85 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mxbr %f8, %f5" + - + input: + bytes: [ 0xb3, 0x4c, 0x00, 0xdd ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mxbr %f13, %f13" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mxdb %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x07 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mxdb %f0, 4095" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mxdb %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mxdb %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x07 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mxdb %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x07 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mxdb %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xd0, 0x00, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mxdb %f13, 0" + - + input: + bytes: [ 0xb3, 0x07, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mxdbr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x07, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mxdbr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x07, 0x00, 0x88 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mxdbr %f8, %f8" + - + input: + bytes: [ 0xb3, 0x07, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "mxdbr %f13, %f0" + - + input: + bytes: [ 0x54, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "n %r0, 0" + - + input: + bytes: [ 0x54, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "n %r0, 4095" + - + input: + bytes: [ 0x54, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "n %r0, 0(%r1)" + - + input: + bytes: [ 0x54, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "n %r0, 0(%r15)" + - + input: + bytes: [ 0x54, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "n %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x54, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "n %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x54, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "n %r15, 0" + - + input: + bytes: [ 0xd4, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nc 0(1), 0" + - + input: + bytes: [ 0xd4, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nc 0(1), 0(%r1)" + - + input: + bytes: [ 0xd4, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nc 0(1), 0(%r15)" + - + input: + bytes: [ 0xd4, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nc 0(1), 4095" + - + input: + bytes: [ 0xd4, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nc 0(1), 4095(%r1)" + - + input: + bytes: [ 0xd4, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nc 0(1), 4095(%r15)" + - + input: + bytes: [ 0xd4, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nc 0(1, %r1), 0" + - + input: + bytes: [ 0xd4, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nc 0(1, %r15), 0" + - + input: + bytes: [ 0xd4, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nc 4095(1, %r1), 0" + - + input: + bytes: [ 0xd4, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nc 4095(1, %r15), 0" + - + input: + bytes: [ 0xd4, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nc 0(256, %r1), 0" + - + input: + bytes: [ 0xd4, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nc 0(256, %r15), 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x80 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ng %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x80 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ng %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ng %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x80 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ng %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x80 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ng %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ng %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ng %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x80 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ng %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x80 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ng %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ng %r15, 0" + - + input: + bytes: [ 0xb9, 0x80, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ngr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x80, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ngr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x80, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ngr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x80, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ngr %r7, %r8" + - + input: + bytes: [ 0x94, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ni 0, 0" + - + input: + bytes: [ 0x94, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ni 4095, 0" + - + input: + bytes: [ 0x94, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ni 0, 255" + - + input: + bytes: [ 0x94, 0x2a, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ni 0(%r1), 42" + - + input: + bytes: [ 0x94, 0x2a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ni 0(%r15), 42" + - + input: + bytes: [ 0x94, 0x2a, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ni 4095(%r1), 42" + - + input: + bytes: [ 0x94, 0x2a, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ni 4095(%r15), 42" + - + input: + bytes: [ 0xc0, 0x0a, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nihf %r0, 0" + - + input: + bytes: [ 0xc0, 0x0a, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nihf %r0, 4294967295" + - + input: + bytes: [ 0xc0, 0xfa, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nihf %r15, 0" + - + input: + bytes: [ 0xa5, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nihh %r0, 0" + - + input: + bytes: [ 0xa5, 0x04, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nihh %r0, 32768" + - + input: + bytes: [ 0xa5, 0x04, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nihh %r0, 65535" + - + input: + bytes: [ 0xa5, 0xf4, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nihh %r15, 0" + - + input: + bytes: [ 0xa5, 0x05, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nihl %r0, 0" + - + input: + bytes: [ 0xa5, 0x05, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nihl %r0, 32768" + - + input: + bytes: [ 0xa5, 0x05, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nihl %r0, 65535" + - + input: + bytes: [ 0xa5, 0xf5, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nihl %r15, 0" + - + input: + bytes: [ 0xc0, 0x0b, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nilf %r0, 0" + - + input: + bytes: [ 0xc0, 0x0b, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nilf %r0, 4294967295" + - + input: + bytes: [ 0xc0, 0xfb, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nilf %r15, 0" + - + input: + bytes: [ 0xa5, 0x06, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nilh %r0, 0" + - + input: + bytes: [ 0xa5, 0x06, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nilh %r0, 32768" + - + input: + bytes: [ 0xa5, 0x06, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nilh %r0, 65535" + - + input: + bytes: [ 0xa5, 0xf6, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nilh %r15, 0" + - + input: + bytes: [ 0xa5, 0x07, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nill %r0, 0" + - + input: + bytes: [ 0xa5, 0x07, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nill %r0, 32768" + - + input: + bytes: [ 0xa5, 0x07, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nill %r0, 65535" + - + input: + bytes: [ 0xa5, 0xf7, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nill %r15, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "niy -524288, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "niy -1, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "niy 0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "niy 1, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "niy 524287, 0" + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "niy 0, 255" + - + input: + bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "niy 0(%r1), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "niy 0(%r15), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "niy 524287(%r1), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "niy 524287(%r15), 42" + - + input: + bytes: [ 0x14, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nr %r0, %r0" + - + input: + bytes: [ 0x14, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nr %r0, %r15" + - + input: + bytes: [ 0x14, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nr %r15, %r0" + - + input: + bytes: [ 0x14, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "nr %r7, %r8" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ny %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ny %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ny %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ny %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ny %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ny %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ny %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ny %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ny %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ny %r15, 0" + - + input: + bytes: [ 0x56, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "o %r0, 0" + - + input: + bytes: [ 0x56, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "o %r0, 4095" + - + input: + bytes: [ 0x56, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "o %r0, 0(%r1)" + - + input: + bytes: [ 0x56, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "o %r0, 0(%r15)" + - + input: + bytes: [ 0x56, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "o %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x56, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "o %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x56, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "o %r15, 0" + - + input: + bytes: [ 0xd6, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oc 0(1), 0" + - + input: + bytes: [ 0xd6, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oc 0(1), 0(%r1)" + - + input: + bytes: [ 0xd6, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oc 0(1), 0(%r15)" + - + input: + bytes: [ 0xd6, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oc 0(1), 4095" + - + input: + bytes: [ 0xd6, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oc 0(1), 4095(%r1)" + - + input: + bytes: [ 0xd6, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oc 0(1), 4095(%r15)" + - + input: + bytes: [ 0xd6, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oc 0(1, %r1), 0" + - + input: + bytes: [ 0xd6, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oc 0(1, %r15), 0" + - + input: + bytes: [ 0xd6, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oc 4095(1, %r1), 0" + - + input: + bytes: [ 0xd6, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oc 4095(1, %r15), 0" + - + input: + bytes: [ 0xd6, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oc 0(256, %r1), 0" + - + input: + bytes: [ 0xd6, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oc 0(256, %r15), 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x81 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "og %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x81 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "og %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x81 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "og %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x81 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "og %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x81 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "og %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x81 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "og %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x81 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "og %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x81 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "og %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x81 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "og %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x81 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "og %r15, 0" + - + input: + bytes: [ 0xb9, 0x81, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ogr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x81, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ogr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x81, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ogr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x81, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ogr %r7, %r8" + - + input: + bytes: [ 0x96, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oi 0, 0" + - + input: + bytes: [ 0x96, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oi 4095, 0" + - + input: + bytes: [ 0x96, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oi 0, 255" + - + input: + bytes: [ 0x96, 0x2a, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oi 0(%r1), 42" + - + input: + bytes: [ 0x96, 0x2a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oi 0(%r15), 42" + - + input: + bytes: [ 0x96, 0x2a, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oi 4095(%r1), 42" + - + input: + bytes: [ 0x96, 0x2a, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oi 4095(%r15), 42" + - + input: + bytes: [ 0xc0, 0x0c, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oihf %r0, 0" + - + input: + bytes: [ 0xc0, 0x0c, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oihf %r0, 4294967295" + - + input: + bytes: [ 0xc0, 0xfc, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oihf %r15, 0" + - + input: + bytes: [ 0xa5, 0x08, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oihh %r0, 0" + - + input: + bytes: [ 0xa5, 0x08, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oihh %r0, 32768" + - + input: + bytes: [ 0xa5, 0x08, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oihh %r0, 65535" + - + input: + bytes: [ 0xa5, 0xf8, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oihh %r15, 0" + - + input: + bytes: [ 0xa5, 0x09, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oihl %r0, 0" + - + input: + bytes: [ 0xa5, 0x09, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oihl %r0, 32768" + - + input: + bytes: [ 0xa5, 0x09, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oihl %r0, 65535" + - + input: + bytes: [ 0xa5, 0xf9, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oihl %r15, 0" + - + input: + bytes: [ 0xc0, 0x0d, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oilf %r0, 0" + - + input: + bytes: [ 0xc0, 0x0d, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oilf %r0, 4294967295" + - + input: + bytes: [ 0xc0, 0xfd, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oilf %r15, 0" + - + input: + bytes: [ 0xa5, 0x0a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oilh %r0, 0" + - + input: + bytes: [ 0xa5, 0x0a, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oilh %r0, 32768" + - + input: + bytes: [ 0xa5, 0x0a, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oilh %r0, 65535" + - + input: + bytes: [ 0xa5, 0xfa, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oilh %r15, 0" + - + input: + bytes: [ 0xa5, 0x0b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oill %r0, 0" + - + input: + bytes: [ 0xa5, 0x0b, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oill %r0, 32768" + - + input: + bytes: [ 0xa5, 0x0b, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oill %r0, 65535" + - + input: + bytes: [ 0xa5, 0xfb, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oill %r15, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oiy -524288, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oiy -1, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oiy 0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oiy 1, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oiy 524287, 0" + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oiy 0, 255" + - + input: + bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oiy 0(%r1), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oiy 0(%r15), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oiy 524287(%r1), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oiy 524287(%r15), 42" + - + input: + bytes: [ 0x16, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "or %r0, %r0" + - + input: + bytes: [ 0x16, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "or %r0, %r15" + - + input: + bytes: [ 0x16, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "or %r15, %r0" + - + input: + bytes: [ 0x16, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "or %r7, %r8" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oy %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oy %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oy %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oy %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oy %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oy %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oy %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oy %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oy %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "oy %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x36 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "pfd 0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x36 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "pfd 0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x36 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "pfd 0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x36 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "pfd 0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x36 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "pfd 0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x36 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "pfd 0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x36 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "pfd 0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x36 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "pfd 0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x36 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "pfd 0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x36 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "pfd 15, 0" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risbg %r0, %r0, 0, 0, 0" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risbg %r0, %r0, 0, 0, 63" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risbg %r0, %r0, 0, 255, 0" + - + input: + bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risbg %r0, %r0, 255, 0, 0" + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risbg %r0, %r15, 0, 0, 0" + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risbg %r15, %r0, 0, 0, 0" + - + input: + bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x55 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "risbg %r4, %r5, 6, 7, 8" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rnsbg %r0, %r0, 0, 0, 0" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rnsbg %r0, %r0, 0, 0, 63" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rnsbg %r0, %r0, 0, 255, 0" + - + input: + bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rnsbg %r0, %r0, 255, 0, 0" + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rnsbg %r0, %r15, 0, 0, 0" + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rnsbg %r15, %r0, 0, 0, 0" + - + input: + bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x54 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rnsbg %r4, %r5, 6, 7, 8" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rosbg %r0, %r0, 0, 0, 0" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rosbg %r0, %r0, 0, 0, 63" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rosbg %r0, %r0, 0, 255, 0" + - + input: + bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rosbg %r0, %r0, 255, 0, 0" + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rosbg %r0, %r15, 0, 0, 0" + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rosbg %r15, %r0, 0, 0, 0" + - + input: + bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x56 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rosbg %r4, %r5, 6, 7, 8" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rxsbg %r0, %r0, 0, 0, 0" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rxsbg %r0, %r0, 0, 0, 63" + - + input: + bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rxsbg %r0, %r0, 0, 255, 0" + - + input: + bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rxsbg %r0, %r0, 255, 0, 0" + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rxsbg %r0, %r15, 0, 0, 0" + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rxsbg %r15, %r0, 0, 0, 0" + - + input: + bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rxsbg %r4, %r5, 6, 7, 8" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rll %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rll %r15, %r1, 0" + - + input: + bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rll %r1, %r15, 0" + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rll %r15, %r15, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rll %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rll %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rll %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rll %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rll %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rll %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rll %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x1d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rll %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rllg %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rllg %r15, %r1, 0" + - + input: + bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rllg %r1, %r15, 0" + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rllg %r15, %r15, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rllg %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rllg %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rllg %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rllg %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rllg %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rllg %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rllg %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x1c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "rllg %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0x5b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "s %r0, 0" + - + input: + bytes: [ 0x5b, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "s %r0, 4095" + - + input: + bytes: [ 0x5b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "s %r0, 0(%r1)" + - + input: + bytes: [ 0x5b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "s %r0, 0(%r15)" + - + input: + bytes: [ 0x5b, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "s %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x5b, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "s %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x5b, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "s %r15, 0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sdb %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sdb %f0, 4095" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sdb %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sdb %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sdb %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sdb %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sdb %f15, 0" + - + input: + bytes: [ 0xb3, 0x1b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sdbr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x1b, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sdbr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x1b, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sdbr %f7, %f8" + - + input: + bytes: [ 0xb3, 0x1b, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sdbr %f15, %f0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "seb %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "seb %f0, 4095" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "seb %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "seb %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "seb %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "seb %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "seb %f15, 0" + - + input: + bytes: [ 0xb3, 0x0b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sebr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x0b, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sebr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x0b, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sebr %f7, %f8" + - + input: + bytes: [ 0xb3, 0x0b, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sebr %f15, %f0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sg %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sg %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sg %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sg %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sg %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sg %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sg %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sg %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sg %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sg %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x19 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgf %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x19 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgf %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x19 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgf %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x19 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgf %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x19 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgf %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x19 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgf %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x19 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgf %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x19 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgf %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x19 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgf %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x19 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgf %r15, 0" + - + input: + bytes: [ 0xb9, 0x19, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgfr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x19, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgfr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x19, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgfr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x19, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgfr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x09, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x09, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x09, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x09, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sgr %r7, %r8" + - + input: + bytes: [ 0x4b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sh %r0, 0" + - + input: + bytes: [ 0x4b, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sh %r0, 4095" + - + input: + bytes: [ 0x4b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sh %r0, 0(%r1)" + - + input: + bytes: [ 0x4b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sh %r0, 0(%r15)" + - + input: + bytes: [ 0x4b, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sh %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x4b, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sh %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x4b, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sh %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x7b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "shy %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x7b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "shy %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x7b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "shy %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x7b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "shy %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x7b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "shy %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x7b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "shy %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x7b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "shy %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x7b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "shy %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x7b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "shy %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x7b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "shy %r15, 0" + - + input: + bytes: [ 0x5f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sl %r0, 0" + - + input: + bytes: [ 0x5f, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sl %r0, 4095" + - + input: + bytes: [ 0x5f, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sl %r0, 0(%r1)" + - + input: + bytes: [ 0x5f, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sl %r0, 0(%r15)" + - + input: + bytes: [ 0x5f, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sl %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x5f, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sl %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x5f, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sl %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x99 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slb %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x99 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slb %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x99 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slb %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x99 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slb %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x99 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slb %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x99 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slb %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x99 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slb %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x99 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slb %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x99 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slb %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x99 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slb %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x89 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slbg %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x89 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slbg %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x89 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slbg %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x89 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slbg %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x89 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slbg %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x89 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slbg %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x89 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slbg %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x89 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slbg %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x89 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slbg %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x89 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slbg %r15, 0" + - + input: + bytes: [ 0xb9, 0x89, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slbgr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x89, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slbgr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x89, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slbgr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x89, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slbgr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x99, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slbr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x99, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slbr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x99, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slbr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x99, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slbr %r7, %r8" + - + input: + bytes: [ 0xc2, 0x05, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slfi %r0, 0" + - + input: + bytes: [ 0xc2, 0x05, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slfi %r0, 4294967295" + - + input: + bytes: [ 0xc2, 0xf5, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slfi %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slg %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slg %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slg %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slg %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slg %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slg %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slg %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slg %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slg %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slg %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgf %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgf %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgf %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgf %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgf %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgf %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgf %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgf %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgf %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x1b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgf %r15, 0" + - + input: + bytes: [ 0xc2, 0x04, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgfi %r0, 0" + - + input: + bytes: [ 0xc2, 0x04, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgfi %r0, 4294967295" + - + input: + bytes: [ 0xc2, 0xf4, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgfi %r15, 0" + - + input: + bytes: [ 0xb9, 0x1b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgfr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x1b, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgfr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x1b, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgfr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x1b, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgfr %r7, %r8" + - + input: + bytes: [ 0xb9, 0x0b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x0b, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x0b, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x0b, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slgr %r7, %r8" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sll %r0, 0" + - + input: + bytes: [ 0x89, 0x70, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sll %r7, 0" + - + input: + bytes: [ 0x89, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sll %r15, 0" + - + input: + bytes: [ 0x89, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sll %r0, 4095" + - + input: + bytes: [ 0x89, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sll %r0, 0(%r1)" + - + input: + bytes: [ 0x89, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sll %r0, 0(%r15)" + - + input: + bytes: [ 0x89, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sll %r0, 4095(%r1)" + - + input: + bytes: [ 0x89, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sll %r0, 4095(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllg %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllg %r15, %r1, 0" + - + input: + bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllg %r1, %r15, 0" + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllg %r15, %r15, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllg %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllg %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllg %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllg %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllg %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllg %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllg %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sllg %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0x1f, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slr %r0, %r0" + - + input: + bytes: [ 0x1f, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slr %r0, %r15" + - + input: + bytes: [ 0x1f, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slr %r15, %r0" + - + input: + bytes: [ 0x1f, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "slr %r7, %r8" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x5f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sly %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x5f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sly %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x5f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sly %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x5f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sly %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x5f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sly %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x5f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sly %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x5f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sly %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x5f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sly %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x5f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sly %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x5f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sly %r15, 0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x15 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqdb %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x15 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqdb %f0, 4095" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x15 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqdb %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x15 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqdb %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x15 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqdb %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x15 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqdb %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x15 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqdb %f15, 0" + - + input: + bytes: [ 0xb3, 0x15, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqdbr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x15, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqdbr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x15, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqdbr %f7, %f8" + - + input: + bytes: [ 0xb3, 0x15, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqdbr %f15, %f0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqeb %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqeb %f0, 4095" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqeb %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqeb %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqeb %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqeb %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqeb %f15, 0" + - + input: + bytes: [ 0xb3, 0x14, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqebr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x14, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqebr %f0, %f15" + - + input: + bytes: [ 0xb3, 0x14, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqebr %f7, %f8" + - + input: + bytes: [ 0xb3, 0x14, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqebr %f15, %f0" + - + input: + bytes: [ 0xb3, 0x16, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqxbr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x16, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqxbr %f0, %f13" + - + input: + bytes: [ 0xb3, 0x16, 0x00, 0x88 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqxbr %f8, %f8" + - + input: + bytes: [ 0xb3, 0x16, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sqxbr %f13, %f0" + - + input: + bytes: [ 0x1b, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sr %r0, %r0" + - + input: + bytes: [ 0x1b, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sr %r0, %r15" + - + input: + bytes: [ 0x1b, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sr %r15, %r0" + - + input: + bytes: [ 0x1b, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sr %r7, %r8" + - + input: + bytes: [ 0x8a, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sra %r0, 0" + - + input: + bytes: [ 0x8a, 0x70, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sra %r7, 0" + - + input: + bytes: [ 0x8a, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sra %r15, 0" + - + input: + bytes: [ 0x8a, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sra %r0, 4095" + - + input: + bytes: [ 0x8a, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sra %r0, 0(%r1)" + - + input: + bytes: [ 0x8a, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sra %r0, 0(%r15)" + - + input: + bytes: [ 0x8a, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sra %r0, 4095(%r1)" + - + input: + bytes: [ 0x8a, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sra %r0, 4095(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srag %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srag %r15, %r1, 0" + - + input: + bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srag %r1, %r15, 0" + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srag %r15, %r15, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srag %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srag %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srag %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srag %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srag %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srag %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srag %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x0a ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srag %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0x88, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srl %r0, 0" + - + input: + bytes: [ 0x88, 0x70, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srl %r7, 0" + - + input: + bytes: [ 0x88, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srl %r15, 0" + - + input: + bytes: [ 0x88, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srl %r0, 4095" + - + input: + bytes: [ 0x88, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srl %r0, 0(%r1)" + - + input: + bytes: [ 0x88, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srl %r0, 0(%r15)" + - + input: + bytes: [ 0x88, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srl %r0, 4095(%r1)" + - + input: + bytes: [ 0x88, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srl %r0, 4095(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlg %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlg %r15, %r1, 0" + - + input: + bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlg %r1, %r15, 0" + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlg %r15, %r15, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlg %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlg %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlg %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlg %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlg %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlg %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlg %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x0c ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srlg %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0xb2, 0x5e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srst %r0, %r0" + - + input: + bytes: [ 0xb2, 0x5e, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srst %r0, %r15" + - + input: + bytes: [ 0xb2, 0x5e, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srst %r15, %r0" + - + input: + bytes: [ 0xb2, 0x5e, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "srst %r7, %r8" + - + input: + bytes: [ 0x50, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "st %r0, 0" + - + input: + bytes: [ 0x50, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "st %r0, 4095" + - + input: + bytes: [ 0x50, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "st %r0, 0(%r1)" + - + input: + bytes: [ 0x50, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "st %r0, 0(%r15)" + - + input: + bytes: [ 0x50, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "st %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x50, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "st %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x50, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "st %r15, 0" + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stc %r0, 0" + - + input: + bytes: [ 0x42, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stc %r0, 4095" + - + input: + bytes: [ 0x42, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stc %r0, 0(%r1)" + - + input: + bytes: [ 0x42, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stc %r0, 0(%r15)" + - + input: + bytes: [ 0x42, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stc %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x42, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stc %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x42, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stc %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x72 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stcy %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x72 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stcy %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x72 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stcy %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x72 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stcy %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x72 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stcy %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x72 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stcy %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x72 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stcy %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x72 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stcy %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x72 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stcy %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x72 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stcy %r15, 0" + - + input: + bytes: [ 0x60, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "std %f0, 0" + - + input: + bytes: [ 0x60, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "std %f0, 4095" + - + input: + bytes: [ 0x60, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "std %f0, 0(%r1)" + - + input: + bytes: [ 0x60, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "std %f0, 0(%r15)" + - + input: + bytes: [ 0x60, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "std %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x60, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "std %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x60, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "std %f15, 0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x80, 0x67 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stdy %f0, -524288" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0xff, 0x67 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stdy %f0, -1" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x67 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stdy %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x01, 0x00, 0x67 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stdy %f0, 1" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x7f, 0x67 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stdy %f0, 524287" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x67 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stdy %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x67 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stdy %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x7f, 0x67 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stdy %f0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x7f, 0x67 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stdy %f0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x67 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stdy %f15, 0" + - + input: + bytes: [ 0x70, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ste %f0, 0" + - + input: + bytes: [ 0x70, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ste %f0, 4095" + - + input: + bytes: [ 0x70, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ste %f0, 0(%r1)" + - + input: + bytes: [ 0x70, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ste %f0, 0(%r15)" + - + input: + bytes: [ 0x70, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ste %f0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x70, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ste %f0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x70, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ste %f15, 0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x80, 0x66 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stey %f0, -524288" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0xff, 0x66 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stey %f0, -1" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x66 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stey %f0, 0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x01, 0x00, 0x66 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stey %f0, 1" + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x7f, 0x66 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stey %f0, 524287" + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x66 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stey %f0, 0(%r1)" + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x66 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stey %f0, 0(%r15)" + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x7f, 0x66 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stey %f0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x7f, 0x66 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stey %f0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x66 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stey %f15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stg %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stg %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stg %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stg %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stg %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stg %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stg %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stg %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stg %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stg %r15, 0" + - + input: + bytes: [ 0x40, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sth %r0, 0" + - + input: + bytes: [ 0x40, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sth %r0, 4095" + - + input: + bytes: [ 0x40, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sth %r0, 0(%r1)" + - + input: + bytes: [ 0x40, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sth %r0, 0(%r15)" + - + input: + bytes: [ 0x40, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sth %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x40, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sth %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x40, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sth %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x70 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthy %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x70 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthy %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x70 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthy %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x70 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthy %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x70 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthy %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x70 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthy %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x70 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthy %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x70 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthy %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x70 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthy %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x70 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sthy %r15, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stmg %r0, %r15, 0" + - + input: + bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stmg %r14, %r15, 0" + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stmg %r15, %r15, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, -524288" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, -1" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, 1" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, 524287" + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, 0(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, 0(%r15)" + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, 524287(%r1)" + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x24 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, 524287(%r15)" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x3e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strv %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x3e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strv %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x3e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strv %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x3e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strv %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x3e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strv %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x3e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strv %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x3e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strv %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x3e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strv %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x3e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strv %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x3e ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strv %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x2f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strvg %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x2f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strvg %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x2f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strvg %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x2f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strvg %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x2f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strvg %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x2f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strvg %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x2f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strvg %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x2f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strvg %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x2f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strvg %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x2f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "strvg %r15, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x50 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sty %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x50 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sty %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x50 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sty %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x50 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sty %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x50 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sty %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x50 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sty %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x50 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sty %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x50 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sty %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x50 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sty %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x50 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sty %r15, 0" + - + input: + bytes: [ 0xb3, 0x4b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sxbr %f0, %f0" + - + input: + bytes: [ 0xb3, 0x4b, 0x00, 0x0d ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sxbr %f0, %f13" + - + input: + bytes: [ 0xb3, 0x4b, 0x00, 0x88 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sxbr %f8, %f8" + - + input: + bytes: [ 0xb3, 0x4b, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sxbr %f13, %f0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x5b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sy %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x5b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sy %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x5b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sy %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x5b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sy %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x5b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sy %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x5b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sy %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x5b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sy %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x5b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sy %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x5b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sy %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x5b ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "sy %r15, 0" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tm 0, 0" + - + input: + bytes: [ 0x91, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tm 4095, 0" + - + input: + bytes: [ 0x91, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tm 0, 255" + - + input: + bytes: [ 0x91, 0x2a, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tm 0(%r1), 42" + - + input: + bytes: [ 0x91, 0x2a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tm 0(%r15), 42" + - + input: + bytes: [ 0x91, 0x2a, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tm 4095(%r1), 42" + - + input: + bytes: [ 0x91, 0x2a, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tm 4095(%r15), 42" + - + input: + bytes: [ 0xa7, 0x02, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmhh %r0, 0" + - + input: + bytes: [ 0xa7, 0x02, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmhh %r0, 32768" + - + input: + bytes: [ 0xa7, 0x02, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmhh %r0, 65535" + - + input: + bytes: [ 0xa7, 0xf2, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmhh %r15, 0" + - + input: + bytes: [ 0xa7, 0x03, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmhl %r0, 0" + - + input: + bytes: [ 0xa7, 0x03, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmhl %r0, 32768" + - + input: + bytes: [ 0xa7, 0x03, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmhl %r0, 65535" + - + input: + bytes: [ 0xa7, 0xf3, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmhl %r15, 0" + - + input: + bytes: [ 0xa7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmlh %r0, 0" + - + input: + bytes: [ 0xa7, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmlh %r0, 32768" + - + input: + bytes: [ 0xa7, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmlh %r0, 65535" + - + input: + bytes: [ 0xa7, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmlh %r15, 0" + - + input: + bytes: [ 0xa7, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmll %r0, 0" + - + input: + bytes: [ 0xa7, 0x01, 0x80, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmll %r0, 32768" + - + input: + bytes: [ 0xa7, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmll %r0, 65535" + - + input: + bytes: [ 0xa7, 0xf1, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmll %r15, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmy -524288, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmy -1, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmy 0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmy 1, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmy 524287, 0" + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmy 0, 255" + - + input: + bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmy 0(%r1), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmy 0(%r15), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmy 524287(%r1), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x51 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "tmy 524287(%r15), 42" + - + input: + bytes: [ 0x57, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "x %r0, 0" + - + input: + bytes: [ 0x57, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "x %r0, 4095" + - + input: + bytes: [ 0x57, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "x %r0, 0(%r1)" + - + input: + bytes: [ 0x57, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "x %r0, 0(%r15)" + - + input: + bytes: [ 0x57, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "x %r0, 4095(%r1, %r15)" + - + input: + bytes: [ 0x57, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "x %r0, 4095(%r15, %r1)" + - + input: + bytes: [ 0x57, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "x %r15, 0" + - + input: + bytes: [ 0xd7, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xc 0(1), 0" + - + input: + bytes: [ 0xd7, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xc 0(1), 0(%r1)" + - + input: + bytes: [ 0xd7, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xc 0(1), 0(%r15)" + - + input: + bytes: [ 0xd7, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xc 0(1), 4095" + - + input: + bytes: [ 0xd7, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xc 0(1), 4095(%r1)" + - + input: + bytes: [ 0xd7, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xc 0(1), 4095(%r15)" + - + input: + bytes: [ 0xd7, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xc 0(1, %r1), 0" + - + input: + bytes: [ 0xd7, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xc 0(1, %r15), 0" + - + input: + bytes: [ 0xd7, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xc 4095(1, %r1), 0" + - + input: + bytes: [ 0xd7, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xc 4095(1, %r15), 0" + - + input: + bytes: [ 0xd7, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xc 0(256, %r1), 0" + - + input: + bytes: [ 0xd7, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xc 0(256, %r15), 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x82 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xg %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x82 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xg %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x82 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xg %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x82 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xg %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x82 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xg %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x82 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xg %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x82 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xg %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x82 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xg %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x82 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xg %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x82 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xg %r15, 0" + - + input: + bytes: [ 0xb9, 0x82, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xgr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x82, 0x00, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xgr %r0, %r15" + - + input: + bytes: [ 0xb9, 0x82, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xgr %r15, %r0" + - + input: + bytes: [ 0xb9, 0x82, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xgr %r7, %r8" + - + input: + bytes: [ 0x97, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xi 0, 0" + - + input: + bytes: [ 0x97, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xi 4095, 0" + - + input: + bytes: [ 0x97, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xi 0, 255" + - + input: + bytes: [ 0x97, 0x2a, 0x10, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xi 0(%r1), 42" + - + input: + bytes: [ 0x97, 0x2a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xi 0(%r15), 42" + - + input: + bytes: [ 0x97, 0x2a, 0x1f, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xi 4095(%r1), 42" + - + input: + bytes: [ 0x97, 0x2a, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xi 4095(%r15), 42" + - + input: + bytes: [ 0xc0, 0x06, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xihf %r0, 0" + - + input: + bytes: [ 0xc0, 0x06, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xihf %r0, 4294967295" + - + input: + bytes: [ 0xc0, 0xf6, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xihf %r15, 0" + - + input: + bytes: [ 0xc0, 0x07, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xilf %r0, 0" + - + input: + bytes: [ 0xc0, 0x07, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xilf %r0, 4294967295" + - + input: + bytes: [ 0xc0, 0xf7, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xilf %r15, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xiy -524288, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xiy -1, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xiy 0, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xiy 1, 0" + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xiy 524287, 0" + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xiy 0, 255" + - + input: + bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xiy 0(%r1), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xiy 0(%r15), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xiy 524287(%r1), 42" + - + input: + bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xiy 524287(%r15), 42" + - + input: + bytes: [ 0x17, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xr %r0, %r0" + - + input: + bytes: [ 0x17, 0x0f ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xr %r0, %r15" + - + input: + bytes: [ 0x17, 0xf0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xr %r15, %r0" + - + input: + bytes: [ 0x17, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xr %r7, %r8" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xy %r0, -524288" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xy %r0, -1" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xy %r0, 0" + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xy %r0, 1" + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xy %r0, 524287" + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xy %r0, 0(%r1)" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xy %r0, 0(%r15)" + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xy %r0, 524287(%r1, %r15)" + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xy %r0, 524287(%r15, %r1)" + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "xy %r15, 0" diff --git a/tests/MC/SystemZ/regs-good.s.yaml b/tests/MC/SystemZ/regs-good.s.yaml new file mode 100644 index 0000000000..cec0be83f2 --- /dev/null +++ b/tests/MC/SystemZ/regs-good.s.yaml @@ -0,0 +1,397 @@ +test_cases: + - + input: + bytes: [ 0x18, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lr %r0, %r1" + - + input: + bytes: [ 0x18, 0x23 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lr %r2, %r3" + - + input: + bytes: [ 0x18, 0x45 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lr %r4, %r5" + - + input: + bytes: [ 0x18, 0x67 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lr %r6, %r7" + - + input: + bytes: [ 0x18, 0x89 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lr %r8, %r9" + - + input: + bytes: [ 0x18, 0xab ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lr %r10, %r11" + - + input: + bytes: [ 0x18, 0xcd ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lr %r12, %r13" + - + input: + bytes: [ 0x18, 0xef ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lr %r14, %r15" + - + input: + bytes: [ 0xb9, 0x04, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgr %r0, %r1" + - + input: + bytes: [ 0xb9, 0x04, 0x00, 0x23 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgr %r2, %r3" + - + input: + bytes: [ 0xb9, 0x04, 0x00, 0x45 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgr %r4, %r5" + - + input: + bytes: [ 0xb9, 0x04, 0x00, 0x67 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgr %r6, %r7" + - + input: + bytes: [ 0xb9, 0x04, 0x00, 0x89 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgr %r8, %r9" + - + input: + bytes: [ 0xb9, 0x04, 0x00, 0xab ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgr %r10, %r11" + - + input: + bytes: [ 0xb9, 0x04, 0x00, 0xcd ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgr %r12, %r13" + - + input: + bytes: [ 0xb9, 0x04, 0x00, 0xef ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lgr %r14, %r15" + - + input: + bytes: [ 0xb9, 0x97, 0x00, 0x00 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlr %r0, %r0" + - + input: + bytes: [ 0xb9, 0x97, 0x00, 0x20 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlr %r2, %r0" + - + input: + bytes: [ 0xb9, 0x97, 0x00, 0x40 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlr %r4, %r0" + - + input: + bytes: [ 0xb9, 0x97, 0x00, 0x60 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlr %r6, %r0" + - + input: + bytes: [ 0xb9, 0x97, 0x00, 0x80 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlr %r8, %r0" + - + input: + bytes: [ 0xb9, 0x97, 0x00, 0xa0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlr %r10, %r0" + - + input: + bytes: [ 0xb9, 0x97, 0x00, 0xc0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlr %r12, %r0" + - + input: + bytes: [ 0xb9, 0x97, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "dlr %r14, %r0" + - + input: + bytes: [ 0x38, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ler %f0, %f1" + - + input: + bytes: [ 0x38, 0x23 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ler %f2, %f3" + - + input: + bytes: [ 0x38, 0x45 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ler %f4, %f5" + - + input: + bytes: [ 0x38, 0x67 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ler %f6, %f7" + - + input: + bytes: [ 0x38, 0x89 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ler %f8, %f9" + - + input: + bytes: [ 0x38, 0xab ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ler %f10, %f11" + - + input: + bytes: [ 0x38, 0xcd ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ler %f12, %f13" + - + input: + bytes: [ 0x38, 0xef ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ler %f14, %f15" + - + input: + bytes: [ 0x28, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldr %f0, %f1" + - + input: + bytes: [ 0x28, 0x23 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldr %f2, %f3" + - + input: + bytes: [ 0x28, 0x45 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldr %f4, %f5" + - + input: + bytes: [ 0x28, 0x67 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldr %f6, %f7" + - + input: + bytes: [ 0x28, 0x89 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldr %f8, %f9" + - + input: + bytes: [ 0x28, 0xab ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldr %f10, %f11" + - + input: + bytes: [ 0x28, 0xcd ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldr %f12, %f13" + - + input: + bytes: [ 0x28, 0xef ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "ldr %f14, %f15" + - + input: + bytes: [ 0xb3, 0x65, 0x00, 0x01 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lxr %f0, %f1" + - + input: + bytes: [ 0xb3, 0x65, 0x00, 0x45 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lxr %f4, %f5" + - + input: + bytes: [ 0xb3, 0x65, 0x00, 0x89 ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lxr %f8, %f9" + - + input: + bytes: [ 0xb3, 0x65, 0x00, 0xcd ] + arch: "CS_ARCH_SYSZ" + options: [ ] + expected: + insns: + - + asm_text: "lxr %f12, %f13" diff --git a/tests/MC/TriCore/ADC_Background_Scan_1_KIT_TC275_LK.s.yaml b/tests/MC/TriCore/ADC_Background_Scan_1_KIT_TC275_LK.s.yaml new file mode 100644 index 0000000000..fba549d2a8 --- /dev/null +++ b/tests/MC/TriCore/ADC_Background_Scan_1_KIT_TC275_LK.s.yaml @@ -0,0 +1,7588 @@ +test_cases: + - + input: + bytes: [ 0x6d, 0x00, 0x43, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x886" + - + input: + bytes: [ 0xc6, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d0, d1" + - + input: + bytes: [ 0x0f, 0xf3, 0x00, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d3, d3, d15" + - + input: + bytes: [ 0x10, 0xaf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, sp, d15, #0" + - + input: + bytes: [ 0x8f, 0x33, 0x40, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d3, #0x3" + - + input: + bytes: [ 0xf6, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d0, #0xc" + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d1, d15, #0x3f" + - + input: + bytes: [ 0xfc, 0x2e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a2, #-0x4" + - + input: + bytes: [ 0x4b, 0x00, 0x41, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "itof d15, d0" + - + input: + bytes: [ 0x10, 0xd4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a4, a13, d15, #0" + - + input: + bytes: [ 0x8b, 0x08, 0x01, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d1, d8, #0x10" + - + input: + bytes: [ 0x40, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a4, a15" + - + input: + bytes: [ 0x82, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #0" + - + input: + bytes: [ 0x3c, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x22" + - + input: + bytes: [ 0x53, 0xc3, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d3, #0xc" + - + input: + bytes: [ 0x6d, 0x00, 0x91, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x522" + - + input: + bytes: [ 0x7d, 0x4f, 0x0d, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne.a a15, a4, #0x1a" + - + input: + bytes: [ 0xee, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0xc" + - + input: + bytes: [ 0xb7, 0x0f, 0x01, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0x2, #0x1" + - + input: + bytes: [ 0x7f, 0x0f, 0x07, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d15, d0, #0xe" + - + input: + bytes: [ 0x3c, 0x1e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x3c" + - + input: + bytes: [ 0x6d, 0x00, 0xf3, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1fe6" + - + input: + bytes: [ 0xa6, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d0, d15" + - + input: + bytes: [ 0x82, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x5" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x86 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x6200" + - + input: + bytes: [ 0x90, 0xdd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a13, a13, d15, #0x2" + - + input: + bytes: [ 0x10, 0xc2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a12, d15, #0" + - + input: + bytes: [ 0x5e, 0x13 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x6" + - + input: + bytes: [ 0x8f, 0x3c, 0x00, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d4, d12, #0x3" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x3000" + - + input: + bytes: [ 0x53, 0x89, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d0, d9, #0x8" + - + input: + bytes: [ 0x53, 0x84, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d4, #0x8" + - + input: + bytes: [ 0xd9, 0xff, 0x02, 0xc0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x302" + - + input: + bytes: [ 0x7e, 0x93 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d9, #0x6" + - + input: + bytes: [ 0x37, 0x0f, 0x81, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x1, #0x1" + - + input: + bytes: [ 0x6d, 0x00, 0xf1, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1e2" + - + input: + bytes: [ 0xc2, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d8, #-0x1" + - + input: + bytes: [ 0x37, 0x0f, 0x81, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0xf, #0x1" + - + input: + bytes: [ 0x37, 0x01, 0xe2, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d1, #0x1, #0x2" + - + input: + bytes: [ 0x8f, 0x3f, 0x00, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d3, d15, #0x3" + - + input: + bytes: [ 0x37, 0xf3, 0x08, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d3, d3, d15, #0, #0x8" + - + input: + bytes: [ 0x53, 0x88, 0x21, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d8, #0x18" + - + input: + bytes: [ 0xd9, 0x22, 0x0c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0xc" + - + input: + bytes: [ 0x5e, 0x1e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x1c" + - + input: + bytes: [ 0x53, 0x88, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d8, #0x8" + - + input: + bytes: [ 0x37, 0x0f, 0x68, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d15, #0x18, #0x8" + - + input: + bytes: [ 0x60, 0xc2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a2, d12" + - + input: + bytes: [ 0xd9, 0x22, 0x08, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x6088" + - + input: + bytes: [ 0x76, 0xcf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d12, #0x1e" + - + input: + bytes: [ 0x6d, 0xff, 0xdc, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x248" + - + input: + bytes: [ 0xc2, 0x31 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d1, #0x3" + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d2, d15, #0x3f" + - + input: + bytes: [ 0x0f, 0x10, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d0, d0, d1" + - + input: + bytes: [ 0x6d, 0xff, 0xee, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xa24" + - + input: + bytes: [ 0x9b, 0x14, 0x85, 0x43 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d4, d4, #0x3851" + - + input: + bytes: [ 0x0f, 0x05, 0x10, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d5, d5, d0" + - + input: + bytes: [ 0x6d, 0xff, 0x06, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3f4" + - + input: + bytes: [ 0x3b, 0x80, 0x00, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x8" + - + input: + bytes: [ 0x91, 0x30, 0x00, 0x3f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a3, #0xf003" + - + input: + bytes: [ 0x6d, 0xff, 0xb7, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x292" + - + input: + bytes: [ 0xc2, 0x18 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d8, #0x1" + - + input: + bytes: [ 0x82, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d11, #0" + - + input: + bytes: [ 0x6f, 0x1f, 0x12, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x1, #0x24" + - + input: + bytes: [ 0x6d, 0xff, 0xa9, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x8ae" + - + input: + bytes: [ 0x6d, 0x00, 0x6b, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x16d6" + - + input: + bytes: [ 0xb7, 0x0f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0, #0x8" + - + input: + bytes: [ 0xdf, 0x0c, 0x9b, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d12, #0, #-0xca" + - + input: + bytes: [ 0x6d, 0xff, 0x83, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xfa" + - + input: + bytes: [ 0x8f, 0x00, 0x21, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d0, d0, #0x10" + - + input: + bytes: [ 0x3f, 0x0f, 0x04, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d15, d0, #0x8" + - + input: + bytes: [ 0x6d, 0xff, 0x0d, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3e6" + - + input: + bytes: [ 0xd9, 0x22, 0x14, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x2014" + - + input: + bytes: [ 0x82, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d12, #0" + - + input: + bytes: [ 0x40, 0xc4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a4, a12" + - + input: + bytes: [ 0x37, 0x00, 0x70, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0x10, #0x10" + - + input: + bytes: [ 0x4b, 0xf0, 0x11, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.u e2, d0, d15" + - + input: + bytes: [ 0x9b, 0x10, 0x13, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d0, d0, #0x131" + - + input: + bytes: [ 0x3c, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xe" + - + input: + bytes: [ 0xbe, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x2a" + - + input: + bytes: [ 0x60, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a15, d15" + - + input: + bytes: [ 0x82, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, #-0x1" + - + input: + bytes: [ 0x6e, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #-0xc" + - + input: + bytes: [ 0x01, 0x20, 0x00, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a2, d0, #0" + - + input: + bytes: [ 0x4b, 0xf1, 0x51, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d2, d1, d15" + - + input: + bytes: [ 0x3b, 0x00, 0x40, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x400" + - + input: + bytes: [ 0x06, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d4, #-0x1" + - + input: + bytes: [ 0x37, 0x0f, 0xe1, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x7, #0x1" + - + input: + bytes: [ 0x6d, 0xff, 0xf2, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x61c" + - + input: + bytes: [ 0x3c, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xa" + - + input: + bytes: [ 0x5e, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x14" + - + input: + bytes: [ 0x82, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d10, #0x1" + - + input: + bytes: [ 0x80, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d4, a15" + - + input: + bytes: [ 0x8f, 0xf8, 0x01, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d8, #0x1f" + - + input: + bytes: [ 0x16, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0x1f" + - + input: + bytes: [ 0x49, 0xf5, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a15]#0" + - + input: + bytes: [ 0x37, 0x0f, 0x64, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d15, #0x4, #0x4" + - + input: + bytes: [ 0x0f, 0x3f, 0x00, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d15, d3" + - + input: + bytes: [ 0xb4, 0xaf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp], d15" + - + input: + bytes: [ 0x49, 0xff, 0x20, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x20" + - + input: + bytes: [ 0x37, 0xf0, 0x02, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0, #0x2" + - + input: + bytes: [ 0x6d, 0xff, 0x4e, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x164" + - + input: + bytes: [ 0x2e, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x1, #0x16" + - + input: + bytes: [ 0x3c, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xa0" + - + input: + bytes: [ 0x4b, 0x2f, 0x41, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d15, d15, d2" + - + input: + bytes: [ 0x8b, 0xf4, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d4, #0xf" + - + input: + bytes: [ 0xdf, 0x10, 0x2b, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d0, #0x1, #0x56" + - + input: + bytes: [ 0xd9, 0xff, 0xc2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0xc02" + - + input: + bytes: [ 0xdf, 0x19, 0x49, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d9, #0x1, #0x92" + - + input: + bytes: [ 0x4b, 0xf0, 0x11, 0x42 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.u e4, d0, d15" + - + input: + bytes: [ 0xbf, 0x45, 0x0b, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d5, #0x4, #0x16" + - + input: + bytes: [ 0x3c, 0x94 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0xd8" + - + input: + bytes: [ 0x40, 0x4c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a12, a4" + - + input: + bytes: [ 0x92, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d1, d15, #0x1" + - + input: + bytes: [ 0x9b, 0x11, 0x13, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d1, d1, #0x131" + - + input: + bytes: [ 0x6f, 0x1f, 0xfa, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0x1, #-0xc" + - + input: + bytes: [ 0x26, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d0" + - + input: + bytes: [ 0x49, 0xff, 0x00, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x40" + - + input: + bytes: [ 0x6d, 0xff, 0xbe, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x84" + - + input: + bytes: [ 0xe2, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d0, d1" + - + input: + bytes: [ 0x60, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a2, d15" + - + input: + bytes: [ 0x96, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x2" + - + input: + bytes: [ 0x6d, 0x00, 0xe1, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1c2" + - + input: + bytes: [ 0x3b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x400" + - + input: + bytes: [ 0x80, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d2, a15" + - + input: + bytes: [ 0xda, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x1f" + - + input: + bytes: [ 0xd9, 0xff, 0x0c, 0x46 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x610c" + - + input: + bytes: [ 0x4b, 0x0f, 0x61, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "utof d2, d15" + - + input: + bytes: [ 0xbb, 0x00, 0xc2, 0x2b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d2, #0xbc20" + - + input: + bytes: [ 0x8b, 0xf0, 0x2f, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min.u d0, d0, #0xff" + - + input: + bytes: [ 0x3c, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x20" + - + input: + bytes: [ 0x8f, 0x20, 0x00, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d1, d0, #0x2" + - + input: + bytes: [ 0x3e, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x18" + - + input: + bytes: [ 0x8f, 0x24, 0x40, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d4, #0x2" + - + input: + bytes: [ 0x8f, 0x24, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, d4, #0x2" + - + input: + bytes: [ 0x8b, 0x87, 0x01, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d7, #0x18" + - + input: + bytes: [ 0xd9, 0xff, 0x80, 0xcb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x4500" + - + input: + bytes: [ 0x49, 0xf4, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a15]#0" + - + input: + bytes: [ 0x76, 0xdb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d13, #0x16" + - + input: + bytes: [ 0x6e, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x52" + - + input: + bytes: [ 0xb7, 0x0f, 0x01, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0x6, #0x1" + - + input: + bytes: [ 0xbe, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x38" + - + input: + bytes: [ 0x6d, 0xff, 0x6a, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x12c" + - + input: + bytes: [ 0x20, 0x60 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.a sp, #0x60" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x46 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0x6000" + - + input: + bytes: [ 0xd9, 0xff, 0x2c, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x106c" + - + input: + bytes: [ 0x96, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x3" + - + input: + bytes: [ 0xc2, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d9, #0x1" + - + input: + bytes: [ 0x6d, 0xff, 0xcb, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x46a" + - + input: + bytes: [ 0x9b, 0x6f, 0x58, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d15, d15, #0x3586" + - + input: + bytes: [ 0xd9, 0x33, 0xc0, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a3, [a3]#-0x300" + - + input: + bytes: [ 0x3b, 0x90, 0x00, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x9" + - + input: + bytes: [ 0x6d, 0xff, 0x8d, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2e6" + - + input: + bytes: [ 0x91, 0x30, 0x00, 0xcf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a12, #0xf003" + - + input: + bytes: [ 0xd9, 0x22, 0x0c, 0x16 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x604c" + - + input: + bytes: [ 0x6d, 0x00, 0xf0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x9e0" + - + input: + bytes: [ 0xb7, 0x7f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x7, #0, #0x8" + - + input: + bytes: [ 0x8f, 0x3f, 0x00, 0xd1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d13, d15, #0x3" + - + input: + bytes: [ 0x7b, 0x00, 0x27, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d15, #0x4270" + - + input: + bytes: [ 0xfc, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a2, #-0xe" + - + input: + bytes: [ 0xb7, 0x2f, 0x82, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x2, #0x1, #0x2" + - + input: + bytes: [ 0x0f, 0xa0, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d0, d0, d10" + - + input: + bytes: [ 0x53, 0x41, 0x20, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d1, d1, #0x4" + - + input: + bytes: [ 0x5e, 0x32 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x3, #0x4" + - + input: + bytes: [ 0x6d, 0xff, 0x32, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xb9c" + - + input: + bytes: [ 0x3b, 0x00, 0x5a, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x25a0" + - + input: + bytes: [ 0x8f, 0xec, 0x1f, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d12, #-0x2" + - + input: + bytes: [ 0x37, 0xf0, 0x05, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0, #0x5" + - + input: + bytes: [ 0x6d, 0x00, 0x0e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1c" + - + input: + bytes: [ 0xc6, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d0, d15" + - + input: + bytes: [ 0x53, 0x48, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d8, #0x4" + - + input: + bytes: [ 0x37, 0x0f, 0x68, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d4, d15, #0, #0x8" + - + input: + bytes: [ 0xd9, 0x22, 0xc0, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#-0x2400" + - + input: + bytes: [ 0x80, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d1, a4" + - + input: + bytes: [ 0x82, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x1" + - + input: + bytes: [ 0x20, 0x38 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.a sp, #0x38" + - + input: + bytes: [ 0x91, 0x00, 0x80, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0xf800" + - + input: + bytes: [ 0x7b, 0x00, 0x00, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d1, #0x1000" + - + input: + bytes: [ 0x6d, 0x00, 0x9a, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1134" + - + input: + bytes: [ 0xd9, 0x3f, 0x00, 0x46 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a3]#0x6100" + - + input: + bytes: [ 0x37, 0x0f, 0x81, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x5, #0x1" + - + input: + bytes: [ 0x6d, 0x00, 0x0a, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1414" + - + input: + bytes: [ 0x4b, 0x0f, 0x71, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftouz d0, d15" + - + input: + bytes: [ 0x5e, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x2, #0x6" + - + input: + bytes: [ 0x91, 0x20, 0x00, 0x27 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0x7002" + - + input: + bytes: [ 0x6d, 0xff, 0x1e, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x5c4" + - + input: + bytes: [ 0x4b, 0x0f, 0x41, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d15, d15, d0" + - + input: + bytes: [ 0x10, 0xdf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, a13, d15, #0" + - + input: + bytes: [ 0x6d, 0xff, 0x89, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xaee" + - + input: + bytes: [ 0x82, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, #0" + - + input: + bytes: [ 0xa2, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d0, d1" + - + input: + bytes: [ 0x37, 0x00, 0x68, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d4, d0, #0, #0x8" + - + input: + bytes: [ 0x4b, 0xf2, 0x41, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d1, d2, d15" + - + input: + bytes: [ 0xd9, 0x22, 0x00, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x6080" + - + input: + bytes: [ 0x37, 0x03, 0x68, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d3, #0x8, #0x8" + - + input: + bytes: [ 0xb7, 0x4f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x4, #0, #0x8" + - + input: + bytes: [ 0xd9, 0x99, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a9, [a9]#0" + - + input: + bytes: [ 0xd9, 0x44, 0x0c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0xc" + - + input: + bytes: [ 0xee, 0x13 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x26" + - + input: + bytes: [ 0x9a, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d4, #0x1" + - + input: + bytes: [ 0xd9, 0xff, 0xa8, 0x92 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x2a68" + - + input: + bytes: [ 0x6d, 0xff, 0xa6, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2b4" + - + input: + bytes: [ 0x89, 0x40, 0xc1, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachei.wi [a4+]#0x1" + - + input: + bytes: [ 0xbf, 0x48, 0xb1, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d8, #0x4, #-0x9e" + - + input: + bytes: [ 0xac, 0xa1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x2, d15" + - + input: + bytes: [ 0xbb, 0x00, 0xc2, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d0, #0xbc20" + - + input: + bytes: [ 0x4b, 0x0f, 0x41, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "itof d15, d15" + - + input: + bytes: [ 0xdc, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ji a15" + - + input: + bytes: [ 0x9b, 0x8f, 0xb9, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d15, d15, #0x4b98" + - + input: + bytes: [ 0xee, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0xc" + - + input: + bytes: [ 0x06, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d0, #0x5" + - + input: + bytes: [ 0x4b, 0x10, 0x01, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div e2, d0, d1" + - + input: + bytes: [ 0x37, 0x0f, 0x02, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x8, #0x2" + - + input: + bytes: [ 0xd9, 0x22, 0xc0, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#-0x4400" + - + input: + bytes: [ 0x6f, 0x0f, 0xfe, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0, #-0x4" + - + input: + bytes: [ 0x15, 0xd0, 0xc0, 0xeb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ldlcx #0xd0003f80" + - + input: + bytes: [ 0x3c, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x2" + - + input: + bytes: [ 0x6d, 0xff, 0xaf, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xa2" + - + input: + bytes: [ 0x4b, 0x0f, 0x61, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "utof d15, d15" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a5, #0x6000" + - + input: + bytes: [ 0x53, 0xc2, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d2, #0xc" + - + input: + bytes: [ 0x91, 0x20, 0x00, 0xa7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a sp, #0x7002" + - + input: + bytes: [ 0x3c, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x14" + - + input: + bytes: [ 0xda, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x10" + - + input: + bytes: [ 0xd9, 0xaa, 0x40, 0x89 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea sp, [sp]#-0x6a00" + - + input: + bytes: [ 0x6d, 0xff, 0x02, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3fc" + - + input: + bytes: [ 0xb7, 0x0f, 0x02, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0x4, #0x2" + - + input: + bytes: [ 0x7b, 0x00, 0x1f, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d15, #0x41f0" + - + input: + bytes: [ 0xc2, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d1, #0x1" + - + input: + bytes: [ 0x3c, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x10" + - + input: + bytes: [ 0x6d, 0x00, 0xca, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x194" + - + input: + bytes: [ 0x76, 0xc5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d12, #0xa" + - + input: + bytes: [ 0x6d, 0x00, 0x27, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x24e" + - + input: + bytes: [ 0x6d, 0x00, 0xab, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x556" + - + input: + bytes: [ 0x82, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x1" + - + input: + bytes: [ 0x91, 0x50, 0x88, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0xf885" + - + input: + bytes: [ 0xbf, 0x30, 0xea, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, #0x3, #-0x2c" + - + input: + bytes: [ 0x0f, 0x04, 0x10, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d4, d4, d0" + - + input: + bytes: [ 0x37, 0x0f, 0x6e, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x2, #0xe" + - + input: + bytes: [ 0xd9, 0xcc, 0x14, 0x36 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a12, [a12]#0x60d4" + - + input: + bytes: [ 0xb7, 0x0f, 0x0c, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0x14, #0xc" + - + input: + bytes: [ 0x86, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d4, #0x2" + - + input: + bytes: [ 0x82, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, #0x1" + - + input: + bytes: [ 0x4b, 0x20, 0x01, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div e2, d0, d2" + - + input: + bytes: [ 0x02, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d15" + - + input: + bytes: [ 0x4b, 0x0f, 0x71, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftouz d4, d15" + - + input: + bytes: [ 0x26, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d15" + - + input: + bytes: [ 0x37, 0x0f, 0x01, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x2, #0x1" + - + input: + bytes: [ 0x82, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d3, #-0x1" + - + input: + bytes: [ 0x6d, 0xff, 0x7a, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x90c" + - + input: + bytes: [ 0x6d, 0xff, 0x19, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3ce" + - + input: + bytes: [ 0xa2, 0xdc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d12, d13" + - + input: + bytes: [ 0x82, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d7, #0x1" + - + input: + bytes: [ 0x5e, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x16" + - + input: + bytes: [ 0x2d, 0x02, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "calli a2" + - + input: + bytes: [ 0x89, 0xa2, 0x86, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x6, d2" + - + input: + bytes: [ 0x49, 0xf2, 0x24, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a15]#0x24" + - + input: + bytes: [ 0xd9, 0xaa, 0x40, 0x8b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea sp, [sp]#-0x4a00" + - + input: + bytes: [ 0x37, 0x0f, 0x61, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x2, #0x1" + - + input: + bytes: [ 0x8f, 0x0f, 0x1f, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d0, d15, #-0x10" + - + input: + bytes: [ 0x6e, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x6" + - + input: + bytes: [ 0x20, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.a sp, #0x20" + - + input: + bytes: [ 0x6d, 0xff, 0xda, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x24c" + - + input: + bytes: [ 0x6d, 0xff, 0x18, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x9d0" + - + input: + bytes: [ 0xda, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x3" + - + input: + bytes: [ 0x02, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, d4" + - + input: + bytes: [ 0x6e, 0x2d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x5a" + - + input: + bytes: [ 0x10, 0xd2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a13, d15, #0" + - + input: + bytes: [ 0xc2, 0xe0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, #-0x2" + - + input: + bytes: [ 0x3c, 0x34 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x68" + - + input: + bytes: [ 0x96, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x8" + - + input: + bytes: [ 0x6d, 0xff, 0xb3, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x9a" + - + input: + bytes: [ 0x3c, 0x37 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x6e" + - + input: + bytes: [ 0x91, 0x10, 0x00, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a3, #0x1" + - + input: + bytes: [ 0x6d, 0xff, 0xe0, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x40" + - + input: + bytes: [ 0x76, 0x13 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d1, #0x6" + - + input: + bytes: [ 0x80, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d0, a2" + - + input: + bytes: [ 0xfd, 0xf0, 0xed, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a15, #-0x26" + - + input: + bytes: [ 0x1d, 0xff, 0x77, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x112" + - + input: + bytes: [ 0x91, 0x30, 0x00, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0xf003" + - + input: + bytes: [ 0x7f, 0x81, 0x0a, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d1, d8, #0x14" + - + input: + bytes: [ 0xa2, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d15, d1" + - + input: + bytes: [ 0x10, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a2, d15, #0" + - + input: + bytes: [ 0x6d, 0xff, 0x45, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x976" + - + input: + bytes: [ 0x82, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #0x1" + - + input: + bytes: [ 0x53, 0x4f, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d15, #0x4" + - + input: + bytes: [ 0x9a, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d2, #-0x1" + - + input: + bytes: [ 0x40, 0x5c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a12, a5" + - + input: + bytes: [ 0x6d, 0x00, 0x72, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x16e4" + - + input: + bytes: [ 0x16, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0x3" + - + input: + bytes: [ 0x6d, 0x00, 0x47, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x48e" + - + input: + bytes: [ 0xd9, 0x22, 0x14, 0x36 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x60d4" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a8, #0" + - + input: + bytes: [ 0xb7, 0x6f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x6, #0, #0x8" + - + input: + bytes: [ 0xd9, 0x22, 0x88, 0xc2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x2b08" + - + input: + bytes: [ 0x91, 0x20, 0x00, 0x5f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a5, #0xf002" + - + input: + bytes: [ 0x6d, 0x00, 0xb3, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x566" + - + input: + bytes: [ 0x49, 0xf2, 0x1c, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a15]#0x1c" + - + input: + bytes: [ 0xd9, 0xff, 0x9c, 0x82 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x2a1c" + - + input: + bytes: [ 0x82, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d9, #0x1" + - + input: + bytes: [ 0x30, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a3, a15" + - + input: + bytes: [ 0x6d, 0x00, 0x15, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x182a" + - + input: + bytes: [ 0x37, 0xf0, 0x01, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0x4, #0x1" + - + input: + bytes: [ 0x3b, 0xf0, 0x0f, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0xff" + - + input: + bytes: [ 0xd9, 0xff, 0xb4, 0x82 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x2a34" + - + input: + bytes: [ 0x6d, 0xff, 0xc6, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x874" + - + input: + bytes: [ 0x8f, 0x3f, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d15, #0x3" + - + input: + bytes: [ 0x4b, 0xf0, 0x11, 0x82 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.u e8, d0, d15" + - + input: + bytes: [ 0x96, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x10" + - + input: + bytes: [ 0x6d, 0xff, 0x37, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x192" + - + input: + bytes: [ 0xc2, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d12, #-0x1" + - + input: + bytes: [ 0x37, 0x0f, 0x04, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x4, #0x4" + - + input: + bytes: [ 0x91, 0x30, 0x00, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0xf003" + - + input: + bytes: [ 0x6d, 0x00, 0x50, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x18a0" + - + input: + bytes: [ 0x02, 0x92 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, d9" + - + input: + bytes: [ 0xda, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0" + - + input: + bytes: [ 0x4b, 0x10, 0x11, 0x82 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.u e8, d0, d1" + - + input: + bytes: [ 0x02, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, d15" + - + input: + bytes: [ 0xa0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a4, #0" + - + input: + bytes: [ 0x53, 0x42, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d2, #0x4" + - + input: + bytes: [ 0x37, 0x0f, 0xe7, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x1, #0x7" + - + input: + bytes: [ 0xfc, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a2, #-0x2" + - + input: + bytes: [ 0x6d, 0x00, 0x5f, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x18be" + - + input: + bytes: [ 0x6d, 0xff, 0xde, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xa44" + - + input: + bytes: [ 0x1d, 0x00, 0x02, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x4" + - + input: + bytes: [ 0x6d, 0x00, 0x5a, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x4b4" + - + input: + bytes: [ 0xb7, 0x0f, 0x01, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0, #0x1" + - + input: + bytes: [ 0xb7, 0x0f, 0x14, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0, #0x14" + - + input: + bytes: [ 0x6d, 0xff, 0xd6, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x454" + - + input: + bytes: [ 0x40, 0xd4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a4, a13" + - + input: + bytes: [ 0x49, 0x40, 0x40, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ldmst [a4]#0, e0" + - + input: + bytes: [ 0x3c, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x24" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0x8000" + - + input: + bytes: [ 0x6d, 0xff, 0xb4, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x98" + - + input: + bytes: [ 0xc5, 0x02, 0x3f, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, #0x3f" + - + input: + bytes: [ 0x8f, 0x34, 0x40, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d4, #0x3" + - + input: + bytes: [ 0x6d, 0x00, 0x65, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x12ca" + - + input: + bytes: [ 0x6d, 0x00, 0x41, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1e82" + - + input: + bytes: [ 0x3b, 0x00, 0x28, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, #0x280" + - + input: + bytes: [ 0x80, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d15, a4" + - + input: + bytes: [ 0xd9, 0xff, 0x8c, 0x62 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x298c" + - + input: + bytes: [ 0xc6, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d3, d15" + - + input: + bytes: [ 0x6d, 0xff, 0xd6, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x54" + - + input: + bytes: [ 0xb4, 0xa2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp], d2" + - + input: + bytes: [ 0x15, 0xd0, 0xc0, 0xe3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "stlcx #0xd0003f80" + - + input: + bytes: [ 0xbb, 0xf0, 0xff, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d15, #0xffff" + - + input: + bytes: [ 0x6d, 0xff, 0x04, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3f8" + - + input: + bytes: [ 0xda, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x20" + - + input: + bytes: [ 0x53, 0x40, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d0, #0x4" + - + input: + bytes: [ 0xe2, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d1" + - + input: + bytes: [ 0xd9, 0xff, 0xe4, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0xfe4" + - + input: + bytes: [ 0x6d, 0x00, 0xf1, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x5e2" + - + input: + bytes: [ 0x37, 0xaf, 0x02, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d10, #0, #0x2" + - + input: + bytes: [ 0x91, 0x20, 0x00, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x6002" + - + input: + bytes: [ 0x06, 0x3f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, #0x3" + - + input: + bytes: [ 0xd9, 0xff, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x10" + - + input: + bytes: [ 0xde, 0x25 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x2, #0x2a" + - + input: + bytes: [ 0x92, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d15, #0x1" + - + input: + bytes: [ 0x7f, 0xf8, 0x0d, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d8, d15, #0x1a" + - + input: + bytes: [ 0x8f, 0x3c, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d12, #0x3" + - + input: + bytes: [ 0x3c, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x4" + - + input: + bytes: [ 0xdf, 0x1f, 0xfb, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0x1, #-0xa" + - + input: + bytes: [ 0x8f, 0x4f, 0x1f, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d1, d15, #-0xc" + - + input: + bytes: [ 0xd9, 0x44, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x30" + - + input: + bytes: [ 0x3c, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x2e" + - + input: + bytes: [ 0x37, 0xf0, 0x01, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0x1e, #0x1" + - + input: + bytes: [ 0x82, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x3" + - + input: + bytes: [ 0x6d, 0xff, 0xe8, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x30" + - + input: + bytes: [ 0x6e, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x8" + - + input: + bytes: [ 0xd9, 0xff, 0xe0, 0xe0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0xfa0" + - + input: + bytes: [ 0x3c, 0x1c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x38" + - + input: + bytes: [ 0x4b, 0x10, 0x11, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.u e0, d0, d1" + - + input: + bytes: [ 0x3c, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xc" + - + input: + bytes: [ 0xa6, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d0" + - + input: + bytes: [ 0x3e, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x8" + - + input: + bytes: [ 0xdf, 0x10, 0xee, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d0, #0x1, #-0x24" + - + input: + bytes: [ 0x76, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d1, #0xe" + - + input: + bytes: [ 0x40, 0xd5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a5, a13" + - + input: + bytes: [ 0xbf, 0x21, 0xcd, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d1, #0x2, #-0x66" + - + input: + bytes: [ 0xd9, 0xff, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x30" + - + input: + bytes: [ 0xa6, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d1, d15" + - + input: + bytes: [ 0x7b, 0x00, 0x37, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d15, #0x4370" + - + input: + bytes: [ 0xbb, 0xf0, 0xff, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d2, #0xffff" + - + input: + bytes: [ 0x77, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "dextr d0, d0, d0, #0x8" + - + input: + bytes: [ 0x3c, 0xd9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x4e" + - + input: + bytes: [ 0xd9, 0x22, 0x30, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x6030" + - + input: + bytes: [ 0x37, 0x0f, 0x02, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0, #0x2" + - + input: + bytes: [ 0x01, 0x28, 0x00, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a2, d8, #0" + - + input: + bytes: [ 0x6d, 0xff, 0x58, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x150" + - + input: + bytes: [ 0x53, 0x4a, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d10, #0x4" + - + input: + bytes: [ 0xd9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a0, [a0]#0" + - + input: + bytes: [ 0xd9, 0xff, 0x40, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x480" + - + input: + bytes: [ 0x53, 0x41, 0x20, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d3, d1, #0x4" + - + input: + bytes: [ 0xac, 0xa3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x6, d15" + - + input: + bytes: [ 0xee, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x10" + - + input: + bytes: [ 0x3c, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x52" + - + input: + bytes: [ 0xd9, 0xff, 0x0a, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x28a" + - + input: + bytes: [ 0xd9, 0xff, 0xdc, 0xd0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0xf5c" + - + input: + bytes: [ 0x26, 0x32 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d2, d3" + - + input: + bytes: [ 0x40, 0x54 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a4, a5" + - + input: + bytes: [ 0xee, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x6" + - + input: + bytes: [ 0x6d, 0x00, 0x15, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2a" + - + input: + bytes: [ 0x76, 0x27 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d2, #0xe" + - + input: + bytes: [ 0x1e, 0x32 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0x3, #0x4" + - + input: + bytes: [ 0x37, 0xf1, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d1, d15, #0, #0x8" + - + input: + bytes: [ 0x02, 0xa4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d10" + - + input: + bytes: [ 0x5f, 0x0f, 0x24, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x48" + - + input: + bytes: [ 0x37, 0x3f, 0x02, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d3, #0, #0x2" + - + input: + bytes: [ 0x6d, 0x00, 0x5b, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xcb6" + - + input: + bytes: [ 0x8b, 0x87, 0x01, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d1, d7, #0x18" + - + input: + bytes: [ 0x82, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x2" + - + input: + bytes: [ 0x49, 0xf2, 0x14, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a15]#0x14" + - + input: + bytes: [ 0x37, 0x0f, 0x68, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0, #0x8" + - + input: + bytes: [ 0xa6, 0x5f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d5" + - + input: + bytes: [ 0x91, 0x20, 0x00, 0x25 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0x5002" + - + input: + bytes: [ 0xde, 0x1e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x3c" + - + input: + bytes: [ 0x96, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x1" + - + input: + bytes: [ 0xb7, 0x7f, 0x03, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x7, #0x1c, #0x3" + - + input: + bytes: [ 0x6d, 0x00, 0x02, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x204" + - + input: + bytes: [ 0x37, 0x0f, 0x04, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0, #0x4" + - + input: + bytes: [ 0x02, 0xd4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d13" + - + input: + bytes: [ 0x49, 0x42, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a4]#0" + - + input: + bytes: [ 0xdf, 0x1f, 0x5d, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0xba" + - + input: + bytes: [ 0x37, 0xf0, 0x03, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0, #0x3" + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0x81 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d8, d15, #0x3f" + - + input: + bytes: [ 0x02, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, d0" + - + input: + bytes: [ 0x6d, 0x00, 0x1f, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x43e" + - + input: + bytes: [ 0x49, 0x33, 0x08, 0x8a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a3, [a3]#-0x1f8" + - + input: + bytes: [ 0x6d, 0x00, 0x72, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x24e4" + - + input: + bytes: [ 0x37, 0x04, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d4, #0, #0x8" + - + input: + bytes: [ 0x3b, 0x00, 0xd0, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #0x2d00" + - + input: + bytes: [ 0xda, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0xf" + - + input: + bytes: [ 0x8f, 0x28, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, d8, #0x2" + - + input: + bytes: [ 0x10, 0xe4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a4, a14, d15, #0" + - + input: + bytes: [ 0xa6, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d8, d2" + - + input: + bytes: [ 0xb7, 0x0f, 0x1c, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0, #0x1c" + - + input: + bytes: [ 0x6d, 0x00, 0xea, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x23d4" + - + input: + bytes: [ 0x7e, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0xa" + - + input: + bytes: [ 0x4b, 0x02, 0x71, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftouz d0, d2" + - + input: + bytes: [ 0x37, 0x01, 0x04, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d1, d1, d0, #0x8, #0x4" + - + input: + bytes: [ 0x3c, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x1c" + - + input: + bytes: [ 0xd9, 0x22, 0x34, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x6034" + - + input: + bytes: [ 0x6d, 0xff, 0xde, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x44" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x6100" + - + input: + bytes: [ 0x6d, 0xff, 0x22, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3bc" + - + input: + bytes: [ 0xd9, 0x22, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x8" + - + input: + bytes: [ 0x06, 0xec ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d12, #-0x2" + - + input: + bytes: [ 0xc2, 0x81 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d1, #-0x8" + - + input: + bytes: [ 0x8f, 0x3f, 0x00, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d1, d15, #0x3" + - + input: + bytes: [ 0x82, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d5, #0" + - + input: + bytes: [ 0x8b, 0xf2, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d2, #0xf" + - + input: + bytes: [ 0xdf, 0x00, 0x2e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d0, #0, #0x5c" + - + input: + bytes: [ 0xa0, 0x35 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a5, #0x3" + - + input: + bytes: [ 0xd9, 0x22, 0x04, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x6084" + - + input: + bytes: [ 0x4b, 0x08, 0x61, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "utof d0, d8" + - + input: + bytes: [ 0x06, 0xaf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, #-0x6" + - + input: + bytes: [ 0x6d, 0x00, 0x03, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x206" + - + input: + bytes: [ 0x37, 0x0f, 0xe1, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x5, #0x1" + - + input: + bytes: [ 0x0f, 0xf1, 0x10, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d1, d1, d15" + - + input: + bytes: [ 0xdf, 0x2f, 0x91, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x2, #-0xde" + - + input: + bytes: [ 0x82, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x2" + - + input: + bytes: [ 0x8f, 0xf0, 0x83, 0x31 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d3, d0, #0x3f" + - + input: + bytes: [ 0xd9, 0x55, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#0x30" + - + input: + bytes: [ 0xdf, 0x1f, 0xfe, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0x1, #-0x4" + - + input: + bytes: [ 0x02, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, d0" + - + input: + bytes: [ 0xda, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x40" + - + input: + bytes: [ 0xc2, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, #-0x1" + - + input: + bytes: [ 0x16, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0x1" + - + input: + bytes: [ 0x80, 0xcf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d15, a12" + - + input: + bytes: [ 0x82, 0x34 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x3" + - + input: + bytes: [ 0x49, 0xff, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0" + - + input: + bytes: [ 0x6d, 0x00, 0x3a, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1074" + - + input: + bytes: [ 0x6d, 0xff, 0x9c, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xac8" + - + input: + bytes: [ 0x8f, 0x7f, 0x00, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d2, d15, #0x7" + - + input: + bytes: [ 0x7f, 0x80, 0x04, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d0, d8, #0x8" + - + input: + bytes: [ 0x82, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0" + - + input: + bytes: [ 0x6d, 0xff, 0xbc, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x488" + - + input: + bytes: [ 0x6d, 0xff, 0xe8, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x830" + - + input: + bytes: [ 0x37, 0xf0, 0x07, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0, #0x7" + - + input: + bytes: [ 0x3b, 0x00, 0x98, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x980" + - + input: + bytes: [ 0x6d, 0x00, 0xbe, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x157c" + - + input: + bytes: [ 0x6d, 0xff, 0x00, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x800" + - + input: + bytes: [ 0x8b, 0x3f, 0x20, 0x43 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min.u d4, d15, #0x3" + - + input: + bytes: [ 0xda, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x2" + - + input: + bytes: [ 0x02, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d2" + - + input: + bytes: [ 0x3c, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x36" + - + input: + bytes: [ 0xa0, 0x56 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a6, #0x5" + - + input: + bytes: [ 0xfe, 0xdb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d13, #0x36" + - + input: + bytes: [ 0x26, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d1, d15" + - + input: + bytes: [ 0x6d, 0x00, 0xdc, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x11b8" + - + input: + bytes: [ 0x82, 0x27 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d7, #0x2" + - + input: + bytes: [ 0x4b, 0xf0, 0x51, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d2, d0, d15" + - + input: + bytes: [ 0x3c, 0x27 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x4e" + - + input: + bytes: [ 0xc6, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d1, d15" + - + input: + bytes: [ 0x15, 0xd0, 0xc0, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "stucx #0xd0003fc0" + - + input: + bytes: [ 0x6d, 0x00, 0xa4, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x548" + - + input: + bytes: [ 0x37, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0, #0x8" + - + input: + bytes: [ 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x0" + - + input: + bytes: [ 0x53, 0x42, 0x20, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d1, d2, #0x4" + - + input: + bytes: [ 0x26, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d2" + - + input: + bytes: [ 0x15, 0xd0, 0xc0, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lducx #0xd0003fc0" + - + input: + bytes: [ 0x4b, 0xf1, 0x11, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.u e2, d1, d15" + - + input: + bytes: [ 0x6d, 0xff, 0x9d, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xc6" + - + input: + bytes: [ 0x1d, 0x00, 0x03, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x6" + - + input: + bytes: [ 0xac, 0xa2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x4, d15" + - + input: + bytes: [ 0xc6, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d15, d1" + - + input: + bytes: [ 0x6d, 0x00, 0x53, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xa6" + - + input: + bytes: [ 0xa0, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a15, #0" + - + input: + bytes: [ 0x2e, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #0x6" + - + input: + bytes: [ 0x5f, 0x9f, 0x23, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d9, #0x46" + - + input: + bytes: [ 0x3f, 0xfc, 0xc9, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d12, d15, #-0x6e" + - + input: + bytes: [ 0x02, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, d4" + - + input: + bytes: [ 0x80, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d15, a15" + - + input: + bytes: [ 0x30, 0x43 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a3, a4" + - + input: + bytes: [ 0xdf, 0x7f, 0xf6, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x7, #-0x14" + - + input: + bytes: [ 0x4b, 0xf2, 0x51, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d15, d2, d15" + - + input: + bytes: [ 0x26, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d2, d0" + - + input: + bytes: [ 0x6d, 0x00, 0x4a, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x894" + - + input: + bytes: [ 0x6d, 0xff, 0x28, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1b0" + - + input: + bytes: [ 0x6d, 0x00, 0xc6, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x218c" + - + input: + bytes: [ 0x06, 0x62 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d2, #0x6" + - + input: + bytes: [ 0x37, 0x0f, 0xe1, 0xb1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d11, d15, #0x3, #0x1" + - + input: + bytes: [ 0x3c, 0x63 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xc6" + - + input: + bytes: [ 0xa6, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d4" + - + input: + bytes: [ 0xd7, 0x10, 0x21, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "imask e0, #0x1, d15, #0x1" + - + input: + bytes: [ 0x3f, 0x40, 0xe3, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, d4, #-0x3a" + - + input: + bytes: [ 0xa6, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d2, d1" + - + input: + bytes: [ 0x06, 0xef ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, #-0x2" + - + input: + bytes: [ 0x6d, 0x00, 0xa5, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x174a" + - + input: + bytes: [ 0xbf, 0x81, 0xf3, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d1, #0x8, #-0x1a" + - + input: + bytes: [ 0x3e, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x10" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x5000" + - + input: + bytes: [ 0x37, 0x0f, 0x70, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d2, d15, #0, #0x10" + - + input: + bytes: [ 0xd9, 0x44, 0x94, 0xd2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x2b54" + - + input: + bytes: [ 0xb7, 0x0f, 0x02, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0, #0x2" + - + input: + bytes: [ 0x53, 0x8f, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d15, #0x8" + - + input: + bytes: [ 0x76, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d2, #0x6" + - + input: + bytes: [ 0xc6, 0x3f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d15, d3" + - + input: + bytes: [ 0x5f, 0x8f, 0x28, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d8, #0x50" + - + input: + bytes: [ 0x8f, 0x31, 0x40, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d1, #0x3" + - + input: + bytes: [ 0x37, 0xf1, 0x82, 0x16 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d1, d1, d15, #0xd, #0x2" + - + input: + bytes: [ 0x6d, 0xff, 0x1e, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xbc4" + - + input: + bytes: [ 0x0f, 0x31, 0x10, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d1, d1, d3" + - + input: + bytes: [ 0xf6, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d2, #0xc" + - + input: + bytes: [ 0x6f, 0x70, 0xec, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d0, #0x7, #-0x28" + - + input: + bytes: [ 0x5e, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x12" + - + input: + bytes: [ 0x91, 0x20, 0x00, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x5002" + - + input: + bytes: [ 0x37, 0x0f, 0x61, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x4, #0x1" + - + input: + bytes: [ 0x01, 0xdd, 0x00, 0xd6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a13, a13, d13, #0" + - + input: + bytes: [ 0x53, 0x42, 0x20, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d3, d2, #0x4" + - + input: + bytes: [ 0xd9, 0xff, 0xd8, 0xc0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0xf18" + - + input: + bytes: [ 0xf6, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d2, #0x6" + - + input: + bytes: [ 0x53, 0x47, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d0, d7, #0x4" + - + input: + bytes: [ 0x82, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, #0" + - + input: + bytes: [ 0x37, 0x0f, 0x01, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x4, #0x1" + - + input: + bytes: [ 0x6d, 0xff, 0x87, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xaf2" + - + input: + bytes: [ 0x8b, 0x09, 0x01, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d9, #0x10" + - + input: + bytes: [ 0xbf, 0x89, 0xea, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d9, #0x8, #-0x2c" + - + input: + bytes: [ 0x6d, 0x00, 0x87, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x50e" + - + input: + bytes: [ 0xb0, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a4, #0x1" + - + input: + bytes: [ 0x6d, 0x00, 0x91, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x122" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x4000" + - + input: + bytes: [ 0xdf, 0x0c, 0xd3, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d12, #0, #-0x5a" + - + input: + bytes: [ 0x60, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a15, d4" + - + input: + bytes: [ 0x82, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0" + - + input: + bytes: [ 0x37, 0x0f, 0x02, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x6, #0x2" + - + input: + bytes: [ 0x37, 0x4f, 0x9f, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d4, #0x1, #0x1f" + - + input: + bytes: [ 0x6d, 0xff, 0xc3, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x7a" + - + input: + bytes: [ 0xbe, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x3e" + - + input: + bytes: [ 0x53, 0x41, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d1, #0x4" + - + input: + bytes: [ 0xb7, 0x2f, 0x02, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x2, #0xa, #0x2" + - + input: + bytes: [ 0xfc, 0x6e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a6, #-0x4" + - + input: + bytes: [ 0x37, 0x00, 0x6e, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0x2, #0xe" + - + input: + bytes: [ 0x3c, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x18" + - + input: + bytes: [ 0x37, 0xf3, 0x08, 0x38 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d3, d3, d15, #0x10, #0x8" + - + input: + bytes: [ 0x6d, 0x00, 0xbc, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1378" + - + input: + bytes: [ 0x8b, 0x09, 0x01, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d4, d9, #0x10" + - + input: + bytes: [ 0x53, 0x47, 0x20, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d1, d7, #0x4" + - + input: + bytes: [ 0x86, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d3, #0x2" + - + input: + bytes: [ 0x10, 0xe5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a5, a14, d15, #0" + - + input: + bytes: [ 0x02, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, d2" + - + input: + bytes: [ 0x6d, 0xff, 0xb9, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x8e" + - + input: + bytes: [ 0x10, 0xcc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a12, a12, d15, #0" + - + input: + bytes: [ 0xd9, 0xff, 0x14, 0x36 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x60d4" + - + input: + bytes: [ 0xbf, 0x21, 0xcb, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d1, #0x2, #-0x6a" + - + input: + bytes: [ 0x82, 0x32 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, #0x3" + - + input: + bytes: [ 0x6d, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x8" + - + input: + bytes: [ 0x6e, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x40" + - + input: + bytes: [ 0x6d, 0x00, 0x38, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1670" + - + input: + bytes: [ 0xd9, 0xff, 0x30, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x10b0" + - + input: + bytes: [ 0x6d, 0xff, 0x9a, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xcc" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a0, #0" + - + input: + bytes: [ 0xc6, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d2, d0" + - + input: + bytes: [ 0x53, 0xcc, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d12, #0xc" + - + input: + bytes: [ 0x02, 0xb4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d11" + - + input: + bytes: [ 0x3c, 0xed ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x26" + - + input: + bytes: [ 0x02, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, d15" + - + input: + bytes: [ 0x6d, 0xff, 0xd6, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xe54" + - + input: + bytes: [ 0x37, 0x0f, 0x82, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x3, #0x2" + - + input: + bytes: [ 0x6e, 0xc9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #-0x6e" + - + input: + bytes: [ 0x3b, 0x90, 0xd0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x3d09" + - + input: + bytes: [ 0x16, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0xf" + - + input: + bytes: [ 0x02, 0x2a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d10, d2" + - + input: + bytes: [ 0xf6, 0x83 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d8, #0x6" + - + input: + bytes: [ 0xc2, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d4, #-0x1" + - + input: + bytes: [ 0x37, 0x21, 0x81, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d1, d1, d2, #0xf, #0x1" + - + input: + bytes: [ 0xa6, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d0, d1" + - + input: + bytes: [ 0xfc, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a15, #-0x14" + - + input: + bytes: [ 0xdf, 0x1f, 0x23, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x46" + - + input: + bytes: [ 0x82, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #-0x1" + - + input: + bytes: [ 0x10, 0xe2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a14, d15, #0" + - + input: + bytes: [ 0xd9, 0xff, 0x0c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0xc" + - + input: + bytes: [ 0x16, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0x7f" + - + input: + bytes: [ 0xc2, 0xc5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d5, #-0x4" + - + input: + bytes: [ 0x3c, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x6" + - + input: + bytes: [ 0x5e, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0xe" + - + input: + bytes: [ 0x0f, 0x10, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d0, d0, d1" + - + input: + bytes: [ 0x9b, 0xe2, 0xcb, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d2, d2, #0x4cbe" + - + input: + bytes: [ 0xc2, 0x1c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d12, #0x1" + - + input: + bytes: [ 0x80, 0xd0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d0, a13" + - + input: + bytes: [ 0x6d, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1d0" + - + input: + bytes: [ 0xdf, 0x04, 0x31, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d4, #0, #0x62" + - + input: + bytes: [ 0x3c, 0xc4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x78" + - + input: + bytes: [ 0xd9, 0xff, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x6400" + - + input: + bytes: [ 0x16, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0x7" + - + input: + bytes: [ 0x89, 0xa2, 0x84, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x4, d2" + - + input: + bytes: [ 0x37, 0x0f, 0x62, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x4, #0x2" + - + input: + bytes: [ 0xfc, 0x4e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a4, #-0x4" + - + input: + bytes: [ 0x86, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d1, #0x2" + - + input: + bytes: [ 0x7b, 0xa0, 0x47, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d0, #0x447a" + - + input: + bytes: [ 0xd9, 0x44, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x4" + - + input: + bytes: [ 0x0f, 0xf0, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d0, d0, d15" + - + input: + bytes: [ 0xd9, 0xff, 0x32, 0x31 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x10f2" + - + input: + bytes: [ 0x82, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #0x4" + - + input: + bytes: [ 0xe2, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d0" + - + input: + bytes: [ 0x01, 0xcd, 0x00, 0xc6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a12, a12, d13, #0" + - + input: + bytes: [ 0x37, 0x21, 0x81, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d1, d1, d2, #0x17, #0x1" + - + input: + bytes: [ 0x82, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #-0x1" + - + input: + bytes: [ 0x10, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, a2, d15, #0" + - + input: + bytes: [ 0x3b, 0xd0, 0x7b, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x37bd" + - + input: + bytes: [ 0xd9, 0x2d, 0x40, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a13, [a2]#0x480" + - + input: + bytes: [ 0x3c, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x28" + - + input: + bytes: [ 0x6f, 0x0f, 0xff, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #-0x2" + - + input: + bytes: [ 0xd9, 0x11, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a1, [a1]#0" + - + input: + bytes: [ 0x3c, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x16" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x100" + - + input: + bytes: [ 0x6f, 0x04, 0x05, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d4, #0, #0xa" + - + input: + bytes: [ 0x26, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d1" + - + input: + bytes: [ 0x10, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a4, a15, d15, #0" + - + input: + bytes: [ 0x6d, 0x00, 0x1b, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x36" + - + input: + bytes: [ 0x82, 0x42 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, #0x4" + - + input: + bytes: [ 0x6d, 0xff, 0xc0, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x80" + - + input: + bytes: [ 0x8b, 0x09, 0x01, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d9, #0x10" + - + input: + bytes: [ 0x3f, 0xf0, 0xfd, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, d15, #-0x6" + - + input: + bytes: [ 0xb7, 0x2f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x2, #0, #0x8" + - + input: + bytes: [ 0x3b, 0xf0, 0x01, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x1f" + - + input: + bytes: [ 0xe2, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d0, d15" + - + input: + bytes: [ 0x6d, 0x00, 0x0d, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1a" + - + input: + bytes: [ 0x09, 0xff, 0xc6, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d15, [a15]#0x6" + - + input: + bytes: [ 0x40, 0xbf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a15, a11" + - + input: + bytes: [ 0x37, 0x03, 0x68, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d3, #0x10, #0x8" + - + input: + bytes: [ 0x53, 0xcf, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d15, #0xc" + - + input: + bytes: [ 0x7f, 0xf8, 0x0b, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d8, d15, #0x16" + - + input: + bytes: [ 0x60, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a4, d1" + - + input: + bytes: [ 0x6d, 0xff, 0x2e, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x5a4" + - + input: + bytes: [ 0xa2, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d12, d15" + - + input: + bytes: [ 0xb7, 0x00, 0x82, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, #0x5, #0x2" + - + input: + bytes: [ 0x3b, 0xf0, 0x00, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d3, #0xf" + - + input: + bytes: [ 0x8f, 0x23, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, d3, #0x2" + - + input: + bytes: [ 0x6d, 0x00, 0x44, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x88" + - + input: + bytes: [ 0x82, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d6, #0" + - + input: + bytes: [ 0x60, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a2, d2" + - + input: + bytes: [ 0x8f, 0x21, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, d1, #0x2" + - + input: + bytes: [ 0xd9, 0x22, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0" + - + input: + bytes: [ 0x20, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.a sp, #0x8" + - + input: + bytes: [ 0x96, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x20" + - + input: + bytes: [ 0x37, 0x0f, 0x03, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0, #0x3" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x6000" + - + input: + bytes: [ 0x6d, 0x00, 0xc4, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x388" + - + input: + bytes: [ 0x6f, 0x0f, 0xfc, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #-0x8" + - + input: + bytes: [ 0xff, 0x3f, 0x0b, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d15, #0x3, #0x16" + - + input: + bytes: [ 0x6d, 0x00, 0xfa, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x23f4" + - + input: + bytes: [ 0x76, 0x6b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d6, #0x16" + - + input: + bytes: [ 0x6d, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x68" + - + input: + bytes: [ 0x49, 0xa5, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [sp]#0" + - + input: + bytes: [ 0x91, 0x20, 0x00, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0x6002" + - + input: + bytes: [ 0xff, 0x88, 0x1f, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d8, #0x8, #0x3e" + - + input: + bytes: [ 0x10, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, a15, d15, #0" + - + input: + bytes: [ 0x6d, 0xff, 0xf2, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x41c" + - + input: + bytes: [ 0xd9, 0xff, 0x30, 0x36 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x60f0" + - + input: + bytes: [ 0x02, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d9, d2" + - + input: + bytes: [ 0xdf, 0x08, 0x92, 0x81 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d8, #0, #0x324" + - + input: + bytes: [ 0xb7, 0x5f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x5, #0, #0x8" + - + input: + bytes: [ 0x8f, 0x7f, 0x00, 0x31 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d3, d15, #0x7" + - + input: + bytes: [ 0x37, 0x0f, 0x02, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x4, #0x2" + - + input: + bytes: [ 0x6d, 0x00, 0x8c, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x318" + - + input: + bytes: [ 0x9a, 0x81 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d1, #-0x8" + - + input: + bytes: [ 0x7b, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d0, #0xd000" + - + input: + bytes: [ 0x40, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a15, a4" + - + input: + bytes: [ 0xd9, 0x88, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a8, [a8]#0" + - + input: + bytes: [ 0x6d, 0x00, 0xf9, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xff2" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0x8000" + - + input: + bytes: [ 0x89, 0xa2, 0x82, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x2, d2" + - + input: + bytes: [ 0x10, 0xcf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, a12, d15, #0" + - + input: + bytes: [ 0x82, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d7, #0" + - + input: + bytes: [ 0x6d, 0xff, 0xb2, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x9c" + - + input: + bytes: [ 0x6d, 0xff, 0x94, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xad8" + - + input: + bytes: [ 0xb7, 0x0f, 0x81, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0x3, #0x1" + - + input: + bytes: [ 0x6d, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x70" + - + input: + bytes: [ 0x02, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, d2" + - + input: + bytes: [ 0xbb, 0x00, 0x68, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d15, #0x9680" + - + input: + bytes: [ 0xd9, 0xff, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x8" + - + input: + bytes: [ 0x26, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d2, d15" + - + input: + bytes: [ 0x09, 0xff, 0xc4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d15, [a15]#0x4" + - + input: + bytes: [ 0x91, 0x30, 0x88, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0xf883" + - + input: + bytes: [ 0x37, 0xbf, 0x81, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d11, #0x3, #0x1" + - + input: + bytes: [ 0x10, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a15, d15, #0" + - + input: + bytes: [ 0xe2, 0x9f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d9" + - + input: + bytes: [ 0xa2, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d15, d0" + - + input: + bytes: [ 0xfc, 0x5e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a5, #-0x4" + - + input: + bytes: [ 0x3b, 0x00, 0xd0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x2d00" + - + input: + bytes: [ 0x02, 0x82 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, d8" + - + input: + bytes: [ 0x40, 0x5f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a15, a5" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a1, #0" + - + input: + bytes: [ 0x4b, 0xf2, 0x51, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d2, d2, d15" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x8000" + - + input: + bytes: [ 0x37, 0xf0, 0x02, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0x1c, #0x2" + - + input: + bytes: [ 0x6d, 0xff, 0x85, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xaf6" + - + input: + bytes: [ 0x02, 0x2b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d11, d2" + - + input: + bytes: [ 0x0f, 0x0f, 0x10, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, d15, d0" + - + input: + bytes: [ 0x6d, 0xff, 0x26, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1b4" + - + input: + bytes: [ 0xd9, 0xff, 0xac, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x8ec" + - + input: + bytes: [ 0x02, 0x5f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, d5" + - + input: + bytes: [ 0x6e, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x12" + - + input: + bytes: [ 0x6d, 0xff, 0x21, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x5be" + - + input: + bytes: [ 0x91, 0x20, 0x00, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x7002" + - + input: + bytes: [ 0x91, 0x20, 0x00, 0xa5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a sp, #0x5002" + - + input: + bytes: [ 0x6d, 0xff, 0xa6, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xb4" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x6000" + - + input: + bytes: [ 0x6d, 0xff, 0xbd, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x86" + - + input: + bytes: [ 0x82, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d10, #0" + - + input: + bytes: [ 0xa0, 0xc6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a6, #0xc" + - + input: + bytes: [ 0xd9, 0x3f, 0x14, 0x36 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a3]#0x60d4" + - + input: + bytes: [ 0x6d, 0x00, 0xea, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x3d4" + - + input: + bytes: [ 0x9a, 0xd4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d4, #-0x3" + - + input: + bytes: [ 0x8f, 0xf0, 0x83, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d4, d0, #0x3f" + - + input: + bytes: [ 0xdf, 0x04, 0x7c, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d4, #0, #-0x108" + - + input: + bytes: [ 0x6d, 0x00, 0x54, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x8a8" + - + input: + bytes: [ 0x02, 0x84 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d8" + - + input: + bytes: [ 0xdf, 0x0c, 0xe0, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d12, #0, #-0x40" + - + input: + bytes: [ 0x6d, 0x00, 0xc3, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1786" + - + input: + bytes: [ 0x3c, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x8" + - + input: + bytes: [ 0x37, 0xf3, 0x08, 0x34 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d3, d3, d15, #0x8, #0x8" + - + input: + bytes: [ 0xda, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x4" + - + input: + bytes: [ 0xbb, 0x70, 0x71, 0x4b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d4, #0xb717" + - + input: + bytes: [ 0x96, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x80" + - + input: + bytes: [ 0x37, 0x0f, 0x68, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d2, d15, #0, #0x8" + - + input: + bytes: [ 0x6d, 0xff, 0x73, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x151a" + - + input: + bytes: [ 0x96, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x4" + - + input: + bytes: [ 0x7e, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x1a" + - + input: + bytes: [ 0x7b, 0x00, 0x2f, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d15, #0x42f0" + - + input: + bytes: [ 0x9b, 0x6f, 0x02, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d15, d15, #0x26" + - + input: + bytes: [ 0xda, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x1" + - + input: + bytes: [ 0x9b, 0xe0, 0xcb, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d0, d0, #0x4cbe" + - + input: + bytes: [ 0x26, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d1" + - + input: + bytes: [ 0x96, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x40" + - + input: + bytes: [ 0x6d, 0xff, 0xbd, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x486" + - + input: + bytes: [ 0x6d, 0xff, 0x71, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x11e" + - + input: + bytes: [ 0x37, 0x0f, 0xe1, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x3, #0x1" + - + input: + bytes: [ 0x37, 0xf0, 0x04, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0, #0x4" + - + input: + bytes: [ 0x6f, 0x1f, 0xf8, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x1, #-0x10" + - + input: + bytes: [ 0xb7, 0x1f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x1, #0, #0x8" + - + input: + bytes: [ 0x37, 0xf0, 0x02, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0x4, #0x2" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a9, #0" + - + input: + bytes: [ 0xd9, 0xff, 0x44, 0x60 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x584" + - + input: + bytes: [ 0xb7, 0x1f, 0x02, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x1, #0x4, #0x2" + - + input: + bytes: [ 0x37, 0x0f, 0x05, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0, #0x5" + - + input: + bytes: [ 0x37, 0x04, 0x68, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d4, #0, #0x8" + - + input: + bytes: [ 0x6d, 0xff, 0xde, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x444" + - + input: + bytes: [ 0xdf, 0x1f, 0x57, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0xae" + - + input: + bytes: [ 0xa2, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d0, d15" + - + input: + bytes: [ 0x02, 0xc4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d12" + - + input: + bytes: [ 0x6d, 0x00, 0x2f, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x5e" + - + input: + bytes: [ 0xb7, 0x01, 0x02, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d2, d1, #0, #0, #0x2" + - + input: + bytes: [ 0x4b, 0xaf, 0x41, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d15, d15, d10" + - + input: + bytes: [ 0x6d, 0xff, 0xfe, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x404" + - + input: + bytes: [ 0x6d, 0x00, 0xbb, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x376" + - + input: + bytes: [ 0xd9, 0xff, 0x18, 0x46 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x6118" + - + input: + bytes: [ 0x6e, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0xe" + - + input: + bytes: [ 0x53, 0x80, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d0, #0x8" + - + input: + bytes: [ 0xd9, 0x44, 0x88, 0x72 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x29c8" + - + input: + bytes: [ 0x3c, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x12" + - + input: + bytes: [ 0x37, 0x0c, 0x68, 0xc0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d12, d12, #0, #0x8" + - + input: + bytes: [ 0x37, 0xf0, 0x87, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0x1, #0x7" + - + input: + bytes: [ 0x6d, 0x00, 0x71, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x24e2" + - + input: + bytes: [ 0x37, 0x4f, 0x01, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d4, #0xe, #0x1" + - + input: + bytes: [ 0x3c, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x1a" + - + input: + bytes: [ 0x37, 0x01, 0x81, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d1, d0, #0x3, #0x1" + - + input: + bytes: [ 0xff, 0x8f, 0x1a, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d15, #0x8, #0x34" + - + input: + bytes: [ 0x80, 0xdf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d15, a13" + - + input: + bytes: [ 0xc2, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, #0x1" + - + input: + bytes: [ 0x4b, 0x8f, 0x41, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d15, d15, d8" + - + input: + bytes: [ 0xc2, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d1, #-0x1" + - + input: + bytes: [ 0x8b, 0xff, 0x21, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min.u d15, d15, #0x1f" + - + input: + bytes: [ 0x40, 0xd2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a2, a13" + - + input: + bytes: [ 0x9a, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d2, #0x2" + - + input: + bytes: [ 0x49, 0xa4, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [sp]#0" + - + input: + bytes: [ 0x3f, 0x08, 0x08, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d8, d0, #0x10" + - + input: + bytes: [ 0x03, 0xf4, 0x0a, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd d15, d5, d4, d15" + - + input: + bytes: [ 0xd9, 0xff, 0x80, 0xc9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x6500" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0x6000" + - + input: + bytes: [ 0x6d, 0x00, 0xf9, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x15f2" + - + input: + bytes: [ 0x0f, 0x80, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d0, d0, d8" + - + input: + bytes: [ 0xd9, 0xff, 0x28, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x1028" + - + input: + bytes: [ 0x91, 0x20, 0x00, 0xa6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a sp, #0x6002" + - + input: + bytes: [ 0x02, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d12, d0" + - + input: + bytes: [ 0xd9, 0x55, 0x0c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#0xc" + - + input: + bytes: [ 0xb7, 0x3f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x3, #0, #0x8" + - + input: + bytes: [ 0x6f, 0x0f, 0xf2, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #-0x1c" + - + input: + bytes: [ 0x4b, 0x0f, 0x71, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftouz d15, d15" + - + input: + bytes: [ 0x53, 0x61, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d1, #0x6" + - + input: + bytes: [ 0x6d, 0xff, 0x5c, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x548" + - + input: + bytes: [ 0x91, 0xf0, 0x01, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x801f" + - + input: + bytes: [ 0xd9, 0xff, 0xc0, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x4400" + - + input: + bytes: [ 0xda, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x8" + - + input: + bytes: [ 0x02, 0x94 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d9" + - + input: + bytes: [ 0x6d, 0x00, 0x29, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x852" + - + input: + bytes: [ 0x37, 0xf1, 0x04, 0x18 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d1, d1, d15, #0x10, #0x4" + - + input: + bytes: [ 0x37, 0xf0, 0x01, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0x2, #0x1" + - + input: + bytes: [ 0x7d, 0xf4, 0x04, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne.a a4, a15, #0x8" + - + input: + bytes: [ 0xd9, 0x22, 0x00, 0x16 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x6040" + - + input: + bytes: [ 0x8f, 0x10, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d0, #0x1" + - + input: + bytes: [ 0x3e, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d2, #0x10" + - + input: + bytes: [ 0xfe, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x28" + - + input: + bytes: [ 0x4b, 0x0f, 0x51, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d15, d15, d0" + - + input: + bytes: [ 0xdf, 0x0c, 0x86, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d12, #0, #-0xf4" + - + input: + bytes: [ 0xc2, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, #0x1" + - + input: + bytes: [ 0x8f, 0x3c, 0x00, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d12, #0x3" + - + input: + bytes: [ 0x6d, 0x00, 0x92, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x124" + - + input: + bytes: [ 0x6d, 0xff, 0xea, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x42c" + - + input: + bytes: [ 0x5f, 0x0f, 0x22, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x44" + - + input: + bytes: [ 0x3c, 0x36 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x6c" + - + input: + bytes: [ 0x82, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d9, #0" + - + input: + bytes: [ 0x5e, 0x43 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x4, #0x6" diff --git a/tests/MC/TriCore/ADC_Queued_Scan_1_KIT_TC397_TFT.s.yaml b/tests/MC/TriCore/ADC_Queued_Scan_1_KIT_TC397_TFT.s.yaml new file mode 100644 index 0000000000..4c9319c6a9 --- /dev/null +++ b/tests/MC/TriCore/ADC_Queued_Scan_1_KIT_TC397_TFT.s.yaml @@ -0,0 +1,8659 @@ +test_cases: + - + input: + bytes: [ 0xdf, 0x0f, 0x08, 0x82 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0, #0x410" + - + input: + bytes: [ 0x91, 0x10, 0x00, 0x25 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0x5001" + - + input: + bytes: [ 0x6d, 0xff, 0xef, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x822" + - + input: + bytes: [ 0x3f, 0xf1, 0xef, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d1, d15, #-0x22" + - + input: + bytes: [ 0x01, 0xd0, 0x00, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a13, d0, #0" + - + input: + bytes: [ 0x8f, 0x24, 0x40, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d4, #0x2" + - + input: + bytes: [ 0xbe, 0x6a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d6, #0x34" + - + input: + bytes: [ 0x3c, 0x64 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xc8" + - + input: + bytes: [ 0x4b, 0x0f, 0x41, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d15, d15, d0" + - + input: + bytes: [ 0x37, 0x0f, 0x04, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0, #0x4" + - + input: + bytes: [ 0x10, 0xe5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a5, a14, d15, #0" + - + input: + bytes: [ 0x37, 0x00, 0x48, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d15, d0, #0, #0x8" + - + input: + bytes: [ 0xd9, 0xff, 0x28, 0xa6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x62a8" + - + input: + bytes: [ 0x3c, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x10" + - + input: + bytes: [ 0x37, 0x0f, 0x81, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x1f, #0x1" + - + input: + bytes: [ 0x37, 0x03, 0x68, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d3, #0x8, #0x8" + - + input: + bytes: [ 0x37, 0xf3, 0x08, 0x34 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d3, d3, d15, #0x8, #0x8" + - + input: + bytes: [ 0x80, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d15, a4" + - + input: + bytes: [ 0xd9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a0, [a0]#0" + - + input: + bytes: [ 0x9a, 0xd4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d4, #-0x3" + - + input: + bytes: [ 0x9a, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d0, #0x2" + - + input: + bytes: [ 0xef, 0x8f, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x18, #0x14" + - + input: + bytes: [ 0xd9, 0xff, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x6400" + - + input: + bytes: [ 0xd9, 0x3f, 0x0c, 0x96 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a3]#0x624c" + - + input: + bytes: [ 0x37, 0xf0, 0x03, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0x8, #0x3" + - + input: + bytes: [ 0x3b, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x1000" + - + input: + bytes: [ 0xee, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0xa" + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d2, d15, #0x3f" + - + input: + bytes: [ 0x6d, 0xff, 0x9c, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xec8" + - + input: + bytes: [ 0x37, 0x0f, 0x01, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x2, #0x1" + - + input: + bytes: [ 0x3c, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x12" + - + input: + bytes: [ 0x4b, 0xf0, 0x11, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.u e0, d0, d15" + - + input: + bytes: [ 0x6f, 0x10, 0xf8, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d0, #0x1, #-0x10" + - + input: + bytes: [ 0xdf, 0x1f, 0x23, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x46" + - + input: + bytes: [ 0x76, 0xc5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d12, #0xa" + - + input: + bytes: [ 0x06, 0xef ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, #-0x2" + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0x81 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d8, d15, #0x3f" + - + input: + bytes: [ 0x40, 0x4c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a12, a4" + - + input: + bytes: [ 0x80, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d15, a15" + - + input: + bytes: [ 0x6f, 0x0f, 0xff, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #-0x2" + - + input: + bytes: [ 0x3c, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x16" + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0x31 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d3, d15, #0x3f" + - + input: + bytes: [ 0x09, 0xff, 0xc4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d15, [a15]#0x4" + - + input: + bytes: [ 0x9b, 0x10, 0x13, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d0, d0, #0x131" + - + input: + bytes: [ 0x49, 0x40, 0x40, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ldmst [a4]#0, e0" + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0x91 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d9, d15, #0x3f" + - + input: + bytes: [ 0x02, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d2" + - + input: + bytes: [ 0x37, 0x0f, 0x02, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x1c, #0x2" + - + input: + bytes: [ 0x8b, 0x09, 0x01, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d9, #0x10" + - + input: + bytes: [ 0x60, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a15, d15" + - + input: + bytes: [ 0x6d, 0xff, 0xab, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x8aa" + - + input: + bytes: [ 0xd9, 0xff, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x428" + - + input: + bytes: [ 0xc2, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d9, #0x1" + - + input: + bytes: [ 0xa2, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d15, d1" + - + input: + bytes: [ 0x80, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d0, a15" + - + input: + bytes: [ 0xbe, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d4, #0x22" + - + input: + bytes: [ 0x10, 0xe2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a14, d15, #0" + - + input: + bytes: [ 0x10, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, a2, d15, #0" + - + input: + bytes: [ 0x49, 0x55, 0x0c, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#0xc" + - + input: + bytes: [ 0x06, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d0, #0x5" + - + input: + bytes: [ 0xf6, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d2, #0x8" + - + input: + bytes: [ 0xfc, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a15, #-0x14" + - + input: + bytes: [ 0x37, 0x00, 0x62, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d0, #0x1c, #0x2" + - + input: + bytes: [ 0x6d, 0xb8, 0xf4, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x7023e8" + - + input: + bytes: [ 0x91, 0x00, 0x03, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0xa030" + - + input: + bytes: [ 0x3b, 0x20, 0xfe, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #-0x1e" + - + input: + bytes: [ 0x37, 0x00, 0x61, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0x6, #0x1" + - + input: + bytes: [ 0xda, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x8" + - + input: + bytes: [ 0x60, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a2, d15" + - + input: + bytes: [ 0x6d, 0x00, 0x15, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2a" + - + input: + bytes: [ 0x80, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d2, a15" + - + input: + bytes: [ 0x6d, 0x00, 0x91, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x122" + - + input: + bytes: [ 0x3e, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0xc" + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d1, d15, #0x3f" + - + input: + bytes: [ 0x91, 0x40, 0x00, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x7004" + - + input: + bytes: [ 0x53, 0x40, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d0, #0x4" + - + input: + bytes: [ 0xc6, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d15, d1" + - + input: + bytes: [ 0x3b, 0x90, 0xd0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x3d09" + - + input: + bytes: [ 0x3b, 0xf0, 0x05, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, #0x5f" + - + input: + bytes: [ 0x6d, 0xff, 0x57, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x752" + - + input: + bytes: [ 0xdf, 0x1f, 0x7f, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0xfe" + - + input: + bytes: [ 0xd9, 0xff, 0x88, 0x72 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x29c8" + - + input: + bytes: [ 0x6d, 0xff, 0xb8, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x90" + - + input: + bytes: [ 0xd9, 0x44, 0x0c, 0x96 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x624c" + - + input: + bytes: [ 0x1e, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0x1, #0x4" + - + input: + bytes: [ 0x82, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #-0x1" + - + input: + bytes: [ 0x7f, 0x0f, 0x04, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d15, d0, #0x8" + - + input: + bytes: [ 0x8b, 0xff, 0x21, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min.u d15, d15, #0x1f" + - + input: + bytes: [ 0x37, 0x01, 0x68, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d1, #0x18, #0x8" + - + input: + bytes: [ 0x7b, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d0, #0xd000" + - + input: + bytes: [ 0x4b, 0x0f, 0x41, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d0, d15, d0" + - + input: + bytes: [ 0xb0, 0x4c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a12, #0x4" + - + input: + bytes: [ 0xda, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x1" + - + input: + bytes: [ 0x96, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x1" + - + input: + bytes: [ 0xdf, 0x00, 0x2e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d0, #0, #0x5c" + - + input: + bytes: [ 0xde, 0x1c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x38" + - + input: + bytes: [ 0x10, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, a15, d15, #0" + - + input: + bytes: [ 0x82, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #0x2" + - + input: + bytes: [ 0x96, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x4" + - + input: + bytes: [ 0x53, 0x41, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d1, #0x4" + - + input: + bytes: [ 0x53, 0x88, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d8, #0x8" + - + input: + bytes: [ 0x37, 0x4f, 0x82, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d4, #0xd, #0x2" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x100" + - + input: + bytes: [ 0x37, 0xf0, 0x02, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0x4, #0x2" + - + input: + bytes: [ 0x37, 0x01, 0x81, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d1, d0, #0x1, #0x1" + - + input: + bytes: [ 0x80, 0xdf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d15, a13" + - + input: + bytes: [ 0x82, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d9, #0x1" + - + input: + bytes: [ 0x02, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, d4" + - + input: + bytes: [ 0xd9, 0xff, 0xf4, 0x42 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x2d34" + - + input: + bytes: [ 0x89, 0x40, 0xc1, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachei.wi [a4+]#0x1" + - + input: + bytes: [ 0x91, 0x10, 0x00, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0x3001" + - + input: + bytes: [ 0x6d, 0xff, 0x8b, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2ea" + - + input: + bytes: [ 0x3c, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x3e" + - + input: + bytes: [ 0x6d, 0x00, 0xce, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1b9c" + - + input: + bytes: [ 0xda, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x7f" + - + input: + bytes: [ 0xd9, 0xff, 0x24, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x164" + - + input: + bytes: [ 0xd9, 0xff, 0x7a, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x57a" + - + input: + bytes: [ 0xbf, 0x38, 0xef, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d8, #0x3, #-0x22" + - + input: + bytes: [ 0x8b, 0x87, 0x01, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d1, d7, #0x18" + - + input: + bytes: [ 0x3b, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x6000" + - + input: + bytes: [ 0x91, 0x10, 0x00, 0xa4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a sp, #0x4001" + - + input: + bytes: [ 0x37, 0xf0, 0x02, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0x1c, #0x2" + - + input: + bytes: [ 0xd9, 0xff, 0xc8, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x2c88" + - + input: + bytes: [ 0x6d, 0xb8, 0x80, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x702300" + - + input: + bytes: [ 0x15, 0xd0, 0xc0, 0xeb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ldlcx #0xd0003f80" + - + input: + bytes: [ 0x4b, 0x00, 0x41, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "itof d0, d0" + - + input: + bytes: [ 0xb4, 0xc2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a12], d2" + - + input: + bytes: [ 0x40, 0xd5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a5, a13" + - + input: + bytes: [ 0x80, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d0, a5" + - + input: + bytes: [ 0x8f, 0x34, 0x40, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d4, #0x3" + - + input: + bytes: [ 0x26, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d3, d15" + - + input: + bytes: [ 0xc6, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d3, d15" + - + input: + bytes: [ 0x37, 0x0f, 0x6e, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x2, #0xe" + - + input: + bytes: [ 0x02, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, d4" + - + input: + bytes: [ 0xd9, 0xff, 0x6c, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x46c" + - + input: + bytes: [ 0xb0, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a4, #0x1" + - + input: + bytes: [ 0x6f, 0x00, 0x1f, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d0, #0, #0x3e" + - + input: + bytes: [ 0xd9, 0xff, 0x0c, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x10c" + - + input: + bytes: [ 0x7b, 0x00, 0x00, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d1, #0x1000" + - + input: + bytes: [ 0x6d, 0xff, 0xe6, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x634" + - + input: + bytes: [ 0x6d, 0xff, 0x6e, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x324" + - + input: + bytes: [ 0x3b, 0xf0, 0x0f, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0xff" + - + input: + bytes: [ 0x6d, 0xff, 0x0c, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x9e8" + - + input: + bytes: [ 0x40, 0x5c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a12, a5" + - + input: + bytes: [ 0x37, 0x0f, 0x62, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x6, #0x2" + - + input: + bytes: [ 0xd9, 0x22, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x4" + - + input: + bytes: [ 0x40, 0xc5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a5, a12" + - + input: + bytes: [ 0x53, 0x41, 0x20, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d1, d1, #0x4" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0x8000" + - + input: + bytes: [ 0x82, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d7, #0x1" + - + input: + bytes: [ 0xd9, 0xff, 0x18, 0x96 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x6258" + - + input: + bytes: [ 0x20, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.a sp, #0x8" + - + input: + bytes: [ 0x8f, 0x29, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, d9, #0x2" + - + input: + bytes: [ 0x10, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a2, d15, #0" + - + input: + bytes: [ 0x60, 0xc2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a2, d12" + - + input: + bytes: [ 0xd9, 0xff, 0x30, 0x96 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x6270" + - + input: + bytes: [ 0x37, 0xf0, 0x02, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0, #0x2" + - + input: + bytes: [ 0x6d, 0xa0, 0x80, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x402300" + - + input: + bytes: [ 0x3b, 0x00, 0x00, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x3000" + - + input: + bytes: [ 0x6d, 0x00, 0x26, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xa4c" + - + input: + bytes: [ 0xb7, 0x0f, 0x01, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0x2, #0x1" + - + input: + bytes: [ 0x8f, 0x24, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d0, d4, #0x2" + - + input: + bytes: [ 0x8b, 0xff, 0x01, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsub d15, d15, #0x1f" + - + input: + bytes: [ 0xd9, 0xff, 0x3c, 0x96 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x627c" + - + input: + bytes: [ 0x6d, 0xff, 0x0e, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x9e4" + - + input: + bytes: [ 0x6e, 0x36 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x6c" + - + input: + bytes: [ 0x9b, 0xe1, 0xcb, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d1, d1, #0x4cbe" + - + input: + bytes: [ 0xdc, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ji a15" + - + input: + bytes: [ 0x53, 0x4f, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d15, #0x4" + - + input: + bytes: [ 0xbf, 0x38, 0xce, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d8, #0x3, #-0x64" + - + input: + bytes: [ 0x49, 0xf4, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a15]#0" + - + input: + bytes: [ 0x37, 0xf0, 0x03, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0, #0x3" + - + input: + bytes: [ 0x37, 0x0f, 0xe1, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x5, #0x1" + - + input: + bytes: [ 0x37, 0xf0, 0x02, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0x1e, #0x2" + - + input: + bytes: [ 0x6d, 0xff, 0x1e, 0xe9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2dc4" + - + input: + bytes: [ 0x8f, 0x3f, 0x00, 0xd1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d13, d15, #0x3" + - + input: + bytes: [ 0x91, 0x10, 0x00, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x5001" + - + input: + bytes: [ 0x0f, 0x91, 0x10, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d1, d1, d9" + - + input: + bytes: [ 0x49, 0xfc, 0x14, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a12, [a15]#0x14" + - + input: + bytes: [ 0x6d, 0xff, 0xf4, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xa18" + - + input: + bytes: [ 0xd9, 0xaa, 0x40, 0x89 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea sp, [sp]#-0x6a00" + - + input: + bytes: [ 0x1d, 0x00, 0x03, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x6" + - + input: + bytes: [ 0x91, 0x10, 0x00, 0xa5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a sp, #0x5001" + - + input: + bytes: [ 0x6d, 0x00, 0xc3, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xd86" + - + input: + bytes: [ 0x0f, 0x0f, 0x10, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, d15, d0" + - + input: + bytes: [ 0xd9, 0x99, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a9, [a9]#0" + - + input: + bytes: [ 0x06, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d1, #0x2" + - + input: + bytes: [ 0x4b, 0x04, 0x11, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.u e2, d4, d0" + - + input: + bytes: [ 0x6d, 0xff, 0xd2, 0xe7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x305c" + - + input: + bytes: [ 0x20, 0x58 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.a sp, #0x58" + - + input: + bytes: [ 0x7f, 0xf9, 0x04, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d9, d15, #0x8" + - + input: + bytes: [ 0xee, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0xe" + - + input: + bytes: [ 0x49, 0xcf, 0x38, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a12]#0x38" + - + input: + bytes: [ 0xd9, 0xff, 0x74, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x4f4" + - + input: + bytes: [ 0x4b, 0x10, 0x41, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d0, d0, d1" + - + input: + bytes: [ 0xbf, 0x81, 0x03, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d1, #0x8, #0x6" + - + input: + bytes: [ 0x7f, 0xf9, 0x0b, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d9, d15, #0x16" + - + input: + bytes: [ 0xd9, 0xff, 0x80, 0xc9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x6500" + - + input: + bytes: [ 0x6d, 0xd0, 0xf4, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x5fdc18" + - + input: + bytes: [ 0xb7, 0x0f, 0x02, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0, #0x2" + - + input: + bytes: [ 0xd9, 0x44, 0x08, 0x60 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x188" + - + input: + bytes: [ 0x82, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d6, #0x2" + - + input: + bytes: [ 0x37, 0x01, 0x70, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d2, d1, #0, #0x10" + - + input: + bytes: [ 0xdc, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ji a11" + - + input: + bytes: [ 0xd9, 0xff, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x5c00" + - + input: + bytes: [ 0x8f, 0x00, 0x01, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d0, d0, #0x10" + - + input: + bytes: [ 0x3c, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xe" + - + input: + bytes: [ 0xc2, 0x18 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d8, #0x1" + - + input: + bytes: [ 0x6d, 0xff, 0xce, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x864" + - + input: + bytes: [ 0x6d, 0x00, 0x61, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2c2" + - + input: + bytes: [ 0x6d, 0x00, 0xb7, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x16e" + - + input: + bytes: [ 0x8f, 0x3c, 0x00, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d4, d12, #0x3" + - + input: + bytes: [ 0xc6, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d0, d15" + - + input: + bytes: [ 0x6d, 0xff, 0x04, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xbf8" + - + input: + bytes: [ 0xb7, 0x0f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0, #0x8" + - + input: + bytes: [ 0x91, 0x40, 0x88, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0xf884" + - + input: + bytes: [ 0x6d, 0x00, 0x1b, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1c36" + - + input: + bytes: [ 0xb7, 0x0f, 0x01, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0, #0x1" + - + input: + bytes: [ 0x7e, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x12" + - + input: + bytes: [ 0x8f, 0x24, 0x00, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d4, #0x2" + - + input: + bytes: [ 0x6d, 0xff, 0x8b, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xea" + - + input: + bytes: [ 0x49, 0x33, 0x14, 0x8a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a3, [a3]#-0x1ec" + - + input: + bytes: [ 0xc6, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d0, d1" + - + input: + bytes: [ 0x37, 0x10, 0x01, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d1, #0x2, #0x1" + - + input: + bytes: [ 0x4b, 0x0f, 0x51, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d15, d15, d0" + - + input: + bytes: [ 0x4b, 0x01, 0x51, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d0, d1, d0" + - + input: + bytes: [ 0x1e, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0x1, #0xe" + - + input: + bytes: [ 0x6d, 0xff, 0x80, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x100" + - + input: + bytes: [ 0xbb, 0xf0, 0xff, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d15, #0xffff" + - + input: + bytes: [ 0x3e, 0x4a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d4, #0x14" + - + input: + bytes: [ 0x3b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x400" + - + input: + bytes: [ 0x37, 0xf0, 0x05, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0x4, #0x5" + - + input: + bytes: [ 0x91, 0x00, 0x03, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x8030" + - + input: + bytes: [ 0x8f, 0x21, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, d1, #0x2" + - + input: + bytes: [ 0x7f, 0xf9, 0x0d, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d9, d15, #0x1a" + - + input: + bytes: [ 0x76, 0x91 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d9, #0x2" + - + input: + bytes: [ 0x02, 0x92 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, d9" + - + input: + bytes: [ 0x3f, 0x0f, 0xfd, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d15, d0, #-0x6" + - + input: + bytes: [ 0x6d, 0xe8, 0x17, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2fffd2" + - + input: + bytes: [ 0x82, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, #0" + - + input: + bytes: [ 0x6d, 0xff, 0x05, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x7f6" + - + input: + bytes: [ 0xd9, 0xff, 0x08, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x3088" + - + input: + bytes: [ 0x37, 0x00, 0xe1, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0x1, #0x1" + - + input: + bytes: [ 0x37, 0x0f, 0xe1, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x1, #0x1" + - + input: + bytes: [ 0x76, 0xcf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d12, #0x1e" + - + input: + bytes: [ 0x82, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #0" + - + input: + bytes: [ 0xa2, 0xdc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d12, d13" + - + input: + bytes: [ 0xd9, 0x44, 0x18, 0x60 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x198" + - + input: + bytes: [ 0x9b, 0x81, 0xb9, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d1, d1, #0x4b98" + - + input: + bytes: [ 0xb7, 0x0f, 0x01, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0x18, #0x1" + - + input: + bytes: [ 0x37, 0x0f, 0x05, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x10, #0x5" + - + input: + bytes: [ 0x2d, 0x0f, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jli a15" + - + input: + bytes: [ 0x53, 0x44, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d4, #0x4" + - + input: + bytes: [ 0x91, 0x40, 0x00, 0xa6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a sp, #0x6004" + - + input: + bytes: [ 0x3e, 0x4e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d4, #0x1c" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x6000" + - + input: + bytes: [ 0x6d, 0x00, 0x53, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xa6" + - + input: + bytes: [ 0xb7, 0x0f, 0x0c, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0x14, #0xc" + - + input: + bytes: [ 0xa0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a4, #0" + - + input: + bytes: [ 0x6d, 0xff, 0xed, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1026" + - + input: + bytes: [ 0xd9, 0xff, 0x0c, 0x96 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x624c" + - + input: + bytes: [ 0x3c, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x42" + - + input: + bytes: [ 0x37, 0xf0, 0x02, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0x4, #0x2" + - + input: + bytes: [ 0xdf, 0x0c, 0xe0, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d12, #0, #-0x40" + - + input: + bytes: [ 0xbb, 0xf0, 0xff, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d2, #0xffff" + - + input: + bytes: [ 0x49, 0x42, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a4]#0" + - + input: + bytes: [ 0xd9, 0xff, 0x70, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x4b0" + - + input: + bytes: [ 0x8f, 0xec, 0x1f, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d12, #-0x2" + - + input: + bytes: [ 0xd9, 0x44, 0x28, 0xa6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x62a8" + - + input: + bytes: [ 0x7f, 0xf9, 0x03, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d9, d15, #0x6" + - + input: + bytes: [ 0x91, 0x20, 0x88, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0xf882" + - + input: + bytes: [ 0xbb, 0x00, 0xc2, 0x2b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d2, #0xbc20" + - + input: + bytes: [ 0xa0, 0x15 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a5, #0x1" + - + input: + bytes: [ 0x6d, 0xff, 0xfc, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x208" + - + input: + bytes: [ 0x6d, 0xe8, 0x90, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2fe0e0" + - + input: + bytes: [ 0x6f, 0x1f, 0xfa, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0x1, #-0xc" + - + input: + bytes: [ 0x49, 0x33, 0x08, 0x8a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a3, [a3]#-0x1f8" + - + input: + bytes: [ 0xda, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x10" + - + input: + bytes: [ 0x6f, 0x20, 0xf2, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d0, #0x2, #-0x1c" + - + input: + bytes: [ 0xd9, 0x2e, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a14, [a2]#0x400" + - + input: + bytes: [ 0x26, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d15" + - + input: + bytes: [ 0xb7, 0x01, 0x02, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d2, d1, #0, #0, #0x2" + - + input: + bytes: [ 0x6d, 0xff, 0x99, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x8ce" + - + input: + bytes: [ 0x3e, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d1, #0x4" + - + input: + bytes: [ 0x26, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d2, d0" + - + input: + bytes: [ 0xdf, 0x1f, 0x70, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0xe0" + - + input: + bytes: [ 0x06, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, #0x1" + - + input: + bytes: [ 0x3e, 0x56 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d5, #0xc" + - + input: + bytes: [ 0xda, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x1f" + - + input: + bytes: [ 0xc2, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d1, #-0x1" + - + input: + bytes: [ 0x49, 0xff, 0x00, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x40" + - + input: + bytes: [ 0x4b, 0xf1, 0x41, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d1, d1, d15" + - + input: + bytes: [ 0x6d, 0xff, 0x67, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x732" + - + input: + bytes: [ 0x8f, 0x31, 0x40, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d1, #0x3" + - + input: + bytes: [ 0x96, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x3" + - + input: + bytes: [ 0x37, 0x0f, 0x04, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x4, #0x4" + - + input: + bytes: [ 0x4b, 0x0f, 0x71, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftouz d4, d15" + - + input: + bytes: [ 0x6d, 0xff, 0x01, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x9fe" + - + input: + bytes: [ 0xc2, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d2, #0x1" + - + input: + bytes: [ 0x37, 0x01, 0x10, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d1, d1, d0, #0, #0x10" + - + input: + bytes: [ 0x53, 0x4a, 0x20, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d2, d10, #0x4" + - + input: + bytes: [ 0xe2, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d0, d1" + - + input: + bytes: [ 0x7f, 0x20, 0x04, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d0, d2, #0x8" + - + input: + bytes: [ 0x80, 0xd0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d0, a13" + - + input: + bytes: [ 0x37, 0x09, 0x68, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d9, d9, #0, #0x8" + - + input: + bytes: [ 0x02, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d15" + - + input: + bytes: [ 0x6f, 0x20, 0xf8, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d0, #0x2, #-0x10" + - + input: + bytes: [ 0x6d, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x114" + - + input: + bytes: [ 0x3c, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x2e" + - + input: + bytes: [ 0x3f, 0xf0, 0x05, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, d15, #0xa" + - + input: + bytes: [ 0x3b, 0x00, 0x10, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x100" + - + input: + bytes: [ 0xda, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0xc" + - + input: + bytes: [ 0x6d, 0x00, 0x4b, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x96" + - + input: + bytes: [ 0x8b, 0xf0, 0x2f, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min.u d0, d0, #0xff" + - + input: + bytes: [ 0xbb, 0x00, 0x68, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d15, #0x9680" + - + input: + bytes: [ 0x3b, 0xb0, 0x7f, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x7fb" + - + input: + bytes: [ 0xfe, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x28" + - + input: + bytes: [ 0x6d, 0xff, 0x45, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x776" + - + input: + bytes: [ 0xbb, 0xd0, 0xcc, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d0, #0xcccd" + - + input: + bytes: [ 0x6d, 0x00, 0x5d, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xba" + - + input: + bytes: [ 0x82, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, #0x1" + - + input: + bytes: [ 0x37, 0x0f, 0x01, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x1e, #0x1" + - + input: + bytes: [ 0xbf, 0x30, 0xe1, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, #0x3, #-0x3e" + - + input: + bytes: [ 0x4b, 0xbf, 0x41, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d15, d15, d11" + - + input: + bytes: [ 0xbf, 0x20, 0xef, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, #0x2, #-0x22" + - + input: + bytes: [ 0x3c, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x34" + - + input: + bytes: [ 0x53, 0x69, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d9, #0x6" + - + input: + bytes: [ 0x01, 0xcd, 0x00, 0xc6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a12, a12, d13, #0" + - + input: + bytes: [ 0x6d, 0x00, 0x1a, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1234" + - + input: + bytes: [ 0x09, 0xc0, 0xca, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a12]#0x8a" + - + input: + bytes: [ 0x7f, 0xf9, 0x0f, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d9, d15, #0x1e" + - + input: + bytes: [ 0x6d, 0xff, 0x62, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x93c" + - + input: + bytes: [ 0xb7, 0x1f, 0x81, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d1, d15, #0x1, #0x17, #0x1" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0" + - + input: + bytes: [ 0xbf, 0xc9, 0x06, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d9, #0xc, #0xc" + - + input: + bytes: [ 0xda, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x2" + - + input: + bytes: [ 0x40, 0x5f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a15, a5" + - + input: + bytes: [ 0x91, 0x20, 0x00, 0x5f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a5, #0xf002" + - + input: + bytes: [ 0x37, 0x0f, 0x61, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x4, #0x1" + - + input: + bytes: [ 0x91, 0x00, 0x0c, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0xa0c0" + - + input: + bytes: [ 0x53, 0xc8, 0x21, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d8, #0x1c" + - + input: + bytes: [ 0x37, 0x0f, 0xe1, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x7, #0x1" + - + input: + bytes: [ 0xda, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0xf" + - + input: + bytes: [ 0x6e, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x8" + - + input: + bytes: [ 0x0f, 0xf1, 0x00, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d1, d1, d15" + - + input: + bytes: [ 0x6d, 0xff, 0x7b, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x70a" + - + input: + bytes: [ 0x9b, 0xb0, 0xbf, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d0, d0, #0x4bfb" + - + input: + bytes: [ 0x09, 0xff, 0xca, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d15, [a15]#0x8a" + - + input: + bytes: [ 0xfc, 0x5e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a5, #-0x4" + - + input: + bytes: [ 0xda, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x3" + - + input: + bytes: [ 0x20, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.a sp, #0x28" + - + input: + bytes: [ 0x82, 0x16 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d6, #0x1" + - + input: + bytes: [ 0xd9, 0xff, 0x20, 0xe0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x3a0" + - + input: + bytes: [ 0xee, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x8" + - + input: + bytes: [ 0x4b, 0xf0, 0x11, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.u e2, d0, d15" + - + input: + bytes: [ 0x6d, 0x00, 0xf9, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xff2" + - + input: + bytes: [ 0x16, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0x3" + - + input: + bytes: [ 0x4b, 0xf2, 0x51, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d15, d2, d15" + - + input: + bytes: [ 0x6d, 0xff, 0xca, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x66c" + - + input: + bytes: [ 0x82, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x3" + - + input: + bytes: [ 0x82, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #-0x1" + - + input: + bytes: [ 0x8f, 0x3c, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d12, #0x3" + - + input: + bytes: [ 0x3e, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d1, #0x16" + - + input: + bytes: [ 0x32, 0x5f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsub d15" + - + input: + bytes: [ 0x82, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, #-0x1" + - + input: + bytes: [ 0x40, 0xd2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a2, a13" + - + input: + bytes: [ 0xd9, 0xff, 0x80, 0xc5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x5b00" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a1, #0" + - + input: + bytes: [ 0x3e, 0x47 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d4, #0xe" + - + input: + bytes: [ 0xdf, 0x10, 0x2b, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d0, #0x1, #0x56" + - + input: + bytes: [ 0xde, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x2, #0x30" + - + input: + bytes: [ 0x37, 0x0f, 0x68, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d4, d15, #0, #0x8" + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d15, d15, #0x3f" + - + input: + bytes: [ 0x06, 0x3f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, #0x3" + - + input: + bytes: [ 0x82, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x1" + - + input: + bytes: [ 0x3b, 0x90, 0xd0, 0x33 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d3, #0x3d09" + - + input: + bytes: [ 0x02, 0x94 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d9" + - + input: + bytes: [ 0x6d, 0xff, 0x9b, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x6ca" + - + input: + bytes: [ 0x53, 0xc2, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d2, #0xc" + - + input: + bytes: [ 0x7b, 0xc0, 0xff, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d0, #0xfffc" + - + input: + bytes: [ 0x6f, 0x1f, 0x12, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x1, #0x24" + - + input: + bytes: [ 0xd9, 0xff, 0x3c, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x17c" + - + input: + bytes: [ 0xd9, 0xff, 0x78, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x538" + - + input: + bytes: [ 0x40, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a4, a15" + - + input: + bytes: [ 0x4e, 0x33 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jgtz d3, #0x6" + - + input: + bytes: [ 0xdf, 0x1f, 0x29, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x52" + - + input: + bytes: [ 0xb7, 0x0f, 0x81, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0x3, #0x1" + - + input: + bytes: [ 0x3e, 0x46 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d4, #0xc" + - + input: + bytes: [ 0x37, 0x01, 0x81, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d1, d0, #0x3, #0x1" + - + input: + bytes: [ 0xc2, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d4, #-0x1" + - + input: + bytes: [ 0x91, 0x30, 0x00, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0xf003" + - + input: + bytes: [ 0x3f, 0x02, 0x08, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d2, d0, #0x10" + - + input: + bytes: [ 0x53, 0x80, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d0, #0x8" + - + input: + bytes: [ 0x6d, 0xff, 0x53, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x75a" + - + input: + bytes: [ 0xd9, 0xff, 0xc4, 0xc2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x2f04" + - + input: + bytes: [ 0x96, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x8" + - + input: + bytes: [ 0x37, 0x0f, 0x62, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x4, #0x2" + - + input: + bytes: [ 0x10, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a4, a15, d15, #0" + - + input: + bytes: [ 0x4b, 0xf2, 0x51, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d2, d2, d15" + - + input: + bytes: [ 0xda, 0x96 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x96" + - + input: + bytes: [ 0x5e, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x2, #0x6" + - + input: + bytes: [ 0x82, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0" + - + input: + bytes: [ 0x16, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0xf" + - + input: + bytes: [ 0xd9, 0x22, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0" + - + input: + bytes: [ 0x3e, 0x66 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d6, #0xc" + - + input: + bytes: [ 0x9b, 0xe2, 0xcb, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d2, d2, #0x4cbe" + - + input: + bytes: [ 0x4e, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jgtz d0, #0x6" + - + input: + bytes: [ 0x1d, 0xff, 0x77, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x112" + - + input: + bytes: [ 0xbf, 0x21, 0xcd, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d1, #0x2, #-0x66" + - + input: + bytes: [ 0x3b, 0xf0, 0x00, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d3, #0xf" + - + input: + bytes: [ 0x16, 0x5f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0x5f" + - + input: + bytes: [ 0x09, 0xff, 0xc6, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d15, [a15]#0x6" + - + input: + bytes: [ 0x8b, 0xf2, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d2, #0xf" + - + input: + bytes: [ 0x6d, 0xff, 0xdf, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xa42" + - + input: + bytes: [ 0xf6, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d0, #0xc" + - + input: + bytes: [ 0x02, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d12, d0" + - + input: + bytes: [ 0x91, 0x80, 0x88, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0xf888" + - + input: + bytes: [ 0xd9, 0xff, 0x24, 0x96 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x6264" + - + input: + bytes: [ 0x37, 0x0f, 0x82, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0xd, #0x2" + - + input: + bytes: [ 0x6d, 0xff, 0xae, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xea4" + - + input: + bytes: [ 0x4b, 0xf0, 0x41, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d15, d0, d15" + - + input: + bytes: [ 0x82, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x2" + - + input: + bytes: [ 0x06, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d4, #0x2" + - + input: + bytes: [ 0xff, 0x8f, 0x1a, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d15, #0x8, #0x34" + - + input: + bytes: [ 0x6d, 0xff, 0x01, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x7fe" + - + input: + bytes: [ 0x8f, 0x3c, 0x00, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d12, #0x3" + - + input: + bytes: [ 0x82, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d6, #0" + - + input: + bytes: [ 0x02, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, d9" + - + input: + bytes: [ 0x4b, 0x0f, 0x71, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftouz d0, d15" + - + input: + bytes: [ 0x37, 0x0f, 0x62, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0xc, #0x2" + - + input: + bytes: [ 0x49, 0xcf, 0x28, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a12]#0x28" + - + input: + bytes: [ 0x01, 0x28, 0x00, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a2, d8, #0" + - + input: + bytes: [ 0x06, 0xaf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, #-0x6" + - + input: + bytes: [ 0x86, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d4, #0x2" + - + input: + bytes: [ 0xb7, 0x3f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x3, #0, #0x8" + - + input: + bytes: [ 0x9b, 0xb1, 0xa5, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d1, d1, #0x4a5b" + - + input: + bytes: [ 0x6d, 0xff, 0x75, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x716" + - + input: + bytes: [ 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x0" + - + input: + bytes: [ 0x86, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d1, #0x2" + - + input: + bytes: [ 0xbe, 0x60 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d6, #0x20" + - + input: + bytes: [ 0x6d, 0xff, 0xc5, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x76" + - + input: + bytes: [ 0xdf, 0x10, 0xee, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d0, #0x1, #-0x24" + - + input: + bytes: [ 0xfc, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a2, #-0xe" + - + input: + bytes: [ 0xa6, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d0, d15" + - + input: + bytes: [ 0x8f, 0x2a, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, d10, #0x2" + - + input: + bytes: [ 0xda, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x20" + - + input: + bytes: [ 0x26, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d3" + - + input: + bytes: [ 0xc6, 0x3f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d15, d3" + - + input: + bytes: [ 0x37, 0xf3, 0x08, 0x38 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d3, d3, d15, #0x10, #0x8" + - + input: + bytes: [ 0x4b, 0x08, 0x61, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "utof d0, d8" + - + input: + bytes: [ 0x37, 0x0f, 0xe2, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x1, #0x2" + - + input: + bytes: [ 0x0f, 0xf3, 0x00, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d3, d3, d15" + - + input: + bytes: [ 0x53, 0xcf, 0x20, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d1, d15, #0xc" + - + input: + bytes: [ 0x7b, 0xa0, 0x47, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d0, #0x447a" + - + input: + bytes: [ 0x5f, 0x2f, 0xf4, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d2, #-0x18" + - + input: + bytes: [ 0x4b, 0xf0, 0x11, 0x42 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.u e4, d0, d15" + - + input: + bytes: [ 0xb7, 0x2f, 0x02, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x2, #0xa, #0x2" + - + input: + bytes: [ 0x6e, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x6" + - + input: + bytes: [ 0x5f, 0x6f, 0x23, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d6, #0x46" + - + input: + bytes: [ 0x3f, 0x10, 0x97, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, d1, #-0xd2" + - + input: + bytes: [ 0x37, 0x0f, 0xe7, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x1, #0x7" + - + input: + bytes: [ 0x37, 0xf0, 0x03, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0x18, #0x3" + - + input: + bytes: [ 0xa6, 0x5f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d5" + - + input: + bytes: [ 0x91, 0x10, 0x88, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0xf881" + - + input: + bytes: [ 0xda, 0x15 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x15" + - + input: + bytes: [ 0x53, 0x20, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d0, #0x2" + - + input: + bytes: [ 0x6d, 0xff, 0x43, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x57a" + - + input: + bytes: [ 0x3c, 0xd9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x4e" + - + input: + bytes: [ 0xb7, 0x5f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x5, #0, #0x8" + - + input: + bytes: [ 0x8f, 0x28, 0x00, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d8, #0x2" + - + input: + bytes: [ 0x6d, 0xff, 0x4b, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x96a" + - + input: + bytes: [ 0xbb, 0x00, 0x68, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d1, #0x9680" + - + input: + bytes: [ 0x91, 0x10, 0x00, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0x4001" + - + input: + bytes: [ 0xfc, 0x2e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a2, #-0x4" + - + input: + bytes: [ 0xfc, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a2, #-0x2" + - + input: + bytes: [ 0xd9, 0xaa, 0x40, 0x85 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea sp, [sp]#0x5600" + - + input: + bytes: [ 0x6d, 0xff, 0x32, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x19c" + - + input: + bytes: [ 0x91, 0x10, 0x00, 0xa1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a sp, #0x1001" + - + input: + bytes: [ 0x02, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, d15" + - + input: + bytes: [ 0xe2, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d0, d15" + - + input: + bytes: [ 0x82, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d5, #0" + - + input: + bytes: [ 0x7e, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x1a" + - + input: + bytes: [ 0x37, 0xf0, 0x01, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0, #0x1" + - + input: + bytes: [ 0x37, 0x0f, 0x81, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x17, #0x1" + - + input: + bytes: [ 0xdf, 0x1f, 0xfb, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0x1, #-0xa" + - + input: + bytes: [ 0x15, 0xd0, 0xc0, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lducx #0xd0003fc0" + - + input: + bytes: [ 0x6d, 0xff, 0xb8, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1a90" + - + input: + bytes: [ 0xdf, 0x1f, 0x54, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0xa8" + - + input: + bytes: [ 0x7e, 0x93 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d9, #0x6" + - + input: + bytes: [ 0x37, 0x0f, 0x65, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x4, #0x5" + - + input: + bytes: [ 0x6d, 0xff, 0x68, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x930" + - + input: + bytes: [ 0x91, 0x50, 0x02, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0xf025" + - + input: + bytes: [ 0x3c, 0x16 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x2c" + - + input: + bytes: [ 0x6f, 0x10, 0xf2, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d0, #0x1, #-0x1c" + - + input: + bytes: [ 0xdf, 0x10, 0xea, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d0, #0x1, #-0x2c" + - + input: + bytes: [ 0xdf, 0x10, 0xf6, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d0, #0x1, #-0x14" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0x7000" + - + input: + bytes: [ 0x6d, 0xff, 0x83, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x6fa" + - + input: + bytes: [ 0xdf, 0x0c, 0x86, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d12, #0, #-0xf4" + - + input: + bytes: [ 0x3c, 0xc4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x78" + - + input: + bytes: [ 0xa2, 0x8f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d15, d8" + - + input: + bytes: [ 0x02, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, d15" + - + input: + bytes: [ 0xd9, 0xff, 0xa4, 0x72 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x29e4" + - + input: + bytes: [ 0xd9, 0x22, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x7c00" + - + input: + bytes: [ 0x82, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0" + - + input: + bytes: [ 0x37, 0x00, 0x68, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d4, d0, #0, #0x8" + - + input: + bytes: [ 0x6d, 0xff, 0x5b, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x74a" + - + input: + bytes: [ 0x37, 0x00, 0xe7, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0x1, #0x7" + - + input: + bytes: [ 0xdf, 0x12, 0x03, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d2, #0x1, #0x6" + - + input: + bytes: [ 0x91, 0x10, 0x00, 0xa3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a sp, #0x3001" + - + input: + bytes: [ 0xc2, 0x31 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d1, #0x3" + - + input: + bytes: [ 0x6d, 0xff, 0x2f, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xfa2" + - + input: + bytes: [ 0x37, 0xf1, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d1, d15, #0, #0x8" + - + input: + bytes: [ 0x3b, 0x00, 0x98, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x980" + - + input: + bytes: [ 0x82, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d9, #0" + - + input: + bytes: [ 0xbe, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d1, #0x20" + - + input: + bytes: [ 0xda, 0x1d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x1d" + - + input: + bytes: [ 0x3f, 0x10, 0xee, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, d1, #-0x24" + - + input: + bytes: [ 0x82, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #0x1" + - + input: + bytes: [ 0x8f, 0x3f, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d15, #0x3" + - + input: + bytes: [ 0x40, 0xe4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a4, a14" + - + input: + bytes: [ 0xc5, 0x06, 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a6, #0x14" + - + input: + bytes: [ 0x96, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x80" + - + input: + bytes: [ 0x91, 0x10, 0x00, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0x1001" + - + input: + bytes: [ 0x26, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d0" + - + input: + bytes: [ 0x0f, 0x31, 0x10, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d1, d1, d3" + - + input: + bytes: [ 0x91, 0x30, 0x00, 0x3f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a3, #0xf003" + - + input: + bytes: [ 0xd9, 0xff, 0x14, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x3094" + - + input: + bytes: [ 0x6d, 0xe8, 0x80, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2fdd00" + - + input: + bytes: [ 0x6e, 0x1d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x3a" + - + input: + bytes: [ 0x7f, 0xf9, 0x02, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d9, d15, #0x4" + - + input: + bytes: [ 0xd9, 0xff, 0xe8, 0xc2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x2f28" + - + input: + bytes: [ 0x37, 0x5f, 0x04, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d5, #0x8, #0x4" + - + input: + bytes: [ 0x4b, 0xf2, 0x41, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d15, d2, d15" + - + input: + bytes: [ 0xd9, 0x22, 0x28, 0xa6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x62a8" + - + input: + bytes: [ 0xc2, 0x81 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d1, #-0x8" + - + input: + bytes: [ 0xbb, 0x00, 0xc2, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d15, #0xbc20" + - + input: + bytes: [ 0x37, 0x1f, 0x02, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d1, #0, #0x2" + - + input: + bytes: [ 0x0f, 0xf1, 0x10, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d1, d1, d15" + - + input: + bytes: [ 0x6d, 0x00, 0xf0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x9e0" + - + input: + bytes: [ 0x0f, 0x3f, 0x00, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d15, d3" + - + input: + bytes: [ 0x02, 0xd4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d13" + - + input: + bytes: [ 0x40, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a15, a4" + - + input: + bytes: [ 0x9b, 0x1f, 0x8d, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d15, d15, #0x38d1" + - + input: + bytes: [ 0x7b, 0x00, 0xf0, 0x13 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d1, #0x3f00" + - + input: + bytes: [ 0x7b, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d1, #0x4000" + - + input: + bytes: [ 0x6d, 0xff, 0xee, 0xe8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2e24" + - + input: + bytes: [ 0x06, 0x62 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d2, #0x6" + - + input: + bytes: [ 0x4b, 0xf2, 0x51, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d10, d2, d15" + - + input: + bytes: [ 0x49, 0xf2, 0x1c, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a15]#0x1c" + - + input: + bytes: [ 0x8f, 0x24, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, d4, #0x2" + - + input: + bytes: [ 0x40, 0xd4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a4, a13" + - + input: + bytes: [ 0x10, 0xd2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a13, d15, #0" + - + input: + bytes: [ 0x6d, 0x00, 0x6d, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x6da" + - + input: + bytes: [ 0xb7, 0x1f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x1, #0, #0x8" + - + input: + bytes: [ 0xd9, 0x22, 0xc0, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#-0x4400" + - + input: + bytes: [ 0x9a, 0x81 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d1, #-0x8" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x8000" + - + input: + bytes: [ 0x37, 0x0f, 0x83, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x3, #0x3" + - + input: + bytes: [ 0x7e, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0xa" + - + input: + bytes: [ 0x6d, 0xa0, 0xf4, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x4023e8" + - + input: + bytes: [ 0x49, 0xff, 0x0c, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0xc" + - + input: + bytes: [ 0xb7, 0x6f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x6, #0, #0x8" + - + input: + bytes: [ 0x10, 0xe4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a4, a14, d15, #0" + - + input: + bytes: [ 0x7f, 0xf0, 0x19, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d0, d15, #0x32" + - + input: + bytes: [ 0x7e, 0x91 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d9, #0x2" + - + input: + bytes: [ 0x0f, 0x0f, 0x00, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d15, d0" + - + input: + bytes: [ 0x6e, 0xef ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #-0x22" + - + input: + bytes: [ 0x3c, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xa" + - + input: + bytes: [ 0x6d, 0x00, 0x25, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1a4a" + - + input: + bytes: [ 0x42, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d1, d0" + - + input: + bytes: [ 0xae, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0x1, #0xe" + - + input: + bytes: [ 0x91, 0x40, 0x00, 0x27 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0x7004" + - + input: + bytes: [ 0x3b, 0x00, 0x40, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x400" + - + input: + bytes: [ 0x09, 0xa0, 0xc4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d0, [sp]#0x4" + - + input: + bytes: [ 0x6f, 0x0f, 0xfc, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #-0x8" + - + input: + bytes: [ 0x02, 0x82 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, d8" + - + input: + bytes: [ 0x37, 0x0f, 0x68, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0, #0x8" + - + input: + bytes: [ 0x1d, 0x00, 0x02, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x4" + - + input: + bytes: [ 0xa2, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d0, d1" + - + input: + bytes: [ 0x37, 0xf0, 0x01, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0x6, #0x1" + - + input: + bytes: [ 0x91, 0x20, 0x00, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a3, #0x2" + - + input: + bytes: [ 0x6d, 0x00, 0xd8, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x19b0" + - + input: + bytes: [ 0x6d, 0xd0, 0x80, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x5fdd00" + - + input: + bytes: [ 0xae, 0x75 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0x7, #0xa" + - + input: + bytes: [ 0x91, 0x50, 0x02, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0xf025" + - + input: + bytes: [ 0x3c, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x4" + - + input: + bytes: [ 0xda, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x14" + - + input: + bytes: [ 0x82, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, #0" + - + input: + bytes: [ 0x82, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d7, #0" + - + input: + bytes: [ 0xbc, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.a a15, #0x2" + - + input: + bytes: [ 0x6d, 0xff, 0xe0, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x840" + - + input: + bytes: [ 0x37, 0x00, 0x70, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0x10, #0x10" + - + input: + bytes: [ 0x82, 0x15 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d5, #0x1" + - + input: + bytes: [ 0xd9, 0xff, 0xec, 0xe2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x2fac" + - + input: + bytes: [ 0xbe, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d4, #0x20" + - + input: + bytes: [ 0x3c, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x36" + - + input: + bytes: [ 0x37, 0xf0, 0x02, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0x14, #0x2" + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d4, d15, #0x3f" + - + input: + bytes: [ 0x3e, 0x16 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d1, #0xc" + - + input: + bytes: [ 0x6e, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x12" + - + input: + bytes: [ 0x3f, 0xf2, 0xf3, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d2, d15, #-0x1a" + - + input: + bytes: [ 0x6d, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x8" + - + input: + bytes: [ 0xa6, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d0, d1" + - + input: + bytes: [ 0xda, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x40" + - + input: + bytes: [ 0x6e, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x34" + - + input: + bytes: [ 0x91, 0x00, 0x0f, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0xa0f0" + - + input: + bytes: [ 0x6d, 0xff, 0xc5, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x276" + - + input: + bytes: [ 0x9b, 0xc0, 0xfc, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d0, d0, #0x3fcc" + - + input: + bytes: [ 0x37, 0x0f, 0x02, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x6, #0x2" + - + input: + bytes: [ 0xdf, 0x10, 0x0a, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d0, #0x1, #0x14" + - + input: + bytes: [ 0x8f, 0x00, 0x21, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d0, d0, #0x10" + - + input: + bytes: [ 0xfd, 0xf0, 0xed, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a15, #-0x26" + - + input: + bytes: [ 0x7b, 0x00, 0x00, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d15, #0x4000" + - + input: + bytes: [ 0x37, 0x00, 0x62, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d0, #0x4, #0x2" + - + input: + bytes: [ 0x3f, 0x0f, 0x04, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d15, d0, #0x8" + - + input: + bytes: [ 0x3c, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x22" + - + input: + bytes: [ 0x01, 0xdd, 0x00, 0xd6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a13, a13, d13, #0" + - + input: + bytes: [ 0x82, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x1" + - + input: + bytes: [ 0xee, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x4" + - + input: + bytes: [ 0x82, 0x27 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d7, #0x2" + - + input: + bytes: [ 0xfe, 0xdb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d13, #0x36" + - + input: + bytes: [ 0x37, 0x04, 0x68, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d4, #0, #0x8" + - + input: + bytes: [ 0x3e, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x8" + - + input: + bytes: [ 0x06, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d4, #-0x1" + - + input: + bytes: [ 0x37, 0xf0, 0x01, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0, #0x1" + - + input: + bytes: [ 0xbf, 0xc9, 0x07, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d9, #0xc, #0xe" + - + input: + bytes: [ 0x3c, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x1c" + - + input: + bytes: [ 0x7b, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d0, #0x4200" + - + input: + bytes: [ 0x30, 0x43 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a3, a4" + - + input: + bytes: [ 0x91, 0x00, 0x09, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0xa090" + - + input: + bytes: [ 0x91, 0x10, 0x00, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x3001" + - + input: + bytes: [ 0x3c, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x40" + - + input: + bytes: [ 0x6d, 0xe8, 0xe1, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2fe23e" + - + input: + bytes: [ 0x6d, 0xff, 0xaa, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xcac" + - + input: + bytes: [ 0xb7, 0x7f, 0x03, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x7, #0x1c, #0x3" + - + input: + bytes: [ 0xb7, 0x00, 0x81, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, #0x3, #0x1" + - + input: + bytes: [ 0x0f, 0x10, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d0, d0, d1" + - + input: + bytes: [ 0xa2, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d15, d0" + - + input: + bytes: [ 0xc6, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d1, d15" + - + input: + bytes: [ 0x8f, 0x3f, 0x00, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d1, d15, #0x3" + - + input: + bytes: [ 0x49, 0xcf, 0x30, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a12]#0x30" + - + input: + bytes: [ 0x26, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d1" + - + input: + bytes: [ 0x5e, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x16" + - + input: + bytes: [ 0xc6, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d15, d2" + - + input: + bytes: [ 0x53, 0x01, 0x21, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d1, #0x10" + - + input: + bytes: [ 0x91, 0x40, 0x00, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x6004" + - + input: + bytes: [ 0xbf, 0xc9, 0x05, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d9, #0xc, #0xa" + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0xa1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d10, d15, #0x3f" + - + input: + bytes: [ 0x91, 0x40, 0x00, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0x6004" + - + input: + bytes: [ 0x37, 0xf3, 0x08, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d3, d3, d15, #0, #0x8" + - + input: + bytes: [ 0x4b, 0xf0, 0x51, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d2, d0, d15" + - + input: + bytes: [ 0x82, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d11, #0" + - + input: + bytes: [ 0x42, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d15" + - + input: + bytes: [ 0xd9, 0xff, 0x30, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x3030" + - + input: + bytes: [ 0x6d, 0x00, 0xbe, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x57c" + - + input: + bytes: [ 0xb7, 0x0f, 0x1c, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0, #0x1c" + - + input: + bytes: [ 0xa6, 0x64 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d4, d6" + - + input: + bytes: [ 0x37, 0x4f, 0x9f, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d4, #0x1, #0x1f" + - + input: + bytes: [ 0x6d, 0xe8, 0xf4, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2fdc18" + - + input: + bytes: [ 0x4b, 0x30, 0x11, 0x42 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.u e4, d0, d3" + - + input: + bytes: [ 0xd9, 0x44, 0x3c, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x17c" + - + input: + bytes: [ 0xc2, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, #-0x1" + - + input: + bytes: [ 0x26, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d1, d15" + - + input: + bytes: [ 0x91, 0x00, 0x0f, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x80f0" + - + input: + bytes: [ 0x91, 0x30, 0x00, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0xf003" + - + input: + bytes: [ 0x3b, 0x00, 0x02, 0x60 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d6, #0x20" + - + input: + bytes: [ 0x3f, 0xf9, 0x65, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d9, d15, #-0x136" + - + input: + bytes: [ 0x3e, 0x58 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d5, #0x10" + - + input: + bytes: [ 0x10, 0xaf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, sp, d15, #0" + - + input: + bytes: [ 0xdf, 0x0c, 0xd3, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d12, #0, #-0x5a" + - + input: + bytes: [ 0x53, 0x00, 0x21, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d0, #0x10" + - + input: + bytes: [ 0x3e, 0x4b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d4, #0x16" + - + input: + bytes: [ 0x3f, 0xf0, 0xfd, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, d15, #-0x6" + - + input: + bytes: [ 0xdf, 0x1f, 0xfe, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0x1, #-0x4" + - + input: + bytes: [ 0x6d, 0xff, 0x6f, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x722" + - + input: + bytes: [ 0xfc, 0x4e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a4, #-0x4" + - + input: + bytes: [ 0x8b, 0x5f, 0x20, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min.u d15, d15, #0x5" + - + input: + bytes: [ 0x01, 0xf0, 0x00, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, a15, d0, #0" + - + input: + bytes: [ 0x8f, 0x3f, 0x00, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d3, d15, #0x3" + - + input: + bytes: [ 0x3c, 0x34 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x68" + - + input: + bytes: [ 0x90, 0xdd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a13, a13, d15, #0x2" + - + input: + bytes: [ 0x6d, 0xff, 0xa6, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xb4" + - + input: + bytes: [ 0x37, 0x4f, 0x04, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d4, #0x10, #0x4" + - + input: + bytes: [ 0x37, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0, #0x8" + - + input: + bytes: [ 0x10, 0xcc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a12, a12, d15, #0" + - + input: + bytes: [ 0xee, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0xc" + - + input: + bytes: [ 0x6d, 0xff, 0x00, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xa00" + - + input: + bytes: [ 0x10, 0xcf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, a12, d15, #0" + - + input: + bytes: [ 0x7f, 0x0f, 0x07, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d15, d0, #0xe" + - + input: + bytes: [ 0xd9, 0xff, 0x08, 0xa6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x6288" + - + input: + bytes: [ 0xbe, 0x65 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d6, #0x2a" + - + input: + bytes: [ 0x3e, 0x5a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d5, #0x14" + - + input: + bytes: [ 0x26, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d2" + - + input: + bytes: [ 0x92, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d15, #0x1" + - + input: + bytes: [ 0x26, 0x3f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d3" + - + input: + bytes: [ 0x6d, 0xff, 0x8b, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x8ea" + - + input: + bytes: [ 0x6d, 0x00, 0xf1, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1e2" + - + input: + bytes: [ 0xdf, 0x04, 0x7c, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d4, #0, #-0x108" + - + input: + bytes: [ 0x8f, 0x4f, 0x1f, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d1, d15, #-0xc" + - + input: + bytes: [ 0xd9, 0x88, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a8, [a8]#0" + - + input: + bytes: [ 0xd7, 0x10, 0x21, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "imask e0, #0x1, d15, #0x1" + - + input: + bytes: [ 0x8f, 0x23, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, d3, #0x2" + - + input: + bytes: [ 0x6b, 0x0f, 0x61, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd.f d4, d1, d15, d0" + - + input: + bytes: [ 0xc2, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, #0x1" + - + input: + bytes: [ 0x6d, 0xff, 0xb6, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xa94" + - + input: + bytes: [ 0xc5, 0x02, 0x3f, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, #0x7f" + - + input: + bytes: [ 0x80, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d0, a2" + - + input: + bytes: [ 0xbe, 0x9c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d9, #0x38" + - + input: + bytes: [ 0x6e, 0xe8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #-0x30" + - + input: + bytes: [ 0x91, 0x10, 0x00, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x4001" + - + input: + bytes: [ 0xe2, 0x9f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d9" + - + input: + bytes: [ 0x3c, 0x1e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x3c" + - + input: + bytes: [ 0xb7, 0x04, 0x08, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d4, #0, #0x18, #0x8" + - + input: + bytes: [ 0x6e, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0xe" + - + input: + bytes: [ 0xbb, 0x00, 0x52, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d0, #0xc520" + - + input: + bytes: [ 0xa6, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d0, d2" + - + input: + bytes: [ 0x3c, 0x1d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x3a" + - + input: + bytes: [ 0x6d, 0x00, 0x2d, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xe5a" + - + input: + bytes: [ 0x8f, 0x0f, 0x1f, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d0, d15, #-0x10" + - + input: + bytes: [ 0x8b, 0x09, 0x01, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d9, #0x10" + - + input: + bytes: [ 0xc2, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d12, #-0x1" + - + input: + bytes: [ 0x3b, 0xf0, 0x49, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x249f" + - + input: + bytes: [ 0x4b, 0x1f, 0x51, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d15, d15, d1" + - + input: + bytes: [ 0x60, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a2, d2" + - + input: + bytes: [ 0xde, 0x25 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x2, #0x2a" + - + input: + bytes: [ 0x5e, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x2, #0xc" + - + input: + bytes: [ 0x86, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d0, #0x2" + - + input: + bytes: [ 0x82, 0x18 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, #0x1" + - + input: + bytes: [ 0x37, 0x5f, 0x02, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d5, #0, #0x2" + - + input: + bytes: [ 0xbf, 0x89, 0x05, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d9, #0x8, #0xa" + - + input: + bytes: [ 0x5e, 0x16 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0xc" + - + input: + bytes: [ 0x8f, 0xf9, 0x01, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d9, #0x1f" + - + input: + bytes: [ 0xbb, 0x00, 0xc2, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d1, #0xbc20" + - + input: + bytes: [ 0x02, 0xc4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d12" + - + input: + bytes: [ 0x3c, 0x25 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x4a" + - + input: + bytes: [ 0xc2, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, #-0x1" + - + input: + bytes: [ 0x15, 0xd0, 0xc0, 0xe3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "stlcx #0xd0003f80" + - + input: + bytes: [ 0xd9, 0xff, 0x38, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x23f8" + - + input: + bytes: [ 0x2e, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x1, #0x16" + - + input: + bytes: [ 0x3c, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x32" + - + input: + bytes: [ 0xe2, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d0" + - + input: + bytes: [ 0x6d, 0x00, 0x9e, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x73c" + - + input: + bytes: [ 0x37, 0xf0, 0x02, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0xc, #0x2" + - + input: + bytes: [ 0x1e, 0x13 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0x1, #0x6" + - + input: + bytes: [ 0x3c, 0x31 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x62" + - + input: + bytes: [ 0xff, 0xc9, 0x03, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d9, #0xc, #0x6" + - + input: + bytes: [ 0xd9, 0xff, 0x34, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x30b4" + - + input: + bytes: [ 0x37, 0x0f, 0x05, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0, #0x5" + - + input: + bytes: [ 0x91, 0x00, 0x0c, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x80c0" + - + input: + bytes: [ 0x7b, 0x80, 0x2c, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d0, #0x42c8" + - + input: + bytes: [ 0xbb, 0x00, 0x40, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d2, #0xf400" + - + input: + bytes: [ 0xdf, 0x0f, 0xb1, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0, #0x162" + - + input: + bytes: [ 0xf6, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d0, #0x4" + - + input: + bytes: [ 0x6f, 0x7f, 0xec, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x7, #-0x28" + - + input: + bytes: [ 0x3c, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xc" + - + input: + bytes: [ 0x60, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a4, d1" + - + input: + bytes: [ 0x49, 0xff, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0" + - + input: + bytes: [ 0x3c, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x24" + - + input: + bytes: [ 0xd9, 0x44, 0x20, 0x93 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x3260" + - + input: + bytes: [ 0x91, 0x30, 0x00, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0xf003" + - + input: + bytes: [ 0x76, 0x6d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d6, #0x1a" + - + input: + bytes: [ 0x6f, 0x0f, 0xf3, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #-0x1a" + - + input: + bytes: [ 0xfc, 0x6e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a6, #-0x4" + - + input: + bytes: [ 0x6d, 0xff, 0xac, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xa8" + - + input: + bytes: [ 0xef, 0x4f, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x14, #0x8" + - + input: + bytes: [ 0xbb, 0x70, 0x71, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d15, #0xb717" + - + input: + bytes: [ 0x0f, 0xf0, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d0, d0, d15" + - + input: + bytes: [ 0x0f, 0x04, 0x10, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d4, d4, d0" + - + input: + bytes: [ 0x5e, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x8" + - + input: + bytes: [ 0x02, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, d2" + - + input: + bytes: [ 0x37, 0x0f, 0x81, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0xf, #0x1" + - + input: + bytes: [ 0x37, 0xf0, 0x87, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0x9, #0x7" + - + input: + bytes: [ 0xa0, 0x66 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a6, #0x6" + - + input: + bytes: [ 0x37, 0x0f, 0x02, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x4, #0x2" + - + input: + bytes: [ 0x96, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x40" + - + input: + bytes: [ 0xc2, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, #0x1" + - + input: + bytes: [ 0x8b, 0x87, 0x01, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d7, #0x18" + - + input: + bytes: [ 0x91, 0x60, 0x88, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0xf886" + - + input: + bytes: [ 0x49, 0xff, 0x20, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x20" + - + input: + bytes: [ 0x6d, 0x00, 0x0f, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x21e" + - + input: + bytes: [ 0x3e, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x1c" + - + input: + bytes: [ 0x3c, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x46" + - + input: + bytes: [ 0xdf, 0x2f, 0x91, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x2, #-0xde" + - + input: + bytes: [ 0x3c, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x18" + - + input: + bytes: [ 0x10, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a15, d15, #0" + - + input: + bytes: [ 0x37, 0xf0, 0x01, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0x1e, #0x1" + - + input: + bytes: [ 0xda, 0xbc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0xbc" + - + input: + bytes: [ 0x0f, 0x05, 0x10, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d5, d5, d0" + - + input: + bytes: [ 0x91, 0x00, 0x06, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x8060" + - + input: + bytes: [ 0x3c, 0x27 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x4e" + - + input: + bytes: [ 0xda, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0" + - + input: + bytes: [ 0x49, 0xa5, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [sp]#0" + - + input: + bytes: [ 0x96, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x2" + - + input: + bytes: [ 0x37, 0x0f, 0x81, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x5, #0x1" + - + input: + bytes: [ 0x4b, 0x02, 0x71, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftouz d4, d2" + - + input: + bytes: [ 0x3e, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x14" + - + input: + bytes: [ 0xa2, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d12, d15" + - + input: + bytes: [ 0x53, 0xc9, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d0, d9, #0xc" + - + input: + bytes: [ 0xd9, 0x44, 0xe0, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x2ca0" + - + input: + bytes: [ 0x60, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a15, d4" + - + input: + bytes: [ 0x49, 0xa4, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [sp]#0" + - + input: + bytes: [ 0xb7, 0x0f, 0x81, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0x1, #0x1" + - + input: + bytes: [ 0x4b, 0x0f, 0x41, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "itof d15, d15" + - + input: + bytes: [ 0x3e, 0x93 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d9, #0x6" + - + input: + bytes: [ 0xd9, 0xff, 0x0c, 0xb0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x2cc" + - + input: + bytes: [ 0x6d, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x70" + - + input: + bytes: [ 0xe2, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d0, d9" + - + input: + bytes: [ 0x4b, 0x0f, 0x41, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d1, d15, d0" + - + input: + bytes: [ 0xa6, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d2, d1" + - + input: + bytes: [ 0x4b, 0x00, 0x41, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "itof d15, d0" + - + input: + bytes: [ 0x8b, 0x14, 0x1f, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d4, #-0xf" + - + input: + bytes: [ 0x6d, 0x00, 0x9f, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x133e" + - + input: + bytes: [ 0x7e, 0x92 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d9, #0x4" + - + input: + bytes: [ 0x6d, 0xff, 0x63, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x93a" + - + input: + bytes: [ 0x3c, 0x33 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x66" + - + input: + bytes: [ 0x6e, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x1c" + - + input: + bytes: [ 0x1d, 0x00, 0xd4, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x3a8" + - + input: + bytes: [ 0xbb, 0x00, 0xa0, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d1, #0xba00" + - + input: + bytes: [ 0x6e, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #-0x14" + - + input: + bytes: [ 0x77, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "dextr d0, d0, d0, #0x8" + - + input: + bytes: [ 0x6d, 0x00, 0xb4, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xf68" + - + input: + bytes: [ 0x02, 0x8f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, d8" + - + input: + bytes: [ 0x26, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d2, d15" + - + input: + bytes: [ 0x80, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d4, a15" + - + input: + bytes: [ 0x37, 0x04, 0xe8, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d4, #0x17, #0x8" + - + input: + bytes: [ 0x6d, 0xff, 0x1f, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x9c2" + - + input: + bytes: [ 0x3b, 0x00, 0x00, 0x31 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d3, #0x1000" + - + input: + bytes: [ 0x6d, 0x00, 0x26, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1c4c" + - + input: + bytes: [ 0x3e, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x10" + - + input: + bytes: [ 0xd9, 0x22, 0xb8, 0xd2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x2b78" + - + input: + bytes: [ 0x30, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a3, a15" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x27 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0x7000" + - + input: + bytes: [ 0x37, 0x03, 0x68, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d3, #0x10, #0x8" + - + input: + bytes: [ 0x91, 0x00, 0x09, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x8090" + - + input: + bytes: [ 0x4b, 0x00, 0x61, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "utof d15, d0" + - + input: + bytes: [ 0x6e, 0xc9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #-0x6e" + - + input: + bytes: [ 0x9b, 0xef, 0xcb, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d15, d15, #0x4cbe" + - + input: + bytes: [ 0x4b, 0x0f, 0x61, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "utof d15, d15" + - + input: + bytes: [ 0xd9, 0xff, 0xb8, 0x42 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x2938" + - + input: + bytes: [ 0xdf, 0x0c, 0x9b, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d12, #0, #-0xca" + - + input: + bytes: [ 0x7b, 0xd0, 0x38, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d0, #0x138d" + - + input: + bytes: [ 0x53, 0x47, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d0, d7, #0x4" + - + input: + bytes: [ 0x6d, 0x00, 0xd3, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1ba6" + - + input: + bytes: [ 0xbf, 0x10, 0x15, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, #0x1, #0x2a" + - + input: + bytes: [ 0x6d, 0x00, 0x63, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xc6" + - + input: + bytes: [ 0x82, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d10, #0" + - + input: + bytes: [ 0xa6, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d4" + - + input: + bytes: [ 0x53, 0x4a, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d10, #0x4" + - + input: + bytes: [ 0x37, 0xf0, 0x81, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0x3, #0x1" + - + input: + bytes: [ 0x0f, 0x0f, 0xb0, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "clz d15, d15" + - + input: + bytes: [ 0x6d, 0x00, 0xcd, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xf9a" + - + input: + bytes: [ 0x91, 0x00, 0x10, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x8100" + - + input: + bytes: [ 0x26, 0x32 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d2, d3" + - + input: + bytes: [ 0x6d, 0xff, 0x22, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x9bc" + - + input: + bytes: [ 0x6d, 0x00, 0x56, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2ac" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0x8000" + - + input: + bytes: [ 0xbb, 0x00, 0xc2, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d0, #0xbc20" + - + input: + bytes: [ 0x16, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0x7" + - + input: + bytes: [ 0xd9, 0xff, 0x24, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x3e4" + - + input: + bytes: [ 0x53, 0x41, 0x20, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d3, d1, #0x4" + - + input: + bytes: [ 0x0f, 0x2f, 0x00, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d15, d2" + - + input: + bytes: [ 0x3b, 0x00, 0x05, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x50" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x2000" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a8, #0" + - + input: + bytes: [ 0x4e, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jgtz d15, #0x6" + - + input: + bytes: [ 0x06, 0xec ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d12, #-0x2" + - + input: + bytes: [ 0x6d, 0x00, 0xc6, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xf8c" + - + input: + bytes: [ 0x76, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d0, #0x6" + - + input: + bytes: [ 0x37, 0x00, 0x62, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d0, #0x14, #0x2" + - + input: + bytes: [ 0x57, 0x00, 0x62, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d0, d15, #0x2" + - + input: + bytes: [ 0xff, 0xc9, 0x04, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d9, #0xc, #0x8" + - + input: + bytes: [ 0xd9, 0xff, 0x0c, 0x60 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x18c" + - + input: + bytes: [ 0x6e, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x60" + - + input: + bytes: [ 0x80, 0xcf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d15, a12" + - + input: + bytes: [ 0xc2, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d1, #0x1" + - + input: + bytes: [ 0xdf, 0x04, 0x3b, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d4, #0, #0x76" + - + input: + bytes: [ 0xb7, 0x7f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x7, #0, #0x8" + - + input: + bytes: [ 0x37, 0x0f, 0x01, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0xc, #0x1" + - + input: + bytes: [ 0xd9, 0x55, 0x08, 0x60 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#0x188" + - + input: + bytes: [ 0x42, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d1, d15" + - + input: + bytes: [ 0xa2, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d0, d15" + - + input: + bytes: [ 0x6d, 0xff, 0x78, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x910" + - + input: + bytes: [ 0x3b, 0x00, 0xd0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x2d00" + - + input: + bytes: [ 0xd9, 0x11, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a1, [a1]#0" + - + input: + bytes: [ 0x6d, 0x88, 0x80, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x102300" + - + input: + bytes: [ 0xda, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x5" + - + input: + bytes: [ 0x3c, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x1a" + - + input: + bytes: [ 0xe2, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d1" + - + input: + bytes: [ 0x8f, 0x10, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d0, #0x1" + - + input: + bytes: [ 0x15, 0xd0, 0xc0, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "stucx #0xd0003fc0" + - + input: + bytes: [ 0xbf, 0x89, 0x06, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d9, #0x8, #0xc" + - + input: + bytes: [ 0x6f, 0x1f, 0xfc, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x1, #-0x8" + - + input: + bytes: [ 0xd9, 0xff, 0x26, 0xb2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x22e6" + - + input: + bytes: [ 0x91, 0x40, 0x00, 0xa7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a sp, #0x7004" + - + input: + bytes: [ 0xd9, 0x22, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x400" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a0, #0" + - + input: + bytes: [ 0x80, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d1, a4" + - + input: + bytes: [ 0x9b, 0xe0, 0xcb, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d0, d0, #0x4cbe" + - + input: + bytes: [ 0x10, 0xdf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, a13, d15, #0" + - + input: + bytes: [ 0x91, 0xc0, 0x88, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0xf88c" + - + input: + bytes: [ 0x40, 0xbf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a15, a11" + - + input: + bytes: [ 0xc2, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d3, #-0x1" + - + input: + bytes: [ 0x02, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d9, d4" + - + input: + bytes: [ 0x4b, 0xf0, 0x51, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d15, d0, d15" + - + input: + bytes: [ 0xb7, 0x2f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x2, #0, #0x8" + - + input: + bytes: [ 0x37, 0x0f, 0x02, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0, #0x2" + - + input: + bytes: [ 0xa6, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d1, d15" + - + input: + bytes: [ 0x10, 0xef ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, a14, d15, #0" + - + input: + bytes: [ 0x49, 0xf5, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a15]#0" + - + input: + bytes: [ 0x76, 0xdb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d13, #0x16" + - + input: + bytes: [ 0x9b, 0x8f, 0xb9, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d15, d15, #0x4b98" + - + input: + bytes: [ 0x02, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, d2" + - + input: + bytes: [ 0x3c, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x6" + - + input: + bytes: [ 0xd9, 0x55, 0x3c, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#0x17c" + - + input: + bytes: [ 0xc6, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d0, d3" + - + input: + bytes: [ 0x2e, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #0x6" + - + input: + bytes: [ 0xb7, 0x4f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x4, #0, #0x8" + - + input: + bytes: [ 0x91, 0x00, 0x06, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0xa060" + - + input: + bytes: [ 0x53, 0x4a, 0x20, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d1, d10, #0x4" + - + input: + bytes: [ 0x3c, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x1e" + - + input: + bytes: [ 0x8f, 0xf9, 0x03, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d9, #0x3f" + - + input: + bytes: [ 0x4b, 0xaf, 0x41, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d15, d15, d10" + - + input: + bytes: [ 0x82, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x2" + - + input: + bytes: [ 0x0f, 0x10, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d0, d0, d1" + - + input: + bytes: [ 0x37, 0x0f, 0x82, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x5, #0x2" + - + input: + bytes: [ 0x3c, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x14" + - + input: + bytes: [ 0x3c, 0x13 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x26" + - + input: + bytes: [ 0x6d, 0x00, 0xe7, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xfce" + - + input: + bytes: [ 0x3f, 0x40, 0xe3, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, d4, #-0x3a" + - + input: + bytes: [ 0x8f, 0x21, 0x00, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d1, #0x2" + - + input: + bytes: [ 0x6f, 0x0f, 0xfe, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0, #-0x4" + - + input: + bytes: [ 0x37, 0xf0, 0x03, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0, #0x3" + - + input: + bytes: [ 0x4b, 0x0f, 0x71, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftouz d15, d15" + - + input: + bytes: [ 0x91, 0x10, 0x00, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x1001" + - + input: + bytes: [ 0x3c, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x2" + - + input: + bytes: [ 0x06, 0x63 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d3, #0x6" + - + input: + bytes: [ 0xd9, 0x44, 0xb0, 0xd2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x2b70" + - + input: + bytes: [ 0x1d, 0x00, 0x9c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x138" + - + input: + bytes: [ 0x02, 0x84 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d8" + - + input: + bytes: [ 0x89, 0xcf, 0x8a, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a12]#0x8a, d15" + - + input: + bytes: [ 0x6d, 0x00, 0x41, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x282" + - + input: + bytes: [ 0xa6, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d0, d3" + - + input: + bytes: [ 0x3c, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x4" + - + input: + bytes: [ 0x16, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0x1" + - + input: + bytes: [ 0x3e, 0x67 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d6, #0xe" + - + input: + bytes: [ 0x4b, 0xf1, 0x51, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d2, d1, d15" + - + input: + bytes: [ 0xa6, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d0" + - + input: + bytes: [ 0x7f, 0x20, 0x09, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d0, d2, #0x12" + - + input: + bytes: [ 0x53, 0x47, 0x20, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d1, d7, #0x4" + - + input: + bytes: [ 0x4b, 0xf1, 0x51, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d0, d1, d15" + - + input: + bytes: [ 0x8b, 0x60, 0x09, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsub d15, d0, #0x96" + - + input: + bytes: [ 0xdf, 0x1f, 0xfa, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0x1, #-0xc" + - + input: + bytes: [ 0xee, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0x14" + - + input: + bytes: [ 0x82, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d3, #-0x1" + - + input: + bytes: [ 0x53, 0xcf, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d15, #0xc" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x7000" + - + input: + bytes: [ 0x3c, 0x94 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0xd8" + - + input: + bytes: [ 0x40, 0xc4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a4, a12" + - + input: + bytes: [ 0xc2, 0xe0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, #-0x2" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a9, #0" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a5, #0x7000" diff --git a/tests/MC/TriCore/J_Call_Loop.s.yaml b/tests/MC/TriCore/J_Call_Loop.s.yaml new file mode 100644 index 0000000000..5f82468c8a --- /dev/null +++ b/tests/MC/TriCore/J_Call_Loop.s.yaml @@ -0,0 +1,2521 @@ +test_cases: + - + input: + bytes: [ 0x6d, 0xff, 0x9d, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xc6" + - + input: + bytes: [ 0x6d, 0xff, 0x02, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3fc" + - + input: + bytes: [ 0x7f, 0xf8, 0x0b, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d8, d15, #0x16" + - + input: + bytes: [ 0x3c, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x16" + - + input: + bytes: [ 0x6d, 0xff, 0xb3, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x9a" + - + input: + bytes: [ 0xff, 0x88, 0x1f, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d8, #0x8, #0x3e" + - + input: + bytes: [ 0x6d, 0x00, 0x1b, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x36" + - + input: + bytes: [ 0x5e, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0xe" + - + input: + bytes: [ 0x3c, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x10" + - + input: + bytes: [ 0x6d, 0xff, 0xbe, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x84" + - + input: + bytes: [ 0x6d, 0xff, 0x58, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x150" + - + input: + bytes: [ 0x6d, 0xff, 0xbd, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x486" + - + input: + bytes: [ 0x7f, 0xf8, 0x0d, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d8, d15, #0x1a" + - + input: + bytes: [ 0x3c, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x1a" + - + input: + bytes: [ 0x6d, 0xff, 0x6a, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x12c" + - + input: + bytes: [ 0x6d, 0xff, 0x94, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xad8" + - + input: + bytes: [ 0x3c, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x2" + - + input: + bytes: [ 0x6d, 0xff, 0x87, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xaf2" + - + input: + bytes: [ 0xbf, 0x45, 0x0b, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d5, #0x4, #0x16" + - + input: + bytes: [ 0x6f, 0x04, 0x05, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d4, #0, #0xa" + - + input: + bytes: [ 0x3c, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x6" + - + input: + bytes: [ 0x6d, 0xff, 0x9a, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xcc" + - + input: + bytes: [ 0x6d, 0xff, 0x4e, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x164" + - + input: + bytes: [ 0x6d, 0xff, 0x83, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xfa" + - + input: + bytes: [ 0x6d, 0xff, 0x37, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x192" + - + input: + bytes: [ 0x6d, 0xff, 0x32, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xb9c" + - + input: + bytes: [ 0x6d, 0xff, 0xc3, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x7a" + - + input: + bytes: [ 0x6d, 0xff, 0x1e, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xbc4" + - + input: + bytes: [ 0x7f, 0x81, 0x0a, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d1, d8, #0x14" + - + input: + bytes: [ 0x3f, 0x08, 0x08, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d8, d0, #0x10" + - + input: + bytes: [ 0x7f, 0x80, 0x04, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d0, d8, #0x8" + - + input: + bytes: [ 0x3c, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xa" + - + input: + bytes: [ 0x6d, 0xff, 0xa6, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xb4" + - + input: + bytes: [ 0x6d, 0xff, 0x26, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1b4" + - + input: + bytes: [ 0x6d, 0xff, 0xda, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x24c" + - + input: + bytes: [ 0xdf, 0x04, 0x31, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d4, #0, #0x62" + - + input: + bytes: [ 0x76, 0x6b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d6, #0x16" + - + input: + bytes: [ 0x3c, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x18" + - + input: + bytes: [ 0x6d, 0xff, 0xdc, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x248" + - + input: + bytes: [ 0x6d, 0xff, 0x8d, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2e6" + - + input: + bytes: [ 0x3c, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x1c" + - + input: + bytes: [ 0x6e, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x6" + - + input: + bytes: [ 0xbf, 0x81, 0xf3, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d1, #0x8, #-0x1a" + - + input: + bytes: [ 0xdf, 0x10, 0xee, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d0, #0x1, #-0x24" + - + input: + bytes: [ 0x6d, 0xff, 0xa6, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2b4" + - + input: + bytes: [ 0x6d, 0xff, 0x19, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3ce" + - + input: + bytes: [ 0xee, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x10" + - + input: + bytes: [ 0x3c, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x12" + - + input: + bytes: [ 0x6d, 0xff, 0xbc, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x488" + - + input: + bytes: [ 0x6e, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x40" + - + input: + bytes: [ 0x6d, 0xff, 0x22, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3bc" + - + input: + bytes: [ 0xff, 0x8f, 0x1a, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d15, #0x8, #0x34" + - + input: + bytes: [ 0x3c, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x36" + - + input: + bytes: [ 0x6e, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x52" + - + input: + bytes: [ 0x6d, 0xff, 0xcb, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x46a" + - + input: + bytes: [ 0x6d, 0xff, 0x1e, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x5c4" + - + input: + bytes: [ 0xfc, 0x6e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a6, #-0x4" + - + input: + bytes: [ 0x6d, 0xff, 0x5c, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x548" + - + input: + bytes: [ 0x6d, 0xff, 0x2e, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x5a4" + - + input: + bytes: [ 0x5e, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x16" + - + input: + bytes: [ 0x6d, 0xff, 0x06, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3f4" + - + input: + bytes: [ 0x6d, 0xff, 0xfe, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x404" + - + input: + bytes: [ 0x6d, 0xff, 0xf2, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x41c" + - + input: + bytes: [ 0x6d, 0xff, 0xea, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x42c" + - + input: + bytes: [ 0x6d, 0xff, 0xde, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x444" + - + input: + bytes: [ 0x6d, 0xff, 0xd6, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x454" + - + input: + bytes: [ 0x5f, 0x9f, 0x23, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d9, #0x46" + - + input: + bytes: [ 0xdf, 0x1f, 0x5d, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0xba" + - + input: + bytes: [ 0x6e, 0x2d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x5a" + - + input: + bytes: [ 0xfe, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x28" + - + input: + bytes: [ 0x3c, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xe" + - + input: + bytes: [ 0xbe, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x2a" + - + input: + bytes: [ 0x3c, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x4" + - + input: + bytes: [ 0xdf, 0x1f, 0x57, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0xae" + - + input: + bytes: [ 0x7e, 0x93 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d9, #0x6" + - + input: + bytes: [ 0x6d, 0xff, 0x7a, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x90c" + - + input: + bytes: [ 0x3c, 0x36 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x6c" + - + input: + bytes: [ 0x7f, 0x0f, 0x07, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d15, d0, #0xe" + - + input: + bytes: [ 0xbf, 0x21, 0xcb, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d1, #0x2, #-0x6a" + - + input: + bytes: [ 0x6d, 0xff, 0x18, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x9d0" + - + input: + bytes: [ 0x6d, 0xff, 0x85, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xaf6" + - + input: + bytes: [ 0x6d, 0xff, 0xd6, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xe54" + - + input: + bytes: [ 0x6d, 0xff, 0x9c, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xac8" + - + input: + bytes: [ 0x6d, 0xff, 0x00, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x800" + - + input: + bytes: [ 0x6d, 0xff, 0xc6, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x874" + - + input: + bytes: [ 0xf6, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d2, #0x6" + - + input: + bytes: [ 0x3c, 0x63 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xc6" + - + input: + bytes: [ 0x6d, 0xff, 0xa9, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x8ae" + - + input: + bytes: [ 0x6d, 0xff, 0x45, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x976" + - + input: + bytes: [ 0x3c, 0x34 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x68" + - + input: + bytes: [ 0xbf, 0x21, 0xcd, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d1, #0x2, #-0x66" + - + input: + bytes: [ 0xde, 0x1e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x3c" + - + input: + bytes: [ 0x3c, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x2e" + - + input: + bytes: [ 0x6d, 0xff, 0xde, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xa44" + - + input: + bytes: [ 0x6d, 0xff, 0x89, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xaee" + - + input: + bytes: [ 0xbf, 0x89, 0xea, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d9, #0x8, #-0x2c" + - + input: + bytes: [ 0x6d, 0xff, 0xe8, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x830" + - + input: + bytes: [ 0x6d, 0xff, 0xee, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xa24" + - + input: + bytes: [ 0x6d, 0xff, 0x73, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x151a" + - + input: + bytes: [ 0xee, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0xc" + - + input: + bytes: [ 0x3c, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x22" + - + input: + bytes: [ 0x5e, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x12" + - + input: + bytes: [ 0x6d, 0xff, 0xde, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x44" + - + input: + bytes: [ 0x5e, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x14" + - + input: + bytes: [ 0x3c, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x52" + - + input: + bytes: [ 0x5e, 0x1e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x1c" + - + input: + bytes: [ 0x3e, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x8" + - + input: + bytes: [ 0x3e, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x10" + - + input: + bytes: [ 0x3c, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x14" + - + input: + bytes: [ 0x3c, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xc" + - + input: + bytes: [ 0x6d, 0xff, 0xb2, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x9c" + - + input: + bytes: [ 0x6d, 0xff, 0xe8, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x30" + - + input: + bytes: [ 0x3e, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x18" + - + input: + bytes: [ 0xbe, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x38" + - + input: + bytes: [ 0xbe, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x3e" + - + input: + bytes: [ 0x5f, 0x0f, 0x22, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x44" + - + input: + bytes: [ 0x5f, 0x0f, 0x24, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x48" + - + input: + bytes: [ 0x3c, 0x27 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x4e" + - + input: + bytes: [ 0xee, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x6" + - + input: + bytes: [ 0x3c, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x24" + - + input: + bytes: [ 0x6d, 0x00, 0x43, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x886" + - + input: + bytes: [ 0x6d, 0x00, 0x54, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x8a8" + - + input: + bytes: [ 0x6d, 0x00, 0x91, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x522" + - + input: + bytes: [ 0x6d, 0x00, 0x4a, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x894" + - + input: + bytes: [ 0x6d, 0x00, 0xa4, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x548" + - + input: + bytes: [ 0xee, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0xc" + - + input: + bytes: [ 0x6d, 0x00, 0xc4, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x388" + - + input: + bytes: [ 0x6d, 0x00, 0x29, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x852" + - + input: + bytes: [ 0xdf, 0x08, 0x92, 0x81 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d8, #0, #0x324" + - + input: + bytes: [ 0x6d, 0x00, 0x5a, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x4b4" + - + input: + bytes: [ 0x6e, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #-0xc" + - + input: + bytes: [ 0x6d, 0x00, 0xbb, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x376" + - + input: + bytes: [ 0x6d, 0x00, 0x8c, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x318" + - + input: + bytes: [ 0x6d, 0x00, 0xf1, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x5e2" + - + input: + bytes: [ 0x6d, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1d0" + - + input: + bytes: [ 0x6d, 0x00, 0xab, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x556" + - + input: + bytes: [ 0x3c, 0x37 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x6e" + - + input: + bytes: [ 0x6d, 0x00, 0x03, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x206" + - + input: + bytes: [ 0x6d, 0x00, 0xb3, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x566" + - + input: + bytes: [ 0x6e, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x12" + - + input: + bytes: [ 0x2d, 0x02, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "calli a2" + - + input: + bytes: [ 0x6d, 0x00, 0x91, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x122" + - + input: + bytes: [ 0x3f, 0xfc, 0xc9, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d12, d15, #-0x6e" + - + input: + bytes: [ 0x6d, 0x00, 0xca, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x194" + - + input: + bytes: [ 0x6d, 0x00, 0x87, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x50e" + - + input: + bytes: [ 0x6d, 0x00, 0x92, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x124" + - + input: + bytes: [ 0x6d, 0x00, 0x47, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x48e" + - + input: + bytes: [ 0x6d, 0x00, 0x1f, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x43e" + - + input: + bytes: [ 0xf6, 0x83 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d8, #0x6" + - + input: + bytes: [ 0x6f, 0x1f, 0xf8, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x1, #-0x10" + - + input: + bytes: [ 0x6f, 0x0f, 0xf2, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #-0x1c" + - + input: + bytes: [ 0x6d, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x68" + - + input: + bytes: [ 0x6d, 0x00, 0xea, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x3d4" + - + input: + bytes: [ 0x6d, 0xff, 0x21, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x5be" + - + input: + bytes: [ 0x3f, 0xf0, 0xfd, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, d15, #-0x6" + - + input: + bytes: [ 0x2e, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x1, #0x16" + - + input: + bytes: [ 0xdf, 0x1f, 0xfe, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0x1, #-0x4" + - + input: + bytes: [ 0x6f, 0x1f, 0x12, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x1, #0x24" + - + input: + bytes: [ 0xdf, 0x1f, 0xfb, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0x1, #-0xa" + - + input: + bytes: [ 0x6f, 0x0f, 0xff, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #-0x2" + - + input: + bytes: [ 0x6f, 0x0f, 0xfc, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #-0x8" + - + input: + bytes: [ 0xdc, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ji a15" + - + input: + bytes: [ 0x6d, 0x00, 0x2f, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x5e" + - + input: + bytes: [ 0x3e, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d2, #0x10" + - + input: + bytes: [ 0x5e, 0x13 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x6" + - + input: + bytes: [ 0xee, 0x13 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x26" + - + input: + bytes: [ 0x5e, 0x32 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x3, #0x4" + - + input: + bytes: [ 0x7d, 0x4f, 0x0d, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne.a a15, a4, #0x1a" + - + input: + bytes: [ 0x3c, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x8" + - + input: + bytes: [ 0xbf, 0x30, 0xea, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, #0x3, #-0x2c" + - + input: + bytes: [ 0x6d, 0xff, 0xe0, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x40" + - + input: + bytes: [ 0x1e, 0x32 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0x3, #0x4" + - + input: + bytes: [ 0x5e, 0x43 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x4, #0x6" + - + input: + bytes: [ 0x5e, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x2, #0x6" + - + input: + bytes: [ 0xdf, 0x19, 0x49, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d9, #0x1, #0x92" + - + input: + bytes: [ 0x5f, 0x8f, 0x28, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d8, #0x50" + - + input: + bytes: [ 0x6d, 0x00, 0xa5, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x174a" + - + input: + bytes: [ 0x6d, 0x00, 0x0a, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1414" + - + input: + bytes: [ 0x6d, 0xff, 0xc0, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x80" + - + input: + bytes: [ 0x6d, 0x00, 0xc3, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1786" + - + input: + bytes: [ 0x3c, 0x1c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x38" + - + input: + bytes: [ 0x6d, 0x00, 0x6b, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x16d6" + - + input: + bytes: [ 0x6d, 0x00, 0xbc, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1378" + - + input: + bytes: [ 0x6d, 0x00, 0x72, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x16e4" + - + input: + bytes: [ 0xff, 0x3f, 0x0b, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d15, #0x3, #0x16" + - + input: + bytes: [ 0x7d, 0xf4, 0x04, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne.a a4, a15, #0x8" + - + input: + bytes: [ 0x3c, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x20" + - + input: + bytes: [ 0x6d, 0xff, 0xd6, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x54" + - + input: + bytes: [ 0x6d, 0xff, 0x28, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1b0" + - + input: + bytes: [ 0xf6, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d2, #0xc" + - + input: + bytes: [ 0x6d, 0xff, 0x71, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x11e" + - + input: + bytes: [ 0x7e, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x1a" + - + input: + bytes: [ 0x6d, 0x00, 0x5b, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xcb6" + - + input: + bytes: [ 0x3f, 0x0f, 0x04, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d15, d0, #0x8" + - + input: + bytes: [ 0xdf, 0x7f, 0xf6, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x7, #-0x14" + - + input: + bytes: [ 0x76, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d1, #0xe" + - + input: + bytes: [ 0x76, 0x13 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d1, #0x6" + - + input: + bytes: [ 0x3c, 0x1e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x3c" + - + input: + bytes: [ 0xf6, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d0, #0xc" + - + input: + bytes: [ 0x7e, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0xa" + - + input: + bytes: [ 0x3f, 0x40, 0xe3, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, d4, #-0x3a" + - + input: + bytes: [ 0x6d, 0x00, 0x65, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x12ca" + - + input: + bytes: [ 0x6d, 0x00, 0xf9, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xff2" + - + input: + bytes: [ 0x6d, 0x00, 0x3a, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1074" + - + input: + bytes: [ 0x6d, 0xff, 0xf2, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x61c" + - + input: + bytes: [ 0x6d, 0x00, 0x9a, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1134" + - + input: + bytes: [ 0x6d, 0x00, 0xdc, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x11b8" + - + input: + bytes: [ 0x6d, 0x00, 0xf0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x9e0" + - + input: + bytes: [ 0x6d, 0xff, 0x0d, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3e6" + - + input: + bytes: [ 0x6d, 0xff, 0x04, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3f8" + - + input: + bytes: [ 0x76, 0x27 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d2, #0xe" + - + input: + bytes: [ 0x76, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d2, #0x6" + - + input: + bytes: [ 0x6d, 0x00, 0x71, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x24e2" + - + input: + bytes: [ 0xfc, 0x5e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a5, #-0x4" + - + input: + bytes: [ 0xfc, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a2, #-0xe" + - + input: + bytes: [ 0x6f, 0x0f, 0xfe, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0, #-0x4" + - + input: + bytes: [ 0x6f, 0x1f, 0xfa, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0x1, #-0xc" + - + input: + bytes: [ 0x1d, 0x00, 0x03, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x6" + - + input: + bytes: [ 0x6d, 0x00, 0x02, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x204" + - + input: + bytes: [ 0x6d, 0x00, 0xe1, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1c2" + - + input: + bytes: [ 0x6d, 0x00, 0x0d, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1a" + - + input: + bytes: [ 0x6d, 0x00, 0x72, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x24e4" + - + input: + bytes: [ 0x6d, 0x00, 0xea, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x23d4" + - + input: + bytes: [ 0x6d, 0x00, 0xfa, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x23f4" + - + input: + bytes: [ 0x6d, 0x00, 0xf3, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1fe6" + - + input: + bytes: [ 0x3c, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xa0" + - + input: + bytes: [ 0x6d, 0x00, 0xc6, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x218c" + - + input: + bytes: [ 0x6d, 0x00, 0x41, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1e82" + - + input: + bytes: [ 0xbf, 0x48, 0xb1, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d8, #0x4, #-0x9e" + - + input: + bytes: [ 0x6f, 0x70, 0xec, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d0, #0x7, #-0x28" + - + input: + bytes: [ 0x6d, 0x00, 0x50, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x18a0" + - + input: + bytes: [ 0x6d, 0x00, 0xf9, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x15f2" + - + input: + bytes: [ 0x6d, 0x00, 0x5f, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x18be" + - + input: + bytes: [ 0x6d, 0x00, 0x38, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1670" + - + input: + bytes: [ 0x6d, 0x00, 0x44, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x88" + - + input: + bytes: [ 0x6d, 0x00, 0x27, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x24e" + - + input: + bytes: [ 0x6d, 0xff, 0xb7, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x292" + - + input: + bytes: [ 0x3c, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x28" + - + input: + bytes: [ 0x6d, 0xff, 0xbd, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x86" + - + input: + bytes: [ 0x6d, 0xff, 0xb9, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x8e" + - + input: + bytes: [ 0x6d, 0xff, 0xb4, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x98" + - + input: + bytes: [ 0x6d, 0xff, 0xaf, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xa2" + - + input: + bytes: [ 0x3c, 0xed ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x26" + - + input: + bytes: [ 0xfc, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a15, #-0x14" + - + input: + bytes: [ 0xfd, 0xf0, 0xed, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a15, #-0x26" + - + input: + bytes: [ 0xdf, 0x1f, 0x23, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x46" + - + input: + bytes: [ 0x6e, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x8" + - + input: + bytes: [ 0x76, 0xcf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d12, #0x1e" + - + input: + bytes: [ 0xfc, 0x4e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a4, #-0x4" + - + input: + bytes: [ 0xdf, 0x0c, 0xe0, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d12, #0, #-0x40" + - + input: + bytes: [ 0xfc, 0x2e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a2, #-0x4" + - + input: + bytes: [ 0x3c, 0xd9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x4e" + - + input: + bytes: [ 0xde, 0x25 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x2, #0x2a" + - + input: + bytes: [ 0x2e, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #0x6" + - + input: + bytes: [ 0xdf, 0x0c, 0xd3, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d12, #0, #-0x5a" + - + input: + bytes: [ 0x76, 0xc5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d12, #0xa" + - + input: + bytes: [ 0xfc, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a2, #-0x2" + - + input: + bytes: [ 0x6e, 0xc9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #-0x6e" + - + input: + bytes: [ 0x3c, 0xc4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x78" + - + input: + bytes: [ 0xdf, 0x00, 0x2e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d0, #0, #0x5c" + - + input: + bytes: [ 0xdf, 0x10, 0x2b, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d0, #0x1, #0x56" + - + input: + bytes: [ 0xfe, 0xdb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d13, #0x36" + - + input: + bytes: [ 0x76, 0xdb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d13, #0x16" + - + input: + bytes: [ 0x6d, 0x00, 0x53, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xa6" + - + input: + bytes: [ 0xdf, 0x0c, 0x9b, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d12, #0, #-0xca" + - + input: + bytes: [ 0x6d, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x70" + - + input: + bytes: [ 0x3c, 0x94 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0xd8" + - + input: + bytes: [ 0xdf, 0x2f, 0x91, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x2, #-0xde" + - + input: + bytes: [ 0x6e, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0xe" + - + input: + bytes: [ 0x6d, 0x00, 0x15, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2a" + - + input: + bytes: [ 0xdf, 0x0c, 0x86, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d12, #0, #-0xf4" + - + input: + bytes: [ 0xdf, 0x04, 0x7c, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d4, #0, #-0x108" + - + input: + bytes: [ 0x6d, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x8" + - + input: + bytes: [ 0x1d, 0xff, 0x77, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x112" + - + input: + bytes: [ 0x1d, 0x00, 0x02, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x4" + - + input: + bytes: [ 0x6d, 0x00, 0x15, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x182a" + - + input: + bytes: [ 0x6d, 0x00, 0xbe, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x157c" + - + input: + bytes: [ 0x6d, 0x00, 0x0e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1c" + - + input: + bytes: [ 0x6d, 0x00, 0xf1, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1e2" + - + input: + bytes: [ 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x0" diff --git a/tests/MC/TriCore/LoadStore.s.yaml b/tests/MC/TriCore/LoadStore.s.yaml new file mode 100644 index 0000000000..d3029e5506 --- /dev/null +++ b/tests/MC/TriCore/LoadStore.s.yaml @@ -0,0 +1,2854 @@ +test_cases: + - + input: + bytes: [ 0x09, 0xff, 0x08, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a15]#0x88" + - + input: + bytes: [ 0x89, 0xff, 0x08, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a15]#0x88, d15" + - + input: + bytes: [ 0x09, 0xf0, 0x0c, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [a15]#0x8c" + - + input: + bytes: [ 0x89, 0xf0, 0x0c, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a15]#0x8c, d0" + - + input: + bytes: [ 0x09, 0xff, 0x00, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a15]#0x80" + - + input: + bytes: [ 0x89, 0xff, 0x00, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a15]#0x80, d15" + - + input: + bytes: [ 0x09, 0xff, 0x40, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x80" + - + input: + bytes: [ 0x09, 0xff, 0x41, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x81" + - + input: + bytes: [ 0x54, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a15]" + - + input: + bytes: [ 0x4c, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a4]#0x4" + - + input: + bytes: [ 0x6c, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a4]#0x4, d15" + - + input: + bytes: [ 0x09, 0xff, 0x43, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x83" + - + input: + bytes: [ 0x89, 0xff, 0x03, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15]#0x83, d15" + - + input: + bytes: [ 0x39, 0x2f, 0x43, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a2]#0x483" + - + input: + bytes: [ 0xc8, 0x52 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a2, [a15]#0x14" + - + input: + bytes: [ 0xd4, 0x2d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a13, [a2]" + - + input: + bytes: [ 0x09, 0x2e, 0x84, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a14, [a2]#0x4" + - + input: + bytes: [ 0x89, 0xc2, 0x84, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [a12]#0x4, a2" + - + input: + bytes: [ 0x09, 0xc2, 0x84, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a2, [a12]#0x4" + - + input: + bytes: [ 0x09, 0x29, 0x48, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d9, [a2]#0x8" + - + input: + bytes: [ 0x09, 0xfa, 0x0c, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.b d10, [a15]#0xc" + - + input: + bytes: [ 0x08, 0xe0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0xe" + - + input: + bytes: [ 0x09, 0x41, 0x41, 0x68 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d1, [a4]#0x181" + - + input: + bytes: [ 0x89, 0x20, 0x01, 0x68 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a2]#0x181, d0" + - + input: + bytes: [ 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0xf" + - + input: + bytes: [ 0x09, 0x4f, 0x42, 0x68 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a4]#0x182" + - + input: + bytes: [ 0x89, 0x2f, 0x02, 0x68 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a2]#0x182, d15" + - + input: + bytes: [ 0x09, 0xf0, 0x50, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0x10" + - + input: + bytes: [ 0x09, 0x4f, 0x40, 0x68 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a4]#0x180" + - + input: + bytes: [ 0x89, 0x2f, 0x00, 0x68 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a2]#0x180, d15" + - + input: + bytes: [ 0x09, 0xf0, 0x51, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0x11" + - + input: + bytes: [ 0x08, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0x1" + - + input: + bytes: [ 0x09, 0x4f, 0x41, 0x68 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a4]#0x181" + - + input: + bytes: [ 0x89, 0x2f, 0x01, 0x68 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a2]#0x181, d15" + - + input: + bytes: [ 0x08, 0xd0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0xd" + - + input: + bytes: [ 0x09, 0xf0, 0x53, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0x13" + - + input: + bytes: [ 0x08, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0x3" + - + input: + bytes: [ 0x14, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]" + - + input: + bytes: [ 0x09, 0xf0, 0x52, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0x12" + - + input: + bytes: [ 0x08, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x2" + - + input: + bytes: [ 0x4c, 0xe2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a14]#0x8" + - + input: + bytes: [ 0x6c, 0xe2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a14]#0x8, d15" + - + input: + bytes: [ 0x08, 0xb0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0xb" + - + input: + bytes: [ 0x09, 0xc2, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.b d2, [a12]#0" + - + input: + bytes: [ 0x09, 0xe1, 0x20, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d1, [a14]#0x120" + - + input: + bytes: [ 0x89, 0xe1, 0x20, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a14]#0x120, d1" + - + input: + bytes: [ 0x09, 0xef, 0x20, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a14]#0x120" + - + input: + bytes: [ 0x89, 0xef, 0x20, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a14]#0x120, d15" + - + input: + bytes: [ 0x09, 0xff, 0xc6, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d15, [a15]#0x6" + - + input: + bytes: [ 0x08, 0xb5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d5, [a15]#0xb" + - + input: + bytes: [ 0x09, 0xf0, 0x0c, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.b d0, [a15]#0xc" + - + input: + bytes: [ 0x89, 0xef, 0x10, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a14]#0x110, d15" + - + input: + bytes: [ 0x08, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0x9" + - + input: + bytes: [ 0x14, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d1, [a2]" + - + input: + bytes: [ 0x34, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a2], d15" + - + input: + bytes: [ 0x0c, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a2]#0x1" + - + input: + bytes: [ 0x2c, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a2]#0x1, d15" + - + input: + bytes: [ 0x0c, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a2]#0x3" + - + input: + bytes: [ 0x2c, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a2]#0x3, d15" + - + input: + bytes: [ 0x08, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0xf" + - + input: + bytes: [ 0x08, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0xa" + - + input: + bytes: [ 0x08, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d1, [a15]#0xf" + - + input: + bytes: [ 0x09, 0xe2, 0x30, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d2, [a14]#0x130" + - + input: + bytes: [ 0x89, 0xe2, 0x30, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a14]#0x130, d2" + - + input: + bytes: [ 0x09, 0xef, 0x30, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a14]#0x130" + - + input: + bytes: [ 0x89, 0xef, 0x30, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a14]#0x130, d15" + - + input: + bytes: [ 0x09, 0xe2, 0x34, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d2, [a14]#0x134" + - + input: + bytes: [ 0x89, 0xe2, 0x34, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a14]#0x134, d2" + - + input: + bytes: [ 0x09, 0xef, 0x34, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a14]#0x134" + - + input: + bytes: [ 0x89, 0xef, 0x34, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a14]#0x134, d15" + - + input: + bytes: [ 0x09, 0xff, 0xc4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d15, [a15]#0x4" + - + input: + bytes: [ 0x08, 0xa5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d5, [a15]#0xa" + - + input: + bytes: [ 0x39, 0x5f, 0x03, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a5]#0x203" + - + input: + bytes: [ 0xe9, 0x4f, 0x03, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a4]#0x203, d15" + - + input: + bytes: [ 0x89, 0xef, 0x14, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a14]#0x114, d15" + - + input: + bytes: [ 0x08, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0x8" + - + input: + bytes: [ 0x2c, 0xc1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a12]#0x1, d15" + - + input: + bytes: [ 0x09, 0xff, 0x0c, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.b d15, [a15]#0xc" + - + input: + bytes: [ 0x34, 0xcf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a12], d15" + - + input: + bytes: [ 0x44, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a15+]" + - + input: + bytes: [ 0x64, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a2+], d15" + - + input: + bytes: [ 0x89, 0x45, 0x94, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [a4]#0x14, a5" + - + input: + bytes: [ 0xd4, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a2, [a15]" + - + input: + bytes: [ 0xd4, 0x2c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a12, [a2]" + - + input: + bytes: [ 0x08, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x4" + - + input: + bytes: [ 0x89, 0x4d, 0x84, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [a4]#0x4, a13" + - + input: + bytes: [ 0xd4, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a2, [a2]" + - + input: + bytes: [ 0xf4, 0x42 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [a4], a2" + - + input: + bytes: [ 0x08, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d9, [a15]#0x4" + - + input: + bytes: [ 0x89, 0x49, 0x08, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a4]#0x8, d9" + - + input: + bytes: [ 0x09, 0xff, 0x6f, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x2f" + - + input: + bytes: [ 0x09, 0xf5, 0x62, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d5, [a15]#0x22" + - + input: + bytes: [ 0x09, 0xf6, 0x63, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d6, [a15]#0x23" + - + input: + bytes: [ 0x09, 0xff, 0x70, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x30" + - + input: + bytes: [ 0x09, 0xf5, 0x5a, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d5, [a15]#0x1a" + - + input: + bytes: [ 0x09, 0xf6, 0x5b, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d6, [a15]#0x1b" + - + input: + bytes: [ 0x09, 0xff, 0x71, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x31" + - + input: + bytes: [ 0x09, 0xf5, 0x6a, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d5, [a15]#0x2a" + - + input: + bytes: [ 0x09, 0xf6, 0x6b, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d6, [a15]#0x2b" + - + input: + bytes: [ 0x08, 0x5f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x5" + - + input: + bytes: [ 0x14, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a2]" + - + input: + bytes: [ 0x09, 0xdf, 0x40, 0x18 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a13]#0x40" + - + input: + bytes: [ 0x89, 0xdf, 0x00, 0x18 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a13]#0x40, d15" + - + input: + bytes: [ 0x09, 0xd1, 0x00, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d1, [a13]#0x40" + - + input: + bytes: [ 0x89, 0xd1, 0x00, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a13]#0x40, d1" + - + input: + bytes: [ 0x14, 0xd0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a13]" + - + input: + bytes: [ 0x34, 0xdf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a13], d15" + - + input: + bytes: [ 0x09, 0xff, 0x6e, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x2e" + - + input: + bytes: [ 0x09, 0xff, 0x61, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x21" + - + input: + bytes: [ 0x09, 0xdf, 0x44, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a13]#0x84" + - + input: + bytes: [ 0x89, 0xdf, 0x04, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a13]#0x84, d15" + - + input: + bytes: [ 0x09, 0xf0, 0x5f, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0x1f" + - + input: + bytes: [ 0x09, 0xd1, 0x00, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d1, [a13]#0x80" + - + input: + bytes: [ 0x89, 0xd1, 0x00, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a13]#0x80, d1" + - + input: + bytes: [ 0x09, 0xff, 0x5e, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x1e" + - + input: + bytes: [ 0x09, 0xf0, 0x60, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0x20" + - + input: + bytes: [ 0x14, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a2]" + - + input: + bytes: [ 0x09, 0xd0, 0x45, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a13]#0x85" + - + input: + bytes: [ 0x89, 0xdf, 0x05, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a13]#0x85, d15" + - + input: + bytes: [ 0x09, 0xff, 0x59, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x19" + - + input: + bytes: [ 0x09, 0xdf, 0x64, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a13]#0xa4" + - + input: + bytes: [ 0x89, 0xdf, 0x24, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a13]#0xa4, d15" + - + input: + bytes: [ 0x09, 0xf0, 0x57, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0x17" + - + input: + bytes: [ 0x09, 0xd1, 0x20, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d1, [a13]#0xa0" + - + input: + bytes: [ 0x89, 0xd1, 0x20, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a13]#0xa0, d1" + - + input: + bytes: [ 0x09, 0xff, 0x56, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x16" + - + input: + bytes: [ 0x09, 0xf0, 0x58, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0x18" + - + input: + bytes: [ 0x09, 0xd0, 0x64, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a13]#0xa4" + - + input: + bytes: [ 0x09, 0xff, 0x69, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x29" + - + input: + bytes: [ 0x39, 0xcf, 0x04, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a12]#0x204" + - + input: + bytes: [ 0xe9, 0xcf, 0x04, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a12]#0x204, d15" + - + input: + bytes: [ 0x09, 0xf0, 0x67, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0x27" + - + input: + bytes: [ 0x19, 0xc1, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d1, [a12]#0x200" + - + input: + bytes: [ 0x59, 0xc1, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a12]#0x200, d1" + - + input: + bytes: [ 0x09, 0xff, 0x66, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x26" + - + input: + bytes: [ 0x09, 0xf0, 0x68, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0x28" + - + input: + bytes: [ 0x39, 0xc0, 0x04, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a12]#0x204" + - + input: + bytes: [ 0x09, 0xf5, 0x6c, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d5, [a15]#0x2c" + - + input: + bytes: [ 0x09, 0x20, 0x4a, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a2]#0xa" + - + input: + bytes: [ 0x09, 0x4f, 0x61, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a4]#0x21" + - + input: + bytes: [ 0x89, 0x2f, 0x21, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a2]#0x21, d15" + - + input: + bytes: [ 0x09, 0x2f, 0x06, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a2]#0x6" + - + input: + bytes: [ 0x09, 0x4f, 0x60, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a4]#0x20" + - + input: + bytes: [ 0x89, 0x2f, 0x20, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a2]#0x20, d15" + - + input: + bytes: [ 0x2c, 0x44 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a4]#0x4, d15" + - + input: + bytes: [ 0xf4, 0x45 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [a4], a5" + - + input: + bytes: [ 0x0c, 0x44 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a4]#0x4" + - + input: + bytes: [ 0x2c, 0x45 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a4]#0x5, d15" + - + input: + bytes: [ 0x89, 0x4f, 0x2c, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a4]#0x2c, d15" + - + input: + bytes: [ 0xd4, 0xcd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a13, [a12]" + - + input: + bytes: [ 0xf4, 0x4d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [a4], a13" + - + input: + bytes: [ 0x74, 0xd0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a13], d0" + - + input: + bytes: [ 0x09, 0xc4, 0x5d, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d4, [a12]#0x1d" + - + input: + bytes: [ 0x4c, 0xc5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a12]#0x14" + - + input: + bytes: [ 0x4c, 0xc4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a12]#0x10" + - + input: + bytes: [ 0x09, 0xff, 0x61, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0xa1" + - + input: + bytes: [ 0x89, 0x2f, 0x21, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a2]#0xa1, d15" + - + input: + bytes: [ 0x48, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a15]#0x4" + - + input: + bytes: [ 0x09, 0x2f, 0x60, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a2]#0xa0" + - + input: + bytes: [ 0x89, 0xff, 0x20, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15]#0xa0, d15" + - + input: + bytes: [ 0x09, 0xcf, 0x5c, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a12]#0x1c" + - + input: + bytes: [ 0x34, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15], d15" + - + input: + bytes: [ 0xf4, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [a15], a5" + - + input: + bytes: [ 0x6c, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a15]#0x14, d15" + - + input: + bytes: [ 0x68, 0x42 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a15]#0x10, d2" + - + input: + bytes: [ 0x68, 0x62 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a15]#0x18, d2" + - + input: + bytes: [ 0x2c, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15]#0x8, d15" + - + input: + bytes: [ 0x6c, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a15]#0x4, d15" + - + input: + bytes: [ 0x2c, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15]#0xe, d15" + - + input: + bytes: [ 0x89, 0xff, 0x0a, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a15]#0xa, d15" + - + input: + bytes: [ 0x89, 0xff, 0x1c, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15]#0x1c, d15" + - + input: + bytes: [ 0x89, 0xff, 0x1d, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15]#0x1d, d15" + - + input: + bytes: [ 0x39, 0xff, 0x37, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x6037" + - + input: + bytes: [ 0x09, 0xff, 0x54, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x14" + - + input: + bytes: [ 0x09, 0xff, 0x5c, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x1c" + - + input: + bytes: [ 0x09, 0xff, 0x5b, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x1b" + - + input: + bytes: [ 0x39, 0xff, 0x33, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x6033" + - + input: + bytes: [ 0x39, 0xff, 0x31, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x6031" + - + input: + bytes: [ 0x39, 0xff, 0x32, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x6032" + - + input: + bytes: [ 0x09, 0xff, 0x10, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a15]#0x50" + - + input: + bytes: [ 0x74, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a2], d15" + - + input: + bytes: [ 0x39, 0x2f, 0x30, 0x46 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a2]#0x6130" + - + input: + bytes: [ 0xe9, 0x2f, 0x30, 0x46 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a2]#0x6130, d15" + - + input: + bytes: [ 0x39, 0x2f, 0x33, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a2]#0x6033" + - + input: + bytes: [ 0xe9, 0x2f, 0x33, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a2]#0x6033, d15" + - + input: + bytes: [ 0x39, 0x2f, 0x18, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a2]#0x6018" + - + input: + bytes: [ 0xe9, 0x2f, 0x18, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a2]#0x6018, d15" + - + input: + bytes: [ 0x39, 0x2f, 0x37, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a2]#0x6037" + - + input: + bytes: [ 0xe9, 0x2f, 0x37, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a2]#0x6037, d15" + - + input: + bytes: [ 0x39, 0x2f, 0x14, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a2]#0x6014" + - + input: + bytes: [ 0x39, 0x20, 0x1c, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a2]#0x601c" + - + input: + bytes: [ 0x08, 0xaf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0xa" + - + input: + bytes: [ 0xe9, 0x2f, 0x1c, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a2]#0x601c, d15" + - + input: + bytes: [ 0x39, 0x20, 0x1b, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a2]#0x601b" + - + input: + bytes: [ 0x08, 0x8f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x8" + - + input: + bytes: [ 0xe9, 0x2f, 0x1b, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a2]#0x601b, d15" + - + input: + bytes: [ 0x39, 0x20, 0x19, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a2]#0x6019" + - + input: + bytes: [ 0x08, 0x9f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x9" + - + input: + bytes: [ 0xe9, 0x2f, 0x19, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a2]#0x6019, d15" + - + input: + bytes: [ 0x39, 0x2f, 0x1a, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a2]#0x601a" + - + input: + bytes: [ 0xe9, 0x2f, 0x1a, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a2]#0x601a, d15" + - + input: + bytes: [ 0x48, 0x34 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d4, [a15]#0xc" + - + input: + bytes: [ 0x19, 0x20, 0x30, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [a2]#0x6030" + - + input: + bytes: [ 0x48, 0x5f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a15]#0x14" + - + input: + bytes: [ 0x48, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d1, [a15]#0x10" + - + input: + bytes: [ 0x74, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a2], d0" + - + input: + bytes: [ 0x19, 0x20, 0x34, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [a2]#0x6034" + - + input: + bytes: [ 0x48, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a15]#0x1c" + - + input: + bytes: [ 0x48, 0x61 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d1, [a15]#0x18" + - + input: + bytes: [ 0x39, 0x2f, 0x03, 0x16 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a2]#0x6043" + - + input: + bytes: [ 0x19, 0x20, 0x00, 0x16 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [a2]#0x6040" + - + input: + bytes: [ 0x48, 0x9f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a15]#0x24" + - + input: + bytes: [ 0x48, 0x81 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d1, [a15]#0x20" + - + input: + bytes: [ 0x39, 0x2f, 0x0f, 0x16 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a2]#0x604f" + - + input: + bytes: [ 0x19, 0x20, 0x0c, 0x16 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [a2]#0x604c" + - + input: + bytes: [ 0x48, 0xbf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a15]#0x2c" + - + input: + bytes: [ 0x48, 0xa1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d1, [a15]#0x28" + - + input: + bytes: [ 0x19, 0x20, 0x00, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [a2]#0x6080" + - + input: + bytes: [ 0x48, 0xdf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a15]#0x34" + - + input: + bytes: [ 0x48, 0xc1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d1, [a15]#0x30" + - + input: + bytes: [ 0x19, 0x20, 0x04, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [a2]#0x6084" + - + input: + bytes: [ 0x48, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a15]#0x3c" + - + input: + bytes: [ 0x48, 0xe1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d1, [a15]#0x38" + - + input: + bytes: [ 0x19, 0x2f, 0x08, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a2]#0x6088" + - + input: + bytes: [ 0x09, 0xf0, 0x04, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [a15]#0x44" + - + input: + bytes: [ 0x09, 0xf1, 0x00, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d1, [a15]#0x40" + - + input: + bytes: [ 0x19, 0x2f, 0x14, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a2]#0x2014" + - + input: + bytes: [ 0x09, 0xf0, 0x0c, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [a15]#0x4c" + - + input: + bytes: [ 0x09, 0xf1, 0x08, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d1, [a15]#0x48" + - + input: + bytes: [ 0xc8, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a2, [a15]#0x4" + - + input: + bytes: [ 0x4c, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a2]#0x8" + - + input: + bytes: [ 0x09, 0x22, 0x88, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a2, [a2]#0x8" + - + input: + bytes: [ 0x09, 0x24, 0x02, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d4, [a2]#0x2" + - + input: + bytes: [ 0x14, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]" + - + input: + bytes: [ 0x39, 0xff, 0x18, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x6018" + - + input: + bytes: [ 0xe9, 0xff, 0x18, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15]#0x6018, d15" + - + input: + bytes: [ 0x39, 0xff, 0x2c, 0x46 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x612c" + - + input: + bytes: [ 0xe9, 0xff, 0x2c, 0x46 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15]#0x612c, d15" + - + input: + bytes: [ 0x39, 0xff, 0x30, 0x46 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x6130" + - + input: + bytes: [ 0xe9, 0xff, 0x30, 0x46 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15]#0x6130, d15" + - + input: + bytes: [ 0x39, 0xf0, 0x10, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0x6010" + - + input: + bytes: [ 0xe9, 0xf0, 0x10, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15]#0x6010, d0" + - + input: + bytes: [ 0x39, 0xf0, 0x12, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0x6012" + - + input: + bytes: [ 0x54, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d1, [a15]" + - + input: + bytes: [ 0xe9, 0xff, 0x12, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15]#0x6012, d15" + - + input: + bytes: [ 0x39, 0xff, 0x10, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x6010" + - + input: + bytes: [ 0xe9, 0xff, 0x10, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15]#0x6010, d15" + - + input: + bytes: [ 0x39, 0xff, 0x11, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x6011" + - + input: + bytes: [ 0x39, 0xff, 0x35, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x6035" + - + input: + bytes: [ 0x85, 0xf1, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d1, #0xf0000010" + - + input: + bytes: [ 0x85, 0xf0, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, #0xf0000010" + - + input: + bytes: [ 0x54, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [a15]" + - + input: + bytes: [ 0x74, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a15], d15" + - + input: + bytes: [ 0x19, 0xff, 0x30, 0x36 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a15]#0x60f0" + - + input: + bytes: [ 0x19, 0xf0, 0x30, 0x36 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [a15]#0x60f0" + - + input: + bytes: [ 0x59, 0xff, 0x30, 0x36 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a15]#0x60f0, d15" + - + input: + bytes: [ 0x2c, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15]#0x4, d15" + - + input: + bytes: [ 0x39, 0xff, 0x34, 0x36 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x60f4" + - + input: + bytes: [ 0xe9, 0xff, 0x34, 0x36 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15]#0x60f4, d15" + - + input: + bytes: [ 0x89, 0xa2, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.d [sp]#0, e2" + - + input: + bytes: [ 0x09, 0xa0, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.d e0, [sp]#0" + - + input: + bytes: [ 0x54, 0x31 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d1, [a3]" + - + input: + bytes: [ 0x08, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x1" + - + input: + bytes: [ 0xd4, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a15, [a15]" + - + input: + bytes: [ 0x54, 0x3f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a3]" + - + input: + bytes: [ 0x74, 0x3f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a3], d15" + - + input: + bytes: [ 0x39, 0x2f, 0x35, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a2]#0x6035" + - + input: + bytes: [ 0x85, 0xff, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, #0xf0000010" + - + input: + bytes: [ 0x49, 0x40, 0x40, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ldmst [a4]#0, e0" + - + input: + bytes: [ 0x74, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a15], d0" + - + input: + bytes: [ 0x74, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a4], d1" + - + input: + bytes: [ 0x74, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a4], d15" + - + input: + bytes: [ 0x15, 0xd0, 0xc0, 0xe3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "stlcx #0xd0003f80" + - + input: + bytes: [ 0x15, 0xd0, 0xc0, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "stucx #0xd0003fc0" + - + input: + bytes: [ 0x85, 0xdf, 0xc4, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, #0xd0003fc4" + - + input: + bytes: [ 0x15, 0xd0, 0xc0, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lducx #0xd0003fc0" + - + input: + bytes: [ 0x15, 0xd0, 0xc0, 0xeb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ldlcx #0xd0003f80" + - + input: + bytes: [ 0x39, 0xff, 0x05, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a15]#0x205" + - + input: + bytes: [ 0xe9, 0xff, 0x05, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15]#0x205, d15" + - + input: + bytes: [ 0x2c, 0xa4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [sp]#0x4, d15" + - + input: + bytes: [ 0x2c, 0xa5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [sp]#0x5, d15" + - + input: + bytes: [ 0x89, 0xaf, 0x31, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [sp]#0x31, d15" + - + input: + bytes: [ 0x89, 0xaf, 0x24, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [sp]#0x24, d15" + - + input: + bytes: [ 0x89, 0xaf, 0x28, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [sp]#0x28, d15" + - + input: + bytes: [ 0x09, 0x2f, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.b d15, [a2]#0" + - + input: + bytes: [ 0x2c, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15]#0xc, d15" + - + input: + bytes: [ 0x28, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15]#0xf, d8" + - + input: + bytes: [ 0x2c, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15]#0x2, d15" + - + input: + bytes: [ 0x08, 0x81 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d1, [a15]#0x8" + - + input: + bytes: [ 0x09, 0xff, 0x00, 0x69 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a15]#0x180" + - + input: + bytes: [ 0x89, 0xf0, 0x00, 0x69 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a15]#0x180, d0" + - + input: + bytes: [ 0x09, 0x22, 0x84, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a2, [a2]#0x4" + - + input: + bytes: [ 0x19, 0xff, 0x00, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a15]#0x280" + - + input: + bytes: [ 0xb4, 0xaf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp], d15" + - + input: + bytes: [ 0xac, 0xa1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x2, d15" + - + input: + bytes: [ 0xac, 0xa2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x4, d15" + - + input: + bytes: [ 0xac, 0xa3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x6, d15" + - + input: + bytes: [ 0xb4, 0xa2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp], d2" + - + input: + bytes: [ 0x89, 0xa2, 0x82, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x2, d2" + - + input: + bytes: [ 0x89, 0xa2, 0x84, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x4, d2" + - + input: + bytes: [ 0x89, 0xa2, 0x86, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x6, d2" + - + input: + bytes: [ 0x54, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a2]" + - + input: + bytes: [ 0x09, 0x51, 0x01, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.b d1, [a5+]#0x1" + - + input: + bytes: [ 0x54, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d2, [a2]" + - + input: + bytes: [ 0x74, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a2], d2" + - + input: + bytes: [ 0xc8, 0x1c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a12, [a15]#0x4" + - + input: + bytes: [ 0xc8, 0x2d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a13, [a15]#0x8" + - + input: + bytes: [ 0x48, 0x3c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d12, [a15]#0xc" + - + input: + bytes: [ 0x09, 0xff, 0x10, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a15+]#0x10" + - + input: + bytes: [ 0x04, 0xdf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a13+]" + - + input: + bytes: [ 0x24, 0xcf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a12+], d15" + - + input: + bytes: [ 0x44, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d1, [a2+]" + - + input: + bytes: [ 0x64, 0xc1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a12+], d1" + - + input: + bytes: [ 0x24, 0xc9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a12+], d9" + - + input: + bytes: [ 0x64, 0xca ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a12+], d10" + - + input: + bytes: [ 0x24, 0xcb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a12+], d11" + - + input: + bytes: [ 0x64, 0xc8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a12+], d8" diff --git a/tests/MC/TriCore/csfr.s.yaml b/tests/MC/TriCore/csfr.s.yaml new file mode 100644 index 0000000000..32536893fc --- /dev/null +++ b/tests/MC/TriCore/csfr.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0xcd, 0x41, 0xe0, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mtcr #-0x1fc, d1" + - + input: + bytes: [ 0x4d, 0x40, 0xe0, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mfcr d2, #0xfe04" diff --git a/tests/MC/TriCore/debug.s.yaml b/tests/MC/TriCore/debug.s.yaml new file mode 100644 index 0000000000..add2ee7297 --- /dev/null +++ b/tests/MC/TriCore/debug.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x4b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cmp.f d0, d0, d0" diff --git a/tests/MC/TriCore/extr_u.s.yaml b/tests/MC/TriCore/extr_u.s.yaml new file mode 100644 index 0000000000..721c1728d6 --- /dev/null +++ b/tests/MC/TriCore/extr_u.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0x17, 0x01, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "extr d0, d1, e2" + - + input: + bytes: [ 0x17, 0x01, 0x60, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "extr.u d0, d1, e2" diff --git a/tests/MC/TriCore/handwrite.s.yaml b/tests/MC/TriCore/handwrite.s.yaml new file mode 100644 index 0000000000..2faf1fc7f4 --- /dev/null +++ b/tests/MC/TriCore/handwrite.s.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0x81 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d8, d15, #0x3f" diff --git a/tests/MC/TriCore/iLLD_TC375_ADS_Bluetooth_RFCOMM.s.yaml b/tests/MC/TriCore/iLLD_TC375_ADS_Bluetooth_RFCOMM.s.yaml new file mode 100644 index 0000000000..0453ebb8ac --- /dev/null +++ b/tests/MC/TriCore/iLLD_TC375_ADS_Bluetooth_RFCOMM.s.yaml @@ -0,0 +1,23563 @@ +test_cases: + - + input: + bytes: [ 0x7e, 0xaa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d10, #0x14" + - + input: + bytes: [ 0x6d, 0xff, 0x75, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x116" + - + input: + bytes: [ 0xa2, 0x8f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d15, d8" + - + input: + bytes: [ 0x1d, 0x00, 0x8c, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x318" + - + input: + bytes: [ 0xc2, 0x34 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d4, #0x3" + - + input: + bytes: [ 0x0b, 0x15, 0x90, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.lt d15, d5, d1" + - + input: + bytes: [ 0x0b, 0xa8, 0x10, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e4, d8, d10" + - + input: + bytes: [ 0x6d, 0xff, 0x83, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xfa" + - + input: + bytes: [ 0x6f, 0x9a, 0x0e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d10, #0x9, #0x1c" + - + input: + bytes: [ 0xbb, 0xf0, 0xfe, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d0, #0xffef" + - + input: + bytes: [ 0xd9, 0x44, 0xa8, 0x9a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#-0x5598" + - + input: + bytes: [ 0x8c, 0xa6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d15, [sp]#0xc" + - + input: + bytes: [ 0x6b, 0x0c, 0x31, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.f d15, d5, d12" + - + input: + bytes: [ 0xce, 0x57 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jgez d5, #0xe" + - + input: + bytes: [ 0x91, 0x40, 0x00, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0xf004" + - + input: + bytes: [ 0x61, 0xff, 0x3a, 0xda ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x4b8c" + - + input: + bytes: [ 0x02, 0xa4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d10" + - + input: + bytes: [ 0x3f, 0xf0, 0xfd, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, d15, #-0x6" + - + input: + bytes: [ 0x0b, 0x0f, 0x90, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min.u d15, d15, d0" + - + input: + bytes: [ 0x6f, 0x0a, 0x0e, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d10, #0, #0x1c" + - + input: + bytes: [ 0x89, 0x4f, 0xa4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a4]#0x24, d15" + - + input: + bytes: [ 0x37, 0x04, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d0, d4, #0, #0x10" + - + input: + bytes: [ 0x3c, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x46" + - + input: + bytes: [ 0x40, 0xde ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a14, a13" + - + input: + bytes: [ 0x9b, 0x14, 0x00, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d4, d4, #0x1" + - + input: + bytes: [ 0x6f, 0x08, 0x18, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d8, #0, #0x30" + - + input: + bytes: [ 0x37, 0x0f, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d15, #0, #0x10" + - + input: + bytes: [ 0xfe, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x26" + - + input: + bytes: [ 0x6d, 0xff, 0xe1, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xa3e" + - + input: + bytes: [ 0x3b, 0x50, 0x04, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, #0x45" + - + input: + bytes: [ 0x1a, 0x89 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d9, d8" + - + input: + bytes: [ 0x8f, 0x24, 0x40, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d4, #0x2" + - + input: + bytes: [ 0xee, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x1c" + - + input: + bytes: [ 0x2e, 0x37 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x3, #0xe" + - + input: + bytes: [ 0x6e, 0x1d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x3a" + - + input: + bytes: [ 0xae, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0, #0x8" + - + input: + bytes: [ 0x2e, 0x1c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x1, #0x18" + - + input: + bytes: [ 0x40, 0xa4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a4, sp" + - + input: + bytes: [ 0x4b, 0xbf, 0x01, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmp.f d15, d15, d11" + - + input: + bytes: [ 0x02, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, d1" + - + input: + bytes: [ 0x0b, 0x1b, 0x80, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.ne d15, d11, d1" + - + input: + bytes: [ 0xd9, 0x99, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a9, [a9]#0" + - + input: + bytes: [ 0x3c, 0x94 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0xd8" + - + input: + bytes: [ 0x0b, 0xab, 0x10, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e4, d11, d10" + - + input: + bytes: [ 0xfe, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x2c" + - + input: + bytes: [ 0x3c, 0x18 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x30" + - + input: + bytes: [ 0x02, 0x94 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d9" + - + input: + bytes: [ 0x6d, 0xff, 0x53, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x15a" + - + input: + bytes: [ 0x6d, 0xff, 0x09, 0x4c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x167ee" + - + input: + bytes: [ 0x6d, 0xff, 0x5b, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xb4a" + - + input: + bytes: [ 0xae, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0x1, #0xe" + - + input: + bytes: [ 0x3c, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x32" + - + input: + bytes: [ 0x3c, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x18" + - + input: + bytes: [ 0x37, 0x00, 0x50, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d8, d0, #0, #0x10" + - + input: + bytes: [ 0xac, 0x42 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a4]#0x4, d15" + - + input: + bytes: [ 0xa2, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d0, d15" + - + input: + bytes: [ 0xd9, 0x55, 0xa0, 0xca ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x54e0" + - + input: + bytes: [ 0xdf, 0x02, 0xee, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d2, #0, #-0x24" + - + input: + bytes: [ 0x49, 0xa2, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [sp]#0" + - + input: + bytes: [ 0x67, 0x23, 0x80, 0x3f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ins.t d3, d3, #0, d2, #0x1f" + - + input: + bytes: [ 0x82, 0x15 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d5, #0x1" + - + input: + bytes: [ 0x3b, 0x90, 0xd0, 0x33 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d3, #0x3d09" + - + input: + bytes: [ 0x8f, 0x00, 0x01, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d0, d0, #0x10" + - + input: + bytes: [ 0x7d, 0xe2, 0x0a, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne.a a2, a14, #0x14" + - + input: + bytes: [ 0x3b, 0x00, 0x04, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x1040" + - + input: + bytes: [ 0xee, 0x2b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x56" + - + input: + bytes: [ 0x0b, 0x27, 0x00, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.eq d15, d7, d2" + - + input: + bytes: [ 0x8c, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d15, [a4]#0x12" + - + input: + bytes: [ 0xbb, 0x00, 0x68, 0x89 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d8, #0x9680" + - + input: + bytes: [ 0x5f, 0x0f, 0xad, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x15a" + - + input: + bytes: [ 0x6d, 0xff, 0x2a, 0x3e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x183ac" + - + input: + bytes: [ 0x49, 0xf4, 0x04, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a15]#0x4" + - + input: + bytes: [ 0x0e, 0xa4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jltz d10, #0x8" + - + input: + bytes: [ 0x88, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d0, [a15]#0x4" + - + input: + bytes: [ 0x1d, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x178" + - + input: + bytes: [ 0x8f, 0x0a, 0x44, 0xa1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d10, d10, #0x40" + - + input: + bytes: [ 0x7e, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x1a" + - + input: + bytes: [ 0xa0, 0xa4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a4, #0xa" + - + input: + bytes: [ 0x6d, 0xff, 0x67, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x132" + - + input: + bytes: [ 0x9a, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d11, #-0x1" + - + input: + bytes: [ 0x02, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, d0" + - + input: + bytes: [ 0x6d, 0xff, 0x06, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x13f4" + - + input: + bytes: [ 0x0b, 0xd1, 0xd0, 0xd0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "subc d13, d1, d13" + - + input: + bytes: [ 0x8b, 0x05, 0xa0, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addc d5, d5, #0" + - + input: + bytes: [ 0x49, 0xff, 0x20, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x20" + - + input: + bytes: [ 0x8f, 0xbf, 0x0f, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d15, #0xfb" + - + input: + bytes: [ 0xae, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0x2, #0x10" + - + input: + bytes: [ 0x6d, 0x00, 0x1d, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xa3a" + - + input: + bytes: [ 0x49, 0xa6, 0x04, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a6, [sp]#0x4" + - + input: + bytes: [ 0x8b, 0xf0, 0x20, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min.u d0, d0, #0xf" + - + input: + bytes: [ 0x6d, 0xff, 0x85, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x4f6" + - + input: + bytes: [ 0x6d, 0xff, 0x55, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x356" + - + input: + bytes: [ 0x02, 0xab ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d11, d10" + - + input: + bytes: [ 0x8b, 0x0f, 0x01, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq d15, d15, #0x10" + - + input: + bytes: [ 0x5e, 0x2b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x2, #0x16" + - + input: + bytes: [ 0x89, 0xff, 0xb6, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a15]#0x36, d15" + - + input: + bytes: [ 0xb7, 0x1a, 0x81, 0xa5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d10, d10, #0x1, #0xb, #0x1" + - + input: + bytes: [ 0x53, 0xcf, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d15, #0xc" + - + input: + bytes: [ 0x6b, 0x0c, 0x31, 0xa5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.f d10, d5, d12" + - + input: + bytes: [ 0x8b, 0x01, 0x03, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d4, d1, #0x30" + - + input: + bytes: [ 0x4b, 0xf1, 0x41, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d1, d1, d15" + - + input: + bytes: [ 0x6d, 0x00, 0x03, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x6" + - + input: + bytes: [ 0x6d, 0x00, 0x07, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x280e" + - + input: + bytes: [ 0xab, 0x0f, 0x83, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sel d4, d1, d15, #0x30" + - + input: + bytes: [ 0x6d, 0x00, 0x1a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x34" + - + input: + bytes: [ 0x3f, 0xf0, 0xf6, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, d15, #-0x14" + - + input: + bytes: [ 0xde, 0x25 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x2, #0x2a" + - + input: + bytes: [ 0xd9, 0xff, 0x0c, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x4c" + - + input: + bytes: [ 0xb0, 0xc4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a4, #-0x4" + - + input: + bytes: [ 0x82, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x2" + - + input: + bytes: [ 0xda, 0x39 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x39" + - + input: + bytes: [ 0xab, 0x1f, 0x20, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "caddn d10, d0, d15, #0x1" + - + input: + bytes: [ 0x10, 0x25 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a5, a2, d15, #0" + - + input: + bytes: [ 0x89, 0x4f, 0xae, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a4]#0x2e, d15" + - + input: + bytes: [ 0x09, 0xd4, 0xb4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d4, [a13]#0x34" + - + input: + bytes: [ 0xd9, 0x55, 0x9c, 0xea ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5464" + - + input: + bytes: [ 0x01, 0xf9, 0x00, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a15, d9, #0" + - + input: + bytes: [ 0x82, 0x44 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x4" + - + input: + bytes: [ 0xd9, 0xee, 0xaa, 0x60 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a14, [a14]#0x9aa" + - + input: + bytes: [ 0x5e, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0xe" + - + input: + bytes: [ 0x49, 0xcf, 0x04, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a12]#0x4" + - + input: + bytes: [ 0xdf, 0x0c, 0x1d, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d12, #0, #0x3a" + - + input: + bytes: [ 0x6d, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x178" + - + input: + bytes: [ 0xdf, 0x04, 0x7c, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d4, #0, #-0x108" + - + input: + bytes: [ 0x09, 0xf0, 0xd8, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a15]#0x18" + - + input: + bytes: [ 0x87, 0x55, 0xbf, 0xdf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.t d13, d5, #0x1f, d5, #0x1f" + - + input: + bytes: [ 0x6d, 0xff, 0x0f, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x9e2" + - + input: + bytes: [ 0x8f, 0x89, 0x01, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d9, #0x18" + - + input: + bytes: [ 0x6f, 0x0f, 0xfc, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #-0x8" + - + input: + bytes: [ 0x6d, 0x00, 0xd0, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x11a0" + - + input: + bytes: [ 0x49, 0xa6, 0x00, 0x4a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a6, [sp]#0x100" + - + input: + bytes: [ 0x4b, 0x0f, 0x41, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d15, d15, d0" + - + input: + bytes: [ 0x3c, 0x38 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x70" + - + input: + bytes: [ 0xd9, 0x55, 0x48, 0x4a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5af8" + - + input: + bytes: [ 0xc5, 0xf5, 0x80, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, #0xf0000900" + - + input: + bytes: [ 0xd9, 0x55, 0x64, 0x8a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x59dc" + - + input: + bytes: [ 0x82, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, #0x1" + - + input: + bytes: [ 0xb7, 0x08, 0x01, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d8, #0, #0, #0x1" + - + input: + bytes: [ 0xd9, 0xff, 0x80, 0xc5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x5b00" + - + input: + bytes: [ 0x3b, 0x20, 0xfe, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #-0x1e" + - + input: + bytes: [ 0x6d, 0x00, 0x9b, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2336" + - + input: + bytes: [ 0xb7, 0x04, 0x02, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d4, #0, #0, #0x2" + - + input: + bytes: [ 0x0b, 0x60, 0x40, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addx d8, d0, d6" + - + input: + bytes: [ 0x6d, 0xff, 0x6c, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1528" + - + input: + bytes: [ 0x40, 0xcd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a13, a12" + - + input: + bytes: [ 0x6d, 0x00, 0x4a, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x294" + - + input: + bytes: [ 0x89, 0xaf, 0xa0, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x20, d15" + - + input: + bytes: [ 0x49, 0x25, 0x01, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a2]#0x1" + - + input: + bytes: [ 0xbf, 0x10, 0x22, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d0, #0x1, #0x44" + - + input: + bytes: [ 0x1e, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #-0x1, #0x10" + - + input: + bytes: [ 0x89, 0x4f, 0xa2, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a4]#0x22, d15" + - + input: + bytes: [ 0x96, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x2" + - + input: + bytes: [ 0x6d, 0xff, 0xf2, 0x38 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x18e1c" + - + input: + bytes: [ 0x5f, 0x0f, 0x23, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x46" + - + input: + bytes: [ 0x8b, 0x00, 0x01, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq d0, d0, #0x10" + - + input: + bytes: [ 0x6e, 0x36 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x6c" + - + input: + bytes: [ 0x7b, 0x00, 0x00, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d1, #0x1000" + - + input: + bytes: [ 0x6d, 0x00, 0x9b, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x536" + - + input: + bytes: [ 0xdf, 0x10, 0x2b, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d0, #0x1, #0x56" + - + input: + bytes: [ 0x6d, 0x00, 0xfd, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x5fa" + - + input: + bytes: [ 0x8b, 0x16, 0x80, 0x60 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addx d6, d6, #0x1" + - + input: + bytes: [ 0x4b, 0xf1, 0x51, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d2, d1, d15" + - + input: + bytes: [ 0x40, 0x42 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a2, a4" + - + input: + bytes: [ 0x6e, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #-0x1a" + - + input: + bytes: [ 0xda, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0xa" + - + input: + bytes: [ 0x6d, 0xff, 0x1a, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3cc" + - + input: + bytes: [ 0x5e, 0x15 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0xa" + - + input: + bytes: [ 0x6d, 0x00, 0x1f, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x223e" + - + input: + bytes: [ 0xd9, 0x3f, 0x10, 0x18 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a3]#-0x7fb0" + - + input: + bytes: [ 0x49, 0xf2, 0x3f, 0x2a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a15]#0xbf" + - + input: + bytes: [ 0xbf, 0x1f, 0x13, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d15, #0x1, #0x26" + - + input: + bytes: [ 0x82, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d5, #0" + - + input: + bytes: [ 0x89, 0xa2, 0x80, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x100, d2" + - + input: + bytes: [ 0x9b, 0x88, 0xb9, 0x84 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d8, d8, #0x4b98" + - + input: + bytes: [ 0x09, 0x40, 0xc6, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a4]#0x6" + - + input: + bytes: [ 0x82, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0" + - + input: + bytes: [ 0x20, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.a sp, #0x20" + - + input: + bytes: [ 0xc2, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, #0x1" + - + input: + bytes: [ 0x6d, 0x00, 0x22, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1e44" + - + input: + bytes: [ 0xee, 0xc4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0x78" + - + input: + bytes: [ 0x0b, 0x89, 0x10, 0x68 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e6, d9, d8" + - + input: + bytes: [ 0xd9, 0xff, 0x50, 0xca ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x58f0" + - + input: + bytes: [ 0x5f, 0x5f, 0xfd, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d5, #-0x6" + - + input: + bytes: [ 0x6d, 0xff, 0x1d, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x13c6" + - + input: + bytes: [ 0x49, 0xa6, 0x08, 0x4a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a6, [sp]#0x108" + - + input: + bytes: [ 0x92, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d9, d15, #0x4" + - + input: + bytes: [ 0x94, 0xd4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d4, [a13]" + - + input: + bytes: [ 0x8f, 0x89, 0x01, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d9, #0x18" + - + input: + bytes: [ 0x0b, 0xf4, 0x80, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min d15, d4, d15" + - + input: + bytes: [ 0xbf, 0x10, 0xfa, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, #0x1, #-0xc" + - + input: + bytes: [ 0xfe, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x24" + - + input: + bytes: [ 0xa6, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d1, d15" + - + input: + bytes: [ 0x49, 0xff, 0x10, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x10" + - + input: + bytes: [ 0x91, 0x10, 0x00, 0xa5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a sp, #0x5001" + - + input: + bytes: [ 0xd9, 0x55, 0x64, 0x5a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5a9c" + - + input: + bytes: [ 0xbb, 0x00, 0xc2, 0x2b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d2, #0xbc20" + - + input: + bytes: [ 0x6f, 0x3f, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x3, #0x60" + - + input: + bytes: [ 0x16, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0x1f" + - + input: + bytes: [ 0xd9, 0xff, 0xa4, 0xda ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x549c" + - + input: + bytes: [ 0x8f, 0x3c, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d12, #0x3" + - + input: + bytes: [ 0x8b, 0x0f, 0x20, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne d0, d15, #0" + - + input: + bytes: [ 0x1e, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0x1, #0xe" + - + input: + bytes: [ 0xd9, 0xff, 0x28, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x28" + - + input: + bytes: [ 0x3f, 0x89, 0xd6, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d9, d8, #-0x54" + - + input: + bytes: [ 0x76, 0x43 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d4, #0x6" + - + input: + bytes: [ 0x3f, 0xfa, 0xf9, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d10, d15, #-0xe" + - + input: + bytes: [ 0x82, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #-0x1" + - + input: + bytes: [ 0x0b, 0x51, 0x50, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addc d3, d1, d5" + - + input: + bytes: [ 0x94, 0xd0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d0, [a13]" + - + input: + bytes: [ 0x82, 0x18 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, #0x1" + - + input: + bytes: [ 0x8b, 0x6f, 0x1c, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d15, #-0x3a" + - + input: + bytes: [ 0x12, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d15, d5" + - + input: + bytes: [ 0xb7, 0x0f, 0x81, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0x3, #0x1" + - + input: + bytes: [ 0x67, 0xff, 0xbf, 0xaf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insn.t d10, d15, #0x1f, d15, #0x1f" + - + input: + bytes: [ 0x53, 0x44, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d4, #0x4" + - + input: + bytes: [ 0xd9, 0x22, 0x80, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#-0x3800" + - + input: + bytes: [ 0x0b, 0xa0, 0x50, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ge.u d15, d0, d10" + - + input: + bytes: [ 0xc2, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, #0x2" + - + input: + bytes: [ 0x7f, 0x1f, 0x04, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d15, d1, #0x8" + - + input: + bytes: [ 0x40, 0x4d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a13, a4" + - + input: + bytes: [ 0xce, 0x84 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jgez d8, #0x8" + - + input: + bytes: [ 0x3f, 0x89, 0xb8, 0x7e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d9, d8, #-0x290" + - + input: + bytes: [ 0x26, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d10, d0" + - + input: + bytes: [ 0xd9, 0x44, 0x24, 0xc0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x324" + - + input: + bytes: [ 0x3f, 0x10, 0x97, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, d1, #-0xd2" + - + input: + bytes: [ 0x5e, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x14" + - + input: + bytes: [ 0x6d, 0xff, 0x22, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x15bc" + - + input: + bytes: [ 0xdf, 0x0f, 0xdf, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0, #0x1be" + - + input: + bytes: [ 0x1d, 0x00, 0x9e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x13c" + - + input: + bytes: [ 0x02, 0xd8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, d13" + - + input: + bytes: [ 0x0b, 0x23, 0x10, 0xa8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e10, d3, d2" + - + input: + bytes: [ 0xee, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x12" + - + input: + bytes: [ 0x6d, 0xff, 0x7a, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x110c" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x2000" + - + input: + bytes: [ 0xb7, 0x1a, 0x01, 0xa6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d10, d10, #0x1, #0xc, #0x1" + - + input: + bytes: [ 0x1d, 0xff, 0xb5, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x496" + - + input: + bytes: [ 0x49, 0xc2, 0x0c, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a12]#0xc" + - + input: + bytes: [ 0x49, 0xa2, 0x13, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [sp]#0x13" + - + input: + bytes: [ 0x2e, 0x25 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x2, #0xa" + - + input: + bytes: [ 0x61, 0xff, 0xe0, 0xd9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x4c40" + - + input: + bytes: [ 0x01, 0xc8, 0x00, 0xe6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a14, a12, d8, #0" + - + input: + bytes: [ 0x49, 0x40, 0x40, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ldmst [a4]#0, e0" + - + input: + bytes: [ 0x0f, 0x0f, 0xb0, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "clz d15, d15" + - + input: + bytes: [ 0x6d, 0x00, 0x5f, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x14be" + - + input: + bytes: [ 0xd9, 0xff, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x6400" + - + input: + bytes: [ 0xf6, 0xa6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d10, #0xc" + - + input: + bytes: [ 0x40, 0x2e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a14, a2" + - + input: + bytes: [ 0xda, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x80" + - + input: + bytes: [ 0x4b, 0x01, 0x71, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftouz d1, d1" + - + input: + bytes: [ 0xdf, 0x02, 0x12, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d2, #0, #0x24" + - + input: + bytes: [ 0x4b, 0x0a, 0x01, 0x82 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div e8, d10, d0" + - + input: + bytes: [ 0x3b, 0xc0, 0x04, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d5, #0x4c" + - + input: + bytes: [ 0x02, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d5, d15" + - + input: + bytes: [ 0x3c, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x6" + - + input: + bytes: [ 0xd9, 0x55, 0x74, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5bcc" + - + input: + bytes: [ 0x6d, 0x00, 0xdd, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x5ba" + - + input: + bytes: [ 0x8b, 0xfe, 0x26, 0x82 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne d8, d14, #0x6f" + - + input: + bytes: [ 0x8f, 0x3f, 0x00, 0xd1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d13, d15, #0x3" + - + input: + bytes: [ 0x10, 0xcc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a12, a12, d15, #0" + - + input: + bytes: [ 0x3b, 0x90, 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x69" + - + input: + bytes: [ 0x3b, 0x60, 0x04, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #0x46" + - + input: + bytes: [ 0x3c, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x4c" + - + input: + bytes: [ 0x3b, 0xe0, 0x02, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x2e" + - + input: + bytes: [ 0x3e, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x6" + - + input: + bytes: [ 0x6d, 0x00, 0x37, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x6e" + - + input: + bytes: [ 0x8b, 0x10, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addx d0, d0, #0x1" + - + input: + bytes: [ 0x6d, 0x00, 0x48, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x90" + - + input: + bytes: [ 0x40, 0x6c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a12, a6" + - + input: + bytes: [ 0x6d, 0x00, 0x36, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x6c" + - + input: + bytes: [ 0x49, 0x55, 0x00, 0x2a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#0x80" + - + input: + bytes: [ 0x6d, 0xff, 0x6c, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1728" + - + input: + bytes: [ 0x0b, 0x71, 0x00, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.eq d15, d1, d7" + - + input: + bytes: [ 0x6d, 0xff, 0x16, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3d4" + - + input: + bytes: [ 0x37, 0x0f, 0x04, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0, #0x4" + - + input: + bytes: [ 0x01, 0xc0, 0x00, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, a12, d0, #0" + - + input: + bytes: [ 0x49, 0xa2, 0x0a, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [sp]#0xa" + - + input: + bytes: [ 0x0b, 0x54, 0x10, 0x88 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e8, d4, d5" + - + input: + bytes: [ 0x6d, 0x00, 0x5e, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x22bc" + - + input: + bytes: [ 0x4b, 0x0f, 0x51, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d15, d15, d0" + - + input: + bytes: [ 0x5f, 0x0f, 0xc4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x188" + - + input: + bytes: [ 0x6d, 0x00, 0x34, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2268" + - + input: + bytes: [ 0x3b, 0xc0, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x4c" + - + input: + bytes: [ 0x6e, 0xef ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #-0x22" + - + input: + bytes: [ 0x01, 0xf0, 0x00, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a15, d0, #0" + - + input: + bytes: [ 0x49, 0xa5, 0x08, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [sp]#0x8" + - + input: + bytes: [ 0x49, 0xaf, 0x12, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [sp]#0x12" + - + input: + bytes: [ 0x7f, 0xfa, 0x1d, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d10, d15, #0x3a" + - + input: + bytes: [ 0xbb, 0xf0, 0xfd, 0xaf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d10, #0xffdf" + - + input: + bytes: [ 0x5f, 0x0f, 0x27, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x4e" + - + input: + bytes: [ 0x40, 0x5d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a13, a5" + - + input: + bytes: [ 0xdf, 0x12, 0x49, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d2, #0x1, #0x92" + - + input: + bytes: [ 0xbf, 0x10, 0x13, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, #0x1, #0x26" + - + input: + bytes: [ 0x49, 0xff, 0x04, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x4" + - + input: + bytes: [ 0x5f, 0x01, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d1, d0, #0x8" + - + input: + bytes: [ 0x8b, 0x61, 0x09, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsub d1, d1, #0x96" + - + input: + bytes: [ 0xdf, 0x04, 0x11, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d4, #0, #0x22" + - + input: + bytes: [ 0xb0, 0x15 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a5, #0x1" + - + input: + bytes: [ 0xd9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a0, [a0]#0" + - + input: + bytes: [ 0x01, 0xf2, 0x20, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt.a d15, a2, a15" + - + input: + bytes: [ 0x6f, 0x08, 0xe2, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d8, #0, #-0x3c" + - + input: + bytes: [ 0xd9, 0xff, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x4" + - + input: + bytes: [ 0x37, 0x0f, 0x81, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x1, #0x1" + - + input: + bytes: [ 0x82, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x4" + - + input: + bytes: [ 0x6d, 0x00, 0x8f, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x11e" + - + input: + bytes: [ 0x3b, 0xa0, 0x00, 0x60 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d6, #0xa" + - + input: + bytes: [ 0x6d, 0x00, 0x3b, 0x18 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x3076" + - + input: + bytes: [ 0x3e, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0xc" + - + input: + bytes: [ 0x40, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a5, a15" + - + input: + bytes: [ 0x6d, 0x00, 0x9e, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xf3c" + - + input: + bytes: [ 0x3b, 0x90, 0x00, 0xb0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d11, #0x9" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0" + - + input: + bytes: [ 0x6f, 0x29, 0x09, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d9, #0x2, #0x12" + - + input: + bytes: [ 0x16, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0x3" + - + input: + bytes: [ 0x8b, 0x01, 0x01, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsub d1, d1, #0x10" + - + input: + bytes: [ 0x76, 0x33 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d3, #0x6" + - + input: + bytes: [ 0x3b, 0x50, 0x06, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #0x65" + - + input: + bytes: [ 0xbe, 0xe4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d14, #0x28" + - + input: + bytes: [ 0xff, 0x14, 0xea, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d4, #0x1, #-0x2c" + - + input: + bytes: [ 0xf6, 0x82 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d8, #0x4" + - + input: + bytes: [ 0x02, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d0" + - + input: + bytes: [ 0x6d, 0x00, 0x8a, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x514" + - + input: + bytes: [ 0x3e, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x1a" + - + input: + bytes: [ 0x6d, 0x00, 0x85, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x50a" + - + input: + bytes: [ 0xc2, 0xcb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d11, #-0x4" + - + input: + bytes: [ 0x3f, 0xbc, 0xf9, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d12, d11, #-0xe" + - + input: + bytes: [ 0x1d, 0xff, 0x77, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x112" + - + input: + bytes: [ 0x6d, 0x00, 0x7c, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x6f8" + - + input: + bytes: [ 0x23, 0x82, 0x0a, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub d0, d10, d2, d8" + - + input: + bytes: [ 0x8b, 0x02, 0x00, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq d2, d2, #0" + - + input: + bytes: [ 0x6d, 0x00, 0x7a, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x22f4" + - + input: + bytes: [ 0x6d, 0xff, 0xd4, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x58" + - + input: + bytes: [ 0x49, 0xf4, 0x08, 0x5a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a15]#0x148" + - + input: + bytes: [ 0xdf, 0x09, 0x14, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d9, #0, #0x28" + - + input: + bytes: [ 0x4b, 0x0d, 0x61, 0xa1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "utof d10, d13" + - + input: + bytes: [ 0xff, 0xdf, 0x6f, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d15, #-0x3, #0xde" + - + input: + bytes: [ 0x8b, 0x02, 0x03, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d2, #0x30" + - + input: + bytes: [ 0x49, 0xff, 0x08, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x8" + - + input: + bytes: [ 0x6f, 0x9a, 0x05, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d10, #0x9, #0xa" + - + input: + bytes: [ 0x3c, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x1e" + - + input: + bytes: [ 0x37, 0xf0, 0x01, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0x2, #0x1" + - + input: + bytes: [ 0x26, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d2, d0" + - + input: + bytes: [ 0x3f, 0xbf, 0x03, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d15, d11, #0x6" + - + input: + bytes: [ 0x26, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d10" + - + input: + bytes: [ 0x9b, 0xc0, 0xfc, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d0, d0, #0x3fcc" + - + input: + bytes: [ 0x5f, 0x0f, 0x37, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x6e" + - + input: + bytes: [ 0xf6, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d2, #0x6" + - + input: + bytes: [ 0xdf, 0x05, 0x12, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d5, #0, #0x24" + - + input: + bytes: [ 0x8f, 0x29, 0x00, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d9, #0x2" + - + input: + bytes: [ 0x8f, 0x24, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, d4, #0x2" + - + input: + bytes: [ 0xd2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e0, #0" + - + input: + bytes: [ 0x0f, 0x0a, 0x00, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d10, d0" + - + input: + bytes: [ 0x02, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, d15" + - + input: + bytes: [ 0x89, 0x45, 0x96, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a4]#0x16, d5" + - + input: + bytes: [ 0xd9, 0x22, 0x28, 0xa6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x62a8" + - + input: + bytes: [ 0x61, 0xff, 0xcd, 0xd4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x5666" + - + input: + bytes: [ 0x02, 0x6a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d10, d6" + - + input: + bytes: [ 0x52, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d0, d15, d0" + - + input: + bytes: [ 0x49, 0x4f, 0x08, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a4]#0x48" + - + input: + bytes: [ 0xbf, 0x1f, 0x5c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d15, #0x1, #0xb8" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "abss d0, d0" + - + input: + bytes: [ 0x3c, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x8" + - + input: + bytes: [ 0x7e, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d1, #0x4" + - + input: + bytes: [ 0xa6, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d2, d1" + - + input: + bytes: [ 0x49, 0xfd, 0x08, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a13, [a15]#0x8" + - + input: + bytes: [ 0x37, 0xf0, 0x01, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0, #0x1" + - + input: + bytes: [ 0xee, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x22" + - + input: + bytes: [ 0x6d, 0x00, 0x96, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x12c" + - + input: + bytes: [ 0x37, 0x0f, 0x62, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0xc, #0x2" + - + input: + bytes: [ 0x7d, 0x24, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq.a a4, a2, #0x8" + - + input: + bytes: [ 0x3b, 0x50, 0x07, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x75" + - + input: + bytes: [ 0xda, 0x5b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x5b" + - + input: + bytes: [ 0xd9, 0xff, 0xa0, 0xea ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x5460" + - + input: + bytes: [ 0x6d, 0xff, 0x2a, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1ac" + - + input: + bytes: [ 0x5f, 0x0f, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x70" + - + input: + bytes: [ 0x6d, 0xff, 0x05, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xbf6" + - + input: + bytes: [ 0x80, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d2, a15" + - + input: + bytes: [ 0x82, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d7, #0" + - + input: + bytes: [ 0x37, 0x00, 0x62, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d0, #0x1c, #0x2" + - + input: + bytes: [ 0xee, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x18" + - + input: + bytes: [ 0x6d, 0x00, 0x71, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x14e2" + - + input: + bytes: [ 0x8b, 0x00, 0x02, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d0, #0x20" + - + input: + bytes: [ 0x02, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, d4" + - + input: + bytes: [ 0x8c, 0x4a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d15, [a4]#0x14" + - + input: + bytes: [ 0x0f, 0x49, 0x10, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d9, d9, d4" + - + input: + bytes: [ 0x37, 0x04, 0x48, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d0, d4, #0, #0x8" + - + input: + bytes: [ 0x1d, 0x00, 0x17, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x22e" + - + input: + bytes: [ 0x6d, 0xff, 0x6f, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x322" + - + input: + bytes: [ 0x91, 0x40, 0x88, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0xf884" + - + input: + bytes: [ 0x3b, 0x00, 0x10, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x100" + - + input: + bytes: [ 0xd9, 0x55, 0x5c, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5be4" + - + input: + bytes: [ 0x60, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a4, d1" + - + input: + bytes: [ 0x46, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "not d3" + - + input: + bytes: [ 0x8b, 0x0f, 0x20, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne d15, d15, #0" + - + input: + bytes: [ 0x37, 0xf0, 0x03, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0, #0x3" + - + input: + bytes: [ 0x8b, 0x1a, 0x60, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "max.u d15, d10, #0x1" + - + input: + bytes: [ 0x8f, 0x0a, 0x02, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d10, #0x20" + - + input: + bytes: [ 0x2e, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x1, #0x16" + - + input: + bytes: [ 0x8f, 0x00, 0x21, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d0, d0, #0x10" + - + input: + bytes: [ 0xbb, 0x00, 0x68, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d15, #0x9680" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x100" + - + input: + bytes: [ 0x6d, 0x00, 0x11, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2222" + - + input: + bytes: [ 0xf6, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d0, #0x4" + - + input: + bytes: [ 0x6f, 0x09, 0x15, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d9, #0, #0x2a" + - + input: + bytes: [ 0x6d, 0x00, 0x06, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xa0c" + - + input: + bytes: [ 0x82, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x2" + - + input: + bytes: [ 0x6d, 0x00, 0xda, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x7b4" + - + input: + bytes: [ 0x02, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d3, d15" + - + input: + bytes: [ 0x16, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0xfb" + - + input: + bytes: [ 0x1d, 0x00, 0x03, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x6" + - + input: + bytes: [ 0x91, 0x20, 0x00, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x8002" + - + input: + bytes: [ 0xb7, 0x04, 0x08, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d4, #0, #0x18, #0x8" + - + input: + bytes: [ 0x7b, 0x80, 0x2c, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d0, #0x42c8" + - + input: + bytes: [ 0x76, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0xe" + - + input: + bytes: [ 0x6d, 0x00, 0xa5, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x434a" + - + input: + bytes: [ 0xd9, 0x44, 0x0c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0xc" + - + input: + bytes: [ 0x6d, 0xff, 0x5e, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x744" + - + input: + bytes: [ 0xd9, 0x22, 0xa4, 0xba ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#-0x551c" + - + input: + bytes: [ 0xd9, 0x44, 0x08, 0xc0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x308" + - + input: + bytes: [ 0x6d, 0xff, 0x0f, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x13e2" + - + input: + bytes: [ 0x3b, 0x80, 0x00, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #0x8" + - + input: + bytes: [ 0x37, 0x04, 0xe8, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d1, d4, #0x17, #0x8" + - + input: + bytes: [ 0xfe, 0xe3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d14, #0x26" + - + input: + bytes: [ 0xd9, 0x55, 0xc0, 0x87 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#0x7e00" + - + input: + bytes: [ 0x6d, 0xff, 0x75, 0x2a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1ab16" + - + input: + bytes: [ 0xee, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x8" + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d2, d15, #0x3f" + - + input: + bytes: [ 0x7b, 0x00, 0x12, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d15, #0x4120" + - + input: + bytes: [ 0x2e, 0x4a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x4, #0x14" + - + input: + bytes: [ 0x6d, 0xff, 0xf4, 0x4b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x16818" + - + input: + bytes: [ 0x91, 0x40, 0x00, 0x27 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0x7004" + - + input: + bytes: [ 0x6d, 0x00, 0x07, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x20e" + - + input: + bytes: [ 0xb7, 0x00, 0x01, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, #0, #0x1" + - + input: + bytes: [ 0x6d, 0xff, 0x22, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3bc" + - + input: + bytes: [ 0x0b, 0x08, 0x10, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne d2, d8, d0" + - + input: + bytes: [ 0x88, 0xaf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d15, [a15]#0x14" + - + input: + bytes: [ 0x37, 0x0f, 0xe7, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x1, #0x7" + - + input: + bytes: [ 0xbb, 0xe0, 0x3c, 0x4b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d4, #0xb3ce" + - + input: + bytes: [ 0xdf, 0x1f, 0x70, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0xe0" + - + input: + bytes: [ 0x8c, 0x42 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d15, [a4]#0x4" + - + input: + bytes: [ 0x26, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d10, d15" + - + input: + bytes: [ 0xdf, 0x04, 0xfb, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d4, #0, #-0xa" + - + input: + bytes: [ 0x6f, 0x1f, 0x12, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x1, #0x24" + - + input: + bytes: [ 0x6d, 0xff, 0x2b, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x13aa" + - + input: + bytes: [ 0x3b, 0x80, 0x05, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x58" + - + input: + bytes: [ 0x6d, 0x00, 0x26, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x224c" + - + input: + bytes: [ 0x7b, 0x00, 0x00, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d15, #0x4000" + - + input: + bytes: [ 0x6d, 0x00, 0x56, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x20ac" + - + input: + bytes: [ 0x01, 0x45, 0x30, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ge.a d15, a5, a4" + - + input: + bytes: [ 0x1d, 0xff, 0xd7, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x452" + - + input: + bytes: [ 0x6d, 0x00, 0x84, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x308" + - + input: + bytes: [ 0x6e, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x20" + - + input: + bytes: [ 0x0f, 0x0a, 0x80, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d10, d0" + - + input: + bytes: [ 0x61, 0xff, 0x02, 0xd9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x4dfc" + - + input: + bytes: [ 0x3c, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x60" + - + input: + bytes: [ 0xab, 0xf0, 0x1f, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cadd d0, d0, d0, #-0x1" + - + input: + bytes: [ 0x6e, 0x3e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x7c" + - + input: + bytes: [ 0xba, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq d15, d15, #0" + - + input: + bytes: [ 0xb7, 0x4f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x4, #0, #0x8" + - + input: + bytes: [ 0x02, 0x5f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, d5" + - + input: + bytes: [ 0xee, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0xe0" + - + input: + bytes: [ 0x6d, 0x00, 0x50, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x22a0" + - + input: + bytes: [ 0x02, 0x9d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d13, d9" + - + input: + bytes: [ 0x1d, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x140" + - + input: + bytes: [ 0x76, 0xdb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d13, #0x16" + - + input: + bytes: [ 0x6d, 0x00, 0xb7, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x76e" + - + input: + bytes: [ 0x37, 0xf0, 0x03, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0, #0x3" + - + input: + bytes: [ 0x8b, 0x0d, 0x00, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.eq d15, d13, #0" + - + input: + bytes: [ 0x61, 0xff, 0x94, 0xd8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x4ed8" + - + input: + bytes: [ 0x6d, 0xff, 0xac, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x4a8" + - + input: + bytes: [ 0x6d, 0x00, 0x36, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1c6c" + - + input: + bytes: [ 0x0b, 0x93, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.eq d0, d3, d9" + - + input: + bytes: [ 0x09, 0xf0, 0x3c, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.q d0, [a15]#-0x4" + - + input: + bytes: [ 0x3c, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xa" + - + input: + bytes: [ 0x0b, 0x04, 0x10, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne d15, d4, d0" + - + input: + bytes: [ 0x02, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, d15" + - + input: + bytes: [ 0xb7, 0x7f, 0x03, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x7, #0x1c, #0x3" + - + input: + bytes: [ 0xdf, 0x1f, 0xfb, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #-0xa" + - + input: + bytes: [ 0x8b, 0x08, 0x00, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq d2, d8, #0" + - + input: + bytes: [ 0x42, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d8, d0" + - + input: + bytes: [ 0x49, 0xa7, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a7, [sp]#0" + - + input: + bytes: [ 0x6d, 0xff, 0xae, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2a4" + - + input: + bytes: [ 0x6d, 0x00, 0x69, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x4d2" + - + input: + bytes: [ 0x6d, 0xff, 0xb8, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x90" + - + input: + bytes: [ 0x4b, 0xf0, 0x51, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d15, d0, d15" + - + input: + bytes: [ 0x6d, 0xff, 0xa1, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xbe" + - + input: + bytes: [ 0xd9, 0xff, 0xcc, 0xaa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x5174" + - + input: + bytes: [ 0x8b, 0x70, 0x00, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min d15, d0, #0x7" + - + input: + bytes: [ 0xbf, 0xa0, 0xf6, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, #0xa, #-0x14" + - + input: + bytes: [ 0x94, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d4, [a15]" + - + input: + bytes: [ 0x46, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "not d1" + - + input: + bytes: [ 0x0b, 0x02, 0x10, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne d15, d2, d0" + - + input: + bytes: [ 0xd9, 0xff, 0x10, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x50" + - + input: + bytes: [ 0x4b, 0xbc, 0x51, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d4, d12, d11" + - + input: + bytes: [ 0xda, 0x69 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x69" + - + input: + bytes: [ 0xdf, 0x2d, 0x0b, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d13, #0x2, #0x16" + - + input: + bytes: [ 0x02, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, d0" + - + input: + bytes: [ 0x3f, 0x0f, 0xf2, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d15, d0, #-0x1c" + - + input: + bytes: [ 0x6d, 0xff, 0xbf, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x482" + - + input: + bytes: [ 0x6d, 0x00, 0x77, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x4ee" + - + input: + bytes: [ 0x37, 0x0f, 0x02, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x4, #0x2" + - + input: + bytes: [ 0x61, 0xff, 0x26, 0xd9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x4db4" + - + input: + bytes: [ 0x8f, 0xf4, 0x0f, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d4, #0xff" + - + input: + bytes: [ 0x9b, 0x34, 0x42, 0x4a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d4, d4, #0xa423" + - + input: + bytes: [ 0x01, 0xf4, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.a a15, a4, a15" + - + input: + bytes: [ 0x01, 0xc0, 0x00, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a12, d0, #0" + - + input: + bytes: [ 0x89, 0xff, 0xba, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a15]#0x3a, d15" + - + input: + bytes: [ 0x8e, 0x87 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlez d8, #0xe" + - + input: + bytes: [ 0x3b, 0xc0, 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x6c" + - + input: + bytes: [ 0x40, 0xd4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a4, a13" + - + input: + bytes: [ 0x7b, 0x60, 0x61, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d15, #0x4616" + - + input: + bytes: [ 0xa0, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a4, #0xf" + - + input: + bytes: [ 0x37, 0xf0, 0x83, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0x1, #0x3" + - + input: + bytes: [ 0xa6, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d0, d3" + - + input: + bytes: [ 0x09, 0xff, 0xe2, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d15, [a15]#0x22" + - + input: + bytes: [ 0x37, 0x05, 0x68, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d5, #0x8, #0x8" + - + input: + bytes: [ 0x8f, 0xf8, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d8, #0xf" + - + input: + bytes: [ 0x8b, 0x48, 0x60, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "max.u d15, d8, #0x4" + - + input: + bytes: [ 0x4b, 0xf0, 0x11, 0x42 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.u e4, d0, d15" + - + input: + bytes: [ 0x6d, 0x00, 0xd0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x5a0" + - + input: + bytes: [ 0xbb, 0x00, 0xc2, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d1, #0xbc20" + - + input: + bytes: [ 0x49, 0x24, 0x3e, 0x2a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a2]#0xbe" + - + input: + bytes: [ 0x8f, 0x19, 0x40, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d9, #0x1" + - + input: + bytes: [ 0xae, 0x75 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0x7, #0xa" + - + input: + bytes: [ 0x3f, 0xf8, 0x07, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d8, d15, #0xe" + - + input: + bytes: [ 0x6d, 0xff, 0x16, 0x4c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x167d4" + - + input: + bytes: [ 0xb7, 0x0f, 0x01, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d8, d15, #0, #0, #0x1" + - + input: + bytes: [ 0x49, 0xae, 0x13, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a14, [sp]#0x13" + - + input: + bytes: [ 0x0b, 0x23, 0x10, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e4, d3, d2" + - + input: + bytes: [ 0x8f, 0x10, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d0, #0x1" + - + input: + bytes: [ 0xa6, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d0, d2" + - + input: + bytes: [ 0x91, 0x10, 0x00, 0x25 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0x5001" + - + input: + bytes: [ 0x4b, 0x0f, 0x11, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.u e0, d15, d0" + - + input: + bytes: [ 0xe2, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d0, d1" + - + input: + bytes: [ 0x0b, 0x60, 0xc0, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "subx d10, d0, d6" + - + input: + bytes: [ 0x02, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d12, d0" + - + input: + bytes: [ 0x76, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d1, #0x4" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x8000" + - + input: + bytes: [ 0x02, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d6, d15" + - + input: + bytes: [ 0xb7, 0x00, 0x81, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, #0x3, #0x1" + - + input: + bytes: [ 0x8f, 0x2a, 0x40, 0xa1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d10, d10, #0x2" + - + input: + bytes: [ 0x3b, 0xe0, 0x02, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x2e" + - + input: + bytes: [ 0xfc, 0x5e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a5, #-0x4" + - + input: + bytes: [ 0x26, 0x51 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d1, d5" + - + input: + bytes: [ 0x3b, 0xb0, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0xb" + - + input: + bytes: [ 0x6d, 0xff, 0x2c, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1a8" + - + input: + bytes: [ 0x92, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d15, #0x3" + - + input: + bytes: [ 0xa2, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d15, d0" + - + input: + bytes: [ 0x3c, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x22" + - + input: + bytes: [ 0x3e, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x14" + - + input: + bytes: [ 0x3c, 0x1e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x3c" + - + input: + bytes: [ 0xfe, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x22" + - + input: + bytes: [ 0x0b, 0x1d, 0x00, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.eq d15, d13, d1" + - + input: + bytes: [ 0x6d, 0x00, 0x95, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x52a" + - + input: + bytes: [ 0x6d, 0xff, 0xf9, 0x2b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1a80e" + - + input: + bytes: [ 0xb7, 0x1a, 0x81, 0xa4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d10, d10, #0x1, #0x9, #0x1" + - + input: + bytes: [ 0x6d, 0xff, 0x66, 0x35 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x19534" + - + input: + bytes: [ 0x4b, 0x12, 0x01, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div e2, d2, d1" + - + input: + bytes: [ 0x06, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d0, #-0x1" + - + input: + bytes: [ 0x37, 0x0f, 0x68, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0, #0x8" + - + input: + bytes: [ 0x6d, 0x00, 0x87, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x10e" + - + input: + bytes: [ 0x07, 0x57, 0xff, 0xcf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor.t d12, d7, #0x1f, d5, #0x1f" + - + input: + bytes: [ 0xc2, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d4, #-0x1" + - + input: + bytes: [ 0xf6, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d0, #0xc" + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0x81 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d8, d15, #0x3f" + - + input: + bytes: [ 0x3b, 0x50, 0xeb, 0x56 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d5, #0x6eb5" + - + input: + bytes: [ 0xd9, 0x22, 0x2c, 0x61 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x11ac" + - + input: + bytes: [ 0x6d, 0xff, 0x0c, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x7e8" + - + input: + bytes: [ 0x37, 0x0f, 0xe1, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x5, #0x1" + - + input: + bytes: [ 0x49, 0x2e, 0x0a, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a14, [a2]#0xa" + - + input: + bytes: [ 0x7e, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x4" + - + input: + bytes: [ 0x6d, 0xff, 0x23, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1ba" + - + input: + bytes: [ 0xc6, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d1, d2" + - + input: + bytes: [ 0x5f, 0x0f, 0xd3, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x1a6" + - + input: + bytes: [ 0x8c, 0xa2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d15, [sp]#0x4" + - + input: + bytes: [ 0x6e, 0xc8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #-0x70" + - + input: + bytes: [ 0xb7, 0x0f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0, #0x8" + - + input: + bytes: [ 0x3b, 0x00, 0x03, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x30" + - + input: + bytes: [ 0x01, 0xef, 0x30, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ge.a d15, a15, a14" + - + input: + bytes: [ 0x09, 0xdf, 0xe4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d15, [a13]#0x24" + - + input: + bytes: [ 0x37, 0xf0, 0x02, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0x4, #0x2" + - + input: + bytes: [ 0x89, 0x4f, 0xa0, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a4]#0x20, d15" + - + input: + bytes: [ 0x8f, 0x0a, 0x48, 0xa1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d10, d10, #0x80" + - + input: + bytes: [ 0x37, 0xf0, 0x81, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0x3, #0x1" + - + input: + bytes: [ 0x4b, 0xdf, 0x41, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d4, d15, d13" + - + input: + bytes: [ 0x3c, 0xeb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x2a" + - + input: + bytes: [ 0x49, 0xa4, 0x14, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [sp]#0x14" + - + input: + bytes: [ 0x89, 0x40, 0xc1, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachei.wi [a4+]#0x1" + - + input: + bytes: [ 0x49, 0xf2, 0x40, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ldmst [a15]#0, e2" + - + input: + bytes: [ 0x9b, 0xf9, 0xff, 0x97 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d9, d9, #0x7fff" + - + input: + bytes: [ 0x5f, 0x0a, 0x0b, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d10, d0, #0x16" + - + input: + bytes: [ 0x9a, 0x18 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d8, #0x1" + - + input: + bytes: [ 0x6d, 0x00, 0x81, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2302" + - + input: + bytes: [ 0xa2, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d2, d15" + - + input: + bytes: [ 0x5f, 0x0f, 0x9f, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x13e" + - + input: + bytes: [ 0x6d, 0x00, 0x96, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xd2c" + - + input: + bytes: [ 0x6f, 0x04, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d4, #0, #0x8" + - + input: + bytes: [ 0x96, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x8" + - + input: + bytes: [ 0x8f, 0x3a, 0x00, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d10, #0x3" + - + input: + bytes: [ 0xab, 0xfa, 0x1f, 0xaa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cadd d10, d10, d10, #-0x1" + - + input: + bytes: [ 0x09, 0xf4, 0xb6, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d4, [a15]#0x36" + - + input: + bytes: [ 0x6d, 0xff, 0x29, 0x2c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1a7ae" + - + input: + bytes: [ 0x5f, 0x0f, 0xf9, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #-0xe" + - + input: + bytes: [ 0x02, 0x59 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d9, d5" + - + input: + bytes: [ 0x3b, 0x50, 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x65" + - + input: + bytes: [ 0x6e, 0x75 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0xea" + - + input: + bytes: [ 0x6d, 0x00, 0xa0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xd40" + - + input: + bytes: [ 0x02, 0x42 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, d4" + - + input: + bytes: [ 0x6e, 0xca ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #-0x6c" + - + input: + bytes: [ 0x8b, 0x03, 0x00, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.ne d15, d3, #0" + - + input: + bytes: [ 0x7e, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x1e" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0" + - + input: + bytes: [ 0x37, 0xf0, 0x87, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0x9, #0x7" + - + input: + bytes: [ 0x3f, 0xf8, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d8, d15, #0x8" + - + input: + bytes: [ 0xda, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0xc" + - + input: + bytes: [ 0xa6, 0x51 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d1, d5" + - + input: + bytes: [ 0x4b, 0x52, 0x51, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d0, d2, d5" + - + input: + bytes: [ 0x82, 0x1c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d12, #0x1" + - + input: + bytes: [ 0xc5, 0x02, 0x3f, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, #0x7f" + - + input: + bytes: [ 0x6d, 0xff, 0x5d, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x946" + - + input: + bytes: [ 0xa0, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a15, #0" + - + input: + bytes: [ 0xca, 0x70 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "caddn d0, d15, #0x7" + - + input: + bytes: [ 0x8f, 0xc3, 0x1f, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d1, d3, #-0x4" + - + input: + bytes: [ 0x01, 0x2e, 0x20, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt.a d15, a14, a2" + - + input: + bytes: [ 0x6e, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #-0x14" + - + input: + bytes: [ 0x3c, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x48" + - + input: + bytes: [ 0x09, 0xff, 0xe0, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d15, [a15]#0x20" + - + input: + bytes: [ 0x37, 0x00, 0x62, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d0, #0x14, #0x2" + - + input: + bytes: [ 0x3c, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x9e" + - + input: + bytes: [ 0x3c, 0x56 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xac" + - + input: + bytes: [ 0xf6, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d1, #0x8" + - + input: + bytes: [ 0x3f, 0xfb, 0xf2, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d11, d15, #-0x1c" + - + input: + bytes: [ 0x3b, 0xa0, 0x03, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x3a" + - + input: + bytes: [ 0x8f, 0x2a, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, d10, #0x2" + - + input: + bytes: [ 0x0b, 0x89, 0x80, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min d15, d9, d8" + - + input: + bytes: [ 0xbc, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.a a15, #0x8" + - + input: + bytes: [ 0x6d, 0x00, 0xcc, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x598" + - + input: + bytes: [ 0xda, 0x44 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x44" + - + input: + bytes: [ 0xa0, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a14, #0" + - + input: + bytes: [ 0x53, 0x4f, 0x20, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d4, d15, #0x4" + - + input: + bytes: [ 0xc2, 0x1d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d13, #0x1" + - + input: + bytes: [ 0x37, 0x00, 0x68, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d4, d0, #0, #0x8" + - + input: + bytes: [ 0x6d, 0xff, 0x96, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xcd4" + - + input: + bytes: [ 0x6d, 0x00, 0xc4, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2f88" + - + input: + bytes: [ 0x77, 0x23, 0x00, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "dextr d0, d3, d2, #0x1c" + - + input: + bytes: [ 0x3c, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x24" + - + input: + bytes: [ 0x82, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x1" + - + input: + bytes: [ 0x09, 0xa0, 0xc4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d0, [sp]#0x4" + - + input: + bytes: [ 0x4b, 0x0f, 0x71, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftouz d0, d15" + - + input: + bytes: [ 0x80, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d15, a2" + - + input: + bytes: [ 0x6d, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x200" + - + input: + bytes: [ 0xda, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x41" + - + input: + bytes: [ 0x8b, 0x61, 0x09, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsub d15, d1, #0x96" + - + input: + bytes: [ 0x0b, 0x37, 0x80, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.ne d15, d7, d3" + - + input: + bytes: [ 0x91, 0x30, 0x00, 0x3f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a3, #0xf003" + - + input: + bytes: [ 0x4b, 0x1f, 0x01, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div e2, d15, d1" + - + input: + bytes: [ 0x6d, 0x00, 0xeb, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1d6" + - + input: + bytes: [ 0x92, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d11, d15, #0x1" + - + input: + bytes: [ 0x42, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d9, d15" + - + input: + bytes: [ 0x1d, 0xff, 0xb3, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x9a" + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d1, d15, #0x3f" + - + input: + bytes: [ 0x6d, 0x00, 0x0c, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x618" + - + input: + bytes: [ 0x7b, 0x00, 0x18, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d1, #0x4180" + - + input: + bytes: [ 0x6f, 0x6a, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d10, #0x6, #0x10" + - + input: + bytes: [ 0x6d, 0x00, 0x65, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xaca" + - + input: + bytes: [ 0x4b, 0x12, 0x51, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d1, d2, d1" + - + input: + bytes: [ 0xda, 0x32 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x32" + - + input: + bytes: [ 0xa6, 0x82 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d2, d8" + - + input: + bytes: [ 0x06, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, #0x1" + - + input: + bytes: [ 0x37, 0x0f, 0x01, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x1e, #0x1" + - + input: + bytes: [ 0x4b, 0x01, 0x51, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d0, d1, d0" + - + input: + bytes: [ 0x6d, 0x00, 0xe2, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x7c4" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x4000" + - + input: + bytes: [ 0x6d, 0xff, 0x04, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xdf8" + - + input: + bytes: [ 0x40, 0x2d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a13, a2" + - + input: + bytes: [ 0xb7, 0x3f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x3, #0, #0x8" + - + input: + bytes: [ 0x4b, 0x08, 0x61, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "utof d0, d8" + - + input: + bytes: [ 0x8f, 0x0a, 0x42, 0xa1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d10, d10, #0x20" + - + input: + bytes: [ 0x1d, 0xff, 0xee, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x424" + - + input: + bytes: [ 0x60, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a15, d15" + - + input: + bytes: [ 0x6d, 0x00, 0x87, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x50e" + - + input: + bytes: [ 0x40, 0x4c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a12, a4" + - + input: + bytes: [ 0x37, 0x00, 0x48, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d4, d0, #0, #0x8" + - + input: + bytes: [ 0x6d, 0xff, 0x76, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x314" + - + input: + bytes: [ 0xd9, 0x44, 0x28, 0xa6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x62a8" + - + input: + bytes: [ 0x02, 0x96 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d6, d9" + - + input: + bytes: [ 0x8b, 0x0f, 0x20, 0x42 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne d4, d15, #0" + - + input: + bytes: [ 0xc6, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d2, d15" + - + input: + bytes: [ 0x4e, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jgtz d0, #0x6" + - + input: + bytes: [ 0x49, 0xa7, 0x08, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a7, [sp]#0x8" + - + input: + bytes: [ 0x4e, 0xa8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jgtz d10, #0x10" + - + input: + bytes: [ 0x3b, 0xf0, 0x26, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x126f" + - + input: + bytes: [ 0xdf, 0x0d, 0x16, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d13, #0, #0x2c" + - + input: + bytes: [ 0x0f, 0xf0, 0xa0, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d5, d0, d15" + - + input: + bytes: [ 0x1d, 0xff, 0xc9, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x46e" + - + input: + bytes: [ 0x9b, 0xe1, 0xcb, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d1, d1, #0x4cbe" + - + input: + bytes: [ 0x1d, 0x00, 0x60, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x2c0" + - + input: + bytes: [ 0x6d, 0xff, 0x3a, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x18c" + - + input: + bytes: [ 0xff, 0x1f, 0xfc, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d15, #0x1, #-0x8" + - + input: + bytes: [ 0xd9, 0x55, 0xb8, 0xba ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5508" + - + input: + bytes: [ 0x80, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d15, a4" + - + input: + bytes: [ 0x96, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x10" + - + input: + bytes: [ 0xf6, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d4, #0x12" + - + input: + bytes: [ 0xdf, 0x10, 0xf6, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d0, #0x1, #-0x14" + - + input: + bytes: [ 0xf6, 0x2e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d2, #0x1c" + - + input: + bytes: [ 0x06, 0xaf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, #-0x6" + - + input: + bytes: [ 0x8b, 0x0f, 0x20, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne d1, d15, #0" + - + input: + bytes: [ 0x40, 0xcf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a15, a12" + - + input: + bytes: [ 0x3b, 0x60, 0x06, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #0x66" + - + input: + bytes: [ 0xd9, 0xff, 0xdc, 0xa2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x2e9c" + - + input: + bytes: [ 0x3f, 0xe8, 0xe6, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d8, d14, #-0x34" + - + input: + bytes: [ 0xc2, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d12, #-0x1" + - + input: + bytes: [ 0x09, 0xff, 0xba, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d15, [a15]#0x3a" + - + input: + bytes: [ 0xbb, 0x00, 0x68, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d1, #0x9680" + - + input: + bytes: [ 0xac, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a4]#0x10, d15" + - + input: + bytes: [ 0x02, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, d10" + - + input: + bytes: [ 0xd9, 0xff, 0xf4, 0xca ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x50cc" + - + input: + bytes: [ 0x3c, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x28" + - + input: + bytes: [ 0x2e, 0x4c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x4, #0x18" + - + input: + bytes: [ 0xd9, 0x55, 0x64, 0xba ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x591c" + - + input: + bytes: [ 0x5f, 0x0f, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0xe8" + - + input: + bytes: [ 0xd9, 0x55, 0x88, 0xca ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x54f8" + - + input: + bytes: [ 0x0b, 0xb1, 0x00, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.eq d15, d1, d11" + - + input: + bytes: [ 0x6d, 0x00, 0x14, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1028" + - + input: + bytes: [ 0x01, 0xf9, 0x00, 0x46 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a4, a15, d9, #0" + - + input: + bytes: [ 0x37, 0xf0, 0x02, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0, #0x2" + - + input: + bytes: [ 0xda, 0x6f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x6f" + - + input: + bytes: [ 0x5f, 0x0f, 0xbf, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x17e" + - + input: + bytes: [ 0x8f, 0x1f, 0x00, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d10, d15, #0x1" + - + input: + bytes: [ 0x3c, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0xe" + - + input: + bytes: [ 0x6d, 0x00, 0xa9, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1f52" + - + input: + bytes: [ 0x0b, 0x45, 0x10, 0x88 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e8, d5, d4" + - + input: + bytes: [ 0x0b, 0x01, 0x10, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e4, d1, d0" + - + input: + bytes: [ 0x9b, 0x81, 0xb9, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d1, d1, #0x4b98" + - + input: + bytes: [ 0xc2, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, #0x2" + - + input: + bytes: [ 0xdf, 0x7f, 0xf6, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x7, #-0x14" + - + input: + bytes: [ 0x26, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d15" + - + input: + bytes: [ 0x6d, 0xff, 0x04, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1f8" + - + input: + bytes: [ 0x61, 0xff, 0x35, 0xd9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x4d96" + - + input: + bytes: [ 0xf6, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d2, #0x4" + - + input: + bytes: [ 0x09, 0xdf, 0xc8, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d15, [a13]#0x8" + - + input: + bytes: [ 0x49, 0x4f, 0x04, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a4]#0x44" + - + input: + bytes: [ 0x37, 0x0f, 0xe2, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x1, #0x2" + - + input: + bytes: [ 0xdf, 0x0f, 0x37, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0, #-0x192" + - + input: + bytes: [ 0x37, 0x0f, 0x61, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x2, #0x1" + - + input: + bytes: [ 0xd9, 0xff, 0x38, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0xf8" + - + input: + bytes: [ 0x8f, 0xc8, 0x3f, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d4, d8, #-0x4" + - + input: + bytes: [ 0x61, 0x00, 0x0e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #0x1c" + - + input: + bytes: [ 0x67, 0xff, 0xbf, 0xbf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insn.t d11, d15, #0x1f, d15, #0x1f" + - + input: + bytes: [ 0xce, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jgez d0, #0x6" + - + input: + bytes: [ 0x91, 0x10, 0x00, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0x8001" + - + input: + bytes: [ 0x2d, 0x0f, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jli a15" + - + input: + bytes: [ 0x96, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x1" + - + input: + bytes: [ 0x2d, 0x02, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "calli a2" + - + input: + bytes: [ 0x82, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x5" + - + input: + bytes: [ 0xb7, 0x7f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x7, #0, #0x8" + - + input: + bytes: [ 0x2e, 0x3c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x3, #0x18" + - + input: + bytes: [ 0x76, 0x47 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d4, #0xe" + - + input: + bytes: [ 0x8f, 0x2a, 0x40, 0x71 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d7, d10, #0x2" + - + input: + bytes: [ 0x6e, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #-0x8" + - + input: + bytes: [ 0xd2, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e6, #0" + - + input: + bytes: [ 0x12, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d9, d15, d0" + - + input: + bytes: [ 0x10, 0xc4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a4, a12, d15, #0" + - + input: + bytes: [ 0xc2, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d3, #-0x1" + - + input: + bytes: [ 0x6f, 0x0f, 0xff, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #-0x2" + - + input: + bytes: [ 0x86, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, #0x4" + - + input: + bytes: [ 0xdf, 0x00, 0xc5, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d0, #0, #-0x76" + - + input: + bytes: [ 0x02, 0x8f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, d8" + - + input: + bytes: [ 0xac, 0xa3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x6, d15" + - + input: + bytes: [ 0x6d, 0x00, 0x6d, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xcda" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a1, #0" + - + input: + bytes: [ 0xd9, 0xee, 0x84, 0x70 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a14, [a14]#0x9c4" + - + input: + bytes: [ 0x8b, 0x60, 0x09, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsub d15, d0, #0x96" + - + input: + bytes: [ 0x6d, 0x00, 0x3c, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1878" + - + input: + bytes: [ 0x6d, 0xff, 0xe8, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x30" + - + input: + bytes: [ 0x6d, 0x00, 0xc8, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1d90" + - + input: + bytes: [ 0xb4, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a15], d15" + - + input: + bytes: [ 0x6d, 0xff, 0x92, 0x2c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1a6dc" + - + input: + bytes: [ 0xee, 0xbf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0x82" + - + input: + bytes: [ 0x53, 0x80, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d0, #0x8" + - + input: + bytes: [ 0x86, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d4, #0x2" + - + input: + bytes: [ 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a2, #0" + - + input: + bytes: [ 0xee, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x80" + - + input: + bytes: [ 0xda, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x4" + - + input: + bytes: [ 0x5e, 0x3c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x3, #0x18" + - + input: + bytes: [ 0x6d, 0x00, 0x02, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1c04" + - + input: + bytes: [ 0xd9, 0x55, 0x2c, 0xda ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5c94" + - + input: + bytes: [ 0x49, 0xf5, 0x3c, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a15]#0x3c" + - + input: + bytes: [ 0x02, 0x6e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d14, d6" + - + input: + bytes: [ 0x49, 0xa6, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a6, [sp]#0" + - + input: + bytes: [ 0x03, 0x6d, 0x0a, 0xc0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd d12, d0, d13, d6" + - + input: + bytes: [ 0x7f, 0xf0, 0xc3, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d0, d15, #-0x7a" + - + input: + bytes: [ 0x6e, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x34" + - + input: + bytes: [ 0x6d, 0xff, 0x49, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x16e" + - + input: + bytes: [ 0xee, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0xa" + - + input: + bytes: [ 0x61, 0xff, 0xda, 0xd9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x4c4c" + - + input: + bytes: [ 0xc2, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d2, #-0x1" + - + input: + bytes: [ 0xa2, 0x98 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d8, d9" + - + input: + bytes: [ 0x37, 0x0f, 0x62, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x6, #0x2" + - + input: + bytes: [ 0x3c, 0xc4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x78" + - + input: + bytes: [ 0x91, 0x40, 0x00, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x7004" + - + input: + bytes: [ 0xdf, 0x0b, 0x11, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d11, #0, #0x22" + - + input: + bytes: [ 0x8f, 0xf0, 0x01, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d5, d0, #0x1f" + - + input: + bytes: [ 0x06, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d4, #0x2" + - + input: + bytes: [ 0x02, 0xa5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d5, d10" + - + input: + bytes: [ 0xce, 0x96 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jgez d9, #0xc" + - + input: + bytes: [ 0x37, 0xf3, 0x08, 0x34 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d3, d3, d15, #0x8, #0x8" + - + input: + bytes: [ 0xda, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x30" + - + input: + bytes: [ 0x49, 0xa6, 0x08, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a6, [sp]#0x8" + - + input: + bytes: [ 0x6f, 0x0f, 0xf3, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #-0x1a" + - + input: + bytes: [ 0x6d, 0xff, 0xb5, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x96" + - + input: + bytes: [ 0x6d, 0xff, 0xeb, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2a" + - + input: + bytes: [ 0x15, 0xd0, 0xc0, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lducx #0xd0003fc0" + - + input: + bytes: [ 0x37, 0xf0, 0x03, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0x6, #0x3" + - + input: + bytes: [ 0x4b, 0x0f, 0x61, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "utof d15, d15" + - + input: + bytes: [ 0x8f, 0x3c, 0x00, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d4, d12, #0x3" + - + input: + bytes: [ 0x5f, 0x9f, 0xef, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d9, #0x1de" + - + input: + bytes: [ 0x3e, 0xed ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d14, #0x1a" + - + input: + bytes: [ 0x3e, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x16" + - + input: + bytes: [ 0x6d, 0x00, 0x88, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x710" + - + input: + bytes: [ 0x61, 0xff, 0x4d, 0xda ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x4b66" + - + input: + bytes: [ 0x09, 0xd4, 0xae, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d4, [a13]#0x2e" + - + input: + bytes: [ 0x6d, 0x00, 0xbc, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2378" + - + input: + bytes: [ 0x42, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d1, d2" + - + input: + bytes: [ 0x3b, 0x50, 0x06, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, #0x65" + - + input: + bytes: [ 0xd9, 0xff, 0x18, 0x96 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x6258" + - + input: + bytes: [ 0x3a, 0x64 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq d15, d4, d6" + - + input: + bytes: [ 0xda, 0x25 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x25" + - + input: + bytes: [ 0x8b, 0x01, 0x00, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.eq d15, d1, #0" + - + input: + bytes: [ 0x0b, 0x39, 0x90, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.lt d0, d9, d3" + - + input: + bytes: [ 0x8b, 0x0f, 0x02, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d4, d15, #0x20" + - + input: + bytes: [ 0xab, 0x10, 0xa0, 0x9f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "seln d9, d15, d0, #0x1" + - + input: + bytes: [ 0xa6, 0x53 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d3, d5" + - + input: + bytes: [ 0x6d, 0xff, 0xa8, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xb0" + - + input: + bytes: [ 0x9b, 0xf6, 0xff, 0x67 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d6, d6, #0x7fff" + - + input: + bytes: [ 0x3f, 0xac, 0xf8, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d12, d10, #-0x10" + - + input: + bytes: [ 0xab, 0xf8, 0x1f, 0x88 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cadd d8, d8, d8, #-0x1" + - + input: + bytes: [ 0x6f, 0x3a, 0xec, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d10, #0x3, #-0x28" + - + input: + bytes: [ 0x3b, 0x80, 0x07, 0x60 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d6, #0x78" + - + input: + bytes: [ 0x6d, 0xff, 0x64, 0x2b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1a938" + - + input: + bytes: [ 0xda, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0" + - + input: + bytes: [ 0xab, 0x69, 0x80, 0x91 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sel d9, d1, d9, #0x6" + - + input: + bytes: [ 0x37, 0x0f, 0x50, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d2, d15, #0, #0x10" + - + input: + bytes: [ 0x6d, 0x00, 0x34, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x468" + - + input: + bytes: [ 0x10, 0xc5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a5, a12, d15, #0" + - + input: + bytes: [ 0x94, 0xdf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d15, [a13]" + - + input: + bytes: [ 0x1d, 0x00, 0xe1, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x1c2" + - + input: + bytes: [ 0xff, 0x1f, 0xf1, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d15, #0x1, #-0x1e" + - + input: + bytes: [ 0xd9, 0xff, 0x28, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x68" + - + input: + bytes: [ 0x0b, 0x19, 0x80, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.ne d2, d9, d1" + - + input: + bytes: [ 0x3f, 0x0f, 0x04, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d15, d0, #0x8" + - + input: + bytes: [ 0x40, 0xd2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a2, a13" + - + input: + bytes: [ 0x37, 0x0f, 0xe8, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x17, #0x8" + - + input: + bytes: [ 0x53, 0xcf, 0x20, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d1, d15, #0xc" + - + input: + bytes: [ 0x3f, 0xf0, 0xf3, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d0, d15, #-0x1a" + - + input: + bytes: [ 0xda, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x19" + - + input: + bytes: [ 0x67, 0x45, 0x80, 0x5f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ins.t d5, d5, #0, d4, #0x1f" + - + input: + bytes: [ 0x5f, 0x0f, 0x2f, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x5e" + - + input: + bytes: [ 0xd9, 0xff, 0x80, 0xc9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x6500" + - + input: + bytes: [ 0x37, 0x04, 0x68, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d4, #0x8, #0x8" + - + input: + bytes: [ 0x0b, 0x71, 0x50, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addc d5, d1, d7" + - + input: + bytes: [ 0xda, 0x43 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x43" + - + input: + bytes: [ 0x60, 0x52 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a2, d5" + - + input: + bytes: [ 0x4b, 0x00, 0x61, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "utof d0, d0" + - + input: + bytes: [ 0x6d, 0xff, 0x67, 0x4c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x16732" + - + input: + bytes: [ 0x6d, 0x00, 0x65, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x22ca" + - + input: + bytes: [ 0x0b, 0x4f, 0x20, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt d0, d15, d4" + - + input: + bytes: [ 0x6d, 0x00, 0x17, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x62e" + - + input: + bytes: [ 0x80, 0x55 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d5, a5" + - + input: + bytes: [ 0xef, 0x4f, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x14, #0x8" + - + input: + bytes: [ 0x9b, 0x34, 0x98, 0x4d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d4, d4, #0xd983" + - + input: + bytes: [ 0x89, 0xf2, 0xb4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a15]#0x34, d2" + - + input: + bytes: [ 0xef, 0x8f, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x18, #0x14" + - + input: + bytes: [ 0x6d, 0xff, 0x97, 0x3e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x182d2" + - + input: + bytes: [ 0x37, 0x0f, 0x48, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d2, d15, #0, #0x8" + - + input: + bytes: [ 0x10, 0xd2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a13, d15, #0" + - + input: + bytes: [ 0x9b, 0xef, 0xcb, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d15, d15, #0x4cbe" + - + input: + bytes: [ 0xee, 0x1d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x3a" + - + input: + bytes: [ 0x6d, 0x00, 0x13, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1e26" + - + input: + bytes: [ 0x5f, 0x0f, 0x2c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x58" + - + input: + bytes: [ 0x49, 0xa5, 0x14, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [sp]#0x14" + - + input: + bytes: [ 0xb0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a5, #0" + - + input: + bytes: [ 0xd9, 0xff, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x5c00" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0x7000" + - + input: + bytes: [ 0x37, 0x0a, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d10, #0, #0x8" + - + input: + bytes: [ 0x2e, 0x3e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x3, #0x1c" + - + input: + bytes: [ 0xf6, 0x8a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d8, #0x14" + - + input: + bytes: [ 0xd9, 0x55, 0x40, 0x9a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x59c0" + - + input: + bytes: [ 0x3b, 0x00, 0x10, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x100" + - + input: + bytes: [ 0xd9, 0x55, 0x0c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#0xc" + - + input: + bytes: [ 0x3c, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x16" + - + input: + bytes: [ 0x49, 0xa4, 0x00, 0x4a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [sp]#0x100" + - + input: + bytes: [ 0x6d, 0x00, 0xab, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x156" + - + input: + bytes: [ 0x7e, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0xc" + - + input: + bytes: [ 0x9d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ja #0" + - + input: + bytes: [ 0x26, 0x31 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d1, d3" + - + input: + bytes: [ 0xa0, 0x74 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a4, #0x7" + - + input: + bytes: [ 0x01, 0xc9, 0x00, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, a12, d9, #0" + - + input: + bytes: [ 0xd9, 0xff, 0x34, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0xb4" + - + input: + bytes: [ 0x91, 0x10, 0x88, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0xf881" + - + input: + bytes: [ 0xfe, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x30" + - + input: + bytes: [ 0x37, 0xf0, 0x02, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0x6, #0x2" + - + input: + bytes: [ 0xd9, 0x55, 0x14, 0xea ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5c6c" + - + input: + bytes: [ 0x3b, 0x60, 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x66" + - + input: + bytes: [ 0x49, 0xa6, 0x0c, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a6, [sp]#0xc" + - + input: + bytes: [ 0x6b, 0x0f, 0x61, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd.f d4, d1, d15, d0" + - + input: + bytes: [ 0xda, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x3" + - + input: + bytes: [ 0x6d, 0xff, 0x81, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x10fe" + - + input: + bytes: [ 0xda, 0x42 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x42" + - + input: + bytes: [ 0xda, 0x64 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x64" + - + input: + bytes: [ 0x4e, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jgtz d0, #0x1a" + - + input: + bytes: [ 0x09, 0xaf, 0xc4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d15, [sp]#0x4" + - + input: + bytes: [ 0xd9, 0x22, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x7c00" + - + input: + bytes: [ 0xa2, 0x54 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d4, d5" + - + input: + bytes: [ 0x37, 0xf0, 0x0c, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0, #0xc" + - + input: + bytes: [ 0x3c, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x2e" + - + input: + bytes: [ 0x76, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d0, #0xe" + - + input: + bytes: [ 0x0b, 0x71, 0xa0, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.lt.u d15, d1, d7" + - + input: + bytes: [ 0xae, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0, #0x6" + - + input: + bytes: [ 0xb0, 0x4e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a14, #0x4" + - + input: + bytes: [ 0x8f, 0x0f, 0x1f, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d0, d15, #-0x10" + - + input: + bytes: [ 0x6d, 0xff, 0x7b, 0x4c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1670a" + - + input: + bytes: [ 0x6f, 0x5f, 0x21, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0x5, #0x42" + - + input: + bytes: [ 0x16, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0x1" + - + input: + bytes: [ 0x6e, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x16" + - + input: + bytes: [ 0x6d, 0xff, 0x8b, 0xe1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3cea" + - + input: + bytes: [ 0xff, 0x1f, 0xf5, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d15, #0x1, #-0x16" + - + input: + bytes: [ 0xac, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a15]#0x12, d15" + - + input: + bytes: [ 0x7e, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0xa" + - + input: + bytes: [ 0xd9, 0xff, 0x0c, 0x96 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x624c" + - + input: + bytes: [ 0x10, 0xc2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a12, d15, #0" + - + input: + bytes: [ 0x4b, 0x0f, 0x41, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "itof d15, d15" + - + input: + bytes: [ 0x8a, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cadd d15, d15, #-0x1" + - + input: + bytes: [ 0x6d, 0xff, 0x3f, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xb82" + - + input: + bytes: [ 0x09, 0x40, 0x8e, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d0, [a4]#0xe" + - + input: + bytes: [ 0x6d, 0x00, 0x2f, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x85e" + - + input: + bytes: [ 0x3b, 0x50, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x45" + - + input: + bytes: [ 0x8b, 0x7f, 0x01, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d4, d15, #0x17" + - + input: + bytes: [ 0xd9, 0xff, 0xee, 0xe2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x2fae" + - + input: + bytes: [ 0xd9, 0xff, 0xa4, 0xba ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x551c" + - + input: + bytes: [ 0x8b, 0x1f, 0x00, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq d2, d15, #0x1" + - + input: + bytes: [ 0x46, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "not d4" + - + input: + bytes: [ 0xd9, 0xaa, 0x40, 0x85 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea sp, [sp]#0x5600" + - + input: + bytes: [ 0x76, 0x92 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d9, #0x4" + - + input: + bytes: [ 0xbd, 0x0e, 0x28, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.a a14, #0x50" + - + input: + bytes: [ 0x94, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d15, [a15]" + - + input: + bytes: [ 0x5f, 0x0f, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x178" + - + input: + bytes: [ 0x49, 0xff, 0x00, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x40" + - + input: + bytes: [ 0xd9, 0xff, 0x44, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x484" + - + input: + bytes: [ 0xda, 0x34 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x34" + - + input: + bytes: [ 0x89, 0xff, 0xb4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a15]#0x34, d15" + - + input: + bytes: [ 0x7f, 0xf0, 0x03, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d0, d15, #0x6" + - + input: + bytes: [ 0x3f, 0xf9, 0xf7, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d9, d15, #-0x12" + - + input: + bytes: [ 0x7b, 0x00, 0xf0, 0x13 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d1, #0x3f00" + - + input: + bytes: [ 0x61, 0xff, 0xbd, 0xd8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x4e86" + - + input: + bytes: [ 0xce, 0x77 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jgez d7, #0xe" + - + input: + bytes: [ 0xde, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x2, #0x30" + - + input: + bytes: [ 0xee, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0x8" + - + input: + bytes: [ 0xb7, 0x01, 0x02, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d2, d1, #0, #0, #0x2" + - + input: + bytes: [ 0x4b, 0x00, 0x41, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "itof d15, d0" + - + input: + bytes: [ 0x8f, 0x1a, 0x40, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d10, #0x1" + - + input: + bytes: [ 0x2e, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x2, #0x6" + - + input: + bytes: [ 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x0" + - + input: + bytes: [ 0x6d, 0xff, 0xab, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xcaa" + - + input: + bytes: [ 0x80, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d0, a15" + - + input: + bytes: [ 0x7e, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d1, #0xe" + - + input: + bytes: [ 0x09, 0xf0, 0xb4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d0, [a15]#0x34" + - + input: + bytes: [ 0x6d, 0x00, 0xe2, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x33c4" + - + input: + bytes: [ 0xda, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x1" + - + input: + bytes: [ 0x37, 0xf0, 0x81, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0x7, #0x1" + - + input: + bytes: [ 0x4b, 0xf2, 0x51, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d15, d2, d15" + - + input: + bytes: [ 0xa0, 0x72 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a2, #0x7" + - + input: + bytes: [ 0x6d, 0x00, 0x48, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x490" + - + input: + bytes: [ 0xac, 0xa1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x2, d15" + - + input: + bytes: [ 0xd9, 0xff, 0xfc, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x1c3c" + - + input: + bytes: [ 0xd9, 0xff, 0x30, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0xb0" + - + input: + bytes: [ 0x3e, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x1c" + - + input: + bytes: [ 0xd9, 0x22, 0xb8, 0x61 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x19b8" + - + input: + bytes: [ 0x76, 0x15 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d1, #0xa" + - + input: + bytes: [ 0x2e, 0x27 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x2, #0xe" + - + input: + bytes: [ 0xd9, 0xee, 0x9e, 0x70 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a14, [a14]#0x9de" + - + input: + bytes: [ 0x6b, 0x0e, 0x21, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.f d15, d2, d14" + - + input: + bytes: [ 0x82, 0x1e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d14, #0x1" + - + input: + bytes: [ 0x86, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d1, #0x2" + - + input: + bytes: [ 0x4b, 0x0c, 0x61, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "utof d15, d12" + - + input: + bytes: [ 0x10, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, a4, d15, #0" + - + input: + bytes: [ 0x6d, 0xff, 0x27, 0x38 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x18fb2" + - + input: + bytes: [ 0x37, 0xf0, 0x01, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0, #0x1" + - + input: + bytes: [ 0x76, 0xb6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d11, #0xc" + - + input: + bytes: [ 0x49, 0x55, 0x0c, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#0xc" + - + input: + bytes: [ 0x6d, 0xff, 0x0a, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3ec" + - + input: + bytes: [ 0x6d, 0x00, 0xdb, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x9b6" + - + input: + bytes: [ 0x5f, 0x8f, 0xc7, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d8, #0x18e" + - + input: + bytes: [ 0xda, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x9" + - + input: + bytes: [ 0x37, 0x0f, 0x6c, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0, #0xc" + - + input: + bytes: [ 0x37, 0x04, 0x68, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d4, #0x18, #0x8" + - + input: + bytes: [ 0x6f, 0x2f, 0x12, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x2, #0x24" + - + input: + bytes: [ 0x0f, 0x10, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d0, d0, d1" + - + input: + bytes: [ 0x6e, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x4" + - + input: + bytes: [ 0x09, 0xf0, 0xb6, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d0, [a15]#0x36" + - + input: + bytes: [ 0x5f, 0x0f, 0xd6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x1ac" + - + input: + bytes: [ 0xc2, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d14, #-0x1" + - + input: + bytes: [ 0x6e, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x10" + - + input: + bytes: [ 0x10, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, a2, d15, #0" + - + input: + bytes: [ 0x6e, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x1c" + - + input: + bytes: [ 0xda, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x8" + - + input: + bytes: [ 0xbd, 0x0f, 0x1a, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.a a15, #0x34" + - + input: + bytes: [ 0x6d, 0xff, 0x01, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1fe" + - + input: + bytes: [ 0x3c, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x3e" + - + input: + bytes: [ 0x6d, 0x00, 0xab, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x556" + - + input: + bytes: [ 0x5f, 0x8f, 0x21, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d8, #0x42" + - + input: + bytes: [ 0x5f, 0x0f, 0xb9, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x172" + - + input: + bytes: [ 0x73, 0xd7, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d0, d7, d13" + - + input: + bytes: [ 0x8b, 0x0f, 0x20, 0x32 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne d3, d15, #0" + - + input: + bytes: [ 0x2e, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #0x18" + - + input: + bytes: [ 0xd9, 0x55, 0x98, 0xca ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x54e8" + - + input: + bytes: [ 0xd9, 0x44, 0x28, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x28" + - + input: + bytes: [ 0x09, 0x40, 0x84, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d0, [a4]#0x4" + - + input: + bytes: [ 0xfc, 0x2e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a2, #-0x4" + - + input: + bytes: [ 0xea, 0x69 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmovn d9, d15, #0x6" + - + input: + bytes: [ 0x3c, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x1e" + - + input: + bytes: [ 0x3c, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x90" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x6000" + - + input: + bytes: [ 0x7a, 0xe8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt d15, d8, d14" + - + input: + bytes: [ 0x60, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a15, d4" + - + input: + bytes: [ 0x82, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d9, #0" + - + input: + bytes: [ 0x6d, 0xff, 0x13, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xfda" + - + input: + bytes: [ 0xdf, 0x0f, 0xcf, 0x81 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0, #0x39e" + - + input: + bytes: [ 0x7f, 0x0e, 0xde, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d14, d0, #-0x44" + - + input: + bytes: [ 0x3b, 0xa0, 0x07, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x7a" + - + input: + bytes: [ 0xd9, 0x55, 0x70, 0x4a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5ad0" + - + input: + bytes: [ 0xd9, 0x88, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a8, [a8]#0" + - + input: + bytes: [ 0xef, 0x7f, 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x17, #0xc" + - + input: + bytes: [ 0xb0, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a15, #0x4" + - + input: + bytes: [ 0x92, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d9, d15, #0x1" + - + input: + bytes: [ 0xd9, 0x55, 0xac, 0xca ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x54d4" + - + input: + bytes: [ 0x6d, 0xff, 0xb3, 0x2a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1aa9a" + - + input: + bytes: [ 0x40, 0x45 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a5, a4" + - + input: + bytes: [ 0x01, 0xdd, 0x00, 0xd6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a13, a13, d13, #0" + - + input: + bytes: [ 0x6d, 0x00, 0x2d, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x225a" + - + input: + bytes: [ 0x6d, 0xff, 0x5a, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xd4c" + - + input: + bytes: [ 0x1d, 0xff, 0x04, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x3f8" + - + input: + bytes: [ 0x20, 0x60 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.a sp, #0x60" + - + input: + bytes: [ 0x7f, 0x0f, 0x16, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d15, d0, #0x2c" + - + input: + bytes: [ 0xc5, 0xff, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, #0xf0001000" + - + input: + bytes: [ 0xd9, 0xff, 0xa8, 0xda ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x5498" + - + input: + bytes: [ 0x37, 0x0f, 0x01, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x2, #0x1" + - + input: + bytes: [ 0x76, 0x4a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d4, #0x14" + - + input: + bytes: [ 0x3f, 0x0f, 0xe8, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d15, d0, #-0x30" + - + input: + bytes: [ 0xd9, 0x55, 0x8c, 0xda ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x54b4" + - + input: + bytes: [ 0x8b, 0x01, 0xa0, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addc d1, d1, #0" + - + input: + bytes: [ 0x09, 0xdf, 0xe2, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d15, [a13]#0x22" + - + input: + bytes: [ 0xd9, 0xee, 0x2e, 0xe0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a14, [a14]#0x3ae" + - + input: + bytes: [ 0x6d, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x30" + - + input: + bytes: [ 0x3b, 0x80, 0x3e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x3e8" + - + input: + bytes: [ 0xbb, 0xd0, 0xcc, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d0, #0xcccd" + - + input: + bytes: [ 0x3e, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0xa" + - + input: + bytes: [ 0xee, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0x6" + - + input: + bytes: [ 0x6d, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x820" + - + input: + bytes: [ 0xc6, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d15, d1" + - + input: + bytes: [ 0x42, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d8" + - + input: + bytes: [ 0xee, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0xc" + - + input: + bytes: [ 0xa6, 0x54 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d4, d5" + - + input: + bytes: [ 0x91, 0x40, 0x00, 0xa7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a sp, #0x7004" + - + input: + bytes: [ 0x6f, 0x5a, 0x06, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d10, #0x5, #0xc" + - + input: + bytes: [ 0xd9, 0x22, 0xc0, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#-0x4400" + - + input: + bytes: [ 0x3e, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x10" + - + input: + bytes: [ 0x37, 0xf0, 0x02, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0x14, #0x2" + - + input: + bytes: [ 0x3c, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x34" + - + input: + bytes: [ 0x02, 0xa7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d7, d10" + - + input: + bytes: [ 0xda, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x5" + - + input: + bytes: [ 0x3b, 0x60, 0xff, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #-0xa" + - + input: + bytes: [ 0x4e, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jgtz d15, #0xe" + - + input: + bytes: [ 0x3c, 0x3f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x7e" + - + input: + bytes: [ 0x37, 0x0f, 0x50, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d4, d15, #0, #0x10" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a0, #0" + - + input: + bytes: [ 0x09, 0xf8, 0xb4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d8, [a15]#0x34" + - + input: + bytes: [ 0x3b, 0x20, 0x05, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x52" + - + input: + bytes: [ 0xdf, 0x02, 0x21, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d2, #0, #0x42" + - + input: + bytes: [ 0x6f, 0x20, 0xf8, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d0, #0x2, #-0x10" + - + input: + bytes: [ 0x6e, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x2e" + - + input: + bytes: [ 0x3c, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xc" + - + input: + bytes: [ 0x6f, 0x29, 0x1b, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d9, #0x2, #0x36" + - + input: + bytes: [ 0x3b, 0x00, 0x01, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d5, #0x10" + - + input: + bytes: [ 0x82, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d3, #0" + - + input: + bytes: [ 0xc2, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d5, #-0x1" + - + input: + bytes: [ 0xd9, 0xff, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x420" + - + input: + bytes: [ 0x7f, 0xf0, 0x06, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d0, d15, #0xc" + - + input: + bytes: [ 0xee, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0xc" + - + input: + bytes: [ 0x6d, 0xff, 0x94, 0x2a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1aad8" + - + input: + bytes: [ 0x6d, 0xff, 0x08, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x7f0" + - + input: + bytes: [ 0x37, 0xf3, 0x08, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d3, d3, d15, #0, #0x8" + - + input: + bytes: [ 0x6d, 0x00, 0xdf, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1be" + - + input: + bytes: [ 0xd9, 0xff, 0xc8, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x1d08" + - + input: + bytes: [ 0xd9, 0x22, 0x08, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x1088" + - + input: + bytes: [ 0x82, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x1" + - + input: + bytes: [ 0xab, 0x0f, 0xa2, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "seln d15, d0, d15, #0x20" + - + input: + bytes: [ 0xfe, 0xdb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d13, #0x36" + - + input: + bytes: [ 0x37, 0xf0, 0x03, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0x18, #0x3" + - + input: + bytes: [ 0xd9, 0x22, 0x48, 0xe1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x1788" + - + input: + bytes: [ 0x1d, 0x00, 0x6e, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x2dc" + - + input: + bytes: [ 0xdf, 0x1f, 0x29, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x52" + - + input: + bytes: [ 0x8f, 0x78, 0x00, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d8, #0x7" + - + input: + bytes: [ 0x4b, 0xf2, 0x51, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d2, d2, d15" + - + input: + bytes: [ 0x82, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d10, #0" + - + input: + bytes: [ 0x37, 0x4f, 0x9f, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d4, #0x1, #0x1f" + - + input: + bytes: [ 0x3c, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x50" + - + input: + bytes: [ 0x49, 0xfc, 0x10, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a12, [a15]#0x10" + - + input: + bytes: [ 0xfe, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x32" + - + input: + bytes: [ 0x6d, 0xff, 0x0d, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1e6" + - + input: + bytes: [ 0x3b, 0xc0, 0x00, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d9, #0xc" + - + input: + bytes: [ 0xda, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x11" + - + input: + bytes: [ 0x7b, 0xd0, 0x38, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d0, #0x138d" + - + input: + bytes: [ 0xd9, 0x55, 0x48, 0x3a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5b38" + - + input: + bytes: [ 0xbb, 0xf0, 0xff, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d2, #0xffff" + - + input: + bytes: [ 0x6d, 0xff, 0x42, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x37c" + - + input: + bytes: [ 0x6d, 0x00, 0x62, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xc4" + - + input: + bytes: [ 0x76, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d0, #0x12" + - + input: + bytes: [ 0xd9, 0x44, 0x3c, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x2bc" + - + input: + bytes: [ 0x3c, 0x43 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x86" + - + input: + bytes: [ 0x7f, 0xf0, 0x28, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d0, d15, #0x50" + - + input: + bytes: [ 0x37, 0x04, 0x68, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d4, #0x10, #0x8" + - + input: + bytes: [ 0x0b, 0xc0, 0xc0, 0xc0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "subx d12, d0, d12" + - + input: + bytes: [ 0x0f, 0x05, 0xd0, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cls d1, d5" + - + input: + bytes: [ 0xd9, 0xff, 0x14, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x54" + - + input: + bytes: [ 0x0f, 0x31, 0x10, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d1, d1, d3" + - + input: + bytes: [ 0xc6, 0x3f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d15, d3" + - + input: + bytes: [ 0xa6, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d5, d15" + - + input: + bytes: [ 0x6d, 0xff, 0xda, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xa4c" + - + input: + bytes: [ 0x6d, 0x00, 0xcc, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xf98" + - + input: + bytes: [ 0x6d, 0xff, 0x28, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3b0" + - + input: + bytes: [ 0x15, 0xd0, 0xc0, 0xe3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "stlcx #0xd0003f80" + - + input: + bytes: [ 0x61, 0xff, 0x4c, 0xda ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x4b68" + - + input: + bytes: [ 0x6d, 0x00, 0x27, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x64e" + - + input: + bytes: [ 0x37, 0x09, 0x50, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d9, d9, #0, #0x10" + - + input: + bytes: [ 0x8c, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d15, [a2]#0x4" + - + input: + bytes: [ 0x76, 0x2a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d2, #0x14" + - + input: + bytes: [ 0x3f, 0x98, 0xe0, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d8, d9, #-0x40" + - + input: + bytes: [ 0x88, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d2, [a15]#0x4" + - + input: + bytes: [ 0x76, 0x85 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d8, #0xa" + - + input: + bytes: [ 0xaa, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmov d0, d15, #0x1" + - + input: + bytes: [ 0x6d, 0xff, 0x91, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xde" + - + input: + bytes: [ 0x2e, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x2, #0x4" + - + input: + bytes: [ 0xd9, 0xff, 0x3c, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x4fc4" + - + input: + bytes: [ 0x3c, 0x3c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x78" + - + input: + bytes: [ 0x3b, 0x20, 0x03, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d10, #0x32" + - + input: + bytes: [ 0x91, 0x20, 0x88, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0xf882" + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d15, d15, #0x3f" + - + input: + bytes: [ 0x3b, 0x60, 0x09, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x96" + - + input: + bytes: [ 0x7f, 0x89, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d9, d8, #0x8" + - + input: + bytes: [ 0x37, 0x0f, 0x70, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0, #0x10" + - + input: + bytes: [ 0x3e, 0x46 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d4, #0xc" + - + input: + bytes: [ 0xd9, 0x22, 0xa8, 0xa1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x1aa8" + - + input: + bytes: [ 0x37, 0x05, 0x68, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d5, #0x18, #0x8" + - + input: + bytes: [ 0xd9, 0x11, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a1, [a1]#0" + - + input: + bytes: [ 0x0b, 0x45, 0x10, 0xa8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e10, d5, d4" + - + input: + bytes: [ 0x06, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d4, #-0x1" + - + input: + bytes: [ 0xd9, 0xff, 0x0c, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0xcc" + - + input: + bytes: [ 0xfe, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x28" + - + input: + bytes: [ 0x6d, 0x00, 0x9a, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xf34" + - + input: + bytes: [ 0x3b, 0xa0, 0x02, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x2a" + - + input: + bytes: [ 0x6f, 0x2f, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x2, #0x68" + - + input: + bytes: [ 0x6d, 0x00, 0xbd, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x77a" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x80" + - + input: + bytes: [ 0x53, 0x8f, 0x20, 0xc0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d12, d15, #0x8" + - + input: + bytes: [ 0x17, 0x45, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "dextr d0, d5, d4, d1" + - + input: + bytes: [ 0x02, 0x45 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d5, d4" + - + input: + bytes: [ 0x82, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #0" + - + input: + bytes: [ 0xd9, 0x55, 0x60, 0xba ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5920" + - + input: + bytes: [ 0xb7, 0x2f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x2, #0, #0x8" + - + input: + bytes: [ 0x6e, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x6" + - + input: + bytes: [ 0x6d, 0xff, 0x60, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x740" + - + input: + bytes: [ 0x37, 0x04, 0x70, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d4, d4, #0, #0x10" + - + input: + bytes: [ 0x6d, 0xff, 0x93, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xda" + - + input: + bytes: [ 0xb7, 0x1a, 0x01, 0xa5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d10, d10, #0x1, #0xa, #0x1" + - + input: + bytes: [ 0x4b, 0x1f, 0x01, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmp.f d15, d15, d1" + - + input: + bytes: [ 0xdf, 0x1f, 0xfb, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0x1, #-0xa" + - + input: + bytes: [ 0xc2, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d2, #0x1" + - + input: + bytes: [ 0x37, 0x08, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d8, #0, #0x10" + - + input: + bytes: [ 0xda, 0x31 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x31" + - + input: + bytes: [ 0x8b, 0x0f, 0x1d, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d8, d15, #-0x30" + - + input: + bytes: [ 0xd9, 0x55, 0xb4, 0xba ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x550c" + - + input: + bytes: [ 0x02, 0x82 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, d8" + - + input: + bytes: [ 0x76, 0xb2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d11, #0x4" + - + input: + bytes: [ 0x61, 0x00, 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #0xc" + - + input: + bytes: [ 0xbe, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x2c" + - + input: + bytes: [ 0x6d, 0xff, 0xfa, 0xe1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3c0c" + - + input: + bytes: [ 0x3f, 0x20, 0x0e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d0, d2, #0x1c" + - + input: + bytes: [ 0x8b, 0x1f, 0x03, 0xa1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsub d10, d15, #0x31" + - + input: + bytes: [ 0x6d, 0xff, 0xa7, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x6b2" + - + input: + bytes: [ 0x4b, 0xbf, 0x41, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d15, d15, d11" + - + input: + bytes: [ 0xfe, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x2a" + - + input: + bytes: [ 0x06, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d4, #0x1" + - + input: + bytes: [ 0x82, 0x78 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, #0x7" + - + input: + bytes: [ 0xf6, 0xb6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d11, #0xc" + - + input: + bytes: [ 0x02, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, d8" + - + input: + bytes: [ 0x3c, 0x39 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x72" + - + input: + bytes: [ 0x06, 0x63 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d3, #0x6" + - + input: + bytes: [ 0x6d, 0x00, 0x91, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x722" + - + input: + bytes: [ 0x01, 0x42, 0x20, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.a a2, a2, a4" + - + input: + bytes: [ 0x6d, 0xff, 0xc9, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x166e" + - + input: + bytes: [ 0x37, 0x0f, 0x6e, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x2, #0xe" + - + input: + bytes: [ 0x89, 0xaf, 0xb4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x34, d15" + - + input: + bytes: [ 0x6f, 0x04, 0x0d, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d4, #0, #0x1a" + - + input: + bytes: [ 0xd9, 0xff, 0x24, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x24" + - + input: + bytes: [ 0x4b, 0xa2, 0x41, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d10, d2, d10" + - + input: + bytes: [ 0x3e, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d1, #0x8" + - + input: + bytes: [ 0x37, 0x0f, 0x0c, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0, #0xc" + - + input: + bytes: [ 0x6d, 0xff, 0x0b, 0x2a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1abea" + - + input: + bytes: [ 0x2b, 0x09, 0x00, 0x9f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cadd d9, d15, d9, d0" + - + input: + bytes: [ 0x8b, 0x0f, 0x01, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsub d15, d15, #0x10" + - + input: + bytes: [ 0xd9, 0xff, 0xb8, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x1bf8" + - + input: + bytes: [ 0x6d, 0xff, 0x47, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x572" + - + input: + bytes: [ 0x6f, 0x1f, 0xfc, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x1, #-0x8" + - + input: + bytes: [ 0xda, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x40" + - + input: + bytes: [ 0xdf, 0xf0, 0x51, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d0, #-0x1, #0xa2" + - + input: + bytes: [ 0x5e, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x2, #0x6" + - + input: + bytes: [ 0x76, 0xcf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d12, #0x1e" + - + input: + bytes: [ 0x9b, 0x8f, 0xb9, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d15, d15, #0x4b98" + - + input: + bytes: [ 0x8b, 0x8f, 0x00, 0x60 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d6, d15, #0x8" + - + input: + bytes: [ 0x7b, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d1, #0x4000" + - + input: + bytes: [ 0x3c, 0x2c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x58" + - + input: + bytes: [ 0x92, 0x39 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d9, d15, #0x3" + - + input: + bytes: [ 0x5f, 0x8f, 0x07, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d8, #0x20e" + - + input: + bytes: [ 0x80, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d1, a4" + - + input: + bytes: [ 0x92, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d15, #0x1" + - + input: + bytes: [ 0x86, 0x6f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, #0x6" + - + input: + bytes: [ 0xd9, 0x55, 0x4c, 0x2a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5b74" + - + input: + bytes: [ 0xd9, 0x55, 0x50, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5bb0" + - + input: + bytes: [ 0xee, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0x1c" + - + input: + bytes: [ 0xee, 0xeb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0x2a" + - + input: + bytes: [ 0x49, 0xff, 0x0c, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0xc" + - + input: + bytes: [ 0x13, 0xa8, 0x20, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd d15, d15, d8, #0xa" + - + input: + bytes: [ 0x6d, 0x00, 0x18, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2230" + - + input: + bytes: [ 0x8b, 0x0f, 0x1d, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d9, d15, #-0x30" + - + input: + bytes: [ 0xc2, 0x18 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d8, #0x1" + - + input: + bytes: [ 0x2e, 0x2b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x2, #0x16" + - + input: + bytes: [ 0x0f, 0xa1, 0x10, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d1, d1, d10" + - + input: + bytes: [ 0x32, 0x58 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsub d8" + - + input: + bytes: [ 0xba, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq d15, d0, #0" + - + input: + bytes: [ 0x6d, 0xff, 0xc5, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1ac76" + - + input: + bytes: [ 0x5f, 0x0f, 0x59, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0xb2" + - + input: + bytes: [ 0x5e, 0x16 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0xc" + - + input: + bytes: [ 0x91, 0x40, 0x00, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0xf004" + - + input: + bytes: [ 0x0b, 0x17, 0x80, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.ne d15, d7, d1" + - + input: + bytes: [ 0x6d, 0x00, 0xb9, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2172" + - + input: + bytes: [ 0x37, 0x02, 0x68, 0xc0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d12, d2, #0, #0x8" + - + input: + bytes: [ 0x1d, 0x00, 0x8c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x118" + - + input: + bytes: [ 0x3b, 0x10, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x41" + - + input: + bytes: [ 0x49, 0xf5, 0x3e, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a15]#0x3e" + - + input: + bytes: [ 0x9b, 0x3f, 0xa8, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d15, d15, #0x3a83" + - + input: + bytes: [ 0x6e, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x1a" + - + input: + bytes: [ 0x5e, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #-0x1, #0x6" + - + input: + bytes: [ 0x3c, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x12" + - + input: + bytes: [ 0x0b, 0x71, 0xd0, 0xb0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "subc d11, d1, d7" + - + input: + bytes: [ 0x0f, 0x02, 0x10, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d2, d2, d0" + - + input: + bytes: [ 0xc2, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d9, #-0x1" + - + input: + bytes: [ 0x5f, 0x8f, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d8, #0xf0" + - + input: + bytes: [ 0xbc, 0x2c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.a a2, #0x18" + - + input: + bytes: [ 0x6b, 0x00, 0x31, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.f d15, d5, d0" + - + input: + bytes: [ 0xd9, 0x44, 0xa0, 0xe5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x5ba0" + - + input: + bytes: [ 0x9a, 0xd4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d4, #-0x3" + - + input: + bytes: [ 0x26, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d1" + - + input: + bytes: [ 0xee, 0x38 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x70" + - + input: + bytes: [ 0x91, 0x50, 0x02, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0xf025" + - + input: + bytes: [ 0x4b, 0x19, 0x41, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d1, d9, d1" + - + input: + bytes: [ 0xd9, 0x22, 0x92, 0x31 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x18d2" + - + input: + bytes: [ 0xa2, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d4, d2" + - + input: + bytes: [ 0x1d, 0x00, 0x9c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x138" + - + input: + bytes: [ 0xfc, 0x2c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a2, #-0x8" + - + input: + bytes: [ 0xee, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0x2" + - + input: + bytes: [ 0x3b, 0x60, 0x06, 0x60 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d6, #0x66" + - + input: + bytes: [ 0x01, 0xa0, 0x00, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, sp, d0, #0" + - + input: + bytes: [ 0x9b, 0xb0, 0xbf, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d0, d0, #0x4bfb" + - + input: + bytes: [ 0x1d, 0x00, 0x18, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x430" + - + input: + bytes: [ 0x91, 0x30, 0x00, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0xf003" + - + input: + bytes: [ 0x6d, 0x00, 0xa1, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2142" + - + input: + bytes: [ 0x7f, 0xf0, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d0, d15, #0x10" + - + input: + bytes: [ 0x6d, 0x00, 0xae, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x195c" + - + input: + bytes: [ 0xff, 0x14, 0xfc, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d4, #0x1, #-0x8" + - + input: + bytes: [ 0x6d, 0x00, 0x3a, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xa74" + - + input: + bytes: [ 0xba, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq d15, d12, #0" + - + input: + bytes: [ 0x09, 0x4f, 0xc4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d15, [a4]#0x4" + - + input: + bytes: [ 0x7d, 0x2f, 0x15, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne.a a15, a2, #0x2a" + - + input: + bytes: [ 0x0b, 0x0f, 0xa0, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "max d15, d15, d0" + - + input: + bytes: [ 0x3b, 0x30, 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x63" + - + input: + bytes: [ 0x91, 0x40, 0x00, 0xa6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a sp, #0x6004" + - + input: + bytes: [ 0x9b, 0x1f, 0x8d, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d15, d15, #0x38d1" + - + input: + bytes: [ 0x6d, 0x00, 0x3b, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2076" + - + input: + bytes: [ 0x61, 0xff, 0x0f, 0xd5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x55e2" + - + input: + bytes: [ 0xab, 0x0f, 0x83, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sel d15, d0, d15, #0x30" + - + input: + bytes: [ 0x6d, 0x00, 0xa0, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2340" + - + input: + bytes: [ 0xbe, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x30" + - + input: + bytes: [ 0x6d, 0xff, 0x89, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xee" + - + input: + bytes: [ 0x3f, 0xf0, 0x05, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, d15, #0xa" + - + input: + bytes: [ 0x37, 0x02, 0x48, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d2, d2, #0, #0x8" + - + input: + bytes: [ 0x0b, 0x60, 0x40, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addx d10, d0, d6" + - + input: + bytes: [ 0x49, 0xff, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0" + - + input: + bytes: [ 0x6d, 0x00, 0xe4, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x5c8" + - + input: + bytes: [ 0x6f, 0x3f, 0x2c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x3, #0x58" + - + input: + bytes: [ 0xd9, 0x22, 0x8c, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0xbcc" + - + input: + bytes: [ 0x6d, 0x00, 0xc5, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x218a" + - + input: + bytes: [ 0x6d, 0xff, 0x7f, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x102" + - + input: + bytes: [ 0x7b, 0x00, 0x12, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d0, #0x4120" + - + input: + bytes: [ 0x02, 0x84 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d8" + - + input: + bytes: [ 0x6d, 0xff, 0x11, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1de" + - + input: + bytes: [ 0x91, 0x20, 0x00, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a3, #0x2" + - + input: + bytes: [ 0x9e, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #-0x1, #0x24" + - + input: + bytes: [ 0xf6, 0xa5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d10, #0xa" + - + input: + bytes: [ 0x5f, 0x0f, 0xf6, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #-0x14" + - + input: + bytes: [ 0x0f, 0x4f, 0x00, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d15, d4" + - + input: + bytes: [ 0x6d, 0x00, 0xd2, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x29a4" + - + input: + bytes: [ 0xc2, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d10, #0x1" + - + input: + bytes: [ 0xae, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0x2, #0x12" + - + input: + bytes: [ 0xb0, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a2, #0x2" + - + input: + bytes: [ 0x3b, 0x40, 0x06, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #0x64" + - + input: + bytes: [ 0x10, 0xa2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, sp, d15, #0" + - + input: + bytes: [ 0x7d, 0x4f, 0x0d, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne.a a15, a4, #0x1a" + - + input: + bytes: [ 0x8f, 0x0f, 0x01, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d15, #0x10" + - + input: + bytes: [ 0x32, 0x5f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsub d15" + - + input: + bytes: [ 0xbe, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x26" + - + input: + bytes: [ 0xee, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0xe" + - + input: + bytes: [ 0x3b, 0x00, 0x03, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x30" + - + input: + bytes: [ 0x6d, 0x00, 0x3b, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2276" + - + input: + bytes: [ 0x3b, 0x00, 0x04, 0xe0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d14, #0x40" + - + input: + bytes: [ 0x6d, 0xff, 0xb1, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x9e" + - + input: + bytes: [ 0x8b, 0x1f, 0xe0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.eq d0, d15, #0x1" + - + input: + bytes: [ 0x32, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsub d0" + - + input: + bytes: [ 0x92, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d4, d15, #-0x1" + - + input: + bytes: [ 0xb4, 0xc2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a12], d2" + - + input: + bytes: [ 0x37, 0x01, 0x50, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d2, d1, #0, #0x10" + - + input: + bytes: [ 0xbb, 0xf0, 0x28, 0xec ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d14, #0xc28f" + - + input: + bytes: [ 0x3e, 0x8c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d8, #0x18" + - + input: + bytes: [ 0x8f, 0x3c, 0x00, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d12, #0x3" + - + input: + bytes: [ 0x6d, 0x00, 0x63, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xc6" + - + input: + bytes: [ 0xdf, 0x08, 0x71, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d8, #0, #-0x11e" + - + input: + bytes: [ 0x02, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, d4" + - + input: + bytes: [ 0x76, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d2, #0x6" + - + input: + bytes: [ 0xee, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0x12" + - + input: + bytes: [ 0x96, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x4" + - + input: + bytes: [ 0xdf, 0x09, 0x63, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d9, #0, #0xc6" + - + input: + bytes: [ 0x6e, 0xe8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #-0x30" + - + input: + bytes: [ 0x10, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a2, d15, #0" + - + input: + bytes: [ 0x6d, 0xff, 0xba, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x48c" + - + input: + bytes: [ 0x37, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0, #0x8" + - + input: + bytes: [ 0x15, 0xd0, 0xc0, 0xeb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ldlcx #0xd0003f80" + - + input: + bytes: [ 0x1e, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0x1, #0x4" + - + input: + bytes: [ 0xdf, 0x09, 0xf6, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d9, #0, #-0x14" + - + input: + bytes: [ 0x3b, 0x00, 0x98, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x980" + - + input: + bytes: [ 0xb7, 0x0f, 0x03, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0, #0x3" + - + input: + bytes: [ 0x76, 0x87 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d8, #0xe" + - + input: + bytes: [ 0xda, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0xff" + - + input: + bytes: [ 0x8f, 0x3f, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d15, #0x3" + - + input: + bytes: [ 0x7f, 0xf1, 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d1, d15, #0xc" + - + input: + bytes: [ 0xda, 0xbc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0xbc" + - + input: + bytes: [ 0x6d, 0x00, 0xd4, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xda8" + - + input: + bytes: [ 0x6d, 0x00, 0xb9, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xd72" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0xd7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a13, #0x7000" + - + input: + bytes: [ 0x2e, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #0xa" + - + input: + bytes: [ 0x8f, 0x1f, 0x1e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d0, d15, #-0x1f" + - + input: + bytes: [ 0x26, 0x3f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d3" + - + input: + bytes: [ 0x6d, 0xff, 0xee, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xc24" + - + input: + bytes: [ 0x8f, 0x46, 0x1f, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d6, #-0xc" + - + input: + bytes: [ 0x4b, 0x00, 0x61, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "utof d15, d0" + - + input: + bytes: [ 0x8b, 0xcf, 0x01, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d15, #0x1c" + - + input: + bytes: [ 0x4e, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jgtz d15, #0x8" + - + input: + bytes: [ 0xb7, 0x0f, 0x81, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d2, d15, #0, #0x1f, #0x1" + - + input: + bytes: [ 0x26, 0x94 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d4, d9" + - + input: + bytes: [ 0x8f, 0x84, 0x1e, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d4, #-0x18" + - + input: + bytes: [ 0x6d, 0xff, 0x84, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2f8" + - + input: + bytes: [ 0x6d, 0x00, 0x0e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1c" + - + input: + bytes: [ 0xbb, 0x70, 0x71, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d15, #0xb717" + - + input: + bytes: [ 0x6d, 0x00, 0x14, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x228" + - + input: + bytes: [ 0x3b, 0x80, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x8" + - + input: + bytes: [ 0x3b, 0x00, 0x02, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x20" + - + input: + bytes: [ 0x8f, 0x1a, 0x40, 0xa1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d10, d10, #0x1" + - + input: + bytes: [ 0x6d, 0xff, 0xbd, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xc86" + - + input: + bytes: [ 0x3f, 0x40, 0xe3, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, d4, #-0x3a" + - + input: + bytes: [ 0x0b, 0x20, 0x50, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ge.u d15, d0, d2" + - + input: + bytes: [ 0x6d, 0xff, 0x6b, 0x4b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1692a" + - + input: + bytes: [ 0x6d, 0x00, 0xdc, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x13b8" + - + input: + bytes: [ 0x6d, 0xff, 0xaa, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xac" + - + input: + bytes: [ 0x5f, 0x10, 0x09, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d0, d1, #0x12" + - + input: + bytes: [ 0xa2, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d0, d1" + - + input: + bytes: [ 0x5f, 0xef, 0x67, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d14, #0xce" + - + input: + bytes: [ 0x49, 0xa5, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [sp]#0" + - + input: + bytes: [ 0xdf, 0x0c, 0x86, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d12, #0, #-0xf4" + - + input: + bytes: [ 0x4e, 0x33 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jgtz d3, #0x6" + - + input: + bytes: [ 0x09, 0xff, 0xb6, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d15, [a15]#0x36" + - + input: + bytes: [ 0x3f, 0xf2, 0x05, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d2, d15, #0xa" + - + input: + bytes: [ 0x3b, 0x80, 0x3e, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x3e8" + - + input: + bytes: [ 0x76, 0x8e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d8, #0x1c" + - + input: + bytes: [ 0x3c, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x14" + - + input: + bytes: [ 0x6e, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x42" + - + input: + bytes: [ 0xdf, 0x1f, 0xf3, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0x1, #-0x1a" + - + input: + bytes: [ 0x46, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "not d6" + - + input: + bytes: [ 0x61, 0xff, 0xfb, 0xd8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x4e0a" + - + input: + bytes: [ 0x82, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d9, #0x1" + - + input: + bytes: [ 0xae, 0x13 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0x1, #0x6" + - + input: + bytes: [ 0x4b, 0x0f, 0x41, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d1, d15, d0" + - + input: + bytes: [ 0x8b, 0x12, 0x80, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addx d2, d2, #0x1" + - + input: + bytes: [ 0x49, 0xa4, 0x04, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [sp]#0x4" + - + input: + bytes: [ 0x6d, 0xff, 0x84, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xaf8" + - + input: + bytes: [ 0xa6, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d2, d15" + - + input: + bytes: [ 0x40, 0xc5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a5, a12" + - + input: + bytes: [ 0xda, 0x2b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x2b" + - + input: + bytes: [ 0x4b, 0x00, 0x71, 0x61 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftouz d6, d0" + - + input: + bytes: [ 0xd9, 0x55, 0x6c, 0x2a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5b54" + - + input: + bytes: [ 0xd9, 0xff, 0xc4, 0x31 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x1cc4" + - + input: + bytes: [ 0x6d, 0x00, 0x32, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x64" + - + input: + bytes: [ 0x91, 0x20, 0x00, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0x8002" + - + input: + bytes: [ 0x8f, 0x00, 0x21, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d1, d0, #0x10" + - + input: + bytes: [ 0x40, 0x5c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a12, a5" + - + input: + bytes: [ 0x02, 0x79 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d9, d7" + - + input: + bytes: [ 0xac, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a15]#0x18, d15" + - + input: + bytes: [ 0x6f, 0x3f, 0x37, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x3, #0x6e" + - + input: + bytes: [ 0x6f, 0x29, 0x19, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d9, #0x2, #0x32" + - + input: + bytes: [ 0x40, 0xc4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a4, a12" + - + input: + bytes: [ 0x3f, 0x8b, 0xe7, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d11, d8, #-0x32" + - + input: + bytes: [ 0x26, 0x53 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d3, d5" + - + input: + bytes: [ 0xb7, 0x0f, 0x81, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0x1, #0x1" + - + input: + bytes: [ 0xd9, 0xff, 0xf0, 0xaa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x5150" + - + input: + bytes: [ 0xc2, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d10, #-0x1" + - + input: + bytes: [ 0x6d, 0x00, 0x69, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2d2" + - + input: + bytes: [ 0xd9, 0xff, 0x28, 0xa6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x62a8" + - + input: + bytes: [ 0x91, 0x30, 0x00, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0xf003" + - + input: + bytes: [ 0x6f, 0x3f, 0x2f, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x3, #0x5e" + - + input: + bytes: [ 0x6d, 0x00, 0x44, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x888" + - + input: + bytes: [ 0x6d, 0xff, 0xd0, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xe60" + - + input: + bytes: [ 0x37, 0x04, 0x50, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d4, d4, #0, #0x10" + - + input: + bytes: [ 0x6d, 0xff, 0x9d, 0x2d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1a4c6" + - + input: + bytes: [ 0x8b, 0xc8, 0x01, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d8, #0x1c" + - + input: + bytes: [ 0xbb, 0x90, 0xff, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d0, #0xfff9" + - + input: + bytes: [ 0x89, 0xff, 0xa2, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a15]#0x22, d15" + - + input: + bytes: [ 0xff, 0x28, 0xf6, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d8, #0x2, #-0x14" + - + input: + bytes: [ 0x01, 0xcf, 0x20, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.a a2, a15, a12" + - + input: + bytes: [ 0x3c, 0x16 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x2c" + - + input: + bytes: [ 0x0b, 0x8f, 0x10, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e4, d15, d8" + - + input: + bytes: [ 0xa6, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d2, d0" + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d4, d15, #0x3f" + - + input: + bytes: [ 0xd9, 0xff, 0x8c, 0xea ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x5474" + - + input: + bytes: [ 0x8b, 0x0d, 0x00, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.ne d15, d13, #0" + - + input: + bytes: [ 0x49, 0x33, 0x08, 0x8a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a3, [a3]#-0x1f8" + - + input: + bytes: [ 0x57, 0x0f, 0x61, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, d0, #0x1" + - + input: + bytes: [ 0x4b, 0x0f, 0x51, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d0, d15, d0" + - + input: + bytes: [ 0x2e, 0x38 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x3, #0x10" + - + input: + bytes: [ 0xde, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x20" + - + input: + bytes: [ 0x37, 0x0f, 0x68, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d4, d15, #0, #0x8" + - + input: + bytes: [ 0x82, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d11, #0x1" + - + input: + bytes: [ 0x7d, 0xc2, 0x05, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne.a a2, a12, #0xa" + - + input: + bytes: [ 0x2e, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x2, #0xc" + - + input: + bytes: [ 0x0b, 0x75, 0xa0, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.lt.u d15, d5, d7" + - + input: + bytes: [ 0x3f, 0xf1, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d1, d15, #0x14" + - + input: + bytes: [ 0x02, 0x95 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d5, d9" + - + input: + bytes: [ 0xda, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x17" + - + input: + bytes: [ 0x6d, 0xff, 0x46, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x774" + - + input: + bytes: [ 0x49, 0xdd, 0x10, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a13, [a13]#0x10" + - + input: + bytes: [ 0xd9, 0xff, 0x38, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0xb8" + - + input: + bytes: [ 0x6d, 0x00, 0x24, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x3448" + - + input: + bytes: [ 0x3f, 0xbf, 0xf8, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d15, d11, #-0x10" + - + input: + bytes: [ 0xbd, 0x0c, 0x79, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.a a12, #0xf2" + - + input: + bytes: [ 0x0b, 0x2f, 0xa0, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "max d15, d15, d2" + - + input: + bytes: [ 0x1d, 0x00, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x10" + - + input: + bytes: [ 0x4b, 0x10, 0x41, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d0, d0, d1" + - + input: + bytes: [ 0xd9, 0xee, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a14, [a14]#0x3c8" + - + input: + bytes: [ 0xdf, 0x2d, 0x05, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d13, #0x2, #0xa" + - + input: + bytes: [ 0xa6, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d0, d15" + - + input: + bytes: [ 0x6e, 0x2d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x5a" + - + input: + bytes: [ 0x4b, 0x0f, 0x71, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftouz d15, d15" + - + input: + bytes: [ 0xbb, 0x00, 0xc2, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d15, #0xbc20" + - + input: + bytes: [ 0x8b, 0xff, 0x00, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d4, d15, #0xf" + - + input: + bytes: [ 0x7f, 0x0f, 0x04, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d15, d0, #0x8" + - + input: + bytes: [ 0x4b, 0x0a, 0x41, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d10, d10, d0" + - + input: + bytes: [ 0x61, 0xff, 0x77, 0xda ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x4b12" + - + input: + bytes: [ 0x3c, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x4" + - + input: + bytes: [ 0xee, 0x37 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x6e" + - + input: + bytes: [ 0x6d, 0xff, 0x33, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x39a" + - + input: + bytes: [ 0x8f, 0x21, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, d1, #0x2" + - + input: + bytes: [ 0xb0, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a12, #-0x1" + - + input: + bytes: [ 0x61, 0xff, 0x41, 0xd9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x4d7e" + - + input: + bytes: [ 0x8b, 0x1f, 0xe0, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.eq d2, d15, #0x1" + - + input: + bytes: [ 0xdf, 0x1f, 0xfe, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0x1, #-0x4" + - + input: + bytes: [ 0x6d, 0x00, 0x15, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x82a" + - + input: + bytes: [ 0xdf, 0x02, 0xf9, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d2, #0, #-0xe" + - + input: + bytes: [ 0x82, 0x2d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d13, #0x2" + - + input: + bytes: [ 0x91, 0x10, 0x00, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x5001" + - + input: + bytes: [ 0x6d, 0xff, 0x1b, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1ca" + - + input: + bytes: [ 0x49, 0xaf, 0x0b, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [sp]#0xb" + - + input: + bytes: [ 0x3e, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0xe" + - + input: + bytes: [ 0x6d, 0x00, 0xa7, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x114e" + - + input: + bytes: [ 0x8b, 0x14, 0x1f, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d4, #-0xf" + - + input: + bytes: [ 0x2e, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #0x1e" + - + input: + bytes: [ 0xda, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x7" + - + input: + bytes: [ 0x40, 0xc6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a6, a12" + - + input: + bytes: [ 0x6d, 0xff, 0xa0, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xac0" + - + input: + bytes: [ 0x15, 0xd0, 0xc0, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "stucx #0xd0003fc0" + - + input: + bytes: [ 0x4b, 0xf1, 0x01, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div e2, d1, d15" + - + input: + bytes: [ 0xa2, 0x5f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d15, d5" + - + input: + bytes: [ 0x76, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d2, #0x12" + - + input: + bytes: [ 0xfc, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a15, #-0x14" + - + input: + bytes: [ 0x6d, 0x00, 0xe0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xbc0" + - + input: + bytes: [ 0x8f, 0x80, 0x20, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d1, d0, #0x8" + - + input: + bytes: [ 0x3e, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x8" + - + input: + bytes: [ 0x6d, 0xe8, 0x3d, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2fbb86" + - + input: + bytes: [ 0xc2, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d11, #-0x1" + - + input: + bytes: [ 0x0b, 0x15, 0x80, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.ne d15, d5, d1" + - + input: + bytes: [ 0x6d, 0x00, 0x73, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1ee6" + - + input: + bytes: [ 0x3b, 0xc0, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0xc" + - + input: + bytes: [ 0xd9, 0xff, 0x50, 0xea ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x5870" + - + input: + bytes: [ 0xd9, 0x55, 0x7c, 0x4a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5ac4" + - + input: + bytes: [ 0x6f, 0x10, 0xf8, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d0, #0x1, #-0x10" + - + input: + bytes: [ 0x0f, 0xcb, 0x10, 0xb0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d11, d11, d12" + - + input: + bytes: [ 0x32, 0x5a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsub d10" + - + input: + bytes: [ 0x8b, 0x01, 0x20, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne d15, d1, #0" + - + input: + bytes: [ 0x3f, 0x0f, 0xfd, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d15, d0, #-0x6" + - + input: + bytes: [ 0x3f, 0xf9, 0x65, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d9, d15, #-0x136" + - + input: + bytes: [ 0x20, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.a sp, #0x50" + - + input: + bytes: [ 0xe2, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d0, d15" + - + input: + bytes: [ 0xff, 0x18, 0xe9, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d8, #0x1, #-0x2e" + - + input: + bytes: [ 0xd9, 0x44, 0x14, 0x7d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#-0x2e2c" + - + input: + bytes: [ 0xd9, 0x44, 0xec, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0xc6c" + - + input: + bytes: [ 0x3b, 0x10, 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x61" + - + input: + bytes: [ 0x6d, 0x00, 0xf2, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x5e4" + - + input: + bytes: [ 0xbc, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.a a2, #0xc" + - + input: + bytes: [ 0x01, 0xca, 0x00, 0x56 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a5, a12, d10, #0" + - + input: + bytes: [ 0x7f, 0x0f, 0x55, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d15, d0, #0xaa" + - + input: + bytes: [ 0x8f, 0x4f, 0x1f, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d1, d15, #-0xc" + - + input: + bytes: [ 0x6d, 0xff, 0x9e, 0x4c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x166c4" + - + input: + bytes: [ 0x6e, 0x55 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0xaa" + - + input: + bytes: [ 0x46, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "not d7" + - + input: + bytes: [ 0xa6, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d2" + - + input: + bytes: [ 0x7f, 0x89, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d9, d8, #0x10" + - + input: + bytes: [ 0x0f, 0x02, 0x00, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d2, d0" + - + input: + bytes: [ 0x6e, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x24" + - + input: + bytes: [ 0x6d, 0x00, 0x2d, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1c5a" + - + input: + bytes: [ 0x10, 0xcf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, a12, d15, #0" + - + input: + bytes: [ 0x3f, 0x21, 0xf9, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d1, d2, #-0xe" + - + input: + bytes: [ 0x06, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d0, #0x5" + - + input: + bytes: [ 0xbf, 0xc0, 0xea, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, #0xc, #-0x2c" + - + input: + bytes: [ 0x3e, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d1, #0x4" + - + input: + bytes: [ 0x06, 0x15 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d5, #0x1" + - + input: + bytes: [ 0x53, 0x48, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d8, #0x4" + - + input: + bytes: [ 0x3e, 0xeb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d14, #0x16" + - + input: + bytes: [ 0xbb, 0x00, 0x40, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d2, #0xf400" + - + input: + bytes: [ 0x3f, 0xf2, 0xf3, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d2, d15, #-0x1a" + - + input: + bytes: [ 0x3b, 0xb0, 0x02, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x2b" + - + input: + bytes: [ 0x37, 0x01, 0x10, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d1, d1, d0, #0, #0x10" + - + input: + bytes: [ 0x49, 0xfc, 0x3f, 0x2a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a12, [a15]#0xbf" + - + input: + bytes: [ 0xac, 0x44 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a4]#0x8, d15" + - + input: + bytes: [ 0xd9, 0x22, 0x1a, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x109a" + - + input: + bytes: [ 0x37, 0x0f, 0x81, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x5, #0x1" + - + input: + bytes: [ 0x02, 0x2a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d10, d2" + - + input: + bytes: [ 0xa2, 0xaf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d15, d10" + - + input: + bytes: [ 0x6e, 0xc9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #-0x6e" + - + input: + bytes: [ 0x0b, 0x31, 0x00, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.eq d15, d1, d3" + - + input: + bytes: [ 0x02, 0xb2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, d11" + - + input: + bytes: [ 0xd9, 0xff, 0x30, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x70" + - + input: + bytes: [ 0xd9, 0xff, 0xb4, 0xe1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x1bb4" + - + input: + bytes: [ 0x4b, 0x80, 0x11, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.u e0, d0, d8" + - + input: + bytes: [ 0x37, 0x0f, 0x01, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0, #0x1" + - + input: + bytes: [ 0xd9, 0xff, 0xf8, 0xea ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x5048" + - + input: + bytes: [ 0x6d, 0x00, 0xf7, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1ee" + - + input: + bytes: [ 0xb0, 0x1d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a13, #0x1" + - + input: + bytes: [ 0x16, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0x2" + - + input: + bytes: [ 0x6d, 0xff, 0xc6, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x74" + - + input: + bytes: [ 0x3c, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x5e" + - + input: + bytes: [ 0xfc, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a2, #-0xe" + - + input: + bytes: [ 0xa0, 0x15 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a5, #0x1" + - + input: + bytes: [ 0x5f, 0x0f, 0x5d, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0xba" + - + input: + bytes: [ 0x20, 0x18 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.a sp, #0x18" + - + input: + bytes: [ 0x6b, 0x05, 0x00, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "pack d2, e0, d5" + - + input: + bytes: [ 0x07, 0xbb, 0x9f, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "nand.t d15, d11, #0x1f, d11, #0x1f" + - + input: + bytes: [ 0x6d, 0x00, 0x93, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1126" + - + input: + bytes: [ 0x6d, 0x00, 0xe8, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1bd0" + - + input: + bytes: [ 0x82, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, #0" + - + input: + bytes: [ 0x7d, 0x42, 0x0f, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne.a a2, a4, #0x1e" + - + input: + bytes: [ 0xac, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a15]#0x14, d15" + - + input: + bytes: [ 0x6e, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x8" + - + input: + bytes: [ 0xdf, 0x08, 0xf9, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d8, #0, #-0xe" + - + input: + bytes: [ 0x6d, 0x00, 0xca, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2194" + - + input: + bytes: [ 0x4b, 0xf8, 0x01, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div e0, d8, d15" + - + input: + bytes: [ 0x02, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, d2" + - + input: + bytes: [ 0xa0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a4, #0" + - + input: + bytes: [ 0x0f, 0x0a, 0x80, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d1, d10, d0" + - + input: + bytes: [ 0x0f, 0xcf, 0x00, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d15, d12" + - + input: + bytes: [ 0x8b, 0x05, 0xc0, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eqany.b d15, d5, #0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne d0, d0, #0" + - + input: + bytes: [ 0x7d, 0x2e, 0x0c, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne.a a14, a2, #0x18" + - + input: + bytes: [ 0x6f, 0x29, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d9, #0x2, #0xd0" + - + input: + bytes: [ 0x6d, 0xff, 0x5f, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x742" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a5, #0x7000" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a8, #0" + - + input: + bytes: [ 0xc2, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, #-0x1" + - + input: + bytes: [ 0x6d, 0x00, 0x3b, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xa76" + - + input: + bytes: [ 0x3c, 0xd9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x4e" + - + input: + bytes: [ 0x7e, 0xe5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d14, #0xa" + - + input: + bytes: [ 0x6d, 0xff, 0x3f, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x182" + - + input: + bytes: [ 0x6d, 0x00, 0x5e, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1ebc" + - + input: + bytes: [ 0x96, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x40" + - + input: + bytes: [ 0x37, 0x01, 0x70, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d2, d1, #0, #0x10" + - + input: + bytes: [ 0x1e, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #-0x1, #0x8" + - + input: + bytes: [ 0x76, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d0, #0x6" + - + input: + bytes: [ 0x6d, 0x00, 0x50, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2a0" + - + input: + bytes: [ 0x0b, 0x1b, 0x90, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.lt d15, d11, d1" + - + input: + bytes: [ 0x80, 0xdf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d15, a13" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x6000" + - + input: + bytes: [ 0x37, 0x00, 0xe1, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0x1, #0x1" + - + input: + bytes: [ 0xd9, 0xff, 0x1c, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0xdc" + - + input: + bytes: [ 0x02, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, d4" + - + input: + bytes: [ 0x91, 0x20, 0x00, 0x58 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a5, #0x8002" + - + input: + bytes: [ 0x6d, 0xff, 0x4c, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x968" + - + input: + bytes: [ 0x3b, 0x00, 0x00, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x3000" + - + input: + bytes: [ 0x37, 0xf0, 0x01, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0x6, #0x1" + - + input: + bytes: [ 0x4b, 0x02, 0x41, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d15, d2, d0" + - + input: + bytes: [ 0xc6, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d0, d15" + - + input: + bytes: [ 0x6e, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x32" + - + input: + bytes: [ 0x76, 0x55 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d5, #0xa" + - + input: + bytes: [ 0x42, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d4, d15" + - + input: + bytes: [ 0xee, 0xd2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0x5c" + - + input: + bytes: [ 0x5e, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x2, #0xc" + - + input: + bytes: [ 0x3c, 0x13 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x26" + - + input: + bytes: [ 0x10, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a15, d15, #0" + - + input: + bytes: [ 0x2d, 0x07, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "calli a7" + - + input: + bytes: [ 0x6f, 0x2f, 0x17, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x2, #0x2e" + - + input: + bytes: [ 0x4b, 0xf5, 0x41, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d3, d5, d15" + - + input: + bytes: [ 0x3c, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xe" + - + input: + bytes: [ 0x7f, 0x0f, 0x4d, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d15, d0, #0x9a" + - + input: + bytes: [ 0xa6, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d0" + - + input: + bytes: [ 0x89, 0x4f, 0xb4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a4]#0x34, d15" + - + input: + bytes: [ 0x6d, 0x00, 0xbd, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1d7a" + - + input: + bytes: [ 0x91, 0x00, 0x06, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x8060" + - + input: + bytes: [ 0xdf, 0x12, 0x11, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d2, #0x1, #0x22" + - + input: + bytes: [ 0x0b, 0x0a, 0x10, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne d15, d10, d0" + - + input: + bytes: [ 0x3c, 0x4c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x98" + - + input: + bytes: [ 0xda, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x1b" + - + input: + bytes: [ 0xbb, 0xf0, 0xf7, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d4, #0xff7f" + - + input: + bytes: [ 0x26, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d1, d15" + - + input: + bytes: [ 0xbd, 0x04, 0x11, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.a a4, #0x22" + - + input: + bytes: [ 0x26, 0x82 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d2, d8" + - + input: + bytes: [ 0xc2, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d1, #0x1" + - + input: + bytes: [ 0x4b, 0x06, 0x61, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "utof d0, d6" + - + input: + bytes: [ 0x3f, 0xf8, 0xf3, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d8, d15, #-0x1a" + - + input: + bytes: [ 0x37, 0xf0, 0x02, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0xc, #0x2" + - + input: + bytes: [ 0x6d, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x160" + - + input: + bytes: [ 0x3b, 0xf0, 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x6f" + - + input: + bytes: [ 0x4b, 0xf2, 0x51, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d8, d2, d15" + - + input: + bytes: [ 0x37, 0x09, 0x68, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d9, d9, #0, #0x8" + - + input: + bytes: [ 0xa2, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d15, d2" + - + input: + bytes: [ 0x3c, 0x45 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x8a" + - + input: + bytes: [ 0x5e, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #-0x1, #0xa" + - + input: + bytes: [ 0x10, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a4, a2, d15, #0" + - + input: + bytes: [ 0x7e, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x8" + - + input: + bytes: [ 0xda, 0x2d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x2d" + - + input: + bytes: [ 0x6d, 0xff, 0x4d, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xb66" + - + input: + bytes: [ 0xdf, 0x0c, 0x9b, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d12, #0, #-0xca" + - + input: + bytes: [ 0x40, 0x54 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a4, a5" + - + input: + bytes: [ 0x4b, 0xf9, 0x41, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d5, d9, d15" + - + input: + bytes: [ 0xd9, 0xee, 0x14, 0xe0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a14, [a14]#0x394" + - + input: + bytes: [ 0x8b, 0x08, 0x08, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsub d15, d8, #0x80" + - + input: + bytes: [ 0x01, 0xcd, 0x00, 0xc6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a12, a12, d13, #0" + - + input: + bytes: [ 0xd9, 0x55, 0xa8, 0xca ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x54d8" + - + input: + bytes: [ 0x6d, 0x00, 0x16, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2c" + - + input: + bytes: [ 0xb7, 0x6f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x6, #0, #0x8" + - + input: + bytes: [ 0x6d, 0xff, 0x07, 0xd5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x55f2" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e4, d0" + - + input: + bytes: [ 0x49, 0xa5, 0x04, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [sp]#0x4" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x200" + - + input: + bytes: [ 0x40, 0xef ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a15, a14" + - + input: + bytes: [ 0x6e, 0x65 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0xca" + - + input: + bytes: [ 0xfa, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt d15, d0, #0x1" + - + input: + bytes: [ 0x26, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d0" + - + input: + bytes: [ 0x0b, 0x60, 0x30, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt.u d15, d0, d6" + - + input: + bytes: [ 0x6d, 0x00, 0xf2, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x23e4" + - + input: + bytes: [ 0x49, 0xaa, 0x38, 0xba ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea sp, [sp]#-0x108" + - + input: + bytes: [ 0x0b, 0x51, 0x00, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.eq d15, d1, d5" + - + input: + bytes: [ 0x0f, 0x13, 0x00, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d3, d3, d1" + - + input: + bytes: [ 0xd9, 0xff, 0x14, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0xd4" + - + input: + bytes: [ 0x3f, 0x0f, 0xeb, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d15, d0, #-0x2a" + - + input: + bytes: [ 0xb7, 0x04, 0x89, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d4, #0, #0x17, #0x9" + - + input: + bytes: [ 0xb7, 0x5f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x5, #0, #0x8" + - + input: + bytes: [ 0x6d, 0x00, 0x09, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x12" + - + input: + bytes: [ 0x0b, 0x60, 0x40, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addx d4, d0, d6" + - + input: + bytes: [ 0xbe, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x3a" + - + input: + bytes: [ 0x8b, 0xf0, 0x1b, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d0, #-0x41" + - + input: + bytes: [ 0x6d, 0x00, 0x8e, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x31c" + - + input: + bytes: [ 0x1d, 0xff, 0xbe, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x484" + - + input: + bytes: [ 0xd9, 0x44, 0xe8, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0xc68" + - + input: + bytes: [ 0x8f, 0x8f, 0x01, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d15, #0x18" + - + input: + bytes: [ 0xd9, 0xff, 0x80, 0xea ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x5480" + - + input: + bytes: [ 0x26, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d9, d15" + - + input: + bytes: [ 0x6f, 0x20, 0xf2, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d0, #0x2, #-0x1c" + - + input: + bytes: [ 0x4b, 0xaf, 0x01, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmp.f d15, d15, d10" + - + input: + bytes: [ 0x8b, 0x07, 0xa0, 0x70 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addc d7, d7, #0" + - + input: + bytes: [ 0x49, 0xa5, 0x00, 0x4a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [sp]#0x100" + - + input: + bytes: [ 0xdf, 0x10, 0x0a, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d0, #0x1, #0x14" + - + input: + bytes: [ 0x1d, 0x00, 0x98, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x130" + - + input: + bytes: [ 0x4b, 0x00, 0x41, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "itof d0, d0" + - + input: + bytes: [ 0x3b, 0xd0, 0x02, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, #0x2d" + - + input: + bytes: [ 0x02, 0xb1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, d11" + - + input: + bytes: [ 0x6d, 0x00, 0x0a, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2214" + - + input: + bytes: [ 0x3b, 0xf0, 0x0f, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0xff" + - + input: + bytes: [ 0x40, 0xa2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a2, sp" + - + input: + bytes: [ 0xc2, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d11, #0x1" + - + input: + bytes: [ 0xdf, 0x0f, 0xb1, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0, #0x162" + - + input: + bytes: [ 0xc2, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d1, #-0x1" + - + input: + bytes: [ 0x89, 0xaf, 0xa2, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x22, d15" + - + input: + bytes: [ 0x3b, 0x40, 0x07, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x74" + - + input: + bytes: [ 0xdf, 0x12, 0x03, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d2, #0x1, #0x6" + - + input: + bytes: [ 0x3c, 0x6e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xdc" + - + input: + bytes: [ 0x82, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #0x1" + - + input: + bytes: [ 0x7c, 0x23 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.a a2, #0x6" + - + input: + bytes: [ 0x6d, 0xff, 0x80, 0x4c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x16700" + - + input: + bytes: [ 0x3b, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x6000" + - + input: + bytes: [ 0x37, 0xf0, 0x01, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0x1e, #0x1" + - + input: + bytes: [ 0x37, 0x00, 0x70, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d10, d0, #0, #0x10" + - + input: + bytes: [ 0xac, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a15]#0x10, d15" + - + input: + bytes: [ 0x16, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0x7" + - + input: + bytes: [ 0x7b, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d0, #0x4200" + - + input: + bytes: [ 0x5f, 0x0f, 0xf4, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #-0x18" + - + input: + bytes: [ 0x6d, 0x00, 0xd6, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x5ac" + - + input: + bytes: [ 0xbb, 0x80, 0x02, 0x4a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d4, #0xa028" + - + input: + bytes: [ 0x02, 0x69 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d9, d6" + - + input: + bytes: [ 0x3e, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d2, #0x8" + - + input: + bytes: [ 0x37, 0x00, 0xe7, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0x1, #0x7" + - + input: + bytes: [ 0x8b, 0x0f, 0x1d, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d15, #-0x30" + - + input: + bytes: [ 0x8f, 0x0a, 0x41, 0xa1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d10, d10, #0x10" + - + input: + bytes: [ 0xdf, 0x02, 0xf8, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d2, #0, #-0x10" + - + input: + bytes: [ 0x6d, 0x00, 0xf4, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1be8" + - + input: + bytes: [ 0x37, 0x03, 0x68, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d3, #0x8, #0x8" + - + input: + bytes: [ 0x37, 0x01, 0xe1, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d1, d1, #0xf, #0x1" + - + input: + bytes: [ 0xbb, 0x00, 0x20, 0x4c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d4, #0xc200" + - + input: + bytes: [ 0xac, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a4]#0x12, d15" + - + input: + bytes: [ 0x3c, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x52" + - + input: + bytes: [ 0x49, 0xaf, 0x0a, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [sp]#0xa" + - + input: + bytes: [ 0x53, 0x20, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d0, #0x2" + - + input: + bytes: [ 0x37, 0x00, 0xe1, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0xf, #0x1" + - + input: + bytes: [ 0x09, 0x44, 0x94, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d4, [a4]#0x14" + - + input: + bytes: [ 0x01, 0x24, 0x00, 0x46 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a4, a2, d4, #0" + - + input: + bytes: [ 0x8b, 0xff, 0x0f, 0xc2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq d12, d15, #0xff" + - + input: + bytes: [ 0x37, 0x09, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d9, #0, #0x10" + - + input: + bytes: [ 0xfd, 0xf0, 0xed, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a15, #-0x26" + - + input: + bytes: [ 0x6d, 0x00, 0xb0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x760" + - + input: + bytes: [ 0xda, 0x75 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x75" + - + input: + bytes: [ 0x9b, 0xe2, 0xcb, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d2, d2, #0x4cbe" + - + input: + bytes: [ 0x6d, 0x00, 0x11, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x22" + - + input: + bytes: [ 0x37, 0xf0, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0, #0x8" + - + input: + bytes: [ 0x46, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "not d0" + - + input: + bytes: [ 0x26, 0x93 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d3, d9" + - + input: + bytes: [ 0x6e, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0xe" + - + input: + bytes: [ 0xdf, 0x0a, 0x33, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d10, #0, #0x66" + - + input: + bytes: [ 0xee, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0xe" + - + input: + bytes: [ 0x6d, 0xff, 0xf3, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x21a" + - + input: + bytes: [ 0x09, 0xf0, 0xba, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d0, [a15]#0x3a" + - + input: + bytes: [ 0x8f, 0x14, 0x1e, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d2, d4, #-0x1f" + - + input: + bytes: [ 0x6d, 0x00, 0xb4, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1d68" + - + input: + bytes: [ 0xee, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x14" + - + input: + bytes: [ 0x01, 0x54, 0x20, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt.a d15, a4, a5" + - + input: + bytes: [ 0xdf, 0x08, 0x11, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d8, #0, #0x22" + - + input: + bytes: [ 0x8f, 0x23, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, d3, #0x2" + - + input: + bytes: [ 0x6d, 0xff, 0xdd, 0x2a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1aa46" + - + input: + bytes: [ 0x6d, 0x00, 0xf8, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x23f0" + - + input: + bytes: [ 0xee, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x16" + - + input: + bytes: [ 0xd9, 0xff, 0x00, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0xc0" + - + input: + bytes: [ 0xd9, 0x3f, 0x0c, 0x96 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a3]#0x624c" + - + input: + bytes: [ 0x26, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d3" + - + input: + bytes: [ 0x3c, 0x2b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x56" + - + input: + bytes: [ 0x6d, 0xff, 0x25, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3b6" + - + input: + bytes: [ 0x3f, 0x0f, 0xf6, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d15, d0, #-0x14" + - + input: + bytes: [ 0x3b, 0x00, 0x40, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x1400" + - + input: + bytes: [ 0x02, 0x51 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, d5" + - + input: + bytes: [ 0x46, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "not d2" + - + input: + bytes: [ 0xd9, 0x22, 0x32, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x1072" + - + input: + bytes: [ 0x06, 0xd5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d5, #-0x3" + - + input: + bytes: [ 0xdc, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ji a15" + - + input: + bytes: [ 0x0b, 0x89, 0x10, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e4, d9, d8" + - + input: + bytes: [ 0x80, 0xcf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d15, a12" + - + input: + bytes: [ 0x6d, 0x00, 0x28, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1e50" + - + input: + bytes: [ 0x76, 0x83 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d8, #0x6" + - + input: + bytes: [ 0x6d, 0xe8, 0xcf, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2fbe62" + - + input: + bytes: [ 0x76, 0xc5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d12, #0xa" + - + input: + bytes: [ 0x3b, 0x10, 0x08, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x81" + - + input: + bytes: [ 0xda, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x2" + - + input: + bytes: [ 0x13, 0xa9, 0x20, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd d15, d15, d9, #0xa" + - + input: + bytes: [ 0x49, 0xaa, 0x30, 0xba ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea sp, [sp]#-0x110" + - + input: + bytes: [ 0x40, 0xe2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a2, a14" + - + input: + bytes: [ 0x9b, 0xc0, 0xdc, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d0, d0, #0x3dcc" + - + input: + bytes: [ 0x3e, 0x47 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d4, #0xe" + - + input: + bytes: [ 0x6d, 0xff, 0x76, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xd14" + - + input: + bytes: [ 0xdf, 0x08, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d8, #0, #0x80" + - + input: + bytes: [ 0x6d, 0xff, 0x92, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xadc" + - + input: + bytes: [ 0x09, 0xf0, 0xd4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a15]#0x14" + - + input: + bytes: [ 0x6e, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x28" + - + input: + bytes: [ 0xc2, 0x2b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d11, #0x2" + - + input: + bytes: [ 0x6b, 0x0e, 0x21, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.f d15, d15, d14" + - + input: + bytes: [ 0x3b, 0xf0, 0x0f, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0xff" + - + input: + bytes: [ 0xd9, 0xff, 0x08, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x48" + - + input: + bytes: [ 0x6e, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0xa" + - + input: + bytes: [ 0x80, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d0, a2" + - + input: + bytes: [ 0xd9, 0x44, 0xfc, 0xb5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x5efc" + - + input: + bytes: [ 0x61, 0xff, 0x86, 0xd4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x56f4" + - + input: + bytes: [ 0x89, 0x40, 0x94, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a4]#0x14, d0" + - + input: + bytes: [ 0x6f, 0x8a, 0x45, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d10, #0x8, #0x8a" + - + input: + bytes: [ 0x5e, 0x2d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x2, #0x1a" + - + input: + bytes: [ 0x8b, 0xff, 0x01, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsub d15, d15, #0x1f" + - + input: + bytes: [ 0xdf, 0x00, 0x31, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d0, #0, #0x62" + - + input: + bytes: [ 0xbb, 0xb0, 0xff, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d15, #0xfffb" + - + input: + bytes: [ 0xd9, 0x55, 0x68, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5b98" + - + input: + bytes: [ 0x76, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d0, #0xa" + - + input: + bytes: [ 0x6d, 0x00, 0x7f, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xfe" + - + input: + bytes: [ 0x40, 0x6f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a15, a6" + - + input: + bytes: [ 0x61, 0xff, 0x95, 0xd4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x56d6" + - + input: + bytes: [ 0x3c, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x1a" + - + input: + bytes: [ 0xa2, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d12, d15" + - + input: + bytes: [ 0x5f, 0x8f, 0xef, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d8, #0x1de" + - + input: + bytes: [ 0x6d, 0x00, 0x8a, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1b14" + - + input: + bytes: [ 0xd9, 0xff, 0x90, 0x9a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x55b0" + - + input: + bytes: [ 0x82, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, #0" + - + input: + bytes: [ 0x0b, 0x64, 0x30, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt.u d15, d4, d6" + - + input: + bytes: [ 0x6d, 0x00, 0x9f, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1b3e" + - + input: + bytes: [ 0xa6, 0x93 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d3, d9" + - + input: + bytes: [ 0x02, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, d2" + - + input: + bytes: [ 0xda, 0x7e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x7e" + - + input: + bytes: [ 0x3c, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x1c" + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x73" + - + input: + bytes: [ 0xdf, 0x10, 0xee, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d0, #0x1, #-0x24" + - + input: + bytes: [ 0x4b, 0xab, 0x01, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmp.f d15, d11, d10" + - + input: + bytes: [ 0x6f, 0x0f, 0xfc, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0, #-0x8" + - + input: + bytes: [ 0x6f, 0x00, 0x1f, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d0, #0, #0x3e" + - + input: + bytes: [ 0x6e, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x18" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a9, #0" + - + input: + bytes: [ 0x10, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, a15, d15, #0" + - + input: + bytes: [ 0x6d, 0xff, 0x98, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x4d0" + - + input: + bytes: [ 0x40, 0x7d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a13, a7" + - + input: + bytes: [ 0xd9, 0x55, 0x64, 0x3a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5b1c" + - + input: + bytes: [ 0x91, 0x40, 0x00, 0x3f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a3, #0xf004" + - + input: + bytes: [ 0x37, 0x0f, 0xe1, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x7, #0x1" + - + input: + bytes: [ 0x8f, 0x28, 0x00, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d8, #0x2" + - + input: + bytes: [ 0x1d, 0x00, 0x5f, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x2be" + - + input: + bytes: [ 0x6d, 0xff, 0x32, 0xd5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x559c" + - + input: + bytes: [ 0x37, 0x10, 0x01, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d1, #0x2, #0x1" + - + input: + bytes: [ 0x37, 0x02, 0x68, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d2, #0, #0x8" + - + input: + bytes: [ 0x8b, 0x0c, 0x20, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne d15, d12, #0" + - + input: + bytes: [ 0x8b, 0x80, 0x00, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d4, d0, #0x8" + - + input: + bytes: [ 0x46, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "not d5" + - + input: + bytes: [ 0x6d, 0xff, 0x9d, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xc6" + - + input: + bytes: [ 0x26, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d2" + - + input: + bytes: [ 0x3a, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq d15, d6, d2" + - + input: + bytes: [ 0x9b, 0xe0, 0xcb, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d0, d0, #0x4cbe" + - + input: + bytes: [ 0xfc, 0xe7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a14, #-0x12" + - + input: + bytes: [ 0x8f, 0x3f, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d0, d15, #0x3" + - + input: + bytes: [ 0x37, 0x0f, 0x82, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x5, #0x2" + - + input: + bytes: [ 0xc2, 0x1e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d14, #0x1" + - + input: + bytes: [ 0x6e, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x12" + - + input: + bytes: [ 0x3b, 0xe0, 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x6e" + - + input: + bytes: [ 0x8c, 0x4b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d15, [a4]#0x16" + - + input: + bytes: [ 0xb0, 0x42 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a2, #0x4" + - + input: + bytes: [ 0x3b, 0x80, 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x68" + - + input: + bytes: [ 0x0f, 0x0f, 0x10, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, d15, d0" + - + input: + bytes: [ 0xbc, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.a a15, #0x14" + - + input: + bytes: [ 0x0b, 0x71, 0x50, 0xb0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addc d11, d1, d7" + - + input: + bytes: [ 0x42, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d4, d0" + - + input: + bytes: [ 0x7b, 0xa0, 0x47, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d0, #0x447a" + - + input: + bytes: [ 0x0f, 0xf0, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d0, d0, d15" + - + input: + bytes: [ 0x8f, 0x3f, 0x00, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d3, d15, #0x3" + - + input: + bytes: [ 0x37, 0x00, 0x70, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0x10, #0x10" + - + input: + bytes: [ 0x49, 0xa5, 0x10, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [sp]#0x10" + - + input: + bytes: [ 0x37, 0x04, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d4, #0, #0x8" + - + input: + bytes: [ 0xda, 0x37 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x37" + - + input: + bytes: [ 0xd9, 0x44, 0x4c, 0xb0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x6cc" + - + input: + bytes: [ 0x20, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.a sp, #0x28" + - + input: + bytes: [ 0xb7, 0x0f, 0x01, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0x18, #0x1" + - + input: + bytes: [ 0x49, 0x4f, 0x01, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a4]#0x1" + - + input: + bytes: [ 0x6d, 0x00, 0x91, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x122" + - + input: + bytes: [ 0xd9, 0x44, 0x34, 0x8b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#-0x4dcc" + - + input: + bytes: [ 0x4b, 0xfa, 0x51, 0xc0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d12, d10, d15" + - + input: + bytes: [ 0xee, 0x15 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x2a" + - + input: + bytes: [ 0x42, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d15" + - + input: + bytes: [ 0x76, 0xc7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d12, #0xe" + - + input: + bytes: [ 0xd9, 0xff, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x8" + - + input: + bytes: [ 0x3f, 0x1f, 0x05, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d15, d1, #0xa" + - + input: + bytes: [ 0xd9, 0x55, 0x34, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5c0c" + - + input: + bytes: [ 0x76, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d0, #0x8" + - + input: + bytes: [ 0x6d, 0x00, 0xbd, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xf7a" + - + input: + bytes: [ 0x6e, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x14" + - + input: + bytes: [ 0xd9, 0xff, 0x18, 0x60 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x198" + - + input: + bytes: [ 0x40, 0x2c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a12, a2" + - + input: + bytes: [ 0x0b, 0x06, 0x10, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne d15, d6, d0" + - + input: + bytes: [ 0x06, 0x13 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d3, #0x1" + - + input: + bytes: [ 0xab, 0xf5, 0x3f, 0x55 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "caddn d5, d5, d5, #-0x1" + - + input: + bytes: [ 0x3b, 0xc0, 0x05, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d5, #0x5c" + - + input: + bytes: [ 0x7e, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x10" + - + input: + bytes: [ 0x3f, 0x8f, 0xf8, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d15, d8, #-0x10" + - + input: + bytes: [ 0x6d, 0xe8, 0xc9, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2fbc6e" + - + input: + bytes: [ 0x76, 0x8b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d8, #0x16" + - + input: + bytes: [ 0x6d, 0xff, 0xb9, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x8e" + - + input: + bytes: [ 0x3b, 0xc0, 0xf9, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #-0x64" + - + input: + bytes: [ 0xd9, 0xff, 0x08, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x88" + - + input: + bytes: [ 0xf6, 0x47 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d4, #0xe" + - + input: + bytes: [ 0x0b, 0x45, 0x10, 0x68 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e6, d5, d4" + - + input: + bytes: [ 0x40, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a4, a2" + - + input: + bytes: [ 0xa0, 0x64 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a4, #0x6" + - + input: + bytes: [ 0x94, 0xaf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d15, [sp]" + - + input: + bytes: [ 0x53, 0x4f, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d15, #0x4" + - + input: + bytes: [ 0x89, 0xaf, 0xae, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x2e, d15" + - + input: + bytes: [ 0x76, 0x25 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d2, #0xa" + - + input: + bytes: [ 0x3b, 0x00, 0x02, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x20" + - + input: + bytes: [ 0xb0, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a4, #0x1" + - + input: + bytes: [ 0x67, 0x10, 0x1f, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ins.t d0, d0, #0x1f, d1, #0" + - + input: + bytes: [ 0x76, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d0, #0xc" + - + input: + bytes: [ 0xb0, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a2, #0x1" + - + input: + bytes: [ 0xd9, 0x32, 0x10, 0x18 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a3]#-0x7fb0" + - + input: + bytes: [ 0x3b, 0xb0, 0x02, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, #0x2b" + - + input: + bytes: [ 0xd9, 0xff, 0x64, 0x7a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x5a1c" + - + input: + bytes: [ 0xab, 0x08, 0xa2, 0x8f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "seln d8, d15, d8, #0x20" + - + input: + bytes: [ 0xbf, 0x19, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d9, #0x1, #0x30" + - + input: + bytes: [ 0x8f, 0x0f, 0x08, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d15, #0x80" + - + input: + bytes: [ 0x37, 0x03, 0x68, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d3, #0x10, #0x8" + - + input: + bytes: [ 0x6d, 0x00, 0x45, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x188a" + - + input: + bytes: [ 0x6d, 0x00, 0xb8, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x370" + - + input: + bytes: [ 0xdf, 0x2f, 0x91, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x2, #-0xde" + - + input: + bytes: [ 0x6d, 0xff, 0x23, 0x2c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1a7ba" + - + input: + bytes: [ 0x5f, 0x0f, 0xd9, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x1b2" + - + input: + bytes: [ 0x80, 0x44 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d4, a4" + - + input: + bytes: [ 0x80, 0xd0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d0, a13" + - + input: + bytes: [ 0x6d, 0x00, 0x92, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x324" + - + input: + bytes: [ 0x53, 0x49, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d9, #0x4" + - + input: + bytes: [ 0xda, 0x96 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x96" + - + input: + bytes: [ 0x3c, 0x64 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xc8" + - + input: + bytes: [ 0x4b, 0xf0, 0x11, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.u e0, d0, d15" + - + input: + bytes: [ 0x6d, 0x00, 0xef, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xdde" + - + input: + bytes: [ 0x02, 0xb0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, d11" + - + input: + bytes: [ 0x02, 0xd4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d13" + - + input: + bytes: [ 0x91, 0x00, 0x03, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x8030" + - + input: + bytes: [ 0x3c, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x4" + - + input: + bytes: [ 0x30, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a3, a15" + - + input: + bytes: [ 0x6d, 0x00, 0x26, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x204c" + - + input: + bytes: [ 0x1e, 0x13 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0x1, #0x6" + - + input: + bytes: [ 0x0b, 0x73, 0x50, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addc d3, d3, d7" + - + input: + bytes: [ 0x9b, 0x74, 0x02, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d4, d4, #0x27" + - + input: + bytes: [ 0x6d, 0x00, 0x4c, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1e98" + - + input: + bytes: [ 0x06, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d1, #0x2" + - + input: + bytes: [ 0x37, 0x04, 0x50, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d2, d4, #0, #0x10" + - + input: + bytes: [ 0xbb, 0xd0, 0xff, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d0, #0xfffd" + - + input: + bytes: [ 0x8b, 0xf8, 0x1f, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d2, d8, #-0x1" + - + input: + bytes: [ 0x8b, 0x10, 0x00, 0xe0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d14, d0, #0x1" + - + input: + bytes: [ 0x6d, 0xff, 0xfc, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x208" + - + input: + bytes: [ 0x8f, 0x80, 0x40, 0xa1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d10, d0, #0x8" + - + input: + bytes: [ 0xfb, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e0, #0xf" + - + input: + bytes: [ 0x40, 0xfc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a12, a15" + - + input: + bytes: [ 0xa0, 0x3e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a14, #0x3" + - + input: + bytes: [ 0x7f, 0xab, 0x05, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d11, d10, #0xa" + - + input: + bytes: [ 0x3b, 0xa0, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0xa" + - + input: + bytes: [ 0x8f, 0x1a, 0x00, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d10, #0x1" + - + input: + bytes: [ 0x3f, 0xf8, 0xf2, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d8, d15, #-0x1c" + - + input: + bytes: [ 0x6b, 0x00, 0x31, 0xb5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.f d11, d5, d0" + - + input: + bytes: [ 0x76, 0x82 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d8, #0x4" + - + input: + bytes: [ 0x4b, 0x0f, 0x41, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d0, d15, d0" + - + input: + bytes: [ 0x8b, 0x14, 0x80, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addx d4, d4, #0x1" + - + input: + bytes: [ 0x3c, 0xdc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x48" + - + input: + bytes: [ 0x7b, 0x10, 0x7e, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d15, #0x47e1" + - + input: + bytes: [ 0xb0, 0xc5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a5, #-0x4" + - + input: + bytes: [ 0x7f, 0x4f, 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d15, d4, #0xc" + - + input: + bytes: [ 0xd9, 0xff, 0x3c, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x2bc" + - + input: + bytes: [ 0xd9, 0xff, 0x34, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x74" + - + input: + bytes: [ 0x6d, 0xff, 0xf0, 0x2a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1aa20" + - + input: + bytes: [ 0x6d, 0x00, 0x38, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x270" + - + input: + bytes: [ 0xa6, 0x31 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d1, d3" + - + input: + bytes: [ 0xda, 0x33 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x33" + - + input: + bytes: [ 0x37, 0x04, 0xe8, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d4, #0x17, #0x8" + - + input: + bytes: [ 0x6d, 0x00, 0x10, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xa20" + - + input: + bytes: [ 0xdf, 0x19, 0x22, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d9, #0x1, #0x44" + - + input: + bytes: [ 0x0b, 0x62, 0x40, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addx d2, d2, d6" + - + input: + bytes: [ 0x5f, 0x0f, 0x25, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x4a" + - + input: + bytes: [ 0x8b, 0x5f, 0x20, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min.u d15, d15, #0x5" + - + input: + bytes: [ 0xd9, 0x55, 0x08, 0xc0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#0x308" + - + input: + bytes: [ 0xd9, 0xff, 0xc0, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x1c80" + - + input: + bytes: [ 0x1d, 0x00, 0xed, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x1da" + - + input: + bytes: [ 0x1d, 0xff, 0x68, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x130" + - + input: + bytes: [ 0x6d, 0x00, 0xb1, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xd62" + - + input: + bytes: [ 0x49, 0xfd, 0x16, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a13, [a15]#0x16" + - + input: + bytes: [ 0x6d, 0xe8, 0x11, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2fd7de" + - + input: + bytes: [ 0x6d, 0xff, 0x7f, 0x4c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x16702" + - + input: + bytes: [ 0xb7, 0x1f, 0x81, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d1, d15, #0x1, #0x17, #0x1" + - + input: + bytes: [ 0x09, 0xff, 0xb4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d15, [a15]#0x34" + - + input: + bytes: [ 0x3b, 0x80, 0x07, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x78" + - + input: + bytes: [ 0xc6, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d0, d3" + - + input: + bytes: [ 0xb4, 0xdf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a13], d15" + - + input: + bytes: [ 0x4b, 0x0f, 0x31, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftoiz d15, d15" + - + input: + bytes: [ 0xd9, 0xff, 0x88, 0xda ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x54b8" + - + input: + bytes: [ 0x37, 0xf0, 0x04, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0, #0x4" + - + input: + bytes: [ 0x5f, 0x0f, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0xf0" + - + input: + bytes: [ 0x82, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x3" + - + input: + bytes: [ 0x09, 0xff, 0xd4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d15, [a15]#0x14" + - + input: + bytes: [ 0x4b, 0x0a, 0x01, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmp.f d15, d10, d0" + - + input: + bytes: [ 0xf6, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d0, #0x8" + - + input: + bytes: [ 0x67, 0x01, 0x80, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ins.t d1, d1, #0, d0, #0x1f" + - + input: + bytes: [ 0x2e, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x1, #0x8" + - + input: + bytes: [ 0xee, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0xa" + - + input: + bytes: [ 0x61, 0xff, 0xe9, 0xd9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x4c2e" + - + input: + bytes: [ 0xbe, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x22" + - + input: + bytes: [ 0x6d, 0x00, 0x29, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x852" + - + input: + bytes: [ 0x5f, 0x0f, 0x2a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x54" + - + input: + bytes: [ 0x42, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d1, d15" + - + input: + bytes: [ 0x3c, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x40" + - + input: + bytes: [ 0x6d, 0x00, 0x68, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x6d0" + - + input: + bytes: [ 0x6d, 0x00, 0x49, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2492" + - + input: + bytes: [ 0x6d, 0xff, 0xf0, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x220" + - + input: + bytes: [ 0x6d, 0x00, 0x05, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xa" + - + input: + bytes: [ 0x6d, 0x00, 0x42, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2284" + - + input: + bytes: [ 0xda, 0x1d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x1d" + - + input: + bytes: [ 0x91, 0x30, 0x00, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0xf003" + - + input: + bytes: [ 0xb7, 0x00, 0x89, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, #0x17, #0x9" + - + input: + bytes: [ 0xbd, 0x02, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.a a2, #0x60" + - + input: + bytes: [ 0x40, 0x52 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a2, a5" + - + input: + bytes: [ 0x9b, 0xb1, 0xa5, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d1, d1, #0x4a5b" + - + input: + bytes: [ 0x82, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d3, #-0x1" + - + input: + bytes: [ 0x5f, 0x01, 0x0b, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d1, d0, #0x16" + - + input: + bytes: [ 0x49, 0xa4, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [sp]#0" + - + input: + bytes: [ 0x76, 0xc6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d12, #0xc" + - + input: + bytes: [ 0xbb, 0x00, 0x52, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d0, #0xc520" + - + input: + bytes: [ 0x3b, 0x40, 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x64" + - + input: + bytes: [ 0x4b, 0x3b, 0x01, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmp.f d15, d11, d3" + - + input: + bytes: [ 0xac, 0xa6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0xc, d15" + - + input: + bytes: [ 0x7f, 0xf1, 0x04, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d1, d15, #0x8" + - + input: + bytes: [ 0x6d, 0xff, 0x94, 0x2b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1a8d8" + - + input: + bytes: [ 0xac, 0x47 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a4]#0xe, d15" + - + input: + bytes: [ 0x82, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d10, #0x1" + - + input: + bytes: [ 0x7f, 0xf0, 0x07, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d0, d15, #0xe" + - + input: + bytes: [ 0x73, 0x6d, 0x0a, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d13, d6" + - + input: + bytes: [ 0x26, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d2" + - + input: + bytes: [ 0xd9, 0x22, 0x96, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x1816" + - + input: + bytes: [ 0x53, 0x69, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d9, #0x6" + - + input: + bytes: [ 0x8b, 0x0f, 0x02, 0xc0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d12, d15, #0x20" + - + input: + bytes: [ 0x6d, 0xff, 0x03, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3fa" + - + input: + bytes: [ 0x1d, 0x00, 0xe5, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x1ca" + - + input: + bytes: [ 0x77, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "dextr d0, d0, d0, #0x8" + - + input: + bytes: [ 0x7f, 0xf1, 0x09, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d1, d15, #0x12" + - + input: + bytes: [ 0x3c, 0xe8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x30" + - + input: + bytes: [ 0x0b, 0xcd, 0x10, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e4, d13, d12" + - + input: + bytes: [ 0x3f, 0x1f, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d15, d1, #0x8" + - + input: + bytes: [ 0x6d, 0xff, 0x2b, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xbaa" + - + input: + bytes: [ 0x8b, 0x00, 0x03, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d0, #0x30" + - + input: + bytes: [ 0x4b, 0x0a, 0x41, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d15, d10, d0" + - + input: + bytes: [ 0xb7, 0x0f, 0x89, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0x17, #0x9" + - + input: + bytes: [ 0x6d, 0xff, 0xdc, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x48" + - + input: + bytes: [ 0x40, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a15, a4" + - + input: + bytes: [ 0x1d, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x114" + - + input: + bytes: [ 0x7b, 0x00, 0x05, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d4, #0x50" + - + input: + bytes: [ 0xd9, 0x22, 0x06, 0x71 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x11c6" + - + input: + bytes: [ 0x1d, 0x00, 0x4a, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x294" + - + input: + bytes: [ 0x8b, 0xa0, 0x60, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt.u d15, d0, #0xa" + - + input: + bytes: [ 0x6d, 0xff, 0x68, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xd30" + - + input: + bytes: [ 0xda, 0x78 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x78" + - + input: + bytes: [ 0x26, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d4" + - + input: + bytes: [ 0x80, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d4, a15" + - + input: + bytes: [ 0x6d, 0x00, 0x5a, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x6b4" + - + input: + bytes: [ 0x6d, 0x00, 0x5f, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1ebe" + - + input: + bytes: [ 0x3b, 0x00, 0x08, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x1080" + - + input: + bytes: [ 0x4b, 0xf0, 0x41, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d15, d0, d15" + - + input: + bytes: [ 0x6d, 0x00, 0xa3, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2146" + - + input: + bytes: [ 0xee, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x1a" + - + input: + bytes: [ 0x37, 0x0c, 0xe8, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d12, #0x17, #0x8" + - + input: + bytes: [ 0xd9, 0xff, 0x10, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x4ff0" + - + input: + bytes: [ 0x6d, 0xff, 0x1a, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xdcc" + - + input: + bytes: [ 0x0b, 0xaa, 0x10, 0x88 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e8, d10, d10" + - + input: + bytes: [ 0x3b, 0xa0, 0x00, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #0xa" + - + input: + bytes: [ 0x6d, 0xff, 0x47, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1372" + - + input: + bytes: [ 0x3b, 0x80, 0x07, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x78" + - + input: + bytes: [ 0x7e, 0x55 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d5, #0xa" + - + input: + bytes: [ 0x0b, 0x01, 0x10, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e2, d1, d0" + - + input: + bytes: [ 0x07, 0x1d, 0xe0, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor.t d15, d13, #0, d1, #0x1f" + - + input: + bytes: [ 0x3b, 0xd0, 0x02, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x2d" + - + input: + bytes: [ 0x3c, 0x70 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xe0" + - + input: + bytes: [ 0x37, 0x0f, 0xe1, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x3, #0x1" + - + input: + bytes: [ 0xd9, 0xff, 0x80, 0x9a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x55c0" + - + input: + bytes: [ 0x53, 0x59, 0x2f, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d9, #0xf5" + - + input: + bytes: [ 0xb0, 0x54 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a4, #0x5" + - + input: + bytes: [ 0x91, 0x40, 0x00, 0x57 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a5, #0x7004" + - + input: + bytes: [ 0x61, 0xff, 0xe9, 0xd8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x4e2e" + - + input: + bytes: [ 0xbc, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.a a15, #0x2" + - + input: + bytes: [ 0xdf, 0x1f, 0xfa, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0x1, #-0xc" + - + input: + bytes: [ 0x0f, 0xf2, 0x00, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d2, d2, d15" + - + input: + bytes: [ 0x90, 0xdd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a13, a13, d15, #0x2" + - + input: + bytes: [ 0x8b, 0x40, 0x00, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d9, d0, #0x4" + - + input: + bytes: [ 0x6d, 0xe8, 0xbd, 0x14 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2fd686" + - + input: + bytes: [ 0xee, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0x14" + - + input: + bytes: [ 0x3b, 0x70, 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x67" + - + input: + bytes: [ 0x6d, 0xff, 0x9d, 0x29 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1acc6" + - + input: + bytes: [ 0xd9, 0x44, 0x40, 0x4b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#-0x4b00" + - + input: + bytes: [ 0x9b, 0x1f, 0x00, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d15, d15, #0x1" + - + input: + bytes: [ 0xb7, 0x1f, 0x08, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x1, #0, #0x8" + - + input: + bytes: [ 0xb7, 0x0f, 0x01, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0, #0x1" + - + input: + bytes: [ 0xff, 0x1f, 0xf7, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d15, #0x1, #-0x12" + - + input: + bytes: [ 0x6d, 0x00, 0xbf, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x57e" + - + input: + bytes: [ 0xd9, 0x55, 0xa4, 0xca ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x54dc" + - + input: + bytes: [ 0x3c, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x36" + - + input: + bytes: [ 0x6d, 0xff, 0x7b, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x10a" + - + input: + bytes: [ 0xa0, 0x94 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a4, #0x9" + - + input: + bytes: [ 0x49, 0xa5, 0x02, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [sp]#0x2" + - + input: + bytes: [ 0x3b, 0xe0, 0x07, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d5, #0x7e" + - + input: + bytes: [ 0xb7, 0x0f, 0x81, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0x1f, #0x1" + - + input: + bytes: [ 0xc2, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, #-0x1" + - + input: + bytes: [ 0x6d, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x8" + - + input: + bytes: [ 0x37, 0x04, 0x68, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d4, #0, #0x8" + - + input: + bytes: [ 0x37, 0x4f, 0x05, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d4, #0, #0x5" + - + input: + bytes: [ 0xdc, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ji a11" + - + input: + bytes: [ 0x6d, 0x00, 0xf3, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x11e6" + - + input: + bytes: [ 0x3b, 0x00, 0x40, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x400" + - + input: + bytes: [ 0xee, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x20" + - + input: + bytes: [ 0x3c, 0x2e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x5c" + - + input: + bytes: [ 0xa0, 0x34 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a4, #0x3" + - + input: + bytes: [ 0x0b, 0x13, 0x80, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.ne d15, d3, d1" + - + input: + bytes: [ 0xdf, 0x09, 0x38, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d9, #0, #0x70" + - + input: + bytes: [ 0xa6, 0x42 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d2, d4" + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d9, #0x3" + - + input: + bytes: [ 0x37, 0xf0, 0x01, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0x4, #0x1" + - + input: + bytes: [ 0x06, 0x3f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, #0x3" + - + input: + bytes: [ 0x3c, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x80" + - + input: + bytes: [ 0xff, 0x1b, 0xf2, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d11, #0x1, #-0x1c" + - + input: + bytes: [ 0xb7, 0x0f, 0x0c, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0x14, #0xc" + - + input: + bytes: [ 0x3c, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x20" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x7000" + - + input: + bytes: [ 0x7f, 0xf0, 0x27, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d0, d15, #0x4e" + - + input: + bytes: [ 0x4b, 0xf0, 0x51, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d2, d0, d15" + - + input: + bytes: [ 0x52, 0x52 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d2, d15, d5" + - + input: + bytes: [ 0x26, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d3, d15" + - + input: + bytes: [ 0x8f, 0xec, 0x1f, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d12, #-0x2" + - + input: + bytes: [ 0x87, 0x55, 0x9f, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.t d15, d5, #0x1f, d5, #0x1f" + - + input: + bytes: [ 0x37, 0x0f, 0x61, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x6, #0x1" + - + input: + bytes: [ 0xa6, 0x5f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d5" + - + input: + bytes: [ 0xce, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jgez d15, #0xc" + - + input: + bytes: [ 0xbd, 0x0e, 0x15, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.a a14, #0x2a" + - + input: + bytes: [ 0x6d, 0x00, 0x6c, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x22d8" + - + input: + bytes: [ 0x4b, 0x0f, 0x41, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d4, d15, d0" + - + input: + bytes: [ 0x6d, 0xff, 0x82, 0x2b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1a8fc" + - + input: + bytes: [ 0x37, 0x0f, 0xe1, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0xf, #0x1" + - + input: + bytes: [ 0xbe, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x20" + - + input: + bytes: [ 0x96, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0x3" + - + input: + bytes: [ 0x8f, 0x8f, 0x01, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d0, d15, #0x18" + - + input: + bytes: [ 0x3b, 0x00, 0x08, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x80" + - + input: + bytes: [ 0x7f, 0xab, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d11, d10, #0x8" + - + input: + bytes: [ 0x02, 0x58 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, d5" + - + input: + bytes: [ 0xdf, 0x08, 0x17, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d8, #0, #0x2e" + - + input: + bytes: [ 0x60, 0xc2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a2, d12" + - + input: + bytes: [ 0x3c, 0xe2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x3c" + - + input: + bytes: [ 0x49, 0xef, 0x01, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a14]#0x1" + - + input: + bytes: [ 0x37, 0x0f, 0x68, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d1, d15, #0, #0x8" + - + input: + bytes: [ 0x6d, 0x00, 0xdb, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x21b6" + - + input: + bytes: [ 0xca, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "caddn d15, d15, #-0x1" + - + input: + bytes: [ 0x0b, 0xf0, 0xa0, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "max d15, d0, d15" + - + input: + bytes: [ 0x8b, 0x00, 0x03, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d4, d0, #0x30" + - + input: + bytes: [ 0x02, 0x86 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d6, d8" + - + input: + bytes: [ 0xa2, 0x9f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d15, d9" + - + input: + bytes: [ 0x3b, 0xf0, 0xff, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0xfff" + - + input: + bytes: [ 0x49, 0xaf, 0x00, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [sp]#0x40" + - + input: + bytes: [ 0x37, 0x0f, 0x62, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x4, #0x2" + - + input: + bytes: [ 0xb4, 0xa4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp], d4" + - + input: + bytes: [ 0x6f, 0x09, 0x14, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d9, #0, #0x28" + - + input: + bytes: [ 0x6d, 0x00, 0xcc, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1198" + - + input: + bytes: [ 0xc2, 0xe5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d5, #-0x2" + - + input: + bytes: [ 0x09, 0xdf, 0xe0, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d15, [a13]#0x20" + - + input: + bytes: [ 0xee, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x24" + - + input: + bytes: [ 0x40, 0x7c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a12, a7" + - + input: + bytes: [ 0x0b, 0xd1, 0x90, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.lt d15, d1, d13" + - + input: + bytes: [ 0xff, 0x1a, 0xea, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d10, #0x1, #-0x2c" + - + input: + bytes: [ 0x6d, 0x00, 0x73, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x22e6" + - + input: + bytes: [ 0x3b, 0xf0, 0x49, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x249f" + - + input: + bytes: [ 0x37, 0x0f, 0x50, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d1, d15, #0, #0x10" + - + input: + bytes: [ 0x6d, 0x00, 0xfc, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x13f8" + - + input: + bytes: [ 0xa0, 0xb4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a4, #0xb" + - + input: + bytes: [ 0x3b, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x40" + - + input: + bytes: [ 0x3c, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x44" + - + input: + bytes: [ 0x6f, 0x10, 0xf2, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d0, #0x1, #-0x1c" + - + input: + bytes: [ 0x4b, 0xf2, 0x41, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d15, d2, d15" + - + input: + bytes: [ 0x6d, 0x00, 0xc3, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x786" + - + input: + bytes: [ 0x7f, 0x0f, 0x05, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d15, d0, #0xa" + - + input: + bytes: [ 0xd9, 0xff, 0x38, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x78" + - + input: + bytes: [ 0x3b, 0xa0, 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x6a" + - + input: + bytes: [ 0x91, 0x40, 0x00, 0x4f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0xf004" + - + input: + bytes: [ 0x8f, 0xf5, 0x0f, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d5, #0xff" + - + input: + bytes: [ 0x7f, 0x2f, 0x05, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d15, d2, #0xa" + - + input: + bytes: [ 0x3b, 0xc0, 0x00, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0xc" + - + input: + bytes: [ 0x37, 0x00, 0x62, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d0, #0x4, #0x2" + - + input: + bytes: [ 0x0b, 0xfa, 0x10, 0x68 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e6, d10, d15" + - + input: + bytes: [ 0x3b, 0x70, 0x06, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #0x67" + - + input: + bytes: [ 0x61, 0xff, 0xd2, 0xd8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x4e5c" + - + input: + bytes: [ 0x67, 0xaa, 0xbf, 0xaf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insn.t d10, d10, #0x1f, d10, #0x1f" + - + input: + bytes: [ 0x8b, 0x0f, 0x03, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d4, d15, #0x30" + - + input: + bytes: [ 0x01, 0xe2, 0x00, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a14, d2, #0" + - + input: + bytes: [ 0x8f, 0x71, 0x01, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d2, d1, #0x17" + - + input: + bytes: [ 0x06, 0x62 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d2, #0x6" + - + input: + bytes: [ 0xd9, 0xdd, 0xe4, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a13, [a13]#0xc64" + - + input: + bytes: [ 0x0b, 0x82, 0x50, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ge.u d0, d2, d8" + - + input: + bytes: [ 0x5f, 0xef, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d14, #0xd8" + - + input: + bytes: [ 0x3c, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x2" + - + input: + bytes: [ 0x6e, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x1e" + - + input: + bytes: [ 0x02, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, d1" + - + input: + bytes: [ 0x5f, 0x0f, 0xf1, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #-0x1e" + - + input: + bytes: [ 0x37, 0x0f, 0x61, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x4, #0x1" + - + input: + bytes: [ 0x7b, 0x00, 0xf8, 0xb3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d11, #0x3f80" + - + input: + bytes: [ 0x49, 0xa5, 0x0c, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [sp]#0xc" + - + input: + bytes: [ 0x76, 0x8c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d8, #0x18" + - + input: + bytes: [ 0x03, 0x6d, 0x0a, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd d9, d0, d13, d6" + - + input: + bytes: [ 0xbe, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d4, #0x22" + - + input: + bytes: [ 0x57, 0x00, 0x62, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d0, d15, #0x2" + - + input: + bytes: [ 0xb7, 0x00, 0x89, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, #0, #0x17, #0x9" + - + input: + bytes: [ 0x6d, 0xff, 0x86, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xf4" + - + input: + bytes: [ 0x6d, 0xff, 0xa9, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x16ae" + - + input: + bytes: [ 0x37, 0x04, 0x68, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d4, d4, #0, #0x8" + - + input: + bytes: [ 0x3b, 0x00, 0x16, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d5, #0x160" + - + input: + bytes: [ 0x6d, 0xff, 0x13, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xbda" + - + input: + bytes: [ 0xd9, 0xff, 0xb0, 0xda ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x5490" + - + input: + bytes: [ 0x7d, 0xef, 0x03, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq.a a15, a14, #0x6" + - + input: + bytes: [ 0x9a, 0x49 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d9, #0x4" + - + input: + bytes: [ 0xd9, 0x22, 0x36, 0x61 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x11b6" + - + input: + bytes: [ 0x91, 0x40, 0x00, 0xf6 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0x6004" + - + input: + bytes: [ 0xd9, 0xff, 0x30, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x3f0" + - + input: + bytes: [ 0x8f, 0x3f, 0x00, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d1, d15, #0x3" + - + input: + bytes: [ 0x6f, 0x5a, 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d10, #0x5, #0xc" + - + input: + bytes: [ 0x6d, 0x00, 0xd8, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x5b0" + - + input: + bytes: [ 0xa2, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d15, d1" + - + input: + bytes: [ 0xc2, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d8, #-0x1" + - + input: + bytes: [ 0x49, 0xfc, 0x14, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a12, [a15]#0x14" + - + input: + bytes: [ 0xc6, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d0, d1" + - + input: + bytes: [ 0x6b, 0x02, 0x31, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.f d15, d4, d2" + - + input: + bytes: [ 0x37, 0x0f, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d0, d15, #0, #0x10" + - + input: + bytes: [ 0xbb, 0x00, 0xa0, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d1, #0xba00" + - + input: + bytes: [ 0xa2, 0xdc ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d12, d13" + - + input: + bytes: [ 0x8b, 0x0f, 0x00, 0x92 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq d9, d15, #0" + - + input: + bytes: [ 0x40, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a4, a15" + - + input: + bytes: [ 0x3b, 0xd0, 0x02, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x2d" + - + input: + bytes: [ 0xee, 0xe9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0x2e" + - + input: + bytes: [ 0xbe, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x2e" + - + input: + bytes: [ 0xd9, 0x22, 0x96, 0x71 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x19d6" + - + input: + bytes: [ 0x3b, 0x70, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x47" + - + input: + bytes: [ 0x37, 0x0f, 0x05, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x10, #0x5" + - + input: + bytes: [ 0x01, 0x2f, 0x10, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne.a d15, a15, a2" + - + input: + bytes: [ 0x6d, 0x00, 0x79, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x34f2" + - + input: + bytes: [ 0x3b, 0x60, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x46" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne d15, d0, #0" + - + input: + bytes: [ 0x42, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d8, d15" + - + input: + bytes: [ 0x37, 0x0f, 0x50, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d15, d15, #0, #0x10" + - + input: + bytes: [ 0xd9, 0xff, 0x10, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x90" + - + input: + bytes: [ 0x8f, 0x38, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, d8, #0x3" + - + input: + bytes: [ 0xa2, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d4, d15" + - + input: + bytes: [ 0x3b, 0x50, 0x04, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #0x45" + - + input: + bytes: [ 0x02, 0xe4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d14" + - + input: + bytes: [ 0x8f, 0x4a, 0x40, 0xa1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d10, d10, #0x4" + - + input: + bytes: [ 0x4b, 0xfa, 0x41, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d4, d10, d15" + - + input: + bytes: [ 0x49, 0xaa, 0x00, 0x8a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea sp, [sp]#-0x200" + - + input: + bytes: [ 0x61, 0xff, 0x60, 0xd9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #-0x4d40" + - + input: + bytes: [ 0x6d, 0xff, 0xa6, 0x3e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x182b4" + - + input: + bytes: [ 0xd9, 0x44, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#-0x6000" + - + input: + bytes: [ 0x6d, 0xff, 0xbc, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x488" + - + input: + bytes: [ 0x02, 0x89 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d9, d8" + - + input: + bytes: [ 0x37, 0x0f, 0x01, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x4, #0x1" + - + input: + bytes: [ 0xf6, 0xa3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d10, #0x6" + - + input: + bytes: [ 0x6d, 0x00, 0x57, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x22ae" + - + input: + bytes: [ 0xc2, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d9, #0x1" + - + input: + bytes: [ 0x3c, 0x15 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x2a" + - + input: + bytes: [ 0x6d, 0xff, 0xf0, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x420" + - + input: + bytes: [ 0x3b, 0x20, 0x07, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x72" + - + input: + bytes: [ 0x8f, 0x8f, 0x00, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d15, #0x8" + - + input: + bytes: [ 0xd9, 0x55, 0x20, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5c20" + - + input: + bytes: [ 0x8f, 0x31, 0x40, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d1, #0x3" + - + input: + bytes: [ 0x80, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d15, a15" + - + input: + bytes: [ 0x0b, 0x40, 0x40, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addx d2, d0, d4" + - + input: + bytes: [ 0xb7, 0x0f, 0x02, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0, #0x2" + - + input: + bytes: [ 0x0b, 0x26, 0x10, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne d15, d6, d2" + - + input: + bytes: [ 0x88, 0x8f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d15, [a15]#0x10" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x27 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0x7000" + - + input: + bytes: [ 0x6d, 0xff, 0xe7, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x232" + - + input: + bytes: [ 0x5f, 0x0f, 0xc2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x184" + - + input: + bytes: [ 0x09, 0x20, 0x94, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d0, [a2]#0x14" + - + input: + bytes: [ 0x91, 0x50, 0x02, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0xf025" + - + input: + bytes: [ 0x91, 0x40, 0x00, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0x6004" + - + input: + bytes: [ 0xbd, 0x04, 0x31, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.a a4, #0x62" + - + input: + bytes: [ 0xd9, 0x22, 0x1a, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x105a" + - + input: + bytes: [ 0x53, 0xc2, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d2, #0xc" + - + input: + bytes: [ 0xbd, 0x0d, 0x22, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.a a13, #0x44" + - + input: + bytes: [ 0x0b, 0x71, 0x50, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addc d9, d1, d7" + - + input: + bytes: [ 0x30, 0x43 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a3, a4" + - + input: + bytes: [ 0x6d, 0x00, 0x9f, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x33e" + - + input: + bytes: [ 0x02, 0x98 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, d9" + - + input: + bytes: [ 0x6d, 0x00, 0x85, 0x12 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x250a" + - + input: + bytes: [ 0x02, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, d0" + - + input: + bytes: [ 0x20, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.a sp, #0x10" + - + input: + bytes: [ 0x6d, 0xff, 0x5d, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1746" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0xe8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a14, #0x8000" + - + input: + bytes: [ 0x02, 0x9c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d12, d9" + - + input: + bytes: [ 0x7e, 0x1d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d1, #0x1a" + - + input: + bytes: [ 0x6d, 0xff, 0x7b, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xb0a" + - + input: + bytes: [ 0xb7, 0x0f, 0x1c, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0, #0, #0x1c" + - + input: + bytes: [ 0x5f, 0x0f, 0xdc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x1b8" + - + input: + bytes: [ 0x02, 0xc4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d12" + - + input: + bytes: [ 0xd9, 0x22, 0xb0, 0x4a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#-0x56d0" + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0x31 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d3, d15, #0x3f" + - + input: + bytes: [ 0x37, 0x0f, 0x81, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x3, #0x1" + - + input: + bytes: [ 0xd9, 0xff, 0x20, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x220" + - + input: + bytes: [ 0x76, 0x13 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d1, #0x6" + - + input: + bytes: [ 0x6d, 0x00, 0xf8, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x21f0" + - + input: + bytes: [ 0x53, 0x40, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d0, #0x4" + - + input: + bytes: [ 0xda, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0xf" + - + input: + bytes: [ 0xbf, 0x10, 0xf5, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d0, #0x1, #-0x16" + - + input: + bytes: [ 0x8f, 0x41, 0x1f, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d1, #-0xc" + - + input: + bytes: [ 0x4b, 0xf0, 0x51, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "q31tof d15, d0, d15" + - + input: + bytes: [ 0x89, 0x40, 0x84, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a4]#0x4, d0" + - + input: + bytes: [ 0x5f, 0x0f, 0x6e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0xdc" + - + input: + bytes: [ 0x3b, 0x80, 0x01, 0xb0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d11, #0x18" + - + input: + bytes: [ 0x8f, 0xdf, 0x0f, 0x41 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d4, d15, #0xfd" + - + input: + bytes: [ 0x6d, 0x00, 0xc7, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1b8e" + - + input: + bytes: [ 0xa2, 0x31 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d1, d3" + - + input: + bytes: [ 0x0b, 0x13, 0x90, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.lt d15, d3, d1" + - + input: + bytes: [ 0xdf, 0x04, 0x50, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d4, #0, #0x4a0" + - + input: + bytes: [ 0xd9, 0x44, 0xa8, 0x4a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#-0x56d8" + - + input: + bytes: [ 0x3b, 0x30, 0x02, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x23" + - + input: + bytes: [ 0xc2, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, #0x1" + - + input: + bytes: [ 0x5f, 0x0f, 0xed, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #-0x26" + - + input: + bytes: [ 0x91, 0x00, 0x03, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a15, #0xa030" + - + input: + bytes: [ 0xda, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0xd" + - + input: + bytes: [ 0x7e, 0x44 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d4, #0x8" + - + input: + bytes: [ 0xf6, 0x84 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d8, #0x8" + - + input: + bytes: [ 0xb7, 0x2f, 0x02, 0xf5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, #0x2, #0xa, #0x2" + - + input: + bytes: [ 0x82, 0x74 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x7" + - + input: + bytes: [ 0xfc, 0x2f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a2, #-0x2" + - + input: + bytes: [ 0xd9, 0xff, 0x2c, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x22c" + - + input: + bytes: [ 0x6d, 0xff, 0x0d, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xde6" + - + input: + bytes: [ 0xd9, 0x55, 0x54, 0x5a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5aac" + - + input: + bytes: [ 0x4b, 0xdb, 0x41, 0xb0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d11, d11, d13" + - + input: + bytes: [ 0xc2, 0x3f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, #0x3" + - + input: + bytes: [ 0x7f, 0x89, 0x2c, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d9, d8, #-0x1a8" + - + input: + bytes: [ 0x2e, 0x2c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x2, #0x18" + - + input: + bytes: [ 0x40, 0xbf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a15, a11" + - + input: + bytes: [ 0x6f, 0x1f, 0xfa, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0x1, #-0xc" + - + input: + bytes: [ 0x40, 0xd5 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a5, a13" + - + input: + bytes: [ 0xc2, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, #0x7" + - + input: + bytes: [ 0xdf, 0x08, 0xd4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d8, #0, #0x1a8" + - + input: + bytes: [ 0x37, 0x05, 0x68, 0xf8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d5, #0x10, #0x8" + - + input: + bytes: [ 0x49, 0xa4, 0x06, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [sp]#0x6" + - + input: + bytes: [ 0x7f, 0x80, 0x18, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d0, d8, #0x30" + - + input: + bytes: [ 0x6d, 0x00, 0xe5, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x13ca" + - + input: + bytes: [ 0x0b, 0x40, 0x50, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ge.u d15, d0, d4" + - + input: + bytes: [ 0x53, 0x4b, 0x20, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d15, d11, #0x4" + - + input: + bytes: [ 0xbb, 0xf0, 0xff, 0x6f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d6, #0xffff" + - + input: + bytes: [ 0x49, 0xf2, 0x1c, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a15]#0x1c" + - + input: + bytes: [ 0x76, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d2, #0x10" + - + input: + bytes: [ 0x7e, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0xe" + - + input: + bytes: [ 0x6f, 0x08, 0x19, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d8, #0, #0x32" + - + input: + bytes: [ 0x01, 0xfe, 0x20, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt.a d15, a14, a15" + - + input: + bytes: [ 0x3f, 0xf0, 0x05, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d0, d15, #0xa" + - + input: + bytes: [ 0x6d, 0xff, 0xf7, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x212" + - + input: + bytes: [ 0xd9, 0xff, 0xac, 0xba ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x5514" + - + input: + bytes: [ 0x02, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d15" + - + input: + bytes: [ 0x8f, 0x24, 0x00, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d4, #0x2" + - + input: + bytes: [ 0xd9, 0x44, 0x0c, 0x96 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x624c" + - + input: + bytes: [ 0xd9, 0xff, 0x68, 0x60 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x5a8" + - + input: + bytes: [ 0x3c, 0x3b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x76" + - + input: + bytes: [ 0x86, 0x5f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d15, #0x5" + - + input: + bytes: [ 0x6e, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0x60" + - + input: + bytes: [ 0x3f, 0xaf, 0xf7, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d15, d10, #-0x12" + - + input: + bytes: [ 0x5f, 0x0f, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x78" + - + input: + bytes: [ 0x26, 0x42 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d2, d4" + - + input: + bytes: [ 0xfc, 0x4e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a4, #-0x4" + - + input: + bytes: [ 0x7b, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d0, #0xd000" + - + input: + bytes: [ 0xd9, 0x55, 0x74, 0x5a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5a8c" + - + input: + bytes: [ 0x49, 0xa2, 0x00, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [sp]#0x40" + - + input: + bytes: [ 0xdf, 0x08, 0x26, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d8, #0, #0x4c" + - + input: + bytes: [ 0xa6, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d0, d4" + - + input: + bytes: [ 0x6d, 0xff, 0xc2, 0xfa ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xa7c" + - + input: + bytes: [ 0x1d, 0xff, 0x4d, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x366" + - + input: + bytes: [ 0x82, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, #-0x1" + - + input: + bytes: [ 0xc5, 0xf5, 0x80, 0xc0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, #0xf0000b00" + - + input: + bytes: [ 0x3c, 0x33 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x66" + - + input: + bytes: [ 0x8b, 0xff, 0x20, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min.u d15, d15, #0xf" + - + input: + bytes: [ 0xdf, 0x04, 0xfd, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d4, #0, #-0x6" + - + input: + bytes: [ 0x8f, 0x34, 0x40, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, d4, #0x3" + - + input: + bytes: [ 0x89, 0xff, 0xa0, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a15]#0x20, d15" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "calla #0" + - + input: + bytes: [ 0x1d, 0xff, 0xa6, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x2b4" + - + input: + bytes: [ 0x80, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d0, a5" + - + input: + bytes: [ 0x16, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0xf" + - + input: + bytes: [ 0x3c, 0x1c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x38" + - + input: + bytes: [ 0xee, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x3e" + - + input: + bytes: [ 0x82, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d11, #0" + - + input: + bytes: [ 0x7f, 0xf8, 0x0a, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d8, d15, #0x14" + - + input: + bytes: [ 0x8f, 0x0a, 0x02, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d1, d10, #0x20" + - + input: + bytes: [ 0x8b, 0x0f, 0xc0, 0x4a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eqany.b d4, d15, #0" + - + input: + bytes: [ 0x49, 0xf2, 0x19, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a15]#0x19" + - + input: + bytes: [ 0xbf, 0x19, 0xe1, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d9, #0x1, #-0x3e" + - + input: + bytes: [ 0x3b, 0x00, 0x00, 0x31 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d3, #0x1000" + - + input: + bytes: [ 0x3c, 0x27 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x4e" + - + input: + bytes: [ 0x6d, 0xff, 0xf7, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xc12" + - + input: + bytes: [ 0xbb, 0xf0, 0xff, 0x9f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d9, #0xffff" + - + input: + bytes: [ 0x60, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a2, d2" + - + input: + bytes: [ 0x6d, 0xff, 0xac, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xa8" + - + input: + bytes: [ 0x6d, 0x00, 0x3d, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x107a" + - + input: + bytes: [ 0xb7, 0x04, 0x02, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d4, #0, #0, #0x2" + - + input: + bytes: [ 0x2e, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #0x10" + - + input: + bytes: [ 0xd9, 0xaa, 0x40, 0x89 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea sp, [sp]#-0x6a00" + - + input: + bytes: [ 0x0b, 0x0c, 0x50, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ge.u d15, d12, d0" + - + input: + bytes: [ 0x49, 0xf2, 0x30, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a15]#0x30" + - + input: + bytes: [ 0x40, 0xfd ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a13, a15" + - + input: + bytes: [ 0xf6, 0x83 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d8, #0x6" + - + input: + bytes: [ 0x1d, 0x00, 0xcb, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x196" + - + input: + bytes: [ 0x6d, 0x00, 0x4c, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xe98" + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0x91 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d9, d15, #0x3f" + - + input: + bytes: [ 0x3e, 0xe8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d14, #0x10" + - + input: + bytes: [ 0x0b, 0x0f, 0x20, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt d1, d15, d0" + - + input: + bytes: [ 0x76, 0x26 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d2, #0xc" + - + input: + bytes: [ 0x02, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d7, d0" + - + input: + bytes: [ 0x6d, 0xff, 0xcc, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xc68" + - + input: + bytes: [ 0xff, 0xdf, 0x33, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d15, #-0x3, #0x66" + - + input: + bytes: [ 0x12, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d15, d8" + - + input: + bytes: [ 0xdf, 0x0c, 0xd3, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d12, #0, #-0x5a" + - + input: + bytes: [ 0x3c, 0x62 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0xc4" + - + input: + bytes: [ 0xc2, 0x5f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, #0x5" + - + input: + bytes: [ 0xee, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x10" + - + input: + bytes: [ 0x37, 0xf0, 0x81, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d0, d15, #0x1, #0x1" + - + input: + bytes: [ 0x8b, 0x02, 0x20, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne d15, d2, #0" + - + input: + bytes: [ 0x1d, 0x00, 0x1b, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x36" + - + input: + bytes: [ 0x37, 0x0a, 0x50, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d4, d10, #0, #0x10" + - + input: + bytes: [ 0x7b, 0x10, 0x00, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d15, #0x1" + - + input: + bytes: [ 0xd9, 0x22, 0x1a, 0x71 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x11da" + - + input: + bytes: [ 0x6d, 0x00, 0x07, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x80e" + - + input: + bytes: [ 0x01, 0x2f, 0x20, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt.a d15, a15, a2" + - + input: + bytes: [ 0x3b, 0x00, 0x07, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x70" + - + input: + bytes: [ 0xbd, 0x0e, 0x1e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.a a14, #0x3c" + - + input: + bytes: [ 0xd9, 0xff, 0x40, 0x4b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x4b00" + - + input: + bytes: [ 0x40, 0x6d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a13, a6" + - + input: + bytes: [ 0x12, 0x19 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d9, d15, d1" + - + input: + bytes: [ 0x88, 0x9f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d15, [a15]#0x12" + - + input: + bytes: [ 0xdf, 0x00, 0x2e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d0, #0, #0x5c" + - + input: + bytes: [ 0x6d, 0x00, 0xbe, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1f7c" + - + input: + bytes: [ 0x90, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a2, a2, d15, #0x2" + - + input: + bytes: [ 0x6d, 0x00, 0x79, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xf2" + - + input: + bytes: [ 0xd9, 0x22, 0x3e, 0x61 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x11be" + - + input: + bytes: [ 0x8b, 0x0f, 0x02, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d15, #0x20" + - + input: + bytes: [ 0x6d, 0x00, 0xf2, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x9e4" + - + input: + bytes: [ 0x8f, 0x75, 0x00, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, d5, #0x7" + - + input: + bytes: [ 0xda, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x20" + - + input: + bytes: [ 0xab, 0x1f, 0x18, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cadd d15, d15, d15, #-0x7f" + - + input: + bytes: [ 0x40, 0xc2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a2, a12" + - + input: + bytes: [ 0x9b, 0x5e, 0xcf, 0xe3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d14, d14, #0x3cf5" + - + input: + bytes: [ 0x0f, 0xf1, 0x00, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d1, d1, d15" + - + input: + bytes: [ 0x3b, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x1000" + - + input: + bytes: [ 0xd9, 0x55, 0x90, 0xca ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x54f0" + - + input: + bytes: [ 0x91, 0x20, 0x00, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0x8002" + - + input: + bytes: [ 0x3f, 0xf8, 0xf0, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d8, d15, #-0x20" + - + input: + bytes: [ 0x6d, 0xff, 0xd0, 0x2b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1a860" + - + input: + bytes: [ 0xbf, 0x19, 0xef, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d9, #0x1, #-0x22" + - + input: + bytes: [ 0x6d, 0xff, 0xf6, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x214" + - + input: + bytes: [ 0x0f, 0x20, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d0, d0, d2" + - + input: + bytes: [ 0x7e, 0x2c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d2, #0x18" + - + input: + bytes: [ 0x02, 0x24 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, d2" + - + input: + bytes: [ 0x8b, 0x70, 0x01, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsub d0, d0, #0x17" + - + input: + bytes: [ 0xbb, 0x00, 0xc2, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d0, #0xbc20" + - + input: + bytes: [ 0x40, 0x64 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a4, a6" + - + input: + bytes: [ 0xda, 0x58 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x58" + - + input: + bytes: [ 0x49, 0xa6, 0x02, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a6, [sp]#0x2" + - + input: + bytes: [ 0x6f, 0x0f, 0x16, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0, #0x2c" + - + input: + bytes: [ 0xd9, 0xff, 0x1c, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x4fe4" + - + input: + bytes: [ 0xbc, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.a a15, #0x6" + - + input: + bytes: [ 0x6d, 0xff, 0xa6, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xb4" + - + input: + bytes: [ 0x8b, 0x03, 0xa0, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addc d3, d3, #0" + - + input: + bytes: [ 0x5f, 0xef, 0x73, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d14, #0xe6" + - + input: + bytes: [ 0x1d, 0xff, 0x28, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #-0x1b0" + - + input: + bytes: [ 0x37, 0x0f, 0x02, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x6, #0x2" + - + input: + bytes: [ 0xd2, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e4, #0" + - + input: + bytes: [ 0x82, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0" + - + input: + bytes: [ 0x4b, 0x30, 0x11, 0x42 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.u e4, d0, d3" + - + input: + bytes: [ 0x6d, 0x00, 0xcd, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x199a" + - + input: + bytes: [ 0x8f, 0xff, 0x83, 0xa1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d10, d15, #0x3f" + - + input: + bytes: [ 0x3f, 0x10, 0xee, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, d1, #-0x24" + - + input: + bytes: [ 0x16, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0x4" + - + input: + bytes: [ 0x3c, 0x1d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x3a" + - + input: + bytes: [ 0xd9, 0xff, 0xce, 0x61 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x1d8e" + - + input: + bytes: [ 0x3b, 0xb0, 0x0d, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0xdb" + - + input: + bytes: [ 0x49, 0xc2, 0x04, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a12]#0x4" + - + input: + bytes: [ 0x32, 0x52 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsub d2" + - + input: + bytes: [ 0xd9, 0xdd, 0xac, 0xba ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a13, [a13]#-0x5514" + - + input: + bytes: [ 0x7e, 0x13 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d1, #0x6" + - + input: + bytes: [ 0xae, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0x2, #0x4" + - + input: + bytes: [ 0xd9, 0xff, 0xcc, 0x51 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x1d4c" + - + input: + bytes: [ 0x6d, 0xff, 0xfc, 0xf7 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1008" + - + input: + bytes: [ 0x10, 0xaf ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a15, sp, d15, #0" + - + input: + bytes: [ 0x7b, 0xc0, 0xff, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d0, #0xfffc" + - + input: + bytes: [ 0x6d, 0x00, 0x5d, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0xba" + - + input: + bytes: [ 0xd9, 0xff, 0xe4, 0x2a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#-0x535c" + - + input: + bytes: [ 0x4b, 0x1f, 0x51, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d15, d15, d1" + - + input: + bytes: [ 0x9a, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d8, #0x4" + - + input: + bytes: [ 0x37, 0xf3, 0x08, 0x38 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d3, d3, d15, #0x10, #0x8" + - + input: + bytes: [ 0x82, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d12, #0" + - + input: + bytes: [ 0x6d, 0xe8, 0x91, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2fe8de" + - + input: + bytes: [ 0x6d, 0x00, 0xae, 0x0d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x1b5c" + - + input: + bytes: [ 0xb0, 0x4c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a12, #0x4" + - + input: + bytes: [ 0x6d, 0xff, 0x43, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x17a" + - + input: + bytes: [ 0xd9, 0xdd, 0xb0, 0xba ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a13, [a13]#-0x5510" + - + input: + bytes: [ 0x9b, 0x04, 0x05, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d4, d4, #0x50" + - + input: + bytes: [ 0x1d, 0x00, 0x02, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x4" + - + input: + bytes: [ 0x37, 0x00, 0x61, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0x6, #0x1" + - + input: + bytes: [ 0x6e, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0xc" + - + input: + bytes: [ 0xdf, 0x1f, 0x23, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x46" + - + input: + bytes: [ 0xb0, 0x1f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a15, #0x1" + - + input: + bytes: [ 0xbf, 0x85, 0x23, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d5, #0x8, #0x46" + - + input: + bytes: [ 0x6d, 0xff, 0x10, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x3e0" + - + input: + bytes: [ 0x40, 0x5f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a15, a5" + - + input: + bytes: [ 0x3c, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x10" + - + input: + bytes: [ 0xdf, 0x0c, 0xe0, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d12, #0, #-0x40" + - + input: + bytes: [ 0xd9, 0x22, 0x26, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x1066" + - + input: + bytes: [ 0xfe, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x38" + - + input: + bytes: [ 0x60, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a2, d15" + - + input: + bytes: [ 0x2e, 0x36 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0x3, #0xc" + - + input: + bytes: [ 0x6f, 0x19, 0x13, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d9, #0x1, #0x26" + - + input: + bytes: [ 0x3f, 0x0f, 0xf0, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d15, d0, #-0x20" + - + input: + bytes: [ 0x4b, 0xf1, 0x51, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d0, d1, d15" + - + input: + bytes: [ 0xda, 0x7f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x7f" + - + input: + bytes: [ 0xd9, 0x55, 0xc0, 0x88 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x7200" + - + input: + bytes: [ 0x0f, 0x00, 0xb0, 0x21 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "clz d2, d0" + - + input: + bytes: [ 0x6d, 0xff, 0x67, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x332" + - + input: + bytes: [ 0x1d, 0x00, 0xaa, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x154" + - + input: + bytes: [ 0xf6, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d0, #0x14" + - + input: + bytes: [ 0x2e, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #0x6" + - + input: + bytes: [ 0x6d, 0xff, 0xba, 0xf9 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xc8c" + - + input: + bytes: [ 0x37, 0x0f, 0xe1, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d15, #0x1, #0x1" + - + input: + bytes: [ 0x06, 0xec ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d12, #-0x2" + - + input: + bytes: [ 0x37, 0xf0, 0x02, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0x1e, #0x2" + - + input: + bytes: [ 0x6d, 0x00, 0xfc, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x23f8" + - + input: + bytes: [ 0x6d, 0xff, 0x32, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x19c" + - + input: + bytes: [ 0x37, 0x9f, 0x83, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d9, #0x3, #0x3" + - + input: + bytes: [ 0x5f, 0x0f, 0x28, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x50" + - + input: + bytes: [ 0xd9, 0x22, 0x22, 0x61 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x11a2" + - + input: + bytes: [ 0x3b, 0x00, 0x50, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d5, #0x500" + - + input: + bytes: [ 0x6f, 0x0f, 0xfe, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0, #-0x4" + - + input: + bytes: [ 0xee, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0x4" + - + input: + bytes: [ 0xdf, 0x08, 0x6a, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d8, #0, #0xd4" + - + input: + bytes: [ 0x7f, 0xf0, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d0, d15, #0xa0" + - + input: + bytes: [ 0xee, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x44" + - + input: + bytes: [ 0x8f, 0xf0, 0x01, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d2, d0, #0x1f" + - + input: + bytes: [ 0x02, 0x92 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d2, d9" + - + input: + bytes: [ 0x8f, 0x21, 0x00, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d15, d1, #0x2" + - + input: + bytes: [ 0x3b, 0x00, 0x08, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d5, #0x80" + - + input: + bytes: [ 0x4e, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jgtz d15, #0x6" + - + input: + bytes: [ 0xee, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x6" + - + input: + bytes: [ 0xac, 0xa2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x4, d15" + - + input: + bytes: [ 0xb7, 0x1f, 0x81, 0x2b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d2, d15, #0x1, #0x17, #0x1" + - + input: + bytes: [ 0x3b, 0x70, 0x04, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #0x47" + - + input: + bytes: [ 0x20, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.a sp, #0x8" + - + input: + bytes: [ 0x8b, 0x03, 0x03, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d3, #0x30" + - + input: + bytes: [ 0x9a, 0xf0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d0, #-0x1" + - + input: + bytes: [ 0xd9, 0x55, 0x3c, 0xea ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a5, [a5]#-0x5c44" + - + input: + bytes: [ 0x09, 0x41, 0x84, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d1, [a4]#0x4" + - + input: + bytes: [ 0x89, 0xaf, 0xa4, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [sp]#0x24, d15" + - + input: + bytes: [ 0xa0, 0x55 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a5, #0x5" + - + input: + bytes: [ 0x37, 0x0f, 0xe8, 0x1b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d1, d15, #0x17, #0x8" + - + input: + bytes: [ 0x3c, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x2" + - + input: + bytes: [ 0x37, 0x00, 0x68, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d5, d0, #0, #0x8" + - + input: + bytes: [ 0x5f, 0x8f, 0x66, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d8, #0xcc" + - + input: + bytes: [ 0xda, 0x22 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0x22" + - + input: + bytes: [ 0x49, 0x33, 0x14, 0x8a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a3, [a3]#-0x1ec" + - + input: + bytes: [ 0x8f, 0x0a, 0x50, 0xa1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d10, d10, #0x100" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x28 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a2, #0x8000" + - + input: + bytes: [ 0x8f, 0x28, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d0, d8, #0x2" + - + input: + bytes: [ 0x49, 0x44, 0x00, 0x1a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [a4]#0x40" + - + input: + bytes: [ 0x6d, 0x00, 0x49, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x2292" + - + input: + bytes: [ 0xee, 0x17 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x2e" + - + input: + bytes: [ 0x6d, 0x00, 0x8b, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0x516" + - + input: + bytes: [ 0x5f, 0x0f, 0xdf, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x1be" + - + input: + bytes: [ 0xa6, 0x52 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d2, d5" + - + input: + bytes: [ 0x1e, 0xf3 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #-0x1, #0x6" + - + input: + bytes: [ 0x37, 0xf0, 0x02, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0x4, #0x2" + - + input: + bytes: [ 0xdf, 0x0f, 0x68, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0, #-0x130" + - + input: + bytes: [ 0x06, 0x11 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d1, #0x1" + - + input: + bytes: [ 0x37, 0x0f, 0x02, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d15, d15, d0, #0x1c, #0x2" + - + input: + bytes: [ 0x6d, 0xff, 0x94, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0xd8" + - + input: + bytes: [ 0x2d, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "calli a15" + - + input: + bytes: [ 0x0b, 0x75, 0x00, 0xf2 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.eq d15, d5, d7" + - + input: + bytes: [ 0x82, 0x54 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x5" + - + input: + bytes: [ 0x37, 0xf0, 0x02, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0x1c, #0x2" + - + input: + bytes: [ 0xee, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #-0x1e" + - + input: + bytes: [ 0x6d, 0xff, 0xeb, 0x3d ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1842a" + - + input: + bytes: [ 0xd9, 0xff, 0xe4, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0xc64" + - + input: + bytes: [ 0x5f, 0x01, 0x0d, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d1, d0, #0x1a" + - + input: + bytes: [ 0x91, 0x30, 0x00, 0x57 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a5, #0x7003" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e0, d0" + - + input: + bytes: [ 0xde, 0x1c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0x1, #0x38" + - + input: + bytes: [ 0x6d, 0xff, 0xb1, 0x2a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x1aa9e" + - + input: + bytes: [ 0x7b, 0x00, 0x12, 0xd4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d13, #0x4120" + - + input: + bytes: [ 0x49, 0xf2, 0x08, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a15]#0x8" + - + input: + bytes: [ 0x37, 0xf0, 0x03, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d15, #0x8, #0x3" + - + input: + bytes: [ 0xee, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0x4" + - + input: + bytes: [ 0x06, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d1, #-0x1" + - + input: + bytes: [ 0x7e, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x6" + - + input: + bytes: [ 0x6d, 0xff, 0x58, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x950" + - + input: + bytes: [ 0xd9, 0xff, 0x20, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x60" + - + input: + bytes: [ 0x6d, 0xff, 0xa7, 0xfe ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #-0x2b2" + - + input: + bytes: [ 0x02, 0x68 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d8, d6" + - + input: + bytes: [ 0x1d, 0x00, 0x8a, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x314" + - + input: + bytes: [ 0xd7, 0x10, 0x21, 0x0f ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "imask e0, #0x1, d15, #0x1" + - + input: + bytes: [ 0x49, 0xa4, 0x08, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a4, [sp]#0x8" + - + input: + bytes: [ 0x82, 0x34 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x3" + - + input: + bytes: [ 0x92, 0x44 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d4, d15, #0x4" + - + input: + bytes: [ 0x91, 0x20, 0x00, 0xd8 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a13, #0x8002" + - + input: + bytes: [ 0x82, 0xf1 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d1, #-0x1" + - + input: + bytes: [ 0x3b, 0x80, 0x00, 0x40 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x8" + - + input: + bytes: [ 0x3c, 0x3a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x74" + - + input: + bytes: [ 0x82, 0x64 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d4, #0x6" + - + input: + bytes: [ 0x01, 0x2f, 0x30, 0xf4 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ge.a d15, a15, a2" + - + input: + bytes: [ 0xd9, 0xff, 0x24, 0x96 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a15, [a15]#0x6264" + - + input: + bytes: [ 0x8e, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlez d15, #0x1e" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x48 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a4, #0x8000" + - + input: + bytes: [ 0xa6, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d0, d1" + - + input: + bytes: [ 0xdc, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ji a14" + - + input: + bytes: [ 0x1d, 0x00, 0x83, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0x106" + - + input: + bytes: [ 0xd9, 0x22, 0x4c, 0xb0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a2, [a2]#0x6cc" + - + input: + bytes: [ 0x5f, 0x0f, 0x29, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x52" + - + input: + bytes: [ 0x37, 0x00, 0xe8, 0xfb ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d15, d0, #0x17, #0x8" + - + input: + bytes: [ 0x6f, 0x0f, 0xf5, 0xff ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0, #-0x16" + - + input: + bytes: [ 0x3b, 0xb0, 0x02, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0x2b" + - + input: + bytes: [ 0x7c, 0x2a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.a a2, #0x14" diff --git a/tests/MC/TriCore/ldst_br_circ.s.yaml b/tests/MC/TriCore/ldst_br_circ.s.yaml new file mode 100644 index 0000000000..34fc412cc5 --- /dev/null +++ b/tests/MC/TriCore/ldst_br_circ.s.yaml @@ -0,0 +1,415 @@ +test_cases: + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.i [p0+r]" + - + input: + bytes: [ 0xa9, 0x00, 0x8a, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.i [p0+c]#0xa" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.w [p0+r]" + - + input: + bytes: [ 0xa9, 0x00, 0x0a, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.w [p0+c]#0xa" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.wi [p0+r]" + - + input: + bytes: [ 0xa9, 0x00, 0x4a, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.wi [p0+c]#0xa" + - + input: + bytes: [ 0x69, 0x02, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmpswap.w [p0+r], e2" + - + input: + bytes: [ 0x69, 0x02, 0xca, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmpswap.w [p0+c]#0xa, e2" + - + input: + bytes: [ 0x29, 0x02, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a2, [p0+r]" + - + input: + bytes: [ 0x29, 0x02, 0x8a, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a2, [p0+c]#0xa" + - + input: + bytes: [ 0x29, 0x02, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.b d2, [p0+r]" + - + input: + bytes: [ 0x29, 0x02, 0x0a, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.b d2, [p0+c]#0xa" + - + input: + bytes: [ 0x29, 0x02, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d2, [p0+r]" + - + input: + bytes: [ 0x29, 0x02, 0x4a, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d2, [p0+c]#0xa" + - + input: + bytes: [ 0x29, 0x02, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.d e2, [p0+r]" + - + input: + bytes: [ 0x29, 0x02, 0x4a, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.d e2, [p0+c]#0xa" + - + input: + bytes: [ 0x29, 0x02, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.da p2, [p0+r]" + - + input: + bytes: [ 0x29, 0x02, 0xca, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.da p2, [p0+c]#0xa" + - + input: + bytes: [ 0x29, 0x02, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d2, [p0+r]" + - + input: + bytes: [ 0x29, 0x02, 0x8a, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d2, [p0+c]#0xa" + - + input: + bytes: [ 0x29, 0x02, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d2, [p0+r]" + - + input: + bytes: [ 0x29, 0x02, 0xca, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d2, [p0+c]#0xa" + - + input: + bytes: [ 0x29, 0x02, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.q d2, [p0+r]" + - + input: + bytes: [ 0x29, 0x02, 0x0a, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.q d2, [p0+c]#0xa" + - + input: + bytes: [ 0x29, 0x02, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d2, [p0+r]" + - + input: + bytes: [ 0x29, 0x02, 0x0a, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d2, [p0+c]#0xa" + - + input: + bytes: [ 0x69, 0x02, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ldmst [p0+r], e2" + - + input: + bytes: [ 0x69, 0x02, 0x4a, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ldmst [p0+c]#0xa, e2" + - + input: + bytes: [ 0xa9, 0x02, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [p0+r], a2" + - + input: + bytes: [ 0xa9, 0x02, 0x8a, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [p0+c]#0xa, a2" + - + input: + bytes: [ 0xa9, 0x02, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [p0+r], d2" + - + input: + bytes: [ 0xa9, 0x02, 0x0a, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [p0+c]#0xa, d2" + - + input: + bytes: [ 0xa9, 0x02, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.d [p0+r], e2" + - + input: + bytes: [ 0xa9, 0x02, 0x4a, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.d [p0+c]#0xa, e2" + - + input: + bytes: [ 0xa9, 0x02, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.da [p0+r], p2" + - + input: + bytes: [ 0xa9, 0x02, 0xca, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.da [p0+c]#0xa, p2" + - + input: + bytes: [ 0xa9, 0x02, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [p0+r], d2" + - + input: + bytes: [ 0xa9, 0x02, 0x8a, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [p0+c]#0xa, d2" + - + input: + bytes: [ 0xa9, 0x02, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.q [p0+r], d2" + - + input: + bytes: [ 0xa9, 0x02, 0x0a, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.q [p0+c]#0xa, d2" + - + input: + bytes: [ 0xa9, 0x02, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [p0+r], d2" + - + input: + bytes: [ 0xa9, 0x02, 0x0a, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [p0+c]#0xa, d2" + - + input: + bytes: [ 0x69, 0x02, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "swap.w [p0+r], d2" + - + input: + bytes: [ 0x69, 0x02, 0x0a, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "swap.w [p0+c]#0xa, d2" + - + input: + bytes: [ 0x69, 0x02, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "swapmsk.w [p0+r], e2" + - + input: + bytes: [ 0x69, 0x02, 0x8a, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "swapmsk.w [p0+c]#0xa, e2" diff --git a/tests/MC/TriCore/rr_insn.s.yaml b/tests/MC/TriCore/rr_insn.s.yaml new file mode 100644 index 0000000000..5f75b11a79 --- /dev/null +++ b/tests/MC/TriCore/rr_insn.s.yaml @@ -0,0 +1,46 @@ +test_cases: + - + input: + bytes: [ 0x0b, 0x20, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "abs d0, d2" + - + input: + bytes: [ 0x0b, 0x60, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "abs.b d0, d6" + - + input: + bytes: [ 0x0b, 0x40, 0xc0, 0x27 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "abs.h d2, d4" + - + input: + bytes: [ 0x0b, 0x10, 0xd0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "abss d0, d1" + - + input: + bytes: [ 0x0b, 0x10, 0xd0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "abss.h d0, d1" diff --git a/tests/MC/TriCore/tc110.s.yaml b/tests/MC/TriCore/tc110.s.yaml new file mode 100644 index 0000000000..f7af4985f8 --- /dev/null +++ b/tests/MC/TriCore/tc110.s.yaml @@ -0,0 +1,5617 @@ +test_cases: + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "abs d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "abs.b d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "abs.h d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "absdif d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "absdif d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "absdif.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "absdif.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "absdifs d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "absdifs d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "absdifs.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "absdifs.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "abss d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "abss.b d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "abss.h d0, d0" + - + input: + bytes: [ 0x1a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "add d15, d0, d0" + - + input: + bytes: [ 0x42, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "add d0, d0" + - + input: + bytes: [ 0x9a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "add d15, d0, #0" + - + input: + bytes: [ 0xc2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "add d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "add d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "add d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "add.a a0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "add.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "add.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "addc d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "addc d0, d0, #0" + - + input: + bytes: [ 0x1b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "addi d0, d0, #0" + - + input: + bytes: [ 0x9b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "addih d0, d0, #0" + - + input: + bytes: [ 0x11, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "addih.a a0, a0, #0" + - + input: + bytes: [ 0x22, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "adds d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "adds d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "adds d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "adds.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "adds.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "adds.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "adds.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "adds.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "adds.u d0, d0, #0" + - + input: + bytes: [ 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "addsc.a a0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "addsc.a a0, a0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "addsc.at a0, a0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "addx d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "addx d0, d0, #0" + - + input: + bytes: [ 0x16, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and d0, d0" + - + input: + bytes: [ 0x96, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and d15, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and d0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and.ne d0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "andn d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "andn d0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "bisr #0" + - + input: + bytes: [ 0xad, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "bisr #0" + - + input: + bytes: [ 0x4b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "bmerge d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "bsplit e0, d0" + - + input: + bytes: [ 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "cadd d0, d15, d0" + - + input: + bytes: [ 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "cadd d0, d15, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "cadd d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "cadd d0, d0, d0, #0" + - + input: + bytes: [ 0x21, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "cadd.a a0, d0, a0, a0" + - + input: + bytes: [ 0xa1, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "cadd.a a0, d0, a0, #0" + - + input: + bytes: [ 0x4a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "caddn d0, d15, d0" + - + input: + bytes: [ 0xca, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "caddn d0, d15, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "caddn d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "caddn d0, d0, d0, #0" + - + input: + bytes: [ 0x21, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "caddn.a a0, d0, a0, a0" + - + input: + bytes: [ 0xa1, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "caddn.a a0, d0, a0, #0" + - + input: + bytes: [ 0x6d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "call #0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "calla #0" + - + input: + bytes: [ 0x2d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "calli a0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "clo d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "clo.b d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "clo.h d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "cls d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xe0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "cls.b d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xe0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "cls.h d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xb0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "clz d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "clz.b d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "clz.h d0, d0" + - + input: + bytes: [ 0x2a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "cmov d0, d15, d0" + - + input: + bytes: [ 0xaa, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "cmov d0, d15, #0" + - + input: + bytes: [ 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "cmovn d0, d15, d0" + - + input: + bytes: [ 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "cmovn d0, d15, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "csub d0, d0, d0, d0" + - + input: + bytes: [ 0x21, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "csub.a a0, d0, a0, a0" + - + input: + bytes: [ 0x2b, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "csubn d0, d0, d0, d0" + - + input: + bytes: [ 0x21, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "csubn.a a0, d0, a0, a0" + - + input: + bytes: [ 0x00, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "debug" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "debug" + - + input: + bytes: [ 0x77, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "dextr d0, d0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "dextr d0, d0, d0, d0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "difsc.a d0, a0, a0, #0" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "disable" + - + input: + bytes: [ 0x0d, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "dsync" + - + input: + bytes: [ 0x72, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "dvadj e0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "dvadj e0, e0, d0" + - + input: + bytes: [ 0x4f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "dvinit e0, d0, d0" + - + input: + bytes: [ 0x4f, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "dvinit.b e0, d0, d0" + - + input: + bytes: [ 0x4f, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "dvinit.bu e0, d0, d0" + - + input: + bytes: [ 0x4f, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "dvinit.h e0, d0, d0" + - + input: + bytes: [ 0x4f, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "dvinit.hu e0, d0, d0" + - + input: + bytes: [ 0x4f, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "dvinit.u e0, d0, d0" + - + input: + bytes: [ 0x32, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "dvstep e0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "dvstep e0, e0, d0" + - + input: + bytes: [ 0xb2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "dvstep.u e0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "dvstep.u e0, e0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "enable" + - + input: + bytes: [ 0x3a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "eq d15, d0, d0" + - + input: + bytes: [ 0xba, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "eq d15, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "eq d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "eq.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "eq.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "eq.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "eq.w d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x60, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "eqany.b d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "eqany.b d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x60, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "eqany.h d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "eqany.h d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "eqz.a d0, a0" + - + input: + bytes: [ 0x17, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "extr d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "extr d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "extr d0, d0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ge d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x30, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ge.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ge.u d0, d0, #0" + - + input: + bytes: [ 0x37, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "imask e0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "imask e0, d0, d0, #0" + - + input: + bytes: [ 0xb7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "imask e0, #0, #0, #0" + - + input: + bytes: [ 0xd7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "imask e0, #0, d0, #0" + - + input: + bytes: [ 0x67, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ins.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x97, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, e0" + - + input: + bytes: [ 0xb7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, #0, #0" + - + input: + bytes: [ 0xd7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x67, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "insn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "isync" + - + input: + bytes: [ 0x5c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "j #0" + - + input: + bytes: [ 0x1d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "j #0" + - + input: + bytes: [ 0x9d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ja #0" + - + input: + bytes: [ 0x1e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0" + - + input: + bytes: [ 0x6e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jeq d15, #0, #0" + - + input: + bytes: [ 0x5f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jeq d0, d0, #0" + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jeq d0, #0, #0" + - + input: + bytes: [ 0x7d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jeq.a a0, a0, #0" + - + input: + bytes: [ 0x7f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jge d0, d0, #0" + - + input: + bytes: [ 0xff, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jge d0, #0, #0" + - + input: + bytes: [ 0x7f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jge.u d0, d0, #0" + - + input: + bytes: [ 0xff, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jge.u d0, #0, #0" + - + input: + bytes: [ 0xfe, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jgez d0, #0" + - + input: + bytes: [ 0x7e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jgtz d0, #0" + - + input: + bytes: [ 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ji a0" + - + input: + bytes: [ 0x2d, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ji a0" + - + input: + bytes: [ 0x5d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jl #0" + - + input: + bytes: [ 0xdd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jla #0" + - + input: + bytes: [ 0xbe, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jlez d0, #0" + - + input: + bytes: [ 0x2d, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jli a0" + - + input: + bytes: [ 0x3f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jlt d0, d0, #0" + - + input: + bytes: [ 0xbf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jlt d0, #0, #0" + - + input: + bytes: [ 0x3f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jlt.u d0, d0, #0" + - + input: + bytes: [ 0xbf, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jlt.u d0, #0, #0" + - + input: + bytes: [ 0x3e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jltz d0, #0" + - + input: + bytes: [ 0x9e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0" + - + input: + bytes: [ 0xee, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jne d15, #0, #0" + - + input: + bytes: [ 0x5f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jne d0, d0, #0" + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jne d0, #0, #0" + - + input: + bytes: [ 0x7d, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jne.a a0, a0, #0" + - + input: + bytes: [ 0x1f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jned d0, d0, #0" + - + input: + bytes: [ 0x9f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jned d0, #0, #0" + - + input: + bytes: [ 0x1f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jnei d0, d0, #0" + - + input: + bytes: [ 0x9f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jnei d0, #0, #0" + - + input: + bytes: [ 0xae, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jnz d15, #0" + - + input: + bytes: [ 0xde, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jnz d0, #0" + - + input: + bytes: [ 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jnz.a a0, #0" + - + input: + bytes: [ 0xbd, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jnz.a a0, #0" + - + input: + bytes: [ 0x4e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0, #0" + - + input: + bytes: [ 0x6f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jnz.t d0, #0, #0" + - + input: + bytes: [ 0x2e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jz d15, #0" + - + input: + bytes: [ 0x5e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jz d0, #0" + - + input: + bytes: [ 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jz.a a0, #0" + - + input: + bytes: [ 0xbd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jz.a a0, #0" + - + input: + bytes: [ 0x0e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #0" + - + input: + bytes: [ 0x6f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "jz.t d0, #0, #0" + - + input: + bytes: [ 0x0c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.a a0, [a15]#0" + - + input: + bytes: [ 0x28, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.a a15, [a0]#0" + - + input: + bytes: [ 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0+]" + - + input: + bytes: [ 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]" + - + input: + bytes: [ 0x99, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.a a0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.a a0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.a a0, [p0+c]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.a a0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]#0" + - + input: + bytes: [ 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.b d15, [a0]#0" + - + input: + bytes: [ 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.b d0, [a15]#0" + - + input: + bytes: [ 0x44, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.b d0, [a0+]" + - + input: + bytes: [ 0x98, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.b d0, [a0]" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.b d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.b d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.b d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.b d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.b d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.b d0, [a0]#0" + - + input: + bytes: [ 0x58, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0]" + - + input: + bytes: [ 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a0]#0" + - + input: + bytes: [ 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0" + - + input: + bytes: [ 0xc4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0+]" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.bu d0, [p0+r]" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.bu d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.bu d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.bu d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.d e0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.d e0, [p0+r]" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.d e0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.d e0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.d e0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.d e0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.da p0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.da p0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.da p0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.da p0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.da p0, [a0]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.da p0, #0" + - + input: + bytes: [ 0x24, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0+]" + - + input: + bytes: [ 0x48, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.h d15, [a0]#0" + - + input: + bytes: [ 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.h d0, [a15]#0" + - + input: + bytes: [ 0xd8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0]" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.h d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.h d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.h d0, [p0+c]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.h d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.hu d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.hu d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.hu d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a0]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.hu d0, #0" + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.q d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.q d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.q d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.q d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.q d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.q d0, [a0]#0" + - + input: + bytes: [ 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]" + - + input: + bytes: [ 0xa4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0+]" + - + input: + bytes: [ 0xc8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.w d15, [a0]#0" + - + input: + bytes: [ 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.w d0, [a15]#0" + - + input: + bytes: [ 0x19, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.w d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.w d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.w d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.w d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ldlcx #0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ldlcx [a0]#0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ldmst [a0+]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ldmst [p0+r], e0" + - + input: + bytes: [ 0xe5, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ldmst #0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ldmst [+a0]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ldmst [p0+c]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ldmst [a0]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lducx [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lducx #0" + - + input: + bytes: [ 0xc5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lea a0, #0" + - + input: + bytes: [ 0xd9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lea a0, [a0]#0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lea a0, [a0]#0" + - + input: + bytes: [ 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "loop a0, #0xffffffe0" + - + input: + bytes: [ 0xfd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "loop a0, #0" + - + input: + bytes: [ 0x7a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lt d15, d0, d0" + - + input: + bytes: [ 0xfa, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lt d15, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lt d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lt.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lt.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lt.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lt.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lt.hu d0, d0, d0" + - + input: + bytes: [ 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lt.u d15, d0, d0" + - + input: + bytes: [ 0x86, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lt.u d15, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lt.w d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "lt.wu d0, d0, d0" + - + input: + bytes: [ 0x03, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "madd d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "madd d0, d0, d0, #0" + - + input: + bytes: [ 0x83, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x13, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "maddm e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "maddm e0, e0, d0, d0" + - + input: + bytes: [ 0x83, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0" + - + input: + bytes: [ 0x43, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "maddm.q e0, e0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "maddm.u e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "maddm.u e0, e0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "maddms e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "maddms e0, e0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "maddms.u e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "maddms.u e0, e0, d0, d0" + - + input: + bytes: [ 0x43, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "maddr.h d0, e0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "maddr.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "maddrs.h d0, e0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x98, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "maddrs.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "madds d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "madds d0, d0, d0, #0" + - + input: + bytes: [ 0x83, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x13, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "madds.u d0, d0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "madds.u d0, d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "max d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "max d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "max.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "max.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "max.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "max.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "max.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "max.u d0, d0, #0" + - + input: + bytes: [ 0x4d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mfcr d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "min d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "min d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "min.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "min.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "min.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "min.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "min.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "min.u d0, d0, #0" + - + input: + bytes: [ 0x02, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mov d0, d0" + - + input: + bytes: [ 0x82, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mov d0, #0" + - + input: + bytes: [ 0xc6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mov d15, #0" + - + input: + bytes: [ 0x3b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mov d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mov d0, d0" + - + input: + bytes: [ 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mov.a a0, d0" + - + input: + bytes: [ 0x01, 0x00, 0x30, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mov.a a0, d0" + - + input: + bytes: [ 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mov.aa a0, a0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mov.aa a0, a0" + - + input: + bytes: [ 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mov.d d0, a0" + - + input: + bytes: [ 0x01, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mov.d d0, a0" + - + input: + bytes: [ 0xbb, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mov.u d0, #0" + - + input: + bytes: [ 0x7b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "movh d0, #0" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "movh.a a0, #0" + - + input: + bytes: [ 0x00, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "movz.a a0" + - + input: + bytes: [ 0x23, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msub d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msub d0, d0, d0, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x33, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubm e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubm e0, e0, d0, d0" + - + input: + bytes: [ 0xa3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0" + - + input: + bytes: [ 0x63, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubm.q e0, e0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubm.u e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubm.u e0, e0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubms e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubms e0, e0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubms.u e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubms.u e0, e0, d0, d0" + - + input: + bytes: [ 0x63, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubr.h d0, e0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubr.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubrs.h d0, e0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x98, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubrs.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubs d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubs d0, d0, d0, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x33, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubs.u d0, d0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "msubs.u d0, d0, d0, d0" + - + input: + bytes: [ 0xcd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mtcr #0, d0" + - + input: + bytes: [ 0xe2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mul d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mul d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mul d0, d0, d0" + - + input: + bytes: [ 0xb3, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0, #0" + - + input: + bytes: [ 0x93, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mul.q d0, d0, d0, #0" + - + input: + bytes: [ 0x53, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mulm e0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0xa0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mulm e0, d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mulm.u e0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x80, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mulm.u e0, d0, d0" + - + input: + bytes: [ 0xb3, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0, #0" + - + input: + bytes: [ 0x93, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "mulr.q d0, d0, d0, #0" + - + input: + bytes: [ 0x53, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "muls d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0xa0, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "muls d0, d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "muls.u d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "muls.u d0, d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "nand d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "nand d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "nand.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ne d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ne.a d0, a0, a0" + - + input: + bytes: [ 0x01, 0x00, 0x90, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "nez.a d0, a0" + - + input: + bytes: [ 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x36, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "nor d0" + - + input: + bytes: [ 0x0f, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "nor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x60, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "nor d0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x56, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or d0, d0" + - + input: + bytes: [ 0xd6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or d15, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or d0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x70, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or.ne d0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "orn d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xe0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "orn d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "orn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x6b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "pack d0, e0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "parity d0, d0" + - + input: + bytes: [ 0x00, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ret" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "ret" + - + input: + bytes: [ 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "rfe" + - + input: + bytes: [ 0x0d, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "rfe" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "rslcx" + - + input: + bytes: [ 0x2f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "rstv" + - + input: + bytes: [ 0xd2, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "rsub d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "rsub d0, d0, #0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "rsubs d0, d0, #0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "rsubs.u d0, d0, #0" + - + input: + bytes: [ 0xd2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sat.b d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sat.b d0, d0" + - + input: + bytes: [ 0xd2, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sat.bu d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sat.bu d0, d0" + - + input: + bytes: [ 0xd2, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sat.h d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sat.h d0, d0" + - + input: + bytes: [ 0xd2, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sat.hu d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sat.hu d0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sel d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sel d0, d0, d0, #0" + - + input: + bytes: [ 0x21, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sel.a a0, d0, a0, a0" + - + input: + bytes: [ 0xa1, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sel.a a0, d0, a0, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "seln d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "seln d0, d0, d0, #0" + - + input: + bytes: [ 0x21, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "seln.a a0, d0, a0, a0" + - + input: + bytes: [ 0xa1, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "seln.a a0, d0, a0, #0" + - + input: + bytes: [ 0x26, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh d0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.b d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.b d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x70, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.h d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.h d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.lt.u d0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.nand.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.ne d0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.orn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.xnor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sh.xor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sha d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sha d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sha d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x10, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sha.b d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sha.b d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sha.h d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sha.h d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "shas d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "shas d0, d0, #0" + - + input: + bytes: [ 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.a [a0]#0, a15" + - + input: + bytes: [ 0x2c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.a [a15]#0, a0" + - + input: + bytes: [ 0x54, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.a [a0+], a0" + - + input: + bytes: [ 0x84, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.a [a0], a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.a [a0+]#0, a0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.a [p0+r], a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.a [+a0]#0, a0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.a [p0+c]#0, a0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.a #0, a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.a [a0]#0, a0" + - + input: + bytes: [ 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.b [a0], d0" + - + input: + bytes: [ 0x8c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.b [a15]#0, d0" + - + input: + bytes: [ 0xa8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.b [a0]#0, d15" + - + input: + bytes: [ 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.b [a0+], d0" + - + input: + bytes: [ 0x25, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.b #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.b [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.b [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.b [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.b [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.b [a0]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.d [a0+]#0, e0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.d [p0+r], e0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.d #0, e0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.d [+a0]#0, e0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.d [p0+c]#0, e0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.d [a0]#0, e0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.da [a0+]#0, p0" + - + input: + bytes: [ 0xa9, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.da [p0+r], p0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.da [+a0]#0, p0" + - + input: + bytes: [ 0xa9, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.da [p0+c]#0, p0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.da [a0]#0, p0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.da #0, p0" + - + input: + bytes: [ 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.h [a0+], d0" + - + input: + bytes: [ 0x4c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.h [a15]#0, d0" + - + input: + bytes: [ 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.h [a0]#0, d15" + - + input: + bytes: [ 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.h [a0], d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.h [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.h [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.h [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.h [p0+c]#0, d0" + - + input: + bytes: [ 0x25, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.h #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.h [a0]#0, d0" + - + input: + bytes: [ 0x65, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.q #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.q [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.q [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.q [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.q [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.q [a0]#0, d0" + - + input: + bytes: [ 0xd5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.t #0, #0, #0" + - + input: + bytes: [ 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.w [a0], d0" + - + input: + bytes: [ 0x94, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.w [a0+], d0" + - + input: + bytes: [ 0xcc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.w [a15]#0, d0" + - + input: + bytes: [ 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d15" + - + input: + bytes: [ 0x59, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.w #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.w [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.w [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.w [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.w [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "stlcx #0" + - + input: + bytes: [ 0x49, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "stlcx [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "stucx #0" + - + input: + bytes: [ 0x49, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "stucx [a0]#0" + - + input: + bytes: [ 0x5a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sub d15, d0, d0" + - + input: + bytes: [ 0xa2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sub d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sub d0, d0, d0" + - + input: + bytes: [ 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sub.a sp, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sub.a a0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sub.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "sub.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "subc d0, d0, d0" + - + input: + bytes: [ 0x62, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "subs d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "subs d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "subs.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "subs.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "subs.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "subs.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "subs.u d0, d0, d0" + - + input: + bytes: [ 0x01, 0x00, 0x10, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "subsc.a a0, a0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "subx d0, d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "svlcx" + - + input: + bytes: [ 0x49, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "swap.a [a0+]#0, a0" + - + input: + bytes: [ 0x69, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "swap.a [p0+r], a0" + - + input: + bytes: [ 0x49, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "swap.a [+a0]#0, a0" + - + input: + bytes: [ 0x69, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "swap.a [p0+c]#0, a0" + - + input: + bytes: [ 0xe5, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "swap.a #0, a0" + - + input: + bytes: [ 0x49, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "swap.a [a0]#0, a0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "swap.w [a0+]#0, d0" + - + input: + bytes: [ 0x69, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "swap.w [p0+r], d0" + - + input: + bytes: [ 0xe5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "swap.w #0, d0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "swap.w [+a0]#0, d0" + - + input: + bytes: [ 0x69, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "swap.w [p0+c]#0, d0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "swap.w [a0]#0, d0" + - + input: + bytes: [ 0xad, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "syscall #0" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "trapsv" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "trapv" + - + input: + bytes: [ 0x4b, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "unpack e0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "xnor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "xnor d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "xnor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "xor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "xor d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "xor.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "xor.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "xor.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "xor.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "xor.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "xor.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "xor.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "xor.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "xor.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "xor.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "xor.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "xor.ne d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_110" ] + expected: + insns: + - + asm_text: "xor.t d0, d0, #0, d0, #0" diff --git a/tests/MC/TriCore/tc120.s.yaml b/tests/MC/TriCore/tc120.s.yaml new file mode 100644 index 0000000000..ef4f2b79da --- /dev/null +++ b/tests/MC/TriCore/tc120.s.yaml @@ -0,0 +1,6832 @@ +test_cases: + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "abs d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "abs.b d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "abs.h d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "absdif d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "absdif d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "absdif.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "absdif.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "absdifs d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "absdifs d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "absdifs.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "abss d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "abss.h d0, d0" + - + input: + bytes: [ 0x12, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "add d0, d15, d0" + - + input: + bytes: [ 0x92, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "add d0, d15, #0" + - + input: + bytes: [ 0x1a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "add d15, d0, d0" + - + input: + bytes: [ 0x42, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "add d0, d0" + - + input: + bytes: [ 0x9a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "add d15, d0, #0" + - + input: + bytes: [ 0xc2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "add d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "add d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "add d0, d0, #0" + - + input: + bytes: [ 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "add.a a0, a0" + - + input: + bytes: [ 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "add.a a0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "add.a a0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "add.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "add.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "addc d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "addc d0, d0, #0" + - + input: + bytes: [ 0x1b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "addi d0, d0, #0" + - + input: + bytes: [ 0x9b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "addih d0, d0, #0" + - + input: + bytes: [ 0x11, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "addih.a a0, a0, #0" + - + input: + bytes: [ 0x22, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "adds d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "adds d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "adds d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "adds.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "adds.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "adds.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "adds.u d0, d0, #0" + - + input: + bytes: [ 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "addsc.a a0, a0, d15, #0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "addsc.a a0, a0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "addsc.at a0, a0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "addx d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "addx d0, d0, #0" + - + input: + bytes: [ 0x26, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and d0, d0" + - + input: + bytes: [ 0x16, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and d15, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and d0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and.ne d0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "andn d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "andn d0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "bisr #0" + - + input: + bytes: [ 0xad, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "bisr #0" + - + input: + bytes: [ 0x4b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "bmerge d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "bsplit e0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cachea.i [a0+]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cachea.i [p0+r]" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cachea.i [+a0]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cachea.i [p0+c]#0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cachea.i [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cachea.w [a0+]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cachea.w [p0+r]" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cachea.w [+a0]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cachea.w [p0+c]#0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cachea.w [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cachea.wi [a0+]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cachea.wi [p0+r]" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cachea.wi [+a0]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cachea.wi [p0+c]#0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cachea.wi [a0]#0" + - + input: + bytes: [ 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cadd d0, d15, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cadd d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cadd d0, d0, d0, #0" + - + input: + bytes: [ 0xca, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "caddn d0, d15, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "caddn d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "caddn d0, d0, d0, #0" + - + input: + bytes: [ 0x5c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "call #0" + - + input: + bytes: [ 0x6d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "call #0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "calla #0" + - + input: + bytes: [ 0x2d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "calli a0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "clo d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "clo.h d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cls d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xe0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cls.h d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xb0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "clz d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "clz.h d0, d0" + - + input: + bytes: [ 0x2a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cmov d0, d15, d0" + - + input: + bytes: [ 0xaa, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cmov d0, d15, #0" + - + input: + bytes: [ 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cmovn d0, d15, d0" + - + input: + bytes: [ 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "cmovn d0, d15, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "csub d0, d0, d0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "csubn d0, d0, d0, d0" + - + input: + bytes: [ 0x00, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "debug" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "debug" + - + input: + bytes: [ 0x77, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "dextr d0, d0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "dextr d0, d0, d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "disable" + - + input: + bytes: [ 0x0d, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "dsync" + - + input: + bytes: [ 0x6b, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "dvadj e0, e0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "dvinit e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "dvinit.b e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "dvinit.bu e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "dvinit.h e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "dvinit.hu e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "dvinit.u e0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "dvstep e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "dvstep.u e0, e0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "enable" + - + input: + bytes: [ 0x3a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "eq d15, d0, d0" + - + input: + bytes: [ 0xba, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "eq d15, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "eq d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "eq.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "eq.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "eq.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "eq.w d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x60, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "eqany.b d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "eqany.b d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x60, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "eqany.h d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "eqany.h d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "eqz.a d0, a0" + - + input: + bytes: [ 0x17, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "extr d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "extr d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "extr d0, d0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ge d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x30, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ge.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ge.u d0, d0, #0" + - + input: + bytes: [ 0x37, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "imask e0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "imask e0, d0, d0, #0" + - + input: + bytes: [ 0xb7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "imask e0, #0, #0, #0" + - + input: + bytes: [ 0xd7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "imask e0, #0, d0, #0" + - + input: + bytes: [ 0x67, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ins.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x97, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, e0" + - + input: + bytes: [ 0xb7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, #0, #0" + - + input: + bytes: [ 0xd7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x67, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "insn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "isync" + - + input: + bytes: [ 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "j #0" + - + input: + bytes: [ 0x1d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "j #0" + - + input: + bytes: [ 0x9d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ja #0" + - + input: + bytes: [ 0x1e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jeq d15, #0, #0" + - + input: + bytes: [ 0x5f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jeq d0, d0, #0" + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jeq d0, #0, #0" + - + input: + bytes: [ 0x7d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jeq.a a0, a0, #0" + - + input: + bytes: [ 0x7f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jge d0, d0, #0" + - + input: + bytes: [ 0xff, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jge d0, #0, #0" + - + input: + bytes: [ 0x7f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jge.u d0, d0, #0" + - + input: + bytes: [ 0xff, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jge.u d0, #0, #0" + - + input: + bytes: [ 0xce, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jgez d0, #0" + - + input: + bytes: [ 0x4e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jgtz d0, #0" + - + input: + bytes: [ 0xdc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ji a0" + - + input: + bytes: [ 0x2d, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ji a0" + - + input: + bytes: [ 0x5d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jl #0" + - + input: + bytes: [ 0xdd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jla #0" + - + input: + bytes: [ 0x8e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jlez d0, #0" + - + input: + bytes: [ 0x2d, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jli a0" + - + input: + bytes: [ 0x3f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jlt d0, d0, #0" + - + input: + bytes: [ 0xbf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jlt d0, #0, #0" + - + input: + bytes: [ 0x3f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jlt.u d0, d0, #0" + - + input: + bytes: [ 0xbf, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jlt.u d0, #0, #0" + - + input: + bytes: [ 0x0e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jltz d0, #0" + - + input: + bytes: [ 0x7e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0" + - + input: + bytes: [ 0x5e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jne d15, #0, #0" + - + input: + bytes: [ 0x5f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jne d0, d0, #0" + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jne d0, #0, #0" + - + input: + bytes: [ 0x7d, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jne.a a0, a0, #0" + - + input: + bytes: [ 0x1f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jned d0, d0, #0" + - + input: + bytes: [ 0x9f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jned d0, #0, #0" + - + input: + bytes: [ 0x1f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jnei d0, d0, #0" + - + input: + bytes: [ 0x9f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jnei d0, #0, #0" + - + input: + bytes: [ 0xee, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jnz d15, #0" + - + input: + bytes: [ 0xf6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jnz d0, #0" + - + input: + bytes: [ 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jnz.a a0, #0" + - + input: + bytes: [ 0xbd, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jnz.a a0, #0" + - + input: + bytes: [ 0xae, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0, #0" + - + input: + bytes: [ 0x6f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jnz.t d0, #0, #0" + - + input: + bytes: [ 0x6e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jz d15, #0" + - + input: + bytes: [ 0x76, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jz d0, #0" + - + input: + bytes: [ 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jz.a a0, #0" + - + input: + bytes: [ 0xbd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jz.a a0, #0" + - + input: + bytes: [ 0x2e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #0" + - + input: + bytes: [ 0x6f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "jz.t d0, #0, #0" + - + input: + bytes: [ 0xd8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.a a15, [sp]#0" + - + input: + bytes: [ 0xc8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.a a0, [a15]#0" + - + input: + bytes: [ 0xcc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.a a15, [a0]#0" + - + input: + bytes: [ 0xc4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0+]" + - + input: + bytes: [ 0xd4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]" + - + input: + bytes: [ 0x99, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.a a0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.a a0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.a a0, [p0+c]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.a a0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.b d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.b d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.b d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.b d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.b d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.b d0, [a0]#0" + - + input: + bytes: [ 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0]" + - + input: + bytes: [ 0x0c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a0]#0" + - + input: + bytes: [ 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0" + - + input: + bytes: [ 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0+]" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.bu d0, [p0+r]" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.bu d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.bu d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.bu d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.d e0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.d e0, [p0+r]" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.d e0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.d e0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.d e0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.d e0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.da p0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.da p0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.da p0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.da p0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.da p0, [a0]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.da p0, #0" + - + input: + bytes: [ 0x84, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0+]" + - + input: + bytes: [ 0x8c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.h d15, [a0]#0" + - + input: + bytes: [ 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.h d0, [a15]#0" + - + input: + bytes: [ 0x94, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0]" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.h d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.h d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.h d0, [p0+c]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.h d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.hu d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.hu d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.hu d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a0]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.hu d0, #0" + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.q d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.q d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.q d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.q d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.q d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.q d0, [a0]#0" + - + input: + bytes: [ 0x58, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.w d15, [sp]#0" + - + input: + bytes: [ 0x54, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]" + - + input: + bytes: [ 0x44, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0+]" + - + input: + bytes: [ 0x4c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.w d15, [a0]#0" + - + input: + bytes: [ 0x48, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.w d0, [a15]#0" + - + input: + bytes: [ 0x19, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.w d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.w d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.w d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.w d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ldlcx #0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ldlcx [a0]#0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ldmst [a0+]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ldmst [p0+r], e0" + - + input: + bytes: [ 0xe5, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ldmst #0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ldmst [+a0]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ldmst [p0+c]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ldmst [a0]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "lducx [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "lducx #0" + - + input: + bytes: [ 0xc5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "lea a0, #0" + - + input: + bytes: [ 0xd9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "lea a0, [a0]#0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "lea a0, [a0]#0" + - + input: + bytes: [ 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "loop a0, #0xffffffe0" + - + input: + bytes: [ 0xfd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "loop a0, #0" + - + input: + bytes: [ 0xfd, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "loopu #0" + - + input: + bytes: [ 0x7a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "lt d15, d0, d0" + - + input: + bytes: [ 0xfa, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "lt d15, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "lt d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "lt.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "lt.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "lt.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "lt.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "lt.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "lt.w d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "lt.wu d0, d0, d0" + - + input: + bytes: [ 0x03, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd d0, d0, d0, #0" + - + input: + bytes: [ 0x13, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd e0, e0, d0, d0" + - + input: + bytes: [ 0x83, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x13, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd.u e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madd.u e0, e0, d0, d0" + - + input: + bytes: [ 0x83, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddr.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddr.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x1c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddr.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddrs.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x98, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddrs.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x9c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddrs.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x03, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds d0, d0, d0, #0" + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds e0, e0, d0, d0" + - + input: + bytes: [ 0x83, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x84, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x94, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x13, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds.u d0, d0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds.u d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds.u e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "madds.u e0, e0, d0, d0" + - + input: + bytes: [ 0xc3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "max d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "max d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "max.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "max.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "max.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "max.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "max.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "max.u d0, d0, #0" + - + input: + bytes: [ 0x4d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mfcr d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "min d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "min d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "min.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "min.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "min.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "min.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "min.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "min.u d0, d0, #0" + - + input: + bytes: [ 0x02, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mov d0, d0" + - + input: + bytes: [ 0x82, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mov d0, #0" + - + input: + bytes: [ 0xda, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mov d15, #0" + - + input: + bytes: [ 0x3b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mov d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mov d0, d0" + - + input: + bytes: [ 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mov.a a0, #0" + - + input: + bytes: [ 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mov.a a0, d0" + - + input: + bytes: [ 0x01, 0x00, 0x30, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mov.a a0, d0" + - + input: + bytes: [ 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mov.aa a0, a0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mov.aa a0, a0" + - + input: + bytes: [ 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mov.d d0, a0" + - + input: + bytes: [ 0x01, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mov.d d0, a0" + - + input: + bytes: [ 0xbb, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mov.u d0, #0" + - + input: + bytes: [ 0x7b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "movh d0, #0" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "movh.a a0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub d0, d0, d0, #0" + - + input: + bytes: [ 0x33, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub e0, e0, d0, d0" + - + input: + bytes: [ 0xa3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x33, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub.u e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msub.u e0, e0, d0, d0" + - + input: + bytes: [ 0xe3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubr.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubr.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x1c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubr.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubrs.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x98, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubrs.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x9c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubrs.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x23, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs d0, d0, d0, #0" + - + input: + bytes: [ 0x33, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs e0, e0, d0, d0" + - + input: + bytes: [ 0xa3, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x84, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x94, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x33, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs.u d0, d0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs.u d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs.u e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "msubs.u e0, e0, d0, d0" + - + input: + bytes: [ 0xcd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mtcr #0, d0" + - + input: + bytes: [ 0xe2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mul d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mul d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mul d0, d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mul e0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mul e0, d0, d0" + - + input: + bytes: [ 0xb3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0uu, #0" + - + input: + bytes: [ 0x93, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mul.q d0, d0, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mul.q d0, d0, d0l, #0" + - + input: + bytes: [ 0x93, 0x00, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mul.q d0, d0, d0, #0" + - + input: + bytes: [ 0x93, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mul.q d0, d0u, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mul.q d0, d0l, d0l, #0" + - + input: + bytes: [ 0x93, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mul.q e0, d0, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mul.q e0, d0, d0l, #0" + - + input: + bytes: [ 0x93, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mul.q e0, d0, d0, #0" + - + input: + bytes: [ 0x53, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mul.u e0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mul.u e0, d0, d0" + - + input: + bytes: [ 0xb3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0uu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0uu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0uu, #0" + - + input: + bytes: [ 0x93, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mulr.q d0, d0u, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x1c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "mulr.q d0, d0l, d0l, #0" + - + input: + bytes: [ 0x53, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "muls d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "muls d0, d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "muls.u d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "muls.u d0, d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "nand d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "nand d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "nand.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ne d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ne.a d0, a0, a0" + - + input: + bytes: [ 0x01, 0x00, 0x90, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "nez.a d0, a0" + - + input: + bytes: [ 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x46, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "nor d0" + - + input: + bytes: [ 0x0f, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "nor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x60, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "nor d0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or d0, d0" + - + input: + bytes: [ 0x96, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or d15, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or d0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x70, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or.ne d0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "orn d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xe0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "orn d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "orn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x6b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "pack d0, e0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "parity d0, d0" + - + input: + bytes: [ 0x00, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ret" + - + input: + bytes: [ 0x0d, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "ret" + - + input: + bytes: [ 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "rfe" + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "rfe" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "rfm" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "rslcx" + - + input: + bytes: [ 0x2f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "rstv" + - + input: + bytes: [ 0x32, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "rsub d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "rsub d0, d0, #0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "rsubs d0, d0, #0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "rsubs.u d0, d0, #0" + - + input: + bytes: [ 0x32, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sat.b d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sat.b d0, d0" + - + input: + bytes: [ 0x32, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sat.bu d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sat.bu d0, d0" + - + input: + bytes: [ 0x32, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sat.h d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sat.h d0, d0" + - + input: + bytes: [ 0x32, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sat.hu d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sat.hu d0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sel d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sel d0, d0, d0, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "seln d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "seln d0, d0, d0, #0" + - + input: + bytes: [ 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh d0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x70, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.h d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.h d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.lt.u d0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.nand.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.ne d0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.orn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.xnor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sh.xor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x86, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sha d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sha d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sha d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sha.h d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sha.h d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "shas d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "shas d0, d0, #0" + - + input: + bytes: [ 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.a [sp]#0, a15" + - + input: + bytes: [ 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.a [a0]#0, a15" + - + input: + bytes: [ 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.a [a15]#0, a0" + - + input: + bytes: [ 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.a [a0+], a0" + - + input: + bytes: [ 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.a [a0], a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.a [a0+]#0, a0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.a [p0+r], a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.a [+a0]#0, a0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.a [p0+c]#0, a0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.a #0, a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.a [a0]#0, a0" + - + input: + bytes: [ 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.b [a0], d0" + - + input: + bytes: [ 0x28, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.b [a15]#0, d0" + - + input: + bytes: [ 0x2c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.b [a0]#0, d15" + - + input: + bytes: [ 0x24, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.b [a0+], d0" + - + input: + bytes: [ 0x25, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.b #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.b [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.b [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.b [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.b [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.b [a0]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.d [a0+]#0, e0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.d [p0+r], e0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.d #0, e0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.d [+a0]#0, e0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.d [p0+c]#0, e0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.d [a0]#0, e0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.da [a0+]#0, p0" + - + input: + bytes: [ 0xa9, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.da [p0+r], p0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.da [+a0]#0, p0" + - + input: + bytes: [ 0xa9, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.da [p0+c]#0, p0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.da [a0]#0, p0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.da #0, p0" + - + input: + bytes: [ 0xa4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.h [a0+], d0" + - + input: + bytes: [ 0xa8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.h [a15]#0, d0" + - + input: + bytes: [ 0xac, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.h [a0]#0, d15" + - + input: + bytes: [ 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.h [a0], d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.h [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.h [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.h [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.h [p0+c]#0, d0" + - + input: + bytes: [ 0x25, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.h #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.h [a0]#0, d0" + - + input: + bytes: [ 0x65, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.q #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.q [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.q [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.q [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.q [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.q [a0]#0, d0" + - + input: + bytes: [ 0xd5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.t #0, #0, #0" + - + input: + bytes: [ 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.w [sp]#0, d15" + - + input: + bytes: [ 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.w [a0], d0" + - + input: + bytes: [ 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.w [a0+], d0" + - + input: + bytes: [ 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.w [a15]#0, d0" + - + input: + bytes: [ 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d15" + - + input: + bytes: [ 0x59, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.w #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.w [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.w [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.w [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.w [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "stlcx #0" + - + input: + bytes: [ 0x49, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "stlcx [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "stucx #0" + - + input: + bytes: [ 0x49, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "stucx [a0]#0" + - + input: + bytes: [ 0x52, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sub d0, d15, d0" + - + input: + bytes: [ 0x5a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sub d15, d0, d0" + - + input: + bytes: [ 0xa2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sub d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sub d0, d0, d0" + - + input: + bytes: [ 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sub.a sp, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sub.a a0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sub.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "sub.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "subc d0, d0, d0" + - + input: + bytes: [ 0x62, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "subs d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "subs d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "subs.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "subs.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "subs.u d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "subx d0, d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "svlcx" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "swap.w [a0+]#0, d0" + - + input: + bytes: [ 0x69, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "swap.w [p0+r], d0" + - + input: + bytes: [ 0xe5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "swap.w #0, d0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "swap.w [+a0]#0, d0" + - + input: + bytes: [ 0x69, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "swap.w [p0+c]#0, d0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "swap.w [a0]#0, d0" + - + input: + bytes: [ 0xad, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "syscall #0" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "trapsv" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "trapv" + - + input: + bytes: [ 0x4b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "unpack e0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "xnor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "xnor d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "xnor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "xor d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "xor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "xor d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "xor.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "xor.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "xor.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "xor.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "xor.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "xor.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "xor.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "xor.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "xor.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "xor.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "xor.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "xor.ne d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_120" ] + expected: + insns: + - + asm_text: "xor.t d0, d0, #0, d0, #0" diff --git a/tests/MC/TriCore/tc130.s.yaml b/tests/MC/TriCore/tc130.s.yaml new file mode 100644 index 0000000000..ba702ef1ca --- /dev/null +++ b/tests/MC/TriCore/tc130.s.yaml @@ -0,0 +1,7066 @@ +test_cases: + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "abs d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "abs.b d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "abs.h d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "absdif d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "absdif d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "absdif.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "absdif.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "absdifs d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "absdifs d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "absdifs.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "abss d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "abss.h d0, d0" + - + input: + bytes: [ 0x12, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "add d0, d15, d0" + - + input: + bytes: [ 0x92, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "add d0, d15, #0" + - + input: + bytes: [ 0x1a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "add d15, d0, d0" + - + input: + bytes: [ 0x42, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "add d0, d0" + - + input: + bytes: [ 0x9a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "add d15, d0, #0" + - + input: + bytes: [ 0xc2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "add d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "add d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "add d0, d0, #0" + - + input: + bytes: [ 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "add.a a0, a0" + - + input: + bytes: [ 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "add.a a0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "add.a a0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "add.b d0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x21, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "add.f d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "add.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "addc d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "addc d0, d0, #0" + - + input: + bytes: [ 0x1b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "addi d0, d0, #0" + - + input: + bytes: [ 0x9b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "addih d0, d0, #0" + - + input: + bytes: [ 0x11, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "addih.a a0, a0, #0" + - + input: + bytes: [ 0x22, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "adds d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "adds d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "adds d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "adds.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "adds.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "adds.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "adds.u d0, d0, #0" + - + input: + bytes: [ 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "addsc.a a0, a0, d15, #0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "addsc.a a0, a0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "addsc.at a0, a0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "addx d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "addx d0, d0, #0" + - + input: + bytes: [ 0x26, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and d0, d0" + - + input: + bytes: [ 0x16, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and d15, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and d0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and.ne d0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "andn d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "andn d0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "bisr #0" + - + input: + bytes: [ 0xad, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "bisr #0" + - + input: + bytes: [ 0x4b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "bmerge d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "bsplit e0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cachea.i [a0+]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cachea.i [p0+r]" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cachea.i [+a0]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cachea.i [p0+c]#0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cachea.i [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cachea.w [a0+]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cachea.w [p0+r]" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cachea.w [+a0]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cachea.w [p0+c]#0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cachea.w [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cachea.wi [a0+]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cachea.wi [p0+r]" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cachea.wi [+a0]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cachea.wi [p0+c]#0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cachea.wi [a0]#0" + - + input: + bytes: [ 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cadd d0, d15, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cadd d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cadd d0, d0, d0, #0" + - + input: + bytes: [ 0xca, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "caddn d0, d15, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "caddn d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "caddn d0, d0, d0, #0" + - + input: + bytes: [ 0x5c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "call #0" + - + input: + bytes: [ 0x6d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "call #0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "calla #0" + - + input: + bytes: [ 0x2d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "calli a0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "clo d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "clo.h d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cls d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xe0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cls.h d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xb0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "clz d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "clz.h d0, d0" + - + input: + bytes: [ 0x2a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cmov d0, d15, d0" + - + input: + bytes: [ 0xaa, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cmov d0, d15, #0" + - + input: + bytes: [ 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cmovn d0, d15, d0" + - + input: + bytes: [ 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cmovn d0, d15, #0" + - + input: + bytes: [ 0x4b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "cmp.f d0, d0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "csub d0, d0, d0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "csubn d0, d0, d0, d0" + - + input: + bytes: [ 0x00, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "debug" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "debug" + - + input: + bytes: [ 0x77, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "dextr d0, d0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "dextr d0, d0, d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "disable" + - + input: + bytes: [ 0x4b, 0x00, 0x51, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "div.f d0, d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "dsync" + - + input: + bytes: [ 0x6b, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "dvadj e0, e0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "dvinit e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "dvinit.b e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "dvinit.bu e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "dvinit.h e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "dvinit.hu e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "dvinit.u e0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "dvstep e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "dvstep.u e0, e0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "enable" + - + input: + bytes: [ 0x3a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "eq d15, d0, d0" + - + input: + bytes: [ 0xba, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "eq d15, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "eq d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "eq.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "eq.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "eq.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "eq.w d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x60, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "eqany.b d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "eqany.b d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x60, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "eqany.h d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "eqany.h d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "eqz.a d0, a0" + - + input: + bytes: [ 0x17, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "extr d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "extr d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "extr d0, d0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, d0, #0" + - + input: + bytes: [ 0x4b, 0x00, 0x01, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ftoi d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x11, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ftoq31 d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x21, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ftou d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ge d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x30, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ge.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ge.u d0, d0, #0" + - + input: + bytes: [ 0x37, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "imask e0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "imask e0, d0, d0, #0" + - + input: + bytes: [ 0xb7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "imask e0, #0, #0, #0" + - + input: + bytes: [ 0xd7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "imask e0, #0, d0, #0" + - + input: + bytes: [ 0x67, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ins.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x97, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, e0" + - + input: + bytes: [ 0xb7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, #0, #0" + - + input: + bytes: [ 0xd7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x67, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "insn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "isync" + - + input: + bytes: [ 0x4b, 0x00, 0x41, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "itof d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ixmax e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ixmax.u e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ixmin e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ixmin.u e0, e0, d0" + - + input: + bytes: [ 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "j #0" + - + input: + bytes: [ 0x1d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "j #0" + - + input: + bytes: [ 0x9d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ja #0" + - + input: + bytes: [ 0x3e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0" + - + input: + bytes: [ 0x1e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jeq d15, #0, #0" + - + input: + bytes: [ 0x5f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jeq d0, d0, #0" + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jeq d0, #0, #0" + - + input: + bytes: [ 0x7d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jeq.a a0, a0, #0" + - + input: + bytes: [ 0x7f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jge d0, d0, #0" + - + input: + bytes: [ 0xff, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jge d0, #0, #0" + - + input: + bytes: [ 0x7f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jge.u d0, d0, #0" + - + input: + bytes: [ 0xff, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jge.u d0, #0, #0" + - + input: + bytes: [ 0xce, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jgez d0, #0" + - + input: + bytes: [ 0x4e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jgtz d0, #0" + - + input: + bytes: [ 0xdc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ji a0" + - + input: + bytes: [ 0x2d, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ji a0" + - + input: + bytes: [ 0x5d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jl #0" + - + input: + bytes: [ 0xdd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jla #0" + - + input: + bytes: [ 0x8e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jlez d0, #0" + - + input: + bytes: [ 0x2d, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jli a0" + - + input: + bytes: [ 0x3f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jlt d0, d0, #0" + - + input: + bytes: [ 0xbf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jlt d0, #0, #0" + - + input: + bytes: [ 0x3f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jlt.u d0, d0, #0" + - + input: + bytes: [ 0xbf, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jlt.u d0, #0, #0" + - + input: + bytes: [ 0x0e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jltz d0, #0" + - + input: + bytes: [ 0x7e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0" + - + input: + bytes: [ 0x5e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jne d15, #0, #0" + - + input: + bytes: [ 0x5f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jne d0, d0, #0" + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jne d0, #0, #0" + - + input: + bytes: [ 0x7d, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jne.a a0, a0, #0" + - + input: + bytes: [ 0x1f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jned d0, d0, #0" + - + input: + bytes: [ 0x9f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jned d0, #0, #0" + - + input: + bytes: [ 0x1f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jnei d0, d0, #0" + - + input: + bytes: [ 0x9f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jnei d0, #0, #0" + - + input: + bytes: [ 0xee, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jnz d15, #0" + - + input: + bytes: [ 0xf6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jnz d0, #0" + - + input: + bytes: [ 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jnz.a a0, #0" + - + input: + bytes: [ 0xbd, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jnz.a a0, #0" + - + input: + bytes: [ 0xae, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0, #0" + - + input: + bytes: [ 0x6f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jnz.t d0, #0, #0" + - + input: + bytes: [ 0x6e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jz d15, #0" + - + input: + bytes: [ 0x76, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jz d0, #0" + - + input: + bytes: [ 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jz.a a0, #0" + - + input: + bytes: [ 0xbd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jz.a a0, #0" + - + input: + bytes: [ 0x2e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #0" + - + input: + bytes: [ 0x6f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "jz.t d0, #0, #0" + - + input: + bytes: [ 0xd8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.a a15, [sp]#0" + - + input: + bytes: [ 0xc8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.a a0, [a15]#0" + - + input: + bytes: [ 0xcc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.a a15, [a0]#0" + - + input: + bytes: [ 0xc4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0+]" + - + input: + bytes: [ 0xd4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]" + - + input: + bytes: [ 0x99, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.a a0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.a a0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.a a0, [p0+c]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.a a0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.b d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.b d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.b d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.b d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.b d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.b d0, [a0]#0" + - + input: + bytes: [ 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0]" + - + input: + bytes: [ 0x0c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a0]#0" + - + input: + bytes: [ 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0" + - + input: + bytes: [ 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0+]" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.bu d0, [p0+r]" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.bu d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.bu d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.bu d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.d e0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.d e0, [p0+r]" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.d e0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.d e0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.d e0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.d e0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.da p0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.da p0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.da p0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.da p0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.da p0, [a0]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.da p0, #0" + - + input: + bytes: [ 0x84, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0+]" + - + input: + bytes: [ 0x8c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.h d15, [a0]#0" + - + input: + bytes: [ 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.h d0, [a15]#0" + - + input: + bytes: [ 0x94, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0]" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.h d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.h d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.h d0, [p0+c]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.h d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.hu d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.hu d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.hu d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a0]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.hu d0, #0" + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.q d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.q d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.q d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.q d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.q d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.q d0, [a0]#0" + - + input: + bytes: [ 0x58, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.w d15, [sp]#0" + - + input: + bytes: [ 0x54, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]" + - + input: + bytes: [ 0x44, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0+]" + - + input: + bytes: [ 0x4c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.w d15, [a0]#0" + - + input: + bytes: [ 0x48, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.w d0, [a15]#0" + - + input: + bytes: [ 0x19, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.w d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.w d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.w d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.w d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ldlcx #0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ldlcx [a0]#0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ldmst [a0+]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ldmst [p0+r], e0" + - + input: + bytes: [ 0xe5, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ldmst #0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ldmst [+a0]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ldmst [p0+c]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ldmst [a0]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "lducx [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "lducx #0" + - + input: + bytes: [ 0xc5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "lea a0, #0" + - + input: + bytes: [ 0xd9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "lea a0, [a0]#0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "lea a0, [a0]#0" + - + input: + bytes: [ 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "loop a0, #0xffffffe0" + - + input: + bytes: [ 0xfd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "loop a0, #0" + - + input: + bytes: [ 0xfd, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "loopu #0" + - + input: + bytes: [ 0x7a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "lt d15, d0, d0" + - + input: + bytes: [ 0xfa, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "lt d15, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "lt d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "lt.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "lt.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "lt.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "lt.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "lt.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "lt.w d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "lt.wu d0, d0, d0" + - + input: + bytes: [ 0x03, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd d0, d0, d0, #0" + - + input: + bytes: [ 0x13, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd e0, e0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x61, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd.f d0, d0, d0, d0" + - + input: + bytes: [ 0x83, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x13, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd.u e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madd.u e0, e0, d0, d0" + - + input: + bytes: [ 0x83, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddr.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddr.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x1c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddr.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddrs.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x98, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddrs.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x9c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddrs.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x03, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds d0, d0, d0, #0" + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds e0, e0, d0, d0" + - + input: + bytes: [ 0x83, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x84, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x94, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x13, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds.u d0, d0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds.u d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds.u e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "madds.u e0, e0, d0, d0" + - + input: + bytes: [ 0xc3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "max d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "max d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "max.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "max.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "max.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "max.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "max.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "max.u d0, d0, #0" + - + input: + bytes: [ 0x4d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mfcr d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "min d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "min d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "min.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "min.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "min.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "min.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "min.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "min.u d0, d0, #0" + - + input: + bytes: [ 0x02, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mov d0, d0" + - + input: + bytes: [ 0x82, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mov d0, #0" + - + input: + bytes: [ 0xda, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mov d15, #0" + - + input: + bytes: [ 0x3b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mov d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mov d0, d0" + - + input: + bytes: [ 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mov.a a0, #0" + - + input: + bytes: [ 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mov.a a0, d0" + - + input: + bytes: [ 0x01, 0x00, 0x30, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mov.a a0, d0" + - + input: + bytes: [ 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mov.aa a0, a0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mov.aa a0, a0" + - + input: + bytes: [ 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mov.d d0, a0" + - + input: + bytes: [ 0x01, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mov.d d0, a0" + - + input: + bytes: [ 0xbb, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mov.u d0, #0" + - + input: + bytes: [ 0x7b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "movh d0, #0" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "movh.a a0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub d0, d0, d0, #0" + - + input: + bytes: [ 0x33, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub e0, e0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x71, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub.f d0, d0, d0, d0" + - + input: + bytes: [ 0xa3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x33, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub.u e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msub.u e0, e0, d0, d0" + - + input: + bytes: [ 0xe3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubr.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubr.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x1c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubr.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubrs.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x98, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubrs.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x9c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubrs.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x23, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs d0, d0, d0, #0" + - + input: + bytes: [ 0x33, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs e0, e0, d0, d0" + - + input: + bytes: [ 0xa3, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x84, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x94, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x33, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs.u d0, d0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs.u d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs.u e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "msubs.u e0, e0, d0, d0" + - + input: + bytes: [ 0xcd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mtcr #0, d0" + - + input: + bytes: [ 0xe2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul d0, d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul e0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x41, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul.f d0, d0, d0" + - + input: + bytes: [ 0xb3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0uu, #0" + - + input: + bytes: [ 0x93, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul.q d0, d0, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul.q d0, d0, d0l, #0" + - + input: + bytes: [ 0x93, 0x00, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul.q d0, d0, d0, #0" + - + input: + bytes: [ 0x93, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul.q d0, d0u, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul.q d0, d0l, d0l, #0" + - + input: + bytes: [ 0x93, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul.q e0, d0, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul.q e0, d0, d0l, #0" + - + input: + bytes: [ 0x93, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul.q e0, d0, d0, #0" + - + input: + bytes: [ 0x53, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul.u e0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mul.u e0, d0, d0" + - + input: + bytes: [ 0xb3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0uu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0uu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0uu, #0" + - + input: + bytes: [ 0x93, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mulr.q d0, d0u, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x1c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "mulr.q d0, d0l, d0l, #0" + - + input: + bytes: [ 0x53, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "muls d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "muls d0, d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "muls.u d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "muls.u d0, d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "nand d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "nand d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "nand.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ne d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ne.a d0, a0, a0" + - + input: + bytes: [ 0x01, 0x00, 0x90, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "nez.a d0, a0" + - + input: + bytes: [ 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x46, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "nor d0" + - + input: + bytes: [ 0x0f, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "nor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x60, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "nor d0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or d0, d0" + - + input: + bytes: [ 0x96, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or d15, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or d0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x70, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or.ne d0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "orn d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xe0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "orn d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "orn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x6b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "pack d0, e0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "parity d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x51, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "q31tof d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x91, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "qseed.f d0, d0" + - + input: + bytes: [ 0x00, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ret" + - + input: + bytes: [ 0x0d, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "ret" + - + input: + bytes: [ 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "rfe" + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "rfe" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "rfm" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "rslcx" + - + input: + bytes: [ 0x2f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "rstv" + - + input: + bytes: [ 0x32, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "rsub d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "rsub d0, d0, #0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "rsubs d0, d0, #0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "rsubs.u d0, d0, #0" + - + input: + bytes: [ 0x32, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sat.b d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sat.b d0, d0" + - + input: + bytes: [ 0x32, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sat.bu d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sat.bu d0, d0" + - + input: + bytes: [ 0x32, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sat.h d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sat.h d0, d0" + - + input: + bytes: [ 0x32, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sat.hu d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sat.hu d0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sel d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sel d0, d0, d0, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "seln d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "seln d0, d0, d0, #0" + - + input: + bytes: [ 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh d0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x70, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.h d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.h d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.lt.u d0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.nand.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.ne d0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.orn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.xnor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sh.xor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x86, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sha d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sha d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sha d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sha.h d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sha.h d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "shas d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "shas d0, d0, #0" + - + input: + bytes: [ 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.a [sp]#0, a15" + - + input: + bytes: [ 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.a [a0]#0, a15" + - + input: + bytes: [ 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.a [a15]#0, a0" + - + input: + bytes: [ 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.a [a0+], a0" + - + input: + bytes: [ 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.a [a0], a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.a [a0+]#0, a0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.a [p0+r], a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.a [+a0]#0, a0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.a [p0+c]#0, a0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.a #0, a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.a [a0]#0, a0" + - + input: + bytes: [ 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.b [a0], d0" + - + input: + bytes: [ 0x28, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.b [a15]#0, d0" + - + input: + bytes: [ 0x2c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.b [a0]#0, d15" + - + input: + bytes: [ 0x24, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.b [a0+], d0" + - + input: + bytes: [ 0x25, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.b #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.b [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.b [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.b [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.b [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.b [a0]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.d [a0+]#0, e0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.d [p0+r], e0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.d #0, e0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.d [+a0]#0, e0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.d [p0+c]#0, e0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.d [a0]#0, e0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.da [a0+]#0, p0" + - + input: + bytes: [ 0xa9, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.da [p0+r], p0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.da [+a0]#0, p0" + - + input: + bytes: [ 0xa9, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.da [p0+c]#0, p0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.da [a0]#0, p0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.da #0, p0" + - + input: + bytes: [ 0xa4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.h [a0+], d0" + - + input: + bytes: [ 0xa8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.h [a15]#0, d0" + - + input: + bytes: [ 0xac, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.h [a0]#0, d15" + - + input: + bytes: [ 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.h [a0], d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.h [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.h [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.h [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.h [p0+c]#0, d0" + - + input: + bytes: [ 0x25, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.h #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.h [a0]#0, d0" + - + input: + bytes: [ 0x65, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.q #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.q [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.q [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.q [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.q [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.q [a0]#0, d0" + - + input: + bytes: [ 0xd5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.t #0, #0, #0" + - + input: + bytes: [ 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.w [sp]#0, d15" + - + input: + bytes: [ 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.w [a0], d0" + - + input: + bytes: [ 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.w [a0+], d0" + - + input: + bytes: [ 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.w [a15]#0, d0" + - + input: + bytes: [ 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d15" + - + input: + bytes: [ 0x59, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.w #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.w [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.w [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.w [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.w [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "stlcx #0" + - + input: + bytes: [ 0x49, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "stlcx [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "stucx #0" + - + input: + bytes: [ 0x49, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "stucx [a0]#0" + - + input: + bytes: [ 0x52, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sub d0, d15, d0" + - + input: + bytes: [ 0x5a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sub d15, d0, d0" + - + input: + bytes: [ 0xa2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sub d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sub d0, d0, d0" + - + input: + bytes: [ 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sub.a sp, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sub.a a0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sub.b d0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x31, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sub.f d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "sub.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "subc d0, d0, d0" + - + input: + bytes: [ 0x62, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "subs d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "subs d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "subs.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "subs.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "subs.u d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "subx d0, d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "svlcx" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "swap.w [a0+]#0, d0" + - + input: + bytes: [ 0x69, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "swap.w [p0+r], d0" + - + input: + bytes: [ 0xe5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "swap.w #0, d0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "swap.w [+a0]#0, d0" + - + input: + bytes: [ 0x69, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "swap.w [p0+c]#0, d0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "swap.w [a0]#0, d0" + - + input: + bytes: [ 0xad, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "syscall #0" + - + input: + bytes: [ 0x75, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "tlbdemap d0" + - + input: + bytes: [ 0x75, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "tlbflush.a" + - + input: + bytes: [ 0x75, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "tlbflush.b" + - + input: + bytes: [ 0x75, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "tlbmap e0" + - + input: + bytes: [ 0x75, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "tlbprobe.a d0" + - + input: + bytes: [ 0x75, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "tlbprobe.i d0" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "trapsv" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "trapv" + - + input: + bytes: [ 0x4b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "unpack e0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xc1, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "updfl d0" + - + input: + bytes: [ 0x4b, 0x00, 0x61, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "utof d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "xnor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "xnor d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "xnor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "xor d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "xor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "xor d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "xor.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "xor.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "xor.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "xor.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "xor.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "xor.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "xor.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "xor.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "xor.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "xor.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "xor.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "xor.ne d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_130" ] + expected: + insns: + - + asm_text: "xor.t d0, d0, #0, d0, #0" diff --git a/tests/MC/TriCore/tc131.s.yaml b/tests/MC/TriCore/tc131.s.yaml new file mode 100644 index 0000000000..72485a82d8 --- /dev/null +++ b/tests/MC/TriCore/tc131.s.yaml @@ -0,0 +1,7147 @@ +test_cases: + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "abs d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "abs.b d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "abs.h d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "absdif d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "absdif d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "absdif.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "absdif.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "absdifs d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "absdifs d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "absdifs.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "abss d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "abss.h d0, d0" + - + input: + bytes: [ 0x12, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "add d0, d15, d0" + - + input: + bytes: [ 0x92, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "add d0, d15, #0" + - + input: + bytes: [ 0x1a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "add d15, d0, d0" + - + input: + bytes: [ 0x42, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "add d0, d0" + - + input: + bytes: [ 0x9a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "add d15, d0, #0" + - + input: + bytes: [ 0xc2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "add d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "add d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "add d0, d0, #0" + - + input: + bytes: [ 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "add.a a0, a0" + - + input: + bytes: [ 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "add.a a0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "add.a a0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "add.b d0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x21, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "add.f d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "add.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "addc d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "addc d0, d0, #0" + - + input: + bytes: [ 0x1b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "addi d0, d0, #0" + - + input: + bytes: [ 0x9b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "addih d0, d0, #0" + - + input: + bytes: [ 0x11, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "addih.a a0, a0, #0" + - + input: + bytes: [ 0x22, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "adds d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "adds d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "adds d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "adds.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "adds.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "adds.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "adds.u d0, d0, #0" + - + input: + bytes: [ 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "addsc.a a0, a0, d15, #0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "addsc.a a0, a0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "addsc.at a0, a0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "addx d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "addx d0, d0, #0" + - + input: + bytes: [ 0x26, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and d0, d0" + - + input: + bytes: [ 0x16, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and d15, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and d0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and.ne d0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "andn d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "andn d0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "bisr #0" + - + input: + bytes: [ 0xad, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "bisr #0" + - + input: + bytes: [ 0x4b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "bmerge d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "bsplit e0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachea.i [a0+]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachea.i [p0+r]" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachea.i [+a0]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachea.i [p0+c]#0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachea.i [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachea.w [a0+]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachea.w [p0+r]" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachea.w [+a0]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachea.w [p0+c]#0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachea.w [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachea.wi [a0+]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachea.wi [p0+r]" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachea.wi [+a0]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachea.wi [p0+c]#0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachea.wi [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachei.w [a0+]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachei.w [+a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachei.w [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachei.wi [a0+]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachei.wi [+a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cachei.wi [a0]#0" + - + input: + bytes: [ 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cadd d0, d15, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cadd d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cadd d0, d0, d0, #0" + - + input: + bytes: [ 0xca, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "caddn d0, d15, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "caddn d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "caddn d0, d0, d0, #0" + - + input: + bytes: [ 0x5c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "call #0" + - + input: + bytes: [ 0x6d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "call #0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "calla #0" + - + input: + bytes: [ 0x2d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "calli a0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "clo d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "clo.h d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cls d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xe0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cls.h d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xb0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "clz d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "clz.h d0, d0" + - + input: + bytes: [ 0x2a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cmov d0, d15, d0" + - + input: + bytes: [ 0xaa, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cmov d0, d15, #0" + - + input: + bytes: [ 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cmovn d0, d15, d0" + - + input: + bytes: [ 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cmovn d0, d15, #0" + - + input: + bytes: [ 0x4b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "cmp.f d0, d0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "csub d0, d0, d0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "csubn d0, d0, d0, d0" + - + input: + bytes: [ 0x00, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "debug" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "debug" + - + input: + bytes: [ 0x77, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "dextr d0, d0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "dextr d0, d0, d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "disable" + - + input: + bytes: [ 0x4b, 0x00, 0x51, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "div.f d0, d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "dsync" + - + input: + bytes: [ 0x6b, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "dvadj e0, e0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "dvinit e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "dvinit.b e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "dvinit.bu e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "dvinit.h e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "dvinit.hu e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "dvinit.u e0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "dvstep e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "dvstep.u e0, e0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "enable" + - + input: + bytes: [ 0x3a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "eq d15, d0, d0" + - + input: + bytes: [ 0xba, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "eq d15, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "eq d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "eq.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "eq.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "eq.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "eq.w d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x60, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "eqany.b d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "eqany.b d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x60, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "eqany.h d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "eqany.h d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "eqz.a d0, a0" + - + input: + bytes: [ 0x17, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "extr d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "extr d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "extr d0, d0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, d0, #0" + - + input: + bytes: [ 0x4b, 0x00, 0x01, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ftoi d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x11, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ftoq31 d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x21, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ftou d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x31, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ftoiz d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x81, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ftoq31z d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x71, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ftouz d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ge d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x30, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ge.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ge.u d0, d0, #0" + - + input: + bytes: [ 0x37, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "imask e0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "imask e0, d0, d0, #0" + - + input: + bytes: [ 0xb7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "imask e0, #0, #0, #0" + - + input: + bytes: [ 0xd7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "imask e0, #0, d0, #0" + - + input: + bytes: [ 0x67, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ins.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x97, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, e0" + - + input: + bytes: [ 0xb7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, #0, #0" + - + input: + bytes: [ 0xd7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x67, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "insn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "isync" + - + input: + bytes: [ 0x4b, 0x00, 0x41, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "itof d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ixmax e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ixmax.u e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ixmin e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ixmin.u e0, e0, d0" + - + input: + bytes: [ 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "j #0" + - + input: + bytes: [ 0x1d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "j #0" + - + input: + bytes: [ 0x9d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ja #0" + - + input: + bytes: [ 0x3e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0" + - + input: + bytes: [ 0x1e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jeq d15, #0, #0" + - + input: + bytes: [ 0x5f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jeq d0, d0, #0" + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jeq d0, #0, #0" + - + input: + bytes: [ 0x7d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jeq.a a0, a0, #0" + - + input: + bytes: [ 0x7f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jge d0, d0, #0" + - + input: + bytes: [ 0xff, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jge d0, #0, #0" + - + input: + bytes: [ 0x7f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jge.u d0, d0, #0" + - + input: + bytes: [ 0xff, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jge.u d0, #0, #0" + - + input: + bytes: [ 0xce, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jgez d0, #0" + - + input: + bytes: [ 0x4e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jgtz d0, #0" + - + input: + bytes: [ 0xdc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ji a0" + - + input: + bytes: [ 0x2d, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ji a0" + - + input: + bytes: [ 0x5d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jl #0" + - + input: + bytes: [ 0xdd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jla #0" + - + input: + bytes: [ 0x8e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jlez d0, #0" + - + input: + bytes: [ 0x2d, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jli a0" + - + input: + bytes: [ 0x3f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jlt d0, d0, #0" + - + input: + bytes: [ 0xbf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jlt d0, #0, #0" + - + input: + bytes: [ 0x3f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jlt.u d0, d0, #0" + - + input: + bytes: [ 0xbf, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jlt.u d0, #0, #0" + - + input: + bytes: [ 0x0e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jltz d0, #0" + - + input: + bytes: [ 0x7e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0" + - + input: + bytes: [ 0x5e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jne d15, #0, #0" + - + input: + bytes: [ 0x5f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jne d0, d0, #0" + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jne d0, #0, #0" + - + input: + bytes: [ 0x7d, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jne.a a0, a0, #0" + - + input: + bytes: [ 0x1f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jned d0, d0, #0" + - + input: + bytes: [ 0x9f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jned d0, #0, #0" + - + input: + bytes: [ 0x1f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jnei d0, d0, #0" + - + input: + bytes: [ 0x9f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jnei d0, #0, #0" + - + input: + bytes: [ 0xee, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jnz d15, #0" + - + input: + bytes: [ 0xf6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jnz d0, #0" + - + input: + bytes: [ 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jnz.a a0, #0" + - + input: + bytes: [ 0xbd, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jnz.a a0, #0" + - + input: + bytes: [ 0xae, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0, #0" + - + input: + bytes: [ 0x6f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jnz.t d0, #0, #0" + - + input: + bytes: [ 0x6e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jz d15, #0" + - + input: + bytes: [ 0x76, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jz d0, #0" + - + input: + bytes: [ 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jz.a a0, #0" + - + input: + bytes: [ 0xbd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jz.a a0, #0" + - + input: + bytes: [ 0x2e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #0" + - + input: + bytes: [ 0x6f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "jz.t d0, #0, #0" + - + input: + bytes: [ 0xd8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.a a15, [sp]#0" + - + input: + bytes: [ 0xc8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.a a0, [a15]#0" + - + input: + bytes: [ 0xcc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.a a15, [a0]#0" + - + input: + bytes: [ 0xc4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0+]" + - + input: + bytes: [ 0xd4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]" + - + input: + bytes: [ 0x99, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.a a0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.a a0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.a a0, [p0+c]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.a a0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.b d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.b d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.b d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.b d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.b d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.b d0, [a0]#0" + - + input: + bytes: [ 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0]" + - + input: + bytes: [ 0x0c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a0]#0" + - + input: + bytes: [ 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0" + - + input: + bytes: [ 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0+]" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.bu d0, [p0+r]" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.bu d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.bu d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.bu d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.d e0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.d e0, [p0+r]" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.d e0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.d e0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.d e0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.d e0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.da p0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.da p0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.da p0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.da p0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.da p0, [a0]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.da p0, #0" + - + input: + bytes: [ 0x84, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0+]" + - + input: + bytes: [ 0x8c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.h d15, [a0]#0" + - + input: + bytes: [ 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.h d0, [a15]#0" + - + input: + bytes: [ 0x94, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0]" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.h d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.h d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.h d0, [p0+c]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.h d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.hu d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.hu d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.hu d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a0]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.hu d0, #0" + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.q d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.q d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.q d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.q d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.q d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.q d0, [a0]#0" + - + input: + bytes: [ 0x58, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.w d15, [sp]#0" + - + input: + bytes: [ 0x54, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]" + - + input: + bytes: [ 0x44, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0+]" + - + input: + bytes: [ 0x4c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.w d15, [a0]#0" + - + input: + bytes: [ 0x48, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.w d0, [a15]#0" + - + input: + bytes: [ 0x19, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.w d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.w d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.w d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.w d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ldlcx #0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ldlcx [a0]#0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ldmst [a0+]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ldmst [p0+r], e0" + - + input: + bytes: [ 0xe5, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ldmst #0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ldmst [+a0]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ldmst [p0+c]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ldmst [a0]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "lducx [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "lducx #0" + - + input: + bytes: [ 0xc5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "lea a0, #0" + - + input: + bytes: [ 0xd9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "lea a0, [a0]#0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "lea a0, [a0]#0" + - + input: + bytes: [ 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "loop a0, #0xffffffe0" + - + input: + bytes: [ 0xfd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "loop a0, #0" + - + input: + bytes: [ 0xfd, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "loopu #0" + - + input: + bytes: [ 0x7a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "lt d15, d0, d0" + - + input: + bytes: [ 0xfa, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "lt d15, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "lt d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "lt.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "lt.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "lt.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "lt.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "lt.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "lt.w d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "lt.wu d0, d0, d0" + - + input: + bytes: [ 0x03, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd d0, d0, d0, #0" + - + input: + bytes: [ 0x13, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd e0, e0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x61, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd.f d0, d0, d0, d0" + - + input: + bytes: [ 0x83, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x13, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd.u e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madd.u e0, e0, d0, d0" + - + input: + bytes: [ 0x83, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddr.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddr.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x1c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddr.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddrs.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x98, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddrs.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x9c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddrs.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x03, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds d0, d0, d0, #0" + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds e0, e0, d0, d0" + - + input: + bytes: [ 0x83, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x84, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x94, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x13, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds.u d0, d0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds.u d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds.u e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "madds.u e0, e0, d0, d0" + - + input: + bytes: [ 0xc3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "max d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "max d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "max.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "max.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "max.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "max.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "max.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "max.u d0, d0, #0" + - + input: + bytes: [ 0x4d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mfcr d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "min d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "min d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "min.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "min.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "min.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "min.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "min.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "min.u d0, d0, #0" + - + input: + bytes: [ 0x02, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mov d0, d0" + - + input: + bytes: [ 0x82, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mov d0, #0" + - + input: + bytes: [ 0xda, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mov d15, #0" + - + input: + bytes: [ 0x3b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mov d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mov d0, d0" + - + input: + bytes: [ 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mov.a a0, #0" + - + input: + bytes: [ 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mov.a a0, d0" + - + input: + bytes: [ 0x01, 0x00, 0x30, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mov.a a0, d0" + - + input: + bytes: [ 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mov.aa a0, a0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mov.aa a0, a0" + - + input: + bytes: [ 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mov.d d0, a0" + - + input: + bytes: [ 0x01, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mov.d d0, a0" + - + input: + bytes: [ 0xbb, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mov.u d0, #0" + - + input: + bytes: [ 0x7b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "movh d0, #0" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "movh.a a0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub d0, d0, d0, #0" + - + input: + bytes: [ 0x33, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub e0, e0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x71, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub.f d0, d0, d0, d0" + - + input: + bytes: [ 0xa3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x33, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub.u e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msub.u e0, e0, d0, d0" + - + input: + bytes: [ 0xe3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubr.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubr.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x1c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubr.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubrs.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x98, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubrs.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x9c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubrs.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x23, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs d0, d0, d0, #0" + - + input: + bytes: [ 0x33, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs e0, e0, d0, d0" + - + input: + bytes: [ 0xa3, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x84, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x94, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x33, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs.u d0, d0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs.u d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs.u e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "msubs.u e0, e0, d0, d0" + - + input: + bytes: [ 0xcd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mtcr #0, d0" + - + input: + bytes: [ 0xe2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul d0, d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul e0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x41, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul.f d0, d0, d0" + - + input: + bytes: [ 0xb3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0uu, #0" + - + input: + bytes: [ 0x93, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul.q d0, d0, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul.q d0, d0, d0l, #0" + - + input: + bytes: [ 0x93, 0x00, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul.q d0, d0, d0, #0" + - + input: + bytes: [ 0x93, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul.q d0, d0u, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul.q d0, d0l, d0l, #0" + - + input: + bytes: [ 0x93, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul.q e0, d0, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul.q e0, d0, d0l, #0" + - + input: + bytes: [ 0x93, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul.q e0, d0, d0, #0" + - + input: + bytes: [ 0x53, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul.u e0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mul.u e0, d0, d0" + - + input: + bytes: [ 0xb3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0uu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0uu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0uu, #0" + - + input: + bytes: [ 0x93, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mulr.q d0, d0u, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x1c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "mulr.q d0, d0l, d0l, #0" + - + input: + bytes: [ 0x53, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "muls d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "muls d0, d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "muls.u d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "muls.u d0, d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "nand d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "nand d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "nand.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ne d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ne.a d0, a0, a0" + - + input: + bytes: [ 0x01, 0x00, 0x90, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "nez.a d0, a0" + - + input: + bytes: [ 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x46, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "nor d0" + - + input: + bytes: [ 0x0f, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "nor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x60, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "nor d0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or d0, d0" + - + input: + bytes: [ 0x96, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or d15, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or d0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x70, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or.ne d0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "orn d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xe0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "orn d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "orn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x6b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "pack d0, e0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "parity d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x51, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "q31tof d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x91, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "qseed.f d0, d0" + - + input: + bytes: [ 0x00, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ret" + - + input: + bytes: [ 0x0d, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "ret" + - + input: + bytes: [ 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "rfe" + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "rfe" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "rfm" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "rslcx" + - + input: + bytes: [ 0x2f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "rstv" + - + input: + bytes: [ 0x32, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "rsub d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "rsub d0, d0, #0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "rsubs d0, d0, #0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "rsubs.u d0, d0, #0" + - + input: + bytes: [ 0x32, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sat.b d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sat.b d0, d0" + - + input: + bytes: [ 0x32, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sat.bu d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sat.bu d0, d0" + - + input: + bytes: [ 0x32, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sat.h d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sat.h d0, d0" + - + input: + bytes: [ 0x32, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sat.hu d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sat.hu d0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sel d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sel d0, d0, d0, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "seln d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "seln d0, d0, d0, #0" + - + input: + bytes: [ 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh d0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x70, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.h d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.h d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.lt.u d0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.nand.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.ne d0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.orn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.xnor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sh.xor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x86, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sha d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sha d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sha d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sha.h d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sha.h d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "shas d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "shas d0, d0, #0" + - + input: + bytes: [ 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.a [sp]#0, a15" + - + input: + bytes: [ 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.a [a0]#0, a15" + - + input: + bytes: [ 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.a [a15]#0, a0" + - + input: + bytes: [ 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.a [a0+], a0" + - + input: + bytes: [ 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.a [a0], a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.a [a0+]#0, a0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.a [p0+r], a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.a [+a0]#0, a0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.a [p0+c]#0, a0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.a #0, a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.a [a0]#0, a0" + - + input: + bytes: [ 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.b [a0], d0" + - + input: + bytes: [ 0x28, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.b [a15]#0, d0" + - + input: + bytes: [ 0x2c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.b [a0]#0, d15" + - + input: + bytes: [ 0x24, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.b [a0+], d0" + - + input: + bytes: [ 0x25, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.b #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.b [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.b [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.b [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.b [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.b [a0]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.d [a0+]#0, e0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.d [p0+r], e0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.d #0, e0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.d [+a0]#0, e0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.d [p0+c]#0, e0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.d [a0]#0, e0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.da [a0+]#0, p0" + - + input: + bytes: [ 0xa9, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.da [p0+r], p0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.da [+a0]#0, p0" + - + input: + bytes: [ 0xa9, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.da [p0+c]#0, p0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.da [a0]#0, p0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.da #0, p0" + - + input: + bytes: [ 0xa4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.h [a0+], d0" + - + input: + bytes: [ 0xa8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.h [a15]#0, d0" + - + input: + bytes: [ 0xac, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.h [a0]#0, d15" + - + input: + bytes: [ 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.h [a0], d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.h [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.h [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.h [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.h [p0+c]#0, d0" + - + input: + bytes: [ 0x25, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.h #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.h [a0]#0, d0" + - + input: + bytes: [ 0x65, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.q #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.q [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.q [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.q [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.q [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.q [a0]#0, d0" + - + input: + bytes: [ 0xd5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.t #0, #0, #0" + - + input: + bytes: [ 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.w [sp]#0, d15" + - + input: + bytes: [ 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.w [a0], d0" + - + input: + bytes: [ 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.w [a0+], d0" + - + input: + bytes: [ 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.w [a15]#0, d0" + - + input: + bytes: [ 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d15" + - + input: + bytes: [ 0x59, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.w #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.w [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.w [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.w [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.w [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "stlcx #0" + - + input: + bytes: [ 0x49, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "stlcx [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "stucx #0" + - + input: + bytes: [ 0x49, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "stucx [a0]#0" + - + input: + bytes: [ 0x52, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sub d0, d15, d0" + - + input: + bytes: [ 0x5a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sub d15, d0, d0" + - + input: + bytes: [ 0xa2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sub d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sub d0, d0, d0" + - + input: + bytes: [ 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sub.a sp, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sub.a a0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sub.b d0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x31, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sub.f d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "sub.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "subc d0, d0, d0" + - + input: + bytes: [ 0x62, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "subs d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "subs d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "subs.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "subs.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "subs.u d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "subx d0, d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "svlcx" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "swap.w [a0+]#0, d0" + - + input: + bytes: [ 0x69, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "swap.w [p0+r], d0" + - + input: + bytes: [ 0xe5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "swap.w #0, d0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "swap.w [+a0]#0, d0" + - + input: + bytes: [ 0x69, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "swap.w [p0+c]#0, d0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "swap.w [a0]#0, d0" + - + input: + bytes: [ 0xad, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "syscall #0" + - + input: + bytes: [ 0x75, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "tlbdemap d0" + - + input: + bytes: [ 0x75, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "tlbflush.a" + - + input: + bytes: [ 0x75, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "tlbflush.b" + - + input: + bytes: [ 0x75, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "tlbmap e0" + - + input: + bytes: [ 0x75, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "tlbprobe.a d0" + - + input: + bytes: [ 0x75, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "tlbprobe.i d0" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "trapsv" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "trapv" + - + input: + bytes: [ 0x4b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "unpack e0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xc1, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "updfl d0" + - + input: + bytes: [ 0x4b, 0x00, 0x61, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "utof d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "xnor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "xnor d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "xnor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "xor d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "xor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "xor d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "xor.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "xor.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "xor.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "xor.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "xor.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "xor.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "xor.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "xor.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "xor.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "xor.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "xor.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "xor.ne d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_131" ] + expected: + insns: + - + asm_text: "xor.t d0, d0, #0, d0, #0" diff --git a/tests/MC/TriCore/tc160.s.yaml b/tests/MC/TriCore/tc160.s.yaml new file mode 100644 index 0000000000..9f77d604a4 --- /dev/null +++ b/tests/MC/TriCore/tc160.s.yaml @@ -0,0 +1,7399 @@ +test_cases: + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "abs d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "abs.b d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "abs.h d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "absdif d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "absdif d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "absdif.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "absdif.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "absdifs d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "absdifs d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "absdifs.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "abss d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "abss.h d0, d0" + - + input: + bytes: [ 0x12, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "add d0, d15, d0" + - + input: + bytes: [ 0x92, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "add d0, d15, #0" + - + input: + bytes: [ 0x1a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "add d15, d0, d0" + - + input: + bytes: [ 0x42, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "add d0, d0" + - + input: + bytes: [ 0x9a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "add d15, d0, #0" + - + input: + bytes: [ 0xc2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "add d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "add d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "add d0, d0, #0" + - + input: + bytes: [ 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "add.a a0, a0" + - + input: + bytes: [ 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "add.a a0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "add.a a0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "add.b d0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x21, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "add.f d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "add.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "addc d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "addc d0, d0, #0" + - + input: + bytes: [ 0x1b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "addi d0, d0, #0" + - + input: + bytes: [ 0x9b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "addih d0, d0, #0" + - + input: + bytes: [ 0x11, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "addih.a a0, a0, #0" + - + input: + bytes: [ 0x22, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "adds d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "adds d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "adds d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "adds.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "adds.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "adds.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "adds.u d0, d0, #0" + - + input: + bytes: [ 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "addsc.a a0, a0, d15, #0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "addsc.a a0, a0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "addsc.at a0, a0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "addx d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "addx d0, d0, #0" + - + input: + bytes: [ 0x26, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and d0, d0" + - + input: + bytes: [ 0x16, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and d15, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and d0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and.ne d0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "andn d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "andn d0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "bisr #0" + - + input: + bytes: [ 0xad, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "bisr #0" + - + input: + bytes: [ 0x4b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "bmerge d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "bsplit e0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachea.i [a0+]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachea.i [p0+r]" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachea.i [+a0]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachea.i [p0+c]#0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachea.i [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachea.w [a0+]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachea.w [p0+r]" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachea.w [+a0]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachea.w [p0+c]#0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachea.w [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachea.wi [a0+]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachea.wi [p0+r]" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachea.wi [+a0]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachea.wi [p0+c]#0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachea.wi [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachei.i [a0+]#0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachei.i [+a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachei.i [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachei.w [a0+]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachei.w [+a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachei.w [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachei.wi [a0+]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachei.wi [+a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cachei.wi [a0]#0" + - + input: + bytes: [ 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cadd d0, d15, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cadd d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cadd d0, d0, d0, #0" + - + input: + bytes: [ 0xca, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "caddn d0, d15, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "caddn d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "caddn d0, d0, d0, #0" + - + input: + bytes: [ 0x5c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "call #0" + - + input: + bytes: [ 0x6d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "call #0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "calla #0" + - + input: + bytes: [ 0x2d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "calli a0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "clo d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "clo.h d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cls d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xe0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cls.h d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xb0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "clz d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "clz.h d0, d0" + - + input: + bytes: [ 0x2a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cmov d0, d15, d0" + - + input: + bytes: [ 0xaa, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cmov d0, d15, #0" + - + input: + bytes: [ 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cmovn d0, d15, d0" + - + input: + bytes: [ 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cmovn d0, d15, #0" + - + input: + bytes: [ 0x4b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "cmp.f d0, d0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "csub d0, d0, d0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "csubn d0, d0, d0, d0" + - + input: + bytes: [ 0x00, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "debug" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "debug" + - + input: + bytes: [ 0x77, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "dextr d0, d0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "dextr d0, d0, d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "disable" + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "disable d0" + - + input: + bytes: [ 0x4b, 0x00, 0x01, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "div e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x11, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "div.u e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x51, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "div.f d0, d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "dsync" + - + input: + bytes: [ 0x6b, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "dvadj e0, e0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "dvinit e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "dvinit.b e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "dvinit.bu e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "dvinit.h e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "dvinit.hu e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "dvinit.u e0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "dvstep e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "dvstep.u e0, e0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "enable" + - + input: + bytes: [ 0x3a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "eq d15, d0, d0" + - + input: + bytes: [ 0xba, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "eq d15, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "eq d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "eq.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "eq.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "eq.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "eq.w d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x60, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "eqany.b d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "eqany.b d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x60, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "eqany.h d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "eqany.h d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "eqz.a d0, a0" + - + input: + bytes: [ 0x17, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "extr d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "extr d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "extr d0, d0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, d0, #0" + - + input: + bytes: [ 0x61, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "fcall #0" + - + input: + bytes: [ 0xe1, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "fcalla #0" + - + input: + bytes: [ 0x2d, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "fcalli a0" + - + input: + bytes: [ 0x00, 0x70 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "fret" + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "fret" + - + input: + bytes: [ 0x4b, 0x00, 0x01, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ftoi d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x11, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ftoq31 d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x21, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ftou d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x31, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ftoiz d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x81, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ftoq31z d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x71, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ftouz d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ge d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x30, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ge.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ge.u d0, d0, #0" + - + input: + bytes: [ 0x37, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "imask e0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "imask e0, d0, d0, #0" + - + input: + bytes: [ 0xb7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "imask e0, #0, #0, #0" + - + input: + bytes: [ 0xd7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "imask e0, #0, d0, #0" + - + input: + bytes: [ 0x67, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ins.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x97, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, e0" + - + input: + bytes: [ 0xb7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, #0, #0" + - + input: + bytes: [ 0xd7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x67, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "insn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "isync" + - + input: + bytes: [ 0x4b, 0x00, 0x41, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "itof d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ixmax e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ixmax.u e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ixmin e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ixmin.u e0, e0, d0" + - + input: + bytes: [ 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "j #0" + - + input: + bytes: [ 0x1d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "j #0" + - + input: + bytes: [ 0x9d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ja #0" + - + input: + bytes: [ 0xbe, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x20" + - + input: + bytes: [ 0x9e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jeq d15, #0, #0x20" + - + input: + bytes: [ 0x3e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0" + - + input: + bytes: [ 0x1e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jeq d15, #0, #0" + - + input: + bytes: [ 0x5f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jeq d0, d0, #0" + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jeq d0, #0, #0" + - + input: + bytes: [ 0x7d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jeq.a a0, a0, #0" + - + input: + bytes: [ 0x7f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jge d0, d0, #0" + - + input: + bytes: [ 0xff, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jge d0, #0, #0" + - + input: + bytes: [ 0x7f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jge.u d0, d0, #0" + - + input: + bytes: [ 0xff, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jge.u d0, #0, #0" + - + input: + bytes: [ 0xce, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jgez d0, #0" + - + input: + bytes: [ 0x4e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jgtz d0, #0" + - + input: + bytes: [ 0xdc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ji a0" + - + input: + bytes: [ 0x2d, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ji a0" + - + input: + bytes: [ 0x5d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jl #0" + - + input: + bytes: [ 0xdd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jla #0" + - + input: + bytes: [ 0x8e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jlez d0, #0" + - + input: + bytes: [ 0x2d, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jli a0" + - + input: + bytes: [ 0x3f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jlt d0, d0, #0" + - + input: + bytes: [ 0xbf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jlt d0, #0, #0" + - + input: + bytes: [ 0x3f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jlt.u d0, d0, #0" + - + input: + bytes: [ 0xbf, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jlt.u d0, #0, #0" + - + input: + bytes: [ 0x0e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jltz d0, #0" + - + input: + bytes: [ 0xfe, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x20" + - + input: + bytes: [ 0xde, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jne d15, #0, #0x20" + - + input: + bytes: [ 0x7e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0" + - + input: + bytes: [ 0x5e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jne d15, #0, #0" + - + input: + bytes: [ 0x5f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jne d0, d0, #0" + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jne d0, #0, #0" + - + input: + bytes: [ 0x7d, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jne.a a0, a0, #0" + - + input: + bytes: [ 0x1f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jned d0, d0, #0" + - + input: + bytes: [ 0x9f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jned d0, #0, #0" + - + input: + bytes: [ 0x1f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jnei d0, d0, #0" + - + input: + bytes: [ 0x9f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jnei d0, #0, #0" + - + input: + bytes: [ 0xee, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jnz d15, #0" + - + input: + bytes: [ 0xf6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jnz d0, #0" + - + input: + bytes: [ 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jnz.a a0, #0" + - + input: + bytes: [ 0xbd, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jnz.a a0, #0" + - + input: + bytes: [ 0xae, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0, #0" + - + input: + bytes: [ 0x6f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jnz.t d0, #0, #0" + - + input: + bytes: [ 0x6e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jz d15, #0" + - + input: + bytes: [ 0x76, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jz d0, #0" + - + input: + bytes: [ 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jz.a a0, #0" + - + input: + bytes: [ 0xbd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jz.a a0, #0" + - + input: + bytes: [ 0x2e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #0" + - + input: + bytes: [ 0x6f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "jz.t d0, #0, #0" + - + input: + bytes: [ 0xd8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.a a15, [sp]#0" + - + input: + bytes: [ 0xc8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.a a0, [a15]#0" + - + input: + bytes: [ 0xcc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.a a15, [a0]#0" + - + input: + bytes: [ 0xc4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0+]" + - + input: + bytes: [ 0xd4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]" + - + input: + bytes: [ 0x99, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.a a0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.a a0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.a a0, [p0+c]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.a a0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]#0" + - + input: + bytes: [ 0x79, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.b d0, [a0]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.b d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.b d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.b d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.b d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.b d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.b d0, [a0]#0" + - + input: + bytes: [ 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0]" + - + input: + bytes: [ 0x0c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a0]#0" + - + input: + bytes: [ 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0" + - + input: + bytes: [ 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0+]" + - + input: + bytes: [ 0x39, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.bu d0, [p0+r]" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.bu d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.bu d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.bu d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.d e0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.d e0, [p0+r]" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.d e0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.d e0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.d e0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.d e0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.da p0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.da p0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.da p0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.da p0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.da p0, [a0]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.da p0, #0" + - + input: + bytes: [ 0x84, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0+]" + - + input: + bytes: [ 0x8c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.h d15, [a0]#0" + - + input: + bytes: [ 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.h d0, [a15]#0" + - + input: + bytes: [ 0x94, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0]" + - + input: + bytes: [ 0xc9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.h d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.h d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.h d0, [p0+c]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.h d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0]#0" + - + input: + bytes: [ 0xb9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.hu d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.hu d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.hu d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a0]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.hu d0, #0" + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.q d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.q d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.q d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.q d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.q d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.q d0, [a0]#0" + - + input: + bytes: [ 0x58, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.w d15, [sp]#0" + - + input: + bytes: [ 0x54, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]" + - + input: + bytes: [ 0x44, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0+]" + - + input: + bytes: [ 0x4c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.w d15, [a0]#0" + - + input: + bytes: [ 0x48, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.w d0, [a15]#0" + - + input: + bytes: [ 0x19, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.w d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.w d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.w d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.w d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ldlcx #0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ldlcx [a0]#0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ldmst [a0+]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ldmst [p0+r], e0" + - + input: + bytes: [ 0xe5, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ldmst #0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ldmst [+a0]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ldmst [p0+c]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ldmst [a0]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "lducx [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "lducx #0" + - + input: + bytes: [ 0xc5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "lea a0, #0" + - + input: + bytes: [ 0xd9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "lea a0, [a0]#0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "lea a0, [a0]#0" + - + input: + bytes: [ 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "loop a0, #0xffffffe0" + - + input: + bytes: [ 0xfd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "loop a0, #0" + - + input: + bytes: [ 0xfd, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "loopu #0" + - + input: + bytes: [ 0x7a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "lt d15, d0, d0" + - + input: + bytes: [ 0xfa, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "lt d15, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "lt d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "lt.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "lt.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "lt.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "lt.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "lt.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "lt.w d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "lt.wu d0, d0, d0" + - + input: + bytes: [ 0x03, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd d0, d0, d0, #0" + - + input: + bytes: [ 0x13, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd e0, e0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x61, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd.f d0, d0, d0, d0" + - + input: + bytes: [ 0x83, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x13, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd.u e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madd.u e0, e0, d0, d0" + - + input: + bytes: [ 0x83, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddr.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddr.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x1c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddr.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddrs.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x98, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddrs.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x9c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddrs.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x03, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds d0, d0, d0, #0" + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds e0, e0, d0, d0" + - + input: + bytes: [ 0x83, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x84, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x94, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x13, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds.u d0, d0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds.u d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds.u e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "madds.u e0, e0, d0, d0" + - + input: + bytes: [ 0xc3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "max d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "max d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "max.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "max.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "max.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "max.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "max.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "max.u d0, d0, #0" + - + input: + bytes: [ 0x4d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mfcr d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "min d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "min d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "min.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "min.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "min.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "min.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "min.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "min.u d0, d0, #0" + - + input: + bytes: [ 0x02, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mov d0, d0" + - + input: + bytes: [ 0x82, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mov d0, #0" + - + input: + bytes: [ 0xd2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mov e0, #0" + - + input: + bytes: [ 0xda, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mov d15, #0" + - + input: + bytes: [ 0x3b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mov d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mov d0, d0" + - + input: + bytes: [ 0xfb, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mov e0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mov e0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mov e0, d0, d0" + - + input: + bytes: [ 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mov.a a0, #0" + - + input: + bytes: [ 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mov.a a0, d0" + - + input: + bytes: [ 0x01, 0x00, 0x30, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mov.a a0, d0" + - + input: + bytes: [ 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mov.aa a0, a0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mov.aa a0, a0" + - + input: + bytes: [ 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mov.d d0, a0" + - + input: + bytes: [ 0x01, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mov.d d0, a0" + - + input: + bytes: [ 0xbb, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mov.u d0, #0" + - + input: + bytes: [ 0x7b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "movh d0, #0" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "movh.a a0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub d0, d0, d0, #0" + - + input: + bytes: [ 0x33, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub e0, e0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x71, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub.f d0, d0, d0, d0" + - + input: + bytes: [ 0xa3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x33, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub.u e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msub.u e0, e0, d0, d0" + - + input: + bytes: [ 0xe3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubr.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubr.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x1c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubr.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubrs.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x98, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubrs.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x9c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubrs.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x23, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs d0, d0, d0, #0" + - + input: + bytes: [ 0x33, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs e0, e0, d0, d0" + - + input: + bytes: [ 0xa3, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x84, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x94, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x33, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs.u d0, d0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs.u d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs.u e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "msubs.u e0, e0, d0, d0" + - + input: + bytes: [ 0xcd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mtcr #0, d0" + - + input: + bytes: [ 0xe2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul d0, d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul e0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x41, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul.f d0, d0, d0" + - + input: + bytes: [ 0xb3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0uu, #0" + - + input: + bytes: [ 0x93, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul.q d0, d0, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul.q d0, d0, d0l, #0" + - + input: + bytes: [ 0x93, 0x00, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul.q d0, d0, d0, #0" + - + input: + bytes: [ 0x93, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul.q d0, d0u, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul.q d0, d0l, d0l, #0" + - + input: + bytes: [ 0x93, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul.q e0, d0, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul.q e0, d0, d0l, #0" + - + input: + bytes: [ 0x93, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul.q e0, d0, d0, #0" + - + input: + bytes: [ 0x53, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul.u e0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mul.u e0, d0, d0" + - + input: + bytes: [ 0xb3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0uu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0uu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0uu, #0" + - + input: + bytes: [ 0x93, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mulr.q d0, d0u, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x1c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "mulr.q d0, d0l, d0l, #0" + - + input: + bytes: [ 0x53, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "muls d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "muls d0, d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "muls.u d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "muls.u d0, d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "nand d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "nand d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "nand.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ne d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ne.a d0, a0, a0" + - + input: + bytes: [ 0x01, 0x00, 0x90, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "nez.a d0, a0" + - + input: + bytes: [ 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x46, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "nor d0" + - + input: + bytes: [ 0x0f, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "nor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x60, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "nor d0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or d0, d0" + - + input: + bytes: [ 0x96, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or d15, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or d0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x70, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or.ne d0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "orn d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xe0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "orn d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "orn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x6b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "pack d0, e0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "parity d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x51, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "q31tof d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x91, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "qseed.f d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "restore d0" + - + input: + bytes: [ 0x00, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ret" + - + input: + bytes: [ 0x0d, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "ret" + - + input: + bytes: [ 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "rfe" + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "rfe" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "rfm" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "rslcx" + - + input: + bytes: [ 0x2f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "rstv" + - + input: + bytes: [ 0x32, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "rsub d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "rsub d0, d0, #0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "rsubs d0, d0, #0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "rsubs.u d0, d0, #0" + - + input: + bytes: [ 0x32, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sat.b d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sat.b d0, d0" + - + input: + bytes: [ 0x32, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sat.bu d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sat.bu d0, d0" + - + input: + bytes: [ 0x32, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sat.h d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sat.h d0, d0" + - + input: + bytes: [ 0x32, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sat.hu d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sat.hu d0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sel d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sel d0, d0, d0, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "seln d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "seln d0, d0, d0, #0" + - + input: + bytes: [ 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh d0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x70, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.h d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.h d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.lt.u d0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.nand.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.ne d0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.orn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.xnor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sh.xor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x86, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sha d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sha d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sha d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sha.h d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sha.h d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "shas d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "shas d0, d0, #0" + - + input: + bytes: [ 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.a [sp]#0, a15" + - + input: + bytes: [ 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.a [a0]#0, a15" + - + input: + bytes: [ 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.a [a15]#0, a0" + - + input: + bytes: [ 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.a [a0+], a0" + - + input: + bytes: [ 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.a [a0], a0" + - + input: + bytes: [ 0xb5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.a [a0]#0, a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.a [a0+]#0, a0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.a [p0+r], a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.a [+a0]#0, a0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.a [p0+c]#0, a0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.a #0, a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.a [a0]#0, a0" + - + input: + bytes: [ 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.b [a0], d0" + - + input: + bytes: [ 0x28, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.b [a15]#0, d0" + - + input: + bytes: [ 0x2c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.b [a0]#0, d15" + - + input: + bytes: [ 0x24, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.b [a0+], d0" + - + input: + bytes: [ 0xe9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.b [a0]#0, d0" + - + input: + bytes: [ 0x25, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.b #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.b [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.b [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.b [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.b [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.b [a0]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.d [a0+]#0, e0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.d [p0+r], e0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.d #0, e0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.d [+a0]#0, e0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.d [p0+c]#0, e0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.d [a0]#0, e0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.da [a0+]#0, p0" + - + input: + bytes: [ 0xa9, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.da [p0+r], p0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.da [+a0]#0, p0" + - + input: + bytes: [ 0xa9, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.da [p0+c]#0, p0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.da [a0]#0, p0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.da #0, p0" + - + input: + bytes: [ 0xa4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.h [a0+], d0" + - + input: + bytes: [ 0xa8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.h [a15]#0, d0" + - + input: + bytes: [ 0xac, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.h [a0]#0, d15" + - + input: + bytes: [ 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.h [a0], d0" + - + input: + bytes: [ 0xf9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.h [a0]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.h [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.h [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.h [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.h [p0+c]#0, d0" + - + input: + bytes: [ 0x25, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.h #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.h [a0]#0, d0" + - + input: + bytes: [ 0x65, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.q #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.q [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.q [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.q [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.q [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.q [a0]#0, d0" + - + input: + bytes: [ 0xd5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.t #0, #0, #0" + - + input: + bytes: [ 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.w [sp]#0, d15" + - + input: + bytes: [ 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.w [a0], d0" + - + input: + bytes: [ 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.w [a0+], d0" + - + input: + bytes: [ 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.w [a15]#0, d0" + - + input: + bytes: [ 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d15" + - + input: + bytes: [ 0x59, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.w #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.w [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.w [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.w [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.w [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "stlcx #0" + - + input: + bytes: [ 0x49, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "stlcx [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "stucx #0" + - + input: + bytes: [ 0x49, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "stucx [a0]#0" + - + input: + bytes: [ 0x52, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sub d0, d15, d0" + - + input: + bytes: [ 0x5a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sub d15, d0, d0" + - + input: + bytes: [ 0xa2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sub d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sub d0, d0, d0" + - + input: + bytes: [ 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sub.a sp, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sub.a a0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sub.b d0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x31, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sub.f d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "sub.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "subc d0, d0, d0" + - + input: + bytes: [ 0x62, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "subs d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "subs d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "subs.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "subs.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "subs.u d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "subx d0, d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "svlcx" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "swap.w [a0+]#0, d0" + - + input: + bytes: [ 0x69, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "swap.w [p0+r], d0" + - + input: + bytes: [ 0xe5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "swap.w #0, d0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "swap.w [+a0]#0, d0" + - + input: + bytes: [ 0x69, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "swap.w [p0+c]#0, d0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "swap.w [a0]#0, d0" + - + input: + bytes: [ 0x69, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "swap.w [p0+i], d0" + - + input: + bytes: [ 0xad, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "syscall #0" + - + input: + bytes: [ 0x75, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "tlbdemap d0" + - + input: + bytes: [ 0x75, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "tlbflush.a" + - + input: + bytes: [ 0x75, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "tlbflush.b" + - + input: + bytes: [ 0x75, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "tlbmap e0" + - + input: + bytes: [ 0x75, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "tlbprobe.a d0" + - + input: + bytes: [ 0x75, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "tlbprobe.i d0" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "trapsv" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "trapv" + - + input: + bytes: [ 0x4b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "unpack e0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xc1, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "updfl d0" + - + input: + bytes: [ 0x4b, 0x00, 0x61, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "utof d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "xnor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "xnor d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "xnor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "xor d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "xor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "xor d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "xor.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "xor.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "xor.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "xor.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "xor.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "xor.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "xor.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "xor.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "xor.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "xor.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "xor.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "xor.ne d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_160" ] + expected: + insns: + - + asm_text: "xor.t d0, d0, #0, d0, #0" diff --git a/tests/MC/TriCore/tc161.s.yaml b/tests/MC/TriCore/tc161.s.yaml new file mode 100644 index 0000000000..c380a16a08 --- /dev/null +++ b/tests/MC/TriCore/tc161.s.yaml @@ -0,0 +1,7516 @@ +test_cases: + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "abs d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "abs.b d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "abs.h d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "absdif d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "absdif d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "absdif.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "absdif.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "absdifs d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "absdifs d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "absdifs.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "abss d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "abss.h d0, d0" + - + input: + bytes: [ 0x12, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "add d0, d15, d0" + - + input: + bytes: [ 0x92, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "add d0, d15, #0" + - + input: + bytes: [ 0x1a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "add d15, d0, d0" + - + input: + bytes: [ 0x42, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "add d0, d0" + - + input: + bytes: [ 0x9a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "add d15, d0, #0" + - + input: + bytes: [ 0xc2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "add d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "add d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "add d0, d0, #0" + - + input: + bytes: [ 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "add.a a0, a0" + - + input: + bytes: [ 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "add.a a0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "add.a a0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "add.b d0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x21, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "add.f d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "add.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "addc d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "addc d0, d0, #0" + - + input: + bytes: [ 0x1b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "addi d0, d0, #0" + - + input: + bytes: [ 0x9b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "addih d0, d0, #0" + - + input: + bytes: [ 0x11, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "addih.a a0, a0, #0" + - + input: + bytes: [ 0x22, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "adds d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "adds d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "adds d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "adds.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "adds.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "adds.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "adds.u d0, d0, #0" + - + input: + bytes: [ 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "addsc.a a0, a0, d15, #0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "addsc.a a0, a0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "addsc.at a0, a0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "addx d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "addx d0, d0, #0" + - + input: + bytes: [ 0x26, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and d0, d0" + - + input: + bytes: [ 0x16, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and d15, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and d0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and.ne d0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "andn d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "andn d0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "bisr #0" + - + input: + bytes: [ 0xad, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "bisr #0" + - + input: + bytes: [ 0xad, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "bisr #0" + - + input: + bytes: [ 0x4b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "bmerge d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "bsplit e0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachea.i [a0+]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachea.i [p0+r]" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachea.i [+a0]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachea.i [p0+c]#0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachea.i [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachea.w [a0+]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachea.w [p0+r]" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachea.w [+a0]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachea.w [p0+c]#0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachea.w [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachea.wi [a0+]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachea.wi [p0+r]" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachea.wi [+a0]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachea.wi [p0+c]#0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachea.wi [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachei.i [a0+]#0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachei.i [+a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachei.i [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachei.w [a0+]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachei.w [+a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachei.w [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachei.wi [a0+]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachei.wi [+a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cachei.wi [a0]#0" + - + input: + bytes: [ 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cadd d0, d15, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cadd d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cadd d0, d0, d0, #0" + - + input: + bytes: [ 0xca, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "caddn d0, d15, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "caddn d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "caddn d0, d0, d0, #0" + - + input: + bytes: [ 0x5c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "call #0" + - + input: + bytes: [ 0x6d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "call #0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "calla #0" + - + input: + bytes: [ 0x2d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "calli a0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "clo d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "clo.h d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cls d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xe0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cls.h d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xb0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "clz d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "clz.h d0, d0" + - + input: + bytes: [ 0x2a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cmov d0, d15, d0" + - + input: + bytes: [ 0xaa, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cmov d0, d15, #0" + - + input: + bytes: [ 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cmovn d0, d15, d0" + - + input: + bytes: [ 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cmovn d0, d15, #0" + - + input: + bytes: [ 0x4b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cmp.f d0, d0, d0" + - + input: + bytes: [ 0x49, 0x00, 0xc0, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cmpswap.w [a0]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cmpswap.w [p0+r], e0" + - + input: + bytes: [ 0x69, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cmpswap.w [p0+c]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cmpswap.w [a0+]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "cmpswap.w [+a0]#0, e0" + - + input: + bytes: [ 0x2b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "csub d0, d0, d0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "csubn d0, d0, d0, d0" + - + input: + bytes: [ 0x00, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "debug" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "debug" + - + input: + bytes: [ 0x77, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "dextr d0, d0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "dextr d0, d0, d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "disable" + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "disable d0" + - + input: + bytes: [ 0x4b, 0x00, 0x01, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "div e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x11, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "div.u e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x51, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "div.f d0, d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "dsync" + - + input: + bytes: [ 0x6b, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "dvadj e0, e0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "dvinit e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "dvinit.b e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "dvinit.bu e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "dvinit.h e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "dvinit.hu e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "dvinit.u e0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "dvstep e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "dvstep.u e0, e0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "enable" + - + input: + bytes: [ 0x3a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "eq d15, d0, d0" + - + input: + bytes: [ 0xba, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "eq d15, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "eq d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "eq.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "eq.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "eq.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "eq.w d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x60, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "eqany.b d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "eqany.b d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x60, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "eqany.h d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "eqany.h d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "eqz.a d0, a0" + - + input: + bytes: [ 0x17, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "extr d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "extr d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "extr d0, d0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, d0, #0" + - + input: + bytes: [ 0x61, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "fcall #0" + - + input: + bytes: [ 0xe1, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "fcalla #0" + - + input: + bytes: [ 0x2d, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "fcalli a0" + - + input: + bytes: [ 0x00, 0x70 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "fret" + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "fret" + - + input: + bytes: [ 0x4b, 0x00, 0x01, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ftoi d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x11, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ftoq31 d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x21, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ftou d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x31, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ftoiz d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x81, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ftoq31z d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x71, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ftouz d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ge d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x30, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ge.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ge.u d0, d0, #0" + - + input: + bytes: [ 0x37, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "imask e0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "imask e0, d0, d0, #0" + - + input: + bytes: [ 0xb7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "imask e0, #0, #0, #0" + - + input: + bytes: [ 0xd7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "imask e0, #0, d0, #0" + - + input: + bytes: [ 0x67, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ins.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x97, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, e0" + - + input: + bytes: [ 0xb7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, #0, #0" + - + input: + bytes: [ 0xd7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x67, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "insn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "isync" + - + input: + bytes: [ 0x4b, 0x00, 0x41, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "itof d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ixmax e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ixmax.u e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ixmin e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ixmin.u e0, e0, d0" + - + input: + bytes: [ 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "j #0" + - + input: + bytes: [ 0x1d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "j #0" + - + input: + bytes: [ 0x9d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ja #0" + - + input: + bytes: [ 0xbe, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x20" + - + input: + bytes: [ 0x9e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jeq d15, #0, #0x20" + - + input: + bytes: [ 0x3e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0" + - + input: + bytes: [ 0x1e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jeq d15, #0, #0" + - + input: + bytes: [ 0x5f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jeq d0, d0, #0" + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jeq d0, #0, #0" + - + input: + bytes: [ 0x7d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jeq.a a0, a0, #0" + - + input: + bytes: [ 0x7f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jge d0, d0, #0" + - + input: + bytes: [ 0xff, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jge d0, #0, #0" + - + input: + bytes: [ 0x7f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jge.u d0, d0, #0" + - + input: + bytes: [ 0xff, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jge.u d0, #0, #0" + - + input: + bytes: [ 0xce, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jgez d0, #0" + - + input: + bytes: [ 0x4e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jgtz d0, #0" + - + input: + bytes: [ 0xdc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ji a0" + - + input: + bytes: [ 0x2d, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ji a0" + - + input: + bytes: [ 0x5d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jl #0" + - + input: + bytes: [ 0xdd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jla #0" + - + input: + bytes: [ 0x8e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jlez d0, #0" + - + input: + bytes: [ 0x2d, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jli a0" + - + input: + bytes: [ 0x3f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jlt d0, d0, #0" + - + input: + bytes: [ 0xbf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jlt d0, #0, #0" + - + input: + bytes: [ 0x3f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jlt.u d0, d0, #0" + - + input: + bytes: [ 0xbf, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jlt.u d0, #0, #0" + - + input: + bytes: [ 0x0e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jltz d0, #0" + - + input: + bytes: [ 0xfe, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x20" + - + input: + bytes: [ 0xde, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jne d15, #0, #0x20" + - + input: + bytes: [ 0x7e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0" + - + input: + bytes: [ 0x5e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jne d15, #0, #0" + - + input: + bytes: [ 0x5f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jne d0, d0, #0" + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jne d0, #0, #0" + - + input: + bytes: [ 0x7d, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jne.a a0, a0, #0" + - + input: + bytes: [ 0x1f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jned d0, d0, #0" + - + input: + bytes: [ 0x9f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jned d0, #0, #0" + - + input: + bytes: [ 0x1f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jnei d0, d0, #0" + - + input: + bytes: [ 0x9f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jnei d0, #0, #0" + - + input: + bytes: [ 0xee, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jnz d15, #0" + - + input: + bytes: [ 0xf6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jnz d0, #0" + - + input: + bytes: [ 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jnz.a a0, #0" + - + input: + bytes: [ 0xbd, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jnz.a a0, #0" + - + input: + bytes: [ 0xae, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0, #0" + - + input: + bytes: [ 0x6f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jnz.t d0, #0, #0" + - + input: + bytes: [ 0x6e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jz d15, #0" + - + input: + bytes: [ 0x76, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jz d0, #0" + - + input: + bytes: [ 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jz.a a0, #0" + - + input: + bytes: [ 0xbd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jz.a a0, #0" + - + input: + bytes: [ 0x2e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #0" + - + input: + bytes: [ 0x6f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "jz.t d0, #0, #0" + - + input: + bytes: [ 0xd8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.a a15, [sp]#0" + - + input: + bytes: [ 0xc8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.a a0, [a15]#0" + - + input: + bytes: [ 0xcc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.a a15, [a0]#0" + - + input: + bytes: [ 0xc4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0+]" + - + input: + bytes: [ 0xd4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]" + - + input: + bytes: [ 0x99, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.a a0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.a a0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.a a0, [p0+c]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.a a0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]#0" + - + input: + bytes: [ 0x79, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.b d0, [a0]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.b d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.b d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.b d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.b d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.b d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.b d0, [a0]#0" + - + input: + bytes: [ 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0]" + - + input: + bytes: [ 0x0c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a0]#0" + - + input: + bytes: [ 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0" + - + input: + bytes: [ 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0+]" + - + input: + bytes: [ 0x39, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.bu d0, [p0+r]" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.bu d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.bu d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.bu d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.d e0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.d e0, [p0+r]" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.d e0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.d e0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.d e0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.d e0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.da p0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.da p0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.da p0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.da p0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.da p0, [a0]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.da p0, #0" + - + input: + bytes: [ 0x84, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0+]" + - + input: + bytes: [ 0x8c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.h d15, [a0]#0" + - + input: + bytes: [ 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.h d0, [a15]#0" + - + input: + bytes: [ 0x94, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0]" + - + input: + bytes: [ 0xc9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.h d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.h d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.h d0, [p0+c]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.h d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0]#0" + - + input: + bytes: [ 0xb9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.hu d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.hu d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.hu d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a0]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.hu d0, #0" + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.q d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.q d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.q d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.q d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.q d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.q d0, [a0]#0" + - + input: + bytes: [ 0x58, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.w d15, [sp]#0" + - + input: + bytes: [ 0x54, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]" + - + input: + bytes: [ 0x44, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0+]" + - + input: + bytes: [ 0x4c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.w d15, [a0]#0" + - + input: + bytes: [ 0x48, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.w d0, [a15]#0" + - + input: + bytes: [ 0x19, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.w d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.w d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.w d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.w d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ldlcx #0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ldlcx [a0]#0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ldmst [a0+]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ldmst [p0+r], e0" + - + input: + bytes: [ 0xe5, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ldmst #0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ldmst [+a0]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ldmst [p0+c]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ldmst [a0]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "lducx [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "lducx #0" + - + input: + bytes: [ 0xc5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "lea a0, #0" + - + input: + bytes: [ 0xd9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "lea a0, [a0]#0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "lea a0, [a0]#0" + - + input: + bytes: [ 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "loop a0, #0xffffffe0" + - + input: + bytes: [ 0xfd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "loop a0, #0" + - + input: + bytes: [ 0xfd, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "loopu #0" + - + input: + bytes: [ 0x7a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "lt d15, d0, d0" + - + input: + bytes: [ 0xfa, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "lt d15, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "lt d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "lt.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "lt.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "lt.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "lt.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "lt.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "lt.w d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "lt.wu d0, d0, d0" + - + input: + bytes: [ 0x03, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd d0, d0, d0, #0" + - + input: + bytes: [ 0x13, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd e0, e0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x61, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd.f d0, d0, d0, d0" + - + input: + bytes: [ 0x83, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x13, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd.u e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madd.u e0, e0, d0, d0" + - + input: + bytes: [ 0x83, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddr.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddr.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x1c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddr.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddrs.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x98, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddrs.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x9c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddrs.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x03, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds d0, d0, d0, #0" + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds e0, e0, d0, d0" + - + input: + bytes: [ 0x83, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x84, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x94, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x13, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds.u d0, d0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds.u d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds.u e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "madds.u e0, e0, d0, d0" + - + input: + bytes: [ 0xc3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "max d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "max d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "max.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "max.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "max.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "max.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "max.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "max.u d0, d0, #0" + - + input: + bytes: [ 0x4d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mfcr d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "min d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "min d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "min.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "min.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "min.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "min.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "min.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "min.u d0, d0, #0" + - + input: + bytes: [ 0x02, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mov d0, d0" + - + input: + bytes: [ 0x82, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mov d0, #0" + - + input: + bytes: [ 0xd2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mov e0, #0" + - + input: + bytes: [ 0xda, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mov d15, #0" + - + input: + bytes: [ 0x3b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mov d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mov d0, d0" + - + input: + bytes: [ 0xfb, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mov e0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mov e0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mov e0, d0, d0" + - + input: + bytes: [ 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mov.a a0, #0" + - + input: + bytes: [ 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mov.a a0, d0" + - + input: + bytes: [ 0x01, 0x00, 0x30, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mov.a a0, d0" + - + input: + bytes: [ 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mov.aa a0, a0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mov.aa a0, a0" + - + input: + bytes: [ 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mov.d d0, a0" + - + input: + bytes: [ 0x01, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mov.d d0, a0" + - + input: + bytes: [ 0xbb, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mov.u d0, #0" + - + input: + bytes: [ 0x7b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "movh d0, #0" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "movh.a a0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub d0, d0, d0, #0" + - + input: + bytes: [ 0x33, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub e0, e0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x71, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub.f d0, d0, d0, d0" + - + input: + bytes: [ 0xa3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x33, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub.u e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msub.u e0, e0, d0, d0" + - + input: + bytes: [ 0xe3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubr.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubr.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x1c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubr.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubrs.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x98, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubrs.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x9c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubrs.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x23, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs d0, d0, d0, #0" + - + input: + bytes: [ 0x33, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs e0, e0, d0, d0" + - + input: + bytes: [ 0xa3, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x84, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x94, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x33, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs.u d0, d0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs.u d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs.u e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "msubs.u e0, e0, d0, d0" + - + input: + bytes: [ 0xcd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mtcr #0, d0" + - + input: + bytes: [ 0xe2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul d0, d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul e0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x41, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul.f d0, d0, d0" + - + input: + bytes: [ 0xb3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0uu, #0" + - + input: + bytes: [ 0x93, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul.q d0, d0, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul.q d0, d0, d0l, #0" + - + input: + bytes: [ 0x93, 0x00, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul.q d0, d0, d0, #0" + - + input: + bytes: [ 0x93, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul.q d0, d0u, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul.q d0, d0l, d0l, #0" + - + input: + bytes: [ 0x93, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul.q e0, d0, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul.q e0, d0, d0l, #0" + - + input: + bytes: [ 0x93, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul.q e0, d0, d0, #0" + - + input: + bytes: [ 0x53, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul.u e0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mul.u e0, d0, d0" + - + input: + bytes: [ 0xb3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0uu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0uu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0uu, #0" + - + input: + bytes: [ 0x93, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mulr.q d0, d0u, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x1c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "mulr.q d0, d0l, d0l, #0" + - + input: + bytes: [ 0x53, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "muls d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "muls d0, d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "muls.u d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "muls.u d0, d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "nand d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "nand d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "nand.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ne d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ne.a d0, a0, a0" + - + input: + bytes: [ 0x01, 0x00, 0x90, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "nez.a d0, a0" + - + input: + bytes: [ 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x46, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "nor d0" + - + input: + bytes: [ 0x0f, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "nor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x60, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "nor d0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or d0, d0" + - + input: + bytes: [ 0x96, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or d15, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or d0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x70, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or.ne d0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "orn d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xe0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "orn d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "orn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x6b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "pack d0, e0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "parity d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x51, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "q31tof d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x91, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "qseed.f d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "restore d0" + - + input: + bytes: [ 0x00, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ret" + - + input: + bytes: [ 0x0d, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "ret" + - + input: + bytes: [ 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "rfe" + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "rfe" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "rfm" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "rslcx" + - + input: + bytes: [ 0x2f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "rstv" + - + input: + bytes: [ 0x32, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "rsub d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "rsub d0, d0, #0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "rsubs d0, d0, #0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "rsubs.u d0, d0, #0" + - + input: + bytes: [ 0x32, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sat.b d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sat.b d0, d0" + - + input: + bytes: [ 0x32, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sat.bu d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sat.bu d0, d0" + - + input: + bytes: [ 0x32, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sat.h d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sat.h d0, d0" + - + input: + bytes: [ 0x32, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sat.hu d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sat.hu d0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sel d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sel d0, d0, d0, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "seln d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "seln d0, d0, d0, #0" + - + input: + bytes: [ 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh d0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x70, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.h d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.h d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.lt.u d0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.nand.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.ne d0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.orn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.xnor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sh.xor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x86, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sha d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sha d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sha d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sha.h d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sha.h d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "shas d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "shas d0, d0, #0" + - + input: + bytes: [ 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.a [sp]#0, a15" + - + input: + bytes: [ 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.a [a0]#0, a15" + - + input: + bytes: [ 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.a [a15]#0, a0" + - + input: + bytes: [ 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.a [a0+], a0" + - + input: + bytes: [ 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.a [a0], a0" + - + input: + bytes: [ 0xb5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.a [a0]#0, a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.a [a0+]#0, a0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.a [p0+r], a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.a [+a0]#0, a0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.a [p0+c]#0, a0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.a #0, a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.a [a0]#0, a0" + - + input: + bytes: [ 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.b [a0], d0" + - + input: + bytes: [ 0x28, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.b [a15]#0, d0" + - + input: + bytes: [ 0x2c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.b [a0]#0, d15" + - + input: + bytes: [ 0x24, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.b [a0+], d0" + - + input: + bytes: [ 0xe9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.b [a0]#0, d0" + - + input: + bytes: [ 0x25, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.b #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.b [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.b [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.b [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.b [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.b [a0]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.d [a0+]#0, e0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.d [p0+r], e0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.d #0, e0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.d [+a0]#0, e0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.d [p0+c]#0, e0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.d [a0]#0, e0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.da [a0+]#0, p0" + - + input: + bytes: [ 0xa9, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.da [p0+r], p0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.da [+a0]#0, p0" + - + input: + bytes: [ 0xa9, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.da [p0+c]#0, p0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.da [a0]#0, p0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.da #0, p0" + - + input: + bytes: [ 0xa4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.h [a0+], d0" + - + input: + bytes: [ 0xa8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.h [a15]#0, d0" + - + input: + bytes: [ 0xac, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.h [a0]#0, d15" + - + input: + bytes: [ 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.h [a0], d0" + - + input: + bytes: [ 0xf9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.h [a0]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.h [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.h [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.h [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.h [p0+c]#0, d0" + - + input: + bytes: [ 0x25, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.h #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.h [a0]#0, d0" + - + input: + bytes: [ 0x65, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.q #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.q [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.q [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.q [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.q [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.q [a0]#0, d0" + - + input: + bytes: [ 0xd5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.t #0, #0, #0" + - + input: + bytes: [ 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.w [sp]#0, d15" + - + input: + bytes: [ 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.w [a0], d0" + - + input: + bytes: [ 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.w [a0+], d0" + - + input: + bytes: [ 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.w [a15]#0, d0" + - + input: + bytes: [ 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d15" + - + input: + bytes: [ 0x59, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.w #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.w [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.w [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.w [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.w [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "stlcx #0" + - + input: + bytes: [ 0x49, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "stlcx [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "stucx #0" + - + input: + bytes: [ 0x49, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "stucx [a0]#0" + - + input: + bytes: [ 0x52, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sub d0, d15, d0" + - + input: + bytes: [ 0x5a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sub d15, d0, d0" + - + input: + bytes: [ 0xa2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sub d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sub d0, d0, d0" + - + input: + bytes: [ 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sub.a sp, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sub.a a0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sub.b d0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x31, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sub.f d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "sub.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "subc d0, d0, d0" + - + input: + bytes: [ 0x62, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "subs d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "subs d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "subs.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "subs.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "subs.u d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "subx d0, d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "svlcx" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "swap.w [a0+]#0, d0" + - + input: + bytes: [ 0x69, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "swap.w [p0+r], d0" + - + input: + bytes: [ 0xe5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "swap.w #0, d0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "swap.w [+a0]#0, d0" + - + input: + bytes: [ 0x69, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "swap.w [p0+c]#0, d0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "swap.w [a0]#0, d0" + - + input: + bytes: [ 0x69, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "swap.w [p0+i], d0" + - + input: + bytes: [ 0x49, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "swapmsk.w [a0+]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "swapmsk.w [p0+r], e0" + - + input: + bytes: [ 0x49, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "swapmsk.w [+a0]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "swapmsk.w [p0+c]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "swapmsk.w [a0]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "swapmsk.w [p0+i], e0" + - + input: + bytes: [ 0xad, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "syscall #0" + - + input: + bytes: [ 0x75, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "tlbdemap d0" + - + input: + bytes: [ 0x75, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "tlbflush.a" + - + input: + bytes: [ 0x75, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "tlbflush.b" + - + input: + bytes: [ 0x75, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "tlbmap e0" + - + input: + bytes: [ 0x75, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "tlbprobe.a d0" + - + input: + bytes: [ 0x75, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "tlbprobe.i d0" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "trapsv" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "trapv" + - + input: + bytes: [ 0x4b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "unpack e0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xc1, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "updfl d0" + - + input: + bytes: [ 0x4b, 0x00, 0x61, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "utof d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "wait" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "xnor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "xnor d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "xnor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "xor d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "xor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "xor d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "xor.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "xor.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "xor.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "xor.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "xor.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "xor.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "xor.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "xor.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "xor.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "xor.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "xor.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "xor.ne d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_161" ] + expected: + insns: + - + asm_text: "xor.t d0, d0, #0, d0, #0" diff --git a/tests/MC/TriCore/tc162.s.yaml b/tests/MC/TriCore/tc162.s.yaml new file mode 100644 index 0000000000..d15e727f24 --- /dev/null +++ b/tests/MC/TriCore/tc162.s.yaml @@ -0,0 +1,7579 @@ +test_cases: + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "abs d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "abs.b d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "abs.h d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "absdif d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "absdif d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "absdif.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "absdif.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "absdifs d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "absdifs d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "absdifs.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "abss d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "abss.h d0, d0" + - + input: + bytes: [ 0x12, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d15, d0" + - + input: + bytes: [ 0x92, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d15, #0" + - + input: + bytes: [ 0x1a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d0, d0" + - + input: + bytes: [ 0x42, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d0" + - + input: + bytes: [ 0x9a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d15, d0, #0" + - + input: + bytes: [ 0xc2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add d0, d0, #0" + - + input: + bytes: [ 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a0, a0" + - + input: + bytes: [ 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.a a0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.b d0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x21, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.f d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "add.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addc d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addc d0, d0, #0" + - + input: + bytes: [ 0x1b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addi d0, d0, #0" + - + input: + bytes: [ 0x9b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih d0, d0, #0" + - + input: + bytes: [ 0x11, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addih.a a0, a0, #0" + - + input: + bytes: [ 0x22, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "adds d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "adds d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "adds d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "adds.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "adds.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "adds.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "adds.u d0, d0, #0" + - + input: + bytes: [ 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a0, a0, d15, #0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.a a0, a0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addsc.at a0, a0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addx d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "addx d0, d0, #0" + - + input: + bytes: [ 0x26, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d0" + - + input: + bytes: [ 0x16, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d15, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and d0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.ne d0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x47, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "andn d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "andn d0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "bisr #0" + - + input: + bytes: [ 0xad, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "bisr #0" + - + input: + bytes: [ 0x4b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "bmerge d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "bsplit e0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.i [a0+]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.i [p0+r]" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.i [+a0]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.i [p0+c]#0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.i [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.w [a0+]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.w [p0+r]" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.w [+a0]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.w [p0+c]#0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.w [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.wi [a0+]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.wi [p0+r]" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.wi [+a0]#0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.wi [p0+c]#0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachea.wi [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachei.i [a0+]#0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachei.i [+a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachei.i [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachei.w [a0+]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachei.w [+a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachei.w [a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachei.wi [a0+]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachei.wi [+a0]#0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x0b ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cachei.wi [a0]#0" + - + input: + bytes: [ 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cadd d0, d15, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cadd d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cadd d0, d0, d0, #0" + - + input: + bytes: [ 0xca, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "caddn d0, d15, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "caddn d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "caddn d0, d0, d0, #0" + - + input: + bytes: [ 0x5c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0" + - + input: + bytes: [ 0x6d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "call #0" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "calla #0" + - + input: + bytes: [ 0x2d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "calli a0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "clo d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "clo.h d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cls d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xe0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cls.h d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xb0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "clz d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "clz.h d0, d0" + - + input: + bytes: [ 0x2a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmov d0, d15, d0" + - + input: + bytes: [ 0xaa, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmov d0, d15, #0" + - + input: + bytes: [ 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmovn d0, d15, d0" + - + input: + bytes: [ 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmovn d0, d15, #0" + - + input: + bytes: [ 0x4b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmp.f d0, d0, d0" + - + input: + bytes: [ 0x49, 0x00, 0xc0, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmpswap.w [a0]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmpswap.w [p0+r], e0" + - + input: + bytes: [ 0x69, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmpswap.w [p0+c]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmpswap.w [a0+]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "cmpswap.w [+a0]#0, e0" + - + input: + bytes: [ 0x4b, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "crc32.b d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "crc32b.w d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "crc32l.w d0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "crcn d0, d0, d0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "csub d0, d0, d0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "csubn d0, d0, d0, d0" + - + input: + bytes: [ 0x00, 0xa0 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "debug" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "debug" + - + input: + bytes: [ 0x77, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "dextr d0, d0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "dextr d0, d0, d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "disable" + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "disable d0" + - + input: + bytes: [ 0x4b, 0x00, 0x01, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x11, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.u e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x51, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "div.f d0, d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "dsync" + - + input: + bytes: [ 0x6b, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "dvadj e0, e0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "dvinit e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "dvinit.b e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "dvinit.bu e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "dvinit.h e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "dvinit.hu e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "dvinit.u e0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "dvstep e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "dvstep.u e0, e0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "enable" + - + input: + bytes: [ 0x3a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq d15, d0, d0" + - + input: + bytes: [ 0xba, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq d15, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eq.w d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x60, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eqany.b d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eqany.b d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x60, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eqany.h d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xc0, 0x0e ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eqany.h d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "eqz.a d0, a0" + - + input: + bytes: [ 0x17, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr d0, d0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "extr.u d0, d0, d0, #0" + - + input: + bytes: [ 0x61, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcall #0" + - + input: + bytes: [ 0xe1, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcalla #0" + - + input: + bytes: [ 0x2d, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fcalli a0" + - + input: + bytes: [ 0x00, 0x70 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fret" + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "fret" + - + input: + bytes: [ 0x4b, 0x00, 0x01, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftoi d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x11, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftoq31 d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x21, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftou d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x31, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftoiz d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x81, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftoq31z d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x71, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftouz d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x51, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ftohp d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ge d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x30, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ge.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x50, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ge.u d0, d0, #0" + - + input: + bytes: [ 0x4b, 0x00, 0x41, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "hptof d0, d0" + - + input: + bytes: [ 0x37, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "imask e0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "imask e0, d0, d0, #0" + - + input: + bytes: [ 0xb7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "imask e0, #0, #0, #0" + - + input: + bytes: [ 0xd7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "imask e0, #0, d0, #0" + - + input: + bytes: [ 0x67, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ins.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x17, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, e0" + - + input: + bytes: [ 0x37, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, #0, #0" + - + input: + bytes: [ 0x57, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x97, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, e0" + - + input: + bytes: [ 0xb7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, #0, #0" + - + input: + bytes: [ 0xd7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insert d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x67, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "insn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "isync" + - + input: + bytes: [ 0x4b, 0x00, 0x41, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "itof d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ixmax e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ixmax.u e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ixmin e0, e0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ixmin.u e0, e0, d0" + - + input: + bytes: [ 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0" + - + input: + bytes: [ 0x1d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "j #0" + - + input: + bytes: [ 0x9d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ja #0" + - + input: + bytes: [ 0xbe, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0x20" + - + input: + bytes: [ 0x9e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0, #0x20" + - + input: + bytes: [ 0x3e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, d0, #0" + - + input: + bytes: [ 0x1e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d15, #0, #0" + - + input: + bytes: [ 0x5f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d0, d0, #0" + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq d0, #0, #0" + - + input: + bytes: [ 0x7d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jeq.a a0, a0, #0" + - + input: + bytes: [ 0x7f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d0, d0, #0" + - + input: + bytes: [ 0xff, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge d0, #0, #0" + - + input: + bytes: [ 0x7f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d0, d0, #0" + - + input: + bytes: [ 0xff, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jge.u d0, #0, #0" + - + input: + bytes: [ 0xce, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jgez d0, #0" + - + input: + bytes: [ 0x4e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jgtz d0, #0" + - + input: + bytes: [ 0xdc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ji a0" + - + input: + bytes: [ 0x2d, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ji a0" + - + input: + bytes: [ 0x5d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jl #0" + - + input: + bytes: [ 0xdd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jla #0" + - + input: + bytes: [ 0x8e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlez d0, #0" + - + input: + bytes: [ 0x2d, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jli a0" + - + input: + bytes: [ 0x3f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d0, d0, #0" + - + input: + bytes: [ 0xbf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt d0, #0, #0" + - + input: + bytes: [ 0x3f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, d0, #0" + - + input: + bytes: [ 0xbf, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jlt.u d0, #0, #0" + - + input: + bytes: [ 0x0e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jltz d0, #0" + - + input: + bytes: [ 0xfe, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0x20" + - + input: + bytes: [ 0xde, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0, #0x20" + - + input: + bytes: [ 0x7e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, d0, #0" + - + input: + bytes: [ 0x5e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d15, #0, #0" + - + input: + bytes: [ 0x5f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d0, d0, #0" + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne d0, #0, #0" + - + input: + bytes: [ 0x7d, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jne.a a0, a0, #0" + - + input: + bytes: [ 0x1f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jned d0, d0, #0" + - + input: + bytes: [ 0x9f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jned d0, #0, #0" + - + input: + bytes: [ 0x1f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnei d0, d0, #0" + - + input: + bytes: [ 0x9f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnei d0, #0, #0" + - + input: + bytes: [ 0xee, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d15, #0" + - + input: + bytes: [ 0xf6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz d0, #0" + - + input: + bytes: [ 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.a a0, #0" + - + input: + bytes: [ 0xbd, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.a a0, #0" + - + input: + bytes: [ 0xae, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d15, #0, #0" + - + input: + bytes: [ 0x6f, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jnz.t d0, #0, #0" + - + input: + bytes: [ 0x6e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d15, #0" + - + input: + bytes: [ 0x76, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz d0, #0" + - + input: + bytes: [ 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.a a0, #0" + - + input: + bytes: [ 0xbd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.a a0, #0" + - + input: + bytes: [ 0x2e, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d15, #0, #0" + - + input: + bytes: [ 0x6f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "jz.t d0, #0, #0" + - + input: + bytes: [ 0xd8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a15, [sp]#0" + - + input: + bytes: [ 0xc8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a0, [a15]#0" + - + input: + bytes: [ 0xcc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a15, [a0]#0" + - + input: + bytes: [ 0xc4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0+]" + - + input: + bytes: [ 0xd4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]" + - + input: + bytes: [ 0x99, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a0, [p0+c]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.a a0, [a0]#0" + - + input: + bytes: [ 0x79, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.b d0, [a0]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.b d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.b d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.b d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.b d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.b d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.b d0, [a0]#0" + - + input: + bytes: [ 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0]" + - + input: + bytes: [ 0x0c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d15, [a0]#0" + - + input: + bytes: [ 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a15]#0" + - + input: + bytes: [ 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0+]" + - + input: + bytes: [ 0x39, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [p0+r]" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.bu d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.d e0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.d e0, [p0+r]" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.d e0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.d e0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.d e0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.d e0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.da p0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.da p0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.da p0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.da p0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.da p0, [a0]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.da p0, #0" + - + input: + bytes: [ 0x84, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0+]" + - + input: + bytes: [ 0x8c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d15, [a0]#0" + - + input: + bytes: [ 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d0, [a15]#0" + - + input: + bytes: [ 0x94, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0]" + - + input: + bytes: [ 0xc9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d0, [p0+c]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.h d0, [a0]#0" + - + input: + bytes: [ 0xb9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a0]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0xc0, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d0, [a0]#0" + - + input: + bytes: [ 0x05, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.hu d0, #0" + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.q d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.q d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.q d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.q d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.q d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.q d0, [a0]#0" + - + input: + bytes: [ 0x58, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [sp]#0" + - + input: + bytes: [ 0x54, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]" + - + input: + bytes: [ 0x44, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0+]" + - + input: + bytes: [ 0x4c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d15, [a0]#0" + - + input: + bytes: [ 0x48, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [a15]#0" + - + input: + bytes: [ 0x19, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]#0" + - + input: + bytes: [ 0x85, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, #0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0+]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [p0+r]" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [+a0]#0" + - + input: + bytes: [ 0x29, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [p0+c]#0" + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ld.w d0, [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ldlcx #0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ldlcx [a0]#0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ldmst [a0+]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ldmst [p0+r], e0" + - + input: + bytes: [ 0xe5, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ldmst #0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ldmst [+a0]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x40, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ldmst [p0+c]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ldmst [a0]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lducx [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lducx #0" + - + input: + bytes: [ 0xc5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a0, #0" + - + input: + bytes: [ 0xd9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a0, [a0]#0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lea a0, [a0]#0" + - + input: + bytes: [ 0xc5, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lha a0, #0" + - + input: + bytes: [ 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a0, #0xffffffe0" + - + input: + bytes: [ 0xfd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loop a0, #0" + - + input: + bytes: [ 0xfd, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "loopu #0" + - + input: + bytes: [ 0x7a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt d15, d0, d0" + - + input: + bytes: [ 0xfa, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt d15, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt.a d0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt.w d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "lt.wu d0, d0, d0" + - + input: + bytes: [ 0x03, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd d0, d0, d0, #0" + - + input: + bytes: [ 0x13, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd e0, e0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x61, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd.f d0, d0, d0, d0" + - + input: + bytes: [ 0x83, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x13, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd.u e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madd.u e0, e0, d0, d0" + - + input: + bytes: [ 0x83, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddm.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddms.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddr.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddr.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddr.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x1c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddr.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddrs.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddrs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x98, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddrs.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x9c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddrs.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x03, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds d0, d0, d0, #0" + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds e0, e0, d0, d0" + - + input: + bytes: [ 0x83, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0x83, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0x83, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0x83, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x43, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0x84, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0x94, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x43, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x43, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x43, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x13, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds.u d0, d0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds.u d0, d0, d0, d0" + - + input: + bytes: [ 0x13, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds.u e0, e0, d0, #0" + - + input: + bytes: [ 0x03, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "madds.u e0, e0, d0, d0" + - + input: + bytes: [ 0xc3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsu.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsum.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsums.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsur.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsurs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xc3, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "maddsus.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "max d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "max d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "max.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "max.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "max.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "max.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "max.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "max.u d0, d0, #0" + - + input: + bytes: [ 0x4d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mfcr d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min.b d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min.bu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "min.u d0, d0, #0" + - + input: + bytes: [ 0x02, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, d0" + - + input: + bytes: [ 0x82, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0" + - + input: + bytes: [ 0xd2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e0, #0" + - + input: + bytes: [ 0xda, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d15, #0" + - + input: + bytes: [ 0x3b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov d0, d0" + - + input: + bytes: [ 0xfb, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov e0, d0, d0" + - + input: + bytes: [ 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a0, #0" + - + input: + bytes: [ 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a0, d0" + - + input: + bytes: [ 0x01, 0x00, 0x30, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.a a0, d0" + - + input: + bytes: [ 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a0, a0" + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.aa a0, a0" + - + input: + bytes: [ 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d0, a0" + - + input: + bytes: [ 0x01, 0x00, 0xc0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.d d0, a0" + - + input: + bytes: [ 0xbb, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mov.u d0, #0" + - + input: + bytes: [ 0x7b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh d0, #0" + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "movh.a a0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub d0, d0, d0, #0" + - + input: + bytes: [ 0x33, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub e0, e0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x71, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub.f d0, d0, d0, d0" + - + input: + bytes: [ 0xa3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x33, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub.u e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msub.u e0, e0, d0, d0" + - + input: + bytes: [ 0xe3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubad.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubadm.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubadms.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubadr.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubadrs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xe3, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubads.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubm.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubms.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubr.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubr.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubr.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x1c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubr.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubrs.h d0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xb8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xbc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubrs.h d0, d0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x98, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubrs.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x9c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubrs.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x23, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs d0, d0, d0, #0" + - + input: + bytes: [ 0x33, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs e0, e0, d0, d0" + - + input: + bytes: [ 0xa3, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0ul, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0lu, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0ll, #0" + - + input: + bytes: [ 0xa3, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs.h e0, e0, d0, d0uu, #0" + - + input: + bytes: [ 0x63, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0x84, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0x94, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs.q d0, d0, d0l, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0, d0l, #0" + - + input: + bytes: [ 0x63, 0x00, 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0, d0, #0" + - + input: + bytes: [ 0x63, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0u, d0u, #0" + - + input: + bytes: [ 0x63, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs.q e0, e0, d0l, d0l, #0" + - + input: + bytes: [ 0x33, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs.u d0, d0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs.u d0, d0, d0, d0" + - + input: + bytes: [ 0x33, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs.u e0, e0, d0, #0" + - + input: + bytes: [ 0x23, 0x00, 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "msubs.u e0, e0, d0, d0" + - + input: + bytes: [ 0xcd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mtcr #0, d0" + - + input: + bytes: [ 0xe2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x0a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul d0, d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul e0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x6a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul e0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x41, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.f d0, d0, d0" + - + input: + bytes: [ 0xb3, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.h e0, d0, d0uu, #0" + - + input: + bytes: [ 0x93, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.q d0, d0, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x04, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.q d0, d0, d0l, #0" + - + input: + bytes: [ 0x93, 0x00, 0x08, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.q d0, d0, d0, #0" + - + input: + bytes: [ 0x93, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.q d0, d0u, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x14, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.q d0, d0l, d0l, #0" + - + input: + bytes: [ 0x93, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.q e0, d0, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.q e0, d0, d0l, #0" + - + input: + bytes: [ 0x93, 0x00, 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.q e0, d0, d0, #0" + - + input: + bytes: [ 0x53, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.u e0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mul.u e0, d0, d0" + - + input: + bytes: [ 0xb3, 0x00, 0x70, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x7c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mulm.h e0, d0, d0uu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0xfc, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mulms.h e0, d0, d0uu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x30, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0ul, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0lu, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x38, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0ll, #0" + - + input: + bytes: [ 0xb3, 0x00, 0x3c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mulr.h d0, d0, d0uu, #0" + - + input: + bytes: [ 0x93, 0x00, 0x18, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mulr.q d0, d0u, d0u, #0" + - + input: + bytes: [ 0x93, 0x00, 0x1c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "mulr.q d0, d0l, d0l, #0" + - + input: + bytes: [ 0x53, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "muls d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x8a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "muls d0, d0, d0" + - + input: + bytes: [ 0x53, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "muls.u d0, d0, #0" + - + input: + bytes: [ 0x73, 0x00, 0x88, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "muls.u d0, d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "nand d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "nand d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "nand.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne d0, d0, #0" + - + input: + bytes: [ 0x01, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ne.a d0, a0, a0" + - + input: + bytes: [ 0x01, 0x00, 0x90, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "nez.a d0, a0" + - + input: + bytes: [ 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "nop" + - + input: + bytes: [ 0x0f, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "nor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x60, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "nor d0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d0, d0" + - + input: + bytes: [ 0x96, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d15, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or d0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x70, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.ne d0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x87, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "orn d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xe0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "orn d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "orn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x6b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "pack d0, e0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "parity d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "popcnt.w d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x51, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "q31tof d0, d0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0x91, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "qseed.f d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "restore d0" + - + input: + bytes: [ 0x00, 0x90 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ret" + - + input: + bytes: [ 0x0d, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "ret" + - + input: + bytes: [ 0x00, 0x80 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rfe" + - + input: + bytes: [ 0x0d, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rfe" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rfm" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rslcx" + - + input: + bytes: [ 0x2f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rstv" + - + input: + bytes: [ 0x32, 0x50 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsub d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsub d0, d0, #0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsubs d0, d0, #0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "rsubs.u d0, d0, #0" + - + input: + bytes: [ 0x32, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sat.b d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sat.b d0, d0" + - + input: + bytes: [ 0x32, 0x10 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sat.bu d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sat.bu d0, d0" + - + input: + bytes: [ 0x32, 0x20 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sat.h d0" + - + input: + bytes: [ 0x0b, 0x00, 0xe0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sat.h d0, d0" + - + input: + bytes: [ 0x32, 0x30 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sat.hu d0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sat.hu d0, d0" + - + input: + bytes: [ 0x2b, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sel d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sel d0, d0, d0, #0" + - + input: + bytes: [ 0x2b, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "seln d0, d0, d0, d0" + - + input: + bytes: [ 0xab, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "seln d0, d0, d0, #0" + - + input: + bytes: [ 0x06, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh d0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.and.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.andn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x70, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.h d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.h d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x90, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.lt.u d0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.nand.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.ne d0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.nor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x27, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.or.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.orn.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.xnor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xa7, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sh.xor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0x86, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha.h d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x20, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sha.h d0, d0, #0" + - + input: + bytes: [ 0x0f, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "shas d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "shas d0, d0, #0" + - + input: + bytes: [ 0x8f, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "shuffle d0, d0, #0" + - + input: + bytes: [ 0xf8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [sp]#0, a15" + - + input: + bytes: [ 0xec, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [a0]#0, a15" + - + input: + bytes: [ 0xe8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [a15]#0, a0" + - + input: + bytes: [ 0xe4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [a0+], a0" + - + input: + bytes: [ 0xf4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [a0], a0" + - + input: + bytes: [ 0xb5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [a0]#0, a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [a0+]#0, a0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [p0+r], a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [+a0]#0, a0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [p0+c]#0, a0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a #0, a0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.a [a0]#0, a0" + - + input: + bytes: [ 0x34, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a0], d0" + - + input: + bytes: [ 0x28, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a15]#0, d0" + - + input: + bytes: [ 0x2c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a0]#0, d15" + - + input: + bytes: [ 0x24, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a0+], d0" + - + input: + bytes: [ 0xe9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a0]#0, d0" + - + input: + bytes: [ 0x25, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.b [a0]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.d [a0+]#0, e0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.d [p0+r], e0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.d #0, e0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.d [+a0]#0, e0" + - + input: + bytes: [ 0xa9, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.d [p0+c]#0, e0" + - + input: + bytes: [ 0x89, 0x00, 0x40, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.d [a0]#0, e0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.da [a0+]#0, p0" + - + input: + bytes: [ 0xa9, 0x00, 0xc0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.da [p0+r], p0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.da [+a0]#0, p0" + - + input: + bytes: [ 0xa9, 0x00, 0xc0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.da [p0+c]#0, p0" + - + input: + bytes: [ 0x89, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.da [a0]#0, p0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.da #0, p0" + - + input: + bytes: [ 0xa4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a0+], d0" + - + input: + bytes: [ 0xa8, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a15]#0, d0" + - + input: + bytes: [ 0xac, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a0]#0, d15" + - + input: + bytes: [ 0xb4, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a0], d0" + - + input: + bytes: [ 0xf9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a0]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [p0+c]#0, d0" + - + input: + bytes: [ 0x25, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.h [a0]#0, d0" + - + input: + bytes: [ 0x65, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.q #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.q [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.q [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.q [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.q [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.q [a0]#0, d0" + - + input: + bytes: [ 0xd5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.t #0, #0, #0" + - + input: + bytes: [ 0x78, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [sp]#0, d15" + - + input: + bytes: [ 0x74, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a0], d0" + - + input: + bytes: [ 0x64, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a0+], d0" + - + input: + bytes: [ 0x68, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a15]#0, d0" + - + input: + bytes: [ 0x6c, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d15" + - + input: + bytes: [ 0x59, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d0" + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w #0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a0+]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [p0+r], d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [+a0]#0, d0" + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [p0+c]#0, d0" + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "st.w [a0]#0, d0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "stlcx #0" + - + input: + bytes: [ 0x49, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "stlcx [a0]#0" + - + input: + bytes: [ 0x15, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "stucx #0" + - + input: + bytes: [ 0x49, 0x00, 0xc0, 0x09 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "stucx [a0]#0" + - + input: + bytes: [ 0x52, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d0, d15, d0" + - + input: + bytes: [ 0x5a, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d15, d0, d0" + - + input: + bytes: [ 0xa2, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub d0, d0, d0" + - + input: + bytes: [ 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.a sp, #0" + - + input: + bytes: [ 0x01, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.a a0, a0, a0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.b d0, d0, d0" + - + input: + bytes: [ 0x6b, 0x00, 0x31, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.f d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "sub.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "subc d0, d0, d0" + - + input: + bytes: [ 0x62, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "subs d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "subs d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xa0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "subs.h d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "subs.hu d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xb0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "subs.u d0, d0, d0" + - + input: + bytes: [ 0x0b, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "subx d0, d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "svlcx" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "swap.w [a0+]#0, d0" + - + input: + bytes: [ 0x69, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "swap.w [p0+r], d0" + - + input: + bytes: [ 0xe5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "swap.w #0, d0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "swap.w [+a0]#0, d0" + - + input: + bytes: [ 0x69, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "swap.w [p0+c]#0, d0" + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "swap.w [a0]#0, d0" + - + input: + bytes: [ 0x69, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "swap.w [p0+i], d0" + - + input: + bytes: [ 0x49, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "swapmsk.w [a0+]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "swapmsk.w [p0+r], e0" + - + input: + bytes: [ 0x49, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "swapmsk.w [+a0]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "swapmsk.w [p0+c]#0, e0" + - + input: + bytes: [ 0x49, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "swapmsk.w [a0]#0, e0" + - + input: + bytes: [ 0x69, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "swapmsk.w [p0+i], e0" + - + input: + bytes: [ 0xad, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "syscall #0" + - + input: + bytes: [ 0x75, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "tlbdemap d0" + - + input: + bytes: [ 0x75, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "tlbflush.a" + - + input: + bytes: [ 0x75, 0x00, 0x50, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "tlbflush.b" + - + input: + bytes: [ 0x75, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "tlbmap e0" + - + input: + bytes: [ 0x75, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "tlbprobe.a d0" + - + input: + bytes: [ 0x75, 0x00, 0x90, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "tlbprobe.i d0" + - + input: + bytes: [ 0x0d, 0x00, 0x40, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "trapsv" + - + input: + bytes: [ 0x0d, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "trapv" + - + input: + bytes: [ 0x4b, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "unpack e0, d0" + - + input: + bytes: [ 0x4b, 0x00, 0xc1, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "updfl d0" + - + input: + bytes: [ 0x4b, 0x00, 0x61, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "utof d0, d0" + - + input: + bytes: [ 0x0d, 0x00, 0x80, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "wait" + - + input: + bytes: [ 0x0f, 0x00, 0xd0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xnor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0xa0, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xnor d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x40, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xnor.t d0, d0, #0, d0, #0" + - + input: + bytes: [ 0xc6, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d0, d0" + - + input: + bytes: [ 0x0f, 0x00, 0xc0, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d0, d0, d0" + - + input: + bytes: [ 0x8f, 0x00, 0x80, 0x01 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0xf0, 0x02 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor.eq d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0xe0, 0x05 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor.eq d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x30, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor.ge d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x60, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor.ge d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x40, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor.ge.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x80, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor.ge.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x10, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor.lt d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor.lt d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor.lt.u d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x40, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor.lt.u d0, d0, #0" + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor.ne d0, d0, d0" + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor.ne d0, d0, #0" + - + input: + bytes: [ 0x07, 0x00, 0x60, 0x00 ] + arch: "CS_ARCH_TRICORE" + options: [ "CS_MODE_TRICORE_162" ] + expected: + insns: + - + asm_text: "xor.t d0, d0, #0, d0, #0" diff --git a/tests/MC/X86/3DNow.s.yaml b/tests/MC/X86/3DNow.s.yaml new file mode 100644 index 0000000000..1ca4563389 --- /dev/null +++ b/tests/MC/X86/3DNow.s.yaml @@ -0,0 +1,253 @@ +test_cases: + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xbf ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pavgusb %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0x5c, 0x16, 0x09, 0xbf ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pavgusb 9(%esi, %edx), %mm3" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pf2id %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0x5c, 0x16, 0x09, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pf2id 9(%esi, %edx), %mm3" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xae ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfacc %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x9e ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfadd %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xb0 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfcmpeq %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x90 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfcmpge %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xa0 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfcmpgt %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xa4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfmax %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x94 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfmin %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xb4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfmul %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x96 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfrcp %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xa6 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfrcpit1 %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xb6 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfrcpit2 %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xa7 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfrsqit1 %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x97 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfrsqrt %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x9a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfsub %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xaa ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfsubr %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pi2fd %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xb7 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pmulhrw %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "femms" + - + input: + bytes: [ 0x0f, 0x0d, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "prefetch (%eax)" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pf2iw %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pi2fw %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x8a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfnacc %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0x8e ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pfpnacc %mm2, %mm1" + - + input: + bytes: [ 0x0f, 0x0f, 0xca, 0xbb ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pswapd %mm2, %mm1" diff --git a/tests/MC/X86/address-size.s.yaml b/tests/MC/X86/address-size.s.yaml new file mode 100644 index 0000000000..cae1ba1f45 --- /dev/null +++ b/tests/MC/X86/address-size.s.yaml @@ -0,0 +1,37 @@ +test_cases: + - + input: + bytes: [ 0x67, 0xc6, 0x06, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movb $0x0, (%esi)" + - + input: + bytes: [ 0xc6, 0x06, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movb $0x0, (%rsi)" + - + input: + bytes: [ 0x67, 0xc6, 0x06, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movb $0x0, (%esi)" + - + input: + bytes: [ 0xc6, 0x06, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movb $0x0, (%rsi)" diff --git a/tests/MC/X86/avx512-encodings.s.yaml b/tests/MC/X86/avx512-encodings.s.yaml new file mode 100644 index 0000000000..e13d723ca0 --- /dev/null +++ b/tests/MC/X86/avx512-encodings.s.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x62, 0xa3, 0x55, 0x48, 0x38, 0xcd, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vinserti32x4 $1, %xmm21, %zmm5, %zmm17" + - + input: + bytes: [ 0x62, 0xe3, 0x1d, 0x40, 0x38, 0x4f, 0x10, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vinserti32x4 $1, 256(%rdi), %zmm28, %zmm17" + - + input: + bytes: [ 0x62, 0x33, 0x7d, 0x48, 0x39, 0xc9, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vextracti32x4 $1, %zmm9, %xmm17" + - + input: + bytes: [ 0x62, 0x33, 0xfd, 0x48, 0x3b, 0xc9, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vextracti64x4 $1, %zmm9, %ymm17" + - + input: + bytes: [ 0x62, 0x73, 0xfd, 0x48, 0x3b, 0x4f, 0x10, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vextracti64x4 $1, %zmm9, 512(%rdi)" + - + input: + bytes: [ 0x62, 0xb1, 0x35, 0x40, 0x72, 0xe1, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrad $2, %zmm17, %zmm25" + - + input: + bytes: [ 0x62, 0xf1, 0x35, 0x40, 0x72, 0x64, 0xb7, 0x08, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrad $2, 512(%rdi, %rsi, 4), %zmm25" + - + input: + bytes: [ 0x62, 0x21, 0x1d, 0x48, 0xe2, 0xc9 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrad %xmm17, %zmm12, %zmm25" + - + input: + bytes: [ 0x62, 0x61, 0x1d, 0x48, 0xe2, 0x4c, 0xb7, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrad 512(%rdi, %rsi, 4), %zmm12, %zmm25" + - + input: + bytes: [ 0x62, 0xf2, 0x7d, 0xc9, 0x58, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpbroadcastd %xmm0, %zmm1 {%k1} {z}" + - + input: + bytes: [ 0x62, 0xf1, 0xfe, 0x4b, 0x6f, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovdqu64 %zmm0, %zmm1 {%k3}" diff --git a/tests/MC/X86/intel-syntax-encoding.s.yaml b/tests/MC/X86/intel-syntax-encoding.s.yaml new file mode 100644 index 0000000000..cd827fbdb6 --- /dev/null +++ b/tests/MC/X86/intel-syntax-encoding.s.yaml @@ -0,0 +1,262 @@ +test_cases: + - + input: + bytes: [ 0x66, 0x83, 0xf0, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "xor ax, 12" + - + input: + bytes: [ 0x83, 0xf0, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "xor eax, 12" + - + input: + bytes: [ 0x48, 0x83, 0xf0, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "xor rax, 12" + - + input: + bytes: [ 0x66, 0x83, 0xc8, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "or ax, 12" + - + input: + bytes: [ 0x83, 0xc8, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "or eax, 12" + - + input: + bytes: [ 0x48, 0x83, 0xc8, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "or rax, 12" + - + input: + bytes: [ 0x66, 0x83, 0xf8, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "cmp ax, 12" + - + input: + bytes: [ 0x83, 0xf8, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "cmp eax, 12" + - + input: + bytes: [ 0x48, 0x83, 0xf8, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "cmp rax, 12" + - + input: + bytes: [ 0x48, 0x89, 0x44, 0x24, 0xf0 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "mov qword ptr [rsp - 16], rax" + - + input: + bytes: [ 0x66, 0x83, 0xc0, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "add ax, -12" + - + input: + bytes: [ 0x83, 0xc0, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "add eax, -12" + - + input: + bytes: [ 0x48, 0x83, 0xc0, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "add rax, -12" + - + input: + bytes: [ 0x66, 0x83, 0xd0, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "adc ax, -12" + - + input: + bytes: [ 0x83, 0xd0, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "adc eax, -12" + - + input: + bytes: [ 0x48, 0x83, 0xd0, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "adc rax, -12" + - + input: + bytes: [ 0x66, 0x83, 0xd8, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sbb ax, -12" + - + input: + bytes: [ 0x83, 0xd8, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sbb eax, -12" + - + input: + bytes: [ 0x48, 0x83, 0xd8, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sbb rax, -12" + - + input: + bytes: [ 0x66, 0x83, 0xf8, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "cmp ax, -12" + - + input: + bytes: [ 0x83, 0xf8, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "cmp eax, -12" + - + input: + bytes: [ 0x48, 0x83, 0xf8, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "cmp rax, -12" + - + input: + bytes: [ 0xf2, 0x0f, 0x10, 0x2c, 0x25, 0xf8, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movsd xmm5, qword ptr [0xfffffffffffffff8]" + - + input: + bytes: [ 0xd1, 0xe7 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "shl edi, 1" + - + input: + bytes: [ 0x0f, 0xc2, 0xd1, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "cmpltps xmm2, xmm1" + - + input: + bytes: [ 0xc3 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "ret" + - + input: + bytes: [ 0xcb ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "retf" + - + input: + bytes: [ 0xc2, 0x08, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "ret 8" + - + input: + bytes: [ 0xca, 0x08, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_64" ] + expected: + insns: + - + asm_text: "retf 8" diff --git a/tests/MC/X86/x86-32-avx.s.yaml b/tests/MC/X86/x86-32-avx.s.yaml new file mode 100644 index 0000000000..bcf43a14be --- /dev/null +++ b/tests/MC/X86/x86-32-avx.s.yaml @@ -0,0 +1,7354 @@ +test_cases: + - + input: + bytes: [ 0xc5, 0xca, 0x58, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddss %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xca, 0x59, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulss %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xca, 0x5c, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubss %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xca, 0x5e, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivss %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xcb, 0x58, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsd %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xcb, 0x59, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulsd %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xcb, 0x5c, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubsd %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xcb, 0x5e, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivsd %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xea, 0x58, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xea, 0x5c, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xea, 0x59, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xea, 0x5e, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xeb, 0x58, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xeb, 0x5c, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xeb, 0x59, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xeb, 0x5e, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xc8, 0x58, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddps %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xc8, 0x5c, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubps %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xc8, 0x59, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulps %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xc8, 0x5e, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivps %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xc9, 0x58, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddpd %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xc9, 0x5c, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubpd %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xc9, 0x59, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulpd %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xc9, 0x5e, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivpd %xmm4, %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xe8, 0x58, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe8, 0x5c, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe8, 0x59, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe8, 0x5e, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x58, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x5c, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x59, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x5e, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xda, 0x5f, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxss %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xdb, 0x5f, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxsd %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xda, 0x5d, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminss %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xdb, 0x5d, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminsd %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xea, 0x5f, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxss -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xeb, 0x5f, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxsd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xea, 0x5d, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminss -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xeb, 0x5d, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminsd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xd8, 0x5f, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxps %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xd9, 0x5f, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxpd %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xd8, 0x5d, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminps %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xd9, 0x5d, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminpd %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xe8, 0x5f, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxps -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x5f, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxpd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe8, 0x5d, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminps -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x5d, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminpd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xd8, 0x54, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandps %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xd9, 0x54, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandpd %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xe8, 0x54, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandps -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x54, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandpd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xd8, 0x56, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vorps %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xd9, 0x56, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vorpd %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xe8, 0x56, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vorps -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x56, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vorpd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xd8, 0x57, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vxorps %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xd9, 0x57, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vxorpd %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xe8, 0x57, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vxorps -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x57, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vxorpd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xd8, 0x55, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandnps %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xd9, 0x55, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandnpd %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xe8, 0x55, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandnps -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x55, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandnpd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xfa, 0x10, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovss -4(%ebx, %ecx, 8), %xmm5" + - + input: + bytes: [ 0xc5, 0xea, 0x10, 0xec ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovss %xmm4, %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xfb, 0x10, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovsd -4(%ebx, %ecx, 8), %xmm5" + - + input: + bytes: [ 0xc5, 0xeb, 0x10, 0xec ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovsd %xmm4, %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe8, 0x15, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpckhps %xmm1, %xmm2, %xmm4" + - + input: + bytes: [ 0xc5, 0xe9, 0x15, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpckhpd %xmm1, %xmm2, %xmm4" + - + input: + bytes: [ 0xc5, 0xe8, 0x14, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpcklps %xmm1, %xmm2, %xmm4" + - + input: + bytes: [ 0xc5, 0xe9, 0x14, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpcklpd %xmm1, %xmm2, %xmm4" + - + input: + bytes: [ 0xc5, 0xe8, 0x15, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpckhps -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x15, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpckhpd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe8, 0x14, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpcklps -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0x14, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpcklpd -4(%ebx, %ecx, 8), %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xc8, 0xc2, 0xc8, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqps %xmm0, %xmm6, %xmm1" + - + input: + bytes: [ 0xc5, 0xc8, 0xc2, 0x08, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqps (%eax), %xmm6, %xmm1" + - + input: + bytes: [ 0xc5, 0xc8, 0xc2, 0xc8, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordps %xmm0, %xmm6, %xmm1" + - + input: + bytes: [ 0xc5, 0xc9, 0xc2, 0xc8, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqpd %xmm0, %xmm6, %xmm1" + - + input: + bytes: [ 0xc5, 0xc9, 0xc2, 0x08, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqpd (%eax), %xmm6, %xmm1" + - + input: + bytes: [ 0xc5, 0xc9, 0xc2, 0xc8, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordpd %xmm0, %xmm6, %xmm1" + - + input: + bytes: [ 0xc5, 0xe8, 0xc6, 0xd9, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vshufps $8, %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc6, 0x5c, 0xcb, 0xfc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vshufps $8, -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc6, 0xd9, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vshufpd $8, %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc6, 0x5c, 0xcb, 0xfc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vshufpd $8, -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpleps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnleps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqps -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpleps -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltps -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqps -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnleps -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltps -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xc8, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordps -4(%ebx, %ecx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordps -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqpd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmplepd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltpd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqpd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnlepd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltpd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordpd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordpd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqpd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmplepd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltpd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqpd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnlepd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltpd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xc9, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordpd -4(%ebx, %ecx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordpd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf8, 0x50, 0xc2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovmskps %xmm2, %eax" + - + input: + bytes: [ 0xc5, 0xf9, 0x50, 0xc2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovmskpd %xmm2, %eax" + - + input: + bytes: [ 0xc5, 0xfc, 0x50, 0xc2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovmskps %ymm2, %eax" + - + input: + bytes: [ 0xc5, 0xfd, 0x50, 0xc2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovmskpd %ymm2, %eax" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqss %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpless %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltss %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqss %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnless %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltss %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordss %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordss %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqss -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpless -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltss -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqss -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnless -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltss -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xca, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordss -4(%ebx, %ecx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordss -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqsd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmplesd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltsd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqsd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnlesd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltsd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordsd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordsd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqsd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmplesd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltsd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqsd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnlesd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltsd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xcb, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordsd -4(%ebx, %ecx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordsd -4(%ebx, %ecx, 8), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf8, 0x2e, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vucomiss %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x2e, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vucomiss (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x2f, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcomiss %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x2f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcomiss (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x2e, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vucomisd %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x2e, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vucomisd (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x2f, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcomisd %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x2f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcomisd (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xfa, 0x2c, 0xc1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttss2si %xmm1, %eax" + - + input: + bytes: [ 0xc5, 0xf2, 0x2a, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsi2ssl (%eax), %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xfb, 0x2c, 0xc1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttsd2si %xmm1, %eax" + - + input: + bytes: [ 0xc5, 0xfb, 0x2c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttsd2si (%ecx), %eax" + - + input: + bytes: [ 0xc5, 0xf3, 0x2a, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsi2sdl (%eax), %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x28, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovaps (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x28, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovaps %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x29, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovaps %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xf9, 0x28, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovapd (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x28, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovapd %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x29, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovapd %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xf8, 0x10, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovups (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x10, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovups %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x11, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovups %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xf9, 0x10, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovupd (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x10, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovupd %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x11, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovupd %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xf8, 0x13, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovlps %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xe8, 0x12, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovlps (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf9, 0x13, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovlpd %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xe9, 0x12, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovlpd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf8, 0x17, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovhps %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xe8, 0x16, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovhps (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf9, 0x17, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovhpd %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xe9, 0x16, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovhpd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0x16, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovlhps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0x12, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovhlps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xfa, 0x2d, 0xc1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtss2si %xmm1, %eax" + - + input: + bytes: [ 0xc5, 0xfa, 0x2d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtss2si (%eax), %ebx" + - + input: + bytes: [ 0xc5, 0xfa, 0x2d, 0xc1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtss2si %xmm1, %eax" + - + input: + bytes: [ 0xc5, 0xfa, 0x2d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtss2si (%eax), %ebx" + - + input: + bytes: [ 0xc5, 0xf8, 0x5b, 0xf5 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2ps %xmm5, %xmm6" + - + input: + bytes: [ 0xc5, 0xf8, 0x5b, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2ps (%eax), %xmm6" + - + input: + bytes: [ 0xc5, 0xdb, 0x5a, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsd2ss %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xdb, 0x5a, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsd2ss (%eax), %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xf9, 0x5b, 0xda ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtps2dq %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf9, 0x5b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtps2dq (%eax), %xmm3" + - + input: + bytes: [ 0xc5, 0xda, 0x5a, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtss2sd %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xda, 0x5a, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtss2sd (%eax), %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xf8, 0x5b, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2ps %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xf8, 0x5b, 0x21 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2ps (%ecx), %xmm4" + - + input: + bytes: [ 0xc5, 0xfa, 0x5b, 0xda ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttps2dq %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xfa, 0x5b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttps2dq (%eax), %xmm3" + - + input: + bytes: [ 0xc5, 0xf8, 0x5a, 0xda ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtps2pd %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf8, 0x5a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtps2pd (%eax), %xmm3" + - + input: + bytes: [ 0xc5, 0xf9, 0x5a, 0xda ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2ps %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf9, 0x51, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtpd %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x51, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtpd (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x51, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtps %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x51, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtps (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xeb, 0x51, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtsd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0x51, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtsd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0x51, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtss %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0x51, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtss (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf8, 0x52, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrsqrtps %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x52, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrsqrtps (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xea, 0x52, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrsqrtss %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0x52, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrsqrtss (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf8, 0x53, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrcpps %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf8, 0x53, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrcpps (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xea, 0x53, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrcpss %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xea, 0x53, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrcpss (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf9, 0xe7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovntdq %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xf9, 0x2b, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovntpd %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xf8, 0x2b, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovntps %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xf8, 0xae, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vldmxcsr (%eax)" + - + input: + bytes: [ 0xc5, 0xf8, 0xae, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vstmxcsr (%eax)" + - + input: + bytes: [ 0xc5, 0xf8, 0xae, 0x15, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vldmxcsr 0xdeadbeef" + - + input: + bytes: [ 0xc5, 0xf8, 0xae, 0x1d, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vstmxcsr 0xdeadbeef" + - + input: + bytes: [ 0xc5, 0xe9, 0xf8, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf9, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf9, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfa, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfa, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfb, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubq %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfb, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe8, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubsb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubsb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe9, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubsw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe9, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubsw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd8, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubusb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubusb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd9, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubusw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd9, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsubusw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfc, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfd, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfd, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfe, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xfe, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd4, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddq %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd4, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xec, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddsb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xec, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddsb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xed, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddsw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xed, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddsw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xdc, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddusb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xdc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddusb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xdd, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddusw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xdd, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpaddusw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe4, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmulhuw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe4, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmulhuw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe5, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmulhw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe5, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmulhw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd5, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmullw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd5, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmullw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf4, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmuludq %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf4, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmuludq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe0, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpavgb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe0, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpavgb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe3, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpavgw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe3, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpavgw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xea, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminsw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xea, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminsw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xda, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminub %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xda, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminub (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xee, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxsw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xee, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxsw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xde, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxub %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xde, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxub (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf6, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsadbw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsadbw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf1, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsllw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf1, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsllw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf2, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpslld %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf2, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpslld (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf3, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsllq %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xf3, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsllq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe1, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsraw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe1, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsraw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe2, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrad %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xe2, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrad (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd1, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrlw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd1, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrlw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd2, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrld %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd2, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrld (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd3, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrlq %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xd3, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrlq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x72, 0xf2, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpslld $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x73, 0xfa, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpslldq $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x73, 0xf2, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsllq $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x71, 0xf2, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsllw $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x72, 0xe2, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrad $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x71, 0xe2, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsraw $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x72, 0xd2, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrld $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x73, 0xda, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrldq $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x73, 0xd2, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrlq $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x71, 0xd2, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsrlw $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe1, 0x72, 0xf2, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpslld $10, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xdb, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpand %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xdb, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpand (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xeb, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpor %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xeb, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpor (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xef, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpxor %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xef, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpxor (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xdf, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpandn %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xdf, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpandn (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x74, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpeqb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x74, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpeqb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x75, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpeqw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x75, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpeqw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x76, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpeqd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x76, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpeqd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x64, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpgtb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x64, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpgtb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x65, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpgtw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x65, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpgtw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x66, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpgtd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x66, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpgtd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x63, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpacksswb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x63, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpacksswb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x6b, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpackssdw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x6b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpackssdw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x67, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpackuswb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x67, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpackuswb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf9, 0x70, 0xda, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpshufd $4, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf9, 0x70, 0x18, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpshufd $4, (%eax), %xmm3" + - + input: + bytes: [ 0xc5, 0xfa, 0x70, 0xda, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpshufhw $4, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xfa, 0x70, 0x18, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpshufhw $4, (%eax), %xmm3" + - + input: + bytes: [ 0xc5, 0xfb, 0x70, 0xda, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpshuflw $4, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xfb, 0x70, 0x18, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpshuflw $4, (%eax), %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x60, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpcklbw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x60, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpcklbw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x61, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpcklwd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x61, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpcklwd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x62, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckldq %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x62, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckldq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x6c, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpcklqdq %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x6c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpcklqdq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x68, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckhbw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x68, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckhbw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x69, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckhwd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x69, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckhwd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x6a, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckhdq %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x6a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckhdq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x6d, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckhqdq %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x6d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpunpckhqdq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc4, 0xd8, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpinsrw $7, %eax, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0xc4, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpinsrw $7, (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf9, 0xc5, 0xc2, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpextrw $7, %xmm2, %eax" + - + input: + bytes: [ 0xc5, 0xf9, 0xd7, 0xc1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovmskb %xmm1, %eax" + - + input: + bytes: [ 0xc5, 0xf9, 0xf7, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaskmovdqu %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0x7e, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovd %xmm1, %eax" + - + input: + bytes: [ 0xc5, 0xf9, 0x7e, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovd %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xf9, 0x6e, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovd %eax, %xmm1" + - + input: + bytes: [ 0xc5, 0xf9, 0x6e, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovd (%eax), %xmm1" + - + input: + bytes: [ 0xc5, 0xf9, 0xd6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovq %xmm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xfa, 0x7e, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovq %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xfa, 0x7e, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovq (%eax), %xmm1" + - + input: + bytes: [ 0xc5, 0xfb, 0xe6, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2dq %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xfa, 0xe6, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2pd %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xfa, 0xe6, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2pd (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xfa, 0x16, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovshdup %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xfa, 0x16, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovshdup (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xfa, 0x12, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovsldup %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xfa, 0x12, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovsldup (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xfb, 0x12, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovddup %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xfb, 0x12, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovddup (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xeb, 0xd0, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsubps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf3, 0xd0, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsubps (%eax), %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xe9, 0xd0, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsubpd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xf1, 0xd0, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsubpd (%eax), %xmm1, %xmm2" + - + input: + bytes: [ 0xc5, 0xeb, 0x7c, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhaddps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0x7c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhaddps (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x7c, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhaddpd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x7c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhaddpd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0x7d, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhsubps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xeb, 0x7d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhsubps (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x7d, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhsubpd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe9, 0x7d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhsubpd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x1c, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpabsb %xmm1, %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x1c, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpabsb (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x1d, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpabsw %xmm1, %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x1d, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpabsw (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x1e, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpabsd %xmm1, %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x1e, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpabsd (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x01, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphaddw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x01, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphaddw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x02, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphaddd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x02, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphaddd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x03, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphaddsw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x03, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphaddsw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x05, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphsubw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x05, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphsubw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x06, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphsubd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x06, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphsubd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x07, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphsubsw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x07, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphsubsw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x04, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaddubsw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x04, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaddubsw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x00, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpshufb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x00, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpshufb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x08, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsignb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x08, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsignb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x09, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsignw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x09, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsignw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x0a, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsignd %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x0a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpsignd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x0b, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmulhrsw %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x0b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmulhrsw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x0f, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpalignr $7, %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x0f, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpalignr $7, (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x0b, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundsd $7, %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x0b, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundsd $7, (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x0a, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundss $7, %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x0a, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundss $7, (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x09, 0xda, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundpd $7, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x09, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundpd $7, (%eax), %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x08, 0xda, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundps $7, %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x08, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundps $7, (%eax), %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x41, 0xda ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphminposuw %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x41, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vphminposuw (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x2b, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpackusdw %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x2b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpackusdw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x29, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpeqq %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x29, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpeqq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x38, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminsb %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x38, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminsb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x39, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminsd %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x39, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminsd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x3b, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminud %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x3b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminud (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x3a, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminuw %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x3a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpminuw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x3c, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxsb %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x3c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxsb (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x3d, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxsd %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x3d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxsd (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x3f, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxud %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x3f, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxud (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x3e, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxuw %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x3e, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmaxuw (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x61, 0x28, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmuldq %xmm2, %xmm3, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x28, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmuldq (%eax), %xmm2, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x40, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmulld %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x40, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmulld (%eax), %xmm5, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x0c, 0xca, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendps $3, %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x0c, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendps $3, (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x0d, 0xca, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendpd $3, %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x0d, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendpd $3, (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x0e, 0xca, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpblendw $3, %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x0e, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpblendw $3, (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x42, 0xca, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmpsadbw $3, %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x42, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmpsadbw $3, (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x40, 0xca, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdpps $3, %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x40, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdpps $3, (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x41, 0xca, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdppd $3, %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x41, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdppd $3, (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x71, 0x4b, 0xdd, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendvpd %xmm2, %xmm5, %xmm1, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x71, 0x4b, 0x18, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendvpd %xmm2, (%eax), %xmm1, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x71, 0x4a, 0xdd, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendvps %xmm2, %xmm5, %xmm1, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x71, 0x4a, 0x18, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendvps %xmm2, (%eax), %xmm1, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x71, 0x4c, 0xdd, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpblendvb %xmm2, %xmm5, %xmm1, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x71, 0x4c, 0x18, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpblendvb %xmm2, (%eax), %xmm1, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x20, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxbw %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x20, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxbw (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x23, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxwd %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x23, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxwd (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x25, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxdq %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x25, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxdq (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x30, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxbw %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x30, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxbw (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x33, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxwd %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x33, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxwd (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x35, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxdq %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x35, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxdq (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x22, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxbq %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x22, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxbq (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x32, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxbq %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x32, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxbq (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x21, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxbd %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x21, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxbd (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x24, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxwq %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x24, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovsxwq (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x31, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxbd %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x31, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxbd (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x34, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxwq %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x34, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpmovzxwq (%eax), %xmm2" + - + input: + bytes: [ 0xc5, 0xf9, 0xc5, 0xc2, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpextrw $7, %xmm2, %eax" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x15, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpextrw $7, %xmm2, (%eax)" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x16, 0xd0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpextrd $7, %xmm2, %eax" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x16, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpextrd $7, %xmm2, (%eax)" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x14, 0xd0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpextrb $7, %xmm2, %eax" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x14, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpextrb $7, %xmm2, (%eax)" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x17, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vextractps $7, %xmm2, (%eax)" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x17, 0xd0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vextractps $7, %xmm2, %eax" + - + input: + bytes: [ 0xc5, 0xe9, 0xc4, 0xe8, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpinsrw $7, %eax, %xmm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xe9, 0xc4, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpinsrw $7, (%eax), %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x20, 0xe8, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpinsrb $7, %eax, %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x20, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpinsrb $7, (%eax), %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x22, 0xe8, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpinsrd $7, %eax, %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x22, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpinsrd $7, (%eax), %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x21, 0xca, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vinsertps $7, %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x21, 0x08, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vinsertps $7, (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x17, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vptest %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x17, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vptest (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x2a, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovntdqa (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x37, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpgtq %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x37, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpgtq (%eax), %xmm5, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x62, 0xea, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpistrm $7, %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x62, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpistrm $7, (%eax), %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x60, 0xea, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpestrm $7, %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x60, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpestrm $7, (%eax), %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x63, 0xea, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpistri $7, %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x63, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpistri $7, (%eax), %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x61, 0xea, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpestri $7, %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x61, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpcmpestri $7, (%eax), %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0xdb, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesimc %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0xdb, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesimc (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xdc, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesenc %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xdc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesenc (%eax), %xmm5, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xdd, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesenclast %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xdd, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesenclast (%eax), %xmm5, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xde, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesdec %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xde, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesdec (%eax), %xmm5, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xdf, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesdeclast %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xdf, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaesdeclast (%eax), %xmm5, %xmm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0xdf, 0xea, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaeskeygenassist $7, %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0xdf, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaeskeygenassist $7, (%eax), %xmm5" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeq_uqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpngeps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpngtps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpfalseps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneq_oqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpgeps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpgtps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmptrueps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeq_osps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmplt_oqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmple_oqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunord_sps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneq_usps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnle_uqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpord_sps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeq_usps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnge_uqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpngt_uqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpfalse_osps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneq_osps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpge_oqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpgt_oqps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmptrue_usps %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0xc5, 0xfc, 0x28, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovaps (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x28, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovaps %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x29, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovaps %ymm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xfd, 0x28, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovapd (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfd, 0x28, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovapd %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xfd, 0x29, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovapd %ymm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xfc, 0x10, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovups (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x10, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovups %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x11, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovups %ymm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xfd, 0x10, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovupd (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfd, 0x10, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovupd %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xfd, 0x11, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovupd %ymm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xec, 0x15, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpckhps %ymm1, %ymm2, %ymm4" + - + input: + bytes: [ 0xc5, 0xed, 0x15, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpckhpd %ymm1, %ymm2, %ymm4" + - + input: + bytes: [ 0xc5, 0xec, 0x14, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpcklps %ymm1, %ymm2, %ymm4" + - + input: + bytes: [ 0xc5, 0xed, 0x14, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpcklpd %ymm1, %ymm2, %ymm4" + - + input: + bytes: [ 0xc5, 0xec, 0x15, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpckhps -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xed, 0x15, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpckhpd -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xec, 0x14, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpcklps -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xed, 0x14, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vunpcklpd -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xfd, 0xe7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovntdq %ymm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xfd, 0x2b, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovntpd %ymm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xfc, 0x2b, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovntps %ymm1, (%eax)" + - + input: + bytes: [ 0xc5, 0xf8, 0x50, 0xc2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovmskps %xmm2, %eax" + - + input: + bytes: [ 0xc5, 0xf9, 0x50, 0xc2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovmskpd %xmm2, %eax" + - + input: + bytes: [ 0xc5, 0xdc, 0x5f, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5f, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5d, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5d, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5c, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5c, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5e, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5e, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x58, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x58, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x59, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x59, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5f, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxps (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5f, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaxpd (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5d, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminps (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5d, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vminpd (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5c, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubps (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5c, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsubpd (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5e, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivps (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5e, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdivpd (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x58, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddps (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x58, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddpd (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x59, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulps (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x59, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmulpd (%eax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xfd, 0x51, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtpd %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xfd, 0x51, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtpd (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x51, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtps %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x51, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vsqrtps (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x52, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrsqrtps %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x52, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrsqrtps (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x53, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrcpps %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x53, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vrcpps (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xdc, 0x54, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x54, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xec, 0x54, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandps -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xed, 0x54, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandpd -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xdc, 0x56, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vorps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x56, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vorpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xec, 0x56, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vorps -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xed, 0x56, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vorpd -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xdc, 0x57, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vxorps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x57, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vxorpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xec, 0x57, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vxorps -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xed, 0x57, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vxorpd -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xdc, 0x55, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandnps %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x55, 0xf2 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandnpd %ymm2, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xec, 0x55, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandnps -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xed, 0x55, 0x6c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vandnpd -4(%ebx, %ecx, 8), %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xfc, 0x5a, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtps2pd %xmm3, %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x5a, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtps2pd (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfe, 0xe6, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2pd %xmm3, %ymm2" + - + input: + bytes: [ 0xc5, 0xfe, 0xe6, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2pd (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfc, 0x5b, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2ps %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xfc, 0x5b, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtdq2ps (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfd, 0x5b, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtps2dq %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xfd, 0x5b, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtps2dq (%eax), %ymm5" + - + input: + bytes: [ 0xc5, 0xfe, 0x5b, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttps2dq %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xfe, 0x5b, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttps2dq (%eax), %ymm5" + - + input: + bytes: [ 0xc5, 0xf9, 0xe6, 0xe9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttpd2dq %xmm1, %xmm5" + - + input: + bytes: [ 0xc5, 0xfd, 0xe6, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttpd2dq %ymm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xf9, 0xe6, 0xe9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttpd2dq %xmm1, %xmm5" + - + input: + bytes: [ 0xc5, 0xf9, 0xe6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttpd2dqx (%eax), %xmm1" + - + input: + bytes: [ 0xc5, 0xfd, 0xe6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttpd2dq %ymm2, %xmm1" + - + input: + bytes: [ 0xc5, 0xfd, 0xe6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvttpd2dqy (%eax), %xmm1" + - + input: + bytes: [ 0xc5, 0xfd, 0x5a, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2ps %ymm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xf9, 0x5a, 0xe9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2ps %xmm1, %xmm5" + - + input: + bytes: [ 0xc5, 0xf9, 0x5a, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2psx (%eax), %xmm1" + - + input: + bytes: [ 0xc5, 0xfd, 0x5a, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2ps %ymm2, %xmm1" + - + input: + bytes: [ 0xc5, 0xfd, 0x5a, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2psy (%eax), %xmm1" + - + input: + bytes: [ 0xc5, 0xff, 0xe6, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2dq %ymm2, %xmm5" + - + input: + bytes: [ 0xc5, 0xff, 0xe6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2dq %ymm2, %xmm1" + - + input: + bytes: [ 0xc5, 0xff, 0xe6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2dqy (%eax), %xmm1" + - + input: + bytes: [ 0xc5, 0xfb, 0xe6, 0xe9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2dq %xmm1, %xmm5" + - + input: + bytes: [ 0xc5, 0xfb, 0xe6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtpd2dqx (%eax), %xmm1" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpleps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnleps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqps -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpleps -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltps -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqps -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnleps -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltps -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xcc, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordps -4(%ebx, %ecx, 8), %ymm6, %ymm2" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordps -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqpd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmplepd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltpd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqpd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnlepd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltpd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordpd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordpd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeqpd -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmplepd -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpltpd -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneqpd -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnlepd -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnltpd -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xcd, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpordpd -4(%ebx, %ecx, 8), %ymm6, %ymm2" + - + input: + bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunordpd -4(%ebx, %ecx, 8), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeq_uqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpngeps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpngtps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpfalseps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneq_oqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpgeps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpgtps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmptrueps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeq_osps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmplt_oqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmple_oqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpunord_sps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneq_usps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnle_uqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpord_sps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpeq_usps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpnge_uqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpngt_uqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpfalse_osps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpneq_osps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpge_oqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmpgt_oqps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcmptrue_usps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xef, 0xd0, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsubps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xf7, 0xd0, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsubps (%eax), %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xed, 0xd0, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsubpd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xf5, 0xd0, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vaddsubpd (%eax), %ymm1, %ymm2" + - + input: + bytes: [ 0xc5, 0xef, 0x7c, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhaddps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xef, 0x7c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhaddps (%eax), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0x7c, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhaddpd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0x7c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhaddpd (%eax), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xef, 0x7d, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhsubps %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xef, 0x7d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhsubps (%eax), %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0x7d, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhsubpd %ymm1, %ymm2, %ymm3" + - + input: + bytes: [ 0xc5, 0xed, 0x7d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vhsubpd (%eax), %ymm2, %ymm3" + - + input: + bytes: [ 0xc4, 0xe3, 0x55, 0x0c, 0xca, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendps $3, %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x55, 0x0c, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendps $3, (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x55, 0x0d, 0xca, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendpd $3, %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x55, 0x0d, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendpd $3, (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x55, 0x40, 0xca, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdpps $3, %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x55, 0x40, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vdpps $3, (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x7d, 0x1a, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vbroadcastf128 (%eax), %ymm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x7d, 0x19, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vbroadcastsd (%eax), %ymm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x18, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vbroadcastss (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x7d, 0x18, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vbroadcastss (%eax), %ymm2" + - + input: + bytes: [ 0xc4, 0xe3, 0x6d, 0x18, 0xea, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vinsertf128 $7, %xmm2, %ymm2, %ymm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x6d, 0x18, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vinsertf128 $7, (%eax), %ymm2, %ymm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x19, 0xd2, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vextractf128 $7, %ymm2, %xmm2" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x19, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vextractf128 $7, %ymm2, (%eax)" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x2f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaskmovpd %xmm2, %xmm5, (%eax)" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x2f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaskmovpd %ymm2, %ymm5, (%eax)" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x2d, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaskmovpd (%eax), %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x6d, 0x2d, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaskmovpd (%eax), %ymm2, %ymm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x2e, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaskmovps %xmm2, %xmm5, (%eax)" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x2e, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaskmovps %ymm2, %ymm5, (%eax)" + - + input: + bytes: [ 0xc4, 0xe2, 0x69, 0x2c, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaskmovps (%eax), %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x6d, 0x2c, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmaskmovps (%eax), %ymm2, %ymm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x04, 0xe9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilps $7, %xmm1, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x04, 0xcd, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilps $7, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x04, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilps $7, (%eax), %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x04, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilps $7, (%eax), %ymm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x0c, 0xc9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilps %xmm1, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x0c, 0xc9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilps %ymm1, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x0c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilps (%eax), %xmm5, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x0c, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x05, 0xe9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilpd $7, %xmm1, %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x05, 0xcd, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilpd $7, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x05, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilpd $7, (%eax), %xmm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x05, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilpd $7, (%eax), %ymm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x0d, 0xc9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilpd %xmm1, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x0d, 0xc9 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilpd %ymm1, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x0d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilpd (%eax), %xmm5, %xmm3" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x0d, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpermilpd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x55, 0x06, 0xca, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vperm2f128 $7, %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x55, 0x06, 0x08, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vperm2f128 $7, (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc5, 0xfc, 0x77 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vzeroall" + - + input: + bytes: [ 0xc5, 0xf8, 0x77 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vzeroupper" + - + input: + bytes: [ 0xc5, 0xfb, 0x2d, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsd2si %xmm4, %ecx" + - + input: + bytes: [ 0xc5, 0xfb, 0x2d, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsd2si (%ecx), %ecx" + - + input: + bytes: [ 0xc5, 0xfb, 0x2d, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsd2si %xmm4, %ecx" + - + input: + bytes: [ 0xc5, 0xfb, 0x2d, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsd2si (%ecx), %ecx" + - + input: + bytes: [ 0xc5, 0xfb, 0x2a, 0x7d, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsi2sdl (%ebp), %xmm0, %xmm7" + - + input: + bytes: [ 0xc5, 0xfb, 0x2a, 0x3c, 0x24 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsi2sdl (%esp), %xmm0, %xmm7" + - + input: + bytes: [ 0xc5, 0xfb, 0x2a, 0x7d, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsi2sdl (%ebp), %xmm0, %xmm7" + - + input: + bytes: [ 0xc5, 0xfb, 0x2a, 0x3c, 0x24 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vcvtsi2sdl (%esp), %xmm0, %xmm7" + - + input: + bytes: [ 0xc5, 0xff, 0xf0, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vlddqu (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xff, 0x12, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovddup %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xff, 0x12, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovddup (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfd, 0x6f, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovdqa %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xfd, 0x7f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovdqa %ymm2, (%eax)" + - + input: + bytes: [ 0xc5, 0xfd, 0x6f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovdqa (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfe, 0x6f, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovdqu %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xfe, 0x7f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovdqu %ymm2, (%eax)" + - + input: + bytes: [ 0xc5, 0xfe, 0x6f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovdqu (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfe, 0x16, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovshdup %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xfe, 0x16, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovshdup (%eax), %ymm2" + - + input: + bytes: [ 0xc5, 0xfe, 0x12, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovsldup %ymm2, %ymm5" + - + input: + bytes: [ 0xc5, 0xfe, 0x12, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vmovsldup (%eax), %ymm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x7d, 0x17, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vptest %ymm2, %ymm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x7d, 0x17, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vptest (%eax), %ymm2" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x09, 0xcd, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundpd $7, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x09, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundpd $7, (%eax), %ymm5" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x08, 0xcd, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundps $7, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x08, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vroundps $7, (%eax), %ymm5" + - + input: + bytes: [ 0xc5, 0xd5, 0xc6, 0xca, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vshufpd $7, %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc5, 0xd5, 0xc6, 0x08, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vshufpd $7, (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc5, 0xd4, 0xc6, 0xca, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vshufps $7, %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc5, 0xd4, 0xc6, 0x08, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vshufps $7, (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x0f, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vtestpd %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x7d, 0x0f, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vtestpd %ymm2, %ymm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x0f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vtestpd (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x7d, 0x0f, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vtestpd (%eax), %ymm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x0e, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vtestps %xmm2, %xmm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x7d, 0x0e, 0xea ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vtestps %ymm2, %ymm5" + - + input: + bytes: [ 0xc4, 0xe2, 0x79, 0x0e, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vtestps (%eax), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0x7d, 0x0e, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vtestps (%eax), %ymm2" + - + input: + bytes: [ 0xc4, 0xe3, 0x75, 0x4b, 0x94, 0x20, 0xad, 0xde, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vblendvpd %ymm0, 0xdead(%eax), %ymm1, %ymm2" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x44, 0xca, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpclmulqdq $17, %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0x51, 0x44, 0x18, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vpclmulqdq $17, (%eax), %xmm5, %xmm3" diff --git a/tests/MC/X86/x86-32-fma3.s.yaml b/tests/MC/X86/x86-32-fma3.s.yaml new file mode 100644 index 0000000000..52f78ef431 --- /dev/null +++ b/tests/MC/X86/x86-32-fma3.s.yaml @@ -0,0 +1,1504 @@ +test_cases: + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x98, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x98, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x98, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x98, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xa8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xa8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xa8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xa8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xb8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xb8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xb8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xb8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x98, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x98, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x98, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x98, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xa8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xa8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xa8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xa8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xb8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xb8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xb8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xb8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x98, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x98, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x98, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x98, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xa8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xa8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xa8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xa8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xb8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xb8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xb8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xb8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x96, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub132pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x96, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub132pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x96, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub132ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x96, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub132ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xa6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub213pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xa6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub213pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xa6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub213ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xa6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub213ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xb6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub231pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xb6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub231pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xb6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub231ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xb6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub231ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x97, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd132pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x97, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd132pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x97, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd132ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x97, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd132ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xa7, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd213pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xa7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd213pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xa7, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd213ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xa7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd213ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xb7, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd231pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xb7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd231pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xb7, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd231ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xb7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd231ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x9a, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub132pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x9a, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub132pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x9a, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub132ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x9a, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub132ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xaa, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub213pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xaa, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub213pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xaa, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub213ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xaa, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub213ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xba, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub231pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xba, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub231pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xba, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub231ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xba, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub231ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x9c, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd132pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x9c, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd132pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x9c, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd132ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x9c, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd132ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xac, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd213pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xac, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd213pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xac, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd213ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xac, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd213ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xbc, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd231pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xbc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd231pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xbc, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd231ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xbc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd231ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x9e, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub132pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0x9e, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub132pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x9e, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub132ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0x9e, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub132ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xae, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub213pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xae, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub213pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xae, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub213ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xae, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub213ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xbe, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub231pd %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd1, 0xbe, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub231pd (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xbe, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub231ps %xmm2, %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x51, 0xbe, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub231ps (%eax), %xmm5, %xmm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x98, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x98, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x98, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x98, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd132ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xa8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xa8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xa8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xa8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd213ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xb8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xb8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xb8, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xb8, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmadd231ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x96, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub132pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x96, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub132pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x96, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub132ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x96, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub132ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xa6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub213pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xa6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub213pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xa6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub213ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xa6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub213ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xb6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub231pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xb6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub231pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xb6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub231ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xb6, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmaddsub231ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x97, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd132pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x97, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd132pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x97, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd132ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x97, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd132ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xa7, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd213pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xa7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd213pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xa7, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd213ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xa7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd213ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xb7, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd231pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xb7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd231pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xb7, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd231ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xb7, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsubadd231ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x9a, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub132pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x9a, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub132pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x9a, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub132ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x9a, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub132ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xaa, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub213pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xaa, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub213pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xaa, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub213ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xaa, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub213ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xba, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub231pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xba, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub231pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xba, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub231ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xba, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfmsub231ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x9c, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd132pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x9c, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd132ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x9c, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd132ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xac, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd213pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xac, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd213pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xac, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd213ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xac, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd213ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xbc, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd231pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xbc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd231pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xbc, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd231ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xbc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmadd231ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x9e, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub132pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0x9e, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub132pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x9e, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub132ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0x9e, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub132ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xae, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub213pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xae, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub213pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xae, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub213ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xae, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub213ps (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xbe, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub231pd %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0xd5, 0xbe, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub231pd (%eax), %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xbe, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub231ps %ymm2, %ymm5, %ymm1" + - + input: + bytes: [ 0xc4, 0xe2, 0x55, 0xbe, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "vfnmsub231ps (%eax), %ymm5, %ymm1" diff --git a/tests/MC/X86/x86-32-ms-inline-asm.s.yaml b/tests/MC/X86/x86-32-ms-inline-asm.s.yaml new file mode 100644 index 0000000000..c4a35a5cbb --- /dev/null +++ b/tests/MC/X86/x86-32-ms-inline-asm.s.yaml @@ -0,0 +1,235 @@ +test_cases: + - + input: + bytes: [ 0x8b, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl (%ebx), %eax" + - + input: + bytes: [ 0x89, 0x4b, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl %ecx, 4(%ebx)" + - + input: + bytes: [ 0x8b, 0x04, 0x85, 0x04, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(, %eax, 4), %eax" + - + input: + bytes: [ 0x8b, 0x04, 0x85, 0x04, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(, %eax, 4), %eax" + - + input: + bytes: [ 0x8b, 0x04, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl (%esi, %eax), %eax" + - + input: + bytes: [ 0x8b, 0x04, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl (%esi, %eax), %eax" + - + input: + bytes: [ 0x8b, 0x04, 0x86 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl (%esi, %eax, 4), %eax" + - + input: + bytes: [ 0x8b, 0x04, 0x86 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl (%esi, %eax, 4), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x06, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(%esi, %eax), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x06, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(%esi, %eax), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x06, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(%esi, %eax), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x06, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(%esi, %eax), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x46, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(%esi, %eax, 2), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x46, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(%esi, %eax, 2), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x46, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(%esi, %eax, 2), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x46, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 4(%esi, %eax, 2), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x46, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 8(%esi, %eax, 2), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x46, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 8(%esi, %eax, 2), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x46, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 8(%esi, %eax, 2), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x46, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 8(%esi, %eax, 2), %eax" + - + input: + bytes: [ 0x8b, 0x44, 0x46, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "movl 16(%esi, %eax, 2), %eax" + - + input: + bytes: [ 0x0f, 0x18, 0x40, 0x40 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "prefetchnta 64(%eax)" + - + input: + bytes: [ 0x60 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pushal" + - + input: + bytes: [ 0x61 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "popal" + - + input: + bytes: [ 0x60 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "pushal" + - + input: + bytes: [ 0x61 ] + arch: "CS_ARCH_X86" + options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ] + expected: + insns: + - + asm_text: "popal" diff --git a/tests/MC/X86/x86_64-avx-clmul-encoding.s.yaml b/tests/MC/X86/x86_64-avx-clmul-encoding.s.yaml new file mode 100644 index 0000000000..c8ca1c4e0e --- /dev/null +++ b/tests/MC/X86/x86_64-avx-clmul-encoding.s.yaml @@ -0,0 +1,19 @@ +test_cases: + - + input: + bytes: [ 0xc4, 0x43, 0x29, 0x44, 0xdc, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpclmulqdq $17, %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x63, 0x29, 0x44, 0x28, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpclmulqdq $17, (%rax), %xmm10, %xmm13" diff --git a/tests/MC/X86/x86_64-avx-encoding.s.yaml b/tests/MC/X86/x86_64-avx-encoding.s.yaml new file mode 100644 index 0000000000..50c2e4f061 --- /dev/null +++ b/tests/MC/X86/x86_64-avx-encoding.s.yaml @@ -0,0 +1,9514 @@ +test_cases: + - + input: + bytes: [ 0xc4, 0x41, 0x32, 0x58, 0xd0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddss %xmm8, %xmm9, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x32, 0x59, 0xd0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulss %xmm8, %xmm9, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x32, 0x5c, 0xd0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubss %xmm8, %xmm9, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x32, 0x5e, 0xd0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivss %xmm8, %xmm9, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x33, 0x58, 0xd0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsd %xmm8, %xmm9, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x33, 0x59, 0xd0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulsd %xmm8, %xmm9, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x33, 0x5c, 0xd0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubsd %xmm8, %xmm9, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x33, 0x5e, 0xd0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivsd %xmm8, %xmm9, %xmm10" + - + input: + bytes: [ 0xc5, 0x2a, 0x58, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddss -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x2a, 0x5c, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubss -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x2a, 0x59, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulss -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x2a, 0x5e, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivss -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x2b, 0x58, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsd -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x2b, 0x5c, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubsd -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x2b, 0x59, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulsd -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x2b, 0x5e, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivsd -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x20, 0x58, 0xfa ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddps %xmm10, %xmm11, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x20, 0x5c, 0xfa ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubps %xmm10, %xmm11, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x20, 0x59, 0xfa ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulps %xmm10, %xmm11, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x20, 0x5e, 0xfa ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivps %xmm10, %xmm11, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x21, 0x58, 0xfa ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddpd %xmm10, %xmm11, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x21, 0x5c, 0xfa ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubpd %xmm10, %xmm11, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x21, 0x59, 0xfa ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulpd %xmm10, %xmm11, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x21, 0x5e, 0xfa ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivpd %xmm10, %xmm11, %xmm15" + - + input: + bytes: [ 0xc5, 0x28, 0x58, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddps -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x28, 0x5c, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubps -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x28, 0x59, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulps -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x28, 0x5e, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivps -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x29, 0x58, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddpd -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x29, 0x5c, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubpd -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x29, 0x59, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulpd -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc5, 0x29, 0x5e, 0x5c, 0xd9, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivpd -4(%rcx, %rbx, 8), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x0a, 0x5f, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxss %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x0b, 0x5f, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxsd %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x0a, 0x5d, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminss %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x0b, 0x5d, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminsd %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc5, 0x1a, 0x5f, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxss -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x1b, 0x5f, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxsd -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x1a, 0x5d, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminss -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x1b, 0x5d, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminsd -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x08, 0x5f, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxps %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x09, 0x5f, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxpd %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x08, 0x5d, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminps %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x09, 0x5d, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminpd %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc5, 0x18, 0x5f, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxps -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x19, 0x5f, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxpd -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x18, 0x5d, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminps -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x19, 0x5d, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminpd -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x08, 0x54, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandps %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x09, 0x54, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandpd %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc5, 0x18, 0x54, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandps -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x19, 0x54, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandpd -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x08, 0x56, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vorps %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x09, 0x56, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vorpd %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc5, 0x18, 0x56, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vorps -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x19, 0x56, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vorpd -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x08, 0x57, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vxorps %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x09, 0x57, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vxorpd %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc5, 0x18, 0x57, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vxorps -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x19, 0x57, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vxorpd -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x08, 0x55, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandnps %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x09, 0x55, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandnpd %xmm10, %xmm14, %xmm12" + - + input: + bytes: [ 0xc5, 0x18, 0x55, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandnps -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x19, 0x55, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandnpd -4(%rbx, %rcx, 8), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x7a, 0x10, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovss -4(%rbx, %rcx, 8), %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x2a, 0x10, 0xfe ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovss %xmm14, %xmm10, %xmm15" + - + input: + bytes: [ 0xc5, 0x7b, 0x10, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovsd -4(%rbx, %rcx, 8), %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x2b, 0x10, 0xfe ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovsd %xmm14, %xmm10, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0x15, 0xef ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpckhps %xmm15, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x15, 0xef ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpckhpd %xmm15, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0x14, 0xef ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpcklps %xmm15, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x14, 0xef ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpcklpd %xmm15, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0x15, 0x7c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpckhps -4(%rbx, %rcx, 8), %xmm12, %xmm15" + - + input: + bytes: [ 0xc5, 0x19, 0x15, 0x7c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpckhpd -4(%rbx, %rcx, 8), %xmm12, %xmm15" + - + input: + bytes: [ 0xc5, 0x18, 0x14, 0x7c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpcklps -4(%rbx, %rcx, 8), %xmm12, %xmm15" + - + input: + bytes: [ 0xc5, 0x19, 0x14, 0x7c, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpcklpd -4(%rbx, %rcx, 8), %xmm12, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xfa, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqps %xmm10, %xmm12, %xmm15" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x38, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqps (%rax), %xmm12, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xfa, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordps %xmm10, %xmm12, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xfa, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqpd %xmm10, %xmm12, %xmm15" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x38, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqpd (%rax), %xmm12, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xfa, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordpd %xmm10, %xmm12, %xmm15" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc6, 0xeb, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vshufps $8, %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc6, 0x6c, 0xcb, 0xfc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vshufps $8, -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc6, 0xeb, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vshufpd $8, %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc6, 0x6c, 0xcb, 0xfc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vshufpd $8, -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpleps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnleps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpleps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnleps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xc8, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordps -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplepd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlepd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplepd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlepd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xc9, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordpd -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpless %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnless %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpless -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnless -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xca, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordss -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplesd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlesd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplesd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlesd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xcb, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordsd -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngeps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalseps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgeps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrueps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_osps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_sps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_usps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_sps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_usps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_osps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_osps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_usps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngeps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalseps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgeps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xc8, 0xc2, 0x54, 0xcb, 0xfc, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtps -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrueps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_osps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_sps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_usps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xc8, 0xc2, 0x54, 0xcb, 0xfc, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqps -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_sps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_usps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_osps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_osps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xc8, 0xc2, 0x54, 0xcb, 0xfc, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqps -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_usps -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngepd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalsepd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgepd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptruepd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_ospd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_spd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_uspd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_spd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uspd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_ospd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_ospd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_uspd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngepd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalsepd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgepd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xc9, 0xc2, 0x54, 0xcb, 0xfc, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtpd -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptruepd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_ospd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_spd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_uspd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xc9, 0xc2, 0x54, 0xcb, 0xfc, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqpd -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_spd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uspd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_ospd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_ospd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xc9, 0xc2, 0x54, 0xcb, 0xfc, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqpd -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_uspd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngess %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalsess %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgess %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptruess %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_osss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_sss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_usss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_sss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_usss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_osss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_osss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_usss %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngess -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalsess -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgess -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xca, 0xc2, 0x54, 0xcb, 0xfc, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtss -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptruess -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_osss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_sss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_usss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xca, 0xc2, 0x54, 0xcb, 0xfc, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqss -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_sss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_usss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_osss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_osss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xca, 0xc2, 0x54, 0xcb, 0xfc, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqss -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_usss -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngesd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalsesd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgesd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptruesd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_ossd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_ssd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_ussd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_ssd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_ussd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_ossd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_ossd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqsd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_ussd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngesd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalsesd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgesd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xcb, 0xc2, 0x54, 0xcb, 0xfc, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtsd -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptruesd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_ossd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_ssd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_ussd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xcb, 0xc2, 0x54, 0xcb, 0xfc, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqsd -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_ssd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_ussd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_ossd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_ossd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0xcb, 0xc2, 0x54, 0xcb, 0xfc, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqsd -4(%rbx, %rcx, 8), %xmm6, %xmm2" + - + input: + bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_ussd -4(%rbx, %rcx, 8), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x2e, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vucomiss %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x78, 0x2e, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vucomiss (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x2f, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcomiss %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x78, 0x2f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcomiss (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0x2e, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vucomisd %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x79, 0x2e, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vucomisd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0x2f, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcomisd %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x79, 0x2f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcomisd (%rax), %xmm12" + - + input: + bytes: [ 0xc5, 0xfa, 0x2c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttss2si (%rcx), %eax" + - + input: + bytes: [ 0xc5, 0x22, 0x2a, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2ssl (%rax), %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x22, 0x2a, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2ssl (%rax), %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0xfb, 0x2c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttsd2si (%rcx), %eax" + - + input: + bytes: [ 0xc5, 0x23, 0x2a, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2sdl (%rax), %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x23, 0x2a, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2sdl (%rax), %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x78, 0x28, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x28, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x78, 0x29, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x79, 0x28, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovapd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0x28, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovapd %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x79, 0x29, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovapd %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x78, 0x10, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x10, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x78, 0x11, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x79, 0x10, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovupd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0x10, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovupd %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x79, 0x11, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovupd %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x78, 0x13, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovlps %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x18, 0x12, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovlps (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x79, 0x13, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovlpd %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x19, 0x12, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovlpd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x78, 0x17, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovhps %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x18, 0x16, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovhps (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x79, 0x17, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovhpd %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x19, 0x16, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovhpd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0x16, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovlhps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0x12, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovhlps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x7a, 0x2d, 0xc3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtss2si %xmm11, %eax" + - + input: + bytes: [ 0xc5, 0xfa, 0x2d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtss2si (%rax), %ebx" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x5b, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2ps %xmm10, %xmm12" + - + input: + bytes: [ 0xc5, 0x78, 0x5b, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2ps (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x13, 0x5a, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsd2ss %xmm12, %xmm13, %xmm10" + - + input: + bytes: [ 0xc5, 0x13, 0x5a, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsd2ss (%rax), %xmm13, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0x5b, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtps2dq %xmm12, %xmm11" + - + input: + bytes: [ 0xc5, 0x79, 0x5b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtps2dq (%rax), %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x12, 0x5a, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtss2sd %xmm12, %xmm13, %xmm10" + - + input: + bytes: [ 0xc5, 0x12, 0x5a, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtss2sd (%rax), %xmm13, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x5b, 0xd5 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2ps %xmm13, %xmm10" + - + input: + bytes: [ 0xc5, 0x78, 0x5b, 0x29 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2ps (%rcx), %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x7a, 0x5b, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttps2dq %xmm12, %xmm11" + - + input: + bytes: [ 0xc5, 0x7a, 0x5b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttps2dq (%rax), %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x5a, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtps2pd %xmm12, %xmm11" + - + input: + bytes: [ 0xc5, 0x78, 0x5a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtps2pd (%rax), %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0x5a, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2ps %xmm12, %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0x51, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtpd %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x79, 0x51, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtpd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x51, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtps %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x78, 0x51, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtps (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0x51, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtsd %xmm11, %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x1b, 0x51, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtsd (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0x51, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtss %xmm11, %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x1a, 0x51, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtss (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x52, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrsqrtps %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x78, 0x52, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrsqrtps (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0x52, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrsqrtss %xmm11, %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x1a, 0x52, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrsqrtss (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x78, 0x53, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrcpps %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x78, 0x53, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrcpps (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x1a, 0x53, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrcpss %xmm11, %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x1a, 0x53, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrcpss (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x79, 0xe7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovntdq %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x79, 0x2b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovntpd %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x78, 0x2b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovntps %xmm11, (%rax)" + - + input: + bytes: [ 0xc5, 0xf8, 0xae, 0x15, 0xfc, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vldmxcsr -4(%rip)" + - + input: + bytes: [ 0xc5, 0xf8, 0xae, 0x5c, 0x24, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vstmxcsr -4(%rsp)" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xf8, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xf8, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xf9, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xf9, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xfa, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xfa, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xfb, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubq %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xfb, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xe8, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubsb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xe8, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubsb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xe9, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubsw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xe9, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubsw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xd8, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubusb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xd8, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubusb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xd9, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubusw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xd9, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsubusw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xfc, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xfc, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xfd, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xfd, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xfe, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xfe, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xd4, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddq %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xd4, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xec, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddsb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xec, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddsb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xed, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddsw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xed, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddsw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xdc, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddusb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xdc, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddusb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xdd, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddusw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xdd, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpaddusw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xe4, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmulhuw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xe4, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmulhuw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xe5, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmulhw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xe5, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmulhw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xd5, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmullw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xd5, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmullw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xf4, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmuludq %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xf4, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmuludq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xe0, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpavgb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xe0, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpavgb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xe3, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpavgw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xe3, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpavgw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xea, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminsw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xea, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminsw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xda, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminub %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xda, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminub (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xee, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxsw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xee, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxsw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xde, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxub %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xde, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxub (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xf6, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsadbw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xf6, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsadbw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xf1, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsllw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xf1, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsllw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xf2, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpslld %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xf2, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpslld (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xf3, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsllq %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xf3, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsllq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xe1, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsraw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xe1, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsraw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xe2, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrad %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xe2, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrad (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xd1, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrlw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xd1, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrlw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xd2, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrld %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xd2, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrld (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xd3, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrlq %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xd3, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrlq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x72, 0xf4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpslld $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x73, 0xfc, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpslldq $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x73, 0xf4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsllq $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x71, 0xf4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsllw $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x72, 0xe4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrad $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x71, 0xe4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsraw $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x72, 0xd4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrld $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x73, 0xdc, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrldq $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x73, 0xd4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrlq $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x71, 0xd4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsrlw $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x11, 0x72, 0xf4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpslld $10, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xdb, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpand %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xdb, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpand (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xeb, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpor %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xeb, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpor (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xef, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpxor %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xef, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpxor (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xdf, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpandn %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xdf, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpandn (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x74, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpeqb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x74, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpeqb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x75, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpeqw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x75, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpeqw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x76, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpeqd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x76, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpeqd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x64, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpgtb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x64, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpgtb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x65, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpgtw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x65, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpgtw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x66, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpgtd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x66, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpgtd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x63, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpacksswb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x63, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpacksswb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x6b, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpackssdw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x6b, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpackssdw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x67, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpackuswb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x67, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpackuswb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0x70, 0xec, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshufd $4, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x79, 0x70, 0x28, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshufd $4, (%rax), %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x7a, 0x70, 0xec, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshufhw $4, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x7a, 0x70, 0x28, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshufhw $4, (%rax), %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x7b, 0x70, 0xec, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshuflw $4, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x7b, 0x70, 0x28, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshuflw $4, (%rax), %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x60, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpcklbw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x60, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpcklbw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x61, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpcklwd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x61, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpcklwd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x62, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckldq %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x62, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckldq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x6c, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpcklqdq %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x6c, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpcklqdq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x68, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckhbw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x68, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckhbw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x69, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckhwd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x69, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckhwd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x6a, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckhdq %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x6a, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckhdq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x6d, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckhqdq %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x6d, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpunpckhqdq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc4, 0xe8, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrw $7, %eax, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0xc4, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrw $7, (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0xc1, 0x79, 0xc5, 0xc4, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrw $7, %xmm12, %eax" + - + input: + bytes: [ 0xc4, 0xc1, 0x79, 0xd7, 0xc4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovmskb %xmm12, %eax" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0xf7, 0xfe ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaskmovdqu %xmm14, %xmm15" + - + input: + bytes: [ 0xc5, 0x79, 0x6e, 0xf0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovd %eax, %xmm14" + - + input: + bytes: [ 0xc5, 0x79, 0x6e, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovd (%rax), %xmm14" + - + input: + bytes: [ 0xc5, 0x79, 0x7e, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovd %xmm14, (%rax)" + - + input: + bytes: [ 0xc4, 0x61, 0xf9, 0x6e, 0xf0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovq %rax, %xmm14" + - + input: + bytes: [ 0xc4, 0xe1, 0xf9, 0x7e, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovq %xmm0, %rax" + - + input: + bytes: [ 0xc5, 0x79, 0xd6, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovq %xmm14, (%rax)" + - + input: + bytes: [ 0xc4, 0x41, 0x7a, 0x7e, 0xe6 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovq %xmm14, %xmm12" + - + input: + bytes: [ 0xc5, 0x7a, 0x7e, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovq (%rax), %xmm14" + - + input: + bytes: [ 0xc4, 0x61, 0xf9, 0x6e, 0xf0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovq %rax, %xmm14" + - + input: + bytes: [ 0xc4, 0x61, 0xf9, 0x7e, 0xf0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovq %xmm14, %rax" + - + input: + bytes: [ 0xc4, 0x41, 0x7b, 0xe6, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2dq %xmm11, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7a, 0xe6, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2pd %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x7a, 0xe6, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2pd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7a, 0x16, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovshdup %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x7a, 0x16, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovshdup (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7a, 0x12, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovsldup %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x7a, 0x12, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovsldup (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7b, 0x12, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovddup %xmm11, %xmm12" + - + input: + bytes: [ 0xc5, 0x7b, 0x12, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovddup (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0xd0, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsubps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x23, 0xd0, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsubps (%rax), %xmm11, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0xd0, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsubpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x21, 0xd0, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsubpd (%rax), %xmm11, %xmm12" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0x7c, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhaddps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0x7c, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhaddps (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x7c, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhaddpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x7c, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhaddpd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1b, 0x7d, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhsubps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x1b, 0x7d, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhsubps (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x19, 0x7d, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhsubpd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x19, 0x7d, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhsubpd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x1c, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpabsb %xmm11, %xmm12" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x1c, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpabsb (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x1d, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpabsw %xmm11, %xmm12" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x1d, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpabsw (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x1e, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpabsd %xmm11, %xmm12" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x1e, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpabsd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x01, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x01, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x02, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x02, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x03, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddsw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x03, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddsw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x05, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x05, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x06, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x06, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x07, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubsw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x07, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubsw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x04, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaddubsw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x04, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaddubsw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x00, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshufb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x00, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshufb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x08, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsignb %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x08, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsignb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x09, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsignw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x09, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsignw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x0a, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsignd %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x0a, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpsignd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0x0b, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmulhrsw %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x0b, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmulhrsw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x43, 0x19, 0x0f, 0xeb, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpalignr $7, %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x19, 0x0f, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpalignr $7, (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x43, 0x19, 0x0b, 0xeb, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundsd $7, %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x19, 0x0b, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundsd $7, (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x43, 0x19, 0x0a, 0xeb, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundss $7, %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x19, 0x0a, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundss $7, (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0x09, 0xec, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundpd $7, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x09, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundpd $7, (%rax), %xmm13" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0x08, 0xec, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundps $7, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x08, 0x28, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundps $7, (%rax), %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x41, 0xec ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphminposuw %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x41, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphminposuw (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x2b, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpackusdw %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x2b, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpackusdw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x29, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpeqq %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x29, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpeqq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x38, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminsb %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x38, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminsb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x39, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminsd %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x39, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminsd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x3b, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminud %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x3b, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminud (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x3a, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminuw %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x3a, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpminuw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x3c, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxsb %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x3c, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxsb (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x3d, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxsd %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x3d, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxsd (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x3f, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxud %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x3f, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxud (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x3e, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxuw %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x3e, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmaxuw (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x11, 0x28, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmuldq %xmm12, %xmm13, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x28, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmuldq (%rax), %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x51, 0x40, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmulld %xmm12, %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x51, 0x40, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmulld (%rax), %xmm5, %xmm13" + - + input: + bytes: [ 0xc4, 0x43, 0x51, 0x0c, 0xdc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendps $3, %xmm12, %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x63, 0x51, 0x0c, 0x18, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendps $3, (%rax), %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x43, 0x51, 0x0d, 0xdc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendpd $3, %xmm12, %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x63, 0x51, 0x0d, 0x18, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendpd $3, (%rax), %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x43, 0x51, 0x0e, 0xdc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpblendw $3, %xmm12, %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x63, 0x51, 0x0e, 0x18, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpblendw $3, (%rax), %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x43, 0x51, 0x42, 0xdc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmpsadbw $3, %xmm12, %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x63, 0x51, 0x42, 0x18, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmpsadbw $3, (%rax), %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x43, 0x51, 0x40, 0xdc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdpps $3, %xmm12, %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x63, 0x51, 0x40, 0x18, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdpps $3, (%rax), %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x43, 0x51, 0x41, 0xdc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdppd $3, %xmm12, %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x63, 0x51, 0x41, 0x18, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdppd $3, (%rax), %xmm5, %xmm11" + - + input: + bytes: [ 0xc4, 0x63, 0x21, 0x4b, 0xed, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendvpd %xmm12, %xmm5, %xmm11, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x21, 0x4b, 0x28, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendvpd %xmm12, (%rax), %xmm11, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x21, 0x4a, 0xed, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendvps %xmm12, %xmm5, %xmm11, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x21, 0x4a, 0x28, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendvps %xmm12, (%rax), %xmm11, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x21, 0x4c, 0xed, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpblendvb %xmm12, %xmm5, %xmm11, %xmm13" + - + input: + bytes: [ 0xc4, 0x63, 0x21, 0x4c, 0x28, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpblendvb %xmm12, (%rax), %xmm11, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x20, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxbw %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x20, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxbw (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x23, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxwd %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x23, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxwd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x25, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxdq %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x25, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxdq (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x30, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxbw %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x30, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxbw (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x33, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxwd %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x33, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxwd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x35, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxdq %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x35, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxdq (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x22, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxbq %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x22, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxbq (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x32, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxbq %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x32, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxbq (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x21, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxbd %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x21, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxbd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x24, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxwq %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x24, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovsxwq (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x31, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxbd %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x31, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxbd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x34, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxwq %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x34, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovzxwq (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0xc1, 0x79, 0xc5, 0xc4, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrw $7, %xmm12, %eax" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x15, 0x20, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrw $7, %xmm12, (%rax)" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x16, 0xe0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrd $7, %xmm12, %eax" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x16, 0x20, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrd $7, %xmm12, (%rax)" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x14, 0xe0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrb $7, %xmm12, %eax" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x14, 0x20, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrb $7, %xmm12, (%rax)" + - + input: + bytes: [ 0xc4, 0x63, 0xf9, 0x16, 0xe1, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrq $7, %xmm12, %rcx" + - + input: + bytes: [ 0xc4, 0x63, 0xf9, 0x16, 0x21, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrq $7, %xmm12, (%rcx)" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x17, 0x20, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vextractps $7, %xmm12, (%rax)" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x17, 0xe0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vextractps $7, %xmm12, %eax" + - + input: + bytes: [ 0xc5, 0x19, 0xc4, 0xd0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrw $7, %eax, %xmm12, %xmm10" + - + input: + bytes: [ 0xc5, 0x19, 0xc4, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrw $7, (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x19, 0x20, 0xd0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrb $7, %eax, %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x19, 0x20, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrb $7, (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x19, 0x22, 0xd0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrd $7, %eax, %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x19, 0x22, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrd $7, (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x99, 0x22, 0xd0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrq $7, %rax, %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x99, 0x22, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrq $7, (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x43, 0x29, 0x21, 0xdc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vinsertps $7, %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x63, 0x29, 0x21, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vinsertps $7, (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x17, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vptest %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x17, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vptest (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x2a, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovntdqa (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x37, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpgtq %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x37, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpgtq (%rax), %xmm10, %xmm13" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0x62, 0xd4, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpistrm $7, %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x62, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpistrm $7, (%rax), %xmm10" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0x60, 0xd4, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpestrm $7, %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x60, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpestrm $7, (%rax), %xmm10" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0x63, 0xd4, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpistri $7, %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x63, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpistri $7, (%rax), %xmm10" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0x61, 0xd4, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpestri $7, %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x61, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmpestri $7, (%rax), %xmm10" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0xdb, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesimc %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0xdb, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesimc (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xdc, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesenc %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xdc, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesenc (%rax), %xmm10, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xdd, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesenclast %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xdd, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesenclast (%rax), %xmm10, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xde, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesdec %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xde, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesdec (%rax), %xmm10, %xmm13" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xdf, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesdeclast %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xdf, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaesdeclast (%rax), %xmm10, %xmm13" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0xdf, 0xd4, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaeskeygenassist $7, %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0xdf, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaeskeygenassist $7, (%rax), %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngeps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalseps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgeps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrueps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_osps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_sps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_usps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_sps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_usps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_osps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_osps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_usps %xmm11, %xmm12, %xmm13" + - + input: + bytes: [ 0xc5, 0x7c, 0x28, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7c, 0x28, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %ymm11, %ymm12" + - + input: + bytes: [ 0xc5, 0x7c, 0x29, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %ymm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x7d, 0x28, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovapd (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7d, 0x28, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovapd %ymm11, %ymm12" + - + input: + bytes: [ 0xc5, 0x7d, 0x29, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovapd %ymm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x7c, 0x10, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7c, 0x10, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups %ymm11, %ymm12" + - + input: + bytes: [ 0xc5, 0x7c, 0x11, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups %ymm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x7d, 0x10, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovupd (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7d, 0x10, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovupd %ymm11, %ymm12" + - + input: + bytes: [ 0xc5, 0x7d, 0x11, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovupd %ymm11, (%rax)" + - + input: + bytes: [ 0xc4, 0xc1, 0x1c, 0x15, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpckhps %ymm11, %ymm12, %ymm4" + - + input: + bytes: [ 0xc4, 0xc1, 0x1d, 0x15, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpckhpd %ymm11, %ymm12, %ymm4" + - + input: + bytes: [ 0xc4, 0xc1, 0x1c, 0x14, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpcklps %ymm11, %ymm12, %ymm4" + - + input: + bytes: [ 0xc4, 0xc1, 0x1d, 0x14, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpcklpd %ymm11, %ymm12, %ymm4" + - + input: + bytes: [ 0xc5, 0x1c, 0x15, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpckhps -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x1d, 0x15, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpckhpd -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x1c, 0x14, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpcklps -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x1d, 0x14, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vunpcklpd -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x7d, 0xe7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovntdq %ymm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x7d, 0x2b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovntpd %ymm11, (%rax)" + - + input: + bytes: [ 0xc5, 0x7c, 0x2b, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovntps %ymm11, (%rax)" + - + input: + bytes: [ 0xc4, 0xc1, 0x78, 0x50, 0xc4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovmskps %xmm12, %eax" + - + input: + bytes: [ 0xc4, 0xc1, 0x79, 0x50, 0xc4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovmskpd %xmm12, %eax" + - + input: + bytes: [ 0xc4, 0xc1, 0x5c, 0x5f, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxps %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5d, 0x5f, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxpd %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5c, 0x5d, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminps %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5d, 0x5d, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminpd %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5c, 0x5c, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubps %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5d, 0x5c, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubpd %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5c, 0x5e, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivps %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5d, 0x5e, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivpd %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5c, 0x58, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddps %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5d, 0x58, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddpd %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5c, 0x59, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulps %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xc1, 0x5d, 0x59, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulpd %ymm12, %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5f, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxps (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5f, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaxpd (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5d, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminps (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5d, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vminpd (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5c, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubps (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5c, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsubpd (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x5e, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivps (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x5e, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdivpd (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x58, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddps (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x58, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddpd (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdc, 0x59, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulps (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc5, 0xdd, 0x59, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmulpd (%rax), %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0x41, 0x7d, 0x51, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtpd %ymm11, %ymm12" + - + input: + bytes: [ 0xc5, 0x7d, 0x51, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtpd (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7c, 0x51, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtps %ymm11, %ymm12" + - + input: + bytes: [ 0xc5, 0x7c, 0x51, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vsqrtps (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7c, 0x52, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrsqrtps %ymm11, %ymm12" + - + input: + bytes: [ 0xc5, 0x7c, 0x52, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrsqrtps (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7c, 0x53, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrcpps %ymm11, %ymm12" + - + input: + bytes: [ 0xc5, 0x7c, 0x53, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vrcpps (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x0c, 0x54, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandps %ymm12, %ymm14, %ymm11" + - + input: + bytes: [ 0xc4, 0x41, 0x0d, 0x54, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandpd %ymm12, %ymm14, %ymm11" + - + input: + bytes: [ 0xc5, 0x1c, 0x54, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandps -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x1d, 0x54, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandpd -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x41, 0x0c, 0x56, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vorps %ymm12, %ymm14, %ymm11" + - + input: + bytes: [ 0xc4, 0x41, 0x0d, 0x56, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vorpd %ymm12, %ymm14, %ymm11" + - + input: + bytes: [ 0xc5, 0x1c, 0x56, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vorps -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x1d, 0x56, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vorpd -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x41, 0x0c, 0x57, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vxorps %ymm12, %ymm14, %ymm11" + - + input: + bytes: [ 0xc4, 0x41, 0x0d, 0x57, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vxorpd %ymm12, %ymm14, %ymm11" + - + input: + bytes: [ 0xc5, 0x1c, 0x57, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vxorps -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x1d, 0x57, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vxorpd -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x41, 0x0c, 0x55, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandnps %ymm12, %ymm14, %ymm11" + - + input: + bytes: [ 0xc4, 0x41, 0x0d, 0x55, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandnpd %ymm12, %ymm14, %ymm11" + - + input: + bytes: [ 0xc5, 0x1c, 0x55, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandnps -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x1d, 0x55, 0x54, 0xcb, 0xfc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vandnpd -4(%rbx, %rcx, 8), %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x41, 0x7c, 0x5a, 0xe5 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtps2pd %xmm13, %ymm12" + - + input: + bytes: [ 0xc5, 0x7c, 0x5a, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtps2pd (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7e, 0xe6, 0xe5 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2pd %xmm13, %ymm12" + - + input: + bytes: [ 0xc5, 0x7e, 0xe6, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2pd (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7c, 0x5b, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2ps %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x7c, 0x5b, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtdq2ps (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7d, 0x5b, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtps2dq %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x7d, 0x5b, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtps2dq (%rax), %ymm10" + - + input: + bytes: [ 0xc4, 0x41, 0x7e, 0x5b, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttps2dq %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x7e, 0x5b, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttps2dq (%rax), %ymm10" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0xe6, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttpd2dq %xmm11, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x7d, 0xe6, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttpd2dq %ymm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0xe6, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttpd2dq %xmm11, %xmm10" + - + input: + bytes: [ 0xc5, 0x79, 0xe6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttpd2dqx (%rax), %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x7d, 0xe6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttpd2dq %ymm12, %xmm11" + - + input: + bytes: [ 0xc5, 0x7d, 0xe6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttpd2dqy (%rax), %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x7d, 0x5a, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2ps %ymm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x79, 0x5a, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2ps %xmm11, %xmm10" + - + input: + bytes: [ 0xc5, 0x79, 0x5a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2psx (%rax), %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x7d, 0x5a, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2ps %ymm12, %xmm11" + - + input: + bytes: [ 0xc5, 0x7d, 0x5a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2psy (%rax), %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x7f, 0xe6, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2dq %ymm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x41, 0x7f, 0xe6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2dq %ymm12, %xmm11" + - + input: + bytes: [ 0xc5, 0x7f, 0xe6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2dqy (%rax), %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x7b, 0xe6, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2dq %xmm11, %xmm10" + - + input: + bytes: [ 0xc5, 0x7b, 0xe6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtpd2dqx (%rax), %xmm11" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpleps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnleps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqps -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpleps -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltps -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqps -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnleps -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltps -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x4c, 0xc2, 0x64, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordps -4(%rbx, %rcx, 8), %ymm6, %ymm12" + - + input: + bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordps -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqpd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplepd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltpd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqpd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlepd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltpd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordpd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordpd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeqpd -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplepd -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpltpd -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneqpd -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x06 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlepd -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x05 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnltpd -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x4d, 0xc2, 0x64, 0xcb, 0xfc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpordpd -4(%rbx, %rcx, 8), %ymm6, %ymm12" + - + input: + bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunordpd -4(%rbx, %rcx, 8), %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_uqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngeps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngtps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x0b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalseps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x0c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_oqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgeps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x0e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgtps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrueps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_osps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmplt_oqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmple_oqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpunord_sps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x14 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_usps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x15 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnlt_uqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x16 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnle_uqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpord_sps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpeq_usps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpnge_uqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x1a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpngt_uqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x1b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpfalse_osps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x1c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpneq_osps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x1d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpge_oqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmpgt_oqps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcmptrue_usps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1f, 0xd0, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsubps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x27, 0xd0, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsubps (%rax), %ymm11, %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0xd0, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsubpd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x25, 0xd0, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vaddsubpd (%rax), %ymm11, %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x1f, 0x7c, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhaddps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1f, 0x7c, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhaddps (%rax), %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0x7c, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhaddpd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1d, 0x7c, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhaddpd (%rax), %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1f, 0x7d, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhsubps %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1f, 0x7d, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhsubps (%rax), %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x41, 0x1d, 0x7d, 0xeb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhsubpd %ymm11, %ymm12, %ymm13" + - + input: + bytes: [ 0xc5, 0x1d, 0x7d, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vhsubpd (%rax), %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x43, 0x2d, 0x0c, 0xdc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendps $3, %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x63, 0x2d, 0x0c, 0x18, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendps $3, (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x43, 0x2d, 0x0d, 0xdc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendpd $3, %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x63, 0x2d, 0x0d, 0x18, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendpd $3, (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x43, 0x2d, 0x40, 0xdc, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdpps $3, %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x63, 0x2d, 0x40, 0x18, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vdpps $3, (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x7d, 0x1a, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vbroadcastf128 (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x62, 0x7d, 0x19, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vbroadcastsd (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x18, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vbroadcastss (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x62, 0x7d, 0x18, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vbroadcastss (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x43, 0x1d, 0x18, 0xd4, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vinsertf128 $7, %xmm12, %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x63, 0x1d, 0x18, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vinsertf128 $7, (%rax), %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x43, 0x7d, 0x19, 0xe4, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vextractf128 $7, %ymm12, %xmm12" + - + input: + bytes: [ 0xc4, 0x63, 0x7d, 0x19, 0x20, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vextractf128 $7, %ymm12, (%rax)" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x2f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaskmovpd %xmm12, %xmm10, (%rax)" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x2f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaskmovpd %ymm12, %ymm10, (%rax)" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x2d, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaskmovpd (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x1d, 0x2d, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaskmovpd (%rax), %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x2e, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaskmovps %xmm12, %xmm10, (%rax)" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x2e, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaskmovps %ymm12, %ymm10, (%rax)" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0x2c, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaskmovps (%rax), %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x62, 0x1d, 0x2c, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmaskmovps (%rax), %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0x04, 0xd3, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilps $7, %xmm11, %xmm10" + - + input: + bytes: [ 0xc4, 0x43, 0x7d, 0x04, 0xda, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilps $7, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x04, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilps $7, (%rax), %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x7d, 0x04, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilps $7, (%rax), %ymm10" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x0c, 0xdb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilps %xmm11, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0x0c, 0xdb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilps %ymm11, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x0c, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilps (%rax), %xmm10, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x0c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0x05, 0xd3, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilpd $7, %xmm11, %xmm10" + - + input: + bytes: [ 0xc4, 0x43, 0x7d, 0x05, 0xda, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilpd $7, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x63, 0x79, 0x05, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilpd $7, (%rax), %xmm10" + - + input: + bytes: [ 0xc4, 0x63, 0x7d, 0x05, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilpd $7, (%rax), %ymm10" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x0d, 0xdb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilpd %xmm11, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0x0d, 0xdb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilpd %ymm11, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x0d, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilpd (%rax), %xmm10, %xmm13" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x0d, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermilpd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x43, 0x2d, 0x06, 0xdc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vperm2f128 $7, %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x63, 0x2d, 0x06, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vperm2f128 $7, (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x41, 0x7b, 0x2d, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsd2si %xmm8, %r8d" + - + input: + bytes: [ 0xc5, 0xfb, 0x2d, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsd2si (%rcx), %ecx" + - + input: + bytes: [ 0xc4, 0xe1, 0xfa, 0x2d, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtss2si %xmm4, %rcx" + - + input: + bytes: [ 0xc4, 0x61, 0xfa, 0x2d, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtss2si (%rcx), %r8" + - + input: + bytes: [ 0xc4, 0x41, 0x3b, 0x2a, 0xf8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2sdl %r8d, %xmm8, %xmm15" + - + input: + bytes: [ 0xc5, 0x3b, 0x2a, 0x7d, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2sdl (%rbp), %xmm8, %xmm15" + - + input: + bytes: [ 0xc4, 0xe1, 0xdb, 0x2a, 0xf1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2sdq %rcx, %xmm4, %xmm6" + - + input: + bytes: [ 0xc4, 0xe1, 0xdb, 0x2a, 0x31 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2sdq (%rcx), %xmm4, %xmm6" + - + input: + bytes: [ 0xc4, 0xe1, 0xda, 0x2a, 0xf1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2ssq %rcx, %xmm4, %xmm6" + - + input: + bytes: [ 0xc4, 0xe1, 0xda, 0x2a, 0x31 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvtsi2ssq (%rcx), %xmm4, %xmm6" + - + input: + bytes: [ 0xc4, 0xe1, 0xfb, 0x2c, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttsd2si %xmm4, %rcx" + - + input: + bytes: [ 0xc4, 0xe1, 0xfb, 0x2c, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttsd2si (%rcx), %rcx" + - + input: + bytes: [ 0xc4, 0xe1, 0xfa, 0x2c, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttss2si %xmm4, %rcx" + - + input: + bytes: [ 0xc4, 0xe1, 0xfa, 0x2c, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vcvttss2si (%rcx), %rcx" + - + input: + bytes: [ 0xc5, 0x7f, 0xf0, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vlddqu (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7f, 0x12, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovddup %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x7f, 0x12, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovddup (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7d, 0x6f, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovdqa %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x7d, 0x7f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovdqa %ymm12, (%rax)" + - + input: + bytes: [ 0xc5, 0x7d, 0x6f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovdqa (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7e, 0x6f, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovdqu %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x7e, 0x7f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovdqu %ymm12, (%rax)" + - + input: + bytes: [ 0xc5, 0x7e, 0x6f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovdqu (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7e, 0x16, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovshdup %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x7e, 0x16, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovshdup (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x41, 0x7e, 0x12, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovsldup %ymm12, %ymm10" + - + input: + bytes: [ 0xc5, 0x7e, 0x12, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovsldup (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x42, 0x7d, 0x17, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vptest %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x62, 0x7d, 0x17, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vptest (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x43, 0x7d, 0x09, 0xda, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundpd $7, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x63, 0x7d, 0x09, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundpd $7, (%rax), %ymm10" + - + input: + bytes: [ 0xc4, 0x43, 0x7d, 0x08, 0xda, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundps $7, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x63, 0x7d, 0x08, 0x10, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vroundps $7, (%rax), %ymm10" + - + input: + bytes: [ 0xc4, 0x41, 0x2d, 0xc6, 0xdc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vshufpd $7, %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc5, 0x2d, 0xc6, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vshufpd $7, (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x41, 0x2c, 0xc6, 0xdc, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vshufps $7, %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc5, 0x2c, 0xc6, 0x18, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vshufps $7, (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x0f, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vtestpd %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x42, 0x7d, 0x0f, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vtestpd %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x0f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vtestpd (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x62, 0x7d, 0x0f, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vtestpd (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x42, 0x79, 0x0e, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vtestps %xmm12, %xmm10" + - + input: + bytes: [ 0xc4, 0x42, 0x7d, 0x0e, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vtestps %ymm12, %ymm10" + - + input: + bytes: [ 0xc4, 0x62, 0x79, 0x0e, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vtestps (%rax), %xmm12" + - + input: + bytes: [ 0xc4, 0x62, 0x7d, 0x0e, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vtestps (%rax), %ymm12" + - + input: + bytes: [ 0xc4, 0x43, 0x79, 0x17, 0xc0, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vextractps $10, %xmm8, %r8d" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x17, 0xe1, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vextractps $7, %xmm4, %ecx" + - + input: + bytes: [ 0xc4, 0xe1, 0xf9, 0x7e, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovq %xmm4, %rcx" + - + input: + bytes: [ 0xc5, 0xf9, 0x50, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovmskpd %xmm4, %ecx" + - + input: + bytes: [ 0xc5, 0xfd, 0x50, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovmskpd %ymm4, %ecx" + - + input: + bytes: [ 0xc5, 0xf8, 0x50, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovmskps %xmm4, %ecx" + - + input: + bytes: [ 0xc5, 0xfc, 0x50, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovmskps %ymm4, %ecx" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x14, 0xe1, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpextrb $7, %xmm4, %ecx" + - + input: + bytes: [ 0xc4, 0x41, 0x01, 0xc4, 0xc0, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrw $7, %r8d, %xmm15, %xmm8" + - + input: + bytes: [ 0xc5, 0xd9, 0xc4, 0xf1, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpinsrw $7, %ecx, %xmm4, %xmm6" + - + input: + bytes: [ 0xc5, 0xf9, 0xd7, 0xcc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmovmskb %xmm4, %ecx" + - + input: + bytes: [ 0xc4, 0x63, 0x1d, 0x4b, 0xac, 0x20, 0xad, 0xde, 0x00, 0x00, 0xb0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vblendvpd %ymm11, 0xdead(%rax, %riz), %ymm12, %ymm13" + - + input: + bytes: [ 0xc4, 0x81, 0x78, 0x29, 0x1c, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %xmm3, (%r14, %r11)" + - + input: + bytes: [ 0xc4, 0x81, 0x78, 0x28, 0x1c, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps (%r14, %r11), %xmm3" + - + input: + bytes: [ 0xc4, 0xc1, 0x78, 0x29, 0x1c, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %xmm3, (%r14, %rbx)" + - + input: + bytes: [ 0xc4, 0xc1, 0x78, 0x28, 0x1c, 0x1e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps (%r14, %rbx), %xmm3" + - + input: + bytes: [ 0xc4, 0xa1, 0x78, 0x29, 0x1c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %xmm3, (%rax, %r11)" + - + input: + bytes: [ 0xc4, 0xe2, 0xf9, 0x92, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vgatherdpd %xmm0, (%rdi, %xmm1, 2), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0xf9, 0x93, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vgatherqpd %xmm0, (%rdi, %xmm1, 2), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0xfd, 0x92, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vgatherdpd %ymm0, (%rdi, %xmm1, 2), %ymm2" + - + input: + bytes: [ 0xc4, 0xe2, 0xfd, 0x93, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vgatherqpd %ymm0, (%rdi, %ymm1, 2), %ymm2" + - + input: + bytes: [ 0xc4, 0x02, 0x39, 0x92, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vgatherdps %xmm8, (%r15, %xmm9, 2), %xmm10" + - + input: + bytes: [ 0xc4, 0x02, 0x39, 0x93, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vgatherqps %xmm8, (%r15, %xmm9, 2), %xmm10" + - + input: + bytes: [ 0xc4, 0x02, 0x3d, 0x92, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vgatherdps %ymm8, (%r15, %ymm9, 2), %ymm10" + - + input: + bytes: [ 0xc4, 0x02, 0x3d, 0x93, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vgatherqps %xmm8, (%r15, %ymm9, 2), %xmm10" + - + input: + bytes: [ 0xc4, 0xe2, 0xf9, 0x90, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpgatherdq %xmm0, (%rdi, %xmm1, 2), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0xf9, 0x91, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpgatherqq %xmm0, (%rdi, %xmm1, 2), %xmm2" + - + input: + bytes: [ 0xc4, 0xe2, 0xfd, 0x90, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpgatherdq %ymm0, (%rdi, %xmm1, 2), %ymm2" + - + input: + bytes: [ 0xc4, 0xe2, 0xfd, 0x91, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpgatherqq %ymm0, (%rdi, %ymm1, 2), %ymm2" + - + input: + bytes: [ 0xc4, 0x02, 0x39, 0x90, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpgatherdd %xmm8, (%r15, %xmm9, 2), %xmm10" + - + input: + bytes: [ 0xc4, 0x02, 0x39, 0x91, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpgatherqd %xmm8, (%r15, %xmm9, 2), %xmm10" + - + input: + bytes: [ 0xc4, 0x02, 0x3d, 0x90, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpgatherdd %ymm8, (%r15, %ymm9, 2), %ymm10" + - + input: + bytes: [ 0xc4, 0x02, 0x3d, 0x91, 0x14, 0x4f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpgatherqd %xmm8, (%r15, %ymm9, 2), %xmm10" + - + input: + bytes: [ 0xc5, 0x78, 0x28, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %xmm0, %xmm8" + - + input: + bytes: [ 0xc5, 0x78, 0x29, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %xmm8, %xmm0" + - + input: + bytes: [ 0xc5, 0x7c, 0x28, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %ymm0, %ymm8" + - + input: + bytes: [ 0xc5, 0x7c, 0x29, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovaps %ymm8, %ymm0" + - + input: + bytes: [ 0xc5, 0x78, 0x10, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups %xmm0, %xmm8" + - + input: + bytes: [ 0xc5, 0x78, 0x11, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups %xmm8, %xmm0" + - + input: + bytes: [ 0xc5, 0x7c, 0x10, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups %ymm0, %ymm8" + - + input: + bytes: [ 0xc5, 0x7c, 0x11, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovups %ymm8, %ymm0" + - + input: + bytes: [ 0xc5, 0x7a, 0x10, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovss %xmm0, %xmm0, %xmm8" + - + input: + bytes: [ 0xc5, 0xba, 0x10, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovss %xmm0, %xmm8, %xmm0" + - + input: + bytes: [ 0xc5, 0x7a, 0x11, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovss %xmm8, %xmm0, %xmm0" + - + input: + bytes: [ 0xc5, 0x7b, 0x10, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovsd %xmm0, %xmm0, %xmm8" + - + input: + bytes: [ 0xc5, 0xbb, 0x10, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovsd %xmm0, %xmm8, %xmm0" + - + input: + bytes: [ 0xc5, 0x7b, 0x11, 0xc0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vmovsd %xmm8, %xmm0, %xmm0" diff --git a/tests/MC/X86/x86_64-bmi-encoding.s.yaml b/tests/MC/X86/x86_64-bmi-encoding.s.yaml new file mode 100644 index 0000000000..af5be80f75 --- /dev/null +++ b/tests/MC/X86/x86_64-bmi-encoding.s.yaml @@ -0,0 +1,451 @@ +test_cases: + - + input: + bytes: [ 0xc4, 0xc2, 0x28, 0xf3, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsmskl %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0xc2, 0xa8, 0xf3, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsmskq %r11, %r10" + - + input: + bytes: [ 0xc4, 0xe2, 0x28, 0xf3, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsmskl (%rax), %r10d" + - + input: + bytes: [ 0xc4, 0xe2, 0xa8, 0xf3, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsmskq (%rax), %r10" + - + input: + bytes: [ 0xc4, 0xc2, 0x28, 0xf3, 0xdb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsil %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0xc2, 0xa8, 0xf3, 0xdb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsiq %r11, %r10" + - + input: + bytes: [ 0xc4, 0xe2, 0x28, 0xf3, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsil (%rax), %r10d" + - + input: + bytes: [ 0xc4, 0xe2, 0xa8, 0xf3, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsiq (%rax), %r10" + - + input: + bytes: [ 0xc4, 0xc2, 0x28, 0xf3, 0xcb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsrl %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0xc2, 0xa8, 0xf3, 0xcb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsrq %r11, %r10" + - + input: + bytes: [ 0xc4, 0xe2, 0x28, 0xf3, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsrl (%rax), %r10d" + - + input: + bytes: [ 0xc4, 0xe2, 0xa8, 0xf3, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsrq (%rax), %r10" + - + input: + bytes: [ 0xc4, 0x62, 0x20, 0xf2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "andnl (%rax), %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x62, 0xa0, 0xf2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "andnq (%rax), %r11, %r10" + - + input: + bytes: [ 0xc4, 0x62, 0x18, 0xf7, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bextrl %r12d, (%rax), %r10d" + - + input: + bytes: [ 0xc4, 0x42, 0x18, 0xf7, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bextrl %r12d, %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x62, 0x98, 0xf7, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bextrq %r12, (%rax), %r10" + - + input: + bytes: [ 0xc4, 0x42, 0x98, 0xf7, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bextrq %r12, %r11, %r10" + - + input: + bytes: [ 0xc4, 0x62, 0x18, 0xf5, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bzhil %r12d, (%rax), %r10d" + - + input: + bytes: [ 0xc4, 0x42, 0x18, 0xf5, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bzhil %r12d, %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x62, 0x98, 0xf5, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bzhiq %r12, (%rax), %r10" + - + input: + bytes: [ 0xc4, 0x42, 0x98, 0xf5, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bzhiq %r12, %r11, %r10" + - + input: + bytes: [ 0xc4, 0x42, 0x22, 0xf5, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pextl %r12d, %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x62, 0x22, 0xf5, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pextl (%rax), %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x42, 0xa2, 0xf5, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pextq %r12, %r11, %r10" + - + input: + bytes: [ 0xc4, 0x62, 0xa2, 0xf5, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pextq (%rax), %r11, %r10" + - + input: + bytes: [ 0xc4, 0x42, 0x23, 0xf5, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pdepl %r12d, %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x62, 0x23, 0xf5, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pdepl (%rax), %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x42, 0xa3, 0xf5, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pdepq %r12, %r11, %r10" + - + input: + bytes: [ 0xc4, 0x62, 0xa3, 0xf5, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pdepq (%rax), %r11, %r10" + - + input: + bytes: [ 0xc4, 0x42, 0x23, 0xf6, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "mulxl %r12d, %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x62, 0x23, 0xf6, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "mulxl (%rax), %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x42, 0xa3, 0xf6, 0xd4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "mulxq %r12, %r11, %r10" + - + input: + bytes: [ 0xc4, 0x62, 0xa3, 0xf6, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "mulxq (%rax), %r11, %r10" + - + input: + bytes: [ 0xc4, 0x43, 0x7b, 0xf0, 0xd4, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rorxl $10, %r12d, %r10d" + - + input: + bytes: [ 0xc4, 0x63, 0x7b, 0xf0, 0x10, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rorxl $31, (%rax), %r10d" + - + input: + bytes: [ 0xc4, 0x43, 0xfb, 0xf0, 0xd4, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rorxq $1, %r12, %r10" + - + input: + bytes: [ 0xc4, 0x63, 0xfb, 0xf0, 0x10, 0x3f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rorxq $63, (%rax), %r10" + - + input: + bytes: [ 0xc4, 0x62, 0x19, 0xf7, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "shlxl %r12d, (%rax), %r10d" + - + input: + bytes: [ 0xc4, 0x42, 0x19, 0xf7, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "shlxl %r12d, %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x62, 0x99, 0xf7, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "shlxq %r12, (%rax), %r10" + - + input: + bytes: [ 0xc4, 0x42, 0x99, 0xf7, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "shlxq %r12, %r11, %r10" + - + input: + bytes: [ 0xc4, 0x62, 0x1a, 0xf7, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sarxl %r12d, (%rax), %r10d" + - + input: + bytes: [ 0xc4, 0x42, 0x1a, 0xf7, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sarxl %r12d, %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x62, 0x9a, 0xf7, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sarxq %r12, (%rax), %r10" + - + input: + bytes: [ 0xc4, 0x42, 0x9a, 0xf7, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sarxq %r12, %r11, %r10" + - + input: + bytes: [ 0xc4, 0x62, 0x1b, 0xf7, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "shrxl %r12d, (%rax), %r10d" + - + input: + bytes: [ 0xc4, 0x42, 0x1b, 0xf7, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "shrxl %r12d, %r11d, %r10d" + - + input: + bytes: [ 0xc4, 0x62, 0x9b, 0xf7, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "shrxq %r12, (%rax), %r10" + - + input: + bytes: [ 0xc4, 0x42, 0x9b, 0xf7, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "shrxq %r12, %r11, %r10" diff --git a/tests/MC/X86/x86_64-encoding.s.yaml b/tests/MC/X86/x86_64-encoding.s.yaml new file mode 100644 index 0000000000..9c83b28e65 --- /dev/null +++ b/tests/MC/X86/x86_64-encoding.s.yaml @@ -0,0 +1,523 @@ +test_cases: + - + input: + bytes: [ 0x65, 0x48, 0x8b, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq %gs:(%rdi), %rax" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf0, 0xc3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32b %bl, %eax" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf0, 0x43, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32b 4(%rbx), %eax" + - + input: + bytes: [ 0x66, 0xf2, 0x0f, 0x38, 0xf1, 0xc3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32w %bx, %eax" + - + input: + bytes: [ 0x66, 0xf2, 0x0f, 0x38, 0xf1, 0x43, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32w 4(%rbx), %eax" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0xc3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32l %ebx, %eax" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0x43, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32l 4(%rbx), %eax" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0x8c, 0xcb, 0xef, 0xbe, 0xad, 0xde ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32l -0x21524111(%rbx, %rcx, 8), %ecx" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0x0c, 0x25, 0x45, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32l 0x45, %ecx" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0x0c, 0x25, 0xed, 0x7e, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32l 0x7eed, %ecx" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0x0c, 0x25, 0xfe, 0xca, 0xbe, 0xba ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32l 0xffffffffbabecafe, %ecx" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0xc9 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32l %ecx, %ecx" + - + input: + bytes: [ 0xf2, 0x41, 0x0f, 0x38, 0xf0, 0xc3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32b %r11b, %eax" + - + input: + bytes: [ 0xf2, 0x0f, 0x38, 0xf0, 0x43, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32b 4(%rbx), %eax" + - + input: + bytes: [ 0xf2, 0x48, 0x0f, 0x38, 0xf0, 0xc7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32b %dil, %rax" + - + input: + bytes: [ 0xf2, 0x49, 0x0f, 0x38, 0xf0, 0xc3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32b %r11b, %rax" + - + input: + bytes: [ 0xf2, 0x48, 0x0f, 0x38, 0xf0, 0x43, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32b 4(%rbx), %rax" + - + input: + bytes: [ 0xf2, 0x48, 0x0f, 0x38, 0xf1, 0xc3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32q %rbx, %rax" + - + input: + bytes: [ 0xf2, 0x48, 0x0f, 0x38, 0xf1, 0x43, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "crc32q 4(%rbx), %rax" + - + input: + bytes: [ 0x49, 0x0f, 0x6e, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq %r8, %mm1" + - + input: + bytes: [ 0x41, 0x0f, 0x6e, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movd %r8d, %mm1" + - + input: + bytes: [ 0x48, 0x0f, 0x6e, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq %rdx, %mm1" + - + input: + bytes: [ 0x0f, 0x6e, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movd %edx, %mm1" + - + input: + bytes: [ 0x49, 0x0f, 0x7e, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq %mm1, %r8" + - + input: + bytes: [ 0x41, 0x0f, 0x7e, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movd %mm1, %r8d" + - + input: + bytes: [ 0x48, 0x0f, 0x7e, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq %mm1, %rdx" + - + input: + bytes: [ 0x0f, 0x7e, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movd %mm1, %edx" + - + input: + bytes: [ 0x0f, 0x3a, 0xcc, 0xd1, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha1rnds4 $1, %xmm1, %xmm2" + - + input: + bytes: [ 0x0f, 0x3a, 0xcc, 0x10, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha1rnds4 $1, (%rax), %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xc8, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha1nexte %xmm1, %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xc9, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha1msg1 %xmm1, %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xc9, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha1msg1 (%rax), %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xca, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha1msg2 %xmm1, %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xca, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha1msg2 (%rax), %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xcb, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha256rnds2 %xmm0, (%rax), %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xcb, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha256rnds2 %xmm0, %xmm1, %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xcb, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha256rnds2 %xmm0, (%rax), %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xcb, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha256rnds2 %xmm0, %xmm1, %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xcc, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha256msg1 %xmm1, %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xcc, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha256msg1 (%rax), %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xcd, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha256msg2 %xmm1, %xmm2" + - + input: + bytes: [ 0x0f, 0x38, 0xcd, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "sha256msg2 (%rax), %xmm2" + - + input: + bytes: [ 0x48, 0x8b, 0x1c, 0x25, 0xad, 0xde, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq 0xdead, %rbx" + - + input: + bytes: [ 0x48, 0x8b, 0x04, 0x25, 0xef, 0xbe, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq 0xbeef, %rax" + - + input: + bytes: [ 0x48, 0x8b, 0x04, 0xe5, 0xfc, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq -4(, %riz, 8), %rax" + - + input: + bytes: [ 0x48, 0x8b, 0x04, 0x21 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq (%rcx, %riz), %rax" + - + input: + bytes: [ 0x48, 0x8b, 0x04, 0xe1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movq (%rcx, %riz, 8), %rax" + - + input: + bytes: [ 0x48, 0x0f, 0xae, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "fxsave64 (%rax)" + - + input: + bytes: [ 0x48, 0x0f, 0xae, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "fxrstor64 (%rax)" + - + input: + bytes: [ 0xc9 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "leave" + - + input: + bytes: [ 0xc9 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "leave" + - + input: + bytes: [ 0x67, 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "flds (%edi)" + - + input: + bytes: [ 0x67, 0xdf, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "filds (%edi)" + - + input: + bytes: [ 0xd9, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "flds (%rdi)" + - + input: + bytes: [ 0xdf, 0x07 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "filds (%rdi)" + - + input: + bytes: [ 0x66, 0x0f, 0xd7, 0xcd ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pmovmskb %xmm5, %ecx" + - + input: + bytes: [ 0x66, 0x0f, 0xc4, 0xe9, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pinsrw $3, %ecx, %xmm5" + - + input: + bytes: [ 0x66, 0x0f, 0xc4, 0xe9, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "pinsrw $3, %ecx, %xmm5" diff --git a/tests/MC/X86/x86_64-fma3-encoding.s.yaml b/tests/MC/X86/x86_64-fma3-encoding.s.yaml new file mode 100644 index 0000000000..4724442010 --- /dev/null +++ b/tests/MC/X86/x86_64-fma3-encoding.s.yaml @@ -0,0 +1,1513 @@ +test_cases: + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0x98, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0x98, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x98, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x98, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xa8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xa8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xa8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xa8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xb8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xb8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xb8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xb8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0x98, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0x98, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0x98, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x98, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xa8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xa8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xa8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xa8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xb8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xb8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xb8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xb8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0x98, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0x98, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x98, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x98, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xa8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xa8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xa8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xa8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xb8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xb8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xb8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xb8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0x96, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub132pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0x96, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub132pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x96, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub132ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x96, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub132ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xa6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub213pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xa6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub213pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xa6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub213ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xa6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub213ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xb6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub231pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xb6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub231pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xb6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub231ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xb6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub231ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0x97, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd132pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0x97, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd132pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x97, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd132ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x97, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd132ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xa7, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd213pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xa7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd213pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xa7, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd213ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xa7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd213ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xb7, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd231pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xb7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd231pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xb7, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd231ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xb7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd231ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0x9a, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub132pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0x9a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub132pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x9a, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub132ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x9a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub132ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xaa, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub213pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xaa, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub213pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xaa, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub213ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xaa, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub213ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xba, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub231pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xba, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub231pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xba, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub231ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xba, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub231ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0x9c, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd132pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0x9c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd132pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x9c, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd132ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x9c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd132ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xac, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd213pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xac, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd213pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xac, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd213ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xac, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd213ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xbc, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd231pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xbc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd231pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xbc, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd231ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xbc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd231ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0x9e, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub132pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0x9e, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub132pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0x9e, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub132ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0x9e, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub132ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xae, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub213pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xae, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub213pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xae, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub213ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xae, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub213ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xa9, 0xbe, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub231pd %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0xa9, 0xbe, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub231pd (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0x29, 0xbe, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub231ps %xmm12, %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x62, 0x29, 0xbe, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub231ps (%rax), %xmm10, %xmm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0x98, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0x98, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0x98, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x98, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd132ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xa8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xa8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xa8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xa8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd213ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xb8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xb8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xb8, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xb8, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmadd231ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0x96, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub132pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0x96, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub132pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0x96, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub132ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x96, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub132ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xa6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub213pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xa6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub213pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xa6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub213ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xa6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub213ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xb6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub231pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xb6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub231pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xb6, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub231ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xb6, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsub231ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0x97, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd132pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0x97, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd132pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0x97, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd132ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x97, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd132ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xa7, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd213pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xa7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd213pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xa7, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd213ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xa7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd213ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xb7, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd231pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xb7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd231pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xb7, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd231ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xb7, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubadd231ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0x9a, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub132pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0x9a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub132pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0x9a, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub132ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x9a, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub132ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xaa, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub213pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xaa, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub213pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xaa, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub213ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xaa, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub213ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xba, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub231pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xba, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub231pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xba, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub231ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xba, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsub231ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0x9c, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd132pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0x9c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd132pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0x9c, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd132ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x9c, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd132ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xac, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd213pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xac, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd213pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xac, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd213ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xac, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd213ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xbc, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd231pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xbc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd231pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xbc, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd231ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xbc, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmadd231ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0x9e, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub132pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0x9e, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub132pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0x9e, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub132ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0x9e, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub132ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xae, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub213pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xae, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub213pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xae, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub213ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xae, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub213ps (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0xad, 0xbe, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub231pd %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0xad, 0xbe, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub231pd (%rax), %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x42, 0x2d, 0xbe, 0xdc ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub231ps %ymm12, %ymm10, %ymm11" + - + input: + bytes: [ 0xc4, 0x62, 0x2d, 0xbe, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsub231ps (%rax), %ymm10, %ymm11" diff --git a/tests/MC/X86/x86_64-fma4-encoding.s.yaml b/tests/MC/X86/x86_64-fma4-encoding.s.yaml new file mode 100644 index 0000000000..84384b1220 --- /dev/null +++ b/tests/MC/X86/x86_64-fma4-encoding.s.yaml @@ -0,0 +1,874 @@ +test_cases: + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6a, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddss (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x6a, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddss %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6a, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddss %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6b, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x6b, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6b, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xc3, 0xf9, 0x6b, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsd %xmm10, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x68, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddps (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x68, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddps %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x68, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddps %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x69, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddpd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x69, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddpd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x69, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddpd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x68, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddps (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x68, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddps %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x68, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddps %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x69, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddpd (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x69, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddpd %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x69, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddpd %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6e, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubss (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x6e, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubss %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6e, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubss %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6f, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubsd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x6f, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubsd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6f, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubsd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubps (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x6c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubps %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6c, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubps %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubpd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x6d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubpd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x6d, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubpd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x6c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubps (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x6c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubps %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x6c, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubps %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x6d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubpd (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x6d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubpd %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x6d, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubpd %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7a, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddss (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x7a, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddss %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7a, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddss %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7b, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddsd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x7b, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddsd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7b, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddsd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x78, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddps (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x78, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddps %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x78, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddps %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x79, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddpd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x79, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddpd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x79, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddpd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x78, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddps (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x78, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddps %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x78, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddps %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x79, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddpd (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x79, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddpd %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x79, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmaddpd %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7e, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubss (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x7e, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubss %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7e, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubss %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7f, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubsd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x7f, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubsd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7f, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubsd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubps (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x7c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubps %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7c, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubps %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubpd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x7d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubpd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x7d, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubpd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x7c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubps (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x7c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubps %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x7c, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubps %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x7d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubpd (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x7d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubpd %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x7d, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfnmsubpd %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x5c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubps (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x5c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubps %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x5c, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubps %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x5d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubpd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x5d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubpd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x5d, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubpd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x5c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubps (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x5c, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubps %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x5c, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubps %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x5d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubpd (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x5d, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubpd %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x5d, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmaddsubpd %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x5e, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddps (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x5e, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddps %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x5e, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddps %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x5f, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddpd (%rcx), %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x79, 0x5f, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddpd %xmm1, (%rcx), %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xf9, 0x5f, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddpd %xmm2, %xmm1, %xmm0, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x5e, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddps (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x5e, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddps %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x5e, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddps %ymm2, %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x5f, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddpd (%rcx), %ymm1, %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x7d, 0x5f, 0x01, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddpd %ymm1, (%rcx), %ymm0, %ymm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xfd, 0x5f, 0xc2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfmsubaddpd %ymm2, %ymm1, %ymm0, %ymm0" diff --git a/tests/MC/X86/x86_64-imm-widths.s.yaml b/tests/MC/X86/x86_64-imm-widths.s.yaml new file mode 100644 index 0000000000..d88cee52cb --- /dev/null +++ b/tests/MC/X86/x86_64-imm-widths.s.yaml @@ -0,0 +1,235 @@ +test_cases: + - + input: + bytes: [ 0x04, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addb $0x00, %al" + - + input: + bytes: [ 0x04, 0x7f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addb $0x7F, %al" + - + input: + bytes: [ 0x04, 0x80 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addb $0x80, %al" + - + input: + bytes: [ 0x04, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addb $0xFF, %al" + - + input: + bytes: [ 0x66, 0x83, 0xc0, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addw $0x0000, %ax" + - + input: + bytes: [ 0x66, 0x83, 0xc0, 0x7f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addw $0x007F, %ax" + - + input: + bytes: [ 0x66, 0x83, 0xc0, 0x80 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addw $-0x80, %ax" + - + input: + bytes: [ 0x66, 0x83, 0xc0, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addw $-1, %ax" + - + input: + bytes: [ 0x83, 0xc0, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addl $0x00000000, %eax" + - + input: + bytes: [ 0x83, 0xc0, 0x7f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addl $0x0000007F, %eax" + - + input: + bytes: [ 0x05, 0x80, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addl $0xFF80, %eax" + - + input: + bytes: [ 0x05, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addl $0xFFFF, %eax" + - + input: + bytes: [ 0x83, 0xc0, 0x80 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addl $-0x80, %eax" + - + input: + bytes: [ 0x83, 0xc0, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addl $-1, %eax" + - + input: + bytes: [ 0x48, 0x83, 0xc0, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0x0000000000000000, %rax" + - + input: + bytes: [ 0x48, 0x83, 0xc0, 0x7f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0x000000000000007F, %rax" + - + input: + bytes: [ 0x48, 0x83, 0xc0, 0x80 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0xFFFFFFFFFFFFFF80, %rax" + - + input: + bytes: [ 0x48, 0x83, 0xc0, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0xFFFFFFFFFFFFFFFF, %rax" + - + input: + bytes: [ 0x48, 0x83, 0xc0, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0x0000000000000000, %rax" + - + input: + bytes: [ 0x48, 0x05, 0x80, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0xFF80, %rax" + - + input: + bytes: [ 0x48, 0x05, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0xFFFF, %rax" + - + input: + bytes: [ 0x48, 0xb8, 0x80, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movabsq $0xFFFFFF80, %rax" + - + input: + bytes: [ 0x48, 0xb8, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "movabsq $0xFFFFFFFF, %rax" + - + input: + bytes: [ 0x48, 0x05, 0xff, 0xff, 0xff, 0x7f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0x000000007FFFFFFF, %rax" + - + input: + bytes: [ 0x48, 0x05, 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0xFFFFFFFF80000000, %rax" + - + input: + bytes: [ 0x48, 0x05, 0x00, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "addq $0xFFFFFFFFFFFFFF00, %rax" diff --git a/tests/MC/X86/x86_64-rand-encoding.s.yaml b/tests/MC/X86/x86_64-rand-encoding.s.yaml new file mode 100644 index 0000000000..30339e469e --- /dev/null +++ b/tests/MC/X86/x86_64-rand-encoding.s.yaml @@ -0,0 +1,109 @@ +test_cases: + - + input: + bytes: [ 0x66, 0x0f, 0xc7, 0xf0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdrandw %ax" + - + input: + bytes: [ 0x0f, 0xc7, 0xf0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdrandl %eax" + - + input: + bytes: [ 0x48, 0x0f, 0xc7, 0xf0 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdrandq %rax" + - + input: + bytes: [ 0x66, 0x41, 0x0f, 0xc7, 0xf3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdrandw %r11w" + - + input: + bytes: [ 0x41, 0x0f, 0xc7, 0xf3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdrandl %r11d" + - + input: + bytes: [ 0x49, 0x0f, 0xc7, 0xf3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdrandq %r11" + - + input: + bytes: [ 0x66, 0x0f, 0xc7, 0xf8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdseedw %ax" + - + input: + bytes: [ 0x0f, 0xc7, 0xf8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdseedl %eax" + - + input: + bytes: [ 0x48, 0x0f, 0xc7, 0xf8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdseedq %rax" + - + input: + bytes: [ 0x66, 0x41, 0x0f, 0xc7, 0xfb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdseedw %r11w" + - + input: + bytes: [ 0x41, 0x0f, 0xc7, 0xfb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdseedl %r11d" + - + input: + bytes: [ 0x49, 0x0f, 0xc7, 0xfb ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "rdseedq %r11" diff --git a/tests/MC/X86/x86_64-rtm-encoding.s.yaml b/tests/MC/X86/x86_64-rtm-encoding.s.yaml new file mode 100644 index 0000000000..0efe2adbea --- /dev/null +++ b/tests/MC/X86/x86_64-rtm-encoding.s.yaml @@ -0,0 +1,28 @@ +test_cases: + - + input: + bytes: [ 0x0f, 0x01, 0xd5 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "xend" + - + input: + bytes: [ 0x0f, 0x01, 0xd6 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "xtest" + - + input: + bytes: [ 0xc6, 0xf8, 0x0d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "xabort $13" diff --git a/tests/MC/X86/x86_64-tbm-encoding.s.yaml b/tests/MC/X86/x86_64-tbm-encoding.s.yaml new file mode 100644 index 0000000000..6110a9a5d8 --- /dev/null +++ b/tests/MC/X86/x86_64-tbm-encoding.s.yaml @@ -0,0 +1,352 @@ +test_cases: + - + input: + bytes: [ 0x8f, 0xea, 0x78, 0x10, 0xc7, 0xfe, 0x0a, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bextrl $2814, %edi, %eax" + - + input: + bytes: [ 0x8f, 0xea, 0x78, 0x10, 0x07, 0xfe, 0x0a, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bextrl $2814, (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xea, 0xf8, 0x10, 0xc7, 0xfe, 0x0a, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bextrq $2814, %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xea, 0xf8, 0x10, 0x07, 0xfe, 0x0a, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "bextrq $2814, (%rdi), %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xcf ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcfilll %edi, %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcfilll (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xcf ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcfillq %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcfillq (%rdi), %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x02, 0xf7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcil %edi, %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x02, 0x37 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcil (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x02, 0xf7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blciq %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x02, 0x37 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blciq (%rdi), %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xef ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcicl %edi, %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x2f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcicl (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xef ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcicq %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0x2f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcicq (%rdi), %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x02, 0xcf ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcmskl %edi, %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x02, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcmskl (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x02, 0xcf ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcmskq %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x02, 0x0f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcmskq (%rdi), %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xdf ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcsl %edi, %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcsl (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xdf ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcsq %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0x1f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blcsq (%rdi), %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xd7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsfilll %edi, %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsfilll (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xd7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsfillq %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0x17 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsfillq (%rdi), %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xf7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsicl %edi, %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x37 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsicl (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xf7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "blsicq %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "t1mskcl %edi, %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x3f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "t1mskcl (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xff ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "t1mskcq %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0x3f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "t1mskcq (%rdi), %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xe7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "tzmskl %edi, %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x27 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "tzmskl (%rdi), %eax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xe7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "tzmskq %rdi, %rax" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0x27 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "tzmskq (%rdi), %rax" diff --git a/tests/MC/X86/x86_64-xop-encoding.s.yaml b/tests/MC/X86/x86_64-xop-encoding.s.yaml new file mode 100644 index 0000000000..d1400f9377 --- /dev/null +++ b/tests/MC/X86/x86_64-xop-encoding.s.yaml @@ -0,0 +1,1360 @@ +test_cases: + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xe2, 0x0c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubwd (%rcx, %rax), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xe2, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubwd %xmm0, %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xe3, 0x0c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubdq (%rcx, %rax), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xe3, 0xc8 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubdq %xmm0, %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xe1, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubbw (%rax), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xe1, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphsubbw %xmm2, %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc7, 0x21 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddwq (%rcx), %xmm4" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc7, 0xd6 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddwq %xmm6, %xmm2" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc6, 0x3c, 0x02 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddwd (%rdx, %rax), %xmm7" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc6, 0xe3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddwd %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd7, 0x34, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphadduwq (%rcx, %rax), %xmm6" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd7, 0xc7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphadduwq %xmm7, %xmm0" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd6, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphadduwd (%rax), %xmm5" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd6, 0xca ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphadduwd %xmm2, %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xdb, 0x64, 0x01, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddudq 8(%rcx, %rax), %xmm4" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xdb, 0xd6 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddudq %xmm6, %xmm2" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd1, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddubw (%rcx), %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd1, 0xc5 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddubw %xmm5, %xmm0" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd3, 0x21 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddubq (%rcx), %xmm4" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd3, 0xd2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddubq %xmm2, %xmm2" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd2, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddubd (%rax), %xmm5" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xd2, 0xfd ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddubd %xmm5, %xmm7" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xcb, 0x22 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphadddq (%rdx), %xmm4" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xcb, 0xec ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphadddq %xmm4, %xmm5" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc1, 0x0c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddbw (%rcx, %rax), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc1, 0xf5 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddbw %xmm5, %xmm6" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc3, 0x0c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddbq (%rcx, %rax), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc3, 0xc2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddbq %xmm2, %xmm0" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc2, 0x0c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddbd (%rcx, %rax), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0xc2, 0xd9 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vphaddbd %xmm1, %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x82, 0x0c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczss (%rcx, %rax), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x82, 0xfd ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczss %xmm5, %xmm7" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x83, 0x0c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczsd (%rcx, %rax), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x83, 0xc7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczsd %xmm7, %xmm0" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x80, 0x58, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczps 4(%rax), %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x80, 0xee ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczps %xmm6, %xmm5" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x80, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczps (%rcx), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x7c, 0x80, 0xe2 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczps %ymm2, %ymm4" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x81, 0x0c, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczpd (%rcx, %rax), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x81, 0xc7 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczpd %xmm7, %xmm0" + - + input: + bytes: [ 0x8f, 0xe9, 0x7c, 0x81, 0x14, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczpd (%rcx, %rax), %ymm2" + - + input: + bytes: [ 0x8f, 0xe9, 0x7c, 0x81, 0xdd ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vfrczpd %ymm5, %ymm3" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x95, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshlw %xmm0, %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe9, 0xf0, 0x95, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshlw (%rax), %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x95, 0x14, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshlw %xmm0, (%rax, %rcx), %xmm2" + - + input: + bytes: [ 0x8f, 0xe9, 0x68, 0x97, 0xf4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshlq %xmm2, %xmm4, %xmm6" + - + input: + bytes: [ 0x8f, 0xe9, 0xe8, 0x97, 0x09 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshlq (%rcx), %xmm2, %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x50, 0x97, 0x34, 0x0a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshlq %xmm5, (%rdx, %rcx), %xmm6" + - + input: + bytes: [ 0x8f, 0xe9, 0x40, 0x96, 0xdd ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshld %xmm7, %xmm5, %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0xe0, 0x96, 0x58, 0x04 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshld 4(%rax), %xmm3, %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0x70, 0x96, 0x2c, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshld %xmm1, (%rax, %rcx), %xmm5" + - + input: + bytes: [ 0x8f, 0xe9, 0x70, 0x94, 0xda ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshlb %xmm1, %xmm2, %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x94, 0x39 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshlb (%rcx), %xmm0, %xmm7" + - + input: + bytes: [ 0x8f, 0xe9, 0x68, 0x94, 0x1c, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshlb %xmm2, (%rax, %rdx), %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0x40, 0x99, 0xdd ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshaw %xmm7, %xmm5, %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0xe8, 0x99, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshaw (%rax), %xmm2, %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x99, 0x5c, 0x08, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshaw %xmm0, 8(%rax, %rcx), %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0x58, 0x9b, 0xe4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshaq %xmm4, %xmm4, %xmm4" + - + input: + bytes: [ 0x8f, 0xe9, 0xe8, 0x9b, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshaq (%rcx), %xmm2, %xmm0" + - + input: + bytes: [ 0x8f, 0xe9, 0x48, 0x9b, 0x2c, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshaq %xmm6, (%rax, %rcx), %xmm5" + - + input: + bytes: [ 0x8f, 0xe9, 0x50, 0x9a, 0xc4 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshad %xmm5, %xmm4, %xmm0" + - + input: + bytes: [ 0x8f, 0xe9, 0xe8, 0x9a, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshad (%rax), %xmm2, %xmm5" + - + input: + bytes: [ 0x8f, 0xe9, 0x68, 0x9a, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshad %xmm2, (%rax), %xmm5" + - + input: + bytes: [ 0x8f, 0xe9, 0x70, 0x98, 0xc1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshab %xmm1, %xmm1, %xmm0" + - + input: + bytes: [ 0x8f, 0xe9, 0xd8, 0x98, 0x01 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshab (%rcx), %xmm4, %xmm0" + - + input: + bytes: [ 0x8f, 0xe9, 0x50, 0x98, 0x19 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpshab %xmm5, (%rcx), %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0xe0, 0x91, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotw (%rax), %xmm3, %xmm6" + - + input: + bytes: [ 0x8f, 0xe9, 0x50, 0x91, 0x0c, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotw %xmm5, (%rax, %rcx), %xmm1" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x91, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotw %xmm0, %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc1, 0x09, 0x2a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotw $42, (%rcx), %xmm1" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc1, 0x20, 0x29 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotw $41, (%rax), %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc1, 0xd9, 0x28 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotw $40, %xmm1, %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0xf0, 0x93, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotq (%rax), %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe9, 0xf0, 0x93, 0x14, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotq (%rax, %rcx), %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe9, 0x78, 0x93, 0xd1 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotq %xmm0, %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc3, 0x10, 0x2a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotq $42, (%rax), %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc3, 0x14, 0x08, 0x2a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotq $42, (%rax, %rcx), %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc3, 0xd1, 0x2a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotq $42, %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe9, 0xf8, 0x92, 0x18 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotd (%rax), %xmm0, %xmm3" + - + input: + bytes: [ 0x8f, 0xe9, 0x68, 0x92, 0x24, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotd %xmm2, (%rax, %rcx), %xmm4" + - + input: + bytes: [ 0x8f, 0xe9, 0x50, 0x92, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotd %xmm5, %xmm3, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc2, 0x31, 0x2b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotd $43, (%rcx), %xmm6" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc2, 0x3c, 0x08, 0x2c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotd $44, (%rax, %rcx), %xmm7" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc2, 0xe4, 0x2d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotd $45, %xmm4, %xmm4" + - + input: + bytes: [ 0x8f, 0xe9, 0xe8, 0x90, 0x29 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotb (%rcx), %xmm2, %xmm5" + - + input: + bytes: [ 0x8f, 0xe9, 0x50, 0x90, 0x24, 0x08 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotb %xmm5, (%rax, %rcx), %xmm4" + - + input: + bytes: [ 0x8f, 0xe9, 0x58, 0x90, 0xd3 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotb %xmm4, %xmm3, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc0, 0x18, 0x2e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotb $46, (%rax), %xmm3" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc0, 0x3c, 0x08, 0x2f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotb $47, (%rax, %rcx), %xmm7" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xc0, 0xed, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vprotb $48, %xmm5, %xmm5" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xb6, 0xe2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmadcswd %xmm1, %xmm2, %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xb6, 0x20, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmadcswd %xmm1, (%rax), %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x48, 0xa6, 0xe4, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmadcsswd %xmm1, %xmm4, %xmm6, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xa6, 0x24, 0x08, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmadcsswd %xmm1, (%rax, %rcx), %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x50, 0x95, 0xe2, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsww %xmm0, %xmm2, %xmm5, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x48, 0x95, 0x20, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsww %xmm1, (%rax), %xmm6, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x48, 0x96, 0xfd, 0x40 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacswd %xmm4, %xmm5, %xmm6, %xmm7" + - + input: + bytes: [ 0x8f, 0xe8, 0x70, 0x96, 0x10, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacswd %xmm0, (%rax), %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x68, 0x85, 0xcb, 0x40 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacssww %xmm4, %xmm3, %xmm2, %xmm1" + - + input: + bytes: [ 0x8f, 0xe8, 0x40, 0x85, 0x39, 0x60 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacssww %xmm6, (%rcx), %xmm7, %xmm7" + - + input: + bytes: [ 0x8f, 0xe8, 0x58, 0x86, 0xd2, 0x40 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsswd %xmm4, %xmm2, %xmm4, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x70, 0x86, 0x44, 0x08, 0x08, 0x00 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsswd %xmm0, 8(%rax, %rcx), %xmm1, %xmm0" + - + input: + bytes: [ 0x8f, 0xe8, 0x68, 0x87, 0xe1, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacssdql %xmm1, %xmm1, %xmm2, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x48, 0x87, 0x29, 0x70 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacssdql %xmm7, (%rcx), %xmm6, %xmm5" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0x8f, 0xca, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacssdqh %xmm3, %xmm2, %xmm0, %xmm1" + - + input: + bytes: [ 0x8f, 0xe8, 0x68, 0x8f, 0x1c, 0x08, 0x70 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacssdqh %xmm7, (%rax, %rcx), %xmm2, %xmm3" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0x8e, 0xea, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacssdd %xmm2, %xmm2, %xmm3, %xmm5" + - + input: + bytes: [ 0x8f, 0xe8, 0x70, 0x8e, 0x10, 0x40 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacssdd %xmm4, (%rax), %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x48, 0x97, 0xf8, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsdql %xmm3, %xmm0, %xmm6, %xmm7" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0x97, 0x69, 0x08, 0x50 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsdql %xmm5, 8(%rcx), %xmm3, %xmm5" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0x9f, 0xd5, 0x70 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsdqh %xmm7, %xmm5, %xmm3, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x68, 0x9f, 0x40, 0x04, 0x50 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsdqh %xmm5, 4(%rax), %xmm2, %xmm0" + - + input: + bytes: [ 0x8f, 0xe8, 0x58, 0x9e, 0xd6, 0x40 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsdd %xmm4, %xmm6, %xmm4, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x58, 0x9e, 0x1c, 0x08, 0x40 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpmacsdd %xmm4, (%rax, %rcx), %xmm4, %xmm3" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xcd, 0xe2, 0x2a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomw $42, %xmm2, %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xcd, 0x20, 0x2a ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomw $42, (%rax), %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xed, 0xe9, 0x2b ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomuw $43, %xmm1, %xmm3, %xmm5" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xed, 0x34, 0x08, 0x2c ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomuw $44, (%rax, %rcx), %xmm0, %xmm6" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xef, 0xfb, 0x2d ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomuq $45, %xmm3, %xmm3, %xmm7" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xef, 0x08, 0x2e ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomuq $46, (%rax), %xmm3, %xmm1" + - + input: + bytes: [ 0x8f, 0xe8, 0x70, 0xee, 0xd0, 0x2f ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomud $47, %xmm0, %xmm1, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x48, 0xee, 0x58, 0x04, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomud $48, 4(%rax), %xmm6, %xmm3" + - + input: + bytes: [ 0x8f, 0xe8, 0x58, 0xec, 0xeb, 0x31 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomub $49, %xmm3, %xmm4, %xmm5" + - + input: + bytes: [ 0x8f, 0xe8, 0x48, 0xec, 0x11, 0x32 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomub $50, (%rcx), %xmm6, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x78, 0xcf, 0xeb, 0x33 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomq $51, %xmm3, %xmm0, %xmm5" + - + input: + bytes: [ 0x8f, 0xe8, 0x70, 0xcf, 0x38, 0x34 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomq $52, (%rax), %xmm1, %xmm7" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xce, 0xc3, 0x35 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomd $53, %xmm3, %xmm3, %xmm0" + - + input: + bytes: [ 0x8f, 0xe8, 0x68, 0xce, 0x11, 0x36 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomd $54, (%rcx), %xmm2, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x58, 0xcc, 0xd6, 0x37 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomb $55, %xmm6, %xmm4, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xcc, 0x50, 0x08, 0x38 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcomb $56, 8(%rax), %xmm3, %xmm2" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xa3, 0xe2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpperm %xmm1, %xmm2, %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0xe0, 0xa3, 0x20, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpperm (%rax), %xmm2, %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xa3, 0x20, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpperm %xmm1, (%rax), %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xa2, 0xe2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmov %xmm1, %xmm2, %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0xe0, 0xa2, 0x20, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmov (%rax), %xmm2, %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x60, 0xa2, 0x20, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmov %xmm1, (%rax), %xmm3, %xmm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x64, 0xa2, 0xe2, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmov %ymm1, %ymm2, %ymm3, %ymm4" + - + input: + bytes: [ 0x8f, 0xe8, 0xe4, 0xa2, 0x20, 0x20 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmov (%rax), %ymm2, %ymm3, %ymm4" + - + input: + bytes: [ 0x8f, 0xe8, 0x64, 0xa2, 0x20, 0x10 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpcmov %ymm1, (%rax), %ymm3, %ymm4" + - + input: + bytes: [ 0xc4, 0xe3, 0x71, 0x49, 0xfa, 0x51 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2pd $1, %xmm5, %xmm2, %xmm1, %xmm7" + - + input: + bytes: [ 0xc4, 0xe3, 0xe1, 0x49, 0x20, 0x32 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2pd $2, (%rax), %xmm3, %xmm3, %xmm4" + - + input: + bytes: [ 0xc4, 0xe3, 0xdd, 0x49, 0x70, 0x08, 0x03 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2pd $3, 8(%rax), %ymm0, %ymm4, %ymm6" + - + input: + bytes: [ 0xc4, 0xe3, 0x71, 0x49, 0x04, 0x08, 0x30 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2pd $0, %xmm3, (%rax, %rcx), %xmm1, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0x65, 0x49, 0xe2, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2pd $1, %ymm1, %ymm2, %ymm3, %ymm4" + - + input: + bytes: [ 0xc4, 0xe3, 0x65, 0x49, 0x20, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2pd $2, %ymm1, (%rax), %ymm3, %ymm4" + - + input: + bytes: [ 0xc4, 0xe3, 0x69, 0x48, 0xcb, 0x40 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2ps $0, %xmm4, %xmm3, %xmm2, %xmm1" + - + input: + bytes: [ 0xc4, 0xe3, 0xe1, 0x48, 0x40, 0x04, 0x21 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2ps $1, 4(%rax), %xmm2, %xmm3, %xmm0" + - + input: + bytes: [ 0xc4, 0xe3, 0xd5, 0x48, 0x30, 0x12 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2ps $2, (%rax), %ymm1, %ymm5, %ymm6" + - + input: + bytes: [ 0xc4, 0xe3, 0x61, 0x48, 0x20, 0x13 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2ps $3, %xmm1, (%rax), %xmm3, %xmm4" + - + input: + bytes: [ 0xc4, 0xe3, 0x6d, 0x48, 0xd4, 0x40 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2ps $0, %ymm4, %ymm4, %ymm2, %ymm2" + - + input: + bytes: [ 0xc4, 0xe3, 0x75, 0x49, 0x40, 0x04, 0x11 ] + arch: "CS_ARCH_X86" + options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ] + expected: + insns: + - + asm_text: "vpermil2pd $1, %ymm1, 4(%rax), %ymm1, %ymm0" diff --git a/tests/Makefile b/tests/Makefile deleted file mode 100644 index 9d44f09cbb..0000000000 --- a/tests/Makefile +++ /dev/null @@ -1,203 +0,0 @@ -# Capstone Disassembler Engine -# By Nguyen Anh Quynh , 2013-2014 - -include ../config.mk -include ../functions.mk - -# Verbose output? -V ?= 0 - -INCDIR = ../include -ifndef BUILDDIR -TESTDIR = . -OBJDIR = . -LIBDIR = .. -else -TESTDIR = $(BUILDDIR)/tests -OBJDIR = $(BUILDDIR)/obj/tests -LIBDIR = $(BUILDDIR) -endif - -ifeq ($(CROSS),) -CC ?= cc -else -CC = $(CROSS)gcc -endif - - -CFLAGS += -Wall -I$(INCDIR) -LDFLAGS += -L$(LIBDIR) - -CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) -LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) - -LIBNAME = capstone - -BIN_EXT = -AR_EXT = a - -# Cygwin? -IS_CYGWIN := $(shell $(CC) -dumpmachine | grep -i cygwin | wc -l) -ifeq ($(IS_CYGWIN),1) -CFLAGS := $(CFLAGS:-fPIC=) -BIN_EXT = .exe -AR_EXT = lib -else -# mingw? -IS_MINGW := $(shell $(CC) --version 2>/dev/null | grep -i "\(mingw\|MSYS\)" | wc -l) -ifeq ($(IS_MINGW),1) -CFLAGS := $(CFLAGS:-fPIC=) -BIN_EXT = .exe -AR_EXT = lib -endif -endif - -ifeq ($(CAPSTONE_STATIC),yes) -ifeq ($(IS_MINGW),1) -ARCHIVE = $(LIBDIR)/$(LIBNAME).$(AR_EXT) -else ifeq ($(IS_CYGWIN),1) -ARCHIVE = $(LIBDIR)/$(LIBNAME).$(AR_EXT) -else -ARCHIVE = $(LIBDIR)/lib$(LIBNAME).$(AR_EXT) -endif -endif - -.PHONY: all clean - -SOURCES = test_basic.c test_detail.c test_skipdata.c test_iter.c test_customized_mnem.c -ifneq (,$(findstring arm,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_ARM -SOURCES += test_arm.c -endif -ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_AARCH64 -SOURCES += test_aarch64.c -endif -ifneq (,$(findstring m68k,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_M68K -SOURCES += test_m68k.c -endif -ifneq (,$(findstring mips,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_MIPS -SOURCES += test_mips.c -endif -ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_POWERPC -SOURCES += test_ppc.c -endif -ifneq (,$(findstring sparc,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_SPARC -SOURCES += test_sparc.c -endif -ifneq (,$(findstring systemz,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_SYSZ -SOURCES += test_systemz.c -endif -ifneq (,$(findstring x86,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_X86 -SOURCES += test_x86.c -endif -ifneq (,$(findstring xcore,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_XCORE -SOURCES += test_xcore.c -endif -ifneq (,$(findstring tms320c64x,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_TMS320C64X -SOURCES += test_tms320c64x.c -endif -ifneq (,$(findstring m680x,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_M680X -SOURCES += test_m680x.c -endif -ifneq (,$(findstring evm,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_EVM -SOURCES += test_evm.c -endif -ifneq (,$(findstring riscv,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_RISCV -SOURCES += test_riscv.c -endif -ifneq (,$(findstring wasm,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_WASM -SOURCES += test_wasm.c -endif -ifneq (,$(findstring evm,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_MOS65XX -SOURCES += test_mos65xx.c -endif -ifneq (,$(findstring bpf,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_BPF -SOURCES += test_bpf.c -endif -ifneq (,$(findstring tricore,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_TRICORE -SOURCES += test_tricore.c -endif -ifneq (,$(findstring sh,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_SH -SOURCES += test_sh.c -endif -ifneq (,$(findstring alpha,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_ALPHA -SOURCES += test_alpha.c -endif -ifneq (,$(findstring hppa,$(CAPSTONE_ARCHS))) -CFLAGS += -DCAPSTONE_HAS_HPPA -SOURCES += test_hppa.c -endif - - -OBJS = $(addprefix $(OBJDIR)/,$(SOURCES:.c=.o)) -BINARY = $(addprefix $(TESTDIR)/,$(SOURCES:.c=$(BIN_EXT))) - -all: $(BINARY) - -clean: - rm -rf $(OBJS) $(BINARY) $(TESTDIR)/*.exe $(TESTDIR)/*.static $(OBJDIR)/lib$(LIBNAME).* $(OBJDIR)/$(LIBNAME).* - rm -f *.d $(TESTDIR)/*.d $(OBJDIR)/*.d - # remove orphan files due to renaming from test.c to test_basic.c - rm -rf $(TESTDIR)/test.o $(TESTDIR)/test.exe $(TESTDIR)/test.static $(TESTDIR)/test - -$(BINARY): $(OBJS) - -$(TESTDIR)/%$(BIN_EXT): $(OBJDIR)/%.o - @mkdir -p $(@D) -ifeq ($(V),0) -ifeq ($(CAPSTONE_SHARED),yes) - $(call log,LINK,$(notdir $@)) - @$(link-dynamic) -endif -ifeq ($(CAPSTONE_STATIC),yes) - $(call log,LINK,$(notdir $(call staticname,$@))) - @$(link-static) -endif -else -ifeq ($(CAPSTONE_SHARED),yes) - $(link-dynamic) -endif -ifeq ($(CAPSTONE_STATIC),yes) - $(link-static) -endif -endif - -$(OBJDIR)/%.o: %.c - @mkdir -p $(@D) -ifeq ($(V),0) - $(call log,CC,$(@:$(OBJDIR)/%=%)) - @$(compile) -else - $(compile) -endif - - -define link-dynamic - $(CC) $(LDFLAGS) $< -l$(LIBNAME) -o $@ -endef - - -define link-static - $(CC) $(LDFLAGS) $< $(ARCHIVE) -o $(call staticname,$@) -endef - - -staticname = $(subst $(BIN_EXT),,$(1)).static$(BIN_EXT) diff --git a/tests/README b/tests/README deleted file mode 100644 index e5d3efb48c..0000000000 --- a/tests/README +++ /dev/null @@ -1,31 +0,0 @@ -This directory contains some test code to show how to use Capstone API. - -- test_basic.c - This code shows the most simple form of API where we only want to get basic - information out of disassembled instruction, such as address, mnemonic and - operand string. - -- test_detail.c: - This code shows how to access to architecture-neutral information in disassembled - instructions, such as implicit registers read/written, or groups of instructions - that this instruction belong to. - -- test_skipdata.c: - This code shows how to use SKIPDATA option to skip broken instructions (most likely - some data mixed with instructions) and continue to decode at the next legitimate - instructions. - -- test_iter.c: - This code shows how to use the API cs_disasm_iter() to decode one instruction at - a time inside a loop. - -- test_customized_mnem.c: - This code shows how to use MNEMONIC option to customize instruction mnemonic - at run-time, and then how to reset the engine to use the default mnemonic. - -- test_.c - These code show how to access architecture-specific information for each - architecture. - -- test_winkernel.cpp - This code shows how to use Capstone from a Windows driver. diff --git a/tests/README.md b/tests/README.md new file mode 100644 index 0000000000..94484d744c --- /dev/null +++ b/tests/README.md @@ -0,0 +1,159 @@ +# Testing in Capstone + +## Running tests + +### Types of test and their location + +_YAML test files_ + +These test files are consumed by the various `cstest` tools. +They contain all detail tests. As well as the LLVM regression tests (`MC` tests). + +Directories group tests by the category they intent to test. + +_Legacy (integration)_ + +Legacy tests which only printed to `stdout`. In practice they only test if the code segfaults. +Checking the produced output was not implemented. + +### Testing tools and usage + +#### `cstest` + +`cstest` is the testing tool written in C. It is implemented in `suite/cstest/` +It consumes the `yaml` files and reports errors or mismatches for disassembled instructions and their details. + +**Building** + +> _Dependencies:_ `cstest` requires the `libyaml` library. + +You build `cstest` by adding the `-DCAPSTONE_BUILD_CSTEST=1` option during configuration of the Capstone build. + +If you build and install Capstone `cstest` gets installed as well. +Otherwise you find it in the build directory. + +```bash +# Install libyaml +# sudo apt install libyaml-dev +# or +# sudo dnf install libyaml-devel +cd "" +# Optionally add the `-DENABLE_ASAN=1` flag. +cmake -B build -DCMAKE_BUILD_TYPE=Debug -DCAPSTONE_BUILD_CSTEST=ON +cmake --build build --config Debug +cmake --install build --prefix "" +``` + +Run the integration tests for `cstest` itself + +```bash +./suite/cstest/test/integration_tests.py cstest +``` + +**Run the tests** + +```bash +# Check supported options +cstest -h +# Run all +cstest tests/ +``` + +Alternatively, you can use the `CMake` test manager. + +```bash +# List available tests +ctest --test-dir build -N +# Run a specific test +ctest --test-dir build -R "" +``` + +#### `cstest_py` + +`cstest_py` is the testing tool written in Python. It is implemented in `bindings/python/cstest_py` +It consumes the `yaml` files and reports errors or mismatches for disassembled instructions and their details. + +**Installing** + +You need to install the Capstone Python bindings first and afterwards the `cstest_py`. + +```bash +# Optionally, create a new virtual environment +python3 -m venv .venv +source .venv/bin/activate + +cd bindings/python +pip install -e . +pip install -e cstest_py +cd ../.. +``` + +Run the integration tests for `cstest_py` itself + +```bash +./suite/cstest/test/integration_tests.py cstest_py +``` + +And run the tests + +```bash +# Check supported options +cstest_py -h +# Run all +cstest_py tests/ +``` + +## Add new tests + +### Unit and integration tests + +Add the source into `test/integration` or `test/unit` respectively and update the `CMakeLists.txt` file. + +### YAML + +There are very few fields which are mandatory to fill. +Check `suite/cstest/test/min_valid_test_file.yaml` to see which one. + +- In general it is useful to just copy a previous test file and rewrite it accordingly. +- If you assign C enumeration identifiers to some fields (to check enumeration values), +ensure they are added on the `suite/cstest/include/test_mapping.h`. Otherwise, `cstest` cannot map the strings +to the values for comparison. +- Rarely used, but useful fields are: `name`, `skip`, `skip_reason`. + +#### MC regression tests + +The `MCUpdater` translates most test files of the LLVM MC regression tests into our YAML files. + +The LLVM regression tests, check the bytes and assembly for all instructions of an architecture. +They do it by passing bytes or assembly to the `llvm-mc` and `FileCheck` tool and compare the output. +We capture this output and process it into YAML. +So you need to install `llvm-mc` and `FileCheck` for our updater to work. + +To update the YAML MC regression tests, you need to install `Auto-Sync` and run the `MCUpdater`. + +```bash +cd suite/auto-sync/ +# Follow install instructions of Auto-Sync described in the README +# And run the updater: +./src/autosync/MCUpdater.py -a ARCH +ls build/mc_out/ +# The produce yaml files. Copy them manually to tests/MC/ARCH +``` + +**Please note:** + +Each of the LLVM test files can contain several `llvm-mc` commands to run on the same file. +This is done to test the same file with different CPU features enabled. +So it can test different assembly flavors etc. + +In Capstone all modules enable always all CPU features (even if this is not +possible in reality). +Due to this, we always parse all `llvm-mc` commands but only write the last version of them to disk. +So if the same test file is tested with three different features enables, once with `FeatureA`, `FeatureB` and `FeatureC` +we only save the output with `FeatureC` enabled. + +This might give you MC test files which fail due to valid but mismatching disassembly. +You can set the `skip` field for those tests and add a `skip_reason`. + +Once https://github.com/capstone-engine/capstone/issues/1992 is resolved, we can +test all variants. diff --git a/tests/cs_details/issue.cs b/tests/cs_details/issue.cs deleted file mode 100644 index fc99d5e238..0000000000 --- a/tests/cs_details/issue.cs +++ /dev/null @@ -1,670 +0,0 @@ -!# issue 0 ARM operand groups 0x90,0xe8,0x0e,0x00 == ldm.w r0, {r1, r2, r3} ; -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0x90,0xe8,0x0e,0x00 == ldm.w r0, {r1, r2, r3} ; op_count: 4 ; operands[0].type: REG = r0 ; operands[0].access: READ ; operands[1].type: REG = r1 ; operands[1].access: WRITE ; operands[2].type: REG = r2 ; operands[2].access: WRITE ; operands[3].type: REG = r3 ; operands[3].access: WRITE ; Registers read: r0 ; Registers modified: r1 r2 r3 ; Groups: IsThumb2 - -!# issue 0 ARM operand groups 0x0e,0xc8 == ldm r0!, {r1, r2, r3} ; -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0x0e,0xc8 == ldm r0!, {r1, r2, r3} ; op_count: 4 ; operands[0].type: REG = r0 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r1 ; operands[1].access: WRITE ; operands[2].type: REG = r2 ; operands[2].access: WRITE ; operands[3].type: REG = r3 ; operands[3].access: WRITE ; Write-back: True ; Registers read: r0 ; Registers modified: r0 r1 r2 r3 ; Groups: IsThumb - -!# issue 0 ARM operand groups 0x00,0x2a,0xf7,0xee == vmov.f32 s5, #1.000000e+00 ; -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x00,0x2a,0xf7,0xee == vmov.f32 s5, #1.000000e+00 ; op_count: 2 ; operands[0].type: REG = s5 ; operands[0].access: WRITE ; operands[1].type: FP = 1.000000 ; Registers modified: s5 ; Groups: HasVFP3 - -!# issue 0 ARM operand groups 0x0f,0x00,0x71,0xe3 == cmn r1, #15 ; -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x0f,0x00,0x71,0xe3 == cmn r1, #0xf ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: READ ; operands[1].type: IMM = 0xf ; operands[1].access: READ ; Update-flags: True ; Registers read: r1 ; Registers modified: cpsr ; Groups: IsARM - -!# issue 0 ARM operand groups 0x03,0x20,0xb0,0xe1 == movs r2, r3 ; -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x03,0x20,0xb0,0xe1 == movs r2, r3 ; op_count: 2 ; operands[0].type: REG = r2 ; operands[0].access: WRITE ; operands[1].type: REG = r3 ; operands[1].access: READ ; Update-flags: True ; Registers read: r3 ; Registers modified: cpsr r2 ; Groups: IsARM - -!# issue 0 ARM operand groups 0xfd,0x8f == ldrh r5, [r7, #62] ; -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0xfd,0x8f == ldrh r5, [r7, #0x3e] ; op_count: 2 ; operands[0].type: REG = r5 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r7 ; operands[1].mem.disp: 0x3e ; operands[1].access: READ ; Registers read: r7 ; Registers modified: r5 ; Groups: IsThumb - -!# issue 0 ARM operand groups 0x61,0xb6 == cpsie f ; -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0x61,0xb6 == cpsie f ; CPSI-mode: 2 ; CPSI-flag: 1 ; Groups: IsThumb - -!# issue 0 ARM operand groups 0x18,0xf8,0x03,0x1e == ldrbt r1, [r8, #3] ; -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0x18,0xf8,0x03,0x1e == ldrbt r1, [r8, #3] ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r8 ; operands[1].mem.disp: 0x3 ; operands[1].access: READ ; Registers read: r8 ; Registers modified: r1 ; Groups: IsThumb2 - -!# issue 0 ARM operand groups 0xb0,0xf8,0x01,0xf1 == pldw [r0, #257] ; -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0xb0,0xf8,0x01,0xf1 == pldw [r0, #0x101] ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = r0 ; operands[0].mem.disp: 0x101 ; operands[0].access: READ ; Registers read: r0 ; Groups: IsThumb2 HasV7 HasMP - -!# issue 0 ARM operand groups 0xd3,0xe8,0x08,0xf0 == tbb [r3, r8] ; -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0xd3,0xe8,0x08,0xf0 == tbb [r3, r8] ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = r3 ; operands[0].mem.index: REG = r8 ; operands[0].access: READ ; Registers read: r3 r8 ; Groups: jump IsThumb2 - -!# issue 0 ARM operand groups 0xd3,0xe8,0x18,0xf0 == tbh [r3, r8, lsl #1] ; -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0xd3,0xe8,0x18,0xf0 == tbh [r3, r8, lsl #1] ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = r3 ; operands[0].mem.index: REG = r8 ; operands[0].mem.lshift: 0x1 ; operands[0].access: READ ; Shift: 2 = 1 ; Registers read: r3 r8 ; Groups: jump IsThumb2 - -!# issue 0 ARM operand groups 0xaf,0xf3,0x43,0x85 == cpsie i, #3 ; -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0xaf,0xf3,0x43,0x85 == cpsie i, #3 ; cpsie i, #3 ; op_count: 1 ; operands[0].type: IMM = 0x3 ; operands[0].access: READ ; CPSI-mode: 2 ; CPSI-flag: 2 ; Groups: IsThumb2 IsNotMClass - -!# issue 0 ARM operand groups 0xbf,0xf3,0x6f,0x8f == isb sy ; -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0xbf,0xf3,0x6f,0x8f == isb sy ; isb sy ; Memory-barrier: 15 ; Groups: IsThumb HasDB - -!# issue 0 ARM operand groups 0x59,0xea,0x7b,0x89 == csel r9, r9, r11, vc ; -!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_V8, CS_OPT_DETAIL -0x59,0xea,0x7b,0x89 == csel r9, r9, r11, vc ; op_count: 3 ; operands[0].type: REG = r9 ; operands[0].access: WRITE ; operands[1].type: REG = r9 ; operands[1].access: READ ; operands[2].type: REG = r11 ; operands[2].access: READ ; Code condition: 7 ; Registers read: cpsr r9 r11 ; Registers modified: r9 ; Groups: HasV8_1MMainline - -!# issue 0 ARM operand groups 0xbf,0xf3,0x56,0x8f == dmb nshst ; -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0xbf,0xf3,0x56,0x8f == dmb nshst ; dmb nshst ; Memory-barrier: 6 ; Groups: IsThumb HasDB - -!# issue 0 ARM operand groups 0x31,0xfa,0x02,0xf2 == lsrs.w r2, r1, r2 ; -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0x31,0xfa,0x02,0xf2 == lsrs.w r2, r1, r2 ; op_count: 3 ; operands[0].type: REG = r2 ; operands[0].access: WRITE ; operands[1].type: REG = r1 ; operands[1].access: READ ; operands[2].type: REG = r2 ; operands[2].access: READ ; Update-flags: True ; Registers read: r1 r2 ; Registers modified: cpsr r2 ; Groups: IsThumb2 - -!# issue 0 ARM operand groups 0x5f,0xf0,0x0c,0x01 == movseq.w r1, #12 ; -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0x08,0xbf == it eq ; Code condition: 0 ; Predicate Mask: 0x1 ; Registers modified: itstate ; Groups: IsThumb2 -0x5f,0xf0,0x0c,0x01 == movseq.w r1, #0xc ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: IMM = 0xc ; operands[1].access: READ ; Code condition: 0 ; Update-flags: True ; Registers modified: cpsr r1 ; Groups: IsThumb2 - -!# issue 0 ARM operand groups 0x52,0xe8,0x01,0x1f == ldrex r1, [r2, #4] ; -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0x52,0xe8,0x01,0x1f == ldrex r1, [r2, #4] ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r2 ; operands[1].mem.disp: 0x4 ; operands[1].access: READ ; Registers read: r2 ; Registers modified: r1 ; Groups: IsThumb HasV8MBaseline - -!# issue 0 ARM operand groups 0xdf,0xec,0x1d,0x1a == vscclrmhi {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr} ; -!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_V8, CS_OPT_DETAIL -0x88,0xbf == it hi ; Code condition: 8 ; Predicate Mask: 0x1 ; Groups: IsThumb2 -0xdf,0xec,0x1d,0x1a == vscclrmhi {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr} ; op_count: 30 ; operands[0].type: REG = s3 ; operands[0].access: WRITE ; operands[1].type: REG = s4 ; operands[1].access: WRITE ; operands[2].type: REG = s5 ; operands[2].access: WRITE ; operands[3].type: REG = s6 ; operands[3].access: WRITE ; operands[4].type: REG = s7 ; operands[4].access: WRITE ; operands[5].type: REG = s8 ; operands[5].access: WRITE ; operands[6].type: REG = s9 ; operands[6].access: WRITE ; operands[7].type: REG = s10 ; operands[7].access: WRITE ; operands[8].type: REG = s11 ; operands[8].access: WRITE ; operands[9].type: REG = s12 ; operands[9].access: WRITE ; operands[10].type: REG = s13 ; operands[10].access: WRITE ; operands[11].type: REG = s14 ; operands[11].access: WRITE ; operands[12].type: REG = s15 ; operands[12].access: WRITE ; operands[13].type: REG = s16 ; operands[13].access: WRITE ; operands[14].type: REG = s17 ; operands[14].access: WRITE ; operands[15].type: REG = s18 ; operands[15].access: WRITE ; operands[16].type: REG = s19 ; operands[16].access: WRITE ; operands[17].type: REG = s20 ; operands[17].access: WRITE ; operands[18].type: REG = s21 ; operands[18].access: WRITE ; operands[19].type: REG = s22 ; operands[19].access: WRITE ; operands[20].type: REG = s23 ; operands[20].access: WRITE ; operands[21].type: REG = s24 ; operands[21].access: WRITE ; operands[22].type: REG = s25 ; operands[22].access: WRITE ; operands[23].type: REG = s26 ; operands[23].access: WRITE ; operands[24].type: REG = s27 ; operands[24].access: WRITE ; operands[25].type: REG = s28 ; operands[25].access: WRITE ; operands[26].type: REG = s29 ; operands[26].access: WRITE ; operands[27].type: REG = s30 ; operands[27].access: WRITE ; operands[28].type: REG = s31 ; operands[28].access: WRITE ; operands[29].type: REG = vpr ; operands[29].access: WRITE ; Code condition: 8 ; Registers modified: s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 vpr ; Groups: HasV8_1MMainline Has8MSecExt - -!# issue 0 ARM operand groups 0x9f,0xec,0x06,0x5b == vscclrm {d5, d6, d7, vpr} ; -!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_V8, CS_OPT_DETAIL -0x9f,0xec,0x06,0x5b == vscclrm {d5, d6, d7, vpr} ; op_count: 4 ; operands[0].type: REG = d5 ; operands[0].access: WRITE ; operands[1].type: REG = d6 ; operands[1].access: WRITE ; operands[2].type: REG = d7 ; operands[2].access: WRITE ; operands[3].type: REG = vpr ; operands[3].access: WRITE ; Registers modified: d5 d6 d7 vpr ; Groups: HasV8_1MMainline Has8MSecExt - -!# issue 0 ARM operand groups 0xbc,0xfd,0x7f,0xaf == vldrh.u32 q5, [r4, #254]! ; -!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_V8 | CS_MODE_MCLASS, CS_OPT_DETAIL -0xbc,0xfd,0x7f,0xaf == vldrh.u32 q5, [r4, #0xfe]! ; op_count: 2 ; operands[0].type: REG = q5 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r4 ; operands[1].mem.disp: 0xfe ; operands[1].access: READ ; Write-back: True ; Registers read: r4 ; Registers modified: r4 q5 ; Groups: HasMVEInt - -!# issue 0 ARM operand groups 0x80,0xfc,0x80,0x1e == vst20.16 {q0, q1}, [r0] ; -!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_MCLASS, CS_OPT_DETAIL -0x80,0xfc,0x80,0x1e == vst20.16 {q0, q1}, [r0] ; op_count: 3 ; operands[0].type: REG = q0 ; operands[0].access: READ ; operands[1].type: REG = q1 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = r0 ; operands[2].access: WRITE ; Registers read: q0 q1 r0 ; Groups: HasMVEInt - -!# issue 0 ARM operand groups 0x98,0xfc,0x4e,0x08 == vcadd.f32 q0, q4, q7, #90 ; -!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_MCLASS, CS_OPT_DETAIL -0x98,0xfc,0x4e,0x08 == vcadd.f32 q0, q4, q7, #90 ; op_count: 4 ; operands[0].type: REG = q0 ; operands[0].access: READ | WRITE ; operands[1].type: REG = q4 ; operands[1].access: READ ; operands[2].type: REG = q7 ; operands[2].access: READ ; operands[3].type: IMM = 0x5a ; operands[3].access: READ ; Registers read: q0 q4 q7 ; Registers modified: q0 ; Groups: HasMVEFloat - -!# issue 0 ARM operand groups 0x94,0xfd,0x46,0x48 == vcadd.f32 q2, q2, q3, #270 ; -!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_V8, CS_OPT_DETAIL -0x94,0xfd,0x46,0x48 == vcadd.f32 q2, q2, q3, #270 ; op_count: 4 ; operands[0].type: REG = q2 ; operands[0].access: WRITE ; operands[1].type: REG = q2 ; operands[1].access: READ ; operands[2].type: REG = q3 ; operands[2].access: READ ; operands[3].type: IMM = 0x10e ; operands[3].access: READ ; Registers read: q2 q3 ; Registers modified: q2 ; Groups: HasNEON HasV8_3a - -!# issue 0 ARM operand groups 0x9d,0xec,0x82,0x6e == vldrb.s16 q3, [sp, q1] ; -!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_MCLASS, CS_OPT_DETAIL -0x9d,0xec,0x82,0x6e == vldrb.s16 q3, [sp, q1] ; op_count: 2 ; operands[0].type: REG = q3 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r13 ; operands[1].mem.index: REG = q1 ; operands[1].access: READ ; Registers read: r13 q1 ; Registers modified: q3 ; Groups: HasMVEInt - -!# issue 0 ARM operand groups 0x90,0xec,0x12,0x6f == vldrh.s32 q3, [r0, q1] ; -!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_MCLASS, CS_OPT_DETAIL -0x90,0xec,0x12,0x6f == vldrh.s32 q3, [r0, q1] ; op_count: 2 ; operands[0].type: REG = q3 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r0 ; operands[1].mem.index: REG = q1 ; operands[1].access: READ ; Registers read: r0 q1 ; Registers modified: q3 ; Groups: HasMVEInt - -!# issue 0 ARM operand groups 0x5f,0xea,0x2d,0x83 == sqrshrl lr, r3, #64, r8 ; -!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_V8 | CS_MODE_MCLASS, CS_OPT_DETAIL -0x5f,0xea,0x2d,0x83 == sqrshrl lr, r3, #0x40, r8 ; op_count: 4 ; operands[0].type: REG = r14 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r3 ; operands[1].access: READ | WRITE ; operands[2].type: IMM = 0x40 ; operands[2].access: READ ; operands[3].type: REG = r8 ; operands[3].access: READ ; Write-back: True ; Registers read: r14 r3 r8 ; Registers modified: r14 r3 ; Groups: HasV8_1MMainline HasMVEInt - -!# issue 0 ARM operand groups 0x82,0xfd,0x21,0xff == vstrd.64 q7, [q1, #264] ; -!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_MCLASS, CS_OPT_DETAIL -0x82,0xfd,0x21,0xff == vstrd.64 q7, [q1, #0x108] ; op_count: 2 ; operands[0].type: REG = q7 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = q1 ; operands[1].mem.disp: 0x108 ; operands[1].access: WRITE ; Registers read: q7 q1 ; Groups: HasMVEInt - -!# issue 0 ARM operand groups 0x06,0x16,0x72,0xe6 == ldrbt r1, [r2], -r6, lsl #12 ; -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x06,0x16,0x72,0xe6 == ldrbt r1, [r2], -r6, lsl #12 ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r2 ; operands[1].mem.index: REG = r6 ; operands[1].access: READ ; Shift: 2 = 12 ; Subtracted: True ; Write-back: True ; Registers read: r2 r6 ; Registers modified: r2 r1 ; Groups: IsARM - -!# issue 0 ARM operand groups 0xf6,0x50,0x33,0xe1 == ldrsh r5, [r3, -r6]! ; -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0xf6,0x50,0x33,0xe1 == ldrsh r5, [r3, -r6]! ; op_count: 2 ; operands[0].type: REG = r5 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r3 ; operands[1].mem.index: REG = r6 ; operands[1].access: READ ; Subtracted: True ; Write-back: True ; Registers read: r3 r6 ; Registers modified: r3 r5 ; Groups: IsARM - -!# issue 0 ARM operand groups 0x1e,0x19,0x7a,0xfd == ldc2l p9, c1, [r10, #-120]! ; -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x1e,0x19,0x7a,0xfd == ldc2l p9, c1, [r10, #-0x78]! ; op_count: 3 ; operands[0].type: P-IMM = 9 ; operands[0].access: READ ; operands[1].type: C-IMM = 1 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = r10 ; operands[2].mem.disp: 0x78 ; operands[2].access: READ ; Registers read: r10 ; Registers modified: r10 ; Groups: IsARM PreV8 - -!# issue 0 ARM operand groups 0x12,0x31,0x7c,0xfc == ldc2l p1, c3, [r12], #-72 ; -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x12,0x31,0x7c,0xfc == ldc2l p1, c3, [r12], #-0x48 ; op_count: 3 ; operands[0].type: P-IMM = 1 ; operands[0].access: READ ; operands[1].type: C-IMM = 3 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = r12 ; operands[2].access: READ ; operands[2].mem.disp: 0x48 ; Subtracted: True ; Registers read: r12 ; Groups: IsARM PreV8 - -!# issue 0 ARM operand groups 0xa4,0xf9,0x6d,0x0e == vld3.16 {d0[], d2[], d4[]}, [r4]! ; -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0xa4,0xf9,0x6d,0x0e == vld3.16 {d0[], d2[], d4[]}, [r4]! ; op_count: 4 ; operands[0].type: REG = d0 ; operands[0].access: WRITE ; operands[1].type: REG = d2 ; operands[1].access: WRITE ; operands[2].type: REG = d4 ; operands[2].access: WRITE ; operands[3].type: MEM ; operands[3].mem.base: REG = r4 ; operands[3].access: READ | WRITE ; Write-back: True ; Registers read: r4 ; Registers modified: r4 d0 d2 d4 - -!# issue 0 ARM operand groups 0x0d,0x50,0x66,0xe4 == strbt r5, [r6], #-13 ; -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x0d,0x50,0x66,0xe4 == strbt r5, [r6], #-0xd ; op_count: 2 ; operands[0].type: REG = r5 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = r6 ; operands[1].access: WRITE ; operands[1].mem.disp: 0xd ; Subtracted: True ; Write-back: True ; Registers read: r5 r6 ; Registers modified: r6 ; Groups: IsARM - -!# issue 0 ARM operand groups 0x00,0x10,0x4f,0xe2 == sub r1, pc, #0 ; -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x00,0x10,0x4f,0xe2 == sub r1, pc, #0 ; op_count: 3 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: REG = r15 ; operands[1].access: READ ; operands[2].type: IMM = 0x0 ; operands[2].access: READ ; Registers read: r15 ; Registers modified: r1 ; Groups: IsARM - -!# issue 0 ARM operand groups 0x9f,0x51,0xd3,0xe7 == bfc r5, #3, #17 ; -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x9f,0x51,0xd3,0xe7 == bfc r5, #3, #0x11 ; op_count: 3 ; operands[0].type: REG = r5 ; operands[0].access: READ | WRITE ; operands[1].type: IMM = 0x3 ; operands[1].access: READ ; operands[2].type: IMM = 0x11 ; operands[2].access: READ ; Write-back: True ; Registers read: r5 ; Registers modified: r5 ; Groups: IsARM HasV6T2 - -!# issue 0 ARM operand groups 0xd8,0xe8,0xff,0x67 == ldaexd r6, r7, [r8] ; -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0xd8,0xe8,0xff,0x67 == ldaexd r6, r7, [r8] ; op_count: 3 ; operands[0].type: REG = r6 ; operands[0].access: WRITE ; operands[1].type: REG = r7 ; operands[1].access: WRITE ; operands[2].type: MEM ; operands[2].mem.base: REG = r8 ; operands[2].access: READ ; Registers read: r8 ; Registers modified: r6 r7 ; Groups: IsThumb HasAcquireRelease HasV7Clrex IsNotMClass - -!# issue 0 ARM operand groups 0x30,0x0f,0xa6,0xe6 == ssat16 r0, #7, r0 ; -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x30,0x0f,0xa6,0xe6 == ssat16 r0, #7, r0 ; op_count: 3 ; operands[0].type: REG = r0 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x7 ; operands[1].access: READ ; operands[2].type: REG = r0 ; operands[2].access: READ ; Registers read: r0 ; Registers modified: r0 ; Groups: IsARM HasV6 - -!# issue 0 ARM operand groups 0x9a,0x8f,0xa0,0xe6 == ssat r8, #1, r10, lsl #31 ; -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x9a,0x8f,0xa0,0xe6 == ssat r8, #1, r10, lsl #0x1f ; op_count: 3 ; operands[0].type: REG = r8 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x1 ; operands[1].access: READ ; operands[2].type: REG = r10 ; operands[2].access: READ ; Shift: 2 = 31 ; Registers read: r10 ; Registers modified: r8 ; Groups: IsARM HasV6 - -!# issue 0 ARM operand groups 0x40,0x1b,0xf5,0xee == vcmp.f64 d17, #0 ; -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x40,0x1b,0xf5,0xee == vcmp.f64 d17, #0 ; op_count: 2 ; operands[0].type: REG = d17 ; operands[0].access: READ ; operands[1].type: IMM = 0x0 ; operands[1].access: READ ; Update-flags: True ; Registers read: d17 ; Registers modified: fpscr_nzcv ; Groups: HasVFP2 HasDPVFP - -!# issue 0 ARM operand groups 0x05,0xf0,0x2f,0xe3 == msr CPSR_fsxc, #5 ; -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x05,0xf0,0x2f,0xe3 == msr cpsr_fsxc, #5 ; op_count: 2 ; operands[0].type: CPSR = fsxc ; operands[0].type: MASK = 15 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x5 ; operands[1].access: READ ; Update-flags: True ; Registers modified: cpsr ; Groups: IsARM - -!# issue 0 ARM operand groups 0xa4,0xf9,0xed,0x0b == vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! ; -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0xa4,0xf9,0xed,0x0b == vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:0x80]! ; op_count: 5 ; operands[0].type: REG = d0 ; operands[0].neon_lane = 1 ; operands[0].access: READ | WRITE ; operands[1].type: REG = d2 ; operands[1].neon_lane = 1 ; operands[1].access: READ | WRITE ; operands[2].type: REG = d4 ; operands[2].neon_lane = 1 ; operands[2].access: READ | WRITE ; operands[3].type: REG = d6 ; operands[3].neon_lane = 1 ; operands[3].access: READ | WRITE ; operands[4].type: MEM ; operands[4].mem.base: REG = r4 ; operands[4].mem.align: 0x80 ; operands[4].access: READ | WRITE ; Write-back: True ; Registers read: d0 d2 d4 d6 r4 ; Registers modified: r4 d0 d2 d4 d6 - -!# issue 0 ARM operand groups 0x42,0x03,0xb0,0xf3 == aesd.8 q0, q1 ; -!# CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8, CS_OPT_DETAIL -0x42,0x03,0xb0,0xf3 == aesd.8 q0, q1 ; op_count: 2 ; operands[0].type: REG = q0 ; operands[0].access: READ | WRITE ; operands[1].type: REG = q1 ; operands[1].access: READ ; Write-back: True ; Registers read: q0 q1 ; Registers modified: q0 ; Groups: HasV8 HasAES - -!# issue 0 ARM operand groups 0x11,0x57,0x54,0xfc == mrrc2 p7, #1, r5, r4, c1 ; -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x11,0x57,0x54,0xfc == mrrc2 p7, #1, r5, r4, c1 ; op_count: 5 ; operands[0].type: P-IMM = 7 ; operands[0].access: READ ; operands[1].type: IMM = 0x1 ; operands[1].access: READ ; operands[2].type: REG = r5 ; operands[2].access: WRITE ; operands[3].type: REG = r4 ; operands[3].access: WRITE ; operands[4].type: C-IMM = 1 ; operands[4].access: READ ; Registers modified: r5 r4 ; Groups: IsARM PreV8 - -!# issue 0 ARM operand groups 0xd3,0x2f,0x82,0xe6 == pkhtb r2, r2, r3, asr #31 ; -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0xd3,0x2f,0x82,0xe6 == pkhtb r2, r2, r3, asr #0x1f ; op_count: 3 ; operands[0].type: REG = r2 ; operands[0].access: WRITE ; operands[1].type: REG = r2 ; operands[1].access: READ ; operands[2].type: REG = r3 ; operands[2].access: READ ; Shift: 1 = 31 ; Registers read: r2 r3 ; Registers modified: r2 ; Groups: IsARM HasV6 - -!# issue 0 ARM operand groups 0x93,0x27,0x82,0xe6 == pkhbt r2, r2, r3, lsl #15 ; -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x93,0x27,0x82,0xe6 == pkhbt r2, r2, r3, lsl #0xf ; op_count: 3 ; operands[0].type: REG = r2 ; operands[0].access: WRITE ; operands[1].type: REG = r2 ; operands[1].access: READ ; operands[2].type: REG = r3 ; operands[2].access: READ ; Shift: 2 = 15 ; Registers read: r2 r3 ; Registers modified: r2 ; Groups: IsARM HasV6 - -!# issue 0 ARM operand groups 0xb4,0x10,0xf0,0xe0 == ldrht r1, [r0], #4 ; -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0xb4,0x10,0xf0,0xe0 == ldrht r1, [r0], #4 ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r0 ; operands[1].access: READ ; operands[1].mem.disp: 0x4 ; Write-back: True ; Registers read: r0 ; Registers modified: r0 r1 ; Groups: IsARM - -!# issue 0 ARM operand groups 0x2f,0xfa,0xa1,0xf3 == sxtb16 r3, r1, ror #16 ; -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0x2f,0xfa,0xa1,0xf3 == sxtb16 r3, r1, ror #16 ; op_count: 2 ; operands[0].type: REG = r3 ; operands[0].access: WRITE ; operands[1].type: REG = r1 ; operands[1].access: READ ; Shift: 4 = 16 ; Registers read: r1 ; Registers modified: r3 ; Groups: HasDSP IsThumb2 - -!# issue 0 ARM operand groups 0x00,0x02,0x01,0xf1 == setend be ; -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0x00,0x02,0x01,0xf1 == setend be ; op_count: 1 ; operands[0].type: SETEND = be ; Groups: IsARM - -!# issue 0 ARM operand groups 0xd0,0xe8,0xaf,0x0f == lda r0, [r0] -!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL -0xd0,0xe8,0xaf,0x0f == lda r0, [r0] ; op_count: 2 ; operands[0].type: REG = r0 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r0 ; operands[1].access: READ ; Registers read: r0 ; Registers modified: r0 ; Groups: IsThumb HasAcquireRelease - -!# issue 0 ARM operand groups 0xef,0xf3,0x11,0x85 == ldrhi pc, [r1, #-0x3ef] -!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL -0xef,0xf3,0x11,0x85 == ldrhi pc, [r1, #-0x3ef] ; op_count: 2 ; operands[0].type: REG = r15 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r1 ; operands[1].mem.disp: 0x3ef ; operands[1].access: READ ; Code condition: 8 ; Registers read: cpsr r1 ; Registers modified: r15 ; Groups: IsARM jump - -!# issue 0 PPC operand groups 0x54,0x22,0xe0,0x06 == slwi r2, r1, 0x1c -!# CS_ARCH_PPC, CS_MODE_32 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL -0x54,0x22,0xe0,0x06 == slwi r2, r1, 0x1c ; op_count: 3 ; operands[0].type: REG = r2 ; operands[1].type: REG = r1 ; operands[2].type: IMM = 0x1c - -!# issue 0 PPC operand groups 0x54,0x66,0xf0,0xbe == srwi r6, r3, 2 -!# CS_ARCH_PPC, CS_MODE_32 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL -0x54,0x66,0xf0,0xbe == srwi r6, r3, 2 ; op_count: 3 ; operands[0].type: REG = r6 ; operands[1].type: REG = r3 ; operands[2].type: IMM = 0x2 - -!# issue 0 PPC operand groups 0x78,0x62,0x26,0xe4 == sldi r2, r3, 4 -!# CS_ARCH_PPC, CS_MODE_32 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL -0x78,0x62,0x26,0xe4 == sldi r2, r3, 4 ; op_count: 3 ; operands[0].type: REG = r2 ; operands[1].type: REG = r3 ; operands[2].type: IMM = 0x4 - -!# issue 0 RISCV operand groups 0x37,0x34,0x00,0x00 == lui s0, 3 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x37,0x34,0x00,0x00 == lui s0, 3 ; op_count: 2 ; operands[0].type: REG = s0 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x3 ; operands[1].access: READ - -!# issue 0 RISCV operand groups 0x97,0x82,0x00,0x00 == auipc t0, 8 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x97,0x82,0x00,0x00 == auipc t0, 8 ; op_count: 2 ; operands[0].type: REG = t0 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x8 ; operands[1].access: READ - -!# issue 0 RISCV operand groups 0xef,0x00,0x80,0x00 == jal 8 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xef,0x00,0x80,0x00 == jal 8 ; op_count: 1 ; operands[0].type: IMM = 0x8 ; operands[0].access: READ ; Groups: call - -!# issue 0 RISCV operand groups 0xef,0xf0,0x1f,0xff == jal -0x10 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xef,0xf0,0x1f,0xff == jal -0x10 ; op_count: 1 ; operands[0].type: IMM = 0xfffffff0 ; operands[0].access: READ ; Groups: call - -!# issue 0 RISCV operand groups 0xe7,0x00,0x45,0x00 == jalr ra, a0, 4 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xe7,0x00,0x45,0x00 == jalr ra, a0, 4 ; op_count: 3 ; operands[0].type: REG = ra ; operands[0].access: WRITE ; operands[1].type: REG = a0 ; operands[1].access: READ ; operands[2].type: IMM = 0x4 ; operands[2].access: READ ; Groups: call - -!# issue 0 RISCV operand groups 0xe7,0x00,0xc0,0xff == jalr ra, zero, -4 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xe7,0x00,0xc0,0xff == jalr ra, zero, -4 ; op_count: 3 ; operands[0].type: REG = ra ; operands[0].access: WRITE ; operands[1].type: REG = zero ; operands[1].access: READ ; operands[2].type: IMM = 0xfffffffc ; operands[2].access: READ ; Groups: call - -!# issue 0 RISCV operand groups 0x63,0x05,0x41,0x00 == beq sp, tp, 0xa -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x63,0x05,0x41,0x00 == beq sp, tp, 0xa ; op_count: 3 ; operands[0].type: REG = sp ; operands[0].access: READ ; operands[1].type: REG = tp ; operands[1].access: READ ; operands[2].type: IMM = 0xa ; operands[2].access: READ ; Groups: branch_relative jump - -!# issue 0 RISCV operand groups 0xe3,0x9d,0x61,0xfe == bne gp, t1, -6 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xe3,0x9d,0x61,0xfe == bne gp, t1, -6 ; op_count: 3 ; operands[0].type: REG = gp ; operands[0].access: READ ; operands[1].type: REG = t1 ; operands[1].access: READ ; operands[2].type: IMM = 0xfffffffa ; operands[2].access: READ ; Groups: branch_relative jump - -!# issue 0 RISCV operand groups 0x63,0xca,0x93,0x00 == blt t2, s1, 0x14 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x63,0xca,0x93,0x00 == blt t2, s1, 0x14 ; op_count: 3 ; operands[0].type: REG = t2 ; operands[0].access: READ ; operands[1].type: REG = s1 ; operands[1].access: READ ; operands[2].type: IMM = 0x14 ; operands[2].access: READ ; Groups: branch_relative jump - -!# issue 0 RISCV operand groups 0x63,0x53,0xb5,0x00 == bge a0, a1, 6 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x63,0x53,0xb5,0x00 == bge a0, a1, 6 ; op_count: 3 ; operands[0].type: REG = a0 ; operands[0].access: READ ; operands[1].type: REG = a1 ; operands[1].access: READ ; operands[2].type: IMM = 0x6 ; operands[2].access: READ ; Groups: branch_relative jump - -!# issue 0 RISCV operand groups 0x63,0x65,0xd6,0x00 == bltu a2, a3, 0xa -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x63,0x65,0xd6,0x00 == bltu a2, a3, 0xa ; op_count: 3 ; operands[0].type: REG = a2 ; operands[0].access: READ ; operands[1].type: REG = a3 ; operands[1].access: READ ; operands[2].type: IMM = 0xa ; operands[2].access: READ ; Groups: branch_relative jump - -!# issue 0 RISCV operand groups 0x63,0x76,0xf7,0x00 == bgeu a4, a5, 0xc -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x63,0x76,0xf7,0x00 == bgeu a4, a5, 0xc ; op_count: 3 ; operands[0].type: REG = a4 ; operands[0].access: READ ; operands[1].type: REG = a5 ; operands[1].access: READ ; operands[2].type: IMM = 0xc ; operands[2].access: READ ; Groups: branch_relative jump - -!# issue 0 RISCV operand groups 0x03,0x88,0x18,0x00 == lb a6, 1(a7) -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x03,0x88,0x18,0x00 == lb a6, 1(a7) ; op_count: 2 ; operands[0].type: REG = a6 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = a7 ; operands[1].mem.disp: 0x1 ; operands[1].access: READ - -!# issue 0 RISCV operand groups 0x03,0x99,0x49,0x00 == lh s2, 4(s3) -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x03,0x99,0x49,0x00 == lh s2, 4(s3) ; op_count: 2 ; operands[0].type: REG = s2 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = s3 ; operands[1].mem.disp: 0x4 ; operands[1].access: READ - -!# issue 0 RISCV operand groups 0x03,0xaa,0x6a,0x00 == lw s4, 6(s5) -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x03,0xaa,0x6a,0x00 == lw s4, 6(s5) ; op_count: 2 ; operands[0].type: REG = s4 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = s5 ; operands[1].mem.disp: 0x6 ; operands[1].access: READ - -!# issue 0 RISCV operand groups 0x03,0xcb,0x2b,0x01 == lbu s6, 0x12(s7) -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x03,0xcb,0x2b,0x01 == lbu s6, 0x12(s7) ; op_count: 2 ; operands[0].type: REG = s6 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = s7 ; operands[1].mem.disp: 0x12 ; operands[1].access: READ - -!# issue 0 RISCV operand groups 0x03,0xdc,0x8c,0x01 == lhu s8, 0x18(s9) -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x03,0xdc,0x8c,0x01 == lhu s8, 0x18(s9) ; op_count: 2 ; operands[0].type: REG = s8 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = s9 ; operands[1].mem.disp: 0x18 ; operands[1].access: READ - -!# issue 0 RISCV operand groups 0x23,0x86,0xad,0x03 == sb s10, 0x2c(s11) -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x23,0x86,0xad,0x03 == sb s10, 0x2c(s11) ; op_count: 2 ; operands[0].type: REG = s10 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = s11 ; operands[1].mem.disp: 0x2c ; operands[1].access: WRITE - -!# issue 0 RISCV operand groups 0x23,0x9a,0xce,0x03 == sh t3, 0x34(t4) -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x23,0x9a,0xce,0x03 == sh t3, 0x34(t4) ; op_count: 2 ; operands[0].type: REG = t3 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = t4 ; operands[1].mem.disp: 0x34 ; operands[1].access: WRITE - -!# issue 0 RISCV operand groups 0x23,0x8f,0xef,0x01 == sb t5, 0x1e(t6) -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x23,0x8f,0xef,0x01 == sb t5, 0x1e(t6) ; op_count: 2 ; operands[0].type: REG = t5 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = t6 ; operands[1].mem.disp: 0x1e ; operands[1].access: WRITE - -!# issue 0 RISCV operand groups 0x93,0x00,0xe0,0x00 == addi ra, zero, 0xe -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x93,0x00,0xe0,0x00 == addi ra, zero, 0xe ; op_count: 3 ; operands[0].type: REG = ra ; operands[0].access: WRITE ; operands[1].type: REG = zero ; operands[1].access: READ ; operands[2].type: IMM = 0xe ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0x13,0xa1,0x01,0x01 == slti sp, gp, 0x10 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x13,0xa1,0x01,0x01 == slti sp, gp, 0x10 ; op_count: 3 ; operands[0].type: REG = sp ; operands[0].access: WRITE ; operands[1].type: REG = gp ; operands[1].access: READ ; operands[2].type: IMM = 0x10 ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0x13,0xb2,0x02,0x7d == sltiu tp, t0, 0x7d0 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x13,0xb2,0x02,0x7d == sltiu tp, t0, 0x7d0 ; op_count: 3 ; operands[0].type: REG = tp ; operands[0].access: WRITE ; operands[1].type: REG = t0 ; operands[1].access: READ ; operands[2].type: IMM = 0x7d0 ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0x13,0xc3,0x03,0xdd == xori t1, t2, -0x230 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x13,0xc3,0x03,0xdd == xori t1, t2, -0x230 ; op_count: 3 ; operands[0].type: REG = t1 ; operands[0].access: WRITE ; operands[1].type: REG = t2 ; operands[1].access: READ ; operands[2].type: IMM = 0xfffffdd0 ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0x13,0xe4,0xc4,0x12 == ori s0, s1, 0x12c -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x13,0xe4,0xc4,0x12 == ori s0, s1, 0x12c ; op_count: 3 ; operands[0].type: REG = s0 ; operands[0].access: WRITE ; operands[1].type: REG = s1 ; operands[1].access: READ ; operands[2].type: IMM = 0x12c ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0x13,0xf5,0x85,0x0c == andi a0, a1, 0xc8 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x13,0xf5,0x85,0x0c == andi a0, a1, 0xc8 ; op_count: 3 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; operands[2].type: IMM = 0xc8 ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0x13,0x96,0xe6,0x01 == slli a2, a3, 0x1e -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x13,0x96,0xe6,0x01 == slli a2, a3, 0x1e ; op_count: 3 ; operands[0].type: REG = a2 ; operands[0].access: WRITE ; operands[1].type: REG = a3 ; operands[1].access: READ ; operands[2].type: IMM = 0x1e ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0x13,0xd7,0x97,0x01 == srli a4, a5, 0x19 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x13,0xd7,0x97,0x01 == srli a4, a5, 0x19 ; op_count: 3 ; operands[0].type: REG = a4 ; operands[0].access: WRITE ; operands[1].type: REG = a5 ; operands[1].access: READ ; operands[2].type: IMM = 0x19 ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0x13,0xd8,0xf8,0x40 == srai a6, a7, 0xf -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x13,0xd8,0xf8,0x40 == srai a6, a7, 0xf ; op_count: 3 ; operands[0].type: REG = a6 ; operands[0].access: WRITE ; operands[1].type: REG = a7 ; operands[1].access: READ ; operands[2].type: IMM = 0xf ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0x33,0x89,0x49,0x01 == add s2, s3, s4 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x33,0x89,0x49,0x01 == add s2, s3, s4 ; op_count: 3 ; operands[0].type: REG = s2 ; operands[0].access: WRITE ; operands[1].type: REG = s3 ; operands[1].access: READ ; operands[2].type: REG = s4 ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0xb3,0x0a,0x7b,0x41 == sub s5, s6, s7 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xb3,0x0a,0x7b,0x41 == sub s5, s6, s7 ; op_count: 3 ; operands[0].type: REG = s5 ; operands[0].access: WRITE ; operands[1].type: REG = s6 ; operands[1].access: READ ; operands[2].type: REG = s7 ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0x33,0xac,0xac,0x01 == slt s8, s9, s10 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x33,0xac,0xac,0x01 == slt s8, s9, s10 ; op_count: 3 ; operands[0].type: REG = s8 ; operands[0].access: WRITE ; operands[1].type: REG = s9 ; operands[1].access: READ ; operands[2].type: REG = s10 ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0xb3,0x3d,0xde,0x01 == sltu s11, t3, t4 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xb3,0x3d,0xde,0x01 == sltu s11, t3, t4 ; op_count: 3 ; operands[0].type: REG = s11 ; operands[0].access: WRITE ; operands[1].type: REG = t3 ; operands[1].access: READ ; operands[2].type: REG = t4 ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0x33,0xd2,0x62,0x40 == sra tp, t0, t1 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x33,0xd2,0x62,0x40 == sra tp, t0, t1 ; op_count: 3 ; operands[0].type: REG = tp ; operands[0].access: WRITE ; operands[1].type: REG = t0 ; operands[1].access: READ ; operands[2].type: REG = t1 ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0xb3,0x43,0x94,0x00 == xor t2, s0, s1 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xb3,0x43,0x94,0x00 == xor t2, s0, s1 ; op_count: 3 ; operands[0].type: REG = t2 ; operands[0].access: WRITE ; operands[1].type: REG = s0 ; operands[1].access: READ ; operands[2].type: REG = s1 ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0x33,0xe5,0xc5,0x00 == or a0, a1, a2 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x33,0xe5,0xc5,0x00 == or a0, a1, a2 ; op_count: 3 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; operands[2].type: REG = a2 ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0xb3,0x76,0xf7,0x00 == and a3, a4, a5 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xb3,0x76,0xf7,0x00 == and a3, a4, a5 ; op_count: 3 ; operands[0].type: REG = a3 ; operands[0].access: WRITE ; operands[1].type: REG = a4 ; operands[1].access: READ ; operands[2].type: REG = a5 ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0xb3,0x54,0x39,0x01 == srl s1, s2, s3 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xb3,0x54,0x39,0x01 == srl s1, s2, s3 ; op_count: 3 ; operands[0].type: REG = s1 ; operands[0].access: WRITE ; operands[1].type: REG = s2 ; operands[1].access: READ ; operands[2].type: REG = s3 ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0xb3,0x50,0x31,0x00 == srl ra, sp, gp -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xb3,0x50,0x31,0x00 == srl ra, sp, gp ; op_count: 3 ; operands[0].type: REG = ra ; operands[0].access: WRITE ; operands[1].type: REG = sp ; operands[1].access: READ ; operands[2].type: REG = gp ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0x33,0x9f,0x0f,0x00 == sll t5, t6, zero -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x33,0x9f,0x0f,0x00 == sll t5, t6, zero ; op_count: 3 ; operands[0].type: REG = t5 ; operands[0].access: WRITE ; operands[1].type: REG = t6 ; operands[1].access: READ ; operands[2].type: REG = zero ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0x73,0x15,0x04,0xb0 == csrrw a0, mcycle, s0 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x73,0x15,0x04,0xb0 == csrrw a0, mcycle, s0 ; op_count: 2 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = s0 ; operands[1].access: READ - -!# issue 0 RISCV operand groups 0xf3,0x56,0x00,0x10 == csrrwi a3, sstatus, 0 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xf3,0x56,0x00,0x10 == csrrwi a3, sstatus, 0 ; op_count: 2 ; operands[0].type: REG = a3 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x0 ; operands[1].access: READ - -!# issue 0 RISCV operand groups 0x33,0x05,0x7b,0x03 == mul a0, s6, s7 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x33,0x05,0x7b,0x03 == mul a0, s6, s7 ; op_count: 3 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = s6 ; operands[1].access: READ ; operands[2].type: REG = s7 ; operands[2].access: READ ; Groups: hasStdExtM - -!# issue 0 RISCV operand groups 0xb3,0x45,0x9c,0x03 == div a1, s8, s9 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xb3,0x45,0x9c,0x03 == div a1, s8, s9 ; op_count: 3 ; operands[0].type: REG = a1 ; operands[0].access: WRITE ; operands[1].type: REG = s8 ; operands[1].access: READ ; operands[2].type: REG = s9 ; operands[2].access: READ ; Groups: hasStdExtM - -!# issue 0 RISCV operand groups 0x33,0x66,0xbd,0x03 == rem a2, s10, s11 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x33,0x66,0xbd,0x03 == rem a2, s10, s11 ; op_count: 3 ; operands[0].type: REG = a2 ; operands[0].access: WRITE ; operands[1].type: REG = s10 ; operands[1].access: READ ; operands[2].type: REG = s11 ; operands[2].access: READ ; Groups: hasStdExtM - -!# issue 0 RISCV operand groups 0x2f,0xa4,0x02,0x10 == lr.w s0, (t0) -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x2f,0xa4,0x02,0x10 == lr.w s0, (t0) ; op_count: 2 ; operands[0].type: REG = s0 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = t0 ; operands[1].access: READ ; Groups: hasStdExtA - -!# issue 0 RISCV operand groups 0xaf,0x23,0x65,0x18 == sc.w t2, t1, (a0) -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xaf,0x23,0x65,0x18 == sc.w t2, t1, (a0) ; op_count: 3 ; operands[0].type: REG = t2 ; operands[0].access: WRITE ; operands[1].type: REG = t1 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = a0 ; operands[2].access: WRITE ; Groups: hasStdExtA - -!# issue 0 RISCV operand groups 0x2f,0x27,0x2f,0x01 == amoadd.w a4, s2, (t5) -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x2f,0x27,0x2f,0x01 == amoadd.w a4, s2, (t5) ; op_count: 3 ; operands[0].type: REG = a4 ; operands[0].access: WRITE ; operands[1].type: REG = s2 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = t5 ; operands[2].access: READ | WRITE ; Groups: hasStdExtA - -!# issue 0 RISCV operand groups 0x43,0xf0,0x20,0x18 == fmadd.s ft0, ft1, ft2, ft3 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x43,0xf0,0x20,0x18 == fmadd.s ft0, ft1, ft2, ft3 ; op_count: 4 ; operands[0].type: REG = ft0 ; operands[0].access: WRITE ; operands[1].type: REG = ft1 ; operands[1].access: READ ; operands[2].type: REG = ft2 ; operands[2].access: READ ; operands[3].type: REG = ft3 ; operands[3].access: READ ; Groups: hasStdExtF - -!# issue 0 RISCV operand groups 0xd3,0x72,0x73,0x00 == fadd.s ft5, ft6, ft7 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xd3,0x72,0x73,0x00 == fadd.s ft5, ft6, ft7 ; op_count: 3 ; operands[0].type: REG = ft5 ; operands[0].access: WRITE ; operands[1].type: REG = ft6 ; operands[1].access: READ ; operands[2].type: REG = ft7 ; operands[2].access: READ ; Groups: hasStdExtF - -!# issue 0 RISCV operand groups 0x53,0xf4,0x04,0x58 == fsqrt.s fs0, fs1 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x53,0xf4,0x04,0x58 == fsqrt.s fs0, fs1 ; op_count: 2 ; operands[0].type: REG = fs0 ; operands[0].access: WRITE ; operands[1].type: REG = fs1 ; operands[1].access: READ ; Groups: hasStdExtF - -!# issue 0 RISCV operand groups 0x53,0x85,0xc5,0x28 == fmin.s fa0, fa1, fa2 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x53,0x85,0xc5,0x28 == fmin.s fa0, fa1, fa2 ; op_count: 3 ; operands[0].type: REG = fa0 ; operands[0].access: WRITE ; operands[1].type: REG = fa1 ; operands[1].access: READ ; operands[2].type: REG = fa2 ; operands[2].access: READ ; Groups: hasStdExtF - -!# issue 0 RISCV operand groups 0x53,0x2e,0xde,0xa1 == feq.s t3, ft8, ft9 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x53,0x2e,0xde,0xa1 == feq.s t3, ft8, ft9 ; op_count: 3 ; operands[0].type: REG = t3 ; operands[0].access: WRITE ; operands[1].type: REG = ft8 ; operands[1].access: READ ; operands[2].type: REG = ft9 ; operands[2].access: READ ; Groups: hasStdExtF - -!# issue 0 RISCV operand groups 0xd3,0x84,0x05,0xf0 == fmv.w.x fs1, a1 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xd3,0x84,0x05,0xf0 == fmv.w.x fs1, a1 ; op_count: 2 ; operands[0].type: REG = fs1 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; Groups: hasStdExtF - -!# issue 0 RISCV operand groups 0x53,0x06,0x05,0xe0 == fmv.x.w a2, fa0 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x53,0x06,0x05,0xe0 == fmv.x.w a2, fa0 ; op_count: 2 ; operands[0].type: REG = a2 ; operands[0].access: WRITE ; operands[1].type: REG = fa0 ; operands[1].access: READ ; Groups: hasStdExtF - -!# issue 0 RISCV operand groups 0x53,0x75,0x00,0xc0 == fcvt.w.s a0, ft0 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x53,0x75,0x00,0xc0 == fcvt.w.s a0, ft0 ; op_count: 2 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = ft0 ; operands[1].access: READ ; Groups: hasStdExtF - -!# issue 0 RISCV operand groups 0xd3,0xf0,0x05,0xd0 == fcvt.s.w ft1, a1 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xd3,0xf0,0x05,0xd0 == fcvt.s.w ft1, a1 ; op_count: 2 ; operands[0].type: REG = ft1 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; Groups: hasStdExtF - -!# issue 0 RISCV operand groups 0xd3,0x15,0x08,0xe0 == fclass.s a1, fa6 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xd3,0x15,0x08,0xe0 == fclass.s a1, fa6 ; op_count: 2 ; operands[0].type: REG = a1 ; operands[0].access: WRITE ; operands[1].type: REG = fa6 ; operands[1].access: READ ; Groups: hasStdExtF - -!# issue 0 RISCV operand groups 0x87,0xaa,0x75,0x00 == flw fs5, 7(a1) -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x87,0xaa,0x75,0x00 == flw fs5, 7(a1) ; op_count: 2 ; operands[0].type: REG = fs5 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = a1 ; operands[1].mem.disp: 0x7 ; operands[1].access: READ ; Groups: hasStdExtF - -!# issue 0 RISCV operand groups 0x27,0x27,0x66,0x01 == fsw fs6, 0xe(a2) -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x27,0x27,0x66,0x01 == fsw fs6, 0xe(a2) ; op_count: 2 ; operands[0].type: REG = fs6 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = a2 ; operands[1].mem.disp: 0xe ; operands[1].access: WRITE ; Groups: hasStdExtF - -!# issue 0 RISCV operand groups 0x43,0xf0,0x20,0x1a == fmadd.d ft0, ft1, ft2, ft3 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x43,0xf0,0x20,0x1a == fmadd.d ft0, ft1, ft2, ft3 ; op_count: 4 ; operands[0].type: REG = ft0 ; operands[0].access: WRITE ; operands[1].type: REG = ft1 ; operands[1].access: READ ; operands[2].type: REG = ft2 ; operands[2].access: READ ; operands[3].type: REG = ft3 ; operands[3].access: READ ; Groups: hasStdExtD - -!# issue 0 RISCV operand groups 0xd3,0x72,0x73,0x02 == fadd.d ft5, ft6, ft7 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0xd3,0x72,0x73,0x02 == fadd.d ft5, ft6, ft7 ; op_count: 3 ; operands[0].type: REG = ft5 ; operands[0].access: WRITE ; operands[1].type: REG = ft6 ; operands[1].access: READ ; operands[2].type: REG = ft7 ; operands[2].access: READ ; Groups: hasStdExtD - -!# issue 0 RISCV operand groups 0x53,0xf4,0x04,0x5a == fsqrt.d fs0, fs1 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x53,0xf4,0x04,0x5a == fsqrt.d fs0, fs1 ; op_count: 2 ; operands[0].type: REG = fs0 ; operands[0].access: WRITE ; operands[1].type: REG = fs1 ; operands[1].access: READ ; Groups: hasStdExtD - -!# issue 0 RISCV operand groups 0x53,0x85,0xc5,0x2a == fmin.d fa0, fa1, fa2 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x53,0x85,0xc5,0x2a == fmin.d fa0, fa1, fa2 ; op_count: 3 ; operands[0].type: REG = fa0 ; operands[0].access: WRITE ; operands[1].type: REG = fa1 ; operands[1].access: READ ; operands[2].type: REG = fa2 ; operands[2].access: READ ; Groups: hasStdExtD - -!# issue 0 RISCV operand groups 0x53,0x2e,0xde,0xa3 == feq.d t3, ft8, ft9 -!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL -0x53,0x2e,0xde,0xa3 == feq.d t3, ft8, ft9 ; op_count: 3 ; operands[0].type: REG = t3 ; operands[0].access: WRITE ; operands[1].type: REG = ft8 ; operands[1].access: READ ; operands[2].type: REG = ft9 ; operands[2].access: READ ; Groups: hasStdExtD - -!# issue 0 RISCV operand groups 0x13,0x04,0xa8,0x7a == addi s0, a6, 0x7aa -!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL -0x13,0x04,0xa8,0x7a == addi s0, a6, 0x7aa ; op_count: 3 ; operands[0].type: REG = s0 ; operands[0].access: WRITE ; operands[1].type: REG = a6 ; operands[1].access: READ ; operands[2].type: IMM = 0x7aa ; operands[2].access: READ - -!# issue 0 RISCV operand groups 0xbb,0x07,0x9c,0x02 == mulw a5, s8, s1 -!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL -0xbb,0x07,0x9c,0x02 == mulw a5, s8, s1 ; op_count: 3 ; operands[0].type: REG = a5 ; operands[0].access: WRITE ; operands[1].type: REG = s8 ; operands[1].access: READ ; operands[2].type: REG = s1 ; operands[2].access: READ ; Groups: hasStdExtM isrv64 - -!# issue 0 RISCV operand groups 0xbb,0x40,0x5d,0x02 == divw ra, s10, t0 -!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL -0xbb,0x40,0x5d,0x02 == divw ra, s10, t0 ; op_count: 3 ; operands[0].type: REG = ra ; operands[0].access: WRITE ; operands[1].type: REG = s10 ; operands[1].access: READ ; operands[2].type: REG = t0 ; operands[2].access: READ ; Groups: hasStdExtM isrv64 - -!# issue 0 RISCV operand groups 0x3b,0x63,0xb7,0x03 == remw t1, a4, s11 -!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL -0x3b,0x63,0xb7,0x03 == remw t1, a4, s11 ; op_count: 3 ; operands[0].type: REG = t1 ; operands[0].access: WRITE ; operands[1].type: REG = a4 ; operands[1].access: READ ; operands[2].type: REG = s11 ; operands[2].access: READ ; Groups: hasStdExtM isrv64 - -!# issue 0 RISCV operand groups 0x2f,0xb4,0x02,0x10 == lr.d s0, (t0) -!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL -0x2f,0xb4,0x02,0x10 == lr.d s0, (t0) ; op_count: 2 ; operands[0].type: REG = s0 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = t0 ; operands[1].access: READ ; Groups: hasStdExtA isrv64 - -!# issue 0 RISCV operand groups 0xaf,0x33,0x65,0x18 == sc.d t2, t1, (a0) -!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL -0xaf,0x33,0x65,0x18 == sc.d t2, t1, (a0) ; op_count: 3 ; operands[0].type: REG = t2 ; operands[0].access: WRITE ; operands[1].type: REG = t1 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = a0 ; operands[2].access: WRITE ; Groups: hasStdExtA isrv64 - -!# issue 0 RISCV operand groups 0x2f,0x37,0x2f,0x01 == amoadd.d a4, s2, (t5) -!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL -0x2f,0x37,0x2f,0x01 == amoadd.d a4, s2, (t5) ; op_count: 3 ; operands[0].type: REG = a4 ; operands[0].access: WRITE ; operands[1].type: REG = s2 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = t5 ; operands[2].access: READ | WRITE ; Groups: hasStdExtA isrv64 - -!# issue 0 RISCV operand groups 0x53,0x75,0x20,0xc0 == fcvt.l.s a0, ft0 -!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL -0x53,0x75,0x20,0xc0 == fcvt.l.s a0, ft0 ; op_count: 2 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = ft0 ; operands[1].access: READ ; Groups: hasStdExtF isrv64 - -!# issue 0 RISCV operand groups 0xd3,0xf0,0x25,0xd0 == fcvt.s.l ft1, a1 -!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL -0xd3,0xf0,0x25,0xd0 == fcvt.s.l ft1, a1 ; op_count: 2 ; operands[0].type: REG = ft1 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; Groups: hasStdExtF isrv64 - -!# issue 0 RISCV operand groups 0xd3,0x84,0x05,0xf2 == fmv.d.x fs1, a1 -!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL -0xd3,0x84,0x05,0xf2 == fmv.d.x fs1, a1 ; op_count: 2 ; operands[0].type: REG = fs1 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; Groups: hasStdExtD isrv64 - -!# issue 0 RISCV operand groups 0x53,0x06,0x05,0xe2 == fmv.x.d a2, fa0 -!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL -0x53,0x06,0x05,0xe2 == fmv.x.d a2, fa0 ; op_count: 2 ; operands[0].type: REG = a2 ; operands[0].access: WRITE ; operands[1].type: REG = fa0 ; operands[1].access: READ ; Groups: hasStdExtD isrv64 - -!# issue 0 RISCV operand groups 0x53,0x75,0x00,0xc2 == fcvt.w.d a0, ft0 -!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL -0x53,0x75,0x00,0xc2 == fcvt.w.d a0, ft0 ; op_count: 2 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = ft0 ; operands[1].access: READ ; Groups: hasStdExtD - -!# issue 0 RISCV operand groups 0xd3,0x80,0x05,0xd2 == fcvt.d.w ft1, a1 -!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL -0xd3,0x80,0x05,0xd2 == fcvt.d.w ft1, a1 ; op_count: 2 ; operands[0].type: REG = ft1 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; Groups: hasStdExtD - -!# issue 0 RISCV operand groups 0xd3,0x15,0x08,0xe2 == fclass.d a1, fa6 -!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL -0xd3,0x15,0x08,0xe2 == fclass.d a1, fa6 ; op_count: 2 ; operands[0].type: REG = a1 ; operands[0].access: WRITE ; operands[1].type: REG = fa6 ; operands[1].access: READ ; Groups: hasStdExtD - -!# issue 0 RISCV operand groups 0x87,0xba,0x75,0x00 == fld fs5, 7(a1) -!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL -0x87,0xba,0x75,0x00 == fld fs5, 7(a1) ; op_count: 2 ; operands[0].type: REG = fs5 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = a1 ; operands[1].mem.disp: 0x7 ; operands[1].access: READ ; Groups: hasStdExtD - -!# issue 0 RISCV operand groups 0x27,0x37,0x66,0x01 == fsd fs6, 0xe(a2) -!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL -0x27,0x37,0x66,0x01 == fsd fs6, 0xe(a2) ; op_count: 2 ; operands[0].type: REG = fs6 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = a2 ; operands[1].mem.disp: 0xe ; operands[1].access: WRITE ; Groups: hasStdExtD - -!# issue 0 RISCV operand groups 0xe8,0x1f == c.addi4spn a0, sp, 0x3fc -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0xe8,0x1f == c.addi4spn a0, sp, 0x3fc ; op_count: 3 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = sp ; operands[1].access: READ ; operands[2].type: IMM = 0x3fc ; operands[2].access: READ ; Groups: hasStdExtC - -!# issue 0 RISCV operand groups 0x7d,0x61 == c.addi16sp sp, 0x1f0 -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0x7d,0x61 == c.addi16sp sp, 0x1f0 ; op_count: 2 ; operands[0].type: REG = sp ; operands[0].access: READ | WRITE ; operands[1].type: IMM = 0x1f0 ; operands[1].access: READ ; Groups: hasStdExtC - -!# issue 0 RISCV operand groups 0x80,0x25 == c.fld fs0, 8(a1) -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0x80,0x25 == c.fld fs0, 8(a1) ; op_count: 2 ; operands[0].type: REG = fs0 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = a1 ; operands[1].mem.disp: 0x8 ; operands[1].access: READ ; Groups: hasStdExtC hasStdExtD - -!# issue 0 RISCV operand groups 0x00,0x46 == c.lw s0, 8(a2) -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0x00,0x46 == c.lw s0, 8(a2) ; op_count: 2 ; operands[0].type: REG = s0 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = a2 ; operands[1].mem.disp: 0x8 ; operands[1].access: READ ; Groups: hasStdExtC - -!# issue 0 RISCV operand groups 0x88,0xa2 == c.fsd fa0, 0(a3) -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0x88,0xa2 == c.fsd fa0, 0(a3) ; op_count: 2 ; operands[0].type: REG = fa0 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = a3 ; operands[1].access: WRITE ; Groups: hasStdExtC hasStdExtD - -!# issue 0 RISCV operand groups 0x04,0xcb == c.sw s1, 0x10(a4) -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0x04,0xcb == c.sw s1, 0x10(a4) ; op_count: 2 ; operands[0].type: REG = s1 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = a4 ; operands[1].mem.disp: 0x10 ; operands[1].access: WRITE ; Groups: hasStdExtC - -!# issue 0 RISCV operand groups 0x55,0x13 == c.addi t1, -0xb -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0x55,0x13 == c.addi t1, -0xb ; op_count: 2 ; operands[0].type: REG = t1 ; operands[0].access: READ | WRITE ; operands[1].type: IMM = 0xfffffff5 ; operands[1].access: READ ; Groups: hasStdExtC - -!# issue 0 RISCV operand groups 0xf2,0x93 == c.add t2, t3 -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0xf2,0x93 == c.add t2, t3 ; op_count: 2 ; operands[0].type: REG = t2 ; operands[0].access: READ | WRITE ; operands[1].type: REG = t3 ; operands[1].access: READ ; Groups: hasStdExtC - -!# issue 0 RISCV operand groups 0x5d,0x45 == c.li a0, 0x17 -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0x5d,0x45 == c.li a0, 0x17 ; op_count: 2 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x17 ; operands[1].access: READ ; Groups: hasStdExtC - -!# issue 0 RISCV operand groups 0x19,0x80 == c.srli s0, 6 -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0x19,0x80 == c.srli s0, 6 ; op_count: 2 ; operands[0].type: REG = s0 ; operands[0].access: READ | WRITE ; operands[1].type: IMM = 0x6 ; operands[1].access: READ ; Groups: hasStdExtC - -!# issue 0 RISCV operand groups 0x15,0x68 == c.lui a6, 5 -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0x15,0x68 == c.lui a6, 5 ; op_count: 2 ; operands[0].type: REG = a6 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x5 ; operands[1].access: READ ; Groups: hasStdExtC - -!# issue 0 RISCV operand groups 0x2a,0xa4 == c.fsdsp fa0, 8(sp) -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0x2a,0xa4 == c.fsdsp fa0, 8(sp) ; op_count: 2 ; operands[0].type: REG = fa0 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = sp ; operands[1].mem.disp: 0x8 ; operands[1].access: WRITE ; Groups: hasStdExtC hasStdExtD - -!# issue 0 RISCV operand groups 0x62,0x24 == c.fldsp fs0, 0x18(sp) -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0x62,0x24 == c.fldsp fs0, 0x18(sp) ; op_count: 2 ; operands[0].type: REG = fs0 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = sp ; operands[1].mem.disp: 0x18 ; operands[1].access: READ ; Groups: hasStdExtC hasStdExtD - -!# issue 0 RISCV operand groups 0xa6,0xff == c.fswsp fs1, 0xfc(sp) -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0xa6,0xff == c.fswsp fs1, 0xfc(sp) ; op_count: 3 ; operands[0].type: REG = fs1 ; operands[0].access: READ ; operands[1].type: IMM = 0xfc ; operands[1].access: READ ; operands[2].type: REG = sp ; operands[2].access: WRITE ; Groups: hasStdExtC hasStdExtF isrv32 - -!# issue 0 RISCV operand groups 0x2a,0x65 == c.flwsp fa0, 0x88(sp) -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0x2a,0x65 == c.flwsp fa0, 0x88(sp) ; op_count: 3 ; operands[0].type: REG = fa0 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x88 ; operands[1].access: READ ; operands[2].type: REG = sp ; operands[2].access: READ ; Groups: hasStdExtC hasStdExtF isrv32 - -!# issue 0 RISCV operand groups 0x76,0x86 == c.mv a2, t4 -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0x76,0x86 == c.mv a2, t4 ; op_count: 2 ; operands[0].type: REG = a2 ; operands[0].access: WRITE ; operands[1].type: REG = t4 ; operands[1].access: READ ; Groups: hasStdExtC - -!# issue 0 RISCV operand groups 0x65,0xdd == c.beqz a0, -8 -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0x65,0xdd == c.beqz a0, -8 ; op_count: 2 ; operands[0].type: REG = a0 ; operands[0].access: READ ; operands[1].type: IMM = 0xfffffff8 ; operands[1].access: READ ; Groups: hasStdExtC branch_relative jump - -!# issue 0 RISCV operand groups 0x01,0x00 == c.nop -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0x01,0x00 == c.nop ; Groups: hasStdExtC - -!# issue 0 RISCV operand groups 0xfd,0xaf == c.j 0x7fe -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0xfd,0xaf == c.j 0x7fe ; op_count: 1 ; operands[0].type: IMM = 0x7fe ; operands[0].access: READ ; Groups: hasStdExtC jump - -!# issue 0 RISCV operand groups 0x82,0x82 == c.jr t0 -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0x82,0x82 == c.jr t0 ; op_count: 1 ; operands[0].type: REG = t0 ; operands[0].access: READ ; Groups: hasStdExtC jump - -!# issue 0 RISCV operand groups 0x11,0x20 == c.jal 4 -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0x11,0x20 == c.jal 4 ; op_count: 1 ; operands[0].type: IMM = 0x4 ; operands[0].access: READ ; Groups: hasStdExtC isrv32 call - -!# issue 0 RISCV operand groups 0x82,0x94 == c.jalr s1 -!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL -0x82,0x94 == c.jalr s1 ; op_count: 1 ; operands[0].type: REG = s1 ; operands[0].access: READ ; Groups: hasStdExtC call - -!# issue 2285 AArch64 operands -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0xc0,0x08,0x9f,0xe0 == ld1w {za0h.s[w12, 0]}, p2/z, [x6] ; op_count: 3 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.tile: za0.s ; operands[0].sme.slice_reg: w12 ; operands[0].sme.slice_offset: 0 ; operands[0].sme.is_vertical: false ; operands[0].access: WRITE ; operands[0].vas: 0x20 ; operands[1].type: PREDICATE ; operands[1].pred.reg: p2 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = x6 ; operands[2].access: READ ; Registers read: w12 p2 x6 ; Registers modified: za0.s ; Groups: HasSME - -!# issue 2285 AArch64 operands -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x41,0x31,0xa2,0xe0 == st1w {za0h.s[w13, 1]}, p4, [x10, x2, lsl #2] ; op_count: 3 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.tile: za0.s ; operands[0].sme.slice_reg: w13 ; operands[0].sme.slice_offset: 1 ; operands[0].sme.is_vertical: false ; operands[0].access: READ ; operands[0].vas: 0x20 ; operands[1].type: PREDICATE ; operands[1].pred.reg: p4 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = x10 ; operands[2].mem.index: REG = x2 ; operands[2].access: WRITE ; Shift: type = 1, value = 2 ; Registers read: za0.s w13 p4 x10 x2 ; Groups: HasSME - -!# issue 2285 AArch64 operands -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x67,0x44,0x71,0x25 == psel p7, p1, p3.s[w13, 1] ; op_count: 3 ; operands[0].type: PREDICATE ; operands[0].pred.reg: p7 ; operands[0].access: WRITE ; operands[1].type: PREDICATE ; operands[1].pred.reg: p1 ; operands[1].access: READ ; operands[2].type: PREDICATE ; operands[2].pred.reg: p3 ; operands[2].pred.vec_select: w13 ; operands[2].pred.imm_index: 1 ; operands[2].access: READ ; operands[2].vas: 0x20 ; Registers read: p1 p3 w13 ; Registers modified: p7 ; Groups: HasSVE2p1_or_HasSME - -!# issue 2285 AArch64 operands -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x7f,0x47,0x03,0xd5 == smstart ; Code-condition: 16 ; Groups: privilege - -!# issue 2285 AArch64 operands -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x55,0x00,0x08,0xc0 == zero {za0.h} ; op_count: 1 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 1 ; operands[0].sme.tile: za0.h ; operands[0].access: WRITE ; operands[0].vas: 0x10 ; Code-condition: 16 ; Registers modified: za0.h ; Groups: HasSME - -!# issue 2285 AArch64 operands -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x02,0xf8,0x55,0xc1 == sdot za.s[w11, 2, vgx4], { z0.h - z3.h }, z5.h[2] ; op_count: 6 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.tile: za ; operands[0].sme.slice_reg: w11 ; operands[0].sme.slice_offset: 2 ; operands[0].sme.is_vertical: false ; operands[0].access: READ | WRITE ; operands[0].vas: 0x20 ; operands[1].type: REG = z0 ; operands[1].is_list_member: true ; operands[1].access: READ ; operands[1].vas: 0x10 ; operands[2].type: REG = z1 ; operands[2].is_list_member: true ; operands[2].access: READ ; operands[2].vas: 0x10 ; operands[3].type: REG = z2 ; operands[3].is_list_member: true ; operands[3].access: READ ; operands[3].vas: 0x10 ; operands[4].type: REG = z3 ; operands[4].is_list_member: true ; operands[4].access: READ ; operands[4].vas: 0x10 ; operands[5].type: REG = z5 ; operands[5].access: READ ; operands[5].vas: 0x10 ; operands[5].vector_index: 2 ; Write-back: True ; Code-condition: 16 ; Registers read: za w11 z0 z1 z2 z3 z5 ; Registers modified: za ; Groups: HasSME2 - -!# issue 2285 AArch64 operands -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0xa4,0x0e,0x06,0xc0 == movaz { z4.d - z7.d }, za.d[w8, 5, vgx4] ; op_count: 5 ; operands[0].type: REG = z4 ; operands[0].is_list_member: true ; operands[0].access: WRITE ; operands[0].vas: 0x40 ; operands[1].type: REG = z5 ; operands[1].is_list_member: true ; operands[1].access: WRITE ; operands[1].vas: 0x40 ; operands[2].type: REG = z6 ; operands[2].is_list_member: true ; operands[2].access: WRITE ; operands[2].vas: 0x40 ; operands[3].type: REG = z7 ; operands[3].is_list_member: true ; operands[3].access: WRITE ; operands[3].vas: 0x40 ; operands[4].type: SME_MATRIX ; operands[4].sme.type: 2 ; operands[4].sme.tile: za ; operands[4].sme.slice_reg: w8 ; operands[4].sme.slice_offset: 5 ; operands[4].sme.is_vertical: false ; operands[4].access: READ | WRITE ; operands[4].vas: 0x40 ; Write-back: True ; Code-condition: 16 ; Registers read: za w8 ; Registers modified: z4 z5 z6 z7 za ; Groups: HasSME2p1 - -!# issue 2285 AArch64 operands -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x80,0xa0,0x8d,0xc0 == luti2 { z0.s - z3.s }, zt0, z4[1] ; op_count: 6 ; operands[0].type: REG = z0 ; operands[0].is_list_member: true ; operands[0].access: WRITE ; operands[0].vas: 0x20 ; operands[1].type: REG = z1 ; operands[1].is_list_member: true ; operands[1].access: WRITE ; operands[1].vas: 0x20 ; operands[2].type: REG = z2 ; operands[2].is_list_member: true ; operands[2].access: WRITE ; operands[2].vas: 0x20 ; operands[3].type: REG = z3 ; operands[3].is_list_member: true ; operands[3].access: WRITE ; operands[3].vas: 0x20 ; operands[4].type: REG = zt0 ; operands[4].access: READ ; operands[5].type: REG = z4 ; operands[5].access: READ ; operands[5].vector_index: 1 ; Code-condition: 16 ; Registers read: zt0 z4 ; Registers modified: z0 z1 z2 z3 ; Groups: HasSME2 - -!# issue 2285 AArch64 operands -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x00,0xb1,0x10,0xc1 == fmla za.h[w9, 0, vgx4], { z8.h - z11.h }, z0.h[0] ; op_count: 6 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.tile: za ; operands[0].sme.slice_reg: w9 ; operands[0].sme.slice_offset: 0 ; operands[0].sme.is_vertical: false ; operands[0].access: READ | WRITE ; operands[0].vas: 0x10 ; operands[1].type: REG = z8 ; operands[1].is_list_member: true ; operands[1].access: READ ; operands[1].vas: 0x10 ; operands[2].type: REG = z9 ; operands[2].is_list_member: true ; operands[2].access: READ ; operands[2].vas: 0x10 ; operands[3].type: REG = z10 ; operands[3].is_list_member: true ; operands[3].access: READ ; operands[3].vas: 0x10 ; operands[4].type: REG = z11 ; operands[4].is_list_member: true ; operands[4].access: READ ; operands[4].vas: 0x10 ; operands[5].type: REG = z0 ; operands[5].access: READ ; operands[5].vas: 0x10 ; operands[5].vector_index: 0 ; Write-back: True ; Code-condition: 16 ; Registers read: za w9 z8 z9 z10 z11 z0 ; Registers modified: za ; Groups: HasSME2p1 HasSMEF16F16 - -!# issue 2285 AArch64 operands -!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL -0x05,0xd0,0x9b,0xc1 == fmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z11.h[1] ; op_count: 6 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.tile: za ; operands[0].sme.slice_reg: w10 ; operands[0].sme.slice_offset: 2:3 ; operands[0].sme.is_vertical: false ; operands[0].access: READ | WRITE ; operands[0].vas: 0x20 ; operands[1].type: REG = z0 ; operands[1].is_list_member: true ; operands[1].access: READ ; operands[1].vas: 0x10 ; operands[2].type: REG = z1 ; operands[2].is_list_member: true ; operands[2].access: READ ; operands[2].vas: 0x10 ; operands[3].type: REG = z2 ; operands[3].is_list_member: true ; operands[3].access: READ ; operands[3].vas: 0x10 ; operands[4].type: REG = z3 ; operands[4].is_list_member: true ; operands[4].access: READ ; operands[4].vas: 0x10 ; operands[5].type: REG = z11 ; operands[5].access: READ ; operands[5].vas: 0x10 ; operands[5].vector_index: 1 ; Write-back: True ; Code-condition: 16 ; Registers read: za w10 z0 z1 z2 z3 z11 ; Registers modified: za ; Groups: HasSME2 - diff --git a/tests/cs_details/README.md b/tests/details/README.md similarity index 100% rename from tests/cs_details/README.md rename to tests/details/README.md diff --git a/tests/details/aarch64.yaml b/tests/details/aarch64.yaml new file mode 100644 index 0000000000..b452333f56 --- /dev/null +++ b/tests/details/aarch64.yaml @@ -0,0 +1,875 @@ +test_cases: + - + input: + bytes: [ 0x09, 0x00, 0x38, 0xd5, 0xbf, 0x40, 0x00, 0xd5, 0x0c, 0x05, 0x13, 0xd5, 0x20, 0x50, 0x02, 0x0e, 0x20, 0xe4, 0x3d, 0x0f, 0x00, 0x18, 0xa0, 0x5f, 0xa2, 0x00, 0xae, 0x9e, 0x9f, 0x37, 0x03, 0xd5, 0xbf, 0x33, 0x03, 0xd5, 0xdf, 0x3f, 0x03, 0xd5, 0x21, 0x7c, 0x02, 0x9b, 0x21, 0x7c, 0x00, 0x53, 0x00, 0x40, 0x21, 0x4b, 0xe1, 0x0b, 0x40, 0xb9, 0x20, 0x04, 0x81, 0xda, 0x20, 0x08, 0x02, 0x8b, 0x10, 0x5b, 0xe8, 0x3c, 0xfd, 0x7b, 0xba, 0xa9, 0xfd, 0xc7, 0x43, 0xf8 ] + arch: "CS_ARCH_AARCH64" + options: [ "CS_OPT_DETAIL" ] + address: 0x2c + expected: + insns: + - + asm_text: "mrs x9, MIDR_EL1" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: x9 + access: CS_AC_WRITE + - + type: AARCH64_OP_SYSREG + sub_type: AARCH64_OP_REG_MRS + sys_raw_val: 0xc000 + cc: AArch64CC_Invalid + update_flags: 1 + regs_write: [ nzcv, x9 ] + + - + asm_text: "msr SPSel, #0" + details: + aarch64: + operands: + - + type: AARCH64_OP_SYSALIAS + sub_type: AARCH64_OP_PSTATEIMM0_15 + sys_raw_val: 0x5 + - + type: AARCH64_OP_IMM + imm: 0x0 + access: CS_AC_READ + cc: AArch64CC_Invalid + + - + asm_text: "msr DBGDTRTX_EL0, x12" + details: + aarch64: + operands: + - + type: AARCH64_OP_SYSREG + sub_type: AARCH64_OP_REG_MSR + sys_raw_val: 0x9828 + - + type: AARCH64_OP_REG + reg: x12 + access: CS_AC_READ + cc: AArch64CC_Invalid + regs_read: [ x12 ] + + - + asm_text: "tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: d0 + access: CS_AC_READ_WRITE + vas: AARCH64LAYOUT_VL_8B + is_vreg: 1 + - + type: AARCH64_OP_REG + reg: q1 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_16B + is_vreg: 1 + - + type: AARCH64_OP_REG + reg: q2 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_16B + is_vreg: 1 + - + type: AARCH64_OP_REG + reg: q3 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_16B + is_vreg: 1 + - + type: AARCH64_OP_REG + reg: d2 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_8B + is_vreg: 1 + cc: AArch64CC_Invalid + writeback: 1 + regs_read: [ d0, q1, q2, q3, d2 ] + regs_write: [ d0 ] + + - + asm_text: "scvtf v0.2s, v1.2s, #3" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: d0 + access: CS_AC_WRITE + vas: AARCH64LAYOUT_VL_2S + - + type: AARCH64_OP_REG + reg: d1 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_2S + - + type: AARCH64_OP_IMM + imm: 0x3 + access: CS_AC_READ + cc: AArch64CC_Invalid + regs_read: [ d1 ] + regs_write: [ d0 ] + + - + asm_text: "fmla s0, s0, v0.s[3]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: s0 + access: CS_AC_READ_WRITE + - + type: AARCH64_OP_REG + reg: s0 + access: CS_AC_READ + - + type: AARCH64_OP_REG + reg: q0 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_S + vector_index: 3 + vector_index_is_set: true + cc: AArch64CC_Invalid + writeback: 1 + regs_read: [ fpcr, s0, q0 ] + regs_write: [ s0 ] + + - + asm_text: "fmov x2, v5.d[1]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: x2 + access: CS_AC_WRITE + - + type: AARCH64_OP_REG + reg: q5 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_D + vector_index: 1 + vector_index_is_set: true + cc: AArch64CC_Invalid + regs_read: [ q5 ] + regs_write: [ x2 ] + + - + asm_text: "dsb nsh" + details: + aarch64: + operands: + - + type: AARCH64_OP_SYSALIAS + sub_type: AARCH64_OP_DB + sys_raw_val: 0x7 + cc: AArch64CC_Invalid + + - + asm_text: "dmb osh" + details: + aarch64: + operands: + - + type: AARCH64_OP_SYSALIAS + sub_type: AARCH64_OP_DB + sys_raw_val: 0x3 + cc: AArch64CC_Invalid + + - + asm_text: "isb" + + - + asm_text: "mul x1, x1, x2" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: x1 + access: CS_AC_WRITE + - + type: AARCH64_OP_REG + reg: x1 + access: CS_AC_READ + - + type: AARCH64_OP_REG + reg: x2 + access: CS_AC_READ + cc: AArch64CC_Invalid + regs_read: [ x1, x2 ] + regs_write: [ x1 ] + + - + asm_text: "lsr w1, w1, #0" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: w1 + access: CS_AC_WRITE + - + type: AARCH64_OP_REG + reg: w1 + access: CS_AC_READ + cc: AArch64CC_Invalid + regs_read: [ w1 ] + regs_write: [ w1 ] + + - + asm_text: "sub w0, w0, w1, uxtw" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: w0 + access: CS_AC_WRITE + - + type: AARCH64_OP_REG + reg: w0 + access: CS_AC_READ + - + type: AARCH64_OP_REG + reg: w1 + access: CS_AC_READ + ext: AARCH64_EXT_UXTW + cc: AArch64CC_Invalid + regs_read: [ w0, w1 ] + regs_write: [ w0 ] + + - + asm_text: "ldr w1, [sp, #8]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: w1 + access: CS_AC_WRITE + - + type: AARCH64_OP_MEM + mem_base: sp + mem_disp: 0x8 + access: CS_AC_READ + cc: AArch64CC_Invalid + regs_read: [ sp ] + regs_write: [ w1 ] + + - + asm_text: "cneg x0, x1, ne" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: x0 + access: CS_AC_WRITE + - + type: AARCH64_OP_REG + reg: x1 + access: CS_AC_READ + cc: AArch64CC_NE + regs_read: [ nzcv, x1 ] + regs_write: [ x0 ] + + - + asm_text: "add x0, x1, x2, lsl #2" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: x0 + access: CS_AC_WRITE + - + type: AARCH64_OP_REG + reg: x1 + access: CS_AC_READ + - + type: AARCH64_OP_REG + reg: x2 + access: CS_AC_READ + shift_type: AARCH64_SFT_LSL + shift_value: 2 + cc: AArch64CC_Invalid + regs_read: [ x1, x2 ] + regs_write: [ x0 ] + + - + asm_text: "ldr q16, [x24, w8, uxtw #4]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: q16 + access: CS_AC_WRITE + - + type: AARCH64_OP_MEM + mem_base: x24 + mem_index: w8 + access: CS_AC_READ + shift_type: AARCH64_SFT_LSL + shift_value: 4 + ext: AARCH64_EXT_UXTW + cc: AArch64CC_Invalid + regs_read: [ x24, w8 ] + regs_write: [ q16 ] + + - + asm_text: "stp x29, x30, [sp, #-0x60]!" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: x29 + access: CS_AC_READ + - + type: AARCH64_OP_REG + reg: x30 + access: CS_AC_READ + - + type: AARCH64_OP_MEM + mem_base: sp + mem_disp: -0x60 + access: CS_AC_WRITE + cc: AArch64CC_Invalid + writeback: 1 + regs_read: [ x29, x30, sp ] + regs_write: [ sp ] + + - + asm_text: "ldr x29, [sp], #0x3c" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: x29 + access: CS_AC_WRITE + - + type: AARCH64_OP_MEM + mem_base: sp + access: CS_AC_READ + - + type: AARCH64_OP_IMM + imm: 0x3c + access: CS_AC_READ + post_indexed: 1 + cc: AArch64CC_Invalid + writeback: 1 + regs_read: [ sp ] + regs_write: [ sp, x29 ] + - + input: + bytes: [ 0xc0,0x08,0x9f,0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ld1w {za0h.s[w12, 0]}, p2/z, [x6]" + details: + aarch64: + operands: + - + type: AARCH64_OP_SME + sme: + type: AARCH64_SME_OP_TILE_VEC + tile: za0.s + slice_reg: w12 + slice_offset_imm: 0 + is_vertical: -1 + access: CS_AC_WRITE + vas: AARCH64LAYOUT_VL_S + - + type: AARCH64_OP_PRED + pred_reg: p2 + access: CS_AC_READ + - + type: AARCH64_OP_MEM + mem_base: x6 + access: CS_AC_READ + regs_read: [ w12, p2, x6 ] + regs_write: [ za0.s ] + groups: [ HasSME ] + - + input: + bytes: [ 0x41,0x31,0xa2,0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "st1w {za0h.s[w13, 1]}, p4, [x10, x2, lsl #2]" + details: + aarch64: + operands: + - + type: AARCH64_OP_SME + sme: + type: AARCH64_SME_OP_TILE_VEC + tile: za0.s + slice_reg: w13 + slice_offset_imm: 1 + is_vertical: -1 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_S + - + type: AARCH64_OP_PRED + pred_reg: p4 + access: CS_AC_READ + - + type: AARCH64_OP_MEM + mem_base: x10 + mem_index: x2 + access: CS_AC_WRITE + shift_type: ARM_SFT_ASR + shift_value: 2 + regs_read: [ za0.s, w13, p4, x10, x2 ] + groups: [ HasSME ] + - + input: + bytes: [ 0x67,0x44,0x71,0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "psel p7, p1, p3.s[w13, 1]" + details: + aarch64: + operands: + - + type: AARCH64_OP_PRED + pred_reg: p7 + access: CS_AC_WRITE + - + type: AARCH64_OP_PRED + pred_reg: p1 + access: CS_AC_READ + - + type: AARCH64_OP_PRED + pred_reg: p3 + pred_vec_select: w13 + pred_imm_index: 1 + pred_imm_index_set: true + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_S + regs_read: [ p1, p3, w13 ] + regs_write: [ p7 ] + groups: [ HasSVE2p1_or_HasSME ] + - + input: + bytes: [ 0x7f,0x47,0x03,0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "smstart" + details: + aarch64: + cc: AArch64CC_Invalid + groups: [ privilege ] + - + input: + bytes: [ 0x55,0x00,0x08,0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "zero {za0.h}" + details: + aarch64: + operands: + - + type: AARCH64_OP_SME + sme: + type: AARCH64_SME_OP_TILE + tile: za0.h + access: CS_AC_WRITE + vas: AARCH64LAYOUT_VL_H + cc: AArch64CC_Invalid + regs_write: [ za0.h ] + groups: [ HasSME ] + - + input: + bytes: [ 0x02,0xf8,0x55,0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "sdot za.s[w11, 2, vgx4], { z0.h - z3.h }, z5.h[2]" + details: + aarch64: + operands: + - + type: AARCH64_OP_SME + sme: + type: AARCH64_SME_OP_TILE_VEC + tile: za + slice_reg: w11 + slice_offset_imm: 2 + is_vertical: -1 + access: CS_AC_READ_WRITE + vas: AARCH64LAYOUT_VL_S + - + type: AARCH64_OP_REG + reg: z0 + is_list_member: 1 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_H + - + type: AARCH64_OP_REG + reg: z1 + is_list_member: 1 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_H + - + type: AARCH64_OP_REG + reg: z2 + is_list_member: 1 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_H + - + type: AARCH64_OP_REG + reg: z3 + is_list_member: 1 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_H + - + type: AARCH64_OP_REG + reg: z5 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_H + vector_index: 2 + vector_index_is_set: true + cc: AArch64CC_Invalid + writeback: 1 + regs_read: [ za, w11, z0, z1, z2, z3, z5 ] + regs_write: [ za ] + groups: [ HasSME2 ] + - + input: + bytes: [ 0xa4,0x0e,0x06,0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "movaz { z4.d - z7.d }, za.d[w8, 5, vgx4]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: z4 + is_list_member: 1 + access: CS_AC_WRITE + vas: AARCH64LAYOUT_VL_D + - + type: AARCH64_OP_REG + reg: z5 + is_list_member: 1 + access: CS_AC_WRITE + vas: AARCH64LAYOUT_VL_D + - + type: AARCH64_OP_REG + reg: z6 + is_list_member: 1 + access: CS_AC_WRITE + vas: AARCH64LAYOUT_VL_D + - + type: AARCH64_OP_REG + reg: z7 + is_list_member: 1 + access: CS_AC_WRITE + vas: AARCH64LAYOUT_VL_D + - + type: AARCH64_OP_SME + sme: + type: AARCH64_SME_OP_TILE_VEC + tile: za + slice_reg: w8 + slice_offset_imm: 5 + is_vertical: -1 + access: CS_AC_READ_WRITE + vas: AARCH64LAYOUT_VL_D + cc: AArch64CC_Invalid + writeback: 1 + regs_read: [ za, w8 ] + regs_write: [ z4, z5, z6, z7, za ] + groups: [ HasSME2p1 ] + - + input: + bytes: [ 0x80,0xa0,0x8d,0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "luti2 { z0.s - z3.s }, zt0, z4[1]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: z0 + is_list_member: 1 + access: CS_AC_WRITE + vas: AARCH64LAYOUT_VL_S + - + type: AARCH64_OP_REG + reg: z1 + is_list_member: 1 + access: CS_AC_WRITE + vas: AARCH64LAYOUT_VL_S + - + type: AARCH64_OP_REG + reg: z2 + is_list_member: 1 + access: CS_AC_WRITE + vas: AARCH64LAYOUT_VL_S + - + type: AARCH64_OP_REG + reg: z3 + is_list_member: 1 + access: CS_AC_WRITE + vas: AARCH64LAYOUT_VL_S + - + type: AARCH64_OP_REG + reg: zt0 + access: CS_AC_READ + - + type: AARCH64_OP_REG + reg: z4 + access: CS_AC_READ + vector_index: 1 + vector_index_is_set: true + cc: AArch64CC_Invalid + regs_read: [ zt0, z4 ] + regs_write: [ z0, z1, z2, z3 ] + groups: [ HasSME2 ] + - + input: + bytes: [ 0x00,0xb1,0x10,0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fmla za.h[w9, 0, vgx4], { z8.h - z11.h }, z0.h[0]" + details: + aarch64: + operands: + - + type: AARCH64_OP_SME + sme: + type: AARCH64_SME_OP_TILE_VEC + tile: za + slice_reg: w9 + slice_offset_imm: 0 + is_vertical: -1 + access: CS_AC_READ_WRITE + vas: AARCH64LAYOUT_VL_H + - + type: AARCH64_OP_REG + reg: z8 + is_list_member: 1 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_H + - + type: AARCH64_OP_REG + reg: z9 + is_list_member: 1 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_H + - + type: AARCH64_OP_REG + reg: z10 + is_list_member: 1 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_H + - + type: AARCH64_OP_REG + reg: z11 + is_list_member: 1 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_H + - + type: AARCH64_OP_REG + reg: z0 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_H + vector_index: 0 + vector_index_is_set: true + cc: AArch64CC_Invalid + writeback: 1 + regs_read: [ za, w9, z8, z9, z10, z11, z0 ] + regs_write: [ za ] + groups: [ HasSME2p1, HasSMEF16F16 ] + - + input: + bytes: [ 0x05,0xd0,0x9b,0xc1 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z11.h[1]" + details: + aarch64: + operands: + - + type: AARCH64_OP_SME + sme: + type: AARCH64_SME_OP_TILE_VEC + tile: za + slice_reg: w10 + slice_offset_ir_first: 2 + slice_offset_ir_offset: 3 + slice_offset_ir_set: true + is_vertical: -1 + access: CS_AC_READ_WRITE + vas: AARCH64LAYOUT_VL_S + - + type: AARCH64_OP_REG + reg: z0 + is_list_member: 1 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_H + - + type: AARCH64_OP_REG + reg: z1 + is_list_member: 1 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_H + - + type: AARCH64_OP_REG + reg: z2 + is_list_member: 1 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_H + - + type: AARCH64_OP_REG + reg: z3 + is_list_member: 1 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_H + - + type: AARCH64_OP_REG + reg: z11 + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_H + vector_index: 1 + vector_index_is_set: true + cc: AArch64CC_Invalid + writeback: 1 + regs_read: [ za, w10, z0, z1, z2, z3, z11 ] + regs_write: [ za ] + groups: [ HasSME2 ] + - + input: + bytes: [ 0x15,0x50,0xdf,0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov z21.d, p15/m, #-0x80" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: z21 + access: CS_AC_READ_WRITE + vas: AARCH64LAYOUT_VL_D + - + type: AARCH64_OP_PRED + pred_reg: p15 + access: CS_AC_READ + - + type: AARCH64_OP_IMM + imm: -0x80 + access: CS_AC_READ + - + input: + bytes: [ 0xd3,0x03,0x9b,0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "luti4 { z19.b, z23.b, z27.b, z31.b }, zt0, { z30, z31 }" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: z19 + is_list_member: 1 + access: CS_AC_WRITE + vas: AARCH64LAYOUT_VL_B + - + type: AARCH64_OP_REG + reg: z23 + is_list_member: 1 + access: CS_AC_WRITE + vas: AARCH64LAYOUT_VL_B + - + type: AARCH64_OP_REG + reg: z27 + is_list_member: 1 + access: CS_AC_WRITE + vas: AARCH64LAYOUT_VL_B + - + type: AARCH64_OP_REG + reg: z31 + is_list_member: 1 + access: CS_AC_WRITE + vas: AARCH64LAYOUT_VL_B + - + type: AARCH64_OP_REG + reg: zt0 + access: CS_AC_READ + - + type: AARCH64_OP_REG + reg: z30 + is_list_member: 1 + access: CS_AC_READ + - + type: AARCH64_OP_REG + reg: z31 + is_list_member: 1 + access: CS_AC_READ + regs_read: [ zt0, z30, z31 ] + regs_write: [ z19, z23, z27, z31 ] + groups: [ HasSME2p1, HasSME_LUTv2 ] diff --git a/tests/details/alpha.yaml b/tests/details/alpha.yaml new file mode 100644 index 0000000000..3d68860439 --- /dev/null +++ b/tests/details/alpha.yaml @@ -0,0 +1,130 @@ +test_cases: + - + input: + bytes: [ 0x02, 0x00, 0xbb, 0x27, 0x50, 0x7a, 0xbd, 0x23, 0xd0, 0xff, 0xde, 0x23, 0x00, 0x00, 0x5e, 0xb7 ] + arch: "alpha" + options: [ CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldah $15,2($13)" + details: + alpha: + operands: + - + type: ALPHA_OP_REG + reg: $15 + - + type: ALPHA_OP_IMM + imm: 0x2 + - + type: ALPHA_OP_REG + reg: $13 + - + asm_text: "lda $15,0x7a50($15)" + details: + alpha: + operands: + - + type: ALPHA_OP_REG + reg: $15 + - + type: ALPHA_OP_IMM + imm: 0x7a50 + - + type: ALPHA_OP_REG + reg: $15 + - + asm_text: "lda $30,0xffd0($30)" + details: + alpha: + operands: + - + type: ALPHA_OP_REG + reg: $30 + - + type: ALPHA_OP_IMM + imm: 0xffd0 + - + type: ALPHA_OP_REG + reg: $30 + - + asm_text: "stq $12,0($30)" + details: + alpha: + operands: + - + type: ALPHA_OP_REG + reg: $12 + - + type: ALPHA_OP_IMM + imm: 0x0 + - + type: ALPHA_OP_REG + reg: $30 + - + input: + bytes: [ 0x27, 0xbb, 0x00, 0x02, 0x23, 0xbd, 0x7a, 0x50, 0x23, 0xde, 0xff, 0xd0, 0xb7, 0x5e, 0x00, 0x00 ] + arch: "alpha" + options: [ CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldah $15,2($13)" + details: + alpha: + operands: + - + type: ALPHA_OP_REG + reg: $15 + - + type: ALPHA_OP_IMM + imm: 0x2 + - + type: ALPHA_OP_REG + reg: $13 + - + asm_text: "lda $15,0x7a50($15)" + details: + alpha: + operands: + - + type: ALPHA_OP_REG + reg: $15 + - + type: ALPHA_OP_IMM + imm: 0x7a50 + - + type: ALPHA_OP_REG + reg: $15 + - + asm_text: "lda $30,0xffd0($30)" + details: + alpha: + operands: + - + type: ALPHA_OP_REG + reg: $30 + - + type: ALPHA_OP_IMM + imm: 0xffd0 + - + type: ALPHA_OP_REG + reg: $30 + - + asm_text: "stq $12,0($30)" + details: + alpha: + operands: + - + type: ALPHA_OP_REG + reg: $12 + - + type: ALPHA_OP_IMM + imm: 0x0 + - + type: ALPHA_OP_REG + reg: $30 + diff --git a/tests/details/arm.yaml b/tests/details/arm.yaml new file mode 100644 index 0000000000..fe862b5335 --- /dev/null +++ b/tests/details/arm.yaml @@ -0,0 +1,2291 @@ +test_cases: + - + input: + bytes: [ 0x86, 0x48, 0x60, 0xf4, 0x4d, 0x0f, 0xe2, 0xf4, 0xed, 0xff, 0xff, 0xeb, 0x04, 0xe0, 0x2d, 0xe5, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x83, 0x22, 0xe5, 0xf1, 0x02, 0x03, 0x0e, 0x00, 0x00, 0xa0, 0xe3, 0x02, 0x30, 0xc1, 0xe7, 0x00, 0x00, 0x53, 0xe3, 0x00, 0x02, 0x01, 0xf1, 0x05, 0x40, 0xd0, 0xe8, 0xf4, 0x80, 0x00, 0x00 ] + arch: "arm" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x80001000 + expected: + insns: + - + asm_text: "vld2.32 {d20, d21}, [r0], r6" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: d20 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: d21 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r0 + mem_index: r6 + access: CS_AC_READ_WRITE + post_indexed: 1 + vector_size: 32 + writeback: 1 + regs_read: [ r0, r6 ] + regs_write: [ r0, d20, d21 ] + - + asm_text: "vld4.16 {d16[], d17[], d18[], d19[]}, [r2]!" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: d16 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: d17 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: d18 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: d19 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r2 + access: CS_AC_READ_WRITE + post_indexed: -1 + vector_size: 16 + writeback: 1 + regs_read: [ r2 ] + regs_write: [ r2, d16, d17, d18, d19 ] + - + asm_text: "bl 0x80000fc4" + details: + arm: + operands: + - + type: ARM_OP_IMM + imm: 0x80000fc4 + access: CS_AC_READ + regs_read: [ r13 ] + regs_write: [ r14 ] + - + asm_text: "str lr, [sp, #-4]!" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r14 + access: CS_AC_READ + - + type: ARM_OP_MEM + mem_base: r13 + mem_disp: 0x4 + access: CS_AC_WRITE + subtracted: 1 + post_indexed: -1 + writeback: 1 + regs_read: [ r14, r13 ] + regs_write: [ r13 ] + - + asm_text: "andeq r0, r0, r0" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_READ + cc: ARMCC_EQ + regs_read: [ cpsr, r0 ] + regs_write: [ r0 ] + - + asm_text: "str r8, [r2, #-0x3e0]!" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r8 + access: CS_AC_READ + - + type: ARM_OP_MEM + mem_base: r2 + mem_disp: 0x3e0 + access: CS_AC_WRITE + subtracted: 1 + post_indexed: -1 + writeback: 1 + regs_read: [ r8, r2 ] + regs_write: [ r2 ] + - + asm_text: "mcreq p2, #0, r0, c3, c1, #7" + details: + arm: + operands: + - + type: ARM_OP_PIMM + imm: 2 + access: CS_AC_READ + - + type: ARM_OP_IMM + imm: 0x0 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_READ + - + type: ARM_OP_CIMM + imm: 3 + access: CS_AC_READ + - + type: ARM_OP_CIMM + imm: 1 + access: CS_AC_READ + - + type: ARM_OP_IMM + imm: 0x7 + access: CS_AC_READ + cc: ARMCC_EQ + regs_read: [ cpsr, r0 ] + - + asm_text: "mov r0, #0" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_WRITE + - + type: ARM_OP_IMM + imm: 0x0 + access: CS_AC_READ + regs_write: [ r0 ] + - + asm_text: "strb r3, [r1, r2]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r3 + access: CS_AC_READ + - + type: ARM_OP_MEM + mem_base: r1 + mem_index: r2 + access: CS_AC_WRITE + regs_read: [ r3, r1, r2 ] + - + asm_text: "cmp r3, #0" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r3 + access: CS_AC_READ + - + type: ARM_OP_IMM + imm: 0x0 + access: CS_AC_READ + update_flags: 1 + regs_read: [ r3 ] + regs_write: [ cpsr ] + - + asm_text: "setend be" + details: + arm: + operands: + - + type: ARM_OP_SETEND + setend: ARM_SETEND_BE + - + asm_text: "ldm r0, {r0, r2, lr} ^" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r2 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r14 + access: CS_AC_WRITE + regs_read: [ r0 ] + regs_write: [ r0, r2, r14 ] + - + asm_text: "strdeq r8, r9, [r0], -r4" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r8 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r9 + access: CS_AC_READ + - + type: ARM_OP_MEM + mem_base: r0 + mem_index: r4 + access: CS_AC_WRITE + subtracted: 1 + cc: ARMCC_EQ + post_indexed: 1 + writeback: 1 + regs_read: [ cpsr, r8, r9, r0, r4 ] + regs_write: [ r0 ] + + - + input: + bytes: [ 0x60, 0xf9, 0x1f, 0x04, 0xe0, 0xf9, 0x4f, 0x07, 0x70, 0x47, 0x00, 0xf0, 0x10, 0xe8, 0xeb, 0x46, 0x83, 0xb0, 0xc9, 0x68, 0x1f, 0xb1, 0x30, 0xbf, 0xaf, 0xf3, 0x20, 0x84, 0x52, 0xf8, 0x23, 0xf0 ] + arch: "arm" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x80001000 + expected: + insns: + - + asm_text: "vld3.8 {d16, d17, d18}, [r0:0x40]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: d16 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: d17 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: d18 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r0 + mem_align: 0x40 + access: CS_AC_READ + vector_size: 8 + regs_read: [ r0 ] + regs_write: [ d16, d17, d18 ] + - + asm_text: "vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: d16 + neon_lane: 1 + access: CS_AC_READ_WRITE + - + type: ARM_OP_REG + reg: d17 + neon_lane: 1 + access: CS_AC_READ_WRITE + - + type: ARM_OP_REG + reg: d18 + neon_lane: 1 + access: CS_AC_READ_WRITE + - + type: ARM_OP_REG + reg: d19 + neon_lane: 1 + access: CS_AC_READ_WRITE + - + type: ARM_OP_MEM + mem_base: r0 + access: CS_AC_READ + vector_size: 16 + regs_read: [ d16, d17, d18, d19, r0 ] + regs_write: [ d16, d17, d18, d19 ] + - + asm_text: "bx lr" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r14 + access: CS_AC_READ + regs_read: [ r14 ] + - + asm_text: "blx 0x8000102c" + details: + arm: + operands: + - + type: ARM_OP_IMM + imm: 0x8000102c + access: CS_AC_READ + regs_read: [ r13 ] + regs_write: [ r14 ] + - + asm_text: "mov r11, sp" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r11 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r13 + access: CS_AC_READ + regs_read: [ r13 ] + regs_write: [ r11 ] + - + asm_text: "sub sp, #0xc" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r13 + access: CS_AC_READ_WRITE + - + type: ARM_OP_IMM + imm: 0xc + access: CS_AC_READ + post_indexed: -1 + writeback: 1 + regs_read: [ r13 ] + regs_write: [ r13 ] + - + asm_text: "ldr r1, [r1, #0xc]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r1 + mem_disp: 0xc + access: CS_AC_READ + regs_read: [ r1 ] + regs_write: [ r1 ] + - + asm_text: "cbz r7, 0x8000101e" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r7 + access: CS_AC_READ + - + type: ARM_OP_IMM + imm: 0x8000101e + access: CS_AC_READ + regs_read: [ r7 ] + - + asm_text: "wfi" + - + asm_text: "cpsie.w f" + details: + arm: + cps_mode: ARM_CPSMODE_IE + cps_flag: ARM_CPSFLAG_F + - + asm_text: "ldr.w pc, [r2, r3, lsl #2]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r15 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r2 + mem_index: r3 + shift_type: ARM_SFT_LSL + shift_value: 2 + regs_read: [ r2, r3 ] + regs_write: [ r15 ] + + - + input: + bytes: [ 0xd1, 0xe8, 0x00, 0xf0, 0xf0, 0x24, 0x04, 0x07, 0x1f, 0x3c, 0xf2, 0xc0, 0x00, 0x00, 0x4f, 0xf0, 0x00, 0x01, 0x46, 0x6c ] + arch: "arm" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x80001000 + expected: + insns: + - + asm_text: "tbb [r1, r0]" + details: + arm: + operands: + - + type: ARM_OP_MEM + mem_base: r1 + mem_index: r0 + access: CS_AC_READ + regs_read: [ r1, r0 ] + - + asm_text: "movs r4, #0xf0" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r4 + access: CS_AC_WRITE + - + type: ARM_OP_IMM + imm: 0xf0 + access: CS_AC_READ + update_flags: 1 + regs_write: [ cpsr, r4 ] + - + asm_text: "lsls r4, r0, #0x1c" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r4 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_READ + - + type: ARM_OP_IMM + imm: 0x1c + access: CS_AC_READ + update_flags: 1 + regs_read: [ r0 ] + regs_write: [ cpsr, r4 ] + - + asm_text: "subs r4, #0x1f" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r4 + access: CS_AC_READ_WRITE + - + type: ARM_OP_IMM + imm: 0x1f + access: CS_AC_READ + update_flags: 1 + post_indexed: -1 + writeback: 1 + regs_read: [ r4 ] + regs_write: [ cpsr, r4 ] + - + asm_text: "stm r0!, {r1, r4, r5, r6, r7}" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_READ_WRITE + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r4 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r5 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r6 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r7 + access: CS_AC_READ + post_indexed: -1 + writeback: 1 + regs_read: [ r0, r1, r4, r5, r6, r7 ] + regs_write: [ r0 ] + - + asm_text: "movs r0, r0" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_READ + update_flags: 1 + regs_read: [ r0 ] + regs_write: [ cpsr, r0 ] + - + asm_text: "mov.w r1, #0" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_WRITE + - + type: ARM_OP_IMM + imm: 0x0 + access: CS_AC_READ + regs_write: [ r1 ] + - + asm_text: "ldr r6, [r0, #0x44]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r6 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r0 + mem_disp: 0x44 + access: CS_AC_READ + regs_read: [ r0 ] + regs_write: [ r6 ] + + - + input: + bytes: [ 0x4f, 0xf0, 0x00, 0x01, 0xbd, 0xe8, 0x00, 0x88, 0xd1, 0xe8, 0x00, 0xf0, 0x18, 0xbf, 0xad, 0xbf, 0xf3, 0xff, 0x0b, 0x0c, 0x86, 0xf3, 0x00, 0x89, 0x80, 0xf3, 0x00, 0x8c, 0x4f, 0xfa, 0x99, 0xf6, 0xd0, 0xff, 0xa2, 0x01 ] + arch: "arm" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x80001000 + expected: + insns: + - + asm_text: "mov.w r1, #0" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_WRITE + - + type: ARM_OP_IMM + imm: 0x0 + access: CS_AC_READ + regs_write: [ r1 ] + - + asm_text: "pop.w {r11, pc}" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r11 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r15 + access: CS_AC_WRITE + post_indexed: -1 + writeback: 1 + regs_write: [ r11, r15 ] + - + asm_text: "tbb [r1, r0]" + details: + arm: + operands: + - + type: ARM_OP_MEM + mem_base: r1 + mem_index: r0 + access: CS_AC_READ + regs_read: [ r1, r0 ] + - + asm_text: "it ne" + details: + arm: + cc: ARMCC_NE + pred_mask: 0x1 + regs_read: [ cpsr ] + regs_write: [ itstate ] + - + asm_text: "iteet ge" + details: + arm: + cc: ARMCC_GE + pred_mask: 0xd + regs_read: [ cpsr ] + regs_write: [ itstate ] + - + asm_text: "vdupge.8 d16, d11[1]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: d16 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: d11 + access: CS_AC_READ + vector_index: 1 + vector_index_is_set: true + cc: ARMCC_GE + vector_size: 8 + regs_read: [ cpsr, d11 ] + regs_write: [ d16 ] + - + asm_text: "msrlt cpsr_fc, r6" + details: + arm: + operands: + - + type: ARM_OP_CPSR + sys_psr_bits: [ ARM_FIELD_CPSR_C, ARM_FIELD_CPSR_C ] + sys_msr_mask: 9 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r6 + access: CS_AC_READ + cc: ARMCC_LT + update_flags: 1 + regs_read: [ cpsr, r6 ] + regs_write: [ cpsr ] + - + asm_text: "msrlt apsr_nzcvqg, r0" + details: + arm: + operands: + - + type: ARM_OP_SYSREG + reg: apsr_nzcvqg + sys_msr_mask: 12 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_READ + cc: ARMCC_LT + update_flags: 1 + regs_read: [ cpsr, r0 ] + regs_write: [ cpsr ] + - + asm_text: "sxtbge.w r6, r9, ror #8" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r6 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r9 + access: CS_AC_READ + shift_type: ARM_SFT_ROR + shift_value: 8 + cc: ARMCC_GE + regs_read: [ cpsr, r9 ] + regs_write: [ r6 ] + - + asm_text: "vaddw.u16 q8, q8, d18" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: q8 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: q8 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: d18 + access: CS_AC_READ + vector_data: ARM_VECTORDATA_U16 + regs_read: [ q8, d18 ] + regs_write: [ q8 ] + + - + input: + bytes: [ 0xef, 0xf3, 0x02, 0x80 ] + arch: "arm" + options: [ CS_MODE_THUMB, CS_MODE_MCLASS, CS_OPT_DETAIL ] + address: 0x80001000 + expected: + insns: + - + asm_text: "mrs r0, eapsr" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_WRITE + - + type: ARM_OP_SYSREG + reg: eapsr + sys_msr_mask: 2 + access: CS_AC_READ + regs_write: [ r0 ] + + - + input: + bytes: [ 0xe0, 0x3b, 0xb2, 0xee, 0x42, 0x00, 0x01, 0xe1, 0x51, 0xf0, 0x7f, 0xf5 ] + arch: "arm" + options: [ CS_MODE_ARM, CS_MODE_V8, CS_OPT_DETAIL ] + address: 0x80001000 + expected: + insns: + - + asm_text: "vcvtt.f64.f16 d3, s1" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: d3 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s1 + access: CS_AC_READ + vector_data: ARM_VECTORDATA_F64F16 + regs_read: [ s1 ] + regs_write: [ d3 ] + - + asm_text: "crc32b r0, r1, r2" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r2 + access: CS_AC_READ + regs_read: [ r1, r2 ] + regs_write: [ r0 ] + - + asm_text: "dmb oshld" + details: + arm: + mem_barrier: ARM_MB_OSHLD + - + input: + bytes: [ 0x90,0xe8,0x0e,0x00 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldm.w r0, {r1, r2, r3}" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r2 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r3 + access: CS_AC_WRITE + regs_read: [ r0 ] + regs_write: [ r1, r2, r3 ] + groups: [ IsThumb2 ] + - + input: + bytes: [ 0x0e,0xc8 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldm r0!, {r1, r2, r3}" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_READ_WRITE + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r2 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r3 + access: CS_AC_WRITE + writeback: 1 + regs_read: [ r0 ] + regs_write: [ r0, r1, r2, r3 ] + groups: [ IsThumb ] + - + input: + bytes: [ 0x00,0x2a,0xf7,0xee ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "vmov.f32 s5, #1.000000e+00" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: s5 + access: CS_AC_WRITE + - + type: ARM_OP_FP + fp: 1.0 + regs_write: [ s5 ] + groups: [ HasVFP3 ] + - + input: + bytes: [ 0x0f,0x00,0x71,0xe3 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "cmn r1, #0xf" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_READ + - + type: ARM_OP_IMM + imm: 0xf + access: CS_AC_READ + update_flags: 1 + regs_read: [ r1 ] + regs_write: [ cpsr ] + groups: [ IsARM ] + - + input: + bytes: [ 0x03,0x20,0xb0,0xe1 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "movs r2, r3" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r2 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r3 + access: CS_AC_READ + update_flags: 1 + regs_read: [ r3 ] + regs_write: [ cpsr, r2 ] + groups: [ IsARM ] + - + input: + bytes: [ 0xfd,0x8f ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldrh r5, [r7, #0x3e]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r5 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r7 + mem_disp: 0x3e + access: CS_AC_READ + regs_read: [ r7 ] + regs_write: [ r5 ] + groups: [ IsThumb ] + - + input: + bytes: [ 0x61,0xb6 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "cpsie f" + details: + arm: + cps_mode: ARM_CPSMODE_IE + cps_flag: ARM_CPSFLAG_F + groups: [ IsThumb ] + - + input: + bytes: [ 0x18,0xf8,0x03,0x1e ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldrbt r1, [r8, #3]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r8 + mem_disp: 0x3 + access: CS_AC_READ + regs_read: [ r8 ] + regs_write: [ r1 ] + groups: [ IsThumb2 ] + - + input: + bytes: [ 0xb0,0xf8,0x01,0xf1 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "pldw [r0, #0x101]" + details: + arm: + operands: + - + type: ARM_OP_MEM + mem_base: r0 + mem_disp: 0x101 + access: CS_AC_READ + regs_read: [ r0 ] + groups: [ IsThumb2, HasV7, HasMP ] + - + input: + bytes: [ 0xd3,0xe8,0x08,0xf0 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "tbb [r3, r8]" + details: + arm: + operands: + - + type: ARM_OP_MEM + mem_base: r3 + mem_index: r8 + access: CS_AC_READ + regs_read: [ r3, r8 ] + groups: [ jump, IsThumb2 ] + - + input: + bytes: [ 0xd3,0xe8,0x18,0xf0 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "tbh [r3, r8, lsl #1]" + details: + arm: + operands: + - + type: ARM_OP_MEM + mem_base: r3 + mem_index: r8 + access: CS_AC_READ + shift_type: ARM_SFT_LSL + shift_value: 1 + regs_read: [ r3, r8 ] + groups: [ jump, IsThumb2 ] + - + input: + bytes: [ 0xaf,0xf3,0x43,0x85 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "cpsie i, #3" + details: + arm: + operands: + - + type: ARM_OP_IMM + imm: 0x3 + access: CS_AC_READ + cps_mode: ARM_CPSMODE_IE + cps_flag: ARM_CPSFLAG_I + groups: [ IsThumb2, IsNotMClass ] + - + input: + bytes: [ 0xbf,0xf3,0x6f,0x8f ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "isb sy" + details: + arm: + mem_barrier: ARM_MB_SY + groups: [ IsThumb, HasDB ] + - + input: + bytes: [ 0x59,0xea,0x7b,0x89 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_MODE_V8, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "csel r9, r9, r11, vc" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r9 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r9 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r11 + access: CS_AC_READ + cc: ARMCC_VC + regs_read: [ cpsr, r9, r11 ] + regs_write: [ r9 ] + groups: [ HasV8_1MMainline ] + - + input: + bytes: [ 0xbf,0xf3,0x56,0x8f ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "dmb nshst" + details: + arm: + mem_barrier: ARM_MB_NSHST + groups: [ IsThumb, HasDB ] + - + input: + bytes: [ 0x31,0xfa,0x02,0xf2 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "lsrs.w r2, r1, r2" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r2 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r2 + access: CS_AC_READ + update_flags: 1 + regs_read: [ r1, r2 ] + regs_write: [ cpsr, r2 ] + groups: [ IsThumb2 ] + - + input: + bytes: [ 0x08,0xbf,0x5f,0xf0,0x0c,0x01 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "it eq" + details: + arm: + cc: ARMCC_EQ + pred_mask: 0x1 + regs_write: [ itstate ] + groups: [ IsThumb2 ] + - + asm_text: "movseq.w r1, #0xc" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_WRITE + - + type: ARM_OP_IMM + imm: 0xc + access: CS_AC_READ + cc: ARMCC_EQ + update_flags: 1 + regs_write: [ cpsr, r1 ] + groups: [ IsThumb2 ] + - + input: + bytes: [ 0x52,0xe8,0x01,0x1f ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldrex r1, [r2, #4]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r2 + mem_disp: 0x4 + access: CS_AC_READ + regs_read: [ r2 ] + regs_write: [ r1 ] + groups: [ IsThumb, HasV8MBaseline ] + - + input: + bytes: [ 0x88,0xbf,0xdf,0xec,0x1d,0x1a ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_MODE_V8, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "it hi" + details: + arm: + cc: ARMCC_HI + pred_mask: 0x1 + groups: [ IsThumb2 ] + - + asm_text: "vscclrmhi {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: s3 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s4 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s5 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s6 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s7 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s8 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s9 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s10 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s11 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s12 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s13 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s14 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s15 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s16 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s17 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s18 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s19 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s20 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s21 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s22 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s23 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s24 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s25 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s26 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s27 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s28 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s29 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s30 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: s31 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: vpr + access: CS_AC_WRITE + cc: ARMCC_HI + regs_write: [ s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr ] + groups: [ HasV8_1MMainline, Has8MSecExt ] + - + input: + bytes: [ 0x9f,0xec,0x06,0x5b ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_MODE_V8, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "vscclrm {d5, d6, d7, vpr}" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: d5 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: d6 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: d7 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: vpr + access: CS_AC_WRITE + regs_write: [ d5, d6, d7, vpr ] + groups: [ HasV8_1MMainline, Has8MSecExt ] + - + input: + bytes: [ 0xbc,0xfd,0x7f,0xaf ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_MODE_V8, CS_MODE_MCLASS, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "vldrh.u32 q5, [r4, #0xfe]!" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: q5 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r4 + mem_disp: 0xfe + access: CS_AC_READ + writeback: 1 + regs_read: [ r4 ] + regs_write: [ r4, q5 ] + groups: [ HasMVEInt ] + - + input: + bytes: [ 0x80,0xfc,0x80,0x1e ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_MODE_MCLASS, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "vst20.16 {q0, q1}, [r0]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: q0 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: q1 + access: CS_AC_READ + - + type: ARM_OP_MEM + mem_base: r0 + access: CS_AC_WRITE + regs_read: [ q0, q1, r0 ] + groups: [ HasMVEInt ] + - + input: + bytes: [ 0x98,0xfc,0x4e,0x08 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_MODE_MCLASS, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "vcadd.f32 q0, q4, q7, #90" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: q0 + access: CS_AC_READ_WRITE + - + type: ARM_OP_REG + reg: q4 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: q7 + access: CS_AC_READ + - + type: ARM_OP_IMM + imm: 0x5a + access: CS_AC_READ + regs_read: [ q0, q4, q7 ] + regs_write: [ q0 ] + groups: [ HasMVEFloat ] + - + input: + bytes: [ 0x94,0xfd,0x46,0x48 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_MODE_V8, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "vcadd.f32 q2, q2, q3, #270" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: q2 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: q2 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: q3 + access: CS_AC_READ + - + type: ARM_OP_IMM + imm: 0x10e + access: CS_AC_READ + regs_read: [ q2, q3 ] + regs_write: [ q2 ] + groups: [ HasNEON, HasV8_3a ] + - + input: + bytes: [ 0x9d,0xec,0x82,0x6e ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_MODE_MCLASS, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "vldrb.s16 q3, [sp, q1]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: q3 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r13 + mem_index: q1 + access: CS_AC_READ + regs_read: [ r13, q1 ] + regs_write: [ q3 ] + groups: [ HasMVEInt ] + - + input: + bytes: [ 0x90,0xec,0x12,0x6f ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_MODE_MCLASS, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "vldrh.s32 q3, [r0, q1]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: q3 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r0 + mem_index: q1 + access: CS_AC_READ + regs_read: [ r0, q1 ] + regs_write: [ q3 ] + groups: [ HasMVEInt ] + - + input: + bytes: [ 0x5f,0xea,0x2d,0x83 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_MODE_V8, CS_MODE_MCLASS, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "sqrshrl lr, r3, #0x40, r8" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r14 + access: CS_AC_READ_WRITE + - + type: ARM_OP_REG + reg: r3 + access: CS_AC_READ_WRITE + - + type: ARM_OP_IMM + imm: 0x40 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r8 + access: CS_AC_READ + writeback: 1 + regs_read: [ r14, r3, r8 ] + regs_write: [ r14, r3 ] + groups: [ HasV8_1MMainline, HasMVEInt ] + - + input: + bytes: [ 0x82,0xfd,0x21,0xff ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_MODE_MCLASS, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "vstrd.64 q7, [q1, #0x108]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: q7 + access: CS_AC_READ + - + type: ARM_OP_MEM + mem_base: q1 + mem_disp: 0x108 + access: CS_AC_WRITE + regs_read: [ q7, q1 ] + groups: [ HasMVEInt ] + - + input: + bytes: [ 0x06,0x16,0x72,0xe6 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldrbt r1, [r2], -r6, lsl #12" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r2 + mem_index: r6 + access: CS_AC_READ + shift_type: ARM_SFT_LSL + shift_value: 12 + subtracted: 1 + writeback: 1 + regs_read: [ r2, r6 ] + regs_write: [ r2, r1 ] + groups: [ IsARM ] + - + input: + bytes: [ 0xf6,0x50,0x33,0xe1 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldrsh r5, [r3, -r6]!" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r5 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r3 + mem_index: r6 + access: CS_AC_READ + subtracted: 1 + writeback: 1 + regs_read: [ r3, r6 ] + regs_write: [ r3, r5 ] + groups: [ IsARM ] + - + input: + bytes: [ 0x1e,0x19,0x7a,0xfd ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldc2l p9, c1, [r10, #-0x78]!" + details: + arm: + operands: + - + type: ARM_OP_PIMM + imm: 9 + access: CS_AC_READ + - + type: ARM_OP_CIMM + imm: 1 + access: CS_AC_READ + - + type: ARM_OP_MEM + mem_base: r10 + mem_disp: 0x78 + access: CS_AC_READ + regs_read: [ r10 ] + regs_write: [ r10 ] + groups: [ IsARM, PreV8 ] + - + input: + bytes: [ 0x12,0x31,0x7c,0xfc ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldc2l p1, c3, [r12], #-0x48" + details: + arm: + operands: + - + type: ARM_OP_PIMM + imm: 1 + access: CS_AC_READ + - + type: ARM_OP_CIMM + imm: 3 + access: CS_AC_READ + - + type: ARM_OP_MEM + mem_base: r12 + access: CS_AC_READ + mem_disp: 0x48 + subtracted: 1 + regs_read: [ r12 ] + groups: [ IsARM, PreV8 ] + - + input: + bytes: [ 0xa4,0xf9,0x6d,0x0e ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "vld3.16 {d0[], d2[], d4[]}, [r4]!" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: d0 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: d2 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: d4 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r4 + access: CS_AC_READ_WRITE + writeback: 1 + regs_read: [ r4 ] + regs_write: [ r4, d0, d2, d4 ] + - + input: + bytes: [ 0x0d,0x50,0x66,0xe4 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "strbt r5, [r6], #-0xd" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r5 + access: CS_AC_READ + - + type: ARM_OP_MEM + mem_base: r6 + access: CS_AC_WRITE + mem_disp: 0xd + subtracted: 1 + writeback: 1 + regs_read: [ r5, r6 ] + regs_write: [ r6 ] + groups: [ IsARM ] + - + input: + bytes: [ 0x00,0x10,0x4f,0xe2 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "sub r1, pc, #0" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r15 + access: CS_AC_READ + - + type: ARM_OP_IMM + imm: 0x0 + access: CS_AC_READ + regs_read: [ r15 ] + regs_write: [ r1 ] + groups: [ IsARM ] + - + input: + bytes: [ 0x9f,0x51,0xd3,0xe7 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "bfc r5, #3, #0x11" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r5 + access: CS_AC_READ_WRITE + - + type: ARM_OP_IMM + imm: 0x3 + access: CS_AC_READ + - + type: ARM_OP_IMM + imm: 0x11 + access: CS_AC_READ + writeback: 1 + regs_read: [ r5 ] + regs_write: [ r5 ] + groups: [ IsARM, HasV6T2 ] + - + input: + bytes: [ 0xd8,0xe8,0xff,0x67 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldaexd r6, r7, [r8]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r6 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r7 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r8 + access: CS_AC_READ + regs_read: [ r8 ] + regs_write: [ r6, r7 ] + groups: [ IsThumb, HasAcquireRelease, HasV7Clrex, IsNotMClass ] + - + input: + bytes: [ 0x30,0x0f,0xa6,0xe6 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ssat16 r0, #7, r0" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_WRITE + - + type: ARM_OP_IMM + imm: 0x7 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_READ + regs_read: [ r0 ] + regs_write: [ r0 ] + groups: [ IsARM, HasV6 ] + - + input: + bytes: [ 0x9a,0x8f,0xa0,0xe6 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ssat r8, #1, r10, lsl #0x1f" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r8 + access: CS_AC_WRITE + - + type: ARM_OP_IMM + imm: 0x1 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r10 + access: CS_AC_READ + shift_type: ARM_SFT_LSL + shift_value: 31 + regs_read: [ r10 ] + regs_write: [ r8 ] + groups: [ IsARM, HasV6 ] + - + input: + bytes: [ 0x40,0x1b,0xf5,0xee ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "vcmp.f64 d17, #0" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: d17 + access: CS_AC_READ + - + type: ARM_OP_IMM + imm: 0x0 + access: CS_AC_READ + update_flags: 1 + regs_read: [ d17 ] + regs_write: [ fpscr_nzcv ] + groups: [ HasVFP2, HasDPVFP ] + - + input: + bytes: [ 0x05,0xf0,0x2f,0xe3 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "msr cpsr_fsxc, #5" + details: + arm: + operands: + - + type: ARM_OP_CPSR + sys_psr_bits: [ ARM_FIELD_CPSR_F, ARM_FIELD_CPSR_S, ARM_FIELD_CPSR_X, ARM_FIELD_CPSR_C ] + sys_msr_mask: 0xf + access: CS_AC_WRITE + - + type: ARM_OP_IMM + imm: 0x5 + access: CS_AC_READ + update_flags: 1 + regs_write: [ cpsr ] + groups: [ IsARM ] + - + input: + bytes: [ 0xa4,0xf9,0xed,0x0b ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:0x80]!" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: d0 + neon_lane: 1 + access: CS_AC_READ_WRITE + - + type: ARM_OP_REG + reg: d2 + neon_lane: 1 + access: CS_AC_READ_WRITE + - + type: ARM_OP_REG + reg: d4 + neon_lane: 1 + access: CS_AC_READ_WRITE + - + type: ARM_OP_REG + reg: d6 + neon_lane: 1 + access: CS_AC_READ_WRITE + - + type: ARM_OP_MEM + mem_base: r4 + mem_align: 0x80 + access: CS_AC_READ_WRITE + writeback: 1 + regs_read: [ d0, d2, d4, d6, r4 ] + regs_write: [ r4, d0, d2, d4, d6 ] + - + input: + bytes: [ 0x42,0x03,0xb0,0xf3 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_MODE_V8, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "aesd.8 q0, q1" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: q0 + access: CS_AC_READ_WRITE + - + type: ARM_OP_REG + reg: q1 + access: CS_AC_READ + writeback: 1 + regs_read: [ q0, q1 ] + regs_write: [ q0 ] + groups: [ HasV8, HasAES ] + - + input: + bytes: [ 0x11,0x57,0x54,0xfc ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mrrc2 p7, #1, r5, r4, c1" + details: + arm: + operands: + - + type: ARM_OP_PIMM + imm: 7 + access: CS_AC_READ + - + type: ARM_OP_IMM + imm: 0x1 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r5 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r4 + access: CS_AC_WRITE + - + type: ARM_OP_CIMM + imm: 1 + access: CS_AC_READ + regs_write: [ r5, r4 ] + groups: [ IsARM, PreV8 ] + - + input: + bytes: [ 0xd3,0x2f,0x82,0xe6 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "pkhtb r2, r2, r3, asr #0x1f" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r2 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r2 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r3 + access: CS_AC_READ + shift_type: ARM_SFT_ASR + shift_value: 31 + regs_read: [ r2, r3 ] + regs_write: [ r2 ] + groups: [ IsARM, HasV6 ] + - + input: + bytes: [ 0x93,0x27,0x82,0xe6 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "pkhbt r2, r2, r3, lsl #0xf" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r2 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r2 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r3 + access: CS_AC_READ + shift_type: ARM_SFT_LSL + shift_value: 15 + regs_read: [ r2, r3 ] + regs_write: [ r2 ] + groups: [ IsARM, HasV6 ] + - + input: + bytes: [ 0xb4,0x10,0xf0,0xe0 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldrht r1, [r0], #4" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r0 + access: CS_AC_READ + mem_disp: 0x4 + writeback: 1 + regs_read: [ r0 ] + regs_write: [ r0, r1 ] + groups: [ IsARM ] + - + input: + bytes: [ 0x2f,0xfa,0xa1,0xf3 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "sxtb16 r3, r1, ror #16" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r3 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_READ + shift_type: ARM_SFT_ROR + shift_value: 16 + regs_read: [ r1 ] + regs_write: [ r3 ] + groups: [ HasDSP, IsThumb2 ] + - + input: + bytes: [ 0x00,0x02,0x01,0xf1 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "setend be" + details: + arm: + operands: + - + type: ARM_OP_SETEND + groups: [ IsARM ] + - + input: + bytes: [ 0xd0,0xe8,0xaf,0x0f ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "lda r0, [r0]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r0 + access: CS_AC_READ + regs_read: [ r0 ] + regs_write: [ r0 ] + groups: [ IsThumb, HasAcquireRelease ] + - + input: + bytes: [ 0xef,0xf3,0x11,0x85 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldrhi pc, [r1, #-0x3ef]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r15 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r1 + mem_disp: 0x3ef + access: CS_AC_READ + cc: ARMCC_HI + regs_read: [ cpsr, r1 ] + regs_write: [ r15 ] + groups: [ IsARM, jump ] diff --git a/tests/details/bpf.yaml b/tests/details/bpf.yaml new file mode 100644 index 0000000000..8988b6ff4f --- /dev/null +++ b/tests/details/bpf.yaml @@ -0,0 +1,137 @@ +test_cases: + - + input: + bytes: [ 0x94, 0x09, 0x00, 0x00, 0x37, 0x13, 0x03, 0x00, 0x87, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "bpf" + options: [ CS_OPT_DETAIL, CS_MODE_BPF_CLASSIC ] + address: 0x0 + expected: + insns: + - + asm_text: "mod 0x31337" + details: + groups: [ BPF_GRP_ALU ] + bpf: + operands: + - + type: BPF_OP_IMM + imm: 0x31337 + regs_read: [ a ] + regs_write: [ a ] + - + asm_text: "txa" + details: + regs_read: [ x ] + groups: [ BPF_GRP_MISC ] + regs_write: [ a ] + - + asm_text: "tax" + details: + regs_read: [ a ] + groups: [ BPF_GRP_MISC ] + regs_write: [ x ] + - + asm_text: "ret a" + details: + groups: [ BPF_GRP_RETURN ] + bpf: + operands: + - + type: BPF_OP_REG + reg: a + regs_read: [ a ] + - + asm_text: "ld #len" + details: + groups: [ BPF_GRP_LOAD ] + bpf: + operands: + - + type: BPF_OP_EXT + ext: BPF_EXT_LEN + regs_write: [ a ] + - + input: + bytes: [ 0x97, 0x09, 0x00, 0x00, 0x37, 0x13, 0x03, 0x00, 0xdc, 0x02, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xdb, 0x3a, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x84, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6d, 0x33, 0x17, 0x02, 0x00, 0x00, 0x00, 0x00 ] + arch: "bpf" + options: [ CS_OPT_DETAIL, CS_MODE_BPF_EXTENDED ] + address: 0x0 + expected: + insns: + - + asm_text: "mod64 r9, 0x31337" + details: + groups: [ BPF_GRP_ALU ] + bpf: + operands: + - + type: BPF_OP_REG + reg: r9 + - + type: BPF_OP_IMM + imm: 0x31337 + regs_read: [ r9 ] + regs_write: [ r9 ] + - + asm_text: "be32 r2" + details: + groups: [ BPF_GRP_ALU ] + bpf: + operands: + - + type: BPF_OP_REG + reg: r2 + regs_read: [ r2 ] + regs_write: [ r2 ] + - + asm_text: "ldb [0x0]" + details: + groups: [ BPF_GRP_LOAD ] + bpf: + operands: + - + type: BPF_OP_MEM + mem_disp: 0x0 + regs_write: [ r0 ] + - + asm_text: "xadddw [r10+0x100], r3" + details: + groups: [ BPF_GRP_STORE ] + bpf: + operands: + - + type: BPF_OP_MEM + mem_base: r10 + mem_disp: 0x100 + - + type: BPF_OP_REG + reg: r3 + regs_read: [ r3, r10 ] + - + asm_text: "neg r2" + details: + groups: [ BPF_GRP_ALU ] + bpf: + operands: + - + type: BPF_OP_REG + reg: r2 + regs_read: [ r2 ] + regs_write: [ r2 ] + - + asm_text: "jsgt r3, r3, +0x217" + details: + groups: [ BPF_GRP_JUMP ] + bpf: + operands: + - + type: BPF_OP_REG + reg: r3 + - + type: BPF_OP_REG + reg: r3 + - + type: BPF_OP_OFF + off: 0x217 + regs_read: [ r3 ] + diff --git a/tests/details/cs_common_details.yaml b/tests/details/cs_common_details.yaml new file mode 100644 index 0000000000..4dd602077d --- /dev/null +++ b/tests/details/cs_common_details.yaml @@ -0,0 +1,2213 @@ +test_cases: + - + input: + bytes: [ 0x8d, 0x4c, 0x32, 0x08, 0x01, 0xd8, 0x81, 0xc6, 0x34, 0x12, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_OPT_DETAIL, CS_MODE_16 ] + address: 0x1000 + expected: + insns: + - + asm_text: "lea cx, [si + 0x32]" + mnemonic: "lea" + op_str: "cx, [si + 0x32]" + - + asm_text: "or byte ptr [bx + di], al" + mnemonic: "or" + op_str: "byte ptr [bx + di], al" + details: + regs_impl_write: [ flags ] + - + asm_text: "fadd dword ptr [bx + di + 0x34c6]" + mnemonic: "fadd" + op_str: "dword ptr [bx + di + 0x34c6]" + details: + regs_impl_write: [ fpsw ] + groups: [ fpu ] + - + asm_text: "adc al, byte ptr [bx + si]" + mnemonic: "adc" + op_str: "al, byte ptr [bx + si]" + details: + regs_impl_read: [ flags ] + regs_impl_write: [ flags ] + - + input: + bytes: [ 0x8d, 0x4c, 0x32, 0x08, 0x01, 0xd8, 0x81, 0xc6, 0x34, 0x12, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_OPT_DETAIL, CS_MODE_32, CS_OPT_SYNTAX_ATT] + address: 0x1000 + expected: + insns: + - + asm_text: "leal 8(%edx, %esi), %ecx" + mnemonic: "leal" + op_str: "8(%edx, %esi), %ecx" + details: + groups: [ not64bitmode ] + - + asm_text: "addl %ebx, %eax" + mnemonic: "addl" + op_str: "%ebx, %eax" + details: + regs_impl_write: [ eflags ] + - + asm_text: "addl $0x1234, %esi" + mnemonic: "addl" + op_str: "$0x1234, %esi" + details: + regs_impl_write: [ eflags ] + - + input: + bytes: [ 0x8d, 0x4c, 0x32, 0x08, 0x01, 0xd8, 0x81, 0xc6, 0x34, 0x12, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_OPT_DETAIL, CS_MODE_32 ] + address: 0x1000 + expected: + insns: + - + asm_text: "lea ecx, [edx + esi + 8]" + mnemonic: "lea" + op_str: "ecx, [edx + esi + 8]" + details: + groups: [ not64bitmode ] + - + asm_text: "add eax, ebx" + mnemonic: "add" + op_str: "eax, ebx" + details: + regs_impl_write: [ eflags ] + - + asm_text: "add esi, 0x1234" + mnemonic: "add" + op_str: "esi, 0x1234" + details: + regs_impl_write: [ eflags ] + - + input: + bytes: [ 0x55, 0x48, 0x8b, 0x05, 0xb8, 0x13, 0x00, 0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_OPT_DETAIL, CS_MODE_64 ] + address: 0x1000 + expected: + insns: + - + asm_text: "push rbp" + mnemonic: "push" + op_str: "rbp" + details: + regs_impl_read: [ rsp ] + regs_impl_write: [ rsp ] + groups: [ mode64 ] + - + asm_text: "mov rax, qword ptr [rip + 0x13b8]" + mnemonic: "mov" + op_str: "rax, qword ptr [rip + 0x13b8]" + - + input: + bytes: [ 0xed, 0xff, 0xff, 0xeb, 0x04, 0xe0, 0x2d, 0xe5, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x83, 0x22, 0xe5, 0xf1, 0x02, 0x03, 0x0e, 0x00, 0x00, 0xa0, 0xe3, 0x02, 0x30, 0xc1, 0xe7, 0x00, 0x00, 0x53, 0xe3 ] + arch: "CS_ARCH_ARM" + options: [ CS_OPT_DETAIL, CS_MODE_ARM ] + address: 0x1000 + expected: + insns: + - + asm_text: "bl 0xfbc" + mnemonic: "bl" + op_str: "0xfbc" + details: + regs_impl_read: [ r13 ] + regs_impl_write: [ r14 ] + groups: [ call, branch_relative, IsARM ] + - + asm_text: "str lr, [sp, #-4]!" + mnemonic: "str" + op_str: "lr, [sp, #-4]!" + details: + regs_impl_write: [ r13 ] + groups: [ IsARM ] + - + asm_text: "andeq r0, r0, r0" + mnemonic: "andeq" + op_str: "r0, r0, r0" + details: + regs_impl_read: [ cpsr ] + groups: [ IsARM ] + - + asm_text: "str r8, [r2, #-0x3e0]!" + mnemonic: "str" + op_str: "r8, [r2, #-0x3e0]!" + details: + regs_impl_write: [ r2 ] + groups: [ IsARM ] + - + asm_text: "mcreq p2, #0, r0, c3, c1, #7" + mnemonic: "mcreq" + op_str: "p2, #0, r0, c3, c1, #7" + details: + regs_impl_read: [ cpsr ] + groups: [ IsARM, privilege ] + - + asm_text: "mov r0, #0" + mnemonic: "mov" + op_str: "r0, #0" + details: + groups: [ IsARM ] + - + asm_text: "strb r3, [r1, r2]" + mnemonic: "strb" + op_str: "r3, [r1, r2]" + details: + groups: [ IsARM ] + - + asm_text: "cmp r3, #0" + mnemonic: "cmp" + op_str: "r3, #0" + details: + regs_impl_write: [ cpsr ] + groups: [ IsARM ] + - + input: + bytes: [ 0x10, 0xf1, 0x10, 0xe7, 0x11, 0xf2, 0x31, 0xe7, 0xdc, 0xa1, 0x2e, 0xf3, 0xe8, 0x4e, 0x62, 0xf3 ] + arch: "CS_ARCH_ARM" + options: [ CS_OPT_DETAIL, CS_MODE_ARM ] + address: 0x1000 + expected: + insns: + - + asm_text: "sdiv r0, r0, r1" + mnemonic: "sdiv" + op_str: "r0, r0, r1" + details: + groups: [ IsARM, HasDivideInARM ] + - + asm_text: "udiv r1, r1, r2" + mnemonic: "udiv" + op_str: "r1, r1, r2" + details: + groups: [ IsARM, HasDivideInARM ] + - + asm_text: "vbit q5, q15, q6" + mnemonic: "vbit" + op_str: "q5, q15, q6" + details: + groups: [ HasNEON ] + - + asm_text: "vcgt.f32 q10, q9, q12" + mnemonic: "vcgt.f32" + op_str: "q10, q9, q12" + details: + groups: [ HasNEON ] + - + input: + bytes: [ 0x70, 0x47, 0xeb, 0x46, 0x83, 0xb0, 0xc9, 0x68 ] + arch: "CS_ARCH_ARM" + options: [ CS_OPT_DETAIL, CS_MODE_THUMB ] + address: 0x1000 + expected: + insns: + - + asm_text: "bx lr" + mnemonic: "bx" + op_str: "lr" + details: + groups: [ jump, IsThumb ] + - + asm_text: "mov r11, sp" + mnemonic: "mov" + op_str: "r11, sp" + details: + groups: [ IsThumb ] + - + asm_text: "sub sp, #0xc" + mnemonic: "sub" + op_str: "sp, #0xc" + details: + groups: [ IsThumb ] + - + asm_text: "ldr r1, [r1, #0xc]" + mnemonic: "ldr" + op_str: "r1, [r1, #0xc]" + details: + groups: [ IsThumb ] + - + input: + bytes: [ 0x4f, 0xf0, 0x00, 0x01, 0xbd, 0xe8, 0x00, 0x88, 0xd1, 0xe8, 0x00, 0xf0 ] + arch: "CS_ARCH_ARM" + options: [ CS_OPT_DETAIL, CS_MODE_THUMB ] + address: 0x1000 + expected: + insns: + - + asm_text: "mov.w r1, #0" + mnemonic: "mov.w" + op_str: "r1, #0" + details: + groups: [ IsThumb2 ] + - + asm_text: "pop.w {r11, pc}" + mnemonic: "pop.w" + op_str: "{r11, pc}" + details: + groups: [ IsThumb2, jump ] + - + asm_text: "tbb [r1, r0]" + mnemonic: "tbb" + op_str: "[r1, r0]" + details: + groups: [ jump, IsThumb2 ] + - + input: + bytes: [ 0xef, 0xf3, 0x02, 0x80 ] + arch: "CS_ARCH_ARM" + options: [ CS_OPT_DETAIL, CS_MODE_THUMB, CS_MODE_MCLASS ] + address: 0x1000 + expected: + insns: + - + asm_text: "mrs r0, eapsr" + mnemonic: "mrs" + op_str: "r0, eapsr" + details: + groups: [ IsThumb, IsMClass ] + - + input: + bytes: [ 0xe0, 0x3b, 0xb2, 0xee, 0x42, 0x00, 0x01, 0xe1, 0x51, 0xf0, 0x7f, 0xf5 ] + arch: "CS_ARCH_ARM" + options: [ CS_OPT_DETAIL, CS_MODE_ARM, CS_MODE_V8 ] + address: 0x1000 + expected: + insns: + - + asm_text: "vcvtt.f64.f16 d3, s1" + mnemonic: "vcvtt.f64.f16" + op_str: "d3, s1" + details: + groups: [ HasFPARMv8, HasDPVFP ] + - + asm_text: "crc32b r0, r1, r2" + mnemonic: "crc32b" + op_str: "r0, r1, r2" + details: + groups: [ IsARM, HasV8, HasCRC ] + - + asm_text: "dmb oshld" + mnemonic: "dmb" + op_str: "oshld" + details: + groups: [ IsARM, HasDB ] + - + input: + bytes: [ 0x09, 0x00, 0x38, 0xd5, 0xbf, 0x40, 0x00, 0xd5, 0x0c, 0x05, 0x13, 0xd5, 0x20, 0x50, 0x02, 0x0e, 0x20, 0xe4, 0x3d, 0x0f, 0x00, 0x18, 0xa0, 0x5f, 0xa2, 0x00, 0xae, 0x9e, 0x9f, 0x37, 0x03, 0xd5, 0xbf, 0x33, 0x03, 0xd5, 0xdf, 0x3f, 0x03, 0xd5, 0x21, 0x7c, 0x02, 0x9b, 0x21, 0x7c, 0x00, 0x53, 0x00, 0x40, 0x21, 0x4b, 0xe1, 0x0b, 0x40, 0xb9, 0x20, 0x04, 0x81, 0xda, 0x20, 0x08, 0x02, 0x8b, 0x10, 0x5b, 0xe8, 0x3c ] + arch: "CS_ARCH_AARCH64" + options: [ CS_OPT_DETAIL, CS_MODE_ARM ] + address: 0x1000 + expected: + insns: + - + asm_text: "mrs x9, MIDR_EL1" + mnemonic: "mrs" + op_str: "x9, MIDR_EL1" + details: + regs_impl_write: [ nzcv ] + groups: [ privilege ] + - + asm_text: "msr SPSel, #0" + mnemonic: "msr" + op_str: "SPSel, #0" + details: + groups: [ privilege ] + - + asm_text: "msr DBGDTRTX_EL0, x12" + mnemonic: "msr" + op_str: "DBGDTRTX_EL0, x12" + details: + groups: [ privilege ] + - + asm_text: "tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b" + mnemonic: "tbx" + op_str: "v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b" + details: + groups: [ HasNEON ] + - + asm_text: "scvtf v0.2s, v1.2s, #3" + mnemonic: "scvtf" + op_str: "v0.2s, v1.2s, #3" + details: + groups: [ HasNEON ] + - + asm_text: "fmla s0, s0, v0.s[3]" + mnemonic: "fmla" + op_str: "s0, s0, v0.s[3]" + details: + regs_impl_read: [ fpcr ] + groups: [ HasNEON ] + - + asm_text: "fmov x2, v5.d[1]" + mnemonic: "fmov" + op_str: "x2, v5.d[1]" + details: + groups: [ HasFPARMv8 ] + - + asm_text: "dsb nsh" + mnemonic: "dsb" + op_str: "nsh" + - + asm_text: "dmb osh" + mnemonic: "dmb" + op_str: "osh" + - + asm_text: "isb" + mnemonic: "isb" + - + asm_text: "mul x1, x1, x2" + mnemonic: "mul" + op_str: "x1, x1, x2" + - + asm_text: "lsr w1, w1, #0" + mnemonic: "lsr" + op_str: "w1, w1, #0" + - + asm_text: "sub w0, w0, w1, uxtw" + mnemonic: "sub" + op_str: "w0, w0, w1, uxtw" + - + asm_text: "ldr w1, [sp, #8]" + mnemonic: "ldr" + op_str: "w1, [sp, #8]" + - + asm_text: "cneg x0, x1, ne" + mnemonic: "cneg" + op_str: "x0, x1, ne" + details: + regs_impl_read: [ nzcv ] + - + asm_text: "add x0, x1, x2, lsl #2" + mnemonic: "add" + op_str: "x0, x1, x2, lsl #2" + - + asm_text: "ldr q16, [x24, w8, uxtw #4]" + mnemonic: "ldr" + op_str: "q16, [x24, w8, uxtw #4]" + details: + groups: [ HasFPARMv8 ] + - + input: + bytes: [ 0x0c, 0x10, 0x00, 0x97, 0x00, 0x00, 0x00, 0x00, 0x24, 0x02, 0x00, 0x0c, 0x8f, 0xa2, 0x00, 0x00, 0x34, 0x21, 0x34, 0x56, 0x00, 0x80, 0x04, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ CS_OPT_DETAIL, CS_MODE_MIPS32, CS_MODE_BIG_ENDIAN ] + address: 0x1000 + expected: + insns: + - + asm_text: "jal 0x40025c" + mnemonic: "jal" + op_str: "0x40025c" + details: + regs_impl_write: [ ra ] + groups: [ stdenc ] + - + asm_text: "nop" + mnemonic: "nop" + details: + groups: [ stdenc, notinmicromips ] + - + asm_text: "addiu $v0, $zero, 0xc" + mnemonic: "addiu" + op_str: "$v0, $zero, 0xc" + details: + groups: [ stdenc, notinmicromips ] + - + asm_text: "lw $v0, ($sp)" + mnemonic: "lw" + op_str: "$v0, ($sp)" + details: + groups: [ stdenc, notinmicromips ] + - + asm_text: "ori $at, $at, 0x3456" + mnemonic: "ori" + op_str: "$at, $at, 0x3456" + details: + groups: [ stdenc ] + - + asm_text: "jr.hb $a0" + mnemonic: "jr.hb" + op_str: "$a0" + details: + groups: [ stdenc, mips32, notmips32r6, notmips64r6, jump ] + - + input: + bytes: [ 0x56, 0x34, 0x21, 0x34, 0xc2, 0x17, 0x01, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ CS_OPT_DETAIL, CS_MODE_MIPS64, CS_MODE_LITTLE_ENDIAN ] + address: 0x1000 + expected: + insns: + - + asm_text: "ori $at, $at, 0x3456" + mnemonic: "ori" + op_str: "$at, $at, 0x3456" + details: + groups: [ stdenc ] + - + asm_text: "srl $v0, $at, 0x1f" + mnemonic: "srl" + op_str: "$v0, $at, 0x1f" + details: + groups: [ stdenc, notinmicromips ] + - + input: + bytes: [ 0x00, 0x07, 0x00, 0x07, 0x00, 0x11, 0x93, 0x7c, 0x01, 0x8c, 0x8b, 0x7c, 0x00, 0xc7, 0x48, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R6, CS_MODE_MICRO, CS_MODE_BIG_ENDIAN ] + address: 0x1000 + expected: + insns: + - + asm_text: "break 7, 0" + mnemonic: "break" + op_str: "7, 0" + details: + groups: [ micromips ] + - + asm_text: "wait 0x11" + mnemonic: "wait" + op_str: "0x11" + details: + groups: [ micromips ] + - + asm_text: "syscall 0x18c" + mnemonic: "syscall" + op_str: "0x18c" + details: + groups: [ micromips, int ] + - + asm_text: "rotrv $t1, $a2, $a3" + mnemonic: "rotrv" + op_str: "$t1, $a2, $a3" + details: + groups: [ micromips ] + - + input: + bytes: [ 0xec, 0x80, 0x00, 0x19, 0x7c, 0x43, 0x22, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R6, CS_MODE_BIG_ENDIAN ] + address: 0x1000 + expected: + insns: + - + asm_text: "addiupc $a0, 0x64" + mnemonic: "addiupc" + op_str: "$a0, 0x64" + details: + groups: [ stdenc, mips32r6 ] + - + asm_text: "align $a0, $v0, $v1, 2" + mnemonic: "align" + op_str: "$a0, $v0, $v1, 2" + details: + groups: [ stdenc, mips32r6 ] + - + input: + bytes: [ 0x80, 0x20, 0x00, 0x00, 0x80, 0x3f, 0x00, 0x00, 0x10, 0x43, 0x23, 0x0e, 0xd0, 0x44, 0x00, 0x80, 0x4c, 0x43, 0x22, 0x02, 0x2d, 0x03, 0x00, 0x80, 0x7c, 0x43, 0x20, 0x14, 0x7c, 0x43, 0x20, 0x93, 0x4f, 0x20, 0x00, 0x21, 0x4c, 0xc8, 0x00, 0x21, 0x40, 0x82, 0x00, 0x14 ] + arch: "CS_ARCH_PPC" + options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ] + address: 0x1000 + expected: + insns: + - + asm_text: "lwz r1, 0(0)" + mnemonic: "lwz" + op_str: "r1, 0(0)" + - + asm_text: "lwz r1, 0(r31)" + mnemonic: "lwz" + op_str: "r1, 0(r31)" + - + asm_text: "vpkpx v2, v3, v4" + mnemonic: "vpkpx" + op_str: "v2, v3, v4" + - + asm_text: "stfs f2, 0x80(r4)" + mnemonic: "stfs" + op_str: "f2, 0x80(r4)" + details: + groups: [ HasFPU ] + - + asm_text: "crand eq, un, 4*cr1+lt" + mnemonic: "crand" + op_str: "eq, un, 4*cr1+lt" + - + asm_text: "cmpwi cr2, r3, 0x80" + mnemonic: "cmpwi" + op_str: "cr2, r3, 0x80" + - + asm_text: "addc r2, r3, r4" + mnemonic: "addc" + op_str: "r2, r3, r4" + details: + regs_impl_write: [ xer ] + - + asm_text: "mulhd. r2, r3, r4" + mnemonic: "mulhd." + op_str: "r2, r3, r4" + details: + regs_impl_write: [ cr0 ] + - + asm_text: "bdnzlrl+" + mnemonic: "bdnzlrl+" + details: + regs_impl_read: [ "ctr", "lr", "**ROUNDING MODE**" ] + regs_impl_write: [ lr, ctr ] + groups: [ jump ] + - + asm_text: "bflrl- 4*cr2+lt" + mnemonic: "bflrl-" + op_str: "4*cr2+lt" + details: + regs_impl_read: [ "ctr", "lr", "**ROUNDING MODE**" ] + regs_impl_write: [ lr, ctr ] + groups: [ jump ] + - + asm_text: "bf eq, 0x103c" + mnemonic: "bf" + op_str: "eq, 0x103c" + details: + regs_impl_read: [ "ctr", "**ROUNDING MODE**" ] + regs_impl_write: [ ctr ] + groups: [ jump, branch_relative ] + - + input: + bytes: [ 0x10, 0x60, 0x2a, 0x10, 0x10, 0x64, 0x28, 0x88, 0x7c, 0x4a, 0x5d, 0x0f ] + arch: "CS_ARCH_PPC" + options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_QPX ] + address: 0x1000 + expected: + insns: + - + asm_text: "qvfabs q3, q5" + mnemonic: "qvfabs" + op_str: "q3, q5" + details: + regs_impl_read: [ "**ROUNDING MODE**" ] + groups: [ HasQPX ] + - + asm_text: "qvfand q3, q4, q5" + mnemonic: "qvfand" + op_str: "q3, q4, q5" + details: + regs_impl_read: [ "**ROUNDING MODE**" ] + groups: [ HasQPX ] + - + asm_text: "qvstfsxa q2, r10, r11" + mnemonic: "qvstfsxa" + op_str: "q2, r10, r11" + details: + regs_impl_read: [ "**ROUNDING MODE**" ] + groups: [ HasQPX ] + - + input: + bytes: [ 0x80, 0xa0, 0x40, 0x02, 0x85, 0xc2, 0x60, 0x08, 0x85, 0xe8, 0x20, 0x01, 0x81, 0xe8, 0x00, 0x00, 0x90, 0x10, 0x20, 0x01, 0xd5, 0xf6, 0x10, 0x16, 0x21, 0x00, 0x00, 0x0a, 0x86, 0x00, 0x40, 0x02, 0x01, 0x00, 0x00, 0x00, 0x12, 0xbf, 0xff, 0xff, 0x10, 0xbf, 0xff, 0xff, 0xa0, 0x02, 0x00, 0x09, 0x0d, 0xbf, 0xff, 0xff, 0xd4, 0x20, 0x60, 0x00, 0xd4, 0x4e, 0x00, 0x16, 0x2a, 0xc2, 0x80, 0x03 ] + arch: "CS_ARCH_SPARC" + options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ] + address: 0x1000 + expected: + insns: + - + asm_text: "cmp %g1, %g2" + mnemonic: "cmp" + op_str: "%g1, %g2" + details: + regs_impl_write: [ icc ] + - + asm_text: "jmpl %o1+8, %g2" + mnemonic: "jmpl" + op_str: "%o1+8, %g2" + - + asm_text: "restore %g0, 1, %g2" + mnemonic: "restore" + op_str: "%g0, 1, %g2" + - + asm_text: "restore" + mnemonic: "restore" + - + asm_text: "mov 1, %o0" + mnemonic: "mov" + op_str: "1, %o0" + - + asm_text: "casx [%i0], %l6, %o2" + mnemonic: "casx" + op_str: "[%i0], %l6, %o2" + details: + groups: [ 64bit ] + - + asm_text: "sethi 0xa, %l0" + mnemonic: "sethi" + op_str: "0xa, %l0" + - + asm_text: "add %g1, %g2, %g3" + mnemonic: "add" + op_str: "%g1, %g2, %g3" + - + asm_text: "nop" + mnemonic: "nop" + - + asm_text: "bne 0x1020" + mnemonic: "bne" + op_str: "0x1020" + details: + regs_impl_read: [ icc ] + groups: [ jump ] + - + asm_text: "ba 0x1024" + mnemonic: "ba" + op_str: "0x1024" + details: + groups: [ jump ] + - + asm_text: "add %o0, %o1, %l0" + mnemonic: "add" + op_str: "%o0, %o1, %l0" + - + asm_text: "fbg 0x102c" + mnemonic: "fbg" + op_str: "0x102c" + details: + regs_impl_read: [ fcc0 ] + groups: [ jump ] + - + asm_text: "st %o2, [%g1]" + mnemonic: "st" + op_str: "%o2, [%g1]" + - + asm_text: "ldsb [%i0+%l6], %o2" + mnemonic: "ldsb" + op_str: "[%i0+%l6], %o2" + - + asm_text: "brnz,a,pn %o2, 0x1048" + mnemonic: "brnz,a,pn" + op_str: "%o2, 0x1048" + details: + groups: [ 64bit, jump ] + - + input: + bytes: [ 0x81, 0xa8, 0x0a, 0x24, 0x89, 0xa0, 0x10, 0x20, 0x89, 0xa0, 0x1a, 0x60, 0x89, 0xa0, 0x00, 0xe0 ] + arch: "CS_ARCH_SPARC" + options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ] + address: 0x1000 + expected: + insns: + - + asm_text: "fcmps %f0, %f4" + mnemonic: "fcmps" + op_str: "%f0, %f4" + - + asm_text: "fstox %f0, %f4" + mnemonic: "fstox" + op_str: "%f0, %f4" + details: + groups: [ 64bit ] + - + asm_text: "fqtoi %f0, %f4" + mnemonic: "fqtoi" + op_str: "%f0, %f4" + details: + groups: [ hardquad ] + - + asm_text: "fnegq %f0, %f4" + mnemonic: "fnegq" + op_str: "%f0, %f4" + details: + groups: [ v9 ] + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x5a, 0x0f, 0x1f, 0xff, 0xc2, 0x09, 0x80, 0x00, 0x00, 0x00, 0x07, 0xf7, 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x57, 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x57, 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x24, 0xb2, 0x4f, 0x00, 0x78 ] + arch: "CS_ARCH_SYSZ" + options: [ CS_OPT_DETAIL ] + address: 0x1000 + expected: + insns: + - + asm_text: "adb %f0, 0" + mnemonic: "adb" + op_str: "%f0, 0" + details: + regs_impl_write: [ cc ] + - + asm_text: "a %r0, 0xfff(%r15, %r1)" + mnemonic: "a" + op_str: "%r0, 0xfff(%r15, %r1)" + details: + regs_impl_write: [ cc ] + - + asm_text: "afi %r0, -0x80000000" + mnemonic: "afi" + op_str: "%r0, -0x80000000" + details: + regs_impl_write: [ cc ] + - + asm_text: "br %r7" + mnemonic: "br" + op_str: "%r7" + details: + groups: [ jump ] + - + asm_text: "xiy 0x7ffff(%r15), 0x2a" + mnemonic: "xiy" + op_str: "0x7ffff(%r15), 0x2a" + details: + regs_impl_write: [ cc ] + - + asm_text: "xy %r0, 0x7ffff(%r1, %r15)" + mnemonic: "xy" + op_str: "%r0, 0x7ffff(%r1, %r15)" + details: + regs_impl_write: [ cc ] + - + asm_text: "stmg %r0, %r0, 0(%r15)" + mnemonic: "stmg" + op_str: "%r0, %r0, 0(%r15)" + - + asm_text: "ear %r7, %a8" + mnemonic: "ear" + op_str: "%r7, %a8" + - + input: + bytes: [ 0xfe, 0x0f, 0xfe, 0x17, 0x13, 0x17, 0xc6, 0xfe, 0xec, 0x17, 0x97, 0xf8, 0xec, 0x4f, 0x1f, 0xfd, 0xec, 0x37, 0x07, 0xf2, 0x45, 0x5b, 0xf9, 0xfa, 0x02, 0x06, 0x1b, 0x10 ] + arch: "CS_ARCH_XCORE" + options: [ CS_OPT_DETAIL] + address: 0x1000 + expected: + insns: + - + asm_text: "get r11, ed" + mnemonic: "get" + op_str: "r11, ed" + details: + regs_impl_write: [ r11 ] + - + asm_text: "ldw et, sp[4]" + mnemonic: "ldw" + op_str: "et, sp[4]" + details: + regs_impl_read: [ sp ] + - + asm_text: "setd res[r3], r4" + mnemonic: "setd" + op_str: "res[r3], r4" + - + asm_text: "init t[r2]:lr, r1" + mnemonic: "init" + op_str: "t[r2]:lr, r1" + - + asm_text: "divu r9, r1, r3" + mnemonic: "divu" + op_str: "r9, r1, r3" + - + asm_text: "lda16 r9, r3[-r11]" + mnemonic: "lda16" + op_str: "r9, r3[-r11]" + - + asm_text: "ldw dp, dp[0x81c5]" + mnemonic: "ldw" + op_str: "dp, dp[0x81c5]" + - + asm_text: "lmul r11, r0, r2, r5, r8, r10" + mnemonic: "lmul" + op_str: "r11, r0, r2, r5, r8, r10" + - + asm_text: "add r1, r2, r3" + mnemonic: "add" + op_str: "r1, r2, r3" + - + input: + bytes: [ 0xd4, 0x40, 0x87, 0x5a, 0x4e, 0x71, 0x02, 0xb4, 0xc0, 0xde, 0xc0, 0xde, 0x5c, 0x00, 0x1d, 0x80, 0x71, 0x12, 0x01, 0x23, 0xf2, 0x3c, 0x44, 0x22, 0x40, 0x49, 0x0e, 0x56, 0x54, 0xc5, 0xf2, 0x3c, 0x44, 0x00, 0x44, 0x7a, 0x00, 0x00, 0xf2, 0x00, 0x0a, 0x28, 0x4e, 0xb9, 0x00, 0x00, 0x00, 0x12, 0x4e, 0x75 ] + arch: "CS_ARCH_M68K" + options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + address: 0x1000 + expected: + insns: + - + asm_text: "add.w d0, d2" + mnemonic: "add.w" + op_str: "d0, d2" + details: + regs_impl_read: [ d0 ] + regs_impl_write: [ d2 ] + - + asm_text: "or.w d3, (a2)+" + mnemonic: "or.w" + op_str: "d3, (a2)+" + details: + regs_impl_read: [ d3 ] + regs_impl_write: [ a2 ] + - + asm_text: "nop" + mnemonic: "nop" + - + asm_text: "andi.l #$c0dec0de, (a4, d5.l * 4)" + mnemonic: "andi.l" + op_str: "#$c0dec0de, (a4, d5.l * 4)" + details: + regs_impl_read: [ d5, a4 ] + - + asm_text: "move.b d0, ([a6, d7.w], $123)" + mnemonic: "move.b" + op_str: "d0, ([a6, d7.w], $123)" + details: + regs_impl_read: [ d0, d7, a6 ] + - + asm_text: "fadd.s #3.141500, fp0" + mnemonic: "fadd.s" + op_str: "#3.141500, fp0" + details: + regs_impl_write: [ fp0 ] + - + asm_text: "scc.b d5" + mnemonic: "scc.b" + op_str: "d5" + details: + regs_impl_write: [ d5 ] + - + asm_text: "fmove.s #1000.000000, fp0" + mnemonic: "fmove.s" + op_str: "#1000.000000, fp0" + details: + regs_impl_write: [ fp0 ] + - + asm_text: "fsub fp2, fp4" + mnemonic: "fsub" + op_str: "fp2, fp4" + details: + regs_impl_read: [ fp2 ] + regs_impl_write: [ fp4 ] + - + asm_text: "jsr $12.l" + mnemonic: "jsr" + op_str: "$12.l" + details: + groups: [ jump ] + - + asm_text: "rts" + mnemonic: "rts" + details: + groups: [ ret ] + - + input: + bytes: [ 0x06, 0x10, 0x19, 0x1a, 0x55, 0x1e, 0x01, 0x23, 0xe9, 0x31, 0x06, 0x34, 0x55, 0xa6, 0x81, 0xa7, 0x89, 0x7f, 0xff, 0xa6, 0x9d, 0x10, 0x00, 0xa7, 0x91, 0xa6, 0x9f, 0x10, 0x00, 0x11, 0xac, 0x99, 0x10, 0x00, 0x39 ] + arch: "CS_ARCH_M680X" + options: [ CS_OPT_DETAIL, CS_MODE_M680X_6809 ] + address: 0x1000 + expected: + insns: + - + asm_text: "ror $10" + mnemonic: "ror" + op_str: "$10" + details: + regs_impl_read: [ cc ] + regs_impl_write: [ cc ] + - + asm_text: "daa" + mnemonic: "daa" + details: + regs_impl_read: [ cc, a ] + regs_impl_write: [ cc, a ] + - + asm_text: "orcc #85" + mnemonic: "orcc" + op_str: "#85" + details: + regs_impl_read: [ cc ] + regs_impl_write: [ cc ] + - + asm_text: "exg d, x" + mnemonic: "exg" + op_str: "d, x" + details: + regs_impl_read: [ d, x ] + regs_impl_write: [ d, x ] + - + asm_text: "bls $0ff2" + mnemonic: "bls" + op_str: "$0ff2" + details: + regs_impl_read: [ cc ] + groups: [ branch_relative, jump ] + - + asm_text: "leay 6, x" + mnemonic: "leay" + op_str: "6, x" + details: + regs_impl_read: [ cc, x ] + regs_impl_write: [ cc, y ] + - + asm_text: "pshs cc, b, x, u" + mnemonic: "pshs" + op_str: "cc, b, x, u" + details: + regs_impl_read: [ s, cc, b, x, u ] + regs_impl_write: [ s ] + - + asm_text: "lda , x++" + mnemonic: "lda" + op_str: ", x++" + details: + regs_impl_read: [ cc, x ] + regs_impl_write: [ cc, a, x ] + - + asm_text: "sta 32767, x" + mnemonic: "sta" + op_str: "32767, x" + details: + regs_impl_read: [ cc, a, x ] + regs_impl_write: [ cc ] + - + asm_text: "lda [$2017, pcr]" + mnemonic: "lda" + op_str: "[$2017, pcr]" + details: + regs_impl_read: [ cc, pc ] + regs_impl_write: [ cc, a ] + - + asm_text: "sta [, x++]" + mnemonic: "sta" + op_str: "[, x++]" + details: + regs_impl_read: [ cc, a, x ] + regs_impl_write: [ cc, x ] + - + asm_text: "lda [$1000]" + mnemonic: "lda" + op_str: "[$1000]" + details: + regs_impl_read: [ cc ] + regs_impl_write: [ cc, a ] + - + asm_text: "cmps [4096, x]" + mnemonic: "cmps" + op_str: "[4096, x]" + details: + regs_impl_read: [ cc, s, x ] + regs_impl_write: [ cc ] + - + asm_text: "rts" + mnemonic: "rts" + details: + regs_impl_read: [ s ] + regs_impl_write: [ s, pc ] + groups: [ return ] + - + input: + bytes: [ 0x0a, 0x00, 0xfe, 0x34, 0x12, 0xd0, 0xff, 0xea, 0x19, 0x56, 0x34, 0x46, 0x80 ] + arch: "CS_ARCH_MOS65XX" + options: [ CS_OPT_DETAIL] + address: 0x1000 + expected: + insns: + - + asm_text: asl a + mnemonic: asl + op_str: a + details: + regs_impl_read: [ A ] + regs_impl_write: [ A, P ] + - + asm_text: brk 0xfe + mnemonic: brk + op_str: "0xfe" + details: + groups: [ int ] + - + input: + bytes: [ 0x97, 0x09, 0x00, 0x00, 0x37, 0x13, 0x03, 0x00, 0xdc, 0x02, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xdb, 0x3a, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x84, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6d, 0x33, 0x17, 0x02, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_BPF" + options: [ CS_OPT_DETAIL, CS_MODE_LITTLE_ENDIAN, CS_MODE_BPF_EXTENDED ] + address: 0x1000 + expected: + insns: + - + asm_text: "mod64 r9, 0x31337" + mnemonic: mod64 + op_str: "r9, 0x31337" + details: + groups: [ alu ] + - + asm_text: "be32 r2" + mnemonic: be32 + op_str: "r2" + details: + groups: [ alu ] + - + asm_text: "ldb [0x0]" + mnemonic: ldb + op_str: "[0x0]" + details: + regs_write: [ r0 ] + groups: [ load ] + - + asm_text: "xadddw [r10+0x100], r3" + mnemonic: xadddw + op_str: "[r10+0x100], r3" + details: + groups: [ store ] + - + asm_text: "neg r2" + mnemonic: neg + op_str: "r2" + details: + groups: [ alu ] + - + asm_text: "jsgt r3, r3, +0x217" + mnemonic: jsgt + op_str: "r3, r3, +0x217" + details: + groups: [ jump ] + - + input: + bytes: [ 0x02, 0x00, 0xbb, 0x27, 0x50, 0x7a, 0xbd, 0x23, 0xd0, 0xff, 0xde, 0x23, 0x00, 0x00, 0x5e, 0xb7 ] + arch: "CS_ARCH_ALPHA" + options: [ CS_OPT_DETAIL, CS_MODE_LITTLE_ENDIAN ] + address: 0x1000 + expected: + insns: + - + asm_text: "ldah $15,2($13)" + mnemonic: "ldah" + op_str: "$15,2($13)" + details: + regs_impl_write: [ $28 ] + - + asm_text: "lda $15,0x7a50($15)" + mnemonic: "lda" + op_str: "$15,0x7a50($15)" + details: + regs_impl_write: [ $28 ] + - + asm_text: "lda $30,0xffd0($30)" + mnemonic: "lda" + op_str: "$30,0xffd0($30)" + details: + regs_impl_write: [ $28 ] + - + asm_text: "stq $12,0($30)" + mnemonic: "stq" + op_str: "$12,0($30)" + details: + regs_impl_write: [ $28 ] + + - + input: + bytes: [ 0x27, 0xbb, 0x00, 0x02, 0x23, 0xbd, 0x7a, 0x50, 0x23, 0xde, 0xff, 0xd0, 0xb7, 0x5e, 0x00, 0x00 ] + arch: "CS_ARCH_ALPHA" + options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ] + address: 0x1000 + expected: + insns: + - + asm_text: "ldah $15,2($13)" + mnemonic: "ldah" + op_str: "$15,2($13)" + details: + regs_impl_write: [ $28 ] + - + asm_text: "lda $15,0x7a50($15)" + mnemonic: "lda" + op_str: "$15,0x7a50($15)" + details: + regs_impl_write: [ $28 ] + - + asm_text: "lda $30,0xffd0($30)" + mnemonic: "lda" + op_str: "$30,0xffd0($30)" + details: + regs_impl_write: [ $28 ] + - + asm_text: "stq $12,0($30)" + mnemonic: "stq" + op_str: "$12,0($30)" + details: + regs_impl_write: [ $28 ] + - + input: + bytes: [ 0x00, 0x20, 0x50, 0xa2, 0x00, 0x01, 0x58, 0x20, 0x00, 0x00, 0x44, 0xa1, 0x00, 0x41, 0x18, 0x40, 0x00, 0x20, 0x08, 0xa2, 0x01, 0x60, 0x48, 0xa1, 0x01, 0x61, 0x18, 0xc0, 0x00, 0x00, 0x14, 0xa1, 0x00, 0x0f, 0x0d, 0x61, 0x00, 0x0f, 0x0e, 0x61, 0x00, 0x01, 0x18, 0x60, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x0c, 0xa0, 0x03, 0xff, 0xc0, 0x1f, 0x00, 0x00, 0x04, 0x00, 0x00, 0x10, 0x04, 0x00, 0x04, 0x22, 0x51, 0x83, 0x04, 0x22, 0x51, 0xc3, 0x04, 0x22, 0x51, 0x83, 0x04, 0x2f, 0x71, 0x83, 0x04, 0x2f, 0x71, 0xc3, 0x04, 0x2f, 0x71, 0x83, 0x04, 0x41, 0x53, 0x43, 0x04, 0x41, 0x53, 0x63, 0x04, 0x41, 0x53, 0x03, 0x04, 0x41, 0x12, 0x00, 0x04, 0x41, 0x16, 0x00, 0x04, 0x41, 0x16, 0x20, 0x04, 0x41, 0x42, 0x00, 0x04, 0x41, 0x46, 0x00, 0x04, 0x41, 0x46, 0x20, 0x04, 0x41, 0x12, 0x40, 0x04, 0x41, 0x12, 0x60, 0x04, 0x41, 0x42, 0x40, 0x04, 0x41, 0x42, 0x60, 0x04, 0x41, 0x18, 0x00, 0x04, 0x41, 0x08, 0x00, 0x04, 0x41, 0x13, 0x80, 0x04, 0x41, 0x13, 0xa0, 0x04, 0x41, 0x52, 0x80, 0x04, 0x41, 0x52, 0xa0, 0x04, 0x5e, 0x72, 0x80, 0x04, 0x41, 0x42, 0x80, 0x04, 0x41, 0x52, 0xc0, 0x04, 0x41, 0x52, 0xe0, 0x04, 0x41, 0x42, 0xc0, 0x04, 0x41, 0x42, 0xe0, 0x14, 0x00, 0xde, 0xad ] + arch: "CS_ARCH_HPPA" + options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_HPPA_20 ] + address: 0x1000 + expected: + insns: + - + asm_text: "ldsid (sr1,r1),rp" + mnemonic: "ldsid" + op_str: "(sr1,r1),rp" + details: + groups: [ system_control ] + - + asm_text: "mtsp r1,sr1" + mnemonic: "mtsp" + op_str: "r1,sr1" + details: + groups: [ system_control ] + - + asm_text: "mfsp sr1,r1" + mnemonic: "mfsp" + op_str: "sr1,r1" + details: + groups: [ system_control ] + - + asm_text: "mtctl r1,cr2" + mnemonic: "mtctl" + op_str: "r1,cr2" + details: + groups: [ system_control ] + - + asm_text: "mfctl cr1,rp" + mnemonic: "mfctl" + op_str: "cr1,rp" + details: + groups: [ system_control ] + - + asm_text: "mfctl,w sar,r1" + mnemonic: "mfctl,w" + op_str: "sar,r1" + details: + groups: [ system_control ] + - + asm_text: "mtsarcm r1" + mnemonic: "mtsarcm" + op_str: "r1" + details: + groups: [ system_control ] + - + asm_text: "mfia r1" + mnemonic: "mfia" + op_str: "r1" + details: + groups: [ system_control ] + - + asm_text: "ssm 0xf,r1" + mnemonic: "ssm" + op_str: "0xf,r1" + details: + groups: [ system_control ] + - + asm_text: "rsm 0xf,r1" + mnemonic: "rsm" + op_str: "0xf,r1" + details: + groups: [ system_control ] + - + asm_text: "mtsm r1" + mnemonic: "mtsm" + op_str: "r1" + details: + groups: [ system_control ] + - + asm_text: "rfi" + mnemonic: "rfi" + details: + groups: [ system_control ] + - + asm_text: "rfi,r" + mnemonic: "rfi,r" + details: + regs_impl_write: [ r1, r8, r9, r16, r17, r24, r25 ] + groups: [ system_control ] + - + asm_text: "break 0x1f,0x1ffe" + mnemonic: "break" + op_str: "0x1f,0x1ffe" + details: + groups: [ system_control ] + - + asm_text: "sync" + mnemonic: "sync" + details: + groups: [ system_control ] + - + asm_text: "syncdma" + mnemonic: "syncdma" + details: + groups: [ system_control ] + - + asm_text: "probe,r (sr1,r1),rp,r3" + mnemonic: "probe,r" + op_str: "(sr1,r1),rp,r3" + details: + groups: [ system_control ] + - + asm_text: "probe,w (sr1,r1),rp,r3" + mnemonic: "probe,w" + op_str: "(sr1,r1),rp,r3" + details: + groups: [ system_control ] + - + asm_text: "probe,r (sr1,r1),rp,r3" + mnemonic: "probe,r" + op_str: "(sr1,r1),rp,r3" + details: + groups: [ system_control ] + - + asm_text: "probei,r (sr1,r1),0xf,r3" + mnemonic: "probei,r" + op_str: "(sr1,r1),0xf,r3" + details: + groups: [ system_control ] + - + asm_text: "probei,w (sr1,r1),0xf,r3" + mnemonic: "probei,w" + op_str: "(sr1,r1),0xf,r3" + details: + groups: [ system_control ] + - + asm_text: "probei,r (sr1,r1),0xf,r3" + mnemonic: "probei,r" + op_str: "(sr1,r1),0xf,r3" + details: + groups: [ system_control ] + - + asm_text: "lpa r1(sr1,rp),r3" + mnemonic: "lpa" + op_str: "r1(sr1,rp),r3" + details: + groups: [ system_control ] + - + asm_text: "lpa,m r1(sr1,rp),r3" + mnemonic: "lpa,m" + op_str: "r1(sr1,rp),r3" + details: + groups: [ system_control ] + - + asm_text: "lci r1(sr1,rp),r3" + mnemonic: "lci" + op_str: "r1(sr1,rp),r3" + details: + groups: [ system_control ] + - + asm_text: "pdtlb r1(rp)" + mnemonic: "pdtlb" + op_str: "r1(rp)" + details: + groups: [ system_control ] + - + asm_text: "pdtlb,l r1(rp)" + mnemonic: "pdtlb,l" + op_str: "r1(rp)" + details: + groups: [ system_control ] + - + asm_text: "pdtlb,l,m r1(rp)" + mnemonic: "pdtlb,l,m" + op_str: "r1(rp)" + details: + groups: [ system_control ] + - + asm_text: "pitlb r1(sr1,rp)" + mnemonic: "pitlb" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "pitlb,l r1(sr1,rp)" + mnemonic: "pitlb,l" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "pitlb,l,m r1(sr1,rp)" + mnemonic: "pitlb,l,m" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "pdtlbe r1(rp)" + mnemonic: "pdtlbe" + op_str: "r1(rp)" + details: + groups: [ system_control ] + - + asm_text: "pdtlbe,m r1(rp)" + mnemonic: "pdtlbe,m" + op_str: "r1(rp)" + details: + groups: [ system_control ] + - + asm_text: "pitlbe r1(sr1,rp)" + mnemonic: "pitlbe" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "pitlbe,m r1(sr1,rp)" + mnemonic: "pitlbe,m" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "idtlbt r1,rp" + mnemonic: "idtlbt" + op_str: "r1,rp" + details: + groups: [ system_control ] + - + asm_text: "iitlbt r1,rp" + mnemonic: "iitlbt" + op_str: "r1,rp" + details: + groups: [ system_control ] + - + asm_text: "pdc r1(rp)" + mnemonic: "pdc" + op_str: "r1(rp)" + details: + groups: [ system_control ] + - + asm_text: "pdc,m r1(rp)" + mnemonic: "pdc,m" + op_str: "r1(rp)" + details: + groups: [ system_control ] + - + asm_text: "fdc r1(sr1,rp)" + mnemonic: "fdc" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "fdc,m r1(sr1,rp)" + mnemonic: "fdc,m" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "fdc 0xf(sr1,rp)" + mnemonic: "fdc" + op_str: "0xf(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "fic r1(sr1,rp)" + mnemonic: "fic" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "fdce r1(sr1,rp)" + mnemonic: "fdce" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "fdce,m r1(sr1,rp)" + mnemonic: "fdce,m" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "fice r1(sr1,rp)" + mnemonic: "fice" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "fice,m r1(sr1,rp)" + mnemonic: "fice,m" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "diag 0xdead" + mnemonic: "diag" + op_str: "0xdead" + details: + groups: [ system_control ] + - + input: + bytes: [ 0xa2, 0x50, 0x20, 0x00, 0x20, 0x58, 0x01, 0x00, 0xa1, 0x44, 0x00, 0x00, 0x40, 0x18, 0x41, 0x00, 0xa2, 0x08, 0x20, 0x00, 0xa1, 0x48, 0x60, 0x01, 0xc0, 0x18, 0x61, 0x01, 0xa1, 0x14, 0x00, 0x00, 0x61, 0x0d, 0x0f, 0x00, 0x61, 0x0e, 0x0f, 0x00, 0x60, 0x18, 0x01, 0x00, 0x00, 0x0c, 0x00, 0x00, 0xa0, 0x0c, 0x00, 0x00, 0x1f, 0xc0, 0xff, 0x03, 0x00, 0x04, 0x00, 0x00, 0x00, 0x04, 0x10, 0x00, 0x83, 0x51, 0x22, 0x04, 0xc3, 0x51, 0x22, 0x04, 0x83, 0x51, 0x22, 0x04, 0x83, 0x71, 0x2f, 0x04, 0xc3, 0x71, 0x2f, 0x04, 0x83, 0x71, 0x2f, 0x04, 0x43, 0x53, 0x41, 0x04, 0x63, 0x53, 0x41, 0x04, 0x03, 0x53, 0x41, 0x04, 0x00, 0x12, 0x41, 0x04, 0x00, 0x16, 0x41, 0x04, 0x20, 0x16, 0x41, 0x04, 0x00, 0x42, 0x41, 0x04, 0x00, 0x46, 0x41, 0x04, 0x20, 0x46, 0x41, 0x04, 0x40, 0x12, 0x41, 0x04, 0x60, 0x12, 0x41, 0x04, 0x40, 0x42, 0x41, 0x04, 0x60, 0x42, 0x41, 0x04, 0x00, 0x18, 0x41, 0x04, 0x00, 0x08, 0x41, 0x04, 0x80, 0x13, 0x41, 0x04, 0xa0, 0x13, 0x41, 0x04, 0x80, 0x52, 0x41, 0x04, 0xa0, 0x52, 0x41, 0x04, 0x80, 0x72, 0x5e, 0x04, 0x80, 0x42, 0x41, 0x04, 0xc0, 0x52, 0x41, 0x04, 0xe0, 0x52, 0x41, 0x04, 0xc0, 0x42, 0x41, 0x04, 0xe0, 0x42, 0x41, 0x04, 0xad, 0xde, 0x00, 0x14 ] + arch: "CS_ARCH_HPPA" + options: [ CS_OPT_DETAIL, CS_MODE_LITTLE_ENDIAN, CS_MODE_HPPA_20 ] + address: 0x1000 + expected: + insns: + - + asm_text: "ldsid (sr1,r1),rp" + mnemonic: "ldsid" + op_str: "(sr1,r1),rp" + details: + groups: [ system_control ] + - + asm_text: "mtsp r1,sr1" + mnemonic: "mtsp" + op_str: "r1,sr1" + details: + groups: [ system_control ] + - + asm_text: "mfsp sr1,r1" + mnemonic: "mfsp" + op_str: "sr1,r1" + details: + groups: [ system_control ] + - + asm_text: "mtctl r1,cr2" + mnemonic: "mtctl" + op_str: "r1,cr2" + details: + groups: [ system_control ] + - + asm_text: "mfctl cr1,rp" + mnemonic: "mfctl" + op_str: "cr1,rp" + details: + groups: [ system_control ] + - + asm_text: "mfctl,w sar,r1" + mnemonic: "mfctl,w" + op_str: "sar,r1" + details: + groups: [ system_control ] + - + asm_text: "mtsarcm r1" + mnemonic: "mtsarcm" + op_str: "r1" + details: + groups: [ system_control ] + - + asm_text: "mfia r1" + mnemonic: "mfia" + op_str: "r1" + details: + groups: [ system_control ] + - + asm_text: "ssm 0xf,r1" + mnemonic: "ssm" + op_str: "0xf,r1" + details: + groups: [ system_control ] + - + asm_text: "rsm 0xf,r1" + mnemonic: "rsm" + op_str: "0xf,r1" + details: + groups: [ system_control ] + - + asm_text: "mtsm r1" + mnemonic: "mtsm" + op_str: "r1" + details: + groups: [ system_control ] + - + asm_text: "rfi" + mnemonic: "rfi" + details: + groups: [ system_control ] + - + asm_text: "rfi,r" + mnemonic: "rfi,r" + details: + regs_impl_write: [ r1, r8, r9, r16, r17, r24, r25 ] + groups: [ system_control ] + - + asm_text: "break 0x1f,0x1ffe" + mnemonic: "break" + op_str: "0x1f,0x1ffe" + details: + groups: [ system_control ] + - + asm_text: "sync" + mnemonic: "sync" + details: + groups: [ system_control ] + - + asm_text: "syncdma" + mnemonic: "syncdma" + details: + groups: [ system_control ] + - + asm_text: "probe,r (sr1,r1),rp,r3" + mnemonic: "probe,r" + op_str: "(sr1,r1),rp,r3" + details: + groups: [ system_control ] + - + asm_text: "probe,w (sr1,r1),rp,r3" + mnemonic: "probe,w" + op_str: "(sr1,r1),rp,r3" + details: + groups: [ system_control ] + - + asm_text: "probe,r (sr1,r1),rp,r3" + mnemonic: "probe,r" + op_str: "(sr1,r1),rp,r3" + details: + groups: [ system_control ] + - + asm_text: "probei,r (sr1,r1),0xf,r3" + mnemonic: "probei,r" + op_str: "(sr1,r1),0xf,r3" + details: + groups: [ system_control ] + - + asm_text: "probei,w (sr1,r1),0xf,r3" + mnemonic: "probei,w" + op_str: "(sr1,r1),0xf,r3" + details: + groups: [ system_control ] + - + asm_text: "probei,r (sr1,r1),0xf,r3" + mnemonic: "probei,r" + op_str: "(sr1,r1),0xf,r3" + details: + groups: [ system_control ] + - + asm_text: "lpa r1(sr1,rp),r3" + mnemonic: "lpa" + op_str: "r1(sr1,rp),r3" + details: + groups: [ system_control ] + - + asm_text: "lpa,m r1(sr1,rp),r3" + mnemonic: "lpa,m" + op_str: "r1(sr1,rp),r3" + details: + groups: [ system_control ] + - + asm_text: "lci r1(sr1,rp),r3" + mnemonic: "lci" + op_str: "r1(sr1,rp),r3" + details: + groups: [ system_control ] + - + asm_text: "pdtlb r1(rp)" + mnemonic: "pdtlb" + op_str: "r1(rp)" + details: + groups: [ system_control ] + - + asm_text: "pdtlb,l r1(rp)" + mnemonic: "pdtlb,l" + op_str: "r1(rp)" + details: + groups: [ system_control ] + - + asm_text: "pdtlb,l,m r1(rp)" + mnemonic: "pdtlb,l,m" + op_str: "r1(rp)" + details: + groups: [ system_control ] + - + asm_text: "pitlb r1(sr1,rp)" + mnemonic: "pitlb" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "pitlb,l r1(sr1,rp)" + mnemonic: "pitlb,l" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "pitlb,l,m r1(sr1,rp)" + mnemonic: "pitlb,l,m" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "pdtlbe r1(rp)" + mnemonic: "pdtlbe" + op_str: "r1(rp)" + details: + groups: [ system_control ] + - + asm_text: "pdtlbe,m r1(rp)" + mnemonic: "pdtlbe,m" + op_str: "r1(rp)" + details: + groups: [ system_control ] + - + asm_text: "pitlbe r1(sr1,rp)" + mnemonic: "pitlbe" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "pitlbe,m r1(sr1,rp)" + mnemonic: "pitlbe,m" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "idtlbt r1,rp" + mnemonic: "idtlbt" + op_str: "r1,rp" + details: + groups: [ system_control ] + - + asm_text: "iitlbt r1,rp" + mnemonic: "iitlbt" + op_str: "r1,rp" + details: + groups: [ system_control ] + - + asm_text: "pdc r1(rp)" + mnemonic: "pdc" + op_str: "r1(rp)" + details: + groups: [ system_control ] + - + asm_text: "pdc,m r1(rp)" + mnemonic: "pdc,m" + op_str: "r1(rp)" + details: + groups: [ system_control ] + - + asm_text: "fdc r1(sr1,rp)" + mnemonic: "fdc" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "fdc,m r1(sr1,rp)" + mnemonic: "fdc,m" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "fdc 0xf(sr1,rp)" + mnemonic: "fdc" + op_str: "0xf(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "fic r1(sr1,rp)" + mnemonic: "fic" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "fdce r1(sr1,rp)" + mnemonic: "fdce" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "fdce,m r1(sr1,rp)" + mnemonic: "fdce,m" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "fice r1(sr1,rp)" + mnemonic: "fice" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "fice,m r1(sr1,rp)" + mnemonic: "fice,m" + op_str: "r1(sr1,rp)" + details: + groups: [ system_control ] + - + asm_text: "diag 0xdead" + mnemonic: "diag" + op_str: "0xdead" + details: + groups: [ system_control ] + - + input: + bytes: [ 0x24, 0x41, 0x40, 0xc3, 0x24, 0x41, 0x60, 0xc3, 0x24, 0x41, 0x40, 0xe3, 0x24, 0x41, 0x60, 0xe3, 0x24, 0x41, 0x68, 0xe3, 0x2c, 0x41, 0x40, 0xc3, 0x2c, 0x41, 0x60, 0xc3, 0x2c, 0x41, 0x40, 0xe3, 0x2c, 0x41, 0x60, 0xe3, 0x2c, 0x41, 0x68, 0xe3, 0x24, 0x62, 0x42, 0xc1, 0x24, 0x62, 0x62, 0xc1, 0x24, 0x62, 0x42, 0xe1, 0x24, 0x62, 0x46, 0xe1, 0x24, 0x62, 0x62, 0xe1, 0x24, 0x62, 0x6a, 0xe1, 0x2c, 0x62, 0x42, 0xc1, 0x2c, 0x62, 0x62, 0xc1, 0x2c, 0x62, 0x42, 0xe1, 0x2c, 0x62, 0x46, 0xe1, 0x2c, 0x62, 0x62, 0xe1, 0x2c, 0x62, 0x6a, 0xe1, 0x24, 0x3e, 0x50, 0xc2, 0x24, 0x3e, 0x50, 0xe2, 0x24, 0x3e, 0x70, 0xe2, 0x24, 0x3e, 0x78, 0xe2, 0x2c, 0x3e, 0x50, 0xc2, 0x2c, 0x3e, 0x50, 0xe2, 0x2c, 0x3e, 0x70, 0xe2, 0x2c, 0x3e, 0x78, 0xe2, 0x24, 0x5e, 0x52, 0xc1, 0x24, 0x5e, 0x52, 0xe1, 0x24, 0x5e, 0x56, 0xe1, 0x24, 0x5e, 0x72, 0xe1, 0x24, 0x5e, 0x7a, 0xe1, 0x2c, 0x5e, 0x52, 0xc1, 0x2c, 0x5e, 0x52, 0xe1, 0x2c, 0x5e, 0x56, 0xe1, 0x2c, 0x5e, 0x72, 0xe1, 0x2c, 0x5e, 0x7a, 0xe1 ] + arch: "CS_ARCH_HPPA" + options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_HPPA_11 ] + address: 0x1000 + expected: + insns: + - + asm_text: "cldwx,3 r1(sr1,rp),r3" + mnemonic: "cldwx,3" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "cldwx,3,s r1(sr1,rp),r3" + mnemonic: "cldwx,3,s" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "cldwx,3,m r1(sr1,rp),r3" + mnemonic: "cldwx,3,m" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "cldwx,3,sm r1(sr1,rp),r3" + mnemonic: "cldwx,3,sm" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "cldwx,3,sm,sl r1(sr1,rp),r3" + mnemonic: "cldwx,3,sm,sl" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "clddx,3 r1(sr1,rp),r3" + mnemonic: "clddx,3" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "clddx,3,s r1(sr1,rp),r3" + mnemonic: "clddx,3,s" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "clddx,3,m r1(sr1,rp),r3" + mnemonic: "clddx,3,m" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "clddx,3,sm r1(sr1,rp),r3" + mnemonic: "clddx,3,sm" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "clddx,3,sm,sl r1(sr1,rp),r3" + mnemonic: "clddx,3,sm,sl" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "cstwx,3 r1,rp(sr1,r3)" + mnemonic: "cstwx,3" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstwx,3,s r1,rp(sr1,r3)" + mnemonic: "cstwx,3,s" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstwx,3,m r1,rp(sr1,r3)" + mnemonic: "cstwx,3,m" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstwx,3,m,bc r1,rp(sr1,r3)" + mnemonic: "cstwx,3,m,bc" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstwx,3,sm r1,rp(sr1,r3)" + mnemonic: "cstwx,3,sm" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstwx,3,sm,sl r1,rp(sr1,r3)" + mnemonic: "cstwx,3,sm,sl" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstdx,3 r1,rp(sr1,r3)" + mnemonic: "cstdx,3" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstdx,3,s r1,rp(sr1,r3)" + mnemonic: "cstdx,3,s" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstdx,3,m r1,rp(sr1,r3)" + mnemonic: "cstdx,3,m" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstdx,3,m,bc r1,rp(sr1,r3)" + mnemonic: "cstdx,3,m,bc" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstdx,3,sm r1,rp(sr1,r3)" + mnemonic: "cstdx,3,sm" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstdx,3,sm,sl r1,rp(sr1,r3)" + mnemonic: "cstdx,3,sm,sl" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cldws,3 0xf(sr1,r1),rp" + mnemonic: "cldws,3" + op_str: "0xf(sr1,r1),rp" + details: + groups: [ assist ] + - + asm_text: "cldws,3,ma 0xf(sr1,r1),rp" + mnemonic: "cldws,3,ma" + op_str: "0xf(sr1,r1),rp" + details: + groups: [ assist ] + - + asm_text: "cldws,3,mb 0xf(sr1,r1),rp" + mnemonic: "cldws,3,mb" + op_str: "0xf(sr1,r1),rp" + details: + groups: [ assist ] + - + asm_text: "cldws,3,mb,sl 0xf(sr1,r1),rp" + mnemonic: "cldws,3,mb,sl" + op_str: "0xf(sr1,r1),rp" + details: + groups: [ assist ] + - + asm_text: "cldds,3 0xf(sr1,r1),rp" + mnemonic: "cldds,3" + op_str: "0xf(sr1,r1),rp" + details: + groups: [ assist ] + - + asm_text: "cldds,3,ma 0xf(sr1,r1),rp" + mnemonic: "cldds,3,ma" + op_str: "0xf(sr1,r1),rp" + details: + groups: [ assist ] + - + asm_text: "cldds,3,mb 0xf(sr1,r1),rp" + mnemonic: "cldds,3,mb" + op_str: "0xf(sr1,r1),rp" + details: + groups: [ assist ] + - + asm_text: "cldds,3,mb,sl 0xf(sr1,r1),rp" + mnemonic: "cldds,3,mb,sl" + op_str: "0xf(sr1,r1),rp" + details: + groups: [ assist ] + - + asm_text: "cstws,3 r1,0xf(sr1,rp)" + mnemonic: "cstws,3" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + - + asm_text: "cstws,3,ma r1,0xf(sr1,rp)" + mnemonic: "cstws,3,ma" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + - + asm_text: "cstws,3,ma,bc r1,0xf(sr1,rp)" + mnemonic: "cstws,3,ma,bc" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + - + asm_text: "cstws,3,mb r1,0xf(sr1,rp)" + mnemonic: "cstws,3,mb" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + - + asm_text: "cstws,3,mb,sl r1,0xf(sr1,rp)" + mnemonic: "cstws,3,mb,sl" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + - + asm_text: "cstds,3 r1,0xf(sr1,rp)" + mnemonic: "cstds,3" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + - + asm_text: "cstds,3,ma r1,0xf(sr1,rp)" + mnemonic: "cstds,3,ma" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + - + asm_text: "cstds,3,ma,bc r1,0xf(sr1,rp)" + mnemonic: "cstds,3,ma,bc" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + - + asm_text: "cstds,3,mb r1,0xf(sr1,rp)" + mnemonic: "cstds,3,mb" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + - + asm_text: "cstds,3,mb,sl r1,0xf(sr1,rp)" + mnemonic: "cstds,3,mb,sl" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + - + input: + bytes: [ 0xc3, 0x40, 0x41, 0x24, 0xc3, 0x60, 0x41, 0x24, 0xe3, 0x40, 0x41, 0x24, 0xe3, 0x60, 0x41, 0x24, 0xe3, 0x68, 0x41, 0x24, 0xc3, 0x40, 0x41, 0x2c, 0xc3, 0x60, 0x41, 0x2c, 0xe3, 0x40, 0x41, 0x2c, 0xe3, 0x60, 0x41, 0x2c, 0xe3, 0x68, 0x41, 0x2c, 0xc1, 0x42, 0x62, 0x24, 0xc1, 0x62, 0x62, 0x24, 0xe1, 0x42, 0x62, 0x24, 0xe1, 0x46, 0x62, 0x24, 0xe1, 0x62, 0x62, 0x24, 0xe1, 0x6a, 0x62, 0x24, 0xc1, 0x42, 0x62, 0x2c, 0xc1, 0x62, 0x62, 0x2c, 0xe1, 0x42, 0x62, 0x2c, 0xe1, 0x46, 0x62, 0x2c, 0xe1, 0x62, 0x62, 0x2c, 0xe1, 0x6a, 0x62, 0x2c, 0xc2, 0x50, 0x3e, 0x24, 0xe2, 0x50, 0x3e, 0x24, 0xe2, 0x70, 0x3e, 0x24, 0xe2, 0x78, 0x3e, 0x24, 0xc2, 0x50, 0x3e, 0x2c, 0xe2, 0x50, 0x3e, 0x2c, 0xe2, 0x70, 0x3e, 0x2c, 0xe2, 0x78, 0x3e, 0x2c, 0xc1, 0x52, 0x5e, 0x24, 0xe1, 0x52, 0x5e, 0x24, 0xe1, 0x56, 0x5e, 0x24, 0xe1, 0x72, 0x5e, 0x24, 0xe1, 0x7a, 0x5e, 0x24, 0xc1, 0x52, 0x5e, 0x2c, 0xe1, 0x52, 0x5e, 0x2c, 0xe1, 0x56, 0x5e, 0x2c, 0xe1, 0x72, 0x5e, 0x2c, 0xe1, 0x7a, 0x5e, 0x2c ] + arch: "CS_ARCH_HPPA" + options: [ CS_OPT_DETAIL, CS_MODE_LITTLE_ENDIAN, CS_MODE_HPPA_11 ] + address: 0x1000 + expected: + insns: + - + asm_text: "cldwx,3 r1(sr1,rp),r3" + mnemonic: "cldwx,3" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "cldwx,3,s r1(sr1,rp),r3" + mnemonic: "cldwx,3,s" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "cldwx,3,m r1(sr1,rp),r3" + mnemonic: "cldwx,3,m" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "cldwx,3,sm r1(sr1,rp),r3" + mnemonic: "cldwx,3,sm" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "cldwx,3,sm,sl r1(sr1,rp),r3" + mnemonic: "cldwx,3,sm,sl" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "clddx,3 r1(sr1,rp),r3" + mnemonic: "clddx,3" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "clddx,3,s r1(sr1,rp),r3" + mnemonic: "clddx,3,s" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "clddx,3,m r1(sr1,rp),r3" + mnemonic: "clddx,3,m" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "clddx,3,sm r1(sr1,rp),r3" + mnemonic: "clddx,3,sm" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "clddx,3,sm,sl r1(sr1,rp),r3" + mnemonic: "clddx,3,sm,sl" + op_str: "r1(sr1,rp),r3" + details: + groups: [ assist ] + - + asm_text: "cstwx,3 r1,rp(sr1,r3)" + mnemonic: "cstwx,3" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstwx,3,s r1,rp(sr1,r3)" + mnemonic: "cstwx,3,s" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstwx,3,m r1,rp(sr1,r3)" + mnemonic: "cstwx,3,m" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstwx,3,m,bc r1,rp(sr1,r3)" + mnemonic: "cstwx,3,m,bc" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstwx,3,sm r1,rp(sr1,r3)" + mnemonic: "cstwx,3,sm" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstwx,3,sm,sl r1,rp(sr1,r3)" + mnemonic: "cstwx,3,sm,sl" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstdx,3 r1,rp(sr1,r3)" + mnemonic: "cstdx,3" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstdx,3,s r1,rp(sr1,r3)" + mnemonic: "cstdx,3,s" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstdx,3,m r1,rp(sr1,r3)" + mnemonic: "cstdx,3,m" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstdx,3,m,bc r1,rp(sr1,r3)" + mnemonic: "cstdx,3,m,bc" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstdx,3,sm r1,rp(sr1,r3)" + mnemonic: "cstdx,3,sm" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cstdx,3,sm,sl r1,rp(sr1,r3)" + mnemonic: "cstdx,3,sm,sl" + op_str: "r1,rp(sr1,r3)" + details: + groups: [ assist ] + - + asm_text: "cldws,3 0xf(sr1,r1),rp" + mnemonic: "cldws,3" + op_str: "0xf(sr1,r1),rp" + details: + groups: [ assist ] + - + asm_text: "cldws,3,ma 0xf(sr1,r1),rp" + mnemonic: "cldws,3,ma" + op_str: "0xf(sr1,r1),rp" + details: + groups: [ assist ] + - + asm_text: "cldws,3,mb 0xf(sr1,r1),rp" + mnemonic: "cldws,3,mb" + op_str: "0xf(sr1,r1),rp" + details: + groups: [ assist ] + - + asm_text: "cldws,3,mb,sl 0xf(sr1,r1),rp" + mnemonic: "cldws,3,mb,sl" + op_str: "0xf(sr1,r1),rp" + details: + groups: [ assist ] + - + asm_text: "cldds,3 0xf(sr1,r1),rp" + mnemonic: "cldds,3" + op_str: "0xf(sr1,r1),rp" + details: + groups: [ assist ] + - + asm_text: "cldds,3,ma 0xf(sr1,r1),rp" + mnemonic: "cldds,3,ma" + op_str: "0xf(sr1,r1),rp" + details: + groups: [ assist ] + - + asm_text: "cldds,3,mb 0xf(sr1,r1),rp" + mnemonic: "cldds,3,mb" + op_str: "0xf(sr1,r1),rp" + details: + groups: [ assist ] + - + asm_text: "cldds,3,mb,sl 0xf(sr1,r1),rp" + mnemonic: "cldds,3,mb,sl" + op_str: "0xf(sr1,r1),rp" + details: + groups: [ assist ] + - + asm_text: "cstws,3 r1,0xf(sr1,rp)" + mnemonic: "cstws,3" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + - + asm_text: "cstws,3,ma r1,0xf(sr1,rp)" + mnemonic: "cstws,3,ma" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + - + asm_text: "cstws,3,ma,bc r1,0xf(sr1,rp)" + mnemonic: "cstws,3,ma,bc" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + - + asm_text: "cstws,3,mb r1,0xf(sr1,rp)" + mnemonic: "cstws,3,mb" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + - + asm_text: "cstws,3,mb,sl r1,0xf(sr1,rp)" + mnemonic: "cstws,3,mb,sl" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + - + asm_text: "cstds,3 r1,0xf(sr1,rp)" + mnemonic: "cstds,3" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + - + asm_text: "cstds,3,ma r1,0xf(sr1,rp)" + mnemonic: "cstds,3,ma" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + - + asm_text: "cstds,3,ma,bc r1,0xf(sr1,rp)" + mnemonic: "cstds,3,ma,bc" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + - + asm_text: "cstds,3,mb r1,0xf(sr1,rp)" + mnemonic: "cstds,3,mb" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + - + asm_text: "cstds,3,mb,sl r1,0xf(sr1,rp)" + mnemonic: "cstds,3,mb,sl" + op_str: "r1,0xf(sr1,rp)" + details: + groups: [ assist ] + diff --git a/tests/details/evm.yaml b/tests/details/evm.yaml new file mode 100644 index 0000000000..6858de6d5a --- /dev/null +++ b/tests/details/evm.yaml @@ -0,0 +1,24 @@ +test_cases: + - + input: + bytes: [ 0x60, 0x61, 0x50 ] + arch: "evm" + options: [ CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "push1 61" + details: + evm: + push: 1 + fee: 3 + groups: [ EVM_GRP_STACK_WRITE ] + - + asm_text: "pop" + details: + evm: + pop: 1 + fee: 2 + groups: [ EVM_GRP_STACK_READ ] + diff --git a/tests/details/hppa.yaml b/tests/details/hppa.yaml new file mode 100644 index 0000000000..ecc7d8ad32 --- /dev/null +++ b/tests/details/hppa.yaml @@ -0,0 +1,2308 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x20, 0x50, 0xa2, 0x00, 0x01, 0x58, 0x20, 0x00, 0x00, 0x44, 0xa1, 0x00, 0x41, 0x18, 0x40, 0x00, 0x20, 0x08, 0xa2, 0x01, 0x60, 0x48, 0xa1, 0x01, 0x61, 0x18, 0xc0, 0x00, 0x00, 0x14, 0xa1, 0x00, 0x0f, 0x0d, 0x61, 0x00, 0x0f, 0x0e, 0x61, 0x00, 0x01, 0x18, 0x60, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x0c, 0xa0, 0x03, 0xff, 0xc0, 0x1f, 0x00, 0x00, 0x04, 0x00, 0x00, 0x10, 0x04, 0x00, 0x04, 0x22, 0x51, 0x83, 0x04, 0x22, 0x51, 0xc3, 0x04, 0x22, 0x51, 0x83, 0x04, 0x2f, 0x71, 0x83, 0x04, 0x2f, 0x71, 0xc3, 0x04, 0x2f, 0x71, 0x83, 0x04, 0x41, 0x53, 0x43, 0x04, 0x41, 0x53, 0x63, 0x04, 0x41, 0x53, 0x03, 0x04, 0x41, 0x12, 0x00, 0x04, 0x41, 0x16, 0x00, 0x04, 0x41, 0x16, 0x20, 0x04, 0x41, 0x42, 0x00, 0x04, 0x41, 0x46, 0x00, 0x04, 0x41, 0x46, 0x20, 0x04, 0x41, 0x12, 0x40, 0x04, 0x41, 0x12, 0x60, 0x04, 0x41, 0x42, 0x40, 0x04, 0x41, 0x42, 0x60, 0x04, 0x41, 0x18, 0x00, 0x04, 0x41, 0x08, 0x00, 0x04, 0x41, 0x13, 0x80, 0x04, 0x41, 0x13, 0xa0, 0x04, 0x41, 0x52, 0x80, 0x04, 0x41, 0x52, 0xa0, 0x04, 0x5e, 0x72, 0x80, 0x04, 0x41, 0x42, 0x80, 0x04, 0x41, 0x52, 0xc0, 0x04, 0x41, 0x52, 0xe0, 0x04, 0x41, 0x42, 0xc0, 0x04, 0x41, 0x42, 0xe0, 0x14, 0x00, 0xde, 0xad ] + arch: "hppa" + options: [ CS_MODE_BIG_ENDIAN, CS_MODE_HPPA_20, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldsid (sr1,r1),rp" + details: + hppa: + operands: + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "mtsp r1,sr1" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_REG + reg: sr1 + - + asm_text: "mfsp sr1,r1" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: sr1 + - + type: HPPA_OP_REG + reg: r1 + - + asm_text: "mtctl r1,cr2" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_REG + reg: cr2 + - + asm_text: "mfctl cr1,rp" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: cr1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "mfctl,w sar,r1" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: sar + - + type: HPPA_OP_REG + reg: r1 + - + asm_text: "mtsarcm r1" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + asm_text: "mfia r1" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + asm_text: "ssm 0xf,r1" + details: + hppa: + operands: + - + type: HPPA_OP_IMM + imm: 0xf + - + type: HPPA_OP_REG + reg: r1 + - + asm_text: "rsm 0xf,r1" + details: + hppa: + operands: + - + type: HPPA_OP_IMM + imm: 0xf + - + type: HPPA_OP_REG + reg: r1 + - + asm_text: "mtsm r1" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + asm_text: "rfi" + - + asm_text: "rfi,r" + - + asm_text: "break 0x1f,0x1ffe" + details: + hppa: + operands: + - + type: HPPA_OP_IMM + imm: 0x1f + - + type: HPPA_OP_IMM + imm: 0x1ffe + - + asm_text: "sync" + - + asm_text: "syncdma" + - + asm_text: "probe,r (sr1,r1),rp,r3" + details: + hppa: + operands: + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "probe,w (sr1,r1),rp,r3" + details: + hppa: + operands: + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "probe,r (sr1,r1),rp,r3" + details: + hppa: + operands: + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "probei,r (sr1,r1),0xf,r3" + details: + hppa: + operands: + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_IMM + imm: 0xf + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "probei,w (sr1,r1),0xf,r3" + details: + hppa: + operands: + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_IMM + imm: 0xf + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "probei,r (sr1,r1),0xf,r3" + details: + hppa: + operands: + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_IMM + imm: 0xf + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "lpa r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "lpa,m r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "lci r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "pdtlb r1(rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr0 + mem_base: rp + - + asm_text: "pdtlb,l r1(rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr0 + mem_base: rp + - + asm_text: "pdtlb,l,m r1(rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr0 + mem_base: rp + - + asm_text: "pitlb r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "pitlb,l r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "pitlb,l,m r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "pdtlbe r1(rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr0 + mem_base: rp + - + asm_text: "pdtlbe,m r1(rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr0 + mem_base: rp + - + asm_text: "pitlbe r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "pitlbe,m r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "idtlbt r1,rp" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "iitlbt r1,rp" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "pdc r1(rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr0 + mem_base: rp + - + asm_text: "pdc,m r1(rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr0 + mem_base: rp + - + asm_text: "fdc r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "fdc,m r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "fdc 0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "fic r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "fdce r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "fdce,m r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "fice r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "fice,m r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "diag 0xdead" + details: + hppa: + operands: + - + type: HPPA_OP_IMM + imm: 0xdead + - + input: + bytes: [ 0xa2, 0x50, 0x20, 0x00, 0x20, 0x58, 0x01, 0x00, 0xa1, 0x44, 0x00, 0x00, 0x40, 0x18, 0x41, 0x00, 0xa2, 0x08, 0x20, 0x00, 0xa1, 0x48, 0x60, 0x01, 0xc0, 0x18, 0x61, 0x01, 0xa1, 0x14, 0x00, 0x00, 0x61, 0x0d, 0x0f, 0x00, 0x61, 0x0e, 0x0f, 0x00, 0x60, 0x18, 0x01, 0x00, 0x00, 0x0c, 0x00, 0x00, 0xa0, 0x0c, 0x00, 0x00, 0x1f, 0xc0, 0xff, 0x03, 0x00, 0x04, 0x00, 0x00, 0x00, 0x04, 0x10, 0x00, 0x83, 0x51, 0x22, 0x04, 0xc3, 0x51, 0x22, 0x04, 0x83, 0x51, 0x22, 0x04, 0x83, 0x71, 0x2f, 0x04, 0xc3, 0x71, 0x2f, 0x04, 0x83, 0x71, 0x2f, 0x04, 0x43, 0x53, 0x41, 0x04, 0x63, 0x53, 0x41, 0x04, 0x03, 0x53, 0x41, 0x04, 0x00, 0x12, 0x41, 0x04, 0x00, 0x16, 0x41, 0x04, 0x20, 0x16, 0x41, 0x04, 0x00, 0x42, 0x41, 0x04, 0x00, 0x46, 0x41, 0x04, 0x20, 0x46, 0x41, 0x04, 0x40, 0x12, 0x41, 0x04, 0x60, 0x12, 0x41, 0x04, 0x40, 0x42, 0x41, 0x04, 0x60, 0x42, 0x41, 0x04, 0x00, 0x18, 0x41, 0x04, 0x00, 0x08, 0x41, 0x04, 0x80, 0x13, 0x41, 0x04, 0xa0, 0x13, 0x41, 0x04, 0x80, 0x52, 0x41, 0x04, 0xa0, 0x52, 0x41, 0x04, 0x80, 0x72, 0x5e, 0x04, 0x80, 0x42, 0x41, 0x04, 0xc0, 0x52, 0x41, 0x04, 0xe0, 0x52, 0x41, 0x04, 0xc0, 0x42, 0x41, 0x04, 0xe0, 0x42, 0x41, 0x04, 0xad, 0xde, 0x00, 0x14 ] + arch: "hppa" + options: [ CS_OPT_DETAIL, CS_MODE_HPPA_20 ] + address: 0x0 + expected: + insns: + - + asm_text: "ldsid (sr1,r1),rp" + details: + hppa: + operands: + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "mtsp r1,sr1" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_REG + reg: sr1 + - + asm_text: "mfsp sr1,r1" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: sr1 + - + type: HPPA_OP_REG + reg: r1 + - + asm_text: "mtctl r1,cr2" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_REG + reg: cr2 + - + asm_text: "mfctl cr1,rp" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: cr1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "mfctl,w sar,r1" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: sar + - + type: HPPA_OP_REG + reg: r1 + - + asm_text: "mtsarcm r1" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + asm_text: "mfia r1" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + asm_text: "ssm 0xf,r1" + details: + hppa: + operands: + - + type: HPPA_OP_IMM + imm: 0xf + - + type: HPPA_OP_REG + reg: r1 + - + asm_text: "rsm 0xf,r1" + details: + hppa: + operands: + - + type: HPPA_OP_IMM + imm: 0xf + - + type: HPPA_OP_REG + reg: r1 + - + asm_text: "mtsm r1" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + asm_text: "rfi" + - + asm_text: "rfi,r" + - + asm_text: "break 0x1f,0x1ffe" + details: + hppa: + operands: + - + type: HPPA_OP_IMM + imm: 0x1f + - + type: HPPA_OP_IMM + imm: 0x1ffe + - + asm_text: "sync" + - + asm_text: "syncdma" + - + asm_text: "probe,r (sr1,r1),rp,r3" + details: + hppa: + operands: + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "probe,w (sr1,r1),rp,r3" + details: + hppa: + operands: + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "probe,r (sr1,r1),rp,r3" + details: + hppa: + operands: + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "probei,r (sr1,r1),0xf,r3" + details: + hppa: + operands: + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_IMM + imm: 0xf + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "probei,w (sr1,r1),0xf,r3" + details: + hppa: + operands: + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_IMM + imm: 0xf + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "probei,r (sr1,r1),0xf,r3" + details: + hppa: + operands: + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_IMM + imm: 0xf + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "lpa r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "lpa,m r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "lci r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "pdtlb r1(rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr0 + mem_base: rp + - + asm_text: "pdtlb,l r1(rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr0 + mem_base: rp + - + asm_text: "pdtlb,l,m r1(rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr0 + mem_base: rp + - + asm_text: "pitlb r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "pitlb,l r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "pitlb,l,m r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "pdtlbe r1(rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr0 + mem_base: rp + - + asm_text: "pdtlbe,m r1(rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr0 + mem_base: rp + - + asm_text: "pitlbe r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "pitlbe,m r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "idtlbt r1,rp" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "iitlbt r1,rp" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "pdc r1(rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr0 + mem_base: rp + - + asm_text: "pdc,m r1(rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr0 + mem_base: rp + - + asm_text: "fdc r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "fdc,m r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "fdc 0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "fic r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "fdce r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "fdce,m r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "fice r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "fice,m r1(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "diag 0xdead" + details: + hppa: + operands: + - + type: HPPA_OP_IMM + imm: 0xdead + - + input: + bytes: [ 0x24, 0x41, 0x40, 0xc3, 0x24, 0x41, 0x60, 0xc3, 0x24, 0x41, 0x40, 0xe3, 0x24, 0x41, 0x60, 0xe3, 0x24, 0x41, 0x68, 0xe3, 0x2c, 0x41, 0x40, 0xc3, 0x2c, 0x41, 0x60, 0xc3, 0x2c, 0x41, 0x40, 0xe3, 0x2c, 0x41, 0x60, 0xe3, 0x2c, 0x41, 0x68, 0xe3, 0x24, 0x62, 0x42, 0xc1, 0x24, 0x62, 0x62, 0xc1, 0x24, 0x62, 0x42, 0xe1, 0x24, 0x62, 0x46, 0xe1, 0x24, 0x62, 0x62, 0xe1, 0x24, 0x62, 0x6a, 0xe1, 0x2c, 0x62, 0x42, 0xc1, 0x2c, 0x62, 0x62, 0xc1, 0x2c, 0x62, 0x42, 0xe1, 0x2c, 0x62, 0x46, 0xe1, 0x2c, 0x62, 0x62, 0xe1, 0x2c, 0x62, 0x6a, 0xe1, 0x24, 0x3e, 0x50, 0xc2, 0x24, 0x3e, 0x50, 0xe2, 0x24, 0x3e, 0x70, 0xe2, 0x24, 0x3e, 0x78, 0xe2, 0x2c, 0x3e, 0x50, 0xc2, 0x2c, 0x3e, 0x50, 0xe2, 0x2c, 0x3e, 0x70, 0xe2, 0x2c, 0x3e, 0x78, 0xe2, 0x24, 0x5e, 0x52, 0xc1, 0x24, 0x5e, 0x52, 0xe1, 0x24, 0x5e, 0x56, 0xe1, 0x24, 0x5e, 0x72, 0xe1, 0x24, 0x5e, 0x7a, 0xe1, 0x2c, 0x5e, 0x52, 0xc1, 0x2c, 0x5e, 0x52, 0xe1, 0x2c, 0x5e, 0x56, 0xe1, 0x2c, 0x5e, 0x72, 0xe1, 0x2c, 0x5e, 0x7a, 0xe1 ] + arch: "hppa" + options: [ CS_OPT_DETAIL, CS_MODE_HPPA_11, CS_MODE_BIG_ENDIAN ] + address: 0x0 + expected: + insns: + - + asm_text: "cldwx,3 r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "cldwx,3,s r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "cldwx,3,m r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "cldwx,3,sm r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "cldwx,3,sm,sl r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "clddx,3 r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "clddx,3,s r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "clddx,3,m r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "clddx,3,sm r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "clddx,3,sm,sl r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "cstwx,3 r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstwx,3,s r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstwx,3,m r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstwx,3,m,bc r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstwx,3,sm r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstwx,3,sm,sl r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstdx,3 r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstdx,3,s r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstdx,3,m r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstdx,3,m,bc r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstdx,3,sm r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstdx,3,sm,sl r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cldws,3 0xf(sr1,r1),rp" + details: + hppa: + operands: + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "cldws,3,ma 0xf(sr1,r1),rp" + details: + hppa: + operands: + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "cldws,3,mb 0xf(sr1,r1),rp" + details: + hppa: + operands: + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "cldws,3,mb,sl 0xf(sr1,r1),rp" + details: + hppa: + operands: + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "cldds,3 0xf(sr1,r1),rp" + details: + hppa: + operands: + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "cldds,3,ma 0xf(sr1,r1),rp" + details: + hppa: + operands: + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "cldds,3,mb 0xf(sr1,r1),rp" + details: + hppa: + operands: + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "cldds,3,mb,sl 0xf(sr1,r1),rp" + details: + hppa: + operands: + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "cstws,3 r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "cstws,3,ma r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "cstws,3,ma,bc r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "cstws,3,mb r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "cstws,3,mb,sl r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "cstds,3 r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "cstds,3,ma r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "cstds,3,ma,bc r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "cstds,3,mb r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "cstds,3,mb,sl r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + input: + bytes: [ 0xc3, 0x40, 0x41, 0x24, 0xc3, 0x60, 0x41, 0x24, 0xe3, 0x40, 0x41, 0x24, 0xe3, 0x60, 0x41, 0x24, 0xe3, 0x68, 0x41, 0x24, 0xc3, 0x40, 0x41, 0x2c, 0xc3, 0x60, 0x41, 0x2c, 0xe3, 0x40, 0x41, 0x2c, 0xe3, 0x60, 0x41, 0x2c, 0xe3, 0x68, 0x41, 0x2c, 0xc1, 0x42, 0x62, 0x24, 0xc1, 0x62, 0x62, 0x24, 0xe1, 0x42, 0x62, 0x24, 0xe1, 0x46, 0x62, 0x24, 0xe1, 0x62, 0x62, 0x24, 0xe1, 0x6a, 0x62, 0x24, 0xc1, 0x42, 0x62, 0x2c, 0xc1, 0x62, 0x62, 0x2c, 0xe1, 0x42, 0x62, 0x2c, 0xe1, 0x46, 0x62, 0x2c, 0xe1, 0x62, 0x62, 0x2c, 0xe1, 0x6a, 0x62, 0x2c, 0xc2, 0x50, 0x3e, 0x24, 0xe2, 0x50, 0x3e, 0x24, 0xe2, 0x70, 0x3e, 0x24, 0xe2, 0x78, 0x3e, 0x24, 0xc2, 0x50, 0x3e, 0x2c, 0xe2, 0x50, 0x3e, 0x2c, 0xe2, 0x70, 0x3e, 0x2c, 0xe2, 0x78, 0x3e, 0x2c, 0xc1, 0x52, 0x5e, 0x24, 0xe1, 0x52, 0x5e, 0x24, 0xe1, 0x56, 0x5e, 0x24, 0xe1, 0x72, 0x5e, 0x24, 0xe1, 0x7a, 0x5e, 0x24, 0xc1, 0x52, 0x5e, 0x2c, 0xe1, 0x52, 0x5e, 0x2c, 0xe1, 0x56, 0x5e, 0x2c, 0xe1, 0x72, 0x5e, 0x2c, 0xe1, 0x7a, 0x5e, 0x2c ] + arch: "hppa" + options: [ CS_OPT_DETAIL, CS_MODE_HPPA_11 ] + address: 0x0 + expected: + insns: + - + asm_text: "cldwx,3 r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "cldwx,3,s r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "cldwx,3,m r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "cldwx,3,sm r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "cldwx,3,sm,sl r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "clddx,3 r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "clddx,3,s r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "clddx,3,m r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "clddx,3,sm r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "clddx,3,sm,sl r1(sr1,rp),r3" + details: + hppa: + operands: + - + type: HPPA_OP_IDX_REG + reg: r1 + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + type: HPPA_OP_REG + reg: r3 + - + asm_text: "cstwx,3 r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstwx,3,s r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstwx,3,m r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstwx,3,m,bc r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstwx,3,sm r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstwx,3,sm,sl r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstdx,3 r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstdx,3,s r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstdx,3,m r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstdx,3,m,bc r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstdx,3,sm r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cstdx,3,sm,sl r1,rp(sr1,r3)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_IDX_REG + reg: rp + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r3 + - + asm_text: "cldws,3 0xf(sr1,r1),rp" + details: + hppa: + operands: + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "cldws,3,ma 0xf(sr1,r1),rp" + details: + hppa: + operands: + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "cldws,3,mb 0xf(sr1,r1),rp" + details: + hppa: + operands: + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "cldws,3,mb,sl 0xf(sr1,r1),rp" + details: + hppa: + operands: + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "cldds,3 0xf(sr1,r1),rp" + details: + hppa: + operands: + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "cldds,3,ma 0xf(sr1,r1),rp" + details: + hppa: + operands: + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "cldds,3,mb 0xf(sr1,r1),rp" + details: + hppa: + operands: + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "cldds,3,mb,sl 0xf(sr1,r1),rp" + details: + hppa: + operands: + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: r1 + - + type: HPPA_OP_REG + reg: rp + - + asm_text: "cstws,3 r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "cstws,3,ma r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "cstws,3,ma,bc r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "cstws,3,mb r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "cstws,3,mb,sl r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "cstds,3 r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "cstds,3,ma r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "cstds,3,ma,bc r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "cstds,3,mb r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + - + asm_text: "cstds,3,mb,sl r1,0xf(sr1,rp)" + details: + hppa: + operands: + - + type: HPPA_OP_REG + reg: r1 + - + type: HPPA_OP_DISP + imm: 0xf + - + type: HPPA_OP_MEM + mem_space: sr1 + mem_base: rp + diff --git a/tests/details/loongarch.yaml b/tests/details/loongarch.yaml new file mode 100644 index 0000000000..0fd5a79e26 --- /dev/null +++ b/tests/details/loongarch.yaml @@ -0,0 +1,107 @@ +test_cases: + - + input: + bytes: [ 0x0c, 0x00, 0x08, 0x14, 0x8c, 0xfd, 0xbf, 0x02 ] + arch: "loongarch" + options: [ CS_OPT_DETAIL, CS_MODE_LOONGARCH32 ] + address: 0x0 + expected: + insns: + - + asm_text: "lu12i.w $t0, 0x4000" + details: + loongarch: + operands: + - + type: LOONGARCH_OP_REG + reg: t0 + - + type: LOONGARCH_OP_IMM + imm: 0x4000 + - + asm_text: "addi.w $t0, $t0, -1" + details: + loongarch: + operands: + - + type: LOONGARCH_OP_REG + reg: t0 + - + type: LOONGARCH_OP_REG + reg: t0 + - + type: LOONGARCH_OP_IMM + imm: -1 + - + input: + bytes: [ 0x80, 0x80, 0x00, 0x40, 0x63, 0x80, 0xff, 0x02, 0x78, 0x20, 0xc0, 0x29, 0x00, 0x84, 0x00, 0x01, 0x00, 0xa4, 0x14, 0x01 ] + arch: "loongarch" + options: [ CS_OPT_DETAIL, CS_MODE_LOONGARCH64] + address: 0x0 + expected: + insns: + - + asm_text: "beqz $a0, 0x80" + details: + loongarch: + operands: + - + type: LOONGARCH_OP_REG + reg: a0 + - + type: LOONGARCH_OP_IMM + imm: 0x80 + groups: [ LOONGARCH_GRP_JUMP, LOONGARCH_GRP_BRANCH_RELATIVE ] + - + asm_text: "addi.d $sp, $sp, -0x20" + details: + loongarch: + operands: + - + type: LOONGARCH_OP_REG + reg: sp + - + type: LOONGARCH_OP_REG + reg: sp + - + type: LOONGARCH_OP_IMM + imm: -0x20 + groups: [ LOONGARCH_FEATURE_ISLA64 ] + - + asm_text: "st.d $s1, $sp, 8" + details: + loongarch: + operands: + - + type: LOONGARCH_OP_REG + reg: s1 + - + type: LOONGARCH_OP_MEM + mem_base: sp + mem_disp: 0x8 + groups: [ LOONGARCH_FEATURE_ISLA64 ] + - + asm_text: "fadd.s $fa0, $fa0, $fa1" + details: + loongarch: + operands: + - + type: LOONGARCH_OP_REG + reg: fa0 + - + type: LOONGARCH_OP_REG + reg: fa0 + - + type: LOONGARCH_OP_REG + reg: fa1 + - + asm_text: "movgr2fr.w $fa0, $zero" + details: + loongarch: + operands: + - + type: LOONGARCH_OP_REG + reg: fa0 + - + type: LOONGARCH_OP_REG + reg: zero diff --git a/tests/details/m680x.yaml b/tests/details/m680x.yaml new file mode 100644 index 0000000000..162231c4fc --- /dev/null +++ b/tests/details/m680x.yaml @@ -0,0 +1,3271 @@ +test_cases: + - + input: + bytes: [ 0x6b, 0x10, 0x00, 0x71, 0x10, 0x00, 0x72, 0x10, 0x10, 0x39 ] + arch: "m680x" + options: [ CS_OPT_DETAIL, CS_MODE_M680X_6301 ] + address: 0x1000 + expected: + insns: + - + asm_text: "tim #16; 0, x" + details: + m680x: + operands: + - + type: M680X_OP_IMMEDIATE + imm: 16 + size: 1 + access: CS_AC_READ + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 0 + offset_bits: 8 + size: 1 + access: CS_AC_READ + regs_read: [ cc, x ] + regs_write: [ cc ] + - + asm_text: "aim #16, $00" + details: + m680x: + operands: + - + type: M680X_OP_IMMEDIATE + imm: 16 + size: 1 + access: CS_AC_READ + - + type: M680X_OP_DIRECT + direct_addr: 0x0000 + direct_addr_set: true + size: 1 + access: CS_AC_READ_WRITE + regs_read: [ cc ] + regs_write: [ cc ] + - + asm_text: "oim #16, $10" + details: + m680x: + operands: + - + type: M680X_OP_IMMEDIATE + imm: 16 + size: 1 + access: CS_AC_READ + - + type: M680X_OP_DIRECT + direct_addr: 0x0010 + direct_addr_set: true + size: 1 + access: CS_AC_READ_WRITE + regs_read: [ cc ] + regs_write: [ cc ] + - + asm_text: "rts" + details: + regs_read: [ s ] + regs_write: [ s, pc ] + groups: [ M680X_GRP_RET ] + - + input: + bytes: [ 0x01, 0x10, 0x10, 0x62, 0x10, 0x10, 0x7b, 0x10, 0x10, 0x00, 0xcd, 0x49, 0x96, 0x02, 0xd2, 0x10, 0x30, 0x23, 0x10, 0x38, 0x10, 0x3b, 0x10, 0x53, 0x10, 0x5d, 0x11, 0x30, 0x43, 0x10, 0x11, 0x37, 0x25, 0x10, 0x11, 0x38, 0x12, 0x11, 0x39, 0x23, 0x11, 0x3b, 0x34, 0x11, 0x8e, 0x10, 0x00, 0x11, 0xaf, 0x10, 0x11, 0xab, 0x10, 0x11, 0xf6, 0x80, 0x00 ] + arch: "m680x" + options: [ CS_OPT_DETAIL, CS_MODE_M680X_6309 ] + address: 0x1000 + expected: + insns: + - + asm_text: "oim #16, $10" + details: + m680x: + operands: + - + type: M680X_OP_IMMEDIATE + imm: 16 + size: 1 + access: CS_AC_READ + - + type: M680X_OP_DIRECT + direct_addr: 0x0010 + direct_addr_set: true + size: 1 + access: CS_AC_READ_WRITE + regs_read: [ cc ] + regs_write: [ cc ] + - + asm_text: "aim #16; -16, x" + details: + m680x: + operands: + - + type: M680X_OP_IMMEDIATE + imm: 16 + size: 1 + access: CS_AC_READ + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: -16 + offset_bits: 5 + size: 1 + access: CS_AC_READ_WRITE + regs_read: [ cc, x ] + regs_write: [ cc ] + - + asm_text: "tim #16, $1000" + details: + m680x: + operands: + - + type: M680X_OP_IMMEDIATE + imm: 16 + size: 1 + access: CS_AC_READ + - + type: M680X_OP_EXTENDED + ext_address: 0x1000 + ext_indirect: -1 + size: 1 + access: CS_AC_READ + regs_read: [ cc ] + regs_write: [ cc ] + - + asm_text: "ldq #1234567890" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: q + size: 4 + access: CS_AC_WRITE + - + type: M680X_OP_IMMEDIATE + imm: 1234567890 + size: 4 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc ] + regs_write: [ cc, q ] + - + asm_text: "addr y, u" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: y + size: 2 + access: CS_AC_READ + - + type: M680X_OP_REGISTER + reg: u + size: 2 + access: CS_AC_READ_WRITE + regs_read: [ cc, y, u ] + regs_write: [ cc, u ] + - + asm_text: "pshsw" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: s + size: 2 + access: CS_AC_READ_WRITE + - + type: M680X_OP_REGISTER + reg: w + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ] + regs_read: [ s, w ] + regs_write: [ s ] + - + asm_text: "puluw" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: u + size: 2 + access: CS_AC_READ_WRITE + - + type: M680X_OP_REGISTER + reg: w + size: 2 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ] + regs_read: [ u ] + regs_write: [ u, w ] + - + asm_text: "comw" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: w + size: 2 + access: CS_AC_READ_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, w ] + regs_write: [ cc, w ] + - + asm_text: "tstw" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: w + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, w ] + regs_write: [ cc ] + - + asm_text: "band a, 0, 3, $10" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_READ_WRITE + - + type: M680X_OP_CONSTANT + const_val: 0 + access: CS_AC_READ + - + type: M680X_OP_CONSTANT + const_val: 3 + access: CS_AC_READ + - + type: M680X_OP_DIRECT + direct_addr: 0x0010 + direct_addr_set: true + size: 1 + access: CS_AC_READ + regs_read: [ a ] + regs_write: [ a ] + - + asm_text: "stbt cc, 4, 5, $10" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: cc + size: 1 + access: CS_AC_READ + - + type: M680X_OP_CONSTANT + const_val: 4 + access: CS_AC_READ + - + type: M680X_OP_CONSTANT + const_val: 5 + access: CS_AC_READ + - + type: M680X_OP_DIRECT + direct_addr: 0x0010 + direct_addr_set: true + size: 1 + access: CS_AC_READ_WRITE + regs_read: [ cc ] + - + asm_text: "tfm x+, y+" + details: + m680x: + operands: + - + type: M680X_OP_INDEXED + idx: + base_reg: x + inc_dec: 1 + flags: [ M680X_IDX_NO_COMMA, M680X_IDX_POST_INC_DEC ] + size: 1 + access: CS_AC_READ + - + type: M680X_OP_INDEXED + idx: + base_reg: y + inc_dec: 1 + flags: [ M680X_IDX_NO_COMMA, M680X_IDX_POST_INC_DEC ] + size: 1 + access: CS_AC_WRITE + regs_read: [ w, x, y ] + regs_write: [ w, x, y ] + - + asm_text: "tfm y-, u-" + details: + m680x: + operands: + - + type: M680X_OP_INDEXED + idx: + base_reg: y + inc_dec: -1 + flags: [ M680X_IDX_NO_COMMA, M680X_IDX_POST_INC_DEC ] + size: 1 + access: CS_AC_READ + - + type: M680X_OP_INDEXED + idx: + base_reg: u + inc_dec: -1 + flags: [ M680X_IDX_NO_COMMA, M680X_IDX_POST_INC_DEC ] + size: 1 + access: CS_AC_WRITE + regs_read: [ w, y, u ] + regs_write: [ w, y, u ] + - + asm_text: "tfm u, s+" + details: + m680x: + operands: + - + type: M680X_OP_INDEXED + idx: + base_reg: u + flags: [ M680X_IDX_NO_COMMA ] + size: 1 + access: CS_AC_READ + - + type: M680X_OP_INDEXED + idx: + base_reg: s + inc_dec: 1 + flags: [ M680X_IDX_NO_COMMA, M680X_IDX_POST_INC_DEC ] + size: 1 + access: CS_AC_WRITE + regs_read: [ w, u, s ] + regs_write: [ w, s ] + - + asm_text: "divq #4096" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: q + size: 4 + access: CS_AC_READ_WRITE + - + type: M680X_OP_IMMEDIATE + imm: 4096 + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, q ] + regs_write: [ cc, q ] + - + asm_text: "muld -16, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: d + size: 2 + access: CS_AC_READ_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: -16 + offset_bits: 5 + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, d, x ] + regs_write: [ cc, d, w ] + - + asm_text: "adde -16, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: e + size: 1 + access: CS_AC_READ_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: -16 + offset_bits: 5 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, e, x ] + regs_write: [ cc, e ] + - + asm_text: "ldf $8000" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: f + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_EXTENDED + ext_address: 0x8000 + ext_indirect: -1 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc ] + regs_write: [ cc, f ] + - + input: + bytes: [ 0x01, 0x09, 0x36, 0x64, 0x7f, 0x74, 0x10, 0x00, 0x90, 0x10, 0xa4, 0x10, 0xb6, 0x10, 0x00, 0x39 ] + arch: "m680x" + options: [ CS_OPT_DETAIL, CS_MODE_M680X_6800 ] + address: 0x1000 + expected: + insns: + - + asm_text: "nop" + - + asm_text: "dex" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: x + size: 2 + access: CS_AC_READ_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, x ] + - + asm_text: "psha" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ a, s ] + regs_write: [ s ] + - + asm_text: "lsr 127, x" + details: + m680x: + operands: + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 127 + offset_bits: 8 + size: 1 + access: CS_AC_READ_WRITE + regs_read: [ cc, x ] + regs_write: [ cc ] + - + asm_text: "lsr $1000" + details: + m680x: + operands: + - + type: M680X_OP_EXTENDED + ext_address: 0x1000 + ext_indirect: -1 + size: 1 + access: CS_AC_READ_WRITE + regs_read: [ cc ] + regs_write: [ cc ] + - + asm_text: "suba $10" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_READ_WRITE + - + type: M680X_OP_DIRECT + direct_addr: 0x0010 + direct_addr_set: true + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, a ] + regs_write: [ cc, a ] + - + asm_text: "anda 16, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_READ_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 16 + offset_bits: 8 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, a, x ] + regs_write: [ cc, a ] + - + asm_text: "ldaa $1000" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_EXTENDED + ext_address: 0x1000 + ext_indirect: -1 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc ] + regs_write: [ cc, a ] + - + asm_text: "rts" + details: + regs_read: [ s ] + regs_write: [ s, pc ] + groups: [ M680X_GRP_RET ] + - + input: + bytes: [ 0x04, 0x05, 0x3c, 0x3d, 0x38, 0x93, 0x10, 0xec, 0x10, 0xed, 0x10, 0x39 ] + arch: "m680x" + options: [ CS_OPT_DETAIL, CS_MODE_M680X_6801 ] + address: 0x1000 + expected: + insns: + - + asm_text: "lsrd" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: d + size: 2 + access: CS_AC_READ_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, d ] + regs_write: [ cc, d ] + - + asm_text: "asld" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: d + size: 2 + access: CS_AC_READ_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, d ] + regs_write: [ cc, d ] + - + asm_text: "pshx" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: x + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ x, s ] + regs_write: [ s ] + - + asm_text: "mul" + details: + regs_read: [ cc, a, b ] + regs_write: [ cc, a, b ] + - + asm_text: "pulx" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: x + size: 2 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ s ] + regs_write: [ x, s ] + - + asm_text: "subd $10" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: d + size: 2 + access: CS_AC_READ_WRITE + - + type: M680X_OP_DIRECT + direct_addr: 0x0010 + direct_addr_set: true + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, d ] + regs_write: [ cc, d ] + - + asm_text: "ldd 16, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: d + size: 2 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 16 + offset_bits: 8 + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, d ] + - + asm_text: "std 16, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: d + size: 2 + access: CS_AC_READ + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 16 + offset_bits: 8 + size: 2 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, d, x ] + regs_write: [ cc ] + - + asm_text: "rts" + details: + regs_read: [ s ] + regs_write: [ s, pc ] + groups: [ M680X_GRP_RET ] + - + input: + bytes: [ 0x04, 0x7f, 0x00, 0x17, 0x22, 0x28, 0x00, 0x2e, 0x00, 0x40, 0x42, 0x5a, 0x70, 0x8e, 0x97, 0x9c, 0xa0, 0x15, 0xad, 0x00, 0xc3, 0x10, 0x00, 0xda, 0x12, 0x34, 0xe5, 0x7f, 0xfe ] + arch: "m680x" + options: [ CS_OPT_DETAIL, CS_MODE_M680X_6805 ] + address: 0x1000 + expected: + insns: + - + asm_text: "brset 2, $7f, $1003" + details: + m680x: + operands: + - + type: M680X_OP_CONSTANT + const_val: 2 + access: CS_AC_READ + - + type: M680X_OP_DIRECT + direct_addr: 0x007f + direct_addr_set: true + size: 1 + access: CS_AC_READ + - + type: M680X_OP_RELATIVE + rel_address: 0x1003 + rel_offset: 0 + regs_read: [ cc ] + regs_write: [ cc ] + groups: [ M680X_GRP_BRAREL, M680X_GRP_JUMP ] + - + asm_text: "bset 3, $22" + details: + m680x: + operands: + - + type: M680X_OP_CONSTANT + const_val: 3 + access: CS_AC_READ + - + type: M680X_OP_DIRECT + direct_addr: 0x0022 + direct_addr_set: true + size: 1 + access: CS_AC_READ_WRITE + - + asm_text: "bhcc $1007" + details: + m680x: + operands: + - + type: M680X_OP_RELATIVE + rel_address: 0x1007 + rel_offset: 0 + regs_read: [ cc ] + groups: [ M680X_GRP_BRAREL, M680X_GRP_JUMP ] + - + asm_text: "bil $1009" + details: + m680x: + operands: + - + type: M680X_OP_RELATIVE + rel_address: 0x1009 + rel_offset: 0 + regs_read: [ cc ] + groups: [ M680X_GRP_BRAREL, M680X_GRP_JUMP ] + - + asm_text: "nega" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_READ_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, a ] + regs_write: [ cc, a ] + - + asm_text: "mul" + details: + regs_read: [ cc, a, x ] + regs_write: [ cc, a, x ] + - + asm_text: "decx" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: x + size: 1 + access: CS_AC_READ_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, x ] + - + asm_text: "neg , x" + details: + m680x: + operands: + - + type: M680X_OP_INDEXED + idx: + base_reg: x + size: 1 + access: CS_AC_READ_WRITE + regs_read: [ cc, x ] + regs_write: [ cc ] + - + asm_text: "stop" + - + asm_text: "tax" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_READ + - + type: M680X_OP_REGISTER + reg: x + size: 1 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ] + regs_read: [ a ] + regs_write: [ x ] + - + asm_text: "rsp" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: s + size: 2 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_write: [ s ] + - + asm_text: "sub #21" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_READ_WRITE + - + type: M680X_OP_IMMEDIATE + imm: 21 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, a ] + regs_write: [ cc, a ] + - + asm_text: "bsr $1014" + details: + m680x: + operands: + - + type: M680X_OP_RELATIVE + rel_address: 0x1014 + rel_offset: 0 + regs_read: [ s ] + regs_write: [ s ] + groups: [ M680X_GRP_BRAREL, M680X_GRP_CALL ] + - + asm_text: "cpx $1000" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: x + size: 1 + access: CS_AC_READ + - + type: M680X_OP_EXTENDED + ext_address: 0x1000 + ext_indirect: -1 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc ] + - + asm_text: "ora 4660, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_READ_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 4660 + offset_bits: 16 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, a, x ] + regs_write: [ cc, a ] + - + asm_text: "bit 127, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_READ + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 127 + offset_bits: 8 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, a, x ] + regs_write: [ cc ] + - + asm_text: "ldx , x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: x + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, x ] + - + input: + bytes: [ 0x31, 0x22, 0x00, 0x35, 0x22, 0x45, 0x10, 0x00, 0x4b, 0x00, 0x51, 0x10, 0x52, 0x5e, 0x22, 0x62, 0x65, 0x12, 0x34, 0x72, 0x84, 0x85, 0x86, 0x87, 0x8a, 0x8b, 0x8c, 0x94, 0x95, 0xa7, 0x10, 0xaf, 0x10, 0x9e, 0x60, 0x7f, 0x9e, 0x6b, 0x7f, 0x00, 0x9e, 0xd6, 0x10, 0x00, 0x9e, 0xe6, 0x7f ] + arch: "m680x" + options: [ CS_OPT_DETAIL, CS_MODE_M680X_6808 ] + address: 0x1000 + expected: + insns: + - + asm_text: "cbeq $22, $1003" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_READ + - + type: M680X_OP_DIRECT + direct_addr: 0x0022 + direct_addr_set: true + size: 1 + access: CS_AC_READ + - + type: M680X_OP_RELATIVE + rel_address: 0x1003 + rel_offset: 0 + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, a ] + groups: [ M680X_GRP_BRAREL, M680X_GRP_JUMP ] + - + asm_text: "sthx $22" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: hx + size: 2 + access: CS_AC_READ + - + type: M680X_OP_DIRECT + direct_addr: 0x0022 + direct_addr_set: true + size: 2 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, hx ] + regs_write: [ cc ] + - + asm_text: "ldhx #4096" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: hx + size: 2 + access: CS_AC_WRITE + - + type: M680X_OP_IMMEDIATE + imm: 4096 + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc ] + regs_write: [ cc, hx ] + - + asm_text: "dbnza $100a" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_READ_WRITE + - + type: M680X_OP_RELATIVE + rel_address: 0x100a + rel_offset: 0 + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, a ] + regs_write: [ a ] + groups: [ M680X_GRP_BRAREL, M680X_GRP_JUMP ] + - + asm_text: "cbeqx #16, $105f" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: x + size: 1 + access: CS_AC_READ + - + type: M680X_OP_IMMEDIATE + imm: 16 + size: 1 + access: CS_AC_READ + - + type: M680X_OP_RELATIVE + rel_address: 0x105f + rel_offset: 82 + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + groups: [ M680X_GRP_BRAREL, M680X_GRP_JUMP ] + - + asm_text: "mov $22; x+" + details: + m680x: + operands: + - + type: M680X_OP_DIRECT + direct_addr: 0x0022 + direct_addr_set: true + size: 1 + access: CS_AC_READ + - + type: M680X_OP_INDEXED + idx: + base_reg: x + inc_dec: 1 + flags: [ M680X_IDX_NO_COMMA, M680X_IDX_POST_INC_DEC ] + size: 1 + access: CS_AC_WRITE + regs_read: [ cc, x, h ] + regs_write: [ cc, x, h ] + - + asm_text: "nsa" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_READ_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, a ] + regs_write: [ cc, a ] + - + asm_text: "cphx #4660" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: hx + size: 2 + access: CS_AC_READ + - + type: M680X_OP_IMMEDIATE + imm: 4660 + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, hx ] + regs_write: [ cc ] + - + asm_text: "daa" + details: + regs_read: [ cc, a ] + regs_write: [ cc, a ] + - + asm_text: "tap" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_READ + - + type: M680X_OP_REGISTER + reg: cc + size: 1 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ] + regs_read: [ a ] + regs_write: [ cc ] + - + asm_text: "tpa" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: cc + size: 1 + access: CS_AC_READ + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ] + regs_read: [ cc ] + regs_write: [ a ] + - + asm_text: "pula" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ s ] + regs_write: [ a, s ] + - + asm_text: "psha" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ a, s ] + regs_write: [ s ] + - + asm_text: "pulh" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: h + size: 1 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ s ] + regs_write: [ h, s ] + - + asm_text: "pshh" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: h + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ h, s ] + regs_write: [ s ] + - + asm_text: "clrh" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: h + size: 1 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc ] + regs_write: [ cc, h ] + - + asm_text: "txs" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: hx + size: 2 + access: CS_AC_READ + - + type: M680X_OP_REGISTER + reg: s + size: 2 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ] + regs_read: [ hx ] + regs_write: [ s ] + - + asm_text: "tsx" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: s + size: 2 + access: CS_AC_READ + - + type: M680X_OP_REGISTER + reg: hx + size: 2 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ] + regs_read: [ s ] + regs_write: [ hx ] + - + asm_text: "ais #16" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: s + size: 2 + access: CS_AC_READ_WRITE + - + type: M680X_OP_IMMEDIATE + imm: 16 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ s ] + regs_write: [ s ] + - + asm_text: "aix #16" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: hx + size: 2 + access: CS_AC_READ_WRITE + - + type: M680X_OP_IMMEDIATE + imm: 16 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ hx ] + regs_write: [ hx ] + - + asm_text: "neg 127, s" + details: + m680x: + operands: + - + type: M680X_OP_INDEXED + idx: + base_reg: s + offset: 127 + offset_bits: 8 + size: 1 + access: CS_AC_READ_WRITE + regs_read: [ cc, s ] + regs_write: [ cc ] + - + asm_text: "dbnz 127, s; $1028" + details: + m680x: + operands: + - + type: M680X_OP_INDEXED + idx: + base_reg: s + offset: 127 + offset_bits: 8 + size: 1 + access: CS_AC_READ_WRITE + - + type: M680X_OP_RELATIVE + rel_address: 0x1028 + rel_offset: 0 + regs_read: [ cc, s ] + groups: [ M680X_GRP_BRAREL, M680X_GRP_JUMP ] + - + asm_text: "lda 4096, s" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: s + offset: 4096 + offset_bits: 16 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, s ] + regs_write: [ cc, a ] + - + asm_text: "lda 127, s" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: s + offset: 127 + offset_bits: 8 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, s ] + regs_write: [ cc, a ] + - + input: + bytes: [ 0x06, 0x10, 0x19, 0x1a, 0x55, 0x1e, 0x01, 0x23, 0xe9, 0x31, 0x06, 0x34, 0x55, 0xa6, 0x81, 0xa7, 0x89, 0x7f, 0xff, 0xa6, 0x9d, 0x10, 0x00, 0xa7, 0x91, 0xa6, 0x9f, 0x10, 0x00, 0x11, 0xac, 0x99, 0x10, 0x00, 0x39, 0xa6, 0x07, 0xa6, 0x27, 0xa6, 0x47, 0xa6, 0x67, 0xa6, 0x0f, 0xa6, 0x10, 0xa6, 0x80, 0xa6, 0x81, 0xa6, 0x82, 0xa6, 0x83, 0xa6, 0x84, 0xa6, 0x85, 0xa6, 0x86, 0xa6, 0x88, 0x7f, 0xa6, 0x88, 0x80, 0xa6, 0x89, 0x7f, 0xff, 0xa6, 0x89, 0x80, 0x00, 0xa6, 0x8b, 0xa6, 0x8c, 0x10, 0xa6, 0x8d, 0x10, 0x00, 0xa6, 0x91, 0xa6, 0x93, 0xa6, 0x94, 0xa6, 0x95, 0xa6, 0x96, 0xa6, 0x98, 0x7f, 0xa6, 0x98, 0x80, 0xa6, 0x99, 0x7f, 0xff, 0xa6, 0x99, 0x80, 0x00, 0xa6, 0x9b, 0xa6, 0x9c, 0x10, 0xa6, 0x9d, 0x10, 0x00, 0xa6, 0x9f, 0x10, 0x00 ] + arch: "m680x" + options: [ CS_OPT_DETAIL, CS_MODE_M680X_6809 ] + address: 0x1000 + expected: + insns: + - + asm_text: "ror $10" + details: + m680x: + operands: + - + type: M680X_OP_DIRECT + direct_addr: 0x0010 + direct_addr_set: true + size: 1 + access: CS_AC_READ_WRITE + regs_read: [ cc ] + regs_write: [ cc ] + - + asm_text: "daa" + details: + regs_read: [ cc, a ] + regs_write: [ cc, a ] + - + asm_text: "orcc #85" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: cc + size: 1 + access: CS_AC_READ_WRITE + - + type: M680X_OP_IMMEDIATE + imm: 85 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc ] + regs_write: [ cc ] + - + asm_text: "exg d, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: d + size: 2 + access: CS_AC_READ_WRITE + - + type: M680X_OP_REGISTER + reg: x + size: 2 + access: CS_AC_READ_WRITE + regs_read: [ d, x ] + regs_write: [ d, x ] + - + asm_text: "bls $0ff2" + details: + m680x: + operands: + - + type: M680X_OP_RELATIVE + rel_address: 0x0ff2 + rel_offset: -23 + regs_read: [ cc ] + groups: [ M680X_GRP_BRAREL, M680X_GRP_JUMP ] + - + asm_text: "leay 6, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: y + size: 2 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 6 + offset_bits: 5 + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, y ] + - + asm_text: "pshs cc, b, x, u" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: s + size: 2 + access: CS_AC_READ_WRITE + - + type: M680X_OP_REGISTER + reg: cc + size: 1 + access: CS_AC_READ + - + type: M680X_OP_REGISTER + reg: b + size: 1 + access: CS_AC_READ + - + type: M680X_OP_REGISTER + reg: x + size: 2 + access: CS_AC_READ + - + type: M680X_OP_REGISTER + reg: u + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ s, cc, b, x, u ] + regs_write: [ s ] + - + asm_text: "lda , x++" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + inc_dec: 2 + flags: [ M680X_IDX_POST_INC_DEC ] + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a, x ] + - + asm_text: "sta 32767, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_READ + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 32767 + offset_bits: 16 + size: 1 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, a, x ] + regs_write: [ cc ] + - + asm_text: "lda [$2017, pcr]" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: pc + offset: 4096 + offset_addr: 0x2017 + offset_bits: 16 + flags: [ M680X_IDX_INDIRECT ] + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, pc ] + regs_write: [ cc, a ] + - + asm_text: "sta [, x++]" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_READ + - + type: M680X_OP_INDEXED + idx: + base_reg: x + inc_dec: 2 + flags: [ M680X_IDX_INDIRECT, M680X_IDX_POST_INC_DEC ] + size: 1 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, a, x ] + regs_write: [ cc, x ] + - + asm_text: "lda [$1000]" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_EXTENDED + ext_address: 0x1000 + ext_indirect: 1 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc ] + regs_write: [ cc, a ] + - + asm_text: "cmps [4096, x]" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: s + size: 2 + access: CS_AC_READ + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 4096 + offset_bits: 16 + flags: [ M680X_IDX_INDIRECT ] + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, s, x ] + regs_write: [ cc ] + - + asm_text: "rts" + details: + regs_read: [ s ] + regs_write: [ s, pc ] + groups: [ M680X_GRP_RET ] + - + asm_text: "lda 7, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 7 + offset_bits: 5 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a ] + - + asm_text: "lda 7, y" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: y + offset: 7 + offset_bits: 5 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, y ] + regs_write: [ cc, a ] + - + asm_text: "lda 7, u" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: u + offset: 7 + offset_bits: 5 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, u ] + regs_write: [ cc, a ] + - + asm_text: "lda 7, s" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: s + offset: 7 + offset_bits: 5 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, s ] + regs_write: [ cc, a ] + - + asm_text: "lda 15, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 15 + offset_bits: 5 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a ] + - + asm_text: "lda -16, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: -16 + offset_bits: 5 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a ] + - + asm_text: "lda , x+" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + inc_dec: 1 + flags: [ M680X_IDX_POST_INC_DEC ] + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a, x ] + - + asm_text: "lda , x++" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + inc_dec: 2 + flags: [ M680X_IDX_POST_INC_DEC ] + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a, x ] + - + asm_text: "lda , -x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + inc_dec: -1 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a, x ] + - + asm_text: "lda , --x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + inc_dec: -2 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a, x ] + - + asm_text: "lda , x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a ] + - + asm_text: "lda b, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset_reg: b + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x, b ] + regs_write: [ cc, a ] + - + asm_text: "lda a, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset_reg: a + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x, a ] + regs_write: [ cc, a ] + - + asm_text: "lda 127, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 127 + offset_bits: 8 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a ] + - + asm_text: "lda -128, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: -128 + offset_bits: 8 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a ] + - + asm_text: "lda 32767, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 32767 + offset_bits: 16 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a ] + - + asm_text: "lda -32768, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: -32768 + offset_bits: 16 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a ] + - + asm_text: "lda d, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset_reg: d + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x, d ] + regs_write: [ cc, a ] + - + asm_text: "lda $1050, pcr" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: pc + offset: 16 + offset_addr: 0x1050 + offset_bits: 8 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, pc ] + regs_write: [ cc, a ] + - + asm_text: "lda $2054, pcr" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: pc + offset: 4096 + offset_addr: 0x2054 + offset_bits: 16 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, pc ] + regs_write: [ cc, a ] + - + asm_text: "lda [, x++]" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + inc_dec: 2 + flags: [ M680X_IDX_INDIRECT, M680X_IDX_POST_INC_DEC ] + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a, x ] + - + asm_text: "lda [, --x]" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + inc_dec: -2 + flags: [ M680X_IDX_INDIRECT ] + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a, x ] + - + asm_text: "lda [, x]" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + flags: [ M680X_IDX_INDIRECT ] + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a ] + - + asm_text: "lda [b, x]" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset_reg: b + flags: [ M680X_IDX_INDIRECT ] + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x, b ] + regs_write: [ cc, a ] + - + asm_text: "lda [a, x]" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset_reg: a + flags: [ M680X_IDX_INDIRECT ] + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x, a ] + regs_write: [ cc, a ] + - + asm_text: "lda [127, x]" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 127 + offset_bits: 8 + flags: [ M680X_IDX_INDIRECT ] + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a ] + - + asm_text: "lda [-128, x]" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: -128 + offset_bits: 8 + flags: [ M680X_IDX_INDIRECT ] + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a ] + - + asm_text: "lda [32767, x]" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 32767 + offset_bits: 16 + flags: [ M680X_IDX_INDIRECT ] + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a ] + - + asm_text: "lda [-32768, x]" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: -32768 + offset_bits: 16 + flags: [ M680X_IDX_INDIRECT ] + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, a ] + - + asm_text: "lda [d, x]" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset_reg: d + flags: [ M680X_IDX_INDIRECT ] + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x, d ] + regs_write: [ cc, a ] + - + asm_text: "lda [$1071, pcr]" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: pc + offset: 16 + offset_addr: 0x1071 + offset_bits: 8 + flags: [ M680X_IDX_INDIRECT ] + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, pc ] + regs_write: [ cc, a ] + - + asm_text: "lda [$2075, pcr]" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: pc + offset: 4096 + offset_addr: 0x2075 + offset_bits: 16 + flags: [ M680X_IDX_INDIRECT ] + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, pc ] + regs_write: [ cc, a ] + - + asm_text: "lda [$1000]" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_EXTENDED + ext_address: 0x1000 + ext_indirect: 1 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc ] + regs_write: [ cc, a ] + - + input: + bytes: [ 0x02, 0x03, 0x12, 0x7f, 0x10, 0x00, 0x13, 0x99, 0x08, 0x00, 0x14, 0x7f, 0x02, 0x15, 0x7f, 0x01, 0x1e, 0x7f, 0x20, 0x00, 0x8f, 0xcf, 0x18, 0x08, 0x18, 0x30, 0x18, 0x3c, 0x18, 0x67, 0x18, 0x8c, 0x10, 0x00, 0x18, 0x8f, 0x18, 0xce, 0x10, 0x00, 0x18, 0xff, 0x10, 0x00, 0x1a, 0xa3, 0x7f, 0x1a, 0xac, 0x1a, 0xee, 0x7f, 0x1a, 0xef, 0x7f, 0xcd, 0xac, 0x7f ] + arch: "m680x" + options: [ CS_OPT_DETAIL, CS_MODE_M680X_6811 ] + address: 0x1000 + expected: + insns: + - + asm_text: "idiv" + details: + regs_read: [ cc, d, x ] + regs_write: [ cc, d, x ] + - + asm_text: "fdiv" + details: + regs_read: [ cc, d, x ] + regs_write: [ cc, d, x ] + - + asm_text: "brset $7f, #16, $1006" + details: + m680x: + operands: + - + type: M680X_OP_DIRECT + direct_addr: 0x007f + direct_addr_set: true + size: 1 + access: CS_AC_READ + - + type: M680X_OP_IMMEDIATE + imm: 16 + size: 1 + access: CS_AC_READ + - + type: M680X_OP_RELATIVE + rel_address: 0x1006 + rel_offset: 0 + regs_read: [ cc ] + groups: [ M680X_GRP_BRAREL, M680X_GRP_JUMP ] + - + asm_text: "brclr $99, #8, $100a" + details: + m680x: + operands: + - + type: M680X_OP_DIRECT + direct_addr: 0x0099 + direct_addr_set: true + size: 1 + access: CS_AC_READ + - + type: M680X_OP_IMMEDIATE + imm: 8 + size: 1 + access: CS_AC_READ + - + type: M680X_OP_RELATIVE + rel_address: 0x100a + rel_offset: 0 + regs_read: [ cc ] + groups: [ M680X_GRP_BRAREL, M680X_GRP_JUMP ] + - + asm_text: "bset $7f, #2" + details: + m680x: + operands: + - + type: M680X_OP_DIRECT + direct_addr: 0x007f + direct_addr_set: true + size: 1 + access: CS_AC_READ_WRITE + - + type: M680X_OP_IMMEDIATE + imm: 2 + size: 1 + access: CS_AC_READ + regs_read: [ cc ] + regs_write: [ cc ] + - + asm_text: "bclr $7f, #1" + details: + m680x: + operands: + - + type: M680X_OP_DIRECT + direct_addr: 0x007f + direct_addr_set: true + size: 1 + access: CS_AC_READ_WRITE + - + type: M680X_OP_IMMEDIATE + imm: 1 + size: 1 + access: CS_AC_READ + regs_read: [ cc ] + regs_write: [ cc ] + - + asm_text: "brset 127, x; #32; $1014" + details: + m680x: + operands: + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 127 + offset_bits: 8 + size: 1 + access: CS_AC_READ + - + type: M680X_OP_IMMEDIATE + imm: 32 + size: 1 + access: CS_AC_READ + - + type: M680X_OP_RELATIVE + rel_address: 0x1014 + rel_offset: 0 + regs_read: [ cc, x ] + groups: [ M680X_GRP_BRAREL, M680X_GRP_JUMP ] + - + asm_text: "xgdx" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: d + size: 2 + access: CS_AC_READ_WRITE + - + type: M680X_OP_REGISTER + reg: x + size: 2 + access: CS_AC_READ_WRITE + flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ] + regs_read: [ d, x ] + regs_write: [ d, x ] + - + asm_text: "stop" + - + asm_text: "iny" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: y + size: 2 + access: CS_AC_READ_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, y ] + regs_write: [ cc, y ] + - + asm_text: "tsy" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: s + size: 2 + access: CS_AC_READ + - + type: M680X_OP_REGISTER + reg: y + size: 2 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ] + regs_read: [ s ] + regs_write: [ y ] + - + asm_text: "pshy" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: y + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ y, s ] + regs_write: [ s ] + - + asm_text: "asr 24, y" + details: + m680x: + operands: + - + type: M680X_OP_INDEXED + idx: + base_reg: y + offset: 24 + offset_bits: 8 + size: 1 + access: CS_AC_READ_WRITE + regs_read: [ cc, y ] + regs_write: [ cc ] + - + asm_text: "cpx #4096" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: x + size: 2 + access: CS_AC_READ + - + type: M680X_OP_IMMEDIATE + imm: 4096 + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc ] + - + asm_text: "xgdy" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: d + size: 2 + access: CS_AC_READ_WRITE + - + type: M680X_OP_REGISTER + reg: y + size: 2 + access: CS_AC_READ_WRITE + flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ] + regs_read: [ d, y ] + regs_write: [ d, y ] + - + asm_text: "ldy #4096" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: y + size: 2 + access: CS_AC_WRITE + - + type: M680X_OP_IMMEDIATE + imm: 4096 + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc ] + regs_write: [ cc, y ] + - + asm_text: "sty $1000" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: y + size: 2 + access: CS_AC_READ + - + type: M680X_OP_EXTENDED + ext_address: 0x1000 + ext_indirect: -1 + size: 2 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, y ] + regs_write: [ cc ] + - + asm_text: "cpd 127, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: d + size: 2 + access: CS_AC_READ + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 127 + offset_bits: 8 + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, d, x ] + regs_write: [ cc ] + - + asm_text: "cpy 26, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: y + size: 2 + access: CS_AC_READ + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 26 + offset_bits: 8 + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, y, x ] + regs_write: [ cc ] + - + asm_text: "ldx 127, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: x + size: 2 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 127 + offset_bits: 8 + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x ] + regs_write: [ cc, x ] + - + asm_text: "sty 127, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: y + size: 2 + access: CS_AC_READ + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 127 + offset_bits: 8 + size: 2 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, y, x ] + regs_write: [ cc ] + - + asm_text: "cpx 127, y" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: x + size: 2 + access: CS_AC_READ + - + type: M680X_OP_INDEXED + idx: + base_reg: y + offset: 127 + offset_bits: 8 + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x, y ] + regs_write: [ cc ] + - + input: + bytes: [ 0x00, 0x04, 0x01, 0x00, 0x0c, 0x00, 0x80, 0x0e, 0x00, 0x80, 0x00, 0x11, 0x1e, 0x10, 0x00, 0x80, 0x00, 0x3b, 0x4a, 0x10, 0x00, 0x04, 0x4b, 0x01, 0x04, 0x4f, 0x7f, 0x80, 0x00, 0x8f, 0x10, 0x00, 0xb7, 0x52, 0xb7, 0xb1, 0xa6, 0x67, 0xa6, 0xfe, 0xa6, 0xf7, 0x18, 0x02, 0xe2, 0x30, 0x39, 0xe2, 0x10, 0x00, 0x18, 0x0c, 0x30, 0x39, 0x10, 0x00, 0x18, 0x11, 0x18, 0x12, 0x10, 0x00, 0x18, 0x19, 0x00, 0x18, 0x1e, 0x00, 0x18, 0x3e, 0x18, 0x3f, 0x00 ] + arch: "m680x" + options: [ CS_OPT_DETAIL, CS_MODE_M680X_CPU12 ] + address: 0x1000 + expected: + insns: + - + asm_text: "bgnd" + - + asm_text: "dbeq b, $1004" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: b + size: 1 + access: CS_AC_READ_WRITE + - + type: M680X_OP_RELATIVE + rel_address: 0x1004 + rel_offset: 0 + regs_read: [ b ] + regs_write: [ b ] + groups: [ M680X_GRP_BRAREL, M680X_GRP_JUMP ] + - + asm_text: "bset 0, x; #-128" + details: + m680x: + operands: + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 0 + offset_bits: 5 + size: 1 + access: CS_AC_READ_WRITE + - + type: M680X_OP_IMMEDIATE + imm: -128 + size: 1 + access: CS_AC_READ + regs_read: [ cc, x ] + regs_write: [ cc ] + - + asm_text: "brset 0, x; #-128; $100b" + details: + m680x: + operands: + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 0 + offset_bits: 5 + size: 1 + access: CS_AC_READ + - + type: M680X_OP_IMMEDIATE + imm: -128 + size: 1 + access: CS_AC_READ + - + type: M680X_OP_RELATIVE + rel_address: 0x100b + rel_offset: 0 + regs_read: [ cc, x ] + groups: [ M680X_GRP_BRAREL, M680X_GRP_JUMP ] + - + asm_text: "ediv" + details: + regs_read: [ cc, d, y, x ] + regs_write: [ cc, d, y ] + - + asm_text: "brset $1000, #-128, $1011" + details: + m680x: + operands: + - + type: M680X_OP_EXTENDED + ext_address: 0x1000 + ext_indirect: -1 + size: 1 + access: CS_AC_READ + - + type: M680X_OP_IMMEDIATE + imm: -128 + size: 1 + access: CS_AC_READ + - + type: M680X_OP_RELATIVE + rel_address: 0x1011 + rel_offset: 0 + regs_read: [ cc ] + groups: [ M680X_GRP_BRAREL, M680X_GRP_JUMP ] + - + asm_text: "pshd" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: d + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ d, s ] + regs_write: [ s ] + - + asm_text: "call $1000, 4" + details: + m680x: + operands: + - + type: M680X_OP_EXTENDED + ext_address: 0x1000 + ext_indirect: -1 + size: 1 + - + type: M680X_OP_CONSTANT + const_val: 4 + regs_read: [ s ] + regs_write: [ s ] + groups: [ M680X_GRP_CALL ] + - + asm_text: "call 1, x; 4" + details: + m680x: + operands: + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 1 + offset_bits: 5 + size: 1 + - + type: M680X_OP_CONSTANT + const_val: 4 + regs_read: [ x, s ] + regs_write: [ s ] + groups: [ M680X_GRP_CALL ] + - + asm_text: "brclr $7f, #-128, $101d" + details: + m680x: + operands: + - + type: M680X_OP_DIRECT + direct_addr: 0x007f + direct_addr_set: true + size: 1 + access: CS_AC_READ + - + type: M680X_OP_IMMEDIATE + imm: -128 + size: 1 + access: CS_AC_READ + - + type: M680X_OP_RELATIVE + rel_address: 0x101d + rel_offset: 0 + regs_read: [ cc ] + groups: [ M680X_GRP_BRAREL, M680X_GRP_JUMP ] + - + asm_text: "cps #4096" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: s + size: 2 + access: CS_AC_READ + - + type: M680X_OP_IMMEDIATE + imm: 4096 + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, s ] + regs_write: [ cc ] + - + asm_text: "tfr x, cc" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: x + size: 2 + access: CS_AC_READ + - + type: M680X_OP_REGISTER + reg: cc + size: 1 + access: CS_AC_WRITE + regs_read: [ x ] + regs_write: [ cc ] + - + asm_text: "exg tmp3, b" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: tmp3 + size: 2 + access: CS_AC_READ_WRITE + - + type: M680X_OP_REGISTER + reg: b + size: 1 + access: CS_AC_READ_WRITE + regs_read: [ tmp3, b ] + regs_write: [ tmp3, b ] + - + asm_text: "ldaa 8, +y" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: y + inc_dec: 8 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, y ] + regs_write: [ cc, a, y ] + - + asm_text: "ldaa d, pc" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: pc + offset_reg: d + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, pc, d ] + regs_write: [ cc, a ] + - + asm_text: "ldaa [d, s]" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: s + offset_reg: d + flags: [ M680X_IDX_INDIRECT ] + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, s, d ] + regs_write: [ cc, a ] + - + asm_text: "movw 12345, x; 4096, x" + details: + m680x: + operands: + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 12345 + offset_bits: 16 + size: 2 + access: CS_AC_READ + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 4096 + offset_bits: 16 + size: 2 + access: CS_AC_WRITE + regs_read: [ x ] + - + asm_text: "movb $3039, $1000" + details: + m680x: + operands: + - + type: M680X_OP_EXTENDED + ext_address: 0x3039 + ext_indirect: -1 + size: 1 + access: CS_AC_READ + - + type: M680X_OP_EXTENDED + ext_address: 0x1000 + ext_indirect: -1 + size: 1 + access: CS_AC_WRITE + - + asm_text: "fdiv" + details: + regs_read: [ cc, d, x ] + regs_write: [ cc, d, x ] + - + asm_text: "emacs $1000" + details: + m680x: + operands: + - + type: M680X_OP_EXTENDED + ext_address: 0x1000 + ext_indirect: -1 + size: 4 + access: CS_AC_READ_WRITE + regs_read: [ cc, x, y ] + regs_write: [ cc, x ] + - + asm_text: "mina 0, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: a + size: 1 + access: CS_AC_READ_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 0 + offset_bits: 5 + size: 1 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, a, x ] + regs_write: [ cc, a ] + - + asm_text: "emaxm 0, x" + details: + m680x: + operands: + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 0 + offset_bits: 5 + size: 1 + access: CS_AC_READ_WRITE + regs_read: [ cc, x, d ] + regs_write: [ cc ] + - + asm_text: "stop" + - + asm_text: "etbl 0, x" + details: + m680x: + operands: + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 0 + offset_bits: 5 + size: 1 + access: CS_AC_READ + regs_read: [ cc, x, b ] + regs_write: [ cc, a, b ] + - + input: + bytes: [ 0x32, 0x10, 0x00, 0x9e, 0xae, 0x9e, 0xce, 0x7f, 0x9e, 0xbe, 0x10, 0x00, 0x9e, 0xfe, 0x7f, 0x3e, 0x10, 0x00, 0x9e, 0xf3, 0x7f, 0x96, 0x10, 0x00, 0x9e, 0xff, 0x7f, 0x82 ] + arch: "m680x" + options: [ CS_OPT_DETAIL, CS_MODE_M680X_HCS08 ] + address: 0x1000 + expected: + insns: + - + asm_text: "ldhx $1000" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: hx + size: 2 + access: CS_AC_WRITE + - + type: M680X_OP_EXTENDED + ext_address: 0x1000 + ext_indirect: -1 + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc ] + regs_write: [ cc, hx ] + - + asm_text: "ldhx , x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: hx + size: 2 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x, h ] + regs_write: [ cc, hx ] + - + asm_text: "ldhx 127, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: hx + size: 2 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 127 + offset_bits: 8 + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x, h ] + regs_write: [ cc, hx ] + - + asm_text: "ldhx 4096, x" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: hx + size: 2 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: x + offset: 4096 + offset_bits: 16 + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, x, h ] + regs_write: [ cc, hx ] + - + asm_text: "ldhx 127, s" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: hx + size: 2 + access: CS_AC_WRITE + - + type: M680X_OP_INDEXED + idx: + base_reg: s + offset: 127 + offset_bits: 8 + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, s ] + regs_write: [ cc, hx ] + - + asm_text: "cphx $1000" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: hx + size: 2 + access: CS_AC_READ + - + type: M680X_OP_EXTENDED + ext_address: 0x1000 + ext_indirect: -1 + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, hx ] + regs_write: [ cc ] + - + asm_text: "cphx 127, s" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: hx + size: 2 + access: CS_AC_READ + - + type: M680X_OP_INDEXED + idx: + base_reg: s + offset: 127 + offset_bits: 8 + size: 2 + access: CS_AC_READ + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, hx, s ] + regs_write: [ cc ] + - + asm_text: "sthx $1000" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: hx + size: 2 + access: CS_AC_READ + - + type: M680X_OP_EXTENDED + ext_address: 0x1000 + ext_indirect: -1 + size: 2 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, hx ] + regs_write: [ cc ] + - + asm_text: "sthx 127, s" + details: + m680x: + operands: + - + type: M680X_OP_REGISTER + reg: hx + size: 2 + access: CS_AC_READ + - + type: M680X_OP_INDEXED + idx: + base_reg: s + offset: 127 + offset_bits: 8 + size: 2 + access: CS_AC_WRITE + flags: [M680X_FIRST_OP_IN_MNEM ] + regs_read: [ cc, hx, s ] + regs_write: [ cc ] + - + asm_text: "bgnd" + diff --git a/tests/details/m68k.yaml b/tests/details/m68k.yaml new file mode 100644 index 0000000000..cd9a786569 --- /dev/null +++ b/tests/details/m68k.yaml @@ -0,0 +1,212 @@ +test_cases: + - + input: + bytes: [ 0xf0, 0x10, 0xf0, 0x00, 0x48, 0xaf, 0xff, 0xff, 0x7f, 0xff, 0x11, 0xb0, 0x01, 0x37, 0x7f, 0xff, 0xff, 0xff, 0x12, 0x34, 0x56, 0x78, 0x01, 0x33, 0x10, 0x10, 0x10, 0x10, 0x32, 0x32, 0x32, 0x32, 0x4c, 0x00, 0x54, 0x04, 0x48, 0xe7, 0xe0, 0x30, 0x4c, 0xdf, 0x0c, 0x07, 0xd4, 0x40, 0x87, 0x5a, 0x4e, 0x71, 0x02, 0xb4, 0xc0, 0xde, 0xc0, 0xde, 0x5c, 0x00, 0x1d, 0x80, 0x71, 0x12, 0x01, 0x23, 0xf2, 0x3c, 0x44, 0x22, 0x40, 0x49, 0x0e, 0x56, 0x54, 0xc5, 0xf2, 0x3c, 0x44, 0x00, 0x44, 0x7a, 0x00, 0x00, 0xf2, 0x00, 0x0a, 0x28, 0x4e, 0xb9, 0x00, 0x00, 0x00, 0x12, 0x4e, 0x75 ] + arch: "m68k" + options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + address: 0x1000 + expected: + insns: + - + asm_text: "fmovem #$0, (a0)" + details: + regs_read: [ a0 ] + m68k: + operands: + - + type: M68K_OP_REG_BITS + register_bits: 0x0 + - + type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - + asm_text: "movem.w d0-d7/a0-a7, $7fff(a7)" + details: + regs_read: [ d0, d1, d2, d3, d4, d5, d6, d7, a0, a1, a2, a3, a4, a5, a6, a7 ] + m68k: + operands: + - + type: M68K_OP_REG_BITS + register_bits: 0xffff + - + type: M68K_OP_MEM + mem: + base_reg: a7 + disp: 0x7fff + address_mode: M68K_AM_REGI_ADDR_DISP + - + asm_text: "move.b ([$7fffffff, a0], d0.w, $12345678), ([$10101010, a0, d0.w], $32323232)" + details: + regs_read: [ d0, a0 ] + m68k: + operands: + - + type: M68K_OP_MEM + mem: + base_reg: a0 + index_reg: d0 + index_size: -1 + address_mode: M68K_AM_MEMI_POST_INDEX + - + type: M68K_OP_MEM + mem: + base_reg: a0 + index_reg: d0 + index_size: -1 + address_mode: M68K_AM_MEMI_PRE_INDEX + - + asm_text: "mulu.l d0, d4:d5" + details: + regs_read: [ d0 ] + regs_write: [ d4, d5 ] + m68k: + operands: + - + type: M68K_OP_REG + reg: d0 + - + type: M68K_OP_REG_PAIR + reg_pair_0: d4 + reg_pair_1: d5 + - + asm_text: "movem.l d0-d2/a2-a3, -(a7)" + details: + regs_read: [ d0, d1, d2, a2, a3 ] + regs_write: [ a7 ] + m68k: + operands: + - + type: M68K_OP_REG_BITS + register_bits: 0xc07 + - + type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR_PRE_DEC + - + asm_text: "movem.l (a7)+, d0-d2/a2-a3" + details: + regs_write: [ a7, d0, d1, d2, a2, a3 ] + m68k: + operands: + - + type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR_POST_INC + - + type: M68K_OP_REG_BITS + register_bits: 0xc07 + - + asm_text: "add.w d0, d2" + details: + regs_read: [ d0 ] + regs_write: [ d2 ] + m68k: + operands: + - + type: M68K_OP_REG + reg: d0 + - + type: M68K_OP_REG + reg: d2 + - + asm_text: "or.w d3, (a2)+" + details: + regs_read: [ d3 ] + regs_write: [ a2 ] + m68k: + operands: + - + type: M68K_OP_REG + reg: d3 + - + type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR_POST_INC + - + asm_text: "nop" + - + asm_text: "andi.l #$c0dec0de, (a4, d5.l * 4)" + details: + regs_read: [ d5, a4 ] + m68k: + operands: + - + type: M68K_OP_IMM + imm: 0xc0dec0de + - + type: M68K_OP_MEM + mem: + base_reg: a4 + index_reg: d5 + index_size: 1 + scale: 4 + address_mode: M68K_AM_AREGI_INDEX_BASE_DISP + - + asm_text: "move.b d0, ([a6, d7.w], $123)" + details: + regs_read: [ d0, d7, a6 ] + m68k: + operands: + - + type: M68K_OP_REG + reg: d0 + - + type: M68K_OP_MEM + mem: + base_reg: a6 + index_reg: d7 + index_size: -1 + address_mode: M68K_AM_MEMI_PRE_INDEX + - + asm_text: "fadd.s #3.141500, fp0" + details: + regs_write: [ fp0 ] + m68k: + operands: + - + type: M68K_OP_FP_SINGLE + simm: 3.141500 + - + type: M68K_OP_REG + reg: fp0 + - + asm_text: "scc.b d5" + details: + regs_write: [ d5 ] + m68k: + operands: + - + type: M68K_OP_REG + reg: d5 + - + asm_text: "fmove.s #1000.000000, fp0" + details: + regs_write: [ fp0 ] + m68k: + operands: + - + type: M68K_OP_FP_SINGLE + simm: 1000.000000 + - + type: M68K_OP_REG + reg: fp0 + - + asm_text: "fsub fp2, fp4" + details: + regs_read: [ fp2 ] + regs_write: [ fp4 ] + m68k: + operands: + - + type: M68K_OP_REG + reg: fp2 + - + type: M68K_OP_REG + reg: fp4 + - + asm_text: "jsr $12.l" + details: + m68k: + operands: + - + type: M68K_OP_MEM + address_mode: M68K_AM_ABSOLUTE_DATA_LONG + - + asm_text: "rts" diff --git a/tests/details/mips.yaml b/tests/details/mips.yaml new file mode 100644 index 0000000000..1695728f89 --- /dev/null +++ b/tests/details/mips.yaml @@ -0,0 +1,220 @@ +test_cases: + - + input: + bytes: [ 0x0c, 0x10, 0x00, 0x97, 0x00, 0x00, 0x00, 0x00, 0x24, 0x02, 0x00, 0x0c, 0x8f, 0xa2, 0x00, 0x00, 0x34, 0x21, 0x34, 0x56 ] + arch: "mips" + options: [ CS_OPT_DETAIL, CS_MODE_MIPS32, CS_MODE_BIG_ENDIAN ] + address: 0x0 + expected: + insns: + - + asm_text: "jal 0x40025c" + details: + mips: + operands: + - + type: MIPS_OP_IMM + imm: 0x40025c + - + asm_text: "nop" + - + asm_text: "addiu $v0, $zero, 0xc" + details: + mips: + operands: + - + type: MIPS_OP_REG + reg: v0 + - + type: MIPS_OP_REG + reg: zero + - + type: MIPS_OP_IMM + imm: 0xc + - + asm_text: "lw $v0, ($sp)" + details: + mips: + operands: + - + type: MIPS_OP_REG + reg: v0 + - + type: MIPS_OP_MEM + mem_base: sp + - + asm_text: "ori $at, $at, 0x3456" + details: + mips: + operands: + - + type: MIPS_OP_REG + reg: at + - + type: MIPS_OP_REG + reg: at + - + type: MIPS_OP_IMM + imm: 0x3456 + - + input: + bytes: [ 0x56, 0x34, 0x21, 0x34, 0xc2, 0x17, 0x01, 0x00 ] + arch: "mips" + options: [ CS_OPT_DETAIL, CS_MODE_MIPS64, CS_MODE_LITTLE_ENDIAN ] + address: 0x0 + expected: + insns: + - + asm_text: "ori $at, $at, 0x3456" + details: + mips: + operands: + - + type: MIPS_OP_REG + reg: at + - + type: MIPS_OP_REG + reg: at + - + type: MIPS_OP_IMM + imm: 0x3456 + - + asm_text: "srl $v0, $at, 0x1f" + details: + mips: + operands: + - + type: MIPS_OP_REG + reg: v0 + - + type: MIPS_OP_REG + reg: at + - + type: MIPS_OP_IMM + imm: 0x1f + - + input: + bytes: [ 0x00, 0x07, 0x00, 0x07, 0x00, 0x11, 0x93, 0x7c, 0x01, 0x8c, 0x8b, 0x7c, 0x00, 0xc7, 0x48, 0xd0 ] + arch: "mips" + options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R6, CS_MODE_MICRO, CS_MODE_BIG_ENDIAN ] + address: 0x0 + expected: + insns: + - + asm_text: "break 7, 0" + details: + mips: + operands: + - + type: MIPS_OP_IMM + imm: 0x7 + - + type: MIPS_OP_IMM + imm: 0x0 + - + asm_text: "wait 0x11" + details: + mips: + operands: + - + type: MIPS_OP_IMM + imm: 0x11 + - + asm_text: "syscall 0x18c" + details: + mips: + operands: + - + type: MIPS_OP_IMM + imm: 0x18c + - + asm_text: "rotrv $t1, $a2, $a3" + details: + mips: + operands: + - + type: MIPS_OP_REG + reg: t1 + - + type: MIPS_OP_REG + reg: a2 + - + type: MIPS_OP_REG + reg: a3 + - + input: + bytes: [ 0xec, 0x80, 0x00, 0x19, 0x7c, 0x43, 0x22, 0xa0 ] + arch: "mips" + options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R6, CS_MODE_BIG_ENDIAN ] + address: 0x0 + expected: + insns: + - + asm_text: "addiupc $a0, 0x64" + details: + mips: + operands: + - + type: MIPS_OP_REG + reg: a0 + - + type: MIPS_OP_IMM + imm: 0x64 + - + asm_text: "align $a0, $v0, $v1, 2" + details: + mips: + operands: + - + type: MIPS_OP_REG + reg: a0 + - + type: MIPS_OP_REG + reg: v0 + - + type: MIPS_OP_REG + reg: v1 + - + type: MIPS_OP_IMM + imm: 0x2 + - + input: + bytes: [ 0x70, 0x00, 0xb2, 0xff ] + arch: "mips" + options: [ CS_MODE_MIPS64, CS_MODE_MIPS2, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "sdc3 $18, 0x70($sp)" + details: + mips: + operands: + - + type: MIPS_OP_REG + reg: s2 + - + type: MIPS_OP_MEM + mem_base: sp + mem_disp: 0x70 + - + input: + bytes: [ 0x70, 0x00, 0xb2, 0xff ] + arch: "mips" + options: [ CS_OPT_DETAIL, CS_MODE_MIPS64, CS_MODE_LITTLE_ENDIAN] + address: 0x0 + expected: + insns: + - + asm_text: "sd $s2, 0x70($sp)" + details: + mips: + operands: + - + type: MIPS_OP_REG + reg: s2 + - + type: MIPS_OP_MEM + mem_base: sp + mem_disp: 0x70 + diff --git a/tests/details/mos65xx.yaml b/tests/details/mos65xx.yaml new file mode 100644 index 0000000000..7b79af5892 --- /dev/null +++ b/tests/details/mos65xx.yaml @@ -0,0 +1,520 @@ +test_cases: + - + input: + bytes: [ 0xa1, 0x12, 0xa5, 0x12, 0xa9, 0x12, 0xad, 0x34, 0x12, 0xb1, 0x12, 0xb5, 0x12, 0xb9, 0x34, 0x12, 0xbd, 0x34, 0x12, 0x0d, 0x34, 0x12, 0x00, 0x81, 0x87, 0x6c, 0x01, 0x00, 0x85, 0xff, 0x10, 0x00, 0x19, 0x42, 0x42, 0x00, 0x49, 0x42 ] + arch: "mos65xx" + options: [ CS_OPT_DETAIL, CS_MODE_MOS65XX_6502, CS_OPT_SYNTAX_MOTOROLA ] + address: 0x1000 + expected: + insns: + - + asm_text: "lda ($12, x)" + details: + mos65xx: + am: MOS65XX_AM_ZP_X_IND + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "lda $12" + details: + mos65xx: + am: MOS65XX_AM_ZP + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "lda #$12" + details: + mos65xx: + am: MOS65XX_AM_IMM + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_IMM + imm: 0x12 + - + asm_text: "lda $1234" + details: + mos65xx: + am: MOS65XX_AM_ABS + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x1234 + - + asm_text: "lda ($12), y" + details: + mos65xx: + am: MOS65XX_AM_ZP_IND_Y + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "lda $12, x" + details: + mos65xx: + am: MOS65XX_AM_ZP_X + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "lda $1234, y" + details: + mos65xx: + am: MOS65XX_AM_ABS_Y + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x1234 + - + asm_text: "lda $1234, x" + details: + mos65xx: + am: MOS65XX_AM_ABS_X + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x1234 + - + asm_text: "ora $1234" + details: + mos65xx: + am: MOS65XX_AM_ABS + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x1234 + - + asm_text: "brk $81" + details: + mos65xx: + am: MOS65XX_AM_INT + modifies_flags: -1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x81 + - + input: + bytes: [ 0x1a, 0x3a, 0x02, 0x12, 0x03, 0x5c, 0x34, 0x12 ] + arch: "mos65xx" + options: [ CS_OPT_DETAIL, CS_MODE_MOS65XX_65C02, CS_OPT_SYNTAX_MOTOROLA ] + address: 0x1000 + expected: + insns: + - + asm_text: "inc a" + details: + mos65xx: + am: MOS65XX_AM_ACC + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_REG + reg: A + - + asm_text: "dec a" + details: + mos65xx: + am: MOS65XX_AM_ACC + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_REG + reg: A + - + asm_text: "nop" + details: + mos65xx: + am: MOS65XX_AM_IMP + modifies_flags: -1 + - + asm_text: "nop" + details: + mos65xx: + am: MOS65XX_AM_IMP + modifies_flags: -1 + - + asm_text: "nop" + details: + mos65xx: + am: MOS65XX_AM_IMP + modifies_flags: -1 + - + input: + bytes: [ 0x07, 0x12, 0x27, 0x12, 0x47, 0x12, 0x67, 0x12, 0x87, 0x12, 0xa7, 0x12, 0xc7, 0x12, 0xe7, 0x12, 0x10, 0xfe, 0x0f, 0x12, 0xfd, 0x4f, 0x12, 0xfd, 0x8f, 0x12, 0xfd, 0xcf, 0x12, 0xfd ] + arch: "mos65xx" + options: [ CS_OPT_DETAIL, CS_MODE_MOS65XX_W65C02, CS_OPT_SYNTAX_MOTOROLA ] + address: 0x1000 + expected: + insns: + - + asm_text: "rmb0 $12" + details: + mos65xx: + am: MOS65XX_AM_ZP + modifies_flags: -1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "rmb2 $12" + details: + mos65xx: + am: MOS65XX_AM_ZP + modifies_flags: -1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "rmb4 $12" + details: + mos65xx: + am: MOS65XX_AM_ZP + modifies_flags: -1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "rmb6 $12" + details: + mos65xx: + am: MOS65XX_AM_ZP + modifies_flags: -1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "smb0 $12" + details: + mos65xx: + am: MOS65XX_AM_ZP + modifies_flags: -1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "smb2 $12" + details: + mos65xx: + am: MOS65XX_AM_ZP + modifies_flags: -1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "smb4 $12" + details: + mos65xx: + am: MOS65XX_AM_ZP + modifies_flags: -1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "smb6 $12" + details: + mos65xx: + am: MOS65XX_AM_ZP + modifies_flags: -1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "bpl $1010" + details: + mos65xx: + am: MOS65XX_AM_REL + modifies_flags: -1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x1010 + - + asm_text: "bbr0 $12, $1012" + details: + mos65xx: + am: MOS65XX_AM_ZP_REL + modifies_flags: -1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + type: MOS65XX_OP_MEM + mem: 0x1012 + - + asm_text: "bbr4 $12, $1015" + details: + mos65xx: + am: MOS65XX_AM_ZP_REL + modifies_flags: -1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + type: MOS65XX_OP_MEM + mem: 0x1015 + - + asm_text: "bbs0 $12, $1018" + details: + mos65xx: + am: MOS65XX_AM_ZP_REL + modifies_flags: -1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + type: MOS65XX_OP_MEM + mem: 0x1018 + - + asm_text: "bbs4 $12, $101b" + details: + mos65xx: + am: MOS65XX_AM_ZP_REL + modifies_flags: -1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + type: MOS65XX_OP_MEM + mem: 0x101b + - + input: + bytes: [ 0xa9, 0x34, 0x12, 0xad, 0x34, 0x12, 0xbd, 0x34, 0x12, 0xb9, 0x34, 0x12, 0xaf, 0x56, 0x34, 0x12, 0xbf, 0x56, 0x34, 0x12, 0xa5, 0x12, 0xb5, 0x12, 0xb2, 0x12, 0xa1, 0x12, 0xb1, 0x12, 0xa7, 0x12, 0xb7, 0x12, 0xa3, 0x12, 0xb3, 0x12, 0xc2, 0x00, 0xe2, 0x00, 0x54, 0x34, 0x12, 0x44, 0x34, 0x12, 0x02, 0x12 ] + arch: "mos65xx" + options: [ CS_OPT_DETAIL, CS_MODE_MOS65XX_65816_LONG_MX, CS_OPT_SYNTAX_MOTOROLA ] + address: 0x1000 + expected: + insns: + - + asm_text: "lda #$1234" + details: + mos65xx: + am: MOS65XX_AM_IMM + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_IMM + imm: 0x1234 + - + asm_text: "lda $1234" + details: + mos65xx: + am: MOS65XX_AM_ABS + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x1234 + - + asm_text: "lda $1234, x" + details: + mos65xx: + am: MOS65XX_AM_ABS_X + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x1234 + - + asm_text: "lda $1234, y" + details: + mos65xx: + am: MOS65XX_AM_ABS_Y + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x1234 + - + asm_text: "lda $123456" + details: + mos65xx: + am: MOS65XX_AM_ABS_LONG + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x123456 + - + asm_text: "lda $123456, x" + details: + mos65xx: + am: MOS65XX_AM_ABS_LONG_X + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x123456 + - + asm_text: "lda $12" + details: + mos65xx: + am: MOS65XX_AM_ZP + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "lda $12, x" + details: + mos65xx: + am: MOS65XX_AM_ZP_X + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "lda ($12)" + details: + mos65xx: + am: MOS65XX_AM_ZP_IND + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "lda ($12, x)" + details: + mos65xx: + am: MOS65XX_AM_ZP_X_IND + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "lda ($12), y" + details: + mos65xx: + am: MOS65XX_AM_ZP_IND_Y + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "lda [$12]" + details: + mos65xx: + am: MOS65XX_AM_ZP_IND_LONG + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "lda [$12], y" + details: + mos65xx: + am: MOS65XX_AM_ZP_IND_LONG_Y + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "lda $12, s" + details: + mos65xx: + am: MOS65XX_AM_SR + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "lda ($12, s), y" + details: + mos65xx: + am: MOS65XX_AM_SR_IND_Y + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + asm_text: "rep #$00" + details: + mos65xx: + am: MOS65XX_AM_IMM + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_IMM + imm: 0x0 + - + asm_text: "sep #$00" + details: + mos65xx: + am: MOS65XX_AM_IMM + modifies_flags: 1 + operands: + - + type: MOS65XX_OP_IMM + imm: 0x0 + - + asm_text: "mvn $12, $34" + details: + mos65xx: + am: MOS65XX_AM_BLOCK + modifies_flags: -1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + type: MOS65XX_OP_MEM + mem: 0x34 + - + asm_text: "mvp $12, $34" + details: + mos65xx: + am: MOS65XX_AM_BLOCK + modifies_flags: -1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + - + type: MOS65XX_OP_MEM + mem: 0x34 + - + asm_text: "cop $12" + details: + mos65xx: + am: MOS65XX_AM_INT + modifies_flags: -1 + operands: + - + type: MOS65XX_OP_MEM + mem: 0x12 + diff --git a/tests/details/ppc.yaml b/tests/details/ppc.yaml new file mode 100644 index 0000000000..079f06ef6a --- /dev/null +++ b/tests/details/ppc.yaml @@ -0,0 +1,1498 @@ +test_cases: + - + input: + bytes: [ 0x43, 0x20, 0x0c, 0x07, 0x41, 0x56, 0xff, 0x17, 0x80, 0x20, 0x00, 0x00, 0x80, 0x3f, 0x00, 0x00, 0x10, 0x43, 0x23, 0x0e, 0xd0, 0x44, 0x00, 0x80, 0x4c, 0x43, 0x22, 0x02, 0x2d, 0x03, 0x00, 0x80, 0x7c, 0x43, 0x20, 0x14, 0x7c, 0x43, 0x20, 0x93, 0x4f, 0x20, 0x00, 0x21, 0x4c, 0xc8, 0x00, 0x21, 0x40, 0x82, 0x00, 0x14 ] + arch: "ppc" + options: [ CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ] + address: 0x1000 + expected: + insns: + - + asm_text: "bcla 0x19, lt, 0xc04" + details: + ppc: + operands: + - + type: PPC_OP_IMM + imm: 0x19 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: "0" + access: CS_AC_READ + - + type: PPC_OP_IMM + imm: 0xc04 + access: CS_AC_READ + bc: + bi: 0 + bi_set: true + bo: 25 + bo_set: true + pred_ctr: PPC_PRED_NZ + - + asm_text: "bdztla 4*cr5+eq, 0xff14" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: "22" + access: CS_AC_READ + - + type: PPC_OP_IMM + imm: 0xff14 + access: CS_AC_READ + bc: + bi: 22 + bi_set: true + bo: 10 + bo_set: true + crX: cr5 + crX_bit: PPC_BI_Z + pred_ctr: PPC_PRED_Z + - + asm_text: "lwz r1, 0(0)" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: r1 + access: CS_AC_WRITE + - + type: PPC_OP_MEM + mem_base: "0" + access: CS_AC_READ + - + asm_text: "lwz r1, 0(r31)" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: r1 + access: CS_AC_WRITE + - + type: PPC_OP_MEM + mem_base: r31 + access: CS_AC_READ + - + asm_text: "vpkpx v2, v3, v4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: v2 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: v3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: v4 + access: CS_AC_READ + - + asm_text: "stfs f2, 0x80(r4)" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f2 + access: CS_AC_READ + - + type: PPC_OP_MEM + mem_base: r4 + mem_disp: 0x80 + access: CS_AC_WRITE + - + asm_text: "crand eq, un, 4*cr1+lt" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: "2" + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: "3" + access: CS_AC_READ + - + type: PPC_OP_REG + reg: "4" + access: CS_AC_READ + - + asm_text: "cmpwi cr2, r3, 0x80" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: cr2 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: r3 + access: CS_AC_READ + - + type: PPC_OP_IMM + imm: 0x80 + access: CS_AC_READ + - + asm_text: "addc r2, r3, r4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: r2 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: r3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: r4 + access: CS_AC_READ + - + asm_text: "mulhd. r2, r3, r4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: r2 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: r3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: r4 + access: CS_AC_READ + update_cr0: 1 + - + asm_text: "bdnzlrl+" + details: + ppc: + bc: + bi: 0 + bi_set: true + bo: 25 + bo_set: true + bh: PPC_BH_SUBROUTINE_RET + pred_ctr: PPC_PRED_NZ + hint: PPC_BR_TAKEN + - + asm_text: "bflrl- 4*cr2+lt" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: "8" + access: CS_AC_READ + bc: + bi: 8 + bi_set: true + bo: 6 + bo_set: true + bh: PPC_BH_SUBROUTINE_RET + crX: cr2 + crX_bit: PPC_BI_LT + hint: PPC_BR_NOT_TAKEN + - + asm_text: "bf eq, 0x1044" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: "2" + access: CS_AC_READ + - + type: PPC_OP_IMM + imm: 0x1044 + access: CS_AC_READ + bc: + bi: 2 + bi_set: true + bo: 4 + bo_set: true + crX: cr0 + crX_bit: PPC_BI_Z + - + input: + bytes: [ 0x10, 0x60, 0x2a, 0x10, 0x10, 0x64, 0x28, 0x88, 0x7c, 0x4a, 0x5d, 0x0f ] + arch: "ppc" + options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN, CS_MODE_QPX, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "qvfabs q3, q5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: q3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: q5 + access: CS_AC_READ + - + asm_text: "qvfand q3, q4, q5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: q3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: q4 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: q5 + access: CS_AC_READ + - + asm_text: "qvstfsxa q2, r10, r11" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: q2 + access: CS_AC_READ + - + type: PPC_OP_MEM + mem_base: r10 + mem_offset: r11 + access: CS_AC_WRITE + - + input: + bytes: [ 0x10, 0x00, 0x1f, 0xec, 0xe0, 0x6d, 0x80, 0x04, 0xe4, 0x6d, 0x80, 0x04, 0x10, 0x60, 0x1c, 0x4c, 0x10, 0x60, 0x1c, 0x0c, 0xf0, 0x6d, 0x80, 0x04, 0xf4, 0x6d, 0x80, 0x04, 0x10, 0x60, 0x1c, 0x4e, 0x10, 0x60, 0x1c, 0x0e, 0x10, 0x60, 0x1a, 0x10, 0x10, 0x60, 0x1a, 0x11, 0x10, 0x63, 0x20, 0x2a, 0x10, 0x63, 0x20, 0x2b, 0x10, 0x83, 0x20, 0x40, 0x10, 0x83, 0x20, 0xc0, 0x10, 0x83, 0x20, 0x00, 0x10, 0x83, 0x20, 0x80, 0x10, 0x63, 0x20, 0x24, 0x10, 0x63, 0x20, 0x25, 0x10, 0x63, 0x29, 0x3a, 0x10, 0x63, 0x29, 0x3b, 0x10, 0x63, 0x29, 0x1c, 0x10, 0x63, 0x29, 0x1d, 0x10, 0x63, 0x29, 0x1e, 0x10, 0x63, 0x29, 0x1f, 0x10, 0x63, 0x24, 0x20, 0x10, 0x63, 0x24, 0x21, 0x10, 0x63, 0x24, 0x60, 0x10, 0x63, 0x24, 0x61, 0x10, 0x63, 0x24, 0xa0, 0x10, 0x63, 0x24, 0xa1, 0x10, 0x63, 0x24, 0xe0, 0x10, 0x63, 0x24, 0xe1, 0x10, 0x60, 0x20, 0x90, 0x10, 0x60, 0x20, 0x91, 0x10, 0x63, 0x29, 0x38, 0x10, 0x63, 0x29, 0x39, 0x10, 0x63, 0x01, 0x32, 0x10, 0x63, 0x01, 0x33, 0x10, 0x63, 0x01, 0x18, 0x10, 0x63, 0x01, 0x19, 0x10, 0x63, 0x01, 0x1a, 0x10, 0x63, 0x01, 0x1b, 0x10, 0x60, 0x19, 0x10, 0x10, 0x60, 0x19, 0x11, 0x10, 0x60, 0x18, 0x50, 0x10, 0x60, 0x18, 0x51, 0x10, 0x63, 0x29, 0x3e, 0x10, 0x63, 0x29, 0x3f, 0x10, 0x63, 0x29, 0x3c, 0x10, 0x63, 0x29, 0x3d, 0x10, 0x60, 0x18, 0x30, 0x10, 0x60, 0x18, 0x31, 0x10, 0x60, 0x18, 0x34, 0x10, 0x60, 0x18, 0x35, 0x10, 0x63, 0x29, 0x2e, 0x10, 0x63, 0x29, 0x2f, 0x10, 0x63, 0x20, 0x28, 0x10, 0x63, 0x20, 0x29, 0x10, 0x63, 0x29, 0x14, 0x10, 0x63, 0x29, 0x15, 0x10, 0x63, 0x29, 0x16, 0x10, 0x63, 0x29, 0x17 ] + arch: "ppc" + options: [ CS_MODE_BIG_ENDIAN, CS_MODE_PS, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "dcbz_l r0, r3" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: r0 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: r3 + access: CS_AC_READ + - + asm_text: "psq_l f3, 4(r13), 1, 0" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_MEM + mem_base: r13 + mem_disp: 0x4 + access: CS_AC_READ + - + type: PPC_OP_IMM + imm: 0x1 + access: CS_AC_READ + - + type: PPC_OP_IMM + imm: 0x0 + access: CS_AC_READ + - + asm_text: "psq_lu f3, 4(r13), 1, 0" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_MEM + mem_base: r13 + mem_disp: 0x4 + access: CS_AC_READ + - + type: PPC_OP_IMM + imm: 0x1 + access: CS_AC_READ + - + type: PPC_OP_IMM + imm: 0x0 + access: CS_AC_READ + - + asm_text: "psq_lux f3, r0, r3, 1, 0" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: r0 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: r3 + access: CS_AC_READ + - + type: PPC_OP_IMM + imm: 0x1 + access: CS_AC_READ + - + type: PPC_OP_IMM + imm: 0x0 + access: CS_AC_READ + - + asm_text: "psq_lx f3, r0, r3, 1, 0" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: r0 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: r3 + access: CS_AC_READ + - + type: PPC_OP_IMM + imm: 0x1 + access: CS_AC_READ + - + type: PPC_OP_IMM + imm: 0x0 + access: CS_AC_READ + - + asm_text: "psq_st f3, 4(r13), 1, 0" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_MEM + mem_base: r13 + mem_disp: 0x4 + access: CS_AC_WRITE + - + type: PPC_OP_IMM + imm: 0x1 + access: CS_AC_READ + - + type: PPC_OP_IMM + imm: 0x0 + access: CS_AC_READ + - + asm_text: "psq_stu f3, 4(r13), 1, 0" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_MEM + mem_base: r13 + mem_disp: 0x4 + access: CS_AC_WRITE + - + type: PPC_OP_IMM + imm: 0x1 + access: CS_AC_READ + - + type: PPC_OP_IMM + imm: 0x0 + access: CS_AC_READ + - + asm_text: "psq_stux f3, r0, r3, 1, 0" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: r0 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: r3 + access: CS_AC_READ + - + type: PPC_OP_IMM + imm: 0x1 + access: CS_AC_READ + - + type: PPC_OP_IMM + imm: 0x0 + access: CS_AC_READ + - + asm_text: "psq_stx f3, r0, r3, 1, 0" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: r0 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: r3 + access: CS_AC_READ + - + type: PPC_OP_IMM + imm: 0x1 + access: CS_AC_READ + - + type: PPC_OP_IMM + imm: 0x0 + access: CS_AC_READ + - + asm_text: "ps_abs f3, f3" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + asm_text: "ps_abs. f3, f3" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + asm_text: "ps_add f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_add. f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_cmpo0 cr1, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: cr1 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_cmpo1 cr1, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: cr1 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_cmpu0 cr1, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: cr1 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_cmpu1 cr1, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: cr1 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_div f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_div. f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_madd f3, f3, f4, f5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f5 + access: CS_AC_READ + - + asm_text: "ps_madd. f3, f3, f4, f5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f5 + access: CS_AC_READ + - + asm_text: "ps_madds0 f3, f3, f4, f5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f5 + access: CS_AC_READ + - + asm_text: "ps_madds0. f3, f3, f4, f5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f5 + access: CS_AC_READ + - + asm_text: "ps_madds1 f3, f3, f4, f5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f5 + access: CS_AC_READ + - + asm_text: "ps_madds1. f3, f3, f4, f5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f5 + access: CS_AC_READ + - + asm_text: "ps_merge00 f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_merge00. f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_merge01 f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_merge01. f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_merge10 f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_merge10. f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_merge11 f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_merge11. f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_mr f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_mr. f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_msub f3, f3, f4, f5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f5 + access: CS_AC_READ + - + asm_text: "ps_msub. f3, f3, f4, f5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f5 + access: CS_AC_READ + - + asm_text: "ps_mul f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_mul. f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_muls0 f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_muls0. f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_muls1 f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_muls1. f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_nabs f3, f3" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + asm_text: "ps_nabs. f3, f3" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + asm_text: "ps_neg f3, f3" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + asm_text: "ps_neg. f3, f3" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + asm_text: "ps_nmadd f3, f3, f4, f5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f5 + access: CS_AC_READ + - + asm_text: "ps_nmadd. f3, f3, f4, f5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f5 + access: CS_AC_READ + - + asm_text: "ps_nmsub f3, f3, f4, f5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f5 + access: CS_AC_READ + - + asm_text: "ps_nmsub. f3, f3, f4, f5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f5 + access: CS_AC_READ + - + asm_text: "ps_res f3, f3" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + asm_text: "ps_res. f3, f3" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + asm_text: "ps_rsqrte f3, f3" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + asm_text: "ps_rsqrte. f3, f3" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + asm_text: "ps_sel f3, f3, f4, f5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f5 + access: CS_AC_READ + - + asm_text: "ps_sel. f3, f3, f4, f5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f5 + access: CS_AC_READ + - + asm_text: "ps_sub f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_sub. f3, f3, f4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + asm_text: "ps_sum0 f3, f3, f4, f5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f5 + access: CS_AC_READ + - + asm_text: "ps_sum0. f3, f3, f4, f5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f5 + access: CS_AC_READ + - + asm_text: "ps_sum1 f3, f3, f4, f5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f5 + access: CS_AC_READ + - + asm_text: "ps_sum1. f3, f3, f4, f5" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_WRITE + - + type: PPC_OP_REG + reg: f3 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f4 + access: CS_AC_READ + - + type: PPC_OP_REG + reg: f5 + access: CS_AC_READ + - + input: + bytes: [ 0x54,0x22,0xe0,0x06 ] + arch: "CS_ARCH_PPC" + options: [ CS_MODE_32, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "slwi r2, r1, 0x1c" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: r2 + - + type: PPC_OP_REG + reg: r1 + - + type: PPC_OP_IMM + imm: 0x1c + - + input: + bytes: [ 0x54,0x66,0xf0,0xbe ] + arch: "CS_ARCH_PPC" + options: [ CS_MODE_32, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "srwi r6, r3, 2" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: r6 + - + type: PPC_OP_REG + reg: r3 + - + type: PPC_OP_IMM + imm: 0x2 + - + input: + bytes: [ 0x78,0x62,0x26,0xe4 ] + arch: "CS_ARCH_PPC" + options: [ CS_MODE_32, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "sldi r2, r3, 4" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: r2 + - + type: PPC_OP_REG + reg: r3 + - + type: PPC_OP_IMM + imm: 0x4 diff --git a/tests/details/riscv.yaml b/tests/details/riscv.yaml new file mode 100644 index 0000000000..9bd6be20f7 --- /dev/null +++ b/tests/details/riscv.yaml @@ -0,0 +1,4049 @@ +test_cases: + - + input: + bytes: [ 0x37, 0x34, 0x00, 0x00, 0x97, 0x82, 0x00, 0x00, 0xef, 0x00, 0x80, 0x00, 0xef, 0xf0, 0x1f, 0xff, 0xe7, 0x00, 0x45, 0x00, 0xe7, 0x00, 0xc0, 0xff, 0x63, 0x05, 0x41, 0x00, 0xe3, 0x9d, 0x61, 0xfe, 0x63, 0xca, 0x93, 0x00, 0x63, 0x53, 0xb5, 0x00, 0x63, 0x65, 0xd6, 0x00, 0x63, 0x76, 0xf7, 0x00, 0x03, 0x88, 0x18, 0x00, 0x03, 0x99, 0x49, 0x00, 0x03, 0xaa, 0x6a, 0x00, 0x03, 0xcb, 0x2b, 0x01, 0x03, 0xdc, 0x8c, 0x01, 0x23, 0x86, 0xad, 0x03, 0x23, 0x9a, 0xce, 0x03, 0x23, 0x8f, 0xef, 0x01, 0x93, 0x00, 0xe0, 0x00, 0x13, 0xa1, 0x01, 0x01, 0x13, 0xb2, 0x02, 0x7d, 0x13, 0xc3, 0x03, 0xdd, 0x13, 0xe4, 0xc4, 0x12, 0x13, 0xf5, 0x85, 0x0c, 0x13, 0x96, 0xe6, 0x01, 0x13, 0xd7, 0x97, 0x01, 0x13, 0xd8, 0xf8, 0x40, 0x33, 0x89, 0x49, 0x01, 0xb3, 0x0a, 0x7b, 0x41, 0x33, 0xac, 0xac, 0x01, 0xb3, 0x3d, 0xde, 0x01, 0x33, 0xd2, 0x62, 0x40, 0xb3, 0x43, 0x94, 0x00, 0x33, 0xe5, 0xc5, 0x00, 0xb3, 0x76, 0xf7, 0x00, 0xb3, 0x54, 0x39, 0x01, 0xb3, 0x50, 0x31, 0x00, 0x33, 0x9f, 0x0f, 0x00, 0x73, 0x15, 0x04, 0xb0, 0xf3, 0x56, 0x00, 0x10, 0x33, 0x05, 0x7b, 0x03, 0xb3, 0x45, 0x9c, 0x03, 0x33, 0x66, 0xbd, 0x03, 0x2f, 0xa4, 0x02, 0x10, 0xaf, 0x23, 0x65, 0x18, 0x2f, 0x27, 0x2f, 0x01, 0x43, 0xf0, 0x20, 0x18, 0xd3, 0x72, 0x73, 0x00, 0x53, 0xf4, 0x04, 0x58, 0x53, 0x85, 0xc5, 0x28, 0x53, 0x2e, 0xde, 0xa1, 0xd3, 0x84, 0x05, 0xf0, 0x53, 0x06, 0x05, 0xe0, 0x53, 0x75, 0x00, 0xc0, 0xd3, 0xf0, 0x05, 0xd0, 0xd3, 0x15, 0x08, 0xe0, 0x87, 0xaa, 0x75, 0x00, 0x27, 0x27, 0x66, 0x01, 0x43, 0xf0, 0x20, 0x1a, 0xd3, 0x72, 0x73, 0x02, 0x53, 0xf4, 0x04, 0x5a, 0x53, 0x85, 0xc5, 0x2a, 0x53, 0x2e, 0xde, 0xa3 ] + arch: "riscv" + options: [ CS_OPT_DETAIL, CS_MODE_RISCV32 ] + address: 0x1000 + expected: + insns: + - + asm_text: "lui s0, 3" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_WRITE + - + type: RISCV_OP_IMM + imm: 0x3 + access: CS_AC_READ + - + asm_text: "auipc t0, 8" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t0 + access: CS_AC_WRITE + - + type: RISCV_OP_IMM + imm: 0x8 + access: CS_AC_READ + - + asm_text: "jal 8" + details: + riscv: + operands: + - + type: RISCV_OP_IMM + imm: 0x8 + access: CS_AC_READ + groups: [ RISCV_GRP_CALL ] + - + asm_text: "jal -0x10" + details: + riscv: + operands: + - + type: RISCV_OP_IMM + imm: -0x10 + access: CS_AC_READ + groups: [ RISCV_GRP_CALL ] + - + asm_text: "jalr ra, a0, 4" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ra + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x4 + access: CS_AC_READ + groups: [ RISCV_GRP_CALL ] + - + asm_text: "jalr ra, zero, -4" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ra + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: zero + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: -4 + access: CS_AC_READ + groups: [ RISCV_GRP_CALL ] + - + asm_text: "beq sp, tp, 0xa" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: tp + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xa + access: CS_AC_READ + groups: [ RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ] + - + asm_text: "bne gp, t1, -6" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: gp + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: -6 + access: CS_AC_READ + groups: [ RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ] + - + asm_text: "blt t2, s1, 0x14" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t2 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x14 + access: CS_AC_READ + groups: [ RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ] + - + asm_text: "bge a0, a1, 6" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x6 + access: CS_AC_READ + groups: [ RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ] + - + asm_text: "bltu a2, a3, 0xa" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: a3 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xa + access: CS_AC_READ + groups: [ RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ] + - + asm_text: "bgeu a4, a5, 0xc" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a4 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: a5 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xc + access: CS_AC_READ + groups: [ RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ] + - + asm_text: "lb a6, 1(a7)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a6 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: a7 + mem_disp: 0x1 + access: CS_AC_READ + - + asm_text: "lh s2, 4(s3)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s2 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: s3 + mem_disp: 0x4 + access: CS_AC_READ + - + asm_text: "lw s4, 6(s5)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s4 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: s5 + mem_disp: 0x6 + access: CS_AC_READ + - + asm_text: "lbu s6, 0x12(s7)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s6 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: s7 + mem_disp: 0x12 + access: CS_AC_READ + - + asm_text: "lhu s8, 0x18(s9)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s8 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: s9 + mem_disp: 0x18 + access: CS_AC_READ + - + asm_text: "sb s10, 0x2c(s11)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s10 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: s11 + mem_disp: 0x2c + access: CS_AC_WRITE + - + asm_text: "sh t3, 0x34(t4)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t3 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: t4 + mem_disp: 0x34 + access: CS_AC_WRITE + - + asm_text: "sb t5, 0x1e(t6)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t5 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: t6 + mem_disp: 0x1e + access: CS_AC_WRITE + - + asm_text: "addi ra, zero, 0xe" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ra + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: zero + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xe + access: CS_AC_READ + - + asm_text: "slti sp, gp, 0x10" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: gp + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x10 + access: CS_AC_READ + - + asm_text: "sltiu tp, t0, 0x7d0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: tp + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t0 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x7d0 + access: CS_AC_READ + - + asm_text: "xori t1, t2, -0x230" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t2 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: -0x230 + access: CS_AC_READ + - + asm_text: "ori s0, s1, 0x12c" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x12c + access: CS_AC_READ + - + asm_text: "andi a0, a1, 0xc8" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xc8 + access: CS_AC_READ + - + asm_text: "slli a2, a3, 0x1e" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a3 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x1e + access: CS_AC_READ + - + asm_text: "srli a4, a5, 0x19" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a4 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a5 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x19 + access: CS_AC_READ + - + asm_text: "srai a6, a7, 0xf" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a6 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a7 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xf + access: CS_AC_READ + - + asm_text: "add s2, s3, s4" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s3 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s4 + access: CS_AC_READ + - + asm_text: "sub s5, s6, s7" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s5 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s6 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s7 + access: CS_AC_READ + - + asm_text: "slt s8, s9, s10" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s8 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s9 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s10 + access: CS_AC_READ + - + asm_text: "sltu s11, t3, t4" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s11 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t3 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: t4 + access: CS_AC_READ + - + asm_text: "sra tp, t0, t1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: tp + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t0 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_READ + - + asm_text: "xor t2, s0, s1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_READ + - + asm_text: "or a0, a1, a2" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_READ + - + asm_text: "and a3, a4, a5" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a3 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a4 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: a5 + access: CS_AC_READ + - + asm_text: "srl s1, s2, s3" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s2 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s3 + access: CS_AC_READ + - + asm_text: "srl ra, sp, gp" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ra + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: gp + access: CS_AC_READ + - + asm_text: "sll t5, t6, zero" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t5 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t6 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: zero + access: CS_AC_READ + - + asm_text: "csrrw a0, mcycle, s0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_READ + - + asm_text: "csrrwi a3, sstatus, 0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a3 + access: CS_AC_WRITE + - + type: RISCV_OP_IMM + imm: 0x0 + access: CS_AC_READ + - + asm_text: "mul a0, s6, s7" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s6 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s7 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTM ] + - + asm_text: "div a1, s8, s9" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s8 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s9 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTM ] + - + asm_text: "rem a2, s10, s11" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s10 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s11 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTM ] + - + asm_text: "lr.w s0, (t0)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: t0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTA ] + - + asm_text: "sc.w t2, t1, (a0)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: a0 + access: CS_AC_WRITE + groups: [ RISCV_GRP_HASSTDEXTA ] + - + asm_text: "amoadd.w a4, s2, (t5)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a4 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s2 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: t5 + access: CS_AC_READ_WRITE + groups: [ RISCV_GRP_HASSTDEXTA ] + - + asm_text: "fmadd.s ft0, ft1, ft2, ft3" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft1 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft2 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft3 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fadd.s ft5, ft6, ft7" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft5 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft6 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft7 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fsqrt.s fs0, fs1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fs1 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fmin.s fa0, fa1, fa2" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fa1 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: fa2 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "feq.s t3, ft8, ft9" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t3 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft8 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft9 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fmv.w.x fs1, a1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fmv.x.w a2, fa0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fcvt.w.s a0, ft0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fcvt.s.w ft1, a1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fclass.s a1, fa6" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fa6 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "flw fs5, 7(a1)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs5 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: a1 + mem_disp: 0x7 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fsw fs6, 0xe(a2)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs6 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: a2 + mem_disp: 0xe + access: CS_AC_WRITE + groups: [ RISCV_GRP_HASSTDEXTF ] + - + asm_text: "fmadd.d ft0, ft1, ft2, ft3" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft1 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft2 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft3 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD ] + - + asm_text: "fadd.d ft5, ft6, ft7" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft5 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft6 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft7 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD ] + - + asm_text: "fsqrt.d fs0, fs1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fs1 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD ] + - + asm_text: "fmin.d fa0, fa1, fa2" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fa1 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: fa2 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD ] + - + asm_text: "feq.d t3, ft8, ft9" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t3 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft8 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft9 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD ] + - + input: + bytes: [ 0x13, 0x04, 0xa8, 0x7a, 0xbb, 0x07, 0x9c, 0x02, 0xbb, 0x40, 0x5d, 0x02, 0x3b, 0x63, 0xb7, 0x03, 0x2f, 0xb4, 0x02, 0x10, 0xaf, 0x33, 0x65, 0x18, 0x2f, 0x37, 0x2f, 0x01, 0x53, 0x75, 0x20, 0xc0, 0xd3, 0xf0, 0x25, 0xd0, 0xd3, 0x84, 0x05, 0xf2, 0x53, 0x06, 0x05, 0xe2, 0x53, 0x75, 0x00, 0xc2, 0xd3, 0x80, 0x05, 0xd2, 0xd3, 0x15, 0x08, 0xe2, 0x87, 0xba, 0x75, 0x00, 0x27, 0x37, 0x66, 0x01 ] + arch: "riscv" + options: [ CS_OPT_DETAIL, CS_MODE_RISCV64 ] + address: 0x1000 + expected: + insns: + - + asm_text: "addi s0, a6, 0x7aa" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a6 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x7aa + access: CS_AC_READ + - + asm_text: "mulw a5, s8, s1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a5 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s8 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64 ] + - + asm_text: "divw ra, s10, t0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ra + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s10 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: t0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64 ] + - + asm_text: "remw t1, a4, s11" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a4 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s11 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64 ] + - + asm_text: "lr.d s0, (t0)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: t0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64 ] + - + asm_text: "sc.d t2, t1, (a0)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: a0 + access: CS_AC_WRITE + groups: [ RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64 ] + - + asm_text: "amoadd.d a4, s2, (t5)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a4 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s2 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: t5 + access: CS_AC_READ_WRITE + groups: [ RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64 ] + - + asm_text: "fcvt.l.s a0, ft0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64 ] + - + asm_text: "fcvt.s.l ft1, a1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64 ] + - + asm_text: "fmv.d.x fs1, a1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64 ] + - + asm_text: "fmv.x.d a2, fa0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64 ] + - + asm_text: "fcvt.w.d a0, ft0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD ] + - + asm_text: "fcvt.d.w ft1, a1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD ] + - + asm_text: "fclass.d a1, fa6" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fa6 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD ] + - + asm_text: "fld fs5, 7(a1)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs5 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: a1 + mem_disp: 0x7 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTD ] + - + asm_text: "fsd fs6, 0xe(a2)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs6 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: a2 + mem_disp: 0xe + access: CS_AC_WRITE + groups: [ RISCV_GRP_HASSTDEXTD ] + - + input: + bytes: [ 0xe8, 0x1f, 0x7d, 0x61, 0x80, 0x25, 0x00, 0x46, 0x88, 0xa2, 0x04, 0xcb, 0x55, 0x13, 0xf2, 0x93, 0x5d, 0x45, 0x19, 0x80, 0x15, 0x68, 0x2a, 0xa4, 0x62, 0x24, 0xa6, 0xff, 0x2a, 0x65, 0x76, 0x86, 0x65, 0xdd, 0x01, 0x00, 0xfd, 0xaf, 0x82, 0x82, 0x11, 0x20, 0x82, 0x94 ] + arch: "riscv" + options: [ CS_OPT_DETAIL, CS_MODE_RISCVC ] + address: 0x1000 + expected: + insns: + - + asm_text: "c.addi4spn a0, sp, 0x3fc" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x3fc + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.addi16sp sp, 0x1f0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_READ_WRITE + - + type: RISCV_OP_IMM + imm: 0x1f0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.fld fs0, 8(a1)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs0 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: a1 + mem_disp: 0x8 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD ] + - + asm_text: "c.lw s0, 8(a2)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: a2 + mem_disp: 0x8 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.fsd fa0, 0(a3)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: a3 + access: CS_AC_WRITE + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD ] + - + asm_text: "c.sw s1, 0x10(a4)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: a4 + mem_disp: 0x10 + access: CS_AC_WRITE + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.addi t1, -0xb" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_READ_WRITE + - + type: RISCV_OP_IMM + imm: -0xb + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.add t2, t3" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t2 + access: CS_AC_READ_WRITE + - + type: RISCV_OP_REG + reg: t3 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.li a0, 0x17" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_IMM + imm: 0x17 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.srli s0, 6" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_READ_WRITE + - + type: RISCV_OP_IMM + imm: 0x6 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.lui a6, 5" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a6 + access: CS_AC_WRITE + - + type: RISCV_OP_IMM + imm: 0x5 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.fsdsp fa0, 8(sp)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: sp + mem_disp: 0x8 + access: CS_AC_WRITE + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD ] + - + asm_text: "c.fldsp fs0, 0x18(sp)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs0 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: sp + mem_disp: 0x18 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD ] + - + asm_text: "c.fswsp fs1, 0xfc(sp)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs1 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xfc + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_WRITE + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32 ] + - + asm_text: "c.flwsp fa0, 0x88(sp)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_WRITE + - + type: RISCV_OP_IMM + imm: 0x88 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32 ] + - + asm_text: "c.mv a2, t4" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t4 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.beqz a0, -8" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: -8 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ] + - + asm_text: "c.nop" + details: + groups: [ RISCV_GRP_HASSTDEXTC ] + - + asm_text: "c.j 0x7fe" + details: + riscv: + operands: + - + type: RISCV_OP_IMM + imm: 0x7fe + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_JUMP ] + - + asm_text: "c.jr t0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t0 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_JUMP ] + - + asm_text: "c.jal 4" + details: + riscv: + operands: + - + type: RISCV_OP_IMM + imm: 0x4 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV32, RISCV_GRP_CALL ] + - + asm_text: "c.jalr s1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_READ + groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_CALL ] + - + input: + bytes: [ 0x37,0x34,0x00,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "lui s0, 3" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_WRITE + - + type: RISCV_OP_IMM + imm: 0x3 + access: CS_AC_READ + - + input: + bytes: [ 0x97,0x82,0x00,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "auipc t0, 8" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t0 + access: CS_AC_WRITE + - + type: RISCV_OP_IMM + imm: 0x8 + access: CS_AC_READ + - + input: + bytes: [ 0xef,0x00,0x80,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "jal 8" + details: + riscv: + operands: + - + type: RISCV_OP_IMM + imm: 0x8 + access: CS_AC_READ + groups: [ call ] + - + input: + bytes: [ 0xef,0xf0,0x1f,0xff ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "jal -0x10" + details: + riscv: + operands: + - + type: RISCV_OP_IMM + imm: -0x10 + access: CS_AC_READ + groups: [ call ] + - + input: + bytes: [ 0xe7,0x00,0x45,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "jalr ra, a0, 4" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ra + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x4 + access: CS_AC_READ + groups: [ call ] + - + input: + bytes: [ 0xe7,0x00,0xc0,0xff ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "jalr ra, zero, -4" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ra + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: zero + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: -4 + access: CS_AC_READ + groups: [ call ] + - + input: + bytes: [ 0x63,0x05,0x41,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "beq sp, tp, 0xa" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: tp + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xa + access: CS_AC_READ + groups: [ branch_relative, jump ] + - + input: + bytes: [ 0xe3,0x9d,0x61,0xfe ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "bne gp, t1, -6" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: gp + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: -6 + access: CS_AC_READ + groups: [ branch_relative, jump ] + - + input: + bytes: [ 0x63,0xca,0x93,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "blt t2, s1, 0x14" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t2 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x14 + access: CS_AC_READ + groups: [ branch_relative, jump ] + - + input: + bytes: [ 0x63,0x53,0xb5,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "bge a0, a1, 6" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x6 + access: CS_AC_READ + groups: [ branch_relative, jump ] + - + input: + bytes: [ 0x63,0x65,0xd6,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "bltu a2, a3, 0xa" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: a3 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xa + access: CS_AC_READ + groups: [ branch_relative, jump ] + - + input: + bytes: [ 0x63,0x76,0xf7,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "bgeu a4, a5, 0xc" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a4 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: a5 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xc + access: CS_AC_READ + groups: [ branch_relative, jump ] + - + input: + bytes: [ 0x03,0x88,0x18,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "lb a6, 1(a7)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a6 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: a7 + mem_disp: 0x1 + access: CS_AC_READ + - + input: + bytes: [ 0x03,0x99,0x49,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "lh s2, 4(s3)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s2 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: s3 + mem_disp: 0x4 + access: CS_AC_READ + - + input: + bytes: [ 0x03,0xaa,0x6a,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "lw s4, 6(s5)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s4 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: s5 + mem_disp: 0x6 + access: CS_AC_READ + - + input: + bytes: [ 0x03,0xcb,0x2b,0x01 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "lbu s6, 0x12(s7)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s6 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: s7 + mem_disp: 0x12 + access: CS_AC_READ + - + input: + bytes: [ 0x03,0xdc,0x8c,0x01 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "lhu s8, 0x18(s9)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s8 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: s9 + mem_disp: 0x18 + access: CS_AC_READ + - + input: + bytes: [ 0x23,0x86,0xad,0x03 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "sb s10, 0x2c(s11)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s10 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: s11 + mem_disp: 0x2c + access: CS_AC_WRITE + - + input: + bytes: [ 0x23,0x9a,0xce,0x03 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "sh t3, 0x34(t4)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t3 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: t4 + mem_disp: 0x34 + access: CS_AC_WRITE + - + input: + bytes: [ 0x23,0x8f,0xef,0x01 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "sb t5, 0x1e(t6)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t5 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: t6 + mem_disp: 0x1e + access: CS_AC_WRITE + - + input: + bytes: [ 0x93,0x00,0xe0,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "addi ra, zero, 0xe" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ra + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: zero + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xe + access: CS_AC_READ + - + input: + bytes: [ 0x13,0xa1,0x01,0x01 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "slti sp, gp, 0x10" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: gp + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x10 + access: CS_AC_READ + - + input: + bytes: [ 0x13,0xb2,0x02,0x7d ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "sltiu tp, t0, 0x7d0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: tp + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t0 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x7d0 + access: CS_AC_READ + - + input: + bytes: [ 0x13,0xc3,0x03,0xdd ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "xori t1, t2, -0x230" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t2 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: -0x230 + access: CS_AC_READ + - + input: + bytes: [ 0x13,0xe4,0xc4,0x12 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ori s0, s1, 0x12c" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x12c + access: CS_AC_READ + - + input: + bytes: [ 0x13,0xf5,0x85,0x0c ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "andi a0, a1, 0xc8" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xc8 + access: CS_AC_READ + - + input: + bytes: [ 0x13,0x96,0xe6,0x01 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "slli a2, a3, 0x1e" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a3 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x1e + access: CS_AC_READ + - + input: + bytes: [ 0x13,0xd7,0x97,0x01 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "srli a4, a5, 0x19" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a4 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a5 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x19 + access: CS_AC_READ + - + input: + bytes: [ 0x13,0xd8,0xf8,0x40 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "srai a6, a7, 0xf" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a6 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a7 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xf + access: CS_AC_READ + - + input: + bytes: [ 0x33,0x89,0x49,0x01 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "add s2, s3, s4" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s3 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s4 + access: CS_AC_READ + - + input: + bytes: [ 0xb3,0x0a,0x7b,0x41 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "sub s5, s6, s7" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s5 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s6 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s7 + access: CS_AC_READ + - + input: + bytes: [ 0x33,0xac,0xac,0x01 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "slt s8, s9, s10" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s8 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s9 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s10 + access: CS_AC_READ + - + input: + bytes: [ 0xb3,0x3d,0xde,0x01 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "sltu s11, t3, t4" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s11 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t3 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: t4 + access: CS_AC_READ + - + input: + bytes: [ 0x33,0xd2,0x62,0x40 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "sra tp, t0, t1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: tp + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t0 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_READ + - + input: + bytes: [ 0xb3,0x43,0x94,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "xor t2, s0, s1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_READ + - + input: + bytes: [ 0x33,0xe5,0xc5,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "or a0, a1, a2" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_READ + - + input: + bytes: [ 0xb3,0x76,0xf7,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "and a3, a4, a5" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a3 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a4 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: a5 + access: CS_AC_READ + - + input: + bytes: [ 0xb3,0x54,0x39,0x01 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "srl s1, s2, s3" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s2 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s3 + access: CS_AC_READ + - + input: + bytes: [ 0xb3,0x50,0x31,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "srl ra, sp, gp" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ra + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: gp + access: CS_AC_READ + - + input: + bytes: [ 0x33,0x9f,0x0f,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "sll t5, t6, zero" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t5 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t6 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: zero + access: CS_AC_READ + - + input: + bytes: [ 0x73,0x15,0x04,0xb0 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "csrrw a0, mcycle, s0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_READ + - + input: + bytes: [ 0xf3,0x56,0x00,0x10 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "csrrwi a3, sstatus, 0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a3 + access: CS_AC_WRITE + - + type: RISCV_OP_IMM + imm: 0x0 + access: CS_AC_READ + - + input: + bytes: [ 0x33,0x05,0x7b,0x03 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mul a0, s6, s7" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s6 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s7 + access: CS_AC_READ + groups: [ hasStdExtM ] + - + input: + bytes: [ 0xb3,0x45,0x9c,0x03 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "div a1, s8, s9" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s8 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s9 + access: CS_AC_READ + groups: [ hasStdExtM ] + - + input: + bytes: [ 0x33,0x66,0xbd,0x03 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "rem a2, s10, s11" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s10 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s11 + access: CS_AC_READ + groups: [ hasStdExtM ] + - + input: + bytes: [ 0x2f,0xa4,0x02,0x10 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "lr.w s0, (t0)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: t0 + access: CS_AC_READ + groups: [ hasStdExtA ] + - + input: + bytes: [ 0xaf,0x23,0x65,0x18 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "sc.w t2, t1, (a0)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: a0 + access: CS_AC_WRITE + groups: [ hasStdExtA ] + - + input: + bytes: [ 0x2f,0x27,0x2f,0x01 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "amoadd.w a4, s2, (t5)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a4 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s2 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: t5 + access: CS_AC_READ_WRITE + groups: [ hasStdExtA ] + - + input: + bytes: [ 0x43,0xf0,0x20,0x18 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fmadd.s ft0, ft1, ft2, ft3" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft1 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft2 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft3 + access: CS_AC_READ + groups: [ hasStdExtF ] + - + input: + bytes: [ 0xd3,0x72,0x73,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fadd.s ft5, ft6, ft7" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft5 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft6 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft7 + access: CS_AC_READ + groups: [ hasStdExtF ] + - + input: + bytes: [ 0x53,0xf4,0x04,0x58 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fsqrt.s fs0, fs1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fs1 + access: CS_AC_READ + groups: [ hasStdExtF ] + - + input: + bytes: [ 0x53,0x85,0xc5,0x28 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fmin.s fa0, fa1, fa2" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fa1 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: fa2 + access: CS_AC_READ + groups: [ hasStdExtF ] + - + input: + bytes: [ 0x53,0x2e,0xde,0xa1 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "feq.s t3, ft8, ft9" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t3 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft8 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft9 + access: CS_AC_READ + groups: [ hasStdExtF ] + - + input: + bytes: [ 0xd3,0x84,0x05,0xf0 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fmv.w.x fs1, a1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + groups: [ hasStdExtF ] + - + input: + bytes: [ 0x53,0x06,0x05,0xe0 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fmv.x.w a2, fa0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_READ + groups: [ hasStdExtF ] + - + input: + bytes: [ 0x53,0x75,0x00,0xc0 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fcvt.w.s a0, ft0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft0 + access: CS_AC_READ + groups: [ hasStdExtF ] + - + input: + bytes: [ 0xd3,0xf0,0x05,0xd0 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fcvt.s.w ft1, a1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + groups: [ hasStdExtF ] + - + input: + bytes: [ 0xd3,0x15,0x08,0xe0 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fclass.s a1, fa6" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fa6 + access: CS_AC_READ + groups: [ hasStdExtF ] + - + input: + bytes: [ 0x87,0xaa,0x75,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "flw fs5, 7(a1)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs5 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: a1 + mem_disp: 0x7 + access: CS_AC_READ + groups: [ hasStdExtF ] + - + input: + bytes: [ 0x27,0x27,0x66,0x01 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fsw fs6, 0xe(a2)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs6 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: a2 + mem_disp: 0xe + access: CS_AC_WRITE + groups: [ hasStdExtF ] + - + input: + bytes: [ 0x43,0xf0,0x20,0x1a ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fmadd.d ft0, ft1, ft2, ft3" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft1 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft2 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft3 + access: CS_AC_READ + groups: [ hasStdExtD ] + - + input: + bytes: [ 0xd3,0x72,0x73,0x02 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fadd.d ft5, ft6, ft7" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft5 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft6 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft7 + access: CS_AC_READ + groups: [ hasStdExtD ] + - + input: + bytes: [ 0x53,0xf4,0x04,0x5a ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fsqrt.d fs0, fs1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fs1 + access: CS_AC_READ + groups: [ hasStdExtD ] + - + input: + bytes: [ 0x53,0x85,0xc5,0x2a ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fmin.d fa0, fa1, fa2" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fa1 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: fa2 + access: CS_AC_READ + groups: [ hasStdExtD ] + - + input: + bytes: [ 0x53,0x2e,0xde,0xa3 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "feq.d t3, ft8, ft9" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t3 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft8 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: ft9 + access: CS_AC_READ + groups: [ hasStdExtD ] + - + input: + bytes: [ 0x13,0x04,0xa8,0x7a ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "addi s0, a6, 0x7aa" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a6 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x7aa + access: CS_AC_READ + - + input: + bytes: [ 0xbb,0x07,0x9c,0x02 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mulw a5, s8, s1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a5 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s8 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_READ + groups: [ hasStdExtM, isrv64 ] + - + input: + bytes: [ 0xbb,0x40,0x5d,0x02 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "divw ra, s10, t0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ra + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s10 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: t0 + access: CS_AC_READ + groups: [ hasStdExtM, isrv64 ] + - + input: + bytes: [ 0x3b,0x63,0xb7,0x03 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "remw t1, a4, s11" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a4 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: s11 + access: CS_AC_READ + groups: [ hasStdExtM, isrv64 ] + - + input: + bytes: [ 0x2f,0xb4,0x02,0x10 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "lr.d s0, (t0)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: t0 + access: CS_AC_READ + groups: [ hasStdExtA, isrv64 ] + - + input: + bytes: [ 0xaf,0x33,0x65,0x18 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "sc.d t2, t1, (a0)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: a0 + access: CS_AC_WRITE + groups: [ hasStdExtA, isrv64 ] + - + input: + bytes: [ 0x2f,0x37,0x2f,0x01 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "amoadd.d a4, s2, (t5)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a4 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: s2 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: t5 + access: CS_AC_READ_WRITE + groups: [ hasStdExtA, isrv64 ] + - + input: + bytes: [ 0x53,0x75,0x20,0xc0 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fcvt.l.s a0, ft0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft0 + access: CS_AC_READ + groups: [ hasStdExtF, isrv64 ] + - + input: + bytes: [ 0xd3,0xf0,0x25,0xd0 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fcvt.s.l ft1, a1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + groups: [ hasStdExtF, isrv64 ] + - + input: + bytes: [ 0xd3,0x84,0x05,0xf2 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fmv.d.x fs1, a1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + groups: [ hasStdExtD, isrv64 ] + - + input: + bytes: [ 0x53,0x06,0x05,0xe2 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fmv.x.d a2, fa0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_READ + groups: [ hasStdExtD, isrv64 ] + - + input: + bytes: [ 0x53,0x75,0x00,0xc2 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fcvt.w.d a0, ft0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: ft0 + access: CS_AC_READ + groups: [ hasStdExtD ] + - + input: + bytes: [ 0xd3,0x80,0x05,0xd2 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fcvt.d.w ft1, a1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: ft1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_READ + groups: [ hasStdExtD ] + - + input: + bytes: [ 0xd3,0x15,0x08,0xe2 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fclass.d a1, fa6" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a1 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: fa6 + access: CS_AC_READ + groups: [ hasStdExtD ] + - + input: + bytes: [ 0x87,0xba,0x75,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fld fs5, 7(a1)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs5 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: a1 + mem_disp: 0x7 + access: CS_AC_READ + groups: [ hasStdExtD ] + - + input: + bytes: [ 0x27,0x37,0x66,0x01 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fsd fs6, 0xe(a2)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs6 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: a2 + mem_disp: 0xe + access: CS_AC_WRITE + groups: [ hasStdExtD ] + - + input: + bytes: [ 0xe8,0x1f ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.addi4spn a0, sp, 0x3fc" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0x3fc + access: CS_AC_READ + groups: [ hasStdExtC ] + - + input: + bytes: [ 0x7d,0x61 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.addi16sp sp, 0x1f0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_READ_WRITE + - + type: RISCV_OP_IMM + imm: 0x1f0 + access: CS_AC_READ + groups: [ hasStdExtC ] + - + input: + bytes: [ 0x80,0x25 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.fld fs0, 8(a1)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs0 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: a1 + mem_disp: 0x8 + access: CS_AC_READ + groups: [ hasStdExtC, hasStdExtD ] + - + input: + bytes: [ 0x00,0x46 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.lw s0, 8(a2)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: a2 + mem_disp: 0x8 + access: CS_AC_READ + groups: [ hasStdExtC ] + - + input: + bytes: [ 0x88,0xa2 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.fsd fa0, 0(a3)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: a3 + access: CS_AC_WRITE + groups: [ hasStdExtC, hasStdExtD ] + - + input: + bytes: [ 0x04,0xcb ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.sw s1, 0x10(a4)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: a4 + mem_disp: 0x10 + access: CS_AC_WRITE + groups: [ hasStdExtC ] + - + input: + bytes: [ 0x55,0x13 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.addi t1, -0xb" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t1 + access: CS_AC_READ_WRITE + - + type: RISCV_OP_IMM + imm: -0xb + access: CS_AC_READ + groups: [ hasStdExtC ] + - + input: + bytes: [ 0xf2,0x93 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.add t2, t3" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t2 + access: CS_AC_READ_WRITE + - + type: RISCV_OP_REG + reg: t3 + access: CS_AC_READ + groups: [ hasStdExtC ] + - + input: + bytes: [ 0x5d,0x45 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.li a0, 0x17" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_WRITE + - + type: RISCV_OP_IMM + imm: 0x17 + access: CS_AC_READ + groups: [ hasStdExtC ] + - + input: + bytes: [ 0x19,0x80 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.srli s0, 6" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s0 + access: CS_AC_READ_WRITE + - + type: RISCV_OP_IMM + imm: 0x6 + access: CS_AC_READ + groups: [ hasStdExtC ] + - + input: + bytes: [ 0x15,0x68 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.lui a6, 5" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a6 + access: CS_AC_WRITE + - + type: RISCV_OP_IMM + imm: 0x5 + access: CS_AC_READ + groups: [ hasStdExtC ] + - + input: + bytes: [ 0x2a,0xa4 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.fsdsp fa0, 8(sp)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_READ + - + type: RISCV_OP_MEM + mem_base: sp + mem_disp: 0x8 + access: CS_AC_WRITE + groups: [ hasStdExtC, hasStdExtD ] + - + input: + bytes: [ 0x62,0x24 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.fldsp fs0, 0x18(sp)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs0 + access: CS_AC_WRITE + - + type: RISCV_OP_MEM + mem_base: sp + mem_disp: 0x18 + access: CS_AC_READ + groups: [ hasStdExtC, hasStdExtD ] + - + input: + bytes: [ 0xa6,0xff ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.fswsp fs1, 0xfc(sp)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fs1 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: 0xfc + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_WRITE + groups: [ hasStdExtC, hasStdExtF, isrv32 ] + - + input: + bytes: [ 0x2a,0x65 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.flwsp fa0, 0x88(sp)" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: fa0 + access: CS_AC_WRITE + - + type: RISCV_OP_IMM + imm: 0x88 + access: CS_AC_READ + - + type: RISCV_OP_REG + reg: sp + access: CS_AC_READ + groups: [ hasStdExtC, hasStdExtF, isrv32 ] + - + input: + bytes: [ 0x76,0x86 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.mv a2, t4" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a2 + access: CS_AC_WRITE + - + type: RISCV_OP_REG + reg: t4 + access: CS_AC_READ + groups: [ hasStdExtC ] + - + input: + bytes: [ 0x65,0xdd ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.beqz a0, -8" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a0 + access: CS_AC_READ + - + type: RISCV_OP_IMM + imm: -0x8 + access: CS_AC_READ + groups: [ hasStdExtC, branch_relative, jump ] + - + input: + bytes: [ 0x01,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.nop" + details: + groups: [ hasStdExtC ] + - + input: + bytes: [ 0xfd,0xaf ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.j 0x7fe" + details: + riscv: + operands: + - + type: RISCV_OP_IMM + imm: 0x7fe + access: CS_AC_READ + groups: [ hasStdExtC, jump ] + - + input: + bytes: [ 0x82,0x82 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.jr t0" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t0 + access: CS_AC_READ + groups: [ hasStdExtC, jump ] + - + input: + bytes: [ 0x11,0x20 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.jal 4" + details: + riscv: + operands: + - + type: RISCV_OP_IMM + imm: 0x4 + access: CS_AC_READ + groups: [ hasStdExtC, isrv32, call ] + - + input: + bytes: [ 0x82,0x94 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.jalr s1" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: s1 + access: CS_AC_READ + groups: [ hasStdExtC, call ] diff --git a/tests/details/sh.yaml b/tests/details/sh.yaml new file mode 100644 index 0000000000..2118f3c47a --- /dev/null +++ b/tests/details/sh.yaml @@ -0,0 +1,111 @@ +test_cases: + - + input: + bytes: [ 0x0c, 0x31, 0x10, 0x20, 0x22, 0x21, 0x36, 0x64, 0x46, 0x25, 0x12, 0x12, 0x1c, 0x02, 0x08, 0xc1, 0x05, 0xc7, 0x0c, 0x71, 0x1f, 0x02, 0x22, 0xcf, 0x06, 0x89, 0x23, 0x00, 0x2b, 0x41, 0x0b, 0x00, 0x0e, 0x40, 0x32, 0x00, 0x0a, 0xf1, 0x09, 0x00 ] + arch: "sh" + options: [ CS_OPT_DETAIL, CS_MODE_SH4A, CS_MODE_SHFPU ] + address: 0x80000000 + expected: + insns: + - + asm_text: "add r0,r1" + details: + regs_read: [ r0 ] + regs_write: [ r1 ] + - + asm_text: "mov.b r1,@r0" + details: + regs_read: [ r0, r1 ] + - + asm_text: "mov.l r2,@r1" + details: + regs_read: [ r1, r2 ] + - + asm_text: "mov.l @r3+,r4" + details: + regs_write: [ r3, r4 ] + - + asm_text: "mov.l r4,@-r5" + details: + regs_read: [ r4 ] + regs_write: [ r5 ] + - + asm_text: "mov.l r1,@(8,r2)" + details: + regs_read: [ r2, r1 ] + - + asm_text: "mov.b @(r0,r1),r2" + details: + regs_read: [ r0, r1 ] + regs_write: [ r2 ] + - + asm_text: "mov.w r0,@(16,gbr)" + details: + regs_read: [ gbr, r0 ] + - + asm_text: "mova 0x80000028,r0" + details: + regs_write: [ r0 ] + - + asm_text: "add #12,r1" + details: + regs_write: [ r1 ] + - + asm_text: "mac.l @r1+,@r2+" + details: + regs_write: [ r1, r2 ] + - + asm_text: "or.b #34,@(r0,gbr)" + details: + regs_read: [ gbr, r0 ] + - + asm_text: "bt 0x80000028" + details: + groups: [ SH_GRP_JUMP, SH_GRP_BRANCH_RELATIVE ] + - + asm_text: "braf r0" + details: + regs_read: [ r0 ] + groups: [ SH_GRP_JUMP, SH_GRP_BRANCH_RELATIVE ] + - + asm_text: "jmp @r1" + details: + regs_read: [ r1 ] + groups: [ SH_GRP_JUMP ] + - + asm_text: "rts" + + - + asm_text: "ldc r0,sr" + details: + regs_read: [ r0 ] + regs_write: [ sr ] + - + asm_text: "stc ssr,r0" + details: + regs_read: [ ssr ] + regs_write: [ r0 ] + - + asm_text: "fmov fr0,@r1" + details: + regs_read: [ r1, fr0 ] + - + asm_text: "nop" + - + input: + bytes: [ 0x32, 0x11, 0x92, 0x00, 0x32, 0x49, 0x31, 0x00 ] + arch: "sh" + options: [ CS_OPT_DETAIL, CS_MODE_SH2A, CS_MODE_SHFPU, CS_MODE_BIG_ENDIAN ] + address: 0x0 + expected: + insns: + - + asm_text: "movu.w @(1024,r1),r2" + details: + regs_read: [ r1 ] + regs_write: [ r2 ] + - + asm_text: "bld.b #4,@(256,r2)" + details: + regs_read: [ r2 ] + diff --git a/tests/details/sparc.yaml b/tests/details/sparc.yaml new file mode 100644 index 0000000000..23eac965ac --- /dev/null +++ b/tests/details/sparc.yaml @@ -0,0 +1,228 @@ +test_cases: + - + input: + bytes: [ 0x80, 0xa0, 0x40, 0x02, 0x85, 0xc2, 0x60, 0x08, 0x85, 0xe8, 0x20, 0x01, 0x81, 0xe8, 0x00, 0x00, 0x90, 0x10, 0x20, 0x01, 0xd5, 0xf6, 0x10, 0x16, 0x21, 0x00, 0x00, 0x0a, 0x86, 0x00, 0x40, 0x02, 0x01, 0x00, 0x00, 0x00, 0x12, 0xbf, 0xff, 0xff, 0x10, 0xbf, 0xff, 0xff, 0xa0, 0x02, 0x00, 0x09, 0x0d, 0xbf, 0xff, 0xff, 0xd4, 0x20, 0x60, 0x00, 0xd4, 0x4e, 0x00, 0x16, 0x2a, 0xc2, 0x80, 0x03 ] + arch: "sparc" + options: [ CS_OPT_DETAIL ] + address: 0x1000 + expected: + insns: + - + asm_text: "cmp %g1, %g2" + details: + sparc: + operands: + - + type: SPARC_OP_REG + reg: g1 + - + type: SPARC_OP_REG + reg: g2 + - + asm_text: "jmpl %o1+8, %g2" + details: + sparc: + operands: + - + type: SPARC_OP_MEM + mem_base: o1 + mem_disp: 0x8 + - + type: SPARC_OP_REG + reg: g2 + - + asm_text: "restore %g0, 1, %g2" + details: + sparc: + operands: + - + type: SPARC_OP_REG + reg: g0 + - + type: SPARC_OP_IMM + imm: 0x1 + - + type: SPARC_OP_REG + reg: g2 + - + asm_text: "restore" + - + asm_text: "mov 1, %o0" + details: + sparc: + operands: + - + type: SPARC_OP_IMM + imm: 0x1 + - + type: SPARC_OP_REG + reg: o0 + - + asm_text: "casx [%i0], %l6, %o2" + details: + sparc: + operands: + - + type: SPARC_OP_MEM + mem_base: i0 + - + type: SPARC_OP_REG + reg: l6 + - + type: SPARC_OP_REG + reg: o2 + - + asm_text: "sethi 0xa, %l0" + details: + sparc: + operands: + - + type: SPARC_OP_IMM + imm: 0xa + - + type: SPARC_OP_REG + reg: l0 + - + asm_text: "add %g1, %g2, %g3" + details: + sparc: + operands: + - + type: SPARC_OP_REG + reg: g1 + - + type: SPARC_OP_REG + reg: g2 + - + type: SPARC_OP_REG + reg: g3 + - + asm_text: "nop" + - + asm_text: "bne 0x1020" + details: + sparc: + operands: + - + type: SPARC_OP_IMM + imm: 0x1020 + cc: SPARC_CC_ICC_NE + - + asm_text: "ba 0x1024" + details: + sparc: + operands: + - + type: SPARC_OP_IMM + imm: 0x1024 + - + asm_text: "add %o0, %o1, %l0" + details: + sparc: + operands: + - + type: SPARC_OP_REG + reg: o0 + - + type: SPARC_OP_REG + reg: o1 + - + type: SPARC_OP_REG + reg: l0 + - + asm_text: "fbg 0x102c" + details: + sparc: + operands: + - + type: SPARC_OP_IMM + imm: 0x102c + cc: SPARC_CC_FCC_G + - + asm_text: "st %o2, [%g1]" + details: + sparc: + operands: + - + type: SPARC_OP_REG + reg: o2 + - + type: SPARC_OP_MEM + mem_base: g1 + - + asm_text: "ldsb [%i0+%l6], %o2" + details: + sparc: + operands: + - + type: SPARC_OP_MEM + mem_base: i0 + mem_index: l6 + - + type: SPARC_OP_REG + reg: o2 + - + asm_text: "brnz,a,pn %o2, 0x1048" + details: + sparc: + operands: + - + type: SPARC_OP_REG + reg: o2 + - + type: SPARC_OP_IMM + imm: 0x1048 + hint: SPARC_HINT_A_PN + - + input: + bytes: [ 0x81, 0xa8, 0x0a, 0x24, 0x89, 0xa0, 0x10, 0x20, 0x89, 0xa0, 0x1a, 0x60, 0x89, 0xa0, 0x00, 0xe0 ] + arch: "sparc" + options: [ CS_OPT_DETAIL ] + address: 0x1000 + expected: + insns: + - + asm_text: "fcmps %f0, %f4" + details: + sparc: + operands: + - + type: SPARC_OP_REG + reg: f0 + - + type: SPARC_OP_REG + reg: f4 + - + asm_text: "fstox %f0, %f4" + details: + sparc: + operands: + - + type: SPARC_OP_REG + reg: f0 + - + type: SPARC_OP_REG + reg: f4 + - + asm_text: "fqtoi %f0, %f4" + details: + sparc: + operands: + - + type: SPARC_OP_REG + reg: f0 + - + type: SPARC_OP_REG + reg: f4 + - + asm_text: "fnegq %f0, %f4" + details: + sparc: + operands: + - + type: SPARC_OP_REG + reg: f0 + - + type: SPARC_OP_REG + reg: f4 + diff --git a/tests/details/systemz.yaml b/tests/details/systemz.yaml new file mode 100644 index 0000000000..da96cbe659 --- /dev/null +++ b/tests/details/systemz.yaml @@ -0,0 +1,117 @@ +test_cases: + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x5a, 0x0f, 0x1f, 0xff, 0xc2, 0x09, 0x80, 0x00, 0x00, 0x00, 0x07, 0xf7, 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x57, 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x57, 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x24, 0xb2, 0x4f, 0x00, 0x78, 0xec, 0x18, 0x00, 0x00, 0xc1, 0x7f ] + arch: "CS_ARCH_SYSZ" + options: [ CS_OPT_DETAIL ] + address: 0x1000 + expected: + insns: + - + asm_text: "adb %f0, 0" + details: + systemz: + operands: + - + type: SYSZ_OP_REG + reg: f0 + - + type: SYSZ_OP_IMM + imm: 0x0 + - + asm_text: "a %r0, 0xfff(%r15, %r1)" + details: + systemz: + operands: + - + type: SYSZ_OP_REG + reg: "0" + - + type: SYSZ_OP_MEM + mem_base: "1" + mem_index: "15" + mem_disp: 0xfff + - + asm_text: "afi %r0, -0x80000000" + details: + systemz: + operands: + - + type: SYSZ_OP_REG + reg: "0" + - + type: SYSZ_OP_IMM + imm: -0x80000000 + - + asm_text: "br %r7" + details: + systemz: + operands: + - + type: SYSZ_OP_REG + reg: "7" + - + asm_text: "xiy 0x7ffff(%r15), 0x2a" + details: + systemz: + operands: + - + type: SYSZ_OP_MEM + mem_base: "15" + mem_disp: 0x7ffff + - + type: SYSZ_OP_IMM + imm: 0x2a + - + asm_text: "xy %r0, 0x7ffff(%r1, %r15)" + details: + systemz: + operands: + - + type: SYSZ_OP_REG + reg: "0" + - + type: SYSZ_OP_MEM + mem_base: "15" + mem_index: "1" + mem_disp: 0x7ffff + - + asm_text: "stmg %r0, %r0, 0(%r15)" + details: + systemz: + operands: + - + type: SYSZ_OP_REG + reg: "0" + - + type: SYSZ_OP_REG + reg: "0" + - + type: SYSZ_OP_MEM + mem_base: "15" + - + asm_text: "ear %r7, %a8" + details: + systemz: + operands: + - + type: SYSZ_OP_REG + reg: "7" + - + type: SYSZ_OP_REG + reg: a8 + - + asm_text: "clije %r1, 0xc1, 0x1028" + details: + systemz: + operands: + - + type: SYSZ_OP_REG + reg: "1" + - + type: SYSZ_OP_IMM + imm: 0xc1 + - + type: SYSZ_OP_IMM + imm: 0x1028 + diff --git a/tests/details/tms320c64x.yaml b/tests/details/tms320c64x.yaml new file mode 100644 index 0000000000..93610edc73 --- /dev/null +++ b/tests/details/tms320c64x.yaml @@ -0,0 +1,147 @@ +test_cases: + - + input: + bytes: [ 0x01, 0xac, 0x88, 0x40, 0x81, 0xac, 0x88, 0x43, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x32, 0x96, 0x02, 0x80, 0x46, 0x9e, 0x05, 0x3c, 0x83, 0xe6, 0x0b, 0x0c, 0x8b, 0x24 ] + arch: "tms320c64x" + options: [ CS_OPT_DETAIL ] + address: 0x1000 + expected: + insns: + - + asm_text: "add.D1 a11, a4, a3" + details: + tms320c64x: + operands: + - + type: TMS320C64X_OP_REG + reg: a11 + - + type: TMS320C64X_OP_REG + reg: a4 + - + type: TMS320C64X_OP_REG + reg: a3 + funit_unit: TMS320C64X_FUNIT_D + funit_side: 1 + funit_side_set: true + parallel: 0 + parallel_set: true + - + asm_text: "[ a1] add.D2 b11, b4, b3 ||" + details: + tms320c64x: + operands: + - + type: TMS320C64X_OP_REG + reg: b11 + - + type: TMS320C64X_OP_REG + reg: b4 + - + type: TMS320C64X_OP_REG + reg: b3 + funit_unit: TMS320C64X_FUNIT_D + funit_side: 2 + funit_side_set: true + cond_reg: a1 + cond_zero: -1 + parallel: 1 + parallel_set: true + - + asm_text: "NOP" + details: + tms320c64x: + funit_unit: TMS320C64X_FUNIT_NO + parallel: 0 + parallel_set: true + - + asm_text: "ldbu.D1T2 *++a4[1], b5" + details: + tms320c64x: + operands: + - + type: TMS320C64X_OP_MEM + mem_base: a4 + mem_disptype: TMS320C64X_MEM_DISP_CONSTANT + mem_disp_const: 0x1 + mem_unit: 2 + mem_direction: TMS320C64X_MEM_DIR_FW + mem_modify: TMS320C64X_MEM_MOD_PRE + mem_scaled: 1 + - + type: TMS320C64X_OP_REG + reg: b5 + funit_unit: TMS320C64X_FUNIT_D + funit_side: 2 + funit_side_set: true + parallel: 0 + parallel_set: true + - + asm_text: "ldbu.D2T2 *+b15[0x46], b5" + details: + tms320c64x: + operands: + - + type: TMS320C64X_OP_MEM + mem_base: b15 + mem_disptype: TMS320C64X_MEM_DISP_CONSTANT + mem_disp_const: 0x46 + mem_unit: 2 + mem_direction: TMS320C64X_MEM_DIR_FW + mem_modify: TMS320C64X_MEM_MOD_NO + mem_scaled: -1 + - + type: TMS320C64X_OP_REG + reg: b5 + funit_unit: TMS320C64X_FUNIT_D + funit_side: 2 + funit_side_set: true + parallel: 0 + parallel_set: true + - + asm_text: "lddw.D1T2 *+a15[4], b11:b10" + details: + tms320c64x: + operands: + - + type: TMS320C64X_OP_MEM + mem_base: a15 + mem_disptype: TMS320C64X_MEM_DISP_CONSTANT + mem_disp_const: 0x4 + mem_unit: 2 + mem_direction: TMS320C64X_MEM_DIR_FW + mem_modify: TMS320C64X_MEM_MOD_NO + mem_scaled: 1 + - + type: TMS320C64X_OP_REGPAIR + reg_pair_0: b11 + reg_pair_1: b10 + funit_unit: TMS320C64X_FUNIT_D + funit_side: 2 + funit_side_set: true + parallel: 0 + parallel_set: true + - + asm_text: "ldndw.D1T1 *+a3(a4), a23:a22" + details: + tms320c64x: + operands: + - + type: TMS320C64X_OP_MEM + mem_base: a3 + mem_disptype: TMS320C64X_MEM_DISP_REGISTER + mem_disp_reg: a4 + mem_unit: 1 + mem_direction: TMS320C64X_MEM_DIR_FW + mem_modify: TMS320C64X_MEM_MOD_NO + mem_scaled: -1 + - + type: TMS320C64X_OP_REGPAIR + reg_pair_0: a23 + reg_pair_1: a22 + funit_unit: TMS320C64X_FUNIT_D + funit_side: 1 + funit_side_set: true + parallel: 0 + parallel_set: true + diff --git a/tests/details/tricore.yaml b/tests/details/tricore.yaml new file mode 100644 index 0000000000..1ded016168 --- /dev/null +++ b/tests/details/tricore.yaml @@ -0,0 +1,101 @@ +test_cases: + - + input: + bytes: [ 0x09, 0xcf, 0xbc, 0xf5, 0x09, 0xf4, 0x01, 0x00, 0x89, 0xfb, 0x8f, 0x74, 0x89, 0xfe, 0x48, 0x01, 0x29, 0x00, 0x19, 0x25, 0x29, 0x03, 0x09, 0xf4, 0x85, 0xf9, 0x68, 0x0f, 0x16, 0x01 ] + arch: "tricore" + options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ld.a a15, [+a12]#-4" + details: + tricore: + operands: + - + type: TRICORE_OP_REG + reg: a15 + - + type: TRICORE_OP_MEM + mem_base: a12 + mem_disp: -4 + - + asm_text: "ld.b d4, [a15+]#1" + details: + tricore: + operands: + - + type: TRICORE_OP_REG + reg: d4 + - + type: TRICORE_OP_MEM + mem_base: a15 + mem_disp: 0x1 + - + asm_text: "st.h [+a15]#0x1cf, d11" + details: + tricore: + operands: + - + type: TRICORE_OP_MEM + mem_base: a15 + mem_disp: 0x1cf + - + type: TRICORE_OP_REG + reg: d11 + - + asm_text: "st.d [a15+]#8, e14" + details: + tricore: + operands: + - + type: TRICORE_OP_MEM + mem_base: a15 + mem_disp: 0x8 + - + type: TRICORE_OP_REG + reg: e14 + - + asm_text: "ld.w d0, [p0+c]#0x99" + details: + tricore: + operands: + - + type: TRICORE_OP_REG + reg: d0 + - + type: TRICORE_OP_MEM + mem_base: p0 + mem_disp: 0x99 + - + asm_text: "ld.b d3, [p0+c]#-0x37" + details: + tricore: + operands: + - + type: TRICORE_OP_REG + reg: d3 + - + type: TRICORE_OP_MEM + mem_base: p0 + mem_disp: -0x37 + - + asm_text: "ld.da p8, #0xf0003428" + details: + tricore: + operands: + - + type: TRICORE_OP_REG + reg: p8 + - + type: TRICORE_OP_IMM + imm: 0xf0003428 + - + asm_text: "and d15, #1" + details: + tricore: + operands: + - + type: TRICORE_OP_IMM + imm: 0x1 + diff --git a/tests/details/wasm.yaml b/tests/details/wasm.yaml new file mode 100644 index 0000000000..1a3a492974 --- /dev/null +++ b/tests/details/wasm.yaml @@ -0,0 +1,58 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x00, 0x20, 0x01, 0x41, 0x20, 0x10, 0xc9, 0x01, 0x45, 0x0b ] + arch: "wasm" + options: [ CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "get_local 0x0" + details: + groups: [ WASM_GRP_VARIABLE ] + wasm: + operands: + - + type: WASM_OP_VARUINT32 + varuint32: 0x0 + size: 1 + - + asm_text: "get_local 0x1" + details: + groups: [ WASM_GRP_VARIABLE ] + wasm: + operands: + - + type: WASM_OP_VARUINT32 + varuint32: 0x1 + size: 1 + - + asm_text: "i32.const 0x20" + details: + groups: [ WASM_GRP_NUMBERIC ] + wasm: + operands: + - + type: WASM_OP_VARUINT32 + varuint32: 0x20 + size: 1 + - + asm_text: "call 0xc9" + details: + groups: [ WASM_GRP_CONTROL ] + wasm: + operands: + - + type: WASM_OP_VARUINT32 + varuint32: 0xc9 + size: 2 + - + asm_text: "i32.eqz" + details: + groups: [ WASM_GRP_NUMBERIC ] + - + asm_text: "end" + details: + groups: [ WASM_GRP_CONTROL ] + diff --git a/tests/details/x86.yaml b/tests/details/x86.yaml new file mode 100644 index 0000000000..4f453121d8 --- /dev/null +++ b/tests/details/x86.yaml @@ -0,0 +1,1242 @@ +test_cases: + - + input: + bytes: [0x8d, 0x4c, 0x32, 0x08, 0x01, 0xd8, 0x81, 0xc6, 0x34, 0x12, 0x00, 0x00, 0x05, 0x23, 0x01, 0x00, 0x00, 0x36, 0x8b, 0x84, 0x91, 0x23, 0x01, 0x00, 0x00, 0x41, 0x8d, 0x84, 0x39, 0x89, 0x67, 0x00, 0x00, 0x8d, 0x87, 0x89, 0x67, 0x00, 0x00, 0xb4, 0xc6, 0x66, 0xe9, 0xb8, 0x00, 0x00, 0x00, 0x67, 0xff, 0xa0, 0x23, 0x01, 0x00, 0x00, 0x66, 0xe8, 0xcb, 0x00, 0x00, 0x00, 0x74, 0xfc, ] + arch: "x86" + options: [ CS_OPT_DETAIL, CS_MODE_16 ] + address: 0x1000 + expected: + insns: + - + asm_text: "lea cx, [si + 0x32]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x8d, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 2 + modrm: 0x4c + enc_modrm_offset: 0x1 + disp: 0x32 + enc_disp_offset: 0x2 + enc_disp_size: 0x1 + operands: + - + type: X86_OP_REG + reg: cx + size: 2 + access: CS_AC_WRITE + - + type: X86_OP_MEM + mem_base: si + mem_disp: 0x32 + size: 2 + access: CS_AC_READ + regs_read: [ si ] + regs_write: [ cx ] + - + asm_text: "or byte ptr [bx + di], al" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x08, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 2 + modrm: 0x1 + enc_modrm_offset: 0x1 + disp: 0x0 + operands: + - + type: X86_OP_MEM + mem_base: bx + mem_index: di + size: 1 + access: CS_AC_READ_WRITE + - + type: X86_OP_REG + reg: al + size: 1 + access: CS_AC_READ + eflags: [ X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_RESET_OF, X86_EFLAGS_RESET_CF, X86_EFLAGS_UNDEFINED_AF ] + regs_read: [ bx, di, al ] + regs_write: [ flags ] + - + asm_text: "fadd dword ptr [bx + di + 0x34c6]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xd8, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 2 + modrm: 0x81 + enc_modrm_offset: 0x1 + disp: 0x34c6 + enc_disp_offset: 0x2 + enc_disp_size: 0x2 + operands: + - + type: X86_OP_MEM + mem_base: bx + mem_index: di + mem_disp: 0x34c6 + size: 4 + access: CS_AC_READ + fpu_flags: [ X86_FPU_FLAGS_MODIFY_C1, X86_FPU_FLAGS_UNDEFINED_C0, X86_FPU_FLAGS_UNDEFINED_C2, X86_FPU_FLAGS_UNDEFINED_C3] + regs_read: [ bx, di ] + regs_write: [ fpsw ] + - + asm_text: "adc al, byte ptr [bx + si]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x12, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 2 + modrm: 0x0 + enc_modrm_offset: 0x1 + disp: 0x0 + operands: + - + type: X86_OP_REG + reg: al + size: 1 + access: CS_AC_READ_WRITE + - + type: X86_OP_MEM + mem_base: bx + mem_index: si + size: 1 + access: CS_AC_READ + eflags: [ X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF, X86_EFLAGS_TEST_CF ] + regs_read: [ flags, al, bx, si ] + regs_write: [ flags, al ] + - + asm_text: "add byte ptr [di], al" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x00, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 2 + modrm: 0x5 + enc_modrm_offset: 0x1 + disp: 0x0 + operands: + - + type: X86_OP_MEM + mem_base: di + size: 1 + access: CS_AC_READ_WRITE + - + type: X86_OP_REG + reg: al + size: 1 + access: CS_AC_READ + eflags: [ X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ] + regs_read: [ di, al ] + regs_write: [ flags ] + - + asm_text: "and ax, word ptr [bx + di]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x23, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 2 + modrm: 0x1 + enc_modrm_offset: 0x1 + disp: 0x0 + operands: + - + type: X86_OP_REG + reg: ax + size: 2 + access: CS_AC_READ_WRITE + - + type: X86_OP_MEM + mem_base: bx + mem_index: di + size: 2 + access: CS_AC_READ + eflags: [ X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_RESET_OF, X86_EFLAGS_RESET_CF, X86_EFLAGS_UNDEFINED_AF ] + regs_read: [ ax, bx, di ] + regs_write: [ flags, ax ] + - + asm_text: "add byte ptr [bx + si], al" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x00, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 2 + modrm: 0x0 + enc_modrm_offset: 0x1 + disp: 0x0 + operands: + - + type: X86_OP_MEM + mem_base: bx + mem_index: si + size: 1 + access: CS_AC_READ_WRITE + - + type: X86_OP_REG + reg: al + size: 1 + access: CS_AC_READ + eflags: [ X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ] + regs_read: [ bx, si, al ] + regs_write: [ flags ] + - + asm_text: "mov ax, word ptr ss:[si + 0x2391]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_SS, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x8b, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 2 + modrm: 0x84 + enc_modrm_offset: 0x2 + disp: 0x2391 + enc_disp_offset: 0x3 + enc_disp_size: 0x2 + operands: + - + type: X86_OP_REG + reg: ax + size: 2 + access: CS_AC_WRITE + - + type: X86_OP_MEM + mem_segment: ss + mem_base: si + mem_disp: 0x2391 + size: 2 + access: CS_AC_READ + regs_read: [ ss, si ] + regs_write: [ ax ] + - + asm_text: "add word ptr [bx + si], ax" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x01, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 2 + modrm: 0x0 + enc_modrm_offset: 0x1 + disp: 0x0 + operands: + - + type: X86_OP_MEM + mem_base: bx + mem_index: si + size: 2 + access: CS_AC_READ_WRITE + - + type: X86_OP_REG + reg: ax + size: 2 + access: CS_AC_READ + eflags: [ X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ] + regs_read: [ bx, si, ax ] + regs_write: [ flags ] + - + asm_text: "add byte ptr [bx + di - 0x73], al" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x00, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 2 + modrm: 0x41 + enc_modrm_offset: 0x1 + disp: -0x73 + enc_disp_offset: 0x2 + enc_disp_size: 0x1 + operands: + - + type: X86_OP_MEM + mem_base: bx + mem_index: di + mem_disp: -0x73 + size: 1 + access: CS_AC_READ_WRITE + - + type: X86_OP_REG + reg: al + size: 1 + access: CS_AC_READ + eflags: [ X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ] + regs_read: [ bx, di, al ] + regs_write: [ flags ] + - + asm_text: "test byte ptr [bx + di], bh" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x84, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 2 + modrm: 0x39 + enc_modrm_offset: 0x1 + disp: 0x0 + operands: + - + type: X86_OP_MEM + mem_base: bx + mem_index: di + size: 1 + - + type: X86_OP_REG + reg: bh + size: 1 + regs_read: [ bx, di ] + - + asm_text: "mov word ptr [bx], sp" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x89, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 2 + modrm: 0x67 + enc_modrm_offset: 0x1 + disp: 0x0 + enc_disp_offset: 0x2 + enc_disp_size: 0x1 + operands: + - + type: X86_OP_MEM + mem_base: bx + size: 2 + access: CS_AC_WRITE + - + type: X86_OP_REG + reg: sp + size: 2 + access: CS_AC_READ + regs_read: [ bx, sp ] + - + asm_text: "add byte ptr [di - 0x7679], cl" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x00, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 2 + modrm: 0x8d + enc_modrm_offset: 0x1 + disp: -0x7679 + enc_disp_offset: 0x2 + enc_disp_size: 0x2 + operands: + - + type: X86_OP_MEM + mem_base: di + mem_disp: -0x7679 + size: 1 + access: CS_AC_READ_WRITE + - + type: X86_OP_REG + reg: cl + size: 1 + access: CS_AC_READ + eflags: [ X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ] + regs_read: [ di, cl ] + regs_write: [ flags ] + - + asm_text: "add byte ptr [eax], al" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_ADDRSIZE ] + opcode: [ 0x00, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + enc_modrm_offset: 0x2 + disp: 0x0 + operands: + - + type: X86_OP_MEM + mem_base: eax + size: 1 + access: CS_AC_READ_WRITE + - + type: X86_OP_REG + reg: al + size: 1 + access: CS_AC_READ + eflags: [ X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ] + regs_read: [ eax, al ] + regs_write: [ flags ] + - + asm_text: "mov ah, 0xc6" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xb4, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 2 + modrm: 0x0 + disp: 0x0 + operands: + - + type: X86_OP_REG + reg: ah + size: 1 + access: CS_AC_WRITE + - + type: X86_OP_IMM + imm: 0xc6 + size: 1 + regs_write: [ ah ] + - + asm_text: "jmp 0x10e7" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_OPSIZE, X86_PREFIX_0 ] + opcode: [ 0xe9, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 2 + modrm: 0x0 + disp: 0x0 + operands: + - + type: X86_OP_IMM + imm: 0x10e7 + size: 4 + - + asm_text: "jmp word ptr [eax + 0x123]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_ADDRSIZE ] + opcode: [ 0xff, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0xa0 + enc_modrm_offset: 0x2 + disp: 0x123 + enc_disp_offset: 0x3 + enc_disp_size: 0x4 + operands: + - + type: X86_OP_MEM + mem_base: eax + mem_disp: 0x123 + size: 2 + access: CS_AC_READ + regs_read: [ eax ] + - + asm_text: "call 0x1107" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_OPSIZE, X86_PREFIX_0 ] + opcode: [ 0xe8, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 2 + modrm: 0x0 + disp: 0x0 + operands: + - + type: X86_OP_IMM + imm: 0x1107 + size: 4 + regs_read: [ esp, eip ] + regs_write: [ esp ] + - + asm_text: "je 0x103a" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x74, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 2 + modrm: 0x0 + disp: 0x0 + operands: + - + type: X86_OP_IMM + imm: 0x103a + size: 2 + eflags: [ X86_EFLAGS_TEST_ZF ] + regs_read: [ flags ] + - + input: + bytes: [0x8d, 0x4c, 0x32, 0x08, 0x01, 0xd8, 0x81, 0xc6, 0x34, 0x12, 0x00, 0x00, 0x05, 0x23, 0x01, 0x00, 0x00, 0x36, 0x8b, 0x84, 0x91, 0x23, 0x01, 0x00, 0x00, 0x41, 0x8d, 0x84, 0x39, 0x89, 0x67, 0x00, 0x00, 0x8d, 0x87, 0x89, 0x67, 0x00, 0x00, 0xb4, 0xc6, 0xe9, 0xea, 0xbe, 0xad, 0xde, 0xff, 0xa0, 0x23, 0x01, 0x00, 0x00, 0xe8, 0xdf, 0xbe, 0xad, 0xde, 0x74, 0xff, ] + arch: "x86" + options: [ CS_OPT_DETAIL, CS_MODE_32, CS_OPT_SYNTAX_ATT ] + address: 0x1000 + expected: + insns: + - + asm_text: "leal 8(%edx, %esi), %ecx" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x8d, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x4c + enc_modrm_offset: 0x1 + disp: 0x8 + enc_disp_offset: 0x3 + enc_disp_size: 0x1 + sib: 0x32 + sib_base: edx + sib_index: esi + sib_scale: 1 + operands: + - + type: X86_OP_MEM + mem_base: edx + mem_index: esi + mem_disp: 0x8 + size: 4 + access: CS_AC_READ + - + type: X86_OP_REG + reg: ecx + size: 4 + access: CS_AC_WRITE + regs_read: [ edx, esi ] + regs_write: [ ecx ] + - + asm_text: "addl %ebx, %eax" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x01, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0xd8 + enc_modrm_offset: 0x1 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_REG + reg: ebx + size: 4 + access: CS_AC_READ + - + type: X86_OP_REG + reg: eax + size: 4 + access: CS_AC_READ_WRITE + eflags: [ X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ] + regs_read: [ ebx, eax ] + regs_write: [ eflags, eax ] + - + asm_text: "addl $0x1234, %esi" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x81, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0xc6 + enc_modrm_offset: 0x1 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_IMM + imm: 0x1234 + size: 4 + - + type: X86_OP_REG + reg: esi + size: 4 + access: CS_AC_READ_WRITE + eflags: [ X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ] + regs_read: [ esi ] + regs_write: [ eflags, esi ] + - + asm_text: "addl $0x123, %eax" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x05, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_IMM + imm: 0x123 + size: 4 + - + type: X86_OP_REG + reg: eax + size: 4 + access: CS_AC_READ_WRITE + eflags: [ X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ] + regs_read: [ eax ] + regs_write: [ eflags, eax ] + - + asm_text: "movl %ss:0x123(%ecx, %edx, 4), %eax" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_SS, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x8b, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x84 + enc_modrm_offset: 0x2 + disp: 0x123 + enc_disp_offset: 0x4 + enc_disp_size: 0x4 + sib: 0x91 + sib_base: ecx + sib_index: edx + sib_scale: 4 + operands: + - + type: X86_OP_MEM + mem_segment: ss + mem_base: ecx + mem_index: edx + mem_scale: 4 + mem_disp: 0x123 + size: 4 + access: CS_AC_READ + - + type: X86_OP_REG + reg: eax + size: 4 + access: CS_AC_WRITE + regs_read: [ ss, ecx, edx ] + regs_write: [ eax ] + - + asm_text: "incl %ecx" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x41, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_REG + reg: ecx + size: 4 + access: CS_AC_READ_WRITE + eflags: [ X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ] + regs_read: [ ecx ] + regs_write: [ eflags, ecx ] + - + asm_text: "leal 0x6789(%ecx, %edi), %eax" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x8d, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x84 + enc_modrm_offset: 0x1 + disp: 0x6789 + enc_disp_offset: 0x3 + enc_disp_size: 0x4 + sib: 0x39 + sib_base: ecx + sib_index: edi + sib_scale: 1 + operands: + - + type: X86_OP_MEM + mem_base: ecx + mem_index: edi + mem_disp: 0x6789 + size: 4 + access: CS_AC_READ + - + type: X86_OP_REG + reg: eax + size: 4 + access: CS_AC_WRITE + regs_read: [ ecx, edi ] + regs_write: [ eax ] + - + asm_text: "leal 0x6789(%edi), %eax" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x8d, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x87 + enc_modrm_offset: 0x1 + disp: 0x6789 + enc_disp_offset: 0x2 + enc_disp_size: 0x4 + sib: 0x0 + operands: + - + type: X86_OP_MEM + mem_base: edi + mem_disp: 0x6789 + size: 4 + access: CS_AC_READ + - + type: X86_OP_REG + reg: eax + size: 4 + access: CS_AC_WRITE + regs_read: [ edi ] + regs_write: [ eax ] + - + asm_text: "movb $0xc6, %ah" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xb4, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_IMM + imm: 0xc6 + size: 1 + - + type: X86_OP_REG + reg: ah + size: 1 + access: CS_AC_WRITE + regs_write: [ ah ] + - + asm_text: "jmp 0xdeadcf18" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xe9, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_IMM + imm: 0xdeadcf18 + size: 4 + - + asm_text: "jmpl *0x123(%eax)" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xff, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0xa0 + enc_modrm_offset: 0x1 + disp: 0x123 + enc_disp_offset: 0x2 + enc_disp_size: 0x4 + sib: 0x0 + operands: + - + type: X86_OP_MEM + mem_base: eax + mem_disp: 0x123 + size: 4 + access: CS_AC_READ + regs_read: [ eax ] + - + asm_text: "calll 0xdeadcf18" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xe8, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_IMM + imm: 0xdeadcf18 + size: 4 + regs_read: [ esp, eip ] + regs_write: [ esp ] + - + asm_text: "je 0x103a" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x74, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_IMM + imm: 0x103a + size: 4 + eflags: [ X86_EFLAGS_TEST_ZF ] + regs_read: [ eflags ] + - + input: + bytes: [0x8d, 0x4c, 0x32, 0x08, 0x01, 0xd8, 0x81, 0xc6, 0x34, 0x12, 0x00, 0x00, 0x05, 0x23, 0x01, 0x00, 0x00, 0x36, 0x8b, 0x84, 0x91, 0x23, 0x01, 0x00, 0x00, 0x41, 0x8d, 0x84, 0x39, 0x89, 0x67, 0x00, 0x00, 0x8d, 0x87, 0x89, 0x67, 0x00, 0x00, 0xb4, 0xc6, 0xe9, 0xea, 0xbe, 0xad, 0xde, 0xff, 0xa0, 0x23, 0x01, 0x00, 0x00, 0xe8, 0xdf, 0xbe, 0xad, 0xde, 0x74, 0xff, ] + arch: "x86" + options: [ CS_OPT_DETAIL, CS_MODE_32 ] + address: 0x1000 + expected: + insns: + - + asm_text: "lea ecx, [edx + esi + 8]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x8d, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x4c + enc_modrm_offset: 0x1 + disp: 0x8 + enc_disp_offset: 0x3 + enc_disp_size: 0x1 + sib: 0x32 + sib_base: edx + sib_index: esi + sib_scale: 1 + operands: + - + type: X86_OP_REG + reg: ecx + size: 4 + access: CS_AC_WRITE + - + type: X86_OP_MEM + mem_base: edx + mem_index: esi + mem_disp: 0x8 + size: 4 + access: CS_AC_READ + regs_read: [ edx, esi ] + regs_write: [ ecx ] + - + asm_text: "add eax, ebx" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x01, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0xd8 + enc_modrm_offset: 0x1 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_REG + reg: eax + size: 4 + access: CS_AC_READ_WRITE + - + type: X86_OP_REG + reg: ebx + size: 4 + access: CS_AC_READ + eflags: [ X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ] + regs_read: [ eax, ebx ] + regs_write: [ eflags, eax ] + - + asm_text: "add esi, 0x1234" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x81, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0xc6 + enc_modrm_offset: 0x1 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_REG + reg: esi + size: 4 + access: CS_AC_READ_WRITE + - + type: X86_OP_IMM + imm: 0x1234 + size: 4 + eflags: [ X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ] + regs_read: [ esi ] + regs_write: [ eflags, esi ] + - + asm_text: "add eax, 0x123" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x05, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_REG + reg: eax + size: 4 + access: CS_AC_READ_WRITE + - + type: X86_OP_IMM + imm: 0x123 + size: 4 + eflags: [ X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ] + regs_read: [ eax ] + regs_write: [ eflags, eax ] + - + asm_text: "mov eax, dword ptr ss:[ecx + edx*4 + 0x123]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_SS, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x8b, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x84 + enc_modrm_offset: 0x2 + disp: 0x123 + enc_disp_offset: 0x4 + enc_disp_size: 0x4 + sib: 0x91 + sib_base: ecx + sib_index: edx + sib_scale: 4 + operands: + - + type: X86_OP_REG + reg: eax + size: 4 + access: CS_AC_WRITE + - + type: X86_OP_MEM + mem_segment: ss + mem_base: ecx + mem_index: edx + mem_scale: 4 + mem_disp: 0x123 + size: 4 + access: CS_AC_READ + regs_read: [ ss, ecx, edx ] + regs_write: [ eax ] + - + asm_text: "inc ecx" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x41, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_REG + reg: ecx + size: 4 + access: CS_AC_READ_WRITE + eflags: [ X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ] + regs_read: [ ecx ] + regs_write: [ eflags, ecx ] + - + asm_text: "lea eax, [ecx + edi + 0x6789]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x8d, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x84 + enc_modrm_offset: 0x1 + disp: 0x6789 + enc_disp_offset: 0x3 + enc_disp_size: 0x4 + sib: 0x39 + sib_base: ecx + sib_index: edi + sib_scale: 1 + operands: + - + type: X86_OP_REG + reg: eax + size: 4 + access: CS_AC_WRITE + - + type: X86_OP_MEM + mem_base: ecx + mem_index: edi + mem_disp: 0x6789 + size: 4 + access: CS_AC_READ + regs_read: [ ecx, edi ] + regs_write: [ eax ] + - + asm_text: "lea eax, [edi + 0x6789]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x8d, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x87 + enc_modrm_offset: 0x1 + disp: 0x6789 + enc_disp_offset: 0x2 + enc_disp_size: 0x4 + sib: 0x0 + operands: + - + type: X86_OP_REG + reg: eax + size: 4 + access: CS_AC_WRITE + - + type: X86_OP_MEM + mem_base: edi + mem_disp: 0x6789 + size: 4 + access: CS_AC_READ + regs_read: [ edi ] + regs_write: [ eax ] + - + asm_text: "mov ah, 0xc6" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xb4, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_REG + reg: ah + size: 1 + access: CS_AC_WRITE + - + type: X86_OP_IMM + imm: 0xc6 + size: 1 + regs_write: [ ah ] + - + asm_text: "jmp 0xdeadcf18" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xe9, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_IMM + imm: 0xdeadcf18 + size: 4 + - + asm_text: "jmp dword ptr [eax + 0x123]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xff, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0xa0 + enc_modrm_offset: 0x1 + disp: 0x123 + enc_disp_offset: 0x2 + enc_disp_size: 0x4 + sib: 0x0 + operands: + - + type: X86_OP_MEM + mem_base: eax + mem_disp: 0x123 + size: 4 + access: CS_AC_READ + regs_read: [ eax ] + - + asm_text: "call 0xdeadcf18" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xe8, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_IMM + imm: 0xdeadcf18 + size: 4 + regs_read: [ esp, eip ] + regs_write: [ esp ] + - + asm_text: "je 0x103a" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x74, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_IMM + imm: 0x103a + size: 4 + eflags: [ X86_EFLAGS_TEST_ZF ] + regs_read: [ eflags ] + - + input: + bytes: [0x55, 0x48, 0x8b, 0x05, 0xb8, 0x13, 0x00, 0x00, 0xe9, 0xea, 0xbe, 0xad, 0xde, 0xff, 0x25, 0x23, 0x01, 0x00, 0x00, 0xe8, 0xdf, 0xbe, 0xad, 0xde, 0x74, 0xff, ] + arch: "x86" + options: [ CS_OPT_DETAIL, CS_MODE_64 ] + address: 0x1000 + expected: + insns: + - + asm_text: "push rbp" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x55, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 8 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_REG + reg: rbp + size: 8 + access: CS_AC_READ + regs_read: [ rsp, rbp ] + regs_write: [ rsp ] + - + asm_text: "mov rax, qword ptr [rip + 0x13b8]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x8b, 0x00, 0x00, 0x00 ] + rex: 0x48 + addr_size: 8 + modrm: 0x5 + enc_modrm_offset: 0x2 + disp: 0x13b8 + enc_disp_offset: 0x3 + enc_disp_size: 0x4 + sib: 0x0 + operands: + - + type: X86_OP_REG + reg: rax + size: 8 + access: CS_AC_WRITE + - + type: X86_OP_MEM + mem_base: rip + mem_disp: 0x13b8 + size: 8 + access: CS_AC_READ + regs_read: [ rip ] + regs_write: [ rax ] + - + asm_text: "jmp 0xffffffffdeadcef7" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xe9, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 8 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_IMM + imm: -0x21523109 + size: 8 + - + asm_text: "jmp qword ptr [rip + 0x123]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xff, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 8 + modrm: 0x25 + enc_modrm_offset: 0x1 + disp: 0x123 + enc_disp_offset: 0x2 + enc_disp_size: 0x4 + sib: 0x0 + operands: + - + type: X86_OP_MEM + mem_base: rip + mem_disp: 0x123 + size: 8 + access: CS_AC_READ + regs_read: [ rip ] + - + asm_text: "call 0xffffffffdeadcef7" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xe8, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 8 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_IMM + imm: -0x21523109 + size: 8 + regs_read: [ rsp, rip ] + regs_write: [ rsp ] + - + asm_text: "je 0x1019" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x74, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 8 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_IMM + imm: 0x1019 + size: 8 + eflags: [ X86_EFLAGS_TEST_ZF ] + regs_read: [ rflags ] diff --git a/tests/details/xcore.yaml b/tests/details/xcore.yaml new file mode 100644 index 0000000000..bf5a348fbd --- /dev/null +++ b/tests/details/xcore.yaml @@ -0,0 +1,128 @@ +test_cases: + - + input: + bytes: [ 0xfe, 0x0f, 0xfe, 0x17, 0x13, 0x17, 0xc6, 0xfe, 0xec, 0x17, 0x97, 0xf8, 0xec, 0x4f, 0x1f, 0xfd, 0xec, 0x37, 0x07, 0xf2, 0x45, 0x5b, 0xf9, 0xfa, 0x02, 0x06, 0x1b, 0x10, 0x09, 0xfd, 0xec, 0xa7 ] + arch: "xcore" + options: [ CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "get r11, ed" + details: + xcore: + operands: + - + type: XCORE_OP_REG + reg: r11 + - + type: XCORE_OP_REG + reg: ed + - + asm_text: "ldw et, sp[4]" + details: + xcore: + operands: + - + type: XCORE_OP_REG + reg: et + - + type: XCORE_OP_MEM + mem_base: sp + mem_disp: 0x4 + - + asm_text: "setd res[r3], r4" + details: + xcore: + operands: + - + type: XCORE_OP_REG + reg: r4 + - + asm_text: "init t[r2]:lr, r1" + details: + xcore: + operands: + - + type: XCORE_OP_MEM + mem_base: r2 + mem_index: lr + - + type: XCORE_OP_REG + reg: r1 + - + asm_text: "divu r9, r1, r3" + details: + xcore: + operands: + - + type: XCORE_OP_REG + reg: r9 + - + type: XCORE_OP_REG + reg: r1 + - + type: XCORE_OP_REG + reg: r3 + - + asm_text: "lda16 r9, r3[-r11]" + details: + xcore: + operands: + - + type: XCORE_OP_REG + reg: r9 + - + asm_text: "ldw dp, dp[0x81c5]" + details: + xcore: + operands: + - + type: XCORE_OP_REG + reg: dp + - + asm_text: "lmul r11, r0, r2, r5, r8, r10" + details: + xcore: + operands: + - + type: XCORE_OP_REG + reg: r11 + - + type: XCORE_OP_REG + reg: r0 + - + type: XCORE_OP_REG + reg: r2 + - + type: XCORE_OP_REG + reg: r5 + - + type: XCORE_OP_REG + reg: r8 + - + type: XCORE_OP_REG + reg: r10 + - + asm_text: "add r1, r2, r3" + details: + xcore: + operands: + - + type: XCORE_OP_REG + reg: r1 + - + type: XCORE_OP_REG + reg: r2 + - + type: XCORE_OP_REG + reg: r3 + - + asm_text: "ldaw r8, r2[-9]" + details: + xcore: + operands: + - + type: XCORE_OP_REG + reg: r8 + diff --git a/tests/features/skipdata.yaml b/tests/features/skipdata.yaml new file mode 100644 index 0000000000..133803d949 --- /dev/null +++ b/tests/features/skipdata.yaml @@ -0,0 +1,49 @@ +test_cases: + - + input: + bytes: [ 0x8d, 0x4c, 0x32, 0x08, 0x01, 0xd8, 0x81, 0xc6, 0x34, 0x12, 0x00, 0x00, 0x00, 0x91, 0x92 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_SKIPDATA ] + address: 0x1000 + expected: + insns: + - + asm_text: "lea ecx, [edx + esi + 8]" + - + asm_text: "add eax, ebx" + - + asm_text: "add esi, 0x1234" + - + asm_text: ".byte 0x00" + - + asm_text: "xchg ecx, eax" + - + asm_text: "xchg edx, eax" + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x5a, 0x0f, 0x1f, 0xff, 0xc2, 0x09, 0x80, 0x00, 0x00, 0x00, 0x07, 0xf7, 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x57, 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x57, 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x24, 0xb2, 0x4f, 0x00, 0x78 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_SKIPDATA ] + address: 0x1000 + expected: + insns: + - + asm_text: "andeq r0, r0, sp, ror #1" + - + asm_text: "svceq #0x5a1a00" + - + asm_text: "stmibeq r2, {r0, r1, r2, r3, r4, r8, r9, r10, r11, r12, sp, lr, pc} ^" + - + asm_text: "andeq r0, r0, r0, lsl #1" + - + asm_text: "bhs 0xffafec34" + - + asm_text: ".byte 0xff, 0xff, 0x7f, 0x57" + - + asm_text: ".byte 0xe3, 0x01, 0xff, 0xff" + - + asm_text: "rsceq r5, r11, pc, ror r7" + - + asm_text: "strhs r0, [r0], #-0xf0" + - + asm_text: "stmdavc r0, {r1, r4, r5, r7, r8, r9, r10, r11, lr}" diff --git a/tests/integration/CMakeLists.txt b/tests/integration/CMakeLists.txt new file mode 100644 index 0000000000..4aee948202 --- /dev/null +++ b/tests/integration/CMakeLists.txt @@ -0,0 +1,17 @@ +cmake_minimum_required(VERSION 3.15) + +# Old integration tests. +if (CAPSTONE_BUILD_LEGACY_TESTS) + enable_testing() + set(TEST_SOURCES test_skipdata.c test_iter.c) + if(CAPSTONE_X86_SUPPORT) + set(TEST_SOURCES ${TEST_SOURCES} test_customized_mnem.c) + endif() + + foreach(TSRC ${TEST_SOURCES}) + string(REGEX REPLACE ".c$" "" TBIN ${TSRC}) + add_executable(${TBIN} "${TESTS_INTEGRATION_DIR}/${TSRC}") + target_link_libraries(${TBIN} PRIVATE capstone) + add_test(NAME "legacy_${TBIN}" COMMAND ${TBIN}) + endforeach() +endif() diff --git a/tests/integration/README.md b/tests/integration/README.md new file mode 100644 index 0000000000..bac4202d1e --- /dev/null +++ b/tests/integration/README.md @@ -0,0 +1,12 @@ +This directory contains some test code to show how to use Capstone API. + +- test_iter.c: + This code shows how to use the API cs_disasm_iter() to decode one instruction at + a time inside a loop. + +- test_customized_mnem.c: + This code shows how to use MNEMONIC option to customize instruction mnemonic + at run-time, and then how to reset the engine to use the default mnemonic. + +- test_winkernel.cpp + This code shows how to use Capstone from a Windows driver. diff --git a/tests/test_customized_mnem.c b/tests/integration/test_customized_mnem.c similarity index 100% rename from tests/test_customized_mnem.c rename to tests/integration/test_customized_mnem.c diff --git a/tests/test_iter.c b/tests/integration/test_iter.c similarity index 100% rename from tests/test_iter.c rename to tests/integration/test_iter.c diff --git a/tests/test_skipdata.c b/tests/integration/test_skipdata.c similarity index 100% rename from tests/test_skipdata.c rename to tests/integration/test_skipdata.c diff --git a/tests/test_winkernel.cpp b/tests/integration/test_winkernel.cpp similarity index 100% rename from tests/test_winkernel.cpp rename to tests/integration/test_winkernel.cpp diff --git a/tests/issues/issues.yaml b/tests/issues/issues.yaml new file mode 100644 index 0000000000..fe7a8c5b12 --- /dev/null +++ b/tests/issues/issues.yaml @@ -0,0 +1,4817 @@ +test_cases: + - + input: + name: "issue 2323 eBPF bswap16 instruction" + bytes: [ 0xd7,0x53,0x3f,0x0c,0x10,0x00,0x00,0x00 ] + arch: "CS_ARCH_BPF" + options: [ CS_MODE_LITTLE_ENDIAN, CS_MODE_BPF_EXTENDED, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "bswap16 r3" + - + input: + name: "issue 2323 eBPF bswap32 instruction" + bytes: [ 0xd7,0x53,0x3f,0x0c,0x20,0x00,0x00,0x00 ] + arch: "CS_ARCH_BPF" + options: [ CS_MODE_LITTLE_ENDIAN, CS_MODE_BPF_EXTENDED, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "bswap32 r3" + - + input: + name: "issue 2323 eBPF bswap64 instruction" + bytes: [ 0xd7,0x53,0x3f,0x0c,0x40,0x00,0x00,0x00 ] + arch: "CS_ARCH_BPF" + options: [ CS_MODE_LITTLE_ENDIAN, CS_MODE_BPF_EXTENDED, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "bswap64 r3" + - + input: + name: "issue 2258 vcmpunordss incorrect read/modified register" + bytes: [ 0x62,0xd1,0x56,0x08,0xc2,0xca,0x03 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "vcmpunordss k1, xmm5, xmm10" + details: + x86: + operands: + - + type: X86_OP_REG + access: CS_AC_WRITE + - + type: X86_OP_REG + access: CS_AC_READ + - + type: X86_OP_REG + access: CS_AC_READ + - + input: + name: "issue 2062 repz Prefix" + bytes: [ 0xf3,0xc3 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "repz ret" + details: + x86: + prefix: [ X86_PREFIX_REP, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + - + input: + name: "issue 2007 RISCV64 instruction groups" + bytes: [ 0x63,0x04,0x03,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "beqz t1, 8" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t1 + - + type: RISCV_OP_IMM + imm: 0x8 + groups: [ branch_relative, jump ] + - + input: + name: "issue 2007 RISCV64 instruction groups" + bytes: [ 0x73,0x00,0x00,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ecall" + details: + groups: [ int ] + - + input: + name: "issue 2007 RISCV64 instruction groups" + bytes: [ 0xef,0x00,0x40,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "jal 4" + details: + riscv: + operands: + - + type: RISCV_OP_IMM + imm: 0x4 + groups: [ call ] + - + input: + name: "issue 2007 RISCV32 instruction groups" + bytes: [ 0x63,0x04,0x03,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "beqz t1, 8" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: t1 + - + type: RISCV_OP_IMM + imm: 0x8 + groups: [ branch_relative, jump ] + - + input: + name: "issue 2007 RISCV32 instruction groups" + bytes: [ 0x73,0x00,0x00,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ecall" + details: + groups: [ int ] + - + input: + name: "issue 2007 RISCV32 instruction groups" + bytes: [ 0xef,0x00,0x40,0x00 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "jal 4" + details: + riscv: + operands: + - + type: RISCV_OP_IMM + imm: 0x4 + groups: [ call ] + - + input: + name: "issue 2007 RISCV32 instruction groups" + bytes: [ 0x11,0x20 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.jal 4" + details: + riscv: + operands: + - + type: RISCV_OP_IMM + imm: 0x4 + groups: [ hasStdExtC, isrv32, call ] + - + input: + name: "issue 2007 RISCV32 instruction groups" + bytes: [ 0x91,0xc1 ] + arch: "CS_ARCH_RISCV" + options: [ CS_MODE_RISCV32, CS_MODE_RISCVC, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "c.beqz a1, 4" + details: + riscv: + operands: + - + type: RISCV_OP_REG + reg: a1 + - + type: RISCV_OP_IMM + imm: 0x4 + groups: [ hasStdExtC, branch_relative, jump ] + - + input: + name: "issue 1997 notrack jmp" + bytes: [ 0x3e,0xff,0xe0 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "notrack jmp rax" + - + input: + name: "issue 1997 notrack call" + bytes: [ 0x3e,0xff,0xd0 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "notrack call rax" + - + input: + name: "issue 1924 SME Index instruction alias printing is not always valid" + bytes: [ 0x02,0x00,0x9f,0xe0 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ld1w {za0h.s[w12, 2]}, p0/z, [x0]" + details: + aarch64: + operands: + - + type: AARCH64_OP_SME + sme: + type: AARCH64_SME_MATRIX_SLICE_REG + tile: za0.s + slice_reg: w12 + slice_offset_imm: 2 + is_vertical: -1 + access: CS_AC_WRITE + vas: AARCH64LAYOUT_VL_S + - + type: AARCH64_OP_PRED + pred_reg: p0 + access: CS_AC_READ + - + type: AARCH64_OP_MEM + mem_base: x0 + access: CS_AC_READ + regs_read: [ w12, p0, x0 ] + regs_write: [ za0.s ] + groups: [ HasSME ] + - + input: + name: "issue 1912 PPC register name" + bytes: [ 0x2d,0x03,0x00,0x80 ] + arch: "CS_ARCH_PPC" + options: [ CS_MODE_BIG_ENDIAN ] + address: 0x0 + expected: + insns: + - + asm_text: "cmpwi cr2, r3, 0x80" + - + input: + name: "issue 1912 PPC no register name" + bytes: [ 0x2d,0x03,0x00,0x80 ] + arch: "CS_ARCH_PPC" + options: [ CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME ] + address: 0x0 + expected: + insns: + - + asm_text: "cmpwi 2, 3, 0x80" + - + input: + name: "issue 1902 PPC psq_st negative displacement" + bytes: [ 0xf3,0xec,0x0f,0xf8 ] + arch: "CS_ARCH_PPC" + options: [ CS_MODE_32, CS_MODE_BIG_ENDIAN, CS_MODE_PS, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "psq_st f31, -8(r12), 0, 0" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: f31 + - + type: PPC_OP_MEM + mem_base: r12 + mem_disp: -8 + - + type: PPC_OP_IMM + imm: 0x0 + - + type: PPC_OP_IMM + imm: 0x0 + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x21,0x04,0x03,0x5e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov b1, v1.b[1]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_B + vector_index: 1 + vector_index_is_set: true + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0xc0,0x1e,0x03,0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov v0.b[1], w22" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_B + vector_index: 1 + vector_index_is_set: true + - + type: AARCH64_OP_REG + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0xc0,0x1e,0x06,0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov v0.h[1], w22" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_H + vector_index: 1 + vector_index_is_set: true + - + type: AARCH64_OP_REG + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0xc0,0x1e,0x0c,0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov v0.s[1], w22" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_S + vector_index: 1 + vector_index_is_set: true + - + type: AARCH64_OP_REG + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0xc0,0x1e,0x18,0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov v0.d[1], x22" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_D + vector_index: 1 + vector_index_is_set: true + - + type: AARCH64_OP_REG + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x20,0x0c,0x03,0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov v0.b[1], v1.b[1]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_B + vector_index: 1 + vector_index_is_set: true + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_B + vector_index: 1 + vector_index_is_set: true + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x20,0x14,0x06,0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov v0.h[1], v1.h[1]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_H + vector_index: 1 + vector_index_is_set: true + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_H + vector_index: 1 + vector_index_is_set: true + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x20,0x24,0x0c,0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov v0.s[1], v1.s[1]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_S + vector_index: 1 + vector_index_is_set: true + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_S + vector_index: 1 + vector_index_is_set: true + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x20,0x44,0x18,0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov v0.d[1], v1.d[1]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_D + vector_index: 1 + vector_index_is_set: true + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_D + vector_index: 1 + vector_index_is_set: true + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x20,0x3c,0x0c,0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov w0, v1.s[1]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_S + vector_index: 1 + vector_index_is_set: true + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x20,0x3c,0x0c,0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov w0, v1.s[1]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_S + vector_index: 1 + vector_index_is_set: true + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x20,0x3c,0x18,0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov x0, v1.d[1]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_D + vector_index: 1 + vector_index_is_set: true + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x20,0x3c,0x18,0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov x0, v1.d[1]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_D + vector_index: 1 + vector_index_is_set: true + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x00,0xc0,0x50,0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fmov z0.h, p0/m, #2.00000000" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_H + - + type: AARCH64_OP_PRED + - + type: AARCH64_OP_FP + fp: 2.0 + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x00,0xc0,0x79,0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fmov z0.h, #2.00000000" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_H + - + type: AARCH64_OP_FP + fp: 2.0 + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0xa1,0xca,0xf8,0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov z1.d, #0x55" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_D + - + type: AARCH64_OP_IMM + imm: 0x55 + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x21,0x44,0x81,0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov p1.b, p1.b" + details: + aarch64: + operands: + - + type: AARCH64_OP_PRED + vas: AARCH64LAYOUT_VL_B + - + type: AARCH64_OP_PRED + vas: AARCH64LAYOUT_VL_B + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x21,0x40,0x51,0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov z1.h, p1/m, #1" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_H + - + type: AARCH64_OP_PRED + - + type: AARCH64_OP_IMM + imm: 0x1 + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x21,0x00,0x51,0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov z1.h, p1/z, #1" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_H + - + type: AARCH64_OP_PRED + - + type: AARCH64_OP_IMM + imm: 0x1 + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x20,0xc0,0x38,0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov z0.b, #1" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_B + - + type: AARCH64_OP_IMM + imm: 0x1 + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x71,0x4a,0x01,0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov p1.b, p2/m, p3.b" + details: + aarch64: + operands: + - + type: AARCH64_OP_PRED + vas: AARCH64LAYOUT_VL_B + - + type: AARCH64_OP_PRED + - + type: AARCH64_OP_PRED + vas: AARCH64LAYOUT_VL_B + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x61,0x48,0x03,0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov p1.b, p2/z, p3.b" + details: + aarch64: + operands: + - + type: AARCH64_OP_PRED + vas: AARCH64LAYOUT_VL_B + - + type: AARCH64_OP_PRED + - + type: AARCH64_OP_PRED + vas: AARCH64LAYOUT_VL_B + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x21,0xa8,0x28,0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov z1.b, p2/m, w1" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_B + - + type: AARCH64_OP_PRED + - + type: AARCH64_OP_REG + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x21,0x38,0x20,0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov z1.b, w1" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_B + - + type: AARCH64_OP_REG + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x01,0x88,0x20,0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov z1.b, p2/m, b0" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_B + - + type: AARCH64_OP_PRED + - + type: AARCH64_OP_REG + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x00,0x20,0x21,0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov z0.b, b0" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_B + - + type: AARCH64_OP_REG + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x00,0x20,0x23,0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov z0.b, z0.b[1]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_B + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_B + vector_index: 1 + vector_index_is_set: true + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x20,0xc4,0x20,0x05 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov z0.b, p1/m, z1.b" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_B + - + type: AARCH64_OP_PRED + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_B + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x20,0x30,0x61,0x04 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov z0.d, z1.d" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_D + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_D + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x40,0x44,0x42,0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "movs p0.b, p1/z, p2.b" + details: + aarch64: + operands: + - + type: AARCH64_OP_PRED + vas: AARCH64LAYOUT_VL_B + - + type: AARCH64_OP_PRED + - + type: AARCH64_OP_PRED + vas: AARCH64LAYOUT_VL_B + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x20,0x44,0xc1,0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "movs p0.b, p1.b" + details: + aarch64: + operands: + - + type: AARCH64_OP_PRED + vas: AARCH64LAYOUT_VL_B + - + type: AARCH64_OP_PRED + vas: AARCH64LAYOUT_VL_B + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x40,0x46,0x01,0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "not p0.b, p1/z, p2.b" + details: + aarch64: + operands: + - + type: AARCH64_OP_PRED + vas: AARCH64LAYOUT_VL_B + - + type: AARCH64_OP_PRED + - + type: AARCH64_OP_PRED + vas: AARCH64LAYOUT_VL_B + - + input: + name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions" + bytes: [ 0x40,0x46,0x41,0x25 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "nots p0.b, p1/z, p2.b" + details: + aarch64: + operands: + - + type: AARCH64_OP_PRED + vas: AARCH64LAYOUT_VL_B + - + type: AARCH64_OP_PRED + - + type: AARCH64_OP_PRED + vas: AARCH64LAYOUT_VL_B + - + input: + name: "issue 1856 AArch64 SYS instruction operands: tlbi 1 op" + bytes: [ 0x1f,0x83,0x08,0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "tlbi vmalle1is" + details: + aarch64: + operands: + - + type: AARCH64_OP_SYSREG + sub_type: AARCH64_OP_TLBI + sys_raw_val: 0x418 + - + input: + name: "issue 1856 AArch64 SYS instruction operands: tlbi 2 op" + bytes: [ 0x22,0x87,0x08,0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "tlbi vae1, x2" + details: + aarch64: + operands: + - + type: AARCH64_OP_SYSREG + sub_type: AARCH64_OP_TLBI + sys_raw_val: 0x439 + - + type: AARCH64_OP_REG + - + input: + name: "issue 1856 AArch64 SYS instruction operands: at" + bytes: [ 0xc0,0x78,0x0c,0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "at s12e0r, x0" + details: + aarch64: + operands: + - + type: AARCH64_OP_SYSALIAS + sub_type: AARCH64_OP_AT + sys_raw_val: 0x23c6 + - + type: AARCH64_OP_REG + - + input: + name: "issue 1856 AArch64 SYS instruction operands: dc" + bytes: [ 0x22,0x7b,0x0b,0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "dc cvau, x2" + details: + aarch64: + operands: + - + type: AARCH64_OP_SYSALIAS + sub_type: AARCH64_OP_DC + sys_raw_val: 0x1bd9 + - + type: AARCH64_OP_REG + - + input: + name: "issue 1856 AArch64 SYS instruction operands: ic" + bytes: [ 0x20,0x75,0x0b,0xd5 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ic ivau, x0" + details: + aarch64: + operands: + - + type: AARCH64_OP_SYSREG + sub_type: AARCH64_OP_IC + sys_raw_val: 0x1ba9 + - + type: AARCH64_OP_REG + - + input: + name: "issue 1843 AArch64 missing VAS specifiers in aliased instructions: mov 16b" + bytes: [ 0x40,0x1e,0xb2,0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov v0.16b, v18.16b" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: q0 + is_vreg: 1 + vas: AARCH64LAYOUT_VL_16B + - + type: AARCH64_OP_REG + reg: q18 + is_vreg: 1 + vas: AARCH64LAYOUT_VL_16B + - + input: + name: "issue 1843 AArch64 missing VAS specifiers in aliased instructions: mov 8b" + bytes: [ 0x40,0x1e,0xb2,0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov v0.8b, v18.8b" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: d0 + is_vreg: 1 + vas: AARCH64LAYOUT_VL_8B + - + type: AARCH64_OP_REG + reg: d18 + is_vreg: 1 + vas: AARCH64LAYOUT_VL_8B + - + input: + name: "issue 1843 AArch64 missing VAS specifiers in aliased instructions: mvn 16b" + bytes: [ 0x40,0x5a,0x20,0x6e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mvn v0.16b, v18.16b" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: q0 + is_vreg: 1 + vas: AARCH64LAYOUT_VL_16B + - + type: AARCH64_OP_REG + reg: q18 + is_vreg: 1 + vas: AARCH64LAYOUT_VL_16B + - + input: + name: "issue 1843 AArch64 missing VAS specifiers in aliased instructions: mvn 8b" + bytes: [ 0x40,0x5a,0x20,0x2e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mvn v0.8b, v18.8b" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: d0 + is_vreg: 1 + vas: AARCH64LAYOUT_VL_8B + - + type: AARCH64_OP_REG + reg: d18 + is_vreg: 1 + vas: AARCH64LAYOUT_VL_8B + - + input: + name: "issue 1839 AArch64 Incorrect detailed disassembly of ldr" + bytes: [ 0x41,0x00,0x40,0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldr x1, [x2]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + access: CS_AC_WRITE + - + type: AARCH64_OP_MEM + access: CS_AC_READ + - + input: + name: "issue 1827 x16 lcall seg:off format" + bytes: [ 0xb8,0x01,0x00,0x00,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov eax, 1" + - + input: + name: "issue 1827 x16 lcall seg:off format" + bytes: [ 0xb9,0x00,0x00,0x00,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov ecx, 0" + - + input: + name: "issue 1827 x16 lcall seg:off format" + bytes: [ 0x80,0xb8,0x01,0x00,0x00,0x00,0xb9 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "cmp byte ptr [eax + 1], 0xb9" + - + input: + name: "issue 1827 x16 lcall seg:off format" + bytes: [ 0x00,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "add byte ptr [eax], al" + - + input: + name: "issue 1827 x16 lcall seg:off format" + bytes: [ 0x01,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "add dword ptr [eax], eax" + - + input: + name: "issue 1827 x16 lcall seg:off format" + bytes: [ 0x33,0xc0 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_16, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "xor ax, ax" + - + input: + name: "issue 1827 x16 lcall seg:off format" + bytes: [ 0xba,0x5a,0xff ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_16, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov dx, 0xff5a" + - + input: + name: "issue 1710 M68K floating point immediates broken on big endian hosts" + bytes: [ 0xf2,0x3c,0x44,0x22,0x40,0x49,0x0e,0x56 ] + arch: "CS_ARCH_M68K" + options: [ CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + address: 0x0 + expected: + insns: + - + asm_text: "fadd.s #3.141500, fp0" + - + input: + name: "issue 1708 M68K floating point loads and stores generate the same op_str" + bytes: [ 0xf2,0x27,0x74,0x00 ] + arch: "CS_ARCH_M68K" + options: [ CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + address: 0x0 + expected: + insns: + - + asm_text: "fmove.d fp0, -(a7)" + - + input: + name: "issue 1708 M68K floating point loads and stores generate the same op_str" + bytes: [ 0xf2,0x1f,0x54,0x80 ] + arch: "CS_ARCH_M68K" + options: [ CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + address: 0x0 + expected: + insns: + - + asm_text: "fmove.d (a7)+, fp1" + - + input: + name: "issue 1708 M68K floating point loads and stores generate the same op_str" + bytes: [ 0x4e,0x75 ] + arch: "CS_ARCH_M68K" + options: [ CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + address: 0x0 + expected: + insns: + - + asm_text: "rts" + - + input: + name: "issue 1661 M68K invalid transfer direction in MOVEC instruction" + bytes: [ 0x4E,0x7A,0x00,0x02 ] + arch: "CS_ARCH_M68K" + options: [ CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + address: 0x0 + expected: + insns: + - + asm_text: "movec cacr, d0" + - + input: + name: "issue 1643 M68K incorrect read of 32-bit imm for bsr" + bytes: [ 0x61,0xff,0x00,0x00,0x0b,0xea ] + arch: "CS_ARCH_M68K" + options: [ CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + address: 0x0 + expected: + insns: + - + asm_text: "bsr.l $bec" + - + input: + name: "issue 1627 Arm64 LD1 missing immediate operand" + bytes: [ 0xe0,0x73,0xdf,0x0c ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ld1 { v0.8b }, [sp], #8" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_8B + - + type: AARCH64_OP_MEM + mem_base: sp + mem_disp: 0x8 + access: CS_AC_READ + - + input: + name: "issue 1587 ARM thumb pushed registers write" + bytes: [ 0x2d,0xe9,0xf0,0x47 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "push.w {r4, r5, r6, r7, r8, r9, r10, lr}" + details: + arm: + operands: + - + type: ARM_OP_REG + access: CS_AC_READ + - + type: ARM_OP_REG + access: CS_AC_READ + - + type: ARM_OP_REG + access: CS_AC_READ + - + type: ARM_OP_REG + access: CS_AC_READ + - + type: ARM_OP_REG + access: CS_AC_READ + - + type: ARM_OP_REG + access: CS_AC_READ + - + type: ARM_OP_REG + access: CS_AC_READ + - + type: ARM_OP_REG + access: CS_AC_READ + - + input: + name: "issue 1504 movhps qword ptr" + bytes: [ 0x0f,0x16,0x08 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "movhps xmm1, qword ptr [rax]" + details: + x86: + opcode: [ 0x0f, 0x16, 0x00, 0x00 ] + - + input: + name: "issue 1505 opcode 0f" + bytes: [ 0x0f,0xa5,0xc2 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "shld edx, eax, cl" + details: + x86: + opcode: [ 0x0f, 0xa5, 0x00, 0x00 ] + - + input: + name: "issue 1478 tbegin." + bytes: [ 0x7c,0x20,0x05,0x1d ] + arch: "CS_ARCH_PPC" + options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "tbegin. 1" + details: + ppc: + update_cr0: 1 + - + input: + name: "issue 970 PPC bdnzt lt" + bytes: [ 0x41,0x00,0xff,0xac ] + arch: "CS_ARCH_PPC" + options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "bdnzt lt, 0xffffffffffffffac" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: "0" + - + type: PPC_OP_IMM + imm: -0x54 + - + input: + name: "issue 970 PPC bdnzt eq" + bytes: [ 0x41,0x02,0xff,0xac ] + arch: "CS_ARCH_PPC" + options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "bdnzt eq, 0xffffffffffffffac" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: "2" + - + type: PPC_OP_IMM + imm: -0x54 + - + input: + name: "issue 969 PPC bdnzflr operand 2" + bytes: [ 0x4c,0x10,0x00,0x20 ] + arch: "CS_ARCH_PPC" + options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "bdnzflr 4*cr4+lt" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: "16" + - + input: + name: "issue 1481 AARCH64 LDR operand2" + bytes: [ 0xe9,0x03,0x40,0xf9 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldr x9, [sp]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + - + type: AARCH64_OP_MEM + mem_base: sp + - + input: + name: "issue 968 PPC absolute branch: bdnzla" + bytes: [ 0x42,0x00,0x12,0x37 ] + arch: "CS_ARCH_PPC" + options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN ] + address: 0x1000 + expected: + insns: + - + asm_text: "bcla 0x10, lt, 0x1234" + - + input: + name: "issue 968 PPC absolute branch: bdzla" + bytes: [ 0x42,0x40,0x12,0x37 ] + arch: "CS_ARCH_PPC" + options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN ] + address: 0x1000 + expected: + insns: + - + asm_text: "bcla 0x12, lt, 0x1234" + - + input: + name: "issue X86 xrelease xchg" + bytes: [ 0xf3,0x87,0x03 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "xrelease xchg dword ptr [ebx], eax" + - + input: + name: "issue X86 xacquire xchg" + bytes: [ 0xf2,0x87,0x03 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "xacquire xchg dword ptr [ebx], eax" + - + input: + name: "issue X86 xrelease" + bytes: [ 0xf3,0xf0,0x31,0x1f ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "xrelease lock xor dword ptr [rdi], ebx" + - + input: + name: "issue 1477 X86 xacquire" + bytes: [ 0xf2,0xf0,0x31,0x1f ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "xacquire lock xor dword ptr [rdi], ebx" + - + input: + name: "issue PPC JUMP group" + bytes: [ 0x41,0x82,0x00,0x10 ] + arch: "CS_ARCH_PPC" + options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "bt eq, 0x10" + details: + groups: [ jump, branch_relative ] + - + input: + name: "issue 1468 PPC bdnz" + bytes: [ 0x42,0x00,0xff,0xf8 ] + arch: "CS_ARCH_PPC" + options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN ] + address: 0x101086c + expected: + insns: + - + asm_text: "bc 0x10, lt, 0x1010864" + - + input: + name: "issue PPC bdnzt" + bytes: [ 0x41,0x00,0xff,0xac ] + arch: "CS_ARCH_PPC" + options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN ] + address: 0x1000 + expected: + insns: + - + asm_text: "bdnzt lt, 0xfac" + - + input: + name: "issue 1469 PPC CRx" + bytes: [ 0x4c,0x02,0x39,0x82 ] + arch: "CS_ARCH_PPC" + options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "crxor lt, eq, 4*cr1+un" + details: + ppc: + operands: + - + type: PPC_OP_REG + reg: "0" + - + type: PPC_OP_REG + reg: "2" + - + type: PPC_OP_REG + reg: "7" + - + input: + name: "issue 1468 B target" + bytes: [ 0x4b,0xff,0xf8,0x00 ] + arch: "CS_ARCH_PPC" + options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN ] + address: 0x1000 + expected: + insns: + - + asm_text: "b 0x800" + - + input: + name: "issue 1456 test alt 1" + bytes: [ 0xf6,0x08,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "test byte ptr [eax], 0" + - + input: + name: "issue 1456 test alt 2" + bytes: [ 0xf7,0x08,0x00,0x00,0x00,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "test dword ptr [eax], 0" + - + input: + name: "issue 1472 lock sub" + bytes: [ 0xF0,0x2B,0x45,0x08 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "lock sub eax, dword ptr [ebp + 8]" + - + input: + name: "issue 1472 lock or" + bytes: [ 0xF0,0x0B,0x45,0x08 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "lock or eax, dword ptr [ebp + 8]" + - + input: + name: "issue 1472 lock and" + bytes: [ 0xF0,0x23,0x45,0x08 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "lock and eax, dword ptr [ebp + 8]" + - + input: + name: "issue 1472 lock add" + bytes: [ 0xF0,0x03,0x45,0x08 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "lock add eax, dword ptr [ebp + 8]" + - + input: + name: "issue 1456 MOV dr" + bytes: [ 0x0f,0x23,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "mov dr0, eax" + - + input: + name: "issue 1456 MOV dr" + bytes: [ 0x0f,0x21,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "mov eax, dr0" + - + input: + name: "issue 1456 MOV cr" + bytes: [ 0x0f,0x22,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "mov cr0, eax" + - + input: + name: "issue 1472 lock adc" + bytes: [ 0xf0,0x12,0x45,0x08 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "lock adc al, byte ptr [ebp + 8]" + - + input: + name: "issue 1456 xmmword" + bytes: [ 0x66,0x0f,0x2f,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "comisd xmm0, xmmword ptr [eax]" + - + input: + name: "issue 1456 ARM printPKHASRShiftImm" + bytes: [ 0xca,0xea,0x21,0x06 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB ] + address: 0x0 + expected: + insns: + - + asm_text: "pkhtb r6, r10, r1, asr #0x20" + - + input: + name: "issue 1456 EIZ" + bytes: [ 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "lea esi, [esi]" + - + input: + name: "issue 1456 ARM POP" + bytes: [ 0x04,0x10,0x9d,0xe4 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_LITTLE_ENDIAN ] + address: 0x0 + expected: + insns: + - + asm_text: "pop {r1}" + - + input: + name: "issue 1456" + bytes: [ 0x31,0x02,0xa0,0xe1 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "lsr r0, r1, r2" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r0 + - + type: ARM_OP_REG + reg: r1 + - + type: ARM_OP_REG + reg: r2 + - + input: + name: "issue 1456" + bytes: [ 0x0c,0x00,0x80,0x12 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov w12, #-1" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + reg: w12 + - + type: AARCH64_OP_IMM + imm: -1 + - + input: + name: "issue 1456" + bytes: [ 0xb8,0x00,0x00,0x00,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_SYNTAX_ATT ] + address: 0x0 + expected: + insns: + - + asm_text: "movl $0, %eax" + - + input: + name: "issue 1456" + bytes: [ 0xd1,0x5e,0x48 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_SYNTAX_ATT ] + address: 0x0 + expected: + insns: + - + asm_text: "rcrl $1, 0x48(%esi)" + - + input: + name: "issue 1456" + bytes: [ 0xd1,0x5e,0x48 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "rcr dword ptr [esi + 0x48], 1" + - + input: + name: "issue 1456" + bytes: [ 0xd1,0x5e,0x48 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_SYNTAX_ATT ] + address: 0x0 + expected: + insns: + - + asm_text: "rcrl $1, 0x48(%esi)" + - + input: + name: "issue 1456" + bytes: [ 0x62,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "bound eax, qword ptr [eax]" + - + input: + name: "issue 1454" + bytes: [ 0xf0,0x0f,0xb1,0x1e ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "lock cmpxchg dword ptr [esi], ebx" + details: + regs_read: [ eax, esi, ebx ] + - + input: + name: "issue 1452" + bytes: [ 0x20,0x3c,0x0c,0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov w0, v1.s[1]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_S + - + input: + name: "issue 1452" + bytes: [ 0x20,0x3c,0x18,0x4e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov x0, v1.d[1]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_D + - + input: + name: "issue 1452" + bytes: [ 0x20,0x3c,0x03,0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "umov w0, v1.b[1]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_B + - + input: + name: "issue 1452" + bytes: [ 0x20,0x3c,0x06,0x0e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "umov w0, v1.h[1]" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + - + type: AARCH64_OP_REG + vas: AARCH64LAYOUT_VL_H + - + input: + name: "issue 1211" + bytes: [ 0xc4,0xe1,0xf8,0x90,0xc0 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "kmovq k0, k0" + - + input: + name: "issue 1211" + bytes: [ 0xc4,0xe1,0xfb,0x92,0xc3 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "kmovq k0, rbx" + - + input: + name: "issue 1211" + bytes: [ 0x62,0xf1,0x7d,0x48,0x74,0x83,0x12,0x00,0x00,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "vpcmpeqb k0, zmm0, zmmword ptr [rbx + 0x12]" + - + input: + name: "issue 1211" + bytes: [ 0x62,0xf2,0x7d,0x48,0x30,0x43,0x08 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "vpmovzxbw zmm0, ymmword ptr [rbx + 0x100]" + - + input: + name: "issue x86 BND register (OSS-fuzz #13467)" + bytes: [ 0x0f,0x1a,0x1a ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "bndldx bnd3, [edx]" + details: + x86: + operands: + - + type: X86_OP_REG + reg: bnd3 + - + type: X86_OP_MEM + - + input: + name: "issue 1335" + bytes: [ 0x0f,0x1f,0xc0 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "nop eax" + - + input: + name: "issue 1335" + bytes: [ 0x48,0x0f,0x1f,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "nop qword ptr [rax]" + - + input: + name: "issue 1259" + bytes: [ 0x0f,0x0d,0x44,0x11,0x40 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "prefetch byte ptr [rcx + rdx + 0x40]" + - + input: + name: "issue 1259" + bytes: [ 0x41,0x0f,0x0d,0x44,0x12,0x40 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "prefetch byte ptr [r10 + rdx + 0x40]" + - + input: + name: "issue 1304" + bytes: [ 0x66,0x0f,0x7f,0x4c,0x24,0x40 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "movdqa xmmword ptr [rsp + 0x40], xmm1" + details: + x86: + operands: + - + type: X86_OP_MEM + access: CS_AC_WRITE + - + type: X86_OP_REG + access: CS_AC_READ + - + input: + name: "issue 1304" + bytes: [ 0x66,0x0f,0x7e,0x04,0x24 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "movd dword ptr [rsp], xmm0" + details: + x86: + operands: + - + type: X86_OP_MEM + access: CS_AC_WRITE + - + type: X86_OP_REG + access: CS_AC_READ + - + input: + name: "issue 1304" + bytes: [ 0xf3,0x41,0x0f,0x7f,0x4d,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "movdqu xmmword ptr [r13], xmm1" + details: + x86: + operands: + - + type: X86_OP_MEM + access: CS_AC_WRITE + - + type: X86_OP_REG + access: CS_AC_READ + - + input: + name: "issue 1346" + bytes: [ 0xf3,0x48,0x0f,0x1e,0xc8 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "rdsspq rax" + - + input: + name: "issue 1346" + bytes: [ 0xf3,0x0f,0x1e,0xc8 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "rdsspd eax" + - + input: + name: "issue 1346" + bytes: [ 0xf3,0x48,0x0f,0xae,0xe8 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "incsspq rax" + - + input: + name: "issue 1346" + bytes: [ 0xf3,0x0f,0xae,0xe8 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "incsspd eax" + - + input: + name: "issue 1346" + bytes: [ 0xf3,0x0f,0x01,0xea ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "saveprevssp" + - + input: + name: "issue 1346" + bytes: [ 0xf3,0x0f,0x01,0x28 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "rstorssp dword ptr [rax]" + - + input: + name: "issue 1346" + bytes: [ 0x67,0xf3,0x0f,0x01,0x28 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "rstorssp dword ptr [eax]" + - + input: + name: "issue 1346" + bytes: [ 0x48,0x0f,0x38,0xf6,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "wrssq qword ptr [rax], rax" + - + input: + name: "issue 1346" + bytes: [ 0x67,0x0f,0x38,0xf6,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "wrssd dword ptr [eax], eax" + - + input: + name: "issue 1346" + bytes: [ 0xf3,0x0f,0x01,0xe8 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "setssbsy" + - + input: + name: "issue 1346" + bytes: [ 0xf3,0x0f,0xae,0x30 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "clrssbsy dword ptr [rax]" + - + input: + name: "issue 1346" + bytes: [ 0x67,0xf3,0x0f,0xae,0x30 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "clrssbsy dword ptr [eax]" + - + input: + name: "issue 1206" + bytes: [ 0xc4,0xe2,0x7d,0x5a,0x0c,0x0e ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "vbroadcasti128 ymm1, xmmword ptr [rsi + rcx]" + - + input: + name: "issue xchg 16bit" + bytes: [ 0x91 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_16 ] + address: 0x0 + expected: + insns: + - + asm_text: "xchg cx, ax" + - + input: + name: "issue ROL 1, ATT syntax" + bytes: [ 0x66,0x48,0xf3,0xd1,0xc0 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_SYNTAX_ATT ] + address: 0x0 + expected: + insns: + - + asm_text: "rolw $1, %ax" + - + input: + name: "issue 1129" + bytes: [ 0xf3,0x0f,0x1e,0xfa ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "endbr64" + - + input: + name: "issue 1129" + bytes: [ 0xf3,0x0f,0x1e,0xfa ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "endbr64" + - + input: + name: "issue 1129" + bytes: [ 0xf3,0x0f,0x1e,0xfb ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "endbr32" + - + input: + name: "issue 1129" + bytes: [ 0xf3,0x0f,0x1e,0xfb ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "endbr32" + - + input: + name: "issue x64 jmp" + bytes: [ 0xeb,0xfe ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x1000 + expected: + insns: + - + asm_text: "jmp 0x1000" + - + input: + name: "issue x64att jmp" + bytes: [ 0xeb,0xfe ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_SYNTAX_ATT ] + address: 0x1000 + expected: + insns: + - + asm_text: "jmp 0x1000" + - + input: + name: "issue x32 jmp" + bytes: [ 0xeb,0xfe ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x1000 + expected: + insns: + - + asm_text: "jmp 0x1000" + - + input: + name: "issue x32att jmp" + bytes: [ 0xeb,0xfe ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_SYNTAX_ATT ] + address: 0x1000 + expected: + insns: + - + asm_text: "jmp 0x1000" + - + input: + name: "issue 1389" + bytes: [ 0x66,0x0f,0x73,0xf9,0x01 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "pslldq xmm1, 1" + details: + x86: + operands: + - + type: X86_OP_REG + access: CS_AC_READ_WRITE + reg: xmm1 + - + type: X86_OP_IMM + size: 1 + imm: 1 + - + input: + name: "issue x64 unsigned" + bytes: [ 0x66,0x83,0xc0,0x80 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_UNSIGNED ] + address: 0x0 + expected: + insns: + - + asm_text: "add ax, 0xff80" + - + input: + name: "issue x64att unsigned" + bytes: [ 0x66,0x83,0xc0,0x80 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_SYNTAX_ATT, CS_OPT_UNSIGNED ] + address: 0x0 + expected: + insns: + - + asm_text: "addw $0xff80, %ax" + - + input: + name: "issue 1323" + bytes: [ 0x70,0x47,0x00 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "bx lr" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r14 + access: CS_AC_READ + regs_read: [ r14 ] + groups: [ jump, IsThumb ] + - + input: + name: "issue 1317" + bytes: [ 0xd0,0xe8,0x11,0xf0 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "tbh [r0, r1, lsl #1]" + details: + arm: + operands: + - + type: ARM_OP_MEM + mem_base: r0 + mem_index: r1 + access: CS_AC_READ + shift_type: ARM_SFT_LSL + shift_value: 1 + regs_read: [ r0, r1 ] + groups: [ jump, IsThumb2 ] + - + input: + name: "issue 1308" + bytes: [ 0x83,0x3d,0xa1,0x75,0x21,0x00,0x04 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "cmp dword ptr [rip + 0x2175a1], 4" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x83, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 8 + modrm: 0x3d + disp: 0x2175a1 + sib: 0x0 + operands: + - + type: X86_OP_MEM + mem_base: rip + mem_disp: 0x2175a1 + size: 4 + access: CS_AC_READ + - + type: X86_OP_IMM + imm: 0x4 + size: 4 + eflags: [ X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ] + regs_read: [ rip ] + regs_write: [ rflags ] + - + input: + name: "issue 1262" + bytes: [ 0x0f,0x95,0x44,0x24,0x5e ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "setne byte ptr [rsp + 0x5e]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x0f, 0x95, 0x00, 0x00 ] + rex: 0x0 + addr_size: 8 + modrm: 0x44 + disp: 0x5e + sib: 0x24 + sib_base: rsp + sib_scale: 1 + operands: + - + type: X86_OP_MEM + mem_base: rsp + mem_disp: 0x5e + size: 1 + access: CS_AC_WRITE + eflags: [ X86_EFLAGS_TEST_ZF ] + regs_read: [ rflags, rsp ] + - + input: + name: "issue 1262" + bytes: [ 0x0f,0x94,0x44,0x24,0x1f ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "sete byte ptr [rsp + 0x1f]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x0f, 0x94, 0x00, 0x00 ] + rex: 0x0 + addr_size: 8 + modrm: 0x44 + disp: 0x1f + sib: 0x24 + sib_base: rsp + sib_scale: 1 + operands: + - + type: X86_OP_MEM + mem_base: rsp + mem_disp: 0x1f + size: 1 + access: CS_AC_WRITE + eflags: [ X86_EFLAGS_TEST_ZF ] + regs_read: [ rflags, rsp ] + - + input: + name: "issue 1263" + bytes: [ 0x67,0x48,0x89,0x18 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "mov qword ptr [eax], rbx" + - + input: + name: "issue 1263" + bytes: [ 0x67,0x48,0x8b,0x03 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "mov rax, qword ptr [ebx]" + - + input: + name: "issue 1255" + bytes: [ 0xdb,0x7c,0x24,0x40 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fstp xword ptr [rsp + 0x40]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xdb, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 8 + modrm: 0x7c + disp: 0x40 + sib: 0x24 + sib_base: rsp + sib_scale: 1 + operands: + - + type: X86_OP_MEM + mem_base: rsp + mem_disp: 0x40 + size: 10 + access: CS_AC_WRITE + fpu_flags: [ X86_FPU_FLAGS_MODIFY_C1, X86_FPU_FLAGS_UNDEFINED_C0, X86_FPU_FLAGS_UNDEFINED_C2, X86_FPU_FLAGS_UNDEFINED_C3 ] + regs_read: [ rsp ] + regs_write: [ fpsw ] + groups: [ fpu ] + - + input: + name: "issue 1255" + bytes: [ 0xdd,0xd9 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fstp st(1)" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xdd, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 8 + modrm: 0xd9 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_REG + reg: st(1) + size: 10 + access: CS_AC_WRITE + eflags: [ X86_EFLAGS_MODIFY_CF, X86_EFLAGS_PRIOR_SF, X86_EFLAGS_PRIOR_AF, X86_EFLAGS_PRIOR_PF ] + regs_write: [ fpsw, st(1) ] + - + input: + name: "issue 1255" + bytes: [ 0xdf,0x7c,0x24,0x68 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fistp qword ptr [rsp + 0x68]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xdf, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 8 + modrm: 0x7c + disp: 0x68 + sib: 0x24 + sib_base: rsp + sib_scale: 1 + operands: + - + type: X86_OP_MEM + mem_base: rsp + mem_disp: 0x68 + size: 8 + access: CS_AC_WRITE + fpu_flags: [ X86_FPU_FLAGS_RESET_C1, X86_FPU_FLAGS_UNDEFINED_C0, X86_FPU_FLAGS_UNDEFINED_C2, X86_FPU_FLAGS_UNDEFINED_C3 ] + regs_read: [ rsp ] + regs_write: [ fpsw ] + groups: [ fpu ] + - + input: + name: "issue 1221" + bytes: [ 0x55,0x48,0x89,0xe5 ] + arch: "CS_ARCH_SPARC" + options: [ CS_MODE_BIG_ENDIAN ] + address: 0x0 + expected: + insns: + - + asm_text: "call 0x55222794" + - + input: + name: "issue 1144" + bytes: [ 0x00,0x00,0x02,0xb6 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_LITTLE_ENDIAN ] + address: 0x0 + expected: + insns: + - + asm_text: "tbz x0, #0x20, 0x4000" + - + input: + name: "issue 1144" + bytes: [ 0x00,0x00,0x04,0xb6 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_LITTLE_ENDIAN ] + address: 0x0 + expected: + insns: + - + asm_text: "tbz x0, #0x20, 0xffffffffffff8000" + - + input: + name: "issue 1144" + bytes: [ 0x00,0x00,0x02,0xb7 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_LITTLE_ENDIAN ] + address: 0x0 + expected: + insns: + - + asm_text: "tbnz x0, #0x20, 0x4000" + - + input: + name: "issue 1144" + bytes: [ 0x00,0x00,0x04,0xb7 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_LITTLE_ENDIAN ] + address: 0x0 + expected: + insns: + - + asm_text: "tbnz x0, #0x20, 0xffffffffffff8000" + - + input: + name: "issue 826" + bytes: [ 0x0b,0x00,0x00,0x0a ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "beq 0x34" + details: + arm: + operands: + - + type: ARM_OP_IMM + imm: 0x34 + cc: ARMCC_EQ + regs_read: [ cpsr ] + groups: [ jump, branch_relative, IsARM ] + - + input: + name: "issue 1047" + bytes: [ 0x48,0x83,0xe4,0xf0 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_SYNTAX_ATT ] + address: 0x0 + expected: + insns: + - + asm_text: "andq $0xfffffffffffffff0, %rsp" + - + input: + name: "issue 959" + bytes: [ 0xa0,0x28,0x57,0x88,0x7c ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "mov al, byte ptr [0x7c885728]" + - + input: + name: "issue 950" + bytes: [ 0x66,0xa3,0x94,0x90,0x04,0x08 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov word ptr [0x8049094], ax" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_OPSIZE, X86_PREFIX_0 ] + opcode: [ 0xa3, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x8049094 + sib: 0x0 + operands: + - + type: X86_OP_MEM + mem_disp: 0x8049094 + size: 2 + access: CS_AC_WRITE + - + type: X86_OP_REG + reg: ax + size: 2 + access: CS_AC_READ + regs_read: [ ax ] + - + input: + name: "issue 938" + bytes: [ 0x70,0x00,0xb2,0xff ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_MIPS64, CS_MODE_LITTLE_ENDIAN ] + address: 0x0 + expected: + insns: + - + asm_text: "sd $s2, 0x70($sp)" + - + input: + name: "issue 915" + bytes: [ 0xf0,0x0f,0x1f,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "lock nop dword ptr [rax]" + - + input: + name: "!# issue 913" + bytes: [ 0x04,0x10,0x9d,0xe4 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "pop {r1}" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_WRITE + writeback: 1 + regs_read: [ r13 ] + regs_write: [ r13, r1 ] + groups: [ IsARM ] + - + input: + name: "issue 884" + bytes: [ 0x64,0x48,0x03,0x04,0x25,0x00,0x00,0x00,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_SYNTAX_ATT ] + address: 0x0 + expected: + insns: + - + asm_text: "addq %fs:0, %rax" + - + input: + name: "issue 872" + bytes: [ 0xf2,0xeb,0x3e ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "bnd jmp 0x41" + - + input: + name: "issue 861" + bytes: [ 0x01,0x81,0xa0,0xfc ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "stc2 p1, c8, [r0], #4" + details: + arm: + operands: + - + type: ARM_OP_PIMM + imm: 1 + access: CS_AC_READ + - + type: ARM_OP_CIMM + imm: 8 + access: CS_AC_READ + - + type: ARM_OP_MEM + mem_base: r0 + mem_disp: 0x4 + access: CS_AC_WRITE + regs_read: [ r0 ] + groups: [ IsARM, PreV8 ] + - + input: + name: "issue 852" + bytes: [ 0x64,0xa3,0x00,0x00,0x00,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov dword ptr fs:[0], eax" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_FS, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xa3, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_MEM + mem_segment: fs + size: 4 + access: CS_AC_WRITE + - + type: X86_OP_REG + reg: eax + size: 4 + access: CS_AC_READ + regs_read: [ fs, eax ] + - + input: + name: "issue 825" + bytes: [ 0x0e,0xf0,0xa0,0xe1 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov pc, lr" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r15 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r14 + access: CS_AC_READ + regs_read: [ r14 ] + regs_write: [ r15 ] + groups: [ jump, return, IsARM ] + - + input: + name: "issue 813" + bytes: [ 0xF6,0xC0,0x04,0x01 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_MODE_BIG_ENDIAN ] + address: 0x0 + expected: + insns: + - + asm_text: "movt r4, #0x801" + - + input: + name: "issue 809" + bytes: [ 0x0f,0x29,0x8d,0xf0,0xfd,0xff,0xff ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "movaps xmmword ptr [rbp - 0x210], xmm1" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x0f, 0x29, 0x00, 0x00 ] + rex: 0x0 + addr_size: 8 + modrm: 0x8d + disp: -0x210 + sib: 0x0 + operands: + - + type: X86_OP_MEM + mem_base: rbp + mem_disp: -0x210 + size: 16 + access: CS_AC_WRITE + - + type: X86_OP_REG + reg: xmm1 + size: 16 + access: CS_AC_READ + regs_read: [ rbp, xmm1 ] + groups: [ sse1 ] + - + input: + name: "issue 807" + bytes: [ 0x4c,0x0f,0x00,0x80,0x16,0x76,0x8a,0xfe ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "sldt word ptr [rax - 0x17589ea]" + - + input: + name: "issue 806" + bytes: [ 0x0f,0x35 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "sysexit" + - + input: + name: "issue 805" + bytes: [ 0x48,0x4c,0x0f,0xb5,0x80,0x16,0x76,0x8a,0xfe ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_SYNTAX_ATT ] + address: 0x0 + expected: + insns: + - + asm_text: "lgs -0x17589ea(%rax), %r8" + - + input: + name: "issue 804" + bytes: [ 0x66,0x48,0xf3,0xd1,0xc0 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_SYNTAX_ATT ] + address: 0x0 + expected: + insns: + - + asm_text: "rolw $1, %ax" + - + input: + name: "issue 789" + bytes: [ 0x8e,0x1e ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_SYNTAX_ATT ] + address: 0x0 + expected: + insns: + - + asm_text: "movw (%rsi), %ds" + - + input: + name: "issue 767" + bytes: [ 0xb1,0xe8,0xfc,0x07 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldm.w r1!, {r2, r3, r4, r5, r6, r7, r8, r9, r10}" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_READ_WRITE + - + type: ARM_OP_REG + reg: r2 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r3 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r4 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r5 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r6 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r7 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r8 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r9 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r10 + access: CS_AC_WRITE + writeback: 1 + regs_read: [ r1 ] + regs_write: [ r1, r2, r3, r4, r5, r6, r7, r8, r9, r10 ] + groups: [ IsThumb2 ] + - + input: + name: "issue 760" + bytes: [ 0x02,0x80,0xbd,0xe8 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "pop {r1, pc}" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r15 + access: CS_AC_WRITE + writeback: 1 + regs_read: [ r13 ] + regs_write: [ r13, r1, r15 ] + groups: [ IsARM, return, jump ] + - + input: + name: "issue 750" + bytes: [ 0x0e,0x00,0x20,0xe9 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "stmdb r0!, {r1, r2, r3}" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_READ_WRITE + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r2 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r3 + access: CS_AC_READ + writeback: 1 + regs_read: [ r0, r1, r2, r3 ] + regs_write: [ r0 ] + groups: [ IsARM ] + - + input: + name: "issue 747" + bytes: [ 0x0e,0x00,0xb0,0xe8 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldm r0!, {r1, r2, r3}" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_READ_WRITE + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r2 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r3 + access: CS_AC_WRITE + writeback: 1 + regs_read: [ r0 ] + regs_write: [ r0, r1, r2, r3 ] + groups: [ IsARM ] + - + input: + name: "issue 747" + bytes: [ 0x0e,0xc8 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldm r0!, {r1, r2, r3}" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_READ_WRITE + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r2 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r3 + access: CS_AC_WRITE + writeback: 1 + regs_read: [ r0 ] + regs_write: [ r0, r1, r2, r3 ] + groups: [ IsThumb ] + - + input: + name: "issue 746" + bytes: [ 0x89,0x00,0x2d,0xe9 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "push {r0, r3, r7}" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r0 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r3 + access: CS_AC_READ + - + type: ARM_OP_REG + reg: r7 + access: CS_AC_READ + writeback: 1 + regs_read: [ r13, r0, r3, r7 ] + regs_write: [ r13 ] + groups: [ IsARM ] + - + input: + name: "issue 744" + bytes: [ 0x02,0x80,0xbd,0xe8 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "pop {r1, pc}" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r15 + access: CS_AC_WRITE + writeback: 1 + regs_read: [ r13 ] + regs_write: [ r13, r1, r15 ] + groups: [ IsARM, return, jump ] + - + input: + name: "issue 741" + bytes: [ 0x83,0xff,0xf7 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "cmp edi, -9" + - + input: + name: "issue 717" + bytes: [ 0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_SYNTAX_ATT ] + address: 0x0 + expected: + insns: + - + asm_text: "movq 0, %rax" + - + input: + name: "issue 711" + bytes: [ 0xa3,0x44,0xb0,0x00,0x10 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov dword ptr [0x1000b044], eax" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xa3, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x1000b044 + sib: 0x0 + operands: + - + type: X86_OP_MEM + mem_disp: 0x1000b044 + size: 4 + access: CS_AC_WRITE + - + type: X86_OP_REG + reg: eax + size: 4 + access: CS_AC_READ + regs_read: [ eax ] + - + input: + name: "issue 613" + bytes: [ 0xd9,0x74,0x24,0xd8 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "fnstenv [rsp - 0x28]" + - + input: + name: "issue 554" + bytes: [ 0xe7,0x84 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "out 0x84, eax" + - + input: + name: "issue 554" + bytes: [ 0xe5,0x8c ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "in eax, 0x8c" + - + input: + name: "issue 545" + bytes: [ 0x95 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "xchg ebp, eax" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x95, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_REG + reg: ebp + size: 4 + access: CS_AC_READ_WRITE + - + type: X86_OP_REG + reg: eax + size: 4 + access: CS_AC_READ_WRITE + regs_read: [ ebp, eax ] + regs_write: [ ebp, eax ] + groups: [ not64bitmode ] + - + input: + name: "issue 544" + bytes: [ 0xdf,0x30 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "fbstp tbyte ptr [eax]" + - + input: + name: "issue 544" + bytes: [ 0xdf,0x20 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "fbld tbyte ptr [eax]" + - + input: + name: "issue 541" + bytes: [ 0x48,0xb8,0x00,0x00,0x00,0x00,0x80,0xf8,0xff,0xff ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "movabs rax, 0xfffff88000000000" + - + input: + name: "issue 499" + bytes: [ 0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "movabs rax, 0x8000000000000000" + - + input: + name: "issue 492" + bytes: [ 0xff,0x18 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "call ptr [eax]" + - + input: + name: "issue 492" + bytes: [ 0xff,0x28 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "jmp ptr [eax]" + - + input: + name: "issue 492" + bytes: [ 0x0f,0xae,0x04,0x24 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "fxsave [esp]" + - + input: + name: "issue 492" + bytes: [ 0x0f,0xae,0x0c,0x24 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "fxrstor [esp]" + - + input: + name: "issue 470" + bytes: [ 0x0f,0x01,0x05,0xa0,0x90,0x04,0x08 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "sgdt [0x80490a0]" + - + input: + name: "issue 470" + bytes: [ 0x0f,0x01,0x0d,0xa7,0x90,0x04,0x08 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "sidt [0x80490a7]" + - + input: + name: "issue 470" + bytes: [ 0x0f,0x01,0x15,0xa0,0x90,0x04,0x08 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "lgdt [0x80490a0]" + - + input: + name: "issue 470" + bytes: [ 0x0f,0x01,0x1d,0xa7,0x90,0x04,0x08 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "lidt [0x80490a7]" + - + input: + name: "issue 459" + bytes: [ 0xd3,0x20,0x11,0xe1 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldrsb r2, [r1, -r3]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r2 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r1 + mem_index: r3 + mem_scale: 0 + access: CS_AC_READ + subtracted: 1 + regs_read: [ r1, r3 ] + regs_write: [ r2 ] + groups: [ IsARM ] + - + input: + name: "issue 456" + bytes: [ 0xe8,0x35,0x64 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_16 ] + address: 0x0 + expected: + insns: + - + asm_text: "call 0x6438" + - + input: + name: "issue 456" + bytes: [ 0xe9,0x35,0x64 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_16 ] + address: 0x0 + expected: + insns: + - + asm_text: "jmp 0x6438" + - + input: + name: "issue 456" + bytes: [ 0x66,0xe9,0x35,0x64,0x93,0x53 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_16 ] + address: 0x0 + expected: + insns: + - + asm_text: "jmp 0x5393643b" + - + input: + name: "issue 456" + bytes: [ 0x66,0xe8,0x35,0x64,0x93,0x53 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_16 ] + address: 0x0 + expected: + insns: + - + asm_text: "call 0x5393643b" + - + input: + name: "issue 456" + bytes: [ 0x66,0xe9,0x35,0x64,0x93,0x53 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_16 ] + address: 0x0 + expected: + insns: + - + asm_text: "jmp 0x5393643b" + - + input: + name: "issue 456" + bytes: [ 0x66,0xe8,0x35,0x64 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "call 0x6439" + - + input: + name: "issue 456" + bytes: [ 0xe9,0x35,0x64,0x93,0x53 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "jmp 0x5393643a" + - + input: + name: "issue 456" + bytes: [ 0x66,0xe9,0x35,0x64 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "jmp 0x6439" + - + input: + name: "issue 458" + bytes: [ 0xA1,0x12,0x34,0x90,0x90 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov eax, dword ptr [0x90903412]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xa1, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x90903412 + sib: 0x0 + operands: + - + type: X86_OP_REG + reg: eax + size: 4 + access: CS_AC_WRITE + - + type: X86_OP_MEM + mem_disp: 0x90903412 + size: 4 + access: CS_AC_READ + regs_write: [ eax ] + - + input: + name: "issue 454" + bytes: [ 0xf2,0x6c ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "repne insb byte ptr es:[edi], dx" + - + input: + name: "issue 454" + bytes: [ 0xf2,0x6d ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "repne insd dword ptr es:[edi], dx" + - + input: + name: "issue 454" + bytes: [ 0xf2,0x6e ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "repne outsb dx, byte ptr [esi]" + - + input: + name: "issue 454" + bytes: [ 0xf2,0x6f ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "repne outsd dx, dword ptr [esi]" + - + input: + name: "issue 454" + bytes: [ 0xf2,0xac ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "repne lodsb al, byte ptr [esi]" + - + input: + name: "issue 454" + bytes: [ 0xf2,0xad ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "repne lodsd eax, dword ptr [esi]" + - + input: + name: "issue 450" + bytes: [ 0xff,0x2d,0x34,0x35,0x23,0x01 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "jmp ptr [0x1233534]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xff, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x2d + disp: 0x1233534 + sib: 0x0 + operands: + - + type: X86_OP_MEM + mem_disp: 0x1233534 + size: 6 + groups: [ jump ] + - + input: + name: "issue 448" + bytes: [ 0xea,0x12,0x34,0x56,0x78,0x9a,0xbc ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ljmp 0xbc9a:0x78563412" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xea, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_IMM + imm: 0xbc9a + size: 2 + - + type: X86_OP_IMM + imm: 0x78563412 + size: 4 + groups: [ not64bitmode, jump ] + - + input: + name: "issue 426" + bytes: [ 0xbb,0x70,0x00,0x00 ] + arch: "CS_ARCH_SPARC" + options: [ CS_MODE_BIG_ENDIAN ] + address: 0x0 + expected: + insns: + - + asm_text: "popc %g0, %i5" + - + input: + name: "issue 358" + bytes: [ 0xe8,0xe3,0xf6,0xff,0xff ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "call 0xfffff6e8" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xe8, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_IMM + imm: 0xfffff6e8 + size: 4 + regs_read: [ esp, eip ] + regs_write: [ esp ] + groups: [ call, branch_relative, not64bitmode ] + - + input: + name: "issue 353" + bytes: [ 0xe6,0xa2 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "out 0xa2, al" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xe6, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_IMM + imm: 0xa2 + size: 1 + - + type: X86_OP_REG + reg: al + size: 1 + access: CS_AC_READ + regs_read: [ al ] + - + input: + name: "issue 305" + bytes: [ 0x34,0x8b ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "xor al, 0x8b" + - + input: + name: "issue 298" + bytes: [ 0xf3,0x90 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "pause" + - + input: + name: "issue 298" + bytes: [ 0x66,0xf3,0xf2,0x0f,0x59,0xff ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "mulsd xmm7, xmm7" + - + input: + name: "issue 294" + bytes: [ 0xc1,0xe6,0x08 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "shl esi, 8" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xc1, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0xe6 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_REG + reg: esi + size: 4 + access: CS_AC_READ_WRITE + - + type: X86_OP_IMM + imm: 0x8 + size: 1 + eflags: [ X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF, X86_EFLAGS_UNDEFINED_AF ] + regs_read: [ esi ] + regs_write: [ eflags, esi ] + - + input: + name: "issue 285" + bytes: [ 0x3c,0x12,0x80 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "cmp al, 0x12" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x3c, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_REG + reg: al + size: 1 + access: CS_AC_READ + - + type: X86_OP_IMM + imm: 0x12 + size: 1 + eflags: [ X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ] + regs_read: [ al ] + regs_write: [ eflags ] + - + input: + name: "issue 265" + bytes: [ 0x52,0xf8,0x23,0x30 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldr.w r3, [r2, r3, lsl #2]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r3 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r2 + mem_index: r3 + mem_scale: 0 + shift_type: ARM_SFT_LSL + shift_value: 2 + regs_read: [ r2, r3 ] + regs_write: [ r3 ] + groups: [ IsThumb2 ] + - + input: + name: "issue 264" + bytes: [ 0x0c,0xbf ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB ] + address: 0x0 + expected: + insns: + - + asm_text: "ite eq" + - + input: + name: "issue 264" + bytes: [ 0x17,0x20 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB ] + address: 0x0 + expected: + insns: + - + asm_text: "movs r0, #0x17" + - + input: + name: "issue 264" + bytes: [ 0x4f,0xf0,0xff,0x30 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB ] + address: 0x0 + expected: + insns: + - + asm_text: "mov.w r0, #0xffffffff" + - + input: + name: "issue 246" + bytes: [ 0x52,0xf8,0x23,0xf0 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB ] + address: 0x0 + expected: + insns: + - + asm_text: "ldr.w pc, [r2, r3, lsl #2]" + - + input: + name: "issue 232" + bytes: [ 0x8e,0x10 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov ss, word ptr [eax]" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0x8e, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x10 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_REG + reg: ss + size: 2 + access: CS_AC_WRITE + - + type: X86_OP_MEM + mem_base: eax + size: 2 + access: CS_AC_READ + regs_read: [ eax ] + regs_write: [ ss ] + groups: [ privilege ] + - + input: + name: "issue 231" + bytes: [ 0x66,0x6b,0xc0,0x02 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "imul ax, ax, 2" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_OPSIZE, X86_PREFIX_0 ] + opcode: [ 0x6b, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0xc0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_REG + reg: ax + size: 2 + access: CS_AC_WRITE + - + type: X86_OP_REG + reg: ax + size: 2 + access: CS_AC_READ + - + type: X86_OP_IMM + imm: 0x2 + size: 2 + eflags: [ X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_OF, X86_EFLAGS_UNDEFINED_ZF, X86_EFLAGS_UNDEFINED_PF, X86_EFLAGS_UNDEFINED_AF ] + regs_read: [ ax ] + regs_write: [ eflags, ax ] + - + input: + name: "issue 230" + bytes: [ 0xec ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "in al, dx" + details: + x86: + prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ] + opcode: [ 0xec, 0x00, 0x00, 0x00 ] + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + operands: + - + type: X86_OP_REG + reg: al + size: 1 + access: CS_AC_WRITE + - + type: X86_OP_REG + reg: dx + size: 2 + access: CS_AC_READ + regs_read: [ dx ] + regs_write: [ al ] + - + input: + name: "issue 213" + bytes: [ 0xea,0xaa,0xff,0x00,0xf0 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_16 ] + address: 0x0 + expected: + insns: + - + asm_text: "ljmp 0xf000:0xffaa" + - + input: + name: "issue 191" + bytes: [ 0xc5,0xe8,0xc2,0x33,0x9b ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "vcmpps xmm6, xmm2, xmmword ptr [rbx], 0x9b" + - + input: + name: "issue 176" + bytes: [ 0xfd,0xff,0xff,0x1a ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_ARM ] + address: 0x0 + expected: + insns: + - + asm_text: "bne 0xfffffffc" + - + input: + name: "issue 151" + bytes: [ 0x4d,0x8d,0x3d,0x02,0x00,0x00,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "lea r15, [rip + 2]" + - + input: + name: "issue 151" + bytes: [ 0xeb,0xb0 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "jmp 0xffffffffffffffb2" + - + input: + name: "issue 134" + bytes: [ 0xe7,0x92,0x11,0x80 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldr r1, [r2, r0, lsl #3]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r2 + mem_index: r0 + access: CS_AC_READ + shift_type: ARM_SFT_LSL + shift_value: 3 + regs_read: [ r2, r0 ] + regs_write: [ r1 ] + groups: [ IsARM ] + - + input: + name: "issue 133" + bytes: [ 0xed,0xdf,0x2b,0x1b ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "vldr d18, [pc, #0x6c]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: d18 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r15 + mem_disp: 0x6c + access: CS_AC_READ + regs_read: [ r15 ] + regs_write: [ d18 ] + groups: [ HasFPRegs ] + - + input: + name: "issue 132" + bytes: [ 0x49,0x19 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldr r1, [pc, #0x64]" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r1 + access: CS_AC_WRITE + - + type: ARM_OP_MEM + mem_base: r15 + mem_disp: 0x64 + access: CS_AC_READ + regs_read: [ r15 ] + regs_write: [ r1 ] + groups: [ IsThumb ] + - + input: + name: "issue 130" + bytes: [ 0xe1,0xa0,0xf0,0x0e ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov pc, lr" + details: + arm: + operands: + - + type: ARM_OP_REG + reg: r15 + access: CS_AC_WRITE + - + type: ARM_OP_REG + reg: r14 + access: CS_AC_READ + regs_read: [ r14 ] + regs_write: [ r15 ] + groups: [ jump, return, IsARM ] + - + input: + name: "issue 85" + bytes: [ 0xee,0x3f,0xbf,0x29 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_LITTLE_ENDIAN ] + address: 0x0 + expected: + insns: + - + asm_text: "stp w14, w15, [sp, #-8]!" + - + input: + name: "issue 82" + bytes: [ 0xf2,0x66,0xaf ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64 ] + address: 0x0 + expected: + insns: + - + asm_text: "repne scasw ax, word ptr [rdi]" + - + input: + name: "issue 35" + bytes: [ 0xe8,0xc6,0x02,0x00,0x00 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "call 0x2cb" + - + input: + name: "issue 8" + bytes: [ 0xff,0x8c,0xf9,0xff,0xff,0x9b,0xf9 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32 ] + address: 0x0 + expected: + insns: + - + asm_text: "dec dword ptr [ecx + edi*8 - 0x6640001]" + - + input: + name: "issue 29" + bytes: [ 0x00,0x00,0x00,0x4c ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM ] + address: 0x0 + expected: + insns: + - + asm_text: "st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]" + - + input: + name: "issue 2233 ARM write to PC is branch" + bytes: [ 0x87,0x46 ] + arch: "CS_ARCH_ARM" + options: [ CS_MODE_THUMB, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "mov pc, r0" + details: + groups: [ IsThumb, jump ] + - + input: + name: "issue 2128" + bytes: [ 0x4c,0x85,0x7d,0x30 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "test qword ptr [rbp + 0x30], r15" + details: + x86: + operands: + - + type: X86_OP_MEM + - + type: X86_OP_REG + reg: r15 + access: CS_AC_READ + regs_read: [ rbp, r15 ] + regs_write: [ rflags ] + - + input: + name: "issue 2079" + bytes: [ 0xd1,0x10 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_32, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "rcl dword ptr [eax]" + details: + x86: + operands: + - + type: X86_OP_MEM + mem_base: eax + - + type: X86_OP_IMM + imm: 0x1 + - + input: + name: "issue 2244" + bytes: [ 0xc5,0xfb,0xc2,0xda,0x06 ] + arch: "CS_ARCH_X86" + options: [ CS_MODE_64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "vcmpnlesd xmm3, xmm0, xmm2" + id: 797 + - + input: + name: "issue 2349" + bytes: [ 0xcf, 0x41, 0xd0, 0x28 ] + arch: "CS_ARCH_LOONGARCH" + options: [ CS_MODE_LOONGARCH64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ld.d $t3, $t2, 0x410" + details: + loongarch: + operands: + - + type: LOONGARCH_OP_REG + - + type: LOONGARCH_OP_MEM + mem_base: t2 + mem_disp: 0x410 + - + input: + name: "issue 2349" + bytes: [ 0x8d, 0x59, 0x10, 0x27 ] + arch: "CS_ARCH_LOONGARCH" + options: [ CS_MODE_LOONGARCH64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "stptr.d $t1, $t0, 0x1058" + details: + loongarch: + operands: + - + type: LOONGARCH_OP_REG + - + type: LOONGARCH_OP_MEM + mem_base: t0 + mem_disp: 0x1058 + - + input: + name: "issue 2349" + bytes: [ 0xa4, 0x15, 0x20, 0x30 ] + arch: "CS_ARCH_LOONGARCH" + options: [ CS_MODE_LOONGARCH64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "vldrepl.w $vr4, $t1, 0x14" + details: + loongarch: + operands: + - + type: LOONGARCH_OP_REG + - + type: LOONGARCH_OP_MEM + mem_base: t1 + mem_disp: 0x14 + - + input: + name: "issue 2349" + bytes: [ 0x68, 0x22, 0xc2, 0x2a ] + arch: "CS_ARCH_LOONGARCH" + options: [ CS_MODE_LOONGARCH64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "preld 8, $t7, 0x88" + details: + loongarch: + operands: + - + type: LOONGARCH_OP_IMM + imm: 0x8 + - + type: LOONGARCH_OP_MEM + mem_base: t7 + mem_disp: 0x88 + - + input: + name: "issue 2349" + bytes: [ 0xe1, 0x2c, 0x30, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ CS_MODE_LOONGARCH64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fldx.s $fa1, $a3, $a7" + details: + loongarch: + operands: + - + type: LOONGARCH_OP_REG + - + type: LOONGARCH_OP_MEM + mem_base: a3 + mem_index: a7 + - + input: + name: "issue 2349" + bytes: [ 0xc4, 0x14, 0x57, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ CS_MODE_LOONGARCH64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "sc.q $a0, $a1, $a2" + details: + loongarch: + operands: + - + type: LOONGARCH_OP_REG + reg: a0 + - + type: LOONGARCH_OP_REG + reg: a1 + - + type: LOONGARCH_OP_MEM + mem_base: a2 + - + input: + name: "issue 2349" + bytes: [ 0xc4, 0x14, 0x61, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ CS_MODE_LOONGARCH64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "amadd.w $a0, $a1, $a2" + details: + loongarch: + operands: + - + type: LOONGARCH_OP_REG + reg: a0 + - + type: LOONGARCH_OP_REG + reg: a1 + - + type: LOONGARCH_OP_MEM + mem_base: a2 + - + input: + name: "issue 2349" + bytes: [ 0xa4, 0x18, 0x78, 0x38 ] + arch: "CS_ARCH_LOONGARCH" + options: [ CS_MODE_LOONGARCH64, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "ldgt.b $a0, $a1, $a2" + details: + loongarch: + operands: + - + type: LOONGARCH_OP_REG + - + type: LOONGARCH_OP_MEM + mem_base: a1 + - + type: LOONGARCH_OP_REG + reg: a2 + - + input: + name: "issue 2268" + bytes: [ 0x00,0x80,0x58,0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fadd z0.h, p0/m, z0.h, #0.5" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + access: CS_AC_READ_WRITE + - + type: AARCH64_OP_PRED + access: CS_AC_READ + - + type: AARCH64_OP_REG + access: CS_AC_READ_WRITE + - + type: AARCH64_OP_SYSIMM + sub_type: AARCH64_OP_EXACTFPIMM + sys_raw_val: 1 + - + input: + name: "issue 2268" + bytes: [ 0x20,0x80,0x58,0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fadd z0.h, p0/m, z0.h, #1.0" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + access: CS_AC_READ_WRITE + - + type: AARCH64_OP_PRED + access: CS_AC_READ + - + type: AARCH64_OP_REG + access: CS_AC_READ_WRITE + - + type: AARCH64_OP_SYSIMM + sub_type: AARCH64_OP_EXACTFPIMM + sys_raw_val: 2 + - + input: + name: "issue 2268" + bytes: [ 0x3f,0x9c,0xda,0x65 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fmul z31.d, p7/m, z31.d, #2.0" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + access: CS_AC_READ_WRITE + - + type: AARCH64_OP_PRED + access: CS_AC_READ + - + type: AARCH64_OP_REG + access: CS_AC_READ_WRITE + - + type: AARCH64_OP_SYSIMM + sub_type: AARCH64_OP_EXACTFPIMM + sys_raw_val: 3 + - + input: + name: "issue 2268" + bytes: [ 0x6a,0xd9,0xf8,0x7e ] + arch: "CS_ARCH_AARCH64" + options: [ CS_MODE_ARM, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "fcmle h10, h11, #0.0" + details: + aarch64: + operands: + - + type: AARCH64_OP_REG + access: CS_AC_WRITE + - + type: AARCH64_OP_REG + access: CS_AC_READ + - + type: AARCH64_OP_SYSIMM + sub_type: AARCH64_OP_EXACTFPIMM + sys_raw_val: 0 + - + input: + name: "issue 2419" + bytes: [ 0x12,0xbf,0xff,0xff ] + arch: "CS_ARCH_SPARC" + options: [ CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "bne -4" + details: + sparc: + cc: SPARC_CC_ICC_NE diff --git a/tests/test_aarch64.c b/tests/test_aarch64.c deleted file mode 100644 index 3c0aa7afb3..0000000000 --- a/tests/test_aarch64.c +++ /dev/null @@ -1,370 +0,0 @@ -/* Capstone Disassembler Engine */ -/* By Nguyen Anh Quynh , 2013-2019 */ - -#include "capstone/aarch64.h" -#include -#include - -#include -#include - -static csh handle; - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - const char *comment; -}; - -static void print_string_hex(const char *comment, unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("%s", comment); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - - printf("\n"); -} - -static void print_insn_detail(cs_insn *ins) -{ - cs_aarch64 *aarch64; - int i; - cs_regs regs_read, regs_write; - unsigned char regs_read_count, regs_write_count; - unsigned char access; - - // detail can be NULL if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - aarch64 = &(ins->detail->aarch64); - if (aarch64->op_count) - printf("\top_count: %u\n", aarch64->op_count); - - for (i = 0; i < aarch64->op_count; i++) { - cs_aarch64_op *op = &(aarch64->operands[i]); - switch(op->type) { - default: - break; - case AARCH64_OP_REG: - printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); - break; - case AARCH64_OP_IMM: - printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); - break; - case AARCH64_OP_FP: -#if defined(_KERNEL_MODE) - // Issue #681: Windows kernel does not support formatting float point - printf("\t\toperands[%u].type: FP = \n", i); -#else - printf("\t\toperands[%u].type: FP = %f\n", i, op->fp); -#endif - break; - case AARCH64_OP_MEM: - printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.base != AARCH64_REG_INVALID) - printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base)); - if (op->mem.index != AARCH64_REG_INVALID) - printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index)); - if (op->mem.disp != 0) - printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); - if (ins->detail->aarch64.post_index) - printf("\t\t\tpost-indexed: true\n"); - - break; - case AARCH64_OP_SME: - printf("\t\toperands[%u].type: SME_MATRIX\n", i); - printf("\t\toperands[%u].sme.type: %d\n", i, op->sme.type); - - if (op->sme.tile != AARCH64_REG_INVALID) - printf("\t\toperands[%u].sme.tile: %s\n", i, cs_reg_name(handle, op->sme.tile)); - if (op->sme.slice_reg != AARCH64_REG_INVALID) - printf("\t\toperands[%u].sme.slice_reg: %s\n", i, cs_reg_name(handle, op->sme.slice_reg)); - if (op->sme.slice_offset.imm != -1 || op->sme.slice_offset.imm_range.first != -1) { - printf("\t\toperands[%u].sme.slice_offset: ", i); - if (op->sme.has_range_offset) - printf("%hhd:%hhd\n", op->sme.slice_offset.imm_range.first, op->sme.slice_offset.imm_range.offset); - else - printf("%d\n", op->sme.slice_offset.imm); - } - if (op->sme.slice_reg != AARCH64_REG_INVALID || op->sme.slice_offset.imm != -1) - printf("\t\toperands[%u].sme.is_vertical: %s\n", i, (op->sme.is_vertical ? "true" : "false")); - break; - case AARCH64_OP_PRED: - printf("\t\toperands[%u].type: PREDICATE\n", i); - if (op->pred.reg != AARCH64_REG_INVALID) - printf("\t\toperands[%u].pred.reg: %s\n", i, cs_reg_name(handle, op->pred.reg)); - if (op->pred.vec_select != AARCH64_REG_INVALID) - printf("\t\toperands[%u].pred.vec_select: %s\n", i, cs_reg_name(handle, op->pred.vec_select)); - if (op->pred.imm_index != -1) - printf("\t\toperands[%u].pred.imm_index: %d\n", i, op->pred.imm_index); - break; - case AARCH64_OP_CIMM: - printf("\t\toperands[%u].type: C-IMM = %u\n", i, (int)op->imm); - break; - case AARCH64_OP_SYSREG: - printf("\t\toperands[%u].type: SYS REG:\n", i); - switch (op->sysop.sub_type) { - default: - printf("Sub type %d not handled.\n", op->sysop.sub_type); - break; - case AARCH64_OP_REG_MRS: - printf("\t\toperands[%u].subtype: REG_MRS = 0x%x\n", i, op->sysop.reg.sysreg); - break; - case AARCH64_OP_REG_MSR: - printf("\t\toperands[%u].subtype: REG_MSR = 0x%x\n", i, op->sysop.reg.sysreg); - break; - case AARCH64_OP_TLBI: - printf("\t\toperands[%u].subtype TLBI = 0x%x\n", i, op->sysop.reg.tlbi); - break; - case AARCH64_OP_IC: - printf("\t\toperands[%u].subtype IC = 0x%x\n", i, op->sysop.reg.ic); - break; - } - break; - case AARCH64_OP_SYSALIAS: - printf("\t\toperands[%u].type: SYS ALIAS:\n", i); - switch (op->sysop.sub_type) { - default: - printf("Sub type %d not handled.\n", op->sysop.sub_type); - break; - case AARCH64_OP_SVCR: - if(op->sysop.alias.svcr == AARCH64_SVCR_SVCRSM) - printf("\t\t\toperands[%u].svcr: BIT = SM\n", i); - else if(op->sysop.alias.svcr == AARCH64_SVCR_SVCRZA) - printf("\t\t\toperands[%u].svcr: BIT = ZA\n", i); - else if(op->sysop.alias.svcr == AARCH64_SVCR_SVCRSMZA) - printf("\t\t\toperands[%u].svcr: BIT = SM & ZA\n", i); - break; - case AARCH64_OP_AT: - printf("\t\toperands[%u].subtype AT = 0x%x\n", i, op->sysop.alias.at); - break; - case AARCH64_OP_DB: - printf("\t\toperands[%u].subtype DB = 0x%x\n", i, op->sysop.alias.db); - break; - case AARCH64_OP_DC: - printf("\t\toperands[%u].subtype DC = 0x%x\n", i, op->sysop.alias.dc); - break; - case AARCH64_OP_ISB: - printf("\t\toperands[%u].subtype ISB = 0x%x\n", i, op->sysop.alias.isb); - break; - case AARCH64_OP_TSB: - printf("\t\toperands[%u].subtype TSB = 0x%x\n", i, op->sysop.alias.tsb); - break; - case AARCH64_OP_PRFM: - printf("\t\toperands[%u].subtype PRFM = 0x%x\n", i, op->sysop.alias.prfm); - break; - case AARCH64_OP_SVEPRFM: - printf("\t\toperands[%u].subtype SVEPRFM = 0x%x\n", i, op->sysop.alias.sveprfm); - break; - case AARCH64_OP_RPRFM: - printf("\t\toperands[%u].subtype RPRFM = 0x%x\n", i, op->sysop.alias.rprfm); - break; - case AARCH64_OP_PSTATEIMM0_15: - printf("\t\toperands[%u].subtype PSTATEIMM0_15 = 0x%x\n", i, op->sysop.alias.pstateimm0_15); - break; - case AARCH64_OP_PSTATEIMM0_1: - printf("\t\toperands[%u].subtype PSTATEIMM0_1 = 0x%x\n", i, op->sysop.alias.pstateimm0_1); - break; - case AARCH64_OP_PSB: - printf("\t\toperands[%u].subtype PSB = 0x%x\n", i, op->sysop.alias.psb); - break; - case AARCH64_OP_BTI: - printf("\t\toperands[%u].subtype BTI = 0x%x\n", i, op->sysop.alias.bti); - break; - case AARCH64_OP_SVEPREDPAT: - printf("\t\toperands[%u].subtype SVEPREDPAT = 0x%x\n", i, op->sysop.alias.svepredpat); - break; - case AARCH64_OP_SVEVECLENSPECIFIER: - printf("\t\toperands[%u].subtype SVEVECLENSPECIFIER = 0x%x\n", i, op->sysop.alias.sveveclenspecifier); - break; - } - break; - case AARCH64_OP_SYSIMM: - printf("\t\toperands[%u].type: SYS IMM:\n", i); - switch(op->sysop.sub_type) { - default: - printf("Sub type %d not handled.\n", op->sysop.sub_type); - break; - case AARCH64_OP_EXACTFPIMM: - printf("\t\toperands[%u].subtype EXACTFPIMM = %d\n", i, op->sysop.imm.exactfpimm); - break; - case AARCH64_OP_DBNXS: - printf("\t\toperands[%u].subtype DBNXS = %d\n", i, op->sysop.imm.dbnxs); - break; - } - break; - } - - access = op->access; - switch(access) { - default: - break; - case CS_AC_READ: - printf("\t\toperands[%u].access: READ\n", i); - break; - case CS_AC_WRITE: - printf("\t\toperands[%u].access: WRITE\n", i); - break; - case CS_AC_READ | CS_AC_WRITE: - printf("\t\toperands[%u].access: READ | WRITE\n", i); - break; - } - - if (op->shift.type != AARCH64_SFT_INVALID && - op->shift.value) - printf("\t\t\tShift: type = %u, value = %u\n", - op->shift.type, op->shift.value); - - if (op->ext != AARCH64_EXT_INVALID) - printf("\t\t\tExt: %u\n", op->ext); - - if (op->vas != AARCH64LAYOUT_INVALID) - printf("\t\t\tVector Arrangement Specifier: 0x%x\n", op->vas); - - if (op->vector_index != -1) - printf("\t\t\tVector Index: %u\n", op->vector_index); - } - - if (aarch64->update_flags) - printf("\tUpdate-flags: True\n"); - - if (ins->detail->writeback) - printf("\tWrite-back: True\n"); - - if (aarch64->cc != AArch64CC_Invalid) - printf("\tCode-condition: %u\n", aarch64->cc); - - // Print out all registers accessed by this instruction (either implicit or explicit) - if (!cs_regs_access(handle, ins, - regs_read, ®s_read_count, - regs_write, ®s_write_count)) { - if (regs_read_count) { - printf("\tRegisters read:"); - for(i = 0; i < regs_read_count; i++) { - printf(" %s", cs_reg_name(handle, regs_read[i])); - } - printf("\n"); - } - - if (regs_write_count) { - printf("\tRegisters modified:"); - for(i = 0; i < regs_write_count; i++) { - printf(" %s", cs_reg_name(handle, regs_write[i])); - } - printf("\n"); - } - } - - printf("\n"); -} - -static void test() -{ -#define AArch64_CODE "\x09\x00\x38\xd5" \ - "\xbf\x40\x00\xd5" \ - "\x0c\x05\x13\xd5" \ - "\x20\x50\x02\x0e" \ - "\x20\xe4\x3d\x0f" \ - "\x00\x18\xa0\x5f" \ - "\xa2\x00\xae\x9e" \ - "\x9f\x37\x03\xd5" \ - "\xbf\x33\x03\xd5" \ - "\xdf\x3f\x03\xd5" \ - "\x21\x7c\x02\x9b" \ - "\x21\x7c\x00\x53" \ - "\x00\x40\x21\x4b" \ - "\xe1\x0b\x40\xb9" \ - "\x20\x04\x81\xda" \ - "\x20\x08\x02\x8b" \ - "\x10\x5b\xe8\x3c" \ - "\xfd\x7b\xba\xa9" \ - "\xfd\xc7\x43\xf8" - - struct platform platforms[] = { - { - CS_ARCH_AARCH64, - CS_MODE_ARM, - (unsigned char *)AArch64_CODE, - sizeof(AArch64_CODE) - 1, - "AARCH64" - }, - }; - - uint64_t address = 0x2c; - cs_insn *insn; - int i; - size_t count; - - for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { - cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", err); - abort(); - } - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); - if (count) { - size_t j; - - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code: ", platforms[i].code, platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); - print_insn_detail(&insn[j]); - } - printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code: ", platforms[i].code, platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - abort(); - } - - printf("\n"); - - cs_close(&handle); - } -} - -int test_macros() { - assert(CS_AARCH64(_INS_BL) == AARCH64_INS_BL); - assert(CS_AARCH64pre(CS_ARCH_) == CS_ARCH_AARCH64); - assert(CS_AARCH64CC(_AL) == AArch64CC_AL); - assert(CS_AARCH64_VL_(16B) == AARCH64LAYOUT_VL_16B); - cs_detail detail = { 0 }; - CS_cs_aarch64() aarch64_detail = { 0 }; - detail.aarch64 = aarch64_detail; - CS_aarch64_op() op = { 0 }; - detail.CS_aarch64_.operands[0] = op; - CS_aarch64_reg() reg = 1; - CS_aarch64_cc() cc = AArch64CC_AL; - CS_aarch64_extender() aarch64_extender = AARCH64_EXT_SXTB; - CS_aarch64_shifter() aarch64_shifter = AARCH64_SFT_LSL; - CS_aarch64_vas() aarch64_vas = AARCH64LAYOUT_VL_16B; - // Do something with them to prevent compiler warnings. - return reg + cc + aarch64_extender + aarch64_shifter + aarch64_vas + detail.aarch64.cc; - -} - -int main() -{ - test(); - test_macros(); - - return 0; -} diff --git a/tests/test_all.sh b/tests/test_all.sh deleted file mode 100644 index 1ff49959bd..0000000000 --- a/tests/test_all.sh +++ /dev/null @@ -1,23 +0,0 @@ -./test_arm -./test_aarch64 -./test_basic -./test_bpf -./test_customized_mnem -./test_detail -./test_evm -./test_iter -./test_m680x -./test_m68k -./test_mips -./test_mos65xx -./test_ppc -./test_skipdata -./test_sparc -./test_systemz -./test_tms320c64x -./test_wasm -./test_winkernel -./test_x86 -./test_xcore -./test_alpha -./test_hppa \ No newline at end of file diff --git a/tests/test_alpha.c b/tests/test_alpha.c deleted file mode 100644 index 0206f25f66..0000000000 --- a/tests/test_alpha.c +++ /dev/null @@ -1,144 +0,0 @@ -/* Capstone Disassembler Engine */ -/* By Dmitry Sibirtsev , 2023 */ - -#include - -#include -#include - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - char *comment; -}; - -static csh handle; - -static void print_string_hex(char *comment, unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("%s", comment); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - - printf("\n"); -} - -static void print_insn_detail(cs_insn *ins) -{ - cs_alpha *alpha; - int i; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - alpha = &(ins->detail->alpha); - if (alpha->op_count) - printf("\top_count: %u\n", alpha->op_count); - - for (i = 0; i < alpha->op_count; i++) { - cs_alpha_op *op = &(alpha->operands[i]); - switch ((int)op->type) { - default: - break; - case ALPHA_OP_REG: - printf("\t\toperands[%u].type: REG = %s\n", i, - cs_reg_name(handle, op->reg)); - break; - case ALPHA_OP_IMM: - printf("\t\toperands[%u].type: IMM = 0x%x\n", i, - op->imm); - break; - } - } - - printf("\n"); -} - -static void test() -{ -#define ALPHA_CODE \ - "\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7" -#define ALPHA_CODE_BE \ - "\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00" - - struct platform platforms[] = { - { - CS_ARCH_ALPHA, - CS_MODE_LITTLE_ENDIAN, - (unsigned char *)ALPHA_CODE, - sizeof(ALPHA_CODE) - 1, - "Alpha (Little-endian)", - }, - { - CS_ARCH_ALPHA, - CS_MODE_BIG_ENDIAN, - (unsigned char *)ALPHA_CODE_BE, - sizeof(ALPHA_CODE) - 1, - "Alpha (Big-endian)", - }, - }; - - uint64_t address = 0x1000; - cs_insn *insn; - int i; - size_t count; - - for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) { - cs_err err = - cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", - err); - continue; - } - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, - address, 0, &insn); - if (count) { - size_t j; - - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code: ", platforms[i].code, - platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%" PRIx64 ":\t%s\t%s\n", - insn[j].address, insn[j].mnemonic, - insn[j].op_str); - print_insn_detail(&insn[j]); - } - printf("0x%" PRIx64 ":\n", - insn[j - 1].address + insn[j - 1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, - platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - } - - printf("\n"); - - cs_close(&handle); - } -} - -int main() -{ - test(); - - return 0; -} diff --git a/tests/test_arm.c b/tests/test_arm.c deleted file mode 100644 index 0696de5729..0000000000 --- a/tests/test_arm.c +++ /dev/null @@ -1,334 +0,0 @@ -/* Capstone Disassembler Engine */ -/* By Nguyen Anh Quynh , 2013-2019 */ - -#include -#include - -#include -#include - -static csh handle; - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - const char *comment; - int syntax; -}; - -static void print_string_hex(const char *comment, unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("%s", comment); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - - printf("\n"); -} - -static void print_insn_detail(csh cs_handle, cs_insn *ins) -{ - cs_arm *arm; - int i; - cs_regs regs_read, regs_write; - uint8_t regs_read_count, regs_write_count; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - arm = &(ins->detail->arm); - - if (arm->op_count) - printf("\top_count: %u\n", arm->op_count); - - for (i = 0; i < arm->op_count; i++) { - cs_arm_op *op = &(arm->operands[i]); - switch((int)op->type) { - default: - break; - case ARM_OP_REG: - printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(cs_handle, op->reg)); - break; - case ARM_OP_IMM: - if (op->imm < 0) - printf("\t\toperands[%u].type: IMM = -0x%" PRIx64 "\n", i, -(op->imm)); - else - printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); - break; - case ARM_OP_FP: -#if defined(_KERNEL_MODE) - // Issue #681: Windows kernel does not support formatting float point - printf("\t\toperands[%u].type: FP = \n", i); -#else - printf("\t\toperands[%u].type: FP = %f\n", i, op->fp); -#endif - break; - case ARM_OP_MEM: - printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.base != ARM_REG_INVALID) - printf("\t\t\toperands[%u].mem.base: REG = %s\n", - i, cs_reg_name(cs_handle, op->mem.base)); - if (op->mem.index != ARM_REG_INVALID) - printf("\t\t\toperands[%u].mem.index: REG = %s\n", - i, cs_reg_name(cs_handle, op->mem.index)); - if (op->mem.scale != 1) - printf("\t\t\toperands[%u].mem.scale: %u\n", i, op->mem.scale); - if (op->mem.disp != 0) - printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); - if (op->mem.lshift != 0) - printf("\t\t\toperands[%u].mem.lshift: 0x%x\n", i, op->mem.lshift); - - break; - case ARM_OP_PIMM: - printf("\t\toperands[%u].type: P-IMM = %" PRIu64 "\n", i, op->imm); - break; - case ARM_OP_CIMM: - printf("\t\toperands[%u].type: C-IMM = %" PRIu64 "\n", i, op->imm); - break; - case ARM_OP_SETEND: - printf("\t\toperands[%u].type: SETEND = %s\n", i, op->setend == ARM_SETEND_BE? "be" : "le"); - break; - case ARM_OP_SYSM: - printf("\t\toperands[%u].type: SYSM = 0x%" PRIx16 "\n", i, op->sysop.sysm); - printf("\t\toperands[%u].type: MASK = %" PRIu8 "\n", i, op->sysop.msr_mask); - break; - case ARM_OP_SYSREG: - printf("\t\toperands[%u].type: SYSREG = %s\n", i, cs_reg_name(handle, (uint32_t) op->sysop.reg.mclasssysreg)); - printf("\t\toperands[%u].type: MASK = %" PRIu8 "\n", i, op->sysop.msr_mask); - break; - case ARM_OP_BANKEDREG: - // FIXME: Printing the name is currenliy not supported if the encodings overlap - // with system registers. - printf("\t\toperands[%u].type: BANKEDREG = %" PRIu32 "\n", i, (uint32_t) op->sysop.reg.bankedreg); - if (op->sysop.msr_mask != UINT8_MAX) - printf("\t\toperands[%u].type: MASK = %" PRIu8 "\n", i, op->sysop.msr_mask); - case ARM_OP_SPSR: - case ARM_OP_CPSR: { - const char type = op->type == ARM_OP_SPSR ? 'S' : 'C'; - printf("\t\toperands[%u].type: %cPSR = ", i, type); - uint16_t field = op->sysop.psr_bits; - if ((field & ARM_FIELD_SPSR_F) || (field & ARM_FIELD_CPSR_F)) - printf("f"); - if ((field & ARM_FIELD_SPSR_S) || (field & ARM_FIELD_CPSR_S)) - printf("s"); - if ((field & ARM_FIELD_SPSR_X) || (field & ARM_FIELD_CPSR_X)) - printf("x"); - if ((field & ARM_FIELD_SPSR_C) || (field & ARM_FIELD_CPSR_C)) - printf("c"); - printf("\n"); - printf("\t\toperands[%u].type: MASK = %" PRIu8 "\n", i, op->sysop.msr_mask); - break; - } - } - - if (op->neon_lane != -1) { - printf("\t\toperands[%u].neon_lane = %u\n", i, op->neon_lane); - } - - switch(op->access) { - default: - break; - case CS_AC_READ: - printf("\t\toperands[%u].access: READ\n", i); - break; - case CS_AC_WRITE: - printf("\t\toperands[%u].access: WRITE\n", i); - break; - case CS_AC_READ | CS_AC_WRITE: - printf("\t\toperands[%u].access: READ | WRITE\n", i); - break; - } - - if (op->shift.type != ARM_SFT_INVALID && op->shift.value) { - if (op->shift.type < ARM_SFT_ASR_REG) - // shift with constant value - printf("\t\t\tShift: %u = %u\n", op->shift.type, op->shift.value); - else - // shift with register - printf("\t\t\tShift: %u = %s\n", op->shift.type, - cs_reg_name(cs_handle, op->shift.value)); - } - - if (op->vector_index != -1) { - printf("\t\toperands[%u].vector_index = %u\n", i, op->vector_index); - } - - if (op->subtracted) - printf("\t\toperands[%u].subtracted = True\n", i); - } - - if (arm->cc != ARMCC_AL && arm->cc != ARMCC_UNDEF) - printf("\tCode condition: %u\n", arm->cc); - - if (arm->vcc != ARMVCC_None) - printf("\tVector code condition: %u\n", arm->vcc); - - if (arm->update_flags) - printf("\tUpdate-flags: True\n"); - - if (ins->detail->writeback) { - if (arm->post_index) - printf("\tWrite-back: Post\n"); - else - printf("\tWrite-back: Pre\n"); - } - - if (arm->cps_mode) - printf("\tCPSI-mode: %u\n", arm->cps_mode); - - if (arm->cps_flag) - printf("\tCPSI-flag: %u\n", arm->cps_flag); - - if (arm->vector_data) - printf("\tVector-data: %u\n", arm->vector_data); - - if (arm->vector_size) - printf("\tVector-size: %u\n", arm->vector_size); - - if (arm->usermode) - printf("\tUser-mode: True\n"); - - if (arm->mem_barrier) - printf("\tMemory-barrier: %u\n", arm->mem_barrier); - - if (arm->pred_mask) - printf("\tPredicate Mask: 0x%x\n", arm->pred_mask); - - // Print out all registers accessed by this instruction (either implicit or explicit) - if (!cs_regs_access(cs_handle, ins, - regs_read, ®s_read_count, - regs_write, ®s_write_count)) { - if (regs_read_count) { - printf("\tRegisters read:"); - for(i = 0; i < regs_read_count; i++) { - printf(" %s", cs_reg_name(cs_handle, regs_read[i])); - } - printf("\n"); - } - - if (regs_write_count) { - printf("\tRegisters modified:"); - for(i = 0; i < regs_write_count; i++) { - printf(" %s", cs_reg_name(cs_handle, regs_write[i])); - } - printf("\n"); - } - } - - printf("\n"); -} - -static void test() -{ -#define ARM_CODE "\x86\x48\x60\xf4\x4d\x0f\xe2\xf4\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00" -#define ARM_CODE2 "\xd1\xe8\x00\xf0\xf0\x24\x04\x07\x1f\x3c\xf2\xc0\x00\x00\x4f\xf0\x00\x01\x46\x6c" -#define THUMB_CODE "\x60\xf9\x1f\x04\xe0\xf9\x4f\x07\x70\x47\x00\xf0\x10\xe8\xeb\x46\x83\xb0\xc9\x68\x1f\xb1\x30\xbf\xaf\xf3\x20\x84\x52\xf8\x23\xf0" -#define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0\x18\xbf\xad\xbf\xf3\xff\x0b\x0c\x86\xf3\x00\x89\x80\xf3\x00\x8c\x4f\xfa\x99\xf6\xd0\xff\xa2\x01" -#define THUMB_MCLASS "\xef\xf3\x02\x80" -#define ARMV8 "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5" - - struct platform platforms[] = { - { - CS_ARCH_ARM, - CS_MODE_ARM, - (unsigned char *)ARM_CODE, - sizeof(ARM_CODE) - 1, - "ARM" - }, - { - CS_ARCH_ARM, - CS_MODE_THUMB, - (unsigned char *)THUMB_CODE, - sizeof(THUMB_CODE) - 1, - "Thumb" - }, - { - CS_ARCH_ARM, - CS_MODE_THUMB, - (unsigned char *)ARM_CODE2, - sizeof(ARM_CODE2) - 1, - "Thumb-mixed" - }, - { - CS_ARCH_ARM, - CS_MODE_THUMB, - (unsigned char *)THUMB_CODE2, - sizeof(THUMB_CODE2) - 1, - "Thumb-2 & register named with numbers", - CS_OPT_SYNTAX_NOREGNAME - }, - { - CS_ARCH_ARM, - (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS), - (unsigned char*)THUMB_MCLASS, - sizeof(THUMB_MCLASS) - 1, - "Thumb-MClass" - }, - { - CS_ARCH_ARM, - (cs_mode)(CS_MODE_ARM + CS_MODE_V8), - (unsigned char*)ARMV8, - sizeof(ARMV8) - 1, - "Arm-V8" - }, - }; - - uint64_t address = 0x80001000; - cs_insn *insn; - int i; - size_t count; - - for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { - cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", err); - abort(); - } - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - - if (platforms[i].syntax) - cs_option(handle, CS_OPT_SYNTAX, platforms[i].syntax); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); - if (count) { - size_t j; - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); - print_insn_detail(handle, &insn[j]); - } - printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - abort(); - } - - printf("\n"); - - cs_close(&handle); - } -} - -int main() -{ - test(); - - return 0; -} - diff --git a/tests/test_basic.c b/tests/test_basic.c deleted file mode 100644 index dbd37a9ffd..0000000000 --- a/tests/test_basic.c +++ /dev/null @@ -1,480 +0,0 @@ -/* Capstone Disassembler Engine */ -/* By Nguyen Anh Quynh , 2013-2019 */ - -#include -#include - -#include -#include - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - const char *comment; - cs_opt_type opt_type; - cs_opt_value opt_value; -}; - -static void print_string_hex(unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("Code: "); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - printf("\n"); -} - -static void test() -{ -#ifdef CAPSTONE_HAS_X86 -#define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" -#define X86_CODE32 "\xba\xcd\xab\x00\x00\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" -#define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00" -#endif -#ifdef CAPSTONE_HAS_ARM -#define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3" -#define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3" -#define ARMV8 "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5" -#define THUMB_MCLASS "\xef\xf3\x02\x80" -#define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68" -#define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0" -#endif -#ifdef CAPSTONE_HAS_MIPS -#define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56" -#define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00" -#define MIPS_32R6M "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0" -#define MIPS_32R6 "\xec\x80\x00\x19\x7c\x43\x22\xa0" -#endif -#ifdef CAPSTONE_HAS_AARCH64 -#define AARCH64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9" -#endif -#ifdef CAPSTONE_HAS_POWERPC -#define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21" -#define PPC_CODE2 "\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f" -#endif -#ifdef CAPSTONE_HAS_SPARC -#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" -#define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" -#endif -#ifdef CAPSTONE_HAS_SYSZ -#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78" -#endif -#ifdef CAPSTONE_HAS_XCORE -#define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10" -#endif -#ifdef CAPSTONE_HAS_M68K -#define M68K_CODE "\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75" -#endif -#ifdef CAPSTONE_HAS_TMS320C64X -#define TMS320C64X_CODE "\x01\xac\x88\x40\x81\xac\x88\x43\x00\x00\x00\x00\x02\x90\x32\x96\x02\x80\x46\x9e\x05\x3c\x83\xe6\x0b\x0c\x8b\x24" -#endif -#ifdef CAPSTONE_HAS_M680X -#define M680X_CODE "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39" -#endif -#ifdef CAPSTONE_HAS_EVM -#define EVM_CODE "\x60\x61" -#endif -#ifdef CAPSTONE_HAS_WASM -#define WASM_CODE "\x20\x00\x20\x01\x41\x20\x10\xc9\x01\x45\x0b" -#endif -#ifdef CAPSTONE_HAS_MOS65XX -#define MOS65XX_CODE "\x0d\x34\x12\x00\x81\x65\x6c\x01\x00\x85\xFF\x10\x00\x19\x42\x42\x00\x49\x42" -#endif -#ifdef CAPSTONE_HAS_BPF -#define EBPF_CODE "\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00" -#endif -#ifdef CAPSTONE_HAS_RISCV -#define RISCV_CODE32 "\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xff\xe7\x00\x45\x00\xe7\x00\xc0\xff\x63\x05\x41\x00\xe3\x9d\x61\xfe\x63\xca\x93\x00\x63\x53\xb5\x00\x63\x65\xd6\x00\x63\x76\xf7\x00\x03\x88\x18\x00\x03\x99\x49\x00\x03\xaa\x6a\x00\x03\xcb\x2b\x01\x03\xdc\x8c\x01\x23\x86\xad\x03\x23\x9a\xce\x03\x23\x8f\xef\x01\x93\x00\xe0\x00\x13\xa1\x01\x01\x13\xb2\x02\x7d\x13\xc3\x03\xdd\x13\xe4\xc4\x12\x13\xf5\x85\x0c\x13\x96\xe6\x01\x13\xd7\x97\x01\x13\xd8\xf8\x40\x33\x89\x49\x01\xb3\x0a\x7b\x41\x33\xac\xac\x01\xb3\x3d\xde\x01\x33\xd2\x62\x40\xb3\x43\x94\x00\x33\xe5\xc5\x00\xb3\x76\xf7\x00\xb3\x54\x39\x01\xb3\x50\x31\x00\x33\x9f\x0f\x00" -#define RISCV_CODE64 "\x13\x04\xa8\x7a" // aaa80413 -#endif -#ifdef CAPSTONE_HAS_ALPHA -#define ALPHA_CODE "\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7" -#define ALPHA_CODE_BE "\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00" -#endif -#ifdef CAPSTONE_HAS_HPPA -#define HPPA_20_CODE_BE "\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad" -#define HPPA_20_CODE "\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14" -#define HPPA_11_CODE_BE "\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1" -#define HPPA_11_CODE "\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c" -#endif - - struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - const char *comment; - cs_opt_type opt_type; - cs_opt_value opt_value; - }; - struct platform platforms[] = { -#ifdef CAPSTONE_HAS_X86 - { - CS_ARCH_X86, - CS_MODE_16, - (unsigned char*)X86_CODE16, - sizeof(X86_CODE16) - 1, - "X86 16bit (Intel syntax)" - }, - { - CS_ARCH_X86, - CS_MODE_32, - (unsigned char*)X86_CODE32, - sizeof(X86_CODE32) - 1, - "X86 32bit (ATT syntax)", - CS_OPT_SYNTAX, - CS_OPT_SYNTAX_ATT, - }, - { - CS_ARCH_X86, - CS_MODE_32, - (unsigned char*)X86_CODE32, - sizeof(X86_CODE32) - 1, - "X86 32 (Intel syntax)" - }, - { - CS_ARCH_X86, - CS_MODE_32, - (unsigned char*)X86_CODE32, - sizeof(X86_CODE32) - 1, - "X86 32 (MASM syntax)", - CS_OPT_SYNTAX, - CS_OPT_SYNTAX_MASM, - }, - { - CS_ARCH_X86, - CS_MODE_64, - (unsigned char*)X86_CODE64, - sizeof(X86_CODE64) - 1, - "X86 64 (Intel syntax)" - }, -#endif -#ifdef CAPSTONE_HAS_ARM - { - CS_ARCH_ARM, - CS_MODE_ARM, - (unsigned char*)ARM_CODE, - sizeof(ARM_CODE) - 1, - "ARM" - }, - { - CS_ARCH_ARM, - CS_MODE_THUMB, - (unsigned char*)THUMB_CODE2, - sizeof(THUMB_CODE2) - 1, - "THUMB-2" - }, - { - CS_ARCH_ARM, - CS_MODE_ARM, - (unsigned char*)ARM_CODE2, - sizeof(ARM_CODE2) - 1, - "ARM: Cortex-A15 + NEON" - }, - { - CS_ARCH_ARM, - CS_MODE_THUMB, - (unsigned char*)THUMB_CODE, - sizeof(THUMB_CODE) - 1, - "THUMB" - }, - { - CS_ARCH_ARM, - (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS), - (unsigned char*)THUMB_MCLASS, - sizeof(THUMB_MCLASS) - 1, - "Thumb-MClass" - }, - { - CS_ARCH_ARM, - (cs_mode)(CS_MODE_ARM + CS_MODE_V8), - (unsigned char*)ARMV8, - sizeof(ARMV8) - 1, - "Arm-V8" - }, -#endif -#ifdef CAPSTONE_HAS_MIPS - { - CS_ARCH_MIPS, - (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN), - (unsigned char*)MIPS_CODE, - sizeof(MIPS_CODE) - 1, - "MIPS-32 (Big-endian)" - }, - { - CS_ARCH_MIPS, - (cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN), - (unsigned char*)MIPS_CODE2, - sizeof(MIPS_CODE2) - 1, - "MIPS-64-EL (Little-endian)" - }, - { - CS_ARCH_MIPS, - (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN), - (unsigned char*)MIPS_32R6M, - sizeof(MIPS_32R6M) - 1, - "MIPS-32R6 | Micro (Big-endian)" - }, - { - CS_ARCH_MIPS, - (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN), - (unsigned char*)MIPS_32R6, - sizeof(MIPS_32R6) - 1, - "MIPS-32R6 (Big-endian)" - }, -#endif -#ifdef CAPSTONE_HAS_AARCH64 - { - CS_ARCH_AARCH64, - CS_MODE_ARM, - (unsigned char*)AARCH64_CODE, - sizeof(AARCH64_CODE) - 1, - "AARCH64" - }, -#endif -#ifdef CAPSTONE_HAS_POWERPC - { - CS_ARCH_PPC, - CS_MODE_BIG_ENDIAN, - (unsigned char*)PPC_CODE, - sizeof(PPC_CODE) - 1, - "PPC-64" - }, - { - CS_ARCH_PPC, - CS_MODE_BIG_ENDIAN, - (unsigned char*)PPC_CODE, - sizeof(PPC_CODE) - 1, - "PPC-64, print register with number only", - CS_OPT_SYNTAX, - CS_OPT_SYNTAX_NOREGNAME - }, - { - CS_ARCH_PPC, - CS_MODE_BIG_ENDIAN + CS_MODE_QPX, - (unsigned char*)PPC_CODE2, - sizeof(PPC_CODE2) - 1, - "PPC-64 + QPX", - }, -#endif -#ifdef CAPSTONE_HAS_SPARC - { - CS_ARCH_SPARC, - CS_MODE_BIG_ENDIAN, - (unsigned char*)SPARC_CODE, - sizeof(SPARC_CODE) - 1, - "Sparc" - }, - { - CS_ARCH_SPARC, - (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9), - (unsigned char*)SPARCV9_CODE, - sizeof(SPARCV9_CODE) - 1, - "SparcV9" - }, -#endif -#ifdef CAPSTONE_HAS_SYSZ - { - CS_ARCH_SYSZ, - (cs_mode)0, - (unsigned char*)SYSZ_CODE, - sizeof(SYSZ_CODE) - 1, - "SystemZ" - }, -#endif -#ifdef CAPSTONE_HAS_XCORE - { - CS_ARCH_XCORE, - (cs_mode)0, - (unsigned char*)XCORE_CODE, - sizeof(XCORE_CODE) - 1, - "XCore" - }, -#endif -#ifdef CAPSTONE_HAS_M68K - { - CS_ARCH_M68K, - (cs_mode)(CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040), - (unsigned char*)M68K_CODE, - sizeof(M68K_CODE) - 1, - "M68K", - }, -#endif -#ifdef CAPSTONE_HAS_TMS320C64X - { - CS_ARCH_TMS320C64X, - 0, - (unsigned char*)TMS320C64X_CODE, - sizeof(TMS320C64X_CODE) - 1, - "TMS320C64x", - }, -#endif -#ifdef CAPSTONE_HAS_M680X - { - CS_ARCH_M680X, - (cs_mode)(CS_MODE_M680X_6809), - (unsigned char*)M680X_CODE, - sizeof(M680X_CODE) - 1, - "M680X_M6809", - }, -#endif -#ifdef CAPSTONE_HAS_EVM - { - CS_ARCH_EVM, - 0, - (unsigned char*)EVM_CODE, - sizeof(EVM_CODE) - 1, - "EVM", - }, -#endif -#ifdef CAPSTONE_HAS_WASM - { - CS_ARCH_WASM, - 0, - (unsigned char*)WASM_CODE, - sizeof(WASM_CODE) - 1, - "WASM", - }, -#endif -#ifdef CAPSTONE_HAS_MOS65XX - { - CS_ARCH_MOS65XX, - 0, - (unsigned char *)MOS65XX_CODE, - sizeof(MOS65XX_CODE) - 1, - "MOS65XX" - }, -#endif -#ifdef CAPSTONE_HAS_BPF - { - CS_ARCH_BPF, - CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED, - (unsigned char*) EBPF_CODE, - sizeof(EBPF_CODE) - 1, - "eBPF" - }, -#endif -#ifdef CAPSTONE_HAS_RISCV - { - CS_ARCH_RISCV, - CS_MODE_RISCV32, - (unsigned char *)RISCV_CODE32, - sizeof(RISCV_CODE32) - 1, - "RISCV32" - }, - { - CS_ARCH_RISCV, - CS_MODE_RISCV64, - (unsigned char *)RISCV_CODE64, - sizeof(RISCV_CODE64) - 1, - "RISCV64" - }, -#endif -#ifdef CAPSTONE_HAS_ALPHA - { - CS_ARCH_ALPHA, - CS_MODE_LITTLE_ENDIAN, - (unsigned char*)ALPHA_CODE, - sizeof(ALPHA_CODE) - 1, - "Alpha (Little-endian)" - }, - { - CS_ARCH_ALPHA, - CS_MODE_BIG_ENDIAN, - (unsigned char*)ALPHA_CODE_BE, - sizeof(ALPHA_CODE) - 1, - "Alpha (Big-endian)" - }, -#endif -#ifdef CAPSTONE_HAS_HPPA - { - CS_ARCH_HPPA, - CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, - (unsigned char*)HPPA_20_CODE_BE, - sizeof(HPPA_20_CODE_BE) - 1, - "HPPA 2.0 (Big-endian)" - }, - { - CS_ARCH_HPPA, - CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, - (unsigned char*)HPPA_20_CODE, - sizeof(HPPA_20_CODE) - 1, - "HPPA 2.0 (Little-endian)" - }, - { - CS_ARCH_HPPA, - CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, - (unsigned char*)HPPA_11_CODE_BE, - sizeof(HPPA_11_CODE_BE) - 1, - "HPPA 1.1 (Big-endian)" - }, - { - CS_ARCH_HPPA, - CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, - (unsigned char*)HPPA_11_CODE, - sizeof(HPPA_11_CODE) - 1, - "HPPA 1.1 (Little-endian)" - }, -#endif - }; - - csh handle; - uint64_t address = 0x1000; - cs_insn *insn; - int i; - size_t count; - cs_err err; - - for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - err = cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", err); - abort(); - } - - if (platforms[i].opt_type) - cs_option(handle, platforms[i].opt_type, platforms[i].opt_value); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); - if (count) { - size_t j; - - print_string_hex(platforms[i].code, platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%" PRIx64 ":\t%s\t\t%s\n", - insn[j].address, insn[j].mnemonic, insn[j].op_str); - } - - // print out the next offset, after the last insn - printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex(platforms[i].code, platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - abort(); - } - - printf("\n"); - - cs_close(&handle); - } -} - -int main() -{ - test(); - - return 0; -} diff --git a/tests/test_bpf.c b/tests/test_bpf.c deleted file mode 100644 index b97e330cbf..0000000000 --- a/tests/test_bpf.c +++ /dev/null @@ -1,187 +0,0 @@ -/* Capstone Disassembly Engine */ -/* By david942j , 2019 */ - -#include -#include - -static csh handle; - -struct platform { - cs_arch arch; - cs_mode mode; - const unsigned char *code; - size_t size; - const char *comment; -}; - -static void print_string_hex(const char *comment, const unsigned char *str, size_t len) -{ - const unsigned char *c; - - printf("%s", comment); - for (c = str; c < str + len; c++) { - printf(" 0x%02x", *c & 0xff); - } - - printf("\n"); -} - -static const char * ext_name[] = { - [BPF_EXT_LEN] = "#len", -}; - -static void print_insn_detail(csh cs_handle, cs_insn *ins) -{ - cs_bpf *bpf; - cs_regs regs_read, regs_write; - uint8_t regs_read_count, regs_write_count; - unsigned i; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - if (ins->detail->groups_count) { - int j; - - printf("\tGroups:"); - for(j = 0; j < ins->detail->groups_count; j++) - printf(" %s", cs_group_name(handle, ins->detail->groups[j])); - printf("\n"); - } - - bpf = &(ins->detail->bpf); - - printf("\tOperand count: %u\n", bpf->op_count); - for (i = 0; i < bpf->op_count; i++) { - cs_bpf_op *op = &(bpf->operands[i]); - printf("\t\toperands[%u].type: ", i); - switch (op->type) { - case BPF_OP_INVALID: - printf("INVALID\n"); - break; - case BPF_OP_REG: - printf("REG = %s\n", cs_reg_name(handle, op->reg)); - break; - case BPF_OP_IMM: - printf("IMM = 0x%" PRIx64 "\n", op->imm); - break; - case BPF_OP_OFF: - printf("OFF = +0x%x\n", op->off); - break; - case BPF_OP_MEM: - printf("MEM\n"); - if (op->mem.base != BPF_REG_INVALID) - printf("\t\t\toperands[%u].mem.base: REG = %s\n", - i, cs_reg_name(handle, op->mem.base)); - printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); - break; - case BPF_OP_MMEM: - printf("MMEM = M[0x%x]\n", op->mmem); - break; - case BPF_OP_MSH: - printf("MSH = 4*([0x%x]&0xf)\n", op->msh); - break; - case BPF_OP_EXT: - printf("EXT = %s\n", ext_name[op->ext]); - break; - } - } - - /* print all registers that are involved in this instruction */ - if (!cs_regs_access(cs_handle, ins, - regs_read, ®s_read_count, - regs_write, ®s_write_count)) { - if (regs_read_count) { - printf("\tRegisters read:"); - for(i = 0; i < regs_read_count; i++) - printf(" %s", cs_reg_name(cs_handle, regs_read[i])); - printf("\n"); - } - - if (regs_write_count) { - printf("\tRegisters modified:"); - for(i = 0; i < regs_write_count; i++) - printf(" %s", cs_reg_name(cs_handle, regs_write[i])); - printf("\n"); - } - } - puts(""); -} - -static void test() -{ -#define CBPF_CODE "\x94\x09\x00\x00\x37\x13\x03\x00" \ - "\x87\x00\x00\x00\x00\x00\x00\x00" \ - "\x07\x00\x00\x00\x00\x00\x00\x00" \ - "\x16\x00\x00\x00\x00\x00\x00\x00" \ - "\x80\x00\x00\x00\x00\x00\x00\x00" - -#define EBPF_CODE "\x97\x09\x00\x00\x37\x13\x03\x00" \ - "\xdc\x02\x00\x00\x20\x00\x00\x00" \ - "\x30\x00\x00\x00\x00\x00\x00\x00" \ - "\xdb\x3a\x00\x01\x00\x00\x00\x00" \ - "\x84\x02\x00\x00\x00\x00\x00\x00" \ - "\x6d\x33\x17\x02\x00\x00\x00\x00" - struct platform platforms[] = { - { - CS_ARCH_BPF, - CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC, - (unsigned char *)CBPF_CODE, - sizeof(CBPF_CODE) - 1, - "cBPF Le" - }, - { - CS_ARCH_BPF, - CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED, - (unsigned char *)EBPF_CODE, - sizeof(EBPF_CODE) - 1, - "eBPF Le" - }, - }; - uint64_t address = 0x0; - cs_insn *insn; - int i; - size_t count; - - for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { - cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", err); - abort(); - } - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); - if (count) { - size_t j; - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); - print_insn_detail(handle, &insn[j]); - } - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - abort(); - } - - cs_close(&handle); - } -} - -int main() -{ - test(); - return 0; -} diff --git a/tests/test_detail.c b/tests/test_detail.c deleted file mode 100644 index ab8de7e1f5..0000000000 --- a/tests/test_detail.c +++ /dev/null @@ -1,432 +0,0 @@ -/* Capstone Disassembler Engine */ -/* By Nguyen Anh Quynh , 2013-2019 */ - -#include -#include - -#include -#include - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - const char *comment; - cs_opt_type opt_type; - cs_opt_value opt_value; -}; - -static void print_string_hex(unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("Code: "); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - printf("\n"); -} - -static void test() -{ -#ifdef CAPSTONE_HAS_X86 -#define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" -#define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" -#define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00" -#endif -#ifdef CAPSTONE_HAS_ARM -#define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3" -#define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3" -#define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68" -#define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0" -#define THUMB_MCLASS "\xef\xf3\x02\x80" -#define ARMV8 "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5" -#endif -#ifdef CAPSTONE_HAS_MIPS -#define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56\x00\x80\x04\x08" -#define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00" -#define MIPS_32R6M "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0" -#define MIPS_32R6 "\xec\x80\x00\x19\x7c\x43\x22\xa0" -#endif -#ifdef CAPSTONE_HAS_AARCH64 -#define AARCH64_CODE "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c" -#endif -#ifdef CAPSTONE_HAS_POWERPC -#define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14" -#define PPC_CODE2 "\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f" -#endif -#ifdef CAPSTONE_HAS_SPARC -#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" -#define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" -#endif -#ifdef CAPSTONE_HAS_SYSZ -#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78" -#endif -#ifdef CAPSTONE_HAS_XCORE -#define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10" -#endif -#ifdef CAPSTONE_HAS_M68K -#define M68K_CODE "\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75" -#endif -#ifdef CAPSTONE_HAS_M680X -#define M680X_CODE "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39" -#endif -#ifdef CAPSTONE_HAS_MOS65XX -#define MOS65XX_CODE "\x0A\x00\xFE\x34\x12\xD0\xFF\xEA\x19\x56\x34\x46\x80" -#endif -#ifdef CAPSTONE_HAS_BPF -#define EBPF_CODE "\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00" -#endif -#ifdef CAPSTONE_HAS_ALPHA -#define ALPHA_CODE "\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7" -#define ALPHA_CODE_BE "\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00" -#endif -#ifdef CAPSTONE_HAS_HPPA -#define HPPA_20_CODE_BE "\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad" -#define HPPA_20_CODE "\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14" -#define HPPA_11_CODE_BE "\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1" -#define HPPA_11_CODE "\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c" -#endif - - struct platform platforms[] = { -#ifdef CAPSTONE_HAS_X86 - { - CS_ARCH_X86, - CS_MODE_16, - (unsigned char *)X86_CODE16, - sizeof(X86_CODE16) - 1, - "X86 16bit (Intel syntax)" - }, - { - CS_ARCH_X86, - CS_MODE_32, - (unsigned char *)X86_CODE32, - sizeof(X86_CODE32) - 1, - "X86 32bit (ATT syntax)", - CS_OPT_SYNTAX, - CS_OPT_SYNTAX_ATT, - }, - { - CS_ARCH_X86, - CS_MODE_32, - (unsigned char *)X86_CODE32, - sizeof(X86_CODE32) - 1, - "X86 32 (Intel syntax)" - }, - { - CS_ARCH_X86, - CS_MODE_64, - (unsigned char *)X86_CODE64, - sizeof(X86_CODE64) - 1, - "X86 64 (Intel syntax)" - }, -#endif -#ifdef CAPSTONE_HAS_ARM - { - CS_ARCH_ARM, - CS_MODE_ARM, - (unsigned char *)ARM_CODE, - sizeof(ARM_CODE) - 1, - "ARM" - }, - { - CS_ARCH_ARM, - CS_MODE_ARM, - (unsigned char *)ARM_CODE2, - sizeof(ARM_CODE2) - 1, - "ARM: Cortex-A15 + NEON" - }, - { - CS_ARCH_ARM, - CS_MODE_THUMB, - (unsigned char *)THUMB_CODE, - sizeof(THUMB_CODE) - 1, - "THUMB" - }, - { - CS_ARCH_ARM, - CS_MODE_THUMB, - (unsigned char *)THUMB_CODE2, - sizeof(THUMB_CODE2) - 1, - "THUMB-2" - }, - { - CS_ARCH_ARM, - (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS), - (unsigned char*)THUMB_MCLASS, - sizeof(THUMB_MCLASS) - 1, - "Thumb-MClass" - }, - { - CS_ARCH_ARM, - (cs_mode)(CS_MODE_ARM + CS_MODE_V8), - (unsigned char*)ARMV8, - sizeof(ARMV8) - 1, - "Arm-V8" - }, -#endif -#ifdef CAPSTONE_HAS_AARCH64 - { - CS_ARCH_AARCH64, - CS_MODE_ARM, - (unsigned char *)AARCH64_CODE, - sizeof(AARCH64_CODE) - 1, - "AARCH64" - }, -#endif -#ifdef CAPSTONE_HAS_MIPS - { - CS_ARCH_MIPS, - (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN), - (unsigned char *)MIPS_CODE, - sizeof(MIPS_CODE) - 1, - "MIPS-32 (Big-endian)" - }, - { - CS_ARCH_MIPS, - (cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN), - (unsigned char *)MIPS_CODE2, - sizeof(MIPS_CODE2) - 1, - "MIPS-64-EL (Little-endian)" - }, - { - CS_ARCH_MIPS, - (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN), - (unsigned char*)MIPS_32R6M, - sizeof(MIPS_32R6M) - 1, - "MIPS-32R6 | Micro (Big-endian)" - }, - { - CS_ARCH_MIPS, - (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN), - (unsigned char*)MIPS_32R6, - sizeof(MIPS_32R6) - 1, - "MIPS-32R6 (Big-endian)" - }, -#endif -#ifdef CAPSTONE_HAS_POWERPC - { - CS_ARCH_PPC, - CS_MODE_BIG_ENDIAN, - (unsigned char*)PPC_CODE, - sizeof(PPC_CODE) - 1, - "PPC-64" - }, - { - CS_ARCH_PPC, - CS_MODE_BIG_ENDIAN + CS_MODE_QPX, - (unsigned char*)PPC_CODE2, - sizeof(PPC_CODE2) - 1, - "PPC-64 + QPX", - }, -#endif -#ifdef CAPSTONE_HAS_SPARC - { - CS_ARCH_SPARC, - CS_MODE_BIG_ENDIAN, - (unsigned char*)SPARC_CODE, - sizeof(SPARC_CODE) - 1, - "Sparc" - }, - { - CS_ARCH_SPARC, - (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9), - (unsigned char*)SPARCV9_CODE, - sizeof(SPARCV9_CODE) - 1, - "SparcV9" - }, -#endif -#ifdef CAPSTONE_HAS_SYSZ - { - CS_ARCH_SYSZ, - (cs_mode)0, - (unsigned char*)SYSZ_CODE, - sizeof(SYSZ_CODE) - 1, - "SystemZ" - }, -#endif -#ifdef CAPSTONE_HAS_XCORE - { - CS_ARCH_XCORE, - (cs_mode)0, - (unsigned char*)XCORE_CODE, - sizeof(XCORE_CODE) - 1, - "XCore" - }, -#endif -#ifdef CAPSTONE_HAS_M68K - { - CS_ARCH_M68K, - (cs_mode)(CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040), - (unsigned char*)M68K_CODE, - sizeof(M68K_CODE) - 1, - "M68K", - }, -#endif -#ifdef CAPSTONE_HAS_M680X - { - CS_ARCH_M680X, - (cs_mode)(CS_MODE_M680X_6809), - (unsigned char*)M680X_CODE, - sizeof(M680X_CODE) - 1, - "M680X_M6809", - }, -#endif -#ifdef CAPSTONE_HAS_MOS65XX - { - CS_ARCH_MOS65XX, - (cs_mode)0, - (unsigned char*)MOS65XX_CODE, - sizeof(MOS65XX_CODE) - 1, - "MOS65XX", - }, -#endif -#ifdef CAPSTONE_HAS_BPF - { - CS_ARCH_BPF, - CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED, - (unsigned char*) EBPF_CODE, - sizeof(EBPF_CODE) - 1, - "eBPF" - }, -#endif -#ifdef CAPSTONE_HAS_ALPHA - { - CS_ARCH_ALPHA, - CS_MODE_LITTLE_ENDIAN, - (unsigned char*)ALPHA_CODE, - sizeof(ALPHA_CODE) - 1, - "Alpha (Little-endian)" - }, - { - CS_ARCH_ALPHA, - CS_MODE_BIG_ENDIAN, - (unsigned char*)ALPHA_CODE_BE, - sizeof(ALPHA_CODE) - 1, - "Alpha (Big-endian)" - }, -#endif -#ifdef CAPSTONE_HAS_HPPA - { - CS_ARCH_HPPA, - CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, - (unsigned char*)HPPA_20_CODE_BE, - sizeof(HPPA_20_CODE_BE) - 1, - "HPPA 2.0 (Big-endian)" - }, - { - CS_ARCH_HPPA, - CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, - (unsigned char*)HPPA_20_CODE, - sizeof(HPPA_20_CODE) - 1, - "HPPA 2.0 (Little-endian)" - }, - { - CS_ARCH_HPPA, - CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, - (unsigned char*)HPPA_11_CODE_BE, - sizeof(HPPA_11_CODE_BE) - 1, - "HPPA 1.1 (Big-endian)" - }, - { - CS_ARCH_HPPA, - CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, - (unsigned char*)HPPA_11_CODE, - sizeof(HPPA_11_CODE) - 1, - "HPPA 1.1 (Little-endian)" - }, -#endif - }; - - csh handle; - uint64_t address = 0x1000; - cs_insn *all_insn; - cs_detail *detail; - int i; - size_t count; - cs_err err; - - for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - err = cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", err); - abort(); - } - - if (platforms[i].opt_type) - cs_option(handle, platforms[i].opt_type, platforms[i].opt_value); - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &all_insn); - if (count) { - size_t j; - int n; - - print_string_hex(platforms[i].code, platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - cs_insn *in = &(all_insn[j]); - printf("0x%" PRIx64 ":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n", - in->address, in->mnemonic, in->op_str, - in->id, cs_insn_name(handle, in->id)); - - // print implicit registers used by this instruction - detail = in->detail; - - if (detail->regs_read_count > 0) { - printf("\tImplicit registers read: "); - for (n = 0; n < detail->regs_read_count; n++) { - printf("%s ", cs_reg_name(handle, detail->regs_read[n])); - } - printf("\n"); - } - - // print implicit registers modified by this instruction - if (detail->regs_write_count > 0) { - printf("\tImplicit registers modified: "); - for (n = 0; n < detail->regs_write_count; n++) { - printf("%s ", cs_reg_name(handle, detail->regs_write[n])); - } - printf("\n"); - } - - // print the groups this instruction belong to - if (detail->groups_count > 0) { - printf("\tThis instruction belongs to groups: "); - for (n = 0; n < detail->groups_count; n++) { - printf("%s ", cs_group_name(handle, detail->groups[n])); - } - printf("\n"); - } - } - - // print out the next offset, after the last insn - printf("0x%" PRIx64 ":\n", all_insn[j-1].address + all_insn[j-1].size); - - // free memory allocated by cs_disasm() - cs_free(all_insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex(platforms[i].code, platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - abort(); - } - - printf("\n"); - - cs_close(&handle); - } -} - -int main() -{ - test(); - - return 0; -} diff --git a/tests/test_evm.c b/tests/test_evm.c deleted file mode 100644 index 7fd0aa30ff..0000000000 --- a/tests/test_evm.c +++ /dev/null @@ -1,126 +0,0 @@ -/* Capstone Disassembler Engine */ -/* By Nguyen Anh Quynh , 2018-2019 */ - -#include -#include - -#include -#include - -static csh handle; - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - const char *comment; -}; - -static void print_string_hex(const char *comment, unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("%s", comment); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - - printf("\n"); -} - -static void print_insn_detail(csh cs_handle, cs_insn *ins) -{ - cs_evm *evm; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - evm = &(ins->detail->evm); - - if (evm->pop) - printf("\tPop: %u\n", evm->pop); - - if (evm->push) - printf("\tPush: %u\n", evm->push); - - if (evm->fee) - printf("\tGas fee: %u\n", evm->fee); - - if (ins->detail->groups_count) { - int j; - - printf("\tGroups: "); - for(j = 0; j < ins->detail->groups_count; j++) { - printf("%s ", cs_group_name(handle, ins->detail->groups[j])); - } - printf("\n"); - } -} - -static void test() -{ -#define EVM_CODE "\x60\x61\x50" - - struct platform platforms[] = { - { - CS_ARCH_EVM, - 0, - (unsigned char *)EVM_CODE, - sizeof(EVM_CODE) - 1, - "EVM" - }, - }; - - uint64_t address = 0x80001000; - cs_insn *insn; - int i; - size_t count; - - for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { - cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", err); - abort(); - } - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); - if (count) { - size_t j; - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); - print_insn_detail(handle, &insn[j]); - } - printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - abort(); - } - - printf("\n"); - - cs_close(&handle); - } -} - -int main() -{ - test(); - - return 0; -} - diff --git a/tests/test_hppa.c b/tests/test_hppa.c deleted file mode 100644 index d96693cc76..0000000000 --- a/tests/test_hppa.c +++ /dev/null @@ -1,186 +0,0 @@ -/* Capstone Disassembler Engine */ -/* By Dmitry Sibirtsev , 2023 */ - -#include - -#include -#include - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - char *comment; -}; - -static csh handle; - -static void print_string_hex(char *comment, unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("%s", comment); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - - printf("\n"); -} - -static void print_insn_detail(cs_insn *ins) -{ - cs_hppa *hppa; - int i; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - hppa = &(ins->detail->hppa); - if (hppa->op_count) - printf("\top_count: %u\n", hppa->op_count); - - for (i = 0; i < hppa->op_count; i++) { - cs_hppa_op *op = &(hppa->operands[i]); - switch ((int)op->type) { - default: - break; - case HPPA_OP_REG: - printf("\t\toperands[%u].type: REG = %s\n", i, - cs_reg_name(handle, op->reg)); - break; - case HPPA_OP_IMM: - printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", - i, op->imm); - break; - case HPPA_OP_IDX_REG: - printf("\t\toperands[%u].type: IDX_REG = %s\n", i, - cs_reg_name(handle, op->reg)); - break; - case HPPA_OP_DISP: - printf("\t\toperands[%u].type: DISP = 0x%" PRIx64 "\n", - i, op->imm); - break; - case HPPA_OP_MEM: - printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.space != HPPA_REG_INVALID) { - printf("\t\t\toperands[%u].mem.space: REG = %s\n", - i, cs_reg_name(handle, op->mem.space)); - } - printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, - cs_reg_name(handle, op->mem.base)); - break; - case HPPA_OP_TARGET: - printf("\t\toperands[%u].type: ", i); - if (op->imm >= 0x8000000000000000) - printf("TARGET = -0x%" PRIx64 "\n", -op->imm); - else - printf("TARGET = 0x%" PRIx64 "\n", op->imm); - break; - } - } - - printf("\n"); -} - -static void test() -{ -#define HPPA_20_CODE_BE \ - "\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad" -#define HPPA_20_CODE \ - "\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14" -#define HPPA_11_CODE_BE \ - "\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1" -#define HPPA_11_CODE \ - "\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c" - - struct platform platforms[] = { - { - CS_ARCH_HPPA, - CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, - (unsigned char *)HPPA_20_CODE_BE, - sizeof(HPPA_20_CODE_BE) - 1, - "HPPA 2.0 (Big-endian)", - }, - { - CS_ARCH_HPPA, - CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, - (unsigned char *)HPPA_20_CODE, - sizeof(HPPA_20_CODE) - 1, - "HPPA 2.0 (Little-endian)", - }, - { - CS_ARCH_HPPA, - CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, - (unsigned char *)HPPA_11_CODE_BE, - sizeof(HPPA_11_CODE_BE) - 1, - "HPPA 1.1 (Big-endian)", - }, - { - CS_ARCH_HPPA, - CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, - (unsigned char *)HPPA_11_CODE, - sizeof(HPPA_11_CODE) - 1, - "HPPA 1.1 (Little-endian)", - }, - }; - - uint64_t address = 0x1000; - cs_insn *insn; - int i; - size_t count; - - for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) { - cs_err err = - cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", - err); - continue; - } - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, - address, 0, &insn); - if (count) { - size_t j; - - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code: ", platforms[i].code, - platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%" PRIx64 ":\t%s\t%s\n", - insn[j].address, insn[j].mnemonic, - insn[j].op_str); - print_insn_detail(&insn[j]); - } - printf("0x%" PRIx64 ":\n", - insn[j - 1].address + insn[j - 1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, - platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - } - - printf("\n"); - - cs_close(&handle); - } -} - -int main() -{ - test(); - - return 0; -} diff --git a/tests/test_loongarch.c b/tests/test_loongarch.c deleted file mode 100644 index 9f67e9c9fa..0000000000 --- a/tests/test_loongarch.c +++ /dev/null @@ -1,160 +0,0 @@ -#include -#include - -#include -#include - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - const char *comment; -}; - -static csh handle; - -static void print_string_hex(const char *comment, unsigned char *str, - size_t len) -{ - unsigned char *c; - - printf("%s", comment); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - - printf("\n"); -} - -static void print_insn_detail(cs_insn *ins) -{ - int i; - int n; - cs_loongarch *loongarch; - cs_detail *detail; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - loongarch = &(ins->detail->loongarch); - detail = ins->detail; - if (loongarch->op_count) - printf("\top_count: %u\n", loongarch->op_count); - - for (i = 0; i < loongarch->op_count; i++) { - cs_loongarch_op *op = &(loongarch->operands[i]); - switch ((int)op->type) { - default: - printf("\terror in opt_type: %u\n", (int)op->type); - break; - case LOONGARCH_OP_REG: - printf("\t\toperands[%u].type: REG = %s\n", i, - cs_reg_name(handle, op->reg)); - break; - case LOONGARCH_OP_IMM: - printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", - i, op->imm); - break; - case LOONGARCH_OP_MEM: - printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.base != LOONGARCH_REG_INVALID) - printf("\t\t\toperands[%u].mem.base: REG = %s\n", - i, cs_reg_name(handle, op->mem.base)); - if (op->mem.disp != 0) - printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 - "\n", - i, op->mem.disp); - - break; - } - } - - // print the groups this instruction belongs to - if (detail->groups_count > 0) { - printf("\tgroups: "); - for (n = 0; n < detail->groups_count; n++) { - printf("%s ", cs_group_name(handle, detail->groups[n])); - } - printf("\n"); - } - - printf("\n"); -} - -static void test() -{ -#define LOONGARCH_CODE32 "\x0c\x00\x08\x14\x8c\xfd\xbf\x02" -#define LOONGARCH_CODE64 \ - "\x80\x80\x00\x40\x63\x80\xff\x02\x78\x20\xc0\x29\x00\x84\x00\x01\x00\xa4" \ - "\x14\x01" - struct platform platforms[] = { - { CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH32, - (unsigned char *)LOONGARCH_CODE32, - sizeof(LOONGARCH_CODE32) - 1, "loongarch32" }, - { CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, - (unsigned char *)LOONGARCH_CODE64, - sizeof(LOONGARCH_CODE64) - 1, "loongarch64" } - }; - - uint64_t address = 0x1000; - cs_insn *insn; - int i; - size_t count; - - for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) { - cs_err err = - cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", - err); - continue; - } - - // To turn on or off the Print Details option - // cs_option(handle, CS_OPT_DETAIL, CS_OPT_OFF); - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, - address, 0, &insn); - if (count) { - size_t j; - - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, - platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%" PRIx64 ":\t%s\t%s\n", - insn[j].address, insn[j].mnemonic, - insn[j].op_str); - print_insn_detail(&insn[j]); - } - printf("0x%" PRIx64 ":\n", - insn[j - 1].address + insn[j - 1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, - platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - } - - printf("\n"); - - cs_close(&handle); - } -} - -int main() -{ - test(); - - return 0; -} diff --git a/tests/test_m680x.c b/tests/test_m680x.c deleted file mode 100644 index aa1f572723..0000000000 --- a/tests/test_m680x.c +++ /dev/null @@ -1,396 +0,0 @@ -/* Capstone Disassembler Engine */ -/* M680X Backend by Wolfgang Schwotzer 2017 */ - -#include -#include - -#include -#include - -#define WITH_DETAILS - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - const char *comment; -}; - -static void print_string_hex(const char *comment, unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("%s", comment); - - for (c = str; c < str + len; c++) - printf("0x%02x ", *c & 0xff); - - printf("\n"); -} - -static void print_string_hex_short(unsigned char *str, size_t len) -{ - unsigned char *c; - - for (c = str; c < str + len; c++) - printf("%02x", *c & 0xff); -} - -static const char *s_access[] = { - "UNCHANGED", "READ", "WRITE", "READ | WRITE", -}; - -static void print_read_write_regs(csh handle, cs_detail *detail) -{ - int i; - - if (detail->regs_read_count > 0) { - printf("\tRegisters read:"); - - for (i = 0; i < detail->regs_read_count; ++i) - printf(" %s", - cs_reg_name(handle, detail->regs_read[i])); - - printf("\n"); - } - - if (detail->regs_write_count > 0) { - printf("\tRegisters modified:"); - - for (i = 0; i < detail->regs_write_count; ++i) - printf(" %s", - cs_reg_name(handle, detail->regs_write[i])); - - printf("\n"); - } -} - -static void print_insn_detail(csh handle, cs_insn *insn) -{ - cs_detail *detail = insn->detail; - cs_m680x *m680x = NULL; - int i; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (detail == NULL) - return; - - m680x = &detail->m680x; - - if (m680x->op_count) - printf("\top_count: %u\n", m680x->op_count); - - for (i = 0; i < m680x->op_count; i++) { - cs_m680x_op *op = &(m680x->operands[i]); - const char *comment; - - switch ((int)op->type) { - default: - break; - - case M680X_OP_REGISTER: - comment = ""; - - if ((i == 0 && (m680x->flags & - M680X_FIRST_OP_IN_MNEM)) || - ((i == 1 && (m680x->flags & - M680X_SECOND_OP_IN_MNEM)))) - comment = " (in mnemonic)"; - - printf("\t\toperands[%u].type: REGISTER = %s%s\n", i, - cs_reg_name(handle, op->reg), comment); - break; - - case M680X_OP_CONSTANT: - printf("\t\toperands[%u].type: CONSTANT = %u\n", i, - op->const_val); - break; - - case M680X_OP_IMMEDIATE: - printf("\t\toperands[%u].type: IMMEDIATE = #%d\n", i, - op->imm); - break; - - case M680X_OP_DIRECT: - printf("\t\toperands[%u].type: DIRECT = 0x%02x\n", i, - op->direct_addr); - break; - - case M680X_OP_EXTENDED: - printf("\t\toperands[%u].type: EXTENDED %s = 0x%04x\n", - i, op->ext.indirect ? "INDIRECT" : "", - op->ext.address); - break; - - case M680X_OP_RELATIVE: - printf("\t\toperands[%u].type: RELATIVE = 0x%04x\n", i, - op->rel.address); - break; - - case M680X_OP_INDEXED: - printf("\t\toperands[%u].type: INDEXED%s\n", i, - (op->idx.flags & M680X_IDX_INDIRECT) ? - " INDIRECT" : ""); - - if (op->idx.base_reg != M680X_REG_INVALID) - printf("\t\t\tbase register: %s\n", - cs_reg_name(handle, op->idx.base_reg)); - - if (op->idx.offset_reg != M680X_REG_INVALID) - printf("\t\t\toffset register: %s\n", - cs_reg_name(handle, op->idx.offset_reg)); - - if ((op->idx.offset_bits != 0) && - (op->idx.offset_reg == M680X_REG_INVALID) && - !op->idx.inc_dec) { - printf("\t\t\toffset: %d\n", op->idx.offset); - - if (op->idx.base_reg == M680X_REG_PC) - printf("\t\t\toffset address: 0x%x\n", - op->idx.offset_addr); - - printf("\t\t\toffset bits: %u\n", - op->idx.offset_bits); - } - - if (op->idx.inc_dec) { - const char *post_pre = op->idx.flags & - M680X_IDX_POST_INC_DEC ? "post" : "pre"; - const char *inc_dec = (op->idx.inc_dec > 0) ? - "increment" : "decrement"; - - printf("\t\t\t%s %s: %d\n", post_pre, inc_dec, - abs(op->idx.inc_dec)); - } - - break; - } - - if (op->size != 0) - printf("\t\t\tsize: %u\n", op->size); - - if (op->access != CS_AC_INVALID) - printf("\t\t\taccess: %s\n", s_access[op->access]); - - } - - print_read_write_regs(handle, detail); - - if (detail->groups_count) { - printf("\tgroups_count: %u\n", detail->groups_count); - } - - printf("\n"); -} - -static bool consistency_checks() -{ - return true; -} - -static void test() -{ -#define M6800_CODE \ - "\x01\x09\x36\x64\x7f\x74\x10\x00\x90\x10\xA4\x10\xb6\x10\x00\x39" - -#define M6801_CODE \ - "\x04\x05\x3c\x3d\x38\x93\x10\xec\x10\xed\x10\x39" - -#define M6805_CODE \ - "\x04\x7f\x00\x17\x22\x28\x00\x2e\x00\x40\x42\x5a\x70\x8e\x97\x9c" \ - "\xa0\x15\xad\x00\xc3\x10\x00\xda\x12\x34\xe5\x7f\xfe" - -#define M6808_CODE \ - "\x31\x22\x00\x35\x22\x45\x10\x00\x4b\x00\x51\x10\x52\x5e\x22\x62" \ - "\x65\x12\x34\x72\x84\x85\x86\x87\x8a\x8b\x8c\x94\x95\xa7\x10\xaf\x10" \ - "\x9e\x60\x7f\x9e\x6b\x7f\x00\x9e\xd6\x10\x00\x9e\xe6\x7f" - -#define HCS08_CODE \ - "\x32\x10\x00\x9e\xae\x9e\xce\x7f\x9e\xbe\x10\x00\x9e\xfe\x7f" \ - "\x3e\x10\x00\x9e\xf3\x7f\x96\x10\x00\x9e\xff\x7f\x82" - -#define M6811_CODE \ - "\x02\x03\x12\x7f\x10\x00\x13\x99\x08\x00\x14\x7f\x02\x15\x7f\x01" \ - "\x1e\x7f\x20\x00\x8f\xcf" \ - "\x18\x08\x18\x30\x18\x3c\x18\x67\x18\x8c\x10\x00\x18\x8f" \ - "\x18\xce\x10\x00\x18\xff\x10\x00" \ - "\x1a\xa3\x7f\x1a\xac\x1a\xee\x7f\x1a\xef\x7f\xcd\xac\x7f" - -#define CPU12_CODE \ - "\x00\x04\x01\x00\x0c\x00\x80\x0e\x00\x80\x00\x11\x1e\x10\x00\x80\x00" \ - "\x3b\x4a\x10\x00\x04\x4b\x01\x04\x4f\x7f\x80\x00\x8f\x10\x00\xb7\x52" \ - "\xb7\xb1\xa6\x67\xa6\xfe\xa6\xf7\x18\x02\xe2\x30\x39\xe2\x10\x00" \ - "\x18\x0c\x30\x39\x10\x00\x18\x11\x18\x12\x10\x00\x18\x19\x00\x18\x1e\x00" \ - "\x18\x3e\x18\x3f\x00" - -#define HD6301_CODE \ - "\x6b\x10\x00\x71\x10\x00\x72\x10\x10\x39" - -#define M6809_CODE \ - "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81" \ - "\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00" \ - "\x11\xac\x99\x10\x00\x39" \ - \ - "\xA6\x07\xA6\x27\xA6\x47\xA6\x67\xA6\x0F\xA6\x10" \ - "\xA6\x80\xA6\x81\xA6\x82\xA6\x83\xA6\x84\xA6\x85\xA6\x86" \ - "\xA6\x88\x7F\xA6\x88\x80\xA6\x89\x7F\xFF\xA6\x89\x80\x00" \ - "\xA6\x8B\xA6\x8C\x10\xA6\x8D\x10\x00" \ - \ - "\xA6\x91\xA6\x93\xA6\x94\xA6\x95\xA6\x96" \ - "\xA6\x98\x7F\xA6\x98\x80\xA6\x99\x7F\xFF\xA6\x99\x80\x00" \ - "\xA6\x9B\xA6\x9C\x10\xA6\x9D\x10\x00\xA6\x9F\x10\x00" - -#define HD6309_CODE \ - "\x01\x10\x10\x62\x10\x10\x7b\x10\x10\x00\xcd\x49\x96\x02\xd2" \ - "\x10\x30\x23\x10\x38\x10\x3b\x10\x53\x10\x5d" \ - "\x11\x30\x43\x10\x11\x37\x25\x10\x11\x38\x12\x11\x39\x23\x11\x3b\x34" \ - "\x11\x8e\x10\x00\x11\xaf\x10\x11\xab\x10\x11\xf6\x80\x00" - - struct platform platforms[] = { - { - CS_ARCH_M680X, - (cs_mode)(CS_MODE_M680X_6301), - (unsigned char *)HD6301_CODE, - sizeof(HD6301_CODE) - 1, - "M680X_HD6301", - }, - { - CS_ARCH_M680X, - (cs_mode)(CS_MODE_M680X_6309), - (unsigned char *)HD6309_CODE, - sizeof(HD6309_CODE) - 1, - "M680X_HD6309", - }, - { - CS_ARCH_M680X, - (cs_mode)(CS_MODE_M680X_6800), - (unsigned char *)M6800_CODE, - sizeof(M6800_CODE) - 1, - "M680X_M6800", - }, - { - CS_ARCH_M680X, - (cs_mode)(CS_MODE_M680X_6801), - (unsigned char *)M6801_CODE, - sizeof(M6801_CODE) - 1, - "M680X_M6801", - }, - { - CS_ARCH_M680X, - (cs_mode)(CS_MODE_M680X_6805), - (unsigned char *)M6805_CODE, - sizeof(M6805_CODE) - 1, - "M680X_M68HC05", - }, - { - CS_ARCH_M680X, - (cs_mode)(CS_MODE_M680X_6808), - (unsigned char *)M6808_CODE, - sizeof(M6808_CODE) - 1, - "M680X_M68HC08", - }, - { - CS_ARCH_M680X, - (cs_mode)(CS_MODE_M680X_6809), - (unsigned char *)M6809_CODE, - sizeof(M6809_CODE) - 1, - "M680X_M6809", - }, - { - CS_ARCH_M680X, - (cs_mode)(CS_MODE_M680X_6811), - (unsigned char *)M6811_CODE, - sizeof(M6811_CODE) - 1, - "M680X_M68HC11", - }, - { - CS_ARCH_M680X, - (cs_mode)(CS_MODE_M680X_CPU12), - (unsigned char *)CPU12_CODE, - sizeof(CPU12_CODE) - 1, - "M680X_CPU12", - }, - { - CS_ARCH_M680X, - (cs_mode)(CS_MODE_M680X_HCS08), - (unsigned char *)HCS08_CODE, - sizeof(HCS08_CODE) - 1, - "M680X_HCS08", - }, - }; - - uint64_t address = 0x1000; - csh handle; - cs_insn *insn; - int i; - size_t count; - const char *nine_spaces = " "; - - if (!consistency_checks()) - abort(); - - for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) { - cs_err err = cs_open(platforms[i].arch, platforms[i].mode, - &handle); - - if (err) { - printf("Failed on cs_open() with error returned: %u\n", - err); - abort(); - } - -#ifdef WITH_DETAILS - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); -#endif - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, - address, 0, &insn); - - if (count) { - size_t j; - - printf("********************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code: ", platforms[i].code, - platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - int slen; - printf("0x%04x: ", (uint16_t)insn[j].address); - print_string_hex_short(insn[j].bytes, - insn[j].size); - printf("%.*s", 1 + ((5 - insn[j].size) * 2), - nine_spaces); - printf("%s", insn[j].mnemonic); - slen = (int)strlen(insn[j].mnemonic); - printf("%.*s", 1 + (5 - slen), nine_spaces); - printf("%s\n", insn[j].op_str); -#ifdef WITH_DETAILS - print_insn_detail(handle, &insn[j]); -#endif - } - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } - else { - printf("********************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, - platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - abort(); - } - - cs_close(&handle); - } -} - -int main() -{ - test(); - - return 0; -} diff --git a/tests/test_m68k.c b/tests/test_m68k.c deleted file mode 100644 index e003f486be..0000000000 --- a/tests/test_m68k.c +++ /dev/null @@ -1,222 +0,0 @@ -/* Capstone Disassembler Engine */ -/* By Daniel Collin, 2013-2019 */ - -#include -#include - -#include -#include - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char* code; - size_t size; - const char* comment; -}; - -static csh handle; - -static void print_string_hex(const char* comment, unsigned char* str, size_t len) -{ - unsigned char *c; - - printf("%s", comment); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - - printf("\n"); -} - -const char* s_addressing_modes[] = { - "", - - "Register Direct - Data", - "Register Direct - Address", - - "Register Indirect - Address", - "Register Indirect - Address with Postincrement", - "Register Indirect - Address with Predecrement", - "Register Indirect - Address with Displacement", - - "Address Register Indirect With Index - 8-bit displacement", - "Address Register Indirect With Index - Base displacement", - - "Memory indirect - Postindex", - "Memory indirect - Preindex", - - "Program Counter Indirect - with Displacement", - - "Program Counter Indirect with Index - with 8-Bit Displacement", - "Program Counter Indirect with Index - with Base Displacement", - - "Program Counter Memory Indirect - Postindexed", - "Program Counter Memory Indirect - Preindexed", - - "Absolute Data Addressing - Short", - "Absolute Data Addressing - Long", - "Immediate value", - "Branch Displacement", -}; - -static void print_read_write_regs(cs_detail* detail) -{ - int i; - - for (i = 0; i < detail->regs_read_count; ++i) - { - uint16_t reg_id = detail->regs_read[i]; - const char* reg_name = cs_reg_name(handle, reg_id); - printf("\treading from reg: %s\n", reg_name); - } - - for (i = 0; i < detail->regs_write_count; ++i) - { - uint16_t reg_id = detail->regs_write[i]; - const char* reg_name = cs_reg_name(handle, reg_id); - printf("\twriting to reg: %s\n", reg_name); - } -} - -static void print_insn_detail(cs_insn *ins) -{ - cs_m68k* m68k; - cs_detail* detail; - int i; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - detail = ins->detail; - m68k = &detail->m68k; - if (m68k->op_count) - printf("\top_count: %u\n", m68k->op_count); - - print_read_write_regs(detail); - - printf("\tgroups_count: %u\n", detail->groups_count); - - for (i = 0; i < m68k->op_count; i++) { - cs_m68k_op* op = &(m68k->operands[i]); - - switch((int)op->type) { - default: - break; - case M68K_OP_REG: - printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); - break; - case M68K_OP_IMM: - printf("\t\toperands[%u].type: IMM = 0x%x\n", i, (int)op->imm); - break; - case M68K_OP_MEM: - printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.base_reg != M68K_REG_INVALID) - printf("\t\t\toperands[%u].mem.base: REG = %s\n", - i, cs_reg_name(handle, op->mem.base_reg)); - if (op->mem.index_reg != M68K_REG_INVALID) { - printf("\t\t\toperands[%u].mem.index: REG = %s\n", - i, cs_reg_name(handle, op->mem.index_reg)); - printf("\t\t\toperands[%u].mem.index: size = %c\n", - i, op->mem.index_size ? 'l' : 'w'); - } - if (op->mem.disp != 0) - printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); - if (op->mem.scale != 0) - printf("\t\t\toperands[%u].mem.scale: %d\n", i, op->mem.scale); - - printf("\t\taddress mode: %s\n", s_addressing_modes[op->address_mode]); - break; - case M68K_OP_FP_SINGLE: - printf("\t\toperands[%u].type: FP_SINGLE\n", i); - printf("\t\t\toperands[%u].simm: %f\n", i, op->simm); - break; - case M68K_OP_FP_DOUBLE: - printf("\t\toperands[%u].type: FP_DOUBLE\n", i); - printf("\t\t\toperands[%u].dimm: %lf\n", i, op->dimm); - break; - case M68K_OP_REG_BITS: - printf("\t\toperands[%u].type: REG_BITS = $%x\n", i, op->register_bits); - break; - case M68K_OP_REG_PAIR: - printf("\t\toperands[%u].type: REG_PAIR = (%s, %s)\n", i, - cs_reg_name(handle, op->reg_pair.reg_0), - cs_reg_name(handle, op->reg_pair.reg_1)); - break; - case M68K_OP_BR_DISP: - printf("\t\toperands[%u].br_disp.disp: 0x%x", i, op->br_disp.disp); - printf("\t\toperands[%u].br_disp.disp_size: %d", i, op->br_disp.disp_size); - break; - } - } - - printf("\n"); -} - -static void test() -{ -#define M68K_CODE "\xf0\x10\xf0\x00\x48\xaf\xff\xff\x7f\xff\x11\xb0\x01\x37\x7f\xff\xff\xff\x12\x34\x56\x78\x01\x33\x10\x10\x10\x10\x32\x32\x32\x32\x4C\x00\x54\x04\x48\xe7\xe0\x30\x4C\xDF\x0C\x07\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75" - struct platform platforms[] = { - { - CS_ARCH_M68K, - (cs_mode)(CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040), - (unsigned char*)M68K_CODE, - sizeof(M68K_CODE) - 1, - "M68K", - }, - }; - - uint64_t address = 0x01000; - cs_insn *insn; - int i; - size_t count; - - for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { - cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", err); - abort(); - } - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); - if (count) { - size_t j; - - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code: ", platforms[i].code, platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - assert(address == insn[j].address && "this means the size of the previous instruction was incorrect"); - address += insn[j].size; - printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); - print_insn_detail(&insn[j]); - } - printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - abort(); - } - - printf("\n"); - - cs_close(&handle); - } -} - -int main() -{ - test(); - - return 0; -} diff --git a/tests/test_mips.c b/tests/test_mips.c deleted file mode 100644 index e5c5a400c9..0000000000 --- a/tests/test_mips.c +++ /dev/null @@ -1,175 +0,0 @@ -/* Capstone Disassembler Engine */ -/* By Nguyen Anh Quynh , 2013-2019 */ - -#include -#include - -#include -#include - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - const char *comment; -}; - -static csh handle; - -static void print_string_hex(const char *comment, unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("%s", comment); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - - printf("\n"); -} - -static void print_insn_detail(cs_insn *ins) -{ - int i; - cs_mips *mips; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - mips = &(ins->detail->mips); - if (mips->op_count) - printf("\top_count: %u\n", mips->op_count); - - for (i = 0; i < mips->op_count; i++) { - cs_mips_op *op = &(mips->operands[i]); - switch((int)op->type) { - default: - break; - case MIPS_OP_REG: - printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); - break; - case MIPS_OP_IMM: - printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); - break; - case MIPS_OP_MEM: - printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.base != MIPS_REG_INVALID) - printf("\t\t\toperands[%u].mem.base: REG = %s\n", - i, cs_reg_name(handle, op->mem.base)); - if (op->mem.disp != 0) - printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp); - - break; - } - - } - - printf("\n"); -} - -static void test() -{ -#define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56" -#define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00" -#define MIPS_32R6M "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0" -#define MIPS_32R6 "\xec\x80\x00\x19\x7c\x43\x22\xa0" -#define MIPS_64SD "\x70\x00\xb2\xff" - - struct platform platforms[] = { - { - CS_ARCH_MIPS, - (cs_mode)(CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN), - (unsigned char *)MIPS_CODE, - sizeof(MIPS_CODE) - 1, - "MIPS-32 (Big-endian)" - }, - { - CS_ARCH_MIPS, - (cs_mode)(CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN), - (unsigned char *)MIPS_CODE2, - sizeof(MIPS_CODE2) - 1, - "MIPS-64-EL (Little-endian)" - }, - { - CS_ARCH_MIPS, - (cs_mode)(CS_MODE_MIPS32R6 | CS_MODE_MICRO | CS_MODE_BIG_ENDIAN), - (unsigned char*)MIPS_32R6M, - sizeof(MIPS_32R6M) - 1, - "MIPS-32R6 | Micro (Big-endian)" - }, - { - CS_ARCH_MIPS, - (cs_mode)(CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN), - (unsigned char*)MIPS_32R6, - sizeof(MIPS_32R6) - 1, - "MIPS-32R6 (Big-endian)" - }, - { - CS_ARCH_MIPS, - (cs_mode)(CS_MODE_MIPS64 | CS_MODE_MIPS2 | CS_MODE_LITTLE_ENDIAN), - (unsigned char *)MIPS_64SD, - sizeof(MIPS_64SD) - 1, - "MIPS-64-EL + Mips II (Little-endian)" - }, - { - CS_ARCH_MIPS, - (cs_mode)(CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN), - (unsigned char *)MIPS_64SD, - sizeof(MIPS_64SD) - 1, - "MIPS-64-EL (Little-endian)" - }, - }; - - uint64_t address = 0x1000; - cs_insn *insn; - int i; - size_t count; - - for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { - cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", err); - abort(); - } - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); - if (count) { - size_t j; - - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); - print_insn_detail(&insn[j]); - } - printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - abort(); - } - - printf("\n"); - - cs_close(&handle); - } -} - -int main() -{ - test(); - - return 0; -} diff --git a/tests/test_mos65xx.c b/tests/test_mos65xx.c deleted file mode 100644 index bb53bea2e8..0000000000 --- a/tests/test_mos65xx.c +++ /dev/null @@ -1,230 +0,0 @@ -/* Capstone Disassembler Engine */ -/* By Sebastian Macke , 2018 */ - -#include -#include - -#include -#include - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - const char *comment; -}; - -static csh handle; - -static void print_string_hex(const char *comment, unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("%s", comment); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - - printf("\n"); -} - -static const char *get_am_name(mos65xx_address_mode mode) -{ - switch(mode) { - default: - case MOS65XX_AM_NONE: - return "No address mode"; - case MOS65XX_AM_IMP: - return "implied"; - case MOS65XX_AM_ACC: - return "accumulator"; - case MOS65XX_AM_IMM: - return "immediate value"; - case MOS65XX_AM_REL: - return "relative"; - case MOS65XX_AM_INT: - return "interrupt signature"; - case MOS65XX_AM_BLOCK: - return "block move"; - case MOS65XX_AM_ZP: - return "zero page"; - case MOS65XX_AM_ZP_X: - return "zero page indexed with x"; - case MOS65XX_AM_ZP_Y: - return "zero page indexed with y"; - case MOS65XX_AM_ZP_REL: - return "relative bit branch"; - case MOS65XX_AM_ZP_IND: - return "zero page indirect"; - case MOS65XX_AM_ZP_X_IND: - return "zero page indexed with x indirect"; - case MOS65XX_AM_ZP_IND_Y: - return "zero page indirect indexed with y"; - case MOS65XX_AM_ZP_IND_LONG: - return "zero page indirect long"; - case MOS65XX_AM_ZP_IND_LONG_Y: - return "zero page indirect long indexed with y"; - case MOS65XX_AM_ABS: - return "absolute"; - case MOS65XX_AM_ABS_X: - return "absolute indexed with x"; - case MOS65XX_AM_ABS_Y: - return "absolute indexed with y"; - case MOS65XX_AM_ABS_IND: - return "absolute indirect"; - case MOS65XX_AM_ABS_X_IND: - return "absolute indexed with x indirect"; - case MOS65XX_AM_ABS_IND_LONG: - return "absolute indirect long"; - case MOS65XX_AM_ABS_LONG: - return "absolute long"; - case MOS65XX_AM_ABS_LONG_X: - return "absolute long indexed with x"; - case MOS65XX_AM_SR: - return "stack relative"; - case MOS65XX_AM_SR_IND_Y: - return "stack relative indirect indexed with y"; - } -} - - -static void print_insn_detail(cs_insn *ins) -{ - cs_mos65xx *mos65xx; - int i; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - mos65xx = &(ins->detail->mos65xx); - - // printf("insn_detail\n"); - printf("\taddress mode: %s\n", get_am_name(mos65xx->am)); - printf("\tmodifies flags: %s\n", mos65xx->modifies_flags ? "true": "false"); - - if (mos65xx->op_count) - printf("\top_count: %u\n", mos65xx->op_count); - - for (i = 0; i < mos65xx->op_count; i++) { - cs_mos65xx_op *op = &(mos65xx->operands[i]); - switch((int)op->type) { - default: - break; - case MOS65XX_OP_REG: - printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); - break; - case MOS65XX_OP_IMM: - printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); - break; - case MOS65XX_OP_MEM: - printf("\t\toperands[%u].type: MEM = 0x%x\n", i, op->mem); - break; - } - } -} - -static void test() -{ -#define M6502_CODE "\xa1\x12\xa5\x12\xa9\x12\xad\x34\x12\xb1\x12\xb5\x12\xb9\x34\x12\xbd\x34\x12" \ - "\x0d\x34\x12\x00\x81\x87\x6c\x01\x00\x85\xFF\x10\x00\x19\x42\x42\x00\x49\x42" - -#define M65C02_CODE "\x1a\x3a" \ - "\x02\x12\x03\x5c\x34\x12" - -#define MW65C02_CODE \ - "\x07\x12\x27\x12\x47\x12\x67\x12\x87\x12\xa7\x12\xc7\x12\xe7\x12" \ - "\x10\xfe\x0f\x12\xfd\x4f\x12\xfd\x8f\x12\xfd\xcf\x12\xfd" - -#define M65816_CODE \ - "\xa9\x34\x12" "\xad\x34\x12" "\xbd\x34\x12" "\xb9\x34\x12" \ - "\xaf\x56\x34\x12" "\xbf\x56\x34\x12" \ - "\xa5\x12" "\xb5\x12" "\xb2\x12" "\xa1\x12" "\xb1\x12" "\xa7\x12" "\xb7\x12" \ - "\xa3\x12" "\xb3\x12" \ - "\xc2\x00" "\xe2\x00" "\x54\x34\x12" "\x44\x34\x12" "\x02\x12" - - struct platform platforms[] = { - { - CS_ARCH_MOS65XX, - (cs_mode)(CS_MODE_MOS65XX_6502), - (unsigned char *)M6502_CODE, - sizeof(M6502_CODE) - 1, - "MOS65XX_6502" - }, - { - CS_ARCH_MOS65XX, - (cs_mode)(CS_MODE_MOS65XX_65C02), - (unsigned char *)M65C02_CODE, - sizeof(M65C02_CODE) - 1, - "MOS65XX_65C02" - }, - { - CS_ARCH_MOS65XX, - (cs_mode)(CS_MODE_MOS65XX_W65C02), - (unsigned char *)MW65C02_CODE, - sizeof(MW65C02_CODE) - 1, - "MOS65XX_W65C02" - }, - { - CS_ARCH_MOS65XX, - (cs_mode)(CS_MODE_MOS65XX_65816_LONG_MX), - (unsigned char *)M65816_CODE, - sizeof(M65816_CODE) - 1, - "MOS65XX_65816 (long m/x)" - }, - }; - - uint64_t address = 0x1000; - cs_insn *insn; - int i; - size_t count; - - for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { - cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u (%s)\n", err, cs_strerror(err)); - abort(); - } - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_MOTOROLA); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); - - if (count) { - size_t j; - - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code: ", platforms[i].code, platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); - print_insn_detail(&insn[j]); - puts(""); - } - printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - abort(); - } - - printf("\n"); - - cs_close(&handle); - } -} - -int main() -{ - test(); - return 0; -} diff --git a/tests/test_ppc.c b/tests/test_ppc.c deleted file mode 100644 index 2a21cbe7c1..0000000000 --- a/tests/test_ppc.c +++ /dev/null @@ -1,178 +0,0 @@ -/* Capstone Disassembler Engine */ -/* By Nguyen Anh Quynh , 2013-2019 */ - -#include - -#include -#include - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - const char *comment; -}; - -static csh handle; - -static void print_string_hex(const char *comment, unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("%s", comment); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - - printf("\n"); -} - -static void print_insn_detail(cs_insn *ins) -{ - cs_ppc *ppc; - int i; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - ppc = &(ins->detail->ppc); - if (ppc->op_count) - printf("\top_count: %u\n", ppc->op_count); - - for (i = 0; i < ppc->op_count; i++) { - cs_ppc_op *op = &(ppc->operands[i]); - switch((int)op->type) { - default: - break; - case PPC_OP_REG: - printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); - break; - case PPC_OP_IMM: - printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); - break; - case PPC_OP_MEM: - printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.base != PPC_REG_INVALID) - printf("\t\t\toperands[%u].mem.base: REG = %s\n", - i, cs_reg_name(handle, op->mem.base)); - if (op->mem.offset != 0) - printf("\t\t\toperands[%u].mem.offset: REG = %s\n", - i, cs_reg_name(handle, op->mem.offset)); - if (op->mem.disp != 0) - printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); - - break; - } - if (op->access == CS_AC_READ) - printf("\t\t\toperands[%u].access: READ\n", i); - else if (op->access == CS_AC_WRITE) - printf("\t\t\toperands[%u].access: WRITE\n", i); - else if (op->access == (CS_AC_READ | CS_AC_WRITE)) - printf("\t\t\toperands[%u].access: READ | WRITE\n", i); - } - - if (ppc->bc.pred_cr != PPC_PRED_INVALID || ppc->bc.pred_ctr != PPC_PRED_INVALID) { - printf("\tBranch:\n"); - printf("\t\tbi: %u\n", ppc->bc.bi); - printf("\t\tbo: %u\n", ppc->bc.bo); - if (ppc->bc.bh != PPC_BH_INVALID) - printf("\t\tbh: %u\n", ppc->bc.bh); - if (ppc->bc.pred_cr != PPC_PRED_INVALID) { - printf("\t\tcrX: %s\n", cs_reg_name(handle, ppc->bc.crX)); - printf("\t\tpred CR-bit: %u\n", ppc->bc.pred_cr); - } - if (ppc->bc.pred_ctr != PPC_PRED_INVALID) - printf("\t\tpred CTR: %u\n", ppc->bc.pred_ctr); - if (ppc->bc.hint != PPC_BR_NOT_GIVEN) - printf("\t\thint: %u\n", ppc->bc.hint); - } - - if (ppc->update_cr0) - printf("\tUpdate-CR0: True\n"); - - printf("\n"); -} - -static void test() -{ -#define PPC_CODE "\x43\x20\x0c\x07\x41\x56\xff\x17\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14" -#define PPC_CODE2 "\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f" -#define PPC_CODE3 "\x10\x00\x1f\xec\xe0\x6d\x80\x04\xe4\x6d\x80\x04\x10\x60\x1c\x4c\x10\x60\x1c\x0c\xf0\x6d\x80\x04\xf4\x6d\x80\x04\x10\x60\x1c\x4e\x10\x60\x1c\x0e\x10\x60\x1a\x10\x10\x60\x1a\x11\x10\x63\x20\x2a\x10\x63\x20\x2b\x10\x83\x20\x40\x10\x83\x20\xC0\x10\x83\x20\x00\x10\x83\x20\x80\x10\x63\x20\x24\x10\x63\x20\x25\x10\x63\x29\x3a\x10\x63\x29\x3b\x10\x63\x29\x1c\x10\x63\x29\x1d\x10\x63\x29\x1e\x10\x63\x29\x1f\x10\x63\x24\x20\x10\x63\x24\x21\x10\x63\x24\x60\x10\x63\x24\x61\x10\x63\x24\xA0\x10\x63\x24\xA1\x10\x63\x24\xE0\x10\x63\x24\xE1\x10\x60\x20\x90\x10\x60\x20\x91\x10\x63\x29\x38\x10\x63\x29\x39\x10\x63\x01\x32\x10\x63\x01\x33\x10\x63\x01\x18\x10\x63\x01\x19\x10\x63\x01\x1A\x10\x63\x01\x1B\x10\x60\x19\x10\x10\x60\x19\x11\x10\x60\x18\x50\x10\x60\x18\x51\x10\x63\x29\x3e\x10\x63\x29\x3f\x10\x63\x29\x3c\x10\x63\x29\x3d\x10\x60\x18\x30\x10\x60\x18\x31\x10\x60\x18\x34\x10\x60\x18\x35\x10\x63\x29\x2e\x10\x63\x29\x2f\x10\x63\x20\x28\x10\x63\x20\x29\x10\x63\x29\x14\x10\x63\x29\x15\x10\x63\x29\x16\x10\x63\x29\x17" - - struct platform platforms[] = { - { - CS_ARCH_PPC, - CS_MODE_BIG_ENDIAN, - (unsigned char*)PPC_CODE, - sizeof(PPC_CODE) - 1, - "PPC-64", - }, - { - CS_ARCH_PPC, - (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_QPX), - (unsigned char*)PPC_CODE2, - sizeof(PPC_CODE2) - 1, - "PPC-64 + QPX", - }, - { - CS_ARCH_PPC, - (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_PS), - (unsigned char*)PPC_CODE3, - sizeof(PPC_CODE3) - 1, - "PPC + PS", - }, - }; - - uint64_t address = 0x1000; - cs_insn *insn; - int i; - size_t count; - - for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { - cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", err); - abort(); - } - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); - if (count) { - size_t j; - - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); - print_insn_detail(&insn[j]); - } - printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - abort(); - } - - printf("\n"); - - cs_close(&handle); - } -} - -int main() -{ - test(); - - return 0; -} diff --git a/tests/test_riscv.c b/tests/test_riscv.c deleted file mode 100644 index 7da86e36f2..0000000000 --- a/tests/test_riscv.c +++ /dev/null @@ -1,176 +0,0 @@ -#include -#include - -#include -#include - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - const char *comment; -}; - -static csh handle; - -static void print_string_hex(const char *comment, unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("%s", comment); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - - printf("\n"); -} - -static void print_insn_detail(cs_insn *ins) -{ - int i; - int n; - cs_riscv *riscv; - cs_detail *detail; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - riscv = &(ins->detail->riscv); - detail = ins->detail; - if (riscv->op_count) - printf("\top_count: %u\n", riscv->op_count); - - for (i = 0; i < riscv->op_count; i++) { - cs_riscv_op *op = &(riscv->operands[i]); - switch((int)op->type) { - default: - printf("\terror in opt_type: %u\n", (int)op->type); - break; - case RISCV_OP_REG: - printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); - break; - case RISCV_OP_IMM: - printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); - break; - case RISCV_OP_MEM: - printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.base != RISCV_REG_INVALID) - printf("\t\t\toperands[%u].mem.base: REG = %s\n", - i, cs_reg_name(handle, op->mem.base)); - if (op->mem.disp != 0) - printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp); - - break; - } - - switch(op->access) { - default: - break; - case CS_AC_READ: - printf("\t\toperands[%u].access: READ\n", i); - break; - case CS_AC_WRITE: - printf("\t\toperands[%u].access: WRITE\n", i); - break; - case CS_AC_READ | CS_AC_WRITE: - printf("\t\toperands[%u].access: READ | WRITE\n", i); - break; - } - - } - - //print the groups this instruction belongs to - if (detail->groups_count > 0) { - printf("\tgroups: "); - for (n = 0; n < detail->groups_count; n++) { - printf("%s ", cs_group_name(handle, detail->groups[n])); - } - printf("\n"); - } - - printf("\n"); -} - -static void test() -{ -#define RISCV_CODE32 "\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xff\xe7\x00\x45\x00\xe7\x00\xc0\xff\x63\x05\x41\x00\xe3\x9d\x61\xfe\x63\xca\x93\x00\x63\x53\xb5\x00\x63\x65\xd6\x00\x63\x76\xf7\x00\x03\x88\x18\x00\x03\x99\x49\x00\x03\xaa\x6a\x00\x03\xcb\x2b\x01\x03\xdc\x8c\x01\x23\x86\xad\x03\x23\x9a\xce\x03\x23\x8f\xef\x01\x93\x00\xe0\x00\x13\xa1\x01\x01\x13\xb2\x02\x7d\x13\xc3\x03\xdd\x13\xe4\xc4\x12\x13\xf5\x85\x0c\x13\x96\xe6\x01\x13\xd7\x97\x01\x13\xd8\xf8\x40\x33\x89\x49\x01\xb3\x0a\x7b\x41\x33\xac\xac\x01\xb3\x3d\xde\x01\x33\xd2\x62\x40\xb3\x43\x94\x00\x33\xe5\xc5\x00\xb3\x76\xf7\x00\xb3\x54\x39\x01\xb3\x50\x31\x00\x33\x9f\x0f\x00\x73\x15\x04\xb0\xf3\x56\x00\x10\x33\x05\x7b\x03\xb3\x45\x9c\x03\x33\x66\xbd\x03\x2f\xa4\x02\x10\xaf\x23\x65\x18\x2f\x27\x2f\x01\x43\xf0\x20\x18\xd3\x72\x73\x00\x53\xf4\x04\x58\x53\x85\xc5\x28\x53\x2e\xde\xa1\xd3\x84\x05\xf0\x53\x06\x05\xe0\x53\x75\x00\xc0\xd3\xf0\x05\xd0\xd3\x15\x08\xe0\x87\xaa\x75\x00\x27\x27\x66\x01\x43\xf0\x20\x1a\xd3\x72\x73\x02\x53\xf4\x04\x5a\x53\x85\xc5\x2a\x53\x2e\xde\xa3" -#define RISCV_CODE64 "\x13\x04\xa8\x7a\xbb\x07\x9c\x02\xbb\x40\x5d\x02\x3b\x63\xb7\x03\x2f\xb4\x02\x10\xaf\x33\x65\x18\x2f\x37\x2f\x01\x53\x75\x20\xc0\xd3\xf0\x25\xd0\xd3\x84\x05\xf2\x53\x06\x05\xe2\x53\x75\x00\xc2\xd3\x80\x05\xd2\xd3\x15\x08\xe2\x87\xba\x75\x00\x27\x37\x66\x01" -#define RISCV_CODEC "\xe8\x1f\x7d\x61\x80\x25\x00\x46\x88\xa2\x04\xcb\x55\x13\xf2\x93\x5d\x45\x19\x80\x15\x68\x2a\xa4\x62\x24\xa6\xff\x2a\x65\x76\x86\x65\xdd\x01\x00\xfd\xaf\x82\x82\x11\x20\x82\x94" - struct platform platforms[] = { - { - CS_ARCH_RISCV, - CS_MODE_RISCV32, - (unsigned char *)RISCV_CODE32, - sizeof(RISCV_CODE32) - 1, - "riscv32" - }, - { - CS_ARCH_RISCV, - CS_MODE_RISCV64, - (unsigned char *)RISCV_CODE64, - sizeof(RISCV_CODE64) - 1, - "riscv64" - }, - { - CS_ARCH_RISCV, - CS_MODE_RISCVC, - (unsigned char *)RISCV_CODEC, - sizeof(RISCV_CODEC) - 1, - "riscvc" - } - }; - - uint64_t address = 0x1000; - cs_insn *insn; - int i; - size_t count; - - for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { - cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", err); - continue; - } - - //To turn on or off the Print Details option - //cs_option(handle, CS_OPT_DETAIL, CS_OPT_OFF); - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); - if (count) { - size_t j; - - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); - print_insn_detail(&insn[j]); - } - printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - } - - printf("\n"); - - cs_close(&handle); - } -} - -int main() -{ - test(); - - return 0; -} diff --git a/tests/test_sh.c b/tests/test_sh.c deleted file mode 100644 index de49fa0166..0000000000 --- a/tests/test_sh.c +++ /dev/null @@ -1,253 +0,0 @@ -/* Capstone Disassembler Engine */ -/* SuperH Backend by Yoshinori Sato */ - -#include -#include - -#include -#include - -#define WITH_DETAILS - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - const char *comment; -}; - -static void print_string_hex(const char *comment, unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("%s", comment); - - for (c = str; c < str + len; c++) - printf("0x%02x ", *c & 0xff); - - printf("\n"); -} - -static void print_read_write_regs(csh handle, cs_detail *detail) -{ - int i; - - if (detail->regs_read_count > 0) { - printf("\tRegisters read:"); - - for (i = 0; i < detail->regs_read_count; ++i) - printf(" %s", - cs_reg_name(handle, detail->regs_read[i])); - - printf("\n"); - } - - if (detail->regs_write_count > 0) { - printf("\tRegisters modified:"); - - for (i = 0; i < detail->regs_write_count; ++i) - printf(" %s", - cs_reg_name(handle, detail->regs_write[i])); - - printf("\n"); - } -} - -static char *reg_address_msg[] = { - "Register indirect", - "Register indirect with predecrement", - "Register indirect with postincrement", -}; - -static void print_insn_detail(csh handle, cs_insn *insn) -{ - cs_detail *detail = insn->detail; - cs_sh *sh = NULL; - int i; - int n; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (detail == NULL) - return; - - sh = &detail->sh; - - if (sh->op_count) - printf("\top_count: %u\n", sh->op_count); - - for (i = 0; i < sh->op_count; i++) { - cs_sh_op *op = &(sh->operands[i]); - - switch ((int)op->type) { - default: - break; - - case SH_OP_REG: - printf("\t\toperands[%u].type: REGISTER = %s\n", i, - cs_reg_name(handle, op->reg)); - break; - - case SH_OP_IMM: - printf("\t\toperands[%u].type: IMMEDIATE = #%" PRIu64 "\n", i, - op->imm); - break; - - case SH_OP_MEM: - printf("\t\toperands[%u].type: MEM ", i); - switch(op->mem.address) { - case SH_OP_MEM_REG_IND: - case SH_OP_MEM_REG_POST: - case SH_OP_MEM_REG_PRE: - printf("%s REG %s\n", - reg_address_msg[op->mem.address - SH_OP_MEM_REG_IND], - cs_reg_name(handle, op->mem.reg)); - break; - case SH_OP_MEM_REG_DISP: - printf("Register indirect with displacement REG %s, DISP %d\n", - cs_reg_name(handle, op->mem.reg), - op->mem.disp); - break; - - case SH_OP_MEM_REG_R0: - printf("R0 indexed\n"); - break; - - case SH_OP_MEM_GBR_DISP: - printf("GBR base with displacement DISP %d\n", - op->mem.disp); - break; - - case SH_OP_MEM_GBR_R0: - printf("GBR base with R0 indexed\n"); - break; - - case SH_OP_MEM_PCR: - printf("PC relative Address=0x%08x\n", - op->mem.disp); - break; - - case SH_OP_MEM_TBR_DISP: - printf("TBR base with displacement DISP %d\n", - op->mem.disp); - break; - case SH_OP_MEM_INVALID: - break; - } - break; - } - - if (sh->size != 0) - printf("\t\t\tsize: %u\n", sh->size); - - } - - print_read_write_regs(handle, detail); - - if (detail->groups_count > 0) { - printf("\tgroups: "); - for (n = 0; n < detail->groups_count; n++) { - printf("%s ", cs_group_name(handle, detail->groups[n])); - } - printf("\n"); - } - - printf("\n"); -} - -static bool consistency_checks() -{ - return true; -} - -static void test() -{ -#define SH4A_CODE \ - "\x0c\x31\x10\x20\x22\x21\x36\x64\x46\x25\x12\x12\x1c\x02\x08\xc1\x05\xc7\x0c" \ - "\x71\x1f\x02\x22\xcf\x06\x89\x23\x00\x2b\x41\x0b\x00\x0e\x40\x32\x00\x0a\xf1\x09\x00" - -#define SH2A_CODE \ - "\x32\x11\x92\x00\x32\x49\x31\x00" - - struct platform platforms[] = { - { - CS_ARCH_SH, - (cs_mode)(CS_MODE_SH4A | CS_MODE_SHFPU), - (unsigned char *)SH4A_CODE, - sizeof(SH4A_CODE) - 1, - "SH_SH4A", - }, - { - CS_ARCH_SH, - (cs_mode)(CS_MODE_SH2A | CS_MODE_SHFPU | CS_MODE_BIG_ENDIAN), - (unsigned char *)SH2A_CODE, - sizeof(SH2A_CODE) - 1, - "SH_SH2A", - }, - }; - - uint64_t address = 0x80000000; - csh handle; - cs_insn *insn; - int i; - size_t count; - - if (!consistency_checks()) - abort(); - - for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) { - cs_err err = cs_open(platforms[i].arch, platforms[i].mode, - &handle); - - if (err) { - printf("Failed on cs_open() with error returned: %u\n", - err); - abort(); - } - -#ifdef WITH_DETAILS - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); -#endif - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, - address, 0, &insn); - - if (count) { - size_t j; - - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code: ", platforms[i].code, - platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%"PRIx64":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); -#ifdef WITH_DETAILS - print_insn_detail(handle, &insn[j]); -#endif - } - printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } - else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, - platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - abort(); - } - - cs_close(&handle); - } -} - -int main() -{ - test(); - - return 0; -} diff --git a/tests/test_sparc.c b/tests/test_sparc.c deleted file mode 100644 index 98c39494eb..0000000000 --- a/tests/test_sparc.c +++ /dev/null @@ -1,152 +0,0 @@ -/* Capstone Disassembler Engine */ -/* By Nguyen Anh Quynh , 2013-2019 */ - -#include - -#include -#include - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - const char *comment; -}; - -static csh handle; - -static void print_string_hex(const char *comment, unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("%s", comment); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - - printf("\n"); -} - -static void print_insn_detail(cs_insn *ins) -{ - cs_sparc *sparc; - int i; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - sparc = &(ins->detail->sparc); - if (sparc->op_count) - printf("\top_count: %u\n", sparc->op_count); - - for (i = 0; i < sparc->op_count; i++) { - cs_sparc_op *op = &(sparc->operands[i]); - switch((int)op->type) { - default: - break; - case SPARC_OP_REG: - printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); - break; - case SPARC_OP_IMM: - printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); - break; - case SPARC_OP_MEM: - printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.base != X86_REG_INVALID) - printf("\t\t\toperands[%u].mem.base: REG = %s\n", - i, cs_reg_name(handle, op->mem.base)); - if (op->mem.index != X86_REG_INVALID) - printf("\t\t\toperands[%u].mem.index: REG = %s\n", - i, cs_reg_name(handle, op->mem.index)); - if (op->mem.disp != 0) - printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); - - break; - } - } - - if (sparc->cc != 0) - printf("\tCode condition: %u\n", sparc->cc); - - if (sparc->hint != 0) - printf("\tHint code: %u\n", sparc->hint); - - printf("\n"); -} - -static void test() -{ -#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" - -#define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" - - struct platform platforms[] = { - { - CS_ARCH_SPARC, - CS_MODE_BIG_ENDIAN, - (unsigned char*)SPARC_CODE, - sizeof(SPARC_CODE) - 1, - "Sparc", - }, - { - CS_ARCH_SPARC, - (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9), - (unsigned char*)SPARCV9_CODE, - sizeof(SPARCV9_CODE) - 1, - "SparcV9" - }, - }; - - uint64_t address = 0x1000; - cs_insn *insn; - int i; - size_t count; - - for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { - cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", err); - abort(); - } - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); - if (count) { - size_t j; - - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); - print_insn_detail(&insn[j]); - } - printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - abort(); - } - - printf("\n"); - - cs_close(&handle); - } -} - -int main() -{ - test(); - - return 0; -} diff --git a/tests/test_systemz.c b/tests/test_systemz.c deleted file mode 100644 index f662247b89..0000000000 --- a/tests/test_systemz.c +++ /dev/null @@ -1,145 +0,0 @@ -/* Capstone Disassembler Engine */ -/* By Nguyen Anh Quynh , 2013-2019 */ - -#include - -#include -#include - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - const char *comment; -}; - -static csh handle; - -static void print_string_hex(const char *comment, unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("%s", comment); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - - printf("\n"); -} - -static void print_insn_detail(cs_insn *ins) -{ - cs_sysz *sysz; - int i; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - sysz = &(ins->detail->sysz); - if (sysz->op_count) - printf("\top_count: %u\n", sysz->op_count); - - for (i = 0; i < sysz->op_count; i++) { - cs_sysz_op *op = &(sysz->operands[i]); - switch((int)op->type) { - default: - break; - case SYSZ_OP_REG: - printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); - break; - case SYSZ_OP_ACREG: - printf("\t\toperands[%u].type: ACREG = %u\n", i, op->reg); - break; - case SYSZ_OP_IMM: - printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); - break; - case SYSZ_OP_MEM: - printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.base != SYSZ_REG_INVALID) - printf("\t\t\toperands[%u].mem.base: REG = %s\n", - i, cs_reg_name(handle, op->mem.base)); - if (op->mem.index != SYSZ_REG_INVALID) - printf("\t\t\toperands[%u].mem.index: REG = %s\n", - i, cs_reg_name(handle, op->mem.index)); - if (op->mem.length != 0) - printf("\t\t\toperands[%u].mem.length: 0x%" PRIx64 "\n", i, op->mem.length); - if (op->mem.disp != 0) - printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp); - - break; - } - } - - if (sysz->cc != 0) - printf("\tCode condition: %u\n", sysz->cc); - - printf("\n"); -} - -static void test() -{ -#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78\xec\x18\x00\x00\xc1\x7f" - - struct platform platforms[] = { - { - CS_ARCH_SYSZ, - CS_MODE_BIG_ENDIAN, - (unsigned char*)SYSZ_CODE, - sizeof(SYSZ_CODE) - 1, - "SystemZ", - }, - }; - - uint64_t address = 0x1000; - cs_insn *insn; - int i; - size_t count; - - for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { - cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", err); - abort(); - } - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); - if (count) { - size_t j; - - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); - print_insn_detail(&insn[j]); - } - printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - abort(); - } - - printf("\n"); - - cs_close(&handle); - } -} - -int main() -{ - test(); - - return 0; -} diff --git a/tests/test_tms320c64x.c b/tests/test_tms320c64x.c deleted file mode 100644 index 28bc05e286..0000000000 --- a/tests/test_tms320c64x.c +++ /dev/null @@ -1,193 +0,0 @@ -/* Capstone Disassembly Engine */ -/* TMS320C64x Backend by Fotis Loukos 2016 */ - -#include - -#include - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - const char *comment; -}; - -static csh handle; - -static void print_string_hex(const char *comment, unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("%s", comment); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - - printf("\n"); -} - -static void print_insn_detail(cs_insn *ins) -{ - cs_tms320c64x *tms320c64x; - int i; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - tms320c64x = &(ins->detail->tms320c64x); - if (tms320c64x->op_count) - printf("\top_count: %u\n", tms320c64x->op_count); - - for (i = 0; i < tms320c64x->op_count; i++) { - cs_tms320c64x_op *op = &(tms320c64x->operands[i]); - switch((int)op->type) { - default: - break; - case TMS320C64X_OP_REG: - printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); - break; - case TMS320C64X_OP_IMM: - printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); - break; - case TMS320C64X_OP_MEM: - printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.base != TMS320C64X_REG_INVALID) - printf("\t\t\toperands[%u].mem.base: REG = %s\n", - i, cs_reg_name(handle, op->mem.base)); - printf("\t\t\toperands[%u].mem.disptype: ", i); - if(op->mem.disptype == TMS320C64X_MEM_DISP_INVALID) { - printf("Invalid\n"); - printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); - } - if(op->mem.disptype == TMS320C64X_MEM_DISP_CONSTANT) { - printf("Constant\n"); - printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); - } - if(op->mem.disptype == TMS320C64X_MEM_DISP_REGISTER) { - printf("Register\n"); - printf("\t\t\toperands[%u].mem.disp: %s\n", i, cs_reg_name(handle, op->mem.disp)); - } - printf("\t\t\toperands[%u].mem.unit: %u\n", i, op->mem.unit); - printf("\t\t\toperands[%u].mem.direction: ", i); - if(op->mem.direction == TMS320C64X_MEM_DIR_INVALID) - printf("Invalid\n"); - if(op->mem.direction == TMS320C64X_MEM_DIR_FW) - printf("Forward\n"); - if(op->mem.direction == TMS320C64X_MEM_DIR_BW) - printf("Backward\n"); - printf("\t\t\toperands[%u].mem.modify: ", i); - if(op->mem.modify == TMS320C64X_MEM_MOD_INVALID) - printf("Invalid\n"); - if(op->mem.modify == TMS320C64X_MEM_MOD_NO) - printf("No\n"); - if(op->mem.modify == TMS320C64X_MEM_MOD_PRE) - printf("Pre\n"); - if(op->mem.modify == TMS320C64X_MEM_MOD_POST) - printf("Post\n"); - printf("\t\t\toperands[%u].mem.scaled: %u\n", i, op->mem.scaled); - - - break; - case TMS320C64X_OP_REGPAIR: - printf("\t\toperands[%u].type: REGPAIR = %s:%s\n", i, cs_reg_name(handle, op->reg + 1), cs_reg_name(handle, op->reg)); - break; - } - } - - printf("\tFunctional unit: "); - switch(tms320c64x->funit.unit) { - case TMS320C64X_FUNIT_D: - printf("D%u\n", tms320c64x->funit.side); - break; - case TMS320C64X_FUNIT_L: - printf("L%u\n", tms320c64x->funit.side); - break; - case TMS320C64X_FUNIT_M: - printf("M%u\n", tms320c64x->funit.side); - break; - case TMS320C64X_FUNIT_S: - printf("S%u\n", tms320c64x->funit.side); - break; - case TMS320C64X_FUNIT_NO: - printf("No Functional Unit\n"); - break; - default: - printf("Unknown (Unit %u, Side %u)\n", tms320c64x->funit.unit, tms320c64x->funit.side); - break; - } - if(tms320c64x->funit.crosspath == 1) - printf("\tCrosspath: 1\n"); - - if(tms320c64x->condition.reg != TMS320C64X_REG_INVALID) - printf("\tCondition: [%c%s]\n", (tms320c64x->condition.zero == 1) ? '!' : ' ', cs_reg_name(handle, tms320c64x->condition.reg)); - printf("\tParallel: %s\n", (tms320c64x->parallel == 1) ? "true" : "false"); - - printf("\n"); -} - -static void test() -{ -#define TMS320C64X_CODE "\x01\xac\x88\x40\x81\xac\x88\x43\x00\x00\x00\x00\x02\x90\x32\x96\x02\x80\x46\x9e\x05\x3c\x83\xe6\x0b\x0c\x8b\x24" - - struct platform platforms[] = { - { - CS_ARCH_TMS320C64X, - CS_MODE_BIG_ENDIAN, - (unsigned char*)TMS320C64X_CODE, - sizeof(TMS320C64X_CODE) - 1, - "TMS320C64x", - }, - }; - - uint64_t address = 0x1000; - cs_insn *insn; - int i; - size_t count; - - for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { - cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", err); - continue; - } - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); - if (count) { - size_t j; - - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%"PRIx64":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); - print_insn_detail(&insn[j]); - } - printf("0x%"PRIx64":\n", insn[j-1].address + insn[j-1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - } - - printf("\n"); - - cs_close(&handle); - } -} - -int main() -{ - test(); - - return 0; -} diff --git a/tests/test_tricore.c b/tests/test_tricore.c deleted file mode 100644 index 38e71ba6e8..0000000000 --- a/tests/test_tricore.c +++ /dev/null @@ -1,145 +0,0 @@ -/* Capstone Disassembler Engine */ -/* By Nguyen Anh Quynh , 2013-2014 */ - -#include - -#include -#include - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - char *comment; -}; - -static csh handle; - -static void print_string_hex(char *comment, unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("%s", comment); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - - printf("\n"); -} - -static void print_insn_detail(cs_insn *ins) -{ - cs_tricore *tricore; - int i; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - tricore = &(ins->detail->tricore); - if (tricore->op_count) - printf("\top_count: %u\n", tricore->op_count); - - for (i = 0; i < tricore->op_count; i++) { - cs_tricore_op *op = &(tricore->operands[i]); - switch ((int)op->type) { - default: - break; - case TRICORE_OP_REG: - printf("\t\toperands[%u].type: REG = %s\n", i, - cs_reg_name(handle, op->reg)); - break; - case TRICORE_OP_IMM: - printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", - i, op->imm); - break; - case TRICORE_OP_MEM: - printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.base != TRICORE_REG_INVALID) - printf("\t\t\toperands[%u].mem.base: REG = %s\n", - i, cs_reg_name(handle, op->mem.base)); - if (op->mem.disp != 0) - printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 - "\n", - i, op->mem.disp); - - break; - } - } - - printf("\n"); -} - -static void test() -{ -//#define TRICORE_CODE "\x16\x01\x20\x01\x1d\x00\x02\x00\x8f\x70\x00\x11\x40\xae\x89\xee\x04\x09\x42\xf2\xe2\xf2\xc2\x11\x19\xff\xc0\x70\x19\xff\x20\x10" -#define TRICORE_CODE \ - "\x09\xcf\xbc\xf5\x09\xf4\x01\x00\x89\xfb\x8f\x74\x89\xfe\x48\x01\x29\x00\x19\x25\x29\x03\x09\xf4\x85\xf9\x68\x0f\x16\x01" - - struct platform platforms[] = { - { - CS_ARCH_TRICORE, - CS_MODE_TRICORE_162, - (unsigned char *)TRICORE_CODE, - sizeof(TRICORE_CODE) - 1, - "TriCore", - }, - }; - - uint64_t address = 0x1000; - cs_insn *insn; - int i; - size_t count; - - for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) { - cs_err err = - cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", - err); - continue; - } - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, - address, 0, &insn); - if (count) { - size_t j; - - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, - platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%" PRIx64 ":\t%s\t%s\n", - insn[j].address, insn[j].mnemonic, - insn[j].op_str); - print_insn_detail(&insn[j]); - } - printf("0x%" PRIx64 ":\n", - insn[j - 1].address + insn[j - 1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, - platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - } - - cs_close(&handle); - } -} - -int main() -{ - test(); - - return 0; -} diff --git a/tests/test_wasm.c b/tests/test_wasm.c deleted file mode 100644 index 95e387d193..0000000000 --- a/tests/test_wasm.c +++ /dev/null @@ -1,159 +0,0 @@ -/* Capstone Disassembler Engine */ -/* By Spike , 2018 */ - -#include -#include - -#include -#include - -static csh handle; - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - const char *comment; -}; - -static void print_string_hex(const char *comment, unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("%s", comment); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - - printf("\n"); -} - -static void print_insn_detail(csh cs_handle, cs_insn *ins) -{ - cs_wasm *wasm; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - if (ins->detail->groups_count) { - int j; - - printf("\tGroups: "); - for(j = 0; j < ins->detail->groups_count; j++) { - printf("%s ", cs_group_name(handle, ins->detail->groups[j])); - } - printf("\n"); - } - - wasm = &(ins->detail->wasm); - - if (wasm->op_count > 0) { - unsigned int i; - - printf("\tOperand count: %u\n", wasm->op_count); - - for (i = 0; i < wasm->op_count; i++) { - switch (wasm->operands[i].type) { - default: - break; - case WASM_OP_INT7: - printf("\t\tOperand[%u] type: int7\n", i); - printf("\t\tOperand[%u] value: %d\n", i, wasm->operands[i].int7); - break; - case WASM_OP_UINT32: - printf("\t\tOperand[%u] type: uint32\n", i); - printf("\t\tOperand[%u] value: 0x%x\n", i, wasm->operands[i].uint32); - break; - case WASM_OP_UINT64: - printf("\t\tOperand[%u] type: uint64\n", i); - printf("\t\tOperand[%u] value: 0x%" PRIx64 "\n", i, wasm->operands[i].uint64); - break; - case WASM_OP_VARUINT32: - printf("\t\tOperand[%u] type: varuint32\n", i); - printf("\t\tOperand[%u] value: 0x%x\n", i, wasm->operands[i].varuint32); - break; - case WASM_OP_VARUINT64: - printf("\t\tOperand[%u] type: varuint64\n", i); - printf("\t\tOperand[%u] value: 0x%" PRIx64 "\n", i, wasm->operands[i].varuint64); - break; - case WASM_OP_IMM: - printf("\t\tOperand[%u] type: imm\n", i); - printf("\t\tOperand[%u] value: 0x%x 0x%x\n", i, wasm->operands[i].immediate[0], wasm->operands[i].immediate[1]); - break; - case WASM_OP_BRTABLE: - printf("\t\tOperand[%u] type: brtable\n", i); - printf("\t\tOperand[%u] value: length=0x%x, address=0x%" PRIx64 ", default_target=%x\n", i, wasm->operands[i].brtable.length, wasm->operands[i].brtable.address, wasm->operands[i].brtable.default_target); - break; - } - printf("\t\tOperand[%u] size: %u\n", i, wasm->operands[i].size); - } - } - - printf("\n"); -} - -static void test() -{ -#define WASM_CODE "\x20\x00\x20\x01\x41\x20\x10\xc9\x01\x45\x0b" - struct platform platforms[] = { - { - CS_ARCH_WASM, - 0, - (unsigned char *)WASM_CODE, - sizeof(WASM_CODE) - 1, - "WASM" - }, - }; - - uint64_t address = 0xffff; - cs_insn *insn; - size_t count; - int i; - - for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { - cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", err); - abort(); - } - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); - if (count) { - size_t j; - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code: ", platforms[i].code, platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); - print_insn_detail(handle, &insn[j]); - } - printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code: ", platforms[i].code, platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - abort(); - } - - printf("\n"); - - cs_close(&handle); - } -} - -int main() -{ - test(); - return 0; -} - diff --git a/tests/test_x86.c b/tests/test_x86.c deleted file mode 100644 index 775c096d33..0000000000 --- a/tests/test_x86.c +++ /dev/null @@ -1,464 +0,0 @@ -/* Capstone Disassembler Engine */ -/* By Nguyen Anh Quynh , 2013 */ - -#include -#include - -#include -#include - -static csh handle; - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - const char *comment; - cs_opt_type opt_type; - cs_opt_value opt_value; -}; - -static void print_string_hex(const char *comment, unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("%s", comment); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - - printf("\n"); -} - -static const char *get_eflag_name(uint64_t flag) -{ - switch(flag) { - default: - return NULL; - case X86_EFLAGS_UNDEFINED_OF: - return "UNDEF_OF"; - case X86_EFLAGS_UNDEFINED_SF: - return "UNDEF_SF"; - case X86_EFLAGS_UNDEFINED_ZF: - return "UNDEF_ZF"; - case X86_EFLAGS_MODIFY_AF: - return "MOD_AF"; - case X86_EFLAGS_UNDEFINED_PF: - return "UNDEF_PF"; - case X86_EFLAGS_MODIFY_CF: - return "MOD_CF"; - case X86_EFLAGS_MODIFY_SF: - return "MOD_SF"; - case X86_EFLAGS_MODIFY_ZF: - return "MOD_ZF"; - case X86_EFLAGS_UNDEFINED_AF: - return "UNDEF_AF"; - case X86_EFLAGS_MODIFY_PF: - return "MOD_PF"; - case X86_EFLAGS_UNDEFINED_CF: - return "UNDEF_CF"; - case X86_EFLAGS_MODIFY_OF: - return "MOD_OF"; - case X86_EFLAGS_RESET_OF: - return "RESET_OF"; - case X86_EFLAGS_RESET_CF: - return "RESET_CF"; - case X86_EFLAGS_RESET_DF: - return "RESET_DF"; - case X86_EFLAGS_RESET_IF: - return "RESET_IF"; - case X86_EFLAGS_TEST_OF: - return "TEST_OF"; - case X86_EFLAGS_TEST_SF: - return "TEST_SF"; - case X86_EFLAGS_TEST_ZF: - return "TEST_ZF"; - case X86_EFLAGS_TEST_PF: - return "TEST_PF"; - case X86_EFLAGS_TEST_CF: - return "TEST_CF"; - case X86_EFLAGS_RESET_SF: - return "RESET_SF"; - case X86_EFLAGS_RESET_AF: - return "RESET_AF"; - case X86_EFLAGS_RESET_TF: - return "RESET_TF"; - case X86_EFLAGS_RESET_NT: - return "RESET_NT"; - case X86_EFLAGS_PRIOR_OF: - return "PRIOR_OF"; - case X86_EFLAGS_PRIOR_SF: - return "PRIOR_SF"; - case X86_EFLAGS_PRIOR_ZF: - return "PRIOR_ZF"; - case X86_EFLAGS_PRIOR_AF: - return "PRIOR_AF"; - case X86_EFLAGS_PRIOR_PF: - return "PRIOR_PF"; - case X86_EFLAGS_PRIOR_CF: - return "PRIOR_CF"; - case X86_EFLAGS_PRIOR_TF: - return "PRIOR_TF"; - case X86_EFLAGS_PRIOR_IF: - return "PRIOR_IF"; - case X86_EFLAGS_PRIOR_DF: - return "PRIOR_DF"; - case X86_EFLAGS_TEST_NT: - return "TEST_NT"; - case X86_EFLAGS_TEST_DF: - return "TEST_DF"; - case X86_EFLAGS_RESET_PF: - return "RESET_PF"; - case X86_EFLAGS_PRIOR_NT: - return "PRIOR_NT"; - case X86_EFLAGS_MODIFY_TF: - return "MOD_TF"; - case X86_EFLAGS_MODIFY_IF: - return "MOD_IF"; - case X86_EFLAGS_MODIFY_DF: - return "MOD_DF"; - case X86_EFLAGS_MODIFY_NT: - return "MOD_NT"; - case X86_EFLAGS_MODIFY_RF: - return "MOD_RF"; - case X86_EFLAGS_SET_CF: - return "SET_CF"; - case X86_EFLAGS_SET_DF: - return "SET_DF"; - case X86_EFLAGS_SET_IF: - return "SET_IF"; - } -} - -static const char *get_fpu_flag_name(uint64_t flag) -{ - switch (flag) { - default: - return NULL; - case X86_FPU_FLAGS_MODIFY_C0: - return "MOD_C0"; - case X86_FPU_FLAGS_MODIFY_C1: - return "MOD_C1"; - case X86_FPU_FLAGS_MODIFY_C2: - return "MOD_C2"; - case X86_FPU_FLAGS_MODIFY_C3: - return "MOD_C3"; - case X86_FPU_FLAGS_RESET_C0: - return "RESET_C0"; - case X86_FPU_FLAGS_RESET_C1: - return "RESET_C1"; - case X86_FPU_FLAGS_RESET_C2: - return "RESET_C2"; - case X86_FPU_FLAGS_RESET_C3: - return "RESET_C3"; - case X86_FPU_FLAGS_SET_C0: - return "SET_C0"; - case X86_FPU_FLAGS_SET_C1: - return "SET_C1"; - case X86_FPU_FLAGS_SET_C2: - return "SET_C2"; - case X86_FPU_FLAGS_SET_C3: - return "SET_C3"; - case X86_FPU_FLAGS_UNDEFINED_C0: - return "UNDEF_C0"; - case X86_FPU_FLAGS_UNDEFINED_C1: - return "UNDEF_C1"; - case X86_FPU_FLAGS_UNDEFINED_C2: - return "UNDEF_C2"; - case X86_FPU_FLAGS_UNDEFINED_C3: - return "UNDEF_C3"; - case X86_FPU_FLAGS_TEST_C0: - return "TEST_C0"; - case X86_FPU_FLAGS_TEST_C1: - return "TEST_C1"; - case X86_FPU_FLAGS_TEST_C2: - return "TEST_C2"; - case X86_FPU_FLAGS_TEST_C3: - return "TEST_C3"; - } -} - -static void print_insn_detail(csh ud, cs_mode mode, cs_insn *ins) -{ - int count, i; - cs_x86 *x86; - cs_regs regs_read, regs_write; - uint8_t regs_read_count, regs_write_count; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - x86 = &(ins->detail->x86); - - print_string_hex("\tPrefix:", x86->prefix, 4); - - print_string_hex("\tOpcode:", x86->opcode, 4); - - printf("\trex: 0x%x\n", x86->rex); - - printf("\taddr_size: %u\n", x86->addr_size); - printf("\tmodrm: 0x%x\n", x86->modrm); - if (x86->encoding.modrm_offset != 0) { - printf("\tmodrm_offset: 0x%x\n", x86->encoding.modrm_offset); - } - - printf("\tdisp: 0x%" PRIx64 "\n", x86->disp); - if (x86->encoding.disp_offset != 0) { - printf("\tdisp_offset: 0x%x\n", x86->encoding.disp_offset); - } - - if (x86->encoding.disp_size != 0) { - printf("\tdisp_size: 0x%x\n", x86->encoding.disp_size); - } - - // SIB is not available in 16-bit mode - if ((mode & CS_MODE_16) == 0) { - printf("\tsib: 0x%x\n", x86->sib); - if (x86->sib_base != X86_REG_INVALID) - printf("\t\tsib_base: %s\n", cs_reg_name(handle, x86->sib_base)); - if (x86->sib_index != X86_REG_INVALID) - printf("\t\tsib_index: %s\n", cs_reg_name(handle, x86->sib_index)); - if (x86->sib_scale != 0) - printf("\t\tsib_scale: %d\n", x86->sib_scale); - } - - // XOP code condition - if (x86->xop_cc != X86_XOP_CC_INVALID) { - printf("\txop_cc: %u\n", x86->xop_cc); - } - - // SSE code condition - if (x86->sse_cc != X86_SSE_CC_INVALID) { - printf("\tsse_cc: %u\n", x86->sse_cc); - } - - // AVX code condition - if (x86->avx_cc != X86_AVX_CC_INVALID) { - printf("\tavx_cc: %u\n", x86->avx_cc); - } - - // AVX Suppress All Exception - if (x86->avx_sae) { - printf("\tavx_sae: %u\n", x86->avx_sae); - } - - // AVX Rounding Mode - if (x86->avx_rm != X86_AVX_RM_INVALID) { - printf("\tavx_rm: %u\n", x86->avx_rm); - } - - // Print out all immediate operands - count = cs_op_count(ud, ins, X86_OP_IMM); - if (count) { - printf("\timm_count: %u\n", count); - for (i = 1; i < count + 1; i++) { - int index = cs_op_index(ud, ins, X86_OP_IMM, i); - printf("\t\timms[%u]: 0x%" PRIx64 "\n", i, x86->operands[index].imm); - if (x86->encoding.imm_offset != 0) { - printf("\timm_offset: 0x%x\n", x86->encoding.imm_offset); - } - - if (x86->encoding.imm_size != 0) { - printf("\timm_size: 0x%x\n", x86->encoding.imm_size); - } - } - } - - if (x86->op_count) - printf("\top_count: %u\n", x86->op_count); - - // Print out all operands - for (i = 0; i < x86->op_count; i++) { - cs_x86_op *op = &(x86->operands[i]); - - switch((int)op->type) { - case X86_OP_REG: - printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); - break; - case X86_OP_IMM: - printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); - break; - case X86_OP_MEM: - printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.segment != X86_REG_INVALID) - printf("\t\t\toperands[%u].mem.segment: REG = %s\n", i, cs_reg_name(handle, op->mem.segment)); - if (op->mem.base != X86_REG_INVALID) - printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base)); - if (op->mem.index != X86_REG_INVALID) - printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index)); - if (op->mem.scale != 1) - printf("\t\t\toperands[%u].mem.scale: %u\n", i, op->mem.scale); - if (op->mem.disp != 0) - printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp); - break; - default: - break; - } - - // AVX broadcast type - if (op->avx_bcast != X86_AVX_BCAST_INVALID) - printf("\t\toperands[%u].avx_bcast: %u\n", i, op->avx_bcast); - - // AVX zero opmask {z} - if (op->avx_zero_opmask != false) - printf("\t\toperands[%u].avx_zero_opmask: TRUE\n", i); - - printf("\t\toperands[%u].size: %u\n", i, op->size); - - switch(op->access) { - default: - break; - case CS_AC_READ: - printf("\t\toperands[%u].access: READ\n", i); - break; - case CS_AC_WRITE: - printf("\t\toperands[%u].access: WRITE\n", i); - break; - case CS_AC_READ | CS_AC_WRITE: - printf("\t\toperands[%u].access: READ | WRITE\n", i); - break; - } - } - - // Print out all registers accessed by this instruction (either implicit or explicit) - if (!cs_regs_access(ud, ins, - regs_read, ®s_read_count, - regs_write, ®s_write_count)) { - if (regs_read_count) { - printf("\tRegisters read:"); - for(i = 0; i < regs_read_count; i++) { - printf(" %s", cs_reg_name(handle, regs_read[i])); - } - printf("\n"); - } - - if (regs_write_count) { - printf("\tRegisters modified:"); - for(i = 0; i < regs_write_count; i++) { - printf(" %s", cs_reg_name(handle, regs_write[i])); - } - printf("\n"); - } - } - - if (x86->eflags || x86->fpu_flags) { - for(i = 0; i < ins->detail->groups_count; i++) { - if (ins->detail->groups[i] == X86_GRP_FPU) { - printf("\tFPU_FLAGS:"); - for(i = 0; i <= 63; i++) - if (x86->fpu_flags & ((uint64_t)1 << i)) { - printf(" %s", get_fpu_flag_name((uint64_t)1 << i)); - } - printf("\n"); - break; - } - } - - if (i == ins->detail->groups_count) { - printf("\tEFLAGS:"); - for(i = 0; i <= 63; i++) - if (x86->eflags & ((uint64_t)1 << i)) { - printf(" %s", get_eflag_name((uint64_t)1 << i)); - } - printf("\n"); - } - } - - printf("\n"); -} - -static void test() -{ -#define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00\xe9\xea\xbe\xad\xde\xff\x25\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff" -#define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\x66\xe9\xb8\x00\x00\x00\x67\xff\xa0\x23\x01\x00\x00\x66\xe8\xcb\x00\x00\x00\x74\xfc" -#define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\xe9\xea\xbe\xad\xde\xff\xa0\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff" - - struct platform platforms[] = { - { - CS_ARCH_X86, - CS_MODE_16, - (unsigned char *)X86_CODE16, - sizeof(X86_CODE16) - 1, - "X86 16bit (Intel syntax)" - }, - { - CS_ARCH_X86, - CS_MODE_32, - (unsigned char *)X86_CODE32, - sizeof(X86_CODE32) - 1, - "X86 32 (AT&T syntax)", - CS_OPT_SYNTAX, - CS_OPT_SYNTAX_ATT, - }, - { - CS_ARCH_X86, - CS_MODE_32, - (unsigned char *)X86_CODE32, - sizeof(X86_CODE32) - 1, - "X86 32 (Intel syntax)" - }, - { - CS_ARCH_X86, - CS_MODE_64, - (unsigned char *)X86_CODE64, - sizeof(X86_CODE64) - 1, - "X86 64 (Intel syntax)" - }, - }; - - uint64_t address = 0x1000; - cs_insn *insn; - int i; - size_t count; - - for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { - cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", err); - abort(); - } - - if (platforms[i].opt_type) - cs_option(handle, platforms[i].opt_type, platforms[i].opt_value); - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); - if (count) { - size_t j; - - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); - print_insn_detail(handle, platforms[i].mode, &insn[j]); - } - printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - abort(); - } - - printf("\n"); - - cs_close(&handle); - } -} - -int main() -{ - test(); - - return 0; -} diff --git a/tests/test_xcore.c b/tests/test_xcore.c deleted file mode 100644 index 12cc1f1bba..0000000000 --- a/tests/test_xcore.c +++ /dev/null @@ -1,140 +0,0 @@ -/* Capstone Disassembler Engine */ -/* By Nguyen Anh Quynh , 2013-2014 */ - -#include - -#include -#include - -struct platform { - cs_arch arch; - cs_mode mode; - unsigned char *code; - size_t size; - const char *comment; -}; - -static csh handle; - -static void print_string_hex(const char *comment, unsigned char *str, size_t len) -{ - unsigned char *c; - - printf("%s", comment); - for (c = str; c < str + len; c++) { - printf("0x%02x ", *c & 0xff); - } - - printf("\n"); -} - -static void print_insn_detail(cs_insn *ins) -{ - cs_xcore *xcore; - int i; - - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; - - xcore = &(ins->detail->xcore); - if (xcore->op_count) - printf("\top_count: %u\n", xcore->op_count); - - for (i = 0; i < xcore->op_count; i++) { - cs_xcore_op *op = &(xcore->operands[i]); - switch((int)op->type) { - default: - break; - case XCORE_OP_REG: - printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); - break; - case XCORE_OP_IMM: - printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); - break; - case XCORE_OP_MEM: - printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.base != XCORE_REG_INVALID) - printf("\t\t\toperands[%u].mem.base: REG = %s\n", - i, cs_reg_name(handle, op->mem.base)); - if (op->mem.index != XCORE_REG_INVALID) - printf("\t\t\toperands[%u].mem.index: REG = %s\n", - i, cs_reg_name(handle, op->mem.index)); - if (op->mem.disp != 0) - printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); - if (op->mem.direct != 1) - printf("\t\t\toperands[%u].mem.direct: -1\n", i); - - - break; - } - } - - printf("\n"); -} - -static void test() -{ -#define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10\x09\xfd\xec\xa7" - - struct platform platforms[] = { - { - CS_ARCH_XCORE, - CS_MODE_BIG_ENDIAN, - (unsigned char*)XCORE_CODE, - sizeof(XCORE_CODE) - 1, - "XCore", - }, - }; - - uint64_t address = 0x1000; - cs_insn *insn; - int i; - size_t count; - - for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { - cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); - if (err) { - printf("Failed on cs_open() with error returned: %u\n", err); - abort(); - } - - cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - - count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); - if (count) { - size_t j; - - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("Disasm:\n"); - - for (j = 0; j < count; j++) { - printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); - print_insn_detail(&insn[j]); - } - printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); - - // free memory allocated by cs_disasm() - cs_free(insn, count); - } else { - printf("****************\n"); - printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); - printf("ERROR: Failed to disasm given code!\n"); - abort(); - } - - printf("\n"); - - cs_close(&handle); - } -} - -int main() -{ - test(); - - return 0; -} diff --git a/tests/unit/CMakeLists.txt b/tests/unit/CMakeLists.txt new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/unit/README.md b/tests/unit/README.md new file mode 100644 index 0000000000..cf9e0e6504 --- /dev/null +++ b/tests/unit/README.md @@ -0,0 +1,2 @@ +Nothing in here yet :( + diff --git a/utils.c b/utils.c index bd5fcf5612..3edf519c57 100644 --- a/utils.c +++ b/utils.c @@ -113,7 +113,11 @@ uint16_t readBytes16(MCInst *MI, const uint8_t *Bytes) /// @param str The string to append to. /// @param str_size The length of @p str /// @param src The string to append. +/// Does nothing if any of the given strings is NULL. void append_to_str_lower(char *str, size_t str_size, const char *src) { + if (!str || !src) { + return; + } char *dest = strchr(str, '\0'); if (dest - str >= str_size) { assert("str_size does not match actual string length." && 0); @@ -125,4 +129,61 @@ void append_to_str_lower(char *str, size_t str_size, const char *src) { str[i] = tolower(src[j]); } str[i] = '\0'; -} \ No newline at end of file +} + +/// @brief Appends the string @p src to the string @p str. @p src is put to lower case. +/// @param str The string to append to. +/// @param str_buf_size Size of buffer @p str. +/// @param src The string to append. +/// Does nothing if any of the given strings is NULL. +void append_to_str(char *str, size_t str_buf_size, const char *src) { + if (!str || !src) { + return; + } + if (strlen(str) + strlen(src) + 1 > str_buf_size) { + assert("str_size does not match actual string length." && 0); + return; + } + strncat(str, src, str_buf_size); +} + + +/// Allocates memory of strlen(str_a) + strlen(str_b) + 1 chars +/// and copies all strings into it as str_a + str_b +/// str_a is passed to realloc and should not be used afterwards. +/// Returns the result. +/// Returns NULL in case of failure. +char *str_append(char *str_a, const char *str_b) { + if (!str_a || !str_b) { + return NULL; + } + assert(str_a && str_b); + size_t asize = strlen(str_a) + strlen(str_b) + 1; + str_a = realloc(str_a, asize); + strncat(str_a, str_b, asize); + return str_a; +} + +/// Returns the given byte sequence @bytes as a string of the +/// form: 0xXX,0xXX... +/// Returns NULL in case of failure. +char *byte_seq_to_str(uint8_t *bytes, size_t len) +{ + if (!bytes) { + return NULL; + } + if (len == 0) { + return NULL; + } + char single_byte[8] = { 0 }; + char *s = calloc(sizeof(char), 32); + for (size_t i = 0; i < len; ++i) { + cs_snprintf(single_byte, sizeof(single_byte), "0x%02" PRIx8 "%s", + bytes[i], i == len - 1 ? "" : ","); + s = str_append(s, single_byte); + if (!s) { + return NULL; + } + } + return s; +} diff --git a/utils.h b/utils.h index 55b2ca255a..3cca580c8f 100644 --- a/utils.h +++ b/utils.h @@ -4,6 +4,7 @@ #ifndef CS_UTILS_H #define CS_UTILS_H +#include #if defined(CAPSTONE_HAS_OSXKERNEL) #include #else @@ -41,9 +42,13 @@ uint16_t readBytes16(MCInst *MI, const uint8_t *Bytes); uint32_t readBytes32(MCInst *MI, const uint8_t *Bytes); void append_to_str_lower(char *str, size_t str_size, const char *src); +void append_to_str(char *str, size_t str_buf_size, const char *src); +char *str_append(char *str_a, const char *str_b); static inline bool strings_match(const char *str0, const char *str1) { return strcmp(str0, str1) == 0; } static inline bool is_blank_char(const char c) { return c == ' ' || c == '\t'; } + +char *byte_seq_to_str(uint8_t *bytes, size_t len); #endif diff --git a/windowsce/COMPILE.md b/windowsce/COMPILE.md index 6ed5abc4cd..2aaceb8c2d 100644 --- a/windowsce/COMPILE.md +++ b/windowsce/COMPILE.md @@ -2,7 +2,7 @@ This documentation explains how to compile Capstone for: - Windows CE 7, a.k.a, [Windows Embedded Compact 7](https://www.microsoft.com/windowsembedded/en-us/windows-embedded-compact-7.aspx), on [ARMv7](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0406c/index.html). - Windows CE 8, a.k.a, [Windows Embedded Compact 2013](https://www.microsoft.com/windowsembedded/en-us/windows-embedded-compact-2013.aspx), on [ARMv7](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0406c/index.html). -To build Capstone for a different platform, please refer to `COMPILE.TXT`. +To build Capstone for a different platform, please refer to `COMPILE_CMAKE.TXT`. # Prerequisites From e6da49d5497f0be1877b576fb2ead74ebedc0d96 Mon Sep 17 00:00:00 2001 From: Giovanni <561184+wargio@users.noreply.github.com> Date: Tue, 3 Sep 2024 09:22:47 +0800 Subject: [PATCH 2/5] Some small fixes for capstone-next (#2460) --- MCInstPrinter.c | 5 +++++ arch/LoongArch/LoongArchModule.h | 6 +++--- include/capstone/aarch64.h | 2 +- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/MCInstPrinter.c b/MCInstPrinter.c index 5dbe7323d1..9671dca9da 100644 --- a/MCInstPrinter.c +++ b/MCInstPrinter.c @@ -8,6 +8,7 @@ extern bool ARM_getFeatureBits(unsigned int mode, unsigned int feature); extern bool PPC_getFeatureBits(unsigned int mode, unsigned int feature); extern bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature); +extern bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature); static bool testFeatureBits(const MCInst *MI, uint32_t Value) { @@ -27,6 +28,10 @@ static bool testFeatureBits(const MCInst *MI, uint32_t Value) #ifdef CAPSTONE_HAS_AARCH64 case CS_ARCH_AARCH64: return AArch64_getFeatureBits(MI->csh->mode, Value); +#endif +#ifdef CAPSTONE_HAS_TRICORE + case CS_ARCH_TRICORE: + return TriCore_getFeatureBits(MI->csh->mode, Value); #endif } } diff --git a/arch/LoongArch/LoongArchModule.h b/arch/LoongArch/LoongArchModule.h index ce0edd7df9..8ffd9ae45b 100644 --- a/arch/LoongArch/LoongArchModule.h +++ b/arch/LoongArch/LoongArchModule.h @@ -2,12 +2,12 @@ /* By Jiajie Chen , 2024 */ /* Yanglin Xun <1109673069@qq.com>, 2024 */ -#ifndef CS_LoongArch_MODULE_H -#define CS_LoongArch_MODULE_H +#ifndef CS_LOONGARCH_MODULE_H +#define CS_LOONGARCH_MODULE_H #include "../../utils.h" cs_err LoongArch_global_init(cs_struct *ud); cs_err LoongArch_option(cs_struct *handle, cs_opt_type type, size_t value); -#endif +#endif // CS_LOONGARCH_MODULE_H diff --git a/include/capstone/aarch64.h b/include/capstone/aarch64.h index e25ca28a82..83fc7faf3e 100644 --- a/include/capstone/aarch64.h +++ b/include/capstone/aarch64.h @@ -80,7 +80,7 @@ typedef enum VectorLayout { // Moved from AArch64BaseInfo.h // The CondCodes constants map directly to the 4-bit encoding of the condition // field for predicated instructions. -typedef enum CondCode { // Meaning (integer) Meaning (floating-point) +typedef enum AArch64CondCode { // Meaning (integer) Meaning (floating-point) AArch64CC_EQ = 0x0, // Equal Equal AArch64CC_NE = 0x1, // Not equal Not equal, or unordered AArch64CC_HS = 0x2, // Unsigned higher or same >, ==, or unordered From 6a7fef60eaa377c048163bf0d5b00199cf402c49 Mon Sep 17 00:00:00 2001 From: Giovanni <561184+wargio@users.noreply.github.com> Date: Sat, 7 Sep 2024 22:30:47 +0800 Subject: [PATCH 3/5] Auto-Sync Mips (#2410) --- .github/workflows/auto-sync.yml | 2 + .gitignore | 2 +- MCInstPrinter.c | 5 + MCRegisterInfo.c | 4 + MCRegisterInfo.h | 2 + Mapping.c | 1 + Mapping.h | 4 + arch/Mips/MipsCP0RegisterMap.h | 190 + arch/Mips/MipsDisassembler.c | 3671 ++- arch/Mips/MipsDisassembler.h | 3 +- arch/Mips/MipsGenAsmWriter.inc | 14955 +++++++--- arch/Mips/MipsGenCSAliasEnum.inc | 119 + arch/Mips/MipsGenCSAliasMnemMap.inc | 119 + arch/Mips/MipsGenCSFeatureEnum.inc | 69 + arch/Mips/MipsGenCSFeatureName.inc | 69 + arch/Mips/MipsGenCSInsnEnum.inc | 1373 + arch/Mips/MipsGenCSMappingInsn.inc | 24465 ++++++++++++++++ arch/Mips/MipsGenCSMappingInsnName.inc | 1373 + arch/Mips/MipsGenCSMappingInsnOp.inc | 18615 ++++++++++++ arch/Mips/MipsGenCSOpGroup.inc | 45 + arch/Mips/MipsGenCSRegEnum.inc | 649 + arch/Mips/MipsGenDisassemblerTables.inc | 17472 +++++++---- arch/Mips/MipsGenInstrInfo.inc | 9263 ++++-- arch/Mips/MipsGenRegisterInfo.inc | 3783 ++- arch/Mips/MipsGenSubtargetInfo.inc | 119 +- arch/Mips/MipsInstPrinter.c | 839 +- arch/Mips/MipsInstPrinter.h | 155 +- arch/Mips/MipsLinkage.h | 21 + arch/Mips/MipsMapping.c | 1398 +- arch/Mips/MipsMapping.h | 57 +- arch/Mips/MipsModule.c | 44 +- arch/Mips/MipsModule.h | 4 +- bindings/java/capstone/Capstone.java | 2 +- bindings/java/capstone/Mips_const.java | 3002 +- bindings/ocaml/mips_const.ml | 3002 +- bindings/python/capstone/__init__.py | 65 +- bindings/python/capstone/mips.py | 4 + bindings/python/capstone/mips_const.py | 3002 +- .../cstest_py/src/cstest_py/cs_modes.py | 4 + cs.c | 29 +- cstool/cstool.c | 589 +- cstool/cstool_mips.c | 2 + docs/cs_v6_release_guide.md | 91 + include/capstone/capstone.h | 39 +- include/capstone/cs_operand.h | 3 +- include/capstone/mips.h | 2400 +- .../Mips/micromips-alu-instructions-EB.s.cs | 4 +- suite/MC/Mips/micromips-alu-instructions.s.cs | 4 +- .../micromips-branch-instructions-EB.s.cs | 20 +- .../Mips/micromips-branch-instructions.s.cs | 20 +- suite/MC/Mips/micromips-expansions.s.cs | 43 +- suite/MC/Mips/mips-alu-instructions.s.cs | 118 +- .../MC/Mips/mips-control-instructions-64.s.cs | 2 +- suite/MC/Mips/mips-control-instructions.s.cs | 2 +- suite/MC/Mips/mips-coprocessor-encodings.s.cs | 32 +- suite/MC/Mips/mips-fpu-instructions.s.cs | 185 +- suite/MC/Mips/mips-memory-instructions.s.cs | 33 +- suite/MC/Mips/mips64-alu-instructions.s.cs | 111 +- suite/MC/Mips/mips64-instructions.s.cs | 5 +- .../Mips/mips64-register-names-n32-n64.s.cs | 33 + suite/MC/Mips/mips_directives.s.cs | 31 +- suite/MC/Mips/nabi-regs.s.cs | 23 +- suite/MC/Mips/test_2r.s.cs | 31 +- suite/MC/Mips/test_2rf.s.cs | 65 +- suite/MC/Mips/test_3r.s.cs | 485 +- suite/MC/Mips/test_3rf.s.cs | 165 +- suite/MC/Mips/test_bit.s.cs | 97 +- suite/MC/Mips/test_cbranch.s.cs | 50 +- suite/MC/Mips/test_ctrlregs.s.cs | 65 +- suite/MC/Mips/test_elm.s.cs | 30 +- suite/MC/Mips/test_elm_insert.s.cs | 7 +- suite/MC/Mips/test_elm_insve.s.cs | 9 +- suite/MC/Mips/test_i10.s.cs | 9 +- suite/MC/Mips/test_i5.s.cs | 89 +- suite/MC/Mips/test_i8.s.cs | 21 +- suite/MC/Mips/test_lsa.s.cs | 9 +- suite/MC/Mips/test_mi10.s.cs | 47 +- suite/MC/Mips/test_vec.s.cs | 15 +- suite/auto-sync/pyproject.toml | 2 +- suite/auto-sync/src/autosync/ASUpdater.py | 2 +- suite/auto-sync/src/autosync/MCUpdater.py | 35 +- .../autosync/cpptranslator/Configurator.py | 6 + .../autosync/cpptranslator/CppTranslator.py | 30 +- .../src/autosync/cpptranslator/Differ.py | 21 +- .../cpptranslator/TemplateCollector.py | 1 - .../Tests/Patches/test_arch_config.json | 25 +- .../autosync/cpptranslator/Tests/test_unit.py | 44 + .../autosync/cpptranslator/arch_config.json | 65 +- .../cpptranslator/patches/AddCSDetail.py | 24 +- .../cpptranslator/patches/FieldFromInstr.py | 35 +- .../cpptranslator/patches/Includes.py | 39 + .../patches/InlineToStaticInline.py | 1 - .../autosync/cpptranslator/patches/Patch.py | 11 - .../autosync/cpptranslator/saved_patches.json | 882 + suite/auto-sync/src/autosync/mcupdater.json | 87 +- suite/cstest/include/test_mapping.h | 20 + suite/cstest/src/test_run.c | 19 +- tests/MC/Mips/invalid-xfail.txt.yaml | 70 + tests/MC/Mips/invalid.txt.yaml | 10 + tests/MC/Mips/mftr-mttr-aliases.s.yaml | 380 + tests/MC/Mips/mftr-mttr-reserved-valid.s.yaml | 40 + .../Mips/micromips-alu-instructions-EB.s.yaml | 68 +- .../MC/Mips/micromips-alu-instructions.s.yaml | 68 +- .../micromips-branch-instructions-EB.s.yaml | 36 +- .../Mips/micromips-branch-instructions.s.yaml | 18 +- .../micromips-jump-instructions-EB.s.yaml | 6 +- ...micromips-loadstore-instructions-EB.s.yaml | 16 +- .../micromips-loadstore-unaligned-EB.s.yaml | 8 +- .../micromips-movcond-instructions-EB.s.yaml | 8 +- .../micromips-multiply-instructions-EB.s.yaml | 8 +- .../micromips-shift-instructions-EB.s.yaml | 16 +- .../micromips-trap-instructions-EB.s.yaml | 12 +- tests/MC/Mips/mips-alu-instructions.s.yaml | 104 +- .../Mips/mips-control-instructions-64.s.yaml | 62 +- .../MC/Mips/mips-control-instructions.s.yaml | 62 +- .../MC/Mips/mips-coprocessor-encodings.s.yaml | 32 +- tests/MC/Mips/mips-fpu-instructions.s.yaml | 200 +- tests/MC/Mips/mips-memory-instructions.s.yaml | 4 +- tests/MC/Mips/mips64-alu-instructions.s.yaml | 90 +- tests/MC/Mips/test_2r.txt.yaml | 150 + tests/MC/Mips/test_2r_msa64.txt.yaml | 10 + tests/MC/Mips/test_2rf.txt.yaml | 320 + tests/MC/Mips/test_3r.txt.yaml | 2420 ++ tests/MC/Mips/test_3rf.txt.yaml | 820 + tests/MC/Mips/test_bit.txt.yaml | 480 + tests/MC/Mips/test_ctrlregs.txt.yaml | 160 + tests/MC/Mips/test_dlsa.txt.yaml | 40 + tests/MC/Mips/test_elm.s.yaml | 2 +- tests/MC/Mips/test_elm.txt.yaml | 140 + tests/MC/Mips/test_elm_insert.txt.yaml | 30 + tests/MC/Mips/test_elm_insert_msa64.txt.yaml | 10 + tests/MC/Mips/test_elm_insve.txt.yaml | 40 + tests/MC/Mips/test_elm_msa64.txt.yaml | 10 + tests/MC/Mips/test_i10.txt.yaml | 40 + tests/MC/Mips/test_i5.txt.yaml | 440 + tests/MC/Mips/test_i8.txt.yaml | 100 + tests/MC/Mips/test_lsa.txt.yaml | 40 + tests/MC/Mips/test_mi10.s.yaml | 6 +- tests/MC/Mips/test_mi10.txt.yaml | 230 + tests/MC/Mips/test_vec.txt.yaml | 70 + tests/MC/Mips/valid-32-el.txt.yaml | 160 + tests/MC/Mips/valid-32.txt.yaml | 160 + tests/MC/Mips/valid-32r6-el.txt.yaml | 60 + tests/MC/Mips/valid-32r6.txt.yaml | 60 + tests/MC/Mips/valid-64-el.txt.yaml | 40 + tests/MC/Mips/valid-64.txt.yaml | 40 + tests/MC/Mips/valid-64r6-el.txt.yaml | 80 + tests/MC/Mips/valid-64r6.txt.yaml | 80 + tests/MC/Mips/valid-el.txt.yaml | 280 + tests/MC/Mips/valid-fp64-el.txt.yaml | 260 + tests/MC/Mips/valid-fp64.txt.yaml | 260 + tests/MC/Mips/valid-micromips-el.txt.yaml | 160 + tests/MC/Mips/valid-micromips.txt.yaml | 160 + tests/MC/Mips/valid-micromips32r3.txt.yaml | 10 + tests/MC/Mips/valid-mips1-el.txt.yaml | 1060 + tests/MC/Mips/valid-mips1.txt.yaml | 1090 + tests/MC/Mips/valid-mips2-el.txt.yaml | 1550 + tests/MC/Mips/valid-mips2.txt.yaml | 1760 ++ tests/MC/Mips/valid-mips3-el.txt.yaml | 1960 ++ tests/MC/Mips/valid-mips3.txt.yaml | 2210 ++ tests/MC/Mips/valid-mips32-el.txt.yaml | 1560 + tests/MC/Mips/valid-mips32.txt.yaml | 3270 +++ tests/MC/Mips/valid-mips32r2-el.txt.yaml | 5250 ++++ tests/MC/Mips/valid-mips32r2.txt.yaml | 10830 +++++++ tests/MC/Mips/valid-mips32r3-el.txt.yaml | 3460 +++ tests/MC/Mips/valid-mips32r3.txt.yaml | 7220 +++++ tests/MC/Mips/valid-mips32r5-el.txt.yaml | 3460 +++ tests/MC/Mips/valid-mips32r5.txt.yaml | 7240 +++++ tests/MC/Mips/valid-mips32r6-el.txt.yaml | 1730 ++ tests/MC/Mips/valid-mips32r6.txt.yaml | 1780 ++ tests/MC/Mips/valid-mips4-el.txt.yaml | 2200 ++ tests/MC/Mips/valid-mips4.txt.yaml | 2490 ++ tests/MC/Mips/valid-mips64-el.txt.yaml | 2420 ++ tests/MC/Mips/valid-mips64-xfail.txt.yaml | 150 + tests/MC/Mips/valid-mips64.txt.yaml | 4350 +++ tests/MC/Mips/valid-mips64r2-el.txt.yaml | 5360 ++++ tests/MC/Mips/valid-mips64r2.txt.yaml | 9440 ++++++ tests/MC/Mips/valid-mips64r3-el.txt.yaml | 2380 ++ tests/MC/Mips/valid-mips64r3.txt.yaml | 4740 +++ tests/MC/Mips/valid-mips64r5-el.txt.yaml | 2380 ++ tests/MC/Mips/valid-mips64r5.txt.yaml | 4750 +++ tests/MC/Mips/valid-mips64r6-el.txt.yaml | 1950 ++ tests/MC/Mips/valid-mips64r6.txt.yaml | 2040 ++ tests/MC/Mips/valid-r2-el.txt.yaml | 310 + tests/MC/Mips/valid-r2.txt.yaml | 310 + tests/MC/Mips/valid-xfail-mips32.txt.yaml | 150 + tests/MC/Mips/valid-xfail-mips32r2.txt.yaml | 160 + tests/MC/Mips/valid-xfail-mips32r3.txt.yaml | 160 + tests/MC/Mips/valid-xfail-mips32r5.txt.yaml | 160 + tests/MC/Mips/valid-xfail-mips32r6.txt.yaml | 100 + tests/MC/Mips/valid-xfail-mips64r2.txt.yaml | 390 + tests/MC/Mips/valid-xfail-mips64r3.txt.yaml | 390 + tests/MC/Mips/valid-xfail-mips64r5.txt.yaml | 390 + tests/MC/Mips/valid-xfail-mips64r6.txt.yaml | 150 + tests/MC/Mips/valid-xfail.txt.yaml | 120 + tests/MC/Mips/valid.s.yaml | 310 + tests/MC/Mips/valid.txt.yaml | 280 + tests/MC/Mips/valid_R6-eva.txt.yaml | 700 + tests/MC/Mips/valid_preR6-eva.txt.yaml | 2820 ++ tests/details/cs_common_details.yaml | 38 +- tests/details/mips.yaml | 71 +- tests/issues/issues.yaml | 142 + 202 files changed, 209201 insertions(+), 21049 deletions(-) create mode 100644 arch/Mips/MipsCP0RegisterMap.h create mode 100644 arch/Mips/MipsGenCSAliasEnum.inc create mode 100644 arch/Mips/MipsGenCSAliasMnemMap.inc create mode 100644 arch/Mips/MipsGenCSFeatureEnum.inc create mode 100644 arch/Mips/MipsGenCSFeatureName.inc create mode 100644 arch/Mips/MipsGenCSInsnEnum.inc create mode 100644 arch/Mips/MipsGenCSMappingInsn.inc create mode 100644 arch/Mips/MipsGenCSMappingInsnName.inc create mode 100644 arch/Mips/MipsGenCSMappingInsnOp.inc create mode 100644 arch/Mips/MipsGenCSOpGroup.inc create mode 100644 arch/Mips/MipsGenCSRegEnum.inc create mode 100644 arch/Mips/MipsLinkage.h create mode 100644 suite/MC/Mips/mips64-register-names-n32-n64.s.cs create mode 100644 suite/auto-sync/src/autosync/cpptranslator/Tests/test_unit.py create mode 100644 tests/MC/Mips/invalid-xfail.txt.yaml create mode 100644 tests/MC/Mips/invalid.txt.yaml create mode 100644 tests/MC/Mips/mftr-mttr-aliases.s.yaml create mode 100644 tests/MC/Mips/mftr-mttr-reserved-valid.s.yaml create mode 100644 tests/MC/Mips/test_2r.txt.yaml create mode 100644 tests/MC/Mips/test_2r_msa64.txt.yaml create mode 100644 tests/MC/Mips/test_2rf.txt.yaml create mode 100644 tests/MC/Mips/test_3r.txt.yaml create mode 100644 tests/MC/Mips/test_3rf.txt.yaml create mode 100644 tests/MC/Mips/test_bit.txt.yaml create mode 100644 tests/MC/Mips/test_ctrlregs.txt.yaml create mode 100644 tests/MC/Mips/test_dlsa.txt.yaml create mode 100644 tests/MC/Mips/test_elm.txt.yaml create mode 100644 tests/MC/Mips/test_elm_insert.txt.yaml create mode 100644 tests/MC/Mips/test_elm_insert_msa64.txt.yaml create mode 100644 tests/MC/Mips/test_elm_insve.txt.yaml create mode 100644 tests/MC/Mips/test_elm_msa64.txt.yaml create mode 100644 tests/MC/Mips/test_i10.txt.yaml create mode 100644 tests/MC/Mips/test_i5.txt.yaml create mode 100644 tests/MC/Mips/test_i8.txt.yaml create mode 100644 tests/MC/Mips/test_lsa.txt.yaml create mode 100644 tests/MC/Mips/test_mi10.txt.yaml create mode 100644 tests/MC/Mips/test_vec.txt.yaml create mode 100644 tests/MC/Mips/valid-32-el.txt.yaml create mode 100644 tests/MC/Mips/valid-32.txt.yaml create mode 100644 tests/MC/Mips/valid-32r6-el.txt.yaml create mode 100644 tests/MC/Mips/valid-32r6.txt.yaml create mode 100644 tests/MC/Mips/valid-64-el.txt.yaml create mode 100644 tests/MC/Mips/valid-64.txt.yaml create mode 100644 tests/MC/Mips/valid-64r6-el.txt.yaml create mode 100644 tests/MC/Mips/valid-64r6.txt.yaml create mode 100644 tests/MC/Mips/valid-el.txt.yaml create mode 100644 tests/MC/Mips/valid-fp64-el.txt.yaml create mode 100644 tests/MC/Mips/valid-fp64.txt.yaml create mode 100644 tests/MC/Mips/valid-micromips-el.txt.yaml create mode 100644 tests/MC/Mips/valid-micromips.txt.yaml create mode 100644 tests/MC/Mips/valid-micromips32r3.txt.yaml create mode 100644 tests/MC/Mips/valid-mips1-el.txt.yaml create mode 100644 tests/MC/Mips/valid-mips1.txt.yaml create mode 100644 tests/MC/Mips/valid-mips2-el.txt.yaml create mode 100644 tests/MC/Mips/valid-mips2.txt.yaml create mode 100644 tests/MC/Mips/valid-mips3-el.txt.yaml create mode 100644 tests/MC/Mips/valid-mips3.txt.yaml create mode 100644 tests/MC/Mips/valid-mips32-el.txt.yaml create mode 100644 tests/MC/Mips/valid-mips32.txt.yaml create mode 100644 tests/MC/Mips/valid-mips32r2-el.txt.yaml create mode 100644 tests/MC/Mips/valid-mips32r2.txt.yaml create mode 100644 tests/MC/Mips/valid-mips32r3-el.txt.yaml create mode 100644 tests/MC/Mips/valid-mips32r3.txt.yaml create mode 100644 tests/MC/Mips/valid-mips32r5-el.txt.yaml create mode 100644 tests/MC/Mips/valid-mips32r5.txt.yaml create mode 100644 tests/MC/Mips/valid-mips32r6-el.txt.yaml create mode 100644 tests/MC/Mips/valid-mips32r6.txt.yaml create mode 100644 tests/MC/Mips/valid-mips4-el.txt.yaml create mode 100644 tests/MC/Mips/valid-mips4.txt.yaml create mode 100644 tests/MC/Mips/valid-mips64-el.txt.yaml create mode 100644 tests/MC/Mips/valid-mips64-xfail.txt.yaml create mode 100644 tests/MC/Mips/valid-mips64.txt.yaml create mode 100644 tests/MC/Mips/valid-mips64r2-el.txt.yaml create mode 100644 tests/MC/Mips/valid-mips64r2.txt.yaml create mode 100644 tests/MC/Mips/valid-mips64r3-el.txt.yaml create mode 100644 tests/MC/Mips/valid-mips64r3.txt.yaml create mode 100644 tests/MC/Mips/valid-mips64r5-el.txt.yaml create mode 100644 tests/MC/Mips/valid-mips64r5.txt.yaml create mode 100644 tests/MC/Mips/valid-mips64r6-el.txt.yaml create mode 100644 tests/MC/Mips/valid-mips64r6.txt.yaml create mode 100644 tests/MC/Mips/valid-r2-el.txt.yaml create mode 100644 tests/MC/Mips/valid-r2.txt.yaml create mode 100644 tests/MC/Mips/valid-xfail-mips32.txt.yaml create mode 100644 tests/MC/Mips/valid-xfail-mips32r2.txt.yaml create mode 100644 tests/MC/Mips/valid-xfail-mips32r3.txt.yaml create mode 100644 tests/MC/Mips/valid-xfail-mips32r5.txt.yaml create mode 100644 tests/MC/Mips/valid-xfail-mips32r6.txt.yaml create mode 100644 tests/MC/Mips/valid-xfail-mips64r2.txt.yaml create mode 100644 tests/MC/Mips/valid-xfail-mips64r3.txt.yaml create mode 100644 tests/MC/Mips/valid-xfail-mips64r5.txt.yaml create mode 100644 tests/MC/Mips/valid-xfail-mips64r6.txt.yaml create mode 100644 tests/MC/Mips/valid-xfail.txt.yaml create mode 100644 tests/MC/Mips/valid.s.yaml create mode 100644 tests/MC/Mips/valid.txt.yaml create mode 100644 tests/MC/Mips/valid_R6-eva.txt.yaml create mode 100644 tests/MC/Mips/valid_preR6-eva.txt.yaml diff --git a/.github/workflows/auto-sync.yml b/.github/workflows/auto-sync.yml index d22729333e..d1428d0655 100644 --- a/.github/workflows/auto-sync.yml +++ b/.github/workflows/auto-sync.yml @@ -77,6 +77,7 @@ jobs: ./src/autosync/ASUpdater.py -d -a ARM -s IncGen ./src/autosync/ASUpdater.py -d -a PPC -s IncGen ./src/autosync/ASUpdater.py -d -a LoongArch -s IncGen + ./src/autosync/ASUpdater.py -d -a Mips -s IncGen - name: CppTranslator - Patch tests run: | @@ -92,6 +93,7 @@ jobs: ./src/autosync/ASUpdater.py --ci -d -a ARM -s Translate ./src/autosync/ASUpdater.py --ci -d -a PPC -s Translate ./src/autosync/ASUpdater.py --ci -d -a LoongArch -s Translate + ./src/autosync/ASUpdater.py --ci -d -a Mips -s Translate - name: Differ - Test save file is up-to-date run: | diff --git a/.gitignore b/.gitignore index 698c6d154f..2e28a30614 100644 --- a/.gitignore +++ b/.gitignore @@ -143,7 +143,7 @@ cstool/cstool android-ndk-* # python virtual env -.venv/ +.ven*/ # Auto-sync files suite/auto-sync/src/autosync.egg-info diff --git a/MCInstPrinter.c b/MCInstPrinter.c index 9671dca9da..4e509c6eee 100644 --- a/MCInstPrinter.c +++ b/MCInstPrinter.c @@ -7,6 +7,7 @@ extern bool ARM_getFeatureBits(unsigned int mode, unsigned int feature); extern bool PPC_getFeatureBits(unsigned int mode, unsigned int feature); +extern bool Mips_getFeatureBits(unsigned int mode, unsigned int feature); extern bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature); extern bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature); @@ -25,6 +26,10 @@ static bool testFeatureBits(const MCInst *MI, uint32_t Value) case CS_ARCH_PPC: return PPC_getFeatureBits(MI->csh->mode, Value); #endif +#ifdef CAPSTONE_HAS_MIPS + case CS_ARCH_MIPS: + return Mips_getFeatureBits(MI->csh->mode, Value); +#endif #ifdef CAPSTONE_HAS_AARCH64 case CS_ARCH_AARCH64: return AArch64_getFeatureBits(MI->csh->mode, Value); diff --git a/MCRegisterInfo.c b/MCRegisterInfo.c index ce9a237a47..e8007fae67 100644 --- a/MCRegisterInfo.c +++ b/MCRegisterInfo.c @@ -149,3 +149,7 @@ bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg) return (c->RegSet[Byte] & (1 << InByte)) != 0; } + +unsigned MCRegisterClass_getRegister(const MCRegisterClass *c, unsigned RegNo) { + return c->RegsBegin[RegNo]; +} diff --git a/MCRegisterInfo.h b/MCRegisterInfo.h index 471a04a9dd..8432e5e2c5 100644 --- a/MCRegisterInfo.h +++ b/MCRegisterInfo.h @@ -113,4 +113,6 @@ const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsi bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg); +unsigned MCRegisterClass_getRegister(const MCRegisterClass *c, unsigned i); + #endif diff --git a/Mapping.c b/Mapping.c index c4f352185e..2548f1cc47 100644 --- a/Mapping.c +++ b/Mapping.c @@ -338,6 +338,7 @@ DEFINE_get_detail_op(aarch64, AArch64); DEFINE_get_detail_op(alpha, Alpha); DEFINE_get_detail_op(hppa, HPPA); DEFINE_get_detail_op(loongarch, LoongArch); +DEFINE_get_detail_op(mips, Mips); DEFINE_get_detail_op(riscv, RISCV); /// Returns true if for this architecture the diff --git a/Mapping.h b/Mapping.h index a2f60cabfe..7bbcfec003 100644 --- a/Mapping.h +++ b/Mapping.h @@ -138,6 +138,7 @@ DECL_get_detail_op(aarch64, AArch64); DECL_get_detail_op(alpha, Alpha); DECL_get_detail_op(hppa, HPPA); DECL_get_detail_op(loongarch, LoongArch); +DECL_get_detail_op(mips, Mips); DECL_get_detail_op(riscv, RISCV); /// Increments the detail->arch.op_count by one. @@ -168,6 +169,8 @@ DEFINE_inc_detail_op_count(hppa, HPPA); DEFINE_dec_detail_op_count(hppa, HPPA); DEFINE_inc_detail_op_count(loongarch, LoongArch); DEFINE_dec_detail_op_count(loongarch, LoongArch); +DEFINE_inc_detail_op_count(mips, Mips); +DEFINE_dec_detail_op_count(mips, Mips); DEFINE_inc_detail_op_count(riscv, RISCV); DEFINE_dec_detail_op_count(riscv, RISCV); @@ -198,6 +201,7 @@ DEFINE_get_arch_detail(aarch64, AArch64); DEFINE_get_arch_detail(alpha, Alpha); DEFINE_get_arch_detail(hppa, HPPA); DEFINE_get_arch_detail(loongarch, LoongArch); +DEFINE_get_arch_detail(mips, Mips); DEFINE_get_arch_detail(riscv, RISCV); static inline bool detail_is_set(const MCInst *MI) diff --git a/arch/Mips/MipsCP0RegisterMap.h b/arch/Mips/MipsCP0RegisterMap.h new file mode 100644 index 0000000000..83951094f5 --- /dev/null +++ b/arch/Mips/MipsCP0RegisterMap.h @@ -0,0 +1,190 @@ +//===- MipsCP0RegisterMap.h - Co-processor register names for Mips/nanoMIPS -===// +// This has been created by hand. + +#ifndef LLVM_LIB_TARGET_MIPS_NANOMIPSCP0REGMAP_H +#define LLVM_LIB_TARGET_MIPS_NANOMIPSCP0REGMAP_H + +struct CP0SelRegister_t { + const char *Name; + int RegNum; + int Select; + int Index; +}; + +static const struct CP0SelRegister_t CP0SelRegs[] = { + {"index", 0, 0}, + {"mvpcontrol", 0, 1}, + {"mvpconf0", 0, 2}, + {"mvpconf1", 0, 3}, + {"vpcontrol", 0, 4}, + {"random", 1, 0}, + {"vpecontrol", 1, 1}, + {"vpeconf0", 1, 2}, + {"vpeconf1", 1, 3}, + {"yqmask", 1, 4}, + {"vpeschedule", 1, 5}, + {"vpeschefback", 1, 6}, + {"vpeopt", 1, 7}, + {"entrylo0", 2, 0}, + {"tcstatus", 2, 1}, + {"tcbind", 2, 2}, + {"tcrestart", 2, 3}, + {"tchalt", 2, 4}, + {"tccontext", 2, 5}, + {"tcschedule", 2, 6}, + {"tcschefback", 2, 7}, + {"entrylo1", 3, 0}, + {"globalnumber", 3, 1}, + {"tcopt", 3, 7}, + {"context", 4, 0}, + {"contextconfig", 4, 1}, + {"userlocal", 4, 2}, + {"xcontextconfig", 4, 3}, + {"debugcontextid", 4, 4}, + {"memorymapid", 4, 5}, + {"pagemask", 5, 0}, + {"pagegrain", 5, 1}, + {"segctl0", 5, 2}, + {"segctl1", 5, 3}, + {"segctl2", 5, 4}, + {"pwbase", 5, 5}, + {"pwfield", 5, 6}, + {"pwsize", 5, 7}, + {"wired", 6, 0}, + {"srsconf0", 6, 1}, + {"srsconf1", 6, 2}, + {"srsconf2", 6, 3}, + {"srsconf3", 6, 4}, + {"srsconf4", 6, 5}, + {"pwctl", 6, 6}, + {"hwrena", 7, 0}, + {"badvaddr", 8, 0}, + {"badinst", 8, 1}, + {"badinstrp", 8, 2}, + {"badinstrx", 8, 3}, + {"count", 9, 0}, + {"entryhi", 10, 0}, + {"guestctl1", 10, 4}, + {"guestctl2", 10, 5}, + {"guestctl3", 10, 6}, + {"compare", 11, 0}, + {"guestctl0ext", 11, 4}, + {"status", 12, 0}, + {"intctl", 12, 1}, + {"srsctl", 12, 2}, + {"srsmap", 12, 3}, + {"view_ipl", 12, 4}, + {"srsmap2", 12, 5}, + {"guestctl0", 12, 6}, + {"gtoffset", 12, 7}, + {"cause", 13, 0}, + {"view_ripl", 13, 4}, + {"nestedexc", 13, 5}, + {"epc", 14, 0}, + {"nestedepc", 14, 2}, + {"prid", 15, 0}, + {"ebase", 15, 1}, + {"cdmmbase", 15, 2}, + {"cmgcrbase", 15, 3}, + {"bevva", 15, 4}, + {"config", 16, 0}, + {"config1", 16, 1}, + {"config2", 16, 2}, + {"config3", 16, 3}, + {"config4", 16, 4}, + {"config5", 16, 5}, + {"lladdr", 17, 0}, + {"maar", 17, 1}, + {"maari", 17, 2}, + {"watchlo0", 18, 0}, + {"watchlo1", 18, 1}, + {"watchlo2", 18, 2}, + {"watchlo3", 18, 3}, + {"watchlo4", 18, 4}, + {"watchlo5", 18, 5}, + {"watchlo6", 18, 6}, + {"watchlo7", 18, 7}, + {"watchlo8", 18, 8}, + {"watchlo9", 18, 9}, + {"watchlo10", 18,10}, + {"watchlo11", 18,11}, + {"watchlo12", 18,12}, + {"watchlo13", 18,13}, + {"watchlo14", 18,14}, + {"watchlo15", 18,15}, + {"watchhi0", 19, 0}, + {"watchhi1", 19, 1}, + {"watchhi2", 19, 2}, + {"watchhi3", 19, 3}, + {"watchhi4", 19, 4}, + {"watchhi5", 19, 5}, + {"watchhi6", 19, 6}, + {"watchhi7", 19, 7}, + {"watchhi8", 19, 8}, + {"watchhi9", 19, 9}, + {"watchhi10", 19,10}, + {"watchhi11", 19,11}, + {"watchhi12", 19,12}, + {"watchhi13", 19,13}, + {"watchhi14", 19,14}, + {"watchhi15", 19,15}, + {"xcontext", 20, 0}, + {"debug", 23, 0}, + {"tracecontrol", 23, 1}, + {"tracecontrol2", 23, 2}, + {"usertracedata1", 23, 3}, + {"traceibpc", 23, 4}, + {"tracedbpc", 23, 5}, + {"debug2", 23, 6}, + {"depc", 24, 0}, + {"tracecontrol3", 24, 2}, + {"usertracedata2", 24, 3}, + {"perfctl0", 25, 0}, + {"perfcnt0", 25, 1}, + {"perfctl1", 25, 2}, + {"perfcnt1", 25, 3}, + {"perfctl2", 25, 4}, + {"perfcnt2", 25, 5}, + {"perfctl3", 25, 6}, + {"perfcnt3", 25, 7}, + {"perfctl4", 25, 8}, + {"perfcnt4", 25, 9}, + {"perfctl5", 25,10}, + {"perfcnt5", 25,11}, + {"perfctl6", 25,12}, + {"perfcnt6", 25,13}, + {"perfctl7", 25,14}, + {"perfcnt7", 25,15}, + {"errctl", 26, 0}, + {"cacheerr", 27, 0}, + {"itaglo", 28, 0}, + {"idatalo", 28, 1}, + {"dtaglo", 28, 2}, + {"ddatalo", 28, 3}, + {"itaghi", 29, 0}, + {"idatahi", 29, 1}, + {"dtaghi", 29, 2}, + {"ddatahi", 29, 3}, + {"errorepc", 30, 0}, + {"desave", 31, 0}, + {"kscratch1", 31, 2}, + {"kscratch2", 31, 3}, + {"kscratch3", 31, 4}, + {"kscratch4", 31, 5}, + {"kscratch5", 31, 6}, + {"kscratch6", 31, 7} +}; + +inline static int COP0Map_getEncIndexMap(int RegNo) +{ + int i; + for (i = 0; i < (sizeof(CP0SelRegs) / sizeof(CP0SelRegs[0])); ++i) { + unsigned RegEnc = (CP0SelRegs[i].RegNum << 5) | CP0SelRegs[i].Select; + if (RegEnc == RegNo) { + return i; + } + } + return -1; +} + +#endif // LLVM_LIB_TARGET_MIPS_NANOMIPSCP0REGMAP_H diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c index c5c6b5c97b..7196de3dbe 100644 --- a/arch/Mips/MipsDisassembler.c +++ b/arch/Mips/MipsDisassembler.c @@ -1,9 +1,22 @@ -//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically translated source file from LLVM. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Only small edits allowed. */ +/* For multiple similar edits, please create a Patch for the translator. */ + +/* Capstone's C++ file translator: */ +/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ + +//===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// // -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -11,527 +24,778 @@ // //===----------------------------------------------------------------------===// -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ - -#ifdef CAPSTONE_HAS_MIPS - #include #include +#include +#include -#include "capstone/platform.h" +#include "../../MCInst.h" +#include "../../MathExtras.h" +#include "../../MCInstPrinter.h" +#include "../../MCDisassembler.h" +#include "../../MCRegisterInfo.h" +#include "../../MCFixedLenDisassembler.h" +#include "../../cs_priv.h" +#include "../../utils.h" +#define GET_SUBTARGETINFO_ENUM +#include "MipsGenSubtargetInfo.inc" -#include "MipsDisassembler.h" +#define GET_INSTRINFO_ENUM +#include "MipsGenInstrInfo.inc" -#include "../../utils.h" +#define GET_REGINFO_ENUM +#include "MipsGenRegisterInfo.inc" -#include "../../MCRegisterInfo.h" -#include "../../SStream.h" +#define CONCAT(a, b) CONCAT_(a, b) +#define CONCAT_(a, b) a##_##b + +#define DEBUG_TYPE "mips-disassembler" + +bool Mips_getFeatureBits(unsigned int mode, unsigned int feature) +{ + switch(feature) { + case Mips_FeatureGP64Bit: + return mode & (CS_MODE_MIPS3 | CS_MODE_MIPS4 | + CS_MODE_MIPS5 | CS_MODE_MIPS64 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureFP64Bit: + return mode & (CS_MODE_MIPS32R6 | CS_MODE_MIPS3 | + CS_MODE_MIPS4 | CS_MODE_MIPS5 | + CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | + CS_MODE_MIPS32R5 | CS_MODE_MIPS64 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureNaN2008: + return mode & (CS_MODE_MIPS32R6 | CS_MODE_MIPS64R6); + case Mips_FeatureAbs2008: + return mode & (CS_MODE_MIPS32R6 | CS_MODE_MIPS64R6); + case Mips_FeatureMips1: + return mode & (CS_MODE_MIPS1 | CS_MODE_MIPS2 | + CS_MODE_MIPS32 | CS_MODE_MIPS32R2 | + CS_MODE_MIPS32R3 | CS_MODE_MIPS32R5 | + CS_MODE_MIPS32R6 | CS_MODE_MIPS3 | + CS_MODE_MIPS4 | CS_MODE_MIPS5 | + CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | + CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | + CS_MODE_MIPS64R6 | CS_MODE_OCTEON | + CS_MODE_OCTEONP); + case Mips_FeatureMips2: + return mode & (CS_MODE_MIPS2 | CS_MODE_MIPS32 | + CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | + CS_MODE_MIPS32R5 | CS_MODE_MIPS32R6 | + CS_MODE_MIPS3 | CS_MODE_MIPS4 | + CS_MODE_MIPS5 | CS_MODE_MIPS64 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureMips3_32: + return mode & (CS_MODE_MIPS32 | CS_MODE_MIPS32R2 | + CS_MODE_MIPS32R3 | CS_MODE_MIPS32R5 | + CS_MODE_MIPS32R6 | CS_MODE_MIPS3 | + CS_MODE_MIPS4 | CS_MODE_MIPS5 | + CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | + CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | + CS_MODE_MIPS64R6 | CS_MODE_OCTEON | + CS_MODE_OCTEONP); + case Mips_FeatureMips3_32r2: + return mode & (CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | + CS_MODE_MIPS32R5 | CS_MODE_MIPS32R6 | + CS_MODE_MIPS3 | CS_MODE_MIPS4 | + CS_MODE_MIPS5 | CS_MODE_MIPS64 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureMips3: + return mode & (CS_MODE_MIPS3 | CS_MODE_MIPS4 | + CS_MODE_MIPS5 | CS_MODE_MIPS64 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureMips4_32: + return mode & (CS_MODE_MIPS32 | CS_MODE_MIPS32R2 | + CS_MODE_MIPS32R3 | CS_MODE_MIPS32R5 | + CS_MODE_MIPS32R6 | CS_MODE_MIPS4 | + CS_MODE_MIPS5 | CS_MODE_MIPS64 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureMips4_32r2: + return mode & (CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | + CS_MODE_MIPS32R5 | CS_MODE_MIPS32R6 | + CS_MODE_MIPS4 | CS_MODE_MIPS5 | + CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | + CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | + CS_MODE_MIPS64R6 | CS_MODE_OCTEON | + CS_MODE_OCTEONP); + case Mips_FeatureMips4: + return mode & (CS_MODE_MIPS4 | CS_MODE_MIPS5 | + CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | + CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | + CS_MODE_MIPS64R6 | CS_MODE_OCTEON | + CS_MODE_OCTEONP); + case Mips_FeatureMips5_32r2: + return mode & (CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | + CS_MODE_MIPS32R5 | CS_MODE_MIPS32R6 | + CS_MODE_MIPS5 | CS_MODE_MIPS64 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureMips5: + return mode & (CS_MODE_MIPS5 | CS_MODE_MIPS64 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureMips32: + return mode & (CS_MODE_MIPS32 | CS_MODE_MIPS32R2 | + CS_MODE_MIPS32R3 | CS_MODE_MIPS32R5 | + CS_MODE_MIPS32R6 | CS_MODE_MIPS64 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureMips32r2: + return mode & (CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | + CS_MODE_MIPS32R5 | CS_MODE_MIPS32R6 | + CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureMips32r3: + return mode & (CS_MODE_MIPS32R3 | CS_MODE_MIPS32R5 | + CS_MODE_MIPS32R6 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6); + case Mips_FeatureMips32r5: + return mode & (CS_MODE_MIPS32R5 | CS_MODE_MIPS32R6 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6); + case Mips_FeatureMips32r6: + return mode & (CS_MODE_MIPS32R6 | CS_MODE_MIPS64R6); + case Mips_FeatureMips64: + return mode & (CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | + CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | + CS_MODE_MIPS64R6 | CS_MODE_OCTEON | + CS_MODE_OCTEONP); + case Mips_FeatureMips64r2: + return mode & (CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | + CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | + CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureMips64r3: + return mode & (CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | + CS_MODE_MIPS64R6); + case Mips_FeatureMips64r5: + return mode & (CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6); + case Mips_FeatureMips64r6: + return mode & CS_MODE_MIPS64R6; + case Mips_FeatureMips16: + return mode & CS_MODE_MIPS16; + case Mips_FeatureMicroMips: + return mode & CS_MODE_MICRO; + case Mips_FeatureNanoMips: + return mode & (CS_MODE_NANOMIPS | CS_MODE_NMS1 | + CS_MODE_I7200); + case Mips_FeatureNMS1: + return mode & CS_MODE_NMS1; + case Mips_FeatureTLB: + return mode & CS_MODE_I7200; + case Mips_FeatureCnMips: + return mode & (CS_MODE_OCTEON | CS_MODE_OCTEONP); + case Mips_FeatureCnMipsP: + return mode & CS_MODE_OCTEONP; + case Mips_FeaturePTR64Bit: + return mode & CS_MODE_MIPS_PTR64; + case Mips_FeatureSoftFloat: + return mode & CS_MODE_MIPS_NOFLOAT; + case Mips_FeatureI7200: + return mode & CS_MODE_I7200; + // optional features always enabled + case Mips_FeatureDSP: // Mips DSP ASE + return true; + case Mips_FeatureDSPR2: // Mips DSP-R2 ASE + return true; + case Mips_FeatureDSPR3: // Mips DSP-R3 ASE + return true; + case Mips_FeatureMips3D: // Mips 3D ASE + return true; + case Mips_FeatureMSA: // Mips MSA ASE + return true; + case Mips_FeatureEVA: { // Mips EVA ASE + if (mode & CS_MODE_NANOMIPS) { + return mode & CS_MODE_I7200; + } + return true; + } + case Mips_FeatureCRC: // Mips R6 CRC ASE + return true; + case Mips_FeatureVirt: // Mips Virtualization ASE + return true; + case Mips_FeatureGINV: // Mips Global Invalidate ASE + return true; + case Mips_FeatureMT: { // Mips MT ASE + if (mode & CS_MODE_NANOMIPS) { + return mode & CS_MODE_I7200; + } + return true; + } + case Mips_FeatureUseIndirectJumpsHazard: + return true; + default: + return false; + } +} -#include "../../MathExtras.h" +static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t *Bytes, + size_t BytesLen, uint64_t Address, SStream *CStream); -//#include "Mips.h" -//#include "MipsRegisterInfo.h" -//#include "MipsSubtarget.h" -#include "../../MCFixedLenDisassembler.h" -#include "../../MCInst.h" -//#include "llvm/MC/MCSubtargetInfo.h" -#include "../../MCRegisterInfo.h" -#include "../../MCDisassembler.h" +// end anonymous namespace // Forward declare these because the autogenerated code will reference them. // Definitions are further down. -static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); +static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); +static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); + unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeGPRNM3RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeGPRNM4RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeGPRNMRARegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeGPRNM3ZRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeGPRNM4ZRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeGPRNM32NZRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeGPRNM32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeGPRNM2R1RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeGPRNM1R1RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeBranchTarget(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeJumpTarget(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeBranchTarget21(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBranchTarget26(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); - -// DecodeBranchTarget7MM - Decode microMIPS branch offset, which is -// shifted left by 1 bit. -static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, - unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); +static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is -// shifted left by 1 bit. -static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, - unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); +static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -// DecodeBranchTargetMM - Decode microMIPS branch offset, which is -// shifted left by 1 bit. -static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -// DecodeJumpTargetMM - Decode microMIPS jump target, which is -// shifted left by 1 bit. -static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeMem(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeCacheOp(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); +static DecodeStatus DecodeCOP0RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeCacheOpR6(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); +static DecodeStatus DecodeCOP0SelRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeCacheOpMM(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); +static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeSyncI(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); +static DecodeStatus DecodeBranchTarget(MCInst *Inst, unsigned Offset, + uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMSA128Mem(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeBranchTarget1SImm16(MCInst *Inst, unsigned Offset, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeMemMMImm4(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); +static DecodeStatus DecodeJumpTarget(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); +static DecodeStatus DecodeBranchTarget21(MCInst *Inst, unsigned Offset, + uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); +static DecodeStatus DecodeBranchTarget21MM(MCInst *Inst, unsigned Offset, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); +static DecodeStatus DecodeBranchTarget26(MCInst *Inst, unsigned Offset, + uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMemMMImm12(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMemMMImm16(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn, - uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder); +// DecodeBranchTarget7MM - Decode microMIPS branch offset, which is +// shifted left by 1 bit. +static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, unsigned Offset, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeFMem3(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder); +// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is +// shifted left by 1 bit. +static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, unsigned Offset, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder); +// DecodeBranchTargetMM - Decode microMIPS branch offset, which is +// shifted left by 1 bit. +static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, unsigned Offset, + uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); +// DecodeBranchTarget26MM - Decode microMIPS branch offset, which is +// shifted left by 1 bit. +static DecodeStatus DecodeBranchTarget26MM(MCInst *Inst, unsigned Offset, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); +// DecodeBranchTargetMM - Decode nanoMIPS branch offset, which is +// shifted left by 1 bit. +#define DECLARE_DecodeBranchTargetNM(bits) \ + static DecodeStatus CONCAT(DecodeBranchTargetNM, bits)( \ + MCInst * Inst, unsigned Offset, uint64_t Address, \ + const void *Decoder); +DECLARE_DecodeBranchTargetNM(10); +DECLARE_DecodeBranchTargetNM(7); +DECLARE_DecodeBranchTargetNM(21); +DECLARE_DecodeBranchTargetNM(25); +DECLARE_DecodeBranchTargetNM(14); +DECLARE_DecodeBranchTargetNM(11); +DECLARE_DecodeBranchTargetNM(5); -static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); +// DecodeJumpTargetMM - Decode microMIPS jump target, which is +// shifted left by 1 bit. +static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); -static DecodeStatus DecodeLiSimm7(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); +// DecodeJumpTargetXMM - Decode microMIPS jump and link exchange target, +// which is shifted left by 2 bit. +static DecodeStatus DecodeJumpTargetXMM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSimm4(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); +static DecodeStatus DecodeMem(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeSimm16(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); +#define DECLARE_DecodeMemNM(Offbits, isSigned, rt) \ + static DecodeStatus CONCAT(DecodeMemNM, \ + CONCAT(Offbits, CONCAT(isSigned, rt)))( \ + MCInst * Inst, uint32_t Insn, uint64_t Address, \ + const void *Decoder); +DECLARE_DecodeMemNM(6, 0, Mips_GPRNM3RegClassID); +DECLARE_DecodeMemNM(7, 0, Mips_GPRNMSPRegClassID); +DECLARE_DecodeMemNM(9, 0, Mips_GPRNMGPRegClassID); +DECLARE_DecodeMemNM(2, 0, Mips_GPRNM3RegClassID); +DECLARE_DecodeMemNM(3, 0, Mips_GPRNM3RegClassID); +DECLARE_DecodeMemNM(21, 0, Mips_GPRNMGPRegClassID); +DECLARE_DecodeMemNM(18, 0, Mips_GPRNMGPRegClassID); +DECLARE_DecodeMemNM(12, 0, Mips_GPRNM32RegClassID); +DECLARE_DecodeMemNM(9, 1, Mips_GPRNM32RegClassID); -// Decode the immediate field of an LSA instruction which -// is off by one. -static DecodeStatus DecodeLSAImm(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeMemZeroNM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); -static DecodeStatus DecodeInsSize(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); +#define DECLARE_DecodeMemNMRX(rt) \ + static DecodeStatus CONCAT(DecodeMemNMRX, \ + rt)(MCInst * Inst, uint32_t Insn, \ + uint64_t Address, const void *Decoder); +DECLARE_DecodeMemNMRX(Mips_GPRNM3RegClassID); +DECLARE_DecodeMemNMRX(Mips_GPRNM32RegClassID); -static DecodeStatus DecodeExtSize(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeMemNM4x4(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeMemEVA(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); +static DecodeStatus DecodeLoadByte15(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeCacheOp(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeCacheOpMM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodePrefeOpMM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeSyncI(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeSyncI_MM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeSynciR6(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeMSA128Mem(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeMemMMImm4(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeMemMMImm9(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeMemMMImm12(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeMemMMImm16(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeFMem(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeFMemMMR2(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeFMem2(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeFMem3(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeFMemCop2MMR6(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSimm9SP(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); +static DecodeStatus DecodeLi16Imm(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder); -static DecodeStatus DecodeANDI16Imm(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); +static DecodeStatus DecodePOOL16BEncodedField(MCInst *Inst, unsigned Value, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); +#define DECLARE_DecodeUImmWithOffsetAndScale(Bits, Offset, Scale) \ + static DecodeStatus CONCAT(DecodeUImmWithOffsetAndScale, \ + CONCAT(Bits, CONCAT(Offset, Scale)))( \ + MCInst * Inst, unsigned Value, uint64_t Address, \ + const void *Decoder); +DECLARE_DecodeUImmWithOffsetAndScale(5, 0, 4); +DECLARE_DecodeUImmWithOffsetAndScale(6, 0, 4); +DECLARE_DecodeUImmWithOffsetAndScale(2, 1, 1); +DECLARE_DecodeUImmWithOffsetAndScale(5, 1, 1); +DECLARE_DecodeUImmWithOffsetAndScale(8, 0, 1); +DECLARE_DecodeUImmWithOffsetAndScale(18, 0, 1); +DECLARE_DecodeUImmWithOffsetAndScale(21, 0, 1); -static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); +#define DEFINE_DecodeUImmWithOffset(Bits, Offset) \ + static DecodeStatus CONCAT(DecodeUImmWithOffset, \ + CONCAT(Bits, Offset))(MCInst * Inst, \ + unsigned Value, \ + uint64_t Address, \ + const void *Decoder) \ + { \ + return CONCAT(DecodeUImmWithOffsetAndScale, \ + CONCAT(Bits, CONCAT(Offset, 1)))( \ + Inst, Value, Address, Decoder); \ + } +DEFINE_DecodeUImmWithOffset(5, 1); +DEFINE_DecodeUImmWithOffset(2, 1); + +#define DECLARE_DecodeSImmWithOffsetAndScale(Bits, Offset, ScaleBy) \ + static DecodeStatus CONCAT( \ + DecodeSImmWithOffsetAndScale, \ + CONCAT(Bits, CONCAT(Offset, ScaleBy)))( \ + MCInst * Inst, unsigned Value, uint64_t Address, \ + const void *Decoder); + +#define DECLARE_DecodeSImmWithOffsetAndScale_2(Bits, Offset) DECLARE_DecodeSImmWithOffsetAndScale(Bits, Offset, 1) +#define DECLARE_DecodeSImmWithOffsetAndScale_3(Bits) DECLARE_DecodeSImmWithOffsetAndScale(Bits, 0, 1) + +DECLARE_DecodeSImmWithOffsetAndScale_3(16); +DECLARE_DecodeSImmWithOffsetAndScale_3(10); +DECLARE_DecodeSImmWithOffsetAndScale_3(4); +DECLARE_DecodeSImmWithOffsetAndScale_3(6); +DECLARE_DecodeSImmWithOffsetAndScale_3(32); + +static DecodeStatus DecodeInsSize(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeImmM1To126(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeUImm4Mask(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeUImm3Shift(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeNMRegListOperand(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeNMRegList16Operand(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeNegImm12(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +#define DECLARE_DecodeSImmWithReg(Bits, Offset, Scale, RegNum) \ + static DecodeStatus CONCAT( \ + DecodeSImmWithReg, \ + CONCAT(Bits, CONCAT(Offset, CONCAT(Scale, RegNum))))( \ + MCInst * Inst, unsigned Value, uint64_t Address, \ + const void *Decoder); +DECLARE_DecodeSImmWithReg(32, 0, 1, Mips_GP_NM); + +#define DECLARE_DecodeUImmWithReg(Bits, Offset, Scale, RegNum) \ + static DecodeStatus CONCAT( \ + DecodeUImmWithReg, \ + CONCAT(Bits, CONCAT(Offset, CONCAT(Scale, RegNum))))( \ + MCInst * Inst, unsigned Value, uint64_t Address, \ + const void *Decoder); +DECLARE_DecodeUImmWithReg(8, 0, 1, Mips_SP_NM); +DECLARE_DecodeUImmWithReg(21, 0, 1, Mips_GP_NM); +DECLARE_DecodeUImmWithReg(18, 0, 1, Mips_GP_NM); + +static DecodeStatus DecodeSImm32s12(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +#define DECLARE_DecodeAddressPCRelNM(Bits) \ + static DecodeStatus CONCAT(DecodeAddressPCRelNM, Bits)( \ + MCInst * Inst, uint32_t Insn, uint64_t Address, \ + const void *Decoder); +DECLARE_DecodeAddressPCRelNM(22); +DECLARE_DecodeAddressPCRelNM(32); + +static DecodeStatus DecodeBranchConflictNM(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeSimm9SP(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeANDI16Imm(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't /// handle. -static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeRegListOperand(MCInst *Inst, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeRegListOperand16(MCInst *Inst, - uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMovePRegPair(MCInst *Inst, - uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); - -#define GET_SUBTARGETINFO_ENUM -#include "MipsGenSubtargetInfo.inc" - -// Hacky: enable all features for disassembler -static uint64_t getFeatureBits(int mode) -{ - uint64_t Bits = (uint64_t)-1; // include every features at first - - // By default we do not support Mips1 - Bits &= ~Mips_FeatureMips1; - - // No MicroMips - Bits &= ~Mips_FeatureMicroMips; - - // ref: MipsGenDisassemblerTables.inc::checkDecoderPredicate() - // some features are mutually execlusive - if (mode & CS_MODE_16) { - //Bits &= ~Mips_FeatureMips32r2; - //Bits &= ~Mips_FeatureMips32; - //Bits &= ~Mips_FeatureFPIdx; - //Bits &= ~Mips_FeatureBitCount; - //Bits &= ~Mips_FeatureSwap; - //Bits &= ~Mips_FeatureSEInReg; - //Bits &= ~Mips_FeatureMips64r2; - //Bits &= ~Mips_FeatureFP64Bit; - } else if (mode & CS_MODE_32) { - Bits &= ~Mips_FeatureMips16; - Bits &= ~Mips_FeatureFP64Bit; - Bits &= ~Mips_FeatureMips64r2; - Bits &= ~Mips_FeatureMips32r6; - Bits &= ~Mips_FeatureMips64r6; - } else if (mode & CS_MODE_64) { - Bits &= ~Mips_FeatureMips16; - Bits &= ~Mips_FeatureMips64r6; - Bits &= ~Mips_FeatureMips32r6; - } else if (mode & CS_MODE_MIPS32R6) { - Bits |= Mips_FeatureMips32r6; - Bits &= ~Mips_FeatureMips16; - Bits &= ~Mips_FeatureFP64Bit; - Bits &= ~Mips_FeatureMips64r6; - Bits &= ~Mips_FeatureMips64r2; - } +static DecodeStatus DecodeINSVE_DF(MCInst *MI, uint32_t insn, uint64_t Address, + const void *Decoder); - if (mode & CS_MODE_MICRO) { - Bits |= Mips_FeatureMicroMips; - Bits &= ~Mips_FeatureMips4_32r2; - Bits &= ~Mips_FeatureMips2; - } +/* +static DecodeStatus DecodeDAHIDATIMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, const void *Decoder); +*/ - return Bits; -} +static DecodeStatus DecodeDAHIDATI(MCInst *MI, uint32_t insn, uint64_t Address, + const void *Decoder); -#include "MipsGenDisassemblerTables.inc" +static DecodeStatus DecodeAddiGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); -#define GET_REGINFO_ENUM -#include "MipsGenRegisterInfo.inc" +static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); -#define GET_REGINFO_MC_DESC -#include "MipsGenRegisterInfo.inc" +static DecodeStatus DecodeDaddiGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); -#define GET_INSTRINFO_ENUM -#include "MipsGenInstrInfo.inc" +static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); -void Mips_init(MCRegisterInfo *MRI) -{ - // InitMCRegisterInfo(MipsRegDesc, 394, RA, PC, - // MipsMCRegisterClasses, 62, - // MipsRegUnitRoots, - // 273, - // MipsRegDiffLists, - // MipsLaneMaskLists, - // MipsRegStrings, - // MipsRegClassStrings, - // MipsSubRegIdxLists, - // 12, - // MipsSubRegIdxRanges, - // MipsRegEncodingTable); +static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); - MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 394, - 0, 0, - MipsMCRegisterClasses, 62, - 0, 0, - MipsRegDiffLists, - 0, - MipsSubRegIdxLists, 12, - 0); -} +static DecodeStatus DecodeBlezlGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); -/// Read two bytes from the ArrayRef and return 16 bit halfword sorted -/// according to the given endianness. -static void readInstruction16(unsigned char *code, uint32_t *insn, - bool isBigEndian) -{ - // We want to read exactly 2 Bytes of data. - if (isBigEndian) - *insn = (code[0] << 8) | code[1]; - else - *insn = (code[1] << 8) | code[0]; -} - -/// readInstruction - read four bytes from the MemoryObject -/// and return 32 bit word sorted according to the given endianness -static void readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips) -{ - // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) - // always precede the low 16 bits in the instruction stream (that is, they - // are placed at lower addresses in the instruction stream). - // - // microMIPS byte ordering: - // Big-endian: 0 | 1 | 2 | 3 - // Little-endian: 1 | 0 | 3 | 2 - - // We want to read exactly 4 Bytes of data. - if (isBigEndian) { - // Encoded as a big-endian 32-bit word in the stream. - *insn = - (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24); - } else { - if (isMicroMips) { - *insn = (code[2] << 0) | (code[3] << 8) | (code[0] << 16) | - ((uint32_t) code[1] << 24); - } else { - *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | - ((uint32_t) code[3] << 24); - } - } -} - -static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr, - const uint8_t *code, size_t code_len, - uint16_t *Size, - uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI) -{ - uint32_t Insn; - DecodeStatus Result; - - if (instr->flat_insn->detail) { - memset(instr->flat_insn->detail, 0, offsetof(cs_detail, mips)+sizeof(cs_mips)); - } - - if (mode & CS_MODE_MICRO) { - if (code_len < 2) - // not enough data - return MCDisassembler_Fail; +static DecodeStatus DecodeBgtzlGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); - readInstruction16((unsigned char*)code, &Insn, isBigEndian); +static DecodeStatus DecodeBgtzGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); - // Calling the auto-generated decoder function. - Result = decodeInstruction(DecoderTableMicroMips16, instr, Insn, Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 2; - return Result; - } +static DecodeStatus DecodeBlezGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); - if (code_len < 4) - // not enough data - return MCDisassembler_Fail; +static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); - readInstruction32((unsigned char*)code, &Insn, isBigEndian, true); +static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder); - //DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); - // Calling the auto-generated decoder function. - Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 4; - return Result; - } - return MCDisassembler_Fail; - } +static DecodeStatus DecodeDINS(MCInst *MI, uint32_t Insn, uint64_t Address, + const void *Decoder); - if (code_len < 4) - // not enough data - return MCDisassembler_Fail; +static DecodeStatus DecodeDEXT(MCInst *MI, uint32_t Insn, uint64_t Address, + const void *Decoder); - readInstruction32((unsigned char*)code, &Insn, isBigEndian, false); +static DecodeStatus DecodeCRC(MCInst *MI, uint32_t Insn, uint64_t Address, + const void *Decoder); - if ((mode & CS_MODE_MIPS2) && ((mode & CS_MODE_MIPS3) == 0)) { - // DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); - Result = decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 4; - return Result; - } - } +static DecodeStatus DecodeRegListOperand(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); - if ((mode & CS_MODE_MIPS32R6) && (mode & CS_MODE_MIPS64)) { - // DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); - Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn, - Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 4; - return Result; - } - } +static DecodeStatus DecodeRegListOperand16(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); - if (mode & CS_MODE_MIPS32R6) { - // DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); - Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn, - Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 4; - return Result; - } - } +static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned RegPair, + uint64_t Address, const void *Decoder); - if (mode & CS_MODE_MIPS64) { - // DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); - Result = decodeInstruction(DecoderTableMips6432, instr, Insn, - Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 4; - return Result; - } - } +static DecodeStatus DecodeMovePOperands(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder); - // DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); - // Calling the auto-generated decoder function. - Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 4; - return Result; - } +static DecodeStatus DecodeFIXMEInstruction(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); - return MCDisassembler_Fail; -} +#include "MipsGenDisassemblerTables.inc" -bool Mips_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, - uint16_t *size, uint64_t address, void *info) +static unsigned getReg(const MCInst *Inst, unsigned RC, unsigned RegNo) { - cs_struct *handle = (cs_struct *)(uintptr_t)ud; - - DecodeStatus status = MipsDisassembler_getInstruction(handle->mode, instr, - code, code_len, - size, - address, MODE_IS_BIG_ENDIAN(handle->mode), (MCRegisterInfo *)info); - - return status == MCDisassembler_Success; + const MCRegisterClass* c = MCRegisterInfo_getRegClass(Inst->MRI, RC); + return MCRegisterClass_getRegister(c, RegNo); } -static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) -{ - const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC); - return rc->RegsBegin[RegNo]; -} +typedef DecodeStatus (*DecodeFN)(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder); -static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeINSVE_DF(MCInst *MI, uint32_t insn, uint64_t Address, + const void *Decoder) { - typedef DecodeStatus (*DecodeFN)(MCInst *, unsigned, uint64_t, const MCRegisterInfo *); // The size of the n field depends on the element size // The register class also depends on this. - uint32_t tmp = fieldFromInstruction(insn, 17, 5); + uint32_t tmp = fieldFromInstruction_4(insn, 17, 5); unsigned NSize = 0; DecodeFN RegDecoder = NULL; - - if ((tmp & 0x18) == 0x00) { // INSVE_B + if ((tmp & 0x18) == 0x00) { // INSVE_B NSize = 4; RegDecoder = DecodeMSA128BRegisterClass; } else if ((tmp & 0x1c) == 0x10) { // INSVE_H @@ -543,38 +807,57 @@ static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn, } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D NSize = 1; RegDecoder = DecodeMSA128DRegisterClass; - } //else llvm_unreachable("Invalid encoding"); - - //assert(NSize != 0 && RegDecoder != nullptr); - if (NSize == 0 || RegDecoder == NULL) - return MCDisassembler_Fail; + } else + assert(0 && "Invalid encoding"); // $wd - tmp = fieldFromInstruction(insn, 6, 5); + tmp = fieldFromInstruction_4(insn, 6, 5); if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; - // $wd_in if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; - // $n - tmp = fieldFromInstruction(insn, 16, NSize); - MCOperand_CreateImm0(MI, tmp); - + tmp = fieldFromInstruction_4(insn, 16, NSize); + MCOperand_CreateImm0(MI, (tmp)); // $ws - tmp = fieldFromInstruction(insn, 11, 5); + tmp = fieldFromInstruction_4(insn, 11, 5); if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; - // $n2 - MCOperand_CreateImm0(MI, 0); + MCOperand_CreateImm0(MI, (0)); return MCDisassembler_Success; } -static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) +/* +static DecodeStatus DecodeDAHIDATIMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, const void *Decoder) +{ + uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); + uint32_t Imm = fieldFromInstruction_4(insn, 0, 16); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); + MCOperand_CreateImm0(MI, (Imm)); + + return MCDisassembler_Success; +} +*/ + +static DecodeStatus DecodeDAHIDATI(MCInst *MI, uint32_t insn, uint64_t Address, + const void *Decoder) + { + uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); + uint32_t Imm = fieldFromInstruction_4(insn, 0, 16); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); + MCOperand_CreateImm0(MI, (Imm)); + + return MCDisassembler_Success; + } + +static DecodeStatus DecodeAddiGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, const void *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the ADDI instruction from the earlier @@ -586,31 +869,74 @@ static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn, // BEQZALC if rs == 0 && rt != 0 // BEQC if rs < rt && rs != 0 - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rt = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = + SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; bool HasRs = false; if (Rs >= Rt) { - MCInst_setOpcode(MI, Mips_BOVC); + MCInst_setOpcode(MI, (Mips_BOVC)); HasRs = true; } else if (Rs != 0 && Rs < Rt) { - MCInst_setOpcode(MI, Mips_BEQC); + MCInst_setOpcode(MI, (Mips_BEQC)); HasRs = true; } else - MCInst_setOpcode(MI, Mips_BEQZALC); + MCInst_setOpcode(MI, (Mips_BEQZALC)); if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + MCOperand_CreateImm0(MI, (Imm)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder) +{ + uint32_t Rt = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = 0; - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); - MCOperand_CreateImm0(MI, Imm); + if (Rs >= Rt) { + MCInst_setOpcode(MI, (Mips_BOVC_MMR6)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 2 + + 4; + } else if (Rs != 0 && Rs < Rt) { + MCInst_setOpcode(MI, (Mips_BEQC_MMR6)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 4 + + 4; + } else { + MCInst_setOpcode(MI, (Mips_BEQZALC_MMR6)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 2 + + 4; + } + + MCOperand_CreateImm0(MI, (Imm)); return MCDisassembler_Success; } -static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeDaddiGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the ADDI instruction from the earlier @@ -622,31 +948,152 @@ static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn, // BNEZALC if rs == 0 && rt != 0 // BNEC if rs < rt && rs != 0 - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rt = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = + SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; bool HasRs = false; if (Rs >= Rt) { - MCInst_setOpcode(MI, Mips_BNVC); + MCInst_setOpcode(MI, (Mips_BNVC)); HasRs = true; } else if (Rs != 0 && Rs < Rt) { - MCInst_setOpcode(MI, Mips_BNEC); + MCInst_setOpcode(MI, (Mips_BNEC)); HasRs = true; } else - MCInst_setOpcode(MI, Mips_BNEZALC); + MCInst_setOpcode(MI, (Mips_BNEZALC)); + + if (HasRs) + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + MCOperand_CreateImm0(MI, (Imm)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder) +{ + uint32_t Rt = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = 0; + + if (Rs >= Rt) { + MCInst_setOpcode(MI, (Mips_BNVC_MMR6)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 2 + + 4; + } else if (Rs != 0 && Rs < Rt) { + MCInst_setOpcode(MI, (Mips_BNEC_MMR6)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 4 + + 4; + } else { + MCInst_setOpcode(MI, (Mips_BNEZALC_MMR6)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 2 + + 4; + } + + MCOperand_CreateImm0(MI, (Imm)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder) +{ + // We have: + // 0b110101 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BGTZC_MMR6 if rs == 0 && rt != 0 + // BLTZC_MMR6 if rs == rt && rt != 0 + // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 + + uint32_t Rt = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = + SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) + MCInst_setOpcode(MI, (Mips_BGTZC_MMR6)); + else if (Rs == Rt) + MCInst_setOpcode(MI, (Mips_BLTZC_MMR6)); + else { + MCInst_setOpcode(MI, (Mips_BLTC_MMR6)); + HasRs = true; + } + + if (HasRs) + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + + MCOperand_CreateImm0(MI, (Imm)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder) +{ + // We have: + // 0b111101 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BLEZC_MMR6 if rs == 0 && rt != 0 + // BGEZC_MMR6 if rs == rt && rt != 0 + // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 + + uint32_t Rt = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = + SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) + MCInst_setOpcode(MI, (Mips_BLEZC_MMR6)); + else if (Rs == Rt) + MCInst_setOpcode(MI, (Mips_BGEZC_MMR6)); + else { + HasRs = true; + MCInst_setOpcode(MI, (Mips_BGEC_MMR6)); + } if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); - MCOperand_CreateImm0(MI, Imm); + MCOperand_CreateImm0(MI, (Imm)); return MCDisassembler_Success; } -static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeBlezlGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the BLEZL instruction from the earlier @@ -659,34 +1106,37 @@ static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn, // BGEZC if rs == rt && rt != 0 // BGEC if rs != rt && rs != 0 && rt != 0 - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rt = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = + SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; bool HasRs = false; if (Rt == 0) return MCDisassembler_Fail; else if (Rs == 0) - MCInst_setOpcode(MI, Mips_BLEZC); + MCInst_setOpcode(MI, (Mips_BLEZC)); else if (Rs == Rt) - MCInst_setOpcode(MI, Mips_BGEZC); + MCInst_setOpcode(MI, (Mips_BGEZC)); else { HasRs = true; - MCInst_setOpcode(MI, Mips_BGEC); + MCInst_setOpcode(MI, (Mips_BGEC)); } if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); - MCOperand_CreateImm0(MI, Imm); + MCOperand_CreateImm0(MI, (Imm)); return MCDisassembler_Success; } -static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeBgtzlGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the BGTZL instruction from the earlier @@ -701,32 +1151,35 @@ static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn, bool HasRs = false; - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rt = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = + SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; if (Rt == 0) return MCDisassembler_Fail; else if (Rs == 0) - MCInst_setOpcode(MI, Mips_BGTZC); + MCInst_setOpcode(MI, (Mips_BGTZC)); else if (Rs == Rt) - MCInst_setOpcode(MI, Mips_BLTZC); + MCInst_setOpcode(MI, (Mips_BLTZC)); else { - MCInst_setOpcode(MI, Mips_BLTC); + MCInst_setOpcode(MI, (Mips_BLTC)); HasRs = true; } if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); - MCOperand_CreateImm0(MI, Imm); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + + MCOperand_CreateImm0(MI, (Imm)); return MCDisassembler_Success; } -static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeBgtzGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, const void *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the BGTZ instruction from the earlier @@ -739,40 +1192,43 @@ static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn, // BLTZALC if rs != 0 && rs == rt // BLTUC if rs != 0 && rs != rt - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rt = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = + SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; bool HasRs = false; bool HasRt = false; if (Rt == 0) { - MCInst_setOpcode(MI, Mips_BGTZ); + MCInst_setOpcode(MI, (Mips_BGTZ)); HasRs = true; } else if (Rs == 0) { - MCInst_setOpcode(MI, Mips_BGTZALC); + MCInst_setOpcode(MI, (Mips_BGTZALC)); HasRt = true; } else if (Rs == Rt) { - MCInst_setOpcode(MI, Mips_BLTZALC); + MCInst_setOpcode(MI, (Mips_BLTZALC)); HasRs = true; } else { - MCInst_setOpcode(MI, Mips_BLTUC); + MCInst_setOpcode(MI, (Mips_BLTUC)); HasRs = true; HasRt = true; } if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); if (HasRt) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); - MCOperand_CreateImm0(MI, Imm); + MCOperand_CreateImm0(MI, (Imm)); return MCDisassembler_Success; } -static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeBlezGroupBranch(MCInst *MI, uint32_t insn, + uint64_t Address, const void *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the BLEZL instruction from the earlier @@ -785,294 +1241,984 @@ static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn, // BGEZALC if rs == rt && rt != 0 // BGEUC if rs != rt && rs != 0 && rt != 0 - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rt = fieldFromInstruction_4(insn, 16, 5); + int64_t Imm = + SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; bool HasRs = false; if (Rt == 0) return MCDisassembler_Fail; else if (Rs == 0) - MCInst_setOpcode(MI, Mips_BLEZALC); + MCInst_setOpcode(MI, (Mips_BLEZALC)); else if (Rs == Rt) - MCInst_setOpcode(MI, Mips_BGEZALC); + MCInst_setOpcode(MI, (Mips_BGEZALC)); else { HasRs = true; - MCInst_setOpcode(MI, Mips_BGEUC); + MCInst_setOpcode(MI, (Mips_BGEUC)); } if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + + MCOperand_CreateImm0(MI, (Imm)); + + return MCDisassembler_Success; +} + +// Override the generated disassembler to produce DEXT all the time. This is +// for feature / behaviour parity with binutils. +static DecodeStatus DecodeDEXT(MCInst *MI, uint32_t Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Msbd = fieldFromInstruction_4(Insn, 11, 5); + unsigned Lsb = fieldFromInstruction_4(Insn, 6, 5); + unsigned Size = 0; + unsigned Pos = 0; + + switch (MCInst_getOpcode(MI)) { + case Mips_DEXT: + Pos = Lsb; + Size = Msbd + 1; + break; + case Mips_DEXTM: + Pos = Lsb; + Size = Msbd + 1 + 32; + break; + case Mips_DEXTU: + Pos = Lsb + 32; + Size = Msbd + 1; + break; + default: + assert(0 && "Unknown DEXT instruction!"); + } + + MCInst_setOpcode(MI, (Mips_DEXT)); + + uint32_t Rs = fieldFromInstruction_4(Insn, 21, 5); + uint32_t Rt = fieldFromInstruction_4(Insn, 16, 5); + + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rt))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); + MCOperand_CreateImm0(MI, (Pos)); + MCOperand_CreateImm0(MI, (Size)); + + return MCDisassembler_Success; +} + +// Override the generated disassembler to produce DINS all the time. This is +// for feature / behaviour parity with binutils. +static DecodeStatus DecodeDINS(MCInst *MI, uint32_t Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Msbd = fieldFromInstruction_4(Insn, 11, 5); + unsigned Lsb = fieldFromInstruction_4(Insn, 6, 5); + unsigned Size = 0; + unsigned Pos = 0; + + switch (MCInst_getOpcode(MI)) { + case Mips_DINS: + Pos = Lsb; + Size = Msbd + 1 - Pos; + break; + case Mips_DINSM: + Pos = Lsb; + Size = Msbd + 33 - Pos; + break; + case Mips_DINSU: + Pos = Lsb + 32; + // mbsd = pos + size - 33 + // mbsd - pos + 33 = size + Size = Msbd + 33 - Pos; + break; + default: + assert(0 && "Unknown DINS instruction!"); + } + + uint32_t Rs = fieldFromInstruction_4(Insn, 21, 5); + uint32_t Rt = fieldFromInstruction_4(Insn, 16, 5); + + MCInst_setOpcode(MI, (Mips_DINS)); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rt))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); + MCOperand_CreateImm0(MI, (Pos)); + MCOperand_CreateImm0(MI, (Size)); + + return MCDisassembler_Success; +} + +// Auto-generated decoder wouldn't add the third operand for CRC32*. +static DecodeStatus DecodeCRC(MCInst *MI, uint32_t Insn, uint64_t Address, + const void *Decoder) +{ + uint32_t Rs = fieldFromInstruction_4(Insn, 21, 5); + uint32_t Rt = fieldFromInstruction_4(Insn, 16, 5); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); + return MCDisassembler_Success; +} + +/// Read two bytes from the ArrayRef and return 16 bit halfword sorted +/// according to the given endianness. +static DecodeStatus readInstruction16(const uint8_t *Bytes, size_t BytesLen, + uint64_t Address, uint64_t *Size, + uint64_t *Insn, bool IsBigEndian) +{ + // We want to read exactly 2 Bytes of data. + if (BytesLen < 2) { + *Size = 0; + return MCDisassembler_Fail; + } + + if (IsBigEndian) { + *Insn = (Bytes[0] << 8) | Bytes[1]; + } else { + *Insn = (Bytes[1] << 8) | Bytes[0]; + } + + return MCDisassembler_Success; +} + +/// Read four bytes from the ArrayRef and return 32 bit word sorted +/// according to the given endianness. +static DecodeStatus readInstruction32(const uint8_t *Bytes, size_t BytesLen, + uint64_t Address, uint64_t *Size, + uint64_t *Insn, bool IsBigEndian, + bool IsMicroMips) +{ + // We want to read exactly 4 Bytes of data. + if (BytesLen < 4) { + *Size = 0; + return MCDisassembler_Fail; + } + + // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) + // always precede the low 16 bits in the instruction stream (that is, they + // are placed at lower addresses in the instruction stream). + // + // microMIPS byte ordering: + // Big-endian: 0 | 1 | 2 | 3 + // Little-endian: 1 | 0 | 3 | 2 + + if (IsBigEndian) { + // Encoded as a big-endian 32-bit word in the stream. + *Insn = (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | + (Bytes[0] << 24); + } else { + if (IsMicroMips) { + *Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | + (Bytes[0] << 16) | (Bytes[1] << 24); + } else { + *Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | + (Bytes[2] << 16) | (Bytes[3] << 24); + } + } + + return MCDisassembler_Success; +} - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); +/// Read 6 bytes from the ArrayRef and return in a 64-bit bit word sorted +/// according to the given endianness and encoding byte-order. +static DecodeStatus readInstruction48(const uint8_t *Bytes, size_t BytesLen, + uint64_t Address, uint64_t *Size, + uint64_t *Insn, bool IsBigEndian, + bool IsNanoMips) +{ + // We want to read exactly 6 Bytes of little-endian data in nanoMIPS mode. + if (BytesLen < 6 || IsBigEndian || !IsNanoMips) { + *Size = 0; + return MCDisassembler_Fail; + } - MCOperand_CreateImm0(MI, Imm); + // High 16 bits of a 32-bit nanoMIPS instruction (where the opcode is) + // always precede the low 16 bits in the instruction stream (that is, they + // are placed at lower addresses in the instruction stream). + // + // nanoMIPS byte ordering: + // Little-endian: 1 | 0 | 3 | 2 | 5 | 4 + *Insn = (Bytes[0] << 0) | (Bytes[1] << 8); + *Insn = ((*Insn << 32) | (Bytes[4] << 0) | (Bytes[5] << 8) | + (Bytes[2] << 16) | ((unsigned)Bytes[3] << 24)); return MCDisassembler_Success; } -static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t *Bytes, + size_t BytesLen, uint64_t Address, SStream *CStream) { + uint64_t Insn; + DecodeStatus Result; + *Size = 0; + + cs_mode mode = Instr->csh->mode; + bool IsBigEndian = mode & CS_MODE_BIG_ENDIAN; + bool IsMicroMips = Mips_getFeatureBits(mode, Mips_FeatureMicroMips); + bool IsNanoMips = Mips_getFeatureBits(mode, Mips_FeatureNanoMips); + bool IsMips32r6 = Mips_getFeatureBits(mode, Mips_FeatureMips32r6); + bool IsMips2 = Mips_getFeatureBits(mode, Mips_FeatureMips2); + bool IsCnMips = Mips_getFeatureBits(mode, Mips_FeatureCnMips); + bool IsCnMipsP = Mips_getFeatureBits(mode, Mips_FeatureCnMipsP); + bool IsFP64 = Mips_getFeatureBits(mode, Mips_FeatureFP64Bit); + bool IsGP64 = Mips_getFeatureBits(mode, Mips_FeatureGP64Bit); + bool IsPTR64 = Mips_getFeatureBits(mode, Mips_FeaturePTR64Bit); + // Only present in MIPS-I and MIPS-II + bool HasCOP3 = !Mips_getFeatureBits(mode, Mips_FeatureMips32) && + !Mips_getFeatureBits(mode, Mips_FeatureMips3); + + if (IsNanoMips) { + uint64_t Insn2; + Result = readInstruction48(Bytes, BytesLen, Address, Size, + &Insn2, IsBigEndian, IsNanoMips); + if (Result != MCDisassembler_Fail) { + // Calling the auto-generated decoder function. + Result = decodeInstruction_8(DecoderTableNanoMips48, + Instr, Insn2, Address, NULL); + if (Result != MCDisassembler_Fail) { + *Size = 6; + return Result; + } + } + + Result = readInstruction32(Bytes, BytesLen, Address, Size, + &Insn, IsBigEndian, IsNanoMips); + if (Result != MCDisassembler_Fail) { + // Calling the auto-generated decoder function. + Result = decodeInstruction_4(DecoderTableNanoMips32, + Instr, Insn, Address, + NULL); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + } + + Result = readInstruction16(Bytes, BytesLen, Address, Size, + &Insn, IsBigEndian); + if (Result != MCDisassembler_Fail) { + // Calling the auto-generated decoder function for NanoMips + // 16-bit instructions. + Result = decodeInstruction_2(DecoderTableNanoMips16, + Instr, Insn, Address, + NULL); + if (Result != MCDisassembler_Fail) { + *Size = 2; + return Result; + } + } + + // This is an invalid instruction. Claim that the Size is 2 bytes. Since + // nanoMIPS instructions have a minimum alignment of 2, the next 2 bytes + // could form a valid instruction. + *Size = 2; + return MCDisassembler_Fail; + } + + if (IsMicroMips) { + Result = readInstruction16(Bytes, BytesLen, Address, Size, + &Insn, IsBigEndian); + if (Result == MCDisassembler_Fail) + return MCDisassembler_Fail; + + if (IsMips32r6) { + // Calling the auto-generated decoder function for microMIPS32R6 + // 16-bit instructions. + Result = decodeInstruction_2(DecoderTableMicroMipsR616, + Instr, Insn, Address, + NULL); + if (Result != MCDisassembler_Fail) { + *Size = 2; + return Result; + } + } + + // Calling the auto-generated decoder function for microMIPS 16-bit + // instructions. + Result = decodeInstruction_2(DecoderTableMicroMips16, Instr, + Insn, Address, NULL); + if (Result != MCDisassembler_Fail) { + *Size = 2; + return Result; + } + + Result = readInstruction32(Bytes, BytesLen, Address, Size, + &Insn, IsBigEndian, IsMicroMips); + if (Result == MCDisassembler_Fail) + return MCDisassembler_Fail; + + if (IsMips32r6) { + // Calling the auto-generated decoder function. + Result = decodeInstruction_4(DecoderTableMicroMipsR632, + Instr, Insn, Address, + NULL); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + } + + // Calling the auto-generated decoder function. + Result = decodeInstruction_4(DecoderTableMicroMips32, Instr, + Insn, Address, NULL); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + + if (IsFP64) { + Result = + decodeInstruction_4(DecoderTableMicroMipsFP6432, + Instr, Insn, Address, NULL); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + } + + // This is an invalid instruction. Claim that the Size is 2 bytes. Since + // microMIPS instructions have a minimum alignment of 2, the next 2 bytes + // could form a valid instruction. The two bytes we rejected as an + // instruction could have actually beeen an inline constant pool that is + // unconditionally branched over. + *Size = 2; + return MCDisassembler_Fail; + } + + // Attempt to read the instruction so that we can attempt to decode it. If + // the buffer is not 4 bytes long, let the higher level logic figure out + // what to do with a size of zero and MCDisassembler::Fail. + Result = readInstruction32(Bytes, BytesLen, Address, Size, &Insn, IsBigEndian, + IsMicroMips); + if (Result == MCDisassembler_Fail) + return MCDisassembler_Fail; + + // The only instruction size for standard encoded MIPS. + *Size = 4; + + if (HasCOP3) { + Result = decodeInstruction_4(DecoderTableCOP3_32, Instr, Insn, + Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + } + + if (IsMips32r6 && IsGP64) { + Result = decodeInstruction_4(DecoderTableMips32r6_64r6_GP6432, + Instr, Insn, Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + } + + if (IsMips32r6 && IsPTR64) { + Result = decodeInstruction_4(DecoderTableMips32r6_64r6_PTR6432, + Instr, Insn, Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + } + + if (IsMips32r6) { + Result = decodeInstruction_4(DecoderTableMips32r6_64r632, Instr, + Insn, Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + } + + if (IsMips2 && IsPTR64) { + Result = decodeInstruction_4(DecoderTableMips32_64_PTR6432, + Instr, Insn, Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + } + + if (IsCnMips) { + Result = decodeInstruction_4(DecoderTableCnMips32, Instr, Insn, + Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + } + + if (IsCnMipsP) { + Result = decodeInstruction_4(DecoderTableCnMipsP32, Instr, Insn, + Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + } + + if (IsGP64) { + Result = decodeInstruction_4(DecoderTableMips6432, Instr, Insn, + Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + } + + if (IsFP64) { + Result = decodeInstruction_4(DecoderTableMipsFP6432, Instr, + Insn, Address, NULL); + if (Result != MCDisassembler_Fail) + return Result; + } + + // Calling the auto-generated decoder function. + Result = decodeInstruction_4(DecoderTableMips32, Instr, Insn, Address, + NULL); + if (Result != MCDisassembler_Fail) + return Result; + return MCDisassembler_Fail; } -static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; + return MCDisassembler_Fail; +} +static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ if (RegNo > 31) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_GPR64RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); + unsigned Reg = getReg(Inst, Mips_GPR64RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; + if (RegNo > 7) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst, Mips_GPRMM16RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} +static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ if (RegNo > 7) return MCDisassembler_Fail; + unsigned Reg = getReg(Inst, Mips_GPRMM16ZeroRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} - Reg = getReg(Decoder, Mips_GPRMM16RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 7) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst, Mips_GPRMM16MovePRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; + if (RegNo > 31) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst, Mips_GPR32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} +static DecodeStatus DecodeGPRNM3RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ if (RegNo > 7) return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_GPRMM16ZeroRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); + RegNo |= ((RegNo & 0x4) ^ 0x4) << 2; + unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeGPRNMRARegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; + MCOperand_CreateReg0(Inst, (Mips_RA_NM)); + return MCDisassembler_Success; +} +static DecodeStatus DecodeGPRNM3ZRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ if (RegNo > 7) return MCDisassembler_Fail; + if (RegNo != 0) + RegNo |= ((RegNo & 0x4) ^ 0x4) << 2; + unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRNM4RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 31) + return MCDisassembler_Fail; + RegNo &= ~0x8; + RegNo += (RegNo < 4 ? 8 : 0); + unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRNM4ZRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 31) + return MCDisassembler_Fail; + RegNo &= ~0x8; + if (RegNo == 3) + RegNo = 0; + else + RegNo += (RegNo < 3 ? 8 : 0); + unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRNM32NZRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo == 0) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRNM32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 31) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRNM2R1RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 31) + return MCDisassembler_Fail; + RegNo += 4; + unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Reg + 1)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRNM1R1RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo != 0 && RegNo != 1) + return MCDisassembler_Fail; + RegNo += 4; + unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} - Reg = getReg(Decoder, Mips_GPRMM16MovePRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); +static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureGP64Bit)) + return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); + + return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); +} + +static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); +} + +static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst, Mips_FGR64RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst, Mips_FGR32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 31) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst, Mips_CCRRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - - if (RegNo > 31) + if (RegNo > 7) return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_GPR32RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); + unsigned Reg = getReg(Inst, Mips_FCCRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - // if (static_cast(Decoder)->isGP64()) - if (Inst->csh->mode & CS_MODE_MIPS64) - return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); + if (RegNo > 31) + return MCDisassembler_Fail; - return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); -} + unsigned Reg = getReg(Inst, Mips_FGRCCRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMem(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) +{ + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); + unsigned Base = fieldFromInstruction_4(Insn, 21, 5); + + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); + + if (MCInst_getOpcode(Inst) == Mips_SC || + MCInst_getOpcode(Inst) == Mips_SCD) + MCOperand_CreateReg0(Inst, (Reg)); + + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + + return MCDisassembler_Success; +} + +#define DEFINE_DecodeMemNM(Offbits, isSigned, rt) \ + static DecodeStatus CONCAT(DecodeMemNM, \ + CONCAT(Offbits, CONCAT(isSigned, rt)))( \ + MCInst * Inst, uint32_t Insn, uint64_t Address, \ + const void *Decoder) \ + { \ + int Offset = (Insn & ((1 << Offbits) - 1)); \ + if (isSigned) \ + Offset = SignExtend32((Offset), Offbits); \ + unsigned Base; \ +\ + switch (rt) { \ + case Mips_GPRNMGPRegClassID: \ + case Mips_GPRNMSPRegClassID: \ + Base = 0; \ + break; \ + case Mips_GPRNM3RegClassID: \ + Base = fieldFromInstruction_4(Insn, Offbits, 3); \ + break; \ + case Mips_GPRNM4RegClassID: \ + case Mips_GPRNM4ZRegClassID: \ +\ + break; \ + default: \ + Base = fieldFromInstruction_4(Insn, Offbits, 5); \ + } \ + Base = getReg(Inst, rt, Base); \ +\ + MCOperand_CreateReg0(Inst, (Base)); \ + MCOperand_CreateImm0(Inst, (Offset)); \ +\ + return MCDisassembler_Success; \ + } +DEFINE_DecodeMemNM(6, 0, Mips_GPRNM3RegClassID); +DEFINE_DecodeMemNM(7, 0, Mips_GPRNMSPRegClassID); +DEFINE_DecodeMemNM(9, 0, Mips_GPRNMGPRegClassID); +DEFINE_DecodeMemNM(2, 0, Mips_GPRNM3RegClassID); +DEFINE_DecodeMemNM(3, 0, Mips_GPRNM3RegClassID); +DEFINE_DecodeMemNM(21, 0, Mips_GPRNMGPRegClassID); +DEFINE_DecodeMemNM(18, 0, Mips_GPRNMGPRegClassID); +DEFINE_DecodeMemNM(12, 0, Mips_GPRNM32RegClassID); +DEFINE_DecodeMemNM(9, 1, Mips_GPRNM32RegClassID); + +static DecodeStatus DecodeMemZeroNM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + unsigned Base; + Base = fieldFromInstruction_4(Insn, 0, 5); + Base = getReg(Inst, Mips_GPRNM32RegClassID, Base); + MCOperand_CreateReg0(Inst, (Base)); + + return MCDisassembler_Success; +} + +#define DEFINE_DecodeMemNMRX(RegClass) \ + static DecodeStatus CONCAT(DecodeMemNMRX, RegClass)( \ + MCInst * Inst, uint32_t Insn, uint64_t Address, \ + const void *Decoder) \ + { \ + unsigned Offset; \ + unsigned Base; \ + Offset = fieldFromInstruction_4(Insn, 0, 5); \ + Base = fieldFromInstruction_4(Insn, 5, 5); \ +\ + Base = getReg(Inst, RegClass, Base); \ + Offset = getReg(Inst, RegClass, Offset); \ + MCOperand_CreateReg0(Inst, (Base)); \ + MCOperand_CreateReg0(Inst, (Offset)); \ +\ + return MCDisassembler_Success; \ + } +DEFINE_DecodeMemNMRX(Mips_GPRNM3RegClassID); +DEFINE_DecodeMemNMRX(Mips_GPRNM32RegClassID); -static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeMemNM4x4(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); -} + int Offset = fieldFromInstruction_4(Insn, 0, 4); + unsigned Base; -static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; + Base = getReg(Inst, Mips_GPRNM32RegClassID, + fieldFromInstruction_4(Insn, 4, 5) & ~0x8); - if (RegNo > 31) - return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); - Reg = getReg(Decoder, Mips_FGR64RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } -static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeMemEVA(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) { - unsigned Reg; + int Offset = SignExtend32((Insn >> 7), 9); + unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); + unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - if (RegNo > 31) - return MCDisassembler_Fail; + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); + + if (MCInst_getOpcode(Inst) == Mips_SCE) + MCOperand_CreateReg0(Inst, (Reg)); + + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); - Reg = getReg(Decoder, Mips_FGR32RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } -static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; +#include "MipsCP0RegisterMap.h" - if (RegNo > 31) - return MCDisassembler_Fail; +static DecodeStatus DecodeCOP0SelRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + int Reg = COP0Map_getEncIndexMap(RegNo); - Reg = getReg(Decoder, Mips_CCRRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); + if (Reg != -1) { + Reg = getReg(Inst, Mips_COP0SelRegClassID, Reg); + MCOperand_CreateReg0(Inst, (Reg)); + } else { + // Not a named register encoding - print numeric register and select value + switch (MCInst_getOpcode(Inst)) { + case Mips_MFC0Sel_NM: + MCInst_setOpcode(Inst, (Mips_MFC0_NM)); + break; + case Mips_MFHC0Sel_NM: + MCInst_setOpcode(Inst, (Mips_MFHC0_NM)); + break; + case Mips_MTC0Sel_NM: + MCInst_setOpcode(Inst, (Mips_MTC0_NM)); + break; + case Mips_MTHC0Sel_NM: + MCInst_setOpcode(Inst, (Mips_MTHC0_NM)); + break; + default: + assert(0 && "Unknown instruction!"); + } + Reg = getReg(Inst, Mips_COP0RegClassID, RegNo >> 5); + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateImm0(Inst, (RegNo & 0x1f)); + } return MCDisassembler_Success; } -static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeLoadByte15(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - unsigned Reg; + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); + unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); - if (RegNo > 7) - return MCDisassembler_Fail; + Base = getReg(Inst, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); + + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); - Reg = getReg(Decoder, Mips_FCCRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } -static DecodeStatus DecodeCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeCacheOp(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) { - unsigned Reg; + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Hint = fieldFromInstruction_4(Insn, 16, 5); + unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - if (RegNo > 7) - return MCDisassembler_Fail; + Base = getReg(Inst, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + MCOperand_CreateImm0(Inst, (Hint)); - Reg = getReg(Decoder, Mips_CCRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } -static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeCacheOpMM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - unsigned Reg; + int Offset = SignExtend32((Insn & 0xfff), 12); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); + unsigned Hint = fieldFromInstruction_4(Insn, 21, 5); - if (RegNo > 31) - return MCDisassembler_Fail; + Base = getReg(Inst, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + MCOperand_CreateImm0(Inst, (Hint)); - Reg = getReg(Decoder, Mips_FGRCCRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } -static DecodeStatus DecodeMem(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodePrefeOpMM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); - int opcode = MCInst_getOpcode(Inst); - - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + int Offset = SignExtend32((Insn & 0x1ff), 9); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); + unsigned Hint = fieldFromInstruction_4(Insn, 21, 5); - if (opcode == Mips_SC || opcode == Mips_SCD) { - MCOperand_CreateReg0(Inst, Reg); - } + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + MCOperand_CreateImm0(Inst, (Hint)); return MCDisassembler_Success; } -static DecodeStatus DecodeCacheOp(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder) { - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Hint = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + int Offset = SignExtend32((Insn >> 7), 9); + unsigned Hint = fieldFromInstruction_4(Insn, 16, 5); + unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - MCOperand_CreateImm0(Inst, Hint); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + MCOperand_CreateImm0(Inst, (Hint)); return MCDisassembler_Success; } -static DecodeStatus DecodeCacheOpMM(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeSyncI(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) { - int Offset = SignExtend32(Insn & 0xfff, 12); - unsigned Base = fieldFromInstruction(Insn, 16, 5); - unsigned Hint = fieldFromInstruction(Insn, 21, 5); + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - MCOperand_CreateImm0(Inst, Hint); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); return MCDisassembler_Success; } -static DecodeStatus DecodeCacheOpR6(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeSyncI_MM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - int Offset = fieldFromInstruction(Insn, 7, 9); - unsigned Hint = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - MCOperand_CreateImm0(Inst, Hint); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); return MCDisassembler_Success; } -static DecodeStatus DecodeSyncI(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeSynciR6(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) { - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + int Immediate = SignExtend32((Insn & 0xffff), 16); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Immediate)); return MCDisassembler_Success; } -static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn, - uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeMSA128Mem(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - int Offset = SignExtend32(fieldFromInstruction(Insn, 16, 10), 10); - unsigned Reg = fieldFromInstruction(Insn, 6, 5); - unsigned Base = fieldFromInstruction(Insn, 11, 5); + int Offset = SignExtend32((fieldFromInstruction_4(Insn, 16, 10)), 10); + unsigned Reg = fieldFromInstruction_4(Insn, 6, 5); + unsigned Base = fieldFromInstruction_4(Insn, 11, 5); - Reg = getReg(Decoder, Mips_MSA128BRegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst, Mips_MSA128BRegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - // MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); // The immediate field of an LD/ST instruction is scaled which means it must // be multiplied (when decoding) by the size (in bytes) of the instructions' @@ -1081,714 +2227,1133 @@ static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn, // .h - 2 bytes // .w - 4 bytes // .d - 8 bytes - switch(MCInst_getOpcode(Inst)) { - default: - //assert (0 && "Unexpected instruction"); - return MCDisassembler_Fail; - break; - case Mips_LD_B: - case Mips_ST_B: - MCOperand_CreateImm0(Inst, Offset); - break; - case Mips_LD_H: - case Mips_ST_H: - MCOperand_CreateImm0(Inst, Offset * 2); - break; - case Mips_LD_W: - case Mips_ST_W: - MCOperand_CreateImm0(Inst, Offset * 4); - break; - case Mips_LD_D: - case Mips_ST_D: - MCOperand_CreateImm0(Inst, Offset * 8); - break; + switch (MCInst_getOpcode(Inst)) { + default: + + return MCDisassembler_Fail; + break; + case Mips_LD_B: + case Mips_ST_B: + MCOperand_CreateImm0(Inst, (Offset)); + break; + case Mips_LD_H: + case Mips_ST_H: + MCOperand_CreateImm0(Inst, (Offset * 2)); + break; + case Mips_LD_W: + case Mips_ST_W: + MCOperand_CreateImm0(Inst, (Offset * 4)); + break; + case Mips_LD_D: + case Mips_ST_D: + MCOperand_CreateImm0(Inst, (Offset * 8)); + break; } return MCDisassembler_Success; } -static DecodeStatus DecodeMemMMImm4(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeMemMMImm4(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { unsigned Offset = Insn & 0xf; - unsigned Reg = fieldFromInstruction(Insn, 7, 3); - unsigned Base = fieldFromInstruction(Insn, 4, 3); + unsigned Reg = fieldFromInstruction_4(Insn, 7, 3); + unsigned Base = fieldFromInstruction_4(Insn, 4, 3); switch (MCInst_getOpcode(Inst)) { - case Mips_LBU16_MM: - case Mips_LHU16_MM: - case Mips_LW16_MM: - if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) - == MCDisassembler_Fail) - return MCDisassembler_Fail; - break; - case Mips_SB16_MM: - case Mips_SH16_MM: - case Mips_SW16_MM: - if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) - == MCDisassembler_Fail) - return MCDisassembler_Fail; - break; + case Mips_LBU16_MM: + case Mips_LHU16_MM: + case Mips_LW16_MM: + if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + break; + case Mips_SB16_MM: + case Mips_SB16_MMR6: + case Mips_SH16_MM: + case Mips_SH16_MMR6: + case Mips_SW16_MM: + case Mips_SW16_MMR6: + if (DecodeGPRMM16ZeroRegisterClass( + Inst, Reg, Address, Decoder) == MCDisassembler_Fail) + return MCDisassembler_Fail; + break; } - if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) - == MCDisassembler_Fail) + if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) == + MCDisassembler_Fail) return MCDisassembler_Fail; switch (MCInst_getOpcode(Inst)) { - case Mips_LBU16_MM: - if (Offset == 0xf) - MCOperand_CreateImm0(Inst, -1); - else - MCOperand_CreateImm0(Inst, Offset); - break; - case Mips_SB16_MM: - MCOperand_CreateImm0(Inst, Offset); - break; - case Mips_LHU16_MM: - case Mips_SH16_MM: - MCOperand_CreateImm0(Inst, Offset << 1); - break; - case Mips_LW16_MM: - case Mips_SW16_MM: - MCOperand_CreateImm0(Inst, Offset << 2); - break; + case Mips_LBU16_MM: + if (Offset == 0xf) + MCOperand_CreateImm0(Inst, (-1)); + else + MCOperand_CreateImm0(Inst, (Offset)); + break; + case Mips_SB16_MM: + case Mips_SB16_MMR6: + MCOperand_CreateImm0(Inst, (Offset)); + break; + case Mips_LHU16_MM: + case Mips_SH16_MM: + case Mips_SH16_MMR6: + MCOperand_CreateImm0(Inst, (Offset << 1)); + break; + case Mips_LW16_MM: + case Mips_SW16_MM: + case Mips_SW16_MMR6: + MCOperand_CreateImm0(Inst, (Offset << 2)); + break; } return MCDisassembler_Success; } -static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { unsigned Offset = Insn & 0x1F; - unsigned Reg = fieldFromInstruction(Insn, 5, 5); + unsigned Reg = fieldFromInstruction_4(Insn, 5, 5); - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Mips_SP); - MCOperand_CreateImm0(Inst, Offset << 2); + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Mips_SP)); + MCOperand_CreateImm0(Inst, (Offset << 2)); return MCDisassembler_Success; } -static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { unsigned Offset = Insn & 0x7F; - unsigned Reg = fieldFromInstruction(Insn, 7, 3); + unsigned Reg = fieldFromInstruction_4(Insn, 7, 3); - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Mips_GP); - MCOperand_CreateImm0(Inst, Offset << 2); + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Mips_GP)); + MCOperand_CreateImm0(Inst, (Offset << 2)); return MCDisassembler_Success; } -static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder) { - int Offset = SignExtend32(Insn & 0xf, 4); + int Offset; + switch (MCInst_getOpcode(Inst)) { + case Mips_LWM16_MMR6: + case Mips_SWM16_MMR6: + Offset = fieldFromInstruction_4(Insn, 4, 4); + break; + default: + Offset = SignExtend32((Insn & 0xf), 4); + break; + } - if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) == MCDisassembler_Fail) + if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) == + MCDisassembler_Fail) return MCDisassembler_Fail; - MCOperand_CreateReg0(Inst, Mips_SP); - MCOperand_CreateImm0(Inst, Offset * 4); + MCOperand_CreateReg0(Inst, (Mips_SP)); + MCOperand_CreateImm0(Inst, (Offset << 2)); return MCDisassembler_Success; } -static DecodeStatus DecodeMemMMImm12(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeMemMMImm9(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - int Offset = SignExtend32(Insn & 0x0fff, 12); - unsigned Reg = fieldFromInstruction(Insn, 21, 5); - unsigned Base = fieldFromInstruction(Insn, 16, 5); + int Offset = SignExtend32((Insn & 0x1ff), 9); + unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - switch (MCInst_getOpcode(Inst)) { - case Mips_SWM32_MM: - case Mips_LWM32_MM: - if (DecodeRegListOperand(Inst, Insn, Address, Decoder) - == MCDisassembler_Fail) - return MCDisassembler_Fail; - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - break; - case Mips_SC_MM: - MCOperand_CreateReg0(Inst, Reg); - // fallthrough - default: - MCOperand_CreateReg0(Inst, Reg); - if (MCInst_getOpcode(Inst) == Mips_LWP_MM || MCInst_getOpcode(Inst) == Mips_SWP_MM) - MCOperand_CreateReg0(Inst, Reg + 1); + if (MCInst_getOpcode(Inst) == Mips_SCE_MM || + MCInst_getOpcode(Inst) == Mips_SC_MMR6) + MCOperand_CreateReg0(Inst, (Reg)); + + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMemMMImm12(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + int Offset = SignExtend32((Insn & 0x0fff), 12); + unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); + + switch (MCInst_getOpcode(Inst)) { + case Mips_SWM32_MM: + case Mips_LWM32_MM: + if (DecodeRegListOperand(Inst, Insn, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + break; + case Mips_SC_MM: + MCOperand_CreateReg0(Inst, (Reg)); + // fall through + default: + MCOperand_CreateReg0(Inst, (Reg)); + if (MCInst_getOpcode(Inst) == Mips_LWP_MM || + MCInst_getOpcode(Inst) == Mips_SWP_MM) + MCOperand_CreateReg0(Inst, (Reg + 1)); + + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); } return MCDisassembler_Success; } -static DecodeStatus DecodeMemMMImm16(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeMemMMImm16(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); + + Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFMem(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) +{ + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); + unsigned Base = fieldFromInstruction_4(Insn, 21, 5); + + Reg = getReg(Inst, Mips_FGR64RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFMemMMR2(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 21, 5); - unsigned Base = fieldFromInstruction(Insn, 16, 5); + // This function is the same as DecodeFMem but with the Reg and Base fields + // swapped according to microMIPS spec. + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); + unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst, Mips_FGR64RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); return MCDisassembler_Success; } -static DecodeStatus DecodeFMem(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeFMem2(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) { - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); + unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Reg = getReg(Decoder, Mips_FGR64RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst, Mips_COP2RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); return MCDisassembler_Success; } -static DecodeStatus DecodeFMem2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeFMem3(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) { - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + int Offset = SignExtend32((Insn & 0xffff), 16); + unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); + unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst, Mips_COP3RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); return MCDisassembler_Success; } -static DecodeStatus DecodeFMem3(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + int Offset = SignExtend32((Insn & 0x07ff), 11); + unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); + unsigned Base = fieldFromInstruction_4(Insn, 11, 5); - Reg = getReg(Decoder, Mips_COP3RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst, Mips_COP2RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); return MCDisassembler_Success; } -static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeFMemCop2MMR6(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - int Offset = SignExtend32(Insn & 0x07ff, 11); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 11, 5); + int Offset = SignExtend32((Insn & 0x07ff), 11); + unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); + unsigned Base = fieldFromInstruction_4(Insn, 16, 5); - Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst, Mips_COP2RegClassID, Reg); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateReg0(Inst, (Reg)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); return MCDisassembler_Success; } -static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - int64_t Offset = SignExtend64((Insn >> 7) & 0x1ff, 9); - unsigned Rt = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); + int64_t Offset = SignExtend64(((Insn >> 7) & 0x1ff), 9); + unsigned Rt = fieldFromInstruction_4(Insn, 16, 5); + unsigned Base = fieldFromInstruction_4(Insn, 21, 5); - Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + Rt = getReg(Inst, Mips_GPR32RegClassID, Rt); + Base = getReg(Inst, Mips_GPR32RegClassID, Base); if (MCInst_getOpcode(Inst) == Mips_SC_R6 || - MCInst_getOpcode(Inst) == Mips_SCD_R6) { - MCOperand_CreateReg0(Inst, Rt); + MCInst_getOpcode(Inst) == Mips_SCD_R6) { + MCOperand_CreateReg0(Inst, (Rt)); } - MCOperand_CreateReg0(Inst, Rt); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateReg0(Inst, (Rt)); + MCOperand_CreateReg0(Inst, (Base)); + MCOperand_CreateImm0(Inst, (Offset)); return MCDisassembler_Success; } -static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { // Currently only hardware register 29 is supported. if (RegNo != 29) - return MCDisassembler_Fail; - - MCOperand_CreateReg0(Inst, Mips_HWR29); - + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, (Mips_HWR29)); return MCDisassembler_Success; } -static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 30 || RegNo % 2) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_AFGR64RegClassID, RegNo /2); - MCOperand_CreateReg0(Inst, Reg); - + unsigned Reg = getReg(Inst, Mips_AFGR64RegClassID, RegNo / 2); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo >= 4) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_ACC64DSPRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); + unsigned Reg = getReg(Inst, Mips_ACC64DSPRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo >= 4) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_HI32DSPRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - + unsigned Reg = getReg(Inst, Mips_HI32DSPRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo >= 4) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_LO32DSPRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - + unsigned Reg = getReg(Inst, Mips_LO32DSPRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 31) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_MSA128BRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - + unsigned Reg = getReg(Inst, Mips_MSA128BRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 31) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_MSA128HRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - + unsigned Reg = getReg(Inst, Mips_MSA128HRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 31) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_MSA128WRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - + unsigned Reg = getReg(Inst, Mips_MSA128WRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 31) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_MSA128DRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - + unsigned Reg = getReg(Inst, Mips_MSA128DRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 7) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_MSACtrlRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - + unsigned Reg = getReg(Inst, Mips_MSACtrlRegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeCOP0RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - unsigned Reg; - if (RegNo > 31) return MCDisassembler_Fail; - Reg = getReg(Decoder, Mips_COP2RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - + unsigned Reg = getReg(Inst, Mips_COP0RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeBranchTarget(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { - uint64_t TargetAddress = (SignExtend32(Offset, 16) * 4) + Address + 4; - MCOperand_CreateImm0(Inst, TargetAddress); + if (RegNo > 31) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst, Mips_COP2RegClassID, RegNo); + MCOperand_CreateReg0(Inst, (Reg)); return MCDisassembler_Success; } -static DecodeStatus DecodeJumpTarget(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeBranchTarget(MCInst *Inst, unsigned Offset, + uint64_t Address, const void *Decoder) { - uint64_t TargetAddress = (fieldFromInstruction(Insn, 0, 26) << 2) | ((Address + 4) & ~0x0FFFFFFF); - MCOperand_CreateImm0(Inst, TargetAddress); + int32_t BranchOffset = (SignExtend32((Offset), 16) * 4) + 4; + MCOperand_CreateImm0(Inst, (BranchOffset)); + return MCDisassembler_Success; +} +static DecodeStatus DecodeBranchTarget1SImm16(MCInst *Inst, unsigned Offset, + uint64_t Address, + const void *Decoder) +{ + int32_t BranchOffset = (SignExtend32((Offset), 16) * 2); + MCOperand_CreateImm0(Inst, (BranchOffset)); return MCDisassembler_Success; } -static DecodeStatus DecodeBranchTarget21(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeJumpTarget(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - int32_t BranchOffset = SignExtend32(Offset, 21) * 4; + unsigned JumpOffset = fieldFromInstruction_4(Insn, 0, 26) << 2; + MCOperand_CreateImm0(Inst, (JumpOffset)); + return MCDisassembler_Success; +} - MCOperand_CreateImm0(Inst, BranchOffset); +static DecodeStatus DecodeBranchTarget21(MCInst *Inst, unsigned Offset, + uint64_t Address, const void *Decoder) +{ + int32_t BranchOffset = SignExtend32((Offset), 21) * 4 + 4; + MCOperand_CreateImm0(Inst, (BranchOffset)); return MCDisassembler_Success; } -static DecodeStatus DecodeBranchTarget26(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeBranchTarget21MM(MCInst *Inst, unsigned Offset, + uint64_t Address, + const void *Decoder) { - int32_t BranchOffset = SignExtend32(Offset, 26) * 4; + int32_t BranchOffset = SignExtend32((Offset), 21) * 4 + 4; - MCOperand_CreateImm0(Inst, BranchOffset); + MCOperand_CreateImm0(Inst, (BranchOffset)); return MCDisassembler_Success; } -static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, - unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeBranchTarget26(MCInst *Inst, unsigned Offset, + uint64_t Address, const void *Decoder) { - int32_t BranchOffset = SignExtend32(Offset, 7) * 2; - MCOperand_CreateImm0(Inst, BranchOffset); + int32_t BranchOffset = SignExtend32((Offset), 26) * 4 + 4; + + MCOperand_CreateImm0(Inst, (BranchOffset)); return MCDisassembler_Success; } -static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, - unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, unsigned Offset, + uint64_t Address, const void *Decoder) { - int32_t BranchOffset = SignExtend32(Offset, 10) * 2; - MCOperand_CreateImm0(Inst, BranchOffset); + int32_t BranchOffset = SignExtend32((Offset << 1), 8); + MCOperand_CreateImm0(Inst, (BranchOffset)); return MCDisassembler_Success; } -static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, unsigned Offset, + uint64_t Address, + const void *Decoder) { - int32_t BranchOffset = SignExtend32(Offset, 16) * 2; - MCOperand_CreateImm0(Inst, BranchOffset); + int32_t BranchOffset = SignExtend32((Offset << 1), 11); + MCOperand_CreateImm0(Inst, (BranchOffset)); + return MCDisassembler_Success; +} +static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, unsigned Offset, + uint64_t Address, const void *Decoder) +{ + int32_t BranchOffset = SignExtend32((Offset), 16) * 2 + 4; + MCOperand_CreateImm0(Inst, (BranchOffset)); return MCDisassembler_Success; } -static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeBranchTarget26MM(MCInst *Inst, unsigned Offset, + uint64_t Address, + const void *Decoder) { - unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; - MCOperand_CreateImm0(Inst, JumpOffset); + int32_t BranchOffset = SignExtend32((Offset << 1), 27); + MCOperand_CreateImm0(Inst, (BranchOffset)); return MCDisassembler_Success; } -static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - if (Value == 0) - MCOperand_CreateImm0(Inst, 1); - else if (Value == 0x7) - MCOperand_CreateImm0(Inst, -1); - else - MCOperand_CreateImm0(Inst, Value << 2); - + unsigned JumpOffset = fieldFromInstruction_4(Insn, 0, 26) << 1; + MCOperand_CreateImm0(Inst, (JumpOffset)); return MCDisassembler_Success; } -static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) +#define DEFINE_DecodeBranchTargetNM(Bits) \ + static DecodeStatus CONCAT(DecodeBranchTargetNM, Bits)( \ + MCInst * Inst, unsigned Offset, uint64_t Address, \ + const void *Decoder) \ + { \ + uint32_t InsnSize = (Bits <= 10) ? 2 : 4; \ + int32_t BranchOffset = \ + SignExtend32((Offset), Bits + 1) + InsnSize; \ +\ + MCOperand_CreateImm0(Inst, (BranchOffset)); \ + return MCDisassembler_Success; \ + } +DEFINE_DecodeBranchTargetNM(10); +DEFINE_DecodeBranchTargetNM(7); +DEFINE_DecodeBranchTargetNM(21); +DEFINE_DecodeBranchTargetNM(25); +DEFINE_DecodeBranchTargetNM(14); +DEFINE_DecodeBranchTargetNM(11); +DEFINE_DecodeBranchTargetNM(5); + +static DecodeStatus DecodeJumpTargetXMM(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - MCOperand_CreateImm0(Inst, Value << 2); + unsigned JumpOffset = fieldFromInstruction_4(Insn, 0, 26) << 2; + MCOperand_CreateImm0(Inst, (JumpOffset)); + return MCDisassembler_Success; +} +static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder) +{ + if (Value == 0) + MCOperand_CreateImm0(Inst, (1)); + else if (Value == 0x7) + MCOperand_CreateImm0(Inst, (-1)); + else + MCOperand_CreateImm0(Inst, (Value << 2)); return MCDisassembler_Success; } -static DecodeStatus DecodeLiSimm7(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeLi16Imm(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder) { if (Value == 0x7F) - MCOperand_CreateImm0(Inst, -1); + MCOperand_CreateImm0(Inst, (-1)); else - MCOperand_CreateImm0(Inst, Value); - + MCOperand_CreateImm0(Inst, (Value)); return MCDisassembler_Success; } -static DecodeStatus DecodeSimm4(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodePOOL16BEncodedField(MCInst *Inst, unsigned Value, + uint64_t Address, + const void *Decoder) { - MCOperand_CreateImm0(Inst, SignExtend32(Value, 4)); - + MCOperand_CreateImm0(Inst, (Value == 0x0 ? 8 : Value)); return MCDisassembler_Success; } -static DecodeStatus DecodeSimm16(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +#define DEFINE_DecodeUImmWithOffsetAndScale(Bits, Offset, Scale) \ + static DecodeStatus CONCAT(DecodeUImmWithOffsetAndScale, \ + CONCAT(Bits, CONCAT(Offset, Scale)))( \ + MCInst * Inst, unsigned Value, uint64_t Address, \ + const void *Decoder) \ + { \ + Value &= ((1 << Bits) - 1); \ + Value *= Scale; \ + MCOperand_CreateImm0(Inst, (Value + Offset)); \ + return MCDisassembler_Success; \ + } +DEFINE_DecodeUImmWithOffsetAndScale(5, 0, 4); +DEFINE_DecodeUImmWithOffsetAndScale(6, 0, 4); +DEFINE_DecodeUImmWithOffsetAndScale(2, 1, 1); +DEFINE_DecodeUImmWithOffsetAndScale(5, 1, 1); +DEFINE_DecodeUImmWithOffsetAndScale(8, 0, 1); +DEFINE_DecodeUImmWithOffsetAndScale(18, 0, 1); +DEFINE_DecodeUImmWithOffsetAndScale(21, 0, 1); + +#define DEFINE_DecodeSImmWithOffsetAndScale(Bits, Offset, ScaleBy) \ + static DecodeStatus CONCAT(DecodeSImmWithOffsetAndScale, \ + CONCAT(Bits, CONCAT(Offset, ScaleBy)))( \ + MCInst * Inst, unsigned Value, uint64_t Address, \ + const void *Decoder) \ + { \ + int32_t Imm = SignExtend32((Value), Bits) * ScaleBy; \ + MCOperand_CreateImm0(Inst, (Imm + Offset)); \ + return MCDisassembler_Success; \ + } + +#define DEFINE_DecodeSImmWithOffsetAndScale_2(Bits, Offset) DEFINE_DecodeSImmWithOffsetAndScale(Bits, Offset, 1) +#define DEFINE_DecodeSImmWithOffsetAndScale_3(Bits) DEFINE_DecodeSImmWithOffsetAndScale(Bits, 0, 1) + +DEFINE_DecodeSImmWithOffsetAndScale_3(16); +DEFINE_DecodeSImmWithOffsetAndScale_3(10); +DEFINE_DecodeSImmWithOffsetAndScale_3(4); +DEFINE_DecodeSImmWithOffsetAndScale_3(6); +DEFINE_DecodeSImmWithOffsetAndScale_3(32); + +static DecodeStatus DecodeInsSize(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) { - MCOperand_CreateImm0(Inst, SignExtend32(Insn, 16)); + // First we need to grab the pos(lsb) from MCInst. + // This function only handles the 32 bit variants of ins, as dins + // variants are handled differently. + int Pos = MCOperand_getImm(MCInst_getOperand(Inst, (2))); + int Size = (int)Insn - Pos + 1; + MCOperand_CreateImm0(Inst, (SignExtend32((Size), 16))); + return MCDisassembler_Success; +} +static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateImm0(Inst, (SignExtend32((Insn), 19) * 4)); return MCDisassembler_Success; } -static DecodeStatus DecodeLSAImm(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - // We add one to the immediate field as it was encoded as 'imm - 1'. - MCOperand_CreateImm0(Inst, Insn + 1); + MCOperand_CreateImm0(Inst, (SignExtend32((Insn), 18) * 8)); + return MCDisassembler_Success; +} +static DecodeStatus DecodeSimm9SP(MCInst *Inst, uint32_t Insn, uint64_t Address, + const void *Decoder) +{ + int32_t DecodedValue; + switch (Insn) { + case 0: + DecodedValue = 256; + break; + case 1: + DecodedValue = 257; + break; + case 510: + DecodedValue = -258; + break; + case 511: + DecodedValue = -257; + break; + default: + DecodedValue = SignExtend32((Insn), 9); + break; + } + MCOperand_CreateImm0(Inst, (DecodedValue * 4)); return MCDisassembler_Success; } -static DecodeStatus DecodeInsSize(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeANDI16Imm(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - // First we need to grab the pos(lsb) from MCInst. - int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2)); - int Size = (int) Insn - Pos + 1; - MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); + // Insn must be >= 0, since it is unsigned that condition is always true. + int32_t DecodedValues[] = { 128, 1, 2, 3, 4, 7, 8, 15, + 16, 31, 32, 63, 64, 255, 32768, 65535 }; + MCOperand_CreateImm0(Inst, (DecodedValues[Insn])); return MCDisassembler_Success; } -static DecodeStatus DecodeExtSize(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeRegListOperand(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - int Size = (int)Insn + 1; + unsigned Regs[] = { Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, + Mips_S5, Mips_S6, Mips_S7, Mips_FP }; + unsigned RegNum; + + unsigned RegLst = fieldFromInstruction_4(Insn, 21, 5); + + // Empty register lists are not allowed. + if (RegLst == 0) + return MCDisassembler_Fail; - MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); + RegNum = RegLst & 0xf; + + // RegLst values 10-15, and 26-31 are reserved. + if (RegNum > 9) + return MCDisassembler_Fail; + + for (unsigned i = 0; i < RegNum; i++) + MCOperand_CreateReg0(Inst, (Regs[i])); + + if (RegLst & 0x10) + MCOperand_CreateReg0(Inst, (Mips_RA)); return MCDisassembler_Success; } -static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeRegListOperand16(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder) { - MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) * 4); + unsigned Regs[] = { Mips_S0, Mips_S1, Mips_S2, Mips_S3 }; + unsigned RegLst; + switch (MCInst_getOpcode(Inst)) { + default: + RegLst = fieldFromInstruction_4(Insn, 4, 2); + break; + case Mips_LWM16_MMR6: + case Mips_SWM16_MMR6: + RegLst = fieldFromInstruction_4(Insn, 8, 2); + break; + } + unsigned RegNum = RegLst & 0x3; + + for (unsigned i = 0; i <= RegNum; i++) + MCOperand_CreateReg0(Inst, (Regs[i])); + + MCOperand_CreateReg0(Inst, (Mips_RA)); return MCDisassembler_Success; } -static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeMovePOperands(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) * 8); + unsigned RegPair = fieldFromInstruction_4(Insn, 7, 3); + if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + + unsigned RegRs; + if (Inst->csh->mode & CS_MODE_MIPS32R6) + RegRs = fieldFromInstruction_4(Insn, 0, 2) | + (fieldFromInstruction_4(Insn, 3, 1) << 2); + else + RegRs = fieldFromInstruction_4(Insn, 1, 3); + if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + + unsigned RegRt = fieldFromInstruction_4(Insn, 4, 3); + if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; return MCDisassembler_Success; } -static DecodeStatus DecodeSimm9SP(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned RegPair, + uint64_t Address, const void *Decoder) { - int32_t DecodedValue; - - switch (Insn) { - case 0: DecodedValue = 256; break; - case 1: DecodedValue = 257; break; - case 510: DecodedValue = -258; break; - case 511: DecodedValue = -257; break; - default: DecodedValue = SignExtend32(Insn, 9); break; + switch (RegPair) { + default: + return MCDisassembler_Fail; + case 0: + MCOperand_CreateReg0(Inst, (Mips_A1)); + MCOperand_CreateReg0(Inst, (Mips_A2)); + break; + case 1: + MCOperand_CreateReg0(Inst, (Mips_A1)); + MCOperand_CreateReg0(Inst, (Mips_A3)); + break; + case 2: + MCOperand_CreateReg0(Inst, (Mips_A2)); + MCOperand_CreateReg0(Inst, (Mips_A3)); + break; + case 3: + MCOperand_CreateReg0(Inst, (Mips_A0)); + MCOperand_CreateReg0(Inst, (Mips_S5)); + break; + case 4: + MCOperand_CreateReg0(Inst, (Mips_A0)); + MCOperand_CreateReg0(Inst, (Mips_S6)); + break; + case 5: + MCOperand_CreateReg0(Inst, (Mips_A0)); + MCOperand_CreateReg0(Inst, (Mips_A1)); + break; + case 6: + MCOperand_CreateReg0(Inst, (Mips_A0)); + MCOperand_CreateReg0(Inst, (Mips_A2)); + break; + case 7: + MCOperand_CreateReg0(Inst, (Mips_A0)); + MCOperand_CreateReg0(Inst, (Mips_A3)); + break; } - MCOperand_CreateImm0(Inst, DecodedValue * 4); return MCDisassembler_Success; } -static DecodeStatus DecodeANDI16Imm(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - // Insn must be >= 0, since it is unsigned that condition is always true. - // assert(Insn < 16); - int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, - 255, 32768, 65535}; + MCOperand_CreateImm0(Inst, (SignExtend32((Insn << 2), 25))); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder) +{ + // We have: + // 0b000111 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BGTZALC_MMR6 if rs == 0 && rt != 0 + // BLTZALC_MMR6 if rs != 0 && rs == rt + // BLTUC_MMR6 if rs != 0 && rs != rt + + uint32_t Rt = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); + uint32_t Imm = 0; + bool HasRs = false; + bool HasRt = false; - if (Insn >= 16) + if (Rt == 0) return MCDisassembler_Fail; + else if (Rs == 0) { + MCInst_setOpcode(MI, (Mips_BGTZALC_MMR6)); + HasRt = true; + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 2 + + 4; + } else if (Rs == Rt) { + MCInst_setOpcode(MI, (Mips_BLTZALC_MMR6)); + HasRs = true; + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 2 + + 4; + } else { + MCInst_setOpcode(MI, (Mips_BLTUC_MMR6)); + HasRs = true; + HasRt = true; + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 4 + + 4; + } - MCOperand_CreateImm0(Inst, DecodedValues[Insn]); + if (HasRs) + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); - return MCDisassembler_Success; -} + if (HasRt) + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); -static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, Insn << 2); + MCOperand_CreateImm0(MI, (Imm)); return MCDisassembler_Success; } -static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Insn, - uint64_t Address, const MCRegisterInfo *Decoder) +static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst *MI, uint32_t insn, + uint64_t Address, + const void *Decoder) { - unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, - Mips_S6, Mips_FP}; - unsigned RegNum; - unsigned int i; + // We have: + // 0b000110 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BLEZALC_MMR6 if rs == 0 && rt != 0 + // BGEZALC_MMR6 if rs == rt && rt != 0 + // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 + + uint32_t Rt = fieldFromInstruction_4(insn, 21, 5); + uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); + uint32_t Imm = 0; + bool HasRs = false; - unsigned RegLst = fieldFromInstruction(Insn, 21, 5); - // Empty register lists are not allowed. - if (RegLst == 0) + if (Rt == 0) return MCDisassembler_Fail; + else if (Rs == 0) { + MCInst_setOpcode(MI, (Mips_BLEZALC_MMR6)); + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 2 + + 4; + } else if (Rs == Rt) { + MCInst_setOpcode(MI, (Mips_BGEZALC_MMR6)); + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 2 + + 4; + } else { + HasRs = true; + MCInst_setOpcode(MI, (Mips_BGEUC_MMR6)); + Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * + 4 + + 4; + } - RegNum = RegLst & 0xf; - for (i = 0; i < MIN(RegNum, ARR_SIZE(Regs)); i++) - MCOperand_CreateReg0(Inst, Regs[i]); + if (HasRs) + MCOperand_CreateReg0( + MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); + MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); - if (RegLst & 0x10) - MCOperand_CreateReg0(Inst, Mips_RA); + MCOperand_CreateImm0(MI, (Imm)); return MCDisassembler_Success; } -static DecodeStatus DecodeRegListOperand16(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) +// This instruction does not have a working decoder, and needs to be +// fixed. This "fixme" function was introduced to keep the backend compiling, +// while making changes to tablegen code. +static DecodeStatus DecodeFIXMEInstruction(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder) { - unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3}; - unsigned RegLst = fieldFromInstruction(Insn, 4, 2); - unsigned RegNum = RegLst & 0x3; - unsigned int i; + return MCDisassembler_Fail; +} - for (i = 0; i <= RegNum; i++) - MCOperand_CreateReg0(Inst, Regs[i]); +static DecodeStatus DecodeImmM1To126(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder) +{ + if (Value == 127) + MCOperand_CreateImm0(Inst, (-1)); + else + MCOperand_CreateImm0(Inst, (Value)); + return MCDisassembler_Success; +} - MCOperand_CreateReg0(Inst, Mips_RA); +static DecodeStatus DecodeUImm4Mask(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder) +{ + if (Value == 12) + MCOperand_CreateImm0(Inst, (0xff)); + else if (Value == 13) + MCOperand_CreateImm0(Inst, (0xffff)); + else + MCOperand_CreateImm0(Inst, (Value)); + return MCDisassembler_Success; +} +static DecodeStatus DecodeUImm3Shift(MCInst *Inst, unsigned Value, + uint64_t Address, const void *Decoder) +{ + if (Value == 0) + MCOperand_CreateImm0(Inst, (8)); + else + MCOperand_CreateImm0(Inst, (Value)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeNMRegListOperand(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder) +{ + unsigned RegStart = fieldFromInstruction_4(Insn, 5, 5); + unsigned RegCount = fieldFromInstruction_4(Insn, 1, 4); + unsigned GP_bit = fieldFromInstruction_4(Insn, 0, 1); + unsigned i; + unsigned RegNo; + + MCOperand_CreateReg0( + Inst, (getReg(Inst, Mips_GPRNM32RegClassID, RegStart))); + for (i = RegStart + 1; i < RegStart + RegCount; i++) { + if (i == RegStart + RegCount - 1 && GP_bit) + RegNo = 28; + else if (i > 31) + RegNo = 16 + (i % 32); // $ra+1 wraps to $s0 + else + RegNo = i; + MCOperand_CreateReg0( + Inst, (getReg(Inst, Mips_GPRNM32RegClassID, RegNo))); + } return MCDisassembler_Success; } -static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) +static DecodeStatus DecodeNMRegList16Operand(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder) { - unsigned RegPair = fieldFromInstruction(Insn, 7, 3); + unsigned RegStart = 30 + fieldFromInstruction_4(Insn, 4, 1); + unsigned RegCount = fieldFromInstruction_4(Insn, 0, 4); + // Re-encode the parameters for 32-bit instruction operand + // and call it's decoder + return DecodeNMRegListOperand(Inst, (RegStart << 5) | (RegCount << 1), + Address, Decoder); +} - switch (RegPair) { - default: - return MCDisassembler_Fail; - case 0: - MCOperand_CreateReg0(Inst, Mips_A1); - MCOperand_CreateReg0(Inst, Mips_A2); - break; - case 1: - MCOperand_CreateReg0(Inst, Mips_A1); - MCOperand_CreateReg0(Inst, Mips_A3); - break; - case 2: - MCOperand_CreateReg0(Inst, Mips_A2); - MCOperand_CreateReg0(Inst, Mips_A3); - break; - case 3: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_S5); - break; - case 4: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_S6); - break; - case 5: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_A1); - break; - case 6: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_A2); - break; - case 7: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_A3); - break; - } +static DecodeStatus DecodeNegImm12(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + int Imm = fieldFromInstruction_4(Insn, 0, 12); + MCOperand_CreateImm0(Inst, (-Imm)); return MCDisassembler_Success; } -static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) +#define DEFINE_DecodeSImmWithReg(Bits, Offset, Scale, RegNum) \ + static DecodeStatus CONCAT( \ + DecodeSImmWithReg, \ + CONCAT(Bits, CONCAT(Offset, CONCAT(Scale, RegNum))))( \ + MCInst * Inst, unsigned Value, uint64_t Address, \ + const void *Decoder) \ + { \ + MCOperand_CreateReg0(Inst, (RegNum)); \ + return CONCAT(DecodeSImmWithOffsetAndScale, \ + CONCAT(Bits, CONCAT(Offset, Scale)))( \ + Inst, Value, Address, Decoder); \ + } +DEFINE_DecodeSImmWithReg(32, 0, 1, Mips_GP_NM); + +#define DEFINE_DecodeUImmWithReg(Bits, Offset, Scale, RegNum) \ + static DecodeStatus CONCAT( \ + DecodeUImmWithReg, \ + CONCAT(Bits, CONCAT(Offset, CONCAT(Scale, RegNum))))( \ + MCInst * Inst, unsigned Value, uint64_t Address, \ + const void *Decoder) \ + { \ + MCOperand_CreateReg0(Inst, (RegNum)); \ + return CONCAT(DecodeUImmWithOffsetAndScale, \ + CONCAT(Bits, CONCAT(Offset, Scale)))( \ + Inst, Value, Address, Decoder); \ + } +DEFINE_DecodeUImmWithReg(8, 0, 1, Mips_SP_NM); +DEFINE_DecodeUImmWithReg(21, 0, 1, Mips_GP_NM); +DEFINE_DecodeUImmWithReg(18, 0, 1, Mips_GP_NM); + +static DecodeStatus DecodeSImm32s12(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { - MCOperand_CreateImm0(Inst, SignExtend32(Insn, 23) * 4); + uint64_t Imm = (Insn) << 12; + MCOperand_CreateImm0(Inst, (Imm)); return MCDisassembler_Success; } -#endif +#define DEFINE_DecodeAddressPCRelNM(Bits) \ + static DecodeStatus CONCAT(DecodeAddressPCRelNM, Bits)( \ + MCInst * Inst, unsigned Offset, uint64_t Address, \ + const void *Decoder) \ + { \ + uint32_t InsnSize = Bits == 32 ? 6 : 4; \ + int32_t BranchOffset = \ + SignExtend32((Offset), Bits) + InsnSize; \ +\ + MCOperand_CreateImm0(Inst, (BranchOffset)); \ + return MCDisassembler_Success; \ + } +DEFINE_DecodeAddressPCRelNM(22); +DEFINE_DecodeAddressPCRelNM(32); + +static DecodeStatus DecodeBranchConflictNM(MCInst *Inst, uint32_t Insn, + uint64_t Address, + const void *Decoder) +{ + unsigned Rt = fieldFromInstruction_4(Insn, 7, 3); + unsigned Rs = fieldFromInstruction_4(Insn, 4, 3); + unsigned Offset = fieldFromInstruction_4(Insn, 0, 4) << 1; + if (Rs < Rt) + MCInst_setOpcode(Inst, (Mips_BEQC16_NM)); + else + MCInst_setOpcode(Inst, (Mips_BNEC16_NM)); + if (DecodeGPRNM3RegisterClass(Inst, Rt, Address, Decoder) == + MCDisassembler_Success && + DecodeGPRNM3RegisterClass(Inst, Rs, Address, Decoder) == + MCDisassembler_Success) + return CONCAT(DecodeBranchTargetNM, 5)(Inst, Offset, Address, + Decoder); + else + return MCDisassembler_Fail; +} + +DecodeStatus Mips_LLVM_getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t *Bytes, + size_t BytesLen, uint64_t Address, SStream *CStream) +{ + return getInstruction(Instr, Size, Bytes, BytesLen, Address, CStream); +} diff --git a/arch/Mips/MipsDisassembler.h b/arch/Mips/MipsDisassembler.h index 961c5f1ae8..3c9c2c8927 100644 --- a/arch/Mips/MipsDisassembler.h +++ b/arch/Mips/MipsDisassembler.h @@ -10,7 +10,6 @@ void Mips_init(MCRegisterInfo *MRI); -bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len, - MCInst *instr, uint16_t *size, uint64_t address, void *info); +bool Mips_getFeatureBits(unsigned int mode, unsigned int feature); #endif diff --git a/arch/Mips/MipsGenAsmWriter.inc b/arch/Mips/MipsGenAsmWriter.inc index 49fb8f5e18..45625228c5 100644 --- a/arch/Mips/MipsGenAsmWriter.inc +++ b/arch/Mips/MipsGenAsmWriter.inc @@ -1,1390 +1,1949 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|*Assembly Writer Source Fragment *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* LLVM-commit: */ +/* LLVM-tag: */ -/// printInstruction - This method is automatically generated by tablegen +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +#include +#include + +/// getMnemonic - This method is automatically generated by tablegen /// from the instruction set description. -static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) -{ - static const uint32_t OpInfo[] = { +static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) { +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ "ins \t\0" + /* 6 */ "dmfc0\t\0" + /* 13 */ "dmfgc0\t\0" + /* 21 */ "mfhgc0\t\0" + /* 29 */ "mthgc0\t\0" + /* 37 */ "dmtgc0\t\0" + /* 45 */ "mfhc0\t\0" + /* 52 */ "mthc0\t\0" + /* 59 */ "dmtc0\t\0" + /* 66 */ "vmm0\t\0" + /* 72 */ "mtm0\t\0" + /* 78 */ "mtp0\t\0" + /* 84 */ "bbit0\t\0" + /* 91 */ "ldc1\t\0" + /* 97 */ "sdc1\t\0" + /* 103 */ "cfc1\t\0" + /* 109 */ "dmfc1\t\0" + /* 116 */ "mfhc1\t\0" + /* 123 */ "mthc1\t\0" + /* 130 */ "ctc1\t\0" + /* 136 */ "dmtc1\t\0" + /* 143 */ "lwc1\t\0" + /* 149 */ "swc1\t\0" + /* 155 */ "ldxc1\t\0" + /* 162 */ "sdxc1\t\0" + /* 169 */ "luxc1\t\0" + /* 176 */ "suxc1\t\0" + /* 183 */ "lwxc1\t\0" + /* 190 */ "swxc1\t\0" + /* 197 */ "mtm1\t\0" + /* 203 */ "mtp1\t\0" + /* 209 */ "bbit1\t\0" + /* 216 */ "bbit032\t\0" + /* 225 */ "bbit132\t\0" + /* 234 */ "dsra32\t\0" + /* 242 */ "bposge32\t\0" + /* 252 */ "dsll32\t\0" + /* 260 */ "dsrl32\t\0" + /* 268 */ "lwm32\t\0" + /* 275 */ "swm32\t\0" + /* 282 */ "drotr32\t\0" + /* 291 */ "cins32\t\0" + /* 299 */ "exts32\t\0" + /* 307 */ "ldc2\t\0" + /* 313 */ "sdc2\t\0" + /* 319 */ "cfc2\t\0" + /* 325 */ "dmfc2\t\0" + /* 332 */ "mfhc2\t\0" + /* 339 */ "mthc2\t\0" + /* 346 */ "ctc2\t\0" + /* 352 */ "dmtc2\t\0" + /* 359 */ "lwc2\t\0" + /* 365 */ "swc2\t\0" + /* 371 */ "mtm2\t\0" + /* 377 */ "mtp2\t\0" + /* 383 */ "addiur2\t\0" + /* 392 */ "ldc3\t\0" + /* 398 */ "sdc3\t\0" + /* 404 */ "lwc3\t\0" + /* 410 */ "swc3\t\0" + /* 416 */ "addius5\t\0" + /* 425 */ "sb16\t\0" + /* 431 */ "bc16\t\0" + /* 437 */ "jrc16\t\0" + /* 444 */ "bnezc16\t\0" + /* 453 */ "beqzc16\t\0" + /* 462 */ "and16\t\0" + /* 469 */ "move16\t\0" + /* 477 */ "sh16\t\0" + /* 483 */ "andi16\t\0" + /* 491 */ "mfhi16\t\0" + /* 499 */ "li16\t\0" + /* 505 */ "break16\t\0" + /* 514 */ "sll16\t\0" + /* 521 */ "srl16\t\0" + /* 528 */ "lwm16\t\0" + /* 535 */ "swm16\t\0" + /* 542 */ "mflo16\t\0" + /* 550 */ "sdbbp16\t\0" + /* 559 */ "jr16\t\0" + /* 565 */ "xor16\t\0" + /* 572 */ "jalrs16\t\0" + /* 581 */ "not16\t\0" + /* 588 */ "lbu16\t\0" + /* 595 */ "subu16\t\0" + /* 603 */ "addu16\t\0" + /* 611 */ "lhu16\t\0" + /* 618 */ "lw16\t\0" + /* 624 */ "sw16\t\0" + /* 630 */ "bnez16\t\0" + /* 638 */ "beqz16\t\0" + /* 646 */ "andi[32]\t\0" + /* 656 */ "addiu[32]\t\0" + /* 667 */ "addiu[r2]\t\0" + /* 678 */ "addiu[rs5]\t\0" + /* 690 */ "balc[16]\t\0" + /* 700 */ "andi[16]\t\0" + /* 710 */ "li[48]\t\0" + /* 718 */ "addiu[48]\t\0" + /* 729 */ "addiu[gp48]\t\0" + /* 742 */ "addiu[gp.b]\t\0" + /* 755 */ "addiu[neg]\t\0" + /* 767 */ "addiu[r1.sp]\t\0" + /* 781 */ "addiu[gp.w]\t\0" + /* 794 */ "saa\t\0" + /* 799 */ "preceu.ph.qbla\t\0" + /* 815 */ "precequ.ph.qbla\t\0" + /* 832 */ "dla\t\0" + /* 837 */ "preceu.ph.qbra\t\0" + /* 853 */ "precequ.ph.qbra\t\0" + /* 870 */ "dsra\t\0" + /* 876 */ "dlsa\t\0" + /* 882 */ "cfcmsa\t\0" + /* 890 */ "ctcmsa\t\0" + /* 898 */ "add_a.b\t\0" + /* 907 */ "min_a.b\t\0" + /* 916 */ "adds_a.b\t\0" + /* 926 */ "max_a.b\t\0" + /* 935 */ "sra.b\t\0" + /* 942 */ "nloc.b\t\0" + /* 950 */ "lapc.b\t\0" + /* 958 */ "nlzc.b\t\0" + /* 966 */ "sld.b\t\0" + /* 973 */ "pckod.b\t\0" + /* 982 */ "ilvod.b\t\0" + /* 991 */ "insve.b\t\0" + /* 1000 */ "vshf.b\t\0" + /* 1008 */ "bneg.b\t\0" + /* 1016 */ "srai.b\t\0" + /* 1024 */ "sldi.b\t\0" + /* 1032 */ "andi.b\t\0" + /* 1040 */ "bnegi.b\t\0" + /* 1049 */ "bseli.b\t\0" + /* 1058 */ "slli.b\t\0" + /* 1066 */ "srli.b\t\0" + /* 1074 */ "binsli.b\t\0" + /* 1084 */ "ceqi.b\t\0" + /* 1092 */ "srari.b\t\0" + /* 1101 */ "bclri.b\t\0" + /* 1110 */ "srlri.b\t\0" + /* 1119 */ "nori.b\t\0" + /* 1127 */ "xori.b\t\0" + /* 1135 */ "binsri.b\t\0" + /* 1145 */ "splati.b\t\0" + /* 1155 */ "bseti.b\t\0" + /* 1164 */ "subvi.b\t\0" + /* 1173 */ "addvi.b\t\0" + /* 1182 */ "bmzi.b\t\0" + /* 1190 */ "bmnzi.b\t\0" + /* 1199 */ "fill.b\t\0" + /* 1207 */ "sll.b\t\0" + /* 1214 */ "srl.b\t\0" + /* 1221 */ "binsl.b\t\0" + /* 1230 */ "ilvl.b\t\0" + /* 1238 */ "ceq.b\t\0" + /* 1245 */ "srar.b\t\0" + /* 1253 */ "bclr.b\t\0" + /* 1261 */ "srlr.b\t\0" + /* 1269 */ "binsr.b\t\0" + /* 1278 */ "ilvr.b\t\0" + /* 1286 */ "asub_s.b\t\0" + /* 1296 */ "mod_s.b\t\0" + /* 1305 */ "cle_s.b\t\0" + /* 1314 */ "ave_s.b\t\0" + /* 1323 */ "clei_s.b\t\0" + /* 1333 */ "mini_s.b\t\0" + /* 1343 */ "clti_s.b\t\0" + /* 1353 */ "maxi_s.b\t\0" + /* 1363 */ "min_s.b\t\0" + /* 1372 */ "aver_s.b\t\0" + /* 1382 */ "subs_s.b\t\0" + /* 1392 */ "adds_s.b\t\0" + /* 1402 */ "sat_s.b\t\0" + /* 1411 */ "clt_s.b\t\0" + /* 1420 */ "subsuu_s.b\t\0" + /* 1432 */ "div_s.b\t\0" + /* 1441 */ "max_s.b\t\0" + /* 1450 */ "copy_s.b\t\0" + /* 1460 */ "splat.b\t\0" + /* 1469 */ "bset.b\t\0" + /* 1477 */ "pcnt.b\t\0" + /* 1485 */ "insert.b\t\0" + /* 1495 */ "st.b\t\0" + /* 1501 */ "asub_u.b\t\0" + /* 1511 */ "mod_u.b\t\0" + /* 1520 */ "cle_u.b\t\0" + /* 1529 */ "ave_u.b\t\0" + /* 1538 */ "clei_u.b\t\0" + /* 1548 */ "mini_u.b\t\0" + /* 1558 */ "clti_u.b\t\0" + /* 1568 */ "maxi_u.b\t\0" + /* 1578 */ "min_u.b\t\0" + /* 1587 */ "aver_u.b\t\0" + /* 1597 */ "subs_u.b\t\0" + /* 1607 */ "adds_u.b\t\0" + /* 1617 */ "subsus_u.b\t\0" + /* 1629 */ "sat_u.b\t\0" + /* 1638 */ "clt_u.b\t\0" + /* 1647 */ "div_u.b\t\0" + /* 1656 */ "max_u.b\t\0" + /* 1665 */ "copy_u.b\t\0" + /* 1675 */ "msubv.b\t\0" + /* 1684 */ "maddv.b\t\0" + /* 1693 */ "pckev.b\t\0" + /* 1702 */ "ilvev.b\t\0" + /* 1711 */ "mulv.b\t\0" + /* 1719 */ "bz.b\t\0" + /* 1725 */ "bnz.b\t\0" + /* 1732 */ "crc32b\t\0" + /* 1740 */ "crc32cb\t\0" + /* 1749 */ "seb\t\0" + /* 1754 */ "jalrc.hb\t\0" + /* 1764 */ "jr.hb\t\0" + /* 1771 */ "jalr.hb\t\0" + /* 1780 */ "lb\t\0" + /* 1784 */ "shra.qb\t\0" + /* 1793 */ "cmpgdu.le.qb\t\0" + /* 1807 */ "cmpgu.le.qb\t\0" + /* 1820 */ "cmpu.le.qb\t\0" + /* 1832 */ "subuh.qb\t\0" + /* 1842 */ "adduh.qb\t\0" + /* 1852 */ "pick.qb\t\0" + /* 1861 */ "shll.qb\t\0" + /* 1870 */ "repl.qb\t\0" + /* 1879 */ "shrl.qb\t\0" + /* 1888 */ "cmpgdu.eq.qb\t\0" + /* 1902 */ "cmpgu.eq.qb\t\0" + /* 1915 */ "cmpu.eq.qb\t\0" + /* 1927 */ "shra_r.qb\t\0" + /* 1938 */ "subuh_r.qb\t\0" + /* 1950 */ "adduh_r.qb\t\0" + /* 1962 */ "shrav_r.qb\t\0" + /* 1974 */ "absq_s.qb\t\0" + /* 1985 */ "subu_s.qb\t\0" + /* 1996 */ "addu_s.qb\t\0" + /* 2007 */ "cmpgdu.lt.qb\t\0" + /* 2021 */ "cmpgu.lt.qb\t\0" + /* 2034 */ "cmpu.lt.qb\t\0" + /* 2046 */ "subu.qb\t\0" + /* 2055 */ "addu.qb\t\0" + /* 2064 */ "shrav.qb\t\0" + /* 2074 */ "shllv.qb\t\0" + /* 2084 */ "replv.qb\t\0" + /* 2094 */ "shrlv.qb\t\0" + /* 2104 */ "raddu.w.qb\t\0" + /* 2116 */ "sb\t\0" + /* 2120 */ "modsub\t\0" + /* 2128 */ "msub\t\0" + /* 2134 */ "bposge32c\t\0" + /* 2145 */ "bc\t\0" + /* 2149 */ "bgec\t\0" + /* 2155 */ "bnec\t\0" + /* 2161 */ "bgeic\t\0" + /* 2168 */ "bneic\t\0" + /* 2175 */ "jic\t\0" + /* 2180 */ "beqic\t\0" + /* 2187 */ "bltic\t\0" + /* 2194 */ "move.balc\t\0" + /* 2205 */ "jialc\t\0" + /* 2212 */ "bgezalc\t\0" + /* 2221 */ "blezalc\t\0" + /* 2230 */ "bnezalc\t\0" + /* 2239 */ "beqzalc\t\0" + /* 2248 */ "bgtzalc\t\0" + /* 2257 */ "bltzalc\t\0" + /* 2266 */ "sync\t\0" + /* 2272 */ "ldpc\t\0" + /* 2278 */ "auipc\t\0" + /* 2285 */ "aluipc\t\0" + /* 2293 */ "addiupc\t\0" + /* 2302 */ "lwupc\t\0" + /* 2309 */ "lwpc\t\0" + /* 2315 */ "swpc\t\0" + /* 2321 */ "beqc\t\0" + /* 2327 */ "restore.jrc\t\0" + /* 2340 */ "jalrc\t\0" + /* 2347 */ "addsc\t\0" + /* 2354 */ "brsc\t\0" + /* 2360 */ "balrsc\t\0" + /* 2368 */ "bltc\t\0" + /* 2374 */ "bgeuc\t\0" + /* 2381 */ "bgeiuc\t\0" + /* 2389 */ "bltiuc\t\0" + /* 2397 */ "bltuc\t\0" + /* 2404 */ "bnvc\t\0" + /* 2410 */ "bovc\t\0" + /* 2416 */ "addwc\t\0" + /* 2423 */ "bgezc\t\0" + /* 2430 */ "blezc\t\0" + /* 2437 */ "bc1nezc\t\0" + /* 2446 */ "bc2nezc\t\0" + /* 2455 */ "bbnezc\t\0" + /* 2463 */ "bc1eqzc\t\0" + /* 2472 */ "bc2eqzc\t\0" + /* 2481 */ "bbeqzc\t\0" + /* 2489 */ "bgtzc\t\0" + /* 2496 */ "bltzc\t\0" + /* 2503 */ "flog2.d\t\0" + /* 2512 */ "fexp2.d\t\0" + /* 2521 */ "add_a.d\t\0" + /* 2530 */ "fmin_a.d\t\0" + /* 2540 */ "adds_a.d\t\0" + /* 2550 */ "fmax_a.d\t\0" + /* 2560 */ "mina.d\t\0" + /* 2568 */ "sra.d\t\0" + /* 2575 */ "maxa.d\t\0" + /* 2583 */ "fsub.d\t\0" + /* 2591 */ "fmsub.d\t\0" + /* 2600 */ "nmsub.d\t\0" + /* 2609 */ "nloc.d\t\0" + /* 2617 */ "nlzc.d\t\0" + /* 2625 */ "fadd.d\t\0" + /* 2633 */ "fmadd.d\t\0" + /* 2642 */ "nmadd.d\t\0" + /* 2651 */ "sld.d\t\0" + /* 2658 */ "pckod.d\t\0" + /* 2667 */ "ilvod.d\t\0" + /* 2676 */ "c.nge.d\t\0" + /* 2685 */ "c.le.d\t\0" + /* 2693 */ "cmp.le.d\t\0" + /* 2703 */ "fcle.d\t\0" + /* 2711 */ "c.ngle.d\t\0" + /* 2721 */ "c.ole.d\t\0" + /* 2730 */ "cmp.sle.d\t\0" + /* 2741 */ "fsle.d\t\0" + /* 2749 */ "c.ule.d\t\0" + /* 2758 */ "cmp.ule.d\t\0" + /* 2769 */ "fcule.d\t\0" + /* 2778 */ "cmp.sule.d\t\0" + /* 2790 */ "fsule.d\t\0" + /* 2799 */ "fcne.d\t\0" + /* 2807 */ "fsne.d\t\0" + /* 2815 */ "fcune.d\t\0" + /* 2824 */ "fsune.d\t\0" + /* 2833 */ "insve.d\t\0" + /* 2842 */ "c.f.d\t\0" + /* 2849 */ "cmp.af.d\t\0" + /* 2859 */ "fcaf.d\t\0" + /* 2867 */ "cmp.saf.d\t\0" + /* 2878 */ "fsaf.d\t\0" + /* 2886 */ "msubf.d\t\0" + /* 2895 */ "maddf.d\t\0" + /* 2904 */ "vshf.d\t\0" + /* 2912 */ "c.sf.d\t\0" + /* 2920 */ "movf.d\t\0" + /* 2928 */ "bneg.d\t\0" + /* 2936 */ "srai.d\t\0" + /* 2944 */ "sldi.d\t\0" + /* 2952 */ "bnegi.d\t\0" + /* 2961 */ "slli.d\t\0" + /* 2969 */ "srli.d\t\0" + /* 2977 */ "binsli.d\t\0" + /* 2987 */ "ceqi.d\t\0" + /* 2995 */ "srari.d\t\0" + /* 3004 */ "bclri.d\t\0" + /* 3013 */ "srlri.d\t\0" + /* 3022 */ "binsri.d\t\0" + /* 3032 */ "splati.d\t\0" + /* 3042 */ "bseti.d\t\0" + /* 3051 */ "subvi.d\t\0" + /* 3060 */ "addvi.d\t\0" + /* 3069 */ "trunc.l.d\t\0" + /* 3080 */ "round.l.d\t\0" + /* 3091 */ "ceil.l.d\t\0" + /* 3101 */ "floor.l.d\t\0" + /* 3112 */ "cvt.l.d\t\0" + /* 3121 */ "sel.d\t\0" + /* 3128 */ "c.ngl.d\t\0" + /* 3137 */ "fill.d\t\0" + /* 3145 */ "sll.d\t\0" + /* 3152 */ "fexupl.d\t\0" + /* 3162 */ "ffql.d\t\0" + /* 3170 */ "srl.d\t\0" + /* 3177 */ "binsl.d\t\0" + /* 3186 */ "fmul.d\t\0" + /* 3194 */ "ilvl.d\t\0" + /* 3202 */ "fmin.d\t\0" + /* 3210 */ "c.un.d\t\0" + /* 3218 */ "cmp.un.d\t\0" + /* 3228 */ "fcun.d\t\0" + /* 3236 */ "cmp.sun.d\t\0" + /* 3247 */ "fsun.d\t\0" + /* 3255 */ "movn.d\t\0" + /* 3263 */ "frcp.d\t\0" + /* 3271 */ "recip.d\t\0" + /* 3280 */ "c.eq.d\t\0" + /* 3288 */ "cmp.eq.d\t\0" + /* 3298 */ "fceq.d\t\0" + /* 3306 */ "c.seq.d\t\0" + /* 3315 */ "cmp.seq.d\t\0" + /* 3326 */ "fseq.d\t\0" + /* 3334 */ "c.ueq.d\t\0" + /* 3343 */ "cmp.ueq.d\t\0" + /* 3354 */ "fcueq.d\t\0" + /* 3363 */ "cmp.sueq.d\t\0" + /* 3375 */ "fsueq.d\t\0" + /* 3384 */ "srar.d\t\0" + /* 3392 */ "bclr.d\t\0" + /* 3400 */ "srlr.d\t\0" + /* 3408 */ "fcor.d\t\0" + /* 3416 */ "fsor.d\t\0" + /* 3424 */ "fexupr.d\t\0" + /* 3434 */ "ffqr.d\t\0" + /* 3442 */ "binsr.d\t\0" + /* 3451 */ "ilvr.d\t\0" + /* 3459 */ "cvt.s.d\t\0" + /* 3468 */ "asub_s.d\t\0" + /* 3478 */ "hsub_s.d\t\0" + /* 3488 */ "dpsub_s.d\t\0" + /* 3499 */ "ftrunc_s.d\t\0" + /* 3511 */ "hadd_s.d\t\0" + /* 3521 */ "dpadd_s.d\t\0" + /* 3532 */ "mod_s.d\t\0" + /* 3541 */ "cle_s.d\t\0" + /* 3550 */ "ave_s.d\t\0" + /* 3559 */ "clei_s.d\t\0" + /* 3569 */ "mini_s.d\t\0" + /* 3579 */ "clti_s.d\t\0" + /* 3589 */ "maxi_s.d\t\0" + /* 3599 */ "min_s.d\t\0" + /* 3608 */ "dotp_s.d\t\0" + /* 3618 */ "aver_s.d\t\0" + /* 3628 */ "subs_s.d\t\0" + /* 3638 */ "adds_s.d\t\0" + /* 3648 */ "sat_s.d\t\0" + /* 3657 */ "clt_s.d\t\0" + /* 3666 */ "ffint_s.d\t\0" + /* 3677 */ "ftint_s.d\t\0" + /* 3688 */ "subsuu_s.d\t\0" + /* 3700 */ "div_s.d\t\0" + /* 3709 */ "max_s.d\t\0" + /* 3718 */ "copy_s.d\t\0" + /* 3728 */ "abs.d\t\0" + /* 3735 */ "fclass.d\t\0" + /* 3745 */ "splat.d\t\0" + /* 3754 */ "bset.d\t\0" + /* 3762 */ "c.ngt.d\t\0" + /* 3771 */ "c.lt.d\t\0" + /* 3779 */ "cmp.lt.d\t\0" + /* 3789 */ "fclt.d\t\0" + /* 3797 */ "c.olt.d\t\0" + /* 3806 */ "cmp.slt.d\t\0" + /* 3817 */ "fslt.d\t\0" + /* 3825 */ "c.ult.d\t\0" + /* 3834 */ "cmp.ult.d\t\0" + /* 3845 */ "fcult.d\t\0" + /* 3854 */ "cmp.sult.d\t\0" + /* 3866 */ "fsult.d\t\0" + /* 3875 */ "pcnt.d\t\0" + /* 3883 */ "frint.d\t\0" + /* 3892 */ "insert.d\t\0" + /* 3902 */ "fsqrt.d\t\0" + /* 3911 */ "frsqrt.d\t\0" + /* 3921 */ "st.d\t\0" + /* 3927 */ "movt.d\t\0" + /* 3935 */ "asub_u.d\t\0" + /* 3945 */ "hsub_u.d\t\0" + /* 3955 */ "dpsub_u.d\t\0" + /* 3966 */ "ftrunc_u.d\t\0" + /* 3978 */ "hadd_u.d\t\0" + /* 3988 */ "dpadd_u.d\t\0" + /* 3999 */ "mod_u.d\t\0" + /* 4008 */ "cle_u.d\t\0" + /* 4017 */ "ave_u.d\t\0" + /* 4026 */ "clei_u.d\t\0" + /* 4036 */ "mini_u.d\t\0" + /* 4046 */ "clti_u.d\t\0" + /* 4056 */ "maxi_u.d\t\0" + /* 4066 */ "min_u.d\t\0" + /* 4075 */ "dotp_u.d\t\0" + /* 4085 */ "aver_u.d\t\0" + /* 4095 */ "subs_u.d\t\0" + /* 4105 */ "adds_u.d\t\0" + /* 4115 */ "subsus_u.d\t\0" + /* 4127 */ "sat_u.d\t\0" + /* 4136 */ "clt_u.d\t\0" + /* 4145 */ "ffint_u.d\t\0" + /* 4156 */ "ftint_u.d\t\0" + /* 4167 */ "div_u.d\t\0" + /* 4176 */ "max_u.d\t\0" + /* 4185 */ "msubv.d\t\0" + /* 4194 */ "maddv.d\t\0" + /* 4203 */ "pckev.d\t\0" + /* 4212 */ "ilvev.d\t\0" + /* 4221 */ "fdiv.d\t\0" + /* 4229 */ "mulv.d\t\0" + /* 4237 */ "mov.d\t\0" + /* 4244 */ "trunc.w.d\t\0" + /* 4255 */ "round.w.d\t\0" + /* 4266 */ "ceil.w.d\t\0" + /* 4276 */ "floor.w.d\t\0" + /* 4287 */ "cvt.w.d\t\0" + /* 4296 */ "fmax.d\t\0" + /* 4304 */ "bz.d\t\0" + /* 4310 */ "selnez.d\t\0" + /* 4320 */ "bnz.d\t\0" + /* 4327 */ "seleqz.d\t\0" + /* 4337 */ "movz.d\t\0" + /* 4345 */ "crc32d\t\0" + /* 4353 */ "saad\t\0" + /* 4359 */ "crc32cd\t\0" + /* 4368 */ "scd\t\0" + /* 4373 */ "dadd\t\0" + /* 4379 */ "madd\t\0" + /* 4385 */ "dshd\t\0" + /* 4391 */ "yield\t\0" + /* 4398 */ "lld\t\0" + /* 4403 */ "and\t\0" + /* 4408 */ "prepend\t\0" + /* 4417 */ "append\t\0" + /* 4425 */ "dmod\t\0" + /* 4431 */ "sd\t\0" + /* 4435 */ "lbe\t\0" + /* 4440 */ "sbe\t\0" + /* 4445 */ "sce\t\0" + /* 4450 */ "cachee\t\0" + /* 4458 */ "prefe\t\0" + /* 4465 */ "bge\t\0" + /* 4470 */ "sge\t\0" + /* 4475 */ "tge\t\0" + /* 4480 */ "cache\t\0" + /* 4487 */ "lhe\t\0" + /* 4492 */ "she\t\0" + /* 4497 */ "sigrie\t\0" + /* 4505 */ "ble\t\0" + /* 4510 */ "lle\t\0" + /* 4515 */ "sle\t\0" + /* 4520 */ "lwle\t\0" + /* 4526 */ "swle\t\0" + /* 4532 */ "bne\t\0" + /* 4537 */ "sne\t\0" + /* 4542 */ "tne\t\0" + /* 4547 */ "dvpe\t\0" + /* 4553 */ "evpe\t\0" + /* 4559 */ "restore\t\0" + /* 4568 */ "lwre\t\0" + /* 4574 */ "swre\t\0" + /* 4580 */ "lbue\t\0" + /* 4586 */ "lhue\t\0" + /* 4592 */ "save\t\0" + /* 4598 */ "move\t\0" + /* 4604 */ "lwe\t\0" + /* 4609 */ "swe\t\0" + /* 4614 */ "bc1f\t\0" + /* 4620 */ "pref\t\0" + /* 4626 */ "movf\t\0" + /* 4632 */ "neg\t\0" + /* 4637 */ "add_a.h\t\0" + /* 4646 */ "min_a.h\t\0" + /* 4655 */ "adds_a.h\t\0" + /* 4665 */ "max_a.h\t\0" + /* 4674 */ "sra.h\t\0" + /* 4681 */ "nloc.h\t\0" + /* 4689 */ "lapc.h\t\0" + /* 4697 */ "nlzc.h\t\0" + /* 4705 */ "sld.h\t\0" + /* 4712 */ "pckod.h\t\0" + /* 4721 */ "ilvod.h\t\0" + /* 4730 */ "insve.h\t\0" + /* 4739 */ "vshf.h\t\0" + /* 4747 */ "bneg.h\t\0" + /* 4755 */ "srai.h\t\0" + /* 4763 */ "sldi.h\t\0" + /* 4771 */ "bnegi.h\t\0" + /* 4780 */ "slli.h\t\0" + /* 4788 */ "srli.h\t\0" + /* 4796 */ "binsli.h\t\0" + /* 4806 */ "ceqi.h\t\0" + /* 4814 */ "srari.h\t\0" + /* 4823 */ "bclri.h\t\0" + /* 4832 */ "srlri.h\t\0" + /* 4841 */ "binsri.h\t\0" + /* 4851 */ "splati.h\t\0" + /* 4861 */ "bseti.h\t\0" + /* 4870 */ "subvi.h\t\0" + /* 4879 */ "addvi.h\t\0" + /* 4888 */ "fill.h\t\0" + /* 4896 */ "sll.h\t\0" + /* 4903 */ "srl.h\t\0" + /* 4910 */ "binsl.h\t\0" + /* 4919 */ "ilvl.h\t\0" + /* 4927 */ "fexdo.h\t\0" + /* 4936 */ "msub_q.h\t\0" + /* 4946 */ "madd_q.h\t\0" + /* 4956 */ "mul_q.h\t\0" + /* 4965 */ "msubr_q.h\t\0" + /* 4976 */ "maddr_q.h\t\0" + /* 4987 */ "mulr_q.h\t\0" + /* 4997 */ "ceq.h\t\0" + /* 5004 */ "ftq.h\t\0" + /* 5011 */ "srar.h\t\0" + /* 5019 */ "bclr.h\t\0" + /* 5027 */ "srlr.h\t\0" + /* 5035 */ "binsr.h\t\0" + /* 5044 */ "ilvr.h\t\0" + /* 5052 */ "asub_s.h\t\0" + /* 5062 */ "hsub_s.h\t\0" + /* 5072 */ "dpsub_s.h\t\0" + /* 5083 */ "hadd_s.h\t\0" + /* 5093 */ "dpadd_s.h\t\0" + /* 5104 */ "mod_s.h\t\0" + /* 5113 */ "cle_s.h\t\0" + /* 5122 */ "ave_s.h\t\0" + /* 5131 */ "clei_s.h\t\0" + /* 5141 */ "mini_s.h\t\0" + /* 5151 */ "clti_s.h\t\0" + /* 5161 */ "maxi_s.h\t\0" + /* 5171 */ "min_s.h\t\0" + /* 5180 */ "dotp_s.h\t\0" + /* 5190 */ "aver_s.h\t\0" + /* 5200 */ "extr_s.h\t\0" + /* 5210 */ "subs_s.h\t\0" + /* 5220 */ "adds_s.h\t\0" + /* 5230 */ "sat_s.h\t\0" + /* 5239 */ "clt_s.h\t\0" + /* 5248 */ "subsuu_s.h\t\0" + /* 5260 */ "div_s.h\t\0" + /* 5269 */ "extrv_s.h\t\0" + /* 5280 */ "max_s.h\t\0" + /* 5289 */ "copy_s.h\t\0" + /* 5299 */ "splat.h\t\0" + /* 5308 */ "bset.h\t\0" + /* 5316 */ "pcnt.h\t\0" + /* 5324 */ "insert.h\t\0" + /* 5334 */ "st.h\t\0" + /* 5340 */ "asub_u.h\t\0" + /* 5350 */ "hsub_u.h\t\0" + /* 5360 */ "dpsub_u.h\t\0" + /* 5371 */ "hadd_u.h\t\0" + /* 5381 */ "dpadd_u.h\t\0" + /* 5392 */ "mod_u.h\t\0" + /* 5401 */ "cle_u.h\t\0" + /* 5410 */ "ave_u.h\t\0" + /* 5419 */ "clei_u.h\t\0" + /* 5429 */ "mini_u.h\t\0" + /* 5439 */ "clti_u.h\t\0" + /* 5449 */ "maxi_u.h\t\0" + /* 5459 */ "min_u.h\t\0" + /* 5468 */ "dotp_u.h\t\0" + /* 5478 */ "aver_u.h\t\0" + /* 5488 */ "subs_u.h\t\0" + /* 5498 */ "adds_u.h\t\0" + /* 5508 */ "subsus_u.h\t\0" + /* 5520 */ "sat_u.h\t\0" + /* 5529 */ "clt_u.h\t\0" + /* 5538 */ "div_u.h\t\0" + /* 5547 */ "max_u.h\t\0" + /* 5556 */ "copy_u.h\t\0" + /* 5566 */ "msubv.h\t\0" + /* 5575 */ "maddv.h\t\0" + /* 5584 */ "pckev.h\t\0" + /* 5593 */ "ilvev.h\t\0" + /* 5602 */ "mulv.h\t\0" + /* 5610 */ "bz.h\t\0" + /* 5616 */ "bnz.h\t\0" + /* 5623 */ "crc32h\t\0" + /* 5631 */ "dsbh\t\0" + /* 5637 */ "wsbh\t\0" + /* 5643 */ "crc32ch\t\0" + /* 5652 */ "seh\t\0" + /* 5657 */ "ualh\t\0" + /* 5663 */ "ulh\t\0" + /* 5668 */ "shra.ph\t\0" + /* 5677 */ "precrq.qb.ph\t\0" + /* 5691 */ "precr.qb.ph\t\0" + /* 5704 */ "precrqu_s.qb.ph\t\0" + /* 5721 */ "cmp.le.ph\t\0" + /* 5732 */ "subqh.ph\t\0" + /* 5742 */ "addqh.ph\t\0" + /* 5752 */ "pick.ph\t\0" + /* 5761 */ "shll.ph\t\0" + /* 5770 */ "repl.ph\t\0" + /* 5779 */ "shrl.ph\t\0" + /* 5788 */ "packrl.ph\t\0" + /* 5799 */ "mul.ph\t\0" + /* 5807 */ "subq.ph\t\0" + /* 5816 */ "addq.ph\t\0" + /* 5825 */ "cmp.eq.ph\t\0" + /* 5836 */ "shra_r.ph\t\0" + /* 5847 */ "subqh_r.ph\t\0" + /* 5859 */ "addqh_r.ph\t\0" + /* 5871 */ "shrav_r.ph\t\0" + /* 5883 */ "shll_s.ph\t\0" + /* 5894 */ "mul_s.ph\t\0" + /* 5904 */ "subq_s.ph\t\0" + /* 5915 */ "addq_s.ph\t\0" + /* 5926 */ "mulq_s.ph\t\0" + /* 5937 */ "absq_s.ph\t\0" + /* 5948 */ "subu_s.ph\t\0" + /* 5959 */ "addu_s.ph\t\0" + /* 5970 */ "shllv_s.ph\t\0" + /* 5982 */ "mulq_rs.ph\t\0" + /* 5994 */ "cmp.lt.ph\t\0" + /* 6005 */ "subu.ph\t\0" + /* 6014 */ "addu.ph\t\0" + /* 6023 */ "shrav.ph\t\0" + /* 6033 */ "shllv.ph\t\0" + /* 6043 */ "replv.ph\t\0" + /* 6053 */ "shrlv.ph\t\0" + /* 6063 */ "dpa.w.ph\t\0" + /* 6073 */ "dpaqx_sa.w.ph\t\0" + /* 6088 */ "dpsqx_sa.w.ph\t\0" + /* 6103 */ "mulsa.w.ph\t\0" + /* 6115 */ "dpaq_s.w.ph\t\0" + /* 6128 */ "mulsaq_s.w.ph\t\0" + /* 6143 */ "dpsq_s.w.ph\t\0" + /* 6156 */ "dpaqx_s.w.ph\t\0" + /* 6170 */ "dpsqx_s.w.ph\t\0" + /* 6184 */ "dps.w.ph\t\0" + /* 6194 */ "dpax.w.ph\t\0" + /* 6205 */ "dpsx.w.ph\t\0" + /* 6216 */ "uash\t\0" + /* 6222 */ "ush\t\0" + /* 6227 */ "dmuh\t\0" + /* 6233 */ "synci\t\0" + /* 6240 */ "daddi\t\0" + /* 6247 */ "andi\t\0" + /* 6253 */ "tgei\t\0" + /* 6259 */ "snei\t\0" + /* 6265 */ "tnei\t\0" + /* 6271 */ "dahi\t\0" + /* 6277 */ "mfhi\t\0" + /* 6283 */ "mthi\t\0" + /* 6289 */ ".align 2\n\tli\t\0" + /* 6303 */ "dli\t\0" + /* 6308 */ "cmpi\t\0" + /* 6314 */ "seqi\t\0" + /* 6320 */ "teqi\t\0" + /* 6326 */ "xori\t\0" + /* 6332 */ "dati\t\0" + /* 6338 */ "slti\t\0" + /* 6344 */ "tlti\t\0" + /* 6350 */ "daui\t\0" + /* 6356 */ "lui\t\0" + /* 6361 */ "ginvi\t\0" + /* 6368 */ "j\t\0" + /* 6371 */ "break\t\0" + /* 6378 */ "fork\t\0" + /* 6384 */ "cvt.d.l\t\0" + /* 6393 */ "cvt.s.l\t\0" + /* 6402 */ "bal\t\0" + /* 6407 */ "jal\t\0" + /* 6412 */ "bgezal\t\0" + /* 6420 */ "bltzal\t\0" + /* 6428 */ "dpau.h.qbl\t\0" + /* 6440 */ "dpsu.h.qbl\t\0" + /* 6452 */ "muleu_s.ph.qbl\t\0" + /* 6468 */ "preceu.ph.qbl\t\0" + /* 6483 */ "precequ.ph.qbl\t\0" + /* 6499 */ "ldl\t\0" + /* 6504 */ "sdl\t\0" + /* 6509 */ "bgel\t\0" + /* 6515 */ "blel\t\0" + /* 6521 */ "bnel\t\0" + /* 6527 */ "bc1fl\t\0" + /* 6534 */ "maq_sa.w.phl\t\0" + /* 6548 */ "preceq.w.phl\t\0" + /* 6562 */ "maq_s.w.phl\t\0" + /* 6575 */ "muleq_s.w.phl\t\0" + /* 6590 */ "hypcall\t\0" + /* 6599 */ "syscall\t\0" + /* 6608 */ "bgezall\t\0" + /* 6617 */ "bltzall\t\0" + /* 6626 */ "dsll\t\0" + /* 6632 */ "drol\t\0" + /* 6638 */ "cvt.s.pl\t\0" + /* 6648 */ "beql\t\0" + /* 6654 */ "dsrl\t\0" + /* 6660 */ "bc1tl\t\0" + /* 6667 */ "bgtl\t\0" + /* 6673 */ "bltl\t\0" + /* 6679 */ "bgeul\t\0" + /* 6686 */ "bleul\t\0" + /* 6693 */ "dmul\t\0" + /* 6699 */ "bgtul\t\0" + /* 6706 */ "bltul\t\0" + /* 6713 */ "lwl\t\0" + /* 6718 */ "swl\t\0" + /* 6723 */ "bgezl\t\0" + /* 6730 */ "blezl\t\0" + /* 6737 */ "bgtzl\t\0" + /* 6744 */ "bltzl\t\0" + /* 6751 */ "drem\t\0" + /* 6757 */ "dinsm\t\0" + /* 6764 */ "dextm\t\0" + /* 6771 */ "ualwm\t\0" + /* 6778 */ "uaswm\t\0" + /* 6785 */ "balign\t\0" + /* 6793 */ "dalign\t\0" + /* 6801 */ "movn\t\0" + /* 6807 */ "dclo\t\0" + /* 6813 */ "mflo\t\0" + /* 6819 */ "shilo\t\0" + /* 6826 */ "mtlo\t\0" + /* 6832 */ "dmulo\t\0" + /* 6839 */ "dbitswap\t\0" + /* 6849 */ "sdbbp\t\0" + /* 6856 */ "extpdp\t\0" + /* 6864 */ "movep\t\0" + /* 6871 */ "mthlip\t\0" + /* 6879 */ "cmp\t\0" + /* 6884 */ "dpop\t\0" + /* 6890 */ "addiur1sp\t\0" + /* 6901 */ "load_ccond_dsp\t\0" + /* 6917 */ "store_ccond_dsp\t\0" + /* 6934 */ "rddsp\t\0" + /* 6941 */ "wrdsp\t\0" + /* 6948 */ "jrcaddiusp\t\0" + /* 6960 */ "jraddiusp\t\0" + /* 6971 */ "swsp\t\0" + /* 6977 */ "extp\t\0" + /* 6983 */ "dvp\t\0" + /* 6988 */ "evp\t\0" + /* 6993 */ "lwp\t\0" + /* 6998 */ "swp\t\0" + /* 7003 */ "beq\t\0" + /* 7008 */ "seq\t\0" + /* 7013 */ "teq\t\0" + /* 7018 */ "dpau.h.qbr\t\0" + /* 7030 */ "dpsu.h.qbr\t\0" + /* 7042 */ "muleu_s.ph.qbr\t\0" + /* 7058 */ "preceu.ph.qbr\t\0" + /* 7073 */ "precequ.ph.qbr\t\0" + /* 7089 */ "ldr\t\0" + /* 7094 */ "sdr\t\0" + /* 7099 */ "maq_sa.w.phr\t\0" + /* 7113 */ "preceq.w.phr\t\0" + /* 7127 */ "maq_s.w.phr\t\0" + /* 7140 */ "muleq_s.w.phr\t\0" + /* 7155 */ "jr\t\0" + /* 7159 */ "jalr\t\0" + /* 7165 */ "nor\t\0" + /* 7170 */ "dror\t\0" + /* 7176 */ "xor\t\0" + /* 7181 */ "rdpgpr\t\0" + /* 7189 */ "wrpgpr\t\0" + /* 7197 */ "mftr\t\0" + /* 7203 */ "drotr\t\0" + /* 7210 */ "mttr\t\0" + /* 7216 */ "rdhwr\t\0" + /* 7223 */ "lwr\t\0" + /* 7228 */ "swr\t\0" + /* 7233 */ "mina.s\t\0" + /* 7241 */ "maxa.s\t\0" + /* 7249 */ "nmsub.s\t\0" + /* 7258 */ "cvt.d.s\t\0" + /* 7267 */ "nmadd.s\t\0" + /* 7276 */ "c.nge.s\t\0" + /* 7285 */ "c.le.s\t\0" + /* 7293 */ "cmp.le.s\t\0" + /* 7303 */ "c.ngle.s\t\0" + /* 7313 */ "c.ole.s\t\0" + /* 7322 */ "cmp.sle.s\t\0" + /* 7333 */ "c.ule.s\t\0" + /* 7342 */ "cmp.ule.s\t\0" + /* 7353 */ "cmp.sule.s\t\0" + /* 7365 */ "c.f.s\t\0" + /* 7372 */ "cmp.af.s\t\0" + /* 7382 */ "cmp.saf.s\t\0" + /* 7393 */ "msubf.s\t\0" + /* 7402 */ "maddf.s\t\0" + /* 7411 */ "c.sf.s\t\0" + /* 7419 */ "movf.s\t\0" + /* 7427 */ "neg.s\t\0" + /* 7434 */ "li.s\t\0" + /* 7440 */ "trunc.l.s\t\0" + /* 7451 */ "round.l.s\t\0" + /* 7462 */ "ceil.l.s\t\0" + /* 7472 */ "floor.l.s\t\0" + /* 7483 */ "cvt.l.s\t\0" + /* 7492 */ "sel.s\t\0" + /* 7499 */ "c.ngl.s\t\0" + /* 7508 */ "mul.s\t\0" + /* 7515 */ "min.s\t\0" + /* 7522 */ "c.un.s\t\0" + /* 7530 */ "cmp.un.s\t\0" + /* 7540 */ "cmp.sun.s\t\0" + /* 7551 */ "movn.s\t\0" + /* 7559 */ "recip.s\t\0" + /* 7568 */ "c.eq.s\t\0" + /* 7576 */ "cmp.eq.s\t\0" + /* 7586 */ "c.seq.s\t\0" + /* 7595 */ "cmp.seq.s\t\0" + /* 7606 */ "c.ueq.s\t\0" + /* 7615 */ "cmp.ueq.s\t\0" + /* 7626 */ "cmp.sueq.s\t\0" + /* 7638 */ "abs.s\t\0" + /* 7645 */ "cvt.ps.s\t\0" + /* 7655 */ "class.s\t\0" + /* 7664 */ "c.ngt.s\t\0" + /* 7673 */ "c.lt.s\t\0" + /* 7681 */ "cmp.lt.s\t\0" + /* 7691 */ "c.olt.s\t\0" + /* 7700 */ "cmp.slt.s\t\0" + /* 7711 */ "c.ult.s\t\0" + /* 7720 */ "cmp.ult.s\t\0" + /* 7731 */ "cmp.sult.s\t\0" + /* 7743 */ "rint.s\t\0" + /* 7751 */ "rsqrt.s\t\0" + /* 7760 */ "movt.s\t\0" + /* 7768 */ "div.s\t\0" + /* 7775 */ "mov.s\t\0" + /* 7782 */ "trunc.w.s\t\0" + /* 7793 */ "round.w.s\t\0" + /* 7804 */ "ceil.w.s\t\0" + /* 7814 */ "floor.w.s\t\0" + /* 7825 */ "cvt.w.s\t\0" + /* 7834 */ "max.s\t\0" + /* 7841 */ "selnez.s\t\0" + /* 7851 */ "seleqz.s\t\0" + /* 7861 */ "movz.s\t\0" + /* 7869 */ "abs\t\0" + /* 7874 */ "jals\t\0" + /* 7880 */ "bgezals\t\0" + /* 7889 */ "bltzals\t\0" + /* 7898 */ "cins\t\0" + /* 7904 */ "dins\t\0" + /* 7910 */ "sub.ps\t\0" + /* 7918 */ "add.ps\t\0" + /* 7926 */ "pll.ps\t\0" + /* 7934 */ "mul.ps\t\0" + /* 7942 */ "pul.ps\t\0" + /* 7950 */ "addr.ps\t\0" + /* 7959 */ "mulr.ps\t\0" + /* 7968 */ "plu.ps\t\0" + /* 7976 */ "puu.ps\t\0" + /* 7984 */ "cvt.pw.ps\t\0" + /* 7995 */ "jalrs\t\0" + /* 8002 */ "exts\t\0" + /* 8008 */ "lhxs\t\0" + /* 8014 */ "shxs\t\0" + /* 8020 */ "lhuxs\t\0" + /* 8027 */ "lwxs\t\0" + /* 8033 */ "swxs\t\0" + /* 8039 */ "bc1t\t\0" + /* 8045 */ "bgt\t\0" + /* 8050 */ "sgt\t\0" + /* 8055 */ "wait\t\0" + /* 8061 */ "blt\t\0" + /* 8066 */ "slt\t\0" + /* 8071 */ "tlt\t\0" + /* 8076 */ "dmult\t\0" + /* 8083 */ "dmt\t\0" + /* 8088 */ "emt\t\0" + /* 8093 */ "not\t\0" + /* 8098 */ "ginvt\t\0" + /* 8105 */ "movt\t\0" + /* 8111 */ "dext\t\0" + /* 8117 */ "lbu\t\0" + /* 8122 */ "dsubu\t\0" + /* 8129 */ "msubu\t\0" + /* 8136 */ "baddu\t\0" + /* 8143 */ "daddu\t\0" + /* 8150 */ "maddu\t\0" + /* 8157 */ "dmodu\t\0" + /* 8164 */ "bgeu\t\0" + /* 8170 */ "sgeu\t\0" + /* 8176 */ "tgeu\t\0" + /* 8182 */ "bleu\t\0" + /* 8188 */ "sleu\t\0" + /* 8194 */ "ulhu\t\0" + /* 8200 */ "dmuhu\t\0" + /* 8207 */ "daddiu\t\0" + /* 8215 */ "tgeiu\t\0" + /* 8222 */ "sltiu\t\0" + /* 8229 */ "tltiu\t\0" + /* 8236 */ "v3mulu\t\0" + /* 8244 */ "dmulu\t\0" + /* 8251 */ "vmulu\t\0" + /* 8258 */ "dremu\t\0" + /* 8265 */ "dmulou\t\0" + /* 8273 */ "cvt.s.pu\t\0" + /* 8283 */ "dinsu\t\0" + /* 8290 */ "bgtu\t\0" + /* 8296 */ "sgtu\t\0" + /* 8302 */ "bltu\t\0" + /* 8308 */ "sltu\t\0" + /* 8314 */ "tltu\t\0" + /* 8320 */ "dmultu\t\0" + /* 8328 */ "dextu\t\0" + /* 8335 */ "ddivu\t\0" + /* 8342 */ "lwu\t\0" + /* 8347 */ "and.v\t\0" + /* 8354 */ "move.v\t\0" + /* 8362 */ "bsel.v\t\0" + /* 8370 */ "nor.v\t\0" + /* 8377 */ "xor.v\t\0" + /* 8384 */ "bz.v\t\0" + /* 8390 */ "bmz.v\t\0" + /* 8397 */ "bnz.v\t\0" + /* 8404 */ "bmnz.v\t\0" + /* 8412 */ "dsrav\t\0" + /* 8419 */ "bitrev\t\0" + /* 8427 */ "ddiv\t\0" + /* 8433 */ "dsllv\t\0" + /* 8440 */ "dsrlv\t\0" + /* 8447 */ "shilov\t\0" + /* 8455 */ "sov\t\0" + /* 8460 */ "extpdpv\t\0" + /* 8469 */ "extpv\t\0" + /* 8476 */ "drotrv\t\0" + /* 8484 */ "insv\t\0" + /* 8490 */ "flog2.w\t\0" + /* 8499 */ "fexp2.w\t\0" + /* 8508 */ "add_a.w\t\0" + /* 8517 */ "fmin_a.w\t\0" + /* 8527 */ "adds_a.w\t\0" + /* 8537 */ "fmax_a.w\t\0" + /* 8547 */ "sra.w\t\0" + /* 8554 */ "fsub.w\t\0" + /* 8562 */ "fmsub.w\t\0" + /* 8571 */ "nloc.w\t\0" + /* 8579 */ "nlzc.w\t\0" + /* 8587 */ "cvt.d.w\t\0" + /* 8596 */ "fadd.w\t\0" + /* 8604 */ "fmadd.w\t\0" + /* 8613 */ "sld.w\t\0" + /* 8620 */ "pckod.w\t\0" + /* 8629 */ "ilvod.w\t\0" + /* 8638 */ "fcle.w\t\0" + /* 8646 */ "fsle.w\t\0" + /* 8654 */ "fcule.w\t\0" + /* 8663 */ "fsule.w\t\0" + /* 8672 */ "fcne.w\t\0" + /* 8680 */ "fsne.w\t\0" + /* 8688 */ "fcune.w\t\0" + /* 8697 */ "fsune.w\t\0" + /* 8706 */ "insve.w\t\0" + /* 8715 */ "fcaf.w\t\0" + /* 8723 */ "fsaf.w\t\0" + /* 8731 */ "vshf.w\t\0" + /* 8739 */ "bneg.w\t\0" + /* 8747 */ "precr_sra.ph.w\t\0" + /* 8763 */ "precrq.ph.w\t\0" + /* 8776 */ "precr_sra_r.ph.w\t\0" + /* 8794 */ "precrq_rs.ph.w\t\0" + /* 8810 */ "subqh.w\t\0" + /* 8819 */ "addqh.w\t\0" + /* 8828 */ "srai.w\t\0" + /* 8836 */ "sldi.w\t\0" + /* 8844 */ "bnegi.w\t\0" + /* 8853 */ "slli.w\t\0" + /* 8861 */ "srli.w\t\0" + /* 8869 */ "binsli.w\t\0" + /* 8879 */ "ceqi.w\t\0" + /* 8887 */ "srari.w\t\0" + /* 8896 */ "bclri.w\t\0" + /* 8905 */ "srlri.w\t\0" + /* 8914 */ "binsri.w\t\0" + /* 8924 */ "splati.w\t\0" + /* 8934 */ "bseti.w\t\0" + /* 8943 */ "subvi.w\t\0" + /* 8952 */ "addvi.w\t\0" + /* 8961 */ "dpaq_sa.l.w\t\0" + /* 8974 */ "dpsq_sa.l.w\t\0" + /* 8987 */ "fill.w\t\0" + /* 8995 */ "sll.w\t\0" + /* 9002 */ "fexupl.w\t\0" + /* 9012 */ "ffql.w\t\0" + /* 9020 */ "srl.w\t\0" + /* 9027 */ "binsl.w\t\0" + /* 9036 */ "fmul.w\t\0" + /* 9044 */ "ilvl.w\t\0" + /* 9052 */ "fmin.w\t\0" + /* 9060 */ "fcun.w\t\0" + /* 9068 */ "fsun.w\t\0" + /* 9076 */ "fexdo.w\t\0" + /* 9085 */ "frcp.w\t\0" + /* 9093 */ "msub_q.w\t\0" + /* 9103 */ "madd_q.w\t\0" + /* 9113 */ "mul_q.w\t\0" + /* 9122 */ "msubr_q.w\t\0" + /* 9133 */ "maddr_q.w\t\0" + /* 9144 */ "mulr_q.w\t\0" + /* 9154 */ "fceq.w\t\0" + /* 9162 */ "fseq.w\t\0" + /* 9170 */ "fcueq.w\t\0" + /* 9179 */ "fsueq.w\t\0" + /* 9188 */ "ftq.w\t\0" + /* 9195 */ "shra_r.w\t\0" + /* 9205 */ "subqh_r.w\t\0" + /* 9216 */ "addqh_r.w\t\0" + /* 9227 */ "extr_r.w\t\0" + /* 9237 */ "shrav_r.w\t\0" + /* 9248 */ "extrv_r.w\t\0" + /* 9259 */ "srar.w\t\0" + /* 9267 */ "bclr.w\t\0" + /* 9275 */ "srlr.w\t\0" + /* 9283 */ "fcor.w\t\0" + /* 9291 */ "fsor.w\t\0" + /* 9299 */ "fexupr.w\t\0" + /* 9309 */ "ffqr.w\t\0" + /* 9317 */ "binsr.w\t\0" + /* 9326 */ "extr.w\t\0" + /* 9334 */ "ilvr.w\t\0" + /* 9342 */ "cvt.s.w\t\0" + /* 9351 */ "asub_s.w\t\0" + /* 9361 */ "hsub_s.w\t\0" + /* 9371 */ "dpsub_s.w\t\0" + /* 9382 */ "ftrunc_s.w\t\0" + /* 9394 */ "hadd_s.w\t\0" + /* 9404 */ "dpadd_s.w\t\0" + /* 9415 */ "mod_s.w\t\0" + /* 9424 */ "cle_s.w\t\0" + /* 9433 */ "ave_s.w\t\0" + /* 9442 */ "clei_s.w\t\0" + /* 9452 */ "mini_s.w\t\0" + /* 9462 */ "clti_s.w\t\0" + /* 9472 */ "maxi_s.w\t\0" + /* 9482 */ "shll_s.w\t\0" + /* 9492 */ "min_s.w\t\0" + /* 9501 */ "dotp_s.w\t\0" + /* 9511 */ "subq_s.w\t\0" + /* 9521 */ "addq_s.w\t\0" + /* 9531 */ "mulq_s.w\t\0" + /* 9541 */ "absq_s.w\t\0" + /* 9551 */ "aver_s.w\t\0" + /* 9561 */ "subs_s.w\t\0" + /* 9571 */ "adds_s.w\t\0" + /* 9581 */ "sat_s.w\t\0" + /* 9590 */ "clt_s.w\t\0" + /* 9599 */ "ffint_s.w\t\0" + /* 9610 */ "ftint_s.w\t\0" + /* 9621 */ "subsuu_s.w\t\0" + /* 9633 */ "div_s.w\t\0" + /* 9642 */ "shllv_s.w\t\0" + /* 9653 */ "max_s.w\t\0" + /* 9662 */ "copy_s.w\t\0" + /* 9672 */ "mulq_rs.w\t\0" + /* 9683 */ "extr_rs.w\t\0" + /* 9694 */ "extrv_rs.w\t\0" + /* 9706 */ "fclass.w\t\0" + /* 9716 */ "splat.w\t\0" + /* 9725 */ "bset.w\t\0" + /* 9733 */ "fclt.w\t\0" + /* 9741 */ "fslt.w\t\0" + /* 9749 */ "fcult.w\t\0" + /* 9758 */ "fsult.w\t\0" + /* 9767 */ "pcnt.w\t\0" + /* 9775 */ "frint.w\t\0" + /* 9784 */ "insert.w\t\0" + /* 9794 */ "fsqrt.w\t\0" + /* 9803 */ "frsqrt.w\t\0" + /* 9813 */ "st.w\t\0" + /* 9819 */ "asub_u.w\t\0" + /* 9829 */ "hsub_u.w\t\0" + /* 9839 */ "dpsub_u.w\t\0" + /* 9850 */ "ftrunc_u.w\t\0" + /* 9862 */ "hadd_u.w\t\0" + /* 9872 */ "dpadd_u.w\t\0" + /* 9883 */ "mod_u.w\t\0" + /* 9892 */ "cle_u.w\t\0" + /* 9901 */ "ave_u.w\t\0" + /* 9910 */ "clei_u.w\t\0" + /* 9920 */ "mini_u.w\t\0" + /* 9930 */ "clti_u.w\t\0" + /* 9940 */ "maxi_u.w\t\0" + /* 9950 */ "min_u.w\t\0" + /* 9959 */ "dotp_u.w\t\0" + /* 9969 */ "aver_u.w\t\0" + /* 9979 */ "subs_u.w\t\0" + /* 9989 */ "adds_u.w\t\0" + /* 9999 */ "subsus_u.w\t\0" + /* 10011 */ "sat_u.w\t\0" + /* 10020 */ "clt_u.w\t\0" + /* 10029 */ "ffint_u.w\t\0" + /* 10040 */ "ftint_u.w\t\0" + /* 10051 */ "div_u.w\t\0" + /* 10060 */ "max_u.w\t\0" + /* 10069 */ "copy_u.w\t\0" + /* 10079 */ "msubv.w\t\0" + /* 10088 */ "maddv.w\t\0" + /* 10097 */ "pckev.w\t\0" + /* 10106 */ "ilvev.w\t\0" + /* 10115 */ "fdiv.w\t\0" + /* 10123 */ "mulv.w\t\0" + /* 10131 */ "extrv.w\t\0" + /* 10140 */ "fmax.w\t\0" + /* 10148 */ "bz.w\t\0" + /* 10154 */ "bnz.w\t\0" + /* 10161 */ "crc32w\t\0" + /* 10169 */ "crc32cw\t\0" + /* 10178 */ "ualw\t\0" + /* 10184 */ "ulw\t\0" + /* 10189 */ "cvt.ps.pw\t\0" + /* 10200 */ "uasw\t\0" + /* 10206 */ "usw\t\0" + /* 10211 */ "extw\t\0" + /* 10217 */ "byterevw\t\0" + /* 10227 */ "bitrevw\t\0" + /* 10236 */ "lbx\t\0" + /* 10241 */ "sbx\t\0" + /* 10246 */ "prefx\t\0" + /* 10253 */ "lhx\t\0" + /* 10258 */ "shx\t\0" + /* 10263 */ "jalx\t\0" + /* 10269 */ "rotx\t\0" + /* 10275 */ "lbux\t\0" + /* 10281 */ "lhux\t\0" + /* 10287 */ "lwx\t\0" + /* 10292 */ "swx\t\0" + /* 10297 */ "bgez\t\0" + /* 10303 */ "blez\t\0" + /* 10309 */ "bnez\t\0" + /* 10315 */ "selnez\t\0" + /* 10323 */ "btnez\t\0" + /* 10330 */ "dclz\t\0" + /* 10336 */ "beqz\t\0" + /* 10342 */ "seleqz\t\0" + /* 10350 */ "bteqz\t\0" + /* 10357 */ "bgtz\t\0" + /* 10363 */ "bltz\t\0" + /* 10369 */ "movz\t\0" + /* 10375 */ "seb\t \0" + /* 10381 */ "seh\t \0" + /* 10387 */ "ddivu\t$zero, \0" + /* 10401 */ "ddiv\t$zero, \0" + /* 10414 */ "addiu\t$sp, \0" + /* 10426 */ "mftc0 \0" + /* 10433 */ "mttc0 \0" + /* 10440 */ "mfthc1 \0" + /* 10448 */ "mtthc1 \0" + /* 10456 */ "cftc1 \0" + /* 10463 */ "mftc1 \0" + /* 10470 */ "cttc1 \0" + /* 10477 */ "mttc1 \0" + /* 10484 */ "sync \0" + /* 10490 */ "ld \0" + /* 10494 */ "\t.word \0" + /* 10502 */ "sd \0" + /* 10506 */ "sne \0" + /* 10511 */ "mfthi \0" + /* 10518 */ "mtthi \0" + /* 10525 */ "mftlo \0" + /* 10532 */ "mttlo \0" + /* 10539 */ "mftdsp \0" + /* 10547 */ "mttdsp \0" + /* 10555 */ "scwp \0" + /* 10561 */ "llwp \0" + /* 10567 */ "seq \0" + /* 10572 */ "mftgpr \0" + /* 10580 */ "mttgpr \0" + /* 10588 */ "dext \0" + /* 10594 */ "mftacx \0" + /* 10602 */ "mttacx \0" + /* 10610 */ "bc1nez \0" + /* 10618 */ "bc2nez \0" + /* 10626 */ "bc1eqz \0" + /* 10634 */ "bc2eqz \0" + /* 10642 */ "# XRay Function Patchable RET.\0" + /* 10673 */ "c.\0" + /* 10676 */ "# XRay Typed Event Log.\0" + /* 10700 */ "# XRay Custom Event Log.\0" + /* 10725 */ "# XRay Function Enter.\0" + /* 10748 */ "# XRay Tail Call Exit.\0" + /* 10771 */ "# XRay Function Exit.\0" + /* 10793 */ "break 0\0" + /* 10801 */ "nop32\0" + /* 10807 */ "LIFETIME_END\0" + /* 10820 */ "PSEUDO_PROBE\0" + /* 10833 */ "BUNDLE\0" + /* 10840 */ "DBG_VALUE\0" + /* 10850 */ "DBG_INSTR_REF\0" + /* 10864 */ "DBG_PHI\0" + /* 10872 */ "DBG_LABEL\0" + /* 10882 */ "LIFETIME_START\0" + /* 10897 */ "DBG_VALUE_LIST\0" + /* 10912 */ "jrc\t$ra\0" + /* 10920 */ "jr\t$ra\0" + /* 10927 */ "ehb\0" + /* 10931 */ "eretnc\0" + /* 10938 */ "pause\0" + /* 10944 */ "tlbinvf\0" + /* 10952 */ "tlbginvf\0" + /* 10961 */ "tlbwi\0" + /* 10967 */ "tlbgwi\0" + /* 10974 */ "# FEntry call\0" + /* 10988 */ "foo\0" + /* 10992 */ "tlbp\0" + /* 10997 */ "tlbgp\0" + /* 11003 */ "ssnop\0" + /* 11009 */ "tlbr\0" + /* 11014 */ "tlbgr\0" + /* 11020 */ "tlbwr\0" + /* 11026 */ "tlbgwr\0" + /* 11033 */ "deret\0" + /* 11039 */ "wait\0" + /* 11044 */ "tlbinv\0" + /* 11051 */ "tlbginv\0" +}; +#endif // CAPSTONE_DIET + + static const uint32_t OpInfo0[] = { 0U, // PHI 0U, // INLINEASM + 0U, // INLINEASM_BR 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS - 9396U, // DBG_VALUE + 10841U, // DBG_VALUE + 10898U, // DBG_VALUE_LIST + 10851U, // DBG_INSTR_REF + 10865U, // DBG_PHI + 10873U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY - 9389U, // BUNDLE - 9406U, // LIFETIME_START - 9376U, // LIFETIME_END + 10834U, // BUNDLE + 10883U, // LIFETIME_START + 10808U, // LIFETIME_END + 10821U, // PSEUDO_PROBE + 0U, // ARITH_FENCE 0U, // STACKMAP + 10975U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG 0U, // STATEPOINT - 0U, // FRAME_ALLOC - 21660U, // ABSQ_S_PH - 18025U, // ABSQ_S_QB - 24850U, // ABSQ_S_W - 134237992U, // ADD - 18294U, // ADDIUPC - 18294U, // ADDIUPC_MM - 22527U, // ADDIUR1SP_MM - 134234410U, // ADDIUR2_MM - 8683851U, // ADDIUS5_MM - 546875U, // ADDIUSP_MM - 134239193U, // ADDQH_PH - 134239310U, // ADDQH_R_PH - 134242253U, // ADDQH_R_W - 134241856U, // ADDQH_W - 134239267U, // ADDQ_PH - 134239366U, // ADDQ_S_PH - 134242558U, // ADDQ_S_W - 134236055U, // ADDSC - 134234730U, // ADDS_A_B - 134236180U, // ADDS_A_D - 134238138U, // ADDS_A_H - 134241564U, // ADDS_A_W - 134235198U, // ADDS_S_B - 134237269U, // ADDS_S_D - 134238695U, // ADDS_S_H - 134242608U, // ADDS_S_W - 134235413U, // ADDS_U_B - 134237736U, // ADDS_U_D - 134238973U, // ADDS_U_H - 134243026U, // ADDS_U_W - 134234575U, // ADDU16_MM - 134235621U, // ADDUH_QB - 134235729U, // ADDUH_R_QB - 134239465U, // ADDU_PH - 134235834U, // ADDU_QB - 134239410U, // ADDU_S_PH - 134235775U, // ADDU_S_QB - 2281718627U, // ADDVI_B - 2281720348U, // ADDVI_D - 2281722002U, // ADDVI_H - 2281725637U, // ADDVI_W - 134235491U, // ADDV_B - 134237836U, // ADDV_D - 134239051U, // ADDV_H - 134243126U, // ADDV_W - 134236094U, // ADDWC - 134234712U, // ADD_A_B - 134236161U, // ADD_A_D - 134238120U, // ADD_A_H - 134241545U, // ADD_A_W - 134237992U, // ADD_MM - 134239685U, // ADDi - 134239685U, // ADDi_MM - 134241307U, // ADDiu - 134241307U, // ADDiu_MM - 134241261U, // ADDu - 134241261U, // ADDu_MM + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 10726U, // PATCHABLE_FUNCTION_ENTER + 10643U, // PATCHABLE_RET + 10772U, // PATCHABLE_FUNCTION_EXIT + 10749U, // PATCHABLE_TAIL_CALL + 10701U, // PATCHABLE_EVENT_CALL + 10677U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // MEMBARRIER + 0U, // JUMP_TABLE_DEBUG_INFO + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ASSERT_ALIGN + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_CONSTANT_POOL + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_CONSTANT_FOLD_BARRIER + 0U, // G_INTRINSIC_FPTRUNC_ROUND + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_ATOMICRMW_FMAX + 0U, // G_ATOMICRMW_FMIN + 0U, // G_ATOMICRMW_UINC_WRAP + 0U, // G_ATOMICRMW_UDEC_WRAP + 0U, // G_FENCE + 0U, // G_PREFETCH + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INVOKE_REGION_START + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_INTRINSIC_CONVERGENT + 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FEXP10 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FLDEXP + 0U, // G_FFREXP + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_IS_FPCLASS + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_GET_FPENV + 0U, // G_SET_FPENV + 0U, // G_RESET_FPENV + 0U, // G_GET_FPMODE + 0U, // G_SET_FPMODE + 0U, // G_RESET_FPMODE + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STACKSAVE + 0U, // G_STACKRESTORE + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_STRICT_FLDEXP + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_FMAXIMUM + 0U, // G_VECREDUCE_FMINIMUM + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 24254U, // ABSMacro 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKDOWN_NM 0U, // ADJCALLSTACKUP - 134240158U, // ALIGN - 18286U, // ALUIPC - 134238014U, // AND - 835930U, // AND16_MM - 134238014U, // AND64 - 134234471U, // ANDI16_MM - 2281718486U, // ANDI_B - 134238014U, // AND_MM - 134241389U, // AND_V + 0U, // ADJCALLSTACKUP_NM + 536894083U, // ALIGN_NM 0U, // AND_V_D_PSEUDO 0U, // AND_V_H_PSEUDO 0U, // AND_V_W_PSEUDO - 134239691U, // ANDi - 134239691U, // ANDi64 - 134239691U, // ANDi_MM - 134238028U, // APPEND - 134235092U, // ASUB_S_B - 134237099U, // ASUB_S_D - 134238527U, // ASUB_S_H - 134242388U, // ASUB_S_W - 134235307U, // ASUB_U_B - 134237566U, // ASUB_U_D - 134238815U, // ASUB_U_H - 134242856U, // ASUB_U_W 0U, // ATOMIC_CMP_SWAP_I16 + 0U, // ATOMIC_CMP_SWAP_I16_POSTRA 0U, // ATOMIC_CMP_SWAP_I32 + 0U, // ATOMIC_CMP_SWAP_I32_POSTRA 0U, // ATOMIC_CMP_SWAP_I64 + 0U, // ATOMIC_CMP_SWAP_I64_POSTRA 0U, // ATOMIC_CMP_SWAP_I8 + 0U, // ATOMIC_CMP_SWAP_I8_POSTRA 0U, // ATOMIC_LOAD_ADD_I16 + 0U, // ATOMIC_LOAD_ADD_I16_POSTRA 0U, // ATOMIC_LOAD_ADD_I32 + 0U, // ATOMIC_LOAD_ADD_I32_POSTRA 0U, // ATOMIC_LOAD_ADD_I64 + 0U, // ATOMIC_LOAD_ADD_I64_POSTRA 0U, // ATOMIC_LOAD_ADD_I8 + 0U, // ATOMIC_LOAD_ADD_I8_POSTRA 0U, // ATOMIC_LOAD_AND_I16 + 0U, // ATOMIC_LOAD_AND_I16_POSTRA 0U, // ATOMIC_LOAD_AND_I32 + 0U, // ATOMIC_LOAD_AND_I32_POSTRA 0U, // ATOMIC_LOAD_AND_I64 + 0U, // ATOMIC_LOAD_AND_I64_POSTRA 0U, // ATOMIC_LOAD_AND_I8 + 0U, // ATOMIC_LOAD_AND_I8_POSTRA + 0U, // ATOMIC_LOAD_MAX_I16 + 0U, // ATOMIC_LOAD_MAX_I16_POSTRA + 0U, // ATOMIC_LOAD_MAX_I32 + 0U, // ATOMIC_LOAD_MAX_I32_POSTRA + 0U, // ATOMIC_LOAD_MAX_I64 + 0U, // ATOMIC_LOAD_MAX_I64_POSTRA + 0U, // ATOMIC_LOAD_MAX_I8 + 0U, // ATOMIC_LOAD_MAX_I8_POSTRA + 0U, // ATOMIC_LOAD_MIN_I16 + 0U, // ATOMIC_LOAD_MIN_I16_POSTRA + 0U, // ATOMIC_LOAD_MIN_I32 + 0U, // ATOMIC_LOAD_MIN_I32_POSTRA + 0U, // ATOMIC_LOAD_MIN_I64 + 0U, // ATOMIC_LOAD_MIN_I64_POSTRA + 0U, // ATOMIC_LOAD_MIN_I8 + 0U, // ATOMIC_LOAD_MIN_I8_POSTRA 0U, // ATOMIC_LOAD_NAND_I16 + 0U, // ATOMIC_LOAD_NAND_I16_POSTRA 0U, // ATOMIC_LOAD_NAND_I32 + 0U, // ATOMIC_LOAD_NAND_I32_POSTRA 0U, // ATOMIC_LOAD_NAND_I64 + 0U, // ATOMIC_LOAD_NAND_I64_POSTRA 0U, // ATOMIC_LOAD_NAND_I8 + 0U, // ATOMIC_LOAD_NAND_I8_POSTRA 0U, // ATOMIC_LOAD_OR_I16 + 0U, // ATOMIC_LOAD_OR_I16_POSTRA 0U, // ATOMIC_LOAD_OR_I32 + 0U, // ATOMIC_LOAD_OR_I32_POSTRA 0U, // ATOMIC_LOAD_OR_I64 + 0U, // ATOMIC_LOAD_OR_I64_POSTRA 0U, // ATOMIC_LOAD_OR_I8 + 0U, // ATOMIC_LOAD_OR_I8_POSTRA 0U, // ATOMIC_LOAD_SUB_I16 + 0U, // ATOMIC_LOAD_SUB_I16_POSTRA 0U, // ATOMIC_LOAD_SUB_I32 + 0U, // ATOMIC_LOAD_SUB_I32_POSTRA 0U, // ATOMIC_LOAD_SUB_I64 + 0U, // ATOMIC_LOAD_SUB_I64_POSTRA 0U, // ATOMIC_LOAD_SUB_I8 + 0U, // ATOMIC_LOAD_SUB_I8_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I16 + 0U, // ATOMIC_LOAD_UMAX_I16_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I32 + 0U, // ATOMIC_LOAD_UMAX_I32_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I64 + 0U, // ATOMIC_LOAD_UMAX_I64_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I8 + 0U, // ATOMIC_LOAD_UMAX_I8_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I16 + 0U, // ATOMIC_LOAD_UMIN_I16_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I32 + 0U, // ATOMIC_LOAD_UMIN_I32_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I64 + 0U, // ATOMIC_LOAD_UMIN_I64_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I8 + 0U, // ATOMIC_LOAD_UMIN_I8_POSTRA 0U, // ATOMIC_LOAD_XOR_I16 + 0U, // ATOMIC_LOAD_XOR_I16_POSTRA 0U, // ATOMIC_LOAD_XOR_I32 + 0U, // ATOMIC_LOAD_XOR_I32_POSTRA 0U, // ATOMIC_LOAD_XOR_I64 + 0U, // ATOMIC_LOAD_XOR_I64_POSTRA 0U, // ATOMIC_LOAD_XOR_I8 + 0U, // ATOMIC_LOAD_XOR_I8_POSTRA 0U, // ATOMIC_SWAP_I16 + 0U, // ATOMIC_SWAP_I16_POSTRA 0U, // ATOMIC_SWAP_I32 + 0U, // ATOMIC_SWAP_I32_POSTRA 0U, // ATOMIC_SWAP_I64 + 0U, // ATOMIC_SWAP_I64_POSTRA 0U, // ATOMIC_SWAP_I8 - 134239795U, // AUI - 18279U, // AUIPC - 134235178U, // AVER_S_B - 134237249U, // AVER_S_D - 134238665U, // AVER_S_H - 134242588U, // AVER_S_W - 134235393U, // AVER_U_B - 134237716U, // AVER_U_D - 134238953U, // AVER_U_H - 134243006U, // AVER_U_W - 134235120U, // AVE_S_B - 134237181U, // AVE_S_D - 134238597U, // AVE_S_H - 134242470U, // AVE_S_W - 134235335U, // AVE_U_B - 134237648U, // AVE_U_D - 134238885U, // AVE_U_H - 134242938U, // AVE_U_W - 23579U, // AddiuRxImmX16 - 1072155U, // AddiuRxPcImmX16 - 285236251U, // AddiuRxRxImm16 - 16800795U, // AddiuRxRxImmX16 - 25189403U, // AddiuRxRyOffMemX16 - 1336343U, // AddiuSpImm16 - 549911U, // AddiuSpImmX16 - 134241261U, // AdduRxRyRz16 - 16797502U, // AndRxRxRy16 + 0U, // ATOMIC_SWAP_I8_POSTRA 0U, // B - 541013U, // B16_MM - 134241260U, // BADDu - 546393U, // BAL - 542494U, // BALC - 134240157U, // BALIGN 0U, // BAL_BR - 167788585U, // BBIT0 - 167788717U, // BBIT032 - 167788710U, // BBIT1 - 167788726U, // BBIT132 - 542473U, // BC - 20351U, // BC0F - 22218U, // BC0FL - 23455U, // BC0T - 22347U, // BC0TL - 25733U, // BC1EQZ - 20357U, // BC1F - 22225U, // BC1FL - 20357U, // BC1F_MM - 25717U, // BC1NEZ - 23461U, // BC1T - 22354U, // BC1TL - 23461U, // BC1T_MM - 25741U, // BC2EQZ - 20363U, // BC2F - 22232U, // BC2FL - 25725U, // BC2NEZ - 23467U, // BC2T - 22361U, // BC2TL - 20369U, // BC3F - 22239U, // BC3FL - 23473U, // BC3T - 22368U, // BC3TL - 2281718555U, // BCLRI_B - 2281720292U, // BCLRI_D - 2281721946U, // BCLRI_H - 2281725581U, // BCLRI_W - 134235059U, // BCLR_B - 134237023U, // BCLR_D - 134238494U, // BCLR_H - 134242304U, // BCLR_W - 134240340U, // BEQ - 134240340U, // BEQ64 - 134236044U, // BEQC - 134240063U, // BEQL - 16882U, // BEQZ16_MM - 18246U, // BEQZALC - 18394U, // BEQZC - 18394U, // BEQZC_MM - 134240340U, // BEQ_MM - 134235917U, // BGEC - 134236068U, // BGEUC - 25500U, // BGEZ - 25500U, // BGEZ64 - 22115U, // BGEZAL - 18219U, // BGEZALC - 22311U, // BGEZALL - 23424U, // BGEZALS_MM - 22115U, // BGEZAL_MM - 18373U, // BGEZC - 22391U, // BGEZL - 25500U, // BGEZ_MM - 25560U, // BGTZ - 25560U, // BGTZ64 - 18255U, // BGTZALC - 18401U, // BGTZC - 22405U, // BGTZL - 25560U, // BGTZ_MM - 2298495744U, // BINSLI_B - 2298497481U, // BINSLI_D - 2298499135U, // BINSLI_H - 2298502770U, // BINSLI_W - 151012243U, // BINSL_B - 151014033U, // BINSL_D - 151015601U, // BINSL_H - 151019280U, // BINSL_W - 2298495805U, // BINSRI_B - 2298497526U, // BINSRI_D - 2298499180U, // BINSRI_H - 2298502815U, // BINSRI_W - 151012291U, // BINSR_B - 151014289U, // BINSR_D - 151015726U, // BINSR_H - 151019570U, // BINSR_W - 23733U, // BITREV - 22477U, // BITSWAP - 25506U, // BLEZ - 25506U, // BLEZ64 - 18228U, // BLEZALC - 18380U, // BLEZC - 22398U, // BLEZL - 25506U, // BLEZ_MM - 134236062U, // BLTC - 134236075U, // BLTUC - 25566U, // BLTZ - 25566U, // BLTZ64 - 22123U, // BLTZAL - 18264U, // BLTZALC - 22320U, // BLTZALL - 23433U, // BLTZALS_MM - 22123U, // BLTZAL_MM - 18408U, // BLTZC - 22412U, // BLTZL - 25566U, // BLTZ_MM - 2298495860U, // BMNZI_B - 151018662U, // BMNZ_V - 2298495852U, // BMZI_B - 151018648U, // BMZ_V - 134238058U, // BNE - 134238058U, // BNE64 - 134235923U, // BNEC - 2281718494U, // BNEGI_B - 2281720240U, // BNEGI_D - 2281721894U, // BNEGI_H - 2281725529U, // BNEGI_W - 134234814U, // BNEG_B - 134236568U, // BNEG_D - 134238222U, // BNEG_H - 134241776U, // BNEG_W - 134239940U, // BNEL - 16874U, // BNEZ16_MM - 18237U, // BNEZALC - 18387U, // BNEZC - 18387U, // BNEZC_MM - 134238058U, // BNE_MM - 134236082U, // BNVC - 17803U, // BNZ_B - 20233U, // BNZ_D - 21363U, // BNZ_H - 23711U, // BNZ_V - 25463U, // BNZ_W - 134236088U, // BOVC - 540871U, // BPOSGE32 + 0U, // BAL_BR_MM + 536893945U, // BEQLImmMacro + 536891762U, // BGE + 536891762U, // BGEImmMacro + 536893806U, // BGEL + 536893806U, // BGELImmMacro + 536895461U, // BGEU + 536895461U, // BGEUImmMacro + 536893976U, // BGEUL + 536893976U, // BGEULImmMacro + 536895342U, // BGT + 536895342U, // BGTImmMacro + 536893964U, // BGTL + 536893964U, // BGTLImmMacro + 536895587U, // BGTU + 536895587U, // BGTUImmMacro + 536893996U, // BGTUL + 536893996U, // BGTULImmMacro + 536891802U, // BLE + 536891802U, // BLEImmMacro + 536893812U, // BLEL + 536893812U, // BLELImmMacro + 536895479U, // BLEU + 536895479U, // BLEUImmMacro + 536893983U, // BLEUL + 536893983U, // BLEULImmMacro + 536895358U, // BLT + 536895358U, // BLTImmMacro + 536893970U, // BLTL + 536893970U, // BLTLImmMacro + 536895599U, // BLTU + 536895599U, // BLTUImmMacro + 536894003U, // BLTUL + 536894003U, // BLTULImmMacro + 536893818U, // BNELImmMacro 0U, // BPOSGE32_PSEUDO - 22080U, // BREAK - 65909U, // BREAK16_MM - 22080U, // BREAK_MM - 2298495719U, // BSELI_B 0U, // BSEL_D_PSEUDO 0U, // BSEL_FD_PSEUDO 0U, // BSEL_FW_PSEUDO 0U, // BSEL_H_PSEUDO - 151018620U, // BSEL_V 0U, // BSEL_W_PSEUDO - 2281718609U, // BSETI_B - 2281720330U, // BSETI_D - 2281721984U, // BSETI_H - 2281725619U, // BSETI_W - 134235275U, // BSET_B - 134237385U, // BSET_D - 134238783U, // BSET_H - 134242762U, // BSET_W - 17797U, // BZ_B - 20217U, // BZ_D - 21357U, // BZ_H - 23698U, // BZ_V - 25457U, // BZ_W - 541278U, // B_MM_Pseudo - 402678723U, // BeqzRxImm16 - 25539U, // BeqzRxImmX16 - 1327710U, // Bimm16 - 541278U, // BimmX16 - 402678696U, // BnezRxImm16 - 25512U, // BnezRxImmX16 - 9368U, // Break16 - 1598417U, // Bteqz16 - 536893428U, // BteqzT8CmpX16 - 536892936U, // BteqzT8CmpiX16 - 536894397U, // BteqzT8SltX16 - 536892966U, // BteqzT8SltiX16 - 536894505U, // BteqzT8SltiuX16 - 536894541U, // BteqzT8SltuX16 - 549841U, // BteqzX16 - 1598390U, // Btnez16 - 671111156U, // BtnezT8CmpX16 - 671110664U, // BtnezT8CmpiX16 - 671112125U, // BtnezT8SltX16 - 671110694U, // BtnezT8SltiX16 - 671112233U, // BtnezT8SltiuX16 - 671112269U, // BtnezT8SltuX16 - 549814U, // BtnezX16 + 0U, // B_MM + 557961U, // B_MMR6_Pseudo + 557961U, // B_MM_Pseudo + 536894300U, // BeqImm + 536891829U, // BneImm + 1073765088U, // BteqzT8CmpX16 + 1073764517U, // BteqzT8CmpiX16 + 1073766275U, // BteqzT8SltX16 + 1073764547U, // BteqzT8SltiX16 + 1073766431U, // BteqzT8SltiuX16 + 1073766517U, // BteqzT8SltuX16 + 1610636000U, // BtnezT8CmpX16 + 1610635429U, // BtnezT8CmpiX16 + 1610637187U, // BtnezT8SltX16 + 1610635459U, // BtnezT8SltiX16 + 1610637343U, // BtnezT8SltiuX16 + 1610637429U, // BtnezT8SltuX16 0U, // BuildPairF64 0U, // BuildPairF64_64 - 85859U, // CACHE - 85859U, // CACHE_MM - 85859U, // CACHE_R6 - 19003U, // CEIL_L_D64 - 23031U, // CEIL_L_S - 20179U, // CEIL_W_D32 - 20179U, // CEIL_W_D64 - 20179U, // CEIL_W_MM - 23353U, // CEIL_W_S - 23353U, // CEIL_W_S_MM - 134234890U, // CEQI_B - 134236627U, // CEQI_D - 134238281U, // CEQI_H - 134241916U, // CEQI_W - 134235044U, // CEQ_B - 134236930U, // CEQ_D - 134238472U, // CEQ_H - 134242192U, // CEQ_W - 16444U, // CFC1 - 16444U, // CFC1_MM - 16968U, // CFCMSA - 134243407U, // CINS - 134243363U, // CINS32 - 19639U, // CLASS_D - 23205U, // CLASS_S - 134235129U, // CLEI_S_B - 134237190U, // CLEI_S_D - 134238606U, // CLEI_S_H - 134242479U, // CLEI_S_W - 2281718992U, // CLEI_U_B - 2281721305U, // CLEI_U_D - 2281722542U, // CLEI_U_H - 2281726595U, // CLEI_U_W - 134235111U, // CLE_S_B - 134237172U, // CLE_S_D - 134238588U, // CLE_S_H - 134242461U, // CLE_S_W - 134235326U, // CLE_U_B - 134237639U, // CLE_U_D - 134238876U, // CLE_U_H - 134242929U, // CLE_U_W - 22452U, // CLO - 22452U, // CLO_MM - 22452U, // CLO_R6 - 134235149U, // CLTI_S_B - 134237210U, // CLTI_S_D - 134238626U, // CLTI_S_H - 134242499U, // CLTI_S_W - 2281719012U, // CLTI_U_B - 2281721325U, // CLTI_U_D - 2281722562U, // CLTI_U_H - 2281726615U, // CLTI_U_W - 134235217U, // CLT_S_B - 134237288U, // CLT_S_D - 134238714U, // CLT_S_H - 134242627U, // CLT_S_W - 134235444U, // CLT_U_B - 134237767U, // CLT_U_D - 134239004U, // CLT_U_H - 134243057U, // CLT_U_W - 25534U, // CLZ - 25534U, // CLZ_MM - 25534U, // CLZ_R6 - 134235667U, // CMPGDU_EQ_QB - 134235572U, // CMPGDU_LE_QB - 134235786U, // CMPGDU_LT_QB - 134235681U, // CMPGU_EQ_QB - 134235586U, // CMPGU_LE_QB - 134235800U, // CMPGU_LT_QB - 17966U, // CMPU_EQ_QB - 17871U, // CMPU_LE_QB - 18085U, // CMPU_LT_QB - 134236919U, // CMP_EQ_D - 21548U, // CMP_EQ_PH - 134240864U, // CMP_EQ_S - 134236489U, // CMP_F_D - 134240675U, // CMP_F_S - 134236333U, // CMP_LE_D - 21444U, // CMP_LE_PH - 134240596U, // CMP_LE_S - 134237410U, // CMP_LT_D - 21717U, // CMP_LT_PH - 134240959U, // CMP_LT_S - 134236507U, // CMP_SAF_D - 134240685U, // CMP_SAF_S - 134236946U, // CMP_SEQ_D - 134240883U, // CMP_SEQ_S - 134236370U, // CMP_SLE_D - 134240625U, // CMP_SLE_S - 134237437U, // CMP_SLT_D - 134240978U, // CMP_SLT_S - 134236994U, // CMP_SUEQ_D - 134240914U, // CMP_SUEQ_S - 134236418U, // CMP_SULE_D - 134240656U, // CMP_SULE_S - 134237485U, // CMP_SULT_D - 134241009U, // CMP_SULT_S - 134236876U, // CMP_SUN_D - 134240837U, // CMP_SUN_S - 134236974U, // CMP_UEQ_D - 134240903U, // CMP_UEQ_S - 134236398U, // CMP_ULE_D - 134240645U, // CMP_ULE_S - 134237465U, // CMP_ULT_D - 134240998U, // CMP_ULT_S - 134236858U, // CMP_UN_D - 134240827U, // CMP_UN_S - 9454U, // CONSTPOOL_ENTRY + 26841U, // CFTC1 + 10989U, // CONSTPOOL_ENTRY 0U, // COPY_FD_PSEUDO 0U, // COPY_FW_PSEUDO - 2952807544U, // COPY_S_B - 2952809637U, // COPY_S_D - 2952811052U, // COPY_S_H - 2952814987U, // COPY_S_W - 2952807759U, // COPY_U_B - 2952810104U, // COPY_U_D - 2952811319U, // COPY_U_H - 2952815394U, // COPY_U_W - 1867863U, // CTC1 - 1867863U, // CTC1_MM - 16976U, // CTCMSA - 22833U, // CVT_D32_S - 23896U, // CVT_D32_W - 23896U, // CVT_D32_W_MM - 22087U, // CVT_D64_L - 22833U, // CVT_D64_S - 23896U, // CVT_D64_W - 22833U, // CVT_D_S_MM - 19024U, // CVT_L_D64 - 19024U, // CVT_L_D64_MM - 23052U, // CVT_L_S - 23052U, // CVT_L_S_MM - 19362U, // CVT_S_D32 - 19362U, // CVT_S_D32_MM - 19362U, // CVT_S_D64 - 22096U, // CVT_S_L - 24651U, // CVT_S_W - 24651U, // CVT_S_W_MM - 20200U, // CVT_W_D32 - 20200U, // CVT_W_D64 - 20200U, // CVT_W_MM - 23374U, // CVT_W_S - 23374U, // CVT_W_S_MM - 19183U, // C_EQ_D32 - 19183U, // C_EQ_D64 - 23128U, // C_EQ_S - 18754U, // C_F_D32 - 18754U, // C_F_D64 - 22940U, // C_F_S - 18597U, // C_LE_D32 - 18597U, // C_LE_D64 - 22860U, // C_LE_S - 19674U, // C_LT_D32 - 19674U, // C_LT_D64 - 23223U, // C_LT_S - 18588U, // C_NGE_D32 - 18588U, // C_NGE_D64 - 22851U, // C_NGE_S - 18623U, // C_NGLE_D32 - 18623U, // C_NGLE_D64 - 22878U, // C_NGLE_S - 19040U, // C_NGL_D32 - 19040U, // C_NGL_D64 - 23068U, // C_NGL_S - 19665U, // C_NGT_D32 - 19665U, // C_NGT_D64 - 23214U, // C_NGT_S - 18633U, // C_OLE_D32 - 18633U, // C_OLE_D64 - 22888U, // C_OLE_S - 19700U, // C_OLT_D32 - 19700U, // C_OLT_D64 - 23241U, // C_OLT_S - 19209U, // C_SEQ_D32 - 19209U, // C_SEQ_D64 - 23146U, // C_SEQ_S - 18824U, // C_SF_D32 - 18824U, // C_SF_D64 - 22986U, // C_SF_S - 19237U, // C_UEQ_D32 - 19237U, // C_UEQ_D64 - 23166U, // C_UEQ_S - 18661U, // C_ULE_D32 - 18661U, // C_ULE_D64 - 22908U, // C_ULE_S - 19728U, // C_ULT_D32 - 19728U, // C_ULT_D64 - 23261U, // C_ULT_S - 19122U, // C_UN_D32 - 19122U, // C_UN_D64 - 23091U, // C_UN_S - 22516U, // CmpRxRy16 - 939546120U, // CmpiRxImm16 - 22024U, // CmpiRxImmX16 - 549945U, // Constant32 - 134237991U, // DADD - 134239684U, // DADDi - 134241306U, // DADDiu - 134241267U, // DADDu - 8689123U, // DAHI - 134240165U, // DALIGN - 8689184U, // DATI - 134239794U, // DAUI - 22476U, // DBITSWAP - 22451U, // DCLO - 22451U, // DCLO_R6 - 25533U, // DCLZ - 25533U, // DCLZ_R6 - 134241469U, // DDIV - 134241377U, // DDIVU - 9480U, // DERET - 9480U, // DERET_MM - 134243425U, // DEXT - 134243400U, // DEXTM - 134243438U, // DEXTU - 546247U, // DI - 134243413U, // DINS - 134243393U, // DINSM - 134243431U, // DINSU - 134241470U, // DIV - 134241378U, // DIVU - 134235238U, // DIV_S_B - 134237331U, // DIV_S_D - 134238735U, // DIV_S_H - 134242670U, // DIV_S_W - 134235453U, // DIV_U_B - 134237798U, // DIV_U_D - 134239013U, // DIV_U_H - 134243088U, // DIV_U_W - 546247U, // DI_MM - 134234690U, // DLSA - 134234690U, // DLSA_R6 - 134234121U, // DMFC0 - 16450U, // DMFC1 - 134234372U, // DMFC2 - 134238036U, // DMOD - 134241281U, // DMODU - 134234128U, // DMTC0 - 1867869U, // DMTC1 - 134234379U, // DMTC2 - 134239671U, // DMUH - 134241299U, // DMUHU - 134240103U, // DMUL - 23495U, // DMULT - 23641U, // DMULTu - 134241343U, // DMULU - 134240103U, // DMUL_R6 - 134237239U, // DOTP_S_D - 134238655U, // DOTP_S_H - 134242538U, // DOTP_S_W - 134237706U, // DOTP_U_D - 134238943U, // DOTP_U_H - 134242996U, // DOTP_U_W - 151014368U, // DPADD_S_D - 151015784U, // DPADD_S_H - 151019657U, // DPADD_S_W - 151014835U, // DPADD_U_D - 151016072U, // DPADD_U_H - 151020125U, // DPADD_U_W - 134239524U, // DPAQX_SA_W_PH - 134239607U, // DPAQX_S_W_PH - 134241998U, // DPAQ_SA_L_W - 134239566U, // DPAQ_S_W_PH - 134239859U, // DPAU_H_QBL - 134240355U, // DPAU_H_QBR - 134239645U, // DPAX_W_PH - 134239514U, // DPA_W_PH - 22521U, // DPOP - 134239539U, // DPSQX_SA_W_PH - 134239621U, // DPSQX_S_W_PH - 134242011U, // DPSQ_SA_L_W - 134239594U, // DPSQ_S_W_PH - 151014335U, // DPSUB_S_D - 151015763U, // DPSUB_S_H - 151019624U, // DPSUB_S_W - 151014802U, // DPSUB_U_D - 151016051U, // DPSUB_U_H - 151020092U, // DPSUB_U_W - 134239871U, // DPSU_H_QBL - 134240367U, // DPSU_H_QBR - 134239656U, // DPSX_W_PH - 134239635U, // DPS_W_PH - 134240512U, // DROTR - 134234351U, // DROTR32 - 134241513U, // DROTRV - 21370U, // DSBH - 25610U, // DSDIV - 20275U, // DSHD - 134240057U, // DSLL - 134234321U, // DSLL32 - 1073764153U, // DSLL64_32 - 134241475U, // DSLLV - 134234684U, // DSRA - 134234303U, // DSRA32 - 134241454U, // DSRAV - 134240069U, // DSRL - 134234329U, // DSRL32 - 134241482U, // DSRLV - 134235901U, // DSUB - 134241246U, // DSUBu - 25596U, // DUDIV - 25611U, // DivRxRy16 - 25597U, // DivuRxRy16 - 9438U, // EHB - 9438U, // EHB_MM - 546259U, // EI - 546259U, // EI_MM - 9481U, // ERET - 9481U, // ERET_MM - 134243426U, // EXT - 134240324U, // EXTP - 134240221U, // EXTPDP - 134241497U, // EXTPDPV - 134241506U, // EXTPV - 134242731U, // EXTRV_RS_W - 134242285U, // EXTRV_R_W - 134238744U, // EXTRV_S_H - 134243168U, // EXTRV_W - 134242720U, // EXTR_RS_W - 134242264U, // EXTR_R_W - 134238675U, // EXTR_S_H - 134242363U, // EXTR_W - 134243419U, // EXTS - 134243371U, // EXTS32 - 134243426U, // EXT_MM + 17885415U, // CTTC1 + 551167U, // Constant32 + 536893990U, // DMULImmMacro + 536893990U, // DMULMacro + 536894129U, // DMULOMacro + 536895562U, // DMULOUMacro + 536893929U, // DROL + 536893929U, // DROLImm + 536894467U, // DROR + 536894467U, // DRORImm + 536895724U, // DSDivIMacro + 536895724U, // DSDivMacro + 536894048U, // DSRemIMacro + 536894048U, // DSRemMacro + 536895632U, // DUDivIMacro + 536895632U, // DUDivMacro + 536895555U, // DURemIMacro + 536895555U, // DURemMacro + 0U, // ERet 0U, // ExtractElementF64 0U, // ExtractElementF64_64 0U, // FABS_D - 19631U, // FABS_D32 - 19631U, // FABS_D64 - 19631U, // FABS_MM - 23198U, // FABS_S - 23198U, // FABS_S_MM 0U, // FABS_W - 134236265U, // FADD_D - 134236266U, // FADD_D32 - 134236266U, // FADD_D64 - 134236266U, // FADD_MM - 134240572U, // FADD_S - 134240572U, // FADD_S_MM - 134241633U, // FADD_W - 134236499U, // FCAF_D - 134241752U, // FCAF_W - 134236929U, // FCEQ_D - 134242191U, // FCEQ_W - 19638U, // FCLASS_D - 25015U, // FCLASS_W - 134236343U, // FCLE_D - 134241675U, // FCLE_W - 134237420U, // FCLT_D - 134242770U, // FCLT_W - 2204821U, // FCMP_D32 - 2204821U, // FCMP_D32_MM - 2204821U, // FCMP_D64 - 2466965U, // FCMP_S32 - 2466965U, // FCMP_S32_MM - 134236439U, // FCNE_D - 134241709U, // FCNE_W - 134237039U, // FCOR_D - 134242320U, // FCOR_W - 134236985U, // FCUEQ_D - 134242207U, // FCUEQ_W - 134236409U, // FCULE_D - 134241691U, // FCULE_W - 134237476U, // FCULT_D - 134242786U, // FCULT_W - 134236455U, // FCUNE_D - 134241725U, // FCUNE_W - 134236868U, // FCUN_D - 134242097U, // FCUN_W - 134237862U, // FDIV_D - 134237863U, // FDIV_D32 - 134237863U, // FDIV_D64 - 134237863U, // FDIV_MM - 134241045U, // FDIV_S - 134241045U, // FDIV_S_MM - 134243152U, // FDIV_W - 134238402U, // FEXDO_H - 134242113U, // FEXDO_W - 134236152U, // FEXP2_D 0U, // FEXP2_D_1_PSEUDO - 134241536U, // FEXP2_W 0U, // FEXP2_W_1_PSEUDO - 19064U, // FEXUPL_D - 24311U, // FEXUPL_W - 19327U, // FEXUPR_D - 24608U, // FEXUPR_W - 19569U, // FFINT_S_D - 24908U, // FFINT_S_W - 20048U, // FFINT_U_D - 25338U, // FFINT_U_W - 19074U, // FFQL_D - 24321U, // FFQL_W - 19337U, // FFQR_D - 24618U, // FFQR_W - 17277U, // FILL_B - 19049U, // FILL_D 0U, // FILL_FD_PSEUDO 0U, // FILL_FW_PSEUDO - 20635U, // FILL_H - 24296U, // FILL_W - 18415U, // FLOG2_D - 23799U, // FLOG2_W - 19013U, // FLOOR_L_D64 - 23041U, // FLOOR_L_S - 20189U, // FLOOR_W_D32 - 20189U, // FLOOR_W_D64 - 20189U, // FLOOR_W_MM - 23363U, // FLOOR_W_S - 23363U, // FLOOR_W_S_MM - 151013489U, // FMADD_D - 151018857U, // FMADD_W - 134236190U, // FMAX_A_D - 134241574U, // FMAX_A_W - 134237937U, // FMAX_D - 134243177U, // FMAX_W - 134236170U, // FMIN_A_D - 134241554U, // FMIN_A_W - 134236842U, // FMIN_D - 134242089U, // FMIN_W - 20150U, // FMOV_D32 - 20150U, // FMOV_D32_MM - 20150U, // FMOV_D64 - 23324U, // FMOV_S - 23324U, // FMOV_S_MM - 151013447U, // FMSUB_D - 151018815U, // FMSUB_W - 134236826U, // FMUL_D - 134236827U, // FMUL_D32 - 134236827U, // FMUL_D64 - 134236827U, // FMUL_MM - 134240805U, // FMUL_S - 134240805U, // FMUL_S_MM - 134242073U, // FMUL_W - 18841U, // FNEG_D32 - 18841U, // FNEG_D64 - 18841U, // FNEG_MM - 23002U, // FNEG_S - 23002U, // FNEG_S_MM - 19175U, // FRCP_D - 24394U, // FRCP_W - 19786U, // FRINT_D - 25084U, // FRINT_W - 19814U, // FRSQRT_D - 25112U, // FRSQRT_W - 134236518U, // FSAF_D - 134241760U, // FSAF_W - 134236957U, // FSEQ_D - 134242199U, // FSEQ_W - 134236381U, // FSLE_D - 134241683U, // FSLE_W - 134237448U, // FSLT_D - 134242778U, // FSLT_W - 134236447U, // FSNE_D - 134241717U, // FSNE_W - 134237047U, // FSOR_D - 134242328U, // FSOR_W - 19805U, // FSQRT_D - 19806U, // FSQRT_D32 - 19806U, // FSQRT_D64 - 19806U, // FSQRT_MM - 23301U, // FSQRT_S - 23301U, // FSQRT_S_MM - 25103U, // FSQRT_W - 134236223U, // FSUB_D - 134236224U, // FSUB_D32 - 134236224U, // FSUB_D64 - 134236224U, // FSUB_MM - 134240554U, // FSUB_S - 134240554U, // FSUB_S_MM - 134241591U, // FSUB_W - 134237006U, // FSUEQ_D - 134242216U, // FSUEQ_W - 134236430U, // FSULE_D - 134241700U, // FSULE_W - 134237497U, // FSULT_D - 134242795U, // FSULT_W - 134236464U, // FSUNE_D - 134241734U, // FSUNE_W - 134236887U, // FSUN_D - 134242105U, // FSUN_W - 19580U, // FTINT_S_D - 24919U, // FTINT_S_W - 20059U, // FTINT_U_D - 25349U, // FTINT_U_W - 134238479U, // FTQ_H - 134242225U, // FTQ_W - 19402U, // FTRUNC_S_D - 24691U, // FTRUNC_S_W - 19869U, // FTRUNC_U_D - 25159U, // FTRUNC_U_W - 1224758783U, // GotPrologue16 - 134237142U, // HADD_S_D - 134238558U, // HADD_S_H - 134242431U, // HADD_S_W - 134237609U, // HADD_U_D - 134238846U, // HADD_U_H - 134242899U, // HADD_U_W - 134237109U, // HSUB_S_D - 134238537U, // HSUB_S_H - 134242398U, // HSUB_S_W - 134237576U, // HSUB_U_D - 134238825U, // HSUB_U_H - 134242866U, // HSUB_U_W - 134235508U, // ILVEV_B - 134237853U, // ILVEV_D - 134239068U, // ILVEV_H - 134243143U, // ILVEV_W - 134235036U, // ILVL_B - 134236834U, // ILVL_D - 134238394U, // ILVL_H - 134242081U, // ILVL_W - 134234788U, // ILVOD_B - 134236307U, // ILVOD_D - 134238196U, // ILVOD_H - 134241666U, // ILVOD_W - 134235084U, // ILVR_B - 134237082U, // ILVR_D - 134238519U, // ILVR_H - 134242371U, // ILVR_W - 134243408U, // INS - 44582043U, // INSERT_B + 2181060764U, // GotPrologue16 + 0U, // INSERT_B_VIDX64_PSEUDO 0U, // INSERT_B_VIDX_PSEUDO - 44584275U, // INSERT_D + 0U, // INSERT_D_VIDX64_PSEUDO 0U, // INSERT_D_VIDX_PSEUDO 0U, // INSERT_FD_PSEUDO + 0U, // INSERT_FD_VIDX64_PSEUDO 0U, // INSERT_FD_VIDX_PSEUDO 0U, // INSERT_FW_PSEUDO + 0U, // INSERT_FW_VIDX64_PSEUDO 0U, // INSERT_FW_VIDX_PSEUDO - 44585551U, // INSERT_H + 0U, // INSERT_H_VIDX64_PSEUDO 0U, // INSERT_H_VIDX_PSEUDO - 44589573U, // INSERT_W + 0U, // INSERT_W_VIDX64_PSEUDO 0U, // INSERT_W_VIDX_PSEUDO - 16801009U, // INSV - 52970157U, // INSVE_B - 52971833U, // INSVE_D - 52973565U, // INSVE_H - 52977103U, // INSVE_W - 134243408U, // INS_MM - 546365U, // J - 546398U, // JAL - 22768U, // JALR - 547056U, // JALR16_MM - 22768U, // JALR64 0U, // JALR64Pseudo + 0U, // JALRCPseudo + 0U, // JALRHB64Pseudo + 0U, // JALRHBPseudo 0U, // JALRPseudo - 541104U, // JALRS16_MM - 23442U, // JALRS_MM - 17822U, // JALR_HB - 22768U, // JALR_MM - 547706U, // JALS_MM - 549771U, // JALX - 549771U, // JALX_MM - 546398U, // JAL_MM - 18212U, // JIALC - 18201U, // JIC - 547052U, // JR - 541091U, // JR16_MM - 547052U, // JR64 - 546873U, // JRADDIUSP - 542610U, // JRC16_MM - 542103U, // JR_HB - 542103U, // JR_HB_R6 - 547052U, // JR_MM - 546365U, // J_MM - 2905694U, // Jal16 - 3167838U, // JalB16 - 546398U, // JalOneReg - 22110U, // JalTwoReg - 9430U, // JrRa16 - 9421U, // JrcRa16 - 549872U, // JrcRx16 - 540673U, // JumpLinkReg16 - 58738087U, // LB - 58738087U, // LB64 - 58737088U, // LBU16_MM - 1358979985U, // LBUX - 58738087U, // LB_MM - 58743769U, // LBu - 58743769U, // LBu64 - 58743769U, // LBu_MM - 58740538U, // LD - 58736688U, // LDC1 - 58736688U, // LDC164 - 58736688U, // LDC1_MM - 58736888U, // LDC2 - 58736888U, // LDC2_R6 - 58736947U, // LDC3 - 17103U, // LDI_B - 18857U, // LDI_D - 20511U, // LDI_H - 24146U, // LDI_W - 58742458U, // LDL - 18273U, // LDPC - 58742954U, // LDR - 1358970992U, // LDXC1 - 1358970992U, // LDXC164 - 58737301U, // LD_B - 58738820U, // LD_D - 58740709U, // LD_H - 58744179U, // LD_W - 25189403U, // LEA_ADDiu - 25189402U, // LEA_ADDiu64 - 25189403U, // LEA_ADDiu_MM - 58741643U, // LH - 58741643U, // LH64 - 58737111U, // LHU16_MM - 1358979974U, // LHX - 58741643U, // LH_MM - 58743822U, // LHu - 58743822U, // LHu64 - 58743822U, // LHu_MM - 16751U, // LI16_MM - 58742563U, // LL - 58740537U, // LLD - 58740537U, // LLD_R6 - 58742563U, // LL_MM - 58742563U, // LL_R6 - 58736647U, // LOAD_ACC128 - 58736647U, // LOAD_ACC64 - 58736647U, // LOAD_ACC64DSP - 58742794U, // LOAD_CCOND_DSP + 0U, // JAL_MMR6 + 547080U, // JalOneReg + 22792U, // JalTwoReg + 50358523U, // LDMacro + 0U, // LDR_D + 0U, // LDR_W + 0U, // LD_F16 + 50348037U, // LOAD_ACC128 + 50348037U, // LOAD_ACC64 + 50348037U, // LOAD_ACC64DSP + 50354934U, // LOAD_CCOND_DSP 0U, // LONG_BRANCH_ADDiu + 0U, // LONG_BRANCH_ADDiu2Op 0U, // LONG_BRANCH_DADDiu + 0U, // LONG_BRANCH_DADDiu2Op 0U, // LONG_BRANCH_LUi - 134234691U, // LSA - 134234691U, // LSA_R6 - 1358971006U, // LUXC1 - 1358971006U, // LUXC164 - 1358971006U, // LUXC1_MM - 33576504U, // LUi - 33576504U, // LUi64 - 33576504U, // LUi_MM - 58745726U, // LW - 58737118U, // LW16_MM - 58745726U, // LW64 - 58736740U, // LWC1 - 58736740U, // LWC1_MM - 58736914U, // LWC2 - 58736914U, // LWC2_R6 - 58736959U, // LWC3 - 58745726U, // LWGP_MM - 58742637U, // LWL - 58742637U, // LWL64 - 58742637U, // LWL_MM - 3522956U, // LWM16_MM - 3522785U, // LWM32_MM - 3528595U, // LWM_MM - 18310U, // LWPC - 137290U, // LWP_MM - 58743054U, // LWR - 58743054U, // LWR64 - 58743054U, // LWR_MM - 58745726U, // LWSP_MM - 18303U, // LWUPC - 58743912U, // LWU_MM - 1358979991U, // LWX - 1358971020U, // LWXC1 - 1358971020U, // LWXC1_MM - 1358977945U, // LWXS_MM - 58745726U, // LW_MM - 58743912U, // LWu - 58738087U, // LbRxRyOffMemX16 - 58743769U, // LbuRxRyOffMemX16 - 58741643U, // LhRxRyOffMemX16 - 58743822U, // LhuRxRyOffMemX16 - 939546111U, // LiRxImm16 - 22005U, // LiRxImmAlignX16 - 22015U, // LiRxImmX16 - 33571334U, // LoadAddr32Imm - 58737158U, // LoadAddr32Reg - 33576447U, // LoadImm32Reg - 22019U, // LoadImm64Reg - 3695486U, // LwConstant32 - 268460926U, // LwRxPcTcp16 - 25470U, // LwRxPcTcpX16 - 58745726U, // LwRxRyOffMemX16 - 1493197694U, // LwRxSpImmX16 - 20269U, // MADD - 151013751U, // MADDF_D - 151017921U, // MADDF_S - 151015667U, // MADDR_Q_H - 151019386U, // MADDR_Q_W - 23546U, // MADDU - 134241274U, // MADDU_DSP - 23546U, // MADDU_MM - 151012706U, // MADDV_B - 151015051U, // MADDV_D - 151016266U, // MADDV_H - 151020341U, // MADDV_W - 134236274U, // MADD_D32 - 134236274U, // MADD_D32_MM - 134236274U, // MADD_D64 - 134237997U, // MADD_DSP - 20269U, // MADD_MM - 151015637U, // MADD_Q_H - 151019356U, // MADD_Q_W - 134240571U, // MADD_S - 134240571U, // MADD_S_MM - 134239974U, // MAQ_SA_W_PHL - 134240436U, // MAQ_SA_W_PHR - 134240002U, // MAQ_S_W_PHL - 134240464U, // MAQ_S_W_PHR - 134236215U, // MAXA_D - 134240544U, // MAXA_S - 134235159U, // MAXI_S_B - 134237220U, // MAXI_S_D - 134238636U, // MAXI_S_H - 134242509U, // MAXI_S_W - 2281719022U, // MAXI_U_B - 2281721335U, // MAXI_U_D - 2281722572U, // MAXI_U_H - 2281726625U, // MAXI_U_W - 134234740U, // MAX_A_B - 134236191U, // MAX_A_D - 134238148U, // MAX_A_H - 134241575U, // MAX_A_W - 134237938U, // MAX_D - 134241111U, // MAX_S - 134235247U, // MAX_S_B - 134237340U, // MAX_S_D - 134238755U, // MAX_S_H - 134242690U, // MAX_S_W - 134235462U, // MAX_U_B - 134237807U, // MAX_U_D - 134239022U, // MAX_U_H - 134243097U, // MAX_U_W - 134234122U, // MFC0 - 16451U, // MFC1 - 16451U, // MFC1_MM - 134234373U, // MFC2 - 16457U, // MFHC1_D32 - 16457U, // MFHC1_D64 - 16457U, // MFHC1_MM - 546281U, // MFHI - 546281U, // MFHI16_MM - 546281U, // MFHI64 - 21993U, // MFHI_DSP - 546281U, // MFHI_MM - 546745U, // MFLO - 546745U, // MFLO16_MM - 546745U, // MFLO64 - 22457U, // MFLO_DSP - 546745U, // MFLO_MM - 134236200U, // MINA_D - 134240536U, // MINA_S - 134235139U, // MINI_S_B - 134237200U, // MINI_S_D - 134238616U, // MINI_S_H - 134242489U, // MINI_S_W - 2281719002U, // MINI_U_B - 2281721315U, // MINI_U_D - 2281722552U, // MINI_U_H - 2281726605U, // MINI_U_W - 134234721U, // MIN_A_B - 134236171U, // MIN_A_D - 134238129U, // MIN_A_H - 134241555U, // MIN_A_W - 134236843U, // MIN_D - 134240812U, // MIN_S - 134235169U, // MIN_S_B - 134237230U, // MIN_S_D - 134238646U, // MIN_S_H - 134242529U, // MIN_S_W - 134235384U, // MIN_U_B - 134237697U, // MIN_U_D - 134238934U, // MIN_U_H - 134242987U, // MIN_U_W + 0U, // LONG_BRANCH_LUi2Op + 0U, // LONG_BRANCH_LUi2Op_64 + 72310U, // LWM_MM + 17196U, // LoadAddrImm32 + 17217U, // LoadAddrImm64 + 50348844U, // LoadAddrReg32 + 50348865U, // LoadAddrReg64 + 22684U, // LoadImm32 + 22688U, // LoadImm64 + 19348U, // LoadImmDoubleFGR + 19348U, // LoadImmDoubleFGR_32 + 19348U, // LoadImmDoubleGPR + 23819U, // LoadImmSingleFGR + 23819U, // LoadImmSingleGPR + 0U, // LoadJumpTableOffset + 1599429U, // LwConstant32 + 26979U, // MFTACX + 26979U, // MFTACX_NM + 536897723U, // MFTC0 + 536897723U, // MFTC0_NM + 26848U, // MFTC1 + 551212U, // MFTDSP + 551212U, // MFTDSP_NM + 26957U, // MFTGPR + 26957U, // MFTGPR_NM + 26825U, // MFTHC1 + 26896U, // MFTHI + 26896U, // MFTHI_NM + 26910U, // MFTLO + 26910U, // MFTLO_NM 0U, // MIPSeh_return32 0U, // MIPSeh_return64 - 134238037U, // MOD - 134235899U, // MODSUB - 134241282U, // MODU - 134235102U, // MOD_S_B - 134237163U, // MOD_S_D - 134238579U, // MOD_S_H - 134242452U, // MOD_S_W - 134235317U, // MOD_U_B - 134237630U, // MOD_U_D - 134238867U, // MOD_U_H - 134242920U, // MOD_U_W - 20345U, // MOVE16_MM - 67491813U, // MOVEP_MM - 23668U, // MOVE_V - 134236560U, // MOVF_D32 - 134236560U, // MOVF_D32_MM - 134236560U, // MOVF_D64 - 134238109U, // MOVF_I - 134238109U, // MOVF_I64 - 134238109U, // MOVF_I_MM - 134240722U, // MOVF_S - 134240722U, // MOVF_S_MM - 134236895U, // MOVN_I64_D64 - 134240173U, // MOVN_I64_I - 134240173U, // MOVN_I64_I64 - 134240848U, // MOVN_I64_S - 134236895U, // MOVN_I_D32 - 134236895U, // MOVN_I_D32_MM - 134236895U, // MOVN_I_D64 - 134240173U, // MOVN_I_I - 134240173U, // MOVN_I_I64 - 134240173U, // MOVN_I_MM - 134240848U, // MOVN_I_S - 134240848U, // MOVN_I_S_MM - 134237558U, // MOVT_D32 - 134237558U, // MOVT_D32_MM - 134237558U, // MOVT_D64 - 134241235U, // MOVT_I - 134241235U, // MOVT_I64 - 134241235U, // MOVT_I_MM - 134241037U, // MOVT_S - 134241037U, // MOVT_S_MM - 134237978U, // MOVZ_I64_D64 - 134243300U, // MOVZ_I64_I - 134243300U, // MOVZ_I64_I64 - 134241138U, // MOVZ_I64_S - 134237978U, // MOVZ_I_D32 - 134237978U, // MOVZ_I_D32_MM - 134237978U, // MOVZ_I_D64 - 134243300U, // MOVZ_I_I - 134243300U, // MOVZ_I_I64 - 134243300U, // MOVZ_I_MM - 134241138U, // MOVZ_I_S - 134241138U, // MOVZ_I_S_MM - 18179U, // MSUB - 151013742U, // MSUBF_D - 151017912U, // MSUBF_S - 151015656U, // MSUBR_Q_H - 151019375U, // MSUBR_Q_W - 23525U, // MSUBU - 134241253U, // MSUBU_DSP - 23525U, // MSUBU_MM - 151012697U, // MSUBV_B - 151015042U, // MSUBV_D - 151016257U, // MSUBV_H - 151020332U, // MSUBV_W - 134236232U, // MSUB_D32 - 134236232U, // MSUB_D32_MM - 134236232U, // MSUB_D64 - 134235907U, // MSUB_DSP - 18179U, // MSUB_MM - 151015627U, // MSUB_Q_H - 151019346U, // MSUB_Q_W - 134240553U, // MSUB_S - 134240553U, // MSUB_S_MM - 134234129U, // MTC0 - 1867870U, // MTC1 - 1867870U, // MTC1_MM - 134234380U, // MTC2 - 1884240U, // MTHC1_D32 - 1884240U, // MTHC1_D64 - 1884240U, // MTHC1_MM - 546287U, // MTHI - 546287U, // MTHI64 - 1873391U, // MTHI_DSP - 546287U, // MTHI_MM - 1873900U, // MTHLIP - 546758U, // MTLO - 546758U, // MTLO64 - 1873862U, // MTLO_DSP - 546758U, // MTLO_MM - 540701U, // MTM0 - 540826U, // MTM1 - 540958U, // MTM2 - 540707U, // MTP0 - 540832U, // MTP1 - 540964U, // MTP2 - 134239672U, // MUH - 134241300U, // MUHU - 134240104U, // MUL - 134240015U, // MULEQ_S_W_PHL - 134240477U, // MULEQ_S_W_PHR - 134239883U, // MULEU_S_PH_QBL - 134240379U, // MULEU_S_PH_QBR - 134239433U, // MULQ_RS_PH - 134242709U, // MULQ_RS_W - 134239377U, // MULQ_S_PH - 134242568U, // MULQ_S_W - 134238462U, // MULR_Q_H - 134242181U, // MULR_Q_W - 134239579U, // MULSAQ_S_W_PH - 134239554U, // MULSA_W_PH - 23496U, // MULT - 134241370U, // MULTU_DSP - 134241224U, // MULT_DSP - 23496U, // MULT_MM - 23642U, // MULTu - 23642U, // MULTu_MM - 134241337U, // MULU - 134235517U, // MULV_B - 134237870U, // MULV_D - 134239077U, // MULV_H - 134243160U, // MULV_W - 134240104U, // MUL_MM - 134239250U, // MUL_PH - 134238431U, // MUL_Q_H - 134242150U, // MUL_Q_W - 134240104U, // MUL_R6 - 134239345U, // MUL_S_PH - 546281U, // Mfhi16 - 546745U, // Mflo16 - 20345U, // Move32R16 - 20345U, // MoveR3216 - 23496U, // MultRxRy16 - 75799496U, // MultRxRyRz16 - 23642U, // MultuRxRy16 - 75799642U, // MultuRxRyRz16 - 17028U, // NLOC_B - 18521U, // NLOC_D - 20436U, // NLOC_H - 23880U, // NLOC_W - 17036U, // NLZC_B - 18529U, // NLZC_D - 20444U, // NLZC_H - 23888U, // NLZC_W - 134236282U, // NMADD_D32 - 134236282U, // NMADD_D32_MM - 134236282U, // NMADD_D64 - 134240570U, // NMADD_S - 134240570U, // NMADD_S_MM - 134236240U, // NMSUB_D32 - 134236240U, // NMSUB_D32_MM - 134236240U, // NMSUB_D64 - 134240552U, // NMSUB_S - 134240552U, // NMSUB_S_MM + 0U, // MSA_FP_EXTEND_D_PSEUDO + 0U, // MSA_FP_EXTEND_W_PSEUDO + 0U, // MSA_FP_ROUND_D_PSEUDO + 0U, // MSA_FP_ROUND_W_PSEUDO + 17885547U, // MTTACX + 17885547U, // MTTACX_NM + 2752571586U, // MTTC0 + 2752571586U, // MTTC0_NM + 17885422U, // MTTC1 + 551220U, // MTTDSP + 551220U, // MTTDSP_NM + 17885525U, // MTTGPR + 17885525U, // MTTGPR_NM + 17885393U, // MTTHC1 + 17885463U, // MTTHI + 17885463U, // MTTHI_NM + 17885477U, // MTTLO + 17885477U, // MTTLO_NM + 536893991U, // MULImmMacro + 536894130U, // MULOMacro + 536895563U, // MULOUMacro + 0U, // MUSTTAILCALLREG_NM + 0U, // MUSTTAILCALL_NM + 24462U, // MultRxRy16 + 86040462U, // MultRxRyRz16 + 24706U, // MultuRxRy16 + 86040706U, // MultuRxRyRz16 0U, // NOP - 134240502U, // NOR - 134240502U, // NOR64 - 2281718573U, // NORI_B - 134240502U, // NOR_MM - 134241412U, // NOR_V + 536894462U, // NORImm + 536894462U, // NORImm64 0U, // NOR_V_D_PSEUDO 0U, // NOR_V_H_PSEUDO 0U, // NOR_V_W_PSEUDO - 16825U, // NOT16_MM - 20387U, // NegRxRy16 - 23502U, // NotRxRy16 - 134240503U, // OR - 836010U, // OR16_MM - 134240503U, // OR64 - 2281718574U, // ORI_B - 134240503U, // OR_MM - 134241413U, // OR_V 0U, // OR_V_D_PSEUDO 0U, // OR_V_H_PSEUDO 0U, // OR_V_W_PSEUDO - 134239771U, // ORi - 134239771U, // ORi64 - 134239771U, // ORi_MM - 16799991U, // OrRxRxRy16 - 134239239U, // PACKRL_PH - 9442U, // PAUSE - 9442U, // PAUSE_MM - 134235499U, // PCKEV_B - 134237844U, // PCKEV_D - 134239059U, // PCKEV_H - 134243134U, // PCKEV_W - 134234779U, // PCKOD_B - 134236298U, // PCKOD_D - 134238187U, // PCKOD_H - 134241657U, // PCKOD_W - 17555U, // PCNT_B - 19778U, // PCNT_D - 21063U, // PCNT_H - 25076U, // PCNT_W - 134239203U, // PICK_PH - 134235631U, // PICK_QB - 22522U, // POP - 22186U, // PRECEQU_PH_QBL - 16906U, // PRECEQU_PH_QBLA - 22682U, // PRECEQU_PH_QBR - 16939U, // PRECEQU_PH_QBRA - 22260U, // PRECEQ_W_PHL - 22722U, // PRECEQ_W_PHR - 22171U, // PRECEU_PH_QBL - 16890U, // PRECEU_PH_QBLA - 22667U, // PRECEU_PH_QBR - 16923U, // PRECEU_PH_QBRA - 134239155U, // PRECRQU_S_QB_PH - 134241800U, // PRECRQ_PH_W - 134239128U, // PRECRQ_QB_PH - 134241831U, // PRECRQ_RS_PH_W - 134239142U, // PRECR_QB_PH - 134241784U, // PRECR_SRA_PH_W - 134241813U, // PRECR_SRA_R_PH_W - 85911U, // PREF - 85911U, // PREF_MM - 85911U, // PREF_R6 - 134238019U, // PREPEND + 536895505U, // PseudoADDIU_NM + 536893544U, // PseudoANDI_NM 0U, // PseudoCMPU_EQ_QB 0U, // PseudoCMPU_LE_QB 0U, // PseudoCMPU_LT_QB 0U, // PseudoCMP_EQ_PH 0U, // PseudoCMP_LE_PH 0U, // PseudoCMP_LT_PH - 16391U, // PseudoCVT_D32_W - 16391U, // PseudoCVT_D64_L - 16391U, // PseudoCVT_D64_W - 16391U, // PseudoCVT_S_L - 16391U, // PseudoCVT_S_W + 16389U, // PseudoCVT_D32_W + 16389U, // PseudoCVT_D64_L + 16389U, // PseudoCVT_D64_W + 16389U, // PseudoCVT_S_L + 16389U, // PseudoCVT_S_W 0U, // PseudoDMULT 0U, // PseudoDMULTu 0U, // PseudoDSDIV 0U, // PseudoDUDIV + 0U, // PseudoD_SELECT_I + 0U, // PseudoD_SELECT_I64 0U, // PseudoIndirectBranch 0U, // PseudoIndirectBranch64 + 0U, // PseudoIndirectBranch64R6 + 0U, // PseudoIndirectBranchNM + 0U, // PseudoIndirectBranchR6 + 0U, // PseudoIndirectBranch_MM + 0U, // PseudoIndirectBranch_MMR6 + 0U, // PseudoIndirectHazardBranch + 0U, // PseudoIndirectHazardBranch64 + 0U, // PseudoIndrectHazardBranch64R6 + 0U, // PseudoIndrectHazardBranchR6 + 100680492U, // PseudoLA_NM + 100685980U, // PseudoLI_NM 0U, // PseudoMADD 0U, // PseudoMADDU + 0U, // PseudoMADDU_MM + 0U, // PseudoMADD_MM 0U, // PseudoMFHI 0U, // PseudoMFHI64 + 0U, // PseudoMFHI_MM 0U, // PseudoMFLO 0U, // PseudoMFLO64 + 0U, // PseudoMFLO_MM 0U, // PseudoMSUB 0U, // PseudoMSUBU + 0U, // PseudoMSUBU_MM + 0U, // PseudoMSUB_MM 0U, // PseudoMTLOHI 0U, // PseudoMTLOHI64 0U, // PseudoMTLOHI_DSP + 0U, // PseudoMTLOHI_MM 0U, // PseudoMULT + 0U, // PseudoMULT_MM 0U, // PseudoMULTu + 0U, // PseudoMULTu_MM 0U, // PseudoPICK_PH 0U, // PseudoPICK_QB 0U, // PseudoReturn 0U, // PseudoReturn64 + 0U, // PseudoReturnNM 0U, // PseudoSDIV 0U, // PseudoSELECTFP_F_D32 0U, // PseudoSELECTFP_F_D64 @@ -1401,413 +1960,2502 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) 0U, // PseudoSELECT_I 0U, // PseudoSELECT_I64 0U, // PseudoSELECT_S + 536895420U, // PseudoSUBU_NM + 536891541U, // PseudoTRUNC_W_D + 536891541U, // PseudoTRUNC_W_D32 + 536895079U, // PseudoTRUNC_W_S 0U, // PseudoUDIV - 18155U, // RADDU_W_QB - 33577003U, // RDDSP - 22791U, // RDHWR - 22791U, // RDHWR64 - 22791U, // RDHWR_MM - 21766U, // REPLV_PH - 18135U, // REPLV_QB - 33575925U, // REPL_PH - 33572353U, // REPL_QB - 19787U, // RINT_D - 23293U, // RINT_S - 134240513U, // ROTR - 134241514U, // ROTRV - 134241514U, // ROTRV_MM - 134240513U, // ROTR_MM - 18992U, // ROUND_L_D64 - 23020U, // ROUND_L_S - 20168U, // ROUND_W_D32 - 20168U, // ROUND_W_D64 - 20168U, // ROUND_W_MM - 23342U, // ROUND_W_S - 23342U, // ROUND_W_S_MM - 0U, // Restore16 - 0U, // RestoreX16 + 536893930U, // ROL + 536893930U, // ROLImm + 536894468U, // ROR + 536894468U, // RORImm 0U, // RetRA 0U, // RetRA16 - 134235208U, // SAT_S_B - 134237279U, // SAT_S_D - 2281722353U, // SAT_S_H - 134242618U, // SAT_S_W - 134235435U, // SAT_U_B - 134237758U, // SAT_U_D - 2281722643U, // SAT_U_H - 134243048U, // SAT_U_W - 58738423U, // SB - 58736980U, // SB16_MM - 58738423U, // SB64 - 58738423U, // SB_MM - 3966874U, // SC - 3968802U, // SCD - 3968802U, // SCD_R6 - 3966874U, // SC_MM - 3966874U, // SC_R6 - 58740570U, // SD - 546774U, // SDBBP - 65946U, // SDBBP16_MM - 546774U, // SDBBP_MM - 546774U, // SDBBP_R6 - 58736694U, // SDC1 - 58736694U, // SDC164 - 58736694U, // SDC1_MM - 58736894U, // SDC2 - 58736894U, // SDC2_R6 - 58736953U, // SDC3 - 25611U, // SDIV - 25611U, // SDIV_MM - 58742463U, // SDL - 58742959U, // SDR - 1358970999U, // SDXC1 - 1358970999U, // SDXC164 - 17810U, // SEB - 17810U, // SEB64 - 17810U, // SEB_MM - 21382U, // SEH - 21382U, // SEH64 - 21382U, // SEH_MM - 134243273U, // SELEQZ - 134243273U, // SELEQZ64 - 134237968U, // SELEQZ_D - 134241128U, // SELEQZ_S - 134243246U, // SELNEZ - 134243246U, // SELNEZ64 - 134237951U, // SELNEZ_D - 134241118U, // SELNEZ_S - 151013977U, // SEL_D - 151018005U, // SEL_S - 134240345U, // SEQ - 134239758U, // SEQi - 58742195U, // SH - 58736993U, // SH16_MM - 58742195U, // SH64 - 2281718455U, // SHF_B - 2281721863U, // SHF_H - 2281725417U, // SHF_W - 22463U, // SHILO - 23761U, // SHILOV - 134239484U, // SHLLV_PH - 134235853U, // SHLLV_QB - 134239421U, // SHLLV_S_PH - 134242679U, // SHLLV_S_W - 134239212U, // SHLL_PH - 134235640U, // SHLL_QB - 134239334U, // SHLL_S_PH - 134242519U, // SHLL_S_W - 134239474U, // SHRAV_PH - 134235843U, // SHRAV_QB - 134239322U, // SHRAV_R_PH - 134235741U, // SHRAV_R_QB - 134242274U, // SHRAV_R_W - 134239119U, // SHRA_PH - 134235563U, // SHRA_QB - 134239287U, // SHRA_R_PH - 134235706U, // SHRA_R_QB - 134242232U, // SHRA_R_W - 134239504U, // SHRLV_PH - 134235873U, // SHRLV_QB - 134239230U, // SHRL_PH - 134235658U, // SHRL_QB - 58742195U, // SH_MM - 2969584334U, // SLDI_B - 2969586088U, // SLDI_D - 2969587742U, // SLDI_H - 2969591377U, // SLDI_W - 822100628U, // SLD_B - 822102147U, // SLD_D - 822104036U, // SLD_H - 822107506U, // SLD_W - 134240058U, // SLL - 134234494U, // SLL16_MM - 1610635066U, // SLL64_32 - 1610635066U, // SLL64_64 - 2281718512U, // SLLI_B - 2281720249U, // SLLI_D - 2281721903U, // SLLI_H - 2281725538U, // SLLI_W - 134241476U, // SLLV - 134241476U, // SLLV_MM - 134235013U, // SLL_B - 134236785U, // SLL_D - 134238371U, // SLL_H - 134240058U, // SLL_MM - 134242032U, // SLL_W - 134241213U, // SLT - 134241213U, // SLT64 - 134241213U, // SLT_MM - 134239782U, // SLTi - 134239782U, // SLTi64 - 134239782U, // SLTi_MM - 134241321U, // SLTiu - 134241321U, // SLTiu64 - 134241321U, // SLTiu_MM - 134241357U, // SLTu - 134241357U, // SLTu64 - 134241357U, // SLTu_MM - 134238063U, // SNE - 134239703U, // SNEi + 50351496U, // SDC1_M1 + 0U, // SDIV_MM_Pseudo + 50358535U, // SDMacro + 536895725U, // SDivIMacro + 536895725U, // SDivMacro + 536897864U, // SEQIMacro + 536897864U, // SEQMacro + 536891767U, // SGE + 536891767U, // SGEImm + 536891767U, // SGEImm64 + 536895467U, // SGEU + 536895467U, // SGEUImm + 536895467U, // SGEUImm64 + 536895347U, // SGTImm + 536895347U, // SGTImm64 + 536895593U, // SGTUImm + 536895593U, // SGTUImm64 + 536891812U, // SLE + 536891812U, // SLEImm + 536891812U, // SLEImm64 + 536895485U, // SLEU + 536895485U, // SLEUImm + 536895485U, // SLEUImm64 + 536895363U, // SLTImm64 + 536895605U, // SLTUImm64 + 536897803U, // SNEIMacro + 536897803U, // SNEMacro 0U, // SNZ_B_PSEUDO 0U, // SNZ_D_PSEUDO 0U, // SNZ_H_PSEUDO 0U, // SNZ_V_PSEUDO 0U, // SNZ_W_PSEUDO - 2952807239U, // SPLATI_B - 2952808960U, // SPLATI_D - 2952810614U, // SPLATI_H - 2952814249U, // SPLATI_W - 805323906U, // SPLAT_B - 805326016U, // SPLAT_D - 805327414U, // SPLAT_H - 805331393U, // SPLAT_W - 134234685U, // SRA - 2281718470U, // SRAI_B - 2281720224U, // SRAI_D - 2281721878U, // SRAI_H - 2281725513U, // SRAI_W - 134234898U, // SRARI_B - 134236635U, // SRARI_D - 2281721937U, // SRARI_H - 134241924U, // SRARI_W - 134235051U, // SRAR_B - 134237015U, // SRAR_D - 134238486U, // SRAR_H - 134242296U, // SRAR_W - 134241455U, // SRAV - 134241455U, // SRAV_MM - 134234749U, // SRA_B - 134236208U, // SRA_D - 134238157U, // SRA_H - 134234685U, // SRA_MM - 134241584U, // SRA_W - 134240070U, // SRL - 134234501U, // SRL16_MM - 2281718520U, // SRLI_B - 2281720257U, // SRLI_D - 2281721911U, // SRLI_H - 2281725546U, // SRLI_W - 134234916U, // SRLRI_B - 134236653U, // SRLRI_D - 2281721955U, // SRLRI_H - 134241942U, // SRLRI_W - 134235067U, // SRLR_B - 134237031U, // SRLR_D - 134238502U, // SRLR_H - 134242312U, // SRLR_W - 134241483U, // SRLV - 134241483U, // SRLV_MM - 134235020U, // SRL_B - 134236810U, // SRL_D - 134238378U, // SRL_H - 134240070U, // SRL_MM - 134242057U, // SRL_W - 9463U, // SSNOP - 9463U, // SSNOP_MM - 58736647U, // STORE_ACC128 - 58736647U, // STORE_ACC64 - 58736647U, // STORE_ACC64DSP - 58742810U, // STORE_CCOND_DSP - 58737829U, // ST_B - 58740080U, // ST_D - 58741337U, // ST_H - 58745378U, // ST_W - 134235902U, // SUB - 134239183U, // SUBQH_PH - 134239298U, // SUBQH_R_PH - 134242242U, // SUBQH_R_W - 134241847U, // SUBQH_W - 134239258U, // SUBQ_PH - 134239355U, // SUBQ_S_PH - 134242548U, // SUBQ_S_W - 134235423U, // SUBSUS_U_B - 134237746U, // SUBSUS_U_D - 134238983U, // SUBSUS_U_H - 134243036U, // SUBSUS_U_W - 134235226U, // SUBSUU_S_B - 134237319U, // SUBSUU_S_D - 134238723U, // SUBSUU_S_H - 134242658U, // SUBSUU_S_W - 134235188U, // SUBS_S_B - 134237259U, // SUBS_S_D - 134238685U, // SUBS_S_H - 134242598U, // SUBS_S_W - 134235403U, // SUBS_U_B - 134237726U, // SUBS_U_D - 134238963U, // SUBS_U_H - 134243016U, // SUBS_U_W - 134234567U, // SUBU16_MM - 134235611U, // SUBUH_QB - 134235717U, // SUBUH_R_QB - 134239456U, // SUBU_PH - 134235825U, // SUBU_QB - 134239399U, // SUBU_S_PH - 134235764U, // SUBU_S_QB - 2281718618U, // SUBVI_B - 2281720339U, // SUBVI_D - 2281721993U, // SUBVI_H - 2281725628U, // SUBVI_W - 134235482U, // SUBV_B - 134237827U, // SUBV_D - 134239042U, // SUBV_H - 134243117U, // SUBV_W - 134235902U, // SUB_MM - 134241247U, // SUBu - 134241247U, // SUBu_MM - 1358971013U, // SUXC1 - 1358971013U, // SUXC164 - 1358971013U, // SUXC1_MM - 58745730U, // SW - 58737124U, // SW16_MM - 58745730U, // SW64 - 58736746U, // SWC1 - 58736746U, // SWC1_MM - 58736920U, // SWC2 - 58736920U, // SWC2_R6 - 58736965U, // SWC3 - 58742642U, // SWL - 58742642U, // SWL64 - 58742642U, // SWL_MM - 3522963U, // SWM16_MM - 3522792U, // SWM32_MM - 3528600U, // SWM_MM - 137295U, // SWP_MM - 58743059U, // SWR - 58743059U, // SWR64 - 58743059U, // SWR_MM - 58745730U, // SWSP_MM - 1358971027U, // SWXC1 - 1358971027U, // SWXC1_MM - 58745730U, // SW_MM - 549939U, // SYNC - 153021U, // SYNCI - 549939U, // SYNC_MM - 546590U, // SYSCALL - 546590U, // SYSCALL_MM + 536894049U, // SRemIMacro + 536894049U, // SRemMacro + 50348037U, // STORE_ACC128 + 50348037U, // STORE_ACC64 + 50348037U, // STORE_ACC64DSP + 50354950U, // STORE_CCOND_DSP + 0U, // STR_D + 0U, // STR_W + 0U, // ST_F16 + 72317U, // SWM_MM 0U, // SZ_B_PSEUDO 0U, // SZ_D_PSEUDO 0U, // SZ_H_PSEUDO 0U, // SZ_V_PSEUDO 0U, // SZ_W_PSEUDO - 0U, // Save16 - 0U, // SaveX16 - 58738423U, // SbRxRyOffMemX16 - 549866U, // SebRx16 - 549878U, // SehRx16 - 4367299U, // SelBeqZ - 4367272U, // SelBneZ - 1828886516U, // SelTBteqZCmp - 1828886024U, // SelTBteqZCmpi - 1828887485U, // SelTBteqZSlt - 1828886054U, // SelTBteqZSlti - 1828887593U, // SelTBteqZSltiu - 1828887629U, // SelTBteqZSltu - 1963104244U, // SelTBtneZCmp - 1963103752U, // SelTBtneZCmpi - 1963105213U, // SelTBtneZSlt - 1963103782U, // SelTBtneZSlti - 1963105321U, // SelTBtneZSltiu - 1963105357U, // SelTBtneZSltu - 58742195U, // ShRxRyOffMemX16 - 134240058U, // SllX16 - 16800964U, // SllvRxRy16 - 92576701U, // SltCCRxRy16 - 23485U, // SltRxRy16 - 92575270U, // SltiCCRxImmX16 - 939546150U, // SltiRxImm16 - 22054U, // SltiRxImmX16 - 92576809U, // SltiuCCRxImmX16 - 939547689U, // SltiuRxImm16 - 23593U, // SltiuRxImmX16 - 92576845U, // SltuCCRxRy16 - 23629U, // SltuRxRy16 - 92576845U, // SltuRxRyRz16 - 134234685U, // SraX16 - 16800943U, // SravRxRy16 - 134240070U, // SrlX16 - 16800971U, // SrlvRxRy16 - 134241247U, // SubuRxRyRz16 - 58745730U, // SwRxRyOffMemX16 - 1493197698U, // SwRxSpImmX16 + 50348827U, // SaaAddr + 50352386U, // SaadAddr + 2713697U, // SelBeqZ + 2713670U, // SelBneZ + 3338754784U, // SelTBteqZCmp + 3338754213U, // SelTBteqZCmpi + 3338755971U, // SelTBteqZSlt + 3338754243U, // SelTBteqZSlti + 3338756127U, // SelTBteqZSltiu + 3338756213U, // SelTBteqZSltu + 3875625696U, // SelTBtneZCmp + 3875625125U, // SelTBtneZCmpi + 3875626883U, // SelTBtneZSlt + 3875625155U, // SelTBtneZSlti + 3875627039U, // SelTBtneZSltiu + 3875627125U, // SelTBtneZSltu + 136372099U, // SltCCRxRy16 + 136370371U, // SltiCCRxImmX16 + 136372255U, // SltiuCCRxImmX16 + 136372341U, // SltuCCRxRy16 + 136372341U, // SltuRxRyRz16 0U, // TAILCALL - 0U, // TAILCALL64_R - 0U, // TAILCALL_R - 134240350U, // TEQ - 33576468U, // TEQI - 33576468U, // TEQI_MM - 134240350U, // TEQ_MM - 134238046U, // TGE - 33576401U, // TGEI - 33578018U, // TGEIU - 33578018U, // TGEIU_MM - 33576401U, // TGEI_MM - 134241288U, // TGEU - 134241288U, // TGEU_MM - 134238046U, // TGE_MM - 9458U, // TLBP - 9458U, // TLBP_MM - 9469U, // TLBR - 9469U, // TLBR_MM - 9448U, // TLBWI - 9448U, // TLBWI_MM - 9474U, // TLBWR - 9474U, // TLBWR_MM - 134241218U, // TLT - 33576492U, // TLTI - 33578032U, // TLTIU_MM - 33576492U, // TLTI_MM - 134241363U, // TLTU - 134241363U, // TLTU_MM - 134241218U, // TLT_MM - 134238068U, // TNE - 33576413U, // TNEI - 33576413U, // TNEI_MM - 134238068U, // TNE_MM + 0U, // TAILCALL64R6REG + 0U, // TAILCALLHB64R6REG + 0U, // TAILCALLHBR6REG + 0U, // TAILCALLR6REG + 0U, // TAILCALLREG + 0U, // TAILCALLREG64 + 0U, // TAILCALLREGHB + 0U, // TAILCALLREGHB64 + 0U, // TAILCALLREG_MM + 0U, // TAILCALLREG_MMR6 + 0U, // TAILCALLREG_NM + 0U, // TAILCALL_MM + 0U, // TAILCALL_MMR6 + 0U, // TAILCALL_NM 0U, // TRAP - 18981U, // TRUNC_L_D64 - 23009U, // TRUNC_L_S - 20157U, // TRUNC_W_D32 - 20157U, // TRUNC_W_D64 - 20157U, // TRUNC_W_MM - 23331U, // TRUNC_W_S - 23331U, // TRUNC_W_S_MM - 33578032U, // TTLTIU - 25597U, // UDIV - 25597U, // UDIV_MM - 134241335U, // V3MULU - 134234135U, // VMM0 - 134241350U, // VMULU - 151012022U, // VSHF_B - 151013760U, // VSHF_D - 151015430U, // VSHF_H - 151018984U, // VSHF_W - 9486U, // WAIT - 547767U, // WAIT_MM - 33577010U, // WRDSP - 21376U, // WSBH - 21376U, // WSBH_MM - 134240507U, // XOR - 836009U, // XOR16_MM - 134240507U, // XOR64 - 2281718581U, // XORI_B - 134240507U, // XOR_MM - 134241419U, // XOR_V + 0U, // TRAP_MM + 0U, // UDIV_MM_Pseudo + 536895633U, // UDivIMacro + 536895633U, // UDivMacro + 536895556U, // URemIMacro + 536895556U, // URemMacro + 50353696U, // Ulh + 50356227U, // Ulhu + 50358217U, // Ulw + 50354255U, // Ush + 50358239U, // Usw 0U, // XOR_V_D_PSEUDO 0U, // XOR_V_H_PSEUDO 0U, // XOR_V_W_PSEUDO - 134239770U, // XORi - 134239770U, // XORi64 - 134239770U, // XORi_MM - 16799995U, // XorRxRxRy16 - 0U + 22322U, // ABSQ_S_PH + 22322U, // ABSQ_S_PH_MM + 18359U, // ABSQ_S_QB + 18359U, // ABSQ_S_QB_MMR2 + 25926U, // ABSQ_S_W + 25926U, // ABSQ_S_W_MM + 536891671U, // ADD + 536888015U, // ADDIU48_NM + 536888026U, // ADDIUGP48_NM + 536888039U, // ADDIUGPB_NM + 536888078U, // ADDIUGPW_NM + 536888052U, // ADDIUNEG_NM + 18678U, // ADDIUPC + 18678U, // ADDIUPC_MM + 18678U, // ADDIUPC_MMR6 + 23275U, // ADDIUR1SP_MM + 536888064U, // ADDIUR1SP_NM + 536887680U, // ADDIUR2_MM + 536887964U, // ADDIUR2_NM + 536887975U, // ADDIURS5_NM + 18923937U, // ADDIUS5_MM + 547624U, // ADDIUSP_MM + 536895505U, // ADDIU_MMR6 + 536887953U, // ADDIU_NM + 536893039U, // ADDQH_PH + 536893039U, // ADDQH_PH_MMR2 + 536893156U, // ADDQH_R_PH + 536893156U, // ADDQH_R_PH_MMR2 + 536896513U, // ADDQH_R_W + 536896513U, // ADDQH_R_W_MMR2 + 536896116U, // ADDQH_W + 536896116U, // ADDQH_W_MMR2 + 536893113U, // ADDQ_PH + 536893113U, // ADDQ_PH_MM + 536893212U, // ADDQ_S_PH + 536893212U, // ADDQ_S_PH_MM + 536896818U, // ADDQ_S_W + 536896818U, // ADDQ_S_W_MM + 536895247U, // ADDR_PS64 + 536889644U, // ADDSC + 536889644U, // ADDSC_MM + 536888213U, // ADDS_A_B + 536889837U, // ADDS_A_D + 536891952U, // ADDS_A_H + 536895824U, // ADDS_A_W + 536888689U, // ADDS_S_B + 536890935U, // ADDS_S_D + 536892517U, // ADDS_S_H + 536896868U, // ADDS_S_W + 536888904U, // ADDS_U_B + 536891402U, // ADDS_U_D + 536892795U, // ADDS_U_H + 536897286U, // ADDS_U_W + 536887900U, // ADDU16_MM + 536887900U, // ADDU16_MMR6 + 536889139U, // ADDUH_QB + 536889139U, // ADDUH_QB_MMR2 + 536889247U, // ADDUH_R_QB + 536889247U, // ADDUH_R_QB_MMR2 + 536895434U, // ADDU_MMR6 + 536893311U, // ADDU_PH + 536893311U, // ADDU_PH_MMR2 + 536889352U, // ADDU_QB + 536889352U, // ADDU_QB_MM + 536893256U, // ADDU_S_PH + 536893256U, // ADDU_S_PH_MMR2 + 536889293U, // ADDU_S_QB + 536889293U, // ADDU_S_QB_MM + 536888470U, // ADDVI_B + 536890357U, // ADDVI_D + 536892176U, // ADDVI_H + 536896249U, // ADDVI_W + 536888982U, // ADDV_B + 536891492U, // ADDV_D + 536892873U, // ADDV_H + 536897386U, // ADDV_W + 536889713U, // ADDWC + 536889713U, // ADDWC_MM + 536888195U, // ADD_A_B + 536889818U, // ADD_A_D + 536891934U, // ADD_A_H + 536895805U, // ADD_A_W + 536891671U, // ADD_MM + 536891671U, // ADD_MMR6 + 536891671U, // ADD_NM + 536893538U, // ADDi + 536893538U, // ADDi_MM + 536895505U, // ADDiu + 536895505U, // ADDiu_MM + 536895434U, // ADDu + 536895434U, // ADDu16_NM + 536895434U, // ADDu4x4_NM + 536895434U, // ADDu_MM + 536895434U, // ADDu_NM + 536894083U, // ALIGN + 536894083U, // ALIGN_MMR6 + 18670U, // ALUIPC + 18670U, // ALUIPC_MMR6 + 151013614U, // ALUIPC_NM + 536891700U, // AND + 20021711U, // AND16_MM + 20021711U, // AND16_MMR6 + 536891700U, // AND16_NM + 536891700U, // AND64 + 536887780U, // ANDI16_MM + 536887780U, // ANDI16_MMR6 + 536887997U, // ANDI16_NM + 536888329U, // ANDI_B + 536893544U, // ANDI_MMR6 + 536887943U, // ANDI_NM + 536891700U, // AND_MM + 536891700U, // AND_MMR6 + 536891700U, // AND_NM + 536895644U, // AND_V + 536893544U, // ANDi + 536893544U, // ANDi64 + 536893544U, // ANDi_MM + 536891714U, // APPEND + 536891714U, // APPEND_MMR2 + 536888583U, // ASUB_S_B + 536890765U, // ASUB_S_D + 536892349U, // ASUB_S_H + 536896648U, // ASUB_S_W + 536888798U, // ASUB_U_B + 536891232U, // ASUB_U_D + 536892637U, // ASUB_U_H + 536897116U, // ASUB_U_W + 536893648U, // AUI + 18663U, // AUIPC + 18663U, // AUIPC_MMR6 + 536893648U, // AUI_MMR6 + 536888669U, // AVER_S_B + 536890915U, // AVER_S_D + 536892487U, // AVER_S_H + 536896848U, // AVER_S_W + 536888884U, // AVER_U_B + 536891382U, // AVER_U_D + 536892775U, // AVER_U_H + 536897266U, // AVER_U_W + 536888611U, // AVE_S_B + 536890847U, // AVE_S_D + 536892419U, // AVE_S_H + 536896730U, // AVE_S_W + 536888826U, // AVE_U_B + 536891314U, // AVE_U_D + 536892707U, // AVE_U_H + 536897198U, // AVE_U_W + 24593U, // AddiuRxImmX16 + 3694609U, // AddiuRxPcImmX16 + 33579025U, // AddiuRxRxImm16 + 33579025U, // AddiuRxRxImmX16 + 167796753U, // AddiuRxRyOffMemX16 + 4221103U, // AddiuSpImm16 + 551087U, // AddiuSpImmX16 + 536895434U, // AdduRxRyRz16 + 33575220U, // AndRxRxRy16 + 557483U, // B16_MM + 536895433U, // BADDu + 563459U, // BAL + 559256U, // BALC + 115379U, // BALC16_NM + 559256U, // BALC_MMR6 + 116888U, // BALC_NM + 536894082U, // BALIGN + 536894082U, // BALIGN_MMR2 + 18745U, // BALRSC_NM + 536889778U, // BBEQZC_NM + 184565845U, // BBIT0 + 184565977U, // BBIT032 + 184565970U, // BBIT1 + 184565986U, // BBIT132 + 536889752U, // BBNEZC_NM + 559202U, // BC + 557488U, // BC16_MMR6 + 559202U, // BC16_NM + 201353603U, // BC1EQZ + 201345440U, // BC1EQZC_MMR6 + 201347591U, // BC1F + 201349504U, // BC1FL + 201347591U, // BC1F_MM + 201353587U, // BC1NEZ + 201345414U, // BC1NEZC_MMR6 + 201351016U, // BC1T + 201349637U, // BC1TL + 201351016U, // BC1T_MM + 201353611U, // BC2EQZ + 201345449U, // BC2EQZC_MMR6 + 201353595U, // BC2NEZ + 201345423U, // BC2NEZC_MMR6 + 536888398U, // BCLRI_B + 536890301U, // BCLRI_D + 536892120U, // BCLRI_H + 536896193U, // BCLRI_W + 536888550U, // BCLR_B + 536890689U, // BCLR_D + 536892316U, // BCLR_H + 536896564U, // BCLR_W + 559202U, // BC_MMR6 + 559202U, // BC_NM + 536894300U, // BEQ + 536894300U, // BEQ64 + 536889618U, // BEQC + 536889618U, // BEQC16_NM + 536889618U, // BEQC64 + 536889618U, // BEQC_MMR6 + 536889618U, // BEQC_NM + 536889618U, // BEQCzero_NM + 754993285U, // BEQIC_NM + 536893945U, // BEQL + 201343615U, // BEQZ16_MM + 201345216U, // BEQZALC + 201345216U, // BEQZALC_MMR6 + 201345459U, // BEQZC + 201343430U, // BEQZC16_MMR6 + 201345459U, // BEQZC16_NM + 201345459U, // BEQZC64 + 201345459U, // BEQZC_MM + 201345459U, // BEQZC_MMR6 + 201345459U, // BEQZC_NM + 536894300U, // BEQ_MM + 536889446U, // BGEC + 536889446U, // BGEC64 + 536889446U, // BGEC_MMR6 + 536889446U, // BGEC_NM + 754993266U, // BGEIC_NM + 754993486U, // BGEIUC_NM + 536889671U, // BGEUC + 536889671U, // BGEUC64 + 536889671U, // BGEUC_MMR6 + 536889671U, // BGEUC_NM + 201353274U, // BGEZ + 201353274U, // BGEZ64 + 201349389U, // BGEZAL + 201345189U, // BGEZALC + 201345189U, // BGEZALC_MMR6 + 201349585U, // BGEZALL + 201350857U, // BGEZALS_MM + 201349389U, // BGEZAL_MM + 201345400U, // BGEZC + 201345400U, // BGEZC64 + 201345400U, // BGEZC_MMR6 + 201349700U, // BGEZL + 201353274U, // BGEZ_MM + 201353334U, // BGTZ + 201353334U, // BGTZ64 + 201345225U, // BGTZALC + 201345225U, // BGTZALC_MMR6 + 201345466U, // BGTZC + 201345466U, // BGTZC64 + 201345466U, // BGTZC_MMR6 + 201349714U, // BGTZL + 201353334U, // BGTZ_MM + 570442803U, // BINSLI_B + 570444706U, // BINSLI_D + 570446525U, // BINSLI_H + 570450598U, // BINSLI_W + 570442950U, // BINSL_B + 570444906U, // BINSL_D + 570446639U, // BINSL_H + 570450756U, // BINSL_W + 570442864U, // BINSRI_B + 570444751U, // BINSRI_D + 570446570U, // BINSRI_H + 570450643U, // BINSRI_W + 570442998U, // BINSR_B + 570445171U, // BINSR_D + 570446764U, // BINSR_H + 570451046U, // BINSR_W + 24804U, // BITREV + 26612U, // BITREVW_NM + 24804U, // BITREV_MM + 23225U, // BITSWAP + 23225U, // BITSWAP_MMR6 + 201353280U, // BLEZ + 201353280U, // BLEZ64 + 201345198U, // BLEZALC + 201345198U, // BLEZALC_MMR6 + 201345407U, // BLEZC + 201345407U, // BLEZC64 + 201345407U, // BLEZC_MMR6 + 201349707U, // BLEZL + 201353280U, // BLEZ_MM + 536889665U, // BLTC + 536889665U, // BLTC64 + 536889665U, // BLTC_MMR6 + 536889665U, // BLTC_NM + 754993292U, // BLTIC_NM + 754993494U, // BLTIUC_NM + 536889694U, // BLTUC + 536889694U, // BLTUC64 + 536889694U, // BLTUC_MMR6 + 536889694U, // BLTUC_NM + 201353340U, // BLTZ + 201353340U, // BLTZ64 + 201349397U, // BLTZAL + 201345234U, // BLTZALC + 201345234U, // BLTZALC_MMR6 + 201349594U, // BLTZALL + 201350866U, // BLTZALS_MM + 201349397U, // BLTZAL_MM + 201345473U, // BLTZC + 201345473U, // BLTZC64 + 201345473U, // BLTZC_MMR6 + 201349721U, // BLTZL + 201353340U, // BLTZ_MM + 570442919U, // BMNZI_B + 570450133U, // BMNZ_V + 570442911U, // BMZI_B + 570450119U, // BMZ_V + 536891829U, // BNE + 536891829U, // BNE64 + 536889452U, // BNEC + 536889452U, // BNEC16_NM + 536889452U, // BNEC64 + 536889452U, // BNEC_MMR6 + 536889452U, // BNEC_NM + 536889452U, // BNECzero_NM + 536888337U, // BNEGI_B + 536890249U, // BNEGI_D + 536892068U, // BNEGI_H + 536896141U, // BNEGI_W + 536888305U, // BNEG_B + 536890225U, // BNEG_D + 536892044U, // BNEG_H + 536896036U, // BNEG_W + 754993273U, // BNEIC_NM + 536893818U, // BNEL + 201343607U, // BNEZ16_MM + 201345207U, // BNEZALC + 201345207U, // BNEZALC_MMR6 + 201345433U, // BNEZC + 201343421U, // BNEZC16_MMR6 + 201345433U, // BNEZC16_NM + 201345433U, // BNEZC64 + 201345433U, // BNEZC_MM + 201345433U, // BNEZC_MMR6 + 201345433U, // BNEZC_NM + 536891829U, // BNE_MM + 536889701U, // BNVC + 536889701U, // BNVC_MMR6 + 201344702U, // BNZ_B + 201347297U, // BNZ_D + 201348593U, // BNZ_H + 201351374U, // BNZ_V + 201353131U, // BNZ_W + 536889707U, // BOVC + 536889707U, // BOVC_MMR6 + 557299U, // BPOSGE32 + 559191U, // BPOSGE32C_MMR3 + 557299U, // BPOSGE32_MM + 235018468U, // BREAK + 147962U, // BREAK16_MM + 147962U, // BREAK16_MMR6 + 547044U, // BREAK16_NM + 235018468U, // BREAK_MM + 235018468U, // BREAK_MMR6 + 547044U, // BREAK_NM + 543027U, // BRSC_NM + 570442778U, // BSELI_B + 570450091U, // BSEL_V + 536888452U, // BSETI_B + 536890339U, // BSETI_D + 536892158U, // BSETI_H + 536896231U, // BSETI_W + 536888766U, // BSET_B + 536891051U, // BSET_D + 536892605U, // BSET_H + 536897022U, // BSET_W + 26602U, // BYTEREVW_NM + 201344696U, // BZ_B + 201347281U, // BZ_D + 201348587U, // BZ_H + 201351361U, // BZ_V + 201353125U, // BZ_W + 738224225U, // BeqzRxImm16 + 201353313U, // BeqzRxImmX16 + 4227977U, // Bimm16 + 557961U, // BimmX16 + 738224198U, // BnezRxImm16 + 201353286U, // BnezRxImmX16 + 10794U, // Break16 + 4745327U, // Bteqz16 + 551023U, // BteqzX16 + 4745300U, // Btnez16 + 550996U, // BtnezX16 + 5411201U, // CACHE + 5411171U, // CACHEE + 5411171U, // CACHEE_MM + 5411201U, // CACHE_MM + 5411201U, // CACHE_MMR6 + 50516353U, // CACHE_NM + 5411201U, // CACHE_R6 + 19476U, // CEIL_L_D64 + 19476U, // CEIL_L_D_MMR6 + 23847U, // CEIL_L_S + 23847U, // CEIL_L_S_MMR6 + 20651U, // CEIL_W_D32 + 20651U, // CEIL_W_D64 + 20651U, // CEIL_W_D_MMR6 + 20651U, // CEIL_W_MM + 24189U, // CEIL_W_S + 24189U, // CEIL_W_S_MM + 24189U, // CEIL_W_S_MMR6 + 536888381U, // CEQI_B + 536890284U, // CEQI_D + 536892103U, // CEQI_H + 536896176U, // CEQI_W + 536888535U, // CEQ_B + 536890596U, // CEQ_D + 536892294U, // CEQ_H + 536896452U, // CEQ_W + 16488U, // CFC1 + 16488U, // CFC1_MM + 16704U, // CFC2_MM + 17267U, // CFCMSA + 536895195U, // CINS + 536887588U, // CINS32 + 536895195U, // CINS64_32 + 536895195U, // CINS_i32 + 20121U, // CLASS_D + 20121U, // CLASS_D_MMR6 + 24040U, // CLASS_S + 24040U, // CLASS_S_MMR6 + 536888620U, // CLEI_S_B + 536890856U, // CLEI_S_D + 536892428U, // CLEI_S_H + 536896739U, // CLEI_S_W + 536888835U, // CLEI_U_B + 536891323U, // CLEI_U_D + 536892716U, // CLEI_U_H + 536897207U, // CLEI_U_W + 536888602U, // CLE_S_B + 536890838U, // CLE_S_D + 536892410U, // CLE_S_H + 536896721U, // CLE_S_W + 536888817U, // CLE_U_B + 536891305U, // CLE_U_D + 536892698U, // CLE_U_H + 536897189U, // CLE_U_W + 23193U, // CLO + 23193U, // CLO_MM + 23193U, // CLO_MMR6 + 23193U, // CLO_NM + 23193U, // CLO_R6 + 536888640U, // CLTI_S_B + 536890876U, // CLTI_S_D + 536892448U, // CLTI_S_H + 536896759U, // CLTI_S_W + 536888855U, // CLTI_U_B + 536891343U, // CLTI_U_D + 536892736U, // CLTI_U_H + 536897227U, // CLTI_U_W + 536888708U, // CLT_S_B + 536890954U, // CLT_S_D + 536892536U, // CLT_S_H + 536896887U, // CLT_S_W + 536888935U, // CLT_U_B + 536891433U, // CLT_U_D + 536892826U, // CLT_U_H + 536897317U, // CLT_U_W + 26716U, // CLZ + 26716U, // CLZ_MM + 26716U, // CLZ_MMR6 + 26716U, // CLZ_NM + 26716U, // CLZ_R6 + 536889185U, // CMPGDU_EQ_QB + 536889185U, // CMPGDU_EQ_QB_MMR2 + 536889090U, // CMPGDU_LE_QB + 536889090U, // CMPGDU_LE_QB_MMR2 + 536889304U, // CMPGDU_LT_QB + 536889304U, // CMPGDU_LT_QB_MMR2 + 536889199U, // CMPGU_EQ_QB + 536889199U, // CMPGU_EQ_QB_MM + 536889104U, // CMPGU_LE_QB + 536889104U, // CMPGU_LE_QB_MM + 536889318U, // CMPGU_LT_QB + 536889318U, // CMPGU_LT_QB_MM + 18300U, // CMPU_EQ_QB + 18300U, // CMPU_EQ_QB_MM + 18205U, // CMPU_LE_QB + 18205U, // CMPU_LE_QB_MM + 18419U, // CMPU_LT_QB + 18419U, // CMPU_LT_QB_MM + 536890146U, // CMP_AF_D_MMR6 + 536894669U, // CMP_AF_S_MMR6 + 536890585U, // CMP_EQ_D + 536890585U, // CMP_EQ_D_MMR6 + 22210U, // CMP_EQ_PH + 22210U, // CMP_EQ_PH_MM + 536894873U, // CMP_EQ_S + 536894873U, // CMP_EQ_S_MMR6 + 536890146U, // CMP_F_D + 536894669U, // CMP_F_S + 536889990U, // CMP_LE_D + 536889990U, // CMP_LE_D_MMR6 + 22106U, // CMP_LE_PH + 22106U, // CMP_LE_PH_MM + 536894590U, // CMP_LE_S + 536894590U, // CMP_LE_S_MMR6 + 536891076U, // CMP_LT_D + 536891076U, // CMP_LT_D_MMR6 + 22379U, // CMP_LT_PH + 22379U, // CMP_LT_PH_MM + 536894978U, // CMP_LT_S + 536894978U, // CMP_LT_S_MMR6 + 536890164U, // CMP_SAF_D + 536890164U, // CMP_SAF_D_MMR6 + 536894679U, // CMP_SAF_S + 536894679U, // CMP_SAF_S_MMR6 + 536890612U, // CMP_SEQ_D + 536890612U, // CMP_SEQ_D_MMR6 + 536894892U, // CMP_SEQ_S + 536894892U, // CMP_SEQ_S_MMR6 + 536890027U, // CMP_SLE_D + 536890027U, // CMP_SLE_D_MMR6 + 536894619U, // CMP_SLE_S + 536894619U, // CMP_SLE_S_MMR6 + 536891103U, // CMP_SLT_D + 536891103U, // CMP_SLT_D_MMR6 + 536894997U, // CMP_SLT_S + 536894997U, // CMP_SLT_S_MMR6 + 536890660U, // CMP_SUEQ_D + 536890660U, // CMP_SUEQ_D_MMR6 + 536894923U, // CMP_SUEQ_S + 536894923U, // CMP_SUEQ_S_MMR6 + 536890075U, // CMP_SULE_D + 536890075U, // CMP_SULE_D_MMR6 + 536894650U, // CMP_SULE_S + 536894650U, // CMP_SULE_S_MMR6 + 536891151U, // CMP_SULT_D + 536891151U, // CMP_SULT_D_MMR6 + 536895028U, // CMP_SULT_S + 536895028U, // CMP_SULT_S_MMR6 + 536890533U, // CMP_SUN_D + 536890533U, // CMP_SUN_D_MMR6 + 536894837U, // CMP_SUN_S + 536894837U, // CMP_SUN_S_MMR6 + 536890640U, // CMP_UEQ_D + 536890640U, // CMP_UEQ_D_MMR6 + 536894912U, // CMP_UEQ_S + 536894912U, // CMP_UEQ_S_MMR6 + 536890055U, // CMP_ULE_D + 536890055U, // CMP_ULE_D_MMR6 + 536894639U, // CMP_ULE_S + 536894639U, // CMP_ULE_S_MMR6 + 536891131U, // CMP_ULT_D + 536891131U, // CMP_ULT_D_MMR6 + 536895017U, // CMP_ULT_S + 536895017U, // CMP_ULT_S_MMR6 + 536890515U, // CMP_UN_D + 536890515U, // CMP_UN_D_MMR6 + 536894827U, // CMP_UN_S + 536894827U, // CMP_UN_S_MMR6 + 1073759659U, // COPY_S_B + 1073761927U, // COPY_S_D + 1073763498U, // COPY_S_H + 1073767871U, // COPY_S_W + 1073759874U, // COPY_U_B + 1073763765U, // COPY_U_H + 1073768278U, // COPY_U_W + 536889029U, // CRC32B + 33572549U, // CRC32B_NM + 536889037U, // CRC32CB + 33572557U, // CRC32CB_NM + 536891656U, // CRC32CD + 536892940U, // CRC32CH + 33576460U, // CRC32CH_NM + 536897466U, // CRC32CW + 33580986U, // CRC32CW_NM + 536891642U, // CRC32D + 536892920U, // CRC32H + 33576440U, // CRC32H_NM + 536897458U, // CRC32W + 33580978U, // CRC32W_NM + 17875075U, // CTC1 + 17875075U, // CTC1_MM + 17875291U, // CTC2_MM + 17275U, // CTCMSA + 23643U, // CVT_D32_S + 23643U, // CVT_D32_S_MM + 24972U, // CVT_D32_W + 24972U, // CVT_D32_W_MM + 22769U, // CVT_D64_L + 23643U, // CVT_D64_S + 23643U, // CVT_D64_S_MM + 24972U, // CVT_D64_W + 24972U, // CVT_D64_W_MM + 22769U, // CVT_D_L_MMR6 + 19497U, // CVT_L_D64 + 19497U, // CVT_L_D64_MM + 19497U, // CVT_L_D_MMR6 + 23868U, // CVT_L_S + 23868U, // CVT_L_S_MM + 23868U, // CVT_L_S_MMR6 + 26574U, // CVT_PS_PW64 + 536894942U, // CVT_PS_S64 + 24369U, // CVT_PW_PS64 + 19844U, // CVT_S_D32 + 19844U, // CVT_S_D32_MM + 19844U, // CVT_S_D64 + 19844U, // CVT_S_D64_MM + 22778U, // CVT_S_L + 22778U, // CVT_S_L_MMR6 + 23023U, // CVT_S_PL64 + 24658U, // CVT_S_PU64 + 25727U, // CVT_S_W + 25727U, // CVT_S_W_MM + 25727U, // CVT_S_W_MMR6 + 20672U, // CVT_W_D32 + 20672U, // CVT_W_D32_MM + 20672U, // CVT_W_D64 + 20672U, // CVT_W_D64_MM + 24210U, // CVT_W_S + 24210U, // CVT_W_S_MM + 24210U, // CVT_W_S_MMR6 + 536890577U, // C_EQ_D32 + 536890577U, // C_EQ_D32_MM + 536890577U, // C_EQ_D64 + 536890577U, // C_EQ_D64_MM + 536894865U, // C_EQ_S + 536894865U, // C_EQ_S_MM + 536890139U, // C_F_D32 + 536890139U, // C_F_D32_MM + 536890139U, // C_F_D64 + 536890139U, // C_F_D64_MM + 536894662U, // C_F_S + 536894662U, // C_F_S_MM + 536889982U, // C_LE_D32 + 536889982U, // C_LE_D32_MM + 536889982U, // C_LE_D64 + 536889982U, // C_LE_D64_MM + 536894582U, // C_LE_S + 536894582U, // C_LE_S_MM + 536891068U, // C_LT_D32 + 536891068U, // C_LT_D32_MM + 536891068U, // C_LT_D64 + 536891068U, // C_LT_D64_MM + 536894970U, // C_LT_S + 536894970U, // C_LT_S_MM + 536889973U, // C_NGE_D32 + 536889973U, // C_NGE_D32_MM + 536889973U, // C_NGE_D64 + 536889973U, // C_NGE_D64_MM + 536894573U, // C_NGE_S + 536894573U, // C_NGE_S_MM + 536890008U, // C_NGLE_D32 + 536890008U, // C_NGLE_D32_MM + 536890008U, // C_NGLE_D64 + 536890008U, // C_NGLE_D64_MM + 536894600U, // C_NGLE_S + 536894600U, // C_NGLE_S_MM + 536890425U, // C_NGL_D32 + 536890425U, // C_NGL_D32_MM + 536890425U, // C_NGL_D64 + 536890425U, // C_NGL_D64_MM + 536894796U, // C_NGL_S + 536894796U, // C_NGL_S_MM + 536891059U, // C_NGT_D32 + 536891059U, // C_NGT_D32_MM + 536891059U, // C_NGT_D64 + 536891059U, // C_NGT_D64_MM + 536894961U, // C_NGT_S + 536894961U, // C_NGT_S_MM + 536890018U, // C_OLE_D32 + 536890018U, // C_OLE_D32_MM + 536890018U, // C_OLE_D64 + 536890018U, // C_OLE_D64_MM + 536894610U, // C_OLE_S + 536894610U, // C_OLE_S_MM + 536891094U, // C_OLT_D32 + 536891094U, // C_OLT_D32_MM + 536891094U, // C_OLT_D64 + 536891094U, // C_OLT_D64_MM + 536894988U, // C_OLT_S + 536894988U, // C_OLT_S_MM + 536890603U, // C_SEQ_D32 + 536890603U, // C_SEQ_D32_MM + 536890603U, // C_SEQ_D64 + 536890603U, // C_SEQ_D64_MM + 536894883U, // C_SEQ_S + 536894883U, // C_SEQ_S_MM + 536890209U, // C_SF_D32 + 536890209U, // C_SF_D32_MM + 536890209U, // C_SF_D64 + 536890209U, // C_SF_D64_MM + 536894708U, // C_SF_S + 536894708U, // C_SF_S_MM + 536890631U, // C_UEQ_D32 + 536890631U, // C_UEQ_D32_MM + 536890631U, // C_UEQ_D64 + 536890631U, // C_UEQ_D64_MM + 536894903U, // C_UEQ_S + 536894903U, // C_UEQ_S_MM + 536890046U, // C_ULE_D32 + 536890046U, // C_ULE_D32_MM + 536890046U, // C_ULE_D64 + 536890046U, // C_ULE_D64_MM + 536894630U, // C_ULE_S + 536894630U, // C_ULE_S_MM + 536891122U, // C_ULT_D32 + 536891122U, // C_ULT_D32_MM + 536891122U, // C_ULT_D64 + 536891122U, // C_ULT_D64_MM + 536895008U, // C_ULT_S + 536895008U, // C_ULT_S_MM + 536890507U, // C_UN_D32 + 536890507U, // C_UN_D32_MM + 536890507U, // C_UN_D64 + 536890507U, // C_UN_D64_MM + 536894819U, // C_UN_S + 536894819U, // C_UN_S_MM + 23264U, // CmpRxRy16 + 1610635429U, // CmpiRxImm16 + 22693U, // CmpiRxImmX16 + 536891670U, // DADD + 536893537U, // DADDi + 536895504U, // DADDiu + 536895440U, // DADDu + 536893568U, // DAHI + 536894090U, // DALIGN + 536893629U, // DATI + 536893647U, // DAUI + 23224U, // DBITSWAP + 23192U, // DCLO + 23192U, // DCLO_R6 + 26715U, // DCLZ + 26715U, // DCLZ_R6 + 536895724U, // DDIV + 536895632U, // DDIVU + 11034U, // DERET + 11034U, // DERET_MM + 11034U, // DERET_MMR6 + 11034U, // DERET_NM + 536895408U, // DEXT + 536897885U, // DEXT64_32 + 536894061U, // DEXTM + 536895625U, // DEXTU + 546916U, // DI + 536895201U, // DINS + 536894054U, // DINSM + 536895580U, // DINSU + 536895725U, // DIV + 536895633U, // DIVU + 536895633U, // DIVU_MMR6 + 536895633U, // DIVU_NM + 536895725U, // DIV_MMR6 + 536895725U, // DIV_NM + 536888729U, // DIV_S_B + 536890997U, // DIV_S_D + 536892557U, // DIV_S_H + 536896930U, // DIV_S_W + 536888944U, // DIV_U_B + 536891464U, // DIV_U_D + 536892835U, // DIV_U_H + 536897348U, // DIV_U_W + 546916U, // DI_MM + 546916U, // DI_MMR6 + 546916U, // DI_NM + 536888173U, // DLSA + 536888173U, // DLSA_R6 + 536887303U, // DMFC0 + 16494U, // DMFC1 + 536887622U, // DMFC2 + 251674950U, // DMFC2_OCTEON + 536887310U, // DMFGC0 + 536891722U, // DMOD + 536895454U, // DMODU + 548756U, // DMT + 2752561212U, // DMTC0 + 17875081U, // DMTC1 + 2752561505U, // DMTC2 + 251674977U, // DMTC2_OCTEON + 2752561190U, // DMTGC0 + 548756U, // DMT_NM + 536893524U, // DMUH + 536895497U, // DMUHU + 536893990U, // DMUL + 24461U, // DMULT + 24705U, // DMULTu + 536895541U, // DMULU + 536893990U, // DMUL_R6 + 536890905U, // DOTP_S_D + 536892477U, // DOTP_S_H + 536896798U, // DOTP_S_W + 536891372U, // DOTP_U_D + 536892765U, // DOTP_U_H + 536897256U, // DOTP_U_W + 570445250U, // DPADD_S_D + 570446822U, // DPADD_S_H + 570451133U, // DPADD_S_W + 570445717U, // DPADD_U_D + 570447110U, // DPADD_U_H + 570451601U, // DPADD_U_W + 536893370U, // DPAQX_SA_W_PH + 536893370U, // DPAQX_SA_W_PH_MMR2 + 536893453U, // DPAQX_S_W_PH + 536893453U, // DPAQX_S_W_PH_MMR2 + 536896258U, // DPAQ_SA_L_W + 536896258U, // DPAQ_SA_L_W_MM + 536893412U, // DPAQ_S_W_PH + 536893412U, // DPAQ_S_W_PH_MM + 536893725U, // DPAU_H_QBL + 536893725U, // DPAU_H_QBL_MM + 536894315U, // DPAU_H_QBR + 536894315U, // DPAU_H_QBR_MM + 536893491U, // DPAX_W_PH + 536893491U, // DPAX_W_PH_MMR2 + 536893360U, // DPA_W_PH + 536893360U, // DPA_W_PH_MMR2 + 23269U, // DPOP + 536893385U, // DPSQX_SA_W_PH + 536893385U, // DPSQX_SA_W_PH_MMR2 + 536893467U, // DPSQX_S_W_PH + 536893467U, // DPSQX_S_W_PH_MMR2 + 536896271U, // DPSQ_SA_L_W + 536896271U, // DPSQ_SA_L_W_MM + 536893440U, // DPSQ_S_W_PH + 536893440U, // DPSQ_S_W_PH_MM + 570445217U, // DPSUB_S_D + 570446801U, // DPSUB_S_H + 570451100U, // DPSUB_S_W + 570445684U, // DPSUB_U_D + 570447089U, // DPSUB_U_H + 570451568U, // DPSUB_U_W + 536893737U, // DPSU_H_QBL + 536893737U, // DPSU_H_QBL_MM + 536894327U, // DPSU_H_QBR + 536894327U, // DPSU_H_QBR_MM + 536893502U, // DPSX_W_PH + 536893502U, // DPSX_W_PH_MMR2 + 536893481U, // DPS_W_PH + 536893481U, // DPS_W_PH_MMR2 + 536894500U, // DROTR + 536887579U, // DROTR32 + 536895773U, // DROTRV + 22016U, // DSBH + 26786U, // DSDIV + 20770U, // DSHD + 536893923U, // DSLL + 536887549U, // DSLL32 + 2147506659U, // DSLL64_32 + 536895730U, // DSLLV + 536888167U, // DSRA + 536887531U, // DSRA32 + 536895709U, // DSRAV + 536893951U, // DSRL + 536887557U, // DSRL32 + 536895737U, // DSRLV + 536889419U, // DSUB + 536895419U, // DSUBu + 26772U, // DUDIV + 547656U, // DVP + 545220U, // DVPE + 545220U, // DVPE_NM + 547656U, // DVP_MMR6 + 26787U, // DivRxRy16 + 26773U, // DivuRxRy16 + 10928U, // EHB + 10928U, // EHB_MM + 10928U, // EHB_MMR6 + 10928U, // EHB_NM + 546928U, // EI + 546928U, // EI_MM + 546928U, // EI_MMR6 + 546928U, // EI_NM + 548761U, // EMT + 548761U, // EMT_NM + 11035U, // ERET + 10932U, // ERETNC + 10932U, // ERETNC_MMR6 + 10932U, // ERETNC_NM + 11035U, // ERET_MM + 11035U, // ERET_MMR6 + 11035U, // ERET_NM + 547661U, // EVP + 545226U, // EVPE + 545226U, // EVPE_NM + 547661U, // EVP_MMR6 + 536895409U, // EXT + 536894274U, // EXTP + 536894153U, // EXTPDP + 536895757U, // EXTPDPV + 536895757U, // EXTPDPV_MM + 536894153U, // EXTPDP_MM + 536895766U, // EXTPV + 536895766U, // EXTPV_MM + 536894274U, // EXTP_MM + 536896991U, // EXTRV_RS_W + 536896991U, // EXTRV_RS_W_MM + 536896545U, // EXTRV_R_W + 536896545U, // EXTRV_R_W_MM + 536892566U, // EXTRV_S_H + 536892566U, // EXTRV_S_H_MM + 536897428U, // EXTRV_W + 536897428U, // EXTRV_W_MM + 536896980U, // EXTR_RS_W + 536896980U, // EXTR_RS_W_MM + 536896524U, // EXTR_R_W + 536896524U, // EXTR_R_W_MM + 536892497U, // EXTR_S_H + 536892497U, // EXTR_S_H_MM + 536896623U, // EXTR_W + 536896623U, // EXTR_W_MM + 536895299U, // EXTS + 536887596U, // EXTS32 + 536897508U, // EXTW_NM + 536895409U, // EXT_MM + 536895409U, // EXT_MMR6 + 536895409U, // EXT_NM + 20113U, // FABS_D32 + 20113U, // FABS_D32_MM + 20113U, // FABS_D64 + 20113U, // FABS_D64_MM + 24023U, // FABS_S + 24023U, // FABS_S_MM + 536889922U, // FADD_D + 536889923U, // FADD_D32 + 536889923U, // FADD_D32_MM + 536889923U, // FADD_D64 + 536889923U, // FADD_D64_MM + 536895215U, // FADD_PS64 + 536894566U, // FADD_S + 536894566U, // FADD_S_MM + 570448998U, // FADD_S_MMR6 + 536895893U, // FADD_W + 536890156U, // FCAF_D + 536896012U, // FCAF_W + 536890595U, // FCEQ_D + 536896451U, // FCEQ_W + 20120U, // FCLASS_D + 26091U, // FCLASS_W + 536890000U, // FCLE_D + 536895935U, // FCLE_W + 536891086U, // FCLT_D + 536897030U, // FCLT_W + 5974450U, // FCMP_D32 + 5974450U, // FCMP_D32_MM + 5974450U, // FCMP_D64 + 6498738U, // FCMP_S32 + 6498738U, // FCMP_S32_MM + 536890096U, // FCNE_D + 536895969U, // FCNE_W + 536890705U, // FCOR_D + 536896580U, // FCOR_W + 536890651U, // FCUEQ_D + 536896467U, // FCUEQ_W + 536890066U, // FCULE_D + 536895951U, // FCULE_W + 536891142U, // FCULT_D + 536897046U, // FCULT_W + 536890112U, // FCUNE_D + 536895985U, // FCUNE_W + 536890525U, // FCUN_D + 536896357U, // FCUN_W + 536891518U, // FDIV_D + 536891519U, // FDIV_D32 + 536891519U, // FDIV_D32_MM + 536891519U, // FDIV_D64 + 536891519U, // FDIV_D64_MM + 536895065U, // FDIV_S + 536895065U, // FDIV_S_MM + 570449497U, // FDIV_S_MMR6 + 536897412U, // FDIV_W + 536892224U, // FEXDO_H + 536896373U, // FEXDO_W + 536889809U, // FEXP2_D + 536895796U, // FEXP2_W + 19537U, // FEXUPL_D + 25387U, // FEXUPL_W + 19809U, // FEXUPR_D + 25684U, // FEXUPR_W + 20051U, // FFINT_S_D + 25984U, // FFINT_S_W + 20530U, // FFINT_U_D + 26414U, // FFINT_U_W + 19547U, // FFQL_D + 25397U, // FFQL_W + 19819U, // FFQR_D + 25694U, // FFQR_W + 17584U, // FILL_B + 19522U, // FILL_D + 21273U, // FILL_H + 25372U, // FILL_W + 18888U, // FLOG2_D + 24875U, // FLOG2_W + 19486U, // FLOOR_L_D64 + 19486U, // FLOOR_L_D_MMR6 + 23857U, // FLOOR_L_S + 23857U, // FLOOR_L_S_MMR6 + 20661U, // FLOOR_W_D32 + 20661U, // FLOOR_W_D64 + 20661U, // FLOOR_W_D_MMR6 + 20661U, // FLOOR_W_MM + 24199U, // FLOOR_W_S + 24199U, // FLOOR_W_S_MM + 24199U, // FLOOR_W_S_MMR6 + 570444362U, // FMADD_D + 570450333U, // FMADD_W + 536889847U, // FMAX_A_D + 536895834U, // FMAX_A_W + 536891593U, // FMAX_D + 536897437U, // FMAX_W + 536889827U, // FMIN_A_D + 536895814U, // FMIN_A_W + 536890499U, // FMIN_D + 536896349U, // FMIN_W + 20622U, // FMOV_D32 + 20622U, // FMOV_D32_MM + 20622U, // FMOV_D64 + 20622U, // FMOV_D64_MM + 20622U, // FMOV_D_MMR6 + 24160U, // FMOV_S + 24160U, // FMOV_S_MM + 24160U, // FMOV_S_MMR6 + 570444320U, // FMSUB_D + 570450291U, // FMSUB_W + 536890483U, // FMUL_D + 536890484U, // FMUL_D32 + 536890484U, // FMUL_D32_MM + 536890484U, // FMUL_D64 + 536890484U, // FMUL_D64_MM + 536895231U, // FMUL_PS64 + 536894805U, // FMUL_S + 536894805U, // FMUL_S_MM + 570449237U, // FMUL_S_MMR6 + 536896333U, // FMUL_W + 19314U, // FNEG_D32 + 19314U, // FNEG_D32_MM + 19314U, // FNEG_D64 + 19314U, // FNEG_D64_MM + 23812U, // FNEG_S + 23812U, // FNEG_S_MM + 23812U, // FNEG_S_MMR6 + 2752567531U, // FORK + 2752567531U, // FORK_NM + 19648U, // FRCP_D + 25470U, // FRCP_W + 20268U, // FRINT_D + 26160U, // FRINT_W + 20296U, // FRSQRT_D + 26188U, // FRSQRT_W + 536890175U, // FSAF_D + 536896020U, // FSAF_W + 536890623U, // FSEQ_D + 536896459U, // FSEQ_W + 536890038U, // FSLE_D + 536895943U, // FSLE_W + 536891114U, // FSLT_D + 536897038U, // FSLT_W + 536890104U, // FSNE_D + 536895977U, // FSNE_W + 536890713U, // FSOR_D + 536896588U, // FSOR_W + 20287U, // FSQRT_D + 20288U, // FSQRT_D32 + 20288U, // FSQRT_D32_MM + 20288U, // FSQRT_D64 + 20288U, // FSQRT_D64_MM + 24137U, // FSQRT_S + 24137U, // FSQRT_S_MM + 26179U, // FSQRT_W + 536889880U, // FSUB_D + 536889881U, // FSUB_D32 + 536889881U, // FSUB_D32_MM + 536889881U, // FSUB_D64 + 536889881U, // FSUB_D64_MM + 536895207U, // FSUB_PS64 + 536894548U, // FSUB_S + 536894548U, // FSUB_S_MM + 570448980U, // FSUB_S_MMR6 + 536895851U, // FSUB_W + 536890672U, // FSUEQ_D + 536896476U, // FSUEQ_W + 536890087U, // FSULE_D + 536895960U, // FSULE_W + 536891163U, // FSULT_D + 536897055U, // FSULT_W + 536890121U, // FSUNE_D + 536895994U, // FSUNE_W + 536890544U, // FSUN_D + 536896365U, // FSUN_W + 20062U, // FTINT_S_D + 25995U, // FTINT_S_W + 20541U, // FTINT_U_D + 26425U, // FTINT_U_W + 536892301U, // FTQ_H + 536896485U, // FTQ_W + 19884U, // FTRUNC_S_D + 25767U, // FTRUNC_S_W + 20351U, // FTRUNC_U_D + 26235U, // FTRUNC_U_W + 547034U, // GINVI + 547034U, // GINVI_MMR6 + 547034U, // GINVI_NM + 268459939U, // GINVT + 268459939U, // GINVT_MMR6 + 268459939U, // GINVT_NM + 536890808U, // HADD_S_D + 536892380U, // HADD_S_H + 536896691U, // HADD_S_W + 536891275U, // HADD_U_D + 536892668U, // HADD_U_H + 536897159U, // HADD_U_W + 536890775U, // HSUB_S_D + 536892359U, // HSUB_S_H + 536896658U, // HSUB_S_W + 536891242U, // HSUB_U_D + 536892647U, // HSUB_U_H + 536897126U, // HSUB_U_W + 661951U, // HYPCALL + 661951U, // HYPCALL_MM + 536888999U, // ILVEV_B + 536891509U, // ILVEV_D + 536892890U, // ILVEV_H + 536897403U, // ILVEV_W + 536888527U, // ILVL_B + 536890491U, // ILVL_D + 536892216U, // ILVL_H + 536896341U, // ILVL_W + 536888279U, // ILVOD_B + 536889964U, // ILVOD_D + 536892018U, // ILVOD_H + 536895926U, // ILVOD_W + 536888575U, // ILVR_B + 536890748U, // ILVR_D + 536892341U, // ILVR_H + 536896631U, // ILVR_W + 536895196U, // INS + 292046286U, // INSERT_B + 308825909U, // INSERT_D + 325604557U, // INSERT_H + 342386233U, // INSERT_W + 33579301U, // INSV + 359154656U, // INSVE_B + 375933714U, // INSVE_D + 392712827U, // INSVE_H + 409494019U, // INSVE_W + 33579301U, // INSV_MM + 536895196U, // INS_MM + 536895196U, // INS_MMR6 + 536887297U, // INS_NM + 219361U, // J + 219400U, // JAL + 23544U, // JALR + 547832U, // JALR16_MM + 23544U, // JALR64 + 547832U, // JALRC16_MMR6 + 18725U, // JALRC16_NM + 18139U, // JALRCHB_NM + 18139U, // JALRC_HB_MMR6 + 18725U, // JALRC_MMR6 + 18725U, // JALRC_NM + 541245U, // JALRS16_MM + 24380U, // JALRS_MM + 18156U, // JALR_HB + 18156U, // JALR_HB64 + 23544U, // JALR_MM + 220867U, // JALS_MM + 223256U, // JALX + 223256U, // JALX_MM + 219400U, // JAL_MM + 18590U, // JIALC + 18590U, // JIALC64 + 18590U, // JIALC_MMR6 + 18560U, // JIC + 18560U, // JIC64 + 18560U, // JIC_MMR6 + 547828U, // JR + 541232U, // JR16_MM + 547828U, // JR64 + 547633U, // JRADDIUSP + 543008U, // JRC16_MM + 541110U, // JRC16_MMR6 + 547621U, // JRCADDIUSP_MMR6 + 543008U, // JRC_NM + 542437U, // JR_HB + 542437U, // JR_HB64 + 542437U, // JR_HB64_R6 + 542437U, // JR_HB_R6 + 547828U, // JR_MM + 219361U, // J_MM + 7575816U, // Jal16 + 8100104U, // JalB16 + 10921U, // JrRa16 + 10913U, // JrcRa16 + 543008U, // JrcRx16 + 543013U, // JumpLinkReg16 + 419451474U, // LAPC32_NM + 419447735U, // LAPC48_NM + 50349813U, // LB + 50349813U, // LB16_NM + 50349813U, // LB64 + 50352468U, // LBE + 50352468U, // LBE_MM + 50349813U, // LBGP_NM + 50348621U, // LBU16_MM + 50356150U, // LBU16_NM + 50356150U, // LBUGP_NM + 3254806564U, // LBUX + 3254806564U, // LBUX_MM + 50358308U, // LBUX_NM + 50356150U, // LBU_MMR6 + 50356150U, // LBU_NM + 50356150U, // LBUs9_NM + 50358269U, // LBX_NM + 50349813U, // LB_MM + 50349813U, // LB_MMR6 + 50349813U, // LB_NM + 50349813U, // LBs9_NM + 50356150U, // LBu + 50356150U, // LBu64 + 50352613U, // LBuE + 50352613U, // LBuE_MM + 50356150U, // LBu_MM + 50352427U, // LD + 50348124U, // LDC1 + 50348124U, // LDC164 + 50348124U, // LDC1_D64_MMR6 + 50348124U, // LDC1_MM_D32 + 50348124U, // LDC1_MM_D64 + 50348340U, // LDC2 + 50348340U, // LDC2_MMR6 + 50348340U, // LDC2_R6 + 50348425U, // LDC3 + 17410U, // LDI_B + 19330U, // LDI_D + 21149U, // LDI_H + 25222U, // LDI_W + 50354532U, // LDL + 18657U, // LDPC + 50355122U, // LDR + 3254796444U, // LDXC1 + 3254796444U, // LDXC164 + 50349000U, // LD_B + 50350685U, // LD_D + 50352739U, // LD_H + 50356647U, // LD_W + 167796753U, // LEA_ADDIU_NM + 167796753U, // LEA_ADDiu + 167796752U, // LEA_ADDiu64 + 167796753U, // LEA_ADDiu_MM + 50353692U, // LH + 50353692U, // LH16_NM + 50353692U, // LH64 + 50352520U, // LHE + 50352520U, // LHE_MM + 50353692U, // LHGP_NM + 50348644U, // LHU16_MM + 50356228U, // LHU16_NM + 50356228U, // LHUGP_NM + 50356053U, // LHUXS_NM + 50358314U, // LHUX_NM + 50356228U, // LHU_NM + 50356228U, // LHUs9_NM + 3254806542U, // LHX + 50356041U, // LHXS_NM + 3254806542U, // LHX_MM + 50358286U, // LHX_NM + 50353692U, // LH_MM + 50353692U, // LH_NM + 50353692U, // LHs9_NM + 50356228U, // LHu + 50356228U, // LHu64 + 50352619U, // LHuE + 50352619U, // LHuE_MM + 50356228U, // LHu_MM + 16884U, // LI16_MM + 16884U, // LI16_MMR6 + 218126492U, // LI16_NM + 100680391U, // LI48_NM + 50354628U, // LL + 50354628U, // LL64 + 50354628U, // LL64_R6 + 50352431U, // LLD + 50352431U, // LLD_R6 + 50352543U, // LLE + 50352543U, // LLE_MM + 536897858U, // LLWP_NM + 50354628U, // LL_MM + 50354628U, // LL_MMR6 + 50354628U, // LL_NM + 50354628U, // LL_R6 + 536888174U, // LSA + 3828450158U, // LSA_MMR6 + 536888174U, // LSA_NM + 536888174U, // LSA_R6 + 251680981U, // LUI_MMR6 + 436230357U, // LUI_NM + 3254796458U, // LUXC1 + 3254796458U, // LUXC164 + 3254796458U, // LUXC1_MM + 251680981U, // LUi + 251680981U, // LUi64 + 251680981U, // LUi_MM + 50358213U, // LW + 50348651U, // LW16_MM + 50358213U, // LW16_NM + 50358213U, // LW4x4_NM + 50358213U, // LW64 + 50348176U, // LWC1 + 50348176U, // LWC1_MM + 50348392U, // LWC2 + 50348392U, // LWC2_MMR6 + 50348392U, // LWC2_R6 + 50348437U, // LWC3 + 50358213U, // LWDSP + 50358213U, // LWDSP_MM + 50352637U, // LWE + 50352637U, // LWE_MM + 50358213U, // LWGP16_NM + 50358213U, // LWGP_MM + 50358213U, // LWGP_NM + 50354746U, // LWL + 50354746U, // LWL64 + 50352553U, // LWLE + 50352553U, // LWLE_MM + 50354746U, // LWL_MM + 66065U, // LWM16_MM + 66065U, // LWM16_MMR6 + 65805U, // LWM32_MM + 587225718U, // LWM_NM + 18694U, // LWPC + 18694U, // LWPC_MMR6 + 419449094U, // LWPC_NM + 453008210U, // LWP_MM + 50355256U, // LWR + 50355256U, // LWR64 + 50352601U, // LWRE + 50352601U, // LWRE_MM + 50355256U, // LWR_MM + 50358213U, // LWSP16_NM + 50358213U, // LWSP_MM + 18687U, // LWUPC + 50356375U, // LWU_MM + 3254806576U, // LWX + 3254796472U, // LWXC1 + 3254796472U, // LWXC1_MM + 50356060U, // LWXS16_NM + 3254804316U, // LWXS_MM + 50356060U, // LWXS_NM + 3254806576U, // LWX_MM + 50358320U, // LWX_NM + 50358213U, // LW_MM + 50358213U, // LW_MMR6 + 50358213U, // LW_NM + 50358213U, // LWs9_NM + 50356375U, // LWu + 50349813U, // LbRxRyOffMemX16 + 50356150U, // LbuRxRyOffMemX16 + 50353692U, // LhRxRyOffMemX16 + 50356228U, // LhuRxRyOffMemX16 + 1610635420U, // LiRxImm16 + 22674U, // LiRxImmAlignX16 + 22684U, // LiRxImmX16 + 26565U, // LwRxPcTcp16 + 26565U, // LwRxPcTcpX16 + 50358213U, // LwRxRyOffMemX16 + 50358213U, // LwRxSpImmX16 + 20764U, // MADD + 570444624U, // MADDF_D + 570444624U, // MADDF_D_MMR6 + 570449131U, // MADDF_S + 570449131U, // MADDF_S_MMR6 + 570446705U, // MADDR_Q_H + 570450862U, // MADDR_Q_W + 24535U, // MADDU + 536895447U, // MADDU_DSP + 536895447U, // MADDU_DSP_MM + 24535U, // MADDU_MM + 570443413U, // MADDV_B + 570445923U, // MADDV_D + 570447304U, // MADDV_H + 570451817U, // MADDV_W + 536889931U, // MADD_D32 + 536889931U, // MADD_D32_MM + 536889931U, // MADD_D64 + 536891676U, // MADD_DSP + 536891676U, // MADD_DSP_MM + 20764U, // MADD_MM + 570446675U, // MADD_Q_H + 570450832U, // MADD_Q_W + 536894565U, // MADD_S + 536894565U, // MADD_S_MM + 536893831U, // MAQ_SA_W_PHL + 536893831U, // MAQ_SA_W_PHL_MM + 536894396U, // MAQ_SA_W_PHR + 536894396U, // MAQ_SA_W_PHR_MM + 536893859U, // MAQ_S_W_PHL + 536893859U, // MAQ_S_W_PHL_MM + 536894424U, // MAQ_S_W_PHR + 536894424U, // MAQ_S_W_PHR_MM + 536889872U, // MAXA_D + 536889872U, // MAXA_D_MMR6 + 536894538U, // MAXA_S + 536894538U, // MAXA_S_MMR6 + 536888650U, // MAXI_S_B + 536890886U, // MAXI_S_D + 536892458U, // MAXI_S_H + 536896769U, // MAXI_S_W + 536888865U, // MAXI_U_B + 536891353U, // MAXI_U_D + 536892746U, // MAXI_U_H + 536897237U, // MAXI_U_W + 536888223U, // MAX_A_B + 536889848U, // MAX_A_D + 536891962U, // MAX_A_H + 536895835U, // MAX_A_W + 536891594U, // MAX_D + 536891594U, // MAX_D_MMR6 + 536895131U, // MAX_S + 536888738U, // MAX_S_B + 536891006U, // MAX_S_D + 536892577U, // MAX_S_H + 536895131U, // MAX_S_MMR6 + 536896950U, // MAX_S_W + 536888953U, // MAX_U_B + 536891473U, // MAX_U_D + 536892844U, // MAX_U_H + 536897357U, // MAX_U_W + 536887304U, // MFC0 + 16392U, // MFC0Sel_NM + 536887304U, // MFC0_MMR6 + 536887304U, // MFC0_NM + 16495U, // MFC1 + 16495U, // MFC1_D64 + 16495U, // MFC1_MM + 16495U, // MFC1_MMR6 + 536887623U, // MFC2 + 16711U, // MFC2_MMR6 + 536887311U, // MFGC0 + 536887311U, // MFGC0_MM + 16430U, // MFHC0Sel_NM + 536887342U, // MFHC0_MMR6 + 536887342U, // MFHC0_NM + 16501U, // MFHC1_D32 + 16501U, // MFHC1_D32_MM + 16501U, // MFHC1_D64 + 16501U, // MFHC1_D64_MM + 16717U, // MFHC2_MMR6 + 536887318U, // MFHGC0 + 536887318U, // MFHGC0_MM + 546950U, // MFHI + 541164U, // MFHI16_MM + 546950U, // MFHI64 + 22662U, // MFHI_DSP + 22662U, // MFHI_DSP_MM + 546950U, // MFHI_MM + 547486U, // MFLO + 541215U, // MFLO16_MM + 547486U, // MFLO64 + 23198U, // MFLO_DSP + 23198U, // MFLO_DSP_MM + 547486U, // MFLO_MM + 536894494U, // MFTR + 536894494U, // MFTR_NM + 536889857U, // MINA_D + 536889857U, // MINA_D_MMR6 + 536894530U, // MINA_S + 536894530U, // MINA_S_MMR6 + 536888630U, // MINI_S_B + 536890866U, // MINI_S_D + 536892438U, // MINI_S_H + 536896749U, // MINI_S_W + 536888845U, // MINI_U_B + 536891333U, // MINI_U_D + 536892726U, // MINI_U_H + 536897217U, // MINI_U_W + 536888204U, // MIN_A_B + 536889828U, // MIN_A_D + 536891943U, // MIN_A_H + 536895815U, // MIN_A_W + 536890500U, // MIN_D + 536890500U, // MIN_D_MMR6 + 536894812U, // MIN_S + 536888660U, // MIN_S_B + 536890896U, // MIN_S_D + 536892468U, // MIN_S_H + 536894812U, // MIN_S_MMR6 + 536896789U, // MIN_S_W + 536888875U, // MIN_U_B + 536891363U, // MIN_U_D + 536892756U, // MIN_U_H + 536897247U, // MIN_U_W + 536891723U, // MOD + 536889417U, // MODSUB + 536889417U, // MODSUB_MM + 536895455U, // MODU + 536895455U, // MODU_MMR6 + 536895455U, // MODU_NM + 536891723U, // MOD_MMR6 + 536891723U, // MOD_NM + 536888593U, // MOD_S_B + 536890829U, // MOD_S_D + 536892401U, // MOD_S_H + 536896712U, // MOD_S_W + 536888808U, // MOD_U_B + 536891296U, // MOD_U_D + 536892689U, // MOD_U_H + 536897180U, // MOD_U_W + 20983U, // MOVE16_MM + 16854U, // MOVE16_MMR6 + 536889491U, // MOVEBALC_NM + 536894161U, // MOVEPREV_NM + 536894161U, // MOVEP_MM + 536894161U, // MOVEP_MMR6 + 536894161U, // MOVEP_NM + 20983U, // MOVE_NM + 24739U, // MOVE_V + 536890217U, // MOVF_D32 + 536890217U, // MOVF_D32_MM + 536890217U, // MOVF_D64 + 536891923U, // MOVF_I + 536891923U, // MOVF_I64 + 536891923U, // MOVF_I_MM + 536894716U, // MOVF_S + 536894716U, // MOVF_S_MM + 536890552U, // MOVN_I64_D64 + 536894098U, // MOVN_I64_I + 536894098U, // MOVN_I64_I64 + 536894848U, // MOVN_I64_S + 536890552U, // MOVN_I_D32 + 536890552U, // MOVN_I_D32_MM + 536890552U, // MOVN_I_D64 + 536894098U, // MOVN_I_I + 536894098U, // MOVN_I_I64 + 536894098U, // MOVN_I_MM + 536894848U, // MOVN_I_S + 536894848U, // MOVN_I_S_MM + 536894098U, // MOVN_NM + 536891224U, // MOVT_D32 + 536891224U, // MOVT_D32_MM + 536891224U, // MOVT_D64 + 536895402U, // MOVT_I + 536895402U, // MOVT_I64 + 536895402U, // MOVT_I_MM + 536895057U, // MOVT_S + 536895057U, // MOVT_S_MM + 536891634U, // MOVZ_I64_D64 + 536897666U, // MOVZ_I64_I + 536897666U, // MOVZ_I64_I64 + 536895158U, // MOVZ_I64_S + 536891634U, // MOVZ_I_D32 + 536891634U, // MOVZ_I_D32_MM + 536891634U, // MOVZ_I_D64 + 536897666U, // MOVZ_I_I + 536897666U, // MOVZ_I_I64 + 536897666U, // MOVZ_I_MM + 536895158U, // MOVZ_I_S + 536895158U, // MOVZ_I_S_MM + 536897666U, // MOVZ_NM + 18513U, // MSUB + 570444615U, // MSUBF_D + 570444615U, // MSUBF_D_MMR6 + 570449122U, // MSUBF_S + 570449122U, // MSUBF_S_MMR6 + 570446694U, // MSUBR_Q_H + 570450851U, // MSUBR_Q_W + 24514U, // MSUBU + 536895426U, // MSUBU_DSP + 536895426U, // MSUBU_DSP_MM + 24514U, // MSUBU_MM + 570443404U, // MSUBV_B + 570445914U, // MSUBV_D + 570447295U, // MSUBV_H + 570451808U, // MSUBV_W + 536889889U, // MSUB_D32 + 536889889U, // MSUB_D32_MM + 536889889U, // MSUB_D64 + 536889425U, // MSUB_DSP + 536889425U, // MSUB_DSP_MM + 18513U, // MSUB_MM + 570446665U, // MSUB_Q_H + 570450822U, // MSUB_Q_W + 536894547U, // MSUB_S + 536894547U, // MSUB_S_MM + 2752561213U, // MTC0 + 16445U, // MTC0Sel_NM + 2752561213U, // MTC0_MMR6 + 536887357U, // MTC0_NM + 17875082U, // MTC1 + 17875082U, // MTC1_D64 + 17875082U, // MTC1_D64_MM + 17875082U, // MTC1_MM + 17875082U, // MTC1_MMR6 + 2752561506U, // MTC2 + 17875298U, // MTC2_MMR6 + 2752561191U, // MTGC0 + 2752561191U, // MTGC0_MM + 16437U, // MTHC0Sel_NM + 2752561205U, // MTHC0_MMR6 + 536887349U, // MTHC0_NM + 17924220U, // MTHC1_D32 + 17924220U, // MTHC1_D32_MM + 17924220U, // MTHC1_D64 + 17924220U, // MTHC1_D64_MM + 17875284U, // MTHC2_MMR6 + 2752561182U, // MTHGC0 + 2752561182U, // MTHGC0_MM + 546956U, // MTHI + 546956U, // MTHI64 + 17881228U, // MTHI_DSP + 17881228U, // MTHI_DSP_MM + 546956U, // MTHI_MM + 17881816U, // MTHLIP + 17881816U, // MTHLIP_MM + 547499U, // MTLO + 547499U, // MTLO64 + 17881771U, // MTLO_DSP + 17881771U, // MTLO_DSP_MM + 547499U, // MTLO_MM + 540745U, // MTM0 + 540870U, // MTM1 + 541044U, // MTM2 + 540751U, // MTP0 + 540876U, // MTP1 + 541050U, // MTP2 + 68213803U, // MTTR + 68213803U, // MTTR_NM + 536893525U, // MUH + 536895498U, // MUHU + 536895498U, // MUHU_MMR6 + 536895498U, // MUHU_NM + 536893525U, // MUH_MMR6 + 536893525U, // MUH_NM + 536893991U, // MUL + 536893991U, // MUL4x4_NM + 536893872U, // MULEQ_S_W_PHL + 536893872U, // MULEQ_S_W_PHL_MM + 536894437U, // MULEQ_S_W_PHR + 536894437U, // MULEQ_S_W_PHR_MM + 536893749U, // MULEU_S_PH_QBL + 536893749U, // MULEU_S_PH_QBL_MM + 536894339U, // MULEU_S_PH_QBR + 536894339U, // MULEU_S_PH_QBR_MM + 536893279U, // MULQ_RS_PH + 536893279U, // MULQ_RS_PH_MM + 536896969U, // MULQ_RS_W + 536896969U, // MULQ_RS_W_MMR2 + 536893223U, // MULQ_S_PH + 536893223U, // MULQ_S_PH_MMR2 + 536896828U, // MULQ_S_W + 536896828U, // MULQ_S_W_MMR2 + 536895256U, // MULR_PS64 + 536892284U, // MULR_Q_H + 536896441U, // MULR_Q_W + 536893425U, // MULSAQ_S_W_PH + 536893425U, // MULSAQ_S_W_PH_MM + 536893400U, // MULSA_W_PH + 536893400U, // MULSA_W_PH_MMR2 + 24462U, // MULT + 536895618U, // MULTU_DSP + 536895618U, // MULTU_DSP_MM + 536895374U, // MULT_DSP + 536895374U, // MULT_DSP_MM + 24462U, // MULT_MM + 24706U, // MULTu + 24706U, // MULTu_MM + 536895535U, // MULU + 536895535U, // MULU_MMR6 + 536895535U, // MULU_NM + 536889008U, // MULV_B + 536891526U, // MULV_D + 536892899U, // MULV_H + 536897420U, // MULV_W + 536893991U, // MUL_MM + 536893991U, // MUL_MMR6 + 536893991U, // MUL_NM + 536893096U, // MUL_PH + 536893096U, // MUL_PH_MMR2 + 536892253U, // MUL_Q_H + 536896410U, // MUL_Q_W + 536893991U, // MUL_R6 + 536893191U, // MUL_S_PH + 536893191U, // MUL_S_PH_MMR2 + 546950U, // Mfhi16 + 547486U, // Mflo16 + 20983U, // Move32R16 + 20983U, // MoveR3216 + 17327U, // NLOC_B + 18994U, // NLOC_D + 21066U, // NLOC_H + 24956U, // NLOC_W + 17343U, // NLZC_B + 19002U, // NLZC_D + 21082U, // NLZC_H + 24964U, // NLZC_W + 536889939U, // NMADD_D32 + 536889939U, // NMADD_D32_MM + 536889939U, // NMADD_D64 + 536894564U, // NMADD_S + 536894564U, // NMADD_S_MM + 536889897U, // NMSUB_D32 + 536889897U, // NMSUB_D32_MM + 536889897U, // NMSUB_D64 + 536894546U, // NMSUB_S + 536894546U, // NMSUB_S_MM + 10802U, // NOP32_NM + 11006U, // NOP_NM + 536894462U, // NOR + 536894462U, // NOR64 + 536888416U, // NORI_B + 536894462U, // NOR_MM + 536894462U, // NOR_MMR6 + 536894462U, // NOR_NM + 536895667U, // NOR_V + 16966U, // NOT16_MM + 16966U, // NOT16_MMR6 + 24478U, // NOT16_NM + 21017U, // NegRxRy16 + 24478U, // NotRxRy16 + 536894463U, // OR + 20021815U, // OR16_MM + 20021815U, // OR16_MMR6 + 536894463U, // OR16_NM + 536894463U, // OR64 + 536888417U, // ORI_B + 536893624U, // ORI_MMR6 + 536893624U, // ORI_NM + 536894463U, // OR_MM + 536894463U, // OR_MMR6 + 536894463U, // OR_NM + 536895668U, // OR_V + 536893624U, // ORi + 536893624U, // ORi64 + 536893624U, // ORi_MM + 33577983U, // OrRxRxRy16 + 536893085U, // PACKRL_PH + 536893085U, // PACKRL_PH_MM + 10939U, // PAUSE + 10939U, // PAUSE_MM + 10939U, // PAUSE_MMR6 + 10939U, // PAUSE_NM + 536888990U, // PCKEV_B + 536891500U, // PCKEV_D + 536892881U, // PCKEV_H + 536897394U, // PCKEV_W + 536888270U, // PCKOD_B + 536889955U, // PCKOD_D + 536892009U, // PCKOD_H + 536895917U, // PCKOD_W + 17862U, // PCNT_B + 20260U, // PCNT_D + 21701U, // PCNT_H + 26152U, // PCNT_W + 536893049U, // PICK_PH + 536893049U, // PICK_PH_MM + 536889149U, // PICK_QB + 536889149U, // PICK_QB_MM + 536895223U, // PLL_PS64 + 536895265U, // PLU_PS64 + 23270U, // POP + 22868U, // PRECEQU_PH_QBL + 17200U, // PRECEQU_PH_QBLA + 17200U, // PRECEQU_PH_QBLA_MM + 22868U, // PRECEQU_PH_QBL_MM + 23458U, // PRECEQU_PH_QBR + 17238U, // PRECEQU_PH_QBRA + 17238U, // PRECEQU_PH_QBRA_MM + 23458U, // PRECEQU_PH_QBR_MM + 22933U, // PRECEQ_W_PHL + 22933U, // PRECEQ_W_PHL_MM + 23498U, // PRECEQ_W_PHR + 23498U, // PRECEQ_W_PHR_MM + 22853U, // PRECEU_PH_QBL + 17184U, // PRECEU_PH_QBLA + 17184U, // PRECEU_PH_QBLA_MM + 22853U, // PRECEU_PH_QBL_MM + 23443U, // PRECEU_PH_QBR + 17222U, // PRECEU_PH_QBRA + 17222U, // PRECEU_PH_QBRA_MM + 23443U, // PRECEU_PH_QBR_MM + 536893001U, // PRECRQU_S_QB_PH + 536893001U, // PRECRQU_S_QB_PH_MM + 536896060U, // PRECRQ_PH_W + 536896060U, // PRECRQ_PH_W_MM + 536892974U, // PRECRQ_QB_PH + 536892974U, // PRECRQ_QB_PH_MM + 536896091U, // PRECRQ_RS_PH_W + 536896091U, // PRECRQ_RS_PH_W_MM + 536892988U, // PRECR_QB_PH + 536892988U, // PRECR_QB_PH_MMR2 + 536896044U, // PRECR_SRA_PH_W + 536896044U, // PRECR_SRA_PH_W_MMR2 + 536896073U, // PRECR_SRA_R_PH_W + 536896073U, // PRECR_SRA_R_PH_W_MMR2 + 5411341U, // PREF + 5411179U, // PREFE + 5411179U, // PREFE_MM + 473081863U, // PREFX_MM + 5411341U, // PREF_MM + 5411341U, // PREF_MMR6 + 50516493U, // PREF_NM + 5411341U, // PREF_R6 + 50516493U, // PREFs9_NM + 536891705U, // PREPEND + 536891705U, // PREPEND_MMR2 + 536895239U, // PUL_PS64 + 536895273U, // PUU_PS64 + 18489U, // RADDU_W_QB + 18489U, // RADDU_W_QB_MM + 234904343U, // RDDSP + 218127127U, // RDDSP_MM + 536894513U, // RDHWR + 536894513U, // RDHWR64 + 536894513U, // RDHWR_MM + 536894513U, // RDHWR_MMR6 + 536894513U, // RDHWR_NM + 23566U, // RDPGPR_MMR6 + 23566U, // RDPGPR_NM + 19656U, // RECIP_D32 + 19656U, // RECIP_D32_MM + 19656U, // RECIP_D64 + 19656U, // RECIP_D64_MM + 23944U, // RECIP_S + 23944U, // RECIP_S_MM + 22428U, // REPLV_PH + 22428U, // REPLV_PH_MM + 18469U, // REPLV_QB + 18469U, // REPLV_QB_MM + 22155U, // REPL_PH + 22155U, // REPL_PH_MM + 486557519U, // REPL_QB + 486557519U, // REPL_QB_MM + 248088U, // RESTOREJRC16_NM + 264472U, // RESTOREJRC_NM + 266704U, // RESTORE_NM + 20269U, // RINT_D + 20269U, // RINT_D_MMR6 + 24128U, // RINT_S + 24128U, // RINT_S_MMR6 + 536894501U, // ROTR + 536895774U, // ROTRV + 536895774U, // ROTRV_MM + 536895774U, // ROTRV_NM + 536894501U, // ROTR_MM + 536894501U, // ROTR_NM + 536897566U, // ROTX_NM + 19465U, // ROUND_L_D64 + 19465U, // ROUND_L_D_MMR6 + 23836U, // ROUND_L_S + 23836U, // ROUND_L_S_MMR6 + 20640U, // ROUND_W_D32 + 20640U, // ROUND_W_D64 + 20640U, // ROUND_W_D_MMR6 + 20640U, // ROUND_W_MM + 24178U, // ROUND_W_S + 24178U, // ROUND_W_S_MM + 24178U, // ROUND_W_S_MMR6 + 20297U, // RSQRT_D32 + 20297U, // RSQRT_D32_MM + 20297U, // RSQRT_D64 + 20297U, // RSQRT_D64_MM + 24136U, // RSQRT_S + 24136U, // RSQRT_S_MM + 0U, // Restore16 + 0U, // RestoreX16 + 8405787U, // SAA + 8409346U, // SAAD + 536888699U, // SAT_S_B + 536890945U, // SAT_S_D + 536892527U, // SAT_S_H + 536896878U, // SAT_S_W + 536888926U, // SAT_U_B + 536891424U, // SAT_U_D + 536892817U, // SAT_U_H + 536897308U, // SAT_U_W + 250353U, // SAVE16_NM + 266737U, // SAVE_NM + 50350149U, // SB + 50348458U, // SB16_MM + 50348458U, // SB16_MMR6 + 50350149U, // SB16_NM + 50350149U, // SB64 + 50352473U, // SBE + 50352473U, // SBE_MM + 50350149U, // SBGP_NM + 50358274U, // SBX_NM + 50350149U, // SB_MM + 50350149U, // SB_MMR6 + 50350149U, // SB_NM + 50350149U, // SBs9_NM + 8964399U, // SC + 8964399U, // SC64 + 8964399U, // SC64_R6 + 8966417U, // SCD + 8966417U, // SCD_R6 + 8966494U, // SCE + 8966494U, // SCE_MM + 606136636U, // SCWP_NM + 8964399U, // SC_MM + 8964399U, // SC_MMR6 + 8964399U, // SC_NM + 8964399U, // SC_R6 + 50352464U, // SD + 285378U, // SDBBP + 148007U, // SDBBP16_MM + 148007U, // SDBBP16_MMR6 + 547522U, // SDBBP16_NM + 662210U, // SDBBP_MM + 285378U, // SDBBP_MMR6 + 547522U, // SDBBP_NM + 285378U, // SDBBP_R6 + 50348130U, // SDC1 + 50348130U, // SDC164 + 50348130U, // SDC1_D64_MMR6 + 50348130U, // SDC1_MM_D32 + 50348130U, // SDC1_MM_D64 + 50348346U, // SDC2 + 50348346U, // SDC2_MMR6 + 50348346U, // SDC2_R6 + 50348431U, // SDC3 + 26787U, // SDIV + 26787U, // SDIV_MM + 50354537U, // SDL + 50355127U, // SDR + 3254796451U, // SDXC1 + 3254796451U, // SDXC164 + 18134U, // SEB + 18134U, // SEB64 + 18134U, // SEB_MM + 18134U, // SEB_NM + 22037U, // SEH + 22037U, // SEH64 + 22037U, // SEH_MM + 22037U, // SEH_NM + 536897639U, // SELEQZ + 536897639U, // SELEQZ64 + 536891624U, // SELEQZ_D + 536891624U, // SELEQZ_D_MMR6 + 536897639U, // SELEQZ_MMR6 + 536895148U, // SELEQZ_S + 536895148U, // SELEQZ_S_MMR6 + 536897612U, // SELNEZ + 536897612U, // SELNEZ64 + 536891607U, // SELNEZ_D + 536891607U, // SELNEZ_D_MMR6 + 536897612U, // SELNEZ_MMR6 + 536895138U, // SELNEZ_S + 536895138U, // SELNEZ_S_MMR6 + 570444850U, // SEL_D + 570444850U, // SEL_D_MMR6 + 570449221U, // SEL_S + 570449221U, // SEL_S_MMR6 + 536894305U, // SEQ + 536893611U, // SEQI_NM + 536893611U, // SEQi + 50354251U, // SH + 50348510U, // SH16_MM + 50348510U, // SH16_MMR6 + 50354251U, // SH16_NM + 50354251U, // SH64 + 50352525U, // SHE + 50352525U, // SHE_MM + 536888298U, // SHF_B + 536892037U, // SHF_H + 536896029U, // SHF_W + 50354251U, // SHGP_NM + 23204U, // SHILO + 24832U, // SHILOV + 24832U, // SHILOV_MM + 23204U, // SHILO_MM + 536893330U, // SHLLV_PH + 536893330U, // SHLLV_PH_MM + 536889371U, // SHLLV_QB + 536889371U, // SHLLV_QB_MM + 536893267U, // SHLLV_S_PH + 536893267U, // SHLLV_S_PH_MM + 536896939U, // SHLLV_S_W + 536896939U, // SHLLV_S_W_MM + 536893058U, // SHLL_PH + 536893058U, // SHLL_PH_MM + 536889158U, // SHLL_QB + 536889158U, // SHLL_QB_MM + 536893180U, // SHLL_S_PH + 536893180U, // SHLL_S_PH_MM + 536896779U, // SHLL_S_W + 536896779U, // SHLL_S_W_MM + 536893320U, // SHRAV_PH + 536893320U, // SHRAV_PH_MM + 536889361U, // SHRAV_QB + 536889361U, // SHRAV_QB_MMR2 + 536893168U, // SHRAV_R_PH + 536893168U, // SHRAV_R_PH_MM + 536889259U, // SHRAV_R_QB + 536889259U, // SHRAV_R_QB_MMR2 + 536896534U, // SHRAV_R_W + 536896534U, // SHRAV_R_W_MM + 536892965U, // SHRA_PH + 536892965U, // SHRA_PH_MM + 536889081U, // SHRA_QB + 536889081U, // SHRA_QB_MMR2 + 536893133U, // SHRA_R_PH + 536893133U, // SHRA_R_PH_MM + 536889224U, // SHRA_R_QB + 536889224U, // SHRA_R_QB_MMR2 + 536896492U, // SHRA_R_W + 536896492U, // SHRA_R_W_MM + 536893350U, // SHRLV_PH + 536893350U, // SHRLV_PH_MMR2 + 536889391U, // SHRLV_QB + 536889391U, // SHRLV_QB_MM + 536893076U, // SHRL_PH + 536893076U, // SHRL_PH_MMR2 + 536889176U, // SHRL_QB + 536889176U, // SHRL_QB_MM + 50356047U, // SHXS_NM + 50358291U, // SHX_NM + 50354251U, // SH_MM + 50354251U, // SH_MMR6 + 50354251U, // SH_NM + 50354251U, // SHs9_NM + 299410U, // SIGRIE + 299410U, // SIGRIE_MMR6 + 545170U, // SIGRIE_NM + 1107313665U, // SLDI_B + 1107315585U, // SLDI_D + 1107317404U, // SLDI_H + 1107321477U, // SLDI_W + 1107313607U, // SLD_B + 1107315292U, // SLD_D + 1107317346U, // SLD_H + 1107321254U, // SLD_W + 536893924U, // SLL + 536887811U, // SLL16_MM + 536887811U, // SLL16_MMR6 + 536893924U, // SLL16_NM + 1073764836U, // SLL64_32 + 1073764836U, // SLL64_64 + 536888355U, // SLLI_B + 536890258U, // SLLI_D + 536892077U, // SLLI_H + 536896150U, // SLLI_W + 536895731U, // SLLV + 536895731U, // SLLV_MM + 536895731U, // SLLV_NM + 536888504U, // SLL_B + 536890442U, // SLL_D + 536892193U, // SLL_H + 536893924U, // SLL_MM + 536893924U, // SLL_MMR6 + 536893924U, // SLL_NM + 536896292U, // SLL_W + 536895363U, // SLT + 536895363U, // SLT64 + 536895519U, // SLTIU_NM + 536893635U, // SLTI_NM + 536895605U, // SLTU_NM + 536895363U, // SLT_MM + 536895363U, // SLT_NM + 536893635U, // SLTi + 536893635U, // SLTi64 + 536893635U, // SLTi_MM + 536895519U, // SLTiu + 536895519U, // SLTiu64 + 536895519U, // SLTiu_MM + 536895605U, // SLTu + 536895605U, // SLTu64 + 536895605U, // SLTu_MM + 536891834U, // SNE + 536893556U, // SNEi + 536895752U, // SOV_NM + 1073759354U, // SPLATI_B + 1073761241U, // SPLATI_D + 1073763060U, // SPLATI_H + 1073767133U, // SPLATI_W + 1073759669U, // SPLAT_B + 1073761954U, // SPLAT_D + 1073763508U, // SPLAT_H + 1073767925U, // SPLAT_W + 536888168U, // SRA + 536888313U, // SRAI_B + 536890233U, // SRAI_D + 536892052U, // SRAI_H + 536896125U, // SRAI_W + 536888389U, // SRARI_B + 536890292U, // SRARI_D + 536892111U, // SRARI_H + 536896184U, // SRARI_W + 536888542U, // SRAR_B + 536890681U, // SRAR_D + 536892308U, // SRAR_H + 536896556U, // SRAR_W + 536895710U, // SRAV + 536895710U, // SRAV_MM + 536895710U, // SRAV_NM + 536888232U, // SRA_B + 536889865U, // SRA_D + 536891971U, // SRA_H + 536888168U, // SRA_MM + 536888168U, // SRA_NM + 536895844U, // SRA_W + 536893952U, // SRL + 536887818U, // SRL16_MM + 536887818U, // SRL16_MMR6 + 536893952U, // SRL16_NM + 536888363U, // SRLI_B + 536890266U, // SRLI_D + 536892085U, // SRLI_H + 536896158U, // SRLI_W + 536888407U, // SRLRI_B + 536890310U, // SRLRI_D + 536892129U, // SRLRI_H + 536896202U, // SRLRI_W + 536888558U, // SRLR_B + 536890697U, // SRLR_D + 536892324U, // SRLR_H + 536896572U, // SRLR_W + 536895738U, // SRLV + 536895738U, // SRLV_MM + 536895738U, // SRLV_NM + 536888511U, // SRL_B + 536890467U, // SRL_D + 536892200U, // SRL_H + 536893952U, // SRL_MM + 536893952U, // SRL_NM + 536896317U, // SRL_W + 11004U, // SSNOP + 11004U, // SSNOP_MM + 11004U, // SSNOP_MMR6 + 50349528U, // ST_B + 50351954U, // ST_D + 50353367U, // ST_H + 50357846U, // ST_W + 536889420U, // SUB + 536893029U, // SUBQH_PH + 536893029U, // SUBQH_PH_MMR2 + 536893144U, // SUBQH_R_PH + 536893144U, // SUBQH_R_PH_MMR2 + 536896502U, // SUBQH_R_W + 536896502U, // SUBQH_R_W_MMR2 + 536896107U, // SUBQH_W + 536896107U, // SUBQH_W_MMR2 + 536893104U, // SUBQ_PH + 536893104U, // SUBQ_PH_MM + 536893201U, // SUBQ_S_PH + 536893201U, // SUBQ_S_PH_MM + 536896808U, // SUBQ_S_W + 536896808U, // SUBQ_S_W_MM + 536888914U, // SUBSUS_U_B + 536891412U, // SUBSUS_U_D + 536892805U, // SUBSUS_U_H + 536897296U, // SUBSUS_U_W + 536888717U, // SUBSUU_S_B + 536890985U, // SUBSUU_S_D + 536892545U, // SUBSUU_S_H + 536896918U, // SUBSUU_S_W + 536888679U, // SUBS_S_B + 536890925U, // SUBS_S_D + 536892507U, // SUBS_S_H + 536896858U, // SUBS_S_W + 536888894U, // SUBS_U_B + 536891392U, // SUBS_U_D + 536892785U, // SUBS_U_H + 536897276U, // SUBS_U_W + 536887892U, // SUBU16_MM + 536887892U, // SUBU16_MMR6 + 536889129U, // SUBUH_QB + 536889129U, // SUBUH_QB_MMR2 + 536889235U, // SUBUH_R_QB + 536889235U, // SUBUH_R_QB_MMR2 + 536895420U, // SUBU_MMR6 + 536893302U, // SUBU_PH + 536893302U, // SUBU_PH_MMR2 + 536889343U, // SUBU_QB + 536889343U, // SUBU_QB_MM + 536893245U, // SUBU_S_PH + 536893245U, // SUBU_S_PH_MMR2 + 536889282U, // SUBU_S_QB + 536889282U, // SUBU_S_QB_MM + 536888461U, // SUBVI_B + 536890348U, // SUBVI_D + 536892167U, // SUBVI_H + 536896240U, // SUBVI_W + 536888973U, // SUBV_B + 536891483U, // SUBV_D + 536892864U, // SUBV_H + 536897377U, // SUBV_W + 536889420U, // SUB_MM + 536889420U, // SUB_MMR6 + 536889420U, // SUB_NM + 536895420U, // SUBu + 536895420U, // SUBu16_NM + 536895420U, // SUBu_MM + 536895420U, // SUBu_NM + 3254796465U, // SUXC1 + 3254796465U, // SUXC164 + 3254796465U, // SUXC1_MM + 50358235U, // SW + 50348657U, // SW16_MM + 50348657U, // SW16_MMR6 + 50358235U, // SW16_NM + 50358235U, // SW4x4_NM + 50358235U, // SW64 + 50348182U, // SWC1 + 50348182U, // SWC1_MM + 50348398U, // SWC2 + 50348398U, // SWC2_MMR6 + 50348398U, // SWC2_R6 + 50348443U, // SWC3 + 50358235U, // SWDSP + 50358235U, // SWDSP_MM + 50352642U, // SWE + 50352642U, // SWE_MM + 50358235U, // SWGP16_NM + 50358235U, // SWGP_NM + 50354751U, // SWL + 50354751U, // SWL64 + 50352559U, // SWLE + 50352559U, // SWLE_MM + 50354751U, // SWL_MM + 66072U, // SWM16_MM + 66072U, // SWM16_MMR6 + 65812U, // SWM32_MM + 587225725U, // SWM_NM + 419449100U, // SWPC_NM + 453008215U, // SWP_MM + 50355261U, // SWR + 50355261U, // SWR64 + 50352607U, // SWRE + 50352607U, // SWRE_MM + 50355261U, // SWR_MM + 50358235U, // SWSP16_NM + 50355004U, // SWSP_MM + 50358235U, // SWSP_MMR6 + 3254796479U, // SWXC1 + 3254796479U, // SWXC1_MM + 50356066U, // SWXS_NM + 50358325U, // SWX_NM + 50358235U, // SW_MM + 50358235U, // SW_MMR6 + 50358235U, // SW_NM + 50358235U, // SWs9_NM + 714997U, // SYNC + 317530U, // SYNCI + 317530U, // SYNCI_MM + 317530U, // SYNCI_MMR6 + 317530U, // SYNCI_NM + 317530U, // SYNCIs9_NM + 714997U, // SYNC_MM + 706779U, // SYNC_MMR6 + 706779U, // SYNC_NM + 285128U, // SYSCALL + 547272U, // SYSCALL16_NM + 661960U, // SYSCALL_MM + 547272U, // SYSCALL_NM + 0U, // Save16 + 0U, // SaveX16 + 50350149U, // SbRxRyOffMemX16 + 551048U, // SebRx16 + 551054U, // SehRx16 + 50354251U, // ShRxRyOffMemX16 + 536893924U, // SllX16 + 33579251U, // SllvRxRy16 + 24451U, // SltRxRy16 + 1610635459U, // SltiRxImm16 + 22723U, // SltiRxImmX16 + 1610637343U, // SltiuRxImm16 + 24607U, // SltiuRxImmX16 + 24693U, // SltuRxRy16 + 536888168U, // SraX16 + 33579230U, // SravRxRy16 + 536893952U, // SrlX16 + 33579258U, // SrlvRxRy16 + 536895420U, // SubuRxRyRz16 + 50358235U, // SwRxRyOffMemX16 + 50358235U, // SwRxSpImmX16 + 536894310U, // TEQ + 22705U, // TEQI + 22705U, // TEQI_MM + 536894310U, // TEQ_MM + 536894310U, // TEQ_NM + 536891772U, // TGE + 22638U, // TGEI + 24600U, // TGEIU + 24600U, // TGEIU_MM + 22638U, // TGEI_MM + 536895473U, // TGEU + 536895473U, // TGEU_MM + 536891772U, // TGE_MM + 11052U, // TLBGINV + 10953U, // TLBGINVF + 10953U, // TLBGINVF_MM + 11052U, // TLBGINV_MM + 10998U, // TLBGP + 10998U, // TLBGP_MM + 11015U, // TLBGR + 11015U, // TLBGR_MM + 10968U, // TLBGWI + 10968U, // TLBGWI_MM + 11027U, // TLBGWR + 11027U, // TLBGWR_MM + 11045U, // TLBINV + 10945U, // TLBINVF + 10945U, // TLBINVF_MMR6 + 10945U, // TLBINVF_NM + 11045U, // TLBINV_MMR6 + 11045U, // TLBINV_NM + 10993U, // TLBP + 10993U, // TLBP_MM + 10993U, // TLBP_NM + 11010U, // TLBR + 11010U, // TLBR_MM + 11010U, // TLBR_NM + 10962U, // TLBWI + 10962U, // TLBWI_MM + 10962U, // TLBWI_NM + 11021U, // TLBWR + 11021U, // TLBWR_MM + 11021U, // TLBWR_NM + 536895368U, // TLT + 22729U, // TLTI + 24614U, // TLTIU_MM + 22729U, // TLTI_MM + 536895611U, // TLTU + 536895611U, // TLTU_MM + 536895368U, // TLT_MM + 536891839U, // TNE + 22650U, // TNEI + 22650U, // TNEI_MM + 536891839U, // TNE_MM + 536891839U, // TNE_NM + 19454U, // TRUNC_L_D64 + 19454U, // TRUNC_L_D_MMR6 + 23825U, // TRUNC_L_S + 23825U, // TRUNC_L_S_MMR6 + 20629U, // TRUNC_W_D32 + 20629U, // TRUNC_W_D64 + 20629U, // TRUNC_W_D_MMR6 + 20629U, // TRUNC_W_MM + 24167U, // TRUNC_W_S + 24167U, // TRUNC_W_S_MM + 24167U, // TRUNC_W_S_MMR6 + 24614U, // TTLTIU + 50353690U, // UALH_NM + 587225716U, // UALWM_NM + 50358211U, // UALW_NM + 50354249U, // UASH_NM + 587225723U, // UASWM_NM + 50358233U, // UASW_NM + 26773U, // UDIV + 26773U, // UDIV_MM + 536895533U, // V3MULU + 536887363U, // VMM0 + 536895548U, // VMULU + 570442729U, // VSHF_B + 570444633U, // VSHF_D + 570446468U, // VSHF_H + 570450460U, // VSHF_W + 11040U, // WAIT + 663416U, // WAIT_MM + 663416U, // WAIT_MMR6 + 663416U, // WAIT_NM + 234904350U, // WRDSP + 218127134U, // WRDSP_MM + 23574U, // WRPGPR_MMR6 + 23574U, // WRPGPR_NM + 22022U, // WSBH + 22022U, // WSBH_MM + 22022U, // WSBH_MMR6 + 536894473U, // XOR + 20021814U, // XOR16_MM + 20021814U, // XOR16_MMR6 + 536894473U, // XOR16_NM + 536894473U, // XOR64 + 536888424U, // XORI_B + 536893623U, // XORI_MMR6 + 536893623U, // XORI_NM + 536894473U, // XOR_MM + 536894473U, // XOR_MMR6 + 536894473U, // XOR_NM + 536895674U, // XOR_V + 536893623U, // XORi + 536893623U, // XORi64 + 536893623U, // XORi_MM + 33577993U, // XorRxRxRy16 + 20776U, // YIELD + 20776U, // YIELD_NM }; - static const uint8_t OpInfo2[] = { + static const uint16_t OpInfo1[] = { 0U, // PHI 0U, // INLINEASM + 0U, // INLINEASM_BR 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG @@ -1815,725 +4463,1716 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 0U, // DBG_VALUE + 0U, // DBG_VALUE_LIST + 0U, // DBG_INSTR_REF + 0U, // DBG_PHI + 0U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 0U, // BUNDLE 0U, // LIFETIME_START 0U, // LIFETIME_END + 0U, // PSEUDO_PROBE + 0U, // ARITH_FENCE 0U, // STACKMAP + 0U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG 0U, // STATEPOINT - 0U, // FRAME_ALLOC - 0U, // ABSQ_S_PH - 0U, // ABSQ_S_QB - 0U, // ABSQ_S_W - 0U, // ADD - 0U, // ADDIUPC - 0U, // ADDIUPC_MM - 0U, // ADDIUR1SP_MM - 0U, // ADDIUR2_MM - 0U, // ADDIUS5_MM - 0U, // ADDIUSP_MM - 0U, // ADDQH_PH - 0U, // ADDQH_R_PH - 0U, // ADDQH_R_W - 0U, // ADDQH_W - 0U, // ADDQ_PH - 0U, // ADDQ_S_PH - 0U, // ADDQ_S_W - 0U, // ADDSC - 0U, // ADDS_A_B - 0U, // ADDS_A_D - 0U, // ADDS_A_H - 0U, // ADDS_A_W - 0U, // ADDS_S_B - 0U, // ADDS_S_D - 0U, // ADDS_S_H - 0U, // ADDS_S_W - 0U, // ADDS_U_B - 0U, // ADDS_U_D - 0U, // ADDS_U_H - 0U, // ADDS_U_W - 0U, // ADDU16_MM - 0U, // ADDUH_QB - 0U, // ADDUH_R_QB - 0U, // ADDU_PH - 0U, // ADDU_QB - 0U, // ADDU_S_PH - 0U, // ADDU_S_QB - 0U, // ADDVI_B - 0U, // ADDVI_D - 0U, // ADDVI_H - 0U, // ADDVI_W - 0U, // ADDV_B - 0U, // ADDV_D - 0U, // ADDV_H - 0U, // ADDV_W - 0U, // ADDWC - 0U, // ADD_A_B - 0U, // ADD_A_D - 0U, // ADD_A_H - 0U, // ADD_A_W - 0U, // ADD_MM - 0U, // ADDi - 0U, // ADDi_MM - 0U, // ADDiu - 0U, // ADDiu_MM - 0U, // ADDu - 0U, // ADDu_MM + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // MEMBARRIER + 0U, // JUMP_TABLE_DEBUG_INFO + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ASSERT_ALIGN + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_CONSTANT_POOL + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_CONSTANT_FOLD_BARRIER + 0U, // G_INTRINSIC_FPTRUNC_ROUND + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_ATOMICRMW_FMAX + 0U, // G_ATOMICRMW_FMIN + 0U, // G_ATOMICRMW_UINC_WRAP + 0U, // G_ATOMICRMW_UDEC_WRAP + 0U, // G_FENCE + 0U, // G_PREFETCH + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INVOKE_REGION_START + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_INTRINSIC_CONVERGENT + 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FEXP10 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FLDEXP + 0U, // G_FFREXP + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_IS_FPCLASS + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_GET_FPENV + 0U, // G_SET_FPENV + 0U, // G_RESET_FPENV + 0U, // G_GET_FPMODE + 0U, // G_SET_FPMODE + 0U, // G_RESET_FPMODE + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STACKSAVE + 0U, // G_STACKRESTORE + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_STRICT_FLDEXP + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_FMAXIMUM + 0U, // G_VECREDUCE_FMINIMUM + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ABSMacro 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKDOWN_NM 0U, // ADJCALLSTACKUP - 4U, // ALIGN - 0U, // ALUIPC - 0U, // AND - 0U, // AND16_MM - 0U, // AND64 - 0U, // ANDI16_MM - 0U, // ANDI_B - 0U, // AND_MM - 0U, // AND_V + 0U, // ADJCALLSTACKUP_NM + 0U, // ALIGN_NM 0U, // AND_V_D_PSEUDO 0U, // AND_V_H_PSEUDO 0U, // AND_V_W_PSEUDO - 1U, // ANDi - 1U, // ANDi64 - 1U, // ANDi_MM - 1U, // APPEND - 0U, // ASUB_S_B - 0U, // ASUB_S_D - 0U, // ASUB_S_H - 0U, // ASUB_S_W - 0U, // ASUB_U_B - 0U, // ASUB_U_D - 0U, // ASUB_U_H - 0U, // ASUB_U_W 0U, // ATOMIC_CMP_SWAP_I16 + 0U, // ATOMIC_CMP_SWAP_I16_POSTRA 0U, // ATOMIC_CMP_SWAP_I32 + 0U, // ATOMIC_CMP_SWAP_I32_POSTRA 0U, // ATOMIC_CMP_SWAP_I64 + 0U, // ATOMIC_CMP_SWAP_I64_POSTRA 0U, // ATOMIC_CMP_SWAP_I8 + 0U, // ATOMIC_CMP_SWAP_I8_POSTRA 0U, // ATOMIC_LOAD_ADD_I16 + 0U, // ATOMIC_LOAD_ADD_I16_POSTRA 0U, // ATOMIC_LOAD_ADD_I32 + 0U, // ATOMIC_LOAD_ADD_I32_POSTRA 0U, // ATOMIC_LOAD_ADD_I64 + 0U, // ATOMIC_LOAD_ADD_I64_POSTRA 0U, // ATOMIC_LOAD_ADD_I8 + 0U, // ATOMIC_LOAD_ADD_I8_POSTRA 0U, // ATOMIC_LOAD_AND_I16 + 0U, // ATOMIC_LOAD_AND_I16_POSTRA 0U, // ATOMIC_LOAD_AND_I32 + 0U, // ATOMIC_LOAD_AND_I32_POSTRA 0U, // ATOMIC_LOAD_AND_I64 + 0U, // ATOMIC_LOAD_AND_I64_POSTRA 0U, // ATOMIC_LOAD_AND_I8 + 0U, // ATOMIC_LOAD_AND_I8_POSTRA + 0U, // ATOMIC_LOAD_MAX_I16 + 0U, // ATOMIC_LOAD_MAX_I16_POSTRA + 0U, // ATOMIC_LOAD_MAX_I32 + 0U, // ATOMIC_LOAD_MAX_I32_POSTRA + 0U, // ATOMIC_LOAD_MAX_I64 + 0U, // ATOMIC_LOAD_MAX_I64_POSTRA + 0U, // ATOMIC_LOAD_MAX_I8 + 0U, // ATOMIC_LOAD_MAX_I8_POSTRA + 0U, // ATOMIC_LOAD_MIN_I16 + 0U, // ATOMIC_LOAD_MIN_I16_POSTRA + 0U, // ATOMIC_LOAD_MIN_I32 + 0U, // ATOMIC_LOAD_MIN_I32_POSTRA + 0U, // ATOMIC_LOAD_MIN_I64 + 0U, // ATOMIC_LOAD_MIN_I64_POSTRA + 0U, // ATOMIC_LOAD_MIN_I8 + 0U, // ATOMIC_LOAD_MIN_I8_POSTRA 0U, // ATOMIC_LOAD_NAND_I16 + 0U, // ATOMIC_LOAD_NAND_I16_POSTRA 0U, // ATOMIC_LOAD_NAND_I32 + 0U, // ATOMIC_LOAD_NAND_I32_POSTRA 0U, // ATOMIC_LOAD_NAND_I64 + 0U, // ATOMIC_LOAD_NAND_I64_POSTRA 0U, // ATOMIC_LOAD_NAND_I8 + 0U, // ATOMIC_LOAD_NAND_I8_POSTRA 0U, // ATOMIC_LOAD_OR_I16 + 0U, // ATOMIC_LOAD_OR_I16_POSTRA 0U, // ATOMIC_LOAD_OR_I32 + 0U, // ATOMIC_LOAD_OR_I32_POSTRA 0U, // ATOMIC_LOAD_OR_I64 + 0U, // ATOMIC_LOAD_OR_I64_POSTRA 0U, // ATOMIC_LOAD_OR_I8 + 0U, // ATOMIC_LOAD_OR_I8_POSTRA 0U, // ATOMIC_LOAD_SUB_I16 + 0U, // ATOMIC_LOAD_SUB_I16_POSTRA 0U, // ATOMIC_LOAD_SUB_I32 + 0U, // ATOMIC_LOAD_SUB_I32_POSTRA 0U, // ATOMIC_LOAD_SUB_I64 + 0U, // ATOMIC_LOAD_SUB_I64_POSTRA 0U, // ATOMIC_LOAD_SUB_I8 + 0U, // ATOMIC_LOAD_SUB_I8_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I16 + 0U, // ATOMIC_LOAD_UMAX_I16_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I32 + 0U, // ATOMIC_LOAD_UMAX_I32_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I64 + 0U, // ATOMIC_LOAD_UMAX_I64_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I8 + 0U, // ATOMIC_LOAD_UMAX_I8_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I16 + 0U, // ATOMIC_LOAD_UMIN_I16_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I32 + 0U, // ATOMIC_LOAD_UMIN_I32_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I64 + 0U, // ATOMIC_LOAD_UMIN_I64_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I8 + 0U, // ATOMIC_LOAD_UMIN_I8_POSTRA 0U, // ATOMIC_LOAD_XOR_I16 + 0U, // ATOMIC_LOAD_XOR_I16_POSTRA 0U, // ATOMIC_LOAD_XOR_I32 + 0U, // ATOMIC_LOAD_XOR_I32_POSTRA 0U, // ATOMIC_LOAD_XOR_I64 + 0U, // ATOMIC_LOAD_XOR_I64_POSTRA 0U, // ATOMIC_LOAD_XOR_I8 + 0U, // ATOMIC_LOAD_XOR_I8_POSTRA 0U, // ATOMIC_SWAP_I16 + 0U, // ATOMIC_SWAP_I16_POSTRA 0U, // ATOMIC_SWAP_I32 + 0U, // ATOMIC_SWAP_I32_POSTRA 0U, // ATOMIC_SWAP_I64 + 0U, // ATOMIC_SWAP_I64_POSTRA 0U, // ATOMIC_SWAP_I8 - 0U, // AUI + 0U, // ATOMIC_SWAP_I8_POSTRA + 0U, // B + 0U, // BAL_BR + 0U, // BAL_BR_MM + 4U, // BEQLImmMacro + 4U, // BGE + 4U, // BGEImmMacro + 4U, // BGEL + 4U, // BGELImmMacro + 4U, // BGEU + 4U, // BGEUImmMacro + 4U, // BGEUL + 4U, // BGEULImmMacro + 4U, // BGT + 4U, // BGTImmMacro + 4U, // BGTL + 4U, // BGTLImmMacro + 4U, // BGTU + 4U, // BGTUImmMacro + 4U, // BGTUL + 4U, // BGTULImmMacro + 4U, // BLE + 4U, // BLEImmMacro + 4U, // BLEL + 4U, // BLELImmMacro + 4U, // BLEU + 4U, // BLEUImmMacro + 4U, // BLEUL + 4U, // BLEULImmMacro + 4U, // BLT + 4U, // BLTImmMacro + 4U, // BLTL + 4U, // BLTLImmMacro + 4U, // BLTU + 4U, // BLTUImmMacro + 4U, // BLTUL + 4U, // BLTULImmMacro + 4U, // BNELImmMacro + 0U, // BPOSGE32_PSEUDO + 0U, // BSEL_D_PSEUDO + 0U, // BSEL_FD_PSEUDO + 0U, // BSEL_FW_PSEUDO + 0U, // BSEL_H_PSEUDO + 0U, // BSEL_W_PSEUDO + 0U, // B_MM + 0U, // B_MMR6_Pseudo + 0U, // B_MM_Pseudo + 4U, // BeqImm + 4U, // BneImm + 0U, // BteqzT8CmpX16 + 0U, // BteqzT8CmpiX16 + 0U, // BteqzT8SltX16 + 0U, // BteqzT8SltiX16 + 0U, // BteqzT8SltiuX16 + 0U, // BteqzT8SltuX16 + 0U, // BtnezT8CmpX16 + 0U, // BtnezT8CmpiX16 + 0U, // BtnezT8SltX16 + 0U, // BtnezT8SltiX16 + 0U, // BtnezT8SltiuX16 + 0U, // BtnezT8SltuX16 + 0U, // BuildPairF64 + 0U, // BuildPairF64_64 + 0U, // CFTC1 + 0U, // CONSTPOOL_ENTRY + 0U, // COPY_FD_PSEUDO + 0U, // COPY_FW_PSEUDO + 0U, // CTTC1 + 0U, // Constant32 + 128U, // DMULImmMacro + 128U, // DMULMacro + 128U, // DMULOMacro + 128U, // DMULOUMacro + 128U, // DROL + 128U, // DROLImm + 128U, // DROR + 128U, // DRORImm + 128U, // DSDivIMacro + 128U, // DSDivMacro + 128U, // DSRemIMacro + 128U, // DSRemMacro + 128U, // DUDivIMacro + 128U, // DUDivMacro + 128U, // DURemIMacro + 128U, // DURemMacro + 0U, // ERet + 0U, // ExtractElementF64 + 0U, // ExtractElementF64_64 + 0U, // FABS_D + 0U, // FABS_W + 0U, // FEXP2_D_1_PSEUDO + 0U, // FEXP2_W_1_PSEUDO + 0U, // FILL_FD_PSEUDO + 0U, // FILL_FW_PSEUDO + 0U, // GotPrologue16 + 0U, // INSERT_B_VIDX64_PSEUDO + 0U, // INSERT_B_VIDX_PSEUDO + 0U, // INSERT_D_VIDX64_PSEUDO + 0U, // INSERT_D_VIDX_PSEUDO + 0U, // INSERT_FD_PSEUDO + 0U, // INSERT_FD_VIDX64_PSEUDO + 0U, // INSERT_FD_VIDX_PSEUDO + 0U, // INSERT_FW_PSEUDO + 0U, // INSERT_FW_VIDX64_PSEUDO + 0U, // INSERT_FW_VIDX_PSEUDO + 0U, // INSERT_H_VIDX64_PSEUDO + 0U, // INSERT_H_VIDX_PSEUDO + 0U, // INSERT_W_VIDX64_PSEUDO + 0U, // INSERT_W_VIDX_PSEUDO + 0U, // JALR64Pseudo + 0U, // JALRCPseudo + 0U, // JALRHB64Pseudo + 0U, // JALRHBPseudo + 0U, // JALRPseudo + 0U, // JAL_MMR6 + 0U, // JalOneReg + 0U, // JalTwoReg + 0U, // LDMacro + 0U, // LDR_D + 0U, // LDR_W + 0U, // LD_F16 + 0U, // LOAD_ACC128 + 0U, // LOAD_ACC64 + 0U, // LOAD_ACC64DSP + 0U, // LOAD_CCOND_DSP + 0U, // LONG_BRANCH_ADDiu + 0U, // LONG_BRANCH_ADDiu2Op + 0U, // LONG_BRANCH_DADDiu + 0U, // LONG_BRANCH_DADDiu2Op + 0U, // LONG_BRANCH_LUi + 0U, // LONG_BRANCH_LUi2Op + 0U, // LONG_BRANCH_LUi2Op_64 + 0U, // LWM_MM + 0U, // LoadAddrImm32 + 0U, // LoadAddrImm64 + 0U, // LoadAddrReg32 + 0U, // LoadAddrReg64 + 0U, // LoadImm32 + 0U, // LoadImm64 + 0U, // LoadImmDoubleFGR + 0U, // LoadImmDoubleFGR_32 + 0U, // LoadImmDoubleGPR + 0U, // LoadImmSingleFGR + 0U, // LoadImmSingleGPR + 0U, // LoadJumpTableOffset + 0U, // LwConstant32 + 0U, // MFTACX + 0U, // MFTACX_NM + 136U, // MFTC0 + 136U, // MFTC0_NM + 0U, // MFTC1 + 0U, // MFTDSP + 0U, // MFTDSP_NM + 0U, // MFTGPR + 0U, // MFTGPR_NM + 0U, // MFTHC1 + 0U, // MFTHI + 0U, // MFTHI_NM + 0U, // MFTLO + 0U, // MFTLO_NM + 0U, // MIPSeh_return32 + 0U, // MIPSeh_return64 + 0U, // MSA_FP_EXTEND_D_PSEUDO + 0U, // MSA_FP_EXTEND_W_PSEUDO + 0U, // MSA_FP_ROUND_D_PSEUDO + 0U, // MSA_FP_ROUND_W_PSEUDO + 0U, // MTTACX + 0U, // MTTACX_NM + 0U, // MTTC0 + 0U, // MTTC0_NM + 0U, // MTTC1 + 0U, // MTTDSP + 0U, // MTTDSP_NM + 0U, // MTTGPR + 0U, // MTTGPR_NM + 0U, // MTTHC1 + 0U, // MTTHI + 0U, // MTTHI_NM + 0U, // MTTLO + 0U, // MTTLO_NM + 128U, // MULImmMacro + 128U, // MULOMacro + 128U, // MULOUMacro + 0U, // MUSTTAILCALLREG_NM + 0U, // MUSTTAILCALL_NM + 0U, // MultRxRy16 + 0U, // MultRxRyRz16 + 0U, // MultuRxRy16 + 0U, // MultuRxRyRz16 + 0U, // NOP + 128U, // NORImm + 128U, // NORImm64 + 0U, // NOR_V_D_PSEUDO + 0U, // NOR_V_H_PSEUDO + 0U, // NOR_V_W_PSEUDO + 0U, // OR_V_D_PSEUDO + 0U, // OR_V_H_PSEUDO + 0U, // OR_V_W_PSEUDO + 12U, // PseudoADDIU_NM + 16U, // PseudoANDI_NM + 0U, // PseudoCMPU_EQ_QB + 0U, // PseudoCMPU_LE_QB + 0U, // PseudoCMPU_LT_QB + 0U, // PseudoCMP_EQ_PH + 0U, // PseudoCMP_LE_PH + 0U, // PseudoCMP_LT_PH + 0U, // PseudoCVT_D32_W + 0U, // PseudoCVT_D64_L + 0U, // PseudoCVT_D64_W + 0U, // PseudoCVT_S_L + 0U, // PseudoCVT_S_W + 0U, // PseudoDMULT + 0U, // PseudoDMULTu + 0U, // PseudoDSDIV + 0U, // PseudoDUDIV + 0U, // PseudoD_SELECT_I + 0U, // PseudoD_SELECT_I64 + 0U, // PseudoIndirectBranch + 0U, // PseudoIndirectBranch64 + 0U, // PseudoIndirectBranch64R6 + 0U, // PseudoIndirectBranchNM + 0U, // PseudoIndirectBranchR6 + 0U, // PseudoIndirectBranch_MM + 0U, // PseudoIndirectBranch_MMR6 + 0U, // PseudoIndirectHazardBranch + 0U, // PseudoIndirectHazardBranch64 + 0U, // PseudoIndrectHazardBranch64R6 + 0U, // PseudoIndrectHazardBranchR6 + 0U, // PseudoLA_NM + 0U, // PseudoLI_NM + 0U, // PseudoMADD + 0U, // PseudoMADDU + 0U, // PseudoMADDU_MM + 0U, // PseudoMADD_MM + 0U, // PseudoMFHI + 0U, // PseudoMFHI64 + 0U, // PseudoMFHI_MM + 0U, // PseudoMFLO + 0U, // PseudoMFLO64 + 0U, // PseudoMFLO_MM + 0U, // PseudoMSUB + 0U, // PseudoMSUBU + 0U, // PseudoMSUBU_MM + 0U, // PseudoMSUB_MM + 0U, // PseudoMTLOHI + 0U, // PseudoMTLOHI64 + 0U, // PseudoMTLOHI_DSP + 0U, // PseudoMTLOHI_MM + 0U, // PseudoMULT + 0U, // PseudoMULT_MM + 0U, // PseudoMULTu + 0U, // PseudoMULTu_MM + 0U, // PseudoPICK_PH + 0U, // PseudoPICK_QB + 0U, // PseudoReturn + 0U, // PseudoReturn64 + 0U, // PseudoReturnNM + 0U, // PseudoSDIV + 0U, // PseudoSELECTFP_F_D32 + 0U, // PseudoSELECTFP_F_D64 + 0U, // PseudoSELECTFP_F_I + 0U, // PseudoSELECTFP_F_I64 + 0U, // PseudoSELECTFP_F_S + 0U, // PseudoSELECTFP_T_D32 + 0U, // PseudoSELECTFP_T_D64 + 0U, // PseudoSELECTFP_T_I + 0U, // PseudoSELECTFP_T_I64 + 0U, // PseudoSELECTFP_T_S + 0U, // PseudoSELECT_D32 + 0U, // PseudoSELECT_D64 + 0U, // PseudoSELECT_I + 0U, // PseudoSELECT_I64 + 0U, // PseudoSELECT_S + 128U, // PseudoSUBU_NM + 128U, // PseudoTRUNC_W_D + 128U, // PseudoTRUNC_W_D32 + 128U, // PseudoTRUNC_W_S + 0U, // PseudoUDIV + 128U, // ROL + 128U, // ROLImm + 128U, // ROR + 128U, // RORImm + 0U, // RetRA + 0U, // RetRA16 + 0U, // SDC1_M1 + 0U, // SDIV_MM_Pseudo + 0U, // SDMacro + 128U, // SDivIMacro + 128U, // SDivMacro + 128U, // SEQIMacro + 128U, // SEQMacro + 128U, // SGE + 128U, // SGEImm + 128U, // SGEImm64 + 128U, // SGEU + 128U, // SGEUImm + 128U, // SGEUImm64 + 128U, // SGTImm + 128U, // SGTImm64 + 128U, // SGTUImm + 128U, // SGTUImm64 + 128U, // SLE + 128U, // SLEImm + 128U, // SLEImm64 + 128U, // SLEU + 128U, // SLEUImm + 128U, // SLEUImm64 + 128U, // SLTImm64 + 128U, // SLTUImm64 + 128U, // SNEIMacro + 128U, // SNEMacro + 0U, // SNZ_B_PSEUDO + 0U, // SNZ_D_PSEUDO + 0U, // SNZ_H_PSEUDO + 0U, // SNZ_V_PSEUDO + 0U, // SNZ_W_PSEUDO + 128U, // SRemIMacro + 128U, // SRemMacro + 0U, // STORE_ACC128 + 0U, // STORE_ACC64 + 0U, // STORE_ACC64DSP + 0U, // STORE_CCOND_DSP + 0U, // STR_D + 0U, // STR_W + 0U, // ST_F16 + 0U, // SWM_MM + 0U, // SZ_B_PSEUDO + 0U, // SZ_D_PSEUDO + 0U, // SZ_H_PSEUDO + 0U, // SZ_V_PSEUDO + 0U, // SZ_W_PSEUDO + 0U, // SaaAddr + 0U, // SaadAddr + 0U, // SelBeqZ + 0U, // SelBneZ + 0U, // SelTBteqZCmp + 0U, // SelTBteqZCmpi + 0U, // SelTBteqZSlt + 0U, // SelTBteqZSlti + 0U, // SelTBteqZSltiu + 0U, // SelTBteqZSltu + 0U, // SelTBtneZCmp + 0U, // SelTBtneZCmpi + 0U, // SelTBtneZSlt + 0U, // SelTBtneZSlti + 0U, // SelTBtneZSltiu + 0U, // SelTBtneZSltu + 0U, // SltCCRxRy16 + 0U, // SltiCCRxImmX16 + 0U, // SltiuCCRxImmX16 + 0U, // SltuCCRxRy16 + 0U, // SltuRxRyRz16 + 0U, // TAILCALL + 0U, // TAILCALL64R6REG + 0U, // TAILCALLHB64R6REG + 0U, // TAILCALLHBR6REG + 0U, // TAILCALLR6REG + 0U, // TAILCALLREG + 0U, // TAILCALLREG64 + 0U, // TAILCALLREGHB + 0U, // TAILCALLREGHB64 + 0U, // TAILCALLREG_MM + 0U, // TAILCALLREG_MMR6 + 0U, // TAILCALLREG_NM + 0U, // TAILCALL_MM + 0U, // TAILCALL_MMR6 + 0U, // TAILCALL_NM + 0U, // TRAP + 0U, // TRAP_MM + 0U, // UDIV_MM_Pseudo + 128U, // UDivIMacro + 128U, // UDivMacro + 128U, // URemIMacro + 128U, // URemMacro + 0U, // Ulh + 0U, // Ulhu + 0U, // Ulw + 0U, // Ush + 0U, // Usw + 0U, // XOR_V_D_PSEUDO + 0U, // XOR_V_H_PSEUDO + 0U, // XOR_V_W_PSEUDO + 0U, // ABSQ_S_PH + 0U, // ABSQ_S_PH_MM + 0U, // ABSQ_S_QB + 0U, // ABSQ_S_QB_MMR2 + 0U, // ABSQ_S_W + 0U, // ABSQ_S_W_MM + 128U, // ADD + 12U, // ADDIU48_NM + 128U, // ADDIUGP48_NM + 128U, // ADDIUGPB_NM + 128U, // ADDIUGPW_NM + 128U, // ADDIUNEG_NM + 0U, // ADDIUPC + 0U, // ADDIUPC_MM + 0U, // ADDIUPC_MMR6 + 0U, // ADDIUR1SP_MM + 20U, // ADDIUR1SP_NM + 128U, // ADDIUR2_MM + 152U, // ADDIUR2_NM + 128U, // ADDIURS5_NM + 0U, // ADDIUS5_MM + 0U, // ADDIUSP_MM + 128U, // ADDIU_MMR6 + 16U, // ADDIU_NM + 128U, // ADDQH_PH + 128U, // ADDQH_PH_MMR2 + 128U, // ADDQH_R_PH + 128U, // ADDQH_R_PH_MMR2 + 128U, // ADDQH_R_W + 128U, // ADDQH_R_W_MMR2 + 128U, // ADDQH_W + 128U, // ADDQH_W_MMR2 + 128U, // ADDQ_PH + 128U, // ADDQ_PH_MM + 128U, // ADDQ_S_PH + 128U, // ADDQ_S_PH_MM + 128U, // ADDQ_S_W + 128U, // ADDQ_S_W_MM + 128U, // ADDR_PS64 + 128U, // ADDSC + 128U, // ADDSC_MM + 128U, // ADDS_A_B + 128U, // ADDS_A_D + 128U, // ADDS_A_H + 128U, // ADDS_A_W + 128U, // ADDS_S_B + 128U, // ADDS_S_D + 128U, // ADDS_S_H + 128U, // ADDS_S_W + 128U, // ADDS_U_B + 128U, // ADDS_U_D + 128U, // ADDS_U_H + 128U, // ADDS_U_W + 128U, // ADDU16_MM + 128U, // ADDU16_MMR6 + 128U, // ADDUH_QB + 128U, // ADDUH_QB_MMR2 + 128U, // ADDUH_R_QB + 128U, // ADDUH_R_QB_MMR2 + 128U, // ADDU_MMR6 + 128U, // ADDU_PH + 128U, // ADDU_PH_MMR2 + 128U, // ADDU_QB + 128U, // ADDU_QB_MM + 128U, // ADDU_S_PH + 128U, // ADDU_S_PH_MMR2 + 128U, // ADDU_S_QB + 128U, // ADDU_S_QB_MM + 152U, // ADDVI_B + 152U, // ADDVI_D + 152U, // ADDVI_H + 152U, // ADDVI_W + 128U, // ADDV_B + 128U, // ADDV_D + 128U, // ADDV_H + 128U, // ADDV_W + 128U, // ADDWC + 128U, // ADDWC_MM + 128U, // ADD_A_B + 128U, // ADD_A_D + 128U, // ADD_A_H + 128U, // ADD_A_W + 128U, // ADD_MM + 128U, // ADD_MMR6 + 128U, // ADD_NM + 128U, // ADDi + 128U, // ADDi_MM + 128U, // ADDiu + 128U, // ADDiu_MM + 128U, // ADDu + 128U, // ADDu16_NM + 128U, // ADDu4x4_NM + 128U, // ADDu_MM + 128U, // ADDu_NM + 1024U, // ALIGN + 1024U, // ALIGN_MMR6 + 0U, // ALUIPC + 0U, // ALUIPC_MMR6 + 0U, // ALUIPC_NM + 128U, // AND + 0U, // AND16_MM + 0U, // AND16_MMR6 + 128U, // AND16_NM + 128U, // AND64 + 128U, // ANDI16_MM + 128U, // ANDI16_MMR6 + 16U, // ANDI16_NM + 20U, // ANDI_B + 16U, // ANDI_MMR6 + 128U, // ANDI_NM + 128U, // AND_MM + 128U, // AND_MMR6 + 128U, // AND_NM + 128U, // AND_V + 16U, // ANDi + 16U, // ANDi64 + 16U, // ANDi_MM + 152U, // APPEND + 152U, // APPEND_MMR2 + 128U, // ASUB_S_B + 128U, // ASUB_S_D + 128U, // ASUB_S_H + 128U, // ASUB_S_W + 128U, // ASUB_U_B + 128U, // ASUB_U_D + 128U, // ASUB_U_H + 128U, // ASUB_U_W + 16U, // AUI 0U, // AUIPC - 0U, // AVER_S_B - 0U, // AVER_S_D - 0U, // AVER_S_H - 0U, // AVER_S_W - 0U, // AVER_U_B - 0U, // AVER_U_D - 0U, // AVER_U_H - 0U, // AVER_U_W - 0U, // AVE_S_B - 0U, // AVE_S_D - 0U, // AVE_S_H - 0U, // AVE_S_W - 0U, // AVE_U_B - 0U, // AVE_U_D - 0U, // AVE_U_H - 0U, // AVE_U_W + 0U, // AUIPC_MMR6 + 16U, // AUI_MMR6 + 128U, // AVER_S_B + 128U, // AVER_S_D + 128U, // AVER_S_H + 128U, // AVER_S_W + 128U, // AVER_U_B + 128U, // AVER_U_D + 128U, // AVER_U_H + 128U, // AVER_U_W + 128U, // AVE_S_B + 128U, // AVE_S_D + 128U, // AVE_S_H + 128U, // AVE_S_W + 128U, // AVE_U_B + 128U, // AVE_U_D + 128U, // AVE_U_H + 128U, // AVE_U_W 0U, // AddiuRxImmX16 0U, // AddiuRxPcImmX16 - 0U, // AddiuRxRxImm16 + 1U, // AddiuRxRxImm16 0U, // AddiuRxRxImmX16 0U, // AddiuRxRyOffMemX16 0U, // AddiuSpImm16 0U, // AddiuSpImmX16 - 0U, // AdduRxRyRz16 + 128U, // AdduRxRyRz16 0U, // AndRxRxRy16 - 0U, // B 0U, // B16_MM - 0U, // BADDu + 128U, // BADDu 0U, // BAL 0U, // BALC - 1U, // BALIGN - 0U, // BAL_BR + 0U, // BALC16_NM + 0U, // BALC_MMR6 + 0U, // BALC_NM + 156U, // BALIGN + 156U, // BALIGN_MMR2 + 0U, // BALRSC_NM + 4U, // BBEQZC_NM 0U, // BBIT0 0U, // BBIT032 0U, // BBIT1 0U, // BBIT132 + 4U, // BBNEZC_NM 0U, // BC - 0U, // BC0F - 0U, // BC0FL - 0U, // BC0T - 0U, // BC0TL + 0U, // BC16_MMR6 + 0U, // BC16_NM 0U, // BC1EQZ + 0U, // BC1EQZC_MMR6 0U, // BC1F 0U, // BC1FL 0U, // BC1F_MM 0U, // BC1NEZ + 0U, // BC1NEZC_MMR6 0U, // BC1T 0U, // BC1TL 0U, // BC1T_MM 0U, // BC2EQZ - 0U, // BC2F - 0U, // BC2FL + 0U, // BC2EQZC_MMR6 0U, // BC2NEZ - 0U, // BC2T - 0U, // BC2TL - 0U, // BC3F - 0U, // BC3FL - 0U, // BC3T - 0U, // BC3TL - 0U, // BCLRI_B - 0U, // BCLRI_D - 0U, // BCLRI_H - 0U, // BCLRI_W - 0U, // BCLR_B - 0U, // BCLR_D - 0U, // BCLR_H - 0U, // BCLR_W - 0U, // BEQ - 0U, // BEQ64 - 0U, // BEQC - 0U, // BEQL + 0U, // BC2NEZC_MMR6 + 136U, // BCLRI_B + 160U, // BCLRI_D + 164U, // BCLRI_H + 152U, // BCLRI_W + 128U, // BCLR_B + 128U, // BCLR_D + 128U, // BCLR_H + 128U, // BCLR_W + 0U, // BC_MMR6 + 0U, // BC_NM + 4U, // BEQ + 4U, // BEQ64 + 4U, // BEQC + 4U, // BEQC16_NM + 4U, // BEQC64 + 4U, // BEQC_MMR6 + 4U, // BEQC_NM + 4U, // BEQCzero_NM + 4U, // BEQIC_NM + 4U, // BEQL 0U, // BEQZ16_MM 0U, // BEQZALC + 0U, // BEQZALC_MMR6 0U, // BEQZC + 0U, // BEQZC16_MMR6 + 0U, // BEQZC16_NM + 0U, // BEQZC64 0U, // BEQZC_MM - 0U, // BEQ_MM - 0U, // BGEC - 0U, // BGEUC + 0U, // BEQZC_MMR6 + 0U, // BEQZC_NM + 4U, // BEQ_MM + 4U, // BGEC + 4U, // BGEC64 + 4U, // BGEC_MMR6 + 4U, // BGEC_NM + 4U, // BGEIC_NM + 4U, // BGEIUC_NM + 4U, // BGEUC + 4U, // BGEUC64 + 4U, // BGEUC_MMR6 + 4U, // BGEUC_NM 0U, // BGEZ 0U, // BGEZ64 0U, // BGEZAL 0U, // BGEZALC + 0U, // BGEZALC_MMR6 0U, // BGEZALL 0U, // BGEZALS_MM 0U, // BGEZAL_MM 0U, // BGEZC + 0U, // BGEZC64 + 0U, // BGEZC_MMR6 0U, // BGEZL 0U, // BGEZ_MM 0U, // BGTZ 0U, // BGTZ64 0U, // BGTZALC + 0U, // BGTZALC_MMR6 0U, // BGTZC + 0U, // BGTZC64 + 0U, // BGTZC_MMR6 0U, // BGTZL 0U, // BGTZ_MM - 1U, // BINSLI_B - 1U, // BINSLI_D - 1U, // BINSLI_H - 1U, // BINSLI_W - 2U, // BINSL_B - 2U, // BINSL_D - 2U, // BINSL_H - 2U, // BINSL_W - 1U, // BINSRI_B - 1U, // BINSRI_D - 1U, // BINSRI_H - 1U, // BINSRI_W - 2U, // BINSR_B - 2U, // BINSR_D - 2U, // BINSR_H - 2U, // BINSR_W + 168U, // BINSLI_B + 44U, // BINSLI_D + 176U, // BINSLI_H + 52U, // BINSLI_W + 184U, // BINSL_B + 184U, // BINSL_D + 184U, // BINSL_H + 184U, // BINSL_W + 168U, // BINSRI_B + 44U, // BINSRI_D + 176U, // BINSRI_H + 52U, // BINSRI_W + 184U, // BINSR_B + 184U, // BINSR_D + 184U, // BINSR_H + 184U, // BINSR_W 0U, // BITREV + 0U, // BITREVW_NM + 0U, // BITREV_MM 0U, // BITSWAP + 0U, // BITSWAP_MMR6 0U, // BLEZ 0U, // BLEZ64 0U, // BLEZALC + 0U, // BLEZALC_MMR6 0U, // BLEZC + 0U, // BLEZC64 + 0U, // BLEZC_MMR6 0U, // BLEZL 0U, // BLEZ_MM - 0U, // BLTC - 0U, // BLTUC + 4U, // BLTC + 4U, // BLTC64 + 4U, // BLTC_MMR6 + 4U, // BLTC_NM + 4U, // BLTIC_NM + 4U, // BLTIUC_NM + 4U, // BLTUC + 4U, // BLTUC64 + 4U, // BLTUC_MMR6 + 4U, // BLTUC_NM 0U, // BLTZ 0U, // BLTZ64 0U, // BLTZAL 0U, // BLTZALC + 0U, // BLTZALC_MMR6 0U, // BLTZALL 0U, // BLTZALS_MM 0U, // BLTZAL_MM 0U, // BLTZC + 0U, // BLTZC64 + 0U, // BLTZC_MMR6 0U, // BLTZL 0U, // BLTZ_MM - 1U, // BMNZI_B - 2U, // BMNZ_V - 1U, // BMZI_B - 2U, // BMZ_V - 0U, // BNE - 0U, // BNE64 - 0U, // BNEC - 0U, // BNEGI_B - 0U, // BNEGI_D - 0U, // BNEGI_H - 0U, // BNEGI_W - 0U, // BNEG_B - 0U, // BNEG_D - 0U, // BNEG_H - 0U, // BNEG_W - 0U, // BNEL + 60U, // BMNZI_B + 184U, // BMNZ_V + 60U, // BMZI_B + 184U, // BMZ_V + 4U, // BNE + 4U, // BNE64 + 4U, // BNEC + 4U, // BNEC16_NM + 4U, // BNEC64 + 4U, // BNEC_MMR6 + 4U, // BNEC_NM + 4U, // BNECzero_NM + 136U, // BNEGI_B + 160U, // BNEGI_D + 164U, // BNEGI_H + 152U, // BNEGI_W + 128U, // BNEG_B + 128U, // BNEG_D + 128U, // BNEG_H + 128U, // BNEG_W + 4U, // BNEIC_NM + 4U, // BNEL 0U, // BNEZ16_MM 0U, // BNEZALC + 0U, // BNEZALC_MMR6 0U, // BNEZC + 0U, // BNEZC16_MMR6 + 0U, // BNEZC16_NM + 0U, // BNEZC64 0U, // BNEZC_MM - 0U, // BNE_MM - 0U, // BNVC + 0U, // BNEZC_MMR6 + 0U, // BNEZC_NM + 4U, // BNE_MM + 4U, // BNVC + 4U, // BNVC_MMR6 0U, // BNZ_B 0U, // BNZ_D 0U, // BNZ_H 0U, // BNZ_V 0U, // BNZ_W - 0U, // BOVC + 4U, // BOVC + 4U, // BOVC_MMR6 0U, // BPOSGE32 - 0U, // BPOSGE32_PSEUDO + 0U, // BPOSGE32C_MMR3 + 0U, // BPOSGE32_MM 0U, // BREAK 0U, // BREAK16_MM + 0U, // BREAK16_MMR6 + 0U, // BREAK16_NM 0U, // BREAK_MM - 1U, // BSELI_B - 0U, // BSEL_D_PSEUDO - 0U, // BSEL_FD_PSEUDO - 0U, // BSEL_FW_PSEUDO - 0U, // BSEL_H_PSEUDO - 2U, // BSEL_V - 0U, // BSEL_W_PSEUDO - 0U, // BSETI_B - 0U, // BSETI_D - 0U, // BSETI_H - 0U, // BSETI_W - 0U, // BSET_B - 0U, // BSET_D - 0U, // BSET_H - 0U, // BSET_W + 0U, // BREAK_MMR6 + 0U, // BREAK_NM + 0U, // BRSC_NM + 60U, // BSELI_B + 184U, // BSEL_V + 136U, // BSETI_B + 160U, // BSETI_D + 164U, // BSETI_H + 152U, // BSETI_W + 128U, // BSET_B + 128U, // BSET_D + 128U, // BSET_H + 128U, // BSET_W + 0U, // BYTEREVW_NM 0U, // BZ_B 0U, // BZ_D 0U, // BZ_H 0U, // BZ_V 0U, // BZ_W - 0U, // B_MM_Pseudo - 0U, // BeqzRxImm16 + 1U, // BeqzRxImm16 0U, // BeqzRxImmX16 0U, // Bimm16 0U, // BimmX16 - 0U, // BnezRxImm16 + 1U, // BnezRxImm16 0U, // BnezRxImmX16 0U, // Break16 0U, // Bteqz16 - 0U, // BteqzT8CmpX16 - 0U, // BteqzT8CmpiX16 - 0U, // BteqzT8SltX16 - 0U, // BteqzT8SltiX16 - 0U, // BteqzT8SltiuX16 - 0U, // BteqzT8SltuX16 0U, // BteqzX16 0U, // Btnez16 - 0U, // BtnezT8CmpX16 - 0U, // BtnezT8CmpiX16 - 0U, // BtnezT8SltX16 - 0U, // BtnezT8SltiX16 - 0U, // BtnezT8SltiuX16 - 0U, // BtnezT8SltuX16 0U, // BtnezX16 - 0U, // BuildPairF64 - 0U, // BuildPairF64_64 0U, // CACHE + 0U, // CACHEE + 0U, // CACHEE_MM 0U, // CACHE_MM + 0U, // CACHE_MMR6 + 0U, // CACHE_NM 0U, // CACHE_R6 0U, // CEIL_L_D64 + 0U, // CEIL_L_D_MMR6 0U, // CEIL_L_S + 0U, // CEIL_L_S_MMR6 0U, // CEIL_W_D32 0U, // CEIL_W_D64 + 0U, // CEIL_W_D_MMR6 0U, // CEIL_W_MM 0U, // CEIL_W_S 0U, // CEIL_W_S_MM - 0U, // CEQI_B - 0U, // CEQI_D - 0U, // CEQI_H - 0U, // CEQI_W - 0U, // CEQ_B - 0U, // CEQ_D - 0U, // CEQ_H - 0U, // CEQ_W + 0U, // CEIL_W_S_MMR6 + 128U, // CEQI_B + 128U, // CEQI_D + 128U, // CEQI_H + 128U, // CEQI_W + 128U, // CEQ_B + 128U, // CEQ_D + 128U, // CEQ_H + 128U, // CEQ_W 0U, // CFC1 0U, // CFC1_MM + 0U, // CFC2_MM 0U, // CFCMSA - 5U, // CINS - 5U, // CINS32 + 2072U, // CINS + 2072U, // CINS32 + 2072U, // CINS64_32 + 2072U, // CINS_i32 0U, // CLASS_D + 0U, // CLASS_D_MMR6 0U, // CLASS_S - 0U, // CLEI_S_B - 0U, // CLEI_S_D - 0U, // CLEI_S_H - 0U, // CLEI_S_W - 0U, // CLEI_U_B - 0U, // CLEI_U_D - 0U, // CLEI_U_H - 0U, // CLEI_U_W - 0U, // CLE_S_B - 0U, // CLE_S_D - 0U, // CLE_S_H - 0U, // CLE_S_W - 0U, // CLE_U_B - 0U, // CLE_U_D - 0U, // CLE_U_H - 0U, // CLE_U_W + 0U, // CLASS_S_MMR6 + 128U, // CLEI_S_B + 128U, // CLEI_S_D + 128U, // CLEI_S_H + 128U, // CLEI_S_W + 152U, // CLEI_U_B + 152U, // CLEI_U_D + 152U, // CLEI_U_H + 152U, // CLEI_U_W + 128U, // CLE_S_B + 128U, // CLE_S_D + 128U, // CLE_S_H + 128U, // CLE_S_W + 128U, // CLE_U_B + 128U, // CLE_U_D + 128U, // CLE_U_H + 128U, // CLE_U_W 0U, // CLO 0U, // CLO_MM + 0U, // CLO_MMR6 + 0U, // CLO_NM 0U, // CLO_R6 - 0U, // CLTI_S_B - 0U, // CLTI_S_D - 0U, // CLTI_S_H - 0U, // CLTI_S_W - 0U, // CLTI_U_B - 0U, // CLTI_U_D - 0U, // CLTI_U_H - 0U, // CLTI_U_W - 0U, // CLT_S_B - 0U, // CLT_S_D - 0U, // CLT_S_H - 0U, // CLT_S_W - 0U, // CLT_U_B - 0U, // CLT_U_D - 0U, // CLT_U_H - 0U, // CLT_U_W + 128U, // CLTI_S_B + 128U, // CLTI_S_D + 128U, // CLTI_S_H + 128U, // CLTI_S_W + 152U, // CLTI_U_B + 152U, // CLTI_U_D + 152U, // CLTI_U_H + 152U, // CLTI_U_W + 128U, // CLT_S_B + 128U, // CLT_S_D + 128U, // CLT_S_H + 128U, // CLT_S_W + 128U, // CLT_U_B + 128U, // CLT_U_D + 128U, // CLT_U_H + 128U, // CLT_U_W 0U, // CLZ 0U, // CLZ_MM + 0U, // CLZ_MMR6 + 0U, // CLZ_NM 0U, // CLZ_R6 - 0U, // CMPGDU_EQ_QB - 0U, // CMPGDU_LE_QB - 0U, // CMPGDU_LT_QB - 0U, // CMPGU_EQ_QB - 0U, // CMPGU_LE_QB - 0U, // CMPGU_LT_QB + 128U, // CMPGDU_EQ_QB + 128U, // CMPGDU_EQ_QB_MMR2 + 128U, // CMPGDU_LE_QB + 128U, // CMPGDU_LE_QB_MMR2 + 128U, // CMPGDU_LT_QB + 128U, // CMPGDU_LT_QB_MMR2 + 128U, // CMPGU_EQ_QB + 128U, // CMPGU_EQ_QB_MM + 128U, // CMPGU_LE_QB + 128U, // CMPGU_LE_QB_MM + 128U, // CMPGU_LT_QB + 128U, // CMPGU_LT_QB_MM 0U, // CMPU_EQ_QB + 0U, // CMPU_EQ_QB_MM 0U, // CMPU_LE_QB + 0U, // CMPU_LE_QB_MM 0U, // CMPU_LT_QB - 0U, // CMP_EQ_D + 0U, // CMPU_LT_QB_MM + 128U, // CMP_AF_D_MMR6 + 128U, // CMP_AF_S_MMR6 + 128U, // CMP_EQ_D + 128U, // CMP_EQ_D_MMR6 0U, // CMP_EQ_PH - 0U, // CMP_EQ_S - 0U, // CMP_F_D - 0U, // CMP_F_S - 0U, // CMP_LE_D + 0U, // CMP_EQ_PH_MM + 128U, // CMP_EQ_S + 128U, // CMP_EQ_S_MMR6 + 128U, // CMP_F_D + 128U, // CMP_F_S + 128U, // CMP_LE_D + 128U, // CMP_LE_D_MMR6 0U, // CMP_LE_PH - 0U, // CMP_LE_S - 0U, // CMP_LT_D + 0U, // CMP_LE_PH_MM + 128U, // CMP_LE_S + 128U, // CMP_LE_S_MMR6 + 128U, // CMP_LT_D + 128U, // CMP_LT_D_MMR6 0U, // CMP_LT_PH - 0U, // CMP_LT_S - 0U, // CMP_SAF_D - 0U, // CMP_SAF_S - 0U, // CMP_SEQ_D - 0U, // CMP_SEQ_S - 0U, // CMP_SLE_D - 0U, // CMP_SLE_S - 0U, // CMP_SLT_D - 0U, // CMP_SLT_S - 0U, // CMP_SUEQ_D - 0U, // CMP_SUEQ_S - 0U, // CMP_SULE_D - 0U, // CMP_SULE_S - 0U, // CMP_SULT_D - 0U, // CMP_SULT_S - 0U, // CMP_SUN_D - 0U, // CMP_SUN_S - 0U, // CMP_UEQ_D - 0U, // CMP_UEQ_S - 0U, // CMP_ULE_D - 0U, // CMP_ULE_S - 0U, // CMP_ULT_D - 0U, // CMP_ULT_S - 0U, // CMP_UN_D - 0U, // CMP_UN_S - 0U, // CONSTPOOL_ENTRY - 0U, // COPY_FD_PSEUDO - 0U, // COPY_FW_PSEUDO - 8U, // COPY_S_B - 8U, // COPY_S_D - 8U, // COPY_S_H - 8U, // COPY_S_W - 8U, // COPY_U_B - 8U, // COPY_U_D - 8U, // COPY_U_H - 8U, // COPY_U_W + 0U, // CMP_LT_PH_MM + 128U, // CMP_LT_S + 128U, // CMP_LT_S_MMR6 + 128U, // CMP_SAF_D + 128U, // CMP_SAF_D_MMR6 + 128U, // CMP_SAF_S + 128U, // CMP_SAF_S_MMR6 + 128U, // CMP_SEQ_D + 128U, // CMP_SEQ_D_MMR6 + 128U, // CMP_SEQ_S + 128U, // CMP_SEQ_S_MMR6 + 128U, // CMP_SLE_D + 128U, // CMP_SLE_D_MMR6 + 128U, // CMP_SLE_S + 128U, // CMP_SLE_S_MMR6 + 128U, // CMP_SLT_D + 128U, // CMP_SLT_D_MMR6 + 128U, // CMP_SLT_S + 128U, // CMP_SLT_S_MMR6 + 128U, // CMP_SUEQ_D + 128U, // CMP_SUEQ_D_MMR6 + 128U, // CMP_SUEQ_S + 128U, // CMP_SUEQ_S_MMR6 + 128U, // CMP_SULE_D + 128U, // CMP_SULE_D_MMR6 + 128U, // CMP_SULE_S + 128U, // CMP_SULE_S_MMR6 + 128U, // CMP_SULT_D + 128U, // CMP_SULT_D_MMR6 + 128U, // CMP_SULT_S + 128U, // CMP_SULT_S_MMR6 + 128U, // CMP_SUN_D + 128U, // CMP_SUN_D_MMR6 + 128U, // CMP_SUN_S + 128U, // CMP_SUN_S_MMR6 + 128U, // CMP_UEQ_D + 128U, // CMP_UEQ_D_MMR6 + 128U, // CMP_UEQ_S + 128U, // CMP_UEQ_S_MMR6 + 128U, // CMP_ULE_D + 128U, // CMP_ULE_D_MMR6 + 128U, // CMP_ULE_S + 128U, // CMP_ULE_S_MMR6 + 128U, // CMP_ULT_D + 128U, // CMP_ULT_D_MMR6 + 128U, // CMP_ULT_S + 128U, // CMP_ULT_S_MMR6 + 128U, // CMP_UN_D + 128U, // CMP_UN_D_MMR6 + 128U, // CMP_UN_S + 128U, // CMP_UN_S_MMR6 + 293U, // COPY_S_B + 321U, // COPY_S_D + 265U, // COPY_S_H + 285U, // COPY_S_W + 293U, // COPY_U_B + 265U, // COPY_U_H + 285U, // COPY_U_W + 128U, // CRC32B + 0U, // CRC32B_NM + 128U, // CRC32CB + 0U, // CRC32CB_NM + 128U, // CRC32CD + 128U, // CRC32CH + 0U, // CRC32CH_NM + 128U, // CRC32CW + 0U, // CRC32CW_NM + 128U, // CRC32D + 128U, // CRC32H + 0U, // CRC32H_NM + 128U, // CRC32W + 0U, // CRC32W_NM 0U, // CTC1 0U, // CTC1_MM + 0U, // CTC2_MM 0U, // CTCMSA 0U, // CVT_D32_S + 0U, // CVT_D32_S_MM 0U, // CVT_D32_W 0U, // CVT_D32_W_MM 0U, // CVT_D64_L 0U, // CVT_D64_S + 0U, // CVT_D64_S_MM 0U, // CVT_D64_W - 0U, // CVT_D_S_MM + 0U, // CVT_D64_W_MM + 0U, // CVT_D_L_MMR6 0U, // CVT_L_D64 0U, // CVT_L_D64_MM + 0U, // CVT_L_D_MMR6 0U, // CVT_L_S 0U, // CVT_L_S_MM + 0U, // CVT_L_S_MMR6 + 0U, // CVT_PS_PW64 + 128U, // CVT_PS_S64 + 0U, // CVT_PW_PS64 0U, // CVT_S_D32 0U, // CVT_S_D32_MM 0U, // CVT_S_D64 + 0U, // CVT_S_D64_MM 0U, // CVT_S_L + 0U, // CVT_S_L_MMR6 + 0U, // CVT_S_PL64 + 0U, // CVT_S_PU64 0U, // CVT_S_W 0U, // CVT_S_W_MM + 0U, // CVT_S_W_MMR6 0U, // CVT_W_D32 + 0U, // CVT_W_D32_MM 0U, // CVT_W_D64 - 0U, // CVT_W_MM + 0U, // CVT_W_D64_MM 0U, // CVT_W_S 0U, // CVT_W_S_MM - 0U, // C_EQ_D32 - 0U, // C_EQ_D64 - 0U, // C_EQ_S - 0U, // C_F_D32 - 0U, // C_F_D64 - 0U, // C_F_S - 0U, // C_LE_D32 - 0U, // C_LE_D64 - 0U, // C_LE_S - 0U, // C_LT_D32 - 0U, // C_LT_D64 - 0U, // C_LT_S - 0U, // C_NGE_D32 - 0U, // C_NGE_D64 - 0U, // C_NGE_S - 0U, // C_NGLE_D32 - 0U, // C_NGLE_D64 - 0U, // C_NGLE_S - 0U, // C_NGL_D32 - 0U, // C_NGL_D64 - 0U, // C_NGL_S - 0U, // C_NGT_D32 - 0U, // C_NGT_D64 - 0U, // C_NGT_S - 0U, // C_OLE_D32 - 0U, // C_OLE_D64 - 0U, // C_OLE_S - 0U, // C_OLT_D32 - 0U, // C_OLT_D64 - 0U, // C_OLT_S - 0U, // C_SEQ_D32 - 0U, // C_SEQ_D64 - 0U, // C_SEQ_S - 0U, // C_SF_D32 - 0U, // C_SF_D64 - 0U, // C_SF_S - 0U, // C_UEQ_D32 - 0U, // C_UEQ_D64 - 0U, // C_UEQ_S - 0U, // C_ULE_D32 - 0U, // C_ULE_D64 - 0U, // C_ULE_S - 0U, // C_ULT_D32 - 0U, // C_ULT_D64 - 0U, // C_ULT_S - 0U, // C_UN_D32 - 0U, // C_UN_D64 - 0U, // C_UN_S + 0U, // CVT_W_S_MMR6 + 128U, // C_EQ_D32 + 128U, // C_EQ_D32_MM + 128U, // C_EQ_D64 + 128U, // C_EQ_D64_MM + 128U, // C_EQ_S + 128U, // C_EQ_S_MM + 128U, // C_F_D32 + 128U, // C_F_D32_MM + 128U, // C_F_D64 + 128U, // C_F_D64_MM + 128U, // C_F_S + 128U, // C_F_S_MM + 128U, // C_LE_D32 + 128U, // C_LE_D32_MM + 128U, // C_LE_D64 + 128U, // C_LE_D64_MM + 128U, // C_LE_S + 128U, // C_LE_S_MM + 128U, // C_LT_D32 + 128U, // C_LT_D32_MM + 128U, // C_LT_D64 + 128U, // C_LT_D64_MM + 128U, // C_LT_S + 128U, // C_LT_S_MM + 128U, // C_NGE_D32 + 128U, // C_NGE_D32_MM + 128U, // C_NGE_D64 + 128U, // C_NGE_D64_MM + 128U, // C_NGE_S + 128U, // C_NGE_S_MM + 128U, // C_NGLE_D32 + 128U, // C_NGLE_D32_MM + 128U, // C_NGLE_D64 + 128U, // C_NGLE_D64_MM + 128U, // C_NGLE_S + 128U, // C_NGLE_S_MM + 128U, // C_NGL_D32 + 128U, // C_NGL_D32_MM + 128U, // C_NGL_D64 + 128U, // C_NGL_D64_MM + 128U, // C_NGL_S + 128U, // C_NGL_S_MM + 128U, // C_NGT_D32 + 128U, // C_NGT_D32_MM + 128U, // C_NGT_D64 + 128U, // C_NGT_D64_MM + 128U, // C_NGT_S + 128U, // C_NGT_S_MM + 128U, // C_OLE_D32 + 128U, // C_OLE_D32_MM + 128U, // C_OLE_D64 + 128U, // C_OLE_D64_MM + 128U, // C_OLE_S + 128U, // C_OLE_S_MM + 128U, // C_OLT_D32 + 128U, // C_OLT_D32_MM + 128U, // C_OLT_D64 + 128U, // C_OLT_D64_MM + 128U, // C_OLT_S + 128U, // C_OLT_S_MM + 128U, // C_SEQ_D32 + 128U, // C_SEQ_D32_MM + 128U, // C_SEQ_D64 + 128U, // C_SEQ_D64_MM + 128U, // C_SEQ_S + 128U, // C_SEQ_S_MM + 128U, // C_SF_D32 + 128U, // C_SF_D32_MM + 128U, // C_SF_D64 + 128U, // C_SF_D64_MM + 128U, // C_SF_S + 128U, // C_SF_S_MM + 128U, // C_UEQ_D32 + 128U, // C_UEQ_D32_MM + 128U, // C_UEQ_D64 + 128U, // C_UEQ_D64_MM + 128U, // C_UEQ_S + 128U, // C_UEQ_S_MM + 128U, // C_ULE_D32 + 128U, // C_ULE_D32_MM + 128U, // C_ULE_D64 + 128U, // C_ULE_D64_MM + 128U, // C_ULE_S + 128U, // C_ULE_S_MM + 128U, // C_ULT_D32 + 128U, // C_ULT_D32_MM + 128U, // C_ULT_D64 + 128U, // C_ULT_D64_MM + 128U, // C_ULT_S + 128U, // C_ULT_S_MM + 128U, // C_UN_D32 + 128U, // C_UN_D32_MM + 128U, // C_UN_D64 + 128U, // C_UN_D64_MM + 128U, // C_UN_S + 128U, // C_UN_S_MM 0U, // CmpRxRy16 - 0U, // CmpiRxImm16 + 1U, // CmpiRxImm16 0U, // CmpiRxImmX16 - 0U, // Constant32 - 0U, // DADD - 0U, // DADDi - 0U, // DADDiu - 0U, // DADDu - 0U, // DAHI - 4U, // DALIGN - 0U, // DATI - 0U, // DAUI + 128U, // DADD + 128U, // DADDi + 128U, // DADDiu + 128U, // DADDu + 16U, // DAHI + 3072U, // DALIGN + 16U, // DATI + 16U, // DAUI 0U, // DBITSWAP 0U, // DCLO 0U, // DCLO_R6 0U, // DCLZ 0U, // DCLZ_R6 - 0U, // DDIV - 0U, // DDIVU + 128U, // DDIV + 128U, // DDIVU 0U, // DERET 0U, // DERET_MM - 21U, // DEXT - 21U, // DEXTM - 21U, // DEXTU + 0U, // DERET_MMR6 + 0U, // DERET_NM + 4128U, // DEXT + 5152U, // DEXT64_32 + 6168U, // DEXTM + 452U, // DEXTU 0U, // DI - 21U, // DINS - 21U, // DINSM - 21U, // DINSU - 0U, // DIV - 0U, // DIVU - 0U, // DIV_S_B - 0U, // DIV_S_D - 0U, // DIV_S_H - 0U, // DIV_S_W - 0U, // DIV_U_B - 0U, // DIV_U_D - 0U, // DIV_U_H - 0U, // DIV_U_W + 7200U, // DINS + 8216U, // DINSM + 580U, // DINSU + 128U, // DIV + 128U, // DIVU + 128U, // DIVU_MMR6 + 128U, // DIVU_NM + 128U, // DIV_MMR6 + 128U, // DIV_NM + 128U, // DIV_S_B + 128U, // DIV_S_D + 128U, // DIV_S_H + 128U, // DIV_S_W + 128U, // DIV_U_B + 128U, // DIV_U_D + 128U, // DIV_U_H + 128U, // DIV_U_W 0U, // DI_MM - 4U, // DLSA - 4U, // DLSA_R6 - 1U, // DMFC0 + 0U, // DI_MMR6 + 0U, // DI_NM + 9216U, // DLSA + 9216U, // DLSA_R6 + 136U, // DMFC0 0U, // DMFC1 - 1U, // DMFC2 - 0U, // DMOD - 0U, // DMODU - 1U, // DMTC0 + 136U, // DMFC2 + 0U, // DMFC2_OCTEON + 136U, // DMFGC0 + 128U, // DMOD + 128U, // DMODU + 0U, // DMT + 0U, // DMTC0 0U, // DMTC1 - 1U, // DMTC2 - 0U, // DMUH - 0U, // DMUHU - 0U, // DMUL + 0U, // DMTC2 + 0U, // DMTC2_OCTEON + 0U, // DMTGC0 + 0U, // DMT_NM + 128U, // DMUH + 128U, // DMUHU + 128U, // DMUL 0U, // DMULT 0U, // DMULTu - 0U, // DMULU - 0U, // DMUL_R6 - 0U, // DOTP_S_D - 0U, // DOTP_S_H - 0U, // DOTP_S_W - 0U, // DOTP_U_D - 0U, // DOTP_U_H - 0U, // DOTP_U_W - 2U, // DPADD_S_D - 2U, // DPADD_S_H - 2U, // DPADD_S_W - 2U, // DPADD_U_D - 2U, // DPADD_U_H - 2U, // DPADD_U_W - 0U, // DPAQX_SA_W_PH - 0U, // DPAQX_S_W_PH - 0U, // DPAQ_SA_L_W - 0U, // DPAQ_S_W_PH - 0U, // DPAU_H_QBL - 0U, // DPAU_H_QBR - 0U, // DPAX_W_PH - 0U, // DPA_W_PH + 128U, // DMULU + 128U, // DMUL_R6 + 128U, // DOTP_S_D + 128U, // DOTP_S_H + 128U, // DOTP_S_W + 128U, // DOTP_U_D + 128U, // DOTP_U_H + 128U, // DOTP_U_W + 184U, // DPADD_S_D + 184U, // DPADD_S_H + 184U, // DPADD_S_W + 184U, // DPADD_U_D + 184U, // DPADD_U_H + 184U, // DPADD_U_W + 128U, // DPAQX_SA_W_PH + 128U, // DPAQX_SA_W_PH_MMR2 + 128U, // DPAQX_S_W_PH + 128U, // DPAQX_S_W_PH_MMR2 + 128U, // DPAQ_SA_L_W + 128U, // DPAQ_SA_L_W_MM + 128U, // DPAQ_S_W_PH + 128U, // DPAQ_S_W_PH_MM + 128U, // DPAU_H_QBL + 128U, // DPAU_H_QBL_MM + 128U, // DPAU_H_QBR + 128U, // DPAU_H_QBR_MM + 128U, // DPAX_W_PH + 128U, // DPAX_W_PH_MMR2 + 128U, // DPA_W_PH + 128U, // DPA_W_PH_MMR2 0U, // DPOP - 0U, // DPSQX_SA_W_PH - 0U, // DPSQX_S_W_PH - 0U, // DPSQ_SA_L_W - 0U, // DPSQ_S_W_PH - 2U, // DPSUB_S_D - 2U, // DPSUB_S_H - 2U, // DPSUB_S_W - 2U, // DPSUB_U_D - 2U, // DPSUB_U_H - 2U, // DPSUB_U_W - 0U, // DPSU_H_QBL - 0U, // DPSU_H_QBR - 0U, // DPSX_W_PH - 0U, // DPS_W_PH - 1U, // DROTR - 1U, // DROTR32 - 0U, // DROTRV + 128U, // DPSQX_SA_W_PH + 128U, // DPSQX_SA_W_PH_MMR2 + 128U, // DPSQX_S_W_PH + 128U, // DPSQX_S_W_PH_MMR2 + 128U, // DPSQ_SA_L_W + 128U, // DPSQ_SA_L_W_MM + 128U, // DPSQ_S_W_PH + 128U, // DPSQ_S_W_PH_MM + 184U, // DPSUB_S_D + 184U, // DPSUB_S_H + 184U, // DPSUB_S_W + 184U, // DPSUB_U_D + 184U, // DPSUB_U_H + 184U, // DPSUB_U_W + 128U, // DPSU_H_QBL + 128U, // DPSU_H_QBL_MM + 128U, // DPSU_H_QBR + 128U, // DPSU_H_QBR_MM + 128U, // DPSX_W_PH + 128U, // DPSX_W_PH_MMR2 + 128U, // DPS_W_PH + 128U, // DPS_W_PH_MMR2 + 160U, // DROTR + 152U, // DROTR32 + 128U, // DROTRV 0U, // DSBH 0U, // DSDIV 0U, // DSHD - 1U, // DSLL - 1U, // DSLL32 - 0U, // DSLL64_32 - 0U, // DSLLV - 1U, // DSRA - 1U, // DSRA32 - 0U, // DSRAV - 1U, // DSRL - 1U, // DSRL32 - 0U, // DSRLV - 0U, // DSUB - 0U, // DSUBu + 160U, // DSLL + 152U, // DSLL32 + 1U, // DSLL64_32 + 128U, // DSLLV + 160U, // DSRA + 152U, // DSRA32 + 128U, // DSRAV + 160U, // DSRL + 152U, // DSRL32 + 128U, // DSRLV + 128U, // DSUB + 128U, // DSUBu 0U, // DUDIV + 0U, // DVP + 0U, // DVPE + 0U, // DVPE_NM + 0U, // DVP_MMR6 0U, // DivRxRy16 0U, // DivuRxRy16 0U, // EHB 0U, // EHB_MM + 0U, // EHB_MMR6 + 0U, // EHB_NM 0U, // EI 0U, // EI_MM + 0U, // EI_MMR6 + 0U, // EI_NM + 0U, // EMT + 0U, // EMT_NM 0U, // ERET + 0U, // ERETNC + 0U, // ERETNC_MMR6 + 0U, // ERETNC_NM 0U, // ERET_MM - 21U, // EXT - 1U, // EXTP - 1U, // EXTPDP - 0U, // EXTPDPV - 0U, // EXTPV - 0U, // EXTRV_RS_W - 0U, // EXTRV_R_W - 0U, // EXTRV_S_H - 0U, // EXTRV_W - 1U, // EXTR_RS_W - 1U, // EXTR_R_W - 1U, // EXTR_S_H - 1U, // EXTR_W - 5U, // EXTS - 5U, // EXTS32 - 21U, // EXT_MM - 0U, // ExtractElementF64 - 0U, // ExtractElementF64_64 - 0U, // FABS_D + 0U, // ERET_MMR6 + 0U, // ERET_NM + 0U, // EVP + 0U, // EVPE + 0U, // EVPE_NM + 0U, // EVP_MMR6 + 5144U, // EXT + 152U, // EXTP + 152U, // EXTPDP + 128U, // EXTPDPV + 128U, // EXTPDPV_MM + 152U, // EXTPDP_MM + 128U, // EXTPV + 128U, // EXTPV_MM + 152U, // EXTP_MM + 128U, // EXTRV_RS_W + 128U, // EXTRV_RS_W_MM + 128U, // EXTRV_R_W + 128U, // EXTRV_R_W_MM + 128U, // EXTRV_S_H + 128U, // EXTRV_S_H_MM + 128U, // EXTRV_W + 128U, // EXTRV_W_MM + 152U, // EXTR_RS_W + 152U, // EXTR_RS_W_MM + 152U, // EXTR_R_W + 152U, // EXTR_R_W_MM + 152U, // EXTR_S_H + 152U, // EXTR_S_H_MM + 152U, // EXTR_W + 152U, // EXTR_W_MM + 2072U, // EXTS + 2072U, // EXTS32 + 2048U, // EXTW_NM + 5144U, // EXT_MM + 5144U, // EXT_MMR6 + 5144U, // EXT_NM 0U, // FABS_D32 + 0U, // FABS_D32_MM 0U, // FABS_D64 - 0U, // FABS_MM + 0U, // FABS_D64_MM 0U, // FABS_S 0U, // FABS_S_MM - 0U, // FABS_W - 0U, // FADD_D - 0U, // FADD_D32 - 0U, // FADD_D64 - 0U, // FADD_MM - 0U, // FADD_S - 0U, // FADD_S_MM - 0U, // FADD_W - 0U, // FCAF_D - 0U, // FCAF_W - 0U, // FCEQ_D - 0U, // FCEQ_W + 128U, // FADD_D + 128U, // FADD_D32 + 128U, // FADD_D32_MM + 128U, // FADD_D64 + 128U, // FADD_D64_MM + 128U, // FADD_PS64 + 128U, // FADD_S + 128U, // FADD_S_MM + 72U, // FADD_S_MMR6 + 128U, // FADD_W + 128U, // FCAF_D + 128U, // FCAF_W + 128U, // FCEQ_D + 128U, // FCEQ_W 0U, // FCLASS_D 0U, // FCLASS_W - 0U, // FCLE_D - 0U, // FCLE_W - 0U, // FCLT_D - 0U, // FCLT_W + 128U, // FCLE_D + 128U, // FCLE_W + 128U, // FCLT_D + 128U, // FCLT_W 0U, // FCMP_D32 0U, // FCMP_D32_MM 0U, // FCMP_D64 0U, // FCMP_S32 0U, // FCMP_S32_MM - 0U, // FCNE_D - 0U, // FCNE_W - 0U, // FCOR_D - 0U, // FCOR_W - 0U, // FCUEQ_D - 0U, // FCUEQ_W - 0U, // FCULE_D - 0U, // FCULE_W - 0U, // FCULT_D - 0U, // FCULT_W - 0U, // FCUNE_D - 0U, // FCUNE_W - 0U, // FCUN_D - 0U, // FCUN_W - 0U, // FDIV_D - 0U, // FDIV_D32 - 0U, // FDIV_D64 - 0U, // FDIV_MM - 0U, // FDIV_S - 0U, // FDIV_S_MM - 0U, // FDIV_W - 0U, // FEXDO_H - 0U, // FEXDO_W - 0U, // FEXP2_D - 0U, // FEXP2_D_1_PSEUDO - 0U, // FEXP2_W - 0U, // FEXP2_W_1_PSEUDO + 128U, // FCNE_D + 128U, // FCNE_W + 128U, // FCOR_D + 128U, // FCOR_W + 128U, // FCUEQ_D + 128U, // FCUEQ_W + 128U, // FCULE_D + 128U, // FCULE_W + 128U, // FCULT_D + 128U, // FCULT_W + 128U, // FCUNE_D + 128U, // FCUNE_W + 128U, // FCUN_D + 128U, // FCUN_W + 128U, // FDIV_D + 128U, // FDIV_D32 + 128U, // FDIV_D32_MM + 128U, // FDIV_D64 + 128U, // FDIV_D64_MM + 128U, // FDIV_S + 128U, // FDIV_S_MM + 72U, // FDIV_S_MMR6 + 128U, // FDIV_W + 128U, // FEXDO_H + 128U, // FEXDO_W + 128U, // FEXP2_D + 128U, // FEXP2_W 0U, // FEXUPL_D 0U, // FEXUPL_W 0U, // FEXUPR_D @@ -2548,195 +6187,247 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) 0U, // FFQR_W 0U, // FILL_B 0U, // FILL_D - 0U, // FILL_FD_PSEUDO - 0U, // FILL_FW_PSEUDO 0U, // FILL_H 0U, // FILL_W 0U, // FLOG2_D 0U, // FLOG2_W 0U, // FLOOR_L_D64 + 0U, // FLOOR_L_D_MMR6 0U, // FLOOR_L_S + 0U, // FLOOR_L_S_MMR6 0U, // FLOOR_W_D32 0U, // FLOOR_W_D64 + 0U, // FLOOR_W_D_MMR6 0U, // FLOOR_W_MM 0U, // FLOOR_W_S 0U, // FLOOR_W_S_MM - 2U, // FMADD_D - 2U, // FMADD_W - 0U, // FMAX_A_D - 0U, // FMAX_A_W - 0U, // FMAX_D - 0U, // FMAX_W - 0U, // FMIN_A_D - 0U, // FMIN_A_W - 0U, // FMIN_D - 0U, // FMIN_W + 0U, // FLOOR_W_S_MMR6 + 184U, // FMADD_D + 184U, // FMADD_W + 128U, // FMAX_A_D + 128U, // FMAX_A_W + 128U, // FMAX_D + 128U, // FMAX_W + 128U, // FMIN_A_D + 128U, // FMIN_A_W + 128U, // FMIN_D + 128U, // FMIN_W 0U, // FMOV_D32 0U, // FMOV_D32_MM 0U, // FMOV_D64 + 0U, // FMOV_D64_MM + 0U, // FMOV_D_MMR6 0U, // FMOV_S 0U, // FMOV_S_MM - 2U, // FMSUB_D - 2U, // FMSUB_W - 0U, // FMUL_D - 0U, // FMUL_D32 - 0U, // FMUL_D64 - 0U, // FMUL_MM - 0U, // FMUL_S - 0U, // FMUL_S_MM - 0U, // FMUL_W + 0U, // FMOV_S_MMR6 + 184U, // FMSUB_D + 184U, // FMSUB_W + 128U, // FMUL_D + 128U, // FMUL_D32 + 128U, // FMUL_D32_MM + 128U, // FMUL_D64 + 128U, // FMUL_D64_MM + 128U, // FMUL_PS64 + 128U, // FMUL_S + 128U, // FMUL_S_MM + 72U, // FMUL_S_MMR6 + 128U, // FMUL_W 0U, // FNEG_D32 + 0U, // FNEG_D32_MM 0U, // FNEG_D64 - 0U, // FNEG_MM + 0U, // FNEG_D64_MM 0U, // FNEG_S 0U, // FNEG_S_MM + 0U, // FNEG_S_MMR6 + 1U, // FORK + 1U, // FORK_NM 0U, // FRCP_D 0U, // FRCP_W 0U, // FRINT_D 0U, // FRINT_W 0U, // FRSQRT_D 0U, // FRSQRT_W - 0U, // FSAF_D - 0U, // FSAF_W - 0U, // FSEQ_D - 0U, // FSEQ_W - 0U, // FSLE_D - 0U, // FSLE_W - 0U, // FSLT_D - 0U, // FSLT_W - 0U, // FSNE_D - 0U, // FSNE_W - 0U, // FSOR_D - 0U, // FSOR_W + 128U, // FSAF_D + 128U, // FSAF_W + 128U, // FSEQ_D + 128U, // FSEQ_W + 128U, // FSLE_D + 128U, // FSLE_W + 128U, // FSLT_D + 128U, // FSLT_W + 128U, // FSNE_D + 128U, // FSNE_W + 128U, // FSOR_D + 128U, // FSOR_W 0U, // FSQRT_D 0U, // FSQRT_D32 + 0U, // FSQRT_D32_MM 0U, // FSQRT_D64 - 0U, // FSQRT_MM + 0U, // FSQRT_D64_MM 0U, // FSQRT_S 0U, // FSQRT_S_MM 0U, // FSQRT_W - 0U, // FSUB_D - 0U, // FSUB_D32 - 0U, // FSUB_D64 - 0U, // FSUB_MM - 0U, // FSUB_S - 0U, // FSUB_S_MM - 0U, // FSUB_W - 0U, // FSUEQ_D - 0U, // FSUEQ_W - 0U, // FSULE_D - 0U, // FSULE_W - 0U, // FSULT_D - 0U, // FSULT_W - 0U, // FSUNE_D - 0U, // FSUNE_W - 0U, // FSUN_D - 0U, // FSUN_W + 128U, // FSUB_D + 128U, // FSUB_D32 + 128U, // FSUB_D32_MM + 128U, // FSUB_D64 + 128U, // FSUB_D64_MM + 128U, // FSUB_PS64 + 128U, // FSUB_S + 128U, // FSUB_S_MM + 72U, // FSUB_S_MMR6 + 128U, // FSUB_W + 128U, // FSUEQ_D + 128U, // FSUEQ_W + 128U, // FSULE_D + 128U, // FSULE_W + 128U, // FSULT_D + 128U, // FSULT_W + 128U, // FSUNE_D + 128U, // FSUNE_W + 128U, // FSUN_D + 128U, // FSUN_W 0U, // FTINT_S_D 0U, // FTINT_S_W 0U, // FTINT_U_D 0U, // FTINT_U_W - 0U, // FTQ_H - 0U, // FTQ_W + 128U, // FTQ_H + 128U, // FTQ_W 0U, // FTRUNC_S_D 0U, // FTRUNC_S_W 0U, // FTRUNC_U_D 0U, // FTRUNC_U_W - 0U, // GotPrologue16 - 0U, // HADD_S_D - 0U, // HADD_S_H - 0U, // HADD_S_W - 0U, // HADD_U_D - 0U, // HADD_U_H - 0U, // HADD_U_W - 0U, // HSUB_S_D - 0U, // HSUB_S_H - 0U, // HSUB_S_W - 0U, // HSUB_U_D - 0U, // HSUB_U_H - 0U, // HSUB_U_W - 0U, // ILVEV_B - 0U, // ILVEV_D - 0U, // ILVEV_H - 0U, // ILVEV_W - 0U, // ILVL_B - 0U, // ILVL_D - 0U, // ILVL_H - 0U, // ILVL_W - 0U, // ILVOD_B - 0U, // ILVOD_D - 0U, // ILVOD_H - 0U, // ILVOD_W - 0U, // ILVR_B - 0U, // ILVR_D - 0U, // ILVR_H - 0U, // ILVR_W - 21U, // INS + 0U, // GINVI + 0U, // GINVI_MMR6 + 0U, // GINVI_NM + 0U, // GINVT + 0U, // GINVT_MMR6 + 0U, // GINVT_NM + 128U, // HADD_S_D + 128U, // HADD_S_H + 128U, // HADD_S_W + 128U, // HADD_U_D + 128U, // HADD_U_H + 128U, // HADD_U_W + 128U, // HSUB_S_D + 128U, // HSUB_S_H + 128U, // HSUB_S_W + 128U, // HSUB_U_D + 128U, // HSUB_U_H + 128U, // HSUB_U_W + 0U, // HYPCALL + 0U, // HYPCALL_MM + 128U, // ILVEV_B + 128U, // ILVEV_D + 128U, // ILVEV_H + 128U, // ILVEV_W + 128U, // ILVL_B + 128U, // ILVL_D + 128U, // ILVL_H + 128U, // ILVL_W + 128U, // ILVOD_B + 128U, // ILVOD_D + 128U, // ILVOD_H + 128U, // ILVOD_W + 128U, // ILVR_B + 128U, // ILVR_D + 128U, // ILVR_H + 128U, // ILVR_W + 7192U, // INS 0U, // INSERT_B - 0U, // INSERT_B_VIDX_PSEUDO 0U, // INSERT_D - 0U, // INSERT_D_VIDX_PSEUDO - 0U, // INSERT_FD_PSEUDO - 0U, // INSERT_FD_VIDX_PSEUDO - 0U, // INSERT_FW_PSEUDO - 0U, // INSERT_FW_VIDX_PSEUDO 0U, // INSERT_H - 0U, // INSERT_H_VIDX_PSEUDO 0U, // INSERT_W - 0U, // INSERT_W_VIDX_PSEUDO 0U, // INSV 0U, // INSVE_B 0U, // INSVE_D 0U, // INSVE_H 0U, // INSVE_W - 21U, // INS_MM + 0U, // INSV_MM + 7192U, // INS_MM + 7192U, // INS_MMR6 + 7192U, // INS_NM 0U, // J 0U, // JAL 0U, // JALR 0U, // JALR16_MM 0U, // JALR64 - 0U, // JALR64Pseudo - 0U, // JALRPseudo + 0U, // JALRC16_MMR6 + 0U, // JALRC16_NM + 0U, // JALRCHB_NM + 0U, // JALRC_HB_MMR6 + 0U, // JALRC_MMR6 + 0U, // JALRC_NM 0U, // JALRS16_MM 0U, // JALRS_MM 0U, // JALR_HB + 0U, // JALR_HB64 0U, // JALR_MM 0U, // JALS_MM 0U, // JALX 0U, // JALX_MM 0U, // JAL_MM 0U, // JIALC + 0U, // JIALC64 + 0U, // JIALC_MMR6 0U, // JIC + 0U, // JIC64 + 0U, // JIC_MMR6 0U, // JR 0U, // JR16_MM 0U, // JR64 0U, // JRADDIUSP 0U, // JRC16_MM + 0U, // JRC16_MMR6 + 0U, // JRCADDIUSP_MMR6 + 0U, // JRC_NM 0U, // JR_HB + 0U, // JR_HB64 + 0U, // JR_HB64_R6 0U, // JR_HB_R6 0U, // JR_MM 0U, // J_MM 0U, // Jal16 0U, // JalB16 - 0U, // JalOneReg - 0U, // JalTwoReg 0U, // JrRa16 0U, // JrcRa16 0U, // JrcRx16 0U, // JumpLinkReg16 + 0U, // LAPC32_NM + 0U, // LAPC48_NM 0U, // LB + 0U, // LB16_NM 0U, // LB64 + 0U, // LBE + 0U, // LBE_MM + 0U, // LBGP_NM 0U, // LBU16_MM - 0U, // LBUX + 0U, // LBU16_NM + 0U, // LBUGP_NM + 1U, // LBUX + 1U, // LBUX_MM + 0U, // LBUX_NM + 0U, // LBU_MMR6 + 0U, // LBU_NM + 0U, // LBUs9_NM + 0U, // LBX_NM 0U, // LB_MM + 0U, // LB_MMR6 + 0U, // LB_NM + 0U, // LBs9_NM 0U, // LBu 0U, // LBu64 + 0U, // LBuE + 0U, // LBuE_MM 0U, // LBu_MM 0U, // LD 0U, // LDC1 0U, // LDC164 - 0U, // LDC1_MM + 0U, // LDC1_D64_MMR6 + 0U, // LDC1_MM_D32 + 0U, // LDC1_MM_D64 0U, // LDC2 + 0U, // LDC2_MMR6 0U, // LDC2_R6 0U, // LDC3 0U, // LDI_B @@ -2746,271 +6437,384 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) 0U, // LDL 0U, // LDPC 0U, // LDR - 0U, // LDXC1 - 0U, // LDXC164 + 1U, // LDXC1 + 1U, // LDXC164 0U, // LD_B 0U, // LD_D 0U, // LD_H 0U, // LD_W + 0U, // LEA_ADDIU_NM 0U, // LEA_ADDiu 0U, // LEA_ADDiu64 0U, // LEA_ADDiu_MM 0U, // LH + 0U, // LH16_NM 0U, // LH64 + 0U, // LHE + 0U, // LHE_MM + 0U, // LHGP_NM 0U, // LHU16_MM - 0U, // LHX + 0U, // LHU16_NM + 0U, // LHUGP_NM + 0U, // LHUXS_NM + 0U, // LHUX_NM + 0U, // LHU_NM + 0U, // LHUs9_NM + 1U, // LHX + 0U, // LHXS_NM + 1U, // LHX_MM + 0U, // LHX_NM 0U, // LH_MM + 0U, // LH_NM + 0U, // LHs9_NM 0U, // LHu 0U, // LHu64 + 0U, // LHuE + 0U, // LHuE_MM 0U, // LHu_MM 0U, // LI16_MM + 0U, // LI16_MMR6 + 0U, // LI16_NM + 0U, // LI48_NM 0U, // LL + 0U, // LL64 + 0U, // LL64_R6 0U, // LLD 0U, // LLD_R6 + 0U, // LLE + 0U, // LLE_MM + 76U, // LLWP_NM 0U, // LL_MM + 0U, // LL_MMR6 + 0U, // LL_NM 0U, // LL_R6 - 0U, // LOAD_ACC128 - 0U, // LOAD_ACC64 - 0U, // LOAD_ACC64DSP - 0U, // LOAD_CCOND_DSP - 0U, // LONG_BRANCH_ADDiu - 0U, // LONG_BRANCH_DADDiu - 0U, // LONG_BRANCH_LUi - 4U, // LSA - 4U, // LSA_R6 - 0U, // LUXC1 - 0U, // LUXC164 - 0U, // LUXC1_MM + 9216U, // LSA + 1U, // LSA_MMR6 + 1024U, // LSA_NM + 9216U, // LSA_R6 + 0U, // LUI_MMR6 + 0U, // LUI_NM + 1U, // LUXC1 + 1U, // LUXC164 + 1U, // LUXC1_MM 0U, // LUi 0U, // LUi64 0U, // LUi_MM 0U, // LW 0U, // LW16_MM + 0U, // LW16_NM + 0U, // LW4x4_NM 0U, // LW64 0U, // LWC1 0U, // LWC1_MM 0U, // LWC2 + 0U, // LWC2_MMR6 0U, // LWC2_R6 0U, // LWC3 + 0U, // LWDSP + 0U, // LWDSP_MM + 0U, // LWE + 0U, // LWE_MM + 0U, // LWGP16_NM 0U, // LWGP_MM + 0U, // LWGP_NM 0U, // LWL 0U, // LWL64 + 0U, // LWLE + 0U, // LWLE_MM 0U, // LWL_MM 0U, // LWM16_MM + 0U, // LWM16_MMR6 0U, // LWM32_MM - 0U, // LWM_MM + 184U, // LWM_NM 0U, // LWPC + 0U, // LWPC_MMR6 + 0U, // LWPC_NM 0U, // LWP_MM 0U, // LWR 0U, // LWR64 + 0U, // LWRE + 0U, // LWRE_MM 0U, // LWR_MM + 0U, // LWSP16_NM 0U, // LWSP_MM 0U, // LWUPC 0U, // LWU_MM - 0U, // LWX - 0U, // LWXC1 - 0U, // LWXC1_MM - 0U, // LWXS_MM + 1U, // LWX + 1U, // LWXC1 + 1U, // LWXC1_MM + 0U, // LWXS16_NM + 1U, // LWXS_MM + 0U, // LWXS_NM + 1U, // LWX_MM + 0U, // LWX_NM 0U, // LW_MM + 0U, // LW_MMR6 + 0U, // LW_NM + 0U, // LWs9_NM 0U, // LWu 0U, // LbRxRyOffMemX16 0U, // LbuRxRyOffMemX16 0U, // LhRxRyOffMemX16 0U, // LhuRxRyOffMemX16 - 0U, // LiRxImm16 + 1U, // LiRxImm16 0U, // LiRxImmAlignX16 0U, // LiRxImmX16 - 0U, // LoadAddr32Imm - 0U, // LoadAddr32Reg - 0U, // LoadImm32Reg - 0U, // LoadImm64Reg - 0U, // LwConstant32 - 0U, // LwRxPcTcp16 + 1U, // LwRxPcTcp16 0U, // LwRxPcTcpX16 0U, // LwRxRyOffMemX16 0U, // LwRxSpImmX16 0U, // MADD - 2U, // MADDF_D - 2U, // MADDF_S - 2U, // MADDR_Q_H - 2U, // MADDR_Q_W + 184U, // MADDF_D + 184U, // MADDF_D_MMR6 + 184U, // MADDF_S + 184U, // MADDF_S_MMR6 + 184U, // MADDR_Q_H + 184U, // MADDR_Q_W 0U, // MADDU - 0U, // MADDU_DSP + 128U, // MADDU_DSP + 128U, // MADDU_DSP_MM 0U, // MADDU_MM - 2U, // MADDV_B - 2U, // MADDV_D - 2U, // MADDV_H - 2U, // MADDV_W - 20U, // MADD_D32 - 20U, // MADD_D32_MM - 20U, // MADD_D64 - 0U, // MADD_DSP + 184U, // MADDV_B + 184U, // MADDV_D + 184U, // MADDV_H + 184U, // MADDV_W + 0U, // MADD_D32 + 0U, // MADD_D32_MM + 0U, // MADD_D64 + 128U, // MADD_DSP + 128U, // MADD_DSP_MM 0U, // MADD_MM - 2U, // MADD_Q_H - 2U, // MADD_Q_W - 20U, // MADD_S - 20U, // MADD_S_MM - 0U, // MAQ_SA_W_PHL - 0U, // MAQ_SA_W_PHR - 0U, // MAQ_S_W_PHL - 0U, // MAQ_S_W_PHR - 0U, // MAXA_D - 0U, // MAXA_S - 0U, // MAXI_S_B - 0U, // MAXI_S_D - 0U, // MAXI_S_H - 0U, // MAXI_S_W - 0U, // MAXI_U_B - 0U, // MAXI_U_D - 0U, // MAXI_U_H - 0U, // MAXI_U_W - 0U, // MAX_A_B - 0U, // MAX_A_D - 0U, // MAX_A_H - 0U, // MAX_A_W - 0U, // MAX_D - 0U, // MAX_S - 0U, // MAX_S_B - 0U, // MAX_S_D - 0U, // MAX_S_H - 0U, // MAX_S_W - 0U, // MAX_U_B - 0U, // MAX_U_D - 0U, // MAX_U_H - 0U, // MAX_U_W - 1U, // MFC0 + 184U, // MADD_Q_H + 184U, // MADD_Q_W + 0U, // MADD_S + 0U, // MADD_S_MM + 128U, // MAQ_SA_W_PHL + 128U, // MAQ_SA_W_PHL_MM + 128U, // MAQ_SA_W_PHR + 128U, // MAQ_SA_W_PHR_MM + 128U, // MAQ_S_W_PHL + 128U, // MAQ_S_W_PHL_MM + 128U, // MAQ_S_W_PHR + 128U, // MAQ_S_W_PHR_MM + 128U, // MAXA_D + 128U, // MAXA_D_MMR6 + 128U, // MAXA_S + 128U, // MAXA_S_MMR6 + 128U, // MAXI_S_B + 128U, // MAXI_S_D + 128U, // MAXI_S_H + 128U, // MAXI_S_W + 152U, // MAXI_U_B + 152U, // MAXI_U_D + 152U, // MAXI_U_H + 152U, // MAXI_U_W + 128U, // MAX_A_B + 128U, // MAX_A_D + 128U, // MAX_A_H + 128U, // MAX_A_W + 128U, // MAX_D + 128U, // MAX_D_MMR6 + 128U, // MAX_S + 128U, // MAX_S_B + 128U, // MAX_S_D + 128U, // MAX_S_H + 128U, // MAX_S_MMR6 + 128U, // MAX_S_W + 128U, // MAX_U_B + 128U, // MAX_U_D + 128U, // MAX_U_H + 128U, // MAX_U_W + 136U, // MFC0 + 0U, // MFC0Sel_NM + 136U, // MFC0_MMR6 + 152U, // MFC0_NM 0U, // MFC1 + 0U, // MFC1_D64 0U, // MFC1_MM - 1U, // MFC2 + 0U, // MFC1_MMR6 + 136U, // MFC2 + 0U, // MFC2_MMR6 + 136U, // MFGC0 + 136U, // MFGC0_MM + 0U, // MFHC0Sel_NM + 136U, // MFHC0_MMR6 + 152U, // MFHC0_NM 0U, // MFHC1_D32 + 0U, // MFHC1_D32_MM 0U, // MFHC1_D64 - 0U, // MFHC1_MM + 0U, // MFHC1_D64_MM + 0U, // MFHC2_MMR6 + 136U, // MFHGC0 + 136U, // MFHGC0_MM 0U, // MFHI 0U, // MFHI16_MM 0U, // MFHI64 0U, // MFHI_DSP + 0U, // MFHI_DSP_MM 0U, // MFHI_MM 0U, // MFLO 0U, // MFLO16_MM 0U, // MFLO64 0U, // MFLO_DSP + 0U, // MFLO_DSP_MM 0U, // MFLO_MM - 0U, // MINA_D - 0U, // MINA_S - 0U, // MINI_S_B - 0U, // MINI_S_D - 0U, // MINI_S_H - 0U, // MINI_S_W - 0U, // MINI_U_B - 0U, // MINI_U_D - 0U, // MINI_U_H - 0U, // MINI_U_W - 0U, // MIN_A_B - 0U, // MIN_A_D - 0U, // MIN_A_H - 0U, // MIN_A_W - 0U, // MIN_D - 0U, // MIN_S - 0U, // MIN_S_B - 0U, // MIN_S_D - 0U, // MIN_S_H - 0U, // MIN_S_W - 0U, // MIN_U_B - 0U, // MIN_U_D - 0U, // MIN_U_H - 0U, // MIN_U_W - 0U, // MIPSeh_return32 - 0U, // MIPSeh_return64 - 0U, // MOD - 0U, // MODSUB - 0U, // MODU - 0U, // MOD_S_B - 0U, // MOD_S_D - 0U, // MOD_S_H - 0U, // MOD_S_W - 0U, // MOD_U_B - 0U, // MOD_U_D - 0U, // MOD_U_H - 0U, // MOD_U_W + 19520U, // MFTR + 19520U, // MFTR_NM + 128U, // MINA_D + 128U, // MINA_D_MMR6 + 128U, // MINA_S + 128U, // MINA_S_MMR6 + 128U, // MINI_S_B + 128U, // MINI_S_D + 128U, // MINI_S_H + 128U, // MINI_S_W + 152U, // MINI_U_B + 152U, // MINI_U_D + 152U, // MINI_U_H + 152U, // MINI_U_W + 128U, // MIN_A_B + 128U, // MIN_A_D + 128U, // MIN_A_H + 128U, // MIN_A_W + 128U, // MIN_D + 128U, // MIN_D_MMR6 + 128U, // MIN_S + 128U, // MIN_S_B + 128U, // MIN_S_D + 128U, // MIN_S_H + 128U, // MIN_S_MMR6 + 128U, // MIN_S_W + 128U, // MIN_U_B + 128U, // MIN_U_D + 128U, // MIN_U_H + 128U, // MIN_U_W + 128U, // MOD + 128U, // MODSUB + 128U, // MODSUB_MM + 128U, // MODU + 128U, // MODU_MMR6 + 128U, // MODU_NM + 128U, // MOD_MMR6 + 128U, // MOD_NM + 128U, // MOD_S_B + 128U, // MOD_S_D + 128U, // MOD_S_H + 128U, // MOD_S_W + 128U, // MOD_U_B + 128U, // MOD_U_D + 128U, // MOD_U_H + 128U, // MOD_U_W 0U, // MOVE16_MM + 0U, // MOVE16_MMR6 + 80U, // MOVEBALC_NM + 0U, // MOVEPREV_NM 0U, // MOVEP_MM + 0U, // MOVEP_MMR6 + 0U, // MOVEP_NM + 0U, // MOVE_NM 0U, // MOVE_V - 0U, // MOVF_D32 - 0U, // MOVF_D32_MM - 0U, // MOVF_D64 - 0U, // MOVF_I - 0U, // MOVF_I64 - 0U, // MOVF_I_MM - 0U, // MOVF_S - 0U, // MOVF_S_MM - 0U, // MOVN_I64_D64 - 0U, // MOVN_I64_I - 0U, // MOVN_I64_I64 - 0U, // MOVN_I64_S - 0U, // MOVN_I_D32 - 0U, // MOVN_I_D32_MM - 0U, // MOVN_I_D64 - 0U, // MOVN_I_I - 0U, // MOVN_I_I64 - 0U, // MOVN_I_MM - 0U, // MOVN_I_S - 0U, // MOVN_I_S_MM - 0U, // MOVT_D32 - 0U, // MOVT_D32_MM - 0U, // MOVT_D64 - 0U, // MOVT_I - 0U, // MOVT_I64 - 0U, // MOVT_I_MM - 0U, // MOVT_S - 0U, // MOVT_S_MM - 0U, // MOVZ_I64_D64 - 0U, // MOVZ_I64_I - 0U, // MOVZ_I64_I64 - 0U, // MOVZ_I64_S - 0U, // MOVZ_I_D32 - 0U, // MOVZ_I_D32_MM - 0U, // MOVZ_I_D64 - 0U, // MOVZ_I_I - 0U, // MOVZ_I_I64 - 0U, // MOVZ_I_MM - 0U, // MOVZ_I_S - 0U, // MOVZ_I_S_MM + 128U, // MOVF_D32 + 128U, // MOVF_D32_MM + 128U, // MOVF_D64 + 128U, // MOVF_I + 128U, // MOVF_I64 + 128U, // MOVF_I_MM + 128U, // MOVF_S + 128U, // MOVF_S_MM + 128U, // MOVN_I64_D64 + 128U, // MOVN_I64_I + 128U, // MOVN_I64_I64 + 128U, // MOVN_I64_S + 128U, // MOVN_I_D32 + 128U, // MOVN_I_D32_MM + 128U, // MOVN_I_D64 + 128U, // MOVN_I_I + 128U, // MOVN_I_I64 + 128U, // MOVN_I_MM + 128U, // MOVN_I_S + 128U, // MOVN_I_S_MM + 128U, // MOVN_NM + 128U, // MOVT_D32 + 128U, // MOVT_D32_MM + 128U, // MOVT_D64 + 128U, // MOVT_I + 128U, // MOVT_I64 + 128U, // MOVT_I_MM + 128U, // MOVT_S + 128U, // MOVT_S_MM + 128U, // MOVZ_I64_D64 + 128U, // MOVZ_I64_I + 128U, // MOVZ_I64_I64 + 128U, // MOVZ_I64_S + 128U, // MOVZ_I_D32 + 128U, // MOVZ_I_D32_MM + 128U, // MOVZ_I_D64 + 128U, // MOVZ_I_I + 128U, // MOVZ_I_I64 + 128U, // MOVZ_I_MM + 128U, // MOVZ_I_S + 128U, // MOVZ_I_S_MM + 128U, // MOVZ_NM 0U, // MSUB - 2U, // MSUBF_D - 2U, // MSUBF_S - 2U, // MSUBR_Q_H - 2U, // MSUBR_Q_W + 184U, // MSUBF_D + 184U, // MSUBF_D_MMR6 + 184U, // MSUBF_S + 184U, // MSUBF_S_MMR6 + 184U, // MSUBR_Q_H + 184U, // MSUBR_Q_W 0U, // MSUBU - 0U, // MSUBU_DSP + 128U, // MSUBU_DSP + 128U, // MSUBU_DSP_MM 0U, // MSUBU_MM - 2U, // MSUBV_B - 2U, // MSUBV_D - 2U, // MSUBV_H - 2U, // MSUBV_W - 20U, // MSUB_D32 - 20U, // MSUB_D32_MM - 20U, // MSUB_D64 - 0U, // MSUB_DSP + 184U, // MSUBV_B + 184U, // MSUBV_D + 184U, // MSUBV_H + 184U, // MSUBV_W + 0U, // MSUB_D32 + 0U, // MSUB_D32_MM + 0U, // MSUB_D64 + 128U, // MSUB_DSP + 128U, // MSUB_DSP_MM 0U, // MSUB_MM - 2U, // MSUB_Q_H - 2U, // MSUB_Q_W - 20U, // MSUB_S - 20U, // MSUB_S_MM - 1U, // MTC0 + 184U, // MSUB_Q_H + 184U, // MSUB_Q_W + 0U, // MSUB_S + 0U, // MSUB_S_MM + 0U, // MTC0 + 0U, // MTC0Sel_NM + 0U, // MTC0_MMR6 + 152U, // MTC0_NM 0U, // MTC1 + 0U, // MTC1_D64 + 0U, // MTC1_D64_MM 0U, // MTC1_MM - 1U, // MTC2 + 0U, // MTC1_MMR6 + 0U, // MTC2 + 0U, // MTC2_MMR6 + 0U, // MTGC0 + 0U, // MTGC0_MM + 0U, // MTHC0Sel_NM + 0U, // MTHC0_MMR6 + 152U, // MTHC0_NM 0U, // MTHC1_D32 + 0U, // MTHC1_D32_MM 0U, // MTHC1_D64 - 0U, // MTHC1_MM + 0U, // MTHC1_D64_MM + 0U, // MTHC2_MMR6 + 0U, // MTHGC0 + 0U, // MTHGC0_MM 0U, // MTHI 0U, // MTHI64 0U, // MTHI_DSP + 0U, // MTHI_DSP_MM 0U, // MTHI_MM 0U, // MTHLIP + 0U, // MTHLIP_MM 0U, // MTLO 0U, // MTLO64 0U, // MTLO_DSP + 0U, // MTLO_DSP_MM 0U, // MTLO_MM 0U, // MTM0 0U, // MTM1 @@ -3018,46 +6822,68 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) 0U, // MTP0 0U, // MTP1 0U, // MTP2 - 0U, // MUH - 0U, // MUHU - 0U, // MUL - 0U, // MULEQ_S_W_PHL - 0U, // MULEQ_S_W_PHR - 0U, // MULEU_S_PH_QBL - 0U, // MULEU_S_PH_QBR - 0U, // MULQ_RS_PH - 0U, // MULQ_RS_W - 0U, // MULQ_S_PH - 0U, // MULQ_S_W - 0U, // MULR_Q_H - 0U, // MULR_Q_W - 0U, // MULSAQ_S_W_PH - 0U, // MULSA_W_PH + 2U, // MTTR + 2U, // MTTR_NM + 128U, // MUH + 128U, // MUHU + 128U, // MUHU_MMR6 + 128U, // MUHU_NM + 128U, // MUH_MMR6 + 128U, // MUH_NM + 128U, // MUL + 128U, // MUL4x4_NM + 128U, // MULEQ_S_W_PHL + 128U, // MULEQ_S_W_PHL_MM + 128U, // MULEQ_S_W_PHR + 128U, // MULEQ_S_W_PHR_MM + 128U, // MULEU_S_PH_QBL + 128U, // MULEU_S_PH_QBL_MM + 128U, // MULEU_S_PH_QBR + 128U, // MULEU_S_PH_QBR_MM + 128U, // MULQ_RS_PH + 128U, // MULQ_RS_PH_MM + 128U, // MULQ_RS_W + 128U, // MULQ_RS_W_MMR2 + 128U, // MULQ_S_PH + 128U, // MULQ_S_PH_MMR2 + 128U, // MULQ_S_W + 128U, // MULQ_S_W_MMR2 + 128U, // MULR_PS64 + 128U, // MULR_Q_H + 128U, // MULR_Q_W + 128U, // MULSAQ_S_W_PH + 128U, // MULSAQ_S_W_PH_MM + 128U, // MULSA_W_PH + 128U, // MULSA_W_PH_MMR2 0U, // MULT - 0U, // MULTU_DSP - 0U, // MULT_DSP + 128U, // MULTU_DSP + 128U, // MULTU_DSP_MM + 128U, // MULT_DSP + 128U, // MULT_DSP_MM 0U, // MULT_MM 0U, // MULTu 0U, // MULTu_MM - 0U, // MULU - 0U, // MULV_B - 0U, // MULV_D - 0U, // MULV_H - 0U, // MULV_W - 0U, // MUL_MM - 0U, // MUL_PH - 0U, // MUL_Q_H - 0U, // MUL_Q_W - 0U, // MUL_R6 - 0U, // MUL_S_PH + 128U, // MULU + 128U, // MULU_MMR6 + 128U, // MULU_NM + 128U, // MULV_B + 128U, // MULV_D + 128U, // MULV_H + 128U, // MULV_W + 128U, // MUL_MM + 128U, // MUL_MMR6 + 128U, // MUL_NM + 128U, // MUL_PH + 128U, // MUL_PH_MMR2 + 128U, // MUL_Q_H + 128U, // MUL_Q_W + 128U, // MUL_R6 + 128U, // MUL_S_PH + 128U, // MUL_S_PH_MMR2 0U, // Mfhi16 0U, // Mflo16 0U, // Move32R16 0U, // MoveR3216 - 0U, // MultRxRy16 - 0U, // MultRxRyRz16 - 0U, // MultuRxRy16 - 0U, // MultuRxRyRz16 0U, // NLOC_B 0U, // NLOC_D 0U, // NLOC_H @@ -3066,2660 +6892,4351 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) 0U, // NLZC_D 0U, // NLZC_H 0U, // NLZC_W - 20U, // NMADD_D32 - 20U, // NMADD_D32_MM - 20U, // NMADD_D64 - 20U, // NMADD_S - 20U, // NMADD_S_MM - 20U, // NMSUB_D32 - 20U, // NMSUB_D32_MM - 20U, // NMSUB_D64 - 20U, // NMSUB_S - 20U, // NMSUB_S_MM - 0U, // NOP - 0U, // NOR - 0U, // NOR64 - 0U, // NORI_B - 0U, // NOR_MM - 0U, // NOR_V - 0U, // NOR_V_D_PSEUDO - 0U, // NOR_V_H_PSEUDO - 0U, // NOR_V_W_PSEUDO + 0U, // NMADD_D32 + 0U, // NMADD_D32_MM + 0U, // NMADD_D64 + 0U, // NMADD_S + 0U, // NMADD_S_MM + 0U, // NMSUB_D32 + 0U, // NMSUB_D32_MM + 0U, // NMSUB_D64 + 0U, // NMSUB_S + 0U, // NMSUB_S_MM + 0U, // NOP32_NM + 0U, // NOP_NM + 128U, // NOR + 128U, // NOR64 + 20U, // NORI_B + 128U, // NOR_MM + 128U, // NOR_MMR6 + 128U, // NOR_NM + 128U, // NOR_V 0U, // NOT16_MM + 0U, // NOT16_MMR6 + 0U, // NOT16_NM 0U, // NegRxRy16 0U, // NotRxRy16 - 0U, // OR + 128U, // OR 0U, // OR16_MM - 0U, // OR64 - 0U, // ORI_B - 0U, // OR_MM - 0U, // OR_V - 0U, // OR_V_D_PSEUDO - 0U, // OR_V_H_PSEUDO - 0U, // OR_V_W_PSEUDO - 1U, // ORi - 1U, // ORi64 - 1U, // ORi_MM + 0U, // OR16_MMR6 + 128U, // OR16_NM + 128U, // OR64 + 20U, // ORI_B + 16U, // ORI_MMR6 + 128U, // ORI_NM + 128U, // OR_MM + 128U, // OR_MMR6 + 128U, // OR_NM + 128U, // OR_V + 16U, // ORi + 16U, // ORi64 + 16U, // ORi_MM 0U, // OrRxRxRy16 - 0U, // PACKRL_PH + 128U, // PACKRL_PH + 128U, // PACKRL_PH_MM 0U, // PAUSE 0U, // PAUSE_MM - 0U, // PCKEV_B - 0U, // PCKEV_D - 0U, // PCKEV_H - 0U, // PCKEV_W - 0U, // PCKOD_B - 0U, // PCKOD_D - 0U, // PCKOD_H - 0U, // PCKOD_W + 0U, // PAUSE_MMR6 + 0U, // PAUSE_NM + 128U, // PCKEV_B + 128U, // PCKEV_D + 128U, // PCKEV_H + 128U, // PCKEV_W + 128U, // PCKOD_B + 128U, // PCKOD_D + 128U, // PCKOD_H + 128U, // PCKOD_W 0U, // PCNT_B 0U, // PCNT_D 0U, // PCNT_H 0U, // PCNT_W - 0U, // PICK_PH - 0U, // PICK_QB + 128U, // PICK_PH + 128U, // PICK_PH_MM + 128U, // PICK_QB + 128U, // PICK_QB_MM + 128U, // PLL_PS64 + 128U, // PLU_PS64 0U, // POP 0U, // PRECEQU_PH_QBL 0U, // PRECEQU_PH_QBLA + 0U, // PRECEQU_PH_QBLA_MM + 0U, // PRECEQU_PH_QBL_MM 0U, // PRECEQU_PH_QBR 0U, // PRECEQU_PH_QBRA + 0U, // PRECEQU_PH_QBRA_MM + 0U, // PRECEQU_PH_QBR_MM 0U, // PRECEQ_W_PHL + 0U, // PRECEQ_W_PHL_MM 0U, // PRECEQ_W_PHR + 0U, // PRECEQ_W_PHR_MM 0U, // PRECEU_PH_QBL 0U, // PRECEU_PH_QBLA + 0U, // PRECEU_PH_QBLA_MM + 0U, // PRECEU_PH_QBL_MM 0U, // PRECEU_PH_QBR 0U, // PRECEU_PH_QBRA - 0U, // PRECRQU_S_QB_PH - 0U, // PRECRQ_PH_W - 0U, // PRECRQ_QB_PH - 0U, // PRECRQ_RS_PH_W - 0U, // PRECR_QB_PH - 1U, // PRECR_SRA_PH_W - 1U, // PRECR_SRA_R_PH_W + 0U, // PRECEU_PH_QBRA_MM + 0U, // PRECEU_PH_QBR_MM + 128U, // PRECRQU_S_QB_PH + 128U, // PRECRQU_S_QB_PH_MM + 128U, // PRECRQ_PH_W + 128U, // PRECRQ_PH_W_MM + 128U, // PRECRQ_QB_PH + 128U, // PRECRQ_QB_PH_MM + 128U, // PRECRQ_RS_PH_W + 128U, // PRECRQ_RS_PH_W_MM + 128U, // PRECR_QB_PH + 128U, // PRECR_QB_PH_MMR2 + 152U, // PRECR_SRA_PH_W + 152U, // PRECR_SRA_PH_W_MMR2 + 152U, // PRECR_SRA_R_PH_W + 152U, // PRECR_SRA_R_PH_W_MMR2 0U, // PREF + 0U, // PREFE + 0U, // PREFE_MM + 0U, // PREFX_MM 0U, // PREF_MM + 0U, // PREF_MMR6 + 0U, // PREF_NM 0U, // PREF_R6 - 1U, // PREPEND - 0U, // PseudoCMPU_EQ_QB - 0U, // PseudoCMPU_LE_QB - 0U, // PseudoCMPU_LT_QB - 0U, // PseudoCMP_EQ_PH - 0U, // PseudoCMP_LE_PH - 0U, // PseudoCMP_LT_PH - 0U, // PseudoCVT_D32_W - 0U, // PseudoCVT_D64_L - 0U, // PseudoCVT_D64_W - 0U, // PseudoCVT_S_L - 0U, // PseudoCVT_S_W - 0U, // PseudoDMULT - 0U, // PseudoDMULTu - 0U, // PseudoDSDIV - 0U, // PseudoDUDIV - 0U, // PseudoIndirectBranch - 0U, // PseudoIndirectBranch64 - 0U, // PseudoMADD - 0U, // PseudoMADDU - 0U, // PseudoMFHI - 0U, // PseudoMFHI64 - 0U, // PseudoMFLO - 0U, // PseudoMFLO64 - 0U, // PseudoMSUB - 0U, // PseudoMSUBU - 0U, // PseudoMTLOHI - 0U, // PseudoMTLOHI64 - 0U, // PseudoMTLOHI_DSP - 0U, // PseudoMULT - 0U, // PseudoMULTu - 0U, // PseudoPICK_PH - 0U, // PseudoPICK_QB - 0U, // PseudoReturn - 0U, // PseudoReturn64 - 0U, // PseudoSDIV - 0U, // PseudoSELECTFP_F_D32 - 0U, // PseudoSELECTFP_F_D64 - 0U, // PseudoSELECTFP_F_I - 0U, // PseudoSELECTFP_F_I64 - 0U, // PseudoSELECTFP_F_S - 0U, // PseudoSELECTFP_T_D32 - 0U, // PseudoSELECTFP_T_D64 - 0U, // PseudoSELECTFP_T_I - 0U, // PseudoSELECTFP_T_I64 - 0U, // PseudoSELECTFP_T_S - 0U, // PseudoSELECT_D32 - 0U, // PseudoSELECT_D64 - 0U, // PseudoSELECT_I - 0U, // PseudoSELECT_I64 - 0U, // PseudoSELECT_S - 0U, // PseudoUDIV + 0U, // PREFs9_NM + 152U, // PREPEND + 152U, // PREPEND_MMR2 + 128U, // PUL_PS64 + 128U, // PUU_PS64 0U, // RADDU_W_QB + 0U, // RADDU_W_QB_MM 0U, // RDDSP - 0U, // RDHWR - 0U, // RDHWR64 - 0U, // RDHWR_MM + 0U, // RDDSP_MM + 20U, // RDHWR + 20U, // RDHWR64 + 20U, // RDHWR_MM + 136U, // RDHWR_MMR6 + 152U, // RDHWR_NM + 0U, // RDPGPR_MMR6 + 0U, // RDPGPR_NM + 0U, // RECIP_D32 + 0U, // RECIP_D32_MM + 0U, // RECIP_D64 + 0U, // RECIP_D64_MM + 0U, // RECIP_S + 0U, // RECIP_S_MM 0U, // REPLV_PH + 0U, // REPLV_PH_MM 0U, // REPLV_QB + 0U, // REPLV_QB_MM 0U, // REPL_PH + 0U, // REPL_PH_MM 0U, // REPL_QB + 0U, // REPL_QB_MM + 0U, // RESTOREJRC16_NM + 0U, // RESTOREJRC_NM + 0U, // RESTORE_NM 0U, // RINT_D + 0U, // RINT_D_MMR6 0U, // RINT_S - 1U, // ROTR - 0U, // ROTRV - 0U, // ROTRV_MM - 1U, // ROTR_MM + 0U, // RINT_S_MMR6 + 152U, // ROTR + 128U, // ROTRV + 128U, // ROTRV_MM + 128U, // ROTRV_NM + 152U, // ROTR_MM + 152U, // ROTR_NM + 18456U, // ROTX_NM 0U, // ROUND_L_D64 + 0U, // ROUND_L_D_MMR6 0U, // ROUND_L_S + 0U, // ROUND_L_S_MMR6 0U, // ROUND_W_D32 0U, // ROUND_W_D64 + 0U, // ROUND_W_D_MMR6 0U, // ROUND_W_MM 0U, // ROUND_W_S 0U, // ROUND_W_S_MM + 0U, // ROUND_W_S_MMR6 + 0U, // RSQRT_D32 + 0U, // RSQRT_D32_MM + 0U, // RSQRT_D64 + 0U, // RSQRT_D64_MM + 0U, // RSQRT_S + 0U, // RSQRT_S_MM 0U, // Restore16 0U, // RestoreX16 - 0U, // RetRA - 0U, // RetRA16 - 1U, // SAT_S_B - 1U, // SAT_S_D - 0U, // SAT_S_H - 1U, // SAT_S_W - 1U, // SAT_U_B - 1U, // SAT_U_D - 0U, // SAT_U_H - 1U, // SAT_U_W + 0U, // SAA + 0U, // SAAD + 136U, // SAT_S_B + 160U, // SAT_S_D + 164U, // SAT_S_H + 152U, // SAT_S_W + 136U, // SAT_U_B + 160U, // SAT_U_D + 164U, // SAT_U_H + 152U, // SAT_U_W + 0U, // SAVE16_NM + 0U, // SAVE_NM 0U, // SB 0U, // SB16_MM + 0U, // SB16_MMR6 + 0U, // SB16_NM 0U, // SB64 + 0U, // SBE + 0U, // SBE_MM + 0U, // SBGP_NM + 0U, // SBX_NM 0U, // SB_MM + 0U, // SB_MMR6 + 0U, // SB_NM + 0U, // SBs9_NM 0U, // SC + 0U, // SC64 + 0U, // SC64_R6 0U, // SCD 0U, // SCD_R6 + 0U, // SCE + 0U, // SCE_MM + 2U, // SCWP_NM 0U, // SC_MM + 0U, // SC_MMR6 + 0U, // SC_NM 0U, // SC_R6 0U, // SD 0U, // SDBBP 0U, // SDBBP16_MM + 0U, // SDBBP16_MMR6 + 0U, // SDBBP16_NM 0U, // SDBBP_MM + 0U, // SDBBP_MMR6 + 0U, // SDBBP_NM 0U, // SDBBP_R6 0U, // SDC1 0U, // SDC164 - 0U, // SDC1_MM + 0U, // SDC1_D64_MMR6 + 0U, // SDC1_MM_D32 + 0U, // SDC1_MM_D64 0U, // SDC2 + 0U, // SDC2_MMR6 0U, // SDC2_R6 0U, // SDC3 0U, // SDIV 0U, // SDIV_MM 0U, // SDL 0U, // SDR - 0U, // SDXC1 - 0U, // SDXC164 + 1U, // SDXC1 + 1U, // SDXC164 0U, // SEB 0U, // SEB64 0U, // SEB_MM + 0U, // SEB_NM 0U, // SEH 0U, // SEH64 0U, // SEH_MM - 0U, // SELEQZ - 0U, // SELEQZ64 - 0U, // SELEQZ_D - 0U, // SELEQZ_S - 0U, // SELNEZ - 0U, // SELNEZ64 - 0U, // SELNEZ_D - 0U, // SELNEZ_S - 2U, // SEL_D - 2U, // SEL_S - 0U, // SEQ - 0U, // SEQi + 0U, // SEH_NM + 128U, // SELEQZ + 128U, // SELEQZ64 + 128U, // SELEQZ_D + 128U, // SELEQZ_D_MMR6 + 128U, // SELEQZ_MMR6 + 128U, // SELEQZ_S + 128U, // SELEQZ_S_MMR6 + 128U, // SELNEZ + 128U, // SELNEZ64 + 128U, // SELNEZ_D + 128U, // SELNEZ_D_MMR6 + 128U, // SELNEZ_MMR6 + 128U, // SELNEZ_S + 128U, // SELNEZ_S_MMR6 + 184U, // SEL_D + 184U, // SEL_D_MMR6 + 184U, // SEL_S + 184U, // SEL_S_MMR6 + 128U, // SEQ + 128U, // SEQI_NM + 128U, // SEQi 0U, // SH 0U, // SH16_MM + 0U, // SH16_MMR6 + 0U, // SH16_NM 0U, // SH64 - 0U, // SHF_B - 0U, // SHF_H - 0U, // SHF_W + 0U, // SHE + 0U, // SHE_MM + 20U, // SHF_B + 20U, // SHF_H + 20U, // SHF_W + 0U, // SHGP_NM 0U, // SHILO 0U, // SHILOV - 0U, // SHLLV_PH - 0U, // SHLLV_QB - 0U, // SHLLV_S_PH - 0U, // SHLLV_S_W - 1U, // SHLL_PH - 1U, // SHLL_QB - 1U, // SHLL_S_PH - 1U, // SHLL_S_W - 0U, // SHRAV_PH - 0U, // SHRAV_QB - 0U, // SHRAV_R_PH - 0U, // SHRAV_R_QB - 0U, // SHRAV_R_W - 1U, // SHRA_PH - 1U, // SHRA_QB - 1U, // SHRA_R_PH - 1U, // SHRA_R_QB - 1U, // SHRA_R_W - 0U, // SHRLV_PH - 0U, // SHRLV_QB - 1U, // SHRL_PH - 1U, // SHRL_QB + 0U, // SHILOV_MM + 0U, // SHILO_MM + 128U, // SHLLV_PH + 128U, // SHLLV_PH_MM + 128U, // SHLLV_QB + 128U, // SHLLV_QB_MM + 128U, // SHLLV_S_PH + 128U, // SHLLV_S_PH_MM + 128U, // SHLLV_S_W + 128U, // SHLLV_S_W_MM + 164U, // SHLL_PH + 164U, // SHLL_PH_MM + 136U, // SHLL_QB + 136U, // SHLL_QB_MM + 164U, // SHLL_S_PH + 164U, // SHLL_S_PH_MM + 152U, // SHLL_S_W + 152U, // SHLL_S_W_MM + 128U, // SHRAV_PH + 128U, // SHRAV_PH_MM + 128U, // SHRAV_QB + 128U, // SHRAV_QB_MMR2 + 128U, // SHRAV_R_PH + 128U, // SHRAV_R_PH_MM + 128U, // SHRAV_R_QB + 128U, // SHRAV_R_QB_MMR2 + 128U, // SHRAV_R_W + 128U, // SHRAV_R_W_MM + 164U, // SHRA_PH + 164U, // SHRA_PH_MM + 136U, // SHRA_QB + 136U, // SHRA_QB_MMR2 + 164U, // SHRA_R_PH + 164U, // SHRA_R_PH_MM + 136U, // SHRA_R_QB + 136U, // SHRA_R_QB_MMR2 + 152U, // SHRA_R_W + 152U, // SHRA_R_W_MM + 128U, // SHRLV_PH + 128U, // SHRLV_PH_MMR2 + 128U, // SHRLV_QB + 128U, // SHRLV_QB_MM + 164U, // SHRL_PH + 164U, // SHRL_PH_MMR2 + 136U, // SHRL_QB + 136U, // SHRL_QB_MM + 0U, // SHXS_NM + 0U, // SHX_NM 0U, // SH_MM - 9U, // SLDI_B - 9U, // SLDI_D - 9U, // SLDI_H - 9U, // SLDI_W - 10U, // SLD_B - 10U, // SLD_D - 10U, // SLD_H - 10U, // SLD_W - 1U, // SLL - 0U, // SLL16_MM - 0U, // SLL64_32 - 0U, // SLL64_64 - 0U, // SLLI_B - 0U, // SLLI_D - 0U, // SLLI_H - 0U, // SLLI_W - 0U, // SLLV - 0U, // SLLV_MM - 0U, // SLL_B - 0U, // SLL_D - 0U, // SLL_H - 1U, // SLL_MM - 0U, // SLL_W - 0U, // SLT - 0U, // SLT64 - 0U, // SLT_MM - 0U, // SLTi - 0U, // SLTi64 - 0U, // SLTi_MM - 0U, // SLTiu - 0U, // SLTiu64 - 0U, // SLTiu_MM - 0U, // SLTu - 0U, // SLTu64 - 0U, // SLTu_MM - 0U, // SNE - 0U, // SNEi - 0U, // SNZ_B_PSEUDO - 0U, // SNZ_D_PSEUDO - 0U, // SNZ_H_PSEUDO - 0U, // SNZ_V_PSEUDO - 0U, // SNZ_W_PSEUDO - 8U, // SPLATI_B - 8U, // SPLATI_D - 8U, // SPLATI_H - 8U, // SPLATI_W - 8U, // SPLAT_B - 8U, // SPLAT_D - 8U, // SPLAT_H - 8U, // SPLAT_W - 1U, // SRA - 0U, // SRAI_B - 0U, // SRAI_D - 0U, // SRAI_H - 0U, // SRAI_W - 1U, // SRARI_B - 1U, // SRARI_D - 0U, // SRARI_H - 1U, // SRARI_W - 0U, // SRAR_B - 0U, // SRAR_D - 0U, // SRAR_H - 0U, // SRAR_W - 0U, // SRAV - 0U, // SRAV_MM - 0U, // SRA_B - 0U, // SRA_D - 0U, // SRA_H - 1U, // SRA_MM - 0U, // SRA_W - 1U, // SRL - 0U, // SRL16_MM - 0U, // SRLI_B - 0U, // SRLI_D - 0U, // SRLI_H - 0U, // SRLI_W - 1U, // SRLRI_B - 1U, // SRLRI_D - 0U, // SRLRI_H - 1U, // SRLRI_W - 0U, // SRLR_B - 0U, // SRLR_D - 0U, // SRLR_H - 0U, // SRLR_W - 0U, // SRLV - 0U, // SRLV_MM - 0U, // SRL_B - 0U, // SRL_D - 0U, // SRL_H - 1U, // SRL_MM - 0U, // SRL_W + 0U, // SH_MMR6 + 0U, // SH_NM + 0U, // SHs9_NM + 0U, // SIGRIE + 0U, // SIGRIE_MMR6 + 0U, // SIGRIE_NM + 305U, // SLDI_B + 85U, // SLDI_D + 297U, // SLDI_H + 89U, // SLDI_W + 313U, // SLD_B + 313U, // SLD_D + 313U, // SLD_H + 313U, // SLD_W + 152U, // SLL + 128U, // SLL16_MM + 128U, // SLL16_MMR6 + 164U, // SLL16_NM + 2U, // SLL64_32 + 2U, // SLL64_64 + 136U, // SLLI_B + 160U, // SLLI_D + 164U, // SLLI_H + 152U, // SLLI_W + 128U, // SLLV + 128U, // SLLV_MM + 128U, // SLLV_NM + 128U, // SLL_B + 128U, // SLL_D + 128U, // SLL_H + 152U, // SLL_MM + 152U, // SLL_MMR6 + 152U, // SLL_NM + 128U, // SLL_W + 128U, // SLT + 128U, // SLT64 + 128U, // SLTIU_NM + 128U, // SLTI_NM + 128U, // SLTU_NM + 128U, // SLT_MM + 128U, // SLT_NM + 128U, // SLTi + 128U, // SLTi64 + 128U, // SLTi_MM + 128U, // SLTiu + 128U, // SLTiu64 + 128U, // SLTiu_MM + 128U, // SLTu + 128U, // SLTu64 + 128U, // SLTu_MM + 128U, // SNE + 128U, // SNEi + 128U, // SOV_NM + 293U, // SPLATI_B + 321U, // SPLATI_D + 265U, // SPLATI_H + 285U, // SPLATI_W + 257U, // SPLAT_B + 257U, // SPLAT_D + 257U, // SPLAT_H + 257U, // SPLAT_W + 152U, // SRA + 136U, // SRAI_B + 160U, // SRAI_D + 164U, // SRAI_H + 152U, // SRAI_W + 136U, // SRARI_B + 160U, // SRARI_D + 164U, // SRARI_H + 152U, // SRARI_W + 128U, // SRAR_B + 128U, // SRAR_D + 128U, // SRAR_H + 128U, // SRAR_W + 128U, // SRAV + 128U, // SRAV_MM + 128U, // SRAV_NM + 128U, // SRA_B + 128U, // SRA_D + 128U, // SRA_H + 152U, // SRA_MM + 152U, // SRA_NM + 128U, // SRA_W + 152U, // SRL + 128U, // SRL16_MM + 128U, // SRL16_MMR6 + 164U, // SRL16_NM + 136U, // SRLI_B + 160U, // SRLI_D + 164U, // SRLI_H + 152U, // SRLI_W + 136U, // SRLRI_B + 160U, // SRLRI_D + 164U, // SRLRI_H + 152U, // SRLRI_W + 128U, // SRLR_B + 128U, // SRLR_D + 128U, // SRLR_H + 128U, // SRLR_W + 128U, // SRLV + 128U, // SRLV_MM + 128U, // SRLV_NM + 128U, // SRL_B + 128U, // SRL_D + 128U, // SRL_H + 152U, // SRL_MM + 152U, // SRL_NM + 128U, // SRL_W 0U, // SSNOP 0U, // SSNOP_MM - 0U, // STORE_ACC128 - 0U, // STORE_ACC64 - 0U, // STORE_ACC64DSP - 0U, // STORE_CCOND_DSP + 0U, // SSNOP_MMR6 0U, // ST_B 0U, // ST_D 0U, // ST_H 0U, // ST_W - 0U, // SUB - 0U, // SUBQH_PH - 0U, // SUBQH_R_PH - 0U, // SUBQH_R_W - 0U, // SUBQH_W - 0U, // SUBQ_PH - 0U, // SUBQ_S_PH - 0U, // SUBQ_S_W - 0U, // SUBSUS_U_B - 0U, // SUBSUS_U_D - 0U, // SUBSUS_U_H - 0U, // SUBSUS_U_W - 0U, // SUBSUU_S_B - 0U, // SUBSUU_S_D - 0U, // SUBSUU_S_H - 0U, // SUBSUU_S_W - 0U, // SUBS_S_B - 0U, // SUBS_S_D - 0U, // SUBS_S_H - 0U, // SUBS_S_W - 0U, // SUBS_U_B - 0U, // SUBS_U_D - 0U, // SUBS_U_H - 0U, // SUBS_U_W - 0U, // SUBU16_MM - 0U, // SUBUH_QB - 0U, // SUBUH_R_QB - 0U, // SUBU_PH - 0U, // SUBU_QB - 0U, // SUBU_S_PH - 0U, // SUBU_S_QB - 0U, // SUBVI_B - 0U, // SUBVI_D - 0U, // SUBVI_H - 0U, // SUBVI_W - 0U, // SUBV_B - 0U, // SUBV_D - 0U, // SUBV_H - 0U, // SUBV_W - 0U, // SUB_MM - 0U, // SUBu - 0U, // SUBu_MM - 0U, // SUXC1 - 0U, // SUXC164 - 0U, // SUXC1_MM + 128U, // SUB + 128U, // SUBQH_PH + 128U, // SUBQH_PH_MMR2 + 128U, // SUBQH_R_PH + 128U, // SUBQH_R_PH_MMR2 + 128U, // SUBQH_R_W + 128U, // SUBQH_R_W_MMR2 + 128U, // SUBQH_W + 128U, // SUBQH_W_MMR2 + 128U, // SUBQ_PH + 128U, // SUBQ_PH_MM + 128U, // SUBQ_S_PH + 128U, // SUBQ_S_PH_MM + 128U, // SUBQ_S_W + 128U, // SUBQ_S_W_MM + 128U, // SUBSUS_U_B + 128U, // SUBSUS_U_D + 128U, // SUBSUS_U_H + 128U, // SUBSUS_U_W + 128U, // SUBSUU_S_B + 128U, // SUBSUU_S_D + 128U, // SUBSUU_S_H + 128U, // SUBSUU_S_W + 128U, // SUBS_S_B + 128U, // SUBS_S_D + 128U, // SUBS_S_H + 128U, // SUBS_S_W + 128U, // SUBS_U_B + 128U, // SUBS_U_D + 128U, // SUBS_U_H + 128U, // SUBS_U_W + 128U, // SUBU16_MM + 128U, // SUBU16_MMR6 + 128U, // SUBUH_QB + 128U, // SUBUH_QB_MMR2 + 128U, // SUBUH_R_QB + 128U, // SUBUH_R_QB_MMR2 + 128U, // SUBU_MMR6 + 128U, // SUBU_PH + 128U, // SUBU_PH_MMR2 + 128U, // SUBU_QB + 128U, // SUBU_QB_MM + 128U, // SUBU_S_PH + 128U, // SUBU_S_PH_MMR2 + 128U, // SUBU_S_QB + 128U, // SUBU_S_QB_MM + 152U, // SUBVI_B + 152U, // SUBVI_D + 152U, // SUBVI_H + 152U, // SUBVI_W + 128U, // SUBV_B + 128U, // SUBV_D + 128U, // SUBV_H + 128U, // SUBV_W + 128U, // SUB_MM + 128U, // SUB_MMR6 + 128U, // SUB_NM + 128U, // SUBu + 128U, // SUBu16_NM + 128U, // SUBu_MM + 128U, // SUBu_NM + 1U, // SUXC1 + 1U, // SUXC164 + 1U, // SUXC1_MM 0U, // SW 0U, // SW16_MM + 0U, // SW16_MMR6 + 0U, // SW16_NM + 0U, // SW4x4_NM 0U, // SW64 0U, // SWC1 0U, // SWC1_MM 0U, // SWC2 + 0U, // SWC2_MMR6 0U, // SWC2_R6 0U, // SWC3 + 0U, // SWDSP + 0U, // SWDSP_MM + 0U, // SWE + 0U, // SWE_MM + 0U, // SWGP16_NM + 0U, // SWGP_NM 0U, // SWL 0U, // SWL64 + 0U, // SWLE + 0U, // SWLE_MM 0U, // SWL_MM 0U, // SWM16_MM + 0U, // SWM16_MMR6 0U, // SWM32_MM - 0U, // SWM_MM + 184U, // SWM_NM + 0U, // SWPC_NM 0U, // SWP_MM 0U, // SWR 0U, // SWR64 + 0U, // SWRE + 0U, // SWRE_MM 0U, // SWR_MM + 0U, // SWSP16_NM 0U, // SWSP_MM - 0U, // SWXC1 - 0U, // SWXC1_MM + 0U, // SWSP_MMR6 + 1U, // SWXC1 + 1U, // SWXC1_MM + 0U, // SWXS_NM + 0U, // SWX_NM 0U, // SW_MM + 0U, // SW_MMR6 + 0U, // SW_NM + 0U, // SWs9_NM 0U, // SYNC 0U, // SYNCI + 0U, // SYNCI_MM + 0U, // SYNCI_MMR6 + 0U, // SYNCI_NM + 0U, // SYNCIs9_NM 0U, // SYNC_MM + 0U, // SYNC_MMR6 + 0U, // SYNC_NM 0U, // SYSCALL + 0U, // SYSCALL16_NM 0U, // SYSCALL_MM - 0U, // SZ_B_PSEUDO - 0U, // SZ_D_PSEUDO - 0U, // SZ_H_PSEUDO - 0U, // SZ_V_PSEUDO - 0U, // SZ_W_PSEUDO + 0U, // SYSCALL_NM 0U, // Save16 0U, // SaveX16 0U, // SbRxRyOffMemX16 0U, // SebRx16 0U, // SehRx16 - 0U, // SelBeqZ - 0U, // SelBneZ - 0U, // SelTBteqZCmp - 0U, // SelTBteqZCmpi - 0U, // SelTBteqZSlt - 0U, // SelTBteqZSlti - 0U, // SelTBteqZSltiu - 0U, // SelTBteqZSltu - 0U, // SelTBtneZCmp - 0U, // SelTBtneZCmpi - 0U, // SelTBtneZSlt - 0U, // SelTBtneZSlti - 0U, // SelTBtneZSltiu - 0U, // SelTBtneZSltu 0U, // ShRxRyOffMemX16 - 1U, // SllX16 + 152U, // SllX16 0U, // SllvRxRy16 - 0U, // SltCCRxRy16 0U, // SltRxRy16 - 0U, // SltiCCRxImmX16 - 0U, // SltiRxImm16 + 1U, // SltiRxImm16 0U, // SltiRxImmX16 - 0U, // SltiuCCRxImmX16 - 0U, // SltiuRxImm16 + 1U, // SltiuRxImm16 0U, // SltiuRxImmX16 - 0U, // SltuCCRxRy16 0U, // SltuRxRy16 - 0U, // SltuRxRyRz16 - 1U, // SraX16 + 152U, // SraX16 0U, // SravRxRy16 - 1U, // SrlX16 + 152U, // SrlX16 0U, // SrlvRxRy16 - 0U, // SubuRxRyRz16 + 128U, // SubuRxRyRz16 0U, // SwRxRyOffMemX16 0U, // SwRxSpImmX16 - 0U, // TAILCALL - 0U, // TAILCALL64_R - 0U, // TAILCALL_R - 1U, // TEQ + 92U, // TEQ 0U, // TEQI 0U, // TEQI_MM - 1U, // TEQ_MM - 1U, // TGE + 164U, // TEQ_MM + 152U, // TEQ_NM + 92U, // TGE 0U, // TGEI 0U, // TGEIU 0U, // TGEIU_MM 0U, // TGEI_MM - 1U, // TGEU - 1U, // TGEU_MM - 1U, // TGE_MM + 92U, // TGEU + 164U, // TGEU_MM + 164U, // TGE_MM + 0U, // TLBGINV + 0U, // TLBGINVF + 0U, // TLBGINVF_MM + 0U, // TLBGINV_MM + 0U, // TLBGP + 0U, // TLBGP_MM + 0U, // TLBGR + 0U, // TLBGR_MM + 0U, // TLBGWI + 0U, // TLBGWI_MM + 0U, // TLBGWR + 0U, // TLBGWR_MM + 0U, // TLBINV + 0U, // TLBINVF + 0U, // TLBINVF_MMR6 + 0U, // TLBINVF_NM + 0U, // TLBINV_MMR6 + 0U, // TLBINV_NM 0U, // TLBP 0U, // TLBP_MM + 0U, // TLBP_NM 0U, // TLBR 0U, // TLBR_MM + 0U, // TLBR_NM 0U, // TLBWI 0U, // TLBWI_MM + 0U, // TLBWI_NM 0U, // TLBWR 0U, // TLBWR_MM - 1U, // TLT + 0U, // TLBWR_NM + 92U, // TLT 0U, // TLTI 0U, // TLTIU_MM 0U, // TLTI_MM - 1U, // TLTU - 1U, // TLTU_MM - 1U, // TLT_MM - 1U, // TNE + 92U, // TLTU + 164U, // TLTU_MM + 164U, // TLT_MM + 92U, // TNE 0U, // TNEI 0U, // TNEI_MM - 1U, // TNE_MM - 0U, // TRAP + 164U, // TNE_MM + 152U, // TNE_NM 0U, // TRUNC_L_D64 + 0U, // TRUNC_L_D_MMR6 0U, // TRUNC_L_S + 0U, // TRUNC_L_S_MMR6 0U, // TRUNC_W_D32 0U, // TRUNC_W_D64 + 0U, // TRUNC_W_D_MMR6 0U, // TRUNC_W_MM 0U, // TRUNC_W_S 0U, // TRUNC_W_S_MM + 0U, // TRUNC_W_S_MMR6 0U, // TTLTIU + 0U, // UALH_NM + 184U, // UALWM_NM + 0U, // UALW_NM + 0U, // UASH_NM + 184U, // UASWM_NM + 0U, // UASW_NM 0U, // UDIV 0U, // UDIV_MM - 0U, // V3MULU - 0U, // VMM0 - 0U, // VMULU - 2U, // VSHF_B - 2U, // VSHF_D - 2U, // VSHF_H - 2U, // VSHF_W + 128U, // V3MULU + 128U, // VMM0 + 128U, // VMULU + 184U, // VSHF_B + 184U, // VSHF_D + 184U, // VSHF_H + 184U, // VSHF_W 0U, // WAIT 0U, // WAIT_MM + 0U, // WAIT_MMR6 + 0U, // WAIT_NM 0U, // WRDSP + 0U, // WRDSP_MM + 0U, // WRPGPR_MMR6 + 0U, // WRPGPR_NM 0U, // WSBH 0U, // WSBH_MM - 0U, // XOR + 0U, // WSBH_MMR6 + 128U, // XOR 0U, // XOR16_MM - 0U, // XOR64 - 0U, // XORI_B - 0U, // XOR_MM - 0U, // XOR_V - 0U, // XOR_V_D_PSEUDO - 0U, // XOR_V_H_PSEUDO - 0U, // XOR_V_W_PSEUDO - 1U, // XORi - 1U, // XORi64 - 1U, // XORi_MM + 0U, // XOR16_MMR6 + 128U, // XOR16_NM + 128U, // XOR64 + 20U, // XORI_B + 16U, // XORI_MMR6 + 128U, // XORI_NM + 128U, // XOR_MM + 128U, // XOR_MMR6 + 128U, // XOR_NM + 128U, // XOR_V + 16U, // XORi + 16U, // XORi64 + 16U, // XORi_MM 0U, // XorRxRxRy16 - 0U + 0U, // YIELD + 0U, // YIELD_NM }; + // Emit the opcode for the instruction. + uint64_t Bits = 0; + Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0; + Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32; + MnemonicBitsInfo MBI = { #ifndef CAPSTONE_DIET - static const char AsmStrs[] = { - /* 0 */ 'j', 'a', 'l', 'r', 'c', 32, 9, 0, - /* 8 */ 'd', 'm', 'f', 'c', '0', 9, 0, - /* 15 */ 'd', 'm', 't', 'c', '0', 9, 0, - /* 22 */ 'v', 'm', 'm', '0', 9, 0, - /* 28 */ 'm', 't', 'm', '0', 9, 0, - /* 34 */ 'm', 't', 'p', '0', 9, 0, - /* 40 */ 'b', 'b', 'i', 't', '0', 9, 0, - /* 47 */ 'l', 'd', 'c', '1', 9, 0, - /* 53 */ 's', 'd', 'c', '1', 9, 0, - /* 59 */ 'c', 'f', 'c', '1', 9, 0, - /* 65 */ 'd', 'm', 'f', 'c', '1', 9, 0, - /* 72 */ 'm', 'f', 'h', 'c', '1', 9, 0, - /* 79 */ 'm', 't', 'h', 'c', '1', 9, 0, - /* 86 */ 'c', 't', 'c', '1', 9, 0, - /* 92 */ 'd', 'm', 't', 'c', '1', 9, 0, - /* 99 */ 'l', 'w', 'c', '1', 9, 0, - /* 105 */ 's', 'w', 'c', '1', 9, 0, - /* 111 */ 'l', 'd', 'x', 'c', '1', 9, 0, - /* 118 */ 's', 'd', 'x', 'c', '1', 9, 0, - /* 125 */ 'l', 'u', 'x', 'c', '1', 9, 0, - /* 132 */ 's', 'u', 'x', 'c', '1', 9, 0, - /* 139 */ 'l', 'w', 'x', 'c', '1', 9, 0, - /* 146 */ 's', 'w', 'x', 'c', '1', 9, 0, - /* 153 */ 'm', 't', 'm', '1', 9, 0, - /* 159 */ 'm', 't', 'p', '1', 9, 0, - /* 165 */ 'b', 'b', 'i', 't', '1', 9, 0, - /* 172 */ 'b', 'b', 'i', 't', '0', '3', '2', 9, 0, - /* 181 */ 'b', 'b', 'i', 't', '1', '3', '2', 9, 0, - /* 190 */ 'd', 's', 'r', 'a', '3', '2', 9, 0, - /* 198 */ 'b', 'p', 'o', 's', 'g', 'e', '3', '2', 9, 0, - /* 208 */ 'd', 's', 'l', 'l', '3', '2', 9, 0, - /* 216 */ 'd', 's', 'r', 'l', '3', '2', 9, 0, - /* 224 */ 'l', 'w', 'm', '3', '2', 9, 0, - /* 231 */ 's', 'w', 'm', '3', '2', 9, 0, - /* 238 */ 'd', 'r', 'o', 't', 'r', '3', '2', 9, 0, - /* 247 */ 'l', 'd', 'c', '2', 9, 0, - /* 253 */ 's', 'd', 'c', '2', 9, 0, - /* 259 */ 'd', 'm', 'f', 'c', '2', 9, 0, - /* 266 */ 'd', 'm', 't', 'c', '2', 9, 0, - /* 273 */ 'l', 'w', 'c', '2', 9, 0, - /* 279 */ 's', 'w', 'c', '2', 9, 0, - /* 285 */ 'm', 't', 'm', '2', 9, 0, - /* 291 */ 'm', 't', 'p', '2', 9, 0, - /* 297 */ 'a', 'd', 'd', 'i', 'u', 'r', '2', 9, 0, - /* 306 */ 'l', 'd', 'c', '3', 9, 0, - /* 312 */ 's', 'd', 'c', '3', 9, 0, - /* 318 */ 'l', 'w', 'c', '3', 9, 0, - /* 324 */ 's', 'w', 'c', '3', 9, 0, - /* 330 */ 'a', 'd', 'd', 'i', 'u', 's', '5', 9, 0, - /* 339 */ 's', 'b', '1', '6', 9, 0, - /* 345 */ 'a', 'n', 'd', '1', '6', 9, 0, - /* 352 */ 's', 'h', '1', '6', 9, 0, - /* 358 */ 'a', 'n', 'd', 'i', '1', '6', 9, 0, - /* 366 */ 'l', 'i', '1', '6', 9, 0, - /* 372 */ 'b', 'r', 'e', 'a', 'k', '1', '6', 9, 0, - /* 381 */ 's', 'l', 'l', '1', '6', 9, 0, - /* 388 */ 's', 'r', 'l', '1', '6', 9, 0, - /* 395 */ 'l', 'w', 'm', '1', '6', 9, 0, - /* 402 */ 's', 'w', 'm', '1', '6', 9, 0, - /* 409 */ 's', 'd', 'b', 'b', 'p', '1', '6', 9, 0, - /* 418 */ 'j', 'r', '1', '6', 9, 0, - /* 424 */ 'x', 'o', 'r', '1', '6', 9, 0, - /* 431 */ 'j', 'a', 'l', 'r', 's', '1', '6', 9, 0, - /* 440 */ 'n', 'o', 't', '1', '6', 9, 0, - /* 447 */ 'l', 'b', 'u', '1', '6', 9, 0, - /* 454 */ 's', 'u', 'b', 'u', '1', '6', 9, 0, - /* 462 */ 'a', 'd', 'd', 'u', '1', '6', 9, 0, - /* 470 */ 'l', 'h', 'u', '1', '6', 9, 0, - /* 477 */ 'l', 'w', '1', '6', 9, 0, - /* 483 */ 's', 'w', '1', '6', 9, 0, - /* 489 */ 'b', 'n', 'e', 'z', '1', '6', 9, 0, - /* 497 */ 'b', 'e', 'q', 'z', '1', '6', 9, 0, - /* 505 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0, - /* 521 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0, - /* 538 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0, - /* 554 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0, - /* 571 */ 'd', 's', 'r', 'a', 9, 0, - /* 577 */ 'd', 'l', 's', 'a', 9, 0, - /* 583 */ 'c', 'f', 'c', 'm', 's', 'a', 9, 0, - /* 591 */ 'c', 't', 'c', 'm', 's', 'a', 9, 0, - /* 599 */ 'a', 'd', 'd', '_', 'a', '.', 'b', 9, 0, - /* 608 */ 'm', 'i', 'n', '_', 'a', '.', 'b', 9, 0, - /* 617 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'b', 9, 0, - /* 627 */ 'm', 'a', 'x', '_', 'a', '.', 'b', 9, 0, - /* 636 */ 's', 'r', 'a', '.', 'b', 9, 0, - /* 643 */ 'n', 'l', 'o', 'c', '.', 'b', 9, 0, - /* 651 */ 'n', 'l', 'z', 'c', '.', 'b', 9, 0, - /* 659 */ 's', 'l', 'd', '.', 'b', 9, 0, - /* 666 */ 'p', 'c', 'k', 'o', 'd', '.', 'b', 9, 0, - /* 675 */ 'i', 'l', 'v', 'o', 'd', '.', 'b', 9, 0, - /* 684 */ 'i', 'n', 's', 'v', 'e', '.', 'b', 9, 0, - /* 693 */ 'v', 's', 'h', 'f', '.', 'b', 9, 0, - /* 701 */ 'b', 'n', 'e', 'g', '.', 'b', 9, 0, - /* 709 */ 's', 'r', 'a', 'i', '.', 'b', 9, 0, - /* 717 */ 's', 'l', 'd', 'i', '.', 'b', 9, 0, - /* 725 */ 'a', 'n', 'd', 'i', '.', 'b', 9, 0, - /* 733 */ 'b', 'n', 'e', 'g', 'i', '.', 'b', 9, 0, - /* 742 */ 'b', 's', 'e', 'l', 'i', '.', 'b', 9, 0, - /* 751 */ 's', 'l', 'l', 'i', '.', 'b', 9, 0, - /* 759 */ 's', 'r', 'l', 'i', '.', 'b', 9, 0, - /* 767 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'b', 9, 0, - /* 777 */ 'c', 'e', 'q', 'i', '.', 'b', 9, 0, - /* 785 */ 's', 'r', 'a', 'r', 'i', '.', 'b', 9, 0, - /* 794 */ 'b', 'c', 'l', 'r', 'i', '.', 'b', 9, 0, - /* 803 */ 's', 'r', 'l', 'r', 'i', '.', 'b', 9, 0, - /* 812 */ 'n', 'o', 'r', 'i', '.', 'b', 9, 0, - /* 820 */ 'x', 'o', 'r', 'i', '.', 'b', 9, 0, - /* 828 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'b', 9, 0, - /* 838 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'b', 9, 0, - /* 848 */ 'b', 's', 'e', 't', 'i', '.', 'b', 9, 0, - /* 857 */ 's', 'u', 'b', 'v', 'i', '.', 'b', 9, 0, - /* 866 */ 'a', 'd', 'd', 'v', 'i', '.', 'b', 9, 0, - /* 875 */ 'b', 'm', 'z', 'i', '.', 'b', 9, 0, - /* 883 */ 'b', 'm', 'n', 'z', 'i', '.', 'b', 9, 0, - /* 892 */ 'f', 'i', 'l', 'l', '.', 'b', 9, 0, - /* 900 */ 's', 'l', 'l', '.', 'b', 9, 0, - /* 907 */ 's', 'r', 'l', '.', 'b', 9, 0, - /* 914 */ 'b', 'i', 'n', 's', 'l', '.', 'b', 9, 0, - /* 923 */ 'i', 'l', 'v', 'l', '.', 'b', 9, 0, - /* 931 */ 'c', 'e', 'q', '.', 'b', 9, 0, - /* 938 */ 's', 'r', 'a', 'r', '.', 'b', 9, 0, - /* 946 */ 'b', 'c', 'l', 'r', '.', 'b', 9, 0, - /* 954 */ 's', 'r', 'l', 'r', '.', 'b', 9, 0, - /* 962 */ 'b', 'i', 'n', 's', 'r', '.', 'b', 9, 0, - /* 971 */ 'i', 'l', 'v', 'r', '.', 'b', 9, 0, - /* 979 */ 'a', 's', 'u', 'b', '_', 's', '.', 'b', 9, 0, - /* 989 */ 'm', 'o', 'd', '_', 's', '.', 'b', 9, 0, - /* 998 */ 'c', 'l', 'e', '_', 's', '.', 'b', 9, 0, - /* 1007 */ 'a', 'v', 'e', '_', 's', '.', 'b', 9, 0, - /* 1016 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'b', 9, 0, - /* 1026 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'b', 9, 0, - /* 1036 */ 'c', 'l', 't', 'i', '_', 's', '.', 'b', 9, 0, - /* 1046 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'b', 9, 0, - /* 1056 */ 'm', 'i', 'n', '_', 's', '.', 'b', 9, 0, - /* 1065 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'b', 9, 0, - /* 1075 */ 's', 'u', 'b', 's', '_', 's', '.', 'b', 9, 0, - /* 1085 */ 'a', 'd', 'd', 's', '_', 's', '.', 'b', 9, 0, - /* 1095 */ 's', 'a', 't', '_', 's', '.', 'b', 9, 0, - /* 1104 */ 'c', 'l', 't', '_', 's', '.', 'b', 9, 0, - /* 1113 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'b', 9, 0, - /* 1125 */ 'd', 'i', 'v', '_', 's', '.', 'b', 9, 0, - /* 1134 */ 'm', 'a', 'x', '_', 's', '.', 'b', 9, 0, - /* 1143 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'b', 9, 0, - /* 1153 */ 's', 'p', 'l', 'a', 't', '.', 'b', 9, 0, - /* 1162 */ 'b', 's', 'e', 't', '.', 'b', 9, 0, - /* 1170 */ 'p', 'c', 'n', 't', '.', 'b', 9, 0, - /* 1178 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'b', 9, 0, - /* 1188 */ 's', 't', '.', 'b', 9, 0, - /* 1194 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'b', 9, 0, - /* 1204 */ 'm', 'o', 'd', '_', 'u', '.', 'b', 9, 0, - /* 1213 */ 'c', 'l', 'e', '_', 'u', '.', 'b', 9, 0, - /* 1222 */ 'a', 'v', 'e', '_', 'u', '.', 'b', 9, 0, - /* 1231 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'b', 9, 0, - /* 1241 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'b', 9, 0, - /* 1251 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'b', 9, 0, - /* 1261 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'b', 9, 0, - /* 1271 */ 'm', 'i', 'n', '_', 'u', '.', 'b', 9, 0, - /* 1280 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'b', 9, 0, - /* 1290 */ 's', 'u', 'b', 's', '_', 'u', '.', 'b', 9, 0, - /* 1300 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'b', 9, 0, - /* 1310 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'b', 9, 0, - /* 1322 */ 's', 'a', 't', '_', 'u', '.', 'b', 9, 0, - /* 1331 */ 'c', 'l', 't', '_', 'u', '.', 'b', 9, 0, - /* 1340 */ 'd', 'i', 'v', '_', 'u', '.', 'b', 9, 0, - /* 1349 */ 'm', 'a', 'x', '_', 'u', '.', 'b', 9, 0, - /* 1358 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'b', 9, 0, - /* 1368 */ 'm', 's', 'u', 'b', 'v', '.', 'b', 9, 0, - /* 1377 */ 'm', 'a', 'd', 'd', 'v', '.', 'b', 9, 0, - /* 1386 */ 'p', 'c', 'k', 'e', 'v', '.', 'b', 9, 0, - /* 1395 */ 'i', 'l', 'v', 'e', 'v', '.', 'b', 9, 0, - /* 1404 */ 'm', 'u', 'l', 'v', '.', 'b', 9, 0, - /* 1412 */ 'b', 'z', '.', 'b', 9, 0, - /* 1418 */ 'b', 'n', 'z', '.', 'b', 9, 0, - /* 1425 */ 's', 'e', 'b', 9, 0, - /* 1430 */ 'j', 'r', '.', 'h', 'b', 9, 0, - /* 1437 */ 'j', 'a', 'l', 'r', '.', 'h', 'b', 9, 0, - /* 1446 */ 'l', 'b', 9, 0, - /* 1450 */ 's', 'h', 'r', 'a', '.', 'q', 'b', 9, 0, - /* 1459 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0, - /* 1473 */ 'c', 'm', 'p', 'g', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0, - /* 1486 */ 'c', 'm', 'p', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0, - /* 1498 */ 's', 'u', 'b', 'u', 'h', '.', 'q', 'b', 9, 0, - /* 1508 */ 'a', 'd', 'd', 'u', 'h', '.', 'q', 'b', 9, 0, - /* 1518 */ 'p', 'i', 'c', 'k', '.', 'q', 'b', 9, 0, - /* 1527 */ 's', 'h', 'l', 'l', '.', 'q', 'b', 9, 0, - /* 1536 */ 'r', 'e', 'p', 'l', '.', 'q', 'b', 9, 0, - /* 1545 */ 's', 'h', 'r', 'l', '.', 'q', 'b', 9, 0, - /* 1554 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0, - /* 1568 */ 'c', 'm', 'p', 'g', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0, - /* 1581 */ 'c', 'm', 'p', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0, - /* 1593 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'q', 'b', 9, 0, - /* 1604 */ 's', 'u', 'b', 'u', 'h', '_', 'r', '.', 'q', 'b', 9, 0, - /* 1616 */ 'a', 'd', 'd', 'u', 'h', '_', 'r', '.', 'q', 'b', 9, 0, - /* 1628 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'q', 'b', 9, 0, - /* 1640 */ 'a', 'b', 's', 'q', '_', 's', '.', 'q', 'b', 9, 0, - /* 1651 */ 's', 'u', 'b', 'u', '_', 's', '.', 'q', 'b', 9, 0, - /* 1662 */ 'a', 'd', 'd', 'u', '_', 's', '.', 'q', 'b', 9, 0, - /* 1673 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0, - /* 1687 */ 'c', 'm', 'p', 'g', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0, - /* 1700 */ 'c', 'm', 'p', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0, - /* 1712 */ 's', 'u', 'b', 'u', '.', 'q', 'b', 9, 0, - /* 1721 */ 'a', 'd', 'd', 'u', '.', 'q', 'b', 9, 0, - /* 1730 */ 's', 'h', 'r', 'a', 'v', '.', 'q', 'b', 9, 0, - /* 1740 */ 's', 'h', 'l', 'l', 'v', '.', 'q', 'b', 9, 0, - /* 1750 */ 'r', 'e', 'p', 'l', 'v', '.', 'q', 'b', 9, 0, - /* 1760 */ 's', 'h', 'r', 'l', 'v', '.', 'q', 'b', 9, 0, - /* 1770 */ 'r', 'a', 'd', 'd', 'u', '.', 'w', '.', 'q', 'b', 9, 0, - /* 1782 */ 's', 'b', 9, 0, - /* 1786 */ 'm', 'o', 'd', 's', 'u', 'b', 9, 0, - /* 1794 */ 'm', 's', 'u', 'b', 9, 0, - /* 1800 */ 'b', 'c', 9, 0, - /* 1804 */ 'b', 'g', 'e', 'c', 9, 0, - /* 1810 */ 'b', 'n', 'e', 'c', 9, 0, - /* 1816 */ 'j', 'i', 'c', 9, 0, - /* 1821 */ 'b', 'a', 'l', 'c', 9, 0, - /* 1827 */ 'j', 'i', 'a', 'l', 'c', 9, 0, - /* 1834 */ 'b', 'g', 'e', 'z', 'a', 'l', 'c', 9, 0, - /* 1843 */ 'b', 'l', 'e', 'z', 'a', 'l', 'c', 9, 0, - /* 1852 */ 'b', 'n', 'e', 'z', 'a', 'l', 'c', 9, 0, - /* 1861 */ 'b', 'e', 'q', 'z', 'a', 'l', 'c', 9, 0, - /* 1870 */ 'b', 'g', 't', 'z', 'a', 'l', 'c', 9, 0, - /* 1879 */ 'b', 'l', 't', 'z', 'a', 'l', 'c', 9, 0, - /* 1888 */ 'l', 'd', 'p', 'c', 9, 0, - /* 1894 */ 'a', 'u', 'i', 'p', 'c', 9, 0, - /* 1901 */ 'a', 'l', 'u', 'i', 'p', 'c', 9, 0, - /* 1909 */ 'a', 'd', 'd', 'i', 'u', 'p', 'c', 9, 0, - /* 1918 */ 'l', 'w', 'u', 'p', 'c', 9, 0, - /* 1925 */ 'l', 'w', 'p', 'c', 9, 0, - /* 1931 */ 'b', 'e', 'q', 'c', 9, 0, - /* 1937 */ 'j', 'r', 'c', 9, 0, - /* 1942 */ 'a', 'd', 'd', 's', 'c', 9, 0, - /* 1949 */ 'b', 'l', 't', 'c', 9, 0, - /* 1955 */ 'b', 'g', 'e', 'u', 'c', 9, 0, - /* 1962 */ 'b', 'l', 't', 'u', 'c', 9, 0, - /* 1969 */ 'b', 'n', 'v', 'c', 9, 0, - /* 1975 */ 'b', 'o', 'v', 'c', 9, 0, - /* 1981 */ 'a', 'd', 'd', 'w', 'c', 9, 0, - /* 1988 */ 'b', 'g', 'e', 'z', 'c', 9, 0, - /* 1995 */ 'b', 'l', 'e', 'z', 'c', 9, 0, - /* 2002 */ 'b', 'n', 'e', 'z', 'c', 9, 0, - /* 2009 */ 'b', 'e', 'q', 'z', 'c', 9, 0, - /* 2016 */ 'b', 'g', 't', 'z', 'c', 9, 0, - /* 2023 */ 'b', 'l', 't', 'z', 'c', 9, 0, - /* 2030 */ 'f', 'l', 'o', 'g', '2', '.', 'd', 9, 0, - /* 2039 */ 'f', 'e', 'x', 'p', '2', '.', 'd', 9, 0, - /* 2048 */ 'a', 'd', 'd', '_', 'a', '.', 'd', 9, 0, - /* 2057 */ 'f', 'm', 'i', 'n', '_', 'a', '.', 'd', 9, 0, - /* 2067 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'd', 9, 0, - /* 2077 */ 'f', 'm', 'a', 'x', '_', 'a', '.', 'd', 9, 0, - /* 2087 */ 'm', 'i', 'n', 'a', '.', 'd', 9, 0, - /* 2095 */ 's', 'r', 'a', '.', 'd', 9, 0, - /* 2102 */ 'm', 'a', 'x', 'a', '.', 'd', 9, 0, - /* 2110 */ 'f', 's', 'u', 'b', '.', 'd', 9, 0, - /* 2118 */ 'f', 'm', 's', 'u', 'b', '.', 'd', 9, 0, - /* 2127 */ 'n', 'm', 's', 'u', 'b', '.', 'd', 9, 0, - /* 2136 */ 'n', 'l', 'o', 'c', '.', 'd', 9, 0, - /* 2144 */ 'n', 'l', 'z', 'c', '.', 'd', 9, 0, - /* 2152 */ 'f', 'a', 'd', 'd', '.', 'd', 9, 0, - /* 2160 */ 'f', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, - /* 2169 */ 'n', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, - /* 2178 */ 's', 'l', 'd', '.', 'd', 9, 0, - /* 2185 */ 'p', 'c', 'k', 'o', 'd', '.', 'd', 9, 0, - /* 2194 */ 'i', 'l', 'v', 'o', 'd', '.', 'd', 9, 0, - /* 2203 */ 'c', '.', 'n', 'g', 'e', '.', 'd', 9, 0, - /* 2212 */ 'c', '.', 'l', 'e', '.', 'd', 9, 0, - /* 2220 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 'd', 9, 0, - /* 2230 */ 'f', 'c', 'l', 'e', '.', 'd', 9, 0, - /* 2238 */ 'c', '.', 'n', 'g', 'l', 'e', '.', 'd', 9, 0, - /* 2248 */ 'c', '.', 'o', 'l', 'e', '.', 'd', 9, 0, - /* 2257 */ 'c', 'm', 'p', '.', 's', 'l', 'e', '.', 'd', 9, 0, - /* 2268 */ 'f', 's', 'l', 'e', '.', 'd', 9, 0, - /* 2276 */ 'c', '.', 'u', 'l', 'e', '.', 'd', 9, 0, - /* 2285 */ 'c', 'm', 'p', '.', 'u', 'l', 'e', '.', 'd', 9, 0, - /* 2296 */ 'f', 'c', 'u', 'l', 'e', '.', 'd', 9, 0, - /* 2305 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 'e', '.', 'd', 9, 0, - /* 2317 */ 'f', 's', 'u', 'l', 'e', '.', 'd', 9, 0, - /* 2326 */ 'f', 'c', 'n', 'e', '.', 'd', 9, 0, - /* 2334 */ 'f', 's', 'n', 'e', '.', 'd', 9, 0, - /* 2342 */ 'f', 'c', 'u', 'n', 'e', '.', 'd', 9, 0, - /* 2351 */ 'f', 's', 'u', 'n', 'e', '.', 'd', 9, 0, - /* 2360 */ 'i', 'n', 's', 'v', 'e', '.', 'd', 9, 0, - /* 2369 */ 'c', '.', 'f', '.', 'd', 9, 0, - /* 2376 */ 'c', 'm', 'p', '.', 'a', 'f', '.', 'd', 9, 0, - /* 2386 */ 'f', 'c', 'a', 'f', '.', 'd', 9, 0, - /* 2394 */ 'c', 'm', 'p', '.', 's', 'a', 'f', '.', 'd', 9, 0, - /* 2405 */ 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6896 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 't', '.', 's', 9, 0, - /* 6908 */ 'r', 'i', 'n', 't', '.', 's', 9, 0, - /* 6916 */ 's', 'q', 'r', 't', '.', 's', 9, 0, - /* 6924 */ 'm', 'o', 'v', 't', '.', 's', 9, 0, - /* 6932 */ 'd', 'i', 'v', '.', 's', 9, 0, - /* 6939 */ 'm', 'o', 'v', '.', 's', 9, 0, - /* 6946 */ 't', 'r', 'u', 'n', 'c', '.', 'w', '.', 's', 9, 0, - /* 6957 */ 'r', 'o', 'u', 'n', 'd', '.', 'w', '.', 's', 9, 0, - /* 6968 */ 'c', 'e', 'i', 'l', '.', 'w', '.', 's', 9, 0, - /* 6978 */ 'f', 'l', 'o', 'o', 'r', '.', 'w', '.', 's', 9, 0, - /* 6989 */ 'c', 'v', 't', '.', 'w', '.', 's', 9, 0, - /* 6998 */ 'm', 'a', 'x', '.', 's', 9, 0, - /* 7005 */ 's', 'e', 'l', 'n', 'e', 'z', '.', 's', 9, 0, - /* 7015 */ 's', 'e', 'l', 'e', 'q', 'z', '.', 's', 9, 0, - /* 7025 */ 'm', 'o', 'v', 'z', '.', 's', 9, 0, - /* 7033 */ 'j', 'a', 'l', 's', 9, 0, - /* 7039 */ 'b', 'g', 'e', 'z', 'a', 'l', 's', 9, 0, - /* 7048 */ 'b', 'l', 't', 'z', 'a', 'l', 's', 9, 0, - /* 7057 */ 'j', 'a', 'l', 'r', 's', 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'u', 'b', 's', 'u', 'u', '_', 's', '.', 'w', 9, 0, - /* 8557 */ 'd', 'i', 'v', '_', 's', '.', 'w', 9, 0, - /* 8566 */ 's', 'h', 'l', 'l', 'v', '_', 's', '.', 'w', 9, 0, - /* 8577 */ 'm', 'a', 'x', '_', 's', '.', 'w', 9, 0, - /* 8586 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'w', 9, 0, - /* 8596 */ 'm', 'u', 'l', 'q', '_', 'r', 's', '.', 'w', 9, 0, - /* 8607 */ 'e', 'x', 't', 'r', '_', 'r', 's', '.', 'w', 9, 0, - /* 8618 */ 'e', 'x', 't', 'r', 'v', '_', 'r', 's', '.', 'w', 9, 0, - /* 8630 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'w', 9, 0, - /* 8640 */ 's', 'p', 'l', 'a', 't', '.', 'w', 9, 0, - /* 8649 */ 'b', 's', 'e', 't', '.', 'w', 9, 0, - /* 8657 */ 'f', 'c', 'l', 't', '.', 'w', 9, 0, - /* 8665 */ 'f', 's', 'l', 't', '.', 'w', 9, 0, - /* 8673 */ 'f', 'c', 'u', 'l', 't', '.', 'w', 9, 0, - /* 8682 */ 'f', 's', 'u', 'l', 't', '.', 'w', 9, 0, - /* 8691 */ 'p', 'c', 'n', 't', '.', 'w', 9, 0, - /* 8699 */ 'f', 'r', 'i', 'n', 't', '.', 'w', 9, 0, - /* 8708 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'w', 9, 0, - /* 8718 */ 'f', 's', 'q', 'r', 't', '.', 'w', 9, 0, - /* 8727 */ 'f', 'r', 's', 'q', 'r', 't', '.', 'w', 9, 0, - /* 8737 */ 's', 't', '.', 'w', 9, 0, - /* 8743 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, - /* 8753 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, - /* 8763 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, - /* 8774 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 'u', '.', 'w', 9, 0, - /* 8786 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0, - /* 8796 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0, - /* 8807 */ 'm', 'o', 'd', '_', 'u', '.', 'w', 9, 0, - /* 8816 */ 'c', 'l', 'e', '_', 'u', '.', 'w', 9, 0, - /* 8825 */ 'a', 'v', 'e', '_', 'u', '.', 'w', 9, 0, - /* 8834 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'w', 9, 0, - /* 8844 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'w', 9, 0, - /* 8854 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'w', 9, 0, - /* 8864 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'w', 9, 0, - /* 8874 */ 'm', 'i', 'n', '_', 'u', '.', 'w', 9, 0, - /* 8883 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'w', 9, 0, - /* 8893 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'w', 9, 0, - /* 8903 */ 's', 'u', 'b', 's', '_', 'u', '.', 'w', 9, 0, - /* 8913 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'w', 9, 0, - /* 8923 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'w', 9, 0, - /* 8935 */ 's', 'a', 't', '_', 'u', '.', 'w', 9, 0, - /* 8944 */ 'c', 'l', 't', '_', 'u', '.', 'w', 9, 0, - /* 8953 */ 'f', 'f', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0, - /* 8964 */ 'f', 't', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0, - /* 8975 */ 'd', 'i', 'v', '_', 'u', '.', 'w', 9, 0, - /* 8984 */ 'm', 'a', 'x', '_', 'u', '.', 'w', 9, 0, - /* 8993 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'w', 9, 0, - /* 9003 */ 'm', 's', 'u', 'b', 'v', '.', 'w', 9, 0, - /* 9012 */ 'm', 'a', 'd', 'd', 'v', '.', 'w', 9, 0, - /* 9021 */ 'p', 'c', 'k', 'e', 'v', '.', 'w', 9, 0, - /* 9030 */ 'i', 'l', 'v', 'e', 'v', '.', 'w', 9, 0, - /* 9039 */ 'f', 'd', 'i', 'v', '.', 'w', 9, 0, - /* 9047 */ 'm', 'u', 'l', 'v', '.', 'w', 9, 0, - /* 9055 */ 'e', 'x', 't', 'r', 'v', '.', 'w', 9, 0, - /* 9064 */ 'f', 'm', 'a', 'x', '.', 'w', 9, 0, - /* 9072 */ 'b', 'z', '.', 'w', 9, 0, - /* 9078 */ 'b', 'n', 'z', '.', 'w', 9, 0, - /* 9085 */ 'l', 'w', 9, 0, - /* 9089 */ 's', 'w', 9, 0, - /* 9093 */ 'l', 'h', 'x', 9, 0, - /* 9098 */ 'j', 'a', 'l', 'x', 9, 0, - /* 9104 */ 'l', 'b', 'u', 'x', 9, 0, - /* 9110 */ 'l', 'w', 'x', 9, 0, - /* 9115 */ 'b', 'g', 'e', 'z', 9, 0, - /* 9121 */ 'b', 'l', 'e', 'z', 9, 0, - /* 9127 */ 'b', 'n', 'e', 'z', 9, 0, - /* 9133 */ 's', 'e', 'l', 'n', 'e', 'z', 9, 0, - /* 9141 */ 'b', 't', 'n', 'e', 'z', 9, 0, - /* 9148 */ 'd', 'c', 'l', 'z', 9, 0, - /* 9154 */ 'b', 'e', 'q', 'z', 9, 0, - /* 9160 */ 's', 'e', 'l', 'e', 'q', 'z', 9, 0, - /* 9168 */ 'b', 't', 'e', 'q', 'z', 9, 0, - /* 9175 */ 'b', 'g', 't', 'z', 9, 0, - /* 9181 */ 'b', 'l', 't', 'z', 9, 0, - /* 9187 */ 'm', 'o', 'v', 'z', 9, 0, - /* 9193 */ 's', 'e', 'b', 9, 32, 0, - /* 9199 */ 'j', 'r', 'c', 9, 32, 0, - /* 9205 */ 's', 'e', 'h', 9, 32, 0, - /* 9211 */ 'd', 'd', 'i', 'v', 'u', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0, - /* 9225 */ 'd', 'd', 'i', 'v', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0, - /* 9238 */ 'a', 'd', 'd', 'i', 'u', 9, '$', 's', 'p', ',', 32, 0, - /* 9250 */ 'c', 'i', 'n', 's', '3', '2', 32, 0, - /* 9258 */ 'e', 'x', 't', 's', '3', '2', 32, 0, - /* 9266 */ 's', 'y', 'n', 'c', 32, 0, - /* 9272 */ 9, '.', 'w', 'o', 'r', 'd', 32, 0, - /* 9280 */ 'd', 'i', 'n', 's', 'm', 32, 0, - /* 9287 */ 'd', 'e', 'x', 't', 'm', 32, 0, - /* 9294 */ 'c', 'i', 'n', 's', 32, 0, - /* 9300 */ 'd', 'i', 'n', 's', 32, 0, - /* 9306 */ 'e', 'x', 't', 's', 32, 0, - /* 9312 */ 'd', 'e', 'x', 't', 32, 0, - /* 9318 */ 'd', 'i', 'n', 's', 'u', 32, 0, - /* 9325 */ 'd', 'e', 'x', 't', 'u', 32, 0, - /* 9332 */ 'b', 'c', '1', 'n', 'e', 'z', 32, 0, - /* 9340 */ 'b', 'c', '2', 'n', 'e', 'z', 32, 0, - /* 9348 */ 'b', 'c', '1', 'e', 'q', 'z', 32, 0, - /* 9356 */ 'b', 'c', '2', 'e', 'q', 'z', 32, 0, - /* 9364 */ 'c', '.', 0, - /* 9367 */ 'b', 'r', 'e', 'a', 'k', 32, '0', 0, - /* 9375 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, - /* 9388 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, - /* 9395 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, - /* 9405 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, - /* 9420 */ 'j', 'r', 'c', 9, 32, '$', 'r', 'a', 0, - /* 9429 */ 'j', 'r', 9, 32, '$', 'r', 'a', 0, - /* 9437 */ 'e', 'h', 'b', 0, - /* 9441 */ 'p', 'a', 'u', 's', 'e', 0, - /* 9447 */ 't', 'l', 'b', 'w', 'i', 0, - /* 9453 */ 'f', 'o', 'o', 0, - /* 9457 */ 't', 'l', 'b', 'p', 0, - /* 9462 */ 's', 's', 'n', 'o', 'p', 0, - /* 9468 */ 't', 'l', 'b', 'r', 0, - /* 9473 */ 't', 'l', 'b', 'w', 'r', 0, - /* 9479 */ 'd', 'e', 'r', 'e', 't', 0, - /* 9485 */ 'w', 'a', 'i', 't', 0, + AsmStrs+(Bits & 16383)-1, +#else + NULL, +#endif // CAPSTONE_DIET + Bits }; -#endif + return MBI; +} - // Emit the opcode for the instruction. - uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)]; - uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)]; - uint64_t Bits = (Bits2 << 32) | Bits1; - // assert(Bits != 0 && "Cannot print this instruction."); -#ifndef CAPSTONE_DIET - SStream_concat0(O, AsmStrs+(Bits & 16383)-1); -#endif +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) { + SStream_concat0(O, ""); + MnemonicBitsInfo MnemonicInfo = getMnemonic(MI, O); + SStream_concat0(O, MnemonicInfo.first); - // Fragment 0 encoded into 4 bits for 11 unique commands. - //printf("Frag-0: %"PRIu64"\n", (Bits >> 14) & 15); - switch ((uint32_t)((Bits >> 14) & 15)) { - default: // llvm_unreachable("Invalid command number."); + uint64_t Bits = MnemonicInfo.second; + assert(Bits != 0 && "Cannot print this instruction."); + + // Fragment 0 encoded into 5 bits for 20 unique commands. + switch ((Bits >> 14) & 31) { + default: assert(0 && "Invalid command number."); case 0: - // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, Break16, CONSTPOOL_EN... + // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... return; break; case 1: - // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... - printOperand(MI, 0, O); + // ABSMacro, ALIGN_NM, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro... + printOperand(MI, 0, O); break; case 2: - // ADDIUS5_MM, CTC1, CTC1_MM, DAHI, DATI, DMTC1, MTC1, MTC1_MM, MTHI_DSP,... - printOperand(MI, 1, O); - SStream_concat0(O, ", "); + // B_MMR6_Pseudo, B_MM_Pseudo, B16_MM, BAL, BALC, BALC_MMR6, BC, BC16_MMR... + printBranchOperand(MI, Address, 0, O); break; case 3: - // AND16_MM, MTHC1_D32, MTHC1_D64, MTHC1_MM, OR16_MM, XOR16_MM - printOperand(MI, 2, O); - SStream_concat0(O, ", "); + // CTTC1, MTTACX, MTTACX_NM, MTTC0, MTTC0_NM, MTTC1, MTTGPR, MTTGPR_NM, M... + printOperand(MI, 1, O); + SStream_concat0(O, ", "); break; case 4: - // BREAK16_MM, SDBBP16_MM - printUnsignedImm8(MI, 0, O); + // LWM_MM, SWM_MM, LWM16_MM, LWM16_MMR6, LWM32_MM, SWM16_MM, SWM16_MMR6, ... + printRegisterList(MI, 0, O); + SStream_concat0(O, ", "); + printMemOperand(MI, 1, O); return; break; case 5: - // CACHE, CACHE_MM, CACHE_R6, PREF, PREF_MM, PREF_R6 - printUnsignedImm(MI, 2, O); - SStream_concat0(O, ", "); - printMemOperand(MI, 0, O); - return; + // SelBeqZ, SelBneZ, SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZ... + printOperand(MI, 3, O); break; case 6: - // FCMP_D32, FCMP_D32_MM, FCMP_D64, FCMP_S32, FCMP_S32_MM - printFCCOperand(MI, 2, O); + // AND16_MM, AND16_MMR6, LSA_MMR6, MTHC1_D32, MTHC1_D32_MM, MTHC1_D64, MT... + printOperand(MI, 2, O); + SStream_concat0(O, ", "); break; case 7: - // LWM16_MM, LWM32_MM, LWM_MM, MOVEP_MM, SWM16_MM, SWM32_MM, SWM_MM - printRegisterList(MI, 0, O); - SStream_concat0(O, ", "); + // BALC16_NM, BALC_NM + printPCRel(MI, Address, 0, O); + return; break; case 8: - // LWP_MM, SWP_MM - printRegisterPair(MI, 0, O); - SStream_concat0(O, ", "); - printMemOperand(MI, 2, O); - return; + // BREAK, BREAK_MM, BREAK_MMR6, HYPCALL, HYPCALL_MM, SDBBP_MM, SYSCALL_MM... + printUImm_10_0(MI, 0, O); break; case 9: - // SYNCI - printMemOperand(MI, 0, O); + // BREAK16_MM, BREAK16_MMR6, SDBBP16_MM, SDBBP16_MMR6 + printUImm_4_0(MI, 0, O); return; break; case 10: - // SelBeqZ, SelBneZ, SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZ... - printOperand(MI, 3, O); + // CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,... + printUImm_5_0(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 11: + // CACHE_NM, PREF_NM, PREFs9_NM, SYNC, SYNC_MM, SYNC_MMR6, SYNC_NM + printUImm_5_0(MI, 0, O); + break; + case 12: + // FCMP_D32, FCMP_D32_MM, FCMP_D64, FCMP_S32, FCMP_S32_MM + printFCCOperand(MI, 2, O); + break; + case 13: + // J, JAL, JALS_MM, JALX, JALX_MM, JAL_MM, J_MM + printJumpOperand(MI, 0, O); + return; + break; + case 14: + // Jal16, JalB16 + printUImm_26_0(MI, 0, O); + break; + case 15: + // RESTOREJRC16_NM, SAVE16_NM + printUImm_8_0(MI, 0, O); + printNanoMipsRegisterList(MI, 1, O); + return; + break; + case 16: + // RESTOREJRC_NM, RESTORE_NM, SAVE_NM + printUImm_12_0(MI, 0, O); + printNanoMipsRegisterList(MI, 1, O); + return; + break; + case 17: + // SDBBP, SDBBP_MMR6, SDBBP_R6, SYSCALL + printUImm_20_0(MI, 0, O); + return; + break; + case 18: + // SIGRIE, SIGRIE_MMR6 + printUImm_16_0(MI, 0, O); + return; + break; + case 19: + // SYNCI, SYNCI_MM, SYNCI_MMR6, SYNCI_NM, SYNCIs9_NM + printMemOperand(MI, 0, O); + return; break; } - // Fragment 1 encoded into 5 bits for 17 unique commands. - //printf("Frag-1: %"PRIu64"\n", (Bits >> 18) & 31); - switch ((uint32_t)((Bits >> 18) & 31)) { - default: // llvm_unreachable("Invalid command number."); + // Fragment 1 encoded into 5 bits for 18 unique commands. + switch ((Bits >> 19) & 31) { + default: assert(0 && "Invalid command number."); case 0: - // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... - SStream_concat0(O, ", "); + // ABSMacro, ALIGN_NM, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro... + SStream_concat0(O, ", "); break; case 1: - // ADDIUS5_MM, DAHI, DATI, MOVEP_MM, MultRxRyRz16, MultuRxRyRz16, SltCCRx... - printOperand(MI, 2, O); + // B_MMR6_Pseudo, B_MM_Pseudo, Constant32, JalOneReg, MFTDSP, MFTDSP_NM, ... + return; break; case 2: - // ADDIUSP_MM, AddiuSpImmX16, B16_MM, BAL, BALC, BC, BPOSGE32, B_MM_Pseud... - return; + // CTTC1, MTTACX, MTTACX_NM, MTTC0, MTTC0_NM, MTTC1, MTTGPR, MTTGPR_NM, M... + printOperand(MI, 0, O); break; case 3: - // AND16_MM, OR16_MM, XOR16_MM - printOperand(MI, 1, O); + // LwConstant32 + SStream_concat0(O, ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t"); + printOperand(MI, 1, O); + SStream_concat0(O, "\n2:"); return; break; case 4: - // AddiuRxPcImmX16 - SStream_concat0(O, ", $pc, "); - printOperand(MI, 1, O); - return; + // MultRxRyRz16, MultuRxRyRz16, SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImm... + printOperand(MI, 2, O); break; case 5: - // AddiuSpImm16, Bimm16 - SStream_concat0(O, " # 16 bit inst"); + // SelBeqZ, SelBneZ + SStream_concat0(O, ", .+4\n\t\n\tmove "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); return; break; case 6: - // Bteqz16, Btnez16 - SStream_concat0(O, " # 16 bit inst"); - return; + // AND16_MM, AND16_MMR6, LSA_MMR6, OR16_MM, OR16_MMR6, PREFX_MM, XOR16_MM... + printOperand(MI, 1, O); break; case 7: - // CTC1, CTC1_MM, DMTC1, MTC1, MTC1_MM, MTHC1_D32, MTHC1_D64, MTHC1_MM, M... - printOperand(MI, 0, O); + // AddiuRxPcImmX16 + SStream_concat0(O, ", $pc, "); + printOperand(MI, 1, O); return; break; case 8: - // FCMP_D32, FCMP_D32_MM, FCMP_D64 - SStream_concat0(O, ".d\t"); - printOperand(MI, 0, O); - SStream_concat0(O, ", "); - printOperand(MI, 1, O); + // AddiuSpImm16, Bimm16 + SStream_concat0(O, " # 16 bit inst"); return; break; case 9: - // FCMP_S32, FCMP_S32_MM - SStream_concat0(O, ".s\t"); - printOperand(MI, 0, O); - SStream_concat0(O, ", "); - printOperand(MI, 1, O); + // Bteqz16, Btnez16 + SStream_concat0(O, " # 16 bit inst"); return; break; case 10: - // INSERT_B, INSERT_D, INSERT_H, INSERT_W, INSVE_B, INSVE_D, INSVE_H, INS... - SStream_concat0(O, "["); + // CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,... + printMemOperand(MI, 0, O); + return; break; case 11: - // Jal16 - SStream_concat0(O, "\n\tnop"); + // FCMP_D32, FCMP_D32_MM, FCMP_D64 + SStream_concat0(O, ".d\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); return; break; case 12: - // JalB16 - SStream_concat0(O, "\t# branch\n\tnop"); + // FCMP_S32, FCMP_S32_MM + SStream_concat0(O, ".s\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); return; break; case 13: - // LWM16_MM, LWM32_MM, LWM_MM, SWM16_MM, SWM32_MM, SWM_MM - printMemOperand(MI, 1, O); - return; + // INSERT_B, INSERT_D, INSERT_H, INSERT_W, INSVE_B, INSVE_D, INSVE_H, INS... + SStream_concat1(O, '['); break; case 14: - // LwConstant32 - SStream_concat0(O, ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t"); - printOperand(MI, 1, O); - SStream_concat0(O, "\n2:"); + // Jal16 + SStream_concat0(O, "\n\tnop"); return; break; case 15: - // SC, SCD, SCD_R6, SC_MM, SC_R6 - printMemOperand(MI, 2, O); + // JalB16 + SStream_concat0(O, "\t# branch\n\tnop"); return; break; case 16: - // SelBeqZ, SelBneZ - SStream_concat0(O, ", .+4\n\t\n\tmove "); - printOperand(MI, 1, O); - SStream_concat0(O, ", "); - printOperand(MI, 2, O); + // SAA, SAAD + SStream_concat0(O, ", ("); + printOperand(MI, 1, O); + SStream_concat1(O, ')'); + return; + break; + case 17: + // SC, SC64, SC64_R6, SCD, SCD_R6, SCE, SCE_MM, SC_MM, SC_MMR6, SC_NM, SC... + printMemOperand(MI, 2, O); return; break; } - // Fragment 2 encoded into 4 bits for 12 unique commands. - //printf("Frag-2: %"PRIu64"\n", (Bits >> 23) & 15); - switch ((uint32_t)((Bits >> 23) & 15)) { - default: // llvm_unreachable("Invalid command number."); + // Fragment 2 encoded into 5 bits for 30 unique commands. + switch ((Bits >> 24) & 31) { + default: assert(0 && "Invalid command number."); case 0: - // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... - printOperand(MI, 1, O); + // ABSMacro, ALIGN_NM, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro... + printOperand(MI, 1, O); break; case 1: - // ADDIUS5_MM, DAHI, DATI + // CTTC1, MTTACX, MTTACX_NM, MTTC1, MTTGPR, MTTGPR_NM, MTTHC1, MTTHI, MTT... return; break; case 2: - // AddiuRxRxImm16, AddiuRxRxImmX16, AndRxRxRy16, BINSLI_B, BINSLI_D, BINS... - printOperand(MI, 2, O); + // GotPrologue16, AddiuRxRxImm16, AddiuRxRxImmX16, AndRxRxRy16, BINSLI_B,... + printOperand(MI, 2, O); break; case 3: - // AddiuRxRyOffMemX16, LEA_ADDiu, LEA_ADDiu64, LEA_ADDiu_MM - printMemOperandEA(MI, 1, O); - return; + // LDMacro, LOAD_ACC128, LOAD_ACC64, LOAD_ACC64DSP, LOAD_CCOND_DSP, LoadA... + printMemOperand(MI, 1, O); break; case 4: - // BBIT0, BBIT032, BBIT1, BBIT132, LUi, LUi64, LUi_MM, LoadAddr32Imm, Loa... - printUnsignedImm(MI, 1, O); + // MTTC0, MTTC0_NM, DMTC0, DMTC2, DMTGC0, FORK, FORK_NM, LSA_MMR6, MTC0, ... + SStream_concat0(O, ", "); break; case 5: - // INSERT_B, INSERT_D, INSERT_H, INSERT_W - printUnsignedImm(MI, 3, O); - SStream_concat0(O, "], "); - printOperand(MI, 2, O); + // MultRxRyRz16, MultuRxRyRz16 + SStream_concat0(O, "\n\tmflo\t"); + printOperand(MI, 0, O); return; break; case 6: - // INSVE_B, INSVE_D, INSVE_H, INSVE_W - printUnsignedImm(MI, 2, O); - SStream_concat0(O, "], "); - printOperand(MI, 3, O); - SStream_concat0(O, "["); - printUnsignedImm(MI, 4, O); - SStream_concat0(O, "]"); + // PseudoLA_NM, PseudoLI_NM, LI48_NM + printUImm_32_0(MI, 1, O); return; break; case 7: - // LB, LB64, LBU16_MM, LB_MM, LBu, LBu64, LBu_MM, LD, LDC1, LDC164, LDC1_... - printMemOperand(MI, 1, O); - return; + // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... + printOperand(MI, 4, O); break; case 8: - // MOVEP_MM - SStream_concat0(O, ", "); - printOperand(MI, 3, O); + // SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16, SltuRxRyRz... + SStream_concat0(O, "\n\tmove\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", $t8"); return; break; case 9: - // MultRxRyRz16, MultuRxRyRz16 - SStream_concat0(O, "\n\tmflo\t"); - printOperand(MI, 0, O); + // ALUIPC_NM + printHi20PCRel(MI, Address, 1, O); return; break; case 10: - // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... - printOperand(MI, 4, O); + // AddiuRxRyOffMemX16, LEA_ADDIU_NM, LEA_ADDiu, LEA_ADDiu64, LEA_ADDiu_MM + printMemOperandEA(MI, 1, O); + return; break; case 11: - // SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16, SltuRxRyRz... - SStream_concat0(O, "\n\tmove\t"); - printOperand(MI, 0, O); - SStream_concat0(O, ", $t8"); + // BBIT0, BBIT032, BBIT1, BBIT132 + printUImm_5_0(MI, 1, O); + SStream_concat0(O, ", "); + printBranchOperand(MI, Address, 2, O); + return; + break; + case 12: + // BC1EQZ, BC1EQZC_MMR6, BC1F, BC1FL, BC1F_MM, BC1NEZ, BC1NEZC_MMR6, BC1T... + printBranchOperand(MI, Address, 1, O); + break; + case 13: + // BEQIC_NM, BGEIC_NM, BGEIUC_NM, BLTIC_NM, BLTIUC_NM, BNEIC_NM, LI16_NM,... + printUImm_7_0(MI, 1, O); + break; + case 14: + // BREAK, BREAK_MM, BREAK_MMR6, RDDSP, WRDSP + printUImm_10_0(MI, 1, O); + return; + break; + case 15: + // DMFC2_OCTEON, DMTC2_OCTEON, LUI_MMR6, LUi, LUi64, LUi_MM + printUImm_16_0(MI, 1, O); + return; + break; + case 16: + // GINVT, GINVT_MMR6, GINVT_NM + printUImm_2_0(MI, 1, O); + return; + break; + case 17: + // INSERT_B + printUImm_4_0(MI, 3, O); + SStream_concat0(O, "], "); + printOperand(MI, 2, O); + return; + break; + case 18: + // INSERT_D + printUImm_1_0(MI, 3, O); + SStream_concat0(O, "], "); + printOperand(MI, 2, O); + return; + break; + case 19: + // INSERT_H + printUImm_3_0(MI, 3, O); + SStream_concat0(O, "], "); + printOperand(MI, 2, O); + return; + break; + case 20: + // INSERT_W + printUImm_2_0(MI, 3, O); + SStream_concat0(O, "], "); + printOperand(MI, 2, O); + return; + break; + case 21: + // INSVE_B + printUImm_4_0(MI, 2, O); + SStream_concat0(O, "], "); + printOperand(MI, 3, O); + SStream_concat1(O, '['); + printUImm_0_0(MI, 4, O); + SStream_concat1(O, ']'); + return; + break; + case 22: + // INSVE_D + printUImm_1_0(MI, 2, O); + SStream_concat0(O, "], "); + printOperand(MI, 3, O); + SStream_concat1(O, '['); + printUImm_0_0(MI, 4, O); + SStream_concat1(O, ']'); + return; + break; + case 23: + // INSVE_H + printUImm_3_0(MI, 2, O); + SStream_concat0(O, "], "); + printOperand(MI, 3, O); + SStream_concat1(O, '['); + printUImm_0_0(MI, 4, O); + SStream_concat1(O, ']'); + return; + break; + case 24: + // INSVE_W + printUImm_2_0(MI, 2, O); + SStream_concat0(O, "], "); + printOperand(MI, 3, O); + SStream_concat1(O, '['); + printUImm_0_0(MI, 4, O); + SStream_concat1(O, ']'); + return; + break; + case 25: + // LAPC32_NM, LAPC48_NM, LWPC_NM, SWPC_NM + printPCRel(MI, Address, 1, O); + return; + break; + case 26: + // LUI_NM + printHi20(MI, 1, O); + return; + break; + case 27: + // LWP_MM, SWP_MM + printMemOperand(MI, 2, O); + return; + break; + case 28: + // PREFX_MM + SStream_concat1(O, '('); + printOperand(MI, 0, O); + SStream_concat1(O, ')'); + return; + break; + case 29: + // REPL_QB, REPL_QB_MM + printUImm_8_0(MI, 1, O); return; break; } - // Fragment 3 encoded into 4 bits for 15 unique commands. - //printf("Frag-3: %"PRIu64"\n", (Bits >> 27) & 15); - switch ((uint32_t)((Bits >> 27) & 15)) { - default: // llvm_unreachable("Invalid command number."); + // Fragment 3 encoded into 5 bits for 19 unique commands. + switch ((Bits >> 29) & 31) { + default: assert(0 && "Invalid command number."); case 0: - // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM, ALU... + // ABSMacro, CFTC1, JalTwoReg, LDMacro, LOAD_ACC128, LOAD_ACC64, LOAD_ACC... return; break; case 1: - // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD... - SStream_concat0(O, ", "); + // ALIGN_NM, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG... + SStream_concat0(O, ", "); break; case 2: - // AddiuRxRxImm16, LwRxPcTcp16 - SStream_concat0(O, "\t# 16 bit inst"); + // BteqzT8CmpX16, BteqzT8CmpiX16, BteqzT8SltX16, BteqzT8SltiX16, BteqzT8S... + SStream_concat0(O, "\n\tbteqz\t"); + printBranchOperand(MI, Address, 2, O); return; break; case 3: - // BeqzRxImm16, BnezRxImm16 - SStream_concat0(O, " # 16 bit inst"); + // BtnezT8CmpX16, BtnezT8CmpiX16, BtnezT8SltX16, BtnezT8SltiX16, BtnezT8S... + SStream_concat0(O, "\n\tbtnez\t"); + printBranchOperand(MI, Address, 2, O); return; break; case 4: - // BteqzT8CmpX16, BteqzT8CmpiX16, BteqzT8SltX16, BteqzT8SltiX16, BteqzT8S... - SStream_concat0(O, "\n\tbteqz\t"); - printOperand(MI, 2, O); + // GotPrologue16 + SStream_concat0(O, "\n\taddiu\t"); + printOperand(MI, 1, O); + SStream_concat0(O, ", $pc, "); + printOperand(MI, 3, O); + SStream_concat0(O, "\n "); return; break; case 5: - // BtnezT8CmpX16, BtnezT8CmpiX16, BtnezT8SltX16, BtnezT8SltiX16, BtnezT8S... - SStream_concat0(O, "\n\tbtnez\t"); - printOperand(MI, 2, O); + // MTTC0, MTTC0_NM, DMTC0, DMTC2, DMTGC0, MTC0, MTC0_MMR6, MTC2, MTGC0, M... + printUImm_3_0(MI, 2, O); return; break; case 6: - // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_D, COPY_U_H, ... - SStream_concat0(O, "["); + // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... + SStream_concat0(O, "\n\tbteqz\t.+4\n\tmove "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; break; case 7: - // CmpiRxImm16, LiRxImm16, SltiRxImm16, SltiuRxImm16 - SStream_concat0(O, " \t# 16 bit inst"); + // SelTBtneZCmp, SelTBtneZCmpi, SelTBtneZSlt, SelTBtneZSlti, SelTBtneZSlt... + SStream_concat0(O, "\n\tbtnez\t.+4\n\tmove "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); return; break; case 8: - // DSLL64_32 - SStream_concat0(O, ", 32"); + // AddiuRxRxImm16, LwRxPcTcp16 + SStream_concat0(O, "\t# 16 bit inst"); return; break; case 9: - // GotPrologue16 - SStream_concat0(O, "\n\taddiu\t"); - printOperand(MI, 1, O); - SStream_concat0(O, ", $pc, "); - printOperand(MI, 3, O); - SStream_concat0(O, "\n "); + // BeqzRxImm16, BnezRxImm16 + SStream_concat0(O, " # 16 bit inst"); return; break; case 10: - // LBUX, LDXC1, LDXC164, LHX, LUXC1, LUXC164, LUXC1_MM, LWX, LWXC1, LWXC1... - SStream_concat0(O, "("); - printOperand(MI, 1, O); - SStream_concat0(O, ")"); - return; + // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ... + SStream_concat1(O, '['); break; case 11: - // LwRxSpImmX16, SwRxSpImmX16 - SStream_concat0(O, " ( "); - printOperand(MI, 1, O); - SStream_concat0(O, " ); "); + // CmpiRxImm16, LiRxImm16, SltiRxImm16, SltiuRxImm16 + SStream_concat0(O, " \t# 16 bit inst"); return; break; case 12: - // SLL64_32, SLL64_64 - SStream_concat0(O, ", 0"); + // DSLL64_32 + SStream_concat0(O, ", 32"); return; break; case 13: - // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... - SStream_concat0(O, "\n\tbteqz\t.+4\n\tmove "); - printOperand(MI, 1, O); - SStream_concat0(O, ", "); - printOperand(MI, 2, O); + // FORK, FORK_NM + printOperand(MI, 2, O); return; break; case 14: - // SelTBtneZCmp, SelTBtneZCmpi, SelTBtneZSlt, SelTBtneZSlti, SelTBtneZSlt... - SStream_concat0(O, "\n\tbtnez\t.+4\n\tmove "); - printOperand(MI, 1, O); - SStream_concat0(O, ", "); - printOperand(MI, 2, O); + // LBUX, LBUX_MM, LDXC1, LDXC164, LHX, LHX_MM, LUXC1, LUXC164, LUXC1_MM, ... + SStream_concat1(O, '('); + printOperand(MI, 1, O); + SStream_concat1(O, ')'); + return; + break; + case 15: + // LSA_MMR6 + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printUImm_2_1(MI, 3, O); + return; + break; + case 16: + // MTTR, MTTR_NM + printUImm_1_0(MI, 2, O); + SStream_concat0(O, ", "); + printUImm_3_0(MI, 3, O); + SStream_concat0(O, ", "); + printUImm_1_0(MI, 4, O); + return; + break; + case 17: + // SCWP_NM + printMemOperand(MI, 3, O); + return; + break; + case 18: + // SLL64_32, SLL64_64 + SStream_concat0(O, ", 0"); return; break; } - // Fragment 4 encoded into 3 bits for 5 unique commands. - //printf("Frag-4: %"PRIu64"\n", (Bits >> 31) & 7); - switch ((uint32_t)((Bits >> 31) & 7)) { - default: // llvm_unreachable("Invalid command number."); + // Fragment 4 encoded into 5 bits for 24 unique commands. + switch ((Bits >> 34) & 31) { + default: assert(0 && "Invalid command number."); case 0: - // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD... - printOperand(MI, 2, O); + // ALIGN_NM, DMULImmMacro, DMULMacro, DMULOMacro, DMULOUMacro, DROL, DROL... + printOperand(MI, 2, O); break; case 1: - // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, ANDI_B, BCLRI_B, BCLRI_D, BCLRI_H,... - printUnsignedImm8(MI, 2, O); + // BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro... + printBranchOperand(MI, Address, 2, O); + return; break; case 2: - // ANDi, ANDi64, ANDi_MM, APPEND, BALIGN, CINS, CINS32, DEXT, DEXTM, DEXT... - printUnsignedImm(MI, 2, O); + // MFTC0, MFTC0_NM, BCLRI_B, BNEGI_B, BSETI_B, COPY_S_H, COPY_U_H, DMFC0,... + printUImm_3_0(MI, 2, O); break; case 3: - // BINSLI_B, BINSLI_D, BINSLI_H, BINSLI_W, BINSRI_B, BINSRI_D, BINSRI_H, ... - printUnsignedImm8(MI, 3, O); + // PseudoADDIU_NM, ADDIU48_NM + printUImm_32_0(MI, 2, O); + return; break; case 4: + // PseudoANDI_NM, ADDIU_NM, ANDI16_NM, ANDI_MMR6, ANDi, ANDi64, ANDi_MM, ... + printUImm_16_0(MI, 2, O); + return; + break; + case 5: + // ADDIUR1SP_NM, ANDI_B, NORI_B, ORI_B, RDHWR, RDHWR64, RDHWR_MM, SHF_B, ... + printUImm_8_0(MI, 2, O); + return; + break; + case 6: + // ADDIUR2_NM, ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, APPEND, APPEND_MMR2, B... + printUImm_5_0(MI, 2, O); + break; + case 7: + // BALIGN, BALIGN_MMR2, COPY_S_W, COPY_U_W, SPLATI_W + printUImm_2_0(MI, 2, O); + break; + case 8: + // BCLRI_D, BNEGI_D, BSETI_D, DEXT, DEXT64_32, DINS, DROTR, DSLL, DSRA, D... + printUImm_6_0(MI, 2, O); + break; + case 9: + // BCLRI_H, BNEGI_H, BSETI_H, COPY_S_B, COPY_U_B, SAT_S_H, SAT_U_H, SHLL_... + printUImm_4_0(MI, 2, O); + break; + case 10: + // BINSLI_B, BINSRI_B, SLDI_H + printUImm_3_0(MI, 3, O); + break; + case 11: + // BINSLI_D, BINSRI_D + printUImm_6_0(MI, 3, O); + return; + break; + case 12: + // BINSLI_H, BINSRI_H, SLDI_B + printUImm_4_0(MI, 3, O); + break; + case 13: + // BINSLI_W, BINSRI_W + printUImm_5_0(MI, 3, O); + return; + break; + case 14: // BINSL_B, BINSL_D, BINSL_H, BINSL_W, BINSR_B, BINSR_D, BINSR_H, BINSR_W... - printOperand(MI, 3, O); + printOperand(MI, 3, O); + break; + case 15: + // BMNZI_B, BMZI_B, BSELI_B + printUImm_8_0(MI, 3, O); + return; + break; + case 16: + // COPY_S_D, MFTR, MFTR_NM, SPLATI_D + printUImm_1_0(MI, 2, O); + break; + case 17: + // DEXTU, DINSU + printUImm_5_32(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 18: + // FADD_S_MMR6, FDIV_S_MMR6, FMUL_S_MMR6, FSUB_S_MMR6 + printOperand(MI, 1, O); + return; + break; + case 19: + // LLWP_NM + printMemOperand(MI, 2, O); + return; + break; + case 20: + // MOVEBALC_NM + printPCRel(MI, Address, 2, O); + return; + break; + case 21: + // SLDI_D + printUImm_1_0(MI, 3, O); + SStream_concat1(O, ']'); + return; + break; + case 22: + // SLDI_W + printUImm_2_0(MI, 3, O); + SStream_concat1(O, ']'); + return; + break; + case 23: + // TEQ, TGE, TGEU, TLT, TLTU, TNE + printUImm_10_0(MI, 2, O); + return; + break; + } + + + // Fragment 5 encoded into 3 bits for 5 unique commands. + switch ((Bits >> 39) & 7) { + default: assert(0 && "Invalid command number."); + case 0: + // ALIGN_NM, ALIGN, ALIGN_MMR6, CINS, CINS32, CINS64_32, CINS_i32, DALIGN... + SStream_concat0(O, ", "); + break; + case 1: + // DMULImmMacro, DMULMacro, DMULOMacro, DMULOUMacro, DROL, DROLImm, DROR,... + return; + break; + case 2: + // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ... + SStream_concat1(O, ']'); + return; + break; + case 3: + // DEXTU + printUImm_5_1(MI, 3, O); + return; + break; + case 4: + // DINSU + printUImm_6_0(MI, 3, O); + return; break; } - // Fragment 5 encoded into 2 bits for 3 unique commands. - //printf("Frag-5: %"PRIu64"\n", (Bits >> 34) & 3); - switch ((uint32_t)((Bits >> 34) & 3)) { - default: // llvm_unreachable("Invalid command number."); + // Fragment 6 encoded into 4 bits for 10 unique commands. + switch ((Bits >> 42) & 15) { + default: assert(0 && "Invalid command number."); case 0: - // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD... + // ALIGN_NM, MADD_D32, MADD_D32_MM, MADD_D64, MADD_S, MADD_S_MM, MOVEPREV... + printOperand(MI, 3, O); return; break; case 1: - // ALIGN, CINS, CINS32, DALIGN, DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, D... - SStream_concat0(O, ", "); + // ALIGN, ALIGN_MMR6, LSA_NM + printUImm_2_0(MI, 3, O); + return; break; case 2: - // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_D, COPY_U_H, ... - SStream_concat0(O, "]"); + // CINS, CINS32, CINS64_32, CINS_i32, EXTS, EXTS32, EXTW_NM, ROTX_NM + printUImm_5_0(MI, 3, O); + break; + case 3: + // DALIGN, MFTR, MFTR_NM + printUImm_3_0(MI, 3, O); + break; + case 4: + // DEXT + printUImm_6_1(MI, 3, O); + return; + break; + case 5: + // DEXT64_32, EXT, EXT_MM, EXT_MMR6, EXT_NM + printUImm_5_1(MI, 3, O); + return; + break; + case 6: + // DEXTM + printUImm_5_33(MI, 3, O); + return; + break; + case 7: + // DINS, INS, INS_MM, INS_MMR6, INS_NM + printUImm_6_0(MI, 3, O); + return; + break; + case 8: + // DINSM + printUImm_6_2(MI, 3, O); + return; + break; + case 9: + // DLSA, DLSA_R6, LSA, LSA_R6 + printUImm_2_1(MI, 3, O); return; break; } - // Fragment 6 encoded into 1 bits for 2 unique commands. - //printf("Frag-6: %"PRIu64"\n", (Bits >> 36) & 1); - if ((Bits >> 36) & 1) { - // DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, EXT, EXT_MM, INS, INS_MM, MADD... - printOperand(MI, 3, O); + // Fragment 7 encoded into 1 bits for 2 unique commands. + if ((Bits >> 46) & 1) { + // MFTR, MFTR_NM, ROTX_NM + SStream_concat0(O, ", "); + printUImm_1_0(MI, 4, O); return; } else { - // ALIGN, CINS, CINS32, DALIGN, DLSA, DLSA_R6, EXTS, EXTS32, LSA, LSA_R6 - printUnsignedImm(MI, 3, O); + // CINS, CINS32, CINS64_32, CINS_i32, DALIGN, EXTS, EXTS32, EXTW_NM return; } + } /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. -static const char *getRegisterName(unsigned RegNo) -{ - // assert(RegNo && RegNo < 394 && "Invalid register number!"); - +static const char *getRegisterName(unsigned RegNo) { #ifndef CAPSTONE_DIET - static const char AsmStrs[] = { - /* 0 */ 'f', '1', '0', 0, - /* 4 */ 'w', '1', '0', 0, - /* 8 */ 'f', '2', '0', 0, - /* 12 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '0', 0, - /* 25 */ 'w', '2', '0', 0, - /* 29 */ 'f', '3', '0', 0, - /* 33 */ 'w', '3', '0', 0, - /* 37 */ 'a', '0', 0, - /* 40 */ 'a', 'c', '0', 0, - /* 44 */ 'f', 'c', 'c', '0', 0, - /* 49 */ 'f', '0', 0, - /* 52 */ 'k', '0', 0, - /* 55 */ 'm', 'p', 'l', '0', 0, - /* 60 */ 'p', '0', 0, - /* 63 */ 's', '0', 0, - /* 66 */ 't', '0', 0, - /* 69 */ 'v', '0', 0, - /* 72 */ 'w', '0', 0, - /* 75 */ 'f', '1', '1', 0, - /* 79 */ 'w', '1', '1', 0, - /* 83 */ 'f', '2', '1', 0, - /* 87 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '1', 0, - /* 100 */ 'w', '2', '1', 0, - /* 104 */ 'f', '3', '1', 0, - /* 108 */ 'w', '3', '1', 0, - /* 112 */ 'a', '1', 0, - /* 115 */ 'a', 'c', '1', 0, - /* 119 */ 'f', 'c', 'c', '1', 0, - /* 124 */ 'f', '1', 0, - /* 127 */ 'k', '1', 0, - /* 130 */ 'm', 'p', 'l', '1', 0, - /* 135 */ 'p', '1', 0, - /* 138 */ 's', '1', 0, - /* 141 */ 't', '1', 0, - /* 144 */ 'v', '1', 0, - /* 147 */ 'w', '1', 0, - /* 150 */ 'f', '1', '2', 0, - /* 154 */ 'w', '1', '2', 0, - /* 158 */ 'f', '2', '2', 0, - /* 162 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '2', 0, - /* 175 */ 'w', '2', '2', 0, - /* 179 */ 'a', '2', 0, - /* 182 */ 'a', 'c', '2', 0, - /* 186 */ 'f', 'c', 'c', '2', 0, - /* 191 */ 'f', '2', 0, - /* 194 */ 'm', 'p', 'l', '2', 0, - /* 199 */ 'p', '2', 0, - /* 202 */ 's', '2', 0, - /* 205 */ 't', '2', 0, - /* 208 */ 'w', '2', 0, - /* 211 */ 'f', '1', '3', 0, - /* 215 */ 'w', '1', '3', 0, - /* 219 */ 'f', '2', '3', 0, - /* 223 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '3', 0, - /* 236 */ 'w', '2', '3', 0, - /* 240 */ 'a', '3', 0, - /* 243 */ 'a', 'c', '3', 0, - /* 247 */ 'f', 'c', 'c', '3', 0, - /* 252 */ 'f', '3', 0, - /* 255 */ 's', '3', 0, - /* 258 */ 't', '3', 0, - /* 261 */ 'w', '3', 0, - /* 264 */ 'f', '1', '4', 0, - /* 268 */ 'w', '1', '4', 0, - /* 272 */ 'f', '2', '4', 0, - /* 276 */ 'w', '2', '4', 0, - /* 280 */ 'f', 'c', 'c', '4', 0, - /* 285 */ 'f', '4', 0, - /* 288 */ 's', '4', 0, - /* 291 */ 't', '4', 0, - /* 294 */ 'w', '4', 0, - /* 297 */ 'f', '1', '5', 0, - /* 301 */ 'w', '1', '5', 0, - /* 305 */ 'f', '2', '5', 0, - /* 309 */ 'w', '2', '5', 0, - /* 313 */ 'f', 'c', 'c', '5', 0, - /* 318 */ 'f', '5', 0, - /* 321 */ 's', '5', 0, - /* 324 */ 't', '5', 0, - /* 327 */ 'w', '5', 0, - /* 330 */ 'f', '1', '6', 0, - /* 334 */ 'w', '1', '6', 0, - /* 338 */ 'f', '2', '6', 0, - /* 342 */ 'w', '2', '6', 0, - /* 346 */ 'f', 'c', 'c', '6', 0, - /* 351 */ 'f', '6', 0, - /* 354 */ 's', '6', 0, - /* 357 */ 't', '6', 0, - /* 360 */ 'w', '6', 0, - /* 363 */ 'f', '1', '7', 0, - /* 367 */ 'w', '1', '7', 0, - /* 371 */ 'f', '2', '7', 0, - /* 375 */ 'w', '2', '7', 0, - /* 379 */ 'f', 'c', 'c', '7', 0, - /* 384 */ 'f', '7', 0, - /* 387 */ 's', '7', 0, - /* 390 */ 't', '7', 0, - /* 393 */ 'w', '7', 0, - /* 396 */ 'f', '1', '8', 0, - /* 400 */ 'w', '1', '8', 0, - /* 404 */ 'f', '2', '8', 0, - /* 408 */ 'w', '2', '8', 0, - /* 412 */ 'f', '8', 0, - /* 415 */ 't', '8', 0, - /* 418 */ 'w', '8', 0, - /* 421 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', '6', '_', '1', '9', 0, - /* 437 */ 'f', '1', '9', 0, - /* 441 */ 'w', '1', '9', 0, - /* 445 */ 'f', '2', '9', 0, - /* 449 */ 'w', '2', '9', 0, - /* 453 */ 'f', '9', 0, - /* 456 */ 't', '9', 0, - /* 459 */ 'w', '9', 0, - /* 462 */ 'D', 'S', 'P', 'E', 'F', 'I', 0, - /* 469 */ 'r', 'a', 0, - /* 472 */ 'h', 'w', 'r', '_', 'c', 'c', 0, - /* 479 */ 'p', 'c', 0, - /* 482 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0, - /* 491 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0, - /* 502 */ 'h', 'i', 0, - /* 505 */ 'h', 'w', 'r', '_', 'c', 'p', 'u', 'n', 'u', 'm', 0, - /* 516 */ 'l', 'o', 0, - /* 519 */ 'z', 'e', 'r', 'o', 0, - /* 524 */ 'h', 'w', 'r', '_', 's', 'y', 'n', 'c', 'i', '_', 's', 't', 'e', 'p', 0, - /* 539 */ 'f', 'p', 0, - /* 542 */ 'g', 'p', 0, - /* 545 */ 's', 'p', 0, - /* 548 */ 'h', 'w', 'r', '_', 'c', 'c', 'r', 'e', 's', 0, - /* 558 */ 'D', 'S', 'P', 'P', 'o', 's', 0, - /* 565 */ 'a', 't', 0, - /* 568 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0, - /* 578 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0, - }; + assert(RegNo && RegNo < 635 && "Invalid register number!"); + static const char AsmStrs[] = { + /* 0 */ "f10\0" + /* 4 */ "watchhi10\0" + /* 14 */ "watchlo10\0" + /* 24 */ "w10\0" + /* 28 */ "f20\0" + /* 32 */ "DSPOutFlag20\0" + /* 45 */ "w20\0" + /* 49 */ "f30\0" + /* 53 */ "w30\0" + /* 57 */ "a0\0" + /* 60 */ "ac0\0" + /* 64 */ "fcc0\0" + /* 69 */ "vpeconf0\0" + /* 78 */ "mvpconf0\0" + /* 87 */ "srsconf0\0" + /* 96 */ "watchhi0\0" + /* 105 */ "k0\0" + /* 108 */ "mpl0\0" + /* 113 */ "perfctl0\0" + /* 122 */ "segctl0\0" + /* 130 */ "guestctl0\0" + /* 140 */ "watchlo0\0" + /* 149 */ "entrylo0\0" + /* 158 */ "p0\0" + /* 161 */ "s0\0" + /* 164 */ "perfcnt0\0" + /* 173 */ "w0\0" + /* 176 */ "f11\0" + /* 180 */ "watchhi11\0" + /* 190 */ "watchlo11\0" + /* 200 */ "w11\0" + /* 204 */ "f21\0" + /* 208 */ "DSPOutFlag21\0" + /* 221 */ "w21\0" + /* 225 */ "f31\0" + /* 229 */ "w31\0" + /* 233 */ "usertracedata1\0" + /* 248 */ "ac1\0" + /* 252 */ "fcc1\0" + /* 257 */ "vpeconf1\0" + /* 266 */ "mvpconf1\0" + /* 275 */ "srsconf1\0" + /* 284 */ "config1\0" + /* 292 */ "kscratch1\0" + /* 302 */ "watchhi1\0" + /* 311 */ "k1\0" + /* 314 */ "mpl1\0" + /* 319 */ "perfctl1\0" + /* 328 */ "segctl1\0" + /* 336 */ "guestctl1\0" + /* 346 */ "watchlo1\0" + /* 355 */ "entrylo1\0" + /* 364 */ "p1\0" + /* 367 */ "s1\0" + /* 370 */ "perfcnt1\0" + /* 379 */ "w1\0" + /* 382 */ "f12\0" + /* 386 */ "watchhi12\0" + /* 396 */ "watchlo12\0" + /* 406 */ "w12\0" + /* 410 */ "f22\0" + /* 414 */ "DSPOutFlag22\0" + /* 427 */ "w22\0" + /* 431 */ "usertracedata2\0" + /* 446 */ "ac2\0" + /* 450 */ "fcc2\0" + /* 455 */ "srsconf2\0" + /* 464 */ "config2\0" + /* 472 */ "debug2\0" + /* 479 */ "kscratch2\0" + /* 489 */ "watchhi2\0" + /* 498 */ "tracecontrol2\0" + /* 512 */ "mpl2\0" + /* 517 */ "perfctl2\0" + /* 526 */ "segctl2\0" + /* 534 */ "guestctl2\0" + /* 544 */ "watchlo2\0" + /* 553 */ "srsmap2\0" + /* 561 */ "s2\0" + /* 564 */ "perfcnt2\0" + /* 573 */ "w2\0" + /* 576 */ "f13\0" + /* 580 */ "watchhi13\0" + /* 590 */ "watchlo13\0" + /* 600 */ "w13\0" + /* 604 */ "f23\0" + /* 608 */ "DSPOutFlag23\0" + /* 621 */ "w23\0" + /* 625 */ "a3\0" + /* 628 */ "ac3\0" + /* 632 */ "fcc3\0" + /* 637 */ "srsconf3\0" + /* 646 */ "config3\0" + /* 654 */ "kscratch3\0" + /* 664 */ "watchhi3\0" + /* 673 */ "tracecontrol3\0" + /* 687 */ "perfctl3\0" + /* 696 */ "guestctl3\0" + /* 706 */ "watchlo3\0" + /* 715 */ "s3\0" + /* 718 */ "perfcnt3\0" + /* 727 */ "w3\0" + /* 730 */ "f14\0" + /* 734 */ "watchhi14\0" + /* 744 */ "watchlo14\0" + /* 754 */ "w14\0" + /* 758 */ "f24\0" + /* 762 */ "w24\0" + /* 766 */ "a4\0" + /* 769 */ "fcc4\0" + /* 774 */ "srsconf4\0" + /* 783 */ "config4\0" + /* 791 */ "kscratch4\0" + /* 801 */ "watchhi4\0" + /* 810 */ "perfctl4\0" + /* 819 */ "watchlo4\0" + /* 828 */ "s4\0" + /* 831 */ "perfcnt4\0" + /* 840 */ "w4\0" + /* 843 */ "f15\0" + /* 847 */ "watchhi15\0" + /* 857 */ "watchlo15\0" + /* 867 */ "w15\0" + /* 871 */ "f25\0" + /* 875 */ "w25\0" + /* 879 */ "a5\0" + /* 882 */ "fcc5\0" + /* 887 */ "f5\0" + /* 890 */ "config5\0" + /* 898 */ "kscratch5\0" + /* 908 */ "watchhi5\0" + /* 917 */ "perfctl5\0" + /* 926 */ "watchlo5\0" + /* 935 */ "s5\0" + /* 938 */ "perfcnt5\0" + /* 947 */ "w5\0" + /* 950 */ "f16\0" + /* 954 */ "w16\0" + /* 958 */ "f26\0" + /* 962 */ "w26\0" + /* 966 */ "a6\0" + /* 969 */ "fcc6\0" + /* 974 */ "f6\0" + /* 977 */ "kscratch6\0" + /* 987 */ "watchhi6\0" + /* 996 */ "perfctl6\0" + /* 1005 */ "watchlo6\0" + /* 1014 */ "s6\0" + /* 1017 */ "perfcnt6\0" + /* 1026 */ "w6\0" + /* 1029 */ "f17\0" + /* 1033 */ "w17\0" + /* 1037 */ "f27\0" + /* 1041 */ "w27\0" + /* 1045 */ "a7\0" + /* 1048 */ "fcc7\0" + /* 1053 */ "f7\0" + /* 1056 */ "watchhi7\0" + /* 1065 */ "perfctl7\0" + /* 1074 */ "watchlo7\0" + /* 1083 */ "s7\0" + /* 1086 */ "perfcnt7\0" + /* 1095 */ "w7\0" + /* 1098 */ "f18\0" + /* 1102 */ "w18\0" + /* 1106 */ "f28\0" + /* 1110 */ "w28\0" + /* 1114 */ "f8\0" + /* 1117 */ "watchhi8\0" + /* 1126 */ "watchlo8\0" + /* 1135 */ "t8\0" + /* 1138 */ "w8\0" + /* 1141 */ "DSPOutFlag16_19\0" + /* 1157 */ "f19\0" + /* 1161 */ "w19\0" + /* 1165 */ "f29\0" + /* 1169 */ "w29\0" + /* 1173 */ "f9\0" + /* 1176 */ "watchhi9\0" + /* 1185 */ "watchlo9\0" + /* 1194 */ "t9\0" + /* 1197 */ "w9\0" + /* 1200 */ "DSPEFI\0" + /* 1207 */ "hwrena\0" + /* 1214 */ "ra\0" + /* 1217 */ "bevva\0" + /* 1223 */ "hwr_cc\0" + /* 1230 */ "tracedbpc\0" + /* 1240 */ "traceibpc\0" + /* 1250 */ "nestedepc\0" + /* 1260 */ "errorepc\0" + /* 1269 */ "nestedexc\0" + /* 1279 */ "wired\0" + /* 1285 */ "memorymapid\0" + /* 1297 */ "prid\0" + /* 1302 */ "debugcontextid\0" + /* 1317 */ "pwfield\0" + /* 1325 */ "tcbind\0" + /* 1332 */ "DSPCCond\0" + /* 1341 */ "tcschedule\0" + /* 1352 */ "vpeschedule\0" + /* 1364 */ "compare\0" + /* 1372 */ "ebase\0" + /* 1378 */ "cdmmbase\0" + /* 1387 */ "cmgcrbase\0" + /* 1397 */ "pwbase\0" + /* 1404 */ "cause\0" + /* 1410 */ "desave\0" + /* 1417 */ "pwsize\0" + /* 1424 */ "DSPOutFlag\0" + /* 1435 */ "xcontextconfig\0" + /* 1450 */ "debug\0" + /* 1456 */ "ddatahi\0" + /* 1464 */ "idatahi\0" + /* 1472 */ "dtaghi\0" + /* 1479 */ "itaghi\0" + /* 1486 */ "entryhi\0" + /* 1494 */ "maari\0" + /* 1500 */ "tcschefback\0" + /* 1512 */ "vpeschefback\0" + /* 1525 */ "pagemask\0" + /* 1534 */ "yqmask\0" + /* 1541 */ "userlocal\0" + /* 1551 */ "tracecontrol\0" + /* 1564 */ "vpecontrol\0" + /* 1575 */ "mvpcontrol\0" + /* 1586 */ "view_ipl\0" + /* 1595 */ "view_ripl\0" + /* 1605 */ "errctl\0" + /* 1612 */ "srsctl\0" + /* 1619 */ "intctl\0" + /* 1626 */ "pwctl\0" + /* 1632 */ "random\0" + /* 1639 */ "hwr_cpunum\0" + /* 1650 */ "pagegrain\0" + /* 1660 */ "ddatalo\0" + /* 1668 */ "idatalo\0" + /* 1676 */ "dtaglo\0" + /* 1683 */ "itaglo\0" + /* 1690 */ "zero\0" + /* 1695 */ "srsmap\0" + /* 1702 */ "hwr_synci_step\0" + /* 1717 */ "fp\0" + /* 1720 */ "gp\0" + /* 1723 */ "badinstrp\0" + /* 1733 */ "sp\0" + /* 1736 */ "maar\0" + /* 1741 */ "lladdr\0" + /* 1748 */ "badvaddr\0" + /* 1757 */ "globalnumber\0" + /* 1770 */ "cacheerr\0" + /* 1779 */ "hwr_ccres\0" + /* 1789 */ "DSPPos\0" + /* 1796 */ "tcstatus\0" + /* 1805 */ "at\0" + /* 1808 */ "gtoffset\0" + /* 1817 */ "tchalt\0" + /* 1824 */ "DSPSCount\0" + /* 1834 */ "count\0" + /* 1840 */ "tcopt\0" + /* 1846 */ "vpeopt\0" + /* 1853 */ "tcrestart\0" + /* 1863 */ "badinst\0" + /* 1871 */ "guestctl0ext\0" + /* 1884 */ "tccontext\0" + /* 1894 */ "xcontext\0" + /* 1903 */ "index\0" + /* 1909 */ "badinstrx\0" + /* 1919 */ "DSPCarry\0" +}; static const uint16_t RegAsmOffset[] = { - 565, 482, 578, 462, 491, 558, 568, 539, 542, 152, 77, 2, 332, 266, - 299, 213, 365, 479, 469, 545, 519, 37, 112, 179, 240, 40, 115, 182, - 243, 565, 45, 120, 187, 248, 281, 314, 347, 380, 2, 77, 152, 213, - 266, 299, 332, 365, 398, 435, 2, 77, 152, 213, 266, 299, 332, 365, - 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, 9, 84, - 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 1, 76, 151, 212, - 265, 298, 331, 364, 397, 434, 9, 84, 159, 220, 273, 306, 339, 372, - 405, 446, 30, 105, 49, 191, 285, 351, 412, 0, 150, 264, 330, 396, - 8, 158, 272, 338, 404, 29, 12, 87, 162, 223, 49, 124, 191, 252, - 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, 297, 330, 363, - 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, 445, 29, 104, - 44, 119, 186, 247, 280, 313, 346, 379, 2, 77, 152, 213, 266, 299, - 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, - 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 539, 49, - 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, - 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, - 445, 29, 104, 542, 40, 115, 182, 243, 505, 524, 472, 548, 266, 299, - 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, - 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 52, 127, - 40, 115, 182, 243, 55, 130, 194, 60, 135, 199, 469, 63, 138, 202, - 255, 288, 321, 354, 387, 545, 66, 141, 205, 258, 291, 324, 357, 390, - 415, 456, 69, 144, 72, 147, 208, 261, 294, 327, 360, 393, 418, 459, - 4, 79, 154, 215, 268, 301, 334, 367, 400, 441, 25, 100, 175, 236, - 276, 309, 342, 375, 408, 449, 33, 108, 519, 37, 112, 179, 240, 40, - 49, 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, - 264, 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, - 404, 445, 29, 104, 421, 502, 52, 127, 516, 63, 138, 202, 255, 288, - 321, 354, 387, 66, 141, 205, 258, 291, 324, 357, 390, 415, 456, 69, - 144, + 178, 1805, 1332, 1919, 1200, 1424, 1789, 1824, 1717, 1717, 1720, 1720, 384, 178, + 2, 952, 732, 845, 578, 1031, 1237, 1214, 1214, 1733, 1733, 1690, 1690, 732, + 845, 952, 1031, 60, 248, 446, 628, 178, 2, 178, 384, 578, 732, 845, + 952, 1031, 1100, 1155, 2, 178, 384, 578, 732, 845, 952, 1031, 1100, 1155, + 2, 178, 384, 578, 732, 845, 952, 1031, 1100, 1155, 1, 177, 383, 577, + 731, 844, 951, 1030, 1099, 1154, 29, 205, 411, 605, 759, 872, 959, 1038, + 1107, 1166, 50, 226, 1, 177, 383, 577, 731, 844, 951, 1030, 1099, 1154, + 29, 205, 411, 605, 759, 872, 959, 1038, 1107, 1166, 50, 226, 1, 177, + 383, 577, 731, 844, 951, 1030, 1099, 1154, 29, 205, 411, 605, 759, 872, + 959, 1038, 1107, 1166, 50, 226, 75, 461, 780, 974, 1114, 0, 382, 730, + 950, 1098, 28, 410, 758, 958, 1106, 49, 32, 208, 414, 608, 75, 263, + 461, 643, 780, 887, 974, 1053, 1114, 1173, 0, 176, 382, 576, 730, 843, + 950, 1029, 1098, 1157, 28, 204, 410, 604, 758, 871, 958, 1037, 1106, 1165, + 49, 225, 64, 252, 450, 632, 769, 882, 969, 1048, 2, 178, 384, 578, + 732, 845, 952, 1031, 1100, 1155, 1, 177, 383, 577, 731, 844, 951, 1030, + 1099, 1154, 29, 205, 411, 605, 759, 872, 959, 1038, 1107, 1166, 50, 226, + 1717, 75, 263, 461, 643, 780, 887, 974, 1053, 1114, 1173, 0, 176, 382, + 576, 730, 843, 950, 1029, 1098, 1157, 28, 204, 410, 604, 758, 871, 958, + 1037, 1106, 1165, 49, 225, 1720, 60, 248, 446, 628, 1639, 1702, 1223, 1779, + 732, 845, 952, 1031, 1100, 1155, 1, 177, 383, 577, 731, 844, 951, 1030, + 1099, 1154, 29, 205, 411, 605, 759, 872, 959, 1038, 1107, 1166, 50, 226, + 959, 1038, 60, 248, 446, 628, 108, 314, 512, 1100, 1155, 1, 177, 383, + 577, 731, 844, 951, 1030, 1099, 1154, 29, 205, 411, 605, 759, 872, 959, + 1038, 1107, 1166, 50, 226, 158, 364, 558, 1214, 951, 1030, 1099, 1154, 29, + 205, 411, 605, 1733, 1100, 1155, 1, 177, 383, 577, 731, 844, 759, 872, + 384, 578, 173, 379, 573, 727, 840, 947, 1026, 1095, 1138, 1197, 24, 200, + 406, 600, 754, 867, 954, 1033, 1102, 1161, 45, 221, 427, 621, 762, 875, + 962, 1041, 1110, 1169, 53, 229, 1690, 57, 245, 443, 625, 766, 879, 966, + 1045, 1863, 1723, 1909, 1748, 1217, 1770, 1404, 1378, 1387, 1364, 1443, 1886, 1436, + 1834, 1456, 1660, 1450, 1302, 1255, 1410, 1472, 1676, 1372, 1486, 1256, 1605, 1260, + 1757, 1808, 1207, 1464, 1668, 1903, 1619, 1479, 1683, 1741, 1736, 1494, 1285, 1575, + 1250, 1269, 1650, 1525, 1297, 1397, 1626, 1317, 1417, 1632, 1612, 1695, 1798, 1325, + 1884, 1817, 1840, 1853, 1341, 1500, 1796, 1551, 1230, 1240, 1541, 1586, 1595, 1576, + 1564, 1846, 1352, 1512, 1279, 1894, 1435, 1534, 105, 311, 161, 367, 561, 715, + 828, 935, 1014, 1083, 170, 376, 570, 724, 837, 944, 1135, 1194, 732, 845, + 952, 1031, 60, 284, 464, 646, 783, 890, 472, 149, 355, 130, 336, 534, + 696, 292, 479, 654, 791, 898, 977, 78, 266, 164, 370, 564, 718, 831, + 938, 1017, 1086, 113, 319, 517, 687, 810, 917, 996, 1065, 122, 328, 526, + 87, 275, 455, 637, 774, 553, 498, 673, 233, 431, 69, 257, 96, 302, + 489, 664, 801, 908, 987, 1056, 1117, 1176, 4, 180, 386, 580, 734, 847, + 140, 346, 544, 706, 819, 926, 1005, 1074, 1126, 1185, 14, 190, 396, 590, + 744, 857, 75, 263, 461, 643, 780, 887, 974, 1053, 1114, 1173, 0, 176, + 382, 576, 730, 843, 950, 1029, 1098, 1157, 28, 204, 410, 604, 758, 871, + 958, 1037, 1106, 1165, 49, 225, 1141, 1461, 959, 1038, 1665, 951, 1030, 1099, + 1154, 29, 205, 411, 605, 1100, 1155, 1, 177, 383, 577, 731, 844, 759, + 872, 384, 578, 1871, }; - //printf("==== RegNo = %u, id = %s\n", RegNo, AsmStrs+RegAsmOffset[RegNo-1]); - //int i; - //for (i = 0; i < sizeof(RegAsmOffset)/2; i++) - // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); - //printf("-------------------------\n"); + assert (*(AsmStrs+RegAsmOffset[RegNo-1]) && + "Invalid alt name index for register!"); return AsmStrs+RegAsmOffset[RegNo-1]; #else return NULL; -#endif +#endif // CAPSTONE_DIET } - #ifdef PRINT_ALIAS_INSTR #undef PRINT_ALIAS_INSTR -static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, SStream *OS) -{ -} +static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) { +#ifndef CAPSTONE_DIET + static const PatternsForOpcode OpToPatterns[] = { + {Mips_MFTACX, 0, 1 }, + {Mips_MFTACX_NM, 1, 1 }, + {Mips_MFTC0, 2, 1 }, + {Mips_MFTC0_NM, 3, 1 }, + {Mips_MFTHI, 4, 1 }, + {Mips_MFTHI_NM, 5, 1 }, + {Mips_MFTLO, 6, 1 }, + {Mips_MFTLO_NM, 7, 1 }, + {Mips_MTTACX, 8, 1 }, + {Mips_MTTACX_NM, 9, 1 }, + {Mips_MTTC0, 10, 1 }, + {Mips_MTTC0_NM, 11, 1 }, + {Mips_MTTHI, 12, 1 }, + {Mips_MTTHI_NM, 13, 1 }, + {Mips_MTTLO, 14, 1 }, + {Mips_MTTLO_NM, 15, 1 }, + {Mips_NORImm, 16, 1 }, + {Mips_NORImm64, 17, 1 }, + {Mips_SLTImm64, 18, 1 }, + {Mips_SLTUImm64, 19, 1 }, + {Mips_ADDIUGP48_NM, 20, 1 }, + {Mips_ADDIUGPB_NM, 21, 1 }, + {Mips_ADDIUGPW_NM, 22, 1 }, + {Mips_ADDIUPC, 23, 1 }, + {Mips_ADDIUPC_MMR6, 24, 1 }, + {Mips_ADDu, 25, 1 }, + {Mips_BC1F, 26, 1 }, + {Mips_BC1FL, 27, 1 }, + {Mips_BC1F_MM, 28, 1 }, + {Mips_BC1T, 29, 1 }, + {Mips_BC1TL, 30, 1 }, + {Mips_BC1T_MM, 31, 1 }, + {Mips_BEQC16_NM, 32, 1 }, + {Mips_BEQC_NM, 33, 2 }, + {Mips_BEQL, 35, 1 }, + {Mips_BGEZAL, 36, 1 }, + {Mips_BGEZAL_MM, 37, 1 }, + {Mips_BNEC16_NM, 38, 1 }, + {Mips_BNEC_NM, 39, 2 }, + {Mips_BNEL, 41, 1 }, + {Mips_BREAK, 42, 2 }, + {Mips_BREAK_MM, 44, 2 }, + {Mips_C_EQ_D32, 46, 1 }, + {Mips_C_EQ_D32_MM, 47, 1 }, + {Mips_C_EQ_D64, 48, 1 }, + {Mips_C_EQ_D64_MM, 49, 1 }, + {Mips_C_EQ_S, 50, 1 }, + {Mips_C_EQ_S_MM, 51, 1 }, + {Mips_C_F_D32, 52, 1 }, + {Mips_C_F_D32_MM, 53, 1 }, + {Mips_C_F_D64, 54, 1 }, + {Mips_C_F_D64_MM, 55, 1 }, + {Mips_C_F_S, 56, 1 }, + {Mips_C_F_S_MM, 57, 1 }, + {Mips_C_LE_D32, 58, 1 }, + {Mips_C_LE_D32_MM, 59, 1 }, + {Mips_C_LE_D64, 60, 1 }, + {Mips_C_LE_D64_MM, 61, 1 }, + {Mips_C_LE_S, 62, 1 }, + {Mips_C_LE_S_MM, 63, 1 }, + {Mips_C_LT_D32, 64, 1 }, + {Mips_C_LT_D32_MM, 65, 1 }, + {Mips_C_LT_D64, 66, 1 }, + {Mips_C_LT_D64_MM, 67, 1 }, + {Mips_C_LT_S, 68, 1 }, + {Mips_C_LT_S_MM, 69, 1 }, + {Mips_C_NGE_D32, 70, 1 }, + {Mips_C_NGE_D32_MM, 71, 1 }, + {Mips_C_NGE_D64, 72, 1 }, + {Mips_C_NGE_D64_MM, 73, 1 }, + {Mips_C_NGE_S, 74, 1 }, + {Mips_C_NGE_S_MM, 75, 1 }, + {Mips_C_NGLE_D32, 76, 1 }, + {Mips_C_NGLE_D32_MM, 77, 1 }, + {Mips_C_NGLE_D64, 78, 1 }, + {Mips_C_NGLE_D64_MM, 79, 1 }, + {Mips_C_NGLE_S, 80, 1 }, + {Mips_C_NGLE_S_MM, 81, 1 }, + {Mips_C_NGL_D32, 82, 1 }, + {Mips_C_NGL_D32_MM, 83, 1 }, + {Mips_C_NGL_D64, 84, 1 }, + {Mips_C_NGL_D64_MM, 85, 1 }, + {Mips_C_NGL_S, 86, 1 }, + {Mips_C_NGL_S_MM, 87, 1 }, + {Mips_C_NGT_D32, 88, 1 }, + {Mips_C_NGT_D32_MM, 89, 1 }, + {Mips_C_NGT_D64, 90, 1 }, + {Mips_C_NGT_D64_MM, 91, 1 }, + {Mips_C_NGT_S, 92, 1 }, + {Mips_C_NGT_S_MM, 93, 1 }, + {Mips_C_OLE_D32, 94, 1 }, + {Mips_C_OLE_D32_MM, 95, 1 }, + {Mips_C_OLE_D64, 96, 1 }, + {Mips_C_OLE_D64_MM, 97, 1 }, + {Mips_C_OLE_S, 98, 1 }, + {Mips_C_OLE_S_MM, 99, 1 }, + {Mips_C_OLT_D32, 100, 1 }, + {Mips_C_OLT_D32_MM, 101, 1 }, + {Mips_C_OLT_D64, 102, 1 }, + {Mips_C_OLT_D64_MM, 103, 1 }, + {Mips_C_OLT_S, 104, 1 }, + {Mips_C_OLT_S_MM, 105, 1 }, + {Mips_C_SEQ_D32, 106, 1 }, + {Mips_C_SEQ_D32_MM, 107, 1 }, + {Mips_C_SEQ_D64, 108, 1 }, + {Mips_C_SEQ_D64_MM, 109, 1 }, + {Mips_C_SEQ_S, 110, 1 }, + {Mips_C_SEQ_S_MM, 111, 1 }, + {Mips_C_SF_D32, 112, 1 }, + {Mips_C_SF_D32_MM, 113, 1 }, + {Mips_C_SF_D64, 114, 1 }, + {Mips_C_SF_D64_MM, 115, 1 }, + {Mips_C_SF_S, 116, 1 }, + {Mips_C_SF_S_MM, 117, 1 }, + {Mips_C_UEQ_D32, 118, 1 }, + {Mips_C_UEQ_D32_MM, 119, 1 }, + {Mips_C_UEQ_D64, 120, 1 }, + {Mips_C_UEQ_D64_MM, 121, 1 }, + {Mips_C_UEQ_S, 122, 1 }, + {Mips_C_UEQ_S_MM, 123, 1 }, + {Mips_C_ULE_D32, 124, 1 }, + {Mips_C_ULE_D32_MM, 125, 1 }, + {Mips_C_ULE_D64, 126, 1 }, + {Mips_C_ULE_D64_MM, 127, 1 }, + {Mips_C_ULE_S, 128, 1 }, + {Mips_C_ULE_S_MM, 129, 1 }, + {Mips_C_ULT_D32, 130, 1 }, + {Mips_C_ULT_D32_MM, 131, 1 }, + {Mips_C_ULT_D64, 132, 1 }, + {Mips_C_ULT_D64_MM, 133, 1 }, + {Mips_C_ULT_S, 134, 1 }, + {Mips_C_ULT_S_MM, 135, 1 }, + {Mips_C_UN_D32, 136, 1 }, + {Mips_C_UN_D32_MM, 137, 1 }, + {Mips_C_UN_D64, 138, 1 }, + {Mips_C_UN_D64_MM, 139, 1 }, + {Mips_C_UN_S, 140, 1 }, + {Mips_C_UN_S_MM, 141, 1 }, + {Mips_DADDu, 142, 1 }, + {Mips_DI, 143, 1 }, + {Mips_DIV, 144, 1 }, + {Mips_DIVU, 145, 1 }, + {Mips_DI_MM, 146, 1 }, + {Mips_DI_MMR6, 147, 1 }, + {Mips_DI_NM, 148, 1 }, + {Mips_DMT, 149, 1 }, + {Mips_DMT_NM, 150, 1 }, + {Mips_DSUB, 151, 2 }, + {Mips_DSUBu, 153, 2 }, + {Mips_DVPE, 155, 1 }, + {Mips_DVPE_NM, 156, 1 }, + {Mips_EI, 157, 1 }, + {Mips_EI_MM, 158, 1 }, + {Mips_EI_MMR6, 159, 1 }, + {Mips_EI_NM, 160, 1 }, + {Mips_EMT, 161, 1 }, + {Mips_EMT_NM, 162, 1 }, + {Mips_EVPE, 163, 1 }, + {Mips_EVPE_NM, 164, 1 }, + {Mips_HYPCALL, 165, 1 }, + {Mips_HYPCALL_MM, 166, 1 }, + {Mips_JALR, 167, 1 }, + {Mips_JALR64, 168, 1 }, + {Mips_JALRCHB_NM, 169, 1 }, + {Mips_JALRC_HB_MMR6, 170, 1 }, + {Mips_JALRC_MMR6, 171, 1 }, + {Mips_JALR_HB, 172, 1 }, + {Mips_JALR_HB64, 173, 1 }, + {Mips_JIALC, 174, 1 }, + {Mips_JIALC64, 175, 1 }, + {Mips_JIC, 176, 1 }, + {Mips_JIC64, 177, 1 }, + {Mips_MFC0_NM, 178, 1 }, + {Mips_MFHC0_NM, 179, 1 }, + {Mips_MOVE16_MM, 180, 1 }, + {Mips_MTC0_NM, 181, 1 }, + {Mips_MTHC0_NM, 182, 1 }, + {Mips_Move32R16, 183, 1 }, + {Mips_NOR_NM, 184, 1 }, + {Mips_OR, 185, 1 }, + {Mips_OR64, 186, 1 }, + {Mips_RDHWR, 187, 1 }, + {Mips_RDHWR64, 188, 1 }, + {Mips_RDHWR_MM, 189, 1 }, + {Mips_RDHWR_MMR6, 190, 1 }, + {Mips_RESTOREJRC16_NM, 191, 1 }, + {Mips_RESTOREJRC_NM, 192, 1 }, + {Mips_RESTORE_NM, 193, 1 }, + {Mips_ROTX_NM, 194, 3 }, + {Mips_SAVE16_NM, 197, 1 }, + {Mips_SAVE_NM, 198, 1 }, + {Mips_SDBBP, 199, 1 }, + {Mips_SDBBP_MMR6, 200, 1 }, + {Mips_SDBBP_R6, 201, 1 }, + {Mips_SIGRIE, 202, 1 }, + {Mips_SIGRIE_MMR6, 203, 1 }, + {Mips_SLL, 204, 1 }, + {Mips_SLL_MM, 205, 1 }, + {Mips_SLL_MMR6, 206, 1 }, + {Mips_SUB, 207, 2 }, + {Mips_SUBU_MMR6, 209, 2 }, + {Mips_SUB_MM, 211, 2 }, + {Mips_SUB_MMR6, 213, 2 }, + {Mips_SUBu, 215, 2 }, + {Mips_SUBu_MM, 217, 2 }, + {Mips_SWSP_MM, 219, 1 }, + {Mips_SYNC, 220, 1 }, + {Mips_SYNC_MM, 221, 1 }, + {Mips_SYNC_MMR6, 222, 1 }, + {Mips_SYNC_NM, 223, 6 }, + {Mips_SYSCALL, 229, 1 }, + {Mips_SYSCALL_MM, 230, 1 }, + {Mips_TEQ, 231, 1 }, + {Mips_TEQ_MM, 232, 1 }, + {Mips_TGE, 233, 1 }, + {Mips_TGEU, 234, 1 }, + {Mips_TGEU_MM, 235, 1 }, + {Mips_TGE_MM, 236, 1 }, + {Mips_TLT, 237, 1 }, + {Mips_TLTU, 238, 1 }, + {Mips_TLTU_MM, 239, 1 }, + {Mips_TLT_MM, 240, 1 }, + {Mips_TNE, 241, 1 }, + {Mips_TNE_MM, 242, 1 }, + {Mips_WAIT_MM, 243, 1 }, + {Mips_WAIT_NM, 244, 1 }, + {Mips_WRDSP, 245, 1 }, + {Mips_WRDSP_MM, 246, 1 }, + {Mips_YIELD, 247, 1 }, + {Mips_YIELD_NM, 248, 1 }, + {0}, }; -static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) -{ - #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) - const char *AsmString; - char *tmp, *AsmMnem, *AsmOps, *c; - int OpIdx, PrintMethodIdx; - MCRegisterInfo *MRI = (MCRegisterInfo *)info; - switch (MCInst_getOpcode(MI)) { - default: return NULL; - case Mips_ADDu: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == Mips_ZERO) { - // (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - AsmString = "move $\x01, $\x02"; - break; - } - return NULL; - case Mips_BC0F: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC0F CC0, brtarget:$offset) - AsmString = "bc0f $\x02"; - break; - } - return NULL; - case Mips_BC0FL: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC0FL CC0, brtarget:$offset) - AsmString = "bc0fl $\x02"; - break; - } - return NULL; - case Mips_BC0T: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC0T CC0, brtarget:$offset) - AsmString = "bc0t $\x02"; - break; - } - return NULL; - case Mips_BC0TL: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC0TL CC0, brtarget:$offset) - AsmString = "bc0tl $\x02"; - break; - } - return NULL; - case Mips_BC1F: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { - // (BC1F FCC0, brtarget:$offset) - AsmString = "bc1f $\x02"; - break; - } - return NULL; - case Mips_BC1FL: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { - // (BC1FL FCC0, brtarget:$offset) - AsmString = "bc1fl $\x02"; - break; - } - return NULL; - case Mips_BC1T: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { - // (BC1T FCC0, brtarget:$offset) - AsmString = "bc1t $\x02"; - break; - } - return NULL; - case Mips_BC1TL: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { - // (BC1TL FCC0, brtarget:$offset) - AsmString = "bc1tl $\x02"; - break; - } - return NULL; - case Mips_BC2F: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC2F CC0, brtarget:$offset) - AsmString = "bc2f $\x02"; - break; - } - return NULL; - case Mips_BC2FL: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC2FL CC0, brtarget:$offset) - AsmString = "bc2fl $\x02"; - break; - } - return NULL; - case Mips_BC2T: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC2T CC0, brtarget:$offset) - AsmString = "bc2t $\x02"; - break; - } - return NULL; - case Mips_BC2TL: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC2TL CC0, brtarget:$offset) - AsmString = "bc2tl $\x02"; - break; - } - return NULL; - case Mips_BC3F: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC3F CC0, brtarget:$offset) - AsmString = "bc3f $\x02"; - break; - } - return NULL; - case Mips_BC3FL: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC3FL CC0, brtarget:$offset) - AsmString = "bc3fl $\x02"; - break; - } - return NULL; - case Mips_BC3T: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC3T CC0, brtarget:$offset) - AsmString = "bc3t $\x02"; - break; - } - return NULL; - case Mips_BC3TL: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { - // (BC3TL CC0, brtarget:$offset) - AsmString = "bc3tl $\x02"; - break; - } - return NULL; - case Mips_BREAK: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { - // (BREAK 0, 0) - AsmString = "break"; - break; - } - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { - // (BREAK uimm10:$imm, 0) - AsmString = "break $\x01"; - break; - } - return NULL; - case Mips_DADDu: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == Mips_ZERO_64) { - // (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - AsmString = "move $\x01, $\x02"; - break; - } - return NULL; - case Mips_DI: - if (MCInst_getNumOperands(MI) == 1 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO) { - // (DI ZERO) - AsmString = "di"; - break; - } - return NULL; - case Mips_EI: - if (MCInst_getNumOperands(MI) == 1 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO) { - // (EI ZERO) - AsmString = "ei"; - break; - } - return NULL; - case Mips_JALR: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1)) { - // (JALR ZERO, GPR32Opnd:$rs) - AsmString = "jr $\x02"; - break; - } - return NULL; - case Mips_JALR64: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO_64 && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 1)) { - // (JALR64 ZERO_64, GPR64Opnd:$rs) - AsmString = "jr $\x02"; - break; - } - return NULL; - case Mips_JALR_HB: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_RA && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1)) { - // (JALR_HB RA, GPR32Opnd:$rs) - AsmString = "jalr.hb $\x02"; - break; - } - return NULL; - case Mips_MOVE16_MM: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO) { - // (MOVE16_MM ZERO, ZERO) - AsmString = "nop"; - break; - } - return NULL; - case Mips_SDBBP: - if (MCInst_getNumOperands(MI) == 1 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { - // (SDBBP 0) - AsmString = "sdbbp"; - break; - } - return NULL; - case Mips_SDBBP_R6: - if (MCInst_getNumOperands(MI) == 1 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { - // (SDBBP_R6 0) - AsmString = "sdbbp"; - break; - } - return NULL; - case Mips_SLL: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (SLL ZERO, ZERO, 0) - AsmString = "nop"; - break; - } - return NULL; - case Mips_SLL_MM: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (SLL_MM ZERO, ZERO, 0) - AsmString = "nop"; - break; - } - return NULL; - case Mips_SUB: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 2)) { - // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - AsmString = "neg $\x01, $\x03"; - break; - } - return NULL; - case Mips_SUBu: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 2)) { - // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - AsmString = "negu $\x01, $\x03"; - break; - } - return NULL; - case Mips_SYNC: - if (MCInst_getNumOperands(MI) == 1 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { - // (SYNC 0) - AsmString = "sync"; - break; - } - return NULL; - case Mips_SYSCALL: - if (MCInst_getNumOperands(MI) == 1 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { - // (SYSCALL 0) - AsmString = "syscall"; - break; - } - return NULL; - case Mips_TEQ: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - AsmString = "teq $\x01, $\x02"; - break; - } - return NULL; - case Mips_TGE: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - AsmString = "tge $\x01, $\x02"; - break; - } - return NULL; - case Mips_TGEU: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - AsmString = "tgeu $\x01, $\x02"; - break; - } - return NULL; - case Mips_TLT: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - AsmString = "tlt $\x01, $\x02"; - break; - } - return NULL; - case Mips_TLTU: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - AsmString = "tltu $\x01, $\x02"; - break; - } - return NULL; - case Mips_TNE: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - AsmString = "tne $\x01, $\x02"; - break; - } - return NULL; - case Mips_WAIT_MM: - if (MCInst_getNumOperands(MI) == 1 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { - // (WAIT_MM 0) - AsmString = "wait"; - break; - } - return NULL; - } + static const AliasPattern Patterns[] = { + // Mips_MFTACX - 0 + {0, 0, 2, 5 }, + // Mips_MFTACX_NM - 1 + {0, 5, 2, 4 }, + // Mips_MFTC0 - 2 + {10, 9, 3, 6 }, + // Mips_MFTC0_NM - 3 + {10, 15, 3, 5 }, + // Mips_MFTHI - 4 + {23, 20, 2, 5 }, + // Mips_MFTHI_NM - 5 + {23, 25, 2, 4 }, + // Mips_MFTLO - 6 + {32, 29, 2, 5 }, + // Mips_MFTLO_NM - 7 + {32, 34, 2, 4 }, + // Mips_MTTACX - 8 + {41, 38, 2, 5 }, + // Mips_MTTACX_NM - 9 + {41, 43, 2, 4 }, + // Mips_MTTC0 - 10 + {51, 47, 3, 6 }, + // Mips_MTTC0_NM - 11 + {51, 53, 3, 5 }, + // Mips_MTTHI - 12 + {64, 58, 2, 5 }, + // Mips_MTTHI_NM - 13 + {64, 63, 2, 4 }, + // Mips_MTTLO - 14 + {73, 67, 2, 5 }, + // Mips_MTTLO_NM - 15 + {73, 72, 2, 4 }, + // Mips_NORImm - 16 + {82, 76, 3, 3 }, + // Mips_NORImm64 - 17 + {82, 79, 3, 3 }, + // Mips_SLTImm64 - 18 + {93, 82, 3, 3 }, + // Mips_SLTUImm64 - 19 + {104, 85, 3, 3 }, + // Mips_ADDIUGP48_NM - 20 + {116, 88, 3, 3 }, + // Mips_ADDIUGPB_NM - 21 + {137, 91, 3, 3 }, + // Mips_ADDIUGPW_NM - 22 + {156, 94, 3, 3 }, + // Mips_ADDIUPC - 23 + {175, 97, 2, 3 }, + // Mips_ADDIUPC_MMR6 - 24 + {175, 100, 2, 3 }, + // Mips_ADDu - 25 + {187, 103, 3, 7 }, + // Mips_BC1F - 26 + {199, 110, 2, 6 }, + // Mips_BC1FL - 27 + {209, 116, 2, 7 }, + // Mips_BC1F_MM - 28 + {199, 123, 2, 4 }, + // Mips_BC1T - 29 + {220, 127, 2, 6 }, + // Mips_BC1TL - 30 + {230, 133, 2, 7 }, + // Mips_BC1T_MM - 31 + {220, 140, 2, 4 }, + // Mips_BEQC16_NM - 32 + {241, 144, 3, 3 }, + // Mips_BEQC_NM - 33 + {259, 147, 3, 3 }, + {274, 150, 3, 3 }, + // Mips_BEQL - 35 + {289, 153, 3, 6 }, + // Mips_BGEZAL - 36 + {304, 159, 2, 6 }, + // Mips_BGEZAL_MM - 37 + {304, 165, 2, 3 }, + // Mips_BNEC16_NM - 38 + {313, 168, 3, 3 }, + // Mips_BNEC_NM - 39 + {331, 171, 3, 3 }, + {346, 174, 3, 3 }, + // Mips_BNEL - 41 + {361, 177, 3, 6 }, + // Mips_BREAK - 42 + {376, 183, 2, 5 }, + {382, 188, 2, 5 }, + // Mips_BREAK_MM - 44 + {376, 193, 2, 3 }, + {382, 196, 2, 3 }, + // Mips_C_EQ_D32 - 46 + {393, 199, 3, 9 }, + // Mips_C_EQ_D32_MM - 47 + {393, 208, 3, 7 }, + // Mips_C_EQ_D64 - 48 + {393, 215, 3, 9 }, + // Mips_C_EQ_D64_MM - 49 + {393, 224, 3, 7 }, + // Mips_C_EQ_S - 50 + {407, 231, 3, 8 }, + // Mips_C_EQ_S_MM - 51 + {407, 239, 3, 6 }, + // Mips_C_F_D32 - 52 + {421, 245, 3, 9 }, + // Mips_C_F_D32_MM - 53 + {421, 254, 3, 7 }, + // Mips_C_F_D64 - 54 + {421, 261, 3, 9 }, + // Mips_C_F_D64_MM - 55 + {421, 270, 3, 7 }, + // Mips_C_F_S - 56 + {434, 277, 3, 8 }, + // Mips_C_F_S_MM - 57 + {434, 285, 3, 6 }, + // Mips_C_LE_D32 - 58 + {447, 291, 3, 9 }, + // Mips_C_LE_D32_MM - 59 + {447, 300, 3, 7 }, + // Mips_C_LE_D64 - 60 + {447, 307, 3, 9 }, + // Mips_C_LE_D64_MM - 61 + {447, 316, 3, 7 }, + // Mips_C_LE_S - 62 + {461, 323, 3, 8 }, + // Mips_C_LE_S_MM - 63 + {461, 331, 3, 6 }, + // Mips_C_LT_D32 - 64 + {475, 337, 3, 9 }, + // Mips_C_LT_D32_MM - 65 + {475, 346, 3, 7 }, + // Mips_C_LT_D64 - 66 + {475, 353, 3, 9 }, + // Mips_C_LT_D64_MM - 67 + {475, 362, 3, 7 }, + // Mips_C_LT_S - 68 + {489, 369, 3, 8 }, + // Mips_C_LT_S_MM - 69 + {489, 377, 3, 6 }, + // Mips_C_NGE_D32 - 70 + {503, 383, 3, 9 }, + // Mips_C_NGE_D32_MM - 71 + {503, 392, 3, 7 }, + // Mips_C_NGE_D64 - 72 + {503, 399, 3, 9 }, + // Mips_C_NGE_D64_MM - 73 + {503, 408, 3, 7 }, + // Mips_C_NGE_S - 74 + {518, 415, 3, 8 }, + // Mips_C_NGE_S_MM - 75 + {518, 423, 3, 6 }, + // Mips_C_NGLE_D32 - 76 + {533, 429, 3, 9 }, + // Mips_C_NGLE_D32_MM - 77 + {533, 438, 3, 7 }, + // Mips_C_NGLE_D64 - 78 + {533, 445, 3, 9 }, + // Mips_C_NGLE_D64_MM - 79 + {533, 454, 3, 7 }, + // Mips_C_NGLE_S - 80 + {549, 461, 3, 8 }, + // Mips_C_NGLE_S_MM - 81 + {549, 469, 3, 6 }, + // Mips_C_NGL_D32 - 82 + {565, 475, 3, 9 }, + // Mips_C_NGL_D32_MM - 83 + {565, 484, 3, 7 }, + // Mips_C_NGL_D64 - 84 + {565, 491, 3, 9 }, + // Mips_C_NGL_D64_MM - 85 + {565, 500, 3, 7 }, + // Mips_C_NGL_S - 86 + {580, 507, 3, 8 }, + // Mips_C_NGL_S_MM - 87 + {580, 515, 3, 6 }, + // Mips_C_NGT_D32 - 88 + {595, 521, 3, 9 }, + // Mips_C_NGT_D32_MM - 89 + {595, 530, 3, 7 }, + // Mips_C_NGT_D64 - 90 + {595, 537, 3, 9 }, + // Mips_C_NGT_D64_MM - 91 + {595, 546, 3, 7 }, + // Mips_C_NGT_S - 92 + {610, 553, 3, 8 }, + // Mips_C_NGT_S_MM - 93 + {610, 561, 3, 6 }, + // Mips_C_OLE_D32 - 94 + {625, 567, 3, 9 }, + // Mips_C_OLE_D32_MM - 95 + {625, 576, 3, 7 }, + // Mips_C_OLE_D64 - 96 + {625, 583, 3, 9 }, + // Mips_C_OLE_D64_MM - 97 + {625, 592, 3, 7 }, + // Mips_C_OLE_S - 98 + {640, 599, 3, 8 }, + // Mips_C_OLE_S_MM - 99 + {640, 607, 3, 6 }, + // Mips_C_OLT_D32 - 100 + {655, 613, 3, 9 }, + // Mips_C_OLT_D32_MM - 101 + {655, 622, 3, 7 }, + // Mips_C_OLT_D64 - 102 + {655, 629, 3, 9 }, + // Mips_C_OLT_D64_MM - 103 + {655, 638, 3, 7 }, + // Mips_C_OLT_S - 104 + {670, 645, 3, 8 }, + // Mips_C_OLT_S_MM - 105 + {670, 653, 3, 6 }, + // Mips_C_SEQ_D32 - 106 + {685, 659, 3, 9 }, + // Mips_C_SEQ_D32_MM - 107 + {685, 668, 3, 7 }, + // Mips_C_SEQ_D64 - 108 + {685, 675, 3, 9 }, + // Mips_C_SEQ_D64_MM - 109 + {685, 684, 3, 7 }, + // Mips_C_SEQ_S - 110 + {700, 691, 3, 8 }, + // Mips_C_SEQ_S_MM - 111 + {700, 699, 3, 6 }, + // Mips_C_SF_D32 - 112 + {715, 705, 3, 9 }, + // Mips_C_SF_D32_MM - 113 + {715, 714, 3, 7 }, + // Mips_C_SF_D64 - 114 + {715, 721, 3, 9 }, + // Mips_C_SF_D64_MM - 115 + {715, 730, 3, 7 }, + // Mips_C_SF_S - 116 + {729, 737, 3, 8 }, + // Mips_C_SF_S_MM - 117 + {729, 745, 3, 6 }, + // Mips_C_UEQ_D32 - 118 + {743, 751, 3, 9 }, + // Mips_C_UEQ_D32_MM - 119 + {743, 760, 3, 7 }, + // Mips_C_UEQ_D64 - 120 + {743, 767, 3, 9 }, + // Mips_C_UEQ_D64_MM - 121 + {743, 776, 3, 7 }, + // Mips_C_UEQ_S - 122 + {758, 783, 3, 8 }, + // Mips_C_UEQ_S_MM - 123 + {758, 791, 3, 6 }, + // Mips_C_ULE_D32 - 124 + {773, 797, 3, 9 }, + // Mips_C_ULE_D32_MM - 125 + {773, 806, 3, 7 }, + // Mips_C_ULE_D64 - 126 + {773, 813, 3, 9 }, + // Mips_C_ULE_D64_MM - 127 + {773, 822, 3, 7 }, + // Mips_C_ULE_S - 128 + {788, 829, 3, 8 }, + // Mips_C_ULE_S_MM - 129 + {788, 837, 3, 6 }, + // Mips_C_ULT_D32 - 130 + {803, 843, 3, 9 }, + // Mips_C_ULT_D32_MM - 131 + {803, 852, 3, 7 }, + // Mips_C_ULT_D64 - 132 + {803, 859, 3, 9 }, + // Mips_C_ULT_D64_MM - 133 + {803, 868, 3, 7 }, + // Mips_C_ULT_S - 134 + {818, 875, 3, 8 }, + // Mips_C_ULT_S_MM - 135 + {818, 883, 3, 6 }, + // Mips_C_UN_D32 - 136 + {833, 889, 3, 9 }, + // Mips_C_UN_D32_MM - 137 + {833, 898, 3, 7 }, + // Mips_C_UN_D64 - 138 + {833, 905, 3, 9 }, + // Mips_C_UN_D64_MM - 139 + {833, 914, 3, 7 }, + // Mips_C_UN_S - 140 + {847, 921, 3, 8 }, + // Mips_C_UN_S_MM - 141 + {847, 929, 3, 6 }, + // Mips_DADDu - 142 + {187, 935, 3, 5 }, + // Mips_DI - 143 + {861, 940, 1, 5 }, + // Mips_DIV - 144 + {864, 945, 3, 5 }, + // Mips_DIVU - 145 + {875, 950, 3, 5 }, + // Mips_DI_MM - 146 + {861, 955, 1, 2 }, + // Mips_DI_MMR6 - 147 + {861, 957, 1, 3 }, + // Mips_DI_NM - 148 + {861, 960, 1, 2 }, + // Mips_DMT - 149 + {887, 962, 1, 4 }, + // Mips_DMT_NM - 150 + {887, 966, 1, 3 }, + // Mips_DSUB - 151 + {891, 969, 3, 6 }, + {903, 975, 3, 6 }, + // Mips_DSUBu - 153 + {911, 981, 3, 6 }, + {924, 987, 3, 6 }, + // Mips_DVPE - 155 + {933, 993, 1, 4 }, + // Mips_DVPE_NM - 156 + {933, 997, 1, 3 }, + // Mips_EI - 157 + {938, 1000, 1, 5 }, + // Mips_EI_MM - 158 + {938, 1005, 1, 2 }, + // Mips_EI_MMR6 - 159 + {938, 1007, 1, 3 }, + // Mips_EI_NM - 160 + {938, 1010, 1, 2 }, + // Mips_EMT - 161 + {941, 1012, 1, 4 }, + // Mips_EMT_NM - 162 + {941, 1016, 1, 3 }, + // Mips_EVPE - 163 + {945, 1019, 1, 4 }, + // Mips_EVPE_NM - 164 + {945, 1023, 1, 3 }, + // Mips_HYPCALL - 165 + {950, 1026, 1, 6 }, + // Mips_HYPCALL_MM - 166 + {950, 1032, 1, 4 }, + // Mips_JALR - 167 + {958, 1036, 2, 6 }, + // Mips_JALR64 - 168 + {958, 1042, 2, 4 }, + // Mips_JALRCHB_NM - 169 + {964, 1046, 2, 3 }, + // Mips_JALRC_HB_MMR6 - 170 + {974, 1049, 2, 4 }, + // Mips_JALRC_MMR6 - 171 + {986, 1053, 2, 4 }, + // Mips_JALR_HB - 172 + {995, 1057, 2, 6 }, + // Mips_JALR_HB64 - 173 + {995, 1063, 2, 5 }, + // Mips_JIALC - 174 + {1006, 1068, 2, 6 }, + // Mips_JIALC64 - 175 + {1006, 1074, 2, 4 }, + // Mips_JIC - 176 + {1015, 1078, 2, 5 }, + // Mips_JIC64 - 177 + {1015, 1083, 2, 4 }, + // Mips_MFC0_NM - 178 + {1022, 1087, 3, 4 }, + // Mips_MFHC0_NM - 179 + {1034, 1091, 3, 4 }, + // Mips_MOVE16_MM - 180 + {1047, 1095, 2, 3 }, + // Mips_MTC0_NM - 181 + {1051, 1098, 3, 4 }, + // Mips_MTHC0_NM - 182 + {1063, 1102, 3, 4 }, + // Mips_Move32R16 - 183 + {1047, 1106, 2, 3 }, + // Mips_NOR_NM - 184 + {1076, 1109, 3, 4 }, + // Mips_OR - 185 + {187, 1113, 3, 7 }, + // Mips_OR64 - 186 + {187, 1120, 3, 5 }, + // Mips_RDHWR - 187 + {1087, 1125, 3, 6 }, + // Mips_RDHWR64 - 188 + {1087, 1131, 3, 4 }, + // Mips_RDHWR_MM - 189 + {1087, 1135, 3, 5 }, + // Mips_RDHWR_MMR6 - 190 + {1087, 1140, 3, 5 }, + // Mips_RESTOREJRC16_NM - 191 + {1100, 1145, 2, 2 }, + // Mips_RESTOREJRC_NM - 192 + {1117, 1147, 2, 2 }, + // Mips_RESTORE_NM - 193 + {1134, 1149, 2, 2 }, + // Mips_ROTX_NM - 194 + {1147, 1151, 5, 6 }, + {1162, 1157, 5, 6 }, + {1177, 1163, 5, 6 }, + // Mips_SAVE16_NM - 197 + {1193, 1169, 2, 2 }, + // Mips_SAVE_NM - 198 + {1203, 1171, 2, 2 }, + // Mips_SDBBP - 199 + {1213, 1173, 1, 5 }, + // Mips_SDBBP_MMR6 - 200 + {1213, 1178, 1, 3 }, + // Mips_SDBBP_R6 - 201 + {1213, 1181, 1, 4 }, + // Mips_SIGRIE - 202 + {1219, 1185, 1, 4 }, + // Mips_SIGRIE_MMR6 - 203 + {1219, 1189, 1, 3 }, + // Mips_SLL - 204 + {1047, 1192, 3, 6 }, + // Mips_SLL_MM - 205 + {1047, 1198, 3, 4 }, + // Mips_SLL_MMR6 - 206 + {1047, 1202, 3, 5 }, + // Mips_SUB - 207 + {1226, 1207, 3, 6 }, + {1237, 1213, 3, 6 }, + // Mips_SUBU_MMR6 - 209 + {1244, 1219, 3, 5 }, + {1256, 1224, 3, 5 }, + // Mips_SUB_MM - 211 + {1226, 1229, 3, 5 }, + {1237, 1234, 3, 5 }, + // Mips_SUB_MMR6 - 213 + {1226, 1239, 3, 5 }, + {1237, 1244, 3, 5 }, + // Mips_SUBu - 215 + {1244, 1249, 3, 6 }, + {1256, 1255, 3, 6 }, + // Mips_SUBu_MM - 217 + {1244, 1261, 3, 5 }, + {1256, 1266, 3, 5 }, + // Mips_SWSP_MM - 219 + {1264, 1271, 3, 2 }, + // Mips_SYNC - 220 + {1276, 1273, 1, 5 }, + // Mips_SYNC_MM - 221 + {1276, 1278, 1, 2 }, + // Mips_SYNC_MMR6 - 222 + {1276, 1280, 1, 3 }, + // Mips_SYNC_NM - 223 + {1276, 1283, 1, 2 }, + {1281, 1285, 1, 2 }, + {1290, 1287, 1, 2 }, + {1298, 1289, 1, 2 }, + {1311, 1291, 1, 2 }, + {1324, 1293, 1, 2 }, + // Mips_SYSCALL - 229 + {1333, 1295, 1, 4 }, + // Mips_SYSCALL_MM - 230 + {1333, 1299, 1, 2 }, + // Mips_TEQ - 231 + {1341, 1301, 3, 7 }, + // Mips_TEQ_MM - 232 + {1341, 1308, 3, 4 }, + // Mips_TGE - 233 + {1352, 1312, 3, 7 }, + // Mips_TGEU - 234 + {1363, 1319, 3, 7 }, + // Mips_TGEU_MM - 235 + {1363, 1326, 3, 4 }, + // Mips_TGE_MM - 236 + {1352, 1330, 3, 4 }, + // Mips_TLT - 237 + {1375, 1334, 3, 7 }, + // Mips_TLTU - 238 + {1386, 1341, 3, 7 }, + // Mips_TLTU_MM - 239 + {1386, 1348, 3, 4 }, + // Mips_TLT_MM - 240 + {1375, 1352, 3, 4 }, + // Mips_TNE - 241 + {1398, 1356, 3, 7 }, + // Mips_TNE_MM - 242 + {1398, 1363, 3, 4 }, + // Mips_WAIT_MM - 243 + {1409, 1367, 1, 2 }, + // Mips_WAIT_NM - 244 + {1409, 1369, 1, 2 }, + // Mips_WRDSP - 245 + {1414, 1371, 2, 4 }, + // Mips_WRDSP_MM - 246 + {1414, 1375, 2, 4 }, + // Mips_YIELD - 247 + {1423, 1379, 2, 5 }, + // Mips_YIELD_NM - 248 + {1423, 1384, 2, 4 }, + {0}, }; - tmp = cs_strdup(AsmString); - AsmMnem = tmp; - for(AsmOps = tmp; *AsmOps; AsmOps++) { - if (*AsmOps == ' ' || *AsmOps == '\t') { - *AsmOps = '\0'; - AsmOps++; - break; + static const AliasPatternCond Conds[] = { + // (MFTACX GPR32Opnd:$rt, AC0) - 0 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (MFTACX_NM GPRNM32Opnd:$rt, AC0) - 5 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (MFTC0 GPR32Opnd:$rd, COP0Opnd:$rt, 0) - 9 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (MFTC0_NM GPRNM32Opnd:$rd, COP0Opnd:$rt, 0) - 15 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (MFTHI GPR32Opnd:$rt, AC0) - 20 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (MFTHI_NM GPRNM32Opnd:$rt, AC0) - 25 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (MFTLO GPR32Opnd:$rt, AC0) - 29 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (MFTLO_NM GPRNM32Opnd:$rt, AC0) - 34 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (MTTACX AC0, GPR32Opnd:$rt) - 38 + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (MTTACX_NM AC0, GPRNM32Opnd:$rt) - 43 + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (MTTC0 COP0Opnd:$rt, GPR32Opnd:$rd, 0) - 47 + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (MTTC0_NM COP0Opnd:$rt, GPRNM32Opnd:$rd, 0) - 53 + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (MTTHI AC0, GPR32Opnd:$rt) - 58 + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (MTTHI_NM AC0, GPRNM32Opnd:$rt) - 63 + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (MTTLO AC0, GPR32Opnd:$rt) - 67 + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (MTTLO_NM AC0, GPRNM32Opnd:$rt) - 72 + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm) - 76 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureGP64Bit}, + // (NORImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 79 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_Feature, Mips_FeatureGP64Bit}, + // (SLTImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 82 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_Feature, Mips_FeatureGP64Bit}, + // (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 85 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_Feature, Mips_FeatureGP64Bit}, + // (ADDIUGP48_NM GPRNM48Opnd:$rt, GPRNMGPOpnd:$rs, sym32_gp_nm:$addr) - 88 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNMGPRegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (ADDIUGPB_NM GPRNM32Opnd:$rt, GPRNMGPOpnd:$rs, sym32_gp_nm:$offset) - 91 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNMGPRegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (ADDIUGPW_NM GPRNM32Opnd:$rt, GPRNMGPOpnd:$rs, sym32_gp_nm:$offset) - 94 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNMGPRegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (ADDIUPC GPR32Opnd:$rd, simm19_lsl2:$imm) - 97 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm) - 100 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - 103 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureGP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (BC1F FCC0, brtarget:$offset) - 110 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (BC1FL FCC0, brtarget:$offset) - 116 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (BC1F_MM FCC0, brtarget:$offset) - 123 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (BC1T FCC0, brtarget:$offset) - 127 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (BC1TL FCC0, brtarget:$offset) - 133 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (BC1T_MM FCC0, brtarget:$offset) - 140 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (BEQC16_NM GPRNM16R3Opnd:$rs, GPRNM16R3Opnd:$rt, brtarget4s1_nm:$offset) - 144 + {AliasPatternCond_K_RegClass, Mips_GPRNM3RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNM3RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (BEQC_NM GPRNM32Opnd:$rt, ZERO_NM, brtarget14_nm:$offset) - 147 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (BEQC_NM ZERO_NM, GPRNM32Opnd:$rt, brtarget14_nm:$offset) - 150 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset) - 153 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (BGEZAL ZERO, brtarget:$offset) - 159 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (BGEZAL_MM ZERO, brtarget_mm:$offset) - 165 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + // (BNEC16_NM GPRNM16R3Opnd:$rs, GPRNM16R3Opnd:$rt, brtarget4s1_nm:$offset) - 168 + {AliasPatternCond_K_RegClass, Mips_GPRNM3RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNM3RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (BNEC_NM GPRNM32Opnd:$rt, ZERO_NM, brtarget14_nm:$offset) - 171 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (BNEC_NM ZERO_NM, GPRNM32Opnd:$rt, brtarget14_nm:$offset) - 174 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset) - 177 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (BREAK 0, 0) - 183 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (BREAK uimm10:$imm, 0) - 188 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (BREAK_MM 0, 0) - 193 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (BREAK_MM uimm10:$imm, 0) - 196 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (C_EQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 199 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_EQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 208 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_EQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 215 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_EQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 224 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_EQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 231 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_EQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 239 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_F_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 245 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_F_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 254 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_F_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 261 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_F_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 270 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_F_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 277 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_F_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 285 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_LE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 291 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_LE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 300 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_LE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 307 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_LE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 316 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_LE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 323 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_LE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 331 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_LT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 337 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_LT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 346 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_LT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 353 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_LT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 362 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_LT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 369 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_LT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 377 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 383 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 392 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 399 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 408 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 415 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 423 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 429 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 438 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 445 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 454 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 461 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 469 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGL_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 475 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGL_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 484 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGL_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 491 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGL_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 500 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGL_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 507 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGL_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 515 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 521 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 530 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 537 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 546 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_NGT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 553 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_NGT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 561 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_OLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 567 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_OLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 576 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_OLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 583 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_OLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 592 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_OLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 599 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_OLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 607 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_OLT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 613 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_OLT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 622 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_OLT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 629 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_OLT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 638 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_OLT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 645 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_OLT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 653 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_SEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 659 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_SEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 668 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_SEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 675 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_SEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 684 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_SEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 691 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_SEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 699 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_SF_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 705 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_SF_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 714 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_SF_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 721 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_SF_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 730 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_SF_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 737 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_SF_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 745 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_UEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 751 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_UEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 760 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_UEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 767 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_UEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 776 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_UEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 783 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_UEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 791 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_ULE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 797 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_ULE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 806 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_ULE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 813 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_ULE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 822 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_ULE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 829 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_ULE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 837 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_ULT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 843 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_ULT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 852 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_ULT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 859 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_ULT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 868 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_ULT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 875 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_ULT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 883 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_UN_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 889 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_UN_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 898 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_UN_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 905 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_UN_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 914 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureFP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (C_UN_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 921 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (C_UN_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 929 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureSoftFloat}, + // (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - 935 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_Feature, Mips_FeatureGP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (DI ZERO) - 940 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (DIV GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt) - 945 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt) - 950 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (DI_MM ZERO) - 955 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (DI_MMR6 ZERO) - 957 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (DI_NM ZERO_NM) - 960 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (DMT ZERO) - 962 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (DMT_NM ZERO_NM) - 966 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs) - 969 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips3}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt) - 975 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips3}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs) - 981 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips3}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt) - 987 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips3}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (DVPE ZERO) - 993 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (DVPE_NM ZERO_NM) - 997 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (EI ZERO) - 1000 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (EI_MM ZERO) - 1005 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (EI_MMR6 ZERO) - 1007 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (EI_NM ZERO_NM) - 1010 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (EMT ZERO) - 1012 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (EMT_NM ZERO_NM) - 1016 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (EVPE ZERO) - 1019 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (EVPE_NM ZERO_NM) - 1023 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + // (HYPCALL 0) - 1026 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r5}, + {AliasPatternCond_K_Feature, Mips_FeatureVirt}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (HYPCALL_MM 0) - 1032 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r5}, + {AliasPatternCond_K_Feature, Mips_FeatureVirt}, + // (JALR ZERO, GPR32Opnd:$rs) - 1036 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureGP64Bit}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (JALR64 ZERO_64, GPR64Opnd:$rs) - 1042 + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips64r6}, + // (JALRCHB_NM ZERO_NM, GPRNM32Opnd:$rs) - 1046 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (JALRC_HB_MMR6 RA, GPR32Opnd:$rs) - 1049 + {AliasPatternCond_K_Reg, Mips_RA}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (JALRC_MMR6 RA, GPR32Opnd:$rs) - 1053 + {AliasPatternCond_K_Reg, Mips_RA}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (JALR_HB RA, GPR32Opnd:$rs) - 1057 + {AliasPatternCond_K_Reg, Mips_RA}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (JALR_HB64 RA_64, GPR64Opnd:$rs) - 1063 + {AliasPatternCond_K_Reg, Mips_RA_64}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips64}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (JIALC GPR32Opnd:$rs, 0) - 1068 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureGP64Bit}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (JIALC64 GPR64Opnd:$rs, 0) - 1074 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips64r6}, + // (JIC GPR32Opnd:$rs, 0) - 1078 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureGP64Bit}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (JIC64 GPR64Opnd:$rs, 0) - 1083 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips64r6}, + // (MFC0_NM GPRNM32Opnd:$rt, COP0Opnd:$c0s, 0) - 1087 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (MFHC0_NM GPRNM32Opnd:$rt, COP0Opnd:$c0s, 0) - 1091 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (MOVE16_MM ZERO, ZERO) - 1095 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (MTC0_NM GPRNM32Opnd:$rt, COP0Opnd:$c0s, 0) - 1098 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (MTHC0_NM GPRNM32Opnd:$rt, COP0Opnd:$c0s, 0) - 1102 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (Move32R16 ZERO, S0) - 1106 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_S0}, + {AliasPatternCond_K_Feature, Mips_FeatureMips16}, + // (NOR_NM GPRNM32Opnd:$rt, GPRNM32Opnd:$rs, ZERO_NM) - 1109 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - 1113 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureGP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - 1120 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_Feature, Mips_FeatureGP64Bit}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (RDHWR GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1125 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_HWRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0) - 1131 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_HWRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureGP64Bit}, + // (RDHWR_MM GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1135 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_HWRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + // (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1140 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_HWRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (RESTOREJRC16_NM uimm8s4_nm:$adj, 0) - 1145 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (RESTOREJRC_NM uimm12s3_nm:$adj, 0) - 1147 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (RESTORE_NM uimm12s3_nm:$adj, 0) - 1149 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ROTX_NM GPRNM32Opnd:$rt, GPRNM32Opnd:$rs, 7, 8, 1) - 1151 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (ROTX_NM GPRNM32Opnd:$rt, GPRNM32Opnd:$rs, 15, 16, 0) - 1157 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Imm, (uint32_t)16}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (ROTX_NM GPRNM32Opnd:$rt, GPRNM32Opnd:$rs, 8, 24, 0) - 1163 + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Imm, (uint32_t)24}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (SAVE16_NM uimm8s4_nm:$adj, 0) - 1169 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SAVE_NM uimm12s3_nm:$adj, 0) - 1171 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SDBBP 0) - 1173 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips64r6}, + // (SDBBP_MMR6 0) - 1178 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (SDBBP_R6 0) - 1181 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (SIGRIE 0) - 1185 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (SIGRIE_MMR6 0) - 1189 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (SLL ZERO, ZERO, 0) - 1192 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (SLL_MM ZERO, ZERO, 0) - 1198 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (SLL_MMR6 ZERO, ZERO, 0) - 1202 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1207 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1213 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1219 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1224 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1229 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + // (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1234 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + // (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1239 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1244 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1249 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1255 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1261 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + // (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1266 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips32r6}, + // (SWSP_MM GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset) - 1271 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (SYNC 0) - 1273 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (SYNC_MM 0) - 1278 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (SYNC_MMR6 0) - 1280 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMips32r6}, + // (SYNC_NM 0) - 1283 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (SYNC_NM 4) - 1285 + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (SYNC_NM 16) - 1287 + {AliasPatternCond_K_Imm, (uint32_t)16}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (SYNC_NM 17) - 1289 + {AliasPatternCond_K_Imm, (uint32_t)17}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (SYNC_NM 18) - 1291 + {AliasPatternCond_K_Imm, (uint32_t)18}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (SYNC_NM 19) - 1293 + {AliasPatternCond_K_Imm, (uint32_t)19}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (SYSCALL 0) - 1295 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (SYSCALL_MM 0) - 1299 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1301 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1308 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1312 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1319 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1326 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1330 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1334 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1341 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1348 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1352 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1356 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMips16}, + {AliasPatternCond_K_Feature, Mips_FeatureMips2}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1363 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (WAIT_MM 0) - 1367 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (WAIT_NM 0) - 1369 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + // (WRDSP GPR32Opnd:$rt, 31) - 1371 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Feature, Mips_FeatureDSP}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + // (WRDSP_MM GPR32Opnd:$rt, 31) - 1375 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Feature, Mips_FeatureDSP}, + {AliasPatternCond_K_Feature, Mips_FeatureMicroMips}, + // (YIELD ZERO, GPR32Opnd:$rs) - 1379 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {AliasPatternCond_K_NegFeature, Mips_FeatureMicroMips}, + {AliasPatternCond_K_NegFeature, Mips_FeatureNanoMips}, + // (YIELD_NM ZERO_NM, GPRNM32Opnd:$rs) - 1384 + {AliasPatternCond_K_Reg, Mips_ZERO_NM}, + {AliasPatternCond_K_RegClass, Mips_GPRNM32RegClassID}, + {AliasPatternCond_K_Feature, Mips_FeatureNanoMips}, + {AliasPatternCond_K_Feature, Mips_FeatureMT}, + {0}, }; + + static const char AsmStrings[] = + /* 0 */ "mftacx $\x01\0" + /* 10 */ "mftc0 $\x01, $\x02\0" + /* 23 */ "mfthi $\x01\0" + /* 32 */ "mftlo $\x01\0" + /* 41 */ "mttacx $\x02\0" + /* 51 */ "mttc0 $\x02, $\x01\0" + /* 64 */ "mtthi $\x02\0" + /* 73 */ "mttlo $\x02\0" + /* 82 */ "nor $\x01, $\x03\0" + /* 93 */ "slt $\x01, $\x03\0" + /* 104 */ "sltu $\x01, $\x03\0" + /* 116 */ "addiu.b32 $\x01, $\x02, $\x03\0" + /* 137 */ "addiu.b $\x01, $\x02, $\x03\0" + /* 156 */ "addiu.w $\x01, $\x02, $\x03\0" + /* 175 */ "lapc $\x01, $\x02\0" + /* 187 */ "move $\x01, $\x02\0" + /* 199 */ "bc1f $\xFF\x02\x01\0" + /* 209 */ "bc1fl $\xFF\x02\x01\0" + /* 220 */ "bc1t $\xFF\x02\x01\0" + /* 230 */ "bc1tl $\xFF\x02\x01\0" + /* 241 */ "beqc $\x02, $\x01, $\xFF\x03\x01\0" + /* 259 */ "beqzc $\x01, $\xFF\x03\x01\0" + /* 274 */ "beqzc $\x02, $\xFF\x03\x01\0" + /* 289 */ "beqzl $\x01, $\xFF\x03\x01\0" + /* 304 */ "bal $\xFF\x02\x01\0" + /* 313 */ "bnec $\x02, $\x01, $\xFF\x03\x01\0" + /* 331 */ "bnezc $\x01, $\xFF\x03\x01\0" + /* 346 */ "bnezc $\x02, $\xFF\x03\x01\0" + /* 361 */ "bnezl $\x01, $\xFF\x03\x01\0" + /* 376 */ "break\0" + /* 382 */ "break $\xFF\x01\x02\0" + /* 393 */ "c.eq.d $\x02, $\x03\0" + /* 407 */ "c.eq.s $\x02, $\x03\0" + /* 421 */ "c.f.d $\x02, $\x03\0" + /* 434 */ "c.f.s $\x02, $\x03\0" + /* 447 */ "c.le.d $\x02, $\x03\0" + /* 461 */ "c.le.s $\x02, $\x03\0" + /* 475 */ "c.lt.d $\x02, $\x03\0" + /* 489 */ "c.lt.s $\x02, $\x03\0" + /* 503 */ "c.nge.d $\x02, $\x03\0" + /* 518 */ "c.nge.s $\x02, $\x03\0" + /* 533 */ "c.ngle.d $\x02, $\x03\0" + /* 549 */ "c.ngle.s $\x02, $\x03\0" + /* 565 */ "c.ngl.d $\x02, $\x03\0" + /* 580 */ "c.ngl.s $\x02, $\x03\0" + /* 595 */ "c.ngt.d $\x02, $\x03\0" + /* 610 */ "c.ngt.s $\x02, $\x03\0" + /* 625 */ "c.ole.d $\x02, $\x03\0" + /* 640 */ "c.ole.s $\x02, $\x03\0" + /* 655 */ "c.olt.d $\x02, $\x03\0" + /* 670 */ "c.olt.s $\x02, $\x03\0" + /* 685 */ "c.seq.d $\x02, $\x03\0" + /* 700 */ "c.seq.s $\x02, $\x03\0" + /* 715 */ "c.sf.d $\x02, $\x03\0" + /* 729 */ "c.sf.s $\x02, $\x03\0" + /* 743 */ "c.ueq.d $\x02, $\x03\0" + /* 758 */ "c.ueq.s $\x02, $\x03\0" + /* 773 */ "c.ule.d $\x02, $\x03\0" + /* 788 */ "c.ule.s $\x02, $\x03\0" + /* 803 */ "c.ult.d $\x02, $\x03\0" + /* 818 */ "c.ult.s $\x02, $\x03\0" + /* 833 */ "c.un.d $\x02, $\x03\0" + /* 847 */ "c.un.s $\x02, $\x03\0" + /* 861 */ "di\0" + /* 864 */ "div $\x01, $\x03\0" + /* 875 */ "divu $\x01, $\x03\0" + /* 887 */ "dmt\0" + /* 891 */ "dneg $\x01, $\x03\0" + /* 903 */ "dneg $\x01\0" + /* 911 */ "dnegu $\x01, $\x03\0" + /* 924 */ "dnegu $\x01\0" + /* 933 */ "dvpe\0" + /* 938 */ "ei\0" + /* 941 */ "emt\0" + /* 945 */ "evpe\0" + /* 950 */ "hypcall\0" + /* 958 */ "jr $\x02\0" + /* 964 */ "jrc.hb $\x02\0" + /* 974 */ "jalrc.hb $\x02\0" + /* 986 */ "jalrc $\x02\0" + /* 995 */ "jalr.hb $\x02\0" + /* 1006 */ "jalrc $\x01\0" + /* 1015 */ "jrc $\x01\0" + /* 1022 */ "mfc0 $\x01, $\x02\0" + /* 1034 */ "mfhc0 $\x01, $\x02\0" + /* 1047 */ "nop\0" + /* 1051 */ "mtc0 $\x01, $\x02\0" + /* 1063 */ "mthc0 $\x01, $\x02\0" + /* 1076 */ "not $\x01, $\x02\0" + /* 1087 */ "rdhwr $\x01, $\x02\0" + /* 1100 */ "restore.jrc $\xFF\x01\x03\0" + /* 1117 */ "restore.jrc $\xFF\x01\x04\0" + /* 1134 */ "restore $\xFF\x01\x04\0" + /* 1147 */ "bitrevb $\x01, $\x02\0" + /* 1162 */ "bitrevh $\x01, $\x02\0" + /* 1177 */ "byterevh $\x01, $\x02\0" + /* 1193 */ "save $\xFF\x01\x03\0" + /* 1203 */ "save $\xFF\x01\x04\0" + /* 1213 */ "sdbbp\0" + /* 1219 */ "sigrie\0" + /* 1226 */ "neg $\x01, $\x03\0" + /* 1237 */ "neg $\x01\0" + /* 1244 */ "negu $\x01, $\x03\0" + /* 1256 */ "negu $\x01\0" + /* 1264 */ "sw $\x01, $\xFF\x02\x05\0" + /* 1276 */ "sync\0" + /* 1281 */ "sync_wmb\0" + /* 1290 */ "sync_mb\0" + /* 1298 */ "sync_acquire\0" + /* 1311 */ "sync_release\0" + /* 1324 */ "sync_rmb\0" + /* 1333 */ "syscall\0" + /* 1341 */ "teq $\x01, $\x02\0" + /* 1352 */ "tge $\x01, $\x02\0" + /* 1363 */ "tgeu $\x01, $\x02\0" + /* 1375 */ "tlt $\x01, $\x02\0" + /* 1386 */ "tltu $\x01, $\x02\0" + /* 1398 */ "tne $\x01, $\x02\0" + /* 1409 */ "wait\0" + /* 1414 */ "wrdsp $\x01\0" + /* 1423 */ "yield $\x02\0" + ; + +#ifndef NDEBUG + //static struct SortCheck { + // SortCheck(ArrayRef OpToPatterns) { + // assert(std::is_sorted( + // OpToPatterns.begin(), OpToPatterns.end(), + // [](const PatternsForOpcode &L, const //PatternsForOpcode &R) { + // return L.Opcode < R.Opcode; + // }) && + // "tablegen failed to sort opcode patterns"); + // } + //} sortCheckVar(OpToPatterns); +#endif + + AliasMatchingData M = { + OpToPatterns, + Patterns, + Conds, + AsmStrings, + NULL, + }; + const char *AsmString = matchAliasPatterns(MI, &M); + if (!AsmString) return false; + + unsigned I = 0; + while (AsmString[I] != ' ' && AsmString[I] != '\t' && + AsmString[I] != '$' && AsmString[I] != '\0') + ++I; + SStream_concat1(OS, '\t'); + char *substr = malloc(I+1); + memcpy(substr, AsmString, I); + substr[I] = '\0'; + SStream_concat0(OS, substr); + free(substr); + if (AsmString[I] != '\0') { + if (AsmString[I] == ' ' || AsmString[I] == '\t') { + SStream_concat1(OS, '\t'); + ++I; } - } - SStream_concat0(OS, AsmMnem); - if (*AsmOps) { - SStream_concat0(OS, "\t"); - for (c = AsmOps; *c; c++) { - if (*c == '$') { - c += 1; - if (*c == (char)0xff) { - c += 1; - OpIdx = *c - 1; - c += 1; - PrintMethodIdx = *c - 1; - printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); + do { + if (AsmString[I] == '$') { + ++I; + if (AsmString[I] == (char)0xff) { + ++I; + int OpIdx = AsmString[I++] - 1; + int PrintMethodIdx = AsmString[I++] - 1; + printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, OS); } else - printOperand(MI, *c - 1, OS); + printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS); } else { - SStream_concat(OS, "%c", *c); + SStream_concat1(OS, AsmString[I++]); } - } + } while (AsmString[I] != '\0'); + } + + return true; +#else + return false; +#endif // CAPSTONE_DIET +} + +static void printCustomAliasOperand( + MCInst *MI, uint64_t Address, unsigned OpIdx, + unsigned PrintMethodIdx, + SStream *OS) { +#ifndef CAPSTONE_DIET + switch (PrintMethodIdx) { + default: + assert(0 && "Unknown PrintMethod kind"); + break; + case 0: + printBranchOperand(MI, Address, OpIdx, OS); + break; + case 1: + printUImm_10_0(MI, OpIdx, OS); + break; + case 2: + printUImm_8_0(MI, OpIdx, OS); + break; + case 3: + printUImm_12_0(MI, OpIdx, OS); + break; + case 4: + printMemOperand(MI, OpIdx, OS); + break; } - return tmp; +#endif // CAPSTONE_DIET } #endif // PRINT_ALIAS_INSTR diff --git a/arch/Mips/MipsGenCSAliasEnum.inc b/arch/Mips/MipsGenCSAliasEnum.inc new file mode 100644 index 0000000000..95cd4e60c5 --- /dev/null +++ b/arch/Mips/MipsGenCSAliasEnum.inc @@ -0,0 +1,119 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + + MIPS_INS_ALIAS_ADDIU_B32, // Real instr.: MIPS_ADDIUGP48_NM + MIPS_INS_ALIAS_BITREVB, // Real instr.: MIPS_ROTX_NM + MIPS_INS_ALIAS_BITREVH, // Real instr.: MIPS_ROTX_NM + MIPS_INS_ALIAS_BYTEREVH, // Real instr.: MIPS_ROTX_NM + MIPS_INS_ALIAS_NOT, // Real instr.: MIPS_NOR_NM + MIPS_INS_ALIAS_RESTORE_JRC, // Real instr.: MIPS_RESTOREJRC16_NM + MIPS_INS_ALIAS_RESTORE, // Real instr.: MIPS_RESTORE_NM + MIPS_INS_ALIAS_SAVE, // Real instr.: MIPS_SAVE16_NM + MIPS_INS_ALIAS_MOVE, // Real instr.: MIPS_OR + MIPS_INS_ALIAS_BAL, // Real instr.: MIPS_BGEZAL + MIPS_INS_ALIAS_JALR_HB, // Real instr.: MIPS_JALR_HB + MIPS_INS_ALIAS_NEG, // Real instr.: MIPS_SUB + MIPS_INS_ALIAS_NEGU, // Real instr.: MIPS_SUBu + MIPS_INS_ALIAS_NOP, // Real instr.: MIPS_SLL + MIPS_INS_ALIAS_BNEZL, // Real instr.: MIPS_BNEL + MIPS_INS_ALIAS_BEQZL, // Real instr.: MIPS_BEQL + MIPS_INS_ALIAS_SYSCALL, // Real instr.: MIPS_SYSCALL + MIPS_INS_ALIAS_BREAK, // Real instr.: MIPS_BREAK + MIPS_INS_ALIAS_EI, // Real instr.: MIPS_EI + MIPS_INS_ALIAS_DI, // Real instr.: MIPS_DI + MIPS_INS_ALIAS_TEQ, // Real instr.: MIPS_TEQ + MIPS_INS_ALIAS_TGE, // Real instr.: MIPS_TGE + MIPS_INS_ALIAS_TGEU, // Real instr.: MIPS_TGEU + MIPS_INS_ALIAS_TLT, // Real instr.: MIPS_TLT + MIPS_INS_ALIAS_TLTU, // Real instr.: MIPS_TLTU + MIPS_INS_ALIAS_TNE, // Real instr.: MIPS_TNE + MIPS_INS_ALIAS_RDHWR, // Real instr.: MIPS_RDHWR + MIPS_INS_ALIAS_SDBBP, // Real instr.: MIPS_SDBBP + MIPS_INS_ALIAS_SYNC, // Real instr.: MIPS_SYNC + MIPS_INS_ALIAS_HYPCALL, // Real instr.: MIPS_HYPCALL + MIPS_INS_ALIAS_NOR, // Real instr.: MIPS_NORImm + MIPS_INS_ALIAS_C_F_S, // Real instr.: MIPS_C_F_S + MIPS_INS_ALIAS_C_UN_S, // Real instr.: MIPS_C_UN_S + MIPS_INS_ALIAS_C_EQ_S, // Real instr.: MIPS_C_EQ_S + MIPS_INS_ALIAS_C_UEQ_S, // Real instr.: MIPS_C_UEQ_S + MIPS_INS_ALIAS_C_OLT_S, // Real instr.: MIPS_C_OLT_S + MIPS_INS_ALIAS_C_ULT_S, // Real instr.: MIPS_C_ULT_S + MIPS_INS_ALIAS_C_OLE_S, // Real instr.: MIPS_C_OLE_S + MIPS_INS_ALIAS_C_ULE_S, // Real instr.: MIPS_C_ULE_S + MIPS_INS_ALIAS_C_SF_S, // Real instr.: MIPS_C_SF_S + MIPS_INS_ALIAS_C_NGLE_S, // Real instr.: MIPS_C_NGLE_S + MIPS_INS_ALIAS_C_SEQ_S, // Real instr.: MIPS_C_SEQ_S + MIPS_INS_ALIAS_C_NGL_S, // Real instr.: MIPS_C_NGL_S + MIPS_INS_ALIAS_C_LT_S, // Real instr.: MIPS_C_LT_S + MIPS_INS_ALIAS_C_NGE_S, // Real instr.: MIPS_C_NGE_S + MIPS_INS_ALIAS_C_LE_S, // Real instr.: MIPS_C_LE_S + MIPS_INS_ALIAS_C_NGT_S, // Real instr.: MIPS_C_NGT_S + MIPS_INS_ALIAS_BC1T, // Real instr.: MIPS_BC1T + MIPS_INS_ALIAS_BC1F, // Real instr.: MIPS_BC1F + MIPS_INS_ALIAS_C_F_D, // Real instr.: MIPS_C_F_D32 + MIPS_INS_ALIAS_C_UN_D, // Real instr.: MIPS_C_UN_D32 + MIPS_INS_ALIAS_C_EQ_D, // Real instr.: MIPS_C_EQ_D32 + MIPS_INS_ALIAS_C_UEQ_D, // Real instr.: MIPS_C_UEQ_D32 + MIPS_INS_ALIAS_C_OLT_D, // Real instr.: MIPS_C_OLT_D32 + MIPS_INS_ALIAS_C_ULT_D, // Real instr.: MIPS_C_ULT_D32 + MIPS_INS_ALIAS_C_OLE_D, // Real instr.: MIPS_C_OLE_D32 + MIPS_INS_ALIAS_C_ULE_D, // Real instr.: MIPS_C_ULE_D32 + MIPS_INS_ALIAS_C_SF_D, // Real instr.: MIPS_C_SF_D32 + MIPS_INS_ALIAS_C_NGLE_D, // Real instr.: MIPS_C_NGLE_D32 + MIPS_INS_ALIAS_C_SEQ_D, // Real instr.: MIPS_C_SEQ_D32 + MIPS_INS_ALIAS_C_NGL_D, // Real instr.: MIPS_C_NGL_D32 + MIPS_INS_ALIAS_C_LT_D, // Real instr.: MIPS_C_LT_D32 + MIPS_INS_ALIAS_C_NGE_D, // Real instr.: MIPS_C_NGE_D32 + MIPS_INS_ALIAS_C_LE_D, // Real instr.: MIPS_C_LE_D32 + MIPS_INS_ALIAS_C_NGT_D, // Real instr.: MIPS_C_NGT_D32 + MIPS_INS_ALIAS_BC1TL, // Real instr.: MIPS_BC1TL + MIPS_INS_ALIAS_BC1FL, // Real instr.: MIPS_BC1FL + MIPS_INS_ALIAS_DNEG, // Real instr.: MIPS_DSUB + MIPS_INS_ALIAS_DNEGU, // Real instr.: MIPS_DSUBu + MIPS_INS_ALIAS_SLT, // Real instr.: MIPS_SLTImm64 + MIPS_INS_ALIAS_SLTU, // Real instr.: MIPS_SLTUImm64 + MIPS_INS_ALIAS_SIGRIE, // Real instr.: MIPS_SIGRIE + MIPS_INS_ALIAS_JR, // Real instr.: MIPS_JALR + MIPS_INS_ALIAS_JRC, // Real instr.: MIPS_JIC + MIPS_INS_ALIAS_JALRC, // Real instr.: MIPS_JIALC + MIPS_INS_ALIAS_DIV, // Real instr.: MIPS_DIV + MIPS_INS_ALIAS_DIVU, // Real instr.: MIPS_DIVU + MIPS_INS_ALIAS_LAPC, // Real instr.: MIPS_ADDIUPC + MIPS_INS_ALIAS_WRDSP, // Real instr.: MIPS_WRDSP + MIPS_INS_ALIAS_WAIT, // Real instr.: MIPS_WAIT_MM + MIPS_INS_ALIAS_SW, // Real instr.: MIPS_SWSP_MM + MIPS_INS_ALIAS_JALRC_HB, // Real instr.: MIPS_JALRC_HB_MMR6 + MIPS_INS_ALIAS_ADDIU_B, // Real instr.: MIPS_ADDIUGPB_NM + MIPS_INS_ALIAS_ADDIU_W, // Real instr.: MIPS_ADDIUGPW_NM + MIPS_INS_ALIAS_JRC_HB, // Real instr.: MIPS_JALRCHB_NM + MIPS_INS_ALIAS_BEQC, // Real instr.: MIPS_BEQC16_NM + MIPS_INS_ALIAS_BNEC, // Real instr.: MIPS_BNEC16_NM + MIPS_INS_ALIAS_BEQZC, // Real instr.: MIPS_BEQC_NM + MIPS_INS_ALIAS_BNEZC, // Real instr.: MIPS_BNEC_NM + MIPS_INS_ALIAS_MFC0, // Real instr.: MIPS_MFC0_NM + MIPS_INS_ALIAS_MFHC0, // Real instr.: MIPS_MFHC0_NM + MIPS_INS_ALIAS_MTC0, // Real instr.: MIPS_MTC0_NM + MIPS_INS_ALIAS_MTHC0, // Real instr.: MIPS_MTHC0_NM + MIPS_INS_ALIAS_DMT, // Real instr.: MIPS_DMT + MIPS_INS_ALIAS_EMT, // Real instr.: MIPS_EMT + MIPS_INS_ALIAS_DVPE, // Real instr.: MIPS_DVPE + MIPS_INS_ALIAS_EVPE, // Real instr.: MIPS_EVPE + MIPS_INS_ALIAS_YIELD, // Real instr.: MIPS_YIELD + MIPS_INS_ALIAS_MFTC0, // Real instr.: MIPS_MFTC0 + MIPS_INS_ALIAS_MFTLO, // Real instr.: MIPS_MFTLO + MIPS_INS_ALIAS_MFTHI, // Real instr.: MIPS_MFTHI + MIPS_INS_ALIAS_MFTACX, // Real instr.: MIPS_MFTACX + MIPS_INS_ALIAS_MTTC0, // Real instr.: MIPS_MTTC0 + MIPS_INS_ALIAS_MTTLO, // Real instr.: MIPS_MTTLO + MIPS_INS_ALIAS_MTTHI, // Real instr.: MIPS_MTTHI + MIPS_INS_ALIAS_MTTACX, // Real instr.: MIPS_MTTACX diff --git a/arch/Mips/MipsGenCSAliasMnemMap.inc b/arch/Mips/MipsGenCSAliasMnemMap.inc new file mode 100644 index 0000000000..08b93c9ed2 --- /dev/null +++ b/arch/Mips/MipsGenCSAliasMnemMap.inc @@ -0,0 +1,119 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + + { MIPS_INS_ALIAS_ADDIU_B32, "addiu_b32" }, + { MIPS_INS_ALIAS_BITREVB, "bitrevb" }, + { MIPS_INS_ALIAS_BITREVH, "bitrevh" }, + { MIPS_INS_ALIAS_BYTEREVH, "byterevh" }, + { MIPS_INS_ALIAS_NOT, "not" }, + { MIPS_INS_ALIAS_RESTORE_JRC, "restore_jrc" }, + { MIPS_INS_ALIAS_RESTORE, "restore" }, + { MIPS_INS_ALIAS_SAVE, "save" }, + { MIPS_INS_ALIAS_MOVE, "move" }, + { MIPS_INS_ALIAS_BAL, "bal" }, + { MIPS_INS_ALIAS_JALR_HB, "jalr_hb" }, + { MIPS_INS_ALIAS_NEG, "neg" }, + { MIPS_INS_ALIAS_NEGU, "negu" }, + { MIPS_INS_ALIAS_NOP, "nop" }, + { MIPS_INS_ALIAS_BNEZL, "bnezl" }, + { MIPS_INS_ALIAS_BEQZL, "beqzl" }, + { MIPS_INS_ALIAS_SYSCALL, "syscall" }, + { MIPS_INS_ALIAS_BREAK, "break" }, + { MIPS_INS_ALIAS_EI, "ei" }, + { MIPS_INS_ALIAS_DI, "di" }, + { MIPS_INS_ALIAS_TEQ, "teq" }, + { MIPS_INS_ALIAS_TGE, "tge" }, + { MIPS_INS_ALIAS_TGEU, "tgeu" }, + { MIPS_INS_ALIAS_TLT, "tlt" }, + { MIPS_INS_ALIAS_TLTU, "tltu" }, + { MIPS_INS_ALIAS_TNE, "tne" }, + { MIPS_INS_ALIAS_RDHWR, "rdhwr" }, + { MIPS_INS_ALIAS_SDBBP, "sdbbp" }, + { MIPS_INS_ALIAS_SYNC, "sync" }, + { MIPS_INS_ALIAS_HYPCALL, "hypcall" }, + { MIPS_INS_ALIAS_NOR, "nor" }, + { MIPS_INS_ALIAS_C_F_S, "c_f_s" }, + { MIPS_INS_ALIAS_C_UN_S, "c_un_s" }, + { MIPS_INS_ALIAS_C_EQ_S, "c_eq_s" }, + { MIPS_INS_ALIAS_C_UEQ_S, "c_ueq_s" }, + { MIPS_INS_ALIAS_C_OLT_S, "c_olt_s" }, + { MIPS_INS_ALIAS_C_ULT_S, "c_ult_s" }, + { MIPS_INS_ALIAS_C_OLE_S, "c_ole_s" }, + { MIPS_INS_ALIAS_C_ULE_S, "c_ule_s" }, + { MIPS_INS_ALIAS_C_SF_S, "c_sf_s" }, + { MIPS_INS_ALIAS_C_NGLE_S, "c_ngle_s" }, + { MIPS_INS_ALIAS_C_SEQ_S, "c_seq_s" }, + { MIPS_INS_ALIAS_C_NGL_S, "c_ngl_s" }, + { MIPS_INS_ALIAS_C_LT_S, "c_lt_s" }, + { MIPS_INS_ALIAS_C_NGE_S, "c_nge_s" }, + { MIPS_INS_ALIAS_C_LE_S, "c_le_s" }, + { MIPS_INS_ALIAS_C_NGT_S, "c_ngt_s" }, + { MIPS_INS_ALIAS_BC1T, "bc1t" }, + { MIPS_INS_ALIAS_BC1F, "bc1f" }, + { MIPS_INS_ALIAS_C_F_D, "c_f_d" }, + { MIPS_INS_ALIAS_C_UN_D, "c_un_d" }, + { MIPS_INS_ALIAS_C_EQ_D, "c_eq_d" }, + { MIPS_INS_ALIAS_C_UEQ_D, "c_ueq_d" }, + { MIPS_INS_ALIAS_C_OLT_D, "c_olt_d" }, + { MIPS_INS_ALIAS_C_ULT_D, "c_ult_d" }, + { MIPS_INS_ALIAS_C_OLE_D, "c_ole_d" }, + { MIPS_INS_ALIAS_C_ULE_D, "c_ule_d" }, + { MIPS_INS_ALIAS_C_SF_D, "c_sf_d" }, + { MIPS_INS_ALIAS_C_NGLE_D, "c_ngle_d" }, + { MIPS_INS_ALIAS_C_SEQ_D, "c_seq_d" }, + { MIPS_INS_ALIAS_C_NGL_D, "c_ngl_d" }, + { MIPS_INS_ALIAS_C_LT_D, "c_lt_d" }, + { MIPS_INS_ALIAS_C_NGE_D, "c_nge_d" }, + { MIPS_INS_ALIAS_C_LE_D, "c_le_d" }, + { MIPS_INS_ALIAS_C_NGT_D, "c_ngt_d" }, + { MIPS_INS_ALIAS_BC1TL, "bc1tl" }, + { MIPS_INS_ALIAS_BC1FL, "bc1fl" }, + { MIPS_INS_ALIAS_DNEG, "dneg" }, + { MIPS_INS_ALIAS_DNEGU, "dnegu" }, + { MIPS_INS_ALIAS_SLT, "slt" }, + { MIPS_INS_ALIAS_SLTU, "sltu" }, + { MIPS_INS_ALIAS_SIGRIE, "sigrie" }, + { MIPS_INS_ALIAS_JR, "jr" }, + { MIPS_INS_ALIAS_JRC, "jrc" }, + { MIPS_INS_ALIAS_JALRC, "jalrc" }, + { MIPS_INS_ALIAS_DIV, "div" }, + { MIPS_INS_ALIAS_DIVU, "divu" }, + { MIPS_INS_ALIAS_LAPC, "lapc" }, + { MIPS_INS_ALIAS_WRDSP, "wrdsp" }, + { MIPS_INS_ALIAS_WAIT, "wait" }, + { MIPS_INS_ALIAS_SW, "sw" }, + { MIPS_INS_ALIAS_JALRC_HB, "jalrc_hb" }, + { MIPS_INS_ALIAS_ADDIU_B, "addiu_b" }, + { MIPS_INS_ALIAS_ADDIU_W, "addiu_w" }, + { MIPS_INS_ALIAS_JRC_HB, "jrc_hb" }, + { MIPS_INS_ALIAS_BEQC, "beqc" }, + { MIPS_INS_ALIAS_BNEC, "bnec" }, + { MIPS_INS_ALIAS_BEQZC, "beqzc" }, + { MIPS_INS_ALIAS_BNEZC, "bnezc" }, + { MIPS_INS_ALIAS_MFC0, "mfc0" }, + { MIPS_INS_ALIAS_MFHC0, "mfhc0" }, + { MIPS_INS_ALIAS_MTC0, "mtc0" }, + { MIPS_INS_ALIAS_MTHC0, "mthc0" }, + { MIPS_INS_ALIAS_DMT, "dmt" }, + { MIPS_INS_ALIAS_EMT, "emt" }, + { MIPS_INS_ALIAS_DVPE, "dvpe" }, + { MIPS_INS_ALIAS_EVPE, "evpe" }, + { MIPS_INS_ALIAS_YIELD, "yield" }, + { MIPS_INS_ALIAS_MFTC0, "mftc0" }, + { MIPS_INS_ALIAS_MFTLO, "mftlo" }, + { MIPS_INS_ALIAS_MFTHI, "mfthi" }, + { MIPS_INS_ALIAS_MFTACX, "mftacx" }, + { MIPS_INS_ALIAS_MTTC0, "mttc0" }, + { MIPS_INS_ALIAS_MTTLO, "mttlo" }, + { MIPS_INS_ALIAS_MTTHI, "mtthi" }, + { MIPS_INS_ALIAS_MTTACX, "mttacx" }, diff --git a/arch/Mips/MipsGenCSFeatureEnum.inc b/arch/Mips/MipsGenCSFeatureEnum.inc new file mode 100644 index 0000000000..46928ceb52 --- /dev/null +++ b/arch/Mips/MipsGenCSFeatureEnum.inc @@ -0,0 +1,69 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +MIPS_FEATURE_HASMIPS2 = 128, +MIPS_FEATURE_HASMIPS3_32, +MIPS_FEATURE_HASMIPS3_32R2, +MIPS_FEATURE_HASMIPS3, +MIPS_FEATURE_NOTMIPS3, +MIPS_FEATURE_HASMIPS4_32, +MIPS_FEATURE_NOTMIPS4_32, +MIPS_FEATURE_HASMIPS4_32R2, +MIPS_FEATURE_HASMIPS5_32R2, +MIPS_FEATURE_HASMIPS32, +MIPS_FEATURE_HASMIPS32R2, +MIPS_FEATURE_HASMIPS32R5, +MIPS_FEATURE_HASMIPS32R6, +MIPS_FEATURE_NOTMIPS32R6, +MIPS_FEATURE_HASNANOMIPS, +MIPS_FEATURE_NOTNANOMIPS, +MIPS_FEATURE_ISGP64BIT, +MIPS_FEATURE_ISGP32BIT, +MIPS_FEATURE_ISPTR64BIT, +MIPS_FEATURE_ISPTR32BIT, +MIPS_FEATURE_HASMIPS64, +MIPS_FEATURE_NOTMIPS64, +MIPS_FEATURE_HASMIPS64R2, +MIPS_FEATURE_HASMIPS64R5, +MIPS_FEATURE_HASMIPS64R6, +MIPS_FEATURE_NOTMIPS64R6, +MIPS_FEATURE_INMIPS16MODE, +MIPS_FEATURE_NOTINMIPS16MODE, +MIPS_FEATURE_HASCNMIPS, +MIPS_FEATURE_NOTCNMIPS, +MIPS_FEATURE_HASCNMIPSP, +MIPS_FEATURE_NOTCNMIPSP, +MIPS_FEATURE_ISSYM32, +MIPS_FEATURE_ISSYM64, +MIPS_FEATURE_HASSTDENC, +MIPS_FEATURE_INMICROMIPS, +MIPS_FEATURE_NOTINMICROMIPS, +MIPS_FEATURE_HASEVA, +MIPS_FEATURE_HASMSA, +MIPS_FEATURE_HASMADD4, +MIPS_FEATURE_HASMT, +MIPS_FEATURE_USEINDIRECTJUMPSHAZARD, +MIPS_FEATURE_NOINDIRECTJUMPGUARDS, +MIPS_FEATURE_HASCRC, +MIPS_FEATURE_HASVIRT, +MIPS_FEATURE_HASGINV, +MIPS_FEATURE_HASTLB, +MIPS_FEATURE_ISFP64BIT, +MIPS_FEATURE_NOTFP64BIT, +MIPS_FEATURE_ISSINGLEFLOAT, +MIPS_FEATURE_ISNOTSINGLEFLOAT, +MIPS_FEATURE_ISNOTSOFTFLOAT, +MIPS_FEATURE_HASMIPS3D, +MIPS_FEATURE_HASDSP, +MIPS_FEATURE_HASDSPR2, +MIPS_FEATURE_HASDSPR3, diff --git a/arch/Mips/MipsGenCSFeatureName.inc b/arch/Mips/MipsGenCSFeatureName.inc new file mode 100644 index 0000000000..495cc3f216 --- /dev/null +++ b/arch/Mips/MipsGenCSFeatureName.inc @@ -0,0 +1,69 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +{ MIPS_FEATURE_HASMIPS2, "HasMips2" }, +{ MIPS_FEATURE_HASMIPS3_32, "HasMips3_32" }, +{ MIPS_FEATURE_HASMIPS3_32R2, "HasMips3_32r2" }, +{ MIPS_FEATURE_HASMIPS3, "HasMips3" }, +{ MIPS_FEATURE_NOTMIPS3, "NotMips3" }, +{ MIPS_FEATURE_HASMIPS4_32, "HasMips4_32" }, +{ MIPS_FEATURE_NOTMIPS4_32, "NotMips4_32" }, +{ MIPS_FEATURE_HASMIPS4_32R2, "HasMips4_32r2" }, +{ MIPS_FEATURE_HASMIPS5_32R2, "HasMips5_32r2" }, +{ MIPS_FEATURE_HASMIPS32, "HasMips32" }, +{ MIPS_FEATURE_HASMIPS32R2, "HasMips32r2" }, +{ MIPS_FEATURE_HASMIPS32R5, "HasMips32r5" }, +{ MIPS_FEATURE_HASMIPS32R6, "HasMips32r6" }, +{ MIPS_FEATURE_NOTMIPS32R6, "NotMips32r6" }, +{ MIPS_FEATURE_HASNANOMIPS, "HasNanoMips" }, +{ MIPS_FEATURE_NOTNANOMIPS, "NotNanoMips" }, +{ MIPS_FEATURE_ISGP64BIT, "IsGP64bit" }, +{ MIPS_FEATURE_ISGP32BIT, "IsGP32bit" }, +{ MIPS_FEATURE_ISPTR64BIT, "IsPTR64bit" }, +{ MIPS_FEATURE_ISPTR32BIT, "IsPTR32bit" }, +{ MIPS_FEATURE_HASMIPS64, "HasMips64" }, +{ MIPS_FEATURE_NOTMIPS64, "NotMips64" }, +{ MIPS_FEATURE_HASMIPS64R2, "HasMips64r2" }, +{ MIPS_FEATURE_HASMIPS64R5, "HasMips64r5" }, +{ MIPS_FEATURE_HASMIPS64R6, "HasMips64r6" }, +{ MIPS_FEATURE_NOTMIPS64R6, "NotMips64r6" }, +{ MIPS_FEATURE_INMIPS16MODE, "InMips16Mode" }, +{ MIPS_FEATURE_NOTINMIPS16MODE, "NotInMips16Mode" }, +{ MIPS_FEATURE_HASCNMIPS, "HasCnMips" }, +{ MIPS_FEATURE_NOTCNMIPS, "NotCnMips" }, +{ MIPS_FEATURE_HASCNMIPSP, "HasCnMipsP" }, +{ MIPS_FEATURE_NOTCNMIPSP, "NotCnMipsP" }, +{ MIPS_FEATURE_ISSYM32, "IsSym32" }, +{ MIPS_FEATURE_ISSYM64, "IsSym64" }, +{ MIPS_FEATURE_HASSTDENC, "HasStdEnc" }, +{ MIPS_FEATURE_INMICROMIPS, "InMicroMips" }, +{ MIPS_FEATURE_NOTINMICROMIPS, "NotInMicroMips" }, +{ MIPS_FEATURE_HASEVA, "HasEVA" }, +{ MIPS_FEATURE_HASMSA, "HasMSA" }, +{ MIPS_FEATURE_HASMADD4, "HasMadd4" }, +{ MIPS_FEATURE_HASMT, "HasMT" }, +{ MIPS_FEATURE_USEINDIRECTJUMPSHAZARD, "UseIndirectJumpsHazard" }, +{ MIPS_FEATURE_NOINDIRECTJUMPGUARDS, "NoIndirectJumpGuards" }, +{ MIPS_FEATURE_HASCRC, "HasCRC" }, +{ MIPS_FEATURE_HASVIRT, "HasVirt" }, +{ MIPS_FEATURE_HASGINV, "HasGINV" }, +{ MIPS_FEATURE_HASTLB, "HasTLB" }, +{ MIPS_FEATURE_ISFP64BIT, "IsFP64bit" }, +{ MIPS_FEATURE_NOTFP64BIT, "NotFP64bit" }, +{ MIPS_FEATURE_ISSINGLEFLOAT, "IsSingleFloat" }, +{ MIPS_FEATURE_ISNOTSINGLEFLOAT, "IsNotSingleFloat" }, +{ MIPS_FEATURE_ISNOTSOFTFLOAT, "IsNotSoftFloat" }, +{ MIPS_FEATURE_HASMIPS3D, "HasMips3D" }, +{ MIPS_FEATURE_HASDSP, "HasDSP" }, +{ MIPS_FEATURE_HASDSPR2, "HasDSPR2" }, +{ MIPS_FEATURE_HASDSPR3, "HasDSPR3" }, diff --git a/arch/Mips/MipsGenCSInsnEnum.inc b/arch/Mips/MipsGenCSInsnEnum.inc new file mode 100644 index 0000000000..202f97f4cb --- /dev/null +++ b/arch/Mips/MipsGenCSInsnEnum.inc @@ -0,0 +1,1373 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + + MIPS_INS_INVALID, + MIPS_INS_ABS, + MIPS_INS_ALIGN, + MIPS_INS_BEQL, + MIPS_INS_BGE, + MIPS_INS_BGEL, + MIPS_INS_BGEU, + MIPS_INS_BGEUL, + MIPS_INS_BGT, + MIPS_INS_BGTL, + MIPS_INS_BGTU, + MIPS_INS_BGTUL, + MIPS_INS_BLE, + MIPS_INS_BLEL, + MIPS_INS_BLEU, + MIPS_INS_BLEUL, + MIPS_INS_BLT, + MIPS_INS_BLTL, + MIPS_INS_BLTU, + MIPS_INS_BLTUL, + MIPS_INS_BNEL, + MIPS_INS_B, + MIPS_INS_BEQ, + MIPS_INS_BNE, + MIPS_INS_CFTC1, + MIPS_INS_CTTC1, + MIPS_INS_DMUL, + MIPS_INS_DMULO, + MIPS_INS_DMULOU, + MIPS_INS_DROL, + MIPS_INS_DROR, + MIPS_INS_DDIV, + MIPS_INS_DREM, + MIPS_INS_DDIVU, + MIPS_INS_DREMU, + MIPS_INS_JAL, + MIPS_INS_LD, + MIPS_INS_LWM, + MIPS_INS_LA, + MIPS_INS_DLA, + MIPS_INS_LI, + MIPS_INS_DLI, + MIPS_INS_LI_D, + MIPS_INS_LI_S, + MIPS_INS_MFTACX, + MIPS_INS_MFTC0, + MIPS_INS_MFTC1, + MIPS_INS_MFTDSP, + MIPS_INS_MFTGPR, + MIPS_INS_MFTHC1, + MIPS_INS_MFTHI, + MIPS_INS_MFTLO, + MIPS_INS_MTTACX, + MIPS_INS_MTTC0, + MIPS_INS_MTTC1, + MIPS_INS_MTTDSP, + MIPS_INS_MTTGPR, + MIPS_INS_MTTHC1, + MIPS_INS_MTTHI, + MIPS_INS_MTTLO, + MIPS_INS_MUL, + MIPS_INS_MULO, + MIPS_INS_MULOU, + MIPS_INS_NOR, + MIPS_INS_ADDIU, + MIPS_INS_ANDI, + MIPS_INS_SUBU, + MIPS_INS_TRUNC_W_D, + MIPS_INS_TRUNC_W_S, + MIPS_INS_ROL, + MIPS_INS_ROR, + MIPS_INS_S_D, + MIPS_INS_SD, + MIPS_INS_DIV, + MIPS_INS_SEQ, + MIPS_INS_SGE, + MIPS_INS_SGEU, + MIPS_INS_SGT, + MIPS_INS_SGTU, + MIPS_INS_SLE, + MIPS_INS_SLEU, + MIPS_INS_SLT, + MIPS_INS_SLTU, + MIPS_INS_SNE, + MIPS_INS_REM, + MIPS_INS_SWM, + MIPS_INS_SAA, + MIPS_INS_SAAD, + MIPS_INS_DIVU, + MIPS_INS_REMU, + MIPS_INS_ULH, + MIPS_INS_ULHU, + MIPS_INS_ULW, + MIPS_INS_USH, + MIPS_INS_USW, + MIPS_INS_ABSQ_S_PH, + MIPS_INS_ABSQ_S_QB, + MIPS_INS_ABSQ_S_W, + MIPS_INS_ADD, + MIPS_INS_ADDIUPC, + MIPS_INS_ADDIUR1SP, + MIPS_INS_ADDIUR2, + MIPS_INS_ADDIUS5, + MIPS_INS_ADDIUSP, + MIPS_INS_ADDQH_PH, + MIPS_INS_ADDQH_R_PH, + MIPS_INS_ADDQH_R_W, + MIPS_INS_ADDQH_W, + MIPS_INS_ADDQ_PH, + MIPS_INS_ADDQ_S_PH, + MIPS_INS_ADDQ_S_W, + MIPS_INS_ADDR_PS, + MIPS_INS_ADDSC, + MIPS_INS_ADDS_A_B, + MIPS_INS_ADDS_A_D, + MIPS_INS_ADDS_A_H, + MIPS_INS_ADDS_A_W, + MIPS_INS_ADDS_S_B, + MIPS_INS_ADDS_S_D, + MIPS_INS_ADDS_S_H, + MIPS_INS_ADDS_S_W, + MIPS_INS_ADDS_U_B, + MIPS_INS_ADDS_U_D, + MIPS_INS_ADDS_U_H, + MIPS_INS_ADDS_U_W, + MIPS_INS_ADDU16, + MIPS_INS_ADDUH_QB, + MIPS_INS_ADDUH_R_QB, + MIPS_INS_ADDU, + MIPS_INS_ADDU_PH, + MIPS_INS_ADDU_QB, + MIPS_INS_ADDU_S_PH, + MIPS_INS_ADDU_S_QB, + MIPS_INS_ADDVI_B, + MIPS_INS_ADDVI_D, + MIPS_INS_ADDVI_H, + MIPS_INS_ADDVI_W, + MIPS_INS_ADDV_B, + MIPS_INS_ADDV_D, + MIPS_INS_ADDV_H, + MIPS_INS_ADDV_W, + MIPS_INS_ADDWC, + MIPS_INS_ADD_A_B, + MIPS_INS_ADD_A_D, + MIPS_INS_ADD_A_H, + MIPS_INS_ADD_A_W, + MIPS_INS_ADDI, + MIPS_INS_ALUIPC, + MIPS_INS_AND, + MIPS_INS_AND16, + MIPS_INS_ANDI16, + MIPS_INS_ANDI_B, + MIPS_INS_AND_V, + MIPS_INS_APPEND, + MIPS_INS_ASUB_S_B, + MIPS_INS_ASUB_S_D, + MIPS_INS_ASUB_S_H, + MIPS_INS_ASUB_S_W, + MIPS_INS_ASUB_U_B, + MIPS_INS_ASUB_U_D, + MIPS_INS_ASUB_U_H, + MIPS_INS_ASUB_U_W, + MIPS_INS_AUI, + MIPS_INS_AUIPC, + MIPS_INS_AVER_S_B, + MIPS_INS_AVER_S_D, + MIPS_INS_AVER_S_H, + MIPS_INS_AVER_S_W, + MIPS_INS_AVER_U_B, + MIPS_INS_AVER_U_D, + MIPS_INS_AVER_U_H, + MIPS_INS_AVER_U_W, + MIPS_INS_AVE_S_B, + MIPS_INS_AVE_S_D, + MIPS_INS_AVE_S_H, + MIPS_INS_AVE_S_W, + MIPS_INS_AVE_U_B, + MIPS_INS_AVE_U_D, + MIPS_INS_AVE_U_H, + MIPS_INS_AVE_U_W, + MIPS_INS_B16, + MIPS_INS_BADDU, + MIPS_INS_BAL, + MIPS_INS_BALC, + MIPS_INS_BALIGN, + MIPS_INS_BALRSC, + MIPS_INS_BBEQZC, + MIPS_INS_BBIT0, + MIPS_INS_BBIT032, + MIPS_INS_BBIT1, + MIPS_INS_BBIT132, + MIPS_INS_BBNEZC, + MIPS_INS_BC, + MIPS_INS_BC16, + MIPS_INS_BC1EQZ, + MIPS_INS_BC1EQZC, + MIPS_INS_BC1F, + MIPS_INS_BC1FL, + MIPS_INS_BC1NEZ, + MIPS_INS_BC1NEZC, + MIPS_INS_BC1T, + MIPS_INS_BC1TL, + MIPS_INS_BC2EQZ, + MIPS_INS_BC2EQZC, + MIPS_INS_BC2NEZ, + MIPS_INS_BC2NEZC, + MIPS_INS_BCLRI_B, + MIPS_INS_BCLRI_D, + MIPS_INS_BCLRI_H, + MIPS_INS_BCLRI_W, + MIPS_INS_BCLR_B, + MIPS_INS_BCLR_D, + MIPS_INS_BCLR_H, + MIPS_INS_BCLR_W, + MIPS_INS_BEQC, + MIPS_INS_BEQIC, + MIPS_INS_BEQZ16, + MIPS_INS_BEQZALC, + MIPS_INS_BEQZC, + MIPS_INS_BEQZC16, + MIPS_INS_BGEC, + MIPS_INS_BGEIC, + MIPS_INS_BGEIUC, + MIPS_INS_BGEUC, + MIPS_INS_BGEZ, + MIPS_INS_BGEZAL, + MIPS_INS_BGEZALC, + MIPS_INS_BGEZALL, + MIPS_INS_BGEZALS, + MIPS_INS_BGEZC, + MIPS_INS_BGEZL, + MIPS_INS_BGTZ, + MIPS_INS_BGTZALC, + MIPS_INS_BGTZC, + MIPS_INS_BGTZL, + MIPS_INS_BINSLI_B, + MIPS_INS_BINSLI_D, + MIPS_INS_BINSLI_H, + MIPS_INS_BINSLI_W, + MIPS_INS_BINSL_B, + MIPS_INS_BINSL_D, + MIPS_INS_BINSL_H, + MIPS_INS_BINSL_W, + MIPS_INS_BINSRI_B, + MIPS_INS_BINSRI_D, + MIPS_INS_BINSRI_H, + MIPS_INS_BINSRI_W, + MIPS_INS_BINSR_B, + MIPS_INS_BINSR_D, + MIPS_INS_BINSR_H, + MIPS_INS_BINSR_W, + MIPS_INS_BITREV, + MIPS_INS_BITREVW, + MIPS_INS_BITSWAP, + MIPS_INS_BLEZ, + MIPS_INS_BLEZALC, + MIPS_INS_BLEZC, + MIPS_INS_BLEZL, + MIPS_INS_BLTC, + MIPS_INS_BLTIC, + MIPS_INS_BLTIUC, + MIPS_INS_BLTUC, + MIPS_INS_BLTZ, + MIPS_INS_BLTZAL, + MIPS_INS_BLTZALC, + MIPS_INS_BLTZALL, + MIPS_INS_BLTZALS, + MIPS_INS_BLTZC, + MIPS_INS_BLTZL, + MIPS_INS_BMNZI_B, + MIPS_INS_BMNZ_V, + MIPS_INS_BMZI_B, + MIPS_INS_BMZ_V, + MIPS_INS_BNEC, + MIPS_INS_BNEGI_B, + MIPS_INS_BNEGI_D, + MIPS_INS_BNEGI_H, + MIPS_INS_BNEGI_W, + MIPS_INS_BNEG_B, + MIPS_INS_BNEG_D, + MIPS_INS_BNEG_H, + MIPS_INS_BNEG_W, + MIPS_INS_BNEIC, + MIPS_INS_BNEZ16, + MIPS_INS_BNEZALC, + MIPS_INS_BNEZC, + MIPS_INS_BNEZC16, + MIPS_INS_BNVC, + MIPS_INS_BNZ_B, + MIPS_INS_BNZ_D, + MIPS_INS_BNZ_H, + MIPS_INS_BNZ_V, + MIPS_INS_BNZ_W, + MIPS_INS_BOVC, + MIPS_INS_BPOSGE32, + MIPS_INS_BPOSGE32C, + MIPS_INS_BREAK, + MIPS_INS_BREAK16, + MIPS_INS_BRSC, + MIPS_INS_BSELI_B, + MIPS_INS_BSEL_V, + MIPS_INS_BSETI_B, + MIPS_INS_BSETI_D, + MIPS_INS_BSETI_H, + MIPS_INS_BSETI_W, + MIPS_INS_BSET_B, + MIPS_INS_BSET_D, + MIPS_INS_BSET_H, + MIPS_INS_BSET_W, + MIPS_INS_BYTEREVW, + MIPS_INS_BZ_B, + MIPS_INS_BZ_D, + MIPS_INS_BZ_H, + MIPS_INS_BZ_V, + MIPS_INS_BZ_W, + MIPS_INS_BEQZ, + MIPS_INS_BNEZ, + MIPS_INS_BTEQZ, + MIPS_INS_BTNEZ, + MIPS_INS_CACHE, + MIPS_INS_CACHEE, + MIPS_INS_CEIL_L_D, + MIPS_INS_CEIL_L_S, + MIPS_INS_CEIL_W_D, + MIPS_INS_CEIL_W_S, + MIPS_INS_CEQI_B, + MIPS_INS_CEQI_D, + MIPS_INS_CEQI_H, + MIPS_INS_CEQI_W, + MIPS_INS_CEQ_B, + MIPS_INS_CEQ_D, + MIPS_INS_CEQ_H, + MIPS_INS_CEQ_W, + MIPS_INS_CFC1, + MIPS_INS_CFC2, + MIPS_INS_CFCMSA, + MIPS_INS_CINS, + MIPS_INS_CINS32, + MIPS_INS_CLASS_D, + MIPS_INS_CLASS_S, + MIPS_INS_CLEI_S_B, + MIPS_INS_CLEI_S_D, + MIPS_INS_CLEI_S_H, + MIPS_INS_CLEI_S_W, + MIPS_INS_CLEI_U_B, + MIPS_INS_CLEI_U_D, + MIPS_INS_CLEI_U_H, + MIPS_INS_CLEI_U_W, + MIPS_INS_CLE_S_B, + MIPS_INS_CLE_S_D, + MIPS_INS_CLE_S_H, + MIPS_INS_CLE_S_W, + MIPS_INS_CLE_U_B, + MIPS_INS_CLE_U_D, + MIPS_INS_CLE_U_H, + MIPS_INS_CLE_U_W, + MIPS_INS_CLO, + MIPS_INS_CLTI_S_B, + MIPS_INS_CLTI_S_D, + MIPS_INS_CLTI_S_H, + MIPS_INS_CLTI_S_W, + MIPS_INS_CLTI_U_B, + MIPS_INS_CLTI_U_D, + MIPS_INS_CLTI_U_H, + MIPS_INS_CLTI_U_W, + MIPS_INS_CLT_S_B, + MIPS_INS_CLT_S_D, + MIPS_INS_CLT_S_H, + MIPS_INS_CLT_S_W, + MIPS_INS_CLT_U_B, + MIPS_INS_CLT_U_D, + MIPS_INS_CLT_U_H, + MIPS_INS_CLT_U_W, + MIPS_INS_CLZ, + MIPS_INS_CMPGDU_EQ_QB, + MIPS_INS_CMPGDU_LE_QB, + MIPS_INS_CMPGDU_LT_QB, + MIPS_INS_CMPGU_EQ_QB, + MIPS_INS_CMPGU_LE_QB, + MIPS_INS_CMPGU_LT_QB, + MIPS_INS_CMPU_EQ_QB, + MIPS_INS_CMPU_LE_QB, + MIPS_INS_CMPU_LT_QB, + MIPS_INS_CMP_AF_D, + MIPS_INS_CMP_AF_S, + MIPS_INS_CMP_EQ_D, + MIPS_INS_CMP_EQ_PH, + MIPS_INS_CMP_EQ_S, + MIPS_INS_CMP_LE_D, + MIPS_INS_CMP_LE_PH, + MIPS_INS_CMP_LE_S, + MIPS_INS_CMP_LT_D, + MIPS_INS_CMP_LT_PH, + MIPS_INS_CMP_LT_S, + MIPS_INS_CMP_SAF_D, + MIPS_INS_CMP_SAF_S, + MIPS_INS_CMP_SEQ_D, + MIPS_INS_CMP_SEQ_S, + MIPS_INS_CMP_SLE_D, + MIPS_INS_CMP_SLE_S, + MIPS_INS_CMP_SLT_D, + MIPS_INS_CMP_SLT_S, + MIPS_INS_CMP_SUEQ_D, + MIPS_INS_CMP_SUEQ_S, + MIPS_INS_CMP_SULE_D, + MIPS_INS_CMP_SULE_S, + MIPS_INS_CMP_SULT_D, + MIPS_INS_CMP_SULT_S, + MIPS_INS_CMP_SUN_D, + MIPS_INS_CMP_SUN_S, + MIPS_INS_CMP_UEQ_D, + MIPS_INS_CMP_UEQ_S, + MIPS_INS_CMP_ULE_D, + MIPS_INS_CMP_ULE_S, + MIPS_INS_CMP_ULT_D, + MIPS_INS_CMP_ULT_S, + MIPS_INS_CMP_UN_D, + MIPS_INS_CMP_UN_S, + MIPS_INS_COPY_S_B, + MIPS_INS_COPY_S_D, + MIPS_INS_COPY_S_H, + MIPS_INS_COPY_S_W, + MIPS_INS_COPY_U_B, + MIPS_INS_COPY_U_H, + MIPS_INS_COPY_U_W, + MIPS_INS_CRC32B, + MIPS_INS_CRC32CB, + MIPS_INS_CRC32CD, + MIPS_INS_CRC32CH, + MIPS_INS_CRC32CW, + MIPS_INS_CRC32D, + MIPS_INS_CRC32H, + MIPS_INS_CRC32W, + MIPS_INS_CTC1, + MIPS_INS_CTC2, + MIPS_INS_CTCMSA, + MIPS_INS_CVT_D_S, + MIPS_INS_CVT_D_W, + MIPS_INS_CVT_D_L, + MIPS_INS_CVT_L_D, + MIPS_INS_CVT_L_S, + MIPS_INS_CVT_PS_PW, + MIPS_INS_CVT_PS_S, + MIPS_INS_CVT_PW_PS, + MIPS_INS_CVT_S_D, + MIPS_INS_CVT_S_L, + MIPS_INS_CVT_S_PL, + MIPS_INS_CVT_S_PU, + MIPS_INS_CVT_S_W, + MIPS_INS_CVT_W_D, + MIPS_INS_CVT_W_S, + MIPS_INS_C_EQ_D, + MIPS_INS_C_EQ_S, + MIPS_INS_C_F_D, + MIPS_INS_C_F_S, + MIPS_INS_C_LE_D, + MIPS_INS_C_LE_S, + MIPS_INS_C_LT_D, + MIPS_INS_C_LT_S, + MIPS_INS_C_NGE_D, + MIPS_INS_C_NGE_S, + MIPS_INS_C_NGLE_D, + MIPS_INS_C_NGLE_S, + MIPS_INS_C_NGL_D, + MIPS_INS_C_NGL_S, + MIPS_INS_C_NGT_D, + MIPS_INS_C_NGT_S, + MIPS_INS_C_OLE_D, + MIPS_INS_C_OLE_S, + MIPS_INS_C_OLT_D, + MIPS_INS_C_OLT_S, + MIPS_INS_C_SEQ_D, + MIPS_INS_C_SEQ_S, + MIPS_INS_C_SF_D, + MIPS_INS_C_SF_S, + MIPS_INS_C_UEQ_D, + MIPS_INS_C_UEQ_S, + MIPS_INS_C_ULE_D, + MIPS_INS_C_ULE_S, + MIPS_INS_C_ULT_D, + MIPS_INS_C_ULT_S, + MIPS_INS_C_UN_D, + MIPS_INS_C_UN_S, + MIPS_INS_CMP, + MIPS_INS_CMPI, + MIPS_INS_DADD, + MIPS_INS_DADDI, + MIPS_INS_DADDIU, + MIPS_INS_DADDU, + MIPS_INS_DAHI, + MIPS_INS_DALIGN, + MIPS_INS_DATI, + MIPS_INS_DAUI, + MIPS_INS_DBITSWAP, + MIPS_INS_DCLO, + MIPS_INS_DCLZ, + MIPS_INS_DERET, + MIPS_INS_DEXT, + MIPS_INS_DEXTM, + MIPS_INS_DEXTU, + MIPS_INS_DI, + MIPS_INS_DINS, + MIPS_INS_DINSM, + MIPS_INS_DINSU, + MIPS_INS_DIV_S_B, + MIPS_INS_DIV_S_D, + MIPS_INS_DIV_S_H, + MIPS_INS_DIV_S_W, + MIPS_INS_DIV_U_B, + MIPS_INS_DIV_U_D, + MIPS_INS_DIV_U_H, + MIPS_INS_DIV_U_W, + MIPS_INS_DLSA, + MIPS_INS_DMFC0, + MIPS_INS_DMFC1, + MIPS_INS_DMFC2, + MIPS_INS_DMFGC0, + MIPS_INS_DMOD, + MIPS_INS_DMODU, + MIPS_INS_DMT, + MIPS_INS_DMTC0, + MIPS_INS_DMTC1, + MIPS_INS_DMTC2, + MIPS_INS_DMTGC0, + MIPS_INS_DMUH, + MIPS_INS_DMUHU, + MIPS_INS_DMULT, + MIPS_INS_DMULTU, + MIPS_INS_DMULU, + MIPS_INS_DOTP_S_D, + MIPS_INS_DOTP_S_H, + MIPS_INS_DOTP_S_W, + MIPS_INS_DOTP_U_D, + MIPS_INS_DOTP_U_H, + MIPS_INS_DOTP_U_W, + MIPS_INS_DPADD_S_D, + MIPS_INS_DPADD_S_H, + MIPS_INS_DPADD_S_W, + MIPS_INS_DPADD_U_D, + MIPS_INS_DPADD_U_H, + MIPS_INS_DPADD_U_W, + MIPS_INS_DPAQX_SA_W_PH, + MIPS_INS_DPAQX_S_W_PH, + MIPS_INS_DPAQ_SA_L_W, + MIPS_INS_DPAQ_S_W_PH, + MIPS_INS_DPAU_H_QBL, + MIPS_INS_DPAU_H_QBR, + MIPS_INS_DPAX_W_PH, + MIPS_INS_DPA_W_PH, + MIPS_INS_DPOP, + MIPS_INS_DPSQX_SA_W_PH, + MIPS_INS_DPSQX_S_W_PH, + MIPS_INS_DPSQ_SA_L_W, + MIPS_INS_DPSQ_S_W_PH, + MIPS_INS_DPSUB_S_D, + MIPS_INS_DPSUB_S_H, + MIPS_INS_DPSUB_S_W, + MIPS_INS_DPSUB_U_D, + MIPS_INS_DPSUB_U_H, + MIPS_INS_DPSUB_U_W, + MIPS_INS_DPSU_H_QBL, + MIPS_INS_DPSU_H_QBR, + MIPS_INS_DPSX_W_PH, + MIPS_INS_DPS_W_PH, + MIPS_INS_DROTR, + MIPS_INS_DROTR32, + MIPS_INS_DROTRV, + MIPS_INS_DSBH, + MIPS_INS_DSHD, + MIPS_INS_DSLL, + MIPS_INS_DSLL32, + MIPS_INS_DSLLV, + MIPS_INS_DSRA, + MIPS_INS_DSRA32, + MIPS_INS_DSRAV, + MIPS_INS_DSRL, + MIPS_INS_DSRL32, + MIPS_INS_DSRLV, + MIPS_INS_DSUB, + MIPS_INS_DSUBU, + MIPS_INS_DVP, + MIPS_INS_DVPE, + MIPS_INS_EHB, + MIPS_INS_EI, + MIPS_INS_EMT, + MIPS_INS_ERET, + MIPS_INS_ERETNC, + MIPS_INS_EVP, + MIPS_INS_EVPE, + MIPS_INS_EXT, + MIPS_INS_EXTP, + MIPS_INS_EXTPDP, + MIPS_INS_EXTPDPV, + MIPS_INS_EXTPV, + MIPS_INS_EXTRV_RS_W, + MIPS_INS_EXTRV_R_W, + MIPS_INS_EXTRV_S_H, + MIPS_INS_EXTRV_W, + MIPS_INS_EXTR_RS_W, + MIPS_INS_EXTR_R_W, + MIPS_INS_EXTR_S_H, + MIPS_INS_EXTR_W, + MIPS_INS_EXTS, + MIPS_INS_EXTS32, + MIPS_INS_EXTW, + MIPS_INS_ABS_D, + MIPS_INS_ABS_S, + MIPS_INS_FADD_D, + MIPS_INS_ADD_D, + MIPS_INS_ADD_PS, + MIPS_INS_ADD_S, + MIPS_INS_FADD_W, + MIPS_INS_FCAF_D, + MIPS_INS_FCAF_W, + MIPS_INS_FCEQ_D, + MIPS_INS_FCEQ_W, + MIPS_INS_FCLASS_D, + MIPS_INS_FCLASS_W, + MIPS_INS_FCLE_D, + MIPS_INS_FCLE_W, + MIPS_INS_FCLT_D, + MIPS_INS_FCLT_W, + MIPS_INS_FCNE_D, + MIPS_INS_FCNE_W, + MIPS_INS_FCOR_D, + MIPS_INS_FCOR_W, + MIPS_INS_FCUEQ_D, + MIPS_INS_FCUEQ_W, + MIPS_INS_FCULE_D, + MIPS_INS_FCULE_W, + MIPS_INS_FCULT_D, + MIPS_INS_FCULT_W, + MIPS_INS_FCUNE_D, + MIPS_INS_FCUNE_W, + MIPS_INS_FCUN_D, + MIPS_INS_FCUN_W, + MIPS_INS_FDIV_D, + MIPS_INS_DIV_D, + MIPS_INS_DIV_S, + MIPS_INS_FDIV_W, + MIPS_INS_FEXDO_H, + MIPS_INS_FEXDO_W, + MIPS_INS_FEXP2_D, + MIPS_INS_FEXP2_W, + MIPS_INS_FEXUPL_D, + MIPS_INS_FEXUPL_W, + MIPS_INS_FEXUPR_D, + MIPS_INS_FEXUPR_W, + MIPS_INS_FFINT_S_D, + MIPS_INS_FFINT_S_W, + MIPS_INS_FFINT_U_D, + MIPS_INS_FFINT_U_W, + MIPS_INS_FFQL_D, + MIPS_INS_FFQL_W, + MIPS_INS_FFQR_D, + MIPS_INS_FFQR_W, + MIPS_INS_FILL_B, + MIPS_INS_FILL_D, + MIPS_INS_FILL_H, + MIPS_INS_FILL_W, + MIPS_INS_FLOG2_D, + MIPS_INS_FLOG2_W, + MIPS_INS_FLOOR_L_D, + MIPS_INS_FLOOR_L_S, + MIPS_INS_FLOOR_W_D, + MIPS_INS_FLOOR_W_S, + MIPS_INS_FMADD_D, + MIPS_INS_FMADD_W, + MIPS_INS_FMAX_A_D, + MIPS_INS_FMAX_A_W, + MIPS_INS_FMAX_D, + MIPS_INS_FMAX_W, + MIPS_INS_FMIN_A_D, + MIPS_INS_FMIN_A_W, + MIPS_INS_FMIN_D, + MIPS_INS_FMIN_W, + MIPS_INS_MOV_D, + MIPS_INS_MOV_S, + MIPS_INS_FMSUB_D, + MIPS_INS_FMSUB_W, + MIPS_INS_FMUL_D, + MIPS_INS_MUL_D, + MIPS_INS_MUL_PS, + MIPS_INS_MUL_S, + MIPS_INS_FMUL_W, + MIPS_INS_NEG_D, + MIPS_INS_NEG_S, + MIPS_INS_FORK, + MIPS_INS_FRCP_D, + MIPS_INS_FRCP_W, + MIPS_INS_FRINT_D, + MIPS_INS_FRINT_W, + MIPS_INS_FRSQRT_D, + MIPS_INS_FRSQRT_W, + MIPS_INS_FSAF_D, + MIPS_INS_FSAF_W, + MIPS_INS_FSEQ_D, + MIPS_INS_FSEQ_W, + MIPS_INS_FSLE_D, + MIPS_INS_FSLE_W, + MIPS_INS_FSLT_D, + MIPS_INS_FSLT_W, + MIPS_INS_FSNE_D, + MIPS_INS_FSNE_W, + MIPS_INS_FSOR_D, + MIPS_INS_FSOR_W, + MIPS_INS_FSQRT_D, + MIPS_INS_SQRT_D, + MIPS_INS_SQRT_S, + MIPS_INS_FSQRT_W, + MIPS_INS_FSUB_D, + MIPS_INS_SUB_D, + MIPS_INS_SUB_PS, + MIPS_INS_SUB_S, + MIPS_INS_FSUB_W, + MIPS_INS_FSUEQ_D, + MIPS_INS_FSUEQ_W, + MIPS_INS_FSULE_D, + MIPS_INS_FSULE_W, + MIPS_INS_FSULT_D, + MIPS_INS_FSULT_W, + MIPS_INS_FSUNE_D, + MIPS_INS_FSUNE_W, + MIPS_INS_FSUN_D, + MIPS_INS_FSUN_W, + MIPS_INS_FTINT_S_D, + MIPS_INS_FTINT_S_W, + MIPS_INS_FTINT_U_D, + MIPS_INS_FTINT_U_W, + MIPS_INS_FTQ_H, + MIPS_INS_FTQ_W, + MIPS_INS_FTRUNC_S_D, + MIPS_INS_FTRUNC_S_W, + MIPS_INS_FTRUNC_U_D, + MIPS_INS_FTRUNC_U_W, + MIPS_INS_GINVI, + MIPS_INS_GINVT, + MIPS_INS_HADD_S_D, + MIPS_INS_HADD_S_H, + MIPS_INS_HADD_S_W, + MIPS_INS_HADD_U_D, + MIPS_INS_HADD_U_H, + MIPS_INS_HADD_U_W, + MIPS_INS_HSUB_S_D, + MIPS_INS_HSUB_S_H, + MIPS_INS_HSUB_S_W, + MIPS_INS_HSUB_U_D, + MIPS_INS_HSUB_U_H, + MIPS_INS_HSUB_U_W, + MIPS_INS_HYPCALL, + MIPS_INS_ILVEV_B, + MIPS_INS_ILVEV_D, + MIPS_INS_ILVEV_H, + MIPS_INS_ILVEV_W, + MIPS_INS_ILVL_B, + MIPS_INS_ILVL_D, + MIPS_INS_ILVL_H, + MIPS_INS_ILVL_W, + MIPS_INS_ILVOD_B, + MIPS_INS_ILVOD_D, + MIPS_INS_ILVOD_H, + MIPS_INS_ILVOD_W, + MIPS_INS_ILVR_B, + MIPS_INS_ILVR_D, + MIPS_INS_ILVR_H, + MIPS_INS_ILVR_W, + MIPS_INS_INS, + MIPS_INS_INSERT_B, + MIPS_INS_INSERT_D, + MIPS_INS_INSERT_H, + MIPS_INS_INSERT_W, + MIPS_INS_INSV, + MIPS_INS_INSVE_B, + MIPS_INS_INSVE_D, + MIPS_INS_INSVE_H, + MIPS_INS_INSVE_W, + MIPS_INS_J, + MIPS_INS_JALR, + MIPS_INS_JALRC, + MIPS_INS_JALRC_HB, + MIPS_INS_JALRS16, + MIPS_INS_JALRS, + MIPS_INS_JALR_HB, + MIPS_INS_JALS, + MIPS_INS_JALX, + MIPS_INS_JIALC, + MIPS_INS_JIC, + MIPS_INS_JR, + MIPS_INS_JR16, + MIPS_INS_JRADDIUSP, + MIPS_INS_JRC, + MIPS_INS_JRC16, + MIPS_INS_JRCADDIUSP, + MIPS_INS_JR_HB, + MIPS_INS_LAPC_H, + MIPS_INS_LAPC_B, + MIPS_INS_LB, + MIPS_INS_LBE, + MIPS_INS_LBU16, + MIPS_INS_LBU, + MIPS_INS_LBUX, + MIPS_INS_LBX, + MIPS_INS_LBUE, + MIPS_INS_LDC1, + MIPS_INS_LDC2, + MIPS_INS_LDC3, + MIPS_INS_LDI_B, + MIPS_INS_LDI_D, + MIPS_INS_LDI_H, + MIPS_INS_LDI_W, + MIPS_INS_LDL, + MIPS_INS_LDPC, + MIPS_INS_LDR, + MIPS_INS_LDXC1, + MIPS_INS_LD_B, + MIPS_INS_LD_D, + MIPS_INS_LD_H, + MIPS_INS_LD_W, + MIPS_INS_LH, + MIPS_INS_LHE, + MIPS_INS_LHU16, + MIPS_INS_LHU, + MIPS_INS_LHUXS, + MIPS_INS_LHUX, + MIPS_INS_LHX, + MIPS_INS_LHXS, + MIPS_INS_LHUE, + MIPS_INS_LI16, + MIPS_INS_LL, + MIPS_INS_LLD, + MIPS_INS_LLE, + MIPS_INS_LLWP, + MIPS_INS_LSA, + MIPS_INS_LUI, + MIPS_INS_LUXC1, + MIPS_INS_LW, + MIPS_INS_LW16, + MIPS_INS_LWC1, + MIPS_INS_LWC2, + MIPS_INS_LWC3, + MIPS_INS_LWE, + MIPS_INS_LWL, + MIPS_INS_LWLE, + MIPS_INS_LWM16, + MIPS_INS_LWM32, + MIPS_INS_LWPC, + MIPS_INS_LWP, + MIPS_INS_LWR, + MIPS_INS_LWRE, + MIPS_INS_LWUPC, + MIPS_INS_LWU, + MIPS_INS_LWX, + MIPS_INS_LWXC1, + MIPS_INS_LWXS, + MIPS_INS_MADD, + MIPS_INS_MADDF_D, + MIPS_INS_MADDF_S, + MIPS_INS_MADDR_Q_H, + MIPS_INS_MADDR_Q_W, + MIPS_INS_MADDU, + MIPS_INS_MADDV_B, + MIPS_INS_MADDV_D, + MIPS_INS_MADDV_H, + MIPS_INS_MADDV_W, + MIPS_INS_MADD_D, + MIPS_INS_MADD_Q_H, + MIPS_INS_MADD_Q_W, + MIPS_INS_MADD_S, + MIPS_INS_MAQ_SA_W_PHL, + MIPS_INS_MAQ_SA_W_PHR, + MIPS_INS_MAQ_S_W_PHL, + MIPS_INS_MAQ_S_W_PHR, + MIPS_INS_MAXA_D, + MIPS_INS_MAXA_S, + MIPS_INS_MAXI_S_B, + MIPS_INS_MAXI_S_D, + MIPS_INS_MAXI_S_H, + MIPS_INS_MAXI_S_W, + MIPS_INS_MAXI_U_B, + MIPS_INS_MAXI_U_D, + MIPS_INS_MAXI_U_H, + MIPS_INS_MAXI_U_W, + MIPS_INS_MAX_A_B, + MIPS_INS_MAX_A_D, + MIPS_INS_MAX_A_H, + MIPS_INS_MAX_A_W, + MIPS_INS_MAX_D, + MIPS_INS_MAX_S, + MIPS_INS_MAX_S_B, + MIPS_INS_MAX_S_D, + MIPS_INS_MAX_S_H, + MIPS_INS_MAX_S_W, + MIPS_INS_MAX_U_B, + MIPS_INS_MAX_U_D, + MIPS_INS_MAX_U_H, + MIPS_INS_MAX_U_W, + MIPS_INS_MFC0, + MIPS_INS_MFC1, + MIPS_INS_MFC2, + MIPS_INS_MFGC0, + MIPS_INS_MFHC0, + MIPS_INS_MFHC1, + MIPS_INS_MFHC2, + MIPS_INS_MFHGC0, + MIPS_INS_MFHI, + MIPS_INS_MFHI16, + MIPS_INS_MFLO, + MIPS_INS_MFLO16, + MIPS_INS_MFTR, + MIPS_INS_MINA_D, + MIPS_INS_MINA_S, + MIPS_INS_MINI_S_B, + MIPS_INS_MINI_S_D, + MIPS_INS_MINI_S_H, + MIPS_INS_MINI_S_W, + MIPS_INS_MINI_U_B, + MIPS_INS_MINI_U_D, + MIPS_INS_MINI_U_H, + MIPS_INS_MINI_U_W, + MIPS_INS_MIN_A_B, + MIPS_INS_MIN_A_D, + MIPS_INS_MIN_A_H, + MIPS_INS_MIN_A_W, + MIPS_INS_MIN_D, + MIPS_INS_MIN_S, + MIPS_INS_MIN_S_B, + MIPS_INS_MIN_S_D, + MIPS_INS_MIN_S_H, + MIPS_INS_MIN_S_W, + MIPS_INS_MIN_U_B, + MIPS_INS_MIN_U_D, + MIPS_INS_MIN_U_H, + MIPS_INS_MIN_U_W, + MIPS_INS_MOD, + MIPS_INS_MODSUB, + MIPS_INS_MODU, + MIPS_INS_MOD_S_B, + MIPS_INS_MOD_S_D, + MIPS_INS_MOD_S_H, + MIPS_INS_MOD_S_W, + MIPS_INS_MOD_U_B, + MIPS_INS_MOD_U_D, + MIPS_INS_MOD_U_H, + MIPS_INS_MOD_U_W, + MIPS_INS_MOVE, + MIPS_INS_MOVE16, + MIPS_INS_MOVE_BALC, + MIPS_INS_MOVEP, + MIPS_INS_MOVE_V, + MIPS_INS_MOVF_D, + MIPS_INS_MOVF, + MIPS_INS_MOVF_S, + MIPS_INS_MOVN_D, + MIPS_INS_MOVN, + MIPS_INS_MOVN_S, + MIPS_INS_MOVT_D, + MIPS_INS_MOVT, + MIPS_INS_MOVT_S, + MIPS_INS_MOVZ_D, + MIPS_INS_MOVZ, + MIPS_INS_MOVZ_S, + MIPS_INS_MSUB, + MIPS_INS_MSUBF_D, + MIPS_INS_MSUBF_S, + MIPS_INS_MSUBR_Q_H, + MIPS_INS_MSUBR_Q_W, + MIPS_INS_MSUBU, + MIPS_INS_MSUBV_B, + MIPS_INS_MSUBV_D, + MIPS_INS_MSUBV_H, + MIPS_INS_MSUBV_W, + MIPS_INS_MSUB_D, + MIPS_INS_MSUB_Q_H, + MIPS_INS_MSUB_Q_W, + MIPS_INS_MSUB_S, + MIPS_INS_MTC0, + MIPS_INS_MTC1, + MIPS_INS_MTC2, + MIPS_INS_MTGC0, + MIPS_INS_MTHC0, + MIPS_INS_MTHC1, + MIPS_INS_MTHC2, + MIPS_INS_MTHGC0, + MIPS_INS_MTHI, + MIPS_INS_MTHLIP, + MIPS_INS_MTLO, + MIPS_INS_MTM0, + MIPS_INS_MTM1, + MIPS_INS_MTM2, + MIPS_INS_MTP0, + MIPS_INS_MTP1, + MIPS_INS_MTP2, + MIPS_INS_MTTR, + MIPS_INS_MUH, + MIPS_INS_MUHU, + MIPS_INS_MULEQ_S_W_PHL, + MIPS_INS_MULEQ_S_W_PHR, + MIPS_INS_MULEU_S_PH_QBL, + MIPS_INS_MULEU_S_PH_QBR, + MIPS_INS_MULQ_RS_PH, + MIPS_INS_MULQ_RS_W, + MIPS_INS_MULQ_S_PH, + MIPS_INS_MULQ_S_W, + MIPS_INS_MULR_PS, + MIPS_INS_MULR_Q_H, + MIPS_INS_MULR_Q_W, + MIPS_INS_MULSAQ_S_W_PH, + MIPS_INS_MULSA_W_PH, + MIPS_INS_MULT, + MIPS_INS_MULTU, + MIPS_INS_MULU, + MIPS_INS_MULV_B, + MIPS_INS_MULV_D, + MIPS_INS_MULV_H, + MIPS_INS_MULV_W, + MIPS_INS_MUL_PH, + MIPS_INS_MUL_Q_H, + MIPS_INS_MUL_Q_W, + MIPS_INS_MUL_S_PH, + MIPS_INS_NLOC_B, + MIPS_INS_NLOC_D, + MIPS_INS_NLOC_H, + MIPS_INS_NLOC_W, + MIPS_INS_NLZC_B, + MIPS_INS_NLZC_D, + MIPS_INS_NLZC_H, + MIPS_INS_NLZC_W, + MIPS_INS_NMADD_D, + MIPS_INS_NMADD_S, + MIPS_INS_NMSUB_D, + MIPS_INS_NMSUB_S, + MIPS_INS_NOP32, + MIPS_INS_NOP, + MIPS_INS_NORI_B, + MIPS_INS_NOR_V, + MIPS_INS_NOT16, + MIPS_INS_NOT, + MIPS_INS_NEG, + MIPS_INS_OR, + MIPS_INS_OR16, + MIPS_INS_ORI_B, + MIPS_INS_ORI, + MIPS_INS_OR_V, + MIPS_INS_PACKRL_PH, + MIPS_INS_PAUSE, + MIPS_INS_PCKEV_B, + MIPS_INS_PCKEV_D, + MIPS_INS_PCKEV_H, + MIPS_INS_PCKEV_W, + MIPS_INS_PCKOD_B, + MIPS_INS_PCKOD_D, + MIPS_INS_PCKOD_H, + MIPS_INS_PCKOD_W, + MIPS_INS_PCNT_B, + MIPS_INS_PCNT_D, + MIPS_INS_PCNT_H, + MIPS_INS_PCNT_W, + MIPS_INS_PICK_PH, + MIPS_INS_PICK_QB, + MIPS_INS_PLL_PS, + MIPS_INS_PLU_PS, + MIPS_INS_POP, + MIPS_INS_PRECEQU_PH_QBL, + MIPS_INS_PRECEQU_PH_QBLA, + MIPS_INS_PRECEQU_PH_QBR, + MIPS_INS_PRECEQU_PH_QBRA, + MIPS_INS_PRECEQ_W_PHL, + MIPS_INS_PRECEQ_W_PHR, + MIPS_INS_PRECEU_PH_QBL, + MIPS_INS_PRECEU_PH_QBLA, + MIPS_INS_PRECEU_PH_QBR, + MIPS_INS_PRECEU_PH_QBRA, + MIPS_INS_PRECRQU_S_QB_PH, + MIPS_INS_PRECRQ_PH_W, + MIPS_INS_PRECRQ_QB_PH, + MIPS_INS_PRECRQ_RS_PH_W, + MIPS_INS_PRECR_QB_PH, + MIPS_INS_PRECR_SRA_PH_W, + MIPS_INS_PRECR_SRA_R_PH_W, + MIPS_INS_PREF, + MIPS_INS_PREFE, + MIPS_INS_PREFX, + MIPS_INS_PREPEND, + MIPS_INS_PUL_PS, + MIPS_INS_PUU_PS, + MIPS_INS_RADDU_W_QB, + MIPS_INS_RDDSP, + MIPS_INS_RDHWR, + MIPS_INS_RDPGPR, + MIPS_INS_RECIP_D, + MIPS_INS_RECIP_S, + MIPS_INS_REPLV_PH, + MIPS_INS_REPLV_QB, + MIPS_INS_REPL_PH, + MIPS_INS_REPL_QB, + MIPS_INS_RESTORE_JRC, + MIPS_INS_RESTORE, + MIPS_INS_RINT_D, + MIPS_INS_RINT_S, + MIPS_INS_ROTR, + MIPS_INS_ROTRV, + MIPS_INS_ROTX, + MIPS_INS_ROUND_L_D, + MIPS_INS_ROUND_L_S, + MIPS_INS_ROUND_W_D, + MIPS_INS_ROUND_W_S, + MIPS_INS_RSQRT_D, + MIPS_INS_RSQRT_S, + MIPS_INS_SAT_S_B, + MIPS_INS_SAT_S_D, + MIPS_INS_SAT_S_H, + MIPS_INS_SAT_S_W, + MIPS_INS_SAT_U_B, + MIPS_INS_SAT_U_D, + MIPS_INS_SAT_U_H, + MIPS_INS_SAT_U_W, + MIPS_INS_SAVE, + MIPS_INS_SB, + MIPS_INS_SB16, + MIPS_INS_SBE, + MIPS_INS_SBX, + MIPS_INS_SC, + MIPS_INS_SCD, + MIPS_INS_SCE, + MIPS_INS_SCWP, + MIPS_INS_SDBBP, + MIPS_INS_SDBBP16, + MIPS_INS_SDC1, + MIPS_INS_SDC2, + MIPS_INS_SDC3, + MIPS_INS_SDL, + MIPS_INS_SDR, + MIPS_INS_SDXC1, + MIPS_INS_SEB, + MIPS_INS_SEH, + MIPS_INS_SELEQZ, + MIPS_INS_SELEQZ_D, + MIPS_INS_SELEQZ_S, + MIPS_INS_SELNEZ, + MIPS_INS_SELNEZ_D, + MIPS_INS_SELNEZ_S, + MIPS_INS_SEL_D, + MIPS_INS_SEL_S, + MIPS_INS_SEQI, + MIPS_INS_SH, + MIPS_INS_SH16, + MIPS_INS_SHE, + MIPS_INS_SHF_B, + MIPS_INS_SHF_H, + MIPS_INS_SHF_W, + MIPS_INS_SHILO, + MIPS_INS_SHILOV, + MIPS_INS_SHLLV_PH, + MIPS_INS_SHLLV_QB, + MIPS_INS_SHLLV_S_PH, + MIPS_INS_SHLLV_S_W, + MIPS_INS_SHLL_PH, + MIPS_INS_SHLL_QB, + MIPS_INS_SHLL_S_PH, + MIPS_INS_SHLL_S_W, + MIPS_INS_SHRAV_PH, + MIPS_INS_SHRAV_QB, + MIPS_INS_SHRAV_R_PH, + MIPS_INS_SHRAV_R_QB, + MIPS_INS_SHRAV_R_W, + MIPS_INS_SHRA_PH, + MIPS_INS_SHRA_QB, + MIPS_INS_SHRA_R_PH, + MIPS_INS_SHRA_R_QB, + MIPS_INS_SHRA_R_W, + MIPS_INS_SHRLV_PH, + MIPS_INS_SHRLV_QB, + MIPS_INS_SHRL_PH, + MIPS_INS_SHRL_QB, + MIPS_INS_SHXS, + MIPS_INS_SHX, + MIPS_INS_SIGRIE, + MIPS_INS_SLDI_B, + MIPS_INS_SLDI_D, + MIPS_INS_SLDI_H, + MIPS_INS_SLDI_W, + MIPS_INS_SLD_B, + MIPS_INS_SLD_D, + MIPS_INS_SLD_H, + MIPS_INS_SLD_W, + MIPS_INS_SLL, + MIPS_INS_SLL16, + MIPS_INS_SLLI_B, + MIPS_INS_SLLI_D, + MIPS_INS_SLLI_H, + MIPS_INS_SLLI_W, + MIPS_INS_SLLV, + MIPS_INS_SLL_B, + MIPS_INS_SLL_D, + MIPS_INS_SLL_H, + MIPS_INS_SLL_W, + MIPS_INS_SLTIU, + MIPS_INS_SLTI, + MIPS_INS_SNEI, + MIPS_INS_SOV, + MIPS_INS_SPLATI_B, + MIPS_INS_SPLATI_D, + MIPS_INS_SPLATI_H, + MIPS_INS_SPLATI_W, + MIPS_INS_SPLAT_B, + MIPS_INS_SPLAT_D, + MIPS_INS_SPLAT_H, + MIPS_INS_SPLAT_W, + MIPS_INS_SRA, + MIPS_INS_SRAI_B, + MIPS_INS_SRAI_D, + MIPS_INS_SRAI_H, + MIPS_INS_SRAI_W, + MIPS_INS_SRARI_B, + MIPS_INS_SRARI_D, + MIPS_INS_SRARI_H, + MIPS_INS_SRARI_W, + MIPS_INS_SRAR_B, + MIPS_INS_SRAR_D, + MIPS_INS_SRAR_H, + MIPS_INS_SRAR_W, + MIPS_INS_SRAV, + MIPS_INS_SRA_B, + MIPS_INS_SRA_D, + MIPS_INS_SRA_H, + MIPS_INS_SRA_W, + MIPS_INS_SRL, + MIPS_INS_SRL16, + MIPS_INS_SRLI_B, + MIPS_INS_SRLI_D, + MIPS_INS_SRLI_H, + MIPS_INS_SRLI_W, + MIPS_INS_SRLRI_B, + MIPS_INS_SRLRI_D, + MIPS_INS_SRLRI_H, + MIPS_INS_SRLRI_W, + MIPS_INS_SRLR_B, + MIPS_INS_SRLR_D, + MIPS_INS_SRLR_H, + MIPS_INS_SRLR_W, + MIPS_INS_SRLV, + MIPS_INS_SRL_B, + MIPS_INS_SRL_D, + MIPS_INS_SRL_H, + MIPS_INS_SRL_W, + MIPS_INS_SSNOP, + MIPS_INS_ST_B, + MIPS_INS_ST_D, + MIPS_INS_ST_H, + MIPS_INS_ST_W, + MIPS_INS_SUB, + MIPS_INS_SUBQH_PH, + MIPS_INS_SUBQH_R_PH, + MIPS_INS_SUBQH_R_W, + MIPS_INS_SUBQH_W, + MIPS_INS_SUBQ_PH, + MIPS_INS_SUBQ_S_PH, + MIPS_INS_SUBQ_S_W, + MIPS_INS_SUBSUS_U_B, + MIPS_INS_SUBSUS_U_D, + MIPS_INS_SUBSUS_U_H, + MIPS_INS_SUBSUS_U_W, + MIPS_INS_SUBSUU_S_B, + MIPS_INS_SUBSUU_S_D, + MIPS_INS_SUBSUU_S_H, + MIPS_INS_SUBSUU_S_W, + MIPS_INS_SUBS_S_B, + MIPS_INS_SUBS_S_D, + MIPS_INS_SUBS_S_H, + MIPS_INS_SUBS_S_W, + MIPS_INS_SUBS_U_B, + MIPS_INS_SUBS_U_D, + MIPS_INS_SUBS_U_H, + MIPS_INS_SUBS_U_W, + MIPS_INS_SUBU16, + MIPS_INS_SUBUH_QB, + MIPS_INS_SUBUH_R_QB, + MIPS_INS_SUBU_PH, + MIPS_INS_SUBU_QB, + MIPS_INS_SUBU_S_PH, + MIPS_INS_SUBU_S_QB, + MIPS_INS_SUBVI_B, + MIPS_INS_SUBVI_D, + MIPS_INS_SUBVI_H, + MIPS_INS_SUBVI_W, + MIPS_INS_SUBV_B, + MIPS_INS_SUBV_D, + MIPS_INS_SUBV_H, + MIPS_INS_SUBV_W, + MIPS_INS_SUXC1, + MIPS_INS_SW, + MIPS_INS_SW16, + MIPS_INS_SWC1, + MIPS_INS_SWC2, + MIPS_INS_SWC3, + MIPS_INS_SWE, + MIPS_INS_SWL, + MIPS_INS_SWLE, + MIPS_INS_SWM16, + MIPS_INS_SWM32, + MIPS_INS_SWPC, + MIPS_INS_SWP, + MIPS_INS_SWR, + MIPS_INS_SWRE, + MIPS_INS_SWSP, + MIPS_INS_SWXC1, + MIPS_INS_SWXS, + MIPS_INS_SWX, + MIPS_INS_SYNC, + MIPS_INS_SYNCI, + MIPS_INS_SYSCALL, + MIPS_INS_TEQ, + MIPS_INS_TEQI, + MIPS_INS_TGE, + MIPS_INS_TGEI, + MIPS_INS_TGEIU, + MIPS_INS_TGEU, + MIPS_INS_TLBGINV, + MIPS_INS_TLBGINVF, + MIPS_INS_TLBGP, + MIPS_INS_TLBGR, + MIPS_INS_TLBGWI, + MIPS_INS_TLBGWR, + MIPS_INS_TLBINV, + MIPS_INS_TLBINVF, + MIPS_INS_TLBP, + MIPS_INS_TLBR, + MIPS_INS_TLBWI, + MIPS_INS_TLBWR, + MIPS_INS_TLT, + MIPS_INS_TLTI, + MIPS_INS_TLTIU, + MIPS_INS_TLTU, + MIPS_INS_TNE, + MIPS_INS_TNEI, + MIPS_INS_TRUNC_L_D, + MIPS_INS_TRUNC_L_S, + MIPS_INS_UALH, + MIPS_INS_UALWM, + MIPS_INS_UALW, + MIPS_INS_UASH, + MIPS_INS_UASWM, + MIPS_INS_UASW, + MIPS_INS_V3MULU, + MIPS_INS_VMM0, + MIPS_INS_VMULU, + MIPS_INS_VSHF_B, + MIPS_INS_VSHF_D, + MIPS_INS_VSHF_H, + MIPS_INS_VSHF_W, + MIPS_INS_WAIT, + MIPS_INS_WRDSP, + MIPS_INS_WRPGPR, + MIPS_INS_WSBH, + MIPS_INS_XOR, + MIPS_INS_XOR16, + MIPS_INS_XORI_B, + MIPS_INS_XORI, + MIPS_INS_XOR_V, + MIPS_INS_YIELD, diff --git a/arch/Mips/MipsGenCSMappingInsn.inc b/arch/Mips/MipsGenCSMappingInsn.inc new file mode 100644 index 0000000000..5e399ea742 --- /dev/null +++ b/arch/Mips/MipsGenCSMappingInsn.inc @@ -0,0 +1,24465 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +{ + /* PHINODE */ + Mips_PHI /* 0 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INLINEASM /* 1 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INLINEASM_BR /* 2 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_CFI_INSTRUCTION /* 3 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_EH_LABEL /* 4 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_GC_LABEL /* 5 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ANNOTATION_LABEL /* 6 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_KILL /* 7 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_EXTRACT_SUBREG /* 8 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_SUBREG /* 9 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_IMPLICIT_DEF /* 10 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SUBREG_TO_REG /* 11 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_COPY_TO_REGCLASS /* 12 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_VALUE */ + Mips_DBG_VALUE /* 13 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_VALUE_LIST */ + Mips_DBG_VALUE_LIST /* 14 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_INSTR_REF */ + Mips_DBG_INSTR_REF /* 15 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_PHI */ + Mips_DBG_PHI /* 16 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_LABEL */ + Mips_DBG_LABEL /* 17 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_REG_SEQUENCE /* 18 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_COPY /* 19 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* BUNDLE */ + Mips_BUNDLE /* 20 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* LIFETIME_START */ + Mips_LIFETIME_START /* 21 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* LIFETIME_END */ + Mips_LIFETIME_END /* 22 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* PSEUDO_PROBE */ + Mips_PSEUDO_PROBE /* 23 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ARITH_FENCE /* 24 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_STACKMAP /* 25 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # FEntry call */ + Mips_FENTRY_CALL /* 26 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PATCHPOINT /* 27 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LOAD_STACK_GUARD /* 28 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PREALLOCATED_SETUP /* 29 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PREALLOCATED_ARG /* 30 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_STATEPOINT /* 31 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LOCAL_ESCAPE /* 32 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_FAULTING_OP /* 33 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PATCHABLE_OP /* 34 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Function Enter. */ + Mips_PATCHABLE_FUNCTION_ENTER /* 35 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Function Patchable RET. */ + Mips_PATCHABLE_RET /* 36 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Function Exit. */ + Mips_PATCHABLE_FUNCTION_EXIT /* 37 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Tail Call Exit. */ + Mips_PATCHABLE_TAIL_CALL /* 38 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Custom Event Log. */ + Mips_PATCHABLE_EVENT_CALL /* 39 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Typed Event Log. */ + Mips_PATCHABLE_TYPED_EVENT_CALL /* 40 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ICALL_BRANCH_FUNNEL /* 41 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_MEMBARRIER /* 42 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_JUMP_TABLE_DEBUG_INFO /* 43 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ASSERT_SEXT /* 44 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ASSERT_ZEXT /* 45 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ASSERT_ALIGN /* 46 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ADD /* 47 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SUB /* 48 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_MUL /* 49 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SDIV /* 50 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UDIV /* 51 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SREM /* 52 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UREM /* 53 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SDIVREM /* 54 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UDIVREM /* 55 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_AND /* 56 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_OR /* 57 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_XOR /* 58 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_IMPLICIT_DEF /* 59 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_PHI /* 60 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FRAME_INDEX /* 61 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_GLOBAL_VALUE /* 62 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_CONSTANT_POOL /* 63 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_EXTRACT /* 64 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UNMERGE_VALUES /* 65 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INSERT /* 66 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_MERGE_VALUES /* 67 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BUILD_VECTOR /* 68 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BUILD_VECTOR_TRUNC /* 69 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_CONCAT_VECTORS /* 70 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_PTRTOINT /* 71 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTTOPTR /* 72 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BITCAST /* 73 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FREEZE /* 74 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_CONSTANT_FOLD_BARRIER /* 75 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTRINSIC_FPTRUNC_ROUND /* 76 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTRINSIC_TRUNC /* 77 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTRINSIC_ROUND /* 78 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTRINSIC_LRINT /* 79 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTRINSIC_ROUNDEVEN /* 80 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_READCYCLECOUNTER /* 81 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_LOAD /* 82 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SEXTLOAD /* 83 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ZEXTLOAD /* 84 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INDEXED_LOAD /* 85 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INDEXED_SEXTLOAD /* 86 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INDEXED_ZEXTLOAD /* 87 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STORE /* 88 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INDEXED_STORE /* 89 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMIC_CMPXCHG_WITH_SUCCESS /* 90 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMIC_CMPXCHG /* 91 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_XCHG /* 92 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_ADD /* 93 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_SUB /* 94 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_AND /* 95 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_NAND /* 96 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_OR /* 97 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_XOR /* 98 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_MAX /* 99 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_MIN /* 100 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_UMAX /* 101 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_UMIN /* 102 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_FADD /* 103 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_FSUB /* 104 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_FMAX /* 105 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_FMIN /* 106 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_UINC_WRAP /* 107 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ATOMICRMW_UDEC_WRAP /* 108 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FENCE /* 109 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_PREFETCH /* 110 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BRCOND /* 111 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BRINDIRECT /* 112 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INVOKE_REGION_START /* 113 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTRINSIC /* 114 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTRINSIC_W_SIDE_EFFECTS /* 115 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTRINSIC_CONVERGENT /* 116 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS /* 117 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ANYEXT /* 118 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_TRUNC /* 119 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_CONSTANT /* 120 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FCONSTANT /* 121 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VASTART /* 122 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VAARG /* 123 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SEXT /* 124 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SEXT_INREG /* 125 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ZEXT /* 126 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SHL /* 127 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_LSHR /* 128 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ASHR /* 129 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FSHL /* 130 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FSHR /* 131 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ROTR /* 132 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ROTL /* 133 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ICMP /* 134 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FCMP /* 135 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SELECT /* 136 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UADDO /* 137 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UADDE /* 138 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_USUBO /* 139 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_USUBE /* 140 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SADDO /* 141 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SADDE /* 142 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SSUBO /* 143 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SSUBE /* 144 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UMULO /* 145 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SMULO /* 146 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UMULH /* 147 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SMULH /* 148 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UADDSAT /* 149 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SADDSAT /* 150 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_USUBSAT /* 151 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SSUBSAT /* 152 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_USHLSAT /* 153 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SSHLSAT /* 154 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SMULFIX /* 155 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UMULFIX /* 156 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SMULFIXSAT /* 157 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UMULFIXSAT /* 158 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SDIVFIX /* 159 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UDIVFIX /* 160 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SDIVFIXSAT /* 161 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UDIVFIXSAT /* 162 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FADD /* 163 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FSUB /* 164 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FMUL /* 165 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FMA /* 166 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FMAD /* 167 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FDIV /* 168 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FREM /* 169 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FPOW /* 170 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FPOWI /* 171 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FEXP /* 172 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FEXP2 /* 173 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FEXP10 /* 174 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FLOG /* 175 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FLOG2 /* 176 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FLOG10 /* 177 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FLDEXP /* 178 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FFREXP /* 179 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FNEG /* 180 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FPEXT /* 181 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FPTRUNC /* 182 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FPTOSI /* 183 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FPTOUI /* 184 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SITOFP /* 185 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UITOFP /* 186 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FABS /* 187 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FCOPYSIGN /* 188 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_IS_FPCLASS /* 189 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FCANONICALIZE /* 190 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FMINNUM /* 191 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FMAXNUM /* 192 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FMINNUM_IEEE /* 193 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FMAXNUM_IEEE /* 194 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FMINIMUM /* 195 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FMAXIMUM /* 196 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_GET_FPENV /* 197 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SET_FPENV /* 198 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_RESET_FPENV /* 199 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_GET_FPMODE /* 200 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SET_FPMODE /* 201 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_RESET_FPMODE /* 202 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_PTR_ADD /* 203 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_PTRMASK /* 204 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SMIN /* 205 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SMAX /* 206 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UMIN /* 207 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UMAX /* 208 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ABS /* 209 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_LROUND /* 210 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_LLROUND /* 211 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BR /* 212 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BRJT /* 213 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_INSERT_VECTOR_ELT /* 214 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_EXTRACT_VECTOR_ELT /* 215 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SHUFFLE_VECTOR /* 216 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_CTTZ /* 217 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_CTTZ_ZERO_UNDEF /* 218 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_CTLZ /* 219 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_CTLZ_ZERO_UNDEF /* 220 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_CTPOP /* 221 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BSWAP /* 222 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BITREVERSE /* 223 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FCEIL /* 224 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FCOS /* 225 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FSIN /* 226 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FSQRT /* 227 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FFLOOR /* 228 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FRINT /* 229 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_FNEARBYINT /* 230 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_ADDRSPACE_CAST /* 231 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BLOCK_ADDR /* 232 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_JUMP_TABLE /* 233 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_DYN_STACKALLOC /* 234 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STACKSAVE /* 235 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STACKRESTORE /* 236 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STRICT_FADD /* 237 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STRICT_FSUB /* 238 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STRICT_FMUL /* 239 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STRICT_FDIV /* 240 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STRICT_FREM /* 241 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STRICT_FMA /* 242 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STRICT_FSQRT /* 243 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_STRICT_FLDEXP /* 244 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_READ_REGISTER /* 245 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_WRITE_REGISTER /* 246 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_MEMCPY /* 247 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_MEMCPY_INLINE /* 248 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_MEMMOVE /* 249 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_MEMSET /* 250 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_BZERO /* 251 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_SEQ_FADD /* 252 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_SEQ_FMUL /* 253 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_FADD /* 254 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_FMUL /* 255 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_FMAX /* 256 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_FMIN /* 257 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_FMAXIMUM /* 258 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_FMINIMUM /* 259 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_ADD /* 260 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_MUL /* 261 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_AND /* 262 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_OR /* 263 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_XOR /* 264 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_SMAX /* 265 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_SMIN /* 266 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_UMAX /* 267 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_VECREDUCE_UMIN /* 268 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_SBFX /* 269 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_G_UBFX /* 270 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* abs $rd, $rs */ + Mips_ABSMacro /* 271 */, MIPS_INS_ABS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_ADJCALLSTACKDOWN /* 272 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ADJCALLSTACKDOWN_NM /* 273 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ADJCALLSTACKUP /* 274 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ADJCALLSTACKUP_NM /* 275 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* align $rd, $rs, $rt, $bp */ + Mips_ALIGN_NM /* 276 */, MIPS_INS_ALIGN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_AND_V_D_PSEUDO /* 277 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_AND_V_H_PSEUDO /* 278 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_AND_V_W_PSEUDO /* 279 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_CMP_SWAP_I16 /* 280 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_CMP_SWAP_I16_POSTRA /* 281 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_CMP_SWAP_I32 /* 282 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_CMP_SWAP_I32_POSTRA /* 283 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_CMP_SWAP_I64 /* 284 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_CMP_SWAP_I64_POSTRA /* 285 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_CMP_SWAP_I8 /* 286 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_CMP_SWAP_I8_POSTRA /* 287 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_ADD_I16 /* 288 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_ADD_I16_POSTRA /* 289 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_ADD_I32 /* 290 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_ADD_I32_POSTRA /* 291 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_ADD_I64 /* 292 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_ADD_I64_POSTRA /* 293 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_ADD_I8 /* 294 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_ADD_I8_POSTRA /* 295 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_AND_I16 /* 296 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_AND_I16_POSTRA /* 297 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_AND_I32 /* 298 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_AND_I32_POSTRA /* 299 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_AND_I64 /* 300 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_AND_I64_POSTRA /* 301 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_AND_I8 /* 302 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_AND_I8_POSTRA /* 303 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MAX_I16 /* 304 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MAX_I16_POSTRA /* 305 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MAX_I32 /* 306 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MAX_I32_POSTRA /* 307 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MAX_I64 /* 308 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MAX_I64_POSTRA /* 309 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MAX_I8 /* 310 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MAX_I8_POSTRA /* 311 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MIN_I16 /* 312 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MIN_I16_POSTRA /* 313 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MIN_I32 /* 314 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MIN_I32_POSTRA /* 315 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MIN_I64 /* 316 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MIN_I64_POSTRA /* 317 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MIN_I8 /* 318 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_MIN_I8_POSTRA /* 319 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_NAND_I16 /* 320 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_NAND_I16_POSTRA /* 321 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_NAND_I32 /* 322 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_NAND_I32_POSTRA /* 323 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_NAND_I64 /* 324 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_NAND_I64_POSTRA /* 325 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_NAND_I8 /* 326 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_NAND_I8_POSTRA /* 327 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_OR_I16 /* 328 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_OR_I16_POSTRA /* 329 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_OR_I32 /* 330 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_OR_I32_POSTRA /* 331 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_OR_I64 /* 332 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_OR_I64_POSTRA /* 333 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_OR_I8 /* 334 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_OR_I8_POSTRA /* 335 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_SUB_I16 /* 336 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_SUB_I16_POSTRA /* 337 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_SUB_I32 /* 338 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_SUB_I32_POSTRA /* 339 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_SUB_I64 /* 340 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_SUB_I64_POSTRA /* 341 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_SUB_I8 /* 342 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_SUB_I8_POSTRA /* 343 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMAX_I16 /* 344 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMAX_I16_POSTRA /* 345 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMAX_I32 /* 346 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMAX_I32_POSTRA /* 347 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMAX_I64 /* 348 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMAX_I64_POSTRA /* 349 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMAX_I8 /* 350 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMAX_I8_POSTRA /* 351 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMIN_I16 /* 352 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMIN_I16_POSTRA /* 353 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMIN_I32 /* 354 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMIN_I32_POSTRA /* 355 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMIN_I64 /* 356 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMIN_I64_POSTRA /* 357 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMIN_I8 /* 358 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_UMIN_I8_POSTRA /* 359 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_XOR_I16 /* 360 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_XOR_I16_POSTRA /* 361 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_XOR_I32 /* 362 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_XOR_I32_POSTRA /* 363 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_XOR_I64 /* 364 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_XOR_I64_POSTRA /* 365 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_XOR_I8 /* 366 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_LOAD_XOR_I8_POSTRA /* 367 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_SWAP_I16 /* 368 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_SWAP_I16_POSTRA /* 369 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_SWAP_I32 /* 370 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_SWAP_I32_POSTRA /* 371 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_SWAP_I64 /* 372 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_SWAP_I64_POSTRA /* 373 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_SWAP_I8 /* 374 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ATOMIC_SWAP_I8_POSTRA /* 375 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_B /* 376 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_BAL_BR /* 377 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_BAL_BR_MM /* 378 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* beql $rs, $imm, $offset */ + Mips_BEQLImmMacro /* 379 */, MIPS_INS_BEQL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bge $rs, $rt, $offset */ + Mips_BGE /* 380 */, MIPS_INS_BGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bge $rs, $imm, $offset */ + Mips_BGEImmMacro /* 381 */, MIPS_INS_BGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgel $rs, $rt, $offset */ + Mips_BGEL /* 382 */, MIPS_INS_BGEL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgel $rs, $imm, $offset */ + Mips_BGELImmMacro /* 383 */, MIPS_INS_BGEL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgeu $rs, $rt, $offset */ + Mips_BGEU /* 384 */, MIPS_INS_BGEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgeu $rs, $imm, $offset */ + Mips_BGEUImmMacro /* 385 */, MIPS_INS_BGEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgeul $rs, $rt, $offset */ + Mips_BGEUL /* 386 */, MIPS_INS_BGEUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgeul $rs, $imm, $offset */ + Mips_BGEULImmMacro /* 387 */, MIPS_INS_BGEUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgt $rs, $rt, $offset */ + Mips_BGT /* 388 */, MIPS_INS_BGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgt $rs, $imm, $offset */ + Mips_BGTImmMacro /* 389 */, MIPS_INS_BGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgtl $rs, $rt, $offset */ + Mips_BGTL /* 390 */, MIPS_INS_BGTL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgtl $rs, $imm, $offset */ + Mips_BGTLImmMacro /* 391 */, MIPS_INS_BGTL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgtu $rs, $rt, $offset */ + Mips_BGTU /* 392 */, MIPS_INS_BGTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgtu $rs, $imm, $offset */ + Mips_BGTUImmMacro /* 393 */, MIPS_INS_BGTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgtul $rs, $rt, $offset */ + Mips_BGTUL /* 394 */, MIPS_INS_BGTUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgtul $rs, $imm, $offset */ + Mips_BGTULImmMacro /* 395 */, MIPS_INS_BGTUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ble $rs, $rt, $offset */ + Mips_BLE /* 396 */, MIPS_INS_BLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ble $rs, $imm, $offset */ + Mips_BLEImmMacro /* 397 */, MIPS_INS_BLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* blel $rs, $rt, $offset */ + Mips_BLEL /* 398 */, MIPS_INS_BLEL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* blel $rs, $imm, $offset */ + Mips_BLELImmMacro /* 399 */, MIPS_INS_BLEL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bleu $rs, $rt, $offset */ + Mips_BLEU /* 400 */, MIPS_INS_BLEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bleu $rs, $imm, $offset */ + Mips_BLEUImmMacro /* 401 */, MIPS_INS_BLEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bleul $rs, $rt, $offset */ + Mips_BLEUL /* 402 */, MIPS_INS_BLEUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bleul $rs, $imm, $offset */ + Mips_BLEULImmMacro /* 403 */, MIPS_INS_BLEUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* blt $rs, $rt, $offset */ + Mips_BLT /* 404 */, MIPS_INS_BLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* blt $rs, $imm, $offset */ + Mips_BLTImmMacro /* 405 */, MIPS_INS_BLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltl $rs, $rt, $offset */ + Mips_BLTL /* 406 */, MIPS_INS_BLTL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltl $rs, $imm, $offset */ + Mips_BLTLImmMacro /* 407 */, MIPS_INS_BLTL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltu $rs, $rt, $offset */ + Mips_BLTU /* 408 */, MIPS_INS_BLTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltu $rs, $imm, $offset */ + Mips_BLTUImmMacro /* 409 */, MIPS_INS_BLTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltul $rs, $rt, $offset */ + Mips_BLTUL /* 410 */, MIPS_INS_BLTUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltul $rs, $imm, $offset */ + Mips_BLTULImmMacro /* 411 */, MIPS_INS_BLTUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bnel $rs, $imm, $offset */ + Mips_BNELImmMacro /* 412 */, MIPS_INS_BNEL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_BPOSGE32_PSEUDO /* 413 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_BSEL_D_PSEUDO /* 414 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_BSEL_FD_PSEUDO /* 415 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_BSEL_FW_PSEUDO /* 416 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_BSEL_H_PSEUDO /* 417 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_BSEL_W_PSEUDO /* 418 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_B_MM /* 419 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* b $offset */ + Mips_B_MMR6_Pseudo /* 420 */, MIPS_INS_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* b $offset */ + Mips_B_MM_Pseudo /* 421 */, MIPS_INS_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* beq $rt, $imm64, $offset */ + Mips_BeqImm /* 422 */, MIPS_INS_BEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bne $rt, $imm64, $offset */ + Mips_BneImm /* 423 */, MIPS_INS_BNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp $rx, $ry + bteqz $imm */ + Mips_BteqzT8CmpX16 /* 424 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cmpi $rx, $imm + bteqz $targ */ + Mips_BteqzT8CmpiX16 /* 425 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slt $rx, $ry + bteqz $imm */ + Mips_BteqzT8SltX16 /* 426 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slti $rx, $imm + bteqz $targ */ + Mips_BteqzT8SltiX16 /* 427 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltiu $rx, $imm + bteqz $targ */ + Mips_BteqzT8SltiuX16 /* 428 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltu $rx, $ry + bteqz $imm */ + Mips_BteqzT8SltuX16 /* 429 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cmp $rx, $ry + btnez $imm */ + Mips_BtnezT8CmpX16 /* 430 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cmpi $rx, $imm + btnez $targ */ + Mips_BtnezT8CmpiX16 /* 431 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slt $rx, $ry + btnez $imm */ + Mips_BtnezT8SltX16 /* 432 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slti $rx, $imm + btnez $targ */ + Mips_BtnezT8SltiX16 /* 433 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltiu $rx, $imm + btnez $targ */ + Mips_BtnezT8SltiuX16 /* 434 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltu $rx, $ry + btnez $imm */ + Mips_BtnezT8SltuX16 /* 435 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_BuildPairF64 /* 436 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_BuildPairF64_64 /* 437 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cftc1 $rt, $ft */ + Mips_CFTC1 /* 438 */, MIPS_INS_CFTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* foo */ + Mips_CONSTPOOL_ENTRY /* 439 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_COPY_FD_PSEUDO /* 440 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_COPY_FW_PSEUDO /* 441 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cttc1 $rt, $ft */ + Mips_CTTC1 /* 442 */, MIPS_INS_CTTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* .word $imm */ + Mips_Constant32 /* 443 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* dmul $rs, $rt, $imm */ + Mips_DMULImmMacro /* 444 */, MIPS_INS_DMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmul $rs, $rt, $rd */ + Mips_DMULMacro /* 445 */, MIPS_INS_DMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmulo $rs, $rt, $rd */ + Mips_DMULOMacro /* 446 */, MIPS_INS_DMULO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmulou $rs, $rt, $rd */ + Mips_DMULOUMacro /* 447 */, MIPS_INS_DMULOU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* drol $rs, $rt, $rd */ + Mips_DROL /* 448 */, MIPS_INS_DROL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* drol $rs, $rt, $imm */ + Mips_DROLImm /* 449 */, MIPS_INS_DROL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dror $rs, $rt, $rd */ + Mips_DROR /* 450 */, MIPS_INS_DROR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dror $rs, $rt, $imm */ + Mips_DRORImm /* 451 */, MIPS_INS_DROR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ddiv $rd, $rs, $imm */ + Mips_DSDivIMacro /* 452 */, MIPS_INS_DDIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ddiv $rd, $rs, $rt */ + Mips_DSDivMacro /* 453 */, MIPS_INS_DDIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* drem $rd, $rs, $imm */ + Mips_DSRemIMacro /* 454 */, MIPS_INS_DREM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* drem $rd, $rs, $rt */ + Mips_DSRemMacro /* 455 */, MIPS_INS_DREM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ddivu $rd, $rs, $imm */ + Mips_DUDivIMacro /* 456 */, MIPS_INS_DDIVU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ddivu $rd, $rs, $rt */ + Mips_DUDivMacro /* 457 */, MIPS_INS_DDIVU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dremu $rd, $rs, $imm */ + Mips_DURemIMacro /* 458 */, MIPS_INS_DREMU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dremu $rd, $rs, $rt */ + Mips_DURemMacro /* 459 */, MIPS_INS_DREMU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_ERet /* 460 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ExtractElementF64 /* 461 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ExtractElementF64_64 /* 462 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_FABS_D /* 463 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_FABS_W /* 464 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_FEXP2_D_1_PSEUDO /* 465 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_FEXP2_W_1_PSEUDO /* 466 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_FILL_FD_PSEUDO /* 467 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_FILL_FW_PSEUDO /* 468 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* li $rh, $immHi + addiu $rl, $$pc, $immLo + */ + Mips_GotPrologue16 /* 469 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_B_VIDX64_PSEUDO /* 470 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_B_VIDX_PSEUDO /* 471 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_D_VIDX64_PSEUDO /* 472 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_D_VIDX_PSEUDO /* 473 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_FD_PSEUDO /* 474 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_FD_VIDX64_PSEUDO /* 475 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_FD_VIDX_PSEUDO /* 476 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_FW_PSEUDO /* 477 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_FW_VIDX64_PSEUDO /* 478 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_FW_VIDX_PSEUDO /* 479 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_H_VIDX64_PSEUDO /* 480 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_H_VIDX_PSEUDO /* 481 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_W_VIDX64_PSEUDO /* 482 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_INSERT_W_VIDX_PSEUDO /* 483 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_JALR64Pseudo /* 484 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_JALRCPseudo /* 485 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_JALRHB64Pseudo /* 486 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_JALRHBPseudo /* 487 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_JALRPseudo /* 488 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_JAL_MMR6 /* 489 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* jal $rs */ + Mips_JalOneReg /* 490 */, MIPS_INS_JAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jal $rd, $rs */ + Mips_JalTwoReg /* 491 */, MIPS_INS_JAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ld $rt, $addr */ + Mips_LDMacro /* 492 */, MIPS_INS_LD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_LDR_D /* 493 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LDR_W /* 494 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LD_F16 /* 495 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $rt, $addr */ + Mips_LOAD_ACC128 /* 496 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $rt, $addr */ + Mips_LOAD_ACC64 /* 497 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $rt, $addr */ + Mips_LOAD_ACC64DSP /* 498 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* load_ccond_dsp $rt, $addr */ + Mips_LOAD_CCOND_DSP /* 499 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LONG_BRANCH_ADDiu /* 500 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LONG_BRANCH_ADDiu2Op /* 501 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LONG_BRANCH_DADDiu /* 502 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LONG_BRANCH_DADDiu2Op /* 503 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LONG_BRANCH_LUi /* 504 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LONG_BRANCH_LUi2Op /* 505 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_LONG_BRANCH_LUi2Op_64 /* 506 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lwm $rt, $addr */ + Mips_LWM_MM /* 507 */, MIPS_INS_LWM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* la $rt, $imm32 */ + Mips_LoadAddrImm32 /* 508 */, MIPS_INS_LA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dla $rt, $imm64 */ + Mips_LoadAddrImm64 /* 509 */, MIPS_INS_DLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* la $rt, $addr */ + Mips_LoadAddrReg32 /* 510 */, MIPS_INS_LA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dla $rt, $addr */ + Mips_LoadAddrReg64 /* 511 */, MIPS_INS_DLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li $rt, $imm32 */ + Mips_LoadImm32 /* 512 */, MIPS_INS_LI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dli $rt, $imm64 */ + Mips_LoadImm64 /* 513 */, MIPS_INS_DLI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li.d $rd, $fpimm */ + Mips_LoadImmDoubleFGR /* 514 */, MIPS_INS_LI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li.d $rd, $fpimm */ + Mips_LoadImmDoubleFGR_32 /* 515 */, MIPS_INS_LI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li.d $rd, $fpimm */ + Mips_LoadImmDoubleGPR /* 516 */, MIPS_INS_LI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li.s $rd, $fpimm */ + Mips_LoadImmSingleFGR /* 517 */, MIPS_INS_LI_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li.s $rd, $fpimm */ + Mips_LoadImmSingleGPR /* 518 */, MIPS_INS_LI_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_LoadJumpTableOffset /* 519 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lw $rx, 1f + b 2f + .align 2 +1: .word $imm +2: */ + Mips_LwConstant32 /* 520 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* mftacx $rt, $ac */ + Mips_MFTACX /* 521 */, MIPS_INS_MFTACX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftacx $rt, $ac */ + Mips_MFTACX_NM /* 522 */, MIPS_INS_MFTACX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftc0 $rd, $rt, $sel */ + Mips_MFTC0 /* 523 */, MIPS_INS_MFTC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftc0 $rd, $rt, $sel */ + Mips_MFTC0_NM /* 524 */, MIPS_INS_MFTC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftc1 $rt, $ft */ + Mips_MFTC1 /* 525 */, MIPS_INS_MFTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftdsp $rt */ + Mips_MFTDSP /* 526 */, MIPS_INS_MFTDSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftdsp $rt */ + Mips_MFTDSP_NM /* 527 */, MIPS_INS_MFTDSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftgpr $rd, $rt */ + Mips_MFTGPR /* 528 */, MIPS_INS_MFTGPR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftgpr $rd, $rt */ + Mips_MFTGPR_NM /* 529 */, MIPS_INS_MFTGPR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfthc1 $rt, $ft */ + Mips_MFTHC1 /* 530 */, MIPS_INS_MFTHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfthi $rt, $ac */ + Mips_MFTHI /* 531 */, MIPS_INS_MFTHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfthi $rt, $ac */ + Mips_MFTHI_NM /* 532 */, MIPS_INS_MFTHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftlo $rt, $ac */ + Mips_MFTLO /* 533 */, MIPS_INS_MFTLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftlo $rt, $ac */ + Mips_MFTLO_NM /* 534 */, MIPS_INS_MFTLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_MIPSeh_return32 /* 535 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_MIPSeh_return64 /* 536 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_MSA_FP_EXTEND_D_PSEUDO /* 537 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_MSA_FP_EXTEND_W_PSEUDO /* 538 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_MSA_FP_ROUND_D_PSEUDO /* 539 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_MSA_FP_ROUND_W_PSEUDO /* 540 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* mttacx $rt, $ac */ + Mips_MTTACX /* 541 */, MIPS_INS_MTTACX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttacx $rt, $ac */ + Mips_MTTACX_NM /* 542 */, MIPS_INS_MTTACX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttc0 $rt, $rd, $sel */ + Mips_MTTC0 /* 543 */, MIPS_INS_MTTC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttc0 $rt, $rd, $sel */ + Mips_MTTC0_NM /* 544 */, MIPS_INS_MTTC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttc1 $rt, $ft */ + Mips_MTTC1 /* 545 */, MIPS_INS_MTTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttdsp $rt */ + Mips_MTTDSP /* 546 */, MIPS_INS_MTTDSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttdsp $rt */ + Mips_MTTDSP_NM /* 547 */, MIPS_INS_MTTDSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttgpr $rd, $rt */ + Mips_MTTGPR /* 548 */, MIPS_INS_MTTGPR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttgpr $rd, $rt */ + Mips_MTTGPR_NM /* 549 */, MIPS_INS_MTTGPR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtthc1 $rt, $ft */ + Mips_MTTHC1 /* 550 */, MIPS_INS_MTTHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtthi $rt, $ac */ + Mips_MTTHI /* 551 */, MIPS_INS_MTTHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtthi $rt, $ac */ + Mips_MTTHI_NM /* 552 */, MIPS_INS_MTTHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttlo $rt, $ac */ + Mips_MTTLO /* 553 */, MIPS_INS_MTTLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttlo $rt, $ac */ + Mips_MTTLO_NM /* 554 */, MIPS_INS_MTTLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul $rd, $rs, $imm */ + Mips_MULImmMacro /* 555 */, MIPS_INS_MUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulo $rd, $rs, $rt */ + Mips_MULOMacro /* 556 */, MIPS_INS_MULO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulou $rd, $rs, $rt */ + Mips_MULOUMacro /* 557 */, MIPS_INS_MULOU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_MUSTTAILCALLREG_NM /* 558 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_MUSTTAILCALL_NM /* 559 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* mult $rx, $ry */ + Mips_MultRxRy16 /* 560 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* mult $rx, $ry + mflo $rz */ + Mips_MultRxRyRz16 /* 561 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* multu $rx, $ry */ + Mips_MultuRxRy16 /* 562 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* multu $rx, $ry + mflo $rz */ + Mips_MultuRxRyRz16 /* 563 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_NOP /* 564 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* nor $rs, $rt, $imm */ + Mips_NORImm /* 565 */, MIPS_INS_NOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP32BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nor $rs, $rt, $imm */ + Mips_NORImm64 /* 566 */, MIPS_INS_NOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_NOR_V_D_PSEUDO /* 567 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_NOR_V_H_PSEUDO /* 568 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_NOR_V_W_PSEUDO /* 569 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_OR_V_D_PSEUDO /* 570 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_OR_V_H_PSEUDO /* 571 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_OR_V_W_PSEUDO /* 572 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* addiu $rt, $rs, $imm */ + Mips_PseudoADDIU_NM /* 573 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* andi $rt, $rs, $mask */ + Mips_PseudoANDI_NM /* 574 */, MIPS_INS_ANDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_PseudoCMPU_EQ_QB /* 575 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoCMPU_LE_QB /* 576 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoCMPU_LT_QB /* 577 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoCMP_EQ_PH /* 578 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoCMP_LE_PH /* 579 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoCMP_LT_PH /* 580 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $fd, $fs */ + Mips_PseudoCVT_D32_W /* 581 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $fd, $fs */ + Mips_PseudoCVT_D64_L /* 582 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $fd, $fs */ + Mips_PseudoCVT_D64_W /* 583 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $fd, $fs */ + Mips_PseudoCVT_S_L /* 584 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $fd, $fs */ + Mips_PseudoCVT_S_W /* 585 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoDMULT /* 586 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoDMULTu /* 587 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoDSDIV /* 588 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoDUDIV /* 589 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoD_SELECT_I /* 590 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoD_SELECT_I64 /* 591 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndirectBranch /* 592 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndirectBranch64 /* 593 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndirectBranch64R6 /* 594 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndirectBranchNM /* 595 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndirectBranchR6 /* 596 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndirectBranch_MM /* 597 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndirectBranch_MMR6 /* 598 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndirectHazardBranch /* 599 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndirectHazardBranch64 /* 600 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndrectHazardBranch64R6 /* 601 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoIndrectHazardBranchR6 /* 602 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* la $rt, $addr */ + Mips_PseudoLA_NM /* 603 */, MIPS_INS_LA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li $rt, $imm */ + Mips_PseudoLI_NM /* 604 */, MIPS_INS_LI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_PseudoMADD /* 605 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMADDU /* 606 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMADDU_MM /* 607 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMADD_MM /* 608 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMFHI /* 609 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMFHI64 /* 610 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMFHI_MM /* 611 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMFLO /* 612 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMFLO64 /* 613 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMFLO_MM /* 614 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMSUB /* 615 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMSUBU /* 616 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMSUBU_MM /* 617 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMSUB_MM /* 618 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMTLOHI /* 619 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMTLOHI64 /* 620 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMTLOHI_DSP /* 621 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMTLOHI_MM /* 622 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMULT /* 623 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMULT_MM /* 624 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMULTu /* 625 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoMULTu_MM /* 626 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoPICK_PH /* 627 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoPICK_QB /* 628 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoReturn /* 629 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoReturn64 /* 630 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoReturnNM /* 631 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSDIV /* 632 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_F_D32 /* 633 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_F_D64 /* 634 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_F_I /* 635 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_F_I64 /* 636 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_F_S /* 637 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_T_D32 /* 638 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_T_D64 /* 639 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_T_I /* 640 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_T_I64 /* 641 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECTFP_T_S /* 642 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECT_D32 /* 643 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECT_D64 /* 644 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECT_I /* 645 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECT_I64 /* 646 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_PseudoSELECT_S /* 647 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* subu $rt, $rs, $imm */ + Mips_PseudoSUBU_NM /* 648 */, MIPS_INS_SUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.d $fd, $fs, $rs */ + Mips_PseudoTRUNC_W_D /* 649 */, MIPS_INS_TRUNC_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.d $fd, $fs, $rs */ + Mips_PseudoTRUNC_W_D32 /* 650 */, MIPS_INS_TRUNC_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.s $fd, $fs, $rs */ + Mips_PseudoTRUNC_W_S /* 651 */, MIPS_INS_TRUNC_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_PseudoUDIV /* 652 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* rol $rs, $rt, $rd */ + Mips_ROL /* 653 */, MIPS_INS_ROL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rol $rs, $rt, $imm */ + Mips_ROLImm /* 654 */, MIPS_INS_ROL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ror $rs, $rt, $rd */ + Mips_ROR /* 655 */, MIPS_INS_ROR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ror $rs, $rt, $imm */ + Mips_RORImm /* 656 */, MIPS_INS_ROR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_RetRA /* 657 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_RetRA16 /* 658 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* s.d $fd, $addr */ + Mips_SDC1_M1 /* 659 */, MIPS_INS_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_SDIV_MM_Pseudo /* 660 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sd $rt, $addr */ + Mips_SDMacro /* 661 */, MIPS_INS_SD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div $rd, $rs, $imm */ + Mips_SDivIMacro /* 662 */, MIPS_INS_DIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div $rd, $rs, $rt */ + Mips_SDivMacro /* 663 */, MIPS_INS_DIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seq $rd, $rs, $imm */ + Mips_SEQIMacro /* 664 */, MIPS_INS_SEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_NOTCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seq $rd, $rs, $rt */ + Mips_SEQMacro /* 665 */, MIPS_INS_SEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_NOTCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sge $rd, $rs, $rt */ + Mips_SGE /* 666 */, MIPS_INS_SGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sge $rd, $rs, $imm */ + Mips_SGEImm /* 667 */, MIPS_INS_SGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP32BIT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sge $rd, $rs, $imm */ + Mips_SGEImm64 /* 668 */, MIPS_INS_SGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sgeu $rd, $rs, $rt */ + Mips_SGEU /* 669 */, MIPS_INS_SGEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sgeu $rd, $rs, $imm */ + Mips_SGEUImm /* 670 */, MIPS_INS_SGEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP32BIT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sgeu $rd, $rs, $imm */ + Mips_SGEUImm64 /* 671 */, MIPS_INS_SGEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sgt $rd, $rs, $imm */ + Mips_SGTImm /* 672 */, MIPS_INS_SGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP32BIT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sgt $rd, $rs, $imm */ + Mips_SGTImm64 /* 673 */, MIPS_INS_SGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sgtu $rd, $rs, $imm */ + Mips_SGTUImm /* 674 */, MIPS_INS_SGTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP32BIT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sgtu $rd, $rs, $imm */ + Mips_SGTUImm64 /* 675 */, MIPS_INS_SGTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sle $rd, $rs, $rt */ + Mips_SLE /* 676 */, MIPS_INS_SLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sle $rd, $rs, $imm */ + Mips_SLEImm /* 677 */, MIPS_INS_SLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP32BIT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sle $rd, $rs, $imm */ + Mips_SLEImm64 /* 678 */, MIPS_INS_SLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sleu $rd, $rs, $rt */ + Mips_SLEU /* 679 */, MIPS_INS_SLEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sleu $rd, $rs, $imm */ + Mips_SLEUImm /* 680 */, MIPS_INS_SLEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP32BIT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sleu $rd, $rs, $imm */ + Mips_SLEUImm64 /* 681 */, MIPS_INS_SLEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slt $rs, $rt, $imm */ + Mips_SLTImm64 /* 682 */, MIPS_INS_SLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sltu $rs, $rt, $imm */ + Mips_SLTUImm64 /* 683 */, MIPS_INS_SLTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_ISGP64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sne $rd, $rs, $imm */ + Mips_SNEIMacro /* 684 */, MIPS_INS_SNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_NOTCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sne $rd, $rs, $rt */ + Mips_SNEMacro /* 685 */, MIPS_INS_SNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_NOTCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_SNZ_B_PSEUDO /* 686 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SNZ_D_PSEUDO /* 687 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SNZ_H_PSEUDO /* 688 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SNZ_V_PSEUDO /* 689 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SNZ_W_PSEUDO /* 690 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* rem $rd, $rs, $imm */ + Mips_SRemIMacro /* 691 */, MIPS_INS_REM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rem $rd, $rs, $rt */ + Mips_SRemMacro /* 692 */, MIPS_INS_REM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* $rt, $addr */ + Mips_STORE_ACC128 /* 693 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $rt, $addr */ + Mips_STORE_ACC64 /* 694 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* $rt, $addr */ + Mips_STORE_ACC64DSP /* 695 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* store_ccond_dsp $rt, $addr */ + Mips_STORE_CCOND_DSP /* 696 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_STR_D /* 697 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_STR_W /* 698 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_ST_F16 /* 699 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* swm $rt, $addr */ + Mips_SWM_MM /* 700 */, MIPS_INS_SWM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_SZ_B_PSEUDO /* 701 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SZ_D_PSEUDO /* 702 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SZ_H_PSEUDO /* 703 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SZ_V_PSEUDO /* 704 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SZ_W_PSEUDO /* 705 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* saa $rt, $addr */ + Mips_SaaAddr /* 706 */, MIPS_INS_SAA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* saad $rt, $addr */ + Mips_SaadAddr /* 707 */, MIPS_INS_SAAD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* beqz $rt, .+4 + + move $rd, $rs */ + Mips_SelBeqZ /* 708 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* bnez $rt, .+4 + + move $rd, $rs */ + Mips_SelBneZ /* 709 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cmp $rl, $rr + bteqz .+4 + move $rd, $rs */ + Mips_SelTBteqZCmp /* 710 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cmpi $rl, $imm + bteqz .+4 + move $rd, $rs */ + Mips_SelTBteqZCmpi /* 711 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slt $rl, $rr + bteqz .+4 + move $rd, $rs */ + Mips_SelTBteqZSlt /* 712 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slti $rl, $imm + bteqz .+4 + move $rd, $rs */ + Mips_SelTBteqZSlti /* 713 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltiu $rl, $imm + bteqz .+4 + move $rd, $rs */ + Mips_SelTBteqZSltiu /* 714 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltu $rl, $rr + bteqz .+4 + move $rd, $rs */ + Mips_SelTBteqZSltu /* 715 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cmp $rl, $rr + btnez .+4 + move $rd, $rs */ + Mips_SelTBtneZCmp /* 716 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cmpi $rl, $imm + btnez .+4 + move $rd, $rs */ + Mips_SelTBtneZCmpi /* 717 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slt $rl, $rr + btnez .+4 + move $rd, $rs */ + Mips_SelTBtneZSlt /* 718 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slti $rl, $imm + btnez .+4 + move $rd, $rs */ + Mips_SelTBtneZSlti /* 719 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltiu $rl, $imm + btnez .+4 + move $rd, $rs */ + Mips_SelTBtneZSltiu /* 720 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltu $rl, $rr + btnez .+4 + move $rd, $rs */ + Mips_SelTBtneZSltu /* 721 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slt $rx, $ry + move $cc, $$t8 */ + Mips_SltCCRxRy16 /* 722 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slti $rx, $imm + move $cc, $$t8 */ + Mips_SltiCCRxImmX16 /* 723 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltiu $rx, $imm + move $cc, $$t8 */ + Mips_SltiuCCRxImmX16 /* 724 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltu $rx, $ry + move $cc, $$t8 */ + Mips_SltuCCRxRy16 /* 725 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltu $rx, $ry + move $rz, $$t8 */ + Mips_SltuRxRyRz16 /* 726 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALL /* 727 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALL64R6REG /* 728 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLHB64R6REG /* 729 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLHBR6REG /* 730 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLR6REG /* 731 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLREG /* 732 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLREG64 /* 733 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLREGHB /* 734 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLREGHB64 /* 735 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLREG_MM /* 736 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLREG_MMR6 /* 737 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALLREG_NM /* 738 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALL_MM /* 739 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALL_MMR6 /* 740 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TAILCALL_NM /* 741 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TRAP /* 742 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_TRAP_MM /* 743 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_UDIV_MM_Pseudo /* 744 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* divu $rd, $rs, $imm */ + Mips_UDivIMacro /* 745 */, MIPS_INS_DIVU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* divu $rd, $rs, $rt */ + Mips_UDivMacro /* 746 */, MIPS_INS_DIVU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* remu $rd, $rs, $imm */ + Mips_URemIMacro /* 747 */, MIPS_INS_REMU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* remu $rd, $rs, $rt */ + Mips_URemMacro /* 748 */, MIPS_INS_REMU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ulh $rt, $addr */ + Mips_Ulh /* 749 */, MIPS_INS_ULH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ulhu $rt, $addr */ + Mips_Ulhu /* 750 */, MIPS_INS_ULHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ulw $rt, $addr */ + Mips_Ulw /* 751 */, MIPS_INS_ULW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ush $rt, $addr */ + Mips_Ush /* 752 */, MIPS_INS_USH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* usw $rt, $addr */ + Mips_Usw /* 753 */, MIPS_INS_USW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_XOR_V_D_PSEUDO /* 754 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_XOR_V_H_PSEUDO /* 755 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_XOR_V_W_PSEUDO /* 756 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* absq_s.ph $rd, $rt */ + Mips_ABSQ_S_PH /* 757 */, MIPS_INS_ABSQ_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* absq_s.ph $rt, $rs */ + Mips_ABSQ_S_PH_MM /* 758 */, MIPS_INS_ABSQ_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* absq_s.qb $rd, $rt */ + Mips_ABSQ_S_QB /* 759 */, MIPS_INS_ABSQ_S_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* absq_s.qb $rt, $rs */ + Mips_ABSQ_S_QB_MMR2 /* 760 */, MIPS_INS_ABSQ_S_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* absq_s.w $rd, $rt */ + Mips_ABSQ_S_W /* 761 */, MIPS_INS_ABSQ_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* absq_s.w $rt, $rs */ + Mips_ABSQ_S_W_MM /* 762 */, MIPS_INS_ABSQ_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add $rd, $rs, $rt */ + Mips_ADD /* 763 */, MIPS_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu[48] $rt, $rs, $imm */ + Mips_ADDIU48_NM /* 764 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu[gp48] $rt, $rs, $addr */ + Mips_ADDIUGP48_NM /* 765 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu[gp.b] $rt, $rs, $offset */ + Mips_ADDIUGPB_NM /* 766 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu[gp.w] $rt, $rs, $offset */ + Mips_ADDIUGPW_NM /* 767 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu[neg] $rt, $rs, $imm */ + Mips_ADDIUNEG_NM /* 768 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiupc $rs, $imm */ + Mips_ADDIUPC /* 769 */, MIPS_INS_ADDIUPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiupc $rs, $imm */ + Mips_ADDIUPC_MM /* 770 */, MIPS_INS_ADDIUPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiupc $rt, $imm */ + Mips_ADDIUPC_MMR6 /* 771 */, MIPS_INS_ADDIUPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiur1sp $rd, $imm */ + Mips_ADDIUR1SP_MM /* 772 */, MIPS_INS_ADDIUR1SP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu[r1.sp] $rt, $rs, $imm */ + Mips_ADDIUR1SP_NM /* 773 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiur2 $rd, $rs, $imm */ + Mips_ADDIUR2_MM /* 774 */, MIPS_INS_ADDIUR2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu[r2] $rt, $rs, $imm */ + Mips_ADDIUR2_NM /* 775 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu[rs5] $rt, $rs, $imm */ + Mips_ADDIURS5_NM /* 776 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addius5 $rd, $imm */ + Mips_ADDIUS5_MM /* 777 */, MIPS_INS_ADDIUS5, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiusp $imm */ + Mips_ADDIUSP_MM /* 778 */, MIPS_INS_ADDIUSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $rt, $rs, $imm16 */ + Mips_ADDIU_MMR6 /* 779 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu[32] $rt, $rs, $imm */ + Mips_ADDIU_NM /* 780 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addqh.ph $rd, $rs, $rt */ + Mips_ADDQH_PH /* 781 */, MIPS_INS_ADDQH_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addqh.ph $rd, $rs, $rt */ + Mips_ADDQH_PH_MMR2 /* 782 */, MIPS_INS_ADDQH_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addqh_r.ph $rd, $rs, $rt */ + Mips_ADDQH_R_PH /* 783 */, MIPS_INS_ADDQH_R_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addqh_r.ph $rd, $rs, $rt */ + Mips_ADDQH_R_PH_MMR2 /* 784 */, MIPS_INS_ADDQH_R_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addqh_r.w $rd, $rs, $rt */ + Mips_ADDQH_R_W /* 785 */, MIPS_INS_ADDQH_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addqh_r.w $rd, $rs, $rt */ + Mips_ADDQH_R_W_MMR2 /* 786 */, MIPS_INS_ADDQH_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addqh.w $rd, $rs, $rt */ + Mips_ADDQH_W /* 787 */, MIPS_INS_ADDQH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addqh.w $rd, $rs, $rt */ + Mips_ADDQH_W_MMR2 /* 788 */, MIPS_INS_ADDQH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addq.ph $rd, $rs, $rt */ + Mips_ADDQ_PH /* 789 */, MIPS_INS_ADDQ_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addq.ph $rd, $rs, $rt */ + Mips_ADDQ_PH_MM /* 790 */, MIPS_INS_ADDQ_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addq_s.ph $rd, $rs, $rt */ + Mips_ADDQ_S_PH /* 791 */, MIPS_INS_ADDQ_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addq_s.ph $rd, $rs, $rt */ + Mips_ADDQ_S_PH_MM /* 792 */, MIPS_INS_ADDQ_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addq_s.w $rd, $rs, $rt */ + Mips_ADDQ_S_W /* 793 */, MIPS_INS_ADDQ_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addq_s.w $rd, $rs, $rt */ + Mips_ADDQ_S_W_MM /* 794 */, MIPS_INS_ADDQ_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addr.ps $fd, $fs, $ft */ + Mips_ADDR_PS64 /* 795 */, MIPS_INS_ADDR_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMIPS3D, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addsc $rd, $rs, $rt */ + Mips_ADDSC /* 796 */, MIPS_INS_ADDSC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCARRY, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addsc $rd, $rs, $rt */ + Mips_ADDSC_MM /* 797 */, MIPS_INS_ADDSC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCARRY, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_a.b $wd, $ws, $wt */ + Mips_ADDS_A_B /* 798 */, MIPS_INS_ADDS_A_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_a.d $wd, $ws, $wt */ + Mips_ADDS_A_D /* 799 */, MIPS_INS_ADDS_A_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_a.h $wd, $ws, $wt */ + Mips_ADDS_A_H /* 800 */, MIPS_INS_ADDS_A_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_a.w $wd, $ws, $wt */ + Mips_ADDS_A_W /* 801 */, MIPS_INS_ADDS_A_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_s.b $wd, $ws, $wt */ + Mips_ADDS_S_B /* 802 */, MIPS_INS_ADDS_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_s.d $wd, $ws, $wt */ + Mips_ADDS_S_D /* 803 */, MIPS_INS_ADDS_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_s.h $wd, $ws, $wt */ + Mips_ADDS_S_H /* 804 */, MIPS_INS_ADDS_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_s.w $wd, $ws, $wt */ + Mips_ADDS_S_W /* 805 */, MIPS_INS_ADDS_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_u.b $wd, $ws, $wt */ + Mips_ADDS_U_B /* 806 */, MIPS_INS_ADDS_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_u.d $wd, $ws, $wt */ + Mips_ADDS_U_D /* 807 */, MIPS_INS_ADDS_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_u.h $wd, $ws, $wt */ + Mips_ADDS_U_H /* 808 */, MIPS_INS_ADDS_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adds_u.w $wd, $ws, $wt */ + Mips_ADDS_U_W /* 809 */, MIPS_INS_ADDS_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu16 $rd, $rs, $rt */ + Mips_ADDU16_MM /* 810 */, MIPS_INS_ADDU16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu16 $rd, $rs, $rt */ + Mips_ADDU16_MMR6 /* 811 */, MIPS_INS_ADDU16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adduh.qb $rd, $rs, $rt */ + Mips_ADDUH_QB /* 812 */, MIPS_INS_ADDUH_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adduh.qb $rd, $rs, $rt */ + Mips_ADDUH_QB_MMR2 /* 813 */, MIPS_INS_ADDUH_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adduh_r.qb $rd, $rs, $rt */ + Mips_ADDUH_R_QB /* 814 */, MIPS_INS_ADDUH_R_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* adduh_r.qb $rd, $rs, $rt */ + Mips_ADDUH_R_QB_MMR2 /* 815 */, MIPS_INS_ADDUH_R_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu $rd, $rs, $rt */ + Mips_ADDU_MMR6 /* 816 */, MIPS_INS_ADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu.ph $rd, $rs, $rt */ + Mips_ADDU_PH /* 817 */, MIPS_INS_ADDU_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu.ph $rd, $rs, $rt */ + Mips_ADDU_PH_MMR2 /* 818 */, MIPS_INS_ADDU_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu.qb $rd, $rs, $rt */ + Mips_ADDU_QB /* 819 */, MIPS_INS_ADDU_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu.qb $rd, $rs, $rt */ + Mips_ADDU_QB_MM /* 820 */, MIPS_INS_ADDU_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu_s.ph $rd, $rs, $rt */ + Mips_ADDU_S_PH /* 821 */, MIPS_INS_ADDU_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu_s.ph $rd, $rs, $rt */ + Mips_ADDU_S_PH_MMR2 /* 822 */, MIPS_INS_ADDU_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu_s.qb $rd, $rs, $rt */ + Mips_ADDU_S_QB /* 823 */, MIPS_INS_ADDU_S_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu_s.qb $rd, $rs, $rt */ + Mips_ADDU_S_QB_MM /* 824 */, MIPS_INS_ADDU_S_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addvi.b $wd, $ws, $imm */ + Mips_ADDVI_B /* 825 */, MIPS_INS_ADDVI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addvi.d $wd, $ws, $imm */ + Mips_ADDVI_D /* 826 */, MIPS_INS_ADDVI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addvi.h $wd, $ws, $imm */ + Mips_ADDVI_H /* 827 */, MIPS_INS_ADDVI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addvi.w $wd, $ws, $imm */ + Mips_ADDVI_W /* 828 */, MIPS_INS_ADDVI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addv.b $wd, $ws, $wt */ + Mips_ADDV_B /* 829 */, MIPS_INS_ADDV_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addv.d $wd, $ws, $wt */ + Mips_ADDV_D /* 830 */, MIPS_INS_ADDV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addv.h $wd, $ws, $wt */ + Mips_ADDV_H /* 831 */, MIPS_INS_ADDV_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addv.w $wd, $ws, $wt */ + Mips_ADDV_W /* 832 */, MIPS_INS_ADDV_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addwc $rd, $rs, $rt */ + Mips_ADDWC /* 833 */, MIPS_INS_ADDWC, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPCARRY, 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addwc $rd, $rs, $rt */ + Mips_ADDWC_MM /* 834 */, MIPS_INS_ADDWC, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPCARRY, 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add_a.b $wd, $ws, $wt */ + Mips_ADD_A_B /* 835 */, MIPS_INS_ADD_A_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add_a.d $wd, $ws, $wt */ + Mips_ADD_A_D /* 836 */, MIPS_INS_ADD_A_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add_a.h $wd, $ws, $wt */ + Mips_ADD_A_H /* 837 */, MIPS_INS_ADD_A_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add_a.w $wd, $ws, $wt */ + Mips_ADD_A_W /* 838 */, MIPS_INS_ADD_A_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add $rd, $rs, $rt */ + Mips_ADD_MM /* 839 */, MIPS_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add $rd, $rs, $rt */ + Mips_ADD_MMR6 /* 840 */, MIPS_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add $rd, $rs, $rt */ + Mips_ADD_NM /* 841 */, MIPS_INS_ADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addi $rt, $rs, $imm16 */ + Mips_ADDi /* 842 */, MIPS_INS_ADDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addi $rt, $rs, $imm16 */ + Mips_ADDi_MM /* 843 */, MIPS_INS_ADDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $rt, $rs, $imm16 */ + Mips_ADDiu /* 844 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $rt, $rs, $imm16 */ + Mips_ADDiu_MM /* 845 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu $rd, $rs, $rt */ + Mips_ADDu /* 846 */, MIPS_INS_ADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu $rd, $rs, $rt */ + Mips_ADDu16_NM /* 847 */, MIPS_INS_ADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu $dst, $rt, $rs */ + Mips_ADDu4x4_NM /* 848 */, MIPS_INS_ADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu $rd, $rs, $rt */ + Mips_ADDu_MM /* 849 */, MIPS_INS_ADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu $rd, $rs, $rt */ + Mips_ADDu_NM /* 850 */, MIPS_INS_ADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* align $rd, $rs, $rt, $bp */ + Mips_ALIGN /* 851 */, MIPS_INS_ALIGN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* align $rd, $rs, $rt, $bp */ + Mips_ALIGN_MMR6 /* 852 */, MIPS_INS_ALIGN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aluipc $rs, $imm */ + Mips_ALUIPC /* 853 */, MIPS_INS_ALUIPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aluipc $rt, $imm */ + Mips_ALUIPC_MMR6 /* 854 */, MIPS_INS_ALUIPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aluipc $rt, $imm */ + Mips_ALUIPC_NM /* 855 */, MIPS_INS_ALUIPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and $rd, $rs, $rt */ + Mips_AND /* 856 */, MIPS_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and16 $rt, $rs */ + Mips_AND16_MM /* 857 */, MIPS_INS_AND16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and16 $rt, $rs */ + Mips_AND16_MMR6 /* 858 */, MIPS_INS_AND16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and $dst, $rs, $rt */ + Mips_AND16_NM /* 859 */, MIPS_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and $rd, $rs, $rt */ + Mips_AND64 /* 860 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* andi16 $rd, $rs, $imm */ + Mips_ANDI16_MM /* 861 */, MIPS_INS_ANDI16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* andi16 $rd, $rs, $imm */ + Mips_ANDI16_MMR6 /* 862 */, MIPS_INS_ANDI16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* andi[16] $rt, $rs, $imm */ + Mips_ANDI16_NM /* 863 */, MIPS_INS_ANDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* andi.b $wd, $ws, $u8 */ + Mips_ANDI_B /* 864 */, MIPS_INS_ANDI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* andi $rt, $rs, $imm16 */ + Mips_ANDI_MMR6 /* 865 */, MIPS_INS_ANDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* andi[32] $rt, $rs, $imm */ + Mips_ANDI_NM /* 866 */, MIPS_INS_ANDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and $rd, $rs, $rt */ + Mips_AND_MM /* 867 */, MIPS_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and $rd, $rs, $rt */ + Mips_AND_MMR6 /* 868 */, MIPS_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and $rd, $rs, $rt */ + Mips_AND_NM /* 869 */, MIPS_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and.v $wd, $ws, $wt */ + Mips_AND_V /* 870 */, MIPS_INS_AND_V, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* andi $rt, $rs, $imm16 */ + Mips_ANDi /* 871 */, MIPS_INS_ANDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* andi $rt, $rs, $imm16 */ + Mips_ANDi64 /* 872 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* andi $rt, $rs, $imm16 */ + Mips_ANDi_MM /* 873 */, MIPS_INS_ANDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* append $rt, $rs, $sa */ + Mips_APPEND /* 874 */, MIPS_INS_APPEND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* append $rt, $rs, $sa */ + Mips_APPEND_MMR2 /* 875 */, MIPS_INS_APPEND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* asub_s.b $wd, $ws, $wt */ + Mips_ASUB_S_B /* 876 */, MIPS_INS_ASUB_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* asub_s.d $wd, $ws, $wt */ + Mips_ASUB_S_D /* 877 */, MIPS_INS_ASUB_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* asub_s.h $wd, $ws, $wt */ + Mips_ASUB_S_H /* 878 */, MIPS_INS_ASUB_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* asub_s.w $wd, $ws, $wt */ + Mips_ASUB_S_W /* 879 */, MIPS_INS_ASUB_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* asub_u.b $wd, $ws, $wt */ + Mips_ASUB_U_B /* 880 */, MIPS_INS_ASUB_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* asub_u.d $wd, $ws, $wt */ + Mips_ASUB_U_D /* 881 */, MIPS_INS_ASUB_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* asub_u.h $wd, $ws, $wt */ + Mips_ASUB_U_H /* 882 */, MIPS_INS_ASUB_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* asub_u.w $wd, $ws, $wt */ + Mips_ASUB_U_W /* 883 */, MIPS_INS_ASUB_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aui $rt, $rs, $imm */ + Mips_AUI /* 884 */, MIPS_INS_AUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* auipc $rs, $imm */ + Mips_AUIPC /* 885 */, MIPS_INS_AUIPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* auipc $rt, $imm */ + Mips_AUIPC_MMR6 /* 886 */, MIPS_INS_AUIPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aui $rt, $rs, $imm */ + Mips_AUI_MMR6 /* 887 */, MIPS_INS_AUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aver_s.b $wd, $ws, $wt */ + Mips_AVER_S_B /* 888 */, MIPS_INS_AVER_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aver_s.d $wd, $ws, $wt */ + Mips_AVER_S_D /* 889 */, MIPS_INS_AVER_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aver_s.h $wd, $ws, $wt */ + Mips_AVER_S_H /* 890 */, MIPS_INS_AVER_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aver_s.w $wd, $ws, $wt */ + Mips_AVER_S_W /* 891 */, MIPS_INS_AVER_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aver_u.b $wd, $ws, $wt */ + Mips_AVER_U_B /* 892 */, MIPS_INS_AVER_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aver_u.d $wd, $ws, $wt */ + Mips_AVER_U_D /* 893 */, MIPS_INS_AVER_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aver_u.h $wd, $ws, $wt */ + Mips_AVER_U_H /* 894 */, MIPS_INS_AVER_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* aver_u.w $wd, $ws, $wt */ + Mips_AVER_U_W /* 895 */, MIPS_INS_AVER_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ave_s.b $wd, $ws, $wt */ + Mips_AVE_S_B /* 896 */, MIPS_INS_AVE_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ave_s.d $wd, $ws, $wt */ + Mips_AVE_S_D /* 897 */, MIPS_INS_AVE_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ave_s.h $wd, $ws, $wt */ + Mips_AVE_S_H /* 898 */, MIPS_INS_AVE_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ave_s.w $wd, $ws, $wt */ + Mips_AVE_S_W /* 899 */, MIPS_INS_AVE_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ave_u.b $wd, $ws, $wt */ + Mips_AVE_U_B /* 900 */, MIPS_INS_AVE_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ave_u.d $wd, $ws, $wt */ + Mips_AVE_U_D /* 901 */, MIPS_INS_AVE_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ave_u.h $wd, $ws, $wt */ + Mips_AVE_U_H /* 902 */, MIPS_INS_AVE_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ave_u.w $wd, $ws, $wt */ + Mips_AVE_U_W /* 903 */, MIPS_INS_AVE_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $rx, $imm16 */ + Mips_AddiuRxImmX16 /* 904 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $rx, $$pc, $imm16 */ + Mips_AddiuRxPcImmX16 /* 905 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $rx, $imm8 # 16 bit inst */ + Mips_AddiuRxRxImm16 /* 906 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $rx, $imm16 */ + Mips_AddiuRxRxImmX16 /* 907 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* addiu $ry, $addr */ + Mips_AddiuRxRyOffMemX16 /* 908 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $$sp, $imm8 # 16 bit inst */ + Mips_AddiuSpImm16 /* 909 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $$sp, $imm16 */ + Mips_AddiuSpImmX16 /* 910 */, MIPS_INS_ADDIU, + #ifndef CAPSTONE_DIET + { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addu $rz, $rx, $ry */ + Mips_AdduRxRyRz16 /* 911 */, MIPS_INS_ADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* and $rz, $ry */ + Mips_AndRxRxRy16 /* 912 */, MIPS_INS_AND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* b16 $offset */ + Mips_B16_MM /* 913 */, MIPS_INS_B16, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* baddu $rd, $rs, $rt */ + Mips_BADDu /* 914 */, MIPS_INS_BADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bal $offset */ + Mips_BAL /* 915 */, MIPS_INS_BAL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* balc $offset */ + Mips_BALC /* 916 */, MIPS_INS_BALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* balc[16] $addr */ + Mips_BALC16_NM /* 917 */, MIPS_INS_BALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA_NM, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* balc $offset */ + Mips_BALC_MMR6 /* 918 */, MIPS_INS_BALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* balc $addr */ + Mips_BALC_NM /* 919 */, MIPS_INS_BALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA_NM, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* balign $rt, $rs, $sa */ + Mips_BALIGN /* 920 */, MIPS_INS_BALIGN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* balign $rt, $rs, $bp */ + Mips_BALIGN_MMR2 /* 921 */, MIPS_INS_BALIGN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* balrsc $rt, $rs */ + Mips_BALRSC_NM /* 922 */, MIPS_INS_BALRSC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bbeqzc $rt, $u, $offset */ + Mips_BBEQZC_NM /* 923 */, MIPS_INS_BBEQZC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bbit0 $rs, $p, $offset */ + Mips_BBIT0 /* 924 */, MIPS_INS_BBIT0, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASCNMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bbit032 $rs, $p, $offset */ + Mips_BBIT032 /* 925 */, MIPS_INS_BBIT032, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASCNMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bbit1 $rs, $p, $offset */ + Mips_BBIT1 /* 926 */, MIPS_INS_BBIT1, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASCNMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bbit132 $rs, $p, $offset */ + Mips_BBIT132 /* 927 */, MIPS_INS_BBIT132, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASCNMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bbnezc $rt, $u, $offset */ + Mips_BBNEZC_NM /* 928 */, MIPS_INS_BBNEZC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc $offset */ + Mips_BC /* 929 */, MIPS_INS_BC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc16 $offset */ + Mips_BC16_MMR6 /* 930 */, MIPS_INS_BC16, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc $addr */ + Mips_BC16_NM /* 931 */, MIPS_INS_BC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1eqz $ft, $offset */ + Mips_BC1EQZ /* 932 */, MIPS_INS_BC1EQZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1eqzc $rt, $offset */ + Mips_BC1EQZC_MMR6 /* 933 */, MIPS_INS_BC1EQZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1f $fcc, $offset */ + Mips_BC1F /* 934 */, MIPS_INS_BC1F, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1fl $fcc, $offset */ + Mips_BC1FL /* 935 */, MIPS_INS_BC1FL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1f $fcc, $offset */ + Mips_BC1F_MM /* 936 */, MIPS_INS_BC1F, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1nez $ft, $offset */ + Mips_BC1NEZ /* 937 */, MIPS_INS_BC1NEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1nezc $rt, $offset */ + Mips_BC1NEZC_MMR6 /* 938 */, MIPS_INS_BC1NEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1t $fcc, $offset */ + Mips_BC1T /* 939 */, MIPS_INS_BC1T, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1tl $fcc, $offset */ + Mips_BC1TL /* 940 */, MIPS_INS_BC1TL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc1t $fcc, $offset */ + Mips_BC1T_MM /* 941 */, MIPS_INS_BC1T, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc2eqz $ct, $offset */ + Mips_BC2EQZ /* 942 */, MIPS_INS_BC2EQZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc2eqzc $rt, $offset */ + Mips_BC2EQZC_MMR6 /* 943 */, MIPS_INS_BC2EQZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc2nez $ct, $offset */ + Mips_BC2NEZ /* 944 */, MIPS_INS_BC2NEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc2nezc $rt, $offset */ + Mips_BC2NEZC_MMR6 /* 945 */, MIPS_INS_BC2NEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bclri.b $wd, $ws, $m */ + Mips_BCLRI_B /* 946 */, MIPS_INS_BCLRI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bclri.d $wd, $ws, $m */ + Mips_BCLRI_D /* 947 */, MIPS_INS_BCLRI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bclri.h $wd, $ws, $m */ + Mips_BCLRI_H /* 948 */, MIPS_INS_BCLRI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bclri.w $wd, $ws, $m */ + Mips_BCLRI_W /* 949 */, MIPS_INS_BCLRI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bclr.b $wd, $ws, $wt */ + Mips_BCLR_B /* 950 */, MIPS_INS_BCLR_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bclr.d $wd, $ws, $wt */ + Mips_BCLR_D /* 951 */, MIPS_INS_BCLR_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bclr.h $wd, $ws, $wt */ + Mips_BCLR_H /* 952 */, MIPS_INS_BCLR_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bclr.w $wd, $ws, $wt */ + Mips_BCLR_W /* 953 */, MIPS_INS_BCLR_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bc $offset */ + Mips_BC_MMR6 /* 954 */, MIPS_INS_BC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bc $addr */ + Mips_BC_NM /* 955 */, MIPS_INS_BC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beq $rs, $rt, $offset */ + Mips_BEQ /* 956 */, MIPS_INS_BEQ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beq $rs, $rt, $offset */ + Mips_BEQ64 /* 957 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* beqc $rs, $rt, $offset */ + Mips_BEQC /* 958 */, MIPS_INS_BEQC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqc $rs, $rt, $offset */ + Mips_BEQC16_NM /* 959 */, MIPS_INS_BEQC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqc $rs, $rt, $offset */ + Mips_BEQC64 /* 960 */, MIPS_INS_BEQC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqc $rs, $rt, $offset */ + Mips_BEQC_MMR6 /* 961 */, MIPS_INS_BEQC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqc $rs, $rt, $offset */ + Mips_BEQC_NM /* 962 */, MIPS_INS_BEQC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqc $rs, $rt, $offset */ + Mips_BEQCzero_NM /* 963 */, MIPS_INS_BEQC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqic $rt, $u, $offset */ + Mips_BEQIC_NM /* 964 */, MIPS_INS_BEQIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beql $rs, $rt, $offset */ + Mips_BEQL /* 965 */, MIPS_INS_BEQL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqz16 $rs, $offset */ + Mips_BEQZ16_MM /* 966 */, MIPS_INS_BEQZ16, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqzalc $rt, $offset */ + Mips_BEQZALC /* 967 */, MIPS_INS_BEQZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqzalc $rt, $offset */ + Mips_BEQZALC_MMR6 /* 968 */, MIPS_INS_BEQZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqzc $rs, $offset */ + Mips_BEQZC /* 969 */, MIPS_INS_BEQZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqzc16 $rs, $offset */ + Mips_BEQZC16_MMR6 /* 970 */, MIPS_INS_BEQZC16, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqzc $rs, $offset */ + Mips_BEQZC16_NM /* 971 */, MIPS_INS_BEQZC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqzc $rs, $offset */ + Mips_BEQZC64 /* 972 */, MIPS_INS_BEQZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqzc $rs, $offset */ + Mips_BEQZC_MM /* 973 */, MIPS_INS_BEQZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqzc $rs, $offset */ + Mips_BEQZC_MMR6 /* 974 */, MIPS_INS_BEQZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqzc $rs, $offset */ + Mips_BEQZC_NM /* 975 */, MIPS_INS_BEQZC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beq $rs, $rt, $offset */ + Mips_BEQ_MM /* 976 */, MIPS_INS_BEQ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgec $rs, $rt, $offset */ + Mips_BGEC /* 977 */, MIPS_INS_BGEC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgec $rs, $rt, $offset */ + Mips_BGEC64 /* 978 */, MIPS_INS_BGEC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgec $rs, $rt, $offset */ + Mips_BGEC_MMR6 /* 979 */, MIPS_INS_BGEC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgec $rs, $rt, $offset */ + Mips_BGEC_NM /* 980 */, MIPS_INS_BGEC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgeic $rt, $u, $offset */ + Mips_BGEIC_NM /* 981 */, MIPS_INS_BGEIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgeiuc $rt, $u, $offset */ + Mips_BGEIUC_NM /* 982 */, MIPS_INS_BGEIUC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgeuc $rs, $rt, $offset */ + Mips_BGEUC /* 983 */, MIPS_INS_BGEUC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgeuc $rs, $rt, $offset */ + Mips_BGEUC64 /* 984 */, MIPS_INS_BGEUC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgeuc $rs, $rt, $offset */ + Mips_BGEUC_MMR6 /* 985 */, MIPS_INS_BGEUC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgeuc $rs, $rt, $offset */ + Mips_BGEUC_NM /* 986 */, MIPS_INS_BGEUC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgez $rs, $offset */ + Mips_BGEZ /* 987 */, MIPS_INS_BGEZ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgez $rs, $offset */ + Mips_BGEZ64 /* 988 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* bgezal $rs, $offset */ + Mips_BGEZAL /* 989 */, MIPS_INS_BGEZAL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgezalc $rt, $offset */ + Mips_BGEZALC /* 990 */, MIPS_INS_BGEZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgezalc $rt, $offset */ + Mips_BGEZALC_MMR6 /* 991 */, MIPS_INS_BGEZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgezall $rs, $offset */ + Mips_BGEZALL /* 992 */, MIPS_INS_BGEZALL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgezals $rs, $offset */ + Mips_BGEZALS_MM /* 993 */, MIPS_INS_BGEZALS, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgezal $rs, $offset */ + Mips_BGEZAL_MM /* 994 */, MIPS_INS_BGEZAL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bgezc $rt, $offset */ + Mips_BGEZC /* 995 */, MIPS_INS_BGEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgezc $rt, $offset */ + Mips_BGEZC64 /* 996 */, MIPS_INS_BGEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgezc $rt, $offset */ + Mips_BGEZC_MMR6 /* 997 */, MIPS_INS_BGEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgezl $rs, $offset */ + Mips_BGEZL /* 998 */, MIPS_INS_BGEZL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgez $rs, $offset */ + Mips_BGEZ_MM /* 999 */, MIPS_INS_BGEZ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgtz $rs, $offset */ + Mips_BGTZ /* 1000 */, MIPS_INS_BGTZ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgtz $rs, $offset */ + Mips_BGTZ64 /* 1001 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* bgtzalc $rt, $offset */ + Mips_BGTZALC /* 1002 */, MIPS_INS_BGTZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgtzalc $rt, $offset */ + Mips_BGTZALC_MMR6 /* 1003 */, MIPS_INS_BGTZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgtzc $rt, $offset */ + Mips_BGTZC /* 1004 */, MIPS_INS_BGTZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgtzc $rt, $offset */ + Mips_BGTZC64 /* 1005 */, MIPS_INS_BGTZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgtzc $rt, $offset */ + Mips_BGTZC_MMR6 /* 1006 */, MIPS_INS_BGTZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgtzl $rs, $offset */ + Mips_BGTZL /* 1007 */, MIPS_INS_BGTZL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bgtz $rs, $offset */ + Mips_BGTZ_MM /* 1008 */, MIPS_INS_BGTZ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* binsli.b $wd, $ws, $m */ + Mips_BINSLI_B /* 1009 */, MIPS_INS_BINSLI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsli.d $wd, $ws, $m */ + Mips_BINSLI_D /* 1010 */, MIPS_INS_BINSLI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsli.h $wd, $ws, $m */ + Mips_BINSLI_H /* 1011 */, MIPS_INS_BINSLI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsli.w $wd, $ws, $m */ + Mips_BINSLI_W /* 1012 */, MIPS_INS_BINSLI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsl.b $wd, $ws, $wt */ + Mips_BINSL_B /* 1013 */, MIPS_INS_BINSL_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsl.d $wd, $ws, $wt */ + Mips_BINSL_D /* 1014 */, MIPS_INS_BINSL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsl.h $wd, $ws, $wt */ + Mips_BINSL_H /* 1015 */, MIPS_INS_BINSL_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsl.w $wd, $ws, $wt */ + Mips_BINSL_W /* 1016 */, MIPS_INS_BINSL_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsri.b $wd, $ws, $m */ + Mips_BINSRI_B /* 1017 */, MIPS_INS_BINSRI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsri.d $wd, $ws, $m */ + Mips_BINSRI_D /* 1018 */, MIPS_INS_BINSRI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsri.h $wd, $ws, $m */ + Mips_BINSRI_H /* 1019 */, MIPS_INS_BINSRI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsri.w $wd, $ws, $m */ + Mips_BINSRI_W /* 1020 */, MIPS_INS_BINSRI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsr.b $wd, $ws, $wt */ + Mips_BINSR_B /* 1021 */, MIPS_INS_BINSR_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsr.d $wd, $ws, $wt */ + Mips_BINSR_D /* 1022 */, MIPS_INS_BINSR_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsr.h $wd, $ws, $wt */ + Mips_BINSR_H /* 1023 */, MIPS_INS_BINSR_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* binsr.w $wd, $ws, $wt */ + Mips_BINSR_W /* 1024 */, MIPS_INS_BINSR_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bitrev $rd, $rt */ + Mips_BITREV /* 1025 */, MIPS_INS_BITREV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bitrevw $rt, $rs */ + Mips_BITREVW_NM /* 1026 */, MIPS_INS_BITREVW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bitrev $rt, $rs */ + Mips_BITREV_MM /* 1027 */, MIPS_INS_BITREV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bitswap $rd, $rt */ + Mips_BITSWAP /* 1028 */, MIPS_INS_BITSWAP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bitswap $rd, $rt */ + Mips_BITSWAP_MMR6 /* 1029 */, MIPS_INS_BITSWAP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* blez $rs, $offset */ + Mips_BLEZ /* 1030 */, MIPS_INS_BLEZ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* blez $rs, $offset */ + Mips_BLEZ64 /* 1031 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* blezalc $rt, $offset */ + Mips_BLEZALC /* 1032 */, MIPS_INS_BLEZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* blezalc $rt, $offset */ + Mips_BLEZALC_MMR6 /* 1033 */, MIPS_INS_BLEZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* blezc $rt, $offset */ + Mips_BLEZC /* 1034 */, MIPS_INS_BLEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* blezc $rt, $offset */ + Mips_BLEZC64 /* 1035 */, MIPS_INS_BLEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* blezc $rt, $offset */ + Mips_BLEZC_MMR6 /* 1036 */, MIPS_INS_BLEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* blezl $rs, $offset */ + Mips_BLEZL /* 1037 */, MIPS_INS_BLEZL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* blez $rs, $offset */ + Mips_BLEZ_MM /* 1038 */, MIPS_INS_BLEZ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltc $rs, $rt, $offset */ + Mips_BLTC /* 1039 */, MIPS_INS_BLTC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltc $rs, $rt, $offset */ + Mips_BLTC64 /* 1040 */, MIPS_INS_BLTC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltc $rs, $rt, $offset */ + Mips_BLTC_MMR6 /* 1041 */, MIPS_INS_BLTC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltc $rs, $rt, $offset */ + Mips_BLTC_NM /* 1042 */, MIPS_INS_BLTC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltic $rt, $u, $offset */ + Mips_BLTIC_NM /* 1043 */, MIPS_INS_BLTIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltiuc $rt, $u, $offset */ + Mips_BLTIUC_NM /* 1044 */, MIPS_INS_BLTIUC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltuc $rs, $rt, $offset */ + Mips_BLTUC /* 1045 */, MIPS_INS_BLTUC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltuc $rs, $rt, $offset */ + Mips_BLTUC64 /* 1046 */, MIPS_INS_BLTUC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltuc $rs, $rt, $offset */ + Mips_BLTUC_MMR6 /* 1047 */, MIPS_INS_BLTUC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltuc $rs, $rt, $offset */ + Mips_BLTUC_NM /* 1048 */, MIPS_INS_BLTUC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltz $rs, $offset */ + Mips_BLTZ /* 1049 */, MIPS_INS_BLTZ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltz $rs, $offset */ + Mips_BLTZ64 /* 1050 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* bltzal $rs, $offset */ + Mips_BLTZAL /* 1051 */, MIPS_INS_BLTZAL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltzalc $rt, $offset */ + Mips_BLTZALC /* 1052 */, MIPS_INS_BLTZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltzalc $rt, $offset */ + Mips_BLTZALC_MMR6 /* 1053 */, MIPS_INS_BLTZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltzall $rs, $offset */ + Mips_BLTZALL /* 1054 */, MIPS_INS_BLTZALL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltzals $rs, $offset */ + Mips_BLTZALS_MM /* 1055 */, MIPS_INS_BLTZALS, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltzal $rs, $offset */ + Mips_BLTZAL_MM /* 1056 */, MIPS_INS_BLTZAL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bltzc $rt, $offset */ + Mips_BLTZC /* 1057 */, MIPS_INS_BLTZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltzc $rt, $offset */ + Mips_BLTZC64 /* 1058 */, MIPS_INS_BLTZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltzc $rt, $offset */ + Mips_BLTZC_MMR6 /* 1059 */, MIPS_INS_BLTZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltzl $rs, $offset */ + Mips_BLTZL /* 1060 */, MIPS_INS_BLTZL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bltz $rs, $offset */ + Mips_BLTZ_MM /* 1061 */, MIPS_INS_BLTZ, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bmnzi.b $wd, $ws, $u8 */ + Mips_BMNZI_B /* 1062 */, MIPS_INS_BMNZI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bmnz.v $wd, $ws, $wt */ + Mips_BMNZ_V /* 1063 */, MIPS_INS_BMNZ_V, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bmzi.b $wd, $ws, $u8 */ + Mips_BMZI_B /* 1064 */, MIPS_INS_BMZI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bmz.v $wd, $ws, $wt */ + Mips_BMZ_V /* 1065 */, MIPS_INS_BMZ_V, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bne $rs, $rt, $offset */ + Mips_BNE /* 1066 */, MIPS_INS_BNE, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bne $rs, $rt, $offset */ + Mips_BNE64 /* 1067 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* bnec $rs, $rt, $offset */ + Mips_BNEC /* 1068 */, MIPS_INS_BNEC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnec $rs, $rt, $offset */ + Mips_BNEC16_NM /* 1069 */, MIPS_INS_BNEC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnec $rs, $rt, $offset */ + Mips_BNEC64 /* 1070 */, MIPS_INS_BNEC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnec $rs, $rt, $offset */ + Mips_BNEC_MMR6 /* 1071 */, MIPS_INS_BNEC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnec $rs, $rt, $offset */ + Mips_BNEC_NM /* 1072 */, MIPS_INS_BNEC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnec $rs, $rt, $offset */ + Mips_BNECzero_NM /* 1073 */, MIPS_INS_BNEC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnegi.b $wd, $ws, $m */ + Mips_BNEGI_B /* 1074 */, MIPS_INS_BNEGI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bnegi.d $wd, $ws, $m */ + Mips_BNEGI_D /* 1075 */, MIPS_INS_BNEGI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bnegi.h $wd, $ws, $m */ + Mips_BNEGI_H /* 1076 */, MIPS_INS_BNEGI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bnegi.w $wd, $ws, $m */ + Mips_BNEGI_W /* 1077 */, MIPS_INS_BNEGI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bneg.b $wd, $ws, $wt */ + Mips_BNEG_B /* 1078 */, MIPS_INS_BNEG_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bneg.d $wd, $ws, $wt */ + Mips_BNEG_D /* 1079 */, MIPS_INS_BNEG_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bneg.h $wd, $ws, $wt */ + Mips_BNEG_H /* 1080 */, MIPS_INS_BNEG_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bneg.w $wd, $ws, $wt */ + Mips_BNEG_W /* 1081 */, MIPS_INS_BNEG_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bneic $rt, $u, $offset */ + Mips_BNEIC_NM /* 1082 */, MIPS_INS_BNEIC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnel $rs, $rt, $offset */ + Mips_BNEL /* 1083 */, MIPS_INS_BNEL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnez16 $rs, $offset */ + Mips_BNEZ16_MM /* 1084 */, MIPS_INS_BNEZ16, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnezalc $rt, $offset */ + Mips_BNEZALC /* 1085 */, MIPS_INS_BNEZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnezalc $rt, $offset */ + Mips_BNEZALC_MMR6 /* 1086 */, MIPS_INS_BNEZALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnezc $rs, $offset */ + Mips_BNEZC /* 1087 */, MIPS_INS_BNEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnezc16 $rs, $offset */ + Mips_BNEZC16_MMR6 /* 1088 */, MIPS_INS_BNEZC16, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnezc $rs, $offset */ + Mips_BNEZC16_NM /* 1089 */, MIPS_INS_BNEZC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnezc $rs, $offset */ + Mips_BNEZC64 /* 1090 */, MIPS_INS_BNEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnezc $rs, $offset */ + Mips_BNEZC_MM /* 1091 */, MIPS_INS_BNEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnezc $rs, $offset */ + Mips_BNEZC_MMR6 /* 1092 */, MIPS_INS_BNEZC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnezc $rs, $offset */ + Mips_BNEZC_NM /* 1093 */, MIPS_INS_BNEZC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bne $rs, $rt, $offset */ + Mips_BNE_MM /* 1094 */, MIPS_INS_BNE, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnvc $rs, $rt, $offset */ + Mips_BNVC /* 1095 */, MIPS_INS_BNVC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnvc $rt, $rs, $offset */ + Mips_BNVC_MMR6 /* 1096 */, MIPS_INS_BNVC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnz.b $wt, $offset */ + Mips_BNZ_B /* 1097 */, MIPS_INS_BNZ_B, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnz.d $wt, $offset */ + Mips_BNZ_D /* 1098 */, MIPS_INS_BNZ_D, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnz.h $wt, $offset */ + Mips_BNZ_H /* 1099 */, MIPS_INS_BNZ_H, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnz.v $wt, $offset */ + Mips_BNZ_V /* 1100 */, MIPS_INS_BNZ_V, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnz.w $wt, $offset */ + Mips_BNZ_W /* 1101 */, MIPS_INS_BNZ_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bovc $rs, $rt, $offset */ + Mips_BOVC /* 1102 */, MIPS_INS_BOVC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bovc $rt, $rs, $offset */ + Mips_BOVC_MMR6 /* 1103 */, MIPS_INS_BOVC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bposge32 $offset */ + Mips_BPOSGE32 /* 1104 */, MIPS_INS_BPOSGE32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASDSP, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bposge32c $offset */ + Mips_BPOSGE32C_MMR3 /* 1105 */, MIPS_INS_BPOSGE32C, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR3, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bposge32 $offset */ + Mips_BPOSGE32_MM /* 1106 */, MIPS_INS_BPOSGE32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_HASDSP, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* break $code_1, $code_2 */ + Mips_BREAK /* 1107 */, MIPS_INS_BREAK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* break16 $code_ */ + Mips_BREAK16_MM /* 1108 */, MIPS_INS_BREAK16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* break16 $code_ */ + Mips_BREAK16_MMR6 /* 1109 */, MIPS_INS_BREAK16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* break $imm */ + Mips_BREAK16_NM /* 1110 */, MIPS_INS_BREAK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* break $code_1, $code_2 */ + Mips_BREAK_MM /* 1111 */, MIPS_INS_BREAK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* break $code_1, $code_2 */ + Mips_BREAK_MMR6 /* 1112 */, MIPS_INS_BREAK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* break $imm */ + Mips_BREAK_NM /* 1113 */, MIPS_INS_BREAK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* brsc $rs */ + Mips_BRSC_NM /* 1114 */, MIPS_INS_BRSC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bseli.b $wd, $ws, $u8 */ + Mips_BSELI_B /* 1115 */, MIPS_INS_BSELI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bsel.v $wd, $ws, $wt */ + Mips_BSEL_V /* 1116 */, MIPS_INS_BSEL_V, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bseti.b $wd, $ws, $m */ + Mips_BSETI_B /* 1117 */, MIPS_INS_BSETI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bseti.d $wd, $ws, $m */ + Mips_BSETI_D /* 1118 */, MIPS_INS_BSETI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bseti.h $wd, $ws, $m */ + Mips_BSETI_H /* 1119 */, MIPS_INS_BSETI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bseti.w $wd, $ws, $m */ + Mips_BSETI_W /* 1120 */, MIPS_INS_BSETI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bset.b $wd, $ws, $wt */ + Mips_BSET_B /* 1121 */, MIPS_INS_BSET_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bset.d $wd, $ws, $wt */ + Mips_BSET_D /* 1122 */, MIPS_INS_BSET_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bset.h $wd, $ws, $wt */ + Mips_BSET_H /* 1123 */, MIPS_INS_BSET_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bset.w $wd, $ws, $wt */ + Mips_BSET_W /* 1124 */, MIPS_INS_BSET_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* byterevw $rt, $rs */ + Mips_BYTEREVW_NM /* 1125 */, MIPS_INS_BYTEREVW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bz.b $wt, $offset */ + Mips_BZ_B /* 1126 */, MIPS_INS_BZ_B, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bz.d $wt, $offset */ + Mips_BZ_D /* 1127 */, MIPS_INS_BZ_D, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bz.h $wt, $offset */ + Mips_BZ_H /* 1128 */, MIPS_INS_BZ_H, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bz.v $wt, $offset */ + Mips_BZ_V /* 1129 */, MIPS_INS_BZ_V, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bz.w $wt, $offset */ + Mips_BZ_W /* 1130 */, MIPS_INS_BZ_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqz $rx, $imm8 # 16 bit inst */ + Mips_BeqzRxImm16 /* 1131 */, MIPS_INS_BEQZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* beqz $rx, $imm16 */ + Mips_BeqzRxImmX16 /* 1132 */, MIPS_INS_BEQZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* b $imm11 # 16 bit inst */ + Mips_Bimm16 /* 1133 */, MIPS_INS_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* b $imm16 */ + Mips_BimmX16 /* 1134 */, MIPS_INS_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnez $rx, $imm8 # 16 bit inst */ + Mips_BnezRxImm16 /* 1135 */, MIPS_INS_BNEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bnez $rx, $imm16 */ + Mips_BnezRxImmX16 /* 1136 */, MIPS_INS_BNEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* break 0 */ + Mips_Break16 /* 1137 */, MIPS_INS_BREAK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* bteqz $imm8 # 16 bit inst */ + Mips_Bteqz16 /* 1138 */, MIPS_INS_BTEQZ, + #ifndef CAPSTONE_DIET + { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* bteqz $imm16 */ + Mips_BteqzX16 /* 1139 */, MIPS_INS_BTEQZ, + #ifndef CAPSTONE_DIET + { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* btnez $imm8 # 16 bit inst */ + Mips_Btnez16 /* 1140 */, MIPS_INS_BTNEZ, + #ifndef CAPSTONE_DIET + { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* btnez $imm16 */ + Mips_BtnezX16 /* 1141 */, MIPS_INS_BTNEZ, + #ifndef CAPSTONE_DIET + { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* cache $hint, $addr */ + Mips_CACHE /* 1142 */, MIPS_INS_CACHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cachee $hint, $addr */ + Mips_CACHEE /* 1143 */, MIPS_INS_CACHEE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cachee $hint, $addr */ + Mips_CACHEE_MM /* 1144 */, MIPS_INS_CACHEE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cache $hint, $addr */ + Mips_CACHE_MM /* 1145 */, MIPS_INS_CACHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cache $hint, $addr */ + Mips_CACHE_MMR6 /* 1146 */, MIPS_INS_CACHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cache $op, $addr */ + Mips_CACHE_NM /* 1147 */, MIPS_INS_CACHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cache $hint, $addr */ + Mips_CACHE_R6 /* 1148 */, MIPS_INS_CACHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.l.d $fd, $fs */ + Mips_CEIL_L_D64 /* 1149 */, MIPS_INS_CEIL_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS3_32, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.l.d $ft, $fs */ + Mips_CEIL_L_D_MMR6 /* 1150 */, MIPS_INS_CEIL_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.l.s $fd, $fs */ + Mips_CEIL_L_S /* 1151 */, MIPS_INS_CEIL_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.l.s $ft, $fs */ + Mips_CEIL_L_S_MMR6 /* 1152 */, MIPS_INS_CEIL_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.w.d $fd, $fs */ + Mips_CEIL_W_D32 /* 1153 */, MIPS_INS_CEIL_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.w.d $fd, $fs */ + Mips_CEIL_W_D64 /* 1154 */, MIPS_INS_CEIL_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.w.d $ft, $fs */ + Mips_CEIL_W_D_MMR6 /* 1155 */, MIPS_INS_CEIL_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.w.d $fd, $fs */ + Mips_CEIL_W_MM /* 1156 */, MIPS_INS_CEIL_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.w.s $fd, $fs */ + Mips_CEIL_W_S /* 1157 */, MIPS_INS_CEIL_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.w.s $fd, $fs */ + Mips_CEIL_W_S_MM /* 1158 */, MIPS_INS_CEIL_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceil.w.s $ft, $fs */ + Mips_CEIL_W_S_MMR6 /* 1159 */, MIPS_INS_CEIL_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceqi.b $wd, $ws, $imm */ + Mips_CEQI_B /* 1160 */, MIPS_INS_CEQI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceqi.d $wd, $ws, $imm */ + Mips_CEQI_D /* 1161 */, MIPS_INS_CEQI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceqi.h $wd, $ws, $imm */ + Mips_CEQI_H /* 1162 */, MIPS_INS_CEQI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceqi.w $wd, $ws, $imm */ + Mips_CEQI_W /* 1163 */, MIPS_INS_CEQI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceq.b $wd, $ws, $wt */ + Mips_CEQ_B /* 1164 */, MIPS_INS_CEQ_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceq.d $wd, $ws, $wt */ + Mips_CEQ_D /* 1165 */, MIPS_INS_CEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceq.h $wd, $ws, $wt */ + Mips_CEQ_H /* 1166 */, MIPS_INS_CEQ_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ceq.w $wd, $ws, $wt */ + Mips_CEQ_W /* 1167 */, MIPS_INS_CEQ_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cfc1 $rt, $fs */ + Mips_CFC1 /* 1168 */, MIPS_INS_CFC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cfc1 $rt, $fs */ + Mips_CFC1_MM /* 1169 */, MIPS_INS_CFC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cfc2 $rt, $impl */ + Mips_CFC2_MM /* 1170 */, MIPS_INS_CFC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cfcmsa $rd, $cs */ + Mips_CFCMSA /* 1171 */, MIPS_INS_CFCMSA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cins $rt, $rs, $pos, $lenm1 */ + Mips_CINS /* 1172 */, MIPS_INS_CINS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMIPS64, MIPS_FEATURE_HASCNMIPS, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cins32 $rt, $rs, $pos, $lenm1 */ + Mips_CINS32 /* 1173 */, MIPS_INS_CINS32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMIPS64, MIPS_FEATURE_HASCNMIPS, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cins $rt, $rs, $pos, $lenm1 */ + Mips_CINS64_32 /* 1174 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cins $rt, $rs, $pos, $lenm1 */ + Mips_CINS_i32 /* 1175 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* class.d $fd, $fs */ + Mips_CLASS_D /* 1176 */, MIPS_INS_CLASS_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* class.d $fd, $fs */ + Mips_CLASS_D_MMR6 /* 1177 */, MIPS_INS_CLASS_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* class.s $fd, $fs */ + Mips_CLASS_S /* 1178 */, MIPS_INS_CLASS_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* class.s $fd, $fs */ + Mips_CLASS_S_MMR6 /* 1179 */, MIPS_INS_CLASS_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clei_s.b $wd, $ws, $imm */ + Mips_CLEI_S_B /* 1180 */, MIPS_INS_CLEI_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clei_s.d $wd, $ws, $imm */ + Mips_CLEI_S_D /* 1181 */, MIPS_INS_CLEI_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clei_s.h $wd, $ws, $imm */ + Mips_CLEI_S_H /* 1182 */, MIPS_INS_CLEI_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clei_s.w $wd, $ws, $imm */ + Mips_CLEI_S_W /* 1183 */, MIPS_INS_CLEI_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clei_u.b $wd, $ws, $imm */ + Mips_CLEI_U_B /* 1184 */, MIPS_INS_CLEI_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clei_u.d $wd, $ws, $imm */ + Mips_CLEI_U_D /* 1185 */, MIPS_INS_CLEI_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clei_u.h $wd, $ws, $imm */ + Mips_CLEI_U_H /* 1186 */, MIPS_INS_CLEI_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clei_u.w $wd, $ws, $imm */ + Mips_CLEI_U_W /* 1187 */, MIPS_INS_CLEI_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cle_s.b $wd, $ws, $wt */ + Mips_CLE_S_B /* 1188 */, MIPS_INS_CLE_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cle_s.d $wd, $ws, $wt */ + Mips_CLE_S_D /* 1189 */, MIPS_INS_CLE_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cle_s.h $wd, $ws, $wt */ + Mips_CLE_S_H /* 1190 */, MIPS_INS_CLE_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cle_s.w $wd, $ws, $wt */ + Mips_CLE_S_W /* 1191 */, MIPS_INS_CLE_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cle_u.b $wd, $ws, $wt */ + Mips_CLE_U_B /* 1192 */, MIPS_INS_CLE_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cle_u.d $wd, $ws, $wt */ + Mips_CLE_U_D /* 1193 */, MIPS_INS_CLE_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cle_u.h $wd, $ws, $wt */ + Mips_CLE_U_H /* 1194 */, MIPS_INS_CLE_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cle_u.w $wd, $ws, $wt */ + Mips_CLE_U_W /* 1195 */, MIPS_INS_CLE_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clo $rd, $rs */ + Mips_CLO /* 1196 */, MIPS_INS_CLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clo $rd, $rs */ + Mips_CLO_MM /* 1197 */, MIPS_INS_CLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clo $rt, $rs */ + Mips_CLO_MMR6 /* 1198 */, MIPS_INS_CLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clo $rt, $rs */ + Mips_CLO_NM /* 1199 */, MIPS_INS_CLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clo $rd, $rs */ + Mips_CLO_R6 /* 1200 */, MIPS_INS_CLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clti_s.b $wd, $ws, $imm */ + Mips_CLTI_S_B /* 1201 */, MIPS_INS_CLTI_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clti_s.d $wd, $ws, $imm */ + Mips_CLTI_S_D /* 1202 */, MIPS_INS_CLTI_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clti_s.h $wd, $ws, $imm */ + Mips_CLTI_S_H /* 1203 */, MIPS_INS_CLTI_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clti_s.w $wd, $ws, $imm */ + Mips_CLTI_S_W /* 1204 */, MIPS_INS_CLTI_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clti_u.b $wd, $ws, $imm */ + Mips_CLTI_U_B /* 1205 */, MIPS_INS_CLTI_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clti_u.d $wd, $ws, $imm */ + Mips_CLTI_U_D /* 1206 */, MIPS_INS_CLTI_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clti_u.h $wd, $ws, $imm */ + Mips_CLTI_U_H /* 1207 */, MIPS_INS_CLTI_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clti_u.w $wd, $ws, $imm */ + Mips_CLTI_U_W /* 1208 */, MIPS_INS_CLTI_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clt_s.b $wd, $ws, $wt */ + Mips_CLT_S_B /* 1209 */, MIPS_INS_CLT_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clt_s.d $wd, $ws, $wt */ + Mips_CLT_S_D /* 1210 */, MIPS_INS_CLT_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clt_s.h $wd, $ws, $wt */ + Mips_CLT_S_H /* 1211 */, MIPS_INS_CLT_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clt_s.w $wd, $ws, $wt */ + Mips_CLT_S_W /* 1212 */, MIPS_INS_CLT_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clt_u.b $wd, $ws, $wt */ + Mips_CLT_U_B /* 1213 */, MIPS_INS_CLT_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clt_u.d $wd, $ws, $wt */ + Mips_CLT_U_D /* 1214 */, MIPS_INS_CLT_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clt_u.h $wd, $ws, $wt */ + Mips_CLT_U_H /* 1215 */, MIPS_INS_CLT_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clt_u.w $wd, $ws, $wt */ + Mips_CLT_U_W /* 1216 */, MIPS_INS_CLT_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clz $rd, $rs */ + Mips_CLZ /* 1217 */, MIPS_INS_CLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clz $rd, $rs */ + Mips_CLZ_MM /* 1218 */, MIPS_INS_CLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clz $rt, $rs */ + Mips_CLZ_MMR6 /* 1219 */, MIPS_INS_CLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clz $rt, $rs */ + Mips_CLZ_NM /* 1220 */, MIPS_INS_CLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* clz $rd, $rs */ + Mips_CLZ_R6 /* 1221 */, MIPS_INS_CLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgdu.eq.qb $rd, $rs, $rt */ + Mips_CMPGDU_EQ_QB /* 1222 */, MIPS_INS_CMPGDU_EQ_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgdu.eq.qb $rd, $rs, $rt */ + Mips_CMPGDU_EQ_QB_MMR2 /* 1223 */, MIPS_INS_CMPGDU_EQ_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgdu.le.qb $rd, $rs, $rt */ + Mips_CMPGDU_LE_QB /* 1224 */, MIPS_INS_CMPGDU_LE_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgdu.le.qb $rd, $rs, $rt */ + Mips_CMPGDU_LE_QB_MMR2 /* 1225 */, MIPS_INS_CMPGDU_LE_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgdu.lt.qb $rd, $rs, $rt */ + Mips_CMPGDU_LT_QB /* 1226 */, MIPS_INS_CMPGDU_LT_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgdu.lt.qb $rd, $rs, $rt */ + Mips_CMPGDU_LT_QB_MMR2 /* 1227 */, MIPS_INS_CMPGDU_LT_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgu.eq.qb $rd, $rs, $rt */ + Mips_CMPGU_EQ_QB /* 1228 */, MIPS_INS_CMPGU_EQ_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgu.eq.qb $rd, $rs, $rt */ + Mips_CMPGU_EQ_QB_MM /* 1229 */, MIPS_INS_CMPGU_EQ_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgu.le.qb $rd, $rs, $rt */ + Mips_CMPGU_LE_QB /* 1230 */, MIPS_INS_CMPGU_LE_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgu.le.qb $rd, $rs, $rt */ + Mips_CMPGU_LE_QB_MM /* 1231 */, MIPS_INS_CMPGU_LE_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgu.lt.qb $rd, $rs, $rt */ + Mips_CMPGU_LT_QB /* 1232 */, MIPS_INS_CMPGU_LT_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpgu.lt.qb $rd, $rs, $rt */ + Mips_CMPGU_LT_QB_MM /* 1233 */, MIPS_INS_CMPGU_LT_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpu.eq.qb $rs, $rt */ + Mips_CMPU_EQ_QB /* 1234 */, MIPS_INS_CMPU_EQ_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpu.eq.qb $rs, $rt */ + Mips_CMPU_EQ_QB_MM /* 1235 */, MIPS_INS_CMPU_EQ_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpu.le.qb $rs, $rt */ + Mips_CMPU_LE_QB /* 1236 */, MIPS_INS_CMPU_LE_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpu.le.qb $rs, $rt */ + Mips_CMPU_LE_QB_MM /* 1237 */, MIPS_INS_CMPU_LE_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpu.lt.qb $rs, $rt */ + Mips_CMPU_LT_QB /* 1238 */, MIPS_INS_CMPU_LT_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpu.lt.qb $rs, $rt */ + Mips_CMPU_LT_QB_MM /* 1239 */, MIPS_INS_CMPU_LT_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.af.d $fd, $fs, $ft */ + Mips_CMP_AF_D_MMR6 /* 1240 */, MIPS_INS_CMP_AF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.af.s $fd, $fs, $ft */ + Mips_CMP_AF_S_MMR6 /* 1241 */, MIPS_INS_CMP_AF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.eq.d $fd, $fs, $ft */ + Mips_CMP_EQ_D /* 1242 */, MIPS_INS_CMP_EQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.eq.d $fd, $fs, $ft */ + Mips_CMP_EQ_D_MMR6 /* 1243 */, MIPS_INS_CMP_EQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.eq.ph $rs, $rt */ + Mips_CMP_EQ_PH /* 1244 */, MIPS_INS_CMP_EQ_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.eq.ph $rs, $rt */ + Mips_CMP_EQ_PH_MM /* 1245 */, MIPS_INS_CMP_EQ_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.eq.s $fd, $fs, $ft */ + Mips_CMP_EQ_S /* 1246 */, MIPS_INS_CMP_EQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.eq.s $fd, $fs, $ft */ + Mips_CMP_EQ_S_MMR6 /* 1247 */, MIPS_INS_CMP_EQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.af.d $fd, $fs, $ft */ + Mips_CMP_F_D /* 1248 */, MIPS_INS_CMP_AF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.af.s $fd, $fs, $ft */ + Mips_CMP_F_S /* 1249 */, MIPS_INS_CMP_AF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.le.d $fd, $fs, $ft */ + Mips_CMP_LE_D /* 1250 */, MIPS_INS_CMP_LE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.le.d $fd, $fs, $ft */ + Mips_CMP_LE_D_MMR6 /* 1251 */, MIPS_INS_CMP_LE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.le.ph $rs, $rt */ + Mips_CMP_LE_PH /* 1252 */, MIPS_INS_CMP_LE_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.le.ph $rs, $rt */ + Mips_CMP_LE_PH_MM /* 1253 */, MIPS_INS_CMP_LE_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.le.s $fd, $fs, $ft */ + Mips_CMP_LE_S /* 1254 */, MIPS_INS_CMP_LE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.le.s $fd, $fs, $ft */ + Mips_CMP_LE_S_MMR6 /* 1255 */, MIPS_INS_CMP_LE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.lt.d $fd, $fs, $ft */ + Mips_CMP_LT_D /* 1256 */, MIPS_INS_CMP_LT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.lt.d $fd, $fs, $ft */ + Mips_CMP_LT_D_MMR6 /* 1257 */, MIPS_INS_CMP_LT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.lt.ph $rs, $rt */ + Mips_CMP_LT_PH /* 1258 */, MIPS_INS_CMP_LT_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.lt.ph $rs, $rt */ + Mips_CMP_LT_PH_MM /* 1259 */, MIPS_INS_CMP_LT_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.lt.s $fd, $fs, $ft */ + Mips_CMP_LT_S /* 1260 */, MIPS_INS_CMP_LT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.lt.s $fd, $fs, $ft */ + Mips_CMP_LT_S_MMR6 /* 1261 */, MIPS_INS_CMP_LT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.saf.d $fd, $fs, $ft */ + Mips_CMP_SAF_D /* 1262 */, MIPS_INS_CMP_SAF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.saf.d $fd, $fs, $ft */ + Mips_CMP_SAF_D_MMR6 /* 1263 */, MIPS_INS_CMP_SAF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.saf.s $fd, $fs, $ft */ + Mips_CMP_SAF_S /* 1264 */, MIPS_INS_CMP_SAF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.saf.s $fd, $fs, $ft */ + Mips_CMP_SAF_S_MMR6 /* 1265 */, MIPS_INS_CMP_SAF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.seq.d $fd, $fs, $ft */ + Mips_CMP_SEQ_D /* 1266 */, MIPS_INS_CMP_SEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.seq.d $fd, $fs, $ft */ + Mips_CMP_SEQ_D_MMR6 /* 1267 */, MIPS_INS_CMP_SEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.seq.s $fd, $fs, $ft */ + Mips_CMP_SEQ_S /* 1268 */, MIPS_INS_CMP_SEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.seq.s $fd, $fs, $ft */ + Mips_CMP_SEQ_S_MMR6 /* 1269 */, MIPS_INS_CMP_SEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sle.d $fd, $fs, $ft */ + Mips_CMP_SLE_D /* 1270 */, MIPS_INS_CMP_SLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sle.d $fd, $fs, $ft */ + Mips_CMP_SLE_D_MMR6 /* 1271 */, MIPS_INS_CMP_SLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sle.s $fd, $fs, $ft */ + Mips_CMP_SLE_S /* 1272 */, MIPS_INS_CMP_SLE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sle.s $fd, $fs, $ft */ + Mips_CMP_SLE_S_MMR6 /* 1273 */, MIPS_INS_CMP_SLE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.slt.d $fd, $fs, $ft */ + Mips_CMP_SLT_D /* 1274 */, MIPS_INS_CMP_SLT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.slt.d $fd, $fs, $ft */ + Mips_CMP_SLT_D_MMR6 /* 1275 */, MIPS_INS_CMP_SLT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.slt.s $fd, $fs, $ft */ + Mips_CMP_SLT_S /* 1276 */, MIPS_INS_CMP_SLT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.slt.s $fd, $fs, $ft */ + Mips_CMP_SLT_S_MMR6 /* 1277 */, MIPS_INS_CMP_SLT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sueq.d $fd, $fs, $ft */ + Mips_CMP_SUEQ_D /* 1278 */, MIPS_INS_CMP_SUEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sueq.d $fd, $fs, $ft */ + Mips_CMP_SUEQ_D_MMR6 /* 1279 */, MIPS_INS_CMP_SUEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sueq.s $fd, $fs, $ft */ + Mips_CMP_SUEQ_S /* 1280 */, MIPS_INS_CMP_SUEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sueq.s $fd, $fs, $ft */ + Mips_CMP_SUEQ_S_MMR6 /* 1281 */, MIPS_INS_CMP_SUEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sule.d $fd, $fs, $ft */ + Mips_CMP_SULE_D /* 1282 */, MIPS_INS_CMP_SULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sule.d $fd, $fs, $ft */ + Mips_CMP_SULE_D_MMR6 /* 1283 */, MIPS_INS_CMP_SULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sule.s $fd, $fs, $ft */ + Mips_CMP_SULE_S /* 1284 */, MIPS_INS_CMP_SULE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sule.s $fd, $fs, $ft */ + Mips_CMP_SULE_S_MMR6 /* 1285 */, MIPS_INS_CMP_SULE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sult.d $fd, $fs, $ft */ + Mips_CMP_SULT_D /* 1286 */, MIPS_INS_CMP_SULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sult.d $fd, $fs, $ft */ + Mips_CMP_SULT_D_MMR6 /* 1287 */, MIPS_INS_CMP_SULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sult.s $fd, $fs, $ft */ + Mips_CMP_SULT_S /* 1288 */, MIPS_INS_CMP_SULT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sult.s $fd, $fs, $ft */ + Mips_CMP_SULT_S_MMR6 /* 1289 */, MIPS_INS_CMP_SULT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sun.d $fd, $fs, $ft */ + Mips_CMP_SUN_D /* 1290 */, MIPS_INS_CMP_SUN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sun.d $fd, $fs, $ft */ + Mips_CMP_SUN_D_MMR6 /* 1291 */, MIPS_INS_CMP_SUN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sun.s $fd, $fs, $ft */ + Mips_CMP_SUN_S /* 1292 */, MIPS_INS_CMP_SUN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.sun.s $fd, $fs, $ft */ + Mips_CMP_SUN_S_MMR6 /* 1293 */, MIPS_INS_CMP_SUN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ueq.d $fd, $fs, $ft */ + Mips_CMP_UEQ_D /* 1294 */, MIPS_INS_CMP_UEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ueq.d $fd, $fs, $ft */ + Mips_CMP_UEQ_D_MMR6 /* 1295 */, MIPS_INS_CMP_UEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ueq.s $fd, $fs, $ft */ + Mips_CMP_UEQ_S /* 1296 */, MIPS_INS_CMP_UEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ueq.s $fd, $fs, $ft */ + Mips_CMP_UEQ_S_MMR6 /* 1297 */, MIPS_INS_CMP_UEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ule.d $fd, $fs, $ft */ + Mips_CMP_ULE_D /* 1298 */, MIPS_INS_CMP_ULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ule.d $fd, $fs, $ft */ + Mips_CMP_ULE_D_MMR6 /* 1299 */, MIPS_INS_CMP_ULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ule.s $fd, $fs, $ft */ + Mips_CMP_ULE_S /* 1300 */, MIPS_INS_CMP_ULE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ule.s $fd, $fs, $ft */ + Mips_CMP_ULE_S_MMR6 /* 1301 */, MIPS_INS_CMP_ULE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ult.d $fd, $fs, $ft */ + Mips_CMP_ULT_D /* 1302 */, MIPS_INS_CMP_ULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ult.d $fd, $fs, $ft */ + Mips_CMP_ULT_D_MMR6 /* 1303 */, MIPS_INS_CMP_ULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ult.s $fd, $fs, $ft */ + Mips_CMP_ULT_S /* 1304 */, MIPS_INS_CMP_ULT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.ult.s $fd, $fs, $ft */ + Mips_CMP_ULT_S_MMR6 /* 1305 */, MIPS_INS_CMP_ULT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.un.d $fd, $fs, $ft */ + Mips_CMP_UN_D /* 1306 */, MIPS_INS_CMP_UN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.un.d $fd, $fs, $ft */ + Mips_CMP_UN_D_MMR6 /* 1307 */, MIPS_INS_CMP_UN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.un.s $fd, $fs, $ft */ + Mips_CMP_UN_S /* 1308 */, MIPS_INS_CMP_UN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp.un.s $fd, $fs, $ft */ + Mips_CMP_UN_S_MMR6 /* 1309 */, MIPS_INS_CMP_UN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* copy_s.b $rd, $ws[$n] */ + Mips_COPY_S_B /* 1310 */, MIPS_INS_COPY_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* copy_s.d $rd, $ws[$n] */ + Mips_COPY_S_D /* 1311 */, MIPS_INS_COPY_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, MIPS_FEATURE_HASMIPS64, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* copy_s.h $rd, $ws[$n] */ + Mips_COPY_S_H /* 1312 */, MIPS_INS_COPY_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* copy_s.w $rd, $ws[$n] */ + Mips_COPY_S_W /* 1313 */, MIPS_INS_COPY_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* copy_u.b $rd, $ws[$n] */ + Mips_COPY_U_B /* 1314 */, MIPS_INS_COPY_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* copy_u.h $rd, $ws[$n] */ + Mips_COPY_U_H /* 1315 */, MIPS_INS_COPY_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* copy_u.w $rd, $ws[$n] */ + Mips_COPY_U_W /* 1316 */, MIPS_INS_COPY_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, MIPS_FEATURE_HASMIPS64, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32b $rd, $rs, $rt */ + Mips_CRC32B /* 1317 */, MIPS_INS_CRC32B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASCRC, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32b $rt, $rs */ + Mips_CRC32B_NM /* 1318 */, MIPS_INS_CRC32B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASCRC, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32cb $rd, $rs, $rt */ + Mips_CRC32CB /* 1319 */, MIPS_INS_CRC32CB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASCRC, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32cb $rt, $rs */ + Mips_CRC32CB_NM /* 1320 */, MIPS_INS_CRC32CB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASCRC, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32cd $rd, $rs, $rt */ + Mips_CRC32CD /* 1321 */, MIPS_INS_CRC32CD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_HASCRC, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32ch $rd, $rs, $rt */ + Mips_CRC32CH /* 1322 */, MIPS_INS_CRC32CH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASCRC, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32ch $rt, $rs */ + Mips_CRC32CH_NM /* 1323 */, MIPS_INS_CRC32CH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASCRC, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32cw $rd, $rs, $rt */ + Mips_CRC32CW /* 1324 */, MIPS_INS_CRC32CW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASCRC, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32cw $rt, $rs */ + Mips_CRC32CW_NM /* 1325 */, MIPS_INS_CRC32CW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASCRC, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32d $rd, $rs, $rt */ + Mips_CRC32D /* 1326 */, MIPS_INS_CRC32D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_HASCRC, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32h $rd, $rs, $rt */ + Mips_CRC32H /* 1327 */, MIPS_INS_CRC32H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASCRC, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32h $rt, $rs */ + Mips_CRC32H_NM /* 1328 */, MIPS_INS_CRC32H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASCRC, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32w $rd, $rs, $rt */ + Mips_CRC32W /* 1329 */, MIPS_INS_CRC32W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASCRC, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* crc32w $rt, $rs */ + Mips_CRC32W_NM /* 1330 */, MIPS_INS_CRC32W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASCRC, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ctc1 $rt, $fs */ + Mips_CTC1 /* 1331 */, MIPS_INS_CTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ctc1 $rt, $fs */ + Mips_CTC1_MM /* 1332 */, MIPS_INS_CTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ctc2 $rt, $impl */ + Mips_CTC2_MM /* 1333 */, MIPS_INS_CTC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ctcmsa $cd, $rs */ + Mips_CTCMSA /* 1334 */, MIPS_INS_CTCMSA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.s $fd, $fs */ + Mips_CVT_D32_S /* 1335 */, MIPS_INS_CVT_D_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.s $fd, $fs */ + Mips_CVT_D32_S_MM /* 1336 */, MIPS_INS_CVT_D_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.w $fd, $fs */ + Mips_CVT_D32_W /* 1337 */, MIPS_INS_CVT_D_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.w $fd, $fs */ + Mips_CVT_D32_W_MM /* 1338 */, MIPS_INS_CVT_D_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.l $fd, $fs */ + Mips_CVT_D64_L /* 1339 */, MIPS_INS_CVT_D_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS3_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.s $fd, $fs */ + Mips_CVT_D64_S /* 1340 */, MIPS_INS_CVT_D_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.s $fd, $fs */ + Mips_CVT_D64_S_MM /* 1341 */, MIPS_INS_CVT_D_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.w $fd, $fs */ + Mips_CVT_D64_W /* 1342 */, MIPS_INS_CVT_D_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.w $fd, $fs */ + Mips_CVT_D64_W_MM /* 1343 */, MIPS_INS_CVT_D_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.d.l $ft, $fs */ + Mips_CVT_D_L_MMR6 /* 1344 */, MIPS_INS_CVT_D_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.l.d $fd, $fs */ + Mips_CVT_L_D64 /* 1345 */, MIPS_INS_CVT_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.l.d $fd, $fs */ + Mips_CVT_L_D64_MM /* 1346 */, MIPS_INS_CVT_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.l.d $ft, $fs */ + Mips_CVT_L_D_MMR6 /* 1347 */, MIPS_INS_CVT_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.l.s $fd, $fs */ + Mips_CVT_L_S /* 1348 */, MIPS_INS_CVT_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.l.s $fd, $fs */ + Mips_CVT_L_S_MM /* 1349 */, MIPS_INS_CVT_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.l.s $ft, $fs */ + Mips_CVT_L_S_MMR6 /* 1350 */, MIPS_INS_CVT_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.ps.pw $fd, $fs */ + Mips_CVT_PS_PW64 /* 1351 */, MIPS_INS_CVT_PS_PW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMIPS3D, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.ps.s $fd, $fs, $ft */ + Mips_CVT_PS_S64 /* 1352 */, MIPS_INS_CVT_PS_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.pw.ps $fd, $fs */ + Mips_CVT_PW_PS64 /* 1353 */, MIPS_INS_CVT_PW_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMIPS3D, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.d $fd, $fs */ + Mips_CVT_S_D32 /* 1354 */, MIPS_INS_CVT_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.d $fd, $fs */ + Mips_CVT_S_D32_MM /* 1355 */, MIPS_INS_CVT_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.d $fd, $fs */ + Mips_CVT_S_D64 /* 1356 */, MIPS_INS_CVT_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.d $fd, $fs */ + Mips_CVT_S_D64_MM /* 1357 */, MIPS_INS_CVT_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.l $fd, $fs */ + Mips_CVT_S_L /* 1358 */, MIPS_INS_CVT_S_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS3_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.l $ft, $fs */ + Mips_CVT_S_L_MMR6 /* 1359 */, MIPS_INS_CVT_S_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.pl $fd, $fs */ + Mips_CVT_S_PL64 /* 1360 */, MIPS_INS_CVT_S_PL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.pu $fd, $fs */ + Mips_CVT_S_PU64 /* 1361 */, MIPS_INS_CVT_S_PU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.w $fd, $fs */ + Mips_CVT_S_W /* 1362 */, MIPS_INS_CVT_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.w $fd, $fs */ + Mips_CVT_S_W_MM /* 1363 */, MIPS_INS_CVT_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.s.w $ft, $fs */ + Mips_CVT_S_W_MMR6 /* 1364 */, MIPS_INS_CVT_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.w.d $fd, $fs */ + Mips_CVT_W_D32 /* 1365 */, MIPS_INS_CVT_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.w.d $fd, $fs */ + Mips_CVT_W_D32_MM /* 1366 */, MIPS_INS_CVT_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.w.d $fd, $fs */ + Mips_CVT_W_D64 /* 1367 */, MIPS_INS_CVT_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.w.d $fd, $fs */ + Mips_CVT_W_D64_MM /* 1368 */, MIPS_INS_CVT_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.w.s $fd, $fs */ + Mips_CVT_W_S /* 1369 */, MIPS_INS_CVT_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.w.s $fd, $fs */ + Mips_CVT_W_S_MM /* 1370 */, MIPS_INS_CVT_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cvt.w.s $ft, $fs */ + Mips_CVT_W_S_MMR6 /* 1371 */, MIPS_INS_CVT_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.eq.d $fcc, $fs, $ft */ + Mips_C_EQ_D32 /* 1372 */, MIPS_INS_C_EQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.eq.d $fcc, $fs, $ft */ + Mips_C_EQ_D32_MM /* 1373 */, MIPS_INS_C_EQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.eq.d $fcc, $fs, $ft */ + Mips_C_EQ_D64 /* 1374 */, MIPS_INS_C_EQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.eq.d $fcc, $fs, $ft */ + Mips_C_EQ_D64_MM /* 1375 */, MIPS_INS_C_EQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.eq.s $fcc, $fs, $ft */ + Mips_C_EQ_S /* 1376 */, MIPS_INS_C_EQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.eq.s $fcc, $fs, $ft */ + Mips_C_EQ_S_MM /* 1377 */, MIPS_INS_C_EQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.f.d $fcc, $fs, $ft */ + Mips_C_F_D32 /* 1378 */, MIPS_INS_C_F_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.f.d $fcc, $fs, $ft */ + Mips_C_F_D32_MM /* 1379 */, MIPS_INS_C_F_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.f.d $fcc, $fs, $ft */ + Mips_C_F_D64 /* 1380 */, MIPS_INS_C_F_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.f.d $fcc, $fs, $ft */ + Mips_C_F_D64_MM /* 1381 */, MIPS_INS_C_F_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.f.s $fcc, $fs, $ft */ + Mips_C_F_S /* 1382 */, MIPS_INS_C_F_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.f.s $fcc, $fs, $ft */ + Mips_C_F_S_MM /* 1383 */, MIPS_INS_C_F_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.le.d $fcc, $fs, $ft */ + Mips_C_LE_D32 /* 1384 */, MIPS_INS_C_LE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.le.d $fcc, $fs, $ft */ + Mips_C_LE_D32_MM /* 1385 */, MIPS_INS_C_LE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.le.d $fcc, $fs, $ft */ + Mips_C_LE_D64 /* 1386 */, MIPS_INS_C_LE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.le.d $fcc, $fs, $ft */ + Mips_C_LE_D64_MM /* 1387 */, MIPS_INS_C_LE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.le.s $fcc, $fs, $ft */ + Mips_C_LE_S /* 1388 */, MIPS_INS_C_LE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.le.s $fcc, $fs, $ft */ + Mips_C_LE_S_MM /* 1389 */, MIPS_INS_C_LE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.lt.d $fcc, $fs, $ft */ + Mips_C_LT_D32 /* 1390 */, MIPS_INS_C_LT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.lt.d $fcc, $fs, $ft */ + Mips_C_LT_D32_MM /* 1391 */, MIPS_INS_C_LT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.lt.d $fcc, $fs, $ft */ + Mips_C_LT_D64 /* 1392 */, MIPS_INS_C_LT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.lt.d $fcc, $fs, $ft */ + Mips_C_LT_D64_MM /* 1393 */, MIPS_INS_C_LT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.lt.s $fcc, $fs, $ft */ + Mips_C_LT_S /* 1394 */, MIPS_INS_C_LT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.lt.s $fcc, $fs, $ft */ + Mips_C_LT_S_MM /* 1395 */, MIPS_INS_C_LT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.nge.d $fcc, $fs, $ft */ + Mips_C_NGE_D32 /* 1396 */, MIPS_INS_C_NGE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.nge.d $fcc, $fs, $ft */ + Mips_C_NGE_D32_MM /* 1397 */, MIPS_INS_C_NGE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.nge.d $fcc, $fs, $ft */ + Mips_C_NGE_D64 /* 1398 */, MIPS_INS_C_NGE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.nge.d $fcc, $fs, $ft */ + Mips_C_NGE_D64_MM /* 1399 */, MIPS_INS_C_NGE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.nge.s $fcc, $fs, $ft */ + Mips_C_NGE_S /* 1400 */, MIPS_INS_C_NGE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.nge.s $fcc, $fs, $ft */ + Mips_C_NGE_S_MM /* 1401 */, MIPS_INS_C_NGE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngle.d $fcc, $fs, $ft */ + Mips_C_NGLE_D32 /* 1402 */, MIPS_INS_C_NGLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngle.d $fcc, $fs, $ft */ + Mips_C_NGLE_D32_MM /* 1403 */, MIPS_INS_C_NGLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngle.d $fcc, $fs, $ft */ + Mips_C_NGLE_D64 /* 1404 */, MIPS_INS_C_NGLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngle.d $fcc, $fs, $ft */ + Mips_C_NGLE_D64_MM /* 1405 */, MIPS_INS_C_NGLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngle.s $fcc, $fs, $ft */ + Mips_C_NGLE_S /* 1406 */, MIPS_INS_C_NGLE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngle.s $fcc, $fs, $ft */ + Mips_C_NGLE_S_MM /* 1407 */, MIPS_INS_C_NGLE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngl.d $fcc, $fs, $ft */ + Mips_C_NGL_D32 /* 1408 */, MIPS_INS_C_NGL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngl.d $fcc, $fs, $ft */ + Mips_C_NGL_D32_MM /* 1409 */, MIPS_INS_C_NGL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngl.d $fcc, $fs, $ft */ + Mips_C_NGL_D64 /* 1410 */, MIPS_INS_C_NGL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngl.d $fcc, $fs, $ft */ + Mips_C_NGL_D64_MM /* 1411 */, MIPS_INS_C_NGL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngl.s $fcc, $fs, $ft */ + Mips_C_NGL_S /* 1412 */, MIPS_INS_C_NGL_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngl.s $fcc, $fs, $ft */ + Mips_C_NGL_S_MM /* 1413 */, MIPS_INS_C_NGL_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngt.d $fcc, $fs, $ft */ + Mips_C_NGT_D32 /* 1414 */, MIPS_INS_C_NGT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngt.d $fcc, $fs, $ft */ + Mips_C_NGT_D32_MM /* 1415 */, MIPS_INS_C_NGT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngt.d $fcc, $fs, $ft */ + Mips_C_NGT_D64 /* 1416 */, MIPS_INS_C_NGT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngt.d $fcc, $fs, $ft */ + Mips_C_NGT_D64_MM /* 1417 */, MIPS_INS_C_NGT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngt.s $fcc, $fs, $ft */ + Mips_C_NGT_S /* 1418 */, MIPS_INS_C_NGT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ngt.s $fcc, $fs, $ft */ + Mips_C_NGT_S_MM /* 1419 */, MIPS_INS_C_NGT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ole.d $fcc, $fs, $ft */ + Mips_C_OLE_D32 /* 1420 */, MIPS_INS_C_OLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ole.d $fcc, $fs, $ft */ + Mips_C_OLE_D32_MM /* 1421 */, MIPS_INS_C_OLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ole.d $fcc, $fs, $ft */ + Mips_C_OLE_D64 /* 1422 */, MIPS_INS_C_OLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ole.d $fcc, $fs, $ft */ + Mips_C_OLE_D64_MM /* 1423 */, MIPS_INS_C_OLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ole.s $fcc, $fs, $ft */ + Mips_C_OLE_S /* 1424 */, MIPS_INS_C_OLE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ole.s $fcc, $fs, $ft */ + Mips_C_OLE_S_MM /* 1425 */, MIPS_INS_C_OLE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.olt.d $fcc, $fs, $ft */ + Mips_C_OLT_D32 /* 1426 */, MIPS_INS_C_OLT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.olt.d $fcc, $fs, $ft */ + Mips_C_OLT_D32_MM /* 1427 */, MIPS_INS_C_OLT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.olt.d $fcc, $fs, $ft */ + Mips_C_OLT_D64 /* 1428 */, MIPS_INS_C_OLT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.olt.d $fcc, $fs, $ft */ + Mips_C_OLT_D64_MM /* 1429 */, MIPS_INS_C_OLT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.olt.s $fcc, $fs, $ft */ + Mips_C_OLT_S /* 1430 */, MIPS_INS_C_OLT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.olt.s $fcc, $fs, $ft */ + Mips_C_OLT_S_MM /* 1431 */, MIPS_INS_C_OLT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.seq.d $fcc, $fs, $ft */ + Mips_C_SEQ_D32 /* 1432 */, MIPS_INS_C_SEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.seq.d $fcc, $fs, $ft */ + Mips_C_SEQ_D32_MM /* 1433 */, MIPS_INS_C_SEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.seq.d $fcc, $fs, $ft */ + Mips_C_SEQ_D64 /* 1434 */, MIPS_INS_C_SEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.seq.d $fcc, $fs, $ft */ + Mips_C_SEQ_D64_MM /* 1435 */, MIPS_INS_C_SEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.seq.s $fcc, $fs, $ft */ + Mips_C_SEQ_S /* 1436 */, MIPS_INS_C_SEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.seq.s $fcc, $fs, $ft */ + Mips_C_SEQ_S_MM /* 1437 */, MIPS_INS_C_SEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.sf.d $fcc, $fs, $ft */ + Mips_C_SF_D32 /* 1438 */, MIPS_INS_C_SF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.sf.d $fcc, $fs, $ft */ + Mips_C_SF_D32_MM /* 1439 */, MIPS_INS_C_SF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.sf.d $fcc, $fs, $ft */ + Mips_C_SF_D64 /* 1440 */, MIPS_INS_C_SF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.sf.d $fcc, $fs, $ft */ + Mips_C_SF_D64_MM /* 1441 */, MIPS_INS_C_SF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.sf.s $fcc, $fs, $ft */ + Mips_C_SF_S /* 1442 */, MIPS_INS_C_SF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.sf.s $fcc, $fs, $ft */ + Mips_C_SF_S_MM /* 1443 */, MIPS_INS_C_SF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ueq.d $fcc, $fs, $ft */ + Mips_C_UEQ_D32 /* 1444 */, MIPS_INS_C_UEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ueq.d $fcc, $fs, $ft */ + Mips_C_UEQ_D32_MM /* 1445 */, MIPS_INS_C_UEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ueq.d $fcc, $fs, $ft */ + Mips_C_UEQ_D64 /* 1446 */, MIPS_INS_C_UEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ueq.d $fcc, $fs, $ft */ + Mips_C_UEQ_D64_MM /* 1447 */, MIPS_INS_C_UEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ueq.s $fcc, $fs, $ft */ + Mips_C_UEQ_S /* 1448 */, MIPS_INS_C_UEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ueq.s $fcc, $fs, $ft */ + Mips_C_UEQ_S_MM /* 1449 */, MIPS_INS_C_UEQ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ule.d $fcc, $fs, $ft */ + Mips_C_ULE_D32 /* 1450 */, MIPS_INS_C_ULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ule.d $fcc, $fs, $ft */ + Mips_C_ULE_D32_MM /* 1451 */, MIPS_INS_C_ULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ule.d $fcc, $fs, $ft */ + Mips_C_ULE_D64 /* 1452 */, MIPS_INS_C_ULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ule.d $fcc, $fs, $ft */ + Mips_C_ULE_D64_MM /* 1453 */, MIPS_INS_C_ULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ule.s $fcc, $fs, $ft */ + Mips_C_ULE_S /* 1454 */, MIPS_INS_C_ULE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ule.s $fcc, $fs, $ft */ + Mips_C_ULE_S_MM /* 1455 */, MIPS_INS_C_ULE_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ult.d $fcc, $fs, $ft */ + Mips_C_ULT_D32 /* 1456 */, MIPS_INS_C_ULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ult.d $fcc, $fs, $ft */ + Mips_C_ULT_D32_MM /* 1457 */, MIPS_INS_C_ULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ult.d $fcc, $fs, $ft */ + Mips_C_ULT_D64 /* 1458 */, MIPS_INS_C_ULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ult.d $fcc, $fs, $ft */ + Mips_C_ULT_D64_MM /* 1459 */, MIPS_INS_C_ULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ult.s $fcc, $fs, $ft */ + Mips_C_ULT_S /* 1460 */, MIPS_INS_C_ULT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.ult.s $fcc, $fs, $ft */ + Mips_C_ULT_S_MM /* 1461 */, MIPS_INS_C_ULT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.un.d $fcc, $fs, $ft */ + Mips_C_UN_D32 /* 1462 */, MIPS_INS_C_UN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.un.d $fcc, $fs, $ft */ + Mips_C_UN_D32_MM /* 1463 */, MIPS_INS_C_UN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.un.d $fcc, $fs, $ft */ + Mips_C_UN_D64 /* 1464 */, MIPS_INS_C_UN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.un.d $fcc, $fs, $ft */ + Mips_C_UN_D64_MM /* 1465 */, MIPS_INS_C_UN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.un.s $fcc, $fs, $ft */ + Mips_C_UN_S /* 1466 */, MIPS_INS_C_UN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.un.s $fcc, $fs, $ft */ + Mips_C_UN_S_MM /* 1467 */, MIPS_INS_C_UN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmp $rx, $ry */ + Mips_CmpRxRy16 /* 1468 */, MIPS_INS_CMP, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpi $rx, $imm8 # 16 bit inst */ + Mips_CmpiRxImm16 /* 1469 */, MIPS_INS_CMPI, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* cmpi $rx, $imm16 */ + Mips_CmpiRxImmX16 /* 1470 */, MIPS_INS_CMPI, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dadd $rd, $rs, $rt */ + Mips_DADD /* 1471 */, MIPS_INS_DADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* daddi $rt, $rs, $imm16 */ + Mips_DADDi /* 1472 */, MIPS_INS_DADDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* daddiu $rt, $rs, $imm16 */ + Mips_DADDiu /* 1473 */, MIPS_INS_DADDIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* daddu $rd, $rs, $rt */ + Mips_DADDu /* 1474 */, MIPS_INS_DADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dahi $rs, $rt, $imm */ + Mips_DAHI /* 1475 */, MIPS_INS_DAHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dalign $rd, $rs, $rt, $bp */ + Mips_DALIGN /* 1476 */, MIPS_INS_DALIGN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dati $rs, $rt, $imm */ + Mips_DATI /* 1477 */, MIPS_INS_DATI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* daui $rt, $rs, $imm */ + Mips_DAUI /* 1478 */, MIPS_INS_DAUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dbitswap $rd, $rt */ + Mips_DBITSWAP /* 1479 */, MIPS_INS_DBITSWAP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dclo $rd, $rs */ + Mips_DCLO /* 1480 */, MIPS_INS_DCLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dclo $rd, $rs */ + Mips_DCLO_R6 /* 1481 */, MIPS_INS_DCLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dclz $rd, $rs */ + Mips_DCLZ /* 1482 */, MIPS_INS_DCLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dclz $rd, $rs */ + Mips_DCLZ_R6 /* 1483 */, MIPS_INS_DCLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ddiv $rd, $rs, $rt */ + Mips_DDIV /* 1484 */, MIPS_INS_DDIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ddivu $rd, $rs, $rt */ + Mips_DDIVU /* 1485 */, MIPS_INS_DDIVU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* deret */ + Mips_DERET /* 1486 */, MIPS_INS_DERET, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* deret */ + Mips_DERET_MM /* 1487 */, MIPS_INS_DERET, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* deret */ + Mips_DERET_MMR6 /* 1488 */, MIPS_INS_DERET, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* deret */ + Mips_DERET_NM /* 1489 */, MIPS_INS_DERET, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dext $rt, $rs, $pos, $size */ + Mips_DEXT /* 1490 */, MIPS_INS_DEXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dext $rt, $rs, $pos, $size */ + Mips_DEXT64_32 /* 1491 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* dextm $rt, $rs, $pos, $size */ + Mips_DEXTM /* 1492 */, MIPS_INS_DEXTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dextu $rt, $rs, $pos, $size */ + Mips_DEXTU /* 1493 */, MIPS_INS_DEXTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* di $rt */ + Mips_DI /* 1494 */, MIPS_INS_DI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dins $rt, $rs, $pos, $size */ + Mips_DINS /* 1495 */, MIPS_INS_DINS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dinsm $rt, $rs, $pos, $size */ + Mips_DINSM /* 1496 */, MIPS_INS_DINSM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dinsu $rt, $rs, $pos, $size */ + Mips_DINSU /* 1497 */, MIPS_INS_DINSU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div $rd, $rs, $rt */ + Mips_DIV /* 1498 */, MIPS_INS_DIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* divu $rd, $rs, $rt */ + Mips_DIVU /* 1499 */, MIPS_INS_DIVU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* divu $rd, $rs, $rt */ + Mips_DIVU_MMR6 /* 1500 */, MIPS_INS_DIVU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* divu $rd, $rs, $rt */ + Mips_DIVU_NM /* 1501 */, MIPS_INS_DIVU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div $rd, $rs, $rt */ + Mips_DIV_MMR6 /* 1502 */, MIPS_INS_DIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div $rd, $rs, $rt */ + Mips_DIV_NM /* 1503 */, MIPS_INS_DIV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div_s.b $wd, $ws, $wt */ + Mips_DIV_S_B /* 1504 */, MIPS_INS_DIV_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div_s.d $wd, $ws, $wt */ + Mips_DIV_S_D /* 1505 */, MIPS_INS_DIV_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div_s.h $wd, $ws, $wt */ + Mips_DIV_S_H /* 1506 */, MIPS_INS_DIV_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div_s.w $wd, $ws, $wt */ + Mips_DIV_S_W /* 1507 */, MIPS_INS_DIV_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div_u.b $wd, $ws, $wt */ + Mips_DIV_U_B /* 1508 */, MIPS_INS_DIV_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div_u.d $wd, $ws, $wt */ + Mips_DIV_U_D /* 1509 */, MIPS_INS_DIV_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div_u.h $wd, $ws, $wt */ + Mips_DIV_U_H /* 1510 */, MIPS_INS_DIV_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div_u.w $wd, $ws, $wt */ + Mips_DIV_U_W /* 1511 */, MIPS_INS_DIV_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* di $rt */ + Mips_DI_MM /* 1512 */, MIPS_INS_DI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* di $rt */ + Mips_DI_MMR6 /* 1513 */, MIPS_INS_DI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* di $rt */ + Mips_DI_NM /* 1514 */, MIPS_INS_DI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dlsa $rd, $rs, $rt, $sa */ + Mips_DLSA /* 1515 */, MIPS_INS_DLSA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, MIPS_FEATURE_HASMIPS64, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dlsa $rd, $rs, $rt, $imm2 */ + Mips_DLSA_R6 /* 1516 */, MIPS_INS_DLSA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmfc0 $rt, $rd, $sel */ + Mips_DMFC0 /* 1517 */, MIPS_INS_DMFC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmfc1 $rt, $fs */ + Mips_DMFC1 /* 1518 */, MIPS_INS_DMFC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmfc2 $rt, $rd, $sel */ + Mips_DMFC2 /* 1519 */, MIPS_INS_DMFC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmfc2 $rt, $imm16 */ + Mips_DMFC2_OCTEON /* 1520 */, MIPS_INS_DMFC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmfgc0 $rt, $rd, $sel */ + Mips_DMFGC0 /* 1521 */, MIPS_INS_DMFGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmod $rd, $rs, $rt */ + Mips_DMOD /* 1522 */, MIPS_INS_DMOD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmodu $rd, $rs, $rt */ + Mips_DMODU /* 1523 */, MIPS_INS_DMODU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmt $rt */ + Mips_DMT /* 1524 */, MIPS_INS_DMT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmtc0 $rt, $rd, $sel */ + Mips_DMTC0 /* 1525 */, MIPS_INS_DMTC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmtc1 $rt, $fs */ + Mips_DMTC1 /* 1526 */, MIPS_INS_DMTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmtc2 $rt, $rd, $sel */ + Mips_DMTC2 /* 1527 */, MIPS_INS_DMTC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS3, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmtc2 $rt, $imm16 */ + Mips_DMTC2_OCTEON /* 1528 */, MIPS_INS_DMTC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmtgc0 $rt, $rd, $sel */ + Mips_DMTGC0 /* 1529 */, MIPS_INS_DMTGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmt $rt */ + Mips_DMT_NM /* 1530 */, MIPS_INS_DMT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmuh $rd, $rs, $rt */ + Mips_DMUH /* 1531 */, MIPS_INS_DMUH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmuhu $rd, $rs, $rt */ + Mips_DMUHU /* 1532 */, MIPS_INS_DMUHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmul $rd, $rs, $rt */ + Mips_DMUL /* 1533 */, MIPS_INS_DMUL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmult $rs, $rt */ + Mips_DMULT /* 1534 */, MIPS_INS_DMULT, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0_64, MIPS_REG_LO0_64, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmultu $rs, $rt */ + Mips_DMULTu /* 1535 */, MIPS_INS_DMULTU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0_64, MIPS_REG_LO0_64, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmulu $rd, $rs, $rt */ + Mips_DMULU /* 1536 */, MIPS_INS_DMULU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dmul $rd, $rs, $rt */ + Mips_DMUL_R6 /* 1537 */, MIPS_INS_DMUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dotp_s.d $wd, $ws, $wt */ + Mips_DOTP_S_D /* 1538 */, MIPS_INS_DOTP_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dotp_s.h $wd, $ws, $wt */ + Mips_DOTP_S_H /* 1539 */, MIPS_INS_DOTP_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dotp_s.w $wd, $ws, $wt */ + Mips_DOTP_S_W /* 1540 */, MIPS_INS_DOTP_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dotp_u.d $wd, $ws, $wt */ + Mips_DOTP_U_D /* 1541 */, MIPS_INS_DOTP_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dotp_u.h $wd, $ws, $wt */ + Mips_DOTP_U_H /* 1542 */, MIPS_INS_DOTP_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dotp_u.w $wd, $ws, $wt */ + Mips_DOTP_U_W /* 1543 */, MIPS_INS_DOTP_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpadd_s.d $wd, $ws, $wt */ + Mips_DPADD_S_D /* 1544 */, MIPS_INS_DPADD_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpadd_s.h $wd, $ws, $wt */ + Mips_DPADD_S_H /* 1545 */, MIPS_INS_DPADD_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpadd_s.w $wd, $ws, $wt */ + Mips_DPADD_S_W /* 1546 */, MIPS_INS_DPADD_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpadd_u.d $wd, $ws, $wt */ + Mips_DPADD_U_D /* 1547 */, MIPS_INS_DPADD_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpadd_u.h $wd, $ws, $wt */ + Mips_DPADD_U_H /* 1548 */, MIPS_INS_DPADD_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpadd_u.w $wd, $ws, $wt */ + Mips_DPADD_U_W /* 1549 */, MIPS_INS_DPADD_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpaqx_sa.w.ph $ac, $rs, $rt */ + Mips_DPAQX_SA_W_PH /* 1550 */, MIPS_INS_DPAQX_SA_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpaqx_sa.w.ph $ac, $rs, $rt */ + Mips_DPAQX_SA_W_PH_MMR2 /* 1551 */, MIPS_INS_DPAQX_SA_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpaqx_s.w.ph $ac, $rs, $rt */ + Mips_DPAQX_S_W_PH /* 1552 */, MIPS_INS_DPAQX_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpaqx_s.w.ph $ac, $rs, $rt */ + Mips_DPAQX_S_W_PH_MMR2 /* 1553 */, MIPS_INS_DPAQX_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpaq_sa.l.w $ac, $rs, $rt */ + Mips_DPAQ_SA_L_W /* 1554 */, MIPS_INS_DPAQ_SA_L_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpaq_sa.l.w $ac, $rs, $rt */ + Mips_DPAQ_SA_L_W_MM /* 1555 */, MIPS_INS_DPAQ_SA_L_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpaq_s.w.ph $ac, $rs, $rt */ + Mips_DPAQ_S_W_PH /* 1556 */, MIPS_INS_DPAQ_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpaq_s.w.ph $ac, $rs, $rt */ + Mips_DPAQ_S_W_PH_MM /* 1557 */, MIPS_INS_DPAQ_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpau.h.qbl $ac, $rs, $rt */ + Mips_DPAU_H_QBL /* 1558 */, MIPS_INS_DPAU_H_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpau.h.qbl $ac, $rs, $rt */ + Mips_DPAU_H_QBL_MM /* 1559 */, MIPS_INS_DPAU_H_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpau.h.qbr $ac, $rs, $rt */ + Mips_DPAU_H_QBR /* 1560 */, MIPS_INS_DPAU_H_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpau.h.qbr $ac, $rs, $rt */ + Mips_DPAU_H_QBR_MM /* 1561 */, MIPS_INS_DPAU_H_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpax.w.ph $ac, $rs, $rt */ + Mips_DPAX_W_PH /* 1562 */, MIPS_INS_DPAX_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpax.w.ph $ac, $rs, $rt */ + Mips_DPAX_W_PH_MMR2 /* 1563 */, MIPS_INS_DPAX_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpa.w.ph $ac, $rs, $rt */ + Mips_DPA_W_PH /* 1564 */, MIPS_INS_DPA_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpa.w.ph $ac, $rs, $rt */ + Mips_DPA_W_PH_MMR2 /* 1565 */, MIPS_INS_DPA_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpop $rd, $rs */ + Mips_DPOP /* 1566 */, MIPS_INS_DPOP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsqx_sa.w.ph $ac, $rs, $rt */ + Mips_DPSQX_SA_W_PH /* 1567 */, MIPS_INS_DPSQX_SA_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsqx_sa.w.ph $ac, $rs, $rt */ + Mips_DPSQX_SA_W_PH_MMR2 /* 1568 */, MIPS_INS_DPSQX_SA_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsqx_s.w.ph $ac, $rs, $rt */ + Mips_DPSQX_S_W_PH /* 1569 */, MIPS_INS_DPSQX_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsqx_s.w.ph $ac, $rs, $rt */ + Mips_DPSQX_S_W_PH_MMR2 /* 1570 */, MIPS_INS_DPSQX_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsq_sa.l.w $ac, $rs, $rt */ + Mips_DPSQ_SA_L_W /* 1571 */, MIPS_INS_DPSQ_SA_L_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsq_sa.l.w $ac, $rs, $rt */ + Mips_DPSQ_SA_L_W_MM /* 1572 */, MIPS_INS_DPSQ_SA_L_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsq_s.w.ph $ac, $rs, $rt */ + Mips_DPSQ_S_W_PH /* 1573 */, MIPS_INS_DPSQ_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsq_s.w.ph $ac, $rs, $rt */ + Mips_DPSQ_S_W_PH_MM /* 1574 */, MIPS_INS_DPSQ_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsub_s.d $wd, $ws, $wt */ + Mips_DPSUB_S_D /* 1575 */, MIPS_INS_DPSUB_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsub_s.h $wd, $ws, $wt */ + Mips_DPSUB_S_H /* 1576 */, MIPS_INS_DPSUB_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsub_s.w $wd, $ws, $wt */ + Mips_DPSUB_S_W /* 1577 */, MIPS_INS_DPSUB_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsub_u.d $wd, $ws, $wt */ + Mips_DPSUB_U_D /* 1578 */, MIPS_INS_DPSUB_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsub_u.h $wd, $ws, $wt */ + Mips_DPSUB_U_H /* 1579 */, MIPS_INS_DPSUB_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsub_u.w $wd, $ws, $wt */ + Mips_DPSUB_U_W /* 1580 */, MIPS_INS_DPSUB_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsu.h.qbl $ac, $rs, $rt */ + Mips_DPSU_H_QBL /* 1581 */, MIPS_INS_DPSU_H_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsu.h.qbl $ac, $rs, $rt */ + Mips_DPSU_H_QBL_MM /* 1582 */, MIPS_INS_DPSU_H_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsu.h.qbr $ac, $rs, $rt */ + Mips_DPSU_H_QBR /* 1583 */, MIPS_INS_DPSU_H_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsu.h.qbr $ac, $rs, $rt */ + Mips_DPSU_H_QBR_MM /* 1584 */, MIPS_INS_DPSU_H_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsx.w.ph $ac, $rs, $rt */ + Mips_DPSX_W_PH /* 1585 */, MIPS_INS_DPSX_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dpsx.w.ph $ac, $rs, $rt */ + Mips_DPSX_W_PH_MMR2 /* 1586 */, MIPS_INS_DPSX_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dps.w.ph $ac, $rs, $rt */ + Mips_DPS_W_PH /* 1587 */, MIPS_INS_DPS_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dps.w.ph $ac, $rs, $rt */ + Mips_DPS_W_PH_MMR2 /* 1588 */, MIPS_INS_DPS_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* drotr $rd, $rt, $shamt */ + Mips_DROTR /* 1589 */, MIPS_INS_DROTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* drotr32 $rd, $rt, $shamt */ + Mips_DROTR32 /* 1590 */, MIPS_INS_DROTR32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* drotrv $rd, $rt, $rs */ + Mips_DROTRV /* 1591 */, MIPS_INS_DROTRV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsbh $rd, $rt */ + Mips_DSBH /* 1592 */, MIPS_INS_DSBH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ddiv $$zero, $rs, $rt */ + Mips_DSDIV /* 1593 */, MIPS_INS_DDIV, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0_64, MIPS_REG_LO0_64, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dshd $rd, $rt */ + Mips_DSHD /* 1594 */, MIPS_INS_DSHD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsll $rd, $rt, $shamt */ + Mips_DSLL /* 1595 */, MIPS_INS_DSLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsll32 $rd, $rt, $shamt */ + Mips_DSLL32 /* 1596 */, MIPS_INS_DSLL32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsll $rd, $rt, 32 */ + Mips_DSLL64_32 /* 1597 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* dsllv $rd, $rt, $rs */ + Mips_DSLLV /* 1598 */, MIPS_INS_DSLLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsra $rd, $rt, $shamt */ + Mips_DSRA /* 1599 */, MIPS_INS_DSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsra32 $rd, $rt, $shamt */ + Mips_DSRA32 /* 1600 */, MIPS_INS_DSRA32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsrav $rd, $rt, $rs */ + Mips_DSRAV /* 1601 */, MIPS_INS_DSRAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsrl $rd, $rt, $shamt */ + Mips_DSRL /* 1602 */, MIPS_INS_DSRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsrl32 $rd, $rt, $shamt */ + Mips_DSRL32 /* 1603 */, MIPS_INS_DSRL32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsrlv $rd, $rt, $rs */ + Mips_DSRLV /* 1604 */, MIPS_INS_DSRLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsub $rd, $rs, $rt */ + Mips_DSUB /* 1605 */, MIPS_INS_DSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dsubu $rd, $rs, $rt */ + Mips_DSUBu /* 1606 */, MIPS_INS_DSUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ddivu $$zero, $rs, $rt */ + Mips_DUDIV /* 1607 */, MIPS_INS_DDIVU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0_64, MIPS_REG_LO0_64, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dvp $rt */ + Mips_DVP /* 1608 */, MIPS_INS_DVP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dvpe $rt */ + Mips_DVPE /* 1609 */, MIPS_INS_DVPE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dvpe $rt */ + Mips_DVPE_NM /* 1610 */, MIPS_INS_DVPE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* dvp $rs */ + Mips_DVP_MMR6 /* 1611 */, MIPS_INS_DVP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div $$zero, $rx, $ry */ + Mips_DivRxRy16 /* 1612 */, MIPS_INS_DIV, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* divu $$zero, $rx, $ry */ + Mips_DivuRxRy16 /* 1613 */, MIPS_INS_DIVU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ehb */ + Mips_EHB /* 1614 */, MIPS_INS_EHB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ehb */ + Mips_EHB_MM /* 1615 */, MIPS_INS_EHB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ehb */ + Mips_EHB_MMR6 /* 1616 */, MIPS_INS_EHB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ehb */ + Mips_EHB_NM /* 1617 */, MIPS_INS_EHB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ei $rt */ + Mips_EI /* 1618 */, MIPS_INS_EI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ei $rt */ + Mips_EI_MM /* 1619 */, MIPS_INS_EI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ei $rt */ + Mips_EI_MMR6 /* 1620 */, MIPS_INS_EI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ei $rt */ + Mips_EI_NM /* 1621 */, MIPS_INS_EI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* emt $rt */ + Mips_EMT /* 1622 */, MIPS_INS_EMT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* emt $rt */ + Mips_EMT_NM /* 1623 */, MIPS_INS_EMT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* eret */ + Mips_ERET /* 1624 */, MIPS_INS_ERET, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3_32, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* eretnc */ + Mips_ERETNC /* 1625 */, MIPS_INS_ERETNC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* eretnc */ + Mips_ERETNC_MMR6 /* 1626 */, MIPS_INS_ERETNC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* eretnc */ + Mips_ERETNC_NM /* 1627 */, MIPS_INS_ERETNC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* eret */ + Mips_ERET_MM /* 1628 */, MIPS_INS_ERET, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* eret */ + Mips_ERET_MMR6 /* 1629 */, MIPS_INS_ERET, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* eret */ + Mips_ERET_NM /* 1630 */, MIPS_INS_ERET, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* evp $rt */ + Mips_EVP /* 1631 */, MIPS_INS_EVP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* evpe $rt */ + Mips_EVPE /* 1632 */, MIPS_INS_EVPE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* evpe $rt */ + Mips_EVPE_NM /* 1633 */, MIPS_INS_EVPE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* evp $rs */ + Mips_EVP_MMR6 /* 1634 */, MIPS_INS_EVP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ext $rt, $rs, $pos, $size */ + Mips_EXT /* 1635 */, MIPS_INS_EXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extp $rt, $ac, $shift_rs */ + Mips_EXTP /* 1636 */, MIPS_INS_EXTP, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extpdp $rt, $ac, $shift_rs */ + Mips_EXTPDP /* 1637 */, MIPS_INS_EXTPDP, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extpdpv $rt, $ac, $shift_rs */ + Mips_EXTPDPV /* 1638 */, MIPS_INS_EXTPDPV, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extpdpv $rt, $ac, $rs */ + Mips_EXTPDPV_MM /* 1639 */, MIPS_INS_EXTPDPV, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extpdp $rt, $ac, $imm */ + Mips_EXTPDP_MM /* 1640 */, MIPS_INS_EXTPDP, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extpv $rt, $ac, $shift_rs */ + Mips_EXTPV /* 1641 */, MIPS_INS_EXTPV, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extpv $rt, $ac, $rs */ + Mips_EXTPV_MM /* 1642 */, MIPS_INS_EXTPV, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extp $rt, $ac, $imm */ + Mips_EXTP_MM /* 1643 */, MIPS_INS_EXTP, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extrv_rs.w $rt, $ac, $shift_rs */ + Mips_EXTRV_RS_W /* 1644 */, MIPS_INS_EXTRV_RS_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extrv_rs.w $rt, $ac, $rs */ + Mips_EXTRV_RS_W_MM /* 1645 */, MIPS_INS_EXTRV_RS_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extrv_r.w $rt, $ac, $shift_rs */ + Mips_EXTRV_R_W /* 1646 */, MIPS_INS_EXTRV_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extrv_r.w $rt, $ac, $rs */ + Mips_EXTRV_R_W_MM /* 1647 */, MIPS_INS_EXTRV_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extrv_s.h $rt, $ac, $shift_rs */ + Mips_EXTRV_S_H /* 1648 */, MIPS_INS_EXTRV_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extrv_s.h $rt, $ac, $rs */ + Mips_EXTRV_S_H_MM /* 1649 */, MIPS_INS_EXTRV_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extrv.w $rt, $ac, $shift_rs */ + Mips_EXTRV_W /* 1650 */, MIPS_INS_EXTRV_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extrv.w $rt, $ac, $rs */ + Mips_EXTRV_W_MM /* 1651 */, MIPS_INS_EXTRV_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extr_rs.w $rt, $ac, $shift_rs */ + Mips_EXTR_RS_W /* 1652 */, MIPS_INS_EXTR_RS_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extr_rs.w $rt, $ac, $imm */ + Mips_EXTR_RS_W_MM /* 1653 */, MIPS_INS_EXTR_RS_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extr_r.w $rt, $ac, $shift_rs */ + Mips_EXTR_R_W /* 1654 */, MIPS_INS_EXTR_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extr_r.w $rt, $ac, $imm */ + Mips_EXTR_R_W_MM /* 1655 */, MIPS_INS_EXTR_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extr_s.h $rt, $ac, $shift_rs */ + Mips_EXTR_S_H /* 1656 */, MIPS_INS_EXTR_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extr_s.h $rt, $ac, $imm */ + Mips_EXTR_S_H_MM /* 1657 */, MIPS_INS_EXTR_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extr.w $rt, $ac, $shift_rs */ + Mips_EXTR_W /* 1658 */, MIPS_INS_EXTR_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extr.w $rt, $ac, $imm */ + Mips_EXTR_W_MM /* 1659 */, MIPS_INS_EXTR_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* exts $rt, $rs, $pos, $lenm1 */ + Mips_EXTS /* 1660 */, MIPS_INS_EXTS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMIPS64, MIPS_FEATURE_HASCNMIPS, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* exts32 $rt, $rs, $pos, $lenm1 */ + Mips_EXTS32 /* 1661 */, MIPS_INS_EXTS32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASMIPS64, MIPS_FEATURE_HASCNMIPS, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* extw $rd, $rs, $rt, $shift */ + Mips_EXTW_NM /* 1662 */, MIPS_INS_EXTW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ext $rt, $rs, $pos, $size */ + Mips_EXT_MM /* 1663 */, MIPS_INS_EXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ext $rt, $rs, $pos, $size */ + Mips_EXT_MMR6 /* 1664 */, MIPS_INS_EXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ext $rt, $rs, $pos, $size */ + Mips_EXT_NM /* 1665 */, MIPS_INS_EXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* abs.d $fd, $fs */ + Mips_FABS_D32 /* 1666 */, MIPS_INS_ABS_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* abs.d $fd, $fs */ + Mips_FABS_D32_MM /* 1667 */, MIPS_INS_ABS_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* abs.d $fd, $fs */ + Mips_FABS_D64 /* 1668 */, MIPS_INS_ABS_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* abs.d $fd, $fs */ + Mips_FABS_D64_MM /* 1669 */, MIPS_INS_ABS_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* abs.s $fd, $fs */ + Mips_FABS_S /* 1670 */, MIPS_INS_ABS_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* abs.s $fd, $fs */ + Mips_FABS_S_MM /* 1671 */, MIPS_INS_ABS_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fadd.d $wd, $ws, $wt */ + Mips_FADD_D /* 1672 */, MIPS_INS_FADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add.d $fd, $fs, $ft */ + Mips_FADD_D32 /* 1673 */, MIPS_INS_ADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add.d $fd, $fs, $ft */ + Mips_FADD_D32_MM /* 1674 */, MIPS_INS_ADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add.d $fd, $fs, $ft */ + Mips_FADD_D64 /* 1675 */, MIPS_INS_ADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add.d $fd, $fs, $ft */ + Mips_FADD_D64_MM /* 1676 */, MIPS_INS_ADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add.ps $fd, $fs, $ft */ + Mips_FADD_PS64 /* 1677 */, MIPS_INS_ADD_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add.s $fd, $fs, $ft */ + Mips_FADD_S /* 1678 */, MIPS_INS_ADD_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add.s $fd, $fs, $ft */ + Mips_FADD_S_MM /* 1679 */, MIPS_INS_ADD_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* add.s $fd, $fs, $ft */ + Mips_FADD_S_MMR6 /* 1680 */, MIPS_INS_ADD_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fadd.w $wd, $ws, $wt */ + Mips_FADD_W /* 1681 */, MIPS_INS_FADD_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcaf.d $wd, $ws, $wt */ + Mips_FCAF_D /* 1682 */, MIPS_INS_FCAF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcaf.w $wd, $ws, $wt */ + Mips_FCAF_W /* 1683 */, MIPS_INS_FCAF_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fceq.d $wd, $ws, $wt */ + Mips_FCEQ_D /* 1684 */, MIPS_INS_FCEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fceq.w $wd, $ws, $wt */ + Mips_FCEQ_W /* 1685 */, MIPS_INS_FCEQ_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fclass.d $wd, $ws */ + Mips_FCLASS_D /* 1686 */, MIPS_INS_FCLASS_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fclass.w $wd, $ws */ + Mips_FCLASS_W /* 1687 */, MIPS_INS_FCLASS_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcle.d $wd, $ws, $wt */ + Mips_FCLE_D /* 1688 */, MIPS_INS_FCLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcle.w $wd, $ws, $wt */ + Mips_FCLE_W /* 1689 */, MIPS_INS_FCLE_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fclt.d $wd, $ws, $wt */ + Mips_FCLT_D /* 1690 */, MIPS_INS_FCLT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fclt.w $wd, $ws, $wt */ + Mips_FCLT_W /* 1691 */, MIPS_INS_FCLT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* c.$cond.d $fs, $ft */ + Mips_FCMP_D32 /* 1692 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* c.$cond.d $fs, $ft */ + Mips_FCMP_D32_MM /* 1693 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* c.$cond.d $fs, $ft */ + Mips_FCMP_D64 /* 1694 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* c.$cond.s $fs, $ft */ + Mips_FCMP_S32 /* 1695 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* c.$cond.s $fs, $ft */ + Mips_FCMP_S32_MM /* 1696 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* fcne.d $wd, $ws, $wt */ + Mips_FCNE_D /* 1697 */, MIPS_INS_FCNE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcne.w $wd, $ws, $wt */ + Mips_FCNE_W /* 1698 */, MIPS_INS_FCNE_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcor.d $wd, $ws, $wt */ + Mips_FCOR_D /* 1699 */, MIPS_INS_FCOR_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcor.w $wd, $ws, $wt */ + Mips_FCOR_W /* 1700 */, MIPS_INS_FCOR_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcueq.d $wd, $ws, $wt */ + Mips_FCUEQ_D /* 1701 */, MIPS_INS_FCUEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcueq.w $wd, $ws, $wt */ + Mips_FCUEQ_W /* 1702 */, MIPS_INS_FCUEQ_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcule.d $wd, $ws, $wt */ + Mips_FCULE_D /* 1703 */, MIPS_INS_FCULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcule.w $wd, $ws, $wt */ + Mips_FCULE_W /* 1704 */, MIPS_INS_FCULE_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcult.d $wd, $ws, $wt */ + Mips_FCULT_D /* 1705 */, MIPS_INS_FCULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcult.w $wd, $ws, $wt */ + Mips_FCULT_W /* 1706 */, MIPS_INS_FCULT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcune.d $wd, $ws, $wt */ + Mips_FCUNE_D /* 1707 */, MIPS_INS_FCUNE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcune.w $wd, $ws, $wt */ + Mips_FCUNE_W /* 1708 */, MIPS_INS_FCUNE_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcun.d $wd, $ws, $wt */ + Mips_FCUN_D /* 1709 */, MIPS_INS_FCUN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fcun.w $wd, $ws, $wt */ + Mips_FCUN_W /* 1710 */, MIPS_INS_FCUN_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fdiv.d $wd, $ws, $wt */ + Mips_FDIV_D /* 1711 */, MIPS_INS_FDIV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div.d $fd, $fs, $ft */ + Mips_FDIV_D32 /* 1712 */, MIPS_INS_DIV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div.d $fd, $fs, $ft */ + Mips_FDIV_D32_MM /* 1713 */, MIPS_INS_DIV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div.d $fd, $fs, $ft */ + Mips_FDIV_D64 /* 1714 */, MIPS_INS_DIV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div.d $fd, $fs, $ft */ + Mips_FDIV_D64_MM /* 1715 */, MIPS_INS_DIV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div.s $fd, $fs, $ft */ + Mips_FDIV_S /* 1716 */, MIPS_INS_DIV_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div.s $fd, $fs, $ft */ + Mips_FDIV_S_MM /* 1717 */, MIPS_INS_DIV_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div.s $fd, $fs, $ft */ + Mips_FDIV_S_MMR6 /* 1718 */, MIPS_INS_DIV_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fdiv.w $wd, $ws, $wt */ + Mips_FDIV_W /* 1719 */, MIPS_INS_FDIV_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fexdo.h $wd, $ws, $wt */ + Mips_FEXDO_H /* 1720 */, MIPS_INS_FEXDO_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fexdo.w $wd, $ws, $wt */ + Mips_FEXDO_W /* 1721 */, MIPS_INS_FEXDO_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fexp2.d $wd, $ws, $wt */ + Mips_FEXP2_D /* 1722 */, MIPS_INS_FEXP2_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fexp2.w $wd, $ws, $wt */ + Mips_FEXP2_W /* 1723 */, MIPS_INS_FEXP2_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fexupl.d $wd, $ws */ + Mips_FEXUPL_D /* 1724 */, MIPS_INS_FEXUPL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fexupl.w $wd, $ws */ + Mips_FEXUPL_W /* 1725 */, MIPS_INS_FEXUPL_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fexupr.d $wd, $ws */ + Mips_FEXUPR_D /* 1726 */, MIPS_INS_FEXUPR_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fexupr.w $wd, $ws */ + Mips_FEXUPR_W /* 1727 */, MIPS_INS_FEXUPR_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ffint_s.d $wd, $ws */ + Mips_FFINT_S_D /* 1728 */, MIPS_INS_FFINT_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ffint_s.w $wd, $ws */ + Mips_FFINT_S_W /* 1729 */, MIPS_INS_FFINT_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ffint_u.d $wd, $ws */ + Mips_FFINT_U_D /* 1730 */, MIPS_INS_FFINT_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ffint_u.w $wd, $ws */ + Mips_FFINT_U_W /* 1731 */, MIPS_INS_FFINT_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ffql.d $wd, $ws */ + Mips_FFQL_D /* 1732 */, MIPS_INS_FFQL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ffql.w $wd, $ws */ + Mips_FFQL_W /* 1733 */, MIPS_INS_FFQL_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ffqr.d $wd, $ws */ + Mips_FFQR_D /* 1734 */, MIPS_INS_FFQR_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ffqr.w $wd, $ws */ + Mips_FFQR_W /* 1735 */, MIPS_INS_FFQR_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fill.b $wd, $rs */ + Mips_FILL_B /* 1736 */, MIPS_INS_FILL_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fill.d $wd, $rs */ + Mips_FILL_D /* 1737 */, MIPS_INS_FILL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, MIPS_FEATURE_HASMIPS64, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fill.h $wd, $rs */ + Mips_FILL_H /* 1738 */, MIPS_INS_FILL_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fill.w $wd, $rs */ + Mips_FILL_W /* 1739 */, MIPS_INS_FILL_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* flog2.d $wd, $ws */ + Mips_FLOG2_D /* 1740 */, MIPS_INS_FLOG2_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* flog2.w $wd, $ws */ + Mips_FLOG2_W /* 1741 */, MIPS_INS_FLOG2_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.l.d $fd, $fs */ + Mips_FLOOR_L_D64 /* 1742 */, MIPS_INS_FLOOR_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS3_32, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.l.d $ft, $fs */ + Mips_FLOOR_L_D_MMR6 /* 1743 */, MIPS_INS_FLOOR_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.l.s $fd, $fs */ + Mips_FLOOR_L_S /* 1744 */, MIPS_INS_FLOOR_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.l.s $ft, $fs */ + Mips_FLOOR_L_S_MMR6 /* 1745 */, MIPS_INS_FLOOR_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.w.d $fd, $fs */ + Mips_FLOOR_W_D32 /* 1746 */, MIPS_INS_FLOOR_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.w.d $fd, $fs */ + Mips_FLOOR_W_D64 /* 1747 */, MIPS_INS_FLOOR_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.w.d $ft, $fs */ + Mips_FLOOR_W_D_MMR6 /* 1748 */, MIPS_INS_FLOOR_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.w.d $fd, $fs */ + Mips_FLOOR_W_MM /* 1749 */, MIPS_INS_FLOOR_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.w.s $fd, $fs */ + Mips_FLOOR_W_S /* 1750 */, MIPS_INS_FLOOR_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.w.s $fd, $fs */ + Mips_FLOOR_W_S_MM /* 1751 */, MIPS_INS_FLOOR_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* floor.w.s $ft, $fs */ + Mips_FLOOR_W_S_MMR6 /* 1752 */, MIPS_INS_FLOOR_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmadd.d $wd, $ws, $wt */ + Mips_FMADD_D /* 1753 */, MIPS_INS_FMADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmadd.w $wd, $ws, $wt */ + Mips_FMADD_W /* 1754 */, MIPS_INS_FMADD_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmax_a.d $wd, $ws, $wt */ + Mips_FMAX_A_D /* 1755 */, MIPS_INS_FMAX_A_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmax_a.w $wd, $ws, $wt */ + Mips_FMAX_A_W /* 1756 */, MIPS_INS_FMAX_A_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmax.d $wd, $ws, $wt */ + Mips_FMAX_D /* 1757 */, MIPS_INS_FMAX_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmax.w $wd, $ws, $wt */ + Mips_FMAX_W /* 1758 */, MIPS_INS_FMAX_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmin_a.d $wd, $ws, $wt */ + Mips_FMIN_A_D /* 1759 */, MIPS_INS_FMIN_A_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmin_a.w $wd, $ws, $wt */ + Mips_FMIN_A_W /* 1760 */, MIPS_INS_FMIN_A_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmin.d $wd, $ws, $wt */ + Mips_FMIN_D /* 1761 */, MIPS_INS_FMIN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmin.w $wd, $ws, $wt */ + Mips_FMIN_W /* 1762 */, MIPS_INS_FMIN_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mov.d $fd, $fs */ + Mips_FMOV_D32 /* 1763 */, MIPS_INS_MOV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mov.d $fd, $fs */ + Mips_FMOV_D32_MM /* 1764 */, MIPS_INS_MOV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mov.d $fd, $fs */ + Mips_FMOV_D64 /* 1765 */, MIPS_INS_MOV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mov.d $fd, $fs */ + Mips_FMOV_D64_MM /* 1766 */, MIPS_INS_MOV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mov.d $ft, $fs */ + Mips_FMOV_D_MMR6 /* 1767 */, MIPS_INS_MOV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mov.s $fd, $fs */ + Mips_FMOV_S /* 1768 */, MIPS_INS_MOV_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mov.s $fd, $fs */ + Mips_FMOV_S_MM /* 1769 */, MIPS_INS_MOV_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mov.s $ft, $fs */ + Mips_FMOV_S_MMR6 /* 1770 */, MIPS_INS_MOV_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmsub.d $wd, $ws, $wt */ + Mips_FMSUB_D /* 1771 */, MIPS_INS_FMSUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmsub.w $wd, $ws, $wt */ + Mips_FMSUB_W /* 1772 */, MIPS_INS_FMSUB_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmul.d $wd, $ws, $wt */ + Mips_FMUL_D /* 1773 */, MIPS_INS_FMUL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.d $fd, $fs, $ft */ + Mips_FMUL_D32 /* 1774 */, MIPS_INS_MUL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.d $fd, $fs, $ft */ + Mips_FMUL_D32_MM /* 1775 */, MIPS_INS_MUL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.d $fd, $fs, $ft */ + Mips_FMUL_D64 /* 1776 */, MIPS_INS_MUL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.d $fd, $fs, $ft */ + Mips_FMUL_D64_MM /* 1777 */, MIPS_INS_MUL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.ps $fd, $fs, $ft */ + Mips_FMUL_PS64 /* 1778 */, MIPS_INS_MUL_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.s $fd, $fs, $ft */ + Mips_FMUL_S /* 1779 */, MIPS_INS_MUL_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.s $fd, $fs, $ft */ + Mips_FMUL_S_MM /* 1780 */, MIPS_INS_MUL_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.s $fd, $fs, $ft */ + Mips_FMUL_S_MMR6 /* 1781 */, MIPS_INS_MUL_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fmul.w $wd, $ws, $wt */ + Mips_FMUL_W /* 1782 */, MIPS_INS_FMUL_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* neg.d $fd, $fs */ + Mips_FNEG_D32 /* 1783 */, MIPS_INS_NEG_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* neg.d $fd, $fs */ + Mips_FNEG_D32_MM /* 1784 */, MIPS_INS_NEG_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* neg.d $fd, $fs */ + Mips_FNEG_D64 /* 1785 */, MIPS_INS_NEG_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* neg.d $fd, $fs */ + Mips_FNEG_D64_MM /* 1786 */, MIPS_INS_NEG_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* neg.s $fd, $fs */ + Mips_FNEG_S /* 1787 */, MIPS_INS_NEG_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* neg.s $fd, $fs */ + Mips_FNEG_S_MM /* 1788 */, MIPS_INS_NEG_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* neg.s $ft, $fs */ + Mips_FNEG_S_MMR6 /* 1789 */, MIPS_INS_NEG_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fork $rd, $rs, $rt */ + Mips_FORK /* 1790 */, MIPS_INS_FORK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fork $rd, $rs, $rt */ + Mips_FORK_NM /* 1791 */, MIPS_INS_FORK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* frcp.d $wd, $ws */ + Mips_FRCP_D /* 1792 */, MIPS_INS_FRCP_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* frcp.w $wd, $ws */ + Mips_FRCP_W /* 1793 */, MIPS_INS_FRCP_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* frint.d $wd, $ws */ + Mips_FRINT_D /* 1794 */, MIPS_INS_FRINT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* frint.w $wd, $ws */ + Mips_FRINT_W /* 1795 */, MIPS_INS_FRINT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* frsqrt.d $wd, $ws */ + Mips_FRSQRT_D /* 1796 */, MIPS_INS_FRSQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* frsqrt.w $wd, $ws */ + Mips_FRSQRT_W /* 1797 */, MIPS_INS_FRSQRT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsaf.d $wd, $ws, $wt */ + Mips_FSAF_D /* 1798 */, MIPS_INS_FSAF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsaf.w $wd, $ws, $wt */ + Mips_FSAF_W /* 1799 */, MIPS_INS_FSAF_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fseq.d $wd, $ws, $wt */ + Mips_FSEQ_D /* 1800 */, MIPS_INS_FSEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fseq.w $wd, $ws, $wt */ + Mips_FSEQ_W /* 1801 */, MIPS_INS_FSEQ_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsle.d $wd, $ws, $wt */ + Mips_FSLE_D /* 1802 */, MIPS_INS_FSLE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsle.w $wd, $ws, $wt */ + Mips_FSLE_W /* 1803 */, MIPS_INS_FSLE_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fslt.d $wd, $ws, $wt */ + Mips_FSLT_D /* 1804 */, MIPS_INS_FSLT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fslt.w $wd, $ws, $wt */ + Mips_FSLT_W /* 1805 */, MIPS_INS_FSLT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsne.d $wd, $ws, $wt */ + Mips_FSNE_D /* 1806 */, MIPS_INS_FSNE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsne.w $wd, $ws, $wt */ + Mips_FSNE_W /* 1807 */, MIPS_INS_FSNE_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsor.d $wd, $ws, $wt */ + Mips_FSOR_D /* 1808 */, MIPS_INS_FSOR_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsor.w $wd, $ws, $wt */ + Mips_FSOR_W /* 1809 */, MIPS_INS_FSOR_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsqrt.d $wd, $ws */ + Mips_FSQRT_D /* 1810 */, MIPS_INS_FSQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sqrt.d $fd, $fs */ + Mips_FSQRT_D32 /* 1811 */, MIPS_INS_SQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sqrt.d $fd, $fs */ + Mips_FSQRT_D32_MM /* 1812 */, MIPS_INS_SQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sqrt.d $fd, $fs */ + Mips_FSQRT_D64 /* 1813 */, MIPS_INS_SQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sqrt.d $fd, $fs */ + Mips_FSQRT_D64_MM /* 1814 */, MIPS_INS_SQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sqrt.s $fd, $fs */ + Mips_FSQRT_S /* 1815 */, MIPS_INS_SQRT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sqrt.s $fd, $fs */ + Mips_FSQRT_S_MM /* 1816 */, MIPS_INS_SQRT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsqrt.w $wd, $ws */ + Mips_FSQRT_W /* 1817 */, MIPS_INS_FSQRT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsub.d $wd, $ws, $wt */ + Mips_FSUB_D /* 1818 */, MIPS_INS_FSUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub.d $fd, $fs, $ft */ + Mips_FSUB_D32 /* 1819 */, MIPS_INS_SUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub.d $fd, $fs, $ft */ + Mips_FSUB_D32_MM /* 1820 */, MIPS_INS_SUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub.d $fd, $fs, $ft */ + Mips_FSUB_D64 /* 1821 */, MIPS_INS_SUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub.d $fd, $fs, $ft */ + Mips_FSUB_D64_MM /* 1822 */, MIPS_INS_SUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub.ps $fd, $fs, $ft */ + Mips_FSUB_PS64 /* 1823 */, MIPS_INS_SUB_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub.s $fd, $fs, $ft */ + Mips_FSUB_S /* 1824 */, MIPS_INS_SUB_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub.s $fd, $fs, $ft */ + Mips_FSUB_S_MM /* 1825 */, MIPS_INS_SUB_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub.s $fd, $fs, $ft */ + Mips_FSUB_S_MMR6 /* 1826 */, MIPS_INS_SUB_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsub.w $wd, $ws, $wt */ + Mips_FSUB_W /* 1827 */, MIPS_INS_FSUB_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsueq.d $wd, $ws, $wt */ + Mips_FSUEQ_D /* 1828 */, MIPS_INS_FSUEQ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsueq.w $wd, $ws, $wt */ + Mips_FSUEQ_W /* 1829 */, MIPS_INS_FSUEQ_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsule.d $wd, $ws, $wt */ + Mips_FSULE_D /* 1830 */, MIPS_INS_FSULE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsule.w $wd, $ws, $wt */ + Mips_FSULE_W /* 1831 */, MIPS_INS_FSULE_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsult.d $wd, $ws, $wt */ + Mips_FSULT_D /* 1832 */, MIPS_INS_FSULT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsult.w $wd, $ws, $wt */ + Mips_FSULT_W /* 1833 */, MIPS_INS_FSULT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsune.d $wd, $ws, $wt */ + Mips_FSUNE_D /* 1834 */, MIPS_INS_FSUNE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsune.w $wd, $ws, $wt */ + Mips_FSUNE_W /* 1835 */, MIPS_INS_FSUNE_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsun.d $wd, $ws, $wt */ + Mips_FSUN_D /* 1836 */, MIPS_INS_FSUN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* fsun.w $wd, $ws, $wt */ + Mips_FSUN_W /* 1837 */, MIPS_INS_FSUN_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftint_s.d $wd, $ws */ + Mips_FTINT_S_D /* 1838 */, MIPS_INS_FTINT_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftint_s.w $wd, $ws */ + Mips_FTINT_S_W /* 1839 */, MIPS_INS_FTINT_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftint_u.d $wd, $ws */ + Mips_FTINT_U_D /* 1840 */, MIPS_INS_FTINT_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftint_u.w $wd, $ws */ + Mips_FTINT_U_W /* 1841 */, MIPS_INS_FTINT_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftq.h $wd, $ws, $wt */ + Mips_FTQ_H /* 1842 */, MIPS_INS_FTQ_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftq.w $wd, $ws, $wt */ + Mips_FTQ_W /* 1843 */, MIPS_INS_FTQ_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftrunc_s.d $wd, $ws */ + Mips_FTRUNC_S_D /* 1844 */, MIPS_INS_FTRUNC_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftrunc_s.w $wd, $ws */ + Mips_FTRUNC_S_W /* 1845 */, MIPS_INS_FTRUNC_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftrunc_u.d $wd, $ws */ + Mips_FTRUNC_U_D /* 1846 */, MIPS_INS_FTRUNC_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ftrunc_u.w $wd, $ws */ + Mips_FTRUNC_U_W /* 1847 */, MIPS_INS_FTRUNC_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ginvi $rs */ + Mips_GINVI /* 1848 */, MIPS_INS_GINVI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASGINV, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ginvi $rs */ + Mips_GINVI_MMR6 /* 1849 */, MIPS_INS_GINVI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASGINV, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ginvi $rs */ + Mips_GINVI_NM /* 1850 */, MIPS_INS_GINVI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASGINV, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ginvt $rs, $type_ */ + Mips_GINVT /* 1851 */, MIPS_INS_GINVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASGINV, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ginvt $rs, $type */ + Mips_GINVT_MMR6 /* 1852 */, MIPS_INS_GINVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_HASGINV, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ginvt $rs, $type */ + Mips_GINVT_NM /* 1853 */, MIPS_INS_GINVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASGINV, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hadd_s.d $wd, $ws, $wt */ + Mips_HADD_S_D /* 1854 */, MIPS_INS_HADD_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hadd_s.h $wd, $ws, $wt */ + Mips_HADD_S_H /* 1855 */, MIPS_INS_HADD_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hadd_s.w $wd, $ws, $wt */ + Mips_HADD_S_W /* 1856 */, MIPS_INS_HADD_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hadd_u.d $wd, $ws, $wt */ + Mips_HADD_U_D /* 1857 */, MIPS_INS_HADD_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hadd_u.h $wd, $ws, $wt */ + Mips_HADD_U_H /* 1858 */, MIPS_INS_HADD_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hadd_u.w $wd, $ws, $wt */ + Mips_HADD_U_W /* 1859 */, MIPS_INS_HADD_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hsub_s.d $wd, $ws, $wt */ + Mips_HSUB_S_D /* 1860 */, MIPS_INS_HSUB_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hsub_s.h $wd, $ws, $wt */ + Mips_HSUB_S_H /* 1861 */, MIPS_INS_HSUB_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hsub_s.w $wd, $ws, $wt */ + Mips_HSUB_S_W /* 1862 */, MIPS_INS_HSUB_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hsub_u.d $wd, $ws, $wt */ + Mips_HSUB_U_D /* 1863 */, MIPS_INS_HSUB_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hsub_u.h $wd, $ws, $wt */ + Mips_HSUB_U_H /* 1864 */, MIPS_INS_HSUB_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hsub_u.w $wd, $ws, $wt */ + Mips_HSUB_U_W /* 1865 */, MIPS_INS_HSUB_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hypcall $code_ */ + Mips_HYPCALL /* 1866 */, MIPS_INS_HYPCALL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* hypcall $code_ */ + Mips_HYPCALL_MM /* 1867 */, MIPS_INS_HYPCALL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvev.b $wd, $ws, $wt */ + Mips_ILVEV_B /* 1868 */, MIPS_INS_ILVEV_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvev.d $wd, $ws, $wt */ + Mips_ILVEV_D /* 1869 */, MIPS_INS_ILVEV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvev.h $wd, $ws, $wt */ + Mips_ILVEV_H /* 1870 */, MIPS_INS_ILVEV_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvev.w $wd, $ws, $wt */ + Mips_ILVEV_W /* 1871 */, MIPS_INS_ILVEV_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvl.b $wd, $ws, $wt */ + Mips_ILVL_B /* 1872 */, MIPS_INS_ILVL_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvl.d $wd, $ws, $wt */ + Mips_ILVL_D /* 1873 */, MIPS_INS_ILVL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvl.h $wd, $ws, $wt */ + Mips_ILVL_H /* 1874 */, MIPS_INS_ILVL_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvl.w $wd, $ws, $wt */ + Mips_ILVL_W /* 1875 */, MIPS_INS_ILVL_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvod.b $wd, $ws, $wt */ + Mips_ILVOD_B /* 1876 */, MIPS_INS_ILVOD_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvod.d $wd, $ws, $wt */ + Mips_ILVOD_D /* 1877 */, MIPS_INS_ILVOD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvod.h $wd, $ws, $wt */ + Mips_ILVOD_H /* 1878 */, MIPS_INS_ILVOD_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvod.w $wd, $ws, $wt */ + Mips_ILVOD_W /* 1879 */, MIPS_INS_ILVOD_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvr.b $wd, $ws, $wt */ + Mips_ILVR_B /* 1880 */, MIPS_INS_ILVR_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvr.d $wd, $ws, $wt */ + Mips_ILVR_D /* 1881 */, MIPS_INS_ILVR_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvr.h $wd, $ws, $wt */ + Mips_ILVR_H /* 1882 */, MIPS_INS_ILVR_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ilvr.w $wd, $ws, $wt */ + Mips_ILVR_W /* 1883 */, MIPS_INS_ILVR_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ins $rt, $rs, $pos, $size */ + Mips_INS /* 1884 */, MIPS_INS_INS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insert.b $wd[$n], $rs */ + Mips_INSERT_B /* 1885 */, MIPS_INS_INSERT_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insert.d $wd[$n], $rs */ + Mips_INSERT_D /* 1886 */, MIPS_INS_INSERT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, MIPS_FEATURE_HASMIPS64, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insert.h $wd[$n], $rs */ + Mips_INSERT_H /* 1887 */, MIPS_INS_INSERT_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insert.w $wd[$n], $rs */ + Mips_INSERT_W /* 1888 */, MIPS_INS_INSERT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insv $rt, $rs */ + Mips_INSV /* 1889 */, MIPS_INS_INSV, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insve.b $wd[$n], $ws[$n2] */ + Mips_INSVE_B /* 1890 */, MIPS_INS_INSVE_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insve.d $wd[$n], $ws[$n2] */ + Mips_INSVE_D /* 1891 */, MIPS_INS_INSVE_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insve.h $wd[$n], $ws[$n2] */ + Mips_INSVE_H /* 1892 */, MIPS_INS_INSVE_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insve.w $wd[$n], $ws[$n2] */ + Mips_INSVE_W /* 1893 */, MIPS_INS_INSVE_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* insv $rt, $rs */ + Mips_INSV_MM /* 1894 */, MIPS_INS_INSV, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ins $rt, $rs, $pos, $size */ + Mips_INS_MM /* 1895 */, MIPS_INS_INS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ins $rt, $rs, $pos, $size */ + Mips_INS_MMR6 /* 1896 */, MIPS_INS_INS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ins $rt, $rs, $pos, $size */ + Mips_INS_NM /* 1897 */, MIPS_INS_INS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* j $target */ + Mips_J /* 1898 */, MIPS_INS_J, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* jal $target */ + Mips_JAL /* 1899 */, MIPS_INS_JAL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalr $rd, $rs */ + Mips_JALR /* 1900 */, MIPS_INS_JALR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOINDIRECTJUMPGUARDS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalr $rs */ + Mips_JALR16_MM /* 1901 */, MIPS_INS_JALR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalr $rd, $rs */ + Mips_JALR64 /* 1902 */, MIPS_INS_JALR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_NOTINMIPS16MODE, MIPS_FEATURE_ISPTR64BIT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalr $rs */ + Mips_JALRC16_MMR6 /* 1903 */, MIPS_INS_JALR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalrc $rt, $rs */ + Mips_JALRC16_NM /* 1904 */, MIPS_INS_JALRC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA_NM, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalrc.hb $rt, $rs */ + Mips_JALRCHB_NM /* 1905 */, MIPS_INS_JALRC_HB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA_NM, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalrc.hb $rt, $rs */ + Mips_JALRC_HB_MMR6 /* 1906 */, MIPS_INS_JALRC_HB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 1, {{ 0 }} + + #endif +}, +{ + /* jalrc $rt, $rs */ + Mips_JALRC_MMR6 /* 1907 */, MIPS_INS_JALRC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalrc $rt, $rs */ + Mips_JALRC_NM /* 1908 */, MIPS_INS_JALRC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA_NM, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalrs16 $rs */ + Mips_JALRS16_MM /* 1909 */, MIPS_INS_JALRS16, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalrs $rd, $rs */ + Mips_JALRS_MM /* 1910 */, MIPS_INS_JALRS, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalr.hb $rd, $rs */ + Mips_JALR_HB /* 1911 */, MIPS_INS_JALR_HB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, 0 }, 0, 1, {{ 0 }} + + #endif +}, +{ + /* jalr.hb $rd, $rs */ + Mips_JALR_HB64 /* 1912 */, MIPS_INS_JALR_HB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R2, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 1, {{ 0 }} + + #endif +}, +{ + /* jalr $rd, $rs */ + Mips_JALR_MM /* 1913 */, MIPS_INS_JALR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jals $target */ + Mips_JALS_MM /* 1914 */, MIPS_INS_JALS, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalx $target */ + Mips_JALX /* 1915 */, MIPS_INS_JALX, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jalx $target */ + Mips_JALX_MM /* 1916 */, MIPS_INS_JALX, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jal $target */ + Mips_JAL_MM /* 1917 */, MIPS_INS_JAL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jialc $rt, $offset */ + Mips_JIALC /* 1918 */, MIPS_INS_JIALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jialc $rt, $offset */ + Mips_JIALC64 /* 1919 */, MIPS_INS_JIALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jialc $rt, $offset */ + Mips_JIALC_MMR6 /* 1920 */, MIPS_INS_JIALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jic $rt, $offset */ + Mips_JIC /* 1921 */, MIPS_INS_JIC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jic $rt, $offset */ + Mips_JIC64 /* 1922 */, MIPS_INS_JIC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS64R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jic $rt, $offset */ + Mips_JIC_MMR6 /* 1923 */, MIPS_INS_JIC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* jr $rs */ + Mips_JR /* 1924 */, MIPS_INS_JR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jr16 $rs */ + Mips_JR16_MM /* 1925 */, MIPS_INS_JR16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jr $rs */ + Mips_JR64 /* 1926 */, MIPS_INS_JR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_NOTINMIPS16MODE, MIPS_FEATURE_ISPTR64BIT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jraddiusp $imm */ + Mips_JRADDIUSP /* 1927 */, MIPS_INS_JRADDIUSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jrc $rs */ + Mips_JRC16_MM /* 1928 */, MIPS_INS_JRC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jrc16 $rs */ + Mips_JRC16_MMR6 /* 1929 */, MIPS_INS_JRC16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jrcaddiusp $imm */ + Mips_JRCADDIUSP_MMR6 /* 1930 */, MIPS_INS_JRCADDIUSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jrc $rs */ + Mips_JRC_NM /* 1931 */, MIPS_INS_JRC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jr.hb $rs */ + Mips_JR_HB /* 1932 */, MIPS_INS_JR_HB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jr.hb $rs */ + Mips_JR_HB64 /* 1933 */, MIPS_INS_JR_HB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jr.hb $rs */ + Mips_JR_HB64_R6 /* 1934 */, MIPS_INS_JR_HB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jr.hb $rs */ + Mips_JR_HB_R6 /* 1935 */, MIPS_INS_JR_HB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jr $rs */ + Mips_JR_MM /* 1936 */, MIPS_INS_JR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* j $target */ + Mips_J_MM /* 1937 */, MIPS_INS_J, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 1, 0, {{ 0 }} + + #endif +}, +{ + /* jal $imm26 + nop */ + Mips_Jal16 /* 1938 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* jal $imm26 # branch + nop */ + Mips_JalB16 /* 1939 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* jr $$ra */ + Mips_JrRa16 /* 1940 */, MIPS_INS_JR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_RET, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jrc $$ra */ + Mips_JrcRa16 /* 1941 */, MIPS_INS_JRC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_GRP_RET, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jrc $rs */ + Mips_JrcRx16 /* 1942 */, MIPS_INS_JRC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_JUMP, MIPS_FEATURE_INMIPS16MODE, 0 }, 1, 1, {{ 0 }} + + #endif +}, +{ + /* jalrc $rx */ + Mips_JumpLinkReg16 /* 1943 */, MIPS_INS_JALRC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_CALL, MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lapc.h $rt, $addr */ + Mips_LAPC32_NM /* 1944 */, MIPS_INS_LAPC_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lapc.b $rt, $addr */ + Mips_LAPC48_NM /* 1945 */, MIPS_INS_LAPC_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lb $rt, $addr */ + Mips_LB /* 1946 */, MIPS_INS_LB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lb $rt, $addr */ + Mips_LB16_NM /* 1947 */, MIPS_INS_LB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lb $rt, $addr */ + Mips_LB64 /* 1948 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lbe $rt, $addr */ + Mips_LBE /* 1949 */, MIPS_INS_LBE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbe $rt, $addr */ + Mips_LBE_MM /* 1950 */, MIPS_INS_LBE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lb $rt, $addr */ + Mips_LBGP_NM /* 1951 */, MIPS_INS_LB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbu16 $rt, $addr */ + Mips_LBU16_MM /* 1952 */, MIPS_INS_LBU16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbu $rt, $addr */ + Mips_LBU16_NM /* 1953 */, MIPS_INS_LBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbu $rt, $addr */ + Mips_LBUGP_NM /* 1954 */, MIPS_INS_LBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbux $rd, ${index}(${base}) */ + Mips_LBUX /* 1955 */, MIPS_INS_LBUX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbux $rd, ${index}(${base}) */ + Mips_LBUX_MM /* 1956 */, MIPS_INS_LBUX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbux $rt, $addr */ + Mips_LBUX_NM /* 1957 */, MIPS_INS_LBUX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbu $rt, $addr */ + Mips_LBU_MMR6 /* 1958 */, MIPS_INS_LBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbu $rt, $addr */ + Mips_LBU_NM /* 1959 */, MIPS_INS_LBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbu $rt, $addr */ + Mips_LBUs9_NM /* 1960 */, MIPS_INS_LBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbx $rt, $addr */ + Mips_LBX_NM /* 1961 */, MIPS_INS_LBX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lb $rt, $addr */ + Mips_LB_MM /* 1962 */, MIPS_INS_LB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lb $rt, $addr */ + Mips_LB_MMR6 /* 1963 */, MIPS_INS_LB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lb $rt, $addr */ + Mips_LB_NM /* 1964 */, MIPS_INS_LB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lb $rt, $addr */ + Mips_LBs9_NM /* 1965 */, MIPS_INS_LB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbu $rt, $addr */ + Mips_LBu /* 1966 */, MIPS_INS_LBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbu $rt, $addr */ + Mips_LBu64 /* 1967 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lbue $rt, $addr */ + Mips_LBuE /* 1968 */, MIPS_INS_LBUE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbue $rt, $addr */ + Mips_LBuE_MM /* 1969 */, MIPS_INS_LBUE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lbu $rt, $addr */ + Mips_LBu_MM /* 1970 */, MIPS_INS_LBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ld $rt, $addr */ + Mips_LD /* 1971 */, MIPS_INS_LD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldc1 $rt, $addr */ + Mips_LDC1 /* 1972 */, MIPS_INS_LDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldc1 $rt, $addr */ + Mips_LDC164 /* 1973 */, MIPS_INS_LDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldc1 $ft, $addr */ + Mips_LDC1_D64_MMR6 /* 1974 */, MIPS_INS_LDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldc1 $rt, $addr */ + Mips_LDC1_MM_D32 /* 1975 */, MIPS_INS_LDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldc1 $rt, $addr */ + Mips_LDC1_MM_D64 /* 1976 */, MIPS_INS_LDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldc2 $rt, $addr */ + Mips_LDC2 /* 1977 */, MIPS_INS_LDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldc2 $rt, $addr */ + Mips_LDC2_MMR6 /* 1978 */, MIPS_INS_LDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldc2 $rt, $addr */ + Mips_LDC2_R6 /* 1979 */, MIPS_INS_LDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldc3 $rt, $addr */ + Mips_LDC3 /* 1980 */, MIPS_INS_LDC3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTCNMIPS, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldi.b $wd, $s10 */ + Mips_LDI_B /* 1981 */, MIPS_INS_LDI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldi.d $wd, $s10 */ + Mips_LDI_D /* 1982 */, MIPS_INS_LDI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldi.h $wd, $s10 */ + Mips_LDI_H /* 1983 */, MIPS_INS_LDI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldi.w $wd, $s10 */ + Mips_LDI_W /* 1984 */, MIPS_INS_LDI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldl $rt, $addr */ + Mips_LDL /* 1985 */, MIPS_INS_LDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldpc $rs, $imm */ + Mips_LDPC /* 1986 */, MIPS_INS_LDPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldr $rt, $addr */ + Mips_LDR /* 1987 */, MIPS_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldxc1 $fd, ${index}(${base}) */ + Mips_LDXC1 /* 1988 */, MIPS_INS_LDXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ldxc1 $fd, ${index}(${base}) */ + Mips_LDXC164 /* 1989 */, MIPS_INS_LDXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ld.b $wd, $addr */ + Mips_LD_B /* 1990 */, MIPS_INS_LD_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ld.d $wd, $addr */ + Mips_LD_D /* 1991 */, MIPS_INS_LD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ld.h $wd, $addr */ + Mips_LD_H /* 1992 */, MIPS_INS_LD_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ld.w $wd, $addr */ + Mips_LD_W /* 1993 */, MIPS_INS_LD_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* addiu $rt, $addr */ + Mips_LEA_ADDIU_NM /* 1994 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* addiu $rt, $addr */ + Mips_LEA_ADDiu /* 1995 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* daddiu $rt, $addr */ + Mips_LEA_ADDiu64 /* 1996 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* addiu $rt, $addr */ + Mips_LEA_ADDiu_MM /* 1997 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lh $rt, $addr */ + Mips_LH /* 1998 */, MIPS_INS_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lh $rt, $addr */ + Mips_LH16_NM /* 1999 */, MIPS_INS_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lh $rt, $addr */ + Mips_LH64 /* 2000 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lhe $rt, $addr */ + Mips_LHE /* 2001 */, MIPS_INS_LHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhe $rt, $addr */ + Mips_LHE_MM /* 2002 */, MIPS_INS_LHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lh $rt, $addr */ + Mips_LHGP_NM /* 2003 */, MIPS_INS_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhu16 $rt, $addr */ + Mips_LHU16_MM /* 2004 */, MIPS_INS_LHU16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhu $rt, $addr */ + Mips_LHU16_NM /* 2005 */, MIPS_INS_LHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhu $rt, $addr */ + Mips_LHUGP_NM /* 2006 */, MIPS_INS_LHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhuxs $rt, $addr */ + Mips_LHUXS_NM /* 2007 */, MIPS_INS_LHUXS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhux $rt, $addr */ + Mips_LHUX_NM /* 2008 */, MIPS_INS_LHUX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhu $rt, $addr */ + Mips_LHU_NM /* 2009 */, MIPS_INS_LHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhu $rt, $addr */ + Mips_LHUs9_NM /* 2010 */, MIPS_INS_LHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhx $rd, ${index}(${base}) */ + Mips_LHX /* 2011 */, MIPS_INS_LHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhxs $rt, $addr */ + Mips_LHXS_NM /* 2012 */, MIPS_INS_LHXS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhx $rd, ${index}(${base}) */ + Mips_LHX_MM /* 2013 */, MIPS_INS_LHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhx $rt, $addr */ + Mips_LHX_NM /* 2014 */, MIPS_INS_LHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lh $rt, $addr */ + Mips_LH_MM /* 2015 */, MIPS_INS_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lh $rt, $addr */ + Mips_LH_NM /* 2016 */, MIPS_INS_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lh $rt, $addr */ + Mips_LHs9_NM /* 2017 */, MIPS_INS_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhu $rt, $addr */ + Mips_LHu /* 2018 */, MIPS_INS_LHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhu $rt, $addr */ + Mips_LHu64 /* 2019 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lhue $rt, $addr */ + Mips_LHuE /* 2020 */, MIPS_INS_LHUE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhue $rt, $addr */ + Mips_LHuE_MM /* 2021 */, MIPS_INS_LHUE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lhu $rt, $addr */ + Mips_LHu_MM /* 2022 */, MIPS_INS_LHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li16 $rd, $imm */ + Mips_LI16_MM /* 2023 */, MIPS_INS_LI16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li16 $rd, $imm */ + Mips_LI16_MMR6 /* 2024 */, MIPS_INS_LI16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li $rt, $eu */ + Mips_LI16_NM /* 2025 */, MIPS_INS_LI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* li[48] $rt, $imm */ + Mips_LI48_NM /* 2026 */, MIPS_INS_LI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ll $rt, $addr */ + Mips_LL /* 2027 */, MIPS_INS_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISPTR32BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ll $rt, $addr */ + Mips_LL64 /* 2028 */, MIPS_INS_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISPTR64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ll $rt, $addr */ + Mips_LL64_R6 /* 2029 */, MIPS_INS_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISPTR64BIT, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lld $rt, $addr */ + Mips_LLD /* 2030 */, MIPS_INS_LLD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lld $rt, $addr */ + Mips_LLD_R6 /* 2031 */, MIPS_INS_LLD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lle $rt, $addr */ + Mips_LLE /* 2032 */, MIPS_INS_LLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lle $rt, $addr */ + Mips_LLE_MM /* 2033 */, MIPS_INS_LLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* llwp $rt, $ru, $addr */ + Mips_LLWP_NM /* 2034 */, MIPS_INS_LLWP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ll $rt, $addr */ + Mips_LL_MM /* 2035 */, MIPS_INS_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ll $rt, $addr */ + Mips_LL_MMR6 /* 2036 */, MIPS_INS_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ll $rt, $addr */ + Mips_LL_NM /* 2037 */, MIPS_INS_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ll $rt, $addr */ + Mips_LL_R6 /* 2038 */, MIPS_INS_LL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISPTR32BIT, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lsa $rd, $rs, $rt, $sa */ + Mips_LSA /* 2039 */, MIPS_INS_LSA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lsa $rt, $rs, $rd, $imm2 */ + Mips_LSA_MMR6 /* 2040 */, MIPS_INS_LSA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lsa $rd, $rs, $rt, $shift */ + Mips_LSA_NM /* 2041 */, MIPS_INS_LSA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lsa $rd, $rs, $rt, $imm2 */ + Mips_LSA_R6 /* 2042 */, MIPS_INS_LSA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lui $rt, $imm16 */ + Mips_LUI_MMR6 /* 2043 */, MIPS_INS_LUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lui $rt, $imm */ + Mips_LUI_NM /* 2044 */, MIPS_INS_LUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* luxc1 $fd, ${index}(${base}) */ + Mips_LUXC1 /* 2045 */, MIPS_INS_LUXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS5_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* luxc1 $fd, ${index}(${base}) */ + Mips_LUXC164 /* 2046 */, MIPS_INS_LUXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS5_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* luxc1 $fd, ${index}(${base}) */ + Mips_LUXC1_MM /* 2047 */, MIPS_INS_LUXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lui $rt, $imm16 */ + Mips_LUi /* 2048 */, MIPS_INS_LUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lui $rt, $imm16 */ + Mips_LUi64 /* 2049 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lui $rt, $imm16 */ + Mips_LUi_MM /* 2050 */, MIPS_INS_LUI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LW /* 2051 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw16 $rt, $addr */ + Mips_LW16_MM /* 2052 */, MIPS_INS_LW16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LW16_NM /* 2053 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LW4x4_NM /* 2054 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LW64 /* 2055 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lwc1 $rt, $addr */ + Mips_LWC1 /* 2056 */, MIPS_INS_LWC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwc1 $rt, $addr */ + Mips_LWC1_MM /* 2057 */, MIPS_INS_LWC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwc2 $rt, $addr */ + Mips_LWC2 /* 2058 */, MIPS_INS_LWC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwc2 $rt, $addr */ + Mips_LWC2_MMR6 /* 2059 */, MIPS_INS_LWC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwc2 $rt, $addr */ + Mips_LWC2_R6 /* 2060 */, MIPS_INS_LWC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwc3 $rt, $addr */ + Mips_LWC3 /* 2061 */, MIPS_INS_LWC3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTCNMIPS, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LWDSP /* 2062 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_NOTINMIPS16MODE, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LWDSP_MM /* 2063 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwe $rt, $addr */ + Mips_LWE /* 2064 */, MIPS_INS_LWE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwe $rt, $addr */ + Mips_LWE_MM /* 2065 */, MIPS_INS_LWE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LWGP16_NM /* 2066 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $offset */ + Mips_LWGP_MM /* 2067 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LWGP_NM /* 2068 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwl $rt, $addr */ + Mips_LWL /* 2069 */, MIPS_INS_LWL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwl $rt, $addr */ + Mips_LWL64 /* 2070 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lwle $rt, $addr */ + Mips_LWLE /* 2071 */, MIPS_INS_LWLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwle $rt, $addr */ + Mips_LWLE_MM /* 2072 */, MIPS_INS_LWLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwl $rt, $addr */ + Mips_LWL_MM /* 2073 */, MIPS_INS_LWL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwm16 $rt, $addr */ + Mips_LWM16_MM /* 2074 */, MIPS_INS_LWM16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwm16 $rt, $addr */ + Mips_LWM16_MMR6 /* 2075 */, MIPS_INS_LWM16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwm32 $rt, $addr */ + Mips_LWM32_MM /* 2076 */, MIPS_INS_LWM32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwm $rt, $addr, $rcount */ + Mips_LWM_NM /* 2077 */, MIPS_INS_LWM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwpc $rs, $imm */ + Mips_LWPC /* 2078 */, MIPS_INS_LWPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwpc $rt, $imm */ + Mips_LWPC_MMR6 /* 2079 */, MIPS_INS_LWPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwpc $rt, $addr */ + Mips_LWPC_NM /* 2080 */, MIPS_INS_LWPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwp $rt, $addr */ + Mips_LWP_MM /* 2081 */, MIPS_INS_LWP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwr $rt, $addr */ + Mips_LWR /* 2082 */, MIPS_INS_LWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwr $rt, $addr */ + Mips_LWR64 /* 2083 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lwre $rt, $addr */ + Mips_LWRE /* 2084 */, MIPS_INS_LWRE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwre $rt, $addr */ + Mips_LWRE_MM /* 2085 */, MIPS_INS_LWRE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwr $rt, $addr */ + Mips_LWR_MM /* 2086 */, MIPS_INS_LWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LWSP16_NM /* 2087 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $offset */ + Mips_LWSP_MM /* 2088 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwupc $rs, $imm */ + Mips_LWUPC /* 2089 */, MIPS_INS_LWUPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwu $rt, $addr */ + Mips_LWU_MM /* 2090 */, MIPS_INS_LWU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwx $rd, ${index}(${base}) */ + Mips_LWX /* 2091 */, MIPS_INS_LWX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwxc1 $fd, ${index}(${base}) */ + Mips_LWXC1 /* 2092 */, MIPS_INS_LWXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwxc1 $fd, ${index}(${base}) */ + Mips_LWXC1_MM /* 2093 */, MIPS_INS_LWXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwxs $rt, $addr */ + Mips_LWXS16_NM /* 2094 */, MIPS_INS_LWXS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwxs $rd, ${index}(${base}) */ + Mips_LWXS_MM /* 2095 */, MIPS_INS_LWXS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwxs $rt, $addr */ + Mips_LWXS_NM /* 2096 */, MIPS_INS_LWXS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwx $rd, ${index}(${base}) */ + Mips_LWX_MM /* 2097 */, MIPS_INS_LWX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwx $rt, $addr */ + Mips_LWX_NM /* 2098 */, MIPS_INS_LWX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LW_MM /* 2099 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LW_MMR6 /* 2100 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LW_NM /* 2101 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rt, $addr */ + Mips_LWs9_NM /* 2102 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lwu $rt, $addr */ + Mips_LWu /* 2103 */, MIPS_INS_LWU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lb $ry, $addr */ + Mips_LbRxRyOffMemX16 /* 2104 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lbu $ry, $addr */ + Mips_LbuRxRyOffMemX16 /* 2105 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lh $ry, $addr */ + Mips_LhRxRyOffMemX16 /* 2106 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lhu $ry, $addr */ + Mips_LhuRxRyOffMemX16 /* 2107 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* li $rx, $imm8 # 16 bit inst */ + Mips_LiRxImm16 /* 2108 */, MIPS_INS_LI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* .align 2 + li $rx, $imm16 */ + Mips_LiRxImmAlignX16 /* 2109 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* li $rx, $imm16 */ + Mips_LiRxImmX16 /* 2110 */, MIPS_INS_LI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rx, $imm8 # 16 bit inst */ + Mips_LwRxPcTcp16 /* 2111 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $rx, $imm16 */ + Mips_LwRxPcTcpX16 /* 2112 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* lw $ry, $addr */ + Mips_LwRxRyOffMemX16 /* 2113 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lw $ry, $addr */ + Mips_LwRxSpImmX16 /* 2114 */, MIPS_INS_LW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd $rs, $rt */ + Mips_MADD /* 2115 */, MIPS_INS_MADD, + #ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddf.d $fd, $fs, $ft */ + Mips_MADDF_D /* 2116 */, MIPS_INS_MADDF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddf.d $fd, $fs, $ft */ + Mips_MADDF_D_MMR6 /* 2117 */, MIPS_INS_MADDF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddf.s $fd, $fs, $ft */ + Mips_MADDF_S /* 2118 */, MIPS_INS_MADDF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddf.s $fd, $fs, $ft */ + Mips_MADDF_S_MMR6 /* 2119 */, MIPS_INS_MADDF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddr_q.h $wd, $ws, $wt */ + Mips_MADDR_Q_H /* 2120 */, MIPS_INS_MADDR_Q_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddr_q.w $wd, $ws, $wt */ + Mips_MADDR_Q_W /* 2121 */, MIPS_INS_MADDR_Q_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddu $rs, $rt */ + Mips_MADDU /* 2122 */, MIPS_INS_MADDU, + #ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddu $ac, $rs, $rt */ + Mips_MADDU_DSP /* 2123 */, MIPS_INS_MADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddu $ac, $rs, $rt */ + Mips_MADDU_DSP_MM /* 2124 */, MIPS_INS_MADDU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddu $rs, $rt */ + Mips_MADDU_MM /* 2125 */, MIPS_INS_MADDU, + #ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddv.b $wd, $ws, $wt */ + Mips_MADDV_B /* 2126 */, MIPS_INS_MADDV_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddv.d $wd, $ws, $wt */ + Mips_MADDV_D /* 2127 */, MIPS_INS_MADDV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddv.h $wd, $ws, $wt */ + Mips_MADDV_H /* 2128 */, MIPS_INS_MADDV_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maddv.w $wd, $ws, $wt */ + Mips_MADDV_W /* 2129 */, MIPS_INS_MADDV_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd.d $fd, $fr, $fs, $ft */ + Mips_MADD_D32 /* 2130 */, MIPS_INS_MADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_HASMADD4 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd.d $fd, $fr, $fs, $ft */ + Mips_MADD_D32_MM /* 2131 */, MIPS_INS_MADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd.d $fd, $fr, $fs, $ft */ + Mips_MADD_D64 /* 2132 */, MIPS_INS_MADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_HASMADD4 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd $ac, $rs, $rt */ + Mips_MADD_DSP /* 2133 */, MIPS_INS_MADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd $ac, $rs, $rt */ + Mips_MADD_DSP_MM /* 2134 */, MIPS_INS_MADD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd $rs, $rt */ + Mips_MADD_MM /* 2135 */, MIPS_INS_MADD, + #ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd_q.h $wd, $ws, $wt */ + Mips_MADD_Q_H /* 2136 */, MIPS_INS_MADD_Q_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd_q.w $wd, $ws, $wt */ + Mips_MADD_Q_W /* 2137 */, MIPS_INS_MADD_Q_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd.s $fd, $fr, $fs, $ft */ + Mips_MADD_S /* 2138 */, MIPS_INS_MADD_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* madd.s $fd, $fr, $fs, $ft */ + Mips_MADD_S_MM /* 2139 */, MIPS_INS_MADD_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maq_sa.w.phl $ac, $rs, $rt */ + Mips_MAQ_SA_W_PHL /* 2140 */, MIPS_INS_MAQ_SA_W_PHL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maq_sa.w.phl $ac, $rs, $rt */ + Mips_MAQ_SA_W_PHL_MM /* 2141 */, MIPS_INS_MAQ_SA_W_PHL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maq_sa.w.phr $ac, $rs, $rt */ + Mips_MAQ_SA_W_PHR /* 2142 */, MIPS_INS_MAQ_SA_W_PHR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maq_sa.w.phr $ac, $rs, $rt */ + Mips_MAQ_SA_W_PHR_MM /* 2143 */, MIPS_INS_MAQ_SA_W_PHR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maq_s.w.phl $ac, $rs, $rt */ + Mips_MAQ_S_W_PHL /* 2144 */, MIPS_INS_MAQ_S_W_PHL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maq_s.w.phl $ac, $rs, $rt */ + Mips_MAQ_S_W_PHL_MM /* 2145 */, MIPS_INS_MAQ_S_W_PHL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maq_s.w.phr $ac, $rs, $rt */ + Mips_MAQ_S_W_PHR /* 2146 */, MIPS_INS_MAQ_S_W_PHR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maq_s.w.phr $ac, $rs, $rt */ + Mips_MAQ_S_W_PHR_MM /* 2147 */, MIPS_INS_MAQ_S_W_PHR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxa.d $fd, $fs, $ft */ + Mips_MAXA_D /* 2148 */, MIPS_INS_MAXA_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxa.d $fd, $fs, $ft */ + Mips_MAXA_D_MMR6 /* 2149 */, MIPS_INS_MAXA_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxa.s $fd, $fs, $ft */ + Mips_MAXA_S /* 2150 */, MIPS_INS_MAXA_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxa.s $fd, $fs, $ft */ + Mips_MAXA_S_MMR6 /* 2151 */, MIPS_INS_MAXA_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxi_s.b $wd, $ws, $imm */ + Mips_MAXI_S_B /* 2152 */, MIPS_INS_MAXI_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxi_s.d $wd, $ws, $imm */ + Mips_MAXI_S_D /* 2153 */, MIPS_INS_MAXI_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxi_s.h $wd, $ws, $imm */ + Mips_MAXI_S_H /* 2154 */, MIPS_INS_MAXI_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxi_s.w $wd, $ws, $imm */ + Mips_MAXI_S_W /* 2155 */, MIPS_INS_MAXI_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxi_u.b $wd, $ws, $imm */ + Mips_MAXI_U_B /* 2156 */, MIPS_INS_MAXI_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxi_u.d $wd, $ws, $imm */ + Mips_MAXI_U_D /* 2157 */, MIPS_INS_MAXI_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxi_u.h $wd, $ws, $imm */ + Mips_MAXI_U_H /* 2158 */, MIPS_INS_MAXI_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* maxi_u.w $wd, $ws, $imm */ + Mips_MAXI_U_W /* 2159 */, MIPS_INS_MAXI_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_a.b $wd, $ws, $wt */ + Mips_MAX_A_B /* 2160 */, MIPS_INS_MAX_A_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_a.d $wd, $ws, $wt */ + Mips_MAX_A_D /* 2161 */, MIPS_INS_MAX_A_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_a.h $wd, $ws, $wt */ + Mips_MAX_A_H /* 2162 */, MIPS_INS_MAX_A_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_a.w $wd, $ws, $wt */ + Mips_MAX_A_W /* 2163 */, MIPS_INS_MAX_A_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max.d $fd, $fs, $ft */ + Mips_MAX_D /* 2164 */, MIPS_INS_MAX_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max.d $fd, $fs, $ft */ + Mips_MAX_D_MMR6 /* 2165 */, MIPS_INS_MAX_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max.s $fd, $fs, $ft */ + Mips_MAX_S /* 2166 */, MIPS_INS_MAX_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_s.b $wd, $ws, $wt */ + Mips_MAX_S_B /* 2167 */, MIPS_INS_MAX_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_s.d $wd, $ws, $wt */ + Mips_MAX_S_D /* 2168 */, MIPS_INS_MAX_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_s.h $wd, $ws, $wt */ + Mips_MAX_S_H /* 2169 */, MIPS_INS_MAX_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max.s $fd, $fs, $ft */ + Mips_MAX_S_MMR6 /* 2170 */, MIPS_INS_MAX_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_s.w $wd, $ws, $wt */ + Mips_MAX_S_W /* 2171 */, MIPS_INS_MAX_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_u.b $wd, $ws, $wt */ + Mips_MAX_U_B /* 2172 */, MIPS_INS_MAX_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_u.d $wd, $ws, $wt */ + Mips_MAX_U_D /* 2173 */, MIPS_INS_MAX_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_u.h $wd, $ws, $wt */ + Mips_MAX_U_H /* 2174 */, MIPS_INS_MAX_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* max_u.w $wd, $ws, $wt */ + Mips_MAX_U_W /* 2175 */, MIPS_INS_MAX_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc0 $rt, $rd, $sel */ + Mips_MFC0 /* 2176 */, MIPS_INS_MFC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc0 $rt, $c0s */ + Mips_MFC0Sel_NM /* 2177 */, MIPS_INS_MFC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc0 $rt, $rs, $sel */ + Mips_MFC0_MMR6 /* 2178 */, MIPS_INS_MFC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc0 $rt, $c0s, $sel */ + Mips_MFC0_NM /* 2179 */, MIPS_INS_MFC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc1 $rt, $fs */ + Mips_MFC1 /* 2180 */, MIPS_INS_MFC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc1 $rt, $fs */ + Mips_MFC1_D64 /* 2181 */, MIPS_INS_MFC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc1 $rt, $fs */ + Mips_MFC1_MM /* 2182 */, MIPS_INS_MFC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc1 $rt, $fs */ + Mips_MFC1_MMR6 /* 2183 */, MIPS_INS_MFC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc2 $rt, $rd, $sel */ + Mips_MFC2 /* 2184 */, MIPS_INS_MFC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfc2 $rt, $impl */ + Mips_MFC2_MMR6 /* 2185 */, MIPS_INS_MFC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfgc0 $rt, $rd, $sel */ + Mips_MFGC0 /* 2186 */, MIPS_INS_MFGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfgc0 $rt, $rs, $sel */ + Mips_MFGC0_MM /* 2187 */, MIPS_INS_MFGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhc0 $rt, $c0s */ + Mips_MFHC0Sel_NM /* 2188 */, MIPS_INS_MFHC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhc0 $rt, $rs, $sel */ + Mips_MFHC0_MMR6 /* 2189 */, MIPS_INS_MFHC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhc0 $rt, $c0s, $sel */ + Mips_MFHC0_NM /* 2190 */, MIPS_INS_MFHC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhc1 $rt, $fs */ + Mips_MFHC1_D32 /* 2191 */, MIPS_INS_MFHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhc1 $rt, $fs */ + Mips_MFHC1_D32_MM /* 2192 */, MIPS_INS_MFHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhc1 $rt, $fs */ + Mips_MFHC1_D64 /* 2193 */, MIPS_INS_MFHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhc1 $rt, $fs */ + Mips_MFHC1_D64_MM /* 2194 */, MIPS_INS_MFHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhc2 $rt, $impl */ + Mips_MFHC2_MMR6 /* 2195 */, MIPS_INS_MFHC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhgc0 $rt, $rd, $sel */ + Mips_MFHGC0 /* 2196 */, MIPS_INS_MFHGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhgc0 $rt, $rs, $sel */ + Mips_MFHGC0_MM /* 2197 */, MIPS_INS_MFHGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhi $rd */ + Mips_MFHI /* 2198 */, MIPS_INS_MFHI, + #ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhi16 $rd */ + Mips_MFHI16_MM /* 2199 */, MIPS_INS_MFHI16, + #ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhi $rd */ + Mips_MFHI64 /* 2200 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* mfhi $rd, $ac */ + Mips_MFHI_DSP /* 2201 */, MIPS_INS_MFHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhi $rs, $ac */ + Mips_MFHI_DSP_MM /* 2202 */, MIPS_INS_MFHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhi $rd */ + Mips_MFHI_MM /* 2203 */, MIPS_INS_MFHI, + #ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mflo $rd */ + Mips_MFLO /* 2204 */, MIPS_INS_MFLO, + #ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mflo16 $rd */ + Mips_MFLO16_MM /* 2205 */, MIPS_INS_MFLO16, + #ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mflo $rd */ + Mips_MFLO64 /* 2206 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* mflo $rd, $ac */ + Mips_MFLO_DSP /* 2207 */, MIPS_INS_MFLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mflo $rs, $ac */ + Mips_MFLO_DSP_MM /* 2208 */, MIPS_INS_MFLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mflo $rd */ + Mips_MFLO_MM /* 2209 */, MIPS_INS_MFLO, + #ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftr $rd, $rt, $u, $sel, $h */ + Mips_MFTR /* 2210 */, MIPS_INS_MFTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mftr $rd, $rt, $u, $sel, $h */ + Mips_MFTR_NM /* 2211 */, MIPS_INS_MFTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mina.d $fd, $fs, $ft */ + Mips_MINA_D /* 2212 */, MIPS_INS_MINA_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mina.d $fd, $fs, $ft */ + Mips_MINA_D_MMR6 /* 2213 */, MIPS_INS_MINA_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mina.s $fd, $fs, $ft */ + Mips_MINA_S /* 2214 */, MIPS_INS_MINA_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mina.s $fd, $fs, $ft */ + Mips_MINA_S_MMR6 /* 2215 */, MIPS_INS_MINA_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mini_s.b $wd, $ws, $imm */ + Mips_MINI_S_B /* 2216 */, MIPS_INS_MINI_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mini_s.d $wd, $ws, $imm */ + Mips_MINI_S_D /* 2217 */, MIPS_INS_MINI_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mini_s.h $wd, $ws, $imm */ + Mips_MINI_S_H /* 2218 */, MIPS_INS_MINI_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mini_s.w $wd, $ws, $imm */ + Mips_MINI_S_W /* 2219 */, MIPS_INS_MINI_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mini_u.b $wd, $ws, $imm */ + Mips_MINI_U_B /* 2220 */, MIPS_INS_MINI_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mini_u.d $wd, $ws, $imm */ + Mips_MINI_U_D /* 2221 */, MIPS_INS_MINI_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mini_u.h $wd, $ws, $imm */ + Mips_MINI_U_H /* 2222 */, MIPS_INS_MINI_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mini_u.w $wd, $ws, $imm */ + Mips_MINI_U_W /* 2223 */, MIPS_INS_MINI_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_a.b $wd, $ws, $wt */ + Mips_MIN_A_B /* 2224 */, MIPS_INS_MIN_A_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_a.d $wd, $ws, $wt */ + Mips_MIN_A_D /* 2225 */, MIPS_INS_MIN_A_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_a.h $wd, $ws, $wt */ + Mips_MIN_A_H /* 2226 */, MIPS_INS_MIN_A_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_a.w $wd, $ws, $wt */ + Mips_MIN_A_W /* 2227 */, MIPS_INS_MIN_A_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min.d $fd, $fs, $ft */ + Mips_MIN_D /* 2228 */, MIPS_INS_MIN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min.d $fd, $fs, $ft */ + Mips_MIN_D_MMR6 /* 2229 */, MIPS_INS_MIN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min.s $fd, $fs, $ft */ + Mips_MIN_S /* 2230 */, MIPS_INS_MIN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_s.b $wd, $ws, $wt */ + Mips_MIN_S_B /* 2231 */, MIPS_INS_MIN_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_s.d $wd, $ws, $wt */ + Mips_MIN_S_D /* 2232 */, MIPS_INS_MIN_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_s.h $wd, $ws, $wt */ + Mips_MIN_S_H /* 2233 */, MIPS_INS_MIN_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min.s $fd, $fs, $ft */ + Mips_MIN_S_MMR6 /* 2234 */, MIPS_INS_MIN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_s.w $wd, $ws, $wt */ + Mips_MIN_S_W /* 2235 */, MIPS_INS_MIN_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_u.b $wd, $ws, $wt */ + Mips_MIN_U_B /* 2236 */, MIPS_INS_MIN_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_u.d $wd, $ws, $wt */ + Mips_MIN_U_D /* 2237 */, MIPS_INS_MIN_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_u.h $wd, $ws, $wt */ + Mips_MIN_U_H /* 2238 */, MIPS_INS_MIN_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* min_u.w $wd, $ws, $wt */ + Mips_MIN_U_W /* 2239 */, MIPS_INS_MIN_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod $rd, $rs, $rt */ + Mips_MOD /* 2240 */, MIPS_INS_MOD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* modsub $rd, $rs, $rt */ + Mips_MODSUB /* 2241 */, MIPS_INS_MODSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* modsub $rd, $rs, $rt */ + Mips_MODSUB_MM /* 2242 */, MIPS_INS_MODSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* modu $rd, $rs, $rt */ + Mips_MODU /* 2243 */, MIPS_INS_MODU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* modu $rd, $rs, $rt */ + Mips_MODU_MMR6 /* 2244 */, MIPS_INS_MODU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* modu $rd, $rs, $rt */ + Mips_MODU_NM /* 2245 */, MIPS_INS_MODU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod $rd, $rs, $rt */ + Mips_MOD_MMR6 /* 2246 */, MIPS_INS_MOD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod $rd, $rs, $rt */ + Mips_MOD_NM /* 2247 */, MIPS_INS_MOD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod_s.b $wd, $ws, $wt */ + Mips_MOD_S_B /* 2248 */, MIPS_INS_MOD_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod_s.d $wd, $ws, $wt */ + Mips_MOD_S_D /* 2249 */, MIPS_INS_MOD_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod_s.h $wd, $ws, $wt */ + Mips_MOD_S_H /* 2250 */, MIPS_INS_MOD_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod_s.w $wd, $ws, $wt */ + Mips_MOD_S_W /* 2251 */, MIPS_INS_MOD_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod_u.b $wd, $ws, $wt */ + Mips_MOD_U_B /* 2252 */, MIPS_INS_MOD_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod_u.d $wd, $ws, $wt */ + Mips_MOD_U_D /* 2253 */, MIPS_INS_MOD_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod_u.h $wd, $ws, $wt */ + Mips_MOD_U_H /* 2254 */, MIPS_INS_MOD_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mod_u.w $wd, $ws, $wt */ + Mips_MOD_U_W /* 2255 */, MIPS_INS_MOD_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* move $rd, $rs */ + Mips_MOVE16_MM /* 2256 */, MIPS_INS_MOVE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* move16 $rd, $rs */ + Mips_MOVE16_MMR6 /* 2257 */, MIPS_INS_MOVE16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* move.balc $rd, $rt, $addr */ + Mips_MOVEBALC_NM /* 2258 */, MIPS_INS_MOVE_BALC, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA_NM, 0 }, { MIPS_GRP_CALL, MIPS_GRP_BRANCH_RELATIVE, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movep $dst1, $dst2, $src1, $src2 */ + Mips_MOVEPREV_NM /* 2259 */, MIPS_INS_MOVEP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movep $rd1, $rd2, $rs, $rt */ + Mips_MOVEP_MM /* 2260 */, MIPS_INS_MOVEP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movep $rd1, $rd2, $rs, $rt */ + Mips_MOVEP_MMR6 /* 2261 */, MIPS_INS_MOVEP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movep $dst1, $dst2, $src1, $src2 */ + Mips_MOVEP_NM /* 2262 */, MIPS_INS_MOVEP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* move $rt, $rs */ + Mips_MOVE_NM /* 2263 */, MIPS_INS_MOVE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* move.v $wd, $ws */ + Mips_MOVE_V /* 2264 */, MIPS_INS_MOVE_V, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movf.d $fd, $fs, $fcc */ + Mips_MOVF_D32 /* 2265 */, MIPS_INS_MOVF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movf.d $fd, $fs, $fcc */ + Mips_MOVF_D32_MM /* 2266 */, MIPS_INS_MOVF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movf.d $fd, $fs, $fcc */ + Mips_MOVF_D64 /* 2267 */, MIPS_INS_MOVF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movf $rd, $rs, $fcc */ + Mips_MOVF_I /* 2268 */, MIPS_INS_MOVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movf $rd, $rs, $fcc */ + Mips_MOVF_I64 /* 2269 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movf $rd, $rs, $fcc */ + Mips_MOVF_I_MM /* 2270 */, MIPS_INS_MOVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movf.s $fd, $fs, $fcc */ + Mips_MOVF_S /* 2271 */, MIPS_INS_MOVF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movf.s $fd, $fs, $fcc */ + Mips_MOVF_S_MM /* 2272 */, MIPS_INS_MOVF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movn.d $fd, $fs, $rt */ + Mips_MOVN_I64_D64 /* 2273 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movn $rd, $rs, $rt */ + Mips_MOVN_I64_I /* 2274 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movn $rd, $rs, $rt */ + Mips_MOVN_I64_I64 /* 2275 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movn.s $fd, $fs, $rt */ + Mips_MOVN_I64_S /* 2276 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movn.d $fd, $fs, $rt */ + Mips_MOVN_I_D32 /* 2277 */, MIPS_INS_MOVN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movn.d $fd, $fs, $rt */ + Mips_MOVN_I_D32_MM /* 2278 */, MIPS_INS_MOVN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movn.d $fd, $fs, $rt */ + Mips_MOVN_I_D64 /* 2279 */, MIPS_INS_MOVN_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movn $rd, $rs, $rt */ + Mips_MOVN_I_I /* 2280 */, MIPS_INS_MOVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movn $rd, $rs, $rt */ + Mips_MOVN_I_I64 /* 2281 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movn $rd, $rs, $rt */ + Mips_MOVN_I_MM /* 2282 */, MIPS_INS_MOVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movn.s $fd, $fs, $rt */ + Mips_MOVN_I_S /* 2283 */, MIPS_INS_MOVN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movn.s $fd, $fs, $rt */ + Mips_MOVN_I_S_MM /* 2284 */, MIPS_INS_MOVN_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movn $rd, $rs, $rt */ + Mips_MOVN_NM /* 2285 */, MIPS_INS_MOVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movt.d $fd, $fs, $fcc */ + Mips_MOVT_D32 /* 2286 */, MIPS_INS_MOVT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movt.d $fd, $fs, $fcc */ + Mips_MOVT_D32_MM /* 2287 */, MIPS_INS_MOVT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movt.d $fd, $fs, $fcc */ + Mips_MOVT_D64 /* 2288 */, MIPS_INS_MOVT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movt $rd, $rs, $fcc */ + Mips_MOVT_I /* 2289 */, MIPS_INS_MOVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movt $rd, $rs, $fcc */ + Mips_MOVT_I64 /* 2290 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movt $rd, $rs, $fcc */ + Mips_MOVT_I_MM /* 2291 */, MIPS_INS_MOVT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movt.s $fd, $fs, $fcc */ + Mips_MOVT_S /* 2292 */, MIPS_INS_MOVT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movt.s $fd, $fs, $fcc */ + Mips_MOVT_S_MM /* 2293 */, MIPS_INS_MOVT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movz.d $fd, $fs, $rt */ + Mips_MOVZ_I64_D64 /* 2294 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movz $rd, $rs, $rt */ + Mips_MOVZ_I64_I /* 2295 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movz $rd, $rs, $rt */ + Mips_MOVZ_I64_I64 /* 2296 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movz.s $fd, $fs, $rt */ + Mips_MOVZ_I64_S /* 2297 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movz.d $fd, $fs, $rt */ + Mips_MOVZ_I_D32 /* 2298 */, MIPS_INS_MOVZ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movz.d $fd, $fs, $rt */ + Mips_MOVZ_I_D32_MM /* 2299 */, MIPS_INS_MOVZ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movz.d $fd, $fs, $rt */ + Mips_MOVZ_I_D64 /* 2300 */, MIPS_INS_MOVZ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movz $rd, $rs, $rt */ + Mips_MOVZ_I_I /* 2301 */, MIPS_INS_MOVZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movz $rd, $rs, $rt */ + Mips_MOVZ_I_I64 /* 2302 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* movz $rd, $rs, $rt */ + Mips_MOVZ_I_MM /* 2303 */, MIPS_INS_MOVZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movz.s $fd, $fs, $rt */ + Mips_MOVZ_I_S /* 2304 */, MIPS_INS_MOVZ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movz.s $fd, $fs, $rt */ + Mips_MOVZ_I_S_MM /* 2305 */, MIPS_INS_MOVZ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* movz $rd, $rs, $rt */ + Mips_MOVZ_NM /* 2306 */, MIPS_INS_MOVZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub $rs, $rt */ + Mips_MSUB /* 2307 */, MIPS_INS_MSUB, + #ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubf.d $fd, $fs, $ft */ + Mips_MSUBF_D /* 2308 */, MIPS_INS_MSUBF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubf.d $fd, $fs, $ft */ + Mips_MSUBF_D_MMR6 /* 2309 */, MIPS_INS_MSUBF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubf.s $fd, $fs, $ft */ + Mips_MSUBF_S /* 2310 */, MIPS_INS_MSUBF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubf.s $fd, $fs, $ft */ + Mips_MSUBF_S_MMR6 /* 2311 */, MIPS_INS_MSUBF_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubr_q.h $wd, $ws, $wt */ + Mips_MSUBR_Q_H /* 2312 */, MIPS_INS_MSUBR_Q_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubr_q.w $wd, $ws, $wt */ + Mips_MSUBR_Q_W /* 2313 */, MIPS_INS_MSUBR_Q_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubu $rs, $rt */ + Mips_MSUBU /* 2314 */, MIPS_INS_MSUBU, + #ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubu $ac, $rs, $rt */ + Mips_MSUBU_DSP /* 2315 */, MIPS_INS_MSUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubu $ac, $rs, $rt */ + Mips_MSUBU_DSP_MM /* 2316 */, MIPS_INS_MSUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubu $rs, $rt */ + Mips_MSUBU_MM /* 2317 */, MIPS_INS_MSUBU, + #ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubv.b $wd, $ws, $wt */ + Mips_MSUBV_B /* 2318 */, MIPS_INS_MSUBV_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubv.d $wd, $ws, $wt */ + Mips_MSUBV_D /* 2319 */, MIPS_INS_MSUBV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubv.h $wd, $ws, $wt */ + Mips_MSUBV_H /* 2320 */, MIPS_INS_MSUBV_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msubv.w $wd, $ws, $wt */ + Mips_MSUBV_W /* 2321 */, MIPS_INS_MSUBV_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub.d $fd, $fr, $fs, $ft */ + Mips_MSUB_D32 /* 2322 */, MIPS_INS_MSUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_HASMADD4 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub.d $fd, $fr, $fs, $ft */ + Mips_MSUB_D32_MM /* 2323 */, MIPS_INS_MSUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub.d $fd, $fr, $fs, $ft */ + Mips_MSUB_D64 /* 2324 */, MIPS_INS_MSUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_HASMADD4 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub $ac, $rs, $rt */ + Mips_MSUB_DSP /* 2325 */, MIPS_INS_MSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub $ac, $rs, $rt */ + Mips_MSUB_DSP_MM /* 2326 */, MIPS_INS_MSUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub $rs, $rt */ + Mips_MSUB_MM /* 2327 */, MIPS_INS_MSUB, + #ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub_q.h $wd, $ws, $wt */ + Mips_MSUB_Q_H /* 2328 */, MIPS_INS_MSUB_Q_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub_q.w $wd, $ws, $wt */ + Mips_MSUB_Q_W /* 2329 */, MIPS_INS_MSUB_Q_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub.s $fd, $fr, $fs, $ft */ + Mips_MSUB_S /* 2330 */, MIPS_INS_MSUB_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* msub.s $fd, $fr, $fs, $ft */ + Mips_MSUB_S_MM /* 2331 */, MIPS_INS_MSUB_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc0 $rt, $rd, $sel */ + Mips_MTC0 /* 2332 */, MIPS_INS_MTC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc0 $rt, $c0s */ + Mips_MTC0Sel_NM /* 2333 */, MIPS_INS_MTC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc0 $rt, $rs, $sel */ + Mips_MTC0_MMR6 /* 2334 */, MIPS_INS_MTC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc0 $rt, $c0s, $sel */ + Mips_MTC0_NM /* 2335 */, MIPS_INS_MTC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc1 $rt, $fs */ + Mips_MTC1 /* 2336 */, MIPS_INS_MTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc1 $rt, $fs */ + Mips_MTC1_D64 /* 2337 */, MIPS_INS_MTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc1 $rt, $fs */ + Mips_MTC1_D64_MM /* 2338 */, MIPS_INS_MTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc1 $rt, $fs */ + Mips_MTC1_MM /* 2339 */, MIPS_INS_MTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc1 $rt, $fs */ + Mips_MTC1_MMR6 /* 2340 */, MIPS_INS_MTC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc2 $rt, $rd, $sel */ + Mips_MTC2 /* 2341 */, MIPS_INS_MTC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtc2 $rt, $impl */ + Mips_MTC2_MMR6 /* 2342 */, MIPS_INS_MTC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtgc0 $rt, $rd, $sel */ + Mips_MTGC0 /* 2343 */, MIPS_INS_MTGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtgc0 $rt, $rs, $sel */ + Mips_MTGC0_MM /* 2344 */, MIPS_INS_MTGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthc0 $rt, $c0s */ + Mips_MTHC0Sel_NM /* 2345 */, MIPS_INS_MTHC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthc0 $rt, $rs, $sel */ + Mips_MTHC0_MMR6 /* 2346 */, MIPS_INS_MTHC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthc0 $rt, $c0s, $sel */ + Mips_MTHC0_NM /* 2347 */, MIPS_INS_MTHC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthc1 $rt, $fs */ + Mips_MTHC1_D32 /* 2348 */, MIPS_INS_MTHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthc1 $rt, $fs */ + Mips_MTHC1_D32_MM /* 2349 */, MIPS_INS_MTHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthc1 $rt, $fs */ + Mips_MTHC1_D64 /* 2350 */, MIPS_INS_MTHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthc1 $rt, $fs */ + Mips_MTHC1_D64_MM /* 2351 */, MIPS_INS_MTHC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthc2 $rt, $impl */ + Mips_MTHC2_MMR6 /* 2352 */, MIPS_INS_MTHC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthgc0 $rt, $rd, $sel */ + Mips_MTHGC0 /* 2353 */, MIPS_INS_MTHGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthgc0 $rt, $rs, $sel */ + Mips_MTHGC0_MM /* 2354 */, MIPS_INS_MTHGC0, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthi $rs */ + Mips_MTHI /* 2355 */, MIPS_INS_MTHI, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthi $rs */ + Mips_MTHI64 /* 2356 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* mthi $rs, $ac */ + Mips_MTHI_DSP /* 2357 */, MIPS_INS_MTHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthi $rs, $ac */ + Mips_MTHI_DSP_MM /* 2358 */, MIPS_INS_MTHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthi $rs */ + Mips_MTHI_MM /* 2359 */, MIPS_INS_MTHI, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthlip $rs, $ac */ + Mips_MTHLIP /* 2360 */, MIPS_INS_MTHLIP, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPPOS, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mthlip $rs, $ac */ + Mips_MTHLIP_MM /* 2361 */, MIPS_INS_MTHLIP, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPPOS, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtlo $rs */ + Mips_MTLO /* 2362 */, MIPS_INS_MTLO, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtlo $rs */ + Mips_MTLO64 /* 2363 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* mtlo $rs, $ac */ + Mips_MTLO_DSP /* 2364 */, MIPS_INS_MTLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtlo $rs, $ac */ + Mips_MTLO_DSP_MM /* 2365 */, MIPS_INS_MTLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtlo $rs */ + Mips_MTLO_MM /* 2366 */, MIPS_INS_MTLO, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtm0 $rs */ + Mips_MTM0 /* 2367 */, MIPS_INS_MTM0, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtm1 $rs */ + Mips_MTM1 /* 2368 */, MIPS_INS_MTM1, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_MPL1, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtm2 $rs */ + Mips_MTM2 /* 2369 */, MIPS_INS_MTM2, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtp0 $rs */ + Mips_MTP0 /* 2370 */, MIPS_INS_MTP0, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_P0, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtp1 $rs */ + Mips_MTP1 /* 2371 */, MIPS_INS_MTP1, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_P1, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mtp2 $rs */ + Mips_MTP2 /* 2372 */, MIPS_INS_MTP2, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_P2, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttr $rt, $rd, $u, $sel, $h */ + Mips_MTTR /* 2373 */, MIPS_INS_MTTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mttr $rt, $rd, $u, $sel, $h */ + Mips_MTTR_NM /* 2374 */, MIPS_INS_MTTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muh $rd, $rs, $rt */ + Mips_MUH /* 2375 */, MIPS_INS_MUH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muhu $rd, $rs, $rt */ + Mips_MUHU /* 2376 */, MIPS_INS_MUHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muhu $rd, $rs, $rt */ + Mips_MUHU_MMR6 /* 2377 */, MIPS_INS_MUHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muhu $rd, $rs, $rt */ + Mips_MUHU_NM /* 2378 */, MIPS_INS_MUHU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muh $rd, $rs, $rt */ + Mips_MUH_MMR6 /* 2379 */, MIPS_INS_MUH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muh $rd, $rs, $rt */ + Mips_MUH_NM /* 2380 */, MIPS_INS_MUH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul $rd, $rs, $rt */ + Mips_MUL /* 2381 */, MIPS_INS_MUL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul $dst, $rt, $rs */ + Mips_MUL4x4_NM /* 2382 */, MIPS_INS_MUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muleq_s.w.phl $rd, $rs, $rt */ + Mips_MULEQ_S_W_PHL /* 2383 */, MIPS_INS_MULEQ_S_W_PHL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muleq_s.w.phl $rd, $rs, $rt */ + Mips_MULEQ_S_W_PHL_MM /* 2384 */, MIPS_INS_MULEQ_S_W_PHL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muleq_s.w.phr $rd, $rs, $rt */ + Mips_MULEQ_S_W_PHR /* 2385 */, MIPS_INS_MULEQ_S_W_PHR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muleq_s.w.phr $rd, $rs, $rt */ + Mips_MULEQ_S_W_PHR_MM /* 2386 */, MIPS_INS_MULEQ_S_W_PHR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muleu_s.ph.qbl $rd, $rs, $rt */ + Mips_MULEU_S_PH_QBL /* 2387 */, MIPS_INS_MULEU_S_PH_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muleu_s.ph.qbl $rd, $rs, $rt */ + Mips_MULEU_S_PH_QBL_MM /* 2388 */, MIPS_INS_MULEU_S_PH_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muleu_s.ph.qbr $rd, $rs, $rt */ + Mips_MULEU_S_PH_QBR /* 2389 */, MIPS_INS_MULEU_S_PH_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* muleu_s.ph.qbr $rd, $rs, $rt */ + Mips_MULEU_S_PH_QBR_MM /* 2390 */, MIPS_INS_MULEU_S_PH_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulq_rs.ph $rd, $rs, $rt */ + Mips_MULQ_RS_PH /* 2391 */, MIPS_INS_MULQ_RS_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulq_rs.ph $rd, $rs, $rt */ + Mips_MULQ_RS_PH_MM /* 2392 */, MIPS_INS_MULQ_RS_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulq_rs.w $rd, $rs, $rt */ + Mips_MULQ_RS_W /* 2393 */, MIPS_INS_MULQ_RS_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulq_rs.w $rd, $rs, $rt */ + Mips_MULQ_RS_W_MMR2 /* 2394 */, MIPS_INS_MULQ_RS_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulq_s.ph $rd, $rs, $rt */ + Mips_MULQ_S_PH /* 2395 */, MIPS_INS_MULQ_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulq_s.ph $rd, $rs, $rt */ + Mips_MULQ_S_PH_MMR2 /* 2396 */, MIPS_INS_MULQ_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulq_s.w $rd, $rs, $rt */ + Mips_MULQ_S_W /* 2397 */, MIPS_INS_MULQ_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulq_s.w $rd, $rs, $rt */ + Mips_MULQ_S_W_MMR2 /* 2398 */, MIPS_INS_MULQ_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulr.ps $fd, $fs, $ft */ + Mips_MULR_PS64 /* 2399 */, MIPS_INS_MULR_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMIPS3D, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulr_q.h $wd, $ws, $wt */ + Mips_MULR_Q_H /* 2400 */, MIPS_INS_MULR_Q_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulr_q.w $wd, $ws, $wt */ + Mips_MULR_Q_W /* 2401 */, MIPS_INS_MULR_Q_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulsaq_s.w.ph $ac, $rs, $rt */ + Mips_MULSAQ_S_W_PH /* 2402 */, MIPS_INS_MULSAQ_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulsaq_s.w.ph $ac, $rs, $rt */ + Mips_MULSAQ_S_W_PH_MM /* 2403 */, MIPS_INS_MULSAQ_S_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulsa.w.ph $ac, $rs, $rt */ + Mips_MULSA_W_PH /* 2404 */, MIPS_INS_MULSA_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulsa.w.ph $ac, $rs, $rt */ + Mips_MULSA_W_PH_MMR2 /* 2405 */, MIPS_INS_MULSA_W_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mult $rs, $rt */ + Mips_MULT /* 2406 */, MIPS_INS_MULT, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* multu $ac, $rs, $rt */ + Mips_MULTU_DSP /* 2407 */, MIPS_INS_MULTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* multu $ac, $rs, $rt */ + Mips_MULTU_DSP_MM /* 2408 */, MIPS_INS_MULTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mult $ac, $rs, $rt */ + Mips_MULT_DSP /* 2409 */, MIPS_INS_MULT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mult $ac, $rs, $rt */ + Mips_MULT_DSP_MM /* 2410 */, MIPS_INS_MULT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mult $rs, $rt */ + Mips_MULT_MM /* 2411 */, MIPS_INS_MULT, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* multu $rs, $rt */ + Mips_MULTu /* 2412 */, MIPS_INS_MULTU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* multu $rs, $rt */ + Mips_MULTu_MM /* 2413 */, MIPS_INS_MULTU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulu $rd, $rs, $rt */ + Mips_MULU /* 2414 */, MIPS_INS_MULU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulu $rd, $rs, $rt */ + Mips_MULU_MMR6 /* 2415 */, MIPS_INS_MULU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulu $rd, $rs, $rt */ + Mips_MULU_NM /* 2416 */, MIPS_INS_MULU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulv.b $wd, $ws, $wt */ + Mips_MULV_B /* 2417 */, MIPS_INS_MULV_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulv.d $wd, $ws, $wt */ + Mips_MULV_D /* 2418 */, MIPS_INS_MULV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulv.h $wd, $ws, $wt */ + Mips_MULV_H /* 2419 */, MIPS_INS_MULV_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mulv.w $wd, $ws, $wt */ + Mips_MULV_W /* 2420 */, MIPS_INS_MULV_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul $rd, $rs, $rt */ + Mips_MUL_MM /* 2421 */, MIPS_INS_MUL, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul $rd, $rs, $rt */ + Mips_MUL_MMR6 /* 2422 */, MIPS_INS_MUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul $rd, $rs, $rt */ + Mips_MUL_NM /* 2423 */, MIPS_INS_MUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.ph $rd, $rs, $rt */ + Mips_MUL_PH /* 2424 */, MIPS_INS_MUL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul.ph $rd, $rs, $rt */ + Mips_MUL_PH_MMR2 /* 2425 */, MIPS_INS_MUL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul_q.h $wd, $ws, $wt */ + Mips_MUL_Q_H /* 2426 */, MIPS_INS_MUL_Q_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul_q.w $wd, $ws, $wt */ + Mips_MUL_Q_W /* 2427 */, MIPS_INS_MUL_Q_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul $rd, $rs, $rt */ + Mips_MUL_R6 /* 2428 */, MIPS_INS_MUL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul_s.ph $rd, $rs, $rt */ + Mips_MUL_S_PH /* 2429 */, MIPS_INS_MUL_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mul_s.ph $rd, $rs, $rt */ + Mips_MUL_S_PH_MMR2 /* 2430 */, MIPS_INS_MUL_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mfhi $rx */ + Mips_Mfhi16 /* 2431 */, MIPS_INS_MFHI, + #ifndef CAPSTONE_DIET + { MIPS_REG_HI0, 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* mflo $rx */ + Mips_Mflo16 /* 2432 */, MIPS_INS_MFLO, + #ifndef CAPSTONE_DIET + { MIPS_REG_LO0, 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* move $r32, $rz */ + Mips_Move32R16 /* 2433 */, MIPS_INS_MOVE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* move $ry, $r32 */ + Mips_MoveR3216 /* 2434 */, MIPS_INS_MOVE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nloc.b $wd, $ws */ + Mips_NLOC_B /* 2435 */, MIPS_INS_NLOC_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nloc.d $wd, $ws */ + Mips_NLOC_D /* 2436 */, MIPS_INS_NLOC_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nloc.h $wd, $ws */ + Mips_NLOC_H /* 2437 */, MIPS_INS_NLOC_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nloc.w $wd, $ws */ + Mips_NLOC_W /* 2438 */, MIPS_INS_NLOC_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nlzc.b $wd, $ws */ + Mips_NLZC_B /* 2439 */, MIPS_INS_NLZC_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nlzc.d $wd, $ws */ + Mips_NLZC_D /* 2440 */, MIPS_INS_NLZC_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nlzc.h $wd, $ws */ + Mips_NLZC_H /* 2441 */, MIPS_INS_NLZC_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nlzc.w $wd, $ws */ + Mips_NLZC_W /* 2442 */, MIPS_INS_NLZC_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmadd.d $fd, $fr, $fs, $ft */ + Mips_NMADD_D32 /* 2443 */, MIPS_INS_NMADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, MIPS_FEATURE_NOTINMICROMIPS }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmadd.d $fd, $fr, $fs, $ft */ + Mips_NMADD_D32_MM /* 2444 */, MIPS_INS_NMADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmadd.d $fd, $fr, $fs, $ft */ + Mips_NMADD_D64 /* 2445 */, MIPS_INS_NMADD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, MIPS_FEATURE_NOTINMICROMIPS }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmadd.s $fd, $fr, $fs, $ft */ + Mips_NMADD_S /* 2446 */, MIPS_INS_NMADD_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmadd.s $fd, $fr, $fs, $ft */ + Mips_NMADD_S_MM /* 2447 */, MIPS_INS_NMADD_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmsub.d $fd, $fr, $fs, $ft */ + Mips_NMSUB_D32 /* 2448 */, MIPS_INS_NMSUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, MIPS_FEATURE_NOTINMICROMIPS }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmsub.d $fd, $fr, $fs, $ft */ + Mips_NMSUB_D32_MM /* 2449 */, MIPS_INS_NMSUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmsub.d $fd, $fr, $fs, $ft */ + Mips_NMSUB_D64 /* 2450 */, MIPS_INS_NMSUB_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, MIPS_FEATURE_NOTINMICROMIPS }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmsub.s $fd, $fr, $fs, $ft */ + Mips_NMSUB_S /* 2451 */, MIPS_INS_NMSUB_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nmsub.s $fd, $fr, $fs, $ft */ + Mips_NMSUB_S_MM /* 2452 */, MIPS_INS_NMSUB_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_HASMADD4, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nop32 */ + Mips_NOP32_NM /* 2453 */, MIPS_INS_NOP32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nop */ + Mips_NOP_NM /* 2454 */, MIPS_INS_NOP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nor $rd, $rs, $rt */ + Mips_NOR /* 2455 */, MIPS_INS_NOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nor $rd, $rs, $rt */ + Mips_NOR64 /* 2456 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* nori.b $wd, $ws, $u8 */ + Mips_NORI_B /* 2457 */, MIPS_INS_NORI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nor $rd, $rs, $rt */ + Mips_NOR_MM /* 2458 */, MIPS_INS_NOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nor $rd, $rs, $rt */ + Mips_NOR_MMR6 /* 2459 */, MIPS_INS_NOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nor $rd, $rs, $rt */ + Mips_NOR_NM /* 2460 */, MIPS_INS_NOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* nor.v $wd, $ws, $wt */ + Mips_NOR_V /* 2461 */, MIPS_INS_NOR_V, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* not16 $rt, $rs */ + Mips_NOT16_MM /* 2462 */, MIPS_INS_NOT16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* not16 $rt, $rs */ + Mips_NOT16_MMR6 /* 2463 */, MIPS_INS_NOT16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* not $rt, $rs */ + Mips_NOT16_NM /* 2464 */, MIPS_INS_NOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* neg $rx, $ry */ + Mips_NegRxRy16 /* 2465 */, MIPS_INS_NEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* not $rx, $ry */ + Mips_NotRxRy16 /* 2466 */, MIPS_INS_NOT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or $rd, $rs, $rt */ + Mips_OR /* 2467 */, MIPS_INS_OR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or16 $rt, $rs */ + Mips_OR16_MM /* 2468 */, MIPS_INS_OR16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or16 $rt, $rs */ + Mips_OR16_MMR6 /* 2469 */, MIPS_INS_OR16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or $dst, $rs, $rt */ + Mips_OR16_NM /* 2470 */, MIPS_INS_OR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or $rd, $rs, $rt */ + Mips_OR64 /* 2471 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* ori.b $wd, $ws, $u8 */ + Mips_ORI_B /* 2472 */, MIPS_INS_ORI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ori $rt, $rs, $imm16 */ + Mips_ORI_MMR6 /* 2473 */, MIPS_INS_ORI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ori $rt, $rs, $imm */ + Mips_ORI_NM /* 2474 */, MIPS_INS_ORI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or $rd, $rs, $rt */ + Mips_OR_MM /* 2475 */, MIPS_INS_OR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or $rd, $rs, $rt */ + Mips_OR_MMR6 /* 2476 */, MIPS_INS_OR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or $rd, $rs, $rt */ + Mips_OR_NM /* 2477 */, MIPS_INS_OR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or.v $wd, $ws, $wt */ + Mips_OR_V /* 2478 */, MIPS_INS_OR_V, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ori $rt, $rs, $imm16 */ + Mips_ORi /* 2479 */, MIPS_INS_ORI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ori $rt, $rs, $imm16 */ + Mips_ORi64 /* 2480 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* ori $rt, $rs, $imm16 */ + Mips_ORi_MM /* 2481 */, MIPS_INS_ORI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* or $rz, $ry */ + Mips_OrRxRxRy16 /* 2482 */, MIPS_INS_OR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* packrl.ph $rd, $rs, $rt */ + Mips_PACKRL_PH /* 2483 */, MIPS_INS_PACKRL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* packrl.ph $rd, $rs, $rt */ + Mips_PACKRL_PH_MM /* 2484 */, MIPS_INS_PACKRL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pause */ + Mips_PAUSE /* 2485 */, MIPS_INS_PAUSE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pause */ + Mips_PAUSE_MM /* 2486 */, MIPS_INS_PAUSE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pause */ + Mips_PAUSE_MMR6 /* 2487 */, MIPS_INS_PAUSE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pause */ + Mips_PAUSE_NM /* 2488 */, MIPS_INS_PAUSE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pckev.b $wd, $ws, $wt */ + Mips_PCKEV_B /* 2489 */, MIPS_INS_PCKEV_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pckev.d $wd, $ws, $wt */ + Mips_PCKEV_D /* 2490 */, MIPS_INS_PCKEV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pckev.h $wd, $ws, $wt */ + Mips_PCKEV_H /* 2491 */, MIPS_INS_PCKEV_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pckev.w $wd, $ws, $wt */ + Mips_PCKEV_W /* 2492 */, MIPS_INS_PCKEV_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pckod.b $wd, $ws, $wt */ + Mips_PCKOD_B /* 2493 */, MIPS_INS_PCKOD_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pckod.d $wd, $ws, $wt */ + Mips_PCKOD_D /* 2494 */, MIPS_INS_PCKOD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pckod.h $wd, $ws, $wt */ + Mips_PCKOD_H /* 2495 */, MIPS_INS_PCKOD_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pckod.w $wd, $ws, $wt */ + Mips_PCKOD_W /* 2496 */, MIPS_INS_PCKOD_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pcnt.b $wd, $ws */ + Mips_PCNT_B /* 2497 */, MIPS_INS_PCNT_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pcnt.d $wd, $ws */ + Mips_PCNT_D /* 2498 */, MIPS_INS_PCNT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pcnt.h $wd, $ws */ + Mips_PCNT_H /* 2499 */, MIPS_INS_PCNT_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pcnt.w $wd, $ws */ + Mips_PCNT_W /* 2500 */, MIPS_INS_PCNT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pick.ph $rd, $rs, $rt */ + Mips_PICK_PH /* 2501 */, MIPS_INS_PICK_PH, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pick.ph $rd, $rs, $rt */ + Mips_PICK_PH_MM /* 2502 */, MIPS_INS_PICK_PH, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pick.qb $rd, $rs, $rt */ + Mips_PICK_QB /* 2503 */, MIPS_INS_PICK_QB, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pick.qb $rd, $rs, $rt */ + Mips_PICK_QB_MM /* 2504 */, MIPS_INS_PICK_QB, + #ifndef CAPSTONE_DIET + { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pll.ps $fd, $fs, $ft */ + Mips_PLL_PS64 /* 2505 */, MIPS_INS_PLL_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* plu.ps $fd, $fs, $ft */ + Mips_PLU_PS64 /* 2506 */, MIPS_INS_PLU_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pop $rd, $rs */ + Mips_POP /* 2507 */, MIPS_INS_POP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precequ.ph.qbl $rd, $rt */ + Mips_PRECEQU_PH_QBL /* 2508 */, MIPS_INS_PRECEQU_PH_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precequ.ph.qbla $rd, $rt */ + Mips_PRECEQU_PH_QBLA /* 2509 */, MIPS_INS_PRECEQU_PH_QBLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precequ.ph.qbla $rt, $rs */ + Mips_PRECEQU_PH_QBLA_MM /* 2510 */, MIPS_INS_PRECEQU_PH_QBLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precequ.ph.qbl $rt, $rs */ + Mips_PRECEQU_PH_QBL_MM /* 2511 */, MIPS_INS_PRECEQU_PH_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precequ.ph.qbr $rd, $rt */ + Mips_PRECEQU_PH_QBR /* 2512 */, MIPS_INS_PRECEQU_PH_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precequ.ph.qbra $rd, $rt */ + Mips_PRECEQU_PH_QBRA /* 2513 */, MIPS_INS_PRECEQU_PH_QBRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precequ.ph.qbra $rt, $rs */ + Mips_PRECEQU_PH_QBRA_MM /* 2514 */, MIPS_INS_PRECEQU_PH_QBRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precequ.ph.qbr $rt, $rs */ + Mips_PRECEQU_PH_QBR_MM /* 2515 */, MIPS_INS_PRECEQU_PH_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceq.w.phl $rd, $rt */ + Mips_PRECEQ_W_PHL /* 2516 */, MIPS_INS_PRECEQ_W_PHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceq.w.phl $rt, $rs */ + Mips_PRECEQ_W_PHL_MM /* 2517 */, MIPS_INS_PRECEQ_W_PHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceq.w.phr $rd, $rt */ + Mips_PRECEQ_W_PHR /* 2518 */, MIPS_INS_PRECEQ_W_PHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceq.w.phr $rt, $rs */ + Mips_PRECEQ_W_PHR_MM /* 2519 */, MIPS_INS_PRECEQ_W_PHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceu.ph.qbl $rd, $rt */ + Mips_PRECEU_PH_QBL /* 2520 */, MIPS_INS_PRECEU_PH_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceu.ph.qbla $rd, $rt */ + Mips_PRECEU_PH_QBLA /* 2521 */, MIPS_INS_PRECEU_PH_QBLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceu.ph.qbla $rt, $rs */ + Mips_PRECEU_PH_QBLA_MM /* 2522 */, MIPS_INS_PRECEU_PH_QBLA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceu.ph.qbl $rt, $rs */ + Mips_PRECEU_PH_QBL_MM /* 2523 */, MIPS_INS_PRECEU_PH_QBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceu.ph.qbr $rd, $rt */ + Mips_PRECEU_PH_QBR /* 2524 */, MIPS_INS_PRECEU_PH_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceu.ph.qbra $rd, $rt */ + Mips_PRECEU_PH_QBRA /* 2525 */, MIPS_INS_PRECEU_PH_QBRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceu.ph.qbra $rt, $rs */ + Mips_PRECEU_PH_QBRA_MM /* 2526 */, MIPS_INS_PRECEU_PH_QBRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* preceu.ph.qbr $rt, $rs */ + Mips_PRECEU_PH_QBR_MM /* 2527 */, MIPS_INS_PRECEU_PH_QBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precrqu_s.qb.ph $rd, $rs, $rt */ + Mips_PRECRQU_S_QB_PH /* 2528 */, MIPS_INS_PRECRQU_S_QB_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precrqu_s.qb.ph $rd, $rs, $rt */ + Mips_PRECRQU_S_QB_PH_MM /* 2529 */, MIPS_INS_PRECRQU_S_QB_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precrq.ph.w $rd, $rs, $rt */ + Mips_PRECRQ_PH_W /* 2530 */, MIPS_INS_PRECRQ_PH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precrq.ph.w $rd, $rs, $rt */ + Mips_PRECRQ_PH_W_MM /* 2531 */, MIPS_INS_PRECRQ_PH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precrq.qb.ph $rd, $rs, $rt */ + Mips_PRECRQ_QB_PH /* 2532 */, MIPS_INS_PRECRQ_QB_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precrq.qb.ph $rd, $rs, $rt */ + Mips_PRECRQ_QB_PH_MM /* 2533 */, MIPS_INS_PRECRQ_QB_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precrq_rs.ph.w $rd, $rs, $rt */ + Mips_PRECRQ_RS_PH_W /* 2534 */, MIPS_INS_PRECRQ_RS_PH_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precrq_rs.ph.w $rd, $rs, $rt */ + Mips_PRECRQ_RS_PH_W_MM /* 2535 */, MIPS_INS_PRECRQ_RS_PH_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precr.qb.ph $rd, $rs, $rt */ + Mips_PRECR_QB_PH /* 2536 */, MIPS_INS_PRECR_QB_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precr.qb.ph $rd, $rs, $rt */ + Mips_PRECR_QB_PH_MMR2 /* 2537 */, MIPS_INS_PRECR_QB_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precr_sra.ph.w $rt, $rs, $sa */ + Mips_PRECR_SRA_PH_W /* 2538 */, MIPS_INS_PRECR_SRA_PH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precr_sra.ph.w $rt, $rs, $sa */ + Mips_PRECR_SRA_PH_W_MMR2 /* 2539 */, MIPS_INS_PRECR_SRA_PH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precr_sra_r.ph.w $rt, $rs, $sa */ + Mips_PRECR_SRA_R_PH_W /* 2540 */, MIPS_INS_PRECR_SRA_R_PH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* precr_sra_r.ph.w $rt, $rs, $sa */ + Mips_PRECR_SRA_R_PH_W_MMR2 /* 2541 */, MIPS_INS_PRECR_SRA_R_PH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pref $hint, $addr */ + Mips_PREF /* 2542 */, MIPS_INS_PREF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3_32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* prefe $hint, $addr */ + Mips_PREFE /* 2543 */, MIPS_INS_PREFE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* prefe $hint, $addr */ + Mips_PREFE_MM /* 2544 */, MIPS_INS_PREFE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* prefx $hint, ${index}(${base}) */ + Mips_PREFX_MM /* 2545 */, MIPS_INS_PREFX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pref $hint, $addr */ + Mips_PREF_MM /* 2546 */, MIPS_INS_PREF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pref $hint, $addr */ + Mips_PREF_MMR6 /* 2547 */, MIPS_INS_PREF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pref $op, $addr */ + Mips_PREF_NM /* 2548 */, MIPS_INS_PREF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pref $hint, $addr */ + Mips_PREF_R6 /* 2549 */, MIPS_INS_PREF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pref $op, $addr */ + Mips_PREFs9_NM /* 2550 */, MIPS_INS_PREF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* prepend $rt, $rs, $sa */ + Mips_PREPEND /* 2551 */, MIPS_INS_PREPEND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* prepend $rt, $rs, $sa */ + Mips_PREPEND_MMR2 /* 2552 */, MIPS_INS_PREPEND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* pul.ps $fd, $fs, $ft */ + Mips_PUL_PS64 /* 2553 */, MIPS_INS_PUL_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* puu.ps $fd, $fs, $ft */ + Mips_PUU_PS64 /* 2554 */, MIPS_INS_PUU_PS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* raddu.w.qb $rd, $rs */ + Mips_RADDU_W_QB /* 2555 */, MIPS_INS_RADDU_W_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* raddu.w.qb $rt, $rs */ + Mips_RADDU_W_QB_MM /* 2556 */, MIPS_INS_RADDU_W_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rddsp $rd, $mask */ + Mips_RDDSP /* 2557 */, MIPS_INS_RDDSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rddsp $rt, $mask */ + Mips_RDDSP_MM /* 2558 */, MIPS_INS_RDDSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rdhwr $rt, $rd, $sel */ + Mips_RDHWR /* 2559 */, MIPS_INS_RDHWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rdhwr $rt, $rd, $sel */ + Mips_RDHWR64 /* 2560 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* rdhwr $rt, $rd, $sel */ + Mips_RDHWR_MM /* 2561 */, MIPS_INS_RDHWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rdhwr $rt, $rs, $sel */ + Mips_RDHWR_MMR6 /* 2562 */, MIPS_INS_RDHWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rdhwr $rt, $hs, $sel */ + Mips_RDHWR_NM /* 2563 */, MIPS_INS_RDHWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rdpgpr $rt, $rd */ + Mips_RDPGPR_MMR6 /* 2564 */, MIPS_INS_RDPGPR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rdpgpr $rt, $rs */ + Mips_RDPGPR_NM /* 2565 */, MIPS_INS_RDPGPR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* recip.d $fd, $fs */ + Mips_RECIP_D32 /* 2566 */, MIPS_INS_RECIP_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* recip.d $fd, $fs */ + Mips_RECIP_D32_MM /* 2567 */, MIPS_INS_RECIP_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* recip.d $fd, $fs */ + Mips_RECIP_D64 /* 2568 */, MIPS_INS_RECIP_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* recip.d $fd, $fs */ + Mips_RECIP_D64_MM /* 2569 */, MIPS_INS_RECIP_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* recip.s $fd, $fs */ + Mips_RECIP_S /* 2570 */, MIPS_INS_RECIP_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* recip.s $fd, $fs */ + Mips_RECIP_S_MM /* 2571 */, MIPS_INS_RECIP_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* replv.ph $rd, $rt */ + Mips_REPLV_PH /* 2572 */, MIPS_INS_REPLV_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* replv.ph $rt, $rs */ + Mips_REPLV_PH_MM /* 2573 */, MIPS_INS_REPLV_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* replv.qb $rd, $rt */ + Mips_REPLV_QB /* 2574 */, MIPS_INS_REPLV_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* replv.qb $rt, $rs */ + Mips_REPLV_QB_MM /* 2575 */, MIPS_INS_REPLV_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* repl.ph $rd, $imm */ + Mips_REPL_PH /* 2576 */, MIPS_INS_REPL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* repl.ph $rd, $imm */ + Mips_REPL_PH_MM /* 2577 */, MIPS_INS_REPL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* repl.qb $rd, $imm */ + Mips_REPL_QB /* 2578 */, MIPS_INS_REPL_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* repl.qb $rt, $imm */ + Mips_REPL_QB_MM /* 2579 */, MIPS_INS_REPL_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* restore.jrc $adj$regs */ + Mips_RESTOREJRC16_NM /* 2580 */, MIPS_INS_RESTORE_JRC, + #ifndef CAPSTONE_DIET + { MIPS_REG_SP_NM, 0 }, { MIPS_REG_SP_NM, 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* restore.jrc $adj$regs */ + Mips_RESTOREJRC_NM /* 2581 */, MIPS_INS_RESTORE_JRC, + #ifndef CAPSTONE_DIET + { MIPS_REG_SP_NM, 0 }, { MIPS_REG_SP_NM, 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* restore $adj$regs */ + Mips_RESTORE_NM /* 2582 */, MIPS_INS_RESTORE, + #ifndef CAPSTONE_DIET + { MIPS_REG_SP_NM, 0 }, { MIPS_REG_SP_NM, 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rint.d $fd, $fs */ + Mips_RINT_D /* 2583 */, MIPS_INS_RINT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rint.d $fd, $fs */ + Mips_RINT_D_MMR6 /* 2584 */, MIPS_INS_RINT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rint.s $fd, $fs */ + Mips_RINT_S /* 2585 */, MIPS_INS_RINT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rint.s $fd, $fs */ + Mips_RINT_S_MMR6 /* 2586 */, MIPS_INS_RINT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rotr $rd, $rt, $shamt */ + Mips_ROTR /* 2587 */, MIPS_INS_ROTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rotrv $rd, $rt, $rs */ + Mips_ROTRV /* 2588 */, MIPS_INS_ROTRV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rotrv $rd, $rt, $rs */ + Mips_ROTRV_MM /* 2589 */, MIPS_INS_ROTRV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rotrv $rd, $rs, $rt */ + Mips_ROTRV_NM /* 2590 */, MIPS_INS_ROTRV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rotr $rd, $rt, $shamt */ + Mips_ROTR_MM /* 2591 */, MIPS_INS_ROTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rotr $rt, $rs, $imm */ + Mips_ROTR_NM /* 2592 */, MIPS_INS_ROTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rotx $rt, $rs, $shift, $shiftx, $stripe */ + Mips_ROTX_NM /* 2593 */, MIPS_INS_ROTX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.l.d $fd, $fs */ + Mips_ROUND_L_D64 /* 2594 */, MIPS_INS_ROUND_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS3_32, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.l.d $ft, $fs */ + Mips_ROUND_L_D_MMR6 /* 2595 */, MIPS_INS_ROUND_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.l.s $fd, $fs */ + Mips_ROUND_L_S /* 2596 */, MIPS_INS_ROUND_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.l.s $ft, $fs */ + Mips_ROUND_L_S_MMR6 /* 2597 */, MIPS_INS_ROUND_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.w.d $fd, $fs */ + Mips_ROUND_W_D32 /* 2598 */, MIPS_INS_ROUND_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.w.d $fd, $fs */ + Mips_ROUND_W_D64 /* 2599 */, MIPS_INS_ROUND_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.w.d $ft, $fs */ + Mips_ROUND_W_D_MMR6 /* 2600 */, MIPS_INS_ROUND_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.w.d $fd, $fs */ + Mips_ROUND_W_MM /* 2601 */, MIPS_INS_ROUND_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.w.s $fd, $fs */ + Mips_ROUND_W_S /* 2602 */, MIPS_INS_ROUND_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.w.s $fd, $fs */ + Mips_ROUND_W_S_MM /* 2603 */, MIPS_INS_ROUND_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* round.w.s $ft, $fs */ + Mips_ROUND_W_S_MMR6 /* 2604 */, MIPS_INS_ROUND_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rsqrt.d $fd, $fs */ + Mips_RSQRT_D32 /* 2605 */, MIPS_INS_RSQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rsqrt.d $fd, $fs */ + Mips_RSQRT_D32_MM /* 2606 */, MIPS_INS_RSQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rsqrt.d $fd, $fs */ + Mips_RSQRT_D64 /* 2607 */, MIPS_INS_RSQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rsqrt.d $fd, $fs */ + Mips_RSQRT_D64_MM /* 2608 */, MIPS_INS_RSQRT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rsqrt.s $fd, $fs */ + Mips_RSQRT_S /* 2609 */, MIPS_INS_RSQRT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* rsqrt.s $fd, $fs */ + Mips_RSQRT_S_MM /* 2610 */, MIPS_INS_RSQRT_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_Restore16 /* 2611 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_RestoreX16 /* 2612 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* saa $rt, (${rs}) */ + Mips_SAA /* 2613 */, MIPS_INS_SAA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* saad $rt, (${rs}) */ + Mips_SAAD /* 2614 */, MIPS_INS_SAAD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sat_s.b $wd, $ws, $m */ + Mips_SAT_S_B /* 2615 */, MIPS_INS_SAT_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sat_s.d $wd, $ws, $m */ + Mips_SAT_S_D /* 2616 */, MIPS_INS_SAT_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sat_s.h $wd, $ws, $m */ + Mips_SAT_S_H /* 2617 */, MIPS_INS_SAT_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sat_s.w $wd, $ws, $m */ + Mips_SAT_S_W /* 2618 */, MIPS_INS_SAT_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sat_u.b $wd, $ws, $m */ + Mips_SAT_U_B /* 2619 */, MIPS_INS_SAT_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sat_u.d $wd, $ws, $m */ + Mips_SAT_U_D /* 2620 */, MIPS_INS_SAT_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sat_u.h $wd, $ws, $m */ + Mips_SAT_U_H /* 2621 */, MIPS_INS_SAT_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sat_u.w $wd, $ws, $m */ + Mips_SAT_U_W /* 2622 */, MIPS_INS_SAT_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* save $adj$regs */ + Mips_SAVE16_NM /* 2623 */, MIPS_INS_SAVE, + #ifndef CAPSTONE_DIET + { MIPS_REG_SP_NM, 0 }, { MIPS_REG_SP_NM, 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* save $adj$regs */ + Mips_SAVE_NM /* 2624 */, MIPS_INS_SAVE, + #ifndef CAPSTONE_DIET + { MIPS_REG_SP_NM, 0 }, { MIPS_REG_SP_NM, 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb $rt, $addr */ + Mips_SB /* 2625 */, MIPS_INS_SB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb16 $rt, $addr */ + Mips_SB16_MM /* 2626 */, MIPS_INS_SB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb16 $rt, $addr */ + Mips_SB16_MMR6 /* 2627 */, MIPS_INS_SB16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb $rt, $addr */ + Mips_SB16_NM /* 2628 */, MIPS_INS_SB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb $rt, $addr */ + Mips_SB64 /* 2629 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sbe $rt, $addr */ + Mips_SBE /* 2630 */, MIPS_INS_SBE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sbe $rt, $addr */ + Mips_SBE_MM /* 2631 */, MIPS_INS_SBE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb $rt, $addr */ + Mips_SBGP_NM /* 2632 */, MIPS_INS_SB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sbx $rt, $addr */ + Mips_SBX_NM /* 2633 */, MIPS_INS_SBX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb $rt, $addr */ + Mips_SB_MM /* 2634 */, MIPS_INS_SB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb $rt, $addr */ + Mips_SB_MMR6 /* 2635 */, MIPS_INS_SB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb $rt, $addr */ + Mips_SB_NM /* 2636 */, MIPS_INS_SB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sb $rt, $addr */ + Mips_SBs9_NM /* 2637 */, MIPS_INS_SB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sc $rt, $addr */ + Mips_SC /* 2638 */, MIPS_INS_SC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISPTR32BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sc $rt, $addr */ + Mips_SC64 /* 2639 */, MIPS_INS_SC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISPTR64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sc $rt, $addr */ + Mips_SC64_R6 /* 2640 */, MIPS_INS_SC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISPTR64BIT, MIPS_FEATURE_HASMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* scd $rt, $addr */ + Mips_SCD /* 2641 */, MIPS_INS_SCD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* scd $rt, $addr */ + Mips_SCD_R6 /* 2642 */, MIPS_INS_SCD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sce $rt, $addr */ + Mips_SCE /* 2643 */, MIPS_INS_SCE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sce $rt, $addr */ + Mips_SCE_MM /* 2644 */, MIPS_INS_SCE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* scwp $rt, $ru, $addr */ + Mips_SCWP_NM /* 2645 */, MIPS_INS_SCWP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sc $rt, $addr */ + Mips_SC_MM /* 2646 */, MIPS_INS_SC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sc $rt, $addr */ + Mips_SC_MMR6 /* 2647 */, MIPS_INS_SC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sc $rt, $addr */ + Mips_SC_NM /* 2648 */, MIPS_INS_SC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sc $rt, $addr */ + Mips_SC_R6 /* 2649 */, MIPS_INS_SC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISPTR32BIT, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sd $rt, $addr */ + Mips_SD /* 2650 */, MIPS_INS_SD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdbbp $code_ */ + Mips_SDBBP /* 2651 */, MIPS_INS_SDBBP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdbbp16 $code_ */ + Mips_SDBBP16_MM /* 2652 */, MIPS_INS_SDBBP16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdbbp16 $code_ */ + Mips_SDBBP16_MMR6 /* 2653 */, MIPS_INS_SDBBP16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdbbp $imm */ + Mips_SDBBP16_NM /* 2654 */, MIPS_INS_SDBBP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdbbp $code_ */ + Mips_SDBBP_MM /* 2655 */, MIPS_INS_SDBBP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdbbp $code_ */ + Mips_SDBBP_MMR6 /* 2656 */, MIPS_INS_SDBBP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdbbp $imm */ + Mips_SDBBP_NM /* 2657 */, MIPS_INS_SDBBP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdbbp $code_ */ + Mips_SDBBP_R6 /* 2658 */, MIPS_INS_SDBBP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdc1 $rt, $addr */ + Mips_SDC1 /* 2659 */, MIPS_INS_SDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdc1 $rt, $addr */ + Mips_SDC164 /* 2660 */, MIPS_INS_SDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdc1 $ft, $addr */ + Mips_SDC1_D64_MMR6 /* 2661 */, MIPS_INS_SDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdc1 $rt, $addr */ + Mips_SDC1_MM_D32 /* 2662 */, MIPS_INS_SDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdc1 $rt, $addr */ + Mips_SDC1_MM_D64 /* 2663 */, MIPS_INS_SDC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdc2 $rt, $addr */ + Mips_SDC2 /* 2664 */, MIPS_INS_SDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdc2 $rt, $addr */ + Mips_SDC2_MMR6 /* 2665 */, MIPS_INS_SDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdc2 $rt, $addr */ + Mips_SDC2_R6 /* 2666 */, MIPS_INS_SDC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdc3 $rt, $addr */ + Mips_SDC3 /* 2667 */, MIPS_INS_SDC3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTCNMIPS, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div $$zero, $rs, $rt */ + Mips_SDIV /* 2668 */, MIPS_INS_DIV, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* div $$zero, $rs, $rt */ + Mips_SDIV_MM /* 2669 */, MIPS_INS_DIV, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdl $rt, $addr */ + Mips_SDL /* 2670 */, MIPS_INS_SDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdr $rt, $addr */ + Mips_SDR /* 2671 */, MIPS_INS_SDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdxc1 $fs, ${index}(${base}) */ + Mips_SDXC1 /* 2672 */, MIPS_INS_SDXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sdxc1 $fs, ${index}(${base}) */ + Mips_SDXC164 /* 2673 */, MIPS_INS_SDXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seb $rd, $rt */ + Mips_SEB /* 2674 */, MIPS_INS_SEB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seb $rd, $rt */ + Mips_SEB64 /* 2675 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* seb $rd, $rt */ + Mips_SEB_MM /* 2676 */, MIPS_INS_SEB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seb $rt, $rs */ + Mips_SEB_NM /* 2677 */, MIPS_INS_SEB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seh $rd, $rt */ + Mips_SEH /* 2678 */, MIPS_INS_SEH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seh $rd, $rt */ + Mips_SEH64 /* 2679 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* seh $rd, $rt */ + Mips_SEH_MM /* 2680 */, MIPS_INS_SEH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seh $rt, $rs */ + Mips_SEH_NM /* 2681 */, MIPS_INS_SEH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seleqz $rd, $rs, $rt */ + Mips_SELEQZ /* 2682 */, MIPS_INS_SELEQZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP32BIT, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seleqz $rd, $rs, $rt */ + Mips_SELEQZ64 /* 2683 */, MIPS_INS_SELEQZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seleqz.d $fd, $fs, $ft */ + Mips_SELEQZ_D /* 2684 */, MIPS_INS_SELEQZ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seleqz.d $fd, $fs, $ft */ + Mips_SELEQZ_D_MMR6 /* 2685 */, MIPS_INS_SELEQZ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seleqz $rd, $rs, $rt */ + Mips_SELEQZ_MMR6 /* 2686 */, MIPS_INS_SELEQZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seleqz.s $fd, $fs, $ft */ + Mips_SELEQZ_S /* 2687 */, MIPS_INS_SELEQZ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seleqz.s $fd, $fs, $ft */ + Mips_SELEQZ_S_MMR6 /* 2688 */, MIPS_INS_SELEQZ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* selnez $rd, $rs, $rt */ + Mips_SELNEZ /* 2689 */, MIPS_INS_SELNEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP32BIT, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* selnez $rd, $rs, $rt */ + Mips_SELNEZ64 /* 2690 */, MIPS_INS_SELNEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISGP64BIT, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* selnez.d $fd, $fs, $ft */ + Mips_SELNEZ_D /* 2691 */, MIPS_INS_SELNEZ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* selnez.d $fd, $fs, $ft */ + Mips_SELNEZ_D_MMR6 /* 2692 */, MIPS_INS_SELNEZ_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* selnez $rd, $rs, $rt */ + Mips_SELNEZ_MMR6 /* 2693 */, MIPS_INS_SELNEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* selnez.s $fd, $fs, $ft */ + Mips_SELNEZ_S /* 2694 */, MIPS_INS_SELNEZ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* selnez.s $fd, $fs, $ft */ + Mips_SELNEZ_S_MMR6 /* 2695 */, MIPS_INS_SELNEZ_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sel.d $fd, $fs, $ft */ + Mips_SEL_D /* 2696 */, MIPS_INS_SEL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sel.d $fd, $fs, $ft */ + Mips_SEL_D_MMR6 /* 2697 */, MIPS_INS_SEL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sel.s $fd, $fs, $ft */ + Mips_SEL_S /* 2698 */, MIPS_INS_SEL_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sel.s $fd, $fs, $ft */ + Mips_SEL_S_MMR6 /* 2699 */, MIPS_INS_SEL_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seq $rd, $rs, $rt */ + Mips_SEQ /* 2700 */, MIPS_INS_SEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seqi $rt, $rs, $imm */ + Mips_SEQI_NM /* 2701 */, MIPS_INS_SEQI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seqi $rt, $rs, $imm10 */ + Mips_SEQi /* 2702 */, MIPS_INS_SEQI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh $rt, $addr */ + Mips_SH /* 2703 */, MIPS_INS_SH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh16 $rt, $addr */ + Mips_SH16_MM /* 2704 */, MIPS_INS_SH16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh16 $rt, $addr */ + Mips_SH16_MMR6 /* 2705 */, MIPS_INS_SH16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh $rt, $addr */ + Mips_SH16_NM /* 2706 */, MIPS_INS_SH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh $rt, $addr */ + Mips_SH64 /* 2707 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* she $rt, $addr */ + Mips_SHE /* 2708 */, MIPS_INS_SHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* she $rt, $addr */ + Mips_SHE_MM /* 2709 */, MIPS_INS_SHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shf.b $wd, $ws, $u8 */ + Mips_SHF_B /* 2710 */, MIPS_INS_SHF_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shf.h $wd, $ws, $u8 */ + Mips_SHF_H /* 2711 */, MIPS_INS_SHF_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shf.w $wd, $ws, $u8 */ + Mips_SHF_W /* 2712 */, MIPS_INS_SHF_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh $rt, $addr */ + Mips_SHGP_NM /* 2713 */, MIPS_INS_SH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shilo $ac, $shift */ + Mips_SHILO /* 2714 */, MIPS_INS_SHILO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shilov $ac, $rs */ + Mips_SHILOV /* 2715 */, MIPS_INS_SHILOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shilov $ac, $rs */ + Mips_SHILOV_MM /* 2716 */, MIPS_INS_SHILOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shilo $ac, $shift */ + Mips_SHILO_MM /* 2717 */, MIPS_INS_SHILO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shllv.ph $rd, $rt, $rs_sa */ + Mips_SHLLV_PH /* 2718 */, MIPS_INS_SHLLV_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shllv.ph $rd, $rt, $rs */ + Mips_SHLLV_PH_MM /* 2719 */, MIPS_INS_SHLLV_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shllv.qb $rd, $rt, $rs_sa */ + Mips_SHLLV_QB /* 2720 */, MIPS_INS_SHLLV_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shllv.qb $rd, $rt, $rs */ + Mips_SHLLV_QB_MM /* 2721 */, MIPS_INS_SHLLV_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shllv_s.ph $rd, $rt, $rs_sa */ + Mips_SHLLV_S_PH /* 2722 */, MIPS_INS_SHLLV_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shllv_s.ph $rd, $rt, $rs */ + Mips_SHLLV_S_PH_MM /* 2723 */, MIPS_INS_SHLLV_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shllv_s.w $rd, $rt, $rs_sa */ + Mips_SHLLV_S_W /* 2724 */, MIPS_INS_SHLLV_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shllv_s.w $rd, $rt, $rs */ + Mips_SHLLV_S_W_MM /* 2725 */, MIPS_INS_SHLLV_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shll.ph $rd, $rt, $rs_sa */ + Mips_SHLL_PH /* 2726 */, MIPS_INS_SHLL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shll.ph $rt, $rs, $sa */ + Mips_SHLL_PH_MM /* 2727 */, MIPS_INS_SHLL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shll.qb $rd, $rt, $rs_sa */ + Mips_SHLL_QB /* 2728 */, MIPS_INS_SHLL_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shll.qb $rt, $rs, $sa */ + Mips_SHLL_QB_MM /* 2729 */, MIPS_INS_SHLL_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shll_s.ph $rd, $rt, $rs_sa */ + Mips_SHLL_S_PH /* 2730 */, MIPS_INS_SHLL_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shll_s.ph $rt, $rs, $sa */ + Mips_SHLL_S_PH_MM /* 2731 */, MIPS_INS_SHLL_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shll_s.w $rd, $rt, $rs_sa */ + Mips_SHLL_S_W /* 2732 */, MIPS_INS_SHLL_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shll_s.w $rt, $rs, $sa */ + Mips_SHLL_S_W_MM /* 2733 */, MIPS_INS_SHLL_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav.ph $rd, $rt, $rs_sa */ + Mips_SHRAV_PH /* 2734 */, MIPS_INS_SHRAV_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav.ph $rd, $rt, $rs */ + Mips_SHRAV_PH_MM /* 2735 */, MIPS_INS_SHRAV_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav.qb $rd, $rt, $rs_sa */ + Mips_SHRAV_QB /* 2736 */, MIPS_INS_SHRAV_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav.qb $rd, $rt, $rs */ + Mips_SHRAV_QB_MMR2 /* 2737 */, MIPS_INS_SHRAV_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav_r.ph $rd, $rt, $rs_sa */ + Mips_SHRAV_R_PH /* 2738 */, MIPS_INS_SHRAV_R_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav_r.ph $rd, $rt, $rs */ + Mips_SHRAV_R_PH_MM /* 2739 */, MIPS_INS_SHRAV_R_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav_r.qb $rd, $rt, $rs_sa */ + Mips_SHRAV_R_QB /* 2740 */, MIPS_INS_SHRAV_R_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav_r.qb $rd, $rt, $rs */ + Mips_SHRAV_R_QB_MMR2 /* 2741 */, MIPS_INS_SHRAV_R_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav_r.w $rd, $rt, $rs_sa */ + Mips_SHRAV_R_W /* 2742 */, MIPS_INS_SHRAV_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrav_r.w $rd, $rt, $rs */ + Mips_SHRAV_R_W_MM /* 2743 */, MIPS_INS_SHRAV_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra.ph $rd, $rt, $rs_sa */ + Mips_SHRA_PH /* 2744 */, MIPS_INS_SHRA_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra.ph $rt, $rs, $sa */ + Mips_SHRA_PH_MM /* 2745 */, MIPS_INS_SHRA_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra.qb $rd, $rt, $rs_sa */ + Mips_SHRA_QB /* 2746 */, MIPS_INS_SHRA_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra.qb $rt, $rs, $sa */ + Mips_SHRA_QB_MMR2 /* 2747 */, MIPS_INS_SHRA_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra_r.ph $rd, $rt, $rs_sa */ + Mips_SHRA_R_PH /* 2748 */, MIPS_INS_SHRA_R_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra_r.ph $rt, $rs, $sa */ + Mips_SHRA_R_PH_MM /* 2749 */, MIPS_INS_SHRA_R_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra_r.qb $rd, $rt, $rs_sa */ + Mips_SHRA_R_QB /* 2750 */, MIPS_INS_SHRA_R_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra_r.qb $rt, $rs, $sa */ + Mips_SHRA_R_QB_MMR2 /* 2751 */, MIPS_INS_SHRA_R_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra_r.w $rd, $rt, $rs_sa */ + Mips_SHRA_R_W /* 2752 */, MIPS_INS_SHRA_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shra_r.w $rt, $rs, $sa */ + Mips_SHRA_R_W_MM /* 2753 */, MIPS_INS_SHRA_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrlv.ph $rd, $rt, $rs_sa */ + Mips_SHRLV_PH /* 2754 */, MIPS_INS_SHRLV_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrlv.ph $rd, $rt, $rs */ + Mips_SHRLV_PH_MMR2 /* 2755 */, MIPS_INS_SHRLV_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrlv.qb $rd, $rt, $rs_sa */ + Mips_SHRLV_QB /* 2756 */, MIPS_INS_SHRLV_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrlv.qb $rd, $rt, $rs */ + Mips_SHRLV_QB_MM /* 2757 */, MIPS_INS_SHRLV_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrl.ph $rd, $rt, $rs_sa */ + Mips_SHRL_PH /* 2758 */, MIPS_INS_SHRL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrl.ph $rt, $rs, $sa */ + Mips_SHRL_PH_MMR2 /* 2759 */, MIPS_INS_SHRL_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrl.qb $rd, $rt, $rs_sa */ + Mips_SHRL_QB /* 2760 */, MIPS_INS_SHRL_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shrl.qb $rt, $rs, $sa */ + Mips_SHRL_QB_MM /* 2761 */, MIPS_INS_SHRL_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shxs $rt, $addr */ + Mips_SHXS_NM /* 2762 */, MIPS_INS_SHXS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* shx $rt, $addr */ + Mips_SHX_NM /* 2763 */, MIPS_INS_SHX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh $rt, $addr */ + Mips_SH_MM /* 2764 */, MIPS_INS_SH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh $rt, $addr */ + Mips_SH_MMR6 /* 2765 */, MIPS_INS_SH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh $rt, $addr */ + Mips_SH_NM /* 2766 */, MIPS_INS_SH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh $rt, $addr */ + Mips_SHs9_NM /* 2767 */, MIPS_INS_SH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sigrie $code_ */ + Mips_SIGRIE /* 2768 */, MIPS_INS_SIGRIE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sigrie $code_ */ + Mips_SIGRIE_MMR6 /* 2769 */, MIPS_INS_SIGRIE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sigrie $imm */ + Mips_SIGRIE_NM /* 2770 */, MIPS_INS_SIGRIE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sldi.b $wd, $ws[$n] */ + Mips_SLDI_B /* 2771 */, MIPS_INS_SLDI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sldi.d $wd, $ws[$n] */ + Mips_SLDI_D /* 2772 */, MIPS_INS_SLDI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sldi.h $wd, $ws[$n] */ + Mips_SLDI_H /* 2773 */, MIPS_INS_SLDI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sldi.w $wd, $ws[$n] */ + Mips_SLDI_W /* 2774 */, MIPS_INS_SLDI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sld.b $wd, $ws[$rt] */ + Mips_SLD_B /* 2775 */, MIPS_INS_SLD_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sld.d $wd, $ws[$rt] */ + Mips_SLD_D /* 2776 */, MIPS_INS_SLD_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sld.h $wd, $ws[$rt] */ + Mips_SLD_H /* 2777 */, MIPS_INS_SLD_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sld.w $wd, $ws[$rt] */ + Mips_SLD_W /* 2778 */, MIPS_INS_SLD_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll $rd, $rt, $shamt */ + Mips_SLL /* 2779 */, MIPS_INS_SLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll16 $rd, $rt, $shamt */ + Mips_SLL16_MM /* 2780 */, MIPS_INS_SLL16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll16 $rd, $rt, $shamt */ + Mips_SLL16_MMR6 /* 2781 */, MIPS_INS_SLL16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll $rt, $rs, $imm */ + Mips_SLL16_NM /* 2782 */, MIPS_INS_SLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll $rd, $rt, 0 */ + Mips_SLL64_32 /* 2783 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sll $rd, $rt, 0 */ + Mips_SLL64_64 /* 2784 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slli.b $wd, $ws, $m */ + Mips_SLLI_B /* 2785 */, MIPS_INS_SLLI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slli.d $wd, $ws, $m */ + Mips_SLLI_D /* 2786 */, MIPS_INS_SLLI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slli.h $wd, $ws, $m */ + Mips_SLLI_H /* 2787 */, MIPS_INS_SLLI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slli.w $wd, $ws, $m */ + Mips_SLLI_W /* 2788 */, MIPS_INS_SLLI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sllv $rd, $rt, $rs */ + Mips_SLLV /* 2789 */, MIPS_INS_SLLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sllv $rd, $rt, $rs */ + Mips_SLLV_MM /* 2790 */, MIPS_INS_SLLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sllv $rd, $rs, $rt */ + Mips_SLLV_NM /* 2791 */, MIPS_INS_SLLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll.b $wd, $ws, $wt */ + Mips_SLL_B /* 2792 */, MIPS_INS_SLL_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll.d $wd, $ws, $wt */ + Mips_SLL_D /* 2793 */, MIPS_INS_SLL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll.h $wd, $ws, $wt */ + Mips_SLL_H /* 2794 */, MIPS_INS_SLL_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll $rd, $rt, $shamt */ + Mips_SLL_MM /* 2795 */, MIPS_INS_SLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll $rd, $rt, $shamt */ + Mips_SLL_MMR6 /* 2796 */, MIPS_INS_SLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll $rt, $rs, $imm */ + Mips_SLL_NM /* 2797 */, MIPS_INS_SLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll.w $wd, $ws, $wt */ + Mips_SLL_W /* 2798 */, MIPS_INS_SLL_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slt $rd, $rs, $rt */ + Mips_SLT /* 2799 */, MIPS_INS_SLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slt $rd, $rs, $rt */ + Mips_SLT64 /* 2800 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltiu $rt, $rs, $imm */ + Mips_SLTIU_NM /* 2801 */, MIPS_INS_SLTIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slti $rt, $rs, $imm */ + Mips_SLTI_NM /* 2802 */, MIPS_INS_SLTI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sltu $rd, $rs, $rt */ + Mips_SLTU_NM /* 2803 */, MIPS_INS_SLTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slt $rd, $rs, $rt */ + Mips_SLT_MM /* 2804 */, MIPS_INS_SLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slt $rd, $rs, $rt */ + Mips_SLT_NM /* 2805 */, MIPS_INS_SLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slti $rt, $rs, $imm16 */ + Mips_SLTi /* 2806 */, MIPS_INS_SLTI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slti $rt, $rs, $imm16 */ + Mips_SLTi64 /* 2807 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* slti $rt, $rs, $imm16 */ + Mips_SLTi_MM /* 2808 */, MIPS_INS_SLTI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sltiu $rt, $rs, $imm16 */ + Mips_SLTiu /* 2809 */, MIPS_INS_SLTIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sltiu $rt, $rs, $imm16 */ + Mips_SLTiu64 /* 2810 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltiu $rt, $rs, $imm16 */ + Mips_SLTiu_MM /* 2811 */, MIPS_INS_SLTIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sltu $rd, $rs, $rt */ + Mips_SLTu /* 2812 */, MIPS_INS_SLTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sltu $rd, $rs, $rt */ + Mips_SLTu64 /* 2813 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sltu $rd, $rs, $rt */ + Mips_SLTu_MM /* 2814 */, MIPS_INS_SLTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sne $rd, $rs, $rt */ + Mips_SNE /* 2815 */, MIPS_INS_SNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* snei $rt, $rs, $imm10 */ + Mips_SNEi /* 2816 */, MIPS_INS_SNEI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sov $rd, $rs, $rt */ + Mips_SOV_NM /* 2817 */, MIPS_INS_SOV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* splati.b $wd, $ws[$n] */ + Mips_SPLATI_B /* 2818 */, MIPS_INS_SPLATI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* splati.d $wd, $ws[$n] */ + Mips_SPLATI_D /* 2819 */, MIPS_INS_SPLATI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* splati.h $wd, $ws[$n] */ + Mips_SPLATI_H /* 2820 */, MIPS_INS_SPLATI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* splati.w $wd, $ws[$n] */ + Mips_SPLATI_W /* 2821 */, MIPS_INS_SPLATI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* splat.b $wd, $ws[$rt] */ + Mips_SPLAT_B /* 2822 */, MIPS_INS_SPLAT_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* splat.d $wd, $ws[$rt] */ + Mips_SPLAT_D /* 2823 */, MIPS_INS_SPLAT_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* splat.h $wd, $ws[$rt] */ + Mips_SPLAT_H /* 2824 */, MIPS_INS_SPLAT_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* splat.w $wd, $ws[$rt] */ + Mips_SPLAT_W /* 2825 */, MIPS_INS_SPLAT_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sra $rd, $rt, $shamt */ + Mips_SRA /* 2826 */, MIPS_INS_SRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srai.b $wd, $ws, $m */ + Mips_SRAI_B /* 2827 */, MIPS_INS_SRAI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srai.d $wd, $ws, $m */ + Mips_SRAI_D /* 2828 */, MIPS_INS_SRAI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srai.h $wd, $ws, $m */ + Mips_SRAI_H /* 2829 */, MIPS_INS_SRAI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srai.w $wd, $ws, $m */ + Mips_SRAI_W /* 2830 */, MIPS_INS_SRAI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srari.b $wd, $ws, $m */ + Mips_SRARI_B /* 2831 */, MIPS_INS_SRARI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srari.d $wd, $ws, $m */ + Mips_SRARI_D /* 2832 */, MIPS_INS_SRARI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srari.h $wd, $ws, $m */ + Mips_SRARI_H /* 2833 */, MIPS_INS_SRARI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srari.w $wd, $ws, $m */ + Mips_SRARI_W /* 2834 */, MIPS_INS_SRARI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srar.b $wd, $ws, $wt */ + Mips_SRAR_B /* 2835 */, MIPS_INS_SRAR_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srar.d $wd, $ws, $wt */ + Mips_SRAR_D /* 2836 */, MIPS_INS_SRAR_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srar.h $wd, $ws, $wt */ + Mips_SRAR_H /* 2837 */, MIPS_INS_SRAR_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srar.w $wd, $ws, $wt */ + Mips_SRAR_W /* 2838 */, MIPS_INS_SRAR_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srav $rd, $rt, $rs */ + Mips_SRAV /* 2839 */, MIPS_INS_SRAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srav $rd, $rt, $rs */ + Mips_SRAV_MM /* 2840 */, MIPS_INS_SRAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srav $rd, $rs, $rt */ + Mips_SRAV_NM /* 2841 */, MIPS_INS_SRAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sra.b $wd, $ws, $wt */ + Mips_SRA_B /* 2842 */, MIPS_INS_SRA_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sra.d $wd, $ws, $wt */ + Mips_SRA_D /* 2843 */, MIPS_INS_SRA_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sra.h $wd, $ws, $wt */ + Mips_SRA_H /* 2844 */, MIPS_INS_SRA_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sra $rd, $rt, $shamt */ + Mips_SRA_MM /* 2845 */, MIPS_INS_SRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sra $rt, $rs, $imm */ + Mips_SRA_NM /* 2846 */, MIPS_INS_SRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sra.w $wd, $ws, $wt */ + Mips_SRA_W /* 2847 */, MIPS_INS_SRA_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl $rd, $rt, $shamt */ + Mips_SRL /* 2848 */, MIPS_INS_SRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl16 $rd, $rt, $shamt */ + Mips_SRL16_MM /* 2849 */, MIPS_INS_SRL16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl16 $rd, $rt, $shamt */ + Mips_SRL16_MMR6 /* 2850 */, MIPS_INS_SRL16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl $rt, $rs, $imm */ + Mips_SRL16_NM /* 2851 */, MIPS_INS_SRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srli.b $wd, $ws, $m */ + Mips_SRLI_B /* 2852 */, MIPS_INS_SRLI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srli.d $wd, $ws, $m */ + Mips_SRLI_D /* 2853 */, MIPS_INS_SRLI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srli.h $wd, $ws, $m */ + Mips_SRLI_H /* 2854 */, MIPS_INS_SRLI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srli.w $wd, $ws, $m */ + Mips_SRLI_W /* 2855 */, MIPS_INS_SRLI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlri.b $wd, $ws, $m */ + Mips_SRLRI_B /* 2856 */, MIPS_INS_SRLRI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlri.d $wd, $ws, $m */ + Mips_SRLRI_D /* 2857 */, MIPS_INS_SRLRI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlri.h $wd, $ws, $m */ + Mips_SRLRI_H /* 2858 */, MIPS_INS_SRLRI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlri.w $wd, $ws, $m */ + Mips_SRLRI_W /* 2859 */, MIPS_INS_SRLRI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlr.b $wd, $ws, $wt */ + Mips_SRLR_B /* 2860 */, MIPS_INS_SRLR_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlr.d $wd, $ws, $wt */ + Mips_SRLR_D /* 2861 */, MIPS_INS_SRLR_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlr.h $wd, $ws, $wt */ + Mips_SRLR_H /* 2862 */, MIPS_INS_SRLR_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlr.w $wd, $ws, $wt */ + Mips_SRLR_W /* 2863 */, MIPS_INS_SRLR_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlv $rd, $rt, $rs */ + Mips_SRLV /* 2864 */, MIPS_INS_SRLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlv $rd, $rt, $rs */ + Mips_SRLV_MM /* 2865 */, MIPS_INS_SRLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlv $rd, $rs, $rt */ + Mips_SRLV_NM /* 2866 */, MIPS_INS_SRLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl.b $wd, $ws, $wt */ + Mips_SRL_B /* 2867 */, MIPS_INS_SRL_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl.d $wd, $ws, $wt */ + Mips_SRL_D /* 2868 */, MIPS_INS_SRL_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl.h $wd, $ws, $wt */ + Mips_SRL_H /* 2869 */, MIPS_INS_SRL_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl $rd, $rt, $shamt */ + Mips_SRL_MM /* 2870 */, MIPS_INS_SRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl $rt, $rs, $imm */ + Mips_SRL_NM /* 2871 */, MIPS_INS_SRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl.w $wd, $ws, $wt */ + Mips_SRL_W /* 2872 */, MIPS_INS_SRL_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ssnop */ + Mips_SSNOP /* 2873 */, MIPS_INS_SSNOP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ssnop */ + Mips_SSNOP_MM /* 2874 */, MIPS_INS_SSNOP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ssnop */ + Mips_SSNOP_MMR6 /* 2875 */, MIPS_INS_SSNOP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* st.b $wd, $addr */ + Mips_ST_B /* 2876 */, MIPS_INS_ST_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* st.d $wd, $addr */ + Mips_ST_D /* 2877 */, MIPS_INS_ST_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* st.h $wd, $addr */ + Mips_ST_H /* 2878 */, MIPS_INS_ST_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* st.w $wd, $addr */ + Mips_ST_W /* 2879 */, MIPS_INS_ST_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub $rd, $rs, $rt */ + Mips_SUB /* 2880 */, MIPS_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subqh.ph $rd, $rs, $rt */ + Mips_SUBQH_PH /* 2881 */, MIPS_INS_SUBQH_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subqh.ph $rd, $rs, $rt */ + Mips_SUBQH_PH_MMR2 /* 2882 */, MIPS_INS_SUBQH_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subqh_r.ph $rd, $rs, $rt */ + Mips_SUBQH_R_PH /* 2883 */, MIPS_INS_SUBQH_R_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subqh_r.ph $rd, $rs, $rt */ + Mips_SUBQH_R_PH_MMR2 /* 2884 */, MIPS_INS_SUBQH_R_PH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subqh_r.w $rd, $rs, $rt */ + Mips_SUBQH_R_W /* 2885 */, MIPS_INS_SUBQH_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subqh_r.w $rd, $rs, $rt */ + Mips_SUBQH_R_W_MMR2 /* 2886 */, MIPS_INS_SUBQH_R_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subqh.w $rd, $rs, $rt */ + Mips_SUBQH_W /* 2887 */, MIPS_INS_SUBQH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subqh.w $rd, $rs, $rt */ + Mips_SUBQH_W_MMR2 /* 2888 */, MIPS_INS_SUBQH_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subq.ph $rd, $rs, $rt */ + Mips_SUBQ_PH /* 2889 */, MIPS_INS_SUBQ_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subq.ph $rd, $rs, $rt */ + Mips_SUBQ_PH_MM /* 2890 */, MIPS_INS_SUBQ_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subq_s.ph $rd, $rs, $rt */ + Mips_SUBQ_S_PH /* 2891 */, MIPS_INS_SUBQ_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subq_s.ph $rd, $rs, $rt */ + Mips_SUBQ_S_PH_MM /* 2892 */, MIPS_INS_SUBQ_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subq_s.w $rd, $rs, $rt */ + Mips_SUBQ_S_W /* 2893 */, MIPS_INS_SUBQ_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subq_s.w $rd, $rs, $rt */ + Mips_SUBQ_S_W_MM /* 2894 */, MIPS_INS_SUBQ_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subsus_u.b $wd, $ws, $wt */ + Mips_SUBSUS_U_B /* 2895 */, MIPS_INS_SUBSUS_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subsus_u.d $wd, $ws, $wt */ + Mips_SUBSUS_U_D /* 2896 */, MIPS_INS_SUBSUS_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subsus_u.h $wd, $ws, $wt */ + Mips_SUBSUS_U_H /* 2897 */, MIPS_INS_SUBSUS_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subsus_u.w $wd, $ws, $wt */ + Mips_SUBSUS_U_W /* 2898 */, MIPS_INS_SUBSUS_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subsuu_s.b $wd, $ws, $wt */ + Mips_SUBSUU_S_B /* 2899 */, MIPS_INS_SUBSUU_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subsuu_s.d $wd, $ws, $wt */ + Mips_SUBSUU_S_D /* 2900 */, MIPS_INS_SUBSUU_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subsuu_s.h $wd, $ws, $wt */ + Mips_SUBSUU_S_H /* 2901 */, MIPS_INS_SUBSUU_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subsuu_s.w $wd, $ws, $wt */ + Mips_SUBSUU_S_W /* 2902 */, MIPS_INS_SUBSUU_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subs_s.b $wd, $ws, $wt */ + Mips_SUBS_S_B /* 2903 */, MIPS_INS_SUBS_S_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subs_s.d $wd, $ws, $wt */ + Mips_SUBS_S_D /* 2904 */, MIPS_INS_SUBS_S_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subs_s.h $wd, $ws, $wt */ + Mips_SUBS_S_H /* 2905 */, MIPS_INS_SUBS_S_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subs_s.w $wd, $ws, $wt */ + Mips_SUBS_S_W /* 2906 */, MIPS_INS_SUBS_S_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subs_u.b $wd, $ws, $wt */ + Mips_SUBS_U_B /* 2907 */, MIPS_INS_SUBS_U_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subs_u.d $wd, $ws, $wt */ + Mips_SUBS_U_D /* 2908 */, MIPS_INS_SUBS_U_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subs_u.h $wd, $ws, $wt */ + Mips_SUBS_U_H /* 2909 */, MIPS_INS_SUBS_U_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subs_u.w $wd, $ws, $wt */ + Mips_SUBS_U_W /* 2910 */, MIPS_INS_SUBS_U_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu16 $rd, $rs, $rt */ + Mips_SUBU16_MM /* 2911 */, MIPS_INS_SUBU16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu16 $rd, $rs, $rt */ + Mips_SUBU16_MMR6 /* 2912 */, MIPS_INS_SUBU16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subuh.qb $rd, $rs, $rt */ + Mips_SUBUH_QB /* 2913 */, MIPS_INS_SUBUH_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subuh.qb $rd, $rs, $rt */ + Mips_SUBUH_QB_MMR2 /* 2914 */, MIPS_INS_SUBUH_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subuh_r.qb $rd, $rs, $rt */ + Mips_SUBUH_R_QB /* 2915 */, MIPS_INS_SUBUH_R_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subuh_r.qb $rd, $rs, $rt */ + Mips_SUBUH_R_QB_MMR2 /* 2916 */, MIPS_INS_SUBUH_R_QB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu $rd, $rs, $rt */ + Mips_SUBU_MMR6 /* 2917 */, MIPS_INS_SUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu.ph $rd, $rs, $rt */ + Mips_SUBU_PH /* 2918 */, MIPS_INS_SUBU_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu.ph $rd, $rs, $rt */ + Mips_SUBU_PH_MMR2 /* 2919 */, MIPS_INS_SUBU_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu.qb $rd, $rs, $rt */ + Mips_SUBU_QB /* 2920 */, MIPS_INS_SUBU_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu.qb $rd, $rs, $rt */ + Mips_SUBU_QB_MM /* 2921 */, MIPS_INS_SUBU_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu_s.ph $rd, $rs, $rt */ + Mips_SUBU_S_PH /* 2922 */, MIPS_INS_SUBU_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu_s.ph $rd, $rs, $rt */ + Mips_SUBU_S_PH_MMR2 /* 2923 */, MIPS_INS_SUBU_S_PH, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSPR2, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu_s.qb $rd, $rs, $rt */ + Mips_SUBU_S_QB /* 2924 */, MIPS_INS_SUBU_S_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu_s.qb $rd, $rs, $rt */ + Mips_SUBU_S_QB_MM /* 2925 */, MIPS_INS_SUBU_S_QB, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subvi.b $wd, $ws, $imm */ + Mips_SUBVI_B /* 2926 */, MIPS_INS_SUBVI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subvi.d $wd, $ws, $imm */ + Mips_SUBVI_D /* 2927 */, MIPS_INS_SUBVI_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subvi.h $wd, $ws, $imm */ + Mips_SUBVI_H /* 2928 */, MIPS_INS_SUBVI_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subvi.w $wd, $ws, $imm */ + Mips_SUBVI_W /* 2929 */, MIPS_INS_SUBVI_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subv.b $wd, $ws, $wt */ + Mips_SUBV_B /* 2930 */, MIPS_INS_SUBV_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subv.d $wd, $ws, $wt */ + Mips_SUBV_D /* 2931 */, MIPS_INS_SUBV_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subv.h $wd, $ws, $wt */ + Mips_SUBV_H /* 2932 */, MIPS_INS_SUBV_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subv.w $wd, $ws, $wt */ + Mips_SUBV_W /* 2933 */, MIPS_INS_SUBV_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub $rd, $rs, $rt */ + Mips_SUB_MM /* 2934 */, MIPS_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub $rd, $rs, $rt */ + Mips_SUB_MMR6 /* 2935 */, MIPS_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sub $rd, $rs, $rt */ + Mips_SUB_NM /* 2936 */, MIPS_INS_SUB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu $rd, $rs, $rt */ + Mips_SUBu /* 2937 */, MIPS_INS_SUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu $rd, $rs, $rt */ + Mips_SUBu16_NM /* 2938 */, MIPS_INS_SUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu $rd, $rs, $rt */ + Mips_SUBu_MM /* 2939 */, MIPS_INS_SUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu $rd, $rs, $rt */ + Mips_SUBu_NM /* 2940 */, MIPS_INS_SUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* suxc1 $fs, ${index}(${base}) */ + Mips_SUXC1 /* 2941 */, MIPS_INS_SUXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS5_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* suxc1 $fs, ${index}(${base}) */ + Mips_SUXC164 /* 2942 */, MIPS_INS_SUXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS5_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* suxc1 $fs, ${index}(${base}) */ + Mips_SUXC1_MM /* 2943 */, MIPS_INS_SUXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SW /* 2944 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw16 $rt, $addr */ + Mips_SW16_MM /* 2945 */, MIPS_INS_SW16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw16 $rt, $addr */ + Mips_SW16_MMR6 /* 2946 */, MIPS_INS_SW16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SW16_NM /* 2947 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SW4x4_NM /* 2948 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SW64 /* 2949 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* swc1 $rt, $addr */ + Mips_SWC1 /* 2950 */, MIPS_INS_SWC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swc1 $rt, $addr */ + Mips_SWC1_MM /* 2951 */, MIPS_INS_SWC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swc2 $rt, $addr */ + Mips_SWC2 /* 2952 */, MIPS_INS_SWC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swc2 $rt, $addr */ + Mips_SWC2_MMR6 /* 2953 */, MIPS_INS_SWC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swc2 $rt, $addr */ + Mips_SWC2_R6 /* 2954 */, MIPS_INS_SWC2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swc3 $rt, $addr */ + Mips_SWC3 /* 2955 */, MIPS_INS_SWC3, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTCNMIPS, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SWDSP /* 2956 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_NOTINMIPS16MODE, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SWDSP_MM /* 2957 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swe $rt, $addr */ + Mips_SWE /* 2958 */, MIPS_INS_SWE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swe $rt, $addr */ + Mips_SWE_MM /* 2959 */, MIPS_INS_SWE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SWGP16_NM /* 2960 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SWGP_NM /* 2961 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swl $rt, $addr */ + Mips_SWL /* 2962 */, MIPS_INS_SWL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swl $rt, $addr */ + Mips_SWL64 /* 2963 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* swle $rt, $addr */ + Mips_SWLE /* 2964 */, MIPS_INS_SWLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swle $rt, $addr */ + Mips_SWLE_MM /* 2965 */, MIPS_INS_SWLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swl $rt, $addr */ + Mips_SWL_MM /* 2966 */, MIPS_INS_SWL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swm16 $rt, $addr */ + Mips_SWM16_MM /* 2967 */, MIPS_INS_SWM16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swm16 $rt, $addr */ + Mips_SWM16_MMR6 /* 2968 */, MIPS_INS_SWM16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swm32 $rt, $addr */ + Mips_SWM32_MM /* 2969 */, MIPS_INS_SWM32, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swm $rt, $addr, $rcount */ + Mips_SWM_NM /* 2970 */, MIPS_INS_SWM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swpc $rt, $addr */ + Mips_SWPC_NM /* 2971 */, MIPS_INS_SWPC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swp $rt, $addr */ + Mips_SWP_MM /* 2972 */, MIPS_INS_SWP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swr $rt, $addr */ + Mips_SWR /* 2973 */, MIPS_INS_SWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swr $rt, $addr */ + Mips_SWR64 /* 2974 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* swre $rt, $addr */ + Mips_SWRE /* 2975 */, MIPS_INS_SWRE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swre $rt, $addr */ + Mips_SWRE_MM /* 2976 */, MIPS_INS_SWRE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_HASEVA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swr $rt, $addr */ + Mips_SWR_MM /* 2977 */, MIPS_INS_SWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SWSP16_NM /* 2978 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swsp $rt, $offset */ + Mips_SWSP_MM /* 2979 */, MIPS_INS_SWSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $offset */ + Mips_SWSP_MMR6 /* 2980 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swxc1 $fs, ${index}(${base}) */ + Mips_SWXC1 /* 2981 */, MIPS_INS_SWXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS4_32R2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swxc1 $fs, ${index}(${base}) */ + Mips_SWXC1_MM /* 2982 */, MIPS_INS_SWXC1, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swxs $rt, $addr */ + Mips_SWXS_NM /* 2983 */, MIPS_INS_SWXS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* swx $rt, $addr */ + Mips_SWX_NM /* 2984 */, MIPS_INS_SWX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SW_MM /* 2985 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SW_MMR6 /* 2986 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SW_NM /* 2987 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $rt, $addr */ + Mips_SWs9_NM /* 2988 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sync $stype */ + Mips_SYNC /* 2989 */, MIPS_INS_SYNC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* synci $addr */ + Mips_SYNCI /* 2990 */, MIPS_INS_SYNCI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* synci $addr */ + Mips_SYNCI_MM /* 2991 */, MIPS_INS_SYNCI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* synci $addr */ + Mips_SYNCI_MMR6 /* 2992 */, MIPS_INS_SYNCI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* synci $addr */ + Mips_SYNCI_NM /* 2993 */, MIPS_INS_SYNCI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* synci $addr */ + Mips_SYNCIs9_NM /* 2994 */, MIPS_INS_SYNCI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sync $stype */ + Mips_SYNC_MM /* 2995 */, MIPS_INS_SYNC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sync $stype */ + Mips_SYNC_MMR6 /* 2996 */, MIPS_INS_SYNC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sync $stype */ + Mips_SYNC_NM /* 2997 */, MIPS_INS_SYNC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* syscall $code_ */ + Mips_SYSCALL /* 2998 */, MIPS_INS_SYSCALL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* syscall $imm */ + Mips_SYSCALL16_NM /* 2999 */, MIPS_INS_SYSCALL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* syscall $code_ */ + Mips_SYSCALL_MM /* 3000 */, MIPS_INS_SYSCALL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* syscall $imm */ + Mips_SYSCALL_NM /* 3001 */, MIPS_INS_SYSCALL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* */ + Mips_Save16 /* 3002 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + Mips_SaveX16 /* 3003 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* sb $ry, $addr */ + Mips_SbRxRyOffMemX16 /* 3004 */, MIPS_INS_SB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seb $rx */ + Mips_SebRx16 /* 3005 */, MIPS_INS_SEB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* seh $rx */ + Mips_SehRx16 /* 3006 */, MIPS_INS_SEH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sh $ry, $addr */ + Mips_ShRxRyOffMemX16 /* 3007 */, MIPS_INS_SH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sll $rx, $ry, $sa6 */ + Mips_SllX16 /* 3008 */, MIPS_INS_SLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sllv $rz, $ry */ + Mips_SllvRxRy16 /* 3009 */, MIPS_INS_SLLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slt $rx, $ry */ + Mips_SltRxRy16 /* 3010 */, MIPS_INS_SLT, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slti $rx, $imm8 # 16 bit inst */ + Mips_SltiRxImm16 /* 3011 */, MIPS_INS_SLTI, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* slti $rx, $imm16 */ + Mips_SltiRxImmX16 /* 3012 */, MIPS_INS_SLTI, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sltiu $rx, $imm8 # 16 bit inst */ + Mips_SltiuRxImm16 /* 3013 */, MIPS_INS_SLTIU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sltiu $rx, $imm16 */ + Mips_SltiuRxImmX16 /* 3014 */, MIPS_INS_SLTIU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sltu $rx, $ry */ + Mips_SltuRxRy16 /* 3015 */, MIPS_INS_SLTU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sra $rx, $ry, $sa6 */ + Mips_SraX16 /* 3016 */, MIPS_INS_SRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srav $rz, $ry */ + Mips_SravRxRy16 /* 3017 */, MIPS_INS_SRAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srl $rx, $ry, $sa6 */ + Mips_SrlX16 /* 3018 */, MIPS_INS_SRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* srlv $rz, $ry */ + Mips_SrlvRxRy16 /* 3019 */, MIPS_INS_SRLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* subu $rz, $rx, $ry */ + Mips_SubuRxRyRz16 /* 3020 */, MIPS_INS_SUBU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $ry, $addr */ + Mips_SwRxRyOffMemX16 /* 3021 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* sw $ry, $addr */ + Mips_SwRxSpImmX16 /* 3022 */, MIPS_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* teq $rs, $rt, $code_ */ + Mips_TEQ /* 3023 */, MIPS_INS_TEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* teqi $rs, $imm16 */ + Mips_TEQI /* 3024 */, MIPS_INS_TEQI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* teqi $rs, $imm16 */ + Mips_TEQI_MM /* 3025 */, MIPS_INS_TEQI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* teq $rs, $rt, $code_ */ + Mips_TEQ_MM /* 3026 */, MIPS_INS_TEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* teq $rs, $rt, $imm */ + Mips_TEQ_NM /* 3027 */, MIPS_INS_TEQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tge $rs, $rt, $code_ */ + Mips_TGE /* 3028 */, MIPS_INS_TGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tgei $rs, $imm16 */ + Mips_TGEI /* 3029 */, MIPS_INS_TGEI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tgeiu $rs, $imm16 */ + Mips_TGEIU /* 3030 */, MIPS_INS_TGEIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tgeiu $rs, $imm16 */ + Mips_TGEIU_MM /* 3031 */, MIPS_INS_TGEIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tgei $rs, $imm16 */ + Mips_TGEI_MM /* 3032 */, MIPS_INS_TGEI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tgeu $rs, $rt, $code_ */ + Mips_TGEU /* 3033 */, MIPS_INS_TGEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tgeu $rs, $rt, $code_ */ + Mips_TGEU_MM /* 3034 */, MIPS_INS_TGEU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tge $rs, $rt, $code_ */ + Mips_TGE_MM /* 3035 */, MIPS_INS_TGE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbginv */ + Mips_TLBGINV /* 3036 */, MIPS_INS_TLBGINV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbginvf */ + Mips_TLBGINVF /* 3037 */, MIPS_INS_TLBGINVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbginvf */ + Mips_TLBGINVF_MM /* 3038 */, MIPS_INS_TLBGINVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbginv */ + Mips_TLBGINV_MM /* 3039 */, MIPS_INS_TLBGINV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbgp */ + Mips_TLBGP /* 3040 */, MIPS_INS_TLBGP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbgp */ + Mips_TLBGP_MM /* 3041 */, MIPS_INS_TLBGP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbgr */ + Mips_TLBGR /* 3042 */, MIPS_INS_TLBGR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbgr */ + Mips_TLBGR_MM /* 3043 */, MIPS_INS_TLBGR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbgwi */ + Mips_TLBGWI /* 3044 */, MIPS_INS_TLBGWI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbgwi */ + Mips_TLBGWI_MM /* 3045 */, MIPS_INS_TLBGWI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbgwr */ + Mips_TLBGWR /* 3046 */, MIPS_INS_TLBGWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbgwr */ + Mips_TLBGWR_MM /* 3047 */, MIPS_INS_TLBGWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R5, MIPS_FEATURE_HASVIRT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbinv */ + Mips_TLBINV /* 3048 */, MIPS_INS_TLBINV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbinvf */ + Mips_TLBINVF /* 3049 */, MIPS_INS_TLBINVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_HASEVA, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbinvf */ + Mips_TLBINVF_MMR6 /* 3050 */, MIPS_INS_TLBINVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbinvf */ + Mips_TLBINVF_NM /* 3051 */, MIPS_INS_TLBINVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASTLB, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbinv */ + Mips_TLBINV_MMR6 /* 3052 */, MIPS_INS_TLBINV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbinv */ + Mips_TLBINV_NM /* 3053 */, MIPS_INS_TLBINV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASTLB, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbp */ + Mips_TLBP /* 3054 */, MIPS_INS_TLBP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbp */ + Mips_TLBP_MM /* 3055 */, MIPS_INS_TLBP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbp */ + Mips_TLBP_NM /* 3056 */, MIPS_INS_TLBP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASTLB, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbr */ + Mips_TLBR /* 3057 */, MIPS_INS_TLBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbr */ + Mips_TLBR_MM /* 3058 */, MIPS_INS_TLBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbr */ + Mips_TLBR_NM /* 3059 */, MIPS_INS_TLBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASTLB, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbwi */ + Mips_TLBWI /* 3060 */, MIPS_INS_TLBWI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbwi */ + Mips_TLBWI_MM /* 3061 */, MIPS_INS_TLBWI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbwi */ + Mips_TLBWI_NM /* 3062 */, MIPS_INS_TLBWI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASTLB, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbwr */ + Mips_TLBWR /* 3063 */, MIPS_INS_TLBWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbwr */ + Mips_TLBWR_MM /* 3064 */, MIPS_INS_TLBWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlbwr */ + Mips_TLBWR_NM /* 3065 */, MIPS_INS_TLBWR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASTLB, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlt $rs, $rt, $code_ */ + Mips_TLT /* 3066 */, MIPS_INS_TLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlti $rs, $imm16 */ + Mips_TLTI /* 3067 */, MIPS_INS_TLTI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tltiu $rs, $imm16 */ + Mips_TLTIU_MM /* 3068 */, MIPS_INS_TLTIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlti $rs, $imm16 */ + Mips_TLTI_MM /* 3069 */, MIPS_INS_TLTI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tltu $rs, $rt, $code_ */ + Mips_TLTU /* 3070 */, MIPS_INS_TLTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tltu $rs, $rt, $code_ */ + Mips_TLTU_MM /* 3071 */, MIPS_INS_TLTU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tlt $rs, $rt, $code_ */ + Mips_TLT_MM /* 3072 */, MIPS_INS_TLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tne $rs, $rt, $code_ */ + Mips_TNE /* 3073 */, MIPS_INS_TNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tnei $rs, $imm16 */ + Mips_TNEI /* 3074 */, MIPS_INS_TNEI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tnei $rs, $imm16 */ + Mips_TNEI_MM /* 3075 */, MIPS_INS_TNEI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tne $rs, $rt, $code_ */ + Mips_TNE_MM /* 3076 */, MIPS_INS_TNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tne $rs, $rt, $imm */ + Mips_TNE_NM /* 3077 */, MIPS_INS_TNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.l.d $fd, $fs */ + Mips_TRUNC_L_D64 /* 3078 */, MIPS_INS_TRUNC_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS3_32, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.l.d $ft, $fs */ + Mips_TRUNC_L_D_MMR6 /* 3079 */, MIPS_INS_TRUNC_L_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.l.s $fd, $fs */ + Mips_TRUNC_L_S /* 3080 */, MIPS_INS_TRUNC_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.l.s $ft, $fs */ + Mips_TRUNC_L_S_MMR6 /* 3081 */, MIPS_INS_TRUNC_L_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.d $fd, $fs */ + Mips_TRUNC_W_D32 /* 3082 */, MIPS_INS_TRUNC_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.d $fd, $fs */ + Mips_TRUNC_W_D64 /* 3083 */, MIPS_INS_TRUNC_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_ISFP64BIT, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.d $ft, $fs */ + Mips_TRUNC_W_D_MMR6 /* 3084 */, MIPS_INS_TRUNC_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.d $fd, $fs */ + Mips_TRUNC_W_MM /* 3085 */, MIPS_INS_TRUNC_W_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTFP64BIT, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.s $fd, $fs */ + Mips_TRUNC_W_S /* 3086 */, MIPS_INS_TRUNC_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_ISNOTSOFTFLOAT, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.s $fd, $fs */ + Mips_TRUNC_W_S_MM /* 3087 */, MIPS_INS_TRUNC_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* trunc.w.s $ft, $fs */ + Mips_TRUNC_W_S_MMR6 /* 3088 */, MIPS_INS_TRUNC_W_S, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, MIPS_FEATURE_ISNOTSOFTFLOAT, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* tltiu $rs, $imm16 */ + Mips_TTLTIU /* 3089 */, MIPS_INS_TLTIU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS2, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ualh $rt, $addr */ + Mips_UALH_NM /* 3090 */, MIPS_INS_UALH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ualwm $rt, $addr, $rcount */ + Mips_UALWM_NM /* 3091 */, MIPS_INS_UALWM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* ualw $rt, $addr */ + Mips_UALW_NM /* 3092 */, MIPS_INS_UALW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* uash $rt, $addr */ + Mips_UASH_NM /* 3093 */, MIPS_INS_UASH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* uaswm $rt, $addr, $rcount */ + Mips_UASWM_NM /* 3094 */, MIPS_INS_UASWM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* uasw $rt, $addr */ + Mips_UASW_NM /* 3095 */, MIPS_INS_UASW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* divu $$zero, $rs, $rt */ + Mips_UDIV /* 3096 */, MIPS_INS_DIVU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTMIPS32R6, MIPS_FEATURE_NOTMIPS64R6, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* divu $$zero, $rs, $rt */ + Mips_UDIV_MM /* 3097 */, MIPS_INS_DIVU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* v3mulu $rd, $rs, $rt */ + Mips_V3MULU /* 3098 */, MIPS_INS_V3MULU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* vmm0 $rd, $rs, $rt */ + Mips_VMM0 /* 3099 */, MIPS_INS_VMM0, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* vmulu $rd, $rs, $rt */ + Mips_VMULU /* 3100 */, MIPS_INS_VMULU, + #ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_FEATURE_HASCNMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* vshf.b $wd, $ws, $wt */ + Mips_VSHF_B /* 3101 */, MIPS_INS_VSHF_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* vshf.d $wd, $ws, $wt */ + Mips_VSHF_D /* 3102 */, MIPS_INS_VSHF_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* vshf.h $wd, $ws, $wt */ + Mips_VSHF_H /* 3103 */, MIPS_INS_VSHF_H, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* vshf.w $wd, $ws, $wt */ + Mips_VSHF_W /* 3104 */, MIPS_INS_VSHF_W, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wait */ + Mips_WAIT /* 3105 */, MIPS_INS_WAIT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS3_32, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wait $code_ */ + Mips_WAIT_MM /* 3106 */, MIPS_INS_WAIT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wait $code_ */ + Mips_WAIT_MMR6 /* 3107 */, MIPS_INS_WAIT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wait $cd */ + Mips_WAIT_NM /* 3108 */, MIPS_INS_WAIT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wrdsp $rs, $mask */ + Mips_WRDSP /* 3109 */, MIPS_INS_WRDSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASDSP, MIPS_FEATURE_NOTINMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wrdsp $rt, $mask */ + Mips_WRDSP_MM /* 3110 */, MIPS_INS_WRDSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASDSP, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wrpgpr $rt, $rs */ + Mips_WRPGPR_MMR6 /* 3111 */, MIPS_INS_WRPGPR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wrpgpr $rt, $rs */ + Mips_WRPGPR_NM /* 3112 */, MIPS_INS_WRPGPR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wsbh $rd, $rt */ + Mips_WSBH /* 3113 */, MIPS_INS_WSBH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMIPS32R2, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wsbh $rd, $rt */ + Mips_WSBH_MM /* 3114 */, MIPS_INS_WSBH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* wsbh $rt, $rs */ + Mips_WSBH_MMR6 /* 3115 */, MIPS_INS_WSBH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor $rd, $rs, $rt */ + Mips_XOR /* 3116 */, MIPS_INS_XOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor16 $rt, $rs */ + Mips_XOR16_MM /* 3117 */, MIPS_INS_XOR16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor16 $rt, $rs */ + Mips_XOR16_MMR6 /* 3118 */, MIPS_INS_XOR16, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor $dst, $rs, $rt */ + Mips_XOR16_NM /* 3119 */, MIPS_INS_XOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor $rd, $rs, $rt */ + Mips_XOR64 /* 3120 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* xori.b $wd, $ws, $u8 */ + Mips_XORI_B /* 3121 */, MIPS_INS_XORI_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xori $rt, $rs, $imm16 */ + Mips_XORI_MMR6 /* 3122 */, MIPS_INS_XORI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xori $rt, $rs, $imm */ + Mips_XORI_NM /* 3123 */, MIPS_INS_XORI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor $rd, $rs, $rt */ + Mips_XOR_MM /* 3124 */, MIPS_INS_XOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor $rd, $rs, $rt */ + Mips_XOR_MMR6 /* 3125 */, MIPS_INS_XOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_HASMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor $rd, $rs, $rt */ + Mips_XOR_NM /* 3126 */, MIPS_INS_XOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor.v $wd, $ws, $wt */ + Mips_XOR_V /* 3127 */, MIPS_INS_XOR_V, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMSA, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xori $rt, $rs, $imm16 */ + Mips_XORi /* 3128 */, MIPS_INS_XORI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xori $rt, $rs, $imm16 */ + Mips_XORi64 /* 3129 */, MIPS_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* xori $rt, $rs, $imm16 */ + Mips_XORi_MM /* 3130 */, MIPS_INS_XORI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMICROMIPS, MIPS_FEATURE_NOTMIPS32R6, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* xor $rz, $ry */ + Mips_XorRxRxRy16 /* 3131 */, MIPS_INS_XOR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_INMIPS16MODE, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* yield $rd, $rs */ + Mips_YIELD /* 3132 */, MIPS_INS_YIELD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASSTDENC, MIPS_FEATURE_HASMT, MIPS_FEATURE_NOTINMICROMIPS, MIPS_FEATURE_NOTNANOMIPS, 0 }, 0, 0, {{ 0 }} + + #endif +}, +{ + /* yield $rd, $rs */ + Mips_YIELD_NM /* 3133 */, MIPS_INS_YIELD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASNANOMIPS, MIPS_FEATURE_HASMT, 0 }, 0, 0, {{ 0 }} + + #endif +}, diff --git a/arch/Mips/MipsGenCSMappingInsnName.inc b/arch/Mips/MipsGenCSMappingInsnName.inc new file mode 100644 index 0000000000..112a6aeb6b --- /dev/null +++ b/arch/Mips/MipsGenCSMappingInsnName.inc @@ -0,0 +1,1373 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + + "invalid", // MIPS_INS_INVALID + "abs", // MIPS_INS_ABS + "align", // MIPS_INS_ALIGN + "beql", // MIPS_INS_BEQL + "bge", // MIPS_INS_BGE + "bgel", // MIPS_INS_BGEL + "bgeu", // MIPS_INS_BGEU + "bgeul", // MIPS_INS_BGEUL + "bgt", // MIPS_INS_BGT + "bgtl", // MIPS_INS_BGTL + "bgtu", // MIPS_INS_BGTU + "bgtul", // MIPS_INS_BGTUL + "ble", // MIPS_INS_BLE + "blel", // MIPS_INS_BLEL + "bleu", // MIPS_INS_BLEU + "bleul", // MIPS_INS_BLEUL + "blt", // MIPS_INS_BLT + "bltl", // MIPS_INS_BLTL + "bltu", // MIPS_INS_BLTU + "bltul", // MIPS_INS_BLTUL + "bnel", // MIPS_INS_BNEL + "b", // MIPS_INS_B + "beq", // MIPS_INS_BEQ + "bne", // MIPS_INS_BNE + "cftc1", // MIPS_INS_CFTC1 + "cttc1", // MIPS_INS_CTTC1 + "dmul", // MIPS_INS_DMUL + "dmulo", // MIPS_INS_DMULO + "dmulou", // MIPS_INS_DMULOU + "drol", // MIPS_INS_DROL + "dror", // MIPS_INS_DROR + "ddiv", // MIPS_INS_DDIV + "drem", // MIPS_INS_DREM + "ddivu", // MIPS_INS_DDIVU + "dremu", // MIPS_INS_DREMU + "jal", // MIPS_INS_JAL + "ld", // MIPS_INS_LD + "lwm", // MIPS_INS_LWM + "la", // MIPS_INS_LA + "dla", // MIPS_INS_DLA + "li", // MIPS_INS_LI + "dli", // MIPS_INS_DLI + "li_d", // MIPS_INS_LI_D + "li_s", // MIPS_INS_LI_S + "mftacx", // MIPS_INS_MFTACX + "mftc0", // MIPS_INS_MFTC0 + "mftc1", // MIPS_INS_MFTC1 + "mftdsp", // MIPS_INS_MFTDSP + "mftgpr", // MIPS_INS_MFTGPR + "mfthc1", // MIPS_INS_MFTHC1 + "mfthi", // MIPS_INS_MFTHI + "mftlo", // MIPS_INS_MFTLO + "mttacx", // MIPS_INS_MTTACX + "mttc0", // MIPS_INS_MTTC0 + "mttc1", // MIPS_INS_MTTC1 + "mttdsp", // MIPS_INS_MTTDSP + "mttgpr", // MIPS_INS_MTTGPR + "mtthc1", // MIPS_INS_MTTHC1 + "mtthi", // MIPS_INS_MTTHI + "mttlo", // MIPS_INS_MTTLO + "mul", // MIPS_INS_MUL + "mulo", // MIPS_INS_MULO + "mulou", // MIPS_INS_MULOU + "nor", // MIPS_INS_NOR + "addiu", // MIPS_INS_ADDIU + "andi", // MIPS_INS_ANDI + "subu", // MIPS_INS_SUBU + "trunc_w_d", // MIPS_INS_TRUNC_W_D + "trunc_w_s", // MIPS_INS_TRUNC_W_S + "rol", // MIPS_INS_ROL + "ror", // MIPS_INS_ROR + "s_d", // MIPS_INS_S_D + "sd", // MIPS_INS_SD + "div", // MIPS_INS_DIV + "seq", // MIPS_INS_SEQ + "sge", // MIPS_INS_SGE + "sgeu", // MIPS_INS_SGEU + "sgt", // MIPS_INS_SGT + "sgtu", // MIPS_INS_SGTU + "sle", // MIPS_INS_SLE + "sleu", // MIPS_INS_SLEU + "slt", // MIPS_INS_SLT + "sltu", // MIPS_INS_SLTU + "sne", // MIPS_INS_SNE + "rem", // MIPS_INS_REM + "swm", // MIPS_INS_SWM + "saa", // MIPS_INS_SAA + "saad", // MIPS_INS_SAAD + "divu", // MIPS_INS_DIVU + "remu", // MIPS_INS_REMU + "ulh", // MIPS_INS_ULH + "ulhu", // MIPS_INS_ULHU + "ulw", // MIPS_INS_ULW + "ush", // MIPS_INS_USH + "usw", // MIPS_INS_USW + "absq_s_ph", // MIPS_INS_ABSQ_S_PH + "absq_s_qb", // MIPS_INS_ABSQ_S_QB + "absq_s_w", // MIPS_INS_ABSQ_S_W + "add", // MIPS_INS_ADD + "addiupc", // MIPS_INS_ADDIUPC + "addiur1sp", // MIPS_INS_ADDIUR1SP + "addiur2", // MIPS_INS_ADDIUR2 + "addius5", // MIPS_INS_ADDIUS5 + "addiusp", // MIPS_INS_ADDIUSP + "addqh_ph", // MIPS_INS_ADDQH_PH + "addqh_r_ph", // MIPS_INS_ADDQH_R_PH + "addqh_r_w", // MIPS_INS_ADDQH_R_W + "addqh_w", // MIPS_INS_ADDQH_W + "addq_ph", // MIPS_INS_ADDQ_PH + "addq_s_ph", // MIPS_INS_ADDQ_S_PH + "addq_s_w", // MIPS_INS_ADDQ_S_W + "addr_ps", // MIPS_INS_ADDR_PS + "addsc", // MIPS_INS_ADDSC + "adds_a_b", // MIPS_INS_ADDS_A_B + "adds_a_d", // MIPS_INS_ADDS_A_D + "adds_a_h", // MIPS_INS_ADDS_A_H + "adds_a_w", // MIPS_INS_ADDS_A_W + "adds_s_b", // MIPS_INS_ADDS_S_B + "adds_s_d", // MIPS_INS_ADDS_S_D + "adds_s_h", // MIPS_INS_ADDS_S_H + "adds_s_w", // MIPS_INS_ADDS_S_W + "adds_u_b", // MIPS_INS_ADDS_U_B + "adds_u_d", // MIPS_INS_ADDS_U_D + "adds_u_h", // MIPS_INS_ADDS_U_H + "adds_u_w", // MIPS_INS_ADDS_U_W + "addu16", // MIPS_INS_ADDU16 + "adduh_qb", // MIPS_INS_ADDUH_QB + "adduh_r_qb", // MIPS_INS_ADDUH_R_QB + "addu", // MIPS_INS_ADDU + "addu_ph", // MIPS_INS_ADDU_PH + "addu_qb", // MIPS_INS_ADDU_QB + "addu_s_ph", // MIPS_INS_ADDU_S_PH + "addu_s_qb", // MIPS_INS_ADDU_S_QB + "addvi_b", // MIPS_INS_ADDVI_B + "addvi_d", // MIPS_INS_ADDVI_D + "addvi_h", // MIPS_INS_ADDVI_H + "addvi_w", // MIPS_INS_ADDVI_W + "addv_b", // MIPS_INS_ADDV_B + "addv_d", // MIPS_INS_ADDV_D + "addv_h", // MIPS_INS_ADDV_H + "addv_w", // MIPS_INS_ADDV_W + "addwc", // MIPS_INS_ADDWC + "add_a_b", // MIPS_INS_ADD_A_B + "add_a_d", // MIPS_INS_ADD_A_D + "add_a_h", // MIPS_INS_ADD_A_H + "add_a_w", // MIPS_INS_ADD_A_W + "addi", // MIPS_INS_ADDI + "aluipc", // MIPS_INS_ALUIPC + "and", // MIPS_INS_AND + "and16", // MIPS_INS_AND16 + "andi16", // MIPS_INS_ANDI16 + "andi_b", // MIPS_INS_ANDI_B + "and_v", // MIPS_INS_AND_V + "append", // MIPS_INS_APPEND + "asub_s_b", // MIPS_INS_ASUB_S_B + "asub_s_d", // MIPS_INS_ASUB_S_D + "asub_s_h", // MIPS_INS_ASUB_S_H + "asub_s_w", // MIPS_INS_ASUB_S_W + "asub_u_b", // MIPS_INS_ASUB_U_B + "asub_u_d", // MIPS_INS_ASUB_U_D + "asub_u_h", // MIPS_INS_ASUB_U_H + "asub_u_w", // MIPS_INS_ASUB_U_W + "aui", // MIPS_INS_AUI + "auipc", // MIPS_INS_AUIPC + "aver_s_b", // MIPS_INS_AVER_S_B + "aver_s_d", // MIPS_INS_AVER_S_D + "aver_s_h", // MIPS_INS_AVER_S_H + "aver_s_w", // MIPS_INS_AVER_S_W + "aver_u_b", // MIPS_INS_AVER_U_B + "aver_u_d", // MIPS_INS_AVER_U_D + "aver_u_h", // MIPS_INS_AVER_U_H + "aver_u_w", // MIPS_INS_AVER_U_W + "ave_s_b", // MIPS_INS_AVE_S_B + "ave_s_d", // MIPS_INS_AVE_S_D + "ave_s_h", // MIPS_INS_AVE_S_H + "ave_s_w", // MIPS_INS_AVE_S_W + "ave_u_b", // MIPS_INS_AVE_U_B + "ave_u_d", // MIPS_INS_AVE_U_D + "ave_u_h", // MIPS_INS_AVE_U_H + "ave_u_w", // MIPS_INS_AVE_U_W + "b16", // MIPS_INS_B16 + "baddu", // MIPS_INS_BADDU + "bal", // MIPS_INS_BAL + "balc", // MIPS_INS_BALC + "balign", // MIPS_INS_BALIGN + "balrsc", // MIPS_INS_BALRSC + "bbeqzc", // MIPS_INS_BBEQZC + "bbit0", // MIPS_INS_BBIT0 + "bbit032", // MIPS_INS_BBIT032 + "bbit1", // MIPS_INS_BBIT1 + "bbit132", // MIPS_INS_BBIT132 + "bbnezc", // MIPS_INS_BBNEZC + "bc", // MIPS_INS_BC + "bc16", // MIPS_INS_BC16 + "bc1eqz", // MIPS_INS_BC1EQZ + "bc1eqzc", // MIPS_INS_BC1EQZC + "bc1f", // MIPS_INS_BC1F + "bc1fl", // MIPS_INS_BC1FL + "bc1nez", // MIPS_INS_BC1NEZ + "bc1nezc", // MIPS_INS_BC1NEZC + "bc1t", // MIPS_INS_BC1T + "bc1tl", // MIPS_INS_BC1TL + "bc2eqz", // MIPS_INS_BC2EQZ + "bc2eqzc", // MIPS_INS_BC2EQZC + "bc2nez", // MIPS_INS_BC2NEZ + "bc2nezc", // MIPS_INS_BC2NEZC + "bclri_b", // MIPS_INS_BCLRI_B + "bclri_d", // MIPS_INS_BCLRI_D + "bclri_h", // MIPS_INS_BCLRI_H + "bclri_w", // MIPS_INS_BCLRI_W + "bclr_b", // MIPS_INS_BCLR_B + "bclr_d", // MIPS_INS_BCLR_D + "bclr_h", // MIPS_INS_BCLR_H + "bclr_w", // MIPS_INS_BCLR_W + "beqc", // MIPS_INS_BEQC + "beqic", // MIPS_INS_BEQIC + "beqz16", // MIPS_INS_BEQZ16 + "beqzalc", // MIPS_INS_BEQZALC + "beqzc", // MIPS_INS_BEQZC + "beqzc16", // MIPS_INS_BEQZC16 + "bgec", // MIPS_INS_BGEC + "bgeic", // MIPS_INS_BGEIC + "bgeiuc", // MIPS_INS_BGEIUC + "bgeuc", // MIPS_INS_BGEUC + "bgez", // MIPS_INS_BGEZ + "bgezal", // MIPS_INS_BGEZAL + "bgezalc", // MIPS_INS_BGEZALC + "bgezall", // MIPS_INS_BGEZALL + "bgezals", // MIPS_INS_BGEZALS + "bgezc", // MIPS_INS_BGEZC + "bgezl", // MIPS_INS_BGEZL + "bgtz", // MIPS_INS_BGTZ + "bgtzalc", // MIPS_INS_BGTZALC + "bgtzc", // MIPS_INS_BGTZC + "bgtzl", // MIPS_INS_BGTZL + "binsli_b", // MIPS_INS_BINSLI_B + "binsli_d", // MIPS_INS_BINSLI_D + "binsli_h", // MIPS_INS_BINSLI_H + "binsli_w", // MIPS_INS_BINSLI_W + "binsl_b", // MIPS_INS_BINSL_B + "binsl_d", // MIPS_INS_BINSL_D + "binsl_h", // MIPS_INS_BINSL_H + "binsl_w", // MIPS_INS_BINSL_W + "binsri_b", // MIPS_INS_BINSRI_B + "binsri_d", // MIPS_INS_BINSRI_D + "binsri_h", // MIPS_INS_BINSRI_H + "binsri_w", // MIPS_INS_BINSRI_W + "binsr_b", // MIPS_INS_BINSR_B + "binsr_d", // MIPS_INS_BINSR_D + "binsr_h", // MIPS_INS_BINSR_H + "binsr_w", // MIPS_INS_BINSR_W + "bitrev", // MIPS_INS_BITREV + "bitrevw", // MIPS_INS_BITREVW + "bitswap", // MIPS_INS_BITSWAP + "blez", // MIPS_INS_BLEZ + "blezalc", // MIPS_INS_BLEZALC + "blezc", // MIPS_INS_BLEZC + "blezl", // MIPS_INS_BLEZL + "bltc", // MIPS_INS_BLTC + "bltic", // MIPS_INS_BLTIC + "bltiuc", // MIPS_INS_BLTIUC + "bltuc", // MIPS_INS_BLTUC + "bltz", // MIPS_INS_BLTZ + "bltzal", // MIPS_INS_BLTZAL + "bltzalc", // MIPS_INS_BLTZALC + "bltzall", // MIPS_INS_BLTZALL + "bltzals", // MIPS_INS_BLTZALS + "bltzc", // MIPS_INS_BLTZC + "bltzl", // MIPS_INS_BLTZL + "bmnzi_b", // MIPS_INS_BMNZI_B + "bmnz_v", // MIPS_INS_BMNZ_V + "bmzi_b", // MIPS_INS_BMZI_B + "bmz_v", // MIPS_INS_BMZ_V + "bnec", // MIPS_INS_BNEC + "bnegi_b", // MIPS_INS_BNEGI_B + "bnegi_d", // MIPS_INS_BNEGI_D + "bnegi_h", // MIPS_INS_BNEGI_H + "bnegi_w", // MIPS_INS_BNEGI_W + "bneg_b", // MIPS_INS_BNEG_B + "bneg_d", // MIPS_INS_BNEG_D + "bneg_h", // MIPS_INS_BNEG_H + "bneg_w", // MIPS_INS_BNEG_W + "bneic", // MIPS_INS_BNEIC + "bnez16", // MIPS_INS_BNEZ16 + "bnezalc", // MIPS_INS_BNEZALC + "bnezc", // MIPS_INS_BNEZC + "bnezc16", // MIPS_INS_BNEZC16 + "bnvc", // MIPS_INS_BNVC + "bnz_b", // MIPS_INS_BNZ_B + "bnz_d", // MIPS_INS_BNZ_D + "bnz_h", // MIPS_INS_BNZ_H + "bnz_v", // MIPS_INS_BNZ_V + "bnz_w", // MIPS_INS_BNZ_W + "bovc", // MIPS_INS_BOVC + "bposge32", // MIPS_INS_BPOSGE32 + "bposge32c", // MIPS_INS_BPOSGE32C + "break", // MIPS_INS_BREAK + "break16", // MIPS_INS_BREAK16 + "brsc", // MIPS_INS_BRSC + "bseli_b", // MIPS_INS_BSELI_B + "bsel_v", // MIPS_INS_BSEL_V + "bseti_b", // MIPS_INS_BSETI_B + "bseti_d", // MIPS_INS_BSETI_D + "bseti_h", // MIPS_INS_BSETI_H + "bseti_w", // MIPS_INS_BSETI_W + "bset_b", // MIPS_INS_BSET_B + "bset_d", // MIPS_INS_BSET_D + "bset_h", // MIPS_INS_BSET_H + "bset_w", // MIPS_INS_BSET_W + "byterevw", // MIPS_INS_BYTEREVW + "bz_b", // MIPS_INS_BZ_B + "bz_d", // MIPS_INS_BZ_D + "bz_h", // MIPS_INS_BZ_H + "bz_v", // MIPS_INS_BZ_V + "bz_w", // MIPS_INS_BZ_W + "beqz", // MIPS_INS_BEQZ + "bnez", // MIPS_INS_BNEZ + "bteqz", // MIPS_INS_BTEQZ + "btnez", // MIPS_INS_BTNEZ + "cache", // MIPS_INS_CACHE + "cachee", // MIPS_INS_CACHEE + "ceil_l_d", // MIPS_INS_CEIL_L_D + "ceil_l_s", // MIPS_INS_CEIL_L_S + "ceil_w_d", // MIPS_INS_CEIL_W_D + "ceil_w_s", // MIPS_INS_CEIL_W_S + "ceqi_b", // MIPS_INS_CEQI_B + "ceqi_d", // MIPS_INS_CEQI_D + "ceqi_h", // MIPS_INS_CEQI_H + "ceqi_w", // MIPS_INS_CEQI_W + "ceq_b", // MIPS_INS_CEQ_B + "ceq_d", // MIPS_INS_CEQ_D + "ceq_h", // MIPS_INS_CEQ_H + "ceq_w", // MIPS_INS_CEQ_W + "cfc1", // MIPS_INS_CFC1 + "cfc2", // MIPS_INS_CFC2 + "cfcmsa", // MIPS_INS_CFCMSA + "cins", // MIPS_INS_CINS + "cins32", // MIPS_INS_CINS32 + "class_d", // MIPS_INS_CLASS_D + "class_s", // MIPS_INS_CLASS_S + "clei_s_b", // MIPS_INS_CLEI_S_B + "clei_s_d", // MIPS_INS_CLEI_S_D + "clei_s_h", // MIPS_INS_CLEI_S_H + "clei_s_w", // MIPS_INS_CLEI_S_W + "clei_u_b", // MIPS_INS_CLEI_U_B + "clei_u_d", // MIPS_INS_CLEI_U_D + "clei_u_h", // MIPS_INS_CLEI_U_H + "clei_u_w", // MIPS_INS_CLEI_U_W + "cle_s_b", // MIPS_INS_CLE_S_B + "cle_s_d", // MIPS_INS_CLE_S_D + "cle_s_h", // MIPS_INS_CLE_S_H + "cle_s_w", // MIPS_INS_CLE_S_W + "cle_u_b", // MIPS_INS_CLE_U_B + "cle_u_d", // MIPS_INS_CLE_U_D + "cle_u_h", // MIPS_INS_CLE_U_H + "cle_u_w", // MIPS_INS_CLE_U_W + "clo", // MIPS_INS_CLO + "clti_s_b", // MIPS_INS_CLTI_S_B + "clti_s_d", // MIPS_INS_CLTI_S_D + "clti_s_h", // MIPS_INS_CLTI_S_H + "clti_s_w", // MIPS_INS_CLTI_S_W + "clti_u_b", // MIPS_INS_CLTI_U_B + "clti_u_d", // MIPS_INS_CLTI_U_D + "clti_u_h", // MIPS_INS_CLTI_U_H + "clti_u_w", // MIPS_INS_CLTI_U_W + "clt_s_b", // MIPS_INS_CLT_S_B + "clt_s_d", // MIPS_INS_CLT_S_D + "clt_s_h", // MIPS_INS_CLT_S_H + "clt_s_w", // MIPS_INS_CLT_S_W + "clt_u_b", // MIPS_INS_CLT_U_B + "clt_u_d", // MIPS_INS_CLT_U_D + "clt_u_h", // MIPS_INS_CLT_U_H + "clt_u_w", // MIPS_INS_CLT_U_W + "clz", // MIPS_INS_CLZ + "cmpgdu_eq_qb", // MIPS_INS_CMPGDU_EQ_QB + "cmpgdu_le_qb", // MIPS_INS_CMPGDU_LE_QB + "cmpgdu_lt_qb", // MIPS_INS_CMPGDU_LT_QB + "cmpgu_eq_qb", // MIPS_INS_CMPGU_EQ_QB + "cmpgu_le_qb", // MIPS_INS_CMPGU_LE_QB + "cmpgu_lt_qb", // MIPS_INS_CMPGU_LT_QB + "cmpu_eq_qb", // MIPS_INS_CMPU_EQ_QB + "cmpu_le_qb", // MIPS_INS_CMPU_LE_QB + "cmpu_lt_qb", // MIPS_INS_CMPU_LT_QB + "cmp_af_d", // MIPS_INS_CMP_AF_D + "cmp_af_s", // MIPS_INS_CMP_AF_S + "cmp_eq_d", // MIPS_INS_CMP_EQ_D + "cmp_eq_ph", // MIPS_INS_CMP_EQ_PH + "cmp_eq_s", // MIPS_INS_CMP_EQ_S + "cmp_le_d", // MIPS_INS_CMP_LE_D + "cmp_le_ph", // MIPS_INS_CMP_LE_PH + "cmp_le_s", // MIPS_INS_CMP_LE_S + "cmp_lt_d", // MIPS_INS_CMP_LT_D + "cmp_lt_ph", // MIPS_INS_CMP_LT_PH + "cmp_lt_s", // MIPS_INS_CMP_LT_S + "cmp_saf_d", // MIPS_INS_CMP_SAF_D + "cmp_saf_s", // MIPS_INS_CMP_SAF_S + "cmp_seq_d", // MIPS_INS_CMP_SEQ_D + "cmp_seq_s", // MIPS_INS_CMP_SEQ_S + "cmp_sle_d", // MIPS_INS_CMP_SLE_D + "cmp_sle_s", // MIPS_INS_CMP_SLE_S + "cmp_slt_d", // MIPS_INS_CMP_SLT_D + "cmp_slt_s", // MIPS_INS_CMP_SLT_S + "cmp_sueq_d", // MIPS_INS_CMP_SUEQ_D + "cmp_sueq_s", // MIPS_INS_CMP_SUEQ_S + "cmp_sule_d", // MIPS_INS_CMP_SULE_D + "cmp_sule_s", // MIPS_INS_CMP_SULE_S + "cmp_sult_d", // MIPS_INS_CMP_SULT_D + "cmp_sult_s", // MIPS_INS_CMP_SULT_S + "cmp_sun_d", // MIPS_INS_CMP_SUN_D + "cmp_sun_s", // MIPS_INS_CMP_SUN_S + "cmp_ueq_d", // MIPS_INS_CMP_UEQ_D + "cmp_ueq_s", // MIPS_INS_CMP_UEQ_S + "cmp_ule_d", // MIPS_INS_CMP_ULE_D + "cmp_ule_s", // MIPS_INS_CMP_ULE_S + "cmp_ult_d", // MIPS_INS_CMP_ULT_D + "cmp_ult_s", // MIPS_INS_CMP_ULT_S + "cmp_un_d", // MIPS_INS_CMP_UN_D + "cmp_un_s", // MIPS_INS_CMP_UN_S + "copy_s_b", // MIPS_INS_COPY_S_B + "copy_s_d", // MIPS_INS_COPY_S_D + "copy_s_h", // MIPS_INS_COPY_S_H + "copy_s_w", // MIPS_INS_COPY_S_W + "copy_u_b", // MIPS_INS_COPY_U_B + "copy_u_h", // MIPS_INS_COPY_U_H + "copy_u_w", // MIPS_INS_COPY_U_W + "crc32b", // MIPS_INS_CRC32B + "crc32cb", // MIPS_INS_CRC32CB + "crc32cd", // MIPS_INS_CRC32CD + "crc32ch", // MIPS_INS_CRC32CH + "crc32cw", // MIPS_INS_CRC32CW + "crc32d", // MIPS_INS_CRC32D + "crc32h", // MIPS_INS_CRC32H + "crc32w", // MIPS_INS_CRC32W + "ctc1", // MIPS_INS_CTC1 + "ctc2", // MIPS_INS_CTC2 + "ctcmsa", // MIPS_INS_CTCMSA + "cvt_d_s", // MIPS_INS_CVT_D_S + "cvt_d_w", // MIPS_INS_CVT_D_W + "cvt_d_l", // MIPS_INS_CVT_D_L + "cvt_l_d", // MIPS_INS_CVT_L_D + "cvt_l_s", // MIPS_INS_CVT_L_S + "cvt_ps_pw", // MIPS_INS_CVT_PS_PW + "cvt_ps_s", // MIPS_INS_CVT_PS_S + "cvt_pw_ps", // MIPS_INS_CVT_PW_PS + "cvt_s_d", // MIPS_INS_CVT_S_D + "cvt_s_l", // MIPS_INS_CVT_S_L + "cvt_s_pl", // MIPS_INS_CVT_S_PL + "cvt_s_pu", // MIPS_INS_CVT_S_PU + "cvt_s_w", // MIPS_INS_CVT_S_W + "cvt_w_d", // MIPS_INS_CVT_W_D + "cvt_w_s", // MIPS_INS_CVT_W_S + "c_eq_d", // MIPS_INS_C_EQ_D + "c_eq_s", // MIPS_INS_C_EQ_S + "c_f_d", // MIPS_INS_C_F_D + "c_f_s", // MIPS_INS_C_F_S + "c_le_d", // MIPS_INS_C_LE_D + "c_le_s", // MIPS_INS_C_LE_S + "c_lt_d", // MIPS_INS_C_LT_D + "c_lt_s", // MIPS_INS_C_LT_S + "c_nge_d", // MIPS_INS_C_NGE_D + "c_nge_s", // MIPS_INS_C_NGE_S + "c_ngle_d", // MIPS_INS_C_NGLE_D + "c_ngle_s", // MIPS_INS_C_NGLE_S + "c_ngl_d", // MIPS_INS_C_NGL_D + "c_ngl_s", // MIPS_INS_C_NGL_S + "c_ngt_d", // MIPS_INS_C_NGT_D + "c_ngt_s", // MIPS_INS_C_NGT_S + "c_ole_d", // MIPS_INS_C_OLE_D + "c_ole_s", // MIPS_INS_C_OLE_S + "c_olt_d", // MIPS_INS_C_OLT_D + "c_olt_s", // MIPS_INS_C_OLT_S + "c_seq_d", // MIPS_INS_C_SEQ_D + "c_seq_s", // MIPS_INS_C_SEQ_S + "c_sf_d", // MIPS_INS_C_SF_D + "c_sf_s", // MIPS_INS_C_SF_S + "c_ueq_d", // MIPS_INS_C_UEQ_D + "c_ueq_s", // MIPS_INS_C_UEQ_S + "c_ule_d", // MIPS_INS_C_ULE_D + "c_ule_s", // MIPS_INS_C_ULE_S + "c_ult_d", // MIPS_INS_C_ULT_D + "c_ult_s", // MIPS_INS_C_ULT_S + "c_un_d", // MIPS_INS_C_UN_D + "c_un_s", // MIPS_INS_C_UN_S + "cmp", // MIPS_INS_CMP + "cmpi", // MIPS_INS_CMPI + "dadd", // MIPS_INS_DADD + "daddi", // MIPS_INS_DADDI + "daddiu", // MIPS_INS_DADDIU + "daddu", // MIPS_INS_DADDU + "dahi", // MIPS_INS_DAHI + "dalign", // MIPS_INS_DALIGN + "dati", // MIPS_INS_DATI + "daui", // MIPS_INS_DAUI + "dbitswap", // MIPS_INS_DBITSWAP + "dclo", // MIPS_INS_DCLO + "dclz", // MIPS_INS_DCLZ + "deret", // MIPS_INS_DERET + "dext", // MIPS_INS_DEXT + "dextm", // MIPS_INS_DEXTM + "dextu", // MIPS_INS_DEXTU + "di", // MIPS_INS_DI + "dins", // MIPS_INS_DINS + "dinsm", // MIPS_INS_DINSM + "dinsu", // MIPS_INS_DINSU + "div_s_b", // MIPS_INS_DIV_S_B + "div_s_d", // MIPS_INS_DIV_S_D + "div_s_h", // MIPS_INS_DIV_S_H + "div_s_w", // MIPS_INS_DIV_S_W + "div_u_b", // MIPS_INS_DIV_U_B + "div_u_d", // MIPS_INS_DIV_U_D + "div_u_h", // MIPS_INS_DIV_U_H + "div_u_w", // MIPS_INS_DIV_U_W + "dlsa", // MIPS_INS_DLSA + "dmfc0", // MIPS_INS_DMFC0 + "dmfc1", // MIPS_INS_DMFC1 + "dmfc2", // MIPS_INS_DMFC2 + "dmfgc0", // MIPS_INS_DMFGC0 + "dmod", // MIPS_INS_DMOD + "dmodu", // MIPS_INS_DMODU + "dmt", // MIPS_INS_DMT + "dmtc0", // MIPS_INS_DMTC0 + "dmtc1", // MIPS_INS_DMTC1 + "dmtc2", // MIPS_INS_DMTC2 + "dmtgc0", // MIPS_INS_DMTGC0 + "dmuh", // MIPS_INS_DMUH + "dmuhu", // MIPS_INS_DMUHU + "dmult", // MIPS_INS_DMULT + "dmultu", // MIPS_INS_DMULTU + "dmulu", // MIPS_INS_DMULU + "dotp_s_d", // MIPS_INS_DOTP_S_D + "dotp_s_h", // MIPS_INS_DOTP_S_H + "dotp_s_w", // MIPS_INS_DOTP_S_W + "dotp_u_d", // MIPS_INS_DOTP_U_D + "dotp_u_h", // MIPS_INS_DOTP_U_H + "dotp_u_w", // MIPS_INS_DOTP_U_W + "dpadd_s_d", // MIPS_INS_DPADD_S_D + "dpadd_s_h", // MIPS_INS_DPADD_S_H + "dpadd_s_w", // MIPS_INS_DPADD_S_W + "dpadd_u_d", // MIPS_INS_DPADD_U_D + "dpadd_u_h", // MIPS_INS_DPADD_U_H + "dpadd_u_w", // MIPS_INS_DPADD_U_W + "dpaqx_sa_w_ph", // MIPS_INS_DPAQX_SA_W_PH + "dpaqx_s_w_ph", // MIPS_INS_DPAQX_S_W_PH + "dpaq_sa_l_w", // MIPS_INS_DPAQ_SA_L_W + "dpaq_s_w_ph", // MIPS_INS_DPAQ_S_W_PH + "dpau_h_qbl", // MIPS_INS_DPAU_H_QBL + "dpau_h_qbr", // MIPS_INS_DPAU_H_QBR + "dpax_w_ph", // MIPS_INS_DPAX_W_PH + "dpa_w_ph", // MIPS_INS_DPA_W_PH + "dpop", // MIPS_INS_DPOP + "dpsqx_sa_w_ph", // MIPS_INS_DPSQX_SA_W_PH + "dpsqx_s_w_ph", // MIPS_INS_DPSQX_S_W_PH + "dpsq_sa_l_w", // MIPS_INS_DPSQ_SA_L_W + "dpsq_s_w_ph", // MIPS_INS_DPSQ_S_W_PH + "dpsub_s_d", // MIPS_INS_DPSUB_S_D + "dpsub_s_h", // MIPS_INS_DPSUB_S_H + "dpsub_s_w", // MIPS_INS_DPSUB_S_W + "dpsub_u_d", // MIPS_INS_DPSUB_U_D + "dpsub_u_h", // MIPS_INS_DPSUB_U_H + "dpsub_u_w", // MIPS_INS_DPSUB_U_W + "dpsu_h_qbl", // MIPS_INS_DPSU_H_QBL + "dpsu_h_qbr", // MIPS_INS_DPSU_H_QBR + "dpsx_w_ph", // MIPS_INS_DPSX_W_PH + "dps_w_ph", // MIPS_INS_DPS_W_PH + "drotr", // MIPS_INS_DROTR + "drotr32", // MIPS_INS_DROTR32 + "drotrv", // MIPS_INS_DROTRV + "dsbh", // MIPS_INS_DSBH + "dshd", // MIPS_INS_DSHD + "dsll", // MIPS_INS_DSLL + "dsll32", // MIPS_INS_DSLL32 + "dsllv", // MIPS_INS_DSLLV + "dsra", // MIPS_INS_DSRA + "dsra32", // MIPS_INS_DSRA32 + "dsrav", // MIPS_INS_DSRAV + "dsrl", // MIPS_INS_DSRL + "dsrl32", // MIPS_INS_DSRL32 + "dsrlv", // MIPS_INS_DSRLV + "dsub", // MIPS_INS_DSUB + "dsubu", // MIPS_INS_DSUBU + "dvp", // MIPS_INS_DVP + "dvpe", // MIPS_INS_DVPE + "ehb", // MIPS_INS_EHB + "ei", // MIPS_INS_EI + "emt", // MIPS_INS_EMT + "eret", // MIPS_INS_ERET + "eretnc", // MIPS_INS_ERETNC + "evp", // MIPS_INS_EVP + "evpe", // MIPS_INS_EVPE + "ext", // MIPS_INS_EXT + "extp", // MIPS_INS_EXTP + "extpdp", // MIPS_INS_EXTPDP + "extpdpv", // MIPS_INS_EXTPDPV + "extpv", // MIPS_INS_EXTPV + "extrv_rs_w", // MIPS_INS_EXTRV_RS_W + "extrv_r_w", // MIPS_INS_EXTRV_R_W + "extrv_s_h", // MIPS_INS_EXTRV_S_H + "extrv_w", // MIPS_INS_EXTRV_W + "extr_rs_w", // MIPS_INS_EXTR_RS_W + "extr_r_w", // MIPS_INS_EXTR_R_W + "extr_s_h", // MIPS_INS_EXTR_S_H + "extr_w", // MIPS_INS_EXTR_W + "exts", // MIPS_INS_EXTS + "exts32", // MIPS_INS_EXTS32 + "extw", // MIPS_INS_EXTW + "abs_d", // MIPS_INS_ABS_D + "abs_s", // MIPS_INS_ABS_S + "fadd_d", // MIPS_INS_FADD_D + "add_d", // MIPS_INS_ADD_D + "add_ps", // MIPS_INS_ADD_PS + "add_s", // MIPS_INS_ADD_S + "fadd_w", // MIPS_INS_FADD_W + "fcaf_d", // MIPS_INS_FCAF_D + "fcaf_w", // MIPS_INS_FCAF_W + "fceq_d", // MIPS_INS_FCEQ_D + "fceq_w", // MIPS_INS_FCEQ_W + "fclass_d", // MIPS_INS_FCLASS_D + "fclass_w", // MIPS_INS_FCLASS_W + "fcle_d", // MIPS_INS_FCLE_D + "fcle_w", // MIPS_INS_FCLE_W + "fclt_d", // MIPS_INS_FCLT_D + "fclt_w", // MIPS_INS_FCLT_W + "fcne_d", // MIPS_INS_FCNE_D + "fcne_w", // MIPS_INS_FCNE_W + "fcor_d", // MIPS_INS_FCOR_D + "fcor_w", // MIPS_INS_FCOR_W + "fcueq_d", // MIPS_INS_FCUEQ_D + "fcueq_w", // MIPS_INS_FCUEQ_W + "fcule_d", // MIPS_INS_FCULE_D + "fcule_w", // MIPS_INS_FCULE_W + "fcult_d", // MIPS_INS_FCULT_D + "fcult_w", // MIPS_INS_FCULT_W + "fcune_d", // MIPS_INS_FCUNE_D + "fcune_w", // MIPS_INS_FCUNE_W + "fcun_d", // MIPS_INS_FCUN_D + "fcun_w", // MIPS_INS_FCUN_W + "fdiv_d", // MIPS_INS_FDIV_D + "div_d", // MIPS_INS_DIV_D + "div_s", // MIPS_INS_DIV_S + "fdiv_w", // MIPS_INS_FDIV_W + "fexdo_h", // MIPS_INS_FEXDO_H + "fexdo_w", // MIPS_INS_FEXDO_W + "fexp2_d", // MIPS_INS_FEXP2_D + "fexp2_w", // MIPS_INS_FEXP2_W + "fexupl_d", // MIPS_INS_FEXUPL_D + "fexupl_w", // MIPS_INS_FEXUPL_W + "fexupr_d", // MIPS_INS_FEXUPR_D + "fexupr_w", // MIPS_INS_FEXUPR_W + "ffint_s_d", // MIPS_INS_FFINT_S_D + "ffint_s_w", // MIPS_INS_FFINT_S_W + "ffint_u_d", // MIPS_INS_FFINT_U_D + "ffint_u_w", // MIPS_INS_FFINT_U_W + "ffql_d", // MIPS_INS_FFQL_D + "ffql_w", // MIPS_INS_FFQL_W + "ffqr_d", // MIPS_INS_FFQR_D + "ffqr_w", // MIPS_INS_FFQR_W + "fill_b", // MIPS_INS_FILL_B + "fill_d", // MIPS_INS_FILL_D + "fill_h", // MIPS_INS_FILL_H + "fill_w", // MIPS_INS_FILL_W + "flog2_d", // MIPS_INS_FLOG2_D + "flog2_w", // MIPS_INS_FLOG2_W + "floor_l_d", // MIPS_INS_FLOOR_L_D + "floor_l_s", // MIPS_INS_FLOOR_L_S + "floor_w_d", // MIPS_INS_FLOOR_W_D + "floor_w_s", // MIPS_INS_FLOOR_W_S + "fmadd_d", // MIPS_INS_FMADD_D + "fmadd_w", // MIPS_INS_FMADD_W + "fmax_a_d", // MIPS_INS_FMAX_A_D + "fmax_a_w", // MIPS_INS_FMAX_A_W + "fmax_d", // MIPS_INS_FMAX_D + "fmax_w", // MIPS_INS_FMAX_W + "fmin_a_d", // MIPS_INS_FMIN_A_D + "fmin_a_w", // MIPS_INS_FMIN_A_W + "fmin_d", // MIPS_INS_FMIN_D + "fmin_w", // MIPS_INS_FMIN_W + "mov_d", // MIPS_INS_MOV_D + "mov_s", // MIPS_INS_MOV_S + "fmsub_d", // MIPS_INS_FMSUB_D + "fmsub_w", // MIPS_INS_FMSUB_W + "fmul_d", // MIPS_INS_FMUL_D + "mul_d", // MIPS_INS_MUL_D + "mul_ps", // MIPS_INS_MUL_PS + "mul_s", // MIPS_INS_MUL_S + "fmul_w", // MIPS_INS_FMUL_W + "neg_d", // MIPS_INS_NEG_D + "neg_s", // MIPS_INS_NEG_S + "fork", // MIPS_INS_FORK + "frcp_d", // MIPS_INS_FRCP_D + "frcp_w", // MIPS_INS_FRCP_W + "frint_d", // MIPS_INS_FRINT_D + "frint_w", // MIPS_INS_FRINT_W + "frsqrt_d", // MIPS_INS_FRSQRT_D + "frsqrt_w", // MIPS_INS_FRSQRT_W + "fsaf_d", // MIPS_INS_FSAF_D + "fsaf_w", // MIPS_INS_FSAF_W + "fseq_d", // MIPS_INS_FSEQ_D + "fseq_w", // MIPS_INS_FSEQ_W + "fsle_d", // MIPS_INS_FSLE_D + "fsle_w", // MIPS_INS_FSLE_W + "fslt_d", // MIPS_INS_FSLT_D + "fslt_w", // MIPS_INS_FSLT_W + "fsne_d", // MIPS_INS_FSNE_D + "fsne_w", // MIPS_INS_FSNE_W + "fsor_d", // MIPS_INS_FSOR_D + "fsor_w", // MIPS_INS_FSOR_W + "fsqrt_d", // MIPS_INS_FSQRT_D + "sqrt_d", // MIPS_INS_SQRT_D + "sqrt_s", // MIPS_INS_SQRT_S + "fsqrt_w", // MIPS_INS_FSQRT_W + "fsub_d", // MIPS_INS_FSUB_D + "sub_d", // MIPS_INS_SUB_D + "sub_ps", // MIPS_INS_SUB_PS + "sub_s", // MIPS_INS_SUB_S + "fsub_w", // MIPS_INS_FSUB_W + "fsueq_d", // MIPS_INS_FSUEQ_D + "fsueq_w", // MIPS_INS_FSUEQ_W + "fsule_d", // MIPS_INS_FSULE_D + "fsule_w", // MIPS_INS_FSULE_W + "fsult_d", // MIPS_INS_FSULT_D + "fsult_w", // MIPS_INS_FSULT_W + "fsune_d", // MIPS_INS_FSUNE_D + "fsune_w", // MIPS_INS_FSUNE_W + "fsun_d", // MIPS_INS_FSUN_D + "fsun_w", // MIPS_INS_FSUN_W + "ftint_s_d", // MIPS_INS_FTINT_S_D + "ftint_s_w", // MIPS_INS_FTINT_S_W + "ftint_u_d", // MIPS_INS_FTINT_U_D + "ftint_u_w", // MIPS_INS_FTINT_U_W + "ftq_h", // MIPS_INS_FTQ_H + "ftq_w", // MIPS_INS_FTQ_W + "ftrunc_s_d", // MIPS_INS_FTRUNC_S_D + "ftrunc_s_w", // MIPS_INS_FTRUNC_S_W + "ftrunc_u_d", // MIPS_INS_FTRUNC_U_D + "ftrunc_u_w", // MIPS_INS_FTRUNC_U_W + "ginvi", // MIPS_INS_GINVI + "ginvt", // MIPS_INS_GINVT + "hadd_s_d", // MIPS_INS_HADD_S_D + "hadd_s_h", // MIPS_INS_HADD_S_H + "hadd_s_w", // MIPS_INS_HADD_S_W + "hadd_u_d", // MIPS_INS_HADD_U_D + "hadd_u_h", // MIPS_INS_HADD_U_H + "hadd_u_w", // MIPS_INS_HADD_U_W + "hsub_s_d", // MIPS_INS_HSUB_S_D + "hsub_s_h", // MIPS_INS_HSUB_S_H + "hsub_s_w", // MIPS_INS_HSUB_S_W + "hsub_u_d", // MIPS_INS_HSUB_U_D + "hsub_u_h", // MIPS_INS_HSUB_U_H + "hsub_u_w", // MIPS_INS_HSUB_U_W + "hypcall", // MIPS_INS_HYPCALL + "ilvev_b", // MIPS_INS_ILVEV_B + "ilvev_d", // MIPS_INS_ILVEV_D + "ilvev_h", // MIPS_INS_ILVEV_H + "ilvev_w", // MIPS_INS_ILVEV_W + "ilvl_b", // MIPS_INS_ILVL_B + "ilvl_d", // MIPS_INS_ILVL_D + "ilvl_h", // MIPS_INS_ILVL_H + "ilvl_w", // MIPS_INS_ILVL_W + "ilvod_b", // MIPS_INS_ILVOD_B + "ilvod_d", // MIPS_INS_ILVOD_D + "ilvod_h", // MIPS_INS_ILVOD_H + "ilvod_w", // MIPS_INS_ILVOD_W + "ilvr_b", // MIPS_INS_ILVR_B + "ilvr_d", // MIPS_INS_ILVR_D + "ilvr_h", // MIPS_INS_ILVR_H + "ilvr_w", // MIPS_INS_ILVR_W + "ins", // MIPS_INS_INS + "insert_b", // MIPS_INS_INSERT_B + "insert_d", // MIPS_INS_INSERT_D + "insert_h", // MIPS_INS_INSERT_H + "insert_w", // MIPS_INS_INSERT_W + "insv", // MIPS_INS_INSV + "insve_b", // MIPS_INS_INSVE_B + "insve_d", // MIPS_INS_INSVE_D + "insve_h", // MIPS_INS_INSVE_H + "insve_w", // MIPS_INS_INSVE_W + "j", // MIPS_INS_J + "jalr", // MIPS_INS_JALR + "jalrc", // MIPS_INS_JALRC + "jalrc_hb", // MIPS_INS_JALRC_HB + "jalrs16", // MIPS_INS_JALRS16 + "jalrs", // MIPS_INS_JALRS + "jalr_hb", // MIPS_INS_JALR_HB + "jals", // MIPS_INS_JALS + "jalx", // MIPS_INS_JALX + "jialc", // MIPS_INS_JIALC + "jic", // MIPS_INS_JIC + "jr", // MIPS_INS_JR + "jr16", // MIPS_INS_JR16 + "jraddiusp", // MIPS_INS_JRADDIUSP + "jrc", // MIPS_INS_JRC + "jrc16", // MIPS_INS_JRC16 + "jrcaddiusp", // MIPS_INS_JRCADDIUSP + "jr_hb", // MIPS_INS_JR_HB + "lapc_h", // MIPS_INS_LAPC_H + "lapc_b", // MIPS_INS_LAPC_B + "lb", // MIPS_INS_LB + "lbe", // MIPS_INS_LBE + "lbu16", // MIPS_INS_LBU16 + "lbu", // MIPS_INS_LBU + "lbux", // MIPS_INS_LBUX + "lbx", // MIPS_INS_LBX + "lbue", // MIPS_INS_LBUE + "ldc1", // MIPS_INS_LDC1 + "ldc2", // MIPS_INS_LDC2 + "ldc3", // MIPS_INS_LDC3 + "ldi_b", // MIPS_INS_LDI_B + "ldi_d", // MIPS_INS_LDI_D + "ldi_h", // MIPS_INS_LDI_H + "ldi_w", // MIPS_INS_LDI_W + "ldl", // MIPS_INS_LDL + "ldpc", // MIPS_INS_LDPC + "ldr", // MIPS_INS_LDR + "ldxc1", // MIPS_INS_LDXC1 + "ld_b", // MIPS_INS_LD_B + "ld_d", // MIPS_INS_LD_D + "ld_h", // MIPS_INS_LD_H + "ld_w", // MIPS_INS_LD_W + "lh", // MIPS_INS_LH + "lhe", // MIPS_INS_LHE + "lhu16", // MIPS_INS_LHU16 + "lhu", // MIPS_INS_LHU + "lhuxs", // MIPS_INS_LHUXS + "lhux", // MIPS_INS_LHUX + "lhx", // MIPS_INS_LHX + "lhxs", // MIPS_INS_LHXS + "lhue", // MIPS_INS_LHUE + "li16", // MIPS_INS_LI16 + "ll", // MIPS_INS_LL + "lld", // MIPS_INS_LLD + "lle", // MIPS_INS_LLE + "llwp", // MIPS_INS_LLWP + "lsa", // MIPS_INS_LSA + "lui", // MIPS_INS_LUI + "luxc1", // MIPS_INS_LUXC1 + "lw", // MIPS_INS_LW + "lw16", // MIPS_INS_LW16 + "lwc1", // MIPS_INS_LWC1 + "lwc2", // MIPS_INS_LWC2 + "lwc3", // MIPS_INS_LWC3 + "lwe", // MIPS_INS_LWE + "lwl", // MIPS_INS_LWL + "lwle", // MIPS_INS_LWLE + "lwm16", // MIPS_INS_LWM16 + "lwm32", // MIPS_INS_LWM32 + "lwpc", // MIPS_INS_LWPC + "lwp", // MIPS_INS_LWP + "lwr", // MIPS_INS_LWR + "lwre", // MIPS_INS_LWRE + "lwupc", // MIPS_INS_LWUPC + "lwu", // MIPS_INS_LWU + "lwx", // MIPS_INS_LWX + "lwxc1", // MIPS_INS_LWXC1 + "lwxs", // MIPS_INS_LWXS + "madd", // MIPS_INS_MADD + "maddf_d", // MIPS_INS_MADDF_D + "maddf_s", // MIPS_INS_MADDF_S + "maddr_q_h", // MIPS_INS_MADDR_Q_H + "maddr_q_w", // MIPS_INS_MADDR_Q_W + "maddu", // MIPS_INS_MADDU + "maddv_b", // MIPS_INS_MADDV_B + "maddv_d", // MIPS_INS_MADDV_D + "maddv_h", // MIPS_INS_MADDV_H + "maddv_w", // MIPS_INS_MADDV_W + "madd_d", // MIPS_INS_MADD_D + "madd_q_h", // MIPS_INS_MADD_Q_H + "madd_q_w", // MIPS_INS_MADD_Q_W + "madd_s", // MIPS_INS_MADD_S + "maq_sa_w_phl", // MIPS_INS_MAQ_SA_W_PHL + "maq_sa_w_phr", // MIPS_INS_MAQ_SA_W_PHR + "maq_s_w_phl", // MIPS_INS_MAQ_S_W_PHL + "maq_s_w_phr", // MIPS_INS_MAQ_S_W_PHR + "maxa_d", // MIPS_INS_MAXA_D + "maxa_s", // MIPS_INS_MAXA_S + "maxi_s_b", // MIPS_INS_MAXI_S_B + "maxi_s_d", // MIPS_INS_MAXI_S_D + "maxi_s_h", // MIPS_INS_MAXI_S_H + "maxi_s_w", // MIPS_INS_MAXI_S_W + "maxi_u_b", // MIPS_INS_MAXI_U_B + "maxi_u_d", // MIPS_INS_MAXI_U_D + "maxi_u_h", // MIPS_INS_MAXI_U_H + "maxi_u_w", // MIPS_INS_MAXI_U_W + "max_a_b", // MIPS_INS_MAX_A_B + "max_a_d", // MIPS_INS_MAX_A_D + "max_a_h", // MIPS_INS_MAX_A_H + "max_a_w", // MIPS_INS_MAX_A_W + "max_d", // MIPS_INS_MAX_D + "max_s", // MIPS_INS_MAX_S + "max_s_b", // MIPS_INS_MAX_S_B + "max_s_d", // MIPS_INS_MAX_S_D + "max_s_h", // MIPS_INS_MAX_S_H + "max_s_w", // MIPS_INS_MAX_S_W + "max_u_b", // MIPS_INS_MAX_U_B + "max_u_d", // MIPS_INS_MAX_U_D + "max_u_h", // MIPS_INS_MAX_U_H + "max_u_w", // MIPS_INS_MAX_U_W + "mfc0", // MIPS_INS_MFC0 + "mfc1", // MIPS_INS_MFC1 + "mfc2", // MIPS_INS_MFC2 + "mfgc0", // MIPS_INS_MFGC0 + "mfhc0", // MIPS_INS_MFHC0 + "mfhc1", // MIPS_INS_MFHC1 + "mfhc2", // MIPS_INS_MFHC2 + "mfhgc0", // MIPS_INS_MFHGC0 + "mfhi", // MIPS_INS_MFHI + "mfhi16", // MIPS_INS_MFHI16 + "mflo", // MIPS_INS_MFLO + "mflo16", // MIPS_INS_MFLO16 + "mftr", // MIPS_INS_MFTR + "mina_d", // MIPS_INS_MINA_D + "mina_s", // MIPS_INS_MINA_S + "mini_s_b", // MIPS_INS_MINI_S_B + "mini_s_d", // MIPS_INS_MINI_S_D + "mini_s_h", // MIPS_INS_MINI_S_H + "mini_s_w", // MIPS_INS_MINI_S_W + "mini_u_b", // MIPS_INS_MINI_U_B + "mini_u_d", // MIPS_INS_MINI_U_D + "mini_u_h", // MIPS_INS_MINI_U_H + "mini_u_w", // MIPS_INS_MINI_U_W + "min_a_b", // MIPS_INS_MIN_A_B + "min_a_d", // MIPS_INS_MIN_A_D + "min_a_h", // MIPS_INS_MIN_A_H + "min_a_w", // MIPS_INS_MIN_A_W + "min_d", // MIPS_INS_MIN_D + "min_s", // MIPS_INS_MIN_S + "min_s_b", // MIPS_INS_MIN_S_B + "min_s_d", // MIPS_INS_MIN_S_D + "min_s_h", // MIPS_INS_MIN_S_H + "min_s_w", // MIPS_INS_MIN_S_W + "min_u_b", // MIPS_INS_MIN_U_B + "min_u_d", // MIPS_INS_MIN_U_D + "min_u_h", // MIPS_INS_MIN_U_H + "min_u_w", // MIPS_INS_MIN_U_W + "mod", // MIPS_INS_MOD + "modsub", // MIPS_INS_MODSUB + "modu", // MIPS_INS_MODU + "mod_s_b", // MIPS_INS_MOD_S_B + "mod_s_d", // MIPS_INS_MOD_S_D + "mod_s_h", // MIPS_INS_MOD_S_H + "mod_s_w", // MIPS_INS_MOD_S_W + "mod_u_b", // MIPS_INS_MOD_U_B + "mod_u_d", // MIPS_INS_MOD_U_D + "mod_u_h", // MIPS_INS_MOD_U_H + "mod_u_w", // MIPS_INS_MOD_U_W + "move", // MIPS_INS_MOVE + "move16", // MIPS_INS_MOVE16 + "move_balc", // MIPS_INS_MOVE_BALC + "movep", // MIPS_INS_MOVEP + "move_v", // MIPS_INS_MOVE_V + "movf_d", // MIPS_INS_MOVF_D + "movf", // MIPS_INS_MOVF + "movf_s", // MIPS_INS_MOVF_S + "movn_d", // MIPS_INS_MOVN_D + "movn", // MIPS_INS_MOVN + "movn_s", // MIPS_INS_MOVN_S + "movt_d", // MIPS_INS_MOVT_D + "movt", // MIPS_INS_MOVT + "movt_s", // MIPS_INS_MOVT_S + "movz_d", // MIPS_INS_MOVZ_D + "movz", // MIPS_INS_MOVZ + "movz_s", // MIPS_INS_MOVZ_S + "msub", // MIPS_INS_MSUB + "msubf_d", // MIPS_INS_MSUBF_D + "msubf_s", // MIPS_INS_MSUBF_S + "msubr_q_h", // MIPS_INS_MSUBR_Q_H + "msubr_q_w", // MIPS_INS_MSUBR_Q_W + "msubu", // MIPS_INS_MSUBU + "msubv_b", // MIPS_INS_MSUBV_B + "msubv_d", // MIPS_INS_MSUBV_D + "msubv_h", // MIPS_INS_MSUBV_H + "msubv_w", // MIPS_INS_MSUBV_W + "msub_d", // MIPS_INS_MSUB_D + "msub_q_h", // MIPS_INS_MSUB_Q_H + "msub_q_w", // MIPS_INS_MSUB_Q_W + "msub_s", // MIPS_INS_MSUB_S + "mtc0", // MIPS_INS_MTC0 + "mtc1", // MIPS_INS_MTC1 + "mtc2", // MIPS_INS_MTC2 + "mtgc0", // MIPS_INS_MTGC0 + "mthc0", // MIPS_INS_MTHC0 + "mthc1", // MIPS_INS_MTHC1 + "mthc2", // MIPS_INS_MTHC2 + "mthgc0", // MIPS_INS_MTHGC0 + "mthi", // MIPS_INS_MTHI + "mthlip", // MIPS_INS_MTHLIP + "mtlo", // MIPS_INS_MTLO + "mtm0", // MIPS_INS_MTM0 + "mtm1", // MIPS_INS_MTM1 + "mtm2", // MIPS_INS_MTM2 + "mtp0", // MIPS_INS_MTP0 + "mtp1", // MIPS_INS_MTP1 + "mtp2", // MIPS_INS_MTP2 + "mttr", // MIPS_INS_MTTR + "muh", // MIPS_INS_MUH + "muhu", // MIPS_INS_MUHU + "muleq_s_w_phl", // MIPS_INS_MULEQ_S_W_PHL + "muleq_s_w_phr", // MIPS_INS_MULEQ_S_W_PHR + "muleu_s_ph_qbl", // MIPS_INS_MULEU_S_PH_QBL + "muleu_s_ph_qbr", // MIPS_INS_MULEU_S_PH_QBR + "mulq_rs_ph", // MIPS_INS_MULQ_RS_PH + "mulq_rs_w", // MIPS_INS_MULQ_RS_W + "mulq_s_ph", // MIPS_INS_MULQ_S_PH + "mulq_s_w", // MIPS_INS_MULQ_S_W + "mulr_ps", // MIPS_INS_MULR_PS + "mulr_q_h", // MIPS_INS_MULR_Q_H + "mulr_q_w", // MIPS_INS_MULR_Q_W + "mulsaq_s_w_ph", // MIPS_INS_MULSAQ_S_W_PH + "mulsa_w_ph", // MIPS_INS_MULSA_W_PH + "mult", // MIPS_INS_MULT + "multu", // MIPS_INS_MULTU + "mulu", // MIPS_INS_MULU + "mulv_b", // MIPS_INS_MULV_B + "mulv_d", // MIPS_INS_MULV_D + "mulv_h", // MIPS_INS_MULV_H + "mulv_w", // MIPS_INS_MULV_W + "mul_ph", // MIPS_INS_MUL_PH + "mul_q_h", // MIPS_INS_MUL_Q_H + "mul_q_w", // MIPS_INS_MUL_Q_W + "mul_s_ph", // MIPS_INS_MUL_S_PH + "nloc_b", // MIPS_INS_NLOC_B + "nloc_d", // MIPS_INS_NLOC_D + "nloc_h", // MIPS_INS_NLOC_H + "nloc_w", // MIPS_INS_NLOC_W + "nlzc_b", // MIPS_INS_NLZC_B + "nlzc_d", // MIPS_INS_NLZC_D + "nlzc_h", // MIPS_INS_NLZC_H + "nlzc_w", // MIPS_INS_NLZC_W + "nmadd_d", // MIPS_INS_NMADD_D + "nmadd_s", // MIPS_INS_NMADD_S + "nmsub_d", // MIPS_INS_NMSUB_D + "nmsub_s", // MIPS_INS_NMSUB_S + "nop32", // MIPS_INS_NOP32 + "nop", // MIPS_INS_NOP + "nori_b", // MIPS_INS_NORI_B + "nor_v", // MIPS_INS_NOR_V + "not16", // MIPS_INS_NOT16 + "not", // MIPS_INS_NOT + "neg", // MIPS_INS_NEG + "or", // MIPS_INS_OR + "or16", // MIPS_INS_OR16 + "ori_b", // MIPS_INS_ORI_B + "ori", // MIPS_INS_ORI + "or_v", // MIPS_INS_OR_V + "packrl_ph", // MIPS_INS_PACKRL_PH + "pause", // MIPS_INS_PAUSE + "pckev_b", // MIPS_INS_PCKEV_B + "pckev_d", // MIPS_INS_PCKEV_D + "pckev_h", // MIPS_INS_PCKEV_H + "pckev_w", // MIPS_INS_PCKEV_W + "pckod_b", // MIPS_INS_PCKOD_B + "pckod_d", // MIPS_INS_PCKOD_D + "pckod_h", // MIPS_INS_PCKOD_H + "pckod_w", // MIPS_INS_PCKOD_W + "pcnt_b", // MIPS_INS_PCNT_B + "pcnt_d", // MIPS_INS_PCNT_D + "pcnt_h", // MIPS_INS_PCNT_H + "pcnt_w", // MIPS_INS_PCNT_W + "pick_ph", // MIPS_INS_PICK_PH + "pick_qb", // MIPS_INS_PICK_QB + "pll_ps", // MIPS_INS_PLL_PS + "plu_ps", // MIPS_INS_PLU_PS + "pop", // MIPS_INS_POP + "precequ_ph_qbl", // MIPS_INS_PRECEQU_PH_QBL + "precequ_ph_qbla", // MIPS_INS_PRECEQU_PH_QBLA + "precequ_ph_qbr", // MIPS_INS_PRECEQU_PH_QBR + "precequ_ph_qbra", // MIPS_INS_PRECEQU_PH_QBRA + "preceq_w_phl", // MIPS_INS_PRECEQ_W_PHL + "preceq_w_phr", // MIPS_INS_PRECEQ_W_PHR + "preceu_ph_qbl", // MIPS_INS_PRECEU_PH_QBL + "preceu_ph_qbla", // MIPS_INS_PRECEU_PH_QBLA + "preceu_ph_qbr", // MIPS_INS_PRECEU_PH_QBR + "preceu_ph_qbra", // MIPS_INS_PRECEU_PH_QBRA + "precrqu_s_qb_ph", // MIPS_INS_PRECRQU_S_QB_PH + "precrq_ph_w", // MIPS_INS_PRECRQ_PH_W + "precrq_qb_ph", // MIPS_INS_PRECRQ_QB_PH + "precrq_rs_ph_w", // MIPS_INS_PRECRQ_RS_PH_W + "precr_qb_ph", // MIPS_INS_PRECR_QB_PH + "precr_sra_ph_w", // MIPS_INS_PRECR_SRA_PH_W + "precr_sra_r_ph_w", // MIPS_INS_PRECR_SRA_R_PH_W + "pref", // MIPS_INS_PREF + "prefe", // MIPS_INS_PREFE + "prefx", // MIPS_INS_PREFX + "prepend", // MIPS_INS_PREPEND + "pul_ps", // MIPS_INS_PUL_PS + "puu_ps", // MIPS_INS_PUU_PS + "raddu_w_qb", // MIPS_INS_RADDU_W_QB + "rddsp", // MIPS_INS_RDDSP + "rdhwr", // MIPS_INS_RDHWR + "rdpgpr", // MIPS_INS_RDPGPR + "recip_d", // MIPS_INS_RECIP_D + "recip_s", // MIPS_INS_RECIP_S + "replv_ph", // MIPS_INS_REPLV_PH + "replv_qb", // MIPS_INS_REPLV_QB + "repl_ph", // MIPS_INS_REPL_PH + "repl_qb", // MIPS_INS_REPL_QB + "restore_jrc", // MIPS_INS_RESTORE_JRC + "restore", // MIPS_INS_RESTORE + "rint_d", // MIPS_INS_RINT_D + "rint_s", // MIPS_INS_RINT_S + "rotr", // MIPS_INS_ROTR + "rotrv", // MIPS_INS_ROTRV + "rotx", // MIPS_INS_ROTX + "round_l_d", // MIPS_INS_ROUND_L_D + "round_l_s", // MIPS_INS_ROUND_L_S + "round_w_d", // MIPS_INS_ROUND_W_D + "round_w_s", // MIPS_INS_ROUND_W_S + "rsqrt_d", // MIPS_INS_RSQRT_D + "rsqrt_s", // MIPS_INS_RSQRT_S + "sat_s_b", // MIPS_INS_SAT_S_B + "sat_s_d", // MIPS_INS_SAT_S_D + "sat_s_h", // MIPS_INS_SAT_S_H + "sat_s_w", // MIPS_INS_SAT_S_W + "sat_u_b", // MIPS_INS_SAT_U_B + "sat_u_d", // MIPS_INS_SAT_U_D + "sat_u_h", // MIPS_INS_SAT_U_H + "sat_u_w", // MIPS_INS_SAT_U_W + "save", // MIPS_INS_SAVE + "sb", // MIPS_INS_SB + "sb16", // MIPS_INS_SB16 + "sbe", // MIPS_INS_SBE + "sbx", // MIPS_INS_SBX + "sc", // MIPS_INS_SC + "scd", // MIPS_INS_SCD + "sce", // MIPS_INS_SCE + "scwp", // MIPS_INS_SCWP + "sdbbp", // MIPS_INS_SDBBP + "sdbbp16", // MIPS_INS_SDBBP16 + "sdc1", // MIPS_INS_SDC1 + "sdc2", // MIPS_INS_SDC2 + "sdc3", // MIPS_INS_SDC3 + "sdl", // MIPS_INS_SDL + "sdr", // MIPS_INS_SDR + "sdxc1", // MIPS_INS_SDXC1 + "seb", // MIPS_INS_SEB + "seh", // MIPS_INS_SEH + "seleqz", // MIPS_INS_SELEQZ + "seleqz_d", // MIPS_INS_SELEQZ_D + "seleqz_s", // MIPS_INS_SELEQZ_S + "selnez", // MIPS_INS_SELNEZ + "selnez_d", // MIPS_INS_SELNEZ_D + "selnez_s", // MIPS_INS_SELNEZ_S + "sel_d", // MIPS_INS_SEL_D + "sel_s", // MIPS_INS_SEL_S + "seqi", // MIPS_INS_SEQI + "sh", // MIPS_INS_SH + "sh16", // MIPS_INS_SH16 + "she", // MIPS_INS_SHE + "shf_b", // MIPS_INS_SHF_B + "shf_h", // MIPS_INS_SHF_H + "shf_w", // MIPS_INS_SHF_W + "shilo", // MIPS_INS_SHILO + "shilov", // MIPS_INS_SHILOV + "shllv_ph", // MIPS_INS_SHLLV_PH + "shllv_qb", // MIPS_INS_SHLLV_QB + "shllv_s_ph", // MIPS_INS_SHLLV_S_PH + "shllv_s_w", // MIPS_INS_SHLLV_S_W + "shll_ph", // MIPS_INS_SHLL_PH + "shll_qb", // MIPS_INS_SHLL_QB + "shll_s_ph", // MIPS_INS_SHLL_S_PH + "shll_s_w", // MIPS_INS_SHLL_S_W + "shrav_ph", // MIPS_INS_SHRAV_PH + "shrav_qb", // MIPS_INS_SHRAV_QB + "shrav_r_ph", // MIPS_INS_SHRAV_R_PH + "shrav_r_qb", // MIPS_INS_SHRAV_R_QB + "shrav_r_w", // MIPS_INS_SHRAV_R_W + "shra_ph", // MIPS_INS_SHRA_PH + "shra_qb", // MIPS_INS_SHRA_QB + "shra_r_ph", // MIPS_INS_SHRA_R_PH + "shra_r_qb", // MIPS_INS_SHRA_R_QB + "shra_r_w", // MIPS_INS_SHRA_R_W + "shrlv_ph", // MIPS_INS_SHRLV_PH + "shrlv_qb", // MIPS_INS_SHRLV_QB + "shrl_ph", // MIPS_INS_SHRL_PH + "shrl_qb", // MIPS_INS_SHRL_QB + "shxs", // MIPS_INS_SHXS + "shx", // MIPS_INS_SHX + "sigrie", // MIPS_INS_SIGRIE + "sldi_b", // MIPS_INS_SLDI_B + "sldi_d", // MIPS_INS_SLDI_D + "sldi_h", // MIPS_INS_SLDI_H + "sldi_w", // MIPS_INS_SLDI_W + "sld_b", // MIPS_INS_SLD_B + "sld_d", // MIPS_INS_SLD_D + "sld_h", // MIPS_INS_SLD_H + "sld_w", // MIPS_INS_SLD_W + "sll", // MIPS_INS_SLL + "sll16", // MIPS_INS_SLL16 + "slli_b", // MIPS_INS_SLLI_B + "slli_d", // MIPS_INS_SLLI_D + "slli_h", // MIPS_INS_SLLI_H + "slli_w", // MIPS_INS_SLLI_W + "sllv", // MIPS_INS_SLLV + "sll_b", // MIPS_INS_SLL_B + "sll_d", // MIPS_INS_SLL_D + "sll_h", // MIPS_INS_SLL_H + "sll_w", // MIPS_INS_SLL_W + "sltiu", // MIPS_INS_SLTIU + "slti", // MIPS_INS_SLTI + "snei", // MIPS_INS_SNEI + "sov", // MIPS_INS_SOV + "splati_b", // MIPS_INS_SPLATI_B + "splati_d", // MIPS_INS_SPLATI_D + "splati_h", // MIPS_INS_SPLATI_H + "splati_w", // MIPS_INS_SPLATI_W + "splat_b", // MIPS_INS_SPLAT_B + "splat_d", // MIPS_INS_SPLAT_D + "splat_h", // MIPS_INS_SPLAT_H + "splat_w", // MIPS_INS_SPLAT_W + "sra", // MIPS_INS_SRA + "srai_b", // MIPS_INS_SRAI_B + "srai_d", // MIPS_INS_SRAI_D + "srai_h", // MIPS_INS_SRAI_H + "srai_w", // MIPS_INS_SRAI_W + "srari_b", // MIPS_INS_SRARI_B + "srari_d", // MIPS_INS_SRARI_D + "srari_h", // MIPS_INS_SRARI_H + "srari_w", // MIPS_INS_SRARI_W + "srar_b", // MIPS_INS_SRAR_B + "srar_d", // MIPS_INS_SRAR_D + "srar_h", // MIPS_INS_SRAR_H + "srar_w", // MIPS_INS_SRAR_W + "srav", // MIPS_INS_SRAV + "sra_b", // MIPS_INS_SRA_B + "sra_d", // MIPS_INS_SRA_D + "sra_h", // MIPS_INS_SRA_H + "sra_w", // MIPS_INS_SRA_W + "srl", // MIPS_INS_SRL + "srl16", // MIPS_INS_SRL16 + "srli_b", // MIPS_INS_SRLI_B + "srli_d", // MIPS_INS_SRLI_D + "srli_h", // MIPS_INS_SRLI_H + "srli_w", // MIPS_INS_SRLI_W + "srlri_b", // MIPS_INS_SRLRI_B + "srlri_d", // MIPS_INS_SRLRI_D + "srlri_h", // MIPS_INS_SRLRI_H + "srlri_w", // MIPS_INS_SRLRI_W + "srlr_b", // MIPS_INS_SRLR_B + "srlr_d", // MIPS_INS_SRLR_D + "srlr_h", // MIPS_INS_SRLR_H + "srlr_w", // MIPS_INS_SRLR_W + "srlv", // MIPS_INS_SRLV + "srl_b", // MIPS_INS_SRL_B + "srl_d", // MIPS_INS_SRL_D + "srl_h", // MIPS_INS_SRL_H + "srl_w", // MIPS_INS_SRL_W + "ssnop", // MIPS_INS_SSNOP + "st_b", // MIPS_INS_ST_B + "st_d", // MIPS_INS_ST_D + "st_h", // MIPS_INS_ST_H + "st_w", // MIPS_INS_ST_W + "sub", // MIPS_INS_SUB + "subqh_ph", // MIPS_INS_SUBQH_PH + "subqh_r_ph", // MIPS_INS_SUBQH_R_PH + "subqh_r_w", // MIPS_INS_SUBQH_R_W + "subqh_w", // MIPS_INS_SUBQH_W + "subq_ph", // MIPS_INS_SUBQ_PH + "subq_s_ph", // MIPS_INS_SUBQ_S_PH + "subq_s_w", // MIPS_INS_SUBQ_S_W + "subsus_u_b", // MIPS_INS_SUBSUS_U_B + "subsus_u_d", // MIPS_INS_SUBSUS_U_D + "subsus_u_h", // MIPS_INS_SUBSUS_U_H + "subsus_u_w", // MIPS_INS_SUBSUS_U_W + "subsuu_s_b", // MIPS_INS_SUBSUU_S_B + "subsuu_s_d", // MIPS_INS_SUBSUU_S_D + "subsuu_s_h", // MIPS_INS_SUBSUU_S_H + "subsuu_s_w", // MIPS_INS_SUBSUU_S_W + "subs_s_b", // MIPS_INS_SUBS_S_B + "subs_s_d", // MIPS_INS_SUBS_S_D + "subs_s_h", // MIPS_INS_SUBS_S_H + "subs_s_w", // MIPS_INS_SUBS_S_W + "subs_u_b", // MIPS_INS_SUBS_U_B + "subs_u_d", // MIPS_INS_SUBS_U_D + "subs_u_h", // MIPS_INS_SUBS_U_H + "subs_u_w", // MIPS_INS_SUBS_U_W + "subu16", // MIPS_INS_SUBU16 + "subuh_qb", // MIPS_INS_SUBUH_QB + "subuh_r_qb", // MIPS_INS_SUBUH_R_QB + "subu_ph", // MIPS_INS_SUBU_PH + "subu_qb", // MIPS_INS_SUBU_QB + "subu_s_ph", // MIPS_INS_SUBU_S_PH + "subu_s_qb", // MIPS_INS_SUBU_S_QB + "subvi_b", // MIPS_INS_SUBVI_B + "subvi_d", // MIPS_INS_SUBVI_D + "subvi_h", // MIPS_INS_SUBVI_H + "subvi_w", // MIPS_INS_SUBVI_W + "subv_b", // MIPS_INS_SUBV_B + "subv_d", // MIPS_INS_SUBV_D + "subv_h", // MIPS_INS_SUBV_H + "subv_w", // MIPS_INS_SUBV_W + "suxc1", // MIPS_INS_SUXC1 + "sw", // MIPS_INS_SW + "sw16", // MIPS_INS_SW16 + "swc1", // MIPS_INS_SWC1 + "swc2", // MIPS_INS_SWC2 + "swc3", // MIPS_INS_SWC3 + "swe", // MIPS_INS_SWE + "swl", // MIPS_INS_SWL + "swle", // MIPS_INS_SWLE + "swm16", // MIPS_INS_SWM16 + "swm32", // MIPS_INS_SWM32 + "swpc", // MIPS_INS_SWPC + "swp", // MIPS_INS_SWP + "swr", // MIPS_INS_SWR + "swre", // MIPS_INS_SWRE + "swsp", // MIPS_INS_SWSP + "swxc1", // MIPS_INS_SWXC1 + "swxs", // MIPS_INS_SWXS + "swx", // MIPS_INS_SWX + "sync", // MIPS_INS_SYNC + "synci", // MIPS_INS_SYNCI + "syscall", // MIPS_INS_SYSCALL + "teq", // MIPS_INS_TEQ + "teqi", // MIPS_INS_TEQI + "tge", // MIPS_INS_TGE + "tgei", // MIPS_INS_TGEI + "tgeiu", // MIPS_INS_TGEIU + "tgeu", // MIPS_INS_TGEU + "tlbginv", // MIPS_INS_TLBGINV + "tlbginvf", // MIPS_INS_TLBGINVF + "tlbgp", // MIPS_INS_TLBGP + "tlbgr", // MIPS_INS_TLBGR + "tlbgwi", // MIPS_INS_TLBGWI + "tlbgwr", // MIPS_INS_TLBGWR + "tlbinv", // MIPS_INS_TLBINV + "tlbinvf", // MIPS_INS_TLBINVF + "tlbp", // MIPS_INS_TLBP + "tlbr", // MIPS_INS_TLBR + "tlbwi", // MIPS_INS_TLBWI + "tlbwr", // MIPS_INS_TLBWR + "tlt", // MIPS_INS_TLT + "tlti", // MIPS_INS_TLTI + "tltiu", // MIPS_INS_TLTIU + "tltu", // MIPS_INS_TLTU + "tne", // MIPS_INS_TNE + "tnei", // MIPS_INS_TNEI + "trunc_l_d", // MIPS_INS_TRUNC_L_D + "trunc_l_s", // MIPS_INS_TRUNC_L_S + "ualh", // MIPS_INS_UALH + "ualwm", // MIPS_INS_UALWM + "ualw", // MIPS_INS_UALW + "uash", // MIPS_INS_UASH + "uaswm", // MIPS_INS_UASWM + "uasw", // MIPS_INS_UASW + "v3mulu", // MIPS_INS_V3MULU + "vmm0", // MIPS_INS_VMM0 + "vmulu", // MIPS_INS_VMULU + "vshf_b", // MIPS_INS_VSHF_B + "vshf_d", // MIPS_INS_VSHF_D + "vshf_h", // MIPS_INS_VSHF_H + "vshf_w", // MIPS_INS_VSHF_W + "wait", // MIPS_INS_WAIT + "wrdsp", // MIPS_INS_WRDSP + "wrpgpr", // MIPS_INS_WRPGPR + "wsbh", // MIPS_INS_WSBH + "xor", // MIPS_INS_XOR + "xor16", // MIPS_INS_XOR16 + "xori_b", // MIPS_INS_XORI_B + "xori", // MIPS_INS_XORI + "xor_v", // MIPS_INS_XOR_V + "yield", // MIPS_INS_YIELD diff --git a/arch/Mips/MipsGenCSMappingInsnOp.inc b/arch/Mips/MipsGenCSMappingInsnOp.inc new file mode 100644 index 0000000000..e2a978ebd3 --- /dev/null +++ b/arch/Mips/MipsGenCSMappingInsnOp.inc @@ -0,0 +1,18615 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +{{{ /* MIPS_PHI (0) - MIPS_INS_INVALID - PHINODE */ + 0 +}}}, +{{{ /* MIPS_INLINEASM (1) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INLINEASM_BR (2) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_CFI_INSTRUCTION (3) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_EH_LABEL (4) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_GC_LABEL (5) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ANNOTATION_LABEL (6) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_KILL (7) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_EXTRACT_SUBREG (8) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_SUBREG (9) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_IMPLICIT_DEF (10) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SUBREG_TO_REG (11) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_COPY_TO_REGCLASS (12) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_DBG_VALUE (13) - MIPS_INS_INVALID - DBG_VALUE */ + 0 +}}}, +{{{ /* MIPS_DBG_VALUE_LIST (14) - MIPS_INS_INVALID - DBG_VALUE_LIST */ + 0 +}}}, +{{{ /* MIPS_DBG_INSTR_REF (15) - MIPS_INS_INVALID - DBG_INSTR_REF */ + 0 +}}}, +{{{ /* MIPS_DBG_PHI (16) - MIPS_INS_INVALID - DBG_PHI */ + 0 +}}}, +{{{ /* MIPS_DBG_LABEL (17) - MIPS_INS_INVALID - DBG_LABEL */ + 0 +}}}, +{{{ /* MIPS_REG_SEQUENCE (18) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_COPY (19) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_BUNDLE (20) - MIPS_INS_INVALID - BUNDLE */ + 0 +}}}, +{{{ /* MIPS_LIFETIME_START (21) - MIPS_INS_INVALID - LIFETIME_START */ + 0 +}}}, +{{{ /* MIPS_LIFETIME_END (22) - MIPS_INS_INVALID - LIFETIME_END */ + 0 +}}}, +{{{ /* MIPS_PSEUDO_PROBE (23) - MIPS_INS_INVALID - PSEUDO_PROBE */ + 0 +}}}, +{{{ /* MIPS_ARITH_FENCE (24) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_STACKMAP (25) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_FENTRY_CALL (26) - MIPS_INS_INVALID - # FEntry call */ + 0 +}}}, +{{{ /* MIPS_PATCHPOINT (27) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LOAD_STACK_GUARD (28) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PREALLOCATED_SETUP (29) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PREALLOCATED_ARG (30) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_STATEPOINT (31) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LOCAL_ESCAPE (32) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_FAULTING_OP (33) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PATCHABLE_OP (34) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PATCHABLE_FUNCTION_ENTER (35) - MIPS_INS_INVALID - # XRay Function Enter. */ + 0 +}}}, +{{{ /* MIPS_PATCHABLE_RET (36) - MIPS_INS_INVALID - # XRay Function Patchable RET. */ + 0 +}}}, +{{{ /* MIPS_PATCHABLE_FUNCTION_EXIT (37) - MIPS_INS_INVALID - # XRay Function Exit. */ + 0 +}}}, +{{{ /* MIPS_PATCHABLE_TAIL_CALL (38) - MIPS_INS_INVALID - # XRay Tail Call Exit. */ + 0 +}}}, +{{{ /* MIPS_PATCHABLE_EVENT_CALL (39) - MIPS_INS_INVALID - # XRay Custom Event Log. */ + 0 +}}}, +{{{ /* MIPS_PATCHABLE_TYPED_EVENT_CALL (40) - MIPS_INS_INVALID - # XRay Typed Event Log. */ + 0 +}}}, +{{{ /* MIPS_ICALL_BRANCH_FUNNEL (41) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_MEMBARRIER (42) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_JUMP_TABLE_DEBUG_INFO (43) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ASSERT_SEXT (44) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ASSERT_ZEXT (45) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ASSERT_ALIGN (46) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ADD (47) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SUB (48) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_MUL (49) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SDIV (50) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UDIV (51) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SREM (52) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UREM (53) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SDIVREM (54) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UDIVREM (55) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_AND (56) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_OR (57) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_XOR (58) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_IMPLICIT_DEF (59) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_PHI (60) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FRAME_INDEX (61) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_GLOBAL_VALUE (62) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_CONSTANT_POOL (63) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_EXTRACT (64) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UNMERGE_VALUES (65) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INSERT (66) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_MERGE_VALUES (67) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BUILD_VECTOR (68) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BUILD_VECTOR_TRUNC (69) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_CONCAT_VECTORS (70) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_PTRTOINT (71) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTTOPTR (72) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BITCAST (73) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FREEZE (74) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_CONSTANT_FOLD_BARRIER (75) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTRINSIC_FPTRUNC_ROUND (76) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTRINSIC_TRUNC (77) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTRINSIC_ROUND (78) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTRINSIC_LRINT (79) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTRINSIC_ROUNDEVEN (80) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_READCYCLECOUNTER (81) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_LOAD (82) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SEXTLOAD (83) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ZEXTLOAD (84) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INDEXED_LOAD (85) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INDEXED_SEXTLOAD (86) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INDEXED_ZEXTLOAD (87) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STORE (88) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INDEXED_STORE (89) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMIC_CMPXCHG_WITH_SUCCESS (90) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMIC_CMPXCHG (91) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_XCHG (92) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_ADD (93) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_SUB (94) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_AND (95) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_NAND (96) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_OR (97) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_XOR (98) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_MAX (99) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_MIN (100) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_UMAX (101) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_UMIN (102) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_FADD (103) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_FSUB (104) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_FMAX (105) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_FMIN (106) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_UINC_WRAP (107) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ATOMICRMW_UDEC_WRAP (108) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FENCE (109) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_PREFETCH (110) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BRCOND (111) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BRINDIRECT (112) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INVOKE_REGION_START (113) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTRINSIC (114) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTRINSIC_W_SIDE_EFFECTS (115) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTRINSIC_CONVERGENT (116) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS (117) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ANYEXT (118) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_TRUNC (119) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_CONSTANT (120) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FCONSTANT (121) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VASTART (122) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VAARG (123) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SEXT (124) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SEXT_INREG (125) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ZEXT (126) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SHL (127) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_LSHR (128) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ASHR (129) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FSHL (130) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FSHR (131) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ROTR (132) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ROTL (133) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ICMP (134) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FCMP (135) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SELECT (136) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UADDO (137) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UADDE (138) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_USUBO (139) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_USUBE (140) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SADDO (141) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SADDE (142) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SSUBO (143) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SSUBE (144) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UMULO (145) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SMULO (146) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UMULH (147) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SMULH (148) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UADDSAT (149) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SADDSAT (150) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_USUBSAT (151) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SSUBSAT (152) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_USHLSAT (153) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SSHLSAT (154) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SMULFIX (155) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UMULFIX (156) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SMULFIXSAT (157) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UMULFIXSAT (158) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SDIVFIX (159) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UDIVFIX (160) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SDIVFIXSAT (161) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UDIVFIXSAT (162) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FADD (163) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FSUB (164) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FMUL (165) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FMA (166) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FMAD (167) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FDIV (168) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FREM (169) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FPOW (170) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FPOWI (171) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FEXP (172) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FEXP2 (173) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FEXP10 (174) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FLOG (175) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FLOG2 (176) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FLOG10 (177) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FLDEXP (178) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FFREXP (179) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FNEG (180) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FPEXT (181) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FPTRUNC (182) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FPTOSI (183) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FPTOUI (184) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SITOFP (185) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UITOFP (186) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FABS (187) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FCOPYSIGN (188) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_IS_FPCLASS (189) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FCANONICALIZE (190) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FMINNUM (191) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FMAXNUM (192) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FMINNUM_IEEE (193) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FMAXNUM_IEEE (194) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FMINIMUM (195) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FMAXIMUM (196) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_GET_FPENV (197) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SET_FPENV (198) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_RESET_FPENV (199) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_GET_FPMODE (200) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SET_FPMODE (201) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_RESET_FPMODE (202) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_PTR_ADD (203) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_PTRMASK (204) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SMIN (205) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SMAX (206) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UMIN (207) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UMAX (208) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ABS (209) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_LROUND (210) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_LLROUND (211) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BR (212) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BRJT (213) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_INSERT_VECTOR_ELT (214) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_EXTRACT_VECTOR_ELT (215) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SHUFFLE_VECTOR (216) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_CTTZ (217) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_CTTZ_ZERO_UNDEF (218) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_CTLZ (219) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_CTLZ_ZERO_UNDEF (220) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_CTPOP (221) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BSWAP (222) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BITREVERSE (223) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FCEIL (224) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FCOS (225) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FSIN (226) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FSQRT (227) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FFLOOR (228) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FRINT (229) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_FNEARBYINT (230) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_ADDRSPACE_CAST (231) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BLOCK_ADDR (232) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_JUMP_TABLE (233) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_DYN_STACKALLOC (234) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STACKSAVE (235) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STACKRESTORE (236) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STRICT_FADD (237) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STRICT_FSUB (238) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STRICT_FMUL (239) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STRICT_FDIV (240) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STRICT_FREM (241) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STRICT_FMA (242) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STRICT_FSQRT (243) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_STRICT_FLDEXP (244) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_READ_REGISTER (245) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_WRITE_REGISTER (246) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_MEMCPY (247) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_MEMCPY_INLINE (248) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_MEMMOVE (249) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_MEMSET (250) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_BZERO (251) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_SEQ_FADD (252) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_SEQ_FMUL (253) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_FADD (254) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_FMUL (255) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_FMAX (256) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_FMIN (257) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_FMAXIMUM (258) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_FMINIMUM (259) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_ADD (260) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_MUL (261) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_AND (262) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_OR (263) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_XOR (264) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_SMAX (265) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_SMIN (266) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_UMAX (267) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_VECREDUCE_UMIN (268) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_SBFX (269) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_G_UBFX (270) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_ABSMacro (271) - MIPS_INS_ABS - abs $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{{{ /* MIPS_ADJCALLSTACKDOWN (272) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ADJCALLSTACKDOWN_NM (273) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ADJCALLSTACKUP (274) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ADJCALLSTACKUP_NM (275) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_ALIGN_NM (276) - MIPS_INS_ALIGN - align $rd, $rs, $rt, $bp */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* bp */ + { 0 } +}}, +{{{ /* MIPS_AND_V_D_PSEUDO (277) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_AND_V_H_PSEUDO (278) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_AND_V_W_PSEUDO (279) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_CMP_SWAP_I16 (280) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_CMP_SWAP_I16_POSTRA (281) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_CMP_SWAP_I32 (282) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_CMP_SWAP_I32_POSTRA (283) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_CMP_SWAP_I64 (284) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_CMP_SWAP_I64_POSTRA (285) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_CMP_SWAP_I8 (286) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_CMP_SWAP_I8_POSTRA (287) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_ADD_I16 (288) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_ADD_I16_POSTRA (289) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_ADD_I32 (290) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_ADD_I32_POSTRA (291) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_ADD_I64 (292) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_ADD_I64_POSTRA (293) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_ADD_I8 (294) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_ADD_I8_POSTRA (295) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_AND_I16 (296) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_AND_I16_POSTRA (297) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_AND_I32 (298) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_AND_I32_POSTRA (299) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_AND_I64 (300) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_AND_I64_POSTRA (301) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_AND_I8 (302) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_AND_I8_POSTRA (303) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MAX_I16 (304) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MAX_I16_POSTRA (305) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MAX_I32 (306) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MAX_I32_POSTRA (307) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MAX_I64 (308) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MAX_I64_POSTRA (309) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MAX_I8 (310) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MAX_I8_POSTRA (311) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MIN_I16 (312) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MIN_I16_POSTRA (313) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MIN_I32 (314) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MIN_I32_POSTRA (315) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MIN_I64 (316) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MIN_I64_POSTRA (317) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MIN_I8 (318) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_MIN_I8_POSTRA (319) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_NAND_I16 (320) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_NAND_I16_POSTRA (321) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_NAND_I32 (322) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_NAND_I32_POSTRA (323) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_NAND_I64 (324) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_NAND_I64_POSTRA (325) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_NAND_I8 (326) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_NAND_I8_POSTRA (327) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_OR_I16 (328) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_OR_I16_POSTRA (329) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_OR_I32 (330) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_OR_I32_POSTRA (331) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_OR_I64 (332) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_OR_I64_POSTRA (333) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_OR_I8 (334) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_OR_I8_POSTRA (335) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_SUB_I16 (336) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_SUB_I16_POSTRA (337) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_SUB_I32 (338) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_SUB_I32_POSTRA (339) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_SUB_I64 (340) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_SUB_I64_POSTRA (341) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_SUB_I8 (342) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_SUB_I8_POSTRA (343) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMAX_I16 (344) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMAX_I16_POSTRA (345) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMAX_I32 (346) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMAX_I32_POSTRA (347) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMAX_I64 (348) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMAX_I64_POSTRA (349) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMAX_I8 (350) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMAX_I8_POSTRA (351) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMIN_I16 (352) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMIN_I16_POSTRA (353) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMIN_I32 (354) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMIN_I32_POSTRA (355) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMIN_I64 (356) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMIN_I64_POSTRA (357) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMIN_I8 (358) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_UMIN_I8_POSTRA (359) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_XOR_I16 (360) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_XOR_I16_POSTRA (361) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_XOR_I32 (362) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_XOR_I32_POSTRA (363) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_XOR_I64 (364) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_XOR_I64_POSTRA (365) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_XOR_I8 (366) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_LOAD_XOR_I8_POSTRA (367) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_SWAP_I16 (368) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_SWAP_I16_POSTRA (369) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_SWAP_I32 (370) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_SWAP_I32_POSTRA (371) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_SWAP_I64 (372) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_SWAP_I64_POSTRA (373) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_SWAP_I8 (374) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ATOMIC_SWAP_I8_POSTRA (375) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_B (376) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_BAL_BR (377) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_BAL_BR_MM (378) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_BEQLImmMacro (379) - MIPS_INS_BEQL - beql $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGE (380) - MIPS_INS_BGE - bge $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEImmMacro (381) - MIPS_INS_BGE - bge $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEL (382) - MIPS_INS_BGEL - bgel $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGELImmMacro (383) - MIPS_INS_BGEL - bgel $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEU (384) - MIPS_INS_BGEU - bgeu $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEUImmMacro (385) - MIPS_INS_BGEU - bgeu $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEUL (386) - MIPS_INS_BGEUL - bgeul $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEULImmMacro (387) - MIPS_INS_BGEUL - bgeul $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGT (388) - MIPS_INS_BGT - bgt $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTImmMacro (389) - MIPS_INS_BGT - bgt $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTL (390) - MIPS_INS_BGTL - bgtl $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTLImmMacro (391) - MIPS_INS_BGTL - bgtl $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTU (392) - MIPS_INS_BGTU - bgtu $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTUImmMacro (393) - MIPS_INS_BGTU - bgtu $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTUL (394) - MIPS_INS_BGTUL - bgtul $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTULImmMacro (395) - MIPS_INS_BGTUL - bgtul $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLE (396) - MIPS_INS_BLE - ble $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEImmMacro (397) - MIPS_INS_BLE - ble $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEL (398) - MIPS_INS_BLEL - blel $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLELImmMacro (399) - MIPS_INS_BLEL - blel $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEU (400) - MIPS_INS_BLEU - bleu $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEUImmMacro (401) - MIPS_INS_BLEU - bleu $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEUL (402) - MIPS_INS_BLEUL - bleul $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEULImmMacro (403) - MIPS_INS_BLEUL - bleul $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLT (404) - MIPS_INS_BLT - blt $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTImmMacro (405) - MIPS_INS_BLT - blt $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTL (406) - MIPS_INS_BLTL - bltl $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTLImmMacro (407) - MIPS_INS_BLTL - bltl $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTU (408) - MIPS_INS_BLTU - bltu $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTUImmMacro (409) - MIPS_INS_BLTU - bltu $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTUL (410) - MIPS_INS_BLTUL - bltul $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTULImmMacro (411) - MIPS_INS_BLTUL - bltul $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNELImmMacro (412) - MIPS_INS_BNEL - bnel $rs, $imm, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{{{ /* MIPS_BPOSGE32_PSEUDO (413) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_BSEL_D_PSEUDO (414) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_BSEL_FD_PSEUDO (415) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_BSEL_FW_PSEUDO (416) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_BSEL_H_PSEUDO (417) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_BSEL_W_PSEUDO (418) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_B_MM (419) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_B_MMR6_Pseudo (420) - MIPS_INS_B - b $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_B_MM_Pseudo (421) - MIPS_INS_B - b $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BeqImm (422) - MIPS_INS_BEQ - beq $rt, $imm64, $offset */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BneImm (423) - MIPS_INS_BNE - bne $rt, $imm64, $offset */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{{{ /* MIPS_BteqzT8CmpX16 (424) - MIPS_INS_INVALID - cmp $rx, $ry + bteqz $imm */ + 0 +}}}, +{{{ /* MIPS_BteqzT8CmpiX16 (425) - MIPS_INS_INVALID - cmpi $rx, $imm + bteqz $targ */ + 0 +}}}, +{{{ /* MIPS_BteqzT8SltX16 (426) - MIPS_INS_INVALID - slt $rx, $ry + bteqz $imm */ + 0 +}}}, +{{{ /* MIPS_BteqzT8SltiX16 (427) - MIPS_INS_INVALID - slti $rx, $imm + bteqz $targ */ + 0 +}}}, +{{{ /* MIPS_BteqzT8SltiuX16 (428) - MIPS_INS_INVALID - sltiu $rx, $imm + bteqz $targ */ + 0 +}}}, +{{{ /* MIPS_BteqzT8SltuX16 (429) - MIPS_INS_INVALID - sltu $rx, $ry + bteqz $imm */ + 0 +}}}, +{{{ /* MIPS_BtnezT8CmpX16 (430) - MIPS_INS_INVALID - cmp $rx, $ry + btnez $imm */ + 0 +}}}, +{{{ /* MIPS_BtnezT8CmpiX16 (431) - MIPS_INS_INVALID - cmpi $rx, $imm + btnez $targ */ + 0 +}}}, +{{{ /* MIPS_BtnezT8SltX16 (432) - MIPS_INS_INVALID - slt $rx, $ry + btnez $imm */ + 0 +}}}, +{{{ /* MIPS_BtnezT8SltiX16 (433) - MIPS_INS_INVALID - slti $rx, $imm + btnez $targ */ + 0 +}}}, +{{{ /* MIPS_BtnezT8SltiuX16 (434) - MIPS_INS_INVALID - sltiu $rx, $imm + btnez $targ */ + 0 +}}}, +{{{ /* MIPS_BtnezT8SltuX16 (435) - MIPS_INS_INVALID - sltu $rx, $ry + btnez $imm */ + 0 +}}}, +{{{ /* MIPS_BuildPairF64 (436) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_BuildPairF64_64 (437) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_CFTC1 (438) - MIPS_INS_CFTC1 - cftc1 $rt, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{{{ /* MIPS_CONSTPOOL_ENTRY (439) - MIPS_INS_INVALID - foo */ + 0 +}}}, +{{{ /* MIPS_COPY_FD_PSEUDO (440) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_COPY_FW_PSEUDO (441) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_CTTC1 (442) - MIPS_INS_CTTC1 - cttc1 $rt, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_Constant32 (443) - MIPS_INS_INVALID - .word $imm */ + 0 +}}}, +{ /* MIPS_DMULImmMacro (444) - MIPS_INS_DMUL - dmul $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DMULMacro (445) - MIPS_INS_DMUL - dmul $rs, $rt, $rd */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_DMULOMacro (446) - MIPS_INS_DMULO - dmulo $rs, $rt, $rd */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_DMULOUMacro (447) - MIPS_INS_DMULOU - dmulou $rs, $rt, $rd */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_DROL (448) - MIPS_INS_DROL - drol $rs, $rt, $rd */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_DROLImm (449) - MIPS_INS_DROL - drol $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DROR (450) - MIPS_INS_DROR - dror $rs, $rt, $rd */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_DRORImm (451) - MIPS_INS_DROR - dror $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DSDivIMacro (452) - MIPS_INS_DDIV - ddiv $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DSDivMacro (453) - MIPS_INS_DDIV - ddiv $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DSRemIMacro (454) - MIPS_INS_DREM - drem $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DSRemMacro (455) - MIPS_INS_DREM - drem $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DUDivIMacro (456) - MIPS_INS_DDIVU - ddivu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DUDivMacro (457) - MIPS_INS_DDIVU - ddivu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DURemIMacro (458) - MIPS_INS_DREMU - dremu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DURemMacro (459) - MIPS_INS_DREMU - dremu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_ERet (460) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ExtractElementF64 (461) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ExtractElementF64_64 (462) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_FABS_D (463) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_FABS_W (464) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_FEXP2_D_1_PSEUDO (465) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_FEXP2_W_1_PSEUDO (466) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_FILL_FD_PSEUDO (467) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_FILL_FW_PSEUDO (468) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_GotPrologue16 (469) - MIPS_INS_INVALID - li $rh, $immHi + addiu $rl, $$pc, $immLo + */ + 0 +}}}, +{{{ /* MIPS_INSERT_B_VIDX64_PSEUDO (470) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_B_VIDX_PSEUDO (471) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_D_VIDX64_PSEUDO (472) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_D_VIDX_PSEUDO (473) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_FD_PSEUDO (474) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_FD_VIDX64_PSEUDO (475) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_FD_VIDX_PSEUDO (476) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_FW_PSEUDO (477) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_FW_VIDX64_PSEUDO (478) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_FW_VIDX_PSEUDO (479) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_H_VIDX64_PSEUDO (480) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_H_VIDX_PSEUDO (481) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_W_VIDX64_PSEUDO (482) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_INSERT_W_VIDX_PSEUDO (483) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_JALR64Pseudo (484) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_JALRCPseudo (485) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_JALRHB64Pseudo (486) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_JALRHBPseudo (487) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_JALRPseudo (488) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_JAL_MMR6 (489) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_JalOneReg (490) - MIPS_INS_JAL - jal $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JalTwoReg (491) - MIPS_INS_JAL - jal $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_LDMacro (492) - MIPS_INS_LD - ld $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_LDR_D (493) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LDR_W (494) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LD_F16 (495) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LOAD_ACC128 (496) - MIPS_INS_INVALID - $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_LOAD_ACC64 (497) - MIPS_INS_INVALID - $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_LOAD_ACC64DSP (498) - MIPS_INS_INVALID - $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_LOAD_CCOND_DSP (499) - MIPS_INS_INVALID - load_ccond_dsp $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_LONG_BRANCH_ADDiu (500) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LONG_BRANCH_ADDiu2Op (501) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LONG_BRANCH_DADDiu (502) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LONG_BRANCH_DADDiu2Op (503) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LONG_BRANCH_LUi (504) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LONG_BRANCH_LUi2Op (505) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LONG_BRANCH_LUi2Op_64 (506) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_LWM_MM (507) - MIPS_INS_LWM - lwm $rt, $addr */ +{ + { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_LoadAddrImm32 (508) - MIPS_INS_LA - la $rt, $imm32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm32 */ + { 0 } +}}, +{ /* MIPS_LoadAddrImm64 (509) - MIPS_INS_DLA - dla $rt, $imm64 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm64 */ + { 0 } +}}, +{ /* MIPS_LoadAddrReg32 (510) - MIPS_INS_LA - la $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LoadAddrReg64 (511) - MIPS_INS_DLA - dla $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LoadImm32 (512) - MIPS_INS_LI - li $rt, $imm32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm32 */ + { 0 } +}}, +{ /* MIPS_LoadImm64 (513) - MIPS_INS_DLI - dli $rt, $imm64 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm64 */ + { 0 } +}}, +{ /* MIPS_LoadImmDoubleFGR (514) - MIPS_INS_LI_D - li.d $rd, $fpimm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* fpimm */ + { 0 } +}}, +{ /* MIPS_LoadImmDoubleFGR_32 (515) - MIPS_INS_LI_D - li.d $rd, $fpimm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* fpimm */ + { 0 } +}}, +{ /* MIPS_LoadImmDoubleGPR (516) - MIPS_INS_LI_D - li.d $rd, $fpimm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* fpimm */ + { 0 } +}}, +{ /* MIPS_LoadImmSingleFGR (517) - MIPS_INS_LI_S - li.s $rd, $fpimm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* fpimm */ + { 0 } +}}, +{ /* MIPS_LoadImmSingleGPR (518) - MIPS_INS_LI_S - li.s $rd, $fpimm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* fpimm */ + { 0 } +}}, +{{{ /* MIPS_LoadJumpTableOffset (519) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_LwConstant32 (520) - MIPS_INS_INVALID - lw $rx, 1f + b 2f + .align 2 +1: .word $imm +2: */ + 0 +}}}, +{ /* MIPS_MFTACX (521) - MIPS_INS_MFTACX - mftacx $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{ /* MIPS_MFTACX_NM (522) - MIPS_INS_MFTACX - mftacx $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{ /* MIPS_MFTC0 (523) - MIPS_INS_MFTC0 - mftc0 $rd, $rt, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFTC0_NM (524) - MIPS_INS_MFTC0 - mftc0 $rd, $rt, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFTC1 (525) - MIPS_INS_MFTC1 - mftc1 $rt, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MFTDSP (526) - MIPS_INS_MFTDSP - mftdsp $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MFTDSP_NM (527) - MIPS_INS_MFTDSP - mftdsp $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MFTGPR (528) - MIPS_INS_MFTGPR - mftgpr $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFTGPR_NM (529) - MIPS_INS_MFTGPR - mftgpr $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFTHC1 (530) - MIPS_INS_MFTHC1 - mfthc1 $rt, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MFTHI (531) - MIPS_INS_MFTHI - mfthi $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{ /* MIPS_MFTHI_NM (532) - MIPS_INS_MFTHI - mfthi $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{ /* MIPS_MFTLO (533) - MIPS_INS_MFTLO - mftlo $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{ /* MIPS_MFTLO_NM (534) - MIPS_INS_MFTLO - mftlo $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{{{ /* MIPS_MIPSeh_return32 (535) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_MIPSeh_return64 (536) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_MSA_FP_EXTEND_D_PSEUDO (537) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_MSA_FP_EXTEND_W_PSEUDO (538) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_MSA_FP_ROUND_D_PSEUDO (539) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_MSA_FP_ROUND_W_PSEUDO (540) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_MTTACX (541) - MIPS_INS_MTTACX - mttacx $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTTACX_NM (542) - MIPS_INS_MTTACX - mttacx $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTTC0 (543) - MIPS_INS_MTTC0 - mttc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTTC0_NM (544) - MIPS_INS_MTTC0 - mttc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTTC1 (545) - MIPS_INS_MTTC1 - mttc1 $rt, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTTDSP (546) - MIPS_INS_MTTDSP - mttdsp $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTTDSP_NM (547) - MIPS_INS_MTTDSP - mttdsp $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTTGPR (548) - MIPS_INS_MTTGPR - mttgpr $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_MTTGPR_NM (549) - MIPS_INS_MTTGPR - mttgpr $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_MTTHC1 (550) - MIPS_INS_MTTHC1 - mtthc1 $rt, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTTHI (551) - MIPS_INS_MTTHI - mtthi $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTTHI_NM (552) - MIPS_INS_MTTHI - mtthi $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTTLO (553) - MIPS_INS_MTTLO - mttlo $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTTLO_NM (554) - MIPS_INS_MTTLO - mttlo $rt, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULImmMacro (555) - MIPS_INS_MUL - mul $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MULOMacro (556) - MIPS_INS_MULO - mulo $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULOUMacro (557) - MIPS_INS_MULOU - mulou $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_MUSTTAILCALLREG_NM (558) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_MUSTTAILCALL_NM (559) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_MultRxRy16 (560) - MIPS_INS_INVALID - mult $rx, $ry */ + 0 +}}}, +{{{ /* MIPS_MultRxRyRz16 (561) - MIPS_INS_INVALID - mult $rx, $ry + mflo $rz */ + 0 +}}}, +{{{ /* MIPS_MultuRxRy16 (562) - MIPS_INS_INVALID - multu $rx, $ry */ + 0 +}}}, +{{{ /* MIPS_MultuRxRyRz16 (563) - MIPS_INS_INVALID - multu $rx, $ry + mflo $rz */ + 0 +}}}, +{{{ /* MIPS_NOP (564) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_NORImm (565) - MIPS_INS_NOR - nor $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_NORImm64 (566) - MIPS_INS_NOR - nor $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{{{ /* MIPS_NOR_V_D_PSEUDO (567) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_NOR_V_H_PSEUDO (568) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_NOR_V_W_PSEUDO (569) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_OR_V_D_PSEUDO (570) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_OR_V_H_PSEUDO (571) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_OR_V_W_PSEUDO (572) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_PseudoADDIU_NM (573) - MIPS_INS_ADDIU - addiu $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_PseudoANDI_NM (574) - MIPS_INS_ANDI - andi $rt, $rs, $mask */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */ + { 0 } +}}, +{{{ /* MIPS_PseudoCMPU_EQ_QB (575) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoCMPU_LE_QB (576) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoCMPU_LT_QB (577) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoCMP_EQ_PH (578) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoCMP_LE_PH (579) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoCMP_LT_PH (580) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoCVT_D32_W (581) - MIPS_INS_INVALID - $fd, $fs */ + 0 +}}}, +{{{ /* MIPS_PseudoCVT_D64_L (582) - MIPS_INS_INVALID - $fd, $fs */ + 0 +}}}, +{{{ /* MIPS_PseudoCVT_D64_W (583) - MIPS_INS_INVALID - $fd, $fs */ + 0 +}}}, +{{{ /* MIPS_PseudoCVT_S_L (584) - MIPS_INS_INVALID - $fd, $fs */ + 0 +}}}, +{{{ /* MIPS_PseudoCVT_S_W (585) - MIPS_INS_INVALID - $fd, $fs */ + 0 +}}}, +{{{ /* MIPS_PseudoDMULT (586) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoDMULTu (587) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoDSDIV (588) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoDUDIV (589) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoD_SELECT_I (590) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoD_SELECT_I64 (591) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndirectBranch (592) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndirectBranch64 (593) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndirectBranch64R6 (594) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndirectBranchNM (595) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndirectBranchR6 (596) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndirectBranch_MM (597) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndirectBranch_MMR6 (598) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndirectHazardBranch (599) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndirectHazardBranch64 (600) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndrectHazardBranch64R6 (601) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoIndrectHazardBranchR6 (602) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_PseudoLA_NM (603) - MIPS_INS_LA - la $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_PseudoLI_NM (604) - MIPS_INS_LI - li $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{{{ /* MIPS_PseudoMADD (605) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMADDU (606) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMADDU_MM (607) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMADD_MM (608) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMFHI (609) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMFHI64 (610) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMFHI_MM (611) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMFLO (612) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMFLO64 (613) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMFLO_MM (614) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMSUB (615) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMSUBU (616) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMSUBU_MM (617) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMSUB_MM (618) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMTLOHI (619) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMTLOHI64 (620) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMTLOHI_DSP (621) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMTLOHI_MM (622) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMULT (623) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMULT_MM (624) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMULTu (625) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoMULTu_MM (626) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoPICK_PH (627) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoPICK_QB (628) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoReturn (629) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoReturn64 (630) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoReturnNM (631) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSDIV (632) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_F_D32 (633) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_F_D64 (634) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_F_I (635) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_F_I64 (636) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_F_S (637) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_T_D32 (638) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_T_D64 (639) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_T_I (640) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_T_I64 (641) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECTFP_T_S (642) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECT_D32 (643) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECT_D64 (644) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECT_I (645) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECT_I64 (646) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_PseudoSELECT_S (647) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_PseudoSUBU_NM (648) - MIPS_INS_SUBU - subu $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_PseudoTRUNC_W_D (649) - MIPS_INS_TRUNC_W_D - trunc.w.d $fd, $fs, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PseudoTRUNC_W_D32 (650) - MIPS_INS_TRUNC_W_D - trunc.w.d $fd, $fs, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PseudoTRUNC_W_S (651) - MIPS_INS_TRUNC_W_S - trunc.w.s $fd, $fs, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{{{ /* MIPS_PseudoUDIV (652) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_ROL (653) - MIPS_INS_ROL - rol $rs, $rt, $rd */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_ROLImm (654) - MIPS_INS_ROL - rol $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ROR (655) - MIPS_INS_ROR - ror $rs, $rt, $rd */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_RORImm (656) - MIPS_INS_ROR - ror $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{{{ /* MIPS_RetRA (657) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_RetRA16 (658) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_SDC1_M1 (659) - MIPS_INS_S_D - s.d $fd, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_SDIV_MM_Pseudo (660) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_SDMacro (661) - MIPS_INS_SD - sd $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDivIMacro (662) - MIPS_INS_DIV - div $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SDivMacro (663) - MIPS_INS_DIV - div $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SEQIMacro (664) - MIPS_INS_SEQ - seq $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SEQMacro (665) - MIPS_INS_SEQ - seq $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SGE (666) - MIPS_INS_SGE - sge $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SGEImm (667) - MIPS_INS_SGE - sge $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SGEImm64 (668) - MIPS_INS_SGE - sge $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SGEU (669) - MIPS_INS_SGEU - sgeu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SGEUImm (670) - MIPS_INS_SGEU - sgeu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SGEUImm64 (671) - MIPS_INS_SGEU - sgeu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SGTImm (672) - MIPS_INS_SGT - sgt $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SGTImm64 (673) - MIPS_INS_SGT - sgt $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SGTUImm (674) - MIPS_INS_SGTU - sgtu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SGTUImm64 (675) - MIPS_INS_SGTU - sgtu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLE (676) - MIPS_INS_SLE - sle $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLEImm (677) - MIPS_INS_SLE - sle $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLEImm64 (678) - MIPS_INS_SLE - sle $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLEU (679) - MIPS_INS_SLEU - sleu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLEUImm (680) - MIPS_INS_SLEU - sleu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLEUImm64 (681) - MIPS_INS_SLEU - sleu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLTImm64 (682) - MIPS_INS_SLT - slt $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLTUImm64 (683) - MIPS_INS_SLTU - sltu $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SNEIMacro (684) - MIPS_INS_SNE - sne $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SNEMacro (685) - MIPS_INS_SNE - sne $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_SNZ_B_PSEUDO (686) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SNZ_D_PSEUDO (687) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SNZ_H_PSEUDO (688) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SNZ_V_PSEUDO (689) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SNZ_W_PSEUDO (690) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_SRemIMacro (691) - MIPS_INS_REM - rem $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SRemMacro (692) - MIPS_INS_REM - rem $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_STORE_ACC128 (693) - MIPS_INS_INVALID - $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_STORE_ACC64 (694) - MIPS_INS_INVALID - $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_STORE_ACC64DSP (695) - MIPS_INS_INVALID - $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_STORE_CCOND_DSP (696) - MIPS_INS_INVALID - store_ccond_dsp $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_STR_D (697) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_STR_W (698) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_ST_F16 (699) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_SWM_MM (700) - MIPS_INS_SWM - swm $rt, $addr */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{{{ /* MIPS_SZ_B_PSEUDO (701) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SZ_D_PSEUDO (702) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SZ_H_PSEUDO (703) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SZ_V_PSEUDO (704) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SZ_W_PSEUDO (705) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_SaaAddr (706) - MIPS_INS_SAA - saa $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SaadAddr (707) - MIPS_INS_SAAD - saad $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_SelBeqZ (708) - MIPS_INS_INVALID - beqz $rt, .+4 + + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelBneZ (709) - MIPS_INS_INVALID - bnez $rt, .+4 + + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBteqZCmp (710) - MIPS_INS_INVALID - cmp $rl, $rr + bteqz .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBteqZCmpi (711) - MIPS_INS_INVALID - cmpi $rl, $imm + bteqz .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBteqZSlt (712) - MIPS_INS_INVALID - slt $rl, $rr + bteqz .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBteqZSlti (713) - MIPS_INS_INVALID - slti $rl, $imm + bteqz .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBteqZSltiu (714) - MIPS_INS_INVALID - sltiu $rl, $imm + bteqz .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBteqZSltu (715) - MIPS_INS_INVALID - sltu $rl, $rr + bteqz .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBtneZCmp (716) - MIPS_INS_INVALID - cmp $rl, $rr + btnez .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBtneZCmpi (717) - MIPS_INS_INVALID - cmpi $rl, $imm + btnez .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBtneZSlt (718) - MIPS_INS_INVALID - slt $rl, $rr + btnez .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBtneZSlti (719) - MIPS_INS_INVALID - slti $rl, $imm + btnez .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBtneZSltiu (720) - MIPS_INS_INVALID - sltiu $rl, $imm + btnez .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SelTBtneZSltu (721) - MIPS_INS_INVALID - sltu $rl, $rr + btnez .+4 + move $rd, $rs */ + 0 +}}}, +{{{ /* MIPS_SltCCRxRy16 (722) - MIPS_INS_INVALID - slt $rx, $ry + move $cc, $$t8 */ + 0 +}}}, +{{{ /* MIPS_SltiCCRxImmX16 (723) - MIPS_INS_INVALID - slti $rx, $imm + move $cc, $$t8 */ + 0 +}}}, +{{{ /* MIPS_SltiuCCRxImmX16 (724) - MIPS_INS_INVALID - sltiu $rx, $imm + move $cc, $$t8 */ + 0 +}}}, +{{{ /* MIPS_SltuCCRxRy16 (725) - MIPS_INS_INVALID - sltu $rx, $ry + move $cc, $$t8 */ + 0 +}}}, +{{{ /* MIPS_SltuRxRyRz16 (726) - MIPS_INS_INVALID - sltu $rx, $ry + move $rz, $$t8 */ + 0 +}}}, +{{{ /* MIPS_TAILCALL (727) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALL64R6REG (728) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLHB64R6REG (729) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLHBR6REG (730) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLR6REG (731) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLREG (732) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLREG64 (733) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLREGHB (734) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLREGHB64 (735) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLREG_MM (736) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLREG_MMR6 (737) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALLREG_NM (738) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALL_MM (739) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALL_MMR6 (740) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TAILCALL_NM (741) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TRAP (742) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_TRAP_MM (743) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_UDIV_MM_Pseudo (744) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_UDivIMacro (745) - MIPS_INS_DIVU - divu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_UDivMacro (746) - MIPS_INS_DIVU - divu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_URemIMacro (747) - MIPS_INS_REMU - remu $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_URemMacro (748) - MIPS_INS_REMU - remu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_Ulh (749) - MIPS_INS_ULH - ulh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_Ulhu (750) - MIPS_INS_ULHU - ulhu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_Ulw (751) - MIPS_INS_ULW - ulw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_Ush (752) - MIPS_INS_USH - ush $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_Usw (753) - MIPS_INS_USW - usw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_XOR_V_D_PSEUDO (754) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_XOR_V_H_PSEUDO (755) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_XOR_V_W_PSEUDO (756) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_ABSQ_S_PH (757) - MIPS_INS_ABSQ_S_PH - absq_s.ph $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ABSQ_S_PH_MM (758) - MIPS_INS_ABSQ_S_PH - absq_s.ph $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_ABSQ_S_QB (759) - MIPS_INS_ABSQ_S_QB - absq_s.qb $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ABSQ_S_QB_MMR2 (760) - MIPS_INS_ABSQ_S_QB - absq_s.qb $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_ABSQ_S_W (761) - MIPS_INS_ABSQ_S_W - absq_s.w $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ABSQ_S_W_MM (762) - MIPS_INS_ABSQ_S_W - absq_s.w $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_ADD (763) - MIPS_INS_ADD - add $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDIU48_NM (764) - MIPS_INS_ADDIU - addiu[48] $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUGP48_NM (765) - MIPS_INS_ADDIU - addiu[gp48] $rt, $rs, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_ADDIUGPB_NM (766) - MIPS_INS_ADDIU - addiu[gp.b] $rt, $rs, $offset */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_ADDIUGPW_NM (767) - MIPS_INS_ADDIU - addiu[gp.w] $rt, $rs, $offset */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_ADDIUNEG_NM (768) - MIPS_INS_ADDIU - addiu[neg] $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUPC (769) - MIPS_INS_ADDIUPC - addiupc $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUPC_MM (770) - MIPS_INS_ADDIUPC - addiupc $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUPC_MMR6 (771) - MIPS_INS_ADDIUPC - addiupc $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUR1SP_MM (772) - MIPS_INS_ADDIUR1SP - addiur1sp $rd, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUR1SP_NM (773) - MIPS_INS_ADDIU - addiu[r1.sp] $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUR2_MM (774) - MIPS_INS_ADDIUR2 - addiur2 $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUR2_NM (775) - MIPS_INS_ADDIU - addiu[r2] $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIURS5_NM (776) - MIPS_INS_ADDIU - addiu[rs5] $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUS5_MM (777) - MIPS_INS_ADDIUS5 - addius5 $rd, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIUSP_MM (778) - MIPS_INS_ADDIUSP - addiusp $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDIU_MMR6 (779) - MIPS_INS_ADDIU - addiu $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_ADDIU_NM (780) - MIPS_INS_ADDIU - addiu[32] $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDQH_PH (781) - MIPS_INS_ADDQH_PH - addqh.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQH_PH_MMR2 (782) - MIPS_INS_ADDQH_PH - addqh.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQH_R_PH (783) - MIPS_INS_ADDQH_R_PH - addqh_r.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQH_R_PH_MMR2 (784) - MIPS_INS_ADDQH_R_PH - addqh_r.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQH_R_W (785) - MIPS_INS_ADDQH_R_W - addqh_r.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQH_R_W_MMR2 (786) - MIPS_INS_ADDQH_R_W - addqh_r.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQH_W (787) - MIPS_INS_ADDQH_W - addqh.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQH_W_MMR2 (788) - MIPS_INS_ADDQH_W - addqh.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQ_PH (789) - MIPS_INS_ADDQ_PH - addq.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQ_PH_MM (790) - MIPS_INS_ADDQ_PH - addq.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQ_S_PH (791) - MIPS_INS_ADDQ_S_PH - addq_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQ_S_PH_MM (792) - MIPS_INS_ADDQ_S_PH - addq_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQ_S_W (793) - MIPS_INS_ADDQ_S_W - addq_s.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDQ_S_W_MM (794) - MIPS_INS_ADDQ_S_W - addq_s.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDR_PS64 (795) - MIPS_INS_ADDR_PS - addr.ps $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_ADDSC (796) - MIPS_INS_ADDSC - addsc $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDSC_MM (797) - MIPS_INS_ADDSC - addsc $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDS_A_B (798) - MIPS_INS_ADDS_A_B - adds_a.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_A_D (799) - MIPS_INS_ADDS_A_D - adds_a.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_A_H (800) - MIPS_INS_ADDS_A_H - adds_a.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_A_W (801) - MIPS_INS_ADDS_A_W - adds_a.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_S_B (802) - MIPS_INS_ADDS_S_B - adds_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_S_D (803) - MIPS_INS_ADDS_S_D - adds_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_S_H (804) - MIPS_INS_ADDS_S_H - adds_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_S_W (805) - MIPS_INS_ADDS_S_W - adds_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_U_B (806) - MIPS_INS_ADDS_U_B - adds_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_U_D (807) - MIPS_INS_ADDS_U_D - adds_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_U_H (808) - MIPS_INS_ADDS_U_H - adds_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDS_U_W (809) - MIPS_INS_ADDS_U_W - adds_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDU16_MM (810) - MIPS_INS_ADDU16 - addu16 $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU16_MMR6 (811) - MIPS_INS_ADDU16 - addu16 $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDUH_QB (812) - MIPS_INS_ADDUH_QB - adduh.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDUH_QB_MMR2 (813) - MIPS_INS_ADDUH_QB - adduh.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDUH_R_QB (814) - MIPS_INS_ADDUH_R_QB - adduh_r.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDUH_R_QB_MMR2 (815) - MIPS_INS_ADDUH_R_QB - adduh_r.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU_MMR6 (816) - MIPS_INS_ADDU - addu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU_PH (817) - MIPS_INS_ADDU_PH - addu.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU_PH_MMR2 (818) - MIPS_INS_ADDU_PH - addu.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU_QB (819) - MIPS_INS_ADDU_QB - addu.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU_QB_MM (820) - MIPS_INS_ADDU_QB - addu.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU_S_PH (821) - MIPS_INS_ADDU_S_PH - addu_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU_S_PH_MMR2 (822) - MIPS_INS_ADDU_S_PH - addu_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU_S_QB (823) - MIPS_INS_ADDU_S_QB - addu_s.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDU_S_QB_MM (824) - MIPS_INS_ADDU_S_QB - addu_s.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDVI_B (825) - MIPS_INS_ADDVI_B - addvi.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDVI_D (826) - MIPS_INS_ADDVI_D - addvi.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDVI_H (827) - MIPS_INS_ADDVI_H - addvi.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDVI_W (828) - MIPS_INS_ADDVI_W - addvi.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ADDV_B (829) - MIPS_INS_ADDV_B - addv.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDV_D (830) - MIPS_INS_ADDV_D - addv.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDV_H (831) - MIPS_INS_ADDV_H - addv.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDV_W (832) - MIPS_INS_ADDV_W - addv.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADDWC (833) - MIPS_INS_ADDWC - addwc $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDWC_MM (834) - MIPS_INS_ADDWC - addwc $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADD_A_B (835) - MIPS_INS_ADD_A_B - add_a.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADD_A_D (836) - MIPS_INS_ADD_A_D - add_a.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADD_A_H (837) - MIPS_INS_ADD_A_H - add_a.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADD_A_W (838) - MIPS_INS_ADD_A_W - add_a.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ADD_MM (839) - MIPS_INS_ADD - add $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADD_MMR6 (840) - MIPS_INS_ADD - add $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADD_NM (841) - MIPS_INS_ADD - add $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDi (842) - MIPS_INS_ADDI - addi $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_ADDi_MM (843) - MIPS_INS_ADDI - addi $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_ADDiu (844) - MIPS_INS_ADDIU - addiu $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_ADDiu_MM (845) - MIPS_INS_ADDIU - addiu $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_ADDu (846) - MIPS_INS_ADDU - addu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDu16_NM (847) - MIPS_INS_ADDU - addu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDu4x4_NM (848) - MIPS_INS_ADDU - addu $dst, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_ADDu_MM (849) - MIPS_INS_ADDU - addu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ADDu_NM (850) - MIPS_INS_ADDU - addu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ALIGN (851) - MIPS_INS_ALIGN - align $rd, $rs, $rt, $bp */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* bp */ + { 0 } +}}, +{ /* MIPS_ALIGN_MMR6 (852) - MIPS_INS_ALIGN - align $rd, $rs, $rt, $bp */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* bp */ + { 0 } +}}, +{ /* MIPS_ALUIPC (853) - MIPS_INS_ALUIPC - aluipc $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ALUIPC_MMR6 (854) - MIPS_INS_ALUIPC - aluipc $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ALUIPC_NM (855) - MIPS_INS_ALUIPC - aluipc $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_AND (856) - MIPS_INS_AND - and $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_AND16_MM (857) - MIPS_INS_AND16 - and16 $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_AND16_MMR6 (858) - MIPS_INS_AND16 - and16 $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_AND16_NM (859) - MIPS_INS_AND - and $dst, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_AND64 (860) - MIPS_INS_INVALID - and $rd, $rs, $rt */ + 0 +}}}, +{ /* MIPS_ANDI16_MM (861) - MIPS_INS_ANDI16 - andi16 $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ANDI16_MMR6 (862) - MIPS_INS_ANDI16 - andi16 $rd, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ANDI16_NM (863) - MIPS_INS_ANDI - andi[16] $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ANDI_B (864) - MIPS_INS_ANDI_B - andi.b $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_ANDI_MMR6 (865) - MIPS_INS_ANDI - andi $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_ANDI_NM (866) - MIPS_INS_ANDI - andi[32] $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_AND_MM (867) - MIPS_INS_AND - and $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_AND_MMR6 (868) - MIPS_INS_AND - and $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_AND_NM (869) - MIPS_INS_AND - and $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_AND_V (870) - MIPS_INS_AND_V - and.v $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ANDi (871) - MIPS_INS_ANDI - andi $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{{{ /* MIPS_ANDi64 (872) - MIPS_INS_INVALID - andi $rt, $rs, $imm16 */ + 0 +}}}, +{ /* MIPS_ANDi_MM (873) - MIPS_INS_ANDI - andi $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_APPEND (874) - MIPS_INS_APPEND - append $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_APPEND_MMR2 (875) - MIPS_INS_APPEND - append $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_ASUB_S_B (876) - MIPS_INS_ASUB_S_B - asub_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ASUB_S_D (877) - MIPS_INS_ASUB_S_D - asub_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ASUB_S_H (878) - MIPS_INS_ASUB_S_H - asub_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ASUB_S_W (879) - MIPS_INS_ASUB_S_W - asub_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ASUB_U_B (880) - MIPS_INS_ASUB_U_B - asub_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ASUB_U_D (881) - MIPS_INS_ASUB_U_D - asub_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ASUB_U_H (882) - MIPS_INS_ASUB_U_H - asub_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ASUB_U_W (883) - MIPS_INS_ASUB_U_W - asub_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AUI (884) - MIPS_INS_AUI - aui $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_AUIPC (885) - MIPS_INS_AUIPC - auipc $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_AUIPC_MMR6 (886) - MIPS_INS_AUIPC - auipc $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_AUI_MMR6 (887) - MIPS_INS_AUI - aui $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_AVER_S_B (888) - MIPS_INS_AVER_S_B - aver_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVER_S_D (889) - MIPS_INS_AVER_S_D - aver_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVER_S_H (890) - MIPS_INS_AVER_S_H - aver_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVER_S_W (891) - MIPS_INS_AVER_S_W - aver_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVER_U_B (892) - MIPS_INS_AVER_U_B - aver_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVER_U_D (893) - MIPS_INS_AVER_U_D - aver_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVER_U_H (894) - MIPS_INS_AVER_U_H - aver_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVER_U_W (895) - MIPS_INS_AVER_U_W - aver_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVE_S_B (896) - MIPS_INS_AVE_S_B - ave_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVE_S_D (897) - MIPS_INS_AVE_S_D - ave_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVE_S_H (898) - MIPS_INS_AVE_S_H - ave_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVE_S_W (899) - MIPS_INS_AVE_S_W - ave_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVE_U_B (900) - MIPS_INS_AVE_U_B - ave_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVE_U_D (901) - MIPS_INS_AVE_U_D - ave_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVE_U_H (902) - MIPS_INS_AVE_U_H - ave_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AVE_U_W (903) - MIPS_INS_AVE_U_W - ave_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_AddiuRxImmX16 (904) - MIPS_INS_ADDIU - addiu $rx, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_AddiuRxPcImmX16 (905) - MIPS_INS_ADDIU - addiu $rx, $$pc, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_AddiuRxRxImm16 (906) - MIPS_INS_ADDIU - addiu $rx, $imm8 # 16 bit inst */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx_ */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{{{ /* MIPS_AddiuRxRxImmX16 (907) - MIPS_INS_INVALID - addiu $rx, $imm16 */ + 0 +}}}, +{ /* MIPS_AddiuRxRyOffMemX16 (908) - MIPS_INS_ADDIU - addiu $ry, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - CPU16RegsPlusSP */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_AddiuSpImm16 (909) - MIPS_INS_ADDIU - addiu $$sp, $imm8 # 16 bit inst */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* MIPS_AddiuSpImmX16 (910) - MIPS_INS_ADDIU - addiu $$sp, $imm16 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_AdduRxRyRz16 (911) - MIPS_INS_ADDU - addu $rz, $rx, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_AndRxRxRy16 (912) - MIPS_INS_AND - and $rz, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_B16_MM (913) - MIPS_INS_B16 - b16 $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BADDu (914) - MIPS_INS_BADDU - baddu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_BAL (915) - MIPS_INS_BAL - bal $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BALC (916) - MIPS_INS_BALC - balc $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BALC16_NM (917) - MIPS_INS_BALC - balc[16] $addr */ +{ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_BALC_MMR6 (918) - MIPS_INS_BALC - balc $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BALC_NM (919) - MIPS_INS_BALC - balc $addr */ +{ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_BALIGN (920) - MIPS_INS_BALIGN - balign $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_BALIGN_MMR2 (921) - MIPS_INS_BALIGN - balign $rt, $rs, $bp */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* bp */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_BALRSC_NM (922) - MIPS_INS_BALRSC - balrsc $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_BBEQZC_NM (923) - MIPS_INS_BBEQZC - bbeqzc $rt, $u, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BBIT0 (924) - MIPS_INS_BBIT0 - bbit0 $rs, $p, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* p */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BBIT032 (925) - MIPS_INS_BBIT032 - bbit032 $rs, $p, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* p */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BBIT1 (926) - MIPS_INS_BBIT1 - bbit1 $rs, $p, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* p */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BBIT132 (927) - MIPS_INS_BBIT132 - bbit132 $rs, $p, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* p */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BBNEZC_NM (928) - MIPS_INS_BBNEZC - bbnezc $rt, $u, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC (929) - MIPS_INS_BC - bc $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC16_MMR6 (930) - MIPS_INS_BC16 - bc16 $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC16_NM (931) - MIPS_INS_BC - bc $addr */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_BC1EQZ (932) - MIPS_INS_BC1EQZ - bc1eqz $ft, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC1EQZC_MMR6 (933) - MIPS_INS_BC1EQZC - bc1eqzc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC1F (934) - MIPS_INS_BC1F - bc1f $fcc, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC1FL (935) - MIPS_INS_BC1FL - bc1fl $fcc, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC1F_MM (936) - MIPS_INS_BC1F - bc1f $fcc, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC1NEZ (937) - MIPS_INS_BC1NEZ - bc1nez $ft, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC1NEZC_MMR6 (938) - MIPS_INS_BC1NEZC - bc1nezc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC1T (939) - MIPS_INS_BC1T - bc1t $fcc, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC1TL (940) - MIPS_INS_BC1TL - bc1tl $fcc, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC1T_MM (941) - MIPS_INS_BC1T - bc1t $fcc, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC2EQZ (942) - MIPS_INS_BC2EQZ - bc2eqz $ct, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ct */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC2EQZC_MMR6 (943) - MIPS_INS_BC2EQZC - bc2eqzc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC2NEZ (944) - MIPS_INS_BC2NEZ - bc2nez $ct, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ct */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC2NEZC_MMR6 (945) - MIPS_INS_BC2NEZC - bc2nezc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BCLRI_B (946) - MIPS_INS_BCLRI_B - bclri.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BCLRI_D (947) - MIPS_INS_BCLRI_D - bclri.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BCLRI_H (948) - MIPS_INS_BCLRI_H - bclri.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BCLRI_W (949) - MIPS_INS_BCLRI_W - bclri.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BCLR_B (950) - MIPS_INS_BCLR_B - bclr.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BCLR_D (951) - MIPS_INS_BCLR_D - bclr.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BCLR_H (952) - MIPS_INS_BCLR_H - bclr.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BCLR_W (953) - MIPS_INS_BCLR_W - bclr.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BC_MMR6 (954) - MIPS_INS_BC - bc $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BC_NM (955) - MIPS_INS_BC - bc $addr */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_BEQ (956) - MIPS_INS_BEQ - beq $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{{{ /* MIPS_BEQ64 (957) - MIPS_INS_INVALID - beq $rs, $rt, $offset */ + 0 +}}}, +{ /* MIPS_BEQC (958) - MIPS_INS_BEQC - beqc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQC16_NM (959) - MIPS_INS_BEQC - beqc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQC64 (960) - MIPS_INS_BEQC - beqc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQC_MMR6 (961) - MIPS_INS_BEQC - beqc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQC_NM (962) - MIPS_INS_BEQC - beqc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQCzero_NM (963) - MIPS_INS_BEQC - beqc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQIC_NM (964) - MIPS_INS_BEQIC - beqic $rt, $u, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQL (965) - MIPS_INS_BEQL - beql $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZ16_MM (966) - MIPS_INS_BEQZ16 - beqz16 $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZALC (967) - MIPS_INS_BEQZALC - beqzalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZALC_MMR6 (968) - MIPS_INS_BEQZALC - beqzalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZC (969) - MIPS_INS_BEQZC - beqzc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZC16_MMR6 (970) - MIPS_INS_BEQZC16 - beqzc16 $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZC16_NM (971) - MIPS_INS_BEQZC - beqzc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZC64 (972) - MIPS_INS_BEQZC - beqzc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZC_MM (973) - MIPS_INS_BEQZC - beqzc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZC_MMR6 (974) - MIPS_INS_BEQZC - beqzc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQZC_NM (975) - MIPS_INS_BEQZC - beqzc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BEQ_MM (976) - MIPS_INS_BEQ - beq $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEC (977) - MIPS_INS_BGEC - bgec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEC64 (978) - MIPS_INS_BGEC - bgec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEC_MMR6 (979) - MIPS_INS_BGEC - bgec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEC_NM (980) - MIPS_INS_BGEC - bgec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEIC_NM (981) - MIPS_INS_BGEIC - bgeic $rt, $u, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEIUC_NM (982) - MIPS_INS_BGEIUC - bgeiuc $rt, $u, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEUC (983) - MIPS_INS_BGEUC - bgeuc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEUC64 (984) - MIPS_INS_BGEUC - bgeuc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEUC_MMR6 (985) - MIPS_INS_BGEUC - bgeuc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEUC_NM (986) - MIPS_INS_BGEUC - bgeuc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZ (987) - MIPS_INS_BGEZ - bgez $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{{{ /* MIPS_BGEZ64 (988) - MIPS_INS_INVALID - bgez $rs, $offset */ + 0 +}}}, +{ /* MIPS_BGEZAL (989) - MIPS_INS_BGEZAL - bgezal $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZALC (990) - MIPS_INS_BGEZALC - bgezalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZALC_MMR6 (991) - MIPS_INS_BGEZALC - bgezalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZALL (992) - MIPS_INS_BGEZALL - bgezall $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZALS_MM (993) - MIPS_INS_BGEZALS - bgezals $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZAL_MM (994) - MIPS_INS_BGEZAL - bgezal $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZC (995) - MIPS_INS_BGEZC - bgezc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZC64 (996) - MIPS_INS_BGEZC - bgezc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZC_MMR6 (997) - MIPS_INS_BGEZC - bgezc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZL (998) - MIPS_INS_BGEZL - bgezl $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGEZ_MM (999) - MIPS_INS_BGEZ - bgez $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTZ (1000) - MIPS_INS_BGTZ - bgtz $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{{{ /* MIPS_BGTZ64 (1001) - MIPS_INS_INVALID - bgtz $rs, $offset */ + 0 +}}}, +{ /* MIPS_BGTZALC (1002) - MIPS_INS_BGTZALC - bgtzalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTZALC_MMR6 (1003) - MIPS_INS_BGTZALC - bgtzalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTZC (1004) - MIPS_INS_BGTZC - bgtzc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTZC64 (1005) - MIPS_INS_BGTZC - bgtzc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTZC_MMR6 (1006) - MIPS_INS_BGTZC - bgtzc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTZL (1007) - MIPS_INS_BGTZL - bgtzl $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BGTZ_MM (1008) - MIPS_INS_BGTZ - bgtz $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BINSLI_B (1009) - MIPS_INS_BINSLI_B - binsli.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BINSLI_D (1010) - MIPS_INS_BINSLI_D - binsli.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BINSLI_H (1011) - MIPS_INS_BINSLI_H - binsli.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BINSLI_W (1012) - MIPS_INS_BINSLI_W - binsli.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BINSL_B (1013) - MIPS_INS_BINSL_B - binsl.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BINSL_D (1014) - MIPS_INS_BINSL_D - binsl.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BINSL_H (1015) - MIPS_INS_BINSL_H - binsl.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BINSL_W (1016) - MIPS_INS_BINSL_W - binsl.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BINSRI_B (1017) - MIPS_INS_BINSRI_B - binsri.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BINSRI_D (1018) - MIPS_INS_BINSRI_D - binsri.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BINSRI_H (1019) - MIPS_INS_BINSRI_H - binsri.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BINSRI_W (1020) - MIPS_INS_BINSRI_W - binsri.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BINSR_B (1021) - MIPS_INS_BINSR_B - binsr.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BINSR_D (1022) - MIPS_INS_BINSR_D - binsr.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BINSR_H (1023) - MIPS_INS_BINSR_H - binsr.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BINSR_W (1024) - MIPS_INS_BINSR_W - binsr.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BITREV (1025) - MIPS_INS_BITREV - bitrev $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_BITREVW_NM (1026) - MIPS_INS_BITREVW - bitrevw $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_BITREV_MM (1027) - MIPS_INS_BITREV - bitrev $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_BITSWAP (1028) - MIPS_INS_BITSWAP - bitswap $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_BITSWAP_MMR6 (1029) - MIPS_INS_BITSWAP - bitswap $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_BLEZ (1030) - MIPS_INS_BLEZ - blez $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{{{ /* MIPS_BLEZ64 (1031) - MIPS_INS_INVALID - blez $rs, $offset */ + 0 +}}}, +{ /* MIPS_BLEZALC (1032) - MIPS_INS_BLEZALC - blezalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEZALC_MMR6 (1033) - MIPS_INS_BLEZALC - blezalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEZC (1034) - MIPS_INS_BLEZC - blezc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEZC64 (1035) - MIPS_INS_BLEZC - blezc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEZC_MMR6 (1036) - MIPS_INS_BLEZC - blezc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEZL (1037) - MIPS_INS_BLEZL - blezl $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLEZ_MM (1038) - MIPS_INS_BLEZ - blez $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTC (1039) - MIPS_INS_BLTC - bltc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTC64 (1040) - MIPS_INS_BLTC - bltc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTC_MMR6 (1041) - MIPS_INS_BLTC - bltc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTC_NM (1042) - MIPS_INS_BLTC - bltc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTIC_NM (1043) - MIPS_INS_BLTIC - bltic $rt, $u, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTIUC_NM (1044) - MIPS_INS_BLTIUC - bltiuc $rt, $u, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTUC (1045) - MIPS_INS_BLTUC - bltuc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTUC64 (1046) - MIPS_INS_BLTUC - bltuc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTUC_MMR6 (1047) - MIPS_INS_BLTUC - bltuc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTUC_NM (1048) - MIPS_INS_BLTUC - bltuc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZ (1049) - MIPS_INS_BLTZ - bltz $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{{{ /* MIPS_BLTZ64 (1050) - MIPS_INS_INVALID - bltz $rs, $offset */ + 0 +}}}, +{ /* MIPS_BLTZAL (1051) - MIPS_INS_BLTZAL - bltzal $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZALC (1052) - MIPS_INS_BLTZALC - bltzalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZALC_MMR6 (1053) - MIPS_INS_BLTZALC - bltzalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZALL (1054) - MIPS_INS_BLTZALL - bltzall $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZALS_MM (1055) - MIPS_INS_BLTZALS - bltzals $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZAL_MM (1056) - MIPS_INS_BLTZAL - bltzal $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZC (1057) - MIPS_INS_BLTZC - bltzc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZC64 (1058) - MIPS_INS_BLTZC - bltzc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZC_MMR6 (1059) - MIPS_INS_BLTZC - bltzc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZL (1060) - MIPS_INS_BLTZL - bltzl $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BLTZ_MM (1061) - MIPS_INS_BLTZ - bltz $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BMNZI_B (1062) - MIPS_INS_BMNZI_B - bmnzi.b $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_BMNZ_V (1063) - MIPS_INS_BMNZ_V - bmnz.v $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BMZI_B (1064) - MIPS_INS_BMZI_B - bmzi.b $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_BMZ_V (1065) - MIPS_INS_BMZ_V - bmz.v $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BNE (1066) - MIPS_INS_BNE - bne $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{{{ /* MIPS_BNE64 (1067) - MIPS_INS_INVALID - bne $rs, $rt, $offset */ + 0 +}}}, +{ /* MIPS_BNEC (1068) - MIPS_INS_BNEC - bnec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEC16_NM (1069) - MIPS_INS_BNEC - bnec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEC64 (1070) - MIPS_INS_BNEC - bnec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEC_MMR6 (1071) - MIPS_INS_BNEC - bnec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEC_NM (1072) - MIPS_INS_BNEC - bnec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNECzero_NM (1073) - MIPS_INS_BNEC - bnec $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEGI_B (1074) - MIPS_INS_BNEGI_B - bnegi.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BNEGI_D (1075) - MIPS_INS_BNEGI_D - bnegi.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BNEGI_H (1076) - MIPS_INS_BNEGI_H - bnegi.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BNEGI_W (1077) - MIPS_INS_BNEGI_W - bnegi.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BNEG_B (1078) - MIPS_INS_BNEG_B - bneg.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BNEG_D (1079) - MIPS_INS_BNEG_D - bneg.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BNEG_H (1080) - MIPS_INS_BNEG_H - bneg.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BNEG_W (1081) - MIPS_INS_BNEG_W - bneg.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BNEIC_NM (1082) - MIPS_INS_BNEIC - bneic $rt, $u, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEL (1083) - MIPS_INS_BNEL - bnel $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZ16_MM (1084) - MIPS_INS_BNEZ16 - bnez16 $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZALC (1085) - MIPS_INS_BNEZALC - bnezalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZALC_MMR6 (1086) - MIPS_INS_BNEZALC - bnezalc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZC (1087) - MIPS_INS_BNEZC - bnezc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZC16_MMR6 (1088) - MIPS_INS_BNEZC16 - bnezc16 $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZC16_NM (1089) - MIPS_INS_BNEZC - bnezc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZC64 (1090) - MIPS_INS_BNEZC - bnezc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZC_MM (1091) - MIPS_INS_BNEZC - bnezc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZC_MMR6 (1092) - MIPS_INS_BNEZC - bnezc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNEZC_NM (1093) - MIPS_INS_BNEZC - bnezc $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNE_MM (1094) - MIPS_INS_BNE - bne $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNVC (1095) - MIPS_INS_BNVC - bnvc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNVC_MMR6 (1096) - MIPS_INS_BNVC - bnvc $rt, $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNZ_B (1097) - MIPS_INS_BNZ_B - bnz.b $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNZ_D (1098) - MIPS_INS_BNZ_D - bnz.d $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNZ_H (1099) - MIPS_INS_BNZ_H - bnz.h $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNZ_V (1100) - MIPS_INS_BNZ_V - bnz.v $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BNZ_W (1101) - MIPS_INS_BNZ_W - bnz.w $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BOVC (1102) - MIPS_INS_BOVC - bovc $rs, $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BOVC_MMR6 (1103) - MIPS_INS_BOVC - bovc $rt, $rs, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BPOSGE32 (1104) - MIPS_INS_BPOSGE32 - bposge32 $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BPOSGE32C_MMR3 (1105) - MIPS_INS_BPOSGE32C - bposge32c $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BPOSGE32_MM (1106) - MIPS_INS_BPOSGE32 - bposge32 $offset */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BREAK (1107) - MIPS_INS_BREAK - break $code_1, $code_2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_2 */ + { 0 } +}}, +{ /* MIPS_BREAK16_MM (1108) - MIPS_INS_BREAK16 - break16 $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_BREAK16_MMR6 (1109) - MIPS_INS_BREAK16 - break16 $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_BREAK16_NM (1110) - MIPS_INS_BREAK - break $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_BREAK_MM (1111) - MIPS_INS_BREAK - break $code_1, $code_2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_2 */ + { 0 } +}}, +{ /* MIPS_BREAK_MMR6 (1112) - MIPS_INS_BREAK - break $code_1, $code_2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_2 */ + { 0 } +}}, +{ /* MIPS_BREAK_NM (1113) - MIPS_INS_BREAK - break $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_BRSC_NM (1114) - MIPS_INS_BRSC - brsc $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* jti */ + { 0 } +}}, +{ /* MIPS_BSELI_B (1115) - MIPS_INS_BSELI_B - bseli.b $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_BSEL_V (1116) - MIPS_INS_BSEL_V - bsel.v $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BSETI_B (1117) - MIPS_INS_BSETI_B - bseti.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BSETI_D (1118) - MIPS_INS_BSETI_D - bseti.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BSETI_H (1119) - MIPS_INS_BSETI_H - bseti.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BSETI_W (1120) - MIPS_INS_BSETI_W - bseti.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_BSET_B (1121) - MIPS_INS_BSET_B - bset.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BSET_D (1122) - MIPS_INS_BSET_D - bset.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BSET_H (1123) - MIPS_INS_BSET_H - bset.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BSET_W (1124) - MIPS_INS_BSET_W - bset.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_BYTEREVW_NM (1125) - MIPS_INS_BYTEREVW - byterevw $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_BZ_B (1126) - MIPS_INS_BZ_B - bz.b $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BZ_D (1127) - MIPS_INS_BZ_D - bz.d $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BZ_H (1128) - MIPS_INS_BZ_H - bz.h $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BZ_V (1129) - MIPS_INS_BZ_V - bz.v $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BZ_W (1130) - MIPS_INS_BZ_W - bz.w $wt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_BeqzRxImm16 (1131) - MIPS_INS_BEQZ - beqz $rx, $imm8 # 16 bit inst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* MIPS_BeqzRxImmX16 (1132) - MIPS_INS_BEQZ - beqz $rx, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_Bimm16 (1133) - MIPS_INS_B - b $imm11 # 16 bit inst */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* imm11 */ + { 0 } +}}, +{ /* MIPS_BimmX16 (1134) - MIPS_INS_B - b $imm16 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_BnezRxImm16 (1135) - MIPS_INS_BNEZ - bnez $rx, $imm8 # 16 bit inst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* MIPS_BnezRxImmX16 (1136) - MIPS_INS_BNEZ - bnez $rx, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_Break16 (1137) - MIPS_INS_BREAK - break 0 */ +{ + { 0 } +}}, +{ /* MIPS_Bteqz16 (1138) - MIPS_INS_BTEQZ - bteqz $imm8 # 16 bit inst */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* MIPS_BteqzX16 (1139) - MIPS_INS_BTEQZ - bteqz $imm16 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_Btnez16 (1140) - MIPS_INS_BTNEZ - btnez $imm8 # 16 bit inst */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* MIPS_BtnezX16 (1141) - MIPS_INS_BTNEZ - btnez $imm16 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_CACHE (1142) - MIPS_INS_CACHE - cache $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_CACHEE (1143) - MIPS_INS_CACHEE - cachee $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_CACHEE_MM (1144) - MIPS_INS_CACHEE - cachee $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_CACHE_MM (1145) - MIPS_INS_CACHE - cache $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_CACHE_MMR6 (1146) - MIPS_INS_CACHE - cache $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_CACHE_NM (1147) - MIPS_INS_CACHE - cache $op, $addr */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* op */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_CACHE_R6 (1148) - MIPS_INS_CACHE - cache $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_CEIL_L_D64 (1149) - MIPS_INS_CEIL_L_D - ceil.l.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_L_D_MMR6 (1150) - MIPS_INS_CEIL_L_D - ceil.l.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_L_S (1151) - MIPS_INS_CEIL_L_S - ceil.l.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_L_S_MMR6 (1152) - MIPS_INS_CEIL_L_S - ceil.l.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_W_D32 (1153) - MIPS_INS_CEIL_W_D - ceil.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_W_D64 (1154) - MIPS_INS_CEIL_W_D - ceil.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_W_D_MMR6 (1155) - MIPS_INS_CEIL_W_D - ceil.w.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_W_MM (1156) - MIPS_INS_CEIL_W_D - ceil.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_W_S (1157) - MIPS_INS_CEIL_W_S - ceil.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_W_S_MM (1158) - MIPS_INS_CEIL_W_S - ceil.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEIL_W_S_MMR6 (1159) - MIPS_INS_CEIL_W_S - ceil.w.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CEQI_B (1160) - MIPS_INS_CEQI_B - ceqi.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CEQI_D (1161) - MIPS_INS_CEQI_D - ceqi.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CEQI_H (1162) - MIPS_INS_CEQI_H - ceqi.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CEQI_W (1163) - MIPS_INS_CEQI_W - ceqi.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CEQ_B (1164) - MIPS_INS_CEQ_B - ceq.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CEQ_D (1165) - MIPS_INS_CEQ_D - ceq.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CEQ_H (1166) - MIPS_INS_CEQ_H - ceq.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CEQ_W (1167) - MIPS_INS_CEQ_W - ceq.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CFC1 (1168) - MIPS_INS_CFC1 - cfc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CFC1_MM (1169) - MIPS_INS_CFC1 - cfc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CFC2_MM (1170) - MIPS_INS_CFC2 - cfc2 $rt, $impl */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* impl */ + { 0 } +}}, +{ /* MIPS_CFCMSA (1171) - MIPS_INS_CFCMSA - cfcmsa $rd, $cs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cs */ + { 0 } +}}, +{ /* MIPS_CINS (1172) - MIPS_INS_CINS - cins $rt, $rs, $pos, $lenm1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lenm1 */ + { 0 } +}}, +{ /* MIPS_CINS32 (1173) - MIPS_INS_CINS32 - cins32 $rt, $rs, $pos, $lenm1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lenm1 */ + { 0 } +}}, +{{{ /* MIPS_CINS64_32 (1174) - MIPS_INS_INVALID - cins $rt, $rs, $pos, $lenm1 */ + 0 +}}}, +{{{ /* MIPS_CINS_i32 (1175) - MIPS_INS_INVALID - cins $rt, $rs, $pos, $lenm1 */ + 0 +}}}, +{ /* MIPS_CLASS_D (1176) - MIPS_INS_CLASS_D - class.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CLASS_D_MMR6 (1177) - MIPS_INS_CLASS_D - class.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CLASS_S (1178) - MIPS_INS_CLASS_S - class.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CLASS_S_MMR6 (1179) - MIPS_INS_CLASS_S - class.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CLEI_S_B (1180) - MIPS_INS_CLEI_S_B - clei_s.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLEI_S_D (1181) - MIPS_INS_CLEI_S_D - clei_s.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLEI_S_H (1182) - MIPS_INS_CLEI_S_H - clei_s.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLEI_S_W (1183) - MIPS_INS_CLEI_S_W - clei_s.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLEI_U_B (1184) - MIPS_INS_CLEI_U_B - clei_u.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLEI_U_D (1185) - MIPS_INS_CLEI_U_D - clei_u.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLEI_U_H (1186) - MIPS_INS_CLEI_U_H - clei_u.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLEI_U_W (1187) - MIPS_INS_CLEI_U_W - clei_u.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLE_S_B (1188) - MIPS_INS_CLE_S_B - cle_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLE_S_D (1189) - MIPS_INS_CLE_S_D - cle_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLE_S_H (1190) - MIPS_INS_CLE_S_H - cle_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLE_S_W (1191) - MIPS_INS_CLE_S_W - cle_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLE_U_B (1192) - MIPS_INS_CLE_U_B - cle_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLE_U_D (1193) - MIPS_INS_CLE_U_D - cle_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLE_U_H (1194) - MIPS_INS_CLE_U_H - cle_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLE_U_W (1195) - MIPS_INS_CLE_U_W - cle_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLO (1196) - MIPS_INS_CLO - clo $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CLO_MM (1197) - MIPS_INS_CLO - clo $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CLO_MMR6 (1198) - MIPS_INS_CLO - clo $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CLO_NM (1199) - MIPS_INS_CLO - clo $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CLO_R6 (1200) - MIPS_INS_CLO - clo $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CLTI_S_B (1201) - MIPS_INS_CLTI_S_B - clti_s.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLTI_S_D (1202) - MIPS_INS_CLTI_S_D - clti_s.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLTI_S_H (1203) - MIPS_INS_CLTI_S_H - clti_s.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLTI_S_W (1204) - MIPS_INS_CLTI_S_W - clti_s.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLTI_U_B (1205) - MIPS_INS_CLTI_U_B - clti_u.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLTI_U_D (1206) - MIPS_INS_CLTI_U_D - clti_u.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLTI_U_H (1207) - MIPS_INS_CLTI_U_H - clti_u.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLTI_U_W (1208) - MIPS_INS_CLTI_U_W - clti_u.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_CLT_S_B (1209) - MIPS_INS_CLT_S_B - clt_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLT_S_D (1210) - MIPS_INS_CLT_S_D - clt_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLT_S_H (1211) - MIPS_INS_CLT_S_H - clt_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLT_S_W (1212) - MIPS_INS_CLT_S_W - clt_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLT_U_B (1213) - MIPS_INS_CLT_U_B - clt_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLT_U_D (1214) - MIPS_INS_CLT_U_D - clt_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLT_U_H (1215) - MIPS_INS_CLT_U_H - clt_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLT_U_W (1216) - MIPS_INS_CLT_U_W - clt_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_CLZ (1217) - MIPS_INS_CLZ - clz $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CLZ_MM (1218) - MIPS_INS_CLZ - clz $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CLZ_MMR6 (1219) - MIPS_INS_CLZ - clz $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CLZ_NM (1220) - MIPS_INS_CLZ - clz $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CLZ_R6 (1221) - MIPS_INS_CLZ - clz $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CMPGDU_EQ_QB (1222) - MIPS_INS_CMPGDU_EQ_QB - cmpgdu.eq.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGDU_EQ_QB_MMR2 (1223) - MIPS_INS_CMPGDU_EQ_QB - cmpgdu.eq.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGDU_LE_QB (1224) - MIPS_INS_CMPGDU_LE_QB - cmpgdu.le.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGDU_LE_QB_MMR2 (1225) - MIPS_INS_CMPGDU_LE_QB - cmpgdu.le.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGDU_LT_QB (1226) - MIPS_INS_CMPGDU_LT_QB - cmpgdu.lt.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGDU_LT_QB_MMR2 (1227) - MIPS_INS_CMPGDU_LT_QB - cmpgdu.lt.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGU_EQ_QB (1228) - MIPS_INS_CMPGU_EQ_QB - cmpgu.eq.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGU_EQ_QB_MM (1229) - MIPS_INS_CMPGU_EQ_QB - cmpgu.eq.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGU_LE_QB (1230) - MIPS_INS_CMPGU_LE_QB - cmpgu.le.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGU_LE_QB_MM (1231) - MIPS_INS_CMPGU_LE_QB - cmpgu.le.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGU_LT_QB (1232) - MIPS_INS_CMPGU_LT_QB - cmpgu.lt.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPGU_LT_QB_MM (1233) - MIPS_INS_CMPGU_LT_QB - cmpgu.lt.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPU_EQ_QB (1234) - MIPS_INS_CMPU_EQ_QB - cmpu.eq.qb $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPU_EQ_QB_MM (1235) - MIPS_INS_CMPU_EQ_QB - cmpu.eq.qb $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPU_LE_QB (1236) - MIPS_INS_CMPU_LE_QB - cmpu.le.qb $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPU_LE_QB_MM (1237) - MIPS_INS_CMPU_LE_QB - cmpu.le.qb $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPU_LT_QB (1238) - MIPS_INS_CMPU_LT_QB - cmpu.lt.qb $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMPU_LT_QB_MM (1239) - MIPS_INS_CMPU_LT_QB - cmpu.lt.qb $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMP_AF_D_MMR6 (1240) - MIPS_INS_CMP_AF_D - cmp.af.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_AF_S_MMR6 (1241) - MIPS_INS_CMP_AF_S - cmp.af.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_EQ_D (1242) - MIPS_INS_CMP_EQ_D - cmp.eq.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_EQ_D_MMR6 (1243) - MIPS_INS_CMP_EQ_D - cmp.eq.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_EQ_PH (1244) - MIPS_INS_CMP_EQ_PH - cmp.eq.ph $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMP_EQ_PH_MM (1245) - MIPS_INS_CMP_EQ_PH - cmp.eq.ph $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMP_EQ_S (1246) - MIPS_INS_CMP_EQ_S - cmp.eq.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_EQ_S_MMR6 (1247) - MIPS_INS_CMP_EQ_S - cmp.eq.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_F_D (1248) - MIPS_INS_CMP_AF_D - cmp.af.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_F_S (1249) - MIPS_INS_CMP_AF_S - cmp.af.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_LE_D (1250) - MIPS_INS_CMP_LE_D - cmp.le.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_LE_D_MMR6 (1251) - MIPS_INS_CMP_LE_D - cmp.le.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_LE_PH (1252) - MIPS_INS_CMP_LE_PH - cmp.le.ph $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMP_LE_PH_MM (1253) - MIPS_INS_CMP_LE_PH - cmp.le.ph $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMP_LE_S (1254) - MIPS_INS_CMP_LE_S - cmp.le.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_LE_S_MMR6 (1255) - MIPS_INS_CMP_LE_S - cmp.le.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_LT_D (1256) - MIPS_INS_CMP_LT_D - cmp.lt.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_LT_D_MMR6 (1257) - MIPS_INS_CMP_LT_D - cmp.lt.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_LT_PH (1258) - MIPS_INS_CMP_LT_PH - cmp.lt.ph $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMP_LT_PH_MM (1259) - MIPS_INS_CMP_LT_PH - cmp.lt.ph $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CMP_LT_S (1260) - MIPS_INS_CMP_LT_S - cmp.lt.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_LT_S_MMR6 (1261) - MIPS_INS_CMP_LT_S - cmp.lt.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SAF_D (1262) - MIPS_INS_CMP_SAF_D - cmp.saf.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SAF_D_MMR6 (1263) - MIPS_INS_CMP_SAF_D - cmp.saf.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SAF_S (1264) - MIPS_INS_CMP_SAF_S - cmp.saf.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SAF_S_MMR6 (1265) - MIPS_INS_CMP_SAF_S - cmp.saf.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SEQ_D (1266) - MIPS_INS_CMP_SEQ_D - cmp.seq.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SEQ_D_MMR6 (1267) - MIPS_INS_CMP_SEQ_D - cmp.seq.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SEQ_S (1268) - MIPS_INS_CMP_SEQ_S - cmp.seq.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SEQ_S_MMR6 (1269) - MIPS_INS_CMP_SEQ_S - cmp.seq.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SLE_D (1270) - MIPS_INS_CMP_SLE_D - cmp.sle.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SLE_D_MMR6 (1271) - MIPS_INS_CMP_SLE_D - cmp.sle.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SLE_S (1272) - MIPS_INS_CMP_SLE_S - cmp.sle.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SLE_S_MMR6 (1273) - MIPS_INS_CMP_SLE_S - cmp.sle.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SLT_D (1274) - MIPS_INS_CMP_SLT_D - cmp.slt.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SLT_D_MMR6 (1275) - MIPS_INS_CMP_SLT_D - cmp.slt.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SLT_S (1276) - MIPS_INS_CMP_SLT_S - cmp.slt.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SLT_S_MMR6 (1277) - MIPS_INS_CMP_SLT_S - cmp.slt.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SUEQ_D (1278) - MIPS_INS_CMP_SUEQ_D - cmp.sueq.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SUEQ_D_MMR6 (1279) - MIPS_INS_CMP_SUEQ_D - cmp.sueq.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SUEQ_S (1280) - MIPS_INS_CMP_SUEQ_S - cmp.sueq.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SUEQ_S_MMR6 (1281) - MIPS_INS_CMP_SUEQ_S - cmp.sueq.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SULE_D (1282) - MIPS_INS_CMP_SULE_D - cmp.sule.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SULE_D_MMR6 (1283) - MIPS_INS_CMP_SULE_D - cmp.sule.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SULE_S (1284) - MIPS_INS_CMP_SULE_S - cmp.sule.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SULE_S_MMR6 (1285) - MIPS_INS_CMP_SULE_S - cmp.sule.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SULT_D (1286) - MIPS_INS_CMP_SULT_D - cmp.sult.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SULT_D_MMR6 (1287) - MIPS_INS_CMP_SULT_D - cmp.sult.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SULT_S (1288) - MIPS_INS_CMP_SULT_S - cmp.sult.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SULT_S_MMR6 (1289) - MIPS_INS_CMP_SULT_S - cmp.sult.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SUN_D (1290) - MIPS_INS_CMP_SUN_D - cmp.sun.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SUN_D_MMR6 (1291) - MIPS_INS_CMP_SUN_D - cmp.sun.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SUN_S (1292) - MIPS_INS_CMP_SUN_S - cmp.sun.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_SUN_S_MMR6 (1293) - MIPS_INS_CMP_SUN_S - cmp.sun.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_UEQ_D (1294) - MIPS_INS_CMP_UEQ_D - cmp.ueq.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_UEQ_D_MMR6 (1295) - MIPS_INS_CMP_UEQ_D - cmp.ueq.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_UEQ_S (1296) - MIPS_INS_CMP_UEQ_S - cmp.ueq.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_UEQ_S_MMR6 (1297) - MIPS_INS_CMP_UEQ_S - cmp.ueq.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_ULE_D (1298) - MIPS_INS_CMP_ULE_D - cmp.ule.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_ULE_D_MMR6 (1299) - MIPS_INS_CMP_ULE_D - cmp.ule.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_ULE_S (1300) - MIPS_INS_CMP_ULE_S - cmp.ule.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_ULE_S_MMR6 (1301) - MIPS_INS_CMP_ULE_S - cmp.ule.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_ULT_D (1302) - MIPS_INS_CMP_ULT_D - cmp.ult.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_ULT_D_MMR6 (1303) - MIPS_INS_CMP_ULT_D - cmp.ult.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_ULT_S (1304) - MIPS_INS_CMP_ULT_S - cmp.ult.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_ULT_S_MMR6 (1305) - MIPS_INS_CMP_ULT_S - cmp.ult.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_UN_D (1306) - MIPS_INS_CMP_UN_D - cmp.un.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_UN_D_MMR6 (1307) - MIPS_INS_CMP_UN_D - cmp.un.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_UN_S (1308) - MIPS_INS_CMP_UN_S - cmp.un.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CMP_UN_S_MMR6 (1309) - MIPS_INS_CMP_UN_S - cmp.un.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_COPY_S_B (1310) - MIPS_INS_COPY_S_B - copy_s.b $rd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_COPY_S_D (1311) - MIPS_INS_COPY_S_D - copy_s.d $rd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_COPY_S_H (1312) - MIPS_INS_COPY_S_H - copy_s.h $rd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_COPY_S_W (1313) - MIPS_INS_COPY_S_W - copy_s.w $rd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_COPY_U_B (1314) - MIPS_INS_COPY_U_B - copy_u.b $rd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_COPY_U_H (1315) - MIPS_INS_COPY_U_H - copy_u.h $rd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_COPY_U_W (1316) - MIPS_INS_COPY_U_W - copy_u.w $rd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_CRC32B (1317) - MIPS_INS_CRC32B - crc32b $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CRC32B_NM (1318) - MIPS_INS_CRC32B - crc32b $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CRC32CB (1319) - MIPS_INS_CRC32CB - crc32cb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CRC32CB_NM (1320) - MIPS_INS_CRC32CB - crc32cb $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CRC32CD (1321) - MIPS_INS_CRC32CD - crc32cd $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CRC32CH (1322) - MIPS_INS_CRC32CH - crc32ch $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CRC32CH_NM (1323) - MIPS_INS_CRC32CH - crc32ch $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CRC32CW (1324) - MIPS_INS_CRC32CW - crc32cw $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CRC32CW_NM (1325) - MIPS_INS_CRC32CW - crc32cw $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CRC32D (1326) - MIPS_INS_CRC32D - crc32d $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CRC32H (1327) - MIPS_INS_CRC32H - crc32h $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CRC32H_NM (1328) - MIPS_INS_CRC32H - crc32h $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CRC32W (1329) - MIPS_INS_CRC32W - crc32w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CRC32W_NM (1330) - MIPS_INS_CRC32W - crc32w $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CTC1 (1331) - MIPS_INS_CTC1 - ctc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CTC1_MM (1332) - MIPS_INS_CTC1 - ctc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CTC2_MM (1333) - MIPS_INS_CTC2 - ctc2 $rt, $impl */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* impl */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_CTCMSA (1334) - MIPS_INS_CTCMSA - ctcmsa $cd, $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_CVT_D32_S (1335) - MIPS_INS_CVT_D_S - cvt.d.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_D32_S_MM (1336) - MIPS_INS_CVT_D_S - cvt.d.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_D32_W (1337) - MIPS_INS_CVT_D_W - cvt.d.w $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_D32_W_MM (1338) - MIPS_INS_CVT_D_W - cvt.d.w $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_D64_L (1339) - MIPS_INS_CVT_D_L - cvt.d.l $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_D64_S (1340) - MIPS_INS_CVT_D_S - cvt.d.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_D64_S_MM (1341) - MIPS_INS_CVT_D_S - cvt.d.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_D64_W (1342) - MIPS_INS_CVT_D_W - cvt.d.w $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_D64_W_MM (1343) - MIPS_INS_CVT_D_W - cvt.d.w $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_D_L_MMR6 (1344) - MIPS_INS_CVT_D_L - cvt.d.l $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_L_D64 (1345) - MIPS_INS_CVT_L_D - cvt.l.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_L_D64_MM (1346) - MIPS_INS_CVT_L_D - cvt.l.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_L_D_MMR6 (1347) - MIPS_INS_CVT_L_D - cvt.l.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_L_S (1348) - MIPS_INS_CVT_L_S - cvt.l.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_L_S_MM (1349) - MIPS_INS_CVT_L_S - cvt.l.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_L_S_MMR6 (1350) - MIPS_INS_CVT_L_S - cvt.l.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_PS_PW64 (1351) - MIPS_INS_CVT_PS_PW - cvt.ps.pw $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_PS_S64 (1352) - MIPS_INS_CVT_PS_S - cvt.ps.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CVT_PW_PS64 (1353) - MIPS_INS_CVT_PW_PS - cvt.pw.ps $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_D32 (1354) - MIPS_INS_CVT_S_D - cvt.s.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_D32_MM (1355) - MIPS_INS_CVT_S_D - cvt.s.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_D64 (1356) - MIPS_INS_CVT_S_D - cvt.s.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_D64_MM (1357) - MIPS_INS_CVT_S_D - cvt.s.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_L (1358) - MIPS_INS_CVT_S_L - cvt.s.l $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_L_MMR6 (1359) - MIPS_INS_CVT_S_L - cvt.s.l $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_PL64 (1360) - MIPS_INS_CVT_S_PL - cvt.s.pl $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_PU64 (1361) - MIPS_INS_CVT_S_PU - cvt.s.pu $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_W (1362) - MIPS_INS_CVT_S_W - cvt.s.w $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_W_MM (1363) - MIPS_INS_CVT_S_W - cvt.s.w $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_S_W_MMR6 (1364) - MIPS_INS_CVT_S_W - cvt.s.w $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_W_D32 (1365) - MIPS_INS_CVT_W_D - cvt.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_W_D32_MM (1366) - MIPS_INS_CVT_W_D - cvt.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_W_D64 (1367) - MIPS_INS_CVT_W_D - cvt.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_W_D64_MM (1368) - MIPS_INS_CVT_W_D - cvt.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_W_S (1369) - MIPS_INS_CVT_W_S - cvt.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_W_S_MM (1370) - MIPS_INS_CVT_W_S - cvt.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_CVT_W_S_MMR6 (1371) - MIPS_INS_CVT_W_S - cvt.w.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_C_EQ_D32 (1372) - MIPS_INS_C_EQ_D - c.eq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_EQ_D32_MM (1373) - MIPS_INS_C_EQ_D - c.eq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_EQ_D64 (1374) - MIPS_INS_C_EQ_D - c.eq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_EQ_D64_MM (1375) - MIPS_INS_C_EQ_D - c.eq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_EQ_S (1376) - MIPS_INS_C_EQ_S - c.eq.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_EQ_S_MM (1377) - MIPS_INS_C_EQ_S - c.eq.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_F_D32 (1378) - MIPS_INS_C_F_D - c.f.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_F_D32_MM (1379) - MIPS_INS_C_F_D - c.f.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_F_D64 (1380) - MIPS_INS_C_F_D - c.f.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_F_D64_MM (1381) - MIPS_INS_C_F_D - c.f.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_F_S (1382) - MIPS_INS_C_F_S - c.f.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_F_S_MM (1383) - MIPS_INS_C_F_S - c.f.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LE_D32 (1384) - MIPS_INS_C_LE_D - c.le.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LE_D32_MM (1385) - MIPS_INS_C_LE_D - c.le.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LE_D64 (1386) - MIPS_INS_C_LE_D - c.le.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LE_D64_MM (1387) - MIPS_INS_C_LE_D - c.le.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LE_S (1388) - MIPS_INS_C_LE_S - c.le.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LE_S_MM (1389) - MIPS_INS_C_LE_S - c.le.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LT_D32 (1390) - MIPS_INS_C_LT_D - c.lt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LT_D32_MM (1391) - MIPS_INS_C_LT_D - c.lt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LT_D64 (1392) - MIPS_INS_C_LT_D - c.lt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LT_D64_MM (1393) - MIPS_INS_C_LT_D - c.lt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LT_S (1394) - MIPS_INS_C_LT_S - c.lt.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_LT_S_MM (1395) - MIPS_INS_C_LT_S - c.lt.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGE_D32 (1396) - MIPS_INS_C_NGE_D - c.nge.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGE_D32_MM (1397) - MIPS_INS_C_NGE_D - c.nge.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGE_D64 (1398) - MIPS_INS_C_NGE_D - c.nge.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGE_D64_MM (1399) - MIPS_INS_C_NGE_D - c.nge.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGE_S (1400) - MIPS_INS_C_NGE_S - c.nge.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGE_S_MM (1401) - MIPS_INS_C_NGE_S - c.nge.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGLE_D32 (1402) - MIPS_INS_C_NGLE_D - c.ngle.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGLE_D32_MM (1403) - MIPS_INS_C_NGLE_D - c.ngle.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGLE_D64 (1404) - MIPS_INS_C_NGLE_D - c.ngle.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGLE_D64_MM (1405) - MIPS_INS_C_NGLE_D - c.ngle.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGLE_S (1406) - MIPS_INS_C_NGLE_S - c.ngle.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGLE_S_MM (1407) - MIPS_INS_C_NGLE_S - c.ngle.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGL_D32 (1408) - MIPS_INS_C_NGL_D - c.ngl.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGL_D32_MM (1409) - MIPS_INS_C_NGL_D - c.ngl.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGL_D64 (1410) - MIPS_INS_C_NGL_D - c.ngl.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGL_D64_MM (1411) - MIPS_INS_C_NGL_D - c.ngl.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGL_S (1412) - MIPS_INS_C_NGL_S - c.ngl.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGL_S_MM (1413) - MIPS_INS_C_NGL_S - c.ngl.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGT_D32 (1414) - MIPS_INS_C_NGT_D - c.ngt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGT_D32_MM (1415) - MIPS_INS_C_NGT_D - c.ngt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGT_D64 (1416) - MIPS_INS_C_NGT_D - c.ngt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGT_D64_MM (1417) - MIPS_INS_C_NGT_D - c.ngt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGT_S (1418) - MIPS_INS_C_NGT_S - c.ngt.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_NGT_S_MM (1419) - MIPS_INS_C_NGT_S - c.ngt.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLE_D32 (1420) - MIPS_INS_C_OLE_D - c.ole.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLE_D32_MM (1421) - MIPS_INS_C_OLE_D - c.ole.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLE_D64 (1422) - MIPS_INS_C_OLE_D - c.ole.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLE_D64_MM (1423) - MIPS_INS_C_OLE_D - c.ole.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLE_S (1424) - MIPS_INS_C_OLE_S - c.ole.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLE_S_MM (1425) - MIPS_INS_C_OLE_S - c.ole.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLT_D32 (1426) - MIPS_INS_C_OLT_D - c.olt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLT_D32_MM (1427) - MIPS_INS_C_OLT_D - c.olt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLT_D64 (1428) - MIPS_INS_C_OLT_D - c.olt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLT_D64_MM (1429) - MIPS_INS_C_OLT_D - c.olt.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLT_S (1430) - MIPS_INS_C_OLT_S - c.olt.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_OLT_S_MM (1431) - MIPS_INS_C_OLT_S - c.olt.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SEQ_D32 (1432) - MIPS_INS_C_SEQ_D - c.seq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SEQ_D32_MM (1433) - MIPS_INS_C_SEQ_D - c.seq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SEQ_D64 (1434) - MIPS_INS_C_SEQ_D - c.seq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SEQ_D64_MM (1435) - MIPS_INS_C_SEQ_D - c.seq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SEQ_S (1436) - MIPS_INS_C_SEQ_S - c.seq.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SEQ_S_MM (1437) - MIPS_INS_C_SEQ_S - c.seq.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SF_D32 (1438) - MIPS_INS_C_SF_D - c.sf.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SF_D32_MM (1439) - MIPS_INS_C_SF_D - c.sf.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SF_D64 (1440) - MIPS_INS_C_SF_D - c.sf.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SF_D64_MM (1441) - MIPS_INS_C_SF_D - c.sf.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SF_S (1442) - MIPS_INS_C_SF_S - c.sf.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_SF_S_MM (1443) - MIPS_INS_C_SF_S - c.sf.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UEQ_D32 (1444) - MIPS_INS_C_UEQ_D - c.ueq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UEQ_D32_MM (1445) - MIPS_INS_C_UEQ_D - c.ueq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UEQ_D64 (1446) - MIPS_INS_C_UEQ_D - c.ueq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UEQ_D64_MM (1447) - MIPS_INS_C_UEQ_D - c.ueq.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UEQ_S (1448) - MIPS_INS_C_UEQ_S - c.ueq.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UEQ_S_MM (1449) - MIPS_INS_C_UEQ_S - c.ueq.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULE_D32 (1450) - MIPS_INS_C_ULE_D - c.ule.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULE_D32_MM (1451) - MIPS_INS_C_ULE_D - c.ule.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULE_D64 (1452) - MIPS_INS_C_ULE_D - c.ule.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULE_D64_MM (1453) - MIPS_INS_C_ULE_D - c.ule.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULE_S (1454) - MIPS_INS_C_ULE_S - c.ule.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULE_S_MM (1455) - MIPS_INS_C_ULE_S - c.ule.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULT_D32 (1456) - MIPS_INS_C_ULT_D - c.ult.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULT_D32_MM (1457) - MIPS_INS_C_ULT_D - c.ult.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULT_D64 (1458) - MIPS_INS_C_ULT_D - c.ult.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULT_D64_MM (1459) - MIPS_INS_C_ULT_D - c.ult.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULT_S (1460) - MIPS_INS_C_ULT_S - c.ult.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_ULT_S_MM (1461) - MIPS_INS_C_ULT_S - c.ult.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UN_D32 (1462) - MIPS_INS_C_UN_D - c.un.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UN_D32_MM (1463) - MIPS_INS_C_UN_D - c.un.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UN_D64 (1464) - MIPS_INS_C_UN_D - c.un.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UN_D64_MM (1465) - MIPS_INS_C_UN_D - c.un.d $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UN_S (1466) - MIPS_INS_C_UN_S - c.un.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_C_UN_S_MM (1467) - MIPS_INS_C_UN_S - c.un.s $fcc, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_CmpRxRy16 (1468) - MIPS_INS_CMP - cmp $rx, $ry */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_CmpiRxImm16 (1469) - MIPS_INS_CMPI - cmpi $rx, $imm8 # 16 bit inst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* MIPS_CmpiRxImmX16 (1470) - MIPS_INS_CMPI - cmpi $rx, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_DADD (1471) - MIPS_INS_DADD - dadd $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DADDi (1472) - MIPS_INS_DADDI - daddi $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_DADDiu (1473) - MIPS_INS_DADDIU - daddiu $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_DADDu (1474) - MIPS_INS_DADDU - daddu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DAHI (1475) - MIPS_INS_DAHI - dahi $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DALIGN (1476) - MIPS_INS_DALIGN - dalign $rd, $rs, $rt, $bp */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* bp */ + { 0 } +}}, +{ /* MIPS_DATI (1477) - MIPS_INS_DATI - dati $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DAUI (1478) - MIPS_INS_DAUI - daui $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_DBITSWAP (1479) - MIPS_INS_DBITSWAP - dbitswap $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DCLO (1480) - MIPS_INS_DCLO - dclo $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DCLO_R6 (1481) - MIPS_INS_DCLO - dclo $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DCLZ (1482) - MIPS_INS_DCLZ - dclz $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DCLZ_R6 (1483) - MIPS_INS_DCLZ - dclz $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DDIV (1484) - MIPS_INS_DDIV - ddiv $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DDIVU (1485) - MIPS_INS_DDIVU - ddivu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DERET (1486) - MIPS_INS_DERET - deret */ +{ + { 0 } +}}, +{ /* MIPS_DERET_MM (1487) - MIPS_INS_DERET - deret */ +{ + { 0 } +}}, +{ /* MIPS_DERET_MMR6 (1488) - MIPS_INS_DERET - deret */ +{ + { 0 } +}}, +{ /* MIPS_DERET_NM (1489) - MIPS_INS_DERET - deret */ +{ + { 0 } +}}, +{ /* MIPS_DEXT (1490) - MIPS_INS_DEXT - dext $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { 0 } +}}, +{{{ /* MIPS_DEXT64_32 (1491) - MIPS_INS_INVALID - dext $rt, $rs, $pos, $size */ + 0 +}}}, +{ /* MIPS_DEXTM (1492) - MIPS_INS_DEXTM - dextm $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { 0 } +}}, +{ /* MIPS_DEXTU (1493) - MIPS_INS_DEXTU - dextu $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { 0 } +}}, +{ /* MIPS_DI (1494) - MIPS_INS_DI - di $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DINS (1495) - MIPS_INS_DINS - dins $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_DINSM (1496) - MIPS_INS_DINSM - dinsm $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_DINSU (1497) - MIPS_INS_DINSU - dinsu $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_DIV (1498) - MIPS_INS_DIV - div $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DIVU (1499) - MIPS_INS_DIVU - divu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DIVU_MMR6 (1500) - MIPS_INS_DIVU - divu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DIVU_NM (1501) - MIPS_INS_DIVU - divu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DIV_MMR6 (1502) - MIPS_INS_DIV - div $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DIV_NM (1503) - MIPS_INS_DIV - div $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DIV_S_B (1504) - MIPS_INS_DIV_S_B - div_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DIV_S_D (1505) - MIPS_INS_DIV_S_D - div_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DIV_S_H (1506) - MIPS_INS_DIV_S_H - div_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DIV_S_W (1507) - MIPS_INS_DIV_S_W - div_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DIV_U_B (1508) - MIPS_INS_DIV_U_B - div_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DIV_U_D (1509) - MIPS_INS_DIV_U_D - div_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DIV_U_H (1510) - MIPS_INS_DIV_U_H - div_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DIV_U_W (1511) - MIPS_INS_DIV_U_W - div_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DI_MM (1512) - MIPS_INS_DI - di $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DI_MMR6 (1513) - MIPS_INS_DI - di $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DI_NM (1514) - MIPS_INS_DI - di $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DLSA (1515) - MIPS_INS_DLSA - dlsa $rd, $rs, $rt, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_DLSA_R6 (1516) - MIPS_INS_DLSA - dlsa $rd, $rs, $rt, $imm2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm2 */ + { 0 } +}}, +{ /* MIPS_DMFC0 (1517) - MIPS_INS_DMFC0 - dmfc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_DMFC1 (1518) - MIPS_INS_DMFC1 - dmfc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_DMFC2 (1519) - MIPS_INS_DMFC2 - dmfc2 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_DMFC2_OCTEON (1520) - MIPS_INS_DMFC2 - dmfc2 $rt, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_DMFGC0 (1521) - MIPS_INS_DMFGC0 - dmfgc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_DMOD (1522) - MIPS_INS_DMOD - dmod $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMODU (1523) - MIPS_INS_DMODU - dmodu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMT (1524) - MIPS_INS_DMT - dmt $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMTC0 (1525) - MIPS_INS_DMTC0 - dmtc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_DMTC1 (1526) - MIPS_INS_DMTC1 - dmtc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMTC2 (1527) - MIPS_INS_DMTC2 - dmtc2 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_DMTC2_OCTEON (1528) - MIPS_INS_DMTC2 - dmtc2 $rt, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_DMTGC0 (1529) - MIPS_INS_DMTGC0 - dmtgc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_DMT_NM (1530) - MIPS_INS_DMT - dmt $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMUH (1531) - MIPS_INS_DMUH - dmuh $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMUHU (1532) - MIPS_INS_DMUHU - dmuhu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMUL (1533) - MIPS_INS_DMUL - dmul $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMULT (1534) - MIPS_INS_DMULT - dmult $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMULTu (1535) - MIPS_INS_DMULTU - dmultu $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMULU (1536) - MIPS_INS_DMULU - dmulu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DMUL_R6 (1537) - MIPS_INS_DMUL - dmul $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DOTP_S_D (1538) - MIPS_INS_DOTP_S_D - dotp_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DOTP_S_H (1539) - MIPS_INS_DOTP_S_H - dotp_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DOTP_S_W (1540) - MIPS_INS_DOTP_S_W - dotp_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DOTP_U_D (1541) - MIPS_INS_DOTP_U_D - dotp_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DOTP_U_H (1542) - MIPS_INS_DOTP_U_H - dotp_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DOTP_U_W (1543) - MIPS_INS_DOTP_U_W - dotp_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPADD_S_D (1544) - MIPS_INS_DPADD_S_D - dpadd_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPADD_S_H (1545) - MIPS_INS_DPADD_S_H - dpadd_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPADD_S_W (1546) - MIPS_INS_DPADD_S_W - dpadd_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPADD_U_D (1547) - MIPS_INS_DPADD_U_D - dpadd_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPADD_U_H (1548) - MIPS_INS_DPADD_U_H - dpadd_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPADD_U_W (1549) - MIPS_INS_DPADD_U_W - dpadd_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPAQX_SA_W_PH (1550) - MIPS_INS_DPAQX_SA_W_PH - dpaqx_sa.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAQX_SA_W_PH_MMR2 (1551) - MIPS_INS_DPAQX_SA_W_PH - dpaqx_sa.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAQX_S_W_PH (1552) - MIPS_INS_DPAQX_S_W_PH - dpaqx_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAQX_S_W_PH_MMR2 (1553) - MIPS_INS_DPAQX_S_W_PH - dpaqx_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAQ_SA_L_W (1554) - MIPS_INS_DPAQ_SA_L_W - dpaq_sa.l.w $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAQ_SA_L_W_MM (1555) - MIPS_INS_DPAQ_SA_L_W - dpaq_sa.l.w $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAQ_S_W_PH (1556) - MIPS_INS_DPAQ_S_W_PH - dpaq_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAQ_S_W_PH_MM (1557) - MIPS_INS_DPAQ_S_W_PH - dpaq_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAU_H_QBL (1558) - MIPS_INS_DPAU_H_QBL - dpau.h.qbl $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAU_H_QBL_MM (1559) - MIPS_INS_DPAU_H_QBL - dpau.h.qbl $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAU_H_QBR (1560) - MIPS_INS_DPAU_H_QBR - dpau.h.qbr $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAU_H_QBR_MM (1561) - MIPS_INS_DPAU_H_QBR - dpau.h.qbr $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAX_W_PH (1562) - MIPS_INS_DPAX_W_PH - dpax.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPAX_W_PH_MMR2 (1563) - MIPS_INS_DPAX_W_PH - dpax.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPA_W_PH (1564) - MIPS_INS_DPA_W_PH - dpa.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPA_W_PH_MMR2 (1565) - MIPS_INS_DPA_W_PH - dpa.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPOP (1566) - MIPS_INS_DPOP - dpop $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DPSQX_SA_W_PH (1567) - MIPS_INS_DPSQX_SA_W_PH - dpsqx_sa.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSQX_SA_W_PH_MMR2 (1568) - MIPS_INS_DPSQX_SA_W_PH - dpsqx_sa.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSQX_S_W_PH (1569) - MIPS_INS_DPSQX_S_W_PH - dpsqx_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSQX_S_W_PH_MMR2 (1570) - MIPS_INS_DPSQX_S_W_PH - dpsqx_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSQ_SA_L_W (1571) - MIPS_INS_DPSQ_SA_L_W - dpsq_sa.l.w $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSQ_SA_L_W_MM (1572) - MIPS_INS_DPSQ_SA_L_W - dpsq_sa.l.w $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSQ_S_W_PH (1573) - MIPS_INS_DPSQ_S_W_PH - dpsq_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSQ_S_W_PH_MM (1574) - MIPS_INS_DPSQ_S_W_PH - dpsq_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSUB_S_D (1575) - MIPS_INS_DPSUB_S_D - dpsub_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPSUB_S_H (1576) - MIPS_INS_DPSUB_S_H - dpsub_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPSUB_S_W (1577) - MIPS_INS_DPSUB_S_W - dpsub_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPSUB_U_D (1578) - MIPS_INS_DPSUB_U_D - dpsub_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPSUB_U_H (1579) - MIPS_INS_DPSUB_U_H - dpsub_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPSUB_U_W (1580) - MIPS_INS_DPSUB_U_W - dpsub_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_DPSU_H_QBL (1581) - MIPS_INS_DPSU_H_QBL - dpsu.h.qbl $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSU_H_QBL_MM (1582) - MIPS_INS_DPSU_H_QBL - dpsu.h.qbl $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSU_H_QBR (1583) - MIPS_INS_DPSU_H_QBR - dpsu.h.qbr $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSU_H_QBR_MM (1584) - MIPS_INS_DPSU_H_QBR - dpsu.h.qbr $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSX_W_PH (1585) - MIPS_INS_DPSX_W_PH - dpsx.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPSX_W_PH_MMR2 (1586) - MIPS_INS_DPSX_W_PH - dpsx.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPS_W_PH (1587) - MIPS_INS_DPS_W_PH - dps.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DPS_W_PH_MMR2 (1588) - MIPS_INS_DPS_W_PH - dps.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_DROTR (1589) - MIPS_INS_DROTR - drotr $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_DROTR32 (1590) - MIPS_INS_DROTR32 - drotr32 $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_DROTRV (1591) - MIPS_INS_DROTRV - drotrv $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DSBH (1592) - MIPS_INS_DSBH - dsbh $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DSDIV (1593) - MIPS_INS_DDIV - ddiv $$zero, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DSHD (1594) - MIPS_INS_DSHD - dshd $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DSLL (1595) - MIPS_INS_DSLL - dsll $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_DSLL32 (1596) - MIPS_INS_DSLL32 - dsll32 $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{{{ /* MIPS_DSLL64_32 (1597) - MIPS_INS_INVALID - dsll $rd, $rt, 32 */ + 0 +}}}, +{ /* MIPS_DSLLV (1598) - MIPS_INS_DSLLV - dsllv $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DSRA (1599) - MIPS_INS_DSRA - dsra $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_DSRA32 (1600) - MIPS_INS_DSRA32 - dsra32 $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_DSRAV (1601) - MIPS_INS_DSRAV - dsrav $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DSRL (1602) - MIPS_INS_DSRL - dsrl $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_DSRL32 (1603) - MIPS_INS_DSRL32 - dsrl32 $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_DSRLV (1604) - MIPS_INS_DSRLV - dsrlv $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DSUB (1605) - MIPS_INS_DSUB - dsub $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DSUBu (1606) - MIPS_INS_DSUBU - dsubu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DUDIV (1607) - MIPS_INS_DDIVU - ddivu $$zero, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DVP (1608) - MIPS_INS_DVP - dvp $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DVPE (1609) - MIPS_INS_DVPE - dvpe $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DVPE_NM (1610) - MIPS_INS_DVPE - dvpe $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_DVP_MMR6 (1611) - MIPS_INS_DVP - dvp $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_DivRxRy16 (1612) - MIPS_INS_DIV - div $$zero, $rx, $ry */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_DivuRxRy16 (1613) - MIPS_INS_DIVU - divu $$zero, $rx, $ry */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_EHB (1614) - MIPS_INS_EHB - ehb */ +{ + { 0 } +}}, +{ /* MIPS_EHB_MM (1615) - MIPS_INS_EHB - ehb */ +{ + { 0 } +}}, +{ /* MIPS_EHB_MMR6 (1616) - MIPS_INS_EHB - ehb */ +{ + { 0 } +}}, +{ /* MIPS_EHB_NM (1617) - MIPS_INS_EHB - ehb */ +{ + { 0 } +}}, +{ /* MIPS_EI (1618) - MIPS_INS_EI - ei $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_EI_MM (1619) - MIPS_INS_EI - ei $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_EI_MMR6 (1620) - MIPS_INS_EI - ei $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_EI_NM (1621) - MIPS_INS_EI - ei $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_EMT (1622) - MIPS_INS_EMT - emt $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_EMT_NM (1623) - MIPS_INS_EMT - emt $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ERET (1624) - MIPS_INS_ERET - eret */ +{ + { 0 } +}}, +{ /* MIPS_ERETNC (1625) - MIPS_INS_ERETNC - eretnc */ +{ + { 0 } +}}, +{ /* MIPS_ERETNC_MMR6 (1626) - MIPS_INS_ERETNC - eretnc */ +{ + { 0 } +}}, +{ /* MIPS_ERETNC_NM (1627) - MIPS_INS_ERETNC - eretnc */ +{ + { 0 } +}}, +{ /* MIPS_ERET_MM (1628) - MIPS_INS_ERET - eret */ +{ + { 0 } +}}, +{ /* MIPS_ERET_MMR6 (1629) - MIPS_INS_ERET - eret */ +{ + { 0 } +}}, +{ /* MIPS_ERET_NM (1630) - MIPS_INS_ERET - eret */ +{ + { 0 } +}}, +{ /* MIPS_EVP (1631) - MIPS_INS_EVP - evp $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_EVPE (1632) - MIPS_INS_EVPE - evpe $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_EVPE_NM (1633) - MIPS_INS_EVPE - evpe $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_EVP_MMR6 (1634) - MIPS_INS_EVP - evp $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_EXT (1635) - MIPS_INS_EXT - ext $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { 0 } +}}, +{ /* MIPS_EXTP (1636) - MIPS_INS_EXTP - extp $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTPDP (1637) - MIPS_INS_EXTPDP - extpdp $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTPDPV (1638) - MIPS_INS_EXTPDPV - extpdpv $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTPDPV_MM (1639) - MIPS_INS_EXTPDPV - extpdpv $rt, $ac, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_EXTPDP_MM (1640) - MIPS_INS_EXTPDP - extpdp $rt, $ac, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_EXTPV (1641) - MIPS_INS_EXTPV - extpv $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTPV_MM (1642) - MIPS_INS_EXTPV - extpv $rt, $ac, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_EXTP_MM (1643) - MIPS_INS_EXTP - extp $rt, $ac, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_EXTRV_RS_W (1644) - MIPS_INS_EXTRV_RS_W - extrv_rs.w $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTRV_RS_W_MM (1645) - MIPS_INS_EXTRV_RS_W - extrv_rs.w $rt, $ac, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_EXTRV_R_W (1646) - MIPS_INS_EXTRV_R_W - extrv_r.w $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTRV_R_W_MM (1647) - MIPS_INS_EXTRV_R_W - extrv_r.w $rt, $ac, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_EXTRV_S_H (1648) - MIPS_INS_EXTRV_S_H - extrv_s.h $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTRV_S_H_MM (1649) - MIPS_INS_EXTRV_S_H - extrv_s.h $rt, $ac, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_EXTRV_W (1650) - MIPS_INS_EXTRV_W - extrv.w $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTRV_W_MM (1651) - MIPS_INS_EXTRV_W - extrv.w $rt, $ac, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_EXTR_RS_W (1652) - MIPS_INS_EXTR_RS_W - extr_rs.w $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTR_RS_W_MM (1653) - MIPS_INS_EXTR_RS_W - extr_rs.w $rt, $ac, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_EXTR_R_W (1654) - MIPS_INS_EXTR_R_W - extr_r.w $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTR_R_W_MM (1655) - MIPS_INS_EXTR_R_W - extr_r.w $rt, $ac, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_EXTR_S_H (1656) - MIPS_INS_EXTR_S_H - extr_s.h $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTR_S_H_MM (1657) - MIPS_INS_EXTR_S_H - extr_s.h $rt, $ac, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_EXTR_W (1658) - MIPS_INS_EXTR_W - extr.w $rt, $ac, $shift_rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift_rs */ + { 0 } +}}, +{ /* MIPS_EXTR_W_MM (1659) - MIPS_INS_EXTR_W - extr.w $rt, $ac, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_EXTS (1660) - MIPS_INS_EXTS - exts $rt, $rs, $pos, $lenm1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lenm1 */ + { 0 } +}}, +{ /* MIPS_EXTS32 (1661) - MIPS_INS_EXTS32 - exts32 $rt, $rs, $pos, $lenm1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lenm1 */ + { 0 } +}}, +{ /* MIPS_EXTW_NM (1662) - MIPS_INS_EXTW - extw $rd, $rs, $rt, $shift */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift */ + { 0 } +}}, +{ /* MIPS_EXT_MM (1663) - MIPS_INS_EXT - ext $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { 0 } +}}, +{ /* MIPS_EXT_MMR6 (1664) - MIPS_INS_EXT - ext $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { 0 } +}}, +{ /* MIPS_EXT_NM (1665) - MIPS_INS_EXT - ext $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { 0 } +}}, +{ /* MIPS_FABS_D32 (1666) - MIPS_INS_ABS_D - abs.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FABS_D32_MM (1667) - MIPS_INS_ABS_D - abs.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FABS_D64 (1668) - MIPS_INS_ABS_D - abs.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FABS_D64_MM (1669) - MIPS_INS_ABS_D - abs.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FABS_S (1670) - MIPS_INS_ABS_S - abs.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FABS_S_MM (1671) - MIPS_INS_ABS_S - abs.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FADD_D (1672) - MIPS_INS_FADD_D - fadd.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FADD_D32 (1673) - MIPS_INS_ADD_D - add.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FADD_D32_MM (1674) - MIPS_INS_ADD_D - add.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FADD_D64 (1675) - MIPS_INS_ADD_D - add.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FADD_D64_MM (1676) - MIPS_INS_ADD_D - add.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FADD_PS64 (1677) - MIPS_INS_ADD_PS - add.ps $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FADD_S (1678) - MIPS_INS_ADD_S - add.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FADD_S_MM (1679) - MIPS_INS_ADD_S - add.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FADD_S_MMR6 (1680) - MIPS_INS_ADD_S - add.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FADD_W (1681) - MIPS_INS_FADD_W - fadd.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCAF_D (1682) - MIPS_INS_FCAF_D - fcaf.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCAF_W (1683) - MIPS_INS_FCAF_W - fcaf.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCEQ_D (1684) - MIPS_INS_FCEQ_D - fceq.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCEQ_W (1685) - MIPS_INS_FCEQ_W - fceq.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCLASS_D (1686) - MIPS_INS_FCLASS_D - fclass.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FCLASS_W (1687) - MIPS_INS_FCLASS_W - fclass.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FCLE_D (1688) - MIPS_INS_FCLE_D - fcle.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCLE_W (1689) - MIPS_INS_FCLE_W - fcle.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCLT_D (1690) - MIPS_INS_FCLT_D - fclt.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCLT_W (1691) - MIPS_INS_FCLT_W - fclt.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{{{ /* MIPS_FCMP_D32 (1692) - MIPS_INS_INVALID - c.$cond.d $fs, $ft */ + 0 +}}}, +{{{ /* MIPS_FCMP_D32_MM (1693) - MIPS_INS_INVALID - c.$cond.d $fs, $ft */ + 0 +}}}, +{{{ /* MIPS_FCMP_D64 (1694) - MIPS_INS_INVALID - c.$cond.d $fs, $ft */ + 0 +}}}, +{{{ /* MIPS_FCMP_S32 (1695) - MIPS_INS_INVALID - c.$cond.s $fs, $ft */ + 0 +}}}, +{{{ /* MIPS_FCMP_S32_MM (1696) - MIPS_INS_INVALID - c.$cond.s $fs, $ft */ + 0 +}}}, +{ /* MIPS_FCNE_D (1697) - MIPS_INS_FCNE_D - fcne.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCNE_W (1698) - MIPS_INS_FCNE_W - fcne.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCOR_D (1699) - MIPS_INS_FCOR_D - fcor.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCOR_W (1700) - MIPS_INS_FCOR_W - fcor.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCUEQ_D (1701) - MIPS_INS_FCUEQ_D - fcueq.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCUEQ_W (1702) - MIPS_INS_FCUEQ_W - fcueq.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCULE_D (1703) - MIPS_INS_FCULE_D - fcule.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCULE_W (1704) - MIPS_INS_FCULE_W - fcule.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCULT_D (1705) - MIPS_INS_FCULT_D - fcult.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCULT_W (1706) - MIPS_INS_FCULT_W - fcult.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCUNE_D (1707) - MIPS_INS_FCUNE_D - fcune.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCUNE_W (1708) - MIPS_INS_FCUNE_W - fcune.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCUN_D (1709) - MIPS_INS_FCUN_D - fcun.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FCUN_W (1710) - MIPS_INS_FCUN_W - fcun.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FDIV_D (1711) - MIPS_INS_FDIV_D - fdiv.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FDIV_D32 (1712) - MIPS_INS_DIV_D - div.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FDIV_D32_MM (1713) - MIPS_INS_DIV_D - div.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FDIV_D64 (1714) - MIPS_INS_DIV_D - div.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FDIV_D64_MM (1715) - MIPS_INS_DIV_D - div.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FDIV_S (1716) - MIPS_INS_DIV_S - div.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FDIV_S_MM (1717) - MIPS_INS_DIV_S - div.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FDIV_S_MMR6 (1718) - MIPS_INS_DIV_S - div.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FDIV_W (1719) - MIPS_INS_FDIV_W - fdiv.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FEXDO_H (1720) - MIPS_INS_FEXDO_H - fexdo.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FEXDO_W (1721) - MIPS_INS_FEXDO_W - fexdo.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FEXP2_D (1722) - MIPS_INS_FEXP2_D - fexp2.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FEXP2_W (1723) - MIPS_INS_FEXP2_W - fexp2.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FEXUPL_D (1724) - MIPS_INS_FEXUPL_D - fexupl.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FEXUPL_W (1725) - MIPS_INS_FEXUPL_W - fexupl.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FEXUPR_D (1726) - MIPS_INS_FEXUPR_D - fexupr.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FEXUPR_W (1727) - MIPS_INS_FEXUPR_W - fexupr.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FFINT_S_D (1728) - MIPS_INS_FFINT_S_D - ffint_s.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FFINT_S_W (1729) - MIPS_INS_FFINT_S_W - ffint_s.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FFINT_U_D (1730) - MIPS_INS_FFINT_U_D - ffint_u.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FFINT_U_W (1731) - MIPS_INS_FFINT_U_W - ffint_u.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FFQL_D (1732) - MIPS_INS_FFQL_D - ffql.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FFQL_W (1733) - MIPS_INS_FFQL_W - ffql.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FFQR_D (1734) - MIPS_INS_FFQR_D - ffqr.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FFQR_W (1735) - MIPS_INS_FFQR_W - ffqr.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FILL_B (1736) - MIPS_INS_FILL_B - fill.b $wd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_FILL_D (1737) - MIPS_INS_FILL_D - fill.d $wd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_FILL_H (1738) - MIPS_INS_FILL_H - fill.h $wd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_FILL_W (1739) - MIPS_INS_FILL_W - fill.w $wd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_FLOG2_D (1740) - MIPS_INS_FLOG2_D - flog2.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FLOG2_W (1741) - MIPS_INS_FLOG2_W - flog2.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FLOOR_L_D64 (1742) - MIPS_INS_FLOOR_L_D - floor.l.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_L_D_MMR6 (1743) - MIPS_INS_FLOOR_L_D - floor.l.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_L_S (1744) - MIPS_INS_FLOOR_L_S - floor.l.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_L_S_MMR6 (1745) - MIPS_INS_FLOOR_L_S - floor.l.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_W_D32 (1746) - MIPS_INS_FLOOR_W_D - floor.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_W_D64 (1747) - MIPS_INS_FLOOR_W_D - floor.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_W_D_MMR6 (1748) - MIPS_INS_FLOOR_W_D - floor.w.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_W_MM (1749) - MIPS_INS_FLOOR_W_D - floor.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_W_S (1750) - MIPS_INS_FLOOR_W_S - floor.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_W_S_MM (1751) - MIPS_INS_FLOOR_W_S - floor.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FLOOR_W_S_MMR6 (1752) - MIPS_INS_FLOOR_W_S - floor.w.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMADD_D (1753) - MIPS_INS_FMADD_D - fmadd.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMADD_W (1754) - MIPS_INS_FMADD_W - fmadd.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMAX_A_D (1755) - MIPS_INS_FMAX_A_D - fmax_a.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMAX_A_W (1756) - MIPS_INS_FMAX_A_W - fmax_a.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMAX_D (1757) - MIPS_INS_FMAX_D - fmax.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMAX_W (1758) - MIPS_INS_FMAX_W - fmax.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMIN_A_D (1759) - MIPS_INS_FMIN_A_D - fmin_a.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMIN_A_W (1760) - MIPS_INS_FMIN_A_W - fmin_a.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMIN_D (1761) - MIPS_INS_FMIN_D - fmin.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMIN_W (1762) - MIPS_INS_FMIN_W - fmin.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMOV_D32 (1763) - MIPS_INS_MOV_D - mov.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMOV_D32_MM (1764) - MIPS_INS_MOV_D - mov.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMOV_D64 (1765) - MIPS_INS_MOV_D - mov.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMOV_D64_MM (1766) - MIPS_INS_MOV_D - mov.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMOV_D_MMR6 (1767) - MIPS_INS_MOV_D - mov.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMOV_S (1768) - MIPS_INS_MOV_S - mov.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMOV_S_MM (1769) - MIPS_INS_MOV_S - mov.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMOV_S_MMR6 (1770) - MIPS_INS_MOV_S - mov.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMSUB_D (1771) - MIPS_INS_FMSUB_D - fmsub.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMSUB_W (1772) - MIPS_INS_FMSUB_W - fmsub.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMUL_D (1773) - MIPS_INS_FMUL_D - fmul.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FMUL_D32 (1774) - MIPS_INS_MUL_D - mul.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FMUL_D32_MM (1775) - MIPS_INS_MUL_D - mul.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FMUL_D64 (1776) - MIPS_INS_MUL_D - mul.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FMUL_D64_MM (1777) - MIPS_INS_MUL_D - mul.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FMUL_PS64 (1778) - MIPS_INS_MUL_PS - mul.ps $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FMUL_S (1779) - MIPS_INS_MUL_S - mul.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FMUL_S_MM (1780) - MIPS_INS_MUL_S - mul.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FMUL_S_MMR6 (1781) - MIPS_INS_MUL_S - mul.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FMUL_W (1782) - MIPS_INS_FMUL_W - fmul.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FNEG_D32 (1783) - MIPS_INS_NEG_D - neg.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FNEG_D32_MM (1784) - MIPS_INS_NEG_D - neg.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FNEG_D64 (1785) - MIPS_INS_NEG_D - neg.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FNEG_D64_MM (1786) - MIPS_INS_NEG_D - neg.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FNEG_S (1787) - MIPS_INS_NEG_S - neg.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FNEG_S_MM (1788) - MIPS_INS_NEG_S - neg.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FNEG_S_MMR6 (1789) - MIPS_INS_NEG_S - neg.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FORK (1790) - MIPS_INS_FORK - fork $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_FORK_NM (1791) - MIPS_INS_FORK - fork $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_FRCP_D (1792) - MIPS_INS_FRCP_D - frcp.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FRCP_W (1793) - MIPS_INS_FRCP_W - frcp.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FRINT_D (1794) - MIPS_INS_FRINT_D - frint.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FRINT_W (1795) - MIPS_INS_FRINT_W - frint.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FRSQRT_D (1796) - MIPS_INS_FRSQRT_D - frsqrt.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FRSQRT_W (1797) - MIPS_INS_FRSQRT_W - frsqrt.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FSAF_D (1798) - MIPS_INS_FSAF_D - fsaf.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSAF_W (1799) - MIPS_INS_FSAF_W - fsaf.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSEQ_D (1800) - MIPS_INS_FSEQ_D - fseq.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSEQ_W (1801) - MIPS_INS_FSEQ_W - fseq.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSLE_D (1802) - MIPS_INS_FSLE_D - fsle.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSLE_W (1803) - MIPS_INS_FSLE_W - fsle.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSLT_D (1804) - MIPS_INS_FSLT_D - fslt.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSLT_W (1805) - MIPS_INS_FSLT_W - fslt.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSNE_D (1806) - MIPS_INS_FSNE_D - fsne.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSNE_W (1807) - MIPS_INS_FSNE_W - fsne.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSOR_D (1808) - MIPS_INS_FSOR_D - fsor.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSOR_W (1809) - MIPS_INS_FSOR_W - fsor.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSQRT_D (1810) - MIPS_INS_FSQRT_D - fsqrt.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FSQRT_D32 (1811) - MIPS_INS_SQRT_D - sqrt.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FSQRT_D32_MM (1812) - MIPS_INS_SQRT_D - sqrt.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FSQRT_D64 (1813) - MIPS_INS_SQRT_D - sqrt.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FSQRT_D64_MM (1814) - MIPS_INS_SQRT_D - sqrt.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FSQRT_S (1815) - MIPS_INS_SQRT_S - sqrt.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FSQRT_S_MM (1816) - MIPS_INS_SQRT_S - sqrt.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FSQRT_W (1817) - MIPS_INS_FSQRT_W - fsqrt.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FSUB_D (1818) - MIPS_INS_FSUB_D - fsub.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSUB_D32 (1819) - MIPS_INS_SUB_D - sub.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FSUB_D32_MM (1820) - MIPS_INS_SUB_D - sub.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FSUB_D64 (1821) - MIPS_INS_SUB_D - sub.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FSUB_D64_MM (1822) - MIPS_INS_SUB_D - sub.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FSUB_PS64 (1823) - MIPS_INS_SUB_PS - sub.ps $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FSUB_S (1824) - MIPS_INS_SUB_S - sub.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FSUB_S_MM (1825) - MIPS_INS_SUB_S - sub.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_FSUB_S_MMR6 (1826) - MIPS_INS_SUB_S - sub.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_FSUB_W (1827) - MIPS_INS_FSUB_W - fsub.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSUEQ_D (1828) - MIPS_INS_FSUEQ_D - fsueq.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSUEQ_W (1829) - MIPS_INS_FSUEQ_W - fsueq.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSULE_D (1830) - MIPS_INS_FSULE_D - fsule.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSULE_W (1831) - MIPS_INS_FSULE_W - fsule.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSULT_D (1832) - MIPS_INS_FSULT_D - fsult.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSULT_W (1833) - MIPS_INS_FSULT_W - fsult.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSUNE_D (1834) - MIPS_INS_FSUNE_D - fsune.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSUNE_W (1835) - MIPS_INS_FSUNE_W - fsune.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSUN_D (1836) - MIPS_INS_FSUN_D - fsun.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FSUN_W (1837) - MIPS_INS_FSUN_W - fsun.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FTINT_S_D (1838) - MIPS_INS_FTINT_S_D - ftint_s.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FTINT_S_W (1839) - MIPS_INS_FTINT_S_W - ftint_s.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FTINT_U_D (1840) - MIPS_INS_FTINT_U_D - ftint_u.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FTINT_U_W (1841) - MIPS_INS_FTINT_U_W - ftint_u.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FTQ_H (1842) - MIPS_INS_FTQ_H - ftq.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FTQ_W (1843) - MIPS_INS_FTQ_W - ftq.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_FTRUNC_S_D (1844) - MIPS_INS_FTRUNC_S_D - ftrunc_s.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FTRUNC_S_W (1845) - MIPS_INS_FTRUNC_S_W - ftrunc_s.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FTRUNC_U_D (1846) - MIPS_INS_FTRUNC_U_D - ftrunc_u.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_FTRUNC_U_W (1847) - MIPS_INS_FTRUNC_U_W - ftrunc_u.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_GINVI (1848) - MIPS_INS_GINVI - ginvi $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_GINVI_MMR6 (1849) - MIPS_INS_GINVI - ginvi $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_GINVI_NM (1850) - MIPS_INS_GINVI - ginvi $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_GINVT (1851) - MIPS_INS_GINVT - ginvt $rs, $type_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* type_ */ + { 0 } +}}, +{ /* MIPS_GINVT_MMR6 (1852) - MIPS_INS_GINVT - ginvt $rs, $type */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* type */ + { 0 } +}}, +{ /* MIPS_GINVT_NM (1853) - MIPS_INS_GINVT - ginvt $rs, $type */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* type */ + { 0 } +}}, +{ /* MIPS_HADD_S_D (1854) - MIPS_INS_HADD_S_D - hadd_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HADD_S_H (1855) - MIPS_INS_HADD_S_H - hadd_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HADD_S_W (1856) - MIPS_INS_HADD_S_W - hadd_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HADD_U_D (1857) - MIPS_INS_HADD_U_D - hadd_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HADD_U_H (1858) - MIPS_INS_HADD_U_H - hadd_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HADD_U_W (1859) - MIPS_INS_HADD_U_W - hadd_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HSUB_S_D (1860) - MIPS_INS_HSUB_S_D - hsub_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HSUB_S_H (1861) - MIPS_INS_HSUB_S_H - hsub_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HSUB_S_W (1862) - MIPS_INS_HSUB_S_W - hsub_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HSUB_U_D (1863) - MIPS_INS_HSUB_U_D - hsub_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HSUB_U_H (1864) - MIPS_INS_HSUB_U_H - hsub_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HSUB_U_W (1865) - MIPS_INS_HSUB_U_W - hsub_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_HYPCALL (1866) - MIPS_INS_HYPCALL - hypcall $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_HYPCALL_MM (1867) - MIPS_INS_HYPCALL - hypcall $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_ILVEV_B (1868) - MIPS_INS_ILVEV_B - ilvev.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVEV_D (1869) - MIPS_INS_ILVEV_D - ilvev.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVEV_H (1870) - MIPS_INS_ILVEV_H - ilvev.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVEV_W (1871) - MIPS_INS_ILVEV_W - ilvev.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVL_B (1872) - MIPS_INS_ILVL_B - ilvl.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVL_D (1873) - MIPS_INS_ILVL_D - ilvl.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVL_H (1874) - MIPS_INS_ILVL_H - ilvl.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVL_W (1875) - MIPS_INS_ILVL_W - ilvl.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVOD_B (1876) - MIPS_INS_ILVOD_B - ilvod.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVOD_D (1877) - MIPS_INS_ILVOD_D - ilvod.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVOD_H (1878) - MIPS_INS_ILVOD_H - ilvod.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVOD_W (1879) - MIPS_INS_ILVOD_W - ilvod.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVR_B (1880) - MIPS_INS_ILVR_B - ilvr.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVR_D (1881) - MIPS_INS_ILVR_D - ilvr.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVR_H (1882) - MIPS_INS_ILVR_H - ilvr.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ILVR_W (1883) - MIPS_INS_ILVR_W - ilvr.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_INS (1884) - MIPS_INS_INS - ins $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_INSERT_B (1885) - MIPS_INS_INSERT_B - insert.b $wd[$n], $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_INSERT_D (1886) - MIPS_INS_INSERT_D - insert.d $wd[$n], $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_INSERT_H (1887) - MIPS_INS_INSERT_H - insert.h $wd[$n], $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_INSERT_W (1888) - MIPS_INS_INSERT_W - insert.w $wd[$n], $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_INSV (1889) - MIPS_INS_INSV - insv $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_INSVE_B (1890) - MIPS_INS_INSVE_B - insve.b $wd[$n], $ws[$n2] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n2 */ + { 0 } +}}, +{ /* MIPS_INSVE_D (1891) - MIPS_INS_INSVE_D - insve.d $wd[$n], $ws[$n2] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n2 */ + { 0 } +}}, +{ /* MIPS_INSVE_H (1892) - MIPS_INS_INSVE_H - insve.h $wd[$n], $ws[$n2] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n2 */ + { 0 } +}}, +{ /* MIPS_INSVE_W (1893) - MIPS_INS_INSVE_W - insve.w $wd[$n], $ws[$n2] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n2 */ + { 0 } +}}, +{ /* MIPS_INSV_MM (1894) - MIPS_INS_INSV - insv $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_INS_MM (1895) - MIPS_INS_INS - ins $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_INS_MMR6 (1896) - MIPS_INS_INS - ins $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_INS_NM (1897) - MIPS_INS_INS - ins $rt, $rs, $pos, $size */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* pos */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_J (1898) - MIPS_INS_J - j $target */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* MIPS_JAL (1899) - MIPS_INS_JAL - jal $target */ +{ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* MIPS_JALR (1900) - MIPS_INS_JALR - jalr $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALR16_MM (1901) - MIPS_INS_JALR - jalr $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALR64 (1902) - MIPS_INS_JALR - jalr $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALRC16_MMR6 (1903) - MIPS_INS_JALR - jalr $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALRC16_NM (1904) - MIPS_INS_JALRC - jalrc $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALRCHB_NM (1905) - MIPS_INS_JALRC_HB - jalrc.hb $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALRC_HB_MMR6 (1906) - MIPS_INS_JALRC_HB - jalrc.hb $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALRC_MMR6 (1907) - MIPS_INS_JALRC - jalrc $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALRC_NM (1908) - MIPS_INS_JALRC - jalrc $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALRS16_MM (1909) - MIPS_INS_JALRS16 - jalrs16 $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALRS_MM (1910) - MIPS_INS_JALRS - jalrs $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALR_HB (1911) - MIPS_INS_JALR_HB - jalr.hb $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALR_HB64 (1912) - MIPS_INS_JALR_HB - jalr.hb $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALR_MM (1913) - MIPS_INS_JALR - jalr $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JALS_MM (1914) - MIPS_INS_JALS - jals $target */ +{ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* MIPS_JALX (1915) - MIPS_INS_JALX - jalx $target */ +{ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* MIPS_JALX_MM (1916) - MIPS_INS_JALX - jalx $target */ +{ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* MIPS_JAL_MM (1917) - MIPS_INS_JAL - jal $target */ +{ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{ /* MIPS_JIALC (1918) - MIPS_INS_JIALC - jialc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_JIALC64 (1919) - MIPS_INS_JIALC - jialc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_JIALC_MMR6 (1920) - MIPS_INS_JIALC - jialc $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_JIC (1921) - MIPS_INS_JIC - jic $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_JIC64 (1922) - MIPS_INS_JIC - jic $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_JIC_MMR6 (1923) - MIPS_INS_JIC - jic $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset */ + { 0 } +}}, +{ /* MIPS_JR (1924) - MIPS_INS_JR - jr $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JR16_MM (1925) - MIPS_INS_JR16 - jr16 $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JR64 (1926) - MIPS_INS_JR - jr $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JRADDIUSP (1927) - MIPS_INS_JRADDIUSP - jraddiusp $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_JRC16_MM (1928) - MIPS_INS_JRC - jrc $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JRC16_MMR6 (1929) - MIPS_INS_JRC16 - jrc16 $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JRCADDIUSP_MMR6 (1930) - MIPS_INS_JRCADDIUSP - jrcaddiusp $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_JRC_NM (1931) - MIPS_INS_JRC - jrc $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JR_HB (1932) - MIPS_INS_JR_HB - jr.hb $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JR_HB64 (1933) - MIPS_INS_JR_HB - jr.hb $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JR_HB64_R6 (1934) - MIPS_INS_JR_HB - jr.hb $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JR_HB_R6 (1935) - MIPS_INS_JR_HB - jr.hb $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JR_MM (1936) - MIPS_INS_JR - jr $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_J_MM (1937) - MIPS_INS_J - j $target */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */ + { 0 } +}}, +{{{ /* MIPS_Jal16 (1938) - MIPS_INS_INVALID - jal $imm26 + nop */ + 0 +}}}, +{{{ /* MIPS_JalB16 (1939) - MIPS_INS_INVALID - jal $imm26 # branch + nop */ + 0 +}}}, +{ /* MIPS_JrRa16 (1940) - MIPS_INS_JR - jr $$ra */ +{ + { 0 } +}}, +{ /* MIPS_JrcRa16 (1941) - MIPS_INS_JRC - jrc $$ra */ +{ + { 0 } +}}, +{ /* MIPS_JrcRx16 (1942) - MIPS_INS_JRC - jrc $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_JumpLinkReg16 (1943) - MIPS_INS_JALRC - jalrc $rx */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { 0 } +}}, +{ /* MIPS_LAPC32_NM (1944) - MIPS_INS_LAPC_H - lapc.h $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_LAPC48_NM (1945) - MIPS_INS_LAPC_B - lapc.b $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_LB (1946) - MIPS_INS_LB - lb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LB16_NM (1947) - MIPS_INS_LB - lb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_LB64 (1948) - MIPS_INS_INVALID - lb $rt, $addr */ + 0 +}}}, +{ /* MIPS_LBE (1949) - MIPS_INS_LBE - lbe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LBE_MM (1950) - MIPS_INS_LBE - lbe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBGP_NM (1951) - MIPS_INS_LB - lb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBU16_MM (1952) - MIPS_INS_LBU16 - lbu16 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_gpr16mm_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm4 */ + { 0 } +}}, +{ /* MIPS_LBU16_NM (1953) - MIPS_INS_LBU - lbu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBUGP_NM (1954) - MIPS_INS_LBU - lbu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBUX (1955) - MIPS_INS_LBUX - lbux $rd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LBUX_MM (1956) - MIPS_INS_LBUX - lbux $rd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LBUX_NM (1957) - MIPS_INS_LBUX - lbux $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBU_MMR6 (1958) - MIPS_INS_LBU - lbu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBU_NM (1959) - MIPS_INS_LBU - lbu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBUs9_NM (1960) - MIPS_INS_LBU - lbu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBX_NM (1961) - MIPS_INS_LBX - lbx $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LB_MM (1962) - MIPS_INS_LB - lb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LB_MMR6 (1963) - MIPS_INS_LB - lb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LB_NM (1964) - MIPS_INS_LB - lb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBs9_NM (1965) - MIPS_INS_LB - lb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBu (1966) - MIPS_INS_LBU - lbu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_LBu64 (1967) - MIPS_INS_INVALID - lbu $rt, $addr */ + 0 +}}}, +{ /* MIPS_LBuE (1968) - MIPS_INS_LBUE - lbue $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LBuE_MM (1969) - MIPS_INS_LBUE - lbue $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LBu_MM (1970) - MIPS_INS_LBU - lbu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LD (1971) - MIPS_INS_LD - ld $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LDC1 (1972) - MIPS_INS_LDC1 - ldc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LDC164 (1973) - MIPS_INS_LDC1 - ldc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LDC1_D64_MMR6 (1974) - MIPS_INS_LDC1 - ldc1 $ft, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LDC1_MM_D32 (1975) - MIPS_INS_LDC1 - ldc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LDC1_MM_D64 (1976) - MIPS_INS_LDC1 - ldc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LDC2 (1977) - MIPS_INS_LDC2 - ldc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LDC2_MMR6 (1978) - MIPS_INS_LDC2 - ldc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm11 */ + { 0 } +}}, +{ /* MIPS_LDC2_R6 (1979) - MIPS_INS_LDC2 - ldc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm11 */ + { 0 } +}}, +{ /* MIPS_LDC3 (1980) - MIPS_INS_LDC3 - ldc3 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LDI_B (1981) - MIPS_INS_LDI_B - ldi.b $wd, $s10 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* s10 */ + { 0 } +}}, +{ /* MIPS_LDI_D (1982) - MIPS_INS_LDI_D - ldi.d $wd, $s10 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* s10 */ + { 0 } +}}, +{ /* MIPS_LDI_H (1983) - MIPS_INS_LDI_H - ldi.h $wd, $s10 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* s10 */ + { 0 } +}}, +{ /* MIPS_LDI_W (1984) - MIPS_INS_LDI_W - ldi.w $wd, $s10 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* s10 */ + { 0 } +}}, +{ /* MIPS_LDL (1985) - MIPS_INS_LDL - ldl $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_LDPC (1986) - MIPS_INS_LDPC - ldpc $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_LDR (1987) - MIPS_INS_LDR - ldr $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_LDXC1 (1988) - MIPS_INS_LDXC1 - ldxc1 $fd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LDXC164 (1989) - MIPS_INS_LDXC1 - ldxc1 $fd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LD_B (1990) - MIPS_INS_LD_B - ld.b $wd, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm10 */ + { 0 } +}}, +{ /* MIPS_LD_D (1991) - MIPS_INS_LD_D - ld.d $wd, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm10_lsl3 */ + { 0 } +}}, +{ /* MIPS_LD_H (1992) - MIPS_INS_LD_H - ld.h $wd, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm10_lsl1 */ + { 0 } +}}, +{ /* MIPS_LD_W (1993) - MIPS_INS_LD_W - ld.w $wd, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm10_lsl2 */ + { 0 } +}}, +{{{ /* MIPS_LEA_ADDIU_NM (1994) - MIPS_INS_INVALID - addiu $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_LEA_ADDiu (1995) - MIPS_INS_INVALID - addiu $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_LEA_ADDiu64 (1996) - MIPS_INS_INVALID - daddiu $rt, $addr */ + 0 +}}}, +{{{ /* MIPS_LEA_ADDiu_MM (1997) - MIPS_INS_INVALID - addiu $rt, $addr */ + 0 +}}}, +{ /* MIPS_LH (1998) - MIPS_INS_LH - lh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LH16_NM (1999) - MIPS_INS_LH - lh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_LH64 (2000) - MIPS_INS_INVALID - lh $rt, $addr */ + 0 +}}}, +{ /* MIPS_LHE (2001) - MIPS_INS_LHE - lhe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LHE_MM (2002) - MIPS_INS_LHE - lhe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LHGP_NM (2003) - MIPS_INS_LH - lh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHU16_MM (2004) - MIPS_INS_LHU16 - lhu16 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_gpr16mm_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm4 */ + { 0 } +}}, +{ /* MIPS_LHU16_NM (2005) - MIPS_INS_LHU - lhu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHUGP_NM (2006) - MIPS_INS_LHU - lhu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHUXS_NM (2007) - MIPS_INS_LHUXS - lhuxs $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHUX_NM (2008) - MIPS_INS_LHUX - lhux $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHU_NM (2009) - MIPS_INS_LHU - lhu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHUs9_NM (2010) - MIPS_INS_LHU - lhu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHX (2011) - MIPS_INS_LHX - lhx $rd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LHXS_NM (2012) - MIPS_INS_LHXS - lhxs $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHX_MM (2013) - MIPS_INS_LHX - lhx $rd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LHX_NM (2014) - MIPS_INS_LHX - lhx $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LH_MM (2015) - MIPS_INS_LH - lh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LH_NM (2016) - MIPS_INS_LH - lh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHs9_NM (2017) - MIPS_INS_LH - lh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LHu (2018) - MIPS_INS_LHU - lhu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_LHu64 (2019) - MIPS_INS_INVALID - lhu $rt, $addr */ + 0 +}}}, +{ /* MIPS_LHuE (2020) - MIPS_INS_LHUE - lhue $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LHuE_MM (2021) - MIPS_INS_LHUE - lhue $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LHu_MM (2022) - MIPS_INS_LHU - lhu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LI16_MM (2023) - MIPS_INS_LI16 - li16 $rd, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_LI16_MMR6 (2024) - MIPS_INS_LI16 - li16 $rd, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_LI16_NM (2025) - MIPS_INS_LI - li $rt, $eu */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* eu */ + { 0 } +}}, +{ /* MIPS_LI48_NM (2026) - MIPS_INS_LI - li[48] $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_LL (2027) - MIPS_INS_LL - ll $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LL64 (2028) - MIPS_INS_LL - ll $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LL64_R6 (2029) - MIPS_INS_LL - ll $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LLD (2030) - MIPS_INS_LLD - lld $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LLD_R6 (2031) - MIPS_INS_LLD - lld $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LLE (2032) - MIPS_INS_LLE - lle $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LLE_MM (2033) - MIPS_INS_LLE - lle $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LLWP_NM (2034) - MIPS_INS_LLWP - llwp $rt, $ru, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ru */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LL_MM (2035) - MIPS_INS_LL - ll $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_LL_MMR6 (2036) - MIPS_INS_LL - ll $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LL_NM (2037) - MIPS_INS_LL - ll $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LL_R6 (2038) - MIPS_INS_LL - ll $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LSA (2039) - MIPS_INS_LSA - lsa $rd, $rs, $rt, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_LSA_MMR6 (2040) - MIPS_INS_LSA - lsa $rt, $rs, $rd, $imm2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm2 */ + { 0 } +}}, +{ /* MIPS_LSA_NM (2041) - MIPS_INS_LSA - lsa $rd, $rs, $rt, $shift */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift */ + { 0 } +}}, +{ /* MIPS_LSA_R6 (2042) - MIPS_INS_LSA - lsa $rd, $rs, $rt, $imm2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm2 */ + { 0 } +}}, +{ /* MIPS_LUI_MMR6 (2043) - MIPS_INS_LUI - lui $rt, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_LUI_NM (2044) - MIPS_INS_LUI - lui $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_LUXC1 (2045) - MIPS_INS_LUXC1 - luxc1 $fd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LUXC164 (2046) - MIPS_INS_LUXC1 - luxc1 $fd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LUXC1_MM (2047) - MIPS_INS_LUXC1 - luxc1 $fd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LUi (2048) - MIPS_INS_LUI - lui $rt, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{{{ /* MIPS_LUi64 (2049) - MIPS_INS_INVALID - lui $rt, $imm16 */ + 0 +}}}, +{ /* MIPS_LUi_MM (2050) - MIPS_INS_LUI - lui $rt, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_LW (2051) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LW16_MM (2052) - MIPS_INS_LW16 - lw16 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_gpr16mm_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm4 */ + { 0 } +}}, +{ /* MIPS_LW16_NM (2053) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LW4x4_NM (2054) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_LW64 (2055) - MIPS_INS_INVALID - lw $rt, $addr */ + 0 +}}}, +{ /* MIPS_LWC1 (2056) - MIPS_INS_LWC1 - lwc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWC1_MM (2057) - MIPS_INS_LWC1 - lwc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWC2 (2058) - MIPS_INS_LWC2 - lwc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWC2_MMR6 (2059) - MIPS_INS_LWC2 - lwc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm11 */ + { 0 } +}}, +{ /* MIPS_LWC2_R6 (2060) - MIPS_INS_LWC2 - lwc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm11 */ + { 0 } +}}, +{ /* MIPS_LWC3 (2061) - MIPS_INS_LWC3 - lwc3 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWDSP (2062) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWDSP_MM (2063) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWE (2064) - MIPS_INS_LWE - lwe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LWE_MM (2065) - MIPS_INS_LWE - lwe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_LWGP16_NM (2066) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWGP_MM (2067) - MIPS_INS_LW - lw $rt, $offset */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* offset - ptr_gp_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* offset - simm7_lsl2 */ + { 0 } +}}, +{ /* MIPS_LWGP_NM (2068) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWL (2069) - MIPS_INS_LWL - lwl $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{{{ /* MIPS_LWL64 (2070) - MIPS_INS_INVALID - lwl $rt, $addr */ + 0 +}}}, +{ /* MIPS_LWLE (2071) - MIPS_INS_LWLE - lwle $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_LWLE_MM (2072) - MIPS_INS_LWLE - lwle $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_LWL_MM (2073) - MIPS_INS_LWL - lwl $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_LWM16_MM (2074) - MIPS_INS_LWM16 - lwm16 $rt, $addr */ +{ + { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_sp_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - uimm8 */ + { 0 } +}}, +{ /* MIPS_LWM16_MMR6 (2075) - MIPS_INS_LWM16 - lwm16 $rt, $addr */ +{ + { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_sp_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - uimm8 */ + { 0 } +}}, +{ /* MIPS_LWM32_MM (2076) - MIPS_INS_LWM32 - lwm32 $rt, $addr */ +{ + { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_LWM_NM (2077) - MIPS_INS_LWM - lwm $rt, $addr, $rcount */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rcount */ + { 0 } +}}, +{ /* MIPS_LWPC (2078) - MIPS_INS_LWPC - lwpc $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_LWPC_MMR6 (2079) - MIPS_INS_LWPC - lwpc $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_LWPC_NM (2080) - MIPS_INS_LWPC - lwpc $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_LWP_MM (2081) - MIPS_INS_LWP - lwp $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_LWR (2082) - MIPS_INS_LWR - lwr $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{{{ /* MIPS_LWR64 (2083) - MIPS_INS_INVALID - lwr $rt, $addr */ + 0 +}}}, +{ /* MIPS_LWRE (2084) - MIPS_INS_LWRE - lwre $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_LWRE_MM (2085) - MIPS_INS_LWRE - lwre $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_LWR_MM (2086) - MIPS_INS_LWR - lwr $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_LWSP16_NM (2087) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWSP_MM (2088) - MIPS_INS_LW - lw $rt, $offset */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* offset - ptr_sp_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - simm5 */ + { 0 } +}}, +{ /* MIPS_LWUPC (2089) - MIPS_INS_LWUPC - lwupc $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_LWU_MM (2090) - MIPS_INS_LWU - lwu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_LWX (2091) - MIPS_INS_LWX - lwx $rd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LWXC1 (2092) - MIPS_INS_LWXC1 - lwxc1 $fd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LWXC1_MM (2093) - MIPS_INS_LWXC1 - lwxc1 $fd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LWXS16_NM (2094) - MIPS_INS_LWXS - lwxs $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWXS_MM (2095) - MIPS_INS_LWXS - lwxs $rd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LWXS_NM (2096) - MIPS_INS_LWXS - lwxs $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWX_MM (2097) - MIPS_INS_LWX - lwx $rd, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_LWX_NM (2098) - MIPS_INS_LWX - lwx $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LW_MM (2099) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LW_MMR6 (2100) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LW_NM (2101) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWs9_NM (2102) - MIPS_INS_LW - lw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_LWu (2103) - MIPS_INS_LWU - lwu $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_LbRxRyOffMemX16 (2104) - MIPS_INS_INVALID - lb $ry, $addr */ + 0 +}}}, +{{{ /* MIPS_LbuRxRyOffMemX16 (2105) - MIPS_INS_INVALID - lbu $ry, $addr */ + 0 +}}}, +{{{ /* MIPS_LhRxRyOffMemX16 (2106) - MIPS_INS_INVALID - lh $ry, $addr */ + 0 +}}}, +{{{ /* MIPS_LhuRxRyOffMemX16 (2107) - MIPS_INS_INVALID - lhu $ry, $addr */ + 0 +}}}, +{ /* MIPS_LiRxImm16 (2108) - MIPS_INS_LI - li $rx, $imm8 # 16 bit inst */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{{{ /* MIPS_LiRxImmAlignX16 (2109) - MIPS_INS_INVALID - .align 2 + li $rx, $imm16 */ + 0 +}}}, +{ /* MIPS_LiRxImmX16 (2110) - MIPS_INS_LI - li $rx, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_LwRxPcTcp16 (2111) - MIPS_INS_LW - lw $rx, $imm8 # 16 bit inst */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { 0 } +}}, +{ /* MIPS_LwRxPcTcpX16 (2112) - MIPS_INS_LW - lw $rx, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* size */ + { 0 } +}}, +{{{ /* MIPS_LwRxRyOffMemX16 (2113) - MIPS_INS_INVALID - lw $ry, $addr */ + 0 +}}}, +{ /* MIPS_LwRxSpImmX16 (2114) - MIPS_INS_LW - lw $ry, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - CPU16RegsPlusSP */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_MADD (2115) - MIPS_INS_MADD - madd $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MADDF_D (2116) - MIPS_INS_MADDF_D - maddf.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MADDF_D_MMR6 (2117) - MIPS_INS_MADDF_D - maddf.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MADDF_S (2118) - MIPS_INS_MADDF_S - maddf.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MADDF_S_MMR6 (2119) - MIPS_INS_MADDF_S - maddf.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MADDR_Q_H (2120) - MIPS_INS_MADDR_Q_H - maddr_q.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MADDR_Q_W (2121) - MIPS_INS_MADDR_Q_W - maddr_q.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MADDU (2122) - MIPS_INS_MADDU - maddu $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MADDU_DSP (2123) - MIPS_INS_MADDU - maddu $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MADDU_DSP_MM (2124) - MIPS_INS_MADDU - maddu $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MADDU_MM (2125) - MIPS_INS_MADDU - maddu $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MADDV_B (2126) - MIPS_INS_MADDV_B - maddv.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MADDV_D (2127) - MIPS_INS_MADDV_D - maddv.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MADDV_H (2128) - MIPS_INS_MADDV_H - maddv.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MADDV_W (2129) - MIPS_INS_MADDV_W - maddv.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MADD_D32 (2130) - MIPS_INS_MADD_D - madd.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MADD_D32_MM (2131) - MIPS_INS_MADD_D - madd.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MADD_D64 (2132) - MIPS_INS_MADD_D - madd.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MADD_DSP (2133) - MIPS_INS_MADD - madd $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MADD_DSP_MM (2134) - MIPS_INS_MADD - madd $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MADD_MM (2135) - MIPS_INS_MADD - madd $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MADD_Q_H (2136) - MIPS_INS_MADD_Q_H - madd_q.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MADD_Q_W (2137) - MIPS_INS_MADD_Q_W - madd_q.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MADD_S (2138) - MIPS_INS_MADD_S - madd.s $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MADD_S_MM (2139) - MIPS_INS_MADD_S - madd.s $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MAQ_SA_W_PHL (2140) - MIPS_INS_MAQ_SA_W_PHL - maq_sa.w.phl $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MAQ_SA_W_PHL_MM (2141) - MIPS_INS_MAQ_SA_W_PHL - maq_sa.w.phl $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MAQ_SA_W_PHR (2142) - MIPS_INS_MAQ_SA_W_PHR - maq_sa.w.phr $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MAQ_SA_W_PHR_MM (2143) - MIPS_INS_MAQ_SA_W_PHR - maq_sa.w.phr $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MAQ_S_W_PHL (2144) - MIPS_INS_MAQ_S_W_PHL - maq_s.w.phl $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MAQ_S_W_PHL_MM (2145) - MIPS_INS_MAQ_S_W_PHL - maq_s.w.phl $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MAQ_S_W_PHR (2146) - MIPS_INS_MAQ_S_W_PHR - maq_s.w.phr $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MAQ_S_W_PHR_MM (2147) - MIPS_INS_MAQ_S_W_PHR - maq_s.w.phr $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MAXA_D (2148) - MIPS_INS_MAXA_D - maxa.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MAXA_D_MMR6 (2149) - MIPS_INS_MAXA_D - maxa.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MAXA_S (2150) - MIPS_INS_MAXA_S - maxa.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MAXA_S_MMR6 (2151) - MIPS_INS_MAXA_S - maxa.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MAXI_S_B (2152) - MIPS_INS_MAXI_S_B - maxi_s.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MAXI_S_D (2153) - MIPS_INS_MAXI_S_D - maxi_s.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MAXI_S_H (2154) - MIPS_INS_MAXI_S_H - maxi_s.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MAXI_S_W (2155) - MIPS_INS_MAXI_S_W - maxi_s.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MAXI_U_B (2156) - MIPS_INS_MAXI_U_B - maxi_u.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MAXI_U_D (2157) - MIPS_INS_MAXI_U_D - maxi_u.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MAXI_U_H (2158) - MIPS_INS_MAXI_U_H - maxi_u.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MAXI_U_W (2159) - MIPS_INS_MAXI_U_W - maxi_u.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MAX_A_B (2160) - MIPS_INS_MAX_A_B - max_a.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_A_D (2161) - MIPS_INS_MAX_A_D - max_a.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_A_H (2162) - MIPS_INS_MAX_A_H - max_a.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_A_W (2163) - MIPS_INS_MAX_A_W - max_a.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_D (2164) - MIPS_INS_MAX_D - max.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MAX_D_MMR6 (2165) - MIPS_INS_MAX_D - max.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MAX_S (2166) - MIPS_INS_MAX_S - max.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MAX_S_B (2167) - MIPS_INS_MAX_S_B - max_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_S_D (2168) - MIPS_INS_MAX_S_D - max_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_S_H (2169) - MIPS_INS_MAX_S_H - max_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_S_MMR6 (2170) - MIPS_INS_MAX_S - max.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MAX_S_W (2171) - MIPS_INS_MAX_S_W - max_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_U_B (2172) - MIPS_INS_MAX_U_B - max_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_U_D (2173) - MIPS_INS_MAX_U_D - max_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_U_H (2174) - MIPS_INS_MAX_U_H - max_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MAX_U_W (2175) - MIPS_INS_MAX_U_W - max_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MFC0 (2176) - MIPS_INS_MFC0 - mfc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFC0Sel_NM (2177) - MIPS_INS_MFC0 - mfc0 $rt, $c0s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c0s */ + { 0 } +}}, +{ /* MIPS_MFC0_MMR6 (2178) - MIPS_INS_MFC0 - mfc0 $rt, $rs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFC0_NM (2179) - MIPS_INS_MFC0 - mfc0 $rt, $c0s, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c0s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFC1 (2180) - MIPS_INS_MFC1 - mfc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_MFC1_D64 (2181) - MIPS_INS_MFC1 - mfc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_MFC1_MM (2182) - MIPS_INS_MFC1 - mfc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_MFC1_MMR6 (2183) - MIPS_INS_MFC1 - mfc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_MFC2 (2184) - MIPS_INS_MFC2 - mfc2 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFC2_MMR6 (2185) - MIPS_INS_MFC2 - mfc2 $rt, $impl */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* impl */ + { 0 } +}}, +{ /* MIPS_MFGC0 (2186) - MIPS_INS_MFGC0 - mfgc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFGC0_MM (2187) - MIPS_INS_MFGC0 - mfgc0 $rt, $rs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFHC0Sel_NM (2188) - MIPS_INS_MFHC0 - mfhc0 $rt, $c0s */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c0s */ + { 0 } +}}, +{ /* MIPS_MFHC0_MMR6 (2189) - MIPS_INS_MFHC0 - mfhc0 $rt, $rs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFHC0_NM (2190) - MIPS_INS_MFHC0 - mfhc0 $rt, $c0s, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c0s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFHC1_D32 (2191) - MIPS_INS_MFHC1 - mfhc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_MFHC1_D32_MM (2192) - MIPS_INS_MFHC1 - mfhc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_MFHC1_D64 (2193) - MIPS_INS_MFHC1 - mfhc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_MFHC1_D64_MM (2194) - MIPS_INS_MFHC1 - mfhc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_MFHC2_MMR6 (2195) - MIPS_INS_MFHC2 - mfhc2 $rt, $impl */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* impl */ + { 0 } +}}, +{ /* MIPS_MFHGC0 (2196) - MIPS_INS_MFHGC0 - mfhgc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFHGC0_MM (2197) - MIPS_INS_MFHGC0 - mfhgc0 $rt, $rs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MFHI (2198) - MIPS_INS_MFHI - mfhi $rd */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_MFHI16_MM (2199) - MIPS_INS_MFHI16 - mfhi16 $rd */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{{{ /* MIPS_MFHI64 (2200) - MIPS_INS_INVALID - mfhi $rd */ + 0 +}}}, +{ /* MIPS_MFHI_DSP (2201) - MIPS_INS_MFHI - mfhi $rd, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{ /* MIPS_MFHI_DSP_MM (2202) - MIPS_INS_MFHI - mfhi $rs, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{ /* MIPS_MFHI_MM (2203) - MIPS_INS_MFHI - mfhi $rd */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_MFLO (2204) - MIPS_INS_MFLO - mflo $rd */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_MFLO16_MM (2205) - MIPS_INS_MFLO16 - mflo16 $rd */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{{{ /* MIPS_MFLO64 (2206) - MIPS_INS_INVALID - mflo $rd */ + 0 +}}}, +{ /* MIPS_MFLO_DSP (2207) - MIPS_INS_MFLO - mflo $rd, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{ /* MIPS_MFLO_DSP_MM (2208) - MIPS_INS_MFLO - mflo $rs, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { 0 } +}}, +{ /* MIPS_MFLO_MM (2209) - MIPS_INS_MFLO - mflo $rd */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_MFTR (2210) - MIPS_INS_MFTR - mftr $rd, $rt, $u, $sel, $h */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* h */ + { 0 } +}}, +{ /* MIPS_MFTR_NM (2211) - MIPS_INS_MFTR - mftr $rd, $rt, $u, $sel, $h */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* h */ + { 0 } +}}, +{ /* MIPS_MINA_D (2212) - MIPS_INS_MINA_D - mina.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MINA_D_MMR6 (2213) - MIPS_INS_MINA_D - mina.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MINA_S (2214) - MIPS_INS_MINA_S - mina.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MINA_S_MMR6 (2215) - MIPS_INS_MINA_S - mina.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MINI_S_B (2216) - MIPS_INS_MINI_S_B - mini_s.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MINI_S_D (2217) - MIPS_INS_MINI_S_D - mini_s.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MINI_S_H (2218) - MIPS_INS_MINI_S_H - mini_s.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MINI_S_W (2219) - MIPS_INS_MINI_S_W - mini_s.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MINI_U_B (2220) - MIPS_INS_MINI_U_B - mini_u.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MINI_U_D (2221) - MIPS_INS_MINI_U_D - mini_u.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MINI_U_H (2222) - MIPS_INS_MINI_U_H - mini_u.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MINI_U_W (2223) - MIPS_INS_MINI_U_W - mini_u.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_MIN_A_B (2224) - MIPS_INS_MIN_A_B - min_a.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_A_D (2225) - MIPS_INS_MIN_A_D - min_a.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_A_H (2226) - MIPS_INS_MIN_A_H - min_a.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_A_W (2227) - MIPS_INS_MIN_A_W - min_a.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_D (2228) - MIPS_INS_MIN_D - min.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MIN_D_MMR6 (2229) - MIPS_INS_MIN_D - min.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MIN_S (2230) - MIPS_INS_MIN_S - min.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MIN_S_B (2231) - MIPS_INS_MIN_S_B - min_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_S_D (2232) - MIPS_INS_MIN_S_D - min_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_S_H (2233) - MIPS_INS_MIN_S_H - min_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_S_MMR6 (2234) - MIPS_INS_MIN_S - min.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MIN_S_W (2235) - MIPS_INS_MIN_S_W - min_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_U_B (2236) - MIPS_INS_MIN_U_B - min_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_U_D (2237) - MIPS_INS_MIN_U_D - min_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_U_H (2238) - MIPS_INS_MIN_U_H - min_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MIN_U_W (2239) - MIPS_INS_MIN_U_W - min_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MOD (2240) - MIPS_INS_MOD - mod $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MODSUB (2241) - MIPS_INS_MODSUB - modsub $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MODSUB_MM (2242) - MIPS_INS_MODSUB - modsub $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MODU (2243) - MIPS_INS_MODU - modu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MODU_MMR6 (2244) - MIPS_INS_MODU - modu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MODU_NM (2245) - MIPS_INS_MODU - modu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MOD_MMR6 (2246) - MIPS_INS_MOD - mod $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MOD_NM (2247) - MIPS_INS_MOD - mod $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MOD_S_B (2248) - MIPS_INS_MOD_S_B - mod_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MOD_S_D (2249) - MIPS_INS_MOD_S_D - mod_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MOD_S_H (2250) - MIPS_INS_MOD_S_H - mod_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MOD_S_W (2251) - MIPS_INS_MOD_S_W - mod_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MOD_U_B (2252) - MIPS_INS_MOD_U_B - mod_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MOD_U_D (2253) - MIPS_INS_MOD_U_D - mod_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MOD_U_H (2254) - MIPS_INS_MOD_U_H - mod_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MOD_U_W (2255) - MIPS_INS_MOD_U_W - mod_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MOVE16_MM (2256) - MIPS_INS_MOVE - move $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MOVE16_MMR6 (2257) - MIPS_INS_MOVE16 - move16 $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MOVEBALC_NM (2258) - MIPS_INS_MOVE_BALC - move.balc $rd, $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM | CS_OP_MEM, CS_AC_INVALID, { CS_DATA_TYPE_iPTR, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_MOVEPREV_NM (2259) - MIPS_INS_MOVEP - movep $dst1, $dst2, $src1, $src2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src2 */ + { 0 } +}}, +{ /* MIPS_MOVEP_MM (2260) - MIPS_INS_MOVEP - movep $rd1, $rd2, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MOVEP_MMR6 (2261) - MIPS_INS_MOVEP - movep $rd1, $rd2, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MOVEP_NM (2262) - MIPS_INS_MOVEP - movep $dst1, $dst2, $src1, $src2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src2 */ + { 0 } +}}, +{ /* MIPS_MOVE_NM (2263) - MIPS_INS_MOVE - move $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MOVE_V (2264) - MIPS_INS_MOVE_V - move.v $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_MOVF_D32 (2265) - MIPS_INS_MOVF_D - movf.d $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVF_D32_MM (2266) - MIPS_INS_MOVF_D - movf.d $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVF_D64 (2267) - MIPS_INS_MOVF_D - movf.d $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVF_I (2268) - MIPS_INS_MOVF - movf $rd, $rs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{{{ /* MIPS_MOVF_I64 (2269) - MIPS_INS_INVALID - movf $rd, $rs, $fcc */ + 0 +}}}, +{ /* MIPS_MOVF_I_MM (2270) - MIPS_INS_MOVF - movf $rd, $rs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVF_S (2271) - MIPS_INS_MOVF_S - movf.s $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVF_S_MM (2272) - MIPS_INS_MOVF_S - movf.s $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{{{ /* MIPS_MOVN_I64_D64 (2273) - MIPS_INS_INVALID - movn.d $fd, $fs, $rt */ + 0 +}}}, +{{{ /* MIPS_MOVN_I64_I (2274) - MIPS_INS_INVALID - movn $rd, $rs, $rt */ + 0 +}}}, +{{{ /* MIPS_MOVN_I64_I64 (2275) - MIPS_INS_INVALID - movn $rd, $rs, $rt */ + 0 +}}}, +{{{ /* MIPS_MOVN_I64_S (2276) - MIPS_INS_INVALID - movn.s $fd, $fs, $rt */ + 0 +}}}, +{ /* MIPS_MOVN_I_D32 (2277) - MIPS_INS_MOVN_D - movn.d $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVN_I_D32_MM (2278) - MIPS_INS_MOVN_D - movn.d $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVN_I_D64 (2279) - MIPS_INS_MOVN_D - movn.d $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVN_I_I (2280) - MIPS_INS_MOVN - movn $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{{{ /* MIPS_MOVN_I_I64 (2281) - MIPS_INS_INVALID - movn $rd, $rs, $rt */ + 0 +}}}, +{ /* MIPS_MOVN_I_MM (2282) - MIPS_INS_MOVN - movn $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVN_I_S (2283) - MIPS_INS_MOVN_S - movn.s $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVN_I_S_MM (2284) - MIPS_INS_MOVN_S - movn.s $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVN_NM (2285) - MIPS_INS_MOVN - movn $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVT_D32 (2286) - MIPS_INS_MOVT_D - movt.d $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVT_D32_MM (2287) - MIPS_INS_MOVT_D - movt.d $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVT_D64 (2288) - MIPS_INS_MOVT_D - movt.d $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVT_I (2289) - MIPS_INS_MOVT - movt $rd, $rs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{{{ /* MIPS_MOVT_I64 (2290) - MIPS_INS_INVALID - movt $rd, $rs, $fcc */ + 0 +}}}, +{ /* MIPS_MOVT_I_MM (2291) - MIPS_INS_MOVT - movt $rd, $rs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVT_S (2292) - MIPS_INS_MOVT_S - movt.s $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVT_S_MM (2293) - MIPS_INS_MOVT_S - movt.s $fd, $fs, $fcc */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcc */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{{{ /* MIPS_MOVZ_I64_D64 (2294) - MIPS_INS_INVALID - movz.d $fd, $fs, $rt */ + 0 +}}}, +{{{ /* MIPS_MOVZ_I64_I (2295) - MIPS_INS_INVALID - movz $rd, $rs, $rt */ + 0 +}}}, +{{{ /* MIPS_MOVZ_I64_I64 (2296) - MIPS_INS_INVALID - movz $rd, $rs, $rt */ + 0 +}}}, +{{{ /* MIPS_MOVZ_I64_S (2297) - MIPS_INS_INVALID - movz.s $fd, $fs, $rt */ + 0 +}}}, +{ /* MIPS_MOVZ_I_D32 (2298) - MIPS_INS_MOVZ_D - movz.d $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVZ_I_D32_MM (2299) - MIPS_INS_MOVZ_D - movz.d $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVZ_I_D64 (2300) - MIPS_INS_MOVZ_D - movz.d $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVZ_I_I (2301) - MIPS_INS_MOVZ - movz $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{{{ /* MIPS_MOVZ_I_I64 (2302) - MIPS_INS_INVALID - movz $rd, $rs, $rt */ + 0 +}}}, +{ /* MIPS_MOVZ_I_MM (2303) - MIPS_INS_MOVZ - movz $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVZ_I_S (2304) - MIPS_INS_MOVZ_S - movz.s $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVZ_I_S_MM (2305) - MIPS_INS_MOVZ_S - movz.s $fd, $fs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MOVZ_NM (2306) - MIPS_INS_MOVZ - movz $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* F */ + { 0 } +}}, +{ /* MIPS_MSUB (2307) - MIPS_INS_MSUB - msub $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MSUBF_D (2308) - MIPS_INS_MSUBF_D - msubf.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MSUBF_D_MMR6 (2309) - MIPS_INS_MSUBF_D - msubf.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MSUBF_S (2310) - MIPS_INS_MSUBF_S - msubf.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MSUBF_S_MMR6 (2311) - MIPS_INS_MSUBF_S - msubf.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MSUBR_Q_H (2312) - MIPS_INS_MSUBR_Q_H - msubr_q.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MSUBR_Q_W (2313) - MIPS_INS_MSUBR_Q_W - msubr_q.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MSUBU (2314) - MIPS_INS_MSUBU - msubu $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MSUBU_DSP (2315) - MIPS_INS_MSUBU - msubu $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MSUBU_DSP_MM (2316) - MIPS_INS_MSUBU - msubu $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MSUBU_MM (2317) - MIPS_INS_MSUBU - msubu $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MSUBV_B (2318) - MIPS_INS_MSUBV_B - msubv.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MSUBV_D (2319) - MIPS_INS_MSUBV_D - msubv.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MSUBV_H (2320) - MIPS_INS_MSUBV_H - msubv.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MSUBV_W (2321) - MIPS_INS_MSUBV_W - msubv.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MSUB_D32 (2322) - MIPS_INS_MSUB_D - msub.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MSUB_D32_MM (2323) - MIPS_INS_MSUB_D - msub.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MSUB_D64 (2324) - MIPS_INS_MSUB_D - msub.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MSUB_DSP (2325) - MIPS_INS_MSUB - msub $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MSUB_DSP_MM (2326) - MIPS_INS_MSUB - msub $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MSUB_MM (2327) - MIPS_INS_MSUB - msub $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MSUB_Q_H (2328) - MIPS_INS_MSUB_Q_H - msub_q.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MSUB_Q_W (2329) - MIPS_INS_MSUB_Q_W - msub_q.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MSUB_S (2330) - MIPS_INS_MSUB_S - msub.s $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MSUB_S_MM (2331) - MIPS_INS_MSUB_S - msub.s $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MTC0 (2332) - MIPS_INS_MTC0 - mtc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTC0Sel_NM (2333) - MIPS_INS_MTC0 - mtc0 $rt, $c0s */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c0s */ + { 0 } +}}, +{ /* MIPS_MTC0_MMR6 (2334) - MIPS_INS_MTC0 - mtc0 $rt, $rs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTC0_NM (2335) - MIPS_INS_MTC0 - mtc0 $rt, $c0s, $sel */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c0s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTC1 (2336) - MIPS_INS_MTC1 - mtc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTC1_D64 (2337) - MIPS_INS_MTC1 - mtc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTC1_D64_MM (2338) - MIPS_INS_MTC1 - mtc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTC1_MM (2339) - MIPS_INS_MTC1 - mtc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTC1_MMR6 (2340) - MIPS_INS_MTC1 - mtc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTC2 (2341) - MIPS_INS_MTC2 - mtc2 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTC2_MMR6 (2342) - MIPS_INS_MTC2 - mtc2 $rt, $impl */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* impl */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTGC0 (2343) - MIPS_INS_MTGC0 - mtgc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTGC0_MM (2344) - MIPS_INS_MTGC0 - mtgc0 $rt, $rs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTHC0Sel_NM (2345) - MIPS_INS_MTHC0 - mthc0 $rt, $c0s */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c0s */ + { 0 } +}}, +{ /* MIPS_MTHC0_MMR6 (2346) - MIPS_INS_MTHC0 - mthc0 $rt, $rs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTHC0_NM (2347) - MIPS_INS_MTHC0 - mthc0 $rt, $c0s, $sel */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* c0s */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTHC1_D32 (2348) - MIPS_INS_MTHC1 - mthc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTHC1_D32_MM (2349) - MIPS_INS_MTHC1 - mthc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTHC1_D64 (2350) - MIPS_INS_MTHC1 - mthc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTHC1_D64_MM (2351) - MIPS_INS_MTHC1 - mthc1 $rt, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTHC2_MMR6 (2352) - MIPS_INS_MTHC2 - mthc2 $rt, $impl */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* impl */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MTHGC0 (2353) - MIPS_INS_MTHGC0 - mthgc0 $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTHGC0_MM (2354) - MIPS_INS_MTHGC0 - mthgc0 $rt, $rs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_MTHI (2355) - MIPS_INS_MTHI - mthi $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{{{ /* MIPS_MTHI64 (2356) - MIPS_INS_INVALID - mthi $rs */ + 0 +}}}, +{ /* MIPS_MTHI_DSP (2357) - MIPS_INS_MTHI - mthi $rs, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTHI_DSP_MM (2358) - MIPS_INS_MTHI - mthi $rs, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTHI_MM (2359) - MIPS_INS_MTHI - mthi $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTHLIP (2360) - MIPS_INS_MTHLIP - mthlip $rs, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MTHLIP_MM (2361) - MIPS_INS_MTHLIP - mthlip $rs, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MTLO (2362) - MIPS_INS_MTLO - mtlo $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{{{ /* MIPS_MTLO64 (2363) - MIPS_INS_INVALID - mtlo $rs */ + 0 +}}}, +{ /* MIPS_MTLO_DSP (2364) - MIPS_INS_MTLO - mtlo $rs, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTLO_DSP_MM (2365) - MIPS_INS_MTLO - mtlo $rs, $ac */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTLO_MM (2366) - MIPS_INS_MTLO - mtlo $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTM0 (2367) - MIPS_INS_MTM0 - mtm0 $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTM1 (2368) - MIPS_INS_MTM1 - mtm1 $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTM2 (2369) - MIPS_INS_MTM2 - mtm2 $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTP0 (2370) - MIPS_INS_MTP0 - mtp0 $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTP1 (2371) - MIPS_INS_MTP1 - mtp1 $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTP2 (2372) - MIPS_INS_MTP2 - mtp2 $rs */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MTTR (2373) - MIPS_INS_MTTR - mttr $rt, $rd, $u, $sel, $h */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* h */ + { 0 } +}}, +{ /* MIPS_MTTR_NM (2374) - MIPS_INS_MTTR - mttr $rt, $rd, $u, $sel, $h */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* h */ + { 0 } +}}, +{ /* MIPS_MUH (2375) - MIPS_INS_MUH - muh $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUHU (2376) - MIPS_INS_MUHU - muhu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUHU_MMR6 (2377) - MIPS_INS_MUHU - muhu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUHU_NM (2378) - MIPS_INS_MUHU - muhu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUH_MMR6 (2379) - MIPS_INS_MUH - muh $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUH_NM (2380) - MIPS_INS_MUH - muh $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUL (2381) - MIPS_INS_MUL - mul $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUL4x4_NM (2382) - MIPS_INS_MUL - mul $dst, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_MULEQ_S_W_PHL (2383) - MIPS_INS_MULEQ_S_W_PHL - muleq_s.w.phl $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULEQ_S_W_PHL_MM (2384) - MIPS_INS_MULEQ_S_W_PHL - muleq_s.w.phl $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULEQ_S_W_PHR (2385) - MIPS_INS_MULEQ_S_W_PHR - muleq_s.w.phr $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULEQ_S_W_PHR_MM (2386) - MIPS_INS_MULEQ_S_W_PHR - muleq_s.w.phr $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULEU_S_PH_QBL (2387) - MIPS_INS_MULEU_S_PH_QBL - muleu_s.ph.qbl $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULEU_S_PH_QBL_MM (2388) - MIPS_INS_MULEU_S_PH_QBL - muleu_s.ph.qbl $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULEU_S_PH_QBR (2389) - MIPS_INS_MULEU_S_PH_QBR - muleu_s.ph.qbr $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULEU_S_PH_QBR_MM (2390) - MIPS_INS_MULEU_S_PH_QBR - muleu_s.ph.qbr $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULQ_RS_PH (2391) - MIPS_INS_MULQ_RS_PH - mulq_rs.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULQ_RS_PH_MM (2392) - MIPS_INS_MULQ_RS_PH - mulq_rs.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULQ_RS_W (2393) - MIPS_INS_MULQ_RS_W - mulq_rs.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULQ_RS_W_MMR2 (2394) - MIPS_INS_MULQ_RS_W - mulq_rs.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULQ_S_PH (2395) - MIPS_INS_MULQ_S_PH - mulq_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULQ_S_PH_MMR2 (2396) - MIPS_INS_MULQ_S_PH - mulq_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULQ_S_W (2397) - MIPS_INS_MULQ_S_W - mulq_s.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULQ_S_W_MMR2 (2398) - MIPS_INS_MULQ_S_W - mulq_s.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULR_PS64 (2399) - MIPS_INS_MULR_PS - mulr.ps $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_MULR_Q_H (2400) - MIPS_INS_MULR_Q_H - mulr_q.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MULR_Q_W (2401) - MIPS_INS_MULR_Q_W - mulr_q.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MULSAQ_S_W_PH (2402) - MIPS_INS_MULSAQ_S_W_PH - mulsaq_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MULSAQ_S_W_PH_MM (2403) - MIPS_INS_MULSAQ_S_W_PH - mulsaq_s.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MULSA_W_PH (2404) - MIPS_INS_MULSA_W_PH - mulsa.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MULSA_W_PH_MMR2 (2405) - MIPS_INS_MULSA_W_PH - mulsa.w.ph $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_MULT (2406) - MIPS_INS_MULT - mult $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULTU_DSP (2407) - MIPS_INS_MULTU - multu $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULTU_DSP_MM (2408) - MIPS_INS_MULTU - multu $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULT_DSP (2409) - MIPS_INS_MULT - mult $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULT_DSP_MM (2410) - MIPS_INS_MULT - mult $ac, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULT_MM (2411) - MIPS_INS_MULT - mult $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULTu (2412) - MIPS_INS_MULTU - multu $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULTu_MM (2413) - MIPS_INS_MULTU - multu $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULU (2414) - MIPS_INS_MULU - mulu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULU_MMR6 (2415) - MIPS_INS_MULU - mulu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULU_NM (2416) - MIPS_INS_MULU - mulu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MULV_B (2417) - MIPS_INS_MULV_B - mulv.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MULV_D (2418) - MIPS_INS_MULV_D - mulv.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MULV_H (2419) - MIPS_INS_MULV_H - mulv.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MULV_W (2420) - MIPS_INS_MULV_W - mulv.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MUL_MM (2421) - MIPS_INS_MUL - mul $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUL_MMR6 (2422) - MIPS_INS_MUL - mul $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUL_NM (2423) - MIPS_INS_MUL - mul $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUL_PH (2424) - MIPS_INS_MUL_PH - mul.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUL_PH_MMR2 (2425) - MIPS_INS_MUL_PH - mul.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUL_Q_H (2426) - MIPS_INS_MUL_Q_H - mul_q.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MUL_Q_W (2427) - MIPS_INS_MUL_Q_W - mul_q.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_MUL_R6 (2428) - MIPS_INS_MUL - mul $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUL_S_PH (2429) - MIPS_INS_MUL_S_PH - mul_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_MUL_S_PH_MMR2 (2430) - MIPS_INS_MUL_S_PH - mul_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_Mfhi16 (2431) - MIPS_INS_MFHI - mfhi $rx */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { 0 } +}}, +{ /* MIPS_Mflo16 (2432) - MIPS_INS_MFLO - mflo $rx */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { 0 } +}}, +{ /* MIPS_Move32R16 (2433) - MIPS_INS_MOVE - move $r32, $rz */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r32 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rz */ + { 0 } +}}, +{ /* MIPS_MoveR3216 (2434) - MIPS_INS_MOVE - move $ry, $r32 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* r32 */ + { 0 } +}}, +{ /* MIPS_NLOC_B (2435) - MIPS_INS_NLOC_B - nloc.b $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_NLOC_D (2436) - MIPS_INS_NLOC_D - nloc.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_NLOC_H (2437) - MIPS_INS_NLOC_H - nloc.h $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_NLOC_W (2438) - MIPS_INS_NLOC_W - nloc.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_NLZC_B (2439) - MIPS_INS_NLZC_B - nlzc.b $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_NLZC_D (2440) - MIPS_INS_NLZC_D - nlzc.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_NLZC_H (2441) - MIPS_INS_NLZC_H - nlzc.h $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_NLZC_W (2442) - MIPS_INS_NLZC_W - nlzc.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_NMADD_D32 (2443) - MIPS_INS_NMADD_D - nmadd.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NMADD_D32_MM (2444) - MIPS_INS_NMADD_D - nmadd.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NMADD_D64 (2445) - MIPS_INS_NMADD_D - nmadd.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NMADD_S (2446) - MIPS_INS_NMADD_S - nmadd.s $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NMADD_S_MM (2447) - MIPS_INS_NMADD_S - nmadd.s $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NMSUB_D32 (2448) - MIPS_INS_NMSUB_D - nmsub.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NMSUB_D32_MM (2449) - MIPS_INS_NMSUB_D - nmsub.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NMSUB_D64 (2450) - MIPS_INS_NMSUB_D - nmsub.d $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NMSUB_S (2451) - MIPS_INS_NMSUB_S - nmsub.s $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NMSUB_S_MM (2452) - MIPS_INS_NMSUB_S - nmsub.s $fd, $fr, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fr */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_NOP32_NM (2453) - MIPS_INS_NOP32 - nop32 */ +{ + { 0 } +}}, +{ /* MIPS_NOP_NM (2454) - MIPS_INS_NOP - nop */ +{ + { 0 } +}}, +{ /* MIPS_NOR (2455) - MIPS_INS_NOR - nor $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_NOR64 (2456) - MIPS_INS_INVALID - nor $rd, $rs, $rt */ + 0 +}}}, +{ /* MIPS_NORI_B (2457) - MIPS_INS_NORI_B - nori.b $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_NOR_MM (2458) - MIPS_INS_NOR - nor $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_NOR_MMR6 (2459) - MIPS_INS_NOR - nor $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_NOR_NM (2460) - MIPS_INS_NOR - nor $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_NOR_V (2461) - MIPS_INS_NOR_V - nor.v $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_NOT16_MM (2462) - MIPS_INS_NOT16 - not16 $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_NOT16_MMR6 (2463) - MIPS_INS_NOT16 - not16 $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_NOT16_NM (2464) - MIPS_INS_NOT - not $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_NegRxRy16 (2465) - MIPS_INS_NEG - neg $rx, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_NotRxRy16 (2466) - MIPS_INS_NOT - not $rx, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_OR (2467) - MIPS_INS_OR - or $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_OR16_MM (2468) - MIPS_INS_OR16 - or16 $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_OR16_MMR6 (2469) - MIPS_INS_OR16 - or16 $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_OR16_NM (2470) - MIPS_INS_OR - or $dst, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_OR64 (2471) - MIPS_INS_INVALID - or $rd, $rs, $rt */ + 0 +}}}, +{ /* MIPS_ORI_B (2472) - MIPS_INS_ORI_B - ori.b $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_ORI_MMR6 (2473) - MIPS_INS_ORI - ori $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_ORI_NM (2474) - MIPS_INS_ORI - ori $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_OR_MM (2475) - MIPS_INS_OR - or $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_OR_MMR6 (2476) - MIPS_INS_OR - or $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_OR_NM (2477) - MIPS_INS_OR - or $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_OR_V (2478) - MIPS_INS_OR_V - or.v $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_ORi (2479) - MIPS_INS_ORI - ori $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{{{ /* MIPS_ORi64 (2480) - MIPS_INS_INVALID - ori $rt, $rs, $imm16 */ + 0 +}}}, +{ /* MIPS_ORi_MM (2481) - MIPS_INS_ORI - ori $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_OrRxRxRy16 (2482) - MIPS_INS_OR - or $rz, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_PACKRL_PH (2483) - MIPS_INS_PACKRL_PH - packrl.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PACKRL_PH_MM (2484) - MIPS_INS_PACKRL_PH - packrl.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PAUSE (2485) - MIPS_INS_PAUSE - pause */ +{ + { 0 } +}}, +{ /* MIPS_PAUSE_MM (2486) - MIPS_INS_PAUSE - pause */ +{ + { 0 } +}}, +{ /* MIPS_PAUSE_MMR6 (2487) - MIPS_INS_PAUSE - pause */ +{ + { 0 } +}}, +{ /* MIPS_PAUSE_NM (2488) - MIPS_INS_PAUSE - pause */ +{ + { 0 } +}}, +{ /* MIPS_PCKEV_B (2489) - MIPS_INS_PCKEV_B - pckev.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_PCKEV_D (2490) - MIPS_INS_PCKEV_D - pckev.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_PCKEV_H (2491) - MIPS_INS_PCKEV_H - pckev.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_PCKEV_W (2492) - MIPS_INS_PCKEV_W - pckev.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_PCKOD_B (2493) - MIPS_INS_PCKOD_B - pckod.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_PCKOD_D (2494) - MIPS_INS_PCKOD_D - pckod.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_PCKOD_H (2495) - MIPS_INS_PCKOD_H - pckod.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_PCKOD_W (2496) - MIPS_INS_PCKOD_W - pckod.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_PCNT_B (2497) - MIPS_INS_PCNT_B - pcnt.b $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_PCNT_D (2498) - MIPS_INS_PCNT_D - pcnt.d $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_PCNT_H (2499) - MIPS_INS_PCNT_H - pcnt.h $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_PCNT_W (2500) - MIPS_INS_PCNT_W - pcnt.w $wd, $ws */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { 0 } +}}, +{ /* MIPS_PICK_PH (2501) - MIPS_INS_PICK_PH - pick.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PICK_PH_MM (2502) - MIPS_INS_PICK_PH - pick.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PICK_QB (2503) - MIPS_INS_PICK_QB - pick.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PICK_QB_MM (2504) - MIPS_INS_PICK_QB - pick.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PLL_PS64 (2505) - MIPS_INS_PLL_PS - pll.ps $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_PLU_PS64 (2506) - MIPS_INS_PLU_PS - plu.ps $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_POP (2507) - MIPS_INS_POP - pop $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEQU_PH_QBL (2508) - MIPS_INS_PRECEQU_PH_QBL - precequ.ph.qbl $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEQU_PH_QBLA (2509) - MIPS_INS_PRECEQU_PH_QBLA - precequ.ph.qbla $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEQU_PH_QBLA_MM (2510) - MIPS_INS_PRECEQU_PH_QBLA - precequ.ph.qbla $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEQU_PH_QBL_MM (2511) - MIPS_INS_PRECEQU_PH_QBL - precequ.ph.qbl $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEQU_PH_QBR (2512) - MIPS_INS_PRECEQU_PH_QBR - precequ.ph.qbr $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEQU_PH_QBRA (2513) - MIPS_INS_PRECEQU_PH_QBRA - precequ.ph.qbra $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEQU_PH_QBRA_MM (2514) - MIPS_INS_PRECEQU_PH_QBRA - precequ.ph.qbra $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEQU_PH_QBR_MM (2515) - MIPS_INS_PRECEQU_PH_QBR - precequ.ph.qbr $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEQ_W_PHL (2516) - MIPS_INS_PRECEQ_W_PHL - preceq.w.phl $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEQ_W_PHL_MM (2517) - MIPS_INS_PRECEQ_W_PHL - preceq.w.phl $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEQ_W_PHR (2518) - MIPS_INS_PRECEQ_W_PHR - preceq.w.phr $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEQ_W_PHR_MM (2519) - MIPS_INS_PRECEQ_W_PHR - preceq.w.phr $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEU_PH_QBL (2520) - MIPS_INS_PRECEU_PH_QBL - preceu.ph.qbl $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEU_PH_QBLA (2521) - MIPS_INS_PRECEU_PH_QBLA - preceu.ph.qbla $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEU_PH_QBLA_MM (2522) - MIPS_INS_PRECEU_PH_QBLA - preceu.ph.qbla $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEU_PH_QBL_MM (2523) - MIPS_INS_PRECEU_PH_QBL - preceu.ph.qbl $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEU_PH_QBR (2524) - MIPS_INS_PRECEU_PH_QBR - preceu.ph.qbr $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEU_PH_QBRA (2525) - MIPS_INS_PRECEU_PH_QBRA - preceu.ph.qbra $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECEU_PH_QBRA_MM (2526) - MIPS_INS_PRECEU_PH_QBRA - preceu.ph.qbra $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECEU_PH_QBR_MM (2527) - MIPS_INS_PRECEU_PH_QBR - preceu.ph.qbr $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_PRECRQU_S_QB_PH (2528) - MIPS_INS_PRECRQU_S_QB_PH - precrqu_s.qb.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECRQU_S_QB_PH_MM (2529) - MIPS_INS_PRECRQU_S_QB_PH - precrqu_s.qb.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECRQ_PH_W (2530) - MIPS_INS_PRECRQ_PH_W - precrq.ph.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECRQ_PH_W_MM (2531) - MIPS_INS_PRECRQ_PH_W - precrq.ph.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECRQ_QB_PH (2532) - MIPS_INS_PRECRQ_QB_PH - precrq.qb.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECRQ_QB_PH_MM (2533) - MIPS_INS_PRECRQ_QB_PH - precrq.qb.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECRQ_RS_PH_W (2534) - MIPS_INS_PRECRQ_RS_PH_W - precrq_rs.ph.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECRQ_RS_PH_W_MM (2535) - MIPS_INS_PRECRQ_RS_PH_W - precrq_rs.ph.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECR_QB_PH (2536) - MIPS_INS_PRECR_QB_PH - precr.qb.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECR_QB_PH_MMR2 (2537) - MIPS_INS_PRECR_QB_PH - precr.qb.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_PRECR_SRA_PH_W (2538) - MIPS_INS_PRECR_SRA_PH_W - precr_sra.ph.w $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_PRECR_SRA_PH_W_MMR2 (2539) - MIPS_INS_PRECR_SRA_PH_W - precr_sra.ph.w $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_PRECR_SRA_R_PH_W (2540) - MIPS_INS_PRECR_SRA_R_PH_W - precr_sra_r.ph.w $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_PRECR_SRA_R_PH_W_MMR2 (2541) - MIPS_INS_PRECR_SRA_R_PH_W - precr_sra_r.ph.w $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_PREF (2542) - MIPS_INS_PREF - pref $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_PREFE (2543) - MIPS_INS_PREFE - prefe $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_PREFE_MM (2544) - MIPS_INS_PREFE - prefe $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_PREFX_MM (2545) - MIPS_INS_PREFX - prefx $hint, ${index}(${base}) */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_PREF_MM (2546) - MIPS_INS_PREF - pref $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_PREF_MMR6 (2547) - MIPS_INS_PREF - pref $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_PREF_NM (2548) - MIPS_INS_PREF - pref $op, $addr */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* op */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_PREF_R6 (2549) - MIPS_INS_PREF - pref $hint, $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hint */ + { 0 } +}}, +{ /* MIPS_PREFs9_NM (2550) - MIPS_INS_PREF - pref $op, $addr */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* op */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_PREPEND (2551) - MIPS_INS_PREPEND - prepend $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_PREPEND_MMR2 (2552) - MIPS_INS_PREPEND - prepend $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_PUL_PS64 (2553) - MIPS_INS_PUL_PS - pul.ps $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_PUU_PS64 (2554) - MIPS_INS_PUU_PS - puu.ps $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_RADDU_W_QB (2555) - MIPS_INS_RADDU_W_QB - raddu.w.qb $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_RADDU_W_QB_MM (2556) - MIPS_INS_RADDU_W_QB - raddu.w.qb $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_RDDSP (2557) - MIPS_INS_RDDSP - rddsp $rd, $mask */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */ + { 0 } +}}, +{ /* MIPS_RDDSP_MM (2558) - MIPS_INS_RDDSP - rddsp $rt, $mask */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */ + { 0 } +}}, +{ /* MIPS_RDHWR (2559) - MIPS_INS_RDHWR - rdhwr $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{{{ /* MIPS_RDHWR64 (2560) - MIPS_INS_INVALID - rdhwr $rt, $rd, $sel */ + 0 +}}}, +{ /* MIPS_RDHWR_MM (2561) - MIPS_INS_RDHWR - rdhwr $rt, $rd, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_RDHWR_MMR6 (2562) - MIPS_INS_RDHWR - rdhwr $rt, $rs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_RDHWR_NM (2563) - MIPS_INS_RDHWR - rdhwr $rt, $hs, $sel */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* hs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sel */ + { 0 } +}}, +{ /* MIPS_RDPGPR_MMR6 (2564) - MIPS_INS_RDPGPR - rdpgpr $rt, $rd */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { 0 } +}}, +{ /* MIPS_RDPGPR_NM (2565) - MIPS_INS_RDPGPR - rdpgpr $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_RECIP_D32 (2566) - MIPS_INS_RECIP_D - recip.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RECIP_D32_MM (2567) - MIPS_INS_RECIP_D - recip.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RECIP_D64 (2568) - MIPS_INS_RECIP_D - recip.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RECIP_D64_MM (2569) - MIPS_INS_RECIP_D - recip.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RECIP_S (2570) - MIPS_INS_RECIP_S - recip.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RECIP_S_MM (2571) - MIPS_INS_RECIP_S - recip.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_REPLV_PH (2572) - MIPS_INS_REPLV_PH - replv.ph $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_REPLV_PH_MM (2573) - MIPS_INS_REPLV_PH - replv.ph $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_REPLV_QB (2574) - MIPS_INS_REPLV_QB - replv.qb $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_REPLV_QB_MM (2575) - MIPS_INS_REPLV_QB - replv.qb $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_REPL_PH (2576) - MIPS_INS_REPL_PH - repl.ph $rd, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_REPL_PH_MM (2577) - MIPS_INS_REPL_PH - repl.ph $rd, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_REPL_QB (2578) - MIPS_INS_REPL_QB - repl.qb $rd, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_REPL_QB_MM (2579) - MIPS_INS_REPL_QB - repl.qb $rt, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_RESTOREJRC16_NM (2580) - MIPS_INS_RESTORE_JRC - restore.jrc $adj$regs */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* adj */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } +}}, +{ /* MIPS_RESTOREJRC_NM (2581) - MIPS_INS_RESTORE_JRC - restore.jrc $adj$regs */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* adj */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } +}}, +{ /* MIPS_RESTORE_NM (2582) - MIPS_INS_RESTORE - restore $adj$regs */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* adj */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } +}}, +{ /* MIPS_RINT_D (2583) - MIPS_INS_RINT_D - rint.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RINT_D_MMR6 (2584) - MIPS_INS_RINT_D - rint.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RINT_S (2585) - MIPS_INS_RINT_S - rint.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RINT_S_MMR6 (2586) - MIPS_INS_RINT_S - rint.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROTR (2587) - MIPS_INS_ROTR - rotr $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_ROTRV (2588) - MIPS_INS_ROTRV - rotrv $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_ROTRV_MM (2589) - MIPS_INS_ROTRV - rotrv $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_ROTRV_NM (2590) - MIPS_INS_ROTRV - rotrv $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_ROTR_MM (2591) - MIPS_INS_ROTR - rotr $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_ROTR_NM (2592) - MIPS_INS_ROTR - rotr $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_ROTX_NM (2593) - MIPS_INS_ROTX - rotx $rt, $rs, $shift, $shiftx, $stripe */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shiftx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* stripe */ + { 0 } +}}, +{ /* MIPS_ROUND_L_D64 (2594) - MIPS_INS_ROUND_L_D - round.l.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_L_D_MMR6 (2595) - MIPS_INS_ROUND_L_D - round.l.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_L_S (2596) - MIPS_INS_ROUND_L_S - round.l.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_L_S_MMR6 (2597) - MIPS_INS_ROUND_L_S - round.l.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_W_D32 (2598) - MIPS_INS_ROUND_W_D - round.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_W_D64 (2599) - MIPS_INS_ROUND_W_D - round.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_W_D_MMR6 (2600) - MIPS_INS_ROUND_W_D - round.w.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_W_MM (2601) - MIPS_INS_ROUND_W_D - round.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_W_S (2602) - MIPS_INS_ROUND_W_S - round.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_W_S_MM (2603) - MIPS_INS_ROUND_W_S - round.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_ROUND_W_S_MMR6 (2604) - MIPS_INS_ROUND_W_S - round.w.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RSQRT_D32 (2605) - MIPS_INS_RSQRT_D - rsqrt.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RSQRT_D32_MM (2606) - MIPS_INS_RSQRT_D - rsqrt.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RSQRT_D64 (2607) - MIPS_INS_RSQRT_D - rsqrt.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RSQRT_D64_MM (2608) - MIPS_INS_RSQRT_D - rsqrt.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RSQRT_S (2609) - MIPS_INS_RSQRT_S - rsqrt.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_RSQRT_S_MM (2610) - MIPS_INS_RSQRT_S - rsqrt.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{{{ /* MIPS_Restore16 (2611) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_RestoreX16 (2612) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_SAA (2613) - MIPS_INS_SAA - saa $rt, (${rs}) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SAAD (2614) - MIPS_INS_SAAD - saad $rt, (${rs}) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SAT_S_B (2615) - MIPS_INS_SAT_S_B - sat_s.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SAT_S_D (2616) - MIPS_INS_SAT_S_D - sat_s.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SAT_S_H (2617) - MIPS_INS_SAT_S_H - sat_s.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SAT_S_W (2618) - MIPS_INS_SAT_S_W - sat_s.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SAT_U_B (2619) - MIPS_INS_SAT_U_B - sat_u.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SAT_U_D (2620) - MIPS_INS_SAT_U_D - sat_u.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SAT_U_H (2621) - MIPS_INS_SAT_U_H - sat_u.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SAT_U_W (2622) - MIPS_INS_SAT_U_W - sat_u.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SAVE16_NM (2623) - MIPS_INS_SAVE - save $adj$regs */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* adj */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } +}}, +{ /* MIPS_SAVE_NM (2624) - MIPS_INS_SAVE - save $adj$regs */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* adj */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* regs */ + { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ + { 0 } +}}, +{ /* MIPS_SB (2625) - MIPS_INS_SB - sb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SB16_MM (2626) - MIPS_INS_SB16 - sb16 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_gpr16mm_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm4 */ + { 0 } +}}, +{ /* MIPS_SB16_MMR6 (2627) - MIPS_INS_SB16 - sb16 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_gpr16mm_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm4 */ + { 0 } +}}, +{ /* MIPS_SB16_NM (2628) - MIPS_INS_SB - sb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_SB64 (2629) - MIPS_INS_INVALID - sb $rt, $addr */ + 0 +}}}, +{ /* MIPS_SBE (2630) - MIPS_INS_SBE - sbe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SBE_MM (2631) - MIPS_INS_SBE - sbe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SBGP_NM (2632) - MIPS_INS_SB - sb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SBX_NM (2633) - MIPS_INS_SBX - sbx $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SB_MM (2634) - MIPS_INS_SB - sb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SB_MMR6 (2635) - MIPS_INS_SB - sb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SB_NM (2636) - MIPS_INS_SB - sb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SBs9_NM (2637) - MIPS_INS_SB - sb $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SC (2638) - MIPS_INS_SC - sc $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SC64 (2639) - MIPS_INS_SC - sc $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SC64_R6 (2640) - MIPS_INS_SC - sc $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SCD (2641) - MIPS_INS_SCD - scd $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SCD_R6 (2642) - MIPS_INS_SCD - scd $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SCE (2643) - MIPS_INS_SCE - sce $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SCE_MM (2644) - MIPS_INS_SCE - sce $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SCWP_NM (2645) - MIPS_INS_SCWP - scwp $rt, $ru, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ru */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SC_MM (2646) - MIPS_INS_SC - sc $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_SC_MMR6 (2647) - MIPS_INS_SC - sc $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SC_NM (2648) - MIPS_INS_SC - sc $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SC_R6 (2649) - MIPS_INS_SC - sc $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SD (2650) - MIPS_INS_SD - sd $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDBBP (2651) - MIPS_INS_SDBBP - sdbbp $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SDBBP16_MM (2652) - MIPS_INS_SDBBP16 - sdbbp16 $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SDBBP16_MMR6 (2653) - MIPS_INS_SDBBP16 - sdbbp16 $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SDBBP16_NM (2654) - MIPS_INS_SDBBP - sdbbp $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SDBBP_MM (2655) - MIPS_INS_SDBBP - sdbbp $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SDBBP_MMR6 (2656) - MIPS_INS_SDBBP - sdbbp $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SDBBP_NM (2657) - MIPS_INS_SDBBP - sdbbp $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SDBBP_R6 (2658) - MIPS_INS_SDBBP - sdbbp $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SDC1 (2659) - MIPS_INS_SDC1 - sdc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDC164 (2660) - MIPS_INS_SDC1 - sdc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDC1_D64_MMR6 (2661) - MIPS_INS_SDC1 - sdc1 $ft, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDC1_MM_D32 (2662) - MIPS_INS_SDC1 - sdc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDC1_MM_D64 (2663) - MIPS_INS_SDC1 - sdc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDC2 (2664) - MIPS_INS_SDC2 - sdc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDC2_MMR6 (2665) - MIPS_INS_SDC2 - sdc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm11 */ + { 0 } +}}, +{ /* MIPS_SDC2_R6 (2666) - MIPS_INS_SDC2 - sdc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm11 */ + { 0 } +}}, +{ /* MIPS_SDC3 (2667) - MIPS_INS_SDC3 - sdc3 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDIV (2668) - MIPS_INS_DIV - div $$zero, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SDIV_MM (2669) - MIPS_INS_DIV - div $$zero, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SDL (2670) - MIPS_INS_SDL - sdl $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDR (2671) - MIPS_INS_SDR - sdr $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SDXC1 (2672) - MIPS_INS_SDXC1 - sdxc1 $fs, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_SDXC164 (2673) - MIPS_INS_SDXC1 - sdxc1 $fs, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_SEB (2674) - MIPS_INS_SEB - seb $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_SEB64 (2675) - MIPS_INS_INVALID - seb $rd, $rt */ + 0 +}}}, +{ /* MIPS_SEB_MM (2676) - MIPS_INS_SEB - seb $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SEB_NM (2677) - MIPS_INS_SEB - seb $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SEH (2678) - MIPS_INS_SEH - seh $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_SEH64 (2679) - MIPS_INS_INVALID - seh $rd, $rt */ + 0 +}}}, +{ /* MIPS_SEH_MM (2680) - MIPS_INS_SEH - seh $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SEH_NM (2681) - MIPS_INS_SEH - seh $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SELEQZ (2682) - MIPS_INS_SELEQZ - seleqz $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SELEQZ64 (2683) - MIPS_INS_SELEQZ - seleqz $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SELEQZ_D (2684) - MIPS_INS_SELEQZ_D - seleqz.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SELEQZ_D_MMR6 (2685) - MIPS_INS_SELEQZ_D - seleqz.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SELEQZ_MMR6 (2686) - MIPS_INS_SELEQZ - seleqz $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SELEQZ_S (2687) - MIPS_INS_SELEQZ_S - seleqz.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SELEQZ_S_MMR6 (2688) - MIPS_INS_SELEQZ_S - seleqz.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SELNEZ (2689) - MIPS_INS_SELNEZ - selnez $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SELNEZ64 (2690) - MIPS_INS_SELNEZ - selnez $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SELNEZ_D (2691) - MIPS_INS_SELNEZ_D - selnez.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SELNEZ_D_MMR6 (2692) - MIPS_INS_SELNEZ_D - selnez.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SELNEZ_MMR6 (2693) - MIPS_INS_SELNEZ - selnez $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SELNEZ_S (2694) - MIPS_INS_SELNEZ_S - selnez.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SELNEZ_S_MMR6 (2695) - MIPS_INS_SELNEZ_S - selnez.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SEL_D (2696) - MIPS_INS_SEL_D - sel.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SEL_D_MMR6 (2697) - MIPS_INS_SEL_D - sel.d $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SEL_S (2698) - MIPS_INS_SEL_S - sel.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SEL_S_MMR6 (2699) - MIPS_INS_SEL_S - sel.s $fd, $fs, $ft */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { 0 } +}}, +{ /* MIPS_SEQ (2700) - MIPS_INS_SEQ - seq $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SEQI_NM (2701) - MIPS_INS_SEQI - seqi $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SEQi (2702) - MIPS_INS_SEQI - seqi $rt, $rs, $imm10 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm10 */ + { 0 } +}}, +{ /* MIPS_SH (2703) - MIPS_INS_SH - sh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SH16_MM (2704) - MIPS_INS_SH16 - sh16 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_gpr16mm_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm4 */ + { 0 } +}}, +{ /* MIPS_SH16_MMR6 (2705) - MIPS_INS_SH16 - sh16 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_gpr16mm_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm4 */ + { 0 } +}}, +{ /* MIPS_SH16_NM (2706) - MIPS_INS_SH - sh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_SH64 (2707) - MIPS_INS_INVALID - sh $rt, $addr */ + 0 +}}}, +{ /* MIPS_SHE (2708) - MIPS_INS_SHE - she $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SHE_MM (2709) - MIPS_INS_SHE - she $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SHF_B (2710) - MIPS_INS_SHF_B - shf.b $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_SHF_H (2711) - MIPS_INS_SHF_H - shf.h $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_SHF_W (2712) - MIPS_INS_SHF_W - shf.w $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_SHGP_NM (2713) - MIPS_INS_SH - sh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SHILO (2714) - MIPS_INS_SHILO - shilo $ac, $shift */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_SHILOV (2715) - MIPS_INS_SHILOV - shilov $ac, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_SHILOV_MM (2716) - MIPS_INS_SHILOV - shilov $ac, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_SHILO_MM (2717) - MIPS_INS_SHILO - shilo $ac, $shift */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* ac */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* acin */ + { 0 } +}}, +{ /* MIPS_SHLLV_PH (2718) - MIPS_INS_SHLLV_PH - shllv.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHLLV_PH_MM (2719) - MIPS_INS_SHLLV_PH - shllv.ph $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHLLV_QB (2720) - MIPS_INS_SHLLV_QB - shllv.qb $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHLLV_QB_MM (2721) - MIPS_INS_SHLLV_QB - shllv.qb $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHLLV_S_PH (2722) - MIPS_INS_SHLLV_S_PH - shllv_s.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHLLV_S_PH_MM (2723) - MIPS_INS_SHLLV_S_PH - shllv_s.ph $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHLLV_S_W (2724) - MIPS_INS_SHLLV_S_W - shllv_s.w $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHLLV_S_W_MM (2725) - MIPS_INS_SHLLV_S_W - shllv_s.w $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHLL_PH (2726) - MIPS_INS_SHLL_PH - shll.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHLL_PH_MM (2727) - MIPS_INS_SHLL_PH - shll.ph $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHLL_QB (2728) - MIPS_INS_SHLL_QB - shll.qb $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHLL_QB_MM (2729) - MIPS_INS_SHLL_QB - shll.qb $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHLL_S_PH (2730) - MIPS_INS_SHLL_S_PH - shll_s.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHLL_S_PH_MM (2731) - MIPS_INS_SHLL_S_PH - shll_s.ph $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHLL_S_W (2732) - MIPS_INS_SHLL_S_W - shll_s.w $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHLL_S_W_MM (2733) - MIPS_INS_SHLL_S_W - shll_s.w $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHRAV_PH (2734) - MIPS_INS_SHRAV_PH - shrav.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRAV_PH_MM (2735) - MIPS_INS_SHRAV_PH - shrav.ph $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHRAV_QB (2736) - MIPS_INS_SHRAV_QB - shrav.qb $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRAV_QB_MMR2 (2737) - MIPS_INS_SHRAV_QB - shrav.qb $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHRAV_R_PH (2738) - MIPS_INS_SHRAV_R_PH - shrav_r.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRAV_R_PH_MM (2739) - MIPS_INS_SHRAV_R_PH - shrav_r.ph $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHRAV_R_QB (2740) - MIPS_INS_SHRAV_R_QB - shrav_r.qb $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRAV_R_QB_MMR2 (2741) - MIPS_INS_SHRAV_R_QB - shrav_r.qb $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHRAV_R_W (2742) - MIPS_INS_SHRAV_R_W - shrav_r.w $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRAV_R_W_MM (2743) - MIPS_INS_SHRAV_R_W - shrav_r.w $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHRA_PH (2744) - MIPS_INS_SHRA_PH - shra.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRA_PH_MM (2745) - MIPS_INS_SHRA_PH - shra.ph $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHRA_QB (2746) - MIPS_INS_SHRA_QB - shra.qb $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRA_QB_MMR2 (2747) - MIPS_INS_SHRA_QB - shra.qb $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHRA_R_PH (2748) - MIPS_INS_SHRA_R_PH - shra_r.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRA_R_PH_MM (2749) - MIPS_INS_SHRA_R_PH - shra_r.ph $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHRA_R_QB (2750) - MIPS_INS_SHRA_R_QB - shra_r.qb $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRA_R_QB_MMR2 (2751) - MIPS_INS_SHRA_R_QB - shra_r.qb $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHRA_R_W (2752) - MIPS_INS_SHRA_R_W - shra_r.w $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRA_R_W_MM (2753) - MIPS_INS_SHRA_R_W - shra_r.w $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHRLV_PH (2754) - MIPS_INS_SHRLV_PH - shrlv.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRLV_PH_MMR2 (2755) - MIPS_INS_SHRLV_PH - shrlv.ph $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHRLV_QB (2756) - MIPS_INS_SHRLV_QB - shrlv.qb $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRLV_QB_MM (2757) - MIPS_INS_SHRLV_QB - shrlv.qb $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SHRL_PH (2758) - MIPS_INS_SHRL_PH - shrl.ph $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRL_PH_MMR2 (2759) - MIPS_INS_SHRL_PH - shrl.ph $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHRL_QB (2760) - MIPS_INS_SHRL_QB - shrl.qb $rd, $rt, $rs_sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs_sa */ + { 0 } +}}, +{ /* MIPS_SHRL_QB_MM (2761) - MIPS_INS_SHRL_QB - shrl.qb $rt, $rs, $sa */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa */ + { 0 } +}}, +{ /* MIPS_SHXS_NM (2762) - MIPS_INS_SHXS - shxs $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SHX_NM (2763) - MIPS_INS_SHX - shx $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SH_MM (2764) - MIPS_INS_SH - sh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SH_MMR6 (2765) - MIPS_INS_SH - sh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SH_NM (2766) - MIPS_INS_SH - sh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SHs9_NM (2767) - MIPS_INS_SH - sh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SIGRIE (2768) - MIPS_INS_SIGRIE - sigrie $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SIGRIE_MMR6 (2769) - MIPS_INS_SIGRIE - sigrie $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SIGRIE_NM (2770) - MIPS_INS_SIGRIE - sigrie $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLDI_B (2771) - MIPS_INS_SLDI_B - sldi.b $wd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_SLDI_D (2772) - MIPS_INS_SLDI_D - sldi.d $wd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_SLDI_H (2773) - MIPS_INS_SLDI_H - sldi.h $wd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_SLDI_W (2774) - MIPS_INS_SLDI_W - sldi.w $wd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_SLD_B (2775) - MIPS_INS_SLD_B - sld.b $wd, $ws[$rt] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLD_D (2776) - MIPS_INS_SLD_D - sld.d $wd, $ws[$rt] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLD_H (2777) - MIPS_INS_SLD_H - sld.h $wd, $ws[$rt] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLD_W (2778) - MIPS_INS_SLD_W - sld.w $wd, $ws[$rt] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLL (2779) - MIPS_INS_SLL - sll $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SLL16_MM (2780) - MIPS_INS_SLL16 - sll16 $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SLL16_MMR6 (2781) - MIPS_INS_SLL16 - sll16 $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SLL16_NM (2782) - MIPS_INS_SLL - sll $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{{{ /* MIPS_SLL64_32 (2783) - MIPS_INS_INVALID - sll $rd, $rt, 0 */ + 0 +}}}, +{{{ /* MIPS_SLL64_64 (2784) - MIPS_INS_INVALID - sll $rd, $rt, 0 */ + 0 +}}}, +{ /* MIPS_SLLI_B (2785) - MIPS_INS_SLLI_B - slli.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SLLI_D (2786) - MIPS_INS_SLLI_D - slli.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SLLI_H (2787) - MIPS_INS_SLLI_H - slli.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SLLI_W (2788) - MIPS_INS_SLLI_W - slli.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SLLV (2789) - MIPS_INS_SLLV - sllv $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SLLV_MM (2790) - MIPS_INS_SLLV - sllv $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SLLV_NM (2791) - MIPS_INS_SLLV - sllv $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLL_B (2792) - MIPS_INS_SLL_B - sll.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SLL_D (2793) - MIPS_INS_SLL_D - sll.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SLL_H (2794) - MIPS_INS_SLL_H - sll.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SLL_MM (2795) - MIPS_INS_SLL - sll $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SLL_MMR6 (2796) - MIPS_INS_SLL - sll $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SLL_NM (2797) - MIPS_INS_SLL - sll $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLL_W (2798) - MIPS_INS_SLL_W - sll.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SLT (2799) - MIPS_INS_SLT - slt $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_SLT64 (2800) - MIPS_INS_INVALID - slt $rd, $rs, $rt */ + 0 +}}}, +{ /* MIPS_SLTIU_NM (2801) - MIPS_INS_SLTIU - sltiu $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLTI_NM (2802) - MIPS_INS_SLTI - slti $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SLTU_NM (2803) - MIPS_INS_SLTU - sltu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLT_MM (2804) - MIPS_INS_SLT - slt $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLT_NM (2805) - MIPS_INS_SLT - slt $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SLTi (2806) - MIPS_INS_SLTI - slti $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{{{ /* MIPS_SLTi64 (2807) - MIPS_INS_INVALID - slti $rt, $rs, $imm16 */ + 0 +}}}, +{ /* MIPS_SLTi_MM (2808) - MIPS_INS_SLTI - slti $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_SLTiu (2809) - MIPS_INS_SLTIU - sltiu $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{{{ /* MIPS_SLTiu64 (2810) - MIPS_INS_INVALID - sltiu $rt, $rs, $imm16 */ + 0 +}}}, +{ /* MIPS_SLTiu_MM (2811) - MIPS_INS_SLTIU - sltiu $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_SLTu (2812) - MIPS_INS_SLTU - sltu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_SLTu64 (2813) - MIPS_INS_INVALID - sltu $rd, $rs, $rt */ + 0 +}}}, +{ /* MIPS_SLTu_MM (2814) - MIPS_INS_SLTU - sltu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SNE (2815) - MIPS_INS_SNE - sne $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SNEi (2816) - MIPS_INS_SNEI - snei $rt, $rs, $imm10 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* imm10 */ + { 0 } +}}, +{ /* MIPS_SOV_NM (2817) - MIPS_INS_SOV - sov $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SPLATI_B (2818) - MIPS_INS_SPLATI_B - splati.b $wd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_SPLATI_D (2819) - MIPS_INS_SPLATI_D - splati.d $wd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_SPLATI_H (2820) - MIPS_INS_SPLATI_H - splati.h $wd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_SPLATI_W (2821) - MIPS_INS_SPLATI_W - splati.w $wd, $ws[$n] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* n */ + { 0 } +}}, +{ /* MIPS_SPLAT_B (2822) - MIPS_INS_SPLAT_B - splat.b $wd, $ws[$rt] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SPLAT_D (2823) - MIPS_INS_SPLAT_D - splat.d $wd, $ws[$rt] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SPLAT_H (2824) - MIPS_INS_SPLAT_H - splat.h $wd, $ws[$rt] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SPLAT_W (2825) - MIPS_INS_SPLAT_W - splat.w $wd, $ws[$rt] */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SRA (2826) - MIPS_INS_SRA - sra $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SRAI_B (2827) - MIPS_INS_SRAI_B - srai.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRAI_D (2828) - MIPS_INS_SRAI_D - srai.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRAI_H (2829) - MIPS_INS_SRAI_H - srai.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRAI_W (2830) - MIPS_INS_SRAI_W - srai.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRARI_B (2831) - MIPS_INS_SRARI_B - srari.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRARI_D (2832) - MIPS_INS_SRARI_D - srari.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRARI_H (2833) - MIPS_INS_SRARI_H - srari.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRARI_W (2834) - MIPS_INS_SRARI_W - srari.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRAR_B (2835) - MIPS_INS_SRAR_B - srar.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRAR_D (2836) - MIPS_INS_SRAR_D - srar.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRAR_H (2837) - MIPS_INS_SRAR_H - srar.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRAR_W (2838) - MIPS_INS_SRAR_W - srar.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRAV (2839) - MIPS_INS_SRAV - srav $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SRAV_MM (2840) - MIPS_INS_SRAV - srav $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SRAV_NM (2841) - MIPS_INS_SRAV - srav $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SRA_B (2842) - MIPS_INS_SRA_B - sra.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRA_D (2843) - MIPS_INS_SRA_D - sra.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRA_H (2844) - MIPS_INS_SRA_H - sra.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRA_MM (2845) - MIPS_INS_SRA - sra $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SRA_NM (2846) - MIPS_INS_SRA - sra $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SRA_W (2847) - MIPS_INS_SRA_W - sra.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRL (2848) - MIPS_INS_SRL - srl $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SRL16_MM (2849) - MIPS_INS_SRL16 - srl16 $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SRL16_MMR6 (2850) - MIPS_INS_SRL16 - srl16 $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SRL16_NM (2851) - MIPS_INS_SRL - srl $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SRLI_B (2852) - MIPS_INS_SRLI_B - srli.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRLI_D (2853) - MIPS_INS_SRLI_D - srli.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRLI_H (2854) - MIPS_INS_SRLI_H - srli.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRLI_W (2855) - MIPS_INS_SRLI_W - srli.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRLRI_B (2856) - MIPS_INS_SRLRI_B - srlri.b $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRLRI_D (2857) - MIPS_INS_SRLRI_D - srlri.d $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRLRI_H (2858) - MIPS_INS_SRLRI_H - srlri.h $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRLRI_W (2859) - MIPS_INS_SRLRI_W - srlri.w $wd, $ws, $m */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* m */ + { 0 } +}}, +{ /* MIPS_SRLR_B (2860) - MIPS_INS_SRLR_B - srlr.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRLR_D (2861) - MIPS_INS_SRLR_D - srlr.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRLR_H (2862) - MIPS_INS_SRLR_H - srlr.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRLR_W (2863) - MIPS_INS_SRLR_W - srlr.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRLV (2864) - MIPS_INS_SRLV - srlv $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SRLV_MM (2865) - MIPS_INS_SRLV - srlv $rd, $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_SRLV_NM (2866) - MIPS_INS_SRLV - srlv $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SRL_B (2867) - MIPS_INS_SRL_B - srl.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRL_D (2868) - MIPS_INS_SRL_D - srl.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRL_H (2869) - MIPS_INS_SRL_H - srl.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SRL_MM (2870) - MIPS_INS_SRL - srl $rd, $rt, $shamt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shamt */ + { 0 } +}}, +{ /* MIPS_SRL_NM (2871) - MIPS_INS_SRL - srl $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SRL_W (2872) - MIPS_INS_SRL_W - srl.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SSNOP (2873) - MIPS_INS_SSNOP - ssnop */ +{ + { 0 } +}}, +{ /* MIPS_SSNOP_MM (2874) - MIPS_INS_SSNOP - ssnop */ +{ + { 0 } +}}, +{ /* MIPS_SSNOP_MMR6 (2875) - MIPS_INS_SSNOP - ssnop */ +{ + { 0 } +}}, +{ /* MIPS_ST_B (2876) - MIPS_INS_ST_B - st.b $wd, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm10 */ + { 0 } +}}, +{ /* MIPS_ST_D (2877) - MIPS_INS_ST_D - st.d $wd, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm10_lsl3 */ + { 0 } +}}, +{ /* MIPS_ST_H (2878) - MIPS_INS_ST_H - st.h $wd, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm10_lsl1 */ + { 0 } +}}, +{ /* MIPS_ST_W (2879) - MIPS_INS_ST_W - st.w $wd, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm10_lsl2 */ + { 0 } +}}, +{ /* MIPS_SUB (2880) - MIPS_INS_SUB - sub $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQH_PH (2881) - MIPS_INS_SUBQH_PH - subqh.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQH_PH_MMR2 (2882) - MIPS_INS_SUBQH_PH - subqh.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQH_R_PH (2883) - MIPS_INS_SUBQH_R_PH - subqh_r.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQH_R_PH_MMR2 (2884) - MIPS_INS_SUBQH_R_PH - subqh_r.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQH_R_W (2885) - MIPS_INS_SUBQH_R_W - subqh_r.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQH_R_W_MMR2 (2886) - MIPS_INS_SUBQH_R_W - subqh_r.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQH_W (2887) - MIPS_INS_SUBQH_W - subqh.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQH_W_MMR2 (2888) - MIPS_INS_SUBQH_W - subqh.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQ_PH (2889) - MIPS_INS_SUBQ_PH - subq.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQ_PH_MM (2890) - MIPS_INS_SUBQ_PH - subq.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQ_S_PH (2891) - MIPS_INS_SUBQ_S_PH - subq_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQ_S_PH_MM (2892) - MIPS_INS_SUBQ_S_PH - subq_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQ_S_W (2893) - MIPS_INS_SUBQ_S_W - subq_s.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBQ_S_W_MM (2894) - MIPS_INS_SUBQ_S_W - subq_s.w $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBSUS_U_B (2895) - MIPS_INS_SUBSUS_U_B - subsus_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBSUS_U_D (2896) - MIPS_INS_SUBSUS_U_D - subsus_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBSUS_U_H (2897) - MIPS_INS_SUBSUS_U_H - subsus_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBSUS_U_W (2898) - MIPS_INS_SUBSUS_U_W - subsus_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBSUU_S_B (2899) - MIPS_INS_SUBSUU_S_B - subsuu_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBSUU_S_D (2900) - MIPS_INS_SUBSUU_S_D - subsuu_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBSUU_S_H (2901) - MIPS_INS_SUBSUU_S_H - subsuu_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBSUU_S_W (2902) - MIPS_INS_SUBSUU_S_W - subsuu_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBS_S_B (2903) - MIPS_INS_SUBS_S_B - subs_s.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBS_S_D (2904) - MIPS_INS_SUBS_S_D - subs_s.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBS_S_H (2905) - MIPS_INS_SUBS_S_H - subs_s.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBS_S_W (2906) - MIPS_INS_SUBS_S_W - subs_s.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBS_U_B (2907) - MIPS_INS_SUBS_U_B - subs_u.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBS_U_D (2908) - MIPS_INS_SUBS_U_D - subs_u.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBS_U_H (2909) - MIPS_INS_SUBS_U_H - subs_u.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBS_U_W (2910) - MIPS_INS_SUBS_U_W - subs_u.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBU16_MM (2911) - MIPS_INS_SUBU16 - subu16 $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU16_MMR6 (2912) - MIPS_INS_SUBU16 - subu16 $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBUH_QB (2913) - MIPS_INS_SUBUH_QB - subuh.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBUH_QB_MMR2 (2914) - MIPS_INS_SUBUH_QB - subuh.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBUH_R_QB (2915) - MIPS_INS_SUBUH_R_QB - subuh_r.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBUH_R_QB_MMR2 (2916) - MIPS_INS_SUBUH_R_QB - subuh_r.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU_MMR6 (2917) - MIPS_INS_SUBU - subu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU_PH (2918) - MIPS_INS_SUBU_PH - subu.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU_PH_MMR2 (2919) - MIPS_INS_SUBU_PH - subu.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU_QB (2920) - MIPS_INS_SUBU_QB - subu.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU_QB_MM (2921) - MIPS_INS_SUBU_QB - subu.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU_S_PH (2922) - MIPS_INS_SUBU_S_PH - subu_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU_S_PH_MMR2 (2923) - MIPS_INS_SUBU_S_PH - subu_s.ph $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU_S_QB (2924) - MIPS_INS_SUBU_S_QB - subu_s.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBU_S_QB_MM (2925) - MIPS_INS_SUBU_S_QB - subu_s.qb $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBVI_B (2926) - MIPS_INS_SUBVI_B - subvi.b $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SUBVI_D (2927) - MIPS_INS_SUBVI_D - subvi.d $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SUBVI_H (2928) - MIPS_INS_SUBVI_H - subvi.h $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SUBVI_W (2929) - MIPS_INS_SUBVI_W - subvi.w $wd, $ws, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SUBV_B (2930) - MIPS_INS_SUBV_B - subv.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBV_D (2931) - MIPS_INS_SUBV_D - subv.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBV_H (2932) - MIPS_INS_SUBV_H - subv.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUBV_W (2933) - MIPS_INS_SUBV_W - subv.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_SUB_MM (2934) - MIPS_INS_SUB - sub $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUB_MMR6 (2935) - MIPS_INS_SUB - sub $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUB_NM (2936) - MIPS_INS_SUB - sub $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBu (2937) - MIPS_INS_SUBU - subu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBu16_NM (2938) - MIPS_INS_SUBU - subu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBu_MM (2939) - MIPS_INS_SUBU - subu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUBu_NM (2940) - MIPS_INS_SUBU - subu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_SUXC1 (2941) - MIPS_INS_SUXC1 - suxc1 $fs, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_SUXC164 (2942) - MIPS_INS_SUXC1 - suxc1 $fs, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_SUXC1_MM (2943) - MIPS_INS_SUXC1 - suxc1 $fs, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_SW (2944) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SW16_MM (2945) - MIPS_INS_SW16 - sw16 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_gpr16mm_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm4 */ + { 0 } +}}, +{ /* MIPS_SW16_MMR6 (2946) - MIPS_INS_SW16 - sw16 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_gpr16mm_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm4 */ + { 0 } +}}, +{ /* MIPS_SW16_NM (2947) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SW4x4_NM (2948) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_SW64 (2949) - MIPS_INS_INVALID - sw $rt, $addr */ + 0 +}}}, +{ /* MIPS_SWC1 (2950) - MIPS_INS_SWC1 - swc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWC1_MM (2951) - MIPS_INS_SWC1 - swc1 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWC2 (2952) - MIPS_INS_SWC2 - swc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWC2_MMR6 (2953) - MIPS_INS_SWC2 - swc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm11 */ + { 0 } +}}, +{ /* MIPS_SWC2_R6 (2954) - MIPS_INS_SWC2 - swc2 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm11 */ + { 0 } +}}, +{ /* MIPS_SWC3 (2955) - MIPS_INS_SWC3 - swc3 $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWDSP (2956) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWDSP_MM (2957) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWE (2958) - MIPS_INS_SWE - swe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SWE_MM (2959) - MIPS_INS_SWE - swe $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SWGP16_NM (2960) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWGP_NM (2961) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWL (2962) - MIPS_INS_SWL - swl $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_SWL64 (2963) - MIPS_INS_INVALID - swl $rt, $addr */ + 0 +}}}, +{ /* MIPS_SWLE (2964) - MIPS_INS_SWLE - swle $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SWLE_MM (2965) - MIPS_INS_SWLE - swle $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SWL_MM (2966) - MIPS_INS_SWL - swl $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_SWM16_MM (2967) - MIPS_INS_SWM16 - swm16 $rt, $addr */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_sp_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - uimm8 */ + { 0 } +}}, +{ /* MIPS_SWM16_MMR6 (2968) - MIPS_INS_SWM16 - swm16 $rt, $addr */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_sp_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - uimm8 */ + { 0 } +}}, +{ /* MIPS_SWM32_MM (2969) - MIPS_INS_SWM32 - swm32 $rt, $addr */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_SWM_NM (2970) - MIPS_INS_SWM - swm $rt, $addr, $rcount */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rcount */ + { 0 } +}}, +{ /* MIPS_SWPC_NM (2971) - MIPS_INS_SWPC - swpc $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_iPTRAny, CS_DATA_TYPE_LAST } }, /* addr */ + { 0 } +}}, +{ /* MIPS_SWP_MM (2972) - MIPS_INS_SWP - swp $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_SWR (2973) - MIPS_INS_SWR - swr $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{{{ /* MIPS_SWR64 (2974) - MIPS_INS_INVALID - swr $rt, $addr */ + 0 +}}}, +{ /* MIPS_SWRE (2975) - MIPS_INS_SWRE - swre $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SWRE_MM (2976) - MIPS_INS_SWRE - swre $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm9 */ + { 0 } +}}, +{ /* MIPS_SWR_MM (2977) - MIPS_INS_SWR - swr $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm12 */ + { 0 } +}}, +{ /* MIPS_SWSP16_NM (2978) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWSP_MM (2979) - MIPS_INS_SWSP - swsp $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* offset - ptr_sp_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - simm5 */ + { 0 } +}}, +{ /* MIPS_SWSP_MMR6 (2980) - MIPS_INS_SW - sw $rt, $offset */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* offset - ptr_sp_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - simm5 */ + { 0 } +}}, +{ /* MIPS_SWXC1 (2981) - MIPS_INS_SWXC1 - swxc1 $fs, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_SWXC1_MM (2982) - MIPS_INS_SWXC1 - swxc1 $fs, ${index}(${base}) */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* base - ptr_rc */ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* index - ptr_rc */ + { 0 } +}}, +{ /* MIPS_SWXS_NM (2983) - MIPS_INS_SWXS - swxs $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWX_NM (2984) - MIPS_INS_SWX - swx $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SW_MM (2985) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SW_MMR6 (2986) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SW_NM (2987) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SWs9_NM (2988) - MIPS_INS_SW - sw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SYNC (2989) - MIPS_INS_SYNC - sync $stype */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* stype */ + { 0 } +}}, +{ /* MIPS_SYNCI (2990) - MIPS_INS_SYNCI - synci $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SYNCI_MM (2991) - MIPS_INS_SYNCI - synci $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SYNCI_MMR6 (2992) - MIPS_INS_SYNCI - synci $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SYNCI_NM (2993) - MIPS_INS_SYNCI - synci $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SYNCIs9_NM (2994) - MIPS_INS_SYNCI - synci $addr */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SYNC_MM (2995) - MIPS_INS_SYNC - sync $stype */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* stype */ + { 0 } +}}, +{ /* MIPS_SYNC_MMR6 (2996) - MIPS_INS_SYNC - sync $stype */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* stype */ + { 0 } +}}, +{ /* MIPS_SYNC_NM (2997) - MIPS_INS_SYNC - sync $stype */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* stype */ + { 0 } +}}, +{ /* MIPS_SYSCALL (2998) - MIPS_INS_SYSCALL - syscall $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SYSCALL16_NM (2999) - MIPS_INS_SYSCALL - syscall $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_SYSCALL_MM (3000) - MIPS_INS_SYSCALL - syscall $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_SYSCALL_NM (3001) - MIPS_INS_SYSCALL - syscall $imm */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{{{ /* MIPS_Save16 (3002) - MIPS_INS_INVALID - */ + 0 +}}}, +{{{ /* MIPS_SaveX16 (3003) - MIPS_INS_INVALID - */ + 0 +}}}, +{ /* MIPS_SbRxRyOffMemX16 (3004) - MIPS_INS_SB - sb $ry, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - CPU16Regs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SebRx16 (3005) - MIPS_INS_SEB - seb $rx */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx_ */ + { 0 } +}}, +{ /* MIPS_SehRx16 (3006) - MIPS_INS_SEH - seh $rx */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx_ */ + { 0 } +}}, +{ /* MIPS_ShRxRyOffMemX16 (3007) - MIPS_INS_SH - sh $ry, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - CPU16Regs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SllX16 (3008) - MIPS_INS_SLL - sll $rx, $ry, $sa6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa6 */ + { 0 } +}}, +{ /* MIPS_SllvRxRy16 (3009) - MIPS_INS_SLLV - sllv $rz, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_SltRxRy16 (3010) - MIPS_INS_SLT - slt $rx, $ry */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_SltiRxImm16 (3011) - MIPS_INS_SLTI - slti $rx, $imm8 # 16 bit inst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* MIPS_SltiRxImmX16 (3012) - MIPS_INS_SLTI - slti $rx, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_SltiuRxImm16 (3013) - MIPS_INS_SLTIU - sltiu $rx, $imm8 # 16 bit inst */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */ + { 0 } +}}, +{ /* MIPS_SltiuRxImmX16 (3014) - MIPS_INS_SLTIU - sltiu $rx, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_SltuRxRy16 (3015) - MIPS_INS_SLTU - sltu $rx, $ry */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_SraX16 (3016) - MIPS_INS_SRA - sra $rx, $ry, $sa6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa6 */ + { 0 } +}}, +{ /* MIPS_SravRxRy16 (3017) - MIPS_INS_SRAV - srav $rz, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_SrlX16 (3018) - MIPS_INS_SRL - srl $rx, $ry, $sa6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sa6 */ + { 0 } +}}, +{ /* MIPS_SrlvRxRy16 (3019) - MIPS_INS_SRLV - srlv $rz, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_SubuRxRyRz16 (3020) - MIPS_INS_SUBU - subu $rz, $rx, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_SwRxRyOffMemX16 (3021) - MIPS_INS_SW - sw $ry, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - CPU16Regs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_SwRxSpImmX16 (3022) - MIPS_INS_SW - sw $ry, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - CPU16RegsPlusSP */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_TEQ (3023) - MIPS_INS_TEQ - teq $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TEQI (3024) - MIPS_INS_TEQI - teqi $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TEQI_MM (3025) - MIPS_INS_TEQI - teqi $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TEQ_MM (3026) - MIPS_INS_TEQ - teq $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TEQ_NM (3027) - MIPS_INS_TEQ - teq $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_TGE (3028) - MIPS_INS_TGE - tge $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TGEI (3029) - MIPS_INS_TGEI - tgei $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TGEIU (3030) - MIPS_INS_TGEIU - tgeiu $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TGEIU_MM (3031) - MIPS_INS_TGEIU - tgeiu $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TGEI_MM (3032) - MIPS_INS_TGEI - tgei $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TGEU (3033) - MIPS_INS_TGEU - tgeu $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TGEU_MM (3034) - MIPS_INS_TGEU - tgeu $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TGE_MM (3035) - MIPS_INS_TGE - tge $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TLBGINV (3036) - MIPS_INS_TLBGINV - tlbginv */ +{ + { 0 } +}}, +{ /* MIPS_TLBGINVF (3037) - MIPS_INS_TLBGINVF - tlbginvf */ +{ + { 0 } +}}, +{ /* MIPS_TLBGINVF_MM (3038) - MIPS_INS_TLBGINVF - tlbginvf */ +{ + { 0 } +}}, +{ /* MIPS_TLBGINV_MM (3039) - MIPS_INS_TLBGINV - tlbginv */ +{ + { 0 } +}}, +{ /* MIPS_TLBGP (3040) - MIPS_INS_TLBGP - tlbgp */ +{ + { 0 } +}}, +{ /* MIPS_TLBGP_MM (3041) - MIPS_INS_TLBGP - tlbgp */ +{ + { 0 } +}}, +{ /* MIPS_TLBGR (3042) - MIPS_INS_TLBGR - tlbgr */ +{ + { 0 } +}}, +{ /* MIPS_TLBGR_MM (3043) - MIPS_INS_TLBGR - tlbgr */ +{ + { 0 } +}}, +{ /* MIPS_TLBGWI (3044) - MIPS_INS_TLBGWI - tlbgwi */ +{ + { 0 } +}}, +{ /* MIPS_TLBGWI_MM (3045) - MIPS_INS_TLBGWI - tlbgwi */ +{ + { 0 } +}}, +{ /* MIPS_TLBGWR (3046) - MIPS_INS_TLBGWR - tlbgwr */ +{ + { 0 } +}}, +{ /* MIPS_TLBGWR_MM (3047) - MIPS_INS_TLBGWR - tlbgwr */ +{ + { 0 } +}}, +{ /* MIPS_TLBINV (3048) - MIPS_INS_TLBINV - tlbinv */ +{ + { 0 } +}}, +{ /* MIPS_TLBINVF (3049) - MIPS_INS_TLBINVF - tlbinvf */ +{ + { 0 } +}}, +{ /* MIPS_TLBINVF_MMR6 (3050) - MIPS_INS_TLBINVF - tlbinvf */ +{ + { 0 } +}}, +{ /* MIPS_TLBINVF_NM (3051) - MIPS_INS_TLBINVF - tlbinvf */ +{ + { 0 } +}}, +{ /* MIPS_TLBINV_MMR6 (3052) - MIPS_INS_TLBINV - tlbinv */ +{ + { 0 } +}}, +{ /* MIPS_TLBINV_NM (3053) - MIPS_INS_TLBINV - tlbinv */ +{ + { 0 } +}}, +{ /* MIPS_TLBP (3054) - MIPS_INS_TLBP - tlbp */ +{ + { 0 } +}}, +{ /* MIPS_TLBP_MM (3055) - MIPS_INS_TLBP - tlbp */ +{ + { 0 } +}}, +{ /* MIPS_TLBP_NM (3056) - MIPS_INS_TLBP - tlbp */ +{ + { 0 } +}}, +{ /* MIPS_TLBR (3057) - MIPS_INS_TLBR - tlbr */ +{ + { 0 } +}}, +{ /* MIPS_TLBR_MM (3058) - MIPS_INS_TLBR - tlbr */ +{ + { 0 } +}}, +{ /* MIPS_TLBR_NM (3059) - MIPS_INS_TLBR - tlbr */ +{ + { 0 } +}}, +{ /* MIPS_TLBWI (3060) - MIPS_INS_TLBWI - tlbwi */ +{ + { 0 } +}}, +{ /* MIPS_TLBWI_MM (3061) - MIPS_INS_TLBWI - tlbwi */ +{ + { 0 } +}}, +{ /* MIPS_TLBWI_NM (3062) - MIPS_INS_TLBWI - tlbwi */ +{ + { 0 } +}}, +{ /* MIPS_TLBWR (3063) - MIPS_INS_TLBWR - tlbwr */ +{ + { 0 } +}}, +{ /* MIPS_TLBWR_MM (3064) - MIPS_INS_TLBWR - tlbwr */ +{ + { 0 } +}}, +{ /* MIPS_TLBWR_NM (3065) - MIPS_INS_TLBWR - tlbwr */ +{ + { 0 } +}}, +{ /* MIPS_TLT (3066) - MIPS_INS_TLT - tlt $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TLTI (3067) - MIPS_INS_TLTI - tlti $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TLTIU_MM (3068) - MIPS_INS_TLTIU - tltiu $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TLTI_MM (3069) - MIPS_INS_TLTI - tlti $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TLTU (3070) - MIPS_INS_TLTU - tltu $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TLTU_MM (3071) - MIPS_INS_TLTU - tltu $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TLT_MM (3072) - MIPS_INS_TLT - tlt $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TNE (3073) - MIPS_INS_TNE - tne $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TNEI (3074) - MIPS_INS_TNEI - tnei $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TNEI_MM (3075) - MIPS_INS_TNEI - tnei $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_TNE_MM (3076) - MIPS_INS_TNE - tne $rs, $rt, $code_ */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_TNE_NM (3077) - MIPS_INS_TNE - tne $rs, $rt, $imm */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_TRUNC_L_D64 (3078) - MIPS_INS_TRUNC_L_D - trunc.l.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_L_D_MMR6 (3079) - MIPS_INS_TRUNC_L_D - trunc.l.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_L_S (3080) - MIPS_INS_TRUNC_L_S - trunc.l.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_L_S_MMR6 (3081) - MIPS_INS_TRUNC_L_S - trunc.l.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_W_D32 (3082) - MIPS_INS_TRUNC_W_D - trunc.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_W_D64 (3083) - MIPS_INS_TRUNC_W_D - trunc.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_W_D_MMR6 (3084) - MIPS_INS_TRUNC_W_D - trunc.w.d $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_W_MM (3085) - MIPS_INS_TRUNC_W_D - trunc.w.d $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_W_S (3086) - MIPS_INS_TRUNC_W_S - trunc.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_W_S_MM (3087) - MIPS_INS_TRUNC_W_S - trunc.w.s $fd, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TRUNC_W_S_MMR6 (3088) - MIPS_INS_TRUNC_W_S - trunc.w.s $ft, $fs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* ft */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* fs */ + { 0 } +}}, +{ /* MIPS_TTLTIU (3089) - MIPS_INS_TLTIU - tltiu $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_UALH_NM (3090) - MIPS_INS_UALH - ualh $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_UALWM_NM (3091) - MIPS_INS_UALWM - ualwm $rt, $addr, $rcount */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rcount */ + { 0 } +}}, +{ /* MIPS_UALW_NM (3092) - MIPS_INS_UALW - ualw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */ + { 0 } +}}, +{ /* MIPS_UASH_NM (3093) - MIPS_INS_UASH - uash $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_UASWM_NM (3094) - MIPS_INS_UASWM - uaswm $rt, $addr, $rcount */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rcount */ + { 0 } +}}, +{ /* MIPS_UASW_NM (3095) - MIPS_INS_UASW - uasw $rt, $addr */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_LAST } }, /* addr - ptr_rc */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - simm16 */ + { 0 } +}}, +{ /* MIPS_UDIV (3096) - MIPS_INS_DIVU - divu $$zero, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_UDIV_MM (3097) - MIPS_INS_DIVU - divu $$zero, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_V3MULU (3098) - MIPS_INS_V3MULU - v3mulu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_VMM0 (3099) - MIPS_INS_VMM0 - vmm0 $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_VMULU (3100) - MIPS_INS_VMULU - vmulu $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_VSHF_B (3101) - MIPS_INS_VSHF_B - vshf.b $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_VSHF_D (3102) - MIPS_INS_VSHF_D - vshf.d $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_VSHF_H (3103) - MIPS_INS_VSHF_H - vshf.h $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_VSHF_W (3104) - MIPS_INS_VSHF_W - vshf.w $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wd_in */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_WAIT (3105) - MIPS_INS_WAIT - wait */ +{ + { 0 } +}}, +{ /* MIPS_WAIT_MM (3106) - MIPS_INS_WAIT - wait $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_WAIT_MMR6 (3107) - MIPS_INS_WAIT - wait $code_ */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* code_ */ + { 0 } +}}, +{ /* MIPS_WAIT_NM (3108) - MIPS_INS_WAIT - wait $cd */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cd */ + { 0 } +}}, +{ /* MIPS_WRDSP (3109) - MIPS_INS_WRDSP - wrdsp $rs, $mask */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */ + { 0 } +}}, +{ /* MIPS_WRDSP_MM (3110) - MIPS_INS_WRDSP - wrdsp $rt, $mask */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */ + { 0 } +}}, +{ /* MIPS_WRPGPR_MMR6 (3111) - MIPS_INS_WRPGPR - wrpgpr $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_WRPGPR_NM (3112) - MIPS_INS_WRPGPR - wrpgpr $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_WSBH (3113) - MIPS_INS_WSBH - wsbh $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_WSBH_MM (3114) - MIPS_INS_WSBH - wsbh $rd, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_WSBH_MMR6 (3115) - MIPS_INS_WSBH - wsbh $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_XOR (3116) - MIPS_INS_XOR - xor $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_XOR16_MM (3117) - MIPS_INS_XOR16 - xor16 $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_XOR16_MMR6 (3118) - MIPS_INS_XOR16 - xor16 $rt, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_XOR16_NM (3119) - MIPS_INS_XOR - xor $dst, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{{{ /* MIPS_XOR64 (3120) - MIPS_INS_INVALID - xor $rd, $rs, $rt */ + 0 +}}}, +{ /* MIPS_XORI_B (3121) - MIPS_INS_XORI_B - xori.b $wd, $ws, $u8 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_vAny, CS_DATA_TYPE_LAST } }, /* u8 */ + { 0 } +}}, +{ /* MIPS_XORI_MMR6 (3122) - MIPS_INS_XORI - xori $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_XORI_NM (3123) - MIPS_INS_XORI - xori $rt, $rs, $imm */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */ + { 0 } +}}, +{ /* MIPS_XOR_MM (3124) - MIPS_INS_XOR - xor $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_XOR_MMR6 (3125) - MIPS_INS_XOR - xor $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_XOR_NM (3126) - MIPS_INS_XOR - xor $rd, $rs, $rt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { 0 } +}}, +{ /* MIPS_XOR_V (3127) - MIPS_INS_XOR_V - xor.v $wd, $ws, $wt */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* ws */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_LAST } }, /* wt */ + { 0 } +}}, +{ /* MIPS_XORi (3128) - MIPS_INS_XORI - xori $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{{{ /* MIPS_XORi64 (3129) - MIPS_INS_INVALID - xori $rt, $rs, $imm16 */ + 0 +}}}, +{ /* MIPS_XORi_MM (3130) - MIPS_INS_XORI - xori $rt, $rs, $imm16 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rt */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */ + { 0 } +}}, +{ /* MIPS_XorRxRxRy16 (3131) - MIPS_INS_XOR - xor $rz, $ry */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rz */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rx */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ry */ + { 0 } +}}, +{ /* MIPS_YIELD (3132) - MIPS_INS_YIELD - yield $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, +{ /* MIPS_YIELD_NM (3133) - MIPS_INS_YIELD - yield $rd, $rs */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rd */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rs */ + { 0 } +}}, diff --git a/arch/Mips/MipsGenCSOpGroup.inc b/arch/Mips/MipsGenCSOpGroup.inc new file mode 100644 index 0000000000..7e991ab535 --- /dev/null +++ b/arch/Mips/MipsGenCSOpGroup.inc @@ -0,0 +1,45 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + + Mips_OP_GROUP_Operand = 0, + Mips_OP_GROUP_BranchOperand = 1, + Mips_OP_GROUP_UImm_1_0 = 2, + Mips_OP_GROUP_UImm_2_0 = 3, + Mips_OP_GROUP_JumpOperand = 4, + Mips_OP_GROUP_MemOperand = 5, + Mips_OP_GROUP_RegisterList = 6, + Mips_OP_GROUP_UImm_3_0 = 7, + Mips_OP_GROUP_PCRel = 8, + Mips_OP_GROUP_UImm_32_0 = 9, + Mips_OP_GROUP_UImm_16_0 = 10, + Mips_OP_GROUP_UImm_8_0 = 11, + Mips_OP_GROUP_UImm_5_0 = 12, + Mips_OP_GROUP_Hi20PCRel = 13, + Mips_OP_GROUP_MemOperandEA = 14, + Mips_OP_GROUP_UImm_6_0 = 15, + Mips_OP_GROUP_UImm_4_0 = 16, + Mips_OP_GROUP_UImm_7_0 = 17, + Mips_OP_GROUP_UImm_10_0 = 18, + Mips_OP_GROUP_UImm_6_1 = 19, + Mips_OP_GROUP_UImm_5_1 = 20, + Mips_OP_GROUP_UImm_5_33 = 21, + Mips_OP_GROUP_UImm_5_32 = 22, + Mips_OP_GROUP_UImm_6_2 = 23, + Mips_OP_GROUP_UImm_2_1 = 24, + Mips_OP_GROUP_FCCOperand = 25, + Mips_OP_GROUP_UImm_0_0 = 26, + Mips_OP_GROUP_UImm_26_0 = 27, + Mips_OP_GROUP_Hi20 = 28, + Mips_OP_GROUP_NanoMipsRegisterList = 29, + Mips_OP_GROUP_UImm_12_0 = 30, + Mips_OP_GROUP_UImm_20_0 = 31, diff --git a/arch/Mips/MipsGenCSRegEnum.inc b/arch/Mips/MipsGenCSRegEnum.inc new file mode 100644 index 0000000000..90d2ca390f --- /dev/null +++ b/arch/Mips/MipsGenCSRegEnum.inc @@ -0,0 +1,649 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + + MIPS_REG_INVALID = 0, + MIPS_REG_AT = 1, + MIPS_REG_AT_NM = 2, + MIPS_REG_DSPCCOND = 3, + MIPS_REG_DSPCARRY = 4, + MIPS_REG_DSPEFI = 5, + MIPS_REG_DSPOUTFLAG = 6, + MIPS_REG_DSPPOS = 7, + MIPS_REG_DSPSCOUNT = 8, + MIPS_REG_FP = 9, + MIPS_REG_FP_NM = 10, + MIPS_REG_GP = 11, + MIPS_REG_GP_NM = 12, + MIPS_REG_MSAACCESS = 13, + MIPS_REG_MSACSR = 14, + MIPS_REG_MSAIR = 15, + MIPS_REG_MSAMAP = 16, + MIPS_REG_MSAMODIFY = 17, + MIPS_REG_MSAREQUEST = 18, + MIPS_REG_MSASAVE = 19, + MIPS_REG_MSAUNMAP = 20, + MIPS_REG_PC = 21, + MIPS_REG_RA = 22, + MIPS_REG_RA_NM = 23, + MIPS_REG_SP = 24, + MIPS_REG_SP_NM = 25, + MIPS_REG_ZERO = 26, + MIPS_REG_ZERO_NM = 27, + MIPS_REG_A0 = 28, + MIPS_REG_A1 = 29, + MIPS_REG_A2 = 30, + MIPS_REG_A3 = 31, + MIPS_REG_AC0 = 32, + MIPS_REG_AC1 = 33, + MIPS_REG_AC2 = 34, + MIPS_REG_AC3 = 35, + MIPS_REG_AT_64 = 36, + MIPS_REG_COP00 = 37, + MIPS_REG_COP01 = 38, + MIPS_REG_COP02 = 39, + MIPS_REG_COP03 = 40, + MIPS_REG_COP04 = 41, + MIPS_REG_COP05 = 42, + MIPS_REG_COP06 = 43, + MIPS_REG_COP07 = 44, + MIPS_REG_COP08 = 45, + MIPS_REG_COP09 = 46, + MIPS_REG_COP20 = 47, + MIPS_REG_COP21 = 48, + MIPS_REG_COP22 = 49, + MIPS_REG_COP23 = 50, + MIPS_REG_COP24 = 51, + MIPS_REG_COP25 = 52, + MIPS_REG_COP26 = 53, + MIPS_REG_COP27 = 54, + MIPS_REG_COP28 = 55, + MIPS_REG_COP29 = 56, + MIPS_REG_COP30 = 57, + MIPS_REG_COP31 = 58, + MIPS_REG_COP32 = 59, + MIPS_REG_COP33 = 60, + MIPS_REG_COP34 = 61, + MIPS_REG_COP35 = 62, + MIPS_REG_COP36 = 63, + MIPS_REG_COP37 = 64, + MIPS_REG_COP38 = 65, + MIPS_REG_COP39 = 66, + MIPS_REG_COP010 = 67, + MIPS_REG_COP011 = 68, + MIPS_REG_COP012 = 69, + MIPS_REG_COP013 = 70, + MIPS_REG_COP014 = 71, + MIPS_REG_COP015 = 72, + MIPS_REG_COP016 = 73, + MIPS_REG_COP017 = 74, + MIPS_REG_COP018 = 75, + MIPS_REG_COP019 = 76, + MIPS_REG_COP020 = 77, + MIPS_REG_COP021 = 78, + MIPS_REG_COP022 = 79, + MIPS_REG_COP023 = 80, + MIPS_REG_COP024 = 81, + MIPS_REG_COP025 = 82, + MIPS_REG_COP026 = 83, + MIPS_REG_COP027 = 84, + MIPS_REG_COP028 = 85, + MIPS_REG_COP029 = 86, + MIPS_REG_COP030 = 87, + MIPS_REG_COP031 = 88, + MIPS_REG_COP210 = 89, + MIPS_REG_COP211 = 90, + MIPS_REG_COP212 = 91, + MIPS_REG_COP213 = 92, + MIPS_REG_COP214 = 93, + MIPS_REG_COP215 = 94, + MIPS_REG_COP216 = 95, + MIPS_REG_COP217 = 96, + MIPS_REG_COP218 = 97, + MIPS_REG_COP219 = 98, + MIPS_REG_COP220 = 99, + MIPS_REG_COP221 = 100, + MIPS_REG_COP222 = 101, + MIPS_REG_COP223 = 102, + MIPS_REG_COP224 = 103, + MIPS_REG_COP225 = 104, + MIPS_REG_COP226 = 105, + MIPS_REG_COP227 = 106, + MIPS_REG_COP228 = 107, + MIPS_REG_COP229 = 108, + MIPS_REG_COP230 = 109, + MIPS_REG_COP231 = 110, + MIPS_REG_COP310 = 111, + MIPS_REG_COP311 = 112, + MIPS_REG_COP312 = 113, + MIPS_REG_COP313 = 114, + MIPS_REG_COP314 = 115, + MIPS_REG_COP315 = 116, + MIPS_REG_COP316 = 117, + MIPS_REG_COP317 = 118, + MIPS_REG_COP318 = 119, + MIPS_REG_COP319 = 120, + MIPS_REG_COP320 = 121, + MIPS_REG_COP321 = 122, + MIPS_REG_COP322 = 123, + MIPS_REG_COP323 = 124, + MIPS_REG_COP324 = 125, + MIPS_REG_COP325 = 126, + MIPS_REG_COP326 = 127, + MIPS_REG_COP327 = 128, + MIPS_REG_COP328 = 129, + MIPS_REG_COP329 = 130, + MIPS_REG_COP330 = 131, + MIPS_REG_COP331 = 132, + MIPS_REG_D0 = 133, + MIPS_REG_D1 = 134, + MIPS_REG_D2 = 135, + MIPS_REG_D3 = 136, + MIPS_REG_D4 = 137, + MIPS_REG_D5 = 138, + MIPS_REG_D6 = 139, + MIPS_REG_D7 = 140, + MIPS_REG_D8 = 141, + MIPS_REG_D9 = 142, + MIPS_REG_D10 = 143, + MIPS_REG_D11 = 144, + MIPS_REG_D12 = 145, + MIPS_REG_D13 = 146, + MIPS_REG_D14 = 147, + MIPS_REG_D15 = 148, + MIPS_REG_DSPOUTFLAG20 = 149, + MIPS_REG_DSPOUTFLAG21 = 150, + MIPS_REG_DSPOUTFLAG22 = 151, + MIPS_REG_DSPOUTFLAG23 = 152, + MIPS_REG_F0 = 153, + MIPS_REG_F1 = 154, + MIPS_REG_F2 = 155, + MIPS_REG_F3 = 156, + MIPS_REG_F4 = 157, + MIPS_REG_F5 = 158, + MIPS_REG_F6 = 159, + MIPS_REG_F7 = 160, + MIPS_REG_F8 = 161, + MIPS_REG_F9 = 162, + MIPS_REG_F10 = 163, + MIPS_REG_F11 = 164, + MIPS_REG_F12 = 165, + MIPS_REG_F13 = 166, + MIPS_REG_F14 = 167, + MIPS_REG_F15 = 168, + MIPS_REG_F16 = 169, + MIPS_REG_F17 = 170, + MIPS_REG_F18 = 171, + MIPS_REG_F19 = 172, + MIPS_REG_F20 = 173, + MIPS_REG_F21 = 174, + MIPS_REG_F22 = 175, + MIPS_REG_F23 = 176, + MIPS_REG_F24 = 177, + MIPS_REG_F25 = 178, + MIPS_REG_F26 = 179, + MIPS_REG_F27 = 180, + MIPS_REG_F28 = 181, + MIPS_REG_F29 = 182, + MIPS_REG_F30 = 183, + MIPS_REG_F31 = 184, + MIPS_REG_FCC0 = 185, + MIPS_REG_FCC1 = 186, + MIPS_REG_FCC2 = 187, + MIPS_REG_FCC3 = 188, + MIPS_REG_FCC4 = 189, + MIPS_REG_FCC5 = 190, + MIPS_REG_FCC6 = 191, + MIPS_REG_FCC7 = 192, + MIPS_REG_FCR0 = 193, + MIPS_REG_FCR1 = 194, + MIPS_REG_FCR2 = 195, + MIPS_REG_FCR3 = 196, + MIPS_REG_FCR4 = 197, + MIPS_REG_FCR5 = 198, + MIPS_REG_FCR6 = 199, + MIPS_REG_FCR7 = 200, + MIPS_REG_FCR8 = 201, + MIPS_REG_FCR9 = 202, + MIPS_REG_FCR10 = 203, + MIPS_REG_FCR11 = 204, + MIPS_REG_FCR12 = 205, + MIPS_REG_FCR13 = 206, + MIPS_REG_FCR14 = 207, + MIPS_REG_FCR15 = 208, + MIPS_REG_FCR16 = 209, + MIPS_REG_FCR17 = 210, + MIPS_REG_FCR18 = 211, + MIPS_REG_FCR19 = 212, + MIPS_REG_FCR20 = 213, + MIPS_REG_FCR21 = 214, + MIPS_REG_FCR22 = 215, + MIPS_REG_FCR23 = 216, + MIPS_REG_FCR24 = 217, + MIPS_REG_FCR25 = 218, + MIPS_REG_FCR26 = 219, + MIPS_REG_FCR27 = 220, + MIPS_REG_FCR28 = 221, + MIPS_REG_FCR29 = 222, + MIPS_REG_FCR30 = 223, + MIPS_REG_FCR31 = 224, + MIPS_REG_FP_64 = 225, + MIPS_REG_F_HI0 = 226, + MIPS_REG_F_HI1 = 227, + MIPS_REG_F_HI2 = 228, + MIPS_REG_F_HI3 = 229, + MIPS_REG_F_HI4 = 230, + MIPS_REG_F_HI5 = 231, + MIPS_REG_F_HI6 = 232, + MIPS_REG_F_HI7 = 233, + MIPS_REG_F_HI8 = 234, + MIPS_REG_F_HI9 = 235, + MIPS_REG_F_HI10 = 236, + MIPS_REG_F_HI11 = 237, + MIPS_REG_F_HI12 = 238, + MIPS_REG_F_HI13 = 239, + MIPS_REG_F_HI14 = 240, + MIPS_REG_F_HI15 = 241, + MIPS_REG_F_HI16 = 242, + MIPS_REG_F_HI17 = 243, + MIPS_REG_F_HI18 = 244, + MIPS_REG_F_HI19 = 245, + MIPS_REG_F_HI20 = 246, + MIPS_REG_F_HI21 = 247, + MIPS_REG_F_HI22 = 248, + MIPS_REG_F_HI23 = 249, + MIPS_REG_F_HI24 = 250, + MIPS_REG_F_HI25 = 251, + MIPS_REG_F_HI26 = 252, + MIPS_REG_F_HI27 = 253, + MIPS_REG_F_HI28 = 254, + MIPS_REG_F_HI29 = 255, + MIPS_REG_F_HI30 = 256, + MIPS_REG_F_HI31 = 257, + MIPS_REG_GP_64 = 258, + MIPS_REG_HI0 = 259, + MIPS_REG_HI1 = 260, + MIPS_REG_HI2 = 261, + MIPS_REG_HI3 = 262, + MIPS_REG_HWR0 = 263, + MIPS_REG_HWR1 = 264, + MIPS_REG_HWR2 = 265, + MIPS_REG_HWR3 = 266, + MIPS_REG_HWR4 = 267, + MIPS_REG_HWR5 = 268, + MIPS_REG_HWR6 = 269, + MIPS_REG_HWR7 = 270, + MIPS_REG_HWR8 = 271, + MIPS_REG_HWR9 = 272, + MIPS_REG_HWR10 = 273, + MIPS_REG_HWR11 = 274, + MIPS_REG_HWR12 = 275, + MIPS_REG_HWR13 = 276, + MIPS_REG_HWR14 = 277, + MIPS_REG_HWR15 = 278, + MIPS_REG_HWR16 = 279, + MIPS_REG_HWR17 = 280, + MIPS_REG_HWR18 = 281, + MIPS_REG_HWR19 = 282, + MIPS_REG_HWR20 = 283, + MIPS_REG_HWR21 = 284, + MIPS_REG_HWR22 = 285, + MIPS_REG_HWR23 = 286, + MIPS_REG_HWR24 = 287, + MIPS_REG_HWR25 = 288, + MIPS_REG_HWR26 = 289, + MIPS_REG_HWR27 = 290, + MIPS_REG_HWR28 = 291, + MIPS_REG_HWR29 = 292, + MIPS_REG_HWR30 = 293, + MIPS_REG_HWR31 = 294, + MIPS_REG_K0 = 295, + MIPS_REG_K1 = 296, + MIPS_REG_LO0 = 297, + MIPS_REG_LO1 = 298, + MIPS_REG_LO2 = 299, + MIPS_REG_LO3 = 300, + MIPS_REG_MPL0 = 301, + MIPS_REG_MPL1 = 302, + MIPS_REG_MPL2 = 303, + MIPS_REG_MSA8 = 304, + MIPS_REG_MSA9 = 305, + MIPS_REG_MSA10 = 306, + MIPS_REG_MSA11 = 307, + MIPS_REG_MSA12 = 308, + MIPS_REG_MSA13 = 309, + MIPS_REG_MSA14 = 310, + MIPS_REG_MSA15 = 311, + MIPS_REG_MSA16 = 312, + MIPS_REG_MSA17 = 313, + MIPS_REG_MSA18 = 314, + MIPS_REG_MSA19 = 315, + MIPS_REG_MSA20 = 316, + MIPS_REG_MSA21 = 317, + MIPS_REG_MSA22 = 318, + MIPS_REG_MSA23 = 319, + MIPS_REG_MSA24 = 320, + MIPS_REG_MSA25 = 321, + MIPS_REG_MSA26 = 322, + MIPS_REG_MSA27 = 323, + MIPS_REG_MSA28 = 324, + MIPS_REG_MSA29 = 325, + MIPS_REG_MSA30 = 326, + MIPS_REG_MSA31 = 327, + MIPS_REG_P0 = 328, + MIPS_REG_P1 = 329, + MIPS_REG_P2 = 330, + MIPS_REG_RA_64 = 331, + MIPS_REG_S0 = 332, + MIPS_REG_S1 = 333, + MIPS_REG_S2 = 334, + MIPS_REG_S3 = 335, + MIPS_REG_S4 = 336, + MIPS_REG_S5 = 337, + MIPS_REG_S6 = 338, + MIPS_REG_S7 = 339, + MIPS_REG_SP_64 = 340, + MIPS_REG_T0 = 341, + MIPS_REG_T1 = 342, + MIPS_REG_T2 = 343, + MIPS_REG_T3 = 344, + MIPS_REG_T4 = 345, + MIPS_REG_T5 = 346, + MIPS_REG_T6 = 347, + MIPS_REG_T7 = 348, + MIPS_REG_T8 = 349, + MIPS_REG_T9 = 350, + MIPS_REG_V0 = 351, + MIPS_REG_V1 = 352, + MIPS_REG_W0 = 353, + MIPS_REG_W1 = 354, + MIPS_REG_W2 = 355, + MIPS_REG_W3 = 356, + MIPS_REG_W4 = 357, + MIPS_REG_W5 = 358, + MIPS_REG_W6 = 359, + MIPS_REG_W7 = 360, + MIPS_REG_W8 = 361, + MIPS_REG_W9 = 362, + MIPS_REG_W10 = 363, + MIPS_REG_W11 = 364, + MIPS_REG_W12 = 365, + MIPS_REG_W13 = 366, + MIPS_REG_W14 = 367, + MIPS_REG_W15 = 368, + MIPS_REG_W16 = 369, + MIPS_REG_W17 = 370, + MIPS_REG_W18 = 371, + MIPS_REG_W19 = 372, + MIPS_REG_W20 = 373, + MIPS_REG_W21 = 374, + MIPS_REG_W22 = 375, + MIPS_REG_W23 = 376, + MIPS_REG_W24 = 377, + MIPS_REG_W25 = 378, + MIPS_REG_W26 = 379, + MIPS_REG_W27 = 380, + MIPS_REG_W28 = 381, + MIPS_REG_W29 = 382, + MIPS_REG_W30 = 383, + MIPS_REG_W31 = 384, + MIPS_REG_ZERO_64 = 385, + MIPS_REG_A0_NM = 386, + MIPS_REG_A1_NM = 387, + MIPS_REG_A2_NM = 388, + MIPS_REG_A3_NM = 389, + MIPS_REG_A4_NM = 390, + MIPS_REG_A5_NM = 391, + MIPS_REG_A6_NM = 392, + MIPS_REG_A7_NM = 393, + MIPS_REG_COP0SEL_BADINST = 394, + MIPS_REG_COP0SEL_BADINSTRP = 395, + MIPS_REG_COP0SEL_BADINSTRX = 396, + MIPS_REG_COP0SEL_BADVADDR = 397, + MIPS_REG_COP0SEL_BEVVA = 398, + MIPS_REG_COP0SEL_CACHEERR = 399, + MIPS_REG_COP0SEL_CAUSE = 400, + MIPS_REG_COP0SEL_CDMMBASE = 401, + MIPS_REG_COP0SEL_CMGCRBASE = 402, + MIPS_REG_COP0SEL_COMPARE = 403, + MIPS_REG_COP0SEL_CONFIG = 404, + MIPS_REG_COP0SEL_CONTEXT = 405, + MIPS_REG_COP0SEL_CONTEXTCONFIG = 406, + MIPS_REG_COP0SEL_COUNT = 407, + MIPS_REG_COP0SEL_DDATAHI = 408, + MIPS_REG_COP0SEL_DDATALO = 409, + MIPS_REG_COP0SEL_DEBUG = 410, + MIPS_REG_COP0SEL_DEBUGCONTEXTID = 411, + MIPS_REG_COP0SEL_DEPC = 412, + MIPS_REG_COP0SEL_DESAVE = 413, + MIPS_REG_COP0SEL_DTAGHI = 414, + MIPS_REG_COP0SEL_DTAGLO = 415, + MIPS_REG_COP0SEL_EBASE = 416, + MIPS_REG_COP0SEL_ENTRYHI = 417, + MIPS_REG_COP0SEL_EPC = 418, + MIPS_REG_COP0SEL_ERRCTL = 419, + MIPS_REG_COP0SEL_ERROREPC = 420, + MIPS_REG_COP0SEL_GLOBALNUMBER = 421, + MIPS_REG_COP0SEL_GTOFFSET = 422, + MIPS_REG_COP0SEL_HWRENA = 423, + MIPS_REG_COP0SEL_IDATAHI = 424, + MIPS_REG_COP0SEL_IDATALO = 425, + MIPS_REG_COP0SEL_INDEX = 426, + MIPS_REG_COP0SEL_INTCTL = 427, + MIPS_REG_COP0SEL_ITAGHI = 428, + MIPS_REG_COP0SEL_ITAGLO = 429, + MIPS_REG_COP0SEL_LLADDR = 430, + MIPS_REG_COP0SEL_MAAR = 431, + MIPS_REG_COP0SEL_MAARI = 432, + MIPS_REG_COP0SEL_MEMORYMAPID = 433, + MIPS_REG_COP0SEL_MVPCONTROL = 434, + MIPS_REG_COP0SEL_NESTEDEPC = 435, + MIPS_REG_COP0SEL_NESTEDEXC = 436, + MIPS_REG_COP0SEL_PAGEGRAIN = 437, + MIPS_REG_COP0SEL_PAGEMASK = 438, + MIPS_REG_COP0SEL_PRID = 439, + MIPS_REG_COP0SEL_PWBASE = 440, + MIPS_REG_COP0SEL_PWCTL = 441, + MIPS_REG_COP0SEL_PWFIELD = 442, + MIPS_REG_COP0SEL_PWSIZE = 443, + MIPS_REG_COP0SEL_RANDOM = 444, + MIPS_REG_COP0SEL_SRSCTL = 445, + MIPS_REG_COP0SEL_SRSMAP = 446, + MIPS_REG_COP0SEL_STATUS = 447, + MIPS_REG_COP0SEL_TCBIND = 448, + MIPS_REG_COP0SEL_TCCONTEXT = 449, + MIPS_REG_COP0SEL_TCHALT = 450, + MIPS_REG_COP0SEL_TCOPT = 451, + MIPS_REG_COP0SEL_TCRESTART = 452, + MIPS_REG_COP0SEL_TCSCHEDULE = 453, + MIPS_REG_COP0SEL_TCSCHEFBACK = 454, + MIPS_REG_COP0SEL_TCSTATUS = 455, + MIPS_REG_COP0SEL_TRACECONTROL = 456, + MIPS_REG_COP0SEL_TRACEDBPC = 457, + MIPS_REG_COP0SEL_TRACEIBPC = 458, + MIPS_REG_COP0SEL_USERLOCAL = 459, + MIPS_REG_COP0SEL_VIEW_IPL = 460, + MIPS_REG_COP0SEL_VIEW_RIPL = 461, + MIPS_REG_COP0SEL_VPCONTROL = 462, + MIPS_REG_COP0SEL_VPECONTROL = 463, + MIPS_REG_COP0SEL_VPEOPT = 464, + MIPS_REG_COP0SEL_VPESCHEDULE = 465, + MIPS_REG_COP0SEL_VPESCHEFBACK = 466, + MIPS_REG_COP0SEL_WIRED = 467, + MIPS_REG_COP0SEL_XCONTEXT = 468, + MIPS_REG_COP0SEL_XCONTEXTCONFIG = 469, + MIPS_REG_COP0SEL_YQMASK = 470, + MIPS_REG_K0_NM = 471, + MIPS_REG_K1_NM = 472, + MIPS_REG_S0_NM = 473, + MIPS_REG_S1_NM = 474, + MIPS_REG_S2_NM = 475, + MIPS_REG_S3_NM = 476, + MIPS_REG_S4_NM = 477, + MIPS_REG_S5_NM = 478, + MIPS_REG_S6_NM = 479, + MIPS_REG_S7_NM = 480, + MIPS_REG_T0_NM = 481, + MIPS_REG_T1_NM = 482, + MIPS_REG_T2_NM = 483, + MIPS_REG_T3_NM = 484, + MIPS_REG_T4_NM = 485, + MIPS_REG_T5_NM = 486, + MIPS_REG_T8_NM = 487, + MIPS_REG_T9_NM = 488, + MIPS_REG_A0_64 = 489, + MIPS_REG_A1_64 = 490, + MIPS_REG_A2_64 = 491, + MIPS_REG_A3_64 = 492, + MIPS_REG_AC0_64 = 493, + MIPS_REG_COP0SEL_CONFIG1 = 494, + MIPS_REG_COP0SEL_CONFIG2 = 495, + MIPS_REG_COP0SEL_CONFIG3 = 496, + MIPS_REG_COP0SEL_CONFIG4 = 497, + MIPS_REG_COP0SEL_CONFIG5 = 498, + MIPS_REG_COP0SEL_DEBUG2 = 499, + MIPS_REG_COP0SEL_ENTRYLO0 = 500, + MIPS_REG_COP0SEL_ENTRYLO1 = 501, + MIPS_REG_COP0SEL_GUESTCTL0 = 502, + MIPS_REG_COP0SEL_GUESTCTL1 = 503, + MIPS_REG_COP0SEL_GUESTCTL2 = 504, + MIPS_REG_COP0SEL_GUESTCTL3 = 505, + MIPS_REG_COP0SEL_KSCRATCH1 = 506, + MIPS_REG_COP0SEL_KSCRATCH2 = 507, + MIPS_REG_COP0SEL_KSCRATCH3 = 508, + MIPS_REG_COP0SEL_KSCRATCH4 = 509, + MIPS_REG_COP0SEL_KSCRATCH5 = 510, + MIPS_REG_COP0SEL_KSCRATCH6 = 511, + MIPS_REG_COP0SEL_MVPCONF0 = 512, + MIPS_REG_COP0SEL_MVPCONF1 = 513, + MIPS_REG_COP0SEL_PERFCNT0 = 514, + MIPS_REG_COP0SEL_PERFCNT1 = 515, + MIPS_REG_COP0SEL_PERFCNT2 = 516, + MIPS_REG_COP0SEL_PERFCNT3 = 517, + MIPS_REG_COP0SEL_PERFCNT4 = 518, + MIPS_REG_COP0SEL_PERFCNT5 = 519, + MIPS_REG_COP0SEL_PERFCNT6 = 520, + MIPS_REG_COP0SEL_PERFCNT7 = 521, + MIPS_REG_COP0SEL_PERFCTL0 = 522, + MIPS_REG_COP0SEL_PERFCTL1 = 523, + MIPS_REG_COP0SEL_PERFCTL2 = 524, + MIPS_REG_COP0SEL_PERFCTL3 = 525, + MIPS_REG_COP0SEL_PERFCTL4 = 526, + MIPS_REG_COP0SEL_PERFCTL5 = 527, + MIPS_REG_COP0SEL_PERFCTL6 = 528, + MIPS_REG_COP0SEL_PERFCTL7 = 529, + MIPS_REG_COP0SEL_SEGCTL0 = 530, + MIPS_REG_COP0SEL_SEGCTL1 = 531, + MIPS_REG_COP0SEL_SEGCTL2 = 532, + MIPS_REG_COP0SEL_SRSCONF0 = 533, + MIPS_REG_COP0SEL_SRSCONF1 = 534, + MIPS_REG_COP0SEL_SRSCONF2 = 535, + MIPS_REG_COP0SEL_SRSCONF3 = 536, + MIPS_REG_COP0SEL_SRSCONF4 = 537, + MIPS_REG_COP0SEL_SRSMAP2 = 538, + MIPS_REG_COP0SEL_TRACECONTROL2 = 539, + MIPS_REG_COP0SEL_TRACECONTROL3 = 540, + MIPS_REG_COP0SEL_USERTRACEDATA1 = 541, + MIPS_REG_COP0SEL_USERTRACEDATA2 = 542, + MIPS_REG_COP0SEL_VPECONF0 = 543, + MIPS_REG_COP0SEL_VPECONF1 = 544, + MIPS_REG_COP0SEL_WATCHHI0 = 545, + MIPS_REG_COP0SEL_WATCHHI1 = 546, + MIPS_REG_COP0SEL_WATCHHI2 = 547, + MIPS_REG_COP0SEL_WATCHHI3 = 548, + MIPS_REG_COP0SEL_WATCHHI4 = 549, + MIPS_REG_COP0SEL_WATCHHI5 = 550, + MIPS_REG_COP0SEL_WATCHHI6 = 551, + MIPS_REG_COP0SEL_WATCHHI7 = 552, + MIPS_REG_COP0SEL_WATCHHI8 = 553, + MIPS_REG_COP0SEL_WATCHHI9 = 554, + MIPS_REG_COP0SEL_WATCHHI10 = 555, + MIPS_REG_COP0SEL_WATCHHI11 = 556, + MIPS_REG_COP0SEL_WATCHHI12 = 557, + MIPS_REG_COP0SEL_WATCHHI13 = 558, + MIPS_REG_COP0SEL_WATCHHI14 = 559, + MIPS_REG_COP0SEL_WATCHHI15 = 560, + MIPS_REG_COP0SEL_WATCHLO0 = 561, + MIPS_REG_COP0SEL_WATCHLO1 = 562, + MIPS_REG_COP0SEL_WATCHLO2 = 563, + MIPS_REG_COP0SEL_WATCHLO3 = 564, + MIPS_REG_COP0SEL_WATCHLO4 = 565, + MIPS_REG_COP0SEL_WATCHLO5 = 566, + MIPS_REG_COP0SEL_WATCHLO6 = 567, + MIPS_REG_COP0SEL_WATCHLO7 = 568, + MIPS_REG_COP0SEL_WATCHLO8 = 569, + MIPS_REG_COP0SEL_WATCHLO9 = 570, + MIPS_REG_COP0SEL_WATCHLO10 = 571, + MIPS_REG_COP0SEL_WATCHLO11 = 572, + MIPS_REG_COP0SEL_WATCHLO12 = 573, + MIPS_REG_COP0SEL_WATCHLO13 = 574, + MIPS_REG_COP0SEL_WATCHLO14 = 575, + MIPS_REG_COP0SEL_WATCHLO15 = 576, + MIPS_REG_D0_64 = 577, + MIPS_REG_D1_64 = 578, + MIPS_REG_D2_64 = 579, + MIPS_REG_D3_64 = 580, + MIPS_REG_D4_64 = 581, + MIPS_REG_D5_64 = 582, + MIPS_REG_D6_64 = 583, + MIPS_REG_D7_64 = 584, + MIPS_REG_D8_64 = 585, + MIPS_REG_D9_64 = 586, + MIPS_REG_D10_64 = 587, + MIPS_REG_D11_64 = 588, + MIPS_REG_D12_64 = 589, + MIPS_REG_D13_64 = 590, + MIPS_REG_D14_64 = 591, + MIPS_REG_D15_64 = 592, + MIPS_REG_D16_64 = 593, + MIPS_REG_D17_64 = 594, + MIPS_REG_D18_64 = 595, + MIPS_REG_D19_64 = 596, + MIPS_REG_D20_64 = 597, + MIPS_REG_D21_64 = 598, + MIPS_REG_D22_64 = 599, + MIPS_REG_D23_64 = 600, + MIPS_REG_D24_64 = 601, + MIPS_REG_D25_64 = 602, + MIPS_REG_D26_64 = 603, + MIPS_REG_D27_64 = 604, + MIPS_REG_D28_64 = 605, + MIPS_REG_D29_64 = 606, + MIPS_REG_D30_64 = 607, + MIPS_REG_D31_64 = 608, + MIPS_REG_DSPOUTFLAG16_19 = 609, + MIPS_REG_HI0_64 = 610, + MIPS_REG_K0_64 = 611, + MIPS_REG_K1_64 = 612, + MIPS_REG_LO0_64 = 613, + MIPS_REG_S0_64 = 614, + MIPS_REG_S1_64 = 615, + MIPS_REG_S2_64 = 616, + MIPS_REG_S3_64 = 617, + MIPS_REG_S4_64 = 618, + MIPS_REG_S5_64 = 619, + MIPS_REG_S6_64 = 620, + MIPS_REG_S7_64 = 621, + MIPS_REG_T0_64 = 622, + MIPS_REG_T1_64 = 623, + MIPS_REG_T2_64 = 624, + MIPS_REG_T3_64 = 625, + MIPS_REG_T4_64 = 626, + MIPS_REG_T5_64 = 627, + MIPS_REG_T6_64 = 628, + MIPS_REG_T7_64 = 629, + MIPS_REG_T8_64 = 630, + MIPS_REG_T9_64 = 631, + MIPS_REG_V0_64 = 632, + MIPS_REG_V1_64 = 633, + MIPS_REG_COP0SEL_GUESTCTL0EXT = 634, + MIPS_REG_ENDING, // 635 diff --git a/arch/Mips/MipsGenDisassemblerTables.inc b/arch/Mips/MipsGenDisassemblerTables.inc index e926f77884..262ea8be87 100644 --- a/arch/Mips/MipsGenDisassemblerTables.inc +++ b/arch/Mips/MipsGenDisassemblerTables.inc @@ -1,13 +1,15 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* * Mips Disassembler *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ #include "../../MCInst.h" #include "../../LEB128.h" @@ -17,6915 +19,12096 @@ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ { \ InsnType fieldMask; \ - if (numBits == sizeof(InsnType)*8) \ + if (numBits == sizeof(InsnType) * 8) \ fieldMask = (InsnType)(-1LL); \ else \ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ return (insn & fieldMask) >> startBit; \ } +static bool Check(DecodeStatus *Out, const DecodeStatus In) { + *Out = (DecodeStatus) (*Out & In); + return *Out != MCDisassembler_Fail; +} + +static const uint8_t DecoderTable16[] = { +/* 0 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 3 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 17 +/* 8 */ MCD_OPC_CheckPredicate, 0, 92, 2, 0, // Skip to: 617 +/* 13 */ MCD_OPC_Decode, 237, 8, 0, // Opcode: Bimm16 +/* 17 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 31 +/* 22 */ MCD_OPC_CheckPredicate, 0, 78, 2, 0, // Skip to: 617 +/* 27 */ MCD_OPC_Decode, 235, 8, 1, // Opcode: BeqzRxImm16 +/* 31 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 45 +/* 36 */ MCD_OPC_CheckPredicate, 0, 64, 2, 0, // Skip to: 617 +/* 41 */ MCD_OPC_Decode, 239, 8, 1, // Opcode: BnezRxImm16 +/* 45 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 59 +/* 50 */ MCD_OPC_CheckPredicate, 0, 50, 2, 0, // Skip to: 617 +/* 55 */ MCD_OPC_Decode, 138, 7, 2, // Opcode: AddiuRxRxImm16 +/* 59 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 73 +/* 64 */ MCD_OPC_CheckPredicate, 0, 36, 2, 0, // Skip to: 617 +/* 69 */ MCD_OPC_Decode, 195, 23, 3, // Opcode: SltiRxImm16 +/* 73 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 87 +/* 78 */ MCD_OPC_CheckPredicate, 0, 22, 2, 0, // Skip to: 617 +/* 83 */ MCD_OPC_Decode, 197, 23, 3, // Opcode: SltiuRxImm16 +/* 87 */ MCD_OPC_FilterValue, 12, 73, 0, 0, // Skip to: 165 +/* 92 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 95 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 109 +/* 100 */ MCD_OPC_CheckPredicate, 0, 0, 2, 0, // Skip to: 617 +/* 105 */ MCD_OPC_Decode, 242, 8, 4, // Opcode: Bteqz16 +/* 109 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 123 +/* 114 */ MCD_OPC_CheckPredicate, 0, 242, 1, 0, // Skip to: 617 +/* 119 */ MCD_OPC_Decode, 244, 8, 4, // Opcode: Btnez16 +/* 123 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 137 +/* 128 */ MCD_OPC_CheckPredicate, 0, 228, 1, 0, // Skip to: 617 +/* 133 */ MCD_OPC_Decode, 141, 7, 4, // Opcode: AddiuSpImm16 +/* 137 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 151 +/* 142 */ MCD_OPC_CheckPredicate, 0, 214, 1, 0, // Skip to: 617 +/* 147 */ MCD_OPC_Decode, 129, 19, 5, // Opcode: Move32R16 +/* 151 */ MCD_OPC_FilterValue, 7, 205, 1, 0, // Skip to: 617 +/* 156 */ MCD_OPC_CheckPredicate, 0, 200, 1, 0, // Skip to: 617 +/* 161 */ MCD_OPC_Decode, 130, 19, 6, // Opcode: MoveR3216 +/* 165 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 179 +/* 170 */ MCD_OPC_CheckPredicate, 0, 186, 1, 0, // Skip to: 617 +/* 175 */ MCD_OPC_Decode, 188, 16, 3, // Opcode: LiRxImm16 +/* 179 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 193 +/* 184 */ MCD_OPC_CheckPredicate, 0, 172, 1, 0, // Skip to: 617 +/* 189 */ MCD_OPC_Decode, 189, 11, 3, // Opcode: CmpiRxImm16 +/* 193 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 207 +/* 198 */ MCD_OPC_CheckPredicate, 0, 158, 1, 0, // Skip to: 617 +/* 203 */ MCD_OPC_Decode, 191, 16, 7, // Opcode: LwRxPcTcp16 +/* 207 */ MCD_OPC_FilterValue, 28, 31, 0, 0, // Skip to: 243 +/* 212 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 215 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 229 +/* 220 */ MCD_OPC_CheckPredicate, 0, 136, 1, 0, // Skip to: 617 +/* 225 */ MCD_OPC_Decode, 143, 7, 8, // Opcode: AdduRxRyRz16 +/* 229 */ MCD_OPC_FilterValue, 3, 127, 1, 0, // Skip to: 617 +/* 234 */ MCD_OPC_CheckPredicate, 0, 122, 1, 0, // Skip to: 617 +/* 239 */ MCD_OPC_Decode, 204, 23, 8, // Opcode: SubuRxRyRz16 +/* 243 */ MCD_OPC_FilterValue, 29, 113, 1, 0, // Skip to: 617 +/* 248 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 251 */ MCD_OPC_FilterValue, 0, 80, 0, 0, // Skip to: 336 +/* 256 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... +/* 259 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 273 +/* 264 */ MCD_OPC_CheckPredicate, 0, 92, 1, 0, // Skip to: 617 +/* 269 */ MCD_OPC_Decode, 151, 15, 9, // Opcode: JumpLinkReg16 +/* 273 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 294 +/* 278 */ MCD_OPC_CheckPredicate, 0, 78, 1, 0, // Skip to: 617 +/* 283 */ MCD_OPC_CheckField, 8, 3, 0, 71, 1, 0, // Skip to: 617 +/* 290 */ MCD_OPC_Decode, 148, 15, 10, // Opcode: JrRa16 +/* 294 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 315 +/* 299 */ MCD_OPC_CheckPredicate, 0, 57, 1, 0, // Skip to: 617 +/* 304 */ MCD_OPC_CheckField, 8, 3, 0, 50, 1, 0, // Skip to: 617 +/* 311 */ MCD_OPC_Decode, 150, 15, 10, // Opcode: JrcRx16 +/* 315 */ MCD_OPC_FilterValue, 7, 41, 1, 0, // Skip to: 617 +/* 320 */ MCD_OPC_CheckPredicate, 0, 36, 1, 0, // Skip to: 617 +/* 325 */ MCD_OPC_CheckField, 8, 3, 0, 29, 1, 0, // Skip to: 617 +/* 332 */ MCD_OPC_Decode, 149, 15, 10, // Opcode: JrcRa16 +/* 336 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 350 +/* 341 */ MCD_OPC_CheckPredicate, 0, 15, 1, 0, // Skip to: 617 +/* 346 */ MCD_OPC_Decode, 194, 23, 11, // Opcode: SltRxRy16 +/* 350 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 364 +/* 355 */ MCD_OPC_CheckPredicate, 0, 1, 1, 0, // Skip to: 617 +/* 360 */ MCD_OPC_Decode, 199, 23, 11, // Opcode: SltuRxRy16 +/* 364 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 378 +/* 369 */ MCD_OPC_CheckPredicate, 0, 243, 0, 0, // Skip to: 617 +/* 374 */ MCD_OPC_Decode, 193, 23, 12, // Opcode: SllvRxRy16 +/* 378 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 399 +/* 383 */ MCD_OPC_CheckPredicate, 0, 229, 0, 0, // Skip to: 617 +/* 388 */ MCD_OPC_CheckField, 5, 6, 0, 222, 0, 0, // Skip to: 617 +/* 395 */ MCD_OPC_Decode, 241, 8, 10, // Opcode: Break16 +/* 399 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 413 +/* 404 */ MCD_OPC_CheckPredicate, 0, 208, 0, 0, // Skip to: 617 +/* 409 */ MCD_OPC_Decode, 203, 23, 12, // Opcode: SrlvRxRy16 +/* 413 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 427 +/* 418 */ MCD_OPC_CheckPredicate, 0, 194, 0, 0, // Skip to: 617 +/* 423 */ MCD_OPC_Decode, 201, 23, 12, // Opcode: SravRxRy16 +/* 427 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 441 +/* 432 */ MCD_OPC_CheckPredicate, 0, 180, 0, 0, // Skip to: 617 +/* 437 */ MCD_OPC_Decode, 188, 11, 11, // Opcode: CmpRxRy16 +/* 441 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 455 +/* 446 */ MCD_OPC_CheckPredicate, 0, 166, 0, 0, // Skip to: 617 +/* 451 */ MCD_OPC_Decode, 144, 7, 12, // Opcode: AndRxRxRy16 +/* 455 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 469 +/* 460 */ MCD_OPC_CheckPredicate, 0, 152, 0, 0, // Skip to: 617 +/* 465 */ MCD_OPC_Decode, 178, 19, 12, // Opcode: OrRxRxRy16 +/* 469 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 483 +/* 474 */ MCD_OPC_CheckPredicate, 0, 138, 0, 0, // Skip to: 617 +/* 479 */ MCD_OPC_Decode, 187, 24, 12, // Opcode: XorRxRxRy16 +/* 483 */ MCD_OPC_FilterValue, 15, 9, 0, 0, // Skip to: 497 +/* 488 */ MCD_OPC_CheckPredicate, 0, 124, 0, 0, // Skip to: 617 +/* 493 */ MCD_OPC_Decode, 162, 19, 11, // Opcode: NotRxRy16 +/* 497 */ MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 518 +/* 502 */ MCD_OPC_CheckPredicate, 0, 110, 0, 0, // Skip to: 617 +/* 507 */ MCD_OPC_CheckField, 5, 3, 0, 103, 0, 0, // Skip to: 617 +/* 514 */ MCD_OPC_Decode, 255, 18, 9, // Opcode: Mfhi16 +/* 518 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 554 +/* 523 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... +/* 526 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 540 +/* 531 */ MCD_OPC_CheckPredicate, 0, 81, 0, 0, // Skip to: 617 +/* 536 */ MCD_OPC_Decode, 189, 23, 13, // Opcode: SebRx16 +/* 540 */ MCD_OPC_FilterValue, 5, 72, 0, 0, // Skip to: 617 +/* 545 */ MCD_OPC_CheckPredicate, 0, 67, 0, 0, // Skip to: 617 +/* 550 */ MCD_OPC_Decode, 190, 23, 13, // Opcode: SehRx16 +/* 554 */ MCD_OPC_FilterValue, 18, 16, 0, 0, // Skip to: 575 +/* 559 */ MCD_OPC_CheckPredicate, 0, 53, 0, 0, // Skip to: 617 +/* 564 */ MCD_OPC_CheckField, 5, 3, 0, 46, 0, 0, // Skip to: 617 +/* 571 */ MCD_OPC_Decode, 128, 19, 9, // Opcode: Mflo16 +/* 575 */ MCD_OPC_FilterValue, 26, 9, 0, 0, // Skip to: 589 +/* 580 */ MCD_OPC_CheckPredicate, 0, 32, 0, 0, // Skip to: 617 +/* 585 */ MCD_OPC_Decode, 204, 12, 11, // Opcode: DivRxRy16 +/* 589 */ MCD_OPC_FilterValue, 27, 9, 0, 0, // Skip to: 603 +/* 594 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 617 +/* 599 */ MCD_OPC_Decode, 205, 12, 11, // Opcode: DivuRxRy16 +/* 603 */ MCD_OPC_FilterValue, 29, 9, 0, 0, // Skip to: 617 +/* 608 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 617 +/* 613 */ MCD_OPC_Decode, 161, 19, 11, // Opcode: NegRxRy16 +/* 617 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTable32[] = { +/* 0 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 3 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 31 +/* 8 */ MCD_OPC_CheckPredicate, 0, 2, 2, 0, // Skip to: 527 +/* 13 */ MCD_OPC_CheckField, 27, 5, 30, 251, 1, 0, // Skip to: 527 +/* 20 */ MCD_OPC_CheckField, 5, 3, 0, 244, 1, 0, // Skip to: 527 +/* 27 */ MCD_OPC_Decode, 137, 7, 14, // Opcode: AddiuRxPcImmX16 +/* 31 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 59 +/* 36 */ MCD_OPC_CheckPredicate, 0, 230, 1, 0, // Skip to: 527 +/* 41 */ MCD_OPC_CheckField, 27, 5, 30, 223, 1, 0, // Skip to: 527 +/* 48 */ MCD_OPC_CheckField, 5, 6, 0, 216, 1, 0, // Skip to: 527 +/* 55 */ MCD_OPC_Decode, 238, 8, 15, // Opcode: BimmX16 +/* 59 */ MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 87 +/* 64 */ MCD_OPC_CheckPredicate, 0, 202, 1, 0, // Skip to: 527 +/* 69 */ MCD_OPC_CheckField, 27, 5, 30, 195, 1, 0, // Skip to: 527 +/* 76 */ MCD_OPC_CheckField, 5, 3, 0, 188, 1, 0, // Skip to: 527 +/* 83 */ MCD_OPC_Decode, 236, 8, 16, // Opcode: BeqzRxImmX16 +/* 87 */ MCD_OPC_FilterValue, 5, 23, 0, 0, // Skip to: 115 +/* 92 */ MCD_OPC_CheckPredicate, 0, 174, 1, 0, // Skip to: 527 +/* 97 */ MCD_OPC_CheckField, 27, 5, 30, 167, 1, 0, // Skip to: 527 +/* 104 */ MCD_OPC_CheckField, 5, 3, 0, 160, 1, 0, // Skip to: 527 +/* 111 */ MCD_OPC_Decode, 240, 8, 16, // Opcode: BnezRxImmX16 +/* 115 */ MCD_OPC_FilterValue, 6, 106, 0, 0, // Skip to: 226 +/* 120 */ MCD_OPC_ExtractField, 27, 5, // Inst{31-27} ... +/* 123 */ MCD_OPC_FilterValue, 30, 143, 1, 0, // Skip to: 527 +/* 128 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 131 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 181 +/* 136 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 139 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 153 +/* 144 */ MCD_OPC_CheckPredicate, 0, 32, 0, 0, // Skip to: 181 +/* 149 */ MCD_OPC_Decode, 192, 23, 17, // Opcode: SllX16 +/* 153 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 167 +/* 158 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 181 +/* 163 */ MCD_OPC_Decode, 202, 23, 17, // Opcode: SrlX16 +/* 167 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 181 +/* 172 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 181 +/* 177 */ MCD_OPC_Decode, 200, 23, 17, // Opcode: SraX16 +/* 181 */ MCD_OPC_ExtractField, 5, 6, // Inst{10-5} ... +/* 184 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 198 +/* 189 */ MCD_OPC_CheckPredicate, 0, 77, 1, 0, // Skip to: 527 +/* 194 */ MCD_OPC_Decode, 243, 8, 18, // Opcode: BteqzX16 +/* 198 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 212 +/* 203 */ MCD_OPC_CheckPredicate, 0, 63, 1, 0, // Skip to: 527 +/* 208 */ MCD_OPC_Decode, 245, 8, 18, // Opcode: BtnezX16 +/* 212 */ MCD_OPC_FilterValue, 24, 54, 1, 0, // Skip to: 527 +/* 217 */ MCD_OPC_CheckPredicate, 0, 49, 1, 0, // Skip to: 527 +/* 222 */ MCD_OPC_Decode, 142, 7, 18, // Opcode: AddiuSpImmX16 +/* 226 */ MCD_OPC_FilterValue, 8, 23, 0, 0, // Skip to: 254 +/* 231 */ MCD_OPC_CheckPredicate, 0, 35, 1, 0, // Skip to: 527 +/* 236 */ MCD_OPC_CheckField, 27, 5, 30, 28, 1, 0, // Skip to: 527 +/* 243 */ MCD_OPC_CheckField, 4, 1, 0, 21, 1, 0, // Skip to: 527 +/* 250 */ MCD_OPC_Decode, 140, 7, 19, // Opcode: AddiuRxRyOffMemX16 +/* 254 */ MCD_OPC_FilterValue, 9, 23, 0, 0, // Skip to: 282 +/* 259 */ MCD_OPC_CheckPredicate, 0, 7, 1, 0, // Skip to: 527 +/* 264 */ MCD_OPC_CheckField, 27, 5, 30, 0, 1, 0, // Skip to: 527 +/* 271 */ MCD_OPC_CheckField, 5, 3, 0, 249, 0, 0, // Skip to: 527 +/* 278 */ MCD_OPC_Decode, 136, 7, 14, // Opcode: AddiuRxImmX16 +/* 282 */ MCD_OPC_FilterValue, 10, 23, 0, 0, // Skip to: 310 +/* 287 */ MCD_OPC_CheckPredicate, 0, 235, 0, 0, // Skip to: 527 +/* 292 */ MCD_OPC_CheckField, 27, 5, 30, 228, 0, 0, // Skip to: 527 +/* 299 */ MCD_OPC_CheckField, 5, 3, 0, 221, 0, 0, // Skip to: 527 +/* 306 */ MCD_OPC_Decode, 196, 23, 14, // Opcode: SltiRxImmX16 +/* 310 */ MCD_OPC_FilterValue, 11, 23, 0, 0, // Skip to: 338 +/* 315 */ MCD_OPC_CheckPredicate, 0, 207, 0, 0, // Skip to: 527 +/* 320 */ MCD_OPC_CheckField, 27, 5, 30, 200, 0, 0, // Skip to: 527 +/* 327 */ MCD_OPC_CheckField, 5, 3, 0, 193, 0, 0, // Skip to: 527 +/* 334 */ MCD_OPC_Decode, 198, 23, 14, // Opcode: SltiuRxImmX16 +/* 338 */ MCD_OPC_FilterValue, 13, 23, 0, 0, // Skip to: 366 +/* 343 */ MCD_OPC_CheckPredicate, 0, 179, 0, 0, // Skip to: 527 +/* 348 */ MCD_OPC_CheckField, 27, 5, 30, 172, 0, 0, // Skip to: 527 +/* 355 */ MCD_OPC_CheckField, 5, 3, 0, 165, 0, 0, // Skip to: 527 +/* 362 */ MCD_OPC_Decode, 190, 16, 14, // Opcode: LiRxImmX16 +/* 366 */ MCD_OPC_FilterValue, 14, 23, 0, 0, // Skip to: 394 +/* 371 */ MCD_OPC_CheckPredicate, 0, 151, 0, 0, // Skip to: 527 +/* 376 */ MCD_OPC_CheckField, 27, 5, 30, 144, 0, 0, // Skip to: 527 +/* 383 */ MCD_OPC_CheckField, 5, 3, 0, 137, 0, 0, // Skip to: 527 +/* 390 */ MCD_OPC_Decode, 190, 11, 14, // Opcode: CmpiRxImmX16 +/* 394 */ MCD_OPC_FilterValue, 18, 16, 0, 0, // Skip to: 415 +/* 399 */ MCD_OPC_CheckPredicate, 0, 123, 0, 0, // Skip to: 527 +/* 404 */ MCD_OPC_CheckField, 27, 5, 30, 116, 0, 0, // Skip to: 527 +/* 411 */ MCD_OPC_Decode, 194, 16, 19, // Opcode: LwRxSpImmX16 +/* 415 */ MCD_OPC_FilterValue, 22, 23, 0, 0, // Skip to: 443 +/* 420 */ MCD_OPC_CheckPredicate, 0, 102, 0, 0, // Skip to: 527 +/* 425 */ MCD_OPC_CheckField, 27, 5, 30, 95, 0, 0, // Skip to: 527 +/* 432 */ MCD_OPC_CheckField, 5, 3, 0, 88, 0, 0, // Skip to: 527 +/* 439 */ MCD_OPC_Decode, 192, 16, 20, // Opcode: LwRxPcTcpX16 +/* 443 */ MCD_OPC_FilterValue, 24, 16, 0, 0, // Skip to: 464 +/* 448 */ MCD_OPC_CheckPredicate, 0, 74, 0, 0, // Skip to: 527 +/* 453 */ MCD_OPC_CheckField, 27, 5, 30, 67, 0, 0, // Skip to: 527 +/* 460 */ MCD_OPC_Decode, 188, 23, 19, // Opcode: SbRxRyOffMemX16 +/* 464 */ MCD_OPC_FilterValue, 25, 16, 0, 0, // Skip to: 485 +/* 469 */ MCD_OPC_CheckPredicate, 0, 53, 0, 0, // Skip to: 527 +/* 474 */ MCD_OPC_CheckField, 27, 5, 30, 46, 0, 0, // Skip to: 527 +/* 481 */ MCD_OPC_Decode, 191, 23, 19, // Opcode: ShRxRyOffMemX16 +/* 485 */ MCD_OPC_FilterValue, 26, 16, 0, 0, // Skip to: 506 +/* 490 */ MCD_OPC_CheckPredicate, 0, 32, 0, 0, // Skip to: 527 +/* 495 */ MCD_OPC_CheckField, 27, 5, 30, 25, 0, 0, // Skip to: 527 +/* 502 */ MCD_OPC_Decode, 206, 23, 19, // Opcode: SwRxSpImmX16 +/* 506 */ MCD_OPC_FilterValue, 27, 16, 0, 0, // Skip to: 527 +/* 511 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 527 +/* 516 */ MCD_OPC_CheckField, 27, 5, 30, 4, 0, 0, // Skip to: 527 +/* 523 */ MCD_OPC_Decode, 205, 23, 19, // Opcode: SwRxRyOffMemX16 +/* 527 */ MCD_OPC_Fail, + 0 +}; + static const uint8_t DecoderTableCOP3_32[] = { /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 15 -/* 7 */ MCD_OPC_CheckPredicate, 1, 40, 0, // Skip to: 51 -/* 11 */ MCD_OPC_Decode, 220, 7, 10, // Opcode: LWC3 -/* 15 */ MCD_OPC_FilterValue, 55, 8, 0, // Skip to: 27 -/* 19 */ MCD_OPC_CheckPredicate, 2, 28, 0, // Skip to: 51 -/* 23 */ MCD_OPC_Decode, 167, 7, 10, // Opcode: LDC3 -/* 27 */ MCD_OPC_FilterValue, 59, 8, 0, // Skip to: 39 -/* 31 */ MCD_OPC_CheckPredicate, 1, 16, 0, // Skip to: 51 -/* 35 */ MCD_OPC_Decode, 242, 12, 10, // Opcode: SWC3 -/* 39 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 51 -/* 43 */ MCD_OPC_CheckPredicate, 2, 4, 0, // Skip to: 51 -/* 47 */ MCD_OPC_Decode, 161, 11, 10, // Opcode: SDC3 -/* 51 */ MCD_OPC_Fail, +/* 3 */ MCD_OPC_FilterValue, 51, 9, 0, 0, // Skip to: 17 +/* 8 */ MCD_OPC_CheckPredicate, 1, 46, 0, 0, // Skip to: 59 +/* 13 */ MCD_OPC_Decode, 141, 16, 21, // Opcode: LWC3 +/* 17 */ MCD_OPC_FilterValue, 55, 9, 0, 0, // Skip to: 31 +/* 22 */ MCD_OPC_CheckPredicate, 2, 32, 0, 0, // Skip to: 59 +/* 27 */ MCD_OPC_Decode, 188, 15, 21, // Opcode: LDC3 +/* 31 */ MCD_OPC_FilterValue, 59, 9, 0, 0, // Skip to: 45 +/* 36 */ MCD_OPC_CheckPredicate, 1, 18, 0, 0, // Skip to: 59 +/* 41 */ MCD_OPC_Decode, 139, 23, 21, // Opcode: SWC3 +/* 45 */ MCD_OPC_FilterValue, 63, 9, 0, 0, // Skip to: 59 +/* 50 */ MCD_OPC_CheckPredicate, 2, 4, 0, 0, // Skip to: 59 +/* 55 */ MCD_OPC_Decode, 235, 20, 21, // Opcode: SDC3 +/* 59 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableCnMips32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 18, 31, 0, 0, // Skip to: 39 +/* 8 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 11 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 25 +/* 16 */ MCD_OPC_CheckPredicate, 3, 239, 1, 0, // Skip to: 516 +/* 21 */ MCD_OPC_Decode, 240, 11, 22, // Opcode: DMFC2_OCTEON +/* 25 */ MCD_OPC_FilterValue, 5, 230, 1, 0, // Skip to: 516 +/* 30 */ MCD_OPC_CheckPredicate, 3, 225, 1, 0, // Skip to: 516 +/* 35 */ MCD_OPC_Decode, 248, 11, 22, // Opcode: DMTC2_OCTEON +/* 39 */ MCD_OPC_FilterValue, 28, 160, 1, 0, // Skip to: 460 +/* 44 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 47 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 68 +/* 52 */ MCD_OPC_CheckPredicate, 3, 203, 1, 0, // Skip to: 516 +/* 57 */ MCD_OPC_CheckField, 6, 5, 0, 196, 1, 0, // Skip to: 516 +/* 64 */ MCD_OPC_Decode, 253, 11, 23, // Opcode: DMUL +/* 68 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 89 +/* 73 */ MCD_OPC_CheckPredicate, 3, 182, 1, 0, // Skip to: 516 +/* 78 */ MCD_OPC_CheckField, 6, 15, 0, 175, 1, 0, // Skip to: 516 +/* 85 */ MCD_OPC_Decode, 191, 18, 24, // Opcode: MTM0 +/* 89 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 110 +/* 94 */ MCD_OPC_CheckPredicate, 3, 161, 1, 0, // Skip to: 516 +/* 99 */ MCD_OPC_CheckField, 6, 15, 0, 154, 1, 0, // Skip to: 516 +/* 106 */ MCD_OPC_Decode, 194, 18, 24, // Opcode: MTP0 +/* 110 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 131 +/* 115 */ MCD_OPC_CheckPredicate, 3, 140, 1, 0, // Skip to: 516 +/* 120 */ MCD_OPC_CheckField, 6, 15, 0, 133, 1, 0, // Skip to: 516 +/* 127 */ MCD_OPC_Decode, 195, 18, 24, // Opcode: MTP1 +/* 131 */ MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 152 +/* 136 */ MCD_OPC_CheckPredicate, 3, 119, 1, 0, // Skip to: 516 +/* 141 */ MCD_OPC_CheckField, 6, 15, 0, 112, 1, 0, // Skip to: 516 +/* 148 */ MCD_OPC_Decode, 196, 18, 24, // Opcode: MTP2 +/* 152 */ MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 173 +/* 157 */ MCD_OPC_CheckPredicate, 3, 98, 1, 0, // Skip to: 516 +/* 162 */ MCD_OPC_CheckField, 6, 15, 0, 91, 1, 0, // Skip to: 516 +/* 169 */ MCD_OPC_Decode, 192, 18, 24, // Opcode: MTM1 +/* 173 */ MCD_OPC_FilterValue, 13, 16, 0, 0, // Skip to: 194 +/* 178 */ MCD_OPC_CheckPredicate, 3, 77, 1, 0, // Skip to: 516 +/* 183 */ MCD_OPC_CheckField, 6, 15, 0, 70, 1, 0, // Skip to: 516 +/* 190 */ MCD_OPC_Decode, 193, 18, 24, // Opcode: MTM2 +/* 194 */ MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 215 +/* 199 */ MCD_OPC_CheckPredicate, 3, 56, 1, 0, // Skip to: 516 +/* 204 */ MCD_OPC_CheckField, 6, 5, 0, 49, 1, 0, // Skip to: 516 +/* 211 */ MCD_OPC_Decode, 156, 24, 23, // Opcode: VMULU +/* 215 */ MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 236 +/* 220 */ MCD_OPC_CheckPredicate, 3, 35, 1, 0, // Skip to: 516 +/* 225 */ MCD_OPC_CheckField, 6, 5, 0, 28, 1, 0, // Skip to: 516 +/* 232 */ MCD_OPC_Decode, 155, 24, 23, // Opcode: VMM0 +/* 236 */ MCD_OPC_FilterValue, 17, 16, 0, 0, // Skip to: 257 +/* 241 */ MCD_OPC_CheckPredicate, 3, 14, 1, 0, // Skip to: 516 +/* 246 */ MCD_OPC_CheckField, 6, 5, 0, 7, 1, 0, // Skip to: 516 +/* 253 */ MCD_OPC_Decode, 154, 24, 23, // Opcode: V3MULU +/* 257 */ MCD_OPC_FilterValue, 40, 16, 0, 0, // Skip to: 278 +/* 262 */ MCD_OPC_CheckPredicate, 3, 249, 0, 0, // Skip to: 516 +/* 267 */ MCD_OPC_CheckField, 6, 5, 0, 242, 0, 0, // Skip to: 516 +/* 274 */ MCD_OPC_Decode, 146, 7, 23, // Opcode: BADDu +/* 278 */ MCD_OPC_FilterValue, 42, 16, 0, 0, // Skip to: 299 +/* 283 */ MCD_OPC_CheckPredicate, 3, 228, 0, 0, // Skip to: 516 +/* 288 */ MCD_OPC_CheckField, 6, 5, 0, 221, 0, 0, // Skip to: 516 +/* 295 */ MCD_OPC_Decode, 140, 21, 23, // Opcode: SEQ +/* 299 */ MCD_OPC_FilterValue, 43, 16, 0, 0, // Skip to: 320 +/* 304 */ MCD_OPC_CheckPredicate, 3, 207, 0, 0, // Skip to: 516 +/* 309 */ MCD_OPC_CheckField, 6, 5, 0, 200, 0, 0, // Skip to: 516 +/* 316 */ MCD_OPC_Decode, 255, 21, 23, // Opcode: SNE +/* 320 */ MCD_OPC_FilterValue, 44, 23, 0, 0, // Skip to: 348 +/* 325 */ MCD_OPC_CheckPredicate, 3, 186, 0, 0, // Skip to: 516 +/* 330 */ MCD_OPC_CheckField, 16, 5, 0, 179, 0, 0, // Skip to: 516 +/* 337 */ MCD_OPC_CheckField, 6, 5, 0, 172, 0, 0, // Skip to: 516 +/* 344 */ MCD_OPC_Decode, 203, 19, 25, // Opcode: POP +/* 348 */ MCD_OPC_FilterValue, 45, 23, 0, 0, // Skip to: 376 +/* 353 */ MCD_OPC_CheckPredicate, 3, 158, 0, 0, // Skip to: 516 +/* 358 */ MCD_OPC_CheckField, 16, 5, 0, 151, 0, 0, // Skip to: 516 +/* 365 */ MCD_OPC_CheckField, 6, 5, 0, 144, 0, 0, // Skip to: 516 +/* 372 */ MCD_OPC_Decode, 158, 12, 26, // Opcode: DPOP +/* 376 */ MCD_OPC_FilterValue, 46, 9, 0, 0, // Skip to: 390 +/* 381 */ MCD_OPC_CheckPredicate, 3, 130, 0, 0, // Skip to: 516 +/* 386 */ MCD_OPC_Decode, 142, 21, 27, // Opcode: SEQi +/* 390 */ MCD_OPC_FilterValue, 47, 9, 0, 0, // Skip to: 404 +/* 395 */ MCD_OPC_CheckPredicate, 3, 116, 0, 0, // Skip to: 516 +/* 400 */ MCD_OPC_Decode, 128, 22, 27, // Opcode: SNEi +/* 404 */ MCD_OPC_FilterValue, 50, 9, 0, 0, // Skip to: 418 +/* 409 */ MCD_OPC_CheckPredicate, 4, 102, 0, 0, // Skip to: 516 +/* 414 */ MCD_OPC_Decode, 148, 9, 28, // Opcode: CINS +/* 418 */ MCD_OPC_FilterValue, 51, 9, 0, 0, // Skip to: 432 +/* 423 */ MCD_OPC_CheckPredicate, 4, 88, 0, 0, // Skip to: 516 +/* 428 */ MCD_OPC_Decode, 149, 9, 28, // Opcode: CINS32 +/* 432 */ MCD_OPC_FilterValue, 58, 9, 0, 0, // Skip to: 446 +/* 437 */ MCD_OPC_CheckPredicate, 4, 74, 0, 0, // Skip to: 516 +/* 442 */ MCD_OPC_Decode, 252, 12, 28, // Opcode: EXTS +/* 446 */ MCD_OPC_FilterValue, 59, 65, 0, 0, // Skip to: 516 +/* 451 */ MCD_OPC_CheckPredicate, 4, 60, 0, 0, // Skip to: 516 +/* 456 */ MCD_OPC_Decode, 253, 12, 28, // Opcode: EXTS32 +/* 460 */ MCD_OPC_FilterValue, 50, 9, 0, 0, // Skip to: 474 +/* 465 */ MCD_OPC_CheckPredicate, 3, 46, 0, 0, // Skip to: 516 +/* 470 */ MCD_OPC_Decode, 156, 7, 29, // Opcode: BBIT0 +/* 474 */ MCD_OPC_FilterValue, 54, 9, 0, 0, // Skip to: 488 +/* 479 */ MCD_OPC_CheckPredicate, 3, 32, 0, 0, // Skip to: 516 +/* 484 */ MCD_OPC_Decode, 157, 7, 29, // Opcode: BBIT032 +/* 488 */ MCD_OPC_FilterValue, 58, 9, 0, 0, // Skip to: 502 +/* 493 */ MCD_OPC_CheckPredicate, 3, 18, 0, 0, // Skip to: 516 +/* 498 */ MCD_OPC_Decode, 158, 7, 29, // Opcode: BBIT1 +/* 502 */ MCD_OPC_FilterValue, 62, 9, 0, 0, // Skip to: 516 +/* 507 */ MCD_OPC_CheckPredicate, 3, 4, 0, 0, // Skip to: 516 +/* 512 */ MCD_OPC_Decode, 159, 7, 29, // Opcode: BBIT132 +/* 516 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableCnMipsP32[] = { +/* 0 */ MCD_OPC_ExtractField, 0, 16, // Inst{15-0} ... +/* 3 */ MCD_OPC_FilterValue, 24, 16, 0, 0, // Skip to: 24 +/* 8 */ MCD_OPC_CheckPredicate, 5, 32, 0, 0, // Skip to: 45 +/* 13 */ MCD_OPC_CheckField, 26, 6, 28, 25, 0, 0, // Skip to: 45 +/* 20 */ MCD_OPC_Decode, 181, 20, 30, // Opcode: SAA +/* 24 */ MCD_OPC_FilterValue, 25, 16, 0, 0, // Skip to: 45 +/* 29 */ MCD_OPC_CheckPredicate, 5, 11, 0, 0, // Skip to: 45 +/* 34 */ MCD_OPC_CheckField, 26, 6, 28, 4, 0, 0, // Skip to: 45 +/* 41 */ MCD_OPC_Decode, 182, 20, 30, // Opcode: SAAD +/* 45 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableMicroMips16[] = { /* 0 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 3 */ MCD_OPC_FilterValue, 1, 26, 0, // Skip to: 33 -/* 7 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 10 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 21 -/* 14 */ MCD_OPC_CheckPredicate, 3, 19, 2, // Skip to: 549 -/* 18 */ MCD_OPC_Decode, 52, 11, // Opcode: ADDU16_MM -/* 21 */ MCD_OPC_FilterValue, 1, 12, 2, // Skip to: 549 -/* 25 */ MCD_OPC_CheckPredicate, 3, 8, 2, // Skip to: 549 -/* 29 */ MCD_OPC_Decode, 214, 12, 11, // Opcode: SUBU16_MM -/* 33 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 45 -/* 37 */ MCD_OPC_CheckPredicate, 3, 252, 1, // Skip to: 549 -/* 41 */ MCD_OPC_Decode, 155, 7, 12, // Opcode: LBU16_MM -/* 45 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 57 -/* 49 */ MCD_OPC_CheckPredicate, 3, 240, 1, // Skip to: 549 -/* 53 */ MCD_OPC_Decode, 233, 8, 13, // Opcode: MOVE16_MM -/* 57 */ MCD_OPC_FilterValue, 9, 27, 0, // Skip to: 88 -/* 61 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 64 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 76 -/* 68 */ MCD_OPC_CheckPredicate, 3, 221, 1, // Skip to: 549 -/* 72 */ MCD_OPC_Decode, 226, 11, 14, // Opcode: SLL16_MM -/* 76 */ MCD_OPC_FilterValue, 1, 213, 1, // Skip to: 549 -/* 80 */ MCD_OPC_CheckPredicate, 3, 209, 1, // Skip to: 549 -/* 84 */ MCD_OPC_Decode, 160, 12, 14, // Opcode: SRL16_MM -/* 88 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 100 -/* 92 */ MCD_OPC_CheckPredicate, 3, 197, 1, // Skip to: 549 -/* 96 */ MCD_OPC_Decode, 186, 7, 12, // Opcode: LHU16_MM -/* 100 */ MCD_OPC_FilterValue, 11, 7, 0, // Skip to: 111 -/* 104 */ MCD_OPC_CheckPredicate, 3, 185, 1, // Skip to: 549 -/* 108 */ MCD_OPC_Decode, 86, 15, // Opcode: ANDI16_MM -/* 111 */ MCD_OPC_FilterValue, 17, 226, 0, // Skip to: 341 -/* 115 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... -/* 118 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 130 -/* 122 */ MCD_OPC_CheckPredicate, 3, 167, 1, // Skip to: 549 -/* 126 */ MCD_OPC_Decode, 130, 10, 16, // Opcode: NOT16_MM -/* 130 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 142 -/* 134 */ MCD_OPC_CheckPredicate, 3, 155, 1, // Skip to: 549 -/* 138 */ MCD_OPC_Decode, 237, 13, 17, // Opcode: XOR16_MM -/* 142 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 153 -/* 146 */ MCD_OPC_CheckPredicate, 3, 143, 1, // Skip to: 549 -/* 150 */ MCD_OPC_Decode, 84, 17, // Opcode: AND16_MM -/* 153 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 165 -/* 157 */ MCD_OPC_CheckPredicate, 3, 132, 1, // Skip to: 549 -/* 161 */ MCD_OPC_Decode, 134, 10, 17, // Opcode: OR16_MM -/* 165 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 177 -/* 169 */ MCD_OPC_CheckPredicate, 3, 120, 1, // Skip to: 549 -/* 173 */ MCD_OPC_Decode, 225, 7, 18, // Opcode: LWM16_MM -/* 177 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 189 -/* 181 */ MCD_OPC_CheckPredicate, 3, 108, 1, // Skip to: 549 -/* 185 */ MCD_OPC_Decode, 246, 12, 18, // Opcode: SWM16_MM -/* 189 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 220 -/* 193 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 196 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 208 -/* 200 */ MCD_OPC_CheckPredicate, 3, 89, 1, // Skip to: 549 -/* 204 */ MCD_OPC_Decode, 137, 7, 19, // Opcode: JR16_MM -/* 208 */ MCD_OPC_FilterValue, 1, 81, 1, // Skip to: 549 -/* 212 */ MCD_OPC_CheckPredicate, 3, 77, 1, // Skip to: 549 -/* 216 */ MCD_OPC_Decode, 140, 7, 19, // Opcode: JRC16_MM -/* 220 */ MCD_OPC_FilterValue, 7, 27, 0, // Skip to: 251 -/* 224 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 227 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 239 -/* 231 */ MCD_OPC_CheckPredicate, 3, 58, 1, // Skip to: 549 -/* 235 */ MCD_OPC_Decode, 250, 6, 19, // Opcode: JALR16_MM -/* 239 */ MCD_OPC_FilterValue, 1, 50, 1, // Skip to: 549 -/* 243 */ MCD_OPC_CheckPredicate, 3, 46, 1, // Skip to: 549 -/* 247 */ MCD_OPC_Decode, 254, 6, 19, // Opcode: JALRS16_MM -/* 251 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 269 -/* 255 */ MCD_OPC_CheckPredicate, 3, 34, 1, // Skip to: 549 -/* 259 */ MCD_OPC_CheckField, 5, 1, 0, 28, 1, // Skip to: 549 -/* 265 */ MCD_OPC_Decode, 187, 8, 19, // Opcode: MFHI16_MM -/* 269 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 287 -/* 273 */ MCD_OPC_CheckPredicate, 3, 16, 1, // Skip to: 549 -/* 277 */ MCD_OPC_CheckField, 5, 1, 0, 10, 1, // Skip to: 549 -/* 283 */ MCD_OPC_Decode, 192, 8, 19, // Opcode: MFLO16_MM -/* 287 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 305 -/* 291 */ MCD_OPC_CheckPredicate, 3, 254, 0, // Skip to: 549 -/* 295 */ MCD_OPC_CheckField, 4, 2, 0, 248, 0, // Skip to: 549 -/* 301 */ MCD_OPC_Decode, 172, 2, 20, // Opcode: BREAK16_MM -/* 305 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 323 -/* 309 */ MCD_OPC_CheckPredicate, 3, 236, 0, // Skip to: 549 -/* 313 */ MCD_OPC_CheckField, 4, 2, 0, 230, 0, // Skip to: 549 -/* 319 */ MCD_OPC_Decode, 153, 11, 20, // Opcode: SDBBP16_MM -/* 323 */ MCD_OPC_FilterValue, 12, 222, 0, // Skip to: 549 -/* 327 */ MCD_OPC_CheckPredicate, 3, 218, 0, // Skip to: 549 -/* 331 */ MCD_OPC_CheckField, 5, 1, 0, 212, 0, // Skip to: 549 -/* 337 */ MCD_OPC_Decode, 139, 7, 21, // Opcode: JRADDIUSP -/* 341 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 353 -/* 345 */ MCD_OPC_CheckPredicate, 3, 200, 0, // Skip to: 549 -/* 349 */ MCD_OPC_Decode, 233, 7, 22, // Opcode: LWSP_MM -/* 353 */ MCD_OPC_FilterValue, 19, 25, 0, // Skip to: 382 -/* 357 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 360 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 371 -/* 364 */ MCD_OPC_CheckPredicate, 3, 181, 0, // Skip to: 549 -/* 368 */ MCD_OPC_Decode, 30, 23, // Opcode: ADDIUS5_MM -/* 371 */ MCD_OPC_FilterValue, 1, 174, 0, // Skip to: 549 -/* 375 */ MCD_OPC_CheckPredicate, 3, 170, 0, // Skip to: 549 -/* 379 */ MCD_OPC_Decode, 31, 24, // Opcode: ADDIUSP_MM -/* 382 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 394 -/* 386 */ MCD_OPC_CheckPredicate, 3, 159, 0, // Skip to: 549 -/* 390 */ MCD_OPC_Decode, 221, 7, 25, // Opcode: LWGP_MM -/* 394 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 406 -/* 398 */ MCD_OPC_CheckPredicate, 3, 147, 0, // Skip to: 549 -/* 402 */ MCD_OPC_Decode, 214, 7, 12, // Opcode: LW16_MM -/* 406 */ MCD_OPC_FilterValue, 27, 25, 0, // Skip to: 435 -/* 410 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 413 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 424 -/* 417 */ MCD_OPC_CheckPredicate, 3, 128, 0, // Skip to: 549 -/* 421 */ MCD_OPC_Decode, 29, 26, // Opcode: ADDIUR2_MM -/* 424 */ MCD_OPC_FilterValue, 1, 121, 0, // Skip to: 549 -/* 428 */ MCD_OPC_CheckPredicate, 3, 117, 0, // Skip to: 549 -/* 432 */ MCD_OPC_Decode, 28, 27, // Opcode: ADDIUR1SP_MM -/* 435 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 453 -/* 439 */ MCD_OPC_CheckPredicate, 3, 106, 0, // Skip to: 549 -/* 443 */ MCD_OPC_CheckField, 0, 1, 0, 100, 0, // Skip to: 549 -/* 449 */ MCD_OPC_Decode, 234, 8, 28, // Opcode: MOVEP_MM -/* 453 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 465 -/* 457 */ MCD_OPC_CheckPredicate, 3, 88, 0, // Skip to: 549 -/* 461 */ MCD_OPC_Decode, 143, 11, 12, // Opcode: SB16_MM -/* 465 */ MCD_OPC_FilterValue, 35, 8, 0, // Skip to: 477 -/* 469 */ MCD_OPC_CheckPredicate, 3, 76, 0, // Skip to: 549 -/* 473 */ MCD_OPC_Decode, 210, 1, 29, // Opcode: BEQZ16_MM -/* 477 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 489 -/* 481 */ MCD_OPC_CheckPredicate, 3, 64, 0, // Skip to: 549 -/* 485 */ MCD_OPC_Decode, 187, 11, 12, // Opcode: SH16_MM -/* 489 */ MCD_OPC_FilterValue, 43, 8, 0, // Skip to: 501 -/* 493 */ MCD_OPC_CheckPredicate, 3, 52, 0, // Skip to: 549 -/* 497 */ MCD_OPC_Decode, 157, 2, 29, // Opcode: BNEZ16_MM -/* 501 */ MCD_OPC_FilterValue, 50, 8, 0, // Skip to: 513 -/* 505 */ MCD_OPC_CheckPredicate, 3, 40, 0, // Skip to: 549 -/* 509 */ MCD_OPC_Decode, 253, 12, 22, // Opcode: SWSP_MM -/* 513 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 525 -/* 517 */ MCD_OPC_CheckPredicate, 4, 28, 0, // Skip to: 549 -/* 521 */ MCD_OPC_Decode, 165, 1, 30, // Opcode: B16_MM -/* 525 */ MCD_OPC_FilterValue, 58, 8, 0, // Skip to: 537 -/* 529 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 549 -/* 533 */ MCD_OPC_Decode, 236, 12, 12, // Opcode: SW16_MM -/* 537 */ MCD_OPC_FilterValue, 59, 8, 0, // Skip to: 549 -/* 541 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 549 -/* 545 */ MCD_OPC_Decode, 192, 7, 31, // Opcode: LI16_MM -/* 549 */ MCD_OPC_Fail, +/* 3 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 39 +/* 8 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 11 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 25 +/* 16 */ MCD_OPC_CheckPredicate, 6, 114, 2, 0, // Skip to: 647 +/* 21 */ MCD_OPC_Decode, 170, 6, 31, // Opcode: ADDU16_MM +/* 25 */ MCD_OPC_FilterValue, 1, 105, 2, 0, // Skip to: 647 +/* 30 */ MCD_OPC_CheckPredicate, 6, 100, 2, 0, // Skip to: 647 +/* 35 */ MCD_OPC_Decode, 223, 22, 31, // Opcode: SUBU16_MM +/* 39 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 53 +/* 44 */ MCD_OPC_CheckPredicate, 7, 86, 2, 0, // Skip to: 647 +/* 49 */ MCD_OPC_Decode, 160, 15, 32, // Opcode: LBU16_MM +/* 53 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 67 +/* 58 */ MCD_OPC_CheckPredicate, 6, 72, 2, 0, // Skip to: 647 +/* 63 */ MCD_OPC_Decode, 208, 17, 33, // Opcode: MOVE16_MM +/* 67 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 103 +/* 72 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 75 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 89 +/* 80 */ MCD_OPC_CheckPredicate, 6, 50, 2, 0, // Skip to: 647 +/* 85 */ MCD_OPC_Decode, 220, 21, 34, // Opcode: SLL16_MM +/* 89 */ MCD_OPC_FilterValue, 1, 41, 2, 0, // Skip to: 647 +/* 94 */ MCD_OPC_CheckPredicate, 6, 36, 2, 0, // Skip to: 647 +/* 99 */ MCD_OPC_Decode, 161, 22, 34, // Opcode: SRL16_MM +/* 103 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 117 +/* 108 */ MCD_OPC_CheckPredicate, 7, 22, 2, 0, // Skip to: 647 +/* 113 */ MCD_OPC_Decode, 212, 15, 32, // Opcode: LHU16_MM +/* 117 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 131 +/* 122 */ MCD_OPC_CheckPredicate, 6, 8, 2, 0, // Skip to: 647 +/* 127 */ MCD_OPC_Decode, 221, 6, 35, // Opcode: ANDI16_MM +/* 131 */ MCD_OPC_FilterValue, 17, 8, 1, 0, // Skip to: 400 +/* 136 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 139 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 153 +/* 144 */ MCD_OPC_CheckPredicate, 6, 242, 1, 0, // Skip to: 647 +/* 149 */ MCD_OPC_Decode, 158, 19, 36, // Opcode: NOT16_MM +/* 153 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 167 +/* 158 */ MCD_OPC_CheckPredicate, 6, 228, 1, 0, // Skip to: 647 +/* 163 */ MCD_OPC_Decode, 173, 24, 37, // Opcode: XOR16_MM +/* 167 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 181 +/* 172 */ MCD_OPC_CheckPredicate, 6, 214, 1, 0, // Skip to: 647 +/* 177 */ MCD_OPC_Decode, 217, 6, 37, // Opcode: AND16_MM +/* 181 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 195 +/* 186 */ MCD_OPC_CheckPredicate, 6, 200, 1, 0, // Skip to: 647 +/* 191 */ MCD_OPC_Decode, 164, 19, 37, // Opcode: OR16_MM +/* 195 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 209 +/* 200 */ MCD_OPC_CheckPredicate, 6, 186, 1, 0, // Skip to: 647 +/* 205 */ MCD_OPC_Decode, 154, 16, 38, // Opcode: LWM16_MM +/* 209 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 223 +/* 214 */ MCD_OPC_CheckPredicate, 6, 172, 1, 0, // Skip to: 647 +/* 219 */ MCD_OPC_Decode, 151, 23, 38, // Opcode: SWM16_MM +/* 223 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 259 +/* 228 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 231 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 245 +/* 236 */ MCD_OPC_CheckPredicate, 6, 150, 1, 0, // Skip to: 647 +/* 241 */ MCD_OPC_Decode, 133, 15, 39, // Opcode: JR16_MM +/* 245 */ MCD_OPC_FilterValue, 1, 141, 1, 0, // Skip to: 647 +/* 250 */ MCD_OPC_CheckPredicate, 6, 136, 1, 0, // Skip to: 647 +/* 255 */ MCD_OPC_Decode, 136, 15, 39, // Opcode: JRC16_MM +/* 259 */ MCD_OPC_FilterValue, 7, 31, 0, 0, // Skip to: 295 +/* 264 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 267 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 281 +/* 272 */ MCD_OPC_CheckPredicate, 6, 114, 1, 0, // Skip to: 647 +/* 277 */ MCD_OPC_Decode, 237, 14, 39, // Opcode: JALR16_MM +/* 281 */ MCD_OPC_FilterValue, 1, 105, 1, 0, // Skip to: 647 +/* 286 */ MCD_OPC_CheckPredicate, 6, 100, 1, 0, // Skip to: 647 +/* 291 */ MCD_OPC_Decode, 245, 14, 39, // Opcode: JALRS16_MM +/* 295 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 316 +/* 300 */ MCD_OPC_CheckPredicate, 6, 86, 1, 0, // Skip to: 647 +/* 305 */ MCD_OPC_CheckField, 5, 1, 0, 79, 1, 0, // Skip to: 647 +/* 312 */ MCD_OPC_Decode, 151, 17, 39, // Opcode: MFHI16_MM +/* 316 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 337 +/* 321 */ MCD_OPC_CheckPredicate, 6, 65, 1, 0, // Skip to: 647 +/* 326 */ MCD_OPC_CheckField, 5, 1, 0, 58, 1, 0, // Skip to: 647 +/* 333 */ MCD_OPC_Decode, 157, 17, 39, // Opcode: MFLO16_MM +/* 337 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 358 +/* 342 */ MCD_OPC_CheckPredicate, 6, 44, 1, 0, // Skip to: 647 +/* 347 */ MCD_OPC_CheckField, 4, 2, 0, 37, 1, 0, // Skip to: 647 +/* 354 */ MCD_OPC_Decode, 212, 8, 40, // Opcode: BREAK16_MM +/* 358 */ MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 379 +/* 363 */ MCD_OPC_CheckPredicate, 6, 23, 1, 0, // Skip to: 647 +/* 368 */ MCD_OPC_CheckField, 4, 2, 0, 16, 1, 0, // Skip to: 647 +/* 375 */ MCD_OPC_Decode, 220, 20, 40, // Opcode: SDBBP16_MM +/* 379 */ MCD_OPC_FilterValue, 12, 7, 1, 0, // Skip to: 647 +/* 384 */ MCD_OPC_CheckPredicate, 6, 2, 1, 0, // Skip to: 647 +/* 389 */ MCD_OPC_CheckField, 5, 1, 0, 251, 0, 0, // Skip to: 647 +/* 396 */ MCD_OPC_Decode, 135, 15, 41, // Opcode: JRADDIUSP +/* 400 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 414 +/* 405 */ MCD_OPC_CheckPredicate, 7, 237, 0, 0, // Skip to: 647 +/* 410 */ MCD_OPC_Decode, 168, 16, 42, // Opcode: LWSP_MM +/* 414 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 450 +/* 419 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 422 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 436 +/* 427 */ MCD_OPC_CheckPredicate, 7, 215, 0, 0, // Skip to: 647 +/* 432 */ MCD_OPC_Decode, 137, 6, 43, // Opcode: ADDIUS5_MM +/* 436 */ MCD_OPC_FilterValue, 1, 206, 0, 0, // Skip to: 647 +/* 441 */ MCD_OPC_CheckPredicate, 7, 201, 0, 0, // Skip to: 647 +/* 446 */ MCD_OPC_Decode, 138, 6, 44, // Opcode: ADDIUSP_MM +/* 450 */ MCD_OPC_FilterValue, 25, 9, 0, 0, // Skip to: 464 +/* 455 */ MCD_OPC_CheckPredicate, 7, 187, 0, 0, // Skip to: 647 +/* 460 */ MCD_OPC_Decode, 147, 16, 45, // Opcode: LWGP_MM +/* 464 */ MCD_OPC_FilterValue, 26, 9, 0, 0, // Skip to: 478 +/* 469 */ MCD_OPC_CheckPredicate, 7, 173, 0, 0, // Skip to: 647 +/* 474 */ MCD_OPC_Decode, 132, 16, 32, // Opcode: LW16_MM +/* 478 */ MCD_OPC_FilterValue, 27, 31, 0, 0, // Skip to: 514 +/* 483 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 486 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 500 +/* 491 */ MCD_OPC_CheckPredicate, 7, 151, 0, 0, // Skip to: 647 +/* 496 */ MCD_OPC_Decode, 134, 6, 46, // Opcode: ADDIUR2_MM +/* 500 */ MCD_OPC_FilterValue, 1, 142, 0, 0, // Skip to: 647 +/* 505 */ MCD_OPC_CheckPredicate, 7, 137, 0, 0, // Skip to: 647 +/* 510 */ MCD_OPC_Decode, 132, 6, 47, // Opcode: ADDIUR1SP_MM +/* 514 */ MCD_OPC_FilterValue, 33, 16, 0, 0, // Skip to: 535 +/* 519 */ MCD_OPC_CheckPredicate, 6, 123, 0, 0, // Skip to: 647 +/* 524 */ MCD_OPC_CheckField, 0, 1, 0, 116, 0, 0, // Skip to: 647 +/* 531 */ MCD_OPC_Decode, 212, 17, 48, // Opcode: MOVEP_MM +/* 535 */ MCD_OPC_FilterValue, 34, 9, 0, 0, // Skip to: 549 +/* 540 */ MCD_OPC_CheckPredicate, 6, 102, 0, 0, // Skip to: 647 +/* 545 */ MCD_OPC_Decode, 194, 20, 32, // Opcode: SB16_MM +/* 549 */ MCD_OPC_FilterValue, 35, 9, 0, 0, // Skip to: 563 +/* 554 */ MCD_OPC_CheckPredicate, 6, 88, 0, 0, // Skip to: 647 +/* 559 */ MCD_OPC_Decode, 198, 7, 49, // Opcode: BEQZ16_MM +/* 563 */ MCD_OPC_FilterValue, 42, 9, 0, 0, // Skip to: 577 +/* 568 */ MCD_OPC_CheckPredicate, 6, 74, 0, 0, // Skip to: 647 +/* 573 */ MCD_OPC_Decode, 144, 21, 32, // Opcode: SH16_MM +/* 577 */ MCD_OPC_FilterValue, 43, 9, 0, 0, // Skip to: 591 +/* 582 */ MCD_OPC_CheckPredicate, 6, 60, 0, 0, // Skip to: 647 +/* 587 */ MCD_OPC_Decode, 188, 8, 49, // Opcode: BNEZ16_MM +/* 591 */ MCD_OPC_FilterValue, 50, 9, 0, 0, // Skip to: 605 +/* 596 */ MCD_OPC_CheckPredicate, 6, 46, 0, 0, // Skip to: 647 +/* 601 */ MCD_OPC_Decode, 163, 23, 42, // Opcode: SWSP_MM +/* 605 */ MCD_OPC_FilterValue, 51, 9, 0, 0, // Skip to: 619 +/* 610 */ MCD_OPC_CheckPredicate, 7, 32, 0, 0, // Skip to: 647 +/* 615 */ MCD_OPC_Decode, 145, 7, 50, // Opcode: B16_MM +/* 619 */ MCD_OPC_FilterValue, 58, 9, 0, 0, // Skip to: 633 +/* 624 */ MCD_OPC_CheckPredicate, 6, 18, 0, 0, // Skip to: 647 +/* 629 */ MCD_OPC_Decode, 129, 23, 32, // Opcode: SW16_MM +/* 633 */ MCD_OPC_FilterValue, 59, 9, 0, 0, // Skip to: 647 +/* 638 */ MCD_OPC_CheckPredicate, 6, 4, 0, 0, // Skip to: 647 +/* 643 */ MCD_OPC_Decode, 231, 15, 51, // Opcode: LI16_MM +/* 647 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableMicroMips32[] = { /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 0, 189, 3, // Skip to: 964 -/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 10 */ MCD_OPC_FilterValue, 0, 90, 0, // Skip to: 104 -/* 14 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 17 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 68 -/* 21 */ MCD_OPC_ExtractField, 11, 15, // Inst{25-11} ... -/* 24 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 36 -/* 28 */ MCD_OPC_CheckPredicate, 3, 28, 0, // Skip to: 60 -/* 32 */ MCD_OPC_Decode, 181, 12, 0, // Opcode: SSNOP_MM -/* 36 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 48 -/* 40 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 60 -/* 44 */ MCD_OPC_Decode, 140, 5, 0, // Opcode: EHB_MM -/* 48 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 60 -/* 52 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 60 -/* 56 */ MCD_OPC_Decode, 148, 10, 0, // Opcode: PAUSE_MM -/* 60 */ MCD_OPC_CheckPredicate, 3, 38, 6, // Skip to: 1638 -/* 64 */ MCD_OPC_Decode, 238, 11, 32, // Opcode: SLL_MM -/* 68 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 80 -/* 72 */ MCD_OPC_CheckPredicate, 3, 26, 6, // Skip to: 1638 -/* 76 */ MCD_OPC_Decode, 178, 12, 32, // Opcode: SRL_MM -/* 80 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 92 -/* 84 */ MCD_OPC_CheckPredicate, 3, 14, 6, // Skip to: 1638 -/* 88 */ MCD_OPC_Decode, 157, 12, 32, // Opcode: SRA_MM -/* 92 */ MCD_OPC_FilterValue, 3, 6, 6, // Skip to: 1638 -/* 96 */ MCD_OPC_CheckPredicate, 3, 2, 6, // Skip to: 1638 -/* 100 */ MCD_OPC_Decode, 250, 10, 32, // Opcode: ROTR_MM -/* 104 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 116 -/* 108 */ MCD_OPC_CheckPredicate, 3, 246, 5, // Skip to: 1638 -/* 112 */ MCD_OPC_Decode, 173, 2, 33, // Opcode: BREAK_MM -/* 116 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 128 -/* 120 */ MCD_OPC_CheckPredicate, 3, 234, 5, // Skip to: 1638 -/* 124 */ MCD_OPC_Decode, 246, 6, 34, // Opcode: INS_MM -/* 128 */ MCD_OPC_FilterValue, 16, 180, 0, // Skip to: 312 -/* 132 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 135 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 147 -/* 139 */ MCD_OPC_CheckPredicate, 3, 215, 5, // Skip to: 1638 -/* 143 */ MCD_OPC_Decode, 234, 11, 35, // Opcode: SLLV_MM -/* 147 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 159 -/* 151 */ MCD_OPC_CheckPredicate, 3, 203, 5, // Skip to: 1638 -/* 155 */ MCD_OPC_Decode, 174, 12, 35, // Opcode: SRLV_MM -/* 159 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 171 -/* 163 */ MCD_OPC_CheckPredicate, 3, 191, 5, // Skip to: 1638 -/* 167 */ MCD_OPC_Decode, 153, 12, 35, // Opcode: SRAV_MM -/* 171 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 183 -/* 175 */ MCD_OPC_CheckPredicate, 3, 179, 5, // Skip to: 1638 -/* 179 */ MCD_OPC_Decode, 249, 10, 35, // Opcode: ROTRV_MM -/* 183 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 194 -/* 187 */ MCD_OPC_CheckPredicate, 3, 167, 5, // Skip to: 1638 -/* 191 */ MCD_OPC_Decode, 72, 36, // Opcode: ADD_MM -/* 194 */ MCD_OPC_FilterValue, 5, 7, 0, // Skip to: 205 -/* 198 */ MCD_OPC_CheckPredicate, 3, 156, 5, // Skip to: 1638 -/* 202 */ MCD_OPC_Decode, 78, 36, // Opcode: ADDu_MM -/* 205 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 217 -/* 209 */ MCD_OPC_CheckPredicate, 3, 145, 5, // Skip to: 1638 -/* 213 */ MCD_OPC_Decode, 229, 12, 36, // Opcode: SUB_MM -/* 217 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 229 -/* 221 */ MCD_OPC_CheckPredicate, 3, 133, 5, // Skip to: 1638 -/* 225 */ MCD_OPC_Decode, 231, 12, 36, // Opcode: SUBu_MM -/* 229 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 241 -/* 233 */ MCD_OPC_CheckPredicate, 3, 121, 5, // Skip to: 1638 -/* 237 */ MCD_OPC_Decode, 217, 9, 36, // Opcode: MUL_MM -/* 241 */ MCD_OPC_FilterValue, 9, 7, 0, // Skip to: 252 -/* 245 */ MCD_OPC_CheckPredicate, 3, 109, 5, // Skip to: 1638 -/* 249 */ MCD_OPC_Decode, 88, 36, // Opcode: AND_MM -/* 252 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 264 -/* 256 */ MCD_OPC_CheckPredicate, 3, 98, 5, // Skip to: 1638 -/* 260 */ MCD_OPC_Decode, 137, 10, 36, // Opcode: OR_MM -/* 264 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 276 -/* 268 */ MCD_OPC_CheckPredicate, 3, 86, 5, // Skip to: 1638 -/* 272 */ MCD_OPC_Decode, 253, 9, 36, // Opcode: NOR_MM -/* 276 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 288 -/* 280 */ MCD_OPC_CheckPredicate, 3, 74, 5, // Skip to: 1638 -/* 284 */ MCD_OPC_Decode, 240, 13, 36, // Opcode: XOR_MM -/* 288 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 300 -/* 292 */ MCD_OPC_CheckPredicate, 3, 62, 5, // Skip to: 1638 -/* 296 */ MCD_OPC_Decode, 242, 11, 36, // Opcode: SLT_MM -/* 300 */ MCD_OPC_FilterValue, 14, 54, 5, // Skip to: 1638 -/* 304 */ MCD_OPC_CheckPredicate, 3, 50, 5, // Skip to: 1638 -/* 308 */ MCD_OPC_Decode, 251, 11, 36, // Opcode: SLTu_MM -/* 312 */ MCD_OPC_FilterValue, 24, 39, 0, // Skip to: 355 -/* 316 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 319 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 331 -/* 323 */ MCD_OPC_CheckPredicate, 3, 31, 5, // Skip to: 1638 -/* 327 */ MCD_OPC_Decode, 253, 8, 37, // Opcode: MOVN_I_MM -/* 331 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 343 -/* 335 */ MCD_OPC_CheckPredicate, 3, 19, 5, // Skip to: 1638 -/* 339 */ MCD_OPC_Decode, 145, 9, 37, // Opcode: MOVZ_I_MM -/* 343 */ MCD_OPC_FilterValue, 4, 11, 5, // Skip to: 1638 -/* 347 */ MCD_OPC_CheckPredicate, 3, 7, 5, // Skip to: 1638 -/* 351 */ MCD_OPC_Decode, 239, 7, 38, // Opcode: LWXS_MM -/* 355 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 367 -/* 359 */ MCD_OPC_CheckPredicate, 3, 251, 4, // Skip to: 1638 -/* 363 */ MCD_OPC_Decode, 160, 5, 39, // Opcode: EXT_MM -/* 367 */ MCD_OPC_FilterValue, 60, 243, 4, // Skip to: 1638 -/* 371 */ MCD_OPC_ExtractField, 6, 6, // Inst{11-6} ... -/* 374 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 386 -/* 378 */ MCD_OPC_CheckPredicate, 3, 232, 4, // Skip to: 1638 -/* 382 */ MCD_OPC_Decode, 185, 13, 40, // Opcode: TEQ_MM -/* 386 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 398 -/* 390 */ MCD_OPC_CheckPredicate, 3, 220, 4, // Skip to: 1638 -/* 394 */ MCD_OPC_Decode, 193, 13, 40, // Opcode: TGE_MM -/* 398 */ MCD_OPC_FilterValue, 13, 123, 0, // Skip to: 525 -/* 402 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 405 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 423 -/* 409 */ MCD_OPC_CheckPredicate, 3, 201, 4, // Skip to: 1638 -/* 413 */ MCD_OPC_CheckField, 16, 10, 0, 195, 4, // Skip to: 1638 -/* 419 */ MCD_OPC_Decode, 195, 13, 0, // Opcode: TLBP_MM -/* 423 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 441 -/* 427 */ MCD_OPC_CheckPredicate, 3, 183, 4, // Skip to: 1638 -/* 431 */ MCD_OPC_CheckField, 16, 10, 0, 177, 4, // Skip to: 1638 -/* 437 */ MCD_OPC_Decode, 197, 13, 0, // Opcode: TLBR_MM -/* 441 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 459 -/* 445 */ MCD_OPC_CheckPredicate, 3, 165, 4, // Skip to: 1638 -/* 449 */ MCD_OPC_CheckField, 16, 10, 0, 159, 4, // Skip to: 1638 -/* 455 */ MCD_OPC_Decode, 199, 13, 0, // Opcode: TLBWI_MM -/* 459 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 477 -/* 463 */ MCD_OPC_CheckPredicate, 3, 147, 4, // Skip to: 1638 -/* 467 */ MCD_OPC_CheckField, 16, 10, 0, 141, 4, // Skip to: 1638 -/* 473 */ MCD_OPC_Decode, 201, 13, 0, // Opcode: TLBWR_MM -/* 477 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 489 -/* 481 */ MCD_OPC_CheckPredicate, 3, 129, 4, // Skip to: 1638 -/* 485 */ MCD_OPC_Decode, 232, 13, 41, // Opcode: WAIT_MM -/* 489 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 507 -/* 493 */ MCD_OPC_CheckPredicate, 3, 117, 4, // Skip to: 1638 -/* 497 */ MCD_OPC_CheckField, 16, 10, 0, 111, 4, // Skip to: 1638 -/* 503 */ MCD_OPC_Decode, 175, 4, 0, // Opcode: DERET_MM -/* 507 */ MCD_OPC_FilterValue, 15, 103, 4, // Skip to: 1638 -/* 511 */ MCD_OPC_CheckPredicate, 3, 99, 4, // Skip to: 1638 -/* 515 */ MCD_OPC_CheckField, 16, 10, 0, 93, 4, // Skip to: 1638 -/* 521 */ MCD_OPC_Decode, 144, 5, 0, // Opcode: ERET_MM -/* 525 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 537 -/* 529 */ MCD_OPC_CheckPredicate, 3, 81, 4, // Skip to: 1638 -/* 533 */ MCD_OPC_Decode, 192, 13, 40, // Opcode: TGEU_MM -/* 537 */ MCD_OPC_FilterValue, 29, 39, 0, // Skip to: 580 -/* 541 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 544 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 562 -/* 548 */ MCD_OPC_CheckPredicate, 3, 62, 4, // Skip to: 1638 -/* 552 */ MCD_OPC_CheckField, 21, 5, 0, 56, 4, // Skip to: 1638 -/* 558 */ MCD_OPC_Decode, 193, 4, 42, // Opcode: DI_MM -/* 562 */ MCD_OPC_FilterValue, 5, 48, 4, // Skip to: 1638 -/* 566 */ MCD_OPC_CheckPredicate, 3, 44, 4, // Skip to: 1638 -/* 570 */ MCD_OPC_CheckField, 21, 5, 0, 38, 4, // Skip to: 1638 -/* 576 */ MCD_OPC_Decode, 142, 5, 42, // Opcode: EI_MM -/* 580 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 592 -/* 584 */ MCD_OPC_CheckPredicate, 3, 26, 4, // Skip to: 1638 -/* 588 */ MCD_OPC_Decode, 208, 13, 40, // Opcode: TLT_MM -/* 592 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 604 -/* 596 */ MCD_OPC_CheckPredicate, 3, 14, 4, // Skip to: 1638 -/* 600 */ MCD_OPC_Decode, 207, 13, 40, // Opcode: TLTU_MM -/* 604 */ MCD_OPC_FilterValue, 44, 171, 0, // Skip to: 779 -/* 608 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 611 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 623 -/* 615 */ MCD_OPC_CheckPredicate, 3, 251, 3, // Skip to: 1638 -/* 619 */ MCD_OPC_Decode, 170, 11, 43, // Opcode: SEB_MM -/* 623 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 635 -/* 627 */ MCD_OPC_CheckPredicate, 3, 239, 3, // Skip to: 1638 -/* 631 */ MCD_OPC_Decode, 173, 11, 43, // Opcode: SEH_MM -/* 635 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 647 -/* 639 */ MCD_OPC_CheckPredicate, 3, 227, 3, // Skip to: 1638 -/* 643 */ MCD_OPC_Decode, 134, 3, 43, // Opcode: CLO_MM -/* 647 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 659 -/* 651 */ MCD_OPC_CheckPredicate, 3, 215, 3, // Skip to: 1638 -/* 655 */ MCD_OPC_Decode, 153, 3, 43, // Opcode: CLZ_MM -/* 659 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 671 -/* 663 */ MCD_OPC_CheckPredicate, 3, 203, 3, // Skip to: 1638 -/* 667 */ MCD_OPC_Decode, 240, 10, 44, // Opcode: RDHWR_MM -/* 671 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 683 -/* 675 */ MCD_OPC_CheckPredicate, 3, 191, 3, // Skip to: 1638 -/* 679 */ MCD_OPC_Decode, 235, 13, 43, // Opcode: WSBH_MM -/* 683 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 695 -/* 687 */ MCD_OPC_CheckPredicate, 3, 179, 3, // Skip to: 1638 -/* 691 */ MCD_OPC_Decode, 209, 9, 45, // Opcode: MULT_MM -/* 695 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 707 -/* 699 */ MCD_OPC_CheckPredicate, 3, 167, 3, // Skip to: 1638 -/* 703 */ MCD_OPC_Decode, 211, 9, 45, // Opcode: MULTu_MM -/* 707 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 719 -/* 711 */ MCD_OPC_CheckPredicate, 3, 155, 3, // Skip to: 1638 -/* 715 */ MCD_OPC_Decode, 163, 11, 45, // Opcode: SDIV_MM -/* 719 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 731 -/* 723 */ MCD_OPC_CheckPredicate, 3, 143, 3, // Skip to: 1638 -/* 727 */ MCD_OPC_Decode, 223, 13, 45, // Opcode: UDIV_MM -/* 731 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 743 -/* 735 */ MCD_OPC_CheckPredicate, 3, 131, 3, // Skip to: 1638 -/* 739 */ MCD_OPC_Decode, 146, 8, 45, // Opcode: MADD_MM -/* 743 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 755 -/* 747 */ MCD_OPC_CheckPredicate, 3, 119, 3, // Skip to: 1638 -/* 751 */ MCD_OPC_Decode, 137, 8, 45, // Opcode: MADDU_MM -/* 755 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 767 -/* 759 */ MCD_OPC_CheckPredicate, 3, 107, 3, // Skip to: 1638 -/* 763 */ MCD_OPC_Decode, 164, 9, 45, // Opcode: MSUB_MM -/* 767 */ MCD_OPC_FilterValue, 15, 99, 3, // Skip to: 1638 -/* 771 */ MCD_OPC_CheckPredicate, 3, 95, 3, // Skip to: 1638 -/* 775 */ MCD_OPC_Decode, 155, 9, 45, // Opcode: MSUBU_MM -/* 779 */ MCD_OPC_FilterValue, 45, 45, 0, // Skip to: 828 -/* 783 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 786 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 804 -/* 790 */ MCD_OPC_CheckPredicate, 3, 76, 3, // Skip to: 1638 -/* 794 */ MCD_OPC_CheckField, 21, 5, 0, 70, 3, // Skip to: 1638 -/* 800 */ MCD_OPC_Decode, 131, 13, 46, // Opcode: SYNC_MM -/* 804 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 816 -/* 808 */ MCD_OPC_CheckPredicate, 3, 58, 3, // Skip to: 1638 -/* 812 */ MCD_OPC_Decode, 133, 13, 41, // Opcode: SYSCALL_MM -/* 816 */ MCD_OPC_FilterValue, 13, 50, 3, // Skip to: 1638 -/* 820 */ MCD_OPC_CheckPredicate, 3, 46, 3, // Skip to: 1638 -/* 824 */ MCD_OPC_Decode, 154, 11, 41, // Opcode: SDBBP_MM -/* 828 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 840 -/* 832 */ MCD_OPC_CheckPredicate, 3, 34, 3, // Skip to: 1638 -/* 836 */ MCD_OPC_Decode, 212, 13, 40, // Opcode: TNE_MM -/* 840 */ MCD_OPC_FilterValue, 53, 75, 0, // Skip to: 919 -/* 844 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 847 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 865 -/* 851 */ MCD_OPC_CheckPredicate, 3, 15, 3, // Skip to: 1638 -/* 855 */ MCD_OPC_CheckField, 21, 5, 0, 9, 3, // Skip to: 1638 -/* 861 */ MCD_OPC_Decode, 190, 8, 42, // Opcode: MFHI_MM -/* 865 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 883 -/* 869 */ MCD_OPC_CheckPredicate, 3, 253, 2, // Skip to: 1638 -/* 873 */ MCD_OPC_CheckField, 21, 5, 0, 247, 2, // Skip to: 1638 -/* 879 */ MCD_OPC_Decode, 195, 8, 42, // Opcode: MFLO_MM -/* 883 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 901 -/* 887 */ MCD_OPC_CheckPredicate, 3, 235, 2, // Skip to: 1638 -/* 891 */ MCD_OPC_CheckField, 21, 5, 0, 229, 2, // Skip to: 1638 -/* 897 */ MCD_OPC_Decode, 179, 9, 42, // Opcode: MTHI_MM -/* 901 */ MCD_OPC_FilterValue, 3, 221, 2, // Skip to: 1638 -/* 905 */ MCD_OPC_CheckPredicate, 3, 217, 2, // Skip to: 1638 -/* 909 */ MCD_OPC_CheckField, 21, 5, 0, 211, 2, // Skip to: 1638 -/* 915 */ MCD_OPC_Decode, 184, 9, 42, // Opcode: MTLO_MM -/* 919 */ MCD_OPC_FilterValue, 60, 203, 2, // Skip to: 1638 -/* 923 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 926 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 952 -/* 930 */ MCD_OPC_CheckPredicate, 3, 10, 0, // Skip to: 944 -/* 934 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 944 -/* 940 */ MCD_OPC_Decode, 143, 7, 42, // Opcode: JR_MM -/* 944 */ MCD_OPC_CheckPredicate, 3, 178, 2, // Skip to: 1638 -/* 948 */ MCD_OPC_Decode, 129, 7, 43, // Opcode: JALR_MM -/* 952 */ MCD_OPC_FilterValue, 4, 170, 2, // Skip to: 1638 -/* 956 */ MCD_OPC_CheckPredicate, 3, 166, 2, // Skip to: 1638 -/* 960 */ MCD_OPC_Decode, 255, 6, 43, // Opcode: JALRS_MM -/* 964 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 975 -/* 968 */ MCD_OPC_CheckPredicate, 3, 154, 2, // Skip to: 1638 -/* 972 */ MCD_OPC_Decode, 74, 47, // Opcode: ADDi_MM -/* 975 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 987 -/* 979 */ MCD_OPC_CheckPredicate, 3, 143, 2, // Skip to: 1638 -/* 983 */ MCD_OPC_Decode, 160, 7, 48, // Opcode: LBu_MM -/* 987 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 999 -/* 991 */ MCD_OPC_CheckPredicate, 3, 131, 2, // Skip to: 1638 -/* 995 */ MCD_OPC_Decode, 145, 11, 48, // Opcode: SB_MM -/* 999 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 1011 -/* 1003 */ MCD_OPC_CheckPredicate, 3, 119, 2, // Skip to: 1638 -/* 1007 */ MCD_OPC_Decode, 157, 7, 48, // Opcode: LB_MM -/* 1011 */ MCD_OPC_FilterValue, 8, 63, 0, // Skip to: 1078 -/* 1015 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 1018 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1030 -/* 1022 */ MCD_OPC_CheckPredicate, 3, 100, 2, // Skip to: 1638 -/* 1026 */ MCD_OPC_Decode, 229, 7, 49, // Opcode: LWP_MM -/* 1030 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1042 -/* 1034 */ MCD_OPC_CheckPredicate, 3, 88, 2, // Skip to: 1638 -/* 1038 */ MCD_OPC_Decode, 226, 7, 49, // Opcode: LWM32_MM -/* 1042 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1054 -/* 1046 */ MCD_OPC_CheckPredicate, 3, 76, 2, // Skip to: 1638 -/* 1050 */ MCD_OPC_Decode, 221, 2, 50, // Opcode: CACHE_MM -/* 1054 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1066 -/* 1058 */ MCD_OPC_CheckPredicate, 3, 64, 2, // Skip to: 1638 -/* 1062 */ MCD_OPC_Decode, 249, 12, 49, // Opcode: SWP_MM -/* 1066 */ MCD_OPC_FilterValue, 13, 56, 2, // Skip to: 1638 -/* 1070 */ MCD_OPC_CheckPredicate, 3, 52, 2, // Skip to: 1638 -/* 1074 */ MCD_OPC_Decode, 247, 12, 49, // Opcode: SWM32_MM -/* 1078 */ MCD_OPC_FilterValue, 12, 7, 0, // Skip to: 1089 -/* 1082 */ MCD_OPC_CheckPredicate, 3, 40, 2, // Skip to: 1638 -/* 1086 */ MCD_OPC_Decode, 76, 47, // Opcode: ADDiu_MM -/* 1089 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1101 -/* 1093 */ MCD_OPC_CheckPredicate, 3, 29, 2, // Skip to: 1638 -/* 1097 */ MCD_OPC_Decode, 191, 7, 48, // Opcode: LHu_MM -/* 1101 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1113 -/* 1105 */ MCD_OPC_CheckPredicate, 3, 17, 2, // Skip to: 1638 -/* 1109 */ MCD_OPC_Decode, 216, 11, 48, // Opcode: SH_MM -/* 1113 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 1125 -/* 1117 */ MCD_OPC_CheckPredicate, 3, 5, 2, // Skip to: 1638 -/* 1121 */ MCD_OPC_Decode, 188, 7, 48, // Opcode: LH_MM -/* 1125 */ MCD_OPC_FilterValue, 16, 207, 0, // Skip to: 1336 -/* 1129 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1132 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1144 -/* 1136 */ MCD_OPC_CheckPredicate, 3, 242, 1, // Skip to: 1638 -/* 1140 */ MCD_OPC_Decode, 140, 2, 51, // Opcode: BLTZ_MM -/* 1144 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1156 -/* 1148 */ MCD_OPC_CheckPredicate, 3, 230, 1, // Skip to: 1638 -/* 1152 */ MCD_OPC_Decode, 137, 2, 51, // Opcode: BLTZAL_MM -/* 1156 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1168 -/* 1160 */ MCD_OPC_CheckPredicate, 3, 218, 1, // Skip to: 1638 -/* 1164 */ MCD_OPC_Decode, 226, 1, 51, // Opcode: BGEZ_MM -/* 1168 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1180 -/* 1172 */ MCD_OPC_CheckPredicate, 3, 206, 1, // Skip to: 1638 -/* 1176 */ MCD_OPC_Decode, 223, 1, 51, // Opcode: BGEZAL_MM -/* 1180 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1192 -/* 1184 */ MCD_OPC_CheckPredicate, 3, 194, 1, // Skip to: 1638 -/* 1188 */ MCD_OPC_Decode, 128, 2, 51, // Opcode: BLEZ_MM -/* 1192 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1204 -/* 1196 */ MCD_OPC_CheckPredicate, 3, 182, 1, // Skip to: 1638 -/* 1200 */ MCD_OPC_Decode, 160, 2, 51, // Opcode: BNEZC_MM -/* 1204 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1216 -/* 1208 */ MCD_OPC_CheckPredicate, 3, 170, 1, // Skip to: 1638 -/* 1212 */ MCD_OPC_Decode, 232, 1, 51, // Opcode: BGTZ_MM -/* 1216 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 1228 -/* 1220 */ MCD_OPC_CheckPredicate, 3, 158, 1, // Skip to: 1638 -/* 1224 */ MCD_OPC_Decode, 213, 1, 51, // Opcode: BEQZC_MM -/* 1228 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1240 -/* 1232 */ MCD_OPC_CheckPredicate, 3, 146, 1, // Skip to: 1638 -/* 1236 */ MCD_OPC_Decode, 205, 13, 52, // Opcode: TLTI_MM -/* 1240 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1252 -/* 1244 */ MCD_OPC_CheckPredicate, 3, 134, 1, // Skip to: 1638 -/* 1248 */ MCD_OPC_Decode, 190, 13, 52, // Opcode: TGEI_MM -/* 1252 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1264 -/* 1256 */ MCD_OPC_CheckPredicate, 3, 122, 1, // Skip to: 1638 -/* 1260 */ MCD_OPC_Decode, 204, 13, 52, // Opcode: TLTIU_MM -/* 1264 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1276 -/* 1268 */ MCD_OPC_CheckPredicate, 3, 110, 1, // Skip to: 1638 -/* 1272 */ MCD_OPC_Decode, 189, 13, 52, // Opcode: TGEIU_MM -/* 1276 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 1288 -/* 1280 */ MCD_OPC_CheckPredicate, 3, 98, 1, // Skip to: 1638 -/* 1284 */ MCD_OPC_Decode, 211, 13, 52, // Opcode: TNEI_MM -/* 1288 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1300 -/* 1292 */ MCD_OPC_CheckPredicate, 3, 86, 1, // Skip to: 1638 -/* 1296 */ MCD_OPC_Decode, 212, 7, 52, // Opcode: LUi_MM -/* 1300 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1312 -/* 1304 */ MCD_OPC_CheckPredicate, 3, 74, 1, // Skip to: 1638 -/* 1308 */ MCD_OPC_Decode, 184, 13, 52, // Opcode: TEQI_MM -/* 1312 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1324 -/* 1316 */ MCD_OPC_CheckPredicate, 3, 62, 1, // Skip to: 1638 -/* 1320 */ MCD_OPC_Decode, 136, 2, 51, // Opcode: BLTZALS_MM -/* 1324 */ MCD_OPC_FilterValue, 19, 54, 1, // Skip to: 1638 -/* 1328 */ MCD_OPC_CheckPredicate, 3, 50, 1, // Skip to: 1638 -/* 1332 */ MCD_OPC_Decode, 222, 1, 51, // Opcode: BGEZALS_MM -/* 1336 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 1348 -/* 1340 */ MCD_OPC_CheckPredicate, 3, 38, 1, // Skip to: 1638 -/* 1344 */ MCD_OPC_Decode, 144, 10, 53, // Opcode: ORi_MM -/* 1348 */ MCD_OPC_FilterValue, 21, 29, 0, // Skip to: 1381 -/* 1352 */ MCD_OPC_ExtractField, 0, 13, // Inst{12-0} ... -/* 1355 */ MCD_OPC_FilterValue, 251, 2, 8, 0, // Skip to: 1368 -/* 1360 */ MCD_OPC_CheckPredicate, 3, 18, 1, // Skip to: 1638 -/* 1364 */ MCD_OPC_Decode, 241, 8, 54, // Opcode: MOVF_I_MM -/* 1368 */ MCD_OPC_FilterValue, 251, 18, 9, 1, // Skip to: 1638 -/* 1373 */ MCD_OPC_CheckPredicate, 3, 5, 1, // Skip to: 1638 -/* 1377 */ MCD_OPC_Decode, 133, 9, 54, // Opcode: MOVT_I_MM -/* 1381 */ MCD_OPC_FilterValue, 24, 99, 0, // Skip to: 1484 -/* 1385 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 1388 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1400 -/* 1392 */ MCD_OPC_CheckPredicate, 3, 242, 0, // Skip to: 1638 -/* 1396 */ MCD_OPC_Decode, 224, 7, 49, // Opcode: LWL_MM -/* 1400 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1412 -/* 1404 */ MCD_OPC_CheckPredicate, 3, 230, 0, // Skip to: 1638 -/* 1408 */ MCD_OPC_Decode, 232, 7, 49, // Opcode: LWR_MM -/* 1412 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1424 -/* 1416 */ MCD_OPC_CheckPredicate, 3, 218, 0, // Skip to: 1638 -/* 1420 */ MCD_OPC_Decode, 182, 10, 50, // Opcode: PREF_MM -/* 1424 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1436 -/* 1428 */ MCD_OPC_CheckPredicate, 3, 206, 0, // Skip to: 1638 -/* 1432 */ MCD_OPC_Decode, 196, 7, 49, // Opcode: LL_MM -/* 1436 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1448 -/* 1440 */ MCD_OPC_CheckPredicate, 3, 194, 0, // Skip to: 1638 -/* 1444 */ MCD_OPC_Decode, 245, 12, 49, // Opcode: SWL_MM -/* 1448 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1460 -/* 1452 */ MCD_OPC_CheckPredicate, 3, 182, 0, // Skip to: 1638 -/* 1456 */ MCD_OPC_Decode, 252, 12, 49, // Opcode: SWR_MM -/* 1460 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1472 -/* 1464 */ MCD_OPC_CheckPredicate, 3, 170, 0, // Skip to: 1638 -/* 1468 */ MCD_OPC_Decode, 149, 11, 49, // Opcode: SC_MM -/* 1472 */ MCD_OPC_FilterValue, 14, 162, 0, // Skip to: 1638 -/* 1476 */ MCD_OPC_CheckPredicate, 3, 158, 0, // Skip to: 1638 -/* 1480 */ MCD_OPC_Decode, 235, 7, 49, // Opcode: LWU_MM -/* 1484 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 1496 -/* 1488 */ MCD_OPC_CheckPredicate, 3, 146, 0, // Skip to: 1638 -/* 1492 */ MCD_OPC_Decode, 247, 13, 53, // Opcode: XORi_MM -/* 1496 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 1508 -/* 1500 */ MCD_OPC_CheckPredicate, 3, 134, 0, // Skip to: 1638 -/* 1504 */ MCD_OPC_Decode, 130, 7, 55, // Opcode: JALS_MM -/* 1508 */ MCD_OPC_FilterValue, 30, 7, 0, // Skip to: 1519 -/* 1512 */ MCD_OPC_CheckPredicate, 3, 122, 0, // Skip to: 1638 -/* 1516 */ MCD_OPC_Decode, 27, 56, // Opcode: ADDIUPC_MM -/* 1519 */ MCD_OPC_FilterValue, 36, 8, 0, // Skip to: 1531 -/* 1523 */ MCD_OPC_CheckPredicate, 3, 111, 0, // Skip to: 1638 -/* 1527 */ MCD_OPC_Decode, 245, 11, 47, // Opcode: SLTi_MM -/* 1531 */ MCD_OPC_FilterValue, 37, 8, 0, // Skip to: 1543 -/* 1535 */ MCD_OPC_CheckPredicate, 3, 99, 0, // Skip to: 1638 -/* 1539 */ MCD_OPC_Decode, 214, 1, 57, // Opcode: BEQ_MM -/* 1543 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 1555 -/* 1547 */ MCD_OPC_CheckPredicate, 3, 87, 0, // Skip to: 1638 -/* 1551 */ MCD_OPC_Decode, 248, 11, 47, // Opcode: SLTiu_MM -/* 1555 */ MCD_OPC_FilterValue, 45, 8, 0, // Skip to: 1567 -/* 1559 */ MCD_OPC_CheckPredicate, 3, 75, 0, // Skip to: 1638 -/* 1563 */ MCD_OPC_Decode, 161, 2, 57, // Opcode: BNE_MM -/* 1567 */ MCD_OPC_FilterValue, 52, 7, 0, // Skip to: 1578 -/* 1571 */ MCD_OPC_CheckPredicate, 3, 63, 0, // Skip to: 1638 -/* 1575 */ MCD_OPC_Decode, 95, 53, // Opcode: ANDi_MM -/* 1578 */ MCD_OPC_FilterValue, 53, 8, 0, // Skip to: 1590 -/* 1582 */ MCD_OPC_CheckPredicate, 3, 52, 0, // Skip to: 1638 -/* 1586 */ MCD_OPC_Decode, 144, 7, 55, // Opcode: J_MM -/* 1590 */ MCD_OPC_FilterValue, 60, 8, 0, // Skip to: 1602 -/* 1594 */ MCD_OPC_CheckPredicate, 3, 40, 0, // Skip to: 1638 -/* 1598 */ MCD_OPC_Decode, 132, 7, 55, // Opcode: JALX_MM -/* 1602 */ MCD_OPC_FilterValue, 61, 8, 0, // Skip to: 1614 -/* 1606 */ MCD_OPC_CheckPredicate, 3, 28, 0, // Skip to: 1638 -/* 1610 */ MCD_OPC_Decode, 133, 7, 55, // Opcode: JAL_MM -/* 1614 */ MCD_OPC_FilterValue, 62, 8, 0, // Skip to: 1626 -/* 1618 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 1638 -/* 1622 */ MCD_OPC_Decode, 128, 13, 48, // Opcode: SW_MM -/* 1626 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 1638 -/* 1630 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 1638 -/* 1634 */ MCD_OPC_Decode, 240, 7, 48, // Opcode: LW_MM -/* 1638 */ MCD_OPC_Fail, +/* 3 */ MCD_OPC_FilterValue, 0, 238, 14, 0, // Skip to: 3830 +/* 8 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 11 */ MCD_OPC_FilterValue, 0, 104, 0, 0, // Skip to: 120 +/* 16 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 19 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 78 +/* 24 */ MCD_OPC_ExtractField, 11, 15, // Inst{25-11} ... +/* 27 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 41 +/* 32 */ MCD_OPC_CheckPredicate, 7, 32, 0, 0, // Skip to: 69 +/* 37 */ MCD_OPC_Decode, 186, 22, 10, // Opcode: SSNOP_MM +/* 41 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 55 +/* 46 */ MCD_OPC_CheckPredicate, 7, 18, 0, 0, // Skip to: 69 +/* 51 */ MCD_OPC_Decode, 207, 12, 10, // Opcode: EHB_MM +/* 55 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 69 +/* 60 */ MCD_OPC_CheckPredicate, 7, 4, 0, 0, // Skip to: 69 +/* 65 */ MCD_OPC_Decode, 182, 19, 10, // Opcode: PAUSE_MM +/* 69 */ MCD_OPC_CheckPredicate, 7, 101, 25, 0, // Skip to: 6575 +/* 74 */ MCD_OPC_Decode, 235, 21, 52, // Opcode: SLL_MM +/* 78 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 92 +/* 83 */ MCD_OPC_CheckPredicate, 7, 87, 25, 0, // Skip to: 6575 +/* 88 */ MCD_OPC_Decode, 182, 22, 52, // Opcode: SRL_MM +/* 92 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 106 +/* 97 */ MCD_OPC_CheckPredicate, 7, 73, 25, 0, // Skip to: 6575 +/* 102 */ MCD_OPC_Decode, 157, 22, 52, // Opcode: SRA_MM +/* 106 */ MCD_OPC_FilterValue, 3, 64, 25, 0, // Skip to: 6575 +/* 111 */ MCD_OPC_CheckPredicate, 7, 59, 25, 0, // Skip to: 6575 +/* 116 */ MCD_OPC_Decode, 159, 20, 52, // Opcode: ROTR_MM +/* 120 */ MCD_OPC_FilterValue, 5, 227, 0, 0, // Skip to: 352 +/* 125 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 128 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 149 +/* 133 */ MCD_OPC_CheckPredicate, 8, 37, 25, 0, // Skip to: 6575 +/* 138 */ MCD_OPC_CheckField, 11, 5, 0, 30, 25, 0, // Skip to: 6575 +/* 145 */ MCD_OPC_Decode, 221, 9, 53, // Opcode: CMP_EQ_PH_MM +/* 149 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 170 +/* 154 */ MCD_OPC_CheckPredicate, 8, 16, 25, 0, // Skip to: 6575 +/* 159 */ MCD_OPC_CheckField, 11, 5, 0, 9, 25, 0, // Skip to: 6575 +/* 166 */ MCD_OPC_Decode, 235, 9, 53, // Opcode: CMP_LT_PH_MM +/* 170 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 191 +/* 175 */ MCD_OPC_CheckPredicate, 8, 251, 24, 0, // Skip to: 6575 +/* 180 */ MCD_OPC_CheckField, 11, 5, 0, 244, 24, 0, // Skip to: 6575 +/* 187 */ MCD_OPC_Decode, 229, 9, 53, // Opcode: CMP_LE_PH_MM +/* 191 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 205 +/* 196 */ MCD_OPC_CheckPredicate, 9, 230, 24, 0, // Skip to: 6575 +/* 201 */ MCD_OPC_Decode, 199, 9, 54, // Opcode: CMPGDU_EQ_QB_MMR2 +/* 205 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 219 +/* 210 */ MCD_OPC_CheckPredicate, 9, 216, 24, 0, // Skip to: 6575 +/* 215 */ MCD_OPC_Decode, 203, 9, 54, // Opcode: CMPGDU_LT_QB_MMR2 +/* 219 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 233 +/* 224 */ MCD_OPC_CheckPredicate, 9, 202, 24, 0, // Skip to: 6575 +/* 229 */ MCD_OPC_Decode, 201, 9, 54, // Opcode: CMPGDU_LE_QB_MMR2 +/* 233 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 254 +/* 238 */ MCD_OPC_CheckPredicate, 8, 188, 24, 0, // Skip to: 6575 +/* 243 */ MCD_OPC_CheckField, 11, 5, 0, 181, 24, 0, // Skip to: 6575 +/* 250 */ MCD_OPC_Decode, 211, 9, 53, // Opcode: CMPU_EQ_QB_MM +/* 254 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 275 +/* 259 */ MCD_OPC_CheckPredicate, 8, 167, 24, 0, // Skip to: 6575 +/* 264 */ MCD_OPC_CheckField, 11, 5, 0, 160, 24, 0, // Skip to: 6575 +/* 271 */ MCD_OPC_Decode, 215, 9, 53, // Opcode: CMPU_LT_QB_MM +/* 275 */ MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 296 +/* 280 */ MCD_OPC_CheckPredicate, 8, 146, 24, 0, // Skip to: 6575 +/* 285 */ MCD_OPC_CheckField, 11, 5, 0, 139, 24, 0, // Skip to: 6575 +/* 292 */ MCD_OPC_Decode, 213, 9, 53, // Opcode: CMPU_LE_QB_MM +/* 296 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 310 +/* 301 */ MCD_OPC_CheckPredicate, 8, 125, 24, 0, // Skip to: 6575 +/* 306 */ MCD_OPC_Decode, 154, 6, 55, // Opcode: ADDQ_S_W_MM +/* 310 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 324 +/* 315 */ MCD_OPC_CheckPredicate, 8, 111, 24, 0, // Skip to: 6575 +/* 320 */ MCD_OPC_Decode, 206, 22, 55, // Opcode: SUBQ_S_W_MM +/* 324 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 338 +/* 329 */ MCD_OPC_CheckPredicate, 8, 97, 24, 0, // Skip to: 6575 +/* 334 */ MCD_OPC_Decode, 157, 6, 55, // Opcode: ADDSC_MM +/* 338 */ MCD_OPC_FilterValue, 15, 88, 24, 0, // Skip to: 6575 +/* 343 */ MCD_OPC_CheckPredicate, 8, 83, 24, 0, // Skip to: 6575 +/* 348 */ MCD_OPC_Decode, 194, 6, 55, // Opcode: ADDWC_MM +/* 352 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 366 +/* 357 */ MCD_OPC_CheckPredicate, 7, 69, 24, 0, // Skip to: 6575 +/* 362 */ MCD_OPC_Decode, 215, 8, 56, // Opcode: BREAK_MM +/* 366 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 380 +/* 371 */ MCD_OPC_CheckPredicate, 6, 55, 24, 0, // Skip to: 6575 +/* 376 */ MCD_OPC_Decode, 231, 14, 57, // Opcode: INS_MM +/* 380 */ MCD_OPC_FilterValue, 13, 167, 1, 0, // Skip to: 808 +/* 385 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 388 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 402 +/* 393 */ MCD_OPC_CheckPredicate, 8, 33, 24, 0, // Skip to: 6575 +/* 398 */ MCD_OPC_Decode, 150, 6, 58, // Opcode: ADDQ_PH_MM +/* 402 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 416 +/* 407 */ MCD_OPC_CheckPredicate, 9, 19, 24, 0, // Skip to: 6575 +/* 412 */ MCD_OPC_Decode, 142, 6, 58, // Opcode: ADDQH_PH_MMR2 +/* 416 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 430 +/* 421 */ MCD_OPC_CheckPredicate, 9, 5, 24, 0, // Skip to: 6575 +/* 426 */ MCD_OPC_Decode, 148, 6, 55, // Opcode: ADDQH_W_MMR2 +/* 430 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 444 +/* 435 */ MCD_OPC_CheckPredicate, 8, 247, 23, 0, // Skip to: 6575 +/* 440 */ MCD_OPC_Decode, 180, 6, 58, // Opcode: ADDU_QB_MM +/* 444 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 458 +/* 449 */ MCD_OPC_CheckPredicate, 9, 233, 23, 0, // Skip to: 6575 +/* 454 */ MCD_OPC_Decode, 178, 6, 58, // Opcode: ADDU_PH_MMR2 +/* 458 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 472 +/* 463 */ MCD_OPC_CheckPredicate, 9, 219, 23, 0, // Skip to: 6575 +/* 468 */ MCD_OPC_Decode, 173, 6, 58, // Opcode: ADDUH_QB_MMR2 +/* 472 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 486 +/* 477 */ MCD_OPC_CheckPredicate, 8, 205, 23, 0, // Skip to: 6575 +/* 482 */ MCD_OPC_Decode, 175, 21, 59, // Opcode: SHRAV_PH_MM +/* 486 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 500 +/* 491 */ MCD_OPC_CheckPredicate, 9, 191, 23, 0, // Skip to: 6575 +/* 496 */ MCD_OPC_Decode, 177, 21, 59, // Opcode: SHRAV_QB_MMR2 +/* 500 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 514 +/* 505 */ MCD_OPC_CheckPredicate, 8, 177, 23, 0, // Skip to: 6575 +/* 510 */ MCD_OPC_Decode, 202, 22, 58, // Opcode: SUBQ_PH_MM +/* 514 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 528 +/* 519 */ MCD_OPC_CheckPredicate, 9, 163, 23, 0, // Skip to: 6575 +/* 524 */ MCD_OPC_Decode, 194, 22, 58, // Opcode: SUBQH_PH_MMR2 +/* 528 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 542 +/* 533 */ MCD_OPC_CheckPredicate, 9, 149, 23, 0, // Skip to: 6575 +/* 538 */ MCD_OPC_Decode, 200, 22, 55, // Opcode: SUBQH_W_MMR2 +/* 542 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 556 +/* 547 */ MCD_OPC_CheckPredicate, 8, 135, 23, 0, // Skip to: 6575 +/* 552 */ MCD_OPC_Decode, 233, 22, 58, // Opcode: SUBU_QB_MM +/* 556 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 570 +/* 561 */ MCD_OPC_CheckPredicate, 9, 121, 23, 0, // Skip to: 6575 +/* 566 */ MCD_OPC_Decode, 231, 22, 58, // Opcode: SUBU_PH_MMR2 +/* 570 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 584 +/* 575 */ MCD_OPC_CheckPredicate, 9, 107, 23, 0, // Skip to: 6575 +/* 580 */ MCD_OPC_Decode, 226, 22, 58, // Opcode: SUBUH_QB_MMR2 +/* 584 */ MCD_OPC_FilterValue, 15, 9, 0, 0, // Skip to: 598 +/* 589 */ MCD_OPC_CheckPredicate, 9, 93, 23, 0, // Skip to: 6575 +/* 594 */ MCD_OPC_Decode, 235, 19, 60, // Opcode: PRECR_SRA_PH_W_MMR2 +/* 598 */ MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 612 +/* 603 */ MCD_OPC_CheckPredicate, 8, 79, 23, 0, // Skip to: 6575 +/* 608 */ MCD_OPC_Decode, 152, 6, 58, // Opcode: ADDQ_S_PH_MM +/* 612 */ MCD_OPC_FilterValue, 17, 9, 0, 0, // Skip to: 626 +/* 617 */ MCD_OPC_CheckPredicate, 9, 65, 23, 0, // Skip to: 6575 +/* 622 */ MCD_OPC_Decode, 144, 6, 58, // Opcode: ADDQH_R_PH_MMR2 +/* 626 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 640 +/* 631 */ MCD_OPC_CheckPredicate, 9, 51, 23, 0, // Skip to: 6575 +/* 636 */ MCD_OPC_Decode, 146, 6, 55, // Opcode: ADDQH_R_W_MMR2 +/* 640 */ MCD_OPC_FilterValue, 19, 9, 0, 0, // Skip to: 654 +/* 645 */ MCD_OPC_CheckPredicate, 8, 37, 23, 0, // Skip to: 6575 +/* 650 */ MCD_OPC_Decode, 184, 6, 58, // Opcode: ADDU_S_QB_MM +/* 654 */ MCD_OPC_FilterValue, 20, 9, 0, 0, // Skip to: 668 +/* 659 */ MCD_OPC_CheckPredicate, 9, 23, 23, 0, // Skip to: 6575 +/* 664 */ MCD_OPC_Decode, 182, 6, 58, // Opcode: ADDU_S_PH_MMR2 +/* 668 */ MCD_OPC_FilterValue, 21, 9, 0, 0, // Skip to: 682 +/* 673 */ MCD_OPC_CheckPredicate, 9, 9, 23, 0, // Skip to: 6575 +/* 678 */ MCD_OPC_Decode, 175, 6, 58, // Opcode: ADDUH_R_QB_MMR2 +/* 682 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 696 +/* 687 */ MCD_OPC_CheckPredicate, 8, 251, 22, 0, // Skip to: 6575 +/* 692 */ MCD_OPC_Decode, 179, 21, 59, // Opcode: SHRAV_R_PH_MM +/* 696 */ MCD_OPC_FilterValue, 23, 9, 0, 0, // Skip to: 710 +/* 701 */ MCD_OPC_CheckPredicate, 9, 237, 22, 0, // Skip to: 6575 +/* 706 */ MCD_OPC_Decode, 181, 21, 59, // Opcode: SHRAV_R_QB_MMR2 +/* 710 */ MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 724 +/* 715 */ MCD_OPC_CheckPredicate, 8, 223, 22, 0, // Skip to: 6575 +/* 720 */ MCD_OPC_Decode, 204, 22, 58, // Opcode: SUBQ_S_PH_MM +/* 724 */ MCD_OPC_FilterValue, 25, 9, 0, 0, // Skip to: 738 +/* 729 */ MCD_OPC_CheckPredicate, 9, 209, 22, 0, // Skip to: 6575 +/* 734 */ MCD_OPC_Decode, 196, 22, 58, // Opcode: SUBQH_R_PH_MMR2 +/* 738 */ MCD_OPC_FilterValue, 26, 9, 0, 0, // Skip to: 752 +/* 743 */ MCD_OPC_CheckPredicate, 9, 195, 22, 0, // Skip to: 6575 +/* 748 */ MCD_OPC_Decode, 198, 22, 55, // Opcode: SUBQH_R_W_MMR2 +/* 752 */ MCD_OPC_FilterValue, 27, 9, 0, 0, // Skip to: 766 +/* 757 */ MCD_OPC_CheckPredicate, 8, 181, 22, 0, // Skip to: 6575 +/* 762 */ MCD_OPC_Decode, 237, 22, 58, // Opcode: SUBU_S_QB_MM +/* 766 */ MCD_OPC_FilterValue, 28, 9, 0, 0, // Skip to: 780 +/* 771 */ MCD_OPC_CheckPredicate, 9, 167, 22, 0, // Skip to: 6575 +/* 776 */ MCD_OPC_Decode, 235, 22, 58, // Opcode: SUBU_S_PH_MMR2 +/* 780 */ MCD_OPC_FilterValue, 29, 9, 0, 0, // Skip to: 794 +/* 785 */ MCD_OPC_CheckPredicate, 9, 153, 22, 0, // Skip to: 6575 +/* 790 */ MCD_OPC_Decode, 228, 22, 58, // Opcode: SUBUH_R_QB_MMR2 +/* 794 */ MCD_OPC_FilterValue, 31, 144, 22, 0, // Skip to: 6575 +/* 799 */ MCD_OPC_CheckPredicate, 9, 139, 22, 0, // Skip to: 6575 +/* 804 */ MCD_OPC_Decode, 237, 19, 60, // Opcode: PRECR_SRA_R_PH_W_MMR2 +/* 808 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 844 +/* 813 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 816 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 830 +/* 821 */ MCD_OPC_CheckPredicate, 8, 117, 22, 0, // Skip to: 6575 +/* 826 */ MCD_OPC_Decode, 159, 21, 59, // Opcode: SHLLV_PH_MM +/* 830 */ MCD_OPC_FilterValue, 16, 108, 22, 0, // Skip to: 6575 +/* 835 */ MCD_OPC_CheckPredicate, 8, 103, 22, 0, // Skip to: 6575 +/* 840 */ MCD_OPC_Decode, 163, 21, 59, // Opcode: SHLLV_S_PH_MM +/* 844 */ MCD_OPC_FilterValue, 16, 213, 0, 0, // Skip to: 1062 +/* 849 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 852 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 866 +/* 857 */ MCD_OPC_CheckPredicate, 7, 81, 22, 0, // Skip to: 6575 +/* 862 */ MCD_OPC_Decode, 230, 21, 61, // Opcode: SLLV_MM +/* 866 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 880 +/* 871 */ MCD_OPC_CheckPredicate, 7, 67, 22, 0, // Skip to: 6575 +/* 876 */ MCD_OPC_Decode, 177, 22, 61, // Opcode: SRLV_MM +/* 880 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 894 +/* 885 */ MCD_OPC_CheckPredicate, 7, 53, 22, 0, // Skip to: 6575 +/* 890 */ MCD_OPC_Decode, 152, 22, 61, // Opcode: SRAV_MM +/* 894 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 908 +/* 899 */ MCD_OPC_CheckPredicate, 7, 39, 22, 0, // Skip to: 6575 +/* 904 */ MCD_OPC_Decode, 157, 20, 61, // Opcode: ROTRV_MM +/* 908 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 922 +/* 913 */ MCD_OPC_CheckPredicate, 6, 25, 22, 0, // Skip to: 6575 +/* 918 */ MCD_OPC_Decode, 199, 6, 55, // Opcode: ADD_MM +/* 922 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 936 +/* 927 */ MCD_OPC_CheckPredicate, 6, 11, 22, 0, // Skip to: 6575 +/* 932 */ MCD_OPC_Decode, 209, 6, 55, // Opcode: ADDu_MM +/* 936 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 950 +/* 941 */ MCD_OPC_CheckPredicate, 6, 253, 21, 0, // Skip to: 6575 +/* 946 */ MCD_OPC_Decode, 246, 22, 55, // Opcode: SUB_MM +/* 950 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 964 +/* 955 */ MCD_OPC_CheckPredicate, 6, 239, 21, 0, // Skip to: 6575 +/* 960 */ MCD_OPC_Decode, 251, 22, 55, // Opcode: SUBu_MM +/* 964 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 978 +/* 969 */ MCD_OPC_CheckPredicate, 6, 225, 21, 0, // Skip to: 6575 +/* 974 */ MCD_OPC_Decode, 245, 18, 55, // Opcode: MUL_MM +/* 978 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 992 +/* 983 */ MCD_OPC_CheckPredicate, 6, 211, 21, 0, // Skip to: 6575 +/* 988 */ MCD_OPC_Decode, 227, 6, 55, // Opcode: AND_MM +/* 992 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 1006 +/* 997 */ MCD_OPC_CheckPredicate, 6, 197, 21, 0, // Skip to: 6575 +/* 1002 */ MCD_OPC_Decode, 171, 19, 55, // Opcode: OR_MM +/* 1006 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 1020 +/* 1011 */ MCD_OPC_CheckPredicate, 6, 183, 21, 0, // Skip to: 6575 +/* 1016 */ MCD_OPC_Decode, 154, 19, 55, // Opcode: NOR_MM +/* 1020 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 1034 +/* 1025 */ MCD_OPC_CheckPredicate, 6, 169, 21, 0, // Skip to: 6575 +/* 1030 */ MCD_OPC_Decode, 180, 24, 55, // Opcode: XOR_MM +/* 1034 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 1048 +/* 1039 */ MCD_OPC_CheckPredicate, 7, 155, 21, 0, // Skip to: 6575 +/* 1044 */ MCD_OPC_Decode, 244, 21, 55, // Opcode: SLT_MM +/* 1048 */ MCD_OPC_FilterValue, 14, 146, 21, 0, // Skip to: 6575 +/* 1053 */ MCD_OPC_CheckPredicate, 7, 141, 21, 0, // Skip to: 6575 +/* 1058 */ MCD_OPC_Decode, 254, 21, 55, // Opcode: SLTu_MM +/* 1062 */ MCD_OPC_FilterValue, 21, 199, 0, 0, // Skip to: 1266 +/* 1067 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1070 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1084 +/* 1075 */ MCD_OPC_CheckPredicate, 8, 119, 21, 0, // Skip to: 6575 +/* 1080 */ MCD_OPC_Decode, 212, 18, 58, // Opcode: MULEU_S_PH_QBL_MM +/* 1084 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 1098 +/* 1089 */ MCD_OPC_CheckPredicate, 8, 105, 21, 0, // Skip to: 6575 +/* 1094 */ MCD_OPC_Decode, 214, 18, 58, // Opcode: MULEU_S_PH_QBR_MM +/* 1098 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1112 +/* 1103 */ MCD_OPC_CheckPredicate, 8, 91, 21, 0, // Skip to: 6575 +/* 1108 */ MCD_OPC_Decode, 216, 18, 58, // Opcode: MULQ_RS_PH_MM +/* 1112 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 1126 +/* 1117 */ MCD_OPC_CheckPredicate, 9, 77, 21, 0, // Skip to: 6575 +/* 1122 */ MCD_OPC_Decode, 220, 18, 58, // Opcode: MULQ_S_PH_MMR2 +/* 1126 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1140 +/* 1131 */ MCD_OPC_CheckPredicate, 9, 63, 21, 0, // Skip to: 6575 +/* 1136 */ MCD_OPC_Decode, 218, 18, 55, // Opcode: MULQ_RS_W_MMR2 +/* 1140 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 1154 +/* 1145 */ MCD_OPC_CheckPredicate, 9, 49, 21, 0, // Skip to: 6575 +/* 1150 */ MCD_OPC_Decode, 222, 18, 55, // Opcode: MULQ_S_W_MMR2 +/* 1154 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 1168 +/* 1159 */ MCD_OPC_CheckPredicate, 9, 35, 21, 0, // Skip to: 6575 +/* 1164 */ MCD_OPC_Decode, 235, 6, 62, // Opcode: APPEND_MMR2 +/* 1168 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 1182 +/* 1173 */ MCD_OPC_CheckPredicate, 9, 21, 21, 0, // Skip to: 6575 +/* 1178 */ MCD_OPC_Decode, 248, 19, 62, // Opcode: PREPEND_MMR2 +/* 1182 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 1196 +/* 1187 */ MCD_OPC_CheckPredicate, 8, 7, 21, 0, // Skip to: 6575 +/* 1192 */ MCD_OPC_Decode, 194, 17, 55, // Opcode: MODSUB_MM +/* 1196 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 1210 +/* 1201 */ MCD_OPC_CheckPredicate, 8, 249, 20, 0, // Skip to: 6575 +/* 1206 */ MCD_OPC_Decode, 183, 21, 61, // Opcode: SHRAV_R_W_MM +/* 1210 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 1224 +/* 1215 */ MCD_OPC_CheckPredicate, 9, 235, 20, 0, // Skip to: 6575 +/* 1220 */ MCD_OPC_Decode, 195, 21, 59, // Opcode: SHRLV_PH_MMR2 +/* 1224 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 1238 +/* 1229 */ MCD_OPC_CheckPredicate, 8, 221, 20, 0, // Skip to: 6575 +/* 1234 */ MCD_OPC_Decode, 197, 21, 59, // Opcode: SHRLV_QB_MM +/* 1238 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 1252 +/* 1243 */ MCD_OPC_CheckPredicate, 8, 207, 20, 0, // Skip to: 6575 +/* 1248 */ MCD_OPC_Decode, 161, 21, 59, // Opcode: SHLLV_QB_MM +/* 1252 */ MCD_OPC_FilterValue, 15, 198, 20, 0, // Skip to: 6575 +/* 1257 */ MCD_OPC_CheckPredicate, 8, 193, 20, 0, // Skip to: 6575 +/* 1262 */ MCD_OPC_Decode, 165, 21, 61, // Opcode: SHLLV_S_W_MM +/* 1266 */ MCD_OPC_FilterValue, 24, 45, 0, 0, // Skip to: 1316 +/* 1271 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1274 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1288 +/* 1279 */ MCD_OPC_CheckPredicate, 6, 171, 20, 0, // Skip to: 6575 +/* 1284 */ MCD_OPC_Decode, 234, 17, 63, // Opcode: MOVN_I_MM +/* 1288 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1302 +/* 1293 */ MCD_OPC_CheckPredicate, 6, 157, 20, 0, // Skip to: 6575 +/* 1298 */ MCD_OPC_Decode, 255, 17, 63, // Opcode: MOVZ_I_MM +/* 1302 */ MCD_OPC_FilterValue, 4, 148, 20, 0, // Skip to: 6575 +/* 1307 */ MCD_OPC_CheckPredicate, 7, 143, 20, 0, // Skip to: 6575 +/* 1312 */ MCD_OPC_Decode, 175, 16, 64, // Opcode: LWXS_MM +/* 1316 */ MCD_OPC_FilterValue, 29, 23, 0, 0, // Skip to: 1344 +/* 1321 */ MCD_OPC_CheckPredicate, 8, 129, 20, 0, // Skip to: 6575 +/* 1326 */ MCD_OPC_CheckField, 22, 4, 0, 122, 20, 0, // Skip to: 6575 +/* 1333 */ MCD_OPC_CheckField, 6, 8, 0, 115, 20, 0, // Skip to: 6575 +/* 1340 */ MCD_OPC_Decode, 157, 21, 65, // Opcode: SHILO_MM +/* 1344 */ MCD_OPC_FilterValue, 37, 73, 0, 0, // Skip to: 1422 +/* 1349 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1352 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1366 +/* 1357 */ MCD_OPC_CheckPredicate, 8, 93, 20, 0, // Skip to: 6575 +/* 1362 */ MCD_OPC_Decode, 208, 18, 54, // Opcode: MULEQ_S_W_PHL_MM +/* 1366 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1380 +/* 1371 */ MCD_OPC_CheckPredicate, 8, 79, 20, 0, // Skip to: 6575 +/* 1376 */ MCD_OPC_Decode, 210, 18, 54, // Opcode: MULEQ_S_W_PHR_MM +/* 1380 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 1394 +/* 1385 */ MCD_OPC_CheckPredicate, 8, 65, 20, 0, // Skip to: 6575 +/* 1390 */ MCD_OPC_Decode, 221, 15, 64, // Opcode: LHX_MM +/* 1394 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1408 +/* 1399 */ MCD_OPC_CheckPredicate, 8, 51, 20, 0, // Skip to: 6575 +/* 1404 */ MCD_OPC_Decode, 177, 16, 64, // Opcode: LWX_MM +/* 1408 */ MCD_OPC_FilterValue, 8, 42, 20, 0, // Skip to: 6575 +/* 1413 */ MCD_OPC_CheckPredicate, 8, 37, 20, 0, // Skip to: 6575 +/* 1418 */ MCD_OPC_Decode, 164, 15, 64, // Opcode: LBUX_MM +/* 1422 */ MCD_OPC_FilterValue, 44, 9, 0, 0, // Skip to: 1436 +/* 1427 */ MCD_OPC_CheckPredicate, 6, 23, 20, 0, // Skip to: 6575 +/* 1432 */ MCD_OPC_Decode, 255, 12, 66, // Opcode: EXT_MM +/* 1436 */ MCD_OPC_FilterValue, 45, 143, 0, 0, // Skip to: 1584 +/* 1441 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1444 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1458 +/* 1449 */ MCD_OPC_CheckPredicate, 9, 1, 20, 0, // Skip to: 6575 +/* 1454 */ MCD_OPC_Decode, 249, 18, 58, // Opcode: MUL_PH_MMR2 +/* 1458 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1472 +/* 1463 */ MCD_OPC_CheckPredicate, 9, 243, 19, 0, // Skip to: 6575 +/* 1468 */ MCD_OPC_Decode, 233, 19, 58, // Opcode: PRECR_QB_PH_MMR2 +/* 1472 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1486 +/* 1477 */ MCD_OPC_CheckPredicate, 8, 229, 19, 0, // Skip to: 6575 +/* 1482 */ MCD_OPC_Decode, 229, 19, 58, // Opcode: PRECRQ_QB_PH_MM +/* 1486 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 1500 +/* 1491 */ MCD_OPC_CheckPredicate, 8, 215, 19, 0, // Skip to: 6575 +/* 1496 */ MCD_OPC_Decode, 227, 19, 67, // Opcode: PRECRQ_PH_W_MM +/* 1500 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1514 +/* 1505 */ MCD_OPC_CheckPredicate, 8, 201, 19, 0, // Skip to: 6575 +/* 1510 */ MCD_OPC_Decode, 231, 19, 67, // Opcode: PRECRQ_RS_PH_W_MM +/* 1514 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 1528 +/* 1519 */ MCD_OPC_CheckPredicate, 8, 187, 19, 0, // Skip to: 6575 +/* 1524 */ MCD_OPC_Decode, 225, 19, 58, // Opcode: PRECRQU_S_QB_PH_MM +/* 1528 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1542 +/* 1533 */ MCD_OPC_CheckPredicate, 8, 173, 19, 0, // Skip to: 6575 +/* 1538 */ MCD_OPC_Decode, 180, 19, 58, // Opcode: PACKRL_PH_MM +/* 1542 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 1556 +/* 1547 */ MCD_OPC_CheckPredicate, 8, 159, 19, 0, // Skip to: 6575 +/* 1552 */ MCD_OPC_Decode, 200, 19, 58, // Opcode: PICK_QB_MM +/* 1556 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 1570 +/* 1561 */ MCD_OPC_CheckPredicate, 8, 145, 19, 0, // Skip to: 6575 +/* 1566 */ MCD_OPC_Decode, 198, 19, 58, // Opcode: PICK_PH_MM +/* 1570 */ MCD_OPC_FilterValue, 16, 136, 19, 0, // Skip to: 6575 +/* 1575 */ MCD_OPC_CheckPredicate, 9, 131, 19, 0, // Skip to: 6575 +/* 1580 */ MCD_OPC_Decode, 254, 18, 58, // Opcode: MUL_S_PH_MMR2 +/* 1584 */ MCD_OPC_FilterValue, 52, 45, 0, 0, // Skip to: 1634 +/* 1589 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1592 */ MCD_OPC_FilterValue, 19, 16, 0, 0, // Skip to: 1613 +/* 1597 */ MCD_OPC_CheckPredicate, 10, 109, 19, 0, // Skip to: 6575 +/* 1602 */ MCD_OPC_CheckField, 14, 2, 0, 102, 19, 0, // Skip to: 6575 +/* 1609 */ MCD_OPC_Decode, 149, 17, 68, // Opcode: MFHGC0_MM +/* 1613 */ MCD_OPC_FilterValue, 27, 93, 19, 0, // Skip to: 6575 +/* 1618 */ MCD_OPC_CheckPredicate, 10, 88, 19, 0, // Skip to: 6575 +/* 1623 */ MCD_OPC_CheckField, 14, 2, 0, 81, 19, 0, // Skip to: 6575 +/* 1630 */ MCD_OPC_Decode, 178, 18, 69, // Opcode: MTHGC0_MM +/* 1634 */ MCD_OPC_FilterValue, 53, 109, 0, 0, // Skip to: 1748 +/* 1639 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1642 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 1656 +/* 1647 */ MCD_OPC_CheckPredicate, 8, 59, 19, 0, // Skip to: 6575 +/* 1652 */ MCD_OPC_Decode, 193, 21, 52, // Opcode: SHRA_R_W_MM +/* 1656 */ MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 1677 +/* 1661 */ MCD_OPC_CheckPredicate, 8, 45, 19, 0, // Skip to: 6575 +/* 1666 */ MCD_OPC_CheckField, 11, 1, 0, 38, 19, 0, // Skip to: 6575 +/* 1673 */ MCD_OPC_Decode, 185, 21, 70, // Opcode: SHRA_PH_MM +/* 1677 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 1713 +/* 1682 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 1685 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1699 +/* 1690 */ MCD_OPC_CheckPredicate, 8, 16, 19, 0, // Skip to: 6575 +/* 1695 */ MCD_OPC_Decode, 167, 21, 70, // Opcode: SHLL_PH_MM +/* 1699 */ MCD_OPC_FilterValue, 1, 7, 19, 0, // Skip to: 6575 +/* 1704 */ MCD_OPC_CheckPredicate, 8, 2, 19, 0, // Skip to: 6575 +/* 1709 */ MCD_OPC_Decode, 171, 21, 70, // Opcode: SHLL_S_PH_MM +/* 1713 */ MCD_OPC_FilterValue, 15, 9, 0, 0, // Skip to: 1727 +/* 1718 */ MCD_OPC_CheckPredicate, 8, 244, 18, 0, // Skip to: 6575 +/* 1723 */ MCD_OPC_Decode, 173, 21, 52, // Opcode: SHLL_S_W_MM +/* 1727 */ MCD_OPC_FilterValue, 28, 235, 18, 0, // Skip to: 6575 +/* 1732 */ MCD_OPC_CheckPredicate, 8, 230, 18, 0, // Skip to: 6575 +/* 1737 */ MCD_OPC_CheckField, 11, 1, 0, 223, 18, 0, // Skip to: 6575 +/* 1744 */ MCD_OPC_Decode, 189, 21, 70, // Opcode: SHRA_R_PH_MM +/* 1748 */ MCD_OPC_FilterValue, 60, 8, 8, 0, // Skip to: 3809 +/* 1753 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1756 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 1792 +/* 1761 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 1764 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1778 +/* 1769 */ MCD_OPC_CheckPredicate, 7, 193, 18, 0, // Skip to: 6575 +/* 1774 */ MCD_OPC_Decode, 210, 23, 71, // Opcode: TEQ_MM +/* 1778 */ MCD_OPC_FilterValue, 1, 184, 18, 0, // Skip to: 6575 +/* 1783 */ MCD_OPC_CheckPredicate, 7, 179, 18, 0, // Skip to: 6575 +/* 1788 */ MCD_OPC_Decode, 128, 24, 71, // Opcode: TLT_MM +/* 1792 */ MCD_OPC_FilterValue, 1, 131, 0, 0, // Skip to: 1928 +/* 1797 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 1800 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 1850 +/* 1805 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1808 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1829 +/* 1813 */ MCD_OPC_CheckPredicate, 8, 149, 18, 0, // Skip to: 6575 +/* 1818 */ MCD_OPC_CheckField, 21, 5, 0, 142, 18, 0, // Skip to: 6575 +/* 1825 */ MCD_OPC_Decode, 154, 17, 72, // Opcode: MFHI_DSP_MM +/* 1829 */ MCD_OPC_FilterValue, 1, 133, 18, 0, // Skip to: 6575 +/* 1834 */ MCD_OPC_CheckPredicate, 8, 128, 18, 0, // Skip to: 6575 +/* 1839 */ MCD_OPC_CheckField, 21, 5, 0, 121, 18, 0, // Skip to: 6575 +/* 1846 */ MCD_OPC_Decode, 182, 18, 73, // Opcode: MTHI_DSP_MM +/* 1850 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1864 +/* 1855 */ MCD_OPC_CheckPredicate, 8, 107, 18, 0, // Skip to: 6575 +/* 1860 */ MCD_OPC_Decode, 169, 21, 74, // Opcode: SHLL_QB_MM +/* 1864 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 1914 +/* 1869 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1872 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1893 +/* 1877 */ MCD_OPC_CheckPredicate, 8, 85, 18, 0, // Skip to: 6575 +/* 1882 */ MCD_OPC_CheckField, 21, 5, 0, 78, 18, 0, // Skip to: 6575 +/* 1889 */ MCD_OPC_Decode, 160, 17, 72, // Opcode: MFLO_DSP_MM +/* 1893 */ MCD_OPC_FilterValue, 1, 69, 18, 0, // Skip to: 6575 +/* 1898 */ MCD_OPC_CheckPredicate, 8, 64, 18, 0, // Skip to: 6575 +/* 1903 */ MCD_OPC_CheckField, 21, 5, 0, 57, 18, 0, // Skip to: 6575 +/* 1910 */ MCD_OPC_Decode, 189, 18, 75, // Opcode: MTLO_DSP_MM +/* 1914 */ MCD_OPC_FilterValue, 3, 48, 18, 0, // Skip to: 6575 +/* 1919 */ MCD_OPC_CheckPredicate, 8, 43, 18, 0, // Skip to: 6575 +/* 1924 */ MCD_OPC_Decode, 201, 21, 74, // Opcode: SHRL_QB_MM +/* 1928 */ MCD_OPC_FilterValue, 2, 101, 0, 0, // Skip to: 2034 +/* 1933 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 1936 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1950 +/* 1941 */ MCD_OPC_CheckPredicate, 9, 21, 18, 0, // Skip to: 6575 +/* 1946 */ MCD_OPC_Decode, 157, 12, 76, // Opcode: DPA_W_PH_MMR2 +/* 1950 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1964 +/* 1955 */ MCD_OPC_CheckPredicate, 9, 7, 18, 0, // Skip to: 6575 +/* 1960 */ MCD_OPC_Decode, 153, 7, 77, // Opcode: BALIGN_MMR2 +/* 1964 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1978 +/* 1969 */ MCD_OPC_CheckPredicate, 9, 249, 17, 0, // Skip to: 6575 +/* 1974 */ MCD_OPC_Decode, 155, 12, 76, // Opcode: DPAX_W_PH_MMR2 +/* 1978 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1992 +/* 1983 */ MCD_OPC_CheckPredicate, 8, 235, 17, 0, // Skip to: 6575 +/* 1988 */ MCD_OPC_Decode, 151, 12, 76, // Opcode: DPAU_H_QBL_MM +/* 1992 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2006 +/* 1997 */ MCD_OPC_CheckPredicate, 8, 221, 17, 0, // Skip to: 6575 +/* 2002 */ MCD_OPC_Decode, 234, 12, 78, // Opcode: EXTPV_MM +/* 2006 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 2020 +/* 2011 */ MCD_OPC_CheckPredicate, 8, 207, 17, 0, // Skip to: 6575 +/* 2016 */ MCD_OPC_Decode, 153, 12, 76, // Opcode: DPAU_H_QBR_MM +/* 2020 */ MCD_OPC_FilterValue, 7, 198, 17, 0, // Skip to: 6575 +/* 2025 */ MCD_OPC_CheckPredicate, 8, 193, 17, 0, // Skip to: 6575 +/* 2030 */ MCD_OPC_Decode, 231, 12, 78, // Opcode: EXTPDPV_MM +/* 2034 */ MCD_OPC_FilterValue, 4, 171, 0, 0, // Skip to: 2210 +/* 2039 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 2042 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2056 +/* 2047 */ MCD_OPC_CheckPredicate, 9, 171, 17, 0, // Skip to: 6575 +/* 2052 */ MCD_OPC_Decode, 248, 5, 79, // Opcode: ABSQ_S_QB_MMR2 +/* 2056 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2070 +/* 2061 */ MCD_OPC_CheckPredicate, 8, 157, 17, 0, // Skip to: 6575 +/* 2066 */ MCD_OPC_Decode, 246, 5, 79, // Opcode: ABSQ_S_PH_MM +/* 2070 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2084 +/* 2075 */ MCD_OPC_CheckPredicate, 8, 143, 17, 0, // Skip to: 6575 +/* 2080 */ MCD_OPC_Decode, 250, 5, 80, // Opcode: ABSQ_S_W_MM +/* 2084 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 2098 +/* 2089 */ MCD_OPC_CheckPredicate, 8, 129, 17, 0, // Skip to: 6575 +/* 2094 */ MCD_OPC_Decode, 131, 8, 80, // Opcode: BITREV_MM +/* 2098 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 2112 +/* 2103 */ MCD_OPC_CheckPredicate, 8, 115, 17, 0, // Skip to: 6575 +/* 2108 */ MCD_OPC_Decode, 230, 14, 81, // Opcode: INSV_MM +/* 2112 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 2126 +/* 2117 */ MCD_OPC_CheckPredicate, 8, 101, 17, 0, // Skip to: 6575 +/* 2122 */ MCD_OPC_Decode, 213, 19, 82, // Opcode: PRECEQ_W_PHL_MM +/* 2126 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 2140 +/* 2131 */ MCD_OPC_CheckPredicate, 8, 87, 17, 0, // Skip to: 6575 +/* 2136 */ MCD_OPC_Decode, 215, 19, 82, // Opcode: PRECEQ_W_PHR_MM +/* 2140 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 2154 +/* 2145 */ MCD_OPC_CheckPredicate, 8, 73, 17, 0, // Skip to: 6575 +/* 2150 */ MCD_OPC_Decode, 207, 19, 79, // Opcode: PRECEQU_PH_QBL_MM +/* 2154 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 2168 +/* 2159 */ MCD_OPC_CheckPredicate, 8, 59, 17, 0, // Skip to: 6575 +/* 2164 */ MCD_OPC_Decode, 211, 19, 79, // Opcode: PRECEQU_PH_QBR_MM +/* 2168 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 2182 +/* 2173 */ MCD_OPC_CheckPredicate, 8, 45, 17, 0, // Skip to: 6575 +/* 2178 */ MCD_OPC_Decode, 219, 19, 79, // Opcode: PRECEU_PH_QBL_MM +/* 2182 */ MCD_OPC_FilterValue, 26, 9, 0, 0, // Skip to: 2196 +/* 2187 */ MCD_OPC_CheckPredicate, 8, 31, 17, 0, // Skip to: 6575 +/* 2192 */ MCD_OPC_Decode, 223, 19, 79, // Opcode: PRECEU_PH_QBR_MM +/* 2196 */ MCD_OPC_FilterValue, 30, 22, 17, 0, // Skip to: 6575 +/* 2201 */ MCD_OPC_CheckPredicate, 8, 17, 17, 0, // Skip to: 6575 +/* 2206 */ MCD_OPC_Decode, 252, 19, 82, // Opcode: RADDU_W_QB_MM +/* 2210 */ MCD_OPC_FilterValue, 5, 87, 0, 0, // Skip to: 2302 +/* 2215 */ MCD_OPC_ExtractField, 11, 15, // Inst{25-11} ... +/* 2218 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2232 +/* 2223 */ MCD_OPC_CheckPredicate, 10, 251, 16, 0, // Skip to: 6575 +/* 2228 */ MCD_OPC_Decode, 225, 23, 10, // Opcode: TLBGP_MM +/* 2232 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2246 +/* 2237 */ MCD_OPC_CheckPredicate, 10, 237, 16, 0, // Skip to: 6575 +/* 2242 */ MCD_OPC_Decode, 227, 23, 10, // Opcode: TLBGR_MM +/* 2246 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2260 +/* 2251 */ MCD_OPC_CheckPredicate, 10, 223, 16, 0, // Skip to: 6575 +/* 2256 */ MCD_OPC_Decode, 229, 23, 10, // Opcode: TLBGWI_MM +/* 2260 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 2274 +/* 2265 */ MCD_OPC_CheckPredicate, 10, 209, 16, 0, // Skip to: 6575 +/* 2270 */ MCD_OPC_Decode, 231, 23, 10, // Opcode: TLBGWR_MM +/* 2274 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 2288 +/* 2279 */ MCD_OPC_CheckPredicate, 10, 195, 16, 0, // Skip to: 6575 +/* 2284 */ MCD_OPC_Decode, 223, 23, 10, // Opcode: TLBGINV_MM +/* 2288 */ MCD_OPC_FilterValue, 10, 186, 16, 0, // Skip to: 6575 +/* 2293 */ MCD_OPC_CheckPredicate, 10, 181, 16, 0, // Skip to: 6575 +/* 2298 */ MCD_OPC_Decode, 222, 23, 10, // Opcode: TLBGINVF_MM +/* 2302 */ MCD_OPC_FilterValue, 7, 31, 0, 0, // Skip to: 2338 +/* 2307 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 2310 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2324 +/* 2315 */ MCD_OPC_CheckPredicate, 9, 159, 16, 0, // Skip to: 6575 +/* 2320 */ MCD_OPC_Decode, 187, 21, 74, // Opcode: SHRA_QB_MMR2 +/* 2324 */ MCD_OPC_FilterValue, 2, 150, 16, 0, // Skip to: 6575 +/* 2329 */ MCD_OPC_CheckPredicate, 9, 145, 16, 0, // Skip to: 6575 +/* 2334 */ MCD_OPC_Decode, 191, 21, 74, // Opcode: SHRA_R_QB_MMR2 +/* 2338 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 2374 +/* 2343 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 2346 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2360 +/* 2351 */ MCD_OPC_CheckPredicate, 7, 123, 16, 0, // Skip to: 6575 +/* 2356 */ MCD_OPC_Decode, 219, 23, 71, // Opcode: TGE_MM +/* 2360 */ MCD_OPC_FilterValue, 1, 114, 16, 0, // Skip to: 6575 +/* 2365 */ MCD_OPC_CheckPredicate, 7, 109, 16, 0, // Skip to: 6575 +/* 2370 */ MCD_OPC_Decode, 255, 23, 71, // Opcode: TLTU_MM +/* 2374 */ MCD_OPC_FilterValue, 9, 101, 0, 0, // Skip to: 2480 +/* 2379 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 2382 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2403 +/* 2387 */ MCD_OPC_CheckPredicate, 8, 87, 16, 0, // Skip to: 6575 +/* 2392 */ MCD_OPC_CheckField, 21, 5, 0, 80, 16, 0, // Skip to: 6575 +/* 2399 */ MCD_OPC_Decode, 185, 18, 83, // Opcode: MTHLIP_MM +/* 2403 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2417 +/* 2408 */ MCD_OPC_CheckPredicate, 8, 66, 16, 0, // Skip to: 6575 +/* 2413 */ MCD_OPC_Decode, 227, 16, 76, // Opcode: MAQ_S_W_PHR_MM +/* 2417 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 2438 +/* 2422 */ MCD_OPC_CheckPredicate, 8, 52, 16, 0, // Skip to: 6575 +/* 2427 */ MCD_OPC_CheckField, 21, 5, 0, 45, 16, 0, // Skip to: 6575 +/* 2434 */ MCD_OPC_Decode, 156, 21, 83, // Opcode: SHILOV_MM +/* 2438 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 2452 +/* 2443 */ MCD_OPC_CheckPredicate, 8, 31, 16, 0, // Skip to: 6575 +/* 2448 */ MCD_OPC_Decode, 225, 16, 76, // Opcode: MAQ_S_W_PHL_MM +/* 2452 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2466 +/* 2457 */ MCD_OPC_CheckPredicate, 8, 17, 16, 0, // Skip to: 6575 +/* 2462 */ MCD_OPC_Decode, 223, 16, 76, // Opcode: MAQ_SA_W_PHR_MM +/* 2466 */ MCD_OPC_FilterValue, 7, 8, 16, 0, // Skip to: 6575 +/* 2471 */ MCD_OPC_CheckPredicate, 8, 3, 16, 0, // Skip to: 6575 +/* 2476 */ MCD_OPC_Decode, 221, 16, 76, // Opcode: MAQ_SA_W_PHL_MM +/* 2480 */ MCD_OPC_FilterValue, 10, 115, 0, 0, // Skip to: 2600 +/* 2485 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 2488 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2502 +/* 2493 */ MCD_OPC_CheckPredicate, 8, 237, 15, 0, // Skip to: 6575 +/* 2498 */ MCD_OPC_Decode, 149, 12, 76, // Opcode: DPAQ_S_W_PH_MM +/* 2502 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2516 +/* 2507 */ MCD_OPC_CheckPredicate, 8, 223, 15, 0, // Skip to: 6575 +/* 2512 */ MCD_OPC_Decode, 214, 16, 76, // Opcode: MADD_DSP_MM +/* 2516 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2530 +/* 2521 */ MCD_OPC_CheckPredicate, 8, 209, 15, 0, // Skip to: 6575 +/* 2526 */ MCD_OPC_Decode, 147, 12, 76, // Opcode: DPAQ_SA_L_W_MM +/* 2530 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 2544 +/* 2535 */ MCD_OPC_CheckPredicate, 8, 195, 15, 0, // Skip to: 6575 +/* 2540 */ MCD_OPC_Decode, 204, 16, 76, // Opcode: MADDU_DSP_MM +/* 2544 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2558 +/* 2549 */ MCD_OPC_CheckPredicate, 9, 181, 15, 0, // Skip to: 6575 +/* 2554 */ MCD_OPC_Decode, 145, 12, 76, // Opcode: DPAQX_S_W_PH_MMR2 +/* 2558 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2572 +/* 2563 */ MCD_OPC_CheckPredicate, 8, 167, 15, 0, // Skip to: 6575 +/* 2568 */ MCD_OPC_Decode, 150, 18, 76, // Opcode: MSUB_DSP_MM +/* 2572 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 2586 +/* 2577 */ MCD_OPC_CheckPredicate, 9, 153, 15, 0, // Skip to: 6575 +/* 2582 */ MCD_OPC_Decode, 143, 12, 76, // Opcode: DPAQX_SA_W_PH_MMR2 +/* 2586 */ MCD_OPC_FilterValue, 7, 144, 15, 0, // Skip to: 6575 +/* 2591 */ MCD_OPC_CheckPredicate, 8, 139, 15, 0, // Skip to: 6575 +/* 2596 */ MCD_OPC_Decode, 140, 18, 76, // Opcode: MSUBU_DSP_MM +/* 2600 */ MCD_OPC_FilterValue, 12, 27, 1, 0, // Skip to: 2888 +/* 2605 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 2608 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2622 +/* 2613 */ MCD_OPC_CheckPredicate, 8, 117, 15, 0, // Skip to: 6575 +/* 2618 */ MCD_OPC_Decode, 141, 20, 84, // Opcode: REPLV_PH_MM +/* 2622 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2636 +/* 2627 */ MCD_OPC_CheckPredicate, 8, 103, 15, 0, // Skip to: 6575 +/* 2632 */ MCD_OPC_Decode, 143, 20, 84, // Opcode: REPLV_QB_MM +/* 2636 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2650 +/* 2641 */ MCD_OPC_CheckPredicate, 7, 89, 15, 0, // Skip to: 6575 +/* 2646 */ MCD_OPC_Decode, 244, 20, 80, // Opcode: SEB_MM +/* 2650 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 2664 +/* 2655 */ MCD_OPC_CheckPredicate, 7, 75, 15, 0, // Skip to: 6575 +/* 2660 */ MCD_OPC_Decode, 248, 20, 80, // Opcode: SEH_MM +/* 2664 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 2678 +/* 2669 */ MCD_OPC_CheckPredicate, 7, 61, 15, 0, // Skip to: 6575 +/* 2674 */ MCD_OPC_Decode, 173, 9, 80, // Opcode: CLO_MM +/* 2678 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 2692 +/* 2683 */ MCD_OPC_CheckPredicate, 7, 47, 15, 0, // Skip to: 6575 +/* 2688 */ MCD_OPC_Decode, 194, 9, 80, // Opcode: CLZ_MM +/* 2692 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 2706 +/* 2697 */ MCD_OPC_CheckPredicate, 6, 33, 15, 0, // Skip to: 6575 +/* 2702 */ MCD_OPC_Decode, 129, 20, 85, // Opcode: RDHWR_MM +/* 2706 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 2720 +/* 2711 */ MCD_OPC_CheckPredicate, 8, 19, 15, 0, // Skip to: 6575 +/* 2716 */ MCD_OPC_Decode, 206, 19, 79, // Opcode: PRECEQU_PH_QBLA_MM +/* 2720 */ MCD_OPC_FilterValue, 15, 9, 0, 0, // Skip to: 2734 +/* 2725 */ MCD_OPC_CheckPredicate, 7, 5, 15, 0, // Skip to: 6575 +/* 2730 */ MCD_OPC_Decode, 170, 24, 80, // Opcode: WSBH_MM +/* 2734 */ MCD_OPC_FilterValue, 17, 9, 0, 0, // Skip to: 2748 +/* 2739 */ MCD_OPC_CheckPredicate, 6, 247, 14, 0, // Skip to: 6575 +/* 2744 */ MCD_OPC_Decode, 235, 18, 86, // Opcode: MULT_MM +/* 2748 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 2762 +/* 2753 */ MCD_OPC_CheckPredicate, 8, 233, 14, 0, // Skip to: 6575 +/* 2758 */ MCD_OPC_Decode, 210, 19, 79, // Opcode: PRECEQU_PH_QBRA_MM +/* 2762 */ MCD_OPC_FilterValue, 19, 9, 0, 0, // Skip to: 2776 +/* 2767 */ MCD_OPC_CheckPredicate, 6, 219, 14, 0, // Skip to: 6575 +/* 2772 */ MCD_OPC_Decode, 237, 18, 86, // Opcode: MULTu_MM +/* 2776 */ MCD_OPC_FilterValue, 21, 9, 0, 0, // Skip to: 2790 +/* 2781 */ MCD_OPC_CheckPredicate, 6, 205, 14, 0, // Skip to: 6575 +/* 2786 */ MCD_OPC_Decode, 237, 20, 86, // Opcode: SDIV_MM +/* 2790 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 2804 +/* 2795 */ MCD_OPC_CheckPredicate, 8, 191, 14, 0, // Skip to: 6575 +/* 2800 */ MCD_OPC_Decode, 218, 19, 79, // Opcode: PRECEU_PH_QBLA_MM +/* 2804 */ MCD_OPC_FilterValue, 23, 9, 0, 0, // Skip to: 2818 +/* 2809 */ MCD_OPC_CheckPredicate, 6, 177, 14, 0, // Skip to: 6575 +/* 2814 */ MCD_OPC_Decode, 153, 24, 86, // Opcode: UDIV_MM +/* 2818 */ MCD_OPC_FilterValue, 25, 9, 0, 0, // Skip to: 2832 +/* 2823 */ MCD_OPC_CheckPredicate, 6, 163, 14, 0, // Skip to: 6575 +/* 2828 */ MCD_OPC_Decode, 215, 16, 86, // Opcode: MADD_MM +/* 2832 */ MCD_OPC_FilterValue, 26, 9, 0, 0, // Skip to: 2846 +/* 2837 */ MCD_OPC_CheckPredicate, 8, 149, 14, 0, // Skip to: 6575 +/* 2842 */ MCD_OPC_Decode, 222, 19, 79, // Opcode: PRECEU_PH_QBRA_MM +/* 2846 */ MCD_OPC_FilterValue, 27, 9, 0, 0, // Skip to: 2860 +/* 2851 */ MCD_OPC_CheckPredicate, 6, 135, 14, 0, // Skip to: 6575 +/* 2856 */ MCD_OPC_Decode, 205, 16, 86, // Opcode: MADDU_MM +/* 2860 */ MCD_OPC_FilterValue, 29, 9, 0, 0, // Skip to: 2874 +/* 2865 */ MCD_OPC_CheckPredicate, 6, 121, 14, 0, // Skip to: 6575 +/* 2870 */ MCD_OPC_Decode, 151, 18, 86, // Opcode: MSUB_MM +/* 2874 */ MCD_OPC_FilterValue, 31, 112, 14, 0, // Skip to: 6575 +/* 2879 */ MCD_OPC_CheckPredicate, 6, 107, 14, 0, // Skip to: 6575 +/* 2884 */ MCD_OPC_Decode, 141, 18, 86, // Opcode: MSUBU_MM +/* 2888 */ MCD_OPC_FilterValue, 13, 206, 0, 0, // Skip to: 3099 +/* 2893 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 2896 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2917 +/* 2901 */ MCD_OPC_CheckPredicate, 7, 85, 14, 0, // Skip to: 6575 +/* 2906 */ MCD_OPC_CheckField, 16, 10, 0, 78, 14, 0, // Skip to: 6575 +/* 2913 */ MCD_OPC_Decode, 239, 23, 10, // Opcode: TLBP_MM +/* 2917 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 2938 +/* 2922 */ MCD_OPC_CheckPredicate, 7, 64, 14, 0, // Skip to: 6575 +/* 2927 */ MCD_OPC_CheckField, 16, 10, 0, 57, 14, 0, // Skip to: 6575 +/* 2934 */ MCD_OPC_Decode, 242, 23, 10, // Opcode: TLBR_MM +/* 2938 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 2959 +/* 2943 */ MCD_OPC_CheckPredicate, 7, 43, 14, 0, // Skip to: 6575 +/* 2948 */ MCD_OPC_CheckField, 16, 10, 0, 36, 14, 0, // Skip to: 6575 +/* 2955 */ MCD_OPC_Decode, 245, 23, 10, // Opcode: TLBWI_MM +/* 2959 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 2980 +/* 2964 */ MCD_OPC_CheckPredicate, 7, 22, 14, 0, // Skip to: 6575 +/* 2969 */ MCD_OPC_CheckField, 16, 10, 0, 15, 14, 0, // Skip to: 6575 +/* 2976 */ MCD_OPC_Decode, 248, 23, 10, // Opcode: TLBWR_MM +/* 2980 */ MCD_OPC_FilterValue, 13, 16, 0, 0, // Skip to: 3001 +/* 2985 */ MCD_OPC_CheckPredicate, 7, 1, 14, 0, // Skip to: 6575 +/* 2990 */ MCD_OPC_CheckField, 21, 5, 0, 250, 13, 0, // Skip to: 6575 +/* 2997 */ MCD_OPC_Decode, 179, 23, 87, // Opcode: SYNC_MM +/* 3001 */ MCD_OPC_FilterValue, 17, 9, 0, 0, // Skip to: 3015 +/* 3006 */ MCD_OPC_CheckPredicate, 7, 236, 13, 0, // Skip to: 6575 +/* 3011 */ MCD_OPC_Decode, 184, 23, 88, // Opcode: SYSCALL_MM +/* 3015 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 3029 +/* 3020 */ MCD_OPC_CheckPredicate, 7, 222, 13, 0, // Skip to: 6575 +/* 3025 */ MCD_OPC_Decode, 162, 24, 88, // Opcode: WAIT_MM +/* 3029 */ MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 3043 +/* 3034 */ MCD_OPC_CheckPredicate, 10, 208, 13, 0, // Skip to: 6575 +/* 3039 */ MCD_OPC_Decode, 203, 14, 88, // Opcode: HYPCALL_MM +/* 3043 */ MCD_OPC_FilterValue, 27, 9, 0, 0, // Skip to: 3057 +/* 3048 */ MCD_OPC_CheckPredicate, 7, 194, 13, 0, // Skip to: 6575 +/* 3053 */ MCD_OPC_Decode, 223, 20, 88, // Opcode: SDBBP_MM +/* 3057 */ MCD_OPC_FilterValue, 28, 16, 0, 0, // Skip to: 3078 +/* 3062 */ MCD_OPC_CheckPredicate, 7, 180, 13, 0, // Skip to: 6575 +/* 3067 */ MCD_OPC_CheckField, 16, 10, 0, 173, 13, 0, // Skip to: 6575 +/* 3074 */ MCD_OPC_Decode, 207, 11, 10, // Opcode: DERET_MM +/* 3078 */ MCD_OPC_FilterValue, 30, 164, 13, 0, // Skip to: 6575 +/* 3083 */ MCD_OPC_CheckPredicate, 7, 159, 13, 0, // Skip to: 6575 +/* 3088 */ MCD_OPC_CheckField, 16, 10, 0, 152, 13, 0, // Skip to: 6575 +/* 3095 */ MCD_OPC_Decode, 220, 12, 10, // Opcode: ERET_MM +/* 3099 */ MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 3120 +/* 3104 */ MCD_OPC_CheckPredicate, 9, 138, 13, 0, // Skip to: 6575 +/* 3109 */ MCD_OPC_CheckField, 11, 1, 0, 131, 13, 0, // Skip to: 6575 +/* 3116 */ MCD_OPC_Decode, 199, 21, 70, // Opcode: SHRL_PH_MMR2 +/* 3120 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 3156 +/* 3125 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 3128 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3142 +/* 3133 */ MCD_OPC_CheckPredicate, 7, 109, 13, 0, // Skip to: 6575 +/* 3138 */ MCD_OPC_Decode, 218, 23, 71, // Opcode: TGEU_MM +/* 3142 */ MCD_OPC_FilterValue, 1, 100, 13, 0, // Skip to: 6575 +/* 3147 */ MCD_OPC_CheckPredicate, 7, 95, 13, 0, // Skip to: 6575 +/* 3152 */ MCD_OPC_Decode, 132, 24, 71, // Opcode: TNE_MM +/* 3156 */ MCD_OPC_FilterValue, 18, 115, 0, 0, // Skip to: 3276 +/* 3161 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 3164 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3178 +/* 3169 */ MCD_OPC_CheckPredicate, 9, 73, 13, 0, // Skip to: 6575 +/* 3174 */ MCD_OPC_Decode, 180, 12, 76, // Opcode: DPS_W_PH_MMR2 +/* 3178 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3192 +/* 3183 */ MCD_OPC_CheckPredicate, 8, 59, 13, 0, // Skip to: 6575 +/* 3188 */ MCD_OPC_Decode, 234, 18, 89, // Opcode: MULT_DSP_MM +/* 3192 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3206 +/* 3197 */ MCD_OPC_CheckPredicate, 9, 45, 13, 0, // Skip to: 6575 +/* 3202 */ MCD_OPC_Decode, 178, 12, 76, // Opcode: DPSX_W_PH_MMR2 +/* 3206 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3220 +/* 3211 */ MCD_OPC_CheckPredicate, 8, 31, 13, 0, // Skip to: 6575 +/* 3216 */ MCD_OPC_Decode, 232, 18, 89, // Opcode: MULTU_DSP_MM +/* 3220 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3234 +/* 3225 */ MCD_OPC_CheckPredicate, 8, 17, 13, 0, // Skip to: 6575 +/* 3230 */ MCD_OPC_Decode, 174, 12, 76, // Opcode: DPSU_H_QBL_MM +/* 3234 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 3248 +/* 3239 */ MCD_OPC_CheckPredicate, 9, 3, 13, 0, // Skip to: 6575 +/* 3244 */ MCD_OPC_Decode, 229, 18, 76, // Opcode: MULSA_W_PH_MMR2 +/* 3248 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 3262 +/* 3253 */ MCD_OPC_CheckPredicate, 8, 245, 12, 0, // Skip to: 6575 +/* 3258 */ MCD_OPC_Decode, 176, 12, 76, // Opcode: DPSU_H_QBR_MM +/* 3262 */ MCD_OPC_FilterValue, 7, 236, 12, 0, // Skip to: 6575 +/* 3267 */ MCD_OPC_CheckPredicate, 8, 231, 12, 0, // Skip to: 6575 +/* 3272 */ MCD_OPC_Decode, 227, 18, 76, // Opcode: MULSAQ_S_W_PH_MM +/* 3276 */ MCD_OPC_FilterValue, 19, 16, 0, 0, // Skip to: 3297 +/* 3281 */ MCD_OPC_CheckPredicate, 10, 217, 12, 0, // Skip to: 6575 +/* 3286 */ MCD_OPC_CheckField, 14, 2, 0, 210, 12, 0, // Skip to: 6575 +/* 3293 */ MCD_OPC_Decode, 139, 17, 68, // Opcode: MFGC0_MM +/* 3297 */ MCD_OPC_FilterValue, 20, 31, 0, 0, // Skip to: 3333 +/* 3302 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 3305 */ MCD_OPC_FilterValue, 25, 9, 0, 0, // Skip to: 3319 +/* 3310 */ MCD_OPC_CheckPredicate, 7, 188, 12, 0, // Skip to: 6575 +/* 3315 */ MCD_OPC_Decode, 146, 9, 90, // Opcode: CFC2_MM +/* 3319 */ MCD_OPC_FilterValue, 27, 179, 12, 0, // Skip to: 6575 +/* 3324 */ MCD_OPC_CheckPredicate, 7, 174, 12, 0, // Skip to: 6575 +/* 3329 */ MCD_OPC_Decode, 181, 10, 91, // Opcode: CTC2_MM +/* 3333 */ MCD_OPC_FilterValue, 21, 87, 0, 0, // Skip to: 3425 +/* 3338 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 3341 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 3362 +/* 3346 */ MCD_OPC_CheckPredicate, 6, 152, 12, 0, // Skip to: 6575 +/* 3351 */ MCD_OPC_CheckField, 21, 5, 0, 145, 12, 0, // Skip to: 6575 +/* 3358 */ MCD_OPC_Decode, 155, 17, 92, // Opcode: MFHI_MM +/* 3362 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 3383 +/* 3367 */ MCD_OPC_CheckPredicate, 6, 131, 12, 0, // Skip to: 6575 +/* 3372 */ MCD_OPC_CheckField, 21, 5, 0, 124, 12, 0, // Skip to: 6575 +/* 3379 */ MCD_OPC_Decode, 161, 17, 92, // Opcode: MFLO_MM +/* 3383 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 3404 +/* 3388 */ MCD_OPC_CheckPredicate, 6, 110, 12, 0, // Skip to: 6575 +/* 3393 */ MCD_OPC_CheckField, 21, 5, 0, 103, 12, 0, // Skip to: 6575 +/* 3400 */ MCD_OPC_Decode, 183, 18, 92, // Opcode: MTHI_MM +/* 3404 */ MCD_OPC_FilterValue, 7, 94, 12, 0, // Skip to: 6575 +/* 3409 */ MCD_OPC_CheckPredicate, 6, 89, 12, 0, // Skip to: 6575 +/* 3414 */ MCD_OPC_CheckField, 21, 5, 0, 82, 12, 0, // Skip to: 6575 +/* 3421 */ MCD_OPC_Decode, 190, 18, 92, // Opcode: MTLO_MM +/* 3425 */ MCD_OPC_FilterValue, 23, 16, 0, 0, // Skip to: 3446 +/* 3430 */ MCD_OPC_CheckPredicate, 8, 68, 12, 0, // Skip to: 6575 +/* 3435 */ MCD_OPC_CheckField, 11, 2, 0, 61, 12, 0, // Skip to: 6575 +/* 3442 */ MCD_OPC_Decode, 147, 20, 93, // Opcode: REPL_QB_MM +/* 3446 */ MCD_OPC_FilterValue, 25, 115, 0, 0, // Skip to: 3566 +/* 3451 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 3454 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3468 +/* 3459 */ MCD_OPC_CheckPredicate, 8, 39, 12, 0, // Skip to: 6575 +/* 3464 */ MCD_OPC_Decode, 254, 19, 94, // Opcode: RDDSP_MM +/* 3468 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3482 +/* 3473 */ MCD_OPC_CheckPredicate, 8, 25, 12, 0, // Skip to: 6575 +/* 3478 */ MCD_OPC_Decode, 251, 12, 95, // Opcode: EXTR_W_MM +/* 3482 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3496 +/* 3487 */ MCD_OPC_CheckPredicate, 8, 11, 12, 0, // Skip to: 6575 +/* 3492 */ MCD_OPC_Decode, 166, 24, 94, // Opcode: WRDSP_MM +/* 3496 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3510 +/* 3501 */ MCD_OPC_CheckPredicate, 8, 253, 11, 0, // Skip to: 6575 +/* 3506 */ MCD_OPC_Decode, 247, 12, 95, // Opcode: EXTR_R_W_MM +/* 3510 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3524 +/* 3515 */ MCD_OPC_CheckPredicate, 8, 239, 11, 0, // Skip to: 6575 +/* 3520 */ MCD_OPC_Decode, 235, 12, 95, // Opcode: EXTP_MM +/* 3524 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 3538 +/* 3529 */ MCD_OPC_CheckPredicate, 8, 225, 11, 0, // Skip to: 6575 +/* 3534 */ MCD_OPC_Decode, 245, 12, 95, // Opcode: EXTR_RS_W_MM +/* 3538 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 3552 +/* 3543 */ MCD_OPC_CheckPredicate, 8, 211, 11, 0, // Skip to: 6575 +/* 3548 */ MCD_OPC_Decode, 232, 12, 95, // Opcode: EXTPDP_MM +/* 3552 */ MCD_OPC_FilterValue, 7, 202, 11, 0, // Skip to: 6575 +/* 3557 */ MCD_OPC_CheckPredicate, 8, 197, 11, 0, // Skip to: 6575 +/* 3562 */ MCD_OPC_Decode, 249, 12, 95, // Opcode: EXTR_S_H_MM +/* 3566 */ MCD_OPC_FilterValue, 26, 115, 0, 0, // Skip to: 3686 +/* 3571 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 3574 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3588 +/* 3579 */ MCD_OPC_CheckPredicate, 8, 175, 11, 0, // Skip to: 6575 +/* 3584 */ MCD_OPC_Decode, 166, 12, 76, // Opcode: DPSQ_S_W_PH_MM +/* 3588 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3602 +/* 3593 */ MCD_OPC_CheckPredicate, 8, 161, 11, 0, // Skip to: 6575 +/* 3598 */ MCD_OPC_Decode, 243, 12, 78, // Opcode: EXTRV_W_MM +/* 3602 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3616 +/* 3607 */ MCD_OPC_CheckPredicate, 8, 147, 11, 0, // Skip to: 6575 +/* 3612 */ MCD_OPC_Decode, 164, 12, 76, // Opcode: DPSQ_SA_L_W_MM +/* 3616 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3630 +/* 3621 */ MCD_OPC_CheckPredicate, 8, 133, 11, 0, // Skip to: 6575 +/* 3626 */ MCD_OPC_Decode, 239, 12, 78, // Opcode: EXTRV_R_W_MM +/* 3630 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3644 +/* 3635 */ MCD_OPC_CheckPredicate, 9, 119, 11, 0, // Skip to: 6575 +/* 3640 */ MCD_OPC_Decode, 162, 12, 76, // Opcode: DPSQX_S_W_PH_MMR2 +/* 3644 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 3658 +/* 3649 */ MCD_OPC_CheckPredicate, 8, 105, 11, 0, // Skip to: 6575 +/* 3654 */ MCD_OPC_Decode, 237, 12, 78, // Opcode: EXTRV_RS_W_MM +/* 3658 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 3672 +/* 3663 */ MCD_OPC_CheckPredicate, 9, 91, 11, 0, // Skip to: 6575 +/* 3668 */ MCD_OPC_Decode, 160, 12, 76, // Opcode: DPSQX_SA_W_PH_MMR2 +/* 3672 */ MCD_OPC_FilterValue, 7, 82, 11, 0, // Skip to: 6575 +/* 3677 */ MCD_OPC_CheckPredicate, 8, 77, 11, 0, // Skip to: 6575 +/* 3682 */ MCD_OPC_Decode, 241, 12, 78, // Opcode: EXTRV_S_H_MM +/* 3686 */ MCD_OPC_FilterValue, 27, 16, 0, 0, // Skip to: 3707 +/* 3691 */ MCD_OPC_CheckPredicate, 10, 63, 11, 0, // Skip to: 6575 +/* 3696 */ MCD_OPC_CheckField, 14, 2, 0, 56, 11, 0, // Skip to: 6575 +/* 3703 */ MCD_OPC_Decode, 168, 18, 69, // Opcode: MTGC0_MM +/* 3707 */ MCD_OPC_FilterValue, 28, 47, 0, 0, // Skip to: 3759 +/* 3712 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 3715 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 3745 +/* 3720 */ MCD_OPC_CheckPredicate, 6, 11, 0, 0, // Skip to: 3736 +/* 3725 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 3736 +/* 3732 */ MCD_OPC_Decode, 144, 15, 92, // Opcode: JR_MM +/* 3736 */ MCD_OPC_CheckPredicate, 6, 18, 11, 0, // Skip to: 6575 +/* 3741 */ MCD_OPC_Decode, 249, 14, 80, // Opcode: JALR_MM +/* 3745 */ MCD_OPC_FilterValue, 9, 9, 11, 0, // Skip to: 6575 +/* 3750 */ MCD_OPC_CheckPredicate, 6, 4, 11, 0, // Skip to: 6575 +/* 3755 */ MCD_OPC_Decode, 246, 14, 80, // Opcode: JALRS_MM +/* 3759 */ MCD_OPC_FilterValue, 29, 251, 10, 0, // Skip to: 6575 +/* 3764 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 3767 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 3788 +/* 3772 */ MCD_OPC_CheckPredicate, 7, 238, 10, 0, // Skip to: 6575 +/* 3777 */ MCD_OPC_CheckField, 21, 5, 0, 231, 10, 0, // Skip to: 6575 +/* 3784 */ MCD_OPC_Decode, 232, 11, 92, // Opcode: DI_MM +/* 3788 */ MCD_OPC_FilterValue, 10, 222, 10, 0, // Skip to: 6575 +/* 3793 */ MCD_OPC_CheckPredicate, 7, 217, 10, 0, // Skip to: 6575 +/* 3798 */ MCD_OPC_CheckField, 21, 5, 0, 210, 10, 0, // Skip to: 6575 +/* 3805 */ MCD_OPC_Decode, 211, 12, 92, // Opcode: EI_MM +/* 3809 */ MCD_OPC_FilterValue, 61, 201, 10, 0, // Skip to: 6575 +/* 3814 */ MCD_OPC_CheckPredicate, 8, 196, 10, 0, // Skip to: 6575 +/* 3819 */ MCD_OPC_CheckField, 6, 5, 0, 189, 10, 0, // Skip to: 6575 +/* 3826 */ MCD_OPC_Decode, 145, 20, 96, // Opcode: REPL_PH_MM +/* 3830 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3844 +/* 3835 */ MCD_OPC_CheckPredicate, 6, 175, 10, 0, // Skip to: 6575 +/* 3840 */ MCD_OPC_Decode, 203, 6, 97, // Opcode: ADDi_MM +/* 3844 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 3858 +/* 3849 */ MCD_OPC_CheckPredicate, 7, 161, 10, 0, // Skip to: 6575 +/* 3854 */ MCD_OPC_Decode, 178, 15, 98, // Opcode: LBu_MM +/* 3858 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 3872 +/* 3863 */ MCD_OPC_CheckPredicate, 7, 147, 10, 0, // Skip to: 6575 +/* 3868 */ MCD_OPC_Decode, 202, 20, 98, // Opcode: SB_MM +/* 3872 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 3886 +/* 3877 */ MCD_OPC_CheckPredicate, 7, 133, 10, 0, // Skip to: 6575 +/* 3882 */ MCD_OPC_Decode, 170, 15, 98, // Opcode: LB_MM +/* 3886 */ MCD_OPC_FilterValue, 8, 73, 0, 0, // Skip to: 3964 +/* 3891 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 3894 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3908 +/* 3899 */ MCD_OPC_CheckPredicate, 7, 111, 10, 0, // Skip to: 6575 +/* 3904 */ MCD_OPC_Decode, 161, 16, 99, // Opcode: LWP_MM +/* 3908 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 3922 +/* 3913 */ MCD_OPC_CheckPredicate, 7, 97, 10, 0, // Skip to: 6575 +/* 3918 */ MCD_OPC_Decode, 156, 16, 99, // Opcode: LWM32_MM +/* 3922 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 3936 +/* 3927 */ MCD_OPC_CheckPredicate, 6, 83, 10, 0, // Skip to: 6575 +/* 3932 */ MCD_OPC_Decode, 249, 8, 100, // Opcode: CACHE_MM +/* 3936 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 3950 +/* 3941 */ MCD_OPC_CheckPredicate, 7, 69, 10, 0, // Skip to: 6575 +/* 3946 */ MCD_OPC_Decode, 156, 23, 99, // Opcode: SWP_MM +/* 3950 */ MCD_OPC_FilterValue, 13, 60, 10, 0, // Skip to: 6575 +/* 3955 */ MCD_OPC_CheckPredicate, 7, 55, 10, 0, // Skip to: 6575 +/* 3960 */ MCD_OPC_Decode, 153, 23, 99, // Opcode: SWM32_MM +/* 3964 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 3978 +/* 3969 */ MCD_OPC_CheckPredicate, 6, 41, 10, 0, // Skip to: 6575 +/* 3974 */ MCD_OPC_Decode, 205, 6, 97, // Opcode: ADDiu_MM +/* 3978 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 3992 +/* 3983 */ MCD_OPC_CheckPredicate, 7, 27, 10, 0, // Skip to: 6575 +/* 3988 */ MCD_OPC_Decode, 230, 15, 98, // Opcode: LHu_MM +/* 3992 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 4006 +/* 3997 */ MCD_OPC_CheckPredicate, 7, 13, 10, 0, // Skip to: 6575 +/* 4002 */ MCD_OPC_Decode, 204, 21, 98, // Opcode: SH_MM +/* 4006 */ MCD_OPC_FilterValue, 15, 9, 0, 0, // Skip to: 4020 +/* 4011 */ MCD_OPC_CheckPredicate, 7, 255, 9, 0, // Skip to: 6575 +/* 4016 */ MCD_OPC_Decode, 223, 15, 98, // Opcode: LH_MM +/* 4020 */ MCD_OPC_FilterValue, 16, 83, 1, 0, // Skip to: 4364 +/* 4025 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 4028 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4042 +/* 4033 */ MCD_OPC_CheckPredicate, 6, 233, 9, 0, // Skip to: 6575 +/* 4038 */ MCD_OPC_Decode, 165, 8, 101, // Opcode: BLTZ_MM +/* 4042 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4056 +/* 4047 */ MCD_OPC_CheckPredicate, 6, 219, 9, 0, // Skip to: 6575 +/* 4052 */ MCD_OPC_Decode, 160, 8, 101, // Opcode: BLTZAL_MM +/* 4056 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 4070 +/* 4061 */ MCD_OPC_CheckPredicate, 6, 205, 9, 0, // Skip to: 6575 +/* 4066 */ MCD_OPC_Decode, 231, 7, 101, // Opcode: BGEZ_MM +/* 4070 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 4084 +/* 4075 */ MCD_OPC_CheckPredicate, 6, 191, 9, 0, // Skip to: 6575 +/* 4080 */ MCD_OPC_Decode, 226, 7, 101, // Opcode: BGEZAL_MM +/* 4084 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4098 +/* 4089 */ MCD_OPC_CheckPredicate, 6, 177, 9, 0, // Skip to: 6575 +/* 4094 */ MCD_OPC_Decode, 142, 8, 101, // Opcode: BLEZ_MM +/* 4098 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4112 +/* 4103 */ MCD_OPC_CheckPredicate, 6, 163, 9, 0, // Skip to: 6575 +/* 4108 */ MCD_OPC_Decode, 195, 8, 101, // Opcode: BNEZC_MM +/* 4112 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4126 +/* 4117 */ MCD_OPC_CheckPredicate, 6, 149, 9, 0, // Skip to: 6575 +/* 4122 */ MCD_OPC_Decode, 240, 7, 101, // Opcode: BGTZ_MM +/* 4126 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 4140 +/* 4131 */ MCD_OPC_CheckPredicate, 6, 135, 9, 0, // Skip to: 6575 +/* 4136 */ MCD_OPC_Decode, 205, 7, 101, // Opcode: BEQZC_MM +/* 4140 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 4154 +/* 4145 */ MCD_OPC_CheckPredicate, 6, 121, 9, 0, // Skip to: 6575 +/* 4150 */ MCD_OPC_Decode, 253, 23, 102, // Opcode: TLTI_MM +/* 4154 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 4168 +/* 4159 */ MCD_OPC_CheckPredicate, 6, 107, 9, 0, // Skip to: 6575 +/* 4164 */ MCD_OPC_Decode, 216, 23, 102, // Opcode: TGEI_MM +/* 4168 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 4182 +/* 4173 */ MCD_OPC_CheckPredicate, 6, 93, 9, 0, // Skip to: 6575 +/* 4178 */ MCD_OPC_Decode, 252, 23, 102, // Opcode: TLTIU_MM +/* 4182 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 4196 +/* 4187 */ MCD_OPC_CheckPredicate, 6, 79, 9, 0, // Skip to: 6575 +/* 4192 */ MCD_OPC_Decode, 215, 23, 102, // Opcode: TGEIU_MM +/* 4196 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 4210 +/* 4201 */ MCD_OPC_CheckPredicate, 6, 65, 9, 0, // Skip to: 6575 +/* 4206 */ MCD_OPC_Decode, 131, 24, 102, // Opcode: TNEI_MM +/* 4210 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 4224 +/* 4215 */ MCD_OPC_CheckPredicate, 6, 51, 9, 0, // Skip to: 6575 +/* 4220 */ MCD_OPC_Decode, 130, 16, 103, // Opcode: LUi_MM +/* 4224 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 4238 +/* 4229 */ MCD_OPC_CheckPredicate, 6, 37, 9, 0, // Skip to: 6575 +/* 4234 */ MCD_OPC_Decode, 209, 23, 102, // Opcode: TEQI_MM +/* 4238 */ MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 4252 +/* 4243 */ MCD_OPC_CheckPredicate, 6, 23, 9, 0, // Skip to: 6575 +/* 4248 */ MCD_OPC_Decode, 175, 23, 104, // Opcode: SYNCI_MM +/* 4252 */ MCD_OPC_FilterValue, 17, 9, 0, 0, // Skip to: 4266 +/* 4257 */ MCD_OPC_CheckPredicate, 6, 9, 9, 0, // Skip to: 6575 +/* 4262 */ MCD_OPC_Decode, 159, 8, 101, // Opcode: BLTZALS_MM +/* 4266 */ MCD_OPC_FilterValue, 19, 9, 0, 0, // Skip to: 4280 +/* 4271 */ MCD_OPC_CheckPredicate, 6, 251, 8, 0, // Skip to: 6575 +/* 4276 */ MCD_OPC_Decode, 225, 7, 101, // Opcode: BGEZALS_MM +/* 4280 */ MCD_OPC_FilterValue, 25, 16, 0, 0, // Skip to: 4301 +/* 4285 */ MCD_OPC_CheckPredicate, 11, 237, 8, 0, // Skip to: 6575 +/* 4290 */ MCD_OPC_CheckField, 16, 5, 0, 230, 8, 0, // Skip to: 6575 +/* 4297 */ MCD_OPC_Decode, 209, 8, 105, // Opcode: BPOSGE32C_MMR3 +/* 4301 */ MCD_OPC_FilterValue, 27, 16, 0, 0, // Skip to: 4322 +/* 4306 */ MCD_OPC_CheckPredicate, 12, 216, 8, 0, // Skip to: 6575 +/* 4311 */ MCD_OPC_CheckField, 16, 5, 0, 209, 8, 0, // Skip to: 6575 +/* 4318 */ MCD_OPC_Decode, 210, 8, 106, // Opcode: BPOSGE32_MM +/* 4322 */ MCD_OPC_FilterValue, 28, 16, 0, 0, // Skip to: 4343 +/* 4327 */ MCD_OPC_CheckPredicate, 13, 195, 8, 0, // Skip to: 6575 +/* 4332 */ MCD_OPC_CheckField, 16, 2, 0, 188, 8, 0, // Skip to: 6575 +/* 4339 */ MCD_OPC_Decode, 168, 7, 107, // Opcode: BC1F_MM +/* 4343 */ MCD_OPC_FilterValue, 29, 179, 8, 0, // Skip to: 6575 +/* 4348 */ MCD_OPC_CheckPredicate, 13, 174, 8, 0, // Skip to: 6575 +/* 4353 */ MCD_OPC_CheckField, 16, 2, 0, 167, 8, 0, // Skip to: 6575 +/* 4360 */ MCD_OPC_Decode, 173, 7, 107, // Opcode: BC1T_MM +/* 4364 */ MCD_OPC_FilterValue, 20, 9, 0, 0, // Skip to: 4378 +/* 4369 */ MCD_OPC_CheckPredicate, 6, 153, 8, 0, // Skip to: 6575 +/* 4374 */ MCD_OPC_Decode, 177, 19, 108, // Opcode: ORi_MM +/* 4378 */ MCD_OPC_FilterValue, 21, 234, 5, 0, // Skip to: 5897 +/* 4383 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 4386 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4400 +/* 4391 */ MCD_OPC_CheckPredicate, 14, 131, 8, 0, // Skip to: 6575 +/* 4396 */ MCD_OPC_Decode, 219, 16, 109, // Opcode: MADD_S_MM +/* 4400 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 4414 +/* 4405 */ MCD_OPC_CheckPredicate, 14, 117, 8, 0, // Skip to: 6575 +/* 4410 */ MCD_OPC_Decode, 143, 19, 109, // Opcode: NMADD_S_MM +/* 4414 */ MCD_OPC_FilterValue, 8, 59, 0, 0, // Skip to: 4478 +/* 4419 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 4422 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4436 +/* 4427 */ MCD_OPC_CheckPredicate, 13, 95, 8, 0, // Skip to: 6575 +/* 4432 */ MCD_OPC_Decode, 173, 16, 110, // Opcode: LWXC1_MM +/* 4436 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 4450 +/* 4441 */ MCD_OPC_CheckPredicate, 13, 81, 8, 0, // Skip to: 6575 +/* 4446 */ MCD_OPC_Decode, 166, 23, 110, // Opcode: SWXC1_MM +/* 4450 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4464 +/* 4455 */ MCD_OPC_CheckPredicate, 15, 67, 8, 0, // Skip to: 6575 +/* 4460 */ MCD_OPC_Decode, 255, 15, 111, // Opcode: LUXC1_MM +/* 4464 */ MCD_OPC_FilterValue, 6, 58, 8, 0, // Skip to: 6575 +/* 4469 */ MCD_OPC_CheckPredicate, 15, 53, 8, 0, // Skip to: 6575 +/* 4474 */ MCD_OPC_Decode, 255, 22, 111, // Opcode: SUXC1_MM +/* 4478 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 4492 +/* 4483 */ MCD_OPC_CheckPredicate, 16, 39, 8, 0, // Skip to: 6575 +/* 4488 */ MCD_OPC_Decode, 211, 16, 112, // Opcode: MADD_D32_MM +/* 4492 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 4506 +/* 4497 */ MCD_OPC_CheckPredicate, 16, 25, 8, 0, // Skip to: 6575 +/* 4502 */ MCD_OPC_Decode, 140, 19, 112, // Opcode: NMADD_D32_MM +/* 4506 */ MCD_OPC_FilterValue, 32, 101, 0, 0, // Skip to: 4612 +/* 4511 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 4514 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4535 +/* 4519 */ MCD_OPC_CheckPredicate, 13, 3, 8, 0, // Skip to: 6575 +/* 4524 */ MCD_OPC_CheckField, 11, 2, 0, 252, 7, 0, // Skip to: 6575 +/* 4531 */ MCD_OPC_Decode, 224, 17, 113, // Opcode: MOVF_S_MM +/* 4535 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 4556 +/* 4540 */ MCD_OPC_CheckPredicate, 13, 238, 7, 0, // Skip to: 6575 +/* 4545 */ MCD_OPC_CheckField, 11, 2, 0, 231, 7, 0, // Skip to: 6575 +/* 4552 */ MCD_OPC_Decode, 245, 17, 113, // Opcode: MOVT_S_MM +/* 4556 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4570 +/* 4561 */ MCD_OPC_CheckPredicate, 6, 217, 7, 0, // Skip to: 6575 +/* 4566 */ MCD_OPC_Decode, 241, 19, 114, // Opcode: PREFX_MM +/* 4570 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 4591 +/* 4575 */ MCD_OPC_CheckPredicate, 17, 203, 7, 0, // Skip to: 6575 +/* 4580 */ MCD_OPC_CheckField, 11, 2, 0, 196, 7, 0, // Skip to: 6575 +/* 4587 */ MCD_OPC_Decode, 218, 17, 115, // Opcode: MOVF_D32_MM +/* 4591 */ MCD_OPC_FilterValue, 9, 187, 7, 0, // Skip to: 6575 +/* 4596 */ MCD_OPC_CheckPredicate, 17, 182, 7, 0, // Skip to: 6575 +/* 4601 */ MCD_OPC_CheckField, 11, 2, 0, 175, 7, 0, // Skip to: 6575 +/* 4608 */ MCD_OPC_Decode, 239, 17, 115, // Opcode: MOVT_D32_MM +/* 4612 */ MCD_OPC_FilterValue, 33, 9, 0, 0, // Skip to: 4626 +/* 4617 */ MCD_OPC_CheckPredicate, 14, 161, 7, 0, // Skip to: 6575 +/* 4622 */ MCD_OPC_Decode, 155, 18, 109, // Opcode: MSUB_S_MM +/* 4626 */ MCD_OPC_FilterValue, 34, 9, 0, 0, // Skip to: 4640 +/* 4631 */ MCD_OPC_CheckPredicate, 14, 147, 7, 0, // Skip to: 6575 +/* 4636 */ MCD_OPC_Decode, 148, 19, 109, // Opcode: NMSUB_S_MM +/* 4640 */ MCD_OPC_FilterValue, 41, 9, 0, 0, // Skip to: 4654 +/* 4645 */ MCD_OPC_CheckPredicate, 16, 133, 7, 0, // Skip to: 6575 +/* 4650 */ MCD_OPC_Decode, 147, 18, 112, // Opcode: MSUB_D32_MM +/* 4654 */ MCD_OPC_FilterValue, 42, 9, 0, 0, // Skip to: 4668 +/* 4659 */ MCD_OPC_CheckPredicate, 16, 119, 7, 0, // Skip to: 6575 +/* 4664 */ MCD_OPC_Decode, 145, 19, 112, // Opcode: NMSUB_D32_MM +/* 4668 */ MCD_OPC_FilterValue, 48, 59, 0, 0, // Skip to: 4732 +/* 4673 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 4676 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4690 +/* 4681 */ MCD_OPC_CheckPredicate, 18, 97, 7, 0, // Skip to: 6575 +/* 4686 */ MCD_OPC_Decode, 138, 13, 116, // Opcode: FADD_D32_MM +/* 4690 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4704 +/* 4695 */ MCD_OPC_CheckPredicate, 18, 83, 7, 0, // Skip to: 6575 +/* 4700 */ MCD_OPC_Decode, 156, 14, 116, // Opcode: FSUB_D32_MM +/* 4704 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4718 +/* 4709 */ MCD_OPC_CheckPredicate, 18, 69, 7, 0, // Skip to: 6575 +/* 4714 */ MCD_OPC_Decode, 239, 13, 116, // Opcode: FMUL_D32_MM +/* 4718 */ MCD_OPC_FilterValue, 7, 60, 7, 0, // Skip to: 6575 +/* 4723 */ MCD_OPC_CheckPredicate, 18, 55, 7, 0, // Skip to: 6575 +/* 4728 */ MCD_OPC_Decode, 177, 13, 116, // Opcode: FDIV_D32_MM +/* 4732 */ MCD_OPC_FilterValue, 56, 59, 0, 0, // Skip to: 4796 +/* 4737 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 4740 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4754 +/* 4745 */ MCD_OPC_CheckPredicate, 13, 33, 7, 0, // Skip to: 6575 +/* 4750 */ MCD_OPC_Decode, 236, 17, 117, // Opcode: MOVN_I_S_MM +/* 4754 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4768 +/* 4759 */ MCD_OPC_CheckPredicate, 13, 19, 7, 0, // Skip to: 6575 +/* 4764 */ MCD_OPC_Decode, 129, 18, 117, // Opcode: MOVZ_I_S_MM +/* 4768 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4782 +/* 4773 */ MCD_OPC_CheckPredicate, 17, 5, 7, 0, // Skip to: 6575 +/* 4778 */ MCD_OPC_Decode, 230, 17, 118, // Opcode: MOVN_I_D32_MM +/* 4782 */ MCD_OPC_FilterValue, 5, 252, 6, 0, // Skip to: 6575 +/* 4787 */ MCD_OPC_CheckPredicate, 17, 247, 6, 0, // Skip to: 6575 +/* 4792 */ MCD_OPC_Decode, 251, 17, 118, // Opcode: MOVZ_I_D32_MM +/* 4796 */ MCD_OPC_FilterValue, 59, 96, 2, 0, // Skip to: 5409 +/* 4801 */ MCD_OPC_ExtractField, 6, 7, // Inst{12-6} ... +/* 4804 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4825 +/* 4809 */ MCD_OPC_CheckPredicate, 19, 225, 6, 0, // Skip to: 6575 +/* 4814 */ MCD_OPC_CheckField, 13, 3, 1, 218, 6, 0, // Skip to: 6575 +/* 4821 */ MCD_OPC_Decode, 134, 17, 119, // Opcode: MFC1_MM +/* 4825 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 4846 +/* 4830 */ MCD_OPC_CheckPredicate, 18, 204, 6, 0, // Skip to: 6575 +/* 4835 */ MCD_OPC_CheckField, 13, 3, 1, 197, 6, 0, // Skip to: 6575 +/* 4842 */ MCD_OPC_Decode, 228, 13, 120, // Opcode: FMOV_D32_MM +/* 4846 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 4882 +/* 4851 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 4854 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4868 +/* 4859 */ MCD_OPC_CheckPredicate, 20, 175, 6, 0, // Skip to: 6575 +/* 4864 */ MCD_OPC_Decode, 197, 10, 121, // Opcode: CVT_L_S_MM +/* 4868 */ MCD_OPC_FilterValue, 2, 166, 6, 0, // Skip to: 6575 +/* 4873 */ MCD_OPC_CheckPredicate, 20, 161, 6, 0, // Skip to: 6575 +/* 4878 */ MCD_OPC_Decode, 194, 10, 122, // Opcode: CVT_L_D64_MM +/* 4882 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4896 +/* 4887 */ MCD_OPC_CheckPredicate, 13, 147, 6, 0, // Skip to: 6575 +/* 4892 */ MCD_OPC_Decode, 222, 17, 123, // Opcode: MOVF_I_MM +/* 4896 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 4932 +/* 4901 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 4904 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4918 +/* 4909 */ MCD_OPC_CheckPredicate, 19, 125, 6, 0, // Skip to: 6575 +/* 4914 */ MCD_OPC_Decode, 178, 20, 124, // Opcode: RSQRT_S_MM +/* 4918 */ MCD_OPC_FilterValue, 2, 116, 6, 0, // Skip to: 6575 +/* 4923 */ MCD_OPC_CheckPredicate, 18, 111, 6, 0, // Skip to: 6575 +/* 4928 */ MCD_OPC_Decode, 174, 20, 120, // Opcode: RSQRT_D32_MM +/* 4932 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 4968 +/* 4937 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 4940 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4954 +/* 4945 */ MCD_OPC_CheckPredicate, 19, 89, 6, 0, // Skip to: 6575 +/* 4950 */ MCD_OPC_Decode, 135, 13, 124, // Opcode: FABS_S_MM +/* 4954 */ MCD_OPC_FilterValue, 1, 80, 6, 0, // Skip to: 6575 +/* 4959 */ MCD_OPC_CheckPredicate, 18, 75, 6, 0, // Skip to: 6575 +/* 4964 */ MCD_OPC_Decode, 131, 13, 120, // Opcode: FABS_D32_MM +/* 4968 */ MCD_OPC_FilterValue, 32, 16, 0, 0, // Skip to: 4989 +/* 4973 */ MCD_OPC_CheckPredicate, 19, 61, 6, 0, // Skip to: 6575 +/* 4978 */ MCD_OPC_CheckField, 13, 3, 1, 54, 6, 0, // Skip to: 6575 +/* 4985 */ MCD_OPC_Decode, 163, 18, 125, // Opcode: MTC1_MM +/* 4989 */ MCD_OPC_FilterValue, 36, 31, 0, 0, // Skip to: 5025 +/* 4994 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 4997 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5011 +/* 5002 */ MCD_OPC_CheckPredicate, 19, 32, 6, 0, // Skip to: 6575 +/* 5007 */ MCD_OPC_Decode, 218, 10, 124, // Opcode: CVT_W_S_MM +/* 5011 */ MCD_OPC_FilterValue, 2, 23, 6, 0, // Skip to: 6575 +/* 5016 */ MCD_OPC_CheckPredicate, 18, 18, 6, 0, // Skip to: 6575 +/* 5021 */ MCD_OPC_Decode, 214, 10, 126, // Opcode: CVT_W_D32_MM +/* 5025 */ MCD_OPC_FilterValue, 37, 9, 0, 0, // Skip to: 5039 +/* 5030 */ MCD_OPC_CheckPredicate, 13, 4, 6, 0, // Skip to: 6575 +/* 5035 */ MCD_OPC_Decode, 243, 17, 123, // Opcode: MOVT_I_MM +/* 5039 */ MCD_OPC_FilterValue, 40, 31, 0, 0, // Skip to: 5075 +/* 5044 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 5047 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5061 +/* 5052 */ MCD_OPC_CheckPredicate, 19, 238, 5, 0, // Skip to: 6575 +/* 5057 */ MCD_OPC_Decode, 152, 14, 124, // Opcode: FSQRT_S_MM +/* 5061 */ MCD_OPC_FilterValue, 2, 229, 5, 0, // Skip to: 6575 +/* 5066 */ MCD_OPC_CheckPredicate, 18, 224, 5, 0, // Skip to: 6575 +/* 5071 */ MCD_OPC_Decode, 148, 14, 120, // Opcode: FSQRT_D32_MM +/* 5075 */ MCD_OPC_FilterValue, 44, 59, 0, 0, // Skip to: 5139 +/* 5080 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 5083 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5097 +/* 5088 */ MCD_OPC_CheckPredicate, 19, 202, 5, 0, // Skip to: 6575 +/* 5093 */ MCD_OPC_Decode, 215, 13, 124, // Opcode: FLOOR_W_S_MM +/* 5097 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 5111 +/* 5102 */ MCD_OPC_CheckPredicate, 19, 188, 5, 0, // Skip to: 6575 +/* 5107 */ MCD_OPC_Decode, 143, 24, 124, // Opcode: TRUNC_W_S_MM +/* 5111 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 5125 +/* 5116 */ MCD_OPC_CheckPredicate, 18, 174, 5, 0, // Skip to: 6575 +/* 5121 */ MCD_OPC_Decode, 213, 13, 126, // Opcode: FLOOR_W_MM +/* 5125 */ MCD_OPC_FilterValue, 3, 165, 5, 0, // Skip to: 6575 +/* 5130 */ MCD_OPC_CheckPredicate, 18, 160, 5, 0, // Skip to: 6575 +/* 5135 */ MCD_OPC_Decode, 141, 24, 126, // Opcode: TRUNC_W_MM +/* 5139 */ MCD_OPC_FilterValue, 45, 16, 0, 0, // Skip to: 5160 +/* 5144 */ MCD_OPC_CheckPredicate, 18, 146, 5, 0, // Skip to: 6575 +/* 5149 */ MCD_OPC_CheckField, 13, 3, 1, 139, 5, 0, // Skip to: 6575 +/* 5156 */ MCD_OPC_Decode, 248, 13, 120, // Opcode: FNEG_D32_MM +/* 5160 */ MCD_OPC_FilterValue, 64, 32, 0, 0, // Skip to: 5197 +/* 5165 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 5168 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5182 +/* 5173 */ MCD_OPC_CheckPredicate, 19, 117, 5, 0, // Skip to: 6575 +/* 5178 */ MCD_OPC_Decode, 145, 9, 127, // Opcode: CFC1_MM +/* 5182 */ MCD_OPC_FilterValue, 1, 108, 5, 0, // Skip to: 6575 +/* 5187 */ MCD_OPC_CheckPredicate, 18, 103, 5, 0, // Skip to: 6575 +/* 5192 */ MCD_OPC_Decode, 144, 17, 128, 1, // Opcode: MFHC1_D32_MM +/* 5197 */ MCD_OPC_FilterValue, 72, 31, 0, 0, // Skip to: 5233 +/* 5202 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 5205 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5219 +/* 5210 */ MCD_OPC_CheckPredicate, 19, 80, 5, 0, // Skip to: 6575 +/* 5215 */ MCD_OPC_Decode, 139, 20, 124, // Opcode: RECIP_S_MM +/* 5219 */ MCD_OPC_FilterValue, 2, 71, 5, 0, // Skip to: 6575 +/* 5224 */ MCD_OPC_CheckPredicate, 18, 66, 5, 0, // Skip to: 6575 +/* 5229 */ MCD_OPC_Decode, 135, 20, 120, // Opcode: RECIP_D32_MM +/* 5233 */ MCD_OPC_FilterValue, 77, 33, 0, 0, // Skip to: 5271 +/* 5238 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 5241 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5256 +/* 5246 */ MCD_OPC_CheckPredicate, 18, 44, 5, 0, // Skip to: 6575 +/* 5251 */ MCD_OPC_Decode, 184, 10, 129, 1, // Opcode: CVT_D32_S_MM +/* 5256 */ MCD_OPC_FilterValue, 1, 34, 5, 0, // Skip to: 6575 +/* 5261 */ MCD_OPC_CheckPredicate, 18, 29, 5, 0, // Skip to: 6575 +/* 5266 */ MCD_OPC_Decode, 186, 10, 129, 1, // Opcode: CVT_D32_W_MM +/* 5271 */ MCD_OPC_FilterValue, 96, 33, 0, 0, // Skip to: 5309 +/* 5276 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 5279 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5294 +/* 5284 */ MCD_OPC_CheckPredicate, 19, 6, 5, 0, // Skip to: 6575 +/* 5289 */ MCD_OPC_Decode, 180, 10, 130, 1, // Opcode: CTC1_MM +/* 5294 */ MCD_OPC_FilterValue, 1, 252, 4, 0, // Skip to: 6575 +/* 5299 */ MCD_OPC_CheckPredicate, 18, 247, 4, 0, // Skip to: 6575 +/* 5304 */ MCD_OPC_Decode, 173, 18, 131, 1, // Opcode: MTHC1_D32_MM +/* 5309 */ MCD_OPC_FilterValue, 108, 59, 0, 0, // Skip to: 5373 +/* 5314 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 5317 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5331 +/* 5322 */ MCD_OPC_CheckPredicate, 19, 224, 4, 0, // Skip to: 6575 +/* 5327 */ MCD_OPC_Decode, 134, 9, 124, // Opcode: CEIL_W_S_MM +/* 5331 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 5345 +/* 5336 */ MCD_OPC_CheckPredicate, 19, 210, 4, 0, // Skip to: 6575 +/* 5341 */ MCD_OPC_Decode, 171, 20, 124, // Opcode: ROUND_W_S_MM +/* 5345 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 5359 +/* 5350 */ MCD_OPC_CheckPredicate, 18, 196, 4, 0, // Skip to: 6575 +/* 5355 */ MCD_OPC_Decode, 132, 9, 126, // Opcode: CEIL_W_MM +/* 5359 */ MCD_OPC_FilterValue, 3, 187, 4, 0, // Skip to: 6575 +/* 5364 */ MCD_OPC_CheckPredicate, 18, 182, 4, 0, // Skip to: 6575 +/* 5369 */ MCD_OPC_Decode, 169, 20, 126, // Opcode: ROUND_W_MM +/* 5373 */ MCD_OPC_FilterValue, 109, 173, 4, 0, // Skip to: 6575 +/* 5378 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 5381 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5395 +/* 5386 */ MCD_OPC_CheckPredicate, 18, 160, 4, 0, // Skip to: 6575 +/* 5391 */ MCD_OPC_Decode, 203, 10, 126, // Opcode: CVT_S_D32_MM +/* 5395 */ MCD_OPC_FilterValue, 1, 151, 4, 0, // Skip to: 6575 +/* 5400 */ MCD_OPC_CheckPredicate, 19, 146, 4, 0, // Skip to: 6575 +/* 5405 */ MCD_OPC_Decode, 211, 10, 124, // Opcode: CVT_S_W_MM +/* 5409 */ MCD_OPC_FilterValue, 60, 137, 4, 0, // Skip to: 6575 +/* 5414 */ MCD_OPC_ExtractField, 6, 7, // Inst{12-6} ... +/* 5417 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5432 +/* 5422 */ MCD_OPC_CheckPredicate, 13, 124, 4, 0, // Skip to: 6575 +/* 5427 */ MCD_OPC_Decode, 231, 10, 132, 1, // Opcode: C_F_S_MM +/* 5432 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5447 +/* 5437 */ MCD_OPC_CheckPredicate, 13, 109, 4, 0, // Skip to: 6575 +/* 5442 */ MCD_OPC_Decode, 187, 11, 132, 1, // Opcode: C_UN_S_MM +/* 5447 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 5462 +/* 5452 */ MCD_OPC_CheckPredicate, 13, 94, 4, 0, // Skip to: 6575 +/* 5457 */ MCD_OPC_Decode, 225, 10, 132, 1, // Opcode: C_EQ_S_MM +/* 5462 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 5477 +/* 5467 */ MCD_OPC_CheckPredicate, 13, 79, 4, 0, // Skip to: 6575 +/* 5472 */ MCD_OPC_Decode, 169, 11, 132, 1, // Opcode: C_UEQ_S_MM +/* 5477 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 5492 +/* 5482 */ MCD_OPC_CheckPredicate, 13, 64, 4, 0, // Skip to: 6575 +/* 5487 */ MCD_OPC_Decode, 151, 11, 132, 1, // Opcode: C_OLT_S_MM +/* 5492 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 5507 +/* 5497 */ MCD_OPC_CheckPredicate, 13, 49, 4, 0, // Skip to: 6575 +/* 5502 */ MCD_OPC_Decode, 181, 11, 132, 1, // Opcode: C_ULT_S_MM +/* 5507 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 5522 +/* 5512 */ MCD_OPC_CheckPredicate, 13, 34, 4, 0, // Skip to: 6575 +/* 5517 */ MCD_OPC_Decode, 145, 11, 132, 1, // Opcode: C_OLE_S_MM +/* 5522 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 5537 +/* 5527 */ MCD_OPC_CheckPredicate, 13, 19, 4, 0, // Skip to: 6575 +/* 5532 */ MCD_OPC_Decode, 175, 11, 132, 1, // Opcode: C_ULE_S_MM +/* 5537 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 5552 +/* 5542 */ MCD_OPC_CheckPredicate, 13, 4, 4, 0, // Skip to: 6575 +/* 5547 */ MCD_OPC_Decode, 163, 11, 132, 1, // Opcode: C_SF_S_MM +/* 5552 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 5567 +/* 5557 */ MCD_OPC_CheckPredicate, 13, 245, 3, 0, // Skip to: 6575 +/* 5562 */ MCD_OPC_Decode, 255, 10, 132, 1, // Opcode: C_NGLE_S_MM +/* 5567 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 5582 +/* 5572 */ MCD_OPC_CheckPredicate, 13, 230, 3, 0, // Skip to: 6575 +/* 5577 */ MCD_OPC_Decode, 157, 11, 132, 1, // Opcode: C_SEQ_S_MM +/* 5582 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 5597 +/* 5587 */ MCD_OPC_CheckPredicate, 13, 215, 3, 0, // Skip to: 6575 +/* 5592 */ MCD_OPC_Decode, 133, 11, 132, 1, // Opcode: C_NGL_S_MM +/* 5597 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 5612 +/* 5602 */ MCD_OPC_CheckPredicate, 13, 200, 3, 0, // Skip to: 6575 +/* 5607 */ MCD_OPC_Decode, 243, 10, 132, 1, // Opcode: C_LT_S_MM +/* 5612 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5627 +/* 5617 */ MCD_OPC_CheckPredicate, 13, 185, 3, 0, // Skip to: 6575 +/* 5622 */ MCD_OPC_Decode, 249, 10, 132, 1, // Opcode: C_NGE_S_MM +/* 5627 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 5642 +/* 5632 */ MCD_OPC_CheckPredicate, 13, 170, 3, 0, // Skip to: 6575 +/* 5637 */ MCD_OPC_Decode, 237, 10, 132, 1, // Opcode: C_LE_S_MM +/* 5642 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5657 +/* 5647 */ MCD_OPC_CheckPredicate, 13, 155, 3, 0, // Skip to: 6575 +/* 5652 */ MCD_OPC_Decode, 139, 11, 132, 1, // Opcode: C_NGT_S_MM +/* 5657 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 5672 +/* 5662 */ MCD_OPC_CheckPredicate, 17, 140, 3, 0, // Skip to: 6575 +/* 5667 */ MCD_OPC_Decode, 227, 10, 133, 1, // Opcode: C_F_D32_MM +/* 5672 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 5687 +/* 5677 */ MCD_OPC_CheckPredicate, 17, 125, 3, 0, // Skip to: 6575 +/* 5682 */ MCD_OPC_Decode, 183, 11, 133, 1, // Opcode: C_UN_D32_MM +/* 5687 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 5702 +/* 5692 */ MCD_OPC_CheckPredicate, 17, 110, 3, 0, // Skip to: 6575 +/* 5697 */ MCD_OPC_Decode, 221, 10, 133, 1, // Opcode: C_EQ_D32_MM +/* 5702 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 5717 +/* 5707 */ MCD_OPC_CheckPredicate, 17, 95, 3, 0, // Skip to: 6575 +/* 5712 */ MCD_OPC_Decode, 165, 11, 133, 1, // Opcode: C_UEQ_D32_MM +/* 5717 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 5732 +/* 5722 */ MCD_OPC_CheckPredicate, 17, 80, 3, 0, // Skip to: 6575 +/* 5727 */ MCD_OPC_Decode, 147, 11, 133, 1, // Opcode: C_OLT_D32_MM +/* 5732 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 5747 +/* 5737 */ MCD_OPC_CheckPredicate, 17, 65, 3, 0, // Skip to: 6575 +/* 5742 */ MCD_OPC_Decode, 177, 11, 133, 1, // Opcode: C_ULT_D32_MM +/* 5747 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 5762 +/* 5752 */ MCD_OPC_CheckPredicate, 17, 50, 3, 0, // Skip to: 6575 +/* 5757 */ MCD_OPC_Decode, 141, 11, 133, 1, // Opcode: C_OLE_D32_MM +/* 5762 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 5777 +/* 5767 */ MCD_OPC_CheckPredicate, 17, 35, 3, 0, // Skip to: 6575 +/* 5772 */ MCD_OPC_Decode, 171, 11, 133, 1, // Opcode: C_ULE_D32_MM +/* 5777 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 5792 +/* 5782 */ MCD_OPC_CheckPredicate, 17, 20, 3, 0, // Skip to: 6575 +/* 5787 */ MCD_OPC_Decode, 159, 11, 133, 1, // Opcode: C_SF_D32_MM +/* 5792 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 5807 +/* 5797 */ MCD_OPC_CheckPredicate, 17, 5, 3, 0, // Skip to: 6575 +/* 5802 */ MCD_OPC_Decode, 251, 10, 133, 1, // Opcode: C_NGLE_D32_MM +/* 5807 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 5822 +/* 5812 */ MCD_OPC_CheckPredicate, 17, 246, 2, 0, // Skip to: 6575 +/* 5817 */ MCD_OPC_Decode, 153, 11, 133, 1, // Opcode: C_SEQ_D32_MM +/* 5822 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 5837 +/* 5827 */ MCD_OPC_CheckPredicate, 17, 231, 2, 0, // Skip to: 6575 +/* 5832 */ MCD_OPC_Decode, 129, 11, 133, 1, // Opcode: C_NGL_D32_MM +/* 5837 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 5852 +/* 5842 */ MCD_OPC_CheckPredicate, 17, 216, 2, 0, // Skip to: 6575 +/* 5847 */ MCD_OPC_Decode, 239, 10, 133, 1, // Opcode: C_LT_D32_MM +/* 5852 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 5867 +/* 5857 */ MCD_OPC_CheckPredicate, 17, 201, 2, 0, // Skip to: 6575 +/* 5862 */ MCD_OPC_Decode, 245, 10, 133, 1, // Opcode: C_NGE_D32_MM +/* 5867 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 5882 +/* 5872 */ MCD_OPC_CheckPredicate, 17, 186, 2, 0, // Skip to: 6575 +/* 5877 */ MCD_OPC_Decode, 233, 10, 133, 1, // Opcode: C_LE_D32_MM +/* 5882 */ MCD_OPC_FilterValue, 31, 176, 2, 0, // Skip to: 6575 +/* 5887 */ MCD_OPC_CheckPredicate, 17, 171, 2, 0, // Skip to: 6575 +/* 5892 */ MCD_OPC_Decode, 135, 11, 133, 1, // Opcode: C_NGT_D32_MM +/* 5897 */ MCD_OPC_FilterValue, 22, 48, 0, 0, // Skip to: 5950 +/* 5902 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... +/* 5905 */ MCD_OPC_FilterValue, 197, 1, 9, 0, 0, // Skip to: 5920 +/* 5911 */ MCD_OPC_CheckPredicate, 8, 147, 2, 0, // Skip to: 6575 +/* 5916 */ MCD_OPC_Decode, 205, 9, 54, // Opcode: CMPGU_EQ_QB_MM +/* 5920 */ MCD_OPC_FilterValue, 133, 2, 9, 0, 0, // Skip to: 5935 +/* 5926 */ MCD_OPC_CheckPredicate, 8, 132, 2, 0, // Skip to: 6575 +/* 5931 */ MCD_OPC_Decode, 209, 9, 54, // Opcode: CMPGU_LT_QB_MM +/* 5935 */ MCD_OPC_FilterValue, 197, 2, 122, 2, 0, // Skip to: 6575 +/* 5941 */ MCD_OPC_CheckPredicate, 8, 117, 2, 0, // Skip to: 6575 +/* 5946 */ MCD_OPC_Decode, 207, 9, 54, // Opcode: CMPGU_LE_QB_MM +/* 5950 */ MCD_OPC_FilterValue, 24, 115, 1, 0, // Skip to: 6326 +/* 5955 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 5958 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5972 +/* 5963 */ MCD_OPC_CheckPredicate, 6, 95, 2, 0, // Skip to: 6575 +/* 5968 */ MCD_OPC_Decode, 153, 16, 99, // Opcode: LWL_MM +/* 5972 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 5986 +/* 5977 */ MCD_OPC_CheckPredicate, 6, 81, 2, 0, // Skip to: 6575 +/* 5982 */ MCD_OPC_Decode, 166, 16, 99, // Opcode: LWR_MM +/* 5986 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6000 +/* 5991 */ MCD_OPC_CheckPredicate, 6, 67, 2, 0, // Skip to: 6575 +/* 5996 */ MCD_OPC_Decode, 242, 19, 100, // Opcode: PREF_MM +/* 6000 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 6014 +/* 6005 */ MCD_OPC_CheckPredicate, 6, 53, 2, 0, // Skip to: 6575 +/* 6010 */ MCD_OPC_Decode, 243, 15, 99, // Opcode: LL_MM +/* 6014 */ MCD_OPC_FilterValue, 6, 123, 0, 0, // Skip to: 6142 +/* 6019 */ MCD_OPC_ExtractField, 9, 3, // Inst{11-9} ... +/* 6022 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6037 +/* 6027 */ MCD_OPC_CheckPredicate, 21, 31, 2, 0, // Skip to: 6575 +/* 6032 */ MCD_OPC_Decode, 177, 15, 134, 1, // Opcode: LBuE_MM +/* 6037 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6052 +/* 6042 */ MCD_OPC_CheckPredicate, 21, 16, 2, 0, // Skip to: 6575 +/* 6047 */ MCD_OPC_Decode, 229, 15, 134, 1, // Opcode: LHuE_MM +/* 6052 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6067 +/* 6057 */ MCD_OPC_CheckPredicate, 22, 1, 2, 0, // Skip to: 6575 +/* 6062 */ MCD_OPC_Decode, 152, 16, 134, 1, // Opcode: LWLE_MM +/* 6067 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 6082 +/* 6072 */ MCD_OPC_CheckPredicate, 22, 242, 1, 0, // Skip to: 6575 +/* 6077 */ MCD_OPC_Decode, 165, 16, 134, 1, // Opcode: LWRE_MM +/* 6082 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 6097 +/* 6087 */ MCD_OPC_CheckPredicate, 21, 227, 1, 0, // Skip to: 6575 +/* 6092 */ MCD_OPC_Decode, 158, 15, 134, 1, // Opcode: LBE_MM +/* 6097 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 6112 +/* 6102 */ MCD_OPC_CheckPredicate, 21, 212, 1, 0, // Skip to: 6575 +/* 6107 */ MCD_OPC_Decode, 210, 15, 134, 1, // Opcode: LHE_MM +/* 6112 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 6127 +/* 6117 */ MCD_OPC_CheckPredicate, 21, 197, 1, 0, // Skip to: 6575 +/* 6122 */ MCD_OPC_Decode, 241, 15, 134, 1, // Opcode: LLE_MM +/* 6127 */ MCD_OPC_FilterValue, 7, 187, 1, 0, // Skip to: 6575 +/* 6132 */ MCD_OPC_CheckPredicate, 21, 182, 1, 0, // Skip to: 6575 +/* 6137 */ MCD_OPC_Decode, 145, 16, 134, 1, // Opcode: LWE_MM +/* 6142 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 6156 +/* 6147 */ MCD_OPC_CheckPredicate, 6, 167, 1, 0, // Skip to: 6575 +/* 6152 */ MCD_OPC_Decode, 150, 23, 99, // Opcode: SWL_MM +/* 6156 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 6170 +/* 6161 */ MCD_OPC_CheckPredicate, 6, 153, 1, 0, // Skip to: 6575 +/* 6166 */ MCD_OPC_Decode, 161, 23, 99, // Opcode: SWR_MM +/* 6170 */ MCD_OPC_FilterValue, 10, 123, 0, 0, // Skip to: 6298 +/* 6175 */ MCD_OPC_ExtractField, 9, 3, // Inst{11-9} ... +/* 6178 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6193 +/* 6183 */ MCD_OPC_CheckPredicate, 22, 131, 1, 0, // Skip to: 6575 +/* 6188 */ MCD_OPC_Decode, 149, 23, 134, 1, // Opcode: SWLE_MM +/* 6193 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6208 +/* 6198 */ MCD_OPC_CheckPredicate, 22, 116, 1, 0, // Skip to: 6575 +/* 6203 */ MCD_OPC_Decode, 160, 23, 134, 1, // Opcode: SWRE_MM +/* 6208 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6223 +/* 6213 */ MCD_OPC_CheckPredicate, 21, 101, 1, 0, // Skip to: 6575 +/* 6218 */ MCD_OPC_Decode, 240, 19, 135, 1, // Opcode: PREFE_MM +/* 6223 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 6238 +/* 6228 */ MCD_OPC_CheckPredicate, 21, 86, 1, 0, // Skip to: 6575 +/* 6233 */ MCD_OPC_Decode, 248, 8, 135, 1, // Opcode: CACHEE_MM +/* 6238 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 6253 +/* 6243 */ MCD_OPC_CheckPredicate, 21, 71, 1, 0, // Skip to: 6575 +/* 6248 */ MCD_OPC_Decode, 199, 20, 134, 1, // Opcode: SBE_MM +/* 6253 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 6268 +/* 6258 */ MCD_OPC_CheckPredicate, 21, 56, 1, 0, // Skip to: 6575 +/* 6263 */ MCD_OPC_Decode, 149, 21, 134, 1, // Opcode: SHE_MM +/* 6268 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 6283 +/* 6273 */ MCD_OPC_CheckPredicate, 21, 41, 1, 0, // Skip to: 6575 +/* 6278 */ MCD_OPC_Decode, 212, 20, 134, 1, // Opcode: SCE_MM +/* 6283 */ MCD_OPC_FilterValue, 7, 31, 1, 0, // Skip to: 6575 +/* 6288 */ MCD_OPC_CheckPredicate, 21, 26, 1, 0, // Skip to: 6575 +/* 6293 */ MCD_OPC_Decode, 143, 23, 134, 1, // Opcode: SWE_MM +/* 6298 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 6312 +/* 6303 */ MCD_OPC_CheckPredicate, 6, 11, 1, 0, // Skip to: 6575 +/* 6308 */ MCD_OPC_Decode, 214, 20, 99, // Opcode: SC_MM +/* 6312 */ MCD_OPC_FilterValue, 14, 2, 1, 0, // Skip to: 6575 +/* 6317 */ MCD_OPC_CheckPredicate, 6, 253, 0, 0, // Skip to: 6575 +/* 6322 */ MCD_OPC_Decode, 170, 16, 99, // Opcode: LWU_MM +/* 6326 */ MCD_OPC_FilterValue, 28, 9, 0, 0, // Skip to: 6340 +/* 6331 */ MCD_OPC_CheckPredicate, 6, 239, 0, 0, // Skip to: 6575 +/* 6336 */ MCD_OPC_Decode, 186, 24, 108, // Opcode: XORi_MM +/* 6340 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 6355 +/* 6345 */ MCD_OPC_CheckPredicate, 6, 225, 0, 0, // Skip to: 6575 +/* 6350 */ MCD_OPC_Decode, 250, 14, 136, 1, // Opcode: JALS_MM +/* 6355 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 6370 +/* 6360 */ MCD_OPC_CheckPredicate, 6, 210, 0, 0, // Skip to: 6575 +/* 6365 */ MCD_OPC_Decode, 130, 6, 137, 1, // Opcode: ADDIUPC_MM +/* 6370 */ MCD_OPC_FilterValue, 36, 9, 0, 0, // Skip to: 6384 +/* 6375 */ MCD_OPC_CheckPredicate, 7, 195, 0, 0, // Skip to: 6575 +/* 6380 */ MCD_OPC_Decode, 248, 21, 97, // Opcode: SLTi_MM +/* 6384 */ MCD_OPC_FilterValue, 37, 10, 0, 0, // Skip to: 6399 +/* 6389 */ MCD_OPC_CheckPredicate, 6, 181, 0, 0, // Skip to: 6575 +/* 6394 */ MCD_OPC_Decode, 208, 7, 138, 1, // Opcode: BEQ_MM +/* 6399 */ MCD_OPC_FilterValue, 38, 10, 0, 0, // Skip to: 6414 +/* 6404 */ MCD_OPC_CheckPredicate, 19, 166, 0, 0, // Skip to: 6575 +/* 6409 */ MCD_OPC_Decode, 135, 23, 139, 1, // Opcode: SWC1_MM +/* 6414 */ MCD_OPC_FilterValue, 39, 10, 0, 0, // Skip to: 6429 +/* 6419 */ MCD_OPC_CheckPredicate, 19, 151, 0, 0, // Skip to: 6575 +/* 6424 */ MCD_OPC_Decode, 137, 16, 139, 1, // Opcode: LWC1_MM +/* 6429 */ MCD_OPC_FilterValue, 44, 9, 0, 0, // Skip to: 6443 +/* 6434 */ MCD_OPC_CheckPredicate, 7, 136, 0, 0, // Skip to: 6575 +/* 6439 */ MCD_OPC_Decode, 251, 21, 97, // Opcode: SLTiu_MM +/* 6443 */ MCD_OPC_FilterValue, 45, 10, 0, 0, // Skip to: 6458 +/* 6448 */ MCD_OPC_CheckPredicate, 6, 122, 0, 0, // Skip to: 6575 +/* 6453 */ MCD_OPC_Decode, 198, 8, 138, 1, // Opcode: BNE_MM +/* 6458 */ MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 6473 +/* 6463 */ MCD_OPC_CheckPredicate, 18, 107, 0, 0, // Skip to: 6575 +/* 6468 */ MCD_OPC_Decode, 230, 20, 139, 1, // Opcode: SDC1_MM_D32 +/* 6473 */ MCD_OPC_FilterValue, 47, 10, 0, 0, // Skip to: 6488 +/* 6478 */ MCD_OPC_CheckPredicate, 18, 92, 0, 0, // Skip to: 6575 +/* 6483 */ MCD_OPC_Decode, 183, 15, 139, 1, // Opcode: LDC1_MM_D32 +/* 6488 */ MCD_OPC_FilterValue, 52, 9, 0, 0, // Skip to: 6502 +/* 6493 */ MCD_OPC_CheckPredicate, 6, 77, 0, 0, // Skip to: 6575 +/* 6498 */ MCD_OPC_Decode, 233, 6, 108, // Opcode: ANDi_MM +/* 6502 */ MCD_OPC_FilterValue, 53, 10, 0, 0, // Skip to: 6517 +/* 6507 */ MCD_OPC_CheckPredicate, 6, 63, 0, 0, // Skip to: 6575 +/* 6512 */ MCD_OPC_Decode, 145, 15, 136, 1, // Opcode: J_MM +/* 6517 */ MCD_OPC_FilterValue, 60, 10, 0, 0, // Skip to: 6532 +/* 6522 */ MCD_OPC_CheckPredicate, 6, 48, 0, 0, // Skip to: 6575 +/* 6527 */ MCD_OPC_Decode, 252, 14, 140, 1, // Opcode: JALX_MM +/* 6532 */ MCD_OPC_FilterValue, 61, 10, 0, 0, // Skip to: 6547 +/* 6537 */ MCD_OPC_CheckPredicate, 6, 33, 0, 0, // Skip to: 6575 +/* 6542 */ MCD_OPC_Decode, 253, 14, 136, 1, // Opcode: JAL_MM +/* 6547 */ MCD_OPC_FilterValue, 62, 9, 0, 0, // Skip to: 6561 +/* 6552 */ MCD_OPC_CheckPredicate, 7, 18, 0, 0, // Skip to: 6575 +/* 6557 */ MCD_OPC_Decode, 169, 23, 98, // Opcode: SW_MM +/* 6561 */ MCD_OPC_FilterValue, 63, 9, 0, 0, // Skip to: 6575 +/* 6566 */ MCD_OPC_CheckPredicate, 7, 4, 0, 0, // Skip to: 6575 +/* 6571 */ MCD_OPC_Decode, 179, 16, 98, // Opcode: LW_MM +/* 6575 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMicroMipsDSP32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 62, 10, 0, 0, // Skip to: 18 +/* 8 */ MCD_OPC_CheckPredicate, 8, 20, 0, 0, // Skip to: 33 +/* 13 */ MCD_OPC_Decode, 141, 23, 141, 1, // Opcode: SWDSP_MM +/* 18 */ MCD_OPC_FilterValue, 63, 10, 0, 0, // Skip to: 33 +/* 23 */ MCD_OPC_CheckPredicate, 8, 5, 0, 0, // Skip to: 33 +/* 28 */ MCD_OPC_Decode, 143, 16, 141, 1, // Opcode: LWDSP_MM +/* 33 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMicroMipsFP6432[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 21, 39, 1, 0, // Skip to: 303 +/* 8 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... +/* 11 */ MCD_OPC_FilterValue, 59, 48, 0, 0, // Skip to: 64 +/* 16 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 19 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 34 +/* 24 */ MCD_OPC_CheckPredicate, 20, 48, 1, 0, // Skip to: 333 +/* 29 */ MCD_OPC_Decode, 162, 18, 142, 1, // Opcode: MTC1_D64_MM +/* 34 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 49 +/* 39 */ MCD_OPC_CheckPredicate, 20, 33, 1, 0, // Skip to: 333 +/* 44 */ MCD_OPC_Decode, 146, 17, 143, 1, // Opcode: MFHC1_D64_MM +/* 49 */ MCD_OPC_FilterValue, 7, 23, 1, 0, // Skip to: 333 +/* 54 */ MCD_OPC_CheckPredicate, 20, 18, 1, 0, // Skip to: 333 +/* 59 */ MCD_OPC_Decode, 175, 18, 144, 1, // Opcode: MTHC1_D64_MM +/* 64 */ MCD_OPC_FilterValue, 123, 16, 0, 0, // Skip to: 85 +/* 69 */ MCD_OPC_CheckPredicate, 20, 3, 1, 0, // Skip to: 333 +/* 74 */ MCD_OPC_CheckField, 11, 5, 4, 252, 0, 0, // Skip to: 333 +/* 81 */ MCD_OPC_Decode, 230, 13, 122, // Opcode: FMOV_D64_MM +/* 85 */ MCD_OPC_FilterValue, 176, 2, 10, 0, 0, // Skip to: 101 +/* 91 */ MCD_OPC_CheckPredicate, 20, 237, 0, 0, // Skip to: 333 +/* 96 */ MCD_OPC_Decode, 140, 13, 145, 1, // Opcode: FADD_D64_MM +/* 101 */ MCD_OPC_FilterValue, 187, 2, 17, 0, 0, // Skip to: 124 +/* 107 */ MCD_OPC_CheckPredicate, 20, 221, 0, 0, // Skip to: 333 +/* 112 */ MCD_OPC_CheckField, 11, 5, 9, 214, 0, 0, // Skip to: 333 +/* 119 */ MCD_OPC_Decode, 216, 10, 146, 1, // Opcode: CVT_W_D64_MM +/* 124 */ MCD_OPC_FilterValue, 240, 2, 10, 0, 0, // Skip to: 140 +/* 130 */ MCD_OPC_CheckPredicate, 20, 198, 0, 0, // Skip to: 333 +/* 135 */ MCD_OPC_Decode, 158, 14, 145, 1, // Opcode: FSUB_D64_MM +/* 140 */ MCD_OPC_FilterValue, 176, 3, 10, 0, 0, // Skip to: 156 +/* 146 */ MCD_OPC_CheckPredicate, 20, 182, 0, 0, // Skip to: 333 +/* 151 */ MCD_OPC_Decode, 241, 13, 145, 1, // Opcode: FMUL_D64_MM +/* 156 */ MCD_OPC_FilterValue, 240, 3, 10, 0, 0, // Skip to: 172 +/* 162 */ MCD_OPC_CheckPredicate, 20, 166, 0, 0, // Skip to: 333 +/* 167 */ MCD_OPC_Decode, 179, 13, 145, 1, // Opcode: FDIV_D64_MM +/* 172 */ MCD_OPC_FilterValue, 187, 4, 45, 0, 0, // Skip to: 223 +/* 178 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 181 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 195 +/* 186 */ MCD_OPC_CheckPredicate, 20, 142, 0, 0, // Skip to: 333 +/* 191 */ MCD_OPC_Decode, 176, 20, 122, // Opcode: RSQRT_D64_MM +/* 195 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 209 +/* 200 */ MCD_OPC_CheckPredicate, 20, 128, 0, 0, // Skip to: 333 +/* 205 */ MCD_OPC_Decode, 150, 14, 122, // Opcode: FSQRT_D64_MM +/* 209 */ MCD_OPC_FilterValue, 10, 119, 0, 0, // Skip to: 333 +/* 214 */ MCD_OPC_CheckPredicate, 20, 114, 0, 0, // Skip to: 333 +/* 219 */ MCD_OPC_Decode, 137, 20, 122, // Opcode: RECIP_D64_MM +/* 223 */ MCD_OPC_FilterValue, 251, 6, 104, 0, 0, // Skip to: 333 +/* 229 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 232 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 246 +/* 237 */ MCD_OPC_CheckPredicate, 20, 91, 0, 0, // Skip to: 333 +/* 242 */ MCD_OPC_Decode, 189, 10, 121, // Opcode: CVT_D64_S_MM +/* 246 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 261 +/* 251 */ MCD_OPC_CheckPredicate, 20, 77, 0, 0, // Skip to: 333 +/* 256 */ MCD_OPC_Decode, 205, 10, 146, 1, // Opcode: CVT_S_D64_MM +/* 261 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 275 +/* 266 */ MCD_OPC_CheckPredicate, 20, 62, 0, 0, // Skip to: 333 +/* 271 */ MCD_OPC_Decode, 133, 13, 122, // Opcode: FABS_D64_MM +/* 275 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 289 +/* 280 */ MCD_OPC_CheckPredicate, 20, 48, 0, 0, // Skip to: 333 +/* 285 */ MCD_OPC_Decode, 250, 13, 122, // Opcode: FNEG_D64_MM +/* 289 */ MCD_OPC_FilterValue, 6, 39, 0, 0, // Skip to: 333 +/* 294 */ MCD_OPC_CheckPredicate, 20, 34, 0, 0, // Skip to: 333 +/* 299 */ MCD_OPC_Decode, 191, 10, 121, // Opcode: CVT_D64_W_MM +/* 303 */ MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 318 +/* 308 */ MCD_OPC_CheckPredicate, 23, 20, 0, 0, // Skip to: 333 +/* 313 */ MCD_OPC_Decode, 229, 20, 139, 1, // Opcode: SDC1_D64_MMR6 +/* 318 */ MCD_OPC_FilterValue, 47, 10, 0, 0, // Skip to: 333 +/* 323 */ MCD_OPC_CheckPredicate, 23, 5, 0, 0, // Skip to: 333 +/* 328 */ MCD_OPC_Decode, 182, 15, 139, 1, // Opcode: LDC1_D64_MMR6 +/* 333 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMicroMipsR616[] = { +/* 0 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 3 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 41 +/* 8 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 11 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 26 +/* 16 */ MCD_OPC_CheckPredicate, 24, 173, 1, 0, // Skip to: 450 +/* 21 */ MCD_OPC_Decode, 171, 6, 147, 1, // Opcode: ADDU16_MMR6 +/* 26 */ MCD_OPC_FilterValue, 1, 163, 1, 0, // Skip to: 450 +/* 31 */ MCD_OPC_CheckPredicate, 24, 158, 1, 0, // Skip to: 450 +/* 36 */ MCD_OPC_Decode, 224, 22, 147, 1, // Opcode: SUBU16_MMR6 +/* 41 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 55 +/* 46 */ MCD_OPC_CheckPredicate, 24, 143, 1, 0, // Skip to: 450 +/* 51 */ MCD_OPC_Decode, 209, 17, 33, // Opcode: MOVE16_MMR6 +/* 55 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 91 +/* 60 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 63 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 77 +/* 68 */ MCD_OPC_CheckPredicate, 24, 121, 1, 0, // Skip to: 450 +/* 73 */ MCD_OPC_Decode, 221, 21, 34, // Opcode: SLL16_MMR6 +/* 77 */ MCD_OPC_FilterValue, 1, 112, 1, 0, // Skip to: 450 +/* 82 */ MCD_OPC_CheckPredicate, 24, 107, 1, 0, // Skip to: 450 +/* 87 */ MCD_OPC_Decode, 162, 22, 34, // Opcode: SRL16_MMR6 +/* 91 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 105 +/* 96 */ MCD_OPC_CheckPredicate, 24, 93, 1, 0, // Skip to: 450 +/* 101 */ MCD_OPC_Decode, 222, 6, 35, // Opcode: ANDI16_MMR6 +/* 105 */ MCD_OPC_FilterValue, 17, 228, 0, 0, // Skip to: 338 +/* 110 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... +/* 113 */ MCD_OPC_FilterValue, 0, 206, 0, 0, // Skip to: 324 +/* 118 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 121 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 159 +/* 126 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 129 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 144 +/* 134 */ MCD_OPC_CheckPredicate, 24, 55, 1, 0, // Skip to: 450 +/* 139 */ MCD_OPC_Decode, 159, 19, 148, 1, // Opcode: NOT16_MMR6 +/* 144 */ MCD_OPC_FilterValue, 1, 45, 1, 0, // Skip to: 450 +/* 149 */ MCD_OPC_CheckPredicate, 24, 40, 1, 0, // Skip to: 450 +/* 154 */ MCD_OPC_Decode, 174, 24, 149, 1, // Opcode: XOR16_MMR6 +/* 159 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 197 +/* 164 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 167 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 182 +/* 172 */ MCD_OPC_CheckPredicate, 24, 17, 1, 0, // Skip to: 450 +/* 177 */ MCD_OPC_Decode, 218, 6, 149, 1, // Opcode: AND16_MMR6 +/* 182 */ MCD_OPC_FilterValue, 1, 7, 1, 0, // Skip to: 450 +/* 187 */ MCD_OPC_CheckPredicate, 24, 2, 1, 0, // Skip to: 450 +/* 192 */ MCD_OPC_Decode, 165, 19, 149, 1, // Opcode: OR16_MMR6 +/* 197 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 233 +/* 202 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 205 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 219 +/* 210 */ MCD_OPC_CheckPredicate, 24, 235, 0, 0, // Skip to: 450 +/* 215 */ MCD_OPC_Decode, 155, 16, 38, // Opcode: LWM16_MMR6 +/* 219 */ MCD_OPC_FilterValue, 1, 226, 0, 0, // Skip to: 450 +/* 224 */ MCD_OPC_CheckPredicate, 24, 221, 0, 0, // Skip to: 450 +/* 229 */ MCD_OPC_Decode, 152, 23, 38, // Opcode: SWM16_MMR6 +/* 233 */ MCD_OPC_FilterValue, 3, 212, 0, 0, // Skip to: 450 +/* 238 */ MCD_OPC_ExtractField, 3, 2, // Inst{4-3} ... +/* 241 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 256 +/* 246 */ MCD_OPC_CheckPredicate, 24, 199, 0, 0, // Skip to: 450 +/* 251 */ MCD_OPC_Decode, 137, 15, 150, 1, // Opcode: JRC16_MMR6 +/* 256 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 271 +/* 261 */ MCD_OPC_CheckPredicate, 24, 184, 0, 0, // Skip to: 450 +/* 266 */ MCD_OPC_Decode, 239, 14, 150, 1, // Opcode: JALRC16_MMR6 +/* 271 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 286 +/* 276 */ MCD_OPC_CheckPredicate, 24, 169, 0, 0, // Skip to: 450 +/* 281 */ MCD_OPC_Decode, 138, 15, 151, 1, // Opcode: JRCADDIUSP_MMR6 +/* 286 */ MCD_OPC_FilterValue, 3, 159, 0, 0, // Skip to: 450 +/* 291 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 294 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 309 +/* 299 */ MCD_OPC_CheckPredicate, 24, 146, 0, 0, // Skip to: 450 +/* 304 */ MCD_OPC_Decode, 213, 8, 152, 1, // Opcode: BREAK16_MMR6 +/* 309 */ MCD_OPC_FilterValue, 1, 136, 0, 0, // Skip to: 450 +/* 314 */ MCD_OPC_CheckPredicate, 24, 131, 0, 0, // Skip to: 450 +/* 319 */ MCD_OPC_Decode, 221, 20, 152, 1, // Opcode: SDBBP16_MMR6 +/* 324 */ MCD_OPC_FilterValue, 1, 121, 0, 0, // Skip to: 450 +/* 329 */ MCD_OPC_CheckPredicate, 24, 116, 0, 0, // Skip to: 450 +/* 334 */ MCD_OPC_Decode, 213, 17, 48, // Opcode: MOVEP_MMR6 +/* 338 */ MCD_OPC_FilterValue, 34, 9, 0, 0, // Skip to: 352 +/* 343 */ MCD_OPC_CheckPredicate, 24, 102, 0, 0, // Skip to: 450 +/* 348 */ MCD_OPC_Decode, 195, 20, 32, // Opcode: SB16_MMR6 +/* 352 */ MCD_OPC_FilterValue, 35, 9, 0, 0, // Skip to: 366 +/* 357 */ MCD_OPC_CheckPredicate, 24, 88, 0, 0, // Skip to: 450 +/* 362 */ MCD_OPC_Decode, 202, 7, 49, // Opcode: BEQZC16_MMR6 +/* 366 */ MCD_OPC_FilterValue, 42, 9, 0, 0, // Skip to: 380 +/* 371 */ MCD_OPC_CheckPredicate, 24, 74, 0, 0, // Skip to: 450 +/* 376 */ MCD_OPC_Decode, 145, 21, 32, // Opcode: SH16_MMR6 +/* 380 */ MCD_OPC_FilterValue, 43, 9, 0, 0, // Skip to: 394 +/* 385 */ MCD_OPC_CheckPredicate, 24, 60, 0, 0, // Skip to: 450 +/* 390 */ MCD_OPC_Decode, 192, 8, 49, // Opcode: BNEZC16_MMR6 +/* 394 */ MCD_OPC_FilterValue, 50, 9, 0, 0, // Skip to: 408 +/* 399 */ MCD_OPC_CheckPredicate, 24, 46, 0, 0, // Skip to: 450 +/* 404 */ MCD_OPC_Decode, 164, 23, 42, // Opcode: SWSP_MMR6 +/* 408 */ MCD_OPC_FilterValue, 51, 9, 0, 0, // Skip to: 422 +/* 413 */ MCD_OPC_CheckPredicate, 24, 32, 0, 0, // Skip to: 450 +/* 418 */ MCD_OPC_Decode, 162, 7, 50, // Opcode: BC16_MMR6 +/* 422 */ MCD_OPC_FilterValue, 58, 9, 0, 0, // Skip to: 436 +/* 427 */ MCD_OPC_CheckPredicate, 24, 18, 0, 0, // Skip to: 450 +/* 432 */ MCD_OPC_Decode, 130, 23, 32, // Opcode: SW16_MMR6 +/* 436 */ MCD_OPC_FilterValue, 59, 9, 0, 0, // Skip to: 450 +/* 441 */ MCD_OPC_CheckPredicate, 24, 4, 0, 0, // Skip to: 450 +/* 446 */ MCD_OPC_Decode, 232, 15, 51, // Opcode: LI16_MMR6 +/* 450 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMicroMipsR632[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 0, 98, 4, 0, // Skip to: 1130 +/* 8 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 11 */ MCD_OPC_FilterValue, 0, 112, 0, 0, // Skip to: 128 +/* 16 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 19 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 78 +/* 24 */ MCD_OPC_ExtractField, 11, 15, // Inst{25-11} ... +/* 27 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 41 +/* 32 */ MCD_OPC_CheckPredicate, 24, 32, 0, 0, // Skip to: 69 +/* 37 */ MCD_OPC_Decode, 187, 22, 10, // Opcode: SSNOP_MMR6 +/* 41 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 55 +/* 46 */ MCD_OPC_CheckPredicate, 24, 18, 0, 0, // Skip to: 69 +/* 51 */ MCD_OPC_Decode, 208, 12, 10, // Opcode: EHB_MMR6 +/* 55 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 69 +/* 60 */ MCD_OPC_CheckPredicate, 24, 4, 0, 0, // Skip to: 69 +/* 65 */ MCD_OPC_Decode, 183, 19, 10, // Opcode: PAUSE_MMR6 +/* 69 */ MCD_OPC_CheckPredicate, 24, 80, 12, 0, // Skip to: 3226 +/* 74 */ MCD_OPC_Decode, 236, 21, 52, // Opcode: SLL_MMR6 +/* 78 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 92 +/* 83 */ MCD_OPC_CheckPredicate, 24, 66, 12, 0, // Skip to: 3226 +/* 88 */ MCD_OPC_Decode, 254, 20, 55, // Opcode: SELEQZ_MMR6 +/* 92 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 106 +/* 97 */ MCD_OPC_CheckPredicate, 24, 52, 12, 0, // Skip to: 3226 +/* 102 */ MCD_OPC_Decode, 133, 21, 55, // Opcode: SELNEZ_MMR6 +/* 106 */ MCD_OPC_FilterValue, 7, 43, 12, 0, // Skip to: 3226 +/* 111 */ MCD_OPC_CheckPredicate, 24, 38, 12, 0, // Skip to: 3226 +/* 116 */ MCD_OPC_CheckField, 14, 2, 0, 31, 12, 0, // Skip to: 3226 +/* 123 */ MCD_OPC_Decode, 130, 20, 153, 1, // Opcode: RDHWR_MMR6 +/* 128 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 142 +/* 133 */ MCD_OPC_CheckPredicate, 24, 16, 12, 0, // Skip to: 3226 +/* 138 */ MCD_OPC_Decode, 216, 8, 56, // Opcode: BREAK_MMR6 +/* 142 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 156 +/* 147 */ MCD_OPC_CheckPredicate, 24, 2, 12, 0, // Skip to: 3226 +/* 152 */ MCD_OPC_Decode, 232, 14, 57, // Opcode: INS_MMR6 +/* 156 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 178 +/* 161 */ MCD_OPC_CheckPredicate, 24, 244, 11, 0, // Skip to: 3226 +/* 166 */ MCD_OPC_CheckField, 6, 3, 0, 237, 11, 0, // Skip to: 3226 +/* 173 */ MCD_OPC_Decode, 248, 15, 154, 1, // Opcode: LSA_MMR6 +/* 178 */ MCD_OPC_FilterValue, 16, 136, 0, 0, // Skip to: 319 +/* 183 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 186 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 207 +/* 191 */ MCD_OPC_CheckPredicate, 24, 214, 11, 0, // Skip to: 3226 +/* 196 */ MCD_OPC_CheckField, 16, 5, 0, 207, 11, 0, // Skip to: 3226 +/* 203 */ MCD_OPC_Decode, 195, 9, 25, // Opcode: CLZ_MMR6 +/* 207 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 221 +/* 212 */ MCD_OPC_CheckPredicate, 24, 193, 11, 0, // Skip to: 3226 +/* 217 */ MCD_OPC_Decode, 200, 6, 55, // Opcode: ADD_MMR6 +/* 221 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 235 +/* 226 */ MCD_OPC_CheckPredicate, 24, 179, 11, 0, // Skip to: 3226 +/* 231 */ MCD_OPC_Decode, 176, 6, 55, // Opcode: ADDU_MMR6 +/* 235 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 249 +/* 240 */ MCD_OPC_CheckPredicate, 24, 165, 11, 0, // Skip to: 3226 +/* 245 */ MCD_OPC_Decode, 247, 22, 55, // Opcode: SUB_MMR6 +/* 249 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 263 +/* 254 */ MCD_OPC_CheckPredicate, 24, 151, 11, 0, // Skip to: 3226 +/* 259 */ MCD_OPC_Decode, 229, 22, 55, // Opcode: SUBU_MMR6 +/* 263 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 277 +/* 268 */ MCD_OPC_CheckPredicate, 24, 137, 11, 0, // Skip to: 3226 +/* 273 */ MCD_OPC_Decode, 228, 6, 55, // Opcode: AND_MMR6 +/* 277 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 291 +/* 282 */ MCD_OPC_CheckPredicate, 24, 123, 11, 0, // Skip to: 3226 +/* 287 */ MCD_OPC_Decode, 172, 19, 55, // Opcode: OR_MMR6 +/* 291 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 305 +/* 296 */ MCD_OPC_CheckPredicate, 24, 109, 11, 0, // Skip to: 3226 +/* 301 */ MCD_OPC_Decode, 155, 19, 55, // Opcode: NOR_MMR6 +/* 305 */ MCD_OPC_FilterValue, 12, 100, 11, 0, // Skip to: 3226 +/* 310 */ MCD_OPC_CheckPredicate, 24, 95, 11, 0, // Skip to: 3226 +/* 315 */ MCD_OPC_Decode, 181, 24, 55, // Opcode: XOR_MMR6 +/* 319 */ MCD_OPC_FilterValue, 24, 115, 0, 0, // Skip to: 439 +/* 324 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 327 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 341 +/* 332 */ MCD_OPC_CheckPredicate, 24, 73, 11, 0, // Skip to: 3226 +/* 337 */ MCD_OPC_Decode, 246, 18, 55, // Opcode: MUL_MMR6 +/* 341 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 355 +/* 346 */ MCD_OPC_CheckPredicate, 24, 59, 11, 0, // Skip to: 3226 +/* 351 */ MCD_OPC_Decode, 203, 18, 55, // Opcode: MUH_MMR6 +/* 355 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 369 +/* 360 */ MCD_OPC_CheckPredicate, 24, 45, 11, 0, // Skip to: 3226 +/* 365 */ MCD_OPC_Decode, 239, 18, 55, // Opcode: MULU_MMR6 +/* 369 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 383 +/* 374 */ MCD_OPC_CheckPredicate, 24, 31, 11, 0, // Skip to: 3226 +/* 379 */ MCD_OPC_Decode, 201, 18, 55, // Opcode: MUHU_MMR6 +/* 383 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 397 +/* 388 */ MCD_OPC_CheckPredicate, 24, 17, 11, 0, // Skip to: 3226 +/* 393 */ MCD_OPC_Decode, 222, 11, 55, // Opcode: DIV_MMR6 +/* 397 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 411 +/* 402 */ MCD_OPC_CheckPredicate, 24, 3, 11, 0, // Skip to: 3226 +/* 407 */ MCD_OPC_Decode, 198, 17, 55, // Opcode: MOD_MMR6 +/* 411 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 425 +/* 416 */ MCD_OPC_CheckPredicate, 24, 245, 10, 0, // Skip to: 3226 +/* 421 */ MCD_OPC_Decode, 220, 11, 55, // Opcode: DIVU_MMR6 +/* 425 */ MCD_OPC_FilterValue, 7, 236, 10, 0, // Skip to: 3226 +/* 430 */ MCD_OPC_CheckPredicate, 24, 231, 10, 0, // Skip to: 3226 +/* 435 */ MCD_OPC_Decode, 196, 17, 55, // Opcode: MODU_MMR6 +/* 439 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 461 +/* 444 */ MCD_OPC_CheckPredicate, 24, 217, 10, 0, // Skip to: 3226 +/* 449 */ MCD_OPC_CheckField, 6, 3, 0, 210, 10, 0, // Skip to: 3226 +/* 456 */ MCD_OPC_Decode, 212, 6, 155, 1, // Opcode: ALIGN_MMR6 +/* 461 */ MCD_OPC_FilterValue, 44, 9, 0, 0, // Skip to: 475 +/* 466 */ MCD_OPC_CheckPredicate, 24, 195, 10, 0, // Skip to: 3226 +/* 471 */ MCD_OPC_Decode, 128, 13, 66, // Opcode: EXT_MMR6 +/* 475 */ MCD_OPC_FilterValue, 52, 45, 0, 0, // Skip to: 525 +/* 480 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 483 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 504 +/* 488 */ MCD_OPC_CheckPredicate, 24, 173, 10, 0, // Skip to: 3226 +/* 493 */ MCD_OPC_CheckField, 14, 2, 0, 166, 10, 0, // Skip to: 3226 +/* 500 */ MCD_OPC_Decode, 141, 17, 68, // Opcode: MFHC0_MMR6 +/* 504 */ MCD_OPC_FilterValue, 11, 157, 10, 0, // Skip to: 3226 +/* 509 */ MCD_OPC_CheckPredicate, 24, 152, 10, 0, // Skip to: 3226 +/* 514 */ MCD_OPC_CheckField, 14, 2, 0, 145, 10, 0, // Skip to: 3226 +/* 521 */ MCD_OPC_Decode, 170, 18, 69, // Opcode: MTHC0_MMR6 +/* 525 */ MCD_OPC_FilterValue, 60, 66, 2, 0, // Skip to: 1108 +/* 530 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 533 */ MCD_OPC_FilterValue, 0, 138, 0, 0, // Skip to: 676 +/* 538 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 541 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 555 +/* 546 */ MCD_OPC_CheckPredicate, 24, 115, 10, 0, // Skip to: 3226 +/* 551 */ MCD_OPC_Decode, 130, 17, 68, // Opcode: MFC0_MMR6 +/* 555 */ MCD_OPC_FilterValue, 5, 45, 0, 0, // Skip to: 605 +/* 560 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 563 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 584 +/* 568 */ MCD_OPC_CheckPredicate, 24, 93, 10, 0, // Skip to: 3226 +/* 573 */ MCD_OPC_CheckField, 21, 5, 0, 86, 10, 0, // Skip to: 3226 +/* 580 */ MCD_OPC_Decode, 203, 12, 92, // Opcode: DVP_MMR6 +/* 584 */ MCD_OPC_FilterValue, 7, 77, 10, 0, // Skip to: 3226 +/* 589 */ MCD_OPC_CheckPredicate, 24, 72, 10, 0, // Skip to: 3226 +/* 594 */ MCD_OPC_CheckField, 21, 5, 0, 65, 10, 0, // Skip to: 3226 +/* 601 */ MCD_OPC_Decode, 226, 12, 92, // Opcode: EVP_MMR6 +/* 605 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 619 +/* 610 */ MCD_OPC_CheckPredicate, 24, 51, 10, 0, // Skip to: 3226 +/* 615 */ MCD_OPC_Decode, 158, 18, 69, // Opcode: MTC0_MMR6 +/* 619 */ MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 640 +/* 624 */ MCD_OPC_CheckPredicate, 24, 37, 10, 0, // Skip to: 3226 +/* 629 */ MCD_OPC_CheckField, 11, 3, 1, 30, 10, 0, // Skip to: 3226 +/* 636 */ MCD_OPC_Decode, 133, 8, 86, // Opcode: BITSWAP_MMR6 +/* 640 */ MCD_OPC_FilterValue, 28, 21, 10, 0, // Skip to: 3226 +/* 645 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 648 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 662 +/* 653 */ MCD_OPC_CheckPredicate, 24, 8, 10, 0, // Skip to: 3226 +/* 658 */ MCD_OPC_Decode, 243, 14, 80, // Opcode: JALRC_MMR6 +/* 662 */ MCD_OPC_FilterValue, 3, 255, 9, 0, // Skip to: 3226 +/* 667 */ MCD_OPC_CheckPredicate, 24, 250, 9, 0, // Skip to: 3226 +/* 672 */ MCD_OPC_Decode, 242, 14, 80, // Opcode: JALRC_HB_MMR6 +/* 676 */ MCD_OPC_FilterValue, 1, 10, 1, 0, // Skip to: 947 +/* 681 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 684 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 734 +/* 689 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 692 */ MCD_OPC_FilterValue, 13, 16, 0, 0, // Skip to: 713 +/* 697 */ MCD_OPC_CheckPredicate, 24, 220, 9, 0, // Skip to: 3226 +/* 702 */ MCD_OPC_CheckField, 16, 10, 0, 213, 9, 0, // Skip to: 3226 +/* 709 */ MCD_OPC_Decode, 236, 23, 10, // Opcode: TLBINV_MMR6 +/* 713 */ MCD_OPC_FilterValue, 29, 204, 9, 0, // Skip to: 3226 +/* 718 */ MCD_OPC_CheckPredicate, 24, 199, 9, 0, // Skip to: 3226 +/* 723 */ MCD_OPC_CheckField, 21, 5, 0, 192, 9, 0, // Skip to: 3226 +/* 730 */ MCD_OPC_Decode, 233, 11, 92, // Opcode: DI_MMR6 +/* 734 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 770 +/* 739 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 742 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 756 +/* 747 */ MCD_OPC_CheckPredicate, 24, 170, 9, 0, // Skip to: 3226 +/* 752 */ MCD_OPC_Decode, 174, 9, 80, // Opcode: CLO_MMR6 +/* 756 */ MCD_OPC_FilterValue, 20, 161, 9, 0, // Skip to: 3226 +/* 761 */ MCD_OPC_CheckPredicate, 24, 156, 9, 0, // Skip to: 3226 +/* 766 */ MCD_OPC_Decode, 137, 17, 90, // Opcode: MFC2_MMR6 +/* 770 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 820 +/* 775 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 778 */ MCD_OPC_FilterValue, 13, 16, 0, 0, // Skip to: 799 +/* 783 */ MCD_OPC_CheckPredicate, 24, 134, 9, 0, // Skip to: 3226 +/* 788 */ MCD_OPC_CheckField, 16, 10, 0, 127, 9, 0, // Skip to: 3226 +/* 795 */ MCD_OPC_Decode, 234, 23, 10, // Opcode: TLBINVF_MMR6 +/* 799 */ MCD_OPC_FilterValue, 29, 118, 9, 0, // Skip to: 3226 +/* 804 */ MCD_OPC_CheckPredicate, 24, 113, 9, 0, // Skip to: 3226 +/* 809 */ MCD_OPC_CheckField, 21, 5, 0, 106, 9, 0, // Skip to: 3226 +/* 816 */ MCD_OPC_Decode, 212, 12, 92, // Opcode: EI_MMR6 +/* 820 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 841 +/* 825 */ MCD_OPC_CheckPredicate, 24, 92, 9, 0, // Skip to: 3226 +/* 830 */ MCD_OPC_CheckField, 6, 5, 20, 85, 9, 0, // Skip to: 3226 +/* 837 */ MCD_OPC_Decode, 166, 18, 91, // Opcode: MTC2_MMR6 +/* 841 */ MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 869 +/* 846 */ MCD_OPC_CheckPredicate, 25, 71, 9, 0, // Skip to: 3226 +/* 851 */ MCD_OPC_CheckField, 21, 5, 0, 64, 9, 0, // Skip to: 3226 +/* 858 */ MCD_OPC_CheckField, 6, 5, 5, 57, 9, 0, // Skip to: 3226 +/* 865 */ MCD_OPC_Decode, 185, 14, 92, // Opcode: GINVI_MMR6 +/* 869 */ MCD_OPC_FilterValue, 5, 23, 0, 0, // Skip to: 897 +/* 874 */ MCD_OPC_CheckPredicate, 24, 43, 9, 0, // Skip to: 3226 +/* 879 */ MCD_OPC_CheckField, 21, 5, 0, 36, 9, 0, // Skip to: 3226 +/* 886 */ MCD_OPC_CheckField, 6, 5, 13, 29, 9, 0, // Skip to: 3226 +/* 893 */ MCD_OPC_Decode, 180, 23, 87, // Opcode: SYNC_MMR6 +/* 897 */ MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 926 +/* 902 */ MCD_OPC_CheckPredicate, 25, 15, 9, 0, // Skip to: 3226 +/* 907 */ MCD_OPC_CheckField, 21, 5, 0, 8, 9, 0, // Skip to: 3226 +/* 914 */ MCD_OPC_CheckField, 6, 3, 5, 1, 9, 0, // Skip to: 3226 +/* 921 */ MCD_OPC_Decode, 188, 14, 156, 1, // Opcode: GINVT_MMR6 +/* 926 */ MCD_OPC_FilterValue, 7, 247, 8, 0, // Skip to: 3226 +/* 931 */ MCD_OPC_CheckPredicate, 24, 242, 8, 0, // Skip to: 3226 +/* 936 */ MCD_OPC_CheckField, 6, 5, 12, 235, 8, 0, // Skip to: 3226 +/* 943 */ MCD_OPC_Decode, 171, 24, 80, // Opcode: WSBH_MMR6 +/* 947 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 997 +/* 952 */ MCD_OPC_ExtractField, 6, 8, // Inst{13-6} ... +/* 955 */ MCD_OPC_FilterValue, 52, 9, 0, 0, // Skip to: 969 +/* 960 */ MCD_OPC_CheckPredicate, 24, 213, 8, 0, // Skip to: 3226 +/* 965 */ MCD_OPC_Decode, 147, 17, 90, // Opcode: MFHC2_MMR6 +/* 969 */ MCD_OPC_FilterValue, 77, 9, 0, 0, // Skip to: 983 +/* 974 */ MCD_OPC_CheckPredicate, 24, 199, 8, 0, // Skip to: 3226 +/* 979 */ MCD_OPC_Decode, 163, 24, 88, // Opcode: WAIT_MMR6 +/* 983 */ MCD_OPC_FilterValue, 116, 190, 8, 0, // Skip to: 3226 +/* 988 */ MCD_OPC_CheckPredicate, 24, 185, 8, 0, // Skip to: 3226 +/* 993 */ MCD_OPC_Decode, 176, 18, 91, // Opcode: MTHC2_MMR6 +/* 997 */ MCD_OPC_FilterValue, 3, 176, 8, 0, // Skip to: 3226 +/* 1002 */ MCD_OPC_ExtractField, 6, 8, // Inst{13-6} ... +/* 1005 */ MCD_OPC_FilterValue, 109, 9, 0, 0, // Skip to: 1019 +/* 1010 */ MCD_OPC_CheckPredicate, 24, 163, 8, 0, // Skip to: 3226 +/* 1015 */ MCD_OPC_Decode, 224, 20, 88, // Opcode: SDBBP_MMR6 +/* 1019 */ MCD_OPC_FilterValue, 133, 1, 9, 0, 0, // Skip to: 1034 +/* 1025 */ MCD_OPC_CheckPredicate, 24, 148, 8, 0, // Skip to: 3226 +/* 1030 */ MCD_OPC_Decode, 132, 20, 80, // Opcode: RDPGPR_MMR6 +/* 1034 */ MCD_OPC_FilterValue, 141, 1, 16, 0, 0, // Skip to: 1056 +/* 1040 */ MCD_OPC_CheckPredicate, 24, 133, 8, 0, // Skip to: 3226 +/* 1045 */ MCD_OPC_CheckField, 16, 10, 0, 126, 8, 0, // Skip to: 3226 +/* 1052 */ MCD_OPC_Decode, 208, 11, 10, // Opcode: DERET_MMR6 +/* 1056 */ MCD_OPC_FilterValue, 197, 1, 9, 0, 0, // Skip to: 1071 +/* 1062 */ MCD_OPC_CheckPredicate, 24, 111, 8, 0, // Skip to: 3226 +/* 1067 */ MCD_OPC_Decode, 167, 24, 80, // Opcode: WRPGPR_MMR6 +/* 1071 */ MCD_OPC_FilterValue, 205, 1, 101, 8, 0, // Skip to: 3226 +/* 1077 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 1080 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1094 +/* 1085 */ MCD_OPC_CheckPredicate, 24, 88, 8, 0, // Skip to: 3226 +/* 1090 */ MCD_OPC_Decode, 221, 12, 10, // Opcode: ERET_MMR6 +/* 1094 */ MCD_OPC_FilterValue, 1, 79, 8, 0, // Skip to: 3226 +/* 1099 */ MCD_OPC_CheckPredicate, 24, 74, 8, 0, // Skip to: 3226 +/* 1104 */ MCD_OPC_Decode, 218, 12, 10, // Opcode: ERETNC_MMR6 +/* 1108 */ MCD_OPC_FilterValue, 63, 65, 8, 0, // Skip to: 3226 +/* 1113 */ MCD_OPC_CheckPredicate, 24, 60, 8, 0, // Skip to: 3226 +/* 1118 */ MCD_OPC_CheckField, 22, 4, 0, 53, 8, 0, // Skip to: 3226 +/* 1125 */ MCD_OPC_Decode, 209, 21, 157, 1, // Opcode: SIGRIE_MMR6 +/* 1130 */ MCD_OPC_FilterValue, 4, 26, 0, 0, // Skip to: 1161 +/* 1135 */ MCD_OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 1152 +/* 1140 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 1152 +/* 1147 */ MCD_OPC_Decode, 251, 15, 158, 1, // Opcode: LUI_MMR6 +/* 1152 */ MCD_OPC_CheckPredicate, 24, 21, 8, 0, // Skip to: 3226 +/* 1157 */ MCD_OPC_Decode, 247, 6, 108, // Opcode: AUI_MMR6 +/* 1161 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1176 +/* 1166 */ MCD_OPC_CheckPredicate, 24, 7, 8, 0, // Skip to: 3226 +/* 1171 */ MCD_OPC_Decode, 166, 15, 159, 1, // Opcode: LBU_MMR6 +/* 1176 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1190 +/* 1181 */ MCD_OPC_CheckPredicate, 24, 248, 7, 0, // Skip to: 3226 +/* 1186 */ MCD_OPC_Decode, 203, 20, 98, // Opcode: SB_MMR6 +/* 1190 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 1205 +/* 1195 */ MCD_OPC_CheckPredicate, 24, 234, 7, 0, // Skip to: 3226 +/* 1200 */ MCD_OPC_Decode, 171, 15, 159, 1, // Opcode: LB_MMR6 +/* 1205 */ MCD_OPC_FilterValue, 8, 105, 0, 0, // Skip to: 1315 +/* 1210 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 1213 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1235 +/* 1218 */ MCD_OPC_CheckPredicate, 24, 211, 7, 0, // Skip to: 3226 +/* 1223 */ MCD_OPC_CheckField, 11, 1, 0, 204, 7, 0, // Skip to: 3226 +/* 1230 */ MCD_OPC_Decode, 139, 16, 160, 1, // Opcode: LWC2_MMR6 +/* 1235 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1257 +/* 1240 */ MCD_OPC_CheckPredicate, 24, 189, 7, 0, // Skip to: 3226 +/* 1245 */ MCD_OPC_CheckField, 11, 1, 0, 182, 7, 0, // Skip to: 3226 +/* 1252 */ MCD_OPC_Decode, 186, 15, 160, 1, // Opcode: LDC2_MMR6 +/* 1257 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1271 +/* 1262 */ MCD_OPC_CheckPredicate, 24, 167, 7, 0, // Skip to: 3226 +/* 1267 */ MCD_OPC_Decode, 250, 8, 100, // Opcode: CACHE_MMR6 +/* 1271 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 1293 +/* 1276 */ MCD_OPC_CheckPredicate, 24, 153, 7, 0, // Skip to: 3226 +/* 1281 */ MCD_OPC_CheckField, 11, 1, 0, 146, 7, 0, // Skip to: 3226 +/* 1288 */ MCD_OPC_Decode, 137, 23, 160, 1, // Opcode: SWC2_MMR6 +/* 1293 */ MCD_OPC_FilterValue, 10, 136, 7, 0, // Skip to: 3226 +/* 1298 */ MCD_OPC_CheckPredicate, 24, 131, 7, 0, // Skip to: 3226 +/* 1303 */ MCD_OPC_CheckField, 11, 1, 0, 124, 7, 0, // Skip to: 3226 +/* 1310 */ MCD_OPC_Decode, 233, 20, 160, 1, // Opcode: SDC2_MMR6 +/* 1315 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 1329 +/* 1320 */ MCD_OPC_CheckPredicate, 24, 109, 7, 0, // Skip to: 3226 +/* 1325 */ MCD_OPC_Decode, 139, 6, 97, // Opcode: ADDIU_MMR6 +/* 1329 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 1343 +/* 1334 */ MCD_OPC_CheckPredicate, 24, 95, 7, 0, // Skip to: 3226 +/* 1339 */ MCD_OPC_Decode, 205, 21, 98, // Opcode: SH_MMR6 +/* 1343 */ MCD_OPC_FilterValue, 16, 78, 0, 0, // Skip to: 1426 +/* 1348 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 1351 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 1366 +/* 1356 */ MCD_OPC_CheckPredicate, 26, 73, 7, 0, // Skip to: 3226 +/* 1361 */ MCD_OPC_Decode, 165, 7, 161, 1, // Opcode: BC1EQZC_MMR6 +/* 1366 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 1381 +/* 1371 */ MCD_OPC_CheckPredicate, 26, 58, 7, 0, // Skip to: 3226 +/* 1376 */ MCD_OPC_Decode, 170, 7, 161, 1, // Opcode: BC1NEZC_MMR6 +/* 1381 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1396 +/* 1386 */ MCD_OPC_CheckPredicate, 24, 43, 7, 0, // Skip to: 3226 +/* 1391 */ MCD_OPC_Decode, 175, 7, 162, 1, // Opcode: BC2EQZC_MMR6 +/* 1396 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1411 +/* 1401 */ MCD_OPC_CheckPredicate, 24, 28, 7, 0, // Skip to: 3226 +/* 1406 */ MCD_OPC_Decode, 177, 7, 162, 1, // Opcode: BC2NEZC_MMR6 +/* 1411 */ MCD_OPC_FilterValue, 12, 18, 7, 0, // Skip to: 3226 +/* 1416 */ MCD_OPC_CheckPredicate, 24, 13, 7, 0, // Skip to: 3226 +/* 1421 */ MCD_OPC_Decode, 176, 23, 163, 1, // Opcode: SYNCI_MMR6 +/* 1426 */ MCD_OPC_FilterValue, 20, 9, 0, 0, // Skip to: 1440 +/* 1431 */ MCD_OPC_CheckPredicate, 24, 254, 6, 0, // Skip to: 3226 +/* 1436 */ MCD_OPC_Decode, 169, 19, 108, // Opcode: ORI_MMR6 +/* 1440 */ MCD_OPC_FilterValue, 21, 87, 5, 0, // Skip to: 2812 +/* 1445 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... +/* 1448 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1463 +/* 1453 */ MCD_OPC_CheckPredicate, 26, 232, 6, 0, // Skip to: 3226 +/* 1458 */ MCD_OPC_Decode, 186, 17, 164, 1, // Opcode: MIN_S_MMR6 +/* 1463 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1478 +/* 1468 */ MCD_OPC_CheckPredicate, 26, 217, 6, 0, // Skip to: 3226 +/* 1473 */ MCD_OPC_Decode, 217, 9, 165, 1, // Opcode: CMP_AF_S_MMR6 +/* 1478 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1493 +/* 1483 */ MCD_OPC_CheckPredicate, 26, 202, 6, 0, // Skip to: 3226 +/* 1488 */ MCD_OPC_Decode, 250, 16, 164, 1, // Opcode: MAX_S_MMR6 +/* 1493 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 1508 +/* 1498 */ MCD_OPC_CheckPredicate, 26, 187, 6, 0, // Skip to: 3226 +/* 1503 */ MCD_OPC_Decode, 216, 9, 166, 1, // Opcode: CMP_AF_D_MMR6 +/* 1508 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 1530 +/* 1513 */ MCD_OPC_CheckPredicate, 24, 172, 6, 0, // Skip to: 3226 +/* 1518 */ MCD_OPC_CheckField, 11, 5, 0, 165, 6, 0, // Skip to: 3226 +/* 1525 */ MCD_OPC_Decode, 154, 20, 167, 1, // Opcode: RINT_S_MMR6 +/* 1530 */ MCD_OPC_FilterValue, 35, 10, 0, 0, // Skip to: 1545 +/* 1535 */ MCD_OPC_CheckPredicate, 26, 150, 6, 0, // Skip to: 3226 +/* 1540 */ MCD_OPC_Decode, 167, 17, 164, 1, // Opcode: MINA_S_MMR6 +/* 1545 */ MCD_OPC_FilterValue, 43, 10, 0, 0, // Skip to: 1560 +/* 1550 */ MCD_OPC_CheckPredicate, 26, 135, 6, 0, // Skip to: 3226 +/* 1555 */ MCD_OPC_Decode, 231, 16, 164, 1, // Opcode: MAXA_S_MMR6 +/* 1560 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 1575 +/* 1565 */ MCD_OPC_CheckPredicate, 26, 120, 6, 0, // Skip to: 3226 +/* 1570 */ MCD_OPC_Decode, 144, 13, 168, 1, // Opcode: FADD_S_MMR6 +/* 1575 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 1590 +/* 1580 */ MCD_OPC_CheckPredicate, 24, 105, 6, 0, // Skip to: 3226 +/* 1585 */ MCD_OPC_Decode, 128, 21, 164, 1, // Opcode: SELEQZ_S_MMR6 +/* 1590 */ MCD_OPC_FilterValue, 59, 31, 0, 0, // Skip to: 1626 +/* 1595 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 1598 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1612 +/* 1603 */ MCD_OPC_CheckPredicate, 26, 82, 6, 0, // Skip to: 3226 +/* 1608 */ MCD_OPC_Decode, 135, 17, 119, // Opcode: MFC1_MMR6 +/* 1612 */ MCD_OPC_FilterValue, 5, 73, 6, 0, // Skip to: 3226 +/* 1617 */ MCD_OPC_CheckPredicate, 26, 68, 6, 0, // Skip to: 3226 +/* 1622 */ MCD_OPC_Decode, 164, 18, 125, // Opcode: MTC1_MMR6 +/* 1626 */ MCD_OPC_FilterValue, 69, 10, 0, 0, // Skip to: 1641 +/* 1631 */ MCD_OPC_CheckPredicate, 26, 54, 6, 0, // Skip to: 3226 +/* 1636 */ MCD_OPC_Decode, 157, 10, 165, 1, // Opcode: CMP_UN_S_MMR6 +/* 1641 */ MCD_OPC_FilterValue, 85, 10, 0, 0, // Skip to: 1656 +/* 1646 */ MCD_OPC_CheckPredicate, 26, 39, 6, 0, // Skip to: 3226 +/* 1651 */ MCD_OPC_Decode, 155, 10, 166, 1, // Opcode: CMP_UN_D_MMR6 +/* 1656 */ MCD_OPC_FilterValue, 96, 17, 0, 0, // Skip to: 1678 +/* 1661 */ MCD_OPC_CheckPredicate, 24, 24, 6, 0, // Skip to: 3226 +/* 1666 */ MCD_OPC_CheckField, 11, 5, 0, 17, 6, 0, // Skip to: 3226 +/* 1673 */ MCD_OPC_Decode, 155, 9, 167, 1, // Opcode: CLASS_S_MMR6 +/* 1678 */ MCD_OPC_FilterValue, 112, 10, 0, 0, // Skip to: 1693 +/* 1683 */ MCD_OPC_CheckPredicate, 26, 2, 6, 0, // Skip to: 3226 +/* 1688 */ MCD_OPC_Decode, 162, 14, 168, 1, // Opcode: FSUB_S_MMR6 +/* 1693 */ MCD_OPC_FilterValue, 120, 10, 0, 0, // Skip to: 1708 +/* 1698 */ MCD_OPC_CheckPredicate, 24, 243, 5, 0, // Skip to: 3226 +/* 1703 */ MCD_OPC_Decode, 135, 21, 164, 1, // Opcode: SELNEZ_S_MMR6 +/* 1708 */ MCD_OPC_FilterValue, 123, 31, 0, 0, // Skip to: 1744 +/* 1713 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 1716 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1730 +/* 1721 */ MCD_OPC_CheckPredicate, 26, 220, 5, 0, // Skip to: 3226 +/* 1726 */ MCD_OPC_Decode, 234, 13, 124, // Opcode: FMOV_S_MMR6 +/* 1730 */ MCD_OPC_FilterValue, 4, 211, 5, 0, // Skip to: 3226 +/* 1735 */ MCD_OPC_CheckPredicate, 26, 206, 5, 0, // Skip to: 3226 +/* 1740 */ MCD_OPC_Decode, 231, 13, 122, // Opcode: FMOV_D_MMR6 +/* 1744 */ MCD_OPC_FilterValue, 133, 1, 10, 0, 0, // Skip to: 1760 +/* 1750 */ MCD_OPC_CheckPredicate, 26, 191, 5, 0, // Skip to: 3226 +/* 1755 */ MCD_OPC_Decode, 223, 9, 165, 1, // Opcode: CMP_EQ_S_MMR6 +/* 1760 */ MCD_OPC_FilterValue, 149, 1, 10, 0, 0, // Skip to: 1776 +/* 1766 */ MCD_OPC_CheckPredicate, 26, 175, 5, 0, // Skip to: 3226 +/* 1771 */ MCD_OPC_Decode, 219, 9, 166, 1, // Opcode: CMP_EQ_D_MMR6 +/* 1776 */ MCD_OPC_FilterValue, 176, 1, 10, 0, 0, // Skip to: 1792 +/* 1782 */ MCD_OPC_CheckPredicate, 26, 159, 5, 0, // Skip to: 3226 +/* 1787 */ MCD_OPC_Decode, 245, 13, 168, 1, // Opcode: FMUL_S_MMR6 +/* 1792 */ MCD_OPC_FilterValue, 184, 1, 10, 0, 0, // Skip to: 1808 +/* 1798 */ MCD_OPC_CheckPredicate, 24, 143, 5, 0, // Skip to: 3226 +/* 1803 */ MCD_OPC_Decode, 139, 21, 169, 1, // Opcode: SEL_S_MMR6 +/* 1808 */ MCD_OPC_FilterValue, 197, 1, 10, 0, 0, // Skip to: 1824 +/* 1814 */ MCD_OPC_CheckPredicate, 26, 127, 5, 0, // Skip to: 3226 +/* 1819 */ MCD_OPC_Decode, 145, 10, 165, 1, // Opcode: CMP_UEQ_S_MMR6 +/* 1824 */ MCD_OPC_FilterValue, 213, 1, 10, 0, 0, // Skip to: 1840 +/* 1830 */ MCD_OPC_CheckPredicate, 26, 111, 5, 0, // Skip to: 3226 +/* 1835 */ MCD_OPC_Decode, 143, 10, 166, 1, // Opcode: CMP_UEQ_D_MMR6 +/* 1840 */ MCD_OPC_FilterValue, 240, 1, 10, 0, 0, // Skip to: 1856 +/* 1846 */ MCD_OPC_CheckPredicate, 26, 95, 5, 0, // Skip to: 3226 +/* 1851 */ MCD_OPC_Decode, 182, 13, 168, 1, // Opcode: FDIV_S_MMR6 +/* 1856 */ MCD_OPC_FilterValue, 133, 2, 10, 0, 0, // Skip to: 1872 +/* 1862 */ MCD_OPC_CheckPredicate, 26, 79, 5, 0, // Skip to: 3226 +/* 1867 */ MCD_OPC_Decode, 237, 9, 165, 1, // Opcode: CMP_LT_S_MMR6 +/* 1872 */ MCD_OPC_FilterValue, 149, 2, 10, 0, 0, // Skip to: 1888 +/* 1878 */ MCD_OPC_CheckPredicate, 26, 63, 5, 0, // Skip to: 3226 +/* 1883 */ MCD_OPC_Decode, 233, 9, 166, 1, // Opcode: CMP_LT_D_MMR6 +/* 1888 */ MCD_OPC_FilterValue, 187, 2, 45, 0, 0, // Skip to: 1939 +/* 1894 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 1897 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1911 +/* 1902 */ MCD_OPC_CheckPredicate, 26, 39, 5, 0, // Skip to: 3226 +/* 1907 */ MCD_OPC_Decode, 198, 10, 121, // Opcode: CVT_L_S_MMR6 +/* 1911 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1925 +/* 1916 */ MCD_OPC_CheckPredicate, 26, 25, 5, 0, // Skip to: 3226 +/* 1921 */ MCD_OPC_Decode, 219, 10, 124, // Opcode: CVT_W_S_MMR6 +/* 1925 */ MCD_OPC_FilterValue, 8, 16, 5, 0, // Skip to: 3226 +/* 1930 */ MCD_OPC_CheckPredicate, 26, 11, 5, 0, // Skip to: 3226 +/* 1935 */ MCD_OPC_Decode, 195, 10, 122, // Opcode: CVT_L_D_MMR6 +/* 1939 */ MCD_OPC_FilterValue, 197, 2, 10, 0, 0, // Skip to: 1955 +/* 1945 */ MCD_OPC_CheckPredicate, 26, 252, 4, 0, // Skip to: 3226 +/* 1950 */ MCD_OPC_Decode, 153, 10, 165, 1, // Opcode: CMP_ULT_S_MMR6 +/* 1955 */ MCD_OPC_FilterValue, 213, 2, 10, 0, 0, // Skip to: 1971 +/* 1961 */ MCD_OPC_CheckPredicate, 26, 236, 4, 0, // Skip to: 3226 +/* 1966 */ MCD_OPC_Decode, 151, 10, 166, 1, // Opcode: CMP_ULT_D_MMR6 +/* 1971 */ MCD_OPC_FilterValue, 133, 3, 10, 0, 0, // Skip to: 1987 +/* 1977 */ MCD_OPC_CheckPredicate, 26, 220, 4, 0, // Skip to: 3226 +/* 1982 */ MCD_OPC_Decode, 231, 9, 165, 1, // Opcode: CMP_LE_S_MMR6 +/* 1987 */ MCD_OPC_FilterValue, 149, 3, 10, 0, 0, // Skip to: 2003 +/* 1993 */ MCD_OPC_CheckPredicate, 26, 204, 4, 0, // Skip to: 3226 +/* 1998 */ MCD_OPC_Decode, 227, 9, 166, 1, // Opcode: CMP_LE_D_MMR6 +/* 2003 */ MCD_OPC_FilterValue, 184, 3, 10, 0, 0, // Skip to: 2019 +/* 2009 */ MCD_OPC_CheckPredicate, 26, 188, 4, 0, // Skip to: 3226 +/* 2014 */ MCD_OPC_Decode, 199, 16, 170, 1, // Opcode: MADDF_S_MMR6 +/* 2019 */ MCD_OPC_FilterValue, 197, 3, 10, 0, 0, // Skip to: 2035 +/* 2025 */ MCD_OPC_CheckPredicate, 26, 172, 4, 0, // Skip to: 3226 +/* 2030 */ MCD_OPC_Decode, 149, 10, 165, 1, // Opcode: CMP_ULE_S_MMR6 +/* 2035 */ MCD_OPC_FilterValue, 213, 3, 10, 0, 0, // Skip to: 2051 +/* 2041 */ MCD_OPC_CheckPredicate, 26, 156, 4, 0, // Skip to: 3226 +/* 2046 */ MCD_OPC_Decode, 147, 10, 166, 1, // Opcode: CMP_ULE_D_MMR6 +/* 2051 */ MCD_OPC_FilterValue, 248, 3, 10, 0, 0, // Skip to: 2067 +/* 2057 */ MCD_OPC_CheckPredicate, 26, 140, 4, 0, // Skip to: 3226 +/* 2062 */ MCD_OPC_Decode, 135, 18, 170, 1, // Opcode: MSUBF_S_MMR6 +/* 2067 */ MCD_OPC_FilterValue, 131, 4, 10, 0, 0, // Skip to: 2083 +/* 2073 */ MCD_OPC_CheckPredicate, 26, 124, 4, 0, // Skip to: 3226 +/* 2078 */ MCD_OPC_Decode, 181, 17, 145, 1, // Opcode: MIN_D_MMR6 +/* 2083 */ MCD_OPC_FilterValue, 133, 4, 10, 0, 0, // Skip to: 2099 +/* 2089 */ MCD_OPC_CheckPredicate, 26, 108, 4, 0, // Skip to: 3226 +/* 2094 */ MCD_OPC_Decode, 241, 9, 165, 1, // Opcode: CMP_SAF_S_MMR6 +/* 2099 */ MCD_OPC_FilterValue, 139, 4, 10, 0, 0, // Skip to: 2115 +/* 2105 */ MCD_OPC_CheckPredicate, 26, 92, 4, 0, // Skip to: 3226 +/* 2110 */ MCD_OPC_Decode, 245, 16, 145, 1, // Opcode: MAX_D_MMR6 +/* 2115 */ MCD_OPC_FilterValue, 149, 4, 10, 0, 0, // Skip to: 2131 +/* 2121 */ MCD_OPC_CheckPredicate, 26, 76, 4, 0, // Skip to: 3226 +/* 2126 */ MCD_OPC_Decode, 239, 9, 166, 1, // Opcode: CMP_SAF_D_MMR6 +/* 2131 */ MCD_OPC_FilterValue, 160, 4, 17, 0, 0, // Skip to: 2154 +/* 2137 */ MCD_OPC_CheckPredicate, 24, 60, 4, 0, // Skip to: 3226 +/* 2142 */ MCD_OPC_CheckField, 11, 5, 0, 53, 4, 0, // Skip to: 3226 +/* 2149 */ MCD_OPC_Decode, 152, 20, 171, 1, // Opcode: RINT_D_MMR6 +/* 2154 */ MCD_OPC_FilterValue, 163, 4, 10, 0, 0, // Skip to: 2170 +/* 2160 */ MCD_OPC_CheckPredicate, 26, 37, 4, 0, // Skip to: 3226 +/* 2165 */ MCD_OPC_Decode, 165, 17, 145, 1, // Opcode: MINA_D_MMR6 +/* 2170 */ MCD_OPC_FilterValue, 171, 4, 10, 0, 0, // Skip to: 2186 +/* 2176 */ MCD_OPC_CheckPredicate, 26, 21, 4, 0, // Skip to: 3226 +/* 2181 */ MCD_OPC_Decode, 229, 16, 145, 1, // Opcode: MAXA_D_MMR6 +/* 2186 */ MCD_OPC_FilterValue, 184, 4, 10, 0, 0, // Skip to: 2202 +/* 2192 */ MCD_OPC_CheckPredicate, 24, 5, 4, 0, // Skip to: 3226 +/* 2197 */ MCD_OPC_Decode, 253, 20, 145, 1, // Opcode: SELEQZ_D_MMR6 +/* 2202 */ MCD_OPC_FilterValue, 197, 4, 10, 0, 0, // Skip to: 2218 +/* 2208 */ MCD_OPC_CheckPredicate, 26, 245, 3, 0, // Skip to: 3226 +/* 2213 */ MCD_OPC_Decode, 141, 10, 165, 1, // Opcode: CMP_SUN_S_MMR6 +/* 2218 */ MCD_OPC_FilterValue, 213, 4, 10, 0, 0, // Skip to: 2234 +/* 2224 */ MCD_OPC_CheckPredicate, 26, 229, 3, 0, // Skip to: 3226 +/* 2229 */ MCD_OPC_Decode, 139, 10, 166, 1, // Opcode: CMP_SUN_D_MMR6 +/* 2234 */ MCD_OPC_FilterValue, 224, 4, 17, 0, 0, // Skip to: 2257 +/* 2240 */ MCD_OPC_CheckPredicate, 24, 213, 3, 0, // Skip to: 3226 +/* 2245 */ MCD_OPC_CheckField, 11, 5, 0, 206, 3, 0, // Skip to: 3226 +/* 2252 */ MCD_OPC_Decode, 153, 9, 171, 1, // Opcode: CLASS_D_MMR6 +/* 2257 */ MCD_OPC_FilterValue, 248, 4, 10, 0, 0, // Skip to: 2273 +/* 2263 */ MCD_OPC_CheckPredicate, 24, 190, 3, 0, // Skip to: 3226 +/* 2268 */ MCD_OPC_Decode, 132, 21, 145, 1, // Opcode: SELNEZ_D_MMR6 +/* 2273 */ MCD_OPC_FilterValue, 133, 5, 10, 0, 0, // Skip to: 2289 +/* 2279 */ MCD_OPC_CheckPredicate, 26, 174, 3, 0, // Skip to: 3226 +/* 2284 */ MCD_OPC_Decode, 245, 9, 165, 1, // Opcode: CMP_SEQ_S_MMR6 +/* 2289 */ MCD_OPC_FilterValue, 149, 5, 10, 0, 0, // Skip to: 2305 +/* 2295 */ MCD_OPC_CheckPredicate, 26, 158, 3, 0, // Skip to: 3226 +/* 2300 */ MCD_OPC_Decode, 243, 9, 166, 1, // Opcode: CMP_SEQ_D_MMR6 +/* 2305 */ MCD_OPC_FilterValue, 184, 5, 10, 0, 0, // Skip to: 2321 +/* 2311 */ MCD_OPC_CheckPredicate, 24, 142, 3, 0, // Skip to: 3226 +/* 2316 */ MCD_OPC_Decode, 137, 21, 172, 1, // Opcode: SEL_D_MMR6 +/* 2321 */ MCD_OPC_FilterValue, 197, 5, 10, 0, 0, // Skip to: 2337 +/* 2327 */ MCD_OPC_CheckPredicate, 26, 126, 3, 0, // Skip to: 3226 +/* 2332 */ MCD_OPC_Decode, 129, 10, 165, 1, // Opcode: CMP_SUEQ_S_MMR6 +/* 2337 */ MCD_OPC_FilterValue, 213, 5, 10, 0, 0, // Skip to: 2353 +/* 2343 */ MCD_OPC_CheckPredicate, 26, 110, 3, 0, // Skip to: 3226 +/* 2348 */ MCD_OPC_Decode, 255, 9, 166, 1, // Opcode: CMP_SUEQ_D_MMR6 +/* 2353 */ MCD_OPC_FilterValue, 133, 6, 10, 0, 0, // Skip to: 2369 +/* 2359 */ MCD_OPC_CheckPredicate, 26, 94, 3, 0, // Skip to: 3226 +/* 2364 */ MCD_OPC_Decode, 253, 9, 165, 1, // Opcode: CMP_SLT_S_MMR6 +/* 2369 */ MCD_OPC_FilterValue, 149, 6, 10, 0, 0, // Skip to: 2385 +/* 2375 */ MCD_OPC_CheckPredicate, 26, 78, 3, 0, // Skip to: 3226 +/* 2380 */ MCD_OPC_Decode, 251, 9, 166, 1, // Opcode: CMP_SLT_D_MMR6 +/* 2385 */ MCD_OPC_FilterValue, 187, 6, 228, 0, 0, // Skip to: 2619 +/* 2391 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 2394 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2408 +/* 2399 */ MCD_OPC_CheckPredicate, 26, 54, 3, 0, // Skip to: 3226 +/* 2404 */ MCD_OPC_Decode, 209, 13, 121, // Opcode: FLOOR_L_S_MMR6 +/* 2408 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2422 +/* 2413 */ MCD_OPC_CheckPredicate, 26, 40, 3, 0, // Skip to: 3226 +/* 2418 */ MCD_OPC_Decode, 216, 13, 124, // Opcode: FLOOR_W_S_MMR6 +/* 2422 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2436 +/* 2427 */ MCD_OPC_CheckPredicate, 26, 26, 3, 0, // Skip to: 3226 +/* 2432 */ MCD_OPC_Decode, 128, 9, 121, // Opcode: CEIL_L_S_MMR6 +/* 2436 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 2450 +/* 2441 */ MCD_OPC_CheckPredicate, 26, 12, 3, 0, // Skip to: 3226 +/* 2446 */ MCD_OPC_Decode, 135, 9, 124, // Opcode: CEIL_W_S_MMR6 +/* 2450 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2464 +/* 2455 */ MCD_OPC_CheckPredicate, 26, 254, 2, 0, // Skip to: 3226 +/* 2460 */ MCD_OPC_Decode, 137, 24, 121, // Opcode: TRUNC_L_S_MMR6 +/* 2464 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2478 +/* 2469 */ MCD_OPC_CheckPredicate, 26, 240, 2, 0, // Skip to: 3226 +/* 2474 */ MCD_OPC_Decode, 144, 24, 124, // Opcode: TRUNC_W_S_MMR6 +/* 2478 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 2492 +/* 2483 */ MCD_OPC_CheckPredicate, 26, 226, 2, 0, // Skip to: 3226 +/* 2488 */ MCD_OPC_Decode, 165, 20, 121, // Opcode: ROUND_L_S_MMR6 +/* 2492 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 2506 +/* 2497 */ MCD_OPC_CheckPredicate, 26, 212, 2, 0, // Skip to: 3226 +/* 2502 */ MCD_OPC_Decode, 172, 20, 124, // Opcode: ROUND_W_S_MMR6 +/* 2506 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 2520 +/* 2511 */ MCD_OPC_CheckPredicate, 26, 198, 2, 0, // Skip to: 3226 +/* 2516 */ MCD_OPC_Decode, 207, 13, 122, // Opcode: FLOOR_L_D_MMR6 +/* 2520 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 2534 +/* 2525 */ MCD_OPC_CheckPredicate, 26, 184, 2, 0, // Skip to: 3226 +/* 2530 */ MCD_OPC_Decode, 212, 13, 126, // Opcode: FLOOR_W_D_MMR6 +/* 2534 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 2548 +/* 2539 */ MCD_OPC_CheckPredicate, 26, 170, 2, 0, // Skip to: 3226 +/* 2544 */ MCD_OPC_Decode, 254, 8, 122, // Opcode: CEIL_L_D_MMR6 +/* 2548 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 2562 +/* 2553 */ MCD_OPC_CheckPredicate, 26, 156, 2, 0, // Skip to: 3226 +/* 2558 */ MCD_OPC_Decode, 131, 9, 126, // Opcode: CEIL_W_D_MMR6 +/* 2562 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 2576 +/* 2567 */ MCD_OPC_CheckPredicate, 26, 142, 2, 0, // Skip to: 3226 +/* 2572 */ MCD_OPC_Decode, 135, 24, 122, // Opcode: TRUNC_L_D_MMR6 +/* 2576 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2591 +/* 2581 */ MCD_OPC_CheckPredicate, 26, 128, 2, 0, // Skip to: 3226 +/* 2586 */ MCD_OPC_Decode, 140, 24, 146, 1, // Opcode: TRUNC_W_D_MMR6 +/* 2591 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 2605 +/* 2596 */ MCD_OPC_CheckPredicate, 26, 113, 2, 0, // Skip to: 3226 +/* 2601 */ MCD_OPC_Decode, 163, 20, 122, // Opcode: ROUND_L_D_MMR6 +/* 2605 */ MCD_OPC_FilterValue, 15, 104, 2, 0, // Skip to: 3226 +/* 2610 */ MCD_OPC_CheckPredicate, 26, 99, 2, 0, // Skip to: 3226 +/* 2615 */ MCD_OPC_Decode, 168, 20, 122, // Opcode: ROUND_W_D_MMR6 +/* 2619 */ MCD_OPC_FilterValue, 197, 6, 10, 0, 0, // Skip to: 2635 +/* 2625 */ MCD_OPC_CheckPredicate, 26, 84, 2, 0, // Skip to: 3226 +/* 2630 */ MCD_OPC_Decode, 137, 10, 165, 1, // Opcode: CMP_SULT_S_MMR6 +/* 2635 */ MCD_OPC_FilterValue, 213, 6, 10, 0, 0, // Skip to: 2651 +/* 2641 */ MCD_OPC_CheckPredicate, 26, 68, 2, 0, // Skip to: 3226 +/* 2646 */ MCD_OPC_Decode, 135, 10, 166, 1, // Opcode: CMP_SULT_D_MMR6 +/* 2651 */ MCD_OPC_FilterValue, 251, 6, 59, 0, 0, // Skip to: 2716 +/* 2657 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 2660 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2674 +/* 2665 */ MCD_OPC_CheckPredicate, 26, 44, 2, 0, // Skip to: 3226 +/* 2670 */ MCD_OPC_Decode, 253, 13, 124, // Opcode: FNEG_S_MMR6 +/* 2674 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 2688 +/* 2679 */ MCD_OPC_CheckPredicate, 26, 30, 2, 0, // Skip to: 3226 +/* 2684 */ MCD_OPC_Decode, 212, 10, 124, // Opcode: CVT_S_W_MMR6 +/* 2688 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 2702 +/* 2693 */ MCD_OPC_CheckPredicate, 23, 16, 2, 0, // Skip to: 3226 +/* 2698 */ MCD_OPC_Decode, 192, 10, 122, // Opcode: CVT_D_L_MMR6 +/* 2702 */ MCD_OPC_FilterValue, 11, 7, 2, 0, // Skip to: 3226 +/* 2707 */ MCD_OPC_CheckPredicate, 23, 2, 2, 0, // Skip to: 3226 +/* 2712 */ MCD_OPC_Decode, 207, 10, 121, // Opcode: CVT_S_L_MMR6 +/* 2716 */ MCD_OPC_FilterValue, 133, 7, 10, 0, 0, // Skip to: 2732 +/* 2722 */ MCD_OPC_CheckPredicate, 26, 243, 1, 0, // Skip to: 3226 +/* 2727 */ MCD_OPC_Decode, 249, 9, 165, 1, // Opcode: CMP_SLE_S_MMR6 +/* 2732 */ MCD_OPC_FilterValue, 149, 7, 10, 0, 0, // Skip to: 2748 +/* 2738 */ MCD_OPC_CheckPredicate, 26, 227, 1, 0, // Skip to: 3226 +/* 2743 */ MCD_OPC_Decode, 247, 9, 166, 1, // Opcode: CMP_SLE_D_MMR6 +/* 2748 */ MCD_OPC_FilterValue, 184, 7, 10, 0, 0, // Skip to: 2764 +/* 2754 */ MCD_OPC_CheckPredicate, 26, 211, 1, 0, // Skip to: 3226 +/* 2759 */ MCD_OPC_Decode, 197, 16, 172, 1, // Opcode: MADDF_D_MMR6 +/* 2764 */ MCD_OPC_FilterValue, 197, 7, 10, 0, 0, // Skip to: 2780 +/* 2770 */ MCD_OPC_CheckPredicate, 26, 195, 1, 0, // Skip to: 3226 +/* 2775 */ MCD_OPC_Decode, 133, 10, 165, 1, // Opcode: CMP_SULE_S_MMR6 +/* 2780 */ MCD_OPC_FilterValue, 213, 7, 10, 0, 0, // Skip to: 2796 +/* 2786 */ MCD_OPC_CheckPredicate, 26, 179, 1, 0, // Skip to: 3226 +/* 2791 */ MCD_OPC_Decode, 131, 10, 166, 1, // Opcode: CMP_SULE_D_MMR6 +/* 2796 */ MCD_OPC_FilterValue, 248, 7, 168, 1, 0, // Skip to: 3226 +/* 2802 */ MCD_OPC_CheckPredicate, 26, 163, 1, 0, // Skip to: 3226 +/* 2807 */ MCD_OPC_Decode, 133, 18, 172, 1, // Opcode: MSUBF_D_MMR6 +/* 2812 */ MCD_OPC_FilterValue, 24, 61, 0, 0, // Skip to: 2878 +/* 2817 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 2820 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2834 +/* 2825 */ MCD_OPC_CheckPredicate, 24, 140, 1, 0, // Skip to: 3226 +/* 2830 */ MCD_OPC_Decode, 243, 19, 100, // Opcode: PREF_MMR6 +/* 2834 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 2856 +/* 2839 */ MCD_OPC_CheckPredicate, 24, 126, 1, 0, // Skip to: 3226 +/* 2844 */ MCD_OPC_CheckField, 9, 3, 0, 119, 1, 0, // Skip to: 3226 +/* 2851 */ MCD_OPC_Decode, 244, 15, 134, 1, // Opcode: LL_MMR6 +/* 2856 */ MCD_OPC_FilterValue, 11, 109, 1, 0, // Skip to: 3226 +/* 2861 */ MCD_OPC_CheckPredicate, 24, 104, 1, 0, // Skip to: 3226 +/* 2866 */ MCD_OPC_CheckField, 9, 3, 0, 97, 1, 0, // Skip to: 3226 +/* 2873 */ MCD_OPC_Decode, 215, 20, 134, 1, // Opcode: SC_MMR6 +/* 2878 */ MCD_OPC_FilterValue, 28, 9, 0, 0, // Skip to: 2892 +/* 2883 */ MCD_OPC_CheckPredicate, 24, 82, 1, 0, // Skip to: 3226 +/* 2888 */ MCD_OPC_Decode, 178, 24, 108, // Opcode: XORI_MMR6 +/* 2892 */ MCD_OPC_FilterValue, 29, 27, 0, 0, // Skip to: 2924 +/* 2897 */ MCD_OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 2914 +/* 2902 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 2914 +/* 2909 */ MCD_OPC_Decode, 200, 7, 173, 1, // Opcode: BEQZALC_MMR6 +/* 2914 */ MCD_OPC_CheckPredicate, 24, 51, 1, 0, // Skip to: 3226 +/* 2919 */ MCD_OPC_Decode, 193, 7, 173, 1, // Opcode: BEQC_MMR6 +/* 2924 */ MCD_OPC_FilterValue, 30, 71, 0, 0, // Skip to: 3000 +/* 2929 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... +/* 2932 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2947 +/* 2937 */ MCD_OPC_CheckPredicate, 24, 28, 1, 0, // Skip to: 3226 +/* 2942 */ MCD_OPC_Decode, 131, 6, 174, 1, // Opcode: ADDIUPC_MMR6 +/* 2947 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2962 +/* 2952 */ MCD_OPC_CheckPredicate, 24, 13, 1, 0, // Skip to: 3226 +/* 2957 */ MCD_OPC_Decode, 159, 16, 174, 1, // Opcode: LWPC_MMR6 +/* 2962 */ MCD_OPC_FilterValue, 3, 3, 1, 0, // Skip to: 3226 +/* 2967 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... +/* 2970 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 2985 +/* 2975 */ MCD_OPC_CheckPredicate, 24, 246, 0, 0, // Skip to: 3226 +/* 2980 */ MCD_OPC_Decode, 246, 6, 175, 1, // Opcode: AUIPC_MMR6 +/* 2985 */ MCD_OPC_FilterValue, 7, 236, 0, 0, // Skip to: 3226 +/* 2990 */ MCD_OPC_CheckPredicate, 24, 231, 0, 0, // Skip to: 3226 +/* 2995 */ MCD_OPC_Decode, 214, 6, 175, 1, // Opcode: ALUIPC_MMR6 +/* 3000 */ MCD_OPC_FilterValue, 31, 27, 0, 0, // Skip to: 3032 +/* 3005 */ MCD_OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 3022 +/* 3010 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 3022 +/* 3017 */ MCD_OPC_Decode, 190, 8, 176, 1, // Opcode: BNEZALC_MMR6 +/* 3022 */ MCD_OPC_CheckPredicate, 24, 199, 0, 0, // Skip to: 3226 +/* 3027 */ MCD_OPC_Decode, 175, 8, 176, 1, // Opcode: BNEC_MMR6 +/* 3032 */ MCD_OPC_FilterValue, 32, 26, 0, 0, // Skip to: 3063 +/* 3037 */ MCD_OPC_CheckPredicate, 24, 11, 0, 0, // Skip to: 3053 +/* 3042 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 3053 +/* 3049 */ MCD_OPC_Decode, 128, 15, 103, // Opcode: JIALC_MMR6 +/* 3053 */ MCD_OPC_CheckPredicate, 24, 168, 0, 0, // Skip to: 3226 +/* 3058 */ MCD_OPC_Decode, 206, 7, 177, 1, // Opcode: BEQZC_MMR6 +/* 3063 */ MCD_OPC_FilterValue, 37, 10, 0, 0, // Skip to: 3078 +/* 3068 */ MCD_OPC_CheckPredicate, 24, 153, 0, 0, // Skip to: 3226 +/* 3073 */ MCD_OPC_Decode, 186, 7, 178, 1, // Opcode: BC_MMR6 +/* 3078 */ MCD_OPC_FilterValue, 40, 26, 0, 0, // Skip to: 3109 +/* 3083 */ MCD_OPC_CheckPredicate, 24, 11, 0, 0, // Skip to: 3099 +/* 3088 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 3099 +/* 3095 */ MCD_OPC_Decode, 131, 15, 103, // Opcode: JIC_MMR6 +/* 3099 */ MCD_OPC_CheckPredicate, 24, 122, 0, 0, // Skip to: 3226 +/* 3104 */ MCD_OPC_Decode, 196, 8, 177, 1, // Opcode: BNEZC_MMR6 +/* 3109 */ MCD_OPC_FilterValue, 45, 10, 0, 0, // Skip to: 3124 +/* 3114 */ MCD_OPC_CheckPredicate, 24, 107, 0, 0, // Skip to: 3226 +/* 3119 */ MCD_OPC_Decode, 150, 7, 178, 1, // Opcode: BALC_MMR6 +/* 3124 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 3139 +/* 3129 */ MCD_OPC_CheckPredicate, 24, 92, 0, 0, // Skip to: 3226 +/* 3134 */ MCD_OPC_Decode, 217, 7, 179, 1, // Opcode: BGEUC_MMR6 +/* 3139 */ MCD_OPC_FilterValue, 52, 9, 0, 0, // Skip to: 3153 +/* 3144 */ MCD_OPC_CheckPredicate, 24, 77, 0, 0, // Skip to: 3226 +/* 3149 */ MCD_OPC_Decode, 225, 6, 108, // Opcode: ANDI_MMR6 +/* 3153 */ MCD_OPC_FilterValue, 53, 10, 0, 0, // Skip to: 3168 +/* 3158 */ MCD_OPC_CheckPredicate, 24, 63, 0, 0, // Skip to: 3226 +/* 3163 */ MCD_OPC_Decode, 145, 8, 180, 1, // Opcode: BLTC_MMR6 +/* 3168 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 3183 +/* 3173 */ MCD_OPC_CheckPredicate, 24, 48, 0, 0, // Skip to: 3226 +/* 3178 */ MCD_OPC_Decode, 151, 8, 181, 1, // Opcode: BLTUC_MMR6 +/* 3183 */ MCD_OPC_FilterValue, 61, 10, 0, 0, // Skip to: 3198 +/* 3188 */ MCD_OPC_CheckPredicate, 24, 33, 0, 0, // Skip to: 3226 +/* 3193 */ MCD_OPC_Decode, 211, 7, 182, 1, // Opcode: BGEC_MMR6 +/* 3198 */ MCD_OPC_FilterValue, 62, 9, 0, 0, // Skip to: 3212 +/* 3203 */ MCD_OPC_CheckPredicate, 24, 18, 0, 0, // Skip to: 3226 +/* 3208 */ MCD_OPC_Decode, 170, 23, 98, // Opcode: SW_MMR6 +/* 3212 */ MCD_OPC_FilterValue, 63, 9, 0, 0, // Skip to: 3226 +/* 3217 */ MCD_OPC_CheckPredicate, 24, 4, 0, 0, // Skip to: 3226 +/* 3222 */ MCD_OPC_Decode, 180, 16, 98, // Opcode: LW_MMR6 +/* 3226 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMicroMipsR6_Ambiguous32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 18 +/* 8 */ MCD_OPC_CheckPredicate, 24, 84, 0, 0, // Skip to: 97 +/* 13 */ MCD_OPC_Decode, 207, 8, 173, 1, // Opcode: BOVC_MMR6 +/* 18 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 33 +/* 23 */ MCD_OPC_CheckPredicate, 24, 69, 0, 0, // Skip to: 97 +/* 28 */ MCD_OPC_Decode, 200, 8, 176, 1, // Opcode: BNVC_MMR6 +/* 33 */ MCD_OPC_FilterValue, 48, 27, 0, 0, // Skip to: 65 +/* 38 */ MCD_OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 55 +/* 43 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 55 +/* 50 */ MCD_OPC_Decode, 137, 8, 179, 1, // Opcode: BLEZALC_MMR6 +/* 55 */ MCD_OPC_CheckPredicate, 24, 37, 0, 0, // Skip to: 97 +/* 60 */ MCD_OPC_Decode, 223, 7, 179, 1, // Opcode: BGEZALC_MMR6 +/* 65 */ MCD_OPC_FilterValue, 56, 27, 0, 0, // Skip to: 97 +/* 70 */ MCD_OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 87 +/* 75 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 87 +/* 82 */ MCD_OPC_Decode, 235, 7, 181, 1, // Opcode: BGTZALC_MMR6 +/* 87 */ MCD_OPC_CheckPredicate, 24, 5, 0, 0, // Skip to: 97 +/* 92 */ MCD_OPC_Decode, 157, 8, 181, 1, // Opcode: BLTZALC_MMR6 +/* 97 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableMips32[] = { /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 0, 173, 3, // Skip to: 948 -/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 10 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 68 -/* 14 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 17 */ MCD_OPC_FilterValue, 0, 137, 53, // Skip to: 13726 -/* 21 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... -/* 24 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 36 -/* 28 */ MCD_OPC_CheckPredicate, 5, 28, 0, // Skip to: 60 -/* 32 */ MCD_OPC_Decode, 180, 12, 0, // Opcode: SSNOP -/* 36 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 48 -/* 40 */ MCD_OPC_CheckPredicate, 5, 16, 0, // Skip to: 60 -/* 44 */ MCD_OPC_Decode, 139, 5, 0, // Opcode: EHB -/* 48 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 60 -/* 52 */ MCD_OPC_CheckPredicate, 6, 4, 0, // Skip to: 60 -/* 56 */ MCD_OPC_Decode, 147, 10, 0, // Opcode: PAUSE -/* 60 */ MCD_OPC_CheckPredicate, 1, 94, 53, // Skip to: 13726 -/* 64 */ MCD_OPC_Decode, 225, 11, 58, // Opcode: SLL -/* 68 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 111 -/* 72 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 75 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 93 -/* 79 */ MCD_OPC_CheckPredicate, 7, 75, 53, // Skip to: 13726 -/* 83 */ MCD_OPC_CheckField, 6, 5, 0, 69, 53, // Skip to: 13726 -/* 89 */ MCD_OPC_Decode, 239, 8, 59, // Opcode: MOVF_I -/* 93 */ MCD_OPC_FilterValue, 1, 61, 53, // Skip to: 13726 -/* 97 */ MCD_OPC_CheckPredicate, 7, 57, 53, // Skip to: 13726 -/* 101 */ MCD_OPC_CheckField, 6, 5, 0, 51, 53, // Skip to: 13726 -/* 107 */ MCD_OPC_Decode, 131, 9, 59, // Opcode: MOVT_I -/* 111 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 142 -/* 115 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 118 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 130 -/* 122 */ MCD_OPC_CheckPredicate, 1, 32, 53, // Skip to: 13726 -/* 126 */ MCD_OPC_Decode, 159, 12, 58, // Opcode: SRL -/* 130 */ MCD_OPC_FilterValue, 1, 24, 53, // Skip to: 13726 -/* 134 */ MCD_OPC_CheckPredicate, 6, 20, 53, // Skip to: 13726 -/* 138 */ MCD_OPC_Decode, 247, 10, 58, // Opcode: ROTR -/* 142 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 160 -/* 146 */ MCD_OPC_CheckPredicate, 5, 8, 53, // Skip to: 13726 -/* 150 */ MCD_OPC_CheckField, 21, 5, 0, 2, 53, // Skip to: 13726 -/* 156 */ MCD_OPC_Decode, 139, 12, 58, // Opcode: SRA -/* 160 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 178 -/* 164 */ MCD_OPC_CheckPredicate, 5, 246, 52, // Skip to: 13726 -/* 168 */ MCD_OPC_CheckField, 6, 5, 0, 240, 52, // Skip to: 13726 -/* 174 */ MCD_OPC_Decode, 233, 11, 36, // Opcode: SLLV -/* 178 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 196 -/* 182 */ MCD_OPC_CheckPredicate, 8, 228, 52, // Skip to: 13726 -/* 186 */ MCD_OPC_CheckField, 8, 3, 0, 222, 52, // Skip to: 13726 -/* 192 */ MCD_OPC_Decode, 205, 7, 60, // Opcode: LSA -/* 196 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 227 -/* 200 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 203 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 215 -/* 207 */ MCD_OPC_CheckPredicate, 5, 203, 52, // Skip to: 13726 -/* 211 */ MCD_OPC_Decode, 173, 12, 36, // Opcode: SRLV -/* 215 */ MCD_OPC_FilterValue, 1, 195, 52, // Skip to: 13726 -/* 219 */ MCD_OPC_CheckPredicate, 6, 191, 52, // Skip to: 13726 -/* 223 */ MCD_OPC_Decode, 248, 10, 36, // Opcode: ROTRV -/* 227 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 245 -/* 231 */ MCD_OPC_CheckPredicate, 5, 179, 52, // Skip to: 13726 -/* 235 */ MCD_OPC_CheckField, 6, 5, 0, 173, 52, // Skip to: 13726 -/* 241 */ MCD_OPC_Decode, 152, 12, 36, // Opcode: SRAV -/* 245 */ MCD_OPC_FilterValue, 8, 27, 0, // Skip to: 276 -/* 249 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... -/* 252 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 264 -/* 256 */ MCD_OPC_CheckPredicate, 5, 154, 52, // Skip to: 13726 -/* 260 */ MCD_OPC_Decode, 136, 7, 61, // Opcode: JR -/* 264 */ MCD_OPC_FilterValue, 16, 146, 52, // Skip to: 13726 -/* 268 */ MCD_OPC_CheckPredicate, 9, 142, 52, // Skip to: 13726 -/* 272 */ MCD_OPC_Decode, 141, 7, 61, // Opcode: JR_HB -/* 276 */ MCD_OPC_FilterValue, 9, 39, 0, // Skip to: 319 -/* 280 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 283 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 301 -/* 287 */ MCD_OPC_CheckPredicate, 1, 123, 52, // Skip to: 13726 -/* 291 */ MCD_OPC_CheckField, 16, 5, 0, 117, 52, // Skip to: 13726 -/* 297 */ MCD_OPC_Decode, 249, 6, 62, // Opcode: JALR -/* 301 */ MCD_OPC_FilterValue, 16, 109, 52, // Skip to: 13726 -/* 305 */ MCD_OPC_CheckPredicate, 10, 105, 52, // Skip to: 13726 -/* 309 */ MCD_OPC_CheckField, 16, 5, 0, 99, 52, // Skip to: 13726 -/* 315 */ MCD_OPC_Decode, 128, 7, 62, // Opcode: JALR_HB -/* 319 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 337 -/* 323 */ MCD_OPC_CheckPredicate, 7, 87, 52, // Skip to: 13726 -/* 327 */ MCD_OPC_CheckField, 6, 5, 0, 81, 52, // Skip to: 13726 -/* 333 */ MCD_OPC_Decode, 143, 9, 63, // Opcode: MOVZ_I_I -/* 337 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 355 -/* 341 */ MCD_OPC_CheckPredicate, 7, 69, 52, // Skip to: 13726 -/* 345 */ MCD_OPC_CheckField, 6, 5, 0, 63, 52, // Skip to: 13726 -/* 351 */ MCD_OPC_Decode, 251, 8, 63, // Opcode: MOVN_I_I -/* 355 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 367 -/* 359 */ MCD_OPC_CheckPredicate, 5, 51, 52, // Skip to: 13726 -/* 363 */ MCD_OPC_Decode, 132, 13, 64, // Opcode: SYSCALL -/* 367 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 379 -/* 371 */ MCD_OPC_CheckPredicate, 5, 39, 52, // Skip to: 13726 -/* 375 */ MCD_OPC_Decode, 171, 2, 33, // Opcode: BREAK -/* 379 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 391 -/* 383 */ MCD_OPC_CheckPredicate, 10, 27, 52, // Skip to: 13726 -/* 387 */ MCD_OPC_Decode, 129, 13, 65, // Opcode: SYNC -/* 391 */ MCD_OPC_FilterValue, 16, 43, 0, // Skip to: 438 -/* 395 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 398 */ MCD_OPC_FilterValue, 0, 12, 52, // Skip to: 13726 -/* 402 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 405 */ MCD_OPC_FilterValue, 0, 5, 52, // Skip to: 13726 -/* 409 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... -/* 412 */ MCD_OPC_FilterValue, 0, 254, 51, // Skip to: 13726 -/* 416 */ MCD_OPC_CheckPredicate, 11, 10, 0, // Skip to: 430 -/* 420 */ MCD_OPC_CheckField, 21, 2, 0, 4, 0, // Skip to: 430 -/* 426 */ MCD_OPC_Decode, 186, 8, 66, // Opcode: MFHI -/* 430 */ MCD_OPC_CheckPredicate, 12, 236, 51, // Skip to: 13726 -/* 434 */ MCD_OPC_Decode, 189, 8, 67, // Opcode: MFHI_DSP -/* 438 */ MCD_OPC_FilterValue, 17, 36, 0, // Skip to: 478 -/* 442 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 445 */ MCD_OPC_FilterValue, 0, 221, 51, // Skip to: 13726 -/* 449 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ... -/* 452 */ MCD_OPC_FilterValue, 0, 214, 51, // Skip to: 13726 -/* 456 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 470 -/* 460 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 470 -/* 466 */ MCD_OPC_Decode, 176, 9, 61, // Opcode: MTHI -/* 470 */ MCD_OPC_CheckPredicate, 12, 196, 51, // Skip to: 13726 -/* 474 */ MCD_OPC_Decode, 178, 9, 68, // Opcode: MTHI_DSP -/* 478 */ MCD_OPC_FilterValue, 18, 43, 0, // Skip to: 525 -/* 482 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 485 */ MCD_OPC_FilterValue, 0, 181, 51, // Skip to: 13726 -/* 489 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 492 */ MCD_OPC_FilterValue, 0, 174, 51, // Skip to: 13726 -/* 496 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... -/* 499 */ MCD_OPC_FilterValue, 0, 167, 51, // Skip to: 13726 -/* 503 */ MCD_OPC_CheckPredicate, 11, 10, 0, // Skip to: 517 -/* 507 */ MCD_OPC_CheckField, 21, 2, 0, 4, 0, // Skip to: 517 -/* 513 */ MCD_OPC_Decode, 191, 8, 66, // Opcode: MFLO -/* 517 */ MCD_OPC_CheckPredicate, 12, 149, 51, // Skip to: 13726 -/* 521 */ MCD_OPC_Decode, 194, 8, 67, // Opcode: MFLO_DSP -/* 525 */ MCD_OPC_FilterValue, 19, 36, 0, // Skip to: 565 -/* 529 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 532 */ MCD_OPC_FilterValue, 0, 134, 51, // Skip to: 13726 +/* 3 */ MCD_OPC_FilterValue, 0, 101, 4, 0, // Skip to: 1133 +/* 8 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 11 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 79 +/* 16 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 19 */ MCD_OPC_FilterValue, 0, 178, 66, 0, // Skip to: 17098 +/* 24 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... +/* 27 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 41 +/* 32 */ MCD_OPC_CheckPredicate, 27, 32, 0, 0, // Skip to: 69 +/* 37 */ MCD_OPC_Decode, 185, 22, 10, // Opcode: SSNOP +/* 41 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 55 +/* 46 */ MCD_OPC_CheckPredicate, 27, 18, 0, 0, // Skip to: 69 +/* 51 */ MCD_OPC_Decode, 206, 12, 10, // Opcode: EHB +/* 55 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 69 +/* 60 */ MCD_OPC_CheckPredicate, 28, 4, 0, 0, // Skip to: 69 +/* 65 */ MCD_OPC_Decode, 181, 19, 10, // Opcode: PAUSE +/* 69 */ MCD_OPC_CheckPredicate, 27, 128, 66, 0, // Skip to: 17098 +/* 74 */ MCD_OPC_Decode, 219, 21, 183, 1, // Opcode: SLL +/* 79 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 131 +/* 84 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 87 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 109 +/* 92 */ MCD_OPC_CheckPredicate, 29, 105, 66, 0, // Skip to: 17098 +/* 97 */ MCD_OPC_CheckField, 6, 5, 0, 98, 66, 0, // Skip to: 17098 +/* 104 */ MCD_OPC_Decode, 220, 17, 184, 1, // Opcode: MOVF_I +/* 109 */ MCD_OPC_FilterValue, 1, 88, 66, 0, // Skip to: 17098 +/* 114 */ MCD_OPC_CheckPredicate, 29, 83, 66, 0, // Skip to: 17098 +/* 119 */ MCD_OPC_CheckField, 6, 5, 0, 76, 66, 0, // Skip to: 17098 +/* 126 */ MCD_OPC_Decode, 241, 17, 184, 1, // Opcode: MOVT_I +/* 131 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 169 +/* 136 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 139 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 154 +/* 144 */ MCD_OPC_CheckPredicate, 27, 53, 66, 0, // Skip to: 17098 +/* 149 */ MCD_OPC_Decode, 160, 22, 183, 1, // Opcode: SRL +/* 154 */ MCD_OPC_FilterValue, 1, 43, 66, 0, // Skip to: 17098 +/* 159 */ MCD_OPC_CheckPredicate, 28, 38, 66, 0, // Skip to: 17098 +/* 164 */ MCD_OPC_Decode, 155, 20, 183, 1, // Opcode: ROTR +/* 169 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 191 +/* 174 */ MCD_OPC_CheckPredicate, 27, 23, 66, 0, // Skip to: 17098 +/* 179 */ MCD_OPC_CheckField, 21, 5, 0, 16, 66, 0, // Skip to: 17098 +/* 186 */ MCD_OPC_Decode, 138, 22, 183, 1, // Opcode: SRA +/* 191 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 212 +/* 196 */ MCD_OPC_CheckPredicate, 27, 1, 66, 0, // Skip to: 17098 +/* 201 */ MCD_OPC_CheckField, 6, 5, 0, 250, 65, 0, // Skip to: 17098 +/* 208 */ MCD_OPC_Decode, 229, 21, 55, // Opcode: SLLV +/* 212 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 234 +/* 217 */ MCD_OPC_CheckPredicate, 30, 236, 65, 0, // Skip to: 17098 +/* 222 */ MCD_OPC_CheckField, 8, 3, 0, 229, 65, 0, // Skip to: 17098 +/* 229 */ MCD_OPC_Decode, 247, 15, 185, 1, // Opcode: LSA +/* 234 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 270 +/* 239 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 242 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 256 +/* 247 */ MCD_OPC_CheckPredicate, 27, 206, 65, 0, // Skip to: 17098 +/* 252 */ MCD_OPC_Decode, 176, 22, 55, // Opcode: SRLV +/* 256 */ MCD_OPC_FilterValue, 1, 197, 65, 0, // Skip to: 17098 +/* 261 */ MCD_OPC_CheckPredicate, 28, 192, 65, 0, // Skip to: 17098 +/* 266 */ MCD_OPC_Decode, 156, 20, 55, // Opcode: ROTRV +/* 270 */ MCD_OPC_FilterValue, 7, 16, 0, 0, // Skip to: 291 +/* 275 */ MCD_OPC_CheckPredicate, 27, 178, 65, 0, // Skip to: 17098 +/* 280 */ MCD_OPC_CheckField, 6, 5, 0, 171, 65, 0, // Skip to: 17098 +/* 287 */ MCD_OPC_Decode, 151, 22, 55, // Opcode: SRAV +/* 291 */ MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 329 +/* 296 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... +/* 299 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 314 +/* 304 */ MCD_OPC_CheckPredicate, 31, 149, 65, 0, // Skip to: 17098 +/* 309 */ MCD_OPC_Decode, 132, 15, 186, 1, // Opcode: JR +/* 314 */ MCD_OPC_FilterValue, 16, 139, 65, 0, // Skip to: 17098 +/* 319 */ MCD_OPC_CheckPredicate, 32, 134, 65, 0, // Skip to: 17098 +/* 324 */ MCD_OPC_Decode, 140, 15, 186, 1, // Opcode: JR_HB +/* 329 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 379 +/* 334 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 337 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 358 +/* 342 */ MCD_OPC_CheckPredicate, 33, 111, 65, 0, // Skip to: 17098 +/* 347 */ MCD_OPC_CheckField, 16, 5, 0, 104, 65, 0, // Skip to: 17098 +/* 354 */ MCD_OPC_Decode, 236, 14, 25, // Opcode: JALR +/* 358 */ MCD_OPC_FilterValue, 16, 95, 65, 0, // Skip to: 17098 +/* 363 */ MCD_OPC_CheckPredicate, 34, 90, 65, 0, // Skip to: 17098 +/* 368 */ MCD_OPC_CheckField, 16, 5, 0, 83, 65, 0, // Skip to: 17098 +/* 375 */ MCD_OPC_Decode, 247, 14, 25, // Opcode: JALR_HB +/* 379 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 401 +/* 384 */ MCD_OPC_CheckPredicate, 35, 69, 65, 0, // Skip to: 17098 +/* 389 */ MCD_OPC_CheckField, 6, 5, 0, 62, 65, 0, // Skip to: 17098 +/* 396 */ MCD_OPC_Decode, 253, 17, 187, 1, // Opcode: MOVZ_I_I +/* 401 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 423 +/* 406 */ MCD_OPC_CheckPredicate, 35, 47, 65, 0, // Skip to: 17098 +/* 411 */ MCD_OPC_CheckField, 6, 5, 0, 40, 65, 0, // Skip to: 17098 +/* 418 */ MCD_OPC_Decode, 232, 17, 187, 1, // Opcode: MOVN_I_I +/* 423 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 438 +/* 428 */ MCD_OPC_CheckPredicate, 27, 25, 65, 0, // Skip to: 17098 +/* 433 */ MCD_OPC_Decode, 182, 23, 188, 1, // Opcode: SYSCALL +/* 438 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 452 +/* 443 */ MCD_OPC_CheckPredicate, 27, 10, 65, 0, // Skip to: 17098 +/* 448 */ MCD_OPC_Decode, 211, 8, 56, // Opcode: BREAK +/* 452 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 467 +/* 457 */ MCD_OPC_CheckPredicate, 36, 252, 64, 0, // Skip to: 17098 +/* 462 */ MCD_OPC_Decode, 173, 23, 189, 1, // Opcode: SYNC +/* 467 */ MCD_OPC_FilterValue, 16, 51, 0, 0, // Skip to: 523 +/* 472 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 475 */ MCD_OPC_FilterValue, 0, 234, 64, 0, // Skip to: 17098 +/* 480 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 483 */ MCD_OPC_FilterValue, 0, 226, 64, 0, // Skip to: 17098 +/* 488 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... +/* 491 */ MCD_OPC_FilterValue, 0, 218, 64, 0, // Skip to: 17098 +/* 496 */ MCD_OPC_CheckPredicate, 31, 12, 0, 0, // Skip to: 513 +/* 501 */ MCD_OPC_CheckField, 21, 2, 0, 5, 0, 0, // Skip to: 513 +/* 508 */ MCD_OPC_Decode, 150, 17, 190, 1, // Opcode: MFHI +/* 513 */ MCD_OPC_CheckPredicate, 37, 196, 64, 0, // Skip to: 17098 +/* 518 */ MCD_OPC_Decode, 153, 17, 191, 1, // Opcode: MFHI_DSP +/* 523 */ MCD_OPC_FilterValue, 17, 43, 0, 0, // Skip to: 571 +/* 528 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 531 */ MCD_OPC_FilterValue, 0, 178, 64, 0, // Skip to: 17098 /* 536 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ... -/* 539 */ MCD_OPC_FilterValue, 0, 127, 51, // Skip to: 13726 -/* 543 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 557 -/* 547 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 557 -/* 553 */ MCD_OPC_Decode, 181, 9, 61, // Opcode: MTLO -/* 557 */ MCD_OPC_CheckPredicate, 12, 109, 51, // Skip to: 13726 -/* 561 */ MCD_OPC_Decode, 183, 9, 69, // Opcode: MTLO_DSP -/* 565 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 583 -/* 569 */ MCD_OPC_CheckPredicate, 14, 97, 51, // Skip to: 13726 -/* 573 */ MCD_OPC_CheckField, 8, 3, 0, 91, 51, // Skip to: 13726 -/* 579 */ MCD_OPC_Decode, 194, 4, 70, // Opcode: DLSA -/* 583 */ MCD_OPC_FilterValue, 24, 36, 0, // Skip to: 623 -/* 587 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 590 */ MCD_OPC_FilterValue, 0, 76, 51, // Skip to: 13726 -/* 594 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 597 */ MCD_OPC_FilterValue, 0, 69, 51, // Skip to: 13726 -/* 601 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 615 -/* 605 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 615 -/* 611 */ MCD_OPC_Decode, 206, 9, 43, // Opcode: MULT -/* 615 */ MCD_OPC_CheckPredicate, 12, 51, 51, // Skip to: 13726 -/* 619 */ MCD_OPC_Decode, 208, 9, 71, // Opcode: MULT_DSP -/* 623 */ MCD_OPC_FilterValue, 25, 36, 0, // Skip to: 663 -/* 627 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 630 */ MCD_OPC_FilterValue, 0, 36, 51, // Skip to: 13726 -/* 634 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 637 */ MCD_OPC_FilterValue, 0, 29, 51, // Skip to: 13726 -/* 641 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 655 -/* 645 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 655 -/* 651 */ MCD_OPC_Decode, 210, 9, 43, // Opcode: MULTu -/* 655 */ MCD_OPC_CheckPredicate, 12, 11, 51, // Skip to: 13726 -/* 659 */ MCD_OPC_Decode, 207, 9, 71, // Opcode: MULTU_DSP -/* 663 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 681 -/* 667 */ MCD_OPC_CheckPredicate, 13, 255, 50, // Skip to: 13726 -/* 671 */ MCD_OPC_CheckField, 6, 10, 0, 249, 50, // Skip to: 13726 -/* 677 */ MCD_OPC_Decode, 162, 11, 43, // Opcode: SDIV -/* 681 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 699 -/* 685 */ MCD_OPC_CheckPredicate, 13, 237, 50, // Skip to: 13726 -/* 689 */ MCD_OPC_CheckField, 6, 10, 0, 231, 50, // Skip to: 13726 -/* 695 */ MCD_OPC_Decode, 222, 13, 43, // Opcode: UDIV -/* 699 */ MCD_OPC_FilterValue, 32, 13, 0, // Skip to: 716 -/* 703 */ MCD_OPC_CheckPredicate, 5, 219, 50, // Skip to: 13726 -/* 707 */ MCD_OPC_CheckField, 6, 5, 0, 213, 50, // Skip to: 13726 -/* 713 */ MCD_OPC_Decode, 25, 35, // Opcode: ADD -/* 716 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 733 -/* 720 */ MCD_OPC_CheckPredicate, 5, 202, 50, // Skip to: 13726 -/* 724 */ MCD_OPC_CheckField, 6, 5, 0, 196, 50, // Skip to: 13726 -/* 730 */ MCD_OPC_Decode, 77, 35, // Opcode: ADDu -/* 733 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 751 -/* 737 */ MCD_OPC_CheckPredicate, 5, 185, 50, // Skip to: 13726 -/* 741 */ MCD_OPC_CheckField, 6, 5, 0, 179, 50, // Skip to: 13726 -/* 747 */ MCD_OPC_Decode, 190, 12, 35, // Opcode: SUB -/* 751 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 769 -/* 755 */ MCD_OPC_CheckPredicate, 5, 167, 50, // Skip to: 13726 -/* 759 */ MCD_OPC_CheckField, 6, 5, 0, 161, 50, // Skip to: 13726 -/* 765 */ MCD_OPC_Decode, 230, 12, 35, // Opcode: SUBu -/* 769 */ MCD_OPC_FilterValue, 36, 13, 0, // Skip to: 786 -/* 773 */ MCD_OPC_CheckPredicate, 1, 149, 50, // Skip to: 13726 -/* 777 */ MCD_OPC_CheckField, 6, 5, 0, 143, 50, // Skip to: 13726 -/* 783 */ MCD_OPC_Decode, 83, 35, // Opcode: AND -/* 786 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 804 -/* 790 */ MCD_OPC_CheckPredicate, 1, 132, 50, // Skip to: 13726 -/* 794 */ MCD_OPC_CheckField, 6, 5, 0, 126, 50, // Skip to: 13726 -/* 800 */ MCD_OPC_Decode, 133, 10, 35, // Opcode: OR -/* 804 */ MCD_OPC_FilterValue, 38, 14, 0, // Skip to: 822 -/* 808 */ MCD_OPC_CheckPredicate, 1, 114, 50, // Skip to: 13726 -/* 812 */ MCD_OPC_CheckField, 6, 5, 0, 108, 50, // Skip to: 13726 -/* 818 */ MCD_OPC_Decode, 236, 13, 35, // Opcode: XOR -/* 822 */ MCD_OPC_FilterValue, 39, 14, 0, // Skip to: 840 -/* 826 */ MCD_OPC_CheckPredicate, 5, 96, 50, // Skip to: 13726 -/* 830 */ MCD_OPC_CheckField, 6, 5, 0, 90, 50, // Skip to: 13726 -/* 836 */ MCD_OPC_Decode, 250, 9, 35, // Opcode: NOR -/* 840 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 858 -/* 844 */ MCD_OPC_CheckPredicate, 5, 78, 50, // Skip to: 13726 -/* 848 */ MCD_OPC_CheckField, 6, 5, 0, 72, 50, // Skip to: 13726 -/* 854 */ MCD_OPC_Decode, 240, 11, 35, // Opcode: SLT -/* 858 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 876 -/* 862 */ MCD_OPC_CheckPredicate, 5, 60, 50, // Skip to: 13726 -/* 866 */ MCD_OPC_CheckField, 6, 5, 0, 54, 50, // Skip to: 13726 -/* 872 */ MCD_OPC_Decode, 249, 11, 35, // Opcode: SLTu -/* 876 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 888 -/* 880 */ MCD_OPC_CheckPredicate, 15, 42, 50, // Skip to: 13726 -/* 884 */ MCD_OPC_Decode, 186, 13, 72, // Opcode: TGE -/* 888 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 900 -/* 892 */ MCD_OPC_CheckPredicate, 15, 30, 50, // Skip to: 13726 -/* 896 */ MCD_OPC_Decode, 191, 13, 72, // Opcode: TGEU -/* 900 */ MCD_OPC_FilterValue, 50, 8, 0, // Skip to: 912 -/* 904 */ MCD_OPC_CheckPredicate, 15, 18, 50, // Skip to: 13726 -/* 908 */ MCD_OPC_Decode, 202, 13, 72, // Opcode: TLT -/* 912 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 924 -/* 916 */ MCD_OPC_CheckPredicate, 15, 6, 50, // Skip to: 13726 -/* 920 */ MCD_OPC_Decode, 206, 13, 72, // Opcode: TLTU -/* 924 */ MCD_OPC_FilterValue, 52, 8, 0, // Skip to: 936 -/* 928 */ MCD_OPC_CheckPredicate, 15, 250, 49, // Skip to: 13726 -/* 932 */ MCD_OPC_Decode, 182, 13, 72, // Opcode: TEQ -/* 936 */ MCD_OPC_FilterValue, 54, 242, 49, // Skip to: 13726 -/* 940 */ MCD_OPC_CheckPredicate, 15, 238, 49, // Skip to: 13726 -/* 944 */ MCD_OPC_Decode, 209, 13, 72, // Opcode: TNE -/* 948 */ MCD_OPC_FilterValue, 1, 201, 0, // Skip to: 1153 -/* 952 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 955 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 967 -/* 959 */ MCD_OPC_CheckPredicate, 5, 219, 49, // Skip to: 13726 -/* 963 */ MCD_OPC_Decode, 131, 2, 73, // Opcode: BLTZ -/* 967 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 979 -/* 971 */ MCD_OPC_CheckPredicate, 5, 207, 49, // Skip to: 13726 -/* 975 */ MCD_OPC_Decode, 217, 1, 73, // Opcode: BGEZ -/* 979 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 991 -/* 983 */ MCD_OPC_CheckPredicate, 16, 195, 49, // Skip to: 13726 -/* 987 */ MCD_OPC_Decode, 139, 2, 73, // Opcode: BLTZL -/* 991 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1003 -/* 995 */ MCD_OPC_CheckPredicate, 16, 183, 49, // Skip to: 13726 -/* 999 */ MCD_OPC_Decode, 225, 1, 73, // Opcode: BGEZL -/* 1003 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1015 -/* 1007 */ MCD_OPC_CheckPredicate, 16, 171, 49, // Skip to: 13726 -/* 1011 */ MCD_OPC_Decode, 187, 13, 74, // Opcode: TGEI -/* 1015 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1027 -/* 1019 */ MCD_OPC_CheckPredicate, 16, 159, 49, // Skip to: 13726 -/* 1023 */ MCD_OPC_Decode, 188, 13, 74, // Opcode: TGEIU -/* 1027 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1039 -/* 1031 */ MCD_OPC_CheckPredicate, 16, 147, 49, // Skip to: 13726 -/* 1035 */ MCD_OPC_Decode, 203, 13, 74, // Opcode: TLTI -/* 1039 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1051 -/* 1043 */ MCD_OPC_CheckPredicate, 16, 135, 49, // Skip to: 13726 -/* 1047 */ MCD_OPC_Decode, 221, 13, 74, // Opcode: TTLTIU -/* 1051 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 1063 -/* 1055 */ MCD_OPC_CheckPredicate, 16, 123, 49, // Skip to: 13726 -/* 1059 */ MCD_OPC_Decode, 183, 13, 74, // Opcode: TEQI -/* 1063 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1075 -/* 1067 */ MCD_OPC_CheckPredicate, 16, 111, 49, // Skip to: 13726 -/* 1071 */ MCD_OPC_Decode, 210, 13, 74, // Opcode: TNEI -/* 1075 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 1087 -/* 1079 */ MCD_OPC_CheckPredicate, 13, 99, 49, // Skip to: 13726 -/* 1083 */ MCD_OPC_Decode, 133, 2, 73, // Opcode: BLTZAL -/* 1087 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1099 -/* 1091 */ MCD_OPC_CheckPredicate, 13, 87, 49, // Skip to: 13726 -/* 1095 */ MCD_OPC_Decode, 219, 1, 73, // Opcode: BGEZAL -/* 1099 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 1111 -/* 1103 */ MCD_OPC_CheckPredicate, 16, 75, 49, // Skip to: 13726 -/* 1107 */ MCD_OPC_Decode, 135, 2, 73, // Opcode: BLTZALL -/* 1111 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 1123 -/* 1115 */ MCD_OPC_CheckPredicate, 16, 63, 49, // Skip to: 13726 -/* 1119 */ MCD_OPC_Decode, 221, 1, 73, // Opcode: BGEZALL -/* 1123 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 1141 -/* 1127 */ MCD_OPC_CheckPredicate, 12, 51, 49, // Skip to: 13726 -/* 1131 */ MCD_OPC_CheckField, 21, 5, 0, 45, 49, // Skip to: 13726 -/* 1137 */ MCD_OPC_Decode, 169, 2, 75, // Opcode: BPOSGE32 -/* 1141 */ MCD_OPC_FilterValue, 31, 37, 49, // Skip to: 13726 -/* 1145 */ MCD_OPC_CheckPredicate, 6, 33, 49, // Skip to: 13726 -/* 1149 */ MCD_OPC_Decode, 130, 13, 76, // Opcode: SYNCI -/* 1153 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1165 -/* 1157 */ MCD_OPC_CheckPredicate, 10, 21, 49, // Skip to: 13726 -/* 1161 */ MCD_OPC_Decode, 247, 6, 77, // Opcode: J -/* 1165 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1177 -/* 1169 */ MCD_OPC_CheckPredicate, 5, 9, 49, // Skip to: 13726 -/* 1173 */ MCD_OPC_Decode, 248, 6, 77, // Opcode: JAL -/* 1177 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1189 -/* 1181 */ MCD_OPC_CheckPredicate, 5, 253, 48, // Skip to: 13726 -/* 1185 */ MCD_OPC_Decode, 206, 1, 78, // Opcode: BEQ -/* 1189 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1201 -/* 1193 */ MCD_OPC_CheckPredicate, 5, 241, 48, // Skip to: 13726 -/* 1197 */ MCD_OPC_Decode, 145, 2, 78, // Opcode: BNE -/* 1201 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1219 -/* 1205 */ MCD_OPC_CheckPredicate, 5, 229, 48, // Skip to: 13726 -/* 1209 */ MCD_OPC_CheckField, 16, 5, 0, 223, 48, // Skip to: 13726 -/* 1215 */ MCD_OPC_Decode, 251, 1, 73, // Opcode: BLEZ -/* 1219 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1237 -/* 1223 */ MCD_OPC_CheckPredicate, 5, 211, 48, // Skip to: 13726 -/* 1227 */ MCD_OPC_CheckField, 16, 5, 0, 205, 48, // Skip to: 13726 -/* 1233 */ MCD_OPC_Decode, 227, 1, 73, // Opcode: BGTZ -/* 1237 */ MCD_OPC_FilterValue, 8, 7, 0, // Skip to: 1248 -/* 1241 */ MCD_OPC_CheckPredicate, 13, 193, 48, // Skip to: 13726 -/* 1245 */ MCD_OPC_Decode, 73, 79, // Opcode: ADDi -/* 1248 */ MCD_OPC_FilterValue, 9, 7, 0, // Skip to: 1259 -/* 1252 */ MCD_OPC_CheckPredicate, 1, 182, 48, // Skip to: 13726 -/* 1256 */ MCD_OPC_Decode, 75, 79, // Opcode: ADDiu -/* 1259 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1271 -/* 1263 */ MCD_OPC_CheckPredicate, 5, 171, 48, // Skip to: 13726 -/* 1267 */ MCD_OPC_Decode, 243, 11, 79, // Opcode: SLTi -/* 1271 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1283 -/* 1275 */ MCD_OPC_CheckPredicate, 5, 159, 48, // Skip to: 13726 -/* 1279 */ MCD_OPC_Decode, 246, 11, 79, // Opcode: SLTiu -/* 1283 */ MCD_OPC_FilterValue, 12, 7, 0, // Skip to: 1294 -/* 1287 */ MCD_OPC_CheckPredicate, 1, 147, 48, // Skip to: 13726 -/* 1291 */ MCD_OPC_Decode, 93, 80, // Opcode: ANDi -/* 1294 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1306 -/* 1298 */ MCD_OPC_CheckPredicate, 5, 136, 48, // Skip to: 13726 -/* 1302 */ MCD_OPC_Decode, 142, 10, 80, // Opcode: ORi -/* 1306 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1318 -/* 1310 */ MCD_OPC_CheckPredicate, 5, 124, 48, // Skip to: 13726 -/* 1314 */ MCD_OPC_Decode, 245, 13, 80, // Opcode: XORi -/* 1318 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 1336 -/* 1322 */ MCD_OPC_CheckPredicate, 5, 112, 48, // Skip to: 13726 -/* 1326 */ MCD_OPC_CheckField, 21, 5, 0, 106, 48, // Skip to: 13726 -/* 1332 */ MCD_OPC_Decode, 210, 7, 52, // Opcode: LUi -/* 1336 */ MCD_OPC_FilterValue, 16, 220, 0, // Skip to: 1560 -/* 1340 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1343 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1361 -/* 1347 */ MCD_OPC_CheckPredicate, 10, 87, 48, // Skip to: 13726 -/* 1351 */ MCD_OPC_CheckField, 3, 8, 0, 81, 48, // Skip to: 13726 -/* 1357 */ MCD_OPC_Decode, 179, 8, 81, // Opcode: MFC0 -/* 1361 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1379 -/* 1365 */ MCD_OPC_CheckPredicate, 10, 69, 48, // Skip to: 13726 -/* 1369 */ MCD_OPC_CheckField, 3, 8, 0, 63, 48, // Skip to: 13726 -/* 1375 */ MCD_OPC_Decode, 169, 9, 81, // Opcode: MTC0 -/* 1379 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 1434 -/* 1383 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 1386 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1398 -/* 1390 */ MCD_OPC_CheckPredicate, 13, 44, 48, // Skip to: 13726 -/* 1394 */ MCD_OPC_Decode, 176, 1, 82, // Opcode: BC0F -/* 1398 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1410 -/* 1402 */ MCD_OPC_CheckPredicate, 13, 32, 48, // Skip to: 13726 -/* 1406 */ MCD_OPC_Decode, 178, 1, 82, // Opcode: BC0T -/* 1410 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1422 -/* 1414 */ MCD_OPC_CheckPredicate, 13, 20, 48, // Skip to: 13726 -/* 1418 */ MCD_OPC_Decode, 177, 1, 82, // Opcode: BC0FL -/* 1422 */ MCD_OPC_FilterValue, 3, 12, 48, // Skip to: 13726 -/* 1426 */ MCD_OPC_CheckPredicate, 13, 8, 48, // Skip to: 13726 -/* 1430 */ MCD_OPC_Decode, 179, 1, 82, // Opcode: BC0TL -/* 1434 */ MCD_OPC_FilterValue, 11, 31, 0, // Skip to: 1469 -/* 1438 */ MCD_OPC_ExtractField, 0, 16, // Inst{15-0} ... -/* 1441 */ MCD_OPC_FilterValue, 128, 192, 1, 8, 0, // Skip to: 1455 -/* 1447 */ MCD_OPC_CheckPredicate, 6, 243, 47, // Skip to: 13726 -/* 1451 */ MCD_OPC_Decode, 179, 4, 42, // Opcode: DI -/* 1455 */ MCD_OPC_FilterValue, 160, 192, 1, 233, 47, // Skip to: 13726 -/* 1461 */ MCD_OPC_CheckPredicate, 6, 229, 47, // Skip to: 13726 -/* 1465 */ MCD_OPC_Decode, 141, 5, 42, // Opcode: EI -/* 1469 */ MCD_OPC_FilterValue, 16, 221, 47, // Skip to: 13726 -/* 1473 */ MCD_OPC_ExtractField, 0, 21, // Inst{20-0} ... -/* 1476 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1488 -/* 1480 */ MCD_OPC_CheckPredicate, 5, 210, 47, // Skip to: 13726 -/* 1484 */ MCD_OPC_Decode, 196, 13, 0, // Opcode: TLBR -/* 1488 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1500 -/* 1492 */ MCD_OPC_CheckPredicate, 5, 198, 47, // Skip to: 13726 -/* 1496 */ MCD_OPC_Decode, 198, 13, 0, // Opcode: TLBWI -/* 1500 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1512 -/* 1504 */ MCD_OPC_CheckPredicate, 5, 186, 47, // Skip to: 13726 -/* 1508 */ MCD_OPC_Decode, 200, 13, 0, // Opcode: TLBWR -/* 1512 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1524 -/* 1516 */ MCD_OPC_CheckPredicate, 5, 174, 47, // Skip to: 13726 -/* 1520 */ MCD_OPC_Decode, 194, 13, 0, // Opcode: TLBP -/* 1524 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 1536 -/* 1528 */ MCD_OPC_CheckPredicate, 17, 162, 47, // Skip to: 13726 -/* 1532 */ MCD_OPC_Decode, 143, 5, 0, // Opcode: ERET -/* 1536 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 1548 -/* 1540 */ MCD_OPC_CheckPredicate, 10, 150, 47, // Skip to: 13726 -/* 1544 */ MCD_OPC_Decode, 174, 4, 0, // Opcode: DERET -/* 1548 */ MCD_OPC_FilterValue, 32, 142, 47, // Skip to: 13726 -/* 1552 */ MCD_OPC_CheckPredicate, 18, 138, 47, // Skip to: 13726 -/* 1556 */ MCD_OPC_Decode, 231, 13, 0, // Opcode: WAIT -/* 1560 */ MCD_OPC_FilterValue, 17, 21, 6, // Skip to: 3121 -/* 1564 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1567 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1585 -/* 1571 */ MCD_OPC_CheckPredicate, 5, 119, 47, // Skip to: 13726 -/* 1575 */ MCD_OPC_CheckField, 0, 11, 0, 113, 47, // Skip to: 13726 -/* 1581 */ MCD_OPC_Decode, 180, 8, 83, // Opcode: MFC1 -/* 1585 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 1603 -/* 1589 */ MCD_OPC_CheckPredicate, 19, 101, 47, // Skip to: 13726 -/* 1593 */ MCD_OPC_CheckField, 0, 11, 0, 95, 47, // Skip to: 13726 -/* 1599 */ MCD_OPC_Decode, 197, 4, 84, // Opcode: DMFC1 -/* 1603 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 1621 -/* 1607 */ MCD_OPC_CheckPredicate, 5, 83, 47, // Skip to: 13726 -/* 1611 */ MCD_OPC_CheckField, 0, 11, 0, 77, 47, // Skip to: 13726 -/* 1617 */ MCD_OPC_Decode, 238, 2, 85, // Opcode: CFC1 -/* 1621 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 1639 -/* 1625 */ MCD_OPC_CheckPredicate, 20, 65, 47, // Skip to: 13726 -/* 1629 */ MCD_OPC_CheckField, 0, 11, 0, 59, 47, // Skip to: 13726 -/* 1635 */ MCD_OPC_Decode, 183, 8, 86, // Opcode: MFHC1_D32 -/* 1639 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1657 -/* 1643 */ MCD_OPC_CheckPredicate, 5, 47, 47, // Skip to: 13726 -/* 1647 */ MCD_OPC_CheckField, 0, 11, 0, 41, 47, // Skip to: 13726 -/* 1653 */ MCD_OPC_Decode, 170, 9, 87, // Opcode: MTC1 -/* 1657 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 1675 -/* 1661 */ MCD_OPC_CheckPredicate, 19, 29, 47, // Skip to: 13726 -/* 1665 */ MCD_OPC_CheckField, 0, 11, 0, 23, 47, // Skip to: 13726 -/* 1671 */ MCD_OPC_Decode, 202, 4, 88, // Opcode: DMTC1 -/* 1675 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1693 -/* 1679 */ MCD_OPC_CheckPredicate, 5, 11, 47, // Skip to: 13726 -/* 1683 */ MCD_OPC_CheckField, 0, 11, 0, 5, 47, // Skip to: 13726 -/* 1689 */ MCD_OPC_Decode, 210, 3, 89, // Opcode: CTC1 -/* 1693 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1711 -/* 1697 */ MCD_OPC_CheckPredicate, 20, 249, 46, // Skip to: 13726 -/* 1701 */ MCD_OPC_CheckField, 0, 11, 0, 243, 46, // Skip to: 13726 -/* 1707 */ MCD_OPC_Decode, 173, 9, 90, // Opcode: MTHC1_D32 -/* 1711 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 1766 -/* 1715 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 1718 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1730 -/* 1722 */ MCD_OPC_CheckPredicate, 13, 224, 46, // Skip to: 13726 -/* 1726 */ MCD_OPC_Decode, 181, 1, 91, // Opcode: BC1F -/* 1730 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1742 -/* 1734 */ MCD_OPC_CheckPredicate, 13, 212, 46, // Skip to: 13726 -/* 1738 */ MCD_OPC_Decode, 185, 1, 91, // Opcode: BC1T -/* 1742 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1754 -/* 1746 */ MCD_OPC_CheckPredicate, 16, 200, 46, // Skip to: 13726 -/* 1750 */ MCD_OPC_Decode, 182, 1, 91, // Opcode: BC1FL -/* 1754 */ MCD_OPC_FilterValue, 3, 192, 46, // Skip to: 13726 -/* 1758 */ MCD_OPC_CheckPredicate, 16, 188, 46, // Skip to: 13726 -/* 1762 */ MCD_OPC_Decode, 186, 1, 91, // Opcode: BC1TL -/* 1766 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1778 -/* 1770 */ MCD_OPC_CheckPredicate, 8, 176, 46, // Skip to: 13726 -/* 1774 */ MCD_OPC_Decode, 192, 2, 92, // Opcode: BZ_V -/* 1778 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 1790 -/* 1782 */ MCD_OPC_CheckPredicate, 8, 164, 46, // Skip to: 13726 -/* 1786 */ MCD_OPC_Decode, 166, 2, 92, // Opcode: BNZ_V -/* 1790 */ MCD_OPC_FilterValue, 16, 80, 2, // Skip to: 2386 -/* 1794 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1797 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1809 -/* 1801 */ MCD_OPC_CheckPredicate, 5, 145, 46, // Skip to: 13726 -/* 1805 */ MCD_OPC_Decode, 174, 5, 93, // Opcode: FADD_S -/* 1809 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1821 -/* 1813 */ MCD_OPC_CheckPredicate, 5, 133, 46, // Skip to: 13726 -/* 1817 */ MCD_OPC_Decode, 176, 6, 93, // Opcode: FSUB_S -/* 1821 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1833 -/* 1825 */ MCD_OPC_CheckPredicate, 5, 121, 46, // Skip to: 13726 -/* 1829 */ MCD_OPC_Decode, 139, 6, 93, // Opcode: FMUL_S -/* 1833 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1845 -/* 1837 */ MCD_OPC_CheckPredicate, 5, 109, 46, // Skip to: 13726 -/* 1841 */ MCD_OPC_Decode, 210, 5, 93, // Opcode: FDIV_S -/* 1845 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1863 -/* 1849 */ MCD_OPC_CheckPredicate, 15, 97, 46, // Skip to: 13726 -/* 1853 */ MCD_OPC_CheckField, 16, 5, 0, 91, 46, // Skip to: 13726 -/* 1859 */ MCD_OPC_Decode, 169, 6, 94, // Opcode: FSQRT_S -/* 1863 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 1881 -/* 1867 */ MCD_OPC_CheckPredicate, 5, 79, 46, // Skip to: 13726 -/* 1871 */ MCD_OPC_CheckField, 16, 5, 0, 73, 46, // Skip to: 13726 -/* 1877 */ MCD_OPC_Decode, 167, 5, 94, // Opcode: FABS_S -/* 1881 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1899 -/* 1885 */ MCD_OPC_CheckPredicate, 5, 61, 46, // Skip to: 13726 -/* 1889 */ MCD_OPC_CheckField, 16, 5, 0, 55, 46, // Skip to: 13726 -/* 1895 */ MCD_OPC_Decode, 131, 6, 94, // Opcode: FMOV_S -/* 1899 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1917 -/* 1903 */ MCD_OPC_CheckPredicate, 5, 43, 46, // Skip to: 13726 -/* 1907 */ MCD_OPC_CheckField, 16, 5, 0, 37, 46, // Skip to: 13726 -/* 1913 */ MCD_OPC_Decode, 145, 6, 94, // Opcode: FNEG_S -/* 1917 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 1935 -/* 1921 */ MCD_OPC_CheckPredicate, 15, 25, 46, // Skip to: 13726 -/* 1925 */ MCD_OPC_CheckField, 16, 5, 0, 19, 46, // Skip to: 13726 -/* 1931 */ MCD_OPC_Decode, 128, 11, 94, // Opcode: ROUND_W_S -/* 1935 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 1953 -/* 1939 */ MCD_OPC_CheckPredicate, 15, 7, 46, // Skip to: 13726 -/* 1943 */ MCD_OPC_CheckField, 16, 5, 0, 1, 46, // Skip to: 13726 -/* 1949 */ MCD_OPC_Decode, 219, 13, 94, // Opcode: TRUNC_W_S -/* 1953 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 1971 -/* 1957 */ MCD_OPC_CheckPredicate, 15, 245, 45, // Skip to: 13726 -/* 1961 */ MCD_OPC_CheckField, 16, 5, 0, 239, 45, // Skip to: 13726 -/* 1967 */ MCD_OPC_Decode, 228, 2, 94, // Opcode: CEIL_W_S -/* 1971 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 1989 -/* 1975 */ MCD_OPC_CheckPredicate, 15, 227, 45, // Skip to: 13726 -/* 1979 */ MCD_OPC_CheckField, 16, 5, 0, 221, 45, // Skip to: 13726 -/* 1985 */ MCD_OPC_Decode, 244, 5, 94, // Opcode: FLOOR_W_S -/* 1989 */ MCD_OPC_FilterValue, 17, 27, 0, // Skip to: 2020 -/* 1993 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 1996 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2008 -/* 2000 */ MCD_OPC_CheckPredicate, 7, 202, 45, // Skip to: 13726 -/* 2004 */ MCD_OPC_Decode, 242, 8, 95, // Opcode: MOVF_S -/* 2008 */ MCD_OPC_FilterValue, 1, 194, 45, // Skip to: 13726 -/* 2012 */ MCD_OPC_CheckPredicate, 7, 190, 45, // Skip to: 13726 -/* 2016 */ MCD_OPC_Decode, 134, 9, 95, // Opcode: MOVT_S -/* 2020 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2032 -/* 2024 */ MCD_OPC_CheckPredicate, 7, 178, 45, // Skip to: 13726 -/* 2028 */ MCD_OPC_Decode, 146, 9, 96, // Opcode: MOVZ_I_S -/* 2032 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2044 -/* 2036 */ MCD_OPC_CheckPredicate, 7, 166, 45, // Skip to: 13726 -/* 2040 */ MCD_OPC_Decode, 254, 8, 96, // Opcode: MOVN_I_S -/* 2044 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 2062 -/* 2048 */ MCD_OPC_CheckPredicate, 21, 154, 45, // Skip to: 13726 -/* 2052 */ MCD_OPC_CheckField, 16, 5, 0, 148, 45, // Skip to: 13726 -/* 2058 */ MCD_OPC_Decode, 213, 3, 97, // Opcode: CVT_D32_S -/* 2062 */ MCD_OPC_FilterValue, 36, 14, 0, // Skip to: 2080 -/* 2066 */ MCD_OPC_CheckPredicate, 5, 136, 45, // Skip to: 13726 -/* 2070 */ MCD_OPC_CheckField, 16, 5, 0, 130, 45, // Skip to: 13726 -/* 2076 */ MCD_OPC_Decode, 233, 3, 94, // Opcode: CVT_W_S -/* 2080 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 2098 -/* 2084 */ MCD_OPC_CheckPredicate, 22, 118, 45, // Skip to: 13726 -/* 2088 */ MCD_OPC_CheckField, 16, 5, 0, 112, 45, // Skip to: 13726 -/* 2094 */ MCD_OPC_Decode, 222, 3, 98, // Opcode: CVT_L_S -/* 2098 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 2116 -/* 2102 */ MCD_OPC_CheckPredicate, 13, 100, 45, // Skip to: 13726 -/* 2106 */ MCD_OPC_CheckField, 6, 5, 0, 94, 45, // Skip to: 13726 -/* 2112 */ MCD_OPC_Decode, 240, 3, 99, // Opcode: C_F_S -/* 2116 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 2134 -/* 2120 */ MCD_OPC_CheckPredicate, 13, 82, 45, // Skip to: 13726 -/* 2124 */ MCD_OPC_CheckField, 6, 5, 0, 76, 45, // Skip to: 13726 -/* 2130 */ MCD_OPC_Decode, 154, 4, 99, // Opcode: C_UN_S -/* 2134 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 2152 -/* 2138 */ MCD_OPC_CheckPredicate, 13, 64, 45, // Skip to: 13726 -/* 2142 */ MCD_OPC_CheckField, 6, 5, 0, 58, 45, // Skip to: 13726 -/* 2148 */ MCD_OPC_Decode, 237, 3, 99, // Opcode: C_EQ_S -/* 2152 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 2170 -/* 2156 */ MCD_OPC_CheckPredicate, 13, 46, 45, // Skip to: 13726 -/* 2160 */ MCD_OPC_CheckField, 6, 5, 0, 40, 45, // Skip to: 13726 -/* 2166 */ MCD_OPC_Decode, 145, 4, 99, // Opcode: C_UEQ_S -/* 2170 */ MCD_OPC_FilterValue, 52, 14, 0, // Skip to: 2188 -/* 2174 */ MCD_OPC_CheckPredicate, 13, 28, 45, // Skip to: 13726 -/* 2178 */ MCD_OPC_CheckField, 6, 5, 0, 22, 45, // Skip to: 13726 -/* 2184 */ MCD_OPC_Decode, 136, 4, 99, // Opcode: C_OLT_S -/* 2188 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 2206 -/* 2192 */ MCD_OPC_CheckPredicate, 13, 10, 45, // Skip to: 13726 -/* 2196 */ MCD_OPC_CheckField, 6, 5, 0, 4, 45, // Skip to: 13726 -/* 2202 */ MCD_OPC_Decode, 151, 4, 99, // Opcode: C_ULT_S -/* 2206 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 2224 -/* 2210 */ MCD_OPC_CheckPredicate, 13, 248, 44, // Skip to: 13726 -/* 2214 */ MCD_OPC_CheckField, 6, 5, 0, 242, 44, // Skip to: 13726 -/* 2220 */ MCD_OPC_Decode, 133, 4, 99, // Opcode: C_OLE_S -/* 2224 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 2242 -/* 2228 */ MCD_OPC_CheckPredicate, 13, 230, 44, // Skip to: 13726 -/* 2232 */ MCD_OPC_CheckField, 6, 5, 0, 224, 44, // Skip to: 13726 -/* 2238 */ MCD_OPC_Decode, 148, 4, 99, // Opcode: C_ULE_S -/* 2242 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 2260 -/* 2246 */ MCD_OPC_CheckPredicate, 13, 212, 44, // Skip to: 13726 -/* 2250 */ MCD_OPC_CheckField, 6, 5, 0, 206, 44, // Skip to: 13726 -/* 2256 */ MCD_OPC_Decode, 142, 4, 99, // Opcode: C_SF_S -/* 2260 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 2278 -/* 2264 */ MCD_OPC_CheckPredicate, 13, 194, 44, // Skip to: 13726 -/* 2268 */ MCD_OPC_CheckField, 6, 5, 0, 188, 44, // Skip to: 13726 -/* 2274 */ MCD_OPC_Decode, 252, 3, 99, // Opcode: C_NGLE_S -/* 2278 */ MCD_OPC_FilterValue, 58, 14, 0, // Skip to: 2296 -/* 2282 */ MCD_OPC_CheckPredicate, 13, 176, 44, // Skip to: 13726 -/* 2286 */ MCD_OPC_CheckField, 6, 5, 0, 170, 44, // Skip to: 13726 -/* 2292 */ MCD_OPC_Decode, 139, 4, 99, // Opcode: C_SEQ_S -/* 2296 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 2314 -/* 2300 */ MCD_OPC_CheckPredicate, 13, 158, 44, // Skip to: 13726 -/* 2304 */ MCD_OPC_CheckField, 6, 5, 0, 152, 44, // Skip to: 13726 -/* 2310 */ MCD_OPC_Decode, 255, 3, 99, // Opcode: C_NGL_S -/* 2314 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 2332 -/* 2318 */ MCD_OPC_CheckPredicate, 13, 140, 44, // Skip to: 13726 -/* 2322 */ MCD_OPC_CheckField, 6, 5, 0, 134, 44, // Skip to: 13726 -/* 2328 */ MCD_OPC_Decode, 246, 3, 99, // Opcode: C_LT_S -/* 2332 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 2350 -/* 2336 */ MCD_OPC_CheckPredicate, 13, 122, 44, // Skip to: 13726 -/* 2340 */ MCD_OPC_CheckField, 6, 5, 0, 116, 44, // Skip to: 13726 -/* 2346 */ MCD_OPC_Decode, 249, 3, 99, // Opcode: C_NGE_S -/* 2350 */ MCD_OPC_FilterValue, 62, 14, 0, // Skip to: 2368 -/* 2354 */ MCD_OPC_CheckPredicate, 13, 104, 44, // Skip to: 13726 -/* 2358 */ MCD_OPC_CheckField, 6, 5, 0, 98, 44, // Skip to: 13726 -/* 2364 */ MCD_OPC_Decode, 243, 3, 99, // Opcode: C_LE_S -/* 2368 */ MCD_OPC_FilterValue, 63, 90, 44, // Skip to: 13726 -/* 2372 */ MCD_OPC_CheckPredicate, 13, 86, 44, // Skip to: 13726 -/* 2376 */ MCD_OPC_CheckField, 6, 5, 0, 80, 44, // Skip to: 13726 -/* 2382 */ MCD_OPC_Decode, 130, 4, 99, // Opcode: C_NGT_S -/* 2386 */ MCD_OPC_FilterValue, 17, 80, 2, // Skip to: 2982 -/* 2390 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 2393 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2405 -/* 2397 */ MCD_OPC_CheckPredicate, 21, 61, 44, // Skip to: 13726 -/* 2401 */ MCD_OPC_Decode, 171, 5, 100, // Opcode: FADD_D32 -/* 2405 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 2417 -/* 2409 */ MCD_OPC_CheckPredicate, 21, 49, 44, // Skip to: 13726 -/* 2413 */ MCD_OPC_Decode, 173, 6, 100, // Opcode: FSUB_D32 -/* 2417 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 2429 -/* 2421 */ MCD_OPC_CheckPredicate, 21, 37, 44, // Skip to: 13726 -/* 2425 */ MCD_OPC_Decode, 136, 6, 100, // Opcode: FMUL_D32 -/* 2429 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 2441 -/* 2433 */ MCD_OPC_CheckPredicate, 21, 25, 44, // Skip to: 13726 -/* 2437 */ MCD_OPC_Decode, 207, 5, 100, // Opcode: FDIV_D32 -/* 2441 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 2459 -/* 2445 */ MCD_OPC_CheckPredicate, 23, 13, 44, // Skip to: 13726 -/* 2449 */ MCD_OPC_CheckField, 16, 5, 0, 7, 44, // Skip to: 13726 -/* 2455 */ MCD_OPC_Decode, 166, 6, 101, // Opcode: FSQRT_D32 -/* 2459 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 2477 -/* 2463 */ MCD_OPC_CheckPredicate, 21, 251, 43, // Skip to: 13726 -/* 2467 */ MCD_OPC_CheckField, 16, 5, 0, 245, 43, // Skip to: 13726 -/* 2473 */ MCD_OPC_Decode, 164, 5, 101, // Opcode: FABS_D32 -/* 2477 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 2495 -/* 2481 */ MCD_OPC_CheckPredicate, 21, 233, 43, // Skip to: 13726 -/* 2485 */ MCD_OPC_CheckField, 16, 5, 0, 227, 43, // Skip to: 13726 -/* 2491 */ MCD_OPC_Decode, 128, 6, 101, // Opcode: FMOV_D32 -/* 2495 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 2513 -/* 2499 */ MCD_OPC_CheckPredicate, 21, 215, 43, // Skip to: 13726 -/* 2503 */ MCD_OPC_CheckField, 16, 5, 0, 209, 43, // Skip to: 13726 -/* 2509 */ MCD_OPC_Decode, 142, 6, 101, // Opcode: FNEG_D32 -/* 2513 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 2531 -/* 2517 */ MCD_OPC_CheckPredicate, 23, 197, 43, // Skip to: 13726 -/* 2521 */ MCD_OPC_CheckField, 16, 5, 0, 191, 43, // Skip to: 13726 -/* 2527 */ MCD_OPC_Decode, 253, 10, 102, // Opcode: ROUND_W_D32 -/* 2531 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 2549 -/* 2535 */ MCD_OPC_CheckPredicate, 23, 179, 43, // Skip to: 13726 -/* 2539 */ MCD_OPC_CheckField, 16, 5, 0, 173, 43, // Skip to: 13726 -/* 2545 */ MCD_OPC_Decode, 216, 13, 102, // Opcode: TRUNC_W_D32 -/* 2549 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 2567 -/* 2553 */ MCD_OPC_CheckPredicate, 23, 161, 43, // Skip to: 13726 -/* 2557 */ MCD_OPC_CheckField, 16, 5, 0, 155, 43, // Skip to: 13726 -/* 2563 */ MCD_OPC_Decode, 225, 2, 102, // Opcode: CEIL_W_D32 -/* 2567 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 2585 -/* 2571 */ MCD_OPC_CheckPredicate, 23, 143, 43, // Skip to: 13726 -/* 2575 */ MCD_OPC_CheckField, 16, 5, 0, 137, 43, // Skip to: 13726 -/* 2581 */ MCD_OPC_Decode, 241, 5, 102, // Opcode: FLOOR_W_D32 -/* 2585 */ MCD_OPC_FilterValue, 17, 27, 0, // Skip to: 2616 -/* 2589 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 2592 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2604 -/* 2596 */ MCD_OPC_CheckPredicate, 24, 118, 43, // Skip to: 13726 -/* 2600 */ MCD_OPC_Decode, 236, 8, 103, // Opcode: MOVF_D32 -/* 2604 */ MCD_OPC_FilterValue, 1, 110, 43, // Skip to: 13726 -/* 2608 */ MCD_OPC_CheckPredicate, 24, 106, 43, // Skip to: 13726 -/* 2612 */ MCD_OPC_Decode, 128, 9, 103, // Opcode: MOVT_D32 -/* 2616 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2628 -/* 2620 */ MCD_OPC_CheckPredicate, 24, 94, 43, // Skip to: 13726 -/* 2624 */ MCD_OPC_Decode, 140, 9, 104, // Opcode: MOVZ_I_D32 -/* 2628 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2640 -/* 2632 */ MCD_OPC_CheckPredicate, 24, 82, 43, // Skip to: 13726 -/* 2636 */ MCD_OPC_Decode, 248, 8, 104, // Opcode: MOVN_I_D32 -/* 2640 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 2658 -/* 2644 */ MCD_OPC_CheckPredicate, 21, 70, 43, // Skip to: 13726 -/* 2648 */ MCD_OPC_CheckField, 16, 5, 0, 64, 43, // Skip to: 13726 -/* 2654 */ MCD_OPC_Decode, 224, 3, 102, // Opcode: CVT_S_D32 -/* 2658 */ MCD_OPC_FilterValue, 36, 14, 0, // Skip to: 2676 -/* 2662 */ MCD_OPC_CheckPredicate, 21, 52, 43, // Skip to: 13726 -/* 2666 */ MCD_OPC_CheckField, 16, 5, 0, 46, 43, // Skip to: 13726 -/* 2672 */ MCD_OPC_Decode, 230, 3, 102, // Opcode: CVT_W_D32 -/* 2676 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 2694 -/* 2680 */ MCD_OPC_CheckPredicate, 22, 34, 43, // Skip to: 13726 -/* 2684 */ MCD_OPC_CheckField, 16, 5, 0, 28, 43, // Skip to: 13726 -/* 2690 */ MCD_OPC_Decode, 220, 3, 105, // Opcode: CVT_L_D64 -/* 2694 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 2712 -/* 2698 */ MCD_OPC_CheckPredicate, 25, 16, 43, // Skip to: 13726 -/* 2702 */ MCD_OPC_CheckField, 6, 5, 0, 10, 43, // Skip to: 13726 -/* 2708 */ MCD_OPC_Decode, 238, 3, 106, // Opcode: C_F_D32 -/* 2712 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 2730 -/* 2716 */ MCD_OPC_CheckPredicate, 25, 254, 42, // Skip to: 13726 -/* 2720 */ MCD_OPC_CheckField, 6, 5, 0, 248, 42, // Skip to: 13726 -/* 2726 */ MCD_OPC_Decode, 152, 4, 106, // Opcode: C_UN_D32 -/* 2730 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 2748 -/* 2734 */ MCD_OPC_CheckPredicate, 25, 236, 42, // Skip to: 13726 -/* 2738 */ MCD_OPC_CheckField, 6, 5, 0, 230, 42, // Skip to: 13726 -/* 2744 */ MCD_OPC_Decode, 235, 3, 106, // Opcode: C_EQ_D32 -/* 2748 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 2766 -/* 2752 */ MCD_OPC_CheckPredicate, 25, 218, 42, // Skip to: 13726 -/* 2756 */ MCD_OPC_CheckField, 6, 5, 0, 212, 42, // Skip to: 13726 -/* 2762 */ MCD_OPC_Decode, 143, 4, 106, // Opcode: C_UEQ_D32 -/* 2766 */ MCD_OPC_FilterValue, 52, 14, 0, // Skip to: 2784 -/* 2770 */ MCD_OPC_CheckPredicate, 25, 200, 42, // Skip to: 13726 -/* 2774 */ MCD_OPC_CheckField, 6, 5, 0, 194, 42, // Skip to: 13726 -/* 2780 */ MCD_OPC_Decode, 134, 4, 106, // Opcode: C_OLT_D32 -/* 2784 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 2802 -/* 2788 */ MCD_OPC_CheckPredicate, 25, 182, 42, // Skip to: 13726 -/* 2792 */ MCD_OPC_CheckField, 6, 5, 0, 176, 42, // Skip to: 13726 -/* 2798 */ MCD_OPC_Decode, 149, 4, 106, // Opcode: C_ULT_D32 -/* 2802 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 2820 -/* 2806 */ MCD_OPC_CheckPredicate, 25, 164, 42, // Skip to: 13726 -/* 2810 */ MCD_OPC_CheckField, 6, 5, 0, 158, 42, // Skip to: 13726 -/* 2816 */ MCD_OPC_Decode, 131, 4, 106, // Opcode: C_OLE_D32 -/* 2820 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 2838 -/* 2824 */ MCD_OPC_CheckPredicate, 25, 146, 42, // Skip to: 13726 -/* 2828 */ MCD_OPC_CheckField, 6, 5, 0, 140, 42, // Skip to: 13726 -/* 2834 */ MCD_OPC_Decode, 146, 4, 106, // Opcode: C_ULE_D32 -/* 2838 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 2856 -/* 2842 */ MCD_OPC_CheckPredicate, 25, 128, 42, // Skip to: 13726 -/* 2846 */ MCD_OPC_CheckField, 6, 5, 0, 122, 42, // Skip to: 13726 -/* 2852 */ MCD_OPC_Decode, 140, 4, 106, // Opcode: C_SF_D32 -/* 2856 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 2874 -/* 2860 */ MCD_OPC_CheckPredicate, 25, 110, 42, // Skip to: 13726 -/* 2864 */ MCD_OPC_CheckField, 6, 5, 0, 104, 42, // Skip to: 13726 -/* 2870 */ MCD_OPC_Decode, 250, 3, 106, // Opcode: C_NGLE_D32 -/* 2874 */ MCD_OPC_FilterValue, 58, 14, 0, // Skip to: 2892 -/* 2878 */ MCD_OPC_CheckPredicate, 25, 92, 42, // Skip to: 13726 -/* 2882 */ MCD_OPC_CheckField, 6, 5, 0, 86, 42, // Skip to: 13726 -/* 2888 */ MCD_OPC_Decode, 137, 4, 106, // Opcode: C_SEQ_D32 -/* 2892 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 2910 -/* 2896 */ MCD_OPC_CheckPredicate, 25, 74, 42, // Skip to: 13726 -/* 2900 */ MCD_OPC_CheckField, 6, 5, 0, 68, 42, // Skip to: 13726 -/* 2906 */ MCD_OPC_Decode, 253, 3, 106, // Opcode: C_NGL_D32 -/* 2910 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 2928 -/* 2914 */ MCD_OPC_CheckPredicate, 25, 56, 42, // Skip to: 13726 -/* 2918 */ MCD_OPC_CheckField, 6, 5, 0, 50, 42, // Skip to: 13726 -/* 2924 */ MCD_OPC_Decode, 244, 3, 106, // Opcode: C_LT_D32 -/* 2928 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 2946 -/* 2932 */ MCD_OPC_CheckPredicate, 25, 38, 42, // Skip to: 13726 -/* 2936 */ MCD_OPC_CheckField, 6, 5, 0, 32, 42, // Skip to: 13726 -/* 2942 */ MCD_OPC_Decode, 247, 3, 106, // Opcode: C_NGE_D32 -/* 2946 */ MCD_OPC_FilterValue, 62, 14, 0, // Skip to: 2964 -/* 2950 */ MCD_OPC_CheckPredicate, 25, 20, 42, // Skip to: 13726 -/* 2954 */ MCD_OPC_CheckField, 6, 5, 0, 14, 42, // Skip to: 13726 -/* 2960 */ MCD_OPC_Decode, 241, 3, 106, // Opcode: C_LE_D32 -/* 2964 */ MCD_OPC_FilterValue, 63, 6, 42, // Skip to: 13726 -/* 2968 */ MCD_OPC_CheckPredicate, 25, 2, 42, // Skip to: 13726 -/* 2972 */ MCD_OPC_CheckField, 6, 5, 0, 252, 41, // Skip to: 13726 -/* 2978 */ MCD_OPC_Decode, 128, 4, 106, // Opcode: C_NGT_D32 -/* 2982 */ MCD_OPC_FilterValue, 20, 39, 0, // Skip to: 3025 -/* 2986 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 2989 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3007 -/* 2993 */ MCD_OPC_CheckPredicate, 5, 233, 41, // Skip to: 13726 -/* 2997 */ MCD_OPC_CheckField, 16, 5, 0, 227, 41, // Skip to: 13726 -/* 3003 */ MCD_OPC_Decode, 228, 3, 94, // Opcode: CVT_S_W -/* 3007 */ MCD_OPC_FilterValue, 33, 219, 41, // Skip to: 13726 -/* 3011 */ MCD_OPC_CheckPredicate, 21, 215, 41, // Skip to: 13726 -/* 3015 */ MCD_OPC_CheckField, 16, 5, 0, 209, 41, // Skip to: 13726 -/* 3021 */ MCD_OPC_Decode, 214, 3, 97, // Opcode: CVT_D32_W -/* 3025 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 3037 -/* 3029 */ MCD_OPC_CheckPredicate, 8, 197, 41, // Skip to: 13726 -/* 3033 */ MCD_OPC_Decode, 189, 2, 92, // Opcode: BZ_B -/* 3037 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 3049 -/* 3041 */ MCD_OPC_CheckPredicate, 8, 185, 41, // Skip to: 13726 -/* 3045 */ MCD_OPC_Decode, 191, 2, 107, // Opcode: BZ_H -/* 3049 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 3061 -/* 3053 */ MCD_OPC_CheckPredicate, 8, 173, 41, // Skip to: 13726 -/* 3057 */ MCD_OPC_Decode, 193, 2, 108, // Opcode: BZ_W -/* 3061 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 3073 -/* 3065 */ MCD_OPC_CheckPredicate, 8, 161, 41, // Skip to: 13726 -/* 3069 */ MCD_OPC_Decode, 190, 2, 109, // Opcode: BZ_D -/* 3073 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 3085 -/* 3077 */ MCD_OPC_CheckPredicate, 8, 149, 41, // Skip to: 13726 -/* 3081 */ MCD_OPC_Decode, 163, 2, 92, // Opcode: BNZ_B -/* 3085 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 3097 -/* 3089 */ MCD_OPC_CheckPredicate, 8, 137, 41, // Skip to: 13726 -/* 3093 */ MCD_OPC_Decode, 165, 2, 107, // Opcode: BNZ_H -/* 3097 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 3109 -/* 3101 */ MCD_OPC_CheckPredicate, 8, 125, 41, // Skip to: 13726 -/* 3105 */ MCD_OPC_Decode, 167, 2, 108, // Opcode: BNZ_W -/* 3109 */ MCD_OPC_FilterValue, 31, 117, 41, // Skip to: 13726 -/* 3113 */ MCD_OPC_CheckPredicate, 8, 113, 41, // Skip to: 13726 -/* 3117 */ MCD_OPC_Decode, 164, 2, 109, // Opcode: BNZ_D -/* 3121 */ MCD_OPC_FilterValue, 18, 94, 0, // Skip to: 3219 -/* 3125 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 3128 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3146 -/* 3132 */ MCD_OPC_CheckPredicate, 5, 94, 41, // Skip to: 13726 -/* 3136 */ MCD_OPC_CheckField, 3, 8, 0, 88, 41, // Skip to: 13726 -/* 3142 */ MCD_OPC_Decode, 182, 8, 81, // Opcode: MFC2 -/* 3146 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 3164 -/* 3150 */ MCD_OPC_CheckPredicate, 5, 76, 41, // Skip to: 13726 -/* 3154 */ MCD_OPC_CheckField, 3, 8, 0, 70, 41, // Skip to: 13726 -/* 3160 */ MCD_OPC_Decode, 172, 9, 81, // Opcode: MTC2 -/* 3164 */ MCD_OPC_FilterValue, 8, 62, 41, // Skip to: 13726 -/* 3168 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 3171 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3183 -/* 3175 */ MCD_OPC_CheckPredicate, 13, 51, 41, // Skip to: 13726 -/* 3179 */ MCD_OPC_Decode, 189, 1, 82, // Opcode: BC2F -/* 3183 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3195 -/* 3187 */ MCD_OPC_CheckPredicate, 13, 39, 41, // Skip to: 13726 -/* 3191 */ MCD_OPC_Decode, 192, 1, 82, // Opcode: BC2T -/* 3195 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3207 -/* 3199 */ MCD_OPC_CheckPredicate, 13, 27, 41, // Skip to: 13726 -/* 3203 */ MCD_OPC_Decode, 190, 1, 82, // Opcode: BC2FL -/* 3207 */ MCD_OPC_FilterValue, 3, 19, 41, // Skip to: 13726 -/* 3211 */ MCD_OPC_CheckPredicate, 13, 15, 41, // Skip to: 13726 -/* 3215 */ MCD_OPC_Decode, 193, 1, 82, // Opcode: BC2TL -/* 3219 */ MCD_OPC_FilterValue, 19, 9, 1, // Skip to: 3488 -/* 3223 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 3226 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 3281 -/* 3230 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 3233 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3245 -/* 3237 */ MCD_OPC_CheckPredicate, 13, 40, 0, // Skip to: 3281 -/* 3241 */ MCD_OPC_Decode, 194, 1, 82, // Opcode: BC3F -/* 3245 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3257 -/* 3249 */ MCD_OPC_CheckPredicate, 13, 28, 0, // Skip to: 3281 -/* 3253 */ MCD_OPC_Decode, 196, 1, 82, // Opcode: BC3T -/* 3257 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3269 -/* 3261 */ MCD_OPC_CheckPredicate, 13, 16, 0, // Skip to: 3281 -/* 3265 */ MCD_OPC_Decode, 195, 1, 82, // Opcode: BC3FL -/* 3269 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 3281 -/* 3273 */ MCD_OPC_CheckPredicate, 13, 4, 0, // Skip to: 3281 -/* 3277 */ MCD_OPC_Decode, 197, 1, 82, // Opcode: BC3TL -/* 3281 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 3284 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3302 -/* 3288 */ MCD_OPC_CheckPredicate, 26, 194, 40, // Skip to: 13726 -/* 3292 */ MCD_OPC_CheckField, 11, 5, 0, 188, 40, // Skip to: 13726 -/* 3298 */ MCD_OPC_Decode, 237, 7, 110, // Opcode: LWXC1 -/* 3302 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 3320 -/* 3306 */ MCD_OPC_CheckPredicate, 27, 176, 40, // Skip to: 13726 -/* 3310 */ MCD_OPC_CheckField, 11, 5, 0, 170, 40, // Skip to: 13726 -/* 3316 */ MCD_OPC_Decode, 175, 7, 111, // Opcode: LDXC1 -/* 3320 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 3338 -/* 3324 */ MCD_OPC_CheckPredicate, 28, 158, 40, // Skip to: 13726 -/* 3328 */ MCD_OPC_CheckField, 11, 5, 0, 152, 40, // Skip to: 13726 -/* 3334 */ MCD_OPC_Decode, 207, 7, 111, // Opcode: LUXC1 -/* 3338 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 3356 -/* 3342 */ MCD_OPC_CheckPredicate, 26, 140, 40, // Skip to: 13726 -/* 3346 */ MCD_OPC_CheckField, 6, 5, 0, 134, 40, // Skip to: 13726 -/* 3352 */ MCD_OPC_Decode, 254, 12, 112, // Opcode: SWXC1 -/* 3356 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 3374 -/* 3360 */ MCD_OPC_CheckPredicate, 27, 122, 40, // Skip to: 13726 -/* 3364 */ MCD_OPC_CheckField, 6, 5, 0, 116, 40, // Skip to: 13726 -/* 3370 */ MCD_OPC_Decode, 166, 11, 113, // Opcode: SDXC1 -/* 3374 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 3392 -/* 3378 */ MCD_OPC_CheckPredicate, 28, 104, 40, // Skip to: 13726 -/* 3382 */ MCD_OPC_CheckField, 6, 5, 0, 98, 40, // Skip to: 13726 -/* 3388 */ MCD_OPC_Decode, 232, 12, 113, // Opcode: SUXC1 -/* 3392 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 3404 -/* 3396 */ MCD_OPC_CheckPredicate, 26, 86, 40, // Skip to: 13726 -/* 3400 */ MCD_OPC_Decode, 149, 8, 114, // Opcode: MADD_S -/* 3404 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 3416 -/* 3408 */ MCD_OPC_CheckPredicate, 29, 74, 40, // Skip to: 13726 -/* 3412 */ MCD_OPC_Decode, 142, 8, 115, // Opcode: MADD_D32 -/* 3416 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 3428 -/* 3420 */ MCD_OPC_CheckPredicate, 26, 62, 40, // Skip to: 13726 -/* 3424 */ MCD_OPC_Decode, 167, 9, 114, // Opcode: MSUB_S -/* 3428 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 3440 -/* 3432 */ MCD_OPC_CheckPredicate, 29, 50, 40, // Skip to: 13726 -/* 3436 */ MCD_OPC_Decode, 160, 9, 115, // Opcode: MSUB_D32 -/* 3440 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 3452 -/* 3444 */ MCD_OPC_CheckPredicate, 26, 38, 40, // Skip to: 13726 -/* 3448 */ MCD_OPC_Decode, 242, 9, 114, // Opcode: NMADD_S -/* 3452 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 3464 -/* 3456 */ MCD_OPC_CheckPredicate, 29, 26, 40, // Skip to: 13726 -/* 3460 */ MCD_OPC_Decode, 239, 9, 115, // Opcode: NMADD_D32 -/* 3464 */ MCD_OPC_FilterValue, 56, 8, 0, // Skip to: 3476 -/* 3468 */ MCD_OPC_CheckPredicate, 26, 14, 40, // Skip to: 13726 -/* 3472 */ MCD_OPC_Decode, 247, 9, 114, // Opcode: NMSUB_S -/* 3476 */ MCD_OPC_FilterValue, 57, 6, 40, // Skip to: 13726 -/* 3480 */ MCD_OPC_CheckPredicate, 29, 2, 40, // Skip to: 13726 -/* 3484 */ MCD_OPC_Decode, 244, 9, 115, // Opcode: NMSUB_D32 -/* 3488 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 3500 -/* 3492 */ MCD_OPC_CheckPredicate, 16, 246, 39, // Skip to: 13726 -/* 3496 */ MCD_OPC_Decode, 209, 1, 78, // Opcode: BEQL -/* 3500 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 3512 -/* 3504 */ MCD_OPC_CheckPredicate, 16, 234, 39, // Skip to: 13726 -/* 3508 */ MCD_OPC_Decode, 156, 2, 78, // Opcode: BNEL -/* 3512 */ MCD_OPC_FilterValue, 22, 14, 0, // Skip to: 3530 -/* 3516 */ MCD_OPC_CheckPredicate, 16, 222, 39, // Skip to: 13726 -/* 3520 */ MCD_OPC_CheckField, 16, 5, 0, 216, 39, // Skip to: 13726 -/* 3526 */ MCD_OPC_Decode, 255, 1, 73, // Opcode: BLEZL -/* 3530 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 3548 -/* 3534 */ MCD_OPC_CheckPredicate, 16, 204, 39, // Skip to: 13726 -/* 3538 */ MCD_OPC_CheckField, 16, 5, 0, 198, 39, // Skip to: 13726 -/* 3544 */ MCD_OPC_Decode, 231, 1, 73, // Opcode: BGTZL -/* 3548 */ MCD_OPC_FilterValue, 28, 229, 0, // Skip to: 3781 -/* 3552 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 3555 */ MCD_OPC_FilterValue, 0, 36, 0, // Skip to: 3595 -/* 3559 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 3562 */ MCD_OPC_FilterValue, 0, 176, 39, // Skip to: 13726 -/* 3566 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 3569 */ MCD_OPC_FilterValue, 0, 169, 39, // Skip to: 13726 -/* 3573 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3587 -/* 3577 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3587 -/* 3583 */ MCD_OPC_Decode, 130, 8, 43, // Opcode: MADD -/* 3587 */ MCD_OPC_CheckPredicate, 12, 151, 39, // Skip to: 13726 -/* 3591 */ MCD_OPC_Decode, 145, 8, 116, // Opcode: MADD_DSP -/* 3595 */ MCD_OPC_FilterValue, 1, 36, 0, // Skip to: 3635 -/* 3599 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 3602 */ MCD_OPC_FilterValue, 0, 136, 39, // Skip to: 13726 -/* 3606 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 3609 */ MCD_OPC_FilterValue, 0, 129, 39, // Skip to: 13726 -/* 3613 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3627 -/* 3617 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3627 -/* 3623 */ MCD_OPC_Decode, 135, 8, 43, // Opcode: MADDU -/* 3627 */ MCD_OPC_CheckPredicate, 12, 111, 39, // Skip to: 13726 -/* 3631 */ MCD_OPC_Decode, 136, 8, 116, // Opcode: MADDU_DSP -/* 3635 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 3653 -/* 3639 */ MCD_OPC_CheckPredicate, 9, 99, 39, // Skip to: 13726 -/* 3643 */ MCD_OPC_CheckField, 6, 5, 0, 93, 39, // Skip to: 13726 -/* 3649 */ MCD_OPC_Decode, 193, 9, 35, // Opcode: MUL -/* 3653 */ MCD_OPC_FilterValue, 4, 36, 0, // Skip to: 3693 -/* 3657 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 3660 */ MCD_OPC_FilterValue, 0, 78, 39, // Skip to: 13726 -/* 3664 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 3667 */ MCD_OPC_FilterValue, 0, 71, 39, // Skip to: 13726 -/* 3671 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3685 -/* 3675 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3685 -/* 3681 */ MCD_OPC_Decode, 148, 9, 43, // Opcode: MSUB -/* 3685 */ MCD_OPC_CheckPredicate, 12, 53, 39, // Skip to: 13726 -/* 3689 */ MCD_OPC_Decode, 163, 9, 116, // Opcode: MSUB_DSP -/* 3693 */ MCD_OPC_FilterValue, 5, 36, 0, // Skip to: 3733 -/* 3697 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 3700 */ MCD_OPC_FilterValue, 0, 38, 39, // Skip to: 13726 -/* 3704 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 3707 */ MCD_OPC_FilterValue, 0, 31, 39, // Skip to: 13726 -/* 3711 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3725 -/* 3715 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3725 -/* 3721 */ MCD_OPC_Decode, 153, 9, 43, // Opcode: MSUBU -/* 3725 */ MCD_OPC_CheckPredicate, 12, 13, 39, // Skip to: 13726 -/* 3729 */ MCD_OPC_Decode, 154, 9, 116, // Opcode: MSUBU_DSP -/* 3733 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3751 -/* 3737 */ MCD_OPC_CheckPredicate, 9, 1, 39, // Skip to: 13726 -/* 3741 */ MCD_OPC_CheckField, 6, 5, 0, 251, 38, // Skip to: 13726 -/* 3747 */ MCD_OPC_Decode, 152, 3, 117, // Opcode: CLZ -/* 3751 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 3769 -/* 3755 */ MCD_OPC_CheckPredicate, 9, 239, 38, // Skip to: 13726 -/* 3759 */ MCD_OPC_CheckField, 6, 5, 0, 233, 38, // Skip to: 13726 -/* 3765 */ MCD_OPC_Decode, 133, 3, 117, // Opcode: CLO -/* 3769 */ MCD_OPC_FilterValue, 63, 225, 38, // Skip to: 13726 -/* 3773 */ MCD_OPC_CheckPredicate, 9, 221, 38, // Skip to: 13726 -/* 3777 */ MCD_OPC_Decode, 152, 11, 64, // Opcode: SDBBP -/* 3781 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 3793 -/* 3785 */ MCD_OPC_CheckPredicate, 9, 209, 38, // Skip to: 13726 -/* 3789 */ MCD_OPC_Decode, 131, 7, 77, // Opcode: JALX -/* 3793 */ MCD_OPC_FilterValue, 30, 28, 28, // Skip to: 10993 -/* 3797 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 3800 */ MCD_OPC_FilterValue, 0, 50, 0, // Skip to: 3854 -/* 3804 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 3807 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3818 -/* 3811 */ MCD_OPC_CheckPredicate, 8, 183, 38, // Skip to: 13726 -/* 3815 */ MCD_OPC_Decode, 87, 118, // Opcode: ANDI_B -/* 3818 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3830 -/* 3822 */ MCD_OPC_CheckPredicate, 8, 172, 38, // Skip to: 13726 -/* 3826 */ MCD_OPC_Decode, 136, 10, 118, // Opcode: ORI_B -/* 3830 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3842 -/* 3834 */ MCD_OPC_CheckPredicate, 8, 160, 38, // Skip to: 13726 -/* 3838 */ MCD_OPC_Decode, 252, 9, 118, // Opcode: NORI_B -/* 3842 */ MCD_OPC_FilterValue, 3, 152, 38, // Skip to: 13726 -/* 3846 */ MCD_OPC_CheckPredicate, 8, 148, 38, // Skip to: 13726 -/* 3850 */ MCD_OPC_Decode, 239, 13, 118, // Opcode: XORI_B -/* 3854 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 3897 -/* 3858 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 3861 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3873 -/* 3865 */ MCD_OPC_CheckPredicate, 8, 129, 38, // Skip to: 13726 -/* 3869 */ MCD_OPC_Decode, 141, 2, 119, // Opcode: BMNZI_B -/* 3873 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3885 -/* 3877 */ MCD_OPC_CheckPredicate, 8, 117, 38, // Skip to: 13726 -/* 3881 */ MCD_OPC_Decode, 143, 2, 119, // Opcode: BMZI_B -/* 3885 */ MCD_OPC_FilterValue, 2, 109, 38, // Skip to: 13726 -/* 3889 */ MCD_OPC_CheckPredicate, 8, 105, 38, // Skip to: 13726 -/* 3893 */ MCD_OPC_Decode, 174, 2, 119, // Opcode: BSELI_B -/* 3897 */ MCD_OPC_FilterValue, 2, 39, 0, // Skip to: 3940 -/* 3901 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 3904 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3916 -/* 3908 */ MCD_OPC_CheckPredicate, 8, 86, 38, // Skip to: 13726 -/* 3912 */ MCD_OPC_Decode, 189, 11, 118, // Opcode: SHF_B -/* 3916 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3928 -/* 3920 */ MCD_OPC_CheckPredicate, 8, 74, 38, // Skip to: 13726 -/* 3924 */ MCD_OPC_Decode, 190, 11, 120, // Opcode: SHF_H -/* 3928 */ MCD_OPC_FilterValue, 2, 66, 38, // Skip to: 13726 -/* 3932 */ MCD_OPC_CheckPredicate, 8, 62, 38, // Skip to: 13726 -/* 3936 */ MCD_OPC_Decode, 191, 11, 121, // Opcode: SHF_W -/* 3940 */ MCD_OPC_FilterValue, 6, 31, 1, // Skip to: 4231 -/* 3944 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 3947 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3958 -/* 3951 */ MCD_OPC_CheckPredicate, 8, 43, 38, // Skip to: 13726 -/* 3955 */ MCD_OPC_Decode, 59, 122, // Opcode: ADDVI_B -/* 3958 */ MCD_OPC_FilterValue, 1, 7, 0, // Skip to: 3969 -/* 3962 */ MCD_OPC_CheckPredicate, 8, 32, 38, // Skip to: 13726 -/* 3966 */ MCD_OPC_Decode, 61, 123, // Opcode: ADDVI_H -/* 3969 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 3980 -/* 3973 */ MCD_OPC_CheckPredicate, 8, 21, 38, // Skip to: 13726 -/* 3977 */ MCD_OPC_Decode, 62, 124, // Opcode: ADDVI_W -/* 3980 */ MCD_OPC_FilterValue, 3, 7, 0, // Skip to: 3991 -/* 3984 */ MCD_OPC_CheckPredicate, 8, 10, 38, // Skip to: 13726 -/* 3988 */ MCD_OPC_Decode, 60, 125, // Opcode: ADDVI_D -/* 3991 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 4003 -/* 3995 */ MCD_OPC_CheckPredicate, 8, 255, 37, // Skip to: 13726 -/* 3999 */ MCD_OPC_Decode, 221, 12, 122, // Opcode: SUBVI_B -/* 4003 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 4015 -/* 4007 */ MCD_OPC_CheckPredicate, 8, 243, 37, // Skip to: 13726 -/* 4011 */ MCD_OPC_Decode, 223, 12, 123, // Opcode: SUBVI_H -/* 4015 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 4027 -/* 4019 */ MCD_OPC_CheckPredicate, 8, 231, 37, // Skip to: 13726 -/* 4023 */ MCD_OPC_Decode, 224, 12, 124, // Opcode: SUBVI_W -/* 4027 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 4039 -/* 4031 */ MCD_OPC_CheckPredicate, 8, 219, 37, // Skip to: 13726 -/* 4035 */ MCD_OPC_Decode, 222, 12, 125, // Opcode: SUBVI_D -/* 4039 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 4051 -/* 4043 */ MCD_OPC_CheckPredicate, 8, 207, 37, // Skip to: 13726 -/* 4047 */ MCD_OPC_Decode, 157, 8, 122, // Opcode: MAXI_S_B -/* 4051 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 4063 -/* 4055 */ MCD_OPC_CheckPredicate, 8, 195, 37, // Skip to: 13726 -/* 4059 */ MCD_OPC_Decode, 159, 8, 123, // Opcode: MAXI_S_H -/* 4063 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 4075 -/* 4067 */ MCD_OPC_CheckPredicate, 8, 183, 37, // Skip to: 13726 -/* 4071 */ MCD_OPC_Decode, 160, 8, 124, // Opcode: MAXI_S_W -/* 4075 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 4087 -/* 4079 */ MCD_OPC_CheckPredicate, 8, 171, 37, // Skip to: 13726 -/* 4083 */ MCD_OPC_Decode, 158, 8, 125, // Opcode: MAXI_S_D -/* 4087 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 4099 -/* 4091 */ MCD_OPC_CheckPredicate, 8, 159, 37, // Skip to: 13726 -/* 4095 */ MCD_OPC_Decode, 161, 8, 122, // Opcode: MAXI_U_B -/* 4099 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 4111 -/* 4103 */ MCD_OPC_CheckPredicate, 8, 147, 37, // Skip to: 13726 -/* 4107 */ MCD_OPC_Decode, 163, 8, 123, // Opcode: MAXI_U_H -/* 4111 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 4123 -/* 4115 */ MCD_OPC_CheckPredicate, 8, 135, 37, // Skip to: 13726 -/* 4119 */ MCD_OPC_Decode, 164, 8, 124, // Opcode: MAXI_U_W -/* 4123 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 4135 -/* 4127 */ MCD_OPC_CheckPredicate, 8, 123, 37, // Skip to: 13726 -/* 4131 */ MCD_OPC_Decode, 162, 8, 125, // Opcode: MAXI_U_D -/* 4135 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 4147 -/* 4139 */ MCD_OPC_CheckPredicate, 8, 111, 37, // Skip to: 13726 -/* 4143 */ MCD_OPC_Decode, 198, 8, 122, // Opcode: MINI_S_B -/* 4147 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 4159 -/* 4151 */ MCD_OPC_CheckPredicate, 8, 99, 37, // Skip to: 13726 -/* 4155 */ MCD_OPC_Decode, 200, 8, 123, // Opcode: MINI_S_H -/* 4159 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 4171 -/* 4163 */ MCD_OPC_CheckPredicate, 8, 87, 37, // Skip to: 13726 -/* 4167 */ MCD_OPC_Decode, 201, 8, 124, // Opcode: MINI_S_W -/* 4171 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 4183 -/* 4175 */ MCD_OPC_CheckPredicate, 8, 75, 37, // Skip to: 13726 -/* 4179 */ MCD_OPC_Decode, 199, 8, 125, // Opcode: MINI_S_D -/* 4183 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 4195 -/* 4187 */ MCD_OPC_CheckPredicate, 8, 63, 37, // Skip to: 13726 -/* 4191 */ MCD_OPC_Decode, 202, 8, 122, // Opcode: MINI_U_B -/* 4195 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 4207 -/* 4199 */ MCD_OPC_CheckPredicate, 8, 51, 37, // Skip to: 13726 -/* 4203 */ MCD_OPC_Decode, 204, 8, 123, // Opcode: MINI_U_H -/* 4207 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 4219 -/* 4211 */ MCD_OPC_CheckPredicate, 8, 39, 37, // Skip to: 13726 -/* 4215 */ MCD_OPC_Decode, 205, 8, 124, // Opcode: MINI_U_W -/* 4219 */ MCD_OPC_FilterValue, 23, 31, 37, // Skip to: 13726 -/* 4223 */ MCD_OPC_CheckPredicate, 8, 27, 37, // Skip to: 13726 -/* 4227 */ MCD_OPC_Decode, 203, 8, 125, // Opcode: MINI_U_D -/* 4231 */ MCD_OPC_FilterValue, 7, 37, 1, // Skip to: 4528 -/* 4235 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 4238 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4250 -/* 4242 */ MCD_OPC_CheckPredicate, 8, 8, 37, // Skip to: 13726 -/* 4246 */ MCD_OPC_Decode, 230, 2, 122, // Opcode: CEQI_B -/* 4250 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 4262 -/* 4254 */ MCD_OPC_CheckPredicate, 8, 252, 36, // Skip to: 13726 -/* 4258 */ MCD_OPC_Decode, 232, 2, 123, // Opcode: CEQI_H -/* 4262 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 4274 -/* 4266 */ MCD_OPC_CheckPredicate, 8, 240, 36, // Skip to: 13726 -/* 4270 */ MCD_OPC_Decode, 233, 2, 124, // Opcode: CEQI_W -/* 4274 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 4286 -/* 4278 */ MCD_OPC_CheckPredicate, 8, 228, 36, // Skip to: 13726 -/* 4282 */ MCD_OPC_Decode, 231, 2, 125, // Opcode: CEQI_D -/* 4286 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 4298 -/* 4290 */ MCD_OPC_CheckPredicate, 8, 216, 36, // Skip to: 13726 -/* 4294 */ MCD_OPC_Decode, 136, 3, 122, // Opcode: CLTI_S_B -/* 4298 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 4310 -/* 4302 */ MCD_OPC_CheckPredicate, 8, 204, 36, // Skip to: 13726 -/* 4306 */ MCD_OPC_Decode, 138, 3, 123, // Opcode: CLTI_S_H -/* 4310 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 4322 -/* 4314 */ MCD_OPC_CheckPredicate, 8, 192, 36, // Skip to: 13726 -/* 4318 */ MCD_OPC_Decode, 139, 3, 124, // Opcode: CLTI_S_W -/* 4322 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 4334 -/* 4326 */ MCD_OPC_CheckPredicate, 8, 180, 36, // Skip to: 13726 -/* 4330 */ MCD_OPC_Decode, 137, 3, 125, // Opcode: CLTI_S_D -/* 4334 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 4346 -/* 4338 */ MCD_OPC_CheckPredicate, 8, 168, 36, // Skip to: 13726 -/* 4342 */ MCD_OPC_Decode, 140, 3, 122, // Opcode: CLTI_U_B -/* 4346 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 4358 -/* 4350 */ MCD_OPC_CheckPredicate, 8, 156, 36, // Skip to: 13726 -/* 4354 */ MCD_OPC_Decode, 142, 3, 123, // Opcode: CLTI_U_H -/* 4358 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 4370 -/* 4362 */ MCD_OPC_CheckPredicate, 8, 144, 36, // Skip to: 13726 -/* 4366 */ MCD_OPC_Decode, 143, 3, 124, // Opcode: CLTI_U_W -/* 4370 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 4382 -/* 4374 */ MCD_OPC_CheckPredicate, 8, 132, 36, // Skip to: 13726 -/* 4378 */ MCD_OPC_Decode, 141, 3, 125, // Opcode: CLTI_U_D -/* 4382 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 4394 -/* 4386 */ MCD_OPC_CheckPredicate, 8, 120, 36, // Skip to: 13726 -/* 4390 */ MCD_OPC_Decode, 245, 2, 122, // Opcode: CLEI_S_B -/* 4394 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 4406 -/* 4398 */ MCD_OPC_CheckPredicate, 8, 108, 36, // Skip to: 13726 -/* 4402 */ MCD_OPC_Decode, 247, 2, 123, // Opcode: CLEI_S_H -/* 4406 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 4418 -/* 4410 */ MCD_OPC_CheckPredicate, 8, 96, 36, // Skip to: 13726 -/* 4414 */ MCD_OPC_Decode, 248, 2, 124, // Opcode: CLEI_S_W -/* 4418 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 4430 -/* 4422 */ MCD_OPC_CheckPredicate, 8, 84, 36, // Skip to: 13726 -/* 4426 */ MCD_OPC_Decode, 246, 2, 125, // Opcode: CLEI_S_D -/* 4430 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 4442 -/* 4434 */ MCD_OPC_CheckPredicate, 8, 72, 36, // Skip to: 13726 -/* 4438 */ MCD_OPC_Decode, 249, 2, 122, // Opcode: CLEI_U_B -/* 4442 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 4454 -/* 4446 */ MCD_OPC_CheckPredicate, 8, 60, 36, // Skip to: 13726 -/* 4450 */ MCD_OPC_Decode, 251, 2, 123, // Opcode: CLEI_U_H -/* 4454 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 4466 -/* 4458 */ MCD_OPC_CheckPredicate, 8, 48, 36, // Skip to: 13726 -/* 4462 */ MCD_OPC_Decode, 252, 2, 124, // Opcode: CLEI_U_W -/* 4466 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 4478 -/* 4470 */ MCD_OPC_CheckPredicate, 8, 36, 36, // Skip to: 13726 -/* 4474 */ MCD_OPC_Decode, 250, 2, 125, // Opcode: CLEI_U_D -/* 4478 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 4490 -/* 4482 */ MCD_OPC_CheckPredicate, 8, 24, 36, // Skip to: 13726 -/* 4486 */ MCD_OPC_Decode, 168, 7, 126, // Opcode: LDI_B -/* 4490 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 4502 -/* 4494 */ MCD_OPC_CheckPredicate, 8, 12, 36, // Skip to: 13726 -/* 4498 */ MCD_OPC_Decode, 170, 7, 127, // Opcode: LDI_H -/* 4502 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 4515 -/* 4506 */ MCD_OPC_CheckPredicate, 8, 0, 36, // Skip to: 13726 -/* 4510 */ MCD_OPC_Decode, 171, 7, 128, 1, // Opcode: LDI_W -/* 4515 */ MCD_OPC_FilterValue, 27, 247, 35, // Skip to: 13726 -/* 4519 */ MCD_OPC_CheckPredicate, 8, 243, 35, // Skip to: 13726 -/* 4523 */ MCD_OPC_Decode, 169, 7, 129, 1, // Opcode: LDI_D -/* 4528 */ MCD_OPC_FilterValue, 9, 61, 2, // Skip to: 5105 -/* 4532 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 4535 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4548 -/* 4539 */ MCD_OPC_CheckPredicate, 8, 223, 35, // Skip to: 13726 -/* 4543 */ MCD_OPC_Decode, 230, 11, 130, 1, // Opcode: SLLI_D -/* 4548 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 4606 -/* 4552 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4555 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4567 -/* 4559 */ MCD_OPC_CheckPredicate, 8, 203, 35, // Skip to: 13726 -/* 4563 */ MCD_OPC_Decode, 232, 11, 124, // Opcode: SLLI_W -/* 4567 */ MCD_OPC_FilterValue, 1, 195, 35, // Skip to: 13726 -/* 4571 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4574 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4587 -/* 4578 */ MCD_OPC_CheckPredicate, 8, 184, 35, // Skip to: 13726 -/* 4582 */ MCD_OPC_Decode, 231, 11, 131, 1, // Opcode: SLLI_H -/* 4587 */ MCD_OPC_FilterValue, 1, 175, 35, // Skip to: 13726 -/* 4591 */ MCD_OPC_CheckPredicate, 8, 171, 35, // Skip to: 13726 -/* 4595 */ MCD_OPC_CheckField, 19, 1, 0, 165, 35, // Skip to: 13726 -/* 4601 */ MCD_OPC_Decode, 229, 11, 132, 1, // Opcode: SLLI_B -/* 4606 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4619 -/* 4610 */ MCD_OPC_CheckPredicate, 8, 152, 35, // Skip to: 13726 -/* 4614 */ MCD_OPC_Decode, 141, 12, 130, 1, // Opcode: SRAI_D -/* 4619 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 4677 -/* 4623 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4626 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4638 -/* 4630 */ MCD_OPC_CheckPredicate, 8, 132, 35, // Skip to: 13726 -/* 4634 */ MCD_OPC_Decode, 143, 12, 124, // Opcode: SRAI_W -/* 4638 */ MCD_OPC_FilterValue, 1, 124, 35, // Skip to: 13726 -/* 4642 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4645 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4658 -/* 4649 */ MCD_OPC_CheckPredicate, 8, 113, 35, // Skip to: 13726 -/* 4653 */ MCD_OPC_Decode, 142, 12, 131, 1, // Opcode: SRAI_H -/* 4658 */ MCD_OPC_FilterValue, 1, 104, 35, // Skip to: 13726 -/* 4662 */ MCD_OPC_CheckPredicate, 8, 100, 35, // Skip to: 13726 -/* 4666 */ MCD_OPC_CheckField, 19, 1, 0, 94, 35, // Skip to: 13726 -/* 4672 */ MCD_OPC_Decode, 140, 12, 132, 1, // Opcode: SRAI_B -/* 4677 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 4690 -/* 4681 */ MCD_OPC_CheckPredicate, 8, 81, 35, // Skip to: 13726 -/* 4685 */ MCD_OPC_Decode, 162, 12, 130, 1, // Opcode: SRLI_D -/* 4690 */ MCD_OPC_FilterValue, 5, 54, 0, // Skip to: 4748 -/* 4694 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4697 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4709 -/* 4701 */ MCD_OPC_CheckPredicate, 8, 61, 35, // Skip to: 13726 -/* 4705 */ MCD_OPC_Decode, 164, 12, 124, // Opcode: SRLI_W -/* 4709 */ MCD_OPC_FilterValue, 1, 53, 35, // Skip to: 13726 -/* 4713 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4716 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4729 -/* 4720 */ MCD_OPC_CheckPredicate, 8, 42, 35, // Skip to: 13726 -/* 4724 */ MCD_OPC_Decode, 163, 12, 131, 1, // Opcode: SRLI_H -/* 4729 */ MCD_OPC_FilterValue, 1, 33, 35, // Skip to: 13726 -/* 4733 */ MCD_OPC_CheckPredicate, 8, 29, 35, // Skip to: 13726 -/* 4737 */ MCD_OPC_CheckField, 19, 1, 0, 23, 35, // Skip to: 13726 -/* 4743 */ MCD_OPC_Decode, 161, 12, 132, 1, // Opcode: SRLI_B -/* 4748 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 4761 -/* 4752 */ MCD_OPC_CheckPredicate, 8, 10, 35, // Skip to: 13726 -/* 4756 */ MCD_OPC_Decode, 199, 1, 130, 1, // Opcode: BCLRI_D -/* 4761 */ MCD_OPC_FilterValue, 7, 54, 0, // Skip to: 4819 -/* 4765 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4768 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4780 -/* 4772 */ MCD_OPC_CheckPredicate, 8, 246, 34, // Skip to: 13726 -/* 4776 */ MCD_OPC_Decode, 201, 1, 124, // Opcode: BCLRI_W -/* 4780 */ MCD_OPC_FilterValue, 1, 238, 34, // Skip to: 13726 -/* 4784 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4787 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4800 -/* 4791 */ MCD_OPC_CheckPredicate, 8, 227, 34, // Skip to: 13726 -/* 4795 */ MCD_OPC_Decode, 200, 1, 131, 1, // Opcode: BCLRI_H -/* 4800 */ MCD_OPC_FilterValue, 1, 218, 34, // Skip to: 13726 -/* 4804 */ MCD_OPC_CheckPredicate, 8, 214, 34, // Skip to: 13726 -/* 4808 */ MCD_OPC_CheckField, 19, 1, 0, 208, 34, // Skip to: 13726 -/* 4814 */ MCD_OPC_Decode, 198, 1, 132, 1, // Opcode: BCLRI_B -/* 4819 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 4832 -/* 4823 */ MCD_OPC_CheckPredicate, 8, 195, 34, // Skip to: 13726 -/* 4827 */ MCD_OPC_Decode, 182, 2, 130, 1, // Opcode: BSETI_D -/* 4832 */ MCD_OPC_FilterValue, 9, 54, 0, // Skip to: 4890 -/* 4836 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4839 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4851 -/* 4843 */ MCD_OPC_CheckPredicate, 8, 175, 34, // Skip to: 13726 -/* 4847 */ MCD_OPC_Decode, 184, 2, 124, // Opcode: BSETI_W -/* 4851 */ MCD_OPC_FilterValue, 1, 167, 34, // Skip to: 13726 -/* 4855 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4858 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4871 -/* 4862 */ MCD_OPC_CheckPredicate, 8, 156, 34, // Skip to: 13726 -/* 4866 */ MCD_OPC_Decode, 183, 2, 131, 1, // Opcode: BSETI_H -/* 4871 */ MCD_OPC_FilterValue, 1, 147, 34, // Skip to: 13726 -/* 4875 */ MCD_OPC_CheckPredicate, 8, 143, 34, // Skip to: 13726 -/* 4879 */ MCD_OPC_CheckField, 19, 1, 0, 137, 34, // Skip to: 13726 -/* 4885 */ MCD_OPC_Decode, 181, 2, 132, 1, // Opcode: BSETI_B -/* 4890 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 4903 -/* 4894 */ MCD_OPC_CheckPredicate, 8, 124, 34, // Skip to: 13726 -/* 4898 */ MCD_OPC_Decode, 149, 2, 130, 1, // Opcode: BNEGI_D -/* 4903 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 4961 -/* 4907 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4910 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4922 -/* 4914 */ MCD_OPC_CheckPredicate, 8, 104, 34, // Skip to: 13726 -/* 4918 */ MCD_OPC_Decode, 151, 2, 124, // Opcode: BNEGI_W -/* 4922 */ MCD_OPC_FilterValue, 1, 96, 34, // Skip to: 13726 -/* 4926 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4929 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4942 -/* 4933 */ MCD_OPC_CheckPredicate, 8, 85, 34, // Skip to: 13726 -/* 4937 */ MCD_OPC_Decode, 150, 2, 131, 1, // Opcode: BNEGI_H -/* 4942 */ MCD_OPC_FilterValue, 1, 76, 34, // Skip to: 13726 -/* 4946 */ MCD_OPC_CheckPredicate, 8, 72, 34, // Skip to: 13726 -/* 4950 */ MCD_OPC_CheckField, 19, 1, 0, 66, 34, // Skip to: 13726 -/* 4956 */ MCD_OPC_Decode, 148, 2, 132, 1, // Opcode: BNEGI_B -/* 4961 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 4974 -/* 4965 */ MCD_OPC_CheckPredicate, 8, 53, 34, // Skip to: 13726 -/* 4969 */ MCD_OPC_Decode, 234, 1, 133, 1, // Opcode: BINSLI_D -/* 4974 */ MCD_OPC_FilterValue, 13, 55, 0, // Skip to: 5033 -/* 4978 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4981 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4994 -/* 4985 */ MCD_OPC_CheckPredicate, 8, 33, 34, // Skip to: 13726 -/* 4989 */ MCD_OPC_Decode, 236, 1, 134, 1, // Opcode: BINSLI_W -/* 4994 */ MCD_OPC_FilterValue, 1, 24, 34, // Skip to: 13726 -/* 4998 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5001 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5014 -/* 5005 */ MCD_OPC_CheckPredicate, 8, 13, 34, // Skip to: 13726 -/* 5009 */ MCD_OPC_Decode, 235, 1, 135, 1, // Opcode: BINSLI_H -/* 5014 */ MCD_OPC_FilterValue, 1, 4, 34, // Skip to: 13726 -/* 5018 */ MCD_OPC_CheckPredicate, 8, 0, 34, // Skip to: 13726 -/* 5022 */ MCD_OPC_CheckField, 19, 1, 0, 250, 33, // Skip to: 13726 -/* 5028 */ MCD_OPC_Decode, 233, 1, 136, 1, // Opcode: BINSLI_B -/* 5033 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 5046 -/* 5037 */ MCD_OPC_CheckPredicate, 8, 237, 33, // Skip to: 13726 -/* 5041 */ MCD_OPC_Decode, 242, 1, 133, 1, // Opcode: BINSRI_D -/* 5046 */ MCD_OPC_FilterValue, 15, 228, 33, // Skip to: 13726 -/* 5050 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5053 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5066 -/* 5057 */ MCD_OPC_CheckPredicate, 8, 217, 33, // Skip to: 13726 -/* 5061 */ MCD_OPC_Decode, 244, 1, 134, 1, // Opcode: BINSRI_W -/* 5066 */ MCD_OPC_FilterValue, 1, 208, 33, // Skip to: 13726 -/* 5070 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5073 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5086 -/* 5077 */ MCD_OPC_CheckPredicate, 8, 197, 33, // Skip to: 13726 -/* 5081 */ MCD_OPC_Decode, 243, 1, 135, 1, // Opcode: BINSRI_H -/* 5086 */ MCD_OPC_FilterValue, 1, 188, 33, // Skip to: 13726 -/* 5090 */ MCD_OPC_CheckPredicate, 8, 184, 33, // Skip to: 13726 -/* 5094 */ MCD_OPC_CheckField, 19, 1, 0, 178, 33, // Skip to: 13726 -/* 5100 */ MCD_OPC_Decode, 241, 1, 136, 1, // Opcode: BINSRI_B -/* 5105 */ MCD_OPC_FilterValue, 10, 31, 1, // Skip to: 5396 -/* 5109 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 5112 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5125 -/* 5116 */ MCD_OPC_CheckPredicate, 8, 158, 33, // Skip to: 13726 -/* 5120 */ MCD_OPC_Decode, 135, 11, 130, 1, // Opcode: SAT_S_D -/* 5125 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 5183 -/* 5129 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5132 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5144 -/* 5136 */ MCD_OPC_CheckPredicate, 8, 138, 33, // Skip to: 13726 -/* 5140 */ MCD_OPC_Decode, 137, 11, 124, // Opcode: SAT_S_W -/* 5144 */ MCD_OPC_FilterValue, 1, 130, 33, // Skip to: 13726 -/* 5148 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5151 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5164 -/* 5155 */ MCD_OPC_CheckPredicate, 8, 119, 33, // Skip to: 13726 -/* 5159 */ MCD_OPC_Decode, 136, 11, 131, 1, // Opcode: SAT_S_H -/* 5164 */ MCD_OPC_FilterValue, 1, 110, 33, // Skip to: 13726 -/* 5168 */ MCD_OPC_CheckPredicate, 8, 106, 33, // Skip to: 13726 -/* 5172 */ MCD_OPC_CheckField, 19, 1, 0, 100, 33, // Skip to: 13726 -/* 5178 */ MCD_OPC_Decode, 134, 11, 132, 1, // Opcode: SAT_S_B -/* 5183 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5196 -/* 5187 */ MCD_OPC_CheckPredicate, 8, 87, 33, // Skip to: 13726 -/* 5191 */ MCD_OPC_Decode, 139, 11, 130, 1, // Opcode: SAT_U_D -/* 5196 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 5254 -/* 5200 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5203 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5215 -/* 5207 */ MCD_OPC_CheckPredicate, 8, 67, 33, // Skip to: 13726 -/* 5211 */ MCD_OPC_Decode, 141, 11, 124, // Opcode: SAT_U_W -/* 5215 */ MCD_OPC_FilterValue, 1, 59, 33, // Skip to: 13726 -/* 5219 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5222 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5235 -/* 5226 */ MCD_OPC_CheckPredicate, 8, 48, 33, // Skip to: 13726 -/* 5230 */ MCD_OPC_Decode, 140, 11, 131, 1, // Opcode: SAT_U_H -/* 5235 */ MCD_OPC_FilterValue, 1, 39, 33, // Skip to: 13726 -/* 5239 */ MCD_OPC_CheckPredicate, 8, 35, 33, // Skip to: 13726 -/* 5243 */ MCD_OPC_CheckField, 19, 1, 0, 29, 33, // Skip to: 13726 -/* 5249 */ MCD_OPC_Decode, 138, 11, 132, 1, // Opcode: SAT_U_B -/* 5254 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5267 -/* 5258 */ MCD_OPC_CheckPredicate, 8, 16, 33, // Skip to: 13726 -/* 5262 */ MCD_OPC_Decode, 145, 12, 130, 1, // Opcode: SRARI_D -/* 5267 */ MCD_OPC_FilterValue, 5, 54, 0, // Skip to: 5325 -/* 5271 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5274 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5286 -/* 5278 */ MCD_OPC_CheckPredicate, 8, 252, 32, // Skip to: 13726 -/* 5282 */ MCD_OPC_Decode, 147, 12, 124, // Opcode: SRARI_W -/* 5286 */ MCD_OPC_FilterValue, 1, 244, 32, // Skip to: 13726 -/* 5290 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5293 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5306 -/* 5297 */ MCD_OPC_CheckPredicate, 8, 233, 32, // Skip to: 13726 -/* 5301 */ MCD_OPC_Decode, 146, 12, 131, 1, // Opcode: SRARI_H -/* 5306 */ MCD_OPC_FilterValue, 1, 224, 32, // Skip to: 13726 -/* 5310 */ MCD_OPC_CheckPredicate, 8, 220, 32, // Skip to: 13726 -/* 5314 */ MCD_OPC_CheckField, 19, 1, 0, 214, 32, // Skip to: 13726 -/* 5320 */ MCD_OPC_Decode, 144, 12, 132, 1, // Opcode: SRARI_B -/* 5325 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5338 -/* 5329 */ MCD_OPC_CheckPredicate, 8, 201, 32, // Skip to: 13726 -/* 5333 */ MCD_OPC_Decode, 166, 12, 130, 1, // Opcode: SRLRI_D -/* 5338 */ MCD_OPC_FilterValue, 7, 192, 32, // Skip to: 13726 -/* 5342 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5345 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5357 -/* 5349 */ MCD_OPC_CheckPredicate, 8, 181, 32, // Skip to: 13726 -/* 5353 */ MCD_OPC_Decode, 168, 12, 124, // Opcode: SRLRI_W -/* 5357 */ MCD_OPC_FilterValue, 1, 173, 32, // Skip to: 13726 -/* 5361 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5364 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5377 -/* 5368 */ MCD_OPC_CheckPredicate, 8, 162, 32, // Skip to: 13726 -/* 5372 */ MCD_OPC_Decode, 167, 12, 131, 1, // Opcode: SRLRI_H -/* 5377 */ MCD_OPC_FilterValue, 1, 153, 32, // Skip to: 13726 -/* 5381 */ MCD_OPC_CheckPredicate, 8, 149, 32, // Skip to: 13726 -/* 5385 */ MCD_OPC_CheckField, 19, 1, 0, 143, 32, // Skip to: 13726 -/* 5391 */ MCD_OPC_Decode, 165, 12, 132, 1, // Opcode: SRLRI_B -/* 5396 */ MCD_OPC_FilterValue, 13, 163, 1, // Skip to: 5819 -/* 5400 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 5403 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5416 -/* 5407 */ MCD_OPC_CheckPredicate, 8, 123, 32, // Skip to: 13726 -/* 5411 */ MCD_OPC_Decode, 235, 11, 137, 1, // Opcode: SLL_B -/* 5416 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5429 -/* 5420 */ MCD_OPC_CheckPredicate, 8, 110, 32, // Skip to: 13726 -/* 5424 */ MCD_OPC_Decode, 237, 11, 138, 1, // Opcode: SLL_H -/* 5429 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5442 -/* 5433 */ MCD_OPC_CheckPredicate, 8, 97, 32, // Skip to: 13726 -/* 5437 */ MCD_OPC_Decode, 239, 11, 139, 1, // Opcode: SLL_W -/* 5442 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5455 -/* 5446 */ MCD_OPC_CheckPredicate, 8, 84, 32, // Skip to: 13726 -/* 5450 */ MCD_OPC_Decode, 236, 11, 140, 1, // Opcode: SLL_D -/* 5455 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5468 -/* 5459 */ MCD_OPC_CheckPredicate, 8, 71, 32, // Skip to: 13726 -/* 5463 */ MCD_OPC_Decode, 154, 12, 137, 1, // Opcode: SRA_B -/* 5468 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 5481 -/* 5472 */ MCD_OPC_CheckPredicate, 8, 58, 32, // Skip to: 13726 -/* 5476 */ MCD_OPC_Decode, 156, 12, 138, 1, // Opcode: SRA_H -/* 5481 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5494 -/* 5485 */ MCD_OPC_CheckPredicate, 8, 45, 32, // Skip to: 13726 -/* 5489 */ MCD_OPC_Decode, 158, 12, 139, 1, // Opcode: SRA_W -/* 5494 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 5507 -/* 5498 */ MCD_OPC_CheckPredicate, 8, 32, 32, // Skip to: 13726 -/* 5502 */ MCD_OPC_Decode, 155, 12, 140, 1, // Opcode: SRA_D -/* 5507 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 5520 -/* 5511 */ MCD_OPC_CheckPredicate, 8, 19, 32, // Skip to: 13726 -/* 5515 */ MCD_OPC_Decode, 175, 12, 137, 1, // Opcode: SRL_B -/* 5520 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 5533 -/* 5524 */ MCD_OPC_CheckPredicate, 8, 6, 32, // Skip to: 13726 -/* 5528 */ MCD_OPC_Decode, 177, 12, 138, 1, // Opcode: SRL_H -/* 5533 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 5546 -/* 5537 */ MCD_OPC_CheckPredicate, 8, 249, 31, // Skip to: 13726 -/* 5541 */ MCD_OPC_Decode, 179, 12, 139, 1, // Opcode: SRL_W -/* 5546 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 5559 -/* 5550 */ MCD_OPC_CheckPredicate, 8, 236, 31, // Skip to: 13726 -/* 5554 */ MCD_OPC_Decode, 176, 12, 140, 1, // Opcode: SRL_D -/* 5559 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 5572 -/* 5563 */ MCD_OPC_CheckPredicate, 8, 223, 31, // Skip to: 13726 -/* 5567 */ MCD_OPC_Decode, 202, 1, 137, 1, // Opcode: BCLR_B -/* 5572 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5585 -/* 5576 */ MCD_OPC_CheckPredicate, 8, 210, 31, // Skip to: 13726 -/* 5580 */ MCD_OPC_Decode, 204, 1, 138, 1, // Opcode: BCLR_H -/* 5585 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 5598 -/* 5589 */ MCD_OPC_CheckPredicate, 8, 197, 31, // Skip to: 13726 -/* 5593 */ MCD_OPC_Decode, 205, 1, 139, 1, // Opcode: BCLR_W -/* 5598 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5611 -/* 5602 */ MCD_OPC_CheckPredicate, 8, 184, 31, // Skip to: 13726 -/* 5606 */ MCD_OPC_Decode, 203, 1, 140, 1, // Opcode: BCLR_D -/* 5611 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 5624 -/* 5615 */ MCD_OPC_CheckPredicate, 8, 171, 31, // Skip to: 13726 -/* 5619 */ MCD_OPC_Decode, 185, 2, 137, 1, // Opcode: BSET_B -/* 5624 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 5637 -/* 5628 */ MCD_OPC_CheckPredicate, 8, 158, 31, // Skip to: 13726 -/* 5632 */ MCD_OPC_Decode, 187, 2, 138, 1, // Opcode: BSET_H -/* 5637 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 5650 -/* 5641 */ MCD_OPC_CheckPredicate, 8, 145, 31, // Skip to: 13726 -/* 5645 */ MCD_OPC_Decode, 188, 2, 139, 1, // Opcode: BSET_W -/* 5650 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 5663 -/* 5654 */ MCD_OPC_CheckPredicate, 8, 132, 31, // Skip to: 13726 -/* 5658 */ MCD_OPC_Decode, 186, 2, 140, 1, // Opcode: BSET_D -/* 5663 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 5676 -/* 5667 */ MCD_OPC_CheckPredicate, 8, 119, 31, // Skip to: 13726 -/* 5671 */ MCD_OPC_Decode, 152, 2, 137, 1, // Opcode: BNEG_B -/* 5676 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 5689 -/* 5680 */ MCD_OPC_CheckPredicate, 8, 106, 31, // Skip to: 13726 -/* 5684 */ MCD_OPC_Decode, 154, 2, 138, 1, // Opcode: BNEG_H -/* 5689 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 5702 -/* 5693 */ MCD_OPC_CheckPredicate, 8, 93, 31, // Skip to: 13726 -/* 5697 */ MCD_OPC_Decode, 155, 2, 139, 1, // Opcode: BNEG_W -/* 5702 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 5715 -/* 5706 */ MCD_OPC_CheckPredicate, 8, 80, 31, // Skip to: 13726 -/* 5710 */ MCD_OPC_Decode, 153, 2, 140, 1, // Opcode: BNEG_D -/* 5715 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 5728 -/* 5719 */ MCD_OPC_CheckPredicate, 8, 67, 31, // Skip to: 13726 -/* 5723 */ MCD_OPC_Decode, 237, 1, 141, 1, // Opcode: BINSL_B -/* 5728 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 5741 -/* 5732 */ MCD_OPC_CheckPredicate, 8, 54, 31, // Skip to: 13726 -/* 5736 */ MCD_OPC_Decode, 239, 1, 142, 1, // Opcode: BINSL_H -/* 5741 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 5754 -/* 5745 */ MCD_OPC_CheckPredicate, 8, 41, 31, // Skip to: 13726 -/* 5749 */ MCD_OPC_Decode, 240, 1, 143, 1, // Opcode: BINSL_W -/* 5754 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 5767 -/* 5758 */ MCD_OPC_CheckPredicate, 8, 28, 31, // Skip to: 13726 -/* 5762 */ MCD_OPC_Decode, 238, 1, 144, 1, // Opcode: BINSL_D -/* 5767 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 5780 -/* 5771 */ MCD_OPC_CheckPredicate, 8, 15, 31, // Skip to: 13726 -/* 5775 */ MCD_OPC_Decode, 245, 1, 141, 1, // Opcode: BINSR_B -/* 5780 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 5793 -/* 5784 */ MCD_OPC_CheckPredicate, 8, 2, 31, // Skip to: 13726 -/* 5788 */ MCD_OPC_Decode, 247, 1, 142, 1, // Opcode: BINSR_H -/* 5793 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 5806 -/* 5797 */ MCD_OPC_CheckPredicate, 8, 245, 30, // Skip to: 13726 -/* 5801 */ MCD_OPC_Decode, 248, 1, 143, 1, // Opcode: BINSR_W -/* 5806 */ MCD_OPC_FilterValue, 31, 236, 30, // Skip to: 13726 -/* 5810 */ MCD_OPC_CheckPredicate, 8, 232, 30, // Skip to: 13726 -/* 5814 */ MCD_OPC_Decode, 246, 1, 144, 1, // Opcode: BINSR_D -/* 5819 */ MCD_OPC_FilterValue, 14, 159, 1, // Skip to: 6238 -/* 5823 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 5826 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5838 -/* 5830 */ MCD_OPC_CheckPredicate, 8, 212, 30, // Skip to: 13726 -/* 5834 */ MCD_OPC_Decode, 63, 137, 1, // Opcode: ADDV_B -/* 5838 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5850 -/* 5842 */ MCD_OPC_CheckPredicate, 8, 200, 30, // Skip to: 13726 -/* 5846 */ MCD_OPC_Decode, 65, 138, 1, // Opcode: ADDV_H -/* 5850 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5862 -/* 5854 */ MCD_OPC_CheckPredicate, 8, 188, 30, // Skip to: 13726 -/* 5858 */ MCD_OPC_Decode, 66, 139, 1, // Opcode: ADDV_W -/* 5862 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 5874 -/* 5866 */ MCD_OPC_CheckPredicate, 8, 176, 30, // Skip to: 13726 -/* 5870 */ MCD_OPC_Decode, 64, 140, 1, // Opcode: ADDV_D -/* 5874 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5887 -/* 5878 */ MCD_OPC_CheckPredicate, 8, 164, 30, // Skip to: 13726 -/* 5882 */ MCD_OPC_Decode, 225, 12, 137, 1, // Opcode: SUBV_B -/* 5887 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 5900 -/* 5891 */ MCD_OPC_CheckPredicate, 8, 151, 30, // Skip to: 13726 -/* 5895 */ MCD_OPC_Decode, 227, 12, 138, 1, // Opcode: SUBV_H -/* 5900 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5913 -/* 5904 */ MCD_OPC_CheckPredicate, 8, 138, 30, // Skip to: 13726 -/* 5908 */ MCD_OPC_Decode, 228, 12, 139, 1, // Opcode: SUBV_W -/* 5913 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 5926 -/* 5917 */ MCD_OPC_CheckPredicate, 8, 125, 30, // Skip to: 13726 -/* 5921 */ MCD_OPC_Decode, 226, 12, 140, 1, // Opcode: SUBV_D -/* 5926 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 5939 -/* 5930 */ MCD_OPC_CheckPredicate, 8, 112, 30, // Skip to: 13726 -/* 5934 */ MCD_OPC_Decode, 171, 8, 137, 1, // Opcode: MAX_S_B -/* 5939 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 5952 -/* 5943 */ MCD_OPC_CheckPredicate, 8, 99, 30, // Skip to: 13726 -/* 5947 */ MCD_OPC_Decode, 173, 8, 138, 1, // Opcode: MAX_S_H -/* 5952 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 5965 -/* 5956 */ MCD_OPC_CheckPredicate, 8, 86, 30, // Skip to: 13726 -/* 5960 */ MCD_OPC_Decode, 174, 8, 139, 1, // Opcode: MAX_S_W -/* 5965 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 5978 -/* 5969 */ MCD_OPC_CheckPredicate, 8, 73, 30, // Skip to: 13726 -/* 5973 */ MCD_OPC_Decode, 172, 8, 140, 1, // Opcode: MAX_S_D -/* 5978 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 5991 -/* 5982 */ MCD_OPC_CheckPredicate, 8, 60, 30, // Skip to: 13726 -/* 5986 */ MCD_OPC_Decode, 175, 8, 137, 1, // Opcode: MAX_U_B -/* 5991 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 6004 -/* 5995 */ MCD_OPC_CheckPredicate, 8, 47, 30, // Skip to: 13726 -/* 5999 */ MCD_OPC_Decode, 177, 8, 138, 1, // Opcode: MAX_U_H -/* 6004 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 6017 -/* 6008 */ MCD_OPC_CheckPredicate, 8, 34, 30, // Skip to: 13726 -/* 6012 */ MCD_OPC_Decode, 178, 8, 139, 1, // Opcode: MAX_U_W -/* 6017 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 6030 -/* 6021 */ MCD_OPC_CheckPredicate, 8, 21, 30, // Skip to: 13726 -/* 6025 */ MCD_OPC_Decode, 176, 8, 140, 1, // Opcode: MAX_U_D -/* 6030 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6043 -/* 6034 */ MCD_OPC_CheckPredicate, 8, 8, 30, // Skip to: 13726 -/* 6038 */ MCD_OPC_Decode, 212, 8, 137, 1, // Opcode: MIN_S_B -/* 6043 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6056 -/* 6047 */ MCD_OPC_CheckPredicate, 8, 251, 29, // Skip to: 13726 -/* 6051 */ MCD_OPC_Decode, 214, 8, 138, 1, // Opcode: MIN_S_H -/* 6056 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6069 -/* 6060 */ MCD_OPC_CheckPredicate, 8, 238, 29, // Skip to: 13726 -/* 6064 */ MCD_OPC_Decode, 215, 8, 139, 1, // Opcode: MIN_S_W -/* 6069 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6082 -/* 6073 */ MCD_OPC_CheckPredicate, 8, 225, 29, // Skip to: 13726 -/* 6077 */ MCD_OPC_Decode, 213, 8, 140, 1, // Opcode: MIN_S_D -/* 6082 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6095 -/* 6086 */ MCD_OPC_CheckPredicate, 8, 212, 29, // Skip to: 13726 -/* 6090 */ MCD_OPC_Decode, 216, 8, 137, 1, // Opcode: MIN_U_B -/* 6095 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6108 -/* 6099 */ MCD_OPC_CheckPredicate, 8, 199, 29, // Skip to: 13726 -/* 6103 */ MCD_OPC_Decode, 218, 8, 138, 1, // Opcode: MIN_U_H -/* 6108 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6121 -/* 6112 */ MCD_OPC_CheckPredicate, 8, 186, 29, // Skip to: 13726 -/* 6116 */ MCD_OPC_Decode, 219, 8, 139, 1, // Opcode: MIN_U_W -/* 6121 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 6134 -/* 6125 */ MCD_OPC_CheckPredicate, 8, 173, 29, // Skip to: 13726 -/* 6129 */ MCD_OPC_Decode, 217, 8, 140, 1, // Opcode: MIN_U_D -/* 6134 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 6147 -/* 6138 */ MCD_OPC_CheckPredicate, 8, 160, 29, // Skip to: 13726 -/* 6142 */ MCD_OPC_Decode, 165, 8, 137, 1, // Opcode: MAX_A_B -/* 6147 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 6160 -/* 6151 */ MCD_OPC_CheckPredicate, 8, 147, 29, // Skip to: 13726 -/* 6155 */ MCD_OPC_Decode, 167, 8, 138, 1, // Opcode: MAX_A_H -/* 6160 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 6173 -/* 6164 */ MCD_OPC_CheckPredicate, 8, 134, 29, // Skip to: 13726 -/* 6168 */ MCD_OPC_Decode, 168, 8, 139, 1, // Opcode: MAX_A_W -/* 6173 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 6186 -/* 6177 */ MCD_OPC_CheckPredicate, 8, 121, 29, // Skip to: 13726 -/* 6181 */ MCD_OPC_Decode, 166, 8, 140, 1, // Opcode: MAX_A_D -/* 6186 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 6199 -/* 6190 */ MCD_OPC_CheckPredicate, 8, 108, 29, // Skip to: 13726 -/* 6194 */ MCD_OPC_Decode, 206, 8, 137, 1, // Opcode: MIN_A_B -/* 6199 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 6212 -/* 6203 */ MCD_OPC_CheckPredicate, 8, 95, 29, // Skip to: 13726 -/* 6207 */ MCD_OPC_Decode, 208, 8, 138, 1, // Opcode: MIN_A_H -/* 6212 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 6225 -/* 6216 */ MCD_OPC_CheckPredicate, 8, 82, 29, // Skip to: 13726 -/* 6220 */ MCD_OPC_Decode, 209, 8, 139, 1, // Opcode: MIN_A_W -/* 6225 */ MCD_OPC_FilterValue, 31, 73, 29, // Skip to: 13726 -/* 6229 */ MCD_OPC_CheckPredicate, 8, 69, 29, // Skip to: 13726 -/* 6233 */ MCD_OPC_Decode, 207, 8, 140, 1, // Opcode: MIN_A_D -/* 6238 */ MCD_OPC_FilterValue, 15, 7, 1, // Skip to: 6505 -/* 6242 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 6245 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6258 -/* 6249 */ MCD_OPC_CheckPredicate, 8, 49, 29, // Skip to: 13726 -/* 6253 */ MCD_OPC_Decode, 234, 2, 137, 1, // Opcode: CEQ_B -/* 6258 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6271 -/* 6262 */ MCD_OPC_CheckPredicate, 8, 36, 29, // Skip to: 13726 -/* 6266 */ MCD_OPC_Decode, 236, 2, 138, 1, // Opcode: CEQ_H -/* 6271 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6284 -/* 6275 */ MCD_OPC_CheckPredicate, 8, 23, 29, // Skip to: 13726 -/* 6279 */ MCD_OPC_Decode, 237, 2, 139, 1, // Opcode: CEQ_W -/* 6284 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6297 -/* 6288 */ MCD_OPC_CheckPredicate, 8, 10, 29, // Skip to: 13726 -/* 6292 */ MCD_OPC_Decode, 235, 2, 140, 1, // Opcode: CEQ_D -/* 6297 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 6310 -/* 6301 */ MCD_OPC_CheckPredicate, 8, 253, 28, // Skip to: 13726 -/* 6305 */ MCD_OPC_Decode, 144, 3, 137, 1, // Opcode: CLT_S_B -/* 6310 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 6323 -/* 6314 */ MCD_OPC_CheckPredicate, 8, 240, 28, // Skip to: 13726 -/* 6318 */ MCD_OPC_Decode, 146, 3, 138, 1, // Opcode: CLT_S_H -/* 6323 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 6336 -/* 6327 */ MCD_OPC_CheckPredicate, 8, 227, 28, // Skip to: 13726 -/* 6331 */ MCD_OPC_Decode, 147, 3, 139, 1, // Opcode: CLT_S_W -/* 6336 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 6349 -/* 6340 */ MCD_OPC_CheckPredicate, 8, 214, 28, // Skip to: 13726 -/* 6344 */ MCD_OPC_Decode, 145, 3, 140, 1, // Opcode: CLT_S_D -/* 6349 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 6362 -/* 6353 */ MCD_OPC_CheckPredicate, 8, 201, 28, // Skip to: 13726 -/* 6357 */ MCD_OPC_Decode, 148, 3, 137, 1, // Opcode: CLT_U_B -/* 6362 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 6375 -/* 6366 */ MCD_OPC_CheckPredicate, 8, 188, 28, // Skip to: 13726 -/* 6370 */ MCD_OPC_Decode, 150, 3, 138, 1, // Opcode: CLT_U_H -/* 6375 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 6388 -/* 6379 */ MCD_OPC_CheckPredicate, 8, 175, 28, // Skip to: 13726 -/* 6383 */ MCD_OPC_Decode, 151, 3, 139, 1, // Opcode: CLT_U_W -/* 6388 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 6401 -/* 6392 */ MCD_OPC_CheckPredicate, 8, 162, 28, // Skip to: 13726 -/* 6396 */ MCD_OPC_Decode, 149, 3, 140, 1, // Opcode: CLT_U_D -/* 6401 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6414 -/* 6405 */ MCD_OPC_CheckPredicate, 8, 149, 28, // Skip to: 13726 -/* 6409 */ MCD_OPC_Decode, 253, 2, 137, 1, // Opcode: CLE_S_B -/* 6414 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6427 -/* 6418 */ MCD_OPC_CheckPredicate, 8, 136, 28, // Skip to: 13726 -/* 6422 */ MCD_OPC_Decode, 255, 2, 138, 1, // Opcode: CLE_S_H -/* 6427 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6440 -/* 6431 */ MCD_OPC_CheckPredicate, 8, 123, 28, // Skip to: 13726 -/* 6435 */ MCD_OPC_Decode, 128, 3, 139, 1, // Opcode: CLE_S_W -/* 6440 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6453 -/* 6444 */ MCD_OPC_CheckPredicate, 8, 110, 28, // Skip to: 13726 -/* 6448 */ MCD_OPC_Decode, 254, 2, 140, 1, // Opcode: CLE_S_D -/* 6453 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6466 -/* 6457 */ MCD_OPC_CheckPredicate, 8, 97, 28, // Skip to: 13726 -/* 6461 */ MCD_OPC_Decode, 129, 3, 137, 1, // Opcode: CLE_U_B -/* 6466 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6479 -/* 6470 */ MCD_OPC_CheckPredicate, 8, 84, 28, // Skip to: 13726 -/* 6474 */ MCD_OPC_Decode, 131, 3, 138, 1, // Opcode: CLE_U_H -/* 6479 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6492 -/* 6483 */ MCD_OPC_CheckPredicate, 8, 71, 28, // Skip to: 13726 -/* 6487 */ MCD_OPC_Decode, 132, 3, 139, 1, // Opcode: CLE_U_W -/* 6492 */ MCD_OPC_FilterValue, 23, 62, 28, // Skip to: 13726 -/* 6496 */ MCD_OPC_CheckPredicate, 8, 58, 28, // Skip to: 13726 -/* 6500 */ MCD_OPC_Decode, 130, 3, 140, 1, // Opcode: CLE_U_D -/* 6505 */ MCD_OPC_FilterValue, 16, 147, 1, // Skip to: 6912 -/* 6509 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 6512 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6524 -/* 6516 */ MCD_OPC_CheckPredicate, 8, 38, 28, // Skip to: 13726 -/* 6520 */ MCD_OPC_Decode, 68, 137, 1, // Opcode: ADD_A_B -/* 6524 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6536 -/* 6528 */ MCD_OPC_CheckPredicate, 8, 26, 28, // Skip to: 13726 -/* 6532 */ MCD_OPC_Decode, 70, 138, 1, // Opcode: ADD_A_H -/* 6536 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6548 -/* 6540 */ MCD_OPC_CheckPredicate, 8, 14, 28, // Skip to: 13726 -/* 6544 */ MCD_OPC_Decode, 71, 139, 1, // Opcode: ADD_A_W -/* 6548 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 6560 -/* 6552 */ MCD_OPC_CheckPredicate, 8, 2, 28, // Skip to: 13726 -/* 6556 */ MCD_OPC_Decode, 69, 140, 1, // Opcode: ADD_A_D -/* 6560 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 6572 -/* 6564 */ MCD_OPC_CheckPredicate, 8, 246, 27, // Skip to: 13726 -/* 6568 */ MCD_OPC_Decode, 40, 137, 1, // Opcode: ADDS_A_B -/* 6572 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 6584 -/* 6576 */ MCD_OPC_CheckPredicate, 8, 234, 27, // Skip to: 13726 -/* 6580 */ MCD_OPC_Decode, 42, 138, 1, // Opcode: ADDS_A_H -/* 6584 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 6596 -/* 6588 */ MCD_OPC_CheckPredicate, 8, 222, 27, // Skip to: 13726 -/* 6592 */ MCD_OPC_Decode, 43, 139, 1, // Opcode: ADDS_A_W -/* 6596 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 6608 -/* 6600 */ MCD_OPC_CheckPredicate, 8, 210, 27, // Skip to: 13726 -/* 6604 */ MCD_OPC_Decode, 41, 140, 1, // Opcode: ADDS_A_D -/* 6608 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 6620 -/* 6612 */ MCD_OPC_CheckPredicate, 8, 198, 27, // Skip to: 13726 -/* 6616 */ MCD_OPC_Decode, 44, 137, 1, // Opcode: ADDS_S_B -/* 6620 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 6632 -/* 6624 */ MCD_OPC_CheckPredicate, 8, 186, 27, // Skip to: 13726 -/* 6628 */ MCD_OPC_Decode, 46, 138, 1, // Opcode: ADDS_S_H -/* 6632 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 6644 -/* 6636 */ MCD_OPC_CheckPredicate, 8, 174, 27, // Skip to: 13726 -/* 6640 */ MCD_OPC_Decode, 47, 139, 1, // Opcode: ADDS_S_W -/* 6644 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 6656 -/* 6648 */ MCD_OPC_CheckPredicate, 8, 162, 27, // Skip to: 13726 -/* 6652 */ MCD_OPC_Decode, 45, 140, 1, // Opcode: ADDS_S_D -/* 6656 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 6668 -/* 6660 */ MCD_OPC_CheckPredicate, 8, 150, 27, // Skip to: 13726 -/* 6664 */ MCD_OPC_Decode, 48, 137, 1, // Opcode: ADDS_U_B -/* 6668 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 6680 -/* 6672 */ MCD_OPC_CheckPredicate, 8, 138, 27, // Skip to: 13726 -/* 6676 */ MCD_OPC_Decode, 50, 138, 1, // Opcode: ADDS_U_H -/* 6680 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 6692 -/* 6684 */ MCD_OPC_CheckPredicate, 8, 126, 27, // Skip to: 13726 -/* 6688 */ MCD_OPC_Decode, 51, 139, 1, // Opcode: ADDS_U_W -/* 6692 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 6704 -/* 6696 */ MCD_OPC_CheckPredicate, 8, 114, 27, // Skip to: 13726 -/* 6700 */ MCD_OPC_Decode, 49, 140, 1, // Opcode: ADDS_U_D -/* 6704 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6717 -/* 6708 */ MCD_OPC_CheckPredicate, 8, 102, 27, // Skip to: 13726 -/* 6712 */ MCD_OPC_Decode, 147, 1, 137, 1, // Opcode: AVE_S_B -/* 6717 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6730 -/* 6721 */ MCD_OPC_CheckPredicate, 8, 89, 27, // Skip to: 13726 -/* 6725 */ MCD_OPC_Decode, 149, 1, 138, 1, // Opcode: AVE_S_H -/* 6730 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6743 -/* 6734 */ MCD_OPC_CheckPredicate, 8, 76, 27, // Skip to: 13726 -/* 6738 */ MCD_OPC_Decode, 150, 1, 139, 1, // Opcode: AVE_S_W -/* 6743 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6756 -/* 6747 */ MCD_OPC_CheckPredicate, 8, 63, 27, // Skip to: 13726 -/* 6751 */ MCD_OPC_Decode, 148, 1, 140, 1, // Opcode: AVE_S_D -/* 6756 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6769 -/* 6760 */ MCD_OPC_CheckPredicate, 8, 50, 27, // Skip to: 13726 -/* 6764 */ MCD_OPC_Decode, 151, 1, 137, 1, // Opcode: AVE_U_B -/* 6769 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6782 -/* 6773 */ MCD_OPC_CheckPredicate, 8, 37, 27, // Skip to: 13726 -/* 6777 */ MCD_OPC_Decode, 153, 1, 138, 1, // Opcode: AVE_U_H -/* 6782 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6795 -/* 6786 */ MCD_OPC_CheckPredicate, 8, 24, 27, // Skip to: 13726 -/* 6790 */ MCD_OPC_Decode, 154, 1, 139, 1, // Opcode: AVE_U_W -/* 6795 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 6808 -/* 6799 */ MCD_OPC_CheckPredicate, 8, 11, 27, // Skip to: 13726 -/* 6803 */ MCD_OPC_Decode, 152, 1, 140, 1, // Opcode: AVE_U_D -/* 6808 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 6821 -/* 6812 */ MCD_OPC_CheckPredicate, 8, 254, 26, // Skip to: 13726 -/* 6816 */ MCD_OPC_Decode, 139, 1, 137, 1, // Opcode: AVER_S_B -/* 6821 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 6834 -/* 6825 */ MCD_OPC_CheckPredicate, 8, 241, 26, // Skip to: 13726 -/* 6829 */ MCD_OPC_Decode, 141, 1, 138, 1, // Opcode: AVER_S_H -/* 6834 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 6847 -/* 6838 */ MCD_OPC_CheckPredicate, 8, 228, 26, // Skip to: 13726 -/* 6842 */ MCD_OPC_Decode, 142, 1, 139, 1, // Opcode: AVER_S_W -/* 6847 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 6860 -/* 6851 */ MCD_OPC_CheckPredicate, 8, 215, 26, // Skip to: 13726 -/* 6855 */ MCD_OPC_Decode, 140, 1, 140, 1, // Opcode: AVER_S_D -/* 6860 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 6873 -/* 6864 */ MCD_OPC_CheckPredicate, 8, 202, 26, // Skip to: 13726 -/* 6868 */ MCD_OPC_Decode, 143, 1, 137, 1, // Opcode: AVER_U_B -/* 6873 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 6886 -/* 6877 */ MCD_OPC_CheckPredicate, 8, 189, 26, // Skip to: 13726 -/* 6881 */ MCD_OPC_Decode, 145, 1, 138, 1, // Opcode: AVER_U_H -/* 6886 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 6899 -/* 6890 */ MCD_OPC_CheckPredicate, 8, 176, 26, // Skip to: 13726 -/* 6894 */ MCD_OPC_Decode, 146, 1, 139, 1, // Opcode: AVER_U_W -/* 6899 */ MCD_OPC_FilterValue, 31, 167, 26, // Skip to: 13726 -/* 6903 */ MCD_OPC_CheckPredicate, 8, 163, 26, // Skip to: 13726 -/* 6907 */ MCD_OPC_Decode, 144, 1, 140, 1, // Opcode: AVER_U_D -/* 6912 */ MCD_OPC_FilterValue, 17, 51, 1, // Skip to: 7223 -/* 6916 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 6919 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6932 -/* 6923 */ MCD_OPC_CheckPredicate, 8, 143, 26, // Skip to: 13726 -/* 6927 */ MCD_OPC_Decode, 206, 12, 137, 1, // Opcode: SUBS_S_B -/* 6932 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6945 -/* 6936 */ MCD_OPC_CheckPredicate, 8, 130, 26, // Skip to: 13726 -/* 6940 */ MCD_OPC_Decode, 208, 12, 138, 1, // Opcode: SUBS_S_H -/* 6945 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6958 -/* 6949 */ MCD_OPC_CheckPredicate, 8, 117, 26, // Skip to: 13726 -/* 6953 */ MCD_OPC_Decode, 209, 12, 139, 1, // Opcode: SUBS_S_W -/* 6958 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6971 -/* 6962 */ MCD_OPC_CheckPredicate, 8, 104, 26, // Skip to: 13726 -/* 6966 */ MCD_OPC_Decode, 207, 12, 140, 1, // Opcode: SUBS_S_D -/* 6971 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 6984 -/* 6975 */ MCD_OPC_CheckPredicate, 8, 91, 26, // Skip to: 13726 -/* 6979 */ MCD_OPC_Decode, 210, 12, 137, 1, // Opcode: SUBS_U_B -/* 6984 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 6997 -/* 6988 */ MCD_OPC_CheckPredicate, 8, 78, 26, // Skip to: 13726 -/* 6992 */ MCD_OPC_Decode, 212, 12, 138, 1, // Opcode: SUBS_U_H -/* 6997 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7010 -/* 7001 */ MCD_OPC_CheckPredicate, 8, 65, 26, // Skip to: 13726 -/* 7005 */ MCD_OPC_Decode, 213, 12, 139, 1, // Opcode: SUBS_U_W -/* 7010 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7023 -/* 7014 */ MCD_OPC_CheckPredicate, 8, 52, 26, // Skip to: 13726 -/* 7018 */ MCD_OPC_Decode, 211, 12, 140, 1, // Opcode: SUBS_U_D -/* 7023 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7036 -/* 7027 */ MCD_OPC_CheckPredicate, 8, 39, 26, // Skip to: 13726 -/* 7031 */ MCD_OPC_Decode, 198, 12, 137, 1, // Opcode: SUBSUS_U_B -/* 7036 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7049 -/* 7040 */ MCD_OPC_CheckPredicate, 8, 26, 26, // Skip to: 13726 -/* 7044 */ MCD_OPC_Decode, 200, 12, 138, 1, // Opcode: SUBSUS_U_H -/* 7049 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7062 -/* 7053 */ MCD_OPC_CheckPredicate, 8, 13, 26, // Skip to: 13726 -/* 7057 */ MCD_OPC_Decode, 201, 12, 139, 1, // Opcode: SUBSUS_U_W -/* 7062 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7075 -/* 7066 */ MCD_OPC_CheckPredicate, 8, 0, 26, // Skip to: 13726 -/* 7070 */ MCD_OPC_Decode, 199, 12, 140, 1, // Opcode: SUBSUS_U_D -/* 7075 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 7088 -/* 7079 */ MCD_OPC_CheckPredicate, 8, 243, 25, // Skip to: 13726 -/* 7083 */ MCD_OPC_Decode, 202, 12, 137, 1, // Opcode: SUBSUU_S_B -/* 7088 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7101 -/* 7092 */ MCD_OPC_CheckPredicate, 8, 230, 25, // Skip to: 13726 -/* 7096 */ MCD_OPC_Decode, 204, 12, 138, 1, // Opcode: SUBSUU_S_H -/* 7101 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7114 -/* 7105 */ MCD_OPC_CheckPredicate, 8, 217, 25, // Skip to: 13726 -/* 7109 */ MCD_OPC_Decode, 205, 12, 139, 1, // Opcode: SUBSUU_S_W -/* 7114 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 7127 -/* 7118 */ MCD_OPC_CheckPredicate, 8, 204, 25, // Skip to: 13726 -/* 7122 */ MCD_OPC_Decode, 203, 12, 140, 1, // Opcode: SUBSUU_S_D -/* 7127 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 7139 -/* 7131 */ MCD_OPC_CheckPredicate, 8, 191, 25, // Skip to: 13726 -/* 7135 */ MCD_OPC_Decode, 97, 137, 1, // Opcode: ASUB_S_B -/* 7139 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 7151 -/* 7143 */ MCD_OPC_CheckPredicate, 8, 179, 25, // Skip to: 13726 -/* 7147 */ MCD_OPC_Decode, 99, 138, 1, // Opcode: ASUB_S_H -/* 7151 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 7163 -/* 7155 */ MCD_OPC_CheckPredicate, 8, 167, 25, // Skip to: 13726 -/* 7159 */ MCD_OPC_Decode, 100, 139, 1, // Opcode: ASUB_S_W -/* 7163 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 7175 -/* 7167 */ MCD_OPC_CheckPredicate, 8, 155, 25, // Skip to: 13726 -/* 7171 */ MCD_OPC_Decode, 98, 140, 1, // Opcode: ASUB_S_D -/* 7175 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 7187 -/* 7179 */ MCD_OPC_CheckPredicate, 8, 143, 25, // Skip to: 13726 -/* 7183 */ MCD_OPC_Decode, 101, 137, 1, // Opcode: ASUB_U_B -/* 7187 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 7199 -/* 7191 */ MCD_OPC_CheckPredicate, 8, 131, 25, // Skip to: 13726 -/* 7195 */ MCD_OPC_Decode, 103, 138, 1, // Opcode: ASUB_U_H -/* 7199 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 7211 -/* 7203 */ MCD_OPC_CheckPredicate, 8, 119, 25, // Skip to: 13726 -/* 7207 */ MCD_OPC_Decode, 104, 139, 1, // Opcode: ASUB_U_W -/* 7211 */ MCD_OPC_FilterValue, 23, 111, 25, // Skip to: 13726 -/* 7215 */ MCD_OPC_CheckPredicate, 8, 107, 25, // Skip to: 13726 -/* 7219 */ MCD_OPC_Decode, 102, 140, 1, // Opcode: ASUB_U_D -/* 7223 */ MCD_OPC_FilterValue, 18, 111, 1, // Skip to: 7594 -/* 7227 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 7230 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7243 -/* 7234 */ MCD_OPC_CheckPredicate, 8, 88, 25, // Skip to: 13726 -/* 7238 */ MCD_OPC_Decode, 213, 9, 137, 1, // Opcode: MULV_B -/* 7243 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7256 -/* 7247 */ MCD_OPC_CheckPredicate, 8, 75, 25, // Skip to: 13726 -/* 7251 */ MCD_OPC_Decode, 215, 9, 138, 1, // Opcode: MULV_H -/* 7256 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7269 -/* 7260 */ MCD_OPC_CheckPredicate, 8, 62, 25, // Skip to: 13726 -/* 7264 */ MCD_OPC_Decode, 216, 9, 139, 1, // Opcode: MULV_W -/* 7269 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7282 -/* 7273 */ MCD_OPC_CheckPredicate, 8, 49, 25, // Skip to: 13726 -/* 7277 */ MCD_OPC_Decode, 214, 9, 140, 1, // Opcode: MULV_D -/* 7282 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7295 -/* 7286 */ MCD_OPC_CheckPredicate, 8, 36, 25, // Skip to: 13726 -/* 7290 */ MCD_OPC_Decode, 138, 8, 141, 1, // Opcode: MADDV_B -/* 7295 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7308 -/* 7299 */ MCD_OPC_CheckPredicate, 8, 23, 25, // Skip to: 13726 -/* 7303 */ MCD_OPC_Decode, 140, 8, 142, 1, // Opcode: MADDV_H -/* 7308 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7321 -/* 7312 */ MCD_OPC_CheckPredicate, 8, 10, 25, // Skip to: 13726 -/* 7316 */ MCD_OPC_Decode, 141, 8, 143, 1, // Opcode: MADDV_W -/* 7321 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7334 -/* 7325 */ MCD_OPC_CheckPredicate, 8, 253, 24, // Skip to: 13726 -/* 7329 */ MCD_OPC_Decode, 139, 8, 144, 1, // Opcode: MADDV_D -/* 7334 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7347 -/* 7338 */ MCD_OPC_CheckPredicate, 8, 240, 24, // Skip to: 13726 -/* 7342 */ MCD_OPC_Decode, 156, 9, 141, 1, // Opcode: MSUBV_B -/* 7347 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7360 -/* 7351 */ MCD_OPC_CheckPredicate, 8, 227, 24, // Skip to: 13726 -/* 7355 */ MCD_OPC_Decode, 158, 9, 142, 1, // Opcode: MSUBV_H -/* 7360 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7373 -/* 7364 */ MCD_OPC_CheckPredicate, 8, 214, 24, // Skip to: 13726 -/* 7368 */ MCD_OPC_Decode, 159, 9, 143, 1, // Opcode: MSUBV_W -/* 7373 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7386 -/* 7377 */ MCD_OPC_CheckPredicate, 8, 201, 24, // Skip to: 13726 -/* 7381 */ MCD_OPC_Decode, 157, 9, 144, 1, // Opcode: MSUBV_D -/* 7386 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 7399 -/* 7390 */ MCD_OPC_CheckPredicate, 8, 188, 24, // Skip to: 13726 -/* 7394 */ MCD_OPC_Decode, 185, 4, 137, 1, // Opcode: DIV_S_B -/* 7399 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 7412 -/* 7403 */ MCD_OPC_CheckPredicate, 8, 175, 24, // Skip to: 13726 -/* 7407 */ MCD_OPC_Decode, 187, 4, 138, 1, // Opcode: DIV_S_H -/* 7412 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 7425 -/* 7416 */ MCD_OPC_CheckPredicate, 8, 162, 24, // Skip to: 13726 -/* 7420 */ MCD_OPC_Decode, 188, 4, 139, 1, // Opcode: DIV_S_W -/* 7425 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 7438 -/* 7429 */ MCD_OPC_CheckPredicate, 8, 149, 24, // Skip to: 13726 -/* 7433 */ MCD_OPC_Decode, 186, 4, 140, 1, // Opcode: DIV_S_D -/* 7438 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 7451 -/* 7442 */ MCD_OPC_CheckPredicate, 8, 136, 24, // Skip to: 13726 -/* 7446 */ MCD_OPC_Decode, 189, 4, 137, 1, // Opcode: DIV_U_B -/* 7451 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 7464 -/* 7455 */ MCD_OPC_CheckPredicate, 8, 123, 24, // Skip to: 13726 -/* 7459 */ MCD_OPC_Decode, 191, 4, 138, 1, // Opcode: DIV_U_H -/* 7464 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 7477 -/* 7468 */ MCD_OPC_CheckPredicate, 8, 110, 24, // Skip to: 13726 -/* 7472 */ MCD_OPC_Decode, 192, 4, 139, 1, // Opcode: DIV_U_W -/* 7477 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 7490 -/* 7481 */ MCD_OPC_CheckPredicate, 8, 97, 24, // Skip to: 13726 -/* 7485 */ MCD_OPC_Decode, 190, 4, 140, 1, // Opcode: DIV_U_D -/* 7490 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 7503 -/* 7494 */ MCD_OPC_CheckPredicate, 8, 84, 24, // Skip to: 13726 -/* 7498 */ MCD_OPC_Decode, 225, 8, 137, 1, // Opcode: MOD_S_B -/* 7503 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 7516 -/* 7507 */ MCD_OPC_CheckPredicate, 8, 71, 24, // Skip to: 13726 -/* 7511 */ MCD_OPC_Decode, 227, 8, 138, 1, // Opcode: MOD_S_H -/* 7516 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 7529 -/* 7520 */ MCD_OPC_CheckPredicate, 8, 58, 24, // Skip to: 13726 -/* 7524 */ MCD_OPC_Decode, 228, 8, 139, 1, // Opcode: MOD_S_W -/* 7529 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 7542 -/* 7533 */ MCD_OPC_CheckPredicate, 8, 45, 24, // Skip to: 13726 -/* 7537 */ MCD_OPC_Decode, 226, 8, 140, 1, // Opcode: MOD_S_D -/* 7542 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 7555 -/* 7546 */ MCD_OPC_CheckPredicate, 8, 32, 24, // Skip to: 13726 -/* 7550 */ MCD_OPC_Decode, 229, 8, 137, 1, // Opcode: MOD_U_B -/* 7555 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 7568 -/* 7559 */ MCD_OPC_CheckPredicate, 8, 19, 24, // Skip to: 13726 -/* 7563 */ MCD_OPC_Decode, 231, 8, 138, 1, // Opcode: MOD_U_H -/* 7568 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 7581 -/* 7572 */ MCD_OPC_CheckPredicate, 8, 6, 24, // Skip to: 13726 -/* 7576 */ MCD_OPC_Decode, 232, 8, 139, 1, // Opcode: MOD_U_W -/* 7581 */ MCD_OPC_FilterValue, 31, 253, 23, // Skip to: 13726 -/* 7585 */ MCD_OPC_CheckPredicate, 8, 249, 23, // Skip to: 13726 -/* 7589 */ MCD_OPC_Decode, 230, 8, 140, 1, // Opcode: MOD_U_D -/* 7594 */ MCD_OPC_FilterValue, 19, 237, 0, // Skip to: 7835 -/* 7598 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 7601 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7614 -/* 7605 */ MCD_OPC_CheckPredicate, 8, 229, 23, // Skip to: 13726 -/* 7609 */ MCD_OPC_Decode, 212, 4, 145, 1, // Opcode: DOTP_S_H -/* 7614 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7627 -/* 7618 */ MCD_OPC_CheckPredicate, 8, 216, 23, // Skip to: 13726 -/* 7622 */ MCD_OPC_Decode, 213, 4, 146, 1, // Opcode: DOTP_S_W -/* 7627 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7640 -/* 7631 */ MCD_OPC_CheckPredicate, 8, 203, 23, // Skip to: 13726 -/* 7635 */ MCD_OPC_Decode, 211, 4, 147, 1, // Opcode: DOTP_S_D -/* 7640 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7653 -/* 7644 */ MCD_OPC_CheckPredicate, 8, 190, 23, // Skip to: 13726 -/* 7648 */ MCD_OPC_Decode, 215, 4, 145, 1, // Opcode: DOTP_U_H -/* 7653 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7666 -/* 7657 */ MCD_OPC_CheckPredicate, 8, 177, 23, // Skip to: 13726 -/* 7661 */ MCD_OPC_Decode, 216, 4, 146, 1, // Opcode: DOTP_U_W -/* 7666 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7679 -/* 7670 */ MCD_OPC_CheckPredicate, 8, 164, 23, // Skip to: 13726 -/* 7674 */ MCD_OPC_Decode, 214, 4, 147, 1, // Opcode: DOTP_U_D -/* 7679 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7692 -/* 7683 */ MCD_OPC_CheckPredicate, 8, 151, 23, // Skip to: 13726 -/* 7687 */ MCD_OPC_Decode, 218, 4, 148, 1, // Opcode: DPADD_S_H -/* 7692 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7705 -/* 7696 */ MCD_OPC_CheckPredicate, 8, 138, 23, // Skip to: 13726 -/* 7700 */ MCD_OPC_Decode, 219, 4, 149, 1, // Opcode: DPADD_S_W -/* 7705 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7718 -/* 7709 */ MCD_OPC_CheckPredicate, 8, 125, 23, // Skip to: 13726 -/* 7713 */ MCD_OPC_Decode, 217, 4, 150, 1, // Opcode: DPADD_S_D -/* 7718 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7731 -/* 7722 */ MCD_OPC_CheckPredicate, 8, 112, 23, // Skip to: 13726 -/* 7726 */ MCD_OPC_Decode, 221, 4, 148, 1, // Opcode: DPADD_U_H -/* 7731 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7744 -/* 7735 */ MCD_OPC_CheckPredicate, 8, 99, 23, // Skip to: 13726 -/* 7739 */ MCD_OPC_Decode, 222, 4, 149, 1, // Opcode: DPADD_U_W -/* 7744 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 7757 -/* 7748 */ MCD_OPC_CheckPredicate, 8, 86, 23, // Skip to: 13726 -/* 7752 */ MCD_OPC_Decode, 220, 4, 150, 1, // Opcode: DPADD_U_D -/* 7757 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 7770 -/* 7761 */ MCD_OPC_CheckPredicate, 8, 73, 23, // Skip to: 13726 -/* 7765 */ MCD_OPC_Decode, 237, 4, 148, 1, // Opcode: DPSUB_S_H -/* 7770 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 7783 -/* 7774 */ MCD_OPC_CheckPredicate, 8, 60, 23, // Skip to: 13726 -/* 7778 */ MCD_OPC_Decode, 238, 4, 149, 1, // Opcode: DPSUB_S_W -/* 7783 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 7796 -/* 7787 */ MCD_OPC_CheckPredicate, 8, 47, 23, // Skip to: 13726 -/* 7791 */ MCD_OPC_Decode, 236, 4, 150, 1, // Opcode: DPSUB_S_D -/* 7796 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 7809 -/* 7800 */ MCD_OPC_CheckPredicate, 8, 34, 23, // Skip to: 13726 -/* 7804 */ MCD_OPC_Decode, 240, 4, 148, 1, // Opcode: DPSUB_U_H -/* 7809 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 7822 -/* 7813 */ MCD_OPC_CheckPredicate, 8, 21, 23, // Skip to: 13726 -/* 7817 */ MCD_OPC_Decode, 241, 4, 149, 1, // Opcode: DPSUB_U_W -/* 7822 */ MCD_OPC_FilterValue, 23, 12, 23, // Skip to: 13726 -/* 7826 */ MCD_OPC_CheckPredicate, 8, 8, 23, // Skip to: 13726 -/* 7830 */ MCD_OPC_Decode, 239, 4, 150, 1, // Opcode: DPSUB_U_D -/* 7835 */ MCD_OPC_FilterValue, 20, 163, 1, // Skip to: 8258 -/* 7839 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 7842 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7855 -/* 7846 */ MCD_OPC_CheckPredicate, 8, 244, 22, // Skip to: 13726 -/* 7850 */ MCD_OPC_Decode, 221, 11, 151, 1, // Opcode: SLD_B -/* 7855 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7868 -/* 7859 */ MCD_OPC_CheckPredicate, 8, 231, 22, // Skip to: 13726 -/* 7863 */ MCD_OPC_Decode, 223, 11, 152, 1, // Opcode: SLD_H -/* 7868 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7881 -/* 7872 */ MCD_OPC_CheckPredicate, 8, 218, 22, // Skip to: 13726 -/* 7876 */ MCD_OPC_Decode, 224, 11, 153, 1, // Opcode: SLD_W -/* 7881 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7894 -/* 7885 */ MCD_OPC_CheckPredicate, 8, 205, 22, // Skip to: 13726 -/* 7889 */ MCD_OPC_Decode, 222, 11, 154, 1, // Opcode: SLD_D -/* 7894 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7907 -/* 7898 */ MCD_OPC_CheckPredicate, 8, 192, 22, // Skip to: 13726 -/* 7902 */ MCD_OPC_Decode, 135, 12, 155, 1, // Opcode: SPLAT_B -/* 7907 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7920 -/* 7911 */ MCD_OPC_CheckPredicate, 8, 179, 22, // Skip to: 13726 -/* 7915 */ MCD_OPC_Decode, 137, 12, 156, 1, // Opcode: SPLAT_H -/* 7920 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7933 -/* 7924 */ MCD_OPC_CheckPredicate, 8, 166, 22, // Skip to: 13726 -/* 7928 */ MCD_OPC_Decode, 138, 12, 157, 1, // Opcode: SPLAT_W -/* 7933 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7946 -/* 7937 */ MCD_OPC_CheckPredicate, 8, 153, 22, // Skip to: 13726 -/* 7941 */ MCD_OPC_Decode, 136, 12, 158, 1, // Opcode: SPLAT_D -/* 7946 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7959 -/* 7950 */ MCD_OPC_CheckPredicate, 8, 140, 22, // Skip to: 13726 -/* 7954 */ MCD_OPC_Decode, 149, 10, 137, 1, // Opcode: PCKEV_B -/* 7959 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7972 -/* 7963 */ MCD_OPC_CheckPredicate, 8, 127, 22, // Skip to: 13726 -/* 7967 */ MCD_OPC_Decode, 151, 10, 138, 1, // Opcode: PCKEV_H -/* 7972 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7985 -/* 7976 */ MCD_OPC_CheckPredicate, 8, 114, 22, // Skip to: 13726 -/* 7980 */ MCD_OPC_Decode, 152, 10, 139, 1, // Opcode: PCKEV_W -/* 7985 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7998 -/* 7989 */ MCD_OPC_CheckPredicate, 8, 101, 22, // Skip to: 13726 -/* 7993 */ MCD_OPC_Decode, 150, 10, 140, 1, // Opcode: PCKEV_D -/* 7998 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 8011 -/* 8002 */ MCD_OPC_CheckPredicate, 8, 88, 22, // Skip to: 13726 -/* 8006 */ MCD_OPC_Decode, 153, 10, 137, 1, // Opcode: PCKOD_B -/* 8011 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 8024 -/* 8015 */ MCD_OPC_CheckPredicate, 8, 75, 22, // Skip to: 13726 -/* 8019 */ MCD_OPC_Decode, 155, 10, 138, 1, // Opcode: PCKOD_H -/* 8024 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 8037 -/* 8028 */ MCD_OPC_CheckPredicate, 8, 62, 22, // Skip to: 13726 -/* 8032 */ MCD_OPC_Decode, 156, 10, 139, 1, // Opcode: PCKOD_W -/* 8037 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 8050 -/* 8041 */ MCD_OPC_CheckPredicate, 8, 49, 22, // Skip to: 13726 -/* 8045 */ MCD_OPC_Decode, 154, 10, 140, 1, // Opcode: PCKOD_D -/* 8050 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 8063 -/* 8054 */ MCD_OPC_CheckPredicate, 8, 36, 22, // Skip to: 13726 -/* 8058 */ MCD_OPC_Decode, 216, 6, 137, 1, // Opcode: ILVL_B -/* 8063 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 8076 -/* 8067 */ MCD_OPC_CheckPredicate, 8, 23, 22, // Skip to: 13726 -/* 8071 */ MCD_OPC_Decode, 218, 6, 138, 1, // Opcode: ILVL_H -/* 8076 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 8089 -/* 8080 */ MCD_OPC_CheckPredicate, 8, 10, 22, // Skip to: 13726 -/* 8084 */ MCD_OPC_Decode, 219, 6, 139, 1, // Opcode: ILVL_W -/* 8089 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 8102 -/* 8093 */ MCD_OPC_CheckPredicate, 8, 253, 21, // Skip to: 13726 -/* 8097 */ MCD_OPC_Decode, 217, 6, 140, 1, // Opcode: ILVL_D -/* 8102 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 8115 -/* 8106 */ MCD_OPC_CheckPredicate, 8, 240, 21, // Skip to: 13726 -/* 8110 */ MCD_OPC_Decode, 224, 6, 137, 1, // Opcode: ILVR_B -/* 8115 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 8128 -/* 8119 */ MCD_OPC_CheckPredicate, 8, 227, 21, // Skip to: 13726 -/* 8123 */ MCD_OPC_Decode, 226, 6, 138, 1, // Opcode: ILVR_H -/* 8128 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 8141 -/* 8132 */ MCD_OPC_CheckPredicate, 8, 214, 21, // Skip to: 13726 -/* 8136 */ MCD_OPC_Decode, 227, 6, 139, 1, // Opcode: ILVR_W -/* 8141 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 8154 -/* 8145 */ MCD_OPC_CheckPredicate, 8, 201, 21, // Skip to: 13726 -/* 8149 */ MCD_OPC_Decode, 225, 6, 140, 1, // Opcode: ILVR_D -/* 8154 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 8167 -/* 8158 */ MCD_OPC_CheckPredicate, 8, 188, 21, // Skip to: 13726 -/* 8162 */ MCD_OPC_Decode, 212, 6, 137, 1, // Opcode: ILVEV_B -/* 8167 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 8180 -/* 8171 */ MCD_OPC_CheckPredicate, 8, 175, 21, // Skip to: 13726 -/* 8175 */ MCD_OPC_Decode, 214, 6, 138, 1, // Opcode: ILVEV_H -/* 8180 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 8193 -/* 8184 */ MCD_OPC_CheckPredicate, 8, 162, 21, // Skip to: 13726 -/* 8188 */ MCD_OPC_Decode, 215, 6, 139, 1, // Opcode: ILVEV_W -/* 8193 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 8206 -/* 8197 */ MCD_OPC_CheckPredicate, 8, 149, 21, // Skip to: 13726 -/* 8201 */ MCD_OPC_Decode, 213, 6, 140, 1, // Opcode: ILVEV_D -/* 8206 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 8219 -/* 8210 */ MCD_OPC_CheckPredicate, 8, 136, 21, // Skip to: 13726 -/* 8214 */ MCD_OPC_Decode, 220, 6, 137, 1, // Opcode: ILVOD_B -/* 8219 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 8232 -/* 8223 */ MCD_OPC_CheckPredicate, 8, 123, 21, // Skip to: 13726 -/* 8227 */ MCD_OPC_Decode, 222, 6, 138, 1, // Opcode: ILVOD_H -/* 8232 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 8245 -/* 8236 */ MCD_OPC_CheckPredicate, 8, 110, 21, // Skip to: 13726 -/* 8240 */ MCD_OPC_Decode, 223, 6, 139, 1, // Opcode: ILVOD_W -/* 8245 */ MCD_OPC_FilterValue, 31, 101, 21, // Skip to: 13726 -/* 8249 */ MCD_OPC_CheckPredicate, 8, 97, 21, // Skip to: 13726 -/* 8253 */ MCD_OPC_Decode, 221, 6, 140, 1, // Opcode: ILVOD_D -/* 8258 */ MCD_OPC_FilterValue, 21, 59, 1, // Skip to: 8577 -/* 8262 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 8265 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8278 -/* 8269 */ MCD_OPC_CheckPredicate, 8, 77, 21, // Skip to: 13726 -/* 8273 */ MCD_OPC_Decode, 227, 13, 141, 1, // Opcode: VSHF_B -/* 8278 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8291 -/* 8282 */ MCD_OPC_CheckPredicate, 8, 64, 21, // Skip to: 13726 -/* 8286 */ MCD_OPC_Decode, 229, 13, 142, 1, // Opcode: VSHF_H -/* 8291 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8304 -/* 8295 */ MCD_OPC_CheckPredicate, 8, 51, 21, // Skip to: 13726 -/* 8299 */ MCD_OPC_Decode, 230, 13, 143, 1, // Opcode: VSHF_W -/* 8304 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 8317 -/* 8308 */ MCD_OPC_CheckPredicate, 8, 38, 21, // Skip to: 13726 -/* 8312 */ MCD_OPC_Decode, 228, 13, 144, 1, // Opcode: VSHF_D -/* 8317 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 8330 -/* 8321 */ MCD_OPC_CheckPredicate, 8, 25, 21, // Skip to: 13726 -/* 8325 */ MCD_OPC_Decode, 148, 12, 137, 1, // Opcode: SRAR_B -/* 8330 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 8343 -/* 8334 */ MCD_OPC_CheckPredicate, 8, 12, 21, // Skip to: 13726 -/* 8338 */ MCD_OPC_Decode, 150, 12, 138, 1, // Opcode: SRAR_H -/* 8343 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 8356 -/* 8347 */ MCD_OPC_CheckPredicate, 8, 255, 20, // Skip to: 13726 -/* 8351 */ MCD_OPC_Decode, 151, 12, 139, 1, // Opcode: SRAR_W -/* 8356 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 8369 -/* 8360 */ MCD_OPC_CheckPredicate, 8, 242, 20, // Skip to: 13726 -/* 8364 */ MCD_OPC_Decode, 149, 12, 140, 1, // Opcode: SRAR_D -/* 8369 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 8382 -/* 8373 */ MCD_OPC_CheckPredicate, 8, 229, 20, // Skip to: 13726 -/* 8377 */ MCD_OPC_Decode, 169, 12, 137, 1, // Opcode: SRLR_B -/* 8382 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 8395 -/* 8386 */ MCD_OPC_CheckPredicate, 8, 216, 20, // Skip to: 13726 -/* 8390 */ MCD_OPC_Decode, 171, 12, 138, 1, // Opcode: SRLR_H -/* 8395 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 8408 -/* 8399 */ MCD_OPC_CheckPredicate, 8, 203, 20, // Skip to: 13726 -/* 8403 */ MCD_OPC_Decode, 172, 12, 139, 1, // Opcode: SRLR_W -/* 8408 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 8421 -/* 8412 */ MCD_OPC_CheckPredicate, 8, 190, 20, // Skip to: 13726 -/* 8416 */ MCD_OPC_Decode, 170, 12, 140, 1, // Opcode: SRLR_D -/* 8421 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 8434 -/* 8425 */ MCD_OPC_CheckPredicate, 8, 177, 20, // Skip to: 13726 -/* 8429 */ MCD_OPC_Decode, 201, 6, 145, 1, // Opcode: HADD_S_H -/* 8434 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 8447 -/* 8438 */ MCD_OPC_CheckPredicate, 8, 164, 20, // Skip to: 13726 -/* 8442 */ MCD_OPC_Decode, 202, 6, 146, 1, // Opcode: HADD_S_W -/* 8447 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 8460 -/* 8451 */ MCD_OPC_CheckPredicate, 8, 151, 20, // Skip to: 13726 -/* 8455 */ MCD_OPC_Decode, 200, 6, 147, 1, // Opcode: HADD_S_D -/* 8460 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 8473 -/* 8464 */ MCD_OPC_CheckPredicate, 8, 138, 20, // Skip to: 13726 -/* 8468 */ MCD_OPC_Decode, 204, 6, 145, 1, // Opcode: HADD_U_H -/* 8473 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 8486 -/* 8477 */ MCD_OPC_CheckPredicate, 8, 125, 20, // Skip to: 13726 -/* 8481 */ MCD_OPC_Decode, 205, 6, 146, 1, // Opcode: HADD_U_W -/* 8486 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 8499 -/* 8490 */ MCD_OPC_CheckPredicate, 8, 112, 20, // Skip to: 13726 -/* 8494 */ MCD_OPC_Decode, 203, 6, 147, 1, // Opcode: HADD_U_D -/* 8499 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 8512 -/* 8503 */ MCD_OPC_CheckPredicate, 8, 99, 20, // Skip to: 13726 -/* 8507 */ MCD_OPC_Decode, 207, 6, 145, 1, // Opcode: HSUB_S_H -/* 8512 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 8525 -/* 8516 */ MCD_OPC_CheckPredicate, 8, 86, 20, // Skip to: 13726 -/* 8520 */ MCD_OPC_Decode, 208, 6, 146, 1, // Opcode: HSUB_S_W -/* 8525 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 8538 -/* 8529 */ MCD_OPC_CheckPredicate, 8, 73, 20, // Skip to: 13726 -/* 8533 */ MCD_OPC_Decode, 206, 6, 147, 1, // Opcode: HSUB_S_D -/* 8538 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 8551 -/* 8542 */ MCD_OPC_CheckPredicate, 8, 60, 20, // Skip to: 13726 -/* 8546 */ MCD_OPC_Decode, 210, 6, 145, 1, // Opcode: HSUB_U_H -/* 8551 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 8564 -/* 8555 */ MCD_OPC_CheckPredicate, 8, 47, 20, // Skip to: 13726 -/* 8559 */ MCD_OPC_Decode, 211, 6, 146, 1, // Opcode: HSUB_U_W -/* 8564 */ MCD_OPC_FilterValue, 31, 38, 20, // Skip to: 13726 -/* 8568 */ MCD_OPC_CheckPredicate, 8, 34, 20, // Skip to: 13726 -/* 8572 */ MCD_OPC_Decode, 209, 6, 147, 1, // Opcode: HSUB_U_D -/* 8577 */ MCD_OPC_FilterValue, 25, 230, 1, // Skip to: 9067 -/* 8581 */ MCD_OPC_ExtractField, 20, 6, // Inst{25-20} ... -/* 8584 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8597 -/* 8588 */ MCD_OPC_CheckPredicate, 8, 14, 20, // Skip to: 13726 -/* 8592 */ MCD_OPC_Decode, 217, 11, 159, 1, // Opcode: SLDI_B -/* 8597 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8616 -/* 8601 */ MCD_OPC_CheckPredicate, 8, 1, 20, // Skip to: 13726 -/* 8605 */ MCD_OPC_CheckField, 19, 1, 0, 251, 19, // Skip to: 13726 -/* 8611 */ MCD_OPC_Decode, 219, 11, 160, 1, // Opcode: SLDI_H -/* 8616 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 8674 -/* 8620 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8623 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8636 -/* 8627 */ MCD_OPC_CheckPredicate, 8, 231, 19, // Skip to: 13726 -/* 8631 */ MCD_OPC_Decode, 220, 11, 161, 1, // Opcode: SLDI_W -/* 8636 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8655 -/* 8640 */ MCD_OPC_CheckPredicate, 8, 218, 19, // Skip to: 13726 -/* 8644 */ MCD_OPC_CheckField, 17, 1, 0, 212, 19, // Skip to: 13726 -/* 8650 */ MCD_OPC_Decode, 218, 11, 162, 1, // Opcode: SLDI_D -/* 8655 */ MCD_OPC_FilterValue, 3, 203, 19, // Skip to: 13726 -/* 8659 */ MCD_OPC_CheckPredicate, 8, 199, 19, // Skip to: 13726 -/* 8663 */ MCD_OPC_CheckField, 16, 2, 2, 193, 19, // Skip to: 13726 -/* 8669 */ MCD_OPC_Decode, 212, 3, 163, 1, // Opcode: CTCMSA -/* 8674 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 8687 -/* 8678 */ MCD_OPC_CheckPredicate, 8, 180, 19, // Skip to: 13726 -/* 8682 */ MCD_OPC_Decode, 131, 12, 164, 1, // Opcode: SPLATI_B -/* 8687 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 8706 -/* 8691 */ MCD_OPC_CheckPredicate, 8, 167, 19, // Skip to: 13726 -/* 8695 */ MCD_OPC_CheckField, 19, 1, 0, 161, 19, // Skip to: 13726 -/* 8701 */ MCD_OPC_Decode, 133, 12, 165, 1, // Opcode: SPLATI_H -/* 8706 */ MCD_OPC_FilterValue, 7, 54, 0, // Skip to: 8764 -/* 8710 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8713 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8726 -/* 8717 */ MCD_OPC_CheckPredicate, 8, 141, 19, // Skip to: 13726 -/* 8721 */ MCD_OPC_Decode, 134, 12, 166, 1, // Opcode: SPLATI_W -/* 8726 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8745 -/* 8730 */ MCD_OPC_CheckPredicate, 8, 128, 19, // Skip to: 13726 -/* 8734 */ MCD_OPC_CheckField, 17, 1, 0, 122, 19, // Skip to: 13726 -/* 8740 */ MCD_OPC_Decode, 132, 12, 167, 1, // Opcode: SPLATI_D -/* 8745 */ MCD_OPC_FilterValue, 3, 113, 19, // Skip to: 13726 -/* 8749 */ MCD_OPC_CheckPredicate, 8, 109, 19, // Skip to: 13726 -/* 8753 */ MCD_OPC_CheckField, 16, 2, 2, 103, 19, // Skip to: 13726 -/* 8759 */ MCD_OPC_Decode, 240, 2, 168, 1, // Opcode: CFCMSA -/* 8764 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 8777 -/* 8768 */ MCD_OPC_CheckPredicate, 8, 90, 19, // Skip to: 13726 -/* 8772 */ MCD_OPC_Decode, 202, 3, 169, 1, // Opcode: COPY_S_B -/* 8777 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 8796 -/* 8781 */ MCD_OPC_CheckPredicate, 8, 77, 19, // Skip to: 13726 -/* 8785 */ MCD_OPC_CheckField, 19, 1, 0, 71, 19, // Skip to: 13726 -/* 8791 */ MCD_OPC_Decode, 204, 3, 170, 1, // Opcode: COPY_S_H -/* 8796 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 8854 -/* 8800 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8803 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8816 -/* 8807 */ MCD_OPC_CheckPredicate, 8, 51, 19, // Skip to: 13726 -/* 8811 */ MCD_OPC_Decode, 205, 3, 171, 1, // Opcode: COPY_S_W -/* 8816 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8835 -/* 8820 */ MCD_OPC_CheckPredicate, 14, 38, 19, // Skip to: 13726 -/* 8824 */ MCD_OPC_CheckField, 17, 1, 0, 32, 19, // Skip to: 13726 -/* 8830 */ MCD_OPC_Decode, 203, 3, 172, 1, // Opcode: COPY_S_D -/* 8835 */ MCD_OPC_FilterValue, 3, 23, 19, // Skip to: 13726 -/* 8839 */ MCD_OPC_CheckPredicate, 8, 19, 19, // Skip to: 13726 -/* 8843 */ MCD_OPC_CheckField, 16, 2, 2, 13, 19, // Skip to: 13726 -/* 8849 */ MCD_OPC_Decode, 235, 8, 173, 1, // Opcode: MOVE_V -/* 8854 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 8867 -/* 8858 */ MCD_OPC_CheckPredicate, 8, 0, 19, // Skip to: 13726 -/* 8862 */ MCD_OPC_Decode, 206, 3, 169, 1, // Opcode: COPY_U_B -/* 8867 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 8886 -/* 8871 */ MCD_OPC_CheckPredicate, 8, 243, 18, // Skip to: 13726 -/* 8875 */ MCD_OPC_CheckField, 19, 1, 0, 237, 18, // Skip to: 13726 -/* 8881 */ MCD_OPC_Decode, 208, 3, 170, 1, // Opcode: COPY_U_H -/* 8886 */ MCD_OPC_FilterValue, 15, 35, 0, // Skip to: 8925 -/* 8890 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8893 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8906 -/* 8897 */ MCD_OPC_CheckPredicate, 8, 217, 18, // Skip to: 13726 -/* 8901 */ MCD_OPC_Decode, 209, 3, 171, 1, // Opcode: COPY_U_W -/* 8906 */ MCD_OPC_FilterValue, 2, 208, 18, // Skip to: 13726 -/* 8910 */ MCD_OPC_CheckPredicate, 14, 204, 18, // Skip to: 13726 -/* 8914 */ MCD_OPC_CheckField, 17, 1, 0, 198, 18, // Skip to: 13726 -/* 8920 */ MCD_OPC_Decode, 207, 3, 172, 1, // Opcode: COPY_U_D -/* 8925 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 8938 -/* 8929 */ MCD_OPC_CheckPredicate, 8, 185, 18, // Skip to: 13726 -/* 8933 */ MCD_OPC_Decode, 229, 6, 174, 1, // Opcode: INSERT_B -/* 8938 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 8957 -/* 8942 */ MCD_OPC_CheckPredicate, 8, 172, 18, // Skip to: 13726 -/* 8946 */ MCD_OPC_CheckField, 19, 1, 0, 166, 18, // Skip to: 13726 -/* 8952 */ MCD_OPC_Decode, 237, 6, 175, 1, // Opcode: INSERT_H -/* 8957 */ MCD_OPC_FilterValue, 19, 35, 0, // Skip to: 8996 -/* 8961 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8964 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8977 -/* 8968 */ MCD_OPC_CheckPredicate, 8, 146, 18, // Skip to: 13726 -/* 8972 */ MCD_OPC_Decode, 239, 6, 176, 1, // Opcode: INSERT_W -/* 8977 */ MCD_OPC_FilterValue, 2, 137, 18, // Skip to: 13726 -/* 8981 */ MCD_OPC_CheckPredicate, 14, 133, 18, // Skip to: 13726 -/* 8985 */ MCD_OPC_CheckField, 17, 1, 0, 127, 18, // Skip to: 13726 -/* 8991 */ MCD_OPC_Decode, 231, 6, 177, 1, // Opcode: INSERT_D -/* 8996 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9009 -/* 9000 */ MCD_OPC_CheckPredicate, 8, 114, 18, // Skip to: 13726 -/* 9004 */ MCD_OPC_Decode, 242, 6, 178, 1, // Opcode: INSVE_B -/* 9009 */ MCD_OPC_FilterValue, 22, 15, 0, // Skip to: 9028 -/* 9013 */ MCD_OPC_CheckPredicate, 8, 101, 18, // Skip to: 13726 -/* 9017 */ MCD_OPC_CheckField, 19, 1, 0, 95, 18, // Skip to: 13726 -/* 9023 */ MCD_OPC_Decode, 244, 6, 178, 1, // Opcode: INSVE_H -/* 9028 */ MCD_OPC_FilterValue, 23, 86, 18, // Skip to: 13726 -/* 9032 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 9035 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9048 -/* 9039 */ MCD_OPC_CheckPredicate, 8, 75, 18, // Skip to: 13726 -/* 9043 */ MCD_OPC_Decode, 245, 6, 178, 1, // Opcode: INSVE_W -/* 9048 */ MCD_OPC_FilterValue, 2, 66, 18, // Skip to: 13726 -/* 9052 */ MCD_OPC_CheckPredicate, 8, 62, 18, // Skip to: 13726 -/* 9056 */ MCD_OPC_CheckField, 17, 1, 0, 56, 18, // Skip to: 13726 -/* 9062 */ MCD_OPC_Decode, 243, 6, 178, 1, // Opcode: INSVE_D -/* 9067 */ MCD_OPC_FilterValue, 26, 163, 1, // Skip to: 9490 -/* 9071 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 9074 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9087 -/* 9078 */ MCD_OPC_CheckPredicate, 8, 36, 18, // Skip to: 13726 -/* 9082 */ MCD_OPC_Decode, 178, 5, 139, 1, // Opcode: FCAF_W -/* 9087 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9100 -/* 9091 */ MCD_OPC_CheckPredicate, 8, 23, 18, // Skip to: 13726 -/* 9095 */ MCD_OPC_Decode, 177, 5, 140, 1, // Opcode: FCAF_D -/* 9100 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9113 -/* 9104 */ MCD_OPC_CheckPredicate, 8, 10, 18, // Skip to: 13726 -/* 9108 */ MCD_OPC_Decode, 205, 5, 139, 1, // Opcode: FCUN_W -/* 9113 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9126 -/* 9117 */ MCD_OPC_CheckPredicate, 8, 253, 17, // Skip to: 13726 -/* 9121 */ MCD_OPC_Decode, 204, 5, 140, 1, // Opcode: FCUN_D -/* 9126 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9139 -/* 9130 */ MCD_OPC_CheckPredicate, 8, 240, 17, // Skip to: 13726 -/* 9134 */ MCD_OPC_Decode, 180, 5, 139, 1, // Opcode: FCEQ_W -/* 9139 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9152 -/* 9143 */ MCD_OPC_CheckPredicate, 8, 227, 17, // Skip to: 13726 -/* 9147 */ MCD_OPC_Decode, 179, 5, 140, 1, // Opcode: FCEQ_D -/* 9152 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9165 -/* 9156 */ MCD_OPC_CheckPredicate, 8, 214, 17, // Skip to: 13726 -/* 9160 */ MCD_OPC_Decode, 197, 5, 139, 1, // Opcode: FCUEQ_W -/* 9165 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9178 -/* 9169 */ MCD_OPC_CheckPredicate, 8, 201, 17, // Skip to: 13726 -/* 9173 */ MCD_OPC_Decode, 196, 5, 140, 1, // Opcode: FCUEQ_D -/* 9178 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9191 -/* 9182 */ MCD_OPC_CheckPredicate, 8, 188, 17, // Skip to: 13726 -/* 9186 */ MCD_OPC_Decode, 186, 5, 139, 1, // Opcode: FCLT_W -/* 9191 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9204 -/* 9195 */ MCD_OPC_CheckPredicate, 8, 175, 17, // Skip to: 13726 -/* 9199 */ MCD_OPC_Decode, 185, 5, 140, 1, // Opcode: FCLT_D -/* 9204 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9217 -/* 9208 */ MCD_OPC_CheckPredicate, 8, 162, 17, // Skip to: 13726 -/* 9212 */ MCD_OPC_Decode, 201, 5, 139, 1, // Opcode: FCULT_W -/* 9217 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9230 -/* 9221 */ MCD_OPC_CheckPredicate, 8, 149, 17, // Skip to: 13726 -/* 9225 */ MCD_OPC_Decode, 200, 5, 140, 1, // Opcode: FCULT_D -/* 9230 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 9243 -/* 9234 */ MCD_OPC_CheckPredicate, 8, 136, 17, // Skip to: 13726 -/* 9238 */ MCD_OPC_Decode, 184, 5, 139, 1, // Opcode: FCLE_W -/* 9243 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 9256 -/* 9247 */ MCD_OPC_CheckPredicate, 8, 123, 17, // Skip to: 13726 -/* 9251 */ MCD_OPC_Decode, 183, 5, 140, 1, // Opcode: FCLE_D -/* 9256 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 9269 -/* 9260 */ MCD_OPC_CheckPredicate, 8, 110, 17, // Skip to: 13726 -/* 9264 */ MCD_OPC_Decode, 199, 5, 139, 1, // Opcode: FCULE_W -/* 9269 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 9282 -/* 9273 */ MCD_OPC_CheckPredicate, 8, 97, 17, // Skip to: 13726 -/* 9277 */ MCD_OPC_Decode, 198, 5, 140, 1, // Opcode: FCULE_D -/* 9282 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 9295 -/* 9286 */ MCD_OPC_CheckPredicate, 8, 84, 17, // Skip to: 13726 -/* 9290 */ MCD_OPC_Decode, 154, 6, 139, 1, // Opcode: FSAF_W -/* 9295 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 9308 -/* 9299 */ MCD_OPC_CheckPredicate, 8, 71, 17, // Skip to: 13726 -/* 9303 */ MCD_OPC_Decode, 153, 6, 140, 1, // Opcode: FSAF_D -/* 9308 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 9321 -/* 9312 */ MCD_OPC_CheckPredicate, 8, 58, 17, // Skip to: 13726 -/* 9316 */ MCD_OPC_Decode, 188, 6, 139, 1, // Opcode: FSUN_W -/* 9321 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 9334 -/* 9325 */ MCD_OPC_CheckPredicate, 8, 45, 17, // Skip to: 13726 -/* 9329 */ MCD_OPC_Decode, 187, 6, 140, 1, // Opcode: FSUN_D -/* 9334 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9347 -/* 9338 */ MCD_OPC_CheckPredicate, 8, 32, 17, // Skip to: 13726 -/* 9342 */ MCD_OPC_Decode, 156, 6, 139, 1, // Opcode: FSEQ_W -/* 9347 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 9360 -/* 9351 */ MCD_OPC_CheckPredicate, 8, 19, 17, // Skip to: 13726 -/* 9355 */ MCD_OPC_Decode, 155, 6, 140, 1, // Opcode: FSEQ_D -/* 9360 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 9373 -/* 9364 */ MCD_OPC_CheckPredicate, 8, 6, 17, // Skip to: 13726 -/* 9368 */ MCD_OPC_Decode, 180, 6, 139, 1, // Opcode: FSUEQ_W -/* 9373 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 9386 -/* 9377 */ MCD_OPC_CheckPredicate, 8, 249, 16, // Skip to: 13726 -/* 9381 */ MCD_OPC_Decode, 179, 6, 140, 1, // Opcode: FSUEQ_D -/* 9386 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 9399 -/* 9390 */ MCD_OPC_CheckPredicate, 8, 236, 16, // Skip to: 13726 -/* 9394 */ MCD_OPC_Decode, 160, 6, 139, 1, // Opcode: FSLT_W -/* 9399 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 9412 -/* 9403 */ MCD_OPC_CheckPredicate, 8, 223, 16, // Skip to: 13726 -/* 9407 */ MCD_OPC_Decode, 159, 6, 140, 1, // Opcode: FSLT_D -/* 9412 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 9425 -/* 9416 */ MCD_OPC_CheckPredicate, 8, 210, 16, // Skip to: 13726 -/* 9420 */ MCD_OPC_Decode, 184, 6, 139, 1, // Opcode: FSULT_W -/* 9425 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 9438 -/* 9429 */ MCD_OPC_CheckPredicate, 8, 197, 16, // Skip to: 13726 -/* 9433 */ MCD_OPC_Decode, 183, 6, 140, 1, // Opcode: FSULT_D -/* 9438 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 9451 -/* 9442 */ MCD_OPC_CheckPredicate, 8, 184, 16, // Skip to: 13726 -/* 9446 */ MCD_OPC_Decode, 158, 6, 139, 1, // Opcode: FSLE_W -/* 9451 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 9464 -/* 9455 */ MCD_OPC_CheckPredicate, 8, 171, 16, // Skip to: 13726 -/* 9459 */ MCD_OPC_Decode, 157, 6, 140, 1, // Opcode: FSLE_D -/* 9464 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 9477 -/* 9468 */ MCD_OPC_CheckPredicate, 8, 158, 16, // Skip to: 13726 -/* 9472 */ MCD_OPC_Decode, 182, 6, 139, 1, // Opcode: FSULE_W -/* 9477 */ MCD_OPC_FilterValue, 31, 149, 16, // Skip to: 13726 -/* 9481 */ MCD_OPC_CheckPredicate, 8, 145, 16, // Skip to: 13726 -/* 9485 */ MCD_OPC_Decode, 181, 6, 140, 1, // Opcode: FSULE_D -/* 9490 */ MCD_OPC_FilterValue, 27, 85, 1, // Skip to: 9835 -/* 9494 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 9497 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9510 -/* 9501 */ MCD_OPC_CheckPredicate, 8, 125, 16, // Skip to: 13726 -/* 9505 */ MCD_OPC_Decode, 176, 5, 139, 1, // Opcode: FADD_W -/* 9510 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9523 -/* 9514 */ MCD_OPC_CheckPredicate, 8, 112, 16, // Skip to: 13726 -/* 9518 */ MCD_OPC_Decode, 170, 5, 140, 1, // Opcode: FADD_D -/* 9523 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9536 -/* 9527 */ MCD_OPC_CheckPredicate, 8, 99, 16, // Skip to: 13726 -/* 9531 */ MCD_OPC_Decode, 178, 6, 139, 1, // Opcode: FSUB_W -/* 9536 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9549 -/* 9540 */ MCD_OPC_CheckPredicate, 8, 86, 16, // Skip to: 13726 -/* 9544 */ MCD_OPC_Decode, 172, 6, 140, 1, // Opcode: FSUB_D -/* 9549 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9562 -/* 9553 */ MCD_OPC_CheckPredicate, 8, 73, 16, // Skip to: 13726 -/* 9557 */ MCD_OPC_Decode, 141, 6, 139, 1, // Opcode: FMUL_W -/* 9562 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9575 -/* 9566 */ MCD_OPC_CheckPredicate, 8, 60, 16, // Skip to: 13726 -/* 9570 */ MCD_OPC_Decode, 135, 6, 140, 1, // Opcode: FMUL_D -/* 9575 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9588 -/* 9579 */ MCD_OPC_CheckPredicate, 8, 47, 16, // Skip to: 13726 -/* 9583 */ MCD_OPC_Decode, 212, 5, 139, 1, // Opcode: FDIV_W -/* 9588 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9601 -/* 9592 */ MCD_OPC_CheckPredicate, 8, 34, 16, // Skip to: 13726 -/* 9596 */ MCD_OPC_Decode, 206, 5, 140, 1, // Opcode: FDIV_D -/* 9601 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9614 -/* 9605 */ MCD_OPC_CheckPredicate, 8, 21, 16, // Skip to: 13726 -/* 9609 */ MCD_OPC_Decode, 247, 5, 143, 1, // Opcode: FMADD_W -/* 9614 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9627 -/* 9618 */ MCD_OPC_CheckPredicate, 8, 8, 16, // Skip to: 13726 -/* 9622 */ MCD_OPC_Decode, 246, 5, 144, 1, // Opcode: FMADD_D -/* 9627 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9640 -/* 9631 */ MCD_OPC_CheckPredicate, 8, 251, 15, // Skip to: 13726 -/* 9635 */ MCD_OPC_Decode, 134, 6, 143, 1, // Opcode: FMSUB_W -/* 9640 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9653 -/* 9644 */ MCD_OPC_CheckPredicate, 8, 238, 15, // Skip to: 13726 -/* 9648 */ MCD_OPC_Decode, 133, 6, 144, 1, // Opcode: FMSUB_D -/* 9653 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 9666 -/* 9657 */ MCD_OPC_CheckPredicate, 8, 225, 15, // Skip to: 13726 -/* 9661 */ MCD_OPC_Decode, 217, 5, 139, 1, // Opcode: FEXP2_W -/* 9666 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 9679 -/* 9670 */ MCD_OPC_CheckPredicate, 8, 212, 15, // Skip to: 13726 -/* 9674 */ MCD_OPC_Decode, 215, 5, 140, 1, // Opcode: FEXP2_D -/* 9679 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 9692 -/* 9683 */ MCD_OPC_CheckPredicate, 8, 199, 15, // Skip to: 13726 -/* 9687 */ MCD_OPC_Decode, 213, 5, 179, 1, // Opcode: FEXDO_H -/* 9692 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 9705 -/* 9696 */ MCD_OPC_CheckPredicate, 8, 186, 15, // Skip to: 13726 -/* 9700 */ MCD_OPC_Decode, 214, 5, 180, 1, // Opcode: FEXDO_W -/* 9705 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9718 -/* 9709 */ MCD_OPC_CheckPredicate, 8, 173, 15, // Skip to: 13726 -/* 9713 */ MCD_OPC_Decode, 193, 6, 179, 1, // Opcode: FTQ_H -/* 9718 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 9731 -/* 9722 */ MCD_OPC_CheckPredicate, 8, 160, 15, // Skip to: 13726 -/* 9726 */ MCD_OPC_Decode, 194, 6, 180, 1, // Opcode: FTQ_W -/* 9731 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 9744 -/* 9735 */ MCD_OPC_CheckPredicate, 8, 147, 15, // Skip to: 13726 -/* 9739 */ MCD_OPC_Decode, 255, 5, 139, 1, // Opcode: FMIN_W -/* 9744 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 9757 -/* 9748 */ MCD_OPC_CheckPredicate, 8, 134, 15, // Skip to: 13726 -/* 9752 */ MCD_OPC_Decode, 254, 5, 140, 1, // Opcode: FMIN_D -/* 9757 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 9770 -/* 9761 */ MCD_OPC_CheckPredicate, 8, 121, 15, // Skip to: 13726 -/* 9765 */ MCD_OPC_Decode, 253, 5, 139, 1, // Opcode: FMIN_A_W -/* 9770 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 9783 -/* 9774 */ MCD_OPC_CheckPredicate, 8, 108, 15, // Skip to: 13726 -/* 9778 */ MCD_OPC_Decode, 252, 5, 140, 1, // Opcode: FMIN_A_D -/* 9783 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 9796 -/* 9787 */ MCD_OPC_CheckPredicate, 8, 95, 15, // Skip to: 13726 -/* 9791 */ MCD_OPC_Decode, 251, 5, 139, 1, // Opcode: FMAX_W -/* 9796 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 9809 -/* 9800 */ MCD_OPC_CheckPredicate, 8, 82, 15, // Skip to: 13726 -/* 9804 */ MCD_OPC_Decode, 250, 5, 140, 1, // Opcode: FMAX_D -/* 9809 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 9822 -/* 9813 */ MCD_OPC_CheckPredicate, 8, 69, 15, // Skip to: 13726 -/* 9817 */ MCD_OPC_Decode, 249, 5, 139, 1, // Opcode: FMAX_A_W -/* 9822 */ MCD_OPC_FilterValue, 31, 60, 15, // Skip to: 13726 -/* 9826 */ MCD_OPC_CheckPredicate, 8, 56, 15, // Skip to: 13726 -/* 9830 */ MCD_OPC_Decode, 248, 5, 140, 1, // Opcode: FMAX_A_D -/* 9835 */ MCD_OPC_FilterValue, 28, 59, 1, // Skip to: 10154 -/* 9839 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 9842 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9855 -/* 9846 */ MCD_OPC_CheckPredicate, 8, 36, 15, // Skip to: 13726 -/* 9850 */ MCD_OPC_Decode, 195, 5, 139, 1, // Opcode: FCOR_W -/* 9855 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9868 -/* 9859 */ MCD_OPC_CheckPredicate, 8, 23, 15, // Skip to: 13726 -/* 9863 */ MCD_OPC_Decode, 194, 5, 140, 1, // Opcode: FCOR_D -/* 9868 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9881 -/* 9872 */ MCD_OPC_CheckPredicate, 8, 10, 15, // Skip to: 13726 -/* 9876 */ MCD_OPC_Decode, 203, 5, 139, 1, // Opcode: FCUNE_W -/* 9881 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9894 -/* 9885 */ MCD_OPC_CheckPredicate, 8, 253, 14, // Skip to: 13726 -/* 9889 */ MCD_OPC_Decode, 202, 5, 140, 1, // Opcode: FCUNE_D -/* 9894 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9907 -/* 9898 */ MCD_OPC_CheckPredicate, 8, 240, 14, // Skip to: 13726 -/* 9902 */ MCD_OPC_Decode, 193, 5, 139, 1, // Opcode: FCNE_W -/* 9907 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9920 -/* 9911 */ MCD_OPC_CheckPredicate, 8, 227, 14, // Skip to: 13726 -/* 9915 */ MCD_OPC_Decode, 192, 5, 140, 1, // Opcode: FCNE_D -/* 9920 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9933 -/* 9924 */ MCD_OPC_CheckPredicate, 8, 214, 14, // Skip to: 13726 -/* 9928 */ MCD_OPC_Decode, 219, 9, 138, 1, // Opcode: MUL_Q_H -/* 9933 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9946 -/* 9937 */ MCD_OPC_CheckPredicate, 8, 201, 14, // Skip to: 13726 -/* 9941 */ MCD_OPC_Decode, 220, 9, 139, 1, // Opcode: MUL_Q_W -/* 9946 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9959 -/* 9950 */ MCD_OPC_CheckPredicate, 8, 188, 14, // Skip to: 13726 -/* 9954 */ MCD_OPC_Decode, 147, 8, 142, 1, // Opcode: MADD_Q_H -/* 9959 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9972 -/* 9963 */ MCD_OPC_CheckPredicate, 8, 175, 14, // Skip to: 13726 -/* 9967 */ MCD_OPC_Decode, 148, 8, 143, 1, // Opcode: MADD_Q_W -/* 9972 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 9985 -/* 9976 */ MCD_OPC_CheckPredicate, 8, 162, 14, // Skip to: 13726 -/* 9980 */ MCD_OPC_Decode, 165, 9, 142, 1, // Opcode: MSUB_Q_H -/* 9985 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 9998 -/* 9989 */ MCD_OPC_CheckPredicate, 8, 149, 14, // Skip to: 13726 -/* 9993 */ MCD_OPC_Decode, 166, 9, 143, 1, // Opcode: MSUB_Q_W -/* 9998 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 10011 -/* 10002 */ MCD_OPC_CheckPredicate, 8, 136, 14, // Skip to: 13726 -/* 10006 */ MCD_OPC_Decode, 164, 6, 139, 1, // Opcode: FSOR_W -/* 10011 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 10024 -/* 10015 */ MCD_OPC_CheckPredicate, 8, 123, 14, // Skip to: 13726 -/* 10019 */ MCD_OPC_Decode, 163, 6, 140, 1, // Opcode: FSOR_D -/* 10024 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 10037 -/* 10028 */ MCD_OPC_CheckPredicate, 8, 110, 14, // Skip to: 13726 -/* 10032 */ MCD_OPC_Decode, 186, 6, 139, 1, // Opcode: FSUNE_W -/* 10037 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 10050 -/* 10041 */ MCD_OPC_CheckPredicate, 8, 97, 14, // Skip to: 13726 -/* 10045 */ MCD_OPC_Decode, 185, 6, 140, 1, // Opcode: FSUNE_D -/* 10050 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 10063 -/* 10054 */ MCD_OPC_CheckPredicate, 8, 84, 14, // Skip to: 13726 -/* 10058 */ MCD_OPC_Decode, 162, 6, 139, 1, // Opcode: FSNE_W -/* 10063 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 10076 -/* 10067 */ MCD_OPC_CheckPredicate, 8, 71, 14, // Skip to: 13726 -/* 10071 */ MCD_OPC_Decode, 161, 6, 140, 1, // Opcode: FSNE_D -/* 10076 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 10089 -/* 10080 */ MCD_OPC_CheckPredicate, 8, 58, 14, // Skip to: 13726 -/* 10084 */ MCD_OPC_Decode, 202, 9, 138, 1, // Opcode: MULR_Q_H -/* 10089 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 10102 -/* 10093 */ MCD_OPC_CheckPredicate, 8, 45, 14, // Skip to: 13726 -/* 10097 */ MCD_OPC_Decode, 203, 9, 139, 1, // Opcode: MULR_Q_W -/* 10102 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 10115 -/* 10106 */ MCD_OPC_CheckPredicate, 8, 32, 14, // Skip to: 13726 -/* 10110 */ MCD_OPC_Decode, 133, 8, 142, 1, // Opcode: MADDR_Q_H -/* 10115 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 10128 -/* 10119 */ MCD_OPC_CheckPredicate, 8, 19, 14, // Skip to: 13726 -/* 10123 */ MCD_OPC_Decode, 134, 8, 143, 1, // Opcode: MADDR_Q_W -/* 10128 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 10141 -/* 10132 */ MCD_OPC_CheckPredicate, 8, 6, 14, // Skip to: 13726 -/* 10136 */ MCD_OPC_Decode, 151, 9, 142, 1, // Opcode: MSUBR_Q_H -/* 10141 */ MCD_OPC_FilterValue, 29, 253, 13, // Skip to: 13726 -/* 10145 */ MCD_OPC_CheckPredicate, 8, 249, 13, // Skip to: 13726 -/* 10149 */ MCD_OPC_Decode, 152, 9, 143, 1, // Opcode: MSUBR_Q_W -/* 10154 */ MCD_OPC_FilterValue, 30, 219, 2, // Skip to: 10889 -/* 10158 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 10161 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10173 -/* 10165 */ MCD_OPC_CheckPredicate, 8, 229, 13, // Skip to: 13726 -/* 10169 */ MCD_OPC_Decode, 89, 137, 1, // Opcode: AND_V -/* 10173 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10186 -/* 10177 */ MCD_OPC_CheckPredicate, 8, 217, 13, // Skip to: 13726 -/* 10181 */ MCD_OPC_Decode, 138, 10, 137, 1, // Opcode: OR_V -/* 10186 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10199 -/* 10190 */ MCD_OPC_CheckPredicate, 8, 204, 13, // Skip to: 13726 -/* 10194 */ MCD_OPC_Decode, 254, 9, 137, 1, // Opcode: NOR_V -/* 10199 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10212 -/* 10203 */ MCD_OPC_CheckPredicate, 8, 191, 13, // Skip to: 13726 -/* 10207 */ MCD_OPC_Decode, 241, 13, 137, 1, // Opcode: XOR_V -/* 10212 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10225 -/* 10216 */ MCD_OPC_CheckPredicate, 8, 178, 13, // Skip to: 13726 -/* 10220 */ MCD_OPC_Decode, 142, 2, 141, 1, // Opcode: BMNZ_V -/* 10225 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10238 -/* 10229 */ MCD_OPC_CheckPredicate, 8, 165, 13, // Skip to: 13726 -/* 10233 */ MCD_OPC_Decode, 144, 2, 141, 1, // Opcode: BMZ_V -/* 10238 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10251 -/* 10242 */ MCD_OPC_CheckPredicate, 8, 152, 13, // Skip to: 13726 -/* 10246 */ MCD_OPC_Decode, 179, 2, 141, 1, // Opcode: BSEL_V -/* 10251 */ MCD_OPC_FilterValue, 24, 211, 0, // Skip to: 10466 -/* 10255 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 10258 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10271 -/* 10262 */ MCD_OPC_CheckPredicate, 8, 132, 13, // Skip to: 13726 -/* 10266 */ MCD_OPC_Decode, 231, 5, 181, 1, // Opcode: FILL_B -/* 10271 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10284 -/* 10275 */ MCD_OPC_CheckPredicate, 8, 119, 13, // Skip to: 13726 -/* 10279 */ MCD_OPC_Decode, 235, 5, 182, 1, // Opcode: FILL_H -/* 10284 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10297 -/* 10288 */ MCD_OPC_CheckPredicate, 8, 106, 13, // Skip to: 13726 -/* 10292 */ MCD_OPC_Decode, 236, 5, 183, 1, // Opcode: FILL_W -/* 10297 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10310 -/* 10301 */ MCD_OPC_CheckPredicate, 14, 93, 13, // Skip to: 13726 -/* 10305 */ MCD_OPC_Decode, 232, 5, 184, 1, // Opcode: FILL_D -/* 10310 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10323 -/* 10314 */ MCD_OPC_CheckPredicate, 8, 80, 13, // Skip to: 13726 -/* 10318 */ MCD_OPC_Decode, 157, 10, 173, 1, // Opcode: PCNT_B -/* 10323 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10336 -/* 10327 */ MCD_OPC_CheckPredicate, 8, 67, 13, // Skip to: 13726 -/* 10331 */ MCD_OPC_Decode, 159, 10, 185, 1, // Opcode: PCNT_H -/* 10336 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10349 -/* 10340 */ MCD_OPC_CheckPredicate, 8, 54, 13, // Skip to: 13726 -/* 10344 */ MCD_OPC_Decode, 160, 10, 186, 1, // Opcode: PCNT_W -/* 10349 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 10362 -/* 10353 */ MCD_OPC_CheckPredicate, 8, 41, 13, // Skip to: 13726 -/* 10357 */ MCD_OPC_Decode, 158, 10, 187, 1, // Opcode: PCNT_D -/* 10362 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 10375 -/* 10366 */ MCD_OPC_CheckPredicate, 8, 28, 13, // Skip to: 13726 -/* 10370 */ MCD_OPC_Decode, 231, 9, 173, 1, // Opcode: NLOC_B -/* 10375 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 10388 -/* 10379 */ MCD_OPC_CheckPredicate, 8, 15, 13, // Skip to: 13726 -/* 10383 */ MCD_OPC_Decode, 233, 9, 185, 1, // Opcode: NLOC_H -/* 10388 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 10401 -/* 10392 */ MCD_OPC_CheckPredicate, 8, 2, 13, // Skip to: 13726 -/* 10396 */ MCD_OPC_Decode, 234, 9, 186, 1, // Opcode: NLOC_W -/* 10401 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 10414 -/* 10405 */ MCD_OPC_CheckPredicate, 8, 245, 12, // Skip to: 13726 -/* 10409 */ MCD_OPC_Decode, 232, 9, 187, 1, // Opcode: NLOC_D -/* 10414 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 10427 -/* 10418 */ MCD_OPC_CheckPredicate, 8, 232, 12, // Skip to: 13726 -/* 10422 */ MCD_OPC_Decode, 235, 9, 173, 1, // Opcode: NLZC_B -/* 10427 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 10440 -/* 10431 */ MCD_OPC_CheckPredicate, 8, 219, 12, // Skip to: 13726 -/* 10435 */ MCD_OPC_Decode, 237, 9, 185, 1, // Opcode: NLZC_H -/* 10440 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 10453 -/* 10444 */ MCD_OPC_CheckPredicate, 8, 206, 12, // Skip to: 13726 -/* 10448 */ MCD_OPC_Decode, 238, 9, 186, 1, // Opcode: NLZC_W -/* 10453 */ MCD_OPC_FilterValue, 15, 197, 12, // Skip to: 13726 -/* 10457 */ MCD_OPC_CheckPredicate, 8, 193, 12, // Skip to: 13726 -/* 10461 */ MCD_OPC_Decode, 236, 9, 187, 1, // Opcode: NLZC_D -/* 10466 */ MCD_OPC_FilterValue, 25, 184, 12, // Skip to: 13726 -/* 10470 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 10473 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10486 -/* 10477 */ MCD_OPC_CheckPredicate, 8, 173, 12, // Skip to: 13726 -/* 10481 */ MCD_OPC_Decode, 182, 5, 186, 1, // Opcode: FCLASS_W -/* 10486 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10499 -/* 10490 */ MCD_OPC_CheckPredicate, 8, 160, 12, // Skip to: 13726 -/* 10494 */ MCD_OPC_Decode, 181, 5, 187, 1, // Opcode: FCLASS_D -/* 10499 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10512 -/* 10503 */ MCD_OPC_CheckPredicate, 8, 147, 12, // Skip to: 13726 -/* 10507 */ MCD_OPC_Decode, 196, 6, 186, 1, // Opcode: FTRUNC_S_W -/* 10512 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10525 -/* 10516 */ MCD_OPC_CheckPredicate, 8, 134, 12, // Skip to: 13726 -/* 10520 */ MCD_OPC_Decode, 195, 6, 187, 1, // Opcode: FTRUNC_S_D -/* 10525 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10538 -/* 10529 */ MCD_OPC_CheckPredicate, 8, 121, 12, // Skip to: 13726 -/* 10533 */ MCD_OPC_Decode, 198, 6, 186, 1, // Opcode: FTRUNC_U_W -/* 10538 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10551 -/* 10542 */ MCD_OPC_CheckPredicate, 8, 108, 12, // Skip to: 13726 -/* 10546 */ MCD_OPC_Decode, 197, 6, 187, 1, // Opcode: FTRUNC_U_D -/* 10551 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10564 -/* 10555 */ MCD_OPC_CheckPredicate, 8, 95, 12, // Skip to: 13726 -/* 10559 */ MCD_OPC_Decode, 171, 6, 186, 1, // Opcode: FSQRT_W -/* 10564 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 10577 -/* 10568 */ MCD_OPC_CheckPredicate, 8, 82, 12, // Skip to: 13726 -/* 10572 */ MCD_OPC_Decode, 165, 6, 187, 1, // Opcode: FSQRT_D -/* 10577 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 10590 -/* 10581 */ MCD_OPC_CheckPredicate, 8, 69, 12, // Skip to: 13726 -/* 10585 */ MCD_OPC_Decode, 152, 6, 186, 1, // Opcode: FRSQRT_W -/* 10590 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 10603 -/* 10594 */ MCD_OPC_CheckPredicate, 8, 56, 12, // Skip to: 13726 -/* 10598 */ MCD_OPC_Decode, 151, 6, 187, 1, // Opcode: FRSQRT_D -/* 10603 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 10616 -/* 10607 */ MCD_OPC_CheckPredicate, 8, 43, 12, // Skip to: 13726 -/* 10611 */ MCD_OPC_Decode, 148, 6, 186, 1, // Opcode: FRCP_W -/* 10616 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 10629 -/* 10620 */ MCD_OPC_CheckPredicate, 8, 30, 12, // Skip to: 13726 -/* 10624 */ MCD_OPC_Decode, 147, 6, 187, 1, // Opcode: FRCP_D -/* 10629 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 10642 -/* 10633 */ MCD_OPC_CheckPredicate, 8, 17, 12, // Skip to: 13726 -/* 10637 */ MCD_OPC_Decode, 150, 6, 186, 1, // Opcode: FRINT_W -/* 10642 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 10655 -/* 10646 */ MCD_OPC_CheckPredicate, 8, 4, 12, // Skip to: 13726 -/* 10650 */ MCD_OPC_Decode, 149, 6, 187, 1, // Opcode: FRINT_D -/* 10655 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 10668 -/* 10659 */ MCD_OPC_CheckPredicate, 8, 247, 11, // Skip to: 13726 -/* 10663 */ MCD_OPC_Decode, 238, 5, 186, 1, // Opcode: FLOG2_W -/* 10668 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 10681 -/* 10672 */ MCD_OPC_CheckPredicate, 8, 234, 11, // Skip to: 13726 -/* 10676 */ MCD_OPC_Decode, 237, 5, 187, 1, // Opcode: FLOG2_D -/* 10681 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 10694 -/* 10685 */ MCD_OPC_CheckPredicate, 8, 221, 11, // Skip to: 13726 -/* 10689 */ MCD_OPC_Decode, 220, 5, 188, 1, // Opcode: FEXUPL_W -/* 10694 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 10707 -/* 10698 */ MCD_OPC_CheckPredicate, 8, 208, 11, // Skip to: 13726 -/* 10702 */ MCD_OPC_Decode, 219, 5, 189, 1, // Opcode: FEXUPL_D -/* 10707 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 10720 -/* 10711 */ MCD_OPC_CheckPredicate, 8, 195, 11, // Skip to: 13726 -/* 10715 */ MCD_OPC_Decode, 222, 5, 188, 1, // Opcode: FEXUPR_W -/* 10720 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 10733 -/* 10724 */ MCD_OPC_CheckPredicate, 8, 182, 11, // Skip to: 13726 -/* 10728 */ MCD_OPC_Decode, 221, 5, 189, 1, // Opcode: FEXUPR_D -/* 10733 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 10746 -/* 10737 */ MCD_OPC_CheckPredicate, 8, 169, 11, // Skip to: 13726 -/* 10741 */ MCD_OPC_Decode, 228, 5, 188, 1, // Opcode: FFQL_W -/* 10746 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 10759 -/* 10750 */ MCD_OPC_CheckPredicate, 8, 156, 11, // Skip to: 13726 -/* 10754 */ MCD_OPC_Decode, 227, 5, 189, 1, // Opcode: FFQL_D -/* 10759 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 10772 -/* 10763 */ MCD_OPC_CheckPredicate, 8, 143, 11, // Skip to: 13726 -/* 10767 */ MCD_OPC_Decode, 230, 5, 188, 1, // Opcode: FFQR_W -/* 10772 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 10785 -/* 10776 */ MCD_OPC_CheckPredicate, 8, 130, 11, // Skip to: 13726 -/* 10780 */ MCD_OPC_Decode, 229, 5, 189, 1, // Opcode: FFQR_D -/* 10785 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 10798 -/* 10789 */ MCD_OPC_CheckPredicate, 8, 117, 11, // Skip to: 13726 -/* 10793 */ MCD_OPC_Decode, 190, 6, 186, 1, // Opcode: FTINT_S_W -/* 10798 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 10811 -/* 10802 */ MCD_OPC_CheckPredicate, 8, 104, 11, // Skip to: 13726 -/* 10806 */ MCD_OPC_Decode, 189, 6, 187, 1, // Opcode: FTINT_S_D -/* 10811 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 10824 -/* 10815 */ MCD_OPC_CheckPredicate, 8, 91, 11, // Skip to: 13726 -/* 10819 */ MCD_OPC_Decode, 192, 6, 186, 1, // Opcode: FTINT_U_W -/* 10824 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 10837 -/* 10828 */ MCD_OPC_CheckPredicate, 8, 78, 11, // Skip to: 13726 -/* 10832 */ MCD_OPC_Decode, 191, 6, 187, 1, // Opcode: FTINT_U_D -/* 10837 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 10850 -/* 10841 */ MCD_OPC_CheckPredicate, 8, 65, 11, // Skip to: 13726 -/* 10845 */ MCD_OPC_Decode, 224, 5, 186, 1, // Opcode: FFINT_S_W -/* 10850 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 10863 -/* 10854 */ MCD_OPC_CheckPredicate, 8, 52, 11, // Skip to: 13726 -/* 10858 */ MCD_OPC_Decode, 223, 5, 187, 1, // Opcode: FFINT_S_D -/* 10863 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 10876 -/* 10867 */ MCD_OPC_CheckPredicate, 8, 39, 11, // Skip to: 13726 -/* 10871 */ MCD_OPC_Decode, 226, 5, 186, 1, // Opcode: FFINT_U_W -/* 10876 */ MCD_OPC_FilterValue, 31, 30, 11, // Skip to: 13726 -/* 10880 */ MCD_OPC_CheckPredicate, 8, 26, 11, // Skip to: 13726 -/* 10884 */ MCD_OPC_Decode, 225, 5, 187, 1, // Opcode: FFINT_U_D -/* 10889 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 10902 -/* 10893 */ MCD_OPC_CheckPredicate, 8, 13, 11, // Skip to: 13726 -/* 10897 */ MCD_OPC_Decode, 177, 7, 190, 1, // Opcode: LD_B -/* 10902 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 10915 -/* 10906 */ MCD_OPC_CheckPredicate, 8, 0, 11, // Skip to: 13726 -/* 10910 */ MCD_OPC_Decode, 179, 7, 190, 1, // Opcode: LD_H -/* 10915 */ MCD_OPC_FilterValue, 34, 9, 0, // Skip to: 10928 -/* 10919 */ MCD_OPC_CheckPredicate, 8, 243, 10, // Skip to: 13726 -/* 10923 */ MCD_OPC_Decode, 180, 7, 190, 1, // Opcode: LD_W -/* 10928 */ MCD_OPC_FilterValue, 35, 9, 0, // Skip to: 10941 -/* 10932 */ MCD_OPC_CheckPredicate, 8, 230, 10, // Skip to: 13726 -/* 10936 */ MCD_OPC_Decode, 178, 7, 190, 1, // Opcode: LD_D -/* 10941 */ MCD_OPC_FilterValue, 36, 9, 0, // Skip to: 10954 -/* 10945 */ MCD_OPC_CheckPredicate, 8, 217, 10, // Skip to: 13726 -/* 10949 */ MCD_OPC_Decode, 186, 12, 190, 1, // Opcode: ST_B -/* 10954 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 10967 -/* 10958 */ MCD_OPC_CheckPredicate, 8, 204, 10, // Skip to: 13726 -/* 10962 */ MCD_OPC_Decode, 188, 12, 190, 1, // Opcode: ST_H -/* 10967 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 10980 -/* 10971 */ MCD_OPC_CheckPredicate, 8, 191, 10, // Skip to: 13726 -/* 10975 */ MCD_OPC_Decode, 189, 12, 190, 1, // Opcode: ST_W -/* 10980 */ MCD_OPC_FilterValue, 39, 182, 10, // Skip to: 13726 -/* 10984 */ MCD_OPC_CheckPredicate, 8, 178, 10, // Skip to: 13726 -/* 10988 */ MCD_OPC_Decode, 187, 12, 190, 1, // Opcode: ST_D -/* 10993 */ MCD_OPC_FilterValue, 31, 113, 9, // Skip to: 13414 -/* 10997 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 11000 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11013 -/* 11004 */ MCD_OPC_CheckPredicate, 6, 158, 10, // Skip to: 13726 -/* 11008 */ MCD_OPC_Decode, 145, 5, 191, 1, // Opcode: EXT -/* 11013 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11026 -/* 11017 */ MCD_OPC_CheckPredicate, 6, 145, 10, // Skip to: 13726 -/* 11021 */ MCD_OPC_Decode, 228, 6, 192, 1, // Opcode: INS -/* 11026 */ MCD_OPC_FilterValue, 10, 42, 0, // Skip to: 11072 -/* 11030 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 11033 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11046 -/* 11037 */ MCD_OPC_CheckPredicate, 12, 125, 10, // Skip to: 13726 -/* 11041 */ MCD_OPC_Decode, 236, 7, 193, 1, // Opcode: LWX -/* 11046 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11059 -/* 11050 */ MCD_OPC_CheckPredicate, 12, 112, 10, // Skip to: 13726 -/* 11054 */ MCD_OPC_Decode, 187, 7, 193, 1, // Opcode: LHX -/* 11059 */ MCD_OPC_FilterValue, 6, 103, 10, // Skip to: 13726 -/* 11063 */ MCD_OPC_CheckPredicate, 12, 99, 10, // Skip to: 13726 -/* 11067 */ MCD_OPC_Decode, 156, 7, 193, 1, // Opcode: LBUX -/* 11072 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 11091 -/* 11076 */ MCD_OPC_CheckPredicate, 12, 86, 10, // Skip to: 13726 -/* 11080 */ MCD_OPC_CheckField, 6, 10, 0, 80, 10, // Skip to: 13726 -/* 11086 */ MCD_OPC_Decode, 241, 6, 194, 1, // Opcode: INSV -/* 11091 */ MCD_OPC_FilterValue, 16, 51, 1, // Skip to: 11402 -/* 11095 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 11098 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11110 -/* 11102 */ MCD_OPC_CheckPredicate, 12, 60, 10, // Skip to: 13726 -/* 11106 */ MCD_OPC_Decode, 56, 195, 1, // Opcode: ADDU_QB -/* 11110 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 11123 -/* 11114 */ MCD_OPC_CheckPredicate, 12, 48, 10, // Skip to: 13726 -/* 11118 */ MCD_OPC_Decode, 218, 12, 195, 1, // Opcode: SUBU_QB -/* 11123 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 11135 -/* 11127 */ MCD_OPC_CheckPredicate, 12, 35, 10, // Skip to: 13726 -/* 11131 */ MCD_OPC_Decode, 58, 195, 1, // Opcode: ADDU_S_QB -/* 11135 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 11148 -/* 11139 */ MCD_OPC_CheckPredicate, 12, 23, 10, // Skip to: 13726 -/* 11143 */ MCD_OPC_Decode, 220, 12, 195, 1, // Opcode: SUBU_S_QB -/* 11148 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 11161 -/* 11152 */ MCD_OPC_CheckPredicate, 12, 10, 10, // Skip to: 13726 -/* 11156 */ MCD_OPC_Decode, 196, 9, 195, 1, // Opcode: MULEU_S_PH_QBL -/* 11161 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 11174 -/* 11165 */ MCD_OPC_CheckPredicate, 12, 253, 9, // Skip to: 13726 -/* 11169 */ MCD_OPC_Decode, 197, 9, 195, 1, // Opcode: MULEU_S_PH_QBR -/* 11174 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 11186 -/* 11178 */ MCD_OPC_CheckPredicate, 30, 240, 9, // Skip to: 13726 -/* 11182 */ MCD_OPC_Decode, 55, 195, 1, // Opcode: ADDU_PH -/* 11186 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 11199 -/* 11190 */ MCD_OPC_CheckPredicate, 30, 228, 9, // Skip to: 13726 -/* 11194 */ MCD_OPC_Decode, 217, 12, 195, 1, // Opcode: SUBU_PH -/* 11199 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 11211 -/* 11203 */ MCD_OPC_CheckPredicate, 12, 215, 9, // Skip to: 13726 -/* 11207 */ MCD_OPC_Decode, 36, 195, 1, // Opcode: ADDQ_PH -/* 11211 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 11224 -/* 11215 */ MCD_OPC_CheckPredicate, 12, 203, 9, // Skip to: 13726 -/* 11219 */ MCD_OPC_Decode, 195, 12, 195, 1, // Opcode: SUBQ_PH -/* 11224 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 11236 -/* 11228 */ MCD_OPC_CheckPredicate, 30, 190, 9, // Skip to: 13726 -/* 11232 */ MCD_OPC_Decode, 57, 195, 1, // Opcode: ADDU_S_PH -/* 11236 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 11249 -/* 11240 */ MCD_OPC_CheckPredicate, 30, 178, 9, // Skip to: 13726 -/* 11244 */ MCD_OPC_Decode, 219, 12, 195, 1, // Opcode: SUBU_S_PH -/* 11249 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 11261 -/* 11253 */ MCD_OPC_CheckPredicate, 12, 165, 9, // Skip to: 13726 -/* 11257 */ MCD_OPC_Decode, 37, 195, 1, // Opcode: ADDQ_S_PH -/* 11261 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 11274 -/* 11265 */ MCD_OPC_CheckPredicate, 12, 153, 9, // Skip to: 13726 -/* 11269 */ MCD_OPC_Decode, 196, 12, 195, 1, // Opcode: SUBQ_S_PH -/* 11274 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 11285 -/* 11278 */ MCD_OPC_CheckPredicate, 12, 140, 9, // Skip to: 13726 -/* 11282 */ MCD_OPC_Decode, 39, 35, // Opcode: ADDSC -/* 11285 */ MCD_OPC_FilterValue, 17, 7, 0, // Skip to: 11296 -/* 11289 */ MCD_OPC_CheckPredicate, 12, 129, 9, // Skip to: 13726 -/* 11293 */ MCD_OPC_Decode, 67, 35, // Opcode: ADDWC -/* 11296 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 11308 -/* 11300 */ MCD_OPC_CheckPredicate, 12, 118, 9, // Skip to: 13726 -/* 11304 */ MCD_OPC_Decode, 223, 8, 35, // Opcode: MODSUB -/* 11308 */ MCD_OPC_FilterValue, 20, 15, 0, // Skip to: 11327 -/* 11312 */ MCD_OPC_CheckPredicate, 12, 106, 9, // Skip to: 13726 -/* 11316 */ MCD_OPC_CheckField, 16, 5, 0, 100, 9, // Skip to: 13726 -/* 11322 */ MCD_OPC_Decode, 236, 10, 196, 1, // Opcode: RADDU_W_QB -/* 11327 */ MCD_OPC_FilterValue, 22, 7, 0, // Skip to: 11338 -/* 11331 */ MCD_OPC_CheckPredicate, 12, 87, 9, // Skip to: 13726 -/* 11335 */ MCD_OPC_Decode, 38, 35, // Opcode: ADDQ_S_W -/* 11338 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 11350 -/* 11342 */ MCD_OPC_CheckPredicate, 12, 76, 9, // Skip to: 13726 -/* 11346 */ MCD_OPC_Decode, 197, 12, 35, // Opcode: SUBQ_S_W -/* 11350 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 11363 -/* 11354 */ MCD_OPC_CheckPredicate, 12, 64, 9, // Skip to: 13726 -/* 11358 */ MCD_OPC_Decode, 194, 9, 197, 1, // Opcode: MULEQ_S_W_PHL -/* 11363 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 11376 -/* 11367 */ MCD_OPC_CheckPredicate, 12, 51, 9, // Skip to: 13726 -/* 11371 */ MCD_OPC_Decode, 195, 9, 197, 1, // Opcode: MULEQ_S_W_PHR -/* 11376 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 11389 -/* 11380 */ MCD_OPC_CheckPredicate, 30, 38, 9, // Skip to: 13726 -/* 11384 */ MCD_OPC_Decode, 200, 9, 195, 1, // Opcode: MULQ_S_PH -/* 11389 */ MCD_OPC_FilterValue, 31, 29, 9, // Skip to: 13726 -/* 11393 */ MCD_OPC_CheckPredicate, 12, 25, 9, // Skip to: 13726 -/* 11397 */ MCD_OPC_Decode, 198, 9, 195, 1, // Opcode: MULQ_RS_PH -/* 11402 */ MCD_OPC_FilterValue, 17, 69, 1, // Skip to: 11731 -/* 11406 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 11409 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 11428 -/* 11413 */ MCD_OPC_CheckPredicate, 12, 5, 9, // Skip to: 13726 -/* 11417 */ MCD_OPC_CheckField, 11, 5, 0, 255, 8, // Skip to: 13726 -/* 11423 */ MCD_OPC_Decode, 161, 3, 198, 1, // Opcode: CMPU_EQ_QB -/* 11428 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 11447 -/* 11432 */ MCD_OPC_CheckPredicate, 12, 242, 8, // Skip to: 13726 -/* 11436 */ MCD_OPC_CheckField, 11, 5, 0, 236, 8, // Skip to: 13726 -/* 11442 */ MCD_OPC_Decode, 163, 3, 198, 1, // Opcode: CMPU_LT_QB -/* 11447 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 11466 -/* 11451 */ MCD_OPC_CheckPredicate, 12, 223, 8, // Skip to: 13726 -/* 11455 */ MCD_OPC_CheckField, 11, 5, 0, 217, 8, // Skip to: 13726 -/* 11461 */ MCD_OPC_Decode, 162, 3, 198, 1, // Opcode: CMPU_LE_QB -/* 11466 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11479 -/* 11470 */ MCD_OPC_CheckPredicate, 12, 204, 8, // Skip to: 13726 -/* 11474 */ MCD_OPC_Decode, 162, 10, 195, 1, // Opcode: PICK_QB -/* 11479 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11492 -/* 11483 */ MCD_OPC_CheckPredicate, 12, 191, 8, // Skip to: 13726 -/* 11487 */ MCD_OPC_Decode, 158, 3, 197, 1, // Opcode: CMPGU_EQ_QB -/* 11492 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 11505 -/* 11496 */ MCD_OPC_CheckPredicate, 12, 178, 8, // Skip to: 13726 -/* 11500 */ MCD_OPC_Decode, 160, 3, 197, 1, // Opcode: CMPGU_LT_QB -/* 11505 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 11518 -/* 11509 */ MCD_OPC_CheckPredicate, 12, 165, 8, // Skip to: 13726 -/* 11513 */ MCD_OPC_Decode, 159, 3, 197, 1, // Opcode: CMPGU_LE_QB -/* 11518 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 11537 -/* 11522 */ MCD_OPC_CheckPredicate, 12, 152, 8, // Skip to: 13726 -/* 11526 */ MCD_OPC_CheckField, 11, 5, 0, 146, 8, // Skip to: 13726 -/* 11532 */ MCD_OPC_Decode, 165, 3, 198, 1, // Opcode: CMP_EQ_PH -/* 11537 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 11556 -/* 11541 */ MCD_OPC_CheckPredicate, 12, 133, 8, // Skip to: 13726 -/* 11545 */ MCD_OPC_CheckField, 11, 5, 0, 127, 8, // Skip to: 13726 -/* 11551 */ MCD_OPC_Decode, 173, 3, 198, 1, // Opcode: CMP_LT_PH -/* 11556 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 11575 -/* 11560 */ MCD_OPC_CheckPredicate, 12, 114, 8, // Skip to: 13726 -/* 11564 */ MCD_OPC_CheckField, 11, 5, 0, 108, 8, // Skip to: 13726 -/* 11570 */ MCD_OPC_Decode, 170, 3, 198, 1, // Opcode: CMP_LE_PH -/* 11575 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 11588 -/* 11579 */ MCD_OPC_CheckPredicate, 12, 95, 8, // Skip to: 13726 -/* 11583 */ MCD_OPC_Decode, 161, 10, 195, 1, // Opcode: PICK_PH -/* 11588 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 11601 -/* 11592 */ MCD_OPC_CheckPredicate, 12, 82, 8, // Skip to: 13726 -/* 11596 */ MCD_OPC_Decode, 176, 10, 195, 1, // Opcode: PRECRQ_QB_PH -/* 11601 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 11614 -/* 11605 */ MCD_OPC_CheckPredicate, 30, 69, 8, // Skip to: 13726 -/* 11609 */ MCD_OPC_Decode, 178, 10, 195, 1, // Opcode: PRECR_QB_PH -/* 11614 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 11627 -/* 11618 */ MCD_OPC_CheckPredicate, 12, 56, 8, // Skip to: 13726 -/* 11622 */ MCD_OPC_Decode, 146, 10, 195, 1, // Opcode: PACKRL_PH -/* 11627 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 11640 -/* 11631 */ MCD_OPC_CheckPredicate, 12, 43, 8, // Skip to: 13726 -/* 11635 */ MCD_OPC_Decode, 174, 10, 195, 1, // Opcode: PRECRQU_S_QB_PH -/* 11640 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 11653 -/* 11644 */ MCD_OPC_CheckPredicate, 12, 30, 8, // Skip to: 13726 -/* 11648 */ MCD_OPC_Decode, 175, 10, 199, 1, // Opcode: PRECRQ_PH_W -/* 11653 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 11666 -/* 11657 */ MCD_OPC_CheckPredicate, 12, 17, 8, // Skip to: 13726 -/* 11661 */ MCD_OPC_Decode, 177, 10, 199, 1, // Opcode: PRECRQ_RS_PH_W -/* 11666 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 11679 -/* 11670 */ MCD_OPC_CheckPredicate, 30, 4, 8, // Skip to: 13726 -/* 11674 */ MCD_OPC_Decode, 155, 3, 197, 1, // Opcode: CMPGDU_EQ_QB -/* 11679 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 11692 -/* 11683 */ MCD_OPC_CheckPredicate, 30, 247, 7, // Skip to: 13726 -/* 11687 */ MCD_OPC_Decode, 157, 3, 197, 1, // Opcode: CMPGDU_LT_QB -/* 11692 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 11705 -/* 11696 */ MCD_OPC_CheckPredicate, 30, 234, 7, // Skip to: 13726 -/* 11700 */ MCD_OPC_Decode, 156, 3, 197, 1, // Opcode: CMPGDU_LE_QB -/* 11705 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 11718 -/* 11709 */ MCD_OPC_CheckPredicate, 30, 221, 7, // Skip to: 13726 -/* 11713 */ MCD_OPC_Decode, 179, 10, 200, 1, // Opcode: PRECR_SRA_PH_W -/* 11718 */ MCD_OPC_FilterValue, 31, 212, 7, // Skip to: 13726 -/* 11722 */ MCD_OPC_CheckPredicate, 30, 208, 7, // Skip to: 13726 -/* 11726 */ MCD_OPC_Decode, 180, 10, 200, 1, // Opcode: PRECR_SRA_R_PH_W -/* 11731 */ MCD_OPC_FilterValue, 18, 74, 1, // Skip to: 12065 -/* 11735 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 11738 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11756 -/* 11742 */ MCD_OPC_CheckPredicate, 30, 188, 7, // Skip to: 13726 -/* 11746 */ MCD_OPC_CheckField, 21, 5, 0, 182, 7, // Skip to: 13726 -/* 11752 */ MCD_OPC_Decode, 23, 201, 1, // Opcode: ABSQ_S_QB -/* 11756 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11769 -/* 11760 */ MCD_OPC_CheckPredicate, 12, 170, 7, // Skip to: 13726 -/* 11764 */ MCD_OPC_Decode, 244, 10, 202, 1, // Opcode: REPL_QB -/* 11769 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 11788 -/* 11773 */ MCD_OPC_CheckPredicate, 12, 157, 7, // Skip to: 13726 -/* 11777 */ MCD_OPC_CheckField, 21, 5, 0, 151, 7, // Skip to: 13726 -/* 11783 */ MCD_OPC_Decode, 242, 10, 203, 1, // Opcode: REPLV_QB -/* 11788 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 11807 -/* 11792 */ MCD_OPC_CheckPredicate, 12, 138, 7, // Skip to: 13726 -/* 11796 */ MCD_OPC_CheckField, 21, 5, 0, 132, 7, // Skip to: 13726 -/* 11802 */ MCD_OPC_Decode, 164, 10, 201, 1, // Opcode: PRECEQU_PH_QBL -/* 11807 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 11826 -/* 11811 */ MCD_OPC_CheckPredicate, 12, 119, 7, // Skip to: 13726 -/* 11815 */ MCD_OPC_CheckField, 21, 5, 0, 113, 7, // Skip to: 13726 -/* 11821 */ MCD_OPC_Decode, 166, 10, 201, 1, // Opcode: PRECEQU_PH_QBR -/* 11826 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 11845 -/* 11830 */ MCD_OPC_CheckPredicate, 12, 100, 7, // Skip to: 13726 -/* 11834 */ MCD_OPC_CheckField, 21, 5, 0, 94, 7, // Skip to: 13726 -/* 11840 */ MCD_OPC_Decode, 165, 10, 201, 1, // Opcode: PRECEQU_PH_QBLA -/* 11845 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 11864 -/* 11849 */ MCD_OPC_CheckPredicate, 12, 81, 7, // Skip to: 13726 -/* 11853 */ MCD_OPC_CheckField, 21, 5, 0, 75, 7, // Skip to: 13726 -/* 11859 */ MCD_OPC_Decode, 167, 10, 201, 1, // Opcode: PRECEQU_PH_QBRA -/* 11864 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 11882 -/* 11868 */ MCD_OPC_CheckPredicate, 12, 62, 7, // Skip to: 13726 -/* 11872 */ MCD_OPC_CheckField, 21, 5, 0, 56, 7, // Skip to: 13726 -/* 11878 */ MCD_OPC_Decode, 22, 201, 1, // Opcode: ABSQ_S_PH -/* 11882 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 11895 -/* 11886 */ MCD_OPC_CheckPredicate, 12, 44, 7, // Skip to: 13726 -/* 11890 */ MCD_OPC_Decode, 243, 10, 202, 1, // Opcode: REPL_PH -/* 11895 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 11914 -/* 11899 */ MCD_OPC_CheckPredicate, 12, 31, 7, // Skip to: 13726 -/* 11903 */ MCD_OPC_CheckField, 21, 5, 0, 25, 7, // Skip to: 13726 -/* 11909 */ MCD_OPC_Decode, 241, 10, 203, 1, // Opcode: REPLV_PH -/* 11914 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 11933 -/* 11918 */ MCD_OPC_CheckPredicate, 12, 12, 7, // Skip to: 13726 -/* 11922 */ MCD_OPC_CheckField, 21, 5, 0, 6, 7, // Skip to: 13726 -/* 11928 */ MCD_OPC_Decode, 168, 10, 204, 1, // Opcode: PRECEQ_W_PHL -/* 11933 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 11952 -/* 11937 */ MCD_OPC_CheckPredicate, 12, 249, 6, // Skip to: 13726 -/* 11941 */ MCD_OPC_CheckField, 21, 5, 0, 243, 6, // Skip to: 13726 -/* 11947 */ MCD_OPC_Decode, 169, 10, 204, 1, // Opcode: PRECEQ_W_PHR -/* 11952 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 11970 -/* 11956 */ MCD_OPC_CheckPredicate, 12, 230, 6, // Skip to: 13726 -/* 11960 */ MCD_OPC_CheckField, 21, 5, 0, 224, 6, // Skip to: 13726 -/* 11966 */ MCD_OPC_Decode, 24, 205, 1, // Opcode: ABSQ_S_W -/* 11970 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 11989 -/* 11974 */ MCD_OPC_CheckPredicate, 12, 212, 6, // Skip to: 13726 -/* 11978 */ MCD_OPC_CheckField, 21, 5, 0, 206, 6, // Skip to: 13726 -/* 11984 */ MCD_OPC_Decode, 249, 1, 205, 1, // Opcode: BITREV -/* 11989 */ MCD_OPC_FilterValue, 28, 15, 0, // Skip to: 12008 -/* 11993 */ MCD_OPC_CheckPredicate, 12, 193, 6, // Skip to: 13726 -/* 11997 */ MCD_OPC_CheckField, 21, 5, 0, 187, 6, // Skip to: 13726 -/* 12003 */ MCD_OPC_Decode, 170, 10, 201, 1, // Opcode: PRECEU_PH_QBL -/* 12008 */ MCD_OPC_FilterValue, 29, 15, 0, // Skip to: 12027 -/* 12012 */ MCD_OPC_CheckPredicate, 12, 174, 6, // Skip to: 13726 -/* 12016 */ MCD_OPC_CheckField, 21, 5, 0, 168, 6, // Skip to: 13726 -/* 12022 */ MCD_OPC_Decode, 172, 10, 201, 1, // Opcode: PRECEU_PH_QBR -/* 12027 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 12046 -/* 12031 */ MCD_OPC_CheckPredicate, 12, 155, 6, // Skip to: 13726 -/* 12035 */ MCD_OPC_CheckField, 21, 5, 0, 149, 6, // Skip to: 13726 -/* 12041 */ MCD_OPC_Decode, 171, 10, 201, 1, // Opcode: PRECEU_PH_QBLA -/* 12046 */ MCD_OPC_FilterValue, 31, 140, 6, // Skip to: 13726 -/* 12050 */ MCD_OPC_CheckPredicate, 12, 136, 6, // Skip to: 13726 -/* 12054 */ MCD_OPC_CheckField, 21, 5, 0, 130, 6, // Skip to: 13726 -/* 12060 */ MCD_OPC_Decode, 173, 10, 201, 1, // Opcode: PRECEU_PH_QBRA -/* 12065 */ MCD_OPC_FilterValue, 19, 31, 1, // Skip to: 12356 -/* 12069 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 12072 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12085 -/* 12076 */ MCD_OPC_CheckPredicate, 12, 110, 6, // Skip to: 13726 -/* 12080 */ MCD_OPC_Decode, 199, 11, 206, 1, // Opcode: SHLL_QB -/* 12085 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12098 -/* 12089 */ MCD_OPC_CheckPredicate, 12, 97, 6, // Skip to: 13726 -/* 12093 */ MCD_OPC_Decode, 215, 11, 206, 1, // Opcode: SHRL_QB -/* 12098 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12111 -/* 12102 */ MCD_OPC_CheckPredicate, 12, 84, 6, // Skip to: 13726 -/* 12106 */ MCD_OPC_Decode, 195, 11, 207, 1, // Opcode: SHLLV_QB -/* 12111 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12124 -/* 12115 */ MCD_OPC_CheckPredicate, 12, 71, 6, // Skip to: 13726 -/* 12119 */ MCD_OPC_Decode, 213, 11, 207, 1, // Opcode: SHRLV_QB -/* 12124 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12137 -/* 12128 */ MCD_OPC_CheckPredicate, 30, 58, 6, // Skip to: 13726 -/* 12132 */ MCD_OPC_Decode, 208, 11, 206, 1, // Opcode: SHRA_QB -/* 12137 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 12150 -/* 12141 */ MCD_OPC_CheckPredicate, 30, 45, 6, // Skip to: 13726 -/* 12145 */ MCD_OPC_Decode, 210, 11, 206, 1, // Opcode: SHRA_R_QB -/* 12150 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 12163 -/* 12154 */ MCD_OPC_CheckPredicate, 30, 32, 6, // Skip to: 13726 -/* 12158 */ MCD_OPC_Decode, 203, 11, 207, 1, // Opcode: SHRAV_QB -/* 12163 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 12176 -/* 12167 */ MCD_OPC_CheckPredicate, 30, 19, 6, // Skip to: 13726 -/* 12171 */ MCD_OPC_Decode, 205, 11, 207, 1, // Opcode: SHRAV_R_QB -/* 12176 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 12189 -/* 12180 */ MCD_OPC_CheckPredicate, 12, 6, 6, // Skip to: 13726 -/* 12184 */ MCD_OPC_Decode, 198, 11, 206, 1, // Opcode: SHLL_PH -/* 12189 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 12202 -/* 12193 */ MCD_OPC_CheckPredicate, 12, 249, 5, // Skip to: 13726 -/* 12197 */ MCD_OPC_Decode, 207, 11, 206, 1, // Opcode: SHRA_PH -/* 12202 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 12215 -/* 12206 */ MCD_OPC_CheckPredicate, 12, 236, 5, // Skip to: 13726 -/* 12210 */ MCD_OPC_Decode, 194, 11, 207, 1, // Opcode: SHLLV_PH -/* 12215 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 12228 -/* 12219 */ MCD_OPC_CheckPredicate, 12, 223, 5, // Skip to: 13726 -/* 12223 */ MCD_OPC_Decode, 202, 11, 207, 1, // Opcode: SHRAV_PH -/* 12228 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 12241 -/* 12232 */ MCD_OPC_CheckPredicate, 12, 210, 5, // Skip to: 13726 -/* 12236 */ MCD_OPC_Decode, 200, 11, 206, 1, // Opcode: SHLL_S_PH -/* 12241 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 12254 -/* 12245 */ MCD_OPC_CheckPredicate, 12, 197, 5, // Skip to: 13726 -/* 12249 */ MCD_OPC_Decode, 209, 11, 206, 1, // Opcode: SHRA_R_PH -/* 12254 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 12267 -/* 12258 */ MCD_OPC_CheckPredicate, 12, 184, 5, // Skip to: 13726 -/* 12262 */ MCD_OPC_Decode, 196, 11, 207, 1, // Opcode: SHLLV_S_PH -/* 12267 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 12280 -/* 12271 */ MCD_OPC_CheckPredicate, 12, 171, 5, // Skip to: 13726 -/* 12275 */ MCD_OPC_Decode, 204, 11, 207, 1, // Opcode: SHRAV_R_PH -/* 12280 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 12293 -/* 12284 */ MCD_OPC_CheckPredicate, 12, 158, 5, // Skip to: 13726 -/* 12288 */ MCD_OPC_Decode, 201, 11, 208, 1, // Opcode: SHLL_S_W -/* 12293 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 12306 -/* 12297 */ MCD_OPC_CheckPredicate, 12, 145, 5, // Skip to: 13726 -/* 12301 */ MCD_OPC_Decode, 211, 11, 208, 1, // Opcode: SHRA_R_W -/* 12306 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 12318 -/* 12310 */ MCD_OPC_CheckPredicate, 12, 132, 5, // Skip to: 13726 -/* 12314 */ MCD_OPC_Decode, 197, 11, 36, // Opcode: SHLLV_S_W -/* 12318 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 12330 -/* 12322 */ MCD_OPC_CheckPredicate, 12, 120, 5, // Skip to: 13726 -/* 12326 */ MCD_OPC_Decode, 206, 11, 36, // Opcode: SHRAV_R_W -/* 12330 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 12343 -/* 12334 */ MCD_OPC_CheckPredicate, 30, 108, 5, // Skip to: 13726 -/* 12338 */ MCD_OPC_Decode, 214, 11, 206, 1, // Opcode: SHRL_PH -/* 12343 */ MCD_OPC_FilterValue, 27, 99, 5, // Skip to: 13726 -/* 12347 */ MCD_OPC_CheckPredicate, 30, 95, 5, // Skip to: 13726 -/* 12351 */ MCD_OPC_Decode, 212, 11, 207, 1, // Opcode: SHRLV_PH -/* 12356 */ MCD_OPC_FilterValue, 24, 199, 0, // Skip to: 12559 -/* 12360 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 12363 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 12375 -/* 12367 */ MCD_OPC_CheckPredicate, 30, 75, 5, // Skip to: 13726 -/* 12371 */ MCD_OPC_Decode, 53, 195, 1, // Opcode: ADDUH_QB -/* 12375 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12388 -/* 12379 */ MCD_OPC_CheckPredicate, 30, 63, 5, // Skip to: 13726 -/* 12383 */ MCD_OPC_Decode, 215, 12, 195, 1, // Opcode: SUBUH_QB -/* 12388 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 12400 -/* 12392 */ MCD_OPC_CheckPredicate, 30, 50, 5, // Skip to: 13726 -/* 12396 */ MCD_OPC_Decode, 54, 195, 1, // Opcode: ADDUH_R_QB -/* 12400 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12413 -/* 12404 */ MCD_OPC_CheckPredicate, 30, 38, 5, // Skip to: 13726 -/* 12408 */ MCD_OPC_Decode, 216, 12, 195, 1, // Opcode: SUBUH_R_QB -/* 12413 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 12425 -/* 12417 */ MCD_OPC_CheckPredicate, 30, 25, 5, // Skip to: 13726 -/* 12421 */ MCD_OPC_Decode, 32, 195, 1, // Opcode: ADDQH_PH -/* 12425 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 12438 -/* 12429 */ MCD_OPC_CheckPredicate, 30, 13, 5, // Skip to: 13726 -/* 12433 */ MCD_OPC_Decode, 191, 12, 195, 1, // Opcode: SUBQH_PH -/* 12438 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 12450 -/* 12442 */ MCD_OPC_CheckPredicate, 30, 0, 5, // Skip to: 13726 -/* 12446 */ MCD_OPC_Decode, 33, 195, 1, // Opcode: ADDQH_R_PH -/* 12450 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 12463 -/* 12454 */ MCD_OPC_CheckPredicate, 30, 244, 4, // Skip to: 13726 -/* 12458 */ MCD_OPC_Decode, 192, 12, 195, 1, // Opcode: SUBQH_R_PH -/* 12463 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 12476 -/* 12467 */ MCD_OPC_CheckPredicate, 30, 231, 4, // Skip to: 13726 -/* 12471 */ MCD_OPC_Decode, 218, 9, 195, 1, // Opcode: MUL_PH -/* 12476 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 12489 -/* 12480 */ MCD_OPC_CheckPredicate, 30, 218, 4, // Skip to: 13726 -/* 12484 */ MCD_OPC_Decode, 222, 9, 195, 1, // Opcode: MUL_S_PH -/* 12489 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 12500 -/* 12493 */ MCD_OPC_CheckPredicate, 30, 205, 4, // Skip to: 13726 -/* 12497 */ MCD_OPC_Decode, 35, 35, // Opcode: ADDQH_W -/* 12500 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 12512 -/* 12504 */ MCD_OPC_CheckPredicate, 30, 194, 4, // Skip to: 13726 -/* 12508 */ MCD_OPC_Decode, 194, 12, 35, // Opcode: SUBQH_W -/* 12512 */ MCD_OPC_FilterValue, 18, 7, 0, // Skip to: 12523 -/* 12516 */ MCD_OPC_CheckPredicate, 30, 182, 4, // Skip to: 13726 -/* 12520 */ MCD_OPC_Decode, 34, 35, // Opcode: ADDQH_R_W -/* 12523 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 12535 -/* 12527 */ MCD_OPC_CheckPredicate, 30, 171, 4, // Skip to: 13726 -/* 12531 */ MCD_OPC_Decode, 193, 12, 35, // Opcode: SUBQH_R_W -/* 12535 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 12547 -/* 12539 */ MCD_OPC_CheckPredicate, 30, 159, 4, // Skip to: 13726 -/* 12543 */ MCD_OPC_Decode, 201, 9, 35, // Opcode: MULQ_S_W -/* 12547 */ MCD_OPC_FilterValue, 23, 151, 4, // Skip to: 13726 -/* 12551 */ MCD_OPC_CheckPredicate, 30, 147, 4, // Skip to: 13726 -/* 12555 */ MCD_OPC_Decode, 199, 9, 35, // Opcode: MULQ_RS_W -/* 12559 */ MCD_OPC_FilterValue, 32, 60, 0, // Skip to: 12623 -/* 12563 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 12566 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 12585 -/* 12570 */ MCD_OPC_CheckPredicate, 6, 128, 4, // Skip to: 13726 -/* 12574 */ MCD_OPC_CheckField, 21, 5, 0, 122, 4, // Skip to: 13726 -/* 12580 */ MCD_OPC_Decode, 234, 13, 205, 1, // Opcode: WSBH -/* 12585 */ MCD_OPC_FilterValue, 16, 15, 0, // Skip to: 12604 -/* 12589 */ MCD_OPC_CheckPredicate, 6, 109, 4, // Skip to: 13726 -/* 12593 */ MCD_OPC_CheckField, 21, 5, 0, 103, 4, // Skip to: 13726 -/* 12599 */ MCD_OPC_Decode, 168, 11, 205, 1, // Opcode: SEB -/* 12604 */ MCD_OPC_FilterValue, 24, 94, 4, // Skip to: 13726 -/* 12608 */ MCD_OPC_CheckPredicate, 6, 90, 4, // Skip to: 13726 -/* 12612 */ MCD_OPC_CheckField, 21, 5, 0, 84, 4, // Skip to: 13726 -/* 12618 */ MCD_OPC_Decode, 171, 11, 205, 1, // Opcode: SEH -/* 12623 */ MCD_OPC_FilterValue, 48, 143, 1, // Skip to: 13026 -/* 12627 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 12630 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12648 -/* 12634 */ MCD_OPC_CheckPredicate, 30, 64, 4, // Skip to: 13726 -/* 12638 */ MCD_OPC_CheckField, 13, 3, 0, 58, 4, // Skip to: 13726 -/* 12644 */ MCD_OPC_Decode, 230, 4, 116, // Opcode: DPA_W_PH -/* 12648 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12666 -/* 12652 */ MCD_OPC_CheckPredicate, 30, 46, 4, // Skip to: 13726 -/* 12656 */ MCD_OPC_CheckField, 13, 3, 0, 40, 4, // Skip to: 13726 -/* 12662 */ MCD_OPC_Decode, 245, 4, 116, // Opcode: DPS_W_PH -/* 12666 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12684 -/* 12670 */ MCD_OPC_CheckPredicate, 30, 28, 4, // Skip to: 13726 -/* 12674 */ MCD_OPC_CheckField, 13, 3, 0, 22, 4, // Skip to: 13726 -/* 12680 */ MCD_OPC_Decode, 205, 9, 116, // Opcode: MULSA_W_PH -/* 12684 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 12702 -/* 12688 */ MCD_OPC_CheckPredicate, 12, 10, 4, // Skip to: 13726 -/* 12692 */ MCD_OPC_CheckField, 13, 3, 0, 4, 4, // Skip to: 13726 -/* 12698 */ MCD_OPC_Decode, 227, 4, 116, // Opcode: DPAU_H_QBL -/* 12702 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 12720 -/* 12706 */ MCD_OPC_CheckPredicate, 12, 248, 3, // Skip to: 13726 -/* 12710 */ MCD_OPC_CheckField, 13, 3, 0, 242, 3, // Skip to: 13726 -/* 12716 */ MCD_OPC_Decode, 226, 4, 116, // Opcode: DPAQ_S_W_PH -/* 12720 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 12738 -/* 12724 */ MCD_OPC_CheckPredicate, 12, 230, 3, // Skip to: 13726 -/* 12728 */ MCD_OPC_CheckField, 13, 3, 0, 224, 3, // Skip to: 13726 -/* 12734 */ MCD_OPC_Decode, 235, 4, 116, // Opcode: DPSQ_S_W_PH -/* 12738 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 12756 -/* 12742 */ MCD_OPC_CheckPredicate, 12, 212, 3, // Skip to: 13726 -/* 12746 */ MCD_OPC_CheckField, 13, 3, 0, 206, 3, // Skip to: 13726 -/* 12752 */ MCD_OPC_Decode, 204, 9, 116, // Opcode: MULSAQ_S_W_PH -/* 12756 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 12774 -/* 12760 */ MCD_OPC_CheckPredicate, 12, 194, 3, // Skip to: 13726 -/* 12764 */ MCD_OPC_CheckField, 13, 3, 0, 188, 3, // Skip to: 13726 -/* 12770 */ MCD_OPC_Decode, 228, 4, 116, // Opcode: DPAU_H_QBR -/* 12774 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 12792 -/* 12778 */ MCD_OPC_CheckPredicate, 30, 176, 3, // Skip to: 13726 -/* 12782 */ MCD_OPC_CheckField, 13, 3, 0, 170, 3, // Skip to: 13726 -/* 12788 */ MCD_OPC_Decode, 229, 4, 116, // Opcode: DPAX_W_PH -/* 12792 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 12810 -/* 12796 */ MCD_OPC_CheckPredicate, 30, 158, 3, // Skip to: 13726 -/* 12800 */ MCD_OPC_CheckField, 13, 3, 0, 152, 3, // Skip to: 13726 -/* 12806 */ MCD_OPC_Decode, 244, 4, 116, // Opcode: DPSX_W_PH -/* 12810 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 12828 -/* 12814 */ MCD_OPC_CheckPredicate, 12, 140, 3, // Skip to: 13726 -/* 12818 */ MCD_OPC_CheckField, 13, 3, 0, 134, 3, // Skip to: 13726 -/* 12824 */ MCD_OPC_Decode, 242, 4, 116, // Opcode: DPSU_H_QBL -/* 12828 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 12846 -/* 12832 */ MCD_OPC_CheckPredicate, 12, 122, 3, // Skip to: 13726 -/* 12836 */ MCD_OPC_CheckField, 13, 3, 0, 116, 3, // Skip to: 13726 -/* 12842 */ MCD_OPC_Decode, 225, 4, 116, // Opcode: DPAQ_SA_L_W -/* 12846 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 12864 -/* 12850 */ MCD_OPC_CheckPredicate, 12, 104, 3, // Skip to: 13726 -/* 12854 */ MCD_OPC_CheckField, 13, 3, 0, 98, 3, // Skip to: 13726 -/* 12860 */ MCD_OPC_Decode, 234, 4, 116, // Opcode: DPSQ_SA_L_W -/* 12864 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 12882 -/* 12868 */ MCD_OPC_CheckPredicate, 12, 86, 3, // Skip to: 13726 -/* 12872 */ MCD_OPC_CheckField, 13, 3, 0, 80, 3, // Skip to: 13726 -/* 12878 */ MCD_OPC_Decode, 243, 4, 116, // Opcode: DPSU_H_QBR -/* 12882 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 12900 -/* 12886 */ MCD_OPC_CheckPredicate, 12, 68, 3, // Skip to: 13726 -/* 12890 */ MCD_OPC_CheckField, 13, 3, 0, 62, 3, // Skip to: 13726 -/* 12896 */ MCD_OPC_Decode, 151, 8, 116, // Opcode: MAQ_SA_W_PHL -/* 12900 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 12918 -/* 12904 */ MCD_OPC_CheckPredicate, 12, 50, 3, // Skip to: 13726 -/* 12908 */ MCD_OPC_CheckField, 13, 3, 0, 44, 3, // Skip to: 13726 -/* 12914 */ MCD_OPC_Decode, 152, 8, 116, // Opcode: MAQ_SA_W_PHR -/* 12918 */ MCD_OPC_FilterValue, 20, 14, 0, // Skip to: 12936 -/* 12922 */ MCD_OPC_CheckPredicate, 12, 32, 3, // Skip to: 13726 -/* 12926 */ MCD_OPC_CheckField, 13, 3, 0, 26, 3, // Skip to: 13726 -/* 12932 */ MCD_OPC_Decode, 153, 8, 116, // Opcode: MAQ_S_W_PHL -/* 12936 */ MCD_OPC_FilterValue, 22, 14, 0, // Skip to: 12954 -/* 12940 */ MCD_OPC_CheckPredicate, 12, 14, 3, // Skip to: 13726 -/* 12944 */ MCD_OPC_CheckField, 13, 3, 0, 8, 3, // Skip to: 13726 -/* 12950 */ MCD_OPC_Decode, 154, 8, 116, // Opcode: MAQ_S_W_PHR -/* 12954 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 12972 -/* 12958 */ MCD_OPC_CheckPredicate, 30, 252, 2, // Skip to: 13726 -/* 12962 */ MCD_OPC_CheckField, 13, 3, 0, 246, 2, // Skip to: 13726 -/* 12968 */ MCD_OPC_Decode, 224, 4, 116, // Opcode: DPAQX_S_W_PH -/* 12972 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 12990 -/* 12976 */ MCD_OPC_CheckPredicate, 30, 234, 2, // Skip to: 13726 -/* 12980 */ MCD_OPC_CheckField, 13, 3, 0, 228, 2, // Skip to: 13726 -/* 12986 */ MCD_OPC_Decode, 233, 4, 116, // Opcode: DPSQX_S_W_PH -/* 12990 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 13008 -/* 12994 */ MCD_OPC_CheckPredicate, 30, 216, 2, // Skip to: 13726 -/* 12998 */ MCD_OPC_CheckField, 13, 3, 0, 210, 2, // Skip to: 13726 -/* 13004 */ MCD_OPC_Decode, 223, 4, 116, // Opcode: DPAQX_SA_W_PH -/* 13008 */ MCD_OPC_FilterValue, 27, 202, 2, // Skip to: 13726 -/* 13012 */ MCD_OPC_CheckPredicate, 30, 198, 2, // Skip to: 13726 -/* 13016 */ MCD_OPC_CheckField, 13, 3, 0, 192, 2, // Skip to: 13726 -/* 13022 */ MCD_OPC_Decode, 232, 4, 116, // Opcode: DPSQX_SA_W_PH -/* 13026 */ MCD_OPC_FilterValue, 49, 41, 0, // Skip to: 13071 -/* 13030 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 13033 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13045 -/* 13037 */ MCD_OPC_CheckPredicate, 30, 173, 2, // Skip to: 13726 -/* 13041 */ MCD_OPC_Decode, 96, 209, 1, // Opcode: APPEND -/* 13045 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13058 -/* 13049 */ MCD_OPC_CheckPredicate, 30, 161, 2, // Skip to: 13726 -/* 13053 */ MCD_OPC_Decode, 184, 10, 209, 1, // Opcode: PREPEND -/* 13058 */ MCD_OPC_FilterValue, 16, 152, 2, // Skip to: 13726 -/* 13062 */ MCD_OPC_CheckPredicate, 30, 148, 2, // Skip to: 13726 -/* 13066 */ MCD_OPC_Decode, 169, 1, 209, 1, // Opcode: BALIGN -/* 13071 */ MCD_OPC_FilterValue, 56, 58, 1, // Skip to: 13389 -/* 13075 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 13078 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13097 -/* 13082 */ MCD_OPC_CheckPredicate, 12, 128, 2, // Skip to: 13726 -/* 13086 */ MCD_OPC_CheckField, 13, 3, 0, 122, 2, // Skip to: 13726 -/* 13092 */ MCD_OPC_Decode, 157, 5, 210, 1, // Opcode: EXTR_W -/* 13097 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 13116 -/* 13101 */ MCD_OPC_CheckPredicate, 12, 109, 2, // Skip to: 13726 -/* 13105 */ MCD_OPC_CheckField, 13, 3, 0, 103, 2, // Skip to: 13726 -/* 13111 */ MCD_OPC_Decode, 153, 5, 211, 1, // Opcode: EXTRV_W -/* 13116 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 13135 -/* 13120 */ MCD_OPC_CheckPredicate, 12, 90, 2, // Skip to: 13726 -/* 13124 */ MCD_OPC_CheckField, 13, 3, 0, 84, 2, // Skip to: 13726 -/* 13130 */ MCD_OPC_Decode, 146, 5, 210, 1, // Opcode: EXTP -/* 13135 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 13154 -/* 13139 */ MCD_OPC_CheckPredicate, 12, 71, 2, // Skip to: 13726 -/* 13143 */ MCD_OPC_CheckField, 13, 3, 0, 65, 2, // Skip to: 13726 -/* 13149 */ MCD_OPC_Decode, 149, 5, 211, 1, // Opcode: EXTPV -/* 13154 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 13173 -/* 13158 */ MCD_OPC_CheckPredicate, 12, 52, 2, // Skip to: 13726 -/* 13162 */ MCD_OPC_CheckField, 13, 3, 0, 46, 2, // Skip to: 13726 -/* 13168 */ MCD_OPC_Decode, 155, 5, 210, 1, // Opcode: EXTR_R_W -/* 13173 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 13192 -/* 13177 */ MCD_OPC_CheckPredicate, 12, 33, 2, // Skip to: 13726 -/* 13181 */ MCD_OPC_CheckField, 13, 3, 0, 27, 2, // Skip to: 13726 -/* 13187 */ MCD_OPC_Decode, 151, 5, 211, 1, // Opcode: EXTRV_R_W -/* 13192 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 13211 -/* 13196 */ MCD_OPC_CheckPredicate, 12, 14, 2, // Skip to: 13726 -/* 13200 */ MCD_OPC_CheckField, 13, 3, 0, 8, 2, // Skip to: 13726 -/* 13206 */ MCD_OPC_Decode, 154, 5, 210, 1, // Opcode: EXTR_RS_W -/* 13211 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 13230 -/* 13215 */ MCD_OPC_CheckPredicate, 12, 251, 1, // Skip to: 13726 -/* 13219 */ MCD_OPC_CheckField, 13, 3, 0, 245, 1, // Skip to: 13726 -/* 13225 */ MCD_OPC_Decode, 150, 5, 211, 1, // Opcode: EXTRV_RS_W -/* 13230 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 13249 -/* 13234 */ MCD_OPC_CheckPredicate, 12, 232, 1, // Skip to: 13726 -/* 13238 */ MCD_OPC_CheckField, 13, 3, 0, 226, 1, // Skip to: 13726 -/* 13244 */ MCD_OPC_Decode, 147, 5, 210, 1, // Opcode: EXTPDP -/* 13249 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 13268 -/* 13253 */ MCD_OPC_CheckPredicate, 12, 213, 1, // Skip to: 13726 -/* 13257 */ MCD_OPC_CheckField, 13, 3, 0, 207, 1, // Skip to: 13726 -/* 13263 */ MCD_OPC_Decode, 148, 5, 211, 1, // Opcode: EXTPDPV -/* 13268 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 13287 -/* 13272 */ MCD_OPC_CheckPredicate, 12, 194, 1, // Skip to: 13726 -/* 13276 */ MCD_OPC_CheckField, 13, 3, 0, 188, 1, // Skip to: 13726 -/* 13282 */ MCD_OPC_Decode, 156, 5, 210, 1, // Opcode: EXTR_S_H -/* 13287 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 13306 -/* 13291 */ MCD_OPC_CheckPredicate, 12, 175, 1, // Skip to: 13726 -/* 13295 */ MCD_OPC_CheckField, 13, 3, 0, 169, 1, // Skip to: 13726 -/* 13301 */ MCD_OPC_Decode, 152, 5, 211, 1, // Opcode: EXTRV_S_H -/* 13306 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 13319 -/* 13310 */ MCD_OPC_CheckPredicate, 12, 156, 1, // Skip to: 13726 -/* 13314 */ MCD_OPC_Decode, 237, 10, 212, 1, // Opcode: RDDSP -/* 13319 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 13332 -/* 13323 */ MCD_OPC_CheckPredicate, 12, 143, 1, // Skip to: 13726 -/* 13327 */ MCD_OPC_Decode, 233, 13, 213, 1, // Opcode: WRDSP -/* 13332 */ MCD_OPC_FilterValue, 26, 15, 0, // Skip to: 13351 -/* 13336 */ MCD_OPC_CheckPredicate, 12, 130, 1, // Skip to: 13726 -/* 13340 */ MCD_OPC_CheckField, 13, 7, 0, 124, 1, // Skip to: 13726 -/* 13346 */ MCD_OPC_Decode, 192, 11, 214, 1, // Opcode: SHILO -/* 13351 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 13370 -/* 13355 */ MCD_OPC_CheckPredicate, 12, 111, 1, // Skip to: 13726 -/* 13359 */ MCD_OPC_CheckField, 13, 8, 0, 105, 1, // Skip to: 13726 -/* 13365 */ MCD_OPC_Decode, 193, 11, 215, 1, // Opcode: SHILOV -/* 13370 */ MCD_OPC_FilterValue, 31, 96, 1, // Skip to: 13726 -/* 13374 */ MCD_OPC_CheckPredicate, 12, 92, 1, // Skip to: 13726 -/* 13378 */ MCD_OPC_CheckField, 13, 8, 0, 86, 1, // Skip to: 13726 -/* 13384 */ MCD_OPC_Decode, 180, 9, 215, 1, // Opcode: MTHLIP -/* 13389 */ MCD_OPC_FilterValue, 59, 77, 1, // Skip to: 13726 -/* 13393 */ MCD_OPC_CheckPredicate, 5, 73, 1, // Skip to: 13726 -/* 13397 */ MCD_OPC_CheckField, 21, 5, 0, 67, 1, // Skip to: 13726 -/* 13403 */ MCD_OPC_CheckField, 6, 5, 0, 61, 1, // Skip to: 13726 -/* 13409 */ MCD_OPC_Decode, 238, 10, 216, 1, // Opcode: RDHWR -/* 13414 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 13427 -/* 13418 */ MCD_OPC_CheckPredicate, 5, 48, 1, // Skip to: 13726 -/* 13422 */ MCD_OPC_Decode, 153, 7, 217, 1, // Opcode: LB -/* 13427 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 13440 -/* 13431 */ MCD_OPC_CheckPredicate, 5, 35, 1, // Skip to: 13726 -/* 13435 */ MCD_OPC_Decode, 184, 7, 217, 1, // Opcode: LH -/* 13440 */ MCD_OPC_FilterValue, 34, 9, 0, // Skip to: 13453 -/* 13444 */ MCD_OPC_CheckPredicate, 11, 22, 1, // Skip to: 13726 -/* 13448 */ MCD_OPC_Decode, 222, 7, 217, 1, // Opcode: LWL -/* 13453 */ MCD_OPC_FilterValue, 35, 9, 0, // Skip to: 13466 -/* 13457 */ MCD_OPC_CheckPredicate, 1, 9, 1, // Skip to: 13726 -/* 13461 */ MCD_OPC_Decode, 213, 7, 217, 1, // Opcode: LW -/* 13466 */ MCD_OPC_FilterValue, 36, 9, 0, // Skip to: 13479 -/* 13470 */ MCD_OPC_CheckPredicate, 5, 252, 0, // Skip to: 13726 -/* 13474 */ MCD_OPC_Decode, 158, 7, 217, 1, // Opcode: LBu -/* 13479 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 13492 -/* 13483 */ MCD_OPC_CheckPredicate, 5, 239, 0, // Skip to: 13726 -/* 13487 */ MCD_OPC_Decode, 189, 7, 217, 1, // Opcode: LHu -/* 13492 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 13505 -/* 13496 */ MCD_OPC_CheckPredicate, 11, 226, 0, // Skip to: 13726 -/* 13500 */ MCD_OPC_Decode, 230, 7, 217, 1, // Opcode: LWR -/* 13505 */ MCD_OPC_FilterValue, 40, 9, 0, // Skip to: 13518 -/* 13509 */ MCD_OPC_CheckPredicate, 5, 213, 0, // Skip to: 13726 -/* 13513 */ MCD_OPC_Decode, 142, 11, 217, 1, // Opcode: SB -/* 13518 */ MCD_OPC_FilterValue, 41, 9, 0, // Skip to: 13531 -/* 13522 */ MCD_OPC_CheckPredicate, 5, 200, 0, // Skip to: 13726 -/* 13526 */ MCD_OPC_Decode, 186, 11, 217, 1, // Opcode: SH -/* 13531 */ MCD_OPC_FilterValue, 42, 9, 0, // Skip to: 13544 -/* 13535 */ MCD_OPC_CheckPredicate, 11, 187, 0, // Skip to: 13726 -/* 13539 */ MCD_OPC_Decode, 243, 12, 217, 1, // Opcode: SWL -/* 13544 */ MCD_OPC_FilterValue, 43, 9, 0, // Skip to: 13557 -/* 13548 */ MCD_OPC_CheckPredicate, 1, 174, 0, // Skip to: 13726 -/* 13552 */ MCD_OPC_Decode, 235, 12, 217, 1, // Opcode: SW -/* 13557 */ MCD_OPC_FilterValue, 46, 9, 0, // Skip to: 13570 -/* 13561 */ MCD_OPC_CheckPredicate, 11, 161, 0, // Skip to: 13726 -/* 13565 */ MCD_OPC_Decode, 250, 12, 217, 1, // Opcode: SWR -/* 13570 */ MCD_OPC_FilterValue, 47, 9, 0, // Skip to: 13583 -/* 13574 */ MCD_OPC_CheckPredicate, 31, 148, 0, // Skip to: 13726 -/* 13578 */ MCD_OPC_Decode, 220, 2, 218, 1, // Opcode: CACHE -/* 13583 */ MCD_OPC_FilterValue, 48, 9, 0, // Skip to: 13596 -/* 13587 */ MCD_OPC_CheckPredicate, 32, 135, 0, // Skip to: 13726 -/* 13591 */ MCD_OPC_Decode, 193, 7, 217, 1, // Opcode: LL -/* 13596 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 13609 -/* 13600 */ MCD_OPC_CheckPredicate, 5, 122, 0, // Skip to: 13726 -/* 13604 */ MCD_OPC_Decode, 216, 7, 219, 1, // Opcode: LWC1 -/* 13609 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 13622 -/* 13613 */ MCD_OPC_CheckPredicate, 33, 109, 0, // Skip to: 13726 -/* 13617 */ MCD_OPC_Decode, 218, 7, 220, 1, // Opcode: LWC2 -/* 13622 */ MCD_OPC_FilterValue, 51, 9, 0, // Skip to: 13635 -/* 13626 */ MCD_OPC_CheckPredicate, 31, 96, 0, // Skip to: 13726 -/* 13630 */ MCD_OPC_Decode, 181, 10, 218, 1, // Opcode: PREF -/* 13635 */ MCD_OPC_FilterValue, 53, 9, 0, // Skip to: 13648 -/* 13639 */ MCD_OPC_CheckPredicate, 34, 83, 0, // Skip to: 13726 -/* 13643 */ MCD_OPC_Decode, 162, 7, 219, 1, // Opcode: LDC1 -/* 13648 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 13661 -/* 13652 */ MCD_OPC_CheckPredicate, 35, 70, 0, // Skip to: 13726 -/* 13656 */ MCD_OPC_Decode, 165, 7, 220, 1, // Opcode: LDC2 -/* 13661 */ MCD_OPC_FilterValue, 56, 9, 0, // Skip to: 13674 -/* 13665 */ MCD_OPC_CheckPredicate, 32, 57, 0, // Skip to: 13726 -/* 13669 */ MCD_OPC_Decode, 146, 11, 217, 1, // Opcode: SC -/* 13674 */ MCD_OPC_FilterValue, 57, 9, 0, // Skip to: 13687 -/* 13678 */ MCD_OPC_CheckPredicate, 5, 44, 0, // Skip to: 13726 -/* 13682 */ MCD_OPC_Decode, 238, 12, 219, 1, // Opcode: SWC1 -/* 13687 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 13700 -/* 13691 */ MCD_OPC_CheckPredicate, 33, 31, 0, // Skip to: 13726 -/* 13695 */ MCD_OPC_Decode, 240, 12, 220, 1, // Opcode: SWC2 -/* 13700 */ MCD_OPC_FilterValue, 61, 9, 0, // Skip to: 13713 -/* 13704 */ MCD_OPC_CheckPredicate, 34, 18, 0, // Skip to: 13726 -/* 13708 */ MCD_OPC_Decode, 156, 11, 219, 1, // Opcode: SDC1 -/* 13713 */ MCD_OPC_FilterValue, 62, 9, 0, // Skip to: 13726 -/* 13717 */ MCD_OPC_CheckPredicate, 35, 5, 0, // Skip to: 13726 -/* 13721 */ MCD_OPC_Decode, 159, 11, 220, 1, // Opcode: SDC2 -/* 13726 */ MCD_OPC_Fail, +/* 539 */ MCD_OPC_FilterValue, 0, 170, 64, 0, // Skip to: 17098 +/* 544 */ MCD_OPC_CheckPredicate, 31, 12, 0, 0, // Skip to: 561 +/* 549 */ MCD_OPC_CheckField, 11, 2, 0, 5, 0, 0, // Skip to: 561 +/* 556 */ MCD_OPC_Decode, 179, 18, 186, 1, // Opcode: MTHI +/* 561 */ MCD_OPC_CheckPredicate, 37, 148, 64, 0, // Skip to: 17098 +/* 566 */ MCD_OPC_Decode, 181, 18, 192, 1, // Opcode: MTHI_DSP +/* 571 */ MCD_OPC_FilterValue, 18, 51, 0, 0, // Skip to: 627 +/* 576 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 579 */ MCD_OPC_FilterValue, 0, 130, 64, 0, // Skip to: 17098 +/* 584 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 587 */ MCD_OPC_FilterValue, 0, 122, 64, 0, // Skip to: 17098 +/* 592 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... +/* 595 */ MCD_OPC_FilterValue, 0, 114, 64, 0, // Skip to: 17098 +/* 600 */ MCD_OPC_CheckPredicate, 31, 12, 0, 0, // Skip to: 617 +/* 605 */ MCD_OPC_CheckField, 21, 2, 0, 5, 0, 0, // Skip to: 617 +/* 612 */ MCD_OPC_Decode, 156, 17, 190, 1, // Opcode: MFLO +/* 617 */ MCD_OPC_CheckPredicate, 37, 92, 64, 0, // Skip to: 17098 +/* 622 */ MCD_OPC_Decode, 159, 17, 191, 1, // Opcode: MFLO_DSP +/* 627 */ MCD_OPC_FilterValue, 19, 43, 0, 0, // Skip to: 675 +/* 632 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 635 */ MCD_OPC_FilterValue, 0, 74, 64, 0, // Skip to: 17098 +/* 640 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ... +/* 643 */ MCD_OPC_FilterValue, 0, 66, 64, 0, // Skip to: 17098 +/* 648 */ MCD_OPC_CheckPredicate, 31, 12, 0, 0, // Skip to: 665 +/* 653 */ MCD_OPC_CheckField, 11, 2, 0, 5, 0, 0, // Skip to: 665 +/* 660 */ MCD_OPC_Decode, 186, 18, 186, 1, // Opcode: MTLO +/* 665 */ MCD_OPC_CheckPredicate, 37, 44, 64, 0, // Skip to: 17098 +/* 670 */ MCD_OPC_Decode, 188, 18, 193, 1, // Opcode: MTLO_DSP +/* 675 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 697 +/* 680 */ MCD_OPC_CheckPredicate, 38, 29, 64, 0, // Skip to: 17098 +/* 685 */ MCD_OPC_CheckField, 8, 3, 0, 22, 64, 0, // Skip to: 17098 +/* 692 */ MCD_OPC_Decode, 235, 11, 194, 1, // Opcode: DLSA +/* 697 */ MCD_OPC_FilterValue, 24, 42, 0, 0, // Skip to: 744 +/* 702 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 705 */ MCD_OPC_FilterValue, 0, 4, 64, 0, // Skip to: 17098 +/* 710 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 713 */ MCD_OPC_FilterValue, 0, 252, 63, 0, // Skip to: 17098 +/* 718 */ MCD_OPC_CheckPredicate, 31, 11, 0, 0, // Skip to: 734 +/* 723 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 734 +/* 730 */ MCD_OPC_Decode, 230, 18, 80, // Opcode: MULT +/* 734 */ MCD_OPC_CheckPredicate, 37, 231, 63, 0, // Skip to: 17098 +/* 739 */ MCD_OPC_Decode, 233, 18, 195, 1, // Opcode: MULT_DSP +/* 744 */ MCD_OPC_FilterValue, 25, 42, 0, 0, // Skip to: 791 +/* 749 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 752 */ MCD_OPC_FilterValue, 0, 213, 63, 0, // Skip to: 17098 +/* 757 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 760 */ MCD_OPC_FilterValue, 0, 205, 63, 0, // Skip to: 17098 +/* 765 */ MCD_OPC_CheckPredicate, 31, 11, 0, 0, // Skip to: 781 +/* 770 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 781 +/* 777 */ MCD_OPC_Decode, 236, 18, 80, // Opcode: MULTu +/* 781 */ MCD_OPC_CheckPredicate, 37, 184, 63, 0, // Skip to: 17098 +/* 786 */ MCD_OPC_Decode, 231, 18, 195, 1, // Opcode: MULTU_DSP +/* 791 */ MCD_OPC_FilterValue, 26, 16, 0, 0, // Skip to: 812 +/* 796 */ MCD_OPC_CheckPredicate, 31, 169, 63, 0, // Skip to: 17098 +/* 801 */ MCD_OPC_CheckField, 6, 10, 0, 162, 63, 0, // Skip to: 17098 +/* 808 */ MCD_OPC_Decode, 236, 20, 80, // Opcode: SDIV +/* 812 */ MCD_OPC_FilterValue, 27, 16, 0, 0, // Skip to: 833 +/* 817 */ MCD_OPC_CheckPredicate, 31, 148, 63, 0, // Skip to: 17098 +/* 822 */ MCD_OPC_CheckField, 6, 10, 0, 141, 63, 0, // Skip to: 17098 +/* 829 */ MCD_OPC_Decode, 152, 24, 80, // Opcode: UDIV +/* 833 */ MCD_OPC_FilterValue, 32, 16, 0, 0, // Skip to: 854 +/* 838 */ MCD_OPC_CheckPredicate, 27, 127, 63, 0, // Skip to: 17098 +/* 843 */ MCD_OPC_CheckField, 6, 5, 0, 120, 63, 0, // Skip to: 17098 +/* 850 */ MCD_OPC_Decode, 251, 5, 61, // Opcode: ADD +/* 854 */ MCD_OPC_FilterValue, 33, 16, 0, 0, // Skip to: 875 +/* 859 */ MCD_OPC_CheckPredicate, 27, 106, 63, 0, // Skip to: 17098 +/* 864 */ MCD_OPC_CheckField, 6, 5, 0, 99, 63, 0, // Skip to: 17098 +/* 871 */ MCD_OPC_Decode, 206, 6, 61, // Opcode: ADDu +/* 875 */ MCD_OPC_FilterValue, 34, 16, 0, 0, // Skip to: 896 +/* 880 */ MCD_OPC_CheckPredicate, 27, 85, 63, 0, // Skip to: 17098 +/* 885 */ MCD_OPC_CheckField, 6, 5, 0, 78, 63, 0, // Skip to: 17098 +/* 892 */ MCD_OPC_Decode, 192, 22, 61, // Opcode: SUB +/* 896 */ MCD_OPC_FilterValue, 35, 16, 0, 0, // Skip to: 917 +/* 901 */ MCD_OPC_CheckPredicate, 27, 64, 63, 0, // Skip to: 17098 +/* 906 */ MCD_OPC_CheckField, 6, 5, 0, 57, 63, 0, // Skip to: 17098 +/* 913 */ MCD_OPC_Decode, 249, 22, 61, // Opcode: SUBu +/* 917 */ MCD_OPC_FilterValue, 36, 16, 0, 0, // Skip to: 938 +/* 922 */ MCD_OPC_CheckPredicate, 27, 43, 63, 0, // Skip to: 17098 +/* 927 */ MCD_OPC_CheckField, 6, 5, 0, 36, 63, 0, // Skip to: 17098 +/* 934 */ MCD_OPC_Decode, 216, 6, 61, // Opcode: AND +/* 938 */ MCD_OPC_FilterValue, 37, 16, 0, 0, // Skip to: 959 +/* 943 */ MCD_OPC_CheckPredicate, 27, 22, 63, 0, // Skip to: 17098 +/* 948 */ MCD_OPC_CheckField, 6, 5, 0, 15, 63, 0, // Skip to: 17098 +/* 955 */ MCD_OPC_Decode, 163, 19, 61, // Opcode: OR +/* 959 */ MCD_OPC_FilterValue, 38, 16, 0, 0, // Skip to: 980 +/* 964 */ MCD_OPC_CheckPredicate, 27, 1, 63, 0, // Skip to: 17098 +/* 969 */ MCD_OPC_CheckField, 6, 5, 0, 250, 62, 0, // Skip to: 17098 +/* 976 */ MCD_OPC_Decode, 172, 24, 61, // Opcode: XOR +/* 980 */ MCD_OPC_FilterValue, 39, 16, 0, 0, // Skip to: 1001 +/* 985 */ MCD_OPC_CheckPredicate, 27, 236, 62, 0, // Skip to: 17098 +/* 990 */ MCD_OPC_CheckField, 6, 5, 0, 229, 62, 0, // Skip to: 17098 +/* 997 */ MCD_OPC_Decode, 151, 19, 61, // Opcode: NOR +/* 1001 */ MCD_OPC_FilterValue, 42, 16, 0, 0, // Skip to: 1022 +/* 1006 */ MCD_OPC_CheckPredicate, 27, 215, 62, 0, // Skip to: 17098 +/* 1011 */ MCD_OPC_CheckField, 6, 5, 0, 208, 62, 0, // Skip to: 17098 +/* 1018 */ MCD_OPC_Decode, 239, 21, 61, // Opcode: SLT +/* 1022 */ MCD_OPC_FilterValue, 43, 16, 0, 0, // Skip to: 1043 +/* 1027 */ MCD_OPC_CheckPredicate, 27, 194, 62, 0, // Skip to: 17098 +/* 1032 */ MCD_OPC_CheckField, 6, 5, 0, 187, 62, 0, // Skip to: 17098 +/* 1039 */ MCD_OPC_Decode, 252, 21, 61, // Opcode: SLTu +/* 1043 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 1058 +/* 1048 */ MCD_OPC_CheckPredicate, 36, 173, 62, 0, // Skip to: 17098 +/* 1053 */ MCD_OPC_Decode, 212, 23, 196, 1, // Opcode: TGE +/* 1058 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 1073 +/* 1063 */ MCD_OPC_CheckPredicate, 36, 158, 62, 0, // Skip to: 17098 +/* 1068 */ MCD_OPC_Decode, 217, 23, 196, 1, // Opcode: TGEU +/* 1073 */ MCD_OPC_FilterValue, 50, 10, 0, 0, // Skip to: 1088 +/* 1078 */ MCD_OPC_CheckPredicate, 36, 143, 62, 0, // Skip to: 17098 +/* 1083 */ MCD_OPC_Decode, 250, 23, 196, 1, // Opcode: TLT +/* 1088 */ MCD_OPC_FilterValue, 51, 10, 0, 0, // Skip to: 1103 +/* 1093 */ MCD_OPC_CheckPredicate, 36, 128, 62, 0, // Skip to: 17098 +/* 1098 */ MCD_OPC_Decode, 254, 23, 196, 1, // Opcode: TLTU +/* 1103 */ MCD_OPC_FilterValue, 52, 10, 0, 0, // Skip to: 1118 +/* 1108 */ MCD_OPC_CheckPredicate, 36, 113, 62, 0, // Skip to: 17098 +/* 1113 */ MCD_OPC_Decode, 207, 23, 196, 1, // Opcode: TEQ +/* 1118 */ MCD_OPC_FilterValue, 54, 103, 62, 0, // Skip to: 17098 +/* 1123 */ MCD_OPC_CheckPredicate, 36, 98, 62, 0, // Skip to: 17098 +/* 1128 */ MCD_OPC_Decode, 129, 24, 196, 1, // Opcode: TNE +/* 1133 */ MCD_OPC_FilterValue, 1, 250, 0, 0, // Skip to: 1388 +/* 1138 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 1141 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1156 +/* 1146 */ MCD_OPC_CheckPredicate, 27, 75, 62, 0, // Skip to: 17098 +/* 1151 */ MCD_OPC_Decode, 153, 8, 197, 1, // Opcode: BLTZ +/* 1156 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1171 +/* 1161 */ MCD_OPC_CheckPredicate, 27, 60, 62, 0, // Skip to: 17098 +/* 1166 */ MCD_OPC_Decode, 219, 7, 197, 1, // Opcode: BGEZ +/* 1171 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1186 +/* 1176 */ MCD_OPC_CheckPredicate, 39, 45, 62, 0, // Skip to: 17098 +/* 1181 */ MCD_OPC_Decode, 164, 8, 197, 1, // Opcode: BLTZL +/* 1186 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1201 +/* 1191 */ MCD_OPC_CheckPredicate, 39, 30, 62, 0, // Skip to: 17098 +/* 1196 */ MCD_OPC_Decode, 230, 7, 197, 1, // Opcode: BGEZL +/* 1201 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 1216 +/* 1206 */ MCD_OPC_CheckPredicate, 39, 15, 62, 0, // Skip to: 17098 +/* 1211 */ MCD_OPC_Decode, 213, 23, 175, 1, // Opcode: TGEI +/* 1216 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 1231 +/* 1221 */ MCD_OPC_CheckPredicate, 39, 0, 62, 0, // Skip to: 17098 +/* 1226 */ MCD_OPC_Decode, 214, 23, 175, 1, // Opcode: TGEIU +/* 1231 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1246 +/* 1236 */ MCD_OPC_CheckPredicate, 39, 241, 61, 0, // Skip to: 17098 +/* 1241 */ MCD_OPC_Decode, 251, 23, 175, 1, // Opcode: TLTI +/* 1246 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1261 +/* 1251 */ MCD_OPC_CheckPredicate, 39, 226, 61, 0, // Skip to: 17098 +/* 1256 */ MCD_OPC_Decode, 145, 24, 175, 1, // Opcode: TTLTIU +/* 1261 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 1276 +/* 1266 */ MCD_OPC_CheckPredicate, 39, 211, 61, 0, // Skip to: 17098 +/* 1271 */ MCD_OPC_Decode, 208, 23, 175, 1, // Opcode: TEQI +/* 1276 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1291 +/* 1281 */ MCD_OPC_CheckPredicate, 39, 196, 61, 0, // Skip to: 17098 +/* 1286 */ MCD_OPC_Decode, 130, 24, 175, 1, // Opcode: TNEI +/* 1291 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 1306 +/* 1296 */ MCD_OPC_CheckPredicate, 31, 181, 61, 0, // Skip to: 17098 +/* 1301 */ MCD_OPC_Decode, 155, 8, 197, 1, // Opcode: BLTZAL +/* 1306 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 1321 +/* 1311 */ MCD_OPC_CheckPredicate, 31, 166, 61, 0, // Skip to: 17098 +/* 1316 */ MCD_OPC_Decode, 221, 7, 197, 1, // Opcode: BGEZAL +/* 1321 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 1336 +/* 1326 */ MCD_OPC_CheckPredicate, 39, 151, 61, 0, // Skip to: 17098 +/* 1331 */ MCD_OPC_Decode, 158, 8, 197, 1, // Opcode: BLTZALL +/* 1336 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 1351 +/* 1341 */ MCD_OPC_CheckPredicate, 39, 136, 61, 0, // Skip to: 17098 +/* 1346 */ MCD_OPC_Decode, 224, 7, 197, 1, // Opcode: BGEZALL +/* 1351 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 1373 +/* 1356 */ MCD_OPC_CheckPredicate, 40, 121, 61, 0, // Skip to: 17098 +/* 1361 */ MCD_OPC_CheckField, 21, 5, 0, 114, 61, 0, // Skip to: 17098 +/* 1368 */ MCD_OPC_Decode, 208, 8, 198, 1, // Opcode: BPOSGE32 +/* 1373 */ MCD_OPC_FilterValue, 31, 104, 61, 0, // Skip to: 17098 +/* 1378 */ MCD_OPC_CheckPredicate, 28, 99, 61, 0, // Skip to: 17098 +/* 1383 */ MCD_OPC_Decode, 174, 23, 199, 1, // Opcode: SYNCI +/* 1388 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1403 +/* 1393 */ MCD_OPC_CheckPredicate, 27, 84, 61, 0, // Skip to: 17098 +/* 1398 */ MCD_OPC_Decode, 234, 14, 200, 1, // Opcode: J +/* 1403 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1418 +/* 1408 */ MCD_OPC_CheckPredicate, 27, 69, 61, 0, // Skip to: 17098 +/* 1413 */ MCD_OPC_Decode, 235, 14, 200, 1, // Opcode: JAL +/* 1418 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 1433 +/* 1423 */ MCD_OPC_CheckPredicate, 27, 54, 61, 0, // Skip to: 17098 +/* 1428 */ MCD_OPC_Decode, 188, 7, 201, 1, // Opcode: BEQ +/* 1433 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1448 +/* 1438 */ MCD_OPC_CheckPredicate, 27, 39, 61, 0, // Skip to: 17098 +/* 1443 */ MCD_OPC_Decode, 170, 8, 201, 1, // Opcode: BNE +/* 1448 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 1470 +/* 1453 */ MCD_OPC_CheckPredicate, 27, 24, 61, 0, // Skip to: 17098 +/* 1458 */ MCD_OPC_CheckField, 16, 5, 0, 17, 61, 0, // Skip to: 17098 +/* 1465 */ MCD_OPC_Decode, 134, 8, 197, 1, // Opcode: BLEZ +/* 1470 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 1492 +/* 1475 */ MCD_OPC_CheckPredicate, 27, 2, 61, 0, // Skip to: 17098 +/* 1480 */ MCD_OPC_CheckField, 16, 5, 0, 251, 60, 0, // Skip to: 17098 +/* 1487 */ MCD_OPC_Decode, 232, 7, 197, 1, // Opcode: BGTZ +/* 1492 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 1507 +/* 1497 */ MCD_OPC_CheckPredicate, 31, 236, 60, 0, // Skip to: 17098 +/* 1502 */ MCD_OPC_Decode, 202, 6, 202, 1, // Opcode: ADDi +/* 1507 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 1522 +/* 1512 */ MCD_OPC_CheckPredicate, 27, 221, 60, 0, // Skip to: 17098 +/* 1517 */ MCD_OPC_Decode, 204, 6, 202, 1, // Opcode: ADDiu +/* 1522 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1537 +/* 1527 */ MCD_OPC_CheckPredicate, 27, 206, 60, 0, // Skip to: 17098 +/* 1532 */ MCD_OPC_Decode, 246, 21, 202, 1, // Opcode: SLTi +/* 1537 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1552 +/* 1542 */ MCD_OPC_CheckPredicate, 27, 191, 60, 0, // Skip to: 17098 +/* 1547 */ MCD_OPC_Decode, 249, 21, 202, 1, // Opcode: SLTiu +/* 1552 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 1567 +/* 1557 */ MCD_OPC_CheckPredicate, 27, 176, 60, 0, // Skip to: 17098 +/* 1562 */ MCD_OPC_Decode, 231, 6, 203, 1, // Opcode: ANDi +/* 1567 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1582 +/* 1572 */ MCD_OPC_CheckPredicate, 27, 161, 60, 0, // Skip to: 17098 +/* 1577 */ MCD_OPC_Decode, 175, 19, 203, 1, // Opcode: ORi +/* 1582 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1597 +/* 1587 */ MCD_OPC_CheckPredicate, 27, 146, 60, 0, // Skip to: 17098 +/* 1592 */ MCD_OPC_Decode, 184, 24, 203, 1, // Opcode: XORi +/* 1597 */ MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 1618 +/* 1602 */ MCD_OPC_CheckPredicate, 27, 131, 60, 0, // Skip to: 17098 +/* 1607 */ MCD_OPC_CheckField, 21, 5, 0, 124, 60, 0, // Skip to: 17098 +/* 1614 */ MCD_OPC_Decode, 128, 16, 103, // Opcode: LUi +/* 1618 */ MCD_OPC_FilterValue, 16, 187, 2, 0, // Skip to: 2322 +/* 1623 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 1626 */ MCD_OPC_FilterValue, 0, 190, 1, 0, // Skip to: 2077 +/* 1631 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 1634 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1656 +/* 1639 */ MCD_OPC_CheckPredicate, 27, 94, 60, 0, // Skip to: 17098 +/* 1644 */ MCD_OPC_CheckField, 4, 7, 0, 87, 60, 0, // Skip to: 17098 +/* 1651 */ MCD_OPC_Decode, 128, 17, 204, 1, // Opcode: MFC0 +/* 1656 */ MCD_OPC_FilterValue, 3, 63, 0, 0, // Skip to: 1724 +/* 1661 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... +/* 1664 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1679 +/* 1669 */ MCD_OPC_CheckPredicate, 41, 64, 60, 0, // Skip to: 17098 +/* 1674 */ MCD_OPC_Decode, 138, 17, 204, 1, // Opcode: MFGC0 +/* 1679 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 1694 +/* 1684 */ MCD_OPC_CheckPredicate, 41, 49, 60, 0, // Skip to: 17098 +/* 1689 */ MCD_OPC_Decode, 167, 18, 205, 1, // Opcode: MTGC0 +/* 1694 */ MCD_OPC_FilterValue, 64, 10, 0, 0, // Skip to: 1709 +/* 1699 */ MCD_OPC_CheckPredicate, 41, 34, 60, 0, // Skip to: 17098 +/* 1704 */ MCD_OPC_Decode, 148, 17, 204, 1, // Opcode: MFHGC0 +/* 1709 */ MCD_OPC_FilterValue, 96, 24, 60, 0, // Skip to: 17098 +/* 1714 */ MCD_OPC_CheckPredicate, 41, 19, 60, 0, // Skip to: 17098 +/* 1719 */ MCD_OPC_Decode, 177, 18, 205, 1, // Opcode: MTHGC0 +/* 1724 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 1746 +/* 1729 */ MCD_OPC_CheckPredicate, 27, 4, 60, 0, // Skip to: 17098 +/* 1734 */ MCD_OPC_CheckField, 4, 7, 0, 253, 59, 0, // Skip to: 17098 +/* 1741 */ MCD_OPC_Decode, 156, 18, 205, 1, // Opcode: MTC0 +/* 1746 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 1768 +/* 1751 */ MCD_OPC_CheckPredicate, 42, 238, 59, 0, // Skip to: 17098 +/* 1756 */ MCD_OPC_CheckField, 6, 5, 0, 231, 59, 0, // Skip to: 17098 +/* 1763 */ MCD_OPC_Decode, 162, 17, 206, 1, // Opcode: MFTR +/* 1768 */ MCD_OPC_FilterValue, 11, 133, 0, 0, // Skip to: 1906 +/* 1773 */ MCD_OPC_ExtractField, 4, 12, // Inst{15-4} ... +/* 1776 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1797 +/* 1781 */ MCD_OPC_CheckPredicate, 42, 208, 59, 0, // Skip to: 17098 +/* 1786 */ MCD_OPC_CheckField, 0, 3, 1, 201, 59, 0, // Skip to: 17098 +/* 1793 */ MCD_OPC_Decode, 201, 12, 92, // Opcode: DVPE +/* 1797 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 1818 +/* 1802 */ MCD_OPC_CheckPredicate, 42, 187, 59, 0, // Skip to: 17098 +/* 1807 */ MCD_OPC_CheckField, 0, 3, 1, 180, 59, 0, // Skip to: 17098 +/* 1814 */ MCD_OPC_Decode, 224, 12, 92, // Opcode: EVPE +/* 1818 */ MCD_OPC_FilterValue, 188, 1, 16, 0, 0, // Skip to: 1840 +/* 1824 */ MCD_OPC_CheckPredicate, 42, 165, 59, 0, // Skip to: 17098 +/* 1829 */ MCD_OPC_CheckField, 0, 3, 1, 158, 59, 0, // Skip to: 17098 +/* 1836 */ MCD_OPC_Decode, 244, 11, 92, // Opcode: DMT +/* 1840 */ MCD_OPC_FilterValue, 190, 1, 16, 0, 0, // Skip to: 1862 +/* 1846 */ MCD_OPC_CheckPredicate, 42, 143, 59, 0, // Skip to: 17098 +/* 1851 */ MCD_OPC_CheckField, 0, 3, 1, 136, 59, 0, // Skip to: 17098 +/* 1858 */ MCD_OPC_Decode, 214, 12, 92, // Opcode: EMT +/* 1862 */ MCD_OPC_FilterValue, 128, 12, 16, 0, 0, // Skip to: 1884 +/* 1868 */ MCD_OPC_CheckPredicate, 28, 121, 59, 0, // Skip to: 17098 +/* 1873 */ MCD_OPC_CheckField, 0, 3, 0, 114, 59, 0, // Skip to: 17098 +/* 1880 */ MCD_OPC_Decode, 214, 11, 92, // Opcode: DI +/* 1884 */ MCD_OPC_FilterValue, 130, 12, 104, 59, 0, // Skip to: 17098 +/* 1890 */ MCD_OPC_CheckPredicate, 28, 99, 59, 0, // Skip to: 17098 +/* 1895 */ MCD_OPC_CheckField, 0, 3, 0, 92, 59, 0, // Skip to: 17098 +/* 1902 */ MCD_OPC_Decode, 210, 12, 92, // Opcode: EI +/* 1906 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 1928 +/* 1911 */ MCD_OPC_CheckPredicate, 42, 78, 59, 0, // Skip to: 17098 +/* 1916 */ MCD_OPC_CheckField, 6, 5, 0, 71, 59, 0, // Skip to: 17098 +/* 1923 */ MCD_OPC_Decode, 197, 18, 206, 1, // Opcode: MTTR +/* 1928 */ MCD_OPC_FilterValue, 16, 61, 59, 0, // Skip to: 17098 +/* 1933 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 1936 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 1972 +/* 1941 */ MCD_OPC_ExtractField, 4, 17, // Inst{20-4} ... +/* 1944 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1958 +/* 1949 */ MCD_OPC_CheckPredicate, 41, 40, 59, 0, // Skip to: 17098 +/* 1954 */ MCD_OPC_Decode, 224, 23, 10, // Opcode: TLBGP +/* 1958 */ MCD_OPC_FilterValue, 2, 31, 59, 0, // Skip to: 17098 +/* 1963 */ MCD_OPC_CheckPredicate, 43, 26, 59, 0, // Skip to: 17098 +/* 1968 */ MCD_OPC_Decode, 161, 24, 10, // Opcode: WAIT +/* 1972 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 1993 +/* 1977 */ MCD_OPC_CheckPredicate, 27, 12, 59, 0, // Skip to: 17098 +/* 1982 */ MCD_OPC_CheckField, 4, 17, 0, 5, 59, 0, // Skip to: 17098 +/* 1989 */ MCD_OPC_Decode, 241, 23, 10, // Opcode: TLBR +/* 1993 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 2014 +/* 1998 */ MCD_OPC_CheckPredicate, 27, 247, 58, 0, // Skip to: 17098 +/* 2003 */ MCD_OPC_CheckField, 4, 17, 0, 240, 58, 0, // Skip to: 17098 +/* 2010 */ MCD_OPC_Decode, 244, 23, 10, // Opcode: TLBWI +/* 2014 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 2035 +/* 2019 */ MCD_OPC_CheckPredicate, 44, 226, 58, 0, // Skip to: 17098 +/* 2024 */ MCD_OPC_CheckField, 4, 17, 0, 219, 58, 0, // Skip to: 17098 +/* 2031 */ MCD_OPC_Decode, 232, 23, 10, // Opcode: TLBINV +/* 2035 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 2056 +/* 2040 */ MCD_OPC_CheckPredicate, 44, 205, 58, 0, // Skip to: 17098 +/* 2045 */ MCD_OPC_CheckField, 4, 17, 0, 198, 58, 0, // Skip to: 17098 +/* 2052 */ MCD_OPC_Decode, 233, 23, 10, // Opcode: TLBINVF +/* 2056 */ MCD_OPC_FilterValue, 6, 189, 58, 0, // Skip to: 17098 +/* 2061 */ MCD_OPC_CheckPredicate, 27, 184, 58, 0, // Skip to: 17098 +/* 2066 */ MCD_OPC_CheckField, 4, 17, 0, 177, 58, 0, // Skip to: 17098 +/* 2073 */ MCD_OPC_Decode, 247, 23, 10, // Opcode: TLBWR +/* 2077 */ MCD_OPC_FilterValue, 1, 168, 58, 0, // Skip to: 17098 +/* 2082 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 2085 */ MCD_OPC_FilterValue, 0, 88, 0, 0, // Skip to: 2178 +/* 2090 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... +/* 2093 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 2116 +/* 2098 */ MCD_OPC_CheckPredicate, 27, 147, 58, 0, // Skip to: 17098 +/* 2103 */ MCD_OPC_CheckField, 6, 20, 128, 128, 32, 138, 58, 0, // Skip to: 17098 +/* 2112 */ MCD_OPC_Decode, 238, 23, 10, // Opcode: TLBP +/* 2116 */ MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 2156 +/* 2121 */ MCD_OPC_ExtractField, 6, 20, // Inst{25-6} ... +/* 2124 */ MCD_OPC_FilterValue, 128, 128, 32, 9, 0, 0, // Skip to: 2140 +/* 2131 */ MCD_OPC_CheckPredicate, 43, 114, 58, 0, // Skip to: 17098 +/* 2136 */ MCD_OPC_Decode, 216, 12, 10, // Opcode: ERET +/* 2140 */ MCD_OPC_FilterValue, 129, 128, 32, 103, 58, 0, // Skip to: 17098 +/* 2147 */ MCD_OPC_CheckPredicate, 45, 98, 58, 0, // Skip to: 17098 +/* 2152 */ MCD_OPC_Decode, 217, 12, 10, // Opcode: ERETNC +/* 2156 */ MCD_OPC_FilterValue, 2, 89, 58, 0, // Skip to: 17098 +/* 2161 */ MCD_OPC_CheckPredicate, 41, 84, 58, 0, // Skip to: 17098 +/* 2166 */ MCD_OPC_CheckField, 25, 1, 1, 77, 58, 0, // Skip to: 17098 +/* 2173 */ MCD_OPC_Decode, 202, 14, 207, 1, // Opcode: HYPCALL +/* 2178 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 2202 +/* 2183 */ MCD_OPC_CheckPredicate, 41, 62, 58, 0, // Skip to: 17098 +/* 2188 */ MCD_OPC_CheckField, 4, 22, 128, 128, 128, 1, 52, 58, 0, // Skip to: 17098 +/* 2198 */ MCD_OPC_Decode, 226, 23, 10, // Opcode: TLBGR +/* 2202 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 2226 +/* 2207 */ MCD_OPC_CheckPredicate, 41, 38, 58, 0, // Skip to: 17098 +/* 2212 */ MCD_OPC_CheckField, 4, 22, 128, 128, 128, 1, 28, 58, 0, // Skip to: 17098 +/* 2222 */ MCD_OPC_Decode, 228, 23, 10, // Opcode: TLBGWI +/* 2226 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 2250 +/* 2231 */ MCD_OPC_CheckPredicate, 41, 14, 58, 0, // Skip to: 17098 +/* 2236 */ MCD_OPC_CheckField, 4, 22, 128, 128, 128, 1, 4, 58, 0, // Skip to: 17098 +/* 2246 */ MCD_OPC_Decode, 220, 23, 10, // Opcode: TLBGINV +/* 2250 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 2274 +/* 2255 */ MCD_OPC_CheckPredicate, 41, 246, 57, 0, // Skip to: 17098 +/* 2260 */ MCD_OPC_CheckField, 4, 22, 128, 128, 128, 1, 236, 57, 0, // Skip to: 17098 +/* 2270 */ MCD_OPC_Decode, 221, 23, 10, // Opcode: TLBGINVF +/* 2274 */ MCD_OPC_FilterValue, 6, 19, 0, 0, // Skip to: 2298 +/* 2279 */ MCD_OPC_CheckPredicate, 41, 222, 57, 0, // Skip to: 17098 +/* 2284 */ MCD_OPC_CheckField, 4, 22, 128, 128, 128, 1, 212, 57, 0, // Skip to: 17098 +/* 2294 */ MCD_OPC_Decode, 230, 23, 10, // Opcode: TLBGWR +/* 2298 */ MCD_OPC_FilterValue, 7, 203, 57, 0, // Skip to: 17098 +/* 2303 */ MCD_OPC_CheckPredicate, 46, 198, 57, 0, // Skip to: 17098 +/* 2308 */ MCD_OPC_CheckField, 4, 22, 129, 128, 128, 1, 188, 57, 0, // Skip to: 17098 +/* 2318 */ MCD_OPC_Decode, 206, 11, 10, // Opcode: DERET +/* 2322 */ MCD_OPC_FilterValue, 17, 205, 7, 0, // Skip to: 4324 +/* 2327 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 2330 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2352 +/* 2335 */ MCD_OPC_CheckPredicate, 47, 166, 57, 0, // Skip to: 17098 +/* 2340 */ MCD_OPC_CheckField, 0, 11, 0, 159, 57, 0, // Skip to: 17098 +/* 2347 */ MCD_OPC_Decode, 132, 17, 208, 1, // Opcode: MFC1 +/* 2352 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 2374 +/* 2357 */ MCD_OPC_CheckPredicate, 48, 144, 57, 0, // Skip to: 17098 +/* 2362 */ MCD_OPC_CheckField, 0, 11, 0, 137, 57, 0, // Skip to: 17098 +/* 2369 */ MCD_OPC_Decode, 238, 11, 209, 1, // Opcode: DMFC1 +/* 2374 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 2396 +/* 2379 */ MCD_OPC_CheckPredicate, 47, 122, 57, 0, // Skip to: 17098 +/* 2384 */ MCD_OPC_CheckField, 0, 11, 0, 115, 57, 0, // Skip to: 17098 +/* 2391 */ MCD_OPC_Decode, 144, 9, 210, 1, // Opcode: CFC1 +/* 2396 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 2418 +/* 2401 */ MCD_OPC_CheckPredicate, 49, 100, 57, 0, // Skip to: 17098 +/* 2406 */ MCD_OPC_CheckField, 0, 11, 0, 93, 57, 0, // Skip to: 17098 +/* 2413 */ MCD_OPC_Decode, 143, 17, 211, 1, // Opcode: MFHC1_D32 +/* 2418 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 2440 +/* 2423 */ MCD_OPC_CheckPredicate, 47, 78, 57, 0, // Skip to: 17098 +/* 2428 */ MCD_OPC_CheckField, 0, 11, 0, 71, 57, 0, // Skip to: 17098 +/* 2435 */ MCD_OPC_Decode, 160, 18, 212, 1, // Opcode: MTC1 +/* 2440 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 2462 +/* 2445 */ MCD_OPC_CheckPredicate, 48, 56, 57, 0, // Skip to: 17098 +/* 2450 */ MCD_OPC_CheckField, 0, 11, 0, 49, 57, 0, // Skip to: 17098 +/* 2457 */ MCD_OPC_Decode, 246, 11, 213, 1, // Opcode: DMTC1 +/* 2462 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 2484 +/* 2467 */ MCD_OPC_CheckPredicate, 47, 34, 57, 0, // Skip to: 17098 +/* 2472 */ MCD_OPC_CheckField, 0, 11, 0, 27, 57, 0, // Skip to: 17098 +/* 2479 */ MCD_OPC_Decode, 179, 10, 214, 1, // Opcode: CTC1 +/* 2484 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 2506 +/* 2489 */ MCD_OPC_CheckPredicate, 49, 12, 57, 0, // Skip to: 17098 +/* 2494 */ MCD_OPC_CheckField, 0, 11, 0, 5, 57, 0, // Skip to: 17098 +/* 2501 */ MCD_OPC_Decode, 172, 18, 215, 1, // Opcode: MTHC1_D32 +/* 2506 */ MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 2574 +/* 2511 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 2514 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2529 +/* 2519 */ MCD_OPC_CheckPredicate, 50, 238, 56, 0, // Skip to: 17098 +/* 2524 */ MCD_OPC_Decode, 166, 7, 216, 1, // Opcode: BC1F +/* 2529 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2544 +/* 2534 */ MCD_OPC_CheckPredicate, 50, 223, 56, 0, // Skip to: 17098 +/* 2539 */ MCD_OPC_Decode, 171, 7, 216, 1, // Opcode: BC1T +/* 2544 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2559 +/* 2549 */ MCD_OPC_CheckPredicate, 51, 208, 56, 0, // Skip to: 17098 +/* 2554 */ MCD_OPC_Decode, 167, 7, 216, 1, // Opcode: BC1FL +/* 2559 */ MCD_OPC_FilterValue, 3, 198, 56, 0, // Skip to: 17098 +/* 2564 */ MCD_OPC_CheckPredicate, 51, 193, 56, 0, // Skip to: 17098 +/* 2569 */ MCD_OPC_Decode, 172, 7, 216, 1, // Opcode: BC1TL +/* 2574 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 2589 +/* 2579 */ MCD_OPC_CheckPredicate, 30, 178, 56, 0, // Skip to: 17098 +/* 2584 */ MCD_OPC_Decode, 233, 8, 217, 1, // Opcode: BZ_V +/* 2589 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2604 +/* 2594 */ MCD_OPC_CheckPredicate, 30, 163, 56, 0, // Skip to: 17098 +/* 2599 */ MCD_OPC_Decode, 204, 8, 217, 1, // Opcode: BNZ_V +/* 2604 */ MCD_OPC_FilterValue, 16, 1, 3, 0, // Skip to: 3378 +/* 2609 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 2612 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2627 +/* 2617 */ MCD_OPC_CheckPredicate, 47, 140, 56, 0, // Skip to: 17098 +/* 2622 */ MCD_OPC_Decode, 142, 13, 218, 1, // Opcode: FADD_S +/* 2627 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2642 +/* 2632 */ MCD_OPC_CheckPredicate, 47, 125, 56, 0, // Skip to: 17098 +/* 2637 */ MCD_OPC_Decode, 160, 14, 218, 1, // Opcode: FSUB_S +/* 2642 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2657 +/* 2647 */ MCD_OPC_CheckPredicate, 47, 110, 56, 0, // Skip to: 17098 +/* 2652 */ MCD_OPC_Decode, 243, 13, 218, 1, // Opcode: FMUL_S +/* 2657 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 2672 +/* 2662 */ MCD_OPC_CheckPredicate, 47, 95, 56, 0, // Skip to: 17098 +/* 2667 */ MCD_OPC_Decode, 180, 13, 218, 1, // Opcode: FDIV_S +/* 2672 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 2694 +/* 2677 */ MCD_OPC_CheckPredicate, 52, 80, 56, 0, // Skip to: 17098 +/* 2682 */ MCD_OPC_CheckField, 16, 5, 0, 73, 56, 0, // Skip to: 17098 +/* 2689 */ MCD_OPC_Decode, 151, 14, 219, 1, // Opcode: FSQRT_S +/* 2694 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 2716 +/* 2699 */ MCD_OPC_CheckPredicate, 47, 58, 56, 0, // Skip to: 17098 +/* 2704 */ MCD_OPC_CheckField, 16, 5, 0, 51, 56, 0, // Skip to: 17098 +/* 2711 */ MCD_OPC_Decode, 134, 13, 219, 1, // Opcode: FABS_S +/* 2716 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 2738 +/* 2721 */ MCD_OPC_CheckPredicate, 47, 36, 56, 0, // Skip to: 17098 +/* 2726 */ MCD_OPC_CheckField, 16, 5, 0, 29, 56, 0, // Skip to: 17098 +/* 2733 */ MCD_OPC_Decode, 232, 13, 219, 1, // Opcode: FMOV_S +/* 2738 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 2760 +/* 2743 */ MCD_OPC_CheckPredicate, 53, 14, 56, 0, // Skip to: 17098 +/* 2748 */ MCD_OPC_CheckField, 16, 5, 0, 7, 56, 0, // Skip to: 17098 +/* 2755 */ MCD_OPC_Decode, 251, 13, 219, 1, // Opcode: FNEG_S +/* 2760 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 2782 +/* 2765 */ MCD_OPC_CheckPredicate, 52, 248, 55, 0, // Skip to: 17098 +/* 2770 */ MCD_OPC_CheckField, 16, 5, 0, 241, 55, 0, // Skip to: 17098 +/* 2777 */ MCD_OPC_Decode, 170, 20, 219, 1, // Opcode: ROUND_W_S +/* 2782 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 2804 +/* 2787 */ MCD_OPC_CheckPredicate, 52, 226, 55, 0, // Skip to: 17098 +/* 2792 */ MCD_OPC_CheckField, 16, 5, 0, 219, 55, 0, // Skip to: 17098 +/* 2799 */ MCD_OPC_Decode, 142, 24, 219, 1, // Opcode: TRUNC_W_S +/* 2804 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 2826 +/* 2809 */ MCD_OPC_CheckPredicate, 52, 204, 55, 0, // Skip to: 17098 +/* 2814 */ MCD_OPC_CheckField, 16, 5, 0, 197, 55, 0, // Skip to: 17098 +/* 2821 */ MCD_OPC_Decode, 133, 9, 219, 1, // Opcode: CEIL_W_S +/* 2826 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2848 +/* 2831 */ MCD_OPC_CheckPredicate, 52, 182, 55, 0, // Skip to: 17098 +/* 2836 */ MCD_OPC_CheckField, 16, 5, 0, 175, 55, 0, // Skip to: 17098 +/* 2843 */ MCD_OPC_Decode, 214, 13, 219, 1, // Opcode: FLOOR_W_S +/* 2848 */ MCD_OPC_FilterValue, 17, 33, 0, 0, // Skip to: 2886 +/* 2853 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 2856 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2871 +/* 2861 */ MCD_OPC_CheckPredicate, 29, 152, 55, 0, // Skip to: 17098 +/* 2866 */ MCD_OPC_Decode, 223, 17, 220, 1, // Opcode: MOVF_S +/* 2871 */ MCD_OPC_FilterValue, 1, 142, 55, 0, // Skip to: 17098 +/* 2876 */ MCD_OPC_CheckPredicate, 29, 137, 55, 0, // Skip to: 17098 +/* 2881 */ MCD_OPC_Decode, 244, 17, 220, 1, // Opcode: MOVT_S +/* 2886 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 2901 +/* 2891 */ MCD_OPC_CheckPredicate, 29, 122, 55, 0, // Skip to: 17098 +/* 2896 */ MCD_OPC_Decode, 128, 18, 221, 1, // Opcode: MOVZ_I_S +/* 2901 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 2916 +/* 2906 */ MCD_OPC_CheckPredicate, 29, 107, 55, 0, // Skip to: 17098 +/* 2911 */ MCD_OPC_Decode, 235, 17, 221, 1, // Opcode: MOVN_I_S +/* 2916 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 2938 +/* 2921 */ MCD_OPC_CheckPredicate, 54, 92, 55, 0, // Skip to: 17098 +/* 2926 */ MCD_OPC_CheckField, 16, 5, 0, 85, 55, 0, // Skip to: 17098 +/* 2933 */ MCD_OPC_Decode, 138, 20, 219, 1, // Opcode: RECIP_S +/* 2938 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 2960 +/* 2943 */ MCD_OPC_CheckPredicate, 54, 70, 55, 0, // Skip to: 17098 +/* 2948 */ MCD_OPC_CheckField, 16, 5, 0, 63, 55, 0, // Skip to: 17098 +/* 2955 */ MCD_OPC_Decode, 177, 20, 219, 1, // Opcode: RSQRT_S +/* 2960 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 2982 +/* 2965 */ MCD_OPC_CheckPredicate, 55, 48, 55, 0, // Skip to: 17098 +/* 2970 */ MCD_OPC_CheckField, 16, 5, 0, 41, 55, 0, // Skip to: 17098 +/* 2977 */ MCD_OPC_Decode, 183, 10, 222, 1, // Opcode: CVT_D32_S +/* 2982 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 3004 +/* 2987 */ MCD_OPC_CheckPredicate, 47, 26, 55, 0, // Skip to: 17098 +/* 2992 */ MCD_OPC_CheckField, 16, 5, 0, 19, 55, 0, // Skip to: 17098 +/* 2999 */ MCD_OPC_Decode, 217, 10, 219, 1, // Opcode: CVT_W_S +/* 3004 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 3026 +/* 3009 */ MCD_OPC_CheckPredicate, 56, 4, 55, 0, // Skip to: 17098 +/* 3014 */ MCD_OPC_CheckField, 16, 5, 0, 253, 54, 0, // Skip to: 17098 +/* 3021 */ MCD_OPC_Decode, 196, 10, 223, 1, // Opcode: CVT_L_S +/* 3026 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 3048 +/* 3031 */ MCD_OPC_CheckPredicate, 50, 238, 54, 0, // Skip to: 17098 +/* 3036 */ MCD_OPC_CheckField, 6, 2, 0, 231, 54, 0, // Skip to: 17098 +/* 3043 */ MCD_OPC_Decode, 230, 10, 224, 1, // Opcode: C_F_S +/* 3048 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 3070 +/* 3053 */ MCD_OPC_CheckPredicate, 50, 216, 54, 0, // Skip to: 17098 +/* 3058 */ MCD_OPC_CheckField, 6, 2, 0, 209, 54, 0, // Skip to: 17098 +/* 3065 */ MCD_OPC_Decode, 186, 11, 224, 1, // Opcode: C_UN_S +/* 3070 */ MCD_OPC_FilterValue, 50, 17, 0, 0, // Skip to: 3092 +/* 3075 */ MCD_OPC_CheckPredicate, 50, 194, 54, 0, // Skip to: 17098 +/* 3080 */ MCD_OPC_CheckField, 6, 2, 0, 187, 54, 0, // Skip to: 17098 +/* 3087 */ MCD_OPC_Decode, 224, 10, 224, 1, // Opcode: C_EQ_S +/* 3092 */ MCD_OPC_FilterValue, 51, 17, 0, 0, // Skip to: 3114 +/* 3097 */ MCD_OPC_CheckPredicate, 50, 172, 54, 0, // Skip to: 17098 +/* 3102 */ MCD_OPC_CheckField, 6, 2, 0, 165, 54, 0, // Skip to: 17098 +/* 3109 */ MCD_OPC_Decode, 168, 11, 224, 1, // Opcode: C_UEQ_S +/* 3114 */ MCD_OPC_FilterValue, 52, 17, 0, 0, // Skip to: 3136 +/* 3119 */ MCD_OPC_CheckPredicate, 50, 150, 54, 0, // Skip to: 17098 +/* 3124 */ MCD_OPC_CheckField, 6, 2, 0, 143, 54, 0, // Skip to: 17098 +/* 3131 */ MCD_OPC_Decode, 150, 11, 224, 1, // Opcode: C_OLT_S +/* 3136 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 3158 +/* 3141 */ MCD_OPC_CheckPredicate, 50, 128, 54, 0, // Skip to: 17098 +/* 3146 */ MCD_OPC_CheckField, 6, 2, 0, 121, 54, 0, // Skip to: 17098 +/* 3153 */ MCD_OPC_Decode, 180, 11, 224, 1, // Opcode: C_ULT_S +/* 3158 */ MCD_OPC_FilterValue, 54, 17, 0, 0, // Skip to: 3180 +/* 3163 */ MCD_OPC_CheckPredicate, 50, 106, 54, 0, // Skip to: 17098 +/* 3168 */ MCD_OPC_CheckField, 6, 2, 0, 99, 54, 0, // Skip to: 17098 +/* 3175 */ MCD_OPC_Decode, 144, 11, 224, 1, // Opcode: C_OLE_S +/* 3180 */ MCD_OPC_FilterValue, 55, 17, 0, 0, // Skip to: 3202 +/* 3185 */ MCD_OPC_CheckPredicate, 50, 84, 54, 0, // Skip to: 17098 +/* 3190 */ MCD_OPC_CheckField, 6, 2, 0, 77, 54, 0, // Skip to: 17098 +/* 3197 */ MCD_OPC_Decode, 174, 11, 224, 1, // Opcode: C_ULE_S +/* 3202 */ MCD_OPC_FilterValue, 56, 17, 0, 0, // Skip to: 3224 +/* 3207 */ MCD_OPC_CheckPredicate, 50, 62, 54, 0, // Skip to: 17098 +/* 3212 */ MCD_OPC_CheckField, 6, 2, 0, 55, 54, 0, // Skip to: 17098 +/* 3219 */ MCD_OPC_Decode, 162, 11, 224, 1, // Opcode: C_SF_S +/* 3224 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 3246 +/* 3229 */ MCD_OPC_CheckPredicate, 50, 40, 54, 0, // Skip to: 17098 +/* 3234 */ MCD_OPC_CheckField, 6, 2, 0, 33, 54, 0, // Skip to: 17098 +/* 3241 */ MCD_OPC_Decode, 254, 10, 224, 1, // Opcode: C_NGLE_S +/* 3246 */ MCD_OPC_FilterValue, 58, 17, 0, 0, // Skip to: 3268 +/* 3251 */ MCD_OPC_CheckPredicate, 50, 18, 54, 0, // Skip to: 17098 +/* 3256 */ MCD_OPC_CheckField, 6, 2, 0, 11, 54, 0, // Skip to: 17098 +/* 3263 */ MCD_OPC_Decode, 156, 11, 224, 1, // Opcode: C_SEQ_S +/* 3268 */ MCD_OPC_FilterValue, 59, 17, 0, 0, // Skip to: 3290 +/* 3273 */ MCD_OPC_CheckPredicate, 50, 252, 53, 0, // Skip to: 17098 +/* 3278 */ MCD_OPC_CheckField, 6, 2, 0, 245, 53, 0, // Skip to: 17098 +/* 3285 */ MCD_OPC_Decode, 132, 11, 224, 1, // Opcode: C_NGL_S +/* 3290 */ MCD_OPC_FilterValue, 60, 17, 0, 0, // Skip to: 3312 +/* 3295 */ MCD_OPC_CheckPredicate, 50, 230, 53, 0, // Skip to: 17098 +/* 3300 */ MCD_OPC_CheckField, 6, 2, 0, 223, 53, 0, // Skip to: 17098 +/* 3307 */ MCD_OPC_Decode, 242, 10, 224, 1, // Opcode: C_LT_S +/* 3312 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 3334 +/* 3317 */ MCD_OPC_CheckPredicate, 50, 208, 53, 0, // Skip to: 17098 +/* 3322 */ MCD_OPC_CheckField, 6, 2, 0, 201, 53, 0, // Skip to: 17098 +/* 3329 */ MCD_OPC_Decode, 248, 10, 224, 1, // Opcode: C_NGE_S +/* 3334 */ MCD_OPC_FilterValue, 62, 17, 0, 0, // Skip to: 3356 +/* 3339 */ MCD_OPC_CheckPredicate, 50, 186, 53, 0, // Skip to: 17098 +/* 3344 */ MCD_OPC_CheckField, 6, 2, 0, 179, 53, 0, // Skip to: 17098 +/* 3351 */ MCD_OPC_Decode, 236, 10, 224, 1, // Opcode: C_LE_S +/* 3356 */ MCD_OPC_FilterValue, 63, 169, 53, 0, // Skip to: 17098 +/* 3361 */ MCD_OPC_CheckPredicate, 50, 164, 53, 0, // Skip to: 17098 +/* 3366 */ MCD_OPC_CheckField, 6, 2, 0, 157, 53, 0, // Skip to: 17098 +/* 3373 */ MCD_OPC_Decode, 138, 11, 224, 1, // Opcode: C_NGT_S +/* 3378 */ MCD_OPC_FilterValue, 17, 1, 3, 0, // Skip to: 4152 +/* 3383 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 3386 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3401 +/* 3391 */ MCD_OPC_CheckPredicate, 55, 134, 53, 0, // Skip to: 17098 +/* 3396 */ MCD_OPC_Decode, 137, 13, 225, 1, // Opcode: FADD_D32 +/* 3401 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 3416 +/* 3406 */ MCD_OPC_CheckPredicate, 55, 119, 53, 0, // Skip to: 17098 +/* 3411 */ MCD_OPC_Decode, 155, 14, 225, 1, // Opcode: FSUB_D32 +/* 3416 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 3431 +/* 3421 */ MCD_OPC_CheckPredicate, 55, 104, 53, 0, // Skip to: 17098 +/* 3426 */ MCD_OPC_Decode, 238, 13, 225, 1, // Opcode: FMUL_D32 +/* 3431 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 3446 +/* 3436 */ MCD_OPC_CheckPredicate, 55, 89, 53, 0, // Skip to: 17098 +/* 3441 */ MCD_OPC_Decode, 176, 13, 225, 1, // Opcode: FDIV_D32 +/* 3446 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 3468 +/* 3451 */ MCD_OPC_CheckPredicate, 57, 74, 53, 0, // Skip to: 17098 +/* 3456 */ MCD_OPC_CheckField, 16, 5, 0, 67, 53, 0, // Skip to: 17098 +/* 3463 */ MCD_OPC_Decode, 147, 14, 226, 1, // Opcode: FSQRT_D32 +/* 3468 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 3490 +/* 3473 */ MCD_OPC_CheckPredicate, 55, 52, 53, 0, // Skip to: 17098 +/* 3478 */ MCD_OPC_CheckField, 16, 5, 0, 45, 53, 0, // Skip to: 17098 +/* 3485 */ MCD_OPC_Decode, 130, 13, 226, 1, // Opcode: FABS_D32 +/* 3490 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 3512 +/* 3495 */ MCD_OPC_CheckPredicate, 55, 30, 53, 0, // Skip to: 17098 +/* 3500 */ MCD_OPC_CheckField, 16, 5, 0, 23, 53, 0, // Skip to: 17098 +/* 3507 */ MCD_OPC_Decode, 227, 13, 226, 1, // Opcode: FMOV_D32 +/* 3512 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 3534 +/* 3517 */ MCD_OPC_CheckPredicate, 55, 8, 53, 0, // Skip to: 17098 +/* 3522 */ MCD_OPC_CheckField, 16, 5, 0, 1, 53, 0, // Skip to: 17098 +/* 3529 */ MCD_OPC_Decode, 247, 13, 226, 1, // Opcode: FNEG_D32 +/* 3534 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 3556 +/* 3539 */ MCD_OPC_CheckPredicate, 57, 242, 52, 0, // Skip to: 17098 +/* 3544 */ MCD_OPC_CheckField, 16, 5, 0, 235, 52, 0, // Skip to: 17098 +/* 3551 */ MCD_OPC_Decode, 166, 20, 227, 1, // Opcode: ROUND_W_D32 +/* 3556 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 3578 +/* 3561 */ MCD_OPC_CheckPredicate, 57, 220, 52, 0, // Skip to: 17098 +/* 3566 */ MCD_OPC_CheckField, 16, 5, 0, 213, 52, 0, // Skip to: 17098 +/* 3573 */ MCD_OPC_Decode, 138, 24, 227, 1, // Opcode: TRUNC_W_D32 +/* 3578 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 3600 +/* 3583 */ MCD_OPC_CheckPredicate, 57, 198, 52, 0, // Skip to: 17098 +/* 3588 */ MCD_OPC_CheckField, 16, 5, 0, 191, 52, 0, // Skip to: 17098 +/* 3595 */ MCD_OPC_Decode, 129, 9, 227, 1, // Opcode: CEIL_W_D32 +/* 3600 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 3622 +/* 3605 */ MCD_OPC_CheckPredicate, 57, 176, 52, 0, // Skip to: 17098 +/* 3610 */ MCD_OPC_CheckField, 16, 5, 0, 169, 52, 0, // Skip to: 17098 +/* 3617 */ MCD_OPC_Decode, 210, 13, 227, 1, // Opcode: FLOOR_W_D32 +/* 3622 */ MCD_OPC_FilterValue, 17, 33, 0, 0, // Skip to: 3660 +/* 3627 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 3630 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3645 +/* 3635 */ MCD_OPC_CheckPredicate, 58, 146, 52, 0, // Skip to: 17098 +/* 3640 */ MCD_OPC_Decode, 217, 17, 228, 1, // Opcode: MOVF_D32 +/* 3645 */ MCD_OPC_FilterValue, 1, 136, 52, 0, // Skip to: 17098 +/* 3650 */ MCD_OPC_CheckPredicate, 58, 131, 52, 0, // Skip to: 17098 +/* 3655 */ MCD_OPC_Decode, 238, 17, 228, 1, // Opcode: MOVT_D32 +/* 3660 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 3675 +/* 3665 */ MCD_OPC_CheckPredicate, 58, 116, 52, 0, // Skip to: 17098 +/* 3670 */ MCD_OPC_Decode, 250, 17, 229, 1, // Opcode: MOVZ_I_D32 +/* 3675 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 3690 +/* 3680 */ MCD_OPC_CheckPredicate, 58, 101, 52, 0, // Skip to: 17098 +/* 3685 */ MCD_OPC_Decode, 229, 17, 229, 1, // Opcode: MOVN_I_D32 +/* 3690 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 3712 +/* 3695 */ MCD_OPC_CheckPredicate, 59, 86, 52, 0, // Skip to: 17098 +/* 3700 */ MCD_OPC_CheckField, 16, 5, 0, 79, 52, 0, // Skip to: 17098 +/* 3707 */ MCD_OPC_Decode, 134, 20, 226, 1, // Opcode: RECIP_D32 +/* 3712 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 3734 +/* 3717 */ MCD_OPC_CheckPredicate, 59, 64, 52, 0, // Skip to: 17098 +/* 3722 */ MCD_OPC_CheckField, 16, 5, 0, 57, 52, 0, // Skip to: 17098 +/* 3729 */ MCD_OPC_Decode, 173, 20, 226, 1, // Opcode: RSQRT_D32 +/* 3734 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 3756 +/* 3739 */ MCD_OPC_CheckPredicate, 55, 42, 52, 0, // Skip to: 17098 +/* 3744 */ MCD_OPC_CheckField, 16, 5, 0, 35, 52, 0, // Skip to: 17098 +/* 3751 */ MCD_OPC_Decode, 202, 10, 227, 1, // Opcode: CVT_S_D32 +/* 3756 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 3778 +/* 3761 */ MCD_OPC_CheckPredicate, 55, 20, 52, 0, // Skip to: 17098 +/* 3766 */ MCD_OPC_CheckField, 16, 5, 0, 13, 52, 0, // Skip to: 17098 +/* 3773 */ MCD_OPC_Decode, 213, 10, 227, 1, // Opcode: CVT_W_D32 +/* 3778 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 3800 +/* 3783 */ MCD_OPC_CheckPredicate, 56, 254, 51, 0, // Skip to: 17098 +/* 3788 */ MCD_OPC_CheckField, 16, 5, 0, 247, 51, 0, // Skip to: 17098 +/* 3795 */ MCD_OPC_Decode, 193, 10, 230, 1, // Opcode: CVT_L_D64 +/* 3800 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 3822 +/* 3805 */ MCD_OPC_CheckPredicate, 60, 232, 51, 0, // Skip to: 17098 +/* 3810 */ MCD_OPC_CheckField, 6, 2, 0, 225, 51, 0, // Skip to: 17098 +/* 3817 */ MCD_OPC_Decode, 226, 10, 231, 1, // Opcode: C_F_D32 +/* 3822 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 3844 +/* 3827 */ MCD_OPC_CheckPredicate, 60, 210, 51, 0, // Skip to: 17098 +/* 3832 */ MCD_OPC_CheckField, 6, 2, 0, 203, 51, 0, // Skip to: 17098 +/* 3839 */ MCD_OPC_Decode, 182, 11, 231, 1, // Opcode: C_UN_D32 +/* 3844 */ MCD_OPC_FilterValue, 50, 17, 0, 0, // Skip to: 3866 +/* 3849 */ MCD_OPC_CheckPredicate, 60, 188, 51, 0, // Skip to: 17098 +/* 3854 */ MCD_OPC_CheckField, 6, 2, 0, 181, 51, 0, // Skip to: 17098 +/* 3861 */ MCD_OPC_Decode, 220, 10, 231, 1, // Opcode: C_EQ_D32 +/* 3866 */ MCD_OPC_FilterValue, 51, 17, 0, 0, // Skip to: 3888 +/* 3871 */ MCD_OPC_CheckPredicate, 60, 166, 51, 0, // Skip to: 17098 +/* 3876 */ MCD_OPC_CheckField, 6, 2, 0, 159, 51, 0, // Skip to: 17098 +/* 3883 */ MCD_OPC_Decode, 164, 11, 231, 1, // Opcode: C_UEQ_D32 +/* 3888 */ MCD_OPC_FilterValue, 52, 17, 0, 0, // Skip to: 3910 +/* 3893 */ MCD_OPC_CheckPredicate, 60, 144, 51, 0, // Skip to: 17098 +/* 3898 */ MCD_OPC_CheckField, 6, 2, 0, 137, 51, 0, // Skip to: 17098 +/* 3905 */ MCD_OPC_Decode, 146, 11, 231, 1, // Opcode: C_OLT_D32 +/* 3910 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 3932 +/* 3915 */ MCD_OPC_CheckPredicate, 60, 122, 51, 0, // Skip to: 17098 +/* 3920 */ MCD_OPC_CheckField, 6, 2, 0, 115, 51, 0, // Skip to: 17098 +/* 3927 */ MCD_OPC_Decode, 176, 11, 231, 1, // Opcode: C_ULT_D32 +/* 3932 */ MCD_OPC_FilterValue, 54, 17, 0, 0, // Skip to: 3954 +/* 3937 */ MCD_OPC_CheckPredicate, 60, 100, 51, 0, // Skip to: 17098 +/* 3942 */ MCD_OPC_CheckField, 6, 2, 0, 93, 51, 0, // Skip to: 17098 +/* 3949 */ MCD_OPC_Decode, 140, 11, 231, 1, // Opcode: C_OLE_D32 +/* 3954 */ MCD_OPC_FilterValue, 55, 17, 0, 0, // Skip to: 3976 +/* 3959 */ MCD_OPC_CheckPredicate, 60, 78, 51, 0, // Skip to: 17098 +/* 3964 */ MCD_OPC_CheckField, 6, 2, 0, 71, 51, 0, // Skip to: 17098 +/* 3971 */ MCD_OPC_Decode, 170, 11, 231, 1, // Opcode: C_ULE_D32 +/* 3976 */ MCD_OPC_FilterValue, 56, 17, 0, 0, // Skip to: 3998 +/* 3981 */ MCD_OPC_CheckPredicate, 60, 56, 51, 0, // Skip to: 17098 +/* 3986 */ MCD_OPC_CheckField, 6, 2, 0, 49, 51, 0, // Skip to: 17098 +/* 3993 */ MCD_OPC_Decode, 158, 11, 231, 1, // Opcode: C_SF_D32 +/* 3998 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 4020 +/* 4003 */ MCD_OPC_CheckPredicate, 60, 34, 51, 0, // Skip to: 17098 +/* 4008 */ MCD_OPC_CheckField, 6, 2, 0, 27, 51, 0, // Skip to: 17098 +/* 4015 */ MCD_OPC_Decode, 250, 10, 231, 1, // Opcode: C_NGLE_D32 +/* 4020 */ MCD_OPC_FilterValue, 58, 17, 0, 0, // Skip to: 4042 +/* 4025 */ MCD_OPC_CheckPredicate, 60, 12, 51, 0, // Skip to: 17098 +/* 4030 */ MCD_OPC_CheckField, 6, 2, 0, 5, 51, 0, // Skip to: 17098 +/* 4037 */ MCD_OPC_Decode, 152, 11, 231, 1, // Opcode: C_SEQ_D32 +/* 4042 */ MCD_OPC_FilterValue, 59, 17, 0, 0, // Skip to: 4064 +/* 4047 */ MCD_OPC_CheckPredicate, 60, 246, 50, 0, // Skip to: 17098 +/* 4052 */ MCD_OPC_CheckField, 6, 2, 0, 239, 50, 0, // Skip to: 17098 +/* 4059 */ MCD_OPC_Decode, 128, 11, 231, 1, // Opcode: C_NGL_D32 +/* 4064 */ MCD_OPC_FilterValue, 60, 17, 0, 0, // Skip to: 4086 +/* 4069 */ MCD_OPC_CheckPredicate, 60, 224, 50, 0, // Skip to: 17098 +/* 4074 */ MCD_OPC_CheckField, 6, 2, 0, 217, 50, 0, // Skip to: 17098 +/* 4081 */ MCD_OPC_Decode, 238, 10, 231, 1, // Opcode: C_LT_D32 +/* 4086 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 4108 +/* 4091 */ MCD_OPC_CheckPredicate, 60, 202, 50, 0, // Skip to: 17098 +/* 4096 */ MCD_OPC_CheckField, 6, 2, 0, 195, 50, 0, // Skip to: 17098 +/* 4103 */ MCD_OPC_Decode, 244, 10, 231, 1, // Opcode: C_NGE_D32 +/* 4108 */ MCD_OPC_FilterValue, 62, 17, 0, 0, // Skip to: 4130 +/* 4113 */ MCD_OPC_CheckPredicate, 60, 180, 50, 0, // Skip to: 17098 +/* 4118 */ MCD_OPC_CheckField, 6, 2, 0, 173, 50, 0, // Skip to: 17098 +/* 4125 */ MCD_OPC_Decode, 232, 10, 231, 1, // Opcode: C_LE_D32 +/* 4130 */ MCD_OPC_FilterValue, 63, 163, 50, 0, // Skip to: 17098 +/* 4135 */ MCD_OPC_CheckPredicate, 60, 158, 50, 0, // Skip to: 17098 +/* 4140 */ MCD_OPC_CheckField, 6, 2, 0, 151, 50, 0, // Skip to: 17098 +/* 4147 */ MCD_OPC_Decode, 134, 11, 231, 1, // Opcode: C_NGT_D32 +/* 4152 */ MCD_OPC_FilterValue, 20, 47, 0, 0, // Skip to: 4204 +/* 4157 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 4160 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 4182 +/* 4165 */ MCD_OPC_CheckPredicate, 47, 128, 50, 0, // Skip to: 17098 +/* 4170 */ MCD_OPC_CheckField, 16, 5, 0, 121, 50, 0, // Skip to: 17098 +/* 4177 */ MCD_OPC_Decode, 210, 10, 219, 1, // Opcode: CVT_S_W +/* 4182 */ MCD_OPC_FilterValue, 33, 111, 50, 0, // Skip to: 17098 +/* 4187 */ MCD_OPC_CheckPredicate, 55, 106, 50, 0, // Skip to: 17098 +/* 4192 */ MCD_OPC_CheckField, 16, 5, 0, 99, 50, 0, // Skip to: 17098 +/* 4199 */ MCD_OPC_Decode, 185, 10, 222, 1, // Opcode: CVT_D32_W +/* 4204 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 4219 +/* 4209 */ MCD_OPC_CheckPredicate, 30, 84, 50, 0, // Skip to: 17098 +/* 4214 */ MCD_OPC_Decode, 230, 8, 217, 1, // Opcode: BZ_B +/* 4219 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 4234 +/* 4224 */ MCD_OPC_CheckPredicate, 30, 69, 50, 0, // Skip to: 17098 +/* 4229 */ MCD_OPC_Decode, 232, 8, 232, 1, // Opcode: BZ_H +/* 4234 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 4249 +/* 4239 */ MCD_OPC_CheckPredicate, 30, 54, 50, 0, // Skip to: 17098 +/* 4244 */ MCD_OPC_Decode, 234, 8, 233, 1, // Opcode: BZ_W +/* 4249 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 4264 +/* 4254 */ MCD_OPC_CheckPredicate, 30, 39, 50, 0, // Skip to: 17098 +/* 4259 */ MCD_OPC_Decode, 231, 8, 234, 1, // Opcode: BZ_D +/* 4264 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 4279 +/* 4269 */ MCD_OPC_CheckPredicate, 30, 24, 50, 0, // Skip to: 17098 +/* 4274 */ MCD_OPC_Decode, 201, 8, 217, 1, // Opcode: BNZ_B +/* 4279 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 4294 +/* 4284 */ MCD_OPC_CheckPredicate, 30, 9, 50, 0, // Skip to: 17098 +/* 4289 */ MCD_OPC_Decode, 203, 8, 232, 1, // Opcode: BNZ_H +/* 4294 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 4309 +/* 4299 */ MCD_OPC_CheckPredicate, 30, 250, 49, 0, // Skip to: 17098 +/* 4304 */ MCD_OPC_Decode, 205, 8, 233, 1, // Opcode: BNZ_W +/* 4309 */ MCD_OPC_FilterValue, 31, 240, 49, 0, // Skip to: 17098 +/* 4314 */ MCD_OPC_CheckPredicate, 30, 235, 49, 0, // Skip to: 17098 +/* 4319 */ MCD_OPC_Decode, 202, 8, 234, 1, // Opcode: BNZ_D +/* 4324 */ MCD_OPC_FilterValue, 18, 47, 0, 0, // Skip to: 4376 +/* 4329 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 4332 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4354 +/* 4337 */ MCD_OPC_CheckPredicate, 27, 212, 49, 0, // Skip to: 17098 +/* 4342 */ MCD_OPC_CheckField, 3, 8, 0, 205, 49, 0, // Skip to: 17098 +/* 4349 */ MCD_OPC_Decode, 136, 17, 235, 1, // Opcode: MFC2 +/* 4354 */ MCD_OPC_FilterValue, 4, 195, 49, 0, // Skip to: 17098 +/* 4359 */ MCD_OPC_CheckPredicate, 27, 190, 49, 0, // Skip to: 17098 +/* 4364 */ MCD_OPC_CheckField, 3, 8, 0, 183, 49, 0, // Skip to: 17098 +/* 4371 */ MCD_OPC_Decode, 165, 18, 236, 1, // Opcode: MTC2 +/* 4376 */ MCD_OPC_FilterValue, 19, 255, 0, 0, // Skip to: 4636 +/* 4381 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 4384 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4406 +/* 4389 */ MCD_OPC_CheckPredicate, 61, 160, 49, 0, // Skip to: 17098 +/* 4394 */ MCD_OPC_CheckField, 11, 5, 0, 153, 49, 0, // Skip to: 17098 +/* 4401 */ MCD_OPC_Decode, 172, 16, 237, 1, // Opcode: LWXC1 +/* 4406 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4428 +/* 4411 */ MCD_OPC_CheckPredicate, 62, 138, 49, 0, // Skip to: 17098 +/* 4416 */ MCD_OPC_CheckField, 11, 5, 0, 131, 49, 0, // Skip to: 17098 +/* 4423 */ MCD_OPC_Decode, 196, 15, 238, 1, // Opcode: LDXC1 +/* 4428 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 4450 +/* 4433 */ MCD_OPC_CheckPredicate, 63, 116, 49, 0, // Skip to: 17098 +/* 4438 */ MCD_OPC_CheckField, 11, 5, 0, 109, 49, 0, // Skip to: 17098 +/* 4445 */ MCD_OPC_Decode, 253, 15, 238, 1, // Opcode: LUXC1 +/* 4450 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 4472 +/* 4455 */ MCD_OPC_CheckPredicate, 61, 94, 49, 0, // Skip to: 17098 +/* 4460 */ MCD_OPC_CheckField, 6, 5, 0, 87, 49, 0, // Skip to: 17098 +/* 4467 */ MCD_OPC_Decode, 165, 23, 239, 1, // Opcode: SWXC1 +/* 4472 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 4494 +/* 4477 */ MCD_OPC_CheckPredicate, 62, 72, 49, 0, // Skip to: 17098 +/* 4482 */ MCD_OPC_CheckField, 6, 5, 0, 65, 49, 0, // Skip to: 17098 +/* 4489 */ MCD_OPC_Decode, 240, 20, 240, 1, // Opcode: SDXC1 +/* 4494 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 4516 +/* 4499 */ MCD_OPC_CheckPredicate, 63, 50, 49, 0, // Skip to: 17098 +/* 4504 */ MCD_OPC_CheckField, 6, 5, 0, 43, 49, 0, // Skip to: 17098 +/* 4511 */ MCD_OPC_Decode, 253, 22, 240, 1, // Opcode: SUXC1 +/* 4516 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 4531 +/* 4521 */ MCD_OPC_CheckPredicate, 64, 28, 49, 0, // Skip to: 17098 +/* 4526 */ MCD_OPC_Decode, 218, 16, 241, 1, // Opcode: MADD_S +/* 4531 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 4546 +/* 4536 */ MCD_OPC_CheckPredicate, 65, 13, 49, 0, // Skip to: 17098 +/* 4541 */ MCD_OPC_Decode, 210, 16, 242, 1, // Opcode: MADD_D32 +/* 4546 */ MCD_OPC_FilterValue, 40, 10, 0, 0, // Skip to: 4561 +/* 4551 */ MCD_OPC_CheckPredicate, 64, 254, 48, 0, // Skip to: 17098 +/* 4556 */ MCD_OPC_Decode, 154, 18, 241, 1, // Opcode: MSUB_S +/* 4561 */ MCD_OPC_FilterValue, 41, 10, 0, 0, // Skip to: 4576 +/* 4566 */ MCD_OPC_CheckPredicate, 65, 239, 48, 0, // Skip to: 17098 +/* 4571 */ MCD_OPC_Decode, 146, 18, 242, 1, // Opcode: MSUB_D32 +/* 4576 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 4591 +/* 4581 */ MCD_OPC_CheckPredicate, 66, 224, 48, 0, // Skip to: 17098 +/* 4586 */ MCD_OPC_Decode, 142, 19, 241, 1, // Opcode: NMADD_S +/* 4591 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 4606 +/* 4596 */ MCD_OPC_CheckPredicate, 67, 209, 48, 0, // Skip to: 17098 +/* 4601 */ MCD_OPC_Decode, 139, 19, 242, 1, // Opcode: NMADD_D32 +/* 4606 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 4621 +/* 4611 */ MCD_OPC_CheckPredicate, 66, 194, 48, 0, // Skip to: 17098 +/* 4616 */ MCD_OPC_Decode, 147, 19, 241, 1, // Opcode: NMSUB_S +/* 4621 */ MCD_OPC_FilterValue, 57, 184, 48, 0, // Skip to: 17098 +/* 4626 */ MCD_OPC_CheckPredicate, 67, 179, 48, 0, // Skip to: 17098 +/* 4631 */ MCD_OPC_Decode, 144, 19, 242, 1, // Opcode: NMSUB_D32 +/* 4636 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 4651 +/* 4641 */ MCD_OPC_CheckPredicate, 39, 164, 48, 0, // Skip to: 17098 +/* 4646 */ MCD_OPC_Decode, 197, 7, 201, 1, // Opcode: BEQL +/* 4651 */ MCD_OPC_FilterValue, 21, 107, 0, 0, // Skip to: 4763 +/* 4656 */ MCD_OPC_ExtractField, 0, 16, // Inst{15-0} ... +/* 4659 */ MCD_OPC_FilterValue, 123, 9, 0, 0, // Skip to: 4673 +/* 4664 */ MCD_OPC_CheckPredicate, 19, 19, 0, 0, // Skip to: 4688 +/* 4669 */ MCD_OPC_Decode, 233, 13, 124, // Opcode: FMOV_S_MM +/* 4673 */ MCD_OPC_FilterValue, 251, 22, 9, 0, 0, // Skip to: 4688 +/* 4679 */ MCD_OPC_CheckPredicate, 19, 4, 0, 0, // Skip to: 4688 +/* 4684 */ MCD_OPC_Decode, 252, 13, 124, // Opcode: FNEG_S_MM +/* 4688 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... +/* 4691 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 4706 +/* 4696 */ MCD_OPC_CheckPredicate, 19, 52, 0, 0, // Skip to: 4753 +/* 4701 */ MCD_OPC_Decode, 143, 13, 164, 1, // Opcode: FADD_S_MM +/* 4706 */ MCD_OPC_FilterValue, 112, 10, 0, 0, // Skip to: 4721 +/* 4711 */ MCD_OPC_CheckPredicate, 19, 37, 0, 0, // Skip to: 4753 +/* 4716 */ MCD_OPC_Decode, 161, 14, 164, 1, // Opcode: FSUB_S_MM +/* 4721 */ MCD_OPC_FilterValue, 176, 1, 10, 0, 0, // Skip to: 4737 +/* 4727 */ MCD_OPC_CheckPredicate, 19, 21, 0, 0, // Skip to: 4753 +/* 4732 */ MCD_OPC_Decode, 244, 13, 164, 1, // Opcode: FMUL_S_MM +/* 4737 */ MCD_OPC_FilterValue, 240, 1, 10, 0, 0, // Skip to: 4753 +/* 4743 */ MCD_OPC_CheckPredicate, 19, 5, 0, 0, // Skip to: 4753 +/* 4748 */ MCD_OPC_Decode, 181, 13, 164, 1, // Opcode: FDIV_S_MM +/* 4753 */ MCD_OPC_CheckPredicate, 39, 52, 48, 0, // Skip to: 17098 +/* 4758 */ MCD_OPC_Decode, 187, 8, 201, 1, // Opcode: BNEL +/* 4763 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 4785 +/* 4768 */ MCD_OPC_CheckPredicate, 39, 37, 48, 0, // Skip to: 17098 +/* 4773 */ MCD_OPC_CheckField, 16, 5, 0, 30, 48, 0, // Skip to: 17098 +/* 4780 */ MCD_OPC_Decode, 141, 8, 197, 1, // Opcode: BLEZL +/* 4785 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 4807 +/* 4790 */ MCD_OPC_CheckPredicate, 39, 15, 48, 0, // Skip to: 17098 +/* 4795 */ MCD_OPC_CheckField, 16, 5, 0, 8, 48, 0, // Skip to: 17098 +/* 4802 */ MCD_OPC_Decode, 239, 7, 197, 1, // Opcode: BGTZL +/* 4807 */ MCD_OPC_FilterValue, 28, 15, 1, 0, // Skip to: 5083 +/* 4812 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 4815 */ MCD_OPC_FilterValue, 0, 42, 0, 0, // Skip to: 4862 +/* 4820 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 4823 */ MCD_OPC_FilterValue, 0, 238, 47, 0, // Skip to: 17098 +/* 4828 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 4831 */ MCD_OPC_FilterValue, 0, 230, 47, 0, // Skip to: 17098 +/* 4836 */ MCD_OPC_CheckPredicate, 68, 11, 0, 0, // Skip to: 4852 +/* 4841 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 4852 +/* 4848 */ MCD_OPC_Decode, 195, 16, 80, // Opcode: MADD +/* 4852 */ MCD_OPC_CheckPredicate, 37, 209, 47, 0, // Skip to: 17098 +/* 4857 */ MCD_OPC_Decode, 213, 16, 243, 1, // Opcode: MADD_DSP +/* 4862 */ MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 4909 +/* 4867 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 4870 */ MCD_OPC_FilterValue, 0, 191, 47, 0, // Skip to: 17098 +/* 4875 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 4878 */ MCD_OPC_FilterValue, 0, 183, 47, 0, // Skip to: 17098 +/* 4883 */ MCD_OPC_CheckPredicate, 68, 11, 0, 0, // Skip to: 4899 +/* 4888 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 4899 +/* 4895 */ MCD_OPC_Decode, 202, 16, 80, // Opcode: MADDU +/* 4899 */ MCD_OPC_CheckPredicate, 37, 162, 47, 0, // Skip to: 17098 +/* 4904 */ MCD_OPC_Decode, 203, 16, 243, 1, // Opcode: MADDU_DSP +/* 4909 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 4930 +/* 4914 */ MCD_OPC_CheckPredicate, 68, 147, 47, 0, // Skip to: 17098 +/* 4919 */ MCD_OPC_CheckField, 6, 5, 0, 140, 47, 0, // Skip to: 17098 +/* 4926 */ MCD_OPC_Decode, 205, 18, 61, // Opcode: MUL +/* 4930 */ MCD_OPC_FilterValue, 4, 42, 0, 0, // Skip to: 4977 +/* 4935 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 4938 */ MCD_OPC_FilterValue, 0, 123, 47, 0, // Skip to: 17098 +/* 4943 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 4946 */ MCD_OPC_FilterValue, 0, 115, 47, 0, // Skip to: 17098 +/* 4951 */ MCD_OPC_CheckPredicate, 68, 11, 0, 0, // Skip to: 4967 +/* 4956 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 4967 +/* 4963 */ MCD_OPC_Decode, 131, 18, 80, // Opcode: MSUB +/* 4967 */ MCD_OPC_CheckPredicate, 37, 94, 47, 0, // Skip to: 17098 +/* 4972 */ MCD_OPC_Decode, 149, 18, 243, 1, // Opcode: MSUB_DSP +/* 4977 */ MCD_OPC_FilterValue, 5, 42, 0, 0, // Skip to: 5024 +/* 4982 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 4985 */ MCD_OPC_FilterValue, 0, 76, 47, 0, // Skip to: 17098 +/* 4990 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 4993 */ MCD_OPC_FilterValue, 0, 68, 47, 0, // Skip to: 17098 +/* 4998 */ MCD_OPC_CheckPredicate, 68, 11, 0, 0, // Skip to: 5014 +/* 5003 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 5014 +/* 5010 */ MCD_OPC_Decode, 138, 18, 80, // Opcode: MSUBU +/* 5014 */ MCD_OPC_CheckPredicate, 37, 47, 47, 0, // Skip to: 17098 +/* 5019 */ MCD_OPC_Decode, 139, 18, 243, 1, // Opcode: MSUBU_DSP +/* 5024 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 5046 +/* 5029 */ MCD_OPC_CheckPredicate, 68, 32, 47, 0, // Skip to: 17098 +/* 5034 */ MCD_OPC_CheckField, 6, 5, 0, 25, 47, 0, // Skip to: 17098 +/* 5041 */ MCD_OPC_Decode, 193, 9, 244, 1, // Opcode: CLZ +/* 5046 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 5068 +/* 5051 */ MCD_OPC_CheckPredicate, 68, 10, 47, 0, // Skip to: 17098 +/* 5056 */ MCD_OPC_CheckField, 6, 5, 0, 3, 47, 0, // Skip to: 17098 +/* 5063 */ MCD_OPC_Decode, 172, 9, 244, 1, // Opcode: CLO +/* 5068 */ MCD_OPC_FilterValue, 63, 249, 46, 0, // Skip to: 17098 +/* 5073 */ MCD_OPC_CheckPredicate, 68, 244, 46, 0, // Skip to: 17098 +/* 5078 */ MCD_OPC_Decode, 219, 20, 188, 1, // Opcode: SDBBP +/* 5083 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 5098 +/* 5088 */ MCD_OPC_CheckPredicate, 68, 229, 46, 0, // Skip to: 17098 +/* 5093 */ MCD_OPC_Decode, 251, 14, 200, 1, // Opcode: JALX +/* 5098 */ MCD_OPC_FilterValue, 30, 201, 32, 0, // Skip to: 13496 +/* 5103 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 5106 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 5174 +/* 5111 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 5114 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5129 +/* 5119 */ MCD_OPC_CheckPredicate, 30, 198, 46, 0, // Skip to: 17098 +/* 5124 */ MCD_OPC_Decode, 224, 6, 245, 1, // Opcode: ANDI_B +/* 5129 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5144 +/* 5134 */ MCD_OPC_CheckPredicate, 30, 183, 46, 0, // Skip to: 17098 +/* 5139 */ MCD_OPC_Decode, 168, 19, 245, 1, // Opcode: ORI_B +/* 5144 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 5159 +/* 5149 */ MCD_OPC_CheckPredicate, 30, 168, 46, 0, // Skip to: 17098 +/* 5154 */ MCD_OPC_Decode, 153, 19, 245, 1, // Opcode: NORI_B +/* 5159 */ MCD_OPC_FilterValue, 3, 158, 46, 0, // Skip to: 17098 +/* 5164 */ MCD_OPC_CheckPredicate, 30, 153, 46, 0, // Skip to: 17098 +/* 5169 */ MCD_OPC_Decode, 177, 24, 245, 1, // Opcode: XORI_B +/* 5174 */ MCD_OPC_FilterValue, 1, 48, 0, 0, // Skip to: 5227 +/* 5179 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 5182 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5197 +/* 5187 */ MCD_OPC_CheckPredicate, 30, 130, 46, 0, // Skip to: 17098 +/* 5192 */ MCD_OPC_Decode, 166, 8, 246, 1, // Opcode: BMNZI_B +/* 5197 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5212 +/* 5202 */ MCD_OPC_CheckPredicate, 30, 115, 46, 0, // Skip to: 17098 +/* 5207 */ MCD_OPC_Decode, 168, 8, 246, 1, // Opcode: BMZI_B +/* 5212 */ MCD_OPC_FilterValue, 2, 105, 46, 0, // Skip to: 17098 +/* 5217 */ MCD_OPC_CheckPredicate, 30, 100, 46, 0, // Skip to: 17098 +/* 5222 */ MCD_OPC_Decode, 219, 8, 246, 1, // Opcode: BSELI_B +/* 5227 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 5280 +/* 5232 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 5235 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5250 +/* 5240 */ MCD_OPC_CheckPredicate, 30, 77, 46, 0, // Skip to: 17098 +/* 5245 */ MCD_OPC_Decode, 150, 21, 245, 1, // Opcode: SHF_B +/* 5250 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5265 +/* 5255 */ MCD_OPC_CheckPredicate, 30, 62, 46, 0, // Skip to: 17098 +/* 5260 */ MCD_OPC_Decode, 151, 21, 247, 1, // Opcode: SHF_H +/* 5265 */ MCD_OPC_FilterValue, 2, 52, 46, 0, // Skip to: 17098 +/* 5270 */ MCD_OPC_CheckPredicate, 30, 47, 46, 0, // Skip to: 17098 +/* 5275 */ MCD_OPC_Decode, 152, 21, 248, 1, // Opcode: SHF_W +/* 5280 */ MCD_OPC_FilterValue, 6, 107, 1, 0, // Skip to: 5648 +/* 5285 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 5288 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5303 +/* 5293 */ MCD_OPC_CheckPredicate, 30, 24, 46, 0, // Skip to: 17098 +/* 5298 */ MCD_OPC_Decode, 185, 6, 249, 1, // Opcode: ADDVI_B +/* 5303 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5318 +/* 5308 */ MCD_OPC_CheckPredicate, 30, 9, 46, 0, // Skip to: 17098 +/* 5313 */ MCD_OPC_Decode, 187, 6, 250, 1, // Opcode: ADDVI_H +/* 5318 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 5333 +/* 5323 */ MCD_OPC_CheckPredicate, 30, 250, 45, 0, // Skip to: 17098 +/* 5328 */ MCD_OPC_Decode, 188, 6, 251, 1, // Opcode: ADDVI_W +/* 5333 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 5348 +/* 5338 */ MCD_OPC_CheckPredicate, 30, 235, 45, 0, // Skip to: 17098 +/* 5343 */ MCD_OPC_Decode, 186, 6, 252, 1, // Opcode: ADDVI_D +/* 5348 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 5363 +/* 5353 */ MCD_OPC_CheckPredicate, 30, 220, 45, 0, // Skip to: 17098 +/* 5358 */ MCD_OPC_Decode, 238, 22, 249, 1, // Opcode: SUBVI_B +/* 5363 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 5378 +/* 5368 */ MCD_OPC_CheckPredicate, 30, 205, 45, 0, // Skip to: 17098 +/* 5373 */ MCD_OPC_Decode, 240, 22, 250, 1, // Opcode: SUBVI_H +/* 5378 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 5393 +/* 5383 */ MCD_OPC_CheckPredicate, 30, 190, 45, 0, // Skip to: 17098 +/* 5388 */ MCD_OPC_Decode, 241, 22, 251, 1, // Opcode: SUBVI_W +/* 5393 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 5408 +/* 5398 */ MCD_OPC_CheckPredicate, 30, 175, 45, 0, // Skip to: 17098 +/* 5403 */ MCD_OPC_Decode, 239, 22, 252, 1, // Opcode: SUBVI_D +/* 5408 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 5423 +/* 5413 */ MCD_OPC_CheckPredicate, 30, 160, 45, 0, // Skip to: 17098 +/* 5418 */ MCD_OPC_Decode, 232, 16, 249, 1, // Opcode: MAXI_S_B +/* 5423 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 5438 +/* 5428 */ MCD_OPC_CheckPredicate, 30, 145, 45, 0, // Skip to: 17098 +/* 5433 */ MCD_OPC_Decode, 234, 16, 250, 1, // Opcode: MAXI_S_H +/* 5438 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 5453 +/* 5443 */ MCD_OPC_CheckPredicate, 30, 130, 45, 0, // Skip to: 17098 +/* 5448 */ MCD_OPC_Decode, 235, 16, 251, 1, // Opcode: MAXI_S_W +/* 5453 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 5468 +/* 5458 */ MCD_OPC_CheckPredicate, 30, 115, 45, 0, // Skip to: 17098 +/* 5463 */ MCD_OPC_Decode, 233, 16, 252, 1, // Opcode: MAXI_S_D +/* 5468 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 5483 +/* 5473 */ MCD_OPC_CheckPredicate, 30, 100, 45, 0, // Skip to: 17098 +/* 5478 */ MCD_OPC_Decode, 236, 16, 249, 1, // Opcode: MAXI_U_B +/* 5483 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5498 +/* 5488 */ MCD_OPC_CheckPredicate, 30, 85, 45, 0, // Skip to: 17098 +/* 5493 */ MCD_OPC_Decode, 238, 16, 250, 1, // Opcode: MAXI_U_H +/* 5498 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 5513 +/* 5503 */ MCD_OPC_CheckPredicate, 30, 70, 45, 0, // Skip to: 17098 +/* 5508 */ MCD_OPC_Decode, 239, 16, 251, 1, // Opcode: MAXI_U_W +/* 5513 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5528 +/* 5518 */ MCD_OPC_CheckPredicate, 30, 55, 45, 0, // Skip to: 17098 +/* 5523 */ MCD_OPC_Decode, 237, 16, 252, 1, // Opcode: MAXI_U_D +/* 5528 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 5543 +/* 5533 */ MCD_OPC_CheckPredicate, 30, 40, 45, 0, // Skip to: 17098 +/* 5538 */ MCD_OPC_Decode, 168, 17, 249, 1, // Opcode: MINI_S_B +/* 5543 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 5558 +/* 5548 */ MCD_OPC_CheckPredicate, 30, 25, 45, 0, // Skip to: 17098 +/* 5553 */ MCD_OPC_Decode, 170, 17, 250, 1, // Opcode: MINI_S_H +/* 5558 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 5573 +/* 5563 */ MCD_OPC_CheckPredicate, 30, 10, 45, 0, // Skip to: 17098 +/* 5568 */ MCD_OPC_Decode, 171, 17, 251, 1, // Opcode: MINI_S_W +/* 5573 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 5588 +/* 5578 */ MCD_OPC_CheckPredicate, 30, 251, 44, 0, // Skip to: 17098 +/* 5583 */ MCD_OPC_Decode, 169, 17, 252, 1, // Opcode: MINI_S_D +/* 5588 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 5603 +/* 5593 */ MCD_OPC_CheckPredicate, 30, 236, 44, 0, // Skip to: 17098 +/* 5598 */ MCD_OPC_Decode, 172, 17, 249, 1, // Opcode: MINI_U_B +/* 5603 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 5618 +/* 5608 */ MCD_OPC_CheckPredicate, 30, 221, 44, 0, // Skip to: 17098 +/* 5613 */ MCD_OPC_Decode, 174, 17, 250, 1, // Opcode: MINI_U_H +/* 5618 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 5633 +/* 5623 */ MCD_OPC_CheckPredicate, 30, 206, 44, 0, // Skip to: 17098 +/* 5628 */ MCD_OPC_Decode, 175, 17, 251, 1, // Opcode: MINI_U_W +/* 5633 */ MCD_OPC_FilterValue, 23, 196, 44, 0, // Skip to: 17098 +/* 5638 */ MCD_OPC_CheckPredicate, 30, 191, 44, 0, // Skip to: 17098 +/* 5643 */ MCD_OPC_Decode, 173, 17, 252, 1, // Opcode: MINI_U_D +/* 5648 */ MCD_OPC_FilterValue, 7, 107, 1, 0, // Skip to: 6016 +/* 5653 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 5656 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5671 +/* 5661 */ MCD_OPC_CheckPredicate, 30, 168, 44, 0, // Skip to: 17098 +/* 5666 */ MCD_OPC_Decode, 136, 9, 249, 1, // Opcode: CEQI_B +/* 5671 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5686 +/* 5676 */ MCD_OPC_CheckPredicate, 30, 153, 44, 0, // Skip to: 17098 +/* 5681 */ MCD_OPC_Decode, 138, 9, 250, 1, // Opcode: CEQI_H +/* 5686 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 5701 +/* 5691 */ MCD_OPC_CheckPredicate, 30, 138, 44, 0, // Skip to: 17098 +/* 5696 */ MCD_OPC_Decode, 139, 9, 251, 1, // Opcode: CEQI_W +/* 5701 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 5716 +/* 5706 */ MCD_OPC_CheckPredicate, 30, 123, 44, 0, // Skip to: 17098 +/* 5711 */ MCD_OPC_Decode, 137, 9, 252, 1, // Opcode: CEQI_D +/* 5716 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 5731 +/* 5721 */ MCD_OPC_CheckPredicate, 30, 108, 44, 0, // Skip to: 17098 +/* 5726 */ MCD_OPC_Decode, 177, 9, 249, 1, // Opcode: CLTI_S_B +/* 5731 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 5746 +/* 5736 */ MCD_OPC_CheckPredicate, 30, 93, 44, 0, // Skip to: 17098 +/* 5741 */ MCD_OPC_Decode, 179, 9, 250, 1, // Opcode: CLTI_S_H +/* 5746 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 5761 +/* 5751 */ MCD_OPC_CheckPredicate, 30, 78, 44, 0, // Skip to: 17098 +/* 5756 */ MCD_OPC_Decode, 180, 9, 251, 1, // Opcode: CLTI_S_W +/* 5761 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 5776 +/* 5766 */ MCD_OPC_CheckPredicate, 30, 63, 44, 0, // Skip to: 17098 +/* 5771 */ MCD_OPC_Decode, 178, 9, 252, 1, // Opcode: CLTI_S_D +/* 5776 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 5791 +/* 5781 */ MCD_OPC_CheckPredicate, 30, 48, 44, 0, // Skip to: 17098 +/* 5786 */ MCD_OPC_Decode, 181, 9, 249, 1, // Opcode: CLTI_U_B +/* 5791 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5806 +/* 5796 */ MCD_OPC_CheckPredicate, 30, 33, 44, 0, // Skip to: 17098 +/* 5801 */ MCD_OPC_Decode, 183, 9, 250, 1, // Opcode: CLTI_U_H +/* 5806 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 5821 +/* 5811 */ MCD_OPC_CheckPredicate, 30, 18, 44, 0, // Skip to: 17098 +/* 5816 */ MCD_OPC_Decode, 184, 9, 251, 1, // Opcode: CLTI_U_W +/* 5821 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5836 +/* 5826 */ MCD_OPC_CheckPredicate, 30, 3, 44, 0, // Skip to: 17098 +/* 5831 */ MCD_OPC_Decode, 182, 9, 252, 1, // Opcode: CLTI_U_D +/* 5836 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 5851 +/* 5841 */ MCD_OPC_CheckPredicate, 30, 244, 43, 0, // Skip to: 17098 +/* 5846 */ MCD_OPC_Decode, 156, 9, 249, 1, // Opcode: CLEI_S_B +/* 5851 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 5866 +/* 5856 */ MCD_OPC_CheckPredicate, 30, 229, 43, 0, // Skip to: 17098 +/* 5861 */ MCD_OPC_Decode, 158, 9, 250, 1, // Opcode: CLEI_S_H +/* 5866 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 5881 +/* 5871 */ MCD_OPC_CheckPredicate, 30, 214, 43, 0, // Skip to: 17098 +/* 5876 */ MCD_OPC_Decode, 159, 9, 251, 1, // Opcode: CLEI_S_W +/* 5881 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 5896 +/* 5886 */ MCD_OPC_CheckPredicate, 30, 199, 43, 0, // Skip to: 17098 +/* 5891 */ MCD_OPC_Decode, 157, 9, 252, 1, // Opcode: CLEI_S_D +/* 5896 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 5911 +/* 5901 */ MCD_OPC_CheckPredicate, 30, 184, 43, 0, // Skip to: 17098 +/* 5906 */ MCD_OPC_Decode, 160, 9, 249, 1, // Opcode: CLEI_U_B +/* 5911 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 5926 +/* 5916 */ MCD_OPC_CheckPredicate, 30, 169, 43, 0, // Skip to: 17098 +/* 5921 */ MCD_OPC_Decode, 162, 9, 250, 1, // Opcode: CLEI_U_H +/* 5926 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 5941 +/* 5931 */ MCD_OPC_CheckPredicate, 30, 154, 43, 0, // Skip to: 17098 +/* 5936 */ MCD_OPC_Decode, 163, 9, 251, 1, // Opcode: CLEI_U_W +/* 5941 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 5956 +/* 5946 */ MCD_OPC_CheckPredicate, 30, 139, 43, 0, // Skip to: 17098 +/* 5951 */ MCD_OPC_Decode, 161, 9, 252, 1, // Opcode: CLEI_U_D +/* 5956 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 5971 +/* 5961 */ MCD_OPC_CheckPredicate, 30, 124, 43, 0, // Skip to: 17098 +/* 5966 */ MCD_OPC_Decode, 189, 15, 253, 1, // Opcode: LDI_B +/* 5971 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 5986 +/* 5976 */ MCD_OPC_CheckPredicate, 30, 109, 43, 0, // Skip to: 17098 +/* 5981 */ MCD_OPC_Decode, 191, 15, 254, 1, // Opcode: LDI_H +/* 5986 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 6001 +/* 5991 */ MCD_OPC_CheckPredicate, 30, 94, 43, 0, // Skip to: 17098 +/* 5996 */ MCD_OPC_Decode, 192, 15, 255, 1, // Opcode: LDI_W +/* 6001 */ MCD_OPC_FilterValue, 27, 84, 43, 0, // Skip to: 17098 +/* 6006 */ MCD_OPC_CheckPredicate, 30, 79, 43, 0, // Skip to: 17098 +/* 6011 */ MCD_OPC_Decode, 190, 15, 128, 2, // Opcode: LDI_D +/* 6016 */ MCD_OPC_FilterValue, 9, 155, 2, 0, // Skip to: 6688 +/* 6021 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 6024 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6039 +/* 6029 */ MCD_OPC_CheckPredicate, 30, 56, 43, 0, // Skip to: 17098 +/* 6034 */ MCD_OPC_Decode, 226, 21, 129, 2, // Opcode: SLLI_D +/* 6039 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 6107 +/* 6044 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6047 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6062 +/* 6052 */ MCD_OPC_CheckPredicate, 30, 33, 43, 0, // Skip to: 17098 +/* 6057 */ MCD_OPC_Decode, 228, 21, 251, 1, // Opcode: SLLI_W +/* 6062 */ MCD_OPC_FilterValue, 1, 23, 43, 0, // Skip to: 17098 +/* 6067 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6070 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6085 +/* 6075 */ MCD_OPC_CheckPredicate, 30, 10, 43, 0, // Skip to: 17098 +/* 6080 */ MCD_OPC_Decode, 227, 21, 130, 2, // Opcode: SLLI_H +/* 6085 */ MCD_OPC_FilterValue, 1, 0, 43, 0, // Skip to: 17098 +/* 6090 */ MCD_OPC_CheckPredicate, 30, 251, 42, 0, // Skip to: 17098 +/* 6095 */ MCD_OPC_CheckField, 19, 1, 0, 244, 42, 0, // Skip to: 17098 +/* 6102 */ MCD_OPC_Decode, 225, 21, 131, 2, // Opcode: SLLI_B +/* 6107 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6122 +/* 6112 */ MCD_OPC_CheckPredicate, 30, 229, 42, 0, // Skip to: 17098 +/* 6117 */ MCD_OPC_Decode, 140, 22, 129, 2, // Opcode: SRAI_D +/* 6122 */ MCD_OPC_FilterValue, 3, 63, 0, 0, // Skip to: 6190 +/* 6127 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6130 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6145 +/* 6135 */ MCD_OPC_CheckPredicate, 30, 206, 42, 0, // Skip to: 17098 +/* 6140 */ MCD_OPC_Decode, 142, 22, 251, 1, // Opcode: SRAI_W +/* 6145 */ MCD_OPC_FilterValue, 1, 196, 42, 0, // Skip to: 17098 +/* 6150 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6153 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6168 +/* 6158 */ MCD_OPC_CheckPredicate, 30, 183, 42, 0, // Skip to: 17098 +/* 6163 */ MCD_OPC_Decode, 141, 22, 130, 2, // Opcode: SRAI_H +/* 6168 */ MCD_OPC_FilterValue, 1, 173, 42, 0, // Skip to: 17098 +/* 6173 */ MCD_OPC_CheckPredicate, 30, 168, 42, 0, // Skip to: 17098 +/* 6178 */ MCD_OPC_CheckField, 19, 1, 0, 161, 42, 0, // Skip to: 17098 +/* 6185 */ MCD_OPC_Decode, 139, 22, 131, 2, // Opcode: SRAI_B +/* 6190 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 6205 +/* 6195 */ MCD_OPC_CheckPredicate, 30, 146, 42, 0, // Skip to: 17098 +/* 6200 */ MCD_OPC_Decode, 165, 22, 129, 2, // Opcode: SRLI_D +/* 6205 */ MCD_OPC_FilterValue, 5, 63, 0, 0, // Skip to: 6273 +/* 6210 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6213 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6228 +/* 6218 */ MCD_OPC_CheckPredicate, 30, 123, 42, 0, // Skip to: 17098 +/* 6223 */ MCD_OPC_Decode, 167, 22, 251, 1, // Opcode: SRLI_W +/* 6228 */ MCD_OPC_FilterValue, 1, 113, 42, 0, // Skip to: 17098 +/* 6233 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6236 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6251 +/* 6241 */ MCD_OPC_CheckPredicate, 30, 100, 42, 0, // Skip to: 17098 +/* 6246 */ MCD_OPC_Decode, 166, 22, 130, 2, // Opcode: SRLI_H +/* 6251 */ MCD_OPC_FilterValue, 1, 90, 42, 0, // Skip to: 17098 +/* 6256 */ MCD_OPC_CheckPredicate, 30, 85, 42, 0, // Skip to: 17098 +/* 6261 */ MCD_OPC_CheckField, 19, 1, 0, 78, 42, 0, // Skip to: 17098 +/* 6268 */ MCD_OPC_Decode, 164, 22, 131, 2, // Opcode: SRLI_B +/* 6273 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 6288 +/* 6278 */ MCD_OPC_CheckPredicate, 30, 63, 42, 0, // Skip to: 17098 +/* 6283 */ MCD_OPC_Decode, 179, 7, 129, 2, // Opcode: BCLRI_D +/* 6288 */ MCD_OPC_FilterValue, 7, 63, 0, 0, // Skip to: 6356 +/* 6293 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6296 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6311 +/* 6301 */ MCD_OPC_CheckPredicate, 30, 40, 42, 0, // Skip to: 17098 +/* 6306 */ MCD_OPC_Decode, 181, 7, 251, 1, // Opcode: BCLRI_W +/* 6311 */ MCD_OPC_FilterValue, 1, 30, 42, 0, // Skip to: 17098 +/* 6316 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6319 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6334 +/* 6324 */ MCD_OPC_CheckPredicate, 30, 17, 42, 0, // Skip to: 17098 +/* 6329 */ MCD_OPC_Decode, 180, 7, 130, 2, // Opcode: BCLRI_H +/* 6334 */ MCD_OPC_FilterValue, 1, 7, 42, 0, // Skip to: 17098 +/* 6339 */ MCD_OPC_CheckPredicate, 30, 2, 42, 0, // Skip to: 17098 +/* 6344 */ MCD_OPC_CheckField, 19, 1, 0, 251, 41, 0, // Skip to: 17098 +/* 6351 */ MCD_OPC_Decode, 178, 7, 131, 2, // Opcode: BCLRI_B +/* 6356 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 6371 +/* 6361 */ MCD_OPC_CheckPredicate, 30, 236, 41, 0, // Skip to: 17098 +/* 6366 */ MCD_OPC_Decode, 222, 8, 129, 2, // Opcode: BSETI_D +/* 6371 */ MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 6439 +/* 6376 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6379 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6394 +/* 6384 */ MCD_OPC_CheckPredicate, 30, 213, 41, 0, // Skip to: 17098 +/* 6389 */ MCD_OPC_Decode, 224, 8, 251, 1, // Opcode: BSETI_W +/* 6394 */ MCD_OPC_FilterValue, 1, 203, 41, 0, // Skip to: 17098 +/* 6399 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6402 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6417 +/* 6407 */ MCD_OPC_CheckPredicate, 30, 190, 41, 0, // Skip to: 17098 +/* 6412 */ MCD_OPC_Decode, 223, 8, 130, 2, // Opcode: BSETI_H +/* 6417 */ MCD_OPC_FilterValue, 1, 180, 41, 0, // Skip to: 17098 +/* 6422 */ MCD_OPC_CheckPredicate, 30, 175, 41, 0, // Skip to: 17098 +/* 6427 */ MCD_OPC_CheckField, 19, 1, 0, 168, 41, 0, // Skip to: 17098 +/* 6434 */ MCD_OPC_Decode, 221, 8, 131, 2, // Opcode: BSETI_B +/* 6439 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 6454 +/* 6444 */ MCD_OPC_CheckPredicate, 30, 153, 41, 0, // Skip to: 17098 +/* 6449 */ MCD_OPC_Decode, 179, 8, 129, 2, // Opcode: BNEGI_D +/* 6454 */ MCD_OPC_FilterValue, 11, 63, 0, 0, // Skip to: 6522 +/* 6459 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6462 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6477 +/* 6467 */ MCD_OPC_CheckPredicate, 30, 130, 41, 0, // Skip to: 17098 +/* 6472 */ MCD_OPC_Decode, 181, 8, 251, 1, // Opcode: BNEGI_W +/* 6477 */ MCD_OPC_FilterValue, 1, 120, 41, 0, // Skip to: 17098 +/* 6482 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6485 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6500 +/* 6490 */ MCD_OPC_CheckPredicate, 30, 107, 41, 0, // Skip to: 17098 +/* 6495 */ MCD_OPC_Decode, 180, 8, 130, 2, // Opcode: BNEGI_H +/* 6500 */ MCD_OPC_FilterValue, 1, 97, 41, 0, // Skip to: 17098 +/* 6505 */ MCD_OPC_CheckPredicate, 30, 92, 41, 0, // Skip to: 17098 +/* 6510 */ MCD_OPC_CheckField, 19, 1, 0, 85, 41, 0, // Skip to: 17098 +/* 6517 */ MCD_OPC_Decode, 178, 8, 131, 2, // Opcode: BNEGI_B +/* 6522 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 6537 +/* 6527 */ MCD_OPC_CheckPredicate, 30, 70, 41, 0, // Skip to: 17098 +/* 6532 */ MCD_OPC_Decode, 242, 7, 132, 2, // Opcode: BINSLI_D +/* 6537 */ MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 6605 +/* 6542 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6545 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6560 +/* 6550 */ MCD_OPC_CheckPredicate, 30, 47, 41, 0, // Skip to: 17098 +/* 6555 */ MCD_OPC_Decode, 244, 7, 133, 2, // Opcode: BINSLI_W +/* 6560 */ MCD_OPC_FilterValue, 1, 37, 41, 0, // Skip to: 17098 +/* 6565 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6568 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6583 +/* 6573 */ MCD_OPC_CheckPredicate, 30, 24, 41, 0, // Skip to: 17098 +/* 6578 */ MCD_OPC_Decode, 243, 7, 134, 2, // Opcode: BINSLI_H +/* 6583 */ MCD_OPC_FilterValue, 1, 14, 41, 0, // Skip to: 17098 +/* 6588 */ MCD_OPC_CheckPredicate, 30, 9, 41, 0, // Skip to: 17098 +/* 6593 */ MCD_OPC_CheckField, 19, 1, 0, 2, 41, 0, // Skip to: 17098 +/* 6600 */ MCD_OPC_Decode, 241, 7, 135, 2, // Opcode: BINSLI_B +/* 6605 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 6620 +/* 6610 */ MCD_OPC_CheckPredicate, 30, 243, 40, 0, // Skip to: 17098 +/* 6615 */ MCD_OPC_Decode, 250, 7, 132, 2, // Opcode: BINSRI_D +/* 6620 */ MCD_OPC_FilterValue, 15, 233, 40, 0, // Skip to: 17098 +/* 6625 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6628 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6643 +/* 6633 */ MCD_OPC_CheckPredicate, 30, 220, 40, 0, // Skip to: 17098 +/* 6638 */ MCD_OPC_Decode, 252, 7, 133, 2, // Opcode: BINSRI_W +/* 6643 */ MCD_OPC_FilterValue, 1, 210, 40, 0, // Skip to: 17098 +/* 6648 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6651 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6666 +/* 6656 */ MCD_OPC_CheckPredicate, 30, 197, 40, 0, // Skip to: 17098 +/* 6661 */ MCD_OPC_Decode, 251, 7, 134, 2, // Opcode: BINSRI_H +/* 6666 */ MCD_OPC_FilterValue, 1, 187, 40, 0, // Skip to: 17098 +/* 6671 */ MCD_OPC_CheckPredicate, 30, 182, 40, 0, // Skip to: 17098 +/* 6676 */ MCD_OPC_CheckField, 19, 1, 0, 175, 40, 0, // Skip to: 17098 +/* 6683 */ MCD_OPC_Decode, 249, 7, 135, 2, // Opcode: BINSRI_B +/* 6688 */ MCD_OPC_FilterValue, 10, 79, 1, 0, // Skip to: 7028 +/* 6693 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 6696 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6711 +/* 6701 */ MCD_OPC_CheckPredicate, 30, 152, 40, 0, // Skip to: 17098 +/* 6706 */ MCD_OPC_Decode, 184, 20, 129, 2, // Opcode: SAT_S_D +/* 6711 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 6779 +/* 6716 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6719 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6734 +/* 6724 */ MCD_OPC_CheckPredicate, 30, 129, 40, 0, // Skip to: 17098 +/* 6729 */ MCD_OPC_Decode, 186, 20, 251, 1, // Opcode: SAT_S_W +/* 6734 */ MCD_OPC_FilterValue, 1, 119, 40, 0, // Skip to: 17098 +/* 6739 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6742 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6757 +/* 6747 */ MCD_OPC_CheckPredicate, 30, 106, 40, 0, // Skip to: 17098 +/* 6752 */ MCD_OPC_Decode, 185, 20, 130, 2, // Opcode: SAT_S_H +/* 6757 */ MCD_OPC_FilterValue, 1, 96, 40, 0, // Skip to: 17098 +/* 6762 */ MCD_OPC_CheckPredicate, 30, 91, 40, 0, // Skip to: 17098 +/* 6767 */ MCD_OPC_CheckField, 19, 1, 0, 84, 40, 0, // Skip to: 17098 +/* 6774 */ MCD_OPC_Decode, 183, 20, 131, 2, // Opcode: SAT_S_B +/* 6779 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6794 +/* 6784 */ MCD_OPC_CheckPredicate, 30, 69, 40, 0, // Skip to: 17098 +/* 6789 */ MCD_OPC_Decode, 188, 20, 129, 2, // Opcode: SAT_U_D +/* 6794 */ MCD_OPC_FilterValue, 3, 63, 0, 0, // Skip to: 6862 +/* 6799 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6802 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6817 +/* 6807 */ MCD_OPC_CheckPredicate, 30, 46, 40, 0, // Skip to: 17098 +/* 6812 */ MCD_OPC_Decode, 190, 20, 251, 1, // Opcode: SAT_U_W +/* 6817 */ MCD_OPC_FilterValue, 1, 36, 40, 0, // Skip to: 17098 +/* 6822 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6825 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6840 +/* 6830 */ MCD_OPC_CheckPredicate, 30, 23, 40, 0, // Skip to: 17098 +/* 6835 */ MCD_OPC_Decode, 189, 20, 130, 2, // Opcode: SAT_U_H +/* 6840 */ MCD_OPC_FilterValue, 1, 13, 40, 0, // Skip to: 17098 +/* 6845 */ MCD_OPC_CheckPredicate, 30, 8, 40, 0, // Skip to: 17098 +/* 6850 */ MCD_OPC_CheckField, 19, 1, 0, 1, 40, 0, // Skip to: 17098 +/* 6857 */ MCD_OPC_Decode, 187, 20, 131, 2, // Opcode: SAT_U_B +/* 6862 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 6877 +/* 6867 */ MCD_OPC_CheckPredicate, 30, 242, 39, 0, // Skip to: 17098 +/* 6872 */ MCD_OPC_Decode, 144, 22, 129, 2, // Opcode: SRARI_D +/* 6877 */ MCD_OPC_FilterValue, 5, 63, 0, 0, // Skip to: 6945 +/* 6882 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6885 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6900 +/* 6890 */ MCD_OPC_CheckPredicate, 30, 219, 39, 0, // Skip to: 17098 +/* 6895 */ MCD_OPC_Decode, 146, 22, 251, 1, // Opcode: SRARI_W +/* 6900 */ MCD_OPC_FilterValue, 1, 209, 39, 0, // Skip to: 17098 +/* 6905 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6908 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6923 +/* 6913 */ MCD_OPC_CheckPredicate, 30, 196, 39, 0, // Skip to: 17098 +/* 6918 */ MCD_OPC_Decode, 145, 22, 130, 2, // Opcode: SRARI_H +/* 6923 */ MCD_OPC_FilterValue, 1, 186, 39, 0, // Skip to: 17098 +/* 6928 */ MCD_OPC_CheckPredicate, 30, 181, 39, 0, // Skip to: 17098 +/* 6933 */ MCD_OPC_CheckField, 19, 1, 0, 174, 39, 0, // Skip to: 17098 +/* 6940 */ MCD_OPC_Decode, 143, 22, 131, 2, // Opcode: SRARI_B +/* 6945 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 6960 +/* 6950 */ MCD_OPC_CheckPredicate, 30, 159, 39, 0, // Skip to: 17098 +/* 6955 */ MCD_OPC_Decode, 169, 22, 129, 2, // Opcode: SRLRI_D +/* 6960 */ MCD_OPC_FilterValue, 7, 149, 39, 0, // Skip to: 17098 +/* 6965 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6968 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6983 +/* 6973 */ MCD_OPC_CheckPredicate, 30, 136, 39, 0, // Skip to: 17098 +/* 6978 */ MCD_OPC_Decode, 171, 22, 251, 1, // Opcode: SRLRI_W +/* 6983 */ MCD_OPC_FilterValue, 1, 126, 39, 0, // Skip to: 17098 +/* 6988 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6991 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7006 +/* 6996 */ MCD_OPC_CheckPredicate, 30, 113, 39, 0, // Skip to: 17098 +/* 7001 */ MCD_OPC_Decode, 170, 22, 130, 2, // Opcode: SRLRI_H +/* 7006 */ MCD_OPC_FilterValue, 1, 103, 39, 0, // Skip to: 17098 +/* 7011 */ MCD_OPC_CheckPredicate, 30, 98, 39, 0, // Skip to: 17098 +/* 7016 */ MCD_OPC_CheckField, 19, 1, 0, 91, 39, 0, // Skip to: 17098 +/* 7023 */ MCD_OPC_Decode, 168, 22, 131, 2, // Opcode: SRLRI_B +/* 7028 */ MCD_OPC_FilterValue, 13, 227, 1, 0, // Skip to: 7516 +/* 7033 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 7036 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7051 +/* 7041 */ MCD_OPC_CheckPredicate, 30, 68, 39, 0, // Skip to: 17098 +/* 7046 */ MCD_OPC_Decode, 232, 21, 136, 2, // Opcode: SLL_B +/* 7051 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7066 +/* 7056 */ MCD_OPC_CheckPredicate, 30, 53, 39, 0, // Skip to: 17098 +/* 7061 */ MCD_OPC_Decode, 234, 21, 137, 2, // Opcode: SLL_H +/* 7066 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7081 +/* 7071 */ MCD_OPC_CheckPredicate, 30, 38, 39, 0, // Skip to: 17098 +/* 7076 */ MCD_OPC_Decode, 238, 21, 138, 2, // Opcode: SLL_W +/* 7081 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 7096 +/* 7086 */ MCD_OPC_CheckPredicate, 30, 23, 39, 0, // Skip to: 17098 +/* 7091 */ MCD_OPC_Decode, 233, 21, 139, 2, // Opcode: SLL_D +/* 7096 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 7111 +/* 7101 */ MCD_OPC_CheckPredicate, 30, 8, 39, 0, // Skip to: 17098 +/* 7106 */ MCD_OPC_Decode, 154, 22, 136, 2, // Opcode: SRA_B +/* 7111 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 7126 +/* 7116 */ MCD_OPC_CheckPredicate, 30, 249, 38, 0, // Skip to: 17098 +/* 7121 */ MCD_OPC_Decode, 156, 22, 137, 2, // Opcode: SRA_H +/* 7126 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 7141 +/* 7131 */ MCD_OPC_CheckPredicate, 30, 234, 38, 0, // Skip to: 17098 +/* 7136 */ MCD_OPC_Decode, 159, 22, 138, 2, // Opcode: SRA_W +/* 7141 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 7156 +/* 7146 */ MCD_OPC_CheckPredicate, 30, 219, 38, 0, // Skip to: 17098 +/* 7151 */ MCD_OPC_Decode, 155, 22, 139, 2, // Opcode: SRA_D +/* 7156 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 7171 +/* 7161 */ MCD_OPC_CheckPredicate, 30, 204, 38, 0, // Skip to: 17098 +/* 7166 */ MCD_OPC_Decode, 179, 22, 136, 2, // Opcode: SRL_B +/* 7171 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 7186 +/* 7176 */ MCD_OPC_CheckPredicate, 30, 189, 38, 0, // Skip to: 17098 +/* 7181 */ MCD_OPC_Decode, 181, 22, 137, 2, // Opcode: SRL_H +/* 7186 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 7201 +/* 7191 */ MCD_OPC_CheckPredicate, 30, 174, 38, 0, // Skip to: 17098 +/* 7196 */ MCD_OPC_Decode, 184, 22, 138, 2, // Opcode: SRL_W +/* 7201 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 7216 +/* 7206 */ MCD_OPC_CheckPredicate, 30, 159, 38, 0, // Skip to: 17098 +/* 7211 */ MCD_OPC_Decode, 180, 22, 139, 2, // Opcode: SRL_D +/* 7216 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 7231 +/* 7221 */ MCD_OPC_CheckPredicate, 30, 144, 38, 0, // Skip to: 17098 +/* 7226 */ MCD_OPC_Decode, 182, 7, 136, 2, // Opcode: BCLR_B +/* 7231 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 7246 +/* 7236 */ MCD_OPC_CheckPredicate, 30, 129, 38, 0, // Skip to: 17098 +/* 7241 */ MCD_OPC_Decode, 184, 7, 137, 2, // Opcode: BCLR_H +/* 7246 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 7261 +/* 7251 */ MCD_OPC_CheckPredicate, 30, 114, 38, 0, // Skip to: 17098 +/* 7256 */ MCD_OPC_Decode, 185, 7, 138, 2, // Opcode: BCLR_W +/* 7261 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 7276 +/* 7266 */ MCD_OPC_CheckPredicate, 30, 99, 38, 0, // Skip to: 17098 +/* 7271 */ MCD_OPC_Decode, 183, 7, 139, 2, // Opcode: BCLR_D +/* 7276 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 7291 +/* 7281 */ MCD_OPC_CheckPredicate, 30, 84, 38, 0, // Skip to: 17098 +/* 7286 */ MCD_OPC_Decode, 225, 8, 136, 2, // Opcode: BSET_B +/* 7291 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 7306 +/* 7296 */ MCD_OPC_CheckPredicate, 30, 69, 38, 0, // Skip to: 17098 +/* 7301 */ MCD_OPC_Decode, 227, 8, 137, 2, // Opcode: BSET_H +/* 7306 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 7321 +/* 7311 */ MCD_OPC_CheckPredicate, 30, 54, 38, 0, // Skip to: 17098 +/* 7316 */ MCD_OPC_Decode, 228, 8, 138, 2, // Opcode: BSET_W +/* 7321 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 7336 +/* 7326 */ MCD_OPC_CheckPredicate, 30, 39, 38, 0, // Skip to: 17098 +/* 7331 */ MCD_OPC_Decode, 226, 8, 139, 2, // Opcode: BSET_D +/* 7336 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 7351 +/* 7341 */ MCD_OPC_CheckPredicate, 30, 24, 38, 0, // Skip to: 17098 +/* 7346 */ MCD_OPC_Decode, 182, 8, 136, 2, // Opcode: BNEG_B +/* 7351 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 7366 +/* 7356 */ MCD_OPC_CheckPredicate, 30, 9, 38, 0, // Skip to: 17098 +/* 7361 */ MCD_OPC_Decode, 184, 8, 137, 2, // Opcode: BNEG_H +/* 7366 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 7381 +/* 7371 */ MCD_OPC_CheckPredicate, 30, 250, 37, 0, // Skip to: 17098 +/* 7376 */ MCD_OPC_Decode, 185, 8, 138, 2, // Opcode: BNEG_W +/* 7381 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 7396 +/* 7386 */ MCD_OPC_CheckPredicate, 30, 235, 37, 0, // Skip to: 17098 +/* 7391 */ MCD_OPC_Decode, 183, 8, 139, 2, // Opcode: BNEG_D +/* 7396 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 7411 +/* 7401 */ MCD_OPC_CheckPredicate, 30, 220, 37, 0, // Skip to: 17098 +/* 7406 */ MCD_OPC_Decode, 245, 7, 140, 2, // Opcode: BINSL_B +/* 7411 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 7426 +/* 7416 */ MCD_OPC_CheckPredicate, 30, 205, 37, 0, // Skip to: 17098 +/* 7421 */ MCD_OPC_Decode, 247, 7, 141, 2, // Opcode: BINSL_H +/* 7426 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 7441 +/* 7431 */ MCD_OPC_CheckPredicate, 30, 190, 37, 0, // Skip to: 17098 +/* 7436 */ MCD_OPC_Decode, 248, 7, 142, 2, // Opcode: BINSL_W +/* 7441 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 7456 +/* 7446 */ MCD_OPC_CheckPredicate, 30, 175, 37, 0, // Skip to: 17098 +/* 7451 */ MCD_OPC_Decode, 246, 7, 143, 2, // Opcode: BINSL_D +/* 7456 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 7471 +/* 7461 */ MCD_OPC_CheckPredicate, 30, 160, 37, 0, // Skip to: 17098 +/* 7466 */ MCD_OPC_Decode, 253, 7, 140, 2, // Opcode: BINSR_B +/* 7471 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 7486 +/* 7476 */ MCD_OPC_CheckPredicate, 30, 145, 37, 0, // Skip to: 17098 +/* 7481 */ MCD_OPC_Decode, 255, 7, 141, 2, // Opcode: BINSR_H +/* 7486 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 7501 +/* 7491 */ MCD_OPC_CheckPredicate, 30, 130, 37, 0, // Skip to: 17098 +/* 7496 */ MCD_OPC_Decode, 128, 8, 142, 2, // Opcode: BINSR_W +/* 7501 */ MCD_OPC_FilterValue, 31, 120, 37, 0, // Skip to: 17098 +/* 7506 */ MCD_OPC_CheckPredicate, 30, 115, 37, 0, // Skip to: 17098 +/* 7511 */ MCD_OPC_Decode, 254, 7, 143, 2, // Opcode: BINSR_D +/* 7516 */ MCD_OPC_FilterValue, 14, 227, 1, 0, // Skip to: 8004 +/* 7521 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 7524 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7539 +/* 7529 */ MCD_OPC_CheckPredicate, 30, 92, 37, 0, // Skip to: 17098 +/* 7534 */ MCD_OPC_Decode, 189, 6, 136, 2, // Opcode: ADDV_B +/* 7539 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7554 +/* 7544 */ MCD_OPC_CheckPredicate, 30, 77, 37, 0, // Skip to: 17098 +/* 7549 */ MCD_OPC_Decode, 191, 6, 137, 2, // Opcode: ADDV_H +/* 7554 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7569 +/* 7559 */ MCD_OPC_CheckPredicate, 30, 62, 37, 0, // Skip to: 17098 +/* 7564 */ MCD_OPC_Decode, 192, 6, 138, 2, // Opcode: ADDV_W +/* 7569 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 7584 +/* 7574 */ MCD_OPC_CheckPredicate, 30, 47, 37, 0, // Skip to: 17098 +/* 7579 */ MCD_OPC_Decode, 190, 6, 139, 2, // Opcode: ADDV_D +/* 7584 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 7599 +/* 7589 */ MCD_OPC_CheckPredicate, 30, 32, 37, 0, // Skip to: 17098 +/* 7594 */ MCD_OPC_Decode, 242, 22, 136, 2, // Opcode: SUBV_B +/* 7599 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 7614 +/* 7604 */ MCD_OPC_CheckPredicate, 30, 17, 37, 0, // Skip to: 17098 +/* 7609 */ MCD_OPC_Decode, 244, 22, 137, 2, // Opcode: SUBV_H +/* 7614 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 7629 +/* 7619 */ MCD_OPC_CheckPredicate, 30, 2, 37, 0, // Skip to: 17098 +/* 7624 */ MCD_OPC_Decode, 245, 22, 138, 2, // Opcode: SUBV_W +/* 7629 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 7644 +/* 7634 */ MCD_OPC_CheckPredicate, 30, 243, 36, 0, // Skip to: 17098 +/* 7639 */ MCD_OPC_Decode, 243, 22, 139, 2, // Opcode: SUBV_D +/* 7644 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 7659 +/* 7649 */ MCD_OPC_CheckPredicate, 30, 228, 36, 0, // Skip to: 17098 +/* 7654 */ MCD_OPC_Decode, 247, 16, 136, 2, // Opcode: MAX_S_B +/* 7659 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 7674 +/* 7664 */ MCD_OPC_CheckPredicate, 30, 213, 36, 0, // Skip to: 17098 +/* 7669 */ MCD_OPC_Decode, 249, 16, 137, 2, // Opcode: MAX_S_H +/* 7674 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 7689 +/* 7679 */ MCD_OPC_CheckPredicate, 30, 198, 36, 0, // Skip to: 17098 +/* 7684 */ MCD_OPC_Decode, 251, 16, 138, 2, // Opcode: MAX_S_W +/* 7689 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 7704 +/* 7694 */ MCD_OPC_CheckPredicate, 30, 183, 36, 0, // Skip to: 17098 +/* 7699 */ MCD_OPC_Decode, 248, 16, 139, 2, // Opcode: MAX_S_D +/* 7704 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 7719 +/* 7709 */ MCD_OPC_CheckPredicate, 30, 168, 36, 0, // Skip to: 17098 +/* 7714 */ MCD_OPC_Decode, 252, 16, 136, 2, // Opcode: MAX_U_B +/* 7719 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 7734 +/* 7724 */ MCD_OPC_CheckPredicate, 30, 153, 36, 0, // Skip to: 17098 +/* 7729 */ MCD_OPC_Decode, 254, 16, 137, 2, // Opcode: MAX_U_H +/* 7734 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 7749 +/* 7739 */ MCD_OPC_CheckPredicate, 30, 138, 36, 0, // Skip to: 17098 +/* 7744 */ MCD_OPC_Decode, 255, 16, 138, 2, // Opcode: MAX_U_W +/* 7749 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 7764 +/* 7754 */ MCD_OPC_CheckPredicate, 30, 123, 36, 0, // Skip to: 17098 +/* 7759 */ MCD_OPC_Decode, 253, 16, 139, 2, // Opcode: MAX_U_D +/* 7764 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 7779 +/* 7769 */ MCD_OPC_CheckPredicate, 30, 108, 36, 0, // Skip to: 17098 +/* 7774 */ MCD_OPC_Decode, 183, 17, 136, 2, // Opcode: MIN_S_B +/* 7779 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 7794 +/* 7784 */ MCD_OPC_CheckPredicate, 30, 93, 36, 0, // Skip to: 17098 +/* 7789 */ MCD_OPC_Decode, 185, 17, 137, 2, // Opcode: MIN_S_H +/* 7794 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 7809 +/* 7799 */ MCD_OPC_CheckPredicate, 30, 78, 36, 0, // Skip to: 17098 +/* 7804 */ MCD_OPC_Decode, 187, 17, 138, 2, // Opcode: MIN_S_W +/* 7809 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 7824 +/* 7814 */ MCD_OPC_CheckPredicate, 30, 63, 36, 0, // Skip to: 17098 +/* 7819 */ MCD_OPC_Decode, 184, 17, 139, 2, // Opcode: MIN_S_D +/* 7824 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 7839 +/* 7829 */ MCD_OPC_CheckPredicate, 30, 48, 36, 0, // Skip to: 17098 +/* 7834 */ MCD_OPC_Decode, 188, 17, 136, 2, // Opcode: MIN_U_B +/* 7839 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 7854 +/* 7844 */ MCD_OPC_CheckPredicate, 30, 33, 36, 0, // Skip to: 17098 +/* 7849 */ MCD_OPC_Decode, 190, 17, 137, 2, // Opcode: MIN_U_H +/* 7854 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 7869 +/* 7859 */ MCD_OPC_CheckPredicate, 30, 18, 36, 0, // Skip to: 17098 +/* 7864 */ MCD_OPC_Decode, 191, 17, 138, 2, // Opcode: MIN_U_W +/* 7869 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 7884 +/* 7874 */ MCD_OPC_CheckPredicate, 30, 3, 36, 0, // Skip to: 17098 +/* 7879 */ MCD_OPC_Decode, 189, 17, 139, 2, // Opcode: MIN_U_D +/* 7884 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 7899 +/* 7889 */ MCD_OPC_CheckPredicate, 30, 244, 35, 0, // Skip to: 17098 +/* 7894 */ MCD_OPC_Decode, 240, 16, 136, 2, // Opcode: MAX_A_B +/* 7899 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 7914 +/* 7904 */ MCD_OPC_CheckPredicate, 30, 229, 35, 0, // Skip to: 17098 +/* 7909 */ MCD_OPC_Decode, 242, 16, 137, 2, // Opcode: MAX_A_H +/* 7914 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 7929 +/* 7919 */ MCD_OPC_CheckPredicate, 30, 214, 35, 0, // Skip to: 17098 +/* 7924 */ MCD_OPC_Decode, 243, 16, 138, 2, // Opcode: MAX_A_W +/* 7929 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 7944 +/* 7934 */ MCD_OPC_CheckPredicate, 30, 199, 35, 0, // Skip to: 17098 +/* 7939 */ MCD_OPC_Decode, 241, 16, 139, 2, // Opcode: MAX_A_D +/* 7944 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 7959 +/* 7949 */ MCD_OPC_CheckPredicate, 30, 184, 35, 0, // Skip to: 17098 +/* 7954 */ MCD_OPC_Decode, 176, 17, 136, 2, // Opcode: MIN_A_B +/* 7959 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 7974 +/* 7964 */ MCD_OPC_CheckPredicate, 30, 169, 35, 0, // Skip to: 17098 +/* 7969 */ MCD_OPC_Decode, 178, 17, 137, 2, // Opcode: MIN_A_H +/* 7974 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 7989 +/* 7979 */ MCD_OPC_CheckPredicate, 30, 154, 35, 0, // Skip to: 17098 +/* 7984 */ MCD_OPC_Decode, 179, 17, 138, 2, // Opcode: MIN_A_W +/* 7989 */ MCD_OPC_FilterValue, 31, 144, 35, 0, // Skip to: 17098 +/* 7994 */ MCD_OPC_CheckPredicate, 30, 139, 35, 0, // Skip to: 17098 +/* 7999 */ MCD_OPC_Decode, 177, 17, 139, 2, // Opcode: MIN_A_D +/* 8004 */ MCD_OPC_FilterValue, 15, 47, 1, 0, // Skip to: 8312 +/* 8009 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 8012 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8027 +/* 8017 */ MCD_OPC_CheckPredicate, 30, 116, 35, 0, // Skip to: 17098 +/* 8022 */ MCD_OPC_Decode, 140, 9, 136, 2, // Opcode: CEQ_B +/* 8027 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8042 +/* 8032 */ MCD_OPC_CheckPredicate, 30, 101, 35, 0, // Skip to: 17098 +/* 8037 */ MCD_OPC_Decode, 142, 9, 137, 2, // Opcode: CEQ_H +/* 8042 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8057 +/* 8047 */ MCD_OPC_CheckPredicate, 30, 86, 35, 0, // Skip to: 17098 +/* 8052 */ MCD_OPC_Decode, 143, 9, 138, 2, // Opcode: CEQ_W +/* 8057 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 8072 +/* 8062 */ MCD_OPC_CheckPredicate, 30, 71, 35, 0, // Skip to: 17098 +/* 8067 */ MCD_OPC_Decode, 141, 9, 139, 2, // Opcode: CEQ_D +/* 8072 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 8087 +/* 8077 */ MCD_OPC_CheckPredicate, 30, 56, 35, 0, // Skip to: 17098 +/* 8082 */ MCD_OPC_Decode, 185, 9, 136, 2, // Opcode: CLT_S_B +/* 8087 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 8102 +/* 8092 */ MCD_OPC_CheckPredicate, 30, 41, 35, 0, // Skip to: 17098 +/* 8097 */ MCD_OPC_Decode, 187, 9, 137, 2, // Opcode: CLT_S_H +/* 8102 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 8117 +/* 8107 */ MCD_OPC_CheckPredicate, 30, 26, 35, 0, // Skip to: 17098 +/* 8112 */ MCD_OPC_Decode, 188, 9, 138, 2, // Opcode: CLT_S_W +/* 8117 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 8132 +/* 8122 */ MCD_OPC_CheckPredicate, 30, 11, 35, 0, // Skip to: 17098 +/* 8127 */ MCD_OPC_Decode, 186, 9, 139, 2, // Opcode: CLT_S_D +/* 8132 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 8147 +/* 8137 */ MCD_OPC_CheckPredicate, 30, 252, 34, 0, // Skip to: 17098 +/* 8142 */ MCD_OPC_Decode, 189, 9, 136, 2, // Opcode: CLT_U_B +/* 8147 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 8162 +/* 8152 */ MCD_OPC_CheckPredicate, 30, 237, 34, 0, // Skip to: 17098 +/* 8157 */ MCD_OPC_Decode, 191, 9, 137, 2, // Opcode: CLT_U_H +/* 8162 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 8177 +/* 8167 */ MCD_OPC_CheckPredicate, 30, 222, 34, 0, // Skip to: 17098 +/* 8172 */ MCD_OPC_Decode, 192, 9, 138, 2, // Opcode: CLT_U_W +/* 8177 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 8192 +/* 8182 */ MCD_OPC_CheckPredicate, 30, 207, 34, 0, // Skip to: 17098 +/* 8187 */ MCD_OPC_Decode, 190, 9, 139, 2, // Opcode: CLT_U_D +/* 8192 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 8207 +/* 8197 */ MCD_OPC_CheckPredicate, 30, 192, 34, 0, // Skip to: 17098 +/* 8202 */ MCD_OPC_Decode, 164, 9, 136, 2, // Opcode: CLE_S_B +/* 8207 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 8222 +/* 8212 */ MCD_OPC_CheckPredicate, 30, 177, 34, 0, // Skip to: 17098 +/* 8217 */ MCD_OPC_Decode, 166, 9, 137, 2, // Opcode: CLE_S_H +/* 8222 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 8237 +/* 8227 */ MCD_OPC_CheckPredicate, 30, 162, 34, 0, // Skip to: 17098 +/* 8232 */ MCD_OPC_Decode, 167, 9, 138, 2, // Opcode: CLE_S_W +/* 8237 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 8252 +/* 8242 */ MCD_OPC_CheckPredicate, 30, 147, 34, 0, // Skip to: 17098 +/* 8247 */ MCD_OPC_Decode, 165, 9, 139, 2, // Opcode: CLE_S_D +/* 8252 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 8267 +/* 8257 */ MCD_OPC_CheckPredicate, 30, 132, 34, 0, // Skip to: 17098 +/* 8262 */ MCD_OPC_Decode, 168, 9, 136, 2, // Opcode: CLE_U_B +/* 8267 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 8282 +/* 8272 */ MCD_OPC_CheckPredicate, 30, 117, 34, 0, // Skip to: 17098 +/* 8277 */ MCD_OPC_Decode, 170, 9, 137, 2, // Opcode: CLE_U_H +/* 8282 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 8297 +/* 8287 */ MCD_OPC_CheckPredicate, 30, 102, 34, 0, // Skip to: 17098 +/* 8292 */ MCD_OPC_Decode, 171, 9, 138, 2, // Opcode: CLE_U_W +/* 8297 */ MCD_OPC_FilterValue, 23, 92, 34, 0, // Skip to: 17098 +/* 8302 */ MCD_OPC_CheckPredicate, 30, 87, 34, 0, // Skip to: 17098 +/* 8307 */ MCD_OPC_Decode, 169, 9, 139, 2, // Opcode: CLE_U_D +/* 8312 */ MCD_OPC_FilterValue, 16, 227, 1, 0, // Skip to: 8800 +/* 8317 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 8320 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8335 +/* 8325 */ MCD_OPC_CheckPredicate, 30, 64, 34, 0, // Skip to: 17098 +/* 8330 */ MCD_OPC_Decode, 195, 6, 136, 2, // Opcode: ADD_A_B +/* 8335 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8350 +/* 8340 */ MCD_OPC_CheckPredicate, 30, 49, 34, 0, // Skip to: 17098 +/* 8345 */ MCD_OPC_Decode, 197, 6, 137, 2, // Opcode: ADD_A_H +/* 8350 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8365 +/* 8355 */ MCD_OPC_CheckPredicate, 30, 34, 34, 0, // Skip to: 17098 +/* 8360 */ MCD_OPC_Decode, 198, 6, 138, 2, // Opcode: ADD_A_W +/* 8365 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 8380 +/* 8370 */ MCD_OPC_CheckPredicate, 30, 19, 34, 0, // Skip to: 17098 +/* 8375 */ MCD_OPC_Decode, 196, 6, 139, 2, // Opcode: ADD_A_D +/* 8380 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 8395 +/* 8385 */ MCD_OPC_CheckPredicate, 30, 4, 34, 0, // Skip to: 17098 +/* 8390 */ MCD_OPC_Decode, 158, 6, 136, 2, // Opcode: ADDS_A_B +/* 8395 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 8410 +/* 8400 */ MCD_OPC_CheckPredicate, 30, 245, 33, 0, // Skip to: 17098 +/* 8405 */ MCD_OPC_Decode, 160, 6, 137, 2, // Opcode: ADDS_A_H +/* 8410 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 8425 +/* 8415 */ MCD_OPC_CheckPredicate, 30, 230, 33, 0, // Skip to: 17098 +/* 8420 */ MCD_OPC_Decode, 161, 6, 138, 2, // Opcode: ADDS_A_W +/* 8425 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 8440 +/* 8430 */ MCD_OPC_CheckPredicate, 30, 215, 33, 0, // Skip to: 17098 +/* 8435 */ MCD_OPC_Decode, 159, 6, 139, 2, // Opcode: ADDS_A_D +/* 8440 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 8455 +/* 8445 */ MCD_OPC_CheckPredicate, 30, 200, 33, 0, // Skip to: 17098 +/* 8450 */ MCD_OPC_Decode, 162, 6, 136, 2, // Opcode: ADDS_S_B +/* 8455 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 8470 +/* 8460 */ MCD_OPC_CheckPredicate, 30, 185, 33, 0, // Skip to: 17098 +/* 8465 */ MCD_OPC_Decode, 164, 6, 137, 2, // Opcode: ADDS_S_H +/* 8470 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 8485 +/* 8475 */ MCD_OPC_CheckPredicate, 30, 170, 33, 0, // Skip to: 17098 +/* 8480 */ MCD_OPC_Decode, 165, 6, 138, 2, // Opcode: ADDS_S_W +/* 8485 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 8500 +/* 8490 */ MCD_OPC_CheckPredicate, 30, 155, 33, 0, // Skip to: 17098 +/* 8495 */ MCD_OPC_Decode, 163, 6, 139, 2, // Opcode: ADDS_S_D +/* 8500 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 8515 +/* 8505 */ MCD_OPC_CheckPredicate, 30, 140, 33, 0, // Skip to: 17098 +/* 8510 */ MCD_OPC_Decode, 166, 6, 136, 2, // Opcode: ADDS_U_B +/* 8515 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 8530 +/* 8520 */ MCD_OPC_CheckPredicate, 30, 125, 33, 0, // Skip to: 17098 +/* 8525 */ MCD_OPC_Decode, 168, 6, 137, 2, // Opcode: ADDS_U_H +/* 8530 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 8545 +/* 8535 */ MCD_OPC_CheckPredicate, 30, 110, 33, 0, // Skip to: 17098 +/* 8540 */ MCD_OPC_Decode, 169, 6, 138, 2, // Opcode: ADDS_U_W +/* 8545 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 8560 +/* 8550 */ MCD_OPC_CheckPredicate, 30, 95, 33, 0, // Skip to: 17098 +/* 8555 */ MCD_OPC_Decode, 167, 6, 139, 2, // Opcode: ADDS_U_D +/* 8560 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 8575 +/* 8565 */ MCD_OPC_CheckPredicate, 30, 80, 33, 0, // Skip to: 17098 +/* 8570 */ MCD_OPC_Decode, 128, 7, 136, 2, // Opcode: AVE_S_B +/* 8575 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 8590 +/* 8580 */ MCD_OPC_CheckPredicate, 30, 65, 33, 0, // Skip to: 17098 +/* 8585 */ MCD_OPC_Decode, 130, 7, 137, 2, // Opcode: AVE_S_H +/* 8590 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 8605 +/* 8595 */ MCD_OPC_CheckPredicate, 30, 50, 33, 0, // Skip to: 17098 +/* 8600 */ MCD_OPC_Decode, 131, 7, 138, 2, // Opcode: AVE_S_W +/* 8605 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 8620 +/* 8610 */ MCD_OPC_CheckPredicate, 30, 35, 33, 0, // Skip to: 17098 +/* 8615 */ MCD_OPC_Decode, 129, 7, 139, 2, // Opcode: AVE_S_D +/* 8620 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 8635 +/* 8625 */ MCD_OPC_CheckPredicate, 30, 20, 33, 0, // Skip to: 17098 +/* 8630 */ MCD_OPC_Decode, 132, 7, 136, 2, // Opcode: AVE_U_B +/* 8635 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 8650 +/* 8640 */ MCD_OPC_CheckPredicate, 30, 5, 33, 0, // Skip to: 17098 +/* 8645 */ MCD_OPC_Decode, 134, 7, 137, 2, // Opcode: AVE_U_H +/* 8650 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 8665 +/* 8655 */ MCD_OPC_CheckPredicate, 30, 246, 32, 0, // Skip to: 17098 +/* 8660 */ MCD_OPC_Decode, 135, 7, 138, 2, // Opcode: AVE_U_W +/* 8665 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 8680 +/* 8670 */ MCD_OPC_CheckPredicate, 30, 231, 32, 0, // Skip to: 17098 +/* 8675 */ MCD_OPC_Decode, 133, 7, 139, 2, // Opcode: AVE_U_D +/* 8680 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 8695 +/* 8685 */ MCD_OPC_CheckPredicate, 30, 216, 32, 0, // Skip to: 17098 +/* 8690 */ MCD_OPC_Decode, 248, 6, 136, 2, // Opcode: AVER_S_B +/* 8695 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 8710 +/* 8700 */ MCD_OPC_CheckPredicate, 30, 201, 32, 0, // Skip to: 17098 +/* 8705 */ MCD_OPC_Decode, 250, 6, 137, 2, // Opcode: AVER_S_H +/* 8710 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 8725 +/* 8715 */ MCD_OPC_CheckPredicate, 30, 186, 32, 0, // Skip to: 17098 +/* 8720 */ MCD_OPC_Decode, 251, 6, 138, 2, // Opcode: AVER_S_W +/* 8725 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 8740 +/* 8730 */ MCD_OPC_CheckPredicate, 30, 171, 32, 0, // Skip to: 17098 +/* 8735 */ MCD_OPC_Decode, 249, 6, 139, 2, // Opcode: AVER_S_D +/* 8740 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 8755 +/* 8745 */ MCD_OPC_CheckPredicate, 30, 156, 32, 0, // Skip to: 17098 +/* 8750 */ MCD_OPC_Decode, 252, 6, 136, 2, // Opcode: AVER_U_B +/* 8755 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 8770 +/* 8760 */ MCD_OPC_CheckPredicate, 30, 141, 32, 0, // Skip to: 17098 +/* 8765 */ MCD_OPC_Decode, 254, 6, 137, 2, // Opcode: AVER_U_H +/* 8770 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 8785 +/* 8775 */ MCD_OPC_CheckPredicate, 30, 126, 32, 0, // Skip to: 17098 +/* 8780 */ MCD_OPC_Decode, 255, 6, 138, 2, // Opcode: AVER_U_W +/* 8785 */ MCD_OPC_FilterValue, 31, 116, 32, 0, // Skip to: 17098 +/* 8790 */ MCD_OPC_CheckPredicate, 30, 111, 32, 0, // Skip to: 17098 +/* 8795 */ MCD_OPC_Decode, 253, 6, 139, 2, // Opcode: AVER_U_D +/* 8800 */ MCD_OPC_FilterValue, 17, 107, 1, 0, // Skip to: 9168 +/* 8805 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 8808 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8823 +/* 8813 */ MCD_OPC_CheckPredicate, 30, 88, 32, 0, // Skip to: 17098 +/* 8818 */ MCD_OPC_Decode, 215, 22, 136, 2, // Opcode: SUBS_S_B +/* 8823 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8838 +/* 8828 */ MCD_OPC_CheckPredicate, 30, 73, 32, 0, // Skip to: 17098 +/* 8833 */ MCD_OPC_Decode, 217, 22, 137, 2, // Opcode: SUBS_S_H +/* 8838 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8853 +/* 8843 */ MCD_OPC_CheckPredicate, 30, 58, 32, 0, // Skip to: 17098 +/* 8848 */ MCD_OPC_Decode, 218, 22, 138, 2, // Opcode: SUBS_S_W +/* 8853 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 8868 +/* 8858 */ MCD_OPC_CheckPredicate, 30, 43, 32, 0, // Skip to: 17098 +/* 8863 */ MCD_OPC_Decode, 216, 22, 139, 2, // Opcode: SUBS_S_D +/* 8868 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 8883 +/* 8873 */ MCD_OPC_CheckPredicate, 30, 28, 32, 0, // Skip to: 17098 +/* 8878 */ MCD_OPC_Decode, 219, 22, 136, 2, // Opcode: SUBS_U_B +/* 8883 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 8898 +/* 8888 */ MCD_OPC_CheckPredicate, 30, 13, 32, 0, // Skip to: 17098 +/* 8893 */ MCD_OPC_Decode, 221, 22, 137, 2, // Opcode: SUBS_U_H +/* 8898 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 8913 +/* 8903 */ MCD_OPC_CheckPredicate, 30, 254, 31, 0, // Skip to: 17098 +/* 8908 */ MCD_OPC_Decode, 222, 22, 138, 2, // Opcode: SUBS_U_W +/* 8913 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 8928 +/* 8918 */ MCD_OPC_CheckPredicate, 30, 239, 31, 0, // Skip to: 17098 +/* 8923 */ MCD_OPC_Decode, 220, 22, 139, 2, // Opcode: SUBS_U_D +/* 8928 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 8943 +/* 8933 */ MCD_OPC_CheckPredicate, 30, 224, 31, 0, // Skip to: 17098 +/* 8938 */ MCD_OPC_Decode, 207, 22, 136, 2, // Opcode: SUBSUS_U_B +/* 8943 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 8958 +/* 8948 */ MCD_OPC_CheckPredicate, 30, 209, 31, 0, // Skip to: 17098 +/* 8953 */ MCD_OPC_Decode, 209, 22, 137, 2, // Opcode: SUBSUS_U_H +/* 8958 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 8973 +/* 8963 */ MCD_OPC_CheckPredicate, 30, 194, 31, 0, // Skip to: 17098 +/* 8968 */ MCD_OPC_Decode, 210, 22, 138, 2, // Opcode: SUBSUS_U_W +/* 8973 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 8988 +/* 8978 */ MCD_OPC_CheckPredicate, 30, 179, 31, 0, // Skip to: 17098 +/* 8983 */ MCD_OPC_Decode, 208, 22, 139, 2, // Opcode: SUBSUS_U_D +/* 8988 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 9003 +/* 8993 */ MCD_OPC_CheckPredicate, 30, 164, 31, 0, // Skip to: 17098 +/* 8998 */ MCD_OPC_Decode, 211, 22, 136, 2, // Opcode: SUBSUU_S_B +/* 9003 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 9018 +/* 9008 */ MCD_OPC_CheckPredicate, 30, 149, 31, 0, // Skip to: 17098 +/* 9013 */ MCD_OPC_Decode, 213, 22, 137, 2, // Opcode: SUBSUU_S_H +/* 9018 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9033 +/* 9023 */ MCD_OPC_CheckPredicate, 30, 134, 31, 0, // Skip to: 17098 +/* 9028 */ MCD_OPC_Decode, 214, 22, 138, 2, // Opcode: SUBSUU_S_W +/* 9033 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 9048 +/* 9038 */ MCD_OPC_CheckPredicate, 30, 119, 31, 0, // Skip to: 17098 +/* 9043 */ MCD_OPC_Decode, 212, 22, 139, 2, // Opcode: SUBSUU_S_D +/* 9048 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 9063 +/* 9053 */ MCD_OPC_CheckPredicate, 30, 104, 31, 0, // Skip to: 17098 +/* 9058 */ MCD_OPC_Decode, 236, 6, 136, 2, // Opcode: ASUB_S_B +/* 9063 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 9078 +/* 9068 */ MCD_OPC_CheckPredicate, 30, 89, 31, 0, // Skip to: 17098 +/* 9073 */ MCD_OPC_Decode, 238, 6, 137, 2, // Opcode: ASUB_S_H +/* 9078 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 9093 +/* 9083 */ MCD_OPC_CheckPredicate, 30, 74, 31, 0, // Skip to: 17098 +/* 9088 */ MCD_OPC_Decode, 239, 6, 138, 2, // Opcode: ASUB_S_W +/* 9093 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 9108 +/* 9098 */ MCD_OPC_CheckPredicate, 30, 59, 31, 0, // Skip to: 17098 +/* 9103 */ MCD_OPC_Decode, 237, 6, 139, 2, // Opcode: ASUB_S_D +/* 9108 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 9123 +/* 9113 */ MCD_OPC_CheckPredicate, 30, 44, 31, 0, // Skip to: 17098 +/* 9118 */ MCD_OPC_Decode, 240, 6, 136, 2, // Opcode: ASUB_U_B +/* 9123 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 9138 +/* 9128 */ MCD_OPC_CheckPredicate, 30, 29, 31, 0, // Skip to: 17098 +/* 9133 */ MCD_OPC_Decode, 242, 6, 137, 2, // Opcode: ASUB_U_H +/* 9138 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 9153 +/* 9143 */ MCD_OPC_CheckPredicate, 30, 14, 31, 0, // Skip to: 17098 +/* 9148 */ MCD_OPC_Decode, 243, 6, 138, 2, // Opcode: ASUB_U_W +/* 9153 */ MCD_OPC_FilterValue, 23, 4, 31, 0, // Skip to: 17098 +/* 9158 */ MCD_OPC_CheckPredicate, 30, 255, 30, 0, // Skip to: 17098 +/* 9163 */ MCD_OPC_Decode, 241, 6, 139, 2, // Opcode: ASUB_U_D +/* 9168 */ MCD_OPC_FilterValue, 18, 167, 1, 0, // Skip to: 9596 +/* 9173 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 9176 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9191 +/* 9181 */ MCD_OPC_CheckPredicate, 30, 232, 30, 0, // Skip to: 17098 +/* 9186 */ MCD_OPC_Decode, 241, 18, 136, 2, // Opcode: MULV_B +/* 9191 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9206 +/* 9196 */ MCD_OPC_CheckPredicate, 30, 217, 30, 0, // Skip to: 17098 +/* 9201 */ MCD_OPC_Decode, 243, 18, 137, 2, // Opcode: MULV_H +/* 9206 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9221 +/* 9211 */ MCD_OPC_CheckPredicate, 30, 202, 30, 0, // Skip to: 17098 +/* 9216 */ MCD_OPC_Decode, 244, 18, 138, 2, // Opcode: MULV_W +/* 9221 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 9236 +/* 9226 */ MCD_OPC_CheckPredicate, 30, 187, 30, 0, // Skip to: 17098 +/* 9231 */ MCD_OPC_Decode, 242, 18, 139, 2, // Opcode: MULV_D +/* 9236 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 9251 +/* 9241 */ MCD_OPC_CheckPredicate, 30, 172, 30, 0, // Skip to: 17098 +/* 9246 */ MCD_OPC_Decode, 206, 16, 140, 2, // Opcode: MADDV_B +/* 9251 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 9266 +/* 9256 */ MCD_OPC_CheckPredicate, 30, 157, 30, 0, // Skip to: 17098 +/* 9261 */ MCD_OPC_Decode, 208, 16, 141, 2, // Opcode: MADDV_H +/* 9266 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 9281 +/* 9271 */ MCD_OPC_CheckPredicate, 30, 142, 30, 0, // Skip to: 17098 +/* 9276 */ MCD_OPC_Decode, 209, 16, 142, 2, // Opcode: MADDV_W +/* 9281 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 9296 +/* 9286 */ MCD_OPC_CheckPredicate, 30, 127, 30, 0, // Skip to: 17098 +/* 9291 */ MCD_OPC_Decode, 207, 16, 143, 2, // Opcode: MADDV_D +/* 9296 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 9311 +/* 9301 */ MCD_OPC_CheckPredicate, 30, 112, 30, 0, // Skip to: 17098 +/* 9306 */ MCD_OPC_Decode, 142, 18, 140, 2, // Opcode: MSUBV_B +/* 9311 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 9326 +/* 9316 */ MCD_OPC_CheckPredicate, 30, 97, 30, 0, // Skip to: 17098 +/* 9321 */ MCD_OPC_Decode, 144, 18, 141, 2, // Opcode: MSUBV_H +/* 9326 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 9341 +/* 9331 */ MCD_OPC_CheckPredicate, 30, 82, 30, 0, // Skip to: 17098 +/* 9336 */ MCD_OPC_Decode, 145, 18, 142, 2, // Opcode: MSUBV_W +/* 9341 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 9356 +/* 9346 */ MCD_OPC_CheckPredicate, 30, 67, 30, 0, // Skip to: 17098 +/* 9351 */ MCD_OPC_Decode, 143, 18, 143, 2, // Opcode: MSUBV_D +/* 9356 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 9371 +/* 9361 */ MCD_OPC_CheckPredicate, 30, 52, 30, 0, // Skip to: 17098 +/* 9366 */ MCD_OPC_Decode, 224, 11, 136, 2, // Opcode: DIV_S_B +/* 9371 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 9386 +/* 9376 */ MCD_OPC_CheckPredicate, 30, 37, 30, 0, // Skip to: 17098 +/* 9381 */ MCD_OPC_Decode, 226, 11, 137, 2, // Opcode: DIV_S_H +/* 9386 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 9401 +/* 9391 */ MCD_OPC_CheckPredicate, 30, 22, 30, 0, // Skip to: 17098 +/* 9396 */ MCD_OPC_Decode, 227, 11, 138, 2, // Opcode: DIV_S_W +/* 9401 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 9416 +/* 9406 */ MCD_OPC_CheckPredicate, 30, 7, 30, 0, // Skip to: 17098 +/* 9411 */ MCD_OPC_Decode, 225, 11, 139, 2, // Opcode: DIV_S_D +/* 9416 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 9431 +/* 9421 */ MCD_OPC_CheckPredicate, 30, 248, 29, 0, // Skip to: 17098 +/* 9426 */ MCD_OPC_Decode, 228, 11, 136, 2, // Opcode: DIV_U_B +/* 9431 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 9446 +/* 9436 */ MCD_OPC_CheckPredicate, 30, 233, 29, 0, // Skip to: 17098 +/* 9441 */ MCD_OPC_Decode, 230, 11, 137, 2, // Opcode: DIV_U_H +/* 9446 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 9461 +/* 9451 */ MCD_OPC_CheckPredicate, 30, 218, 29, 0, // Skip to: 17098 +/* 9456 */ MCD_OPC_Decode, 231, 11, 138, 2, // Opcode: DIV_U_W +/* 9461 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 9476 +/* 9466 */ MCD_OPC_CheckPredicate, 30, 203, 29, 0, // Skip to: 17098 +/* 9471 */ MCD_OPC_Decode, 229, 11, 139, 2, // Opcode: DIV_U_D +/* 9476 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 9491 +/* 9481 */ MCD_OPC_CheckPredicate, 30, 188, 29, 0, // Skip to: 17098 +/* 9486 */ MCD_OPC_Decode, 200, 17, 136, 2, // Opcode: MOD_S_B +/* 9491 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 9506 +/* 9496 */ MCD_OPC_CheckPredicate, 30, 173, 29, 0, // Skip to: 17098 +/* 9501 */ MCD_OPC_Decode, 202, 17, 137, 2, // Opcode: MOD_S_H +/* 9506 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 9521 +/* 9511 */ MCD_OPC_CheckPredicate, 30, 158, 29, 0, // Skip to: 17098 +/* 9516 */ MCD_OPC_Decode, 203, 17, 138, 2, // Opcode: MOD_S_W +/* 9521 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 9536 +/* 9526 */ MCD_OPC_CheckPredicate, 30, 143, 29, 0, // Skip to: 17098 +/* 9531 */ MCD_OPC_Decode, 201, 17, 139, 2, // Opcode: MOD_S_D +/* 9536 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 9551 +/* 9541 */ MCD_OPC_CheckPredicate, 30, 128, 29, 0, // Skip to: 17098 +/* 9546 */ MCD_OPC_Decode, 204, 17, 136, 2, // Opcode: MOD_U_B +/* 9551 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 9566 +/* 9556 */ MCD_OPC_CheckPredicate, 30, 113, 29, 0, // Skip to: 17098 +/* 9561 */ MCD_OPC_Decode, 206, 17, 137, 2, // Opcode: MOD_U_H +/* 9566 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 9581 +/* 9571 */ MCD_OPC_CheckPredicate, 30, 98, 29, 0, // Skip to: 17098 +/* 9576 */ MCD_OPC_Decode, 207, 17, 138, 2, // Opcode: MOD_U_W +/* 9581 */ MCD_OPC_FilterValue, 31, 88, 29, 0, // Skip to: 17098 +/* 9586 */ MCD_OPC_CheckPredicate, 30, 83, 29, 0, // Skip to: 17098 +/* 9591 */ MCD_OPC_Decode, 205, 17, 139, 2, // Opcode: MOD_U_D +/* 9596 */ MCD_OPC_FilterValue, 19, 17, 1, 0, // Skip to: 9874 +/* 9601 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 9604 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9619 +/* 9609 */ MCD_OPC_CheckPredicate, 30, 60, 29, 0, // Skip to: 17098 +/* 9614 */ MCD_OPC_Decode, 131, 12, 144, 2, // Opcode: DOTP_S_H +/* 9619 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9634 +/* 9624 */ MCD_OPC_CheckPredicate, 30, 45, 29, 0, // Skip to: 17098 +/* 9629 */ MCD_OPC_Decode, 132, 12, 145, 2, // Opcode: DOTP_S_W +/* 9634 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 9649 +/* 9639 */ MCD_OPC_CheckPredicate, 30, 30, 29, 0, // Skip to: 17098 +/* 9644 */ MCD_OPC_Decode, 130, 12, 146, 2, // Opcode: DOTP_S_D +/* 9649 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 9664 +/* 9654 */ MCD_OPC_CheckPredicate, 30, 15, 29, 0, // Skip to: 17098 +/* 9659 */ MCD_OPC_Decode, 134, 12, 144, 2, // Opcode: DOTP_U_H +/* 9664 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 9679 +/* 9669 */ MCD_OPC_CheckPredicate, 30, 0, 29, 0, // Skip to: 17098 +/* 9674 */ MCD_OPC_Decode, 135, 12, 145, 2, // Opcode: DOTP_U_W +/* 9679 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 9694 +/* 9684 */ MCD_OPC_CheckPredicate, 30, 241, 28, 0, // Skip to: 17098 +/* 9689 */ MCD_OPC_Decode, 133, 12, 146, 2, // Opcode: DOTP_U_D +/* 9694 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 9709 +/* 9699 */ MCD_OPC_CheckPredicate, 30, 226, 28, 0, // Skip to: 17098 +/* 9704 */ MCD_OPC_Decode, 137, 12, 147, 2, // Opcode: DPADD_S_H +/* 9709 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 9724 +/* 9714 */ MCD_OPC_CheckPredicate, 30, 211, 28, 0, // Skip to: 17098 +/* 9719 */ MCD_OPC_Decode, 138, 12, 148, 2, // Opcode: DPADD_S_W +/* 9724 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 9739 +/* 9729 */ MCD_OPC_CheckPredicate, 30, 196, 28, 0, // Skip to: 17098 +/* 9734 */ MCD_OPC_Decode, 136, 12, 149, 2, // Opcode: DPADD_S_D +/* 9739 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 9754 +/* 9744 */ MCD_OPC_CheckPredicate, 30, 181, 28, 0, // Skip to: 17098 +/* 9749 */ MCD_OPC_Decode, 140, 12, 147, 2, // Opcode: DPADD_U_H +/* 9754 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9769 +/* 9759 */ MCD_OPC_CheckPredicate, 30, 166, 28, 0, // Skip to: 17098 +/* 9764 */ MCD_OPC_Decode, 141, 12, 148, 2, // Opcode: DPADD_U_W +/* 9769 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 9784 +/* 9774 */ MCD_OPC_CheckPredicate, 30, 151, 28, 0, // Skip to: 17098 +/* 9779 */ MCD_OPC_Decode, 139, 12, 149, 2, // Opcode: DPADD_U_D +/* 9784 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 9799 +/* 9789 */ MCD_OPC_CheckPredicate, 30, 136, 28, 0, // Skip to: 17098 +/* 9794 */ MCD_OPC_Decode, 168, 12, 147, 2, // Opcode: DPSUB_S_H +/* 9799 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 9814 +/* 9804 */ MCD_OPC_CheckPredicate, 30, 121, 28, 0, // Skip to: 17098 +/* 9809 */ MCD_OPC_Decode, 169, 12, 148, 2, // Opcode: DPSUB_S_W +/* 9814 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 9829 +/* 9819 */ MCD_OPC_CheckPredicate, 30, 106, 28, 0, // Skip to: 17098 +/* 9824 */ MCD_OPC_Decode, 167, 12, 149, 2, // Opcode: DPSUB_S_D +/* 9829 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 9844 +/* 9834 */ MCD_OPC_CheckPredicate, 30, 91, 28, 0, // Skip to: 17098 +/* 9839 */ MCD_OPC_Decode, 171, 12, 147, 2, // Opcode: DPSUB_U_H +/* 9844 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 9859 +/* 9849 */ MCD_OPC_CheckPredicate, 30, 76, 28, 0, // Skip to: 17098 +/* 9854 */ MCD_OPC_Decode, 172, 12, 148, 2, // Opcode: DPSUB_U_W +/* 9859 */ MCD_OPC_FilterValue, 23, 66, 28, 0, // Skip to: 17098 +/* 9864 */ MCD_OPC_CheckPredicate, 30, 61, 28, 0, // Skip to: 17098 +/* 9869 */ MCD_OPC_Decode, 170, 12, 149, 2, // Opcode: DPSUB_U_D +/* 9874 */ MCD_OPC_FilterValue, 20, 227, 1, 0, // Skip to: 10362 +/* 9879 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 9882 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9897 +/* 9887 */ MCD_OPC_CheckPredicate, 30, 38, 28, 0, // Skip to: 17098 +/* 9892 */ MCD_OPC_Decode, 215, 21, 150, 2, // Opcode: SLD_B +/* 9897 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9912 +/* 9902 */ MCD_OPC_CheckPredicate, 30, 23, 28, 0, // Skip to: 17098 +/* 9907 */ MCD_OPC_Decode, 217, 21, 151, 2, // Opcode: SLD_H +/* 9912 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9927 +/* 9917 */ MCD_OPC_CheckPredicate, 30, 8, 28, 0, // Skip to: 17098 +/* 9922 */ MCD_OPC_Decode, 218, 21, 152, 2, // Opcode: SLD_W +/* 9927 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 9942 +/* 9932 */ MCD_OPC_CheckPredicate, 30, 249, 27, 0, // Skip to: 17098 +/* 9937 */ MCD_OPC_Decode, 216, 21, 153, 2, // Opcode: SLD_D +/* 9942 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 9957 +/* 9947 */ MCD_OPC_CheckPredicate, 30, 234, 27, 0, // Skip to: 17098 +/* 9952 */ MCD_OPC_Decode, 134, 22, 154, 2, // Opcode: SPLAT_B +/* 9957 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 9972 +/* 9962 */ MCD_OPC_CheckPredicate, 30, 219, 27, 0, // Skip to: 17098 +/* 9967 */ MCD_OPC_Decode, 136, 22, 155, 2, // Opcode: SPLAT_H +/* 9972 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 9987 +/* 9977 */ MCD_OPC_CheckPredicate, 30, 204, 27, 0, // Skip to: 17098 +/* 9982 */ MCD_OPC_Decode, 137, 22, 156, 2, // Opcode: SPLAT_W +/* 9987 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 10002 +/* 9992 */ MCD_OPC_CheckPredicate, 30, 189, 27, 0, // Skip to: 17098 +/* 9997 */ MCD_OPC_Decode, 135, 22, 157, 2, // Opcode: SPLAT_D +/* 10002 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 10017 +/* 10007 */ MCD_OPC_CheckPredicate, 30, 174, 27, 0, // Skip to: 17098 +/* 10012 */ MCD_OPC_Decode, 185, 19, 136, 2, // Opcode: PCKEV_B +/* 10017 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 10032 +/* 10022 */ MCD_OPC_CheckPredicate, 30, 159, 27, 0, // Skip to: 17098 +/* 10027 */ MCD_OPC_Decode, 187, 19, 137, 2, // Opcode: PCKEV_H +/* 10032 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 10047 +/* 10037 */ MCD_OPC_CheckPredicate, 30, 144, 27, 0, // Skip to: 17098 +/* 10042 */ MCD_OPC_Decode, 188, 19, 138, 2, // Opcode: PCKEV_W +/* 10047 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 10062 +/* 10052 */ MCD_OPC_CheckPredicate, 30, 129, 27, 0, // Skip to: 17098 +/* 10057 */ MCD_OPC_Decode, 186, 19, 139, 2, // Opcode: PCKEV_D +/* 10062 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 10077 +/* 10067 */ MCD_OPC_CheckPredicate, 30, 114, 27, 0, // Skip to: 17098 +/* 10072 */ MCD_OPC_Decode, 189, 19, 136, 2, // Opcode: PCKOD_B +/* 10077 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 10092 +/* 10082 */ MCD_OPC_CheckPredicate, 30, 99, 27, 0, // Skip to: 17098 +/* 10087 */ MCD_OPC_Decode, 191, 19, 137, 2, // Opcode: PCKOD_H +/* 10092 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 10107 +/* 10097 */ MCD_OPC_CheckPredicate, 30, 84, 27, 0, // Skip to: 17098 +/* 10102 */ MCD_OPC_Decode, 192, 19, 138, 2, // Opcode: PCKOD_W +/* 10107 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 10122 +/* 10112 */ MCD_OPC_CheckPredicate, 30, 69, 27, 0, // Skip to: 17098 +/* 10117 */ MCD_OPC_Decode, 190, 19, 139, 2, // Opcode: PCKOD_D +/* 10122 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 10137 +/* 10127 */ MCD_OPC_CheckPredicate, 30, 54, 27, 0, // Skip to: 17098 +/* 10132 */ MCD_OPC_Decode, 208, 14, 136, 2, // Opcode: ILVL_B +/* 10137 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 10152 +/* 10142 */ MCD_OPC_CheckPredicate, 30, 39, 27, 0, // Skip to: 17098 +/* 10147 */ MCD_OPC_Decode, 210, 14, 137, 2, // Opcode: ILVL_H +/* 10152 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 10167 +/* 10157 */ MCD_OPC_CheckPredicate, 30, 24, 27, 0, // Skip to: 17098 +/* 10162 */ MCD_OPC_Decode, 211, 14, 138, 2, // Opcode: ILVL_W +/* 10167 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 10182 +/* 10172 */ MCD_OPC_CheckPredicate, 30, 9, 27, 0, // Skip to: 17098 +/* 10177 */ MCD_OPC_Decode, 209, 14, 139, 2, // Opcode: ILVL_D +/* 10182 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 10197 +/* 10187 */ MCD_OPC_CheckPredicate, 30, 250, 26, 0, // Skip to: 17098 +/* 10192 */ MCD_OPC_Decode, 216, 14, 136, 2, // Opcode: ILVR_B +/* 10197 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 10212 +/* 10202 */ MCD_OPC_CheckPredicate, 30, 235, 26, 0, // Skip to: 17098 +/* 10207 */ MCD_OPC_Decode, 218, 14, 137, 2, // Opcode: ILVR_H +/* 10212 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 10227 +/* 10217 */ MCD_OPC_CheckPredicate, 30, 220, 26, 0, // Skip to: 17098 +/* 10222 */ MCD_OPC_Decode, 219, 14, 138, 2, // Opcode: ILVR_W +/* 10227 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 10242 +/* 10232 */ MCD_OPC_CheckPredicate, 30, 205, 26, 0, // Skip to: 17098 +/* 10237 */ MCD_OPC_Decode, 217, 14, 139, 2, // Opcode: ILVR_D +/* 10242 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 10257 +/* 10247 */ MCD_OPC_CheckPredicate, 30, 190, 26, 0, // Skip to: 17098 +/* 10252 */ MCD_OPC_Decode, 204, 14, 136, 2, // Opcode: ILVEV_B +/* 10257 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 10272 +/* 10262 */ MCD_OPC_CheckPredicate, 30, 175, 26, 0, // Skip to: 17098 +/* 10267 */ MCD_OPC_Decode, 206, 14, 137, 2, // Opcode: ILVEV_H +/* 10272 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 10287 +/* 10277 */ MCD_OPC_CheckPredicate, 30, 160, 26, 0, // Skip to: 17098 +/* 10282 */ MCD_OPC_Decode, 207, 14, 138, 2, // Opcode: ILVEV_W +/* 10287 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 10302 +/* 10292 */ MCD_OPC_CheckPredicate, 30, 145, 26, 0, // Skip to: 17098 +/* 10297 */ MCD_OPC_Decode, 205, 14, 139, 2, // Opcode: ILVEV_D +/* 10302 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 10317 +/* 10307 */ MCD_OPC_CheckPredicate, 30, 130, 26, 0, // Skip to: 17098 +/* 10312 */ MCD_OPC_Decode, 212, 14, 136, 2, // Opcode: ILVOD_B +/* 10317 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 10332 +/* 10322 */ MCD_OPC_CheckPredicate, 30, 115, 26, 0, // Skip to: 17098 +/* 10327 */ MCD_OPC_Decode, 214, 14, 137, 2, // Opcode: ILVOD_H +/* 10332 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 10347 +/* 10337 */ MCD_OPC_CheckPredicate, 30, 100, 26, 0, // Skip to: 17098 +/* 10342 */ MCD_OPC_Decode, 215, 14, 138, 2, // Opcode: ILVOD_W +/* 10347 */ MCD_OPC_FilterValue, 31, 90, 26, 0, // Skip to: 17098 +/* 10352 */ MCD_OPC_CheckPredicate, 30, 85, 26, 0, // Skip to: 17098 +/* 10357 */ MCD_OPC_Decode, 213, 14, 139, 2, // Opcode: ILVOD_D +/* 10362 */ MCD_OPC_FilterValue, 21, 107, 1, 0, // Skip to: 10730 +/* 10367 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 10370 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10385 +/* 10375 */ MCD_OPC_CheckPredicate, 30, 62, 26, 0, // Skip to: 17098 +/* 10380 */ MCD_OPC_Decode, 157, 24, 140, 2, // Opcode: VSHF_B +/* 10385 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 10400 +/* 10390 */ MCD_OPC_CheckPredicate, 30, 47, 26, 0, // Skip to: 17098 +/* 10395 */ MCD_OPC_Decode, 159, 24, 141, 2, // Opcode: VSHF_H +/* 10400 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 10415 +/* 10405 */ MCD_OPC_CheckPredicate, 30, 32, 26, 0, // Skip to: 17098 +/* 10410 */ MCD_OPC_Decode, 160, 24, 142, 2, // Opcode: VSHF_W +/* 10415 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 10430 +/* 10420 */ MCD_OPC_CheckPredicate, 30, 17, 26, 0, // Skip to: 17098 +/* 10425 */ MCD_OPC_Decode, 158, 24, 143, 2, // Opcode: VSHF_D +/* 10430 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 10445 +/* 10435 */ MCD_OPC_CheckPredicate, 30, 2, 26, 0, // Skip to: 17098 +/* 10440 */ MCD_OPC_Decode, 147, 22, 136, 2, // Opcode: SRAR_B +/* 10445 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 10460 +/* 10450 */ MCD_OPC_CheckPredicate, 30, 243, 25, 0, // Skip to: 17098 +/* 10455 */ MCD_OPC_Decode, 149, 22, 137, 2, // Opcode: SRAR_H +/* 10460 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 10475 +/* 10465 */ MCD_OPC_CheckPredicate, 30, 228, 25, 0, // Skip to: 17098 +/* 10470 */ MCD_OPC_Decode, 150, 22, 138, 2, // Opcode: SRAR_W +/* 10475 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 10490 +/* 10480 */ MCD_OPC_CheckPredicate, 30, 213, 25, 0, // Skip to: 17098 +/* 10485 */ MCD_OPC_Decode, 148, 22, 139, 2, // Opcode: SRAR_D +/* 10490 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 10505 +/* 10495 */ MCD_OPC_CheckPredicate, 30, 198, 25, 0, // Skip to: 17098 +/* 10500 */ MCD_OPC_Decode, 172, 22, 136, 2, // Opcode: SRLR_B +/* 10505 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 10520 +/* 10510 */ MCD_OPC_CheckPredicate, 30, 183, 25, 0, // Skip to: 17098 +/* 10515 */ MCD_OPC_Decode, 174, 22, 137, 2, // Opcode: SRLR_H +/* 10520 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 10535 +/* 10525 */ MCD_OPC_CheckPredicate, 30, 168, 25, 0, // Skip to: 17098 +/* 10530 */ MCD_OPC_Decode, 175, 22, 138, 2, // Opcode: SRLR_W +/* 10535 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 10550 +/* 10540 */ MCD_OPC_CheckPredicate, 30, 153, 25, 0, // Skip to: 17098 +/* 10545 */ MCD_OPC_Decode, 173, 22, 139, 2, // Opcode: SRLR_D +/* 10550 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 10565 +/* 10555 */ MCD_OPC_CheckPredicate, 30, 138, 25, 0, // Skip to: 17098 +/* 10560 */ MCD_OPC_Decode, 191, 14, 144, 2, // Opcode: HADD_S_H +/* 10565 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 10580 +/* 10570 */ MCD_OPC_CheckPredicate, 30, 123, 25, 0, // Skip to: 17098 +/* 10575 */ MCD_OPC_Decode, 192, 14, 145, 2, // Opcode: HADD_S_W +/* 10580 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 10595 +/* 10585 */ MCD_OPC_CheckPredicate, 30, 108, 25, 0, // Skip to: 17098 +/* 10590 */ MCD_OPC_Decode, 190, 14, 146, 2, // Opcode: HADD_S_D +/* 10595 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 10610 +/* 10600 */ MCD_OPC_CheckPredicate, 30, 93, 25, 0, // Skip to: 17098 +/* 10605 */ MCD_OPC_Decode, 194, 14, 144, 2, // Opcode: HADD_U_H +/* 10610 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 10625 +/* 10615 */ MCD_OPC_CheckPredicate, 30, 78, 25, 0, // Skip to: 17098 +/* 10620 */ MCD_OPC_Decode, 195, 14, 145, 2, // Opcode: HADD_U_W +/* 10625 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 10640 +/* 10630 */ MCD_OPC_CheckPredicate, 30, 63, 25, 0, // Skip to: 17098 +/* 10635 */ MCD_OPC_Decode, 193, 14, 146, 2, // Opcode: HADD_U_D +/* 10640 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 10655 +/* 10645 */ MCD_OPC_CheckPredicate, 30, 48, 25, 0, // Skip to: 17098 +/* 10650 */ MCD_OPC_Decode, 197, 14, 144, 2, // Opcode: HSUB_S_H +/* 10655 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 10670 +/* 10660 */ MCD_OPC_CheckPredicate, 30, 33, 25, 0, // Skip to: 17098 +/* 10665 */ MCD_OPC_Decode, 198, 14, 145, 2, // Opcode: HSUB_S_W +/* 10670 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 10685 +/* 10675 */ MCD_OPC_CheckPredicate, 30, 18, 25, 0, // Skip to: 17098 +/* 10680 */ MCD_OPC_Decode, 196, 14, 146, 2, // Opcode: HSUB_S_D +/* 10685 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 10700 +/* 10690 */ MCD_OPC_CheckPredicate, 30, 3, 25, 0, // Skip to: 17098 +/* 10695 */ MCD_OPC_Decode, 200, 14, 144, 2, // Opcode: HSUB_U_H +/* 10700 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 10715 +/* 10705 */ MCD_OPC_CheckPredicate, 30, 244, 24, 0, // Skip to: 17098 +/* 10710 */ MCD_OPC_Decode, 201, 14, 145, 2, // Opcode: HSUB_U_W +/* 10715 */ MCD_OPC_FilterValue, 31, 234, 24, 0, // Skip to: 17098 +/* 10720 */ MCD_OPC_CheckPredicate, 30, 229, 24, 0, // Skip to: 17098 +/* 10725 */ MCD_OPC_Decode, 199, 14, 146, 2, // Opcode: HSUB_U_D +/* 10730 */ MCD_OPC_FilterValue, 25, 26, 2, 0, // Skip to: 11273 +/* 10735 */ MCD_OPC_ExtractField, 20, 6, // Inst{25-20} ... +/* 10738 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10753 +/* 10743 */ MCD_OPC_CheckPredicate, 30, 206, 24, 0, // Skip to: 17098 +/* 10748 */ MCD_OPC_Decode, 211, 21, 158, 2, // Opcode: SLDI_B +/* 10753 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 10775 +/* 10758 */ MCD_OPC_CheckPredicate, 30, 191, 24, 0, // Skip to: 17098 +/* 10763 */ MCD_OPC_CheckField, 19, 1, 0, 184, 24, 0, // Skip to: 17098 +/* 10770 */ MCD_OPC_Decode, 213, 21, 159, 2, // Opcode: SLDI_H +/* 10775 */ MCD_OPC_FilterValue, 3, 62, 0, 0, // Skip to: 10842 +/* 10780 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... +/* 10783 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10798 +/* 10788 */ MCD_OPC_CheckPredicate, 30, 161, 24, 0, // Skip to: 17098 +/* 10793 */ MCD_OPC_Decode, 214, 21, 160, 2, // Opcode: SLDI_W +/* 10798 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 10820 +/* 10803 */ MCD_OPC_CheckPredicate, 30, 146, 24, 0, // Skip to: 17098 +/* 10808 */ MCD_OPC_CheckField, 17, 1, 0, 139, 24, 0, // Skip to: 17098 +/* 10815 */ MCD_OPC_Decode, 212, 21, 161, 2, // Opcode: SLDI_D +/* 10820 */ MCD_OPC_FilterValue, 3, 129, 24, 0, // Skip to: 17098 +/* 10825 */ MCD_OPC_CheckPredicate, 30, 124, 24, 0, // Skip to: 17098 +/* 10830 */ MCD_OPC_CheckField, 16, 2, 2, 117, 24, 0, // Skip to: 17098 +/* 10837 */ MCD_OPC_Decode, 182, 10, 162, 2, // Opcode: CTCMSA +/* 10842 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 10857 +/* 10847 */ MCD_OPC_CheckPredicate, 30, 102, 24, 0, // Skip to: 17098 +/* 10852 */ MCD_OPC_Decode, 130, 22, 163, 2, // Opcode: SPLATI_B +/* 10857 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 10879 +/* 10862 */ MCD_OPC_CheckPredicate, 30, 87, 24, 0, // Skip to: 17098 +/* 10867 */ MCD_OPC_CheckField, 19, 1, 0, 80, 24, 0, // Skip to: 17098 +/* 10874 */ MCD_OPC_Decode, 132, 22, 164, 2, // Opcode: SPLATI_H +/* 10879 */ MCD_OPC_FilterValue, 7, 62, 0, 0, // Skip to: 10946 +/* 10884 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... +/* 10887 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10902 +/* 10892 */ MCD_OPC_CheckPredicate, 30, 57, 24, 0, // Skip to: 17098 +/* 10897 */ MCD_OPC_Decode, 133, 22, 165, 2, // Opcode: SPLATI_W +/* 10902 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 10924 +/* 10907 */ MCD_OPC_CheckPredicate, 30, 42, 24, 0, // Skip to: 17098 +/* 10912 */ MCD_OPC_CheckField, 17, 1, 0, 35, 24, 0, // Skip to: 17098 +/* 10919 */ MCD_OPC_Decode, 131, 22, 166, 2, // Opcode: SPLATI_D +/* 10924 */ MCD_OPC_FilterValue, 3, 25, 24, 0, // Skip to: 17098 +/* 10929 */ MCD_OPC_CheckPredicate, 30, 20, 24, 0, // Skip to: 17098 +/* 10934 */ MCD_OPC_CheckField, 16, 2, 2, 13, 24, 0, // Skip to: 17098 +/* 10941 */ MCD_OPC_Decode, 147, 9, 167, 2, // Opcode: CFCMSA +/* 10946 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 10961 +/* 10951 */ MCD_OPC_CheckPredicate, 30, 254, 23, 0, // Skip to: 17098 +/* 10956 */ MCD_OPC_Decode, 158, 10, 168, 2, // Opcode: COPY_S_B +/* 10961 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 10983 +/* 10966 */ MCD_OPC_CheckPredicate, 30, 239, 23, 0, // Skip to: 17098 +/* 10971 */ MCD_OPC_CheckField, 19, 1, 0, 232, 23, 0, // Skip to: 17098 +/* 10978 */ MCD_OPC_Decode, 160, 10, 169, 2, // Opcode: COPY_S_H +/* 10983 */ MCD_OPC_FilterValue, 11, 62, 0, 0, // Skip to: 11050 +/* 10988 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... +/* 10991 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11006 +/* 10996 */ MCD_OPC_CheckPredicate, 30, 209, 23, 0, // Skip to: 17098 +/* 11001 */ MCD_OPC_Decode, 161, 10, 170, 2, // Opcode: COPY_S_W +/* 11006 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 11028 +/* 11011 */ MCD_OPC_CheckPredicate, 38, 194, 23, 0, // Skip to: 17098 +/* 11016 */ MCD_OPC_CheckField, 17, 1, 0, 187, 23, 0, // Skip to: 17098 +/* 11023 */ MCD_OPC_Decode, 159, 10, 171, 2, // Opcode: COPY_S_D +/* 11028 */ MCD_OPC_FilterValue, 3, 177, 23, 0, // Skip to: 17098 +/* 11033 */ MCD_OPC_CheckPredicate, 30, 172, 23, 0, // Skip to: 17098 +/* 11038 */ MCD_OPC_CheckField, 16, 2, 2, 165, 23, 0, // Skip to: 17098 +/* 11045 */ MCD_OPC_Decode, 216, 17, 172, 2, // Opcode: MOVE_V +/* 11050 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 11065 +/* 11055 */ MCD_OPC_CheckPredicate, 30, 150, 23, 0, // Skip to: 17098 +/* 11060 */ MCD_OPC_Decode, 162, 10, 168, 2, // Opcode: COPY_U_B +/* 11065 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 11087 +/* 11070 */ MCD_OPC_CheckPredicate, 30, 135, 23, 0, // Skip to: 17098 +/* 11075 */ MCD_OPC_CheckField, 19, 1, 0, 128, 23, 0, // Skip to: 17098 +/* 11082 */ MCD_OPC_Decode, 163, 10, 169, 2, // Opcode: COPY_U_H +/* 11087 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 11109 +/* 11092 */ MCD_OPC_CheckPredicate, 38, 113, 23, 0, // Skip to: 17098 +/* 11097 */ MCD_OPC_CheckField, 18, 2, 0, 106, 23, 0, // Skip to: 17098 +/* 11104 */ MCD_OPC_Decode, 164, 10, 170, 2, // Opcode: COPY_U_W +/* 11109 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 11124 +/* 11114 */ MCD_OPC_CheckPredicate, 30, 91, 23, 0, // Skip to: 17098 +/* 11119 */ MCD_OPC_Decode, 221, 14, 173, 2, // Opcode: INSERT_B +/* 11124 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 11146 +/* 11129 */ MCD_OPC_CheckPredicate, 30, 76, 23, 0, // Skip to: 17098 +/* 11134 */ MCD_OPC_CheckField, 19, 1, 0, 69, 23, 0, // Skip to: 17098 +/* 11141 */ MCD_OPC_Decode, 223, 14, 174, 2, // Opcode: INSERT_H +/* 11146 */ MCD_OPC_FilterValue, 19, 40, 0, 0, // Skip to: 11191 +/* 11151 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... +/* 11154 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11169 +/* 11159 */ MCD_OPC_CheckPredicate, 30, 46, 23, 0, // Skip to: 17098 +/* 11164 */ MCD_OPC_Decode, 224, 14, 175, 2, // Opcode: INSERT_W +/* 11169 */ MCD_OPC_FilterValue, 2, 36, 23, 0, // Skip to: 17098 +/* 11174 */ MCD_OPC_CheckPredicate, 38, 31, 23, 0, // Skip to: 17098 +/* 11179 */ MCD_OPC_CheckField, 17, 1, 0, 24, 23, 0, // Skip to: 17098 +/* 11186 */ MCD_OPC_Decode, 222, 14, 176, 2, // Opcode: INSERT_D +/* 11191 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 11206 +/* 11196 */ MCD_OPC_CheckPredicate, 30, 9, 23, 0, // Skip to: 17098 +/* 11201 */ MCD_OPC_Decode, 226, 14, 177, 2, // Opcode: INSVE_B +/* 11206 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 11228 +/* 11211 */ MCD_OPC_CheckPredicate, 30, 250, 22, 0, // Skip to: 17098 +/* 11216 */ MCD_OPC_CheckField, 19, 1, 0, 243, 22, 0, // Skip to: 17098 +/* 11223 */ MCD_OPC_Decode, 228, 14, 177, 2, // Opcode: INSVE_H +/* 11228 */ MCD_OPC_FilterValue, 23, 233, 22, 0, // Skip to: 17098 +/* 11233 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... +/* 11236 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11251 +/* 11241 */ MCD_OPC_CheckPredicate, 30, 220, 22, 0, // Skip to: 17098 +/* 11246 */ MCD_OPC_Decode, 229, 14, 177, 2, // Opcode: INSVE_W +/* 11251 */ MCD_OPC_FilterValue, 2, 210, 22, 0, // Skip to: 17098 +/* 11256 */ MCD_OPC_CheckPredicate, 30, 205, 22, 0, // Skip to: 17098 +/* 11261 */ MCD_OPC_CheckField, 17, 1, 0, 198, 22, 0, // Skip to: 17098 +/* 11268 */ MCD_OPC_Decode, 227, 14, 177, 2, // Opcode: INSVE_D +/* 11273 */ MCD_OPC_FilterValue, 26, 227, 1, 0, // Skip to: 11761 +/* 11278 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 11281 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11296 +/* 11286 */ MCD_OPC_CheckPredicate, 30, 175, 22, 0, // Skip to: 17098 +/* 11291 */ MCD_OPC_Decode, 147, 13, 138, 2, // Opcode: FCAF_W +/* 11296 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 11311 +/* 11301 */ MCD_OPC_CheckPredicate, 30, 160, 22, 0, // Skip to: 17098 +/* 11306 */ MCD_OPC_Decode, 146, 13, 139, 2, // Opcode: FCAF_D +/* 11311 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 11326 +/* 11316 */ MCD_OPC_CheckPredicate, 30, 145, 22, 0, // Skip to: 17098 +/* 11321 */ MCD_OPC_Decode, 174, 13, 138, 2, // Opcode: FCUN_W +/* 11326 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 11341 +/* 11331 */ MCD_OPC_CheckPredicate, 30, 130, 22, 0, // Skip to: 17098 +/* 11336 */ MCD_OPC_Decode, 173, 13, 139, 2, // Opcode: FCUN_D +/* 11341 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 11356 +/* 11346 */ MCD_OPC_CheckPredicate, 30, 115, 22, 0, // Skip to: 17098 +/* 11351 */ MCD_OPC_Decode, 149, 13, 138, 2, // Opcode: FCEQ_W +/* 11356 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 11371 +/* 11361 */ MCD_OPC_CheckPredicate, 30, 100, 22, 0, // Skip to: 17098 +/* 11366 */ MCD_OPC_Decode, 148, 13, 139, 2, // Opcode: FCEQ_D +/* 11371 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 11386 +/* 11376 */ MCD_OPC_CheckPredicate, 30, 85, 22, 0, // Skip to: 17098 +/* 11381 */ MCD_OPC_Decode, 166, 13, 138, 2, // Opcode: FCUEQ_W +/* 11386 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 11401 +/* 11391 */ MCD_OPC_CheckPredicate, 30, 70, 22, 0, // Skip to: 17098 +/* 11396 */ MCD_OPC_Decode, 165, 13, 139, 2, // Opcode: FCUEQ_D +/* 11401 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 11416 +/* 11406 */ MCD_OPC_CheckPredicate, 30, 55, 22, 0, // Skip to: 17098 +/* 11411 */ MCD_OPC_Decode, 155, 13, 138, 2, // Opcode: FCLT_W +/* 11416 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 11431 +/* 11421 */ MCD_OPC_CheckPredicate, 30, 40, 22, 0, // Skip to: 17098 +/* 11426 */ MCD_OPC_Decode, 154, 13, 139, 2, // Opcode: FCLT_D +/* 11431 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 11446 +/* 11436 */ MCD_OPC_CheckPredicate, 30, 25, 22, 0, // Skip to: 17098 +/* 11441 */ MCD_OPC_Decode, 170, 13, 138, 2, // Opcode: FCULT_W +/* 11446 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 11461 +/* 11451 */ MCD_OPC_CheckPredicate, 30, 10, 22, 0, // Skip to: 17098 +/* 11456 */ MCD_OPC_Decode, 169, 13, 139, 2, // Opcode: FCULT_D +/* 11461 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 11476 +/* 11466 */ MCD_OPC_CheckPredicate, 30, 251, 21, 0, // Skip to: 17098 +/* 11471 */ MCD_OPC_Decode, 153, 13, 138, 2, // Opcode: FCLE_W +/* 11476 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 11491 +/* 11481 */ MCD_OPC_CheckPredicate, 30, 236, 21, 0, // Skip to: 17098 +/* 11486 */ MCD_OPC_Decode, 152, 13, 139, 2, // Opcode: FCLE_D +/* 11491 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 11506 +/* 11496 */ MCD_OPC_CheckPredicate, 30, 221, 21, 0, // Skip to: 17098 +/* 11501 */ MCD_OPC_Decode, 168, 13, 138, 2, // Opcode: FCULE_W +/* 11506 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 11521 +/* 11511 */ MCD_OPC_CheckPredicate, 30, 206, 21, 0, // Skip to: 17098 +/* 11516 */ MCD_OPC_Decode, 167, 13, 139, 2, // Opcode: FCULE_D +/* 11521 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 11536 +/* 11526 */ MCD_OPC_CheckPredicate, 30, 191, 21, 0, // Skip to: 17098 +/* 11531 */ MCD_OPC_Decode, 135, 14, 138, 2, // Opcode: FSAF_W +/* 11536 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 11551 +/* 11541 */ MCD_OPC_CheckPredicate, 30, 176, 21, 0, // Skip to: 17098 +/* 11546 */ MCD_OPC_Decode, 134, 14, 139, 2, // Opcode: FSAF_D +/* 11551 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 11566 +/* 11556 */ MCD_OPC_CheckPredicate, 30, 161, 21, 0, // Skip to: 17098 +/* 11561 */ MCD_OPC_Decode, 173, 14, 138, 2, // Opcode: FSUN_W +/* 11566 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 11581 +/* 11571 */ MCD_OPC_CheckPredicate, 30, 146, 21, 0, // Skip to: 17098 +/* 11576 */ MCD_OPC_Decode, 172, 14, 139, 2, // Opcode: FSUN_D +/* 11581 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 11596 +/* 11586 */ MCD_OPC_CheckPredicate, 30, 131, 21, 0, // Skip to: 17098 +/* 11591 */ MCD_OPC_Decode, 137, 14, 138, 2, // Opcode: FSEQ_W +/* 11596 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 11611 +/* 11601 */ MCD_OPC_CheckPredicate, 30, 116, 21, 0, // Skip to: 17098 +/* 11606 */ MCD_OPC_Decode, 136, 14, 139, 2, // Opcode: FSEQ_D +/* 11611 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 11626 +/* 11616 */ MCD_OPC_CheckPredicate, 30, 101, 21, 0, // Skip to: 17098 +/* 11621 */ MCD_OPC_Decode, 165, 14, 138, 2, // Opcode: FSUEQ_W +/* 11626 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 11641 +/* 11631 */ MCD_OPC_CheckPredicate, 30, 86, 21, 0, // Skip to: 17098 +/* 11636 */ MCD_OPC_Decode, 164, 14, 139, 2, // Opcode: FSUEQ_D +/* 11641 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 11656 +/* 11646 */ MCD_OPC_CheckPredicate, 30, 71, 21, 0, // Skip to: 17098 +/* 11651 */ MCD_OPC_Decode, 141, 14, 138, 2, // Opcode: FSLT_W +/* 11656 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 11671 +/* 11661 */ MCD_OPC_CheckPredicate, 30, 56, 21, 0, // Skip to: 17098 +/* 11666 */ MCD_OPC_Decode, 140, 14, 139, 2, // Opcode: FSLT_D +/* 11671 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 11686 +/* 11676 */ MCD_OPC_CheckPredicate, 30, 41, 21, 0, // Skip to: 17098 +/* 11681 */ MCD_OPC_Decode, 169, 14, 138, 2, // Opcode: FSULT_W +/* 11686 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 11701 +/* 11691 */ MCD_OPC_CheckPredicate, 30, 26, 21, 0, // Skip to: 17098 +/* 11696 */ MCD_OPC_Decode, 168, 14, 139, 2, // Opcode: FSULT_D +/* 11701 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 11716 +/* 11706 */ MCD_OPC_CheckPredicate, 30, 11, 21, 0, // Skip to: 17098 +/* 11711 */ MCD_OPC_Decode, 139, 14, 138, 2, // Opcode: FSLE_W +/* 11716 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 11731 +/* 11721 */ MCD_OPC_CheckPredicate, 30, 252, 20, 0, // Skip to: 17098 +/* 11726 */ MCD_OPC_Decode, 138, 14, 139, 2, // Opcode: FSLE_D +/* 11731 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 11746 +/* 11736 */ MCD_OPC_CheckPredicate, 30, 237, 20, 0, // Skip to: 17098 +/* 11741 */ MCD_OPC_Decode, 167, 14, 138, 2, // Opcode: FSULE_W +/* 11746 */ MCD_OPC_FilterValue, 31, 227, 20, 0, // Skip to: 17098 +/* 11751 */ MCD_OPC_CheckPredicate, 30, 222, 20, 0, // Skip to: 17098 +/* 11756 */ MCD_OPC_Decode, 166, 14, 139, 2, // Opcode: FSULE_D +/* 11761 */ MCD_OPC_FilterValue, 27, 137, 1, 0, // Skip to: 12159 +/* 11766 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 11769 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11784 +/* 11774 */ MCD_OPC_CheckPredicate, 30, 199, 20, 0, // Skip to: 17098 +/* 11779 */ MCD_OPC_Decode, 145, 13, 138, 2, // Opcode: FADD_W +/* 11784 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 11799 +/* 11789 */ MCD_OPC_CheckPredicate, 30, 184, 20, 0, // Skip to: 17098 +/* 11794 */ MCD_OPC_Decode, 136, 13, 139, 2, // Opcode: FADD_D +/* 11799 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 11814 +/* 11804 */ MCD_OPC_CheckPredicate, 30, 169, 20, 0, // Skip to: 17098 +/* 11809 */ MCD_OPC_Decode, 163, 14, 138, 2, // Opcode: FSUB_W +/* 11814 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 11829 +/* 11819 */ MCD_OPC_CheckPredicate, 30, 154, 20, 0, // Skip to: 17098 +/* 11824 */ MCD_OPC_Decode, 154, 14, 139, 2, // Opcode: FSUB_D +/* 11829 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 11844 +/* 11834 */ MCD_OPC_CheckPredicate, 30, 139, 20, 0, // Skip to: 17098 +/* 11839 */ MCD_OPC_Decode, 246, 13, 138, 2, // Opcode: FMUL_W +/* 11844 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 11859 +/* 11849 */ MCD_OPC_CheckPredicate, 30, 124, 20, 0, // Skip to: 17098 +/* 11854 */ MCD_OPC_Decode, 237, 13, 139, 2, // Opcode: FMUL_D +/* 11859 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 11874 +/* 11864 */ MCD_OPC_CheckPredicate, 30, 109, 20, 0, // Skip to: 17098 +/* 11869 */ MCD_OPC_Decode, 183, 13, 138, 2, // Opcode: FDIV_W +/* 11874 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 11889 +/* 11879 */ MCD_OPC_CheckPredicate, 30, 94, 20, 0, // Skip to: 17098 +/* 11884 */ MCD_OPC_Decode, 175, 13, 139, 2, // Opcode: FDIV_D +/* 11889 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 11904 +/* 11894 */ MCD_OPC_CheckPredicate, 30, 79, 20, 0, // Skip to: 17098 +/* 11899 */ MCD_OPC_Decode, 218, 13, 142, 2, // Opcode: FMADD_W +/* 11904 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 11919 +/* 11909 */ MCD_OPC_CheckPredicate, 30, 64, 20, 0, // Skip to: 17098 +/* 11914 */ MCD_OPC_Decode, 217, 13, 143, 2, // Opcode: FMADD_D +/* 11919 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 11934 +/* 11924 */ MCD_OPC_CheckPredicate, 30, 49, 20, 0, // Skip to: 17098 +/* 11929 */ MCD_OPC_Decode, 236, 13, 142, 2, // Opcode: FMSUB_W +/* 11934 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 11949 +/* 11939 */ MCD_OPC_CheckPredicate, 30, 34, 20, 0, // Skip to: 17098 +/* 11944 */ MCD_OPC_Decode, 235, 13, 143, 2, // Opcode: FMSUB_D +/* 11949 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 11964 +/* 11954 */ MCD_OPC_CheckPredicate, 30, 19, 20, 0, // Skip to: 17098 +/* 11959 */ MCD_OPC_Decode, 187, 13, 138, 2, // Opcode: FEXP2_W +/* 11964 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 11979 +/* 11969 */ MCD_OPC_CheckPredicate, 30, 4, 20, 0, // Skip to: 17098 +/* 11974 */ MCD_OPC_Decode, 186, 13, 139, 2, // Opcode: FEXP2_D +/* 11979 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 11994 +/* 11984 */ MCD_OPC_CheckPredicate, 30, 245, 19, 0, // Skip to: 17098 +/* 11989 */ MCD_OPC_Decode, 184, 13, 178, 2, // Opcode: FEXDO_H +/* 11994 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 12009 +/* 11999 */ MCD_OPC_CheckPredicate, 30, 230, 19, 0, // Skip to: 17098 +/* 12004 */ MCD_OPC_Decode, 185, 13, 179, 2, // Opcode: FEXDO_W +/* 12009 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 12024 +/* 12014 */ MCD_OPC_CheckPredicate, 30, 215, 19, 0, // Skip to: 17098 +/* 12019 */ MCD_OPC_Decode, 178, 14, 178, 2, // Opcode: FTQ_H +/* 12024 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 12039 +/* 12029 */ MCD_OPC_CheckPredicate, 30, 200, 19, 0, // Skip to: 17098 +/* 12034 */ MCD_OPC_Decode, 179, 14, 179, 2, // Opcode: FTQ_W +/* 12039 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 12054 +/* 12044 */ MCD_OPC_CheckPredicate, 30, 185, 19, 0, // Skip to: 17098 +/* 12049 */ MCD_OPC_Decode, 226, 13, 138, 2, // Opcode: FMIN_W +/* 12054 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 12069 +/* 12059 */ MCD_OPC_CheckPredicate, 30, 170, 19, 0, // Skip to: 17098 +/* 12064 */ MCD_OPC_Decode, 225, 13, 139, 2, // Opcode: FMIN_D +/* 12069 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 12084 +/* 12074 */ MCD_OPC_CheckPredicate, 30, 155, 19, 0, // Skip to: 17098 +/* 12079 */ MCD_OPC_Decode, 224, 13, 138, 2, // Opcode: FMIN_A_W +/* 12084 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 12099 +/* 12089 */ MCD_OPC_CheckPredicate, 30, 140, 19, 0, // Skip to: 17098 +/* 12094 */ MCD_OPC_Decode, 223, 13, 139, 2, // Opcode: FMIN_A_D +/* 12099 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 12114 +/* 12104 */ MCD_OPC_CheckPredicate, 30, 125, 19, 0, // Skip to: 17098 +/* 12109 */ MCD_OPC_Decode, 222, 13, 138, 2, // Opcode: FMAX_W +/* 12114 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 12129 +/* 12119 */ MCD_OPC_CheckPredicate, 30, 110, 19, 0, // Skip to: 17098 +/* 12124 */ MCD_OPC_Decode, 221, 13, 139, 2, // Opcode: FMAX_D +/* 12129 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 12144 +/* 12134 */ MCD_OPC_CheckPredicate, 30, 95, 19, 0, // Skip to: 17098 +/* 12139 */ MCD_OPC_Decode, 220, 13, 138, 2, // Opcode: FMAX_A_W +/* 12144 */ MCD_OPC_FilterValue, 31, 85, 19, 0, // Skip to: 17098 +/* 12149 */ MCD_OPC_CheckPredicate, 30, 80, 19, 0, // Skip to: 17098 +/* 12154 */ MCD_OPC_Decode, 219, 13, 139, 2, // Opcode: FMAX_A_D +/* 12159 */ MCD_OPC_FilterValue, 28, 107, 1, 0, // Skip to: 12527 +/* 12164 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 12167 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 12182 +/* 12172 */ MCD_OPC_CheckPredicate, 30, 57, 19, 0, // Skip to: 17098 +/* 12177 */ MCD_OPC_Decode, 164, 13, 138, 2, // Opcode: FCOR_W +/* 12182 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 12197 +/* 12187 */ MCD_OPC_CheckPredicate, 30, 42, 19, 0, // Skip to: 17098 +/* 12192 */ MCD_OPC_Decode, 163, 13, 139, 2, // Opcode: FCOR_D +/* 12197 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 12212 +/* 12202 */ MCD_OPC_CheckPredicate, 30, 27, 19, 0, // Skip to: 17098 +/* 12207 */ MCD_OPC_Decode, 172, 13, 138, 2, // Opcode: FCUNE_W +/* 12212 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 12227 +/* 12217 */ MCD_OPC_CheckPredicate, 30, 12, 19, 0, // Skip to: 17098 +/* 12222 */ MCD_OPC_Decode, 171, 13, 139, 2, // Opcode: FCUNE_D +/* 12227 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 12242 +/* 12232 */ MCD_OPC_CheckPredicate, 30, 253, 18, 0, // Skip to: 17098 +/* 12237 */ MCD_OPC_Decode, 162, 13, 138, 2, // Opcode: FCNE_W +/* 12242 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 12257 +/* 12247 */ MCD_OPC_CheckPredicate, 30, 238, 18, 0, // Skip to: 17098 +/* 12252 */ MCD_OPC_Decode, 161, 13, 139, 2, // Opcode: FCNE_D +/* 12257 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 12272 +/* 12262 */ MCD_OPC_CheckPredicate, 30, 223, 18, 0, // Skip to: 17098 +/* 12267 */ MCD_OPC_Decode, 250, 18, 137, 2, // Opcode: MUL_Q_H +/* 12272 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 12287 +/* 12277 */ MCD_OPC_CheckPredicate, 30, 208, 18, 0, // Skip to: 17098 +/* 12282 */ MCD_OPC_Decode, 251, 18, 138, 2, // Opcode: MUL_Q_W +/* 12287 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 12302 +/* 12292 */ MCD_OPC_CheckPredicate, 30, 193, 18, 0, // Skip to: 17098 +/* 12297 */ MCD_OPC_Decode, 216, 16, 141, 2, // Opcode: MADD_Q_H +/* 12302 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 12317 +/* 12307 */ MCD_OPC_CheckPredicate, 30, 178, 18, 0, // Skip to: 17098 +/* 12312 */ MCD_OPC_Decode, 217, 16, 142, 2, // Opcode: MADD_Q_W +/* 12317 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 12332 +/* 12322 */ MCD_OPC_CheckPredicate, 30, 163, 18, 0, // Skip to: 17098 +/* 12327 */ MCD_OPC_Decode, 152, 18, 141, 2, // Opcode: MSUB_Q_H +/* 12332 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 12347 +/* 12337 */ MCD_OPC_CheckPredicate, 30, 148, 18, 0, // Skip to: 17098 +/* 12342 */ MCD_OPC_Decode, 153, 18, 142, 2, // Opcode: MSUB_Q_W +/* 12347 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 12362 +/* 12352 */ MCD_OPC_CheckPredicate, 30, 133, 18, 0, // Skip to: 17098 +/* 12357 */ MCD_OPC_Decode, 145, 14, 138, 2, // Opcode: FSOR_W +/* 12362 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 12377 +/* 12367 */ MCD_OPC_CheckPredicate, 30, 118, 18, 0, // Skip to: 17098 +/* 12372 */ MCD_OPC_Decode, 144, 14, 139, 2, // Opcode: FSOR_D +/* 12377 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 12392 +/* 12382 */ MCD_OPC_CheckPredicate, 30, 103, 18, 0, // Skip to: 17098 +/* 12387 */ MCD_OPC_Decode, 171, 14, 138, 2, // Opcode: FSUNE_W +/* 12392 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 12407 +/* 12397 */ MCD_OPC_CheckPredicate, 30, 88, 18, 0, // Skip to: 17098 +/* 12402 */ MCD_OPC_Decode, 170, 14, 139, 2, // Opcode: FSUNE_D +/* 12407 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 12422 +/* 12412 */ MCD_OPC_CheckPredicate, 30, 73, 18, 0, // Skip to: 17098 +/* 12417 */ MCD_OPC_Decode, 143, 14, 138, 2, // Opcode: FSNE_W +/* 12422 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 12437 +/* 12427 */ MCD_OPC_CheckPredicate, 30, 58, 18, 0, // Skip to: 17098 +/* 12432 */ MCD_OPC_Decode, 142, 14, 139, 2, // Opcode: FSNE_D +/* 12437 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 12452 +/* 12442 */ MCD_OPC_CheckPredicate, 30, 43, 18, 0, // Skip to: 17098 +/* 12447 */ MCD_OPC_Decode, 224, 18, 137, 2, // Opcode: MULR_Q_H +/* 12452 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 12467 +/* 12457 */ MCD_OPC_CheckPredicate, 30, 28, 18, 0, // Skip to: 17098 +/* 12462 */ MCD_OPC_Decode, 225, 18, 138, 2, // Opcode: MULR_Q_W +/* 12467 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 12482 +/* 12472 */ MCD_OPC_CheckPredicate, 30, 13, 18, 0, // Skip to: 17098 +/* 12477 */ MCD_OPC_Decode, 200, 16, 141, 2, // Opcode: MADDR_Q_H +/* 12482 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 12497 +/* 12487 */ MCD_OPC_CheckPredicate, 30, 254, 17, 0, // Skip to: 17098 +/* 12492 */ MCD_OPC_Decode, 201, 16, 142, 2, // Opcode: MADDR_Q_W +/* 12497 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 12512 +/* 12502 */ MCD_OPC_CheckPredicate, 30, 239, 17, 0, // Skip to: 17098 +/* 12507 */ MCD_OPC_Decode, 136, 18, 141, 2, // Opcode: MSUBR_Q_H +/* 12512 */ MCD_OPC_FilterValue, 29, 229, 17, 0, // Skip to: 17098 +/* 12517 */ MCD_OPC_CheckPredicate, 30, 224, 17, 0, // Skip to: 17098 +/* 12522 */ MCD_OPC_Decode, 137, 18, 142, 2, // Opcode: MSUBR_Q_W +/* 12527 */ MCD_OPC_FilterValue, 30, 76, 3, 0, // Skip to: 13376 +/* 12532 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 12535 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12550 +/* 12540 */ MCD_OPC_CheckPredicate, 30, 201, 17, 0, // Skip to: 17098 +/* 12545 */ MCD_OPC_Decode, 230, 6, 136, 2, // Opcode: AND_V +/* 12550 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 12565 +/* 12555 */ MCD_OPC_CheckPredicate, 30, 186, 17, 0, // Skip to: 17098 +/* 12560 */ MCD_OPC_Decode, 174, 19, 136, 2, // Opcode: OR_V +/* 12565 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 12580 +/* 12570 */ MCD_OPC_CheckPredicate, 30, 171, 17, 0, // Skip to: 17098 +/* 12575 */ MCD_OPC_Decode, 157, 19, 136, 2, // Opcode: NOR_V +/* 12580 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 12595 +/* 12585 */ MCD_OPC_CheckPredicate, 30, 156, 17, 0, // Skip to: 17098 +/* 12590 */ MCD_OPC_Decode, 183, 24, 136, 2, // Opcode: XOR_V +/* 12595 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 12610 +/* 12600 */ MCD_OPC_CheckPredicate, 30, 141, 17, 0, // Skip to: 17098 +/* 12605 */ MCD_OPC_Decode, 167, 8, 140, 2, // Opcode: BMNZ_V +/* 12610 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 12625 +/* 12615 */ MCD_OPC_CheckPredicate, 30, 126, 17, 0, // Skip to: 17098 +/* 12620 */ MCD_OPC_Decode, 169, 8, 140, 2, // Opcode: BMZ_V +/* 12625 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 12640 +/* 12630 */ MCD_OPC_CheckPredicate, 30, 111, 17, 0, // Skip to: 17098 +/* 12635 */ MCD_OPC_Decode, 220, 8, 140, 2, // Opcode: BSEL_V +/* 12640 */ MCD_OPC_FilterValue, 24, 243, 0, 0, // Skip to: 12888 +/* 12645 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 12648 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12663 +/* 12653 */ MCD_OPC_CheckPredicate, 30, 88, 17, 0, // Skip to: 17098 +/* 12658 */ MCD_OPC_Decode, 200, 13, 180, 2, // Opcode: FILL_B +/* 12663 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 12678 +/* 12668 */ MCD_OPC_CheckPredicate, 30, 73, 17, 0, // Skip to: 17098 +/* 12673 */ MCD_OPC_Decode, 202, 13, 181, 2, // Opcode: FILL_H +/* 12678 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 12693 +/* 12683 */ MCD_OPC_CheckPredicate, 30, 58, 17, 0, // Skip to: 17098 +/* 12688 */ MCD_OPC_Decode, 203, 13, 182, 2, // Opcode: FILL_W +/* 12693 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 12708 +/* 12698 */ MCD_OPC_CheckPredicate, 38, 43, 17, 0, // Skip to: 17098 +/* 12703 */ MCD_OPC_Decode, 201, 13, 183, 2, // Opcode: FILL_D +/* 12708 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 12723 +/* 12713 */ MCD_OPC_CheckPredicate, 30, 28, 17, 0, // Skip to: 17098 +/* 12718 */ MCD_OPC_Decode, 193, 19, 172, 2, // Opcode: PCNT_B +/* 12723 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 12738 +/* 12728 */ MCD_OPC_CheckPredicate, 30, 13, 17, 0, // Skip to: 17098 +/* 12733 */ MCD_OPC_Decode, 195, 19, 184, 2, // Opcode: PCNT_H +/* 12738 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 12753 +/* 12743 */ MCD_OPC_CheckPredicate, 30, 254, 16, 0, // Skip to: 17098 +/* 12748 */ MCD_OPC_Decode, 196, 19, 185, 2, // Opcode: PCNT_W +/* 12753 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 12768 +/* 12758 */ MCD_OPC_CheckPredicate, 30, 239, 16, 0, // Skip to: 17098 +/* 12763 */ MCD_OPC_Decode, 194, 19, 186, 2, // Opcode: PCNT_D +/* 12768 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 12783 +/* 12773 */ MCD_OPC_CheckPredicate, 30, 224, 16, 0, // Skip to: 17098 +/* 12778 */ MCD_OPC_Decode, 131, 19, 172, 2, // Opcode: NLOC_B +/* 12783 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 12798 +/* 12788 */ MCD_OPC_CheckPredicate, 30, 209, 16, 0, // Skip to: 17098 +/* 12793 */ MCD_OPC_Decode, 133, 19, 184, 2, // Opcode: NLOC_H +/* 12798 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 12813 +/* 12803 */ MCD_OPC_CheckPredicate, 30, 194, 16, 0, // Skip to: 17098 +/* 12808 */ MCD_OPC_Decode, 134, 19, 185, 2, // Opcode: NLOC_W +/* 12813 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 12828 +/* 12818 */ MCD_OPC_CheckPredicate, 30, 179, 16, 0, // Skip to: 17098 +/* 12823 */ MCD_OPC_Decode, 132, 19, 186, 2, // Opcode: NLOC_D +/* 12828 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 12843 +/* 12833 */ MCD_OPC_CheckPredicate, 30, 164, 16, 0, // Skip to: 17098 +/* 12838 */ MCD_OPC_Decode, 135, 19, 172, 2, // Opcode: NLZC_B +/* 12843 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 12858 +/* 12848 */ MCD_OPC_CheckPredicate, 30, 149, 16, 0, // Skip to: 17098 +/* 12853 */ MCD_OPC_Decode, 137, 19, 184, 2, // Opcode: NLZC_H +/* 12858 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 12873 +/* 12863 */ MCD_OPC_CheckPredicate, 30, 134, 16, 0, // Skip to: 17098 +/* 12868 */ MCD_OPC_Decode, 138, 19, 185, 2, // Opcode: NLZC_W +/* 12873 */ MCD_OPC_FilterValue, 15, 124, 16, 0, // Skip to: 17098 +/* 12878 */ MCD_OPC_CheckPredicate, 30, 119, 16, 0, // Skip to: 17098 +/* 12883 */ MCD_OPC_Decode, 136, 19, 186, 2, // Opcode: NLZC_D +/* 12888 */ MCD_OPC_FilterValue, 25, 109, 16, 0, // Skip to: 17098 +/* 12893 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 12896 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12911 +/* 12901 */ MCD_OPC_CheckPredicate, 30, 96, 16, 0, // Skip to: 17098 +/* 12906 */ MCD_OPC_Decode, 151, 13, 185, 2, // Opcode: FCLASS_W +/* 12911 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 12926 +/* 12916 */ MCD_OPC_CheckPredicate, 30, 81, 16, 0, // Skip to: 17098 +/* 12921 */ MCD_OPC_Decode, 150, 13, 186, 2, // Opcode: FCLASS_D +/* 12926 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 12941 +/* 12931 */ MCD_OPC_CheckPredicate, 30, 66, 16, 0, // Skip to: 17098 +/* 12936 */ MCD_OPC_Decode, 181, 14, 185, 2, // Opcode: FTRUNC_S_W +/* 12941 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 12956 +/* 12946 */ MCD_OPC_CheckPredicate, 30, 51, 16, 0, // Skip to: 17098 +/* 12951 */ MCD_OPC_Decode, 180, 14, 186, 2, // Opcode: FTRUNC_S_D +/* 12956 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 12971 +/* 12961 */ MCD_OPC_CheckPredicate, 30, 36, 16, 0, // Skip to: 17098 +/* 12966 */ MCD_OPC_Decode, 183, 14, 185, 2, // Opcode: FTRUNC_U_W +/* 12971 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 12986 +/* 12976 */ MCD_OPC_CheckPredicate, 30, 21, 16, 0, // Skip to: 17098 +/* 12981 */ MCD_OPC_Decode, 182, 14, 186, 2, // Opcode: FTRUNC_U_D +/* 12986 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 13001 +/* 12991 */ MCD_OPC_CheckPredicate, 30, 6, 16, 0, // Skip to: 17098 +/* 12996 */ MCD_OPC_Decode, 153, 14, 185, 2, // Opcode: FSQRT_W +/* 13001 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 13016 +/* 13006 */ MCD_OPC_CheckPredicate, 30, 247, 15, 0, // Skip to: 17098 +/* 13011 */ MCD_OPC_Decode, 146, 14, 186, 2, // Opcode: FSQRT_D +/* 13016 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 13031 +/* 13021 */ MCD_OPC_CheckPredicate, 30, 232, 15, 0, // Skip to: 17098 +/* 13026 */ MCD_OPC_Decode, 133, 14, 185, 2, // Opcode: FRSQRT_W +/* 13031 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 13046 +/* 13036 */ MCD_OPC_CheckPredicate, 30, 217, 15, 0, // Skip to: 17098 +/* 13041 */ MCD_OPC_Decode, 132, 14, 186, 2, // Opcode: FRSQRT_D +/* 13046 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 13061 +/* 13051 */ MCD_OPC_CheckPredicate, 30, 202, 15, 0, // Skip to: 17098 +/* 13056 */ MCD_OPC_Decode, 129, 14, 185, 2, // Opcode: FRCP_W +/* 13061 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 13076 +/* 13066 */ MCD_OPC_CheckPredicate, 30, 187, 15, 0, // Skip to: 17098 +/* 13071 */ MCD_OPC_Decode, 128, 14, 186, 2, // Opcode: FRCP_D +/* 13076 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 13091 +/* 13081 */ MCD_OPC_CheckPredicate, 30, 172, 15, 0, // Skip to: 17098 +/* 13086 */ MCD_OPC_Decode, 131, 14, 185, 2, // Opcode: FRINT_W +/* 13091 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 13106 +/* 13096 */ MCD_OPC_CheckPredicate, 30, 157, 15, 0, // Skip to: 17098 +/* 13101 */ MCD_OPC_Decode, 130, 14, 186, 2, // Opcode: FRINT_D +/* 13106 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 13121 +/* 13111 */ MCD_OPC_CheckPredicate, 30, 142, 15, 0, // Skip to: 17098 +/* 13116 */ MCD_OPC_Decode, 205, 13, 185, 2, // Opcode: FLOG2_W +/* 13121 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 13136 +/* 13126 */ MCD_OPC_CheckPredicate, 30, 127, 15, 0, // Skip to: 17098 +/* 13131 */ MCD_OPC_Decode, 204, 13, 186, 2, // Opcode: FLOG2_D +/* 13136 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 13151 +/* 13141 */ MCD_OPC_CheckPredicate, 30, 112, 15, 0, // Skip to: 17098 +/* 13146 */ MCD_OPC_Decode, 189, 13, 187, 2, // Opcode: FEXUPL_W +/* 13151 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 13166 +/* 13156 */ MCD_OPC_CheckPredicate, 30, 97, 15, 0, // Skip to: 17098 +/* 13161 */ MCD_OPC_Decode, 188, 13, 188, 2, // Opcode: FEXUPL_D +/* 13166 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 13181 +/* 13171 */ MCD_OPC_CheckPredicate, 30, 82, 15, 0, // Skip to: 17098 +/* 13176 */ MCD_OPC_Decode, 191, 13, 187, 2, // Opcode: FEXUPR_W +/* 13181 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 13196 +/* 13186 */ MCD_OPC_CheckPredicate, 30, 67, 15, 0, // Skip to: 17098 +/* 13191 */ MCD_OPC_Decode, 190, 13, 188, 2, // Opcode: FEXUPR_D +/* 13196 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 13211 +/* 13201 */ MCD_OPC_CheckPredicate, 30, 52, 15, 0, // Skip to: 17098 +/* 13206 */ MCD_OPC_Decode, 197, 13, 187, 2, // Opcode: FFQL_W +/* 13211 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 13226 +/* 13216 */ MCD_OPC_CheckPredicate, 30, 37, 15, 0, // Skip to: 17098 +/* 13221 */ MCD_OPC_Decode, 196, 13, 188, 2, // Opcode: FFQL_D +/* 13226 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 13241 +/* 13231 */ MCD_OPC_CheckPredicate, 30, 22, 15, 0, // Skip to: 17098 +/* 13236 */ MCD_OPC_Decode, 199, 13, 187, 2, // Opcode: FFQR_W +/* 13241 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 13256 +/* 13246 */ MCD_OPC_CheckPredicate, 30, 7, 15, 0, // Skip to: 17098 +/* 13251 */ MCD_OPC_Decode, 198, 13, 188, 2, // Opcode: FFQR_D +/* 13256 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 13271 +/* 13261 */ MCD_OPC_CheckPredicate, 30, 248, 14, 0, // Skip to: 17098 +/* 13266 */ MCD_OPC_Decode, 175, 14, 185, 2, // Opcode: FTINT_S_W +/* 13271 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 13286 +/* 13276 */ MCD_OPC_CheckPredicate, 30, 233, 14, 0, // Skip to: 17098 +/* 13281 */ MCD_OPC_Decode, 174, 14, 186, 2, // Opcode: FTINT_S_D +/* 13286 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 13301 +/* 13291 */ MCD_OPC_CheckPredicate, 30, 218, 14, 0, // Skip to: 17098 +/* 13296 */ MCD_OPC_Decode, 177, 14, 185, 2, // Opcode: FTINT_U_W +/* 13301 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 13316 +/* 13306 */ MCD_OPC_CheckPredicate, 30, 203, 14, 0, // Skip to: 17098 +/* 13311 */ MCD_OPC_Decode, 176, 14, 186, 2, // Opcode: FTINT_U_D +/* 13316 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 13331 +/* 13321 */ MCD_OPC_CheckPredicate, 30, 188, 14, 0, // Skip to: 17098 +/* 13326 */ MCD_OPC_Decode, 193, 13, 185, 2, // Opcode: FFINT_S_W +/* 13331 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 13346 +/* 13336 */ MCD_OPC_CheckPredicate, 30, 173, 14, 0, // Skip to: 17098 +/* 13341 */ MCD_OPC_Decode, 192, 13, 186, 2, // Opcode: FFINT_S_D +/* 13346 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 13361 +/* 13351 */ MCD_OPC_CheckPredicate, 30, 158, 14, 0, // Skip to: 17098 +/* 13356 */ MCD_OPC_Decode, 195, 13, 185, 2, // Opcode: FFINT_U_W +/* 13361 */ MCD_OPC_FilterValue, 31, 148, 14, 0, // Skip to: 17098 +/* 13366 */ MCD_OPC_CheckPredicate, 30, 143, 14, 0, // Skip to: 17098 +/* 13371 */ MCD_OPC_Decode, 194, 13, 186, 2, // Opcode: FFINT_U_D +/* 13376 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 13391 +/* 13381 */ MCD_OPC_CheckPredicate, 30, 128, 14, 0, // Skip to: 17098 +/* 13386 */ MCD_OPC_Decode, 198, 15, 189, 2, // Opcode: LD_B +/* 13391 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 13406 +/* 13396 */ MCD_OPC_CheckPredicate, 30, 113, 14, 0, // Skip to: 17098 +/* 13401 */ MCD_OPC_Decode, 200, 15, 189, 2, // Opcode: LD_H +/* 13406 */ MCD_OPC_FilterValue, 34, 10, 0, 0, // Skip to: 13421 +/* 13411 */ MCD_OPC_CheckPredicate, 30, 98, 14, 0, // Skip to: 17098 +/* 13416 */ MCD_OPC_Decode, 201, 15, 189, 2, // Opcode: LD_W +/* 13421 */ MCD_OPC_FilterValue, 35, 10, 0, 0, // Skip to: 13436 +/* 13426 */ MCD_OPC_CheckPredicate, 30, 83, 14, 0, // Skip to: 17098 +/* 13431 */ MCD_OPC_Decode, 199, 15, 189, 2, // Opcode: LD_D +/* 13436 */ MCD_OPC_FilterValue, 36, 10, 0, 0, // Skip to: 13451 +/* 13441 */ MCD_OPC_CheckPredicate, 30, 68, 14, 0, // Skip to: 17098 +/* 13446 */ MCD_OPC_Decode, 188, 22, 189, 2, // Opcode: ST_B +/* 13451 */ MCD_OPC_FilterValue, 37, 10, 0, 0, // Skip to: 13466 +/* 13456 */ MCD_OPC_CheckPredicate, 30, 53, 14, 0, // Skip to: 17098 +/* 13461 */ MCD_OPC_Decode, 190, 22, 189, 2, // Opcode: ST_H +/* 13466 */ MCD_OPC_FilterValue, 38, 10, 0, 0, // Skip to: 13481 +/* 13471 */ MCD_OPC_CheckPredicate, 30, 38, 14, 0, // Skip to: 17098 +/* 13476 */ MCD_OPC_Decode, 191, 22, 189, 2, // Opcode: ST_W +/* 13481 */ MCD_OPC_FilterValue, 39, 28, 14, 0, // Skip to: 17098 +/* 13486 */ MCD_OPC_CheckPredicate, 30, 23, 14, 0, // Skip to: 17098 +/* 13491 */ MCD_OPC_Decode, 189, 22, 189, 2, // Opcode: ST_D +/* 13496 */ MCD_OPC_FilterValue, 31, 165, 12, 0, // Skip to: 16738 +/* 13501 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 13504 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13519 +/* 13509 */ MCD_OPC_CheckPredicate, 28, 0, 14, 0, // Skip to: 17098 +/* 13514 */ MCD_OPC_Decode, 227, 12, 190, 2, // Opcode: EXT +/* 13519 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 13534 +/* 13524 */ MCD_OPC_CheckPredicate, 28, 241, 13, 0, // Skip to: 17098 +/* 13529 */ MCD_OPC_Decode, 220, 14, 191, 2, // Opcode: INS +/* 13534 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 13556 +/* 13539 */ MCD_OPC_CheckPredicate, 42, 226, 13, 0, // Skip to: 17098 +/* 13544 */ MCD_OPC_CheckField, 6, 5, 0, 219, 13, 0, // Skip to: 17098 +/* 13551 */ MCD_OPC_Decode, 254, 13, 192, 2, // Opcode: FORK +/* 13556 */ MCD_OPC_FilterValue, 9, 23, 0, 0, // Skip to: 13584 +/* 13561 */ MCD_OPC_CheckPredicate, 42, 204, 13, 0, // Skip to: 17098 +/* 13566 */ MCD_OPC_CheckField, 16, 5, 0, 197, 13, 0, // Skip to: 17098 +/* 13573 */ MCD_OPC_CheckField, 6, 5, 0, 190, 13, 0, // Skip to: 17098 +/* 13580 */ MCD_OPC_Decode, 188, 24, 25, // Opcode: YIELD +/* 13584 */ MCD_OPC_FilterValue, 10, 48, 0, 0, // Skip to: 13637 +/* 13589 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 13592 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13607 +/* 13597 */ MCD_OPC_CheckPredicate, 37, 168, 13, 0, // Skip to: 17098 +/* 13602 */ MCD_OPC_Decode, 171, 16, 193, 2, // Opcode: LWX +/* 13607 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 13622 +/* 13612 */ MCD_OPC_CheckPredicate, 37, 153, 13, 0, // Skip to: 17098 +/* 13617 */ MCD_OPC_Decode, 219, 15, 193, 2, // Opcode: LHX +/* 13622 */ MCD_OPC_FilterValue, 6, 143, 13, 0, // Skip to: 17098 +/* 13627 */ MCD_OPC_CheckPredicate, 37, 138, 13, 0, // Skip to: 17098 +/* 13632 */ MCD_OPC_Decode, 163, 15, 193, 2, // Opcode: LBUX +/* 13637 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 13659 +/* 13642 */ MCD_OPC_CheckPredicate, 37, 123, 13, 0, // Skip to: 17098 +/* 13647 */ MCD_OPC_CheckField, 6, 10, 0, 116, 13, 0, // Skip to: 17098 +/* 13654 */ MCD_OPC_Decode, 225, 14, 194, 2, // Opcode: INSV +/* 13659 */ MCD_OPC_FilterValue, 16, 109, 1, 0, // Skip to: 14029 +/* 13664 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 13667 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13682 +/* 13672 */ MCD_OPC_CheckPredicate, 37, 93, 13, 0, // Skip to: 17098 +/* 13677 */ MCD_OPC_Decode, 179, 6, 195, 2, // Opcode: ADDU_QB +/* 13682 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 13697 +/* 13687 */ MCD_OPC_CheckPredicate, 37, 78, 13, 0, // Skip to: 17098 +/* 13692 */ MCD_OPC_Decode, 232, 22, 195, 2, // Opcode: SUBU_QB +/* 13697 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 13712 +/* 13702 */ MCD_OPC_CheckPredicate, 37, 63, 13, 0, // Skip to: 17098 +/* 13707 */ MCD_OPC_Decode, 183, 6, 195, 2, // Opcode: ADDU_S_QB +/* 13712 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 13727 +/* 13717 */ MCD_OPC_CheckPredicate, 37, 48, 13, 0, // Skip to: 17098 +/* 13722 */ MCD_OPC_Decode, 236, 22, 195, 2, // Opcode: SUBU_S_QB +/* 13727 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 13742 +/* 13732 */ MCD_OPC_CheckPredicate, 37, 33, 13, 0, // Skip to: 17098 +/* 13737 */ MCD_OPC_Decode, 211, 18, 195, 2, // Opcode: MULEU_S_PH_QBL +/* 13742 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 13757 +/* 13747 */ MCD_OPC_CheckPredicate, 37, 18, 13, 0, // Skip to: 17098 +/* 13752 */ MCD_OPC_Decode, 213, 18, 195, 2, // Opcode: MULEU_S_PH_QBR +/* 13757 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 13772 +/* 13762 */ MCD_OPC_CheckPredicate, 69, 3, 13, 0, // Skip to: 17098 +/* 13767 */ MCD_OPC_Decode, 177, 6, 195, 2, // Opcode: ADDU_PH +/* 13772 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 13787 +/* 13777 */ MCD_OPC_CheckPredicate, 69, 244, 12, 0, // Skip to: 17098 +/* 13782 */ MCD_OPC_Decode, 230, 22, 195, 2, // Opcode: SUBU_PH +/* 13787 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 13802 +/* 13792 */ MCD_OPC_CheckPredicate, 37, 229, 12, 0, // Skip to: 17098 +/* 13797 */ MCD_OPC_Decode, 149, 6, 195, 2, // Opcode: ADDQ_PH +/* 13802 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 13817 +/* 13807 */ MCD_OPC_CheckPredicate, 37, 214, 12, 0, // Skip to: 17098 +/* 13812 */ MCD_OPC_Decode, 201, 22, 195, 2, // Opcode: SUBQ_PH +/* 13817 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 13832 +/* 13822 */ MCD_OPC_CheckPredicate, 69, 199, 12, 0, // Skip to: 17098 +/* 13827 */ MCD_OPC_Decode, 181, 6, 195, 2, // Opcode: ADDU_S_PH +/* 13832 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 13847 +/* 13837 */ MCD_OPC_CheckPredicate, 69, 184, 12, 0, // Skip to: 17098 +/* 13842 */ MCD_OPC_Decode, 234, 22, 195, 2, // Opcode: SUBU_S_PH +/* 13847 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 13862 +/* 13852 */ MCD_OPC_CheckPredicate, 37, 169, 12, 0, // Skip to: 17098 +/* 13857 */ MCD_OPC_Decode, 151, 6, 195, 2, // Opcode: ADDQ_S_PH +/* 13862 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 13877 +/* 13867 */ MCD_OPC_CheckPredicate, 37, 154, 12, 0, // Skip to: 17098 +/* 13872 */ MCD_OPC_Decode, 203, 22, 195, 2, // Opcode: SUBQ_S_PH +/* 13877 */ MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 13891 +/* 13882 */ MCD_OPC_CheckPredicate, 37, 139, 12, 0, // Skip to: 17098 +/* 13887 */ MCD_OPC_Decode, 156, 6, 61, // Opcode: ADDSC +/* 13891 */ MCD_OPC_FilterValue, 17, 9, 0, 0, // Skip to: 13905 +/* 13896 */ MCD_OPC_CheckPredicate, 37, 125, 12, 0, // Skip to: 17098 +/* 13901 */ MCD_OPC_Decode, 193, 6, 61, // Opcode: ADDWC +/* 13905 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 13919 +/* 13910 */ MCD_OPC_CheckPredicate, 37, 111, 12, 0, // Skip to: 17098 +/* 13915 */ MCD_OPC_Decode, 193, 17, 61, // Opcode: MODSUB +/* 13919 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 13941 +/* 13924 */ MCD_OPC_CheckPredicate, 37, 97, 12, 0, // Skip to: 17098 +/* 13929 */ MCD_OPC_CheckField, 16, 5, 0, 90, 12, 0, // Skip to: 17098 +/* 13936 */ MCD_OPC_Decode, 251, 19, 196, 2, // Opcode: RADDU_W_QB +/* 13941 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 13955 +/* 13946 */ MCD_OPC_CheckPredicate, 37, 75, 12, 0, // Skip to: 17098 +/* 13951 */ MCD_OPC_Decode, 153, 6, 61, // Opcode: ADDQ_S_W +/* 13955 */ MCD_OPC_FilterValue, 23, 9, 0, 0, // Skip to: 13969 +/* 13960 */ MCD_OPC_CheckPredicate, 37, 61, 12, 0, // Skip to: 17098 +/* 13965 */ MCD_OPC_Decode, 205, 22, 61, // Opcode: SUBQ_S_W +/* 13969 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 13984 +/* 13974 */ MCD_OPC_CheckPredicate, 37, 47, 12, 0, // Skip to: 17098 +/* 13979 */ MCD_OPC_Decode, 207, 18, 197, 2, // Opcode: MULEQ_S_W_PHL +/* 13984 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 13999 +/* 13989 */ MCD_OPC_CheckPredicate, 37, 32, 12, 0, // Skip to: 17098 +/* 13994 */ MCD_OPC_Decode, 209, 18, 197, 2, // Opcode: MULEQ_S_W_PHR +/* 13999 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 14014 +/* 14004 */ MCD_OPC_CheckPredicate, 69, 17, 12, 0, // Skip to: 17098 +/* 14009 */ MCD_OPC_Decode, 219, 18, 195, 2, // Opcode: MULQ_S_PH +/* 14014 */ MCD_OPC_FilterValue, 31, 7, 12, 0, // Skip to: 17098 +/* 14019 */ MCD_OPC_CheckPredicate, 37, 2, 12, 0, // Skip to: 17098 +/* 14024 */ MCD_OPC_Decode, 215, 18, 195, 2, // Opcode: MULQ_RS_PH +/* 14029 */ MCD_OPC_FilterValue, 17, 113, 1, 0, // Skip to: 14403 +/* 14034 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 14037 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 14058 +/* 14042 */ MCD_OPC_CheckPredicate, 37, 235, 11, 0, // Skip to: 17098 +/* 14047 */ MCD_OPC_CheckField, 11, 5, 0, 228, 11, 0, // Skip to: 17098 +/* 14054 */ MCD_OPC_Decode, 210, 9, 79, // Opcode: CMPU_EQ_QB +/* 14058 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 14079 +/* 14063 */ MCD_OPC_CheckPredicate, 37, 214, 11, 0, // Skip to: 17098 +/* 14068 */ MCD_OPC_CheckField, 11, 5, 0, 207, 11, 0, // Skip to: 17098 +/* 14075 */ MCD_OPC_Decode, 214, 9, 79, // Opcode: CMPU_LT_QB +/* 14079 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 14100 +/* 14084 */ MCD_OPC_CheckPredicate, 37, 193, 11, 0, // Skip to: 17098 +/* 14089 */ MCD_OPC_CheckField, 11, 5, 0, 186, 11, 0, // Skip to: 17098 +/* 14096 */ MCD_OPC_Decode, 212, 9, 79, // Opcode: CMPU_LE_QB +/* 14100 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 14115 +/* 14105 */ MCD_OPC_CheckPredicate, 37, 172, 11, 0, // Skip to: 17098 +/* 14110 */ MCD_OPC_Decode, 199, 19, 195, 2, // Opcode: PICK_QB +/* 14115 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 14130 +/* 14120 */ MCD_OPC_CheckPredicate, 37, 157, 11, 0, // Skip to: 17098 +/* 14125 */ MCD_OPC_Decode, 204, 9, 197, 2, // Opcode: CMPGU_EQ_QB +/* 14130 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 14145 +/* 14135 */ MCD_OPC_CheckPredicate, 37, 142, 11, 0, // Skip to: 17098 +/* 14140 */ MCD_OPC_Decode, 208, 9, 197, 2, // Opcode: CMPGU_LT_QB +/* 14145 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 14160 +/* 14150 */ MCD_OPC_CheckPredicate, 37, 127, 11, 0, // Skip to: 17098 +/* 14155 */ MCD_OPC_Decode, 206, 9, 197, 2, // Opcode: CMPGU_LE_QB +/* 14160 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 14181 +/* 14165 */ MCD_OPC_CheckPredicate, 37, 112, 11, 0, // Skip to: 17098 +/* 14170 */ MCD_OPC_CheckField, 11, 5, 0, 105, 11, 0, // Skip to: 17098 +/* 14177 */ MCD_OPC_Decode, 220, 9, 79, // Opcode: CMP_EQ_PH +/* 14181 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 14202 +/* 14186 */ MCD_OPC_CheckPredicate, 37, 91, 11, 0, // Skip to: 17098 +/* 14191 */ MCD_OPC_CheckField, 11, 5, 0, 84, 11, 0, // Skip to: 17098 +/* 14198 */ MCD_OPC_Decode, 234, 9, 79, // Opcode: CMP_LT_PH +/* 14202 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 14223 +/* 14207 */ MCD_OPC_CheckPredicate, 37, 70, 11, 0, // Skip to: 17098 +/* 14212 */ MCD_OPC_CheckField, 11, 5, 0, 63, 11, 0, // Skip to: 17098 +/* 14219 */ MCD_OPC_Decode, 228, 9, 79, // Opcode: CMP_LE_PH +/* 14223 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 14238 +/* 14228 */ MCD_OPC_CheckPredicate, 37, 49, 11, 0, // Skip to: 17098 +/* 14233 */ MCD_OPC_Decode, 197, 19, 195, 2, // Opcode: PICK_PH +/* 14238 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 14253 +/* 14243 */ MCD_OPC_CheckPredicate, 37, 34, 11, 0, // Skip to: 17098 +/* 14248 */ MCD_OPC_Decode, 228, 19, 195, 2, // Opcode: PRECRQ_QB_PH +/* 14253 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 14268 +/* 14258 */ MCD_OPC_CheckPredicate, 69, 19, 11, 0, // Skip to: 17098 +/* 14263 */ MCD_OPC_Decode, 232, 19, 195, 2, // Opcode: PRECR_QB_PH +/* 14268 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 14283 +/* 14273 */ MCD_OPC_CheckPredicate, 37, 4, 11, 0, // Skip to: 17098 +/* 14278 */ MCD_OPC_Decode, 179, 19, 195, 2, // Opcode: PACKRL_PH +/* 14283 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 14298 +/* 14288 */ MCD_OPC_CheckPredicate, 37, 245, 10, 0, // Skip to: 17098 +/* 14293 */ MCD_OPC_Decode, 224, 19, 195, 2, // Opcode: PRECRQU_S_QB_PH +/* 14298 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 14313 +/* 14303 */ MCD_OPC_CheckPredicate, 37, 230, 10, 0, // Skip to: 17098 +/* 14308 */ MCD_OPC_Decode, 226, 19, 198, 2, // Opcode: PRECRQ_PH_W +/* 14313 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 14328 +/* 14318 */ MCD_OPC_CheckPredicate, 37, 215, 10, 0, // Skip to: 17098 +/* 14323 */ MCD_OPC_Decode, 230, 19, 198, 2, // Opcode: PRECRQ_RS_PH_W +/* 14328 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 14343 +/* 14333 */ MCD_OPC_CheckPredicate, 69, 200, 10, 0, // Skip to: 17098 +/* 14338 */ MCD_OPC_Decode, 198, 9, 197, 2, // Opcode: CMPGDU_EQ_QB +/* 14343 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 14358 +/* 14348 */ MCD_OPC_CheckPredicate, 69, 185, 10, 0, // Skip to: 17098 +/* 14353 */ MCD_OPC_Decode, 202, 9, 197, 2, // Opcode: CMPGDU_LT_QB +/* 14358 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 14373 +/* 14363 */ MCD_OPC_CheckPredicate, 69, 170, 10, 0, // Skip to: 17098 +/* 14368 */ MCD_OPC_Decode, 200, 9, 197, 2, // Opcode: CMPGDU_LE_QB +/* 14373 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 14388 +/* 14378 */ MCD_OPC_CheckPredicate, 69, 155, 10, 0, // Skip to: 17098 +/* 14383 */ MCD_OPC_Decode, 234, 19, 199, 2, // Opcode: PRECR_SRA_PH_W +/* 14388 */ MCD_OPC_FilterValue, 31, 145, 10, 0, // Skip to: 17098 +/* 14393 */ MCD_OPC_CheckPredicate, 69, 140, 10, 0, // Skip to: 17098 +/* 14398 */ MCD_OPC_Decode, 236, 19, 199, 2, // Opcode: PRECR_SRA_R_PH_W +/* 14403 */ MCD_OPC_FilterValue, 18, 128, 1, 0, // Skip to: 14792 +/* 14408 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 14411 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 14433 +/* 14416 */ MCD_OPC_CheckPredicate, 69, 117, 10, 0, // Skip to: 17098 +/* 14421 */ MCD_OPC_CheckField, 21, 5, 0, 110, 10, 0, // Skip to: 17098 +/* 14428 */ MCD_OPC_Decode, 247, 5, 200, 2, // Opcode: ABSQ_S_QB +/* 14433 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 14448 +/* 14438 */ MCD_OPC_CheckPredicate, 37, 95, 10, 0, // Skip to: 17098 +/* 14443 */ MCD_OPC_Decode, 146, 20, 201, 2, // Opcode: REPL_QB +/* 14448 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 14470 +/* 14453 */ MCD_OPC_CheckPredicate, 37, 80, 10, 0, // Skip to: 17098 +/* 14458 */ MCD_OPC_CheckField, 21, 5, 0, 73, 10, 0, // Skip to: 17098 +/* 14465 */ MCD_OPC_Decode, 142, 20, 202, 2, // Opcode: REPLV_QB +/* 14470 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 14492 +/* 14475 */ MCD_OPC_CheckPredicate, 37, 58, 10, 0, // Skip to: 17098 +/* 14480 */ MCD_OPC_CheckField, 21, 5, 0, 51, 10, 0, // Skip to: 17098 +/* 14487 */ MCD_OPC_Decode, 204, 19, 200, 2, // Opcode: PRECEQU_PH_QBL +/* 14492 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 14514 +/* 14497 */ MCD_OPC_CheckPredicate, 37, 36, 10, 0, // Skip to: 17098 +/* 14502 */ MCD_OPC_CheckField, 21, 5, 0, 29, 10, 0, // Skip to: 17098 +/* 14509 */ MCD_OPC_Decode, 208, 19, 200, 2, // Opcode: PRECEQU_PH_QBR +/* 14514 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 14536 +/* 14519 */ MCD_OPC_CheckPredicate, 37, 14, 10, 0, // Skip to: 17098 +/* 14524 */ MCD_OPC_CheckField, 21, 5, 0, 7, 10, 0, // Skip to: 17098 +/* 14531 */ MCD_OPC_Decode, 205, 19, 200, 2, // Opcode: PRECEQU_PH_QBLA +/* 14536 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 14558 +/* 14541 */ MCD_OPC_CheckPredicate, 37, 248, 9, 0, // Skip to: 17098 +/* 14546 */ MCD_OPC_CheckField, 21, 5, 0, 241, 9, 0, // Skip to: 17098 +/* 14553 */ MCD_OPC_Decode, 209, 19, 200, 2, // Opcode: PRECEQU_PH_QBRA +/* 14558 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 14580 +/* 14563 */ MCD_OPC_CheckPredicate, 37, 226, 9, 0, // Skip to: 17098 +/* 14568 */ MCD_OPC_CheckField, 21, 5, 0, 219, 9, 0, // Skip to: 17098 +/* 14575 */ MCD_OPC_Decode, 245, 5, 200, 2, // Opcode: ABSQ_S_PH +/* 14580 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 14594 +/* 14585 */ MCD_OPC_CheckPredicate, 37, 204, 9, 0, // Skip to: 17098 +/* 14590 */ MCD_OPC_Decode, 144, 20, 96, // Opcode: REPL_PH +/* 14594 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 14616 +/* 14599 */ MCD_OPC_CheckPredicate, 37, 190, 9, 0, // Skip to: 17098 +/* 14604 */ MCD_OPC_CheckField, 21, 5, 0, 183, 9, 0, // Skip to: 17098 +/* 14611 */ MCD_OPC_Decode, 140, 20, 202, 2, // Opcode: REPLV_PH +/* 14616 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 14638 +/* 14621 */ MCD_OPC_CheckPredicate, 37, 168, 9, 0, // Skip to: 17098 +/* 14626 */ MCD_OPC_CheckField, 21, 5, 0, 161, 9, 0, // Skip to: 17098 +/* 14633 */ MCD_OPC_Decode, 212, 19, 203, 2, // Opcode: PRECEQ_W_PHL +/* 14638 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 14660 +/* 14643 */ MCD_OPC_CheckPredicate, 37, 146, 9, 0, // Skip to: 17098 +/* 14648 */ MCD_OPC_CheckField, 21, 5, 0, 139, 9, 0, // Skip to: 17098 +/* 14655 */ MCD_OPC_Decode, 214, 19, 203, 2, // Opcode: PRECEQ_W_PHR +/* 14660 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 14682 +/* 14665 */ MCD_OPC_CheckPredicate, 37, 124, 9, 0, // Skip to: 17098 +/* 14670 */ MCD_OPC_CheckField, 21, 5, 0, 117, 9, 0, // Skip to: 17098 +/* 14677 */ MCD_OPC_Decode, 249, 5, 204, 2, // Opcode: ABSQ_S_W +/* 14682 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 14704 +/* 14687 */ MCD_OPC_CheckPredicate, 37, 102, 9, 0, // Skip to: 17098 +/* 14692 */ MCD_OPC_CheckField, 21, 5, 0, 95, 9, 0, // Skip to: 17098 +/* 14699 */ MCD_OPC_Decode, 129, 8, 204, 2, // Opcode: BITREV +/* 14704 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 14726 +/* 14709 */ MCD_OPC_CheckPredicate, 37, 80, 9, 0, // Skip to: 17098 +/* 14714 */ MCD_OPC_CheckField, 21, 5, 0, 73, 9, 0, // Skip to: 17098 +/* 14721 */ MCD_OPC_Decode, 216, 19, 200, 2, // Opcode: PRECEU_PH_QBL +/* 14726 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 14748 +/* 14731 */ MCD_OPC_CheckPredicate, 37, 58, 9, 0, // Skip to: 17098 +/* 14736 */ MCD_OPC_CheckField, 21, 5, 0, 51, 9, 0, // Skip to: 17098 +/* 14743 */ MCD_OPC_Decode, 220, 19, 200, 2, // Opcode: PRECEU_PH_QBR +/* 14748 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 14770 +/* 14753 */ MCD_OPC_CheckPredicate, 37, 36, 9, 0, // Skip to: 17098 +/* 14758 */ MCD_OPC_CheckField, 21, 5, 0, 29, 9, 0, // Skip to: 17098 +/* 14765 */ MCD_OPC_Decode, 217, 19, 200, 2, // Opcode: PRECEU_PH_QBLA +/* 14770 */ MCD_OPC_FilterValue, 31, 19, 9, 0, // Skip to: 17098 +/* 14775 */ MCD_OPC_CheckPredicate, 37, 14, 9, 0, // Skip to: 17098 +/* 14780 */ MCD_OPC_CheckField, 21, 5, 0, 7, 9, 0, // Skip to: 17098 +/* 14787 */ MCD_OPC_Decode, 221, 19, 200, 2, // Opcode: PRECEU_PH_QBRA +/* 14792 */ MCD_OPC_FilterValue, 19, 75, 1, 0, // Skip to: 15128 +/* 14797 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 14800 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14815 +/* 14805 */ MCD_OPC_CheckPredicate, 37, 240, 8, 0, // Skip to: 17098 +/* 14810 */ MCD_OPC_Decode, 168, 21, 205, 2, // Opcode: SHLL_QB +/* 14815 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 14830 +/* 14820 */ MCD_OPC_CheckPredicate, 37, 225, 8, 0, // Skip to: 17098 +/* 14825 */ MCD_OPC_Decode, 200, 21, 205, 2, // Opcode: SHRL_QB +/* 14830 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 14845 +/* 14835 */ MCD_OPC_CheckPredicate, 37, 210, 8, 0, // Skip to: 17098 +/* 14840 */ MCD_OPC_Decode, 160, 21, 206, 2, // Opcode: SHLLV_QB +/* 14845 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 14860 +/* 14850 */ MCD_OPC_CheckPredicate, 37, 195, 8, 0, // Skip to: 17098 +/* 14855 */ MCD_OPC_Decode, 196, 21, 206, 2, // Opcode: SHRLV_QB +/* 14860 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 14875 +/* 14865 */ MCD_OPC_CheckPredicate, 69, 180, 8, 0, // Skip to: 17098 +/* 14870 */ MCD_OPC_Decode, 186, 21, 205, 2, // Opcode: SHRA_QB +/* 14875 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 14890 +/* 14880 */ MCD_OPC_CheckPredicate, 69, 165, 8, 0, // Skip to: 17098 +/* 14885 */ MCD_OPC_Decode, 190, 21, 205, 2, // Opcode: SHRA_R_QB +/* 14890 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 14905 +/* 14895 */ MCD_OPC_CheckPredicate, 69, 150, 8, 0, // Skip to: 17098 +/* 14900 */ MCD_OPC_Decode, 176, 21, 206, 2, // Opcode: SHRAV_QB +/* 14905 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 14920 +/* 14910 */ MCD_OPC_CheckPredicate, 69, 135, 8, 0, // Skip to: 17098 +/* 14915 */ MCD_OPC_Decode, 180, 21, 206, 2, // Opcode: SHRAV_R_QB +/* 14920 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 14935 +/* 14925 */ MCD_OPC_CheckPredicate, 37, 120, 8, 0, // Skip to: 17098 +/* 14930 */ MCD_OPC_Decode, 166, 21, 205, 2, // Opcode: SHLL_PH +/* 14935 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 14950 +/* 14940 */ MCD_OPC_CheckPredicate, 37, 105, 8, 0, // Skip to: 17098 +/* 14945 */ MCD_OPC_Decode, 184, 21, 205, 2, // Opcode: SHRA_PH +/* 14950 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 14965 +/* 14955 */ MCD_OPC_CheckPredicate, 37, 90, 8, 0, // Skip to: 17098 +/* 14960 */ MCD_OPC_Decode, 158, 21, 206, 2, // Opcode: SHLLV_PH +/* 14965 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 14980 +/* 14970 */ MCD_OPC_CheckPredicate, 37, 75, 8, 0, // Skip to: 17098 +/* 14975 */ MCD_OPC_Decode, 174, 21, 206, 2, // Opcode: SHRAV_PH +/* 14980 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 14995 +/* 14985 */ MCD_OPC_CheckPredicate, 37, 60, 8, 0, // Skip to: 17098 +/* 14990 */ MCD_OPC_Decode, 170, 21, 205, 2, // Opcode: SHLL_S_PH +/* 14995 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 15010 +/* 15000 */ MCD_OPC_CheckPredicate, 37, 45, 8, 0, // Skip to: 17098 +/* 15005 */ MCD_OPC_Decode, 188, 21, 205, 2, // Opcode: SHRA_R_PH +/* 15010 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 15025 +/* 15015 */ MCD_OPC_CheckPredicate, 37, 30, 8, 0, // Skip to: 17098 +/* 15020 */ MCD_OPC_Decode, 162, 21, 206, 2, // Opcode: SHLLV_S_PH +/* 15025 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 15040 +/* 15030 */ MCD_OPC_CheckPredicate, 37, 15, 8, 0, // Skip to: 17098 +/* 15035 */ MCD_OPC_Decode, 178, 21, 206, 2, // Opcode: SHRAV_R_PH +/* 15040 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 15055 +/* 15045 */ MCD_OPC_CheckPredicate, 37, 0, 8, 0, // Skip to: 17098 +/* 15050 */ MCD_OPC_Decode, 172, 21, 207, 2, // Opcode: SHLL_S_W +/* 15055 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 15070 +/* 15060 */ MCD_OPC_CheckPredicate, 37, 241, 7, 0, // Skip to: 17098 +/* 15065 */ MCD_OPC_Decode, 192, 21, 207, 2, // Opcode: SHRA_R_W +/* 15070 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 15084 +/* 15075 */ MCD_OPC_CheckPredicate, 37, 226, 7, 0, // Skip to: 17098 +/* 15080 */ MCD_OPC_Decode, 164, 21, 55, // Opcode: SHLLV_S_W +/* 15084 */ MCD_OPC_FilterValue, 23, 9, 0, 0, // Skip to: 15098 +/* 15089 */ MCD_OPC_CheckPredicate, 37, 212, 7, 0, // Skip to: 17098 +/* 15094 */ MCD_OPC_Decode, 182, 21, 55, // Opcode: SHRAV_R_W +/* 15098 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 15113 +/* 15103 */ MCD_OPC_CheckPredicate, 69, 198, 7, 0, // Skip to: 17098 +/* 15108 */ MCD_OPC_Decode, 198, 21, 205, 2, // Opcode: SHRL_PH +/* 15113 */ MCD_OPC_FilterValue, 27, 188, 7, 0, // Skip to: 17098 +/* 15118 */ MCD_OPC_CheckPredicate, 69, 183, 7, 0, // Skip to: 17098 +/* 15123 */ MCD_OPC_Decode, 194, 21, 206, 2, // Opcode: SHRLV_PH +/* 15128 */ MCD_OPC_FilterValue, 24, 237, 0, 0, // Skip to: 15370 +/* 15133 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 15136 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 15151 +/* 15141 */ MCD_OPC_CheckPredicate, 69, 160, 7, 0, // Skip to: 17098 +/* 15146 */ MCD_OPC_Decode, 172, 6, 195, 2, // Opcode: ADDUH_QB +/* 15151 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 15166 +/* 15156 */ MCD_OPC_CheckPredicate, 69, 145, 7, 0, // Skip to: 17098 +/* 15161 */ MCD_OPC_Decode, 225, 22, 195, 2, // Opcode: SUBUH_QB +/* 15166 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 15181 +/* 15171 */ MCD_OPC_CheckPredicate, 69, 130, 7, 0, // Skip to: 17098 +/* 15176 */ MCD_OPC_Decode, 174, 6, 195, 2, // Opcode: ADDUH_R_QB +/* 15181 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 15196 +/* 15186 */ MCD_OPC_CheckPredicate, 69, 115, 7, 0, // Skip to: 17098 +/* 15191 */ MCD_OPC_Decode, 227, 22, 195, 2, // Opcode: SUBUH_R_QB +/* 15196 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 15211 +/* 15201 */ MCD_OPC_CheckPredicate, 69, 100, 7, 0, // Skip to: 17098 +/* 15206 */ MCD_OPC_Decode, 141, 6, 195, 2, // Opcode: ADDQH_PH +/* 15211 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 15226 +/* 15216 */ MCD_OPC_CheckPredicate, 69, 85, 7, 0, // Skip to: 17098 +/* 15221 */ MCD_OPC_Decode, 193, 22, 195, 2, // Opcode: SUBQH_PH +/* 15226 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 15241 +/* 15231 */ MCD_OPC_CheckPredicate, 69, 70, 7, 0, // Skip to: 17098 +/* 15236 */ MCD_OPC_Decode, 143, 6, 195, 2, // Opcode: ADDQH_R_PH +/* 15241 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 15256 +/* 15246 */ MCD_OPC_CheckPredicate, 69, 55, 7, 0, // Skip to: 17098 +/* 15251 */ MCD_OPC_Decode, 195, 22, 195, 2, // Opcode: SUBQH_R_PH +/* 15256 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 15271 +/* 15261 */ MCD_OPC_CheckPredicate, 69, 40, 7, 0, // Skip to: 17098 +/* 15266 */ MCD_OPC_Decode, 248, 18, 195, 2, // Opcode: MUL_PH +/* 15271 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 15286 +/* 15276 */ MCD_OPC_CheckPredicate, 69, 25, 7, 0, // Skip to: 17098 +/* 15281 */ MCD_OPC_Decode, 253, 18, 195, 2, // Opcode: MUL_S_PH +/* 15286 */ MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 15300 +/* 15291 */ MCD_OPC_CheckPredicate, 69, 10, 7, 0, // Skip to: 17098 +/* 15296 */ MCD_OPC_Decode, 147, 6, 61, // Opcode: ADDQH_W +/* 15300 */ MCD_OPC_FilterValue, 17, 9, 0, 0, // Skip to: 15314 +/* 15305 */ MCD_OPC_CheckPredicate, 69, 252, 6, 0, // Skip to: 17098 +/* 15310 */ MCD_OPC_Decode, 199, 22, 61, // Opcode: SUBQH_W +/* 15314 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 15328 +/* 15319 */ MCD_OPC_CheckPredicate, 69, 238, 6, 0, // Skip to: 17098 +/* 15324 */ MCD_OPC_Decode, 145, 6, 61, // Opcode: ADDQH_R_W +/* 15328 */ MCD_OPC_FilterValue, 19, 9, 0, 0, // Skip to: 15342 +/* 15333 */ MCD_OPC_CheckPredicate, 69, 224, 6, 0, // Skip to: 17098 +/* 15338 */ MCD_OPC_Decode, 197, 22, 61, // Opcode: SUBQH_R_W +/* 15342 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 15356 +/* 15347 */ MCD_OPC_CheckPredicate, 69, 210, 6, 0, // Skip to: 17098 +/* 15352 */ MCD_OPC_Decode, 221, 18, 61, // Opcode: MULQ_S_W +/* 15356 */ MCD_OPC_FilterValue, 23, 201, 6, 0, // Skip to: 17098 +/* 15361 */ MCD_OPC_CheckPredicate, 69, 196, 6, 0, // Skip to: 17098 +/* 15366 */ MCD_OPC_Decode, 217, 18, 61, // Opcode: MULQ_RS_W +/* 15370 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 15392 +/* 15375 */ MCD_OPC_CheckPredicate, 70, 182, 6, 0, // Skip to: 17098 +/* 15380 */ MCD_OPC_CheckField, 6, 1, 0, 175, 6, 0, // Skip to: 17098 +/* 15387 */ MCD_OPC_Decode, 151, 16, 208, 2, // Opcode: LWLE +/* 15392 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 15414 +/* 15397 */ MCD_OPC_CheckPredicate, 70, 160, 6, 0, // Skip to: 17098 +/* 15402 */ MCD_OPC_CheckField, 6, 1, 0, 153, 6, 0, // Skip to: 17098 +/* 15409 */ MCD_OPC_Decode, 164, 16, 208, 2, // Opcode: LWRE +/* 15414 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 15436 +/* 15419 */ MCD_OPC_CheckPredicate, 44, 138, 6, 0, // Skip to: 17098 +/* 15424 */ MCD_OPC_CheckField, 6, 1, 0, 131, 6, 0, // Skip to: 17098 +/* 15431 */ MCD_OPC_Decode, 247, 8, 209, 2, // Opcode: CACHEE +/* 15436 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 15458 +/* 15441 */ MCD_OPC_CheckPredicate, 44, 116, 6, 0, // Skip to: 17098 +/* 15446 */ MCD_OPC_CheckField, 6, 1, 0, 109, 6, 0, // Skip to: 17098 +/* 15453 */ MCD_OPC_Decode, 198, 20, 208, 2, // Opcode: SBE +/* 15458 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 15480 +/* 15463 */ MCD_OPC_CheckPredicate, 44, 94, 6, 0, // Skip to: 17098 +/* 15468 */ MCD_OPC_CheckField, 6, 1, 0, 87, 6, 0, // Skip to: 17098 +/* 15475 */ MCD_OPC_Decode, 148, 21, 208, 2, // Opcode: SHE +/* 15480 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 15502 +/* 15485 */ MCD_OPC_CheckPredicate, 44, 72, 6, 0, // Skip to: 17098 +/* 15490 */ MCD_OPC_CheckField, 6, 1, 0, 65, 6, 0, // Skip to: 17098 +/* 15497 */ MCD_OPC_Decode, 211, 20, 208, 2, // Opcode: SCE +/* 15502 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 15524 +/* 15507 */ MCD_OPC_CheckPredicate, 44, 50, 6, 0, // Skip to: 17098 +/* 15512 */ MCD_OPC_CheckField, 6, 1, 0, 43, 6, 0, // Skip to: 17098 +/* 15519 */ MCD_OPC_Decode, 142, 23, 208, 2, // Opcode: SWE +/* 15524 */ MCD_OPC_FilterValue, 32, 69, 0, 0, // Skip to: 15598 +/* 15529 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 15532 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 15554 +/* 15537 */ MCD_OPC_CheckPredicate, 28, 20, 6, 0, // Skip to: 17098 +/* 15542 */ MCD_OPC_CheckField, 21, 5, 0, 13, 6, 0, // Skip to: 17098 +/* 15549 */ MCD_OPC_Decode, 169, 24, 204, 2, // Opcode: WSBH +/* 15554 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 15576 +/* 15559 */ MCD_OPC_CheckPredicate, 28, 254, 5, 0, // Skip to: 17098 +/* 15564 */ MCD_OPC_CheckField, 21, 5, 0, 247, 5, 0, // Skip to: 17098 +/* 15571 */ MCD_OPC_Decode, 242, 20, 204, 2, // Opcode: SEB +/* 15576 */ MCD_OPC_FilterValue, 24, 237, 5, 0, // Skip to: 17098 +/* 15581 */ MCD_OPC_CheckPredicate, 28, 232, 5, 0, // Skip to: 17098 +/* 15586 */ MCD_OPC_CheckField, 21, 5, 0, 225, 5, 0, // Skip to: 17098 +/* 15593 */ MCD_OPC_Decode, 246, 20, 204, 2, // Opcode: SEH +/* 15598 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 15620 +/* 15603 */ MCD_OPC_CheckPredicate, 70, 210, 5, 0, // Skip to: 17098 +/* 15608 */ MCD_OPC_CheckField, 6, 1, 0, 203, 5, 0, // Skip to: 17098 +/* 15615 */ MCD_OPC_Decode, 148, 23, 208, 2, // Opcode: SWLE +/* 15620 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 15642 +/* 15625 */ MCD_OPC_CheckPredicate, 70, 188, 5, 0, // Skip to: 17098 +/* 15630 */ MCD_OPC_CheckField, 6, 1, 0, 181, 5, 0, // Skip to: 17098 +/* 15637 */ MCD_OPC_Decode, 159, 23, 208, 2, // Opcode: SWRE +/* 15642 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 15664 +/* 15647 */ MCD_OPC_CheckPredicate, 44, 166, 5, 0, // Skip to: 17098 +/* 15652 */ MCD_OPC_CheckField, 6, 1, 0, 159, 5, 0, // Skip to: 17098 +/* 15659 */ MCD_OPC_Decode, 239, 19, 209, 2, // Opcode: PREFE +/* 15664 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 15686 +/* 15669 */ MCD_OPC_CheckPredicate, 44, 144, 5, 0, // Skip to: 17098 +/* 15674 */ MCD_OPC_CheckField, 6, 1, 0, 137, 5, 0, // Skip to: 17098 +/* 15681 */ MCD_OPC_Decode, 176, 15, 208, 2, // Opcode: LBuE +/* 15686 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 15708 +/* 15691 */ MCD_OPC_CheckPredicate, 44, 122, 5, 0, // Skip to: 17098 +/* 15696 */ MCD_OPC_CheckField, 6, 1, 0, 115, 5, 0, // Skip to: 17098 +/* 15703 */ MCD_OPC_Decode, 228, 15, 208, 2, // Opcode: LHuE +/* 15708 */ MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 15730 +/* 15713 */ MCD_OPC_CheckPredicate, 44, 100, 5, 0, // Skip to: 17098 +/* 15718 */ MCD_OPC_CheckField, 6, 1, 0, 93, 5, 0, // Skip to: 17098 +/* 15725 */ MCD_OPC_Decode, 157, 15, 208, 2, // Opcode: LBE +/* 15730 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 15752 +/* 15735 */ MCD_OPC_CheckPredicate, 44, 78, 5, 0, // Skip to: 17098 +/* 15740 */ MCD_OPC_CheckField, 6, 1, 0, 71, 5, 0, // Skip to: 17098 +/* 15747 */ MCD_OPC_Decode, 209, 15, 208, 2, // Opcode: LHE +/* 15752 */ MCD_OPC_FilterValue, 46, 17, 0, 0, // Skip to: 15774 +/* 15757 */ MCD_OPC_CheckPredicate, 44, 56, 5, 0, // Skip to: 17098 +/* 15762 */ MCD_OPC_CheckField, 6, 1, 0, 49, 5, 0, // Skip to: 17098 +/* 15769 */ MCD_OPC_Decode, 240, 15, 208, 2, // Opcode: LLE +/* 15774 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 15796 +/* 15779 */ MCD_OPC_CheckPredicate, 44, 34, 5, 0, // Skip to: 17098 +/* 15784 */ MCD_OPC_CheckField, 6, 1, 0, 27, 5, 0, // Skip to: 17098 +/* 15791 */ MCD_OPC_Decode, 144, 16, 208, 2, // Opcode: LWE +/* 15796 */ MCD_OPC_FilterValue, 48, 231, 1, 0, // Skip to: 16288 +/* 15801 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 15804 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 15826 +/* 15809 */ MCD_OPC_CheckPredicate, 69, 4, 5, 0, // Skip to: 17098 +/* 15814 */ MCD_OPC_CheckField, 13, 3, 0, 253, 4, 0, // Skip to: 17098 +/* 15821 */ MCD_OPC_Decode, 156, 12, 243, 1, // Opcode: DPA_W_PH +/* 15826 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 15848 +/* 15831 */ MCD_OPC_CheckPredicate, 69, 238, 4, 0, // Skip to: 17098 +/* 15836 */ MCD_OPC_CheckField, 13, 3, 0, 231, 4, 0, // Skip to: 17098 +/* 15843 */ MCD_OPC_Decode, 179, 12, 243, 1, // Opcode: DPS_W_PH +/* 15848 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 15870 +/* 15853 */ MCD_OPC_CheckPredicate, 69, 216, 4, 0, // Skip to: 17098 +/* 15858 */ MCD_OPC_CheckField, 13, 3, 0, 209, 4, 0, // Skip to: 17098 +/* 15865 */ MCD_OPC_Decode, 228, 18, 243, 1, // Opcode: MULSA_W_PH +/* 15870 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 15892 +/* 15875 */ MCD_OPC_CheckPredicate, 37, 194, 4, 0, // Skip to: 17098 +/* 15880 */ MCD_OPC_CheckField, 13, 3, 0, 187, 4, 0, // Skip to: 17098 +/* 15887 */ MCD_OPC_Decode, 150, 12, 243, 1, // Opcode: DPAU_H_QBL +/* 15892 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 15914 +/* 15897 */ MCD_OPC_CheckPredicate, 37, 172, 4, 0, // Skip to: 17098 +/* 15902 */ MCD_OPC_CheckField, 13, 3, 0, 165, 4, 0, // Skip to: 17098 +/* 15909 */ MCD_OPC_Decode, 148, 12, 243, 1, // Opcode: DPAQ_S_W_PH +/* 15914 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 15936 +/* 15919 */ MCD_OPC_CheckPredicate, 37, 150, 4, 0, // Skip to: 17098 +/* 15924 */ MCD_OPC_CheckField, 13, 3, 0, 143, 4, 0, // Skip to: 17098 +/* 15931 */ MCD_OPC_Decode, 165, 12, 243, 1, // Opcode: DPSQ_S_W_PH +/* 15936 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 15958 +/* 15941 */ MCD_OPC_CheckPredicate, 37, 128, 4, 0, // Skip to: 17098 +/* 15946 */ MCD_OPC_CheckField, 13, 3, 0, 121, 4, 0, // Skip to: 17098 +/* 15953 */ MCD_OPC_Decode, 226, 18, 243, 1, // Opcode: MULSAQ_S_W_PH +/* 15958 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 15980 +/* 15963 */ MCD_OPC_CheckPredicate, 37, 106, 4, 0, // Skip to: 17098 +/* 15968 */ MCD_OPC_CheckField, 13, 3, 0, 99, 4, 0, // Skip to: 17098 +/* 15975 */ MCD_OPC_Decode, 152, 12, 243, 1, // Opcode: DPAU_H_QBR +/* 15980 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 16002 +/* 15985 */ MCD_OPC_CheckPredicate, 69, 84, 4, 0, // Skip to: 17098 +/* 15990 */ MCD_OPC_CheckField, 13, 3, 0, 77, 4, 0, // Skip to: 17098 +/* 15997 */ MCD_OPC_Decode, 154, 12, 243, 1, // Opcode: DPAX_W_PH +/* 16002 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 16024 +/* 16007 */ MCD_OPC_CheckPredicate, 69, 62, 4, 0, // Skip to: 17098 +/* 16012 */ MCD_OPC_CheckField, 13, 3, 0, 55, 4, 0, // Skip to: 17098 +/* 16019 */ MCD_OPC_Decode, 177, 12, 243, 1, // Opcode: DPSX_W_PH +/* 16024 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 16046 +/* 16029 */ MCD_OPC_CheckPredicate, 37, 40, 4, 0, // Skip to: 17098 +/* 16034 */ MCD_OPC_CheckField, 13, 3, 0, 33, 4, 0, // Skip to: 17098 +/* 16041 */ MCD_OPC_Decode, 173, 12, 243, 1, // Opcode: DPSU_H_QBL +/* 16046 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 16068 +/* 16051 */ MCD_OPC_CheckPredicate, 37, 18, 4, 0, // Skip to: 17098 +/* 16056 */ MCD_OPC_CheckField, 13, 3, 0, 11, 4, 0, // Skip to: 17098 +/* 16063 */ MCD_OPC_Decode, 146, 12, 243, 1, // Opcode: DPAQ_SA_L_W +/* 16068 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 16090 +/* 16073 */ MCD_OPC_CheckPredicate, 37, 252, 3, 0, // Skip to: 17098 +/* 16078 */ MCD_OPC_CheckField, 13, 3, 0, 245, 3, 0, // Skip to: 17098 +/* 16085 */ MCD_OPC_Decode, 163, 12, 243, 1, // Opcode: DPSQ_SA_L_W +/* 16090 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 16112 +/* 16095 */ MCD_OPC_CheckPredicate, 37, 230, 3, 0, // Skip to: 17098 +/* 16100 */ MCD_OPC_CheckField, 13, 3, 0, 223, 3, 0, // Skip to: 17098 +/* 16107 */ MCD_OPC_Decode, 175, 12, 243, 1, // Opcode: DPSU_H_QBR +/* 16112 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 16134 +/* 16117 */ MCD_OPC_CheckPredicate, 37, 208, 3, 0, // Skip to: 17098 +/* 16122 */ MCD_OPC_CheckField, 13, 3, 0, 201, 3, 0, // Skip to: 17098 +/* 16129 */ MCD_OPC_Decode, 220, 16, 243, 1, // Opcode: MAQ_SA_W_PHL +/* 16134 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 16156 +/* 16139 */ MCD_OPC_CheckPredicate, 37, 186, 3, 0, // Skip to: 17098 +/* 16144 */ MCD_OPC_CheckField, 13, 3, 0, 179, 3, 0, // Skip to: 17098 +/* 16151 */ MCD_OPC_Decode, 222, 16, 243, 1, // Opcode: MAQ_SA_W_PHR +/* 16156 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 16178 +/* 16161 */ MCD_OPC_CheckPredicate, 37, 164, 3, 0, // Skip to: 17098 +/* 16166 */ MCD_OPC_CheckField, 13, 3, 0, 157, 3, 0, // Skip to: 17098 +/* 16173 */ MCD_OPC_Decode, 224, 16, 243, 1, // Opcode: MAQ_S_W_PHL +/* 16178 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 16200 +/* 16183 */ MCD_OPC_CheckPredicate, 37, 142, 3, 0, // Skip to: 17098 +/* 16188 */ MCD_OPC_CheckField, 13, 3, 0, 135, 3, 0, // Skip to: 17098 +/* 16195 */ MCD_OPC_Decode, 226, 16, 243, 1, // Opcode: MAQ_S_W_PHR +/* 16200 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 16222 +/* 16205 */ MCD_OPC_CheckPredicate, 69, 120, 3, 0, // Skip to: 17098 +/* 16210 */ MCD_OPC_CheckField, 13, 3, 0, 113, 3, 0, // Skip to: 17098 +/* 16217 */ MCD_OPC_Decode, 144, 12, 243, 1, // Opcode: DPAQX_S_W_PH +/* 16222 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 16244 +/* 16227 */ MCD_OPC_CheckPredicate, 69, 98, 3, 0, // Skip to: 17098 +/* 16232 */ MCD_OPC_CheckField, 13, 3, 0, 91, 3, 0, // Skip to: 17098 +/* 16239 */ MCD_OPC_Decode, 161, 12, 243, 1, // Opcode: DPSQX_S_W_PH +/* 16244 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 16266 +/* 16249 */ MCD_OPC_CheckPredicate, 69, 76, 3, 0, // Skip to: 17098 +/* 16254 */ MCD_OPC_CheckField, 13, 3, 0, 69, 3, 0, // Skip to: 17098 +/* 16261 */ MCD_OPC_Decode, 142, 12, 243, 1, // Opcode: DPAQX_SA_W_PH +/* 16266 */ MCD_OPC_FilterValue, 27, 59, 3, 0, // Skip to: 17098 +/* 16271 */ MCD_OPC_CheckPredicate, 69, 54, 3, 0, // Skip to: 17098 +/* 16276 */ MCD_OPC_CheckField, 13, 3, 0, 47, 3, 0, // Skip to: 17098 +/* 16283 */ MCD_OPC_Decode, 159, 12, 243, 1, // Opcode: DPSQX_SA_W_PH +/* 16288 */ MCD_OPC_FilterValue, 49, 48, 0, 0, // Skip to: 16341 +/* 16293 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 16296 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16311 +/* 16301 */ MCD_OPC_CheckPredicate, 69, 24, 3, 0, // Skip to: 17098 +/* 16306 */ MCD_OPC_Decode, 234, 6, 210, 2, // Opcode: APPEND +/* 16311 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 16326 +/* 16316 */ MCD_OPC_CheckPredicate, 69, 9, 3, 0, // Skip to: 17098 +/* 16321 */ MCD_OPC_Decode, 247, 19, 210, 2, // Opcode: PREPEND +/* 16326 */ MCD_OPC_FilterValue, 16, 255, 2, 0, // Skip to: 17098 +/* 16331 */ MCD_OPC_CheckPredicate, 69, 250, 2, 0, // Skip to: 17098 +/* 16336 */ MCD_OPC_Decode, 152, 7, 210, 2, // Opcode: BALIGN +/* 16341 */ MCD_OPC_FilterValue, 56, 107, 1, 0, // Skip to: 16709 +/* 16346 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 16349 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16371 +/* 16354 */ MCD_OPC_CheckPredicate, 37, 227, 2, 0, // Skip to: 17098 +/* 16359 */ MCD_OPC_CheckField, 13, 3, 0, 220, 2, 0, // Skip to: 17098 +/* 16366 */ MCD_OPC_Decode, 250, 12, 211, 2, // Opcode: EXTR_W +/* 16371 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 16393 +/* 16376 */ MCD_OPC_CheckPredicate, 37, 205, 2, 0, // Skip to: 17098 +/* 16381 */ MCD_OPC_CheckField, 13, 3, 0, 198, 2, 0, // Skip to: 17098 +/* 16388 */ MCD_OPC_Decode, 242, 12, 212, 2, // Opcode: EXTRV_W +/* 16393 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 16415 +/* 16398 */ MCD_OPC_CheckPredicate, 37, 183, 2, 0, // Skip to: 17098 +/* 16403 */ MCD_OPC_CheckField, 13, 3, 0, 176, 2, 0, // Skip to: 17098 +/* 16410 */ MCD_OPC_Decode, 228, 12, 211, 2, // Opcode: EXTP +/* 16415 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 16437 +/* 16420 */ MCD_OPC_CheckPredicate, 37, 161, 2, 0, // Skip to: 17098 +/* 16425 */ MCD_OPC_CheckField, 13, 3, 0, 154, 2, 0, // Skip to: 17098 +/* 16432 */ MCD_OPC_Decode, 233, 12, 212, 2, // Opcode: EXTPV +/* 16437 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 16459 +/* 16442 */ MCD_OPC_CheckPredicate, 37, 139, 2, 0, // Skip to: 17098 +/* 16447 */ MCD_OPC_CheckField, 13, 3, 0, 132, 2, 0, // Skip to: 17098 +/* 16454 */ MCD_OPC_Decode, 246, 12, 211, 2, // Opcode: EXTR_R_W +/* 16459 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 16481 +/* 16464 */ MCD_OPC_CheckPredicate, 37, 117, 2, 0, // Skip to: 17098 +/* 16469 */ MCD_OPC_CheckField, 13, 3, 0, 110, 2, 0, // Skip to: 17098 +/* 16476 */ MCD_OPC_Decode, 238, 12, 212, 2, // Opcode: EXTRV_R_W +/* 16481 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 16503 +/* 16486 */ MCD_OPC_CheckPredicate, 37, 95, 2, 0, // Skip to: 17098 +/* 16491 */ MCD_OPC_CheckField, 13, 3, 0, 88, 2, 0, // Skip to: 17098 +/* 16498 */ MCD_OPC_Decode, 244, 12, 211, 2, // Opcode: EXTR_RS_W +/* 16503 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 16525 +/* 16508 */ MCD_OPC_CheckPredicate, 37, 73, 2, 0, // Skip to: 17098 +/* 16513 */ MCD_OPC_CheckField, 13, 3, 0, 66, 2, 0, // Skip to: 17098 +/* 16520 */ MCD_OPC_Decode, 236, 12, 212, 2, // Opcode: EXTRV_RS_W +/* 16525 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 16547 +/* 16530 */ MCD_OPC_CheckPredicate, 37, 51, 2, 0, // Skip to: 17098 +/* 16535 */ MCD_OPC_CheckField, 13, 3, 0, 44, 2, 0, // Skip to: 17098 +/* 16542 */ MCD_OPC_Decode, 229, 12, 211, 2, // Opcode: EXTPDP +/* 16547 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 16569 +/* 16552 */ MCD_OPC_CheckPredicate, 37, 29, 2, 0, // Skip to: 17098 +/* 16557 */ MCD_OPC_CheckField, 13, 3, 0, 22, 2, 0, // Skip to: 17098 +/* 16564 */ MCD_OPC_Decode, 230, 12, 212, 2, // Opcode: EXTPDPV +/* 16569 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 16591 +/* 16574 */ MCD_OPC_CheckPredicate, 37, 7, 2, 0, // Skip to: 17098 +/* 16579 */ MCD_OPC_CheckField, 13, 3, 0, 0, 2, 0, // Skip to: 17098 +/* 16586 */ MCD_OPC_Decode, 248, 12, 211, 2, // Opcode: EXTR_S_H +/* 16591 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 16613 +/* 16596 */ MCD_OPC_CheckPredicate, 37, 241, 1, 0, // Skip to: 17098 +/* 16601 */ MCD_OPC_CheckField, 13, 3, 0, 234, 1, 0, // Skip to: 17098 +/* 16608 */ MCD_OPC_Decode, 240, 12, 212, 2, // Opcode: EXTRV_S_H +/* 16613 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 16628 +/* 16618 */ MCD_OPC_CheckPredicate, 37, 219, 1, 0, // Skip to: 17098 +/* 16623 */ MCD_OPC_Decode, 253, 19, 213, 2, // Opcode: RDDSP +/* 16628 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 16643 +/* 16633 */ MCD_OPC_CheckPredicate, 40, 204, 1, 0, // Skip to: 17098 +/* 16638 */ MCD_OPC_Decode, 165, 24, 214, 2, // Opcode: WRDSP +/* 16643 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 16665 +/* 16648 */ MCD_OPC_CheckPredicate, 37, 189, 1, 0, // Skip to: 17098 +/* 16653 */ MCD_OPC_CheckField, 13, 7, 0, 182, 1, 0, // Skip to: 17098 +/* 16660 */ MCD_OPC_Decode, 154, 21, 215, 2, // Opcode: SHILO +/* 16665 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 16687 +/* 16670 */ MCD_OPC_CheckPredicate, 37, 167, 1, 0, // Skip to: 17098 +/* 16675 */ MCD_OPC_CheckField, 13, 8, 0, 160, 1, 0, // Skip to: 17098 +/* 16682 */ MCD_OPC_Decode, 155, 21, 216, 2, // Opcode: SHILOV +/* 16687 */ MCD_OPC_FilterValue, 31, 150, 1, 0, // Skip to: 17098 +/* 16692 */ MCD_OPC_CheckPredicate, 37, 145, 1, 0, // Skip to: 17098 +/* 16697 */ MCD_OPC_CheckField, 13, 8, 0, 138, 1, 0, // Skip to: 17098 +/* 16704 */ MCD_OPC_Decode, 184, 18, 216, 2, // Opcode: MTHLIP +/* 16709 */ MCD_OPC_FilterValue, 59, 128, 1, 0, // Skip to: 17098 +/* 16714 */ MCD_OPC_CheckPredicate, 27, 123, 1, 0, // Skip to: 17098 +/* 16719 */ MCD_OPC_CheckField, 21, 5, 0, 116, 1, 0, // Skip to: 17098 +/* 16726 */ MCD_OPC_CheckField, 9, 2, 0, 109, 1, 0, // Skip to: 17098 +/* 16733 */ MCD_OPC_Decode, 255, 19, 217, 2, // Opcode: RDHWR +/* 16738 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 16753 +/* 16743 */ MCD_OPC_CheckPredicate, 27, 94, 1, 0, // Skip to: 17098 +/* 16748 */ MCD_OPC_Decode, 154, 15, 141, 1, // Opcode: LB +/* 16753 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 16768 +/* 16758 */ MCD_OPC_CheckPredicate, 27, 79, 1, 0, // Skip to: 17098 +/* 16763 */ MCD_OPC_Decode, 206, 15, 141, 1, // Opcode: LH +/* 16768 */ MCD_OPC_FilterValue, 34, 10, 0, 0, // Skip to: 16783 +/* 16773 */ MCD_OPC_CheckPredicate, 31, 64, 1, 0, // Skip to: 17098 +/* 16778 */ MCD_OPC_Decode, 149, 16, 141, 1, // Opcode: LWL +/* 16783 */ MCD_OPC_FilterValue, 35, 10, 0, 0, // Skip to: 16798 +/* 16788 */ MCD_OPC_CheckPredicate, 27, 49, 1, 0, // Skip to: 17098 +/* 16793 */ MCD_OPC_Decode, 131, 16, 141, 1, // Opcode: LW +/* 16798 */ MCD_OPC_FilterValue, 36, 10, 0, 0, // Skip to: 16813 +/* 16803 */ MCD_OPC_CheckPredicate, 27, 34, 1, 0, // Skip to: 17098 +/* 16808 */ MCD_OPC_Decode, 174, 15, 141, 1, // Opcode: LBu +/* 16813 */ MCD_OPC_FilterValue, 37, 10, 0, 0, // Skip to: 16828 +/* 16818 */ MCD_OPC_CheckPredicate, 27, 19, 1, 0, // Skip to: 17098 +/* 16823 */ MCD_OPC_Decode, 226, 15, 141, 1, // Opcode: LHu +/* 16828 */ MCD_OPC_FilterValue, 38, 10, 0, 0, // Skip to: 16843 +/* 16833 */ MCD_OPC_CheckPredicate, 31, 4, 1, 0, // Skip to: 17098 +/* 16838 */ MCD_OPC_Decode, 162, 16, 141, 1, // Opcode: LWR +/* 16843 */ MCD_OPC_FilterValue, 40, 10, 0, 0, // Skip to: 16858 +/* 16848 */ MCD_OPC_CheckPredicate, 27, 245, 0, 0, // Skip to: 17098 +/* 16853 */ MCD_OPC_Decode, 193, 20, 141, 1, // Opcode: SB +/* 16858 */ MCD_OPC_FilterValue, 41, 10, 0, 0, // Skip to: 16873 +/* 16863 */ MCD_OPC_CheckPredicate, 27, 230, 0, 0, // Skip to: 17098 +/* 16868 */ MCD_OPC_Decode, 143, 21, 141, 1, // Opcode: SH +/* 16873 */ MCD_OPC_FilterValue, 42, 10, 0, 0, // Skip to: 16888 +/* 16878 */ MCD_OPC_CheckPredicate, 31, 215, 0, 0, // Skip to: 17098 +/* 16883 */ MCD_OPC_Decode, 146, 23, 141, 1, // Opcode: SWL +/* 16888 */ MCD_OPC_FilterValue, 43, 10, 0, 0, // Skip to: 16903 +/* 16893 */ MCD_OPC_CheckPredicate, 27, 200, 0, 0, // Skip to: 17098 +/* 16898 */ MCD_OPC_Decode, 128, 23, 141, 1, // Opcode: SW +/* 16903 */ MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 16918 +/* 16908 */ MCD_OPC_CheckPredicate, 31, 185, 0, 0, // Skip to: 17098 +/* 16913 */ MCD_OPC_Decode, 157, 23, 141, 1, // Opcode: SWR +/* 16918 */ MCD_OPC_FilterValue, 47, 10, 0, 0, // Skip to: 16933 +/* 16923 */ MCD_OPC_CheckPredicate, 71, 170, 0, 0, // Skip to: 17098 +/* 16928 */ MCD_OPC_Decode, 246, 8, 218, 2, // Opcode: CACHE +/* 16933 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 16948 +/* 16938 */ MCD_OPC_CheckPredicate, 72, 155, 0, 0, // Skip to: 17098 +/* 16943 */ MCD_OPC_Decode, 235, 15, 141, 1, // Opcode: LL +/* 16948 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 16963 +/* 16953 */ MCD_OPC_CheckPredicate, 47, 140, 0, 0, // Skip to: 17098 +/* 16958 */ MCD_OPC_Decode, 136, 16, 219, 2, // Opcode: LWC1 +/* 16963 */ MCD_OPC_FilterValue, 50, 10, 0, 0, // Skip to: 16978 +/* 16968 */ MCD_OPC_CheckPredicate, 31, 125, 0, 0, // Skip to: 17098 +/* 16973 */ MCD_OPC_Decode, 138, 16, 220, 2, // Opcode: LWC2 +/* 16978 */ MCD_OPC_FilterValue, 51, 10, 0, 0, // Skip to: 16993 +/* 16983 */ MCD_OPC_CheckPredicate, 71, 110, 0, 0, // Skip to: 17098 +/* 16988 */ MCD_OPC_Decode, 238, 19, 218, 2, // Opcode: PREF +/* 16993 */ MCD_OPC_FilterValue, 53, 10, 0, 0, // Skip to: 17008 +/* 16998 */ MCD_OPC_CheckPredicate, 57, 95, 0, 0, // Skip to: 17098 +/* 17003 */ MCD_OPC_Decode, 180, 15, 219, 2, // Opcode: LDC1 +/* 17008 */ MCD_OPC_FilterValue, 54, 10, 0, 0, // Skip to: 17023 +/* 17013 */ MCD_OPC_CheckPredicate, 39, 80, 0, 0, // Skip to: 17098 +/* 17018 */ MCD_OPC_Decode, 185, 15, 220, 2, // Opcode: LDC2 +/* 17023 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 17038 +/* 17028 */ MCD_OPC_CheckPredicate, 72, 65, 0, 0, // Skip to: 17098 +/* 17033 */ MCD_OPC_Decode, 206, 20, 141, 1, // Opcode: SC +/* 17038 */ MCD_OPC_FilterValue, 57, 10, 0, 0, // Skip to: 17053 +/* 17043 */ MCD_OPC_CheckPredicate, 47, 50, 0, 0, // Skip to: 17098 +/* 17048 */ MCD_OPC_Decode, 134, 23, 219, 2, // Opcode: SWC1 +/* 17053 */ MCD_OPC_FilterValue, 58, 10, 0, 0, // Skip to: 17068 +/* 17058 */ MCD_OPC_CheckPredicate, 31, 35, 0, 0, // Skip to: 17098 +/* 17063 */ MCD_OPC_Decode, 136, 23, 220, 2, // Opcode: SWC2 +/* 17068 */ MCD_OPC_FilterValue, 61, 10, 0, 0, // Skip to: 17083 +/* 17073 */ MCD_OPC_CheckPredicate, 57, 20, 0, 0, // Skip to: 17098 +/* 17078 */ MCD_OPC_Decode, 227, 20, 219, 2, // Opcode: SDC1 +/* 17083 */ MCD_OPC_FilterValue, 62, 10, 0, 0, // Skip to: 17098 +/* 17088 */ MCD_OPC_CheckPredicate, 39, 5, 0, 0, // Skip to: 17098 +/* 17093 */ MCD_OPC_Decode, 232, 20, 220, 2, // Opcode: SDC2 +/* 17098 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMips32_64_PTR6432[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 24 +/* 8 */ MCD_OPC_CheckPredicate, 73, 41, 0, 0, // Skip to: 54 +/* 13 */ MCD_OPC_CheckField, 0, 21, 8, 34, 0, 0, // Skip to: 54 +/* 20 */ MCD_OPC_Decode, 134, 15, 24, // Opcode: JR64 +/* 24 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 39 +/* 29 */ MCD_OPC_CheckPredicate, 74, 20, 0, 0, // Skip to: 54 +/* 34 */ MCD_OPC_Decode, 236, 15, 141, 1, // Opcode: LL64 +/* 39 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 54 +/* 44 */ MCD_OPC_CheckPredicate, 74, 5, 0, 0, // Skip to: 54 +/* 49 */ MCD_OPC_Decode, 207, 20, 141, 1, // Opcode: SC64 +/* 54 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableMips32r6_64r632[] = { /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 0, 205, 1, // Skip to: 468 -/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 10 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 29 -/* 14 */ MCD_OPC_CheckPredicate, 36, 37, 7, // Skip to: 1847 -/* 18 */ MCD_OPC_CheckField, 8, 3, 0, 31, 7, // Skip to: 1847 -/* 24 */ MCD_OPC_Decode, 206, 7, 221, 1, // Opcode: LSA_R6 -/* 29 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 47 -/* 33 */ MCD_OPC_CheckPredicate, 36, 18, 7, // Skip to: 1847 -/* 37 */ MCD_OPC_CheckField, 6, 15, 16, 12, 7, // Skip to: 1847 -/* 43 */ MCD_OPC_Decode, 142, 7, 61, // Opcode: JR_HB_R6 -/* 47 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 59 -/* 51 */ MCD_OPC_CheckPredicate, 36, 0, 7, // Skip to: 1847 -/* 55 */ MCD_OPC_Decode, 155, 11, 64, // Opcode: SDBBP_R6 -/* 59 */ MCD_OPC_FilterValue, 16, 20, 0, // Skip to: 83 -/* 63 */ MCD_OPC_CheckPredicate, 36, 244, 6, // Skip to: 1847 -/* 67 */ MCD_OPC_CheckField, 16, 5, 0, 238, 6, // Skip to: 1847 -/* 73 */ MCD_OPC_CheckField, 6, 5, 1, 232, 6, // Skip to: 1847 -/* 79 */ MCD_OPC_Decode, 154, 3, 62, // Opcode: CLZ_R6 -/* 83 */ MCD_OPC_FilterValue, 17, 20, 0, // Skip to: 107 -/* 87 */ MCD_OPC_CheckPredicate, 36, 220, 6, // Skip to: 1847 -/* 91 */ MCD_OPC_CheckField, 16, 5, 0, 214, 6, // Skip to: 1847 -/* 97 */ MCD_OPC_CheckField, 6, 5, 1, 208, 6, // Skip to: 1847 -/* 103 */ MCD_OPC_Decode, 135, 3, 62, // Opcode: CLO_R6 -/* 107 */ MCD_OPC_FilterValue, 18, 21, 0, // Skip to: 132 -/* 111 */ MCD_OPC_CheckPredicate, 37, 196, 6, // Skip to: 1847 -/* 115 */ MCD_OPC_CheckField, 16, 5, 0, 190, 6, // Skip to: 1847 -/* 121 */ MCD_OPC_CheckField, 6, 5, 1, 184, 6, // Skip to: 1847 -/* 127 */ MCD_OPC_Decode, 171, 4, 222, 1, // Opcode: DCLZ_R6 -/* 132 */ MCD_OPC_FilterValue, 19, 21, 0, // Skip to: 157 -/* 136 */ MCD_OPC_CheckPredicate, 37, 171, 6, // Skip to: 1847 -/* 140 */ MCD_OPC_CheckField, 16, 5, 0, 165, 6, // Skip to: 1847 -/* 146 */ MCD_OPC_CheckField, 6, 5, 1, 159, 6, // Skip to: 1847 -/* 152 */ MCD_OPC_Decode, 169, 4, 222, 1, // Opcode: DCLO_R6 -/* 157 */ MCD_OPC_FilterValue, 21, 15, 0, // Skip to: 176 -/* 161 */ MCD_OPC_CheckPredicate, 37, 146, 6, // Skip to: 1847 -/* 165 */ MCD_OPC_CheckField, 8, 3, 0, 140, 6, // Skip to: 1847 -/* 171 */ MCD_OPC_Decode, 195, 4, 223, 1, // Opcode: DLSA_R6 -/* 176 */ MCD_OPC_FilterValue, 24, 27, 0, // Skip to: 207 -/* 180 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 183 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 195 -/* 187 */ MCD_OPC_CheckPredicate, 36, 120, 6, // Skip to: 1847 -/* 191 */ MCD_OPC_Decode, 221, 9, 35, // Opcode: MUL_R6 -/* 195 */ MCD_OPC_FilterValue, 3, 112, 6, // Skip to: 1847 -/* 199 */ MCD_OPC_CheckPredicate, 36, 108, 6, // Skip to: 1847 -/* 203 */ MCD_OPC_Decode, 191, 9, 35, // Opcode: MUH -/* 207 */ MCD_OPC_FilterValue, 25, 27, 0, // Skip to: 238 -/* 211 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 214 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 226 -/* 218 */ MCD_OPC_CheckPredicate, 36, 89, 6, // Skip to: 1847 -/* 222 */ MCD_OPC_Decode, 212, 9, 35, // Opcode: MULU -/* 226 */ MCD_OPC_FilterValue, 3, 81, 6, // Skip to: 1847 -/* 230 */ MCD_OPC_CheckPredicate, 36, 77, 6, // Skip to: 1847 -/* 234 */ MCD_OPC_Decode, 192, 9, 35, // Opcode: MUHU -/* 238 */ MCD_OPC_FilterValue, 26, 27, 0, // Skip to: 269 -/* 242 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 245 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 257 -/* 249 */ MCD_OPC_CheckPredicate, 36, 58, 6, // Skip to: 1847 -/* 253 */ MCD_OPC_Decode, 183, 4, 35, // Opcode: DIV -/* 257 */ MCD_OPC_FilterValue, 3, 50, 6, // Skip to: 1847 -/* 261 */ MCD_OPC_CheckPredicate, 36, 46, 6, // Skip to: 1847 -/* 265 */ MCD_OPC_Decode, 222, 8, 35, // Opcode: MOD -/* 269 */ MCD_OPC_FilterValue, 27, 27, 0, // Skip to: 300 -/* 273 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 276 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 288 -/* 280 */ MCD_OPC_CheckPredicate, 36, 27, 6, // Skip to: 1847 -/* 284 */ MCD_OPC_Decode, 184, 4, 35, // Opcode: DIVU -/* 288 */ MCD_OPC_FilterValue, 3, 19, 6, // Skip to: 1847 -/* 292 */ MCD_OPC_CheckPredicate, 36, 15, 6, // Skip to: 1847 -/* 296 */ MCD_OPC_Decode, 224, 8, 35, // Opcode: MODU -/* 300 */ MCD_OPC_FilterValue, 28, 29, 0, // Skip to: 333 -/* 304 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 307 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 320 -/* 311 */ MCD_OPC_CheckPredicate, 37, 252, 5, // Skip to: 1847 -/* 315 */ MCD_OPC_Decode, 210, 4, 224, 1, // Opcode: DMUL_R6 -/* 320 */ MCD_OPC_FilterValue, 3, 243, 5, // Skip to: 1847 -/* 324 */ MCD_OPC_CheckPredicate, 37, 239, 5, // Skip to: 1847 -/* 328 */ MCD_OPC_Decode, 204, 4, 224, 1, // Opcode: DMUH -/* 333 */ MCD_OPC_FilterValue, 29, 29, 0, // Skip to: 366 -/* 337 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 340 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 353 -/* 344 */ MCD_OPC_CheckPredicate, 37, 219, 5, // Skip to: 1847 -/* 348 */ MCD_OPC_Decode, 209, 4, 224, 1, // Opcode: DMULU -/* 353 */ MCD_OPC_FilterValue, 3, 210, 5, // Skip to: 1847 -/* 357 */ MCD_OPC_CheckPredicate, 37, 206, 5, // Skip to: 1847 -/* 361 */ MCD_OPC_Decode, 205, 4, 224, 1, // Opcode: DMUHU -/* 366 */ MCD_OPC_FilterValue, 30, 29, 0, // Skip to: 399 -/* 370 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 373 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 386 -/* 377 */ MCD_OPC_CheckPredicate, 37, 186, 5, // Skip to: 1847 -/* 381 */ MCD_OPC_Decode, 172, 4, 224, 1, // Opcode: DDIV -/* 386 */ MCD_OPC_FilterValue, 3, 177, 5, // Skip to: 1847 -/* 390 */ MCD_OPC_CheckPredicate, 37, 173, 5, // Skip to: 1847 -/* 394 */ MCD_OPC_Decode, 199, 4, 224, 1, // Opcode: DMOD -/* 399 */ MCD_OPC_FilterValue, 31, 29, 0, // Skip to: 432 -/* 403 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 406 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 419 -/* 410 */ MCD_OPC_CheckPredicate, 37, 153, 5, // Skip to: 1847 -/* 414 */ MCD_OPC_Decode, 173, 4, 224, 1, // Opcode: DDIVU -/* 419 */ MCD_OPC_FilterValue, 3, 144, 5, // Skip to: 1847 -/* 423 */ MCD_OPC_CheckPredicate, 37, 140, 5, // Skip to: 1847 -/* 427 */ MCD_OPC_Decode, 200, 4, 224, 1, // Opcode: DMODU -/* 432 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 450 -/* 436 */ MCD_OPC_CheckPredicate, 38, 127, 5, // Skip to: 1847 -/* 440 */ MCD_OPC_CheckField, 6, 5, 0, 121, 5, // Skip to: 1847 -/* 446 */ MCD_OPC_Decode, 174, 11, 35, // Opcode: SELEQZ -/* 450 */ MCD_OPC_FilterValue, 55, 113, 5, // Skip to: 1847 -/* 454 */ MCD_OPC_CheckPredicate, 38, 109, 5, // Skip to: 1847 -/* 458 */ MCD_OPC_CheckField, 6, 5, 0, 103, 5, // Skip to: 1847 -/* 464 */ MCD_OPC_Decode, 178, 11, 35, // Opcode: SELNEZ -/* 468 */ MCD_OPC_FilterValue, 1, 47, 0, // Skip to: 519 -/* 472 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 475 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 488 -/* 479 */ MCD_OPC_CheckPredicate, 37, 84, 5, // Skip to: 1847 -/* 483 */ MCD_OPC_Decode, 163, 4, 225, 1, // Opcode: DAHI -/* 488 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 506 -/* 492 */ MCD_OPC_CheckPredicate, 36, 71, 5, // Skip to: 1847 -/* 496 */ MCD_OPC_CheckField, 21, 5, 0, 65, 5, // Skip to: 1847 -/* 502 */ MCD_OPC_Decode, 167, 1, 75, // Opcode: BAL -/* 506 */ MCD_OPC_FilterValue, 30, 57, 5, // Skip to: 1847 -/* 510 */ MCD_OPC_CheckPredicate, 37, 53, 5, // Skip to: 1847 -/* 514 */ MCD_OPC_Decode, 165, 4, 225, 1, // Opcode: DATI -/* 519 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 532 -/* 523 */ MCD_OPC_CheckPredicate, 36, 40, 5, // Skip to: 1847 -/* 527 */ MCD_OPC_Decode, 220, 1, 226, 1, // Opcode: BGEZALC -/* 532 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 545 -/* 536 */ MCD_OPC_CheckPredicate, 36, 27, 5, // Skip to: 1847 -/* 540 */ MCD_OPC_Decode, 134, 2, 227, 1, // Opcode: BLTZALC -/* 545 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 558 -/* 549 */ MCD_OPC_CheckPredicate, 36, 14, 5, // Skip to: 1847 -/* 553 */ MCD_OPC_Decode, 208, 1, 228, 1, // Opcode: BEQC -/* 558 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 570 -/* 562 */ MCD_OPC_CheckPredicate, 36, 1, 5, // Skip to: 1847 -/* 566 */ MCD_OPC_Decode, 137, 1, 47, // Opcode: AUI -/* 570 */ MCD_OPC_FilterValue, 17, 5, 3, // Skip to: 1347 -/* 574 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 577 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 590 -/* 581 */ MCD_OPC_CheckPredicate, 36, 238, 4, // Skip to: 1847 -/* 585 */ MCD_OPC_Decode, 180, 1, 229, 1, // Opcode: BC1EQZ -/* 590 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 603 -/* 594 */ MCD_OPC_CheckPredicate, 36, 225, 4, // Skip to: 1847 -/* 598 */ MCD_OPC_Decode, 184, 1, 229, 1, // Opcode: BC1NEZ -/* 603 */ MCD_OPC_FilterValue, 16, 150, 0, // Skip to: 757 -/* 607 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 610 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 623 -/* 614 */ MCD_OPC_CheckPredicate, 36, 205, 4, // Skip to: 1847 -/* 618 */ MCD_OPC_Decode, 183, 11, 230, 1, // Opcode: SEL_S -/* 623 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 635 -/* 627 */ MCD_OPC_CheckPredicate, 36, 192, 4, // Skip to: 1847 -/* 631 */ MCD_OPC_Decode, 177, 11, 93, // Opcode: SELEQZ_S -/* 635 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 647 -/* 639 */ MCD_OPC_CheckPredicate, 36, 180, 4, // Skip to: 1847 -/* 643 */ MCD_OPC_Decode, 181, 11, 93, // Opcode: SELNEZ_S -/* 647 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 660 -/* 651 */ MCD_OPC_CheckPredicate, 36, 168, 4, // Skip to: 1847 -/* 655 */ MCD_OPC_Decode, 132, 8, 231, 1, // Opcode: MADDF_S -/* 660 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 673 -/* 664 */ MCD_OPC_CheckPredicate, 36, 155, 4, // Skip to: 1847 -/* 668 */ MCD_OPC_Decode, 150, 9, 231, 1, // Opcode: MSUBF_S -/* 673 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 691 -/* 677 */ MCD_OPC_CheckPredicate, 36, 142, 4, // Skip to: 1847 -/* 681 */ MCD_OPC_CheckField, 16, 5, 0, 136, 4, // Skip to: 1847 -/* 687 */ MCD_OPC_Decode, 246, 10, 94, // Opcode: RINT_S -/* 691 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 709 -/* 695 */ MCD_OPC_CheckPredicate, 36, 124, 4, // Skip to: 1847 -/* 699 */ MCD_OPC_CheckField, 16, 5, 0, 118, 4, // Skip to: 1847 -/* 705 */ MCD_OPC_Decode, 244, 2, 94, // Opcode: CLASS_S -/* 709 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 721 -/* 713 */ MCD_OPC_CheckPredicate, 36, 106, 4, // Skip to: 1847 -/* 717 */ MCD_OPC_Decode, 211, 8, 93, // Opcode: MIN_S -/* 721 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 733 -/* 725 */ MCD_OPC_CheckPredicate, 36, 94, 4, // Skip to: 1847 -/* 729 */ MCD_OPC_Decode, 170, 8, 93, // Opcode: MAX_S -/* 733 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 745 -/* 737 */ MCD_OPC_CheckPredicate, 36, 82, 4, // Skip to: 1847 -/* 741 */ MCD_OPC_Decode, 197, 8, 93, // Opcode: MINA_S -/* 745 */ MCD_OPC_FilterValue, 31, 74, 4, // Skip to: 1847 -/* 749 */ MCD_OPC_CheckPredicate, 36, 70, 4, // Skip to: 1847 -/* 753 */ MCD_OPC_Decode, 156, 8, 93, // Opcode: MAXA_S -/* 757 */ MCD_OPC_FilterValue, 17, 156, 0, // Skip to: 917 -/* 761 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 764 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 777 -/* 768 */ MCD_OPC_CheckPredicate, 36, 51, 4, // Skip to: 1847 -/* 772 */ MCD_OPC_Decode, 182, 11, 232, 1, // Opcode: SEL_D -/* 777 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 790 -/* 781 */ MCD_OPC_CheckPredicate, 36, 38, 4, // Skip to: 1847 -/* 785 */ MCD_OPC_Decode, 176, 11, 233, 1, // Opcode: SELEQZ_D -/* 790 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 803 -/* 794 */ MCD_OPC_CheckPredicate, 36, 25, 4, // Skip to: 1847 -/* 798 */ MCD_OPC_Decode, 180, 11, 233, 1, // Opcode: SELNEZ_D -/* 803 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 816 -/* 807 */ MCD_OPC_CheckPredicate, 36, 12, 4, // Skip to: 1847 -/* 811 */ MCD_OPC_Decode, 131, 8, 234, 1, // Opcode: MADDF_D -/* 816 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 829 -/* 820 */ MCD_OPC_CheckPredicate, 36, 255, 3, // Skip to: 1847 -/* 824 */ MCD_OPC_Decode, 149, 9, 234, 1, // Opcode: MSUBF_D -/* 829 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 847 -/* 833 */ MCD_OPC_CheckPredicate, 36, 242, 3, // Skip to: 1847 -/* 837 */ MCD_OPC_CheckField, 16, 5, 0, 236, 3, // Skip to: 1847 -/* 843 */ MCD_OPC_Decode, 245, 10, 105, // Opcode: RINT_D -/* 847 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 865 -/* 851 */ MCD_OPC_CheckPredicate, 36, 224, 3, // Skip to: 1847 -/* 855 */ MCD_OPC_CheckField, 16, 5, 0, 218, 3, // Skip to: 1847 -/* 861 */ MCD_OPC_Decode, 243, 2, 105, // Opcode: CLASS_D -/* 865 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 878 -/* 869 */ MCD_OPC_CheckPredicate, 36, 206, 3, // Skip to: 1847 -/* 873 */ MCD_OPC_Decode, 210, 8, 233, 1, // Opcode: MIN_D -/* 878 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 891 -/* 882 */ MCD_OPC_CheckPredicate, 36, 193, 3, // Skip to: 1847 -/* 886 */ MCD_OPC_Decode, 169, 8, 233, 1, // Opcode: MAX_D -/* 891 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 904 -/* 895 */ MCD_OPC_CheckPredicate, 36, 180, 3, // Skip to: 1847 -/* 899 */ MCD_OPC_Decode, 196, 8, 233, 1, // Opcode: MINA_D -/* 904 */ MCD_OPC_FilterValue, 31, 171, 3, // Skip to: 1847 -/* 908 */ MCD_OPC_CheckPredicate, 36, 167, 3, // Skip to: 1847 -/* 912 */ MCD_OPC_Decode, 155, 8, 233, 1, // Opcode: MAXA_D -/* 917 */ MCD_OPC_FilterValue, 20, 211, 0, // Skip to: 1132 -/* 921 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 924 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 937 -/* 928 */ MCD_OPC_CheckPredicate, 36, 147, 3, // Skip to: 1847 -/* 932 */ MCD_OPC_Decode, 168, 3, 235, 1, // Opcode: CMP_F_S -/* 937 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 950 -/* 941 */ MCD_OPC_CheckPredicate, 36, 134, 3, // Skip to: 1847 -/* 945 */ MCD_OPC_Decode, 198, 3, 235, 1, // Opcode: CMP_UN_S -/* 950 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 963 -/* 954 */ MCD_OPC_CheckPredicate, 36, 121, 3, // Skip to: 1847 -/* 958 */ MCD_OPC_Decode, 166, 3, 235, 1, // Opcode: CMP_EQ_S -/* 963 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 976 -/* 967 */ MCD_OPC_CheckPredicate, 36, 108, 3, // Skip to: 1847 -/* 971 */ MCD_OPC_Decode, 192, 3, 235, 1, // Opcode: CMP_UEQ_S -/* 976 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 989 -/* 980 */ MCD_OPC_CheckPredicate, 36, 95, 3, // Skip to: 1847 -/* 984 */ MCD_OPC_Decode, 174, 3, 235, 1, // Opcode: CMP_LT_S -/* 989 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1002 -/* 993 */ MCD_OPC_CheckPredicate, 36, 82, 3, // Skip to: 1847 -/* 997 */ MCD_OPC_Decode, 196, 3, 235, 1, // Opcode: CMP_ULT_S -/* 1002 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1015 -/* 1006 */ MCD_OPC_CheckPredicate, 36, 69, 3, // Skip to: 1847 -/* 1010 */ MCD_OPC_Decode, 171, 3, 235, 1, // Opcode: CMP_LE_S -/* 1015 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1028 -/* 1019 */ MCD_OPC_CheckPredicate, 36, 56, 3, // Skip to: 1847 -/* 1023 */ MCD_OPC_Decode, 194, 3, 235, 1, // Opcode: CMP_ULE_S -/* 1028 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1041 -/* 1032 */ MCD_OPC_CheckPredicate, 36, 43, 3, // Skip to: 1847 -/* 1036 */ MCD_OPC_Decode, 176, 3, 235, 1, // Opcode: CMP_SAF_S -/* 1041 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1054 -/* 1045 */ MCD_OPC_CheckPredicate, 36, 30, 3, // Skip to: 1847 -/* 1049 */ MCD_OPC_Decode, 190, 3, 235, 1, // Opcode: CMP_SUN_S -/* 1054 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1067 -/* 1058 */ MCD_OPC_CheckPredicate, 36, 17, 3, // Skip to: 1847 -/* 1062 */ MCD_OPC_Decode, 178, 3, 235, 1, // Opcode: CMP_SEQ_S -/* 1067 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1080 -/* 1071 */ MCD_OPC_CheckPredicate, 36, 4, 3, // Skip to: 1847 -/* 1075 */ MCD_OPC_Decode, 184, 3, 235, 1, // Opcode: CMP_SUEQ_S -/* 1080 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1093 -/* 1084 */ MCD_OPC_CheckPredicate, 36, 247, 2, // Skip to: 1847 -/* 1088 */ MCD_OPC_Decode, 182, 3, 235, 1, // Opcode: CMP_SLT_S -/* 1093 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1106 -/* 1097 */ MCD_OPC_CheckPredicate, 36, 234, 2, // Skip to: 1847 -/* 1101 */ MCD_OPC_Decode, 188, 3, 235, 1, // Opcode: CMP_SULT_S -/* 1106 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1119 -/* 1110 */ MCD_OPC_CheckPredicate, 36, 221, 2, // Skip to: 1847 -/* 1114 */ MCD_OPC_Decode, 180, 3, 235, 1, // Opcode: CMP_SLE_S -/* 1119 */ MCD_OPC_FilterValue, 15, 212, 2, // Skip to: 1847 -/* 1123 */ MCD_OPC_CheckPredicate, 36, 208, 2, // Skip to: 1847 -/* 1127 */ MCD_OPC_Decode, 186, 3, 235, 1, // Opcode: CMP_SULE_S -/* 1132 */ MCD_OPC_FilterValue, 21, 199, 2, // Skip to: 1847 -/* 1136 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1139 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1152 -/* 1143 */ MCD_OPC_CheckPredicate, 36, 188, 2, // Skip to: 1847 -/* 1147 */ MCD_OPC_Decode, 167, 3, 236, 1, // Opcode: CMP_F_D -/* 1152 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1165 -/* 1156 */ MCD_OPC_CheckPredicate, 36, 175, 2, // Skip to: 1847 -/* 1160 */ MCD_OPC_Decode, 197, 3, 236, 1, // Opcode: CMP_UN_D -/* 1165 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1178 -/* 1169 */ MCD_OPC_CheckPredicate, 36, 162, 2, // Skip to: 1847 -/* 1173 */ MCD_OPC_Decode, 164, 3, 236, 1, // Opcode: CMP_EQ_D -/* 1178 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 1191 -/* 1182 */ MCD_OPC_CheckPredicate, 36, 149, 2, // Skip to: 1847 -/* 1186 */ MCD_OPC_Decode, 191, 3, 236, 1, // Opcode: CMP_UEQ_D -/* 1191 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 1204 -/* 1195 */ MCD_OPC_CheckPredicate, 36, 136, 2, // Skip to: 1847 -/* 1199 */ MCD_OPC_Decode, 172, 3, 236, 1, // Opcode: CMP_LT_D -/* 1204 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1217 -/* 1208 */ MCD_OPC_CheckPredicate, 36, 123, 2, // Skip to: 1847 -/* 1212 */ MCD_OPC_Decode, 195, 3, 236, 1, // Opcode: CMP_ULT_D -/* 1217 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1230 -/* 1221 */ MCD_OPC_CheckPredicate, 36, 110, 2, // Skip to: 1847 -/* 1225 */ MCD_OPC_Decode, 169, 3, 236, 1, // Opcode: CMP_LE_D -/* 1230 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1243 -/* 1234 */ MCD_OPC_CheckPredicate, 36, 97, 2, // Skip to: 1847 -/* 1238 */ MCD_OPC_Decode, 193, 3, 236, 1, // Opcode: CMP_ULE_D -/* 1243 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1256 -/* 1247 */ MCD_OPC_CheckPredicate, 36, 84, 2, // Skip to: 1847 -/* 1251 */ MCD_OPC_Decode, 175, 3, 236, 1, // Opcode: CMP_SAF_D -/* 1256 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1269 -/* 1260 */ MCD_OPC_CheckPredicate, 36, 71, 2, // Skip to: 1847 -/* 1264 */ MCD_OPC_Decode, 189, 3, 236, 1, // Opcode: CMP_SUN_D -/* 1269 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1282 -/* 1273 */ MCD_OPC_CheckPredicate, 36, 58, 2, // Skip to: 1847 -/* 1277 */ MCD_OPC_Decode, 177, 3, 236, 1, // Opcode: CMP_SEQ_D -/* 1282 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1295 -/* 1286 */ MCD_OPC_CheckPredicate, 36, 45, 2, // Skip to: 1847 -/* 1290 */ MCD_OPC_Decode, 183, 3, 236, 1, // Opcode: CMP_SUEQ_D -/* 1295 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1308 -/* 1299 */ MCD_OPC_CheckPredicate, 36, 32, 2, // Skip to: 1847 -/* 1303 */ MCD_OPC_Decode, 181, 3, 236, 1, // Opcode: CMP_SLT_D -/* 1308 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1321 -/* 1312 */ MCD_OPC_CheckPredicate, 36, 19, 2, // Skip to: 1847 -/* 1316 */ MCD_OPC_Decode, 187, 3, 236, 1, // Opcode: CMP_SULT_D -/* 1321 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1334 -/* 1325 */ MCD_OPC_CheckPredicate, 36, 6, 2, // Skip to: 1847 -/* 1329 */ MCD_OPC_Decode, 179, 3, 236, 1, // Opcode: CMP_SLE_D -/* 1334 */ MCD_OPC_FilterValue, 15, 253, 1, // Skip to: 1847 -/* 1338 */ MCD_OPC_CheckPredicate, 36, 249, 1, // Skip to: 1847 -/* 1342 */ MCD_OPC_Decode, 185, 3, 236, 1, // Opcode: CMP_SULE_D -/* 1347 */ MCD_OPC_FilterValue, 18, 81, 0, // Skip to: 1432 -/* 1351 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1354 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1367 -/* 1358 */ MCD_OPC_CheckPredicate, 36, 229, 1, // Skip to: 1847 -/* 1362 */ MCD_OPC_Decode, 188, 1, 237, 1, // Opcode: BC2EQZ -/* 1367 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1380 -/* 1371 */ MCD_OPC_CheckPredicate, 36, 216, 1, // Skip to: 1847 -/* 1375 */ MCD_OPC_Decode, 219, 7, 238, 1, // Opcode: LWC2_R6 -/* 1380 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1393 -/* 1384 */ MCD_OPC_CheckPredicate, 36, 203, 1, // Skip to: 1847 -/* 1388 */ MCD_OPC_Decode, 241, 12, 238, 1, // Opcode: SWC2_R6 -/* 1393 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1406 -/* 1397 */ MCD_OPC_CheckPredicate, 36, 190, 1, // Skip to: 1847 -/* 1401 */ MCD_OPC_Decode, 191, 1, 237, 1, // Opcode: BC2NEZ -/* 1406 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1419 -/* 1410 */ MCD_OPC_CheckPredicate, 36, 177, 1, // Skip to: 1847 -/* 1414 */ MCD_OPC_Decode, 166, 7, 238, 1, // Opcode: LDC2_R6 -/* 1419 */ MCD_OPC_FilterValue, 15, 168, 1, // Skip to: 1847 -/* 1423 */ MCD_OPC_CheckPredicate, 36, 164, 1, // Skip to: 1847 -/* 1427 */ MCD_OPC_Decode, 160, 11, 238, 1, // Opcode: SDC2_R6 -/* 1432 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 1445 -/* 1436 */ MCD_OPC_CheckPredicate, 36, 151, 1, // Skip to: 1847 -/* 1440 */ MCD_OPC_Decode, 224, 1, 239, 1, // Opcode: BGEZC -/* 1445 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 1458 -/* 1449 */ MCD_OPC_CheckPredicate, 36, 138, 1, // Skip to: 1847 -/* 1453 */ MCD_OPC_Decode, 138, 2, 240, 1, // Opcode: BLTZC -/* 1458 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 1471 -/* 1462 */ MCD_OPC_CheckPredicate, 36, 125, 1, // Skip to: 1847 -/* 1466 */ MCD_OPC_Decode, 147, 2, 241, 1, // Opcode: BNEC -/* 1471 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 1484 -/* 1475 */ MCD_OPC_CheckPredicate, 37, 112, 1, // Skip to: 1847 -/* 1479 */ MCD_OPC_Decode, 166, 4, 242, 1, // Opcode: DAUI -/* 1484 */ MCD_OPC_FilterValue, 31, 182, 0, // Skip to: 1670 -/* 1488 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1491 */ MCD_OPC_FilterValue, 32, 40, 0, // Skip to: 1535 -/* 1495 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 1498 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1523 -/* 1502 */ MCD_OPC_CheckPredicate, 36, 85, 1, // Skip to: 1847 -/* 1506 */ MCD_OPC_CheckField, 21, 5, 0, 79, 1, // Skip to: 1847 -/* 1512 */ MCD_OPC_CheckField, 6, 2, 0, 73, 1, // Skip to: 1847 -/* 1518 */ MCD_OPC_Decode, 250, 1, 205, 1, // Opcode: BITSWAP -/* 1523 */ MCD_OPC_FilterValue, 2, 64, 1, // Skip to: 1847 -/* 1527 */ MCD_OPC_CheckPredicate, 36, 60, 1, // Skip to: 1847 -/* 1531 */ MCD_OPC_Decode, 81, 221, 1, // Opcode: ALIGN -/* 1535 */ MCD_OPC_FilterValue, 36, 41, 0, // Skip to: 1580 -/* 1539 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... -/* 1542 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1567 -/* 1546 */ MCD_OPC_CheckPredicate, 37, 41, 1, // Skip to: 1847 -/* 1550 */ MCD_OPC_CheckField, 21, 5, 0, 35, 1, // Skip to: 1847 -/* 1556 */ MCD_OPC_CheckField, 6, 3, 0, 29, 1, // Skip to: 1847 -/* 1562 */ MCD_OPC_Decode, 167, 4, 243, 1, // Opcode: DBITSWAP -/* 1567 */ MCD_OPC_FilterValue, 1, 20, 1, // Skip to: 1847 -/* 1571 */ MCD_OPC_CheckPredicate, 37, 16, 1, // Skip to: 1847 -/* 1575 */ MCD_OPC_Decode, 164, 4, 244, 1, // Opcode: DALIGN -/* 1580 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 1599 -/* 1584 */ MCD_OPC_CheckPredicate, 36, 3, 1, // Skip to: 1847 -/* 1588 */ MCD_OPC_CheckField, 6, 1, 0, 253, 0, // Skip to: 1847 -/* 1594 */ MCD_OPC_Decode, 222, 2, 245, 1, // Opcode: CACHE_R6 -/* 1599 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 1612 -/* 1603 */ MCD_OPC_CheckPredicate, 36, 240, 0, // Skip to: 1847 -/* 1607 */ MCD_OPC_Decode, 150, 11, 246, 1, // Opcode: SC_R6 -/* 1612 */ MCD_OPC_FilterValue, 39, 9, 0, // Skip to: 1625 -/* 1616 */ MCD_OPC_CheckPredicate, 36, 227, 0, // Skip to: 1847 -/* 1620 */ MCD_OPC_Decode, 148, 11, 246, 1, // Opcode: SCD_R6 -/* 1625 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 1644 -/* 1629 */ MCD_OPC_CheckPredicate, 36, 214, 0, // Skip to: 1847 -/* 1633 */ MCD_OPC_CheckField, 6, 1, 0, 208, 0, // Skip to: 1847 -/* 1639 */ MCD_OPC_Decode, 183, 10, 245, 1, // Opcode: PREF_R6 -/* 1644 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 1657 -/* 1648 */ MCD_OPC_CheckPredicate, 36, 195, 0, // Skip to: 1847 -/* 1652 */ MCD_OPC_Decode, 197, 7, 246, 1, // Opcode: LL_R6 -/* 1657 */ MCD_OPC_FilterValue, 55, 186, 0, // Skip to: 1847 -/* 1661 */ MCD_OPC_CheckPredicate, 36, 182, 0, // Skip to: 1847 -/* 1665 */ MCD_OPC_Decode, 195, 7, 246, 1, // Opcode: LLD_R6 -/* 1670 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 1683 -/* 1674 */ MCD_OPC_CheckPredicate, 36, 169, 0, // Skip to: 1847 -/* 1678 */ MCD_OPC_Decode, 175, 1, 247, 1, // Opcode: BC -/* 1683 */ MCD_OPC_FilterValue, 54, 23, 0, // Skip to: 1710 -/* 1687 */ MCD_OPC_CheckPredicate, 36, 10, 0, // Skip to: 1701 -/* 1691 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 1701 -/* 1697 */ MCD_OPC_Decode, 135, 7, 52, // Opcode: JIC -/* 1701 */ MCD_OPC_CheckPredicate, 36, 142, 0, // Skip to: 1847 -/* 1705 */ MCD_OPC_Decode, 212, 1, 248, 1, // Opcode: BEQZC -/* 1710 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 1723 -/* 1714 */ MCD_OPC_CheckPredicate, 36, 129, 0, // Skip to: 1847 -/* 1718 */ MCD_OPC_Decode, 168, 1, 247, 1, // Opcode: BALC -/* 1723 */ MCD_OPC_FilterValue, 59, 93, 0, // Skip to: 1820 -/* 1727 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... -/* 1730 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1742 -/* 1734 */ MCD_OPC_CheckPredicate, 36, 109, 0, // Skip to: 1847 -/* 1738 */ MCD_OPC_Decode, 26, 249, 1, // Opcode: ADDIUPC -/* 1742 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1755 -/* 1746 */ MCD_OPC_CheckPredicate, 36, 97, 0, // Skip to: 1847 -/* 1750 */ MCD_OPC_Decode, 228, 7, 249, 1, // Opcode: LWPC -/* 1755 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1768 -/* 1759 */ MCD_OPC_CheckPredicate, 36, 84, 0, // Skip to: 1847 -/* 1763 */ MCD_OPC_Decode, 234, 7, 249, 1, // Opcode: LWUPC -/* 1768 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 1847 -/* 1772 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... -/* 1775 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1788 -/* 1779 */ MCD_OPC_CheckPredicate, 37, 64, 0, // Skip to: 1847 -/* 1783 */ MCD_OPC_Decode, 173, 7, 250, 1, // Opcode: LDPC -/* 1788 */ MCD_OPC_FilterValue, 1, 55, 0, // Skip to: 1847 -/* 1792 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 1795 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1808 -/* 1799 */ MCD_OPC_CheckPredicate, 36, 44, 0, // Skip to: 1847 -/* 1803 */ MCD_OPC_Decode, 138, 1, 251, 1, // Opcode: AUIPC -/* 1808 */ MCD_OPC_FilterValue, 3, 35, 0, // Skip to: 1847 -/* 1812 */ MCD_OPC_CheckPredicate, 36, 31, 0, // Skip to: 1847 -/* 1816 */ MCD_OPC_Decode, 82, 251, 1, // Opcode: ALUIPC -/* 1820 */ MCD_OPC_FilterValue, 62, 23, 0, // Skip to: 1847 -/* 1824 */ MCD_OPC_CheckPredicate, 36, 10, 0, // Skip to: 1838 -/* 1828 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 1838 -/* 1834 */ MCD_OPC_Decode, 134, 7, 52, // Opcode: JIALC -/* 1838 */ MCD_OPC_CheckPredicate, 36, 5, 0, // Skip to: 1847 -/* 1842 */ MCD_OPC_Decode, 159, 2, 248, 1, // Opcode: BNEZC -/* 1847 */ MCD_OPC_Fail, +/* 3 */ MCD_OPC_FilterValue, 0, 14, 2, 0, // Skip to: 534 +/* 8 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 11 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 33 +/* 16 */ MCD_OPC_CheckPredicate, 75, 133, 9, 0, // Skip to: 2458 +/* 21 */ MCD_OPC_CheckField, 8, 3, 0, 126, 9, 0, // Skip to: 2458 +/* 28 */ MCD_OPC_Decode, 250, 15, 185, 1, // Opcode: LSA_R6 +/* 33 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 55 +/* 38 */ MCD_OPC_CheckPredicate, 75, 111, 9, 0, // Skip to: 2458 +/* 43 */ MCD_OPC_CheckField, 6, 15, 16, 104, 9, 0, // Skip to: 2458 +/* 50 */ MCD_OPC_Decode, 143, 15, 186, 1, // Opcode: JR_HB_R6 +/* 55 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 70 +/* 60 */ MCD_OPC_CheckPredicate, 76, 89, 9, 0, // Skip to: 2458 +/* 65 */ MCD_OPC_Decode, 226, 20, 188, 1, // Opcode: SDBBP_R6 +/* 70 */ MCD_OPC_FilterValue, 16, 23, 0, 0, // Skip to: 98 +/* 75 */ MCD_OPC_CheckPredicate, 75, 74, 9, 0, // Skip to: 2458 +/* 80 */ MCD_OPC_CheckField, 16, 5, 0, 67, 9, 0, // Skip to: 2458 +/* 87 */ MCD_OPC_CheckField, 6, 5, 1, 60, 9, 0, // Skip to: 2458 +/* 94 */ MCD_OPC_Decode, 197, 9, 25, // Opcode: CLZ_R6 +/* 98 */ MCD_OPC_FilterValue, 17, 23, 0, 0, // Skip to: 126 +/* 103 */ MCD_OPC_CheckPredicate, 75, 46, 9, 0, // Skip to: 2458 +/* 108 */ MCD_OPC_CheckField, 16, 5, 0, 39, 9, 0, // Skip to: 2458 +/* 115 */ MCD_OPC_CheckField, 6, 5, 1, 32, 9, 0, // Skip to: 2458 +/* 122 */ MCD_OPC_Decode, 176, 9, 25, // Opcode: CLO_R6 +/* 126 */ MCD_OPC_FilterValue, 18, 23, 0, 0, // Skip to: 154 +/* 131 */ MCD_OPC_CheckPredicate, 77, 18, 9, 0, // Skip to: 2458 +/* 136 */ MCD_OPC_CheckField, 16, 5, 0, 11, 9, 0, // Skip to: 2458 +/* 143 */ MCD_OPC_CheckField, 6, 5, 1, 4, 9, 0, // Skip to: 2458 +/* 150 */ MCD_OPC_Decode, 203, 11, 26, // Opcode: DCLZ_R6 +/* 154 */ MCD_OPC_FilterValue, 19, 23, 0, 0, // Skip to: 182 +/* 159 */ MCD_OPC_CheckPredicate, 77, 246, 8, 0, // Skip to: 2458 +/* 164 */ MCD_OPC_CheckField, 16, 5, 0, 239, 8, 0, // Skip to: 2458 +/* 171 */ MCD_OPC_CheckField, 6, 5, 1, 232, 8, 0, // Skip to: 2458 +/* 178 */ MCD_OPC_Decode, 201, 11, 26, // Opcode: DCLO_R6 +/* 182 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 204 +/* 187 */ MCD_OPC_CheckPredicate, 77, 218, 8, 0, // Skip to: 2458 +/* 192 */ MCD_OPC_CheckField, 8, 3, 0, 211, 8, 0, // Skip to: 2458 +/* 199 */ MCD_OPC_Decode, 236, 11, 194, 1, // Opcode: DLSA_R6 +/* 204 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 240 +/* 209 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 212 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 226 +/* 217 */ MCD_OPC_CheckPredicate, 76, 188, 8, 0, // Skip to: 2458 +/* 222 */ MCD_OPC_Decode, 252, 18, 61, // Opcode: MUL_R6 +/* 226 */ MCD_OPC_FilterValue, 3, 179, 8, 0, // Skip to: 2458 +/* 231 */ MCD_OPC_CheckPredicate, 76, 174, 8, 0, // Skip to: 2458 +/* 236 */ MCD_OPC_Decode, 199, 18, 61, // Opcode: MUH +/* 240 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 276 +/* 245 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 248 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 262 +/* 253 */ MCD_OPC_CheckPredicate, 76, 152, 8, 0, // Skip to: 2458 +/* 258 */ MCD_OPC_Decode, 238, 18, 61, // Opcode: MULU +/* 262 */ MCD_OPC_FilterValue, 3, 143, 8, 0, // Skip to: 2458 +/* 267 */ MCD_OPC_CheckPredicate, 76, 138, 8, 0, // Skip to: 2458 +/* 272 */ MCD_OPC_Decode, 200, 18, 61, // Opcode: MUHU +/* 276 */ MCD_OPC_FilterValue, 26, 31, 0, 0, // Skip to: 312 +/* 281 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 284 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 298 +/* 289 */ MCD_OPC_CheckPredicate, 76, 116, 8, 0, // Skip to: 2458 +/* 294 */ MCD_OPC_Decode, 218, 11, 61, // Opcode: DIV +/* 298 */ MCD_OPC_FilterValue, 3, 107, 8, 0, // Skip to: 2458 +/* 303 */ MCD_OPC_CheckPredicate, 76, 102, 8, 0, // Skip to: 2458 +/* 308 */ MCD_OPC_Decode, 192, 17, 61, // Opcode: MOD +/* 312 */ MCD_OPC_FilterValue, 27, 31, 0, 0, // Skip to: 348 +/* 317 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 320 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 334 +/* 325 */ MCD_OPC_CheckPredicate, 76, 80, 8, 0, // Skip to: 2458 +/* 330 */ MCD_OPC_Decode, 219, 11, 61, // Opcode: DIVU +/* 334 */ MCD_OPC_FilterValue, 3, 71, 8, 0, // Skip to: 2458 +/* 339 */ MCD_OPC_CheckPredicate, 76, 66, 8, 0, // Skip to: 2458 +/* 344 */ MCD_OPC_Decode, 195, 17, 61, // Opcode: MODU +/* 348 */ MCD_OPC_FilterValue, 28, 31, 0, 0, // Skip to: 384 +/* 353 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 356 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 370 +/* 361 */ MCD_OPC_CheckPredicate, 77, 44, 8, 0, // Skip to: 2458 +/* 366 */ MCD_OPC_Decode, 129, 12, 23, // Opcode: DMUL_R6 +/* 370 */ MCD_OPC_FilterValue, 3, 35, 8, 0, // Skip to: 2458 +/* 375 */ MCD_OPC_CheckPredicate, 77, 30, 8, 0, // Skip to: 2458 +/* 380 */ MCD_OPC_Decode, 251, 11, 23, // Opcode: DMUH +/* 384 */ MCD_OPC_FilterValue, 29, 31, 0, 0, // Skip to: 420 +/* 389 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 392 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 406 +/* 397 */ MCD_OPC_CheckPredicate, 77, 8, 8, 0, // Skip to: 2458 +/* 402 */ MCD_OPC_Decode, 128, 12, 23, // Opcode: DMULU +/* 406 */ MCD_OPC_FilterValue, 3, 255, 7, 0, // Skip to: 2458 +/* 411 */ MCD_OPC_CheckPredicate, 77, 250, 7, 0, // Skip to: 2458 +/* 416 */ MCD_OPC_Decode, 252, 11, 23, // Opcode: DMUHU +/* 420 */ MCD_OPC_FilterValue, 30, 31, 0, 0, // Skip to: 456 +/* 425 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 428 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 442 +/* 433 */ MCD_OPC_CheckPredicate, 77, 228, 7, 0, // Skip to: 2458 +/* 438 */ MCD_OPC_Decode, 204, 11, 23, // Opcode: DDIV +/* 442 */ MCD_OPC_FilterValue, 3, 219, 7, 0, // Skip to: 2458 +/* 447 */ MCD_OPC_CheckPredicate, 77, 214, 7, 0, // Skip to: 2458 +/* 452 */ MCD_OPC_Decode, 242, 11, 23, // Opcode: DMOD +/* 456 */ MCD_OPC_FilterValue, 31, 31, 0, 0, // Skip to: 492 +/* 461 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 464 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 478 +/* 469 */ MCD_OPC_CheckPredicate, 77, 192, 7, 0, // Skip to: 2458 +/* 474 */ MCD_OPC_Decode, 205, 11, 23, // Opcode: DDIVU +/* 478 */ MCD_OPC_FilterValue, 3, 183, 7, 0, // Skip to: 2458 +/* 483 */ MCD_OPC_CheckPredicate, 77, 178, 7, 0, // Skip to: 2458 +/* 488 */ MCD_OPC_Decode, 243, 11, 23, // Opcode: DMODU +/* 492 */ MCD_OPC_FilterValue, 53, 16, 0, 0, // Skip to: 513 +/* 497 */ MCD_OPC_CheckPredicate, 78, 164, 7, 0, // Skip to: 2458 +/* 502 */ MCD_OPC_CheckField, 6, 5, 0, 157, 7, 0, // Skip to: 2458 +/* 509 */ MCD_OPC_Decode, 250, 20, 61, // Opcode: SELEQZ +/* 513 */ MCD_OPC_FilterValue, 55, 148, 7, 0, // Skip to: 2458 +/* 518 */ MCD_OPC_CheckPredicate, 78, 143, 7, 0, // Skip to: 2458 +/* 523 */ MCD_OPC_CheckField, 6, 5, 0, 136, 7, 0, // Skip to: 2458 +/* 530 */ MCD_OPC_Decode, 129, 21, 61, // Opcode: SELNEZ +/* 534 */ MCD_OPC_FilterValue, 1, 77, 0, 0, // Skip to: 616 +/* 539 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 542 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 557 +/* 547 */ MCD_OPC_CheckPredicate, 77, 114, 7, 0, // Skip to: 2458 +/* 552 */ MCD_OPC_Decode, 195, 11, 221, 2, // Opcode: DAHI +/* 557 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 579 +/* 562 */ MCD_OPC_CheckPredicate, 75, 99, 7, 0, // Skip to: 2458 +/* 567 */ MCD_OPC_CheckField, 21, 5, 0, 92, 7, 0, // Skip to: 2458 +/* 574 */ MCD_OPC_Decode, 147, 7, 198, 1, // Opcode: BAL +/* 579 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 601 +/* 584 */ MCD_OPC_CheckPredicate, 76, 77, 7, 0, // Skip to: 2458 +/* 589 */ MCD_OPC_CheckField, 21, 5, 0, 70, 7, 0, // Skip to: 2458 +/* 596 */ MCD_OPC_Decode, 208, 21, 222, 2, // Opcode: SIGRIE +/* 601 */ MCD_OPC_FilterValue, 30, 60, 7, 0, // Skip to: 2458 +/* 606 */ MCD_OPC_CheckPredicate, 77, 55, 7, 0, // Skip to: 2458 +/* 611 */ MCD_OPC_Decode, 197, 11, 221, 2, // Opcode: DATI +/* 616 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 631 +/* 621 */ MCD_OPC_CheckPredicate, 76, 40, 7, 0, // Skip to: 2458 +/* 626 */ MCD_OPC_Decode, 222, 7, 223, 2, // Opcode: BGEZALC +/* 631 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 646 +/* 636 */ MCD_OPC_CheckPredicate, 76, 25, 7, 0, // Skip to: 2458 +/* 641 */ MCD_OPC_Decode, 156, 8, 224, 2, // Opcode: BLTZALC +/* 646 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 661 +/* 651 */ MCD_OPC_CheckPredicate, 76, 10, 7, 0, // Skip to: 2458 +/* 656 */ MCD_OPC_Decode, 190, 7, 225, 2, // Opcode: BEQC +/* 661 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 676 +/* 666 */ MCD_OPC_CheckPredicate, 75, 251, 6, 0, // Skip to: 2458 +/* 671 */ MCD_OPC_Decode, 244, 6, 203, 1, // Opcode: AUI +/* 676 */ MCD_OPC_FilterValue, 16, 45, 0, 0, // Skip to: 726 +/* 681 */ MCD_OPC_ExtractField, 0, 16, // Inst{15-0} ... +/* 684 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 705 +/* 689 */ MCD_OPC_CheckPredicate, 75, 228, 6, 0, // Skip to: 2458 +/* 694 */ MCD_OPC_CheckField, 21, 5, 11, 221, 6, 0, // Skip to: 2458 +/* 701 */ MCD_OPC_Decode, 223, 12, 92, // Opcode: EVP +/* 705 */ MCD_OPC_FilterValue, 36, 212, 6, 0, // Skip to: 2458 +/* 710 */ MCD_OPC_CheckPredicate, 75, 207, 6, 0, // Skip to: 2458 +/* 715 */ MCD_OPC_CheckField, 21, 5, 11, 200, 6, 0, // Skip to: 2458 +/* 722 */ MCD_OPC_Decode, 200, 12, 92, // Opcode: DVP +/* 726 */ MCD_OPC_FilterValue, 17, 135, 3, 0, // Skip to: 1634 +/* 731 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 734 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 749 +/* 739 */ MCD_OPC_CheckPredicate, 79, 178, 6, 0, // Skip to: 2458 +/* 744 */ MCD_OPC_Decode, 164, 7, 226, 2, // Opcode: BC1EQZ +/* 749 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 764 +/* 754 */ MCD_OPC_CheckPredicate, 79, 163, 6, 0, // Skip to: 2458 +/* 759 */ MCD_OPC_Decode, 169, 7, 226, 2, // Opcode: BC1NEZ +/* 764 */ MCD_OPC_FilterValue, 16, 182, 0, 0, // Skip to: 951 +/* 769 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 772 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 787 +/* 777 */ MCD_OPC_CheckPredicate, 79, 140, 6, 0, // Skip to: 2458 +/* 782 */ MCD_OPC_Decode, 138, 21, 227, 2, // Opcode: SEL_S +/* 787 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 802 +/* 792 */ MCD_OPC_CheckPredicate, 79, 125, 6, 0, // Skip to: 2458 +/* 797 */ MCD_OPC_Decode, 255, 20, 218, 1, // Opcode: SELEQZ_S +/* 802 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 817 +/* 807 */ MCD_OPC_CheckPredicate, 79, 110, 6, 0, // Skip to: 2458 +/* 812 */ MCD_OPC_Decode, 134, 21, 218, 1, // Opcode: SELNEZ_S +/* 817 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 832 +/* 822 */ MCD_OPC_CheckPredicate, 79, 95, 6, 0, // Skip to: 2458 +/* 827 */ MCD_OPC_Decode, 198, 16, 228, 2, // Opcode: MADDF_S +/* 832 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 847 +/* 837 */ MCD_OPC_CheckPredicate, 79, 80, 6, 0, // Skip to: 2458 +/* 842 */ MCD_OPC_Decode, 134, 18, 228, 2, // Opcode: MSUBF_S +/* 847 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 869 +/* 852 */ MCD_OPC_CheckPredicate, 79, 65, 6, 0, // Skip to: 2458 +/* 857 */ MCD_OPC_CheckField, 16, 5, 0, 58, 6, 0, // Skip to: 2458 +/* 864 */ MCD_OPC_Decode, 153, 20, 219, 1, // Opcode: RINT_S +/* 869 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 891 +/* 874 */ MCD_OPC_CheckPredicate, 79, 43, 6, 0, // Skip to: 2458 +/* 879 */ MCD_OPC_CheckField, 16, 5, 0, 36, 6, 0, // Skip to: 2458 +/* 886 */ MCD_OPC_Decode, 154, 9, 219, 1, // Opcode: CLASS_S +/* 891 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 906 +/* 896 */ MCD_OPC_CheckPredicate, 79, 21, 6, 0, // Skip to: 2458 +/* 901 */ MCD_OPC_Decode, 182, 17, 218, 1, // Opcode: MIN_S +/* 906 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 921 +/* 911 */ MCD_OPC_CheckPredicate, 79, 6, 6, 0, // Skip to: 2458 +/* 916 */ MCD_OPC_Decode, 246, 16, 218, 1, // Opcode: MAX_S +/* 921 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 936 +/* 926 */ MCD_OPC_CheckPredicate, 79, 247, 5, 0, // Skip to: 2458 +/* 931 */ MCD_OPC_Decode, 166, 17, 218, 1, // Opcode: MINA_S +/* 936 */ MCD_OPC_FilterValue, 31, 237, 5, 0, // Skip to: 2458 +/* 941 */ MCD_OPC_CheckPredicate, 79, 232, 5, 0, // Skip to: 2458 +/* 946 */ MCD_OPC_Decode, 230, 16, 218, 1, // Opcode: MAXA_S +/* 951 */ MCD_OPC_FilterValue, 17, 182, 0, 0, // Skip to: 1138 +/* 956 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 959 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 974 +/* 964 */ MCD_OPC_CheckPredicate, 79, 209, 5, 0, // Skip to: 2458 +/* 969 */ MCD_OPC_Decode, 136, 21, 229, 2, // Opcode: SEL_D +/* 974 */ MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 989 +/* 979 */ MCD_OPC_CheckPredicate, 79, 194, 5, 0, // Skip to: 2458 +/* 984 */ MCD_OPC_Decode, 252, 20, 230, 2, // Opcode: SELEQZ_D +/* 989 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 1004 +/* 994 */ MCD_OPC_CheckPredicate, 79, 179, 5, 0, // Skip to: 2458 +/* 999 */ MCD_OPC_Decode, 131, 21, 230, 2, // Opcode: SELNEZ_D +/* 1004 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 1019 +/* 1009 */ MCD_OPC_CheckPredicate, 79, 164, 5, 0, // Skip to: 2458 +/* 1014 */ MCD_OPC_Decode, 196, 16, 229, 2, // Opcode: MADDF_D +/* 1019 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 1034 +/* 1024 */ MCD_OPC_CheckPredicate, 79, 149, 5, 0, // Skip to: 2458 +/* 1029 */ MCD_OPC_Decode, 132, 18, 229, 2, // Opcode: MSUBF_D +/* 1034 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 1056 +/* 1039 */ MCD_OPC_CheckPredicate, 79, 134, 5, 0, // Skip to: 2458 +/* 1044 */ MCD_OPC_CheckField, 16, 5, 0, 127, 5, 0, // Skip to: 2458 +/* 1051 */ MCD_OPC_Decode, 151, 20, 230, 1, // Opcode: RINT_D +/* 1056 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 1078 +/* 1061 */ MCD_OPC_CheckPredicate, 79, 112, 5, 0, // Skip to: 2458 +/* 1066 */ MCD_OPC_CheckField, 16, 5, 0, 105, 5, 0, // Skip to: 2458 +/* 1073 */ MCD_OPC_Decode, 152, 9, 230, 1, // Opcode: CLASS_D +/* 1078 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 1093 +/* 1083 */ MCD_OPC_CheckPredicate, 79, 90, 5, 0, // Skip to: 2458 +/* 1088 */ MCD_OPC_Decode, 180, 17, 230, 2, // Opcode: MIN_D +/* 1093 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 1108 +/* 1098 */ MCD_OPC_CheckPredicate, 79, 75, 5, 0, // Skip to: 2458 +/* 1103 */ MCD_OPC_Decode, 244, 16, 230, 2, // Opcode: MAX_D +/* 1108 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 1123 +/* 1113 */ MCD_OPC_CheckPredicate, 79, 60, 5, 0, // Skip to: 2458 +/* 1118 */ MCD_OPC_Decode, 164, 17, 230, 2, // Opcode: MINA_D +/* 1123 */ MCD_OPC_FilterValue, 31, 50, 5, 0, // Skip to: 2458 +/* 1128 */ MCD_OPC_CheckPredicate, 79, 45, 5, 0, // Skip to: 2458 +/* 1133 */ MCD_OPC_Decode, 228, 16, 230, 2, // Opcode: MAXA_D +/* 1138 */ MCD_OPC_FilterValue, 20, 243, 0, 0, // Skip to: 1386 +/* 1143 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 1146 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1161 +/* 1151 */ MCD_OPC_CheckPredicate, 79, 22, 5, 0, // Skip to: 2458 +/* 1156 */ MCD_OPC_Decode, 225, 9, 231, 2, // Opcode: CMP_F_S +/* 1161 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1176 +/* 1166 */ MCD_OPC_CheckPredicate, 79, 7, 5, 0, // Skip to: 2458 +/* 1171 */ MCD_OPC_Decode, 156, 10, 231, 2, // Opcode: CMP_UN_S +/* 1176 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1191 +/* 1181 */ MCD_OPC_CheckPredicate, 79, 248, 4, 0, // Skip to: 2458 +/* 1186 */ MCD_OPC_Decode, 222, 9, 231, 2, // Opcode: CMP_EQ_S +/* 1191 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1206 +/* 1196 */ MCD_OPC_CheckPredicate, 79, 233, 4, 0, // Skip to: 2458 +/* 1201 */ MCD_OPC_Decode, 144, 10, 231, 2, // Opcode: CMP_UEQ_S +/* 1206 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 1221 +/* 1211 */ MCD_OPC_CheckPredicate, 79, 218, 4, 0, // Skip to: 2458 +/* 1216 */ MCD_OPC_Decode, 236, 9, 231, 2, // Opcode: CMP_LT_S +/* 1221 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1236 +/* 1226 */ MCD_OPC_CheckPredicate, 79, 203, 4, 0, // Skip to: 2458 +/* 1231 */ MCD_OPC_Decode, 152, 10, 231, 2, // Opcode: CMP_ULT_S +/* 1236 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 1251 +/* 1241 */ MCD_OPC_CheckPredicate, 79, 188, 4, 0, // Skip to: 2458 +/* 1246 */ MCD_OPC_Decode, 230, 9, 231, 2, // Opcode: CMP_LE_S +/* 1251 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 1266 +/* 1256 */ MCD_OPC_CheckPredicate, 79, 173, 4, 0, // Skip to: 2458 +/* 1261 */ MCD_OPC_Decode, 148, 10, 231, 2, // Opcode: CMP_ULE_S +/* 1266 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 1281 +/* 1271 */ MCD_OPC_CheckPredicate, 79, 158, 4, 0, // Skip to: 2458 +/* 1276 */ MCD_OPC_Decode, 240, 9, 231, 2, // Opcode: CMP_SAF_S +/* 1281 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 1296 +/* 1286 */ MCD_OPC_CheckPredicate, 79, 143, 4, 0, // Skip to: 2458 +/* 1291 */ MCD_OPC_Decode, 140, 10, 231, 2, // Opcode: CMP_SUN_S +/* 1296 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1311 +/* 1301 */ MCD_OPC_CheckPredicate, 79, 128, 4, 0, // Skip to: 2458 +/* 1306 */ MCD_OPC_Decode, 244, 9, 231, 2, // Opcode: CMP_SEQ_S +/* 1311 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1326 +/* 1316 */ MCD_OPC_CheckPredicate, 79, 113, 4, 0, // Skip to: 2458 +/* 1321 */ MCD_OPC_Decode, 128, 10, 231, 2, // Opcode: CMP_SUEQ_S +/* 1326 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 1341 +/* 1331 */ MCD_OPC_CheckPredicate, 79, 98, 4, 0, // Skip to: 2458 +/* 1336 */ MCD_OPC_Decode, 252, 9, 231, 2, // Opcode: CMP_SLT_S +/* 1341 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1356 +/* 1346 */ MCD_OPC_CheckPredicate, 79, 83, 4, 0, // Skip to: 2458 +/* 1351 */ MCD_OPC_Decode, 136, 10, 231, 2, // Opcode: CMP_SULT_S +/* 1356 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1371 +/* 1361 */ MCD_OPC_CheckPredicate, 79, 68, 4, 0, // Skip to: 2458 +/* 1366 */ MCD_OPC_Decode, 248, 9, 231, 2, // Opcode: CMP_SLE_S +/* 1371 */ MCD_OPC_FilterValue, 15, 58, 4, 0, // Skip to: 2458 +/* 1376 */ MCD_OPC_CheckPredicate, 79, 53, 4, 0, // Skip to: 2458 +/* 1381 */ MCD_OPC_Decode, 132, 10, 231, 2, // Opcode: CMP_SULE_S +/* 1386 */ MCD_OPC_FilterValue, 21, 43, 4, 0, // Skip to: 2458 +/* 1391 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 1394 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1409 +/* 1399 */ MCD_OPC_CheckPredicate, 79, 30, 4, 0, // Skip to: 2458 +/* 1404 */ MCD_OPC_Decode, 224, 9, 232, 2, // Opcode: CMP_F_D +/* 1409 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1424 +/* 1414 */ MCD_OPC_CheckPredicate, 79, 15, 4, 0, // Skip to: 2458 +/* 1419 */ MCD_OPC_Decode, 154, 10, 232, 2, // Opcode: CMP_UN_D +/* 1424 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1439 +/* 1429 */ MCD_OPC_CheckPredicate, 79, 0, 4, 0, // Skip to: 2458 +/* 1434 */ MCD_OPC_Decode, 218, 9, 232, 2, // Opcode: CMP_EQ_D +/* 1439 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1454 +/* 1444 */ MCD_OPC_CheckPredicate, 79, 241, 3, 0, // Skip to: 2458 +/* 1449 */ MCD_OPC_Decode, 142, 10, 232, 2, // Opcode: CMP_UEQ_D +/* 1454 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 1469 +/* 1459 */ MCD_OPC_CheckPredicate, 79, 226, 3, 0, // Skip to: 2458 +/* 1464 */ MCD_OPC_Decode, 232, 9, 232, 2, // Opcode: CMP_LT_D +/* 1469 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1484 +/* 1474 */ MCD_OPC_CheckPredicate, 79, 211, 3, 0, // Skip to: 2458 +/* 1479 */ MCD_OPC_Decode, 150, 10, 232, 2, // Opcode: CMP_ULT_D +/* 1484 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 1499 +/* 1489 */ MCD_OPC_CheckPredicate, 79, 196, 3, 0, // Skip to: 2458 +/* 1494 */ MCD_OPC_Decode, 226, 9, 232, 2, // Opcode: CMP_LE_D +/* 1499 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 1514 +/* 1504 */ MCD_OPC_CheckPredicate, 79, 181, 3, 0, // Skip to: 2458 +/* 1509 */ MCD_OPC_Decode, 146, 10, 232, 2, // Opcode: CMP_ULE_D +/* 1514 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 1529 +/* 1519 */ MCD_OPC_CheckPredicate, 79, 166, 3, 0, // Skip to: 2458 +/* 1524 */ MCD_OPC_Decode, 238, 9, 232, 2, // Opcode: CMP_SAF_D +/* 1529 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 1544 +/* 1534 */ MCD_OPC_CheckPredicate, 79, 151, 3, 0, // Skip to: 2458 +/* 1539 */ MCD_OPC_Decode, 138, 10, 232, 2, // Opcode: CMP_SUN_D +/* 1544 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1559 +/* 1549 */ MCD_OPC_CheckPredicate, 79, 136, 3, 0, // Skip to: 2458 +/* 1554 */ MCD_OPC_Decode, 242, 9, 232, 2, // Opcode: CMP_SEQ_D +/* 1559 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1574 +/* 1564 */ MCD_OPC_CheckPredicate, 79, 121, 3, 0, // Skip to: 2458 +/* 1569 */ MCD_OPC_Decode, 254, 9, 232, 2, // Opcode: CMP_SUEQ_D +/* 1574 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 1589 +/* 1579 */ MCD_OPC_CheckPredicate, 79, 106, 3, 0, // Skip to: 2458 +/* 1584 */ MCD_OPC_Decode, 250, 9, 232, 2, // Opcode: CMP_SLT_D +/* 1589 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1604 +/* 1594 */ MCD_OPC_CheckPredicate, 79, 91, 3, 0, // Skip to: 2458 +/* 1599 */ MCD_OPC_Decode, 134, 10, 232, 2, // Opcode: CMP_SULT_D +/* 1604 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1619 +/* 1609 */ MCD_OPC_CheckPredicate, 79, 76, 3, 0, // Skip to: 2458 +/* 1614 */ MCD_OPC_Decode, 246, 9, 232, 2, // Opcode: CMP_SLE_D +/* 1619 */ MCD_OPC_FilterValue, 15, 66, 3, 0, // Skip to: 2458 +/* 1624 */ MCD_OPC_CheckPredicate, 79, 61, 3, 0, // Skip to: 2458 +/* 1629 */ MCD_OPC_Decode, 130, 10, 232, 2, // Opcode: CMP_SULE_D +/* 1634 */ MCD_OPC_FilterValue, 18, 93, 0, 0, // Skip to: 1732 +/* 1639 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 1642 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 1657 +/* 1647 */ MCD_OPC_CheckPredicate, 76, 38, 3, 0, // Skip to: 2458 +/* 1652 */ MCD_OPC_Decode, 174, 7, 233, 2, // Opcode: BC2EQZ +/* 1657 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1672 +/* 1662 */ MCD_OPC_CheckPredicate, 76, 23, 3, 0, // Skip to: 2458 +/* 1667 */ MCD_OPC_Decode, 140, 16, 234, 2, // Opcode: LWC2_R6 +/* 1672 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1687 +/* 1677 */ MCD_OPC_CheckPredicate, 76, 8, 3, 0, // Skip to: 2458 +/* 1682 */ MCD_OPC_Decode, 138, 23, 234, 2, // Opcode: SWC2_R6 +/* 1687 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1702 +/* 1692 */ MCD_OPC_CheckPredicate, 76, 249, 2, 0, // Skip to: 2458 +/* 1697 */ MCD_OPC_Decode, 176, 7, 233, 2, // Opcode: BC2NEZ +/* 1702 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1717 +/* 1707 */ MCD_OPC_CheckPredicate, 76, 234, 2, 0, // Skip to: 2458 +/* 1712 */ MCD_OPC_Decode, 187, 15, 234, 2, // Opcode: LDC2_R6 +/* 1717 */ MCD_OPC_FilterValue, 15, 224, 2, 0, // Skip to: 2458 +/* 1722 */ MCD_OPC_CheckPredicate, 76, 219, 2, 0, // Skip to: 2458 +/* 1727 */ MCD_OPC_Decode, 234, 20, 234, 2, // Opcode: SDC2_R6 +/* 1732 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 1747 +/* 1737 */ MCD_OPC_CheckPredicate, 76, 204, 2, 0, // Skip to: 2458 +/* 1742 */ MCD_OPC_Decode, 227, 7, 235, 2, // Opcode: BGEZC +/* 1747 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 1762 +/* 1752 */ MCD_OPC_CheckPredicate, 76, 189, 2, 0, // Skip to: 2458 +/* 1757 */ MCD_OPC_Decode, 161, 8, 236, 2, // Opcode: BLTZC +/* 1762 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 1777 +/* 1767 */ MCD_OPC_CheckPredicate, 76, 174, 2, 0, // Skip to: 2458 +/* 1772 */ MCD_OPC_Decode, 172, 8, 237, 2, // Opcode: BNEC +/* 1777 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 1792 +/* 1782 */ MCD_OPC_CheckPredicate, 77, 159, 2, 0, // Skip to: 2458 +/* 1787 */ MCD_OPC_Decode, 198, 11, 238, 2, // Opcode: DAUI +/* 1792 */ MCD_OPC_FilterValue, 31, 135, 1, 0, // Skip to: 2188 +/* 1797 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 1800 */ MCD_OPC_FilterValue, 15, 123, 0, 0, // Skip to: 1928 +/* 1805 */ MCD_OPC_ExtractField, 6, 10, // Inst{15-6} ... +/* 1808 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1823 +/* 1813 */ MCD_OPC_CheckPredicate, 80, 128, 2, 0, // Skip to: 2458 +/* 1818 */ MCD_OPC_Decode, 165, 10, 239, 2, // Opcode: CRC32B +/* 1823 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1838 +/* 1828 */ MCD_OPC_CheckPredicate, 80, 113, 2, 0, // Skip to: 2458 +/* 1833 */ MCD_OPC_Decode, 175, 10, 239, 2, // Opcode: CRC32H +/* 1838 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1853 +/* 1843 */ MCD_OPC_CheckPredicate, 80, 98, 2, 0, // Skip to: 2458 +/* 1848 */ MCD_OPC_Decode, 177, 10, 239, 2, // Opcode: CRC32W +/* 1853 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1868 +/* 1858 */ MCD_OPC_CheckPredicate, 81, 83, 2, 0, // Skip to: 2458 +/* 1863 */ MCD_OPC_Decode, 174, 10, 239, 2, // Opcode: CRC32D +/* 1868 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 1883 +/* 1873 */ MCD_OPC_CheckPredicate, 80, 68, 2, 0, // Skip to: 2458 +/* 1878 */ MCD_OPC_Decode, 167, 10, 239, 2, // Opcode: CRC32CB +/* 1883 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1898 +/* 1888 */ MCD_OPC_CheckPredicate, 80, 53, 2, 0, // Skip to: 2458 +/* 1893 */ MCD_OPC_Decode, 170, 10, 239, 2, // Opcode: CRC32CH +/* 1898 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 1913 +/* 1903 */ MCD_OPC_CheckPredicate, 80, 38, 2, 0, // Skip to: 2458 +/* 1908 */ MCD_OPC_Decode, 172, 10, 239, 2, // Opcode: CRC32CW +/* 1913 */ MCD_OPC_FilterValue, 7, 28, 2, 0, // Skip to: 2458 +/* 1918 */ MCD_OPC_CheckPredicate, 81, 23, 2, 0, // Skip to: 2458 +/* 1923 */ MCD_OPC_Decode, 169, 10, 239, 2, // Opcode: CRC32CD +/* 1928 */ MCD_OPC_FilterValue, 32, 47, 0, 0, // Skip to: 1980 +/* 1933 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 1936 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1965 +/* 1941 */ MCD_OPC_CheckPredicate, 75, 0, 2, 0, // Skip to: 2458 +/* 1946 */ MCD_OPC_CheckField, 21, 5, 0, 249, 1, 0, // Skip to: 2458 +/* 1953 */ MCD_OPC_CheckField, 6, 2, 0, 242, 1, 0, // Skip to: 2458 +/* 1960 */ MCD_OPC_Decode, 132, 8, 204, 2, // Opcode: BITSWAP +/* 1965 */ MCD_OPC_FilterValue, 2, 232, 1, 0, // Skip to: 2458 +/* 1970 */ MCD_OPC_CheckPredicate, 75, 227, 1, 0, // Skip to: 2458 +/* 1975 */ MCD_OPC_Decode, 211, 6, 240, 2, // Opcode: ALIGN +/* 1980 */ MCD_OPC_FilterValue, 36, 47, 0, 0, // Skip to: 2032 +/* 1985 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 1988 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2017 +/* 1993 */ MCD_OPC_CheckPredicate, 77, 204, 1, 0, // Skip to: 2458 +/* 1998 */ MCD_OPC_CheckField, 21, 5, 0, 197, 1, 0, // Skip to: 2458 +/* 2005 */ MCD_OPC_CheckField, 6, 3, 0, 190, 1, 0, // Skip to: 2458 +/* 2012 */ MCD_OPC_Decode, 199, 11, 241, 2, // Opcode: DBITSWAP +/* 2017 */ MCD_OPC_FilterValue, 1, 180, 1, 0, // Skip to: 2458 +/* 2022 */ MCD_OPC_CheckPredicate, 77, 175, 1, 0, // Skip to: 2458 +/* 2027 */ MCD_OPC_Decode, 196, 11, 242, 2, // Opcode: DALIGN +/* 2032 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 2054 +/* 2037 */ MCD_OPC_CheckPredicate, 76, 160, 1, 0, // Skip to: 2458 +/* 2042 */ MCD_OPC_CheckField, 6, 1, 0, 153, 1, 0, // Skip to: 2458 +/* 2049 */ MCD_OPC_Decode, 252, 8, 209, 2, // Opcode: CACHE_R6 +/* 2054 */ MCD_OPC_FilterValue, 38, 10, 0, 0, // Skip to: 2069 +/* 2059 */ MCD_OPC_CheckPredicate, 82, 138, 1, 0, // Skip to: 2458 +/* 2064 */ MCD_OPC_Decode, 217, 20, 243, 2, // Opcode: SC_R6 +/* 2069 */ MCD_OPC_FilterValue, 39, 10, 0, 0, // Skip to: 2084 +/* 2074 */ MCD_OPC_CheckPredicate, 75, 123, 1, 0, // Skip to: 2458 +/* 2079 */ MCD_OPC_Decode, 210, 20, 243, 2, // Opcode: SCD_R6 +/* 2084 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 2106 +/* 2089 */ MCD_OPC_CheckPredicate, 76, 108, 1, 0, // Skip to: 2458 +/* 2094 */ MCD_OPC_CheckField, 6, 1, 0, 101, 1, 0, // Skip to: 2458 +/* 2101 */ MCD_OPC_Decode, 245, 19, 209, 2, // Opcode: PREF_R6 +/* 2106 */ MCD_OPC_FilterValue, 54, 10, 0, 0, // Skip to: 2121 +/* 2111 */ MCD_OPC_CheckPredicate, 82, 86, 1, 0, // Skip to: 2458 +/* 2116 */ MCD_OPC_Decode, 246, 15, 243, 2, // Opcode: LL_R6 +/* 2121 */ MCD_OPC_FilterValue, 55, 10, 0, 0, // Skip to: 2136 +/* 2126 */ MCD_OPC_CheckPredicate, 77, 71, 1, 0, // Skip to: 2458 +/* 2131 */ MCD_OPC_Decode, 239, 15, 243, 2, // Opcode: LLD_R6 +/* 2136 */ MCD_OPC_FilterValue, 61, 61, 1, 0, // Skip to: 2458 +/* 2141 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 2144 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2166 +/* 2149 */ MCD_OPC_CheckPredicate, 83, 48, 1, 0, // Skip to: 2458 +/* 2154 */ MCD_OPC_CheckField, 8, 13, 0, 41, 1, 0, // Skip to: 2458 +/* 2161 */ MCD_OPC_Decode, 184, 14, 186, 1, // Opcode: GINVI +/* 2166 */ MCD_OPC_FilterValue, 2, 31, 1, 0, // Skip to: 2458 +/* 2171 */ MCD_OPC_CheckPredicate, 83, 26, 1, 0, // Skip to: 2458 +/* 2176 */ MCD_OPC_CheckField, 10, 11, 0, 19, 1, 0, // Skip to: 2458 +/* 2183 */ MCD_OPC_Decode, 187, 14, 244, 2, // Opcode: GINVT +/* 2188 */ MCD_OPC_FilterValue, 50, 10, 0, 0, // Skip to: 2203 +/* 2193 */ MCD_OPC_CheckPredicate, 76, 4, 1, 0, // Skip to: 2458 +/* 2198 */ MCD_OPC_Decode, 161, 7, 245, 2, // Opcode: BC +/* 2203 */ MCD_OPC_FilterValue, 53, 27, 0, 0, // Skip to: 2235 +/* 2208 */ MCD_OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 2225 +/* 2213 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 2225 +/* 2220 */ MCD_OPC_Decode, 238, 7, 180, 1, // Opcode: BGTZC_MMR6 +/* 2225 */ MCD_OPC_CheckPredicate, 24, 228, 0, 0, // Skip to: 2458 +/* 2230 */ MCD_OPC_Decode, 163, 8, 180, 1, // Opcode: BLTZC_MMR6 +/* 2235 */ MCD_OPC_FilterValue, 54, 26, 0, 0, // Skip to: 2266 +/* 2240 */ MCD_OPC_CheckPredicate, 75, 11, 0, 0, // Skip to: 2256 +/* 2245 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 2256 +/* 2252 */ MCD_OPC_Decode, 129, 15, 103, // Opcode: JIC +/* 2256 */ MCD_OPC_CheckPredicate, 76, 197, 0, 0, // Skip to: 2458 +/* 2261 */ MCD_OPC_Decode, 201, 7, 246, 2, // Opcode: BEQZC +/* 2266 */ MCD_OPC_FilterValue, 58, 10, 0, 0, // Skip to: 2281 +/* 2271 */ MCD_OPC_CheckPredicate, 75, 182, 0, 0, // Skip to: 2458 +/* 2276 */ MCD_OPC_Decode, 148, 7, 245, 2, // Opcode: BALC +/* 2281 */ MCD_OPC_FilterValue, 59, 109, 0, 0, // Skip to: 2395 +/* 2286 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... +/* 2289 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2304 +/* 2294 */ MCD_OPC_CheckPredicate, 75, 159, 0, 0, // Skip to: 2458 +/* 2299 */ MCD_OPC_Decode, 129, 6, 174, 1, // Opcode: ADDIUPC +/* 2304 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2319 +/* 2309 */ MCD_OPC_CheckPredicate, 75, 144, 0, 0, // Skip to: 2458 +/* 2314 */ MCD_OPC_Decode, 158, 16, 174, 1, // Opcode: LWPC +/* 2319 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2334 +/* 2324 */ MCD_OPC_CheckPredicate, 84, 129, 0, 0, // Skip to: 2458 +/* 2329 */ MCD_OPC_Decode, 169, 16, 174, 1, // Opcode: LWUPC +/* 2334 */ MCD_OPC_FilterValue, 3, 119, 0, 0, // Skip to: 2458 +/* 2339 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 2342 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2357 +/* 2347 */ MCD_OPC_CheckPredicate, 84, 106, 0, 0, // Skip to: 2458 +/* 2352 */ MCD_OPC_Decode, 194, 15, 247, 2, // Opcode: LDPC +/* 2357 */ MCD_OPC_FilterValue, 1, 96, 0, 0, // Skip to: 2458 +/* 2362 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 2365 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2380 +/* 2370 */ MCD_OPC_CheckPredicate, 75, 83, 0, 0, // Skip to: 2458 +/* 2375 */ MCD_OPC_Decode, 245, 6, 175, 1, // Opcode: AUIPC +/* 2380 */ MCD_OPC_FilterValue, 3, 73, 0, 0, // Skip to: 2458 +/* 2385 */ MCD_OPC_CheckPredicate, 75, 68, 0, 0, // Skip to: 2458 +/* 2390 */ MCD_OPC_Decode, 213, 6, 175, 1, // Opcode: ALUIPC +/* 2395 */ MCD_OPC_FilterValue, 61, 27, 0, 0, // Skip to: 2427 +/* 2400 */ MCD_OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 2417 +/* 2405 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 2417 +/* 2412 */ MCD_OPC_Decode, 140, 8, 182, 1, // Opcode: BLEZC_MMR6 +/* 2417 */ MCD_OPC_CheckPredicate, 24, 36, 0, 0, // Skip to: 2458 +/* 2422 */ MCD_OPC_Decode, 229, 7, 182, 1, // Opcode: BGEZC_MMR6 +/* 2427 */ MCD_OPC_FilterValue, 62, 26, 0, 0, // Skip to: 2458 +/* 2432 */ MCD_OPC_CheckPredicate, 75, 11, 0, 0, // Skip to: 2448 +/* 2437 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 2448 +/* 2444 */ MCD_OPC_Decode, 254, 14, 103, // Opcode: JIALC +/* 2448 */ MCD_OPC_CheckPredicate, 76, 5, 0, 0, // Skip to: 2458 +/* 2453 */ MCD_OPC_Decode, 191, 8, 246, 2, // Opcode: BNEZC +/* 2458 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMips32r6_64r6_Ambiguous32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 6, 27, 0, 0, // Skip to: 35 +/* 8 */ MCD_OPC_CheckPredicate, 76, 12, 0, 0, // Skip to: 25 +/* 13 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 25 +/* 20 */ MCD_OPC_Decode, 136, 8, 223, 2, // Opcode: BLEZALC +/* 25 */ MCD_OPC_CheckPredicate, 76, 165, 0, 0, // Skip to: 195 +/* 30 */ MCD_OPC_Decode, 215, 7, 223, 2, // Opcode: BGEUC +/* 35 */ MCD_OPC_FilterValue, 7, 27, 0, 0, // Skip to: 67 +/* 40 */ MCD_OPC_CheckPredicate, 76, 12, 0, 0, // Skip to: 57 +/* 45 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 57 +/* 52 */ MCD_OPC_Decode, 234, 7, 224, 2, // Opcode: BGTZALC +/* 57 */ MCD_OPC_CheckPredicate, 76, 133, 0, 0, // Skip to: 195 +/* 62 */ MCD_OPC_Decode, 149, 8, 224, 2, // Opcode: BLTUC +/* 67 */ MCD_OPC_FilterValue, 8, 27, 0, 0, // Skip to: 99 +/* 72 */ MCD_OPC_CheckPredicate, 76, 12, 0, 0, // Skip to: 89 +/* 77 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 89 +/* 84 */ MCD_OPC_Decode, 199, 7, 237, 2, // Opcode: BEQZALC +/* 89 */ MCD_OPC_CheckPredicate, 76, 101, 0, 0, // Skip to: 195 +/* 94 */ MCD_OPC_Decode, 206, 8, 225, 2, // Opcode: BOVC +/* 99 */ MCD_OPC_FilterValue, 22, 27, 0, 0, // Skip to: 131 +/* 104 */ MCD_OPC_CheckPredicate, 76, 12, 0, 0, // Skip to: 121 +/* 109 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 121 +/* 116 */ MCD_OPC_Decode, 138, 8, 235, 2, // Opcode: BLEZC +/* 121 */ MCD_OPC_CheckPredicate, 76, 69, 0, 0, // Skip to: 195 +/* 126 */ MCD_OPC_Decode, 209, 7, 235, 2, // Opcode: BGEC +/* 131 */ MCD_OPC_FilterValue, 23, 27, 0, 0, // Skip to: 163 +/* 136 */ MCD_OPC_CheckPredicate, 76, 12, 0, 0, // Skip to: 153 +/* 141 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 153 +/* 148 */ MCD_OPC_Decode, 236, 7, 236, 2, // Opcode: BGTZC +/* 153 */ MCD_OPC_CheckPredicate, 76, 37, 0, 0, // Skip to: 195 +/* 158 */ MCD_OPC_Decode, 143, 8, 236, 2, // Opcode: BLTC +/* 163 */ MCD_OPC_FilterValue, 24, 27, 0, 0, // Skip to: 195 +/* 168 */ MCD_OPC_CheckPredicate, 76, 12, 0, 0, // Skip to: 185 +/* 173 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 185 +/* 180 */ MCD_OPC_Decode, 189, 8, 237, 2, // Opcode: BNEZALC +/* 185 */ MCD_OPC_CheckPredicate, 76, 5, 0, 0, // Skip to: 195 +/* 190 */ MCD_OPC_Decode, 199, 8, 237, 2, // Opcode: BNVC +/* 195 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMips32r6_64r6_BranchZero32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 18 +/* 8 */ MCD_OPC_CheckPredicate, 85, 20, 0, 0, // Skip to: 33 +/* 13 */ MCD_OPC_Decode, 228, 7, 235, 2, // Opcode: BGEZC64 +/* 18 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 33 +/* 23 */ MCD_OPC_CheckPredicate, 85, 5, 0, 0, // Skip to: 33 +/* 28 */ MCD_OPC_Decode, 162, 8, 236, 2, // Opcode: BLTZC64 +/* 33 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableMips32r6_64r6_GP6432[] = { -/* 0 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... -/* 3 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 22 -/* 7 */ MCD_OPC_CheckPredicate, 39, 30, 0, // Skip to: 41 -/* 11 */ MCD_OPC_CheckField, 26, 6, 0, 24, 0, // Skip to: 41 -/* 17 */ MCD_OPC_Decode, 175, 11, 224, 1, // Opcode: SELEQZ64 -/* 22 */ MCD_OPC_FilterValue, 55, 15, 0, // Skip to: 41 -/* 26 */ MCD_OPC_CheckPredicate, 39, 11, 0, // Skip to: 41 -/* 30 */ MCD_OPC_CheckField, 26, 6, 0, 5, 0, // Skip to: 41 -/* 36 */ MCD_OPC_Decode, 179, 11, 224, 1, // Opcode: SELNEZ64 -/* 41 */ MCD_OPC_Fail, +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 61 +/* 8 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... +/* 11 */ MCD_OPC_FilterValue, 53, 9, 0, 0, // Skip to: 25 +/* 16 */ MCD_OPC_CheckPredicate, 86, 226, 0, 0, // Skip to: 247 +/* 21 */ MCD_OPC_Decode, 251, 20, 23, // Opcode: SELEQZ64 +/* 25 */ MCD_OPC_FilterValue, 55, 9, 0, 0, // Skip to: 39 +/* 30 */ MCD_OPC_CheckPredicate, 86, 212, 0, 0, // Skip to: 247 +/* 35 */ MCD_OPC_Decode, 130, 21, 23, // Opcode: SELNEZ64 +/* 39 */ MCD_OPC_FilterValue, 137, 8, 202, 0, 0, // Skip to: 247 +/* 45 */ MCD_OPC_CheckPredicate, 75, 197, 0, 0, // Skip to: 247 +/* 50 */ MCD_OPC_CheckField, 11, 10, 0, 190, 0, 0, // Skip to: 247 +/* 57 */ MCD_OPC_Decode, 142, 15, 24, // Opcode: JR_HB64_R6 +/* 61 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 76 +/* 66 */ MCD_OPC_CheckPredicate, 85, 176, 0, 0, // Skip to: 247 +/* 71 */ MCD_OPC_Decode, 216, 7, 223, 2, // Opcode: BGEUC64 +/* 76 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 91 +/* 81 */ MCD_OPC_CheckPredicate, 85, 161, 0, 0, // Skip to: 247 +/* 86 */ MCD_OPC_Decode, 150, 8, 224, 2, // Opcode: BLTUC64 +/* 91 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 106 +/* 96 */ MCD_OPC_CheckPredicate, 85, 146, 0, 0, // Skip to: 247 +/* 101 */ MCD_OPC_Decode, 192, 7, 225, 2, // Opcode: BEQC64 +/* 106 */ MCD_OPC_FilterValue, 22, 27, 0, 0, // Skip to: 138 +/* 111 */ MCD_OPC_CheckPredicate, 85, 12, 0, 0, // Skip to: 128 +/* 116 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 128 +/* 123 */ MCD_OPC_Decode, 139, 8, 235, 2, // Opcode: BLEZC64 +/* 128 */ MCD_OPC_CheckPredicate, 85, 114, 0, 0, // Skip to: 247 +/* 133 */ MCD_OPC_Decode, 210, 7, 235, 2, // Opcode: BGEC64 +/* 138 */ MCD_OPC_FilterValue, 23, 27, 0, 0, // Skip to: 170 +/* 143 */ MCD_OPC_CheckPredicate, 85, 12, 0, 0, // Skip to: 160 +/* 148 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 160 +/* 155 */ MCD_OPC_Decode, 237, 7, 236, 2, // Opcode: BGTZC64 +/* 160 */ MCD_OPC_CheckPredicate, 85, 82, 0, 0, // Skip to: 247 +/* 165 */ MCD_OPC_Decode, 144, 8, 236, 2, // Opcode: BLTC64 +/* 170 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 185 +/* 175 */ MCD_OPC_CheckPredicate, 85, 67, 0, 0, // Skip to: 247 +/* 180 */ MCD_OPC_Decode, 174, 8, 237, 2, // Opcode: BNEC64 +/* 185 */ MCD_OPC_FilterValue, 54, 26, 0, 0, // Skip to: 216 +/* 190 */ MCD_OPC_CheckPredicate, 85, 11, 0, 0, // Skip to: 206 +/* 195 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 206 +/* 202 */ MCD_OPC_Decode, 130, 15, 22, // Opcode: JIC64 +/* 206 */ MCD_OPC_CheckPredicate, 85, 36, 0, 0, // Skip to: 247 +/* 211 */ MCD_OPC_Decode, 204, 7, 248, 2, // Opcode: BEQZC64 +/* 216 */ MCD_OPC_FilterValue, 62, 26, 0, 0, // Skip to: 247 +/* 221 */ MCD_OPC_CheckPredicate, 85, 11, 0, 0, // Skip to: 237 +/* 226 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 237 +/* 233 */ MCD_OPC_Decode, 255, 14, 22, // Opcode: JIALC64 +/* 237 */ MCD_OPC_CheckPredicate, 85, 5, 0, 0, // Skip to: 247 +/* 242 */ MCD_OPC_Decode, 194, 8, 248, 2, // Opcode: BNEZC64 +/* 247 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMips32r6_64r6_PTR6432[] = { +/* 0 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 3 */ MCD_OPC_FilterValue, 38, 17, 0, 0, // Skip to: 25 +/* 8 */ MCD_OPC_CheckPredicate, 87, 34, 0, 0, // Skip to: 47 +/* 13 */ MCD_OPC_CheckField, 26, 6, 31, 27, 0, 0, // Skip to: 47 +/* 20 */ MCD_OPC_Decode, 208, 20, 243, 2, // Opcode: SC64_R6 +/* 25 */ MCD_OPC_FilterValue, 54, 17, 0, 0, // Skip to: 47 +/* 30 */ MCD_OPC_CheckPredicate, 87, 12, 0, 0, // Skip to: 47 +/* 35 */ MCD_OPC_CheckField, 26, 6, 31, 5, 0, 0, // Skip to: 47 +/* 42 */ MCD_OPC_Decode, 237, 15, 243, 2, // Opcode: LL64_R6 +/* 47 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableMips6432[] = { /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 0, 112, 1, // Skip to: 375 -/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 10 */ MCD_OPC_FilterValue, 20, 15, 0, // Skip to: 29 -/* 14 */ MCD_OPC_CheckPredicate, 19, 42, 9, // Skip to: 2364 -/* 18 */ MCD_OPC_CheckField, 6, 5, 0, 36, 9, // Skip to: 2364 -/* 24 */ MCD_OPC_Decode, 255, 4, 252, 1, // Opcode: DSLLV -/* 29 */ MCD_OPC_FilterValue, 22, 29, 0, // Skip to: 62 -/* 33 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 36 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 49 -/* 40 */ MCD_OPC_CheckPredicate, 19, 16, 9, // Skip to: 2364 -/* 44 */ MCD_OPC_Decode, 133, 5, 252, 1, // Opcode: DSRLV -/* 49 */ MCD_OPC_FilterValue, 1, 7, 9, // Skip to: 2364 -/* 53 */ MCD_OPC_CheckPredicate, 40, 3, 9, // Skip to: 2364 -/* 57 */ MCD_OPC_Decode, 248, 4, 252, 1, // Opcode: DROTRV -/* 62 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 81 -/* 66 */ MCD_OPC_CheckPredicate, 19, 246, 8, // Skip to: 2364 -/* 70 */ MCD_OPC_CheckField, 6, 5, 0, 240, 8, // Skip to: 2364 -/* 76 */ MCD_OPC_Decode, 130, 5, 252, 1, // Opcode: DSRAV -/* 81 */ MCD_OPC_FilterValue, 28, 15, 0, // Skip to: 100 -/* 85 */ MCD_OPC_CheckPredicate, 41, 227, 8, // Skip to: 2364 -/* 89 */ MCD_OPC_CheckField, 6, 10, 0, 221, 8, // Skip to: 2364 -/* 95 */ MCD_OPC_Decode, 207, 4, 253, 1, // Opcode: DMULT -/* 100 */ MCD_OPC_FilterValue, 29, 15, 0, // Skip to: 119 -/* 104 */ MCD_OPC_CheckPredicate, 41, 208, 8, // Skip to: 2364 -/* 108 */ MCD_OPC_CheckField, 6, 10, 0, 202, 8, // Skip to: 2364 -/* 114 */ MCD_OPC_Decode, 208, 4, 253, 1, // Opcode: DMULTu -/* 119 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 138 -/* 123 */ MCD_OPC_CheckPredicate, 41, 189, 8, // Skip to: 2364 -/* 127 */ MCD_OPC_CheckField, 6, 10, 0, 183, 8, // Skip to: 2364 -/* 133 */ MCD_OPC_Decode, 250, 4, 253, 1, // Opcode: DSDIV -/* 138 */ MCD_OPC_FilterValue, 31, 15, 0, // Skip to: 157 -/* 142 */ MCD_OPC_CheckPredicate, 41, 170, 8, // Skip to: 2364 -/* 146 */ MCD_OPC_CheckField, 6, 10, 0, 164, 8, // Skip to: 2364 -/* 152 */ MCD_OPC_Decode, 136, 5, 253, 1, // Opcode: DUDIV -/* 157 */ MCD_OPC_FilterValue, 44, 15, 0, // Skip to: 176 -/* 161 */ MCD_OPC_CheckPredicate, 19, 151, 8, // Skip to: 2364 -/* 165 */ MCD_OPC_CheckField, 6, 5, 0, 145, 8, // Skip to: 2364 -/* 171 */ MCD_OPC_Decode, 159, 4, 224, 1, // Opcode: DADD -/* 176 */ MCD_OPC_FilterValue, 45, 15, 0, // Skip to: 195 -/* 180 */ MCD_OPC_CheckPredicate, 19, 132, 8, // Skip to: 2364 -/* 184 */ MCD_OPC_CheckField, 6, 5, 0, 126, 8, // Skip to: 2364 -/* 190 */ MCD_OPC_Decode, 162, 4, 224, 1, // Opcode: DADDu -/* 195 */ MCD_OPC_FilterValue, 46, 15, 0, // Skip to: 214 -/* 199 */ MCD_OPC_CheckPredicate, 19, 113, 8, // Skip to: 2364 -/* 203 */ MCD_OPC_CheckField, 6, 5, 0, 107, 8, // Skip to: 2364 -/* 209 */ MCD_OPC_Decode, 134, 5, 224, 1, // Opcode: DSUB -/* 214 */ MCD_OPC_FilterValue, 47, 15, 0, // Skip to: 233 -/* 218 */ MCD_OPC_CheckPredicate, 19, 94, 8, // Skip to: 2364 -/* 222 */ MCD_OPC_CheckField, 6, 5, 0, 88, 8, // Skip to: 2364 -/* 228 */ MCD_OPC_Decode, 135, 5, 224, 1, // Opcode: DSUBu -/* 233 */ MCD_OPC_FilterValue, 56, 15, 0, // Skip to: 252 -/* 237 */ MCD_OPC_CheckPredicate, 19, 75, 8, // Skip to: 2364 -/* 241 */ MCD_OPC_CheckField, 21, 5, 0, 69, 8, // Skip to: 2364 -/* 247 */ MCD_OPC_Decode, 252, 4, 254, 1, // Opcode: DSLL -/* 252 */ MCD_OPC_FilterValue, 58, 29, 0, // Skip to: 285 -/* 256 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 259 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 272 -/* 263 */ MCD_OPC_CheckPredicate, 19, 49, 8, // Skip to: 2364 -/* 267 */ MCD_OPC_Decode, 131, 5, 254, 1, // Opcode: DSRL -/* 272 */ MCD_OPC_FilterValue, 1, 40, 8, // Skip to: 2364 -/* 276 */ MCD_OPC_CheckPredicate, 40, 36, 8, // Skip to: 2364 -/* 280 */ MCD_OPC_Decode, 246, 4, 254, 1, // Opcode: DROTR -/* 285 */ MCD_OPC_FilterValue, 59, 15, 0, // Skip to: 304 -/* 289 */ MCD_OPC_CheckPredicate, 19, 23, 8, // Skip to: 2364 -/* 293 */ MCD_OPC_CheckField, 21, 5, 0, 17, 8, // Skip to: 2364 -/* 299 */ MCD_OPC_Decode, 128, 5, 254, 1, // Opcode: DSRA -/* 304 */ MCD_OPC_FilterValue, 60, 15, 0, // Skip to: 323 -/* 308 */ MCD_OPC_CheckPredicate, 19, 4, 8, // Skip to: 2364 -/* 312 */ MCD_OPC_CheckField, 21, 5, 0, 254, 7, // Skip to: 2364 -/* 318 */ MCD_OPC_Decode, 253, 4, 254, 1, // Opcode: DSLL32 -/* 323 */ MCD_OPC_FilterValue, 62, 29, 0, // Skip to: 356 -/* 327 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 330 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 343 -/* 334 */ MCD_OPC_CheckPredicate, 19, 234, 7, // Skip to: 2364 -/* 338 */ MCD_OPC_Decode, 132, 5, 254, 1, // Opcode: DSRL32 -/* 343 */ MCD_OPC_FilterValue, 1, 225, 7, // Skip to: 2364 -/* 347 */ MCD_OPC_CheckPredicate, 40, 221, 7, // Skip to: 2364 -/* 351 */ MCD_OPC_Decode, 247, 4, 254, 1, // Opcode: DROTR32 -/* 356 */ MCD_OPC_FilterValue, 63, 212, 7, // Skip to: 2364 -/* 360 */ MCD_OPC_CheckPredicate, 19, 208, 7, // Skip to: 2364 -/* 364 */ MCD_OPC_CheckField, 21, 5, 0, 202, 7, // Skip to: 2364 -/* 370 */ MCD_OPC_Decode, 129, 5, 254, 1, // Opcode: DSRA32 -/* 375 */ MCD_OPC_FilterValue, 16, 41, 0, // Skip to: 420 -/* 379 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 382 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 401 -/* 386 */ MCD_OPC_CheckPredicate, 42, 182, 7, // Skip to: 2364 -/* 390 */ MCD_OPC_CheckField, 3, 8, 0, 176, 7, // Skip to: 2364 -/* 396 */ MCD_OPC_Decode, 196, 4, 255, 1, // Opcode: DMFC0 -/* 401 */ MCD_OPC_FilterValue, 5, 167, 7, // Skip to: 2364 -/* 405 */ MCD_OPC_CheckPredicate, 42, 163, 7, // Skip to: 2364 -/* 409 */ MCD_OPC_CheckField, 3, 8, 0, 157, 7, // Skip to: 2364 -/* 415 */ MCD_OPC_Decode, 201, 4, 255, 1, // Opcode: DMTC0 -/* 420 */ MCD_OPC_FilterValue, 17, 222, 3, // Skip to: 1414 -/* 424 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 427 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 485 -/* 431 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 434 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 453 -/* 438 */ MCD_OPC_CheckPredicate, 43, 130, 7, // Skip to: 2364 -/* 442 */ MCD_OPC_CheckField, 6, 5, 0, 124, 7, // Skip to: 2364 -/* 448 */ MCD_OPC_Decode, 184, 8, 128, 2, // Opcode: MFHC1_D64 -/* 453 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 472 -/* 457 */ MCD_OPC_CheckPredicate, 43, 111, 7, // Skip to: 2364 -/* 461 */ MCD_OPC_CheckField, 6, 5, 0, 105, 7, // Skip to: 2364 -/* 467 */ MCD_OPC_Decode, 174, 9, 129, 2, // Opcode: MTHC1_D64 -/* 472 */ MCD_OPC_FilterValue, 17, 96, 7, // Skip to: 2364 -/* 476 */ MCD_OPC_CheckPredicate, 44, 92, 7, // Skip to: 2364 -/* 480 */ MCD_OPC_Decode, 172, 5, 233, 1, // Opcode: FADD_D64 -/* 485 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 504 -/* 489 */ MCD_OPC_CheckPredicate, 44, 79, 7, // Skip to: 2364 -/* 493 */ MCD_OPC_CheckField, 21, 5, 17, 73, 7, // Skip to: 2364 -/* 499 */ MCD_OPC_Decode, 174, 6, 233, 1, // Opcode: FSUB_D64 -/* 504 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 523 -/* 508 */ MCD_OPC_CheckPredicate, 44, 60, 7, // Skip to: 2364 -/* 512 */ MCD_OPC_CheckField, 21, 5, 17, 54, 7, // Skip to: 2364 -/* 518 */ MCD_OPC_Decode, 137, 6, 233, 1, // Opcode: FMUL_D64 -/* 523 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 542 -/* 527 */ MCD_OPC_CheckPredicate, 44, 41, 7, // Skip to: 2364 -/* 531 */ MCD_OPC_CheckField, 21, 5, 17, 35, 7, // Skip to: 2364 -/* 537 */ MCD_OPC_Decode, 208, 5, 233, 1, // Opcode: FDIV_D64 -/* 542 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 561 -/* 546 */ MCD_OPC_CheckPredicate, 45, 22, 7, // Skip to: 2364 -/* 550 */ MCD_OPC_CheckField, 16, 10, 160, 4, 15, 7, // Skip to: 2364 -/* 557 */ MCD_OPC_Decode, 167, 6, 105, // Opcode: FSQRT_D64 -/* 561 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 580 -/* 565 */ MCD_OPC_CheckPredicate, 44, 3, 7, // Skip to: 2364 -/* 569 */ MCD_OPC_CheckField, 16, 10, 160, 4, 252, 6, // Skip to: 2364 -/* 576 */ MCD_OPC_Decode, 165, 5, 105, // Opcode: FABS_D64 -/* 580 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 599 -/* 584 */ MCD_OPC_CheckPredicate, 44, 240, 6, // Skip to: 2364 -/* 588 */ MCD_OPC_CheckField, 16, 10, 160, 4, 233, 6, // Skip to: 2364 -/* 595 */ MCD_OPC_Decode, 130, 6, 105, // Opcode: FMOV_D64 -/* 599 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 618 -/* 603 */ MCD_OPC_CheckPredicate, 44, 221, 6, // Skip to: 2364 -/* 607 */ MCD_OPC_CheckField, 16, 10, 160, 4, 214, 6, // Skip to: 2364 -/* 614 */ MCD_OPC_Decode, 143, 6, 105, // Opcode: FNEG_D64 -/* 618 */ MCD_OPC_FilterValue, 8, 29, 0, // Skip to: 651 -/* 622 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 625 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 638 -/* 630 */ MCD_OPC_CheckPredicate, 44, 194, 6, // Skip to: 2364 -/* 634 */ MCD_OPC_Decode, 252, 10, 98, // Opcode: ROUND_L_S -/* 638 */ MCD_OPC_FilterValue, 160, 4, 185, 6, // Skip to: 2364 -/* 643 */ MCD_OPC_CheckPredicate, 44, 181, 6, // Skip to: 2364 -/* 647 */ MCD_OPC_Decode, 251, 10, 105, // Opcode: ROUND_L_D64 -/* 651 */ MCD_OPC_FilterValue, 9, 29, 0, // Skip to: 684 -/* 655 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 658 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 671 -/* 663 */ MCD_OPC_CheckPredicate, 44, 161, 6, // Skip to: 2364 -/* 667 */ MCD_OPC_Decode, 215, 13, 98, // Opcode: TRUNC_L_S -/* 671 */ MCD_OPC_FilterValue, 160, 4, 152, 6, // Skip to: 2364 -/* 676 */ MCD_OPC_CheckPredicate, 44, 148, 6, // Skip to: 2364 -/* 680 */ MCD_OPC_Decode, 214, 13, 105, // Opcode: TRUNC_L_D64 -/* 684 */ MCD_OPC_FilterValue, 10, 29, 0, // Skip to: 717 -/* 688 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 691 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 704 -/* 696 */ MCD_OPC_CheckPredicate, 44, 128, 6, // Skip to: 2364 -/* 700 */ MCD_OPC_Decode, 224, 2, 98, // Opcode: CEIL_L_S -/* 704 */ MCD_OPC_FilterValue, 160, 4, 119, 6, // Skip to: 2364 -/* 709 */ MCD_OPC_CheckPredicate, 44, 115, 6, // Skip to: 2364 -/* 713 */ MCD_OPC_Decode, 223, 2, 105, // Opcode: CEIL_L_D64 -/* 717 */ MCD_OPC_FilterValue, 11, 29, 0, // Skip to: 750 -/* 721 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 724 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 737 -/* 729 */ MCD_OPC_CheckPredicate, 44, 95, 6, // Skip to: 2364 -/* 733 */ MCD_OPC_Decode, 240, 5, 98, // Opcode: FLOOR_L_S -/* 737 */ MCD_OPC_FilterValue, 160, 4, 86, 6, // Skip to: 2364 -/* 742 */ MCD_OPC_CheckPredicate, 44, 82, 6, // Skip to: 2364 -/* 746 */ MCD_OPC_Decode, 239, 5, 105, // Opcode: FLOOR_L_D64 -/* 750 */ MCD_OPC_FilterValue, 12, 16, 0, // Skip to: 770 -/* 754 */ MCD_OPC_CheckPredicate, 45, 70, 6, // Skip to: 2364 -/* 758 */ MCD_OPC_CheckField, 16, 10, 160, 4, 63, 6, // Skip to: 2364 -/* 765 */ MCD_OPC_Decode, 254, 10, 130, 2, // Opcode: ROUND_W_D64 -/* 770 */ MCD_OPC_FilterValue, 13, 16, 0, // Skip to: 790 -/* 774 */ MCD_OPC_CheckPredicate, 45, 50, 6, // Skip to: 2364 -/* 778 */ MCD_OPC_CheckField, 16, 10, 160, 4, 43, 6, // Skip to: 2364 -/* 785 */ MCD_OPC_Decode, 217, 13, 130, 2, // Opcode: TRUNC_W_D64 -/* 790 */ MCD_OPC_FilterValue, 14, 16, 0, // Skip to: 810 -/* 794 */ MCD_OPC_CheckPredicate, 45, 30, 6, // Skip to: 2364 -/* 798 */ MCD_OPC_CheckField, 16, 10, 160, 4, 23, 6, // Skip to: 2364 -/* 805 */ MCD_OPC_Decode, 226, 2, 130, 2, // Opcode: CEIL_W_D64 -/* 810 */ MCD_OPC_FilterValue, 15, 16, 0, // Skip to: 830 -/* 814 */ MCD_OPC_CheckPredicate, 45, 10, 6, // Skip to: 2364 -/* 818 */ MCD_OPC_CheckField, 16, 10, 160, 4, 3, 6, // Skip to: 2364 -/* 825 */ MCD_OPC_Decode, 242, 5, 130, 2, // Opcode: FLOOR_W_D64 -/* 830 */ MCD_OPC_FilterValue, 17, 41, 0, // Skip to: 875 -/* 834 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 837 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 856 -/* 841 */ MCD_OPC_CheckPredicate, 46, 239, 5, // Skip to: 2364 -/* 845 */ MCD_OPC_CheckField, 21, 5, 17, 233, 5, // Skip to: 2364 -/* 851 */ MCD_OPC_Decode, 238, 8, 131, 2, // Opcode: MOVF_D64 -/* 856 */ MCD_OPC_FilterValue, 1, 224, 5, // Skip to: 2364 -/* 860 */ MCD_OPC_CheckPredicate, 46, 220, 5, // Skip to: 2364 -/* 864 */ MCD_OPC_CheckField, 21, 5, 17, 214, 5, // Skip to: 2364 -/* 870 */ MCD_OPC_Decode, 130, 9, 131, 2, // Opcode: MOVT_D64 -/* 875 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 894 -/* 879 */ MCD_OPC_CheckPredicate, 46, 201, 5, // Skip to: 2364 -/* 883 */ MCD_OPC_CheckField, 21, 5, 17, 195, 5, // Skip to: 2364 -/* 889 */ MCD_OPC_Decode, 142, 9, 132, 2, // Opcode: MOVZ_I_D64 -/* 894 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 913 -/* 898 */ MCD_OPC_CheckPredicate, 46, 182, 5, // Skip to: 2364 -/* 902 */ MCD_OPC_CheckField, 21, 5, 17, 176, 5, // Skip to: 2364 -/* 908 */ MCD_OPC_Decode, 250, 8, 132, 2, // Opcode: MOVN_I_D64 -/* 913 */ MCD_OPC_FilterValue, 32, 31, 0, // Skip to: 948 -/* 917 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 920 */ MCD_OPC_FilterValue, 160, 4, 9, 0, // Skip to: 934 -/* 925 */ MCD_OPC_CheckPredicate, 44, 155, 5, // Skip to: 2364 -/* 929 */ MCD_OPC_Decode, 226, 3, 130, 2, // Opcode: CVT_S_D64 -/* 934 */ MCD_OPC_FilterValue, 160, 5, 145, 5, // Skip to: 2364 -/* 939 */ MCD_OPC_CheckPredicate, 44, 141, 5, // Skip to: 2364 -/* 943 */ MCD_OPC_Decode, 227, 3, 130, 2, // Opcode: CVT_S_L -/* 948 */ MCD_OPC_FilterValue, 33, 42, 0, // Skip to: 994 -/* 952 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 955 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 968 -/* 960 */ MCD_OPC_CheckPredicate, 44, 120, 5, // Skip to: 2364 -/* 964 */ MCD_OPC_Decode, 217, 3, 98, // Opcode: CVT_D64_S -/* 968 */ MCD_OPC_FilterValue, 128, 5, 8, 0, // Skip to: 981 -/* 973 */ MCD_OPC_CheckPredicate, 44, 107, 5, // Skip to: 2364 -/* 977 */ MCD_OPC_Decode, 218, 3, 98, // Opcode: CVT_D64_W -/* 981 */ MCD_OPC_FilterValue, 160, 5, 98, 5, // Skip to: 2364 -/* 986 */ MCD_OPC_CheckPredicate, 44, 94, 5, // Skip to: 2364 -/* 990 */ MCD_OPC_Decode, 216, 3, 105, // Opcode: CVT_D64_L -/* 994 */ MCD_OPC_FilterValue, 36, 16, 0, // Skip to: 1014 -/* 998 */ MCD_OPC_CheckPredicate, 44, 82, 5, // Skip to: 2364 -/* 1002 */ MCD_OPC_CheckField, 16, 10, 160, 4, 75, 5, // Skip to: 2364 -/* 1009 */ MCD_OPC_Decode, 231, 3, 130, 2, // Opcode: CVT_W_D64 -/* 1014 */ MCD_OPC_FilterValue, 48, 21, 0, // Skip to: 1039 -/* 1018 */ MCD_OPC_CheckPredicate, 47, 62, 5, // Skip to: 2364 -/* 1022 */ MCD_OPC_CheckField, 21, 5, 17, 56, 5, // Skip to: 2364 -/* 1028 */ MCD_OPC_CheckField, 6, 5, 0, 50, 5, // Skip to: 2364 -/* 1034 */ MCD_OPC_Decode, 239, 3, 133, 2, // Opcode: C_F_D64 -/* 1039 */ MCD_OPC_FilterValue, 49, 21, 0, // Skip to: 1064 -/* 1043 */ MCD_OPC_CheckPredicate, 47, 37, 5, // Skip to: 2364 -/* 1047 */ MCD_OPC_CheckField, 21, 5, 17, 31, 5, // Skip to: 2364 -/* 1053 */ MCD_OPC_CheckField, 6, 5, 0, 25, 5, // Skip to: 2364 -/* 1059 */ MCD_OPC_Decode, 153, 4, 133, 2, // Opcode: C_UN_D64 -/* 1064 */ MCD_OPC_FilterValue, 50, 21, 0, // Skip to: 1089 -/* 1068 */ MCD_OPC_CheckPredicate, 47, 12, 5, // Skip to: 2364 -/* 1072 */ MCD_OPC_CheckField, 21, 5, 17, 6, 5, // Skip to: 2364 -/* 1078 */ MCD_OPC_CheckField, 6, 5, 0, 0, 5, // Skip to: 2364 -/* 1084 */ MCD_OPC_Decode, 236, 3, 133, 2, // Opcode: C_EQ_D64 -/* 1089 */ MCD_OPC_FilterValue, 51, 21, 0, // Skip to: 1114 -/* 1093 */ MCD_OPC_CheckPredicate, 47, 243, 4, // Skip to: 2364 -/* 1097 */ MCD_OPC_CheckField, 21, 5, 17, 237, 4, // Skip to: 2364 -/* 1103 */ MCD_OPC_CheckField, 6, 5, 0, 231, 4, // Skip to: 2364 -/* 1109 */ MCD_OPC_Decode, 144, 4, 133, 2, // Opcode: C_UEQ_D64 -/* 1114 */ MCD_OPC_FilterValue, 52, 21, 0, // Skip to: 1139 -/* 1118 */ MCD_OPC_CheckPredicate, 47, 218, 4, // Skip to: 2364 -/* 1122 */ MCD_OPC_CheckField, 21, 5, 17, 212, 4, // Skip to: 2364 -/* 1128 */ MCD_OPC_CheckField, 6, 5, 0, 206, 4, // Skip to: 2364 -/* 1134 */ MCD_OPC_Decode, 135, 4, 133, 2, // Opcode: C_OLT_D64 -/* 1139 */ MCD_OPC_FilterValue, 53, 21, 0, // Skip to: 1164 -/* 1143 */ MCD_OPC_CheckPredicate, 47, 193, 4, // Skip to: 2364 -/* 1147 */ MCD_OPC_CheckField, 21, 5, 17, 187, 4, // Skip to: 2364 -/* 1153 */ MCD_OPC_CheckField, 6, 5, 0, 181, 4, // Skip to: 2364 -/* 1159 */ MCD_OPC_Decode, 150, 4, 133, 2, // Opcode: C_ULT_D64 -/* 1164 */ MCD_OPC_FilterValue, 54, 21, 0, // Skip to: 1189 -/* 1168 */ MCD_OPC_CheckPredicate, 47, 168, 4, // Skip to: 2364 -/* 1172 */ MCD_OPC_CheckField, 21, 5, 17, 162, 4, // Skip to: 2364 -/* 1178 */ MCD_OPC_CheckField, 6, 5, 0, 156, 4, // Skip to: 2364 -/* 1184 */ MCD_OPC_Decode, 132, 4, 133, 2, // Opcode: C_OLE_D64 -/* 1189 */ MCD_OPC_FilterValue, 55, 21, 0, // Skip to: 1214 -/* 1193 */ MCD_OPC_CheckPredicate, 47, 143, 4, // Skip to: 2364 -/* 1197 */ MCD_OPC_CheckField, 21, 5, 17, 137, 4, // Skip to: 2364 -/* 1203 */ MCD_OPC_CheckField, 6, 5, 0, 131, 4, // Skip to: 2364 -/* 1209 */ MCD_OPC_Decode, 147, 4, 133, 2, // Opcode: C_ULE_D64 -/* 1214 */ MCD_OPC_FilterValue, 56, 21, 0, // Skip to: 1239 -/* 1218 */ MCD_OPC_CheckPredicate, 47, 118, 4, // Skip to: 2364 -/* 1222 */ MCD_OPC_CheckField, 21, 5, 17, 112, 4, // Skip to: 2364 -/* 1228 */ MCD_OPC_CheckField, 6, 5, 0, 106, 4, // Skip to: 2364 -/* 1234 */ MCD_OPC_Decode, 141, 4, 133, 2, // Opcode: C_SF_D64 -/* 1239 */ MCD_OPC_FilterValue, 57, 21, 0, // Skip to: 1264 -/* 1243 */ MCD_OPC_CheckPredicate, 47, 93, 4, // Skip to: 2364 -/* 1247 */ MCD_OPC_CheckField, 21, 5, 17, 87, 4, // Skip to: 2364 -/* 1253 */ MCD_OPC_CheckField, 6, 5, 0, 81, 4, // Skip to: 2364 -/* 1259 */ MCD_OPC_Decode, 251, 3, 133, 2, // Opcode: C_NGLE_D64 -/* 1264 */ MCD_OPC_FilterValue, 58, 21, 0, // Skip to: 1289 -/* 1268 */ MCD_OPC_CheckPredicate, 47, 68, 4, // Skip to: 2364 -/* 1272 */ MCD_OPC_CheckField, 21, 5, 17, 62, 4, // Skip to: 2364 -/* 1278 */ MCD_OPC_CheckField, 6, 5, 0, 56, 4, // Skip to: 2364 -/* 1284 */ MCD_OPC_Decode, 138, 4, 133, 2, // Opcode: C_SEQ_D64 -/* 1289 */ MCD_OPC_FilterValue, 59, 21, 0, // Skip to: 1314 -/* 1293 */ MCD_OPC_CheckPredicate, 47, 43, 4, // Skip to: 2364 -/* 1297 */ MCD_OPC_CheckField, 21, 5, 17, 37, 4, // Skip to: 2364 -/* 1303 */ MCD_OPC_CheckField, 6, 5, 0, 31, 4, // Skip to: 2364 -/* 1309 */ MCD_OPC_Decode, 254, 3, 133, 2, // Opcode: C_NGL_D64 -/* 1314 */ MCD_OPC_FilterValue, 60, 21, 0, // Skip to: 1339 -/* 1318 */ MCD_OPC_CheckPredicate, 47, 18, 4, // Skip to: 2364 -/* 1322 */ MCD_OPC_CheckField, 21, 5, 17, 12, 4, // Skip to: 2364 -/* 1328 */ MCD_OPC_CheckField, 6, 5, 0, 6, 4, // Skip to: 2364 -/* 1334 */ MCD_OPC_Decode, 245, 3, 133, 2, // Opcode: C_LT_D64 -/* 1339 */ MCD_OPC_FilterValue, 61, 21, 0, // Skip to: 1364 -/* 1343 */ MCD_OPC_CheckPredicate, 47, 249, 3, // Skip to: 2364 -/* 1347 */ MCD_OPC_CheckField, 21, 5, 17, 243, 3, // Skip to: 2364 -/* 1353 */ MCD_OPC_CheckField, 6, 5, 0, 237, 3, // Skip to: 2364 -/* 1359 */ MCD_OPC_Decode, 248, 3, 133, 2, // Opcode: C_NGE_D64 -/* 1364 */ MCD_OPC_FilterValue, 62, 21, 0, // Skip to: 1389 -/* 1368 */ MCD_OPC_CheckPredicate, 47, 224, 3, // Skip to: 2364 -/* 1372 */ MCD_OPC_CheckField, 21, 5, 17, 218, 3, // Skip to: 2364 -/* 1378 */ MCD_OPC_CheckField, 6, 5, 0, 212, 3, // Skip to: 2364 -/* 1384 */ MCD_OPC_Decode, 242, 3, 133, 2, // Opcode: C_LE_D64 -/* 1389 */ MCD_OPC_FilterValue, 63, 203, 3, // Skip to: 2364 -/* 1393 */ MCD_OPC_CheckPredicate, 47, 199, 3, // Skip to: 2364 -/* 1397 */ MCD_OPC_CheckField, 21, 5, 17, 193, 3, // Skip to: 2364 -/* 1403 */ MCD_OPC_CheckField, 6, 5, 0, 187, 3, // Skip to: 2364 -/* 1409 */ MCD_OPC_Decode, 129, 4, 133, 2, // Opcode: C_NGT_D64 -/* 1414 */ MCD_OPC_FilterValue, 18, 41, 0, // Skip to: 1459 -/* 1418 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1421 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1440 -/* 1425 */ MCD_OPC_CheckPredicate, 42, 167, 3, // Skip to: 2364 -/* 1429 */ MCD_OPC_CheckField, 3, 8, 0, 161, 3, // Skip to: 2364 -/* 1435 */ MCD_OPC_Decode, 198, 4, 255, 1, // Opcode: DMFC2 -/* 1440 */ MCD_OPC_FilterValue, 5, 152, 3, // Skip to: 2364 -/* 1444 */ MCD_OPC_CheckPredicate, 42, 148, 3, // Skip to: 2364 -/* 1448 */ MCD_OPC_CheckField, 3, 8, 0, 142, 3, // Skip to: 2364 -/* 1454 */ MCD_OPC_Decode, 203, 4, 255, 1, // Opcode: DMTC2 -/* 1459 */ MCD_OPC_FilterValue, 19, 131, 0, // Skip to: 1594 -/* 1463 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1466 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1485 -/* 1470 */ MCD_OPC_CheckPredicate, 48, 122, 3, // Skip to: 2364 -/* 1474 */ MCD_OPC_CheckField, 11, 5, 0, 116, 3, // Skip to: 2364 -/* 1480 */ MCD_OPC_Decode, 176, 7, 134, 2, // Opcode: LDXC164 -/* 1485 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 1504 -/* 1489 */ MCD_OPC_CheckPredicate, 49, 103, 3, // Skip to: 2364 -/* 1493 */ MCD_OPC_CheckField, 11, 5, 0, 97, 3, // Skip to: 2364 -/* 1499 */ MCD_OPC_Decode, 208, 7, 134, 2, // Opcode: LUXC164 -/* 1504 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 1523 -/* 1508 */ MCD_OPC_CheckPredicate, 48, 84, 3, // Skip to: 2364 -/* 1512 */ MCD_OPC_CheckField, 6, 5, 0, 78, 3, // Skip to: 2364 -/* 1518 */ MCD_OPC_Decode, 167, 11, 135, 2, // Opcode: SDXC164 -/* 1523 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 1542 -/* 1527 */ MCD_OPC_CheckPredicate, 49, 65, 3, // Skip to: 2364 -/* 1531 */ MCD_OPC_CheckField, 6, 5, 0, 59, 3, // Skip to: 2364 -/* 1537 */ MCD_OPC_Decode, 233, 12, 135, 2, // Opcode: SUXC164 -/* 1542 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 1555 -/* 1546 */ MCD_OPC_CheckPredicate, 48, 46, 3, // Skip to: 2364 -/* 1550 */ MCD_OPC_Decode, 144, 8, 136, 2, // Opcode: MADD_D64 -/* 1555 */ MCD_OPC_FilterValue, 41, 9, 0, // Skip to: 1568 -/* 1559 */ MCD_OPC_CheckPredicate, 48, 33, 3, // Skip to: 2364 -/* 1563 */ MCD_OPC_Decode, 162, 9, 136, 2, // Opcode: MSUB_D64 -/* 1568 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 1581 -/* 1572 */ MCD_OPC_CheckPredicate, 48, 20, 3, // Skip to: 2364 -/* 1576 */ MCD_OPC_Decode, 241, 9, 136, 2, // Opcode: NMADD_D64 -/* 1581 */ MCD_OPC_FilterValue, 57, 11, 3, // Skip to: 2364 -/* 1585 */ MCD_OPC_CheckPredicate, 48, 7, 3, // Skip to: 2364 -/* 1589 */ MCD_OPC_Decode, 246, 9, 136, 2, // Opcode: NMSUB_D64 -/* 1594 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 1607 -/* 1598 */ MCD_OPC_CheckPredicate, 41, 250, 2, // Skip to: 2364 -/* 1602 */ MCD_OPC_Decode, 160, 4, 137, 2, // Opcode: DADDi -/* 1607 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 1620 -/* 1611 */ MCD_OPC_CheckPredicate, 19, 237, 2, // Skip to: 2364 -/* 1615 */ MCD_OPC_Decode, 161, 4, 137, 2, // Opcode: DADDiu -/* 1620 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 1633 -/* 1624 */ MCD_OPC_CheckPredicate, 41, 224, 2, // Skip to: 2364 -/* 1628 */ MCD_OPC_Decode, 172, 7, 217, 1, // Opcode: LDL -/* 1633 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 1646 -/* 1637 */ MCD_OPC_CheckPredicate, 41, 211, 2, // Skip to: 2364 -/* 1641 */ MCD_OPC_Decode, 174, 7, 217, 1, // Opcode: LDR -/* 1646 */ MCD_OPC_FilterValue, 28, 159, 1, // Skip to: 2065 -/* 1650 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1653 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 1672 -/* 1657 */ MCD_OPC_CheckPredicate, 50, 191, 2, // Skip to: 2364 -/* 1661 */ MCD_OPC_CheckField, 6, 5, 0, 185, 2, // Skip to: 2364 -/* 1667 */ MCD_OPC_Decode, 206, 4, 224, 1, // Opcode: DMUL -/* 1672 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 1691 -/* 1676 */ MCD_OPC_CheckPredicate, 50, 172, 2, // Skip to: 2364 -/* 1680 */ MCD_OPC_CheckField, 6, 15, 0, 166, 2, // Skip to: 2364 -/* 1686 */ MCD_OPC_Decode, 185, 9, 138, 2, // Opcode: MTM0 -/* 1691 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 1710 -/* 1695 */ MCD_OPC_CheckPredicate, 50, 153, 2, // Skip to: 2364 -/* 1699 */ MCD_OPC_CheckField, 6, 15, 0, 147, 2, // Skip to: 2364 -/* 1705 */ MCD_OPC_Decode, 188, 9, 138, 2, // Opcode: MTP0 -/* 1710 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 1729 -/* 1714 */ MCD_OPC_CheckPredicate, 50, 134, 2, // Skip to: 2364 -/* 1718 */ MCD_OPC_CheckField, 6, 15, 0, 128, 2, // Skip to: 2364 -/* 1724 */ MCD_OPC_Decode, 189, 9, 138, 2, // Opcode: MTP1 -/* 1729 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 1748 -/* 1733 */ MCD_OPC_CheckPredicate, 50, 115, 2, // Skip to: 2364 -/* 1737 */ MCD_OPC_CheckField, 6, 15, 0, 109, 2, // Skip to: 2364 -/* 1743 */ MCD_OPC_Decode, 190, 9, 138, 2, // Opcode: MTP2 -/* 1748 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 1767 -/* 1752 */ MCD_OPC_CheckPredicate, 50, 96, 2, // Skip to: 2364 -/* 1756 */ MCD_OPC_CheckField, 6, 15, 0, 90, 2, // Skip to: 2364 -/* 1762 */ MCD_OPC_Decode, 186, 9, 138, 2, // Opcode: MTM1 -/* 1767 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 1786 -/* 1771 */ MCD_OPC_CheckPredicate, 50, 77, 2, // Skip to: 2364 -/* 1775 */ MCD_OPC_CheckField, 6, 15, 0, 71, 2, // Skip to: 2364 -/* 1781 */ MCD_OPC_Decode, 187, 9, 138, 2, // Opcode: MTM2 -/* 1786 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 1805 -/* 1790 */ MCD_OPC_CheckPredicate, 50, 58, 2, // Skip to: 2364 -/* 1794 */ MCD_OPC_CheckField, 6, 5, 0, 52, 2, // Skip to: 2364 -/* 1800 */ MCD_OPC_Decode, 226, 13, 224, 1, // Opcode: VMULU -/* 1805 */ MCD_OPC_FilterValue, 16, 15, 0, // Skip to: 1824 -/* 1809 */ MCD_OPC_CheckPredicate, 50, 39, 2, // Skip to: 2364 -/* 1813 */ MCD_OPC_CheckField, 6, 5, 0, 33, 2, // Skip to: 2364 -/* 1819 */ MCD_OPC_Decode, 225, 13, 224, 1, // Opcode: VMM0 -/* 1824 */ MCD_OPC_FilterValue, 17, 15, 0, // Skip to: 1843 -/* 1828 */ MCD_OPC_CheckPredicate, 50, 20, 2, // Skip to: 2364 -/* 1832 */ MCD_OPC_CheckField, 6, 5, 0, 14, 2, // Skip to: 2364 -/* 1838 */ MCD_OPC_Decode, 224, 13, 224, 1, // Opcode: V3MULU -/* 1843 */ MCD_OPC_FilterValue, 36, 15, 0, // Skip to: 1862 -/* 1847 */ MCD_OPC_CheckPredicate, 51, 1, 2, // Skip to: 2364 -/* 1851 */ MCD_OPC_CheckField, 6, 5, 0, 251, 1, // Skip to: 2364 -/* 1857 */ MCD_OPC_Decode, 170, 4, 139, 2, // Opcode: DCLZ -/* 1862 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 1881 -/* 1866 */ MCD_OPC_CheckPredicate, 51, 238, 1, // Skip to: 2364 -/* 1870 */ MCD_OPC_CheckField, 6, 5, 0, 232, 1, // Skip to: 2364 -/* 1876 */ MCD_OPC_Decode, 168, 4, 139, 2, // Opcode: DCLO -/* 1881 */ MCD_OPC_FilterValue, 40, 15, 0, // Skip to: 1900 -/* 1885 */ MCD_OPC_CheckPredicate, 50, 219, 1, // Skip to: 2364 -/* 1889 */ MCD_OPC_CheckField, 6, 5, 0, 213, 1, // Skip to: 2364 -/* 1895 */ MCD_OPC_Decode, 166, 1, 224, 1, // Opcode: BADDu -/* 1900 */ MCD_OPC_FilterValue, 42, 15, 0, // Skip to: 1919 -/* 1904 */ MCD_OPC_CheckPredicate, 50, 200, 1, // Skip to: 2364 -/* 1908 */ MCD_OPC_CheckField, 6, 5, 0, 194, 1, // Skip to: 2364 -/* 1914 */ MCD_OPC_Decode, 184, 11, 224, 1, // Opcode: SEQ -/* 1919 */ MCD_OPC_FilterValue, 43, 15, 0, // Skip to: 1938 -/* 1923 */ MCD_OPC_CheckPredicate, 50, 181, 1, // Skip to: 2364 -/* 1927 */ MCD_OPC_CheckField, 6, 5, 0, 175, 1, // Skip to: 2364 -/* 1933 */ MCD_OPC_Decode, 252, 11, 224, 1, // Opcode: SNE -/* 1938 */ MCD_OPC_FilterValue, 44, 20, 0, // Skip to: 1962 -/* 1942 */ MCD_OPC_CheckPredicate, 50, 162, 1, // Skip to: 2364 -/* 1946 */ MCD_OPC_CheckField, 16, 5, 0, 156, 1, // Skip to: 2364 -/* 1952 */ MCD_OPC_CheckField, 6, 5, 0, 150, 1, // Skip to: 2364 -/* 1958 */ MCD_OPC_Decode, 163, 10, 62, // Opcode: POP -/* 1962 */ MCD_OPC_FilterValue, 45, 21, 0, // Skip to: 1987 -/* 1966 */ MCD_OPC_CheckPredicate, 50, 138, 1, // Skip to: 2364 -/* 1970 */ MCD_OPC_CheckField, 16, 5, 0, 132, 1, // Skip to: 2364 -/* 1976 */ MCD_OPC_CheckField, 6, 5, 0, 126, 1, // Skip to: 2364 -/* 1982 */ MCD_OPC_Decode, 231, 4, 222, 1, // Opcode: DPOP -/* 1987 */ MCD_OPC_FilterValue, 46, 9, 0, // Skip to: 2000 -/* 1991 */ MCD_OPC_CheckPredicate, 50, 113, 1, // Skip to: 2364 -/* 1995 */ MCD_OPC_Decode, 185, 11, 140, 2, // Opcode: SEQi -/* 2000 */ MCD_OPC_FilterValue, 47, 9, 0, // Skip to: 2013 -/* 2004 */ MCD_OPC_CheckPredicate, 50, 100, 1, // Skip to: 2364 -/* 2008 */ MCD_OPC_Decode, 253, 11, 140, 2, // Opcode: SNEi -/* 2013 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 2026 -/* 2017 */ MCD_OPC_CheckPredicate, 50, 87, 1, // Skip to: 2364 -/* 2021 */ MCD_OPC_Decode, 241, 2, 141, 2, // Opcode: CINS -/* 2026 */ MCD_OPC_FilterValue, 51, 9, 0, // Skip to: 2039 -/* 2030 */ MCD_OPC_CheckPredicate, 50, 74, 1, // Skip to: 2364 -/* 2034 */ MCD_OPC_Decode, 242, 2, 141, 2, // Opcode: CINS32 -/* 2039 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 2052 -/* 2043 */ MCD_OPC_CheckPredicate, 50, 61, 1, // Skip to: 2364 -/* 2047 */ MCD_OPC_Decode, 158, 5, 141, 2, // Opcode: EXTS -/* 2052 */ MCD_OPC_FilterValue, 59, 52, 1, // Skip to: 2364 -/* 2056 */ MCD_OPC_CheckPredicate, 50, 48, 1, // Skip to: 2364 -/* 2060 */ MCD_OPC_Decode, 159, 5, 141, 2, // Opcode: EXTS32 -/* 2065 */ MCD_OPC_FilterValue, 31, 126, 0, // Skip to: 2195 -/* 2069 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 2072 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 2085 -/* 2076 */ MCD_OPC_CheckPredicate, 6, 28, 1, // Skip to: 2364 -/* 2080 */ MCD_OPC_Decode, 177, 4, 142, 2, // Opcode: DEXTM -/* 2085 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 2098 -/* 2089 */ MCD_OPC_CheckPredicate, 6, 15, 1, // Skip to: 2364 -/* 2093 */ MCD_OPC_Decode, 178, 4, 142, 2, // Opcode: DEXTU -/* 2098 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 2111 -/* 2102 */ MCD_OPC_CheckPredicate, 6, 2, 1, // Skip to: 2364 -/* 2106 */ MCD_OPC_Decode, 176, 4, 142, 2, // Opcode: DEXT -/* 2111 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 2124 -/* 2115 */ MCD_OPC_CheckPredicate, 6, 245, 0, // Skip to: 2364 -/* 2119 */ MCD_OPC_Decode, 181, 4, 143, 2, // Opcode: DINSM -/* 2124 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 2137 -/* 2128 */ MCD_OPC_CheckPredicate, 6, 232, 0, // Skip to: 2364 -/* 2132 */ MCD_OPC_Decode, 182, 4, 143, 2, // Opcode: DINSU -/* 2137 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 2150 -/* 2141 */ MCD_OPC_CheckPredicate, 6, 219, 0, // Skip to: 2364 -/* 2145 */ MCD_OPC_Decode, 180, 4, 143, 2, // Opcode: DINS -/* 2150 */ MCD_OPC_FilterValue, 36, 210, 0, // Skip to: 2364 -/* 2154 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 2157 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 2176 -/* 2161 */ MCD_OPC_CheckPredicate, 40, 199, 0, // Skip to: 2364 -/* 2165 */ MCD_OPC_CheckField, 21, 5, 0, 193, 0, // Skip to: 2364 -/* 2171 */ MCD_OPC_Decode, 249, 4, 243, 1, // Opcode: DSBH -/* 2176 */ MCD_OPC_FilterValue, 5, 184, 0, // Skip to: 2364 -/* 2180 */ MCD_OPC_CheckPredicate, 40, 180, 0, // Skip to: 2364 -/* 2184 */ MCD_OPC_CheckField, 21, 5, 0, 174, 0, // Skip to: 2364 -/* 2190 */ MCD_OPC_Decode, 251, 4, 243, 1, // Opcode: DSHD -/* 2195 */ MCD_OPC_FilterValue, 39, 9, 0, // Skip to: 2208 -/* 2199 */ MCD_OPC_CheckPredicate, 19, 161, 0, // Skip to: 2364 -/* 2203 */ MCD_OPC_Decode, 241, 7, 217, 1, // Opcode: LWu -/* 2208 */ MCD_OPC_FilterValue, 44, 9, 0, // Skip to: 2221 -/* 2212 */ MCD_OPC_CheckPredicate, 41, 148, 0, // Skip to: 2364 -/* 2216 */ MCD_OPC_Decode, 164, 11, 217, 1, // Opcode: SDL -/* 2221 */ MCD_OPC_FilterValue, 45, 9, 0, // Skip to: 2234 -/* 2225 */ MCD_OPC_CheckPredicate, 41, 135, 0, // Skip to: 2364 -/* 2229 */ MCD_OPC_Decode, 165, 11, 217, 1, // Opcode: SDR -/* 2234 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 2247 -/* 2238 */ MCD_OPC_CheckPredicate, 50, 122, 0, // Skip to: 2364 -/* 2242 */ MCD_OPC_Decode, 171, 1, 144, 2, // Opcode: BBIT0 -/* 2247 */ MCD_OPC_FilterValue, 52, 9, 0, // Skip to: 2260 -/* 2251 */ MCD_OPC_CheckPredicate, 41, 109, 0, // Skip to: 2364 -/* 2255 */ MCD_OPC_Decode, 194, 7, 217, 1, // Opcode: LLD -/* 2260 */ MCD_OPC_FilterValue, 53, 9, 0, // Skip to: 2273 -/* 2264 */ MCD_OPC_CheckPredicate, 52, 96, 0, // Skip to: 2364 -/* 2268 */ MCD_OPC_Decode, 163, 7, 219, 1, // Opcode: LDC164 -/* 2273 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 2286 -/* 2277 */ MCD_OPC_CheckPredicate, 50, 83, 0, // Skip to: 2364 -/* 2281 */ MCD_OPC_Decode, 172, 1, 144, 2, // Opcode: BBIT032 -/* 2286 */ MCD_OPC_FilterValue, 55, 9, 0, // Skip to: 2299 -/* 2290 */ MCD_OPC_CheckPredicate, 19, 70, 0, // Skip to: 2364 -/* 2294 */ MCD_OPC_Decode, 161, 7, 217, 1, // Opcode: LD -/* 2299 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 2312 -/* 2303 */ MCD_OPC_CheckPredicate, 50, 57, 0, // Skip to: 2364 -/* 2307 */ MCD_OPC_Decode, 173, 1, 144, 2, // Opcode: BBIT1 -/* 2312 */ MCD_OPC_FilterValue, 60, 9, 0, // Skip to: 2325 -/* 2316 */ MCD_OPC_CheckPredicate, 41, 44, 0, // Skip to: 2364 -/* 2320 */ MCD_OPC_Decode, 147, 11, 217, 1, // Opcode: SCD -/* 2325 */ MCD_OPC_FilterValue, 61, 9, 0, // Skip to: 2338 -/* 2329 */ MCD_OPC_CheckPredicate, 52, 31, 0, // Skip to: 2364 -/* 2333 */ MCD_OPC_Decode, 157, 11, 219, 1, // Opcode: SDC164 -/* 2338 */ MCD_OPC_FilterValue, 62, 9, 0, // Skip to: 2351 -/* 2342 */ MCD_OPC_CheckPredicate, 50, 18, 0, // Skip to: 2364 -/* 2346 */ MCD_OPC_Decode, 174, 1, 144, 2, // Opcode: BBIT132 -/* 2351 */ MCD_OPC_FilterValue, 63, 9, 0, // Skip to: 2364 -/* 2355 */ MCD_OPC_CheckPredicate, 19, 5, 0, // Skip to: 2364 -/* 2359 */ MCD_OPC_Decode, 151, 11, 217, 1, // Opcode: SD -/* 2364 */ MCD_OPC_Fail, +/* 3 */ MCD_OPC_FilterValue, 0, 236, 1, 0, // Skip to: 500 +/* 8 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 11 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 32 +/* 16 */ MCD_OPC_CheckPredicate, 88, 244, 4, 0, // Skip to: 1289 +/* 21 */ MCD_OPC_CheckField, 6, 15, 16, 237, 4, 0, // Skip to: 1289 +/* 28 */ MCD_OPC_Decode, 141, 15, 24, // Opcode: JR_HB64 +/* 32 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 82 +/* 37 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 40 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 61 +/* 45 */ MCD_OPC_CheckPredicate, 89, 215, 4, 0, // Skip to: 1289 +/* 50 */ MCD_OPC_CheckField, 16, 5, 0, 208, 4, 0, // Skip to: 1289 +/* 57 */ MCD_OPC_Decode, 238, 14, 26, // Opcode: JALR64 +/* 61 */ MCD_OPC_FilterValue, 16, 199, 4, 0, // Skip to: 1289 +/* 66 */ MCD_OPC_CheckPredicate, 90, 194, 4, 0, // Skip to: 1289 +/* 71 */ MCD_OPC_CheckField, 16, 5, 0, 187, 4, 0, // Skip to: 1289 +/* 78 */ MCD_OPC_Decode, 248, 14, 26, // Opcode: JALR_HB64 +/* 82 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 104 +/* 87 */ MCD_OPC_CheckPredicate, 91, 173, 4, 0, // Skip to: 1289 +/* 92 */ MCD_OPC_CheckField, 6, 5, 0, 166, 4, 0, // Skip to: 1289 +/* 99 */ MCD_OPC_Decode, 190, 12, 249, 2, // Opcode: DSLLV +/* 104 */ MCD_OPC_FilterValue, 22, 33, 0, 0, // Skip to: 142 +/* 109 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 112 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 127 +/* 117 */ MCD_OPC_CheckPredicate, 91, 143, 4, 0, // Skip to: 1289 +/* 122 */ MCD_OPC_Decode, 196, 12, 249, 2, // Opcode: DSRLV +/* 127 */ MCD_OPC_FilterValue, 1, 133, 4, 0, // Skip to: 1289 +/* 132 */ MCD_OPC_CheckPredicate, 90, 128, 4, 0, // Skip to: 1289 +/* 137 */ MCD_OPC_Decode, 183, 12, 249, 2, // Opcode: DROTRV +/* 142 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 164 +/* 147 */ MCD_OPC_CheckPredicate, 91, 113, 4, 0, // Skip to: 1289 +/* 152 */ MCD_OPC_CheckField, 6, 5, 0, 106, 4, 0, // Skip to: 1289 +/* 159 */ MCD_OPC_Decode, 193, 12, 249, 2, // Opcode: DSRAV +/* 164 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 186 +/* 169 */ MCD_OPC_CheckPredicate, 92, 91, 4, 0, // Skip to: 1289 +/* 174 */ MCD_OPC_CheckField, 6, 10, 0, 84, 4, 0, // Skip to: 1289 +/* 181 */ MCD_OPC_Decode, 254, 11, 250, 2, // Opcode: DMULT +/* 186 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 208 +/* 191 */ MCD_OPC_CheckPredicate, 92, 69, 4, 0, // Skip to: 1289 +/* 196 */ MCD_OPC_CheckField, 6, 10, 0, 62, 4, 0, // Skip to: 1289 +/* 203 */ MCD_OPC_Decode, 255, 11, 250, 2, // Opcode: DMULTu +/* 208 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 230 +/* 213 */ MCD_OPC_CheckPredicate, 92, 47, 4, 0, // Skip to: 1289 +/* 218 */ MCD_OPC_CheckField, 6, 10, 0, 40, 4, 0, // Skip to: 1289 +/* 225 */ MCD_OPC_Decode, 185, 12, 250, 2, // Opcode: DSDIV +/* 230 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 252 +/* 235 */ MCD_OPC_CheckPredicate, 92, 25, 4, 0, // Skip to: 1289 +/* 240 */ MCD_OPC_CheckField, 6, 10, 0, 18, 4, 0, // Skip to: 1289 +/* 247 */ MCD_OPC_Decode, 199, 12, 250, 2, // Opcode: DUDIV +/* 252 */ MCD_OPC_FilterValue, 44, 16, 0, 0, // Skip to: 273 +/* 257 */ MCD_OPC_CheckPredicate, 91, 3, 4, 0, // Skip to: 1289 +/* 262 */ MCD_OPC_CheckField, 6, 5, 0, 252, 3, 0, // Skip to: 1289 +/* 269 */ MCD_OPC_Decode, 191, 11, 23, // Opcode: DADD +/* 273 */ MCD_OPC_FilterValue, 45, 16, 0, 0, // Skip to: 294 +/* 278 */ MCD_OPC_CheckPredicate, 91, 238, 3, 0, // Skip to: 1289 +/* 283 */ MCD_OPC_CheckField, 6, 5, 0, 231, 3, 0, // Skip to: 1289 +/* 290 */ MCD_OPC_Decode, 194, 11, 23, // Opcode: DADDu +/* 294 */ MCD_OPC_FilterValue, 46, 16, 0, 0, // Skip to: 315 +/* 299 */ MCD_OPC_CheckPredicate, 91, 217, 3, 0, // Skip to: 1289 +/* 304 */ MCD_OPC_CheckField, 6, 5, 0, 210, 3, 0, // Skip to: 1289 +/* 311 */ MCD_OPC_Decode, 197, 12, 23, // Opcode: DSUB +/* 315 */ MCD_OPC_FilterValue, 47, 16, 0, 0, // Skip to: 336 +/* 320 */ MCD_OPC_CheckPredicate, 91, 196, 3, 0, // Skip to: 1289 +/* 325 */ MCD_OPC_CheckField, 6, 5, 0, 189, 3, 0, // Skip to: 1289 +/* 332 */ MCD_OPC_Decode, 198, 12, 23, // Opcode: DSUBu +/* 336 */ MCD_OPC_FilterValue, 56, 17, 0, 0, // Skip to: 358 +/* 341 */ MCD_OPC_CheckPredicate, 91, 175, 3, 0, // Skip to: 1289 +/* 346 */ MCD_OPC_CheckField, 21, 5, 0, 168, 3, 0, // Skip to: 1289 +/* 353 */ MCD_OPC_Decode, 187, 12, 251, 2, // Opcode: DSLL +/* 358 */ MCD_OPC_FilterValue, 58, 33, 0, 0, // Skip to: 396 +/* 363 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 366 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 381 +/* 371 */ MCD_OPC_CheckPredicate, 91, 145, 3, 0, // Skip to: 1289 +/* 376 */ MCD_OPC_Decode, 194, 12, 251, 2, // Opcode: DSRL +/* 381 */ MCD_OPC_FilterValue, 1, 135, 3, 0, // Skip to: 1289 +/* 386 */ MCD_OPC_CheckPredicate, 90, 130, 3, 0, // Skip to: 1289 +/* 391 */ MCD_OPC_Decode, 181, 12, 251, 2, // Opcode: DROTR +/* 396 */ MCD_OPC_FilterValue, 59, 17, 0, 0, // Skip to: 418 +/* 401 */ MCD_OPC_CheckPredicate, 91, 115, 3, 0, // Skip to: 1289 +/* 406 */ MCD_OPC_CheckField, 21, 5, 0, 108, 3, 0, // Skip to: 1289 +/* 413 */ MCD_OPC_Decode, 191, 12, 251, 2, // Opcode: DSRA +/* 418 */ MCD_OPC_FilterValue, 60, 17, 0, 0, // Skip to: 440 +/* 423 */ MCD_OPC_CheckPredicate, 91, 93, 3, 0, // Skip to: 1289 +/* 428 */ MCD_OPC_CheckField, 21, 5, 0, 86, 3, 0, // Skip to: 1289 +/* 435 */ MCD_OPC_Decode, 188, 12, 251, 2, // Opcode: DSLL32 +/* 440 */ MCD_OPC_FilterValue, 62, 33, 0, 0, // Skip to: 478 +/* 445 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 448 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 463 +/* 453 */ MCD_OPC_CheckPredicate, 91, 63, 3, 0, // Skip to: 1289 +/* 458 */ MCD_OPC_Decode, 195, 12, 251, 2, // Opcode: DSRL32 +/* 463 */ MCD_OPC_FilterValue, 1, 53, 3, 0, // Skip to: 1289 +/* 468 */ MCD_OPC_CheckPredicate, 90, 48, 3, 0, // Skip to: 1289 +/* 473 */ MCD_OPC_Decode, 182, 12, 251, 2, // Opcode: DROTR32 +/* 478 */ MCD_OPC_FilterValue, 63, 38, 3, 0, // Skip to: 1289 +/* 483 */ MCD_OPC_CheckPredicate, 91, 33, 3, 0, // Skip to: 1289 +/* 488 */ MCD_OPC_CheckField, 21, 5, 0, 26, 3, 0, // Skip to: 1289 +/* 495 */ MCD_OPC_Decode, 192, 12, 251, 2, // Opcode: DSRA32 +/* 500 */ MCD_OPC_FilterValue, 16, 85, 0, 0, // Skip to: 590 +/* 505 */ MCD_OPC_ExtractField, 3, 8, // Inst{10-3} ... +/* 508 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 546 +/* 513 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 516 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 531 +/* 521 */ MCD_OPC_CheckPredicate, 93, 251, 2, 0, // Skip to: 1289 +/* 526 */ MCD_OPC_Decode, 237, 11, 252, 2, // Opcode: DMFC0 +/* 531 */ MCD_OPC_FilterValue, 5, 241, 2, 0, // Skip to: 1289 +/* 536 */ MCD_OPC_CheckPredicate, 93, 236, 2, 0, // Skip to: 1289 +/* 541 */ MCD_OPC_Decode, 245, 11, 253, 2, // Opcode: DMTC0 +/* 546 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 568 +/* 551 */ MCD_OPC_CheckPredicate, 94, 221, 2, 0, // Skip to: 1289 +/* 556 */ MCD_OPC_CheckField, 21, 5, 3, 214, 2, 0, // Skip to: 1289 +/* 563 */ MCD_OPC_Decode, 241, 11, 252, 2, // Opcode: DMFGC0 +/* 568 */ MCD_OPC_FilterValue, 96, 204, 2, 0, // Skip to: 1289 +/* 573 */ MCD_OPC_CheckPredicate, 94, 199, 2, 0, // Skip to: 1289 +/* 578 */ MCD_OPC_CheckField, 21, 5, 3, 192, 2, 0, // Skip to: 1289 +/* 585 */ MCD_OPC_Decode, 249, 11, 253, 2, // Opcode: DMTGC0 +/* 590 */ MCD_OPC_FilterValue, 18, 47, 0, 0, // Skip to: 642 +/* 595 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 598 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 620 +/* 603 */ MCD_OPC_CheckPredicate, 93, 169, 2, 0, // Skip to: 1289 +/* 608 */ MCD_OPC_CheckField, 3, 8, 0, 162, 2, 0, // Skip to: 1289 +/* 615 */ MCD_OPC_Decode, 239, 11, 254, 2, // Opcode: DMFC2 +/* 620 */ MCD_OPC_FilterValue, 5, 152, 2, 0, // Skip to: 1289 +/* 625 */ MCD_OPC_CheckPredicate, 93, 147, 2, 0, // Skip to: 1289 +/* 630 */ MCD_OPC_CheckField, 3, 8, 0, 140, 2, 0, // Skip to: 1289 +/* 637 */ MCD_OPC_Decode, 247, 11, 255, 2, // Opcode: DMTC2 +/* 642 */ MCD_OPC_FilterValue, 21, 3, 1, 0, // Skip to: 906 +/* 647 */ MCD_OPC_ExtractField, 0, 13, // Inst{12-0} ... +/* 650 */ MCD_OPC_FilterValue, 188, 8, 10, 0, 0, // Skip to: 666 +/* 656 */ MCD_OPC_CheckPredicate, 15, 116, 2, 0, // Skip to: 1289 +/* 661 */ MCD_OPC_Decode, 229, 10, 128, 3, // Opcode: C_F_D64_MM +/* 666 */ MCD_OPC_FilterValue, 252, 8, 10, 0, 0, // Skip to: 682 +/* 672 */ MCD_OPC_CheckPredicate, 15, 100, 2, 0, // Skip to: 1289 +/* 677 */ MCD_OPC_Decode, 185, 11, 128, 3, // Opcode: C_UN_D64_MM +/* 682 */ MCD_OPC_FilterValue, 188, 9, 10, 0, 0, // Skip to: 698 +/* 688 */ MCD_OPC_CheckPredicate, 15, 84, 2, 0, // Skip to: 1289 +/* 693 */ MCD_OPC_Decode, 223, 10, 128, 3, // Opcode: C_EQ_D64_MM +/* 698 */ MCD_OPC_FilterValue, 252, 9, 10, 0, 0, // Skip to: 714 +/* 704 */ MCD_OPC_CheckPredicate, 15, 68, 2, 0, // Skip to: 1289 +/* 709 */ MCD_OPC_Decode, 167, 11, 128, 3, // Opcode: C_UEQ_D64_MM +/* 714 */ MCD_OPC_FilterValue, 188, 10, 10, 0, 0, // Skip to: 730 +/* 720 */ MCD_OPC_CheckPredicate, 15, 52, 2, 0, // Skip to: 1289 +/* 725 */ MCD_OPC_Decode, 149, 11, 128, 3, // Opcode: C_OLT_D64_MM +/* 730 */ MCD_OPC_FilterValue, 252, 10, 10, 0, 0, // Skip to: 746 +/* 736 */ MCD_OPC_CheckPredicate, 15, 36, 2, 0, // Skip to: 1289 +/* 741 */ MCD_OPC_Decode, 179, 11, 128, 3, // Opcode: C_ULT_D64_MM +/* 746 */ MCD_OPC_FilterValue, 188, 11, 10, 0, 0, // Skip to: 762 +/* 752 */ MCD_OPC_CheckPredicate, 15, 20, 2, 0, // Skip to: 1289 +/* 757 */ MCD_OPC_Decode, 143, 11, 128, 3, // Opcode: C_OLE_D64_MM +/* 762 */ MCD_OPC_FilterValue, 252, 11, 10, 0, 0, // Skip to: 778 +/* 768 */ MCD_OPC_CheckPredicate, 15, 4, 2, 0, // Skip to: 1289 +/* 773 */ MCD_OPC_Decode, 173, 11, 128, 3, // Opcode: C_ULE_D64_MM +/* 778 */ MCD_OPC_FilterValue, 188, 12, 10, 0, 0, // Skip to: 794 +/* 784 */ MCD_OPC_CheckPredicate, 15, 244, 1, 0, // Skip to: 1289 +/* 789 */ MCD_OPC_Decode, 161, 11, 128, 3, // Opcode: C_SF_D64_MM +/* 794 */ MCD_OPC_FilterValue, 252, 12, 10, 0, 0, // Skip to: 810 +/* 800 */ MCD_OPC_CheckPredicate, 15, 228, 1, 0, // Skip to: 1289 +/* 805 */ MCD_OPC_Decode, 253, 10, 128, 3, // Opcode: C_NGLE_D64_MM +/* 810 */ MCD_OPC_FilterValue, 188, 13, 10, 0, 0, // Skip to: 826 +/* 816 */ MCD_OPC_CheckPredicate, 15, 212, 1, 0, // Skip to: 1289 +/* 821 */ MCD_OPC_Decode, 155, 11, 128, 3, // Opcode: C_SEQ_D64_MM +/* 826 */ MCD_OPC_FilterValue, 252, 13, 10, 0, 0, // Skip to: 842 +/* 832 */ MCD_OPC_CheckPredicate, 15, 196, 1, 0, // Skip to: 1289 +/* 837 */ MCD_OPC_Decode, 131, 11, 128, 3, // Opcode: C_NGL_D64_MM +/* 842 */ MCD_OPC_FilterValue, 188, 14, 10, 0, 0, // Skip to: 858 +/* 848 */ MCD_OPC_CheckPredicate, 15, 180, 1, 0, // Skip to: 1289 +/* 853 */ MCD_OPC_Decode, 241, 10, 128, 3, // Opcode: C_LT_D64_MM +/* 858 */ MCD_OPC_FilterValue, 252, 14, 10, 0, 0, // Skip to: 874 +/* 864 */ MCD_OPC_CheckPredicate, 15, 164, 1, 0, // Skip to: 1289 +/* 869 */ MCD_OPC_Decode, 247, 10, 128, 3, // Opcode: C_NGE_D64_MM +/* 874 */ MCD_OPC_FilterValue, 188, 15, 10, 0, 0, // Skip to: 890 +/* 880 */ MCD_OPC_CheckPredicate, 15, 148, 1, 0, // Skip to: 1289 +/* 885 */ MCD_OPC_Decode, 235, 10, 128, 3, // Opcode: C_LE_D64_MM +/* 890 */ MCD_OPC_FilterValue, 252, 15, 137, 1, 0, // Skip to: 1289 +/* 896 */ MCD_OPC_CheckPredicate, 15, 132, 1, 0, // Skip to: 1289 +/* 901 */ MCD_OPC_Decode, 137, 11, 128, 3, // Opcode: C_NGT_D64_MM +/* 906 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 921 +/* 911 */ MCD_OPC_CheckPredicate, 95, 117, 1, 0, // Skip to: 1289 +/* 916 */ MCD_OPC_Decode, 192, 11, 129, 3, // Opcode: DADDi +/* 921 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 936 +/* 926 */ MCD_OPC_CheckPredicate, 91, 102, 1, 0, // Skip to: 1289 +/* 931 */ MCD_OPC_Decode, 193, 11, 129, 3, // Opcode: DADDiu +/* 936 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 951 +/* 941 */ MCD_OPC_CheckPredicate, 95, 87, 1, 0, // Skip to: 1289 +/* 946 */ MCD_OPC_Decode, 193, 15, 141, 1, // Opcode: LDL +/* 951 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 966 +/* 956 */ MCD_OPC_CheckPredicate, 95, 72, 1, 0, // Skip to: 1289 +/* 961 */ MCD_OPC_Decode, 195, 15, 141, 1, // Opcode: LDR +/* 966 */ MCD_OPC_FilterValue, 28, 33, 0, 0, // Skip to: 1004 +/* 971 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... +/* 974 */ MCD_OPC_FilterValue, 36, 10, 0, 0, // Skip to: 989 +/* 979 */ MCD_OPC_CheckPredicate, 96, 49, 1, 0, // Skip to: 1289 +/* 984 */ MCD_OPC_Decode, 202, 11, 130, 3, // Opcode: DCLZ +/* 989 */ MCD_OPC_FilterValue, 37, 39, 1, 0, // Skip to: 1289 +/* 994 */ MCD_OPC_CheckPredicate, 96, 34, 1, 0, // Skip to: 1289 +/* 999 */ MCD_OPC_Decode, 200, 11, 130, 3, // Opcode: DCLO +/* 1004 */ MCD_OPC_FilterValue, 31, 145, 0, 0, // Skip to: 1154 +/* 1009 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 1012 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1027 +/* 1017 */ MCD_OPC_CheckPredicate, 90, 11, 1, 0, // Skip to: 1289 +/* 1022 */ MCD_OPC_Decode, 212, 11, 131, 3, // Opcode: DEXTM +/* 1027 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1042 +/* 1032 */ MCD_OPC_CheckPredicate, 90, 252, 0, 0, // Skip to: 1289 +/* 1037 */ MCD_OPC_Decode, 213, 11, 131, 3, // Opcode: DEXTU +/* 1042 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1057 +/* 1047 */ MCD_OPC_CheckPredicate, 90, 237, 0, 0, // Skip to: 1289 +/* 1052 */ MCD_OPC_Decode, 210, 11, 131, 3, // Opcode: DEXT +/* 1057 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1072 +/* 1062 */ MCD_OPC_CheckPredicate, 90, 222, 0, 0, // Skip to: 1289 +/* 1067 */ MCD_OPC_Decode, 216, 11, 132, 3, // Opcode: DINSM +/* 1072 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 1087 +/* 1077 */ MCD_OPC_CheckPredicate, 90, 207, 0, 0, // Skip to: 1289 +/* 1082 */ MCD_OPC_Decode, 217, 11, 132, 3, // Opcode: DINSU +/* 1087 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 1102 +/* 1092 */ MCD_OPC_CheckPredicate, 90, 192, 0, 0, // Skip to: 1289 +/* 1097 */ MCD_OPC_Decode, 215, 11, 132, 3, // Opcode: DINS +/* 1102 */ MCD_OPC_FilterValue, 36, 182, 0, 0, // Skip to: 1289 +/* 1107 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1110 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1132 +/* 1115 */ MCD_OPC_CheckPredicate, 90, 169, 0, 0, // Skip to: 1289 +/* 1120 */ MCD_OPC_CheckField, 21, 5, 0, 162, 0, 0, // Skip to: 1289 +/* 1127 */ MCD_OPC_Decode, 184, 12, 241, 2, // Opcode: DSBH +/* 1132 */ MCD_OPC_FilterValue, 5, 152, 0, 0, // Skip to: 1289 +/* 1137 */ MCD_OPC_CheckPredicate, 90, 147, 0, 0, // Skip to: 1289 +/* 1142 */ MCD_OPC_CheckField, 21, 5, 0, 140, 0, 0, // Skip to: 1289 +/* 1149 */ MCD_OPC_Decode, 186, 12, 241, 2, // Opcode: DSHD +/* 1154 */ MCD_OPC_FilterValue, 39, 10, 0, 0, // Skip to: 1169 +/* 1159 */ MCD_OPC_CheckPredicate, 91, 125, 0, 0, // Skip to: 1289 +/* 1164 */ MCD_OPC_Decode, 183, 16, 141, 1, // Opcode: LWu +/* 1169 */ MCD_OPC_FilterValue, 44, 10, 0, 0, // Skip to: 1184 +/* 1174 */ MCD_OPC_CheckPredicate, 95, 110, 0, 0, // Skip to: 1289 +/* 1179 */ MCD_OPC_Decode, 238, 20, 141, 1, // Opcode: SDL +/* 1184 */ MCD_OPC_FilterValue, 45, 10, 0, 0, // Skip to: 1199 +/* 1189 */ MCD_OPC_CheckPredicate, 95, 95, 0, 0, // Skip to: 1289 +/* 1194 */ MCD_OPC_Decode, 239, 20, 141, 1, // Opcode: SDR +/* 1199 */ MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 1214 +/* 1204 */ MCD_OPC_CheckPredicate, 20, 80, 0, 0, // Skip to: 1289 +/* 1209 */ MCD_OPC_Decode, 231, 20, 139, 1, // Opcode: SDC1_MM_D64 +/* 1214 */ MCD_OPC_FilterValue, 47, 10, 0, 0, // Skip to: 1229 +/* 1219 */ MCD_OPC_CheckPredicate, 20, 65, 0, 0, // Skip to: 1289 +/* 1224 */ MCD_OPC_Decode, 184, 15, 139, 1, // Opcode: LDC1_MM_D64 +/* 1229 */ MCD_OPC_FilterValue, 52, 10, 0, 0, // Skip to: 1244 +/* 1234 */ MCD_OPC_CheckPredicate, 92, 50, 0, 0, // Skip to: 1289 +/* 1239 */ MCD_OPC_Decode, 238, 15, 141, 1, // Opcode: LLD +/* 1244 */ MCD_OPC_FilterValue, 55, 10, 0, 0, // Skip to: 1259 +/* 1249 */ MCD_OPC_CheckPredicate, 91, 35, 0, 0, // Skip to: 1289 +/* 1254 */ MCD_OPC_Decode, 179, 15, 141, 1, // Opcode: LD +/* 1259 */ MCD_OPC_FilterValue, 60, 10, 0, 0, // Skip to: 1274 +/* 1264 */ MCD_OPC_CheckPredicate, 95, 20, 0, 0, // Skip to: 1289 +/* 1269 */ MCD_OPC_Decode, 209, 20, 141, 1, // Opcode: SCD +/* 1274 */ MCD_OPC_FilterValue, 63, 10, 0, 0, // Skip to: 1289 +/* 1279 */ MCD_OPC_CheckPredicate, 91, 5, 0, 0, // Skip to: 1289 +/* 1284 */ MCD_OPC_Decode, 218, 20, 141, 1, // Opcode: SD +/* 1289 */ MCD_OPC_Fail, 0 }; -static bool getbool(uint64_t b) -{ - return b != 0; -} +static const uint8_t DecoderTableMipsDSP32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 35, 10, 0, 0, // Skip to: 18 +/* 8 */ MCD_OPC_CheckPredicate, 97, 20, 0, 0, // Skip to: 33 +/* 13 */ MCD_OPC_Decode, 142, 16, 141, 1, // Opcode: LWDSP +/* 18 */ MCD_OPC_FilterValue, 43, 10, 0, 0, // Skip to: 33 +/* 23 */ MCD_OPC_CheckPredicate, 97, 5, 0, 0, // Skip to: 33 +/* 28 */ MCD_OPC_Decode, 140, 23, 141, 1, // Opcode: SWDSP +/* 33 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMipsFP6432[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 17, 249, 5, 0, // Skip to: 1537 +/* 8 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 11 */ MCD_OPC_FilterValue, 0, 121, 0, 0, // Skip to: 137 +/* 16 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 19 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 41 +/* 24 */ MCD_OPC_CheckPredicate, 98, 158, 6, 0, // Skip to: 1723 +/* 29 */ MCD_OPC_CheckField, 6, 5, 0, 151, 6, 0, // Skip to: 1723 +/* 36 */ MCD_OPC_Decode, 133, 17, 133, 3, // Opcode: MFC1_D64 +/* 41 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 63 +/* 46 */ MCD_OPC_CheckPredicate, 99, 136, 6, 0, // Skip to: 1723 +/* 51 */ MCD_OPC_CheckField, 6, 5, 0, 129, 6, 0, // Skip to: 1723 +/* 58 */ MCD_OPC_Decode, 145, 17, 133, 3, // Opcode: MFHC1_D64 +/* 63 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 85 +/* 68 */ MCD_OPC_CheckPredicate, 98, 114, 6, 0, // Skip to: 1723 +/* 73 */ MCD_OPC_CheckField, 6, 5, 0, 107, 6, 0, // Skip to: 1723 +/* 80 */ MCD_OPC_Decode, 161, 18, 134, 3, // Opcode: MTC1_D64 +/* 85 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 107 +/* 90 */ MCD_OPC_CheckPredicate, 99, 92, 6, 0, // Skip to: 1723 +/* 95 */ MCD_OPC_CheckField, 6, 5, 0, 85, 6, 0, // Skip to: 1723 +/* 102 */ MCD_OPC_Decode, 174, 18, 135, 3, // Opcode: MTHC1_D64 +/* 107 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 122 +/* 112 */ MCD_OPC_CheckPredicate, 98, 70, 6, 0, // Skip to: 1723 +/* 117 */ MCD_OPC_Decode, 139, 13, 230, 2, // Opcode: FADD_D64 +/* 122 */ MCD_OPC_FilterValue, 22, 60, 6, 0, // Skip to: 1723 +/* 127 */ MCD_OPC_CheckPredicate, 100, 55, 6, 0, // Skip to: 1723 +/* 132 */ MCD_OPC_Decode, 141, 13, 230, 2, // Opcode: FADD_PS64 +/* 137 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 175 +/* 142 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 145 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 160 +/* 150 */ MCD_OPC_CheckPredicate, 98, 32, 6, 0, // Skip to: 1723 +/* 155 */ MCD_OPC_Decode, 157, 14, 230, 2, // Opcode: FSUB_D64 +/* 160 */ MCD_OPC_FilterValue, 22, 22, 6, 0, // Skip to: 1723 +/* 165 */ MCD_OPC_CheckPredicate, 100, 17, 6, 0, // Skip to: 1723 +/* 170 */ MCD_OPC_Decode, 159, 14, 230, 2, // Opcode: FSUB_PS64 +/* 175 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 213 +/* 180 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 183 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 198 +/* 188 */ MCD_OPC_CheckPredicate, 98, 250, 5, 0, // Skip to: 1723 +/* 193 */ MCD_OPC_Decode, 240, 13, 230, 2, // Opcode: FMUL_D64 +/* 198 */ MCD_OPC_FilterValue, 22, 240, 5, 0, // Skip to: 1723 +/* 203 */ MCD_OPC_CheckPredicate, 100, 235, 5, 0, // Skip to: 1723 +/* 208 */ MCD_OPC_Decode, 242, 13, 230, 2, // Opcode: FMUL_PS64 +/* 213 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 235 +/* 218 */ MCD_OPC_CheckPredicate, 98, 220, 5, 0, // Skip to: 1723 +/* 223 */ MCD_OPC_CheckField, 21, 5, 17, 213, 5, 0, // Skip to: 1723 +/* 230 */ MCD_OPC_Decode, 178, 13, 230, 2, // Opcode: FDIV_D64 +/* 235 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 258 +/* 240 */ MCD_OPC_CheckPredicate, 101, 198, 5, 0, // Skip to: 1723 +/* 245 */ MCD_OPC_CheckField, 16, 10, 160, 4, 190, 5, 0, // Skip to: 1723 +/* 253 */ MCD_OPC_Decode, 149, 14, 230, 1, // Opcode: FSQRT_D64 +/* 258 */ MCD_OPC_FilterValue, 5, 18, 0, 0, // Skip to: 281 +/* 263 */ MCD_OPC_CheckPredicate, 98, 175, 5, 0, // Skip to: 1723 +/* 268 */ MCD_OPC_CheckField, 16, 10, 160, 4, 167, 5, 0, // Skip to: 1723 +/* 276 */ MCD_OPC_Decode, 132, 13, 230, 1, // Opcode: FABS_D64 +/* 281 */ MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 304 +/* 286 */ MCD_OPC_CheckPredicate, 98, 152, 5, 0, // Skip to: 1723 +/* 291 */ MCD_OPC_CheckField, 16, 10, 160, 4, 144, 5, 0, // Skip to: 1723 +/* 299 */ MCD_OPC_Decode, 229, 13, 230, 1, // Opcode: FMOV_D64 +/* 304 */ MCD_OPC_FilterValue, 7, 18, 0, 0, // Skip to: 327 +/* 309 */ MCD_OPC_CheckPredicate, 98, 129, 5, 0, // Skip to: 1723 +/* 314 */ MCD_OPC_CheckField, 16, 10, 160, 4, 121, 5, 0, // Skip to: 1723 +/* 322 */ MCD_OPC_Decode, 249, 13, 230, 1, // Opcode: FNEG_D64 +/* 327 */ MCD_OPC_FilterValue, 8, 35, 0, 0, // Skip to: 367 +/* 332 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 335 */ MCD_OPC_FilterValue, 128, 4, 10, 0, 0, // Skip to: 351 +/* 341 */ MCD_OPC_CheckPredicate, 101, 97, 5, 0, // Skip to: 1723 +/* 346 */ MCD_OPC_Decode, 164, 20, 223, 1, // Opcode: ROUND_L_S +/* 351 */ MCD_OPC_FilterValue, 160, 4, 86, 5, 0, // Skip to: 1723 +/* 357 */ MCD_OPC_CheckPredicate, 102, 81, 5, 0, // Skip to: 1723 +/* 362 */ MCD_OPC_Decode, 162, 20, 230, 1, // Opcode: ROUND_L_D64 +/* 367 */ MCD_OPC_FilterValue, 9, 35, 0, 0, // Skip to: 407 +/* 372 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 375 */ MCD_OPC_FilterValue, 128, 4, 10, 0, 0, // Skip to: 391 +/* 381 */ MCD_OPC_CheckPredicate, 101, 57, 5, 0, // Skip to: 1723 +/* 386 */ MCD_OPC_Decode, 136, 24, 223, 1, // Opcode: TRUNC_L_S +/* 391 */ MCD_OPC_FilterValue, 160, 4, 46, 5, 0, // Skip to: 1723 +/* 397 */ MCD_OPC_CheckPredicate, 102, 41, 5, 0, // Skip to: 1723 +/* 402 */ MCD_OPC_Decode, 134, 24, 230, 1, // Opcode: TRUNC_L_D64 +/* 407 */ MCD_OPC_FilterValue, 10, 35, 0, 0, // Skip to: 447 +/* 412 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 415 */ MCD_OPC_FilterValue, 128, 4, 10, 0, 0, // Skip to: 431 +/* 421 */ MCD_OPC_CheckPredicate, 101, 17, 5, 0, // Skip to: 1723 +/* 426 */ MCD_OPC_Decode, 255, 8, 223, 1, // Opcode: CEIL_L_S +/* 431 */ MCD_OPC_FilterValue, 160, 4, 6, 5, 0, // Skip to: 1723 +/* 437 */ MCD_OPC_CheckPredicate, 102, 1, 5, 0, // Skip to: 1723 +/* 442 */ MCD_OPC_Decode, 253, 8, 230, 1, // Opcode: CEIL_L_D64 +/* 447 */ MCD_OPC_FilterValue, 11, 35, 0, 0, // Skip to: 487 +/* 452 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 455 */ MCD_OPC_FilterValue, 128, 4, 10, 0, 0, // Skip to: 471 +/* 461 */ MCD_OPC_CheckPredicate, 101, 233, 4, 0, // Skip to: 1723 +/* 466 */ MCD_OPC_Decode, 208, 13, 223, 1, // Opcode: FLOOR_L_S +/* 471 */ MCD_OPC_FilterValue, 160, 4, 222, 4, 0, // Skip to: 1723 +/* 477 */ MCD_OPC_CheckPredicate, 102, 217, 4, 0, // Skip to: 1723 +/* 482 */ MCD_OPC_Decode, 206, 13, 230, 1, // Opcode: FLOOR_L_D64 +/* 487 */ MCD_OPC_FilterValue, 12, 18, 0, 0, // Skip to: 510 +/* 492 */ MCD_OPC_CheckPredicate, 101, 202, 4, 0, // Skip to: 1723 +/* 497 */ MCD_OPC_CheckField, 16, 10, 160, 4, 194, 4, 0, // Skip to: 1723 +/* 505 */ MCD_OPC_Decode, 167, 20, 136, 3, // Opcode: ROUND_W_D64 +/* 510 */ MCD_OPC_FilterValue, 13, 18, 0, 0, // Skip to: 533 +/* 515 */ MCD_OPC_CheckPredicate, 101, 179, 4, 0, // Skip to: 1723 +/* 520 */ MCD_OPC_CheckField, 16, 10, 160, 4, 171, 4, 0, // Skip to: 1723 +/* 528 */ MCD_OPC_Decode, 139, 24, 136, 3, // Opcode: TRUNC_W_D64 +/* 533 */ MCD_OPC_FilterValue, 14, 18, 0, 0, // Skip to: 556 +/* 538 */ MCD_OPC_CheckPredicate, 101, 156, 4, 0, // Skip to: 1723 +/* 543 */ MCD_OPC_CheckField, 16, 10, 160, 4, 148, 4, 0, // Skip to: 1723 +/* 551 */ MCD_OPC_Decode, 130, 9, 136, 3, // Opcode: CEIL_W_D64 +/* 556 */ MCD_OPC_FilterValue, 15, 18, 0, 0, // Skip to: 579 +/* 561 */ MCD_OPC_CheckPredicate, 101, 133, 4, 0, // Skip to: 1723 +/* 566 */ MCD_OPC_CheckField, 16, 10, 160, 4, 125, 4, 0, // Skip to: 1723 +/* 574 */ MCD_OPC_Decode, 211, 13, 136, 3, // Opcode: FLOOR_W_D64 +/* 579 */ MCD_OPC_FilterValue, 17, 47, 0, 0, // Skip to: 631 +/* 584 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 587 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 609 +/* 592 */ MCD_OPC_CheckPredicate, 103, 102, 4, 0, // Skip to: 1723 +/* 597 */ MCD_OPC_CheckField, 21, 5, 17, 95, 4, 0, // Skip to: 1723 +/* 604 */ MCD_OPC_Decode, 219, 17, 137, 3, // Opcode: MOVF_D64 +/* 609 */ MCD_OPC_FilterValue, 1, 85, 4, 0, // Skip to: 1723 +/* 614 */ MCD_OPC_CheckPredicate, 103, 80, 4, 0, // Skip to: 1723 +/* 619 */ MCD_OPC_CheckField, 21, 5, 17, 73, 4, 0, // Skip to: 1723 +/* 626 */ MCD_OPC_Decode, 240, 17, 137, 3, // Opcode: MOVT_D64 +/* 631 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 653 +/* 636 */ MCD_OPC_CheckPredicate, 103, 58, 4, 0, // Skip to: 1723 +/* 641 */ MCD_OPC_CheckField, 21, 5, 17, 51, 4, 0, // Skip to: 1723 +/* 648 */ MCD_OPC_Decode, 252, 17, 138, 3, // Opcode: MOVZ_I_D64 +/* 653 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 675 +/* 658 */ MCD_OPC_CheckPredicate, 103, 36, 4, 0, // Skip to: 1723 +/* 663 */ MCD_OPC_CheckField, 21, 5, 17, 29, 4, 0, // Skip to: 1723 +/* 670 */ MCD_OPC_Decode, 231, 17, 138, 3, // Opcode: MOVN_I_D64 +/* 675 */ MCD_OPC_FilterValue, 21, 18, 0, 0, // Skip to: 698 +/* 680 */ MCD_OPC_CheckPredicate, 104, 14, 4, 0, // Skip to: 1723 +/* 685 */ MCD_OPC_CheckField, 16, 10, 160, 4, 6, 4, 0, // Skip to: 1723 +/* 693 */ MCD_OPC_Decode, 136, 20, 230, 1, // Opcode: RECIP_D64 +/* 698 */ MCD_OPC_FilterValue, 22, 18, 0, 0, // Skip to: 721 +/* 703 */ MCD_OPC_CheckPredicate, 104, 247, 3, 0, // Skip to: 1723 +/* 708 */ MCD_OPC_CheckField, 16, 10, 160, 4, 239, 3, 0, // Skip to: 1723 +/* 716 */ MCD_OPC_Decode, 175, 20, 230, 1, // Opcode: RSQRT_D64 +/* 721 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 743 +/* 726 */ MCD_OPC_CheckPredicate, 105, 224, 3, 0, // Skip to: 1723 +/* 731 */ MCD_OPC_CheckField, 21, 5, 22, 217, 3, 0, // Skip to: 1723 +/* 738 */ MCD_OPC_Decode, 155, 6, 230, 2, // Opcode: ADDR_PS64 +/* 743 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 765 +/* 748 */ MCD_OPC_CheckPredicate, 105, 202, 3, 0, // Skip to: 1723 +/* 753 */ MCD_OPC_CheckField, 21, 5, 22, 195, 3, 0, // Skip to: 1723 +/* 760 */ MCD_OPC_Decode, 223, 18, 230, 2, // Opcode: MULR_PS64 +/* 765 */ MCD_OPC_FilterValue, 32, 51, 0, 0, // Skip to: 821 +/* 770 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 773 */ MCD_OPC_FilterValue, 160, 4, 10, 0, 0, // Skip to: 789 +/* 779 */ MCD_OPC_CheckPredicate, 98, 171, 3, 0, // Skip to: 1723 +/* 784 */ MCD_OPC_Decode, 204, 10, 136, 3, // Opcode: CVT_S_D64 +/* 789 */ MCD_OPC_FilterValue, 160, 5, 10, 0, 0, // Skip to: 805 +/* 795 */ MCD_OPC_CheckPredicate, 106, 155, 3, 0, // Skip to: 1723 +/* 800 */ MCD_OPC_Decode, 206, 10, 136, 3, // Opcode: CVT_S_L +/* 805 */ MCD_OPC_FilterValue, 192, 5, 144, 3, 0, // Skip to: 1723 +/* 811 */ MCD_OPC_CheckPredicate, 100, 139, 3, 0, // Skip to: 1723 +/* 816 */ MCD_OPC_Decode, 209, 10, 136, 3, // Opcode: CVT_S_PU64 +/* 821 */ MCD_OPC_FilterValue, 33, 51, 0, 0, // Skip to: 877 +/* 826 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 829 */ MCD_OPC_FilterValue, 128, 4, 10, 0, 0, // Skip to: 845 +/* 835 */ MCD_OPC_CheckPredicate, 98, 115, 3, 0, // Skip to: 1723 +/* 840 */ MCD_OPC_Decode, 188, 10, 223, 1, // Opcode: CVT_D64_S +/* 845 */ MCD_OPC_FilterValue, 128, 5, 10, 0, 0, // Skip to: 861 +/* 851 */ MCD_OPC_CheckPredicate, 98, 99, 3, 0, // Skip to: 1723 +/* 856 */ MCD_OPC_Decode, 190, 10, 223, 1, // Opcode: CVT_D64_W +/* 861 */ MCD_OPC_FilterValue, 160, 5, 88, 3, 0, // Skip to: 1723 +/* 867 */ MCD_OPC_CheckPredicate, 106, 83, 3, 0, // Skip to: 1723 +/* 872 */ MCD_OPC_Decode, 187, 10, 230, 1, // Opcode: CVT_D64_L +/* 877 */ MCD_OPC_FilterValue, 36, 35, 0, 0, // Skip to: 917 +/* 882 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 885 */ MCD_OPC_FilterValue, 160, 4, 10, 0, 0, // Skip to: 901 +/* 891 */ MCD_OPC_CheckPredicate, 98, 59, 3, 0, // Skip to: 1723 +/* 896 */ MCD_OPC_Decode, 215, 10, 136, 3, // Opcode: CVT_W_D64 +/* 901 */ MCD_OPC_FilterValue, 192, 5, 48, 3, 0, // Skip to: 1723 +/* 907 */ MCD_OPC_CheckPredicate, 105, 43, 3, 0, // Skip to: 1723 +/* 912 */ MCD_OPC_Decode, 201, 10, 230, 1, // Opcode: CVT_PW_PS64 +/* 917 */ MCD_OPC_FilterValue, 38, 40, 0, 0, // Skip to: 962 +/* 922 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 925 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 940 +/* 930 */ MCD_OPC_CheckPredicate, 100, 20, 3, 0, // Skip to: 1723 +/* 935 */ MCD_OPC_Decode, 200, 10, 139, 3, // Opcode: CVT_PS_S64 +/* 940 */ MCD_OPC_FilterValue, 20, 10, 3, 0, // Skip to: 1723 +/* 945 */ MCD_OPC_CheckPredicate, 105, 5, 3, 0, // Skip to: 1723 +/* 950 */ MCD_OPC_CheckField, 16, 5, 0, 254, 2, 0, // Skip to: 1723 +/* 957 */ MCD_OPC_Decode, 199, 10, 230, 1, // Opcode: CVT_PS_PW64 +/* 962 */ MCD_OPC_FilterValue, 40, 18, 0, 0, // Skip to: 985 +/* 967 */ MCD_OPC_CheckPredicate, 100, 239, 2, 0, // Skip to: 1723 +/* 972 */ MCD_OPC_CheckField, 16, 10, 192, 5, 231, 2, 0, // Skip to: 1723 +/* 980 */ MCD_OPC_Decode, 208, 10, 136, 3, // Opcode: CVT_S_PL64 +/* 985 */ MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 1007 +/* 990 */ MCD_OPC_CheckPredicate, 100, 216, 2, 0, // Skip to: 1723 +/* 995 */ MCD_OPC_CheckField, 21, 5, 22, 209, 2, 0, // Skip to: 1723 +/* 1002 */ MCD_OPC_Decode, 201, 19, 230, 2, // Opcode: PLL_PS64 +/* 1007 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 1029 +/* 1012 */ MCD_OPC_CheckPredicate, 100, 194, 2, 0, // Skip to: 1723 +/* 1017 */ MCD_OPC_CheckField, 21, 5, 22, 187, 2, 0, // Skip to: 1723 +/* 1024 */ MCD_OPC_Decode, 202, 19, 230, 2, // Opcode: PLU_PS64 +/* 1029 */ MCD_OPC_FilterValue, 46, 17, 0, 0, // Skip to: 1051 +/* 1034 */ MCD_OPC_CheckPredicate, 100, 172, 2, 0, // Skip to: 1723 +/* 1039 */ MCD_OPC_CheckField, 21, 5, 22, 165, 2, 0, // Skip to: 1723 +/* 1046 */ MCD_OPC_Decode, 249, 19, 230, 2, // Opcode: PUL_PS64 +/* 1051 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 1073 +/* 1056 */ MCD_OPC_CheckPredicate, 100, 150, 2, 0, // Skip to: 1723 +/* 1061 */ MCD_OPC_CheckField, 21, 5, 22, 143, 2, 0, // Skip to: 1723 +/* 1068 */ MCD_OPC_Decode, 250, 19, 230, 2, // Opcode: PUU_PS64 +/* 1073 */ MCD_OPC_FilterValue, 48, 24, 0, 0, // Skip to: 1102 +/* 1078 */ MCD_OPC_CheckPredicate, 107, 128, 2, 0, // Skip to: 1723 +/* 1083 */ MCD_OPC_CheckField, 21, 5, 17, 121, 2, 0, // Skip to: 1723 +/* 1090 */ MCD_OPC_CheckField, 6, 2, 0, 114, 2, 0, // Skip to: 1723 +/* 1097 */ MCD_OPC_Decode, 228, 10, 140, 3, // Opcode: C_F_D64 +/* 1102 */ MCD_OPC_FilterValue, 49, 24, 0, 0, // Skip to: 1131 +/* 1107 */ MCD_OPC_CheckPredicate, 107, 99, 2, 0, // Skip to: 1723 +/* 1112 */ MCD_OPC_CheckField, 21, 5, 17, 92, 2, 0, // Skip to: 1723 +/* 1119 */ MCD_OPC_CheckField, 6, 2, 0, 85, 2, 0, // Skip to: 1723 +/* 1126 */ MCD_OPC_Decode, 184, 11, 140, 3, // Opcode: C_UN_D64 +/* 1131 */ MCD_OPC_FilterValue, 50, 24, 0, 0, // Skip to: 1160 +/* 1136 */ MCD_OPC_CheckPredicate, 107, 70, 2, 0, // Skip to: 1723 +/* 1141 */ MCD_OPC_CheckField, 21, 5, 17, 63, 2, 0, // Skip to: 1723 +/* 1148 */ MCD_OPC_CheckField, 6, 2, 0, 56, 2, 0, // Skip to: 1723 +/* 1155 */ MCD_OPC_Decode, 222, 10, 140, 3, // Opcode: C_EQ_D64 +/* 1160 */ MCD_OPC_FilterValue, 51, 24, 0, 0, // Skip to: 1189 +/* 1165 */ MCD_OPC_CheckPredicate, 107, 41, 2, 0, // Skip to: 1723 +/* 1170 */ MCD_OPC_CheckField, 21, 5, 17, 34, 2, 0, // Skip to: 1723 +/* 1177 */ MCD_OPC_CheckField, 6, 2, 0, 27, 2, 0, // Skip to: 1723 +/* 1184 */ MCD_OPC_Decode, 166, 11, 140, 3, // Opcode: C_UEQ_D64 +/* 1189 */ MCD_OPC_FilterValue, 52, 24, 0, 0, // Skip to: 1218 +/* 1194 */ MCD_OPC_CheckPredicate, 107, 12, 2, 0, // Skip to: 1723 +/* 1199 */ MCD_OPC_CheckField, 21, 5, 17, 5, 2, 0, // Skip to: 1723 +/* 1206 */ MCD_OPC_CheckField, 6, 2, 0, 254, 1, 0, // Skip to: 1723 +/* 1213 */ MCD_OPC_Decode, 148, 11, 140, 3, // Opcode: C_OLT_D64 +/* 1218 */ MCD_OPC_FilterValue, 53, 24, 0, 0, // Skip to: 1247 +/* 1223 */ MCD_OPC_CheckPredicate, 107, 239, 1, 0, // Skip to: 1723 +/* 1228 */ MCD_OPC_CheckField, 21, 5, 17, 232, 1, 0, // Skip to: 1723 +/* 1235 */ MCD_OPC_CheckField, 6, 2, 0, 225, 1, 0, // Skip to: 1723 +/* 1242 */ MCD_OPC_Decode, 178, 11, 140, 3, // Opcode: C_ULT_D64 +/* 1247 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1276 +/* 1252 */ MCD_OPC_CheckPredicate, 107, 210, 1, 0, // Skip to: 1723 +/* 1257 */ MCD_OPC_CheckField, 21, 5, 17, 203, 1, 0, // Skip to: 1723 +/* 1264 */ MCD_OPC_CheckField, 6, 2, 0, 196, 1, 0, // Skip to: 1723 +/* 1271 */ MCD_OPC_Decode, 142, 11, 140, 3, // Opcode: C_OLE_D64 +/* 1276 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 1305 +/* 1281 */ MCD_OPC_CheckPredicate, 107, 181, 1, 0, // Skip to: 1723 +/* 1286 */ MCD_OPC_CheckField, 21, 5, 17, 174, 1, 0, // Skip to: 1723 +/* 1293 */ MCD_OPC_CheckField, 6, 2, 0, 167, 1, 0, // Skip to: 1723 +/* 1300 */ MCD_OPC_Decode, 172, 11, 140, 3, // Opcode: C_ULE_D64 +/* 1305 */ MCD_OPC_FilterValue, 56, 24, 0, 0, // Skip to: 1334 +/* 1310 */ MCD_OPC_CheckPredicate, 107, 152, 1, 0, // Skip to: 1723 +/* 1315 */ MCD_OPC_CheckField, 21, 5, 17, 145, 1, 0, // Skip to: 1723 +/* 1322 */ MCD_OPC_CheckField, 6, 2, 0, 138, 1, 0, // Skip to: 1723 +/* 1329 */ MCD_OPC_Decode, 160, 11, 140, 3, // Opcode: C_SF_D64 +/* 1334 */ MCD_OPC_FilterValue, 57, 24, 0, 0, // Skip to: 1363 +/* 1339 */ MCD_OPC_CheckPredicate, 107, 123, 1, 0, // Skip to: 1723 +/* 1344 */ MCD_OPC_CheckField, 21, 5, 17, 116, 1, 0, // Skip to: 1723 +/* 1351 */ MCD_OPC_CheckField, 6, 2, 0, 109, 1, 0, // Skip to: 1723 +/* 1358 */ MCD_OPC_Decode, 252, 10, 140, 3, // Opcode: C_NGLE_D64 +/* 1363 */ MCD_OPC_FilterValue, 58, 24, 0, 0, // Skip to: 1392 +/* 1368 */ MCD_OPC_CheckPredicate, 107, 94, 1, 0, // Skip to: 1723 +/* 1373 */ MCD_OPC_CheckField, 21, 5, 17, 87, 1, 0, // Skip to: 1723 +/* 1380 */ MCD_OPC_CheckField, 6, 2, 0, 80, 1, 0, // Skip to: 1723 +/* 1387 */ MCD_OPC_Decode, 154, 11, 140, 3, // Opcode: C_SEQ_D64 +/* 1392 */ MCD_OPC_FilterValue, 59, 24, 0, 0, // Skip to: 1421 +/* 1397 */ MCD_OPC_CheckPredicate, 107, 65, 1, 0, // Skip to: 1723 +/* 1402 */ MCD_OPC_CheckField, 21, 5, 17, 58, 1, 0, // Skip to: 1723 +/* 1409 */ MCD_OPC_CheckField, 6, 2, 0, 51, 1, 0, // Skip to: 1723 +/* 1416 */ MCD_OPC_Decode, 130, 11, 140, 3, // Opcode: C_NGL_D64 +/* 1421 */ MCD_OPC_FilterValue, 60, 24, 0, 0, // Skip to: 1450 +/* 1426 */ MCD_OPC_CheckPredicate, 107, 36, 1, 0, // Skip to: 1723 +/* 1431 */ MCD_OPC_CheckField, 21, 5, 17, 29, 1, 0, // Skip to: 1723 +/* 1438 */ MCD_OPC_CheckField, 6, 2, 0, 22, 1, 0, // Skip to: 1723 +/* 1445 */ MCD_OPC_Decode, 240, 10, 140, 3, // Opcode: C_LT_D64 +/* 1450 */ MCD_OPC_FilterValue, 61, 24, 0, 0, // Skip to: 1479 +/* 1455 */ MCD_OPC_CheckPredicate, 107, 7, 1, 0, // Skip to: 1723 +/* 1460 */ MCD_OPC_CheckField, 21, 5, 17, 0, 1, 0, // Skip to: 1723 +/* 1467 */ MCD_OPC_CheckField, 6, 2, 0, 249, 0, 0, // Skip to: 1723 +/* 1474 */ MCD_OPC_Decode, 246, 10, 140, 3, // Opcode: C_NGE_D64 +/* 1479 */ MCD_OPC_FilterValue, 62, 24, 0, 0, // Skip to: 1508 +/* 1484 */ MCD_OPC_CheckPredicate, 107, 234, 0, 0, // Skip to: 1723 +/* 1489 */ MCD_OPC_CheckField, 21, 5, 17, 227, 0, 0, // Skip to: 1723 +/* 1496 */ MCD_OPC_CheckField, 6, 2, 0, 220, 0, 0, // Skip to: 1723 +/* 1503 */ MCD_OPC_Decode, 234, 10, 140, 3, // Opcode: C_LE_D64 +/* 1508 */ MCD_OPC_FilterValue, 63, 210, 0, 0, // Skip to: 1723 +/* 1513 */ MCD_OPC_CheckPredicate, 107, 205, 0, 0, // Skip to: 1723 +/* 1518 */ MCD_OPC_CheckField, 21, 5, 17, 198, 0, 0, // Skip to: 1723 +/* 1525 */ MCD_OPC_CheckField, 6, 2, 0, 191, 0, 0, // Skip to: 1723 +/* 1532 */ MCD_OPC_Decode, 136, 11, 140, 3, // Opcode: C_NGT_D64 +/* 1537 */ MCD_OPC_FilterValue, 19, 151, 0, 0, // Skip to: 1693 +/* 1542 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 1545 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 1567 +/* 1550 */ MCD_OPC_CheckPredicate, 108, 168, 0, 0, // Skip to: 1723 +/* 1555 */ MCD_OPC_CheckField, 11, 5, 0, 161, 0, 0, // Skip to: 1723 +/* 1562 */ MCD_OPC_Decode, 197, 15, 141, 3, // Opcode: LDXC164 +/* 1567 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 1589 +/* 1572 */ MCD_OPC_CheckPredicate, 109, 146, 0, 0, // Skip to: 1723 +/* 1577 */ MCD_OPC_CheckField, 11, 5, 0, 139, 0, 0, // Skip to: 1723 +/* 1584 */ MCD_OPC_Decode, 254, 15, 141, 3, // Opcode: LUXC164 +/* 1589 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 1611 +/* 1594 */ MCD_OPC_CheckPredicate, 108, 124, 0, 0, // Skip to: 1723 +/* 1599 */ MCD_OPC_CheckField, 6, 5, 0, 117, 0, 0, // Skip to: 1723 +/* 1606 */ MCD_OPC_Decode, 241, 20, 142, 3, // Opcode: SDXC164 +/* 1611 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 1633 +/* 1616 */ MCD_OPC_CheckPredicate, 109, 102, 0, 0, // Skip to: 1723 +/* 1621 */ MCD_OPC_CheckField, 6, 5, 0, 95, 0, 0, // Skip to: 1723 +/* 1628 */ MCD_OPC_Decode, 254, 22, 142, 3, // Opcode: SUXC164 +/* 1633 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 1648 +/* 1638 */ MCD_OPC_CheckPredicate, 110, 80, 0, 0, // Skip to: 1723 +/* 1643 */ MCD_OPC_Decode, 212, 16, 143, 3, // Opcode: MADD_D64 +/* 1648 */ MCD_OPC_FilterValue, 41, 10, 0, 0, // Skip to: 1663 +/* 1653 */ MCD_OPC_CheckPredicate, 110, 65, 0, 0, // Skip to: 1723 +/* 1658 */ MCD_OPC_Decode, 148, 18, 143, 3, // Opcode: MSUB_D64 +/* 1663 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 1678 +/* 1668 */ MCD_OPC_CheckPredicate, 111, 50, 0, 0, // Skip to: 1723 +/* 1673 */ MCD_OPC_Decode, 141, 19, 143, 3, // Opcode: NMADD_D64 +/* 1678 */ MCD_OPC_FilterValue, 57, 40, 0, 0, // Skip to: 1723 +/* 1683 */ MCD_OPC_CheckPredicate, 111, 35, 0, 0, // Skip to: 1723 +/* 1688 */ MCD_OPC_Decode, 146, 19, 143, 3, // Opcode: NMSUB_D64 +/* 1693 */ MCD_OPC_FilterValue, 53, 10, 0, 0, // Skip to: 1708 +/* 1698 */ MCD_OPC_CheckPredicate, 101, 20, 0, 0, // Skip to: 1723 +/* 1703 */ MCD_OPC_Decode, 181, 15, 219, 2, // Opcode: LDC164 +/* 1708 */ MCD_OPC_FilterValue, 61, 10, 0, 0, // Skip to: 1723 +/* 1713 */ MCD_OPC_CheckPredicate, 101, 5, 0, 0, // Skip to: 1723 +/* 1718 */ MCD_OPC_Decode, 228, 20, 219, 2, // Opcode: SDC164 +/* 1723 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableNanoMips16[] = { +/* 0 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 3 */ MCD_OPC_FilterValue, 4, 60, 0, 0, // Skip to: 68 +/* 8 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 25 +/* 13 */ MCD_OPC_CheckField, 2, 8, 2, 5, 0, 0, // Skip to: 25 +/* 20 */ MCD_OPC_Decode, 183, 23, 144, 3, // Opcode: SYSCALL16_NM +/* 25 */ MCD_OPC_ExtractField, 3, 7, // Inst{9-3} ... +/* 28 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 43 +/* 33 */ MCD_OPC_CheckPredicate, 112, 20, 0, 0, // Skip to: 58 +/* 38 */ MCD_OPC_Decode, 214, 8, 145, 3, // Opcode: BREAK16_NM +/* 43 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 58 +/* 48 */ MCD_OPC_CheckPredicate, 112, 5, 0, 0, // Skip to: 58 +/* 53 */ MCD_OPC_Decode, 222, 20, 145, 3, // Opcode: SDBBP16_NM +/* 58 */ MCD_OPC_CheckPredicate, 112, 243, 2, 0, // Skip to: 818 +/* 63 */ MCD_OPC_Decode, 215, 17, 146, 3, // Opcode: MOVE_NM +/* 68 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 83 +/* 73 */ MCD_OPC_CheckPredicate, 112, 228, 2, 0, // Skip to: 818 +/* 78 */ MCD_OPC_Decode, 133, 16, 147, 3, // Opcode: LW16_NM +/* 83 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 98 +/* 88 */ MCD_OPC_CheckPredicate, 112, 213, 2, 0, // Skip to: 818 +/* 93 */ MCD_OPC_Decode, 163, 7, 148, 3, // Opcode: BC16_NM +/* 98 */ MCD_OPC_FilterValue, 7, 33, 0, 0, // Skip to: 136 +/* 103 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 106 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 121 +/* 111 */ MCD_OPC_CheckPredicate, 112, 190, 2, 0, // Skip to: 818 +/* 116 */ MCD_OPC_Decode, 191, 20, 149, 3, // Opcode: SAVE16_NM +/* 121 */ MCD_OPC_FilterValue, 1, 180, 2, 0, // Skip to: 818 +/* 126 */ MCD_OPC_CheckPredicate, 112, 175, 2, 0, // Skip to: 818 +/* 131 */ MCD_OPC_Decode, 148, 20, 149, 3, // Opcode: RESTOREJRC16_NM +/* 136 */ MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 174 +/* 141 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 144 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 159 +/* 149 */ MCD_OPC_CheckPredicate, 112, 152, 2, 0, // Skip to: 818 +/* 154 */ MCD_OPC_Decode, 222, 21, 150, 3, // Opcode: SLL16_NM +/* 159 */ MCD_OPC_FilterValue, 1, 142, 2, 0, // Skip to: 818 +/* 164 */ MCD_OPC_CheckPredicate, 112, 137, 2, 0, // Skip to: 818 +/* 169 */ MCD_OPC_Decode, 163, 22, 150, 3, // Opcode: SRL16_NM +/* 174 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 189 +/* 179 */ MCD_OPC_CheckPredicate, 112, 122, 2, 0, // Skip to: 818 +/* 184 */ MCD_OPC_Decode, 167, 16, 151, 3, // Opcode: LWSP16_NM +/* 189 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 204 +/* 194 */ MCD_OPC_CheckPredicate, 112, 107, 2, 0, // Skip to: 818 +/* 199 */ MCD_OPC_Decode, 149, 7, 148, 3, // Opcode: BALC16_NM +/* 204 */ MCD_OPC_FilterValue, 15, 47, 0, 0, // Skip to: 256 +/* 209 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 212 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 234 +/* 217 */ MCD_OPC_CheckPredicate, 112, 84, 2, 0, // Skip to: 818 +/* 222 */ MCD_OPC_CheckField, 8, 1, 0, 77, 2, 0, // Skip to: 818 +/* 229 */ MCD_OPC_Decode, 208, 6, 152, 3, // Opcode: ADDu4x4_NM +/* 234 */ MCD_OPC_FilterValue, 1, 67, 2, 0, // Skip to: 818 +/* 239 */ MCD_OPC_CheckPredicate, 112, 62, 2, 0, // Skip to: 818 +/* 244 */ MCD_OPC_CheckField, 8, 1, 0, 55, 2, 0, // Skip to: 818 +/* 251 */ MCD_OPC_Decode, 206, 18, 152, 3, // Opcode: MUL4x4_NM +/* 256 */ MCD_OPC_FilterValue, 20, 86, 0, 0, // Skip to: 347 +/* 261 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 264 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 332 +/* 269 */ MCD_OPC_ExtractField, 1, 3, // Inst{3-1} ... +/* 272 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 287 +/* 277 */ MCD_OPC_CheckPredicate, 112, 24, 2, 0, // Skip to: 818 +/* 282 */ MCD_OPC_Decode, 160, 19, 153, 3, // Opcode: NOT16_NM +/* 287 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 302 +/* 292 */ MCD_OPC_CheckPredicate, 112, 9, 2, 0, // Skip to: 818 +/* 297 */ MCD_OPC_Decode, 175, 24, 154, 3, // Opcode: XOR16_NM +/* 302 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 317 +/* 307 */ MCD_OPC_CheckPredicate, 112, 250, 1, 0, // Skip to: 818 +/* 312 */ MCD_OPC_Decode, 219, 6, 154, 3, // Opcode: AND16_NM +/* 317 */ MCD_OPC_FilterValue, 6, 240, 1, 0, // Skip to: 818 +/* 322 */ MCD_OPC_CheckPredicate, 112, 235, 1, 0, // Skip to: 818 +/* 327 */ MCD_OPC_Decode, 166, 19, 154, 3, // Opcode: OR16_NM +/* 332 */ MCD_OPC_FilterValue, 1, 225, 1, 0, // Skip to: 818 +/* 337 */ MCD_OPC_CheckPredicate, 112, 220, 1, 0, // Skip to: 818 +/* 342 */ MCD_OPC_Decode, 174, 16, 155, 3, // Opcode: LWXS16_NM +/* 347 */ MCD_OPC_FilterValue, 21, 10, 0, 0, // Skip to: 362 +/* 352 */ MCD_OPC_CheckPredicate, 112, 205, 1, 0, // Skip to: 818 +/* 357 */ MCD_OPC_Decode, 146, 16, 156, 3, // Opcode: LWGP16_NM +/* 362 */ MCD_OPC_FilterValue, 23, 48, 0, 0, // Skip to: 415 +/* 367 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 370 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 385 +/* 375 */ MCD_OPC_CheckPredicate, 112, 182, 1, 0, // Skip to: 818 +/* 380 */ MCD_OPC_Decode, 155, 15, 157, 3, // Opcode: LB16_NM +/* 385 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 400 +/* 390 */ MCD_OPC_CheckPredicate, 112, 167, 1, 0, // Skip to: 818 +/* 395 */ MCD_OPC_Decode, 196, 20, 158, 3, // Opcode: SB16_NM +/* 400 */ MCD_OPC_FilterValue, 2, 157, 1, 0, // Skip to: 818 +/* 405 */ MCD_OPC_CheckPredicate, 112, 152, 1, 0, // Skip to: 818 +/* 410 */ MCD_OPC_Decode, 161, 15, 157, 3, // Opcode: LBU16_NM +/* 415 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 437 +/* 420 */ MCD_OPC_CheckPredicate, 112, 137, 1, 0, // Skip to: 818 +/* 425 */ MCD_OPC_CheckField, 6, 1, 1, 130, 1, 0, // Skip to: 818 +/* 432 */ MCD_OPC_Decode, 133, 6, 159, 3, // Opcode: ADDIUR1SP_NM +/* 437 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 452 +/* 442 */ MCD_OPC_CheckPredicate, 112, 115, 1, 0, // Skip to: 818 +/* 447 */ MCD_OPC_Decode, 134, 16, 160, 3, // Opcode: LW4x4_NM +/* 452 */ MCD_OPC_FilterValue, 31, 63, 0, 0, // Skip to: 520 +/* 457 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 460 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 498 +/* 465 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 468 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 483 +/* 473 */ MCD_OPC_CheckPredicate, 112, 84, 1, 0, // Skip to: 818 +/* 478 */ MCD_OPC_Decode, 207, 15, 161, 3, // Opcode: LH16_NM +/* 483 */ MCD_OPC_FilterValue, 1, 74, 1, 0, // Skip to: 818 +/* 488 */ MCD_OPC_CheckPredicate, 112, 69, 1, 0, // Skip to: 818 +/* 493 */ MCD_OPC_Decode, 213, 15, 161, 3, // Opcode: LHU16_NM +/* 498 */ MCD_OPC_FilterValue, 1, 59, 1, 0, // Skip to: 818 +/* 503 */ MCD_OPC_CheckPredicate, 112, 54, 1, 0, // Skip to: 818 +/* 508 */ MCD_OPC_CheckField, 3, 1, 0, 47, 1, 0, // Skip to: 818 +/* 515 */ MCD_OPC_Decode, 146, 21, 162, 3, // Opcode: SH16_NM +/* 520 */ MCD_OPC_FilterValue, 36, 56, 0, 0, // Skip to: 581 +/* 525 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 528 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 543 +/* 533 */ MCD_OPC_CheckPredicate, 112, 24, 1, 0, // Skip to: 818 +/* 538 */ MCD_OPC_Decode, 135, 6, 163, 3, // Opcode: ADDIUR2_NM +/* 543 */ MCD_OPC_FilterValue, 1, 14, 1, 0, // Skip to: 818 +/* 548 */ MCD_OPC_CheckPredicate, 112, 18, 0, 0, // Skip to: 571 +/* 553 */ MCD_OPC_CheckField, 4, 6, 0, 11, 0, 0, // Skip to: 571 +/* 560 */ MCD_OPC_CheckField, 0, 3, 0, 4, 0, 0, // Skip to: 571 +/* 567 */ MCD_OPC_Decode, 150, 19, 10, // Opcode: NOP_NM +/* 571 */ MCD_OPC_CheckPredicate, 112, 242, 0, 0, // Skip to: 818 +/* 576 */ MCD_OPC_Decode, 136, 6, 164, 3, // Opcode: ADDIURS5_NM +/* 581 */ MCD_OPC_FilterValue, 37, 10, 0, 0, // Skip to: 596 +/* 586 */ MCD_OPC_CheckPredicate, 112, 227, 0, 0, // Skip to: 818 +/* 591 */ MCD_OPC_Decode, 131, 23, 165, 3, // Opcode: SW16_NM +/* 596 */ MCD_OPC_FilterValue, 38, 10, 0, 0, // Skip to: 611 +/* 601 */ MCD_OPC_CheckPredicate, 112, 212, 0, 0, // Skip to: 818 +/* 606 */ MCD_OPC_Decode, 203, 7, 166, 3, // Opcode: BEQZC16_NM +/* 611 */ MCD_OPC_FilterValue, 44, 33, 0, 0, // Skip to: 649 +/* 616 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 619 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 634 +/* 624 */ MCD_OPC_CheckPredicate, 112, 189, 0, 0, // Skip to: 818 +/* 629 */ MCD_OPC_Decode, 207, 6, 167, 3, // Opcode: ADDu16_NM +/* 634 */ MCD_OPC_FilterValue, 1, 179, 0, 0, // Skip to: 818 +/* 639 */ MCD_OPC_CheckPredicate, 112, 174, 0, 0, // Skip to: 818 +/* 644 */ MCD_OPC_Decode, 250, 22, 167, 3, // Opcode: SUBu16_NM +/* 649 */ MCD_OPC_FilterValue, 45, 10, 0, 0, // Skip to: 664 +/* 654 */ MCD_OPC_CheckPredicate, 112, 159, 0, 0, // Skip to: 818 +/* 659 */ MCD_OPC_Decode, 162, 23, 151, 3, // Opcode: SWSP16_NM +/* 664 */ MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 679 +/* 669 */ MCD_OPC_CheckPredicate, 112, 144, 0, 0, // Skip to: 818 +/* 674 */ MCD_OPC_Decode, 193, 8, 166, 3, // Opcode: BNEZC16_NM +/* 679 */ MCD_OPC_FilterValue, 47, 10, 0, 0, // Skip to: 694 +/* 684 */ MCD_OPC_CheckPredicate, 112, 129, 0, 0, // Skip to: 818 +/* 689 */ MCD_OPC_Decode, 214, 17, 168, 3, // Opcode: MOVEP_NM +/* 694 */ MCD_OPC_FilterValue, 52, 10, 0, 0, // Skip to: 709 +/* 699 */ MCD_OPC_CheckPredicate, 112, 114, 0, 0, // Skip to: 818 +/* 704 */ MCD_OPC_Decode, 233, 15, 169, 3, // Opcode: LI16_NM +/* 709 */ MCD_OPC_FilterValue, 53, 10, 0, 0, // Skip to: 724 +/* 714 */ MCD_OPC_CheckPredicate, 112, 99, 0, 0, // Skip to: 818 +/* 719 */ MCD_OPC_Decode, 144, 23, 170, 3, // Opcode: SWGP16_NM +/* 724 */ MCD_OPC_FilterValue, 54, 44, 0, 0, // Skip to: 773 +/* 729 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 746 +/* 734 */ MCD_OPC_CheckField, 0, 5, 0, 5, 0, 0, // Skip to: 746 +/* 741 */ MCD_OPC_Decode, 139, 15, 171, 3, // Opcode: JRC_NM +/* 746 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 763 +/* 751 */ MCD_OPC_CheckField, 0, 4, 0, 5, 0, 0, // Skip to: 763 +/* 758 */ MCD_OPC_Decode, 240, 14, 172, 3, // Opcode: JALRC16_NM +/* 763 */ MCD_OPC_CheckPredicate, 112, 50, 0, 0, // Skip to: 818 +/* 768 */ MCD_OPC_Decode, 191, 7, 173, 3, // Opcode: BEQC16_NM +/* 773 */ MCD_OPC_FilterValue, 60, 10, 0, 0, // Skip to: 788 +/* 778 */ MCD_OPC_CheckPredicate, 112, 35, 0, 0, // Skip to: 818 +/* 783 */ MCD_OPC_Decode, 223, 6, 174, 3, // Opcode: ANDI16_NM +/* 788 */ MCD_OPC_FilterValue, 61, 10, 0, 0, // Skip to: 803 +/* 793 */ MCD_OPC_CheckPredicate, 112, 20, 0, 0, // Skip to: 818 +/* 798 */ MCD_OPC_Decode, 132, 23, 175, 3, // Opcode: SW4x4_NM +/* 803 */ MCD_OPC_FilterValue, 63, 10, 0, 0, // Skip to: 818 +/* 808 */ MCD_OPC_CheckPredicate, 112, 5, 0, 0, // Skip to: 818 +/* 813 */ MCD_OPC_Decode, 211, 17, 176, 3, // Opcode: MOVEPREV_NM +/* 818 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableNanoMips32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 83 +/* 8 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 25 +/* 13 */ MCD_OPC_CheckField, 18, 8, 2, 5, 0, 0, // Skip to: 25 +/* 20 */ MCD_OPC_Decode, 185, 23, 177, 3, // Opcode: SYSCALL_NM +/* 25 */ MCD_OPC_ExtractField, 19, 7, // Inst{25-19} ... +/* 28 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43 +/* 33 */ MCD_OPC_CheckPredicate, 112, 35, 0, 0, // Skip to: 73 +/* 38 */ MCD_OPC_Decode, 210, 21, 178, 3, // Opcode: SIGRIE_NM +/* 43 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 58 +/* 48 */ MCD_OPC_CheckPredicate, 112, 20, 0, 0, // Skip to: 73 +/* 53 */ MCD_OPC_Decode, 217, 8, 178, 3, // Opcode: BREAK_NM +/* 58 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 73 +/* 63 */ MCD_OPC_CheckPredicate, 112, 5, 0, 0, // Skip to: 73 +/* 68 */ MCD_OPC_Decode, 225, 20, 178, 3, // Opcode: SDBBP_NM +/* 73 */ MCD_OPC_CheckPredicate, 112, 165, 12, 0, // Skip to: 3315 +/* 78 */ MCD_OPC_Decode, 140, 6, 179, 3, // Opcode: ADDIU_NM +/* 83 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 98 +/* 88 */ MCD_OPC_CheckPredicate, 112, 150, 12, 0, // Skip to: 3315 +/* 93 */ MCD_OPC_Decode, 152, 15, 180, 3, // Opcode: LAPC32_NM +/* 98 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 113 +/* 103 */ MCD_OPC_CheckPredicate, 112, 135, 12, 0, // Skip to: 3315 +/* 108 */ MCD_OPC_Decode, 210, 17, 181, 3, // Opcode: MOVEBALC_NM +/* 113 */ MCD_OPC_FilterValue, 8, 55, 6, 0, // Skip to: 1709 +/* 118 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... +/* 121 */ MCD_OPC_FilterValue, 0, 64, 1, 0, // Skip to: 446 +/* 126 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 129 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 190 +/* 134 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 137 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 175 +/* 142 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 145 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 160 +/* 150 */ MCD_OPC_CheckPredicate, 112, 88, 12, 0, // Skip to: 3315 +/* 155 */ MCD_OPC_Decode, 211, 23, 182, 3, // Opcode: TEQ_NM +/* 160 */ MCD_OPC_FilterValue, 1, 78, 12, 0, // Skip to: 3315 +/* 165 */ MCD_OPC_CheckPredicate, 112, 73, 12, 0, // Skip to: 3315 +/* 170 */ MCD_OPC_Decode, 133, 24, 182, 3, // Opcode: TNE_NM +/* 175 */ MCD_OPC_FilterValue, 7, 63, 12, 0, // Skip to: 3315 +/* 180 */ MCD_OPC_CheckPredicate, 112, 58, 12, 0, // Skip to: 3315 +/* 185 */ MCD_OPC_Decode, 131, 20, 183, 3, // Opcode: RDHWR_NM +/* 190 */ MCD_OPC_FilterValue, 7, 198, 0, 0, // Skip to: 393 +/* 195 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 198 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 213 +/* 203 */ MCD_OPC_CheckPredicate, 112, 35, 12, 0, // Skip to: 3315 +/* 208 */ MCD_OPC_Decode, 169, 15, 184, 3, // Opcode: LBX_NM +/* 213 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 228 +/* 218 */ MCD_OPC_CheckPredicate, 112, 20, 12, 0, // Skip to: 3315 +/* 223 */ MCD_OPC_Decode, 201, 20, 184, 3, // Opcode: SBX_NM +/* 228 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 243 +/* 233 */ MCD_OPC_CheckPredicate, 112, 5, 12, 0, // Skip to: 3315 +/* 238 */ MCD_OPC_Decode, 165, 15, 184, 3, // Opcode: LBUX_NM +/* 243 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 258 +/* 248 */ MCD_OPC_CheckPredicate, 112, 246, 11, 0, // Skip to: 3315 +/* 253 */ MCD_OPC_Decode, 222, 15, 184, 3, // Opcode: LHX_NM +/* 258 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 273 +/* 263 */ MCD_OPC_CheckPredicate, 112, 231, 11, 0, // Skip to: 3315 +/* 268 */ MCD_OPC_Decode, 220, 15, 184, 3, // Opcode: LHXS_NM +/* 273 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 288 +/* 278 */ MCD_OPC_CheckPredicate, 112, 216, 11, 0, // Skip to: 3315 +/* 283 */ MCD_OPC_Decode, 203, 21, 184, 3, // Opcode: SHX_NM +/* 288 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 303 +/* 293 */ MCD_OPC_CheckPredicate, 112, 201, 11, 0, // Skip to: 3315 +/* 298 */ MCD_OPC_Decode, 202, 21, 184, 3, // Opcode: SHXS_NM +/* 303 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 318 +/* 308 */ MCD_OPC_CheckPredicate, 112, 186, 11, 0, // Skip to: 3315 +/* 313 */ MCD_OPC_Decode, 216, 15, 184, 3, // Opcode: LHUX_NM +/* 318 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 333 +/* 323 */ MCD_OPC_CheckPredicate, 112, 171, 11, 0, // Skip to: 3315 +/* 328 */ MCD_OPC_Decode, 215, 15, 184, 3, // Opcode: LHUXS_NM +/* 333 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 348 +/* 338 */ MCD_OPC_CheckPredicate, 112, 156, 11, 0, // Skip to: 3315 +/* 343 */ MCD_OPC_Decode, 178, 16, 184, 3, // Opcode: LWX_NM +/* 348 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 363 +/* 353 */ MCD_OPC_CheckPredicate, 112, 141, 11, 0, // Skip to: 3315 +/* 358 */ MCD_OPC_Decode, 176, 16, 184, 3, // Opcode: LWXS_NM +/* 363 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 378 +/* 368 */ MCD_OPC_CheckPredicate, 112, 126, 11, 0, // Skip to: 3315 +/* 373 */ MCD_OPC_Decode, 168, 23, 184, 3, // Opcode: SWX_NM +/* 378 */ MCD_OPC_FilterValue, 19, 116, 11, 0, // Skip to: 3315 +/* 383 */ MCD_OPC_CheckPredicate, 112, 111, 11, 0, // Skip to: 3315 +/* 388 */ MCD_OPC_Decode, 167, 23, 184, 3, // Opcode: SWXS_NM +/* 393 */ MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 431 +/* 398 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 401 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 416 +/* 406 */ MCD_OPC_CheckPredicate, 112, 88, 11, 0, // Skip to: 3315 +/* 411 */ MCD_OPC_Decode, 245, 20, 185, 3, // Opcode: SEB_NM +/* 416 */ MCD_OPC_FilterValue, 1, 78, 11, 0, // Skip to: 3315 +/* 421 */ MCD_OPC_CheckPredicate, 112, 73, 11, 0, // Skip to: 3315 +/* 426 */ MCD_OPC_Decode, 249, 20, 185, 3, // Opcode: SEH_NM +/* 431 */ MCD_OPC_FilterValue, 15, 63, 11, 0, // Skip to: 3315 +/* 436 */ MCD_OPC_CheckPredicate, 112, 58, 11, 0, // Skip to: 3315 +/* 441 */ MCD_OPC_Decode, 249, 15, 186, 3, // Opcode: LSA_NM +/* 446 */ MCD_OPC_FilterValue, 1, 161, 1, 0, // Skip to: 868 +/* 451 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 454 */ MCD_OPC_FilterValue, 0, 10, 1, 0, // Skip to: 725 +/* 459 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 462 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 477 +/* 467 */ MCD_OPC_CheckPredicate, 112, 27, 11, 0, // Skip to: 3315 +/* 472 */ MCD_OPC_Decode, 231, 21, 187, 3, // Opcode: SLLV_NM +/* 477 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 492 +/* 482 */ MCD_OPC_CheckPredicate, 112, 12, 11, 0, // Skip to: 3315 +/* 487 */ MCD_OPC_Decode, 178, 22, 187, 3, // Opcode: SRLV_NM +/* 492 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 507 +/* 497 */ MCD_OPC_CheckPredicate, 112, 253, 10, 0, // Skip to: 3315 +/* 502 */ MCD_OPC_Decode, 153, 22, 187, 3, // Opcode: SRAV_NM +/* 507 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 522 +/* 512 */ MCD_OPC_CheckPredicate, 112, 238, 10, 0, // Skip to: 3315 +/* 517 */ MCD_OPC_Decode, 158, 20, 187, 3, // Opcode: ROTRV_NM +/* 522 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 537 +/* 527 */ MCD_OPC_CheckPredicate, 112, 223, 10, 0, // Skip to: 3315 +/* 532 */ MCD_OPC_Decode, 201, 6, 187, 3, // Opcode: ADD_NM +/* 537 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 552 +/* 542 */ MCD_OPC_CheckPredicate, 112, 208, 10, 0, // Skip to: 3315 +/* 547 */ MCD_OPC_Decode, 210, 6, 187, 3, // Opcode: ADDu_NM +/* 552 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 567 +/* 557 */ MCD_OPC_CheckPredicate, 112, 193, 10, 0, // Skip to: 3315 +/* 562 */ MCD_OPC_Decode, 248, 22, 187, 3, // Opcode: SUB_NM +/* 567 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 582 +/* 572 */ MCD_OPC_CheckPredicate, 112, 178, 10, 0, // Skip to: 3315 +/* 577 */ MCD_OPC_Decode, 252, 22, 187, 3, // Opcode: SUBu_NM +/* 582 */ MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 620 +/* 587 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 590 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 605 +/* 595 */ MCD_OPC_CheckPredicate, 112, 155, 10, 0, // Skip to: 3315 +/* 600 */ MCD_OPC_Decode, 130, 18, 188, 3, // Opcode: MOVZ_NM +/* 605 */ MCD_OPC_FilterValue, 1, 145, 10, 0, // Skip to: 3315 +/* 610 */ MCD_OPC_CheckPredicate, 112, 140, 10, 0, // Skip to: 3315 +/* 615 */ MCD_OPC_Decode, 237, 17, 188, 3, // Opcode: MOVN_NM +/* 620 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 635 +/* 625 */ MCD_OPC_CheckPredicate, 112, 125, 10, 0, // Skip to: 3315 +/* 630 */ MCD_OPC_Decode, 229, 6, 187, 3, // Opcode: AND_NM +/* 635 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 650 +/* 640 */ MCD_OPC_CheckPredicate, 112, 110, 10, 0, // Skip to: 3315 +/* 645 */ MCD_OPC_Decode, 173, 19, 187, 3, // Opcode: OR_NM +/* 650 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 665 +/* 655 */ MCD_OPC_CheckPredicate, 112, 95, 10, 0, // Skip to: 3315 +/* 660 */ MCD_OPC_Decode, 156, 19, 187, 3, // Opcode: NOR_NM +/* 665 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 680 +/* 670 */ MCD_OPC_CheckPredicate, 112, 80, 10, 0, // Skip to: 3315 +/* 675 */ MCD_OPC_Decode, 182, 24, 187, 3, // Opcode: XOR_NM +/* 680 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 695 +/* 685 */ MCD_OPC_CheckPredicate, 112, 65, 10, 0, // Skip to: 3315 +/* 690 */ MCD_OPC_Decode, 245, 21, 187, 3, // Opcode: SLT_NM +/* 695 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 710 +/* 700 */ MCD_OPC_CheckPredicate, 112, 50, 10, 0, // Skip to: 3315 +/* 705 */ MCD_OPC_Decode, 243, 21, 187, 3, // Opcode: SLTU_NM +/* 710 */ MCD_OPC_FilterValue, 15, 40, 10, 0, // Skip to: 3315 +/* 715 */ MCD_OPC_CheckPredicate, 112, 35, 10, 0, // Skip to: 3315 +/* 720 */ MCD_OPC_Decode, 129, 22, 187, 3, // Opcode: SOV_NM +/* 725 */ MCD_OPC_FilterValue, 8, 123, 0, 0, // Skip to: 853 +/* 730 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 733 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 748 +/* 738 */ MCD_OPC_CheckPredicate, 112, 12, 10, 0, // Skip to: 3315 +/* 743 */ MCD_OPC_Decode, 247, 18, 187, 3, // Opcode: MUL_NM +/* 748 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 763 +/* 753 */ MCD_OPC_CheckPredicate, 112, 253, 9, 0, // Skip to: 3315 +/* 758 */ MCD_OPC_Decode, 204, 18, 187, 3, // Opcode: MUH_NM +/* 763 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 778 +/* 768 */ MCD_OPC_CheckPredicate, 112, 238, 9, 0, // Skip to: 3315 +/* 773 */ MCD_OPC_Decode, 240, 18, 187, 3, // Opcode: MULU_NM +/* 778 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 793 +/* 783 */ MCD_OPC_CheckPredicate, 112, 223, 9, 0, // Skip to: 3315 +/* 788 */ MCD_OPC_Decode, 202, 18, 187, 3, // Opcode: MUHU_NM +/* 793 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 808 +/* 798 */ MCD_OPC_CheckPredicate, 112, 208, 9, 0, // Skip to: 3315 +/* 803 */ MCD_OPC_Decode, 223, 11, 187, 3, // Opcode: DIV_NM +/* 808 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 823 +/* 813 */ MCD_OPC_CheckPredicate, 112, 193, 9, 0, // Skip to: 3315 +/* 818 */ MCD_OPC_Decode, 199, 17, 187, 3, // Opcode: MOD_NM +/* 823 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 838 +/* 828 */ MCD_OPC_CheckPredicate, 112, 178, 9, 0, // Skip to: 3315 +/* 833 */ MCD_OPC_Decode, 221, 11, 187, 3, // Opcode: DIVU_NM +/* 838 */ MCD_OPC_FilterValue, 7, 168, 9, 0, // Skip to: 3315 +/* 843 */ MCD_OPC_CheckPredicate, 112, 163, 9, 0, // Skip to: 3315 +/* 848 */ MCD_OPC_Decode, 197, 17, 187, 3, // Opcode: MODU_NM +/* 853 */ MCD_OPC_FilterValue, 15, 153, 9, 0, // Skip to: 3315 +/* 858 */ MCD_OPC_CheckPredicate, 112, 148, 9, 0, // Skip to: 3315 +/* 863 */ MCD_OPC_Decode, 254, 12, 189, 3, // Opcode: EXTW_NM +/* 868 */ MCD_OPC_FilterValue, 2, 194, 0, 0, // Skip to: 1067 +/* 873 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 876 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 898 +/* 881 */ MCD_OPC_CheckPredicate, 113, 125, 9, 0, // Skip to: 3315 +/* 886 */ MCD_OPC_CheckField, 0, 4, 8, 118, 9, 0, // Skip to: 3315 +/* 893 */ MCD_OPC_Decode, 255, 13, 190, 3, // Opcode: FORK_NM +/* 898 */ MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 927 +/* 903 */ MCD_OPC_CheckPredicate, 113, 103, 9, 0, // Skip to: 3315 +/* 908 */ MCD_OPC_CheckField, 10, 6, 0, 96, 9, 0, // Skip to: 3315 +/* 915 */ MCD_OPC_CheckField, 0, 4, 8, 89, 9, 0, // Skip to: 3315 +/* 922 */ MCD_OPC_Decode, 189, 24, 185, 3, // Opcode: YIELD_NM +/* 927 */ MCD_OPC_FilterValue, 15, 79, 9, 0, // Skip to: 3315 +/* 932 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 935 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 957 +/* 940 */ MCD_OPC_CheckPredicate, 114, 66, 9, 0, // Skip to: 3315 +/* 945 */ MCD_OPC_CheckField, 0, 4, 8, 59, 9, 0, // Skip to: 3315 +/* 952 */ MCD_OPC_Decode, 166, 10, 191, 3, // Opcode: CRC32B_NM +/* 957 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 979 +/* 962 */ MCD_OPC_CheckPredicate, 114, 44, 9, 0, // Skip to: 3315 +/* 967 */ MCD_OPC_CheckField, 0, 4, 8, 37, 9, 0, // Skip to: 3315 +/* 974 */ MCD_OPC_Decode, 176, 10, 191, 3, // Opcode: CRC32H_NM +/* 979 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1001 +/* 984 */ MCD_OPC_CheckPredicate, 114, 22, 9, 0, // Skip to: 3315 +/* 989 */ MCD_OPC_CheckField, 0, 4, 8, 15, 9, 0, // Skip to: 3315 +/* 996 */ MCD_OPC_Decode, 178, 10, 191, 3, // Opcode: CRC32W_NM +/* 1001 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 1023 +/* 1006 */ MCD_OPC_CheckPredicate, 114, 0, 9, 0, // Skip to: 3315 +/* 1011 */ MCD_OPC_CheckField, 0, 4, 8, 249, 8, 0, // Skip to: 3315 +/* 1018 */ MCD_OPC_Decode, 168, 10, 191, 3, // Opcode: CRC32CB_NM +/* 1023 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 1045 +/* 1028 */ MCD_OPC_CheckPredicate, 114, 234, 8, 0, // Skip to: 3315 +/* 1033 */ MCD_OPC_CheckField, 0, 4, 8, 227, 8, 0, // Skip to: 3315 +/* 1040 */ MCD_OPC_Decode, 171, 10, 191, 3, // Opcode: CRC32CH_NM +/* 1045 */ MCD_OPC_FilterValue, 6, 217, 8, 0, // Skip to: 3315 +/* 1050 */ MCD_OPC_CheckPredicate, 114, 212, 8, 0, // Skip to: 3315 +/* 1055 */ MCD_OPC_CheckField, 0, 4, 8, 205, 8, 0, // Skip to: 3315 +/* 1062 */ MCD_OPC_Decode, 173, 10, 191, 3, // Opcode: CRC32CW_NM +/* 1067 */ MCD_OPC_FilterValue, 3, 195, 8, 0, // Skip to: 3315 +/* 1072 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 1075 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1113 +/* 1080 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 1083 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1098 +/* 1088 */ MCD_OPC_CheckPredicate, 112, 174, 8, 0, // Skip to: 3315 +/* 1093 */ MCD_OPC_Decode, 129, 17, 192, 3, // Opcode: MFC0Sel_NM +/* 1098 */ MCD_OPC_FilterValue, 8, 164, 8, 0, // Skip to: 3315 +/* 1103 */ MCD_OPC_CheckPredicate, 112, 159, 8, 0, // Skip to: 3315 +/* 1108 */ MCD_OPC_Decode, 140, 17, 192, 3, // Opcode: MFHC0Sel_NM +/* 1113 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 1151 +/* 1118 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 1121 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1136 +/* 1126 */ MCD_OPC_CheckPredicate, 112, 136, 8, 0, // Skip to: 3315 +/* 1131 */ MCD_OPC_Decode, 157, 18, 192, 3, // Opcode: MTC0Sel_NM +/* 1136 */ MCD_OPC_FilterValue, 8, 126, 8, 0, // Skip to: 3315 +/* 1141 */ MCD_OPC_CheckPredicate, 112, 121, 8, 0, // Skip to: 3315 +/* 1146 */ MCD_OPC_Decode, 169, 18, 192, 3, // Opcode: MTHC0Sel_NM +/* 1151 */ MCD_OPC_FilterValue, 5, 47, 0, 0, // Skip to: 1203 +/* 1156 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 1159 */ MCD_OPC_FilterValue, 56, 17, 0, 0, // Skip to: 1181 +/* 1164 */ MCD_OPC_CheckPredicate, 112, 98, 8, 0, // Skip to: 3315 +/* 1169 */ MCD_OPC_CheckField, 0, 4, 15, 91, 8, 0, // Skip to: 3315 +/* 1176 */ MCD_OPC_Decode, 133, 20, 185, 3, // Opcode: RDPGPR_NM +/* 1181 */ MCD_OPC_FilterValue, 60, 81, 8, 0, // Skip to: 3315 +/* 1186 */ MCD_OPC_CheckPredicate, 112, 76, 8, 0, // Skip to: 3315 +/* 1191 */ MCD_OPC_CheckField, 0, 4, 15, 69, 8, 0, // Skip to: 3315 +/* 1198 */ MCD_OPC_Decode, 168, 24, 185, 3, // Opcode: WRPGPR_NM +/* 1203 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 1225 +/* 1208 */ MCD_OPC_CheckPredicate, 113, 54, 8, 0, // Skip to: 3315 +/* 1213 */ MCD_OPC_CheckField, 0, 3, 0, 47, 8, 0, // Skip to: 3315 +/* 1220 */ MCD_OPC_Decode, 163, 17, 193, 3, // Opcode: MFTR_NM +/* 1225 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 1247 +/* 1230 */ MCD_OPC_CheckPredicate, 113, 32, 8, 0, // Skip to: 3315 +/* 1235 */ MCD_OPC_CheckField, 0, 3, 0, 25, 8, 0, // Skip to: 3315 +/* 1242 */ MCD_OPC_Decode, 198, 18, 194, 3, // Opcode: MTTR_NM +/* 1247 */ MCD_OPC_FilterValue, 10, 91, 0, 0, // Skip to: 1343 +/* 1252 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... +/* 1255 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1277 +/* 1260 */ MCD_OPC_CheckPredicate, 113, 2, 8, 0, // Skip to: 3315 +/* 1265 */ MCD_OPC_CheckField, 0, 4, 0, 251, 7, 0, // Skip to: 3315 +/* 1272 */ MCD_OPC_Decode, 202, 12, 195, 3, // Opcode: DVPE_NM +/* 1277 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 1299 +/* 1282 */ MCD_OPC_CheckPredicate, 113, 236, 7, 0, // Skip to: 3315 +/* 1287 */ MCD_OPC_CheckField, 0, 4, 0, 229, 7, 0, // Skip to: 3315 +/* 1294 */ MCD_OPC_Decode, 225, 12, 195, 3, // Opcode: EVPE_NM +/* 1299 */ MCD_OPC_FilterValue, 66, 17, 0, 0, // Skip to: 1321 +/* 1304 */ MCD_OPC_CheckPredicate, 113, 214, 7, 0, // Skip to: 3315 +/* 1309 */ MCD_OPC_CheckField, 0, 4, 0, 207, 7, 0, // Skip to: 3315 +/* 1316 */ MCD_OPC_Decode, 250, 11, 195, 3, // Opcode: DMT_NM +/* 1321 */ MCD_OPC_FilterValue, 67, 197, 7, 0, // Skip to: 3315 +/* 1326 */ MCD_OPC_CheckPredicate, 113, 192, 7, 0, // Skip to: 3315 +/* 1331 */ MCD_OPC_CheckField, 0, 4, 0, 185, 7, 0, // Skip to: 3315 +/* 1338 */ MCD_OPC_Decode, 215, 12, 195, 3, // Opcode: EMT_NM +/* 1343 */ MCD_OPC_FilterValue, 12, 47, 0, 0, // Skip to: 1395 +/* 1348 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 1351 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 1373 +/* 1356 */ MCD_OPC_CheckPredicate, 112, 162, 7, 0, // Skip to: 3315 +/* 1361 */ MCD_OPC_CheckField, 0, 4, 15, 155, 7, 0, // Skip to: 3315 +/* 1368 */ MCD_OPC_Decode, 175, 9, 185, 3, // Opcode: CLO_NM +/* 1373 */ MCD_OPC_FilterValue, 22, 145, 7, 0, // Skip to: 3315 +/* 1378 */ MCD_OPC_CheckPredicate, 112, 140, 7, 0, // Skip to: 3315 +/* 1383 */ MCD_OPC_CheckField, 0, 4, 15, 133, 7, 0, // Skip to: 3315 +/* 1390 */ MCD_OPC_Decode, 196, 9, 185, 3, // Opcode: CLZ_NM +/* 1395 */ MCD_OPC_FilterValue, 13, 123, 7, 0, // Skip to: 3315 +/* 1400 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 1403 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1424 +/* 1408 */ MCD_OPC_CheckPredicate, 115, 110, 7, 0, // Skip to: 3315 +/* 1413 */ MCD_OPC_CheckField, 0, 4, 15, 103, 7, 0, // Skip to: 3315 +/* 1420 */ MCD_OPC_Decode, 240, 23, 10, // Opcode: TLBP_NM +/* 1424 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 1445 +/* 1429 */ MCD_OPC_CheckPredicate, 115, 89, 7, 0, // Skip to: 3315 +/* 1434 */ MCD_OPC_CheckField, 0, 4, 15, 82, 7, 0, // Skip to: 3315 +/* 1441 */ MCD_OPC_Decode, 237, 23, 10, // Opcode: TLBINV_NM +/* 1445 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 1467 +/* 1450 */ MCD_OPC_CheckPredicate, 116, 68, 7, 0, // Skip to: 3315 +/* 1455 */ MCD_OPC_CheckField, 0, 4, 15, 61, 7, 0, // Skip to: 3315 +/* 1462 */ MCD_OPC_Decode, 189, 14, 196, 3, // Opcode: GINVT_NM +/* 1467 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 1488 +/* 1472 */ MCD_OPC_CheckPredicate, 115, 46, 7, 0, // Skip to: 3315 +/* 1477 */ MCD_OPC_CheckField, 0, 4, 15, 39, 7, 0, // Skip to: 3315 +/* 1484 */ MCD_OPC_Decode, 243, 23, 10, // Opcode: TLBR_NM +/* 1488 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 1509 +/* 1493 */ MCD_OPC_CheckPredicate, 115, 25, 7, 0, // Skip to: 3315 +/* 1498 */ MCD_OPC_CheckField, 0, 4, 15, 18, 7, 0, // Skip to: 3315 +/* 1505 */ MCD_OPC_Decode, 235, 23, 10, // Opcode: TLBINVF_NM +/* 1509 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 1531 +/* 1514 */ MCD_OPC_CheckPredicate, 116, 4, 7, 0, // Skip to: 3315 +/* 1519 */ MCD_OPC_CheckField, 0, 4, 15, 253, 6, 0, // Skip to: 3315 +/* 1526 */ MCD_OPC_Decode, 186, 14, 197, 3, // Opcode: GINVI_NM +/* 1531 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 1552 +/* 1536 */ MCD_OPC_CheckPredicate, 115, 238, 6, 0, // Skip to: 3315 +/* 1541 */ MCD_OPC_CheckField, 0, 4, 15, 231, 6, 0, // Skip to: 3315 +/* 1548 */ MCD_OPC_Decode, 246, 23, 10, // Opcode: TLBWI_NM +/* 1552 */ MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 1573 +/* 1557 */ MCD_OPC_CheckPredicate, 115, 217, 6, 0, // Skip to: 3315 +/* 1562 */ MCD_OPC_CheckField, 0, 4, 15, 210, 6, 0, // Skip to: 3315 +/* 1569 */ MCD_OPC_Decode, 249, 23, 10, // Opcode: TLBWR_NM +/* 1573 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 1595 +/* 1578 */ MCD_OPC_CheckPredicate, 112, 196, 6, 0, // Skip to: 3315 +/* 1583 */ MCD_OPC_CheckField, 0, 4, 15, 189, 6, 0, // Skip to: 3315 +/* 1590 */ MCD_OPC_Decode, 234, 11, 195, 3, // Opcode: DI_NM +/* 1595 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 1617 +/* 1600 */ MCD_OPC_CheckPredicate, 112, 174, 6, 0, // Skip to: 3315 +/* 1605 */ MCD_OPC_CheckField, 0, 4, 15, 167, 6, 0, // Skip to: 3315 +/* 1612 */ MCD_OPC_Decode, 213, 12, 195, 3, // Opcode: EI_NM +/* 1617 */ MCD_OPC_FilterValue, 48, 16, 0, 0, // Skip to: 1638 +/* 1622 */ MCD_OPC_CheckPredicate, 112, 152, 6, 0, // Skip to: 3315 +/* 1627 */ MCD_OPC_CheckField, 0, 4, 15, 145, 6, 0, // Skip to: 3315 +/* 1634 */ MCD_OPC_Decode, 164, 24, 88, // Opcode: WAIT_NM +/* 1638 */ MCD_OPC_FilterValue, 56, 16, 0, 0, // Skip to: 1659 +/* 1643 */ MCD_OPC_CheckPredicate, 112, 131, 6, 0, // Skip to: 3315 +/* 1648 */ MCD_OPC_CheckField, 0, 4, 15, 124, 6, 0, // Skip to: 3315 +/* 1655 */ MCD_OPC_Decode, 209, 11, 10, // Opcode: DERET_NM +/* 1659 */ MCD_OPC_FilterValue, 60, 115, 6, 0, // Skip to: 3315 +/* 1664 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1667 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1688 +/* 1672 */ MCD_OPC_CheckPredicate, 112, 102, 6, 0, // Skip to: 3315 +/* 1677 */ MCD_OPC_CheckField, 0, 4, 15, 95, 6, 0, // Skip to: 3315 +/* 1684 */ MCD_OPC_Decode, 222, 12, 10, // Opcode: ERET_NM +/* 1688 */ MCD_OPC_FilterValue, 1, 86, 6, 0, // Skip to: 3315 +/* 1693 */ MCD_OPC_CheckPredicate, 112, 81, 6, 0, // Skip to: 3315 +/* 1698 */ MCD_OPC_CheckField, 0, 4, 15, 74, 6, 0, // Skip to: 3315 +/* 1705 */ MCD_OPC_Decode, 219, 12, 10, // Opcode: ERETNC_NM +/* 1709 */ MCD_OPC_FilterValue, 10, 33, 0, 0, // Skip to: 1747 +/* 1714 */ MCD_OPC_ExtractField, 25, 1, // Inst{25} ... +/* 1717 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1732 +/* 1722 */ MCD_OPC_CheckPredicate, 112, 52, 6, 0, // Skip to: 3315 +/* 1727 */ MCD_OPC_Decode, 187, 7, 198, 3, // Opcode: BC_NM +/* 1732 */ MCD_OPC_FilterValue, 1, 42, 6, 0, // Skip to: 3315 +/* 1737 */ MCD_OPC_CheckPredicate, 112, 37, 6, 0, // Skip to: 3315 +/* 1742 */ MCD_OPC_Decode, 151, 7, 198, 3, // Opcode: BALC_NM +/* 1747 */ MCD_OPC_FilterValue, 16, 48, 0, 0, // Skip to: 1800 +/* 1752 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 1755 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1770 +/* 1760 */ MCD_OPC_CheckPredicate, 112, 14, 6, 0, // Skip to: 3315 +/* 1765 */ MCD_OPC_Decode, 255, 5, 199, 3, // Opcode: ADDIUGPW_NM +/* 1770 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1785 +/* 1775 */ MCD_OPC_CheckPredicate, 112, 255, 5, 0, // Skip to: 3315 +/* 1780 */ MCD_OPC_Decode, 148, 16, 200, 3, // Opcode: LWGP_NM +/* 1785 */ MCD_OPC_FilterValue, 3, 245, 5, 0, // Skip to: 3315 +/* 1790 */ MCD_OPC_CheckPredicate, 112, 240, 5, 0, // Skip to: 3315 +/* 1795 */ MCD_OPC_Decode, 145, 23, 200, 3, // Opcode: SWGP_NM +/* 1800 */ MCD_OPC_FilterValue, 17, 123, 0, 0, // Skip to: 1928 +/* 1805 */ MCD_OPC_ExtractField, 18, 3, // Inst{20-18} ... +/* 1808 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1823 +/* 1813 */ MCD_OPC_CheckPredicate, 112, 217, 5, 0, // Skip to: 3315 +/* 1818 */ MCD_OPC_Decode, 159, 15, 201, 3, // Opcode: LBGP_NM +/* 1823 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1838 +/* 1828 */ MCD_OPC_CheckPredicate, 112, 202, 5, 0, // Skip to: 3315 +/* 1833 */ MCD_OPC_Decode, 200, 20, 201, 3, // Opcode: SBGP_NM +/* 1838 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1853 +/* 1843 */ MCD_OPC_CheckPredicate, 112, 187, 5, 0, // Skip to: 3315 +/* 1848 */ MCD_OPC_Decode, 162, 15, 201, 3, // Opcode: LBUGP_NM +/* 1853 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1868 +/* 1858 */ MCD_OPC_CheckPredicate, 112, 172, 5, 0, // Skip to: 3315 +/* 1863 */ MCD_OPC_Decode, 254, 5, 202, 3, // Opcode: ADDIUGPB_NM +/* 1868 */ MCD_OPC_FilterValue, 4, 33, 0, 0, // Skip to: 1906 +/* 1873 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 1876 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1891 +/* 1881 */ MCD_OPC_CheckPredicate, 112, 149, 5, 0, // Skip to: 3315 +/* 1886 */ MCD_OPC_Decode, 211, 15, 203, 3, // Opcode: LHGP_NM +/* 1891 */ MCD_OPC_FilterValue, 1, 139, 5, 0, // Skip to: 3315 +/* 1896 */ MCD_OPC_CheckPredicate, 112, 134, 5, 0, // Skip to: 3315 +/* 1901 */ MCD_OPC_Decode, 214, 15, 203, 3, // Opcode: LHUGP_NM +/* 1906 */ MCD_OPC_FilterValue, 5, 124, 5, 0, // Skip to: 3315 +/* 1911 */ MCD_OPC_CheckPredicate, 112, 119, 5, 0, // Skip to: 3315 +/* 1916 */ MCD_OPC_CheckField, 0, 1, 0, 112, 5, 0, // Skip to: 3315 +/* 1923 */ MCD_OPC_Decode, 153, 21, 203, 3, // Opcode: SHGP_NM +/* 1928 */ MCD_OPC_FilterValue, 18, 65, 0, 0, // Skip to: 1998 +/* 1933 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 1936 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1951 +/* 1941 */ MCD_OPC_CheckPredicate, 112, 89, 5, 0, // Skip to: 3315 +/* 1946 */ MCD_OPC_Decode, 244, 14, 185, 3, // Opcode: JALRC_NM +/* 1951 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1966 +/* 1956 */ MCD_OPC_CheckPredicate, 112, 74, 5, 0, // Skip to: 3315 +/* 1961 */ MCD_OPC_Decode, 241, 14, 185, 3, // Opcode: JALRCHB_NM +/* 1966 */ MCD_OPC_FilterValue, 8, 64, 5, 0, // Skip to: 3315 +/* 1971 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 1988 +/* 1976 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 1988 +/* 1983 */ MCD_OPC_Decode, 218, 8, 197, 3, // Opcode: BRSC_NM +/* 1988 */ MCD_OPC_CheckPredicate, 112, 42, 5, 0, // Skip to: 3315 +/* 1993 */ MCD_OPC_Decode, 154, 7, 204, 3, // Opcode: BALRSC_NM +/* 1998 */ MCD_OPC_FilterValue, 32, 217, 1, 0, // Skip to: 2476 +/* 2003 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 2006 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2021 +/* 2011 */ MCD_OPC_CheckPredicate, 112, 19, 5, 0, // Skip to: 3315 +/* 2016 */ MCD_OPC_Decode, 170, 19, 205, 3, // Opcode: ORI_NM +/* 2021 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2036 +/* 2026 */ MCD_OPC_CheckPredicate, 112, 4, 5, 0, // Skip to: 3315 +/* 2031 */ MCD_OPC_Decode, 179, 24, 205, 3, // Opcode: XORI_NM +/* 2036 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2051 +/* 2041 */ MCD_OPC_CheckPredicate, 112, 245, 4, 0, // Skip to: 3315 +/* 2046 */ MCD_OPC_Decode, 226, 6, 205, 3, // Opcode: ANDI_NM +/* 2051 */ MCD_OPC_FilterValue, 3, 69, 0, 0, // Skip to: 2125 +/* 2056 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 2059 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2081 +/* 2064 */ MCD_OPC_CheckPredicate, 112, 222, 4, 0, // Skip to: 3315 +/* 2069 */ MCD_OPC_CheckField, 20, 1, 0, 215, 4, 0, // Skip to: 3315 +/* 2076 */ MCD_OPC_Decode, 192, 20, 206, 3, // Opcode: SAVE_NM +/* 2081 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 2103 +/* 2086 */ MCD_OPC_CheckPredicate, 112, 200, 4, 0, // Skip to: 3315 +/* 2091 */ MCD_OPC_CheckField, 20, 1, 0, 193, 4, 0, // Skip to: 3315 +/* 2098 */ MCD_OPC_Decode, 150, 20, 206, 3, // Opcode: RESTORE_NM +/* 2103 */ MCD_OPC_FilterValue, 3, 183, 4, 0, // Skip to: 3315 +/* 2108 */ MCD_OPC_CheckPredicate, 112, 178, 4, 0, // Skip to: 3315 +/* 2113 */ MCD_OPC_CheckField, 20, 1, 0, 171, 4, 0, // Skip to: 3315 +/* 2120 */ MCD_OPC_Decode, 149, 20, 206, 3, // Opcode: RESTOREJRC_NM +/* 2125 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 2140 +/* 2130 */ MCD_OPC_CheckPredicate, 112, 156, 4, 0, // Skip to: 3315 +/* 2135 */ MCD_OPC_Decode, 242, 21, 205, 3, // Opcode: SLTI_NM +/* 2140 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 2155 +/* 2145 */ MCD_OPC_CheckPredicate, 112, 141, 4, 0, // Skip to: 3315 +/* 2150 */ MCD_OPC_Decode, 241, 21, 205, 3, // Opcode: SLTIU_NM +/* 2155 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 2170 +/* 2160 */ MCD_OPC_CheckPredicate, 112, 126, 4, 0, // Skip to: 3315 +/* 2165 */ MCD_OPC_Decode, 141, 21, 205, 3, // Opcode: SEQI_NM +/* 2170 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 2185 +/* 2175 */ MCD_OPC_CheckPredicate, 112, 111, 4, 0, // Skip to: 3315 +/* 2180 */ MCD_OPC_Decode, 128, 6, 207, 3, // Opcode: ADDIUNEG_NM +/* 2185 */ MCD_OPC_FilterValue, 12, 150, 0, 0, // Skip to: 2340 +/* 2190 */ MCD_OPC_ExtractField, 5, 4, // Inst{8-5} ... +/* 2193 */ MCD_OPC_FilterValue, 0, 97, 0, 0, // Skip to: 2295 +/* 2198 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 2201 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2222 +/* 2206 */ MCD_OPC_CheckPredicate, 112, 74, 0, 0, // Skip to: 2285 +/* 2211 */ MCD_OPC_CheckField, 16, 10, 0, 67, 0, 0, // Skip to: 2285 +/* 2218 */ MCD_OPC_Decode, 149, 19, 10, // Opcode: NOP32_NM +/* 2222 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 2243 +/* 2227 */ MCD_OPC_CheckPredicate, 112, 53, 0, 0, // Skip to: 2285 +/* 2232 */ MCD_OPC_CheckField, 16, 10, 0, 46, 0, 0, // Skip to: 2285 +/* 2239 */ MCD_OPC_Decode, 209, 12, 10, // Opcode: EHB_NM +/* 2243 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 2264 +/* 2248 */ MCD_OPC_CheckPredicate, 112, 32, 0, 0, // Skip to: 2285 +/* 2253 */ MCD_OPC_CheckField, 16, 10, 0, 25, 0, 0, // Skip to: 2285 +/* 2260 */ MCD_OPC_Decode, 184, 19, 10, // Opcode: PAUSE_NM +/* 2264 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 2285 +/* 2269 */ MCD_OPC_CheckPredicate, 112, 11, 0, 0, // Skip to: 2285 +/* 2274 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 2285 +/* 2281 */ MCD_OPC_Decode, 181, 23, 87, // Opcode: SYNC_NM +/* 2285 */ MCD_OPC_CheckPredicate, 112, 1, 4, 0, // Skip to: 3315 +/* 2290 */ MCD_OPC_Decode, 237, 21, 208, 3, // Opcode: SLL_NM +/* 2295 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2310 +/* 2300 */ MCD_OPC_CheckPredicate, 112, 242, 3, 0, // Skip to: 3315 +/* 2305 */ MCD_OPC_Decode, 183, 22, 208, 3, // Opcode: SRL_NM +/* 2310 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 2325 +/* 2315 */ MCD_OPC_CheckPredicate, 112, 227, 3, 0, // Skip to: 3315 +/* 2320 */ MCD_OPC_Decode, 158, 22, 208, 3, // Opcode: SRA_NM +/* 2325 */ MCD_OPC_FilterValue, 6, 217, 3, 0, // Skip to: 3315 +/* 2330 */ MCD_OPC_CheckPredicate, 112, 212, 3, 0, // Skip to: 3315 +/* 2335 */ MCD_OPC_Decode, 160, 20, 208, 3, // Opcode: ROTR_NM +/* 2340 */ MCD_OPC_FilterValue, 13, 73, 0, 0, // Skip to: 2418 +/* 2345 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 2348 */ MCD_OPC_FilterValue, 0, 194, 3, 0, // Skip to: 3315 +/* 2353 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 2356 */ MCD_OPC_FilterValue, 0, 186, 3, 0, // Skip to: 3315 +/* 2361 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 2364 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 2386 +/* 2369 */ MCD_OPC_CheckPredicate, 112, 34, 0, 0, // Skip to: 2408 +/* 2374 */ MCD_OPC_CheckField, 6, 5, 8, 27, 0, 0, // Skip to: 2408 +/* 2381 */ MCD_OPC_Decode, 229, 8, 185, 3, // Opcode: BYTEREVW_NM +/* 2386 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 2408 +/* 2391 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 2408 +/* 2396 */ MCD_OPC_CheckField, 6, 5, 0, 5, 0, 0, // Skip to: 2408 +/* 2403 */ MCD_OPC_Decode, 130, 8, 185, 3, // Opcode: BITREVW_NM +/* 2408 */ MCD_OPC_CheckPredicate, 112, 134, 3, 0, // Skip to: 3315 +/* 2413 */ MCD_OPC_Decode, 161, 20, 209, 3, // Opcode: ROTX_NM +/* 2418 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 2447 +/* 2423 */ MCD_OPC_CheckPredicate, 112, 119, 3, 0, // Skip to: 3315 +/* 2428 */ MCD_OPC_CheckField, 11, 1, 0, 112, 3, 0, // Skip to: 3315 +/* 2435 */ MCD_OPC_CheckField, 5, 1, 0, 105, 3, 0, // Skip to: 3315 +/* 2442 */ MCD_OPC_Decode, 233, 14, 210, 3, // Opcode: INS_NM +/* 2447 */ MCD_OPC_FilterValue, 15, 95, 3, 0, // Skip to: 3315 +/* 2452 */ MCD_OPC_CheckPredicate, 112, 90, 3, 0, // Skip to: 3315 +/* 2457 */ MCD_OPC_CheckField, 11, 1, 0, 83, 3, 0, // Skip to: 3315 +/* 2464 */ MCD_OPC_CheckField, 5, 1, 0, 76, 3, 0, // Skip to: 3315 +/* 2471 */ MCD_OPC_Decode, 129, 13, 211, 3, // Opcode: EXT_NM +/* 2476 */ MCD_OPC_FilterValue, 33, 155, 0, 0, // Skip to: 2636 +/* 2481 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 2484 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2499 +/* 2489 */ MCD_OPC_CheckPredicate, 112, 53, 3, 0, // Skip to: 3315 +/* 2494 */ MCD_OPC_Decode, 172, 15, 212, 3, // Opcode: LB_NM +/* 2499 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2514 +/* 2504 */ MCD_OPC_CheckPredicate, 112, 38, 3, 0, // Skip to: 3315 +/* 2509 */ MCD_OPC_Decode, 204, 20, 212, 3, // Opcode: SB_NM +/* 2514 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2529 +/* 2519 */ MCD_OPC_CheckPredicate, 112, 23, 3, 0, // Skip to: 3315 +/* 2524 */ MCD_OPC_Decode, 167, 15, 212, 3, // Opcode: LBU_NM +/* 2529 */ MCD_OPC_FilterValue, 3, 27, 0, 0, // Skip to: 2561 +/* 2534 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 2551 +/* 2539 */ MCD_OPC_CheckField, 21, 5, 31, 5, 0, 0, // Skip to: 2551 +/* 2546 */ MCD_OPC_Decode, 177, 23, 213, 3, // Opcode: SYNCI_NM +/* 2551 */ MCD_OPC_CheckPredicate, 112, 247, 2, 0, // Skip to: 3315 +/* 2556 */ MCD_OPC_Decode, 244, 19, 214, 3, // Opcode: PREF_NM +/* 2561 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 2576 +/* 2566 */ MCD_OPC_CheckPredicate, 112, 232, 2, 0, // Skip to: 3315 +/* 2571 */ MCD_OPC_Decode, 224, 15, 212, 3, // Opcode: LH_NM +/* 2576 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 2591 +/* 2581 */ MCD_OPC_CheckPredicate, 112, 217, 2, 0, // Skip to: 3315 +/* 2586 */ MCD_OPC_Decode, 206, 21, 212, 3, // Opcode: SH_NM +/* 2591 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 2606 +/* 2596 */ MCD_OPC_CheckPredicate, 112, 202, 2, 0, // Skip to: 3315 +/* 2601 */ MCD_OPC_Decode, 217, 15, 212, 3, // Opcode: LHU_NM +/* 2606 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 2621 +/* 2611 */ MCD_OPC_CheckPredicate, 112, 187, 2, 0, // Skip to: 3315 +/* 2616 */ MCD_OPC_Decode, 181, 16, 212, 3, // Opcode: LW_NM +/* 2621 */ MCD_OPC_FilterValue, 9, 177, 2, 0, // Skip to: 3315 +/* 2626 */ MCD_OPC_CheckPredicate, 112, 172, 2, 0, // Skip to: 3315 +/* 2631 */ MCD_OPC_Decode, 171, 23, 212, 3, // Opcode: SW_NM +/* 2636 */ MCD_OPC_FilterValue, 34, 48, 0, 0, // Skip to: 2689 +/* 2641 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 2644 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2659 +/* 2649 */ MCD_OPC_CheckPredicate, 112, 149, 2, 0, // Skip to: 3315 +/* 2654 */ MCD_OPC_Decode, 194, 7, 215, 3, // Opcode: BEQC_NM +/* 2659 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2674 +/* 2664 */ MCD_OPC_CheckPredicate, 112, 134, 2, 0, // Skip to: 3315 +/* 2669 */ MCD_OPC_Decode, 212, 7, 215, 3, // Opcode: BGEC_NM +/* 2674 */ MCD_OPC_FilterValue, 3, 124, 2, 0, // Skip to: 3315 +/* 2679 */ MCD_OPC_CheckPredicate, 112, 119, 2, 0, // Skip to: 3315 +/* 2684 */ MCD_OPC_Decode, 218, 7, 215, 3, // Opcode: BGEUC_NM +/* 2689 */ MCD_OPC_FilterValue, 41, 146, 1, 0, // Skip to: 3096 +/* 2694 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 2697 */ MCD_OPC_FilterValue, 0, 78, 0, 0, // Skip to: 2780 +/* 2702 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... +/* 2705 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2720 +/* 2710 */ MCD_OPC_CheckPredicate, 112, 88, 2, 0, // Skip to: 3315 +/* 2715 */ MCD_OPC_Decode, 173, 15, 216, 3, // Opcode: LBs9_NM +/* 2720 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2735 +/* 2725 */ MCD_OPC_CheckPredicate, 112, 73, 2, 0, // Skip to: 3315 +/* 2730 */ MCD_OPC_Decode, 168, 15, 216, 3, // Opcode: LBUs9_NM +/* 2735 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2750 +/* 2740 */ MCD_OPC_CheckPredicate, 112, 58, 2, 0, // Skip to: 3315 +/* 2745 */ MCD_OPC_Decode, 225, 15, 216, 3, // Opcode: LHs9_NM +/* 2750 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 2765 +/* 2755 */ MCD_OPC_CheckPredicate, 112, 43, 2, 0, // Skip to: 3315 +/* 2760 */ MCD_OPC_Decode, 218, 15, 216, 3, // Opcode: LHUs9_NM +/* 2765 */ MCD_OPC_FilterValue, 4, 33, 2, 0, // Skip to: 3315 +/* 2770 */ MCD_OPC_CheckPredicate, 112, 28, 2, 0, // Skip to: 3315 +/* 2775 */ MCD_OPC_Decode, 182, 16, 216, 3, // Opcode: LWs9_NM +/* 2780 */ MCD_OPC_FilterValue, 1, 56, 0, 0, // Skip to: 2841 +/* 2785 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... +/* 2788 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2803 +/* 2793 */ MCD_OPC_CheckPredicate, 112, 5, 2, 0, // Skip to: 3315 +/* 2798 */ MCD_OPC_Decode, 146, 24, 141, 1, // Opcode: UALH_NM +/* 2803 */ MCD_OPC_FilterValue, 5, 251, 1, 0, // Skip to: 3315 +/* 2808 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 2811 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2826 +/* 2816 */ MCD_OPC_CheckPredicate, 112, 238, 1, 0, // Skip to: 3315 +/* 2821 */ MCD_OPC_Decode, 245, 15, 217, 3, // Opcode: LL_NM +/* 2826 */ MCD_OPC_FilterValue, 1, 228, 1, 0, // Skip to: 3315 +/* 2831 */ MCD_OPC_CheckPredicate, 112, 223, 1, 0, // Skip to: 3315 +/* 2836 */ MCD_OPC_Decode, 242, 15, 218, 3, // Opcode: LLWP_NM +/* 2841 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 2856 +/* 2846 */ MCD_OPC_CheckPredicate, 112, 208, 1, 0, // Skip to: 3315 +/* 2851 */ MCD_OPC_Decode, 157, 16, 219, 3, // Opcode: LWM_NM +/* 2856 */ MCD_OPC_FilterValue, 5, 27, 0, 0, // Skip to: 2888 +/* 2861 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 2878 +/* 2866 */ MCD_OPC_CheckField, 12, 3, 1, 5, 0, 0, // Skip to: 2878 +/* 2873 */ MCD_OPC_Decode, 148, 24, 141, 1, // Opcode: UALW_NM +/* 2878 */ MCD_OPC_CheckPredicate, 112, 176, 1, 0, // Skip to: 3315 +/* 2883 */ MCD_OPC_Decode, 147, 24, 219, 3, // Opcode: UALWM_NM +/* 2888 */ MCD_OPC_FilterValue, 8, 80, 0, 0, // Skip to: 2973 +/* 2893 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... +/* 2896 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2911 +/* 2901 */ MCD_OPC_CheckPredicate, 112, 153, 1, 0, // Skip to: 3315 +/* 2906 */ MCD_OPC_Decode, 205, 20, 216, 3, // Opcode: SBs9_NM +/* 2911 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 2943 +/* 2916 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 2933 +/* 2921 */ MCD_OPC_CheckField, 21, 5, 31, 5, 0, 0, // Skip to: 2933 +/* 2928 */ MCD_OPC_Decode, 178, 23, 220, 3, // Opcode: SYNCIs9_NM +/* 2933 */ MCD_OPC_CheckPredicate, 112, 121, 1, 0, // Skip to: 3315 +/* 2938 */ MCD_OPC_Decode, 246, 19, 221, 3, // Opcode: PREFs9_NM +/* 2943 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2958 +/* 2948 */ MCD_OPC_CheckPredicate, 112, 106, 1, 0, // Skip to: 3315 +/* 2953 */ MCD_OPC_Decode, 207, 21, 216, 3, // Opcode: SHs9_NM +/* 2958 */ MCD_OPC_FilterValue, 4, 96, 1, 0, // Skip to: 3315 +/* 2963 */ MCD_OPC_CheckPredicate, 112, 91, 1, 0, // Skip to: 3315 +/* 2968 */ MCD_OPC_Decode, 172, 23, 216, 3, // Opcode: SWs9_NM +/* 2973 */ MCD_OPC_FilterValue, 9, 71, 0, 0, // Skip to: 3049 +/* 2978 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... +/* 2981 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2996 +/* 2986 */ MCD_OPC_CheckPredicate, 112, 68, 1, 0, // Skip to: 3315 +/* 2991 */ MCD_OPC_Decode, 149, 24, 141, 1, // Opcode: UASH_NM +/* 2996 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 3011 +/* 3001 */ MCD_OPC_CheckPredicate, 112, 53, 1, 0, // Skip to: 3315 +/* 3006 */ MCD_OPC_Decode, 251, 8, 221, 3, // Opcode: CACHE_NM +/* 3011 */ MCD_OPC_FilterValue, 5, 43, 1, 0, // Skip to: 3315 +/* 3016 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3019 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3034 +/* 3024 */ MCD_OPC_CheckPredicate, 112, 30, 1, 0, // Skip to: 3315 +/* 3029 */ MCD_OPC_Decode, 216, 20, 222, 3, // Opcode: SC_NM +/* 3034 */ MCD_OPC_FilterValue, 1, 20, 1, 0, // Skip to: 3315 +/* 3039 */ MCD_OPC_CheckPredicate, 112, 15, 1, 0, // Skip to: 3315 +/* 3044 */ MCD_OPC_Decode, 213, 20, 223, 3, // Opcode: SCWP_NM +/* 3049 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 3064 +/* 3054 */ MCD_OPC_CheckPredicate, 112, 0, 1, 0, // Skip to: 3315 +/* 3059 */ MCD_OPC_Decode, 154, 23, 219, 3, // Opcode: SWM_NM +/* 3064 */ MCD_OPC_FilterValue, 13, 246, 0, 0, // Skip to: 3315 +/* 3069 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 3086 +/* 3074 */ MCD_OPC_CheckField, 12, 3, 1, 5, 0, 0, // Skip to: 3086 +/* 3081 */ MCD_OPC_Decode, 151, 24, 141, 1, // Opcode: UASW_NM +/* 3086 */ MCD_OPC_CheckPredicate, 112, 224, 0, 0, // Skip to: 3315 +/* 3091 */ MCD_OPC_Decode, 150, 24, 219, 3, // Opcode: UASWM_NM +/* 3096 */ MCD_OPC_FilterValue, 42, 48, 0, 0, // Skip to: 3149 +/* 3101 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 3104 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3119 +/* 3109 */ MCD_OPC_CheckPredicate, 112, 201, 0, 0, // Skip to: 3315 +/* 3114 */ MCD_OPC_Decode, 176, 8, 215, 3, // Opcode: BNEC_NM +/* 3119 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 3134 +/* 3124 */ MCD_OPC_CheckPredicate, 112, 186, 0, 0, // Skip to: 3315 +/* 3129 */ MCD_OPC_Decode, 146, 8, 215, 3, // Opcode: BLTC_NM +/* 3134 */ MCD_OPC_FilterValue, 3, 176, 0, 0, // Skip to: 3315 +/* 3139 */ MCD_OPC_CheckPredicate, 112, 171, 0, 0, // Skip to: 3315 +/* 3144 */ MCD_OPC_Decode, 152, 8, 215, 3, // Opcode: BLTUC_NM +/* 3149 */ MCD_OPC_FilterValue, 50, 123, 0, 0, // Skip to: 3277 +/* 3154 */ MCD_OPC_ExtractField, 18, 3, // Inst{20-18} ... +/* 3157 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3172 +/* 3162 */ MCD_OPC_CheckPredicate, 112, 148, 0, 0, // Skip to: 3315 +/* 3167 */ MCD_OPC_Decode, 196, 7, 224, 3, // Opcode: BEQIC_NM +/* 3172 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 3187 +/* 3177 */ MCD_OPC_CheckPredicate, 112, 133, 0, 0, // Skip to: 3315 +/* 3182 */ MCD_OPC_Decode, 155, 7, 225, 3, // Opcode: BBEQZC_NM +/* 3187 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 3202 +/* 3192 */ MCD_OPC_CheckPredicate, 112, 118, 0, 0, // Skip to: 3315 +/* 3197 */ MCD_OPC_Decode, 213, 7, 224, 3, // Opcode: BGEIC_NM +/* 3202 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 3217 +/* 3207 */ MCD_OPC_CheckPredicate, 112, 103, 0, 0, // Skip to: 3315 +/* 3212 */ MCD_OPC_Decode, 214, 7, 224, 3, // Opcode: BGEIUC_NM +/* 3217 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 3232 +/* 3222 */ MCD_OPC_CheckPredicate, 112, 88, 0, 0, // Skip to: 3315 +/* 3227 */ MCD_OPC_Decode, 186, 8, 224, 3, // Opcode: BNEIC_NM +/* 3232 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 3247 +/* 3237 */ MCD_OPC_CheckPredicate, 112, 73, 0, 0, // Skip to: 3315 +/* 3242 */ MCD_OPC_Decode, 160, 7, 225, 3, // Opcode: BBNEZC_NM +/* 3247 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 3262 +/* 3252 */ MCD_OPC_CheckPredicate, 112, 58, 0, 0, // Skip to: 3315 +/* 3257 */ MCD_OPC_Decode, 147, 8, 224, 3, // Opcode: BLTIC_NM +/* 3262 */ MCD_OPC_FilterValue, 7, 48, 0, 0, // Skip to: 3315 +/* 3267 */ MCD_OPC_CheckPredicate, 112, 43, 0, 0, // Skip to: 3315 +/* 3272 */ MCD_OPC_Decode, 148, 8, 224, 3, // Opcode: BLTIUC_NM +/* 3277 */ MCD_OPC_FilterValue, 56, 33, 0, 0, // Skip to: 3315 +/* 3282 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 3285 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3300 +/* 3290 */ MCD_OPC_CheckPredicate, 112, 20, 0, 0, // Skip to: 3315 +/* 3295 */ MCD_OPC_Decode, 252, 15, 226, 3, // Opcode: LUI_NM +/* 3300 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 3315 +/* 3305 */ MCD_OPC_CheckPredicate, 112, 5, 0, 0, // Skip to: 3315 +/* 3310 */ MCD_OPC_Decode, 215, 6, 226, 3, // Opcode: ALUIPC_NM +/* 3315 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableNanoMips48[] = { +/* 0 */ MCD_OPC_ExtractField, 32, 5, // Inst{36-32} ... +/* 3 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 25 +/* 8 */ MCD_OPC_CheckPredicate, 112, 122, 0, 0, // Skip to: 135 +/* 13 */ MCD_OPC_CheckField, 42, 6, 24, 115, 0, 0, // Skip to: 135 +/* 20 */ MCD_OPC_Decode, 234, 15, 227, 3, // Opcode: LI48_NM +/* 25 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 47 +/* 30 */ MCD_OPC_CheckPredicate, 112, 100, 0, 0, // Skip to: 135 +/* 35 */ MCD_OPC_CheckField, 42, 6, 24, 93, 0, 0, // Skip to: 135 +/* 42 */ MCD_OPC_Decode, 252, 5, 228, 3, // Opcode: ADDIU48_NM +/* 47 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 69 +/* 52 */ MCD_OPC_CheckPredicate, 112, 78, 0, 0, // Skip to: 135 +/* 57 */ MCD_OPC_CheckField, 42, 6, 24, 71, 0, 0, // Skip to: 135 +/* 64 */ MCD_OPC_Decode, 253, 5, 229, 3, // Opcode: ADDIUGP48_NM +/* 69 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 91 +/* 74 */ MCD_OPC_CheckPredicate, 112, 56, 0, 0, // Skip to: 135 +/* 79 */ MCD_OPC_CheckField, 42, 6, 24, 49, 0, 0, // Skip to: 135 +/* 86 */ MCD_OPC_Decode, 153, 15, 230, 3, // Opcode: LAPC48_NM +/* 91 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 113 +/* 96 */ MCD_OPC_CheckPredicate, 112, 34, 0, 0, // Skip to: 135 +/* 101 */ MCD_OPC_CheckField, 42, 6, 24, 27, 0, 0, // Skip to: 135 +/* 108 */ MCD_OPC_Decode, 160, 16, 230, 3, // Opcode: LWPC_NM +/* 113 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 135 +/* 118 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 135 +/* 123 */ MCD_OPC_CheckField, 42, 6, 24, 5, 0, 0, // Skip to: 135 +/* 130 */ MCD_OPC_Decode, 155, 23, 230, 3, // Opcode: SWPC_NM +/* 135 */ MCD_OPC_Fail, + 0 +}; -static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) -{ +static const uint8_t DecoderTableNanoMips_Conflict_Space16[] = { +/* 0 */ MCD_OPC_CheckPredicate, 112, 12, 0, 0, // Skip to: 17 +/* 5 */ MCD_OPC_CheckField, 10, 6, 54, 5, 0, 0, // Skip to: 17 +/* 12 */ MCD_OPC_Decode, 173, 8, 173, 3, // Opcode: BNEC16_NM +/* 17 */ MCD_OPC_Fail, + 0 +}; + +static bool checkDecoderPredicate(MCInst *Inst, unsigned Idx) { switch (Idx) { - default: // llvm_unreachable("Invalid index!"); + default: /* llvm_unreachable("Invalid index!"); */ case 0: - return getbool((Bits & Mips_FeatureMips16)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16)); case 1: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMicroMips)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureCnMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 2: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMicroMips)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureCnMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 3: - return getbool((Bits & Mips_FeatureMicroMips)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureCnMips)); case 4: - return getbool((Bits & Mips_FeatureMips32) && (Bits & Mips_FeatureMicroMips)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureCnMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 5: - return getbool(!(Bits & Mips_FeatureMips16)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureCnMipsP)); case 6: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6)); case 7: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 8: - return getbool((Bits & Mips_FeatureMSA)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureDSP)); case 9: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureDSPR2)); case 10: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r5) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureVirt)); case 11: - return getbool(!(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureDSPR3)); case 12: - return getbool((Bits & Mips_FeatureDSP)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureDSP)); case 13: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); case 14: - return getbool((Bits & Mips_FeatureMSA) && (Bits & Mips_FeatureMips64)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNoMadd4)); case 15: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); case 16: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNoMadd4)); case 17: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); case 18: - return getbool(!(Bits & Mips_FeatureMicroMips)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); case 19: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); case 20: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2) && !(Bits & Mips_FeatureFP64Bit)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); case 21: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureEVA)); case 22: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32r2)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureEVA)); case 23: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureFP64Bit)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); case 24: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6)); case 25: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureFP64Bit)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureGINV)); case 26: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); case 27: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 28: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips5_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 29: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 30: - return getbool((Bits & Mips_FeatureDSPR2)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMSA)); case 31: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 32: - return getbool((Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6)); case 33: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureUseIndirectJumpsHazard) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 34: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips2)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32)); case 35: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 36: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 37: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64r6)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureDSP)); case 38: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureGP64Bit) && (Bits & Mips_FeatureMips32r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMSA) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64)); case 39: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureGP64Bit) && (Bits & Mips_FeatureMips32r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 40: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64r2)); + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureDSP) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 41: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r5) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureVirt) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 42: - return getbool((Bits & Mips_FeatureMips64)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMT) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 43: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2) && (Bits & Mips_FeatureFP64Bit)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3_32) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 44: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r2) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureEVA) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 45: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && (Bits & Mips_FeatureFP64Bit)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r5) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 46: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); case 47: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && (Bits & Mips_FeatureFP64Bit)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 48: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 49: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips5_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 50: - return getbool((Bits & Mips_FeatureCnMips)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 51: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64) && !(Bits & Mips_FeatureMips64r6)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); case 52: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips2)); + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 53: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); + case 54: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 55: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 56: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 57: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 58: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 59: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 60: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 61: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); + case 62: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 63: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips5_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 64: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNoMadd4)); + case 65: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNoMadd4)); + case 66: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNoMadd4) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 67: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNoMadd4) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 68: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); + case 69: + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureDSPR2)); + case 70: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureEVA) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 71: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3_32) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); + case 72: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeaturePTR64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); + case 73: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeaturePTR64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 74: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeaturePTR64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 75: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6)); + case 76: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 77: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 78: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureGP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 79: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 80: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureCRC) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 81: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureCRC) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 82: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeaturePTR64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 83: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureGINV) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 84: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6)); + case 85: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureGP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6)); + case 86: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureGP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6)); + case 87: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeaturePTR64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 88: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 89: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeaturePTR64Bit)); + case 90: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 91: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 92: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 93: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureGP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3)); + case 94: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r5) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureVirt)); + case 95: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6)); + case 96: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureGP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 97: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureDSP)); + case 98: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 99: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 100: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 101: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 102: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3_32) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 103: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 104: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 105: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3D)); + case 106: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips3_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 107: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 108: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat)); + case 109: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips5_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 110: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNoMadd4)); + case 111: + return (!Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips16) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureFP64Bit) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips4_32r2) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips32r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMips64r6) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureSoftFloat) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNoMadd4) && !Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMicroMips)); + case 112: + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips)); + case 113: + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureMT)); + case 114: + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureCRC)); + case 115: + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureTLB)); + case 116: + return (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureNanoMips) && Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureGINV)); } } -#define DecodeToMCInst(fname,fieldname, InsnType) \ +#define DecodeToMCInst(fname, fieldname, InsnType) \ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ - uint64_t Address, void *Decoder) \ + uint64_t Address, const void *Decoder, bool *DecodeComplete) \ { \ + *DecodeComplete = true; \ InsnType tmp; \ switch (Idx) { \ - default: \ + default: /* llvm_unreachable("Invalid index!"); */ \ case 0: \ + tmp = fieldname(insn, 0, 11); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 1: \ tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 2: \ tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 3: \ - tmp = 0; \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 4: \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 5: \ + tmp = 0x0; \ tmp |= fieldname(insn, 3, 2) << 3; \ tmp |= fieldname(insn, 5, 3) << 0; \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 4: \ + case 6: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 5: \ + case 7: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 8: \ tmp = fieldname(insn, 2, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 6: \ + case 9: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 10: \ + return S; \ + case 11: \ tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 7: \ + case 12: \ tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 8: \ - tmp = 0; \ + case 13: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 14: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 0, 5) << 0; \ tmp |= fieldname(insn, 16, 5) << 11; \ tmp |= fieldname(insn, 21, 6) << 5; \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 9: \ + case 15: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 11; \ + tmp |= fieldname(insn, 21, 6) << 5; \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 16: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 11; \ + tmp |= fieldname(insn, 21, 6) << 5; \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 17: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 21, 1) << 5; \ + tmp |= fieldname(insn, 22, 5) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 10: \ - if (DecodeFMem3(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 18: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 11; \ + tmp |= fieldname(insn, 21, 6) << 5; \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 11: \ + case 19: \ + if (!Check(&S, DecodeFIXMEInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 20: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 11; \ + tmp |= fieldname(insn, 21, 6) << 5; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 21: \ + if (!Check(&S, DecodeFMem3(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 22: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 23: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 24: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 25: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 26: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 27: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 10); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_10_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 28: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 29: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 30: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 31: \ tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 1, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 12: \ - if (DecodeMemMMImm4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 32: \ + if (!Check(&S, DecodeMemMMImm4(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 13: \ + case 33: \ tmp = fieldname(insn, 5, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 14: \ + case 34: \ tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 1, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodePOOL16BEncodedField(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 15: \ + case 35: \ tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeANDI16Imm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeANDI16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 16: \ + case 36: \ tmp = fieldname(insn, 3, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 17: \ + case 37: \ tmp = fieldname(insn, 3, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 3, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 18: \ - if (DecodeMemMMReglistImm4Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 38: \ + if (!Check(&S, DecodeMemMMReglistImm4Lsl2(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 19: \ + case 39: \ tmp = fieldname(insn, 0, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 20: \ + case 40: \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 21: \ + case 41: \ tmp = fieldname(insn, 0, 5); \ - if (DecodeUImm5lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeUImmWithOffsetAndScale_5_0_4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 22: \ - if (DecodeMemMMSPImm5Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 42: \ + if (!Check(&S, DecodeMemMMSPImm5Lsl2(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 23: \ + case 43: \ tmp = fieldname(insn, 5, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 1, 4); \ - if (DecodeSimm4(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_4_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 24: \ + case 44: \ tmp = fieldname(insn, 1, 9); \ - if (DecodeSimm9SP(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeSimm9SP(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 25: \ - if (DecodeMemMMGPImm7Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 45: \ + if (!Check(&S, DecodeMemMMGPImm7Lsl2(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 26: \ + case 46: \ tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 1, 3); \ - if (DecodeAddiur2Simm7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAddiur2Simm7(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 27: \ + case 47: \ tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 1, 6); \ - if (DecodeUImm6Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeUImmWithOffsetAndScale_6_0_4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 28: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeMovePRegPair(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 1, 3); \ - if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 48: \ + if (!Check(&S, DecodeMovePOperands(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 29: \ + case 49: \ tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 7); \ - if (DecodeBranchTarget7MM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeBranchTarget7MM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 30: \ + case 50: \ tmp = fieldname(insn, 0, 10); \ - if (DecodeBranchTarget10MM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeBranchTarget10MM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 31: \ + case 51: \ tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 7); \ - if (DecodeLiSimm7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeLi16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 32: \ + case 52: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 33: \ + case 53: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 54: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 55: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 56: \ tmp = fieldname(insn, 16, 10); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 6, 10); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 34: \ + case 57: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 11, 5); \ - if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 35: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeInsSize(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 36: \ + case 58: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 37: \ + case 59: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 38: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 39: \ + case 60: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ - if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 40: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 41: \ - tmp = fieldname(insn, 16, 10); \ MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 42: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 43: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 44: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 45: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 46: \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 47: \ + case 61: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 48: \ - if (DecodeMemMMImm16(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 49: \ - if (DecodeMemMMImm12(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 50: \ - if (DecodeCacheOpMM(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 51: \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 52: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 53: \ + case 62: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 54: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 13, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 55: \ - if (DecodeJumpTargetMM(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 56: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 23); \ - if (DecodeSimm23Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 57: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 58: \ + case 63: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 59: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 60: \ + case 64: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 2); \ - if (DecodeLSAImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 61: \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 62: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 65: \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_6_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 63: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 66: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 64: \ - tmp = fieldname(insn, 6, 20); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 65: \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 66: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeUImmWithOffset_5_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 67: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 68: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeHI32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeCOP0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 3); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 69: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeLO32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeCOP0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 3); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 70: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 2); \ - if (DecodeLSAImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 71: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 72: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 10); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 73: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeHI32DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 74: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 13, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 75: \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeLO32DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 76: \ - if (DecodeSyncI(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 77: \ - if (DecodeJumpTarget(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 78: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 79: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 80: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 81: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 82: \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 83: \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 84: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 85: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 86: \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 87: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 88: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 10); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 89: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 90: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCOP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 91: \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeCOP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 92: \ tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 93: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 13, 8); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 94: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 7); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 95: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 96: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 10); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_10_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 97: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 98: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMemMMImm16(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 99: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMemMMImm12(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 100: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCacheOpMM(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 101: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTargetMM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 102: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 103: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 104: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeSyncI_MM(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 105: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget1SImm16(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 106: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTargetMM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 107: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeBranchTargetMM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 108: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 109: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 110: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 111: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 112: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 113: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 114: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 115: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 116: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 117: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 118: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 119: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 120: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 121: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 122: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 123: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 124: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 125: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 126: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 127: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeCCRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 128: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 129: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 130: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 6); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeCCRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 131: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 132: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 133: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 6); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 134: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeMemMMImm9(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 135: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodePrefeOpMM(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 136: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeJumpTargetMM(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 137: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 23, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 23); \ + if (!Check(&S, DecodeSimm23Lsl2(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 138: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTargetMM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 139: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFMemMMR2(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 140: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeJumpTargetXMM(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 141: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMem(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 142: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 143: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 144: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 145: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 146: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 147: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 148: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 149: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 150: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 151: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeUImmWithOffsetAndScale_5_0_4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 152: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 4); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 153: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 3); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 154: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 9, 2); \ + if (!Check(&S, DecodeUImmWithOffset_2_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 155: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 9, 2); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 156: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 9, 2); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 157: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 16); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 158: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 159: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeLoadByte15(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 160: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFMemCop2MMR6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 161: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 2); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTargetMM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 162: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeCOP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTargetMM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 163: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeSynciR6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 164: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 165: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 166: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 2); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 167: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 168: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 169: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 170: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 171: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 2); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 172: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 173: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodePOP35GroupBranchMMR6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 174: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 19); \ + if (!Check(&S, DecodeSimm19Lsl2(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 175: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 176: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 2); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodePOP37GroupBranchMMR6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 177: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 21); \ + if (!Check(&S, DecodeBranchTarget21MM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 178: \ - if (DecodeINSVE_DF_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 26); \ + if (!Check(&S, DecodeBranchTarget26MM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 179: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeBlezGroupBranchMMR6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 180: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodePOP65GroupBranchMMR6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 181: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeBgtzGroupBranchMMR6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 182: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodePOP75GroupBranchMMR6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 183: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 184: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 18, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 185: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 2); \ + if (!Check(&S, DecodeUImmWithOffset_2_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 186: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 187: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 188: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 20); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 189: \ tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 190: \ - if (DecodeMSA128Mem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 191: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 11, 5); \ - if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 192: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeHI32DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 193: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeLO32DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 194: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 2); \ + if (!Check(&S, DecodeUImmWithOffset_2_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 195: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 196: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 10); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 197: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 198: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 199: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeSyncI(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 200: \ + if (!Check(&S, DecodeJumpTarget(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 201: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 200: \ + case 202: \ tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 203: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 204: \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeCOP0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 201: \ + case 205: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCOP0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 202: \ + case 206: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 10); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 4, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 203: \ + case 207: \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 208: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 209: \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 204: \ + case 210: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCCRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 211: \ tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 205: \ + case 212: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 206: \ + case 213: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 207: \ + case 214: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCCRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 208: \ + case 215: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 209: \ + case 216: \ + tmp = fieldname(insn, 18, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 217: \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 218: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 210: \ + case 219: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 220: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 18, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 221: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 222: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 223: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 224: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 225: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 226: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 227: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 228: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 18, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 229: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 230: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 231: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 232: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 233: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 234: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 235: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeCOP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 236: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeCOP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 237: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 238: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 239: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 240: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 241: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 242: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 243: \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 244: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 245: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 246: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 247: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 248: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 249: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 250: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 251: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 252: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 253: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 254: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 255: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 256: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 257: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 258: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 259: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 260: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 261: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 262: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 263: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 264: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 265: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 266: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 267: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 268: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 269: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 270: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 271: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 272: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 273: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 274: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 275: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 276: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 277: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 278: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 279: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 280: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 281: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 282: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 283: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 284: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 285: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 286: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 287: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 288: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 289: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 290: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 291: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 292: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 293: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 294: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 295: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 296: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 297: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 298: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 299: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 300: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 301: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 302: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 303: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 304: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 305: \ + if (!Check(&S, DecodeINSVE_DF(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 306: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 307: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 308: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 309: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 310: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 311: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 312: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 313: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 314: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 315: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 316: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 317: \ + if (!Check(&S, DecodeMSA128Mem(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 318: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeUImmWithOffset_5_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 319: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeInsSize(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 320: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 321: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 322: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 323: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 324: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 325: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 326: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 327: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 328: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 329: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 330: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 331: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 332: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 333: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 334: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeDSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 335: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 336: \ + if (!Check(&S, DecodeMemEVA(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 337: \ + if (!Check(&S, DecodeCacheeOp_CacheOpR6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 338: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 339: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 340: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 341: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 342: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 343: \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 6); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_6_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 344: \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 2); \ + if (!Check(&S, DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 345: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 346: \ + if (!Check(&S, DecodeCacheOp(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 347: \ + if (!Check(&S, DecodeFMem(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 348: \ + if (!Check(&S, DecodeFMem2(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 349: \ + if (!Check(&S, DecodeDAHIDATI(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 350: \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 351: \ + if (!Check(&S, DecodeBlezGroupBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 352: \ + if (!Check(&S, DecodeBgtzGroupBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 353: \ + if (!Check(&S, DecodeAddiGroupBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 354: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 355: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 356: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 357: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 358: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 359: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 360: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 361: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeCOP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeBranchTarget(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 362: \ + if (!Check(&S, DecodeFMemCop2R6(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 363: \ + if (!Check(&S, DecodeBlezlGroupBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 364: \ + if (!Check(&S, DecodeBgtzlGroupBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 365: \ + if (!Check(&S, DecodeDaddiGroupBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 366: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 367: \ + if (!Check(&S, DecodeCRC(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 368: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 369: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 370: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 371: \ + if (!Check(&S, DecodeSpecial3LlSc(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 372: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 373: \ + tmp = fieldname(insn, 0, 26); \ + if (!Check(&S, DecodeBranchTarget26(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 374: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 21); \ + if (!Check(&S, DecodeBranchTarget21(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 375: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 18); \ + if (!Check(&S, DecodeSimm18Lsl3(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 376: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 21); \ + if (!Check(&S, DecodeBranchTarget21(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 377: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 378: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 379: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 380: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeCOP0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 381: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeCOP0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 382: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeCOP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 383: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeCOP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 384: \ + tmp = fieldname(insn, 13, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 385: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_16_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 386: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 387: \ + if (!Check(&S, DecodeDEXT(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 388: \ + if (!Check(&S, DecodeDINS(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 389: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 390: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 391: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 392: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 393: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 18, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 394: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 395: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 396: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeFCCRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 397: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 398: \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodePtrRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 399: \ + tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFGR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 400: \ + tmp = fieldname(insn, 0, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 401: \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 402: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPRNM32NZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 403: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 7) << 2; \ + if (!Check(&S, DecodeMemNM_6_0_Mips_GPRNM3RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 404: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 10; \ + tmp |= fieldname(insn, 1, 9) << 1; \ + if (!Check(&S, DecodeBranchTargetNM_10(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 405: \ + tmp = fieldname(insn, 4, 4) << 4; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + if (!Check(&S, DecodeNMRegList16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 406: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodeUImm3Shift(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 407: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5) << 2; \ + if (!Check(&S, DecodeMemNM_7_0_Mips_GPRNMSPRegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 408: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 3) << 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + if (!Check(&S, DecodeGPRNM4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 0; \ + tmp |= fieldname(insn, 4, 1) << 4; \ + if (!Check(&S, DecodeGPRNM4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 409: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 410: \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 411: \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 3) << 0; \ + tmp |= fieldname(insn, 7, 3) << 5; \ + if (!Check(&S, DecodeMemNMRX_Mips_GPRNM3RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 412: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 7) << 2; \ + if (!Check(&S, DecodeMemNM_9_0_Mips_GPRNMGPRegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 413: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 2) << 0; \ + tmp |= fieldname(insn, 4, 3) << 2; \ + if (!Check(&S, DecodeMemNM_2_0_Mips_GPRNM3RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 414: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3ZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 2) << 0; \ + tmp |= fieldname(insn, 4, 3) << 2; \ + if (!Check(&S, DecodeMemNM_2_0_Mips_GPRNM3RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 415: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 6) << 2; \ + if (!Check(&S, DecodeUImmWithReg_8_0_1_Mips_SP_NM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 416: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 3) << 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + if (!Check(&S, DecodeGPRNM4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 4; \ + tmp |= fieldname(insn, 3, 1) << 3; \ + tmp |= fieldname(insn, 4, 1) << 8; \ + tmp |= fieldname(insn, 8, 1) << 2; \ + if (!Check(&S, DecodeMemNM4x4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 417: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 2) << 1; \ + tmp |= fieldname(insn, 4, 3) << 3; \ + if (!Check(&S, DecodeMemNM_3_0_Mips_GPRNM3RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 418: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3ZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 2) << 1; \ + tmp |= fieldname(insn, 4, 3) << 3; \ + if (!Check(&S, DecodeMemNM_3_0_Mips_GPRNM3RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 419: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 420: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 0; \ + tmp |= fieldname(insn, 4, 1) << 3; \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_4_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 211: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 421: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3ZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 7) << 2; \ + if (!Check(&S, DecodeMemNM_6_0_Mips_GPRNM3RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 212: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 10); \ - MCOperand_CreateImm0(MI, tmp); \ + case 422: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 7; \ + tmp |= fieldname(insn, 1, 6) << 1; \ + if (!Check(&S, DecodeBranchTargetNM_7(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 213: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ + case 423: \ + tmp = fieldname(insn, 1, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 424: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 1) << 1; \ + tmp |= fieldname(insn, 8, 1) << 0; \ + if (!Check(&S, DecodeGPRNM2R1RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 0; \ + tmp |= fieldname(insn, 4, 1) << 4; \ + if (!Check(&S, DecodeGPRNM4ZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 3) << 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + if (!Check(&S, DecodeGPRNM4ZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 214: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 6); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 425: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 7); \ + if (!Check(&S, DecodeImmM1To126(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 215: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 426: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3ZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 7) << 2; \ + if (!Check(&S, DecodeMemNM_9_0_Mips_GPRNMGPRegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 216: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 427: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 217: \ - if (DecodeMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 428: \ + tmp = fieldname(insn, 4, 1); \ + if (!Check(&S, DecodeGPRNMRARegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 218: \ - if (DecodeCacheOp(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 429: \ + if (!Check(&S, DecodeBranchConflictNM(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 219: \ - if (DecodeFMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 430: \ + tmp = fieldname(insn, 7, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 3); \ + if (!Check(&S, DecodeGPRNM3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeUImm4Mask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 220: \ - if (DecodeFMem2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 431: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 3) << 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + if (!Check(&S, DecodeGPRNM4ZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 4; \ + tmp |= fieldname(insn, 3, 1) << 3; \ + tmp |= fieldname(insn, 4, 1) << 8; \ + tmp |= fieldname(insn, 8, 1) << 2; \ + if (!Check(&S, DecodeMemNM4x4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 432: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 0; \ + tmp |= fieldname(insn, 4, 1) << 4; \ + if (!Check(&S, DecodeGPRNM4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 3) << 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + if (!Check(&S, DecodeGPRNM4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 1) << 1; \ + tmp |= fieldname(insn, 8, 1) << 0; \ + if (!Check(&S, DecodeGPRNM2R1RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 433: \ + tmp = fieldname(insn, 0, 18); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 221: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 434: \ + tmp = fieldname(insn, 0, 19); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 435: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 2); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 222: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 436: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 223: \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 21; \ + tmp |= fieldname(insn, 1, 20) << 1; \ + if (!Check(&S, DecodeAddressPCRelNM_22(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 437: \ + tmp = fieldname(insn, 24, 1); \ + if (!Check(&S, DecodeGPRNM1R1RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 21, 3) << 0; \ + tmp |= fieldname(insn, 25, 1) << 4; \ + if (!Check(&S, DecodeGPRNM4ZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 21; \ + tmp |= fieldname(insn, 1, 20) << 1; \ + if (!Check(&S, DecodeBranchTargetNM_21(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 438: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 439: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 2); \ + if (!Check(&S, DecodeCOP0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 224: \ + case 440: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 10); \ + if (!Check(&S, DecodeMemNMRX_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 225: \ + case 441: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 226: \ - if (DecodeBlezGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 227: \ - if (DecodeBgtzGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 228: \ - if (DecodeAddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 229: \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 230: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 442: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 9, 2); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 231: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 443: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 232: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 444: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 233: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 234: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 445: \ tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 235: \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ - if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 236: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 446: \ tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 237: \ + case 447: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 238: \ - if (DecodeFMemCop2R6(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 239: \ - if (DecodeBlezlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 240: \ - if (DecodeBgtzlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 241: \ - if (DecodeDaddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 448: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 10); \ + if (!Check(&S, DecodeCOP0SelRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 242: \ + case 449: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 243: \ + if (!Check(&S, DecodeCOP0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 1); \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 3, 1); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 244: \ + case 450: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeCOP0RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 1); \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 3, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 451: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 452: \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 3); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 245: \ - if (DecodeCacheOpR6(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 246: \ - if (DecodeSpecial3LlSc(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 453: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 247: \ - tmp = fieldname(insn, 0, 26); \ - if (DecodeBranchTarget26(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 454: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 25; \ + tmp |= fieldname(insn, 1, 24) << 1; \ + if (!Check(&S, DecodeBranchTargetNM_25(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 248: \ + case 455: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 21); \ - if (DecodeBranchTarget21(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 2, 19) << 2; \ + if (!Check(&S, DecodeUImmWithReg_21_0_1_Mips_GP_NM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 249: \ + case 456: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 19); \ - if (DecodeSimm19Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 2, 19) << 2; \ + if (!Check(&S, DecodeMemNM_21_0_Mips_GPRNMGPRegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 250: \ + case 457: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 18); \ - if (DecodeSimm18Lsl3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMemNM_18_0_Mips_GPRNMGPRegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 251: \ + case 458: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 18); \ + if (!Check(&S, DecodeUImmWithReg_18_0_1_Mips_GP_NM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 252: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 459: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 1, 17) << 1; \ + if (!Check(&S, DecodeMemNM_18_0_Mips_GPRNMGPRegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 253: \ + case 460: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32NZRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 254: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 461: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 255: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 3); \ + case 462: \ + tmp = fieldname(insn, 3, 9) << 3; \ MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 2, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + tmp |= fieldname(insn, 21, 5) << 5; \ + if (!Check(&S, DecodeNMRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 256: \ + case 463: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, DecodeNegImm12(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 257: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 464: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 258: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 259: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 260: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 465: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 7, 4) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 6, 1); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 261: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 466: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 262: \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeInsSize(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 263: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 467: \ tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 264: \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeUImmWithOffset_5_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 468: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 5) << 12; \ + if (!Check(&S, DecodeMemNM_12_0_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 469: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 5) << 12; \ + if (!Check(&S, DecodeMemNM_12_0_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 470: \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 5) << 12; \ + if (!Check(&S, DecodeMemNM_12_0_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 265: \ + case 471: \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 14; \ + tmp |= fieldname(insn, 1, 13) << 1; \ + if (!Check(&S, DecodeBranchTargetNM_14(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 266: \ + case 472: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 15, 6) << 8; \ + if (!Check(&S, DecodeMemNM_9_1_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 267: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 473: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 2, 6) << 2; \ + tmp |= fieldname(insn, 15, 6) << 8; \ + if (!Check(&S, DecodeMemNM_9_1_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 268: \ + case 474: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 3, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMemZeroNM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 475: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 15, 6) << 8; \ + if (!Check(&S, DecodeMemNM_9_1_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 3); \ + if (!Check(&S, DecodeUImm3Shift(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 476: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 15, 6) << 8; \ + if (!Check(&S, DecodeMemNM_9_1_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 477: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 10); \ MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 15, 6) << 8; \ + if (!Check(&S, DecodeMemNM_9_1_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 269: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 478: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 2, 6) << 2; \ + tmp |= fieldname(insn, 15, 6) << 8; \ + if (!Check(&S, DecodeMemNM_9_1_Mips_GPRNM32RegClassID(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 270: \ + case 479: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 3, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMemZeroNM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 480: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 7); \ MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 11; \ + tmp |= fieldname(insn, 1, 10) << 1; \ + if (!Check(&S, DecodeBranchTargetNM_11(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 271: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 481: \ tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 6); \ + if (!Check(&S, DecodeSImmWithOffsetAndScale_32_0_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 11; \ + tmp |= fieldname(insn, 1, 10) << 1; \ + if (!Check(&S, DecodeBranchTargetNM_11(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 482: \ + tmp = fieldname(insn, 21, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 19; \ + tmp |= fieldname(insn, 2, 10) << 9; \ + tmp |= fieldname(insn, 12, 9) << 0; \ + if (!Check(&S, DecodeSImm32s12(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 483: \ + tmp = fieldname(insn, 37, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 16) << 16; \ + tmp |= fieldname(insn, 16, 16) << 0; \ MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ - case 272: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ + case 484: \ + tmp = fieldname(insn, 37, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 37, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 16) << 16; \ + tmp |= fieldname(insn, 16, 16) << 0; \ MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 485: \ + tmp = fieldname(insn, 37, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 16) << 16; \ + tmp |= fieldname(insn, 16, 16) << 0; \ + if (!Check(&S, DecodeSImmWithReg_32_0_1_Mips_GP_NM(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 486: \ + tmp = fieldname(insn, 37, 5); \ + if (!Check(&S, DecodeGPRNM32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 16) << 16; \ + tmp |= fieldname(insn, 16, 16) << 0; \ + if (!Check(&S, DecodeAddressPCRelNM_32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ } \ } #define DecodeInstruction(fname, fieldname, decoder, InsnType) \ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ - InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \ -{ \ - uint64_t Bits = getFeatureBits(feature); \ + InsnType insn, uint64_t Address, const void *Decoder) { \ const uint8_t *Ptr = DecodeTable; \ - uint32_t CurFieldValue = 0, ExpectedValue; \ + uint64_t CurFieldValue = 0; \ DecodeStatus S = MCDisassembler_Success; \ - unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ - InsnType Val, FieldValue, PositiveMask, NegativeMask; \ - bool Pred, Fail; \ - for (;;) { \ + while (true) { \ switch (*Ptr) { \ default: \ return MCDisassembler_Fail; \ case MCD_OPC_ExtractField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ + unsigned Start = *++Ptr; \ + unsigned Len = *++Ptr; \ ++Ptr; \ - CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ + CurFieldValue = fieldname(insn, Start, Len); \ break; \ } \ case MCD_OPC_FilterValue: { \ - Val = (InsnType)decodeULEB128(++Ptr, &Len); \ + /* Decode the field value. */ \ + unsigned Len; \ + uint64_t Val = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ - NumToSkip = *Ptr++; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the filter operation. */ \ if (Val != CurFieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ - FieldValue = fieldname(insn, Start, Len); \ - ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NumToSkip = *Ptr++; \ + unsigned Start = *++Ptr; \ + unsigned Len = *++Ptr; \ + uint64_t FieldValue = fieldname(insn, Start, Len); \ + /* Decode the field value. */ \ + unsigned PtrLen = 0; \ + uint64_t ExpectedValue = decodeULEB128(++Ptr, &PtrLen); \ + Ptr += PtrLen; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* If the actual and expected values don't match, skip. */ \ if (ExpectedValue != FieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckPredicate: { \ - PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ + unsigned Len; \ + /* Decode the Predicate Index value. */ \ + unsigned PIdx = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ - NumToSkip = *Ptr++; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ - Pred = checkDecoderPredicate(PIdx, Bits); \ + NumToSkip |= (*Ptr++) << 16; \ + /* Check the predicate. */ \ + bool Pred = checkDecoderPredicate(MI, PIdx); \ if (!Pred) \ Ptr += NumToSkip; \ - (void)Pred; \ break; \ } \ case MCD_OPC_Decode: { \ - Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ + unsigned Len; \ + /* Decode the Opcode value. */ \ + unsigned Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_clear(MI); \ + MCInst_setOpcode(MI, Opc); \ + bool DecodeComplete; \ + S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \ + return S; \ + } \ + case MCD_OPC_TryDecode: { \ + unsigned Len; \ + /* Decode the Opcode value. */ \ + unsigned Opc = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ - DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ + unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \ Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the decode operation. */ \ MCInst_setOpcode(MI, Opc); \ - return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ + bool DecodeComplete; \ + S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \ + if (DecodeComplete) { \ + /* Decoding complete. */ \ + return S; \ + } else { \ + /* LLVM uses a MCInst on the stack, but for our use case, */ \ + /* it is enough for now to reset the op counter. */ \ + MCInst_clear(MI); \ + /* If the decoding was incomplete, skip. */ \ + Ptr += NumToSkip; \ + /* Reset decode status. This also drops a SoftFail status that could be */ \ + /* set before the decode attempt. */ \ + S = MCDisassembler_Success; \ + } \ + break; \ } \ case MCD_OPC_SoftFail: { \ - PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ + /* Decode the mask values. */ \ + unsigned Len; \ + uint64_t PositiveMask = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ - NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ + uint64_t NegativeMask = decodeULEB128(Ptr, &Len); \ Ptr += Len; \ - Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + bool Fail = (insn & PositiveMask) != 0 || (~insn & NegativeMask) != 0; \ if (Fail) \ S = MCDisassembler_SoftFail; \ break; \ @@ -6935,8 +12118,15 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ } \ } \ } \ + /* Bogisity detected in disassembler state machine! */ \ } -FieldFromInstruction(fieldFromInstruction, uint32_t) -DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) -DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint32_t) +FieldFromInstruction(fieldFromInstruction_4, uint32_t) +FieldFromInstruction(fieldFromInstruction_2, uint32_t) +FieldFromInstruction(fieldFromInstruction_8, uint64_t) +DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) +DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint32_t) +DecodeToMCInst(decodeToMCInst_8, fieldFromInstruction_8, uint64_t) +DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) +DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, uint32_t) +DecodeInstruction(decodeInstruction_8, fieldFromInstruction_8, decodeToMCInst_8, uint64_t) diff --git a/arch/Mips/MipsGenInstrInfo.inc b/arch/Mips/MipsGenInstrInfo.inc index b6e8983edc..d4913e6b9f 100644 --- a/arch/Mips/MipsGenInstrInfo.inc +++ b/arch/Mips/MipsGenInstrInfo.inc @@ -1,1805 +1,7478 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|*Target Instruction Enum Values *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* LLVM-commit: */ +/* LLVM-tag: */ +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM -enum { + enum { Mips_PHI = 0, Mips_INLINEASM = 1, - Mips_CFI_INSTRUCTION = 2, - Mips_EH_LABEL = 3, - Mips_GC_LABEL = 4, - Mips_KILL = 5, - Mips_EXTRACT_SUBREG = 6, - Mips_INSERT_SUBREG = 7, - Mips_IMPLICIT_DEF = 8, - Mips_SUBREG_TO_REG = 9, - Mips_COPY_TO_REGCLASS = 10, - Mips_DBG_VALUE = 11, - Mips_REG_SEQUENCE = 12, - Mips_COPY = 13, - Mips_BUNDLE = 14, - Mips_LIFETIME_START = 15, - Mips_LIFETIME_END = 16, - Mips_STACKMAP = 17, - Mips_PATCHPOINT = 18, - Mips_LOAD_STACK_GUARD = 19, - Mips_STATEPOINT = 20, - Mips_FRAME_ALLOC = 21, - Mips_ABSQ_S_PH = 22, - Mips_ABSQ_S_QB = 23, - Mips_ABSQ_S_W = 24, - Mips_ADD = 25, - Mips_ADDIUPC = 26, - Mips_ADDIUPC_MM = 27, - Mips_ADDIUR1SP_MM = 28, - Mips_ADDIUR2_MM = 29, - Mips_ADDIUS5_MM = 30, - Mips_ADDIUSP_MM = 31, - Mips_ADDQH_PH = 32, - Mips_ADDQH_R_PH = 33, - Mips_ADDQH_R_W = 34, - Mips_ADDQH_W = 35, - Mips_ADDQ_PH = 36, - Mips_ADDQ_S_PH = 37, - Mips_ADDQ_S_W = 38, - Mips_ADDSC = 39, - Mips_ADDS_A_B = 40, - Mips_ADDS_A_D = 41, - Mips_ADDS_A_H = 42, - Mips_ADDS_A_W = 43, - Mips_ADDS_S_B = 44, - Mips_ADDS_S_D = 45, - Mips_ADDS_S_H = 46, - Mips_ADDS_S_W = 47, - Mips_ADDS_U_B = 48, - Mips_ADDS_U_D = 49, - Mips_ADDS_U_H = 50, - Mips_ADDS_U_W = 51, - Mips_ADDU16_MM = 52, - Mips_ADDUH_QB = 53, - Mips_ADDUH_R_QB = 54, - Mips_ADDU_PH = 55, - Mips_ADDU_QB = 56, - Mips_ADDU_S_PH = 57, - Mips_ADDU_S_QB = 58, - Mips_ADDVI_B = 59, - Mips_ADDVI_D = 60, - Mips_ADDVI_H = 61, - Mips_ADDVI_W = 62, - Mips_ADDV_B = 63, - Mips_ADDV_D = 64, - Mips_ADDV_H = 65, - Mips_ADDV_W = 66, - Mips_ADDWC = 67, - Mips_ADD_A_B = 68, - Mips_ADD_A_D = 69, - Mips_ADD_A_H = 70, - Mips_ADD_A_W = 71, - Mips_ADD_MM = 72, - Mips_ADDi = 73, - Mips_ADDi_MM = 74, - Mips_ADDiu = 75, - Mips_ADDiu_MM = 76, - Mips_ADDu = 77, - Mips_ADDu_MM = 78, - Mips_ADJCALLSTACKDOWN = 79, - Mips_ADJCALLSTACKUP = 80, - Mips_ALIGN = 81, - Mips_ALUIPC = 82, - Mips_AND = 83, - Mips_AND16_MM = 84, - Mips_AND64 = 85, - Mips_ANDI16_MM = 86, - Mips_ANDI_B = 87, - Mips_AND_MM = 88, - Mips_AND_V = 89, - Mips_AND_V_D_PSEUDO = 90, - Mips_AND_V_H_PSEUDO = 91, - Mips_AND_V_W_PSEUDO = 92, - Mips_ANDi = 93, - Mips_ANDi64 = 94, - Mips_ANDi_MM = 95, - Mips_APPEND = 96, - Mips_ASUB_S_B = 97, - Mips_ASUB_S_D = 98, - Mips_ASUB_S_H = 99, - Mips_ASUB_S_W = 100, - Mips_ASUB_U_B = 101, - Mips_ASUB_U_D = 102, - Mips_ASUB_U_H = 103, - Mips_ASUB_U_W = 104, - Mips_ATOMIC_CMP_SWAP_I16 = 105, - Mips_ATOMIC_CMP_SWAP_I32 = 106, - Mips_ATOMIC_CMP_SWAP_I64 = 107, - Mips_ATOMIC_CMP_SWAP_I8 = 108, - Mips_ATOMIC_LOAD_ADD_I16 = 109, - Mips_ATOMIC_LOAD_ADD_I32 = 110, - Mips_ATOMIC_LOAD_ADD_I64 = 111, - Mips_ATOMIC_LOAD_ADD_I8 = 112, - Mips_ATOMIC_LOAD_AND_I16 = 113, - Mips_ATOMIC_LOAD_AND_I32 = 114, - Mips_ATOMIC_LOAD_AND_I64 = 115, - Mips_ATOMIC_LOAD_AND_I8 = 116, - Mips_ATOMIC_LOAD_NAND_I16 = 117, - Mips_ATOMIC_LOAD_NAND_I32 = 118, - Mips_ATOMIC_LOAD_NAND_I64 = 119, - Mips_ATOMIC_LOAD_NAND_I8 = 120, - Mips_ATOMIC_LOAD_OR_I16 = 121, - Mips_ATOMIC_LOAD_OR_I32 = 122, - Mips_ATOMIC_LOAD_OR_I64 = 123, - Mips_ATOMIC_LOAD_OR_I8 = 124, - Mips_ATOMIC_LOAD_SUB_I16 = 125, - Mips_ATOMIC_LOAD_SUB_I32 = 126, - Mips_ATOMIC_LOAD_SUB_I64 = 127, - Mips_ATOMIC_LOAD_SUB_I8 = 128, - Mips_ATOMIC_LOAD_XOR_I16 = 129, - Mips_ATOMIC_LOAD_XOR_I32 = 130, - Mips_ATOMIC_LOAD_XOR_I64 = 131, - Mips_ATOMIC_LOAD_XOR_I8 = 132, - Mips_ATOMIC_SWAP_I16 = 133, - Mips_ATOMIC_SWAP_I32 = 134, - Mips_ATOMIC_SWAP_I64 = 135, - Mips_ATOMIC_SWAP_I8 = 136, - Mips_AUI = 137, - Mips_AUIPC = 138, - Mips_AVER_S_B = 139, - Mips_AVER_S_D = 140, - Mips_AVER_S_H = 141, - Mips_AVER_S_W = 142, - Mips_AVER_U_B = 143, - Mips_AVER_U_D = 144, - Mips_AVER_U_H = 145, - Mips_AVER_U_W = 146, - Mips_AVE_S_B = 147, - Mips_AVE_S_D = 148, - Mips_AVE_S_H = 149, - Mips_AVE_S_W = 150, - Mips_AVE_U_B = 151, - Mips_AVE_U_D = 152, - Mips_AVE_U_H = 153, - Mips_AVE_U_W = 154, - Mips_AddiuRxImmX16 = 155, - Mips_AddiuRxPcImmX16 = 156, - Mips_AddiuRxRxImm16 = 157, - Mips_AddiuRxRxImmX16 = 158, - Mips_AddiuRxRyOffMemX16 = 159, - Mips_AddiuSpImm16 = 160, - Mips_AddiuSpImmX16 = 161, - Mips_AdduRxRyRz16 = 162, - Mips_AndRxRxRy16 = 163, - Mips_B = 164, - Mips_B16_MM = 165, - Mips_BADDu = 166, - Mips_BAL = 167, - Mips_BALC = 168, - Mips_BALIGN = 169, - Mips_BAL_BR = 170, - Mips_BBIT0 = 171, - Mips_BBIT032 = 172, - Mips_BBIT1 = 173, - Mips_BBIT132 = 174, - Mips_BC = 175, - Mips_BC0F = 176, - Mips_BC0FL = 177, - Mips_BC0T = 178, - Mips_BC0TL = 179, - Mips_BC1EQZ = 180, - Mips_BC1F = 181, - Mips_BC1FL = 182, - Mips_BC1F_MM = 183, - Mips_BC1NEZ = 184, - Mips_BC1T = 185, - Mips_BC1TL = 186, - Mips_BC1T_MM = 187, - Mips_BC2EQZ = 188, - Mips_BC2F = 189, - Mips_BC2FL = 190, - Mips_BC2NEZ = 191, - Mips_BC2T = 192, - Mips_BC2TL = 193, - Mips_BC3F = 194, - Mips_BC3FL = 195, - Mips_BC3T = 196, - Mips_BC3TL = 197, - Mips_BCLRI_B = 198, - Mips_BCLRI_D = 199, - Mips_BCLRI_H = 200, - Mips_BCLRI_W = 201, - Mips_BCLR_B = 202, - Mips_BCLR_D = 203, - Mips_BCLR_H = 204, - Mips_BCLR_W = 205, - Mips_BEQ = 206, - Mips_BEQ64 = 207, - Mips_BEQC = 208, - Mips_BEQL = 209, - Mips_BEQZ16_MM = 210, - Mips_BEQZALC = 211, - Mips_BEQZC = 212, - Mips_BEQZC_MM = 213, - Mips_BEQ_MM = 214, - Mips_BGEC = 215, - Mips_BGEUC = 216, - Mips_BGEZ = 217, - Mips_BGEZ64 = 218, - Mips_BGEZAL = 219, - Mips_BGEZALC = 220, - Mips_BGEZALL = 221, - Mips_BGEZALS_MM = 222, - Mips_BGEZAL_MM = 223, - Mips_BGEZC = 224, - Mips_BGEZL = 225, - Mips_BGEZ_MM = 226, - Mips_BGTZ = 227, - Mips_BGTZ64 = 228, - Mips_BGTZALC = 229, - Mips_BGTZC = 230, - Mips_BGTZL = 231, - Mips_BGTZ_MM = 232, - Mips_BINSLI_B = 233, - Mips_BINSLI_D = 234, - Mips_BINSLI_H = 235, - Mips_BINSLI_W = 236, - Mips_BINSL_B = 237, - Mips_BINSL_D = 238, - Mips_BINSL_H = 239, - Mips_BINSL_W = 240, - Mips_BINSRI_B = 241, - Mips_BINSRI_D = 242, - Mips_BINSRI_H = 243, - Mips_BINSRI_W = 244, - Mips_BINSR_B = 245, - Mips_BINSR_D = 246, - Mips_BINSR_H = 247, - Mips_BINSR_W = 248, - Mips_BITREV = 249, - Mips_BITSWAP = 250, - Mips_BLEZ = 251, - Mips_BLEZ64 = 252, - Mips_BLEZALC = 253, - Mips_BLEZC = 254, - Mips_BLEZL = 255, - Mips_BLEZ_MM = 256, - Mips_BLTC = 257, - Mips_BLTUC = 258, - Mips_BLTZ = 259, - Mips_BLTZ64 = 260, - Mips_BLTZAL = 261, - Mips_BLTZALC = 262, - Mips_BLTZALL = 263, - Mips_BLTZALS_MM = 264, - Mips_BLTZAL_MM = 265, - Mips_BLTZC = 266, - Mips_BLTZL = 267, - Mips_BLTZ_MM = 268, - Mips_BMNZI_B = 269, - Mips_BMNZ_V = 270, - Mips_BMZI_B = 271, - Mips_BMZ_V = 272, - Mips_BNE = 273, - Mips_BNE64 = 274, - Mips_BNEC = 275, - Mips_BNEGI_B = 276, - Mips_BNEGI_D = 277, - Mips_BNEGI_H = 278, - Mips_BNEGI_W = 279, - Mips_BNEG_B = 280, - Mips_BNEG_D = 281, - Mips_BNEG_H = 282, - Mips_BNEG_W = 283, - Mips_BNEL = 284, - Mips_BNEZ16_MM = 285, - Mips_BNEZALC = 286, - Mips_BNEZC = 287, - Mips_BNEZC_MM = 288, - Mips_BNE_MM = 289, - Mips_BNVC = 290, - Mips_BNZ_B = 291, - Mips_BNZ_D = 292, - Mips_BNZ_H = 293, - Mips_BNZ_V = 294, - Mips_BNZ_W = 295, - Mips_BOVC = 296, - Mips_BPOSGE32 = 297, - Mips_BPOSGE32_PSEUDO = 298, - Mips_BREAK = 299, - Mips_BREAK16_MM = 300, - Mips_BREAK_MM = 301, - Mips_BSELI_B = 302, - Mips_BSEL_D_PSEUDO = 303, - Mips_BSEL_FD_PSEUDO = 304, - Mips_BSEL_FW_PSEUDO = 305, - Mips_BSEL_H_PSEUDO = 306, - Mips_BSEL_V = 307, - Mips_BSEL_W_PSEUDO = 308, - Mips_BSETI_B = 309, - Mips_BSETI_D = 310, - Mips_BSETI_H = 311, - Mips_BSETI_W = 312, - Mips_BSET_B = 313, - Mips_BSET_D = 314, - Mips_BSET_H = 315, - Mips_BSET_W = 316, - Mips_BZ_B = 317, - Mips_BZ_D = 318, - Mips_BZ_H = 319, - Mips_BZ_V = 320, - Mips_BZ_W = 321, - Mips_B_MM_Pseudo = 322, - Mips_BeqzRxImm16 = 323, - Mips_BeqzRxImmX16 = 324, - Mips_Bimm16 = 325, - Mips_BimmX16 = 326, - Mips_BnezRxImm16 = 327, - Mips_BnezRxImmX16 = 328, - Mips_Break16 = 329, - Mips_Bteqz16 = 330, - Mips_BteqzT8CmpX16 = 331, - Mips_BteqzT8CmpiX16 = 332, - Mips_BteqzT8SltX16 = 333, - Mips_BteqzT8SltiX16 = 334, - Mips_BteqzT8SltiuX16 = 335, - Mips_BteqzT8SltuX16 = 336, - Mips_BteqzX16 = 337, - Mips_Btnez16 = 338, - Mips_BtnezT8CmpX16 = 339, - Mips_BtnezT8CmpiX16 = 340, - Mips_BtnezT8SltX16 = 341, - Mips_BtnezT8SltiX16 = 342, - Mips_BtnezT8SltiuX16 = 343, - Mips_BtnezT8SltuX16 = 344, - Mips_BtnezX16 = 345, - Mips_BuildPairF64 = 346, - Mips_BuildPairF64_64 = 347, - Mips_CACHE = 348, - Mips_CACHE_MM = 349, - Mips_CACHE_R6 = 350, - Mips_CEIL_L_D64 = 351, - Mips_CEIL_L_S = 352, - Mips_CEIL_W_D32 = 353, - Mips_CEIL_W_D64 = 354, - Mips_CEIL_W_MM = 355, - Mips_CEIL_W_S = 356, - Mips_CEIL_W_S_MM = 357, - Mips_CEQI_B = 358, - Mips_CEQI_D = 359, - Mips_CEQI_H = 360, - Mips_CEQI_W = 361, - Mips_CEQ_B = 362, - Mips_CEQ_D = 363, - Mips_CEQ_H = 364, - Mips_CEQ_W = 365, - Mips_CFC1 = 366, - Mips_CFC1_MM = 367, - Mips_CFCMSA = 368, - Mips_CINS = 369, - Mips_CINS32 = 370, - Mips_CLASS_D = 371, - Mips_CLASS_S = 372, - Mips_CLEI_S_B = 373, - Mips_CLEI_S_D = 374, - Mips_CLEI_S_H = 375, - Mips_CLEI_S_W = 376, - Mips_CLEI_U_B = 377, - Mips_CLEI_U_D = 378, - Mips_CLEI_U_H = 379, - Mips_CLEI_U_W = 380, - Mips_CLE_S_B = 381, - Mips_CLE_S_D = 382, - Mips_CLE_S_H = 383, - Mips_CLE_S_W = 384, - Mips_CLE_U_B = 385, - Mips_CLE_U_D = 386, - Mips_CLE_U_H = 387, - Mips_CLE_U_W = 388, - Mips_CLO = 389, - Mips_CLO_MM = 390, - Mips_CLO_R6 = 391, - Mips_CLTI_S_B = 392, - Mips_CLTI_S_D = 393, - Mips_CLTI_S_H = 394, - Mips_CLTI_S_W = 395, - Mips_CLTI_U_B = 396, - Mips_CLTI_U_D = 397, - Mips_CLTI_U_H = 398, - Mips_CLTI_U_W = 399, - Mips_CLT_S_B = 400, - Mips_CLT_S_D = 401, - Mips_CLT_S_H = 402, - Mips_CLT_S_W = 403, - Mips_CLT_U_B = 404, - Mips_CLT_U_D = 405, - Mips_CLT_U_H = 406, - Mips_CLT_U_W = 407, - Mips_CLZ = 408, - Mips_CLZ_MM = 409, - Mips_CLZ_R6 = 410, - Mips_CMPGDU_EQ_QB = 411, - Mips_CMPGDU_LE_QB = 412, - Mips_CMPGDU_LT_QB = 413, - Mips_CMPGU_EQ_QB = 414, - Mips_CMPGU_LE_QB = 415, - Mips_CMPGU_LT_QB = 416, - Mips_CMPU_EQ_QB = 417, - Mips_CMPU_LE_QB = 418, - Mips_CMPU_LT_QB = 419, - Mips_CMP_EQ_D = 420, - Mips_CMP_EQ_PH = 421, - Mips_CMP_EQ_S = 422, - Mips_CMP_F_D = 423, - Mips_CMP_F_S = 424, - Mips_CMP_LE_D = 425, - Mips_CMP_LE_PH = 426, - Mips_CMP_LE_S = 427, - Mips_CMP_LT_D = 428, - Mips_CMP_LT_PH = 429, - Mips_CMP_LT_S = 430, - Mips_CMP_SAF_D = 431, - Mips_CMP_SAF_S = 432, - Mips_CMP_SEQ_D = 433, - Mips_CMP_SEQ_S = 434, - Mips_CMP_SLE_D = 435, - Mips_CMP_SLE_S = 436, - Mips_CMP_SLT_D = 437, - Mips_CMP_SLT_S = 438, - Mips_CMP_SUEQ_D = 439, - Mips_CMP_SUEQ_S = 440, - Mips_CMP_SULE_D = 441, - Mips_CMP_SULE_S = 442, - Mips_CMP_SULT_D = 443, - Mips_CMP_SULT_S = 444, - Mips_CMP_SUN_D = 445, - Mips_CMP_SUN_S = 446, - Mips_CMP_UEQ_D = 447, - Mips_CMP_UEQ_S = 448, - Mips_CMP_ULE_D = 449, - Mips_CMP_ULE_S = 450, - Mips_CMP_ULT_D = 451, - Mips_CMP_ULT_S = 452, - Mips_CMP_UN_D = 453, - Mips_CMP_UN_S = 454, - Mips_CONSTPOOL_ENTRY = 455, - Mips_COPY_FD_PSEUDO = 456, - Mips_COPY_FW_PSEUDO = 457, - Mips_COPY_S_B = 458, - Mips_COPY_S_D = 459, - Mips_COPY_S_H = 460, - Mips_COPY_S_W = 461, - Mips_COPY_U_B = 462, - Mips_COPY_U_D = 463, - Mips_COPY_U_H = 464, - Mips_COPY_U_W = 465, - Mips_CTC1 = 466, - Mips_CTC1_MM = 467, - Mips_CTCMSA = 468, - Mips_CVT_D32_S = 469, - Mips_CVT_D32_W = 470, - Mips_CVT_D32_W_MM = 471, - Mips_CVT_D64_L = 472, - Mips_CVT_D64_S = 473, - Mips_CVT_D64_W = 474, - Mips_CVT_D_S_MM = 475, - Mips_CVT_L_D64 = 476, - Mips_CVT_L_D64_MM = 477, - Mips_CVT_L_S = 478, - Mips_CVT_L_S_MM = 479, - Mips_CVT_S_D32 = 480, - Mips_CVT_S_D32_MM = 481, - Mips_CVT_S_D64 = 482, - Mips_CVT_S_L = 483, - Mips_CVT_S_W = 484, - Mips_CVT_S_W_MM = 485, - Mips_CVT_W_D32 = 486, - Mips_CVT_W_D64 = 487, - Mips_CVT_W_MM = 488, - Mips_CVT_W_S = 489, - Mips_CVT_W_S_MM = 490, - Mips_C_EQ_D32 = 491, - Mips_C_EQ_D64 = 492, - Mips_C_EQ_S = 493, - Mips_C_F_D32 = 494, - Mips_C_F_D64 = 495, - Mips_C_F_S = 496, - Mips_C_LE_D32 = 497, - Mips_C_LE_D64 = 498, - Mips_C_LE_S = 499, - Mips_C_LT_D32 = 500, - Mips_C_LT_D64 = 501, - Mips_C_LT_S = 502, - Mips_C_NGE_D32 = 503, - Mips_C_NGE_D64 = 504, - Mips_C_NGE_S = 505, - Mips_C_NGLE_D32 = 506, - Mips_C_NGLE_D64 = 507, - Mips_C_NGLE_S = 508, - Mips_C_NGL_D32 = 509, - Mips_C_NGL_D64 = 510, - Mips_C_NGL_S = 511, - Mips_C_NGT_D32 = 512, - Mips_C_NGT_D64 = 513, - Mips_C_NGT_S = 514, - Mips_C_OLE_D32 = 515, - Mips_C_OLE_D64 = 516, - Mips_C_OLE_S = 517, - Mips_C_OLT_D32 = 518, - Mips_C_OLT_D64 = 519, - Mips_C_OLT_S = 520, - Mips_C_SEQ_D32 = 521, - Mips_C_SEQ_D64 = 522, - Mips_C_SEQ_S = 523, - Mips_C_SF_D32 = 524, - Mips_C_SF_D64 = 525, - Mips_C_SF_S = 526, - Mips_C_UEQ_D32 = 527, - Mips_C_UEQ_D64 = 528, - Mips_C_UEQ_S = 529, - Mips_C_ULE_D32 = 530, - Mips_C_ULE_D64 = 531, - Mips_C_ULE_S = 532, - Mips_C_ULT_D32 = 533, - Mips_C_ULT_D64 = 534, - Mips_C_ULT_S = 535, - Mips_C_UN_D32 = 536, - Mips_C_UN_D64 = 537, - Mips_C_UN_S = 538, - Mips_CmpRxRy16 = 539, - Mips_CmpiRxImm16 = 540, - Mips_CmpiRxImmX16 = 541, - Mips_Constant32 = 542, - Mips_DADD = 543, - Mips_DADDi = 544, - Mips_DADDiu = 545, - Mips_DADDu = 546, - Mips_DAHI = 547, - Mips_DALIGN = 548, - Mips_DATI = 549, - Mips_DAUI = 550, - Mips_DBITSWAP = 551, - Mips_DCLO = 552, - Mips_DCLO_R6 = 553, - Mips_DCLZ = 554, - Mips_DCLZ_R6 = 555, - Mips_DDIV = 556, - Mips_DDIVU = 557, - Mips_DERET = 558, - Mips_DERET_MM = 559, - Mips_DEXT = 560, - Mips_DEXTM = 561, - Mips_DEXTU = 562, - Mips_DI = 563, - Mips_DINS = 564, - Mips_DINSM = 565, - Mips_DINSU = 566, - Mips_DIV = 567, - Mips_DIVU = 568, - Mips_DIV_S_B = 569, - Mips_DIV_S_D = 570, - Mips_DIV_S_H = 571, - Mips_DIV_S_W = 572, - Mips_DIV_U_B = 573, - Mips_DIV_U_D = 574, - Mips_DIV_U_H = 575, - Mips_DIV_U_W = 576, - Mips_DI_MM = 577, - Mips_DLSA = 578, - Mips_DLSA_R6 = 579, - Mips_DMFC0 = 580, - Mips_DMFC1 = 581, - Mips_DMFC2 = 582, - Mips_DMOD = 583, - Mips_DMODU = 584, - Mips_DMTC0 = 585, - Mips_DMTC1 = 586, - Mips_DMTC2 = 587, - Mips_DMUH = 588, - Mips_DMUHU = 589, - Mips_DMUL = 590, - Mips_DMULT = 591, - Mips_DMULTu = 592, - Mips_DMULU = 593, - Mips_DMUL_R6 = 594, - Mips_DOTP_S_D = 595, - Mips_DOTP_S_H = 596, - Mips_DOTP_S_W = 597, - Mips_DOTP_U_D = 598, - Mips_DOTP_U_H = 599, - Mips_DOTP_U_W = 600, - Mips_DPADD_S_D = 601, - Mips_DPADD_S_H = 602, - Mips_DPADD_S_W = 603, - Mips_DPADD_U_D = 604, - Mips_DPADD_U_H = 605, - Mips_DPADD_U_W = 606, - Mips_DPAQX_SA_W_PH = 607, - Mips_DPAQX_S_W_PH = 608, - Mips_DPAQ_SA_L_W = 609, - Mips_DPAQ_S_W_PH = 610, - Mips_DPAU_H_QBL = 611, - Mips_DPAU_H_QBR = 612, - Mips_DPAX_W_PH = 613, - Mips_DPA_W_PH = 614, - Mips_DPOP = 615, - Mips_DPSQX_SA_W_PH = 616, - Mips_DPSQX_S_W_PH = 617, - Mips_DPSQ_SA_L_W = 618, - Mips_DPSQ_S_W_PH = 619, - Mips_DPSUB_S_D = 620, - Mips_DPSUB_S_H = 621, - Mips_DPSUB_S_W = 622, - Mips_DPSUB_U_D = 623, - Mips_DPSUB_U_H = 624, - Mips_DPSUB_U_W = 625, - Mips_DPSU_H_QBL = 626, - Mips_DPSU_H_QBR = 627, - Mips_DPSX_W_PH = 628, - Mips_DPS_W_PH = 629, - Mips_DROTR = 630, - Mips_DROTR32 = 631, - Mips_DROTRV = 632, - Mips_DSBH = 633, - Mips_DSDIV = 634, - Mips_DSHD = 635, - Mips_DSLL = 636, - Mips_DSLL32 = 637, - Mips_DSLL64_32 = 638, - Mips_DSLLV = 639, - Mips_DSRA = 640, - Mips_DSRA32 = 641, - Mips_DSRAV = 642, - Mips_DSRL = 643, - Mips_DSRL32 = 644, - Mips_DSRLV = 645, - Mips_DSUB = 646, - Mips_DSUBu = 647, - Mips_DUDIV = 648, - Mips_DivRxRy16 = 649, - Mips_DivuRxRy16 = 650, - Mips_EHB = 651, - Mips_EHB_MM = 652, - Mips_EI = 653, - Mips_EI_MM = 654, - Mips_ERET = 655, - Mips_ERET_MM = 656, - Mips_EXT = 657, - Mips_EXTP = 658, - Mips_EXTPDP = 659, - Mips_EXTPDPV = 660, - Mips_EXTPV = 661, - Mips_EXTRV_RS_W = 662, - Mips_EXTRV_R_W = 663, - Mips_EXTRV_S_H = 664, - Mips_EXTRV_W = 665, - Mips_EXTR_RS_W = 666, - Mips_EXTR_R_W = 667, - Mips_EXTR_S_H = 668, - Mips_EXTR_W = 669, - Mips_EXTS = 670, - Mips_EXTS32 = 671, - Mips_EXT_MM = 672, - Mips_ExtractElementF64 = 673, - Mips_ExtractElementF64_64 = 674, - Mips_FABS_D = 675, - Mips_FABS_D32 = 676, - Mips_FABS_D64 = 677, - Mips_FABS_MM = 678, - Mips_FABS_S = 679, - Mips_FABS_S_MM = 680, - Mips_FABS_W = 681, - Mips_FADD_D = 682, - Mips_FADD_D32 = 683, - Mips_FADD_D64 = 684, - Mips_FADD_MM = 685, - Mips_FADD_S = 686, - Mips_FADD_S_MM = 687, - Mips_FADD_W = 688, - Mips_FCAF_D = 689, - Mips_FCAF_W = 690, - Mips_FCEQ_D = 691, - Mips_FCEQ_W = 692, - Mips_FCLASS_D = 693, - Mips_FCLASS_W = 694, - Mips_FCLE_D = 695, - Mips_FCLE_W = 696, - Mips_FCLT_D = 697, - Mips_FCLT_W = 698, - Mips_FCMP_D32 = 699, - Mips_FCMP_D32_MM = 700, - Mips_FCMP_D64 = 701, - Mips_FCMP_S32 = 702, - Mips_FCMP_S32_MM = 703, - Mips_FCNE_D = 704, - Mips_FCNE_W = 705, - Mips_FCOR_D = 706, - Mips_FCOR_W = 707, - Mips_FCUEQ_D = 708, - Mips_FCUEQ_W = 709, - Mips_FCULE_D = 710, - Mips_FCULE_W = 711, - Mips_FCULT_D = 712, - Mips_FCULT_W = 713, - Mips_FCUNE_D = 714, - Mips_FCUNE_W = 715, - Mips_FCUN_D = 716, - Mips_FCUN_W = 717, - Mips_FDIV_D = 718, - Mips_FDIV_D32 = 719, - Mips_FDIV_D64 = 720, - Mips_FDIV_MM = 721, - Mips_FDIV_S = 722, - Mips_FDIV_S_MM = 723, - Mips_FDIV_W = 724, - Mips_FEXDO_H = 725, - Mips_FEXDO_W = 726, - Mips_FEXP2_D = 727, - Mips_FEXP2_D_1_PSEUDO = 728, - Mips_FEXP2_W = 729, - Mips_FEXP2_W_1_PSEUDO = 730, - Mips_FEXUPL_D = 731, - Mips_FEXUPL_W = 732, - Mips_FEXUPR_D = 733, - Mips_FEXUPR_W = 734, - Mips_FFINT_S_D = 735, - Mips_FFINT_S_W = 736, - Mips_FFINT_U_D = 737, - Mips_FFINT_U_W = 738, - Mips_FFQL_D = 739, - Mips_FFQL_W = 740, - Mips_FFQR_D = 741, - Mips_FFQR_W = 742, - Mips_FILL_B = 743, - Mips_FILL_D = 744, - Mips_FILL_FD_PSEUDO = 745, - Mips_FILL_FW_PSEUDO = 746, - Mips_FILL_H = 747, - Mips_FILL_W = 748, - Mips_FLOG2_D = 749, - Mips_FLOG2_W = 750, - Mips_FLOOR_L_D64 = 751, - Mips_FLOOR_L_S = 752, - Mips_FLOOR_W_D32 = 753, - Mips_FLOOR_W_D64 = 754, - Mips_FLOOR_W_MM = 755, - Mips_FLOOR_W_S = 756, - Mips_FLOOR_W_S_MM = 757, - Mips_FMADD_D = 758, - Mips_FMADD_W = 759, - Mips_FMAX_A_D = 760, - Mips_FMAX_A_W = 761, - Mips_FMAX_D = 762, - Mips_FMAX_W = 763, - Mips_FMIN_A_D = 764, - Mips_FMIN_A_W = 765, - Mips_FMIN_D = 766, - Mips_FMIN_W = 767, - Mips_FMOV_D32 = 768, - Mips_FMOV_D32_MM = 769, - Mips_FMOV_D64 = 770, - Mips_FMOV_S = 771, - Mips_FMOV_S_MM = 772, - Mips_FMSUB_D = 773, - Mips_FMSUB_W = 774, - Mips_FMUL_D = 775, - Mips_FMUL_D32 = 776, - Mips_FMUL_D64 = 777, - Mips_FMUL_MM = 778, - Mips_FMUL_S = 779, - Mips_FMUL_S_MM = 780, - Mips_FMUL_W = 781, - Mips_FNEG_D32 = 782, - Mips_FNEG_D64 = 783, - Mips_FNEG_MM = 784, - Mips_FNEG_S = 785, - Mips_FNEG_S_MM = 786, - Mips_FRCP_D = 787, - Mips_FRCP_W = 788, - Mips_FRINT_D = 789, - Mips_FRINT_W = 790, - Mips_FRSQRT_D = 791, - Mips_FRSQRT_W = 792, - Mips_FSAF_D = 793, - Mips_FSAF_W = 794, - Mips_FSEQ_D = 795, - Mips_FSEQ_W = 796, - Mips_FSLE_D = 797, - Mips_FSLE_W = 798, - Mips_FSLT_D = 799, - Mips_FSLT_W = 800, - Mips_FSNE_D = 801, - Mips_FSNE_W = 802, - Mips_FSOR_D = 803, - Mips_FSOR_W = 804, - Mips_FSQRT_D = 805, - Mips_FSQRT_D32 = 806, - Mips_FSQRT_D64 = 807, - Mips_FSQRT_MM = 808, - Mips_FSQRT_S = 809, - Mips_FSQRT_S_MM = 810, - Mips_FSQRT_W = 811, - Mips_FSUB_D = 812, - Mips_FSUB_D32 = 813, - Mips_FSUB_D64 = 814, - Mips_FSUB_MM = 815, - Mips_FSUB_S = 816, - Mips_FSUB_S_MM = 817, - Mips_FSUB_W = 818, - Mips_FSUEQ_D = 819, - Mips_FSUEQ_W = 820, - Mips_FSULE_D = 821, - Mips_FSULE_W = 822, - Mips_FSULT_D = 823, - Mips_FSULT_W = 824, - Mips_FSUNE_D = 825, - Mips_FSUNE_W = 826, - Mips_FSUN_D = 827, - Mips_FSUN_W = 828, - Mips_FTINT_S_D = 829, - Mips_FTINT_S_W = 830, - Mips_FTINT_U_D = 831, - Mips_FTINT_U_W = 832, - Mips_FTQ_H = 833, - Mips_FTQ_W = 834, - Mips_FTRUNC_S_D = 835, - Mips_FTRUNC_S_W = 836, - Mips_FTRUNC_U_D = 837, - Mips_FTRUNC_U_W = 838, - Mips_GotPrologue16 = 839, - Mips_HADD_S_D = 840, - Mips_HADD_S_H = 841, - Mips_HADD_S_W = 842, - Mips_HADD_U_D = 843, - Mips_HADD_U_H = 844, - Mips_HADD_U_W = 845, - Mips_HSUB_S_D = 846, - Mips_HSUB_S_H = 847, - Mips_HSUB_S_W = 848, - Mips_HSUB_U_D = 849, - Mips_HSUB_U_H = 850, - Mips_HSUB_U_W = 851, - Mips_ILVEV_B = 852, - Mips_ILVEV_D = 853, - Mips_ILVEV_H = 854, - Mips_ILVEV_W = 855, - Mips_ILVL_B = 856, - Mips_ILVL_D = 857, - Mips_ILVL_H = 858, - Mips_ILVL_W = 859, - Mips_ILVOD_B = 860, - Mips_ILVOD_D = 861, - Mips_ILVOD_H = 862, - Mips_ILVOD_W = 863, - Mips_ILVR_B = 864, - Mips_ILVR_D = 865, - Mips_ILVR_H = 866, - Mips_ILVR_W = 867, - Mips_INS = 868, - Mips_INSERT_B = 869, - Mips_INSERT_B_VIDX_PSEUDO = 870, - Mips_INSERT_D = 871, - Mips_INSERT_D_VIDX_PSEUDO = 872, - Mips_INSERT_FD_PSEUDO = 873, - Mips_INSERT_FD_VIDX_PSEUDO = 874, - Mips_INSERT_FW_PSEUDO = 875, - Mips_INSERT_FW_VIDX_PSEUDO = 876, - Mips_INSERT_H = 877, - Mips_INSERT_H_VIDX_PSEUDO = 878, - Mips_INSERT_W = 879, - Mips_INSERT_W_VIDX_PSEUDO = 880, - Mips_INSV = 881, - Mips_INSVE_B = 882, - Mips_INSVE_D = 883, - Mips_INSVE_H = 884, - Mips_INSVE_W = 885, - Mips_INS_MM = 886, - Mips_J = 887, - Mips_JAL = 888, - Mips_JALR = 889, - Mips_JALR16_MM = 890, - Mips_JALR64 = 891, - Mips_JALR64Pseudo = 892, - Mips_JALRPseudo = 893, - Mips_JALRS16_MM = 894, - Mips_JALRS_MM = 895, - Mips_JALR_HB = 896, - Mips_JALR_MM = 897, - Mips_JALS_MM = 898, - Mips_JALX = 899, - Mips_JALX_MM = 900, - Mips_JAL_MM = 901, - Mips_JIALC = 902, - Mips_JIC = 903, - Mips_JR = 904, - Mips_JR16_MM = 905, - Mips_JR64 = 906, - Mips_JRADDIUSP = 907, - Mips_JRC16_MM = 908, - Mips_JR_HB = 909, - Mips_JR_HB_R6 = 910, - Mips_JR_MM = 911, - Mips_J_MM = 912, - Mips_Jal16 = 913, - Mips_JalB16 = 914, - Mips_JalOneReg = 915, - Mips_JalTwoReg = 916, - Mips_JrRa16 = 917, - Mips_JrcRa16 = 918, - Mips_JrcRx16 = 919, - Mips_JumpLinkReg16 = 920, - Mips_LB = 921, - Mips_LB64 = 922, - Mips_LBU16_MM = 923, - Mips_LBUX = 924, - Mips_LB_MM = 925, - Mips_LBu = 926, - Mips_LBu64 = 927, - Mips_LBu_MM = 928, - Mips_LD = 929, - Mips_LDC1 = 930, - Mips_LDC164 = 931, - Mips_LDC1_MM = 932, - Mips_LDC2 = 933, - Mips_LDC2_R6 = 934, - Mips_LDC3 = 935, - Mips_LDI_B = 936, - Mips_LDI_D = 937, - Mips_LDI_H = 938, - Mips_LDI_W = 939, - Mips_LDL = 940, - Mips_LDPC = 941, - Mips_LDR = 942, - Mips_LDXC1 = 943, - Mips_LDXC164 = 944, - Mips_LD_B = 945, - Mips_LD_D = 946, - Mips_LD_H = 947, - Mips_LD_W = 948, - Mips_LEA_ADDiu = 949, - Mips_LEA_ADDiu64 = 950, - Mips_LEA_ADDiu_MM = 951, - Mips_LH = 952, - Mips_LH64 = 953, - Mips_LHU16_MM = 954, - Mips_LHX = 955, - Mips_LH_MM = 956, - Mips_LHu = 957, - Mips_LHu64 = 958, - Mips_LHu_MM = 959, - Mips_LI16_MM = 960, - Mips_LL = 961, - Mips_LLD = 962, - Mips_LLD_R6 = 963, - Mips_LL_MM = 964, - Mips_LL_R6 = 965, - Mips_LOAD_ACC128 = 966, - Mips_LOAD_ACC64 = 967, - Mips_LOAD_ACC64DSP = 968, - Mips_LOAD_CCOND_DSP = 969, - Mips_LONG_BRANCH_ADDiu = 970, - Mips_LONG_BRANCH_DADDiu = 971, - Mips_LONG_BRANCH_LUi = 972, - Mips_LSA = 973, - Mips_LSA_R6 = 974, - Mips_LUXC1 = 975, - Mips_LUXC164 = 976, - Mips_LUXC1_MM = 977, - Mips_LUi = 978, - Mips_LUi64 = 979, - Mips_LUi_MM = 980, - Mips_LW = 981, - Mips_LW16_MM = 982, - Mips_LW64 = 983, - Mips_LWC1 = 984, - Mips_LWC1_MM = 985, - Mips_LWC2 = 986, - Mips_LWC2_R6 = 987, - Mips_LWC3 = 988, - Mips_LWGP_MM = 989, - Mips_LWL = 990, - Mips_LWL64 = 991, - Mips_LWL_MM = 992, - Mips_LWM16_MM = 993, - Mips_LWM32_MM = 994, - Mips_LWM_MM = 995, - Mips_LWPC = 996, - Mips_LWP_MM = 997, - Mips_LWR = 998, - Mips_LWR64 = 999, - Mips_LWR_MM = 1000, - Mips_LWSP_MM = 1001, - Mips_LWUPC = 1002, - Mips_LWU_MM = 1003, - Mips_LWX = 1004, - Mips_LWXC1 = 1005, - Mips_LWXC1_MM = 1006, - Mips_LWXS_MM = 1007, - Mips_LW_MM = 1008, - Mips_LWu = 1009, - Mips_LbRxRyOffMemX16 = 1010, - Mips_LbuRxRyOffMemX16 = 1011, - Mips_LhRxRyOffMemX16 = 1012, - Mips_LhuRxRyOffMemX16 = 1013, - Mips_LiRxImm16 = 1014, - Mips_LiRxImmAlignX16 = 1015, - Mips_LiRxImmX16 = 1016, - Mips_LoadAddr32Imm = 1017, - Mips_LoadAddr32Reg = 1018, - Mips_LoadImm32Reg = 1019, - Mips_LoadImm64Reg = 1020, - Mips_LwConstant32 = 1021, - Mips_LwRxPcTcp16 = 1022, - Mips_LwRxPcTcpX16 = 1023, - Mips_LwRxRyOffMemX16 = 1024, - Mips_LwRxSpImmX16 = 1025, - Mips_MADD = 1026, - Mips_MADDF_D = 1027, - Mips_MADDF_S = 1028, - Mips_MADDR_Q_H = 1029, - Mips_MADDR_Q_W = 1030, - Mips_MADDU = 1031, - Mips_MADDU_DSP = 1032, - Mips_MADDU_MM = 1033, - Mips_MADDV_B = 1034, - Mips_MADDV_D = 1035, - Mips_MADDV_H = 1036, - Mips_MADDV_W = 1037, - Mips_MADD_D32 = 1038, - Mips_MADD_D32_MM = 1039, - Mips_MADD_D64 = 1040, - Mips_MADD_DSP = 1041, - Mips_MADD_MM = 1042, - Mips_MADD_Q_H = 1043, - Mips_MADD_Q_W = 1044, - Mips_MADD_S = 1045, - Mips_MADD_S_MM = 1046, - Mips_MAQ_SA_W_PHL = 1047, - Mips_MAQ_SA_W_PHR = 1048, - Mips_MAQ_S_W_PHL = 1049, - Mips_MAQ_S_W_PHR = 1050, - Mips_MAXA_D = 1051, - Mips_MAXA_S = 1052, - Mips_MAXI_S_B = 1053, - Mips_MAXI_S_D = 1054, - Mips_MAXI_S_H = 1055, - Mips_MAXI_S_W = 1056, - Mips_MAXI_U_B = 1057, - Mips_MAXI_U_D = 1058, - Mips_MAXI_U_H = 1059, - Mips_MAXI_U_W = 1060, - Mips_MAX_A_B = 1061, - Mips_MAX_A_D = 1062, - Mips_MAX_A_H = 1063, - Mips_MAX_A_W = 1064, - Mips_MAX_D = 1065, - Mips_MAX_S = 1066, - Mips_MAX_S_B = 1067, - Mips_MAX_S_D = 1068, - Mips_MAX_S_H = 1069, - Mips_MAX_S_W = 1070, - Mips_MAX_U_B = 1071, - Mips_MAX_U_D = 1072, - Mips_MAX_U_H = 1073, - Mips_MAX_U_W = 1074, - Mips_MFC0 = 1075, - Mips_MFC1 = 1076, - Mips_MFC1_MM = 1077, - Mips_MFC2 = 1078, - Mips_MFHC1_D32 = 1079, - Mips_MFHC1_D64 = 1080, - Mips_MFHC1_MM = 1081, - Mips_MFHI = 1082, - Mips_MFHI16_MM = 1083, - Mips_MFHI64 = 1084, - Mips_MFHI_DSP = 1085, - Mips_MFHI_MM = 1086, - Mips_MFLO = 1087, - Mips_MFLO16_MM = 1088, - Mips_MFLO64 = 1089, - Mips_MFLO_DSP = 1090, - Mips_MFLO_MM = 1091, - Mips_MINA_D = 1092, - Mips_MINA_S = 1093, - Mips_MINI_S_B = 1094, - Mips_MINI_S_D = 1095, - Mips_MINI_S_H = 1096, - Mips_MINI_S_W = 1097, - Mips_MINI_U_B = 1098, - Mips_MINI_U_D = 1099, - Mips_MINI_U_H = 1100, - Mips_MINI_U_W = 1101, - Mips_MIN_A_B = 1102, - Mips_MIN_A_D = 1103, - Mips_MIN_A_H = 1104, - Mips_MIN_A_W = 1105, - Mips_MIN_D = 1106, - Mips_MIN_S = 1107, - Mips_MIN_S_B = 1108, - Mips_MIN_S_D = 1109, - Mips_MIN_S_H = 1110, - Mips_MIN_S_W = 1111, - Mips_MIN_U_B = 1112, - Mips_MIN_U_D = 1113, - Mips_MIN_U_H = 1114, - Mips_MIN_U_W = 1115, - Mips_MIPSeh_return32 = 1116, - Mips_MIPSeh_return64 = 1117, - Mips_MOD = 1118, - Mips_MODSUB = 1119, - Mips_MODU = 1120, - Mips_MOD_S_B = 1121, - Mips_MOD_S_D = 1122, - Mips_MOD_S_H = 1123, - Mips_MOD_S_W = 1124, - Mips_MOD_U_B = 1125, - Mips_MOD_U_D = 1126, - Mips_MOD_U_H = 1127, - Mips_MOD_U_W = 1128, - Mips_MOVE16_MM = 1129, - Mips_MOVEP_MM = 1130, - Mips_MOVE_V = 1131, - Mips_MOVF_D32 = 1132, - Mips_MOVF_D32_MM = 1133, - Mips_MOVF_D64 = 1134, - Mips_MOVF_I = 1135, - Mips_MOVF_I64 = 1136, - Mips_MOVF_I_MM = 1137, - Mips_MOVF_S = 1138, - Mips_MOVF_S_MM = 1139, - Mips_MOVN_I64_D64 = 1140, - Mips_MOVN_I64_I = 1141, - Mips_MOVN_I64_I64 = 1142, - Mips_MOVN_I64_S = 1143, - Mips_MOVN_I_D32 = 1144, - Mips_MOVN_I_D32_MM = 1145, - Mips_MOVN_I_D64 = 1146, - Mips_MOVN_I_I = 1147, - Mips_MOVN_I_I64 = 1148, - Mips_MOVN_I_MM = 1149, - Mips_MOVN_I_S = 1150, - Mips_MOVN_I_S_MM = 1151, - Mips_MOVT_D32 = 1152, - Mips_MOVT_D32_MM = 1153, - Mips_MOVT_D64 = 1154, - Mips_MOVT_I = 1155, - Mips_MOVT_I64 = 1156, - Mips_MOVT_I_MM = 1157, - Mips_MOVT_S = 1158, - Mips_MOVT_S_MM = 1159, - Mips_MOVZ_I64_D64 = 1160, - Mips_MOVZ_I64_I = 1161, - Mips_MOVZ_I64_I64 = 1162, - Mips_MOVZ_I64_S = 1163, - Mips_MOVZ_I_D32 = 1164, - Mips_MOVZ_I_D32_MM = 1165, - Mips_MOVZ_I_D64 = 1166, - Mips_MOVZ_I_I = 1167, - Mips_MOVZ_I_I64 = 1168, - Mips_MOVZ_I_MM = 1169, - Mips_MOVZ_I_S = 1170, - Mips_MOVZ_I_S_MM = 1171, - Mips_MSUB = 1172, - Mips_MSUBF_D = 1173, - Mips_MSUBF_S = 1174, - Mips_MSUBR_Q_H = 1175, - Mips_MSUBR_Q_W = 1176, - Mips_MSUBU = 1177, - Mips_MSUBU_DSP = 1178, - Mips_MSUBU_MM = 1179, - Mips_MSUBV_B = 1180, - Mips_MSUBV_D = 1181, - Mips_MSUBV_H = 1182, - Mips_MSUBV_W = 1183, - Mips_MSUB_D32 = 1184, - Mips_MSUB_D32_MM = 1185, - Mips_MSUB_D64 = 1186, - Mips_MSUB_DSP = 1187, - Mips_MSUB_MM = 1188, - Mips_MSUB_Q_H = 1189, - Mips_MSUB_Q_W = 1190, - Mips_MSUB_S = 1191, - Mips_MSUB_S_MM = 1192, - Mips_MTC0 = 1193, - Mips_MTC1 = 1194, - Mips_MTC1_MM = 1195, - Mips_MTC2 = 1196, - Mips_MTHC1_D32 = 1197, - Mips_MTHC1_D64 = 1198, - Mips_MTHC1_MM = 1199, - Mips_MTHI = 1200, - Mips_MTHI64 = 1201, - Mips_MTHI_DSP = 1202, - Mips_MTHI_MM = 1203, - Mips_MTHLIP = 1204, - Mips_MTLO = 1205, - Mips_MTLO64 = 1206, - Mips_MTLO_DSP = 1207, - Mips_MTLO_MM = 1208, - Mips_MTM0 = 1209, - Mips_MTM1 = 1210, - Mips_MTM2 = 1211, - Mips_MTP0 = 1212, - Mips_MTP1 = 1213, - Mips_MTP2 = 1214, - Mips_MUH = 1215, - Mips_MUHU = 1216, - Mips_MUL = 1217, - Mips_MULEQ_S_W_PHL = 1218, - Mips_MULEQ_S_W_PHR = 1219, - Mips_MULEU_S_PH_QBL = 1220, - Mips_MULEU_S_PH_QBR = 1221, - Mips_MULQ_RS_PH = 1222, - Mips_MULQ_RS_W = 1223, - Mips_MULQ_S_PH = 1224, - Mips_MULQ_S_W = 1225, - Mips_MULR_Q_H = 1226, - Mips_MULR_Q_W = 1227, - Mips_MULSAQ_S_W_PH = 1228, - Mips_MULSA_W_PH = 1229, - Mips_MULT = 1230, - Mips_MULTU_DSP = 1231, - Mips_MULT_DSP = 1232, - Mips_MULT_MM = 1233, - Mips_MULTu = 1234, - Mips_MULTu_MM = 1235, - Mips_MULU = 1236, - Mips_MULV_B = 1237, - Mips_MULV_D = 1238, - Mips_MULV_H = 1239, - Mips_MULV_W = 1240, - Mips_MUL_MM = 1241, - Mips_MUL_PH = 1242, - Mips_MUL_Q_H = 1243, - Mips_MUL_Q_W = 1244, - Mips_MUL_R6 = 1245, - Mips_MUL_S_PH = 1246, - Mips_Mfhi16 = 1247, - Mips_Mflo16 = 1248, - Mips_Move32R16 = 1249, - Mips_MoveR3216 = 1250, - Mips_MultRxRy16 = 1251, - Mips_MultRxRyRz16 = 1252, - Mips_MultuRxRy16 = 1253, - Mips_MultuRxRyRz16 = 1254, - Mips_NLOC_B = 1255, - Mips_NLOC_D = 1256, - Mips_NLOC_H = 1257, - Mips_NLOC_W = 1258, - Mips_NLZC_B = 1259, - Mips_NLZC_D = 1260, - Mips_NLZC_H = 1261, - Mips_NLZC_W = 1262, - Mips_NMADD_D32 = 1263, - Mips_NMADD_D32_MM = 1264, - Mips_NMADD_D64 = 1265, - Mips_NMADD_S = 1266, - Mips_NMADD_S_MM = 1267, - Mips_NMSUB_D32 = 1268, - Mips_NMSUB_D32_MM = 1269, - Mips_NMSUB_D64 = 1270, - Mips_NMSUB_S = 1271, - Mips_NMSUB_S_MM = 1272, - Mips_NOP = 1273, - Mips_NOR = 1274, - Mips_NOR64 = 1275, - Mips_NORI_B = 1276, - Mips_NOR_MM = 1277, - Mips_NOR_V = 1278, - Mips_NOR_V_D_PSEUDO = 1279, - Mips_NOR_V_H_PSEUDO = 1280, - Mips_NOR_V_W_PSEUDO = 1281, - Mips_NOT16_MM = 1282, - Mips_NegRxRy16 = 1283, - Mips_NotRxRy16 = 1284, - Mips_OR = 1285, - Mips_OR16_MM = 1286, - Mips_OR64 = 1287, - Mips_ORI_B = 1288, - Mips_OR_MM = 1289, - Mips_OR_V = 1290, - Mips_OR_V_D_PSEUDO = 1291, - Mips_OR_V_H_PSEUDO = 1292, - Mips_OR_V_W_PSEUDO = 1293, - Mips_ORi = 1294, - Mips_ORi64 = 1295, - Mips_ORi_MM = 1296, - Mips_OrRxRxRy16 = 1297, - Mips_PACKRL_PH = 1298, - Mips_PAUSE = 1299, - Mips_PAUSE_MM = 1300, - Mips_PCKEV_B = 1301, - Mips_PCKEV_D = 1302, - Mips_PCKEV_H = 1303, - Mips_PCKEV_W = 1304, - Mips_PCKOD_B = 1305, - Mips_PCKOD_D = 1306, - Mips_PCKOD_H = 1307, - Mips_PCKOD_W = 1308, - Mips_PCNT_B = 1309, - Mips_PCNT_D = 1310, - Mips_PCNT_H = 1311, - Mips_PCNT_W = 1312, - Mips_PICK_PH = 1313, - Mips_PICK_QB = 1314, - Mips_POP = 1315, - Mips_PRECEQU_PH_QBL = 1316, - Mips_PRECEQU_PH_QBLA = 1317, - Mips_PRECEQU_PH_QBR = 1318, - Mips_PRECEQU_PH_QBRA = 1319, - Mips_PRECEQ_W_PHL = 1320, - Mips_PRECEQ_W_PHR = 1321, - Mips_PRECEU_PH_QBL = 1322, - Mips_PRECEU_PH_QBLA = 1323, - Mips_PRECEU_PH_QBR = 1324, - Mips_PRECEU_PH_QBRA = 1325, - Mips_PRECRQU_S_QB_PH = 1326, - Mips_PRECRQ_PH_W = 1327, - Mips_PRECRQ_QB_PH = 1328, - Mips_PRECRQ_RS_PH_W = 1329, - Mips_PRECR_QB_PH = 1330, - Mips_PRECR_SRA_PH_W = 1331, - Mips_PRECR_SRA_R_PH_W = 1332, - Mips_PREF = 1333, - Mips_PREF_MM = 1334, - Mips_PREF_R6 = 1335, - Mips_PREPEND = 1336, - Mips_PseudoCMPU_EQ_QB = 1337, - Mips_PseudoCMPU_LE_QB = 1338, - Mips_PseudoCMPU_LT_QB = 1339, - Mips_PseudoCMP_EQ_PH = 1340, - Mips_PseudoCMP_LE_PH = 1341, - Mips_PseudoCMP_LT_PH = 1342, - Mips_PseudoCVT_D32_W = 1343, - Mips_PseudoCVT_D64_L = 1344, - Mips_PseudoCVT_D64_W = 1345, - Mips_PseudoCVT_S_L = 1346, - Mips_PseudoCVT_S_W = 1347, - Mips_PseudoDMULT = 1348, - Mips_PseudoDMULTu = 1349, - Mips_PseudoDSDIV = 1350, - Mips_PseudoDUDIV = 1351, - Mips_PseudoIndirectBranch = 1352, - Mips_PseudoIndirectBranch64 = 1353, - Mips_PseudoMADD = 1354, - Mips_PseudoMADDU = 1355, - Mips_PseudoMFHI = 1356, - Mips_PseudoMFHI64 = 1357, - Mips_PseudoMFLO = 1358, - Mips_PseudoMFLO64 = 1359, - Mips_PseudoMSUB = 1360, - Mips_PseudoMSUBU = 1361, - Mips_PseudoMTLOHI = 1362, - Mips_PseudoMTLOHI64 = 1363, - Mips_PseudoMTLOHI_DSP = 1364, - Mips_PseudoMULT = 1365, - Mips_PseudoMULTu = 1366, - Mips_PseudoPICK_PH = 1367, - Mips_PseudoPICK_QB = 1368, - Mips_PseudoReturn = 1369, - Mips_PseudoReturn64 = 1370, - Mips_PseudoSDIV = 1371, - Mips_PseudoSELECTFP_F_D32 = 1372, - Mips_PseudoSELECTFP_F_D64 = 1373, - Mips_PseudoSELECTFP_F_I = 1374, - Mips_PseudoSELECTFP_F_I64 = 1375, - Mips_PseudoSELECTFP_F_S = 1376, - Mips_PseudoSELECTFP_T_D32 = 1377, - Mips_PseudoSELECTFP_T_D64 = 1378, - Mips_PseudoSELECTFP_T_I = 1379, - Mips_PseudoSELECTFP_T_I64 = 1380, - Mips_PseudoSELECTFP_T_S = 1381, - Mips_PseudoSELECT_D32 = 1382, - Mips_PseudoSELECT_D64 = 1383, - Mips_PseudoSELECT_I = 1384, - Mips_PseudoSELECT_I64 = 1385, - Mips_PseudoSELECT_S = 1386, - Mips_PseudoUDIV = 1387, - Mips_RADDU_W_QB = 1388, - Mips_RDDSP = 1389, - Mips_RDHWR = 1390, - Mips_RDHWR64 = 1391, - Mips_RDHWR_MM = 1392, - Mips_REPLV_PH = 1393, - Mips_REPLV_QB = 1394, - Mips_REPL_PH = 1395, - Mips_REPL_QB = 1396, - Mips_RINT_D = 1397, - Mips_RINT_S = 1398, - Mips_ROTR = 1399, - Mips_ROTRV = 1400, - Mips_ROTRV_MM = 1401, - Mips_ROTR_MM = 1402, - Mips_ROUND_L_D64 = 1403, - Mips_ROUND_L_S = 1404, - Mips_ROUND_W_D32 = 1405, - Mips_ROUND_W_D64 = 1406, - Mips_ROUND_W_MM = 1407, - Mips_ROUND_W_S = 1408, - Mips_ROUND_W_S_MM = 1409, - Mips_Restore16 = 1410, - Mips_RestoreX16 = 1411, - Mips_RetRA = 1412, - Mips_RetRA16 = 1413, - Mips_SAT_S_B = 1414, - Mips_SAT_S_D = 1415, - Mips_SAT_S_H = 1416, - Mips_SAT_S_W = 1417, - Mips_SAT_U_B = 1418, - Mips_SAT_U_D = 1419, - Mips_SAT_U_H = 1420, - Mips_SAT_U_W = 1421, - Mips_SB = 1422, - Mips_SB16_MM = 1423, - Mips_SB64 = 1424, - Mips_SB_MM = 1425, - Mips_SC = 1426, - Mips_SCD = 1427, - Mips_SCD_R6 = 1428, - Mips_SC_MM = 1429, - Mips_SC_R6 = 1430, - Mips_SD = 1431, - Mips_SDBBP = 1432, - Mips_SDBBP16_MM = 1433, - Mips_SDBBP_MM = 1434, - Mips_SDBBP_R6 = 1435, - Mips_SDC1 = 1436, - Mips_SDC164 = 1437, - Mips_SDC1_MM = 1438, - Mips_SDC2 = 1439, - Mips_SDC2_R6 = 1440, - Mips_SDC3 = 1441, - Mips_SDIV = 1442, - Mips_SDIV_MM = 1443, - Mips_SDL = 1444, - Mips_SDR = 1445, - Mips_SDXC1 = 1446, - Mips_SDXC164 = 1447, - Mips_SEB = 1448, - Mips_SEB64 = 1449, - Mips_SEB_MM = 1450, - Mips_SEH = 1451, - Mips_SEH64 = 1452, - Mips_SEH_MM = 1453, - Mips_SELEQZ = 1454, - Mips_SELEQZ64 = 1455, - Mips_SELEQZ_D = 1456, - Mips_SELEQZ_S = 1457, - Mips_SELNEZ = 1458, - Mips_SELNEZ64 = 1459, - Mips_SELNEZ_D = 1460, - Mips_SELNEZ_S = 1461, - Mips_SEL_D = 1462, - Mips_SEL_S = 1463, - Mips_SEQ = 1464, - Mips_SEQi = 1465, - Mips_SH = 1466, - Mips_SH16_MM = 1467, - Mips_SH64 = 1468, - Mips_SHF_B = 1469, - Mips_SHF_H = 1470, - Mips_SHF_W = 1471, - Mips_SHILO = 1472, - Mips_SHILOV = 1473, - Mips_SHLLV_PH = 1474, - Mips_SHLLV_QB = 1475, - Mips_SHLLV_S_PH = 1476, - Mips_SHLLV_S_W = 1477, - Mips_SHLL_PH = 1478, - Mips_SHLL_QB = 1479, - Mips_SHLL_S_PH = 1480, - Mips_SHLL_S_W = 1481, - Mips_SHRAV_PH = 1482, - Mips_SHRAV_QB = 1483, - Mips_SHRAV_R_PH = 1484, - Mips_SHRAV_R_QB = 1485, - Mips_SHRAV_R_W = 1486, - Mips_SHRA_PH = 1487, - Mips_SHRA_QB = 1488, - Mips_SHRA_R_PH = 1489, - Mips_SHRA_R_QB = 1490, - Mips_SHRA_R_W = 1491, - Mips_SHRLV_PH = 1492, - Mips_SHRLV_QB = 1493, - Mips_SHRL_PH = 1494, - Mips_SHRL_QB = 1495, - Mips_SH_MM = 1496, - Mips_SLDI_B = 1497, - Mips_SLDI_D = 1498, - Mips_SLDI_H = 1499, - Mips_SLDI_W = 1500, - Mips_SLD_B = 1501, - Mips_SLD_D = 1502, - Mips_SLD_H = 1503, - Mips_SLD_W = 1504, - Mips_SLL = 1505, - Mips_SLL16_MM = 1506, - Mips_SLL64_32 = 1507, - Mips_SLL64_64 = 1508, - Mips_SLLI_B = 1509, - Mips_SLLI_D = 1510, - Mips_SLLI_H = 1511, - Mips_SLLI_W = 1512, - Mips_SLLV = 1513, - Mips_SLLV_MM = 1514, - Mips_SLL_B = 1515, - Mips_SLL_D = 1516, - Mips_SLL_H = 1517, - Mips_SLL_MM = 1518, - Mips_SLL_W = 1519, - Mips_SLT = 1520, - Mips_SLT64 = 1521, - Mips_SLT_MM = 1522, - Mips_SLTi = 1523, - Mips_SLTi64 = 1524, - Mips_SLTi_MM = 1525, - Mips_SLTiu = 1526, - Mips_SLTiu64 = 1527, - Mips_SLTiu_MM = 1528, - Mips_SLTu = 1529, - Mips_SLTu64 = 1530, - Mips_SLTu_MM = 1531, - Mips_SNE = 1532, - Mips_SNEi = 1533, - Mips_SNZ_B_PSEUDO = 1534, - Mips_SNZ_D_PSEUDO = 1535, - Mips_SNZ_H_PSEUDO = 1536, - Mips_SNZ_V_PSEUDO = 1537, - Mips_SNZ_W_PSEUDO = 1538, - Mips_SPLATI_B = 1539, - Mips_SPLATI_D = 1540, - Mips_SPLATI_H = 1541, - Mips_SPLATI_W = 1542, - Mips_SPLAT_B = 1543, - Mips_SPLAT_D = 1544, - Mips_SPLAT_H = 1545, - Mips_SPLAT_W = 1546, - Mips_SRA = 1547, - Mips_SRAI_B = 1548, - Mips_SRAI_D = 1549, - Mips_SRAI_H = 1550, - Mips_SRAI_W = 1551, - Mips_SRARI_B = 1552, - Mips_SRARI_D = 1553, - Mips_SRARI_H = 1554, - Mips_SRARI_W = 1555, - Mips_SRAR_B = 1556, - Mips_SRAR_D = 1557, - Mips_SRAR_H = 1558, - Mips_SRAR_W = 1559, - Mips_SRAV = 1560, - Mips_SRAV_MM = 1561, - Mips_SRA_B = 1562, - Mips_SRA_D = 1563, - Mips_SRA_H = 1564, - Mips_SRA_MM = 1565, - Mips_SRA_W = 1566, - Mips_SRL = 1567, - Mips_SRL16_MM = 1568, - Mips_SRLI_B = 1569, - Mips_SRLI_D = 1570, - Mips_SRLI_H = 1571, - Mips_SRLI_W = 1572, - Mips_SRLRI_B = 1573, - Mips_SRLRI_D = 1574, - Mips_SRLRI_H = 1575, - Mips_SRLRI_W = 1576, - Mips_SRLR_B = 1577, - Mips_SRLR_D = 1578, - Mips_SRLR_H = 1579, - Mips_SRLR_W = 1580, - Mips_SRLV = 1581, - Mips_SRLV_MM = 1582, - Mips_SRL_B = 1583, - Mips_SRL_D = 1584, - Mips_SRL_H = 1585, - Mips_SRL_MM = 1586, - Mips_SRL_W = 1587, - Mips_SSNOP = 1588, - Mips_SSNOP_MM = 1589, - Mips_STORE_ACC128 = 1590, - Mips_STORE_ACC64 = 1591, - Mips_STORE_ACC64DSP = 1592, - Mips_STORE_CCOND_DSP = 1593, - Mips_ST_B = 1594, - Mips_ST_D = 1595, - Mips_ST_H = 1596, - Mips_ST_W = 1597, - Mips_SUB = 1598, - Mips_SUBQH_PH = 1599, - Mips_SUBQH_R_PH = 1600, - Mips_SUBQH_R_W = 1601, - Mips_SUBQH_W = 1602, - Mips_SUBQ_PH = 1603, - Mips_SUBQ_S_PH = 1604, - Mips_SUBQ_S_W = 1605, - Mips_SUBSUS_U_B = 1606, - Mips_SUBSUS_U_D = 1607, - Mips_SUBSUS_U_H = 1608, - Mips_SUBSUS_U_W = 1609, - Mips_SUBSUU_S_B = 1610, - Mips_SUBSUU_S_D = 1611, - Mips_SUBSUU_S_H = 1612, - Mips_SUBSUU_S_W = 1613, - Mips_SUBS_S_B = 1614, - Mips_SUBS_S_D = 1615, - Mips_SUBS_S_H = 1616, - Mips_SUBS_S_W = 1617, - Mips_SUBS_U_B = 1618, - Mips_SUBS_U_D = 1619, - Mips_SUBS_U_H = 1620, - Mips_SUBS_U_W = 1621, - Mips_SUBU16_MM = 1622, - Mips_SUBUH_QB = 1623, - Mips_SUBUH_R_QB = 1624, - Mips_SUBU_PH = 1625, - Mips_SUBU_QB = 1626, - Mips_SUBU_S_PH = 1627, - Mips_SUBU_S_QB = 1628, - Mips_SUBVI_B = 1629, - Mips_SUBVI_D = 1630, - Mips_SUBVI_H = 1631, - Mips_SUBVI_W = 1632, - Mips_SUBV_B = 1633, - Mips_SUBV_D = 1634, - Mips_SUBV_H = 1635, - Mips_SUBV_W = 1636, - Mips_SUB_MM = 1637, - Mips_SUBu = 1638, - Mips_SUBu_MM = 1639, - Mips_SUXC1 = 1640, - Mips_SUXC164 = 1641, - Mips_SUXC1_MM = 1642, - Mips_SW = 1643, - Mips_SW16_MM = 1644, - Mips_SW64 = 1645, - Mips_SWC1 = 1646, - Mips_SWC1_MM = 1647, - Mips_SWC2 = 1648, - Mips_SWC2_R6 = 1649, - Mips_SWC3 = 1650, - Mips_SWL = 1651, - Mips_SWL64 = 1652, - Mips_SWL_MM = 1653, - Mips_SWM16_MM = 1654, - Mips_SWM32_MM = 1655, - Mips_SWM_MM = 1656, - Mips_SWP_MM = 1657, - Mips_SWR = 1658, - Mips_SWR64 = 1659, - Mips_SWR_MM = 1660, - Mips_SWSP_MM = 1661, - Mips_SWXC1 = 1662, - Mips_SWXC1_MM = 1663, - Mips_SW_MM = 1664, - Mips_SYNC = 1665, - Mips_SYNCI = 1666, - Mips_SYNC_MM = 1667, - Mips_SYSCALL = 1668, - Mips_SYSCALL_MM = 1669, - Mips_SZ_B_PSEUDO = 1670, - Mips_SZ_D_PSEUDO = 1671, - Mips_SZ_H_PSEUDO = 1672, - Mips_SZ_V_PSEUDO = 1673, - Mips_SZ_W_PSEUDO = 1674, - Mips_Save16 = 1675, - Mips_SaveX16 = 1676, - Mips_SbRxRyOffMemX16 = 1677, - Mips_SebRx16 = 1678, - Mips_SehRx16 = 1679, - Mips_SelBeqZ = 1680, - Mips_SelBneZ = 1681, - Mips_SelTBteqZCmp = 1682, - Mips_SelTBteqZCmpi = 1683, - Mips_SelTBteqZSlt = 1684, - Mips_SelTBteqZSlti = 1685, - Mips_SelTBteqZSltiu = 1686, - Mips_SelTBteqZSltu = 1687, - Mips_SelTBtneZCmp = 1688, - Mips_SelTBtneZCmpi = 1689, - Mips_SelTBtneZSlt = 1690, - Mips_SelTBtneZSlti = 1691, - Mips_SelTBtneZSltiu = 1692, - Mips_SelTBtneZSltu = 1693, - Mips_ShRxRyOffMemX16 = 1694, - Mips_SllX16 = 1695, - Mips_SllvRxRy16 = 1696, - Mips_SltCCRxRy16 = 1697, - Mips_SltRxRy16 = 1698, - Mips_SltiCCRxImmX16 = 1699, - Mips_SltiRxImm16 = 1700, - Mips_SltiRxImmX16 = 1701, - Mips_SltiuCCRxImmX16 = 1702, - Mips_SltiuRxImm16 = 1703, - Mips_SltiuRxImmX16 = 1704, - Mips_SltuCCRxRy16 = 1705, - Mips_SltuRxRy16 = 1706, - Mips_SltuRxRyRz16 = 1707, - Mips_SraX16 = 1708, - Mips_SravRxRy16 = 1709, - Mips_SrlX16 = 1710, - Mips_SrlvRxRy16 = 1711, - Mips_SubuRxRyRz16 = 1712, - Mips_SwRxRyOffMemX16 = 1713, - Mips_SwRxSpImmX16 = 1714, - Mips_TAILCALL = 1715, - Mips_TAILCALL64_R = 1716, - Mips_TAILCALL_R = 1717, - Mips_TEQ = 1718, - Mips_TEQI = 1719, - Mips_TEQI_MM = 1720, - Mips_TEQ_MM = 1721, - Mips_TGE = 1722, - Mips_TGEI = 1723, - Mips_TGEIU = 1724, - Mips_TGEIU_MM = 1725, - Mips_TGEI_MM = 1726, - Mips_TGEU = 1727, - Mips_TGEU_MM = 1728, - Mips_TGE_MM = 1729, - Mips_TLBP = 1730, - Mips_TLBP_MM = 1731, - Mips_TLBR = 1732, - Mips_TLBR_MM = 1733, - Mips_TLBWI = 1734, - Mips_TLBWI_MM = 1735, - Mips_TLBWR = 1736, - Mips_TLBWR_MM = 1737, - Mips_TLT = 1738, - Mips_TLTI = 1739, - Mips_TLTIU_MM = 1740, - Mips_TLTI_MM = 1741, - Mips_TLTU = 1742, - Mips_TLTU_MM = 1743, - Mips_TLT_MM = 1744, - Mips_TNE = 1745, - Mips_TNEI = 1746, - Mips_TNEI_MM = 1747, - Mips_TNE_MM = 1748, - Mips_TRAP = 1749, - Mips_TRUNC_L_D64 = 1750, - Mips_TRUNC_L_S = 1751, - Mips_TRUNC_W_D32 = 1752, - Mips_TRUNC_W_D64 = 1753, - Mips_TRUNC_W_MM = 1754, - Mips_TRUNC_W_S = 1755, - Mips_TRUNC_W_S_MM = 1756, - Mips_TTLTIU = 1757, - Mips_UDIV = 1758, - Mips_UDIV_MM = 1759, - Mips_V3MULU = 1760, - Mips_VMM0 = 1761, - Mips_VMULU = 1762, - Mips_VSHF_B = 1763, - Mips_VSHF_D = 1764, - Mips_VSHF_H = 1765, - Mips_VSHF_W = 1766, - Mips_WAIT = 1767, - Mips_WAIT_MM = 1768, - Mips_WRDSP = 1769, - Mips_WSBH = 1770, - Mips_WSBH_MM = 1771, - Mips_XOR = 1772, - Mips_XOR16_MM = 1773, - Mips_XOR64 = 1774, - Mips_XORI_B = 1775, - Mips_XOR_MM = 1776, - Mips_XOR_V = 1777, - Mips_XOR_V_D_PSEUDO = 1778, - Mips_XOR_V_H_PSEUDO = 1779, - Mips_XOR_V_W_PSEUDO = 1780, - Mips_XORi = 1781, - Mips_XORi64 = 1782, - Mips_XORi_MM = 1783, - Mips_XorRxRxRy16 = 1784, - Mips_INSTRUCTION_LIST_END = 1785 -}; + Mips_INLINEASM_BR = 2, + Mips_CFI_INSTRUCTION = 3, + Mips_EH_LABEL = 4, + Mips_GC_LABEL = 5, + Mips_ANNOTATION_LABEL = 6, + Mips_KILL = 7, + Mips_EXTRACT_SUBREG = 8, + Mips_INSERT_SUBREG = 9, + Mips_IMPLICIT_DEF = 10, + Mips_SUBREG_TO_REG = 11, + Mips_COPY_TO_REGCLASS = 12, + Mips_DBG_VALUE = 13, + Mips_DBG_VALUE_LIST = 14, + Mips_DBG_INSTR_REF = 15, + Mips_DBG_PHI = 16, + Mips_DBG_LABEL = 17, + Mips_REG_SEQUENCE = 18, + Mips_COPY = 19, + Mips_BUNDLE = 20, + Mips_LIFETIME_START = 21, + Mips_LIFETIME_END = 22, + Mips_PSEUDO_PROBE = 23, + Mips_ARITH_FENCE = 24, + Mips_STACKMAP = 25, + Mips_FENTRY_CALL = 26, + Mips_PATCHPOINT = 27, + Mips_LOAD_STACK_GUARD = 28, + Mips_PREALLOCATED_SETUP = 29, + Mips_PREALLOCATED_ARG = 30, + Mips_STATEPOINT = 31, + Mips_LOCAL_ESCAPE = 32, + Mips_FAULTING_OP = 33, + Mips_PATCHABLE_OP = 34, + Mips_PATCHABLE_FUNCTION_ENTER = 35, + Mips_PATCHABLE_RET = 36, + Mips_PATCHABLE_FUNCTION_EXIT = 37, + Mips_PATCHABLE_TAIL_CALL = 38, + Mips_PATCHABLE_EVENT_CALL = 39, + Mips_PATCHABLE_TYPED_EVENT_CALL = 40, + Mips_ICALL_BRANCH_FUNNEL = 41, + Mips_MEMBARRIER = 42, + Mips_JUMP_TABLE_DEBUG_INFO = 43, + Mips_G_ASSERT_SEXT = 44, + Mips_G_ASSERT_ZEXT = 45, + Mips_G_ASSERT_ALIGN = 46, + Mips_G_ADD = 47, + Mips_G_SUB = 48, + Mips_G_MUL = 49, + Mips_G_SDIV = 50, + Mips_G_UDIV = 51, + Mips_G_SREM = 52, + Mips_G_UREM = 53, + Mips_G_SDIVREM = 54, + Mips_G_UDIVREM = 55, + Mips_G_AND = 56, + Mips_G_OR = 57, + Mips_G_XOR = 58, + Mips_G_IMPLICIT_DEF = 59, + Mips_G_PHI = 60, + Mips_G_FRAME_INDEX = 61, + Mips_G_GLOBAL_VALUE = 62, + Mips_G_CONSTANT_POOL = 63, + Mips_G_EXTRACT = 64, + Mips_G_UNMERGE_VALUES = 65, + Mips_G_INSERT = 66, + Mips_G_MERGE_VALUES = 67, + Mips_G_BUILD_VECTOR = 68, + Mips_G_BUILD_VECTOR_TRUNC = 69, + Mips_G_CONCAT_VECTORS = 70, + Mips_G_PTRTOINT = 71, + Mips_G_INTTOPTR = 72, + Mips_G_BITCAST = 73, + Mips_G_FREEZE = 74, + Mips_G_CONSTANT_FOLD_BARRIER = 75, + Mips_G_INTRINSIC_FPTRUNC_ROUND = 76, + Mips_G_INTRINSIC_TRUNC = 77, + Mips_G_INTRINSIC_ROUND = 78, + Mips_G_INTRINSIC_LRINT = 79, + Mips_G_INTRINSIC_ROUNDEVEN = 80, + Mips_G_READCYCLECOUNTER = 81, + Mips_G_LOAD = 82, + Mips_G_SEXTLOAD = 83, + Mips_G_ZEXTLOAD = 84, + Mips_G_INDEXED_LOAD = 85, + Mips_G_INDEXED_SEXTLOAD = 86, + Mips_G_INDEXED_ZEXTLOAD = 87, + Mips_G_STORE = 88, + Mips_G_INDEXED_STORE = 89, + Mips_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90, + Mips_G_ATOMIC_CMPXCHG = 91, + Mips_G_ATOMICRMW_XCHG = 92, + Mips_G_ATOMICRMW_ADD = 93, + Mips_G_ATOMICRMW_SUB = 94, + Mips_G_ATOMICRMW_AND = 95, + Mips_G_ATOMICRMW_NAND = 96, + Mips_G_ATOMICRMW_OR = 97, + Mips_G_ATOMICRMW_XOR = 98, + Mips_G_ATOMICRMW_MAX = 99, + Mips_G_ATOMICRMW_MIN = 100, + Mips_G_ATOMICRMW_UMAX = 101, + Mips_G_ATOMICRMW_UMIN = 102, + Mips_G_ATOMICRMW_FADD = 103, + Mips_G_ATOMICRMW_FSUB = 104, + Mips_G_ATOMICRMW_FMAX = 105, + Mips_G_ATOMICRMW_FMIN = 106, + Mips_G_ATOMICRMW_UINC_WRAP = 107, + Mips_G_ATOMICRMW_UDEC_WRAP = 108, + Mips_G_FENCE = 109, + Mips_G_PREFETCH = 110, + Mips_G_BRCOND = 111, + Mips_G_BRINDIRECT = 112, + Mips_G_INVOKE_REGION_START = 113, + Mips_G_INTRINSIC = 114, + Mips_G_INTRINSIC_W_SIDE_EFFECTS = 115, + Mips_G_INTRINSIC_CONVERGENT = 116, + Mips_G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117, + Mips_G_ANYEXT = 118, + Mips_G_TRUNC = 119, + Mips_G_CONSTANT = 120, + Mips_G_FCONSTANT = 121, + Mips_G_VASTART = 122, + Mips_G_VAARG = 123, + Mips_G_SEXT = 124, + Mips_G_SEXT_INREG = 125, + Mips_G_ZEXT = 126, + Mips_G_SHL = 127, + Mips_G_LSHR = 128, + Mips_G_ASHR = 129, + Mips_G_FSHL = 130, + Mips_G_FSHR = 131, + Mips_G_ROTR = 132, + Mips_G_ROTL = 133, + Mips_G_ICMP = 134, + Mips_G_FCMP = 135, + Mips_G_SELECT = 136, + Mips_G_UADDO = 137, + Mips_G_UADDE = 138, + Mips_G_USUBO = 139, + Mips_G_USUBE = 140, + Mips_G_SADDO = 141, + Mips_G_SADDE = 142, + Mips_G_SSUBO = 143, + Mips_G_SSUBE = 144, + Mips_G_UMULO = 145, + Mips_G_SMULO = 146, + Mips_G_UMULH = 147, + Mips_G_SMULH = 148, + Mips_G_UADDSAT = 149, + Mips_G_SADDSAT = 150, + Mips_G_USUBSAT = 151, + Mips_G_SSUBSAT = 152, + Mips_G_USHLSAT = 153, + Mips_G_SSHLSAT = 154, + Mips_G_SMULFIX = 155, + Mips_G_UMULFIX = 156, + Mips_G_SMULFIXSAT = 157, + Mips_G_UMULFIXSAT = 158, + Mips_G_SDIVFIX = 159, + Mips_G_UDIVFIX = 160, + Mips_G_SDIVFIXSAT = 161, + Mips_G_UDIVFIXSAT = 162, + Mips_G_FADD = 163, + Mips_G_FSUB = 164, + Mips_G_FMUL = 165, + Mips_G_FMA = 166, + Mips_G_FMAD = 167, + Mips_G_FDIV = 168, + Mips_G_FREM = 169, + Mips_G_FPOW = 170, + Mips_G_FPOWI = 171, + Mips_G_FEXP = 172, + Mips_G_FEXP2 = 173, + Mips_G_FEXP10 = 174, + Mips_G_FLOG = 175, + Mips_G_FLOG2 = 176, + Mips_G_FLOG10 = 177, + Mips_G_FLDEXP = 178, + Mips_G_FFREXP = 179, + Mips_G_FNEG = 180, + Mips_G_FPEXT = 181, + Mips_G_FPTRUNC = 182, + Mips_G_FPTOSI = 183, + Mips_G_FPTOUI = 184, + Mips_G_SITOFP = 185, + Mips_G_UITOFP = 186, + Mips_G_FABS = 187, + Mips_G_FCOPYSIGN = 188, + Mips_G_IS_FPCLASS = 189, + Mips_G_FCANONICALIZE = 190, + Mips_G_FMINNUM = 191, + Mips_G_FMAXNUM = 192, + Mips_G_FMINNUM_IEEE = 193, + Mips_G_FMAXNUM_IEEE = 194, + Mips_G_FMINIMUM = 195, + Mips_G_FMAXIMUM = 196, + Mips_G_GET_FPENV = 197, + Mips_G_SET_FPENV = 198, + Mips_G_RESET_FPENV = 199, + Mips_G_GET_FPMODE = 200, + Mips_G_SET_FPMODE = 201, + Mips_G_RESET_FPMODE = 202, + Mips_G_PTR_ADD = 203, + Mips_G_PTRMASK = 204, + Mips_G_SMIN = 205, + Mips_G_SMAX = 206, + Mips_G_UMIN = 207, + Mips_G_UMAX = 208, + Mips_G_ABS = 209, + Mips_G_LROUND = 210, + Mips_G_LLROUND = 211, + Mips_G_BR = 212, + Mips_G_BRJT = 213, + Mips_G_INSERT_VECTOR_ELT = 214, + Mips_G_EXTRACT_VECTOR_ELT = 215, + Mips_G_SHUFFLE_VECTOR = 216, + Mips_G_CTTZ = 217, + Mips_G_CTTZ_ZERO_UNDEF = 218, + Mips_G_CTLZ = 219, + Mips_G_CTLZ_ZERO_UNDEF = 220, + Mips_G_CTPOP = 221, + Mips_G_BSWAP = 222, + Mips_G_BITREVERSE = 223, + Mips_G_FCEIL = 224, + Mips_G_FCOS = 225, + Mips_G_FSIN = 226, + Mips_G_FSQRT = 227, + Mips_G_FFLOOR = 228, + Mips_G_FRINT = 229, + Mips_G_FNEARBYINT = 230, + Mips_G_ADDRSPACE_CAST = 231, + Mips_G_BLOCK_ADDR = 232, + Mips_G_JUMP_TABLE = 233, + Mips_G_DYN_STACKALLOC = 234, + Mips_G_STACKSAVE = 235, + Mips_G_STACKRESTORE = 236, + Mips_G_STRICT_FADD = 237, + Mips_G_STRICT_FSUB = 238, + Mips_G_STRICT_FMUL = 239, + Mips_G_STRICT_FDIV = 240, + Mips_G_STRICT_FREM = 241, + Mips_G_STRICT_FMA = 242, + Mips_G_STRICT_FSQRT = 243, + Mips_G_STRICT_FLDEXP = 244, + Mips_G_READ_REGISTER = 245, + Mips_G_WRITE_REGISTER = 246, + Mips_G_MEMCPY = 247, + Mips_G_MEMCPY_INLINE = 248, + Mips_G_MEMMOVE = 249, + Mips_G_MEMSET = 250, + Mips_G_BZERO = 251, + Mips_G_VECREDUCE_SEQ_FADD = 252, + Mips_G_VECREDUCE_SEQ_FMUL = 253, + Mips_G_VECREDUCE_FADD = 254, + Mips_G_VECREDUCE_FMUL = 255, + Mips_G_VECREDUCE_FMAX = 256, + Mips_G_VECREDUCE_FMIN = 257, + Mips_G_VECREDUCE_FMAXIMUM = 258, + Mips_G_VECREDUCE_FMINIMUM = 259, + Mips_G_VECREDUCE_ADD = 260, + Mips_G_VECREDUCE_MUL = 261, + Mips_G_VECREDUCE_AND = 262, + Mips_G_VECREDUCE_OR = 263, + Mips_G_VECREDUCE_XOR = 264, + Mips_G_VECREDUCE_SMAX = 265, + Mips_G_VECREDUCE_SMIN = 266, + Mips_G_VECREDUCE_UMAX = 267, + Mips_G_VECREDUCE_UMIN = 268, + Mips_G_SBFX = 269, + Mips_G_UBFX = 270, + Mips_ABSMacro = 271, + Mips_ADJCALLSTACKDOWN = 272, + Mips_ADJCALLSTACKDOWN_NM = 273, + Mips_ADJCALLSTACKUP = 274, + Mips_ADJCALLSTACKUP_NM = 275, + Mips_ALIGN_NM = 276, + Mips_AND_V_D_PSEUDO = 277, + Mips_AND_V_H_PSEUDO = 278, + Mips_AND_V_W_PSEUDO = 279, + Mips_ATOMIC_CMP_SWAP_I16 = 280, + Mips_ATOMIC_CMP_SWAP_I16_POSTRA = 281, + Mips_ATOMIC_CMP_SWAP_I32 = 282, + Mips_ATOMIC_CMP_SWAP_I32_POSTRA = 283, + Mips_ATOMIC_CMP_SWAP_I64 = 284, + Mips_ATOMIC_CMP_SWAP_I64_POSTRA = 285, + Mips_ATOMIC_CMP_SWAP_I8 = 286, + Mips_ATOMIC_CMP_SWAP_I8_POSTRA = 287, + Mips_ATOMIC_LOAD_ADD_I16 = 288, + Mips_ATOMIC_LOAD_ADD_I16_POSTRA = 289, + Mips_ATOMIC_LOAD_ADD_I32 = 290, + Mips_ATOMIC_LOAD_ADD_I32_POSTRA = 291, + Mips_ATOMIC_LOAD_ADD_I64 = 292, + Mips_ATOMIC_LOAD_ADD_I64_POSTRA = 293, + Mips_ATOMIC_LOAD_ADD_I8 = 294, + Mips_ATOMIC_LOAD_ADD_I8_POSTRA = 295, + Mips_ATOMIC_LOAD_AND_I16 = 296, + Mips_ATOMIC_LOAD_AND_I16_POSTRA = 297, + Mips_ATOMIC_LOAD_AND_I32 = 298, + Mips_ATOMIC_LOAD_AND_I32_POSTRA = 299, + Mips_ATOMIC_LOAD_AND_I64 = 300, + Mips_ATOMIC_LOAD_AND_I64_POSTRA = 301, + Mips_ATOMIC_LOAD_AND_I8 = 302, + Mips_ATOMIC_LOAD_AND_I8_POSTRA = 303, + Mips_ATOMIC_LOAD_MAX_I16 = 304, + Mips_ATOMIC_LOAD_MAX_I16_POSTRA = 305, + Mips_ATOMIC_LOAD_MAX_I32 = 306, + Mips_ATOMIC_LOAD_MAX_I32_POSTRA = 307, + Mips_ATOMIC_LOAD_MAX_I64 = 308, + Mips_ATOMIC_LOAD_MAX_I64_POSTRA = 309, + Mips_ATOMIC_LOAD_MAX_I8 = 310, + Mips_ATOMIC_LOAD_MAX_I8_POSTRA = 311, + Mips_ATOMIC_LOAD_MIN_I16 = 312, + Mips_ATOMIC_LOAD_MIN_I16_POSTRA = 313, + Mips_ATOMIC_LOAD_MIN_I32 = 314, + Mips_ATOMIC_LOAD_MIN_I32_POSTRA = 315, + Mips_ATOMIC_LOAD_MIN_I64 = 316, + Mips_ATOMIC_LOAD_MIN_I64_POSTRA = 317, + Mips_ATOMIC_LOAD_MIN_I8 = 318, + Mips_ATOMIC_LOAD_MIN_I8_POSTRA = 319, + Mips_ATOMIC_LOAD_NAND_I16 = 320, + Mips_ATOMIC_LOAD_NAND_I16_POSTRA = 321, + Mips_ATOMIC_LOAD_NAND_I32 = 322, + Mips_ATOMIC_LOAD_NAND_I32_POSTRA = 323, + Mips_ATOMIC_LOAD_NAND_I64 = 324, + Mips_ATOMIC_LOAD_NAND_I64_POSTRA = 325, + Mips_ATOMIC_LOAD_NAND_I8 = 326, + Mips_ATOMIC_LOAD_NAND_I8_POSTRA = 327, + Mips_ATOMIC_LOAD_OR_I16 = 328, + Mips_ATOMIC_LOAD_OR_I16_POSTRA = 329, + Mips_ATOMIC_LOAD_OR_I32 = 330, + Mips_ATOMIC_LOAD_OR_I32_POSTRA = 331, + Mips_ATOMIC_LOAD_OR_I64 = 332, + Mips_ATOMIC_LOAD_OR_I64_POSTRA = 333, + Mips_ATOMIC_LOAD_OR_I8 = 334, + Mips_ATOMIC_LOAD_OR_I8_POSTRA = 335, + Mips_ATOMIC_LOAD_SUB_I16 = 336, + Mips_ATOMIC_LOAD_SUB_I16_POSTRA = 337, + Mips_ATOMIC_LOAD_SUB_I32 = 338, + Mips_ATOMIC_LOAD_SUB_I32_POSTRA = 339, + Mips_ATOMIC_LOAD_SUB_I64 = 340, + Mips_ATOMIC_LOAD_SUB_I64_POSTRA = 341, + Mips_ATOMIC_LOAD_SUB_I8 = 342, + Mips_ATOMIC_LOAD_SUB_I8_POSTRA = 343, + Mips_ATOMIC_LOAD_UMAX_I16 = 344, + Mips_ATOMIC_LOAD_UMAX_I16_POSTRA = 345, + Mips_ATOMIC_LOAD_UMAX_I32 = 346, + Mips_ATOMIC_LOAD_UMAX_I32_POSTRA = 347, + Mips_ATOMIC_LOAD_UMAX_I64 = 348, + Mips_ATOMIC_LOAD_UMAX_I64_POSTRA = 349, + Mips_ATOMIC_LOAD_UMAX_I8 = 350, + Mips_ATOMIC_LOAD_UMAX_I8_POSTRA = 351, + Mips_ATOMIC_LOAD_UMIN_I16 = 352, + Mips_ATOMIC_LOAD_UMIN_I16_POSTRA = 353, + Mips_ATOMIC_LOAD_UMIN_I32 = 354, + Mips_ATOMIC_LOAD_UMIN_I32_POSTRA = 355, + Mips_ATOMIC_LOAD_UMIN_I64 = 356, + Mips_ATOMIC_LOAD_UMIN_I64_POSTRA = 357, + Mips_ATOMIC_LOAD_UMIN_I8 = 358, + Mips_ATOMIC_LOAD_UMIN_I8_POSTRA = 359, + Mips_ATOMIC_LOAD_XOR_I16 = 360, + Mips_ATOMIC_LOAD_XOR_I16_POSTRA = 361, + Mips_ATOMIC_LOAD_XOR_I32 = 362, + Mips_ATOMIC_LOAD_XOR_I32_POSTRA = 363, + Mips_ATOMIC_LOAD_XOR_I64 = 364, + Mips_ATOMIC_LOAD_XOR_I64_POSTRA = 365, + Mips_ATOMIC_LOAD_XOR_I8 = 366, + Mips_ATOMIC_LOAD_XOR_I8_POSTRA = 367, + Mips_ATOMIC_SWAP_I16 = 368, + Mips_ATOMIC_SWAP_I16_POSTRA = 369, + Mips_ATOMIC_SWAP_I32 = 370, + Mips_ATOMIC_SWAP_I32_POSTRA = 371, + Mips_ATOMIC_SWAP_I64 = 372, + Mips_ATOMIC_SWAP_I64_POSTRA = 373, + Mips_ATOMIC_SWAP_I8 = 374, + Mips_ATOMIC_SWAP_I8_POSTRA = 375, + Mips_B = 376, + Mips_BAL_BR = 377, + Mips_BAL_BR_MM = 378, + Mips_BEQLImmMacro = 379, + Mips_BGE = 380, + Mips_BGEImmMacro = 381, + Mips_BGEL = 382, + Mips_BGELImmMacro = 383, + Mips_BGEU = 384, + Mips_BGEUImmMacro = 385, + Mips_BGEUL = 386, + Mips_BGEULImmMacro = 387, + Mips_BGT = 388, + Mips_BGTImmMacro = 389, + Mips_BGTL = 390, + Mips_BGTLImmMacro = 391, + Mips_BGTU = 392, + Mips_BGTUImmMacro = 393, + Mips_BGTUL = 394, + Mips_BGTULImmMacro = 395, + Mips_BLE = 396, + Mips_BLEImmMacro = 397, + Mips_BLEL = 398, + Mips_BLELImmMacro = 399, + Mips_BLEU = 400, + Mips_BLEUImmMacro = 401, + Mips_BLEUL = 402, + Mips_BLEULImmMacro = 403, + Mips_BLT = 404, + Mips_BLTImmMacro = 405, + Mips_BLTL = 406, + Mips_BLTLImmMacro = 407, + Mips_BLTU = 408, + Mips_BLTUImmMacro = 409, + Mips_BLTUL = 410, + Mips_BLTULImmMacro = 411, + Mips_BNELImmMacro = 412, + Mips_BPOSGE32_PSEUDO = 413, + Mips_BSEL_D_PSEUDO = 414, + Mips_BSEL_FD_PSEUDO = 415, + Mips_BSEL_FW_PSEUDO = 416, + Mips_BSEL_H_PSEUDO = 417, + Mips_BSEL_W_PSEUDO = 418, + Mips_B_MM = 419, + Mips_B_MMR6_Pseudo = 420, + Mips_B_MM_Pseudo = 421, + Mips_BeqImm = 422, + Mips_BneImm = 423, + Mips_BteqzT8CmpX16 = 424, + Mips_BteqzT8CmpiX16 = 425, + Mips_BteqzT8SltX16 = 426, + Mips_BteqzT8SltiX16 = 427, + Mips_BteqzT8SltiuX16 = 428, + Mips_BteqzT8SltuX16 = 429, + Mips_BtnezT8CmpX16 = 430, + Mips_BtnezT8CmpiX16 = 431, + Mips_BtnezT8SltX16 = 432, + Mips_BtnezT8SltiX16 = 433, + Mips_BtnezT8SltiuX16 = 434, + Mips_BtnezT8SltuX16 = 435, + Mips_BuildPairF64 = 436, + Mips_BuildPairF64_64 = 437, + Mips_CFTC1 = 438, + Mips_CONSTPOOL_ENTRY = 439, + Mips_COPY_FD_PSEUDO = 440, + Mips_COPY_FW_PSEUDO = 441, + Mips_CTTC1 = 442, + Mips_Constant32 = 443, + Mips_DMULImmMacro = 444, + Mips_DMULMacro = 445, + Mips_DMULOMacro = 446, + Mips_DMULOUMacro = 447, + Mips_DROL = 448, + Mips_DROLImm = 449, + Mips_DROR = 450, + Mips_DRORImm = 451, + Mips_DSDivIMacro = 452, + Mips_DSDivMacro = 453, + Mips_DSRemIMacro = 454, + Mips_DSRemMacro = 455, + Mips_DUDivIMacro = 456, + Mips_DUDivMacro = 457, + Mips_DURemIMacro = 458, + Mips_DURemMacro = 459, + Mips_ERet = 460, + Mips_ExtractElementF64 = 461, + Mips_ExtractElementF64_64 = 462, + Mips_FABS_D = 463, + Mips_FABS_W = 464, + Mips_FEXP2_D_1_PSEUDO = 465, + Mips_FEXP2_W_1_PSEUDO = 466, + Mips_FILL_FD_PSEUDO = 467, + Mips_FILL_FW_PSEUDO = 468, + Mips_GotPrologue16 = 469, + Mips_INSERT_B_VIDX64_PSEUDO = 470, + Mips_INSERT_B_VIDX_PSEUDO = 471, + Mips_INSERT_D_VIDX64_PSEUDO = 472, + Mips_INSERT_D_VIDX_PSEUDO = 473, + Mips_INSERT_FD_PSEUDO = 474, + Mips_INSERT_FD_VIDX64_PSEUDO = 475, + Mips_INSERT_FD_VIDX_PSEUDO = 476, + Mips_INSERT_FW_PSEUDO = 477, + Mips_INSERT_FW_VIDX64_PSEUDO = 478, + Mips_INSERT_FW_VIDX_PSEUDO = 479, + Mips_INSERT_H_VIDX64_PSEUDO = 480, + Mips_INSERT_H_VIDX_PSEUDO = 481, + Mips_INSERT_W_VIDX64_PSEUDO = 482, + Mips_INSERT_W_VIDX_PSEUDO = 483, + Mips_JALR64Pseudo = 484, + Mips_JALRCPseudo = 485, + Mips_JALRHB64Pseudo = 486, + Mips_JALRHBPseudo = 487, + Mips_JALRPseudo = 488, + Mips_JAL_MMR6 = 489, + Mips_JalOneReg = 490, + Mips_JalTwoReg = 491, + Mips_LDMacro = 492, + Mips_LDR_D = 493, + Mips_LDR_W = 494, + Mips_LD_F16 = 495, + Mips_LOAD_ACC128 = 496, + Mips_LOAD_ACC64 = 497, + Mips_LOAD_ACC64DSP = 498, + Mips_LOAD_CCOND_DSP = 499, + Mips_LONG_BRANCH_ADDiu = 500, + Mips_LONG_BRANCH_ADDiu2Op = 501, + Mips_LONG_BRANCH_DADDiu = 502, + Mips_LONG_BRANCH_DADDiu2Op = 503, + Mips_LONG_BRANCH_LUi = 504, + Mips_LONG_BRANCH_LUi2Op = 505, + Mips_LONG_BRANCH_LUi2Op_64 = 506, + Mips_LWM_MM = 507, + Mips_LoadAddrImm32 = 508, + Mips_LoadAddrImm64 = 509, + Mips_LoadAddrReg32 = 510, + Mips_LoadAddrReg64 = 511, + Mips_LoadImm32 = 512, + Mips_LoadImm64 = 513, + Mips_LoadImmDoubleFGR = 514, + Mips_LoadImmDoubleFGR_32 = 515, + Mips_LoadImmDoubleGPR = 516, + Mips_LoadImmSingleFGR = 517, + Mips_LoadImmSingleGPR = 518, + Mips_LoadJumpTableOffset = 519, + Mips_LwConstant32 = 520, + Mips_MFTACX = 521, + Mips_MFTACX_NM = 522, + Mips_MFTC0 = 523, + Mips_MFTC0_NM = 524, + Mips_MFTC1 = 525, + Mips_MFTDSP = 526, + Mips_MFTDSP_NM = 527, + Mips_MFTGPR = 528, + Mips_MFTGPR_NM = 529, + Mips_MFTHC1 = 530, + Mips_MFTHI = 531, + Mips_MFTHI_NM = 532, + Mips_MFTLO = 533, + Mips_MFTLO_NM = 534, + Mips_MIPSeh_return32 = 535, + Mips_MIPSeh_return64 = 536, + Mips_MSA_FP_EXTEND_D_PSEUDO = 537, + Mips_MSA_FP_EXTEND_W_PSEUDO = 538, + Mips_MSA_FP_ROUND_D_PSEUDO = 539, + Mips_MSA_FP_ROUND_W_PSEUDO = 540, + Mips_MTTACX = 541, + Mips_MTTACX_NM = 542, + Mips_MTTC0 = 543, + Mips_MTTC0_NM = 544, + Mips_MTTC1 = 545, + Mips_MTTDSP = 546, + Mips_MTTDSP_NM = 547, + Mips_MTTGPR = 548, + Mips_MTTGPR_NM = 549, + Mips_MTTHC1 = 550, + Mips_MTTHI = 551, + Mips_MTTHI_NM = 552, + Mips_MTTLO = 553, + Mips_MTTLO_NM = 554, + Mips_MULImmMacro = 555, + Mips_MULOMacro = 556, + Mips_MULOUMacro = 557, + Mips_MUSTTAILCALLREG_NM = 558, + Mips_MUSTTAILCALL_NM = 559, + Mips_MultRxRy16 = 560, + Mips_MultRxRyRz16 = 561, + Mips_MultuRxRy16 = 562, + Mips_MultuRxRyRz16 = 563, + Mips_NOP = 564, + Mips_NORImm = 565, + Mips_NORImm64 = 566, + Mips_NOR_V_D_PSEUDO = 567, + Mips_NOR_V_H_PSEUDO = 568, + Mips_NOR_V_W_PSEUDO = 569, + Mips_OR_V_D_PSEUDO = 570, + Mips_OR_V_H_PSEUDO = 571, + Mips_OR_V_W_PSEUDO = 572, + Mips_PseudoADDIU_NM = 573, + Mips_PseudoANDI_NM = 574, + Mips_PseudoCMPU_EQ_QB = 575, + Mips_PseudoCMPU_LE_QB = 576, + Mips_PseudoCMPU_LT_QB = 577, + Mips_PseudoCMP_EQ_PH = 578, + Mips_PseudoCMP_LE_PH = 579, + Mips_PseudoCMP_LT_PH = 580, + Mips_PseudoCVT_D32_W = 581, + Mips_PseudoCVT_D64_L = 582, + Mips_PseudoCVT_D64_W = 583, + Mips_PseudoCVT_S_L = 584, + Mips_PseudoCVT_S_W = 585, + Mips_PseudoDMULT = 586, + Mips_PseudoDMULTu = 587, + Mips_PseudoDSDIV = 588, + Mips_PseudoDUDIV = 589, + Mips_PseudoD_SELECT_I = 590, + Mips_PseudoD_SELECT_I64 = 591, + Mips_PseudoIndirectBranch = 592, + Mips_PseudoIndirectBranch64 = 593, + Mips_PseudoIndirectBranch64R6 = 594, + Mips_PseudoIndirectBranchNM = 595, + Mips_PseudoIndirectBranchR6 = 596, + Mips_PseudoIndirectBranch_MM = 597, + Mips_PseudoIndirectBranch_MMR6 = 598, + Mips_PseudoIndirectHazardBranch = 599, + Mips_PseudoIndirectHazardBranch64 = 600, + Mips_PseudoIndrectHazardBranch64R6 = 601, + Mips_PseudoIndrectHazardBranchR6 = 602, + Mips_PseudoLA_NM = 603, + Mips_PseudoLI_NM = 604, + Mips_PseudoMADD = 605, + Mips_PseudoMADDU = 606, + Mips_PseudoMADDU_MM = 607, + Mips_PseudoMADD_MM = 608, + Mips_PseudoMFHI = 609, + Mips_PseudoMFHI64 = 610, + Mips_PseudoMFHI_MM = 611, + Mips_PseudoMFLO = 612, + Mips_PseudoMFLO64 = 613, + Mips_PseudoMFLO_MM = 614, + Mips_PseudoMSUB = 615, + Mips_PseudoMSUBU = 616, + Mips_PseudoMSUBU_MM = 617, + Mips_PseudoMSUB_MM = 618, + Mips_PseudoMTLOHI = 619, + Mips_PseudoMTLOHI64 = 620, + Mips_PseudoMTLOHI_DSP = 621, + Mips_PseudoMTLOHI_MM = 622, + Mips_PseudoMULT = 623, + Mips_PseudoMULT_MM = 624, + Mips_PseudoMULTu = 625, + Mips_PseudoMULTu_MM = 626, + Mips_PseudoPICK_PH = 627, + Mips_PseudoPICK_QB = 628, + Mips_PseudoReturn = 629, + Mips_PseudoReturn64 = 630, + Mips_PseudoReturnNM = 631, + Mips_PseudoSDIV = 632, + Mips_PseudoSELECTFP_F_D32 = 633, + Mips_PseudoSELECTFP_F_D64 = 634, + Mips_PseudoSELECTFP_F_I = 635, + Mips_PseudoSELECTFP_F_I64 = 636, + Mips_PseudoSELECTFP_F_S = 637, + Mips_PseudoSELECTFP_T_D32 = 638, + Mips_PseudoSELECTFP_T_D64 = 639, + Mips_PseudoSELECTFP_T_I = 640, + Mips_PseudoSELECTFP_T_I64 = 641, + Mips_PseudoSELECTFP_T_S = 642, + Mips_PseudoSELECT_D32 = 643, + Mips_PseudoSELECT_D64 = 644, + Mips_PseudoSELECT_I = 645, + Mips_PseudoSELECT_I64 = 646, + Mips_PseudoSELECT_S = 647, + Mips_PseudoSUBU_NM = 648, + Mips_PseudoTRUNC_W_D = 649, + Mips_PseudoTRUNC_W_D32 = 650, + Mips_PseudoTRUNC_W_S = 651, + Mips_PseudoUDIV = 652, + Mips_ROL = 653, + Mips_ROLImm = 654, + Mips_ROR = 655, + Mips_RORImm = 656, + Mips_RetRA = 657, + Mips_RetRA16 = 658, + Mips_SDC1_M1 = 659, + Mips_SDIV_MM_Pseudo = 660, + Mips_SDMacro = 661, + Mips_SDivIMacro = 662, + Mips_SDivMacro = 663, + Mips_SEQIMacro = 664, + Mips_SEQMacro = 665, + Mips_SGE = 666, + Mips_SGEImm = 667, + Mips_SGEImm64 = 668, + Mips_SGEU = 669, + Mips_SGEUImm = 670, + Mips_SGEUImm64 = 671, + Mips_SGTImm = 672, + Mips_SGTImm64 = 673, + Mips_SGTUImm = 674, + Mips_SGTUImm64 = 675, + Mips_SLE = 676, + Mips_SLEImm = 677, + Mips_SLEImm64 = 678, + Mips_SLEU = 679, + Mips_SLEUImm = 680, + Mips_SLEUImm64 = 681, + Mips_SLTImm64 = 682, + Mips_SLTUImm64 = 683, + Mips_SNEIMacro = 684, + Mips_SNEMacro = 685, + Mips_SNZ_B_PSEUDO = 686, + Mips_SNZ_D_PSEUDO = 687, + Mips_SNZ_H_PSEUDO = 688, + Mips_SNZ_V_PSEUDO = 689, + Mips_SNZ_W_PSEUDO = 690, + Mips_SRemIMacro = 691, + Mips_SRemMacro = 692, + Mips_STORE_ACC128 = 693, + Mips_STORE_ACC64 = 694, + Mips_STORE_ACC64DSP = 695, + Mips_STORE_CCOND_DSP = 696, + Mips_STR_D = 697, + Mips_STR_W = 698, + Mips_ST_F16 = 699, + Mips_SWM_MM = 700, + Mips_SZ_B_PSEUDO = 701, + Mips_SZ_D_PSEUDO = 702, + Mips_SZ_H_PSEUDO = 703, + Mips_SZ_V_PSEUDO = 704, + Mips_SZ_W_PSEUDO = 705, + Mips_SaaAddr = 706, + Mips_SaadAddr = 707, + Mips_SelBeqZ = 708, + Mips_SelBneZ = 709, + Mips_SelTBteqZCmp = 710, + Mips_SelTBteqZCmpi = 711, + Mips_SelTBteqZSlt = 712, + Mips_SelTBteqZSlti = 713, + Mips_SelTBteqZSltiu = 714, + Mips_SelTBteqZSltu = 715, + Mips_SelTBtneZCmp = 716, + Mips_SelTBtneZCmpi = 717, + Mips_SelTBtneZSlt = 718, + Mips_SelTBtneZSlti = 719, + Mips_SelTBtneZSltiu = 720, + Mips_SelTBtneZSltu = 721, + Mips_SltCCRxRy16 = 722, + Mips_SltiCCRxImmX16 = 723, + Mips_SltiuCCRxImmX16 = 724, + Mips_SltuCCRxRy16 = 725, + Mips_SltuRxRyRz16 = 726, + Mips_TAILCALL = 727, + Mips_TAILCALL64R6REG = 728, + Mips_TAILCALLHB64R6REG = 729, + Mips_TAILCALLHBR6REG = 730, + Mips_TAILCALLR6REG = 731, + Mips_TAILCALLREG = 732, + Mips_TAILCALLREG64 = 733, + Mips_TAILCALLREGHB = 734, + Mips_TAILCALLREGHB64 = 735, + Mips_TAILCALLREG_MM = 736, + Mips_TAILCALLREG_MMR6 = 737, + Mips_TAILCALLREG_NM = 738, + Mips_TAILCALL_MM = 739, + Mips_TAILCALL_MMR6 = 740, + Mips_TAILCALL_NM = 741, + Mips_TRAP = 742, + Mips_TRAP_MM = 743, + Mips_UDIV_MM_Pseudo = 744, + Mips_UDivIMacro = 745, + Mips_UDivMacro = 746, + Mips_URemIMacro = 747, + Mips_URemMacro = 748, + Mips_Ulh = 749, + Mips_Ulhu = 750, + Mips_Ulw = 751, + Mips_Ush = 752, + Mips_Usw = 753, + Mips_XOR_V_D_PSEUDO = 754, + Mips_XOR_V_H_PSEUDO = 755, + Mips_XOR_V_W_PSEUDO = 756, + Mips_ABSQ_S_PH = 757, + Mips_ABSQ_S_PH_MM = 758, + Mips_ABSQ_S_QB = 759, + Mips_ABSQ_S_QB_MMR2 = 760, + Mips_ABSQ_S_W = 761, + Mips_ABSQ_S_W_MM = 762, + Mips_ADD = 763, + Mips_ADDIU48_NM = 764, + Mips_ADDIUGP48_NM = 765, + Mips_ADDIUGPB_NM = 766, + Mips_ADDIUGPW_NM = 767, + Mips_ADDIUNEG_NM = 768, + Mips_ADDIUPC = 769, + Mips_ADDIUPC_MM = 770, + Mips_ADDIUPC_MMR6 = 771, + Mips_ADDIUR1SP_MM = 772, + Mips_ADDIUR1SP_NM = 773, + Mips_ADDIUR2_MM = 774, + Mips_ADDIUR2_NM = 775, + Mips_ADDIURS5_NM = 776, + Mips_ADDIUS5_MM = 777, + Mips_ADDIUSP_MM = 778, + Mips_ADDIU_MMR6 = 779, + Mips_ADDIU_NM = 780, + Mips_ADDQH_PH = 781, + Mips_ADDQH_PH_MMR2 = 782, + Mips_ADDQH_R_PH = 783, + Mips_ADDQH_R_PH_MMR2 = 784, + Mips_ADDQH_R_W = 785, + Mips_ADDQH_R_W_MMR2 = 786, + Mips_ADDQH_W = 787, + Mips_ADDQH_W_MMR2 = 788, + Mips_ADDQ_PH = 789, + Mips_ADDQ_PH_MM = 790, + Mips_ADDQ_S_PH = 791, + Mips_ADDQ_S_PH_MM = 792, + Mips_ADDQ_S_W = 793, + Mips_ADDQ_S_W_MM = 794, + Mips_ADDR_PS64 = 795, + Mips_ADDSC = 796, + Mips_ADDSC_MM = 797, + Mips_ADDS_A_B = 798, + Mips_ADDS_A_D = 799, + Mips_ADDS_A_H = 800, + Mips_ADDS_A_W = 801, + Mips_ADDS_S_B = 802, + Mips_ADDS_S_D = 803, + Mips_ADDS_S_H = 804, + Mips_ADDS_S_W = 805, + Mips_ADDS_U_B = 806, + Mips_ADDS_U_D = 807, + Mips_ADDS_U_H = 808, + Mips_ADDS_U_W = 809, + Mips_ADDU16_MM = 810, + Mips_ADDU16_MMR6 = 811, + Mips_ADDUH_QB = 812, + Mips_ADDUH_QB_MMR2 = 813, + Mips_ADDUH_R_QB = 814, + Mips_ADDUH_R_QB_MMR2 = 815, + Mips_ADDU_MMR6 = 816, + Mips_ADDU_PH = 817, + Mips_ADDU_PH_MMR2 = 818, + Mips_ADDU_QB = 819, + Mips_ADDU_QB_MM = 820, + Mips_ADDU_S_PH = 821, + Mips_ADDU_S_PH_MMR2 = 822, + Mips_ADDU_S_QB = 823, + Mips_ADDU_S_QB_MM = 824, + Mips_ADDVI_B = 825, + Mips_ADDVI_D = 826, + Mips_ADDVI_H = 827, + Mips_ADDVI_W = 828, + Mips_ADDV_B = 829, + Mips_ADDV_D = 830, + Mips_ADDV_H = 831, + Mips_ADDV_W = 832, + Mips_ADDWC = 833, + Mips_ADDWC_MM = 834, + Mips_ADD_A_B = 835, + Mips_ADD_A_D = 836, + Mips_ADD_A_H = 837, + Mips_ADD_A_W = 838, + Mips_ADD_MM = 839, + Mips_ADD_MMR6 = 840, + Mips_ADD_NM = 841, + Mips_ADDi = 842, + Mips_ADDi_MM = 843, + Mips_ADDiu = 844, + Mips_ADDiu_MM = 845, + Mips_ADDu = 846, + Mips_ADDu16_NM = 847, + Mips_ADDu4x4_NM = 848, + Mips_ADDu_MM = 849, + Mips_ADDu_NM = 850, + Mips_ALIGN = 851, + Mips_ALIGN_MMR6 = 852, + Mips_ALUIPC = 853, + Mips_ALUIPC_MMR6 = 854, + Mips_ALUIPC_NM = 855, + Mips_AND = 856, + Mips_AND16_MM = 857, + Mips_AND16_MMR6 = 858, + Mips_AND16_NM = 859, + Mips_AND64 = 860, + Mips_ANDI16_MM = 861, + Mips_ANDI16_MMR6 = 862, + Mips_ANDI16_NM = 863, + Mips_ANDI_B = 864, + Mips_ANDI_MMR6 = 865, + Mips_ANDI_NM = 866, + Mips_AND_MM = 867, + Mips_AND_MMR6 = 868, + Mips_AND_NM = 869, + Mips_AND_V = 870, + Mips_ANDi = 871, + Mips_ANDi64 = 872, + Mips_ANDi_MM = 873, + Mips_APPEND = 874, + Mips_APPEND_MMR2 = 875, + Mips_ASUB_S_B = 876, + Mips_ASUB_S_D = 877, + Mips_ASUB_S_H = 878, + Mips_ASUB_S_W = 879, + Mips_ASUB_U_B = 880, + Mips_ASUB_U_D = 881, + Mips_ASUB_U_H = 882, + Mips_ASUB_U_W = 883, + Mips_AUI = 884, + Mips_AUIPC = 885, + Mips_AUIPC_MMR6 = 886, + Mips_AUI_MMR6 = 887, + Mips_AVER_S_B = 888, + Mips_AVER_S_D = 889, + Mips_AVER_S_H = 890, + Mips_AVER_S_W = 891, + Mips_AVER_U_B = 892, + Mips_AVER_U_D = 893, + Mips_AVER_U_H = 894, + Mips_AVER_U_W = 895, + Mips_AVE_S_B = 896, + Mips_AVE_S_D = 897, + Mips_AVE_S_H = 898, + Mips_AVE_S_W = 899, + Mips_AVE_U_B = 900, + Mips_AVE_U_D = 901, + Mips_AVE_U_H = 902, + Mips_AVE_U_W = 903, + Mips_AddiuRxImmX16 = 904, + Mips_AddiuRxPcImmX16 = 905, + Mips_AddiuRxRxImm16 = 906, + Mips_AddiuRxRxImmX16 = 907, + Mips_AddiuRxRyOffMemX16 = 908, + Mips_AddiuSpImm16 = 909, + Mips_AddiuSpImmX16 = 910, + Mips_AdduRxRyRz16 = 911, + Mips_AndRxRxRy16 = 912, + Mips_B16_MM = 913, + Mips_BADDu = 914, + Mips_BAL = 915, + Mips_BALC = 916, + Mips_BALC16_NM = 917, + Mips_BALC_MMR6 = 918, + Mips_BALC_NM = 919, + Mips_BALIGN = 920, + Mips_BALIGN_MMR2 = 921, + Mips_BALRSC_NM = 922, + Mips_BBEQZC_NM = 923, + Mips_BBIT0 = 924, + Mips_BBIT032 = 925, + Mips_BBIT1 = 926, + Mips_BBIT132 = 927, + Mips_BBNEZC_NM = 928, + Mips_BC = 929, + Mips_BC16_MMR6 = 930, + Mips_BC16_NM = 931, + Mips_BC1EQZ = 932, + Mips_BC1EQZC_MMR6 = 933, + Mips_BC1F = 934, + Mips_BC1FL = 935, + Mips_BC1F_MM = 936, + Mips_BC1NEZ = 937, + Mips_BC1NEZC_MMR6 = 938, + Mips_BC1T = 939, + Mips_BC1TL = 940, + Mips_BC1T_MM = 941, + Mips_BC2EQZ = 942, + Mips_BC2EQZC_MMR6 = 943, + Mips_BC2NEZ = 944, + Mips_BC2NEZC_MMR6 = 945, + Mips_BCLRI_B = 946, + Mips_BCLRI_D = 947, + Mips_BCLRI_H = 948, + Mips_BCLRI_W = 949, + Mips_BCLR_B = 950, + Mips_BCLR_D = 951, + Mips_BCLR_H = 952, + Mips_BCLR_W = 953, + Mips_BC_MMR6 = 954, + Mips_BC_NM = 955, + Mips_BEQ = 956, + Mips_BEQ64 = 957, + Mips_BEQC = 958, + Mips_BEQC16_NM = 959, + Mips_BEQC64 = 960, + Mips_BEQC_MMR6 = 961, + Mips_BEQC_NM = 962, + Mips_BEQCzero_NM = 963, + Mips_BEQIC_NM = 964, + Mips_BEQL = 965, + Mips_BEQZ16_MM = 966, + Mips_BEQZALC = 967, + Mips_BEQZALC_MMR6 = 968, + Mips_BEQZC = 969, + Mips_BEQZC16_MMR6 = 970, + Mips_BEQZC16_NM = 971, + Mips_BEQZC64 = 972, + Mips_BEQZC_MM = 973, + Mips_BEQZC_MMR6 = 974, + Mips_BEQZC_NM = 975, + Mips_BEQ_MM = 976, + Mips_BGEC = 977, + Mips_BGEC64 = 978, + Mips_BGEC_MMR6 = 979, + Mips_BGEC_NM = 980, + Mips_BGEIC_NM = 981, + Mips_BGEIUC_NM = 982, + Mips_BGEUC = 983, + Mips_BGEUC64 = 984, + Mips_BGEUC_MMR6 = 985, + Mips_BGEUC_NM = 986, + Mips_BGEZ = 987, + Mips_BGEZ64 = 988, + Mips_BGEZAL = 989, + Mips_BGEZALC = 990, + Mips_BGEZALC_MMR6 = 991, + Mips_BGEZALL = 992, + Mips_BGEZALS_MM = 993, + Mips_BGEZAL_MM = 994, + Mips_BGEZC = 995, + Mips_BGEZC64 = 996, + Mips_BGEZC_MMR6 = 997, + Mips_BGEZL = 998, + Mips_BGEZ_MM = 999, + Mips_BGTZ = 1000, + Mips_BGTZ64 = 1001, + Mips_BGTZALC = 1002, + Mips_BGTZALC_MMR6 = 1003, + Mips_BGTZC = 1004, + Mips_BGTZC64 = 1005, + Mips_BGTZC_MMR6 = 1006, + Mips_BGTZL = 1007, + Mips_BGTZ_MM = 1008, + Mips_BINSLI_B = 1009, + Mips_BINSLI_D = 1010, + Mips_BINSLI_H = 1011, + Mips_BINSLI_W = 1012, + Mips_BINSL_B = 1013, + Mips_BINSL_D = 1014, + Mips_BINSL_H = 1015, + Mips_BINSL_W = 1016, + Mips_BINSRI_B = 1017, + Mips_BINSRI_D = 1018, + Mips_BINSRI_H = 1019, + Mips_BINSRI_W = 1020, + Mips_BINSR_B = 1021, + Mips_BINSR_D = 1022, + Mips_BINSR_H = 1023, + Mips_BINSR_W = 1024, + Mips_BITREV = 1025, + Mips_BITREVW_NM = 1026, + Mips_BITREV_MM = 1027, + Mips_BITSWAP = 1028, + Mips_BITSWAP_MMR6 = 1029, + Mips_BLEZ = 1030, + Mips_BLEZ64 = 1031, + Mips_BLEZALC = 1032, + Mips_BLEZALC_MMR6 = 1033, + Mips_BLEZC = 1034, + Mips_BLEZC64 = 1035, + Mips_BLEZC_MMR6 = 1036, + Mips_BLEZL = 1037, + Mips_BLEZ_MM = 1038, + Mips_BLTC = 1039, + Mips_BLTC64 = 1040, + Mips_BLTC_MMR6 = 1041, + Mips_BLTC_NM = 1042, + Mips_BLTIC_NM = 1043, + Mips_BLTIUC_NM = 1044, + Mips_BLTUC = 1045, + Mips_BLTUC64 = 1046, + Mips_BLTUC_MMR6 = 1047, + Mips_BLTUC_NM = 1048, + Mips_BLTZ = 1049, + Mips_BLTZ64 = 1050, + Mips_BLTZAL = 1051, + Mips_BLTZALC = 1052, + Mips_BLTZALC_MMR6 = 1053, + Mips_BLTZALL = 1054, + Mips_BLTZALS_MM = 1055, + Mips_BLTZAL_MM = 1056, + Mips_BLTZC = 1057, + Mips_BLTZC64 = 1058, + Mips_BLTZC_MMR6 = 1059, + Mips_BLTZL = 1060, + Mips_BLTZ_MM = 1061, + Mips_BMNZI_B = 1062, + Mips_BMNZ_V = 1063, + Mips_BMZI_B = 1064, + Mips_BMZ_V = 1065, + Mips_BNE = 1066, + Mips_BNE64 = 1067, + Mips_BNEC = 1068, + Mips_BNEC16_NM = 1069, + Mips_BNEC64 = 1070, + Mips_BNEC_MMR6 = 1071, + Mips_BNEC_NM = 1072, + Mips_BNECzero_NM = 1073, + Mips_BNEGI_B = 1074, + Mips_BNEGI_D = 1075, + Mips_BNEGI_H = 1076, + Mips_BNEGI_W = 1077, + Mips_BNEG_B = 1078, + Mips_BNEG_D = 1079, + Mips_BNEG_H = 1080, + Mips_BNEG_W = 1081, + Mips_BNEIC_NM = 1082, + Mips_BNEL = 1083, + Mips_BNEZ16_MM = 1084, + Mips_BNEZALC = 1085, + Mips_BNEZALC_MMR6 = 1086, + Mips_BNEZC = 1087, + Mips_BNEZC16_MMR6 = 1088, + Mips_BNEZC16_NM = 1089, + Mips_BNEZC64 = 1090, + Mips_BNEZC_MM = 1091, + Mips_BNEZC_MMR6 = 1092, + Mips_BNEZC_NM = 1093, + Mips_BNE_MM = 1094, + Mips_BNVC = 1095, + Mips_BNVC_MMR6 = 1096, + Mips_BNZ_B = 1097, + Mips_BNZ_D = 1098, + Mips_BNZ_H = 1099, + Mips_BNZ_V = 1100, + Mips_BNZ_W = 1101, + Mips_BOVC = 1102, + Mips_BOVC_MMR6 = 1103, + Mips_BPOSGE32 = 1104, + Mips_BPOSGE32C_MMR3 = 1105, + Mips_BPOSGE32_MM = 1106, + Mips_BREAK = 1107, + Mips_BREAK16_MM = 1108, + Mips_BREAK16_MMR6 = 1109, + Mips_BREAK16_NM = 1110, + Mips_BREAK_MM = 1111, + Mips_BREAK_MMR6 = 1112, + Mips_BREAK_NM = 1113, + Mips_BRSC_NM = 1114, + Mips_BSELI_B = 1115, + Mips_BSEL_V = 1116, + Mips_BSETI_B = 1117, + Mips_BSETI_D = 1118, + Mips_BSETI_H = 1119, + Mips_BSETI_W = 1120, + Mips_BSET_B = 1121, + Mips_BSET_D = 1122, + Mips_BSET_H = 1123, + Mips_BSET_W = 1124, + Mips_BYTEREVW_NM = 1125, + Mips_BZ_B = 1126, + Mips_BZ_D = 1127, + Mips_BZ_H = 1128, + Mips_BZ_V = 1129, + Mips_BZ_W = 1130, + Mips_BeqzRxImm16 = 1131, + Mips_BeqzRxImmX16 = 1132, + Mips_Bimm16 = 1133, + Mips_BimmX16 = 1134, + Mips_BnezRxImm16 = 1135, + Mips_BnezRxImmX16 = 1136, + Mips_Break16 = 1137, + Mips_Bteqz16 = 1138, + Mips_BteqzX16 = 1139, + Mips_Btnez16 = 1140, + Mips_BtnezX16 = 1141, + Mips_CACHE = 1142, + Mips_CACHEE = 1143, + Mips_CACHEE_MM = 1144, + Mips_CACHE_MM = 1145, + Mips_CACHE_MMR6 = 1146, + Mips_CACHE_NM = 1147, + Mips_CACHE_R6 = 1148, + Mips_CEIL_L_D64 = 1149, + Mips_CEIL_L_D_MMR6 = 1150, + Mips_CEIL_L_S = 1151, + Mips_CEIL_L_S_MMR6 = 1152, + Mips_CEIL_W_D32 = 1153, + Mips_CEIL_W_D64 = 1154, + Mips_CEIL_W_D_MMR6 = 1155, + Mips_CEIL_W_MM = 1156, + Mips_CEIL_W_S = 1157, + Mips_CEIL_W_S_MM = 1158, + Mips_CEIL_W_S_MMR6 = 1159, + Mips_CEQI_B = 1160, + Mips_CEQI_D = 1161, + Mips_CEQI_H = 1162, + Mips_CEQI_W = 1163, + Mips_CEQ_B = 1164, + Mips_CEQ_D = 1165, + Mips_CEQ_H = 1166, + Mips_CEQ_W = 1167, + Mips_CFC1 = 1168, + Mips_CFC1_MM = 1169, + Mips_CFC2_MM = 1170, + Mips_CFCMSA = 1171, + Mips_CINS = 1172, + Mips_CINS32 = 1173, + Mips_CINS64_32 = 1174, + Mips_CINS_i32 = 1175, + Mips_CLASS_D = 1176, + Mips_CLASS_D_MMR6 = 1177, + Mips_CLASS_S = 1178, + Mips_CLASS_S_MMR6 = 1179, + Mips_CLEI_S_B = 1180, + Mips_CLEI_S_D = 1181, + Mips_CLEI_S_H = 1182, + Mips_CLEI_S_W = 1183, + Mips_CLEI_U_B = 1184, + Mips_CLEI_U_D = 1185, + Mips_CLEI_U_H = 1186, + Mips_CLEI_U_W = 1187, + Mips_CLE_S_B = 1188, + Mips_CLE_S_D = 1189, + Mips_CLE_S_H = 1190, + Mips_CLE_S_W = 1191, + Mips_CLE_U_B = 1192, + Mips_CLE_U_D = 1193, + Mips_CLE_U_H = 1194, + Mips_CLE_U_W = 1195, + Mips_CLO = 1196, + Mips_CLO_MM = 1197, + Mips_CLO_MMR6 = 1198, + Mips_CLO_NM = 1199, + Mips_CLO_R6 = 1200, + Mips_CLTI_S_B = 1201, + Mips_CLTI_S_D = 1202, + Mips_CLTI_S_H = 1203, + Mips_CLTI_S_W = 1204, + Mips_CLTI_U_B = 1205, + Mips_CLTI_U_D = 1206, + Mips_CLTI_U_H = 1207, + Mips_CLTI_U_W = 1208, + Mips_CLT_S_B = 1209, + Mips_CLT_S_D = 1210, + Mips_CLT_S_H = 1211, + Mips_CLT_S_W = 1212, + Mips_CLT_U_B = 1213, + Mips_CLT_U_D = 1214, + Mips_CLT_U_H = 1215, + Mips_CLT_U_W = 1216, + Mips_CLZ = 1217, + Mips_CLZ_MM = 1218, + Mips_CLZ_MMR6 = 1219, + Mips_CLZ_NM = 1220, + Mips_CLZ_R6 = 1221, + Mips_CMPGDU_EQ_QB = 1222, + Mips_CMPGDU_EQ_QB_MMR2 = 1223, + Mips_CMPGDU_LE_QB = 1224, + Mips_CMPGDU_LE_QB_MMR2 = 1225, + Mips_CMPGDU_LT_QB = 1226, + Mips_CMPGDU_LT_QB_MMR2 = 1227, + Mips_CMPGU_EQ_QB = 1228, + Mips_CMPGU_EQ_QB_MM = 1229, + Mips_CMPGU_LE_QB = 1230, + Mips_CMPGU_LE_QB_MM = 1231, + Mips_CMPGU_LT_QB = 1232, + Mips_CMPGU_LT_QB_MM = 1233, + Mips_CMPU_EQ_QB = 1234, + Mips_CMPU_EQ_QB_MM = 1235, + Mips_CMPU_LE_QB = 1236, + Mips_CMPU_LE_QB_MM = 1237, + Mips_CMPU_LT_QB = 1238, + Mips_CMPU_LT_QB_MM = 1239, + Mips_CMP_AF_D_MMR6 = 1240, + Mips_CMP_AF_S_MMR6 = 1241, + Mips_CMP_EQ_D = 1242, + Mips_CMP_EQ_D_MMR6 = 1243, + Mips_CMP_EQ_PH = 1244, + Mips_CMP_EQ_PH_MM = 1245, + Mips_CMP_EQ_S = 1246, + Mips_CMP_EQ_S_MMR6 = 1247, + Mips_CMP_F_D = 1248, + Mips_CMP_F_S = 1249, + Mips_CMP_LE_D = 1250, + Mips_CMP_LE_D_MMR6 = 1251, + Mips_CMP_LE_PH = 1252, + Mips_CMP_LE_PH_MM = 1253, + Mips_CMP_LE_S = 1254, + Mips_CMP_LE_S_MMR6 = 1255, + Mips_CMP_LT_D = 1256, + Mips_CMP_LT_D_MMR6 = 1257, + Mips_CMP_LT_PH = 1258, + Mips_CMP_LT_PH_MM = 1259, + Mips_CMP_LT_S = 1260, + Mips_CMP_LT_S_MMR6 = 1261, + Mips_CMP_SAF_D = 1262, + Mips_CMP_SAF_D_MMR6 = 1263, + Mips_CMP_SAF_S = 1264, + Mips_CMP_SAF_S_MMR6 = 1265, + Mips_CMP_SEQ_D = 1266, + Mips_CMP_SEQ_D_MMR6 = 1267, + Mips_CMP_SEQ_S = 1268, + Mips_CMP_SEQ_S_MMR6 = 1269, + Mips_CMP_SLE_D = 1270, + Mips_CMP_SLE_D_MMR6 = 1271, + Mips_CMP_SLE_S = 1272, + Mips_CMP_SLE_S_MMR6 = 1273, + Mips_CMP_SLT_D = 1274, + Mips_CMP_SLT_D_MMR6 = 1275, + Mips_CMP_SLT_S = 1276, + Mips_CMP_SLT_S_MMR6 = 1277, + Mips_CMP_SUEQ_D = 1278, + Mips_CMP_SUEQ_D_MMR6 = 1279, + Mips_CMP_SUEQ_S = 1280, + Mips_CMP_SUEQ_S_MMR6 = 1281, + Mips_CMP_SULE_D = 1282, + Mips_CMP_SULE_D_MMR6 = 1283, + Mips_CMP_SULE_S = 1284, + Mips_CMP_SULE_S_MMR6 = 1285, + Mips_CMP_SULT_D = 1286, + Mips_CMP_SULT_D_MMR6 = 1287, + Mips_CMP_SULT_S = 1288, + Mips_CMP_SULT_S_MMR6 = 1289, + Mips_CMP_SUN_D = 1290, + Mips_CMP_SUN_D_MMR6 = 1291, + Mips_CMP_SUN_S = 1292, + Mips_CMP_SUN_S_MMR6 = 1293, + Mips_CMP_UEQ_D = 1294, + Mips_CMP_UEQ_D_MMR6 = 1295, + Mips_CMP_UEQ_S = 1296, + Mips_CMP_UEQ_S_MMR6 = 1297, + Mips_CMP_ULE_D = 1298, + Mips_CMP_ULE_D_MMR6 = 1299, + Mips_CMP_ULE_S = 1300, + Mips_CMP_ULE_S_MMR6 = 1301, + Mips_CMP_ULT_D = 1302, + Mips_CMP_ULT_D_MMR6 = 1303, + Mips_CMP_ULT_S = 1304, + Mips_CMP_ULT_S_MMR6 = 1305, + Mips_CMP_UN_D = 1306, + Mips_CMP_UN_D_MMR6 = 1307, + Mips_CMP_UN_S = 1308, + Mips_CMP_UN_S_MMR6 = 1309, + Mips_COPY_S_B = 1310, + Mips_COPY_S_D = 1311, + Mips_COPY_S_H = 1312, + Mips_COPY_S_W = 1313, + Mips_COPY_U_B = 1314, + Mips_COPY_U_H = 1315, + Mips_COPY_U_W = 1316, + Mips_CRC32B = 1317, + Mips_CRC32B_NM = 1318, + Mips_CRC32CB = 1319, + Mips_CRC32CB_NM = 1320, + Mips_CRC32CD = 1321, + Mips_CRC32CH = 1322, + Mips_CRC32CH_NM = 1323, + Mips_CRC32CW = 1324, + Mips_CRC32CW_NM = 1325, + Mips_CRC32D = 1326, + Mips_CRC32H = 1327, + Mips_CRC32H_NM = 1328, + Mips_CRC32W = 1329, + Mips_CRC32W_NM = 1330, + Mips_CTC1 = 1331, + Mips_CTC1_MM = 1332, + Mips_CTC2_MM = 1333, + Mips_CTCMSA = 1334, + Mips_CVT_D32_S = 1335, + Mips_CVT_D32_S_MM = 1336, + Mips_CVT_D32_W = 1337, + Mips_CVT_D32_W_MM = 1338, + Mips_CVT_D64_L = 1339, + Mips_CVT_D64_S = 1340, + Mips_CVT_D64_S_MM = 1341, + Mips_CVT_D64_W = 1342, + Mips_CVT_D64_W_MM = 1343, + Mips_CVT_D_L_MMR6 = 1344, + Mips_CVT_L_D64 = 1345, + Mips_CVT_L_D64_MM = 1346, + Mips_CVT_L_D_MMR6 = 1347, + Mips_CVT_L_S = 1348, + Mips_CVT_L_S_MM = 1349, + Mips_CVT_L_S_MMR6 = 1350, + Mips_CVT_PS_PW64 = 1351, + Mips_CVT_PS_S64 = 1352, + Mips_CVT_PW_PS64 = 1353, + Mips_CVT_S_D32 = 1354, + Mips_CVT_S_D32_MM = 1355, + Mips_CVT_S_D64 = 1356, + Mips_CVT_S_D64_MM = 1357, + Mips_CVT_S_L = 1358, + Mips_CVT_S_L_MMR6 = 1359, + Mips_CVT_S_PL64 = 1360, + Mips_CVT_S_PU64 = 1361, + Mips_CVT_S_W = 1362, + Mips_CVT_S_W_MM = 1363, + Mips_CVT_S_W_MMR6 = 1364, + Mips_CVT_W_D32 = 1365, + Mips_CVT_W_D32_MM = 1366, + Mips_CVT_W_D64 = 1367, + Mips_CVT_W_D64_MM = 1368, + Mips_CVT_W_S = 1369, + Mips_CVT_W_S_MM = 1370, + Mips_CVT_W_S_MMR6 = 1371, + Mips_C_EQ_D32 = 1372, + Mips_C_EQ_D32_MM = 1373, + Mips_C_EQ_D64 = 1374, + Mips_C_EQ_D64_MM = 1375, + Mips_C_EQ_S = 1376, + Mips_C_EQ_S_MM = 1377, + Mips_C_F_D32 = 1378, + Mips_C_F_D32_MM = 1379, + Mips_C_F_D64 = 1380, + Mips_C_F_D64_MM = 1381, + Mips_C_F_S = 1382, + Mips_C_F_S_MM = 1383, + Mips_C_LE_D32 = 1384, + Mips_C_LE_D32_MM = 1385, + Mips_C_LE_D64 = 1386, + Mips_C_LE_D64_MM = 1387, + Mips_C_LE_S = 1388, + Mips_C_LE_S_MM = 1389, + Mips_C_LT_D32 = 1390, + Mips_C_LT_D32_MM = 1391, + Mips_C_LT_D64 = 1392, + Mips_C_LT_D64_MM = 1393, + Mips_C_LT_S = 1394, + Mips_C_LT_S_MM = 1395, + Mips_C_NGE_D32 = 1396, + Mips_C_NGE_D32_MM = 1397, + Mips_C_NGE_D64 = 1398, + Mips_C_NGE_D64_MM = 1399, + Mips_C_NGE_S = 1400, + Mips_C_NGE_S_MM = 1401, + Mips_C_NGLE_D32 = 1402, + Mips_C_NGLE_D32_MM = 1403, + Mips_C_NGLE_D64 = 1404, + Mips_C_NGLE_D64_MM = 1405, + Mips_C_NGLE_S = 1406, + Mips_C_NGLE_S_MM = 1407, + Mips_C_NGL_D32 = 1408, + Mips_C_NGL_D32_MM = 1409, + Mips_C_NGL_D64 = 1410, + Mips_C_NGL_D64_MM = 1411, + Mips_C_NGL_S = 1412, + Mips_C_NGL_S_MM = 1413, + Mips_C_NGT_D32 = 1414, + Mips_C_NGT_D32_MM = 1415, + Mips_C_NGT_D64 = 1416, + Mips_C_NGT_D64_MM = 1417, + Mips_C_NGT_S = 1418, + Mips_C_NGT_S_MM = 1419, + Mips_C_OLE_D32 = 1420, + Mips_C_OLE_D32_MM = 1421, + Mips_C_OLE_D64 = 1422, + Mips_C_OLE_D64_MM = 1423, + Mips_C_OLE_S = 1424, + Mips_C_OLE_S_MM = 1425, + Mips_C_OLT_D32 = 1426, + Mips_C_OLT_D32_MM = 1427, + Mips_C_OLT_D64 = 1428, + Mips_C_OLT_D64_MM = 1429, + Mips_C_OLT_S = 1430, + Mips_C_OLT_S_MM = 1431, + Mips_C_SEQ_D32 = 1432, + Mips_C_SEQ_D32_MM = 1433, + Mips_C_SEQ_D64 = 1434, + Mips_C_SEQ_D64_MM = 1435, + Mips_C_SEQ_S = 1436, + Mips_C_SEQ_S_MM = 1437, + Mips_C_SF_D32 = 1438, + Mips_C_SF_D32_MM = 1439, + Mips_C_SF_D64 = 1440, + Mips_C_SF_D64_MM = 1441, + Mips_C_SF_S = 1442, + Mips_C_SF_S_MM = 1443, + Mips_C_UEQ_D32 = 1444, + Mips_C_UEQ_D32_MM = 1445, + Mips_C_UEQ_D64 = 1446, + Mips_C_UEQ_D64_MM = 1447, + Mips_C_UEQ_S = 1448, + Mips_C_UEQ_S_MM = 1449, + Mips_C_ULE_D32 = 1450, + Mips_C_ULE_D32_MM = 1451, + Mips_C_ULE_D64 = 1452, + Mips_C_ULE_D64_MM = 1453, + Mips_C_ULE_S = 1454, + Mips_C_ULE_S_MM = 1455, + Mips_C_ULT_D32 = 1456, + Mips_C_ULT_D32_MM = 1457, + Mips_C_ULT_D64 = 1458, + Mips_C_ULT_D64_MM = 1459, + Mips_C_ULT_S = 1460, + Mips_C_ULT_S_MM = 1461, + Mips_C_UN_D32 = 1462, + Mips_C_UN_D32_MM = 1463, + Mips_C_UN_D64 = 1464, + Mips_C_UN_D64_MM = 1465, + Mips_C_UN_S = 1466, + Mips_C_UN_S_MM = 1467, + Mips_CmpRxRy16 = 1468, + Mips_CmpiRxImm16 = 1469, + Mips_CmpiRxImmX16 = 1470, + Mips_DADD = 1471, + Mips_DADDi = 1472, + Mips_DADDiu = 1473, + Mips_DADDu = 1474, + Mips_DAHI = 1475, + Mips_DALIGN = 1476, + Mips_DATI = 1477, + Mips_DAUI = 1478, + Mips_DBITSWAP = 1479, + Mips_DCLO = 1480, + Mips_DCLO_R6 = 1481, + Mips_DCLZ = 1482, + Mips_DCLZ_R6 = 1483, + Mips_DDIV = 1484, + Mips_DDIVU = 1485, + Mips_DERET = 1486, + Mips_DERET_MM = 1487, + Mips_DERET_MMR6 = 1488, + Mips_DERET_NM = 1489, + Mips_DEXT = 1490, + Mips_DEXT64_32 = 1491, + Mips_DEXTM = 1492, + Mips_DEXTU = 1493, + Mips_DI = 1494, + Mips_DINS = 1495, + Mips_DINSM = 1496, + Mips_DINSU = 1497, + Mips_DIV = 1498, + Mips_DIVU = 1499, + Mips_DIVU_MMR6 = 1500, + Mips_DIVU_NM = 1501, + Mips_DIV_MMR6 = 1502, + Mips_DIV_NM = 1503, + Mips_DIV_S_B = 1504, + Mips_DIV_S_D = 1505, + Mips_DIV_S_H = 1506, + Mips_DIV_S_W = 1507, + Mips_DIV_U_B = 1508, + Mips_DIV_U_D = 1509, + Mips_DIV_U_H = 1510, + Mips_DIV_U_W = 1511, + Mips_DI_MM = 1512, + Mips_DI_MMR6 = 1513, + Mips_DI_NM = 1514, + Mips_DLSA = 1515, + Mips_DLSA_R6 = 1516, + Mips_DMFC0 = 1517, + Mips_DMFC1 = 1518, + Mips_DMFC2 = 1519, + Mips_DMFC2_OCTEON = 1520, + Mips_DMFGC0 = 1521, + Mips_DMOD = 1522, + Mips_DMODU = 1523, + Mips_DMT = 1524, + Mips_DMTC0 = 1525, + Mips_DMTC1 = 1526, + Mips_DMTC2 = 1527, + Mips_DMTC2_OCTEON = 1528, + Mips_DMTGC0 = 1529, + Mips_DMT_NM = 1530, + Mips_DMUH = 1531, + Mips_DMUHU = 1532, + Mips_DMUL = 1533, + Mips_DMULT = 1534, + Mips_DMULTu = 1535, + Mips_DMULU = 1536, + Mips_DMUL_R6 = 1537, + Mips_DOTP_S_D = 1538, + Mips_DOTP_S_H = 1539, + Mips_DOTP_S_W = 1540, + Mips_DOTP_U_D = 1541, + Mips_DOTP_U_H = 1542, + Mips_DOTP_U_W = 1543, + Mips_DPADD_S_D = 1544, + Mips_DPADD_S_H = 1545, + Mips_DPADD_S_W = 1546, + Mips_DPADD_U_D = 1547, + Mips_DPADD_U_H = 1548, + Mips_DPADD_U_W = 1549, + Mips_DPAQX_SA_W_PH = 1550, + Mips_DPAQX_SA_W_PH_MMR2 = 1551, + Mips_DPAQX_S_W_PH = 1552, + Mips_DPAQX_S_W_PH_MMR2 = 1553, + Mips_DPAQ_SA_L_W = 1554, + Mips_DPAQ_SA_L_W_MM = 1555, + Mips_DPAQ_S_W_PH = 1556, + Mips_DPAQ_S_W_PH_MM = 1557, + Mips_DPAU_H_QBL = 1558, + Mips_DPAU_H_QBL_MM = 1559, + Mips_DPAU_H_QBR = 1560, + Mips_DPAU_H_QBR_MM = 1561, + Mips_DPAX_W_PH = 1562, + Mips_DPAX_W_PH_MMR2 = 1563, + Mips_DPA_W_PH = 1564, + Mips_DPA_W_PH_MMR2 = 1565, + Mips_DPOP = 1566, + Mips_DPSQX_SA_W_PH = 1567, + Mips_DPSQX_SA_W_PH_MMR2 = 1568, + Mips_DPSQX_S_W_PH = 1569, + Mips_DPSQX_S_W_PH_MMR2 = 1570, + Mips_DPSQ_SA_L_W = 1571, + Mips_DPSQ_SA_L_W_MM = 1572, + Mips_DPSQ_S_W_PH = 1573, + Mips_DPSQ_S_W_PH_MM = 1574, + Mips_DPSUB_S_D = 1575, + Mips_DPSUB_S_H = 1576, + Mips_DPSUB_S_W = 1577, + Mips_DPSUB_U_D = 1578, + Mips_DPSUB_U_H = 1579, + Mips_DPSUB_U_W = 1580, + Mips_DPSU_H_QBL = 1581, + Mips_DPSU_H_QBL_MM = 1582, + Mips_DPSU_H_QBR = 1583, + Mips_DPSU_H_QBR_MM = 1584, + Mips_DPSX_W_PH = 1585, + Mips_DPSX_W_PH_MMR2 = 1586, + Mips_DPS_W_PH = 1587, + Mips_DPS_W_PH_MMR2 = 1588, + Mips_DROTR = 1589, + Mips_DROTR32 = 1590, + Mips_DROTRV = 1591, + Mips_DSBH = 1592, + Mips_DSDIV = 1593, + Mips_DSHD = 1594, + Mips_DSLL = 1595, + Mips_DSLL32 = 1596, + Mips_DSLL64_32 = 1597, + Mips_DSLLV = 1598, + Mips_DSRA = 1599, + Mips_DSRA32 = 1600, + Mips_DSRAV = 1601, + Mips_DSRL = 1602, + Mips_DSRL32 = 1603, + Mips_DSRLV = 1604, + Mips_DSUB = 1605, + Mips_DSUBu = 1606, + Mips_DUDIV = 1607, + Mips_DVP = 1608, + Mips_DVPE = 1609, + Mips_DVPE_NM = 1610, + Mips_DVP_MMR6 = 1611, + Mips_DivRxRy16 = 1612, + Mips_DivuRxRy16 = 1613, + Mips_EHB = 1614, + Mips_EHB_MM = 1615, + Mips_EHB_MMR6 = 1616, + Mips_EHB_NM = 1617, + Mips_EI = 1618, + Mips_EI_MM = 1619, + Mips_EI_MMR6 = 1620, + Mips_EI_NM = 1621, + Mips_EMT = 1622, + Mips_EMT_NM = 1623, + Mips_ERET = 1624, + Mips_ERETNC = 1625, + Mips_ERETNC_MMR6 = 1626, + Mips_ERETNC_NM = 1627, + Mips_ERET_MM = 1628, + Mips_ERET_MMR6 = 1629, + Mips_ERET_NM = 1630, + Mips_EVP = 1631, + Mips_EVPE = 1632, + Mips_EVPE_NM = 1633, + Mips_EVP_MMR6 = 1634, + Mips_EXT = 1635, + Mips_EXTP = 1636, + Mips_EXTPDP = 1637, + Mips_EXTPDPV = 1638, + Mips_EXTPDPV_MM = 1639, + Mips_EXTPDP_MM = 1640, + Mips_EXTPV = 1641, + Mips_EXTPV_MM = 1642, + Mips_EXTP_MM = 1643, + Mips_EXTRV_RS_W = 1644, + Mips_EXTRV_RS_W_MM = 1645, + Mips_EXTRV_R_W = 1646, + Mips_EXTRV_R_W_MM = 1647, + Mips_EXTRV_S_H = 1648, + Mips_EXTRV_S_H_MM = 1649, + Mips_EXTRV_W = 1650, + Mips_EXTRV_W_MM = 1651, + Mips_EXTR_RS_W = 1652, + Mips_EXTR_RS_W_MM = 1653, + Mips_EXTR_R_W = 1654, + Mips_EXTR_R_W_MM = 1655, + Mips_EXTR_S_H = 1656, + Mips_EXTR_S_H_MM = 1657, + Mips_EXTR_W = 1658, + Mips_EXTR_W_MM = 1659, + Mips_EXTS = 1660, + Mips_EXTS32 = 1661, + Mips_EXTW_NM = 1662, + Mips_EXT_MM = 1663, + Mips_EXT_MMR6 = 1664, + Mips_EXT_NM = 1665, + Mips_FABS_D32 = 1666, + Mips_FABS_D32_MM = 1667, + Mips_FABS_D64 = 1668, + Mips_FABS_D64_MM = 1669, + Mips_FABS_S = 1670, + Mips_FABS_S_MM = 1671, + Mips_FADD_D = 1672, + Mips_FADD_D32 = 1673, + Mips_FADD_D32_MM = 1674, + Mips_FADD_D64 = 1675, + Mips_FADD_D64_MM = 1676, + Mips_FADD_PS64 = 1677, + Mips_FADD_S = 1678, + Mips_FADD_S_MM = 1679, + Mips_FADD_S_MMR6 = 1680, + Mips_FADD_W = 1681, + Mips_FCAF_D = 1682, + Mips_FCAF_W = 1683, + Mips_FCEQ_D = 1684, + Mips_FCEQ_W = 1685, + Mips_FCLASS_D = 1686, + Mips_FCLASS_W = 1687, + Mips_FCLE_D = 1688, + Mips_FCLE_W = 1689, + Mips_FCLT_D = 1690, + Mips_FCLT_W = 1691, + Mips_FCMP_D32 = 1692, + Mips_FCMP_D32_MM = 1693, + Mips_FCMP_D64 = 1694, + Mips_FCMP_S32 = 1695, + Mips_FCMP_S32_MM = 1696, + Mips_FCNE_D = 1697, + Mips_FCNE_W = 1698, + Mips_FCOR_D = 1699, + Mips_FCOR_W = 1700, + Mips_FCUEQ_D = 1701, + Mips_FCUEQ_W = 1702, + Mips_FCULE_D = 1703, + Mips_FCULE_W = 1704, + Mips_FCULT_D = 1705, + Mips_FCULT_W = 1706, + Mips_FCUNE_D = 1707, + Mips_FCUNE_W = 1708, + Mips_FCUN_D = 1709, + Mips_FCUN_W = 1710, + Mips_FDIV_D = 1711, + Mips_FDIV_D32 = 1712, + Mips_FDIV_D32_MM = 1713, + Mips_FDIV_D64 = 1714, + Mips_FDIV_D64_MM = 1715, + Mips_FDIV_S = 1716, + Mips_FDIV_S_MM = 1717, + Mips_FDIV_S_MMR6 = 1718, + Mips_FDIV_W = 1719, + Mips_FEXDO_H = 1720, + Mips_FEXDO_W = 1721, + Mips_FEXP2_D = 1722, + Mips_FEXP2_W = 1723, + Mips_FEXUPL_D = 1724, + Mips_FEXUPL_W = 1725, + Mips_FEXUPR_D = 1726, + Mips_FEXUPR_W = 1727, + Mips_FFINT_S_D = 1728, + Mips_FFINT_S_W = 1729, + Mips_FFINT_U_D = 1730, + Mips_FFINT_U_W = 1731, + Mips_FFQL_D = 1732, + Mips_FFQL_W = 1733, + Mips_FFQR_D = 1734, + Mips_FFQR_W = 1735, + Mips_FILL_B = 1736, + Mips_FILL_D = 1737, + Mips_FILL_H = 1738, + Mips_FILL_W = 1739, + Mips_FLOG2_D = 1740, + Mips_FLOG2_W = 1741, + Mips_FLOOR_L_D64 = 1742, + Mips_FLOOR_L_D_MMR6 = 1743, + Mips_FLOOR_L_S = 1744, + Mips_FLOOR_L_S_MMR6 = 1745, + Mips_FLOOR_W_D32 = 1746, + Mips_FLOOR_W_D64 = 1747, + Mips_FLOOR_W_D_MMR6 = 1748, + Mips_FLOOR_W_MM = 1749, + Mips_FLOOR_W_S = 1750, + Mips_FLOOR_W_S_MM = 1751, + Mips_FLOOR_W_S_MMR6 = 1752, + Mips_FMADD_D = 1753, + Mips_FMADD_W = 1754, + Mips_FMAX_A_D = 1755, + Mips_FMAX_A_W = 1756, + Mips_FMAX_D = 1757, + Mips_FMAX_W = 1758, + Mips_FMIN_A_D = 1759, + Mips_FMIN_A_W = 1760, + Mips_FMIN_D = 1761, + Mips_FMIN_W = 1762, + Mips_FMOV_D32 = 1763, + Mips_FMOV_D32_MM = 1764, + Mips_FMOV_D64 = 1765, + Mips_FMOV_D64_MM = 1766, + Mips_FMOV_D_MMR6 = 1767, + Mips_FMOV_S = 1768, + Mips_FMOV_S_MM = 1769, + Mips_FMOV_S_MMR6 = 1770, + Mips_FMSUB_D = 1771, + Mips_FMSUB_W = 1772, + Mips_FMUL_D = 1773, + Mips_FMUL_D32 = 1774, + Mips_FMUL_D32_MM = 1775, + Mips_FMUL_D64 = 1776, + Mips_FMUL_D64_MM = 1777, + Mips_FMUL_PS64 = 1778, + Mips_FMUL_S = 1779, + Mips_FMUL_S_MM = 1780, + Mips_FMUL_S_MMR6 = 1781, + Mips_FMUL_W = 1782, + Mips_FNEG_D32 = 1783, + Mips_FNEG_D32_MM = 1784, + Mips_FNEG_D64 = 1785, + Mips_FNEG_D64_MM = 1786, + Mips_FNEG_S = 1787, + Mips_FNEG_S_MM = 1788, + Mips_FNEG_S_MMR6 = 1789, + Mips_FORK = 1790, + Mips_FORK_NM = 1791, + Mips_FRCP_D = 1792, + Mips_FRCP_W = 1793, + Mips_FRINT_D = 1794, + Mips_FRINT_W = 1795, + Mips_FRSQRT_D = 1796, + Mips_FRSQRT_W = 1797, + Mips_FSAF_D = 1798, + Mips_FSAF_W = 1799, + Mips_FSEQ_D = 1800, + Mips_FSEQ_W = 1801, + Mips_FSLE_D = 1802, + Mips_FSLE_W = 1803, + Mips_FSLT_D = 1804, + Mips_FSLT_W = 1805, + Mips_FSNE_D = 1806, + Mips_FSNE_W = 1807, + Mips_FSOR_D = 1808, + Mips_FSOR_W = 1809, + Mips_FSQRT_D = 1810, + Mips_FSQRT_D32 = 1811, + Mips_FSQRT_D32_MM = 1812, + Mips_FSQRT_D64 = 1813, + Mips_FSQRT_D64_MM = 1814, + Mips_FSQRT_S = 1815, + Mips_FSQRT_S_MM = 1816, + Mips_FSQRT_W = 1817, + Mips_FSUB_D = 1818, + Mips_FSUB_D32 = 1819, + Mips_FSUB_D32_MM = 1820, + Mips_FSUB_D64 = 1821, + Mips_FSUB_D64_MM = 1822, + Mips_FSUB_PS64 = 1823, + Mips_FSUB_S = 1824, + Mips_FSUB_S_MM = 1825, + Mips_FSUB_S_MMR6 = 1826, + Mips_FSUB_W = 1827, + Mips_FSUEQ_D = 1828, + Mips_FSUEQ_W = 1829, + Mips_FSULE_D = 1830, + Mips_FSULE_W = 1831, + Mips_FSULT_D = 1832, + Mips_FSULT_W = 1833, + Mips_FSUNE_D = 1834, + Mips_FSUNE_W = 1835, + Mips_FSUN_D = 1836, + Mips_FSUN_W = 1837, + Mips_FTINT_S_D = 1838, + Mips_FTINT_S_W = 1839, + Mips_FTINT_U_D = 1840, + Mips_FTINT_U_W = 1841, + Mips_FTQ_H = 1842, + Mips_FTQ_W = 1843, + Mips_FTRUNC_S_D = 1844, + Mips_FTRUNC_S_W = 1845, + Mips_FTRUNC_U_D = 1846, + Mips_FTRUNC_U_W = 1847, + Mips_GINVI = 1848, + Mips_GINVI_MMR6 = 1849, + Mips_GINVI_NM = 1850, + Mips_GINVT = 1851, + Mips_GINVT_MMR6 = 1852, + Mips_GINVT_NM = 1853, + Mips_HADD_S_D = 1854, + Mips_HADD_S_H = 1855, + Mips_HADD_S_W = 1856, + Mips_HADD_U_D = 1857, + Mips_HADD_U_H = 1858, + Mips_HADD_U_W = 1859, + Mips_HSUB_S_D = 1860, + Mips_HSUB_S_H = 1861, + Mips_HSUB_S_W = 1862, + Mips_HSUB_U_D = 1863, + Mips_HSUB_U_H = 1864, + Mips_HSUB_U_W = 1865, + Mips_HYPCALL = 1866, + Mips_HYPCALL_MM = 1867, + Mips_ILVEV_B = 1868, + Mips_ILVEV_D = 1869, + Mips_ILVEV_H = 1870, + Mips_ILVEV_W = 1871, + Mips_ILVL_B = 1872, + Mips_ILVL_D = 1873, + Mips_ILVL_H = 1874, + Mips_ILVL_W = 1875, + Mips_ILVOD_B = 1876, + Mips_ILVOD_D = 1877, + Mips_ILVOD_H = 1878, + Mips_ILVOD_W = 1879, + Mips_ILVR_B = 1880, + Mips_ILVR_D = 1881, + Mips_ILVR_H = 1882, + Mips_ILVR_W = 1883, + Mips_INS = 1884, + Mips_INSERT_B = 1885, + Mips_INSERT_D = 1886, + Mips_INSERT_H = 1887, + Mips_INSERT_W = 1888, + Mips_INSV = 1889, + Mips_INSVE_B = 1890, + Mips_INSVE_D = 1891, + Mips_INSVE_H = 1892, + Mips_INSVE_W = 1893, + Mips_INSV_MM = 1894, + Mips_INS_MM = 1895, + Mips_INS_MMR6 = 1896, + Mips_INS_NM = 1897, + Mips_J = 1898, + Mips_JAL = 1899, + Mips_JALR = 1900, + Mips_JALR16_MM = 1901, + Mips_JALR64 = 1902, + Mips_JALRC16_MMR6 = 1903, + Mips_JALRC16_NM = 1904, + Mips_JALRCHB_NM = 1905, + Mips_JALRC_HB_MMR6 = 1906, + Mips_JALRC_MMR6 = 1907, + Mips_JALRC_NM = 1908, + Mips_JALRS16_MM = 1909, + Mips_JALRS_MM = 1910, + Mips_JALR_HB = 1911, + Mips_JALR_HB64 = 1912, + Mips_JALR_MM = 1913, + Mips_JALS_MM = 1914, + Mips_JALX = 1915, + Mips_JALX_MM = 1916, + Mips_JAL_MM = 1917, + Mips_JIALC = 1918, + Mips_JIALC64 = 1919, + Mips_JIALC_MMR6 = 1920, + Mips_JIC = 1921, + Mips_JIC64 = 1922, + Mips_JIC_MMR6 = 1923, + Mips_JR = 1924, + Mips_JR16_MM = 1925, + Mips_JR64 = 1926, + Mips_JRADDIUSP = 1927, + Mips_JRC16_MM = 1928, + Mips_JRC16_MMR6 = 1929, + Mips_JRCADDIUSP_MMR6 = 1930, + Mips_JRC_NM = 1931, + Mips_JR_HB = 1932, + Mips_JR_HB64 = 1933, + Mips_JR_HB64_R6 = 1934, + Mips_JR_HB_R6 = 1935, + Mips_JR_MM = 1936, + Mips_J_MM = 1937, + Mips_Jal16 = 1938, + Mips_JalB16 = 1939, + Mips_JrRa16 = 1940, + Mips_JrcRa16 = 1941, + Mips_JrcRx16 = 1942, + Mips_JumpLinkReg16 = 1943, + Mips_LAPC32_NM = 1944, + Mips_LAPC48_NM = 1945, + Mips_LB = 1946, + Mips_LB16_NM = 1947, + Mips_LB64 = 1948, + Mips_LBE = 1949, + Mips_LBE_MM = 1950, + Mips_LBGP_NM = 1951, + Mips_LBU16_MM = 1952, + Mips_LBU16_NM = 1953, + Mips_LBUGP_NM = 1954, + Mips_LBUX = 1955, + Mips_LBUX_MM = 1956, + Mips_LBUX_NM = 1957, + Mips_LBU_MMR6 = 1958, + Mips_LBU_NM = 1959, + Mips_LBUs9_NM = 1960, + Mips_LBX_NM = 1961, + Mips_LB_MM = 1962, + Mips_LB_MMR6 = 1963, + Mips_LB_NM = 1964, + Mips_LBs9_NM = 1965, + Mips_LBu = 1966, + Mips_LBu64 = 1967, + Mips_LBuE = 1968, + Mips_LBuE_MM = 1969, + Mips_LBu_MM = 1970, + Mips_LD = 1971, + Mips_LDC1 = 1972, + Mips_LDC164 = 1973, + Mips_LDC1_D64_MMR6 = 1974, + Mips_LDC1_MM_D32 = 1975, + Mips_LDC1_MM_D64 = 1976, + Mips_LDC2 = 1977, + Mips_LDC2_MMR6 = 1978, + Mips_LDC2_R6 = 1979, + Mips_LDC3 = 1980, + Mips_LDI_B = 1981, + Mips_LDI_D = 1982, + Mips_LDI_H = 1983, + Mips_LDI_W = 1984, + Mips_LDL = 1985, + Mips_LDPC = 1986, + Mips_LDR = 1987, + Mips_LDXC1 = 1988, + Mips_LDXC164 = 1989, + Mips_LD_B = 1990, + Mips_LD_D = 1991, + Mips_LD_H = 1992, + Mips_LD_W = 1993, + Mips_LEA_ADDIU_NM = 1994, + Mips_LEA_ADDiu = 1995, + Mips_LEA_ADDiu64 = 1996, + Mips_LEA_ADDiu_MM = 1997, + Mips_LH = 1998, + Mips_LH16_NM = 1999, + Mips_LH64 = 2000, + Mips_LHE = 2001, + Mips_LHE_MM = 2002, + Mips_LHGP_NM = 2003, + Mips_LHU16_MM = 2004, + Mips_LHU16_NM = 2005, + Mips_LHUGP_NM = 2006, + Mips_LHUXS_NM = 2007, + Mips_LHUX_NM = 2008, + Mips_LHU_NM = 2009, + Mips_LHUs9_NM = 2010, + Mips_LHX = 2011, + Mips_LHXS_NM = 2012, + Mips_LHX_MM = 2013, + Mips_LHX_NM = 2014, + Mips_LH_MM = 2015, + Mips_LH_NM = 2016, + Mips_LHs9_NM = 2017, + Mips_LHu = 2018, + Mips_LHu64 = 2019, + Mips_LHuE = 2020, + Mips_LHuE_MM = 2021, + Mips_LHu_MM = 2022, + Mips_LI16_MM = 2023, + Mips_LI16_MMR6 = 2024, + Mips_LI16_NM = 2025, + Mips_LI48_NM = 2026, + Mips_LL = 2027, + Mips_LL64 = 2028, + Mips_LL64_R6 = 2029, + Mips_LLD = 2030, + Mips_LLD_R6 = 2031, + Mips_LLE = 2032, + Mips_LLE_MM = 2033, + Mips_LLWP_NM = 2034, + Mips_LL_MM = 2035, + Mips_LL_MMR6 = 2036, + Mips_LL_NM = 2037, + Mips_LL_R6 = 2038, + Mips_LSA = 2039, + Mips_LSA_MMR6 = 2040, + Mips_LSA_NM = 2041, + Mips_LSA_R6 = 2042, + Mips_LUI_MMR6 = 2043, + Mips_LUI_NM = 2044, + Mips_LUXC1 = 2045, + Mips_LUXC164 = 2046, + Mips_LUXC1_MM = 2047, + Mips_LUi = 2048, + Mips_LUi64 = 2049, + Mips_LUi_MM = 2050, + Mips_LW = 2051, + Mips_LW16_MM = 2052, + Mips_LW16_NM = 2053, + Mips_LW4x4_NM = 2054, + Mips_LW64 = 2055, + Mips_LWC1 = 2056, + Mips_LWC1_MM = 2057, + Mips_LWC2 = 2058, + Mips_LWC2_MMR6 = 2059, + Mips_LWC2_R6 = 2060, + Mips_LWC3 = 2061, + Mips_LWDSP = 2062, + Mips_LWDSP_MM = 2063, + Mips_LWE = 2064, + Mips_LWE_MM = 2065, + Mips_LWGP16_NM = 2066, + Mips_LWGP_MM = 2067, + Mips_LWGP_NM = 2068, + Mips_LWL = 2069, + Mips_LWL64 = 2070, + Mips_LWLE = 2071, + Mips_LWLE_MM = 2072, + Mips_LWL_MM = 2073, + Mips_LWM16_MM = 2074, + Mips_LWM16_MMR6 = 2075, + Mips_LWM32_MM = 2076, + Mips_LWM_NM = 2077, + Mips_LWPC = 2078, + Mips_LWPC_MMR6 = 2079, + Mips_LWPC_NM = 2080, + Mips_LWP_MM = 2081, + Mips_LWR = 2082, + Mips_LWR64 = 2083, + Mips_LWRE = 2084, + Mips_LWRE_MM = 2085, + Mips_LWR_MM = 2086, + Mips_LWSP16_NM = 2087, + Mips_LWSP_MM = 2088, + Mips_LWUPC = 2089, + Mips_LWU_MM = 2090, + Mips_LWX = 2091, + Mips_LWXC1 = 2092, + Mips_LWXC1_MM = 2093, + Mips_LWXS16_NM = 2094, + Mips_LWXS_MM = 2095, + Mips_LWXS_NM = 2096, + Mips_LWX_MM = 2097, + Mips_LWX_NM = 2098, + Mips_LW_MM = 2099, + Mips_LW_MMR6 = 2100, + Mips_LW_NM = 2101, + Mips_LWs9_NM = 2102, + Mips_LWu = 2103, + Mips_LbRxRyOffMemX16 = 2104, + Mips_LbuRxRyOffMemX16 = 2105, + Mips_LhRxRyOffMemX16 = 2106, + Mips_LhuRxRyOffMemX16 = 2107, + Mips_LiRxImm16 = 2108, + Mips_LiRxImmAlignX16 = 2109, + Mips_LiRxImmX16 = 2110, + Mips_LwRxPcTcp16 = 2111, + Mips_LwRxPcTcpX16 = 2112, + Mips_LwRxRyOffMemX16 = 2113, + Mips_LwRxSpImmX16 = 2114, + Mips_MADD = 2115, + Mips_MADDF_D = 2116, + Mips_MADDF_D_MMR6 = 2117, + Mips_MADDF_S = 2118, + Mips_MADDF_S_MMR6 = 2119, + Mips_MADDR_Q_H = 2120, + Mips_MADDR_Q_W = 2121, + Mips_MADDU = 2122, + Mips_MADDU_DSP = 2123, + Mips_MADDU_DSP_MM = 2124, + Mips_MADDU_MM = 2125, + Mips_MADDV_B = 2126, + Mips_MADDV_D = 2127, + Mips_MADDV_H = 2128, + Mips_MADDV_W = 2129, + Mips_MADD_D32 = 2130, + Mips_MADD_D32_MM = 2131, + Mips_MADD_D64 = 2132, + Mips_MADD_DSP = 2133, + Mips_MADD_DSP_MM = 2134, + Mips_MADD_MM = 2135, + Mips_MADD_Q_H = 2136, + Mips_MADD_Q_W = 2137, + Mips_MADD_S = 2138, + Mips_MADD_S_MM = 2139, + Mips_MAQ_SA_W_PHL = 2140, + Mips_MAQ_SA_W_PHL_MM = 2141, + Mips_MAQ_SA_W_PHR = 2142, + Mips_MAQ_SA_W_PHR_MM = 2143, + Mips_MAQ_S_W_PHL = 2144, + Mips_MAQ_S_W_PHL_MM = 2145, + Mips_MAQ_S_W_PHR = 2146, + Mips_MAQ_S_W_PHR_MM = 2147, + Mips_MAXA_D = 2148, + Mips_MAXA_D_MMR6 = 2149, + Mips_MAXA_S = 2150, + Mips_MAXA_S_MMR6 = 2151, + Mips_MAXI_S_B = 2152, + Mips_MAXI_S_D = 2153, + Mips_MAXI_S_H = 2154, + Mips_MAXI_S_W = 2155, + Mips_MAXI_U_B = 2156, + Mips_MAXI_U_D = 2157, + Mips_MAXI_U_H = 2158, + Mips_MAXI_U_W = 2159, + Mips_MAX_A_B = 2160, + Mips_MAX_A_D = 2161, + Mips_MAX_A_H = 2162, + Mips_MAX_A_W = 2163, + Mips_MAX_D = 2164, + Mips_MAX_D_MMR6 = 2165, + Mips_MAX_S = 2166, + Mips_MAX_S_B = 2167, + Mips_MAX_S_D = 2168, + Mips_MAX_S_H = 2169, + Mips_MAX_S_MMR6 = 2170, + Mips_MAX_S_W = 2171, + Mips_MAX_U_B = 2172, + Mips_MAX_U_D = 2173, + Mips_MAX_U_H = 2174, + Mips_MAX_U_W = 2175, + Mips_MFC0 = 2176, + Mips_MFC0Sel_NM = 2177, + Mips_MFC0_MMR6 = 2178, + Mips_MFC0_NM = 2179, + Mips_MFC1 = 2180, + Mips_MFC1_D64 = 2181, + Mips_MFC1_MM = 2182, + Mips_MFC1_MMR6 = 2183, + Mips_MFC2 = 2184, + Mips_MFC2_MMR6 = 2185, + Mips_MFGC0 = 2186, + Mips_MFGC0_MM = 2187, + Mips_MFHC0Sel_NM = 2188, + Mips_MFHC0_MMR6 = 2189, + Mips_MFHC0_NM = 2190, + Mips_MFHC1_D32 = 2191, + Mips_MFHC1_D32_MM = 2192, + Mips_MFHC1_D64 = 2193, + Mips_MFHC1_D64_MM = 2194, + Mips_MFHC2_MMR6 = 2195, + Mips_MFHGC0 = 2196, + Mips_MFHGC0_MM = 2197, + Mips_MFHI = 2198, + Mips_MFHI16_MM = 2199, + Mips_MFHI64 = 2200, + Mips_MFHI_DSP = 2201, + Mips_MFHI_DSP_MM = 2202, + Mips_MFHI_MM = 2203, + Mips_MFLO = 2204, + Mips_MFLO16_MM = 2205, + Mips_MFLO64 = 2206, + Mips_MFLO_DSP = 2207, + Mips_MFLO_DSP_MM = 2208, + Mips_MFLO_MM = 2209, + Mips_MFTR = 2210, + Mips_MFTR_NM = 2211, + Mips_MINA_D = 2212, + Mips_MINA_D_MMR6 = 2213, + Mips_MINA_S = 2214, + Mips_MINA_S_MMR6 = 2215, + Mips_MINI_S_B = 2216, + Mips_MINI_S_D = 2217, + Mips_MINI_S_H = 2218, + Mips_MINI_S_W = 2219, + Mips_MINI_U_B = 2220, + Mips_MINI_U_D = 2221, + Mips_MINI_U_H = 2222, + Mips_MINI_U_W = 2223, + Mips_MIN_A_B = 2224, + Mips_MIN_A_D = 2225, + Mips_MIN_A_H = 2226, + Mips_MIN_A_W = 2227, + Mips_MIN_D = 2228, + Mips_MIN_D_MMR6 = 2229, + Mips_MIN_S = 2230, + Mips_MIN_S_B = 2231, + Mips_MIN_S_D = 2232, + Mips_MIN_S_H = 2233, + Mips_MIN_S_MMR6 = 2234, + Mips_MIN_S_W = 2235, + Mips_MIN_U_B = 2236, + Mips_MIN_U_D = 2237, + Mips_MIN_U_H = 2238, + Mips_MIN_U_W = 2239, + Mips_MOD = 2240, + Mips_MODSUB = 2241, + Mips_MODSUB_MM = 2242, + Mips_MODU = 2243, + Mips_MODU_MMR6 = 2244, + Mips_MODU_NM = 2245, + Mips_MOD_MMR6 = 2246, + Mips_MOD_NM = 2247, + Mips_MOD_S_B = 2248, + Mips_MOD_S_D = 2249, + Mips_MOD_S_H = 2250, + Mips_MOD_S_W = 2251, + Mips_MOD_U_B = 2252, + Mips_MOD_U_D = 2253, + Mips_MOD_U_H = 2254, + Mips_MOD_U_W = 2255, + Mips_MOVE16_MM = 2256, + Mips_MOVE16_MMR6 = 2257, + Mips_MOVEBALC_NM = 2258, + Mips_MOVEPREV_NM = 2259, + Mips_MOVEP_MM = 2260, + Mips_MOVEP_MMR6 = 2261, + Mips_MOVEP_NM = 2262, + Mips_MOVE_NM = 2263, + Mips_MOVE_V = 2264, + Mips_MOVF_D32 = 2265, + Mips_MOVF_D32_MM = 2266, + Mips_MOVF_D64 = 2267, + Mips_MOVF_I = 2268, + Mips_MOVF_I64 = 2269, + Mips_MOVF_I_MM = 2270, + Mips_MOVF_S = 2271, + Mips_MOVF_S_MM = 2272, + Mips_MOVN_I64_D64 = 2273, + Mips_MOVN_I64_I = 2274, + Mips_MOVN_I64_I64 = 2275, + Mips_MOVN_I64_S = 2276, + Mips_MOVN_I_D32 = 2277, + Mips_MOVN_I_D32_MM = 2278, + Mips_MOVN_I_D64 = 2279, + Mips_MOVN_I_I = 2280, + Mips_MOVN_I_I64 = 2281, + Mips_MOVN_I_MM = 2282, + Mips_MOVN_I_S = 2283, + Mips_MOVN_I_S_MM = 2284, + Mips_MOVN_NM = 2285, + Mips_MOVT_D32 = 2286, + Mips_MOVT_D32_MM = 2287, + Mips_MOVT_D64 = 2288, + Mips_MOVT_I = 2289, + Mips_MOVT_I64 = 2290, + Mips_MOVT_I_MM = 2291, + Mips_MOVT_S = 2292, + Mips_MOVT_S_MM = 2293, + Mips_MOVZ_I64_D64 = 2294, + Mips_MOVZ_I64_I = 2295, + Mips_MOVZ_I64_I64 = 2296, + Mips_MOVZ_I64_S = 2297, + Mips_MOVZ_I_D32 = 2298, + Mips_MOVZ_I_D32_MM = 2299, + Mips_MOVZ_I_D64 = 2300, + Mips_MOVZ_I_I = 2301, + Mips_MOVZ_I_I64 = 2302, + Mips_MOVZ_I_MM = 2303, + Mips_MOVZ_I_S = 2304, + Mips_MOVZ_I_S_MM = 2305, + Mips_MOVZ_NM = 2306, + Mips_MSUB = 2307, + Mips_MSUBF_D = 2308, + Mips_MSUBF_D_MMR6 = 2309, + Mips_MSUBF_S = 2310, + Mips_MSUBF_S_MMR6 = 2311, + Mips_MSUBR_Q_H = 2312, + Mips_MSUBR_Q_W = 2313, + Mips_MSUBU = 2314, + Mips_MSUBU_DSP = 2315, + Mips_MSUBU_DSP_MM = 2316, + Mips_MSUBU_MM = 2317, + Mips_MSUBV_B = 2318, + Mips_MSUBV_D = 2319, + Mips_MSUBV_H = 2320, + Mips_MSUBV_W = 2321, + Mips_MSUB_D32 = 2322, + Mips_MSUB_D32_MM = 2323, + Mips_MSUB_D64 = 2324, + Mips_MSUB_DSP = 2325, + Mips_MSUB_DSP_MM = 2326, + Mips_MSUB_MM = 2327, + Mips_MSUB_Q_H = 2328, + Mips_MSUB_Q_W = 2329, + Mips_MSUB_S = 2330, + Mips_MSUB_S_MM = 2331, + Mips_MTC0 = 2332, + Mips_MTC0Sel_NM = 2333, + Mips_MTC0_MMR6 = 2334, + Mips_MTC0_NM = 2335, + Mips_MTC1 = 2336, + Mips_MTC1_D64 = 2337, + Mips_MTC1_D64_MM = 2338, + Mips_MTC1_MM = 2339, + Mips_MTC1_MMR6 = 2340, + Mips_MTC2 = 2341, + Mips_MTC2_MMR6 = 2342, + Mips_MTGC0 = 2343, + Mips_MTGC0_MM = 2344, + Mips_MTHC0Sel_NM = 2345, + Mips_MTHC0_MMR6 = 2346, + Mips_MTHC0_NM = 2347, + Mips_MTHC1_D32 = 2348, + Mips_MTHC1_D32_MM = 2349, + Mips_MTHC1_D64 = 2350, + Mips_MTHC1_D64_MM = 2351, + Mips_MTHC2_MMR6 = 2352, + Mips_MTHGC0 = 2353, + Mips_MTHGC0_MM = 2354, + Mips_MTHI = 2355, + Mips_MTHI64 = 2356, + Mips_MTHI_DSP = 2357, + Mips_MTHI_DSP_MM = 2358, + Mips_MTHI_MM = 2359, + Mips_MTHLIP = 2360, + Mips_MTHLIP_MM = 2361, + Mips_MTLO = 2362, + Mips_MTLO64 = 2363, + Mips_MTLO_DSP = 2364, + Mips_MTLO_DSP_MM = 2365, + Mips_MTLO_MM = 2366, + Mips_MTM0 = 2367, + Mips_MTM1 = 2368, + Mips_MTM2 = 2369, + Mips_MTP0 = 2370, + Mips_MTP1 = 2371, + Mips_MTP2 = 2372, + Mips_MTTR = 2373, + Mips_MTTR_NM = 2374, + Mips_MUH = 2375, + Mips_MUHU = 2376, + Mips_MUHU_MMR6 = 2377, + Mips_MUHU_NM = 2378, + Mips_MUH_MMR6 = 2379, + Mips_MUH_NM = 2380, + Mips_MUL = 2381, + Mips_MUL4x4_NM = 2382, + Mips_MULEQ_S_W_PHL = 2383, + Mips_MULEQ_S_W_PHL_MM = 2384, + Mips_MULEQ_S_W_PHR = 2385, + Mips_MULEQ_S_W_PHR_MM = 2386, + Mips_MULEU_S_PH_QBL = 2387, + Mips_MULEU_S_PH_QBL_MM = 2388, + Mips_MULEU_S_PH_QBR = 2389, + Mips_MULEU_S_PH_QBR_MM = 2390, + Mips_MULQ_RS_PH = 2391, + Mips_MULQ_RS_PH_MM = 2392, + Mips_MULQ_RS_W = 2393, + Mips_MULQ_RS_W_MMR2 = 2394, + Mips_MULQ_S_PH = 2395, + Mips_MULQ_S_PH_MMR2 = 2396, + Mips_MULQ_S_W = 2397, + Mips_MULQ_S_W_MMR2 = 2398, + Mips_MULR_PS64 = 2399, + Mips_MULR_Q_H = 2400, + Mips_MULR_Q_W = 2401, + Mips_MULSAQ_S_W_PH = 2402, + Mips_MULSAQ_S_W_PH_MM = 2403, + Mips_MULSA_W_PH = 2404, + Mips_MULSA_W_PH_MMR2 = 2405, + Mips_MULT = 2406, + Mips_MULTU_DSP = 2407, + Mips_MULTU_DSP_MM = 2408, + Mips_MULT_DSP = 2409, + Mips_MULT_DSP_MM = 2410, + Mips_MULT_MM = 2411, + Mips_MULTu = 2412, + Mips_MULTu_MM = 2413, + Mips_MULU = 2414, + Mips_MULU_MMR6 = 2415, + Mips_MULU_NM = 2416, + Mips_MULV_B = 2417, + Mips_MULV_D = 2418, + Mips_MULV_H = 2419, + Mips_MULV_W = 2420, + Mips_MUL_MM = 2421, + Mips_MUL_MMR6 = 2422, + Mips_MUL_NM = 2423, + Mips_MUL_PH = 2424, + Mips_MUL_PH_MMR2 = 2425, + Mips_MUL_Q_H = 2426, + Mips_MUL_Q_W = 2427, + Mips_MUL_R6 = 2428, + Mips_MUL_S_PH = 2429, + Mips_MUL_S_PH_MMR2 = 2430, + Mips_Mfhi16 = 2431, + Mips_Mflo16 = 2432, + Mips_Move32R16 = 2433, + Mips_MoveR3216 = 2434, + Mips_NLOC_B = 2435, + Mips_NLOC_D = 2436, + Mips_NLOC_H = 2437, + Mips_NLOC_W = 2438, + Mips_NLZC_B = 2439, + Mips_NLZC_D = 2440, + Mips_NLZC_H = 2441, + Mips_NLZC_W = 2442, + Mips_NMADD_D32 = 2443, + Mips_NMADD_D32_MM = 2444, + Mips_NMADD_D64 = 2445, + Mips_NMADD_S = 2446, + Mips_NMADD_S_MM = 2447, + Mips_NMSUB_D32 = 2448, + Mips_NMSUB_D32_MM = 2449, + Mips_NMSUB_D64 = 2450, + Mips_NMSUB_S = 2451, + Mips_NMSUB_S_MM = 2452, + Mips_NOP32_NM = 2453, + Mips_NOP_NM = 2454, + Mips_NOR = 2455, + Mips_NOR64 = 2456, + Mips_NORI_B = 2457, + Mips_NOR_MM = 2458, + Mips_NOR_MMR6 = 2459, + Mips_NOR_NM = 2460, + Mips_NOR_V = 2461, + Mips_NOT16_MM = 2462, + Mips_NOT16_MMR6 = 2463, + Mips_NOT16_NM = 2464, + Mips_NegRxRy16 = 2465, + Mips_NotRxRy16 = 2466, + Mips_OR = 2467, + Mips_OR16_MM = 2468, + Mips_OR16_MMR6 = 2469, + Mips_OR16_NM = 2470, + Mips_OR64 = 2471, + Mips_ORI_B = 2472, + Mips_ORI_MMR6 = 2473, + Mips_ORI_NM = 2474, + Mips_OR_MM = 2475, + Mips_OR_MMR6 = 2476, + Mips_OR_NM = 2477, + Mips_OR_V = 2478, + Mips_ORi = 2479, + Mips_ORi64 = 2480, + Mips_ORi_MM = 2481, + Mips_OrRxRxRy16 = 2482, + Mips_PACKRL_PH = 2483, + Mips_PACKRL_PH_MM = 2484, + Mips_PAUSE = 2485, + Mips_PAUSE_MM = 2486, + Mips_PAUSE_MMR6 = 2487, + Mips_PAUSE_NM = 2488, + Mips_PCKEV_B = 2489, + Mips_PCKEV_D = 2490, + Mips_PCKEV_H = 2491, + Mips_PCKEV_W = 2492, + Mips_PCKOD_B = 2493, + Mips_PCKOD_D = 2494, + Mips_PCKOD_H = 2495, + Mips_PCKOD_W = 2496, + Mips_PCNT_B = 2497, + Mips_PCNT_D = 2498, + Mips_PCNT_H = 2499, + Mips_PCNT_W = 2500, + Mips_PICK_PH = 2501, + Mips_PICK_PH_MM = 2502, + Mips_PICK_QB = 2503, + Mips_PICK_QB_MM = 2504, + Mips_PLL_PS64 = 2505, + Mips_PLU_PS64 = 2506, + Mips_POP = 2507, + Mips_PRECEQU_PH_QBL = 2508, + Mips_PRECEQU_PH_QBLA = 2509, + Mips_PRECEQU_PH_QBLA_MM = 2510, + Mips_PRECEQU_PH_QBL_MM = 2511, + Mips_PRECEQU_PH_QBR = 2512, + Mips_PRECEQU_PH_QBRA = 2513, + Mips_PRECEQU_PH_QBRA_MM = 2514, + Mips_PRECEQU_PH_QBR_MM = 2515, + Mips_PRECEQ_W_PHL = 2516, + Mips_PRECEQ_W_PHL_MM = 2517, + Mips_PRECEQ_W_PHR = 2518, + Mips_PRECEQ_W_PHR_MM = 2519, + Mips_PRECEU_PH_QBL = 2520, + Mips_PRECEU_PH_QBLA = 2521, + Mips_PRECEU_PH_QBLA_MM = 2522, + Mips_PRECEU_PH_QBL_MM = 2523, + Mips_PRECEU_PH_QBR = 2524, + Mips_PRECEU_PH_QBRA = 2525, + Mips_PRECEU_PH_QBRA_MM = 2526, + Mips_PRECEU_PH_QBR_MM = 2527, + Mips_PRECRQU_S_QB_PH = 2528, + Mips_PRECRQU_S_QB_PH_MM = 2529, + Mips_PRECRQ_PH_W = 2530, + Mips_PRECRQ_PH_W_MM = 2531, + Mips_PRECRQ_QB_PH = 2532, + Mips_PRECRQ_QB_PH_MM = 2533, + Mips_PRECRQ_RS_PH_W = 2534, + Mips_PRECRQ_RS_PH_W_MM = 2535, + Mips_PRECR_QB_PH = 2536, + Mips_PRECR_QB_PH_MMR2 = 2537, + Mips_PRECR_SRA_PH_W = 2538, + Mips_PRECR_SRA_PH_W_MMR2 = 2539, + Mips_PRECR_SRA_R_PH_W = 2540, + Mips_PRECR_SRA_R_PH_W_MMR2 = 2541, + Mips_PREF = 2542, + Mips_PREFE = 2543, + Mips_PREFE_MM = 2544, + Mips_PREFX_MM = 2545, + Mips_PREF_MM = 2546, + Mips_PREF_MMR6 = 2547, + Mips_PREF_NM = 2548, + Mips_PREF_R6 = 2549, + Mips_PREFs9_NM = 2550, + Mips_PREPEND = 2551, + Mips_PREPEND_MMR2 = 2552, + Mips_PUL_PS64 = 2553, + Mips_PUU_PS64 = 2554, + Mips_RADDU_W_QB = 2555, + Mips_RADDU_W_QB_MM = 2556, + Mips_RDDSP = 2557, + Mips_RDDSP_MM = 2558, + Mips_RDHWR = 2559, + Mips_RDHWR64 = 2560, + Mips_RDHWR_MM = 2561, + Mips_RDHWR_MMR6 = 2562, + Mips_RDHWR_NM = 2563, + Mips_RDPGPR_MMR6 = 2564, + Mips_RDPGPR_NM = 2565, + Mips_RECIP_D32 = 2566, + Mips_RECIP_D32_MM = 2567, + Mips_RECIP_D64 = 2568, + Mips_RECIP_D64_MM = 2569, + Mips_RECIP_S = 2570, + Mips_RECIP_S_MM = 2571, + Mips_REPLV_PH = 2572, + Mips_REPLV_PH_MM = 2573, + Mips_REPLV_QB = 2574, + Mips_REPLV_QB_MM = 2575, + Mips_REPL_PH = 2576, + Mips_REPL_PH_MM = 2577, + Mips_REPL_QB = 2578, + Mips_REPL_QB_MM = 2579, + Mips_RESTOREJRC16_NM = 2580, + Mips_RESTOREJRC_NM = 2581, + Mips_RESTORE_NM = 2582, + Mips_RINT_D = 2583, + Mips_RINT_D_MMR6 = 2584, + Mips_RINT_S = 2585, + Mips_RINT_S_MMR6 = 2586, + Mips_ROTR = 2587, + Mips_ROTRV = 2588, + Mips_ROTRV_MM = 2589, + Mips_ROTRV_NM = 2590, + Mips_ROTR_MM = 2591, + Mips_ROTR_NM = 2592, + Mips_ROTX_NM = 2593, + Mips_ROUND_L_D64 = 2594, + Mips_ROUND_L_D_MMR6 = 2595, + Mips_ROUND_L_S = 2596, + Mips_ROUND_L_S_MMR6 = 2597, + Mips_ROUND_W_D32 = 2598, + Mips_ROUND_W_D64 = 2599, + Mips_ROUND_W_D_MMR6 = 2600, + Mips_ROUND_W_MM = 2601, + Mips_ROUND_W_S = 2602, + Mips_ROUND_W_S_MM = 2603, + Mips_ROUND_W_S_MMR6 = 2604, + Mips_RSQRT_D32 = 2605, + Mips_RSQRT_D32_MM = 2606, + Mips_RSQRT_D64 = 2607, + Mips_RSQRT_D64_MM = 2608, + Mips_RSQRT_S = 2609, + Mips_RSQRT_S_MM = 2610, + Mips_Restore16 = 2611, + Mips_RestoreX16 = 2612, + Mips_SAA = 2613, + Mips_SAAD = 2614, + Mips_SAT_S_B = 2615, + Mips_SAT_S_D = 2616, + Mips_SAT_S_H = 2617, + Mips_SAT_S_W = 2618, + Mips_SAT_U_B = 2619, + Mips_SAT_U_D = 2620, + Mips_SAT_U_H = 2621, + Mips_SAT_U_W = 2622, + Mips_SAVE16_NM = 2623, + Mips_SAVE_NM = 2624, + Mips_SB = 2625, + Mips_SB16_MM = 2626, + Mips_SB16_MMR6 = 2627, + Mips_SB16_NM = 2628, + Mips_SB64 = 2629, + Mips_SBE = 2630, + Mips_SBE_MM = 2631, + Mips_SBGP_NM = 2632, + Mips_SBX_NM = 2633, + Mips_SB_MM = 2634, + Mips_SB_MMR6 = 2635, + Mips_SB_NM = 2636, + Mips_SBs9_NM = 2637, + Mips_SC = 2638, + Mips_SC64 = 2639, + Mips_SC64_R6 = 2640, + Mips_SCD = 2641, + Mips_SCD_R6 = 2642, + Mips_SCE = 2643, + Mips_SCE_MM = 2644, + Mips_SCWP_NM = 2645, + Mips_SC_MM = 2646, + Mips_SC_MMR6 = 2647, + Mips_SC_NM = 2648, + Mips_SC_R6 = 2649, + Mips_SD = 2650, + Mips_SDBBP = 2651, + Mips_SDBBP16_MM = 2652, + Mips_SDBBP16_MMR6 = 2653, + Mips_SDBBP16_NM = 2654, + Mips_SDBBP_MM = 2655, + Mips_SDBBP_MMR6 = 2656, + Mips_SDBBP_NM = 2657, + Mips_SDBBP_R6 = 2658, + Mips_SDC1 = 2659, + Mips_SDC164 = 2660, + Mips_SDC1_D64_MMR6 = 2661, + Mips_SDC1_MM_D32 = 2662, + Mips_SDC1_MM_D64 = 2663, + Mips_SDC2 = 2664, + Mips_SDC2_MMR6 = 2665, + Mips_SDC2_R6 = 2666, + Mips_SDC3 = 2667, + Mips_SDIV = 2668, + Mips_SDIV_MM = 2669, + Mips_SDL = 2670, + Mips_SDR = 2671, + Mips_SDXC1 = 2672, + Mips_SDXC164 = 2673, + Mips_SEB = 2674, + Mips_SEB64 = 2675, + Mips_SEB_MM = 2676, + Mips_SEB_NM = 2677, + Mips_SEH = 2678, + Mips_SEH64 = 2679, + Mips_SEH_MM = 2680, + Mips_SEH_NM = 2681, + Mips_SELEQZ = 2682, + Mips_SELEQZ64 = 2683, + Mips_SELEQZ_D = 2684, + Mips_SELEQZ_D_MMR6 = 2685, + Mips_SELEQZ_MMR6 = 2686, + Mips_SELEQZ_S = 2687, + Mips_SELEQZ_S_MMR6 = 2688, + Mips_SELNEZ = 2689, + Mips_SELNEZ64 = 2690, + Mips_SELNEZ_D = 2691, + Mips_SELNEZ_D_MMR6 = 2692, + Mips_SELNEZ_MMR6 = 2693, + Mips_SELNEZ_S = 2694, + Mips_SELNEZ_S_MMR6 = 2695, + Mips_SEL_D = 2696, + Mips_SEL_D_MMR6 = 2697, + Mips_SEL_S = 2698, + Mips_SEL_S_MMR6 = 2699, + Mips_SEQ = 2700, + Mips_SEQI_NM = 2701, + Mips_SEQi = 2702, + Mips_SH = 2703, + Mips_SH16_MM = 2704, + Mips_SH16_MMR6 = 2705, + Mips_SH16_NM = 2706, + Mips_SH64 = 2707, + Mips_SHE = 2708, + Mips_SHE_MM = 2709, + Mips_SHF_B = 2710, + Mips_SHF_H = 2711, + Mips_SHF_W = 2712, + Mips_SHGP_NM = 2713, + Mips_SHILO = 2714, + Mips_SHILOV = 2715, + Mips_SHILOV_MM = 2716, + Mips_SHILO_MM = 2717, + Mips_SHLLV_PH = 2718, + Mips_SHLLV_PH_MM = 2719, + Mips_SHLLV_QB = 2720, + Mips_SHLLV_QB_MM = 2721, + Mips_SHLLV_S_PH = 2722, + Mips_SHLLV_S_PH_MM = 2723, + Mips_SHLLV_S_W = 2724, + Mips_SHLLV_S_W_MM = 2725, + Mips_SHLL_PH = 2726, + Mips_SHLL_PH_MM = 2727, + Mips_SHLL_QB = 2728, + Mips_SHLL_QB_MM = 2729, + Mips_SHLL_S_PH = 2730, + Mips_SHLL_S_PH_MM = 2731, + Mips_SHLL_S_W = 2732, + Mips_SHLL_S_W_MM = 2733, + Mips_SHRAV_PH = 2734, + Mips_SHRAV_PH_MM = 2735, + Mips_SHRAV_QB = 2736, + Mips_SHRAV_QB_MMR2 = 2737, + Mips_SHRAV_R_PH = 2738, + Mips_SHRAV_R_PH_MM = 2739, + Mips_SHRAV_R_QB = 2740, + Mips_SHRAV_R_QB_MMR2 = 2741, + Mips_SHRAV_R_W = 2742, + Mips_SHRAV_R_W_MM = 2743, + Mips_SHRA_PH = 2744, + Mips_SHRA_PH_MM = 2745, + Mips_SHRA_QB = 2746, + Mips_SHRA_QB_MMR2 = 2747, + Mips_SHRA_R_PH = 2748, + Mips_SHRA_R_PH_MM = 2749, + Mips_SHRA_R_QB = 2750, + Mips_SHRA_R_QB_MMR2 = 2751, + Mips_SHRA_R_W = 2752, + Mips_SHRA_R_W_MM = 2753, + Mips_SHRLV_PH = 2754, + Mips_SHRLV_PH_MMR2 = 2755, + Mips_SHRLV_QB = 2756, + Mips_SHRLV_QB_MM = 2757, + Mips_SHRL_PH = 2758, + Mips_SHRL_PH_MMR2 = 2759, + Mips_SHRL_QB = 2760, + Mips_SHRL_QB_MM = 2761, + Mips_SHXS_NM = 2762, + Mips_SHX_NM = 2763, + Mips_SH_MM = 2764, + Mips_SH_MMR6 = 2765, + Mips_SH_NM = 2766, + Mips_SHs9_NM = 2767, + Mips_SIGRIE = 2768, + Mips_SIGRIE_MMR6 = 2769, + Mips_SIGRIE_NM = 2770, + Mips_SLDI_B = 2771, + Mips_SLDI_D = 2772, + Mips_SLDI_H = 2773, + Mips_SLDI_W = 2774, + Mips_SLD_B = 2775, + Mips_SLD_D = 2776, + Mips_SLD_H = 2777, + Mips_SLD_W = 2778, + Mips_SLL = 2779, + Mips_SLL16_MM = 2780, + Mips_SLL16_MMR6 = 2781, + Mips_SLL16_NM = 2782, + Mips_SLL64_32 = 2783, + Mips_SLL64_64 = 2784, + Mips_SLLI_B = 2785, + Mips_SLLI_D = 2786, + Mips_SLLI_H = 2787, + Mips_SLLI_W = 2788, + Mips_SLLV = 2789, + Mips_SLLV_MM = 2790, + Mips_SLLV_NM = 2791, + Mips_SLL_B = 2792, + Mips_SLL_D = 2793, + Mips_SLL_H = 2794, + Mips_SLL_MM = 2795, + Mips_SLL_MMR6 = 2796, + Mips_SLL_NM = 2797, + Mips_SLL_W = 2798, + Mips_SLT = 2799, + Mips_SLT64 = 2800, + Mips_SLTIU_NM = 2801, + Mips_SLTI_NM = 2802, + Mips_SLTU_NM = 2803, + Mips_SLT_MM = 2804, + Mips_SLT_NM = 2805, + Mips_SLTi = 2806, + Mips_SLTi64 = 2807, + Mips_SLTi_MM = 2808, + Mips_SLTiu = 2809, + Mips_SLTiu64 = 2810, + Mips_SLTiu_MM = 2811, + Mips_SLTu = 2812, + Mips_SLTu64 = 2813, + Mips_SLTu_MM = 2814, + Mips_SNE = 2815, + Mips_SNEi = 2816, + Mips_SOV_NM = 2817, + Mips_SPLATI_B = 2818, + Mips_SPLATI_D = 2819, + Mips_SPLATI_H = 2820, + Mips_SPLATI_W = 2821, + Mips_SPLAT_B = 2822, + Mips_SPLAT_D = 2823, + Mips_SPLAT_H = 2824, + Mips_SPLAT_W = 2825, + Mips_SRA = 2826, + Mips_SRAI_B = 2827, + Mips_SRAI_D = 2828, + Mips_SRAI_H = 2829, + Mips_SRAI_W = 2830, + Mips_SRARI_B = 2831, + Mips_SRARI_D = 2832, + Mips_SRARI_H = 2833, + Mips_SRARI_W = 2834, + Mips_SRAR_B = 2835, + Mips_SRAR_D = 2836, + Mips_SRAR_H = 2837, + Mips_SRAR_W = 2838, + Mips_SRAV = 2839, + Mips_SRAV_MM = 2840, + Mips_SRAV_NM = 2841, + Mips_SRA_B = 2842, + Mips_SRA_D = 2843, + Mips_SRA_H = 2844, + Mips_SRA_MM = 2845, + Mips_SRA_NM = 2846, + Mips_SRA_W = 2847, + Mips_SRL = 2848, + Mips_SRL16_MM = 2849, + Mips_SRL16_MMR6 = 2850, + Mips_SRL16_NM = 2851, + Mips_SRLI_B = 2852, + Mips_SRLI_D = 2853, + Mips_SRLI_H = 2854, + Mips_SRLI_W = 2855, + Mips_SRLRI_B = 2856, + Mips_SRLRI_D = 2857, + Mips_SRLRI_H = 2858, + Mips_SRLRI_W = 2859, + Mips_SRLR_B = 2860, + Mips_SRLR_D = 2861, + Mips_SRLR_H = 2862, + Mips_SRLR_W = 2863, + Mips_SRLV = 2864, + Mips_SRLV_MM = 2865, + Mips_SRLV_NM = 2866, + Mips_SRL_B = 2867, + Mips_SRL_D = 2868, + Mips_SRL_H = 2869, + Mips_SRL_MM = 2870, + Mips_SRL_NM = 2871, + Mips_SRL_W = 2872, + Mips_SSNOP = 2873, + Mips_SSNOP_MM = 2874, + Mips_SSNOP_MMR6 = 2875, + Mips_ST_B = 2876, + Mips_ST_D = 2877, + Mips_ST_H = 2878, + Mips_ST_W = 2879, + Mips_SUB = 2880, + Mips_SUBQH_PH = 2881, + Mips_SUBQH_PH_MMR2 = 2882, + Mips_SUBQH_R_PH = 2883, + Mips_SUBQH_R_PH_MMR2 = 2884, + Mips_SUBQH_R_W = 2885, + Mips_SUBQH_R_W_MMR2 = 2886, + Mips_SUBQH_W = 2887, + Mips_SUBQH_W_MMR2 = 2888, + Mips_SUBQ_PH = 2889, + Mips_SUBQ_PH_MM = 2890, + Mips_SUBQ_S_PH = 2891, + Mips_SUBQ_S_PH_MM = 2892, + Mips_SUBQ_S_W = 2893, + Mips_SUBQ_S_W_MM = 2894, + Mips_SUBSUS_U_B = 2895, + Mips_SUBSUS_U_D = 2896, + Mips_SUBSUS_U_H = 2897, + Mips_SUBSUS_U_W = 2898, + Mips_SUBSUU_S_B = 2899, + Mips_SUBSUU_S_D = 2900, + Mips_SUBSUU_S_H = 2901, + Mips_SUBSUU_S_W = 2902, + Mips_SUBS_S_B = 2903, + Mips_SUBS_S_D = 2904, + Mips_SUBS_S_H = 2905, + Mips_SUBS_S_W = 2906, + Mips_SUBS_U_B = 2907, + Mips_SUBS_U_D = 2908, + Mips_SUBS_U_H = 2909, + Mips_SUBS_U_W = 2910, + Mips_SUBU16_MM = 2911, + Mips_SUBU16_MMR6 = 2912, + Mips_SUBUH_QB = 2913, + Mips_SUBUH_QB_MMR2 = 2914, + Mips_SUBUH_R_QB = 2915, + Mips_SUBUH_R_QB_MMR2 = 2916, + Mips_SUBU_MMR6 = 2917, + Mips_SUBU_PH = 2918, + Mips_SUBU_PH_MMR2 = 2919, + Mips_SUBU_QB = 2920, + Mips_SUBU_QB_MM = 2921, + Mips_SUBU_S_PH = 2922, + Mips_SUBU_S_PH_MMR2 = 2923, + Mips_SUBU_S_QB = 2924, + Mips_SUBU_S_QB_MM = 2925, + Mips_SUBVI_B = 2926, + Mips_SUBVI_D = 2927, + Mips_SUBVI_H = 2928, + Mips_SUBVI_W = 2929, + Mips_SUBV_B = 2930, + Mips_SUBV_D = 2931, + Mips_SUBV_H = 2932, + Mips_SUBV_W = 2933, + Mips_SUB_MM = 2934, + Mips_SUB_MMR6 = 2935, + Mips_SUB_NM = 2936, + Mips_SUBu = 2937, + Mips_SUBu16_NM = 2938, + Mips_SUBu_MM = 2939, + Mips_SUBu_NM = 2940, + Mips_SUXC1 = 2941, + Mips_SUXC164 = 2942, + Mips_SUXC1_MM = 2943, + Mips_SW = 2944, + Mips_SW16_MM = 2945, + Mips_SW16_MMR6 = 2946, + Mips_SW16_NM = 2947, + Mips_SW4x4_NM = 2948, + Mips_SW64 = 2949, + Mips_SWC1 = 2950, + Mips_SWC1_MM = 2951, + Mips_SWC2 = 2952, + Mips_SWC2_MMR6 = 2953, + Mips_SWC2_R6 = 2954, + Mips_SWC3 = 2955, + Mips_SWDSP = 2956, + Mips_SWDSP_MM = 2957, + Mips_SWE = 2958, + Mips_SWE_MM = 2959, + Mips_SWGP16_NM = 2960, + Mips_SWGP_NM = 2961, + Mips_SWL = 2962, + Mips_SWL64 = 2963, + Mips_SWLE = 2964, + Mips_SWLE_MM = 2965, + Mips_SWL_MM = 2966, + Mips_SWM16_MM = 2967, + Mips_SWM16_MMR6 = 2968, + Mips_SWM32_MM = 2969, + Mips_SWM_NM = 2970, + Mips_SWPC_NM = 2971, + Mips_SWP_MM = 2972, + Mips_SWR = 2973, + Mips_SWR64 = 2974, + Mips_SWRE = 2975, + Mips_SWRE_MM = 2976, + Mips_SWR_MM = 2977, + Mips_SWSP16_NM = 2978, + Mips_SWSP_MM = 2979, + Mips_SWSP_MMR6 = 2980, + Mips_SWXC1 = 2981, + Mips_SWXC1_MM = 2982, + Mips_SWXS_NM = 2983, + Mips_SWX_NM = 2984, + Mips_SW_MM = 2985, + Mips_SW_MMR6 = 2986, + Mips_SW_NM = 2987, + Mips_SWs9_NM = 2988, + Mips_SYNC = 2989, + Mips_SYNCI = 2990, + Mips_SYNCI_MM = 2991, + Mips_SYNCI_MMR6 = 2992, + Mips_SYNCI_NM = 2993, + Mips_SYNCIs9_NM = 2994, + Mips_SYNC_MM = 2995, + Mips_SYNC_MMR6 = 2996, + Mips_SYNC_NM = 2997, + Mips_SYSCALL = 2998, + Mips_SYSCALL16_NM = 2999, + Mips_SYSCALL_MM = 3000, + Mips_SYSCALL_NM = 3001, + Mips_Save16 = 3002, + Mips_SaveX16 = 3003, + Mips_SbRxRyOffMemX16 = 3004, + Mips_SebRx16 = 3005, + Mips_SehRx16 = 3006, + Mips_ShRxRyOffMemX16 = 3007, + Mips_SllX16 = 3008, + Mips_SllvRxRy16 = 3009, + Mips_SltRxRy16 = 3010, + Mips_SltiRxImm16 = 3011, + Mips_SltiRxImmX16 = 3012, + Mips_SltiuRxImm16 = 3013, + Mips_SltiuRxImmX16 = 3014, + Mips_SltuRxRy16 = 3015, + Mips_SraX16 = 3016, + Mips_SravRxRy16 = 3017, + Mips_SrlX16 = 3018, + Mips_SrlvRxRy16 = 3019, + Mips_SubuRxRyRz16 = 3020, + Mips_SwRxRyOffMemX16 = 3021, + Mips_SwRxSpImmX16 = 3022, + Mips_TEQ = 3023, + Mips_TEQI = 3024, + Mips_TEQI_MM = 3025, + Mips_TEQ_MM = 3026, + Mips_TEQ_NM = 3027, + Mips_TGE = 3028, + Mips_TGEI = 3029, + Mips_TGEIU = 3030, + Mips_TGEIU_MM = 3031, + Mips_TGEI_MM = 3032, + Mips_TGEU = 3033, + Mips_TGEU_MM = 3034, + Mips_TGE_MM = 3035, + Mips_TLBGINV = 3036, + Mips_TLBGINVF = 3037, + Mips_TLBGINVF_MM = 3038, + Mips_TLBGINV_MM = 3039, + Mips_TLBGP = 3040, + Mips_TLBGP_MM = 3041, + Mips_TLBGR = 3042, + Mips_TLBGR_MM = 3043, + Mips_TLBGWI = 3044, + Mips_TLBGWI_MM = 3045, + Mips_TLBGWR = 3046, + Mips_TLBGWR_MM = 3047, + Mips_TLBINV = 3048, + Mips_TLBINVF = 3049, + Mips_TLBINVF_MMR6 = 3050, + Mips_TLBINVF_NM = 3051, + Mips_TLBINV_MMR6 = 3052, + Mips_TLBINV_NM = 3053, + Mips_TLBP = 3054, + Mips_TLBP_MM = 3055, + Mips_TLBP_NM = 3056, + Mips_TLBR = 3057, + Mips_TLBR_MM = 3058, + Mips_TLBR_NM = 3059, + Mips_TLBWI = 3060, + Mips_TLBWI_MM = 3061, + Mips_TLBWI_NM = 3062, + Mips_TLBWR = 3063, + Mips_TLBWR_MM = 3064, + Mips_TLBWR_NM = 3065, + Mips_TLT = 3066, + Mips_TLTI = 3067, + Mips_TLTIU_MM = 3068, + Mips_TLTI_MM = 3069, + Mips_TLTU = 3070, + Mips_TLTU_MM = 3071, + Mips_TLT_MM = 3072, + Mips_TNE = 3073, + Mips_TNEI = 3074, + Mips_TNEI_MM = 3075, + Mips_TNE_MM = 3076, + Mips_TNE_NM = 3077, + Mips_TRUNC_L_D64 = 3078, + Mips_TRUNC_L_D_MMR6 = 3079, + Mips_TRUNC_L_S = 3080, + Mips_TRUNC_L_S_MMR6 = 3081, + Mips_TRUNC_W_D32 = 3082, + Mips_TRUNC_W_D64 = 3083, + Mips_TRUNC_W_D_MMR6 = 3084, + Mips_TRUNC_W_MM = 3085, + Mips_TRUNC_W_S = 3086, + Mips_TRUNC_W_S_MM = 3087, + Mips_TRUNC_W_S_MMR6 = 3088, + Mips_TTLTIU = 3089, + Mips_UALH_NM = 3090, + Mips_UALWM_NM = 3091, + Mips_UALW_NM = 3092, + Mips_UASH_NM = 3093, + Mips_UASWM_NM = 3094, + Mips_UASW_NM = 3095, + Mips_UDIV = 3096, + Mips_UDIV_MM = 3097, + Mips_V3MULU = 3098, + Mips_VMM0 = 3099, + Mips_VMULU = 3100, + Mips_VSHF_B = 3101, + Mips_VSHF_D = 3102, + Mips_VSHF_H = 3103, + Mips_VSHF_W = 3104, + Mips_WAIT = 3105, + Mips_WAIT_MM = 3106, + Mips_WAIT_MMR6 = 3107, + Mips_WAIT_NM = 3108, + Mips_WRDSP = 3109, + Mips_WRDSP_MM = 3110, + Mips_WRPGPR_MMR6 = 3111, + Mips_WRPGPR_NM = 3112, + Mips_WSBH = 3113, + Mips_WSBH_MM = 3114, + Mips_WSBH_MMR6 = 3115, + Mips_XOR = 3116, + Mips_XOR16_MM = 3117, + Mips_XOR16_MMR6 = 3118, + Mips_XOR16_NM = 3119, + Mips_XOR64 = 3120, + Mips_XORI_B = 3121, + Mips_XORI_MMR6 = 3122, + Mips_XORI_NM = 3123, + Mips_XOR_MM = 3124, + Mips_XOR_MMR6 = 3125, + Mips_XOR_NM = 3126, + Mips_XOR_V = 3127, + Mips_XORi = 3128, + Mips_XORi64 = 3129, + Mips_XORi_MM = 3130, + Mips_XorRxRxRy16 = 3131, + Mips_YIELD = 3132, + Mips_YIELD_NM = 3133, + INSTRUCTION_LIST_END = 3134 + }; #endif // GET_INSTRINFO_ENUM + +#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) +typedef struct MipsInstrTable { + MCInstrDesc Insts[3134]; + MCOperandInfo OperandInfo[1301]; + MCPhysReg ImplicitOps[70]; +} MipsInstrTable; + +#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) + +#ifdef GET_INSTRINFO_MC_DESC +#undef GET_INSTRINFO_MC_DESC + +static const unsigned MipsImpOpBase = sizeof(MCOperandInfo) / (sizeof(MCPhysReg)); + +static const MipsInstrTable MipsDescs = { + { + { 2, &MipsDescs.OperandInfo[416] }, // Inst #3133 = YIELD_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #3132 = YIELD + { 3, &MipsDescs.OperandInfo[626] }, // Inst #3131 = XorRxRxRy16 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3130 = XORi_MM + { 3, &MipsDescs.OperandInfo[224] }, // Inst #3129 = XORi64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3128 = XORi + { 3, &MipsDescs.OperandInfo[578] }, // Inst #3127 = XOR_V + { 3, &MipsDescs.OperandInfo[596] }, // Inst #3126 = XOR_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #3125 = XOR_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #3124 = XOR_MM + { 3, &MipsDescs.OperandInfo[391] }, // Inst #3123 = XORI_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3122 = XORI_MMR6 + { 3, &MipsDescs.OperandInfo[584] }, // Inst #3121 = XORI_B + { 3, &MipsDescs.OperandInfo[227] }, // Inst #3120 = XOR64 + { 3, &MipsDescs.OperandInfo[599] }, // Inst #3119 = XOR16_NM + { 3, &MipsDescs.OperandInfo[611] }, // Inst #3118 = XOR16_MMR6 + { 3, &MipsDescs.OperandInfo[611] }, // Inst #3117 = XOR16_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #3116 = XOR + { 2, &MipsDescs.OperandInfo[140] }, // Inst #3115 = WSBH_MMR6 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #3114 = WSBH_MM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #3113 = WSBH + { 2, &MipsDescs.OperandInfo[416] }, // Inst #3112 = WRPGPR_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #3111 = WRPGPR_MMR6 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3110 = WRDSP_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3109 = WRDSP + { 1, &MipsDescs.OperandInfo[0] }, // Inst #3108 = WAIT_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #3107 = WAIT_MMR6 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #3106 = WAIT_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3105 = WAIT + { 4, &MipsDescs.OperandInfo[194] }, // Inst #3104 = VSHF_W + { 4, &MipsDescs.OperandInfo[198] }, // Inst #3103 = VSHF_H + { 4, &MipsDescs.OperandInfo[190] }, // Inst #3102 = VSHF_D + { 4, &MipsDescs.OperandInfo[672] }, // Inst #3101 = VSHF_B + { 3, &MipsDescs.OperandInfo[227] }, // Inst #3100 = VMULU + { 3, &MipsDescs.OperandInfo[227] }, // Inst #3099 = VMM0 + { 3, &MipsDescs.OperandInfo[227] }, // Inst #3098 = V3MULU + { 2, &MipsDescs.OperandInfo[140] }, // Inst #3097 = UDIV_MM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #3096 = UDIV + { 3, &MipsDescs.OperandInfo[928] }, // Inst #3095 = UASW_NM + { 4, &MipsDescs.OperandInfo[1010] }, // Inst #3094 = UASWM_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #3093 = UASH_NM + { 4, &MipsDescs.OperandInfo[1297] }, // Inst #3092 = UALW_NM + { 4, &MipsDescs.OperandInfo[1010] }, // Inst #3091 = UALWM_NM + { 4, &MipsDescs.OperandInfo[1297] }, // Inst #3090 = UALH_NM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3089 = TTLTIU + { 2, &MipsDescs.OperandInfo[699] }, // Inst #3088 = TRUNC_W_S_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #3087 = TRUNC_W_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #3086 = TRUNC_W_S + { 2, &MipsDescs.OperandInfo[695] }, // Inst #3085 = TRUNC_W_MM + { 2, &MipsDescs.OperandInfo[697] }, // Inst #3084 = TRUNC_W_D_MMR6 + { 2, &MipsDescs.OperandInfo[697] }, // Inst #3083 = TRUNC_W_D64 + { 2, &MipsDescs.OperandInfo[695] }, // Inst #3082 = TRUNC_W_D32 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #3081 = TRUNC_L_S_MMR6 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #3080 = TRUNC_L_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #3079 = TRUNC_L_D_MMR6 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #3078 = TRUNC_L_D64 + { 3, &MipsDescs.OperandInfo[391] }, // Inst #3077 = TNE_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3076 = TNE_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3075 = TNEI_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3074 = TNEI + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3073 = TNE + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3072 = TLT_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3071 = TLTU_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3070 = TLTU + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3069 = TLTI_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3068 = TLTIU_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3067 = TLTI + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3066 = TLT + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3065 = TLBWR_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3064 = TLBWR_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3063 = TLBWR + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3062 = TLBWI_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3061 = TLBWI_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3060 = TLBWI + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3059 = TLBR_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3058 = TLBR_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3057 = TLBR + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3056 = TLBP_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3055 = TLBP_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3054 = TLBP + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3053 = TLBINV_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3052 = TLBINV_MMR6 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3051 = TLBINVF_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3050 = TLBINVF_MMR6 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3049 = TLBINVF + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3048 = TLBINV + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3047 = TLBGWR_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3046 = TLBGWR + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3045 = TLBGWI_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3044 = TLBGWI + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3043 = TLBGR_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3042 = TLBGR + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3041 = TLBGP_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3040 = TLBGP + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3039 = TLBGINV_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3038 = TLBGINVF_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3037 = TLBGINVF + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3036 = TLBGINV + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3035 = TGE_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3034 = TGEU_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3033 = TGEU + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3032 = TGEI_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3031 = TGEIU_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3030 = TGEIU + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3029 = TGEI + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3028 = TGE + { 3, &MipsDescs.OperandInfo[391] }, // Inst #3027 = TEQ_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3026 = TEQ_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3025 = TEQI_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #3024 = TEQI + { 3, &MipsDescs.OperandInfo[233] }, // Inst #3023 = TEQ + { 3, &MipsDescs.OperandInfo[623] }, // Inst #3022 = SwRxSpImmX16 + { 3, &MipsDescs.OperandInfo[1027] }, // Inst #3021 = SwRxRyOffMemX16 + { 3, &MipsDescs.OperandInfo[421] }, // Inst #3020 = SubuRxRyRz16 + { 3, &MipsDescs.OperandInfo[626] }, // Inst #3019 = SrlvRxRy16 + { 3, &MipsDescs.OperandInfo[547] }, // Inst #3018 = SrlX16 + { 3, &MipsDescs.OperandInfo[626] }, // Inst #3017 = SravRxRy16 + { 3, &MipsDescs.OperandInfo[547] }, // Inst #3016 = SraX16 + { 2, &MipsDescs.OperandInfo[419] }, // Inst #3015 = SltuRxRy16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #3014 = SltiuRxImmX16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #3013 = SltiuRxImm16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #3012 = SltiRxImmX16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #3011 = SltiRxImm16 + { 2, &MipsDescs.OperandInfo[419] }, // Inst #3010 = SltRxRy16 + { 3, &MipsDescs.OperandInfo[626] }, // Inst #3009 = SllvRxRy16 + { 3, &MipsDescs.OperandInfo[547] }, // Inst #3008 = SllX16 + { 3, &MipsDescs.OperandInfo[1027] }, // Inst #3007 = ShRxRyOffMemX16 + { 2, &MipsDescs.OperandInfo[1295] }, // Inst #3006 = SehRx16 + { 2, &MipsDescs.OperandInfo[1295] }, // Inst #3005 = SebRx16 + { 3, &MipsDescs.OperandInfo[1027] }, // Inst #3004 = SbRxRyOffMemX16 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3003 = SaveX16 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #3002 = Save16 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #3001 = SYSCALL_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #3000 = SYSCALL_MM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2999 = SYSCALL16_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2998 = SYSCALL + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2997 = SYNC_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2996 = SYNC_MMR6 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2995 = SYNC_MM + { 2, &MipsDescs.OperandInfo[1293] }, // Inst #2994 = SYNCIs9_NM + { 2, &MipsDescs.OperandInfo[1293] }, // Inst #2993 = SYNCI_NM + { 2, &MipsDescs.OperandInfo[1293] }, // Inst #2992 = SYNCI_MMR6 + { 2, &MipsDescs.OperandInfo[1293] }, // Inst #2991 = SYNCI_MM + { 2, &MipsDescs.OperandInfo[1293] }, // Inst #2990 = SYNCI + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2989 = SYNC + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2988 = SWs9_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2987 = SW_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2986 = SW_MMR6 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2985 = SW_MM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2984 = SWX_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2983 = SWXS_NM + { 3, &MipsDescs.OperandInfo[1024] }, // Inst #2982 = SWXC1_MM + { 3, &MipsDescs.OperandInfo[1024] }, // Inst #2981 = SWXC1 + { 3, &MipsDescs.OperandInfo[1021] }, // Inst #2980 = SWSP_MMR6 + { 3, &MipsDescs.OperandInfo[1021] }, // Inst #2979 = SWSP_MM + { 3, &MipsDescs.OperandInfo[1018] }, // Inst #2978 = SWSP16_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2977 = SWR_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2976 = SWRE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2975 = SWRE + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2974 = SWR64 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2973 = SWR + { 4, &MipsDescs.OperandInfo[1014] }, // Inst #2972 = SWP_MM + { 2, &MipsDescs.OperandInfo[609] }, // Inst #2971 = SWPC_NM + { 4, &MipsDescs.OperandInfo[1010] }, // Inst #2970 = SWM_NM + { 3, &MipsDescs.OperandInfo[354] }, // Inst #2969 = SWM32_MM + { 3, &MipsDescs.OperandInfo[1007] }, // Inst #2968 = SWM16_MMR6 + { 3, &MipsDescs.OperandInfo[1007] }, // Inst #2967 = SWM16_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2966 = SWL_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2965 = SWLE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2964 = SWLE + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2963 = SWL64 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2962 = SWL + { 3, &MipsDescs.OperandInfo[1000] }, // Inst #2961 = SWGP_NM + { 3, &MipsDescs.OperandInfo[1290] }, // Inst #2960 = SWGP16_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2959 = SWE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2958 = SWE + { 3, &MipsDescs.OperandInfo[991] }, // Inst #2957 = SWDSP_MM + { 3, &MipsDescs.OperandInfo[991] }, // Inst #2956 = SWDSP + { 3, &MipsDescs.OperandInfo[940] }, // Inst #2955 = SWC3 + { 3, &MipsDescs.OperandInfo[934] }, // Inst #2954 = SWC2_R6 + { 3, &MipsDescs.OperandInfo[937] }, // Inst #2953 = SWC2_MMR6 + { 3, &MipsDescs.OperandInfo[934] }, // Inst #2952 = SWC2 + { 3, &MipsDescs.OperandInfo[988] }, // Inst #2951 = SWC1_MM + { 3, &MipsDescs.OperandInfo[988] }, // Inst #2950 = SWC1 + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2949 = SW64 + { 3, &MipsDescs.OperandInfo[1287] }, // Inst #2948 = SW4x4_NM + { 3, &MipsDescs.OperandInfo[1212] }, // Inst #2947 = SW16_NM + { 3, &MipsDescs.OperandInfo[1209] }, // Inst #2946 = SW16_MMR6 + { 3, &MipsDescs.OperandInfo[1209] }, // Inst #2945 = SW16_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2944 = SW + { 3, &MipsDescs.OperandInfo[958] }, // Inst #2943 = SUXC1_MM + { 3, &MipsDescs.OperandInfo[958] }, // Inst #2942 = SUXC164 + { 3, &MipsDescs.OperandInfo[955] }, // Inst #2941 = SUXC1 + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2940 = SUBu_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2939 = SUBu_MM + { 3, &MipsDescs.OperandInfo[599] }, // Inst #2938 = SUBu16_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2937 = SUBu + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2936 = SUB_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2935 = SUB_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2934 = SUB_MM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2933 = SUBV_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2932 = SUBV_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2931 = SUBV_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2930 = SUBV_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2929 = SUBVI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2928 = SUBVI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2927 = SUBVI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2926 = SUBVI_B + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2925 = SUBU_S_QB_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2924 = SUBU_S_QB + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2923 = SUBU_S_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2922 = SUBU_S_PH + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2921 = SUBU_QB_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2920 = SUBU_QB + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2919 = SUBU_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2918 = SUBU_PH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2917 = SUBU_MMR6 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2916 = SUBUH_R_QB_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2915 = SUBUH_R_QB + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2914 = SUBUH_QB_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2913 = SUBUH_QB + { 3, &MipsDescs.OperandInfo[581] }, // Inst #2912 = SUBU16_MMR6 + { 3, &MipsDescs.OperandInfo[581] }, // Inst #2911 = SUBU16_MM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2910 = SUBS_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2909 = SUBS_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2908 = SUBS_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2907 = SUBS_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2906 = SUBS_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2905 = SUBS_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2904 = SUBS_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2903 = SUBS_S_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2902 = SUBSUU_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2901 = SUBSUU_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2900 = SUBSUU_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2899 = SUBSUU_S_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2898 = SUBSUS_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2897 = SUBSUS_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2896 = SUBSUS_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2895 = SUBSUS_U_B + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2894 = SUBQ_S_W_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2893 = SUBQ_S_W + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2892 = SUBQ_S_PH_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2891 = SUBQ_S_PH + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2890 = SUBQ_PH_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2889 = SUBQ_PH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2888 = SUBQH_W_MMR2 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2887 = SUBQH_W + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2886 = SUBQH_R_W_MMR2 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2885 = SUBQH_R_W + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2884 = SUBQH_R_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2883 = SUBQH_R_PH + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2882 = SUBQH_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2881 = SUBQH_PH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2880 = SUB + { 3, &MipsDescs.OperandInfo[970] }, // Inst #2879 = ST_W + { 3, &MipsDescs.OperandInfo[967] }, // Inst #2878 = ST_H + { 3, &MipsDescs.OperandInfo[964] }, // Inst #2877 = ST_D + { 3, &MipsDescs.OperandInfo[961] }, // Inst #2876 = ST_B + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2875 = SSNOP_MMR6 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2874 = SSNOP_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2873 = SSNOP + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2872 = SRL_W + { 3, &MipsDescs.OperandInfo[391] }, // Inst #2871 = SRL_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2870 = SRL_MM + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2869 = SRL_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2868 = SRL_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2867 = SRL_B + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2866 = SRLV_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2865 = SRLV_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2864 = SRLV + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2863 = SRLR_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2862 = SRLR_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2861 = SRLR_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2860 = SRLR_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2859 = SRLRI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2858 = SRLRI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2857 = SRLRI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2856 = SRLRI_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2855 = SRLI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2854 = SRLI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2853 = SRLI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2852 = SRLI_B + { 3, &MipsDescs.OperandInfo[566] }, // Inst #2851 = SRL16_NM + { 3, &MipsDescs.OperandInfo[563] }, // Inst #2850 = SRL16_MMR6 + { 3, &MipsDescs.OperandInfo[563] }, // Inst #2849 = SRL16_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2848 = SRL + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2847 = SRA_W + { 3, &MipsDescs.OperandInfo[391] }, // Inst #2846 = SRA_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2845 = SRA_MM + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2844 = SRA_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2843 = SRA_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2842 = SRA_B + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2841 = SRAV_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2840 = SRAV_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2839 = SRAV + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2838 = SRAR_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2837 = SRAR_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2836 = SRAR_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2835 = SRAR_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2834 = SRARI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2833 = SRARI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2832 = SRARI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2831 = SRARI_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2830 = SRAI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2829 = SRAI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2828 = SRAI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2827 = SRAI_B + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2826 = SRA + { 3, &MipsDescs.OperandInfo[1284] }, // Inst #2825 = SPLAT_W + { 3, &MipsDescs.OperandInfo[1281] }, // Inst #2824 = SPLAT_H + { 3, &MipsDescs.OperandInfo[1278] }, // Inst #2823 = SPLAT_D + { 3, &MipsDescs.OperandInfo[1275] }, // Inst #2822 = SPLAT_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2821 = SPLATI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2820 = SPLATI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2819 = SPLATI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2818 = SPLATI_B + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2817 = SOV_NM + { 3, &MipsDescs.OperandInfo[224] }, // Inst #2816 = SNEi + { 3, &MipsDescs.OperandInfo[227] }, // Inst #2815 = SNE + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2814 = SLTu_MM + { 3, &MipsDescs.OperandInfo[1269] }, // Inst #2813 = SLTu64 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2812 = SLTu + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2811 = SLTiu_MM + { 3, &MipsDescs.OperandInfo[1272] }, // Inst #2810 = SLTiu64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2809 = SLTiu + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2808 = SLTi_MM + { 3, &MipsDescs.OperandInfo[1272] }, // Inst #2807 = SLTi64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2806 = SLTi + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2805 = SLT_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2804 = SLT_MM + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2803 = SLTU_NM + { 3, &MipsDescs.OperandInfo[391] }, // Inst #2802 = SLTI_NM + { 3, &MipsDescs.OperandInfo[391] }, // Inst #2801 = SLTIU_NM + { 3, &MipsDescs.OperandInfo[1269] }, // Inst #2800 = SLT64 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2799 = SLT + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2798 = SLL_W + { 3, &MipsDescs.OperandInfo[391] }, // Inst #2797 = SLL_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2796 = SLL_MMR6 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2795 = SLL_MM + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2794 = SLL_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2793 = SLL_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2792 = SLL_B + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2791 = SLLV_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2790 = SLLV_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2789 = SLLV + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2788 = SLLI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2787 = SLLI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2786 = SLLI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2785 = SLLI_B + { 2, &MipsDescs.OperandInfo[394] }, // Inst #2784 = SLL64_64 + { 2, &MipsDescs.OperandInfo[817] }, // Inst #2783 = SLL64_32 + { 3, &MipsDescs.OperandInfo[566] }, // Inst #2782 = SLL16_NM + { 3, &MipsDescs.OperandInfo[563] }, // Inst #2781 = SLL16_MMR6 + { 3, &MipsDescs.OperandInfo[563] }, // Inst #2780 = SLL16_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2779 = SLL + { 4, &MipsDescs.OperandInfo[1265] }, // Inst #2778 = SLD_W + { 4, &MipsDescs.OperandInfo[1261] }, // Inst #2777 = SLD_H + { 4, &MipsDescs.OperandInfo[1257] }, // Inst #2776 = SLD_D + { 4, &MipsDescs.OperandInfo[1253] }, // Inst #2775 = SLD_B + { 4, &MipsDescs.OperandInfo[668] }, // Inst #2774 = SLDI_W + { 4, &MipsDescs.OperandInfo[664] }, // Inst #2773 = SLDI_H + { 4, &MipsDescs.OperandInfo[660] }, // Inst #2772 = SLDI_D + { 4, &MipsDescs.OperandInfo[656] }, // Inst #2771 = SLDI_B + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2770 = SIGRIE_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2769 = SIGRIE_MMR6 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2768 = SIGRIE + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2767 = SHs9_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2766 = SH_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2765 = SH_MMR6 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2764 = SH_MM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2763 = SHX_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2762 = SHXS_NM + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2761 = SHRL_QB_MM + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2760 = SHRL_QB + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2759 = SHRL_PH_MMR2 + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2758 = SHRL_PH + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2757 = SHRLV_QB_MM + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2756 = SHRLV_QB + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2755 = SHRLV_PH_MMR2 + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2754 = SHRLV_PH + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2753 = SHRA_R_W_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2752 = SHRA_R_W + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2751 = SHRA_R_QB_MMR2 + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2750 = SHRA_R_QB + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2749 = SHRA_R_PH_MM + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2748 = SHRA_R_PH + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2747 = SHRA_QB_MMR2 + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2746 = SHRA_QB + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2745 = SHRA_PH_MM + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2744 = SHRA_PH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2743 = SHRAV_R_W_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2742 = SHRAV_R_W + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2741 = SHRAV_R_QB_MMR2 + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2740 = SHRAV_R_QB + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2739 = SHRAV_R_PH_MM + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2738 = SHRAV_R_PH + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2737 = SHRAV_QB_MMR2 + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2736 = SHRAV_QB + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2735 = SHRAV_PH_MM + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2734 = SHRAV_PH + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2733 = SHLL_S_W_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2732 = SHLL_S_W + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2731 = SHLL_S_PH_MM + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2730 = SHLL_S_PH + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2729 = SHLL_QB_MM + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2728 = SHLL_QB + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2727 = SHLL_PH_MM + { 3, &MipsDescs.OperandInfo[1250] }, // Inst #2726 = SHLL_PH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2725 = SHLLV_S_W_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2724 = SHLLV_S_W + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2723 = SHLLV_S_PH_MM + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2722 = SHLLV_S_PH + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2721 = SHLLV_QB_MM + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2720 = SHLLV_QB + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2719 = SHLLV_PH_MM + { 3, &MipsDescs.OperandInfo[1247] }, // Inst #2718 = SHLLV_PH + { 3, &MipsDescs.OperandInfo[1244] }, // Inst #2717 = SHILO_MM + { 3, &MipsDescs.OperandInfo[1160] }, // Inst #2716 = SHILOV_MM + { 3, &MipsDescs.OperandInfo[1160] }, // Inst #2715 = SHILOV + { 3, &MipsDescs.OperandInfo[1244] }, // Inst #2714 = SHILO + { 3, &MipsDescs.OperandInfo[919] }, // Inst #2713 = SHGP_NM + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2712 = SHF_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2711 = SHF_H + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2710 = SHF_B + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2709 = SHE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2708 = SHE + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2707 = SH64 + { 3, &MipsDescs.OperandInfo[1212] }, // Inst #2706 = SH16_NM + { 3, &MipsDescs.OperandInfo[1209] }, // Inst #2705 = SH16_MMR6 + { 3, &MipsDescs.OperandInfo[1209] }, // Inst #2704 = SH16_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2703 = SH + { 3, &MipsDescs.OperandInfo[224] }, // Inst #2702 = SEQi + { 3, &MipsDescs.OperandInfo[391] }, // Inst #2701 = SEQI_NM + { 3, &MipsDescs.OperandInfo[227] }, // Inst #2700 = SEQ + { 4, &MipsDescs.OperandInfo[1240] }, // Inst #2699 = SEL_S_MMR6 + { 4, &MipsDescs.OperandInfo[1240] }, // Inst #2698 = SEL_S + { 4, &MipsDescs.OperandInfo[1033] }, // Inst #2697 = SEL_D_MMR6 + { 4, &MipsDescs.OperandInfo[1033] }, // Inst #2696 = SEL_D + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2695 = SELNEZ_S_MMR6 + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2694 = SELNEZ_S + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2693 = SELNEZ_MMR6 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2692 = SELNEZ_D_MMR6 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2691 = SELNEZ_D + { 3, &MipsDescs.OperandInfo[227] }, // Inst #2690 = SELNEZ64 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2689 = SELNEZ + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2688 = SELEQZ_S_MMR6 + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2687 = SELEQZ_S + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2686 = SELEQZ_MMR6 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2685 = SELEQZ_D_MMR6 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2684 = SELEQZ_D + { 3, &MipsDescs.OperandInfo[227] }, // Inst #2683 = SELEQZ64 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2682 = SELEQZ + { 2, &MipsDescs.OperandInfo[416] }, // Inst #2681 = SEH_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2680 = SEH_MM + { 2, &MipsDescs.OperandInfo[394] }, // Inst #2679 = SEH64 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2678 = SEH + { 2, &MipsDescs.OperandInfo[416] }, // Inst #2677 = SEB_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2676 = SEB_MM + { 2, &MipsDescs.OperandInfo[394] }, // Inst #2675 = SEB64 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2674 = SEB + { 3, &MipsDescs.OperandInfo[958] }, // Inst #2673 = SDXC164 + { 3, &MipsDescs.OperandInfo[955] }, // Inst #2672 = SDXC1 + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2671 = SDR + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2670 = SDL + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2669 = SDIV_MM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2668 = SDIV + { 3, &MipsDescs.OperandInfo[940] }, // Inst #2667 = SDC3 + { 3, &MipsDescs.OperandInfo[934] }, // Inst #2666 = SDC2_R6 + { 3, &MipsDescs.OperandInfo[937] }, // Inst #2665 = SDC2_MMR6 + { 3, &MipsDescs.OperandInfo[934] }, // Inst #2664 = SDC2 + { 3, &MipsDescs.OperandInfo[931] }, // Inst #2663 = SDC1_MM_D64 + { 3, &MipsDescs.OperandInfo[519] }, // Inst #2662 = SDC1_MM_D32 + { 3, &MipsDescs.OperandInfo[931] }, // Inst #2661 = SDC1_D64_MMR6 + { 3, &MipsDescs.OperandInfo[931] }, // Inst #2660 = SDC164 + { 3, &MipsDescs.OperandInfo[519] }, // Inst #2659 = SDC1 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2658 = SDBBP_R6 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2657 = SDBBP_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2656 = SDBBP_MMR6 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2655 = SDBBP_MM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2654 = SDBBP16_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2653 = SDBBP16_MMR6 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2652 = SDBBP16_MM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #2651 = SDBBP + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2650 = SD + { 4, &MipsDescs.OperandInfo[1219] }, // Inst #2649 = SC_R6 + { 4, &MipsDescs.OperandInfo[1236] }, // Inst #2648 = SC_NM + { 4, &MipsDescs.OperandInfo[1215] }, // Inst #2647 = SC_MMR6 + { 4, &MipsDescs.OperandInfo[1215] }, // Inst #2646 = SC_MM + { 5, &MipsDescs.OperandInfo[1231] }, // Inst #2645 = SCWP_NM + { 4, &MipsDescs.OperandInfo[1215] }, // Inst #2644 = SCE_MM + { 4, &MipsDescs.OperandInfo[1215] }, // Inst #2643 = SCE + { 4, &MipsDescs.OperandInfo[1227] }, // Inst #2642 = SCD_R6 + { 4, &MipsDescs.OperandInfo[1223] }, // Inst #2641 = SCD + { 4, &MipsDescs.OperandInfo[1219] }, // Inst #2640 = SC64_R6 + { 4, &MipsDescs.OperandInfo[1215] }, // Inst #2639 = SC64 + { 4, &MipsDescs.OperandInfo[1215] }, // Inst #2638 = SC + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2637 = SBs9_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2636 = SB_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2635 = SB_MMR6 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2634 = SB_MM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2633 = SBX_NM + { 3, &MipsDescs.OperandInfo[919] }, // Inst #2632 = SBGP_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2631 = SBE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2630 = SBE + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2629 = SB64 + { 3, &MipsDescs.OperandInfo[1212] }, // Inst #2628 = SB16_NM + { 3, &MipsDescs.OperandInfo[1209] }, // Inst #2627 = SB16_MMR6 + { 3, &MipsDescs.OperandInfo[1209] }, // Inst #2626 = SB16_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2625 = SB + { 2, &MipsDescs.OperandInfo[1202] }, // Inst #2624 = SAVE_NM + { 2, &MipsDescs.OperandInfo[1202] }, // Inst #2623 = SAVE16_NM + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2622 = SAT_U_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2621 = SAT_U_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2620 = SAT_U_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2619 = SAT_U_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2618 = SAT_S_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2617 = SAT_S_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2616 = SAT_S_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2615 = SAT_S_B + { 2, &MipsDescs.OperandInfo[394] }, // Inst #2614 = SAAD + { 2, &MipsDescs.OperandInfo[394] }, // Inst #2613 = SAA + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2612 = RestoreX16 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2611 = Restore16 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #2610 = RSQRT_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #2609 = RSQRT_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #2608 = RSQRT_D64_MM + { 2, &MipsDescs.OperandInfo[691] }, // Inst #2607 = RSQRT_D64 + { 2, &MipsDescs.OperandInfo[829] }, // Inst #2606 = RSQRT_D32_MM + { 2, &MipsDescs.OperandInfo[829] }, // Inst #2605 = RSQRT_D32 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #2604 = ROUND_W_S_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #2603 = ROUND_W_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #2602 = ROUND_W_S + { 2, &MipsDescs.OperandInfo[695] }, // Inst #2601 = ROUND_W_MM + { 2, &MipsDescs.OperandInfo[691] }, // Inst #2600 = ROUND_W_D_MMR6 + { 2, &MipsDescs.OperandInfo[697] }, // Inst #2599 = ROUND_W_D64 + { 2, &MipsDescs.OperandInfo[695] }, // Inst #2598 = ROUND_W_D32 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #2597 = ROUND_L_S_MMR6 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #2596 = ROUND_L_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #2595 = ROUND_L_D_MMR6 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #2594 = ROUND_L_D64 + { 5, &MipsDescs.OperandInfo[1204] }, // Inst #2593 = ROTX_NM + { 3, &MipsDescs.OperandInfo[391] }, // Inst #2592 = ROTR_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2591 = ROTR_MM + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2590 = ROTRV_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2589 = ROTRV_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2588 = ROTRV + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2587 = ROTR + { 2, &MipsDescs.OperandInfo[699] }, // Inst #2586 = RINT_S_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #2585 = RINT_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #2584 = RINT_D_MMR6 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #2583 = RINT_D + { 2, &MipsDescs.OperandInfo[1202] }, // Inst #2582 = RESTORE_NM + { 2, &MipsDescs.OperandInfo[1202] }, // Inst #2581 = RESTOREJRC_NM + { 2, &MipsDescs.OperandInfo[1202] }, // Inst #2580 = RESTOREJRC16_NM + { 2, &MipsDescs.OperandInfo[1200] }, // Inst #2579 = REPL_QB_MM + { 2, &MipsDescs.OperandInfo[1200] }, // Inst #2578 = REPL_QB + { 2, &MipsDescs.OperandInfo[1200] }, // Inst #2577 = REPL_PH_MM + { 2, &MipsDescs.OperandInfo[1200] }, // Inst #2576 = REPL_PH + { 2, &MipsDescs.OperandInfo[1198] }, // Inst #2575 = REPLV_QB_MM + { 2, &MipsDescs.OperandInfo[1198] }, // Inst #2574 = REPLV_QB + { 2, &MipsDescs.OperandInfo[1198] }, // Inst #2573 = REPLV_PH_MM + { 2, &MipsDescs.OperandInfo[1198] }, // Inst #2572 = REPLV_PH + { 2, &MipsDescs.OperandInfo[699] }, // Inst #2571 = RECIP_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #2570 = RECIP_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #2569 = RECIP_D64_MM + { 2, &MipsDescs.OperandInfo[691] }, // Inst #2568 = RECIP_D64 + { 2, &MipsDescs.OperandInfo[829] }, // Inst #2567 = RECIP_D32_MM + { 2, &MipsDescs.OperandInfo[829] }, // Inst #2566 = RECIP_D32 + { 2, &MipsDescs.OperandInfo[416] }, // Inst #2565 = RDPGPR_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2564 = RDPGPR_MMR6 + { 3, &MipsDescs.OperandInfo[386] }, // Inst #2563 = RDHWR_NM + { 3, &MipsDescs.OperandInfo[1192] }, // Inst #2562 = RDHWR_MMR6 + { 3, &MipsDescs.OperandInfo[1192] }, // Inst #2561 = RDHWR_MM + { 3, &MipsDescs.OperandInfo[1195] }, // Inst #2560 = RDHWR64 + { 3, &MipsDescs.OperandInfo[1192] }, // Inst #2559 = RDHWR + { 2, &MipsDescs.OperandInfo[364] }, // Inst #2558 = RDDSP_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #2557 = RDDSP + { 2, &MipsDescs.OperandInfo[1180] }, // Inst #2556 = RADDU_W_QB_MM + { 2, &MipsDescs.OperandInfo[1180] }, // Inst #2555 = RADDU_W_QB + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2554 = PUU_PS64 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2553 = PUL_PS64 + { 4, &MipsDescs.OperandInfo[614] }, // Inst #2552 = PREPEND_MMR2 + { 4, &MipsDescs.OperandInfo[614] }, // Inst #2551 = PREPEND + { 3, &MipsDescs.OperandInfo[354] }, // Inst #2550 = PREFs9_NM + { 3, &MipsDescs.OperandInfo[688] }, // Inst #2549 = PREF_R6 + { 3, &MipsDescs.OperandInfo[354] }, // Inst #2548 = PREF_NM + { 3, &MipsDescs.OperandInfo[688] }, // Inst #2547 = PREF_MMR6 + { 3, &MipsDescs.OperandInfo[688] }, // Inst #2546 = PREF_MM + { 3, &MipsDescs.OperandInfo[1189] }, // Inst #2545 = PREFX_MM + { 3, &MipsDescs.OperandInfo[688] }, // Inst #2544 = PREFE_MM + { 3, &MipsDescs.OperandInfo[688] }, // Inst #2543 = PREFE + { 3, &MipsDescs.OperandInfo[688] }, // Inst #2542 = PREF + { 4, &MipsDescs.OperandInfo[1185] }, // Inst #2541 = PRECR_SRA_R_PH_W_MMR2 + { 4, &MipsDescs.OperandInfo[1185] }, // Inst #2540 = PRECR_SRA_R_PH_W + { 4, &MipsDescs.OperandInfo[1185] }, // Inst #2539 = PRECR_SRA_PH_W_MMR2 + { 4, &MipsDescs.OperandInfo[1185] }, // Inst #2538 = PRECR_SRA_PH_W + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2537 = PRECR_QB_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2536 = PRECR_QB_PH + { 3, &MipsDescs.OperandInfo[1182] }, // Inst #2535 = PRECRQ_RS_PH_W_MM + { 3, &MipsDescs.OperandInfo[1182] }, // Inst #2534 = PRECRQ_RS_PH_W + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2533 = PRECRQ_QB_PH_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2532 = PRECRQ_QB_PH + { 3, &MipsDescs.OperandInfo[1182] }, // Inst #2531 = PRECRQ_PH_W_MM + { 3, &MipsDescs.OperandInfo[1182] }, // Inst #2530 = PRECRQ_PH_W + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2529 = PRECRQU_S_QB_PH_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2528 = PRECRQU_S_QB_PH + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2527 = PRECEU_PH_QBR_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2526 = PRECEU_PH_QBRA_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2525 = PRECEU_PH_QBRA + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2524 = PRECEU_PH_QBR + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2523 = PRECEU_PH_QBL_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2522 = PRECEU_PH_QBLA_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2521 = PRECEU_PH_QBLA + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2520 = PRECEU_PH_QBL + { 2, &MipsDescs.OperandInfo[1180] }, // Inst #2519 = PRECEQ_W_PHR_MM + { 2, &MipsDescs.OperandInfo[1180] }, // Inst #2518 = PRECEQ_W_PHR + { 2, &MipsDescs.OperandInfo[1180] }, // Inst #2517 = PRECEQ_W_PHL_MM + { 2, &MipsDescs.OperandInfo[1180] }, // Inst #2516 = PRECEQ_W_PHL + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2515 = PRECEQU_PH_QBR_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2514 = PRECEQU_PH_QBRA_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2513 = PRECEQU_PH_QBRA + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2512 = PRECEQU_PH_QBR + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2511 = PRECEQU_PH_QBL_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2510 = PRECEQU_PH_QBLA_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2509 = PRECEQU_PH_QBLA + { 2, &MipsDescs.OperandInfo[550] }, // Inst #2508 = PRECEQU_PH_QBL + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2507 = POP + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2506 = PLU_PS64 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2505 = PLL_PS64 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2504 = PICK_QB_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2503 = PICK_QB + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2502 = PICK_PH_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2501 = PICK_PH + { 2, &MipsDescs.OperandInfo[244] }, // Inst #2500 = PCNT_W + { 2, &MipsDescs.OperandInfo[1174] }, // Inst #2499 = PCNT_H + { 2, &MipsDescs.OperandInfo[242] }, // Inst #2498 = PCNT_D + { 2, &MipsDescs.OperandInfo[1087] }, // Inst #2497 = PCNT_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2496 = PCKOD_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2495 = PCKOD_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2494 = PCKOD_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2493 = PCKOD_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2492 = PCKEV_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2491 = PCKEV_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2490 = PCKEV_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2489 = PCKEV_B + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2488 = PAUSE_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2487 = PAUSE_MMR6 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2486 = PAUSE_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2485 = PAUSE + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2484 = PACKRL_PH_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2483 = PACKRL_PH + { 3, &MipsDescs.OperandInfo[626] }, // Inst #2482 = OrRxRxRy16 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2481 = ORi_MM + { 3, &MipsDescs.OperandInfo[224] }, // Inst #2480 = ORi64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2479 = ORi + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2478 = OR_V + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2477 = OR_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2476 = OR_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2475 = OR_MM + { 3, &MipsDescs.OperandInfo[391] }, // Inst #2474 = ORI_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #2473 = ORI_MMR6 + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2472 = ORI_B + { 3, &MipsDescs.OperandInfo[227] }, // Inst #2471 = OR64 + { 3, &MipsDescs.OperandInfo[599] }, // Inst #2470 = OR16_NM + { 3, &MipsDescs.OperandInfo[611] }, // Inst #2469 = OR16_MMR6 + { 3, &MipsDescs.OperandInfo[611] }, // Inst #2468 = OR16_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2467 = OR + { 2, &MipsDescs.OperandInfo[419] }, // Inst #2466 = NotRxRy16 + { 2, &MipsDescs.OperandInfo[419] }, // Inst #2465 = NegRxRy16 + { 2, &MipsDescs.OperandInfo[1178] }, // Inst #2464 = NOT16_NM + { 2, &MipsDescs.OperandInfo[1176] }, // Inst #2463 = NOT16_MMR6 + { 2, &MipsDescs.OperandInfo[1176] }, // Inst #2462 = NOT16_MM + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2461 = NOR_V + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2460 = NOR_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2459 = NOR_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2458 = NOR_MM + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2457 = NORI_B + { 3, &MipsDescs.OperandInfo[227] }, // Inst #2456 = NOR64 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2455 = NOR + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2454 = NOP_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2453 = NOP32_NM + { 4, &MipsDescs.OperandInfo[1049] }, // Inst #2452 = NMSUB_S_MM + { 4, &MipsDescs.OperandInfo[1049] }, // Inst #2451 = NMSUB_S + { 4, &MipsDescs.OperandInfo[1045] }, // Inst #2450 = NMSUB_D64 + { 4, &MipsDescs.OperandInfo[1041] }, // Inst #2449 = NMSUB_D32_MM + { 4, &MipsDescs.OperandInfo[1041] }, // Inst #2448 = NMSUB_D32 + { 4, &MipsDescs.OperandInfo[1049] }, // Inst #2447 = NMADD_S_MM + { 4, &MipsDescs.OperandInfo[1049] }, // Inst #2446 = NMADD_S + { 4, &MipsDescs.OperandInfo[1045] }, // Inst #2445 = NMADD_D64 + { 4, &MipsDescs.OperandInfo[1041] }, // Inst #2444 = NMADD_D32_MM + { 4, &MipsDescs.OperandInfo[1041] }, // Inst #2443 = NMADD_D32 + { 2, &MipsDescs.OperandInfo[244] }, // Inst #2442 = NLZC_W + { 2, &MipsDescs.OperandInfo[1174] }, // Inst #2441 = NLZC_H + { 2, &MipsDescs.OperandInfo[242] }, // Inst #2440 = NLZC_D + { 2, &MipsDescs.OperandInfo[1087] }, // Inst #2439 = NLZC_B + { 2, &MipsDescs.OperandInfo[244] }, // Inst #2438 = NLOC_W + { 2, &MipsDescs.OperandInfo[1174] }, // Inst #2437 = NLOC_H + { 2, &MipsDescs.OperandInfo[242] }, // Inst #2436 = NLOC_D + { 2, &MipsDescs.OperandInfo[1087] }, // Inst #2435 = NLOC_B + { 2, &MipsDescs.OperandInfo[1172] }, // Inst #2434 = MoveR3216 + { 2, &MipsDescs.OperandInfo[1170] }, // Inst #2433 = Move32R16 + { 1, &MipsDescs.OperandInfo[915] }, // Inst #2432 = Mflo16 + { 1, &MipsDescs.OperandInfo[915] }, // Inst #2431 = Mfhi16 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2430 = MUL_S_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2429 = MUL_S_PH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2428 = MUL_R6 + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2427 = MUL_Q_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2426 = MUL_Q_H + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2425 = MUL_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2424 = MUL_PH + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2423 = MUL_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2422 = MUL_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2421 = MUL_MM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2420 = MULV_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2419 = MULV_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2418 = MULV_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2417 = MULV_B + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2416 = MULU_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2415 = MULU_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2414 = MULU + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2413 = MULTu_MM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2412 = MULTu + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2411 = MULT_MM + { 3, &MipsDescs.OperandInfo[463] }, // Inst #2410 = MULT_DSP_MM + { 3, &MipsDescs.OperandInfo[463] }, // Inst #2409 = MULT_DSP + { 3, &MipsDescs.OperandInfo[463] }, // Inst #2408 = MULTU_DSP_MM + { 3, &MipsDescs.OperandInfo[463] }, // Inst #2407 = MULTU_DSP + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2406 = MULT + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2405 = MULSA_W_PH_MMR2 + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2404 = MULSA_W_PH + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2403 = MULSAQ_S_W_PH_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2402 = MULSAQ_S_W_PH + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2401 = MULR_Q_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2400 = MULR_Q_H + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2399 = MULR_PS64 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2398 = MULQ_S_W_MMR2 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2397 = MULQ_S_W + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2396 = MULQ_S_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2395 = MULQ_S_PH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2394 = MULQ_RS_W_MMR2 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2393 = MULQ_RS_W + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2392 = MULQ_RS_PH_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2391 = MULQ_RS_PH + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2390 = MULEU_S_PH_QBR_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2389 = MULEU_S_PH_QBR + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2388 = MULEU_S_PH_QBL_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #2387 = MULEU_S_PH_QBL + { 3, &MipsDescs.OperandInfo[719] }, // Inst #2386 = MULEQ_S_W_PHR_MM + { 3, &MipsDescs.OperandInfo[719] }, // Inst #2385 = MULEQ_S_W_PHR + { 3, &MipsDescs.OperandInfo[719] }, // Inst #2384 = MULEQ_S_W_PHL_MM + { 3, &MipsDescs.OperandInfo[719] }, // Inst #2383 = MULEQ_S_W_PHL + { 3, &MipsDescs.OperandInfo[602] }, // Inst #2382 = MUL4x4_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2381 = MUL + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2380 = MUH_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2379 = MUH_MMR6 + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2378 = MUHU_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2377 = MUHU_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2376 = MUHU + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2375 = MUH + { 5, &MipsDescs.OperandInfo[1165] }, // Inst #2374 = MTTR_NM + { 5, &MipsDescs.OperandInfo[1062] }, // Inst #2373 = MTTR + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2372 = MTP2 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2371 = MTP1 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2370 = MTP0 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2369 = MTM2 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2368 = MTM1 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2367 = MTM0 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2366 = MTLO_MM + { 2, &MipsDescs.OperandInfo[1163] }, // Inst #2365 = MTLO_DSP_MM + { 2, &MipsDescs.OperandInfo[1163] }, // Inst #2364 = MTLO_DSP + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2363 = MTLO64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2362 = MTLO + { 3, &MipsDescs.OperandInfo[1160] }, // Inst #2361 = MTHLIP_MM + { 3, &MipsDescs.OperandInfo[1160] }, // Inst #2360 = MTHLIP + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2359 = MTHI_MM + { 2, &MipsDescs.OperandInfo[1158] }, // Inst #2358 = MTHI_DSP_MM + { 2, &MipsDescs.OperandInfo[1158] }, // Inst #2357 = MTHI_DSP + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2356 = MTHI64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2355 = MTHI + { 3, &MipsDescs.OperandInfo[408] }, // Inst #2354 = MTHGC0_MM + { 3, &MipsDescs.OperandInfo[408] }, // Inst #2353 = MTHGC0 + { 2, &MipsDescs.OperandInfo[745] }, // Inst #2352 = MTHC2_MMR6 + { 3, &MipsDescs.OperandInfo[1155] }, // Inst #2351 = MTHC1_D64_MM + { 3, &MipsDescs.OperandInfo[1155] }, // Inst #2350 = MTHC1_D64 + { 3, &MipsDescs.OperandInfo[1152] }, // Inst #2349 = MTHC1_D32_MM + { 3, &MipsDescs.OperandInfo[1152] }, // Inst #2348 = MTHC1_D32 + { 3, &MipsDescs.OperandInfo[386] }, // Inst #2347 = MTHC0_NM + { 3, &MipsDescs.OperandInfo[408] }, // Inst #2346 = MTHC0_MMR6 + { 2, &MipsDescs.OperandInfo[1053] }, // Inst #2345 = MTHC0Sel_NM + { 3, &MipsDescs.OperandInfo[408] }, // Inst #2344 = MTGC0_MM + { 3, &MipsDescs.OperandInfo[408] }, // Inst #2343 = MTGC0 + { 2, &MipsDescs.OperandInfo[745] }, // Inst #2342 = MTC2_MMR6 + { 3, &MipsDescs.OperandInfo[1149] }, // Inst #2341 = MTC2 + { 2, &MipsDescs.OperandInfo[414] }, // Inst #2340 = MTC1_MMR6 + { 2, &MipsDescs.OperandInfo[414] }, // Inst #2339 = MTC1_MM + { 2, &MipsDescs.OperandInfo[431] }, // Inst #2338 = MTC1_D64_MM + { 2, &MipsDescs.OperandInfo[431] }, // Inst #2337 = MTC1_D64 + { 2, &MipsDescs.OperandInfo[414] }, // Inst #2336 = MTC1 + { 3, &MipsDescs.OperandInfo[386] }, // Inst #2335 = MTC0_NM + { 3, &MipsDescs.OperandInfo[408] }, // Inst #2334 = MTC0_MMR6 + { 2, &MipsDescs.OperandInfo[1053] }, // Inst #2333 = MTC0Sel_NM + { 3, &MipsDescs.OperandInfo[408] }, // Inst #2332 = MTC0 + { 4, &MipsDescs.OperandInfo[1049] }, // Inst #2331 = MSUB_S_MM + { 4, &MipsDescs.OperandInfo[1049] }, // Inst #2330 = MSUB_S + { 4, &MipsDescs.OperandInfo[194] }, // Inst #2329 = MSUB_Q_W + { 4, &MipsDescs.OperandInfo[198] }, // Inst #2328 = MSUB_Q_H + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2327 = MSUB_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2326 = MSUB_DSP_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2325 = MSUB_DSP + { 4, &MipsDescs.OperandInfo[1045] }, // Inst #2324 = MSUB_D64 + { 4, &MipsDescs.OperandInfo[1041] }, // Inst #2323 = MSUB_D32_MM + { 4, &MipsDescs.OperandInfo[1041] }, // Inst #2322 = MSUB_D32 + { 4, &MipsDescs.OperandInfo[194] }, // Inst #2321 = MSUBV_W + { 4, &MipsDescs.OperandInfo[198] }, // Inst #2320 = MSUBV_H + { 4, &MipsDescs.OperandInfo[190] }, // Inst #2319 = MSUBV_D + { 4, &MipsDescs.OperandInfo[672] }, // Inst #2318 = MSUBV_B + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2317 = MSUBU_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2316 = MSUBU_DSP_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2315 = MSUBU_DSP + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2314 = MSUBU + { 4, &MipsDescs.OperandInfo[194] }, // Inst #2313 = MSUBR_Q_W + { 4, &MipsDescs.OperandInfo[198] }, // Inst #2312 = MSUBR_Q_H + { 4, &MipsDescs.OperandInfo[1037] }, // Inst #2311 = MSUBF_S_MMR6 + { 4, &MipsDescs.OperandInfo[1037] }, // Inst #2310 = MSUBF_S + { 4, &MipsDescs.OperandInfo[1033] }, // Inst #2309 = MSUBF_D_MMR6 + { 4, &MipsDescs.OperandInfo[1033] }, // Inst #2308 = MSUBF_D + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2307 = MSUB + { 4, &MipsDescs.OperandInfo[1145] }, // Inst #2306 = MOVZ_NM + { 4, &MipsDescs.OperandInfo[1141] }, // Inst #2305 = MOVZ_I_S_MM + { 4, &MipsDescs.OperandInfo[1141] }, // Inst #2304 = MOVZ_I_S + { 4, &MipsDescs.OperandInfo[1133] }, // Inst #2303 = MOVZ_I_MM + { 4, &MipsDescs.OperandInfo[1137] }, // Inst #2302 = MOVZ_I_I64 + { 4, &MipsDescs.OperandInfo[1133] }, // Inst #2301 = MOVZ_I_I + { 4, &MipsDescs.OperandInfo[1129] }, // Inst #2300 = MOVZ_I_D64 + { 4, &MipsDescs.OperandInfo[1125] }, // Inst #2299 = MOVZ_I_D32_MM + { 4, &MipsDescs.OperandInfo[1125] }, // Inst #2298 = MOVZ_I_D32 + { 4, &MipsDescs.OperandInfo[1121] }, // Inst #2297 = MOVZ_I64_S + { 4, &MipsDescs.OperandInfo[1117] }, // Inst #2296 = MOVZ_I64_I64 + { 4, &MipsDescs.OperandInfo[1113] }, // Inst #2295 = MOVZ_I64_I + { 4, &MipsDescs.OperandInfo[1109] }, // Inst #2294 = MOVZ_I64_D64 + { 4, &MipsDescs.OperandInfo[1105] }, // Inst #2293 = MOVT_S_MM + { 4, &MipsDescs.OperandInfo[1105] }, // Inst #2292 = MOVT_S + { 4, &MipsDescs.OperandInfo[1097] }, // Inst #2291 = MOVT_I_MM + { 4, &MipsDescs.OperandInfo[1101] }, // Inst #2290 = MOVT_I64 + { 4, &MipsDescs.OperandInfo[1097] }, // Inst #2289 = MOVT_I + { 4, &MipsDescs.OperandInfo[1093] }, // Inst #2288 = MOVT_D64 + { 4, &MipsDescs.OperandInfo[1089] }, // Inst #2287 = MOVT_D32_MM + { 4, &MipsDescs.OperandInfo[1089] }, // Inst #2286 = MOVT_D32 + { 4, &MipsDescs.OperandInfo[1145] }, // Inst #2285 = MOVN_NM + { 4, &MipsDescs.OperandInfo[1141] }, // Inst #2284 = MOVN_I_S_MM + { 4, &MipsDescs.OperandInfo[1141] }, // Inst #2283 = MOVN_I_S + { 4, &MipsDescs.OperandInfo[1133] }, // Inst #2282 = MOVN_I_MM + { 4, &MipsDescs.OperandInfo[1137] }, // Inst #2281 = MOVN_I_I64 + { 4, &MipsDescs.OperandInfo[1133] }, // Inst #2280 = MOVN_I_I + { 4, &MipsDescs.OperandInfo[1129] }, // Inst #2279 = MOVN_I_D64 + { 4, &MipsDescs.OperandInfo[1125] }, // Inst #2278 = MOVN_I_D32_MM + { 4, &MipsDescs.OperandInfo[1125] }, // Inst #2277 = MOVN_I_D32 + { 4, &MipsDescs.OperandInfo[1121] }, // Inst #2276 = MOVN_I64_S + { 4, &MipsDescs.OperandInfo[1117] }, // Inst #2275 = MOVN_I64_I64 + { 4, &MipsDescs.OperandInfo[1113] }, // Inst #2274 = MOVN_I64_I + { 4, &MipsDescs.OperandInfo[1109] }, // Inst #2273 = MOVN_I64_D64 + { 4, &MipsDescs.OperandInfo[1105] }, // Inst #2272 = MOVF_S_MM + { 4, &MipsDescs.OperandInfo[1105] }, // Inst #2271 = MOVF_S + { 4, &MipsDescs.OperandInfo[1097] }, // Inst #2270 = MOVF_I_MM + { 4, &MipsDescs.OperandInfo[1101] }, // Inst #2269 = MOVF_I64 + { 4, &MipsDescs.OperandInfo[1097] }, // Inst #2268 = MOVF_I + { 4, &MipsDescs.OperandInfo[1093] }, // Inst #2267 = MOVF_D64 + { 4, &MipsDescs.OperandInfo[1089] }, // Inst #2266 = MOVF_D32_MM + { 4, &MipsDescs.OperandInfo[1089] }, // Inst #2265 = MOVF_D32 + { 2, &MipsDescs.OperandInfo[1087] }, // Inst #2264 = MOVE_V + { 2, &MipsDescs.OperandInfo[629] }, // Inst #2263 = MOVE_NM + { 4, &MipsDescs.OperandInfo[1083] }, // Inst #2262 = MOVEP_NM + { 4, &MipsDescs.OperandInfo[1079] }, // Inst #2261 = MOVEP_MMR6 + { 4, &MipsDescs.OperandInfo[1079] }, // Inst #2260 = MOVEP_MM + { 4, &MipsDescs.OperandInfo[1075] }, // Inst #2259 = MOVEPREV_NM + { 3, &MipsDescs.OperandInfo[1072] }, // Inst #2258 = MOVEBALC_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2257 = MOVE16_MMR6 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2256 = MOVE16_MM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2255 = MOD_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2254 = MOD_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2253 = MOD_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2252 = MOD_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2251 = MOD_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2250 = MOD_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2249 = MOD_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2248 = MOD_S_B + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2247 = MOD_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2246 = MOD_MMR6 + { 3, &MipsDescs.OperandInfo[596] }, // Inst #2245 = MODU_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2244 = MODU_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2243 = MODU + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2242 = MODSUB_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2241 = MODSUB + { 3, &MipsDescs.OperandInfo[230] }, // Inst #2240 = MOD + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2239 = MIN_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2238 = MIN_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2237 = MIN_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2236 = MIN_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2235 = MIN_S_W + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2234 = MIN_S_MMR6 + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2233 = MIN_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2232 = MIN_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2231 = MIN_S_B + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2230 = MIN_S + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2229 = MIN_D_MMR6 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2228 = MIN_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2227 = MIN_A_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2226 = MIN_A_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2225 = MIN_A_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2224 = MIN_A_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2223 = MINI_U_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2222 = MINI_U_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2221 = MINI_U_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2220 = MINI_U_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2219 = MINI_S_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2218 = MINI_S_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2217 = MINI_S_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2216 = MINI_S_B + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2215 = MINA_S_MMR6 + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2214 = MINA_S + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2213 = MINA_D_MMR6 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2212 = MINA_D + { 5, &MipsDescs.OperandInfo[1067] }, // Inst #2211 = MFTR_NM + { 5, &MipsDescs.OperandInfo[1062] }, // Inst #2210 = MFTR + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2209 = MFLO_MM + { 2, &MipsDescs.OperandInfo[379] }, // Inst #2208 = MFLO_DSP_MM + { 2, &MipsDescs.OperandInfo[379] }, // Inst #2207 = MFLO_DSP + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2206 = MFLO64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2205 = MFLO16_MM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2204 = MFLO + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2203 = MFHI_MM + { 2, &MipsDescs.OperandInfo[379] }, // Inst #2202 = MFHI_DSP_MM + { 2, &MipsDescs.OperandInfo[379] }, // Inst #2201 = MFHI_DSP + { 1, &MipsDescs.OperandInfo[310] }, // Inst #2200 = MFHI64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2199 = MFHI16_MM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #2198 = MFHI + { 3, &MipsDescs.OperandInfo[383] }, // Inst #2197 = MFHGC0_MM + { 3, &MipsDescs.OperandInfo[383] }, // Inst #2196 = MFHGC0 + { 2, &MipsDescs.OperandInfo[703] }, // Inst #2195 = MFHC2_MMR6 + { 2, &MipsDescs.OperandInfo[1055] }, // Inst #2194 = MFHC1_D64_MM + { 2, &MipsDescs.OperandInfo[1055] }, // Inst #2193 = MFHC1_D64 + { 2, &MipsDescs.OperandInfo[1060] }, // Inst #2192 = MFHC1_D32_MM + { 2, &MipsDescs.OperandInfo[1060] }, // Inst #2191 = MFHC1_D32 + { 3, &MipsDescs.OperandInfo[386] }, // Inst #2190 = MFHC0_NM + { 3, &MipsDescs.OperandInfo[383] }, // Inst #2189 = MFHC0_MMR6 + { 2, &MipsDescs.OperandInfo[1053] }, // Inst #2188 = MFHC0Sel_NM + { 3, &MipsDescs.OperandInfo[383] }, // Inst #2187 = MFGC0_MM + { 3, &MipsDescs.OperandInfo[383] }, // Inst #2186 = MFGC0 + { 2, &MipsDescs.OperandInfo[703] }, // Inst #2185 = MFC2_MMR6 + { 3, &MipsDescs.OperandInfo[1057] }, // Inst #2184 = MFC2 + { 2, &MipsDescs.OperandInfo[389] }, // Inst #2183 = MFC1_MMR6 + { 2, &MipsDescs.OperandInfo[389] }, // Inst #2182 = MFC1_MM + { 2, &MipsDescs.OperandInfo[1055] }, // Inst #2181 = MFC1_D64 + { 2, &MipsDescs.OperandInfo[389] }, // Inst #2180 = MFC1 + { 3, &MipsDescs.OperandInfo[386] }, // Inst #2179 = MFC0_NM + { 3, &MipsDescs.OperandInfo[383] }, // Inst #2178 = MFC0_MMR6 + { 2, &MipsDescs.OperandInfo[1053] }, // Inst #2177 = MFC0Sel_NM + { 3, &MipsDescs.OperandInfo[383] }, // Inst #2176 = MFC0 + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2175 = MAX_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2174 = MAX_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2173 = MAX_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2172 = MAX_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2171 = MAX_S_W + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2170 = MAX_S_MMR6 + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2169 = MAX_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2168 = MAX_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2167 = MAX_S_B + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2166 = MAX_S + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2165 = MAX_D_MMR6 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2164 = MAX_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #2163 = MAX_A_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #2162 = MAX_A_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #2161 = MAX_A_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #2160 = MAX_A_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2159 = MAXI_U_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2158 = MAXI_U_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2157 = MAXI_U_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2156 = MAXI_U_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #2155 = MAXI_S_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #2154 = MAXI_S_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #2153 = MAXI_S_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #2152 = MAXI_S_B + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2151 = MAXA_S_MMR6 + { 3, &MipsDescs.OperandInfo[834] }, // Inst #2150 = MAXA_S + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2149 = MAXA_D_MMR6 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #2148 = MAXA_D + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2147 = MAQ_S_W_PHR_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2146 = MAQ_S_W_PHR + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2145 = MAQ_S_W_PHL_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2144 = MAQ_S_W_PHL + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2143 = MAQ_SA_W_PHR_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2142 = MAQ_SA_W_PHR + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2141 = MAQ_SA_W_PHL_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2140 = MAQ_SA_W_PHL + { 4, &MipsDescs.OperandInfo[1049] }, // Inst #2139 = MADD_S_MM + { 4, &MipsDescs.OperandInfo[1049] }, // Inst #2138 = MADD_S + { 4, &MipsDescs.OperandInfo[194] }, // Inst #2137 = MADD_Q_W + { 4, &MipsDescs.OperandInfo[198] }, // Inst #2136 = MADD_Q_H + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2135 = MADD_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2134 = MADD_DSP_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2133 = MADD_DSP + { 4, &MipsDescs.OperandInfo[1045] }, // Inst #2132 = MADD_D64 + { 4, &MipsDescs.OperandInfo[1041] }, // Inst #2131 = MADD_D32_MM + { 4, &MipsDescs.OperandInfo[1041] }, // Inst #2130 = MADD_D32 + { 4, &MipsDescs.OperandInfo[194] }, // Inst #2129 = MADDV_W + { 4, &MipsDescs.OperandInfo[198] }, // Inst #2128 = MADDV_H + { 4, &MipsDescs.OperandInfo[190] }, // Inst #2127 = MADDV_D + { 4, &MipsDescs.OperandInfo[672] }, // Inst #2126 = MADDV_B + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2125 = MADDU_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2124 = MADDU_DSP_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #2123 = MADDU_DSP + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2122 = MADDU + { 4, &MipsDescs.OperandInfo[194] }, // Inst #2121 = MADDR_Q_W + { 4, &MipsDescs.OperandInfo[198] }, // Inst #2120 = MADDR_Q_H + { 4, &MipsDescs.OperandInfo[1037] }, // Inst #2119 = MADDF_S_MMR6 + { 4, &MipsDescs.OperandInfo[1037] }, // Inst #2118 = MADDF_S + { 4, &MipsDescs.OperandInfo[1033] }, // Inst #2117 = MADDF_D_MMR6 + { 4, &MipsDescs.OperandInfo[1033] }, // Inst #2116 = MADDF_D + { 2, &MipsDescs.OperandInfo[140] }, // Inst #2115 = MADD + { 3, &MipsDescs.OperandInfo[623] }, // Inst #2114 = LwRxSpImmX16 + { 3, &MipsDescs.OperandInfo[1027] }, // Inst #2113 = LwRxRyOffMemX16 + { 3, &MipsDescs.OperandInfo[1030] }, // Inst #2112 = LwRxPcTcpX16 + { 3, &MipsDescs.OperandInfo[1030] }, // Inst #2111 = LwRxPcTcp16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #2110 = LiRxImmX16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #2109 = LiRxImmAlignX16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #2108 = LiRxImm16 + { 3, &MipsDescs.OperandInfo[1027] }, // Inst #2107 = LhuRxRyOffMemX16 + { 3, &MipsDescs.OperandInfo[1027] }, // Inst #2106 = LhRxRyOffMemX16 + { 3, &MipsDescs.OperandInfo[1027] }, // Inst #2105 = LbuRxRyOffMemX16 + { 3, &MipsDescs.OperandInfo[1027] }, // Inst #2104 = LbRxRyOffMemX16 + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2103 = LWu + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2102 = LWs9_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2101 = LW_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2100 = LW_MMR6 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2099 = LW_MM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2098 = LWX_NM + { 3, &MipsDescs.OperandInfo[925] }, // Inst #2097 = LWX_MM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2096 = LWXS_NM + { 3, &MipsDescs.OperandInfo[925] }, // Inst #2095 = LWXS_MM + { 3, &MipsDescs.OperandInfo[916] }, // Inst #2094 = LWXS16_NM + { 3, &MipsDescs.OperandInfo[1024] }, // Inst #2093 = LWXC1_MM + { 3, &MipsDescs.OperandInfo[1024] }, // Inst #2092 = LWXC1 + { 3, &MipsDescs.OperandInfo[925] }, // Inst #2091 = LWX + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2090 = LWU_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #2089 = LWUPC + { 3, &MipsDescs.OperandInfo[1021] }, // Inst #2088 = LWSP_MM + { 3, &MipsDescs.OperandInfo[1018] }, // Inst #2087 = LWSP16_NM + { 4, &MipsDescs.OperandInfo[1003] }, // Inst #2086 = LWR_MM + { 4, &MipsDescs.OperandInfo[1003] }, // Inst #2085 = LWRE_MM + { 4, &MipsDescs.OperandInfo[1003] }, // Inst #2084 = LWRE + { 4, &MipsDescs.OperandInfo[951] }, // Inst #2083 = LWR64 + { 4, &MipsDescs.OperandInfo[1003] }, // Inst #2082 = LWR + { 4, &MipsDescs.OperandInfo[1014] }, // Inst #2081 = LWP_MM + { 2, &MipsDescs.OperandInfo[609] }, // Inst #2080 = LWPC_NM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #2079 = LWPC_MMR6 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #2078 = LWPC + { 4, &MipsDescs.OperandInfo[1010] }, // Inst #2077 = LWM_NM + { 3, &MipsDescs.OperandInfo[354] }, // Inst #2076 = LWM32_MM + { 3, &MipsDescs.OperandInfo[1007] }, // Inst #2075 = LWM16_MMR6 + { 3, &MipsDescs.OperandInfo[1007] }, // Inst #2074 = LWM16_MM + { 4, &MipsDescs.OperandInfo[1003] }, // Inst #2073 = LWL_MM + { 4, &MipsDescs.OperandInfo[1003] }, // Inst #2072 = LWLE_MM + { 4, &MipsDescs.OperandInfo[1003] }, // Inst #2071 = LWLE + { 4, &MipsDescs.OperandInfo[951] }, // Inst #2070 = LWL64 + { 4, &MipsDescs.OperandInfo[1003] }, // Inst #2069 = LWL + { 3, &MipsDescs.OperandInfo[1000] }, // Inst #2068 = LWGP_NM + { 3, &MipsDescs.OperandInfo[997] }, // Inst #2067 = LWGP_MM + { 3, &MipsDescs.OperandInfo[994] }, // Inst #2066 = LWGP16_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2065 = LWE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2064 = LWE + { 3, &MipsDescs.OperandInfo[991] }, // Inst #2063 = LWDSP_MM + { 3, &MipsDescs.OperandInfo[991] }, // Inst #2062 = LWDSP + { 3, &MipsDescs.OperandInfo[940] }, // Inst #2061 = LWC3 + { 3, &MipsDescs.OperandInfo[934] }, // Inst #2060 = LWC2_R6 + { 3, &MipsDescs.OperandInfo[937] }, // Inst #2059 = LWC2_MMR6 + { 3, &MipsDescs.OperandInfo[934] }, // Inst #2058 = LWC2 + { 3, &MipsDescs.OperandInfo[988] }, // Inst #2057 = LWC1_MM + { 3, &MipsDescs.OperandInfo[988] }, // Inst #2056 = LWC1 + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2055 = LW64 + { 3, &MipsDescs.OperandInfo[985] }, // Inst #2054 = LW4x4_NM + { 3, &MipsDescs.OperandInfo[916] }, // Inst #2053 = LW16_NM + { 3, &MipsDescs.OperandInfo[922] }, // Inst #2052 = LW16_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2051 = LW + { 2, &MipsDescs.OperandInfo[364] }, // Inst #2050 = LUi_MM + { 2, &MipsDescs.OperandInfo[359] }, // Inst #2049 = LUi64 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #2048 = LUi + { 3, &MipsDescs.OperandInfo[958] }, // Inst #2047 = LUXC1_MM + { 3, &MipsDescs.OperandInfo[958] }, // Inst #2046 = LUXC164 + { 3, &MipsDescs.OperandInfo[955] }, // Inst #2045 = LUXC1 + { 2, &MipsDescs.OperandInfo[450] }, // Inst #2044 = LUI_NM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #2043 = LUI_MMR6 + { 4, &MipsDescs.OperandInfo[605] }, // Inst #2042 = LSA_R6 + { 4, &MipsDescs.OperandInfo[142] }, // Inst #2041 = LSA_NM + { 4, &MipsDescs.OperandInfo[605] }, // Inst #2040 = LSA_MMR6 + { 4, &MipsDescs.OperandInfo[605] }, // Inst #2039 = LSA + { 3, &MipsDescs.OperandInfo[975] }, // Inst #2038 = LL_R6 + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2037 = LL_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2036 = LL_MMR6 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2035 = LL_MM + { 4, &MipsDescs.OperandInfo[981] }, // Inst #2034 = LLWP_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2033 = LLE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2032 = LLE + { 3, &MipsDescs.OperandInfo[978] }, // Inst #2031 = LLD_R6 + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2030 = LLD + { 3, &MipsDescs.OperandInfo[975] }, // Inst #2029 = LL64_R6 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2028 = LL64 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2027 = LL + { 2, &MipsDescs.OperandInfo[450] }, // Inst #2026 = LI48_NM + { 2, &MipsDescs.OperandInfo[973] }, // Inst #2025 = LI16_NM + { 2, &MipsDescs.OperandInfo[558] }, // Inst #2024 = LI16_MMR6 + { 2, &MipsDescs.OperandInfo[558] }, // Inst #2023 = LI16_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2022 = LHu_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2021 = LHuE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2020 = LHuE + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2019 = LHu64 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2018 = LHu + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2017 = LHs9_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2016 = LH_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2015 = LH_MM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2014 = LHX_NM + { 3, &MipsDescs.OperandInfo[925] }, // Inst #2013 = LHX_MM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2012 = LHXS_NM + { 3, &MipsDescs.OperandInfo[925] }, // Inst #2011 = LHX + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2010 = LHUs9_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2009 = LHU_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2008 = LHUX_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #2007 = LHUXS_NM + { 3, &MipsDescs.OperandInfo[919] }, // Inst #2006 = LHUGP_NM + { 3, &MipsDescs.OperandInfo[916] }, // Inst #2005 = LHU16_NM + { 3, &MipsDescs.OperandInfo[922] }, // Inst #2004 = LHU16_MM + { 3, &MipsDescs.OperandInfo[919] }, // Inst #2003 = LHGP_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2002 = LHE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #2001 = LHE + { 3, &MipsDescs.OperandInfo[361] }, // Inst #2000 = LH64 + { 3, &MipsDescs.OperandInfo[916] }, // Inst #1999 = LH16_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1998 = LH + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1997 = LEA_ADDiu_MM + { 3, &MipsDescs.OperandInfo[361] }, // Inst #1996 = LEA_ADDiu64 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1995 = LEA_ADDiu + { 3, &MipsDescs.OperandInfo[928] }, // Inst #1994 = LEA_ADDIU_NM + { 3, &MipsDescs.OperandInfo[970] }, // Inst #1993 = LD_W + { 3, &MipsDescs.OperandInfo[967] }, // Inst #1992 = LD_H + { 3, &MipsDescs.OperandInfo[964] }, // Inst #1991 = LD_D + { 3, &MipsDescs.OperandInfo[961] }, // Inst #1990 = LD_B + { 3, &MipsDescs.OperandInfo[958] }, // Inst #1989 = LDXC164 + { 3, &MipsDescs.OperandInfo[955] }, // Inst #1988 = LDXC1 + { 4, &MipsDescs.OperandInfo[951] }, // Inst #1987 = LDR + { 2, &MipsDescs.OperandInfo[359] }, // Inst #1986 = LDPC + { 4, &MipsDescs.OperandInfo[951] }, // Inst #1985 = LDL + { 2, &MipsDescs.OperandInfo[949] }, // Inst #1984 = LDI_W + { 2, &MipsDescs.OperandInfo[947] }, // Inst #1983 = LDI_H + { 2, &MipsDescs.OperandInfo[945] }, // Inst #1982 = LDI_D + { 2, &MipsDescs.OperandInfo[943] }, // Inst #1981 = LDI_B + { 3, &MipsDescs.OperandInfo[940] }, // Inst #1980 = LDC3 + { 3, &MipsDescs.OperandInfo[934] }, // Inst #1979 = LDC2_R6 + { 3, &MipsDescs.OperandInfo[937] }, // Inst #1978 = LDC2_MMR6 + { 3, &MipsDescs.OperandInfo[934] }, // Inst #1977 = LDC2 + { 3, &MipsDescs.OperandInfo[931] }, // Inst #1976 = LDC1_MM_D64 + { 3, &MipsDescs.OperandInfo[519] }, // Inst #1975 = LDC1_MM_D32 + { 3, &MipsDescs.OperandInfo[931] }, // Inst #1974 = LDC1_D64_MMR6 + { 3, &MipsDescs.OperandInfo[931] }, // Inst #1973 = LDC164 + { 3, &MipsDescs.OperandInfo[519] }, // Inst #1972 = LDC1 + { 3, &MipsDescs.OperandInfo[361] }, // Inst #1971 = LD + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1970 = LBu_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1969 = LBuE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1968 = LBuE + { 3, &MipsDescs.OperandInfo[361] }, // Inst #1967 = LBu64 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1966 = LBu + { 3, &MipsDescs.OperandInfo[928] }, // Inst #1965 = LBs9_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #1964 = LB_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1963 = LB_MMR6 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1962 = LB_MM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #1961 = LBX_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #1960 = LBUs9_NM + { 3, &MipsDescs.OperandInfo[928] }, // Inst #1959 = LBU_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1958 = LBU_MMR6 + { 3, &MipsDescs.OperandInfo[928] }, // Inst #1957 = LBUX_NM + { 3, &MipsDescs.OperandInfo[925] }, // Inst #1956 = LBUX_MM + { 3, &MipsDescs.OperandInfo[925] }, // Inst #1955 = LBUX + { 3, &MipsDescs.OperandInfo[919] }, // Inst #1954 = LBUGP_NM + { 3, &MipsDescs.OperandInfo[916] }, // Inst #1953 = LBU16_NM + { 3, &MipsDescs.OperandInfo[922] }, // Inst #1952 = LBU16_MM + { 3, &MipsDescs.OperandInfo[919] }, // Inst #1951 = LBGP_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1950 = LBE_MM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1949 = LBE + { 3, &MipsDescs.OperandInfo[361] }, // Inst #1948 = LB64 + { 3, &MipsDescs.OperandInfo[916] }, // Inst #1947 = LB16_NM + { 3, &MipsDescs.OperandInfo[312] }, // Inst #1946 = LB + { 2, &MipsDescs.OperandInfo[609] }, // Inst #1945 = LAPC48_NM + { 2, &MipsDescs.OperandInfo[609] }, // Inst #1944 = LAPC32_NM + { 1, &MipsDescs.OperandInfo[915] }, // Inst #1943 = JumpLinkReg16 + { 1, &MipsDescs.OperandInfo[915] }, // Inst #1942 = JrcRx16 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1941 = JrcRa16 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1940 = JrRa16 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1939 = JalB16 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1938 = Jal16 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1937 = J_MM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1936 = JR_MM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1935 = JR_HB_R6 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #1934 = JR_HB64_R6 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #1933 = JR_HB64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1932 = JR_HB + { 1, &MipsDescs.OperandInfo[311] }, // Inst #1931 = JRC_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1930 = JRCADDIUSP_MMR6 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1929 = JRC16_MMR6 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1928 = JRC16_MM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1927 = JRADDIUSP + { 1, &MipsDescs.OperandInfo[310] }, // Inst #1926 = JR64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1925 = JR16_MM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1924 = JR + { 2, &MipsDescs.OperandInfo[364] }, // Inst #1923 = JIC_MMR6 + { 2, &MipsDescs.OperandInfo[359] }, // Inst #1922 = JIC64 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #1921 = JIC + { 2, &MipsDescs.OperandInfo[364] }, // Inst #1920 = JIALC_MMR6 + { 2, &MipsDescs.OperandInfo[359] }, // Inst #1919 = JIALC64 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #1918 = JIALC + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1917 = JAL_MM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1916 = JALX_MM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1915 = JALX + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1914 = JALS_MM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1913 = JALR_MM + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1912 = JALR_HB64 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1911 = JALR_HB + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1910 = JALRS_MM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1909 = JALRS16_MM + { 2, &MipsDescs.OperandInfo[416] }, // Inst #1908 = JALRC_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1907 = JALRC_MMR6 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1906 = JALRC_HB_MMR6 + { 2, &MipsDescs.OperandInfo[416] }, // Inst #1905 = JALRCHB_NM + { 2, &MipsDescs.OperandInfo[913] }, // Inst #1904 = JALRC16_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1903 = JALRC16_MMR6 + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1902 = JALR64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1901 = JALR16_MM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1900 = JALR + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1899 = JAL + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1898 = J + { 5, &MipsDescs.OperandInfo[908] }, // Inst #1897 = INS_NM + { 5, &MipsDescs.OperandInfo[864] }, // Inst #1896 = INS_MMR6 + { 5, &MipsDescs.OperandInfo[864] }, // Inst #1895 = INS_MM + { 3, &MipsDescs.OperandInfo[885] }, // Inst #1894 = INSV_MM + { 5, &MipsDescs.OperandInfo[903] }, // Inst #1893 = INSVE_W + { 5, &MipsDescs.OperandInfo[898] }, // Inst #1892 = INSVE_H + { 5, &MipsDescs.OperandInfo[893] }, // Inst #1891 = INSVE_D + { 5, &MipsDescs.OperandInfo[888] }, // Inst #1890 = INSVE_B + { 3, &MipsDescs.OperandInfo[885] }, // Inst #1889 = INSV + { 4, &MipsDescs.OperandInfo[881] }, // Inst #1888 = INSERT_W + { 4, &MipsDescs.OperandInfo[877] }, // Inst #1887 = INSERT_H + { 4, &MipsDescs.OperandInfo[873] }, // Inst #1886 = INSERT_D + { 4, &MipsDescs.OperandInfo[869] }, // Inst #1885 = INSERT_B + { 5, &MipsDescs.OperandInfo[864] }, // Inst #1884 = INS + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1883 = ILVR_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1882 = ILVR_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1881 = ILVR_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1880 = ILVR_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1879 = ILVOD_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1878 = ILVOD_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1877 = ILVOD_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1876 = ILVOD_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1875 = ILVL_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1874 = ILVL_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1873 = ILVL_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1872 = ILVL_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1871 = ILVEV_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1870 = ILVEV_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1869 = ILVEV_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1868 = ILVEV_B + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1867 = HYPCALL_MM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1866 = HYPCALL + { 3, &MipsDescs.OperandInfo[795] }, // Inst #1865 = HSUB_U_W + { 3, &MipsDescs.OperandInfo[792] }, // Inst #1864 = HSUB_U_H + { 3, &MipsDescs.OperandInfo[789] }, // Inst #1863 = HSUB_U_D + { 3, &MipsDescs.OperandInfo[795] }, // Inst #1862 = HSUB_S_W + { 3, &MipsDescs.OperandInfo[792] }, // Inst #1861 = HSUB_S_H + { 3, &MipsDescs.OperandInfo[789] }, // Inst #1860 = HSUB_S_D + { 3, &MipsDescs.OperandInfo[795] }, // Inst #1859 = HADD_U_W + { 3, &MipsDescs.OperandInfo[792] }, // Inst #1858 = HADD_U_H + { 3, &MipsDescs.OperandInfo[789] }, // Inst #1857 = HADD_U_D + { 3, &MipsDescs.OperandInfo[795] }, // Inst #1856 = HADD_S_W + { 3, &MipsDescs.OperandInfo[792] }, // Inst #1855 = HADD_S_H + { 3, &MipsDescs.OperandInfo[789] }, // Inst #1854 = HADD_S_D + { 2, &MipsDescs.OperandInfo[450] }, // Inst #1853 = GINVT_NM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #1852 = GINVT_MMR6 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #1851 = GINVT + { 1, &MipsDescs.OperandInfo[311] }, // Inst #1850 = GINVI_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1849 = GINVI_MMR6 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1848 = GINVI + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1847 = FTRUNC_U_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1846 = FTRUNC_U_D + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1845 = FTRUNC_S_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1844 = FTRUNC_S_D + { 3, &MipsDescs.OperandInfo[849] }, // Inst #1843 = FTQ_W + { 3, &MipsDescs.OperandInfo[846] }, // Inst #1842 = FTQ_H + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1841 = FTINT_U_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1840 = FTINT_U_D + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1839 = FTINT_S_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1838 = FTINT_S_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1837 = FSUN_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1836 = FSUN_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1835 = FSUNE_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1834 = FSUNE_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1833 = FSULT_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1832 = FSULT_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1831 = FSULE_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1830 = FSULE_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1829 = FSUEQ_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1828 = FSUEQ_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1827 = FSUB_W + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1826 = FSUB_S_MMR6 + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1825 = FSUB_S_MM + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1824 = FSUB_S + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1823 = FSUB_PS64 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1822 = FSUB_D64_MM + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1821 = FSUB_D64 + { 3, &MipsDescs.OperandInfo[831] }, // Inst #1820 = FSUB_D32_MM + { 3, &MipsDescs.OperandInfo[831] }, // Inst #1819 = FSUB_D32 + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1818 = FSUB_D + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1817 = FSQRT_W + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1816 = FSQRT_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1815 = FSQRT_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1814 = FSQRT_D64_MM + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1813 = FSQRT_D64 + { 2, &MipsDescs.OperandInfo[829] }, // Inst #1812 = FSQRT_D32_MM + { 2, &MipsDescs.OperandInfo[829] }, // Inst #1811 = FSQRT_D32 + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1810 = FSQRT_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1809 = FSOR_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1808 = FSOR_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1807 = FSNE_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1806 = FSNE_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1805 = FSLT_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1804 = FSLT_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1803 = FSLE_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1802 = FSLE_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1801 = FSEQ_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1800 = FSEQ_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1799 = FSAF_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1798 = FSAF_D + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1797 = FRSQRT_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1796 = FRSQRT_D + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1795 = FRINT_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1794 = FRINT_D + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1793 = FRCP_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1792 = FRCP_D + { 3, &MipsDescs.OperandInfo[596] }, // Inst #1791 = FORK_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1790 = FORK + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1789 = FNEG_S_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1788 = FNEG_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1787 = FNEG_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1786 = FNEG_D64_MM + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1785 = FNEG_D64 + { 2, &MipsDescs.OperandInfo[829] }, // Inst #1784 = FNEG_D32_MM + { 2, &MipsDescs.OperandInfo[829] }, // Inst #1783 = FNEG_D32 + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1782 = FMUL_W + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1781 = FMUL_S_MMR6 + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1780 = FMUL_S_MM + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1779 = FMUL_S + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1778 = FMUL_PS64 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1777 = FMUL_D64_MM + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1776 = FMUL_D64 + { 3, &MipsDescs.OperandInfo[831] }, // Inst #1775 = FMUL_D32_MM + { 3, &MipsDescs.OperandInfo[831] }, // Inst #1774 = FMUL_D32 + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1773 = FMUL_D + { 4, &MipsDescs.OperandInfo[194] }, // Inst #1772 = FMSUB_W + { 4, &MipsDescs.OperandInfo[190] }, // Inst #1771 = FMSUB_D + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1770 = FMOV_S_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1769 = FMOV_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1768 = FMOV_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1767 = FMOV_D_MMR6 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1766 = FMOV_D64_MM + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1765 = FMOV_D64 + { 2, &MipsDescs.OperandInfo[829] }, // Inst #1764 = FMOV_D32_MM + { 2, &MipsDescs.OperandInfo[829] }, // Inst #1763 = FMOV_D32 + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1762 = FMIN_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1761 = FMIN_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1760 = FMIN_A_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1759 = FMIN_A_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1758 = FMAX_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1757 = FMAX_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1756 = FMAX_A_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1755 = FMAX_A_D + { 4, &MipsDescs.OperandInfo[194] }, // Inst #1754 = FMADD_W + { 4, &MipsDescs.OperandInfo[190] }, // Inst #1753 = FMADD_D + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1752 = FLOOR_W_S_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1751 = FLOOR_W_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1750 = FLOOR_W_S + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1749 = FLOOR_W_MM + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1748 = FLOOR_W_D_MMR6 + { 2, &MipsDescs.OperandInfo[697] }, // Inst #1747 = FLOOR_W_D64 + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1746 = FLOOR_W_D32 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1745 = FLOOR_L_S_MMR6 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1744 = FLOOR_L_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1743 = FLOOR_L_D_MMR6 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1742 = FLOOR_L_D64 + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1741 = FLOG2_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1740 = FLOG2_D + { 2, &MipsDescs.OperandInfo[862] }, // Inst #1739 = FILL_W + { 2, &MipsDescs.OperandInfo[860] }, // Inst #1738 = FILL_H + { 2, &MipsDescs.OperandInfo[858] }, // Inst #1737 = FILL_D + { 2, &MipsDescs.OperandInfo[856] }, // Inst #1736 = FILL_B + { 2, &MipsDescs.OperandInfo[854] }, // Inst #1735 = FFQR_W + { 2, &MipsDescs.OperandInfo[852] }, // Inst #1734 = FFQR_D + { 2, &MipsDescs.OperandInfo[854] }, // Inst #1733 = FFQL_W + { 2, &MipsDescs.OperandInfo[852] }, // Inst #1732 = FFQL_D + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1731 = FFINT_U_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1730 = FFINT_U_D + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1729 = FFINT_S_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1728 = FFINT_S_D + { 2, &MipsDescs.OperandInfo[854] }, // Inst #1727 = FEXUPR_W + { 2, &MipsDescs.OperandInfo[852] }, // Inst #1726 = FEXUPR_D + { 2, &MipsDescs.OperandInfo[854] }, // Inst #1725 = FEXUPL_W + { 2, &MipsDescs.OperandInfo[852] }, // Inst #1724 = FEXUPL_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1723 = FEXP2_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1722 = FEXP2_D + { 3, &MipsDescs.OperandInfo[849] }, // Inst #1721 = FEXDO_W + { 3, &MipsDescs.OperandInfo[846] }, // Inst #1720 = FEXDO_H + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1719 = FDIV_W + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1718 = FDIV_S_MMR6 + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1717 = FDIV_S_MM + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1716 = FDIV_S + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1715 = FDIV_D64_MM + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1714 = FDIV_D64 + { 3, &MipsDescs.OperandInfo[831] }, // Inst #1713 = FDIV_D32_MM + { 3, &MipsDescs.OperandInfo[831] }, // Inst #1712 = FDIV_D32 + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1711 = FDIV_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1710 = FCUN_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1709 = FCUN_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1708 = FCUNE_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1707 = FCUNE_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1706 = FCULT_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1705 = FCULT_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1704 = FCULE_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1703 = FCULE_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1702 = FCUEQ_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1701 = FCUEQ_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1700 = FCOR_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1699 = FCOR_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1698 = FCNE_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1697 = FCNE_D + { 3, &MipsDescs.OperandInfo[843] }, // Inst #1696 = FCMP_S32_MM + { 3, &MipsDescs.OperandInfo[843] }, // Inst #1695 = FCMP_S32 + { 3, &MipsDescs.OperandInfo[840] }, // Inst #1694 = FCMP_D64 + { 3, &MipsDescs.OperandInfo[837] }, // Inst #1693 = FCMP_D32_MM + { 3, &MipsDescs.OperandInfo[837] }, // Inst #1692 = FCMP_D32 + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1691 = FCLT_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1690 = FCLT_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1689 = FCLE_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1688 = FCLE_D + { 2, &MipsDescs.OperandInfo[244] }, // Inst #1687 = FCLASS_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #1686 = FCLASS_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1685 = FCEQ_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1684 = FCEQ_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1683 = FCAF_W + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1682 = FCAF_D + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1681 = FADD_W + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1680 = FADD_S_MMR6 + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1679 = FADD_S_MM + { 3, &MipsDescs.OperandInfo[834] }, // Inst #1678 = FADD_S + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1677 = FADD_PS64 + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1676 = FADD_D64_MM + { 3, &MipsDescs.OperandInfo[575] }, // Inst #1675 = FADD_D64 + { 3, &MipsDescs.OperandInfo[831] }, // Inst #1674 = FADD_D32_MM + { 3, &MipsDescs.OperandInfo[831] }, // Inst #1673 = FADD_D32 + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1672 = FADD_D + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1671 = FABS_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1670 = FABS_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1669 = FABS_D64_MM + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1668 = FABS_D64 + { 2, &MipsDescs.OperandInfo[829] }, // Inst #1667 = FABS_D32_MM + { 2, &MipsDescs.OperandInfo[829] }, // Inst #1666 = FABS_D32 + { 4, &MipsDescs.OperandInfo[825] }, // Inst #1665 = EXT_NM + { 4, &MipsDescs.OperandInfo[715] }, // Inst #1664 = EXT_MMR6 + { 4, &MipsDescs.OperandInfo[715] }, // Inst #1663 = EXT_MM + { 4, &MipsDescs.OperandInfo[142] }, // Inst #1662 = EXTW_NM + { 4, &MipsDescs.OperandInfo[707] }, // Inst #1661 = EXTS32 + { 4, &MipsDescs.OperandInfo[707] }, // Inst #1660 = EXTS + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1659 = EXTR_W_MM + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1658 = EXTR_W + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1657 = EXTR_S_H_MM + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1656 = EXTR_S_H + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1655 = EXTR_R_W_MM + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1654 = EXTR_R_W + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1653 = EXTR_RS_W_MM + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1652 = EXTR_RS_W + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1651 = EXTRV_W_MM + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1650 = EXTRV_W + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1649 = EXTRV_S_H_MM + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1648 = EXTRV_S_H + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1647 = EXTRV_R_W_MM + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1646 = EXTRV_R_W + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1645 = EXTRV_RS_W_MM + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1644 = EXTRV_RS_W + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1643 = EXTP_MM + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1642 = EXTPV_MM + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1641 = EXTPV + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1640 = EXTPDP_MM + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1639 = EXTPDPV_MM + { 3, &MipsDescs.OperandInfo[822] }, // Inst #1638 = EXTPDPV + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1637 = EXTPDP + { 3, &MipsDescs.OperandInfo[819] }, // Inst #1636 = EXTP + { 4, &MipsDescs.OperandInfo[715] }, // Inst #1635 = EXT + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1634 = EVP_MMR6 + { 1, &MipsDescs.OperandInfo[311] }, // Inst #1633 = EVPE_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1632 = EVPE + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1631 = EVP + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1630 = ERET_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1629 = ERET_MMR6 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1628 = ERET_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1627 = ERETNC_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1626 = ERETNC_MMR6 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1625 = ERETNC + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1624 = ERET + { 1, &MipsDescs.OperandInfo[311] }, // Inst #1623 = EMT_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1622 = EMT + { 1, &MipsDescs.OperandInfo[311] }, // Inst #1621 = EI_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1620 = EI_MMR6 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1619 = EI_MM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1618 = EI + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1617 = EHB_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1616 = EHB_MMR6 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1615 = EHB_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1614 = EHB + { 2, &MipsDescs.OperandInfo[419] }, // Inst #1613 = DivuRxRy16 + { 2, &MipsDescs.OperandInfo[419] }, // Inst #1612 = DivRxRy16 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1611 = DVP_MMR6 + { 1, &MipsDescs.OperandInfo[311] }, // Inst #1610 = DVPE_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1609 = DVPE + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1608 = DVP + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1607 = DUDIV + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1606 = DSUBu + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1605 = DSUB + { 3, &MipsDescs.OperandInfo[814] }, // Inst #1604 = DSRLV + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1603 = DSRL32 + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1602 = DSRL + { 3, &MipsDescs.OperandInfo[814] }, // Inst #1601 = DSRAV + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1600 = DSRA32 + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1599 = DSRA + { 3, &MipsDescs.OperandInfo[814] }, // Inst #1598 = DSLLV + { 2, &MipsDescs.OperandInfo[817] }, // Inst #1597 = DSLL64_32 + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1596 = DSLL32 + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1595 = DSLL + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1594 = DSHD + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1593 = DSDIV + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1592 = DSBH + { 3, &MipsDescs.OperandInfo[814] }, // Inst #1591 = DROTRV + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1590 = DROTR32 + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1589 = DROTR + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1588 = DPS_W_PH_MMR2 + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1587 = DPS_W_PH + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1586 = DPSX_W_PH_MMR2 + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1585 = DPSX_W_PH + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1584 = DPSU_H_QBR_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1583 = DPSU_H_QBR + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1582 = DPSU_H_QBL_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1581 = DPSU_H_QBL + { 4, &MipsDescs.OperandInfo[806] }, // Inst #1580 = DPSUB_U_W + { 4, &MipsDescs.OperandInfo[802] }, // Inst #1579 = DPSUB_U_H + { 4, &MipsDescs.OperandInfo[798] }, // Inst #1578 = DPSUB_U_D + { 4, &MipsDescs.OperandInfo[806] }, // Inst #1577 = DPSUB_S_W + { 4, &MipsDescs.OperandInfo[802] }, // Inst #1576 = DPSUB_S_H + { 4, &MipsDescs.OperandInfo[798] }, // Inst #1575 = DPSUB_S_D + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1574 = DPSQ_S_W_PH_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1573 = DPSQ_S_W_PH + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1572 = DPSQ_SA_L_W_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1571 = DPSQ_SA_L_W + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1570 = DPSQX_S_W_PH_MMR2 + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1569 = DPSQX_S_W_PH + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1568 = DPSQX_SA_W_PH_MMR2 + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1567 = DPSQX_SA_W_PH + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1566 = DPOP + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1565 = DPA_W_PH_MMR2 + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1564 = DPA_W_PH + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1563 = DPAX_W_PH_MMR2 + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1562 = DPAX_W_PH + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1561 = DPAU_H_QBR_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1560 = DPAU_H_QBR + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1559 = DPAU_H_QBL_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1558 = DPAU_H_QBL + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1557 = DPAQ_S_W_PH_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1556 = DPAQ_S_W_PH + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1555 = DPAQ_SA_L_W_MM + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1554 = DPAQ_SA_L_W + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1553 = DPAQX_S_W_PH_MMR2 + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1552 = DPAQX_S_W_PH + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1551 = DPAQX_SA_W_PH_MMR2 + { 4, &MipsDescs.OperandInfo[810] }, // Inst #1550 = DPAQX_SA_W_PH + { 4, &MipsDescs.OperandInfo[806] }, // Inst #1549 = DPADD_U_W + { 4, &MipsDescs.OperandInfo[802] }, // Inst #1548 = DPADD_U_H + { 4, &MipsDescs.OperandInfo[798] }, // Inst #1547 = DPADD_U_D + { 4, &MipsDescs.OperandInfo[806] }, // Inst #1546 = DPADD_S_W + { 4, &MipsDescs.OperandInfo[802] }, // Inst #1545 = DPADD_S_H + { 4, &MipsDescs.OperandInfo[798] }, // Inst #1544 = DPADD_S_D + { 3, &MipsDescs.OperandInfo[795] }, // Inst #1543 = DOTP_U_W + { 3, &MipsDescs.OperandInfo[792] }, // Inst #1542 = DOTP_U_H + { 3, &MipsDescs.OperandInfo[789] }, // Inst #1541 = DOTP_U_D + { 3, &MipsDescs.OperandInfo[795] }, // Inst #1540 = DOTP_S_W + { 3, &MipsDescs.OperandInfo[792] }, // Inst #1539 = DOTP_S_H + { 3, &MipsDescs.OperandInfo[789] }, // Inst #1538 = DOTP_S_D + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1537 = DMUL_R6 + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1536 = DMULU + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1535 = DMULTu + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1534 = DMULT + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1533 = DMUL + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1532 = DMUHU + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1531 = DMUH + { 1, &MipsDescs.OperandInfo[311] }, // Inst #1530 = DMT_NM + { 3, &MipsDescs.OperandInfo[783] }, // Inst #1529 = DMTGC0 + { 2, &MipsDescs.OperandInfo[359] }, // Inst #1528 = DMTC2_OCTEON + { 3, &MipsDescs.OperandInfo[786] }, // Inst #1527 = DMTC2 + { 2, &MipsDescs.OperandInfo[429] }, // Inst #1526 = DMTC1 + { 3, &MipsDescs.OperandInfo[783] }, // Inst #1525 = DMTC0 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1524 = DMT + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1523 = DMODU + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1522 = DMOD + { 3, &MipsDescs.OperandInfo[775] }, // Inst #1521 = DMFGC0 + { 2, &MipsDescs.OperandInfo[359] }, // Inst #1520 = DMFC2_OCTEON + { 3, &MipsDescs.OperandInfo[780] }, // Inst #1519 = DMFC2 + { 2, &MipsDescs.OperandInfo[778] }, // Inst #1518 = DMFC1 + { 3, &MipsDescs.OperandInfo[775] }, // Inst #1517 = DMFC0 + { 4, &MipsDescs.OperandInfo[766] }, // Inst #1516 = DLSA_R6 + { 4, &MipsDescs.OperandInfo[766] }, // Inst #1515 = DLSA + { 1, &MipsDescs.OperandInfo[311] }, // Inst #1514 = DI_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1513 = DI_MMR6 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1512 = DI_MM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1511 = DIV_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1510 = DIV_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1509 = DIV_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1508 = DIV_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1507 = DIV_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1506 = DIV_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1505 = DIV_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1504 = DIV_S_B + { 3, &MipsDescs.OperandInfo[596] }, // Inst #1503 = DIV_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1502 = DIV_MMR6 + { 3, &MipsDescs.OperandInfo[596] }, // Inst #1501 = DIVU_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1500 = DIVU_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1499 = DIVU + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1498 = DIV + { 5, &MipsDescs.OperandInfo[770] }, // Inst #1497 = DINSU + { 5, &MipsDescs.OperandInfo[770] }, // Inst #1496 = DINSM + { 5, &MipsDescs.OperandInfo[770] }, // Inst #1495 = DINS + { 1, &MipsDescs.OperandInfo[189] }, // Inst #1494 = DI + { 4, &MipsDescs.OperandInfo[707] }, // Inst #1493 = DEXTU + { 4, &MipsDescs.OperandInfo[707] }, // Inst #1492 = DEXTM + { 4, &MipsDescs.OperandInfo[711] }, // Inst #1491 = DEXT64_32 + { 4, &MipsDescs.OperandInfo[707] }, // Inst #1490 = DEXT + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1489 = DERET_NM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1488 = DERET_MMR6 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1487 = DERET_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1486 = DERET + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1485 = DDIVU + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1484 = DDIV + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1483 = DCLZ_R6 + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1482 = DCLZ + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1481 = DCLO_R6 + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1480 = DCLO + { 2, &MipsDescs.OperandInfo[394] }, // Inst #1479 = DBITSWAP + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1478 = DAUI + { 3, &MipsDescs.OperandInfo[763] }, // Inst #1477 = DATI + { 4, &MipsDescs.OperandInfo[766] }, // Inst #1476 = DALIGN + { 3, &MipsDescs.OperandInfo[763] }, // Inst #1475 = DAHI + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1474 = DADDu + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1473 = DADDiu + { 3, &MipsDescs.OperandInfo[224] }, // Inst #1472 = DADDi + { 3, &MipsDescs.OperandInfo[227] }, // Inst #1471 = DADD + { 2, &MipsDescs.OperandInfo[618] }, // Inst #1470 = CmpiRxImmX16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #1469 = CmpiRxImm16 + { 2, &MipsDescs.OperandInfo[419] }, // Inst #1468 = CmpRxRy16 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1467 = C_UN_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1466 = C_UN_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1465 = C_UN_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1464 = C_UN_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1463 = C_UN_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1462 = C_UN_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1461 = C_ULT_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1460 = C_ULT_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1459 = C_ULT_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1458 = C_ULT_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1457 = C_ULT_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1456 = C_ULT_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1455 = C_ULE_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1454 = C_ULE_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1453 = C_ULE_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1452 = C_ULE_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1451 = C_ULE_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1450 = C_ULE_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1449 = C_UEQ_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1448 = C_UEQ_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1447 = C_UEQ_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1446 = C_UEQ_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1445 = C_UEQ_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1444 = C_UEQ_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1443 = C_SF_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1442 = C_SF_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1441 = C_SF_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1440 = C_SF_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1439 = C_SF_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1438 = C_SF_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1437 = C_SEQ_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1436 = C_SEQ_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1435 = C_SEQ_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1434 = C_SEQ_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1433 = C_SEQ_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1432 = C_SEQ_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1431 = C_OLT_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1430 = C_OLT_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1429 = C_OLT_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1428 = C_OLT_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1427 = C_OLT_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1426 = C_OLT_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1425 = C_OLE_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1424 = C_OLE_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1423 = C_OLE_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1422 = C_OLE_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1421 = C_OLE_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1420 = C_OLE_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1419 = C_NGT_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1418 = C_NGT_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1417 = C_NGT_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1416 = C_NGT_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1415 = C_NGT_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1414 = C_NGT_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1413 = C_NGL_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1412 = C_NGL_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1411 = C_NGL_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1410 = C_NGL_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1409 = C_NGL_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1408 = C_NGL_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1407 = C_NGLE_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1406 = C_NGLE_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1405 = C_NGLE_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1404 = C_NGLE_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1403 = C_NGLE_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1402 = C_NGLE_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1401 = C_NGE_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1400 = C_NGE_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1399 = C_NGE_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1398 = C_NGE_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1397 = C_NGE_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1396 = C_NGE_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1395 = C_LT_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1394 = C_LT_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1393 = C_LT_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1392 = C_LT_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1391 = C_LT_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1390 = C_LT_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1389 = C_LE_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1388 = C_LE_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1387 = C_LE_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1386 = C_LE_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1385 = C_LE_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1384 = C_LE_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1383 = C_F_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1382 = C_F_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1381 = C_F_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1380 = C_F_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1379 = C_F_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1378 = C_F_D32 + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1377 = C_EQ_S_MM + { 3, &MipsDescs.OperandInfo[760] }, // Inst #1376 = C_EQ_S + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1375 = C_EQ_D64_MM + { 3, &MipsDescs.OperandInfo[757] }, // Inst #1374 = C_EQ_D64 + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1373 = C_EQ_D32_MM + { 3, &MipsDescs.OperandInfo[754] }, // Inst #1372 = C_EQ_D32 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1371 = CVT_W_S_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1370 = CVT_W_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1369 = CVT_W_S + { 2, &MipsDescs.OperandInfo[697] }, // Inst #1368 = CVT_W_D64_MM + { 2, &MipsDescs.OperandInfo[697] }, // Inst #1367 = CVT_W_D64 + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1366 = CVT_W_D32_MM + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1365 = CVT_W_D32 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1364 = CVT_S_W_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1363 = CVT_S_W_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1362 = CVT_S_W + { 2, &MipsDescs.OperandInfo[697] }, // Inst #1361 = CVT_S_PU64 + { 2, &MipsDescs.OperandInfo[697] }, // Inst #1360 = CVT_S_PL64 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1359 = CVT_S_L_MMR6 + { 2, &MipsDescs.OperandInfo[697] }, // Inst #1358 = CVT_S_L + { 2, &MipsDescs.OperandInfo[697] }, // Inst #1357 = CVT_S_D64_MM + { 2, &MipsDescs.OperandInfo[697] }, // Inst #1356 = CVT_S_D64 + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1355 = CVT_S_D32_MM + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1354 = CVT_S_D32 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1353 = CVT_PW_PS64 + { 3, &MipsDescs.OperandInfo[751] }, // Inst #1352 = CVT_PS_S64 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1351 = CVT_PS_PW64 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1350 = CVT_L_S_MMR6 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1349 = CVT_L_S_MM + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1348 = CVT_L_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1347 = CVT_L_D_MMR6 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1346 = CVT_L_D64_MM + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1345 = CVT_L_D64 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1344 = CVT_D_L_MMR6 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1343 = CVT_D64_W_MM + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1342 = CVT_D64_W + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1341 = CVT_D64_S_MM + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1340 = CVT_D64_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1339 = CVT_D64_L + { 2, &MipsDescs.OperandInfo[749] }, // Inst #1338 = CVT_D32_W_MM + { 2, &MipsDescs.OperandInfo[749] }, // Inst #1337 = CVT_D32_W + { 2, &MipsDescs.OperandInfo[749] }, // Inst #1336 = CVT_D32_S_MM + { 2, &MipsDescs.OperandInfo[749] }, // Inst #1335 = CVT_D32_S + { 2, &MipsDescs.OperandInfo[747] }, // Inst #1334 = CTCMSA + { 2, &MipsDescs.OperandInfo[745] }, // Inst #1333 = CTC2_MM + { 2, &MipsDescs.OperandInfo[743] }, // Inst #1332 = CTC1_MM + { 2, &MipsDescs.OperandInfo[743] }, // Inst #1331 = CTC1 + { 3, &MipsDescs.OperandInfo[740] }, // Inst #1330 = CRC32W_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1329 = CRC32W + { 3, &MipsDescs.OperandInfo[740] }, // Inst #1328 = CRC32H_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1327 = CRC32H + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1326 = CRC32D + { 3, &MipsDescs.OperandInfo[740] }, // Inst #1325 = CRC32CW_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1324 = CRC32CW + { 3, &MipsDescs.OperandInfo[740] }, // Inst #1323 = CRC32CH_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1322 = CRC32CH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1321 = CRC32CD + { 3, &MipsDescs.OperandInfo[740] }, // Inst #1320 = CRC32CB_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1319 = CRC32CB + { 3, &MipsDescs.OperandInfo[740] }, // Inst #1318 = CRC32B_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #1317 = CRC32B + { 3, &MipsDescs.OperandInfo[737] }, // Inst #1316 = COPY_U_W + { 3, &MipsDescs.OperandInfo[734] }, // Inst #1315 = COPY_U_H + { 3, &MipsDescs.OperandInfo[728] }, // Inst #1314 = COPY_U_B + { 3, &MipsDescs.OperandInfo[737] }, // Inst #1313 = COPY_S_W + { 3, &MipsDescs.OperandInfo[734] }, // Inst #1312 = COPY_S_H + { 3, &MipsDescs.OperandInfo[731] }, // Inst #1311 = COPY_S_D + { 3, &MipsDescs.OperandInfo[728] }, // Inst #1310 = COPY_S_B + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1309 = CMP_UN_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1308 = CMP_UN_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1307 = CMP_UN_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1306 = CMP_UN_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1305 = CMP_ULT_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1304 = CMP_ULT_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1303 = CMP_ULT_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1302 = CMP_ULT_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1301 = CMP_ULE_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1300 = CMP_ULE_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1299 = CMP_ULE_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1298 = CMP_ULE_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1297 = CMP_UEQ_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1296 = CMP_UEQ_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1295 = CMP_UEQ_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1294 = CMP_UEQ_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1293 = CMP_SUN_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1292 = CMP_SUN_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1291 = CMP_SUN_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1290 = CMP_SUN_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1289 = CMP_SULT_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1288 = CMP_SULT_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1287 = CMP_SULT_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1286 = CMP_SULT_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1285 = CMP_SULE_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1284 = CMP_SULE_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1283 = CMP_SULE_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1282 = CMP_SULE_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1281 = CMP_SUEQ_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1280 = CMP_SUEQ_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1279 = CMP_SUEQ_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1278 = CMP_SUEQ_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1277 = CMP_SLT_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1276 = CMP_SLT_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1275 = CMP_SLT_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1274 = CMP_SLT_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1273 = CMP_SLE_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1272 = CMP_SLE_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1271 = CMP_SLE_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1270 = CMP_SLE_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1269 = CMP_SEQ_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1268 = CMP_SEQ_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1267 = CMP_SEQ_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1266 = CMP_SEQ_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1265 = CMP_SAF_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1264 = CMP_SAF_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1263 = CMP_SAF_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1262 = CMP_SAF_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1261 = CMP_LT_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1260 = CMP_LT_S + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1259 = CMP_LT_PH_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1258 = CMP_LT_PH + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1257 = CMP_LT_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1256 = CMP_LT_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1255 = CMP_LE_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1254 = CMP_LE_S + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1253 = CMP_LE_PH_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1252 = CMP_LE_PH + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1251 = CMP_LE_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1250 = CMP_LE_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1249 = CMP_F_S + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1248 = CMP_F_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1247 = CMP_EQ_S_MMR6 + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1246 = CMP_EQ_S + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1245 = CMP_EQ_PH_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1244 = CMP_EQ_PH + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1243 = CMP_EQ_D_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1242 = CMP_EQ_D + { 3, &MipsDescs.OperandInfo[725] }, // Inst #1241 = CMP_AF_S_MMR6 + { 3, &MipsDescs.OperandInfo[722] }, // Inst #1240 = CMP_AF_D_MMR6 + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1239 = CMPU_LT_QB_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1238 = CMPU_LT_QB + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1237 = CMPU_LE_QB_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1236 = CMPU_LE_QB + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1235 = CMPU_EQ_QB_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #1234 = CMPU_EQ_QB + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1233 = CMPGU_LT_QB_MM + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1232 = CMPGU_LT_QB + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1231 = CMPGU_LE_QB_MM + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1230 = CMPGU_LE_QB + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1229 = CMPGU_EQ_QB_MM + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1228 = CMPGU_EQ_QB + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1227 = CMPGDU_LT_QB_MMR2 + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1226 = CMPGDU_LT_QB + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1225 = CMPGDU_LE_QB_MMR2 + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1224 = CMPGDU_LE_QB + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1223 = CMPGDU_EQ_QB_MMR2 + { 3, &MipsDescs.OperandInfo[719] }, // Inst #1222 = CMPGDU_EQ_QB + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1221 = CLZ_R6 + { 2, &MipsDescs.OperandInfo[416] }, // Inst #1220 = CLZ_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1219 = CLZ_MMR6 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1218 = CLZ_MM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1217 = CLZ + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1216 = CLT_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1215 = CLT_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1214 = CLT_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1213 = CLT_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1212 = CLT_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1211 = CLT_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1210 = CLT_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1209 = CLT_S_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #1208 = CLTI_U_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #1207 = CLTI_U_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #1206 = CLTI_U_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #1205 = CLTI_U_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #1204 = CLTI_S_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #1203 = CLTI_S_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #1202 = CLTI_S_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #1201 = CLTI_S_B + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1200 = CLO_R6 + { 2, &MipsDescs.OperandInfo[416] }, // Inst #1199 = CLO_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1198 = CLO_MMR6 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1197 = CLO_MM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1196 = CLO + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1195 = CLE_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1194 = CLE_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1193 = CLE_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1192 = CLE_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1191 = CLE_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1190 = CLE_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1189 = CLE_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1188 = CLE_S_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #1187 = CLEI_U_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #1186 = CLEI_U_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #1185 = CLEI_U_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #1184 = CLEI_U_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #1183 = CLEI_S_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #1182 = CLEI_S_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #1181 = CLEI_S_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #1180 = CLEI_S_B + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1179 = CLASS_S_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1178 = CLASS_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1177 = CLASS_D_MMR6 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1176 = CLASS_D + { 4, &MipsDescs.OperandInfo[715] }, // Inst #1175 = CINS_i32 + { 4, &MipsDescs.OperandInfo[711] }, // Inst #1174 = CINS64_32 + { 4, &MipsDescs.OperandInfo[707] }, // Inst #1173 = CINS32 + { 4, &MipsDescs.OperandInfo[707] }, // Inst #1172 = CINS + { 2, &MipsDescs.OperandInfo[705] }, // Inst #1171 = CFCMSA + { 2, &MipsDescs.OperandInfo[703] }, // Inst #1170 = CFC2_MM + { 2, &MipsDescs.OperandInfo[701] }, // Inst #1169 = CFC1_MM + { 2, &MipsDescs.OperandInfo[701] }, // Inst #1168 = CFC1 + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1167 = CEQ_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1166 = CEQ_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1165 = CEQ_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1164 = CEQ_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #1163 = CEQI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #1162 = CEQI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #1161 = CEQI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #1160 = CEQI_B + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1159 = CEIL_W_S_MMR6 + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1158 = CEIL_W_S_MM + { 2, &MipsDescs.OperandInfo[699] }, // Inst #1157 = CEIL_W_S + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1156 = CEIL_W_MM + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1155 = CEIL_W_D_MMR6 + { 2, &MipsDescs.OperandInfo[697] }, // Inst #1154 = CEIL_W_D64 + { 2, &MipsDescs.OperandInfo[695] }, // Inst #1153 = CEIL_W_D32 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1152 = CEIL_L_S_MMR6 + { 2, &MipsDescs.OperandInfo[693] }, // Inst #1151 = CEIL_L_S + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1150 = CEIL_L_D_MMR6 + { 2, &MipsDescs.OperandInfo[691] }, // Inst #1149 = CEIL_L_D64 + { 3, &MipsDescs.OperandInfo[688] }, // Inst #1148 = CACHE_R6 + { 3, &MipsDescs.OperandInfo[354] }, // Inst #1147 = CACHE_NM + { 3, &MipsDescs.OperandInfo[688] }, // Inst #1146 = CACHE_MMR6 + { 3, &MipsDescs.OperandInfo[688] }, // Inst #1145 = CACHE_MM + { 3, &MipsDescs.OperandInfo[688] }, // Inst #1144 = CACHEE_MM + { 3, &MipsDescs.OperandInfo[688] }, // Inst #1143 = CACHEE + { 3, &MipsDescs.OperandInfo[688] }, // Inst #1142 = CACHE + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1141 = BtnezX16 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1140 = Btnez16 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1139 = BteqzX16 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1138 = Bteqz16 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1137 = Break16 + { 2, &MipsDescs.OperandInfo[686] }, // Inst #1136 = BnezRxImmX16 + { 2, &MipsDescs.OperandInfo[686] }, // Inst #1135 = BnezRxImm16 + { 1, &MipsDescs.OperandInfo[182] }, // Inst #1134 = BimmX16 + { 1, &MipsDescs.OperandInfo[182] }, // Inst #1133 = Bimm16 + { 2, &MipsDescs.OperandInfo[686] }, // Inst #1132 = BeqzRxImmX16 + { 2, &MipsDescs.OperandInfo[686] }, // Inst #1131 = BeqzRxImm16 + { 2, &MipsDescs.OperandInfo[682] }, // Inst #1130 = BZ_W + { 2, &MipsDescs.OperandInfo[676] }, // Inst #1129 = BZ_V + { 2, &MipsDescs.OperandInfo[680] }, // Inst #1128 = BZ_H + { 2, &MipsDescs.OperandInfo[678] }, // Inst #1127 = BZ_D + { 2, &MipsDescs.OperandInfo[676] }, // Inst #1126 = BZ_B + { 2, &MipsDescs.OperandInfo[416] }, // Inst #1125 = BYTEREVW_NM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1124 = BSET_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1123 = BSET_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1122 = BSET_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1121 = BSET_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #1120 = BSETI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #1119 = BSETI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #1118 = BSETI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #1117 = BSETI_B + { 4, &MipsDescs.OperandInfo[672] }, // Inst #1116 = BSEL_V + { 4, &MipsDescs.OperandInfo[656] }, // Inst #1115 = BSELI_B + { 2, &MipsDescs.OperandInfo[684] }, // Inst #1114 = BRSC_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1113 = BREAK_NM + { 2, &MipsDescs.OperandInfo[13] }, // Inst #1112 = BREAK_MMR6 + { 2, &MipsDescs.OperandInfo[13] }, // Inst #1111 = BREAK_MM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1110 = BREAK16_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1109 = BREAK16_MMR6 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #1108 = BREAK16_MM + { 2, &MipsDescs.OperandInfo[13] }, // Inst #1107 = BREAK + { 1, &MipsDescs.OperandInfo[182] }, // Inst #1106 = BPOSGE32_MM + { 1, &MipsDescs.OperandInfo[182] }, // Inst #1105 = BPOSGE32C_MMR3 + { 1, &MipsDescs.OperandInfo[182] }, // Inst #1104 = BPOSGE32 + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1103 = BOVC_MMR6 + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1102 = BOVC + { 2, &MipsDescs.OperandInfo[682] }, // Inst #1101 = BNZ_W + { 2, &MipsDescs.OperandInfo[676] }, // Inst #1100 = BNZ_V + { 2, &MipsDescs.OperandInfo[680] }, // Inst #1099 = BNZ_H + { 2, &MipsDescs.OperandInfo[678] }, // Inst #1098 = BNZ_D + { 2, &MipsDescs.OperandInfo[676] }, // Inst #1097 = BNZ_B + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1096 = BNVC_MMR6 + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1095 = BNVC + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1094 = BNE_MM + { 2, &MipsDescs.OperandInfo[609] }, // Inst #1093 = BNEZC_NM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1092 = BNEZC_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1091 = BNEZC_MM + { 2, &MipsDescs.OperandInfo[352] }, // Inst #1090 = BNEZC64 + { 2, &MipsDescs.OperandInfo[654] }, // Inst #1089 = BNEZC16_NM + { 2, &MipsDescs.OperandInfo[652] }, // Inst #1088 = BNEZC16_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1087 = BNEZC + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1086 = BNEZALC_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1085 = BNEZALC + { 2, &MipsDescs.OperandInfo[652] }, // Inst #1084 = BNEZ16_MM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1083 = BNEL + { 3, &MipsDescs.OperandInfo[631] }, // Inst #1082 = BNEIC_NM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #1081 = BNEG_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #1080 = BNEG_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #1079 = BNEG_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #1078 = BNEG_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #1077 = BNEGI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #1076 = BNEGI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #1075 = BNEGI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #1074 = BNEGI_B + { 3, &MipsDescs.OperandInfo[649] }, // Inst #1073 = BNECzero_NM + { 3, &MipsDescs.OperandInfo[646] }, // Inst #1072 = BNEC_NM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1071 = BNEC_MMR6 + { 3, &MipsDescs.OperandInfo[344] }, // Inst #1070 = BNEC64 + { 3, &MipsDescs.OperandInfo[643] }, // Inst #1069 = BNEC16_NM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1068 = BNEC + { 3, &MipsDescs.OperandInfo[344] }, // Inst #1067 = BNE64 + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1066 = BNE + { 4, &MipsDescs.OperandInfo[672] }, // Inst #1065 = BMZ_V + { 4, &MipsDescs.OperandInfo[656] }, // Inst #1064 = BMZI_B + { 4, &MipsDescs.OperandInfo[672] }, // Inst #1063 = BMNZ_V + { 4, &MipsDescs.OperandInfo[656] }, // Inst #1062 = BMNZI_B + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1061 = BLTZ_MM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1060 = BLTZL + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1059 = BLTZC_MMR6 + { 2, &MipsDescs.OperandInfo[352] }, // Inst #1058 = BLTZC64 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1057 = BLTZC + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1056 = BLTZAL_MM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1055 = BLTZALS_MM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1054 = BLTZALL + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1053 = BLTZALC_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1052 = BLTZALC + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1051 = BLTZAL + { 2, &MipsDescs.OperandInfo[352] }, // Inst #1050 = BLTZ64 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1049 = BLTZ + { 3, &MipsDescs.OperandInfo[646] }, // Inst #1048 = BLTUC_NM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1047 = BLTUC_MMR6 + { 3, &MipsDescs.OperandInfo[344] }, // Inst #1046 = BLTUC64 + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1045 = BLTUC + { 3, &MipsDescs.OperandInfo[631] }, // Inst #1044 = BLTIUC_NM + { 3, &MipsDescs.OperandInfo[631] }, // Inst #1043 = BLTIC_NM + { 3, &MipsDescs.OperandInfo[646] }, // Inst #1042 = BLTC_NM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1041 = BLTC_MMR6 + { 3, &MipsDescs.OperandInfo[344] }, // Inst #1040 = BLTC64 + { 3, &MipsDescs.OperandInfo[186] }, // Inst #1039 = BLTC + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1038 = BLEZ_MM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1037 = BLEZL + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1036 = BLEZC_MMR6 + { 2, &MipsDescs.OperandInfo[352] }, // Inst #1035 = BLEZC64 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1034 = BLEZC + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1033 = BLEZALC_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1032 = BLEZALC + { 2, &MipsDescs.OperandInfo[352] }, // Inst #1031 = BLEZ64 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1030 = BLEZ + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1029 = BITSWAP_MMR6 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1028 = BITSWAP + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1027 = BITREV_MM + { 2, &MipsDescs.OperandInfo[416] }, // Inst #1026 = BITREVW_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #1025 = BITREV + { 4, &MipsDescs.OperandInfo[194] }, // Inst #1024 = BINSR_W + { 4, &MipsDescs.OperandInfo[198] }, // Inst #1023 = BINSR_H + { 4, &MipsDescs.OperandInfo[190] }, // Inst #1022 = BINSR_D + { 4, &MipsDescs.OperandInfo[672] }, // Inst #1021 = BINSR_B + { 4, &MipsDescs.OperandInfo[668] }, // Inst #1020 = BINSRI_W + { 4, &MipsDescs.OperandInfo[664] }, // Inst #1019 = BINSRI_H + { 4, &MipsDescs.OperandInfo[660] }, // Inst #1018 = BINSRI_D + { 4, &MipsDescs.OperandInfo[656] }, // Inst #1017 = BINSRI_B + { 4, &MipsDescs.OperandInfo[194] }, // Inst #1016 = BINSL_W + { 4, &MipsDescs.OperandInfo[198] }, // Inst #1015 = BINSL_H + { 4, &MipsDescs.OperandInfo[190] }, // Inst #1014 = BINSL_D + { 4, &MipsDescs.OperandInfo[672] }, // Inst #1013 = BINSL_B + { 4, &MipsDescs.OperandInfo[668] }, // Inst #1012 = BINSLI_W + { 4, &MipsDescs.OperandInfo[664] }, // Inst #1011 = BINSLI_H + { 4, &MipsDescs.OperandInfo[660] }, // Inst #1010 = BINSLI_D + { 4, &MipsDescs.OperandInfo[656] }, // Inst #1009 = BINSLI_B + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1008 = BGTZ_MM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1007 = BGTZL + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1006 = BGTZC_MMR6 + { 2, &MipsDescs.OperandInfo[352] }, // Inst #1005 = BGTZC64 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1004 = BGTZC + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1003 = BGTZALC_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1002 = BGTZALC + { 2, &MipsDescs.OperandInfo[352] }, // Inst #1001 = BGTZ64 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #1000 = BGTZ + { 2, &MipsDescs.OperandInfo[350] }, // Inst #999 = BGEZ_MM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #998 = BGEZL + { 2, &MipsDescs.OperandInfo[350] }, // Inst #997 = BGEZC_MMR6 + { 2, &MipsDescs.OperandInfo[352] }, // Inst #996 = BGEZC64 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #995 = BGEZC + { 2, &MipsDescs.OperandInfo[350] }, // Inst #994 = BGEZAL_MM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #993 = BGEZALS_MM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #992 = BGEZALL + { 2, &MipsDescs.OperandInfo[350] }, // Inst #991 = BGEZALC_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #990 = BGEZALC + { 2, &MipsDescs.OperandInfo[350] }, // Inst #989 = BGEZAL + { 2, &MipsDescs.OperandInfo[352] }, // Inst #988 = BGEZ64 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #987 = BGEZ + { 3, &MipsDescs.OperandInfo[646] }, // Inst #986 = BGEUC_NM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #985 = BGEUC_MMR6 + { 3, &MipsDescs.OperandInfo[344] }, // Inst #984 = BGEUC64 + { 3, &MipsDescs.OperandInfo[186] }, // Inst #983 = BGEUC + { 3, &MipsDescs.OperandInfo[631] }, // Inst #982 = BGEIUC_NM + { 3, &MipsDescs.OperandInfo[631] }, // Inst #981 = BGEIC_NM + { 3, &MipsDescs.OperandInfo[646] }, // Inst #980 = BGEC_NM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #979 = BGEC_MMR6 + { 3, &MipsDescs.OperandInfo[344] }, // Inst #978 = BGEC64 + { 3, &MipsDescs.OperandInfo[186] }, // Inst #977 = BGEC + { 3, &MipsDescs.OperandInfo[186] }, // Inst #976 = BEQ_MM + { 2, &MipsDescs.OperandInfo[609] }, // Inst #975 = BEQZC_NM + { 2, &MipsDescs.OperandInfo[350] }, // Inst #974 = BEQZC_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #973 = BEQZC_MM + { 2, &MipsDescs.OperandInfo[352] }, // Inst #972 = BEQZC64 + { 2, &MipsDescs.OperandInfo[654] }, // Inst #971 = BEQZC16_NM + { 2, &MipsDescs.OperandInfo[652] }, // Inst #970 = BEQZC16_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #969 = BEQZC + { 2, &MipsDescs.OperandInfo[350] }, // Inst #968 = BEQZALC_MMR6 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #967 = BEQZALC + { 2, &MipsDescs.OperandInfo[652] }, // Inst #966 = BEQZ16_MM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #965 = BEQL + { 3, &MipsDescs.OperandInfo[631] }, // Inst #964 = BEQIC_NM + { 3, &MipsDescs.OperandInfo[649] }, // Inst #963 = BEQCzero_NM + { 3, &MipsDescs.OperandInfo[646] }, // Inst #962 = BEQC_NM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #961 = BEQC_MMR6 + { 3, &MipsDescs.OperandInfo[344] }, // Inst #960 = BEQC64 + { 3, &MipsDescs.OperandInfo[643] }, // Inst #959 = BEQC16_NM + { 3, &MipsDescs.OperandInfo[186] }, // Inst #958 = BEQC + { 3, &MipsDescs.OperandInfo[344] }, // Inst #957 = BEQ64 + { 3, &MipsDescs.OperandInfo[186] }, // Inst #956 = BEQ + { 1, &MipsDescs.OperandInfo[182] }, // Inst #955 = BC_NM + { 1, &MipsDescs.OperandInfo[182] }, // Inst #954 = BC_MMR6 + { 3, &MipsDescs.OperandInfo[152] }, // Inst #953 = BCLR_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #952 = BCLR_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #951 = BCLR_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #950 = BCLR_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #949 = BCLRI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #948 = BCLRI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #947 = BCLRI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #946 = BCLRI_B + { 2, &MipsDescs.OperandInfo[641] }, // Inst #945 = BC2NEZC_MMR6 + { 2, &MipsDescs.OperandInfo[641] }, // Inst #944 = BC2NEZ + { 2, &MipsDescs.OperandInfo[641] }, // Inst #943 = BC2EQZC_MMR6 + { 2, &MipsDescs.OperandInfo[641] }, // Inst #942 = BC2EQZ + { 2, &MipsDescs.OperandInfo[639] }, // Inst #941 = BC1T_MM + { 2, &MipsDescs.OperandInfo[639] }, // Inst #940 = BC1TL + { 2, &MipsDescs.OperandInfo[639] }, // Inst #939 = BC1T + { 2, &MipsDescs.OperandInfo[637] }, // Inst #938 = BC1NEZC_MMR6 + { 2, &MipsDescs.OperandInfo[637] }, // Inst #937 = BC1NEZ + { 2, &MipsDescs.OperandInfo[639] }, // Inst #936 = BC1F_MM + { 2, &MipsDescs.OperandInfo[639] }, // Inst #935 = BC1FL + { 2, &MipsDescs.OperandInfo[639] }, // Inst #934 = BC1F + { 2, &MipsDescs.OperandInfo[637] }, // Inst #933 = BC1EQZC_MMR6 + { 2, &MipsDescs.OperandInfo[637] }, // Inst #932 = BC1EQZ + { 1, &MipsDescs.OperandInfo[182] }, // Inst #931 = BC16_NM + { 1, &MipsDescs.OperandInfo[182] }, // Inst #930 = BC16_MMR6 + { 1, &MipsDescs.OperandInfo[182] }, // Inst #929 = BC + { 3, &MipsDescs.OperandInfo[631] }, // Inst #928 = BBNEZC_NM + { 3, &MipsDescs.OperandInfo[634] }, // Inst #927 = BBIT132 + { 3, &MipsDescs.OperandInfo[634] }, // Inst #926 = BBIT1 + { 3, &MipsDescs.OperandInfo[634] }, // Inst #925 = BBIT032 + { 3, &MipsDescs.OperandInfo[634] }, // Inst #924 = BBIT0 + { 3, &MipsDescs.OperandInfo[631] }, // Inst #923 = BBEQZC_NM + { 2, &MipsDescs.OperandInfo[629] }, // Inst #922 = BALRSC_NM + { 4, &MipsDescs.OperandInfo[614] }, // Inst #921 = BALIGN_MMR2 + { 4, &MipsDescs.OperandInfo[614] }, // Inst #920 = BALIGN + { 1, &MipsDescs.OperandInfo[182] }, // Inst #919 = BALC_NM + { 1, &MipsDescs.OperandInfo[182] }, // Inst #918 = BALC_MMR6 + { 1, &MipsDescs.OperandInfo[182] }, // Inst #917 = BALC16_NM + { 1, &MipsDescs.OperandInfo[182] }, // Inst #916 = BALC + { 1, &MipsDescs.OperandInfo[182] }, // Inst #915 = BAL + { 3, &MipsDescs.OperandInfo[227] }, // Inst #914 = BADDu + { 1, &MipsDescs.OperandInfo[182] }, // Inst #913 = B16_MM + { 3, &MipsDescs.OperandInfo[626] }, // Inst #912 = AndRxRxRy16 + { 3, &MipsDescs.OperandInfo[421] }, // Inst #911 = AdduRxRyRz16 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #910 = AddiuSpImmX16 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #909 = AddiuSpImm16 + { 3, &MipsDescs.OperandInfo[623] }, // Inst #908 = AddiuRxRyOffMemX16 + { 3, &MipsDescs.OperandInfo[620] }, // Inst #907 = AddiuRxRxImmX16 + { 3, &MipsDescs.OperandInfo[620] }, // Inst #906 = AddiuRxRxImm16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #905 = AddiuRxPcImmX16 + { 2, &MipsDescs.OperandInfo[618] }, // Inst #904 = AddiuRxImmX16 + { 3, &MipsDescs.OperandInfo[152] }, // Inst #903 = AVE_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #902 = AVE_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #901 = AVE_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #900 = AVE_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #899 = AVE_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #898 = AVE_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #897 = AVE_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #896 = AVE_S_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #895 = AVER_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #894 = AVER_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #893 = AVER_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #892 = AVER_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #891 = AVER_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #890 = AVER_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #889 = AVER_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #888 = AVER_S_B + { 3, &MipsDescs.OperandInfo[233] }, // Inst #887 = AUI_MMR6 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #886 = AUIPC_MMR6 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #885 = AUIPC + { 3, &MipsDescs.OperandInfo[233] }, // Inst #884 = AUI + { 3, &MipsDescs.OperandInfo[152] }, // Inst #883 = ASUB_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #882 = ASUB_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #881 = ASUB_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #880 = ASUB_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #879 = ASUB_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #878 = ASUB_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #877 = ASUB_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #876 = ASUB_S_B + { 4, &MipsDescs.OperandInfo[614] }, // Inst #875 = APPEND_MMR2 + { 4, &MipsDescs.OperandInfo[614] }, // Inst #874 = APPEND + { 3, &MipsDescs.OperandInfo[233] }, // Inst #873 = ANDi_MM + { 3, &MipsDescs.OperandInfo[224] }, // Inst #872 = ANDi64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #871 = ANDi + { 3, &MipsDescs.OperandInfo[578] }, // Inst #870 = AND_V + { 3, &MipsDescs.OperandInfo[596] }, // Inst #869 = AND_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #868 = AND_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #867 = AND_MM + { 3, &MipsDescs.OperandInfo[391] }, // Inst #866 = ANDI_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #865 = ANDI_MMR6 + { 3, &MipsDescs.OperandInfo[584] }, // Inst #864 = ANDI_B + { 3, &MipsDescs.OperandInfo[566] }, // Inst #863 = ANDI16_NM + { 3, &MipsDescs.OperandInfo[563] }, // Inst #862 = ANDI16_MMR6 + { 3, &MipsDescs.OperandInfo[563] }, // Inst #861 = ANDI16_MM + { 3, &MipsDescs.OperandInfo[227] }, // Inst #860 = AND64 + { 3, &MipsDescs.OperandInfo[599] }, // Inst #859 = AND16_NM + { 3, &MipsDescs.OperandInfo[611] }, // Inst #858 = AND16_MMR6 + { 3, &MipsDescs.OperandInfo[611] }, // Inst #857 = AND16_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #856 = AND + { 2, &MipsDescs.OperandInfo[609] }, // Inst #855 = ALUIPC_NM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #854 = ALUIPC_MMR6 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #853 = ALUIPC + { 4, &MipsDescs.OperandInfo[605] }, // Inst #852 = ALIGN_MMR6 + { 4, &MipsDescs.OperandInfo[605] }, // Inst #851 = ALIGN + { 3, &MipsDescs.OperandInfo[596] }, // Inst #850 = ADDu_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #849 = ADDu_MM + { 3, &MipsDescs.OperandInfo[602] }, // Inst #848 = ADDu4x4_NM + { 3, &MipsDescs.OperandInfo[599] }, // Inst #847 = ADDu16_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #846 = ADDu + { 3, &MipsDescs.OperandInfo[233] }, // Inst #845 = ADDiu_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #844 = ADDiu + { 3, &MipsDescs.OperandInfo[233] }, // Inst #843 = ADDi_MM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #842 = ADDi + { 3, &MipsDescs.OperandInfo[596] }, // Inst #841 = ADD_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #840 = ADD_MMR6 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #839 = ADD_MM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #838 = ADD_A_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #837 = ADD_A_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #836 = ADD_A_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #835 = ADD_A_B + { 3, &MipsDescs.OperandInfo[230] }, // Inst #834 = ADDWC_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #833 = ADDWC + { 3, &MipsDescs.OperandInfo[152] }, // Inst #832 = ADDV_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #831 = ADDV_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #830 = ADDV_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #829 = ADDV_B + { 3, &MipsDescs.OperandInfo[593] }, // Inst #828 = ADDVI_W + { 3, &MipsDescs.OperandInfo[590] }, // Inst #827 = ADDVI_H + { 3, &MipsDescs.OperandInfo[587] }, // Inst #826 = ADDVI_D + { 3, &MipsDescs.OperandInfo[584] }, // Inst #825 = ADDVI_B + { 3, &MipsDescs.OperandInfo[572] }, // Inst #824 = ADDU_S_QB_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #823 = ADDU_S_QB + { 3, &MipsDescs.OperandInfo[572] }, // Inst #822 = ADDU_S_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #821 = ADDU_S_PH + { 3, &MipsDescs.OperandInfo[572] }, // Inst #820 = ADDU_QB_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #819 = ADDU_QB + { 3, &MipsDescs.OperandInfo[572] }, // Inst #818 = ADDU_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #817 = ADDU_PH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #816 = ADDU_MMR6 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #815 = ADDUH_R_QB_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #814 = ADDUH_R_QB + { 3, &MipsDescs.OperandInfo[572] }, // Inst #813 = ADDUH_QB_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #812 = ADDUH_QB + { 3, &MipsDescs.OperandInfo[581] }, // Inst #811 = ADDU16_MMR6 + { 3, &MipsDescs.OperandInfo[581] }, // Inst #810 = ADDU16_MM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #809 = ADDS_U_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #808 = ADDS_U_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #807 = ADDS_U_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #806 = ADDS_U_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #805 = ADDS_S_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #804 = ADDS_S_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #803 = ADDS_S_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #802 = ADDS_S_B + { 3, &MipsDescs.OperandInfo[152] }, // Inst #801 = ADDS_A_W + { 3, &MipsDescs.OperandInfo[149] }, // Inst #800 = ADDS_A_H + { 3, &MipsDescs.OperandInfo[146] }, // Inst #799 = ADDS_A_D + { 3, &MipsDescs.OperandInfo[578] }, // Inst #798 = ADDS_A_B + { 3, &MipsDescs.OperandInfo[230] }, // Inst #797 = ADDSC_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #796 = ADDSC + { 3, &MipsDescs.OperandInfo[575] }, // Inst #795 = ADDR_PS64 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #794 = ADDQ_S_W_MM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #793 = ADDQ_S_W + { 3, &MipsDescs.OperandInfo[572] }, // Inst #792 = ADDQ_S_PH_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #791 = ADDQ_S_PH + { 3, &MipsDescs.OperandInfo[572] }, // Inst #790 = ADDQ_PH_MM + { 3, &MipsDescs.OperandInfo[572] }, // Inst #789 = ADDQ_PH + { 3, &MipsDescs.OperandInfo[230] }, // Inst #788 = ADDQH_W_MMR2 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #787 = ADDQH_W + { 3, &MipsDescs.OperandInfo[230] }, // Inst #786 = ADDQH_R_W_MMR2 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #785 = ADDQH_R_W + { 3, &MipsDescs.OperandInfo[572] }, // Inst #784 = ADDQH_R_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #783 = ADDQH_R_PH + { 3, &MipsDescs.OperandInfo[572] }, // Inst #782 = ADDQH_PH_MMR2 + { 3, &MipsDescs.OperandInfo[572] }, // Inst #781 = ADDQH_PH + { 3, &MipsDescs.OperandInfo[391] }, // Inst #780 = ADDIU_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #779 = ADDIU_MMR6 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #778 = ADDIUSP_MM + { 3, &MipsDescs.OperandInfo[569] }, // Inst #777 = ADDIUS5_MM + { 3, &MipsDescs.OperandInfo[552] }, // Inst #776 = ADDIURS5_NM + { 3, &MipsDescs.OperandInfo[566] }, // Inst #775 = ADDIUR2_NM + { 3, &MipsDescs.OperandInfo[563] }, // Inst #774 = ADDIUR2_MM + { 3, &MipsDescs.OperandInfo[560] }, // Inst #773 = ADDIUR1SP_NM + { 2, &MipsDescs.OperandInfo[558] }, // Inst #772 = ADDIUR1SP_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #771 = ADDIUPC_MMR6 + { 2, &MipsDescs.OperandInfo[558] }, // Inst #770 = ADDIUPC_MM + { 2, &MipsDescs.OperandInfo[364] }, // Inst #769 = ADDIUPC + { 3, &MipsDescs.OperandInfo[391] }, // Inst #768 = ADDIUNEG_NM + { 3, &MipsDescs.OperandInfo[555] }, // Inst #767 = ADDIUGPW_NM + { 3, &MipsDescs.OperandInfo[555] }, // Inst #766 = ADDIUGPB_NM + { 3, &MipsDescs.OperandInfo[391] }, // Inst #765 = ADDIUGP48_NM + { 3, &MipsDescs.OperandInfo[552] }, // Inst #764 = ADDIU48_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #763 = ADD + { 2, &MipsDescs.OperandInfo[140] }, // Inst #762 = ABSQ_S_W_MM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #761 = ABSQ_S_W + { 2, &MipsDescs.OperandInfo[550] }, // Inst #760 = ABSQ_S_QB_MMR2 + { 2, &MipsDescs.OperandInfo[550] }, // Inst #759 = ABSQ_S_QB + { 2, &MipsDescs.OperandInfo[550] }, // Inst #758 = ABSQ_S_PH_MM + { 2, &MipsDescs.OperandInfo[550] }, // Inst #757 = ABSQ_S_PH + { 3, &MipsDescs.OperandInfo[152] }, // Inst #756 = XOR_V_W_PSEUDO + { 3, &MipsDescs.OperandInfo[149] }, // Inst #755 = XOR_V_H_PSEUDO + { 3, &MipsDescs.OperandInfo[146] }, // Inst #754 = XOR_V_D_PSEUDO + { 3, &MipsDescs.OperandInfo[312] }, // Inst #753 = Usw + { 3, &MipsDescs.OperandInfo[312] }, // Inst #752 = Ush + { 3, &MipsDescs.OperandInfo[312] }, // Inst #751 = Ulw + { 3, &MipsDescs.OperandInfo[312] }, // Inst #750 = Ulhu + { 3, &MipsDescs.OperandInfo[312] }, // Inst #749 = Ulh + { 3, &MipsDescs.OperandInfo[230] }, // Inst #748 = URemMacro + { 3, &MipsDescs.OperandInfo[233] }, // Inst #747 = URemIMacro + { 3, &MipsDescs.OperandInfo[230] }, // Inst #746 = UDivMacro + { 3, &MipsDescs.OperandInfo[233] }, // Inst #745 = UDivIMacro + { 3, &MipsDescs.OperandInfo[460] }, // Inst #744 = UDIV_MM_Pseudo + { 0, &MipsDescs.OperandInfo[1] }, // Inst #743 = TRAP_MM + { 0, &MipsDescs.OperandInfo[1] }, // Inst #742 = TRAP + { 1, &MipsDescs.OperandInfo[182] }, // Inst #741 = TAILCALL_NM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #740 = TAILCALL_MMR6 + { 1, &MipsDescs.OperandInfo[0] }, // Inst #739 = TAILCALL_MM + { 1, &MipsDescs.OperandInfo[418] }, // Inst #738 = TAILCALLREG_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #737 = TAILCALLREG_MMR6 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #736 = TAILCALLREG_MM + { 1, &MipsDescs.OperandInfo[310] }, // Inst #735 = TAILCALLREGHB64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #734 = TAILCALLREGHB + { 1, &MipsDescs.OperandInfo[310] }, // Inst #733 = TAILCALLREG64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #732 = TAILCALLREG + { 1, &MipsDescs.OperandInfo[189] }, // Inst #731 = TAILCALLR6REG + { 1, &MipsDescs.OperandInfo[189] }, // Inst #730 = TAILCALLHBR6REG + { 1, &MipsDescs.OperandInfo[310] }, // Inst #729 = TAILCALLHB64R6REG + { 1, &MipsDescs.OperandInfo[310] }, // Inst #728 = TAILCALL64R6REG + { 1, &MipsDescs.OperandInfo[0] }, // Inst #727 = TAILCALL + { 3, &MipsDescs.OperandInfo[421] }, // Inst #726 = SltuRxRyRz16 + { 3, &MipsDescs.OperandInfo[421] }, // Inst #725 = SltuCCRxRy16 + { 3, &MipsDescs.OperandInfo[547] }, // Inst #724 = SltiuCCRxImmX16 + { 3, &MipsDescs.OperandInfo[547] }, // Inst #723 = SltiCCRxImmX16 + { 3, &MipsDescs.OperandInfo[421] }, // Inst #722 = SltCCRxRy16 + { 5, &MipsDescs.OperandInfo[537] }, // Inst #721 = SelTBtneZSltu + { 5, &MipsDescs.OperandInfo[542] }, // Inst #720 = SelTBtneZSltiu + { 5, &MipsDescs.OperandInfo[542] }, // Inst #719 = SelTBtneZSlti + { 5, &MipsDescs.OperandInfo[537] }, // Inst #718 = SelTBtneZSlt + { 5, &MipsDescs.OperandInfo[542] }, // Inst #717 = SelTBtneZCmpi + { 5, &MipsDescs.OperandInfo[537] }, // Inst #716 = SelTBtneZCmp + { 5, &MipsDescs.OperandInfo[537] }, // Inst #715 = SelTBteqZSltu + { 5, &MipsDescs.OperandInfo[542] }, // Inst #714 = SelTBteqZSltiu + { 5, &MipsDescs.OperandInfo[542] }, // Inst #713 = SelTBteqZSlti + { 5, &MipsDescs.OperandInfo[537] }, // Inst #712 = SelTBteqZSlt + { 5, &MipsDescs.OperandInfo[542] }, // Inst #711 = SelTBteqZCmpi + { 5, &MipsDescs.OperandInfo[537] }, // Inst #710 = SelTBteqZCmp + { 4, &MipsDescs.OperandInfo[533] }, // Inst #709 = SelBneZ + { 4, &MipsDescs.OperandInfo[533] }, // Inst #708 = SelBeqZ + { 3, &MipsDescs.OperandInfo[361] }, // Inst #707 = SaadAddr + { 3, &MipsDescs.OperandInfo[361] }, // Inst #706 = SaaAddr + { 2, &MipsDescs.OperandInfo[531] }, // Inst #705 = SZ_W_PSEUDO + { 2, &MipsDescs.OperandInfo[525] }, // Inst #704 = SZ_V_PSEUDO + { 2, &MipsDescs.OperandInfo[529] }, // Inst #703 = SZ_H_PSEUDO + { 2, &MipsDescs.OperandInfo[527] }, // Inst #702 = SZ_D_PSEUDO + { 2, &MipsDescs.OperandInfo[525] }, // Inst #701 = SZ_B_PSEUDO + { 3, &MipsDescs.OperandInfo[354] }, // Inst #700 = SWM_MM + { 3, &MipsDescs.OperandInfo[321] }, // Inst #699 = ST_F16 + { 3, &MipsDescs.OperandInfo[318] }, // Inst #698 = STR_W + { 3, &MipsDescs.OperandInfo[315] }, // Inst #697 = STR_D + { 3, &MipsDescs.OperandInfo[333] }, // Inst #696 = STORE_CCOND_DSP + { 3, &MipsDescs.OperandInfo[330] }, // Inst #695 = STORE_ACC64DSP + { 3, &MipsDescs.OperandInfo[327] }, // Inst #694 = STORE_ACC64 + { 3, &MipsDescs.OperandInfo[324] }, // Inst #693 = STORE_ACC128 + { 3, &MipsDescs.OperandInfo[230] }, // Inst #692 = SRemMacro + { 3, &MipsDescs.OperandInfo[233] }, // Inst #691 = SRemIMacro + { 2, &MipsDescs.OperandInfo[531] }, // Inst #690 = SNZ_W_PSEUDO + { 2, &MipsDescs.OperandInfo[525] }, // Inst #689 = SNZ_V_PSEUDO + { 2, &MipsDescs.OperandInfo[529] }, // Inst #688 = SNZ_H_PSEUDO + { 2, &MipsDescs.OperandInfo[527] }, // Inst #687 = SNZ_D_PSEUDO + { 2, &MipsDescs.OperandInfo[525] }, // Inst #686 = SNZ_B_PSEUDO + { 3, &MipsDescs.OperandInfo[230] }, // Inst #685 = SNEMacro + { 3, &MipsDescs.OperandInfo[233] }, // Inst #684 = SNEIMacro + { 3, &MipsDescs.OperandInfo[224] }, // Inst #683 = SLTUImm64 + { 3, &MipsDescs.OperandInfo[224] }, // Inst #682 = SLTImm64 + { 3, &MipsDescs.OperandInfo[224] }, // Inst #681 = SLEUImm64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #680 = SLEUImm + { 3, &MipsDescs.OperandInfo[230] }, // Inst #679 = SLEU + { 3, &MipsDescs.OperandInfo[224] }, // Inst #678 = SLEImm64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #677 = SLEImm + { 3, &MipsDescs.OperandInfo[230] }, // Inst #676 = SLE + { 3, &MipsDescs.OperandInfo[224] }, // Inst #675 = SGTUImm64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #674 = SGTUImm + { 3, &MipsDescs.OperandInfo[224] }, // Inst #673 = SGTImm64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #672 = SGTImm + { 3, &MipsDescs.OperandInfo[224] }, // Inst #671 = SGEUImm64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #670 = SGEUImm + { 3, &MipsDescs.OperandInfo[230] }, // Inst #669 = SGEU + { 3, &MipsDescs.OperandInfo[224] }, // Inst #668 = SGEImm64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #667 = SGEImm + { 3, &MipsDescs.OperandInfo[230] }, // Inst #666 = SGE + { 3, &MipsDescs.OperandInfo[230] }, // Inst #665 = SEQMacro + { 3, &MipsDescs.OperandInfo[233] }, // Inst #664 = SEQIMacro + { 3, &MipsDescs.OperandInfo[522] }, // Inst #663 = SDivMacro + { 3, &MipsDescs.OperandInfo[233] }, // Inst #662 = SDivIMacro + { 3, &MipsDescs.OperandInfo[312] }, // Inst #661 = SDMacro + { 3, &MipsDescs.OperandInfo[460] }, // Inst #660 = SDIV_MM_Pseudo + { 3, &MipsDescs.OperandInfo[519] }, // Inst #659 = SDC1_M1 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #658 = RetRA16 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #657 = RetRA + { 3, &MipsDescs.OperandInfo[233] }, // Inst #656 = RORImm + { 3, &MipsDescs.OperandInfo[230] }, // Inst #655 = ROR + { 3, &MipsDescs.OperandInfo[233] }, // Inst #654 = ROLImm + { 3, &MipsDescs.OperandInfo[230] }, // Inst #653 = ROL + { 3, &MipsDescs.OperandInfo[460] }, // Inst #652 = PseudoUDIV + { 3, &MipsDescs.OperandInfo[516] }, // Inst #651 = PseudoTRUNC_W_S + { 3, &MipsDescs.OperandInfo[513] }, // Inst #650 = PseudoTRUNC_W_D32 + { 3, &MipsDescs.OperandInfo[510] }, // Inst #649 = PseudoTRUNC_W_D + { 3, &MipsDescs.OperandInfo[391] }, // Inst #648 = PseudoSUBU_NM + { 4, &MipsDescs.OperandInfo[506] }, // Inst #647 = PseudoSELECT_S + { 4, &MipsDescs.OperandInfo[502] }, // Inst #646 = PseudoSELECT_I64 + { 4, &MipsDescs.OperandInfo[498] }, // Inst #645 = PseudoSELECT_I + { 4, &MipsDescs.OperandInfo[494] }, // Inst #644 = PseudoSELECT_D64 + { 4, &MipsDescs.OperandInfo[490] }, // Inst #643 = PseudoSELECT_D32 + { 4, &MipsDescs.OperandInfo[486] }, // Inst #642 = PseudoSELECTFP_T_S + { 4, &MipsDescs.OperandInfo[482] }, // Inst #641 = PseudoSELECTFP_T_I64 + { 4, &MipsDescs.OperandInfo[478] }, // Inst #640 = PseudoSELECTFP_T_I + { 4, &MipsDescs.OperandInfo[474] }, // Inst #639 = PseudoSELECTFP_T_D64 + { 4, &MipsDescs.OperandInfo[470] }, // Inst #638 = PseudoSELECTFP_T_D32 + { 4, &MipsDescs.OperandInfo[486] }, // Inst #637 = PseudoSELECTFP_F_S + { 4, &MipsDescs.OperandInfo[482] }, // Inst #636 = PseudoSELECTFP_F_I64 + { 4, &MipsDescs.OperandInfo[478] }, // Inst #635 = PseudoSELECTFP_F_I + { 4, &MipsDescs.OperandInfo[474] }, // Inst #634 = PseudoSELECTFP_F_D64 + { 4, &MipsDescs.OperandInfo[470] }, // Inst #633 = PseudoSELECTFP_F_D32 + { 3, &MipsDescs.OperandInfo[460] }, // Inst #632 = PseudoSDIV + { 1, &MipsDescs.OperandInfo[311] }, // Inst #631 = PseudoReturnNM + { 1, &MipsDescs.OperandInfo[310] }, // Inst #630 = PseudoReturn64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #629 = PseudoReturn + { 4, &MipsDescs.OperandInfo[466] }, // Inst #628 = PseudoPICK_QB + { 4, &MipsDescs.OperandInfo[466] }, // Inst #627 = PseudoPICK_PH + { 3, &MipsDescs.OperandInfo[460] }, // Inst #626 = PseudoMULTu_MM + { 3, &MipsDescs.OperandInfo[460] }, // Inst #625 = PseudoMULTu + { 3, &MipsDescs.OperandInfo[460] }, // Inst #624 = PseudoMULT_MM + { 3, &MipsDescs.OperandInfo[460] }, // Inst #623 = PseudoMULT + { 3, &MipsDescs.OperandInfo[460] }, // Inst #622 = PseudoMTLOHI_MM + { 3, &MipsDescs.OperandInfo[463] }, // Inst #621 = PseudoMTLOHI_DSP + { 3, &MipsDescs.OperandInfo[433] }, // Inst #620 = PseudoMTLOHI64 + { 3, &MipsDescs.OperandInfo[460] }, // Inst #619 = PseudoMTLOHI + { 4, &MipsDescs.OperandInfo[452] }, // Inst #618 = PseudoMSUB_MM + { 4, &MipsDescs.OperandInfo[452] }, // Inst #617 = PseudoMSUBU_MM + { 4, &MipsDescs.OperandInfo[452] }, // Inst #616 = PseudoMSUBU + { 4, &MipsDescs.OperandInfo[452] }, // Inst #615 = PseudoMSUB + { 2, &MipsDescs.OperandInfo[456] }, // Inst #614 = PseudoMFLO_MM + { 2, &MipsDescs.OperandInfo[458] }, // Inst #613 = PseudoMFLO64 + { 2, &MipsDescs.OperandInfo[456] }, // Inst #612 = PseudoMFLO + { 2, &MipsDescs.OperandInfo[456] }, // Inst #611 = PseudoMFHI_MM + { 2, &MipsDescs.OperandInfo[458] }, // Inst #610 = PseudoMFHI64 + { 2, &MipsDescs.OperandInfo[456] }, // Inst #609 = PseudoMFHI + { 4, &MipsDescs.OperandInfo[452] }, // Inst #608 = PseudoMADD_MM + { 4, &MipsDescs.OperandInfo[452] }, // Inst #607 = PseudoMADDU_MM + { 4, &MipsDescs.OperandInfo[452] }, // Inst #606 = PseudoMADDU + { 4, &MipsDescs.OperandInfo[452] }, // Inst #605 = PseudoMADD + { 2, &MipsDescs.OperandInfo[450] }, // Inst #604 = PseudoLI_NM + { 2, &MipsDescs.OperandInfo[450] }, // Inst #603 = PseudoLA_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #602 = PseudoIndrectHazardBranchR6 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #601 = PseudoIndrectHazardBranch64R6 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #600 = PseudoIndirectHazardBranch64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #599 = PseudoIndirectHazardBranch + { 1, &MipsDescs.OperandInfo[189] }, // Inst #598 = PseudoIndirectBranch_MMR6 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #597 = PseudoIndirectBranch_MM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #596 = PseudoIndirectBranchR6 + { 1, &MipsDescs.OperandInfo[311] }, // Inst #595 = PseudoIndirectBranchNM + { 1, &MipsDescs.OperandInfo[310] }, // Inst #594 = PseudoIndirectBranch64R6 + { 1, &MipsDescs.OperandInfo[310] }, // Inst #593 = PseudoIndirectBranch64 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #592 = PseudoIndirectBranch + { 7, &MipsDescs.OperandInfo[443] }, // Inst #591 = PseudoD_SELECT_I64 + { 7, &MipsDescs.OperandInfo[436] }, // Inst #590 = PseudoD_SELECT_I + { 3, &MipsDescs.OperandInfo[433] }, // Inst #589 = PseudoDUDIV + { 3, &MipsDescs.OperandInfo[433] }, // Inst #588 = PseudoDSDIV + { 3, &MipsDescs.OperandInfo[433] }, // Inst #587 = PseudoDMULTu + { 3, &MipsDescs.OperandInfo[433] }, // Inst #586 = PseudoDMULT + { 2, &MipsDescs.OperandInfo[414] }, // Inst #585 = PseudoCVT_S_W + { 2, &MipsDescs.OperandInfo[429] }, // Inst #584 = PseudoCVT_S_L + { 2, &MipsDescs.OperandInfo[431] }, // Inst #583 = PseudoCVT_D64_W + { 2, &MipsDescs.OperandInfo[429] }, // Inst #582 = PseudoCVT_D64_L + { 2, &MipsDescs.OperandInfo[427] }, // Inst #581 = PseudoCVT_D32_W + { 3, &MipsDescs.OperandInfo[424] }, // Inst #580 = PseudoCMP_LT_PH + { 3, &MipsDescs.OperandInfo[424] }, // Inst #579 = PseudoCMP_LE_PH + { 3, &MipsDescs.OperandInfo[424] }, // Inst #578 = PseudoCMP_EQ_PH + { 3, &MipsDescs.OperandInfo[424] }, // Inst #577 = PseudoCMPU_LT_QB + { 3, &MipsDescs.OperandInfo[424] }, // Inst #576 = PseudoCMPU_LE_QB + { 3, &MipsDescs.OperandInfo[424] }, // Inst #575 = PseudoCMPU_EQ_QB + { 3, &MipsDescs.OperandInfo[391] }, // Inst #574 = PseudoANDI_NM + { 3, &MipsDescs.OperandInfo[391] }, // Inst #573 = PseudoADDIU_NM + { 3, &MipsDescs.OperandInfo[152] }, // Inst #572 = OR_V_W_PSEUDO + { 3, &MipsDescs.OperandInfo[149] }, // Inst #571 = OR_V_H_PSEUDO + { 3, &MipsDescs.OperandInfo[146] }, // Inst #570 = OR_V_D_PSEUDO + { 3, &MipsDescs.OperandInfo[152] }, // Inst #569 = NOR_V_W_PSEUDO + { 3, &MipsDescs.OperandInfo[149] }, // Inst #568 = NOR_V_H_PSEUDO + { 3, &MipsDescs.OperandInfo[146] }, // Inst #567 = NOR_V_D_PSEUDO + { 3, &MipsDescs.OperandInfo[224] }, // Inst #566 = NORImm64 + { 3, &MipsDescs.OperandInfo[233] }, // Inst #565 = NORImm + { 0, &MipsDescs.OperandInfo[1] }, // Inst #564 = NOP + { 3, &MipsDescs.OperandInfo[421] }, // Inst #563 = MultuRxRyRz16 + { 2, &MipsDescs.OperandInfo[419] }, // Inst #562 = MultuRxRy16 + { 3, &MipsDescs.OperandInfo[421] }, // Inst #561 = MultRxRyRz16 + { 2, &MipsDescs.OperandInfo[419] }, // Inst #560 = MultRxRy16 + { 1, &MipsDescs.OperandInfo[182] }, // Inst #559 = MUSTTAILCALL_NM + { 1, &MipsDescs.OperandInfo[418] }, // Inst #558 = MUSTTAILCALLREG_NM + { 3, &MipsDescs.OperandInfo[230] }, // Inst #557 = MULOUMacro + { 3, &MipsDescs.OperandInfo[230] }, // Inst #556 = MULOMacro + { 3, &MipsDescs.OperandInfo[233] }, // Inst #555 = MULImmMacro + { 2, &MipsDescs.OperandInfo[406] }, // Inst #554 = MTTLO_NM + { 2, &MipsDescs.OperandInfo[404] }, // Inst #553 = MTTLO + { 2, &MipsDescs.OperandInfo[406] }, // Inst #552 = MTTHI_NM + { 2, &MipsDescs.OperandInfo[404] }, // Inst #551 = MTTHI + { 2, &MipsDescs.OperandInfo[414] }, // Inst #550 = MTTHC1 + { 2, &MipsDescs.OperandInfo[416] }, // Inst #549 = MTTGPR_NM + { 2, &MipsDescs.OperandInfo[140] }, // Inst #548 = MTTGPR + { 1, &MipsDescs.OperandInfo[311] }, // Inst #547 = MTTDSP_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #546 = MTTDSP + { 2, &MipsDescs.OperandInfo[414] }, // Inst #545 = MTTC1 + { 3, &MipsDescs.OperandInfo[411] }, // Inst #544 = MTTC0_NM + { 3, &MipsDescs.OperandInfo[408] }, // Inst #543 = MTTC0 + { 2, &MipsDescs.OperandInfo[406] }, // Inst #542 = MTTACX_NM + { 2, &MipsDescs.OperandInfo[404] }, // Inst #541 = MTTACX + { 2, &MipsDescs.OperandInfo[402] }, // Inst #540 = MSA_FP_ROUND_W_PSEUDO + { 2, &MipsDescs.OperandInfo[400] }, // Inst #539 = MSA_FP_ROUND_D_PSEUDO + { 2, &MipsDescs.OperandInfo[398] }, // Inst #538 = MSA_FP_EXTEND_W_PSEUDO + { 2, &MipsDescs.OperandInfo[396] }, // Inst #537 = MSA_FP_EXTEND_D_PSEUDO + { 2, &MipsDescs.OperandInfo[394] }, // Inst #536 = MIPSeh_return64 + { 2, &MipsDescs.OperandInfo[140] }, // Inst #535 = MIPSeh_return32 + { 2, &MipsDescs.OperandInfo[381] }, // Inst #534 = MFTLO_NM + { 2, &MipsDescs.OperandInfo[379] }, // Inst #533 = MFTLO + { 2, &MipsDescs.OperandInfo[381] }, // Inst #532 = MFTHI_NM + { 2, &MipsDescs.OperandInfo[379] }, // Inst #531 = MFTHI + { 2, &MipsDescs.OperandInfo[389] }, // Inst #530 = MFTHC1 + { 3, &MipsDescs.OperandInfo[391] }, // Inst #529 = MFTGPR_NM + { 3, &MipsDescs.OperandInfo[233] }, // Inst #528 = MFTGPR + { 1, &MipsDescs.OperandInfo[311] }, // Inst #527 = MFTDSP_NM + { 1, &MipsDescs.OperandInfo[189] }, // Inst #526 = MFTDSP + { 2, &MipsDescs.OperandInfo[389] }, // Inst #525 = MFTC1 + { 3, &MipsDescs.OperandInfo[386] }, // Inst #524 = MFTC0_NM + { 3, &MipsDescs.OperandInfo[383] }, // Inst #523 = MFTC0 + { 2, &MipsDescs.OperandInfo[381] }, // Inst #522 = MFTACX_NM + { 2, &MipsDescs.OperandInfo[379] }, // Inst #521 = MFTACX + { 3, &MipsDescs.OperandInfo[376] }, // Inst #520 = LwConstant32 + { 4, &MipsDescs.OperandInfo[372] }, // Inst #519 = LoadJumpTableOffset + { 2, &MipsDescs.OperandInfo[364] }, // Inst #518 = LoadImmSingleGPR + { 2, &MipsDescs.OperandInfo[370] }, // Inst #517 = LoadImmSingleFGR + { 2, &MipsDescs.OperandInfo[364] }, // Inst #516 = LoadImmDoubleGPR + { 2, &MipsDescs.OperandInfo[368] }, // Inst #515 = LoadImmDoubleFGR_32 + { 2, &MipsDescs.OperandInfo[366] }, // Inst #514 = LoadImmDoubleFGR + { 2, &MipsDescs.OperandInfo[359] }, // Inst #513 = LoadImm64 + { 2, &MipsDescs.OperandInfo[364] }, // Inst #512 = LoadImm32 + { 3, &MipsDescs.OperandInfo[361] }, // Inst #511 = LoadAddrReg64 + { 3, &MipsDescs.OperandInfo[312] }, // Inst #510 = LoadAddrReg32 + { 2, &MipsDescs.OperandInfo[359] }, // Inst #509 = LoadAddrImm64 + { 2, &MipsDescs.OperandInfo[357] }, // Inst #508 = LoadAddrImm32 + { 3, &MipsDescs.OperandInfo[354] }, // Inst #507 = LWM_MM + { 2, &MipsDescs.OperandInfo[352] }, // Inst #506 = LONG_BRANCH_LUi2Op_64 + { 2, &MipsDescs.OperandInfo[350] }, // Inst #505 = LONG_BRANCH_LUi2Op + { 3, &MipsDescs.OperandInfo[347] }, // Inst #504 = LONG_BRANCH_LUi + { 3, &MipsDescs.OperandInfo[344] }, // Inst #503 = LONG_BRANCH_DADDiu2Op + { 4, &MipsDescs.OperandInfo[340] }, // Inst #502 = LONG_BRANCH_DADDiu + { 3, &MipsDescs.OperandInfo[186] }, // Inst #501 = LONG_BRANCH_ADDiu2Op + { 4, &MipsDescs.OperandInfo[336] }, // Inst #500 = LONG_BRANCH_ADDiu + { 3, &MipsDescs.OperandInfo[333] }, // Inst #499 = LOAD_CCOND_DSP + { 3, &MipsDescs.OperandInfo[330] }, // Inst #498 = LOAD_ACC64DSP + { 3, &MipsDescs.OperandInfo[327] }, // Inst #497 = LOAD_ACC64 + { 3, &MipsDescs.OperandInfo[324] }, // Inst #496 = LOAD_ACC128 + { 3, &MipsDescs.OperandInfo[321] }, // Inst #495 = LD_F16 + { 3, &MipsDescs.OperandInfo[318] }, // Inst #494 = LDR_W + { 3, &MipsDescs.OperandInfo[315] }, // Inst #493 = LDR_D + { 3, &MipsDescs.OperandInfo[312] }, // Inst #492 = LDMacro + { 2, &MipsDescs.OperandInfo[140] }, // Inst #491 = JalTwoReg + { 1, &MipsDescs.OperandInfo[189] }, // Inst #490 = JalOneReg + { 1, &MipsDescs.OperandInfo[0] }, // Inst #489 = JAL_MMR6 + { 1, &MipsDescs.OperandInfo[189] }, // Inst #488 = JALRPseudo + { 1, &MipsDescs.OperandInfo[189] }, // Inst #487 = JALRHBPseudo + { 1, &MipsDescs.OperandInfo[310] }, // Inst #486 = JALRHB64Pseudo + { 1, &MipsDescs.OperandInfo[311] }, // Inst #485 = JALRCPseudo + { 1, &MipsDescs.OperandInfo[310] }, // Inst #484 = JALR64Pseudo + { 4, &MipsDescs.OperandInfo[306] }, // Inst #483 = INSERT_W_VIDX_PSEUDO + { 4, &MipsDescs.OperandInfo[302] }, // Inst #482 = INSERT_W_VIDX64_PSEUDO + { 4, &MipsDescs.OperandInfo[298] }, // Inst #481 = INSERT_H_VIDX_PSEUDO + { 4, &MipsDescs.OperandInfo[294] }, // Inst #480 = INSERT_H_VIDX64_PSEUDO + { 4, &MipsDescs.OperandInfo[290] }, // Inst #479 = INSERT_FW_VIDX_PSEUDO + { 4, &MipsDescs.OperandInfo[286] }, // Inst #478 = INSERT_FW_VIDX64_PSEUDO + { 4, &MipsDescs.OperandInfo[282] }, // Inst #477 = INSERT_FW_PSEUDO + { 4, &MipsDescs.OperandInfo[278] }, // Inst #476 = INSERT_FD_VIDX_PSEUDO + { 4, &MipsDescs.OperandInfo[274] }, // Inst #475 = INSERT_FD_VIDX64_PSEUDO + { 4, &MipsDescs.OperandInfo[270] }, // Inst #474 = INSERT_FD_PSEUDO + { 4, &MipsDescs.OperandInfo[266] }, // Inst #473 = INSERT_D_VIDX_PSEUDO + { 4, &MipsDescs.OperandInfo[262] }, // Inst #472 = INSERT_D_VIDX64_PSEUDO + { 4, &MipsDescs.OperandInfo[258] }, // Inst #471 = INSERT_B_VIDX_PSEUDO + { 4, &MipsDescs.OperandInfo[254] }, // Inst #470 = INSERT_B_VIDX64_PSEUDO + { 4, &MipsDescs.OperandInfo[250] }, // Inst #469 = GotPrologue16 + { 2, &MipsDescs.OperandInfo[248] }, // Inst #468 = FILL_FW_PSEUDO + { 2, &MipsDescs.OperandInfo[246] }, // Inst #467 = FILL_FD_PSEUDO + { 2, &MipsDescs.OperandInfo[244] }, // Inst #466 = FEXP2_W_1_PSEUDO + { 2, &MipsDescs.OperandInfo[242] }, // Inst #465 = FEXP2_D_1_PSEUDO + { 2, &MipsDescs.OperandInfo[244] }, // Inst #464 = FABS_W + { 2, &MipsDescs.OperandInfo[242] }, // Inst #463 = FABS_D + { 3, &MipsDescs.OperandInfo[239] }, // Inst #462 = ExtractElementF64_64 + { 3, &MipsDescs.OperandInfo[236] }, // Inst #461 = ExtractElementF64 + { 0, &MipsDescs.OperandInfo[1] }, // Inst #460 = ERet + { 3, &MipsDescs.OperandInfo[227] }, // Inst #459 = DURemMacro + { 3, &MipsDescs.OperandInfo[224] }, // Inst #458 = DURemIMacro + { 3, &MipsDescs.OperandInfo[227] }, // Inst #457 = DUDivMacro + { 3, &MipsDescs.OperandInfo[224] }, // Inst #456 = DUDivIMacro + { 3, &MipsDescs.OperandInfo[227] }, // Inst #455 = DSRemMacro + { 3, &MipsDescs.OperandInfo[224] }, // Inst #454 = DSRemIMacro + { 3, &MipsDescs.OperandInfo[227] }, // Inst #453 = DSDivMacro + { 3, &MipsDescs.OperandInfo[224] }, // Inst #452 = DSDivIMacro + { 3, &MipsDescs.OperandInfo[233] }, // Inst #451 = DRORImm + { 3, &MipsDescs.OperandInfo[230] }, // Inst #450 = DROR + { 3, &MipsDescs.OperandInfo[233] }, // Inst #449 = DROLImm + { 3, &MipsDescs.OperandInfo[230] }, // Inst #448 = DROL + { 3, &MipsDescs.OperandInfo[227] }, // Inst #447 = DMULOUMacro + { 3, &MipsDescs.OperandInfo[227] }, // Inst #446 = DMULOMacro + { 3, &MipsDescs.OperandInfo[227] }, // Inst #445 = DMULMacro + { 3, &MipsDescs.OperandInfo[224] }, // Inst #444 = DMULImmMacro + { 1, &MipsDescs.OperandInfo[0] }, // Inst #443 = Constant32 + { 2, &MipsDescs.OperandInfo[222] }, // Inst #442 = CTTC1 + { 3, &MipsDescs.OperandInfo[219] }, // Inst #441 = COPY_FW_PSEUDO + { 3, &MipsDescs.OperandInfo[216] }, // Inst #440 = COPY_FD_PSEUDO + { 3, &MipsDescs.OperandInfo[2] }, // Inst #439 = CONSTPOOL_ENTRY + { 2, &MipsDescs.OperandInfo[214] }, // Inst #438 = CFTC1 + { 3, &MipsDescs.OperandInfo[211] }, // Inst #437 = BuildPairF64_64 + { 3, &MipsDescs.OperandInfo[208] }, // Inst #436 = BuildPairF64 + { 3, &MipsDescs.OperandInfo[202] }, // Inst #435 = BtnezT8SltuX16 + { 3, &MipsDescs.OperandInfo[205] }, // Inst #434 = BtnezT8SltiuX16 + { 3, &MipsDescs.OperandInfo[205] }, // Inst #433 = BtnezT8SltiX16 + { 3, &MipsDescs.OperandInfo[202] }, // Inst #432 = BtnezT8SltX16 + { 3, &MipsDescs.OperandInfo[205] }, // Inst #431 = BtnezT8CmpiX16 + { 3, &MipsDescs.OperandInfo[202] }, // Inst #430 = BtnezT8CmpX16 + { 3, &MipsDescs.OperandInfo[202] }, // Inst #429 = BteqzT8SltuX16 + { 3, &MipsDescs.OperandInfo[205] }, // Inst #428 = BteqzT8SltiuX16 + { 3, &MipsDescs.OperandInfo[205] }, // Inst #427 = BteqzT8SltiX16 + { 3, &MipsDescs.OperandInfo[202] }, // Inst #426 = BteqzT8SltX16 + { 3, &MipsDescs.OperandInfo[205] }, // Inst #425 = BteqzT8CmpiX16 + { 3, &MipsDescs.OperandInfo[202] }, // Inst #424 = BteqzT8CmpX16 + { 3, &MipsDescs.OperandInfo[183] }, // Inst #423 = BneImm + { 3, &MipsDescs.OperandInfo[183] }, // Inst #422 = BeqImm + { 1, &MipsDescs.OperandInfo[182] }, // Inst #421 = B_MM_Pseudo + { 1, &MipsDescs.OperandInfo[182] }, // Inst #420 = B_MMR6_Pseudo + { 1, &MipsDescs.OperandInfo[182] }, // Inst #419 = B_MM + { 4, &MipsDescs.OperandInfo[194] }, // Inst #418 = BSEL_W_PSEUDO + { 4, &MipsDescs.OperandInfo[198] }, // Inst #417 = BSEL_H_PSEUDO + { 4, &MipsDescs.OperandInfo[194] }, // Inst #416 = BSEL_FW_PSEUDO + { 4, &MipsDescs.OperandInfo[190] }, // Inst #415 = BSEL_FD_PSEUDO + { 4, &MipsDescs.OperandInfo[190] }, // Inst #414 = BSEL_D_PSEUDO + { 1, &MipsDescs.OperandInfo[189] }, // Inst #413 = BPOSGE32_PSEUDO + { 3, &MipsDescs.OperandInfo[183] }, // Inst #412 = BNELImmMacro + { 3, &MipsDescs.OperandInfo[183] }, // Inst #411 = BLTULImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #410 = BLTUL + { 3, &MipsDescs.OperandInfo[183] }, // Inst #409 = BLTUImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #408 = BLTU + { 3, &MipsDescs.OperandInfo[183] }, // Inst #407 = BLTLImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #406 = BLTL + { 3, &MipsDescs.OperandInfo[183] }, // Inst #405 = BLTImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #404 = BLT + { 3, &MipsDescs.OperandInfo[183] }, // Inst #403 = BLEULImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #402 = BLEUL + { 3, &MipsDescs.OperandInfo[183] }, // Inst #401 = BLEUImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #400 = BLEU + { 3, &MipsDescs.OperandInfo[183] }, // Inst #399 = BLELImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #398 = BLEL + { 3, &MipsDescs.OperandInfo[183] }, // Inst #397 = BLEImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #396 = BLE + { 3, &MipsDescs.OperandInfo[183] }, // Inst #395 = BGTULImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #394 = BGTUL + { 3, &MipsDescs.OperandInfo[183] }, // Inst #393 = BGTUImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #392 = BGTU + { 3, &MipsDescs.OperandInfo[183] }, // Inst #391 = BGTLImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #390 = BGTL + { 3, &MipsDescs.OperandInfo[183] }, // Inst #389 = BGTImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #388 = BGT + { 3, &MipsDescs.OperandInfo[183] }, // Inst #387 = BGEULImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #386 = BGEUL + { 3, &MipsDescs.OperandInfo[183] }, // Inst #385 = BGEUImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #384 = BGEU + { 3, &MipsDescs.OperandInfo[183] }, // Inst #383 = BGELImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #382 = BGEL + { 3, &MipsDescs.OperandInfo[183] }, // Inst #381 = BGEImmMacro + { 3, &MipsDescs.OperandInfo[186] }, // Inst #380 = BGE + { 3, &MipsDescs.OperandInfo[183] }, // Inst #379 = BEQLImmMacro + { 1, &MipsDescs.OperandInfo[182] }, // Inst #378 = BAL_BR_MM + { 1, &MipsDescs.OperandInfo[182] }, // Inst #377 = BAL_BR + { 1, &MipsDescs.OperandInfo[182] }, // Inst #376 = B + { 6, &MipsDescs.OperandInfo[173] }, // Inst #375 = ATOMIC_SWAP_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #374 = ATOMIC_SWAP_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #373 = ATOMIC_SWAP_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #372 = ATOMIC_SWAP_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #371 = ATOMIC_SWAP_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #370 = ATOMIC_SWAP_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #369 = ATOMIC_SWAP_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #368 = ATOMIC_SWAP_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #367 = ATOMIC_LOAD_XOR_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #366 = ATOMIC_LOAD_XOR_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #365 = ATOMIC_LOAD_XOR_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #364 = ATOMIC_LOAD_XOR_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #363 = ATOMIC_LOAD_XOR_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #362 = ATOMIC_LOAD_XOR_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #361 = ATOMIC_LOAD_XOR_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #360 = ATOMIC_LOAD_XOR_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #359 = ATOMIC_LOAD_UMIN_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #358 = ATOMIC_LOAD_UMIN_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #357 = ATOMIC_LOAD_UMIN_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #356 = ATOMIC_LOAD_UMIN_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #355 = ATOMIC_LOAD_UMIN_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #354 = ATOMIC_LOAD_UMIN_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #353 = ATOMIC_LOAD_UMIN_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #352 = ATOMIC_LOAD_UMIN_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #351 = ATOMIC_LOAD_UMAX_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #350 = ATOMIC_LOAD_UMAX_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #349 = ATOMIC_LOAD_UMAX_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #348 = ATOMIC_LOAD_UMAX_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #347 = ATOMIC_LOAD_UMAX_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #346 = ATOMIC_LOAD_UMAX_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #345 = ATOMIC_LOAD_UMAX_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #344 = ATOMIC_LOAD_UMAX_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #343 = ATOMIC_LOAD_SUB_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #342 = ATOMIC_LOAD_SUB_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #341 = ATOMIC_LOAD_SUB_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #340 = ATOMIC_LOAD_SUB_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #339 = ATOMIC_LOAD_SUB_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #338 = ATOMIC_LOAD_SUB_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #337 = ATOMIC_LOAD_SUB_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #336 = ATOMIC_LOAD_SUB_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #335 = ATOMIC_LOAD_OR_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #334 = ATOMIC_LOAD_OR_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #333 = ATOMIC_LOAD_OR_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #332 = ATOMIC_LOAD_OR_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #331 = ATOMIC_LOAD_OR_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #330 = ATOMIC_LOAD_OR_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #329 = ATOMIC_LOAD_OR_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #328 = ATOMIC_LOAD_OR_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #327 = ATOMIC_LOAD_NAND_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #326 = ATOMIC_LOAD_NAND_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #325 = ATOMIC_LOAD_NAND_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #324 = ATOMIC_LOAD_NAND_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #323 = ATOMIC_LOAD_NAND_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #322 = ATOMIC_LOAD_NAND_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #321 = ATOMIC_LOAD_NAND_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #320 = ATOMIC_LOAD_NAND_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #319 = ATOMIC_LOAD_MIN_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #318 = ATOMIC_LOAD_MIN_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #317 = ATOMIC_LOAD_MIN_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #316 = ATOMIC_LOAD_MIN_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #315 = ATOMIC_LOAD_MIN_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #314 = ATOMIC_LOAD_MIN_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #313 = ATOMIC_LOAD_MIN_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #312 = ATOMIC_LOAD_MIN_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #311 = ATOMIC_LOAD_MAX_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #310 = ATOMIC_LOAD_MAX_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #309 = ATOMIC_LOAD_MAX_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #308 = ATOMIC_LOAD_MAX_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #307 = ATOMIC_LOAD_MAX_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #306 = ATOMIC_LOAD_MAX_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #305 = ATOMIC_LOAD_MAX_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #304 = ATOMIC_LOAD_MAX_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #303 = ATOMIC_LOAD_AND_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #302 = ATOMIC_LOAD_AND_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #301 = ATOMIC_LOAD_AND_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #300 = ATOMIC_LOAD_AND_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #299 = ATOMIC_LOAD_AND_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #298 = ATOMIC_LOAD_AND_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #297 = ATOMIC_LOAD_AND_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #296 = ATOMIC_LOAD_AND_I16 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #295 = ATOMIC_LOAD_ADD_I8_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #294 = ATOMIC_LOAD_ADD_I8 + { 3, &MipsDescs.OperandInfo[179] }, // Inst #293 = ATOMIC_LOAD_ADD_I64_POSTRA + { 3, &MipsDescs.OperandInfo[179] }, // Inst #292 = ATOMIC_LOAD_ADD_I64 + { 3, &MipsDescs.OperandInfo[170] }, // Inst #291 = ATOMIC_LOAD_ADD_I32_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #290 = ATOMIC_LOAD_ADD_I32 + { 6, &MipsDescs.OperandInfo[173] }, // Inst #289 = ATOMIC_LOAD_ADD_I16_POSTRA + { 3, &MipsDescs.OperandInfo[170] }, // Inst #288 = ATOMIC_LOAD_ADD_I16 + { 7, &MipsDescs.OperandInfo[159] }, // Inst #287 = ATOMIC_CMP_SWAP_I8_POSTRA + { 4, &MipsDescs.OperandInfo[155] }, // Inst #286 = ATOMIC_CMP_SWAP_I8 + { 4, &MipsDescs.OperandInfo[166] }, // Inst #285 = ATOMIC_CMP_SWAP_I64_POSTRA + { 4, &MipsDescs.OperandInfo[166] }, // Inst #284 = ATOMIC_CMP_SWAP_I64 + { 4, &MipsDescs.OperandInfo[155] }, // Inst #283 = ATOMIC_CMP_SWAP_I32_POSTRA + { 4, &MipsDescs.OperandInfo[155] }, // Inst #282 = ATOMIC_CMP_SWAP_I32 + { 7, &MipsDescs.OperandInfo[159] }, // Inst #281 = ATOMIC_CMP_SWAP_I16_POSTRA + { 4, &MipsDescs.OperandInfo[155] }, // Inst #280 = ATOMIC_CMP_SWAP_I16 + { 3, &MipsDescs.OperandInfo[152] }, // Inst #279 = AND_V_W_PSEUDO + { 3, &MipsDescs.OperandInfo[149] }, // Inst #278 = AND_V_H_PSEUDO + { 3, &MipsDescs.OperandInfo[146] }, // Inst #277 = AND_V_D_PSEUDO + { 4, &MipsDescs.OperandInfo[142] }, // Inst #276 = ALIGN_NM + { 2, &MipsDescs.OperandInfo[21] }, // Inst #275 = ADJCALLSTACKUP_NM + { 2, &MipsDescs.OperandInfo[21] }, // Inst #274 = ADJCALLSTACKUP + { 2, &MipsDescs.OperandInfo[21] }, // Inst #273 = ADJCALLSTACKDOWN_NM + { 2, &MipsDescs.OperandInfo[21] }, // Inst #272 = ADJCALLSTACKDOWN + { 2, &MipsDescs.OperandInfo[140] }, // Inst #271 = ABSMacro + { 4, &MipsDescs.OperandInfo[136] }, // Inst #270 = G_UBFX + { 4, &MipsDescs.OperandInfo[136] }, // Inst #269 = G_SBFX + { 2, &MipsDescs.OperandInfo[56] }, // Inst #268 = G_VECREDUCE_UMIN + { 2, &MipsDescs.OperandInfo[56] }, // Inst #267 = G_VECREDUCE_UMAX + { 2, &MipsDescs.OperandInfo[56] }, // Inst #266 = G_VECREDUCE_SMIN + { 2, &MipsDescs.OperandInfo[56] }, // Inst #265 = G_VECREDUCE_SMAX + { 2, &MipsDescs.OperandInfo[56] }, // Inst #264 = G_VECREDUCE_XOR + { 2, &MipsDescs.OperandInfo[56] }, // Inst #263 = G_VECREDUCE_OR + { 2, &MipsDescs.OperandInfo[56] }, // Inst #262 = G_VECREDUCE_AND + { 2, &MipsDescs.OperandInfo[56] }, // Inst #261 = G_VECREDUCE_MUL + { 2, &MipsDescs.OperandInfo[56] }, // Inst #260 = G_VECREDUCE_ADD + { 2, &MipsDescs.OperandInfo[56] }, // Inst #259 = G_VECREDUCE_FMINIMUM + { 2, &MipsDescs.OperandInfo[56] }, // Inst #258 = G_VECREDUCE_FMAXIMUM + { 2, &MipsDescs.OperandInfo[56] }, // Inst #257 = G_VECREDUCE_FMIN + { 2, &MipsDescs.OperandInfo[56] }, // Inst #256 = G_VECREDUCE_FMAX + { 2, &MipsDescs.OperandInfo[56] }, // Inst #255 = G_VECREDUCE_FMUL + { 2, &MipsDescs.OperandInfo[56] }, // Inst #254 = G_VECREDUCE_FADD + { 3, &MipsDescs.OperandInfo[123] }, // Inst #253 = G_VECREDUCE_SEQ_FMUL + { 3, &MipsDescs.OperandInfo[123] }, // Inst #252 = G_VECREDUCE_SEQ_FADD + { 3, &MipsDescs.OperandInfo[53] }, // Inst #251 = G_BZERO + { 4, &MipsDescs.OperandInfo[132] }, // Inst #250 = G_MEMSET + { 4, &MipsDescs.OperandInfo[132] }, // Inst #249 = G_MEMMOVE + { 3, &MipsDescs.OperandInfo[123] }, // Inst #248 = G_MEMCPY_INLINE + { 4, &MipsDescs.OperandInfo[132] }, // Inst #247 = G_MEMCPY + { 2, &MipsDescs.OperandInfo[130] }, // Inst #246 = G_WRITE_REGISTER + { 2, &MipsDescs.OperandInfo[51] }, // Inst #245 = G_READ_REGISTER + { 3, &MipsDescs.OperandInfo[96] }, // Inst #244 = G_STRICT_FLDEXP + { 2, &MipsDescs.OperandInfo[62] }, // Inst #243 = G_STRICT_FSQRT + { 4, &MipsDescs.OperandInfo[46] }, // Inst #242 = G_STRICT_FMA + { 3, &MipsDescs.OperandInfo[43] }, // Inst #241 = G_STRICT_FREM + { 3, &MipsDescs.OperandInfo[43] }, // Inst #240 = G_STRICT_FDIV + { 3, &MipsDescs.OperandInfo[43] }, // Inst #239 = G_STRICT_FMUL + { 3, &MipsDescs.OperandInfo[43] }, // Inst #238 = G_STRICT_FSUB + { 3, &MipsDescs.OperandInfo[43] }, // Inst #237 = G_STRICT_FADD + { 1, &MipsDescs.OperandInfo[50] }, // Inst #236 = G_STACKRESTORE + { 1, &MipsDescs.OperandInfo[50] }, // Inst #235 = G_STACKSAVE + { 3, &MipsDescs.OperandInfo[64] }, // Inst #234 = G_DYN_STACKALLOC + { 2, &MipsDescs.OperandInfo[51] }, // Inst #233 = G_JUMP_TABLE + { 2, &MipsDescs.OperandInfo[51] }, // Inst #232 = G_BLOCK_ADDR + { 2, &MipsDescs.OperandInfo[56] }, // Inst #231 = G_ADDRSPACE_CAST + { 2, &MipsDescs.OperandInfo[62] }, // Inst #230 = G_FNEARBYINT + { 2, &MipsDescs.OperandInfo[62] }, // Inst #229 = G_FRINT + { 2, &MipsDescs.OperandInfo[62] }, // Inst #228 = G_FFLOOR + { 2, &MipsDescs.OperandInfo[62] }, // Inst #227 = G_FSQRT + { 2, &MipsDescs.OperandInfo[62] }, // Inst #226 = G_FSIN + { 2, &MipsDescs.OperandInfo[62] }, // Inst #225 = G_FCOS + { 2, &MipsDescs.OperandInfo[62] }, // Inst #224 = G_FCEIL + { 2, &MipsDescs.OperandInfo[62] }, // Inst #223 = G_BITREVERSE + { 2, &MipsDescs.OperandInfo[62] }, // Inst #222 = G_BSWAP + { 2, &MipsDescs.OperandInfo[56] }, // Inst #221 = G_CTPOP + { 2, &MipsDescs.OperandInfo[56] }, // Inst #220 = G_CTLZ_ZERO_UNDEF + { 2, &MipsDescs.OperandInfo[56] }, // Inst #219 = G_CTLZ + { 2, &MipsDescs.OperandInfo[56] }, // Inst #218 = G_CTTZ_ZERO_UNDEF + { 2, &MipsDescs.OperandInfo[56] }, // Inst #217 = G_CTTZ + { 4, &MipsDescs.OperandInfo[126] }, // Inst #216 = G_SHUFFLE_VECTOR + { 3, &MipsDescs.OperandInfo[123] }, // Inst #215 = G_EXTRACT_VECTOR_ELT + { 4, &MipsDescs.OperandInfo[119] }, // Inst #214 = G_INSERT_VECTOR_ELT + { 3, &MipsDescs.OperandInfo[116] }, // Inst #213 = G_BRJT + { 1, &MipsDescs.OperandInfo[0] }, // Inst #212 = G_BR + { 2, &MipsDescs.OperandInfo[56] }, // Inst #211 = G_LLROUND + { 2, &MipsDescs.OperandInfo[56] }, // Inst #210 = G_LROUND + { 2, &MipsDescs.OperandInfo[62] }, // Inst #209 = G_ABS + { 3, &MipsDescs.OperandInfo[43] }, // Inst #208 = G_UMAX + { 3, &MipsDescs.OperandInfo[43] }, // Inst #207 = G_UMIN + { 3, &MipsDescs.OperandInfo[43] }, // Inst #206 = G_SMAX + { 3, &MipsDescs.OperandInfo[43] }, // Inst #205 = G_SMIN + { 3, &MipsDescs.OperandInfo[96] }, // Inst #204 = G_PTRMASK + { 3, &MipsDescs.OperandInfo[96] }, // Inst #203 = G_PTR_ADD + { 0, &MipsDescs.OperandInfo[1] }, // Inst #202 = G_RESET_FPMODE + { 1, &MipsDescs.OperandInfo[50] }, // Inst #201 = G_SET_FPMODE + { 1, &MipsDescs.OperandInfo[50] }, // Inst #200 = G_GET_FPMODE + { 0, &MipsDescs.OperandInfo[1] }, // Inst #199 = G_RESET_FPENV + { 1, &MipsDescs.OperandInfo[50] }, // Inst #198 = G_SET_FPENV + { 1, &MipsDescs.OperandInfo[50] }, // Inst #197 = G_GET_FPENV + { 3, &MipsDescs.OperandInfo[43] }, // Inst #196 = G_FMAXIMUM + { 3, &MipsDescs.OperandInfo[43] }, // Inst #195 = G_FMINIMUM + { 3, &MipsDescs.OperandInfo[43] }, // Inst #194 = G_FMAXNUM_IEEE + { 3, &MipsDescs.OperandInfo[43] }, // Inst #193 = G_FMINNUM_IEEE + { 3, &MipsDescs.OperandInfo[43] }, // Inst #192 = G_FMAXNUM + { 3, &MipsDescs.OperandInfo[43] }, // Inst #191 = G_FMINNUM + { 2, &MipsDescs.OperandInfo[62] }, // Inst #190 = G_FCANONICALIZE + { 3, &MipsDescs.OperandInfo[93] }, // Inst #189 = G_IS_FPCLASS + { 3, &MipsDescs.OperandInfo[96] }, // Inst #188 = G_FCOPYSIGN + { 2, &MipsDescs.OperandInfo[62] }, // Inst #187 = G_FABS + { 2, &MipsDescs.OperandInfo[56] }, // Inst #186 = G_UITOFP + { 2, &MipsDescs.OperandInfo[56] }, // Inst #185 = G_SITOFP + { 2, &MipsDescs.OperandInfo[56] }, // Inst #184 = G_FPTOUI + { 2, &MipsDescs.OperandInfo[56] }, // Inst #183 = G_FPTOSI + { 2, &MipsDescs.OperandInfo[56] }, // Inst #182 = G_FPTRUNC + { 2, &MipsDescs.OperandInfo[56] }, // Inst #181 = G_FPEXT + { 2, &MipsDescs.OperandInfo[62] }, // Inst #180 = G_FNEG + { 3, &MipsDescs.OperandInfo[86] }, // Inst #179 = G_FFREXP + { 3, &MipsDescs.OperandInfo[96] }, // Inst #178 = G_FLDEXP + { 2, &MipsDescs.OperandInfo[62] }, // Inst #177 = G_FLOG10 + { 2, &MipsDescs.OperandInfo[62] }, // Inst #176 = G_FLOG2 + { 2, &MipsDescs.OperandInfo[62] }, // Inst #175 = G_FLOG + { 2, &MipsDescs.OperandInfo[62] }, // Inst #174 = G_FEXP10 + { 2, &MipsDescs.OperandInfo[62] }, // Inst #173 = G_FEXP2 + { 2, &MipsDescs.OperandInfo[62] }, // Inst #172 = G_FEXP + { 3, &MipsDescs.OperandInfo[96] }, // Inst #171 = G_FPOWI + { 3, &MipsDescs.OperandInfo[43] }, // Inst #170 = G_FPOW + { 3, &MipsDescs.OperandInfo[43] }, // Inst #169 = G_FREM + { 3, &MipsDescs.OperandInfo[43] }, // Inst #168 = G_FDIV + { 4, &MipsDescs.OperandInfo[46] }, // Inst #167 = G_FMAD + { 4, &MipsDescs.OperandInfo[46] }, // Inst #166 = G_FMA + { 3, &MipsDescs.OperandInfo[43] }, // Inst #165 = G_FMUL + { 3, &MipsDescs.OperandInfo[43] }, // Inst #164 = G_FSUB + { 3, &MipsDescs.OperandInfo[43] }, // Inst #163 = G_FADD + { 4, &MipsDescs.OperandInfo[112] }, // Inst #162 = G_UDIVFIXSAT + { 4, &MipsDescs.OperandInfo[112] }, // Inst #161 = G_SDIVFIXSAT + { 4, &MipsDescs.OperandInfo[112] }, // Inst #160 = G_UDIVFIX + { 4, &MipsDescs.OperandInfo[112] }, // Inst #159 = G_SDIVFIX + { 4, &MipsDescs.OperandInfo[112] }, // Inst #158 = G_UMULFIXSAT + { 4, &MipsDescs.OperandInfo[112] }, // Inst #157 = G_SMULFIXSAT + { 4, &MipsDescs.OperandInfo[112] }, // Inst #156 = G_UMULFIX + { 4, &MipsDescs.OperandInfo[112] }, // Inst #155 = G_SMULFIX + { 3, &MipsDescs.OperandInfo[96] }, // Inst #154 = G_SSHLSAT + { 3, &MipsDescs.OperandInfo[96] }, // Inst #153 = G_USHLSAT + { 3, &MipsDescs.OperandInfo[43] }, // Inst #152 = G_SSUBSAT + { 3, &MipsDescs.OperandInfo[43] }, // Inst #151 = G_USUBSAT + { 3, &MipsDescs.OperandInfo[43] }, // Inst #150 = G_SADDSAT + { 3, &MipsDescs.OperandInfo[43] }, // Inst #149 = G_UADDSAT + { 3, &MipsDescs.OperandInfo[43] }, // Inst #148 = G_SMULH + { 3, &MipsDescs.OperandInfo[43] }, // Inst #147 = G_UMULH + { 4, &MipsDescs.OperandInfo[82] }, // Inst #146 = G_SMULO + { 4, &MipsDescs.OperandInfo[82] }, // Inst #145 = G_UMULO + { 5, &MipsDescs.OperandInfo[107] }, // Inst #144 = G_SSUBE + { 4, &MipsDescs.OperandInfo[82] }, // Inst #143 = G_SSUBO + { 5, &MipsDescs.OperandInfo[107] }, // Inst #142 = G_SADDE + { 4, &MipsDescs.OperandInfo[82] }, // Inst #141 = G_SADDO + { 5, &MipsDescs.OperandInfo[107] }, // Inst #140 = G_USUBE + { 4, &MipsDescs.OperandInfo[82] }, // Inst #139 = G_USUBO + { 5, &MipsDescs.OperandInfo[107] }, // Inst #138 = G_UADDE + { 4, &MipsDescs.OperandInfo[82] }, // Inst #137 = G_UADDO + { 4, &MipsDescs.OperandInfo[82] }, // Inst #136 = G_SELECT + { 4, &MipsDescs.OperandInfo[103] }, // Inst #135 = G_FCMP + { 4, &MipsDescs.OperandInfo[103] }, // Inst #134 = G_ICMP + { 3, &MipsDescs.OperandInfo[96] }, // Inst #133 = G_ROTL + { 3, &MipsDescs.OperandInfo[96] }, // Inst #132 = G_ROTR + { 4, &MipsDescs.OperandInfo[99] }, // Inst #131 = G_FSHR + { 4, &MipsDescs.OperandInfo[99] }, // Inst #130 = G_FSHL + { 3, &MipsDescs.OperandInfo[96] }, // Inst #129 = G_ASHR + { 3, &MipsDescs.OperandInfo[96] }, // Inst #128 = G_LSHR + { 3, &MipsDescs.OperandInfo[96] }, // Inst #127 = G_SHL + { 2, &MipsDescs.OperandInfo[56] }, // Inst #126 = G_ZEXT + { 3, &MipsDescs.OperandInfo[40] }, // Inst #125 = G_SEXT_INREG + { 2, &MipsDescs.OperandInfo[56] }, // Inst #124 = G_SEXT + { 3, &MipsDescs.OperandInfo[93] }, // Inst #123 = G_VAARG + { 1, &MipsDescs.OperandInfo[50] }, // Inst #122 = G_VASTART + { 2, &MipsDescs.OperandInfo[51] }, // Inst #121 = G_FCONSTANT + { 2, &MipsDescs.OperandInfo[51] }, // Inst #120 = G_CONSTANT + { 2, &MipsDescs.OperandInfo[56] }, // Inst #119 = G_TRUNC + { 2, &MipsDescs.OperandInfo[56] }, // Inst #118 = G_ANYEXT + { 1, &MipsDescs.OperandInfo[0] }, // Inst #117 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS + { 1, &MipsDescs.OperandInfo[0] }, // Inst #116 = G_INTRINSIC_CONVERGENT + { 1, &MipsDescs.OperandInfo[0] }, // Inst #115 = G_INTRINSIC_W_SIDE_EFFECTS + { 1, &MipsDescs.OperandInfo[0] }, // Inst #114 = G_INTRINSIC + { 0, &MipsDescs.OperandInfo[1] }, // Inst #113 = G_INVOKE_REGION_START + { 1, &MipsDescs.OperandInfo[50] }, // Inst #112 = G_BRINDIRECT + { 2, &MipsDescs.OperandInfo[51] }, // Inst #111 = G_BRCOND + { 4, &MipsDescs.OperandInfo[89] }, // Inst #110 = G_PREFETCH + { 2, &MipsDescs.OperandInfo[21] }, // Inst #109 = G_FENCE + { 3, &MipsDescs.OperandInfo[86] }, // Inst #108 = G_ATOMICRMW_UDEC_WRAP + { 3, &MipsDescs.OperandInfo[86] }, // Inst #107 = G_ATOMICRMW_UINC_WRAP + { 3, &MipsDescs.OperandInfo[86] }, // Inst #106 = G_ATOMICRMW_FMIN + { 3, &MipsDescs.OperandInfo[86] }, // Inst #105 = G_ATOMICRMW_FMAX + { 3, &MipsDescs.OperandInfo[86] }, // Inst #104 = G_ATOMICRMW_FSUB + { 3, &MipsDescs.OperandInfo[86] }, // Inst #103 = G_ATOMICRMW_FADD + { 3, &MipsDescs.OperandInfo[86] }, // Inst #102 = G_ATOMICRMW_UMIN + { 3, &MipsDescs.OperandInfo[86] }, // Inst #101 = G_ATOMICRMW_UMAX + { 3, &MipsDescs.OperandInfo[86] }, // Inst #100 = G_ATOMICRMW_MIN + { 3, &MipsDescs.OperandInfo[86] }, // Inst #99 = G_ATOMICRMW_MAX + { 3, &MipsDescs.OperandInfo[86] }, // Inst #98 = G_ATOMICRMW_XOR + { 3, &MipsDescs.OperandInfo[86] }, // Inst #97 = G_ATOMICRMW_OR + { 3, &MipsDescs.OperandInfo[86] }, // Inst #96 = G_ATOMICRMW_NAND + { 3, &MipsDescs.OperandInfo[86] }, // Inst #95 = G_ATOMICRMW_AND + { 3, &MipsDescs.OperandInfo[86] }, // Inst #94 = G_ATOMICRMW_SUB + { 3, &MipsDescs.OperandInfo[86] }, // Inst #93 = G_ATOMICRMW_ADD + { 3, &MipsDescs.OperandInfo[86] }, // Inst #92 = G_ATOMICRMW_XCHG + { 4, &MipsDescs.OperandInfo[82] }, // Inst #91 = G_ATOMIC_CMPXCHG + { 5, &MipsDescs.OperandInfo[77] }, // Inst #90 = G_ATOMIC_CMPXCHG_WITH_SUCCESS + { 5, &MipsDescs.OperandInfo[72] }, // Inst #89 = G_INDEXED_STORE + { 2, &MipsDescs.OperandInfo[56] }, // Inst #88 = G_STORE + { 5, &MipsDescs.OperandInfo[67] }, // Inst #87 = G_INDEXED_ZEXTLOAD + { 5, &MipsDescs.OperandInfo[67] }, // Inst #86 = G_INDEXED_SEXTLOAD + { 5, &MipsDescs.OperandInfo[67] }, // Inst #85 = G_INDEXED_LOAD + { 2, &MipsDescs.OperandInfo[56] }, // Inst #84 = G_ZEXTLOAD + { 2, &MipsDescs.OperandInfo[56] }, // Inst #83 = G_SEXTLOAD + { 2, &MipsDescs.OperandInfo[56] }, // Inst #82 = G_LOAD + { 1, &MipsDescs.OperandInfo[50] }, // Inst #81 = G_READCYCLECOUNTER + { 2, &MipsDescs.OperandInfo[62] }, // Inst #80 = G_INTRINSIC_ROUNDEVEN + { 2, &MipsDescs.OperandInfo[56] }, // Inst #79 = G_INTRINSIC_LRINT + { 2, &MipsDescs.OperandInfo[62] }, // Inst #78 = G_INTRINSIC_ROUND + { 2, &MipsDescs.OperandInfo[62] }, // Inst #77 = G_INTRINSIC_TRUNC + { 3, &MipsDescs.OperandInfo[64] }, // Inst #76 = G_INTRINSIC_FPTRUNC_ROUND + { 2, &MipsDescs.OperandInfo[62] }, // Inst #75 = G_CONSTANT_FOLD_BARRIER + { 2, &MipsDescs.OperandInfo[62] }, // Inst #74 = G_FREEZE + { 2, &MipsDescs.OperandInfo[56] }, // Inst #73 = G_BITCAST + { 2, &MipsDescs.OperandInfo[56] }, // Inst #72 = G_INTTOPTR + { 2, &MipsDescs.OperandInfo[56] }, // Inst #71 = G_PTRTOINT + { 2, &MipsDescs.OperandInfo[56] }, // Inst #70 = G_CONCAT_VECTORS + { 2, &MipsDescs.OperandInfo[56] }, // Inst #69 = G_BUILD_VECTOR_TRUNC + { 2, &MipsDescs.OperandInfo[56] }, // Inst #68 = G_BUILD_VECTOR + { 2, &MipsDescs.OperandInfo[56] }, // Inst #67 = G_MERGE_VALUES + { 4, &MipsDescs.OperandInfo[58] }, // Inst #66 = G_INSERT + { 2, &MipsDescs.OperandInfo[56] }, // Inst #65 = G_UNMERGE_VALUES + { 3, &MipsDescs.OperandInfo[53] }, // Inst #64 = G_EXTRACT + { 2, &MipsDescs.OperandInfo[51] }, // Inst #63 = G_CONSTANT_POOL + { 2, &MipsDescs.OperandInfo[51] }, // Inst #62 = G_GLOBAL_VALUE + { 2, &MipsDescs.OperandInfo[51] }, // Inst #61 = G_FRAME_INDEX + { 1, &MipsDescs.OperandInfo[50] }, // Inst #60 = G_PHI + { 1, &MipsDescs.OperandInfo[50] }, // Inst #59 = G_IMPLICIT_DEF + { 3, &MipsDescs.OperandInfo[43] }, // Inst #58 = G_XOR + { 3, &MipsDescs.OperandInfo[43] }, // Inst #57 = G_OR + { 3, &MipsDescs.OperandInfo[43] }, // Inst #56 = G_AND + { 4, &MipsDescs.OperandInfo[46] }, // Inst #55 = G_UDIVREM + { 4, &MipsDescs.OperandInfo[46] }, // Inst #54 = G_SDIVREM + { 3, &MipsDescs.OperandInfo[43] }, // Inst #53 = G_UREM + { 3, &MipsDescs.OperandInfo[43] }, // Inst #52 = G_SREM + { 3, &MipsDescs.OperandInfo[43] }, // Inst #51 = G_UDIV + { 3, &MipsDescs.OperandInfo[43] }, // Inst #50 = G_SDIV + { 3, &MipsDescs.OperandInfo[43] }, // Inst #49 = G_MUL + { 3, &MipsDescs.OperandInfo[43] }, // Inst #48 = G_SUB + { 3, &MipsDescs.OperandInfo[43] }, // Inst #47 = G_ADD + { 3, &MipsDescs.OperandInfo[40] }, // Inst #46 = G_ASSERT_ALIGN + { 3, &MipsDescs.OperandInfo[40] }, // Inst #45 = G_ASSERT_ZEXT + { 3, &MipsDescs.OperandInfo[40] }, // Inst #44 = G_ASSERT_SEXT + { 1, &MipsDescs.OperandInfo[1] }, // Inst #43 = JUMP_TABLE_DEBUG_INFO + { 0, &MipsDescs.OperandInfo[1] }, // Inst #42 = MEMBARRIER + { 0, &MipsDescs.OperandInfo[1] }, // Inst #41 = ICALL_BRANCH_FUNNEL + { 3, &MipsDescs.OperandInfo[37] }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL + { 2, &MipsDescs.OperandInfo[35] }, // Inst #39 = PATCHABLE_EVENT_CALL + { 0, &MipsDescs.OperandInfo[1] }, // Inst #38 = PATCHABLE_TAIL_CALL + { 0, &MipsDescs.OperandInfo[1] }, // Inst #37 = PATCHABLE_FUNCTION_EXIT + { 0, &MipsDescs.OperandInfo[1] }, // Inst #36 = PATCHABLE_RET + { 0, &MipsDescs.OperandInfo[1] }, // Inst #35 = PATCHABLE_FUNCTION_ENTER + { 0, &MipsDescs.OperandInfo[1] }, // Inst #34 = PATCHABLE_OP + { 1, &MipsDescs.OperandInfo[0] }, // Inst #33 = FAULTING_OP + { 2, &MipsDescs.OperandInfo[33] }, // Inst #32 = LOCAL_ESCAPE + { 0, &MipsDescs.OperandInfo[1] }, // Inst #31 = STATEPOINT + { 3, &MipsDescs.OperandInfo[30] }, // Inst #30 = PREALLOCATED_ARG + { 1, &MipsDescs.OperandInfo[1] }, // Inst #29 = PREALLOCATED_SETUP + { 1, &MipsDescs.OperandInfo[29] }, // Inst #28 = LOAD_STACK_GUARD + { 6, &MipsDescs.OperandInfo[23] }, // Inst #27 = PATCHPOINT + { 0, &MipsDescs.OperandInfo[1] }, // Inst #26 = FENTRY_CALL + { 2, &MipsDescs.OperandInfo[21] }, // Inst #25 = STACKMAP + { 2, &MipsDescs.OperandInfo[19] }, // Inst #24 = ARITH_FENCE + { 4, &MipsDescs.OperandInfo[15] }, // Inst #23 = PSEUDO_PROBE + { 1, &MipsDescs.OperandInfo[1] }, // Inst #22 = LIFETIME_END + { 1, &MipsDescs.OperandInfo[1] }, // Inst #21 = LIFETIME_START + { 0, &MipsDescs.OperandInfo[1] }, // Inst #20 = BUNDLE + { 2, &MipsDescs.OperandInfo[13] }, // Inst #19 = COPY + { 2, &MipsDescs.OperandInfo[13] }, // Inst #18 = REG_SEQUENCE + { 1, &MipsDescs.OperandInfo[0] }, // Inst #17 = DBG_LABEL + { 0, &MipsDescs.OperandInfo[1] }, // Inst #16 = DBG_PHI + { 0, &MipsDescs.OperandInfo[1] }, // Inst #15 = DBG_INSTR_REF + { 0, &MipsDescs.OperandInfo[1] }, // Inst #14 = DBG_VALUE_LIST + { 0, &MipsDescs.OperandInfo[1] }, // Inst #13 = DBG_VALUE + { 3, &MipsDescs.OperandInfo[2] }, // Inst #12 = COPY_TO_REGCLASS + { 4, &MipsDescs.OperandInfo[9] }, // Inst #11 = SUBREG_TO_REG + { 1, &MipsDescs.OperandInfo[0] }, // Inst #10 = IMPLICIT_DEF + { 4, &MipsDescs.OperandInfo[5] }, // Inst #9 = INSERT_SUBREG + { 3, &MipsDescs.OperandInfo[2] }, // Inst #8 = EXTRACT_SUBREG + { 0, &MipsDescs.OperandInfo[1] }, // Inst #7 = KILL + { 1, &MipsDescs.OperandInfo[1] }, // Inst #6 = ANNOTATION_LABEL + { 1, &MipsDescs.OperandInfo[1] }, // Inst #5 = GC_LABEL + { 1, &MipsDescs.OperandInfo[1] }, // Inst #4 = EH_LABEL + { 1, &MipsDescs.OperandInfo[1] }, // Inst #3 = CFI_INSTRUCTION + { 0, &MipsDescs.OperandInfo[1] }, // Inst #2 = INLINEASM_BR + { 0, &MipsDescs.OperandInfo[1] }, // Inst #1 = INLINEASM + { 1, &MipsDescs.OperandInfo[0] }, // Inst #0 = PHI + }, { + /* 0 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 1 */ + /* 1 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 2 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 5 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 9 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 13 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 15 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 19 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) }, + /* 21 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 23 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 29 */ { 0, 0|(1<, 2013-2019 */ - - #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM enum { Mips_NoRegister, Mips_AT = 1, - Mips_DSPCCond = 2, - Mips_DSPCarry = 3, - Mips_DSPEFI = 4, - Mips_DSPOutFlag = 5, - Mips_DSPPos = 6, - Mips_DSPSCount = 7, - Mips_FP = 8, - Mips_GP = 9, - Mips_MSAAccess = 10, - Mips_MSACSR = 11, - Mips_MSAIR = 12, - Mips_MSAMap = 13, - Mips_MSAModify = 14, - Mips_MSARequest = 15, - Mips_MSASave = 16, - Mips_MSAUnmap = 17, - Mips_PC = 18, - Mips_RA = 19, - Mips_SP = 20, - Mips_ZERO = 21, - Mips_A0 = 22, - Mips_A1 = 23, - Mips_A2 = 24, - Mips_A3 = 25, - Mips_AC0 = 26, - Mips_AC1 = 27, - Mips_AC2 = 28, - Mips_AC3 = 29, - Mips_AT_64 = 30, - Mips_CC0 = 31, - Mips_CC1 = 32, - Mips_CC2 = 33, - Mips_CC3 = 34, - Mips_CC4 = 35, - Mips_CC5 = 36, - Mips_CC6 = 37, - Mips_CC7 = 38, - Mips_COP20 = 39, - Mips_COP21 = 40, - Mips_COP22 = 41, - Mips_COP23 = 42, - Mips_COP24 = 43, - Mips_COP25 = 44, - Mips_COP26 = 45, - Mips_COP27 = 46, - Mips_COP28 = 47, - Mips_COP29 = 48, - Mips_COP30 = 49, - Mips_COP31 = 50, - Mips_COP32 = 51, - Mips_COP33 = 52, - Mips_COP34 = 53, - Mips_COP35 = 54, - Mips_COP36 = 55, - Mips_COP37 = 56, - Mips_COP38 = 57, - Mips_COP39 = 58, - Mips_COP210 = 59, - Mips_COP211 = 60, - Mips_COP212 = 61, - Mips_COP213 = 62, - Mips_COP214 = 63, - Mips_COP215 = 64, - Mips_COP216 = 65, - Mips_COP217 = 66, - Mips_COP218 = 67, - Mips_COP219 = 68, - Mips_COP220 = 69, - Mips_COP221 = 70, - Mips_COP222 = 71, - Mips_COP223 = 72, - Mips_COP224 = 73, - Mips_COP225 = 74, - Mips_COP226 = 75, - Mips_COP227 = 76, - Mips_COP228 = 77, - Mips_COP229 = 78, - Mips_COP230 = 79, - Mips_COP231 = 80, - Mips_COP310 = 81, - Mips_COP311 = 82, - Mips_COP312 = 83, - Mips_COP313 = 84, - Mips_COP314 = 85, - Mips_COP315 = 86, - Mips_COP316 = 87, - Mips_COP317 = 88, - Mips_COP318 = 89, - Mips_COP319 = 90, - Mips_COP320 = 91, - Mips_COP321 = 92, - Mips_COP322 = 93, - Mips_COP323 = 94, - Mips_COP324 = 95, - Mips_COP325 = 96, - Mips_COP326 = 97, - Mips_COP327 = 98, - Mips_COP328 = 99, - Mips_COP329 = 100, - Mips_COP330 = 101, - Mips_COP331 = 102, - Mips_D0 = 103, - Mips_D1 = 104, - Mips_D2 = 105, - Mips_D3 = 106, - Mips_D4 = 107, - Mips_D5 = 108, - Mips_D6 = 109, - Mips_D7 = 110, - Mips_D8 = 111, - Mips_D9 = 112, - Mips_D10 = 113, - Mips_D11 = 114, - Mips_D12 = 115, - Mips_D13 = 116, - Mips_D14 = 117, - Mips_D15 = 118, - Mips_DSPOutFlag20 = 119, - Mips_DSPOutFlag21 = 120, - Mips_DSPOutFlag22 = 121, - Mips_DSPOutFlag23 = 122, - Mips_F0 = 123, - Mips_F1 = 124, - Mips_F2 = 125, - Mips_F3 = 126, - Mips_F4 = 127, - Mips_F5 = 128, - Mips_F6 = 129, - Mips_F7 = 130, - Mips_F8 = 131, - Mips_F9 = 132, - Mips_F10 = 133, - Mips_F11 = 134, - Mips_F12 = 135, - Mips_F13 = 136, - Mips_F14 = 137, - Mips_F15 = 138, - Mips_F16 = 139, - Mips_F17 = 140, - Mips_F18 = 141, - Mips_F19 = 142, - Mips_F20 = 143, - Mips_F21 = 144, - Mips_F22 = 145, - Mips_F23 = 146, - Mips_F24 = 147, - Mips_F25 = 148, - Mips_F26 = 149, - Mips_F27 = 150, - Mips_F28 = 151, - Mips_F29 = 152, - Mips_F30 = 153, - Mips_F31 = 154, - Mips_FCC0 = 155, - Mips_FCC1 = 156, - Mips_FCC2 = 157, - Mips_FCC3 = 158, - Mips_FCC4 = 159, - Mips_FCC5 = 160, - Mips_FCC6 = 161, - Mips_FCC7 = 162, - Mips_FCR0 = 163, - Mips_FCR1 = 164, - Mips_FCR2 = 165, - Mips_FCR3 = 166, - Mips_FCR4 = 167, - Mips_FCR5 = 168, - Mips_FCR6 = 169, - Mips_FCR7 = 170, - Mips_FCR8 = 171, - Mips_FCR9 = 172, - Mips_FCR10 = 173, - Mips_FCR11 = 174, - Mips_FCR12 = 175, - Mips_FCR13 = 176, - Mips_FCR14 = 177, - Mips_FCR15 = 178, - Mips_FCR16 = 179, - Mips_FCR17 = 180, - Mips_FCR18 = 181, - Mips_FCR19 = 182, - Mips_FCR20 = 183, - Mips_FCR21 = 184, - Mips_FCR22 = 185, - Mips_FCR23 = 186, - Mips_FCR24 = 187, - Mips_FCR25 = 188, - Mips_FCR26 = 189, - Mips_FCR27 = 190, - Mips_FCR28 = 191, - Mips_FCR29 = 192, - Mips_FCR30 = 193, - Mips_FCR31 = 194, - Mips_FP_64 = 195, - Mips_F_HI0 = 196, - Mips_F_HI1 = 197, - Mips_F_HI2 = 198, - Mips_F_HI3 = 199, - Mips_F_HI4 = 200, - Mips_F_HI5 = 201, - Mips_F_HI6 = 202, - Mips_F_HI7 = 203, - Mips_F_HI8 = 204, - Mips_F_HI9 = 205, - Mips_F_HI10 = 206, - Mips_F_HI11 = 207, - Mips_F_HI12 = 208, - Mips_F_HI13 = 209, - Mips_F_HI14 = 210, - Mips_F_HI15 = 211, - Mips_F_HI16 = 212, - Mips_F_HI17 = 213, - Mips_F_HI18 = 214, - Mips_F_HI19 = 215, - Mips_F_HI20 = 216, - Mips_F_HI21 = 217, - Mips_F_HI22 = 218, - Mips_F_HI23 = 219, - Mips_F_HI24 = 220, - Mips_F_HI25 = 221, - Mips_F_HI26 = 222, - Mips_F_HI27 = 223, - Mips_F_HI28 = 224, - Mips_F_HI29 = 225, - Mips_F_HI30 = 226, - Mips_F_HI31 = 227, - Mips_GP_64 = 228, - Mips_HI0 = 229, - Mips_HI1 = 230, - Mips_HI2 = 231, - Mips_HI3 = 232, - Mips_HWR0 = 233, - Mips_HWR1 = 234, - Mips_HWR2 = 235, - Mips_HWR3 = 236, - Mips_HWR4 = 237, - Mips_HWR5 = 238, - Mips_HWR6 = 239, - Mips_HWR7 = 240, - Mips_HWR8 = 241, - Mips_HWR9 = 242, - Mips_HWR10 = 243, - Mips_HWR11 = 244, - Mips_HWR12 = 245, - Mips_HWR13 = 246, - Mips_HWR14 = 247, - Mips_HWR15 = 248, - Mips_HWR16 = 249, - Mips_HWR17 = 250, - Mips_HWR18 = 251, - Mips_HWR19 = 252, - Mips_HWR20 = 253, - Mips_HWR21 = 254, - Mips_HWR22 = 255, - Mips_HWR23 = 256, - Mips_HWR24 = 257, - Mips_HWR25 = 258, - Mips_HWR26 = 259, - Mips_HWR27 = 260, - Mips_HWR28 = 261, - Mips_HWR29 = 262, - Mips_HWR30 = 263, - Mips_HWR31 = 264, - Mips_K0 = 265, - Mips_K1 = 266, - Mips_LO0 = 267, - Mips_LO1 = 268, - Mips_LO2 = 269, - Mips_LO3 = 270, - Mips_MPL0 = 271, - Mips_MPL1 = 272, - Mips_MPL2 = 273, - Mips_P0 = 274, - Mips_P1 = 275, - Mips_P2 = 276, - Mips_RA_64 = 277, - Mips_S0 = 278, - Mips_S1 = 279, - Mips_S2 = 280, - Mips_S3 = 281, - Mips_S4 = 282, - Mips_S5 = 283, - Mips_S6 = 284, - Mips_S7 = 285, - Mips_SP_64 = 286, - Mips_T0 = 287, - Mips_T1 = 288, - Mips_T2 = 289, - Mips_T3 = 290, - Mips_T4 = 291, - Mips_T5 = 292, - Mips_T6 = 293, - Mips_T7 = 294, - Mips_T8 = 295, - Mips_T9 = 296, - Mips_V0 = 297, - Mips_V1 = 298, - Mips_W0 = 299, - Mips_W1 = 300, - Mips_W2 = 301, - Mips_W3 = 302, - Mips_W4 = 303, - Mips_W5 = 304, - Mips_W6 = 305, - Mips_W7 = 306, - Mips_W8 = 307, - Mips_W9 = 308, - Mips_W10 = 309, - Mips_W11 = 310, - Mips_W12 = 311, - Mips_W13 = 312, - Mips_W14 = 313, - Mips_W15 = 314, - Mips_W16 = 315, - Mips_W17 = 316, - Mips_W18 = 317, - Mips_W19 = 318, - Mips_W20 = 319, - Mips_W21 = 320, - Mips_W22 = 321, - Mips_W23 = 322, - Mips_W24 = 323, - Mips_W25 = 324, - Mips_W26 = 325, - Mips_W27 = 326, - Mips_W28 = 327, - Mips_W29 = 328, - Mips_W30 = 329, - Mips_W31 = 330, - Mips_ZERO_64 = 331, - Mips_A0_64 = 332, - Mips_A1_64 = 333, - Mips_A2_64 = 334, - Mips_A3_64 = 335, - Mips_AC0_64 = 336, - Mips_D0_64 = 337, - Mips_D1_64 = 338, - Mips_D2_64 = 339, - Mips_D3_64 = 340, - Mips_D4_64 = 341, - Mips_D5_64 = 342, - Mips_D6_64 = 343, - Mips_D7_64 = 344, - Mips_D8_64 = 345, - Mips_D9_64 = 346, - Mips_D10_64 = 347, - Mips_D11_64 = 348, - Mips_D12_64 = 349, - Mips_D13_64 = 350, - Mips_D14_64 = 351, - Mips_D15_64 = 352, - Mips_D16_64 = 353, - Mips_D17_64 = 354, - Mips_D18_64 = 355, - Mips_D19_64 = 356, - Mips_D20_64 = 357, - Mips_D21_64 = 358, - Mips_D22_64 = 359, - Mips_D23_64 = 360, - Mips_D24_64 = 361, - Mips_D25_64 = 362, - Mips_D26_64 = 363, - Mips_D27_64 = 364, - Mips_D28_64 = 365, - Mips_D29_64 = 366, - Mips_D30_64 = 367, - Mips_D31_64 = 368, - Mips_DSPOutFlag16_19 = 369, - Mips_HI0_64 = 370, - Mips_K0_64 = 371, - Mips_K1_64 = 372, - Mips_LO0_64 = 373, - Mips_S0_64 = 374, - Mips_S1_64 = 375, - Mips_S2_64 = 376, - Mips_S3_64 = 377, - Mips_S4_64 = 378, - Mips_S5_64 = 379, - Mips_S6_64 = 380, - Mips_S7_64 = 381, - Mips_T0_64 = 382, - Mips_T1_64 = 383, - Mips_T2_64 = 384, - Mips_T3_64 = 385, - Mips_T4_64 = 386, - Mips_T5_64 = 387, - Mips_T6_64 = 388, - Mips_T7_64 = 389, - Mips_T8_64 = 390, - Mips_T9_64 = 391, - Mips_V0_64 = 392, - Mips_V1_64 = 393, - Mips_NUM_TARGET_REGS // 394 + Mips_AT_NM = 2, + Mips_DSPCCond = 3, + Mips_DSPCarry = 4, + Mips_DSPEFI = 5, + Mips_DSPOutFlag = 6, + Mips_DSPPos = 7, + Mips_DSPSCount = 8, + Mips_FP = 9, + Mips_FP_NM = 10, + Mips_GP = 11, + Mips_GP_NM = 12, + Mips_MSAAccess = 13, + Mips_MSACSR = 14, + Mips_MSAIR = 15, + Mips_MSAMap = 16, + Mips_MSAModify = 17, + Mips_MSARequest = 18, + Mips_MSASave = 19, + Mips_MSAUnmap = 20, + Mips_PC = 21, + Mips_RA = 22, + Mips_RA_NM = 23, + Mips_SP = 24, + Mips_SP_NM = 25, + Mips_ZERO = 26, + Mips_ZERO_NM = 27, + Mips_A0 = 28, + Mips_A1 = 29, + Mips_A2 = 30, + Mips_A3 = 31, + Mips_AC0 = 32, + Mips_AC1 = 33, + Mips_AC2 = 34, + Mips_AC3 = 35, + Mips_AT_64 = 36, + Mips_COP00 = 37, + Mips_COP01 = 38, + Mips_COP02 = 39, + Mips_COP03 = 40, + Mips_COP04 = 41, + Mips_COP05 = 42, + Mips_COP06 = 43, + Mips_COP07 = 44, + Mips_COP08 = 45, + Mips_COP09 = 46, + Mips_COP20 = 47, + Mips_COP21 = 48, + Mips_COP22 = 49, + Mips_COP23 = 50, + Mips_COP24 = 51, + Mips_COP25 = 52, + Mips_COP26 = 53, + Mips_COP27 = 54, + Mips_COP28 = 55, + Mips_COP29 = 56, + Mips_COP30 = 57, + Mips_COP31 = 58, + Mips_COP32 = 59, + Mips_COP33 = 60, + Mips_COP34 = 61, + Mips_COP35 = 62, + Mips_COP36 = 63, + Mips_COP37 = 64, + Mips_COP38 = 65, + Mips_COP39 = 66, + Mips_COP010 = 67, + Mips_COP011 = 68, + Mips_COP012 = 69, + Mips_COP013 = 70, + Mips_COP014 = 71, + Mips_COP015 = 72, + Mips_COP016 = 73, + Mips_COP017 = 74, + Mips_COP018 = 75, + Mips_COP019 = 76, + Mips_COP020 = 77, + Mips_COP021 = 78, + Mips_COP022 = 79, + Mips_COP023 = 80, + Mips_COP024 = 81, + Mips_COP025 = 82, + Mips_COP026 = 83, + Mips_COP027 = 84, + Mips_COP028 = 85, + Mips_COP029 = 86, + Mips_COP030 = 87, + Mips_COP031 = 88, + Mips_COP210 = 89, + Mips_COP211 = 90, + Mips_COP212 = 91, + Mips_COP213 = 92, + Mips_COP214 = 93, + Mips_COP215 = 94, + Mips_COP216 = 95, + Mips_COP217 = 96, + Mips_COP218 = 97, + Mips_COP219 = 98, + Mips_COP220 = 99, + Mips_COP221 = 100, + Mips_COP222 = 101, + Mips_COP223 = 102, + Mips_COP224 = 103, + Mips_COP225 = 104, + Mips_COP226 = 105, + Mips_COP227 = 106, + Mips_COP228 = 107, + Mips_COP229 = 108, + Mips_COP230 = 109, + Mips_COP231 = 110, + Mips_COP310 = 111, + Mips_COP311 = 112, + Mips_COP312 = 113, + Mips_COP313 = 114, + Mips_COP314 = 115, + Mips_COP315 = 116, + Mips_COP316 = 117, + Mips_COP317 = 118, + Mips_COP318 = 119, + Mips_COP319 = 120, + Mips_COP320 = 121, + Mips_COP321 = 122, + Mips_COP322 = 123, + Mips_COP323 = 124, + Mips_COP324 = 125, + Mips_COP325 = 126, + Mips_COP326 = 127, + Mips_COP327 = 128, + Mips_COP328 = 129, + Mips_COP329 = 130, + Mips_COP330 = 131, + Mips_COP331 = 132, + Mips_D0 = 133, + Mips_D1 = 134, + Mips_D2 = 135, + Mips_D3 = 136, + Mips_D4 = 137, + Mips_D5 = 138, + Mips_D6 = 139, + Mips_D7 = 140, + Mips_D8 = 141, + Mips_D9 = 142, + Mips_D10 = 143, + Mips_D11 = 144, + Mips_D12 = 145, + Mips_D13 = 146, + Mips_D14 = 147, + Mips_D15 = 148, + Mips_DSPOutFlag20 = 149, + Mips_DSPOutFlag21 = 150, + Mips_DSPOutFlag22 = 151, + Mips_DSPOutFlag23 = 152, + Mips_F0 = 153, + Mips_F1 = 154, + Mips_F2 = 155, + Mips_F3 = 156, + Mips_F4 = 157, + Mips_F5 = 158, + Mips_F6 = 159, + Mips_F7 = 160, + Mips_F8 = 161, + Mips_F9 = 162, + Mips_F10 = 163, + Mips_F11 = 164, + Mips_F12 = 165, + Mips_F13 = 166, + Mips_F14 = 167, + Mips_F15 = 168, + Mips_F16 = 169, + Mips_F17 = 170, + Mips_F18 = 171, + Mips_F19 = 172, + Mips_F20 = 173, + Mips_F21 = 174, + Mips_F22 = 175, + Mips_F23 = 176, + Mips_F24 = 177, + Mips_F25 = 178, + Mips_F26 = 179, + Mips_F27 = 180, + Mips_F28 = 181, + Mips_F29 = 182, + Mips_F30 = 183, + Mips_F31 = 184, + Mips_FCC0 = 185, + Mips_FCC1 = 186, + Mips_FCC2 = 187, + Mips_FCC3 = 188, + Mips_FCC4 = 189, + Mips_FCC5 = 190, + Mips_FCC6 = 191, + Mips_FCC7 = 192, + Mips_FCR0 = 193, + Mips_FCR1 = 194, + Mips_FCR2 = 195, + Mips_FCR3 = 196, + Mips_FCR4 = 197, + Mips_FCR5 = 198, + Mips_FCR6 = 199, + Mips_FCR7 = 200, + Mips_FCR8 = 201, + Mips_FCR9 = 202, + Mips_FCR10 = 203, + Mips_FCR11 = 204, + Mips_FCR12 = 205, + Mips_FCR13 = 206, + Mips_FCR14 = 207, + Mips_FCR15 = 208, + Mips_FCR16 = 209, + Mips_FCR17 = 210, + Mips_FCR18 = 211, + Mips_FCR19 = 212, + Mips_FCR20 = 213, + Mips_FCR21 = 214, + Mips_FCR22 = 215, + Mips_FCR23 = 216, + Mips_FCR24 = 217, + Mips_FCR25 = 218, + Mips_FCR26 = 219, + Mips_FCR27 = 220, + Mips_FCR28 = 221, + Mips_FCR29 = 222, + Mips_FCR30 = 223, + Mips_FCR31 = 224, + Mips_FP_64 = 225, + Mips_F_HI0 = 226, + Mips_F_HI1 = 227, + Mips_F_HI2 = 228, + Mips_F_HI3 = 229, + Mips_F_HI4 = 230, + Mips_F_HI5 = 231, + Mips_F_HI6 = 232, + Mips_F_HI7 = 233, + Mips_F_HI8 = 234, + Mips_F_HI9 = 235, + Mips_F_HI10 = 236, + Mips_F_HI11 = 237, + Mips_F_HI12 = 238, + Mips_F_HI13 = 239, + Mips_F_HI14 = 240, + Mips_F_HI15 = 241, + Mips_F_HI16 = 242, + Mips_F_HI17 = 243, + Mips_F_HI18 = 244, + Mips_F_HI19 = 245, + Mips_F_HI20 = 246, + Mips_F_HI21 = 247, + Mips_F_HI22 = 248, + Mips_F_HI23 = 249, + Mips_F_HI24 = 250, + Mips_F_HI25 = 251, + Mips_F_HI26 = 252, + Mips_F_HI27 = 253, + Mips_F_HI28 = 254, + Mips_F_HI29 = 255, + Mips_F_HI30 = 256, + Mips_F_HI31 = 257, + Mips_GP_64 = 258, + Mips_HI0 = 259, + Mips_HI1 = 260, + Mips_HI2 = 261, + Mips_HI3 = 262, + Mips_HWR0 = 263, + Mips_HWR1 = 264, + Mips_HWR2 = 265, + Mips_HWR3 = 266, + Mips_HWR4 = 267, + Mips_HWR5 = 268, + Mips_HWR6 = 269, + Mips_HWR7 = 270, + Mips_HWR8 = 271, + Mips_HWR9 = 272, + Mips_HWR10 = 273, + Mips_HWR11 = 274, + Mips_HWR12 = 275, + Mips_HWR13 = 276, + Mips_HWR14 = 277, + Mips_HWR15 = 278, + Mips_HWR16 = 279, + Mips_HWR17 = 280, + Mips_HWR18 = 281, + Mips_HWR19 = 282, + Mips_HWR20 = 283, + Mips_HWR21 = 284, + Mips_HWR22 = 285, + Mips_HWR23 = 286, + Mips_HWR24 = 287, + Mips_HWR25 = 288, + Mips_HWR26 = 289, + Mips_HWR27 = 290, + Mips_HWR28 = 291, + Mips_HWR29 = 292, + Mips_HWR30 = 293, + Mips_HWR31 = 294, + Mips_K0 = 295, + Mips_K1 = 296, + Mips_LO0 = 297, + Mips_LO1 = 298, + Mips_LO2 = 299, + Mips_LO3 = 300, + Mips_MPL0 = 301, + Mips_MPL1 = 302, + Mips_MPL2 = 303, + Mips_MSA8 = 304, + Mips_MSA9 = 305, + Mips_MSA10 = 306, + Mips_MSA11 = 307, + Mips_MSA12 = 308, + Mips_MSA13 = 309, + Mips_MSA14 = 310, + Mips_MSA15 = 311, + Mips_MSA16 = 312, + Mips_MSA17 = 313, + Mips_MSA18 = 314, + Mips_MSA19 = 315, + Mips_MSA20 = 316, + Mips_MSA21 = 317, + Mips_MSA22 = 318, + Mips_MSA23 = 319, + Mips_MSA24 = 320, + Mips_MSA25 = 321, + Mips_MSA26 = 322, + Mips_MSA27 = 323, + Mips_MSA28 = 324, + Mips_MSA29 = 325, + Mips_MSA30 = 326, + Mips_MSA31 = 327, + Mips_P0 = 328, + Mips_P1 = 329, + Mips_P2 = 330, + Mips_RA_64 = 331, + Mips_S0 = 332, + Mips_S1 = 333, + Mips_S2 = 334, + Mips_S3 = 335, + Mips_S4 = 336, + Mips_S5 = 337, + Mips_S6 = 338, + Mips_S7 = 339, + Mips_SP_64 = 340, + Mips_T0 = 341, + Mips_T1 = 342, + Mips_T2 = 343, + Mips_T3 = 344, + Mips_T4 = 345, + Mips_T5 = 346, + Mips_T6 = 347, + Mips_T7 = 348, + Mips_T8 = 349, + Mips_T9 = 350, + Mips_V0 = 351, + Mips_V1 = 352, + Mips_W0 = 353, + Mips_W1 = 354, + Mips_W2 = 355, + Mips_W3 = 356, + Mips_W4 = 357, + Mips_W5 = 358, + Mips_W6 = 359, + Mips_W7 = 360, + Mips_W8 = 361, + Mips_W9 = 362, + Mips_W10 = 363, + Mips_W11 = 364, + Mips_W12 = 365, + Mips_W13 = 366, + Mips_W14 = 367, + Mips_W15 = 368, + Mips_W16 = 369, + Mips_W17 = 370, + Mips_W18 = 371, + Mips_W19 = 372, + Mips_W20 = 373, + Mips_W21 = 374, + Mips_W22 = 375, + Mips_W23 = 376, + Mips_W24 = 377, + Mips_W25 = 378, + Mips_W26 = 379, + Mips_W27 = 380, + Mips_W28 = 381, + Mips_W29 = 382, + Mips_W30 = 383, + Mips_W31 = 384, + Mips_ZERO_64 = 385, + Mips_A0_NM = 386, + Mips_A1_NM = 387, + Mips_A2_NM = 388, + Mips_A3_NM = 389, + Mips_A4_NM = 390, + Mips_A5_NM = 391, + Mips_A6_NM = 392, + Mips_A7_NM = 393, + Mips_COP0Sel_BADINST = 394, + Mips_COP0Sel_BADINSTRP = 395, + Mips_COP0Sel_BADINSTRX = 396, + Mips_COP0Sel_BADVADDR = 397, + Mips_COP0Sel_BEVVA = 398, + Mips_COP0Sel_CACHEERR = 399, + Mips_COP0Sel_CAUSE = 400, + Mips_COP0Sel_CDMMBASE = 401, + Mips_COP0Sel_CMGCRBASE = 402, + Mips_COP0Sel_COMPARE = 403, + Mips_COP0Sel_CONFIG = 404, + Mips_COP0Sel_CONTEXT = 405, + Mips_COP0Sel_CONTEXTCONFIG = 406, + Mips_COP0Sel_COUNT = 407, + Mips_COP0Sel_DDATAHI = 408, + Mips_COP0Sel_DDATALO = 409, + Mips_COP0Sel_DEBUG = 410, + Mips_COP0Sel_DEBUGCONTEXTID = 411, + Mips_COP0Sel_DEPC = 412, + Mips_COP0Sel_DESAVE = 413, + Mips_COP0Sel_DTAGHI = 414, + Mips_COP0Sel_DTAGLO = 415, + Mips_COP0Sel_EBASE = 416, + Mips_COP0Sel_ENTRYHI = 417, + Mips_COP0Sel_EPC = 418, + Mips_COP0Sel_ERRCTL = 419, + Mips_COP0Sel_ERROREPC = 420, + Mips_COP0Sel_GLOBALNUMBER = 421, + Mips_COP0Sel_GTOFFSET = 422, + Mips_COP0Sel_HWRENA = 423, + Mips_COP0Sel_IDATAHI = 424, + Mips_COP0Sel_IDATALO = 425, + Mips_COP0Sel_INDEX = 426, + Mips_COP0Sel_INTCTL = 427, + Mips_COP0Sel_ITAGHI = 428, + Mips_COP0Sel_ITAGLO = 429, + Mips_COP0Sel_LLADDR = 430, + Mips_COP0Sel_MAAR = 431, + Mips_COP0Sel_MAARI = 432, + Mips_COP0Sel_MEMORYMAPID = 433, + Mips_COP0Sel_MVPCONTROL = 434, + Mips_COP0Sel_NESTEDEPC = 435, + Mips_COP0Sel_NESTEDEXC = 436, + Mips_COP0Sel_PAGEGRAIN = 437, + Mips_COP0Sel_PAGEMASK = 438, + Mips_COP0Sel_PRID = 439, + Mips_COP0Sel_PWBASE = 440, + Mips_COP0Sel_PWCTL = 441, + Mips_COP0Sel_PWFIELD = 442, + Mips_COP0Sel_PWSIZE = 443, + Mips_COP0Sel_RANDOM = 444, + Mips_COP0Sel_SRSCTL = 445, + Mips_COP0Sel_SRSMAP = 446, + Mips_COP0Sel_STATUS = 447, + Mips_COP0Sel_TCBIND = 448, + Mips_COP0Sel_TCCONTEXT = 449, + Mips_COP0Sel_TCHALT = 450, + Mips_COP0Sel_TCOPT = 451, + Mips_COP0Sel_TCRESTART = 452, + Mips_COP0Sel_TCSCHEDULE = 453, + Mips_COP0Sel_TCSCHEFBACK = 454, + Mips_COP0Sel_TCSTATUS = 455, + Mips_COP0Sel_TRACECONTROL = 456, + Mips_COP0Sel_TRACEDBPC = 457, + Mips_COP0Sel_TRACEIBPC = 458, + Mips_COP0Sel_USERLOCAL = 459, + Mips_COP0Sel_VIEW_IPL = 460, + Mips_COP0Sel_VIEW_RIPL = 461, + Mips_COP0Sel_VPCONTROL = 462, + Mips_COP0Sel_VPECONTROL = 463, + Mips_COP0Sel_VPEOPT = 464, + Mips_COP0Sel_VPESCHEDULE = 465, + Mips_COP0Sel_VPESCHEFBACK = 466, + Mips_COP0Sel_WIRED = 467, + Mips_COP0Sel_XCONTEXT = 468, + Mips_COP0Sel_XCONTEXTCONFIG = 469, + Mips_COP0Sel_YQMASK = 470, + Mips_K0_NM = 471, + Mips_K1_NM = 472, + Mips_S0_NM = 473, + Mips_S1_NM = 474, + Mips_S2_NM = 475, + Mips_S3_NM = 476, + Mips_S4_NM = 477, + Mips_S5_NM = 478, + Mips_S6_NM = 479, + Mips_S7_NM = 480, + Mips_T0_NM = 481, + Mips_T1_NM = 482, + Mips_T2_NM = 483, + Mips_T3_NM = 484, + Mips_T4_NM = 485, + Mips_T5_NM = 486, + Mips_T8_NM = 487, + Mips_T9_NM = 488, + Mips_A0_64 = 489, + Mips_A1_64 = 490, + Mips_A2_64 = 491, + Mips_A3_64 = 492, + Mips_AC0_64 = 493, + Mips_COP0Sel_CONFIG1 = 494, + Mips_COP0Sel_CONFIG2 = 495, + Mips_COP0Sel_CONFIG3 = 496, + Mips_COP0Sel_CONFIG4 = 497, + Mips_COP0Sel_CONFIG5 = 498, + Mips_COP0Sel_DEBUG2 = 499, + Mips_COP0Sel_ENTRYLO0 = 500, + Mips_COP0Sel_ENTRYLO1 = 501, + Mips_COP0Sel_GUESTCTL0 = 502, + Mips_COP0Sel_GUESTCTL1 = 503, + Mips_COP0Sel_GUESTCTL2 = 504, + Mips_COP0Sel_GUESTCTL3 = 505, + Mips_COP0Sel_KSCRATCH1 = 506, + Mips_COP0Sel_KSCRATCH2 = 507, + Mips_COP0Sel_KSCRATCH3 = 508, + Mips_COP0Sel_KSCRATCH4 = 509, + Mips_COP0Sel_KSCRATCH5 = 510, + Mips_COP0Sel_KSCRATCH6 = 511, + Mips_COP0Sel_MVPCONF0 = 512, + Mips_COP0Sel_MVPCONF1 = 513, + Mips_COP0Sel_PERFCNT0 = 514, + Mips_COP0Sel_PERFCNT1 = 515, + Mips_COP0Sel_PERFCNT2 = 516, + Mips_COP0Sel_PERFCNT3 = 517, + Mips_COP0Sel_PERFCNT4 = 518, + Mips_COP0Sel_PERFCNT5 = 519, + Mips_COP0Sel_PERFCNT6 = 520, + Mips_COP0Sel_PERFCNT7 = 521, + Mips_COP0Sel_PERFCTL0 = 522, + Mips_COP0Sel_PERFCTL1 = 523, + Mips_COP0Sel_PERFCTL2 = 524, + Mips_COP0Sel_PERFCTL3 = 525, + Mips_COP0Sel_PERFCTL4 = 526, + Mips_COP0Sel_PERFCTL5 = 527, + Mips_COP0Sel_PERFCTL6 = 528, + Mips_COP0Sel_PERFCTL7 = 529, + Mips_COP0Sel_SEGCTL0 = 530, + Mips_COP0Sel_SEGCTL1 = 531, + Mips_COP0Sel_SEGCTL2 = 532, + Mips_COP0Sel_SRSCONF0 = 533, + Mips_COP0Sel_SRSCONF1 = 534, + Mips_COP0Sel_SRSCONF2 = 535, + Mips_COP0Sel_SRSCONF3 = 536, + Mips_COP0Sel_SRSCONF4 = 537, + Mips_COP0Sel_SRSMAP2 = 538, + Mips_COP0Sel_TRACECONTROL2 = 539, + Mips_COP0Sel_TRACECONTROL3 = 540, + Mips_COP0Sel_USERTRACEDATA1 = 541, + Mips_COP0Sel_USERTRACEDATA2 = 542, + Mips_COP0Sel_VPECONF0 = 543, + Mips_COP0Sel_VPECONF1 = 544, + Mips_COP0Sel_WATCHHI0 = 545, + Mips_COP0Sel_WATCHHI1 = 546, + Mips_COP0Sel_WATCHHI2 = 547, + Mips_COP0Sel_WATCHHI3 = 548, + Mips_COP0Sel_WATCHHI4 = 549, + Mips_COP0Sel_WATCHHI5 = 550, + Mips_COP0Sel_WATCHHI6 = 551, + Mips_COP0Sel_WATCHHI7 = 552, + Mips_COP0Sel_WATCHHI8 = 553, + Mips_COP0Sel_WATCHHI9 = 554, + Mips_COP0Sel_WATCHHI10 = 555, + Mips_COP0Sel_WATCHHI11 = 556, + Mips_COP0Sel_WATCHHI12 = 557, + Mips_COP0Sel_WATCHHI13 = 558, + Mips_COP0Sel_WATCHHI14 = 559, + Mips_COP0Sel_WATCHHI15 = 560, + Mips_COP0Sel_WATCHLO0 = 561, + Mips_COP0Sel_WATCHLO1 = 562, + Mips_COP0Sel_WATCHLO2 = 563, + Mips_COP0Sel_WATCHLO3 = 564, + Mips_COP0Sel_WATCHLO4 = 565, + Mips_COP0Sel_WATCHLO5 = 566, + Mips_COP0Sel_WATCHLO6 = 567, + Mips_COP0Sel_WATCHLO7 = 568, + Mips_COP0Sel_WATCHLO8 = 569, + Mips_COP0Sel_WATCHLO9 = 570, + Mips_COP0Sel_WATCHLO10 = 571, + Mips_COP0Sel_WATCHLO11 = 572, + Mips_COP0Sel_WATCHLO12 = 573, + Mips_COP0Sel_WATCHLO13 = 574, + Mips_COP0Sel_WATCHLO14 = 575, + Mips_COP0Sel_WATCHLO15 = 576, + Mips_D0_64 = 577, + Mips_D1_64 = 578, + Mips_D2_64 = 579, + Mips_D3_64 = 580, + Mips_D4_64 = 581, + Mips_D5_64 = 582, + Mips_D6_64 = 583, + Mips_D7_64 = 584, + Mips_D8_64 = 585, + Mips_D9_64 = 586, + Mips_D10_64 = 587, + Mips_D11_64 = 588, + Mips_D12_64 = 589, + Mips_D13_64 = 590, + Mips_D14_64 = 591, + Mips_D15_64 = 592, + Mips_D16_64 = 593, + Mips_D17_64 = 594, + Mips_D18_64 = 595, + Mips_D19_64 = 596, + Mips_D20_64 = 597, + Mips_D21_64 = 598, + Mips_D22_64 = 599, + Mips_D23_64 = 600, + Mips_D24_64 = 601, + Mips_D25_64 = 602, + Mips_D26_64 = 603, + Mips_D27_64 = 604, + Mips_D28_64 = 605, + Mips_D29_64 = 606, + Mips_D30_64 = 607, + Mips_D31_64 = 608, + Mips_DSPOutFlag16_19 = 609, + Mips_HI0_64 = 610, + Mips_K0_64 = 611, + Mips_K1_64 = 612, + Mips_LO0_64 = 613, + Mips_S0_64 = 614, + Mips_S1_64 = 615, + Mips_S2_64 = 616, + Mips_S3_64 = 617, + Mips_S4_64 = 618, + Mips_S5_64 = 619, + Mips_S6_64 = 620, + Mips_S7_64 = 621, + Mips_T0_64 = 622, + Mips_T1_64 = 623, + Mips_T2_64 = 624, + Mips_T3_64 = 625, + Mips_T4_64 = 626, + Mips_T5_64 = 627, + Mips_T6_64 = 628, + Mips_T7_64 = 629, + Mips_T8_64 = 630, + Mips_T9_64 = 631, + Mips_V0_64 = 632, + Mips_V1_64 = 633, + Mips_COP0Sel_GUESTCTL0EXT = 634, + NUM_TARGET_REGS // 635 }; // Register classes + enum { - Mips_OddSPRegClassID = 0, - Mips_CCRRegClassID = 1, - Mips_COP2RegClassID = 2, - Mips_COP3RegClassID = 3, - Mips_DSPRRegClassID = 4, - Mips_FGR32RegClassID = 5, - Mips_FGRCCRegClassID = 6, - Mips_FGRH32RegClassID = 7, - Mips_GPR32RegClassID = 8, - Mips_HWRegsRegClassID = 9, - Mips_OddSP_with_sub_hiRegClassID = 10, - Mips_FGR32_and_OddSPRegClassID = 11, - Mips_FGRH32_and_OddSPRegClassID = 12, - Mips_OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID = 13, - Mips_CPU16RegsPlusSPRegClassID = 14, - Mips_CCRegClassID = 15, - Mips_CPU16RegsRegClassID = 16, - Mips_FCCRegClassID = 17, - Mips_GPRMM16RegClassID = 18, - Mips_GPRMM16MovePRegClassID = 19, - Mips_GPRMM16ZeroRegClassID = 20, - Mips_MSACtrlRegClassID = 21, - Mips_OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID = 22, - Mips_CPU16Regs_and_GPRMM16ZeroRegClassID = 23, - Mips_CPU16Regs_and_GPRMM16MovePRegClassID = 24, - Mips_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 25, - Mips_HI32DSPRegClassID = 26, - Mips_LO32DSPRegClassID = 27, - Mips_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 28, - Mips_CPURARegRegClassID = 29, - Mips_CPUSPRegRegClassID = 30, - Mips_DSPCCRegClassID = 31, - Mips_HI32RegClassID = 32, - Mips_LO32RegClassID = 33, - Mips_FGR64RegClassID = 34, - Mips_GPR64RegClassID = 35, - Mips_AFGR64RegClassID = 36, - Mips_FGR64_and_OddSPRegClassID = 37, - Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 38, - Mips_AFGR64_and_OddSPRegClassID = 39, - Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID = 40, - Mips_GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 41, - Mips_GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 42, - Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 43, - Mips_ACC64DSPRegClassID = 44, - Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 45, - Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 46, - Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 47, - Mips_OCTEON_MPLRegClassID = 48, - Mips_OCTEON_PRegClassID = 49, - Mips_ACC64RegClassID = 50, - Mips_GPR64_with_sub_32_in_CPURARegRegClassID = 51, - Mips_GPR64_with_sub_32_in_CPUSPRegRegClassID = 52, - Mips_HI64RegClassID = 53, - Mips_LO64RegClassID = 54, - Mips_MSA128BRegClassID = 55, - Mips_MSA128DRegClassID = 56, - Mips_MSA128HRegClassID = 57, - Mips_MSA128WRegClassID = 58, - Mips_MSA128B_with_sub_64_in_OddSPRegClassID = 59, - Mips_MSA128WEvensRegClassID = 60, - Mips_ACC128RegClassID = 61, + Mips_MSA128F16RegClassID = 0, + Mips_COP0SelRegClassID = 1, + Mips_CCRRegClassID = 2, + Mips_COP0RegClassID = 3, + Mips_COP2RegClassID = 4, + Mips_COP3RegClassID = 5, + Mips_DSPRRegClassID = 6, + Mips_FGR32RegClassID = 7, + Mips_FGRCCRegClassID = 8, + Mips_GPR32RegClassID = 9, + Mips_GPRNM32RegClassID = 10, + Mips_HWRegsRegClassID = 11, + Mips_MSACtrlRegClassID = 12, + Mips_GPR32NONZERORegClassID = 13, + Mips_GPRNM32NZRegClassID = 14, + Mips_GPRNM32_TAILRegClassID = 15, + Mips_GPRNM4RegClassID = 16, + Mips_GPRNM4ZRegClassID = 17, + Mips_GPRNM4_and_GPRNM4ZRegClassID = 18, + Mips_CPU16RegsPlusSPRegClassID = 19, + Mips_CPU16RegsRegClassID = 20, + Mips_FCCRegClassID = 21, + Mips_GPRMM16RegClassID = 22, + Mips_GPRMM16MovePRegClassID = 23, + Mips_GPRMM16ZeroRegClassID = 24, + Mips_GPRNM3RegClassID = 25, + Mips_GPRNM3ZRegClassID = 26, + Mips_GPRNM4_and_GPRNM32_TAILRegClassID = 27, + Mips_CPU16Regs_and_GPRMM16ZeroRegClassID = 28, + Mips_GPR32NONZERO_and_GPRMM16MovePRegClassID = 29, + Mips_GPRNM3_and_GPRNM3ZRegClassID = 30, + Mips_GPRNM4Z_and_GPRNM32_TAILRegClassID = 31, + Mips_GPRMM16MovePPairSecondRegClassID = 32, + Mips_CPU16Regs_and_GPRMM16MovePRegClassID = 33, + Mips_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 34, + Mips_GPRNM2R1RegClassID = 35, + Mips_GPRNM2R2RegClassID = 36, + Mips_HI32DSPRegClassID = 37, + Mips_LO32DSPRegClassID = 38, + Mips_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 39, + Mips_GPRMM16MovePPairFirstRegClassID = 40, + Mips_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 41, + Mips_GPRNM2R1_and_GPRNM2R2RegClassID = 42, + Mips_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 43, + Mips_GPRNM1R1RegClassID = 44, + Mips_CPURARegRegClassID = 45, + Mips_CPUSPRegRegClassID = 46, + Mips_DSPCCRegClassID = 47, + Mips_GP32RegClassID = 48, + Mips_GPR32ZERORegClassID = 49, + Mips_GPRNM1R1_and_GPRNM2R2RegClassID = 50, + Mips_GPRNMGPRegClassID = 51, + Mips_GPRNMRARegClassID = 52, + Mips_GPRNMSPRegClassID = 53, + Mips_HI32RegClassID = 54, + Mips_LO32RegClassID = 55, + Mips_SP32RegClassID = 56, + Mips_FGR64RegClassID = 57, + Mips_GPR64RegClassID = 58, + Mips_GPR64_with_sub_32_in_GPR32NONZERORegClassID = 59, + Mips_AFGR64RegClassID = 60, + Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 61, + Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID = 62, + Mips_GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 63, + Mips_GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 64, + Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 65, + Mips_GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID = 66, + Mips_GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID = 67, + Mips_ACC64DSPRegClassID = 68, + Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 69, + Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 70, + Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 71, + Mips_GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID = 72, + Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 73, + Mips_OCTEON_MPLRegClassID = 74, + Mips_OCTEON_PRegClassID = 75, + Mips_GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 76, + Mips_ACC64RegClassID = 77, + Mips_GP64RegClassID = 78, + Mips_GPR64_with_sub_32_in_CPURARegRegClassID = 79, + Mips_GPR64_with_sub_32_in_GPR32ZERORegClassID = 80, + Mips_HI64RegClassID = 81, + Mips_LO64RegClassID = 82, + Mips_SP64RegClassID = 83, + Mips_MSA128BRegClassID = 84, + Mips_MSA128DRegClassID = 85, + Mips_MSA128HRegClassID = 86, + Mips_MSA128WRegClassID = 87, + Mips_MSA128WEvensRegClassID = 88, + Mips_ACC128RegClassID = 89, + }; +// Subregister indices + +enum { + Mips_NoSubRegister, + Mips_sub_32, // 1 + Mips_sub_64, // 2 + Mips_sub_dsp16_19, // 3 + Mips_sub_dsp20, // 4 + Mips_sub_dsp21, // 5 + Mips_sub_dsp22, // 6 + Mips_sub_dsp23, // 7 + Mips_sub_hi, // 8 + Mips_sub_lo, // 9 + Mips_sub_hi_then_sub_32, // 10 + Mips_sub_32_sub_hi_then_sub_32, // 11 + Mips_NUM_TARGET_SUBREGS +}; #endif // GET_REGINFO_ENUM -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|*MC Register Information *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2019 */ +/* Do not edit. */ +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC static const MCPhysReg MipsRegDiffLists[] = { - /* 0 */ 0, 0, - /* 2 */ 4, 1, 1, 1, 1, 0, - /* 8 */ 364, -250, 1, 1, 1, 0, - /* 14 */ 20, 1, 0, - /* 17 */ 21, 1, 0, - /* 20 */ 22, 1, 0, - /* 23 */ 23, 1, 0, - /* 26 */ 24, 1, 0, - /* 29 */ 25, 1, 0, - /* 32 */ 26, 1, 0, - /* 35 */ 27, 1, 0, - /* 38 */ 28, 1, 0, - /* 41 */ 29, 1, 0, - /* 44 */ 30, 1, 0, - /* 47 */ 31, 1, 0, - /* 50 */ 32, 1, 0, - /* 53 */ 33, 1, 0, - /* 56 */ 34, 1, 0, - /* 59 */ 35, 1, 0, - /* 62 */ -97, 1, 0, - /* 65 */ -23, 1, 0, - /* 68 */ 3, 0, - /* 70 */ 4, 0, - /* 72 */ 6, 0, - /* 74 */ 11, 0, - /* 76 */ 12, 0, - /* 78 */ 22, 0, - /* 80 */ 23, 0, - /* 82 */ 29, 0, - /* 84 */ 30, 0, - /* 86 */ -228, 72, 0, - /* 89 */ -190, 72, 0, - /* 92 */ 38, -214, 73, 0, - /* 96 */ 95, 0, - /* 98 */ 96, 0, - /* 100 */ 106, 0, - /* 102 */ 187, 0, - /* 104 */ 219, 0, - /* 106 */ 258, 0, - /* 108 */ 266, 0, - /* 110 */ 310, 0, - /* 112 */ -505, 0, - /* 114 */ -428, 0, - /* 116 */ -364, 0, - /* 118 */ -310, 0, - /* 120 */ -307, 0, - /* 122 */ -266, 0, - /* 124 */ -258, 0, - /* 126 */ -241, 0, - /* 128 */ -219, 0, - /* 130 */ 37, -106, 103, -141, -203, 0, - /* 136 */ -187, 0, - /* 138 */ -141, 0, - /* 140 */ -126, 0, - /* 142 */ -121, 0, - /* 144 */ -117, 0, - /* 146 */ -116, 0, - /* 148 */ -115, 0, - /* 150 */ -114, 0, - /* 152 */ -106, 0, - /* 154 */ -96, 0, - /* 156 */ -95, 0, - /* 158 */ 141, -38, 0, - /* 161 */ -20, 234, -38, 0, - /* 165 */ -21, 235, -38, 0, - /* 169 */ -22, 236, -38, 0, - /* 173 */ -23, 237, -38, 0, - /* 177 */ -24, 238, -38, 0, - /* 181 */ -25, 239, -38, 0, - /* 185 */ -26, 240, -38, 0, - /* 189 */ -27, 241, -38, 0, - /* 193 */ -28, 242, -38, 0, - /* 197 */ -29, 243, -38, 0, - /* 201 */ -30, 244, -38, 0, - /* 205 */ -31, 245, -38, 0, - /* 209 */ -32, 246, -38, 0, - /* 213 */ -33, 247, -38, 0, - /* 217 */ -34, 248, -38, 0, - /* 221 */ -35, 249, -38, 0, - /* 225 */ -36, 250, -38, 0, - /* 229 */ -241, 347, -37, 0, - /* 233 */ -203, 344, -34, 0, - /* 237 */ -29, 0, - /* 239 */ -26, 0, - /* 241 */ -25, 0, - /* 243 */ -24, 0, - /* 245 */ -20, 0, - /* 247 */ -15, 0, - /* 249 */ -14, 0, - /* 251 */ -1, 0, + /* 0 */ -603, 0, + /* 2 */ -461, 0, + /* 4 */ -359, 0, + /* 6 */ -351, 0, + /* 8 */ -316, 0, + /* 10 */ -309, 0, + /* 12 */ -282, 0, + /* 14 */ -281, 0, + /* 16 */ -265, 0, + /* 18 */ -247, 0, + /* 20 */ 120, -316, 313, -351, -227, 0, + /* 26 */ 351, -224, 0, + /* 29 */ -20, 444, -224, 0, + /* 33 */ -21, 445, -224, 0, + /* 37 */ -22, 446, -224, 0, + /* 41 */ -23, 447, -224, 0, + /* 45 */ -24, 448, -224, 0, + /* 49 */ -25, 449, -224, 0, + /* 53 */ -26, 450, -224, 0, + /* 57 */ -27, 451, -224, 0, + /* 61 */ -28, 452, -224, 0, + /* 65 */ -29, 453, -224, 0, + /* 69 */ -30, 454, -224, 0, + /* 73 */ -31, 455, -224, 0, + /* 77 */ -32, 456, -224, 0, + /* 81 */ -33, 457, -224, 0, + /* 85 */ -34, 458, -224, 0, + /* 89 */ -35, 459, -224, 0, + /* 93 */ -36, 460, -224, 0, + /* 97 */ -216, 0, + /* 99 */ -146, 0, + /* 101 */ -145, 0, + /* 103 */ -144, 0, + /* 105 */ -143, 0, + /* 107 */ -265, 581, -120, 0, + /* 111 */ -227, 578, -117, 0, + /* 115 */ 265, -38, 0, + /* 118 */ -35, 0, + /* 120 */ 603, -460, 1, 1, 1, 0, + /* 126 */ 1, 1, 1, 1, 0, + /* 131 */ 20, 1, 0, + /* 134 */ 21, 1, 0, + /* 137 */ 22, 1, 0, + /* 140 */ 23, 1, 0, + /* 143 */ 24, 1, 0, + /* 146 */ 25, 1, 0, + /* 149 */ 26, 1, 0, + /* 152 */ 27, 1, 0, + /* 155 */ 28, 1, 0, + /* 158 */ 29, 1, 0, + /* 161 */ 30, 1, 0, + /* 164 */ 31, 1, 0, + /* 167 */ 32, 1, 0, + /* 170 */ 33, 1, 0, + /* 173 */ 34, 1, 0, + /* 176 */ 35, 1, 0, + /* 179 */ 35, 0, + /* 181 */ 72, 0, + /* 183 */ 224, -424, 73, 0, + /* 187 */ 216, 0, + /* 189 */ 247, 0, + /* 191 */ 281, 0, + /* 193 */ 282, 0, + /* 195 */ 309, 0, + /* 197 */ 316, 0, + /* 199 */ 359, 0, + /* 201 */ 461, 0, }; static const uint16_t MipsSubRegIdxLists[] = { @@ -595,1085 +849,2274 @@ static const uint16_t MipsSubRegIdxLists[] = { }; static const MCRegisterDesc MipsRegDesc[] = { // Descriptors - { 6, 0, 0, 0, 0, 0 }, - { 2007, 1, 82, 1, 4017, 0 }, - { 2010, 1, 1, 1, 4017, 0 }, - { 2102, 1, 1, 1, 4017, 0 }, - { 1973, 1, 1, 1, 4017, 0 }, - { 2027, 8, 1, 2, 32, 4 }, - { 2054, 1, 1, 1, 1089, 0 }, - { 2071, 1, 1, 1, 1089, 0 }, - { 1985, 1, 102, 1, 1089, 0 }, - { 1988, 1, 104, 1, 1089, 0 }, - { 2061, 1, 1, 1, 1089, 0 }, - { 2000, 1, 1, 1, 1089, 0 }, - { 1994, 1, 1, 1, 1089, 0 }, - { 2038, 1, 1, 1, 1089, 0 }, - { 2092, 1, 1, 1, 1089, 0 }, - { 2081, 1, 1, 1, 1089, 0 }, - { 2019, 1, 1, 1, 1089, 0 }, - { 2045, 1, 1, 1, 1089, 0 }, - { 1970, 1, 1, 1, 1089, 0 }, - { 1967, 1, 106, 1, 1089, 0 }, - { 1991, 1, 108, 1, 1089, 0 }, - { 1980, 1, 110, 1, 1089, 0 }, - { 152, 1, 110, 1, 1089, 0 }, - { 365, 1, 110, 1, 1089, 0 }, - { 537, 1, 110, 1, 1089, 0 }, - { 703, 1, 110, 1, 1089, 0 }, - { 155, 190, 110, 9, 1042, 10 }, - { 368, 190, 1, 9, 1042, 10 }, - { 540, 190, 1, 9, 1042, 10 }, - { 706, 190, 1, 9, 1042, 10 }, - { 1271, 237, 1, 0, 0, 2 }, - { 160, 1, 1, 1, 1153, 0 }, - { 373, 1, 1, 1, 1153, 0 }, - { 545, 1, 1, 1, 1153, 0 }, - { 711, 1, 1, 1, 1153, 0 }, - { 1278, 1, 1, 1, 1153, 0 }, - { 1412, 1, 1, 1, 1153, 0 }, - { 1542, 1, 1, 1, 1153, 0 }, - { 1672, 1, 1, 1, 1153, 0 }, - { 70, 1, 1, 1, 1153, 0 }, - { 283, 1, 1, 1, 1153, 0 }, - { 496, 1, 1, 1, 1153, 0 }, - { 662, 1, 1, 1, 1153, 0 }, - { 820, 1, 1, 1, 1153, 0 }, - { 1383, 1, 1, 1, 1153, 0 }, - { 1513, 1, 1, 1, 1153, 0 }, - { 1643, 1, 1, 1, 1153, 0 }, - { 1773, 1, 1, 1, 1153, 0 }, - { 1911, 1, 1, 1, 1153, 0 }, - { 130, 1, 1, 1, 1153, 0 }, - { 343, 1, 1, 1, 1153, 0 }, - { 531, 1, 1, 1, 1153, 0 }, - { 697, 1, 1, 1, 1153, 0 }, - { 842, 1, 1, 1, 1153, 0 }, - { 1405, 1, 1, 1, 1153, 0 }, - { 1535, 1, 1, 1, 1153, 0 }, - { 1665, 1, 1, 1, 1153, 0 }, - { 1795, 1, 1, 1, 1153, 0 }, - { 1933, 1, 1, 1, 1153, 0 }, - { 0, 1, 1, 1, 1153, 0 }, - { 213, 1, 1, 1, 1153, 0 }, - { 426, 1, 1, 1, 1153, 0 }, - { 592, 1, 1, 1, 1153, 0 }, - { 750, 1, 1, 1, 1153, 0 }, - { 1313, 1, 1, 1, 1153, 0 }, - { 1447, 1, 1, 1, 1153, 0 }, - { 1577, 1, 1, 1, 1153, 0 }, - { 1707, 1, 1, 1, 1153, 0 }, - { 1829, 1, 1, 1, 1153, 0 }, - { 45, 1, 1, 1, 1153, 0 }, - { 258, 1, 1, 1, 1153, 0 }, - { 471, 1, 1, 1, 1153, 0 }, - { 637, 1, 1, 1, 1153, 0 }, - { 795, 1, 1, 1, 1153, 0 }, - { 1358, 1, 1, 1, 1153, 0 }, - { 1488, 1, 1, 1, 1153, 0 }, - { 1618, 1, 1, 1, 1153, 0 }, - { 1748, 1, 1, 1, 1153, 0 }, - { 1886, 1, 1, 1, 1153, 0 }, - { 105, 1, 1, 1, 1153, 0 }, - { 318, 1, 1, 1, 1153, 0 }, - { 7, 1, 1, 1, 1153, 0 }, - { 220, 1, 1, 1, 1153, 0 }, - { 433, 1, 1, 1, 1153, 0 }, - { 599, 1, 1, 1, 1153, 0 }, - { 757, 1, 1, 1, 1153, 0 }, - { 1320, 1, 1, 1, 1153, 0 }, - { 1454, 1, 1, 1, 1153, 0 }, - { 1584, 1, 1, 1, 1153, 0 }, - { 1714, 1, 1, 1, 1153, 0 }, - { 1836, 1, 1, 1, 1153, 0 }, - { 52, 1, 1, 1, 1153, 0 }, - { 265, 1, 1, 1, 1153, 0 }, - { 478, 1, 1, 1, 1153, 0 }, - { 644, 1, 1, 1, 1153, 0 }, - { 802, 1, 1, 1, 1153, 0 }, - { 1365, 1, 1, 1, 1153, 0 }, - { 1495, 1, 1, 1, 1153, 0 }, - { 1625, 1, 1, 1, 1153, 0 }, - { 1755, 1, 1, 1, 1153, 0 }, - { 1893, 1, 1, 1, 1153, 0 }, - { 112, 1, 1, 1, 1153, 0 }, - { 325, 1, 1, 1, 1153, 0 }, - { 164, 14, 1, 9, 994, 10 }, - { 377, 17, 1, 9, 994, 10 }, - { 549, 20, 1, 9, 994, 10 }, - { 715, 23, 1, 9, 994, 10 }, - { 1282, 26, 1, 9, 994, 10 }, - { 1416, 29, 1, 9, 994, 10 }, - { 1546, 32, 1, 9, 994, 10 }, - { 1676, 35, 1, 9, 994, 10 }, - { 1801, 38, 1, 9, 994, 10 }, - { 1939, 41, 1, 9, 994, 10 }, - { 14, 44, 1, 9, 994, 10 }, - { 227, 47, 1, 9, 994, 10 }, - { 440, 50, 1, 9, 994, 10 }, - { 606, 53, 1, 9, 994, 10 }, - { 764, 56, 1, 9, 994, 10 }, - { 1327, 59, 1, 9, 994, 10 }, - { 92, 1, 150, 1, 2401, 0 }, - { 305, 1, 148, 1, 2401, 0 }, - { 518, 1, 146, 1, 2401, 0 }, - { 684, 1, 144, 1, 2401, 0 }, - { 167, 1, 161, 1, 3985, 0 }, - { 380, 1, 165, 1, 3985, 0 }, - { 552, 1, 165, 1, 3985, 0 }, - { 718, 1, 169, 1, 3985, 0 }, - { 1285, 1, 169, 1, 3985, 0 }, - { 1419, 1, 173, 1, 3985, 0 }, - { 1549, 1, 173, 1, 3985, 0 }, - { 1679, 1, 177, 1, 3985, 0 }, - { 1804, 1, 177, 1, 3985, 0 }, - { 1942, 1, 181, 1, 3985, 0 }, - { 18, 1, 181, 1, 3985, 0 }, - { 231, 1, 185, 1, 3985, 0 }, - { 444, 1, 185, 1, 3985, 0 }, - { 610, 1, 189, 1, 3985, 0 }, - { 768, 1, 189, 1, 3985, 0 }, - { 1331, 1, 193, 1, 3985, 0 }, - { 1461, 1, 193, 1, 3985, 0 }, - { 1591, 1, 197, 1, 3985, 0 }, - { 1721, 1, 197, 1, 3985, 0 }, - { 1843, 1, 201, 1, 3985, 0 }, - { 59, 1, 201, 1, 3985, 0 }, - { 272, 1, 205, 1, 3985, 0 }, - { 485, 1, 205, 1, 3985, 0 }, - { 651, 1, 209, 1, 3985, 0 }, - { 809, 1, 209, 1, 3985, 0 }, - { 1372, 1, 213, 1, 3985, 0 }, - { 1502, 1, 213, 1, 3985, 0 }, - { 1632, 1, 217, 1, 3985, 0 }, - { 1762, 1, 217, 1, 3985, 0 }, - { 1900, 1, 221, 1, 3985, 0 }, - { 119, 1, 221, 1, 3985, 0 }, - { 332, 1, 225, 1, 3985, 0 }, - { 159, 1, 1, 1, 3985, 0 }, - { 372, 1, 1, 1, 3985, 0 }, - { 544, 1, 1, 1, 3985, 0 }, - { 710, 1, 1, 1, 3985, 0 }, - { 1277, 1, 1, 1, 3985, 0 }, - { 1411, 1, 1, 1, 3985, 0 }, - { 1541, 1, 1, 1, 3985, 0 }, - { 1671, 1, 1, 1, 3985, 0 }, - { 191, 1, 1, 1, 3985, 0 }, - { 404, 1, 1, 1, 3985, 0 }, - { 573, 1, 1, 1, 3985, 0 }, - { 731, 1, 1, 1, 3985, 0 }, - { 1294, 1, 1, 1, 3985, 0 }, - { 1428, 1, 1, 1, 3985, 0 }, - { 1558, 1, 1, 1, 3985, 0 }, - { 1688, 1, 1, 1, 3985, 0 }, - { 1813, 1, 1, 1, 3985, 0 }, - { 1951, 1, 1, 1, 3985, 0 }, - { 29, 1, 1, 1, 3985, 0 }, - { 242, 1, 1, 1, 3985, 0 }, - { 455, 1, 1, 1, 3985, 0 }, - { 621, 1, 1, 1, 3985, 0 }, - { 779, 1, 1, 1, 3985, 0 }, - { 1342, 1, 1, 1, 3985, 0 }, - { 1472, 1, 1, 1, 3985, 0 }, - { 1602, 1, 1, 1, 3985, 0 }, - { 1732, 1, 1, 1, 3985, 0 }, - { 1854, 1, 1, 1, 3985, 0 }, - { 76, 1, 1, 1, 3985, 0 }, - { 289, 1, 1, 1, 3985, 0 }, - { 502, 1, 1, 1, 3985, 0 }, - { 668, 1, 1, 1, 3985, 0 }, - { 826, 1, 1, 1, 3985, 0 }, - { 1389, 1, 1, 1, 3985, 0 }, - { 1519, 1, 1, 1, 3985, 0 }, - { 1649, 1, 1, 1, 3985, 0 }, - { 1779, 1, 1, 1, 3985, 0 }, - { 1917, 1, 1, 1, 3985, 0 }, - { 136, 1, 1, 1, 3985, 0 }, - { 349, 1, 1, 1, 3985, 0 }, - { 1253, 136, 1, 0, 1184, 2 }, - { 170, 1, 158, 1, 3953, 0 }, - { 383, 1, 158, 1, 3953, 0 }, - { 555, 1, 158, 1, 3953, 0 }, - { 721, 1, 158, 1, 3953, 0 }, - { 1288, 1, 158, 1, 3953, 0 }, - { 1422, 1, 158, 1, 3953, 0 }, - { 1552, 1, 158, 1, 3953, 0 }, - { 1682, 1, 158, 1, 3953, 0 }, - { 1807, 1, 158, 1, 3953, 0 }, - { 1945, 1, 158, 1, 3953, 0 }, - { 22, 1, 158, 1, 3953, 0 }, - { 235, 1, 158, 1, 3953, 0 }, - { 448, 1, 158, 1, 3953, 0 }, - { 614, 1, 158, 1, 3953, 0 }, - { 772, 1, 158, 1, 3953, 0 }, - { 1335, 1, 158, 1, 3953, 0 }, - { 1465, 1, 158, 1, 3953, 0 }, - { 1595, 1, 158, 1, 3953, 0 }, - { 1725, 1, 158, 1, 3953, 0 }, - { 1847, 1, 158, 1, 3953, 0 }, - { 63, 1, 158, 1, 3953, 0 }, - { 276, 1, 158, 1, 3953, 0 }, - { 489, 1, 158, 1, 3953, 0 }, - { 655, 1, 158, 1, 3953, 0 }, - { 813, 1, 158, 1, 3953, 0 }, - { 1376, 1, 158, 1, 3953, 0 }, - { 1506, 1, 158, 1, 3953, 0 }, - { 1636, 1, 158, 1, 3953, 0 }, - { 1766, 1, 158, 1, 3953, 0 }, - { 1904, 1, 158, 1, 3953, 0 }, - { 123, 1, 158, 1, 3953, 0 }, - { 336, 1, 158, 1, 3953, 0 }, - { 1259, 128, 1, 0, 1216, 2 }, - { 172, 1, 233, 1, 1826, 0 }, - { 385, 1, 134, 1, 1826, 0 }, - { 557, 1, 134, 1, 1826, 0 }, - { 723, 1, 134, 1, 1826, 0 }, - { 196, 1, 1, 1, 3921, 0 }, - { 409, 1, 1, 1, 3921, 0 }, - { 578, 1, 1, 1, 3921, 0 }, - { 736, 1, 1, 1, 3921, 0 }, - { 1299, 1, 1, 1, 3921, 0 }, - { 1433, 1, 1, 1, 3921, 0 }, - { 1563, 1, 1, 1, 3921, 0 }, - { 1693, 1, 1, 1, 3921, 0 }, - { 1818, 1, 1, 1, 3921, 0 }, - { 1956, 1, 1, 1, 3921, 0 }, - { 35, 1, 1, 1, 3921, 0 }, - { 248, 1, 1, 1, 3921, 0 }, - { 461, 1, 1, 1, 3921, 0 }, - { 627, 1, 1, 1, 3921, 0 }, - { 785, 1, 1, 1, 3921, 0 }, - { 1348, 1, 1, 1, 3921, 0 }, - { 1478, 1, 1, 1, 3921, 0 }, - { 1608, 1, 1, 1, 3921, 0 }, - { 1738, 1, 1, 1, 3921, 0 }, - { 1860, 1, 1, 1, 3921, 0 }, - { 82, 1, 1, 1, 3921, 0 }, - { 295, 1, 1, 1, 3921, 0 }, - { 508, 1, 1, 1, 3921, 0 }, - { 674, 1, 1, 1, 3921, 0 }, - { 832, 1, 1, 1, 3921, 0 }, - { 1395, 1, 1, 1, 3921, 0 }, - { 1525, 1, 1, 1, 3921, 0 }, - { 1655, 1, 1, 1, 3921, 0 }, - { 1785, 1, 1, 1, 3921, 0 }, - { 1923, 1, 1, 1, 3921, 0 }, - { 142, 1, 1, 1, 3921, 0 }, - { 355, 1, 1, 1, 3921, 0 }, - { 176, 1, 100, 1, 3921, 0 }, - { 389, 1, 100, 1, 3921, 0 }, - { 184, 1, 229, 1, 1794, 0 }, - { 397, 1, 126, 1, 1794, 0 }, - { 566, 1, 126, 1, 1794, 0 }, - { 727, 1, 126, 1, 1794, 0 }, - { 179, 1, 1, 1, 3889, 0 }, - { 392, 1, 1, 1, 3889, 0 }, - { 561, 1, 1, 1, 3889, 0 }, - { 188, 1, 1, 1, 3889, 0 }, - { 401, 1, 1, 1, 3889, 0 }, - { 570, 1, 1, 1, 3889, 0 }, - { 1239, 124, 1, 0, 1248, 2 }, - { 201, 1, 98, 1, 3857, 0 }, - { 414, 1, 98, 1, 3857, 0 }, - { 583, 1, 98, 1, 3857, 0 }, - { 741, 1, 98, 1, 3857, 0 }, - { 1304, 1, 98, 1, 3857, 0 }, - { 1438, 1, 98, 1, 3857, 0 }, - { 1568, 1, 98, 1, 3857, 0 }, - { 1698, 1, 98, 1, 3857, 0 }, - { 1265, 122, 1, 0, 1280, 2 }, - { 204, 1, 96, 1, 3825, 0 }, - { 417, 1, 96, 1, 3825, 0 }, - { 586, 1, 96, 1, 3825, 0 }, - { 744, 1, 96, 1, 3825, 0 }, - { 1307, 1, 96, 1, 3825, 0 }, - { 1441, 1, 96, 1, 3825, 0 }, - { 1571, 1, 96, 1, 3825, 0 }, - { 1701, 1, 96, 1, 3825, 0 }, - { 1823, 1, 96, 1, 3825, 0 }, - { 1961, 1, 96, 1, 3825, 0 }, - { 207, 1, 96, 1, 3825, 0 }, - { 420, 1, 96, 1, 3825, 0 }, - { 210, 92, 1, 8, 1425, 10 }, - { 423, 92, 1, 8, 1425, 10 }, - { 589, 92, 1, 8, 1425, 10 }, - { 747, 92, 1, 8, 1425, 10 }, - { 1310, 92, 1, 8, 1425, 10 }, - { 1444, 92, 1, 8, 1425, 10 }, - { 1574, 92, 1, 8, 1425, 10 }, - { 1704, 92, 1, 8, 1425, 10 }, - { 1826, 92, 1, 8, 1425, 10 }, - { 1964, 92, 1, 8, 1425, 10 }, - { 41, 92, 1, 8, 1425, 10 }, - { 254, 92, 1, 8, 1425, 10 }, - { 467, 92, 1, 8, 1425, 10 }, - { 633, 92, 1, 8, 1425, 10 }, - { 791, 92, 1, 8, 1425, 10 }, - { 1354, 92, 1, 8, 1425, 10 }, - { 1484, 92, 1, 8, 1425, 10 }, - { 1614, 92, 1, 8, 1425, 10 }, - { 1744, 92, 1, 8, 1425, 10 }, - { 1866, 92, 1, 8, 1425, 10 }, - { 88, 92, 1, 8, 1425, 10 }, - { 301, 92, 1, 8, 1425, 10 }, - { 514, 92, 1, 8, 1425, 10 }, - { 680, 92, 1, 8, 1425, 10 }, - { 838, 92, 1, 8, 1425, 10 }, - { 1401, 92, 1, 8, 1425, 10 }, - { 1531, 92, 1, 8, 1425, 10 }, - { 1661, 92, 1, 8, 1425, 10 }, - { 1791, 92, 1, 8, 1425, 10 }, - { 1929, 92, 1, 8, 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1940, 183, 1, 8, 741539, 8 }, + { 2684, 183, 1, 8, 741540, 8 }, + { 2945, 183, 1, 8, 741541, 8 }, + { 3190, 183, 1, 8, 741542, 8 }, + { 3417, 183, 1, 8, 741543, 8 }, + { 3626, 183, 1, 8, 741544, 8 }, + { 229, 183, 1, 8, 741545, 8 }, + { 683, 183, 1, 8, 741546, 8 }, + { 2347, 4, 1, 0, 4125, 0 }, + { 4548, 1, 1, 1, 4423, 11 }, + { 4572, 1, 1, 1, 4424, 11 }, + { 4596, 1, 1, 1, 4425, 11 }, + { 4614, 1, 1, 1, 4426, 11 }, + { 4632, 1, 1, 1, 4427, 11 }, + { 4650, 1, 1, 1, 4428, 11 }, + { 4668, 1, 1, 1, 4429, 11 }, + { 4680, 1, 1, 1, 4430, 11 }, + { 5108, 1, 1, 1, 4431, 11 }, + { 4863, 1, 1, 1, 4432, 11 }, + { 5210, 1, 1, 1, 4433, 11 }, + { 4912, 1, 1, 1, 4434, 11 }, + { 3721, 1, 1, 1, 4435, 11 }, + { 4956, 1, 1, 1, 4436, 11 }, + { 4069, 1, 1, 1, 4437, 11 }, + { 4019, 1, 1, 1, 4438, 11 }, + { 4036, 1, 1, 1, 4439, 11 }, + { 3989, 1, 1, 1, 4440, 11 }, + { 4158, 1, 1, 1, 4441, 11 }, + { 5180, 1, 1, 1, 4442, 11 }, + { 4136, 1, 1, 1, 4443, 11 }, + { 5047, 1, 1, 1, 4444, 11 }, + { 4194, 1, 1, 1, 4445, 11 }, + { 4775, 1, 1, 1, 4446, 11 }, + { 4173, 1, 1, 1, 4447, 11 }, + { 3896, 1, 1, 1, 4448, 11 }, + { 3789, 1, 1, 1, 4449, 11 }, + { 4083, 1, 1, 1, 4450, 11 }, + { 4226, 1, 1, 1, 4451, 11 }, + { 4807, 1, 1, 1, 4452, 11 }, + { 4005, 1, 1, 1, 4453, 11 }, + { 4256, 1, 1, 1, 4454, 11 }, + { 3819, 1, 1, 1, 4455, 11 }, + { 4489, 1, 1, 1, 4456, 11 }, + { 3802, 1, 1, 1, 4457, 11 }, + { 4929, 1, 1, 1, 4458, 11 }, + { 5015, 1, 1, 1, 4459, 11 }, + { 3703, 1, 1, 1, 4460, 11 }, + { 4210, 1, 1, 1, 4461, 11 }, + { 4791, 1, 1, 1, 4462, 11 }, + { 5196, 1, 1, 1, 4463, 11 }, + { 4519, 1, 1, 1, 4464, 11 }, + { 4241, 1, 1, 1, 4465, 11 }, + { 4822, 1, 1, 1, 4466, 11 }, + { 4897, 1, 1, 1, 4467, 11 }, + { 4884, 1, 1, 1, 4468, 11 }, + { 4272, 1, 1, 1, 4469, 11 }, + { 3863, 1, 1, 1, 4470, 11 }, + { 4417, 1, 1, 1, 4471, 11 }, + { 3771, 1, 1, 1, 4472, 11 }, + { 3831, 1, 1, 1, 4473, 11 }, + { 4757, 1, 1, 1, 4474, 11 }, + { 4327, 1, 1, 1, 4475, 11 }, + { 3883, 1, 1, 1, 4476, 11 }, + { 4054, 1, 1, 1, 4477, 11 }, + { 4534, 1, 1, 1, 4478, 11 }, + { 3919, 1, 1, 1, 4479, 11 }, + { 4098, 1, 1, 1, 4480, 11 }, + { 4742, 1, 1, 1, 4481, 11 }, + { 4504, 1, 1, 1, 4482, 11 }, + { 4842, 1, 1, 1, 4483, 11 }, + { 4997, 1, 1, 1, 4484, 11 }, + { 3935, 1, 1, 1, 4485, 11 }, + { 5145, 1, 1, 1, 4486, 11 }, + { 5032, 1, 1, 1, 4487, 11 }, + { 5061, 1, 1, 1, 4488, 11 }, + { 5090, 1, 1, 1, 4489, 11 }, + { 3950, 1, 1, 1, 4490, 11 }, + { 4286, 1, 1, 1, 4491, 11 }, + { 4980, 1, 1, 1, 4492, 11 }, + { 4377, 1, 1, 1, 4493, 11 }, + { 3735, 1, 1, 1, 4494, 11 }, + { 3753, 1, 1, 1, 4495, 11 }, + { 4359, 1, 1, 1, 4496, 11 }, + { 4472, 1, 1, 1, 4497, 11 }, + { 4454, 1, 1, 1, 4498, 11 }, + { 4436, 1, 1, 1, 4499, 11 }, + { 4398, 1, 1, 1, 4500, 11 }, + { 5075, 1, 1, 1, 4501, 11 }, + { 3969, 1, 1, 1, 4502, 11 }, + { 4306, 1, 1, 1, 4503, 11 }, + { 3849, 1, 1, 1, 4504, 11 }, + { 5163, 1, 1, 1, 4505, 11 }, + { 4113, 1, 1, 1, 4506, 11 }, + { 4344, 1, 1, 1, 4507, 11 }, + { 4554, 1, 1, 1, 4508, 11 }, + { 4578, 1, 1, 1, 4509, 11 }, + { 4560, 1, 1, 1, 4510, 11 }, + { 4584, 1, 1, 1, 4511, 11 }, + { 4602, 1, 1, 1, 4512, 11 }, + { 4620, 1, 1, 1, 4513, 11 }, + { 4638, 1, 1, 1, 4514, 11 }, + { 4656, 1, 1, 1, 4515, 11 }, + { 4674, 1, 1, 1, 4516, 11 }, + { 4686, 1, 1, 1, 4517, 11 }, + { 4566, 1, 1, 1, 4518, 11 }, + { 4590, 1, 1, 1, 4519, 11 }, + { 4608, 1, 1, 1, 4520, 11 }, + { 4626, 1, 1, 1, 4521, 11 }, + { 4644, 1, 1, 1, 4522, 11 }, + { 4662, 1, 1, 1, 4523, 11 }, + { 4692, 1, 1, 1, 4524, 11 }, + { 4698, 1, 1, 1, 4525, 11 }, + { 1971, 2, 1, 0, 4127, 0 }, + { 2049, 2, 1, 0, 4128, 0 }, + { 2099, 2, 1, 0, 4129, 0 }, + { 2137, 2, 1, 0, 4130, 0 }, + { 1977, 20, 1, 12, 507939, 8 }, + { 773, 1, 1, 1, 4526, 11 }, + { 1193, 1, 1, 1, 4527, 11 }, + { 1620, 1, 1, 1, 4528, 11 }, + { 2404, 1, 1, 1, 4529, 11 }, + { 2705, 1, 1, 1, 4530, 11 }, + { 1209, 1, 1, 1, 4531, 11 }, + { 398, 1, 1, 1, 4532, 11 }, + { 906, 1, 1, 1, 4533, 11 }, + { 363, 1, 1, 1, 4534, 11 }, + { 871, 1, 1, 1, 4535, 11 }, + { 1325, 1, 1, 1, 4536, 11 }, + { 1716, 1, 1, 1, 4537, 11 }, + { 789, 1, 1, 1, 4538, 11 }, + { 1224, 1, 1, 1, 4539, 11 }, + { 1636, 1, 1, 1, 4540, 11 }, + { 2420, 1, 1, 1, 4541, 11 }, + { 2721, 1, 1, 1, 4542, 11 }, + { 2966, 1, 1, 1, 4543, 11 }, + { 265, 1, 1, 1, 4544, 11 }, + { 739, 1, 1, 1, 4545, 11 }, + { 431, 1, 1, 1, 4546, 11 }, + { 939, 1, 1, 1, 4547, 11 }, + { 1389, 1, 1, 1, 4548, 11 }, + { 1764, 1, 1, 1, 4549, 11 }, + { 2508, 1, 1, 1, 4550, 11 }, + { 2809, 1, 1, 1, 4551, 11 }, + { 3054, 1, 1, 1, 4552, 11 }, + { 3281, 1, 1, 1, 4553, 11 }, + { 330, 1, 1, 1, 4554, 11 }, + { 838, 1, 1, 1, 4555, 11 }, + { 1292, 1, 1, 1, 4556, 11 }, + { 1699, 1, 1, 1, 4557, 11 }, + { 2461, 1, 1, 1, 4558, 11 }, + { 2762, 1, 1, 1, 4559, 11 }, + { 3007, 1, 1, 1, 4560, 11 }, + { 3234, 1, 1, 1, 4561, 11 }, + { 347, 1, 1, 1, 4562, 11 }, + { 855, 1, 1, 1, 4563, 11 }, + { 1309, 1, 1, 1, 4564, 11 }, + { 282, 1, 1, 1, 4565, 11 }, + { 756, 1, 1, 1, 4566, 11 }, + { 1176, 1, 1, 1, 4567, 11 }, + { 1603, 1, 1, 1, 4568, 11 }, + { 2387, 1, 1, 1, 4569, 11 }, + { 1360, 1, 1, 1, 4570, 11 }, + { 1265, 1, 1, 1, 4571, 11 }, + { 1677, 1, 1, 1, 4572, 11 }, + { 687, 1, 1, 1, 4573, 11 }, + { 1141, 1, 1, 1, 4574, 11 }, + { 248, 1, 1, 1, 4575, 11 }, + { 722, 1, 1, 1, 4576, 11 }, + { 299, 1, 1, 1, 4577, 11 }, + { 807, 1, 1, 1, 4578, 11 }, + { 1242, 1, 1, 1, 4579, 11 }, + { 1654, 1, 1, 1, 4580, 11 }, + { 2438, 1, 1, 1, 4581, 11 }, + { 2739, 1, 1, 1, 4582, 11 }, + { 2984, 1, 1, 1, 4583, 11 }, + { 3211, 1, 1, 1, 4584, 11 }, + { 3438, 1, 1, 1, 4585, 11 }, + { 3647, 1, 1, 1, 4586, 11 }, + { 41, 1, 1, 1, 4587, 11 }, + { 495, 1, 1, 1, 4588, 11 }, + { 1003, 1, 1, 1, 4589, 11 }, + { 1450, 1, 1, 1, 4590, 11 }, + { 1825, 1, 1, 1, 4591, 11 }, + { 2569, 1, 1, 1, 4592, 11 }, + { 381, 1, 1, 1, 4593, 11 }, + { 889, 1, 1, 1, 4594, 11 }, + { 1343, 1, 1, 1, 4595, 11 }, + { 1734, 1, 1, 1, 4596, 11 }, + { 2478, 1, 1, 1, 4597, 11 }, + { 2779, 1, 1, 1, 4598, 11 }, + { 3024, 1, 1, 1, 4599, 11 }, + { 3251, 1, 1, 1, 4600, 11 }, + { 3461, 1, 1, 1, 4601, 11 }, + { 3670, 1, 1, 1, 4602, 11 }, + { 66, 1, 1, 1, 4603, 11 }, + { 520, 1, 1, 1, 4604, 11 }, + { 1028, 1, 1, 1, 4605, 11 }, + { 1475, 1, 1, 1, 4606, 11 }, + { 1850, 1, 1, 1, 4607, 11 }, + { 2594, 1, 1, 1, 4608, 11 }, + { 1984, 184, 27, 9, 741515, 8 }, + { 2055, 184, 27, 9, 741516, 8 }, + { 2105, 184, 27, 9, 741517, 8 }, + { 2143, 184, 27, 9, 741518, 8 }, + { 2175, 184, 27, 9, 741519, 8 }, + { 2207, 184, 27, 9, 741520, 8 }, + { 2239, 184, 27, 9, 741521, 8 }, + { 2271, 184, 27, 9, 741522, 8 }, + { 2303, 184, 27, 9, 741523, 8 }, + { 2329, 184, 27, 9, 741524, 8 }, + { 1950, 184, 27, 9, 741525, 8 }, + { 2028, 184, 27, 9, 741526, 8 }, + { 2085, 184, 27, 9, 741527, 8 }, + { 2123, 184, 27, 9, 741528, 8 }, + { 2161, 184, 27, 9, 741529, 8 }, + { 2193, 184, 27, 9, 741530, 8 }, + { 2225, 184, 27, 9, 741531, 8 }, + { 2257, 184, 27, 9, 741532, 8 }, + { 2289, 184, 27, 9, 741533, 8 }, + { 2315, 184, 27, 9, 741534, 8 }, + { 1957, 184, 27, 9, 741535, 8 }, + { 2035, 184, 27, 9, 741536, 8 }, + { 2092, 184, 27, 9, 741537, 8 }, + { 2130, 184, 27, 9, 741538, 8 }, + { 2168, 184, 27, 9, 741539, 8 }, + { 2200, 184, 27, 9, 741540, 8 }, + { 2232, 184, 27, 9, 741541, 8 }, + { 2264, 184, 27, 9, 741542, 8 }, + { 2296, 184, 27, 9, 741543, 8 }, + { 2322, 184, 27, 9, 741544, 8 }, + { 1964, 184, 27, 9, 741545, 8 }, + { 2042, 184, 27, 9, 741546, 8 }, + { 3554, 1, 0, 1, 4101, 11 }, + { 1990, 6, 113, 0, 4132, 0 }, + { 1997, 8, 1, 0, 4371, 0 }, + { 2061, 8, 1, 0, 4372, 0 }, + { 2003, 8, 109, 0, 4131, 0 }, + { 2010, 12, 1, 0, 4403, 0 }, + { 2067, 12, 1, 0, 4404, 0 }, + { 2111, 12, 1, 0, 4405, 0 }, + { 2149, 12, 1, 0, 4406, 0 }, + { 2181, 12, 1, 0, 4407, 0 }, + { 2213, 12, 1, 0, 4408, 0 }, + { 2245, 12, 1, 0, 4409, 0 }, + { 2277, 12, 1, 0, 4410, 0 }, + { 2016, 14, 1, 0, 4411, 0 }, + { 2073, 14, 1, 0, 4412, 0 }, + { 2117, 14, 1, 0, 4413, 0 }, + { 2155, 14, 1, 0, 4414, 0 }, + { 2187, 14, 1, 0, 4415, 0 }, + { 2219, 14, 1, 0, 4416, 0 }, + { 2251, 14, 1, 0, 4417, 0 }, + { 2283, 14, 1, 0, 4418, 0 }, + { 2309, 14, 1, 0, 4419, 0 }, + { 2335, 14, 1, 0, 4420, 0 }, + { 2022, 14, 1, 0, 4421, 0 }, + { 2079, 14, 1, 0, 4422, 0 }, + { 5124, 1, 1, 1, 4609, 11 }, }; - // OddSP Register Class... - static const MCPhysReg OddSP[] = { - Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, + // MSA128F16 Register Class... + static const MCPhysReg MSA128F16[] = { + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, + }; + + // MSA128F16 Bit set. + static const uint8_t MSA128F16Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; - // OddSP Bit set. - static const uint8_t OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, + // COP0Sel Register Class... + static const MCPhysReg COP0Sel[] = { + Mips_COP0Sel_INDEX, Mips_COP0Sel_MVPCONTROL, Mips_COP0Sel_MVPCONF0, Mips_COP0Sel_MVPCONF1, Mips_COP0Sel_VPCONTROL, Mips_COP0Sel_RANDOM, Mips_COP0Sel_VPECONTROL, Mips_COP0Sel_VPECONF0, Mips_COP0Sel_VPECONF1, Mips_COP0Sel_YQMASK, Mips_COP0Sel_VPESCHEDULE, Mips_COP0Sel_VPESCHEFBACK, Mips_COP0Sel_VPEOPT, Mips_COP0Sel_ENTRYLO0, Mips_COP0Sel_TCSTATUS, Mips_COP0Sel_TCBIND, Mips_COP0Sel_TCRESTART, Mips_COP0Sel_TCHALT, Mips_COP0Sel_TCCONTEXT, Mips_COP0Sel_TCSCHEDULE, Mips_COP0Sel_TCSCHEFBACK, Mips_COP0Sel_ENTRYLO1, Mips_COP0Sel_GLOBALNUMBER, Mips_COP0Sel_TCOPT, Mips_COP0Sel_CONTEXT, Mips_COP0Sel_CONTEXTCONFIG, Mips_COP0Sel_USERLOCAL, Mips_COP0Sel_XCONTEXTCONFIG, Mips_COP0Sel_DEBUGCONTEXTID, Mips_COP0Sel_MEMORYMAPID, Mips_COP0Sel_PAGEMASK, Mips_COP0Sel_PAGEGRAIN, Mips_COP0Sel_SEGCTL0, Mips_COP0Sel_SEGCTL1, Mips_COP0Sel_SEGCTL2, Mips_COP0Sel_PWBASE, Mips_COP0Sel_PWFIELD, Mips_COP0Sel_PWSIZE, Mips_COP0Sel_WIRED, Mips_COP0Sel_SRSCONF0, Mips_COP0Sel_SRSCONF1, Mips_COP0Sel_SRSCONF2, Mips_COP0Sel_SRSCONF3, Mips_COP0Sel_SRSCONF4, Mips_COP0Sel_PWCTL, Mips_COP0Sel_HWRENA, Mips_COP0Sel_BADVADDR, Mips_COP0Sel_BADINST, Mips_COP0Sel_BADINSTRP, Mips_COP0Sel_BADINSTRX, Mips_COP0Sel_COUNT, Mips_COP0Sel_ENTRYHI, Mips_COP0Sel_GUESTCTL1, Mips_COP0Sel_GUESTCTL2, Mips_COP0Sel_GUESTCTL3, Mips_COP0Sel_COMPARE, Mips_COP0Sel_GUESTCTL0EXT, Mips_COP0Sel_STATUS, Mips_COP0Sel_INTCTL, Mips_COP0Sel_SRSCTL, Mips_COP0Sel_SRSMAP, Mips_COP0Sel_VIEW_IPL, Mips_COP0Sel_SRSMAP2, Mips_COP0Sel_GUESTCTL0, Mips_COP0Sel_GTOFFSET, Mips_COP0Sel_CAUSE, Mips_COP0Sel_VIEW_RIPL, Mips_COP0Sel_NESTEDEXC, Mips_COP0Sel_EPC, Mips_COP0Sel_NESTEDEPC, Mips_COP0Sel_PRID, Mips_COP0Sel_EBASE, Mips_COP0Sel_CDMMBASE, Mips_COP0Sel_CMGCRBASE, Mips_COP0Sel_BEVVA, Mips_COP0Sel_CONFIG, Mips_COP0Sel_CONFIG1, Mips_COP0Sel_CONFIG2, Mips_COP0Sel_CONFIG3, Mips_COP0Sel_CONFIG4, Mips_COP0Sel_CONFIG5, Mips_COP0Sel_LLADDR, Mips_COP0Sel_MAAR, Mips_COP0Sel_MAARI, Mips_COP0Sel_WATCHLO0, Mips_COP0Sel_WATCHLO1, Mips_COP0Sel_WATCHLO2, Mips_COP0Sel_WATCHLO3, Mips_COP0Sel_WATCHLO4, Mips_COP0Sel_WATCHLO5, Mips_COP0Sel_WATCHLO6, Mips_COP0Sel_WATCHLO7, Mips_COP0Sel_WATCHLO8, Mips_COP0Sel_WATCHLO9, Mips_COP0Sel_WATCHLO10, Mips_COP0Sel_WATCHLO11, Mips_COP0Sel_WATCHLO12, Mips_COP0Sel_WATCHLO13, Mips_COP0Sel_WATCHLO14, Mips_COP0Sel_WATCHLO15, Mips_COP0Sel_WATCHHI0, Mips_COP0Sel_WATCHHI1, Mips_COP0Sel_WATCHHI2, Mips_COP0Sel_WATCHHI3, Mips_COP0Sel_WATCHHI4, Mips_COP0Sel_WATCHHI5, Mips_COP0Sel_WATCHHI6, Mips_COP0Sel_WATCHHI7, Mips_COP0Sel_WATCHHI8, Mips_COP0Sel_WATCHHI9, Mips_COP0Sel_WATCHHI10, Mips_COP0Sel_WATCHHI11, Mips_COP0Sel_WATCHHI12, Mips_COP0Sel_WATCHHI13, Mips_COP0Sel_WATCHHI14, Mips_COP0Sel_WATCHHI15, Mips_COP0Sel_XCONTEXT, Mips_COP0Sel_DEBUG, Mips_COP0Sel_TRACECONTROL, Mips_COP0Sel_TRACECONTROL2, Mips_COP0Sel_USERTRACEDATA1, Mips_COP0Sel_TRACEIBPC, Mips_COP0Sel_TRACEDBPC, Mips_COP0Sel_DEBUG2, Mips_COP0Sel_DEPC, Mips_COP0Sel_TRACECONTROL3, Mips_COP0Sel_USERTRACEDATA2, Mips_COP0Sel_PERFCTL0, Mips_COP0Sel_PERFCNT0, Mips_COP0Sel_PERFCTL1, Mips_COP0Sel_PERFCNT1, Mips_COP0Sel_PERFCTL2, Mips_COP0Sel_PERFCNT2, Mips_COP0Sel_PERFCTL3, Mips_COP0Sel_PERFCNT3, Mips_COP0Sel_PERFCTL4, Mips_COP0Sel_PERFCNT4, Mips_COP0Sel_PERFCTL5, Mips_COP0Sel_PERFCNT5, Mips_COP0Sel_PERFCTL6, Mips_COP0Sel_PERFCNT6, Mips_COP0Sel_PERFCTL7, Mips_COP0Sel_PERFCNT7, Mips_COP0Sel_ERRCTL, Mips_COP0Sel_CACHEERR, Mips_COP0Sel_ITAGLO, Mips_COP0Sel_IDATALO, Mips_COP0Sel_DTAGLO, Mips_COP0Sel_DDATALO, Mips_COP0Sel_ITAGHI, Mips_COP0Sel_IDATAHI, Mips_COP0Sel_DTAGHI, Mips_COP0Sel_DDATAHI, Mips_COP0Sel_ERROREPC, Mips_COP0Sel_DESAVE, Mips_COP0Sel_KSCRATCH1, Mips_COP0Sel_KSCRATCH2, Mips_COP0Sel_KSCRATCH3, Mips_COP0Sel_KSCRATCH4, Mips_COP0Sel_KSCRATCH5, Mips_COP0Sel_KSCRATCH6, + }; + + // COP0Sel Bit set. + static const uint8_t COP0SelBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, }; // CCR Register Class... static const MCPhysReg CCR[] = { - Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, Mips_FCR30, Mips_FCR31, + Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, Mips_FCR30, Mips_FCR31, }; // CCR Bit set. static const uint8_t CCRBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, + }; + + // COP0 Register Class... + static const MCPhysReg COP0[] = { + Mips_COP00, Mips_COP01, Mips_COP02, Mips_COP03, Mips_COP04, Mips_COP05, Mips_COP06, Mips_COP07, Mips_COP08, Mips_COP09, Mips_COP010, Mips_COP011, Mips_COP012, Mips_COP013, Mips_COP014, Mips_COP015, Mips_COP016, Mips_COP017, Mips_COP018, Mips_COP019, Mips_COP020, Mips_COP021, Mips_COP022, Mips_COP023, Mips_COP024, Mips_COP025, Mips_COP026, Mips_COP027, Mips_COP028, Mips_COP029, Mips_COP030, Mips_COP031, + }; + + // COP0 Bit set. + static const uint8_t COP0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0xe0, 0x7f, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01, }; // COP2 Register Class... static const MCPhysReg COP2[] = { - Mips_COP20, Mips_COP21, Mips_COP22, Mips_COP23, Mips_COP24, Mips_COP25, Mips_COP26, Mips_COP27, Mips_COP28, Mips_COP29, Mips_COP210, Mips_COP211, Mips_COP212, Mips_COP213, Mips_COP214, Mips_COP215, Mips_COP216, Mips_COP217, Mips_COP218, Mips_COP219, Mips_COP220, Mips_COP221, Mips_COP222, Mips_COP223, Mips_COP224, Mips_COP225, Mips_COP226, Mips_COP227, Mips_COP228, Mips_COP229, Mips_COP230, Mips_COP231, + Mips_COP20, Mips_COP21, Mips_COP22, Mips_COP23, Mips_COP24, Mips_COP25, Mips_COP26, Mips_COP27, Mips_COP28, Mips_COP29, Mips_COP210, Mips_COP211, Mips_COP212, Mips_COP213, Mips_COP214, Mips_COP215, Mips_COP216, Mips_COP217, Mips_COP218, Mips_COP219, Mips_COP220, Mips_COP221, Mips_COP222, Mips_COP223, Mips_COP224, Mips_COP225, Mips_COP226, Mips_COP227, Mips_COP228, Mips_COP229, Mips_COP230, Mips_COP231, }; // COP2 Bit set. static const uint8_t COP2Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0xf8, 0xff, 0xff, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f, }; // COP3 Register Class... static const MCPhysReg COP3[] = { - Mips_COP30, Mips_COP31, Mips_COP32, Mips_COP33, Mips_COP34, Mips_COP35, Mips_COP36, Mips_COP37, Mips_COP38, Mips_COP39, Mips_COP310, Mips_COP311, Mips_COP312, Mips_COP313, Mips_COP314, Mips_COP315, Mips_COP316, Mips_COP317, Mips_COP318, Mips_COP319, Mips_COP320, Mips_COP321, Mips_COP322, Mips_COP323, Mips_COP324, Mips_COP325, Mips_COP326, Mips_COP327, Mips_COP328, Mips_COP329, Mips_COP330, Mips_COP331, + Mips_COP30, Mips_COP31, Mips_COP32, Mips_COP33, Mips_COP34, Mips_COP35, Mips_COP36, Mips_COP37, Mips_COP38, Mips_COP39, Mips_COP310, Mips_COP311, Mips_COP312, Mips_COP313, Mips_COP314, Mips_COP315, Mips_COP316, Mips_COP317, Mips_COP318, Mips_COP319, Mips_COP320, Mips_COP321, Mips_COP322, Mips_COP323, Mips_COP324, Mips_COP325, Mips_COP326, Mips_COP327, Mips_COP328, Mips_COP329, Mips_COP330, Mips_COP331, }; // COP3 Bit set. static const uint8_t COP3Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0xfe, 0xff, 0x7f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x1f, }; // DSPR Register Class... static const MCPhysReg DSPR[] = { - Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, + Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, }; // DSPR Bit set. static const uint8_t DSPRBits[] = { - 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, + 0x02, 0x0a, 0x40, 0xf5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0xf0, 0xef, 0xff, 0x01, }; // FGR32 Register Class... static const MCPhysReg FGR32[] = { - Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, + Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, }; // FGR32 Bit set. static const uint8_t FGR32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // FGRCC Register Class... static const MCPhysReg FGRCC[] = { - Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, + Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, }; // FGRCC Bit set. static const uint8_t FGRCCBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, - }; - - // FGRH32 Register Class... - static const MCPhysReg FGRH32[] = { - Mips_F_HI0, Mips_F_HI1, Mips_F_HI2, Mips_F_HI3, Mips_F_HI4, Mips_F_HI5, Mips_F_HI6, Mips_F_HI7, Mips_F_HI8, Mips_F_HI9, Mips_F_HI10, Mips_F_HI11, Mips_F_HI12, Mips_F_HI13, Mips_F_HI14, Mips_F_HI15, Mips_F_HI16, Mips_F_HI17, Mips_F_HI18, Mips_F_HI19, Mips_F_HI20, Mips_F_HI21, Mips_F_HI22, Mips_F_HI23, Mips_F_HI24, Mips_F_HI25, Mips_F_HI26, Mips_F_HI27, Mips_F_HI28, Mips_F_HI29, Mips_F_HI30, Mips_F_HI31, - }; - - // FGRH32 Bit set. - static const uint8_t FGRH32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // GPR32 Register Class... static const MCPhysReg GPR32[] = { - Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, + Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, }; // GPR32 Bit set. static const uint8_t GPR32Bits[] = { - 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, + 0x02, 0x0a, 0x40, 0xf5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0xf0, 0xef, 0xff, 0x01, + }; + + // GPRNM32 Register Class... + static const MCPhysReg GPRNM32[] = { + Mips_ZERO_NM, Mips_AT_NM, Mips_T4_NM, Mips_T5_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, Mips_A4_NM, Mips_A5_NM, Mips_A6_NM, Mips_A7_NM, Mips_T0_NM, Mips_T1_NM, Mips_T2_NM, Mips_T3_NM, Mips_S0_NM, Mips_S1_NM, Mips_S2_NM, Mips_S3_NM, Mips_S4_NM, Mips_S5_NM, Mips_S6_NM, Mips_S7_NM, Mips_T8_NM, Mips_T9_NM, Mips_K0_NM, Mips_K1_NM, Mips_GP_NM, Mips_SP_NM, Mips_FP_NM, Mips_RA_NM, + }; + + // GPRNM32 Bit set. + static const uint8_t GPRNM32Bits[] = { + 0x04, 0x14, 0x80, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x01, }; // HWRegs Register Class... static const MCPhysReg HWRegs[] = { - Mips_HWR0, Mips_HWR1, Mips_HWR2, Mips_HWR3, Mips_HWR4, Mips_HWR5, Mips_HWR6, Mips_HWR7, Mips_HWR8, Mips_HWR9, Mips_HWR10, Mips_HWR11, Mips_HWR12, Mips_HWR13, Mips_HWR14, Mips_HWR15, Mips_HWR16, Mips_HWR17, Mips_HWR18, Mips_HWR19, Mips_HWR20, Mips_HWR21, Mips_HWR22, Mips_HWR23, Mips_HWR24, Mips_HWR25, Mips_HWR26, Mips_HWR27, Mips_HWR28, Mips_HWR29, Mips_HWR30, Mips_HWR31, + Mips_HWR0, Mips_HWR1, Mips_HWR2, Mips_HWR3, Mips_HWR4, Mips_HWR5, Mips_HWR6, Mips_HWR7, Mips_HWR8, Mips_HWR9, Mips_HWR10, Mips_HWR11, Mips_HWR12, Mips_HWR13, Mips_HWR14, Mips_HWR15, Mips_HWR16, Mips_HWR17, Mips_HWR18, Mips_HWR19, Mips_HWR20, Mips_HWR21, Mips_HWR22, Mips_HWR23, Mips_HWR24, Mips_HWR25, Mips_HWR26, Mips_HWR27, Mips_HWR28, Mips_HWR29, Mips_HWR30, Mips_HWR31, }; // HWRegs Bit set. static const uint8_t HWRegsBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; - // OddSP_with_sub_hi Register Class... - static const MCPhysReg OddSP_with_sub_hi[] = { - Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, + // MSACtrl Register Class... + static const MCPhysReg MSACtrl[] = { + Mips_MSAIR, Mips_MSACSR, Mips_MSAAccess, Mips_MSASave, Mips_MSAModify, Mips_MSARequest, Mips_MSAMap, Mips_MSAUnmap, Mips_MSA8, Mips_MSA9, Mips_MSA10, Mips_MSA11, Mips_MSA12, Mips_MSA13, Mips_MSA14, Mips_MSA15, Mips_MSA16, Mips_MSA17, Mips_MSA18, Mips_MSA19, Mips_MSA20, Mips_MSA21, Mips_MSA22, Mips_MSA23, Mips_MSA24, Mips_MSA25, Mips_MSA26, Mips_MSA27, Mips_MSA28, Mips_MSA29, Mips_MSA30, Mips_MSA31, }; - // OddSP_with_sub_hi Bit set. - static const uint8_t OddSP_with_sub_hiBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, + // MSACtrl Bit set. + static const uint8_t MSACtrlBits[] = { + 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, }; - // FGR32_and_OddSP Register Class... - static const MCPhysReg FGR32_and_OddSP[] = { - Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, + // GPR32NONZERO Register Class... + static const MCPhysReg GPR32NONZERO[] = { + Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, }; - // FGR32_and_OddSP Bit set. - static const uint8_t FGR32_and_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, + // GPR32NONZERO Bit set. + static const uint8_t GPR32NONZEROBits[] = { + 0x02, 0x0a, 0x40, 0xf1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0xf0, 0xef, 0xff, 0x01, }; - // FGRH32_and_OddSP Register Class... - static const MCPhysReg FGRH32_and_OddSP[] = { - Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, + // GPRNM32NZ Register Class... + static const MCPhysReg GPRNM32NZ[] = { + Mips_AT_NM, Mips_T4_NM, Mips_T5_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, Mips_A4_NM, Mips_A5_NM, Mips_A6_NM, Mips_A7_NM, Mips_T0_NM, Mips_T1_NM, Mips_T2_NM, Mips_T3_NM, Mips_S0_NM, Mips_S1_NM, Mips_S2_NM, Mips_S3_NM, Mips_S4_NM, Mips_S5_NM, Mips_S6_NM, Mips_S7_NM, Mips_T8_NM, Mips_T9_NM, Mips_K0_NM, Mips_K1_NM, Mips_GP_NM, Mips_SP_NM, Mips_FP_NM, Mips_RA_NM, }; - // FGRH32_and_OddSP Bit set. - static const uint8_t FGRH32_and_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, + // GPRNM32NZ Bit set. + static const uint8_t GPRNM32NZBits[] = { + 0x04, 0x14, 0x80, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x01, }; - // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class... - static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = { - Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, + // GPRNM32_TAIL Register Class... + static const MCPhysReg GPRNM32_TAIL[] = { + Mips_T4_NM, Mips_T5_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, Mips_A4_NM, Mips_A5_NM, Mips_A6_NM, Mips_A7_NM, Mips_T0_NM, Mips_T1_NM, Mips_T2_NM, Mips_T3_NM, Mips_T8_NM, Mips_T9_NM, }; - // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set. - static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, + // GPRNM32_TAIL Bit set. + static const uint8_t GPRNM32_TAILBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, }; - // CPU16RegsPlusSP Register Class... - static const MCPhysReg CPU16RegsPlusSP[] = { - Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, Mips_SP, + // GPRNM4 Register Class... + static const MCPhysReg GPRNM4[] = { + Mips_A4_NM, Mips_A5_NM, Mips_A6_NM, Mips_A7_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, Mips_S0_NM, Mips_S1_NM, Mips_S2_NM, Mips_S3_NM, Mips_S4_NM, Mips_S5_NM, Mips_S6_NM, Mips_S7_NM, }; - // CPU16RegsPlusSP Bit set. - static const uint8_t CPU16RegsPlusSPBits[] = { - 0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, + // GPRNM4 Bit set. + static const uint8_t GPRNM4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, }; - // CC Register Class... - static const MCPhysReg CC[] = { - Mips_CC0, Mips_CC1, Mips_CC2, Mips_CC3, Mips_CC4, Mips_CC5, Mips_CC6, Mips_CC7, + // GPRNM4Z Register Class... + static const MCPhysReg GPRNM4Z[] = { + Mips_A4_NM, Mips_A5_NM, Mips_A6_NM, Mips_ZERO_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, Mips_S0_NM, Mips_S1_NM, Mips_S2_NM, Mips_S3_NM, Mips_S4_NM, Mips_S5_NM, Mips_S6_NM, Mips_S7_NM, }; - // CC Bit set. - static const uint8_t CCBits[] = { - 0x00, 0x00, 0x00, 0x80, 0x7f, + // GPRNM4Z Bit set. + static const uint8_t GPRNM4ZBits[] = { + 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, + }; + + // GPRNM4_and_GPRNM4Z Register Class... + static const MCPhysReg GPRNM4_and_GPRNM4Z[] = { + Mips_A4_NM, Mips_A5_NM, Mips_A6_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, Mips_S0_NM, Mips_S1_NM, Mips_S2_NM, Mips_S3_NM, Mips_S4_NM, Mips_S5_NM, Mips_S6_NM, Mips_S7_NM, + }; + + // GPRNM4_and_GPRNM4Z Bit set. + static const uint8_t GPRNM4_and_GPRNM4ZBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, + }; + + // CPU16RegsPlusSP Register Class... + static const MCPhysReg CPU16RegsPlusSP[] = { + Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, Mips_SP, + }; + + // CPU16RegsPlusSP Bit set. + static const uint8_t CPU16RegsPlusSPBits[] = { + 0x00, 0x00, 0x00, 0xf1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x80, 0x01, }; // CPU16Regs Register Class... static const MCPhysReg CPU16Regs[] = { - Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, + Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, }; // CPU16Regs Bit set. static const uint8_t CPU16RegsBits[] = { - 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, + 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x80, 0x01, }; // FCC Register Class... static const MCPhysReg FCC[] = { - Mips_FCC0, Mips_FCC1, Mips_FCC2, Mips_FCC3, Mips_FCC4, Mips_FCC5, Mips_FCC6, Mips_FCC7, + Mips_FCC0, Mips_FCC1, Mips_FCC2, Mips_FCC3, Mips_FCC4, Mips_FCC5, Mips_FCC6, Mips_FCC7, }; // FCC Bit set. static const uint8_t FCCBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, }; // GPRMM16 Register Class... static const MCPhysReg GPRMM16[] = { - Mips_S0, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, + Mips_S0, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, }; // GPRMM16 Bit set. static const uint8_t GPRMM16Bits[] = { - 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, + 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x80, 0x01, }; // GPRMM16MoveP Register Class... static const MCPhysReg GPRMM16MoveP[] = { - Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4, + Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4, }; // GPRMM16MoveP Bit set. static const uint8_t GPRMM16MovePBits[] = { - 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01, 0x80, 0x01, }; // GPRMM16Zero Register Class... static const MCPhysReg GPRMM16Zero[] = { - Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, + Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, }; // GPRMM16Zero Bit set. static const uint8_t GPRMM16ZeroBits[] = { - 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, + 0x00, 0x00, 0x00, 0xf4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x80, 0x01, }; - // MSACtrl Register Class... - static const MCPhysReg MSACtrl[] = { - Mips_MSAIR, Mips_MSACSR, Mips_MSAAccess, Mips_MSASave, Mips_MSAModify, Mips_MSARequest, Mips_MSAMap, Mips_MSAUnmap, + // GPRNM3 Register Class... + static const MCPhysReg GPRNM3[] = { + Mips_S0_NM, Mips_S1_NM, Mips_S2_NM, Mips_S3_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, }; - // MSACtrl Bit set. - static const uint8_t MSACtrlBits[] = { - 0x00, 0xfc, 0x03, + // GPRNM3 Bit set. + static const uint8_t GPRNM3Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, }; - // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class... - static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = { - Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, + // GPRNM3Z Register Class... + static const MCPhysReg GPRNM3Z[] = { + Mips_ZERO_NM, Mips_S1_NM, Mips_S2_NM, Mips_S3_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, }; - // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set. - static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, + // GPRNM3Z Bit set. + static const uint8_t GPRNM3ZBits[] = { + 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, + }; + + // GPRNM4_and_GPRNM32_TAIL Register Class... + static const MCPhysReg GPRNM4_and_GPRNM32_TAIL[] = { + Mips_A4_NM, Mips_A5_NM, Mips_A6_NM, Mips_A7_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, + }; + + // GPRNM4_and_GPRNM32_TAIL Bit set. + static const uint8_t GPRNM4_and_GPRNM32_TAILBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, }; // CPU16Regs_and_GPRMM16Zero Register Class... static const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = { - Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, + Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, }; // CPU16Regs_and_GPRMM16Zero Bit set. static const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, + 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x80, 0x01, + }; + + // GPR32NONZERO_and_GPRMM16MoveP Register Class... + static const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = { + Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4, + }; + + // GPR32NONZERO_and_GPRMM16MoveP Bit set. + static const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01, 0x80, 0x01, + }; + + // GPRNM3_and_GPRNM3Z Register Class... + static const MCPhysReg GPRNM3_and_GPRNM3Z[] = { + Mips_S1_NM, Mips_S2_NM, Mips_S3_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, + }; + + // GPRNM3_and_GPRNM3Z Bit set. + static const uint8_t GPRNM3_and_GPRNM3ZBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, + }; + + // GPRNM4Z_and_GPRNM32_TAIL Register Class... + static const MCPhysReg GPRNM4Z_and_GPRNM32_TAIL[] = { + Mips_A4_NM, Mips_A5_NM, Mips_A6_NM, Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, + }; + + // GPRNM4Z_and_GPRNM32_TAIL Bit set. + static const uint8_t GPRNM4Z_and_GPRNM32_TAILBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, + }; + + // GPRMM16MovePPairSecond Register Class... + static const MCPhysReg GPRMM16MovePPairSecond[] = { + Mips_A1, Mips_A2, Mips_A3, Mips_S5, Mips_S6, + }; + + // GPRMM16MovePPairSecond Bit set. + static const uint8_t GPRMM16MovePPairSecondBits[] = { + 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, }; // CPU16Regs_and_GPRMM16MoveP Register Class... static const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = { - Mips_S1, Mips_V0, Mips_V1, Mips_S0, + Mips_S1, Mips_V0, Mips_V1, Mips_S0, }; // CPU16Regs_and_GPRMM16MoveP Bit set. static const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x80, 0x01, }; // GPRMM16MoveP_and_GPRMM16Zero Register Class... static const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = { - Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, + Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, }; // GPRMM16MoveP_and_GPRMM16Zero Bit set. static const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x80, 0x01, + }; + + // GPRNM2R1 Register Class... + static const MCPhysReg GPRNM2R1[] = { + Mips_A0_NM, Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, + }; + + // GPRNM2R1 Bit set. + static const uint8_t GPRNM2R1Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, + }; + + // GPRNM2R2 Register Class... + static const MCPhysReg GPRNM2R2[] = { + Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, Mips_A4_NM, + }; + + // GPRNM2R2 Bit set. + static const uint8_t GPRNM2R2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, }; // HI32DSP Register Class... static const MCPhysReg HI32DSP[] = { - Mips_HI0, Mips_HI1, Mips_HI2, Mips_HI3, + Mips_HI0, Mips_HI1, Mips_HI2, Mips_HI3, }; // HI32DSP Bit set. static const uint8_t HI32DSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, }; // LO32DSP Register Class... static const MCPhysReg LO32DSP[] = { - Mips_LO0, Mips_LO1, Mips_LO2, Mips_LO3, + Mips_LO0, Mips_LO1, Mips_LO2, Mips_LO3, }; // LO32DSP Bit set. static const uint8_t LO32DSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, + }; + + // CPU16Regs_and_GPRMM16MovePPairSecond Register Class... + static const MCPhysReg CPU16Regs_and_GPRMM16MovePPairSecond[] = { + Mips_A1, Mips_A2, Mips_A3, + }; + + // CPU16Regs_and_GPRMM16MovePPairSecond Bit set. + static const uint8_t CPU16Regs_and_GPRMM16MovePPairSecondBits[] = { + 0x00, 0x00, 0x00, 0xe0, + }; + + // GPRMM16MovePPairFirst Register Class... + static const MCPhysReg GPRMM16MovePPairFirst[] = { + Mips_A0, Mips_A1, Mips_A2, + }; + + // GPRMM16MovePPairFirst Bit set. + static const uint8_t GPRMM16MovePPairFirstBits[] = { + 0x00, 0x00, 0x00, 0x70, }; // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... static const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { - Mips_S1, Mips_V0, Mips_V1, + Mips_S1, Mips_V0, Mips_V1, }; // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. static const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x80, 0x01, + }; + + // GPRNM2R1_and_GPRNM2R2 Register Class... + static const MCPhysReg GPRNM2R1_and_GPRNM2R2[] = { + Mips_A1_NM, Mips_A2_NM, Mips_A3_NM, + }; + + // GPRNM2R1_and_GPRNM2R2 Bit set. + static const uint8_t GPRNM2R1_and_GPRNM2R2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, + }; + + // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class... + static const MCPhysReg GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = { + Mips_A1, Mips_A2, + }; + + // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set. + static const uint8_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = { + 0x00, 0x00, 0x00, 0x60, + }; + + // GPRNM1R1 Register Class... + static const MCPhysReg GPRNM1R1[] = { + Mips_A0_NM, Mips_A1_NM, + }; + + // GPRNM1R1 Bit set. + static const uint8_t GPRNM1R1Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, }; // CPURAReg Register Class... static const MCPhysReg CPURAReg[] = { - Mips_RA, + Mips_RA, }; // CPURAReg Bit set. static const uint8_t CPURARegBits[] = { - 0x00, 0x00, 0x08, + 0x00, 0x00, 0x40, }; // CPUSPReg Register Class... static const MCPhysReg CPUSPReg[] = { - Mips_SP, + Mips_SP, }; // CPUSPReg Bit set. static const uint8_t CPUSPRegBits[] = { - 0x00, 0x00, 0x10, + 0x00, 0x00, 0x00, 0x01, }; // DSPCC Register Class... static const MCPhysReg DSPCC[] = { - Mips_DSPCCond, + Mips_DSPCCond, }; // DSPCC Bit set. static const uint8_t DSPCCBits[] = { - 0x04, + 0x08, + }; + + // GP32 Register Class... + static const MCPhysReg GP32[] = { + Mips_GP, + }; + + // GP32 Bit set. + static const uint8_t GP32Bits[] = { + 0x00, 0x08, + }; + + // GPR32ZERO Register Class... + static const MCPhysReg GPR32ZERO[] = { + Mips_ZERO, + }; + + // GPR32ZERO Bit set. + static const uint8_t GPR32ZEROBits[] = { + 0x00, 0x00, 0x00, 0x04, + }; + + // GPRNM1R1_and_GPRNM2R2 Register Class... + static const MCPhysReg GPRNM1R1_and_GPRNM2R2[] = { + Mips_A1_NM, + }; + + // GPRNM1R1_and_GPRNM2R2 Bit set. + static const uint8_t GPRNM1R1_and_GPRNM2R2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, + }; + + // GPRNMGP Register Class... + static const MCPhysReg GPRNMGP[] = { + Mips_GP_NM, + }; + + // GPRNMGP Bit set. + static const uint8_t GPRNMGPBits[] = { + 0x00, 0x10, + }; + + // GPRNMRA Register Class... + static const MCPhysReg GPRNMRA[] = { + Mips_RA_NM, + }; + + // GPRNMRA Bit set. + static const uint8_t GPRNMRABits[] = { + 0x00, 0x00, 0x80, + }; + + // GPRNMSP Register Class... + static const MCPhysReg GPRNMSP[] = { + Mips_SP_NM, + }; + + // GPRNMSP Bit set. + static const uint8_t GPRNMSPBits[] = { + 0x00, 0x00, 0x00, 0x02, }; // HI32 Register Class... static const MCPhysReg HI32[] = { - Mips_HI0, + Mips_HI0, }; // HI32 Bit set. static const uint8_t HI32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, }; // LO32 Register Class... static const MCPhysReg LO32[] = { - Mips_LO0, + Mips_LO0, }; // LO32 Bit set. static const uint8_t LO32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, + }; + + // SP32 Register Class... + static const MCPhysReg SP32[] = { + Mips_SP, + }; + + // SP32 Bit set. + static const uint8_t SP32Bits[] = { + 0x00, 0x00, 0x00, 0x01, }; // FGR64 Register Class... static const MCPhysReg FGR64[] = { - Mips_D0_64, Mips_D1_64, Mips_D2_64, Mips_D3_64, Mips_D4_64, Mips_D5_64, Mips_D6_64, Mips_D7_64, Mips_D8_64, Mips_D9_64, Mips_D10_64, Mips_D11_64, Mips_D12_64, Mips_D13_64, Mips_D14_64, Mips_D15_64, Mips_D16_64, Mips_D17_64, Mips_D18_64, Mips_D19_64, Mips_D20_64, Mips_D21_64, Mips_D22_64, Mips_D23_64, Mips_D24_64, Mips_D25_64, Mips_D26_64, Mips_D27_64, Mips_D28_64, Mips_D29_64, Mips_D30_64, Mips_D31_64, + Mips_D0_64, Mips_D1_64, Mips_D2_64, Mips_D3_64, Mips_D4_64, Mips_D5_64, Mips_D6_64, Mips_D7_64, Mips_D8_64, Mips_D9_64, Mips_D10_64, Mips_D11_64, Mips_D12_64, Mips_D13_64, Mips_D14_64, Mips_D15_64, Mips_D16_64, Mips_D17_64, Mips_D18_64, Mips_D19_64, Mips_D20_64, Mips_D21_64, Mips_D22_64, Mips_D23_64, Mips_D24_64, Mips_D25_64, Mips_D26_64, Mips_D27_64, Mips_D28_64, Mips_D29_64, Mips_D30_64, Mips_D31_64, }; // FGR64 Bit set. static const uint8_t FGR64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // GPR64 Register Class... static const MCPhysReg GPR64[] = { - Mips_ZERO_64, Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, Mips_RA_64, + Mips_ZERO_64, Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, Mips_RA_64, }; // GPR64 Bit set. static const uint8_t GPR64Bits[] = { - 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, }; - // AFGR64 Register Class... - static const MCPhysReg AFGR64[] = { - Mips_D0, Mips_D1, Mips_D2, Mips_D3, Mips_D4, Mips_D5, Mips_D6, Mips_D7, Mips_D8, Mips_D9, Mips_D10, Mips_D11, Mips_D12, Mips_D13, Mips_D14, Mips_D15, + // GPR64_with_sub_32_in_GPR32NONZERO Register Class... + static const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = { + Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, Mips_RA_64, }; - // AFGR64 Bit set. - static const uint8_t AFGR64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, + // GPR64_with_sub_32_in_GPR32NONZERO Bit set. + static const uint8_t GPR64_with_sub_32_in_GPR32NONZEROBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, }; - // FGR64_and_OddSP Register Class... - static const MCPhysReg FGR64_and_OddSP[] = { - Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, + // AFGR64 Register Class... + static const MCPhysReg AFGR64[] = { + Mips_D0, Mips_D1, Mips_D2, Mips_D3, Mips_D4, Mips_D5, Mips_D6, Mips_D7, Mips_D8, Mips_D9, Mips_D10, Mips_D11, Mips_D12, Mips_D13, Mips_D14, Mips_D15, }; - // FGR64_and_OddSP Bit set. - static const uint8_t FGR64_and_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, + // AFGR64 Bit set. + static const uint8_t AFGR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class... static const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = { - Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, Mips_SP_64, + Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, Mips_SP_64, }; // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set. static const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, - }; - - // AFGR64_and_OddSP Register Class... - static const MCPhysReg AFGR64_and_OddSP[] = { - Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, - }; - - // AFGR64_and_OddSP Bit set. - static const uint8_t AFGR64_and_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_CPU16Regs Register Class... static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = { - Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, + Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, }; // GPR64_with_sub_32_in_CPU16Regs Bit set. static const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_GPRMM16MoveP Register Class... static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = { - Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, + Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, }; // GPR64_with_sub_32_in_GPRMM16MoveP Bit set. static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, }; // GPR64_with_sub_32_in_GPRMM16Zero Register Class... static const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = { - Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, + Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, }; // GPR64_with_sub_32_in_GPRMM16Zero Bit set. static const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class... static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = { - Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, + Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set. static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, + }; + + // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Register Class... + static const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = { + Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, + }; + + // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Bit set. + static const uint8_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, + }; + + // GPR64_with_sub_32_in_GPRMM16MovePPairSecond Register Class... + static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairSecond[] = { + Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S5_64, Mips_S6_64, + }; + + // GPR64_with_sub_32_in_GPRMM16MovePPairSecond Bit set. + static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, }; // ACC64DSP Register Class... static const MCPhysReg ACC64DSP[] = { - Mips_AC0, Mips_AC1, Mips_AC2, Mips_AC3, + Mips_AC0, Mips_AC1, Mips_AC2, Mips_AC3, }; // ACC64DSP Bit set. static const uint8_t ACC64DSPBits[] = { - 0x00, 0x00, 0x00, 0x3c, + 0x00, 0x00, 0x00, 0x00, 0x0f, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class... static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = { - Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, + Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set. static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class... static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = { - Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S1_64, + Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S1_64, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set. static const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, + }; + + // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Register Class... + static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond[] = { + Mips_A1_64, Mips_A2_64, Mips_A3_64, + }; + + // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Bit set. + static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, + }; + + // GPR64_with_sub_32_in_GPRMM16MovePPairFirst Register Class... + static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst[] = { + Mips_A0_64, Mips_A1_64, Mips_A2_64, + }; + + // GPR64_with_sub_32_in_GPRMM16MovePPairFirst Bit set. + static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { - Mips_V0_64, Mips_V1_64, Mips_S1_64, + Mips_V0_64, Mips_V1_64, Mips_S1_64, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. static const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, }; // OCTEON_MPL Register Class... static const MCPhysReg OCTEON_MPL[] = { - Mips_MPL0, Mips_MPL1, Mips_MPL2, + Mips_MPL0, Mips_MPL1, Mips_MPL2, }; // OCTEON_MPL Bit set. static const uint8_t OCTEON_MPLBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, }; // OCTEON_P Register Class... static const MCPhysReg OCTEON_P[] = { - Mips_P0, Mips_P1, Mips_P2, + Mips_P0, Mips_P1, Mips_P2, }; // OCTEON_P Bit set. static const uint8_t OCTEON_PBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, + }; + + // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class... + static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = { + Mips_A1_64, Mips_A2_64, + }; + + // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set. + static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, }; // ACC64 Register Class... static const MCPhysReg ACC64[] = { - Mips_AC0, + Mips_AC0, }; // ACC64 Bit set. static const uint8_t ACC64Bits[] = { - 0x00, 0x00, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x01, + }; + + // GP64 Register Class... + static const MCPhysReg GP64[] = { + Mips_GP_64, + }; + + // GP64 Bit set. + static const uint8_t GP64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, }; // GPR64_with_sub_32_in_CPURAReg Register Class... static const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = { - Mips_RA_64, + Mips_RA_64, }; // GPR64_with_sub_32_in_CPURAReg Bit set. static const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, }; - // GPR64_with_sub_32_in_CPUSPReg Register Class... - static const MCPhysReg GPR64_with_sub_32_in_CPUSPReg[] = { - Mips_SP_64, + // GPR64_with_sub_32_in_GPR32ZERO Register Class... + static const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = { + Mips_ZERO_64, }; - // GPR64_with_sub_32_in_CPUSPReg Bit set. - static const uint8_t GPR64_with_sub_32_in_CPUSPRegBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, + // GPR64_with_sub_32_in_GPR32ZERO Bit set. + static const uint8_t GPR64_with_sub_32_in_GPR32ZEROBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, }; // HI64 Register Class... static const MCPhysReg HI64[] = { - Mips_HI0_64, + Mips_HI0_64, }; // HI64 Bit set. static const uint8_t HI64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, }; // LO64 Register Class... static const MCPhysReg LO64[] = { - Mips_LO0_64, + Mips_LO0_64, }; // LO64 Bit set. static const uint8_t LO64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, + }; + + // SP64 Register Class... + static const MCPhysReg SP64[] = { + Mips_SP_64, + }; + + // SP64 Bit set. + static const uint8_t SP64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, }; // MSA128B Register Class... static const MCPhysReg MSA128B[] = { - Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, }; // MSA128B Bit set. static const uint8_t MSA128BBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // MSA128D Register Class... static const MCPhysReg MSA128D[] = { - Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, }; // MSA128D Bit set. static const uint8_t MSA128DBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // MSA128H Register Class... static const MCPhysReg MSA128H[] = { - Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, }; // MSA128H Bit set. static const uint8_t MSA128HBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // MSA128W Register Class... static const MCPhysReg MSA128W[] = { - Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, }; // MSA128W Bit set. static const uint8_t MSA128WBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, - }; - - // MSA128B_with_sub_64_in_OddSP Register Class... - static const MCPhysReg MSA128B_with_sub_64_in_OddSP[] = { - Mips_W1, Mips_W3, Mips_W5, Mips_W7, Mips_W9, Mips_W11, Mips_W13, Mips_W15, Mips_W17, Mips_W19, Mips_W21, Mips_W23, Mips_W25, Mips_W27, Mips_W29, Mips_W31, - }; - - // MSA128B_with_sub_64_in_OddSP Bit set. - static const uint8_t MSA128B_with_sub_64_in_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // MSA128WEvens Register Class... static const MCPhysReg MSA128WEvens[] = { - Mips_W0, Mips_W2, Mips_W4, Mips_W6, Mips_W8, Mips_W10, Mips_W12, Mips_W14, Mips_W16, Mips_W18, Mips_W20, Mips_W22, Mips_W24, Mips_W26, Mips_W28, Mips_W30, + Mips_W0, Mips_W2, Mips_W4, Mips_W6, Mips_W8, Mips_W10, Mips_W12, Mips_W14, Mips_W16, Mips_W18, Mips_W20, Mips_W22, Mips_W24, Mips_W26, Mips_W28, Mips_W30, }; // MSA128WEvens Bit set. static const uint8_t MSA128WEvensBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, }; // ACC128 Register Class... static const MCPhysReg ACC128[] = { - Mips_AC0_64, + Mips_AC0_64, }; // ACC128 Bit set. static const uint8_t ACC128Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, }; static const MCRegisterClass MipsMCRegisterClasses[] = { - { OddSP, OddSPBits, sizeof(OddSPBits) }, + { MSA128F16, MSA128F16Bits, sizeof(MSA128F16Bits) }, + { COP0Sel, COP0SelBits, sizeof(COP0SelBits) }, { CCR, CCRBits, sizeof(CCRBits) }, + { COP0, COP0Bits, sizeof(COP0Bits) }, { COP2, COP2Bits, sizeof(COP2Bits) }, { COP3, COP3Bits, sizeof(COP3Bits) }, { DSPR, DSPRBits, sizeof(DSPRBits) }, { FGR32, FGR32Bits, sizeof(FGR32Bits) }, { FGRCC, FGRCCBits, sizeof(FGRCCBits) }, - { FGRH32, FGRH32Bits, sizeof(FGRH32Bits) }, { GPR32, GPR32Bits, sizeof(GPR32Bits) }, + { GPRNM32, GPRNM32Bits, sizeof(GPRNM32Bits) }, { HWRegs, HWRegsBits, sizeof(HWRegsBits) }, - { OddSP_with_sub_hi, OddSP_with_sub_hiBits, sizeof(OddSP_with_sub_hiBits) }, - { FGR32_and_OddSP, FGR32_and_OddSPBits, sizeof(FGR32_and_OddSPBits) }, - { FGRH32_and_OddSP, FGRH32_and_OddSPBits, sizeof(FGRH32_and_OddSPBits) }, - { OddSP_with_sub_hi_with_sub_hi_in_FGRH32, OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits) }, + { MSACtrl, MSACtrlBits, sizeof(MSACtrlBits) }, + { GPR32NONZERO, GPR32NONZEROBits, sizeof(GPR32NONZEROBits) }, + { GPRNM32NZ, GPRNM32NZBits, sizeof(GPRNM32NZBits) }, + { GPRNM32_TAIL, GPRNM32_TAILBits, sizeof(GPRNM32_TAILBits) }, + { GPRNM4, GPRNM4Bits, sizeof(GPRNM4Bits) }, + { GPRNM4Z, GPRNM4ZBits, sizeof(GPRNM4ZBits) }, + { GPRNM4_and_GPRNM4Z, GPRNM4_and_GPRNM4ZBits, sizeof(GPRNM4_and_GPRNM4ZBits) }, { CPU16RegsPlusSP, CPU16RegsPlusSPBits, sizeof(CPU16RegsPlusSPBits) }, - { CC, CCBits, sizeof(CCBits) }, { CPU16Regs, CPU16RegsBits, sizeof(CPU16RegsBits) }, { FCC, FCCBits, sizeof(FCCBits) }, { GPRMM16, GPRMM16Bits, sizeof(GPRMM16Bits) }, { GPRMM16MoveP, GPRMM16MovePBits, sizeof(GPRMM16MovePBits) }, { GPRMM16Zero, GPRMM16ZeroBits, sizeof(GPRMM16ZeroBits) }, - { MSACtrl, MSACtrlBits, sizeof(MSACtrlBits) }, - { OddSP_with_sub_hi_with_sub_hi_in_FGR32, OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits) }, + { GPRNM3, GPRNM3Bits, sizeof(GPRNM3Bits) }, + { GPRNM3Z, GPRNM3ZBits, sizeof(GPRNM3ZBits) }, + { GPRNM4_and_GPRNM32_TAIL, GPRNM4_and_GPRNM32_TAILBits, sizeof(GPRNM4_and_GPRNM32_TAILBits) }, { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, sizeof(CPU16Regs_and_GPRMM16ZeroBits) }, + { GPR32NONZERO_and_GPRMM16MoveP, GPR32NONZERO_and_GPRMM16MovePBits, sizeof(GPR32NONZERO_and_GPRMM16MovePBits) }, + { GPRNM3_and_GPRNM3Z, GPRNM3_and_GPRNM3ZBits, sizeof(GPRNM3_and_GPRNM3ZBits) }, + { GPRNM4Z_and_GPRNM32_TAIL, GPRNM4Z_and_GPRNM32_TAILBits, sizeof(GPRNM4Z_and_GPRNM32_TAILBits) }, + { GPRMM16MovePPairSecond, GPRMM16MovePPairSecondBits, sizeof(GPRMM16MovePPairSecondBits) }, { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, sizeof(CPU16Regs_and_GPRMM16MovePBits) }, { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits) }, + { GPRNM2R1, GPRNM2R1Bits, sizeof(GPRNM2R1Bits) }, + { GPRNM2R2, GPRNM2R2Bits, sizeof(GPRNM2R2Bits) }, { HI32DSP, HI32DSPBits, sizeof(HI32DSPBits) }, { LO32DSP, LO32DSPBits, sizeof(LO32DSPBits) }, + { CPU16Regs_and_GPRMM16MovePPairSecond, CPU16Regs_and_GPRMM16MovePPairSecondBits, sizeof(CPU16Regs_and_GPRMM16MovePPairSecondBits) }, + { GPRMM16MovePPairFirst, GPRMM16MovePPairFirstBits, sizeof(GPRMM16MovePPairFirstBits) }, { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits) }, + { GPRNM2R1_and_GPRNM2R2, GPRNM2R1_and_GPRNM2R2Bits, sizeof(GPRNM2R1_and_GPRNM2R2Bits) }, + { GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, sizeof(GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits) }, + { GPRNM1R1, GPRNM1R1Bits, sizeof(GPRNM1R1Bits) }, { CPURAReg, CPURARegBits, sizeof(CPURARegBits) }, { CPUSPReg, CPUSPRegBits, sizeof(CPUSPRegBits) }, { DSPCC, DSPCCBits, sizeof(DSPCCBits) }, + { GP32, GP32Bits, sizeof(GP32Bits) }, + { GPR32ZERO, GPR32ZEROBits, sizeof(GPR32ZEROBits) }, + { GPRNM1R1_and_GPRNM2R2, GPRNM1R1_and_GPRNM2R2Bits, sizeof(GPRNM1R1_and_GPRNM2R2Bits) }, + { GPRNMGP, GPRNMGPBits, sizeof(GPRNMGPBits) }, + { GPRNMRA, GPRNMRABits, sizeof(GPRNMRABits) }, + { GPRNMSP, GPRNMSPBits, sizeof(GPRNMSPBits) }, { HI32, HI32Bits, sizeof(HI32Bits) }, { LO32, LO32Bits, sizeof(LO32Bits) }, + { SP32, SP32Bits, sizeof(SP32Bits) }, { FGR64, FGR64Bits, sizeof(FGR64Bits) }, { GPR64, GPR64Bits, sizeof(GPR64Bits) }, + { GPR64_with_sub_32_in_GPR32NONZERO, GPR64_with_sub_32_in_GPR32NONZEROBits, sizeof(GPR64_with_sub_32_in_GPR32NONZEROBits) }, { AFGR64, AFGR64Bits, sizeof(AFGR64Bits) }, - { FGR64_and_OddSP, FGR64_and_OddSPBits, sizeof(FGR64_and_OddSPBits) }, { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits) }, - { AFGR64_and_OddSP, AFGR64_and_OddSPBits, sizeof(AFGR64_and_OddSPBits) }, { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, sizeof(GPR64_with_sub_32_in_CPU16RegsBits) }, { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits) }, { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits) }, { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits) }, + { GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP, GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits, sizeof(GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits) }, + { GPR64_with_sub_32_in_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits) }, { ACC64DSP, ACC64DSPBits, sizeof(ACC64DSPBits) }, { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits) }, { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits) }, + { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits) }, + { GPR64_with_sub_32_in_GPRMM16MovePPairFirst, GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits) }, { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits) }, { OCTEON_MPL, OCTEON_MPLBits, sizeof(OCTEON_MPLBits) }, { OCTEON_P, OCTEON_PBits, sizeof(OCTEON_PBits) }, + { GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits) }, { ACC64, ACC64Bits, sizeof(ACC64Bits) }, + { GP64, GP64Bits, sizeof(GP64Bits) }, { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, sizeof(GPR64_with_sub_32_in_CPURARegBits) }, - { GPR64_with_sub_32_in_CPUSPReg, GPR64_with_sub_32_in_CPUSPRegBits, sizeof(GPR64_with_sub_32_in_CPUSPRegBits) }, + { GPR64_with_sub_32_in_GPR32ZERO, GPR64_with_sub_32_in_GPR32ZEROBits, sizeof(GPR64_with_sub_32_in_GPR32ZEROBits) }, { HI64, HI64Bits, sizeof(HI64Bits) }, { LO64, LO64Bits, sizeof(LO64Bits) }, + { SP64, SP64Bits, sizeof(SP64Bits) }, { MSA128B, MSA128BBits, sizeof(MSA128BBits) }, { MSA128D, MSA128DBits, sizeof(MSA128DBits) }, { MSA128H, MSA128HBits, sizeof(MSA128HBits) }, { MSA128W, MSA128WBits, sizeof(MSA128WBits) }, - { MSA128B_with_sub_64_in_OddSP, MSA128B_with_sub_64_in_OddSPBits, sizeof(MSA128B_with_sub_64_in_OddSPBits) }, { MSA128WEvens, MSA128WEvensBits, sizeof(MSA128WEvensBits) }, { ACC128, ACC128Bits, sizeof(ACC128Bits) }, }; -#endif // GET_REGINFO_MC_DESC \ No newline at end of file +static const uint16_t MipsRegEncodingTable[] = { + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 30, + 30, + 28, + 28, + 2, + 1, + 0, + 6, + 4, + 5, + 3, + 7, + 0, + 31, + 31, + 29, + 29, + 0, + 0, + 4, + 5, + 6, + 7, + 0, + 1, + 2, + 3, + 1, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 0, + 2, + 4, + 6, + 8, + 10, + 12, + 14, + 16, + 18, + 20, + 22, + 24, + 26, + 28, + 30, + 0, + 0, + 0, + 0, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 30, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 28, + 0, + 1, + 2, + 3, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 26, + 27, + 0, + 1, + 2, + 3, + 0, + 1, + 2, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 0, + 1, + 2, + 31, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 29, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 24, + 25, + 2, + 3, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 0, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 257, + 258, + 259, + 256, + 484, + 864, + 416, + 482, + 483, + 352, + 512, + 128, + 129, + 288, + 931, + 899, + 736, + 132, + 768, + 992, + 930, + 898, + 481, + 320, + 448, + 832, + 960, + 97, + 391, + 224, + 929, + 897, + 0, + 385, + 928, + 896, + 544, + 545, + 546, + 133, + 1, + 450, + 421, + 161, + 160, + 480, + 165, + 198, + 166, + 167, + 32, + 386, + 387, + 384, + 66, + 69, + 68, + 103, + 67, + 70, + 71, + 65, + 737, + 741, + 740, + 130, + 388, + 420, + 4, + 33, + 39, + 37, + 38, + 192, + 640, + 131, + 36, + 26, + 27, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 12, + 13, + 14, + 15, + 2, + 3, + 24, + 25, + 4, + 5, + 6, + 7, + 0, + 513, + 514, + 515, + 516, + 517, + 742, + 64, + 96, + 390, + 324, + 325, + 326, + 994, + 995, + 996, + 997, + 998, + 999, + 2, + 3, + 801, + 803, + 805, + 807, + 809, + 811, + 813, + 815, + 800, + 802, + 804, + 806, + 808, + 810, + 812, + 814, + 162, + 163, + 164, + 193, + 194, + 195, + 196, + 197, + 389, + 738, + 770, + 739, + 771, + 34, + 35, + 608, + 609, + 610, + 611, + 612, + 613, + 614, + 615, + 616, + 617, + 618, + 619, + 620, + 621, + 622, + 623, + 576, + 577, + 578, + 579, + 580, + 581, + 582, + 583, + 584, + 585, + 586, + 587, + 588, + 589, + 590, + 591, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 0, + 0, + 26, + 27, + 0, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 24, + 25, + 2, + 3, + 356, +}; +#endif // GET_REGINFO_MC_DESC + + + diff --git a/arch/Mips/MipsGenSubtargetInfo.inc b/arch/Mips/MipsGenSubtargetInfo.inc index 36e7a7f866..8501cd9e29 100644 --- a/arch/Mips/MipsGenSubtargetInfo.inc +++ b/arch/Mips/MipsGenSubtargetInfo.inc @@ -1,52 +1,83 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|*Subtarget Enumeration Source Fragment *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* LLVM-commit: */ +/* LLVM-tag: */ +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ #ifdef GET_SUBTARGETINFO_ENUM #undef GET_SUBTARGETINFO_ENUM -#define Mips_FeatureCnMips (1ULL << 0) -#define Mips_FeatureDSP (1ULL << 1) -#define Mips_FeatureDSPR2 (1ULL << 2) -#define Mips_FeatureFP64Bit (1ULL << 3) -#define Mips_FeatureFPXX (1ULL << 4) -#define Mips_FeatureGP64Bit (1ULL << 5) -#define Mips_FeatureMSA (1ULL << 6) -#define Mips_FeatureMicroMips (1ULL << 7) -#define Mips_FeatureMips1 (1ULL << 8) -#define Mips_FeatureMips2 (1ULL << 9) -#define Mips_FeatureMips3 (1ULL << 10) -#define Mips_FeatureMips3_32 (1ULL << 11) -#define Mips_FeatureMips3_32r2 (1ULL << 12) -#define Mips_FeatureMips4 (1ULL << 13) -#define Mips_FeatureMips4_32 (1ULL << 14) -#define Mips_FeatureMips4_32r2 (1ULL << 15) -#define Mips_FeatureMips5 (1ULL << 16) -#define Mips_FeatureMips5_32r2 (1ULL << 17) -#define Mips_FeatureMips16 (1ULL << 18) -#define Mips_FeatureMips32 (1ULL << 19) -#define Mips_FeatureMips32r2 (1ULL << 20) -#define Mips_FeatureMips32r3 (1ULL << 21) -#define Mips_FeatureMips32r5 (1ULL << 22) -#define Mips_FeatureMips32r6 (1ULL << 23) -#define Mips_FeatureMips64 (1ULL << 24) -#define Mips_FeatureMips64r2 (1ULL << 25) -#define Mips_FeatureMips64r3 (1ULL << 26) -#define Mips_FeatureMips64r5 (1ULL << 27) -#define Mips_FeatureMips64r6 (1ULL << 28) -#define Mips_FeatureNaN2008 (1ULL << 29) -#define Mips_FeatureNoABICalls (1ULL << 30) -#define Mips_FeatureNoOddSPReg (1ULL << 31) -#define Mips_FeatureSingleFloat (1ULL << 32) -#define Mips_FeatureVFPU (1ULL << 33) - +enum { + Mips_FeatureAbs2008 = 0, + Mips_FeatureCRC = 1, + Mips_FeatureCnMips = 2, + Mips_FeatureCnMipsP = 3, + Mips_FeatureDSP = 4, + Mips_FeatureDSPR2 = 5, + Mips_FeatureDSPR3 = 6, + Mips_FeatureEVA = 7, + Mips_FeatureFP64Bit = 8, + Mips_FeatureFPXX = 9, + Mips_FeatureGINV = 10, + Mips_FeatureGP64Bit = 11, + Mips_FeatureI7200 = 12, + Mips_FeatureLongCalls = 13, + Mips_FeatureMSA = 14, + Mips_FeatureMT = 15, + Mips_FeatureMicroMips = 16, + Mips_FeatureMips1 = 17, + Mips_FeatureMips2 = 18, + Mips_FeatureMips3 = 19, + Mips_FeatureMips3D = 20, + Mips_FeatureMips3_32 = 21, + Mips_FeatureMips3_32r2 = 22, + Mips_FeatureMips4 = 23, + Mips_FeatureMips4_32 = 24, + Mips_FeatureMips4_32r2 = 25, + Mips_FeatureMips5 = 26, + Mips_FeatureMips5_32r2 = 27, + Mips_FeatureMips16 = 28, + Mips_FeatureMips32 = 29, + Mips_FeatureMips32r2 = 30, + Mips_FeatureMips32r3 = 31, + Mips_FeatureMips32r5 = 32, + Mips_FeatureMips32r6 = 33, + Mips_FeatureMips64 = 34, + Mips_FeatureMips64r2 = 35, + Mips_FeatureMips64r3 = 36, + Mips_FeatureMips64r5 = 37, + Mips_FeatureMips64r6 = 38, + Mips_FeatureNMS1 = 39, + Mips_FeatureNaN2008 = 40, + Mips_FeatureNanoMips = 41, + Mips_FeatureNoABICalls = 42, + Mips_FeatureNoMadd4 = 43, + Mips_FeatureNoOddSPReg = 44, + Mips_FeaturePCRel = 45, + Mips_FeaturePTR64Bit = 46, + Mips_FeatureRelax = 47, + Mips_FeatureSingleFloat = 48, + Mips_FeatureSoftFloat = 49, + Mips_FeatureSym32 = 50, + Mips_FeatureTLB = 51, + Mips_FeatureUseAbsoluteJumpTables = 52, + Mips_FeatureUseIndirectJumpsHazard = 53, + Mips_FeatureUseTCCInDIV = 54, + Mips_FeatureVFPU = 55, + Mips_FeatureVirt = 56, + Mips_FeatureXGOT = 57, + Mips_FeatureXformHw110880 = 58, + Mips_ImplP5600 = 59, + Mips_NumSubtargetFeatures = 60 +}; #endif // GET_SUBTARGETINFO_ENUM + + diff --git a/arch/Mips/MipsInstPrinter.c b/arch/Mips/MipsInstPrinter.c index 9b00ad9248..eda8062946 100644 --- a/arch/Mips/MipsInstPrinter.c +++ b/arch/Mips/MipsInstPrinter.c @@ -1,9 +1,22 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically translated source file from LLVM. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Only small edits allowed. */ +/* For multiple similar edits, please create a Patch for the translator. */ + +/* Capstone's C++ file translator: */ +/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ + //===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -11,251 +24,257 @@ // //===----------------------------------------------------------------------===// -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ - -#ifdef CAPSTONE_HAS_MIPS - -#include -#include -#include // debug +#include #include +#include +#include -#include "MipsInstPrinter.h" -#include "../../MCInst.h" -#include "../../utils.h" -#include "../../SStream.h" -#include "../../MCRegisterInfo.h" #include "MipsMapping.h" - #include "MipsInstPrinter.h" -static void printUnsignedImm(MCInst *MI, int opNum, SStream *O); -static char *printAliasInstr(MCInst *MI, SStream *O, void *info); -static char *printAlias(MCInst *MI, SStream *OS); - -// These enumeration declarations were originally in MipsInstrInfo.h but -// had to be moved here to avoid circular dependencies between -// LLVMMipsCodeGen and LLVMMipsAsmPrinter. - -// Mips Condition Codes -typedef enum Mips_CondCode { - // To be used with float branch True - Mips_FCOND_F, - Mips_FCOND_UN, - Mips_FCOND_OEQ, - Mips_FCOND_UEQ, - Mips_FCOND_OLT, - Mips_FCOND_ULT, - Mips_FCOND_OLE, - Mips_FCOND_ULE, - Mips_FCOND_SF, - Mips_FCOND_NGLE, - Mips_FCOND_SEQ, - Mips_FCOND_NGL, - Mips_FCOND_LT, - Mips_FCOND_NGE, - Mips_FCOND_LE, - Mips_FCOND_NGT, - - // To be used with float branch False - // This conditions have the same mnemonic as the - // above ones, but are used with a branch False; - Mips_FCOND_T, - Mips_FCOND_OR, - Mips_FCOND_UNE, - Mips_FCOND_ONE, - Mips_FCOND_UGE, - Mips_FCOND_OGE, - Mips_FCOND_UGT, - Mips_FCOND_OGT, - Mips_FCOND_ST, - Mips_FCOND_GLE, - Mips_FCOND_SNE, - Mips_FCOND_GL, - Mips_FCOND_NLT, - Mips_FCOND_GE, - Mips_FCOND_NLE, - Mips_FCOND_GT -} Mips_CondCode; +#define GET_SUBTARGETINFO_ENUM +#include "MipsGenSubtargetInfo.inc" #define GET_INSTRINFO_ENUM #include "MipsGenInstrInfo.inc" -static const char *getRegisterName(unsigned RegNo); -static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI); +#define GET_REGINFO_ENUM +#include "MipsGenRegisterInfo.inc" -static void set_mem_access(MCInst *MI, bool status) -{ - MI->csh->doing_mem = status; +#define CONCAT(a, b) CONCAT_(a, b) +#define CONCAT_(a, b) a##_##b - if (MI->csh->detail_opt != CS_OPT_ON) - return; +#define DEBUG_TYPE "asm-printer" - if (status) { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_MEM; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = MIPS_REG_INVALID; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = 0; - } else { - // done, create the next operand slot - MI->flat_insn->detail->mips.op_count++; - } -} +#define PRINT_ALIAS_INSTR +#include "MipsGenAsmWriter.inc" -static bool isReg(MCInst *MI, unsigned OpNo, unsigned R) +static bool isReg(const MCInst *MI, unsigned OpNo, unsigned R) { - return (MCOperand_isReg(MCInst_getOperand(MI, OpNo)) && - MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == R); + return MCOperand_getReg(MCInst_getOperand((MCInst *)MI, (OpNo))) == R; } -static const char* MipsFCCToString(Mips_CondCode CC) +static const char *MipsFCCToString(Mips_CondCode CC) { switch (CC) { - default: return 0; // never reach - case Mips_FCOND_F: - case Mips_FCOND_T: return "f"; - case Mips_FCOND_UN: - case Mips_FCOND_OR: return "un"; - case Mips_FCOND_OEQ: - case Mips_FCOND_UNE: return "eq"; - case Mips_FCOND_UEQ: - case Mips_FCOND_ONE: return "ueq"; - case Mips_FCOND_OLT: - case Mips_FCOND_UGE: return "olt"; - case Mips_FCOND_ULT: - case Mips_FCOND_OGE: return "ult"; - case Mips_FCOND_OLE: - case Mips_FCOND_UGT: return "ole"; - case Mips_FCOND_ULE: - case Mips_FCOND_OGT: return "ule"; - case Mips_FCOND_SF: - case Mips_FCOND_ST: return "sf"; - case Mips_FCOND_NGLE: - case Mips_FCOND_GLE: return "ngle"; - case Mips_FCOND_SEQ: - case Mips_FCOND_SNE: return "seq"; - case Mips_FCOND_NGL: - case Mips_FCOND_GL: return "ngl"; - case Mips_FCOND_LT: - case Mips_FCOND_NLT: return "lt"; - case Mips_FCOND_NGE: - case Mips_FCOND_GE: return "nge"; - case Mips_FCOND_LE: - case Mips_FCOND_NLE: return "le"; - case Mips_FCOND_NGT: - case Mips_FCOND_GT: return "ngt"; + case Mips_FCOND_F: + case Mips_FCOND_T: + return "f"; + case Mips_FCOND_UN: + case Mips_FCOND_OR: + return "un"; + case Mips_FCOND_OEQ: + case Mips_FCOND_UNE: + return "eq"; + case Mips_FCOND_UEQ: + case Mips_FCOND_ONE: + return "ueq"; + case Mips_FCOND_OLT: + case Mips_FCOND_UGE: + return "olt"; + case Mips_FCOND_ULT: + case Mips_FCOND_OGE: + return "ult"; + case Mips_FCOND_OLE: + case Mips_FCOND_UGT: + return "ole"; + case Mips_FCOND_ULE: + case Mips_FCOND_OGT: + return "ule"; + case Mips_FCOND_SF: + case Mips_FCOND_ST: + return "sf"; + case Mips_FCOND_NGLE: + case Mips_FCOND_GLE: + return "ngle"; + case Mips_FCOND_SEQ: + case Mips_FCOND_SNE: + return "seq"; + case Mips_FCOND_NGL: + case Mips_FCOND_GL: + return "ngl"; + case Mips_FCOND_LT: + case Mips_FCOND_NLT: + return "lt"; + case Mips_FCOND_NGE: + case Mips_FCOND_GE: + return "nge"; + case Mips_FCOND_LE: + case Mips_FCOND_NLE: + return "le"; + case Mips_FCOND_NGT: + case Mips_FCOND_GT: + return "ngt"; } + assert(0 && "Impossible condition code!"); + return ""; } -static void printRegName(SStream *OS, unsigned RegNo) -{ - SStream_concat(OS, "$%s", getRegisterName(RegNo)); -} +const char *Mips_LLVM_getRegisterName(unsigned RegNo, bool noRegName); -void Mips_printInst(MCInst *MI, SStream *O, void *info) +static void printRegName(MCInst *MI, SStream *OS, MCRegister Reg) { - char *mnem; + int syntax_opt = MI->csh->syntax; + if (!(syntax_opt & CS_OPT_SYNTAX_NO_DOLLAR)) { + SStream_concat1(OS, '$'); + } + SStream_concat0(OS, Mips_LLVM_getRegisterName(Reg, syntax_opt & CS_OPT_SYNTAX_NOREGNAME)); +} - switch (MCInst_getOpcode(MI)) { - default: break; - case Mips_Save16: - case Mips_SaveX16: - case Mips_Restore16: - case Mips_RestoreX16: - return; +void Mips_LLVM_printInst(MCInst *MI, uint64_t Address, SStream *O) { + bool useAliasDetails = map_use_alias_details(MI); + if (!useAliasDetails) { + SStream_Close(O); + printInstruction(MI, Address, O); + SStream_Open(O); + map_set_fill_detail_ops(MI, false); } - // Try to print any aliases first. - mnem = printAliasInstr(MI, O, info); - if (!mnem) { - mnem = printAlias(MI, O); - if (!mnem) { - printInstruction(MI, O, NULL); - } + if (printAliasInstr(MI, Address, O) || + printAlias4(MI, Address, O)) { + MCInst_setIsAlias(MI, true); + } else { + printInstruction(MI, Address, O); } - if (mnem) { - // fixup instruction id due to the change in alias instruction - MCInst_setOpcodePub(MI, Mips_map_insn(mnem)); - cs_mem_free(mnem); + if (!useAliasDetails) { + map_set_fill_detail_ops(MI, true); } } -static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) +void printOperand(MCInst *MI, unsigned OpNo, SStream *O) { - MCOperand *Op; + switch (MCInst_getOpcode(MI)) { + default: + break; + case Mips_AND16_NM: + case Mips_XOR16_NM: + case Mips_OR16_NM: + if (MCInst_getNumOperands(MI) == 2 && OpNo == 2) + OpNo = 0; // rt, rs -> rt, rs, rt + break; + case Mips_ADDu4x4_NM: + case Mips_MUL4x4_NM: + if (MCInst_getNumOperands(MI) == 2 && OpNo > 0) + OpNo = OpNo - 1; // rt, rs -> rt, rt, rs + break; + } - if (OpNo >= MI->size) + MCOperand *Op = MCInst_getOperand(MI, (OpNo)); + if (MCOperand_isReg(Op)) { + add_cs_detail(MI, Mips_OP_GROUP_Operand, OpNo); + printRegName(MI, O, MCOperand_getReg(Op)); return; + } - Op = MCInst_getOperand(MI, OpNo); - if (MCOperand_isReg(Op)) { - unsigned int reg = MCOperand_getReg(Op); - printRegName(O, reg); - reg = Mips_map_register(reg); - if (MI->csh->detail_opt) { - if (MI->csh->doing_mem) { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = reg; - } else { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg; - MI->flat_insn->detail->mips.op_count++; - } - } - } else if (MCOperand_isImm(Op)) { - int64_t imm = MCOperand_getImm(Op); - if (MI->csh->doing_mem) { - if (imm) { // only print Imm offset if it is not 0 - printInt64(O, imm); - } - if (MI->csh->detail_opt) - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm; - } else { - printInt64(O, imm); - - if (MI->csh->detail_opt) { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm; - MI->flat_insn->detail->mips.op_count++; - } + + if (MCOperand_isImm(Op)) { + switch (MCInst_getOpcode(MI)) { + case Mips_LI48_NM: + case Mips_ANDI16_NM: + case Mips_ANDI_NM: + case Mips_ORI_NM: + case Mips_XORI_NM: + case Mips_TEQ_NM: + case Mips_TNE_NM: + case Mips_SIGRIE_NM: + case Mips_SDBBP_NM: + case Mips_SDBBP16_NM: + case Mips_BREAK_NM: + case Mips_BREAK16_NM: + case Mips_SYSCALL_NM: + case Mips_SYSCALL16_NM: + case Mips_WAIT_NM: + CONCAT(printUImm, CONCAT(32, 0)) + (MI, OpNo, O); + break; + default: + add_cs_detail(MI, Mips_OP_GROUP_Operand, OpNo); + printInt64(O, MCOperand_getImm(Op)); + break; } + return; } } -static void printUnsignedImm(MCInst *MI, int opNum, SStream *O) +static void printJumpOperand(MCInst *MI, unsigned OpNo, SStream *O) { - MCOperand *MO = MCInst_getOperand(MI, opNum); - if (MCOperand_isImm(MO)) { - int64_t imm = MCOperand_getImm(MO); - printInt64(O, imm); + add_cs_detail(MI, Mips_OP_GROUP_JumpOperand, OpNo); + MCOperand *Op = MCInst_getOperand(MI, (OpNo)); + if (MCOperand_isReg(Op)) + return printRegName(MI, O, MCOperand_getReg(Op)); - if (MI->csh->detail_opt) { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = (unsigned short int)imm; - MI->flat_insn->detail->mips.op_count++; - } - } else - printOperand(MI, opNum, O); + printInt64(O, MCOperand_getImm(Op)); } -static void printUnsignedImm8(MCInst *MI, int opNum, SStream *O) +static void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo, SStream *O) { - MCOperand *MO = MCInst_getOperand(MI, opNum); - if (MCOperand_isImm(MO)) { - uint8_t imm = (uint8_t)MCOperand_getImm(MO); - if (imm > HEX_THRESHOLD) - SStream_concat(O, "0x%x", imm); - else - SStream_concat(O, "%u", imm); - if (MI->csh->detail_opt) { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm; - MI->flat_insn->detail->mips.op_count++; - } - } else - printOperand(MI, opNum, O); + add_cs_detail(MI, Mips_OP_GROUP_BranchOperand, OpNo); + MCOperand *Op = MCInst_getOperand(MI, (OpNo)); + if (MCOperand_isReg(Op)) + return printRegName(MI, O, MCOperand_getReg(Op)); + + uint64_t Target = Address + MCOperand_getImm(Op); + printInt64(O, Target); } +#define DEFINE_printUImm(Bits) \ + static void CONCAT(printUImm, CONCAT(Bits, 0))(MCInst * MI, int opNum, \ + SStream *O) \ + { \ + add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), opNum); \ + MCOperand *MO = MCInst_getOperand(MI, (opNum)); \ + if (MCOperand_isImm(MO)) { \ + uint64_t Imm = MCOperand_getImm(MO); \ + Imm &= (((uint64_t)1) << Bits) - 1; \ + printUInt64(O, Imm); \ + return; \ + } \ + MCOperand *Op = MCInst_getOperand(MI, (opNum)); \ + printRegName(MI, O, MCOperand_getReg(Op)); \ + } + +#define DEFINE_printUImm_2(Bits, Offset) \ + static void CONCAT(printUImm, CONCAT(Bits, Offset))(MCInst * MI, int opNum, \ + SStream *O) \ + { \ + add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, Offset)), \ + opNum); \ + MCOperand *MO = MCInst_getOperand(MI, (opNum)); \ + if (MCOperand_isImm(MO)) { \ + uint64_t Imm = MCOperand_getImm(MO); \ + Imm -= Offset; \ + Imm &= (1 << Bits) - 1; \ + Imm += Offset; \ + printUInt64(O, Imm); \ + return; \ + } \ + MCOperand *Op = MCInst_getOperand(MI, (opNum)); \ + printRegName(MI, O, MCOperand_getReg(Op)); \ + } + +DEFINE_printUImm(0); +DEFINE_printUImm(1); +DEFINE_printUImm(10); +DEFINE_printUImm(12); +DEFINE_printUImm(16); +DEFINE_printUImm(2); +DEFINE_printUImm(20); +DEFINE_printUImm(26); +DEFINE_printUImm(3); +DEFINE_printUImm(32); +DEFINE_printUImm(4); +DEFINE_printUImm(5); +DEFINE_printUImm(6); +DEFINE_printUImm(7); +DEFINE_printUImm(8); +DEFINE_printUImm_2(2, 1); +DEFINE_printUImm_2(5, 1); +DEFINE_printUImm_2(5, 32); +DEFINE_printUImm_2(5, 33); +DEFINE_printUImm_2(6, 1); +DEFINE_printUImm_2(6, 2); + static void printMemOperand(MCInst *MI, int opNum, SStream *O) { // Load/Store memory operands -- imm($reg) @@ -265,160 +284,348 @@ static void printMemOperand(MCInst *MI, int opNum, SStream *O) // opNum can be invalid if instruction had reglist as operand. // MemOperand is always last operand of instruction (base + offset). switch (MCInst_getOpcode(MI)) { - default: - break; - case Mips_SWM32_MM: - case Mips_LWM32_MM: - case Mips_SWM16_MM: - case Mips_LWM16_MM: - opNum = MCInst_getNumOperands(MI) - 2; - break; + default: + break; + case Mips_SWM32_MM: + case Mips_LWM32_MM: + case Mips_SWM16_MM: + case Mips_SWM16_MMR6: + case Mips_LWM16_MM: + case Mips_LWM16_MMR6: + opNum = MCInst_getNumOperands(MI) - 2; + break; } set_mem_access(MI, true); - printOperand(MI, opNum + 1, O); + // Index register is encoded as immediate value + // in case of nanoMIPS indexed instructions + switch (MCInst_getOpcode(MI)) { + // No offset needed for paired LL/SC + case Mips_LLWP_NM: + case Mips_SCWP_NM: + break; + case Mips_LWX_NM: + case Mips_LWXS_NM: + case Mips_LWXS16_NM: + case Mips_LBX_NM: + case Mips_LBUX_NM: + case Mips_LHX_NM: + case Mips_LHUX_NM: + case Mips_LHXS_NM: + case Mips_LHUXS_NM: + case Mips_SWX_NM: + case Mips_SWXS_NM: + case Mips_SBX_NM: + case Mips_SHX_NM: + case Mips_SHXS_NM: + if (!MCOperand_isReg(MCInst_getOperand(MI, (opNum + 1)))) { + add_cs_detail(MI, Mips_OP_GROUP_MemOperand, (opNum + 1)); + printRegName(MI, O, MCOperand_getImm(MCInst_getOperand( + MI, (opNum + 1)))); + break; + } + // Fall through + default: + printOperand((MCInst *)MI, opNum + 1, O); + break; + } SStream_concat0(O, "("); - printOperand(MI, opNum, O); + printOperand((MCInst *)MI, opNum, O); SStream_concat0(O, ")"); set_mem_access(MI, false); } -// TODO??? static void printMemOperandEA(MCInst *MI, int opNum, SStream *O) { // when using stack locations for not load/store instructions // print the same way as all normal 3 operand instructions. - printOperand(MI, opNum, O); + printOperand((MCInst *)MI, opNum, O); SStream_concat0(O, ", "); - printOperand(MI, opNum + 1, O); - return; + printOperand((MCInst *)MI, opNum + 1, O); } static void printFCCOperand(MCInst *MI, int opNum, SStream *O) { - MCOperand *MO = MCInst_getOperand(MI, opNum); - SStream_concat0(O, MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO))); + MCOperand *MO = MCInst_getOperand(MI, (opNum)); + SStream_concat0(O, + MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO))); } -static void printRegisterPair(MCInst *MI, int opNum, SStream *O) +static bool printAlias(const char *Str, const MCInst *MI, uint64_t Address, + unsigned OpNo, SStream *OS, bool IsBranch) { - printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, opNum))); + SStream_concat(OS, "%s%s", "\t", Str); + SStream_concat0(OS, "\t"); + if (IsBranch) + printBranchOperand((MCInst *)MI, Address, OpNo, OS); + else + printOperand((MCInst *)MI, OpNo, OS); + return true; } -static char *printAlias1(const char *Str, MCInst *MI, unsigned OpNo, SStream *OS) +static bool printAlias2(const char *Str, const MCInst *MI, uint64_t Address, + unsigned OpNo0, unsigned OpNo1, SStream *OS, bool IsBranch) { - SStream_concat(OS, "%s\t", Str); - printOperand(MI, OpNo, OS); - return cs_strdup(Str); + printAlias(Str, MI, Address, OpNo0, OS, IsBranch); + SStream_concat0(OS, ", "); + if (IsBranch) + printBranchOperand((MCInst *)MI, Address, OpNo1, OS); + else + printOperand((MCInst *)MI, OpNo1, OS); + return true; } -static char *printAlias2(const char *Str, MCInst *MI, - unsigned OpNo0, unsigned OpNo1, SStream *OS) +static bool printAlias3(const char *Str, const MCInst *MI, uint64_t Address, + unsigned OpNo0, unsigned OpNo1, unsigned OpNo2, SStream *OS) { - char *tmp; - - tmp = printAlias1(Str, MI, OpNo0, OS); + printAlias(Str, MI, Address, OpNo0, OS, false); SStream_concat0(OS, ", "); - printOperand(MI, OpNo1, OS); - - return tmp; + printOperand((MCInst *)MI, OpNo1, OS); + SStream_concat0(OS, ", "); + printOperand((MCInst *)MI, OpNo2, OS); + return true; } -#define GET_REGINFO_ENUM -#include "MipsGenRegisterInfo.inc" - -static char *printAlias(MCInst *MI, SStream *OS) +static bool printAlias4(const MCInst *MI, uint64_t Address, SStream *OS) { switch (MCInst_getOpcode(MI)) { - case Mips_BEQ: - case Mips_BEQ_MM: - // beq $zero, $zero, $L2 => b $L2 - // beq $r0, $zero, $L2 => beqz $r0, $L2 - if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO)) - return printAlias1("b", MI, 2, OS); - if (isReg(MI, 1, Mips_ZERO)) - return printAlias2("beqz", MI, 0, 2, OS); - return NULL; - case Mips_BEQ64: - // beq $r0, $zero, $L2 => beqz $r0, $L2 - if (isReg(MI, 1, Mips_ZERO_64)) - return printAlias2("beqz", MI, 0, 2, OS); - return NULL; - case Mips_BNE: - // bne $r0, $zero, $L2 => bnez $r0, $L2 - if (isReg(MI, 1, Mips_ZERO)) - return printAlias2("bnez", MI, 0, 2, OS); - return NULL; - case Mips_BNE64: - // bne $r0, $zero, $L2 => bnez $r0, $L2 - if (isReg(MI, 1, Mips_ZERO_64)) - return printAlias2("bnez", MI, 0, 2, OS); - return NULL; - case Mips_BGEZAL: - // bgezal $zero, $L1 => bal $L1 - if (isReg(MI, 0, Mips_ZERO)) - return printAlias1("bal", MI, 1, OS); - return NULL; - case Mips_BC1T: - // bc1t $fcc0, $L1 => bc1t $L1 - if (isReg(MI, 0, Mips_FCC0)) - return printAlias1("bc1t", MI, 1, OS); - return NULL; - case Mips_BC1F: - // bc1f $fcc0, $L1 => bc1f $L1 - if (isReg(MI, 0, Mips_FCC0)) - return printAlias1("bc1f", MI, 1, OS); - return NULL; - case Mips_JALR: - // jalr $ra, $r1 => jalr $r1 - if (isReg(MI, 0, Mips_RA)) - return printAlias1("jalr", MI, 1, OS); - return NULL; - case Mips_JALR64: - // jalr $ra, $r1 => jalr $r1 - if (isReg(MI, 0, Mips_RA_64)) - return printAlias1("jalr", MI, 1, OS); - return NULL; - case Mips_NOR: - case Mips_NOR_MM: - // nor $r0, $r1, $zero => not $r0, $r1 - if (isReg(MI, 2, Mips_ZERO)) - return printAlias2("not", MI, 0, 1, OS); - return NULL; - case Mips_NOR64: - // nor $r0, $r1, $zero => not $r0, $r1 - if (isReg(MI, 2, Mips_ZERO_64)) - return printAlias2("not", MI, 0, 1, OS); - return NULL; - case Mips_OR: - // or $r0, $r1, $zero => move $r0, $r1 - if (isReg(MI, 2, Mips_ZERO)) - return printAlias2("move", MI, 0, 1, OS); - return NULL; - default: return NULL; + case Mips_BEQ: + case Mips_BEQ_MM: + // beq $zero, $zero, $L2 => b $L2 + // beq $r0, $zero, $L2 => beqz $r0, $L2 + return (isReg(MI, 0, Mips_ZERO) && + isReg(MI, 1, Mips_ZERO) && + printAlias("b", MI, Address, 2, OS, true)) || + (isReg(MI, 1, Mips_ZERO) && + printAlias2("beqz", MI, Address, 0, 2, OS, true)); + case Mips_BEQ64: + // beq $r0, $zero, $L2 => beqz $r0, $L2 + return isReg(MI, 1, Mips_ZERO_64) && + printAlias2("beqz", MI, Address, 0, 2, OS, true); + case Mips_BNE: + case Mips_BNE_MM: + // bne $r0, $zero, $L2 => bnez $r0, $L2 + return isReg(MI, 1, Mips_ZERO) && + printAlias2("bnez", MI, Address, 0, 2, OS, true); + case Mips_BNE64: + // bne $r0, $zero, $L2 => bnez $r0, $L2 + return isReg(MI, 1, Mips_ZERO_64) && + printAlias2("bnez", MI, Address, 0, 2, OS, true); + case Mips_BGEZAL: + // bgezal $zero, $L1 => bal $L1 + return isReg(MI, 0, Mips_ZERO) && + printAlias("bal", MI, Address, 1, OS, true); + case Mips_BC1T: + // bc1t $fcc0, $L1 => bc1t $L1 + return isReg(MI, 0, Mips_FCC0) && + printAlias("bc1t", MI, Address, 1, OS, true); + case Mips_BC1F: + // bc1f $fcc0, $L1 => bc1f $L1 + return isReg(MI, 0, Mips_FCC0) && + printAlias("bc1f", MI, Address, 1, OS, true); + case Mips_JALR: + // jalr $zero, $r1 => jr $r1 + // jalr $ra, $r1 => jalr $r1 + return (isReg(MI, 0, Mips_ZERO) && + printAlias("jr", MI, Address, 1, OS, false)) || + (isReg(MI, 0, Mips_RA) && + printAlias("jalr", MI, Address, 1, OS, false)); + case Mips_JALR64: + // jalr $zero, $r1 => jr $r1 + // jalr $ra, $r1 => jalr $r1 + return (isReg(MI, 0, Mips_ZERO_64) && + printAlias("jr", MI, Address, 1, OS, false)) || + (isReg(MI, 0, Mips_RA_64) && + printAlias("jalr", MI, Address, 1, OS, false)); + case Mips_NOR: + case Mips_NOR_MM: + case Mips_NOR_MMR6: + // nor $r0, $r1, $zero => not $r0, $r1 + return isReg(MI, 2, Mips_ZERO) && + printAlias2("not", MI, Address, 0, 1, OS, false); + case Mips_NOR64: + // nor $r0, $r1, $zero => not $r0, $r1 + return isReg(MI, 2, Mips_ZERO_64) && + printAlias2("not", MI, Address, 0, 1, OS, false); + case Mips_OR: + case Mips_ADDu: + // or $r0, $r1, $zero => move $r0, $r1 + // addu $r0, $r1, $zero => move $r0, $r1 + return isReg(MI, 2, Mips_ZERO) && + printAlias2("move", MI, Address, 0, 1, OS, false); + case Mips_LI48_NM: + case Mips_LI16_NM: + // li[16/48] $r0, imm => li $r0, imm + return printAlias2("li", MI, Address, 0, 1, OS, false); + case Mips_ADDIU_NM: + case Mips_ADDIUNEG_NM: + if (isReg(MI, 1, Mips_ZERO_NM)) + return printAlias2("li", MI, Address, 0, 2, OS, false); + else + return printAlias3("addiu", MI, Address, 0, 1, 2, OS); + case Mips_ADDIU48_NM: + case Mips_ADDIURS5_NM: + case Mips_ADDIUR1SP_NM: + case Mips_ADDIUR2_NM: + case Mips_ADDIUGPB_NM: + case Mips_ADDIUGPW_NM: + return printAlias3("addiu", MI, Address, 0, 1, 2, OS); + case Mips_ANDI16_NM: + case Mips_ANDI_NM: + // andi[16/32] $r0, $r1, imm => andi $r0, $r1, imm + return printAlias3("andi", MI, Address, 0, 1, 2, OS); + default: + return false; } } static void printRegisterList(MCInst *MI, int opNum, SStream *O) { - int i, e, reg; - // - 2 because register List is always first operand of instruction and it is // always followed by memory operand (base + offset). - for (i = opNum, e = MCInst_getNumOperands(MI) - 2; i != e; ++i) { + add_cs_detail(MI, Mips_OP_GROUP_RegisterList, opNum); + for (int i = opNum, e = MCInst_getNumOperands(MI) - 2; i != e; ++i) { if (i != opNum) SStream_concat0(O, ", "); - reg = MCOperand_getReg(MCInst_getOperand(MI, i)); - printRegName(O, reg); - if (MI->csh->detail_opt) { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg; - MI->flat_insn->detail->mips.op_count++; - } + printRegName(MI, O, MCOperand_getReg(MCInst_getOperand(MI, (i)))); } } -#define PRINT_ALIAS_INSTR -#include "MipsGenAsmWriter.inc" +static void printNanoMipsRegisterList(MCInst *MI, int OpNum, SStream *O) +{ + add_cs_detail(MI, Mips_OP_GROUP_NanoMipsRegisterList, OpNum); + for (unsigned I = OpNum; I < MCInst_getNumOperands(MI); I++) { + SStream_concat0(O, ", "); + printRegName(MI, O, MCOperand_getReg(MCInst_getOperand(MI, (I)))); + } +} + +static void printHi20(MCInst *MI, int OpNum, SStream *O) +{ + MCOperand *MO = MCInst_getOperand(MI, (OpNum)); + if (MCOperand_isImm(MO)) { + add_cs_detail(MI, Mips_OP_GROUP_Hi20, OpNum); + SStream_concat0(O, "%hi("); + printUInt64(O, MCOperand_getImm(MO)); + SStream_concat0(O, ")"); + } else + printOperand(MI, OpNum, O); +} -#endif +static void printHi20PCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O) +{ + MCOperand *MO = MCInst_getOperand(MI, (OpNum)); + if (MCOperand_isImm(MO)) { + add_cs_detail(MI, Mips_OP_GROUP_Hi20PCRel, OpNum); + SStream_concat0(O, "%pcrel_hi("); + printUInt64(O, MCOperand_getImm(MO) + Address); + SStream_concat0(O, ")"); + } else + printOperand(MI, OpNum, O); +} + +static void printPCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O) +{ + MCOperand *MO = MCInst_getOperand(MI, (OpNum)); + if (MCOperand_isImm(MO)) { + add_cs_detail(MI, Mips_OP_GROUP_PCRel, OpNum); + printUInt64(O, MCOperand_getImm(MO) + Address); + } + else + printOperand(MI, OpNum, O); +} + +const char *Mips_LLVM_getRegisterName(unsigned RegNo, bool noRegName) +{ + if (!RegNo || RegNo >= MIPS_REG_ENDING) { + return NULL; + } + if (noRegName) { + return getRegisterName(RegNo); + } + switch(RegNo) { + case MIPS_REG_AT: + case MIPS_REG_AT_64: + return "at"; + case MIPS_REG_A0: + case MIPS_REG_A0_64: + return "a0"; + case MIPS_REG_A1: + case MIPS_REG_A1_64: + return "a1"; + case MIPS_REG_A2: + case MIPS_REG_A2_64: + return "a2"; + case MIPS_REG_A3: + case MIPS_REG_A3_64: + return "a3"; + case MIPS_REG_K0: + case MIPS_REG_K0_64: + return "k0"; + case MIPS_REG_K1: + case MIPS_REG_K1_64: + return "k1"; + case MIPS_REG_S0: + case MIPS_REG_S0_64: + return "s0"; + case MIPS_REG_S1: + case MIPS_REG_S1_64: + return "s1"; + case MIPS_REG_S2: + case MIPS_REG_S2_64: + return "s2"; + case MIPS_REG_S3: + case MIPS_REG_S3_64: + return "s3"; + case MIPS_REG_S4: + case MIPS_REG_S4_64: + return "s4"; + case MIPS_REG_S5: + case MIPS_REG_S5_64: + return "s5"; + case MIPS_REG_S6: + case MIPS_REG_S6_64: + return "s6"; + case MIPS_REG_S7: + case MIPS_REG_S7_64: + return "s7"; + case MIPS_REG_T0: + case MIPS_REG_T0_64: + return "t0"; + case MIPS_REG_T1: + case MIPS_REG_T1_64: + return "t1"; + case MIPS_REG_T2: + case MIPS_REG_T2_64: + return "t2"; + case MIPS_REG_T3: + case MIPS_REG_T3_64: + return "t3"; + case MIPS_REG_T4: + case MIPS_REG_T4_64: + return "t4"; + case MIPS_REG_T5: + case MIPS_REG_T5_64: + return "t5"; + case MIPS_REG_T6: + case MIPS_REG_T6_64: + return "t6"; + case MIPS_REG_T7: + case MIPS_REG_T7_64: + return "t7"; + case MIPS_REG_T8: + case MIPS_REG_T8_64: + return "t8"; + case MIPS_REG_T9: + case MIPS_REG_T9_64: + return "t9"; + case MIPS_REG_V0: + case MIPS_REG_V0_64: + return "v0"; + case MIPS_REG_V1: + case MIPS_REG_V1_64: + return "v1"; + default: + return getRegisterName(RegNo); + } +} \ No newline at end of file diff --git a/arch/Mips/MipsInstPrinter.h b/arch/Mips/MipsInstPrinter.h index 659ef77901..0d92d8d796 100644 --- a/arch/Mips/MipsInstPrinter.h +++ b/arch/Mips/MipsInstPrinter.h @@ -1,9 +1,24 @@ +#include "../../SStream.h" +#include "../../MCInst.h" +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically translated source file from LLVM. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Only small edits allowed. */ +/* For multiple similar edits, please create a Patch for the translator. */ + +/* Capstone's C++ file translator: */ +/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ + //=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -11,15 +26,133 @@ // //===----------------------------------------------------------------------===// -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ +#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSINSTPRINTER_H +#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSINSTPRINTER_H +#include +#include +#include +#include -#ifndef CS_MIPSINSTPRINTER_H -#define CS_MIPSINSTPRINTER_H +#include "../../MCInstPrinter.h" +#include "../../cs_priv.h" +#define CONCAT(a, b) CONCAT_(a, b) +#define CONCAT_(a, b) a##_##b -#include "../../MCInst.h" -#include "../../SStream.h" +// These enumeration declarations were originally in MipsInstrInfo.h but +// had to be moved here to avoid circular dependencies between +// LLVMMipsCodeGen and LLVMMipsAsmPrinter. +// CS namespace begin: Mips + +// Mips Branch Codes +typedef enum MipsFPBranchCode { + Mips_BRANCH_F, + Mips_BRANCH_T, + Mips_BRANCH_FL, + Mips_BRANCH_TL, + Mips_BRANCH_INVALID +} Mips_FPBranchCode; + +// Mips Condition Codes +typedef enum MipsCondCode { + // To be used with float branch True + Mips_FCOND_F, + Mips_FCOND_UN, + Mips_FCOND_OEQ, + Mips_FCOND_UEQ, + Mips_FCOND_OLT, + Mips_FCOND_ULT, + Mips_FCOND_OLE, + Mips_FCOND_ULE, + Mips_FCOND_SF, + Mips_FCOND_NGLE, + Mips_FCOND_SEQ, + Mips_FCOND_NGL, + Mips_FCOND_LT, + Mips_FCOND_NGE, + Mips_FCOND_LE, + Mips_FCOND_NGT, + + // To be used with float branch False + // This conditions have the same mnemonic as the + // above ones, but are used with a branch False; + Mips_FCOND_T, + Mips_FCOND_OR, + Mips_FCOND_UNE, + Mips_FCOND_ONE, + Mips_FCOND_UGE, + Mips_FCOND_OGE, + Mips_FCOND_UGT, + Mips_FCOND_OGT, + Mips_FCOND_ST, + Mips_FCOND_GLE, + Mips_FCOND_SNE, + Mips_FCOND_GL, + Mips_FCOND_NLT, + Mips_FCOND_GE, + Mips_FCOND_NLE, + Mips_FCOND_GT +} Mips_CondCode; + +static const char *MipsFCCToString(Mips_CondCode CC); + +// CS namespace end: Mips + +// end namespace Mips + +// Autogenerated by tblgen. +static const char *getRegisterName(unsigned RegNo); +static void printInstruction(MCInst *MI, uint64_t Address, SStream *O); +static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS); +static void printCustomAliasOperand(MCInst *MI, uint64_t Address, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *O); +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printJumpOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo, + SStream *O); + +#define DECLARE_printUImm_2(Bits, Offset) \ + static void CONCAT(printUImm, CONCAT(Bits, Offset))( \ + MCInst *MI, int opNum, SStream *O) +#define DECLARE_printUImm(Bits) \ + static void CONCAT(printUImm, CONCAT(Bits, 0))( \ + MCInst *MI, int opNum, SStream *O) +DECLARE_printUImm(0); +DECLARE_printUImm(1); +DECLARE_printUImm(10); +DECLARE_printUImm(12); +DECLARE_printUImm(16); +DECLARE_printUImm(2); +DECLARE_printUImm(20); +DECLARE_printUImm(26); +DECLARE_printUImm(3); +DECLARE_printUImm(32); +DECLARE_printUImm(4); +DECLARE_printUImm(5); +DECLARE_printUImm(6); +DECLARE_printUImm(7); +DECLARE_printUImm(8); +DECLARE_printUImm_2(2, 1); +DECLARE_printUImm_2(5, 1); +DECLARE_printUImm_2(5, 32); +DECLARE_printUImm_2(5, 33); +DECLARE_printUImm_2(6, 1); +DECLARE_printUImm_2(6, 2); -void Mips_printInst(MCInst *MI, SStream *O, void *info); +static void printMemOperand(MCInst *MI, int opNum, SStream *O); +static void printMemOperandEA(MCInst *MI, int opNum, SStream *O); +static void printFCCOperand(MCInst *MI, int opNum, SStream *O); +static bool printAlias(const char *Str, const MCInst *MI, uint64_t Address, + unsigned OpNo, SStream *OS, bool IsBranch); +static bool printAlias2(const char *Str, const MCInst *MI, uint64_t Address, + unsigned OpNo0, unsigned OpNo1, SStream *OS, + bool IsBranch); +static bool printAlias3(const char *Str, const MCInst *MI, uint64_t Address, + unsigned OpNo0, unsigned OpNo1, unsigned OpNo2, SStream *OS); +static bool printAlias4(const MCInst *MI, uint64_t Address, SStream *OS); +static void printRegisterList(MCInst *MI, int opNum, SStream *O); +static void printNanoMipsRegisterList(MCInst *MI, int opNum, SStream *O); +static void printHi20(MCInst *MI, int OpNum, SStream *O); +static void printHi20PCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O); +static void printPCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O); #endif diff --git a/arch/Mips/MipsLinkage.h b/arch/Mips/MipsLinkage.h new file mode 100644 index 0000000000..93d3d99800 --- /dev/null +++ b/arch/Mips/MipsLinkage.h @@ -0,0 +1,21 @@ +/* Capstone Disassembly Engine */ +/* By Giovanni Dante Grazioli, deroad , 2024 */ + +#ifndef CS_MIPS_LINKAGE_H +#define CS_MIPS_LINKAGE_H + +// Function definitions to call static LLVM functions. + +#include "../../MCDisassembler.h" +#include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include "../../SStream.h" +#include "capstone/capstone.h" + +const char *Mips_LLVM_getRegisterName(unsigned RegNo, bool noRegName); +void Mips_LLVM_printInst(MCInst *MI, uint64_t Address, SStream *O); +DecodeStatus Mips_LLVM_getInstruction(MCInst *Instr, uint64_t *Size, + const uint8_t *Bytes, size_t BytesLen, + uint64_t Address, SStream *CStream); + +#endif // CS_MIPS_LINKAGE_H diff --git a/arch/Mips/MipsMapping.c b/arch/Mips/MipsMapping.c index 41dda33d3a..3f1ec49ce9 100644 --- a/arch/Mips/MipsMapping.c +++ b/arch/Mips/MipsMapping.c @@ -1,1071 +1,467 @@ /* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* By Giovanni Dante Grazioli, deroad , 2024 */ #ifdef CAPSTONE_HAS_MIPS -#include // debug +#include #include +#include +#include + #include "../../Mapping.h" -#include "../../utils.h" +#include "../../MCDisassembler.h" +#include "../../cs_priv.h" +#include "../../cs_simple_types.h" #include "MipsMapping.h" +#include "MipsLinkage.h" +#include "MipsDisassembler.h" + +#define GET_REGINFO_ENUM +#define GET_REGINFO_MC_DESC +#include "MipsGenRegisterInfo.inc" #define GET_INSTRINFO_ENUM #include "MipsGenInstrInfo.inc" -#ifndef CAPSTONE_DIET -static const name_map reg_name_maps[] = { - { MIPS_REG_INVALID, NULL }, - - { MIPS_REG_PC, "pc"}, - - //{ MIPS_REG_0, "0"}, - { MIPS_REG_0, "zero"}, - { MIPS_REG_1, "at"}, - //{ MIPS_REG_1, "1"}, - { MIPS_REG_2, "v0"}, - //{ MIPS_REG_2, "2"}, - { MIPS_REG_3, "v1"}, - //{ MIPS_REG_3, "3"}, - { MIPS_REG_4, "a0"}, - //{ MIPS_REG_4, "4"}, - { MIPS_REG_5, "a1"}, - //{ MIPS_REG_5, "5"}, - { MIPS_REG_6, "a2"}, - //{ MIPS_REG_6, "6"}, - { MIPS_REG_7, "a3"}, - //{ MIPS_REG_7, "7"}, - { MIPS_REG_8, "t0"}, - //{ MIPS_REG_8, "8"}, - { MIPS_REG_9, "t1"}, - //{ MIPS_REG_9, "9"}, - { MIPS_REG_10, "t2"}, - //{ MIPS_REG_10, "10"}, - { MIPS_REG_11, "t3"}, - //{ MIPS_REG_11, "11"}, - { MIPS_REG_12, "t4"}, - //{ MIPS_REG_12, "12"}, - { MIPS_REG_13, "t5"}, - //{ MIPS_REG_13, "13"}, - { MIPS_REG_14, "t6"}, - //{ MIPS_REG_14, "14"}, - { MIPS_REG_15, "t7"}, - //{ MIPS_REG_15, "15"}, - { MIPS_REG_16, "s0"}, - //{ MIPS_REG_16, "16"}, - { MIPS_REG_17, "s1"}, - //{ MIPS_REG_17, "17"}, - { MIPS_REG_18, "s2"}, - //{ MIPS_REG_18, "18"}, - { MIPS_REG_19, "s3"}, - //{ MIPS_REG_19, "19"}, - { MIPS_REG_20, "s4"}, - //{ MIPS_REG_20, "20"}, - { MIPS_REG_21, "s5"}, - //{ MIPS_REG_21, "21"}, - { MIPS_REG_22, "s6"}, - //{ MIPS_REG_22, "22"}, - { MIPS_REG_23, "s7"}, - //{ MIPS_REG_23, "23"}, - { MIPS_REG_24, "t8"}, - //{ MIPS_REG_24, "24"}, - { MIPS_REG_25, "t9"}, - //{ MIPS_REG_25, "25"}, - { MIPS_REG_26, "k0"}, - //{ MIPS_REG_26, "26"}, - { MIPS_REG_27, "k1"}, - //{ MIPS_REG_27, "27"}, - { MIPS_REG_28, "gp"}, - //{ MIPS_REG_28, "28"}, - { MIPS_REG_29, "sp"}, - //{ MIPS_REG_29, "29"}, - { MIPS_REG_30, "fp"}, - //{ MIPS_REG_30, "30"}, - { MIPS_REG_31, "ra"}, - //{ MIPS_REG_31, "31"}, - - { MIPS_REG_DSPCCOND, "dspccond"}, - { MIPS_REG_DSPCARRY, "dspcarry"}, - { MIPS_REG_DSPEFI, "dspefi"}, - { MIPS_REG_DSPOUTFLAG, "dspoutflag"}, - { MIPS_REG_DSPOUTFLAG16_19, "dspoutflag16_19"}, - { MIPS_REG_DSPOUTFLAG20, "dspoutflag20"}, - { MIPS_REG_DSPOUTFLAG21, "dspoutflag21"}, - { MIPS_REG_DSPOUTFLAG22, "dspoutflag22"}, - { MIPS_REG_DSPOUTFLAG23, "dspoutflag23"}, - { MIPS_REG_DSPPOS, "dsppos"}, - { MIPS_REG_DSPSCOUNT, "dspscount"}, - - { MIPS_REG_AC0, "ac0"}, - { MIPS_REG_AC1, "ac1"}, - { MIPS_REG_AC2, "ac2"}, - { MIPS_REG_AC3, "ac3"}, +void Mips_init_mri(MCRegisterInfo *MRI) +{ + MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, sizeof(MipsRegDesc), + 0, 0, MipsMCRegisterClasses, + ARR_SIZE(MipsMCRegisterClasses), 0, 0, + MipsRegDiffLists, 0, + MipsSubRegIdxLists, + ARR_SIZE(MipsSubRegIdxLists), 0); +} - { MIPS_REG_CC0, "cc0"}, - { MIPS_REG_CC1, "cc1"}, - { MIPS_REG_CC2, "cc2"}, - { MIPS_REG_CC3, "cc3"}, - { MIPS_REG_CC4, "cc4"}, - { MIPS_REG_CC5, "cc5"}, - { MIPS_REG_CC6, "cc6"}, - { MIPS_REG_CC7, "cc7"}, +const char *Mips_reg_name(csh handle, unsigned int reg) +{ + int syntax_opt = ((cs_struct *)(uintptr_t)handle)->syntax; + return Mips_LLVM_getRegisterName(reg, + syntax_opt & CS_OPT_SYNTAX_NOREGNAME); +} - { MIPS_REG_F0, "f0"}, - { MIPS_REG_F1, "f1"}, - { MIPS_REG_F2, "f2"}, - { MIPS_REG_F3, "f3"}, - { MIPS_REG_F4, "f4"}, - { MIPS_REG_F5, "f5"}, - { MIPS_REG_F6, "f6"}, - { MIPS_REG_F7, "f7"}, - { MIPS_REG_F8, "f8"}, - { MIPS_REG_F9, "f9"}, - { MIPS_REG_F10, "f10"}, - { MIPS_REG_F11, "f11"}, - { MIPS_REG_F12, "f12"}, - { MIPS_REG_F13, "f13"}, - { MIPS_REG_F14, "f14"}, - { MIPS_REG_F15, "f15"}, - { MIPS_REG_F16, "f16"}, - { MIPS_REG_F17, "f17"}, - { MIPS_REG_F18, "f18"}, - { MIPS_REG_F19, "f19"}, - { MIPS_REG_F20, "f20"}, - { MIPS_REG_F21, "f21"}, - { MIPS_REG_F22, "f22"}, - { MIPS_REG_F23, "f23"}, - { MIPS_REG_F24, "f24"}, - { MIPS_REG_F25, "f25"}, - { MIPS_REG_F26, "f26"}, - { MIPS_REG_F27, "f27"}, - { MIPS_REG_F28, "f28"}, - { MIPS_REG_F29, "f29"}, - { MIPS_REG_F30, "f30"}, - { MIPS_REG_F31, "f31"}, +void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) +{ + // Not used by Mips. Information is set after disassembly. +} - { MIPS_REG_FCC0, "fcc0"}, - { MIPS_REG_FCC1, "fcc1"}, - { MIPS_REG_FCC2, "fcc2"}, - { MIPS_REG_FCC3, "fcc3"}, - { MIPS_REG_FCC4, "fcc4"}, - { MIPS_REG_FCC5, "fcc5"}, - { MIPS_REG_FCC6, "fcc6"}, - { MIPS_REG_FCC7, "fcc7"}, +static const char *const insn_name_maps[] = { +#include "MipsGenCSMappingInsnName.inc" +}; - { MIPS_REG_W0, "w0"}, - { MIPS_REG_W1, "w1"}, - { MIPS_REG_W2, "w2"}, - { MIPS_REG_W3, "w3"}, - { MIPS_REG_W4, "w4"}, - { MIPS_REG_W5, "w5"}, - { MIPS_REG_W6, "w6"}, - { MIPS_REG_W7, "w7"}, - { MIPS_REG_W8, "w8"}, - { MIPS_REG_W9, "w9"}, - { MIPS_REG_W10, "w10"}, - { MIPS_REG_W11, "w11"}, - { MIPS_REG_W12, "w12"}, - { MIPS_REG_W13, "w13"}, - { MIPS_REG_W14, "w14"}, - { MIPS_REG_W15, "w15"}, - { MIPS_REG_W16, "w16"}, - { MIPS_REG_W17, "w17"}, - { MIPS_REG_W18, "w18"}, - { MIPS_REG_W19, "w19"}, - { MIPS_REG_W20, "w20"}, - { MIPS_REG_W21, "w21"}, - { MIPS_REG_W22, "w22"}, - { MIPS_REG_W23, "w23"}, - { MIPS_REG_W24, "w24"}, - { MIPS_REG_W25, "w25"}, - { MIPS_REG_W26, "w26"}, - { MIPS_REG_W27, "w27"}, - { MIPS_REG_W28, "w28"}, - { MIPS_REG_W29, "w29"}, - { MIPS_REG_W30, "w30"}, - { MIPS_REG_W31, "w31"}, +const char *Mips_insn_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + if (id < ARR_SIZE(insn_name_maps)) + return insn_name_maps[id]; + // not found + return NULL; +#else + return NULL; +#endif +} - { MIPS_REG_HI, "hi"}, - { MIPS_REG_LO, "lo"}, +#ifndef CAPSTONE_DIET +static const name_map group_name_maps[] = { + { MIPS_GRP_INVALID, NULL }, - { MIPS_REG_P0, "p0"}, - { MIPS_REG_P1, "p1"}, - { MIPS_REG_P2, "p2"}, + { MIPS_GRP_JUMP, "jump" }, + { MIPS_GRP_CALL, "call" }, + { MIPS_GRP_RET, "return" }, + { MIPS_GRP_INT, "int" }, + { MIPS_GRP_IRET, "iret" }, + { MIPS_GRP_PRIVILEGE, "privilege" }, + { MIPS_GRP_BRANCH_RELATIVE, "branch_relative" }, - { MIPS_REG_MPL0, "mpl0"}, - { MIPS_REG_MPL1, "mpl1"}, - { MIPS_REG_MPL2, "mpl2"}, +// architecture-specific groups +#include "MipsGenCSFeatureName.inc" }; #endif -const char *Mips_reg_name(csh handle, unsigned int reg) +const char *Mips_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - if (reg >= ARR_SIZE(reg_name_maps)) - return NULL; - - return reg_name_maps[reg].name; + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else return NULL; #endif } -static const insn_map insns[] = { - // dummy item - { - 0, 0, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - -#include "MipsMappingInsn.inc" +const insn_map mips_insns[] = { +#include "MipsGenCSMappingInsn.inc" }; -// given internal insn id, return public instruction info -void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) +void Mips_reg_access(const cs_insn *insn, cs_regs regs_read, + uint8_t *regs_read_count, cs_regs regs_write, + uint8_t *regs_write_count) { - unsigned int i; - - i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); - if (i != 0) { - insn->id = insns[i].mapid; + uint8_t i; + uint8_t read_count, write_count; + cs_mips *mips = &(insn->detail->mips); + + read_count = insn->detail->regs_read_count; + write_count = insn->detail->regs_write_count; + + // implicit registers + memcpy(regs_read, insn->detail->regs_read, + read_count * sizeof(insn->detail->regs_read[0])); + memcpy(regs_write, insn->detail->regs_write, + write_count * sizeof(insn->detail->regs_write[0])); + + // explicit registers + for (i = 0; i < mips->op_count; i++) { + cs_mips_op *op = &(mips->operands[i]); + switch ((int)op->type) { + case MIPS_OP_REG: + if ((op->access & CS_AC_READ) && + !arr_exist(regs_read, read_count, op->reg)) { + regs_read[read_count] = (uint16_t)op->reg; + read_count++; + } + if ((op->access & CS_AC_WRITE) && + !arr_exist(regs_write, write_count, op->reg)) { + regs_write[write_count] = (uint16_t)op->reg; + write_count++; + } + break; + case MIPS_OP_MEM: + // registers appeared in memory references always being read + if ((op->mem.base != MIPS_REG_INVALID) && + !arr_exist(regs_read, read_count, op->mem.base)) { + regs_read[read_count] = (uint16_t)op->mem.base; + read_count++; + } + if ((insn->detail->writeback) && + (op->mem.base != MIPS_REG_INVALID) && + !arr_exist(regs_write, write_count, op->mem.base)) { + regs_write[write_count] = + (uint16_t)op->mem.base; + write_count++; + } + default: + break; + } + } - if (h->detail_opt) { -#ifndef CAPSTONE_DIET - memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); - insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); + *regs_read_count = read_count; + *regs_write_count = write_count; +} - memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); - insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); +void Mips_set_instr_map_data(MCInst *MI) +{ + // Fixes for missing groups. + if (MCInst_getOpcode(MI) == Mips_JR) { + unsigned Reg = MCInst_getOpVal(MI, 0); + switch (Reg) { + case MIPS_REG_RA: + case MIPS_REG_RA_64: + add_group(MI, MIPS_GRP_RET); + break; + } + } - memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); - insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); + map_cs_id(MI, mips_insns, ARR_SIZE(mips_insns)); + map_implicit_reads(MI, mips_insns); + map_implicit_writes(MI, mips_insns); + map_groups(MI, mips_insns); +} - if (insns[i].branch || insns[i].indirect_branch) { - // this insn also belongs to JUMP group. add JUMP group - insn->detail->groups[insn->detail->groups_count] = MIPS_GRP_JUMP; - insn->detail->groups_count++; - } -#endif - } +bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, + void *info) +{ + uint64_t size64; + Mips_init_cs_detail(instr); + instr->MRI = (MCRegisterInfo *)info; + map_set_fill_detail_ops(instr, true); + + bool result = Mips_LLVM_getInstruction(instr, &size64, code, code_len, + address, + info) != MCDisassembler_Fail; + if (result) { + Mips_set_instr_map_data(instr); } + *size = size64; + return result; +} + +void Mips_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info) +{ + MCRegisterInfo *MRI = (MCRegisterInfo *)info; + MI->MRI = MRI; + + Mips_LLVM_printInst(MI, MI->address, O); +} + +static void Mips_setup_op(cs_mips_op *op) +{ + memset(op, 0, sizeof(cs_mips_op)); + op->type = MIPS_OP_INVALID; } -static const name_map insn_name_maps[] = { - { MIPS_INS_INVALID, NULL }, +void Mips_init_cs_detail(MCInst *MI) +{ + if (detail_is_set(MI)) { + unsigned int i; - { MIPS_INS_ABSQ_S, "absq_s" }, - { MIPS_INS_ADD, "add" }, - { MIPS_INS_ADDIUPC, "addiupc" }, - { MIPS_INS_ADDIUR1SP, "addiur1sp" }, - { MIPS_INS_ADDIUR2, "addiur2" }, - { MIPS_INS_ADDIUS5, "addius5" }, - { MIPS_INS_ADDIUSP, "addiusp" }, - { MIPS_INS_ADDQH, "addqh" }, - { MIPS_INS_ADDQH_R, "addqh_r" }, - { MIPS_INS_ADDQ, "addq" }, - { MIPS_INS_ADDQ_S, "addq_s" }, - { MIPS_INS_ADDSC, "addsc" }, - { MIPS_INS_ADDS_A, "adds_a" }, - { MIPS_INS_ADDS_S, "adds_s" }, - { MIPS_INS_ADDS_U, "adds_u" }, - { MIPS_INS_ADDU16, "addu16" }, - { MIPS_INS_ADDUH, "adduh" }, - { MIPS_INS_ADDUH_R, "adduh_r" }, - { MIPS_INS_ADDU, "addu" }, - { MIPS_INS_ADDU_S, "addu_s" }, - { MIPS_INS_ADDVI, "addvi" }, - { MIPS_INS_ADDV, "addv" }, - { MIPS_INS_ADDWC, "addwc" }, - { MIPS_INS_ADD_A, "add_a" }, - { MIPS_INS_ADDI, "addi" }, - { MIPS_INS_ADDIU, "addiu" }, - { MIPS_INS_ALIGN, "align" }, - { MIPS_INS_ALUIPC, "aluipc" }, - { MIPS_INS_AND, "and" }, - { MIPS_INS_AND16, "and16" }, - { MIPS_INS_ANDI16, "andi16" }, - { MIPS_INS_ANDI, "andi" }, - { MIPS_INS_APPEND, "append" }, - { MIPS_INS_ASUB_S, "asub_s" }, - { MIPS_INS_ASUB_U, "asub_u" }, - { MIPS_INS_AUI, "aui" }, - { MIPS_INS_AUIPC, "auipc" }, - { MIPS_INS_AVER_S, "aver_s" }, - { MIPS_INS_AVER_U, "aver_u" }, - { MIPS_INS_AVE_S, "ave_s" }, - { MIPS_INS_AVE_U, "ave_u" }, - { MIPS_INS_B16, "b16" }, - { MIPS_INS_BADDU, "baddu" }, - { MIPS_INS_BAL, "bal" }, - { MIPS_INS_BALC, "balc" }, - { MIPS_INS_BALIGN, "balign" }, - { MIPS_INS_BBIT0, "bbit0" }, - { MIPS_INS_BBIT032, "bbit032" }, - { MIPS_INS_BBIT1, "bbit1" }, - { MIPS_INS_BBIT132, "bbit132" }, - { MIPS_INS_BC, "bc" }, - { MIPS_INS_BC0F, "bc0f" }, - { MIPS_INS_BC0FL, "bc0fl" }, - { MIPS_INS_BC0T, "bc0t" }, - { MIPS_INS_BC0TL, "bc0tl" }, - { MIPS_INS_BC1EQZ, "bc1eqz" }, - { MIPS_INS_BC1F, "bc1f" }, - { MIPS_INS_BC1FL, "bc1fl" }, - { MIPS_INS_BC1NEZ, "bc1nez" }, - { MIPS_INS_BC1T, "bc1t" }, - { MIPS_INS_BC1TL, "bc1tl" }, - { MIPS_INS_BC2EQZ, "bc2eqz" }, - { MIPS_INS_BC2F, "bc2f" }, - { MIPS_INS_BC2FL, "bc2fl" }, - { MIPS_INS_BC2NEZ, "bc2nez" }, - { MIPS_INS_BC2T, "bc2t" }, - { MIPS_INS_BC2TL, "bc2tl" }, - { MIPS_INS_BC3F, "bc3f" }, - { MIPS_INS_BC3FL, "bc3fl" }, - { MIPS_INS_BC3T, "bc3t" }, - { MIPS_INS_BC3TL, "bc3tl" }, - { MIPS_INS_BCLRI, "bclri" }, - { MIPS_INS_BCLR, "bclr" }, - { MIPS_INS_BEQ, "beq" }, - { MIPS_INS_BEQC, "beqc" }, - { MIPS_INS_BEQL, "beql" }, - { MIPS_INS_BEQZ16, "beqz16" }, - { MIPS_INS_BEQZALC, "beqzalc" }, - { MIPS_INS_BEQZC, "beqzc" }, - { MIPS_INS_BGEC, "bgec" }, - { MIPS_INS_BGEUC, "bgeuc" }, - { MIPS_INS_BGEZ, "bgez" }, - { MIPS_INS_BGEZAL, "bgezal" }, - { MIPS_INS_BGEZALC, "bgezalc" }, - { MIPS_INS_BGEZALL, "bgezall" }, - { MIPS_INS_BGEZALS, "bgezals" }, - { MIPS_INS_BGEZC, "bgezc" }, - { MIPS_INS_BGEZL, "bgezl" }, - { MIPS_INS_BGTZ, "bgtz" }, - { MIPS_INS_BGTZALC, "bgtzalc" }, - { MIPS_INS_BGTZC, "bgtzc" }, - { MIPS_INS_BGTZL, "bgtzl" }, - { MIPS_INS_BINSLI, "binsli" }, - { MIPS_INS_BINSL, "binsl" }, - { MIPS_INS_BINSRI, "binsri" }, - { MIPS_INS_BINSR, "binsr" }, - { MIPS_INS_BITREV, "bitrev" }, - { MIPS_INS_BITSWAP, "bitswap" }, - { MIPS_INS_BLEZ, "blez" }, - { MIPS_INS_BLEZALC, "blezalc" }, - { MIPS_INS_BLEZC, "blezc" }, - { MIPS_INS_BLEZL, "blezl" }, - { MIPS_INS_BLTC, "bltc" }, - { MIPS_INS_BLTUC, "bltuc" }, - { MIPS_INS_BLTZ, "bltz" }, - { MIPS_INS_BLTZAL, "bltzal" }, - { MIPS_INS_BLTZALC, "bltzalc" }, - { MIPS_INS_BLTZALL, "bltzall" }, - { MIPS_INS_BLTZALS, "bltzals" }, - { MIPS_INS_BLTZC, "bltzc" }, - { MIPS_INS_BLTZL, "bltzl" }, - { MIPS_INS_BMNZI, "bmnzi" }, - { MIPS_INS_BMNZ, "bmnz" }, - { MIPS_INS_BMZI, "bmzi" }, - { MIPS_INS_BMZ, "bmz" }, - { MIPS_INS_BNE, "bne" }, - { MIPS_INS_BNEC, "bnec" }, - { MIPS_INS_BNEGI, "bnegi" }, - { MIPS_INS_BNEG, "bneg" }, - { MIPS_INS_BNEL, "bnel" }, - { MIPS_INS_BNEZ16, "bnez16" }, - { MIPS_INS_BNEZALC, "bnezalc" }, - { MIPS_INS_BNEZC, "bnezc" }, - { MIPS_INS_BNVC, "bnvc" }, - { MIPS_INS_BNZ, "bnz" }, - { MIPS_INS_BOVC, "bovc" }, - { MIPS_INS_BPOSGE32, "bposge32" }, - { MIPS_INS_BREAK, "break" }, - { MIPS_INS_BREAK16, "break16" }, - { MIPS_INS_BSELI, "bseli" }, - { MIPS_INS_BSEL, "bsel" }, - { MIPS_INS_BSETI, "bseti" }, - { MIPS_INS_BSET, "bset" }, - { MIPS_INS_BZ, "bz" }, - { MIPS_INS_BEQZ, "beqz" }, - { MIPS_INS_B, "b" }, - { MIPS_INS_BNEZ, "bnez" }, - { MIPS_INS_BTEQZ, "bteqz" }, - { MIPS_INS_BTNEZ, "btnez" }, - { MIPS_INS_CACHE, "cache" }, - { MIPS_INS_CEIL, "ceil" }, - { MIPS_INS_CEQI, "ceqi" }, - { MIPS_INS_CEQ, "ceq" }, - { MIPS_INS_CFC1, "cfc1" }, - { MIPS_INS_CFCMSA, "cfcmsa" }, - { MIPS_INS_CINS, "cins" }, - { MIPS_INS_CINS32, "cins32" }, - { MIPS_INS_CLASS, "class" }, - { MIPS_INS_CLEI_S, "clei_s" }, - { MIPS_INS_CLEI_U, "clei_u" }, - { MIPS_INS_CLE_S, "cle_s" }, - { MIPS_INS_CLE_U, "cle_u" }, - { MIPS_INS_CLO, "clo" }, - { MIPS_INS_CLTI_S, "clti_s" }, - { MIPS_INS_CLTI_U, "clti_u" }, - { MIPS_INS_CLT_S, "clt_s" }, - { MIPS_INS_CLT_U, "clt_u" }, - { MIPS_INS_CLZ, "clz" }, - { MIPS_INS_CMPGDU, "cmpgdu" }, - { MIPS_INS_CMPGU, "cmpgu" }, - { MIPS_INS_CMPU, "cmpu" }, - { MIPS_INS_CMP, "cmp" }, - { MIPS_INS_COPY_S, "copy_s" }, - { MIPS_INS_COPY_U, "copy_u" }, - { MIPS_INS_CTC1, "ctc1" }, - { MIPS_INS_CTCMSA, "ctcmsa" }, - { MIPS_INS_CVT, "cvt" }, - { MIPS_INS_C, "c" }, - { MIPS_INS_CMPI, "cmpi" }, - { MIPS_INS_DADD, "dadd" }, - { MIPS_INS_DADDI, "daddi" }, - { MIPS_INS_DADDIU, "daddiu" }, - { MIPS_INS_DADDU, "daddu" }, - { MIPS_INS_DAHI, "dahi" }, - { MIPS_INS_DALIGN, "dalign" }, - { MIPS_INS_DATI, "dati" }, - { MIPS_INS_DAUI, "daui" }, - { MIPS_INS_DBITSWAP, "dbitswap" }, - { MIPS_INS_DCLO, "dclo" }, - { MIPS_INS_DCLZ, "dclz" }, - { MIPS_INS_DDIV, "ddiv" }, - { MIPS_INS_DDIVU, "ddivu" }, - { MIPS_INS_DERET, "deret" }, - { MIPS_INS_DEXT, "dext" }, - { MIPS_INS_DEXTM, "dextm" }, - { MIPS_INS_DEXTU, "dextu" }, - { MIPS_INS_DI, "di" }, - { MIPS_INS_DINS, "dins" }, - { MIPS_INS_DINSM, "dinsm" }, - { MIPS_INS_DINSU, "dinsu" }, - { MIPS_INS_DIV, "div" }, - { MIPS_INS_DIVU, "divu" }, - { MIPS_INS_DIV_S, "div_s" }, - { MIPS_INS_DIV_U, "div_u" }, - { MIPS_INS_DLSA, "dlsa" }, - { MIPS_INS_DMFC0, "dmfc0" }, - { MIPS_INS_DMFC1, "dmfc1" }, - { MIPS_INS_DMFC2, "dmfc2" }, - { MIPS_INS_DMOD, "dmod" }, - { MIPS_INS_DMODU, "dmodu" }, - { MIPS_INS_DMTC0, "dmtc0" }, - { MIPS_INS_DMTC1, "dmtc1" }, - { MIPS_INS_DMTC2, "dmtc2" }, - { MIPS_INS_DMUH, "dmuh" }, - { MIPS_INS_DMUHU, "dmuhu" }, - { MIPS_INS_DMUL, "dmul" }, - { MIPS_INS_DMULT, "dmult" }, - { MIPS_INS_DMULTU, "dmultu" }, - { MIPS_INS_DMULU, "dmulu" }, - { MIPS_INS_DOTP_S, "dotp_s" }, - { MIPS_INS_DOTP_U, "dotp_u" }, - { MIPS_INS_DPADD_S, "dpadd_s" }, - { MIPS_INS_DPADD_U, "dpadd_u" }, - { MIPS_INS_DPAQX_SA, "dpaqx_sa" }, - { MIPS_INS_DPAQX_S, "dpaqx_s" }, - { MIPS_INS_DPAQ_SA, "dpaq_sa" }, - { MIPS_INS_DPAQ_S, "dpaq_s" }, - { MIPS_INS_DPAU, "dpau" }, - { MIPS_INS_DPAX, "dpax" }, - { MIPS_INS_DPA, "dpa" }, - { MIPS_INS_DPOP, "dpop" }, - { MIPS_INS_DPSQX_SA, "dpsqx_sa" }, - { MIPS_INS_DPSQX_S, "dpsqx_s" }, - { MIPS_INS_DPSQ_SA, "dpsq_sa" }, - { MIPS_INS_DPSQ_S, "dpsq_s" }, - { MIPS_INS_DPSUB_S, "dpsub_s" }, - { MIPS_INS_DPSUB_U, "dpsub_u" }, - { MIPS_INS_DPSU, "dpsu" }, - { MIPS_INS_DPSX, "dpsx" }, - { MIPS_INS_DPS, "dps" }, - { MIPS_INS_DROTR, "drotr" }, - { MIPS_INS_DROTR32, "drotr32" }, - { MIPS_INS_DROTRV, "drotrv" }, - { MIPS_INS_DSBH, "dsbh" }, - { MIPS_INS_DSHD, "dshd" }, - { MIPS_INS_DSLL, "dsll" }, - { MIPS_INS_DSLL32, "dsll32" }, - { MIPS_INS_DSLLV, "dsllv" }, - { MIPS_INS_DSRA, "dsra" }, - { MIPS_INS_DSRA32, "dsra32" }, - { MIPS_INS_DSRAV, "dsrav" }, - { MIPS_INS_DSRL, "dsrl" }, - { MIPS_INS_DSRL32, "dsrl32" }, - { MIPS_INS_DSRLV, "dsrlv" }, - { MIPS_INS_DSUB, "dsub" }, - { MIPS_INS_DSUBU, "dsubu" }, - { MIPS_INS_EHB, "ehb" }, - { MIPS_INS_EI, "ei" }, - { MIPS_INS_ERET, "eret" }, - { MIPS_INS_EXT, "ext" }, - { MIPS_INS_EXTP, "extp" }, - { MIPS_INS_EXTPDP, "extpdp" }, - { MIPS_INS_EXTPDPV, "extpdpv" }, - { MIPS_INS_EXTPV, "extpv" }, - { MIPS_INS_EXTRV_RS, "extrv_rs" }, - { MIPS_INS_EXTRV_R, "extrv_r" }, - { MIPS_INS_EXTRV_S, "extrv_s" }, - { MIPS_INS_EXTRV, "extrv" }, - { MIPS_INS_EXTR_RS, "extr_rs" }, - { MIPS_INS_EXTR_R, "extr_r" }, - { MIPS_INS_EXTR_S, "extr_s" }, - { MIPS_INS_EXTR, "extr" }, - { MIPS_INS_EXTS, "exts" }, - { MIPS_INS_EXTS32, "exts32" }, - { MIPS_INS_ABS, "abs" }, - { MIPS_INS_FADD, "fadd" }, - { MIPS_INS_FCAF, "fcaf" }, - { MIPS_INS_FCEQ, "fceq" }, - { MIPS_INS_FCLASS, "fclass" }, - { MIPS_INS_FCLE, "fcle" }, - { MIPS_INS_FCLT, "fclt" }, - { MIPS_INS_FCNE, "fcne" }, - { MIPS_INS_FCOR, "fcor" }, - { MIPS_INS_FCUEQ, "fcueq" }, - { MIPS_INS_FCULE, "fcule" }, - { MIPS_INS_FCULT, "fcult" }, - { MIPS_INS_FCUNE, "fcune" }, - { MIPS_INS_FCUN, "fcun" }, - { MIPS_INS_FDIV, "fdiv" }, - { MIPS_INS_FEXDO, "fexdo" }, - { MIPS_INS_FEXP2, "fexp2" }, - { MIPS_INS_FEXUPL, "fexupl" }, - { MIPS_INS_FEXUPR, "fexupr" }, - { MIPS_INS_FFINT_S, "ffint_s" }, - { MIPS_INS_FFINT_U, "ffint_u" }, - { MIPS_INS_FFQL, "ffql" }, - { MIPS_INS_FFQR, "ffqr" }, - { MIPS_INS_FILL, "fill" }, - { MIPS_INS_FLOG2, "flog2" }, - { MIPS_INS_FLOOR, "floor" }, - { MIPS_INS_FMADD, "fmadd" }, - { MIPS_INS_FMAX_A, "fmax_a" }, - { MIPS_INS_FMAX, "fmax" }, - { MIPS_INS_FMIN_A, "fmin_a" }, - { MIPS_INS_FMIN, "fmin" }, - { MIPS_INS_MOV, "mov" }, - { MIPS_INS_FMSUB, "fmsub" }, - { MIPS_INS_FMUL, "fmul" }, - { MIPS_INS_MUL, "mul" }, - { MIPS_INS_NEG, "neg" }, - { MIPS_INS_FRCP, "frcp" }, - { MIPS_INS_FRINT, "frint" }, - { MIPS_INS_FRSQRT, "frsqrt" }, - { MIPS_INS_FSAF, "fsaf" }, - { MIPS_INS_FSEQ, "fseq" }, - { MIPS_INS_FSLE, "fsle" }, - { MIPS_INS_FSLT, "fslt" }, - { MIPS_INS_FSNE, "fsne" }, - { MIPS_INS_FSOR, "fsor" }, - { MIPS_INS_FSQRT, "fsqrt" }, - { MIPS_INS_SQRT, "sqrt" }, - { MIPS_INS_FSUB, "fsub" }, - { MIPS_INS_SUB, "sub" }, - { MIPS_INS_FSUEQ, "fsueq" }, - { MIPS_INS_FSULE, "fsule" }, - { MIPS_INS_FSULT, "fsult" }, - { MIPS_INS_FSUNE, "fsune" }, - { MIPS_INS_FSUN, "fsun" }, - { MIPS_INS_FTINT_S, "ftint_s" }, - { MIPS_INS_FTINT_U, "ftint_u" }, - { MIPS_INS_FTQ, "ftq" }, - { MIPS_INS_FTRUNC_S, "ftrunc_s" }, - { MIPS_INS_FTRUNC_U, "ftrunc_u" }, - { MIPS_INS_HADD_S, "hadd_s" }, - { MIPS_INS_HADD_U, "hadd_u" }, - { MIPS_INS_HSUB_S, "hsub_s" }, - { MIPS_INS_HSUB_U, "hsub_u" }, - { MIPS_INS_ILVEV, "ilvev" }, - { MIPS_INS_ILVL, "ilvl" }, - { MIPS_INS_ILVOD, "ilvod" }, - { MIPS_INS_ILVR, "ilvr" }, - { MIPS_INS_INS, "ins" }, - { MIPS_INS_INSERT, "insert" }, - { MIPS_INS_INSV, "insv" }, - { MIPS_INS_INSVE, "insve" }, - { MIPS_INS_J, "j" }, - { MIPS_INS_JAL, "jal" }, - { MIPS_INS_JALR, "jalr" }, - { MIPS_INS_JALRS16, "jalrs16" }, - { MIPS_INS_JALRS, "jalrs" }, - { MIPS_INS_JALS, "jals" }, - { MIPS_INS_JALX, "jalx" }, - { MIPS_INS_JIALC, "jialc" }, - { MIPS_INS_JIC, "jic" }, - { MIPS_INS_JR, "jr" }, - { MIPS_INS_JR16, "jr16" }, - { MIPS_INS_JRADDIUSP, "jraddiusp" }, - { MIPS_INS_JRC, "jrc" }, - { MIPS_INS_JALRC, "jalrc" }, - { MIPS_INS_LB, "lb" }, - { MIPS_INS_LBU16, "lbu16" }, - { MIPS_INS_LBUX, "lbux" }, - { MIPS_INS_LBU, "lbu" }, - { MIPS_INS_LD, "ld" }, - { MIPS_INS_LDC1, "ldc1" }, - { MIPS_INS_LDC2, "ldc2" }, - { MIPS_INS_LDC3, "ldc3" }, - { MIPS_INS_LDI, "ldi" }, - { MIPS_INS_LDL, "ldl" }, - { MIPS_INS_LDPC, "ldpc" }, - { MIPS_INS_LDR, "ldr" }, - { MIPS_INS_LDXC1, "ldxc1" }, - { MIPS_INS_LH, "lh" }, - { MIPS_INS_LHU16, "lhu16" }, - { MIPS_INS_LHX, "lhx" }, - { MIPS_INS_LHU, "lhu" }, - { MIPS_INS_LI16, "li16" }, - { MIPS_INS_LL, "ll" }, - { MIPS_INS_LLD, "lld" }, - { MIPS_INS_LSA, "lsa" }, - { MIPS_INS_LUXC1, "luxc1" }, - { MIPS_INS_LUI, "lui" }, - { MIPS_INS_LW, "lw" }, - { MIPS_INS_LW16, "lw16" }, - { MIPS_INS_LWC1, "lwc1" }, - { MIPS_INS_LWC2, "lwc2" }, - { MIPS_INS_LWC3, "lwc3" }, - { MIPS_INS_LWL, "lwl" }, - { MIPS_INS_LWM16, "lwm16" }, - { MIPS_INS_LWM32, "lwm32" }, - { MIPS_INS_LWPC, "lwpc" }, - { MIPS_INS_LWP, "lwp" }, - { MIPS_INS_LWR, "lwr" }, - { MIPS_INS_LWUPC, "lwupc" }, - { MIPS_INS_LWU, "lwu" }, - { MIPS_INS_LWX, "lwx" }, - { MIPS_INS_LWXC1, "lwxc1" }, - { MIPS_INS_LWXS, "lwxs" }, - { MIPS_INS_LI, "li" }, - { MIPS_INS_MADD, "madd" }, - { MIPS_INS_MADDF, "maddf" }, - { MIPS_INS_MADDR_Q, "maddr_q" }, - { MIPS_INS_MADDU, "maddu" }, - { MIPS_INS_MADDV, "maddv" }, - { MIPS_INS_MADD_Q, "madd_q" }, - { MIPS_INS_MAQ_SA, "maq_sa" }, - { MIPS_INS_MAQ_S, "maq_s" }, - { MIPS_INS_MAXA, "maxa" }, - { MIPS_INS_MAXI_S, "maxi_s" }, - { MIPS_INS_MAXI_U, "maxi_u" }, - { MIPS_INS_MAX_A, "max_a" }, - { MIPS_INS_MAX, "max" }, - { MIPS_INS_MAX_S, "max_s" }, - { MIPS_INS_MAX_U, "max_u" }, - { MIPS_INS_MFC0, "mfc0" }, - { MIPS_INS_MFC1, "mfc1" }, - { MIPS_INS_MFC2, "mfc2" }, - { MIPS_INS_MFHC1, "mfhc1" }, - { MIPS_INS_MFHI, "mfhi" }, - { MIPS_INS_MFLO, "mflo" }, - { MIPS_INS_MINA, "mina" }, - { MIPS_INS_MINI_S, "mini_s" }, - { MIPS_INS_MINI_U, "mini_u" }, - { MIPS_INS_MIN_A, "min_a" }, - { MIPS_INS_MIN, "min" }, - { MIPS_INS_MIN_S, "min_s" }, - { MIPS_INS_MIN_U, "min_u" }, - { MIPS_INS_MOD, "mod" }, - { MIPS_INS_MODSUB, "modsub" }, - { MIPS_INS_MODU, "modu" }, - { MIPS_INS_MOD_S, "mod_s" }, - { MIPS_INS_MOD_U, "mod_u" }, - { MIPS_INS_MOVE, "move" }, - { MIPS_INS_MOVEP, "movep" }, - { MIPS_INS_MOVF, "movf" }, - { MIPS_INS_MOVN, "movn" }, - { MIPS_INS_MOVT, "movt" }, - { MIPS_INS_MOVZ, "movz" }, - { MIPS_INS_MSUB, "msub" }, - { MIPS_INS_MSUBF, "msubf" }, - { MIPS_INS_MSUBR_Q, "msubr_q" }, - { MIPS_INS_MSUBU, "msubu" }, - { MIPS_INS_MSUBV, "msubv" }, - { MIPS_INS_MSUB_Q, "msub_q" }, - { MIPS_INS_MTC0, "mtc0" }, - { MIPS_INS_MTC1, "mtc1" }, - { MIPS_INS_MTC2, "mtc2" }, - { MIPS_INS_MTHC1, "mthc1" }, - { MIPS_INS_MTHI, "mthi" }, - { MIPS_INS_MTHLIP, "mthlip" }, - { MIPS_INS_MTLO, "mtlo" }, - { MIPS_INS_MTM0, "mtm0" }, - { MIPS_INS_MTM1, "mtm1" }, - { MIPS_INS_MTM2, "mtm2" }, - { MIPS_INS_MTP0, "mtp0" }, - { MIPS_INS_MTP1, "mtp1" }, - { MIPS_INS_MTP2, "mtp2" }, - { MIPS_INS_MUH, "muh" }, - { MIPS_INS_MUHU, "muhu" }, - { MIPS_INS_MULEQ_S, "muleq_s" }, - { MIPS_INS_MULEU_S, "muleu_s" }, - { MIPS_INS_MULQ_RS, "mulq_rs" }, - { MIPS_INS_MULQ_S, "mulq_s" }, - { MIPS_INS_MULR_Q, "mulr_q" }, - { MIPS_INS_MULSAQ_S, "mulsaq_s" }, - { MIPS_INS_MULSA, "mulsa" }, - { MIPS_INS_MULT, "mult" }, - { MIPS_INS_MULTU, "multu" }, - { MIPS_INS_MULU, "mulu" }, - { MIPS_INS_MULV, "mulv" }, - { MIPS_INS_MUL_Q, "mul_q" }, - { MIPS_INS_MUL_S, "mul_s" }, - { MIPS_INS_NLOC, "nloc" }, - { MIPS_INS_NLZC, "nlzc" }, - { MIPS_INS_NMADD, "nmadd" }, - { MIPS_INS_NMSUB, "nmsub" }, - { MIPS_INS_NOR, "nor" }, - { MIPS_INS_NORI, "nori" }, - { MIPS_INS_NOT16, "not16" }, - { MIPS_INS_NOT, "not" }, - { MIPS_INS_OR, "or" }, - { MIPS_INS_OR16, "or16" }, - { MIPS_INS_ORI, "ori" }, - { MIPS_INS_PACKRL, "packrl" }, - { MIPS_INS_PAUSE, "pause" }, - { MIPS_INS_PCKEV, "pckev" }, - { MIPS_INS_PCKOD, "pckod" }, - { MIPS_INS_PCNT, "pcnt" }, - { MIPS_INS_PICK, "pick" }, - { MIPS_INS_POP, "pop" }, - { MIPS_INS_PRECEQU, "precequ" }, - { MIPS_INS_PRECEQ, "preceq" }, - { MIPS_INS_PRECEU, "preceu" }, - { MIPS_INS_PRECRQU_S, "precrqu_s" }, - { MIPS_INS_PRECRQ, "precrq" }, - { MIPS_INS_PRECRQ_RS, "precrq_rs" }, - { MIPS_INS_PRECR, "precr" }, - { MIPS_INS_PRECR_SRA, "precr_sra" }, - { MIPS_INS_PRECR_SRA_R, "precr_sra_r" }, - { MIPS_INS_PREF, "pref" }, - { MIPS_INS_PREPEND, "prepend" }, - { MIPS_INS_RADDU, "raddu" }, - { MIPS_INS_RDDSP, "rddsp" }, - { MIPS_INS_RDHWR, "rdhwr" }, - { MIPS_INS_REPLV, "replv" }, - { MIPS_INS_REPL, "repl" }, - { MIPS_INS_RINT, "rint" }, - { MIPS_INS_ROTR, "rotr" }, - { MIPS_INS_ROTRV, "rotrv" }, - { MIPS_INS_ROUND, "round" }, - { MIPS_INS_SAT_S, "sat_s" }, - { MIPS_INS_SAT_U, "sat_u" }, - { MIPS_INS_SB, "sb" }, - { MIPS_INS_SB16, "sb16" }, - { MIPS_INS_SC, "sc" }, - { MIPS_INS_SCD, "scd" }, - { MIPS_INS_SD, "sd" }, - { MIPS_INS_SDBBP, "sdbbp" }, - { MIPS_INS_SDBBP16, "sdbbp16" }, - { MIPS_INS_SDC1, "sdc1" }, - { MIPS_INS_SDC2, "sdc2" }, - { MIPS_INS_SDC3, "sdc3" }, - { MIPS_INS_SDL, "sdl" }, - { MIPS_INS_SDR, "sdr" }, - { MIPS_INS_SDXC1, "sdxc1" }, - { MIPS_INS_SEB, "seb" }, - { MIPS_INS_SEH, "seh" }, - { MIPS_INS_SELEQZ, "seleqz" }, - { MIPS_INS_SELNEZ, "selnez" }, - { MIPS_INS_SEL, "sel" }, - { MIPS_INS_SEQ, "seq" }, - { MIPS_INS_SEQI, "seqi" }, - { MIPS_INS_SH, "sh" }, - { MIPS_INS_SH16, "sh16" }, - { MIPS_INS_SHF, "shf" }, - { MIPS_INS_SHILO, "shilo" }, - { MIPS_INS_SHILOV, "shilov" }, - { MIPS_INS_SHLLV, "shllv" }, - { MIPS_INS_SHLLV_S, "shllv_s" }, - { MIPS_INS_SHLL, "shll" }, - { MIPS_INS_SHLL_S, "shll_s" }, - { MIPS_INS_SHRAV, "shrav" }, - { MIPS_INS_SHRAV_R, "shrav_r" }, - { MIPS_INS_SHRA, "shra" }, - { MIPS_INS_SHRA_R, "shra_r" }, - { MIPS_INS_SHRLV, "shrlv" }, - { MIPS_INS_SHRL, "shrl" }, - { MIPS_INS_SLDI, "sldi" }, - { MIPS_INS_SLD, "sld" }, - { MIPS_INS_SLL, "sll" }, - { MIPS_INS_SLL16, "sll16" }, - { MIPS_INS_SLLI, "slli" }, - { MIPS_INS_SLLV, "sllv" }, - { MIPS_INS_SLT, "slt" }, - { MIPS_INS_SLTI, "slti" }, - { MIPS_INS_SLTIU, "sltiu" }, - { MIPS_INS_SLTU, "sltu" }, - { MIPS_INS_SNE, "sne" }, - { MIPS_INS_SNEI, "snei" }, - { MIPS_INS_SPLATI, "splati" }, - { MIPS_INS_SPLAT, "splat" }, - { MIPS_INS_SRA, "sra" }, - { MIPS_INS_SRAI, "srai" }, - { MIPS_INS_SRARI, "srari" }, - { MIPS_INS_SRAR, "srar" }, - { MIPS_INS_SRAV, "srav" }, - { MIPS_INS_SRL, "srl" }, - { MIPS_INS_SRL16, "srl16" }, - { MIPS_INS_SRLI, "srli" }, - { MIPS_INS_SRLRI, "srlri" }, - { MIPS_INS_SRLR, "srlr" }, - { MIPS_INS_SRLV, "srlv" }, - { MIPS_INS_SSNOP, "ssnop" }, - { MIPS_INS_ST, "st" }, - { MIPS_INS_SUBQH, "subqh" }, - { MIPS_INS_SUBQH_R, "subqh_r" }, - { MIPS_INS_SUBQ, "subq" }, - { MIPS_INS_SUBQ_S, "subq_s" }, - { MIPS_INS_SUBSUS_U, "subsus_u" }, - { MIPS_INS_SUBSUU_S, "subsuu_s" }, - { MIPS_INS_SUBS_S, "subs_s" }, - { MIPS_INS_SUBS_U, "subs_u" }, - { MIPS_INS_SUBU16, "subu16" }, - { MIPS_INS_SUBUH, "subuh" }, - { MIPS_INS_SUBUH_R, "subuh_r" }, - { MIPS_INS_SUBU, "subu" }, - { MIPS_INS_SUBU_S, "subu_s" }, - { MIPS_INS_SUBVI, "subvi" }, - { MIPS_INS_SUBV, "subv" }, - { MIPS_INS_SUXC1, "suxc1" }, - { MIPS_INS_SW, "sw" }, - { MIPS_INS_SW16, "sw16" }, - { MIPS_INS_SWC1, "swc1" }, - { MIPS_INS_SWC2, "swc2" }, - { MIPS_INS_SWC3, "swc3" }, - { MIPS_INS_SWL, "swl" }, - { MIPS_INS_SWM16, "swm16" }, - { MIPS_INS_SWM32, "swm32" }, - { MIPS_INS_SWP, "swp" }, - { MIPS_INS_SWR, "swr" }, - { MIPS_INS_SWXC1, "swxc1" }, - { MIPS_INS_SYNC, "sync" }, - { MIPS_INS_SYNCI, "synci" }, - { MIPS_INS_SYSCALL, "syscall" }, - { MIPS_INS_TEQ, "teq" }, - { MIPS_INS_TEQI, "teqi" }, - { MIPS_INS_TGE, "tge" }, - { MIPS_INS_TGEI, "tgei" }, - { MIPS_INS_TGEIU, "tgeiu" }, - { MIPS_INS_TGEU, "tgeu" }, - { MIPS_INS_TLBP, "tlbp" }, - { MIPS_INS_TLBR, "tlbr" }, - { MIPS_INS_TLBWI, "tlbwi" }, - { MIPS_INS_TLBWR, "tlbwr" }, - { MIPS_INS_TLT, "tlt" }, - { MIPS_INS_TLTI, "tlti" }, - { MIPS_INS_TLTIU, "tltiu" }, - { MIPS_INS_TLTU, "tltu" }, - { MIPS_INS_TNE, "tne" }, - { MIPS_INS_TNEI, "tnei" }, - { MIPS_INS_TRUNC, "trunc" }, - { MIPS_INS_V3MULU, "v3mulu" }, - { MIPS_INS_VMM0, "vmm0" }, - { MIPS_INS_VMULU, "vmulu" }, - { MIPS_INS_VSHF, "vshf" }, - { MIPS_INS_WAIT, "wait" }, - { MIPS_INS_WRDSP, "wrdsp" }, - { MIPS_INS_WSBH, "wsbh" }, - { MIPS_INS_XOR, "xor" }, - { MIPS_INS_XOR16, "xor16" }, - { MIPS_INS_XORI, "xori" }, + memset(get_detail(MI), 0, + offsetof(cs_detail, mips) + sizeof(cs_mips)); - // alias instructions - { MIPS_INS_NOP, "nop" }, - { MIPS_INS_NEGU, "negu" }, + for (i = 0; i < ARR_SIZE(Mips_get_detail(MI)->operands); i++) + Mips_setup_op(&Mips_get_detail(MI)->operands[i]); + } +} - { MIPS_INS_JALR_HB, "jalr.hb" }, - { MIPS_INS_JR_HB, "jr.hb" }, +static const map_insn_ops insn_operands[] = { +#include "MipsGenCSMappingInsnOp.inc" }; -const char *Mips_insn_name(csh handle, unsigned int id) +static void Mips_set_detail_op_mem_reg(MCInst *MI, unsigned OpNum, mips_reg Reg) { -#ifndef CAPSTONE_DIET - if (id >= MIPS_INS_ENDING) - return NULL; + Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM; + Mips_get_detail_op(MI, 0)->mem.base = Reg; + Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); +} - return insn_name_maps[id].name; -#else - return NULL; -#endif +static void Mips_set_detail_op_mem_disp(MCInst *MI, unsigned OpNum, int64_t Imm) +{ + Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM; + Mips_get_detail_op(MI, 0)->mem.disp = Imm; + Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); } -#ifndef CAPSTONE_DIET -static const name_map group_name_maps[] = { - // generic groups - { MIPS_GRP_INVALID, NULL }, - { MIPS_GRP_JUMP, "jump" }, - { MIPS_GRP_CALL, "call" }, - { MIPS_GRP_RET, "ret" }, - { MIPS_GRP_INT, "int" }, - { MIPS_GRP_IRET, "iret" }, - { MIPS_GRP_PRIVILEGE, "privileged" }, - { MIPS_GRP_BRANCH_RELATIVE, "branch_relative" }, +static void Mips_set_detail_op_imm(MCInst *MI, unsigned OpNum, int64_t Imm) +{ + if (!detail_is_set(MI)) + return; - // architecture-specific groups - { MIPS_GRP_BITCOUNT, "bitcount" }, - { MIPS_GRP_DSP, "dsp" }, - { MIPS_GRP_DSPR2, "dspr2" }, - { MIPS_GRP_FPIDX, "fpidx" }, - { MIPS_GRP_MSA, "msa" }, - { MIPS_GRP_MIPS32R2, "mips32r2" }, - { MIPS_GRP_MIPS64, "mips64" }, - { MIPS_GRP_MIPS64R2, "mips64r2" }, - { MIPS_GRP_SEINREG, "seinreg" }, - { MIPS_GRP_STDENC, "stdenc" }, - { MIPS_GRP_SWAP, "swap" }, - { MIPS_GRP_MICROMIPS, "micromips" }, - { MIPS_GRP_MIPS16MODE, "mips16mode" }, - { MIPS_GRP_FP64BIT, "fp64bit" }, - { MIPS_GRP_NONANSFPMATH, "nonansfpmath" }, - { MIPS_GRP_NOTFP64BIT, "notfp64bit" }, - { MIPS_GRP_NOTINMICROMIPS, "notinmicromips" }, - { MIPS_GRP_NOTNACL, "notnacl" }, + if (doing_mem(MI)) { + Mips_set_detail_op_mem_disp(MI, OpNum, Imm); + return; + } + + Mips_get_detail_op(MI, 0)->type = MIPS_OP_IMM; + Mips_get_detail_op(MI, 0)->imm = Imm; + Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); + Mips_inc_op_count(MI); +} - { MIPS_GRP_NOTMIPS32R6, "notmips32r6" }, - { MIPS_GRP_NOTMIPS64R6, "notmips64r6" }, - { MIPS_GRP_CNMIPS, "cnmips" }, +static void Mips_set_detail_op_uimm(MCInst *MI, unsigned OpNum, uint64_t Imm) +{ + if (!detail_is_set(MI)) + return; - { MIPS_GRP_MIPS32, "mips32" }, - { MIPS_GRP_MIPS32R6, "mips32r6" }, - { MIPS_GRP_MIPS64R6, "mips64r6" }, + if (doing_mem(MI)) { + Mips_set_detail_op_mem_disp(MI, OpNum, Imm); + return; + } - { MIPS_GRP_MIPS2, "mips2" }, - { MIPS_GRP_MIPS3, "mips3" }, - { MIPS_GRP_MIPS3_32, "mips3_32"}, - { MIPS_GRP_MIPS3_32R2, "mips3_32r2" }, + Mips_get_detail_op(MI, 0)->type = MIPS_OP_IMM; + Mips_get_detail_op(MI, 0)->uimm = Imm; + Mips_get_detail_op(MI, 0)->is_unsigned = true; + Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); + Mips_inc_op_count(MI); +} - { MIPS_GRP_MIPS4_32, "mips4_32" }, - { MIPS_GRP_MIPS4_32R2, "mips4_32r2" }, - { MIPS_GRP_MIPS5_32R2, "mips5_32r2" }, +static void Mips_set_detail_op_reg(MCInst *MI, unsigned OpNum, mips_reg Reg, + bool is_reglist) +{ + if (!detail_is_set(MI)) + return; - { MIPS_GRP_GP32BIT, "gp32bit" }, - { MIPS_GRP_GP64BIT, "gp64bit" }, -}; -#endif + if (doing_mem(MI)) { + Mips_set_detail_op_mem_reg(MI, OpNum, Reg); + return; + } -const char *Mips_group_name(csh handle, unsigned int id) + CS_ASSERT((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG); + Mips_get_detail_op(MI, 0)->type = MIPS_OP_REG; + Mips_get_detail_op(MI, 0)->reg = Reg; + Mips_get_detail_op(MI, 0)->is_reglist = is_reglist; + Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); + Mips_inc_op_count(MI); +} + +static void Mips_set_detail_op_operand(MCInst *MI, unsigned OpNum) { -#ifndef CAPSTONE_DIET - return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); -#else - return NULL; -#endif + cs_op_type op_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM; + int64_t value = MCInst_getOpVal(MI, OpNum); + if (op_type == CS_OP_IMM) { + Mips_set_detail_op_imm(MI, OpNum, value); + } else if (op_type == CS_OP_REG) { + Mips_set_detail_op_reg(MI, OpNum, value, false); + } else + printf("Operand type %d not handled!\n", op_type); } -// map instruction name to public instruction ID -mips_reg Mips_map_insn(const char *name) +static void Mips_set_detail_op_branch(MCInst *MI, unsigned OpNum) { - // handle special alias first - unsigned int i; + cs_op_type op_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM; + if (op_type == CS_OP_IMM) { + uint64_t Target = (uint64_t)MCInst_getOpVal(MI, OpNum); + Mips_set_detail_op_uimm(MI, OpNum, Target + MI->address); + } else if (op_type == CS_OP_REG) { + Mips_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum), + false); + } else + printf("Operand type %d not handled!\n", op_type); +} - // NOTE: skip first NULL name in insn_name_maps - i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); +static void Mips_set_detail_op_unsigned(MCInst *MI, unsigned OpNum) +{ + Mips_set_detail_op_uimm(MI, OpNum, MCInst_getOpVal(MI, OpNum)); +} - return (i != -1)? i : MIPS_REG_INVALID; +static void Mips_set_detail_op_unsigned_offset(MCInst *MI, unsigned OpNum, + unsigned Bits, uint64_t Offset) +{ + uint64_t Imm = MCInst_getOpVal(MI, OpNum); + Imm -= Offset; + Imm &= (((uint64_t)1) << Bits) - 1; + Imm += Offset; + Mips_set_detail_op_uimm(MI, OpNum, Imm); } -// map internal raw register to 'public' register -mips_reg Mips_map_register(unsigned int r) +static void Mips_set_detail_op_mem_nanomips(MCInst *MI, unsigned OpNum) { - // for some reasons different Mips modes can map different register number to - // the same Mips register. this function handles the issue for exposing Mips - // operands by mapping internal registers to 'public' register. - static const unsigned int map[] = { 0, - MIPS_REG_AT, MIPS_REG_DSPCCOND, MIPS_REG_DSPCARRY, MIPS_REG_DSPEFI, MIPS_REG_DSPOUTFLAG, - MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, MIPS_REG_FP, MIPS_REG_GP, MIPS_REG_2, - MIPS_REG_1, MIPS_REG_0, MIPS_REG_6, MIPS_REG_4, MIPS_REG_5, - MIPS_REG_3, MIPS_REG_7, MIPS_REG_PC, MIPS_REG_RA, MIPS_REG_SP, - MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3, - MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, MIPS_REG_AT, - MIPS_REG_CC0, MIPS_REG_CC1, MIPS_REG_CC2, MIPS_REG_CC3, MIPS_REG_CC4, - MIPS_REG_CC5, MIPS_REG_CC6, MIPS_REG_CC7, MIPS_REG_0, MIPS_REG_1, - MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, - MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_0, MIPS_REG_1, - MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, - MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, - MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, - MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, - MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, - MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, - MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, - MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, - MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, - MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, - MIPS_REG_30, MIPS_REG_31, MIPS_REG_F0, MIPS_REG_F2, MIPS_REG_F4, - MIPS_REG_F6, MIPS_REG_F8, MIPS_REG_F10, MIPS_REG_F12, MIPS_REG_F14, - MIPS_REG_F16, MIPS_REG_F18, MIPS_REG_F20, MIPS_REG_F22, MIPS_REG_F24, - MIPS_REG_F26, MIPS_REG_F28, MIPS_REG_F30, MIPS_REG_DSPOUTFLAG20, MIPS_REG_DSPOUTFLAG21, - MIPS_REG_DSPOUTFLAG22, MIPS_REG_DSPOUTFLAG23, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, - MIPS_REG_F3, MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, - MIPS_REG_F8, MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, - MIPS_REG_F13, MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, - MIPS_REG_F18, MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, - MIPS_REG_F23, MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, - MIPS_REG_F28, MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_FCC0, - MIPS_REG_FCC1, MIPS_REG_FCC2, MIPS_REG_FCC3, MIPS_REG_FCC4, MIPS_REG_FCC5, - MIPS_REG_FCC6, MIPS_REG_FCC7, MIPS_REG_0, MIPS_REG_1, MIPS_REG_2, - MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, - MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, - MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, - MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, - MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, - MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_FP, - MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, MIPS_REG_F4, - MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, MIPS_REG_F9, - MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, MIPS_REG_F14, - MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, MIPS_REG_F19, - MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, MIPS_REG_F24, - MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, MIPS_REG_F29, - MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_GP, MIPS_REG_AC0, MIPS_REG_AC1, - MIPS_REG_AC2, MIPS_REG_AC3, 0, 0, 0, - 0, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, - MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, - MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, - MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, - MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, - MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_K0, - MIPS_REG_K1, MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, - MIPS_REG_MPL0, MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, - MIPS_REG_P2, MIPS_REG_RA, MIPS_REG_S0, MIPS_REG_S1, MIPS_REG_S2, - MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6, MIPS_REG_S7, - MIPS_REG_SP, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3, - MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8, - MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1, MIPS_REG_W0, MIPS_REG_W1, - MIPS_REG_W2, MIPS_REG_W3, MIPS_REG_W4, MIPS_REG_W5, MIPS_REG_W6, - MIPS_REG_W7, MIPS_REG_W8, MIPS_REG_W9, MIPS_REG_W10, MIPS_REG_W11, - MIPS_REG_W12, MIPS_REG_W13, MIPS_REG_W14, MIPS_REG_W15, MIPS_REG_W16, - MIPS_REG_W17, MIPS_REG_W18, MIPS_REG_W19, MIPS_REG_W20, MIPS_REG_W21, - MIPS_REG_W22, MIPS_REG_W23, MIPS_REG_W24, MIPS_REG_W25, MIPS_REG_W26, - MIPS_REG_W27, MIPS_REG_W28, MIPS_REG_W29, MIPS_REG_W30, MIPS_REG_W31, - MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3, - MIPS_REG_AC0, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, - MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, - MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, - MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, - MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, - MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, - MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_DSPOUTFLAG16_19, MIPS_REG_HI, - MIPS_REG_K0, MIPS_REG_K1, MIPS_REG_LO, MIPS_REG_S0, MIPS_REG_S1, - MIPS_REG_S2, MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6, - MIPS_REG_S7, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3, - MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8, - MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1 - }; + CS_ASSERT(doing_mem(MI)) - if (r < ARR_SIZE(map)) - return map[r]; + MCOperand *Op = MCInst_getOperand(MI, OpNum); + Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM; + // Base is a register, but nanoMips uses the Imm value as register. + Mips_get_detail_op(MI, 0)->mem.base = MCOperand_getImm(Op); + Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); +} - // cannot find this register - return 0; +static void Mips_set_detail_op_reglist(MCInst *MI, unsigned OpNum, + bool isNanoMips) +{ + if (isNanoMips) { + for (unsigned i = OpNum; i < MCInst_getNumOperands(MI); i++) { + Mips_set_detail_op_reg(MI, i, MCInst_getOpVal(MI, i), + true); + } + return; + } + // -2 because register List is always first operand of instruction + // and it is always followed by memory operand (base + offset). + for (unsigned i = OpNum, e = MCInst_getNumOperands(MI) - 2; i != e; + ++i) { + Mips_set_detail_op_reg(MI, i, MCInst_getOpVal(MI, i), true); + } +} + +static void Mips_set_detail_op_unsigned_address(MCInst *MI, unsigned OpNum) +{ + uint64_t Target = MI->address + (uint64_t)MCInst_getOpVal(MI, OpNum); + Mips_set_detail_op_imm(MI, OpNum, Target); +} + +void Mips_add_cs_detail(MCInst *MI, mips_op_group op_group, va_list args) +{ + if (!detail_is_set(MI) || !map_fill_detail_ops(MI)) + return; + + unsigned OpNum = va_arg(args, unsigned); + + switch (op_group) { + default: + printf("Operand group %d not handled!\n", op_group); + return; + case Mips_OP_GROUP_MemOperand: + // this is only used by nanoMips. + return Mips_set_detail_op_mem_nanomips(MI, OpNum); + case Mips_OP_GROUP_BranchOperand: + /* fall-thru */ + case Mips_OP_GROUP_JumpOperand: + return Mips_set_detail_op_branch(MI, OpNum); + case Mips_OP_GROUP_Operand: + return Mips_set_detail_op_operand(MI, OpNum); + case Mips_OP_GROUP_UImm_1_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 1, 0); + case Mips_OP_GROUP_UImm_2_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 2, 0); + case Mips_OP_GROUP_UImm_3_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 3, 0); + case Mips_OP_GROUP_UImm_32_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 32, 0); + case Mips_OP_GROUP_UImm_16_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 16, 0); + case Mips_OP_GROUP_UImm_8_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 8, 0); + case Mips_OP_GROUP_UImm_5_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 0); + case Mips_OP_GROUP_UImm_6_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 6, 0); + case Mips_OP_GROUP_UImm_4_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 4, 0); + case Mips_OP_GROUP_UImm_7_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 7, 0); + case Mips_OP_GROUP_UImm_10_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 10, 0); + case Mips_OP_GROUP_UImm_6_1: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 6, 1); + case Mips_OP_GROUP_UImm_5_1: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 1); + case Mips_OP_GROUP_UImm_5_33: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 33); + case Mips_OP_GROUP_UImm_5_32: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 32); + case Mips_OP_GROUP_UImm_6_2: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 6, 2); + case Mips_OP_GROUP_UImm_2_1: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 2, 1); + case Mips_OP_GROUP_UImm_0_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 0, 0); + case Mips_OP_GROUP_UImm_26_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 26, 0); + case Mips_OP_GROUP_UImm_12_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 12, 0); + case Mips_OP_GROUP_UImm_20_0: + return Mips_set_detail_op_unsigned_offset(MI, OpNum, 20, 0); + case Mips_OP_GROUP_RegisterList: + return Mips_set_detail_op_reglist(MI, OpNum, false); + case Mips_OP_GROUP_NanoMipsRegisterList: + return Mips_set_detail_op_reglist(MI, OpNum, true); + case Mips_OP_GROUP_PCRel: + /* fall-thru */ + case Mips_OP_GROUP_Hi20PCRel: + return Mips_set_detail_op_unsigned_address(MI, OpNum); + case Mips_OP_GROUP_Hi20: + return Mips_set_detail_op_unsigned(MI, OpNum); + } +} + +void Mips_set_mem_access(MCInst *MI, bool status) +{ + if (!detail_is_set(MI)) + return; + set_doing_mem(MI, status); + if (status) { + if (Mips_get_detail(MI)->op_count > 0 && + Mips_get_detail_op(MI, -1)->type == MIPS_OP_MEM && + Mips_get_detail_op(MI, -1)->mem.disp == 0) { + // Previous memory operand not done yet. Select it. + Mips_dec_op_count(MI); + return; + } + + // Init a new one. + Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM; + Mips_get_detail_op(MI, 0)->mem.base = MIPS_REG_INVALID; + Mips_get_detail_op(MI, 0)->mem.disp = 0; + +#ifndef CAPSTONE_DIET + uint8_t access = + map_get_op_access(MI, Mips_get_detail(MI)->op_count); + Mips_get_detail_op(MI, 0)->access = access; +#endif + } else { + // done, select the next operand slot + Mips_inc_op_count(MI); + } } #endif diff --git a/arch/Mips/MipsMapping.h b/arch/Mips/MipsMapping.h index 2b5c95dce5..4f73be7fde 100644 --- a/arch/Mips/MipsMapping.h +++ b/arch/Mips/MipsMapping.h @@ -1,25 +1,62 @@ /* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* By Giovanni Dante Grazioli, deroad , 2024 */ -#ifndef CS_MIPS_MAP_H -#define CS_MIPS_MAP_H +#ifndef CS_MIPS_MAPPING_H +#define CS_MIPS_MAPPING_H -#include "capstone/capstone.h" +#include "../../include/capstone/capstone.h" +#include "../../utils.h" +#include "../../Mapping.h" + +typedef enum { +#include "MipsGenCSOpGroup.inc" +} mips_op_group; + +void Mips_init_mri(MCRegisterInfo *MRI); // return name of register in friendly string const char *Mips_reg_name(csh handle, unsigned int reg); -// given internal insn id, return public instruction info +void Mips_printer(MCInst *MI, SStream *O, + void * /* MCRegisterInfo* */ info); + +// given internal insn id, return public instruction ID void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); const char *Mips_insn_name(csh handle, unsigned int id); const char *Mips_group_name(csh handle, unsigned int id); -// map instruction name to instruction ID -mips_reg Mips_map_insn(const char *name); +bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, + void *info); + +void Mips_reg_access(const cs_insn *insn, cs_regs regs_read, + uint8_t *regs_read_count, cs_regs regs_write, + uint8_t *regs_write_count); + +// cs_detail related functions +void Mips_init_cs_detail(MCInst *MI); + +void Mips_set_mem_access(MCInst *MI, bool status); + +void Mips_add_cs_detail(MCInst *MI, mips_op_group op_group, va_list args); + +static inline void add_cs_detail(MCInst *MI, mips_op_group op_group, ...) +{ + if (!detail_is_set(MI)) + return; + va_list args; + va_start(args, op_group); + Mips_add_cs_detail(MI, op_group, args); + va_end(args); +} -// map internal raw register to 'public' register -mips_reg Mips_map_register(unsigned int r); +static inline void set_mem_access(MCInst *MI, bool status) +{ + if (!detail_is_set(MI)) + return; + Mips_set_mem_access(MI, status); +} -#endif +#endif // CS_MIPS_MAPPING_H diff --git a/arch/Mips/MipsModule.c b/arch/Mips/MipsModule.c index e06871d3b4..6a1a963cb5 100644 --- a/arch/Mips/MipsModule.c +++ b/arch/Mips/MipsModule.c @@ -1,52 +1,52 @@ /* Capstone Disassembly Engine */ -/* By Dang Hoang Vu 2013 */ +/* By Giovanni Dante Grazioli, deroad , 2024 */ #ifdef CAPSTONE_HAS_MIPS -#include "../../utils.h" +#include + +#include "MipsModule.h" #include "../../MCRegisterInfo.h" -#include "MipsDisassembler.h" -#include "MipsInstPrinter.h" +#include "../../cs_priv.h" #include "MipsMapping.h" -#include "MipsModule.h" - -// Returns mode value with implied bits set -static cs_mode updated_mode(cs_mode mode) -{ - if (mode & CS_MODE_MIPS32R6) { - mode |= CS_MODE_32; - } - - return mode; -} cs_err Mips_global_init(cs_struct *ud) { MCRegisterInfo *mri; mri = cs_mem_malloc(sizeof(*mri)); - Mips_init(mri); - ud->printer = Mips_printInst; + Mips_init_mri(mri); + + ud->printer = Mips_printer; ud->printer_info = mri; ud->getinsn_info = mri; ud->reg_name = Mips_reg_name; ud->insn_id = Mips_get_insn_id; ud->insn_name = Mips_insn_name; ud->group_name = Mips_group_name; - ud->disasm = Mips_getInstruction; + ud->post_printer = NULL; +#ifndef CAPSTONE_DIET + ud->reg_access = Mips_reg_access; +#endif return CS_ERR_OK; } cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value) { - if (type == CS_OPT_MODE) { - handle->mode = updated_mode(value); - return CS_ERR_OK; + switch (type) { + case CS_OPT_MODE: + handle->mode = (cs_mode)value; + break; + case CS_OPT_SYNTAX: + handle->syntax |= (int)value; + break; + default: + break; } - return CS_ERR_OPTION; + return CS_ERR_OK; } #endif diff --git a/arch/Mips/MipsModule.h b/arch/Mips/MipsModule.h index d1aa2cfff8..b404171ddf 100644 --- a/arch/Mips/MipsModule.h +++ b/arch/Mips/MipsModule.h @@ -1,5 +1,5 @@ /* Capstone Disassembly Engine */ -/* By Travis Finkenauer , 2018 */ +/* By Giovanni Dante Grazioli, deroad , 2024 */ #ifndef CS_MIPS_MODULE_H #define CS_MIPS_MODULE_H @@ -9,4 +9,4 @@ cs_err Mips_global_init(cs_struct *ud); cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value); -#endif +#endif // CS_MIPS_MODULE_H diff --git a/bindings/java/capstone/Capstone.java b/bindings/java/capstone/Capstone.java index 1a37b5d400..8e5639b23f 100644 --- a/bindings/java/capstone/Capstone.java +++ b/bindings/java/capstone/Capstone.java @@ -84,7 +84,7 @@ public static class ByReference extends _cs_detail implements Structure.ByRefere public short[] regs_write = new short[20]; public byte regs_write_count; // list of semantic groups this instruction belongs to. - public byte[] groups = new byte[8]; + public byte[] groups = new byte[16]; public byte groups_count; public UnionArch arch; diff --git a/bindings/java/capstone/Mips_const.java b/bindings/java/capstone/Mips_const.java index 01f637f80e..a1b66910c6 100644 --- a/bindings/java/capstone/Mips_const.java +++ b/bindings/java/capstone/Mips_const.java @@ -9,816 +9,2111 @@ public class Mips_const { public static final int MIPS_OP_MEM = 3; public static final int MIPS_REG_INVALID = 0; - public static final int MIPS_REG_PC = 1; - public static final int MIPS_REG_0 = 2; - public static final int MIPS_REG_1 = 3; - public static final int MIPS_REG_2 = 4; - public static final int MIPS_REG_3 = 5; - public static final int MIPS_REG_4 = 6; - public static final int MIPS_REG_5 = 7; - public static final int MIPS_REG_6 = 8; - public static final int MIPS_REG_7 = 9; - public static final int MIPS_REG_8 = 10; - public static final int MIPS_REG_9 = 11; - public static final int MIPS_REG_10 = 12; - public static final int MIPS_REG_11 = 13; - public static final int MIPS_REG_12 = 14; - public static final int MIPS_REG_13 = 15; - public static final int MIPS_REG_14 = 16; - public static final int MIPS_REG_15 = 17; - public static final int MIPS_REG_16 = 18; - public static final int MIPS_REG_17 = 19; - public static final int MIPS_REG_18 = 20; - public static final int MIPS_REG_19 = 21; - public static final int MIPS_REG_20 = 22; - public static final int MIPS_REG_21 = 23; - public static final int MIPS_REG_22 = 24; - public static final int MIPS_REG_23 = 25; - public static final int MIPS_REG_24 = 26; - public static final int MIPS_REG_25 = 27; - public static final int MIPS_REG_26 = 28; - public static final int MIPS_REG_27 = 29; - public static final int MIPS_REG_28 = 30; - public static final int MIPS_REG_29 = 31; - public static final int MIPS_REG_30 = 32; - public static final int MIPS_REG_31 = 33; - public static final int MIPS_REG_DSPCCOND = 34; - public static final int MIPS_REG_DSPCARRY = 35; - public static final int MIPS_REG_DSPEFI = 36; - public static final int MIPS_REG_DSPOUTFLAG = 37; - public static final int MIPS_REG_DSPOUTFLAG16_19 = 38; - public static final int MIPS_REG_DSPOUTFLAG20 = 39; - public static final int MIPS_REG_DSPOUTFLAG21 = 40; - public static final int MIPS_REG_DSPOUTFLAG22 = 41; - public static final int MIPS_REG_DSPOUTFLAG23 = 42; - public static final int MIPS_REG_DSPPOS = 43; - public static final int MIPS_REG_DSPSCOUNT = 44; - public static final int MIPS_REG_AC0 = 45; - public static final int MIPS_REG_AC1 = 46; - public static final int MIPS_REG_AC2 = 47; - public static final int MIPS_REG_AC3 = 48; - public static final int MIPS_REG_CC0 = 49; - public static final int MIPS_REG_CC1 = 50; - public static final int MIPS_REG_CC2 = 51; - public static final int MIPS_REG_CC3 = 52; - public static final int MIPS_REG_CC4 = 53; - public static final int MIPS_REG_CC5 = 54; - public static final int MIPS_REG_CC6 = 55; - public static final int MIPS_REG_CC7 = 56; - public static final int MIPS_REG_F0 = 57; - public static final int MIPS_REG_F1 = 58; - public static final int MIPS_REG_F2 = 59; - public static final int MIPS_REG_F3 = 60; - public static final int MIPS_REG_F4 = 61; - public static final int MIPS_REG_F5 = 62; - public static final int MIPS_REG_F6 = 63; - public static final int MIPS_REG_F7 = 64; - public static final int MIPS_REG_F8 = 65; - public static final int MIPS_REG_F9 = 66; - public static final int MIPS_REG_F10 = 67; - public static final int MIPS_REG_F11 = 68; - public static final int MIPS_REG_F12 = 69; - public static final int MIPS_REG_F13 = 70; - public static final int MIPS_REG_F14 = 71; - public static final int MIPS_REG_F15 = 72; - public static final int MIPS_REG_F16 = 73; - public static final int MIPS_REG_F17 = 74; - public static final int MIPS_REG_F18 = 75; - public static final int MIPS_REG_F19 = 76; - public static final int MIPS_REG_F20 = 77; - public static final int MIPS_REG_F21 = 78; - public static final int MIPS_REG_F22 = 79; - public static final int MIPS_REG_F23 = 80; - public static final int MIPS_REG_F24 = 81; - public static final int MIPS_REG_F25 = 82; - public static final int MIPS_REG_F26 = 83; - public static final int MIPS_REG_F27 = 84; - public static final int MIPS_REG_F28 = 85; - public static final int MIPS_REG_F29 = 86; - public static final int MIPS_REG_F30 = 87; - public static final int MIPS_REG_F31 = 88; - public static final int MIPS_REG_FCC0 = 89; - public static final int MIPS_REG_FCC1 = 90; - public static final int MIPS_REG_FCC2 = 91; - public static final int MIPS_REG_FCC3 = 92; - public static final int MIPS_REG_FCC4 = 93; - public static final int MIPS_REG_FCC5 = 94; - public static final int MIPS_REG_FCC6 = 95; - public static final int MIPS_REG_FCC7 = 96; - public static final int MIPS_REG_W0 = 97; - public static final int MIPS_REG_W1 = 98; - public static final int MIPS_REG_W2 = 99; - public static final int MIPS_REG_W3 = 100; - public static final int MIPS_REG_W4 = 101; - public static final int MIPS_REG_W5 = 102; - public static final int MIPS_REG_W6 = 103; - public static final int MIPS_REG_W7 = 104; - public static final int MIPS_REG_W8 = 105; - public static final int MIPS_REG_W9 = 106; - public static final int MIPS_REG_W10 = 107; - public static final int MIPS_REG_W11 = 108; - public static final int MIPS_REG_W12 = 109; - public static final int MIPS_REG_W13 = 110; - public static final int MIPS_REG_W14 = 111; - public static final int MIPS_REG_W15 = 112; - public static final int MIPS_REG_W16 = 113; - public static final int MIPS_REG_W17 = 114; - public static final int MIPS_REG_W18 = 115; - public static final int MIPS_REG_W19 = 116; - public static final int MIPS_REG_W20 = 117; - public static final int MIPS_REG_W21 = 118; - public static final int MIPS_REG_W22 = 119; - public static final int MIPS_REG_W23 = 120; - public static final int MIPS_REG_W24 = 121; - public static final int MIPS_REG_W25 = 122; - public static final int MIPS_REG_W26 = 123; - public static final int MIPS_REG_W27 = 124; - public static final int MIPS_REG_W28 = 125; - public static final int MIPS_REG_W29 = 126; - public static final int MIPS_REG_W30 = 127; - public static final int MIPS_REG_W31 = 128; - public static final int MIPS_REG_HI = 129; - public static final int MIPS_REG_LO = 130; - public static final int MIPS_REG_P0 = 131; - public static final int MIPS_REG_P1 = 132; - public static final int MIPS_REG_P2 = 133; - public static final int MIPS_REG_MPL0 = 134; - public static final int MIPS_REG_MPL1 = 135; - public static final int MIPS_REG_MPL2 = 136; - public static final int MIPS_REG_ENDING = 137; - public static final int MIPS_REG_ZERO = MIPS_REG_0; - public static final int MIPS_REG_AT = MIPS_REG_1; - public static final int MIPS_REG_V0 = MIPS_REG_2; - public static final int MIPS_REG_V1 = MIPS_REG_3; - public static final int MIPS_REG_A0 = MIPS_REG_4; - public static final int MIPS_REG_A1 = MIPS_REG_5; - public static final int MIPS_REG_A2 = MIPS_REG_6; - public static final int MIPS_REG_A3 = MIPS_REG_7; - public static final int MIPS_REG_T0 = MIPS_REG_8; - public static final int MIPS_REG_T1 = MIPS_REG_9; - public static final int MIPS_REG_T2 = MIPS_REG_10; - public static final int MIPS_REG_T3 = MIPS_REG_11; - public static final int MIPS_REG_T4 = MIPS_REG_12; - public static final int MIPS_REG_T5 = MIPS_REG_13; - public static final int MIPS_REG_T6 = MIPS_REG_14; - public static final int MIPS_REG_T7 = MIPS_REG_15; - public static final int MIPS_REG_S0 = MIPS_REG_16; - public static final int MIPS_REG_S1 = MIPS_REG_17; - public static final int MIPS_REG_S2 = MIPS_REG_18; - public static final int MIPS_REG_S3 = MIPS_REG_19; - public static final int MIPS_REG_S4 = MIPS_REG_20; - public static final int MIPS_REG_S5 = MIPS_REG_21; - public static final int MIPS_REG_S6 = MIPS_REG_22; - public static final int MIPS_REG_S7 = MIPS_REG_23; - public static final int MIPS_REG_T8 = MIPS_REG_24; - public static final int MIPS_REG_T9 = MIPS_REG_25; - public static final int MIPS_REG_K0 = MIPS_REG_26; - public static final int MIPS_REG_K1 = MIPS_REG_27; - public static final int MIPS_REG_GP = MIPS_REG_28; - public static final int MIPS_REG_SP = MIPS_REG_29; - public static final int MIPS_REG_FP = MIPS_REG_30; - public static final int MIPS_REG_S8 = MIPS_REG_30; - public static final int MIPS_REG_RA = MIPS_REG_31; - public static final int MIPS_REG_HI0 = MIPS_REG_AC0; - public static final int MIPS_REG_HI1 = MIPS_REG_AC1; - public static final int MIPS_REG_HI2 = MIPS_REG_AC2; - public static final int MIPS_REG_HI3 = MIPS_REG_AC3; - public static final int MIPS_REG_LO0 = MIPS_REG_HI0; - public static final int MIPS_REG_LO1 = MIPS_REG_HI1; - public static final int MIPS_REG_LO2 = MIPS_REG_HI2; - public static final int MIPS_REG_LO3 = MIPS_REG_HI3; + public static final int MIPS_REG_AT = 1; + public static final int MIPS_REG_AT_NM = 2; + public static final int MIPS_REG_DSPCCOND = 3; + public static final int MIPS_REG_DSPCARRY = 4; + public static final int MIPS_REG_DSPEFI = 5; + public static final int MIPS_REG_DSPOUTFLAG = 6; + public static final int MIPS_REG_DSPPOS = 7; + public static final int MIPS_REG_DSPSCOUNT = 8; + public static final int MIPS_REG_FP = 9; + public static final int MIPS_REG_FP_NM = 10; + public static final int MIPS_REG_GP = 11; + public static final int MIPS_REG_GP_NM = 12; + public static final int MIPS_REG_MSAACCESS = 13; + public static final int MIPS_REG_MSACSR = 14; + public static final int MIPS_REG_MSAIR = 15; + public static final int MIPS_REG_MSAMAP = 16; + public static final int MIPS_REG_MSAMODIFY = 17; + public static final int MIPS_REG_MSAREQUEST = 18; + public static final int MIPS_REG_MSASAVE = 19; + public static final int MIPS_REG_MSAUNMAP = 20; + public static final int MIPS_REG_PC = 21; + public static final int MIPS_REG_RA = 22; + public static final int MIPS_REG_RA_NM = 23; + public static final int MIPS_REG_SP = 24; + public static final int MIPS_REG_SP_NM = 25; + public static final int MIPS_REG_ZERO = 26; + public static final int MIPS_REG_ZERO_NM = 27; + public static final int MIPS_REG_A0 = 28; + public static final int MIPS_REG_A1 = 29; + public static final int MIPS_REG_A2 = 30; + public static final int MIPS_REG_A3 = 31; + public static final int MIPS_REG_AC0 = 32; + public static final int MIPS_REG_AC1 = 33; + public static final int MIPS_REG_AC2 = 34; + public static final int MIPS_REG_AC3 = 35; + public static final int MIPS_REG_AT_64 = 36; + public static final int MIPS_REG_COP00 = 37; + public static final int MIPS_REG_COP01 = 38; + public static final int MIPS_REG_COP02 = 39; + public static final int MIPS_REG_COP03 = 40; + public static final int MIPS_REG_COP04 = 41; + public static final int MIPS_REG_COP05 = 42; + public static final int MIPS_REG_COP06 = 43; + public static final int MIPS_REG_COP07 = 44; + public static final int MIPS_REG_COP08 = 45; + public static final int MIPS_REG_COP09 = 46; + public static final int MIPS_REG_COP20 = 47; + public static final int MIPS_REG_COP21 = 48; + public static final int MIPS_REG_COP22 = 49; + public static final int MIPS_REG_COP23 = 50; + public static final int MIPS_REG_COP24 = 51; + public static final int MIPS_REG_COP25 = 52; + public static final int MIPS_REG_COP26 = 53; + public static final int MIPS_REG_COP27 = 54; + public static final int MIPS_REG_COP28 = 55; + public static final int MIPS_REG_COP29 = 56; + public static final int MIPS_REG_COP30 = 57; + public static final int MIPS_REG_COP31 = 58; + public static final int MIPS_REG_COP32 = 59; + public static final int MIPS_REG_COP33 = 60; + public static final int MIPS_REG_COP34 = 61; + public static final int MIPS_REG_COP35 = 62; + public static final int MIPS_REG_COP36 = 63; + public static final int MIPS_REG_COP37 = 64; + public static final int MIPS_REG_COP38 = 65; + public static final int MIPS_REG_COP39 = 66; + public static final int MIPS_REG_COP010 = 67; + public static final int MIPS_REG_COP011 = 68; + public static final int MIPS_REG_COP012 = 69; + public static final int MIPS_REG_COP013 = 70; + public static final int MIPS_REG_COP014 = 71; + public static final int MIPS_REG_COP015 = 72; + public static final int MIPS_REG_COP016 = 73; + public static final int MIPS_REG_COP017 = 74; + public static final int MIPS_REG_COP018 = 75; + public static final int MIPS_REG_COP019 = 76; + public static final int MIPS_REG_COP020 = 77; + public static final int MIPS_REG_COP021 = 78; + public static final int MIPS_REG_COP022 = 79; + public static final int MIPS_REG_COP023 = 80; + public static final int MIPS_REG_COP024 = 81; + public static final int MIPS_REG_COP025 = 82; + public static final int MIPS_REG_COP026 = 83; + public static final int MIPS_REG_COP027 = 84; + public static final int MIPS_REG_COP028 = 85; + public static final int MIPS_REG_COP029 = 86; + public static final int MIPS_REG_COP030 = 87; + public static final int MIPS_REG_COP031 = 88; + public static final int MIPS_REG_COP210 = 89; + public static final int MIPS_REG_COP211 = 90; + public static final int MIPS_REG_COP212 = 91; + public static final int MIPS_REG_COP213 = 92; + public static final int MIPS_REG_COP214 = 93; + public static final int MIPS_REG_COP215 = 94; + public static final int MIPS_REG_COP216 = 95; + public static final int MIPS_REG_COP217 = 96; + public static final int MIPS_REG_COP218 = 97; + public static final int MIPS_REG_COP219 = 98; + public static final int MIPS_REG_COP220 = 99; + public static final int MIPS_REG_COP221 = 100; + public static final int MIPS_REG_COP222 = 101; + public static final int MIPS_REG_COP223 = 102; + public static final int MIPS_REG_COP224 = 103; + public static final int MIPS_REG_COP225 = 104; + public static final int MIPS_REG_COP226 = 105; + public static final int MIPS_REG_COP227 = 106; + public static final int MIPS_REG_COP228 = 107; + public static final int MIPS_REG_COP229 = 108; + public static final int MIPS_REG_COP230 = 109; + public static final int MIPS_REG_COP231 = 110; + public static final int MIPS_REG_COP310 = 111; + public static final int MIPS_REG_COP311 = 112; + public static final int MIPS_REG_COP312 = 113; + public static final int MIPS_REG_COP313 = 114; + public static final int MIPS_REG_COP314 = 115; + public static final int MIPS_REG_COP315 = 116; + public static final int MIPS_REG_COP316 = 117; + public static final int MIPS_REG_COP317 = 118; + public static final int MIPS_REG_COP318 = 119; + public static final int MIPS_REG_COP319 = 120; + public static final int MIPS_REG_COP320 = 121; + public static final int MIPS_REG_COP321 = 122; + public static final int MIPS_REG_COP322 = 123; + public static final int MIPS_REG_COP323 = 124; + public static final int MIPS_REG_COP324 = 125; + public static final int MIPS_REG_COP325 = 126; + public static final int MIPS_REG_COP326 = 127; + public static final int MIPS_REG_COP327 = 128; + public static final int MIPS_REG_COP328 = 129; + public static final int MIPS_REG_COP329 = 130; + public static final int MIPS_REG_COP330 = 131; + public static final int MIPS_REG_COP331 = 132; + public static final int MIPS_REG_D0 = 133; + public static final int MIPS_REG_D1 = 134; + public static final int MIPS_REG_D2 = 135; + public static final int MIPS_REG_D3 = 136; + public static final int MIPS_REG_D4 = 137; + public static final int MIPS_REG_D5 = 138; + public static final int MIPS_REG_D6 = 139; + public static final int MIPS_REG_D7 = 140; + public static final int MIPS_REG_D8 = 141; + public static final int MIPS_REG_D9 = 142; + public static final int MIPS_REG_D10 = 143; + public static final int MIPS_REG_D11 = 144; + public static final int MIPS_REG_D12 = 145; + public static final int MIPS_REG_D13 = 146; + public static final int MIPS_REG_D14 = 147; + public static final int MIPS_REG_D15 = 148; + public static final int MIPS_REG_DSPOUTFLAG20 = 149; + public static final int MIPS_REG_DSPOUTFLAG21 = 150; + public static final int MIPS_REG_DSPOUTFLAG22 = 151; + public static final int MIPS_REG_DSPOUTFLAG23 = 152; + public static final int MIPS_REG_F0 = 153; + public static final int MIPS_REG_F1 = 154; + public static final int MIPS_REG_F2 = 155; + public static final int MIPS_REG_F3 = 156; + public static final int MIPS_REG_F4 = 157; + public static final int MIPS_REG_F5 = 158; + public static final int MIPS_REG_F6 = 159; + public static final int MIPS_REG_F7 = 160; + public static final int MIPS_REG_F8 = 161; + public static final int MIPS_REG_F9 = 162; + public static final int MIPS_REG_F10 = 163; + public static final int MIPS_REG_F11 = 164; + public static final int MIPS_REG_F12 = 165; + public static final int MIPS_REG_F13 = 166; + public static final int MIPS_REG_F14 = 167; + public static final int MIPS_REG_F15 = 168; + public static final int MIPS_REG_F16 = 169; + public static final int MIPS_REG_F17 = 170; + public static final int MIPS_REG_F18 = 171; + public static final int MIPS_REG_F19 = 172; + public static final int MIPS_REG_F20 = 173; + public static final int MIPS_REG_F21 = 174; + public static final int MIPS_REG_F22 = 175; + public static final int MIPS_REG_F23 = 176; + public static final int MIPS_REG_F24 = 177; + public static final int MIPS_REG_F25 = 178; + public static final int MIPS_REG_F26 = 179; + public static final int MIPS_REG_F27 = 180; + public static final int MIPS_REG_F28 = 181; + public static final int MIPS_REG_F29 = 182; + public static final int MIPS_REG_F30 = 183; + public static final int MIPS_REG_F31 = 184; + public static final int MIPS_REG_FCC0 = 185; + public static final int MIPS_REG_FCC1 = 186; + public static final int MIPS_REG_FCC2 = 187; + public static final int MIPS_REG_FCC3 = 188; + public static final int MIPS_REG_FCC4 = 189; + public static final int MIPS_REG_FCC5 = 190; + public static final int MIPS_REG_FCC6 = 191; + public static final int MIPS_REG_FCC7 = 192; + public static final int MIPS_REG_FCR0 = 193; + public static final int MIPS_REG_FCR1 = 194; + public static final int MIPS_REG_FCR2 = 195; + public static final int MIPS_REG_FCR3 = 196; + public static final int MIPS_REG_FCR4 = 197; + public static final int MIPS_REG_FCR5 = 198; + public static final int MIPS_REG_FCR6 = 199; + public static final int MIPS_REG_FCR7 = 200; + public static final int MIPS_REG_FCR8 = 201; + public static final int MIPS_REG_FCR9 = 202; + public static final int MIPS_REG_FCR10 = 203; + public static final int MIPS_REG_FCR11 = 204; + public static final int MIPS_REG_FCR12 = 205; + public static final int MIPS_REG_FCR13 = 206; + public static final int MIPS_REG_FCR14 = 207; + public static final int MIPS_REG_FCR15 = 208; + public static final int MIPS_REG_FCR16 = 209; + public static final int MIPS_REG_FCR17 = 210; + public static final int MIPS_REG_FCR18 = 211; + public static final int MIPS_REG_FCR19 = 212; + public static final int MIPS_REG_FCR20 = 213; + public static final int MIPS_REG_FCR21 = 214; + public static final int MIPS_REG_FCR22 = 215; + public static final int MIPS_REG_FCR23 = 216; + public static final int MIPS_REG_FCR24 = 217; + public static final int MIPS_REG_FCR25 = 218; + public static final int MIPS_REG_FCR26 = 219; + public static final int MIPS_REG_FCR27 = 220; + public static final int MIPS_REG_FCR28 = 221; + public static final int MIPS_REG_FCR29 = 222; + public static final int MIPS_REG_FCR30 = 223; + public static final int MIPS_REG_FCR31 = 224; + public static final int MIPS_REG_FP_64 = 225; + public static final int MIPS_REG_F_HI0 = 226; + public static final int MIPS_REG_F_HI1 = 227; + public static final int MIPS_REG_F_HI2 = 228; + public static final int MIPS_REG_F_HI3 = 229; + public static final int MIPS_REG_F_HI4 = 230; + public static final int MIPS_REG_F_HI5 = 231; + public static final int MIPS_REG_F_HI6 = 232; + public static final int MIPS_REG_F_HI7 = 233; + public static final int MIPS_REG_F_HI8 = 234; + public static final int MIPS_REG_F_HI9 = 235; + public static final int MIPS_REG_F_HI10 = 236; + public static final int MIPS_REG_F_HI11 = 237; + public static final int MIPS_REG_F_HI12 = 238; + public static final int MIPS_REG_F_HI13 = 239; + public static final int MIPS_REG_F_HI14 = 240; + public static final int MIPS_REG_F_HI15 = 241; + public static final int MIPS_REG_F_HI16 = 242; + public static final int MIPS_REG_F_HI17 = 243; + public static final int MIPS_REG_F_HI18 = 244; + public static final int MIPS_REG_F_HI19 = 245; + public static final int MIPS_REG_F_HI20 = 246; + public static final int MIPS_REG_F_HI21 = 247; + public static final int MIPS_REG_F_HI22 = 248; + public static final int MIPS_REG_F_HI23 = 249; + public static final int MIPS_REG_F_HI24 = 250; + public static final int MIPS_REG_F_HI25 = 251; + public static final int MIPS_REG_F_HI26 = 252; + public static final int MIPS_REG_F_HI27 = 253; + public static final int MIPS_REG_F_HI28 = 254; + public static final int MIPS_REG_F_HI29 = 255; + public static final int MIPS_REG_F_HI30 = 256; + public static final int MIPS_REG_F_HI31 = 257; + public static final int MIPS_REG_GP_64 = 258; + public static final int MIPS_REG_HI0 = 259; + public static final int MIPS_REG_HI1 = 260; + public static final int MIPS_REG_HI2 = 261; + public static final int MIPS_REG_HI3 = 262; + public static final int MIPS_REG_HWR0 = 263; + public static final int MIPS_REG_HWR1 = 264; + public static final int MIPS_REG_HWR2 = 265; + public static final int MIPS_REG_HWR3 = 266; + public static final int MIPS_REG_HWR4 = 267; + public static final int MIPS_REG_HWR5 = 268; + public static final int MIPS_REG_HWR6 = 269; + public static final int MIPS_REG_HWR7 = 270; + public static final int MIPS_REG_HWR8 = 271; + public static final int MIPS_REG_HWR9 = 272; + public static final int MIPS_REG_HWR10 = 273; + public static final int MIPS_REG_HWR11 = 274; + public static final int MIPS_REG_HWR12 = 275; + public static final int MIPS_REG_HWR13 = 276; + public static final int MIPS_REG_HWR14 = 277; + public static final int MIPS_REG_HWR15 = 278; + public static final int MIPS_REG_HWR16 = 279; + public static final int MIPS_REG_HWR17 = 280; + public static final int MIPS_REG_HWR18 = 281; + public static final int MIPS_REG_HWR19 = 282; + public static final int MIPS_REG_HWR20 = 283; + public static final int MIPS_REG_HWR21 = 284; + public static final int MIPS_REG_HWR22 = 285; + public static final int MIPS_REG_HWR23 = 286; + public static final int MIPS_REG_HWR24 = 287; + public static final int MIPS_REG_HWR25 = 288; + public static final int MIPS_REG_HWR26 = 289; + public static final int MIPS_REG_HWR27 = 290; + public static final int MIPS_REG_HWR28 = 291; + public static final int MIPS_REG_HWR29 = 292; + public static final int MIPS_REG_HWR30 = 293; + public static final int MIPS_REG_HWR31 = 294; + public static final int MIPS_REG_K0 = 295; + public static final int MIPS_REG_K1 = 296; + public static final int MIPS_REG_LO0 = 297; + public static final int MIPS_REG_LO1 = 298; + public static final int MIPS_REG_LO2 = 299; + public static final int MIPS_REG_LO3 = 300; + public static final int MIPS_REG_MPL0 = 301; + public static final int MIPS_REG_MPL1 = 302; + public static final int MIPS_REG_MPL2 = 303; + public static final int MIPS_REG_MSA8 = 304; + public static final int MIPS_REG_MSA9 = 305; + public static final int MIPS_REG_MSA10 = 306; + public static final int MIPS_REG_MSA11 = 307; + public static final int MIPS_REG_MSA12 = 308; + public static final int MIPS_REG_MSA13 = 309; + public static final int MIPS_REG_MSA14 = 310; + public static final int MIPS_REG_MSA15 = 311; + public static final int MIPS_REG_MSA16 = 312; + public static final int MIPS_REG_MSA17 = 313; + public static final int MIPS_REG_MSA18 = 314; + public static final int MIPS_REG_MSA19 = 315; + public static final int MIPS_REG_MSA20 = 316; + public static final int MIPS_REG_MSA21 = 317; + public static final int MIPS_REG_MSA22 = 318; + public static final int MIPS_REG_MSA23 = 319; + public static final int MIPS_REG_MSA24 = 320; + public static final int MIPS_REG_MSA25 = 321; + public static final int MIPS_REG_MSA26 = 322; + public static final int MIPS_REG_MSA27 = 323; + public static final int MIPS_REG_MSA28 = 324; + public static final int MIPS_REG_MSA29 = 325; + public static final int MIPS_REG_MSA30 = 326; + public static final int MIPS_REG_MSA31 = 327; + public static final int MIPS_REG_P0 = 328; + public static final int MIPS_REG_P1 = 329; + public static final int MIPS_REG_P2 = 330; + public static final int MIPS_REG_RA_64 = 331; + public static final int MIPS_REG_S0 = 332; + public static final int MIPS_REG_S1 = 333; + public static final int MIPS_REG_S2 = 334; + public static final int MIPS_REG_S3 = 335; + public static final int MIPS_REG_S4 = 336; + public static final int MIPS_REG_S5 = 337; + public static final int MIPS_REG_S6 = 338; + public static final int MIPS_REG_S7 = 339; + public static final int MIPS_REG_SP_64 = 340; + public static final int MIPS_REG_T0 = 341; + public static final int MIPS_REG_T1 = 342; + public static final int MIPS_REG_T2 = 343; + public static final int MIPS_REG_T3 = 344; + public static final int MIPS_REG_T4 = 345; + public static final int MIPS_REG_T5 = 346; + public static final int MIPS_REG_T6 = 347; + public static final int MIPS_REG_T7 = 348; + public static final int MIPS_REG_T8 = 349; + public static final int MIPS_REG_T9 = 350; + public static final int MIPS_REG_V0 = 351; + public static final int MIPS_REG_V1 = 352; + public static final int MIPS_REG_W0 = 353; + public static final int MIPS_REG_W1 = 354; + public static final int MIPS_REG_W2 = 355; + public static final int MIPS_REG_W3 = 356; + public static final int MIPS_REG_W4 = 357; + public static final int MIPS_REG_W5 = 358; + public static final int MIPS_REG_W6 = 359; + public static final int MIPS_REG_W7 = 360; + public static final int MIPS_REG_W8 = 361; + public static final int MIPS_REG_W9 = 362; + public static final int MIPS_REG_W10 = 363; + public static final int MIPS_REG_W11 = 364; + public static final int MIPS_REG_W12 = 365; + public static final int MIPS_REG_W13 = 366; + public static final int MIPS_REG_W14 = 367; + public static final int MIPS_REG_W15 = 368; + public static final int MIPS_REG_W16 = 369; + public static final int MIPS_REG_W17 = 370; + public static final int MIPS_REG_W18 = 371; + public static final int MIPS_REG_W19 = 372; + public static final int MIPS_REG_W20 = 373; + public static final int MIPS_REG_W21 = 374; + public static final int MIPS_REG_W22 = 375; + public static final int MIPS_REG_W23 = 376; + public static final int MIPS_REG_W24 = 377; + public static final int MIPS_REG_W25 = 378; + public static final int MIPS_REG_W26 = 379; + public static final int MIPS_REG_W27 = 380; + public static final int MIPS_REG_W28 = 381; + public static final int MIPS_REG_W29 = 382; + public static final int MIPS_REG_W30 = 383; + public static final int MIPS_REG_W31 = 384; + public static final int MIPS_REG_ZERO_64 = 385; + public static final int MIPS_REG_A0_NM = 386; + public static final int MIPS_REG_A1_NM = 387; + public static final int MIPS_REG_A2_NM = 388; + public static final int MIPS_REG_A3_NM = 389; + public static final int MIPS_REG_A4_NM = 390; + public static final int MIPS_REG_A5_NM = 391; + public static final int MIPS_REG_A6_NM = 392; + public static final int MIPS_REG_A7_NM = 393; + public static final int MIPS_REG_COP0SEL_BADINST = 394; + public static final int MIPS_REG_COP0SEL_BADINSTRP = 395; + public static final int MIPS_REG_COP0SEL_BADINSTRX = 396; + public static final int MIPS_REG_COP0SEL_BADVADDR = 397; + public static final int MIPS_REG_COP0SEL_BEVVA = 398; + public static final int MIPS_REG_COP0SEL_CACHEERR = 399; + public static final int MIPS_REG_COP0SEL_CAUSE = 400; + public static final int MIPS_REG_COP0SEL_CDMMBASE = 401; + public static final int MIPS_REG_COP0SEL_CMGCRBASE = 402; + public static final int MIPS_REG_COP0SEL_COMPARE = 403; + public static final int MIPS_REG_COP0SEL_CONFIG = 404; + public static final int MIPS_REG_COP0SEL_CONTEXT = 405; + public static final int MIPS_REG_COP0SEL_CONTEXTCONFIG = 406; + public static final int MIPS_REG_COP0SEL_COUNT = 407; + public static final int MIPS_REG_COP0SEL_DDATAHI = 408; + public static final int MIPS_REG_COP0SEL_DDATALO = 409; + public static final int MIPS_REG_COP0SEL_DEBUG = 410; + public static final int MIPS_REG_COP0SEL_DEBUGCONTEXTID = 411; + public static final int MIPS_REG_COP0SEL_DEPC = 412; + public static final int MIPS_REG_COP0SEL_DESAVE = 413; + public static final int MIPS_REG_COP0SEL_DTAGHI = 414; + public static final int MIPS_REG_COP0SEL_DTAGLO = 415; + public static final int MIPS_REG_COP0SEL_EBASE = 416; + public static final int MIPS_REG_COP0SEL_ENTRYHI = 417; + public static final int MIPS_REG_COP0SEL_EPC = 418; + public static final int MIPS_REG_COP0SEL_ERRCTL = 419; + public static final int MIPS_REG_COP0SEL_ERROREPC = 420; + public static final int MIPS_REG_COP0SEL_GLOBALNUMBER = 421; + public static final int MIPS_REG_COP0SEL_GTOFFSET = 422; + public static final int MIPS_REG_COP0SEL_HWRENA = 423; + public static final int MIPS_REG_COP0SEL_IDATAHI = 424; + public static final int MIPS_REG_COP0SEL_IDATALO = 425; + public static final int MIPS_REG_COP0SEL_INDEX = 426; + public static final int MIPS_REG_COP0SEL_INTCTL = 427; + public static final int MIPS_REG_COP0SEL_ITAGHI = 428; + public static final int MIPS_REG_COP0SEL_ITAGLO = 429; + public static final int MIPS_REG_COP0SEL_LLADDR = 430; + public static final int MIPS_REG_COP0SEL_MAAR = 431; + public static final int MIPS_REG_COP0SEL_MAARI = 432; + public static final int MIPS_REG_COP0SEL_MEMORYMAPID = 433; + public static final int MIPS_REG_COP0SEL_MVPCONTROL = 434; + public static final int MIPS_REG_COP0SEL_NESTEDEPC = 435; + public static final int MIPS_REG_COP0SEL_NESTEDEXC = 436; + public static final int MIPS_REG_COP0SEL_PAGEGRAIN = 437; + public static final int MIPS_REG_COP0SEL_PAGEMASK = 438; + public static final int MIPS_REG_COP0SEL_PRID = 439; + public static final int MIPS_REG_COP0SEL_PWBASE = 440; + public static final int MIPS_REG_COP0SEL_PWCTL = 441; + public static final int MIPS_REG_COP0SEL_PWFIELD = 442; + public static final int MIPS_REG_COP0SEL_PWSIZE = 443; + public static final int MIPS_REG_COP0SEL_RANDOM = 444; + public static final int MIPS_REG_COP0SEL_SRSCTL = 445; + public static final int MIPS_REG_COP0SEL_SRSMAP = 446; + public static final int MIPS_REG_COP0SEL_STATUS = 447; + public static final int MIPS_REG_COP0SEL_TCBIND = 448; + public static final int MIPS_REG_COP0SEL_TCCONTEXT = 449; + public static final int MIPS_REG_COP0SEL_TCHALT = 450; + public static final int MIPS_REG_COP0SEL_TCOPT = 451; + public static final int MIPS_REG_COP0SEL_TCRESTART = 452; + public static final int MIPS_REG_COP0SEL_TCSCHEDULE = 453; + public static final int MIPS_REG_COP0SEL_TCSCHEFBACK = 454; + public static final int MIPS_REG_COP0SEL_TCSTATUS = 455; + public static final int MIPS_REG_COP0SEL_TRACECONTROL = 456; + public static final int MIPS_REG_COP0SEL_TRACEDBPC = 457; + public static final int MIPS_REG_COP0SEL_TRACEIBPC = 458; + public static final int MIPS_REG_COP0SEL_USERLOCAL = 459; + public static final int MIPS_REG_COP0SEL_VIEW_IPL = 460; + public static final int MIPS_REG_COP0SEL_VIEW_RIPL = 461; + public static final int MIPS_REG_COP0SEL_VPCONTROL = 462; + public static final int MIPS_REG_COP0SEL_VPECONTROL = 463; + public static final int MIPS_REG_COP0SEL_VPEOPT = 464; + public static final int MIPS_REG_COP0SEL_VPESCHEDULE = 465; + public static final int MIPS_REG_COP0SEL_VPESCHEFBACK = 466; + public static final int MIPS_REG_COP0SEL_WIRED = 467; + public static final int MIPS_REG_COP0SEL_XCONTEXT = 468; + public static final int MIPS_REG_COP0SEL_XCONTEXTCONFIG = 469; + public static final int MIPS_REG_COP0SEL_YQMASK = 470; + public static final int MIPS_REG_K0_NM = 471; + public static final int MIPS_REG_K1_NM = 472; + public static final int MIPS_REG_S0_NM = 473; + public static final int MIPS_REG_S1_NM = 474; + public static final int MIPS_REG_S2_NM = 475; + public static final int MIPS_REG_S3_NM = 476; + public static final int MIPS_REG_S4_NM = 477; + public static final int MIPS_REG_S5_NM = 478; + public static final int MIPS_REG_S6_NM = 479; + public static final int MIPS_REG_S7_NM = 480; + public static final int MIPS_REG_T0_NM = 481; + public static final int MIPS_REG_T1_NM = 482; + public static final int MIPS_REG_T2_NM = 483; + public static final int MIPS_REG_T3_NM = 484; + public static final int MIPS_REG_T4_NM = 485; + public static final int MIPS_REG_T5_NM = 486; + public static final int MIPS_REG_T8_NM = 487; + public static final int MIPS_REG_T9_NM = 488; + public static final int MIPS_REG_A0_64 = 489; + public static final int MIPS_REG_A1_64 = 490; + public static final int MIPS_REG_A2_64 = 491; + public static final int MIPS_REG_A3_64 = 492; + public static final int MIPS_REG_AC0_64 = 493; + public static final int MIPS_REG_COP0SEL_CONFIG1 = 494; + public static final int MIPS_REG_COP0SEL_CONFIG2 = 495; + public static final int MIPS_REG_COP0SEL_CONFIG3 = 496; + public static final int MIPS_REG_COP0SEL_CONFIG4 = 497; + public static final int MIPS_REG_COP0SEL_CONFIG5 = 498; + public static final int MIPS_REG_COP0SEL_DEBUG2 = 499; + public static final int MIPS_REG_COP0SEL_ENTRYLO0 = 500; + public static final int MIPS_REG_COP0SEL_ENTRYLO1 = 501; + public static final int MIPS_REG_COP0SEL_GUESTCTL0 = 502; + public static final int MIPS_REG_COP0SEL_GUESTCTL1 = 503; + public static final int MIPS_REG_COP0SEL_GUESTCTL2 = 504; + public static final int MIPS_REG_COP0SEL_GUESTCTL3 = 505; + public static final int MIPS_REG_COP0SEL_KSCRATCH1 = 506; + public static final int MIPS_REG_COP0SEL_KSCRATCH2 = 507; + public static final int MIPS_REG_COP0SEL_KSCRATCH3 = 508; + public static final int MIPS_REG_COP0SEL_KSCRATCH4 = 509; + public static final int MIPS_REG_COP0SEL_KSCRATCH5 = 510; + public static final int MIPS_REG_COP0SEL_KSCRATCH6 = 511; + public static final int MIPS_REG_COP0SEL_MVPCONF0 = 512; + public static final int MIPS_REG_COP0SEL_MVPCONF1 = 513; + public static final int MIPS_REG_COP0SEL_PERFCNT0 = 514; + public static final int MIPS_REG_COP0SEL_PERFCNT1 = 515; + public static final int MIPS_REG_COP0SEL_PERFCNT2 = 516; + public static final int MIPS_REG_COP0SEL_PERFCNT3 = 517; + public static final int MIPS_REG_COP0SEL_PERFCNT4 = 518; + public static final int MIPS_REG_COP0SEL_PERFCNT5 = 519; + public static final int MIPS_REG_COP0SEL_PERFCNT6 = 520; + public static final int MIPS_REG_COP0SEL_PERFCNT7 = 521; + public static final int MIPS_REG_COP0SEL_PERFCTL0 = 522; + public static final int MIPS_REG_COP0SEL_PERFCTL1 = 523; + public static final int MIPS_REG_COP0SEL_PERFCTL2 = 524; + public static final int MIPS_REG_COP0SEL_PERFCTL3 = 525; + public static final int MIPS_REG_COP0SEL_PERFCTL4 = 526; + public static final int MIPS_REG_COP0SEL_PERFCTL5 = 527; + public static final int MIPS_REG_COP0SEL_PERFCTL6 = 528; + public static final int MIPS_REG_COP0SEL_PERFCTL7 = 529; + public static final int MIPS_REG_COP0SEL_SEGCTL0 = 530; + public static final int MIPS_REG_COP0SEL_SEGCTL1 = 531; + public static final int MIPS_REG_COP0SEL_SEGCTL2 = 532; + public static final int MIPS_REG_COP0SEL_SRSCONF0 = 533; + public static final int MIPS_REG_COP0SEL_SRSCONF1 = 534; + public static final int MIPS_REG_COP0SEL_SRSCONF2 = 535; + public static final int MIPS_REG_COP0SEL_SRSCONF3 = 536; + public static final int MIPS_REG_COP0SEL_SRSCONF4 = 537; + public static final int MIPS_REG_COP0SEL_SRSMAP2 = 538; + public static final int MIPS_REG_COP0SEL_TRACECONTROL2 = 539; + public static final int MIPS_REG_COP0SEL_TRACECONTROL3 = 540; + public static final int MIPS_REG_COP0SEL_USERTRACEDATA1 = 541; + public static final int MIPS_REG_COP0SEL_USERTRACEDATA2 = 542; + public static final int MIPS_REG_COP0SEL_VPECONF0 = 543; + public static final int MIPS_REG_COP0SEL_VPECONF1 = 544; + public static final int MIPS_REG_COP0SEL_WATCHHI0 = 545; + public static final int MIPS_REG_COP0SEL_WATCHHI1 = 546; + public static final int MIPS_REG_COP0SEL_WATCHHI2 = 547; + public static final int MIPS_REG_COP0SEL_WATCHHI3 = 548; + public static final int MIPS_REG_COP0SEL_WATCHHI4 = 549; + public static final int MIPS_REG_COP0SEL_WATCHHI5 = 550; + public static final int MIPS_REG_COP0SEL_WATCHHI6 = 551; + public static final int MIPS_REG_COP0SEL_WATCHHI7 = 552; + public static final int MIPS_REG_COP0SEL_WATCHHI8 = 553; + public static final int MIPS_REG_COP0SEL_WATCHHI9 = 554; + public static final int MIPS_REG_COP0SEL_WATCHHI10 = 555; + public static final int MIPS_REG_COP0SEL_WATCHHI11 = 556; + public static final int MIPS_REG_COP0SEL_WATCHHI12 = 557; + public static final int MIPS_REG_COP0SEL_WATCHHI13 = 558; + public static final int MIPS_REG_COP0SEL_WATCHHI14 = 559; + public static final int MIPS_REG_COP0SEL_WATCHHI15 = 560; + public static final int MIPS_REG_COP0SEL_WATCHLO0 = 561; + public static final int MIPS_REG_COP0SEL_WATCHLO1 = 562; + public static final int MIPS_REG_COP0SEL_WATCHLO2 = 563; + public static final int MIPS_REG_COP0SEL_WATCHLO3 = 564; + public static final int MIPS_REG_COP0SEL_WATCHLO4 = 565; + public static final int MIPS_REG_COP0SEL_WATCHLO5 = 566; + public static final int MIPS_REG_COP0SEL_WATCHLO6 = 567; + public static final int MIPS_REG_COP0SEL_WATCHLO7 = 568; + public static final int MIPS_REG_COP0SEL_WATCHLO8 = 569; + public static final int MIPS_REG_COP0SEL_WATCHLO9 = 570; + public static final int MIPS_REG_COP0SEL_WATCHLO10 = 571; + public static final int MIPS_REG_COP0SEL_WATCHLO11 = 572; + public static final int MIPS_REG_COP0SEL_WATCHLO12 = 573; + public static final int MIPS_REG_COP0SEL_WATCHLO13 = 574; + public static final int MIPS_REG_COP0SEL_WATCHLO14 = 575; + public static final int MIPS_REG_COP0SEL_WATCHLO15 = 576; + public static final int MIPS_REG_D0_64 = 577; + public static final int MIPS_REG_D1_64 = 578; + public static final int MIPS_REG_D2_64 = 579; + public static final int MIPS_REG_D3_64 = 580; + public static final int MIPS_REG_D4_64 = 581; + public static final int MIPS_REG_D5_64 = 582; + public static final int MIPS_REG_D6_64 = 583; + public static final int MIPS_REG_D7_64 = 584; + public static final int MIPS_REG_D8_64 = 585; + public static final int MIPS_REG_D9_64 = 586; + public static final int MIPS_REG_D10_64 = 587; + public static final int MIPS_REG_D11_64 = 588; + public static final int MIPS_REG_D12_64 = 589; + public static final int MIPS_REG_D13_64 = 590; + public static final int MIPS_REG_D14_64 = 591; + public static final int MIPS_REG_D15_64 = 592; + public static final int MIPS_REG_D16_64 = 593; + public static final int MIPS_REG_D17_64 = 594; + public static final int MIPS_REG_D18_64 = 595; + public static final int MIPS_REG_D19_64 = 596; + public static final int MIPS_REG_D20_64 = 597; + public static final int MIPS_REG_D21_64 = 598; + public static final int MIPS_REG_D22_64 = 599; + public static final int MIPS_REG_D23_64 = 600; + public static final int MIPS_REG_D24_64 = 601; + public static final int MIPS_REG_D25_64 = 602; + public static final int MIPS_REG_D26_64 = 603; + public static final int MIPS_REG_D27_64 = 604; + public static final int MIPS_REG_D28_64 = 605; + public static final int MIPS_REG_D29_64 = 606; + public static final int MIPS_REG_D30_64 = 607; + public static final int MIPS_REG_D31_64 = 608; + public static final int MIPS_REG_DSPOUTFLAG16_19 = 609; + public static final int MIPS_REG_HI0_64 = 610; + public static final int MIPS_REG_K0_64 = 611; + public static final int MIPS_REG_K1_64 = 612; + public static final int MIPS_REG_LO0_64 = 613; + public static final int MIPS_REG_S0_64 = 614; + public static final int MIPS_REG_S1_64 = 615; + public static final int MIPS_REG_S2_64 = 616; + public static final int MIPS_REG_S3_64 = 617; + public static final int MIPS_REG_S4_64 = 618; + public static final int MIPS_REG_S5_64 = 619; + public static final int MIPS_REG_S6_64 = 620; + public static final int MIPS_REG_S7_64 = 621; + public static final int MIPS_REG_T0_64 = 622; + public static final int MIPS_REG_T1_64 = 623; + public static final int MIPS_REG_T2_64 = 624; + public static final int MIPS_REG_T3_64 = 625; + public static final int MIPS_REG_T4_64 = 626; + public static final int MIPS_REG_T5_64 = 627; + public static final int MIPS_REG_T6_64 = 628; + public static final int MIPS_REG_T7_64 = 629; + public static final int MIPS_REG_T8_64 = 630; + public static final int MIPS_REG_T9_64 = 631; + public static final int MIPS_REG_V0_64 = 632; + public static final int MIPS_REG_V1_64 = 633; + public static final int MIPS_REG_COP0SEL_GUESTCTL0EXT = 634; + public static final int MIPS_REG_ENDING = 635; public static final int MIPS_INS_INVALID = 0; - public static final int MIPS_INS_ABSQ_S = 1; - public static final int MIPS_INS_ADD = 2; - public static final int MIPS_INS_ADDIUPC = 3; - public static final int MIPS_INS_ADDIUR1SP = 4; - public static final int MIPS_INS_ADDIUR2 = 5; - public static final int MIPS_INS_ADDIUS5 = 6; - public static final int MIPS_INS_ADDIUSP = 7; - public static final int MIPS_INS_ADDQH = 8; - public static final int MIPS_INS_ADDQH_R = 9; - public static final int MIPS_INS_ADDQ = 10; - public static final int MIPS_INS_ADDQ_S = 11; - public static final int MIPS_INS_ADDSC = 12; - public static final int MIPS_INS_ADDS_A = 13; - public static final int MIPS_INS_ADDS_S = 14; - public static final int MIPS_INS_ADDS_U = 15; - public static final int MIPS_INS_ADDU16 = 16; - public static final int MIPS_INS_ADDUH = 17; - public static final int MIPS_INS_ADDUH_R = 18; - public static final int MIPS_INS_ADDU = 19; - public static final int MIPS_INS_ADDU_S = 20; - public static final int MIPS_INS_ADDVI = 21; - public static final int MIPS_INS_ADDV = 22; - public static final int MIPS_INS_ADDWC = 23; - public static final int MIPS_INS_ADD_A = 24; - public static final int MIPS_INS_ADDI = 25; - public static final int MIPS_INS_ADDIU = 26; - public static final int MIPS_INS_ALIGN = 27; - public static final int MIPS_INS_ALUIPC = 28; - public static final int MIPS_INS_AND = 29; - public static final int MIPS_INS_AND16 = 30; - public static final int MIPS_INS_ANDI16 = 31; - public static final int MIPS_INS_ANDI = 32; - public static final int MIPS_INS_APPEND = 33; - public static final int MIPS_INS_ASUB_S = 34; - public static final int MIPS_INS_ASUB_U = 35; - public static final int MIPS_INS_AUI = 36; - public static final int MIPS_INS_AUIPC = 37; - public static final int MIPS_INS_AVER_S = 38; - public static final int MIPS_INS_AVER_U = 39; - public static final int MIPS_INS_AVE_S = 40; - public static final int MIPS_INS_AVE_U = 41; - public static final int MIPS_INS_B16 = 42; - public static final int MIPS_INS_BADDU = 43; - public static final int MIPS_INS_BAL = 44; - public static final int MIPS_INS_BALC = 45; - public static final int MIPS_INS_BALIGN = 46; - public static final int MIPS_INS_BBIT0 = 47; - public static final int MIPS_INS_BBIT032 = 48; - public static final int MIPS_INS_BBIT1 = 49; - public static final int MIPS_INS_BBIT132 = 50; - public static final int MIPS_INS_BC = 51; - public static final int MIPS_INS_BC0F = 52; - public static final int MIPS_INS_BC0FL = 53; - public static final int MIPS_INS_BC0T = 54; - public static final int MIPS_INS_BC0TL = 55; - public static final int MIPS_INS_BC1EQZ = 56; - public static final int MIPS_INS_BC1F = 57; - public static final int MIPS_INS_BC1FL = 58; - public static final int MIPS_INS_BC1NEZ = 59; - public static final int MIPS_INS_BC1T = 60; - public static final int MIPS_INS_BC1TL = 61; - public static final int MIPS_INS_BC2EQZ = 62; - public static final int MIPS_INS_BC2F = 63; - public static final int MIPS_INS_BC2FL = 64; - public static final int MIPS_INS_BC2NEZ = 65; - public static final int MIPS_INS_BC2T = 66; - public static final int MIPS_INS_BC2TL = 67; - public static final int MIPS_INS_BC3F = 68; - public static final int MIPS_INS_BC3FL = 69; - public static final int MIPS_INS_BC3T = 70; - public static final int MIPS_INS_BC3TL = 71; - public static final int MIPS_INS_BCLRI = 72; - public static final int MIPS_INS_BCLR = 73; - public static final int MIPS_INS_BEQ = 74; - public static final int MIPS_INS_BEQC = 75; - public static final int MIPS_INS_BEQL = 76; - public static final int MIPS_INS_BEQZ16 = 77; - public static final int MIPS_INS_BEQZALC = 78; - public static final int MIPS_INS_BEQZC = 79; - public static final int MIPS_INS_BGEC = 80; - public static final int MIPS_INS_BGEUC = 81; - public static final int MIPS_INS_BGEZ = 82; - public static final int MIPS_INS_BGEZAL = 83; - public static final int MIPS_INS_BGEZALC = 84; - public static final int MIPS_INS_BGEZALL = 85; - public static final int MIPS_INS_BGEZALS = 86; - public static final int MIPS_INS_BGEZC = 87; - public static final int MIPS_INS_BGEZL = 88; - public static final int MIPS_INS_BGTZ = 89; - public static final int MIPS_INS_BGTZALC = 90; - public static final int MIPS_INS_BGTZC = 91; - public static final int MIPS_INS_BGTZL = 92; - public static final int MIPS_INS_BINSLI = 93; - public static final int MIPS_INS_BINSL = 94; - public static final int MIPS_INS_BINSRI = 95; - public static final int MIPS_INS_BINSR = 96; - public static final int MIPS_INS_BITREV = 97; - public static final int MIPS_INS_BITSWAP = 98; - public static final int MIPS_INS_BLEZ = 99; - public static final int MIPS_INS_BLEZALC = 100; - public static final int MIPS_INS_BLEZC = 101; - public static final int MIPS_INS_BLEZL = 102; - public static final int MIPS_INS_BLTC = 103; - public static final int MIPS_INS_BLTUC = 104; - public static final int MIPS_INS_BLTZ = 105; - public static final int MIPS_INS_BLTZAL = 106; - public static final int MIPS_INS_BLTZALC = 107; - public static final int MIPS_INS_BLTZALL = 108; - public static final int MIPS_INS_BLTZALS = 109; - public static final int MIPS_INS_BLTZC = 110; - public static final int MIPS_INS_BLTZL = 111; - public static final int MIPS_INS_BMNZI = 112; - public static final int MIPS_INS_BMNZ = 113; - public static final int MIPS_INS_BMZI = 114; - public static final int MIPS_INS_BMZ = 115; - public static final int MIPS_INS_BNE = 116; - public static final int MIPS_INS_BNEC = 117; - public static final int MIPS_INS_BNEGI = 118; - public static final int MIPS_INS_BNEG = 119; - public static final int MIPS_INS_BNEL = 120; - public static final int MIPS_INS_BNEZ16 = 121; - public static final int MIPS_INS_BNEZALC = 122; - public static final int MIPS_INS_BNEZC = 123; - public static final int MIPS_INS_BNVC = 124; - public static final int MIPS_INS_BNZ = 125; - public static final int MIPS_INS_BOVC = 126; - public static final int MIPS_INS_BPOSGE32 = 127; - public static final int MIPS_INS_BREAK = 128; - public static final int MIPS_INS_BREAK16 = 129; - public static final int MIPS_INS_BSELI = 130; - public static final int MIPS_INS_BSEL = 131; - public static final int MIPS_INS_BSETI = 132; - public static final int MIPS_INS_BSET = 133; - public static final int MIPS_INS_BZ = 134; - public static final int MIPS_INS_BEQZ = 135; - public static final int MIPS_INS_B = 136; - public static final int MIPS_INS_BNEZ = 137; - public static final int MIPS_INS_BTEQZ = 138; - public static final int MIPS_INS_BTNEZ = 139; - public static final int MIPS_INS_CACHE = 140; - public static final int MIPS_INS_CEIL = 141; - public static final int MIPS_INS_CEQI = 142; - public static final int MIPS_INS_CEQ = 143; - public static final int MIPS_INS_CFC1 = 144; - public static final int MIPS_INS_CFCMSA = 145; - public static final int MIPS_INS_CINS = 146; - public static final int MIPS_INS_CINS32 = 147; - public static final int MIPS_INS_CLASS = 148; - public static final int MIPS_INS_CLEI_S = 149; - public static final int MIPS_INS_CLEI_U = 150; - public static final int MIPS_INS_CLE_S = 151; - public static final int MIPS_INS_CLE_U = 152; - public static final int MIPS_INS_CLO = 153; - public static final int MIPS_INS_CLTI_S = 154; - public static final int MIPS_INS_CLTI_U = 155; - public static final int MIPS_INS_CLT_S = 156; - public static final int MIPS_INS_CLT_U = 157; - public static final int MIPS_INS_CLZ = 158; - public static final int MIPS_INS_CMPGDU = 159; - public static final int MIPS_INS_CMPGU = 160; - public static final int MIPS_INS_CMPU = 161; - public static final int MIPS_INS_CMP = 162; - public static final int MIPS_INS_COPY_S = 163; - public static final int MIPS_INS_COPY_U = 164; - public static final int MIPS_INS_CTC1 = 165; - public static final int MIPS_INS_CTCMSA = 166; - public static final int MIPS_INS_CVT = 167; - public static final int MIPS_INS_C = 168; - public static final int MIPS_INS_CMPI = 169; - public static final int MIPS_INS_DADD = 170; - public static final int MIPS_INS_DADDI = 171; - public static final int MIPS_INS_DADDIU = 172; - public static final int MIPS_INS_DADDU = 173; - public static final int MIPS_INS_DAHI = 174; - public static final int MIPS_INS_DALIGN = 175; - public static final int MIPS_INS_DATI = 176; - public static final int MIPS_INS_DAUI = 177; - public static final int MIPS_INS_DBITSWAP = 178; - public static final int MIPS_INS_DCLO = 179; - public static final int MIPS_INS_DCLZ = 180; - public static final int MIPS_INS_DDIV = 181; - public static final int MIPS_INS_DDIVU = 182; - public static final int MIPS_INS_DERET = 183; - public static final int MIPS_INS_DEXT = 184; - public static final int MIPS_INS_DEXTM = 185; - public static final int MIPS_INS_DEXTU = 186; - public static final int MIPS_INS_DI = 187; - public static final int MIPS_INS_DINS = 188; - public static final int MIPS_INS_DINSM = 189; - public static final int MIPS_INS_DINSU = 190; - public static final int MIPS_INS_DIV = 191; - public static final int MIPS_INS_DIVU = 192; - public static final int MIPS_INS_DIV_S = 193; - public static final int MIPS_INS_DIV_U = 194; - public static final int MIPS_INS_DLSA = 195; - public static final int MIPS_INS_DMFC0 = 196; - public static final int MIPS_INS_DMFC1 = 197; - public static final int MIPS_INS_DMFC2 = 198; - public static final int MIPS_INS_DMOD = 199; - public static final int MIPS_INS_DMODU = 200; - public static final int MIPS_INS_DMTC0 = 201; - public static final int MIPS_INS_DMTC1 = 202; - public static final int MIPS_INS_DMTC2 = 203; - public static final int MIPS_INS_DMUH = 204; - public static final int MIPS_INS_DMUHU = 205; - public static final int MIPS_INS_DMUL = 206; - public static final int MIPS_INS_DMULT = 207; - public static final int MIPS_INS_DMULTU = 208; - public static final int MIPS_INS_DMULU = 209; - public static final int MIPS_INS_DOTP_S = 210; - public static final int MIPS_INS_DOTP_U = 211; - public static final int MIPS_INS_DPADD_S = 212; - public static final int MIPS_INS_DPADD_U = 213; - public static final int MIPS_INS_DPAQX_SA = 214; - public static final int MIPS_INS_DPAQX_S = 215; - public static final int MIPS_INS_DPAQ_SA = 216; - public static final int MIPS_INS_DPAQ_S = 217; - public static final int MIPS_INS_DPAU = 218; - public static final int MIPS_INS_DPAX = 219; - public static final int MIPS_INS_DPA = 220; - public static final int MIPS_INS_DPOP = 221; - public static final int MIPS_INS_DPSQX_SA = 222; - public static final int MIPS_INS_DPSQX_S = 223; - public static final int MIPS_INS_DPSQ_SA = 224; - public static final int MIPS_INS_DPSQ_S = 225; - public static final int MIPS_INS_DPSUB_S = 226; - public static final int MIPS_INS_DPSUB_U = 227; - public static final int MIPS_INS_DPSU = 228; - public static final int MIPS_INS_DPSX = 229; - public static final int MIPS_INS_DPS = 230; - public static final int MIPS_INS_DROTR = 231; - public static final int MIPS_INS_DROTR32 = 232; - public static final int MIPS_INS_DROTRV = 233; - public static final int MIPS_INS_DSBH = 234; - public static final int MIPS_INS_DSHD = 235; - public static final int MIPS_INS_DSLL = 236; - public static final int MIPS_INS_DSLL32 = 237; - public static final int MIPS_INS_DSLLV = 238; - public static final int MIPS_INS_DSRA = 239; - public static final int MIPS_INS_DSRA32 = 240; - public static final int MIPS_INS_DSRAV = 241; - public static final int MIPS_INS_DSRL = 242; - public static final int MIPS_INS_DSRL32 = 243; - public static final int MIPS_INS_DSRLV = 244; - public static final int MIPS_INS_DSUB = 245; - public static final int MIPS_INS_DSUBU = 246; - public static final int MIPS_INS_EHB = 247; - public static final int MIPS_INS_EI = 248; - public static final int MIPS_INS_ERET = 249; - public static final int MIPS_INS_EXT = 250; - public static final int MIPS_INS_EXTP = 251; - public static final int MIPS_INS_EXTPDP = 252; - public static final int MIPS_INS_EXTPDPV = 253; - public static final int MIPS_INS_EXTPV = 254; - public static final int MIPS_INS_EXTRV_RS = 255; - public static final int MIPS_INS_EXTRV_R = 256; - public static final int MIPS_INS_EXTRV_S = 257; - public static final int MIPS_INS_EXTRV = 258; - public static final int MIPS_INS_EXTR_RS = 259; - public static final int MIPS_INS_EXTR_R = 260; - public static final int MIPS_INS_EXTR_S = 261; - public static final int MIPS_INS_EXTR = 262; - public static final int MIPS_INS_EXTS = 263; - public static final int MIPS_INS_EXTS32 = 264; - public static final int MIPS_INS_ABS = 265; - public static final int MIPS_INS_FADD = 266; - public static final int MIPS_INS_FCAF = 267; - public static final int MIPS_INS_FCEQ = 268; - public static final int MIPS_INS_FCLASS = 269; - public static final int MIPS_INS_FCLE = 270; - public static final int MIPS_INS_FCLT = 271; - public static final int MIPS_INS_FCNE = 272; - public static final int MIPS_INS_FCOR = 273; - public static final int MIPS_INS_FCUEQ = 274; - public static final int MIPS_INS_FCULE = 275; - public static final int MIPS_INS_FCULT = 276; - public static final int MIPS_INS_FCUNE = 277; - public static final int MIPS_INS_FCUN = 278; - public static final int MIPS_INS_FDIV = 279; - public static final int MIPS_INS_FEXDO = 280; - public static final int MIPS_INS_FEXP2 = 281; - public static final int MIPS_INS_FEXUPL = 282; - public static final int MIPS_INS_FEXUPR = 283; - public static final int MIPS_INS_FFINT_S = 284; - public static final int MIPS_INS_FFINT_U = 285; - public static final int MIPS_INS_FFQL = 286; - public static final int MIPS_INS_FFQR = 287; - public static final int MIPS_INS_FILL = 288; - public static final int MIPS_INS_FLOG2 = 289; - public static final int MIPS_INS_FLOOR = 290; - public static final int MIPS_INS_FMADD = 291; - public static final int MIPS_INS_FMAX_A = 292; - public static final int MIPS_INS_FMAX = 293; - public static final int MIPS_INS_FMIN_A = 294; - public static final int MIPS_INS_FMIN = 295; - public static final int MIPS_INS_MOV = 296; - public static final int MIPS_INS_FMSUB = 297; - public static final int MIPS_INS_FMUL = 298; - public static final int MIPS_INS_MUL = 299; - public static final int MIPS_INS_NEG = 300; - public static final int MIPS_INS_FRCP = 301; - public static final int MIPS_INS_FRINT = 302; - public static final int MIPS_INS_FRSQRT = 303; - public static final int MIPS_INS_FSAF = 304; - public static final int MIPS_INS_FSEQ = 305; - public static final int MIPS_INS_FSLE = 306; - public static final int MIPS_INS_FSLT = 307; - public static final int MIPS_INS_FSNE = 308; - public static final int MIPS_INS_FSOR = 309; - public static final int MIPS_INS_FSQRT = 310; - public static final int MIPS_INS_SQRT = 311; - public static final int MIPS_INS_FSUB = 312; - public static final int MIPS_INS_SUB = 313; - public static final int MIPS_INS_FSUEQ = 314; - public static final int MIPS_INS_FSULE = 315; - public static final int MIPS_INS_FSULT = 316; - public static final int MIPS_INS_FSUNE = 317; - public static final int MIPS_INS_FSUN = 318; - public static final int MIPS_INS_FTINT_S = 319; - public static final int MIPS_INS_FTINT_U = 320; - public static final int MIPS_INS_FTQ = 321; - public static final int MIPS_INS_FTRUNC_S = 322; - public static final int MIPS_INS_FTRUNC_U = 323; - public static final int MIPS_INS_HADD_S = 324; - public static final int MIPS_INS_HADD_U = 325; - public static final int MIPS_INS_HSUB_S = 326; - public static final int MIPS_INS_HSUB_U = 327; - public static final int MIPS_INS_ILVEV = 328; - public static final int MIPS_INS_ILVL = 329; - public static final int MIPS_INS_ILVOD = 330; - public static final int MIPS_INS_ILVR = 331; - public static final int MIPS_INS_INS = 332; - public static final int MIPS_INS_INSERT = 333; - public static final int MIPS_INS_INSV = 334; - public static final int MIPS_INS_INSVE = 335; - public static final int MIPS_INS_J = 336; - public static final int MIPS_INS_JAL = 337; - public static final int MIPS_INS_JALR = 338; - public static final int MIPS_INS_JALRS16 = 339; - public static final int MIPS_INS_JALRS = 340; - public static final int MIPS_INS_JALS = 341; - public static final int MIPS_INS_JALX = 342; - public static final int MIPS_INS_JIALC = 343; - public static final int MIPS_INS_JIC = 344; - public static final int MIPS_INS_JR = 345; - public static final int MIPS_INS_JR16 = 346; - public static final int MIPS_INS_JRADDIUSP = 347; - public static final int MIPS_INS_JRC = 348; - public static final int MIPS_INS_JALRC = 349; - public static final int MIPS_INS_LB = 350; - public static final int MIPS_INS_LBU16 = 351; - public static final int MIPS_INS_LBUX = 352; - public static final int MIPS_INS_LBU = 353; - public static final int MIPS_INS_LD = 354; - public static final int MIPS_INS_LDC1 = 355; - public static final int MIPS_INS_LDC2 = 356; - public static final int MIPS_INS_LDC3 = 357; - public static final int MIPS_INS_LDI = 358; - public static final int MIPS_INS_LDL = 359; - public static final int MIPS_INS_LDPC = 360; - public static final int MIPS_INS_LDR = 361; - public static final int MIPS_INS_LDXC1 = 362; - public static final int MIPS_INS_LH = 363; - public static final int MIPS_INS_LHU16 = 364; - public static final int MIPS_INS_LHX = 365; - public static final int MIPS_INS_LHU = 366; - public static final int MIPS_INS_LI16 = 367; - public static final int MIPS_INS_LL = 368; - public static final int MIPS_INS_LLD = 369; - public static final int MIPS_INS_LSA = 370; - public static final int MIPS_INS_LUXC1 = 371; - public static final int MIPS_INS_LUI = 372; - public static final int MIPS_INS_LW = 373; - public static final int MIPS_INS_LW16 = 374; - public static final int MIPS_INS_LWC1 = 375; - public static final int MIPS_INS_LWC2 = 376; - public static final int MIPS_INS_LWC3 = 377; - public static final int MIPS_INS_LWL = 378; - public static final int MIPS_INS_LWM16 = 379; - public static final int MIPS_INS_LWM32 = 380; - public static final int MIPS_INS_LWPC = 381; - public static final int MIPS_INS_LWP = 382; - public static final int MIPS_INS_LWR = 383; - public static final int MIPS_INS_LWUPC = 384; - public static final int MIPS_INS_LWU = 385; - public static final int MIPS_INS_LWX = 386; - public static final int MIPS_INS_LWXC1 = 387; - public static final int MIPS_INS_LWXS = 388; - public static final int MIPS_INS_LI = 389; - public static final int MIPS_INS_MADD = 390; - public static final int MIPS_INS_MADDF = 391; - public static final int MIPS_INS_MADDR_Q = 392; - public static final int MIPS_INS_MADDU = 393; - public static final int MIPS_INS_MADDV = 394; - public static final int MIPS_INS_MADD_Q = 395; - public static final int MIPS_INS_MAQ_SA = 396; - public static final int MIPS_INS_MAQ_S = 397; - public static final int MIPS_INS_MAXA = 398; - public static final int MIPS_INS_MAXI_S = 399; - public static final int MIPS_INS_MAXI_U = 400; - public static final int MIPS_INS_MAX_A = 401; - public static final int MIPS_INS_MAX = 402; - public static final int MIPS_INS_MAX_S = 403; - public static final int MIPS_INS_MAX_U = 404; - public static final int MIPS_INS_MFC0 = 405; - public static final int MIPS_INS_MFC1 = 406; - public static final int MIPS_INS_MFC2 = 407; - public static final int MIPS_INS_MFHC1 = 408; - public static final int MIPS_INS_MFHI = 409; - public static final int MIPS_INS_MFLO = 410; - public static final int MIPS_INS_MINA = 411; - public static final int MIPS_INS_MINI_S = 412; - public static final int MIPS_INS_MINI_U = 413; - public static final int MIPS_INS_MIN_A = 414; - public static final int MIPS_INS_MIN = 415; - public static final int MIPS_INS_MIN_S = 416; - public static final int MIPS_INS_MIN_U = 417; - public static final int MIPS_INS_MOD = 418; - public static final int MIPS_INS_MODSUB = 419; - public static final int MIPS_INS_MODU = 420; - public static final int MIPS_INS_MOD_S = 421; - public static final int MIPS_INS_MOD_U = 422; - public static final int MIPS_INS_MOVE = 423; - public static final int MIPS_INS_MOVEP = 424; - public static final int MIPS_INS_MOVF = 425; - public static final int MIPS_INS_MOVN = 426; - public static final int MIPS_INS_MOVT = 427; - public static final int MIPS_INS_MOVZ = 428; - public static final int MIPS_INS_MSUB = 429; - public static final int MIPS_INS_MSUBF = 430; - public static final int MIPS_INS_MSUBR_Q = 431; - public static final int MIPS_INS_MSUBU = 432; - public static final int MIPS_INS_MSUBV = 433; - public static final int MIPS_INS_MSUB_Q = 434; - public static final int MIPS_INS_MTC0 = 435; - public static final int MIPS_INS_MTC1 = 436; - public static final int MIPS_INS_MTC2 = 437; - public static final int MIPS_INS_MTHC1 = 438; - public static final int MIPS_INS_MTHI = 439; - public static final int MIPS_INS_MTHLIP = 440; - public static final int MIPS_INS_MTLO = 441; - public static final int MIPS_INS_MTM0 = 442; - public static final int MIPS_INS_MTM1 = 443; - public static final int MIPS_INS_MTM2 = 444; - public static final int MIPS_INS_MTP0 = 445; - public static final int MIPS_INS_MTP1 = 446; - public static final int MIPS_INS_MTP2 = 447; - public static final int MIPS_INS_MUH = 448; - public static final int MIPS_INS_MUHU = 449; - public static final int MIPS_INS_MULEQ_S = 450; - public static final int MIPS_INS_MULEU_S = 451; - public static final int MIPS_INS_MULQ_RS = 452; - public static final int MIPS_INS_MULQ_S = 453; - public static final int MIPS_INS_MULR_Q = 454; - public static final int MIPS_INS_MULSAQ_S = 455; - public static final int MIPS_INS_MULSA = 456; - public static final int MIPS_INS_MULT = 457; - public static final int MIPS_INS_MULTU = 458; - public static final int MIPS_INS_MULU = 459; - public static final int MIPS_INS_MULV = 460; - public static final int MIPS_INS_MUL_Q = 461; - public static final int MIPS_INS_MUL_S = 462; - public static final int MIPS_INS_NLOC = 463; - public static final int MIPS_INS_NLZC = 464; - public static final int MIPS_INS_NMADD = 465; - public static final int MIPS_INS_NMSUB = 466; - public static final int MIPS_INS_NOR = 467; - public static final int MIPS_INS_NORI = 468; - public static final int MIPS_INS_NOT16 = 469; - public static final int MIPS_INS_NOT = 470; - public static final int MIPS_INS_OR = 471; - public static final int MIPS_INS_OR16 = 472; - public static final int MIPS_INS_ORI = 473; - public static final int MIPS_INS_PACKRL = 474; - public static final int MIPS_INS_PAUSE = 475; - public static final int MIPS_INS_PCKEV = 476; - public static final int MIPS_INS_PCKOD = 477; - public static final int MIPS_INS_PCNT = 478; - public static final int MIPS_INS_PICK = 479; - public static final int MIPS_INS_POP = 480; - public static final int MIPS_INS_PRECEQU = 481; - public static final int MIPS_INS_PRECEQ = 482; - public static final int MIPS_INS_PRECEU = 483; - public static final int MIPS_INS_PRECRQU_S = 484; - public static final int MIPS_INS_PRECRQ = 485; - public static final int MIPS_INS_PRECRQ_RS = 486; - public static final int MIPS_INS_PRECR = 487; - public static final int MIPS_INS_PRECR_SRA = 488; - public static final int MIPS_INS_PRECR_SRA_R = 489; - public static final int MIPS_INS_PREF = 490; - public static final int MIPS_INS_PREPEND = 491; - public static final int MIPS_INS_RADDU = 492; - public static final int MIPS_INS_RDDSP = 493; - public static final int MIPS_INS_RDHWR = 494; - public static final int MIPS_INS_REPLV = 495; - public static final int MIPS_INS_REPL = 496; - public static final int MIPS_INS_RINT = 497; - public static final int MIPS_INS_ROTR = 498; - public static final int MIPS_INS_ROTRV = 499; - public static final int MIPS_INS_ROUND = 500; - public static final int MIPS_INS_SAT_S = 501; - public static final int MIPS_INS_SAT_U = 502; - public static final int MIPS_INS_SB = 503; - public static final int MIPS_INS_SB16 = 504; - public static final int MIPS_INS_SC = 505; - public static final int MIPS_INS_SCD = 506; - public static final int MIPS_INS_SD = 507; - public static final int MIPS_INS_SDBBP = 508; - public static final int MIPS_INS_SDBBP16 = 509; - public static final int MIPS_INS_SDC1 = 510; - public static final int MIPS_INS_SDC2 = 511; - public static final int MIPS_INS_SDC3 = 512; - public static final int MIPS_INS_SDL = 513; - public static final int MIPS_INS_SDR = 514; - public static final int MIPS_INS_SDXC1 = 515; - public static final int MIPS_INS_SEB = 516; - public static final int MIPS_INS_SEH = 517; - public static final int MIPS_INS_SELEQZ = 518; - public static final int MIPS_INS_SELNEZ = 519; - public static final int MIPS_INS_SEL = 520; - public static final int MIPS_INS_SEQ = 521; - public static final int MIPS_INS_SEQI = 522; - public static final int MIPS_INS_SH = 523; - public static final int MIPS_INS_SH16 = 524; - public static final int MIPS_INS_SHF = 525; - public static final int MIPS_INS_SHILO = 526; - public static final int MIPS_INS_SHILOV = 527; - public static final int MIPS_INS_SHLLV = 528; - public static final int MIPS_INS_SHLLV_S = 529; - public static final int MIPS_INS_SHLL = 530; - public static final int MIPS_INS_SHLL_S = 531; - public static final int MIPS_INS_SHRAV = 532; - public static final int MIPS_INS_SHRAV_R = 533; - public static final int MIPS_INS_SHRA = 534; - public static final int MIPS_INS_SHRA_R = 535; - public static final int MIPS_INS_SHRLV = 536; - public static final int MIPS_INS_SHRL = 537; - public static final int MIPS_INS_SLDI = 538; - public static final int MIPS_INS_SLD = 539; - public static final int MIPS_INS_SLL = 540; - public static final int MIPS_INS_SLL16 = 541; - public static final int MIPS_INS_SLLI = 542; - public static final int MIPS_INS_SLLV = 543; - public static final int MIPS_INS_SLT = 544; - public static final int MIPS_INS_SLTI = 545; - public static final int MIPS_INS_SLTIU = 546; - public static final int MIPS_INS_SLTU = 547; - public static final int MIPS_INS_SNE = 548; - public static final int MIPS_INS_SNEI = 549; - public static final int MIPS_INS_SPLATI = 550; - public static final int MIPS_INS_SPLAT = 551; - public static final int MIPS_INS_SRA = 552; - public static final int MIPS_INS_SRAI = 553; - public static final int MIPS_INS_SRARI = 554; - public static final int MIPS_INS_SRAR = 555; - public static final int MIPS_INS_SRAV = 556; - public static final int MIPS_INS_SRL = 557; - public static final int MIPS_INS_SRL16 = 558; - public static final int MIPS_INS_SRLI = 559; - public static final int MIPS_INS_SRLRI = 560; - public static final int MIPS_INS_SRLR = 561; - public static final int MIPS_INS_SRLV = 562; - public static final int MIPS_INS_SSNOP = 563; - public static final int MIPS_INS_ST = 564; - public static final int MIPS_INS_SUBQH = 565; - public static final int MIPS_INS_SUBQH_R = 566; - public static final int MIPS_INS_SUBQ = 567; - public static final int MIPS_INS_SUBQ_S = 568; - public static final int MIPS_INS_SUBSUS_U = 569; - public static final int MIPS_INS_SUBSUU_S = 570; - public static final int MIPS_INS_SUBS_S = 571; - public static final int MIPS_INS_SUBS_U = 572; - public static final int MIPS_INS_SUBU16 = 573; - public static final int MIPS_INS_SUBUH = 574; - public static final int MIPS_INS_SUBUH_R = 575; - public static final int MIPS_INS_SUBU = 576; - public static final int MIPS_INS_SUBU_S = 577; - public static final int MIPS_INS_SUBVI = 578; - public static final int MIPS_INS_SUBV = 579; - public static final int MIPS_INS_SUXC1 = 580; - public static final int MIPS_INS_SW = 581; - public static final int MIPS_INS_SW16 = 582; - public static final int MIPS_INS_SWC1 = 583; - public static final int MIPS_INS_SWC2 = 584; - public static final int MIPS_INS_SWC3 = 585; - public static final int MIPS_INS_SWL = 586; - public static final int MIPS_INS_SWM16 = 587; - public static final int MIPS_INS_SWM32 = 588; - public static final int MIPS_INS_SWP = 589; - public static final int MIPS_INS_SWR = 590; - public static final int MIPS_INS_SWXC1 = 591; - public static final int MIPS_INS_SYNC = 592; - public static final int MIPS_INS_SYNCI = 593; - public static final int MIPS_INS_SYSCALL = 594; - public static final int MIPS_INS_TEQ = 595; - public static final int MIPS_INS_TEQI = 596; - public static final int MIPS_INS_TGE = 597; - public static final int MIPS_INS_TGEI = 598; - public static final int MIPS_INS_TGEIU = 599; - public static final int MIPS_INS_TGEU = 600; - public static final int MIPS_INS_TLBP = 601; - public static final int MIPS_INS_TLBR = 602; - public static final int MIPS_INS_TLBWI = 603; - public static final int MIPS_INS_TLBWR = 604; - public static final int MIPS_INS_TLT = 605; - public static final int MIPS_INS_TLTI = 606; - public static final int MIPS_INS_TLTIU = 607; - public static final int MIPS_INS_TLTU = 608; - public static final int MIPS_INS_TNE = 609; - public static final int MIPS_INS_TNEI = 610; - public static final int MIPS_INS_TRUNC = 611; - public static final int MIPS_INS_V3MULU = 612; - public static final int MIPS_INS_VMM0 = 613; - public static final int MIPS_INS_VMULU = 614; - public static final int MIPS_INS_VSHF = 615; - public static final int MIPS_INS_WAIT = 616; - public static final int MIPS_INS_WRDSP = 617; - public static final int MIPS_INS_WSBH = 618; - public static final int MIPS_INS_XOR = 619; - public static final int MIPS_INS_XOR16 = 620; - public static final int MIPS_INS_XORI = 621; - - // some alias instructions - public static final int MIPS_INS_NOP = 622; - public static final int MIPS_INS_NEGU = 623; - - // special instructions - public static final int MIPS_INS_JALR_HB = 624; - public static final int MIPS_INS_JR_HB = 625; - public static final int MIPS_INS_ENDING = 626; + public static final int MIPS_INS_ABS = 1; + public static final int MIPS_INS_ALIGN = 2; + public static final int MIPS_INS_BEQL = 3; + public static final int MIPS_INS_BGE = 4; + public static final int MIPS_INS_BGEL = 5; + public static final int MIPS_INS_BGEU = 6; + public static final int MIPS_INS_BGEUL = 7; + public static final int MIPS_INS_BGT = 8; + public static final int MIPS_INS_BGTL = 9; + public static final int MIPS_INS_BGTU = 10; + public static final int MIPS_INS_BGTUL = 11; + public static final int MIPS_INS_BLE = 12; + public static final int MIPS_INS_BLEL = 13; + public static final int MIPS_INS_BLEU = 14; + public static final int MIPS_INS_BLEUL = 15; + public static final int MIPS_INS_BLT = 16; + public static final int MIPS_INS_BLTL = 17; + public static final int MIPS_INS_BLTU = 18; + public static final int MIPS_INS_BLTUL = 19; + public static final int MIPS_INS_BNEL = 20; + public static final int MIPS_INS_B = 21; + public static final int MIPS_INS_BEQ = 22; + public static final int MIPS_INS_BNE = 23; + public static final int MIPS_INS_CFTC1 = 24; + public static final int MIPS_INS_CTTC1 = 25; + public static final int MIPS_INS_DMUL = 26; + public static final int MIPS_INS_DMULO = 27; + public static final int MIPS_INS_DMULOU = 28; + public static final int MIPS_INS_DROL = 29; + public static final int MIPS_INS_DROR = 30; + public static final int MIPS_INS_DDIV = 31; + public static final int MIPS_INS_DREM = 32; + public static final int MIPS_INS_DDIVU = 33; + public static final int MIPS_INS_DREMU = 34; + public static final int MIPS_INS_JAL = 35; + public static final int MIPS_INS_LD = 36; + public static final int MIPS_INS_LWM = 37; + public static final int MIPS_INS_LA = 38; + public static final int MIPS_INS_DLA = 39; + public static final int MIPS_INS_LI = 40; + public static final int MIPS_INS_DLI = 41; + public static final int MIPS_INS_LI_D = 42; + public static final int MIPS_INS_LI_S = 43; + public static final int MIPS_INS_MFTACX = 44; + public static final int MIPS_INS_MFTC0 = 45; + public static final int MIPS_INS_MFTC1 = 46; + public static final int MIPS_INS_MFTDSP = 47; + public static final int MIPS_INS_MFTGPR = 48; + public static final int MIPS_INS_MFTHC1 = 49; + public static final int MIPS_INS_MFTHI = 50; + public static final int MIPS_INS_MFTLO = 51; + public static final int MIPS_INS_MTTACX = 52; + public static final int MIPS_INS_MTTC0 = 53; + public static final int MIPS_INS_MTTC1 = 54; + public static final int MIPS_INS_MTTDSP = 55; + public static final int MIPS_INS_MTTGPR = 56; + public static final int MIPS_INS_MTTHC1 = 57; + public static final int MIPS_INS_MTTHI = 58; + public static final int MIPS_INS_MTTLO = 59; + public static final int MIPS_INS_MUL = 60; + public static final int MIPS_INS_MULO = 61; + public static final int MIPS_INS_MULOU = 62; + public static final int MIPS_INS_NOR = 63; + public static final int MIPS_INS_ADDIU = 64; + public static final int MIPS_INS_ANDI = 65; + public static final int MIPS_INS_SUBU = 66; + public static final int MIPS_INS_TRUNC_W_D = 67; + public static final int MIPS_INS_TRUNC_W_S = 68; + public static final int MIPS_INS_ROL = 69; + public static final int MIPS_INS_ROR = 70; + public static final int MIPS_INS_S_D = 71; + public static final int MIPS_INS_SD = 72; + public static final int MIPS_INS_DIV = 73; + public static final int MIPS_INS_SEQ = 74; + public static final int MIPS_INS_SGE = 75; + public static final int MIPS_INS_SGEU = 76; + public static final int MIPS_INS_SGT = 77; + public static final int MIPS_INS_SGTU = 78; + public static final int MIPS_INS_SLE = 79; + public static final int MIPS_INS_SLEU = 80; + public static final int MIPS_INS_SLT = 81; + public static final int MIPS_INS_SLTU = 82; + public static final int MIPS_INS_SNE = 83; + public static final int MIPS_INS_REM = 84; + public static final int MIPS_INS_SWM = 85; + public static final int MIPS_INS_SAA = 86; + public static final int MIPS_INS_SAAD = 87; + public static final int MIPS_INS_DIVU = 88; + public static final int MIPS_INS_REMU = 89; + public static final int MIPS_INS_ULH = 90; + public static final int MIPS_INS_ULHU = 91; + public static final int MIPS_INS_ULW = 92; + public static final int MIPS_INS_USH = 93; + public static final int MIPS_INS_USW = 94; + public static final int MIPS_INS_ABSQ_S_PH = 95; + public static final int MIPS_INS_ABSQ_S_QB = 96; + public static final int MIPS_INS_ABSQ_S_W = 97; + public static final int MIPS_INS_ADD = 98; + public static final int MIPS_INS_ADDIUPC = 99; + public static final int MIPS_INS_ADDIUR1SP = 100; + public static final int MIPS_INS_ADDIUR2 = 101; + public static final int MIPS_INS_ADDIUS5 = 102; + public static final int MIPS_INS_ADDIUSP = 103; + public static final int MIPS_INS_ADDQH_PH = 104; + public static final int MIPS_INS_ADDQH_R_PH = 105; + public static final int MIPS_INS_ADDQH_R_W = 106; + public static final int MIPS_INS_ADDQH_W = 107; + public static final int MIPS_INS_ADDQ_PH = 108; + public static final int MIPS_INS_ADDQ_S_PH = 109; + public static final int MIPS_INS_ADDQ_S_W = 110; + public static final int MIPS_INS_ADDR_PS = 111; + public static final int MIPS_INS_ADDSC = 112; + public static final int MIPS_INS_ADDS_A_B = 113; + public static final int MIPS_INS_ADDS_A_D = 114; + public static final int MIPS_INS_ADDS_A_H = 115; + public static final int MIPS_INS_ADDS_A_W = 116; + public static final int MIPS_INS_ADDS_S_B = 117; + public static final int MIPS_INS_ADDS_S_D = 118; + public static final int MIPS_INS_ADDS_S_H = 119; + public static final int MIPS_INS_ADDS_S_W = 120; + public static final int MIPS_INS_ADDS_U_B = 121; + public static final int MIPS_INS_ADDS_U_D = 122; + public static final int MIPS_INS_ADDS_U_H = 123; + public static final int MIPS_INS_ADDS_U_W = 124; + public static final int MIPS_INS_ADDU16 = 125; + public static final int MIPS_INS_ADDUH_QB = 126; + public static final int MIPS_INS_ADDUH_R_QB = 127; + public static final int MIPS_INS_ADDU = 128; + public static final int MIPS_INS_ADDU_PH = 129; + public static final int MIPS_INS_ADDU_QB = 130; + public static final int MIPS_INS_ADDU_S_PH = 131; + public static final int MIPS_INS_ADDU_S_QB = 132; + public static final int MIPS_INS_ADDVI_B = 133; + public static final int MIPS_INS_ADDVI_D = 134; + public static final int MIPS_INS_ADDVI_H = 135; + public static final int MIPS_INS_ADDVI_W = 136; + public static final int MIPS_INS_ADDV_B = 137; + public static final int MIPS_INS_ADDV_D = 138; + public static final int MIPS_INS_ADDV_H = 139; + public static final int MIPS_INS_ADDV_W = 140; + public static final int MIPS_INS_ADDWC = 141; + public static final int MIPS_INS_ADD_A_B = 142; + public static final int MIPS_INS_ADD_A_D = 143; + public static final int MIPS_INS_ADD_A_H = 144; + public static final int MIPS_INS_ADD_A_W = 145; + public static final int MIPS_INS_ADDI = 146; + public static final int MIPS_INS_ALUIPC = 147; + public static final int MIPS_INS_AND = 148; + public static final int MIPS_INS_AND16 = 149; + public static final int MIPS_INS_ANDI16 = 150; + public static final int MIPS_INS_ANDI_B = 151; + public static final int MIPS_INS_AND_V = 152; + public static final int MIPS_INS_APPEND = 153; + public static final int MIPS_INS_ASUB_S_B = 154; + public static final int MIPS_INS_ASUB_S_D = 155; + public static final int MIPS_INS_ASUB_S_H = 156; + public static final int MIPS_INS_ASUB_S_W = 157; + public static final int MIPS_INS_ASUB_U_B = 158; + public static final int MIPS_INS_ASUB_U_D = 159; + public static final int MIPS_INS_ASUB_U_H = 160; + public static final int MIPS_INS_ASUB_U_W = 161; + public static final int MIPS_INS_AUI = 162; + public static final int MIPS_INS_AUIPC = 163; + public static final int MIPS_INS_AVER_S_B = 164; + public static final int MIPS_INS_AVER_S_D = 165; + public static final int MIPS_INS_AVER_S_H = 166; + public static final int MIPS_INS_AVER_S_W = 167; + public static final int MIPS_INS_AVER_U_B = 168; + public static final int MIPS_INS_AVER_U_D = 169; + public static final int MIPS_INS_AVER_U_H = 170; + public static final int MIPS_INS_AVER_U_W = 171; + public static final int MIPS_INS_AVE_S_B = 172; + public static final int MIPS_INS_AVE_S_D = 173; + public static final int MIPS_INS_AVE_S_H = 174; + public static final int MIPS_INS_AVE_S_W = 175; + public static final int MIPS_INS_AVE_U_B = 176; + public static final int MIPS_INS_AVE_U_D = 177; + public static final int MIPS_INS_AVE_U_H = 178; + public static final int MIPS_INS_AVE_U_W = 179; + public static final int MIPS_INS_B16 = 180; + public static final int MIPS_INS_BADDU = 181; + public static final int MIPS_INS_BAL = 182; + public static final int MIPS_INS_BALC = 183; + public static final int MIPS_INS_BALIGN = 184; + public static final int MIPS_INS_BALRSC = 185; + public static final int MIPS_INS_BBEQZC = 186; + public static final int MIPS_INS_BBIT0 = 187; + public static final int MIPS_INS_BBIT032 = 188; + public static final int MIPS_INS_BBIT1 = 189; + public static final int MIPS_INS_BBIT132 = 190; + public static final int MIPS_INS_BBNEZC = 191; + public static final int MIPS_INS_BC = 192; + public static final int MIPS_INS_BC16 = 193; + public static final int MIPS_INS_BC1EQZ = 194; + public static final int MIPS_INS_BC1EQZC = 195; + public static final int MIPS_INS_BC1F = 196; + public static final int MIPS_INS_BC1FL = 197; + public static final int MIPS_INS_BC1NEZ = 198; + public static final int MIPS_INS_BC1NEZC = 199; + public static final int MIPS_INS_BC1T = 200; + public static final int MIPS_INS_BC1TL = 201; + public static final int MIPS_INS_BC2EQZ = 202; + public static final int MIPS_INS_BC2EQZC = 203; + public static final int MIPS_INS_BC2NEZ = 204; + public static final int MIPS_INS_BC2NEZC = 205; + public static final int MIPS_INS_BCLRI_B = 206; + public static final int MIPS_INS_BCLRI_D = 207; + public static final int MIPS_INS_BCLRI_H = 208; + public static final int MIPS_INS_BCLRI_W = 209; + public static final int MIPS_INS_BCLR_B = 210; + public static final int MIPS_INS_BCLR_D = 211; + public static final int MIPS_INS_BCLR_H = 212; + public static final int MIPS_INS_BCLR_W = 213; + public static final int MIPS_INS_BEQC = 214; + public static final int MIPS_INS_BEQIC = 215; + public static final int MIPS_INS_BEQZ16 = 216; + public static final int MIPS_INS_BEQZALC = 217; + public static final int MIPS_INS_BEQZC = 218; + public static final int MIPS_INS_BEQZC16 = 219; + public static final int MIPS_INS_BGEC = 220; + public static final int MIPS_INS_BGEIC = 221; + public static final int MIPS_INS_BGEIUC = 222; + public static final int MIPS_INS_BGEUC = 223; + public static final int MIPS_INS_BGEZ = 224; + public static final int MIPS_INS_BGEZAL = 225; + public static final int MIPS_INS_BGEZALC = 226; + public static final int MIPS_INS_BGEZALL = 227; + public static final int MIPS_INS_BGEZALS = 228; + public static final int MIPS_INS_BGEZC = 229; + public static final int MIPS_INS_BGEZL = 230; + public static final int MIPS_INS_BGTZ = 231; + public static final int MIPS_INS_BGTZALC = 232; + public static final int MIPS_INS_BGTZC = 233; + public static final int MIPS_INS_BGTZL = 234; + public static final int MIPS_INS_BINSLI_B = 235; + public static final int MIPS_INS_BINSLI_D = 236; + public static final int MIPS_INS_BINSLI_H = 237; + public static final int MIPS_INS_BINSLI_W = 238; + public static final int MIPS_INS_BINSL_B = 239; + public static final int MIPS_INS_BINSL_D = 240; + public static final int MIPS_INS_BINSL_H = 241; + public static final int MIPS_INS_BINSL_W = 242; + public static final int MIPS_INS_BINSRI_B = 243; + public static final int MIPS_INS_BINSRI_D = 244; + public static final int MIPS_INS_BINSRI_H = 245; + public static final int MIPS_INS_BINSRI_W = 246; + public static final int MIPS_INS_BINSR_B = 247; + public static final int MIPS_INS_BINSR_D = 248; + public static final int MIPS_INS_BINSR_H = 249; + public static final int MIPS_INS_BINSR_W = 250; + public static final int MIPS_INS_BITREV = 251; + public static final int MIPS_INS_BITREVW = 252; + public static final int MIPS_INS_BITSWAP = 253; + public static final int MIPS_INS_BLEZ = 254; + public static final int MIPS_INS_BLEZALC = 255; + public static final int MIPS_INS_BLEZC = 256; + public static final int MIPS_INS_BLEZL = 257; + public static final int MIPS_INS_BLTC = 258; + public static final int MIPS_INS_BLTIC = 259; + public static final int MIPS_INS_BLTIUC = 260; + public static final int MIPS_INS_BLTUC = 261; + public static final int MIPS_INS_BLTZ = 262; + public static final int MIPS_INS_BLTZAL = 263; + public static final int MIPS_INS_BLTZALC = 264; + public static final int MIPS_INS_BLTZALL = 265; + public static final int MIPS_INS_BLTZALS = 266; + public static final int MIPS_INS_BLTZC = 267; + public static final int MIPS_INS_BLTZL = 268; + public static final int MIPS_INS_BMNZI_B = 269; + public static final int MIPS_INS_BMNZ_V = 270; + public static final int MIPS_INS_BMZI_B = 271; + public static final int MIPS_INS_BMZ_V = 272; + public static final int MIPS_INS_BNEC = 273; + public static final int MIPS_INS_BNEGI_B = 274; + public static final int MIPS_INS_BNEGI_D = 275; + public static final int MIPS_INS_BNEGI_H = 276; + public static final int MIPS_INS_BNEGI_W = 277; + public static final int MIPS_INS_BNEG_B = 278; + public static final int MIPS_INS_BNEG_D = 279; + public static final int MIPS_INS_BNEG_H = 280; + public static final int MIPS_INS_BNEG_W = 281; + public static final int MIPS_INS_BNEIC = 282; + public static final int MIPS_INS_BNEZ16 = 283; + public static final int MIPS_INS_BNEZALC = 284; + public static final int MIPS_INS_BNEZC = 285; + public static final int MIPS_INS_BNEZC16 = 286; + public static final int MIPS_INS_BNVC = 287; + public static final int MIPS_INS_BNZ_B = 288; + public static final int MIPS_INS_BNZ_D = 289; + public static final int MIPS_INS_BNZ_H = 290; + public static final int MIPS_INS_BNZ_V = 291; + public static final int MIPS_INS_BNZ_W = 292; + public static final int MIPS_INS_BOVC = 293; + public static final int MIPS_INS_BPOSGE32 = 294; + public static final int MIPS_INS_BPOSGE32C = 295; + public static final int MIPS_INS_BREAK = 296; + public static final int MIPS_INS_BREAK16 = 297; + public static final int MIPS_INS_BRSC = 298; + public static final int MIPS_INS_BSELI_B = 299; + public static final int MIPS_INS_BSEL_V = 300; + public static final int MIPS_INS_BSETI_B = 301; + public static final int MIPS_INS_BSETI_D = 302; + public static final int MIPS_INS_BSETI_H = 303; + public static final int MIPS_INS_BSETI_W = 304; + public static final int MIPS_INS_BSET_B = 305; + public static final int MIPS_INS_BSET_D = 306; + public static final int MIPS_INS_BSET_H = 307; + public static final int MIPS_INS_BSET_W = 308; + public static final int MIPS_INS_BYTEREVW = 309; + public static final int MIPS_INS_BZ_B = 310; + public static final int MIPS_INS_BZ_D = 311; + public static final int MIPS_INS_BZ_H = 312; + public static final int MIPS_INS_BZ_V = 313; + public static final int MIPS_INS_BZ_W = 314; + public static final int MIPS_INS_BEQZ = 315; + public static final int MIPS_INS_BNEZ = 316; + public static final int MIPS_INS_BTEQZ = 317; + public static final int MIPS_INS_BTNEZ = 318; + public static final int MIPS_INS_CACHE = 319; + public static final int MIPS_INS_CACHEE = 320; + public static final int MIPS_INS_CEIL_L_D = 321; + public static final int MIPS_INS_CEIL_L_S = 322; + public static final int MIPS_INS_CEIL_W_D = 323; + public static final int MIPS_INS_CEIL_W_S = 324; + public static final int MIPS_INS_CEQI_B = 325; + public static final int MIPS_INS_CEQI_D = 326; + public static final int MIPS_INS_CEQI_H = 327; + public static final int MIPS_INS_CEQI_W = 328; + public static final int MIPS_INS_CEQ_B = 329; + public static final int MIPS_INS_CEQ_D = 330; + public static final int MIPS_INS_CEQ_H = 331; + public static final int MIPS_INS_CEQ_W = 332; + public static final int MIPS_INS_CFC1 = 333; + public static final int MIPS_INS_CFC2 = 334; + public static final int MIPS_INS_CFCMSA = 335; + public static final int MIPS_INS_CINS = 336; + public static final int MIPS_INS_CINS32 = 337; + public static final int MIPS_INS_CLASS_D = 338; + public static final int MIPS_INS_CLASS_S = 339; + public static final int MIPS_INS_CLEI_S_B = 340; + public static final int MIPS_INS_CLEI_S_D = 341; + public static final int MIPS_INS_CLEI_S_H = 342; + public static final int MIPS_INS_CLEI_S_W = 343; + public static final int MIPS_INS_CLEI_U_B = 344; + public static final int MIPS_INS_CLEI_U_D = 345; + public static final int MIPS_INS_CLEI_U_H = 346; + public static final int MIPS_INS_CLEI_U_W = 347; + public static final int MIPS_INS_CLE_S_B = 348; + public static final int MIPS_INS_CLE_S_D = 349; + public static final int MIPS_INS_CLE_S_H = 350; + public static final int MIPS_INS_CLE_S_W = 351; + public static final int MIPS_INS_CLE_U_B = 352; + public static final int MIPS_INS_CLE_U_D = 353; + public static final int MIPS_INS_CLE_U_H = 354; + public static final int MIPS_INS_CLE_U_W = 355; + public static final int MIPS_INS_CLO = 356; + public static final int MIPS_INS_CLTI_S_B = 357; + public static final int MIPS_INS_CLTI_S_D = 358; + public static final int MIPS_INS_CLTI_S_H = 359; + public static final int MIPS_INS_CLTI_S_W = 360; + public static final int MIPS_INS_CLTI_U_B = 361; + public static final int MIPS_INS_CLTI_U_D = 362; + public static final int MIPS_INS_CLTI_U_H = 363; + public static final int MIPS_INS_CLTI_U_W = 364; + public static final int MIPS_INS_CLT_S_B = 365; + public static final int MIPS_INS_CLT_S_D = 366; + public static final int MIPS_INS_CLT_S_H = 367; + public static final int MIPS_INS_CLT_S_W = 368; + public static final int MIPS_INS_CLT_U_B = 369; + public static final int MIPS_INS_CLT_U_D = 370; + public static final int MIPS_INS_CLT_U_H = 371; + public static final int MIPS_INS_CLT_U_W = 372; + public static final int MIPS_INS_CLZ = 373; + public static final int MIPS_INS_CMPGDU_EQ_QB = 374; + public static final int MIPS_INS_CMPGDU_LE_QB = 375; + public static final int MIPS_INS_CMPGDU_LT_QB = 376; + public static final int MIPS_INS_CMPGU_EQ_QB = 377; + public static final int MIPS_INS_CMPGU_LE_QB = 378; + public static final int MIPS_INS_CMPGU_LT_QB = 379; + public static final int MIPS_INS_CMPU_EQ_QB = 380; + public static final int MIPS_INS_CMPU_LE_QB = 381; + public static final int MIPS_INS_CMPU_LT_QB = 382; + public static final int MIPS_INS_CMP_AF_D = 383; + public static final int MIPS_INS_CMP_AF_S = 384; + public static final int MIPS_INS_CMP_EQ_D = 385; + public static final int MIPS_INS_CMP_EQ_PH = 386; + public static final int MIPS_INS_CMP_EQ_S = 387; + public static final int MIPS_INS_CMP_LE_D = 388; + public static final int MIPS_INS_CMP_LE_PH = 389; + public static final int MIPS_INS_CMP_LE_S = 390; + public static final int MIPS_INS_CMP_LT_D = 391; + public static final int MIPS_INS_CMP_LT_PH = 392; + public static final int MIPS_INS_CMP_LT_S = 393; + public static final int MIPS_INS_CMP_SAF_D = 394; + public static final int MIPS_INS_CMP_SAF_S = 395; + public static final int MIPS_INS_CMP_SEQ_D = 396; + public static final int MIPS_INS_CMP_SEQ_S = 397; + public static final int MIPS_INS_CMP_SLE_D = 398; + public static final int MIPS_INS_CMP_SLE_S = 399; + public static final int MIPS_INS_CMP_SLT_D = 400; + public static final int MIPS_INS_CMP_SLT_S = 401; + public static final int MIPS_INS_CMP_SUEQ_D = 402; + public static final int MIPS_INS_CMP_SUEQ_S = 403; + public static final int MIPS_INS_CMP_SULE_D = 404; + public static final int MIPS_INS_CMP_SULE_S = 405; + public static final int MIPS_INS_CMP_SULT_D = 406; + public static final int MIPS_INS_CMP_SULT_S = 407; + public static final int MIPS_INS_CMP_SUN_D = 408; + public static final int MIPS_INS_CMP_SUN_S = 409; + public static final int MIPS_INS_CMP_UEQ_D = 410; + public static final int MIPS_INS_CMP_UEQ_S = 411; + public static final int MIPS_INS_CMP_ULE_D = 412; + public static final int MIPS_INS_CMP_ULE_S = 413; + public static final int MIPS_INS_CMP_ULT_D = 414; + public static final int MIPS_INS_CMP_ULT_S = 415; + public static final int MIPS_INS_CMP_UN_D = 416; + public static final int MIPS_INS_CMP_UN_S = 417; + public static final int MIPS_INS_COPY_S_B = 418; + public static final int MIPS_INS_COPY_S_D = 419; + public static final int MIPS_INS_COPY_S_H = 420; + public static final int MIPS_INS_COPY_S_W = 421; + public static final int MIPS_INS_COPY_U_B = 422; + public static final int MIPS_INS_COPY_U_H = 423; + public static final int MIPS_INS_COPY_U_W = 424; + public static final int MIPS_INS_CRC32B = 425; + public static final int MIPS_INS_CRC32CB = 426; + public static final int MIPS_INS_CRC32CD = 427; + public static final int MIPS_INS_CRC32CH = 428; + public static final int MIPS_INS_CRC32CW = 429; + public static final int MIPS_INS_CRC32D = 430; + public static final int MIPS_INS_CRC32H = 431; + public static final int MIPS_INS_CRC32W = 432; + public static final int MIPS_INS_CTC1 = 433; + public static final int MIPS_INS_CTC2 = 434; + public static final int MIPS_INS_CTCMSA = 435; + public static final int MIPS_INS_CVT_D_S = 436; + public static final int MIPS_INS_CVT_D_W = 437; + public static final int MIPS_INS_CVT_D_L = 438; + public static final int MIPS_INS_CVT_L_D = 439; + public static final int MIPS_INS_CVT_L_S = 440; + public static final int MIPS_INS_CVT_PS_PW = 441; + public static final int MIPS_INS_CVT_PS_S = 442; + public static final int MIPS_INS_CVT_PW_PS = 443; + public static final int MIPS_INS_CVT_S_D = 444; + public static final int MIPS_INS_CVT_S_L = 445; + public static final int MIPS_INS_CVT_S_PL = 446; + public static final int MIPS_INS_CVT_S_PU = 447; + public static final int MIPS_INS_CVT_S_W = 448; + public static final int MIPS_INS_CVT_W_D = 449; + public static final int MIPS_INS_CVT_W_S = 450; + public static final int MIPS_INS_C_EQ_D = 451; + public static final int MIPS_INS_C_EQ_S = 452; + public static final int MIPS_INS_C_F_D = 453; + public static final int MIPS_INS_C_F_S = 454; + public static final int MIPS_INS_C_LE_D = 455; + public static final int MIPS_INS_C_LE_S = 456; + public static final int MIPS_INS_C_LT_D = 457; + public static final int MIPS_INS_C_LT_S = 458; + public static final int MIPS_INS_C_NGE_D = 459; + public static final int MIPS_INS_C_NGE_S = 460; + public static final int MIPS_INS_C_NGLE_D = 461; + public static final int MIPS_INS_C_NGLE_S = 462; + public static final int MIPS_INS_C_NGL_D = 463; + public static final int MIPS_INS_C_NGL_S = 464; + public static final int MIPS_INS_C_NGT_D = 465; + public static final int MIPS_INS_C_NGT_S = 466; + public static final int MIPS_INS_C_OLE_D = 467; + public static final int MIPS_INS_C_OLE_S = 468; + public static final int MIPS_INS_C_OLT_D = 469; + public static final int MIPS_INS_C_OLT_S = 470; + public static final int MIPS_INS_C_SEQ_D = 471; + public static final int MIPS_INS_C_SEQ_S = 472; + public static final int MIPS_INS_C_SF_D = 473; + public static final int MIPS_INS_C_SF_S = 474; + public static final int MIPS_INS_C_UEQ_D = 475; + public static final int MIPS_INS_C_UEQ_S = 476; + public static final int MIPS_INS_C_ULE_D = 477; + public static final int MIPS_INS_C_ULE_S = 478; + public static final int MIPS_INS_C_ULT_D = 479; + public static final int MIPS_INS_C_ULT_S = 480; + public static final int MIPS_INS_C_UN_D = 481; + public static final int MIPS_INS_C_UN_S = 482; + public static final int MIPS_INS_CMP = 483; + public static final int MIPS_INS_CMPI = 484; + public static final int MIPS_INS_DADD = 485; + public static final int MIPS_INS_DADDI = 486; + public static final int MIPS_INS_DADDIU = 487; + public static final int MIPS_INS_DADDU = 488; + public static final int MIPS_INS_DAHI = 489; + public static final int MIPS_INS_DALIGN = 490; + public static final int MIPS_INS_DATI = 491; + public static final int MIPS_INS_DAUI = 492; + public static final int MIPS_INS_DBITSWAP = 493; + public static final int MIPS_INS_DCLO = 494; + public static final int MIPS_INS_DCLZ = 495; + public static final int MIPS_INS_DERET = 496; + public static final int MIPS_INS_DEXT = 497; + public static final int MIPS_INS_DEXTM = 498; + public static final int MIPS_INS_DEXTU = 499; + public static final int MIPS_INS_DI = 500; + public static final int MIPS_INS_DINS = 501; + public static final int MIPS_INS_DINSM = 502; + public static final int MIPS_INS_DINSU = 503; + public static final int MIPS_INS_DIV_S_B = 504; + public static final int MIPS_INS_DIV_S_D = 505; + public static final int MIPS_INS_DIV_S_H = 506; + public static final int MIPS_INS_DIV_S_W = 507; + public static final int MIPS_INS_DIV_U_B = 508; + public static final int MIPS_INS_DIV_U_D = 509; + public static final int MIPS_INS_DIV_U_H = 510; + public static final int MIPS_INS_DIV_U_W = 511; + public static final int MIPS_INS_DLSA = 512; + public static final int MIPS_INS_DMFC0 = 513; + public static final int MIPS_INS_DMFC1 = 514; + public static final int MIPS_INS_DMFC2 = 515; + public static final int MIPS_INS_DMFGC0 = 516; + public static final int MIPS_INS_DMOD = 517; + public static final int MIPS_INS_DMODU = 518; + public static final int MIPS_INS_DMT = 519; + public static final int MIPS_INS_DMTC0 = 520; + public static final int MIPS_INS_DMTC1 = 521; + public static final int MIPS_INS_DMTC2 = 522; + public static final int MIPS_INS_DMTGC0 = 523; + public static final int MIPS_INS_DMUH = 524; + public static final int MIPS_INS_DMUHU = 525; + public static final int MIPS_INS_DMULT = 526; + public static final int MIPS_INS_DMULTU = 527; + public static final int MIPS_INS_DMULU = 528; + public static final int MIPS_INS_DOTP_S_D = 529; + public static final int MIPS_INS_DOTP_S_H = 530; + public static final int MIPS_INS_DOTP_S_W = 531; + public static final int MIPS_INS_DOTP_U_D = 532; + public static final int MIPS_INS_DOTP_U_H = 533; + public static final int MIPS_INS_DOTP_U_W = 534; + public static final int MIPS_INS_DPADD_S_D = 535; + public static final int MIPS_INS_DPADD_S_H = 536; + public static final int MIPS_INS_DPADD_S_W = 537; + public static final int MIPS_INS_DPADD_U_D = 538; + public static final int MIPS_INS_DPADD_U_H = 539; + public static final int MIPS_INS_DPADD_U_W = 540; + public static final int MIPS_INS_DPAQX_SA_W_PH = 541; + public static final int MIPS_INS_DPAQX_S_W_PH = 542; + public static final int MIPS_INS_DPAQ_SA_L_W = 543; + public static final int MIPS_INS_DPAQ_S_W_PH = 544; + public static final int MIPS_INS_DPAU_H_QBL = 545; + public static final int MIPS_INS_DPAU_H_QBR = 546; + public static final int MIPS_INS_DPAX_W_PH = 547; + public static final int MIPS_INS_DPA_W_PH = 548; + public static final int MIPS_INS_DPOP = 549; + public static final int MIPS_INS_DPSQX_SA_W_PH = 550; + public static final int MIPS_INS_DPSQX_S_W_PH = 551; + public static final int MIPS_INS_DPSQ_SA_L_W = 552; + public static final int MIPS_INS_DPSQ_S_W_PH = 553; + public static final int MIPS_INS_DPSUB_S_D = 554; + public static final int MIPS_INS_DPSUB_S_H = 555; + public static final int MIPS_INS_DPSUB_S_W = 556; + public static final int MIPS_INS_DPSUB_U_D = 557; + public static final int MIPS_INS_DPSUB_U_H = 558; + public static final int MIPS_INS_DPSUB_U_W = 559; + public static final int MIPS_INS_DPSU_H_QBL = 560; + public static final int MIPS_INS_DPSU_H_QBR = 561; + public static final int MIPS_INS_DPSX_W_PH = 562; + public static final int MIPS_INS_DPS_W_PH = 563; + public static final int MIPS_INS_DROTR = 564; + public static final int MIPS_INS_DROTR32 = 565; + public static final int MIPS_INS_DROTRV = 566; + public static final int MIPS_INS_DSBH = 567; + public static final int MIPS_INS_DSHD = 568; + public static final int MIPS_INS_DSLL = 569; + public static final int MIPS_INS_DSLL32 = 570; + public static final int MIPS_INS_DSLLV = 571; + public static final int MIPS_INS_DSRA = 572; + public static final int MIPS_INS_DSRA32 = 573; + public static final int MIPS_INS_DSRAV = 574; + public static final int MIPS_INS_DSRL = 575; + public static final int MIPS_INS_DSRL32 = 576; + public static final int MIPS_INS_DSRLV = 577; + public static final int MIPS_INS_DSUB = 578; + public static final int MIPS_INS_DSUBU = 579; + public static final int MIPS_INS_DVP = 580; + public static final int MIPS_INS_DVPE = 581; + public static final int MIPS_INS_EHB = 582; + public static final int MIPS_INS_EI = 583; + public static final int MIPS_INS_EMT = 584; + public static final int MIPS_INS_ERET = 585; + public static final int MIPS_INS_ERETNC = 586; + public static final int MIPS_INS_EVP = 587; + public static final int MIPS_INS_EVPE = 588; + public static final int MIPS_INS_EXT = 589; + public static final int MIPS_INS_EXTP = 590; + public static final int MIPS_INS_EXTPDP = 591; + public static final int MIPS_INS_EXTPDPV = 592; + public static final int MIPS_INS_EXTPV = 593; + public static final int MIPS_INS_EXTRV_RS_W = 594; + public static final int MIPS_INS_EXTRV_R_W = 595; + public static final int MIPS_INS_EXTRV_S_H = 596; + public static final int MIPS_INS_EXTRV_W = 597; + public static final int MIPS_INS_EXTR_RS_W = 598; + public static final int MIPS_INS_EXTR_R_W = 599; + public static final int MIPS_INS_EXTR_S_H = 600; + public static final int MIPS_INS_EXTR_W = 601; + public static final int MIPS_INS_EXTS = 602; + public static final int MIPS_INS_EXTS32 = 603; + public static final int MIPS_INS_EXTW = 604; + public static final int MIPS_INS_ABS_D = 605; + public static final int MIPS_INS_ABS_S = 606; + public static final int MIPS_INS_FADD_D = 607; + public static final int MIPS_INS_ADD_D = 608; + public static final int MIPS_INS_ADD_PS = 609; + public static final int MIPS_INS_ADD_S = 610; + public static final int MIPS_INS_FADD_W = 611; + public static final int MIPS_INS_FCAF_D = 612; + public static final int MIPS_INS_FCAF_W = 613; + public static final int MIPS_INS_FCEQ_D = 614; + public static final int MIPS_INS_FCEQ_W = 615; + public static final int MIPS_INS_FCLASS_D = 616; + public static final int MIPS_INS_FCLASS_W = 617; + public static final int MIPS_INS_FCLE_D = 618; + public static final int MIPS_INS_FCLE_W = 619; + public static final int MIPS_INS_FCLT_D = 620; + public static final int MIPS_INS_FCLT_W = 621; + public static final int MIPS_INS_FCNE_D = 622; + public static final int MIPS_INS_FCNE_W = 623; + public static final int MIPS_INS_FCOR_D = 624; + public static final int MIPS_INS_FCOR_W = 625; + public static final int MIPS_INS_FCUEQ_D = 626; + public static final int MIPS_INS_FCUEQ_W = 627; + public static final int MIPS_INS_FCULE_D = 628; + public static final int MIPS_INS_FCULE_W = 629; + public static final int MIPS_INS_FCULT_D = 630; + public static final int MIPS_INS_FCULT_W = 631; + public static final int MIPS_INS_FCUNE_D = 632; + public static final int MIPS_INS_FCUNE_W = 633; + public static final int MIPS_INS_FCUN_D = 634; + public static final int MIPS_INS_FCUN_W = 635; + public static final int MIPS_INS_FDIV_D = 636; + public static final int MIPS_INS_DIV_D = 637; + public static final int MIPS_INS_DIV_S = 638; + public static final int MIPS_INS_FDIV_W = 639; + public static final int MIPS_INS_FEXDO_H = 640; + public static final int MIPS_INS_FEXDO_W = 641; + public static final int MIPS_INS_FEXP2_D = 642; + public static final int MIPS_INS_FEXP2_W = 643; + public static final int MIPS_INS_FEXUPL_D = 644; + public static final int MIPS_INS_FEXUPL_W = 645; + public static final int MIPS_INS_FEXUPR_D = 646; + public static final int MIPS_INS_FEXUPR_W = 647; + public static final int MIPS_INS_FFINT_S_D = 648; + public static final int MIPS_INS_FFINT_S_W = 649; + public static final int MIPS_INS_FFINT_U_D = 650; + public static final int MIPS_INS_FFINT_U_W = 651; + public static final int MIPS_INS_FFQL_D = 652; + public static final int MIPS_INS_FFQL_W = 653; + public static final int MIPS_INS_FFQR_D = 654; + public static final int MIPS_INS_FFQR_W = 655; + public static final int MIPS_INS_FILL_B = 656; + public static final int MIPS_INS_FILL_D = 657; + public static final int MIPS_INS_FILL_H = 658; + public static final int MIPS_INS_FILL_W = 659; + public static final int MIPS_INS_FLOG2_D = 660; + public static final int MIPS_INS_FLOG2_W = 661; + public static final int MIPS_INS_FLOOR_L_D = 662; + public static final int MIPS_INS_FLOOR_L_S = 663; + public static final int MIPS_INS_FLOOR_W_D = 664; + public static final int MIPS_INS_FLOOR_W_S = 665; + public static final int MIPS_INS_FMADD_D = 666; + public static final int MIPS_INS_FMADD_W = 667; + public static final int MIPS_INS_FMAX_A_D = 668; + public static final int MIPS_INS_FMAX_A_W = 669; + public static final int MIPS_INS_FMAX_D = 670; + public static final int MIPS_INS_FMAX_W = 671; + public static final int MIPS_INS_FMIN_A_D = 672; + public static final int MIPS_INS_FMIN_A_W = 673; + public static final int MIPS_INS_FMIN_D = 674; + public static final int MIPS_INS_FMIN_W = 675; + public static final int MIPS_INS_MOV_D = 676; + public static final int MIPS_INS_MOV_S = 677; + public static final int MIPS_INS_FMSUB_D = 678; + public static final int MIPS_INS_FMSUB_W = 679; + public static final int MIPS_INS_FMUL_D = 680; + public static final int MIPS_INS_MUL_D = 681; + public static final int MIPS_INS_MUL_PS = 682; + public static final int MIPS_INS_MUL_S = 683; + public static final int MIPS_INS_FMUL_W = 684; + public static final int MIPS_INS_NEG_D = 685; + public static final int MIPS_INS_NEG_S = 686; + public static final int MIPS_INS_FORK = 687; + public static final int MIPS_INS_FRCP_D = 688; + public static final int MIPS_INS_FRCP_W = 689; + public static final int MIPS_INS_FRINT_D = 690; + public static final int MIPS_INS_FRINT_W = 691; + public static final int MIPS_INS_FRSQRT_D = 692; + public static final int MIPS_INS_FRSQRT_W = 693; + public static final int MIPS_INS_FSAF_D = 694; + public static final int MIPS_INS_FSAF_W = 695; + public static final int MIPS_INS_FSEQ_D = 696; + public static final int MIPS_INS_FSEQ_W = 697; + public static final int MIPS_INS_FSLE_D = 698; + public static final int MIPS_INS_FSLE_W = 699; + public static final int MIPS_INS_FSLT_D = 700; + public static final int MIPS_INS_FSLT_W = 701; + public static final int MIPS_INS_FSNE_D = 702; + public static final int MIPS_INS_FSNE_W = 703; + public static final int MIPS_INS_FSOR_D = 704; + public static final int MIPS_INS_FSOR_W = 705; + public static final int MIPS_INS_FSQRT_D = 706; + public static final int MIPS_INS_SQRT_D = 707; + public static final int MIPS_INS_SQRT_S = 708; + public static final int MIPS_INS_FSQRT_W = 709; + public static final int MIPS_INS_FSUB_D = 710; + public static final int MIPS_INS_SUB_D = 711; + public static final int MIPS_INS_SUB_PS = 712; + public static final int MIPS_INS_SUB_S = 713; + public static final int MIPS_INS_FSUB_W = 714; + public static final int MIPS_INS_FSUEQ_D = 715; + public static final int MIPS_INS_FSUEQ_W = 716; + public static final int MIPS_INS_FSULE_D = 717; + public static final int MIPS_INS_FSULE_W = 718; + public static final int MIPS_INS_FSULT_D = 719; + public static final int MIPS_INS_FSULT_W = 720; + public static final int MIPS_INS_FSUNE_D = 721; + public static final int MIPS_INS_FSUNE_W = 722; + public static final int MIPS_INS_FSUN_D = 723; + public static final int MIPS_INS_FSUN_W = 724; + public static final int MIPS_INS_FTINT_S_D = 725; + public static final int MIPS_INS_FTINT_S_W = 726; + public static final int MIPS_INS_FTINT_U_D = 727; + public static final int MIPS_INS_FTINT_U_W = 728; + public static final int MIPS_INS_FTQ_H = 729; + public static final int MIPS_INS_FTQ_W = 730; + public static final int MIPS_INS_FTRUNC_S_D = 731; + public static final int MIPS_INS_FTRUNC_S_W = 732; + public static final int MIPS_INS_FTRUNC_U_D = 733; + public static final int MIPS_INS_FTRUNC_U_W = 734; + public static final int MIPS_INS_GINVI = 735; + public static final int MIPS_INS_GINVT = 736; + public static final int MIPS_INS_HADD_S_D = 737; + public static final int MIPS_INS_HADD_S_H = 738; + public static final int MIPS_INS_HADD_S_W = 739; + public static final int MIPS_INS_HADD_U_D = 740; + public static final int MIPS_INS_HADD_U_H = 741; + public static final int MIPS_INS_HADD_U_W = 742; + public static final int MIPS_INS_HSUB_S_D = 743; + public static final int MIPS_INS_HSUB_S_H = 744; + public static final int MIPS_INS_HSUB_S_W = 745; + public static final int MIPS_INS_HSUB_U_D = 746; + public static final int MIPS_INS_HSUB_U_H = 747; + public static final int MIPS_INS_HSUB_U_W = 748; + public static final int MIPS_INS_HYPCALL = 749; + public static final int MIPS_INS_ILVEV_B = 750; + public static final int MIPS_INS_ILVEV_D = 751; + public static final int MIPS_INS_ILVEV_H = 752; + public static final int MIPS_INS_ILVEV_W = 753; + public static final int MIPS_INS_ILVL_B = 754; + public static final int MIPS_INS_ILVL_D = 755; + public static final int MIPS_INS_ILVL_H = 756; + public static final int MIPS_INS_ILVL_W = 757; + public static final int MIPS_INS_ILVOD_B = 758; + public static final int MIPS_INS_ILVOD_D = 759; + public static final int MIPS_INS_ILVOD_H = 760; + public static final int MIPS_INS_ILVOD_W = 761; + public static final int MIPS_INS_ILVR_B = 762; + public static final int MIPS_INS_ILVR_D = 763; + public static final int MIPS_INS_ILVR_H = 764; + public static final int MIPS_INS_ILVR_W = 765; + public static final int MIPS_INS_INS = 766; + public static final int MIPS_INS_INSERT_B = 767; + public static final int MIPS_INS_INSERT_D = 768; + public static final int MIPS_INS_INSERT_H = 769; + public static final int MIPS_INS_INSERT_W = 770; + public static final int MIPS_INS_INSV = 771; + public static final int MIPS_INS_INSVE_B = 772; + public static final int MIPS_INS_INSVE_D = 773; + public static final int MIPS_INS_INSVE_H = 774; + public static final int MIPS_INS_INSVE_W = 775; + public static final int MIPS_INS_J = 776; + public static final int MIPS_INS_JALR = 777; + public static final int MIPS_INS_JALRC = 778; + public static final int MIPS_INS_JALRC_HB = 779; + public static final int MIPS_INS_JALRS16 = 780; + public static final int MIPS_INS_JALRS = 781; + public static final int MIPS_INS_JALR_HB = 782; + public static final int MIPS_INS_JALS = 783; + public static final int MIPS_INS_JALX = 784; + public static final int MIPS_INS_JIALC = 785; + public static final int MIPS_INS_JIC = 786; + public static final int MIPS_INS_JR = 787; + public static final int MIPS_INS_JR16 = 788; + public static final int MIPS_INS_JRADDIUSP = 789; + public static final int MIPS_INS_JRC = 790; + public static final int MIPS_INS_JRC16 = 791; + public static final int MIPS_INS_JRCADDIUSP = 792; + public static final int MIPS_INS_JR_HB = 793; + public static final int MIPS_INS_LAPC_H = 794; + public static final int MIPS_INS_LAPC_B = 795; + public static final int MIPS_INS_LB = 796; + public static final int MIPS_INS_LBE = 797; + public static final int MIPS_INS_LBU16 = 798; + public static final int MIPS_INS_LBU = 799; + public static final int MIPS_INS_LBUX = 800; + public static final int MIPS_INS_LBX = 801; + public static final int MIPS_INS_LBUE = 802; + public static final int MIPS_INS_LDC1 = 803; + public static final int MIPS_INS_LDC2 = 804; + public static final int MIPS_INS_LDC3 = 805; + public static final int MIPS_INS_LDI_B = 806; + public static final int MIPS_INS_LDI_D = 807; + public static final int MIPS_INS_LDI_H = 808; + public static final int MIPS_INS_LDI_W = 809; + public static final int MIPS_INS_LDL = 810; + public static final int MIPS_INS_LDPC = 811; + public static final int MIPS_INS_LDR = 812; + public static final int MIPS_INS_LDXC1 = 813; + public static final int MIPS_INS_LD_B = 814; + public static final int MIPS_INS_LD_D = 815; + public static final int MIPS_INS_LD_H = 816; + public static final int MIPS_INS_LD_W = 817; + public static final int MIPS_INS_LH = 818; + public static final int MIPS_INS_LHE = 819; + public static final int MIPS_INS_LHU16 = 820; + public static final int MIPS_INS_LHU = 821; + public static final int MIPS_INS_LHUXS = 822; + public static final int MIPS_INS_LHUX = 823; + public static final int MIPS_INS_LHX = 824; + public static final int MIPS_INS_LHXS = 825; + public static final int MIPS_INS_LHUE = 826; + public static final int MIPS_INS_LI16 = 827; + public static final int MIPS_INS_LL = 828; + public static final int MIPS_INS_LLD = 829; + public static final int MIPS_INS_LLE = 830; + public static final int MIPS_INS_LLWP = 831; + public static final int MIPS_INS_LSA = 832; + public static final int MIPS_INS_LUI = 833; + public static final int MIPS_INS_LUXC1 = 834; + public static final int MIPS_INS_LW = 835; + public static final int MIPS_INS_LW16 = 836; + public static final int MIPS_INS_LWC1 = 837; + public static final int MIPS_INS_LWC2 = 838; + public static final int MIPS_INS_LWC3 = 839; + public static final int MIPS_INS_LWE = 840; + public static final int MIPS_INS_LWL = 841; + public static final int MIPS_INS_LWLE = 842; + public static final int MIPS_INS_LWM16 = 843; + public static final int MIPS_INS_LWM32 = 844; + public static final int MIPS_INS_LWPC = 845; + public static final int MIPS_INS_LWP = 846; + public static final int MIPS_INS_LWR = 847; + public static final int MIPS_INS_LWRE = 848; + public static final int MIPS_INS_LWUPC = 849; + public static final int MIPS_INS_LWU = 850; + public static final int MIPS_INS_LWX = 851; + public static final int MIPS_INS_LWXC1 = 852; + public static final int MIPS_INS_LWXS = 853; + public static final int MIPS_INS_MADD = 854; + public static final int MIPS_INS_MADDF_D = 855; + public static final int MIPS_INS_MADDF_S = 856; + public static final int MIPS_INS_MADDR_Q_H = 857; + public static final int MIPS_INS_MADDR_Q_W = 858; + public static final int MIPS_INS_MADDU = 859; + public static final int MIPS_INS_MADDV_B = 860; + public static final int MIPS_INS_MADDV_D = 861; + public static final int MIPS_INS_MADDV_H = 862; + public static final int MIPS_INS_MADDV_W = 863; + public static final int MIPS_INS_MADD_D = 864; + public static final int MIPS_INS_MADD_Q_H = 865; + public static final int MIPS_INS_MADD_Q_W = 866; + public static final int MIPS_INS_MADD_S = 867; + public static final int MIPS_INS_MAQ_SA_W_PHL = 868; + public static final int MIPS_INS_MAQ_SA_W_PHR = 869; + public static final int MIPS_INS_MAQ_S_W_PHL = 870; + public static final int MIPS_INS_MAQ_S_W_PHR = 871; + public static final int MIPS_INS_MAXA_D = 872; + public static final int MIPS_INS_MAXA_S = 873; + public static final int MIPS_INS_MAXI_S_B = 874; + public static final int MIPS_INS_MAXI_S_D = 875; + public static final int MIPS_INS_MAXI_S_H = 876; + public static final int MIPS_INS_MAXI_S_W = 877; + public static final int MIPS_INS_MAXI_U_B = 878; + public static final int MIPS_INS_MAXI_U_D = 879; + public static final int MIPS_INS_MAXI_U_H = 880; + public static final int MIPS_INS_MAXI_U_W = 881; + public static final int MIPS_INS_MAX_A_B = 882; + public static final int MIPS_INS_MAX_A_D = 883; + public static final int MIPS_INS_MAX_A_H = 884; + public static final int MIPS_INS_MAX_A_W = 885; + public static final int MIPS_INS_MAX_D = 886; + public static final int MIPS_INS_MAX_S = 887; + public static final int MIPS_INS_MAX_S_B = 888; + public static final int MIPS_INS_MAX_S_D = 889; + public static final int MIPS_INS_MAX_S_H = 890; + public static final int MIPS_INS_MAX_S_W = 891; + public static final int MIPS_INS_MAX_U_B = 892; + public static final int MIPS_INS_MAX_U_D = 893; + public static final int MIPS_INS_MAX_U_H = 894; + public static final int MIPS_INS_MAX_U_W = 895; + public static final int MIPS_INS_MFC0 = 896; + public static final int MIPS_INS_MFC1 = 897; + public static final int MIPS_INS_MFC2 = 898; + public static final int MIPS_INS_MFGC0 = 899; + public static final int MIPS_INS_MFHC0 = 900; + public static final int MIPS_INS_MFHC1 = 901; + public static final int MIPS_INS_MFHC2 = 902; + public static final int MIPS_INS_MFHGC0 = 903; + public static final int MIPS_INS_MFHI = 904; + public static final int MIPS_INS_MFHI16 = 905; + public static final int MIPS_INS_MFLO = 906; + public static final int MIPS_INS_MFLO16 = 907; + public static final int MIPS_INS_MFTR = 908; + public static final int MIPS_INS_MINA_D = 909; + public static final int MIPS_INS_MINA_S = 910; + public static final int MIPS_INS_MINI_S_B = 911; + public static final int MIPS_INS_MINI_S_D = 912; + public static final int MIPS_INS_MINI_S_H = 913; + public static final int MIPS_INS_MINI_S_W = 914; + public static final int MIPS_INS_MINI_U_B = 915; + public static final int MIPS_INS_MINI_U_D = 916; + public static final int MIPS_INS_MINI_U_H = 917; + public static final int MIPS_INS_MINI_U_W = 918; + public static final int MIPS_INS_MIN_A_B = 919; + public static final int MIPS_INS_MIN_A_D = 920; + public static final int MIPS_INS_MIN_A_H = 921; + public static final int MIPS_INS_MIN_A_W = 922; + public static final int MIPS_INS_MIN_D = 923; + public static final int MIPS_INS_MIN_S = 924; + public static final int MIPS_INS_MIN_S_B = 925; + public static final int MIPS_INS_MIN_S_D = 926; + public static final int MIPS_INS_MIN_S_H = 927; + public static final int MIPS_INS_MIN_S_W = 928; + public static final int MIPS_INS_MIN_U_B = 929; + public static final int MIPS_INS_MIN_U_D = 930; + public static final int MIPS_INS_MIN_U_H = 931; + public static final int MIPS_INS_MIN_U_W = 932; + public static final int MIPS_INS_MOD = 933; + public static final int MIPS_INS_MODSUB = 934; + public static final int MIPS_INS_MODU = 935; + public static final int MIPS_INS_MOD_S_B = 936; + public static final int MIPS_INS_MOD_S_D = 937; + public static final int MIPS_INS_MOD_S_H = 938; + public static final int MIPS_INS_MOD_S_W = 939; + public static final int MIPS_INS_MOD_U_B = 940; + public static final int MIPS_INS_MOD_U_D = 941; + public static final int MIPS_INS_MOD_U_H = 942; + public static final int MIPS_INS_MOD_U_W = 943; + public static final int MIPS_INS_MOVE = 944; + public static final int MIPS_INS_MOVE16 = 945; + public static final int MIPS_INS_MOVE_BALC = 946; + public static final int MIPS_INS_MOVEP = 947; + public static final int MIPS_INS_MOVE_V = 948; + public static final int MIPS_INS_MOVF_D = 949; + public static final int MIPS_INS_MOVF = 950; + public static final int MIPS_INS_MOVF_S = 951; + public static final int MIPS_INS_MOVN_D = 952; + public static final int MIPS_INS_MOVN = 953; + public static final int MIPS_INS_MOVN_S = 954; + public static final int MIPS_INS_MOVT_D = 955; + public static final int MIPS_INS_MOVT = 956; + public static final int MIPS_INS_MOVT_S = 957; + public static final int MIPS_INS_MOVZ_D = 958; + public static final int MIPS_INS_MOVZ = 959; + public static final int MIPS_INS_MOVZ_S = 960; + public static final int MIPS_INS_MSUB = 961; + public static final int MIPS_INS_MSUBF_D = 962; + public static final int MIPS_INS_MSUBF_S = 963; + public static final int MIPS_INS_MSUBR_Q_H = 964; + public static final int MIPS_INS_MSUBR_Q_W = 965; + public static final int MIPS_INS_MSUBU = 966; + public static final int MIPS_INS_MSUBV_B = 967; + public static final int MIPS_INS_MSUBV_D = 968; + public static final int MIPS_INS_MSUBV_H = 969; + public static final int MIPS_INS_MSUBV_W = 970; + public static final int MIPS_INS_MSUB_D = 971; + public static final int MIPS_INS_MSUB_Q_H = 972; + public static final int MIPS_INS_MSUB_Q_W = 973; + public static final int MIPS_INS_MSUB_S = 974; + public static final int MIPS_INS_MTC0 = 975; + public static final int MIPS_INS_MTC1 = 976; + public static final int MIPS_INS_MTC2 = 977; + public static final int MIPS_INS_MTGC0 = 978; + public static final int MIPS_INS_MTHC0 = 979; + public static final int MIPS_INS_MTHC1 = 980; + public static final int MIPS_INS_MTHC2 = 981; + public static final int MIPS_INS_MTHGC0 = 982; + public static final int MIPS_INS_MTHI = 983; + public static final int MIPS_INS_MTHLIP = 984; + public static final int MIPS_INS_MTLO = 985; + public static final int MIPS_INS_MTM0 = 986; + public static final int MIPS_INS_MTM1 = 987; + public static final int MIPS_INS_MTM2 = 988; + public static final int MIPS_INS_MTP0 = 989; + public static final int MIPS_INS_MTP1 = 990; + public static final int MIPS_INS_MTP2 = 991; + public static final int MIPS_INS_MTTR = 992; + public static final int MIPS_INS_MUH = 993; + public static final int MIPS_INS_MUHU = 994; + public static final int MIPS_INS_MULEQ_S_W_PHL = 995; + public static final int MIPS_INS_MULEQ_S_W_PHR = 996; + public static final int MIPS_INS_MULEU_S_PH_QBL = 997; + public static final int MIPS_INS_MULEU_S_PH_QBR = 998; + public static final int MIPS_INS_MULQ_RS_PH = 999; + public static final int MIPS_INS_MULQ_RS_W = 1000; + public static final int MIPS_INS_MULQ_S_PH = 1001; + public static final int MIPS_INS_MULQ_S_W = 1002; + public static final int MIPS_INS_MULR_PS = 1003; + public static final int MIPS_INS_MULR_Q_H = 1004; + public static final int MIPS_INS_MULR_Q_W = 1005; + public static final int MIPS_INS_MULSAQ_S_W_PH = 1006; + public static final int MIPS_INS_MULSA_W_PH = 1007; + public static final int MIPS_INS_MULT = 1008; + public static final int MIPS_INS_MULTU = 1009; + public static final int MIPS_INS_MULU = 1010; + public static final int MIPS_INS_MULV_B = 1011; + public static final int MIPS_INS_MULV_D = 1012; + public static final int MIPS_INS_MULV_H = 1013; + public static final int MIPS_INS_MULV_W = 1014; + public static final int MIPS_INS_MUL_PH = 1015; + public static final int MIPS_INS_MUL_Q_H = 1016; + public static final int MIPS_INS_MUL_Q_W = 1017; + public static final int MIPS_INS_MUL_S_PH = 1018; + public static final int MIPS_INS_NLOC_B = 1019; + public static final int MIPS_INS_NLOC_D = 1020; + public static final int MIPS_INS_NLOC_H = 1021; + public static final int MIPS_INS_NLOC_W = 1022; + public static final int MIPS_INS_NLZC_B = 1023; + public static final int MIPS_INS_NLZC_D = 1024; + public static final int MIPS_INS_NLZC_H = 1025; + public static final int MIPS_INS_NLZC_W = 1026; + public static final int MIPS_INS_NMADD_D = 1027; + public static final int MIPS_INS_NMADD_S = 1028; + public static final int MIPS_INS_NMSUB_D = 1029; + public static final int MIPS_INS_NMSUB_S = 1030; + public static final int MIPS_INS_NOP32 = 1031; + public static final int MIPS_INS_NOP = 1032; + public static final int MIPS_INS_NORI_B = 1033; + public static final int MIPS_INS_NOR_V = 1034; + public static final int MIPS_INS_NOT16 = 1035; + public static final int MIPS_INS_NOT = 1036; + public static final int MIPS_INS_NEG = 1037; + public static final int MIPS_INS_OR = 1038; + public static final int MIPS_INS_OR16 = 1039; + public static final int MIPS_INS_ORI_B = 1040; + public static final int MIPS_INS_ORI = 1041; + public static final int MIPS_INS_OR_V = 1042; + public static final int MIPS_INS_PACKRL_PH = 1043; + public static final int MIPS_INS_PAUSE = 1044; + public static final int MIPS_INS_PCKEV_B = 1045; + public static final int MIPS_INS_PCKEV_D = 1046; + public static final int MIPS_INS_PCKEV_H = 1047; + public static final int MIPS_INS_PCKEV_W = 1048; + public static final int MIPS_INS_PCKOD_B = 1049; + public static final int MIPS_INS_PCKOD_D = 1050; + public static final int MIPS_INS_PCKOD_H = 1051; + public static final int MIPS_INS_PCKOD_W = 1052; + public static final int MIPS_INS_PCNT_B = 1053; + public static final int MIPS_INS_PCNT_D = 1054; + public static final int MIPS_INS_PCNT_H = 1055; + public static final int MIPS_INS_PCNT_W = 1056; + public static final int MIPS_INS_PICK_PH = 1057; + public static final int MIPS_INS_PICK_QB = 1058; + public static final int MIPS_INS_PLL_PS = 1059; + public static final int MIPS_INS_PLU_PS = 1060; + public static final int MIPS_INS_POP = 1061; + public static final int MIPS_INS_PRECEQU_PH_QBL = 1062; + public static final int MIPS_INS_PRECEQU_PH_QBLA = 1063; + public static final int MIPS_INS_PRECEQU_PH_QBR = 1064; + public static final int MIPS_INS_PRECEQU_PH_QBRA = 1065; + public static final int MIPS_INS_PRECEQ_W_PHL = 1066; + public static final int MIPS_INS_PRECEQ_W_PHR = 1067; + public static final int MIPS_INS_PRECEU_PH_QBL = 1068; + public static final int MIPS_INS_PRECEU_PH_QBLA = 1069; + public static final int MIPS_INS_PRECEU_PH_QBR = 1070; + public static final int MIPS_INS_PRECEU_PH_QBRA = 1071; + public static final int MIPS_INS_PRECRQU_S_QB_PH = 1072; + public static final int MIPS_INS_PRECRQ_PH_W = 1073; + public static final int MIPS_INS_PRECRQ_QB_PH = 1074; + public static final int MIPS_INS_PRECRQ_RS_PH_W = 1075; + public static final int MIPS_INS_PRECR_QB_PH = 1076; + public static final int MIPS_INS_PRECR_SRA_PH_W = 1077; + public static final int MIPS_INS_PRECR_SRA_R_PH_W = 1078; + public static final int MIPS_INS_PREF = 1079; + public static final int MIPS_INS_PREFE = 1080; + public static final int MIPS_INS_PREFX = 1081; + public static final int MIPS_INS_PREPEND = 1082; + public static final int MIPS_INS_PUL_PS = 1083; + public static final int MIPS_INS_PUU_PS = 1084; + public static final int MIPS_INS_RADDU_W_QB = 1085; + public static final int MIPS_INS_RDDSP = 1086; + public static final int MIPS_INS_RDHWR = 1087; + public static final int MIPS_INS_RDPGPR = 1088; + public static final int MIPS_INS_RECIP_D = 1089; + public static final int MIPS_INS_RECIP_S = 1090; + public static final int MIPS_INS_REPLV_PH = 1091; + public static final int MIPS_INS_REPLV_QB = 1092; + public static final int MIPS_INS_REPL_PH = 1093; + public static final int MIPS_INS_REPL_QB = 1094; + public static final int MIPS_INS_RESTORE_JRC = 1095; + public static final int MIPS_INS_RESTORE = 1096; + public static final int MIPS_INS_RINT_D = 1097; + public static final int MIPS_INS_RINT_S = 1098; + public static final int MIPS_INS_ROTR = 1099; + public static final int MIPS_INS_ROTRV = 1100; + public static final int MIPS_INS_ROTX = 1101; + public static final int MIPS_INS_ROUND_L_D = 1102; + public static final int MIPS_INS_ROUND_L_S = 1103; + public static final int MIPS_INS_ROUND_W_D = 1104; + public static final int MIPS_INS_ROUND_W_S = 1105; + public static final int MIPS_INS_RSQRT_D = 1106; + public static final int MIPS_INS_RSQRT_S = 1107; + public static final int MIPS_INS_SAT_S_B = 1108; + public static final int MIPS_INS_SAT_S_D = 1109; + public static final int MIPS_INS_SAT_S_H = 1110; + public static final int MIPS_INS_SAT_S_W = 1111; + public static final int MIPS_INS_SAT_U_B = 1112; + public static final int MIPS_INS_SAT_U_D = 1113; + public static final int MIPS_INS_SAT_U_H = 1114; + public static final int MIPS_INS_SAT_U_W = 1115; + public static final int MIPS_INS_SAVE = 1116; + public static final int MIPS_INS_SB = 1117; + public static final int MIPS_INS_SB16 = 1118; + public static final int MIPS_INS_SBE = 1119; + public static final int MIPS_INS_SBX = 1120; + public static final int MIPS_INS_SC = 1121; + public static final int MIPS_INS_SCD = 1122; + public static final int MIPS_INS_SCE = 1123; + public static final int MIPS_INS_SCWP = 1124; + public static final int MIPS_INS_SDBBP = 1125; + public static final int MIPS_INS_SDBBP16 = 1126; + public static final int MIPS_INS_SDC1 = 1127; + public static final int MIPS_INS_SDC2 = 1128; + public static final int MIPS_INS_SDC3 = 1129; + public static final int MIPS_INS_SDL = 1130; + public static final int MIPS_INS_SDR = 1131; + public static final int MIPS_INS_SDXC1 = 1132; + public static final int MIPS_INS_SEB = 1133; + public static final int MIPS_INS_SEH = 1134; + public static final int MIPS_INS_SELEQZ = 1135; + public static final int MIPS_INS_SELEQZ_D = 1136; + public static final int MIPS_INS_SELEQZ_S = 1137; + public static final int MIPS_INS_SELNEZ = 1138; + public static final int MIPS_INS_SELNEZ_D = 1139; + public static final int MIPS_INS_SELNEZ_S = 1140; + public static final int MIPS_INS_SEL_D = 1141; + public static final int MIPS_INS_SEL_S = 1142; + public static final int MIPS_INS_SEQI = 1143; + public static final int MIPS_INS_SH = 1144; + public static final int MIPS_INS_SH16 = 1145; + public static final int MIPS_INS_SHE = 1146; + public static final int MIPS_INS_SHF_B = 1147; + public static final int MIPS_INS_SHF_H = 1148; + public static final int MIPS_INS_SHF_W = 1149; + public static final int MIPS_INS_SHILO = 1150; + public static final int MIPS_INS_SHILOV = 1151; + public static final int MIPS_INS_SHLLV_PH = 1152; + public static final int MIPS_INS_SHLLV_QB = 1153; + public static final int MIPS_INS_SHLLV_S_PH = 1154; + public static final int MIPS_INS_SHLLV_S_W = 1155; + public static final int MIPS_INS_SHLL_PH = 1156; + public static final int MIPS_INS_SHLL_QB = 1157; + public static final int MIPS_INS_SHLL_S_PH = 1158; + public static final int MIPS_INS_SHLL_S_W = 1159; + public static final int MIPS_INS_SHRAV_PH = 1160; + public static final int MIPS_INS_SHRAV_QB = 1161; + public static final int MIPS_INS_SHRAV_R_PH = 1162; + public static final int MIPS_INS_SHRAV_R_QB = 1163; + public static final int MIPS_INS_SHRAV_R_W = 1164; + public static final int MIPS_INS_SHRA_PH = 1165; + public static final int MIPS_INS_SHRA_QB = 1166; + public static final int MIPS_INS_SHRA_R_PH = 1167; + public static final int MIPS_INS_SHRA_R_QB = 1168; + public static final int MIPS_INS_SHRA_R_W = 1169; + public static final int MIPS_INS_SHRLV_PH = 1170; + public static final int MIPS_INS_SHRLV_QB = 1171; + public static final int MIPS_INS_SHRL_PH = 1172; + public static final int MIPS_INS_SHRL_QB = 1173; + public static final int MIPS_INS_SHXS = 1174; + public static final int MIPS_INS_SHX = 1175; + public static final int MIPS_INS_SIGRIE = 1176; + public static final int MIPS_INS_SLDI_B = 1177; + public static final int MIPS_INS_SLDI_D = 1178; + public static final int MIPS_INS_SLDI_H = 1179; + public static final int MIPS_INS_SLDI_W = 1180; + public static final int MIPS_INS_SLD_B = 1181; + public static final int MIPS_INS_SLD_D = 1182; + public static final int MIPS_INS_SLD_H = 1183; + public static final int MIPS_INS_SLD_W = 1184; + public static final int MIPS_INS_SLL = 1185; + public static final int MIPS_INS_SLL16 = 1186; + public static final int MIPS_INS_SLLI_B = 1187; + public static final int MIPS_INS_SLLI_D = 1188; + public static final int MIPS_INS_SLLI_H = 1189; + public static final int MIPS_INS_SLLI_W = 1190; + public static final int MIPS_INS_SLLV = 1191; + public static final int MIPS_INS_SLL_B = 1192; + public static final int MIPS_INS_SLL_D = 1193; + public static final int MIPS_INS_SLL_H = 1194; + public static final int MIPS_INS_SLL_W = 1195; + public static final int MIPS_INS_SLTIU = 1196; + public static final int MIPS_INS_SLTI = 1197; + public static final int MIPS_INS_SNEI = 1198; + public static final int MIPS_INS_SOV = 1199; + public static final int MIPS_INS_SPLATI_B = 1200; + public static final int MIPS_INS_SPLATI_D = 1201; + public static final int MIPS_INS_SPLATI_H = 1202; + public static final int MIPS_INS_SPLATI_W = 1203; + public static final int MIPS_INS_SPLAT_B = 1204; + public static final int MIPS_INS_SPLAT_D = 1205; + public static final int MIPS_INS_SPLAT_H = 1206; + public static final int MIPS_INS_SPLAT_W = 1207; + public static final int MIPS_INS_SRA = 1208; + public static final int MIPS_INS_SRAI_B = 1209; + public static final int MIPS_INS_SRAI_D = 1210; + public static final int MIPS_INS_SRAI_H = 1211; + public static final int MIPS_INS_SRAI_W = 1212; + public static final int MIPS_INS_SRARI_B = 1213; + public static final int MIPS_INS_SRARI_D = 1214; + public static final int MIPS_INS_SRARI_H = 1215; + public static final int MIPS_INS_SRARI_W = 1216; + public static final int MIPS_INS_SRAR_B = 1217; + public static final int MIPS_INS_SRAR_D = 1218; + public static final int MIPS_INS_SRAR_H = 1219; + public static final int MIPS_INS_SRAR_W = 1220; + public static final int MIPS_INS_SRAV = 1221; + public static final int MIPS_INS_SRA_B = 1222; + public static final int MIPS_INS_SRA_D = 1223; + public static final int MIPS_INS_SRA_H = 1224; + public static final int MIPS_INS_SRA_W = 1225; + public static final int MIPS_INS_SRL = 1226; + public static final int MIPS_INS_SRL16 = 1227; + public static final int MIPS_INS_SRLI_B = 1228; + public static final int MIPS_INS_SRLI_D = 1229; + public static final int MIPS_INS_SRLI_H = 1230; + public static final int MIPS_INS_SRLI_W = 1231; + public static final int MIPS_INS_SRLRI_B = 1232; + public static final int MIPS_INS_SRLRI_D = 1233; + public static final int MIPS_INS_SRLRI_H = 1234; + public static final int MIPS_INS_SRLRI_W = 1235; + public static final int MIPS_INS_SRLR_B = 1236; + public static final int MIPS_INS_SRLR_D = 1237; + public static final int MIPS_INS_SRLR_H = 1238; + public static final int MIPS_INS_SRLR_W = 1239; + public static final int MIPS_INS_SRLV = 1240; + public static final int MIPS_INS_SRL_B = 1241; + public static final int MIPS_INS_SRL_D = 1242; + public static final int MIPS_INS_SRL_H = 1243; + public static final int MIPS_INS_SRL_W = 1244; + public static final int MIPS_INS_SSNOP = 1245; + public static final int MIPS_INS_ST_B = 1246; + public static final int MIPS_INS_ST_D = 1247; + public static final int MIPS_INS_ST_H = 1248; + public static final int MIPS_INS_ST_W = 1249; + public static final int MIPS_INS_SUB = 1250; + public static final int MIPS_INS_SUBQH_PH = 1251; + public static final int MIPS_INS_SUBQH_R_PH = 1252; + public static final int MIPS_INS_SUBQH_R_W = 1253; + public static final int MIPS_INS_SUBQH_W = 1254; + public static final int MIPS_INS_SUBQ_PH = 1255; + public static final int MIPS_INS_SUBQ_S_PH = 1256; + public static final int MIPS_INS_SUBQ_S_W = 1257; + public static final int MIPS_INS_SUBSUS_U_B = 1258; + public static final int MIPS_INS_SUBSUS_U_D = 1259; + public static final int MIPS_INS_SUBSUS_U_H = 1260; + public static final int MIPS_INS_SUBSUS_U_W = 1261; + public static final int MIPS_INS_SUBSUU_S_B = 1262; + public static final int MIPS_INS_SUBSUU_S_D = 1263; + public static final int MIPS_INS_SUBSUU_S_H = 1264; + public static final int MIPS_INS_SUBSUU_S_W = 1265; + public static final int MIPS_INS_SUBS_S_B = 1266; + public static final int MIPS_INS_SUBS_S_D = 1267; + public static final int MIPS_INS_SUBS_S_H = 1268; + public static final int MIPS_INS_SUBS_S_W = 1269; + public static final int MIPS_INS_SUBS_U_B = 1270; + public static final int MIPS_INS_SUBS_U_D = 1271; + public static final int MIPS_INS_SUBS_U_H = 1272; + public static final int MIPS_INS_SUBS_U_W = 1273; + public static final int MIPS_INS_SUBU16 = 1274; + public static final int MIPS_INS_SUBUH_QB = 1275; + public static final int MIPS_INS_SUBUH_R_QB = 1276; + public static final int MIPS_INS_SUBU_PH = 1277; + public static final int MIPS_INS_SUBU_QB = 1278; + public static final int MIPS_INS_SUBU_S_PH = 1279; + public static final int MIPS_INS_SUBU_S_QB = 1280; + public static final int MIPS_INS_SUBVI_B = 1281; + public static final int MIPS_INS_SUBVI_D = 1282; + public static final int MIPS_INS_SUBVI_H = 1283; + public static final int MIPS_INS_SUBVI_W = 1284; + public static final int MIPS_INS_SUBV_B = 1285; + public static final int MIPS_INS_SUBV_D = 1286; + public static final int MIPS_INS_SUBV_H = 1287; + public static final int MIPS_INS_SUBV_W = 1288; + public static final int MIPS_INS_SUXC1 = 1289; + public static final int MIPS_INS_SW = 1290; + public static final int MIPS_INS_SW16 = 1291; + public static final int MIPS_INS_SWC1 = 1292; + public static final int MIPS_INS_SWC2 = 1293; + public static final int MIPS_INS_SWC3 = 1294; + public static final int MIPS_INS_SWE = 1295; + public static final int MIPS_INS_SWL = 1296; + public static final int MIPS_INS_SWLE = 1297; + public static final int MIPS_INS_SWM16 = 1298; + public static final int MIPS_INS_SWM32 = 1299; + public static final int MIPS_INS_SWPC = 1300; + public static final int MIPS_INS_SWP = 1301; + public static final int MIPS_INS_SWR = 1302; + public static final int MIPS_INS_SWRE = 1303; + public static final int MIPS_INS_SWSP = 1304; + public static final int MIPS_INS_SWXC1 = 1305; + public static final int MIPS_INS_SWXS = 1306; + public static final int MIPS_INS_SWX = 1307; + public static final int MIPS_INS_SYNC = 1308; + public static final int MIPS_INS_SYNCI = 1309; + public static final int MIPS_INS_SYSCALL = 1310; + public static final int MIPS_INS_TEQ = 1311; + public static final int MIPS_INS_TEQI = 1312; + public static final int MIPS_INS_TGE = 1313; + public static final int MIPS_INS_TGEI = 1314; + public static final int MIPS_INS_TGEIU = 1315; + public static final int MIPS_INS_TGEU = 1316; + public static final int MIPS_INS_TLBGINV = 1317; + public static final int MIPS_INS_TLBGINVF = 1318; + public static final int MIPS_INS_TLBGP = 1319; + public static final int MIPS_INS_TLBGR = 1320; + public static final int MIPS_INS_TLBGWI = 1321; + public static final int MIPS_INS_TLBGWR = 1322; + public static final int MIPS_INS_TLBINV = 1323; + public static final int MIPS_INS_TLBINVF = 1324; + public static final int MIPS_INS_TLBP = 1325; + public static final int MIPS_INS_TLBR = 1326; + public static final int MIPS_INS_TLBWI = 1327; + public static final int MIPS_INS_TLBWR = 1328; + public static final int MIPS_INS_TLT = 1329; + public static final int MIPS_INS_TLTI = 1330; + public static final int MIPS_INS_TLTIU = 1331; + public static final int MIPS_INS_TLTU = 1332; + public static final int MIPS_INS_TNE = 1333; + public static final int MIPS_INS_TNEI = 1334; + public static final int MIPS_INS_TRUNC_L_D = 1335; + public static final int MIPS_INS_TRUNC_L_S = 1336; + public static final int MIPS_INS_UALH = 1337; + public static final int MIPS_INS_UALWM = 1338; + public static final int MIPS_INS_UALW = 1339; + public static final int MIPS_INS_UASH = 1340; + public static final int MIPS_INS_UASWM = 1341; + public static final int MIPS_INS_UASW = 1342; + public static final int MIPS_INS_V3MULU = 1343; + public static final int MIPS_INS_VMM0 = 1344; + public static final int MIPS_INS_VMULU = 1345; + public static final int MIPS_INS_VSHF_B = 1346; + public static final int MIPS_INS_VSHF_D = 1347; + public static final int MIPS_INS_VSHF_H = 1348; + public static final int MIPS_INS_VSHF_W = 1349; + public static final int MIPS_INS_WAIT = 1350; + public static final int MIPS_INS_WRDSP = 1351; + public static final int MIPS_INS_WRPGPR = 1352; + public static final int MIPS_INS_WSBH = 1353; + public static final int MIPS_INS_XOR = 1354; + public static final int MIPS_INS_XOR16 = 1355; + public static final int MIPS_INS_XORI_B = 1356; + public static final int MIPS_INS_XORI = 1357; + public static final int MIPS_INS_XOR_V = 1358; + public static final int MIPS_INS_YIELD = 1359; + public static final int MIPS_INS_ENDING = 1360; + public static final int MIPS_INS_ALIAS_BEGIN = 1361; + public static final int MIPS_INS_ALIAS_ADDIU_B32 = 1362; + public static final int MIPS_INS_ALIAS_BITREVB = 1363; + public static final int MIPS_INS_ALIAS_BITREVH = 1364; + public static final int MIPS_INS_ALIAS_BYTEREVH = 1365; + public static final int MIPS_INS_ALIAS_NOT = 1366; + public static final int MIPS_INS_ALIAS_RESTORE_JRC = 1367; + public static final int MIPS_INS_ALIAS_RESTORE = 1368; + public static final int MIPS_INS_ALIAS_SAVE = 1369; + public static final int MIPS_INS_ALIAS_MOVE = 1370; + public static final int MIPS_INS_ALIAS_BAL = 1371; + public static final int MIPS_INS_ALIAS_JALR_HB = 1372; + public static final int MIPS_INS_ALIAS_NEG = 1373; + public static final int MIPS_INS_ALIAS_NEGU = 1374; + public static final int MIPS_INS_ALIAS_NOP = 1375; + public static final int MIPS_INS_ALIAS_BNEZL = 1376; + public static final int MIPS_INS_ALIAS_BEQZL = 1377; + public static final int MIPS_INS_ALIAS_SYSCALL = 1378; + public static final int MIPS_INS_ALIAS_BREAK = 1379; + public static final int MIPS_INS_ALIAS_EI = 1380; + public static final int MIPS_INS_ALIAS_DI = 1381; + public static final int MIPS_INS_ALIAS_TEQ = 1382; + public static final int MIPS_INS_ALIAS_TGE = 1383; + public static final int MIPS_INS_ALIAS_TGEU = 1384; + public static final int MIPS_INS_ALIAS_TLT = 1385; + public static final int MIPS_INS_ALIAS_TLTU = 1386; + public static final int MIPS_INS_ALIAS_TNE = 1387; + public static final int MIPS_INS_ALIAS_RDHWR = 1388; + public static final int MIPS_INS_ALIAS_SDBBP = 1389; + public static final int MIPS_INS_ALIAS_SYNC = 1390; + public static final int MIPS_INS_ALIAS_HYPCALL = 1391; + public static final int MIPS_INS_ALIAS_NOR = 1392; + public static final int MIPS_INS_ALIAS_C_F_S = 1393; + public static final int MIPS_INS_ALIAS_C_UN_S = 1394; + public static final int MIPS_INS_ALIAS_C_EQ_S = 1395; + public static final int MIPS_INS_ALIAS_C_UEQ_S = 1396; + public static final int MIPS_INS_ALIAS_C_OLT_S = 1397; + public static final int MIPS_INS_ALIAS_C_ULT_S = 1398; + public static final int MIPS_INS_ALIAS_C_OLE_S = 1399; + public static final int MIPS_INS_ALIAS_C_ULE_S = 1400; + public static final int MIPS_INS_ALIAS_C_SF_S = 1401; + public static final int MIPS_INS_ALIAS_C_NGLE_S = 1402; + public static final int MIPS_INS_ALIAS_C_SEQ_S = 1403; + public static final int MIPS_INS_ALIAS_C_NGL_S = 1404; + public static final int MIPS_INS_ALIAS_C_LT_S = 1405; + public static final int MIPS_INS_ALIAS_C_NGE_S = 1406; + public static final int MIPS_INS_ALIAS_C_LE_S = 1407; + public static final int MIPS_INS_ALIAS_C_NGT_S = 1408; + public static final int MIPS_INS_ALIAS_BC1T = 1409; + public static final int MIPS_INS_ALIAS_BC1F = 1410; + public static final int MIPS_INS_ALIAS_C_F_D = 1411; + public static final int MIPS_INS_ALIAS_C_UN_D = 1412; + public static final int MIPS_INS_ALIAS_C_EQ_D = 1413; + public static final int MIPS_INS_ALIAS_C_UEQ_D = 1414; + public static final int MIPS_INS_ALIAS_C_OLT_D = 1415; + public static final int MIPS_INS_ALIAS_C_ULT_D = 1416; + public static final int MIPS_INS_ALIAS_C_OLE_D = 1417; + public static final int MIPS_INS_ALIAS_C_ULE_D = 1418; + public static final int MIPS_INS_ALIAS_C_SF_D = 1419; + public static final int MIPS_INS_ALIAS_C_NGLE_D = 1420; + public static final int MIPS_INS_ALIAS_C_SEQ_D = 1421; + public static final int MIPS_INS_ALIAS_C_NGL_D = 1422; + public static final int MIPS_INS_ALIAS_C_LT_D = 1423; + public static final int MIPS_INS_ALIAS_C_NGE_D = 1424; + public static final int MIPS_INS_ALIAS_C_LE_D = 1425; + public static final int MIPS_INS_ALIAS_C_NGT_D = 1426; + public static final int MIPS_INS_ALIAS_BC1TL = 1427; + public static final int MIPS_INS_ALIAS_BC1FL = 1428; + public static final int MIPS_INS_ALIAS_DNEG = 1429; + public static final int MIPS_INS_ALIAS_DNEGU = 1430; + public static final int MIPS_INS_ALIAS_SLT = 1431; + public static final int MIPS_INS_ALIAS_SLTU = 1432; + public static final int MIPS_INS_ALIAS_SIGRIE = 1433; + public static final int MIPS_INS_ALIAS_JR = 1434; + public static final int MIPS_INS_ALIAS_JRC = 1435; + public static final int MIPS_INS_ALIAS_JALRC = 1436; + public static final int MIPS_INS_ALIAS_DIV = 1437; + public static final int MIPS_INS_ALIAS_DIVU = 1438; + public static final int MIPS_INS_ALIAS_LAPC = 1439; + public static final int MIPS_INS_ALIAS_WRDSP = 1440; + public static final int MIPS_INS_ALIAS_WAIT = 1441; + public static final int MIPS_INS_ALIAS_SW = 1442; + public static final int MIPS_INS_ALIAS_JALRC_HB = 1443; + public static final int MIPS_INS_ALIAS_ADDIU_B = 1444; + public static final int MIPS_INS_ALIAS_ADDIU_W = 1445; + public static final int MIPS_INS_ALIAS_JRC_HB = 1446; + public static final int MIPS_INS_ALIAS_BEQC = 1447; + public static final int MIPS_INS_ALIAS_BNEC = 1448; + public static final int MIPS_INS_ALIAS_BEQZC = 1449; + public static final int MIPS_INS_ALIAS_BNEZC = 1450; + public static final int MIPS_INS_ALIAS_MFC0 = 1451; + public static final int MIPS_INS_ALIAS_MFHC0 = 1452; + public static final int MIPS_INS_ALIAS_MTC0 = 1453; + public static final int MIPS_INS_ALIAS_MTHC0 = 1454; + public static final int MIPS_INS_ALIAS_DMT = 1455; + public static final int MIPS_INS_ALIAS_EMT = 1456; + public static final int MIPS_INS_ALIAS_DVPE = 1457; + public static final int MIPS_INS_ALIAS_EVPE = 1458; + public static final int MIPS_INS_ALIAS_YIELD = 1459; + public static final int MIPS_INS_ALIAS_MFTC0 = 1460; + public static final int MIPS_INS_ALIAS_MFTLO = 1461; + public static final int MIPS_INS_ALIAS_MFTHI = 1462; + public static final int MIPS_INS_ALIAS_MFTACX = 1463; + public static final int MIPS_INS_ALIAS_MTTC0 = 1464; + public static final int MIPS_INS_ALIAS_MTTLO = 1465; + public static final int MIPS_INS_ALIAS_MTTHI = 1466; + public static final int MIPS_INS_ALIAS_MTTACX = 1467; + public static final int MIPS_INS_ALIAS_END = 1468; public static final int MIPS_GRP_INVALID = 0; public static final int MIPS_GRP_JUMP = 1; @@ -828,38 +2123,61 @@ public class Mips_const { public static final int MIPS_GRP_IRET = 5; public static final int MIPS_GRP_PRIVILEGE = 6; public static final int MIPS_GRP_BRANCH_RELATIVE = 7; - public static final int MIPS_GRP_BITCOUNT = 128; - public static final int MIPS_GRP_DSP = 129; - public static final int MIPS_GRP_DSPR2 = 130; - public static final int MIPS_GRP_FPIDX = 131; - public static final int MIPS_GRP_MSA = 132; - public static final int MIPS_GRP_MIPS32R2 = 133; - public static final int MIPS_GRP_MIPS64 = 134; - public static final int MIPS_GRP_MIPS64R2 = 135; - public static final int MIPS_GRP_SEINREG = 136; - public static final int MIPS_GRP_STDENC = 137; - public static final int MIPS_GRP_SWAP = 138; - public static final int MIPS_GRP_MICROMIPS = 139; - public static final int MIPS_GRP_MIPS16MODE = 140; - public static final int MIPS_GRP_FP64BIT = 141; - public static final int MIPS_GRP_NONANSFPMATH = 142; - public static final int MIPS_GRP_NOTFP64BIT = 143; - public static final int MIPS_GRP_NOTINMICROMIPS = 144; - public static final int MIPS_GRP_NOTNACL = 145; - public static final int MIPS_GRP_NOTMIPS32R6 = 146; - public static final int MIPS_GRP_NOTMIPS64R6 = 147; - public static final int MIPS_GRP_CNMIPS = 148; - public static final int MIPS_GRP_MIPS32 = 149; - public static final int MIPS_GRP_MIPS32R6 = 150; - public static final int MIPS_GRP_MIPS64R6 = 151; - public static final int MIPS_GRP_MIPS2 = 152; - public static final int MIPS_GRP_MIPS3 = 153; - public static final int MIPS_GRP_MIPS3_32 = 154; - public static final int MIPS_GRP_MIPS3_32R2 = 155; - public static final int MIPS_GRP_MIPS4_32 = 156; - public static final int MIPS_GRP_MIPS4_32R2 = 157; - public static final int MIPS_GRP_MIPS5_32R2 = 158; - public static final int MIPS_GRP_GP32BIT = 159; - public static final int MIPS_GRP_GP64BIT = 160; - public static final int MIPS_GRP_ENDING = 161; + public static final int MIPS_FEATURE_HASMIPS2 = 128; + public static final int MIPS_FEATURE_HASMIPS3_32 = 129; + public static final int MIPS_FEATURE_HASMIPS3_32R2 = 130; + public static final int MIPS_FEATURE_HASMIPS3 = 131; + public static final int MIPS_FEATURE_NOTMIPS3 = 132; + public static final int MIPS_FEATURE_HASMIPS4_32 = 133; + public static final int MIPS_FEATURE_NOTMIPS4_32 = 134; + public static final int MIPS_FEATURE_HASMIPS4_32R2 = 135; + public static final int MIPS_FEATURE_HASMIPS5_32R2 = 136; + public static final int MIPS_FEATURE_HASMIPS32 = 137; + public static final int MIPS_FEATURE_HASMIPS32R2 = 138; + public static final int MIPS_FEATURE_HASMIPS32R5 = 139; + public static final int MIPS_FEATURE_HASMIPS32R6 = 140; + public static final int MIPS_FEATURE_NOTMIPS32R6 = 141; + public static final int MIPS_FEATURE_HASNANOMIPS = 142; + public static final int MIPS_FEATURE_NOTNANOMIPS = 143; + public static final int MIPS_FEATURE_ISGP64BIT = 144; + public static final int MIPS_FEATURE_ISGP32BIT = 145; + public static final int MIPS_FEATURE_ISPTR64BIT = 146; + public static final int MIPS_FEATURE_ISPTR32BIT = 147; + public static final int MIPS_FEATURE_HASMIPS64 = 148; + public static final int MIPS_FEATURE_NOTMIPS64 = 149; + public static final int MIPS_FEATURE_HASMIPS64R2 = 150; + public static final int MIPS_FEATURE_HASMIPS64R5 = 151; + public static final int MIPS_FEATURE_HASMIPS64R6 = 152; + public static final int MIPS_FEATURE_NOTMIPS64R6 = 153; + public static final int MIPS_FEATURE_INMIPS16MODE = 154; + public static final int MIPS_FEATURE_NOTINMIPS16MODE = 155; + public static final int MIPS_FEATURE_HASCNMIPS = 156; + public static final int MIPS_FEATURE_NOTCNMIPS = 157; + public static final int MIPS_FEATURE_HASCNMIPSP = 158; + public static final int MIPS_FEATURE_NOTCNMIPSP = 159; + public static final int MIPS_FEATURE_ISSYM32 = 160; + public static final int MIPS_FEATURE_ISSYM64 = 161; + public static final int MIPS_FEATURE_HASSTDENC = 162; + public static final int MIPS_FEATURE_INMICROMIPS = 163; + public static final int MIPS_FEATURE_NOTINMICROMIPS = 164; + public static final int MIPS_FEATURE_HASEVA = 165; + public static final int MIPS_FEATURE_HASMSA = 166; + public static final int MIPS_FEATURE_HASMADD4 = 167; + public static final int MIPS_FEATURE_HASMT = 168; + public static final int MIPS_FEATURE_USEINDIRECTJUMPSHAZARD = 169; + public static final int MIPS_FEATURE_NOINDIRECTJUMPGUARDS = 170; + public static final int MIPS_FEATURE_HASCRC = 171; + public static final int MIPS_FEATURE_HASVIRT = 172; + public static final int MIPS_FEATURE_HASGINV = 173; + public static final int MIPS_FEATURE_HASTLB = 174; + public static final int MIPS_FEATURE_ISFP64BIT = 175; + public static final int MIPS_FEATURE_NOTFP64BIT = 176; + public static final int MIPS_FEATURE_ISSINGLEFLOAT = 177; + public static final int MIPS_FEATURE_ISNOTSINGLEFLOAT = 178; + public static final int MIPS_FEATURE_ISNOTSOFTFLOAT = 179; + public static final int MIPS_FEATURE_HASMIPS3D = 180; + public static final int MIPS_FEATURE_HASDSP = 181; + public static final int MIPS_FEATURE_HASDSPR2 = 182; + public static final int MIPS_FEATURE_HASDSPR3 = 183; + public static final int MIPS_GRP_ENDING = 184; } \ No newline at end of file diff --git a/bindings/ocaml/mips_const.ml b/bindings/ocaml/mips_const.ml index e0b581be66..fed8ff15b7 100644 --- a/bindings/ocaml/mips_const.ml +++ b/bindings/ocaml/mips_const.ml @@ -6,816 +6,2111 @@ let _MIPS_OP_IMM = 2;; let _MIPS_OP_MEM = 3;; let _MIPS_REG_INVALID = 0;; -let _MIPS_REG_PC = 1;; -let _MIPS_REG_0 = 2;; -let _MIPS_REG_1 = 3;; -let _MIPS_REG_2 = 4;; -let _MIPS_REG_3 = 5;; -let _MIPS_REG_4 = 6;; -let _MIPS_REG_5 = 7;; -let _MIPS_REG_6 = 8;; -let _MIPS_REG_7 = 9;; -let _MIPS_REG_8 = 10;; -let _MIPS_REG_9 = 11;; -let _MIPS_REG_10 = 12;; -let _MIPS_REG_11 = 13;; -let _MIPS_REG_12 = 14;; -let _MIPS_REG_13 = 15;; -let _MIPS_REG_14 = 16;; -let _MIPS_REG_15 = 17;; -let _MIPS_REG_16 = 18;; -let _MIPS_REG_17 = 19;; -let _MIPS_REG_18 = 20;; -let _MIPS_REG_19 = 21;; -let _MIPS_REG_20 = 22;; -let _MIPS_REG_21 = 23;; -let _MIPS_REG_22 = 24;; -let _MIPS_REG_23 = 25;; -let _MIPS_REG_24 = 26;; -let _MIPS_REG_25 = 27;; -let _MIPS_REG_26 = 28;; -let _MIPS_REG_27 = 29;; -let _MIPS_REG_28 = 30;; -let _MIPS_REG_29 = 31;; -let _MIPS_REG_30 = 32;; -let _MIPS_REG_31 = 33;; -let _MIPS_REG_DSPCCOND = 34;; -let _MIPS_REG_DSPCARRY = 35;; -let _MIPS_REG_DSPEFI = 36;; -let _MIPS_REG_DSPOUTFLAG = 37;; -let _MIPS_REG_DSPOUTFLAG16_19 = 38;; -let _MIPS_REG_DSPOUTFLAG20 = 39;; -let _MIPS_REG_DSPOUTFLAG21 = 40;; -let _MIPS_REG_DSPOUTFLAG22 = 41;; -let _MIPS_REG_DSPOUTFLAG23 = 42;; -let _MIPS_REG_DSPPOS = 43;; -let _MIPS_REG_DSPSCOUNT = 44;; -let _MIPS_REG_AC0 = 45;; -let _MIPS_REG_AC1 = 46;; -let _MIPS_REG_AC2 = 47;; -let _MIPS_REG_AC3 = 48;; -let _MIPS_REG_CC0 = 49;; -let _MIPS_REG_CC1 = 50;; -let _MIPS_REG_CC2 = 51;; -let _MIPS_REG_CC3 = 52;; -let _MIPS_REG_CC4 = 53;; -let _MIPS_REG_CC5 = 54;; -let _MIPS_REG_CC6 = 55;; -let _MIPS_REG_CC7 = 56;; -let _MIPS_REG_F0 = 57;; -let _MIPS_REG_F1 = 58;; -let _MIPS_REG_F2 = 59;; -let _MIPS_REG_F3 = 60;; -let _MIPS_REG_F4 = 61;; -let _MIPS_REG_F5 = 62;; -let _MIPS_REG_F6 = 63;; -let _MIPS_REG_F7 = 64;; -let _MIPS_REG_F8 = 65;; -let _MIPS_REG_F9 = 66;; -let _MIPS_REG_F10 = 67;; -let _MIPS_REG_F11 = 68;; -let _MIPS_REG_F12 = 69;; -let _MIPS_REG_F13 = 70;; -let _MIPS_REG_F14 = 71;; -let _MIPS_REG_F15 = 72;; -let _MIPS_REG_F16 = 73;; -let _MIPS_REG_F17 = 74;; -let _MIPS_REG_F18 = 75;; -let _MIPS_REG_F19 = 76;; -let _MIPS_REG_F20 = 77;; -let _MIPS_REG_F21 = 78;; -let _MIPS_REG_F22 = 79;; -let _MIPS_REG_F23 = 80;; -let _MIPS_REG_F24 = 81;; -let _MIPS_REG_F25 = 82;; -let _MIPS_REG_F26 = 83;; -let _MIPS_REG_F27 = 84;; -let _MIPS_REG_F28 = 85;; -let _MIPS_REG_F29 = 86;; -let _MIPS_REG_F30 = 87;; -let _MIPS_REG_F31 = 88;; -let _MIPS_REG_FCC0 = 89;; -let _MIPS_REG_FCC1 = 90;; -let _MIPS_REG_FCC2 = 91;; -let _MIPS_REG_FCC3 = 92;; -let _MIPS_REG_FCC4 = 93;; -let _MIPS_REG_FCC5 = 94;; -let _MIPS_REG_FCC6 = 95;; -let _MIPS_REG_FCC7 = 96;; -let _MIPS_REG_W0 = 97;; -let _MIPS_REG_W1 = 98;; -let _MIPS_REG_W2 = 99;; -let _MIPS_REG_W3 = 100;; -let _MIPS_REG_W4 = 101;; -let _MIPS_REG_W5 = 102;; -let _MIPS_REG_W6 = 103;; -let _MIPS_REG_W7 = 104;; -let _MIPS_REG_W8 = 105;; -let _MIPS_REG_W9 = 106;; -let _MIPS_REG_W10 = 107;; -let _MIPS_REG_W11 = 108;; -let _MIPS_REG_W12 = 109;; -let _MIPS_REG_W13 = 110;; -let _MIPS_REG_W14 = 111;; -let _MIPS_REG_W15 = 112;; -let _MIPS_REG_W16 = 113;; -let _MIPS_REG_W17 = 114;; -let _MIPS_REG_W18 = 115;; -let _MIPS_REG_W19 = 116;; -let _MIPS_REG_W20 = 117;; -let _MIPS_REG_W21 = 118;; -let _MIPS_REG_W22 = 119;; -let _MIPS_REG_W23 = 120;; -let _MIPS_REG_W24 = 121;; -let _MIPS_REG_W25 = 122;; -let _MIPS_REG_W26 = 123;; -let _MIPS_REG_W27 = 124;; -let _MIPS_REG_W28 = 125;; -let _MIPS_REG_W29 = 126;; -let _MIPS_REG_W30 = 127;; -let _MIPS_REG_W31 = 128;; -let _MIPS_REG_HI = 129;; -let _MIPS_REG_LO = 130;; -let _MIPS_REG_P0 = 131;; -let _MIPS_REG_P1 = 132;; -let _MIPS_REG_P2 = 133;; -let _MIPS_REG_MPL0 = 134;; -let _MIPS_REG_MPL1 = 135;; -let _MIPS_REG_MPL2 = 136;; -let _MIPS_REG_ENDING = 137;; -let _MIPS_REG_ZERO = _MIPS_REG_0;; -let _MIPS_REG_AT = _MIPS_REG_1;; -let _MIPS_REG_V0 = _MIPS_REG_2;; -let _MIPS_REG_V1 = _MIPS_REG_3;; -let _MIPS_REG_A0 = _MIPS_REG_4;; -let _MIPS_REG_A1 = _MIPS_REG_5;; -let _MIPS_REG_A2 = _MIPS_REG_6;; -let _MIPS_REG_A3 = _MIPS_REG_7;; -let _MIPS_REG_T0 = _MIPS_REG_8;; -let _MIPS_REG_T1 = _MIPS_REG_9;; -let _MIPS_REG_T2 = _MIPS_REG_10;; -let _MIPS_REG_T3 = _MIPS_REG_11;; -let _MIPS_REG_T4 = _MIPS_REG_12;; -let _MIPS_REG_T5 = _MIPS_REG_13;; -let _MIPS_REG_T6 = _MIPS_REG_14;; -let _MIPS_REG_T7 = _MIPS_REG_15;; -let _MIPS_REG_S0 = _MIPS_REG_16;; -let _MIPS_REG_S1 = _MIPS_REG_17;; -let _MIPS_REG_S2 = _MIPS_REG_18;; -let _MIPS_REG_S3 = _MIPS_REG_19;; -let _MIPS_REG_S4 = _MIPS_REG_20;; -let _MIPS_REG_S5 = _MIPS_REG_21;; -let _MIPS_REG_S6 = _MIPS_REG_22;; -let _MIPS_REG_S7 = _MIPS_REG_23;; -let _MIPS_REG_T8 = _MIPS_REG_24;; -let _MIPS_REG_T9 = _MIPS_REG_25;; -let _MIPS_REG_K0 = _MIPS_REG_26;; -let _MIPS_REG_K1 = _MIPS_REG_27;; -let _MIPS_REG_GP = _MIPS_REG_28;; -let _MIPS_REG_SP = _MIPS_REG_29;; -let _MIPS_REG_FP = _MIPS_REG_30;; -let _MIPS_REG_S8 = _MIPS_REG_30;; -let _MIPS_REG_RA = _MIPS_REG_31;; -let _MIPS_REG_HI0 = _MIPS_REG_AC0;; -let _MIPS_REG_HI1 = _MIPS_REG_AC1;; -let _MIPS_REG_HI2 = _MIPS_REG_AC2;; -let _MIPS_REG_HI3 = _MIPS_REG_AC3;; -let _MIPS_REG_LO0 = _MIPS_REG_HI0;; -let _MIPS_REG_LO1 = _MIPS_REG_HI1;; -let _MIPS_REG_LO2 = _MIPS_REG_HI2;; -let _MIPS_REG_LO3 = _MIPS_REG_HI3;; +let _MIPS_REG_AT = 1;; +let _MIPS_REG_AT_NM = 2;; +let _MIPS_REG_DSPCCOND = 3;; +let _MIPS_REG_DSPCARRY = 4;; +let _MIPS_REG_DSPEFI = 5;; +let _MIPS_REG_DSPOUTFLAG = 6;; +let _MIPS_REG_DSPPOS = 7;; +let _MIPS_REG_DSPSCOUNT = 8;; +let _MIPS_REG_FP = 9;; +let _MIPS_REG_FP_NM = 10;; +let _MIPS_REG_GP = 11;; +let _MIPS_REG_GP_NM = 12;; +let _MIPS_REG_MSAACCESS = 13;; +let _MIPS_REG_MSACSR = 14;; +let _MIPS_REG_MSAIR = 15;; +let _MIPS_REG_MSAMAP = 16;; +let _MIPS_REG_MSAMODIFY = 17;; +let _MIPS_REG_MSAREQUEST = 18;; +let _MIPS_REG_MSASAVE = 19;; +let _MIPS_REG_MSAUNMAP = 20;; +let _MIPS_REG_PC = 21;; +let _MIPS_REG_RA = 22;; +let _MIPS_REG_RA_NM = 23;; +let _MIPS_REG_SP = 24;; +let _MIPS_REG_SP_NM = 25;; +let _MIPS_REG_ZERO = 26;; +let _MIPS_REG_ZERO_NM = 27;; +let _MIPS_REG_A0 = 28;; +let _MIPS_REG_A1 = 29;; +let _MIPS_REG_A2 = 30;; +let _MIPS_REG_A3 = 31;; +let _MIPS_REG_AC0 = 32;; +let _MIPS_REG_AC1 = 33;; +let _MIPS_REG_AC2 = 34;; +let _MIPS_REG_AC3 = 35;; +let _MIPS_REG_AT_64 = 36;; +let _MIPS_REG_COP00 = 37;; +let _MIPS_REG_COP01 = 38;; +let _MIPS_REG_COP02 = 39;; +let _MIPS_REG_COP03 = 40;; +let _MIPS_REG_COP04 = 41;; +let _MIPS_REG_COP05 = 42;; +let _MIPS_REG_COP06 = 43;; +let _MIPS_REG_COP07 = 44;; +let _MIPS_REG_COP08 = 45;; +let _MIPS_REG_COP09 = 46;; +let _MIPS_REG_COP20 = 47;; +let _MIPS_REG_COP21 = 48;; +let _MIPS_REG_COP22 = 49;; +let _MIPS_REG_COP23 = 50;; +let _MIPS_REG_COP24 = 51;; +let _MIPS_REG_COP25 = 52;; +let _MIPS_REG_COP26 = 53;; +let _MIPS_REG_COP27 = 54;; +let _MIPS_REG_COP28 = 55;; +let _MIPS_REG_COP29 = 56;; +let _MIPS_REG_COP30 = 57;; +let _MIPS_REG_COP31 = 58;; +let _MIPS_REG_COP32 = 59;; +let _MIPS_REG_COP33 = 60;; +let _MIPS_REG_COP34 = 61;; +let _MIPS_REG_COP35 = 62;; +let _MIPS_REG_COP36 = 63;; +let _MIPS_REG_COP37 = 64;; +let _MIPS_REG_COP38 = 65;; +let _MIPS_REG_COP39 = 66;; +let _MIPS_REG_COP010 = 67;; +let _MIPS_REG_COP011 = 68;; +let _MIPS_REG_COP012 = 69;; +let _MIPS_REG_COP013 = 70;; +let _MIPS_REG_COP014 = 71;; +let _MIPS_REG_COP015 = 72;; +let _MIPS_REG_COP016 = 73;; +let _MIPS_REG_COP017 = 74;; +let _MIPS_REG_COP018 = 75;; +let _MIPS_REG_COP019 = 76;; +let _MIPS_REG_COP020 = 77;; +let _MIPS_REG_COP021 = 78;; +let _MIPS_REG_COP022 = 79;; +let _MIPS_REG_COP023 = 80;; +let _MIPS_REG_COP024 = 81;; +let _MIPS_REG_COP025 = 82;; +let _MIPS_REG_COP026 = 83;; +let _MIPS_REG_COP027 = 84;; +let _MIPS_REG_COP028 = 85;; +let _MIPS_REG_COP029 = 86;; +let _MIPS_REG_COP030 = 87;; +let _MIPS_REG_COP031 = 88;; +let _MIPS_REG_COP210 = 89;; +let _MIPS_REG_COP211 = 90;; +let _MIPS_REG_COP212 = 91;; +let _MIPS_REG_COP213 = 92;; +let _MIPS_REG_COP214 = 93;; +let _MIPS_REG_COP215 = 94;; +let _MIPS_REG_COP216 = 95;; +let _MIPS_REG_COP217 = 96;; +let _MIPS_REG_COP218 = 97;; +let _MIPS_REG_COP219 = 98;; +let _MIPS_REG_COP220 = 99;; +let _MIPS_REG_COP221 = 100;; +let _MIPS_REG_COP222 = 101;; +let _MIPS_REG_COP223 = 102;; +let _MIPS_REG_COP224 = 103;; +let _MIPS_REG_COP225 = 104;; +let _MIPS_REG_COP226 = 105;; +let _MIPS_REG_COP227 = 106;; +let _MIPS_REG_COP228 = 107;; +let _MIPS_REG_COP229 = 108;; +let _MIPS_REG_COP230 = 109;; +let _MIPS_REG_COP231 = 110;; +let _MIPS_REG_COP310 = 111;; +let _MIPS_REG_COP311 = 112;; +let _MIPS_REG_COP312 = 113;; +let _MIPS_REG_COP313 = 114;; +let _MIPS_REG_COP314 = 115;; +let _MIPS_REG_COP315 = 116;; +let _MIPS_REG_COP316 = 117;; +let _MIPS_REG_COP317 = 118;; +let _MIPS_REG_COP318 = 119;; +let _MIPS_REG_COP319 = 120;; +let _MIPS_REG_COP320 = 121;; +let _MIPS_REG_COP321 = 122;; +let _MIPS_REG_COP322 = 123;; +let _MIPS_REG_COP323 = 124;; +let _MIPS_REG_COP324 = 125;; +let _MIPS_REG_COP325 = 126;; +let _MIPS_REG_COP326 = 127;; +let _MIPS_REG_COP327 = 128;; +let _MIPS_REG_COP328 = 129;; +let _MIPS_REG_COP329 = 130;; +let _MIPS_REG_COP330 = 131;; +let _MIPS_REG_COP331 = 132;; +let _MIPS_REG_D0 = 133;; +let _MIPS_REG_D1 = 134;; +let _MIPS_REG_D2 = 135;; +let _MIPS_REG_D3 = 136;; +let _MIPS_REG_D4 = 137;; +let _MIPS_REG_D5 = 138;; +let _MIPS_REG_D6 = 139;; +let _MIPS_REG_D7 = 140;; +let _MIPS_REG_D8 = 141;; +let _MIPS_REG_D9 = 142;; +let _MIPS_REG_D10 = 143;; +let _MIPS_REG_D11 = 144;; +let _MIPS_REG_D12 = 145;; +let _MIPS_REG_D13 = 146;; +let _MIPS_REG_D14 = 147;; +let _MIPS_REG_D15 = 148;; +let _MIPS_REG_DSPOUTFLAG20 = 149;; +let _MIPS_REG_DSPOUTFLAG21 = 150;; +let _MIPS_REG_DSPOUTFLAG22 = 151;; +let _MIPS_REG_DSPOUTFLAG23 = 152;; +let _MIPS_REG_F0 = 153;; +let _MIPS_REG_F1 = 154;; +let _MIPS_REG_F2 = 155;; +let _MIPS_REG_F3 = 156;; +let _MIPS_REG_F4 = 157;; +let _MIPS_REG_F5 = 158;; +let _MIPS_REG_F6 = 159;; +let _MIPS_REG_F7 = 160;; +let _MIPS_REG_F8 = 161;; +let _MIPS_REG_F9 = 162;; +let _MIPS_REG_F10 = 163;; +let _MIPS_REG_F11 = 164;; +let _MIPS_REG_F12 = 165;; +let _MIPS_REG_F13 = 166;; +let _MIPS_REG_F14 = 167;; +let _MIPS_REG_F15 = 168;; +let _MIPS_REG_F16 = 169;; +let _MIPS_REG_F17 = 170;; +let _MIPS_REG_F18 = 171;; +let _MIPS_REG_F19 = 172;; +let _MIPS_REG_F20 = 173;; +let _MIPS_REG_F21 = 174;; +let _MIPS_REG_F22 = 175;; +let _MIPS_REG_F23 = 176;; +let _MIPS_REG_F24 = 177;; +let _MIPS_REG_F25 = 178;; +let _MIPS_REG_F26 = 179;; +let _MIPS_REG_F27 = 180;; +let _MIPS_REG_F28 = 181;; +let _MIPS_REG_F29 = 182;; +let _MIPS_REG_F30 = 183;; +let _MIPS_REG_F31 = 184;; +let _MIPS_REG_FCC0 = 185;; +let _MIPS_REG_FCC1 = 186;; +let _MIPS_REG_FCC2 = 187;; +let _MIPS_REG_FCC3 = 188;; +let _MIPS_REG_FCC4 = 189;; +let _MIPS_REG_FCC5 = 190;; +let _MIPS_REG_FCC6 = 191;; +let _MIPS_REG_FCC7 = 192;; +let _MIPS_REG_FCR0 = 193;; +let _MIPS_REG_FCR1 = 194;; +let _MIPS_REG_FCR2 = 195;; +let _MIPS_REG_FCR3 = 196;; +let _MIPS_REG_FCR4 = 197;; +let _MIPS_REG_FCR5 = 198;; +let _MIPS_REG_FCR6 = 199;; +let _MIPS_REG_FCR7 = 200;; +let _MIPS_REG_FCR8 = 201;; +let _MIPS_REG_FCR9 = 202;; +let _MIPS_REG_FCR10 = 203;; +let _MIPS_REG_FCR11 = 204;; +let _MIPS_REG_FCR12 = 205;; +let _MIPS_REG_FCR13 = 206;; +let _MIPS_REG_FCR14 = 207;; +let _MIPS_REG_FCR15 = 208;; +let _MIPS_REG_FCR16 = 209;; +let _MIPS_REG_FCR17 = 210;; +let _MIPS_REG_FCR18 = 211;; +let _MIPS_REG_FCR19 = 212;; +let _MIPS_REG_FCR20 = 213;; +let _MIPS_REG_FCR21 = 214;; +let _MIPS_REG_FCR22 = 215;; +let _MIPS_REG_FCR23 = 216;; +let _MIPS_REG_FCR24 = 217;; +let _MIPS_REG_FCR25 = 218;; +let _MIPS_REG_FCR26 = 219;; +let _MIPS_REG_FCR27 = 220;; +let _MIPS_REG_FCR28 = 221;; +let _MIPS_REG_FCR29 = 222;; +let _MIPS_REG_FCR30 = 223;; +let _MIPS_REG_FCR31 = 224;; +let _MIPS_REG_FP_64 = 225;; +let _MIPS_REG_F_HI0 = 226;; +let _MIPS_REG_F_HI1 = 227;; +let _MIPS_REG_F_HI2 = 228;; +let _MIPS_REG_F_HI3 = 229;; +let _MIPS_REG_F_HI4 = 230;; +let _MIPS_REG_F_HI5 = 231;; +let _MIPS_REG_F_HI6 = 232;; +let _MIPS_REG_F_HI7 = 233;; +let _MIPS_REG_F_HI8 = 234;; +let _MIPS_REG_F_HI9 = 235;; +let _MIPS_REG_F_HI10 = 236;; +let _MIPS_REG_F_HI11 = 237;; +let _MIPS_REG_F_HI12 = 238;; +let _MIPS_REG_F_HI13 = 239;; +let _MIPS_REG_F_HI14 = 240;; +let _MIPS_REG_F_HI15 = 241;; +let _MIPS_REG_F_HI16 = 242;; +let _MIPS_REG_F_HI17 = 243;; +let _MIPS_REG_F_HI18 = 244;; +let _MIPS_REG_F_HI19 = 245;; +let _MIPS_REG_F_HI20 = 246;; +let _MIPS_REG_F_HI21 = 247;; +let _MIPS_REG_F_HI22 = 248;; +let _MIPS_REG_F_HI23 = 249;; +let _MIPS_REG_F_HI24 = 250;; +let _MIPS_REG_F_HI25 = 251;; +let _MIPS_REG_F_HI26 = 252;; +let _MIPS_REG_F_HI27 = 253;; +let _MIPS_REG_F_HI28 = 254;; +let _MIPS_REG_F_HI29 = 255;; +let _MIPS_REG_F_HI30 = 256;; +let _MIPS_REG_F_HI31 = 257;; +let _MIPS_REG_GP_64 = 258;; +let _MIPS_REG_HI0 = 259;; +let _MIPS_REG_HI1 = 260;; +let _MIPS_REG_HI2 = 261;; +let _MIPS_REG_HI3 = 262;; +let _MIPS_REG_HWR0 = 263;; +let _MIPS_REG_HWR1 = 264;; +let _MIPS_REG_HWR2 = 265;; +let _MIPS_REG_HWR3 = 266;; +let _MIPS_REG_HWR4 = 267;; +let _MIPS_REG_HWR5 = 268;; +let _MIPS_REG_HWR6 = 269;; +let _MIPS_REG_HWR7 = 270;; +let _MIPS_REG_HWR8 = 271;; +let _MIPS_REG_HWR9 = 272;; +let _MIPS_REG_HWR10 = 273;; +let _MIPS_REG_HWR11 = 274;; +let _MIPS_REG_HWR12 = 275;; +let _MIPS_REG_HWR13 = 276;; +let _MIPS_REG_HWR14 = 277;; +let _MIPS_REG_HWR15 = 278;; +let _MIPS_REG_HWR16 = 279;; +let _MIPS_REG_HWR17 = 280;; +let _MIPS_REG_HWR18 = 281;; +let _MIPS_REG_HWR19 = 282;; +let _MIPS_REG_HWR20 = 283;; +let _MIPS_REG_HWR21 = 284;; +let _MIPS_REG_HWR22 = 285;; +let _MIPS_REG_HWR23 = 286;; +let _MIPS_REG_HWR24 = 287;; +let _MIPS_REG_HWR25 = 288;; +let _MIPS_REG_HWR26 = 289;; +let _MIPS_REG_HWR27 = 290;; +let _MIPS_REG_HWR28 = 291;; +let _MIPS_REG_HWR29 = 292;; +let _MIPS_REG_HWR30 = 293;; +let _MIPS_REG_HWR31 = 294;; +let _MIPS_REG_K0 = 295;; +let _MIPS_REG_K1 = 296;; +let _MIPS_REG_LO0 = 297;; +let _MIPS_REG_LO1 = 298;; +let _MIPS_REG_LO2 = 299;; +let _MIPS_REG_LO3 = 300;; +let _MIPS_REG_MPL0 = 301;; +let _MIPS_REG_MPL1 = 302;; +let _MIPS_REG_MPL2 = 303;; +let _MIPS_REG_MSA8 = 304;; +let _MIPS_REG_MSA9 = 305;; +let _MIPS_REG_MSA10 = 306;; +let _MIPS_REG_MSA11 = 307;; +let _MIPS_REG_MSA12 = 308;; +let _MIPS_REG_MSA13 = 309;; +let _MIPS_REG_MSA14 = 310;; +let _MIPS_REG_MSA15 = 311;; +let _MIPS_REG_MSA16 = 312;; +let _MIPS_REG_MSA17 = 313;; +let _MIPS_REG_MSA18 = 314;; +let _MIPS_REG_MSA19 = 315;; +let _MIPS_REG_MSA20 = 316;; +let _MIPS_REG_MSA21 = 317;; +let _MIPS_REG_MSA22 = 318;; +let _MIPS_REG_MSA23 = 319;; +let _MIPS_REG_MSA24 = 320;; +let _MIPS_REG_MSA25 = 321;; +let _MIPS_REG_MSA26 = 322;; +let _MIPS_REG_MSA27 = 323;; +let _MIPS_REG_MSA28 = 324;; +let _MIPS_REG_MSA29 = 325;; +let _MIPS_REG_MSA30 = 326;; +let _MIPS_REG_MSA31 = 327;; +let _MIPS_REG_P0 = 328;; +let _MIPS_REG_P1 = 329;; +let _MIPS_REG_P2 = 330;; +let _MIPS_REG_RA_64 = 331;; +let _MIPS_REG_S0 = 332;; +let _MIPS_REG_S1 = 333;; +let _MIPS_REG_S2 = 334;; +let _MIPS_REG_S3 = 335;; +let _MIPS_REG_S4 = 336;; +let _MIPS_REG_S5 = 337;; +let _MIPS_REG_S6 = 338;; +let _MIPS_REG_S7 = 339;; +let _MIPS_REG_SP_64 = 340;; +let _MIPS_REG_T0 = 341;; +let _MIPS_REG_T1 = 342;; +let _MIPS_REG_T2 = 343;; +let _MIPS_REG_T3 = 344;; +let _MIPS_REG_T4 = 345;; +let _MIPS_REG_T5 = 346;; +let _MIPS_REG_T6 = 347;; +let _MIPS_REG_T7 = 348;; +let _MIPS_REG_T8 = 349;; +let _MIPS_REG_T9 = 350;; +let _MIPS_REG_V0 = 351;; +let _MIPS_REG_V1 = 352;; +let _MIPS_REG_W0 = 353;; +let _MIPS_REG_W1 = 354;; +let _MIPS_REG_W2 = 355;; +let _MIPS_REG_W3 = 356;; +let _MIPS_REG_W4 = 357;; +let _MIPS_REG_W5 = 358;; +let _MIPS_REG_W6 = 359;; +let _MIPS_REG_W7 = 360;; +let _MIPS_REG_W8 = 361;; +let _MIPS_REG_W9 = 362;; +let _MIPS_REG_W10 = 363;; +let _MIPS_REG_W11 = 364;; +let _MIPS_REG_W12 = 365;; +let _MIPS_REG_W13 = 366;; +let _MIPS_REG_W14 = 367;; +let _MIPS_REG_W15 = 368;; +let _MIPS_REG_W16 = 369;; +let _MIPS_REG_W17 = 370;; +let _MIPS_REG_W18 = 371;; +let _MIPS_REG_W19 = 372;; +let _MIPS_REG_W20 = 373;; +let _MIPS_REG_W21 = 374;; +let _MIPS_REG_W22 = 375;; +let _MIPS_REG_W23 = 376;; +let _MIPS_REG_W24 = 377;; +let _MIPS_REG_W25 = 378;; +let _MIPS_REG_W26 = 379;; +let _MIPS_REG_W27 = 380;; +let _MIPS_REG_W28 = 381;; +let _MIPS_REG_W29 = 382;; +let _MIPS_REG_W30 = 383;; +let _MIPS_REG_W31 = 384;; +let _MIPS_REG_ZERO_64 = 385;; +let _MIPS_REG_A0_NM = 386;; +let _MIPS_REG_A1_NM = 387;; +let _MIPS_REG_A2_NM = 388;; +let _MIPS_REG_A3_NM = 389;; +let _MIPS_REG_A4_NM = 390;; +let _MIPS_REG_A5_NM = 391;; +let _MIPS_REG_A6_NM = 392;; +let _MIPS_REG_A7_NM = 393;; +let _MIPS_REG_COP0SEL_BADINST = 394;; +let _MIPS_REG_COP0SEL_BADINSTRP = 395;; +let _MIPS_REG_COP0SEL_BADINSTRX = 396;; +let _MIPS_REG_COP0SEL_BADVADDR = 397;; +let _MIPS_REG_COP0SEL_BEVVA = 398;; +let _MIPS_REG_COP0SEL_CACHEERR = 399;; +let _MIPS_REG_COP0SEL_CAUSE = 400;; +let _MIPS_REG_COP0SEL_CDMMBASE = 401;; +let _MIPS_REG_COP0SEL_CMGCRBASE = 402;; +let _MIPS_REG_COP0SEL_COMPARE = 403;; +let _MIPS_REG_COP0SEL_CONFIG = 404;; +let _MIPS_REG_COP0SEL_CONTEXT = 405;; +let _MIPS_REG_COP0SEL_CONTEXTCONFIG = 406;; +let _MIPS_REG_COP0SEL_COUNT = 407;; +let _MIPS_REG_COP0SEL_DDATAHI = 408;; +let _MIPS_REG_COP0SEL_DDATALO = 409;; +let _MIPS_REG_COP0SEL_DEBUG = 410;; +let _MIPS_REG_COP0SEL_DEBUGCONTEXTID = 411;; +let _MIPS_REG_COP0SEL_DEPC = 412;; +let _MIPS_REG_COP0SEL_DESAVE = 413;; +let _MIPS_REG_COP0SEL_DTAGHI = 414;; +let _MIPS_REG_COP0SEL_DTAGLO = 415;; +let _MIPS_REG_COP0SEL_EBASE = 416;; +let _MIPS_REG_COP0SEL_ENTRYHI = 417;; +let _MIPS_REG_COP0SEL_EPC = 418;; +let _MIPS_REG_COP0SEL_ERRCTL = 419;; +let _MIPS_REG_COP0SEL_ERROREPC = 420;; +let _MIPS_REG_COP0SEL_GLOBALNUMBER = 421;; +let _MIPS_REG_COP0SEL_GTOFFSET = 422;; +let _MIPS_REG_COP0SEL_HWRENA = 423;; +let _MIPS_REG_COP0SEL_IDATAHI = 424;; +let _MIPS_REG_COP0SEL_IDATALO = 425;; +let _MIPS_REG_COP0SEL_INDEX = 426;; +let _MIPS_REG_COP0SEL_INTCTL = 427;; +let _MIPS_REG_COP0SEL_ITAGHI = 428;; +let _MIPS_REG_COP0SEL_ITAGLO = 429;; +let _MIPS_REG_COP0SEL_LLADDR = 430;; +let _MIPS_REG_COP0SEL_MAAR = 431;; +let _MIPS_REG_COP0SEL_MAARI = 432;; +let _MIPS_REG_COP0SEL_MEMORYMAPID = 433;; +let _MIPS_REG_COP0SEL_MVPCONTROL = 434;; +let _MIPS_REG_COP0SEL_NESTEDEPC = 435;; +let _MIPS_REG_COP0SEL_NESTEDEXC = 436;; +let _MIPS_REG_COP0SEL_PAGEGRAIN = 437;; +let _MIPS_REG_COP0SEL_PAGEMASK = 438;; +let _MIPS_REG_COP0SEL_PRID = 439;; +let _MIPS_REG_COP0SEL_PWBASE = 440;; +let _MIPS_REG_COP0SEL_PWCTL = 441;; +let _MIPS_REG_COP0SEL_PWFIELD = 442;; +let _MIPS_REG_COP0SEL_PWSIZE = 443;; +let _MIPS_REG_COP0SEL_RANDOM = 444;; +let _MIPS_REG_COP0SEL_SRSCTL = 445;; +let _MIPS_REG_COP0SEL_SRSMAP = 446;; +let _MIPS_REG_COP0SEL_STATUS = 447;; +let _MIPS_REG_COP0SEL_TCBIND = 448;; +let _MIPS_REG_COP0SEL_TCCONTEXT = 449;; +let _MIPS_REG_COP0SEL_TCHALT = 450;; +let _MIPS_REG_COP0SEL_TCOPT = 451;; +let _MIPS_REG_COP0SEL_TCRESTART = 452;; +let _MIPS_REG_COP0SEL_TCSCHEDULE = 453;; +let _MIPS_REG_COP0SEL_TCSCHEFBACK = 454;; +let _MIPS_REG_COP0SEL_TCSTATUS = 455;; +let _MIPS_REG_COP0SEL_TRACECONTROL = 456;; +let _MIPS_REG_COP0SEL_TRACEDBPC = 457;; +let _MIPS_REG_COP0SEL_TRACEIBPC = 458;; +let _MIPS_REG_COP0SEL_USERLOCAL = 459;; +let _MIPS_REG_COP0SEL_VIEW_IPL = 460;; +let _MIPS_REG_COP0SEL_VIEW_RIPL = 461;; +let _MIPS_REG_COP0SEL_VPCONTROL = 462;; +let _MIPS_REG_COP0SEL_VPECONTROL = 463;; +let _MIPS_REG_COP0SEL_VPEOPT = 464;; +let _MIPS_REG_COP0SEL_VPESCHEDULE = 465;; +let _MIPS_REG_COP0SEL_VPESCHEFBACK = 466;; +let _MIPS_REG_COP0SEL_WIRED = 467;; +let _MIPS_REG_COP0SEL_XCONTEXT = 468;; +let _MIPS_REG_COP0SEL_XCONTEXTCONFIG = 469;; +let _MIPS_REG_COP0SEL_YQMASK = 470;; +let _MIPS_REG_K0_NM = 471;; +let _MIPS_REG_K1_NM = 472;; +let _MIPS_REG_S0_NM = 473;; +let _MIPS_REG_S1_NM = 474;; +let _MIPS_REG_S2_NM = 475;; +let _MIPS_REG_S3_NM = 476;; +let _MIPS_REG_S4_NM = 477;; +let _MIPS_REG_S5_NM = 478;; +let _MIPS_REG_S6_NM = 479;; +let _MIPS_REG_S7_NM = 480;; +let _MIPS_REG_T0_NM = 481;; +let _MIPS_REG_T1_NM = 482;; +let _MIPS_REG_T2_NM = 483;; +let _MIPS_REG_T3_NM = 484;; +let _MIPS_REG_T4_NM = 485;; +let _MIPS_REG_T5_NM = 486;; +let _MIPS_REG_T8_NM = 487;; +let _MIPS_REG_T9_NM = 488;; +let _MIPS_REG_A0_64 = 489;; +let _MIPS_REG_A1_64 = 490;; +let _MIPS_REG_A2_64 = 491;; +let _MIPS_REG_A3_64 = 492;; +let _MIPS_REG_AC0_64 = 493;; +let _MIPS_REG_COP0SEL_CONFIG1 = 494;; +let _MIPS_REG_COP0SEL_CONFIG2 = 495;; +let _MIPS_REG_COP0SEL_CONFIG3 = 496;; +let _MIPS_REG_COP0SEL_CONFIG4 = 497;; +let _MIPS_REG_COP0SEL_CONFIG5 = 498;; +let _MIPS_REG_COP0SEL_DEBUG2 = 499;; +let _MIPS_REG_COP0SEL_ENTRYLO0 = 500;; +let _MIPS_REG_COP0SEL_ENTRYLO1 = 501;; +let _MIPS_REG_COP0SEL_GUESTCTL0 = 502;; +let _MIPS_REG_COP0SEL_GUESTCTL1 = 503;; +let _MIPS_REG_COP0SEL_GUESTCTL2 = 504;; +let _MIPS_REG_COP0SEL_GUESTCTL3 = 505;; +let _MIPS_REG_COP0SEL_KSCRATCH1 = 506;; +let _MIPS_REG_COP0SEL_KSCRATCH2 = 507;; +let _MIPS_REG_COP0SEL_KSCRATCH3 = 508;; +let _MIPS_REG_COP0SEL_KSCRATCH4 = 509;; +let _MIPS_REG_COP0SEL_KSCRATCH5 = 510;; +let _MIPS_REG_COP0SEL_KSCRATCH6 = 511;; +let _MIPS_REG_COP0SEL_MVPCONF0 = 512;; +let _MIPS_REG_COP0SEL_MVPCONF1 = 513;; +let _MIPS_REG_COP0SEL_PERFCNT0 = 514;; +let _MIPS_REG_COP0SEL_PERFCNT1 = 515;; +let _MIPS_REG_COP0SEL_PERFCNT2 = 516;; +let _MIPS_REG_COP0SEL_PERFCNT3 = 517;; +let _MIPS_REG_COP0SEL_PERFCNT4 = 518;; +let _MIPS_REG_COP0SEL_PERFCNT5 = 519;; +let _MIPS_REG_COP0SEL_PERFCNT6 = 520;; +let _MIPS_REG_COP0SEL_PERFCNT7 = 521;; +let _MIPS_REG_COP0SEL_PERFCTL0 = 522;; +let _MIPS_REG_COP0SEL_PERFCTL1 = 523;; +let _MIPS_REG_COP0SEL_PERFCTL2 = 524;; +let _MIPS_REG_COP0SEL_PERFCTL3 = 525;; +let _MIPS_REG_COP0SEL_PERFCTL4 = 526;; +let _MIPS_REG_COP0SEL_PERFCTL5 = 527;; +let _MIPS_REG_COP0SEL_PERFCTL6 = 528;; +let _MIPS_REG_COP0SEL_PERFCTL7 = 529;; +let _MIPS_REG_COP0SEL_SEGCTL0 = 530;; +let _MIPS_REG_COP0SEL_SEGCTL1 = 531;; +let _MIPS_REG_COP0SEL_SEGCTL2 = 532;; +let _MIPS_REG_COP0SEL_SRSCONF0 = 533;; +let _MIPS_REG_COP0SEL_SRSCONF1 = 534;; +let _MIPS_REG_COP0SEL_SRSCONF2 = 535;; +let _MIPS_REG_COP0SEL_SRSCONF3 = 536;; +let _MIPS_REG_COP0SEL_SRSCONF4 = 537;; +let _MIPS_REG_COP0SEL_SRSMAP2 = 538;; +let _MIPS_REG_COP0SEL_TRACECONTROL2 = 539;; +let _MIPS_REG_COP0SEL_TRACECONTROL3 = 540;; +let _MIPS_REG_COP0SEL_USERTRACEDATA1 = 541;; +let _MIPS_REG_COP0SEL_USERTRACEDATA2 = 542;; +let _MIPS_REG_COP0SEL_VPECONF0 = 543;; +let _MIPS_REG_COP0SEL_VPECONF1 = 544;; +let _MIPS_REG_COP0SEL_WATCHHI0 = 545;; +let _MIPS_REG_COP0SEL_WATCHHI1 = 546;; +let _MIPS_REG_COP0SEL_WATCHHI2 = 547;; +let _MIPS_REG_COP0SEL_WATCHHI3 = 548;; +let _MIPS_REG_COP0SEL_WATCHHI4 = 549;; +let _MIPS_REG_COP0SEL_WATCHHI5 = 550;; +let _MIPS_REG_COP0SEL_WATCHHI6 = 551;; +let _MIPS_REG_COP0SEL_WATCHHI7 = 552;; +let _MIPS_REG_COP0SEL_WATCHHI8 = 553;; +let _MIPS_REG_COP0SEL_WATCHHI9 = 554;; +let _MIPS_REG_COP0SEL_WATCHHI10 = 555;; +let _MIPS_REG_COP0SEL_WATCHHI11 = 556;; +let _MIPS_REG_COP0SEL_WATCHHI12 = 557;; +let _MIPS_REG_COP0SEL_WATCHHI13 = 558;; +let _MIPS_REG_COP0SEL_WATCHHI14 = 559;; +let _MIPS_REG_COP0SEL_WATCHHI15 = 560;; +let _MIPS_REG_COP0SEL_WATCHLO0 = 561;; +let _MIPS_REG_COP0SEL_WATCHLO1 = 562;; +let _MIPS_REG_COP0SEL_WATCHLO2 = 563;; +let _MIPS_REG_COP0SEL_WATCHLO3 = 564;; +let _MIPS_REG_COP0SEL_WATCHLO4 = 565;; +let _MIPS_REG_COP0SEL_WATCHLO5 = 566;; +let _MIPS_REG_COP0SEL_WATCHLO6 = 567;; +let _MIPS_REG_COP0SEL_WATCHLO7 = 568;; +let _MIPS_REG_COP0SEL_WATCHLO8 = 569;; +let _MIPS_REG_COP0SEL_WATCHLO9 = 570;; +let _MIPS_REG_COP0SEL_WATCHLO10 = 571;; +let _MIPS_REG_COP0SEL_WATCHLO11 = 572;; +let _MIPS_REG_COP0SEL_WATCHLO12 = 573;; +let _MIPS_REG_COP0SEL_WATCHLO13 = 574;; +let _MIPS_REG_COP0SEL_WATCHLO14 = 575;; +let _MIPS_REG_COP0SEL_WATCHLO15 = 576;; +let _MIPS_REG_D0_64 = 577;; +let _MIPS_REG_D1_64 = 578;; +let _MIPS_REG_D2_64 = 579;; +let _MIPS_REG_D3_64 = 580;; +let _MIPS_REG_D4_64 = 581;; +let _MIPS_REG_D5_64 = 582;; +let _MIPS_REG_D6_64 = 583;; +let _MIPS_REG_D7_64 = 584;; +let _MIPS_REG_D8_64 = 585;; +let _MIPS_REG_D9_64 = 586;; +let _MIPS_REG_D10_64 = 587;; +let _MIPS_REG_D11_64 = 588;; +let _MIPS_REG_D12_64 = 589;; +let _MIPS_REG_D13_64 = 590;; +let _MIPS_REG_D14_64 = 591;; +let _MIPS_REG_D15_64 = 592;; +let _MIPS_REG_D16_64 = 593;; +let _MIPS_REG_D17_64 = 594;; +let _MIPS_REG_D18_64 = 595;; +let _MIPS_REG_D19_64 = 596;; +let _MIPS_REG_D20_64 = 597;; +let _MIPS_REG_D21_64 = 598;; +let _MIPS_REG_D22_64 = 599;; +let _MIPS_REG_D23_64 = 600;; +let _MIPS_REG_D24_64 = 601;; +let _MIPS_REG_D25_64 = 602;; +let _MIPS_REG_D26_64 = 603;; +let _MIPS_REG_D27_64 = 604;; +let _MIPS_REG_D28_64 = 605;; +let _MIPS_REG_D29_64 = 606;; +let _MIPS_REG_D30_64 = 607;; +let _MIPS_REG_D31_64 = 608;; +let _MIPS_REG_DSPOUTFLAG16_19 = 609;; +let _MIPS_REG_HI0_64 = 610;; +let _MIPS_REG_K0_64 = 611;; +let _MIPS_REG_K1_64 = 612;; +let _MIPS_REG_LO0_64 = 613;; +let _MIPS_REG_S0_64 = 614;; +let _MIPS_REG_S1_64 = 615;; +let _MIPS_REG_S2_64 = 616;; +let _MIPS_REG_S3_64 = 617;; +let _MIPS_REG_S4_64 = 618;; +let _MIPS_REG_S5_64 = 619;; +let _MIPS_REG_S6_64 = 620;; +let _MIPS_REG_S7_64 = 621;; +let _MIPS_REG_T0_64 = 622;; +let _MIPS_REG_T1_64 = 623;; +let _MIPS_REG_T2_64 = 624;; +let _MIPS_REG_T3_64 = 625;; +let _MIPS_REG_T4_64 = 626;; +let _MIPS_REG_T5_64 = 627;; +let _MIPS_REG_T6_64 = 628;; +let _MIPS_REG_T7_64 = 629;; +let _MIPS_REG_T8_64 = 630;; +let _MIPS_REG_T9_64 = 631;; +let _MIPS_REG_V0_64 = 632;; +let _MIPS_REG_V1_64 = 633;; +let _MIPS_REG_COP0SEL_GUESTCTL0EXT = 634;; +let _MIPS_REG_ENDING = 635;; let _MIPS_INS_INVALID = 0;; -let _MIPS_INS_ABSQ_S = 1;; -let _MIPS_INS_ADD = 2;; -let _MIPS_INS_ADDIUPC = 3;; -let _MIPS_INS_ADDIUR1SP = 4;; -let _MIPS_INS_ADDIUR2 = 5;; -let _MIPS_INS_ADDIUS5 = 6;; -let _MIPS_INS_ADDIUSP = 7;; -let _MIPS_INS_ADDQH = 8;; -let _MIPS_INS_ADDQH_R = 9;; -let _MIPS_INS_ADDQ = 10;; -let _MIPS_INS_ADDQ_S = 11;; -let _MIPS_INS_ADDSC = 12;; -let _MIPS_INS_ADDS_A = 13;; -let _MIPS_INS_ADDS_S = 14;; -let _MIPS_INS_ADDS_U = 15;; -let _MIPS_INS_ADDU16 = 16;; -let _MIPS_INS_ADDUH = 17;; -let _MIPS_INS_ADDUH_R = 18;; -let _MIPS_INS_ADDU = 19;; -let _MIPS_INS_ADDU_S = 20;; -let _MIPS_INS_ADDVI = 21;; -let _MIPS_INS_ADDV = 22;; -let _MIPS_INS_ADDWC = 23;; -let _MIPS_INS_ADD_A = 24;; -let _MIPS_INS_ADDI = 25;; -let _MIPS_INS_ADDIU = 26;; -let _MIPS_INS_ALIGN = 27;; -let _MIPS_INS_ALUIPC = 28;; -let _MIPS_INS_AND = 29;; -let _MIPS_INS_AND16 = 30;; -let _MIPS_INS_ANDI16 = 31;; -let _MIPS_INS_ANDI = 32;; -let _MIPS_INS_APPEND = 33;; -let _MIPS_INS_ASUB_S = 34;; -let _MIPS_INS_ASUB_U = 35;; -let _MIPS_INS_AUI = 36;; -let _MIPS_INS_AUIPC = 37;; -let _MIPS_INS_AVER_S = 38;; -let _MIPS_INS_AVER_U = 39;; -let _MIPS_INS_AVE_S = 40;; -let _MIPS_INS_AVE_U = 41;; -let _MIPS_INS_B16 = 42;; -let _MIPS_INS_BADDU = 43;; -let _MIPS_INS_BAL = 44;; -let _MIPS_INS_BALC = 45;; -let _MIPS_INS_BALIGN = 46;; -let _MIPS_INS_BBIT0 = 47;; -let _MIPS_INS_BBIT032 = 48;; -let _MIPS_INS_BBIT1 = 49;; -let _MIPS_INS_BBIT132 = 50;; -let _MIPS_INS_BC = 51;; -let _MIPS_INS_BC0F = 52;; -let _MIPS_INS_BC0FL = 53;; -let _MIPS_INS_BC0T = 54;; -let _MIPS_INS_BC0TL = 55;; -let _MIPS_INS_BC1EQZ = 56;; -let _MIPS_INS_BC1F = 57;; -let _MIPS_INS_BC1FL = 58;; -let _MIPS_INS_BC1NEZ = 59;; -let _MIPS_INS_BC1T = 60;; -let _MIPS_INS_BC1TL = 61;; -let _MIPS_INS_BC2EQZ = 62;; -let _MIPS_INS_BC2F = 63;; -let _MIPS_INS_BC2FL = 64;; -let _MIPS_INS_BC2NEZ = 65;; -let _MIPS_INS_BC2T = 66;; -let _MIPS_INS_BC2TL = 67;; -let _MIPS_INS_BC3F = 68;; -let _MIPS_INS_BC3FL = 69;; -let _MIPS_INS_BC3T = 70;; -let _MIPS_INS_BC3TL = 71;; -let _MIPS_INS_BCLRI = 72;; -let _MIPS_INS_BCLR = 73;; -let _MIPS_INS_BEQ = 74;; -let _MIPS_INS_BEQC = 75;; -let _MIPS_INS_BEQL = 76;; -let _MIPS_INS_BEQZ16 = 77;; -let _MIPS_INS_BEQZALC = 78;; -let _MIPS_INS_BEQZC = 79;; -let _MIPS_INS_BGEC = 80;; -let _MIPS_INS_BGEUC = 81;; -let _MIPS_INS_BGEZ = 82;; -let _MIPS_INS_BGEZAL = 83;; -let _MIPS_INS_BGEZALC = 84;; -let _MIPS_INS_BGEZALL = 85;; -let _MIPS_INS_BGEZALS = 86;; -let _MIPS_INS_BGEZC = 87;; -let _MIPS_INS_BGEZL = 88;; -let _MIPS_INS_BGTZ = 89;; -let _MIPS_INS_BGTZALC = 90;; -let _MIPS_INS_BGTZC = 91;; -let _MIPS_INS_BGTZL = 92;; -let _MIPS_INS_BINSLI = 93;; -let _MIPS_INS_BINSL = 94;; -let _MIPS_INS_BINSRI = 95;; -let _MIPS_INS_BINSR = 96;; -let _MIPS_INS_BITREV = 97;; -let _MIPS_INS_BITSWAP = 98;; -let _MIPS_INS_BLEZ = 99;; -let _MIPS_INS_BLEZALC = 100;; -let _MIPS_INS_BLEZC = 101;; -let _MIPS_INS_BLEZL = 102;; -let _MIPS_INS_BLTC = 103;; -let _MIPS_INS_BLTUC = 104;; -let _MIPS_INS_BLTZ = 105;; -let _MIPS_INS_BLTZAL = 106;; -let _MIPS_INS_BLTZALC = 107;; -let _MIPS_INS_BLTZALL = 108;; -let _MIPS_INS_BLTZALS = 109;; -let _MIPS_INS_BLTZC = 110;; -let _MIPS_INS_BLTZL = 111;; -let _MIPS_INS_BMNZI = 112;; -let _MIPS_INS_BMNZ = 113;; -let _MIPS_INS_BMZI = 114;; -let _MIPS_INS_BMZ = 115;; -let _MIPS_INS_BNE = 116;; -let _MIPS_INS_BNEC = 117;; -let _MIPS_INS_BNEGI = 118;; -let _MIPS_INS_BNEG = 119;; -let _MIPS_INS_BNEL = 120;; -let _MIPS_INS_BNEZ16 = 121;; -let _MIPS_INS_BNEZALC = 122;; -let _MIPS_INS_BNEZC = 123;; -let _MIPS_INS_BNVC = 124;; -let _MIPS_INS_BNZ = 125;; -let _MIPS_INS_BOVC = 126;; -let _MIPS_INS_BPOSGE32 = 127;; -let _MIPS_INS_BREAK = 128;; -let _MIPS_INS_BREAK16 = 129;; -let _MIPS_INS_BSELI = 130;; -let _MIPS_INS_BSEL = 131;; -let _MIPS_INS_BSETI = 132;; -let _MIPS_INS_BSET = 133;; -let _MIPS_INS_BZ = 134;; -let _MIPS_INS_BEQZ = 135;; -let _MIPS_INS_B = 136;; -let _MIPS_INS_BNEZ = 137;; -let _MIPS_INS_BTEQZ = 138;; -let _MIPS_INS_BTNEZ = 139;; -let _MIPS_INS_CACHE = 140;; -let _MIPS_INS_CEIL = 141;; -let _MIPS_INS_CEQI = 142;; -let _MIPS_INS_CEQ = 143;; -let _MIPS_INS_CFC1 = 144;; -let _MIPS_INS_CFCMSA = 145;; -let _MIPS_INS_CINS = 146;; -let _MIPS_INS_CINS32 = 147;; -let _MIPS_INS_CLASS = 148;; -let _MIPS_INS_CLEI_S = 149;; -let _MIPS_INS_CLEI_U = 150;; -let _MIPS_INS_CLE_S = 151;; -let _MIPS_INS_CLE_U = 152;; -let _MIPS_INS_CLO = 153;; -let _MIPS_INS_CLTI_S = 154;; -let _MIPS_INS_CLTI_U = 155;; -let _MIPS_INS_CLT_S = 156;; -let _MIPS_INS_CLT_U = 157;; -let _MIPS_INS_CLZ = 158;; -let _MIPS_INS_CMPGDU = 159;; -let _MIPS_INS_CMPGU = 160;; -let _MIPS_INS_CMPU = 161;; -let _MIPS_INS_CMP = 162;; -let _MIPS_INS_COPY_S = 163;; -let _MIPS_INS_COPY_U = 164;; -let _MIPS_INS_CTC1 = 165;; -let _MIPS_INS_CTCMSA = 166;; -let _MIPS_INS_CVT = 167;; -let _MIPS_INS_C = 168;; -let _MIPS_INS_CMPI = 169;; -let _MIPS_INS_DADD = 170;; -let _MIPS_INS_DADDI = 171;; -let _MIPS_INS_DADDIU = 172;; -let _MIPS_INS_DADDU = 173;; -let _MIPS_INS_DAHI = 174;; -let _MIPS_INS_DALIGN = 175;; -let _MIPS_INS_DATI = 176;; -let _MIPS_INS_DAUI = 177;; -let _MIPS_INS_DBITSWAP = 178;; -let _MIPS_INS_DCLO = 179;; -let _MIPS_INS_DCLZ = 180;; -let _MIPS_INS_DDIV = 181;; -let _MIPS_INS_DDIVU = 182;; -let _MIPS_INS_DERET = 183;; -let _MIPS_INS_DEXT = 184;; -let _MIPS_INS_DEXTM = 185;; -let _MIPS_INS_DEXTU = 186;; -let _MIPS_INS_DI = 187;; -let _MIPS_INS_DINS = 188;; -let _MIPS_INS_DINSM = 189;; -let _MIPS_INS_DINSU = 190;; -let _MIPS_INS_DIV = 191;; -let _MIPS_INS_DIVU = 192;; -let _MIPS_INS_DIV_S = 193;; -let _MIPS_INS_DIV_U = 194;; -let _MIPS_INS_DLSA = 195;; -let _MIPS_INS_DMFC0 = 196;; -let _MIPS_INS_DMFC1 = 197;; -let _MIPS_INS_DMFC2 = 198;; -let _MIPS_INS_DMOD = 199;; -let _MIPS_INS_DMODU = 200;; -let _MIPS_INS_DMTC0 = 201;; -let _MIPS_INS_DMTC1 = 202;; -let _MIPS_INS_DMTC2 = 203;; -let _MIPS_INS_DMUH = 204;; -let _MIPS_INS_DMUHU = 205;; -let _MIPS_INS_DMUL = 206;; -let _MIPS_INS_DMULT = 207;; -let _MIPS_INS_DMULTU = 208;; -let _MIPS_INS_DMULU = 209;; -let _MIPS_INS_DOTP_S = 210;; -let _MIPS_INS_DOTP_U = 211;; -let _MIPS_INS_DPADD_S = 212;; -let _MIPS_INS_DPADD_U = 213;; -let _MIPS_INS_DPAQX_SA = 214;; -let _MIPS_INS_DPAQX_S = 215;; -let _MIPS_INS_DPAQ_SA = 216;; -let _MIPS_INS_DPAQ_S = 217;; -let _MIPS_INS_DPAU = 218;; -let _MIPS_INS_DPAX = 219;; -let _MIPS_INS_DPA = 220;; -let _MIPS_INS_DPOP = 221;; -let _MIPS_INS_DPSQX_SA = 222;; -let _MIPS_INS_DPSQX_S = 223;; -let _MIPS_INS_DPSQ_SA = 224;; -let _MIPS_INS_DPSQ_S = 225;; -let _MIPS_INS_DPSUB_S = 226;; -let _MIPS_INS_DPSUB_U = 227;; -let _MIPS_INS_DPSU = 228;; -let _MIPS_INS_DPSX = 229;; -let _MIPS_INS_DPS = 230;; -let _MIPS_INS_DROTR = 231;; -let _MIPS_INS_DROTR32 = 232;; -let _MIPS_INS_DROTRV = 233;; -let _MIPS_INS_DSBH = 234;; -let _MIPS_INS_DSHD = 235;; -let _MIPS_INS_DSLL = 236;; -let _MIPS_INS_DSLL32 = 237;; -let _MIPS_INS_DSLLV = 238;; -let _MIPS_INS_DSRA = 239;; -let _MIPS_INS_DSRA32 = 240;; -let _MIPS_INS_DSRAV = 241;; -let _MIPS_INS_DSRL = 242;; -let _MIPS_INS_DSRL32 = 243;; -let _MIPS_INS_DSRLV = 244;; -let _MIPS_INS_DSUB = 245;; -let _MIPS_INS_DSUBU = 246;; -let _MIPS_INS_EHB = 247;; -let _MIPS_INS_EI = 248;; -let _MIPS_INS_ERET = 249;; -let _MIPS_INS_EXT = 250;; -let _MIPS_INS_EXTP = 251;; -let _MIPS_INS_EXTPDP = 252;; -let _MIPS_INS_EXTPDPV = 253;; -let _MIPS_INS_EXTPV = 254;; -let _MIPS_INS_EXTRV_RS = 255;; -let _MIPS_INS_EXTRV_R = 256;; -let _MIPS_INS_EXTRV_S = 257;; -let _MIPS_INS_EXTRV = 258;; -let _MIPS_INS_EXTR_RS = 259;; -let _MIPS_INS_EXTR_R = 260;; -let _MIPS_INS_EXTR_S = 261;; -let _MIPS_INS_EXTR = 262;; -let _MIPS_INS_EXTS = 263;; -let _MIPS_INS_EXTS32 = 264;; -let _MIPS_INS_ABS = 265;; -let _MIPS_INS_FADD = 266;; -let _MIPS_INS_FCAF = 267;; -let _MIPS_INS_FCEQ = 268;; -let _MIPS_INS_FCLASS = 269;; -let _MIPS_INS_FCLE = 270;; -let _MIPS_INS_FCLT = 271;; -let _MIPS_INS_FCNE = 272;; -let _MIPS_INS_FCOR = 273;; -let _MIPS_INS_FCUEQ = 274;; -let _MIPS_INS_FCULE = 275;; -let _MIPS_INS_FCULT = 276;; -let _MIPS_INS_FCUNE = 277;; -let _MIPS_INS_FCUN = 278;; -let _MIPS_INS_FDIV = 279;; -let _MIPS_INS_FEXDO = 280;; -let _MIPS_INS_FEXP2 = 281;; -let _MIPS_INS_FEXUPL = 282;; -let _MIPS_INS_FEXUPR = 283;; -let _MIPS_INS_FFINT_S = 284;; -let _MIPS_INS_FFINT_U = 285;; -let _MIPS_INS_FFQL = 286;; -let _MIPS_INS_FFQR = 287;; -let _MIPS_INS_FILL = 288;; -let _MIPS_INS_FLOG2 = 289;; -let _MIPS_INS_FLOOR = 290;; -let _MIPS_INS_FMADD = 291;; -let _MIPS_INS_FMAX_A = 292;; -let _MIPS_INS_FMAX = 293;; -let _MIPS_INS_FMIN_A = 294;; -let _MIPS_INS_FMIN = 295;; -let _MIPS_INS_MOV = 296;; -let _MIPS_INS_FMSUB = 297;; -let _MIPS_INS_FMUL = 298;; -let _MIPS_INS_MUL = 299;; -let _MIPS_INS_NEG = 300;; -let _MIPS_INS_FRCP = 301;; -let _MIPS_INS_FRINT = 302;; -let _MIPS_INS_FRSQRT = 303;; -let _MIPS_INS_FSAF = 304;; -let _MIPS_INS_FSEQ = 305;; -let _MIPS_INS_FSLE = 306;; -let _MIPS_INS_FSLT = 307;; -let _MIPS_INS_FSNE = 308;; -let _MIPS_INS_FSOR = 309;; -let _MIPS_INS_FSQRT = 310;; -let _MIPS_INS_SQRT = 311;; -let _MIPS_INS_FSUB = 312;; -let _MIPS_INS_SUB = 313;; -let _MIPS_INS_FSUEQ = 314;; -let _MIPS_INS_FSULE = 315;; -let _MIPS_INS_FSULT = 316;; -let _MIPS_INS_FSUNE = 317;; -let _MIPS_INS_FSUN = 318;; -let _MIPS_INS_FTINT_S = 319;; -let _MIPS_INS_FTINT_U = 320;; -let _MIPS_INS_FTQ = 321;; -let _MIPS_INS_FTRUNC_S = 322;; -let _MIPS_INS_FTRUNC_U = 323;; -let _MIPS_INS_HADD_S = 324;; -let _MIPS_INS_HADD_U = 325;; -let _MIPS_INS_HSUB_S = 326;; -let _MIPS_INS_HSUB_U = 327;; -let _MIPS_INS_ILVEV = 328;; -let _MIPS_INS_ILVL = 329;; -let _MIPS_INS_ILVOD = 330;; -let _MIPS_INS_ILVR = 331;; -let _MIPS_INS_INS = 332;; -let _MIPS_INS_INSERT = 333;; -let _MIPS_INS_INSV = 334;; -let _MIPS_INS_INSVE = 335;; -let _MIPS_INS_J = 336;; -let _MIPS_INS_JAL = 337;; -let _MIPS_INS_JALR = 338;; -let _MIPS_INS_JALRS16 = 339;; -let _MIPS_INS_JALRS = 340;; -let _MIPS_INS_JALS = 341;; -let _MIPS_INS_JALX = 342;; -let _MIPS_INS_JIALC = 343;; -let _MIPS_INS_JIC = 344;; -let _MIPS_INS_JR = 345;; -let _MIPS_INS_JR16 = 346;; -let _MIPS_INS_JRADDIUSP = 347;; -let _MIPS_INS_JRC = 348;; -let _MIPS_INS_JALRC = 349;; -let _MIPS_INS_LB = 350;; -let _MIPS_INS_LBU16 = 351;; -let _MIPS_INS_LBUX = 352;; -let _MIPS_INS_LBU = 353;; -let _MIPS_INS_LD = 354;; -let _MIPS_INS_LDC1 = 355;; -let _MIPS_INS_LDC2 = 356;; -let _MIPS_INS_LDC3 = 357;; -let _MIPS_INS_LDI = 358;; -let _MIPS_INS_LDL = 359;; -let _MIPS_INS_LDPC = 360;; -let _MIPS_INS_LDR = 361;; -let _MIPS_INS_LDXC1 = 362;; -let _MIPS_INS_LH = 363;; -let _MIPS_INS_LHU16 = 364;; -let _MIPS_INS_LHX = 365;; -let _MIPS_INS_LHU = 366;; -let _MIPS_INS_LI16 = 367;; -let _MIPS_INS_LL = 368;; -let _MIPS_INS_LLD = 369;; -let _MIPS_INS_LSA = 370;; -let _MIPS_INS_LUXC1 = 371;; -let _MIPS_INS_LUI = 372;; -let _MIPS_INS_LW = 373;; -let _MIPS_INS_LW16 = 374;; -let _MIPS_INS_LWC1 = 375;; -let _MIPS_INS_LWC2 = 376;; -let _MIPS_INS_LWC3 = 377;; -let _MIPS_INS_LWL = 378;; -let _MIPS_INS_LWM16 = 379;; -let _MIPS_INS_LWM32 = 380;; -let _MIPS_INS_LWPC = 381;; -let _MIPS_INS_LWP = 382;; -let _MIPS_INS_LWR = 383;; -let _MIPS_INS_LWUPC = 384;; -let _MIPS_INS_LWU = 385;; -let _MIPS_INS_LWX = 386;; -let _MIPS_INS_LWXC1 = 387;; -let _MIPS_INS_LWXS = 388;; -let _MIPS_INS_LI = 389;; -let _MIPS_INS_MADD = 390;; -let _MIPS_INS_MADDF = 391;; -let _MIPS_INS_MADDR_Q = 392;; -let _MIPS_INS_MADDU = 393;; -let _MIPS_INS_MADDV = 394;; -let _MIPS_INS_MADD_Q = 395;; -let _MIPS_INS_MAQ_SA = 396;; -let _MIPS_INS_MAQ_S = 397;; -let _MIPS_INS_MAXA = 398;; -let _MIPS_INS_MAXI_S = 399;; -let _MIPS_INS_MAXI_U = 400;; -let _MIPS_INS_MAX_A = 401;; -let _MIPS_INS_MAX = 402;; -let _MIPS_INS_MAX_S = 403;; -let _MIPS_INS_MAX_U = 404;; -let _MIPS_INS_MFC0 = 405;; -let _MIPS_INS_MFC1 = 406;; -let _MIPS_INS_MFC2 = 407;; -let _MIPS_INS_MFHC1 = 408;; -let _MIPS_INS_MFHI = 409;; -let _MIPS_INS_MFLO = 410;; -let _MIPS_INS_MINA = 411;; -let _MIPS_INS_MINI_S = 412;; -let _MIPS_INS_MINI_U = 413;; -let _MIPS_INS_MIN_A = 414;; -let _MIPS_INS_MIN = 415;; -let _MIPS_INS_MIN_S = 416;; -let _MIPS_INS_MIN_U = 417;; -let _MIPS_INS_MOD = 418;; -let _MIPS_INS_MODSUB = 419;; -let _MIPS_INS_MODU = 420;; -let _MIPS_INS_MOD_S = 421;; -let _MIPS_INS_MOD_U = 422;; -let _MIPS_INS_MOVE = 423;; -let _MIPS_INS_MOVEP = 424;; -let _MIPS_INS_MOVF = 425;; -let _MIPS_INS_MOVN = 426;; -let _MIPS_INS_MOVT = 427;; -let _MIPS_INS_MOVZ = 428;; -let _MIPS_INS_MSUB = 429;; -let _MIPS_INS_MSUBF = 430;; -let _MIPS_INS_MSUBR_Q = 431;; -let _MIPS_INS_MSUBU = 432;; -let _MIPS_INS_MSUBV = 433;; -let _MIPS_INS_MSUB_Q = 434;; -let _MIPS_INS_MTC0 = 435;; -let _MIPS_INS_MTC1 = 436;; -let _MIPS_INS_MTC2 = 437;; -let _MIPS_INS_MTHC1 = 438;; -let _MIPS_INS_MTHI = 439;; -let _MIPS_INS_MTHLIP = 440;; -let _MIPS_INS_MTLO = 441;; -let _MIPS_INS_MTM0 = 442;; -let _MIPS_INS_MTM1 = 443;; -let _MIPS_INS_MTM2 = 444;; -let _MIPS_INS_MTP0 = 445;; -let _MIPS_INS_MTP1 = 446;; -let _MIPS_INS_MTP2 = 447;; -let _MIPS_INS_MUH = 448;; -let _MIPS_INS_MUHU = 449;; -let _MIPS_INS_MULEQ_S = 450;; -let _MIPS_INS_MULEU_S = 451;; -let _MIPS_INS_MULQ_RS = 452;; -let _MIPS_INS_MULQ_S = 453;; -let _MIPS_INS_MULR_Q = 454;; -let _MIPS_INS_MULSAQ_S = 455;; -let _MIPS_INS_MULSA = 456;; -let _MIPS_INS_MULT = 457;; -let _MIPS_INS_MULTU = 458;; -let _MIPS_INS_MULU = 459;; -let _MIPS_INS_MULV = 460;; -let _MIPS_INS_MUL_Q = 461;; -let _MIPS_INS_MUL_S = 462;; -let _MIPS_INS_NLOC = 463;; -let _MIPS_INS_NLZC = 464;; -let _MIPS_INS_NMADD = 465;; -let _MIPS_INS_NMSUB = 466;; -let _MIPS_INS_NOR = 467;; -let _MIPS_INS_NORI = 468;; -let _MIPS_INS_NOT16 = 469;; -let _MIPS_INS_NOT = 470;; -let _MIPS_INS_OR = 471;; -let _MIPS_INS_OR16 = 472;; -let _MIPS_INS_ORI = 473;; -let _MIPS_INS_PACKRL = 474;; -let _MIPS_INS_PAUSE = 475;; -let _MIPS_INS_PCKEV = 476;; -let _MIPS_INS_PCKOD = 477;; -let _MIPS_INS_PCNT = 478;; -let _MIPS_INS_PICK = 479;; -let _MIPS_INS_POP = 480;; -let _MIPS_INS_PRECEQU = 481;; -let _MIPS_INS_PRECEQ = 482;; -let _MIPS_INS_PRECEU = 483;; -let _MIPS_INS_PRECRQU_S = 484;; -let _MIPS_INS_PRECRQ = 485;; -let _MIPS_INS_PRECRQ_RS = 486;; -let _MIPS_INS_PRECR = 487;; -let _MIPS_INS_PRECR_SRA = 488;; -let _MIPS_INS_PRECR_SRA_R = 489;; -let _MIPS_INS_PREF = 490;; -let _MIPS_INS_PREPEND = 491;; -let _MIPS_INS_RADDU = 492;; -let _MIPS_INS_RDDSP = 493;; -let _MIPS_INS_RDHWR = 494;; -let _MIPS_INS_REPLV = 495;; -let _MIPS_INS_REPL = 496;; -let _MIPS_INS_RINT = 497;; -let _MIPS_INS_ROTR = 498;; -let _MIPS_INS_ROTRV = 499;; -let _MIPS_INS_ROUND = 500;; -let _MIPS_INS_SAT_S = 501;; -let _MIPS_INS_SAT_U = 502;; -let _MIPS_INS_SB = 503;; -let _MIPS_INS_SB16 = 504;; -let _MIPS_INS_SC = 505;; -let _MIPS_INS_SCD = 506;; -let _MIPS_INS_SD = 507;; -let _MIPS_INS_SDBBP = 508;; -let _MIPS_INS_SDBBP16 = 509;; -let _MIPS_INS_SDC1 = 510;; -let _MIPS_INS_SDC2 = 511;; -let _MIPS_INS_SDC3 = 512;; -let _MIPS_INS_SDL = 513;; -let _MIPS_INS_SDR = 514;; -let _MIPS_INS_SDXC1 = 515;; -let _MIPS_INS_SEB = 516;; -let _MIPS_INS_SEH = 517;; -let _MIPS_INS_SELEQZ = 518;; -let _MIPS_INS_SELNEZ = 519;; -let _MIPS_INS_SEL = 520;; -let _MIPS_INS_SEQ = 521;; -let _MIPS_INS_SEQI = 522;; -let _MIPS_INS_SH = 523;; -let _MIPS_INS_SH16 = 524;; -let _MIPS_INS_SHF = 525;; -let _MIPS_INS_SHILO = 526;; -let _MIPS_INS_SHILOV = 527;; -let _MIPS_INS_SHLLV = 528;; -let _MIPS_INS_SHLLV_S = 529;; -let _MIPS_INS_SHLL = 530;; -let _MIPS_INS_SHLL_S = 531;; -let _MIPS_INS_SHRAV = 532;; -let _MIPS_INS_SHRAV_R = 533;; -let _MIPS_INS_SHRA = 534;; -let _MIPS_INS_SHRA_R = 535;; -let _MIPS_INS_SHRLV = 536;; -let _MIPS_INS_SHRL = 537;; -let _MIPS_INS_SLDI = 538;; -let _MIPS_INS_SLD = 539;; -let _MIPS_INS_SLL = 540;; -let _MIPS_INS_SLL16 = 541;; -let _MIPS_INS_SLLI = 542;; -let _MIPS_INS_SLLV = 543;; -let _MIPS_INS_SLT = 544;; -let _MIPS_INS_SLTI = 545;; -let _MIPS_INS_SLTIU = 546;; -let _MIPS_INS_SLTU = 547;; -let _MIPS_INS_SNE = 548;; -let _MIPS_INS_SNEI = 549;; -let _MIPS_INS_SPLATI = 550;; -let _MIPS_INS_SPLAT = 551;; -let _MIPS_INS_SRA = 552;; -let _MIPS_INS_SRAI = 553;; -let _MIPS_INS_SRARI = 554;; -let _MIPS_INS_SRAR = 555;; -let _MIPS_INS_SRAV = 556;; -let _MIPS_INS_SRL = 557;; -let _MIPS_INS_SRL16 = 558;; -let _MIPS_INS_SRLI = 559;; -let _MIPS_INS_SRLRI = 560;; -let _MIPS_INS_SRLR = 561;; -let _MIPS_INS_SRLV = 562;; -let _MIPS_INS_SSNOP = 563;; -let _MIPS_INS_ST = 564;; -let _MIPS_INS_SUBQH = 565;; -let _MIPS_INS_SUBQH_R = 566;; -let _MIPS_INS_SUBQ = 567;; -let _MIPS_INS_SUBQ_S = 568;; -let _MIPS_INS_SUBSUS_U = 569;; -let _MIPS_INS_SUBSUU_S = 570;; -let _MIPS_INS_SUBS_S = 571;; -let _MIPS_INS_SUBS_U = 572;; -let _MIPS_INS_SUBU16 = 573;; -let _MIPS_INS_SUBUH = 574;; -let _MIPS_INS_SUBUH_R = 575;; -let _MIPS_INS_SUBU = 576;; -let _MIPS_INS_SUBU_S = 577;; -let _MIPS_INS_SUBVI = 578;; -let _MIPS_INS_SUBV = 579;; -let _MIPS_INS_SUXC1 = 580;; -let _MIPS_INS_SW = 581;; -let _MIPS_INS_SW16 = 582;; -let _MIPS_INS_SWC1 = 583;; -let _MIPS_INS_SWC2 = 584;; -let _MIPS_INS_SWC3 = 585;; -let _MIPS_INS_SWL = 586;; -let _MIPS_INS_SWM16 = 587;; -let _MIPS_INS_SWM32 = 588;; -let _MIPS_INS_SWP = 589;; -let _MIPS_INS_SWR = 590;; -let _MIPS_INS_SWXC1 = 591;; -let _MIPS_INS_SYNC = 592;; -let _MIPS_INS_SYNCI = 593;; -let _MIPS_INS_SYSCALL = 594;; -let _MIPS_INS_TEQ = 595;; -let _MIPS_INS_TEQI = 596;; -let _MIPS_INS_TGE = 597;; -let _MIPS_INS_TGEI = 598;; -let _MIPS_INS_TGEIU = 599;; -let _MIPS_INS_TGEU = 600;; -let _MIPS_INS_TLBP = 601;; -let _MIPS_INS_TLBR = 602;; -let _MIPS_INS_TLBWI = 603;; -let _MIPS_INS_TLBWR = 604;; -let _MIPS_INS_TLT = 605;; -let _MIPS_INS_TLTI = 606;; -let _MIPS_INS_TLTIU = 607;; -let _MIPS_INS_TLTU = 608;; -let _MIPS_INS_TNE = 609;; -let _MIPS_INS_TNEI = 610;; -let _MIPS_INS_TRUNC = 611;; -let _MIPS_INS_V3MULU = 612;; -let _MIPS_INS_VMM0 = 613;; -let _MIPS_INS_VMULU = 614;; -let _MIPS_INS_VSHF = 615;; -let _MIPS_INS_WAIT = 616;; -let _MIPS_INS_WRDSP = 617;; -let _MIPS_INS_WSBH = 618;; -let _MIPS_INS_XOR = 619;; -let _MIPS_INS_XOR16 = 620;; -let _MIPS_INS_XORI = 621;; - -(* some alias instructions *) -let _MIPS_INS_NOP = 622;; -let _MIPS_INS_NEGU = 623;; - -(* special instructions *) -let _MIPS_INS_JALR_HB = 624;; -let _MIPS_INS_JR_HB = 625;; -let _MIPS_INS_ENDING = 626;; +let _MIPS_INS_ABS = 1;; +let _MIPS_INS_ALIGN = 2;; +let _MIPS_INS_BEQL = 3;; +let _MIPS_INS_BGE = 4;; +let _MIPS_INS_BGEL = 5;; +let _MIPS_INS_BGEU = 6;; +let _MIPS_INS_BGEUL = 7;; +let _MIPS_INS_BGT = 8;; +let _MIPS_INS_BGTL = 9;; +let _MIPS_INS_BGTU = 10;; +let _MIPS_INS_BGTUL = 11;; +let _MIPS_INS_BLE = 12;; +let _MIPS_INS_BLEL = 13;; +let _MIPS_INS_BLEU = 14;; +let _MIPS_INS_BLEUL = 15;; +let _MIPS_INS_BLT = 16;; +let _MIPS_INS_BLTL = 17;; +let _MIPS_INS_BLTU = 18;; +let _MIPS_INS_BLTUL = 19;; +let _MIPS_INS_BNEL = 20;; +let _MIPS_INS_B = 21;; +let _MIPS_INS_BEQ = 22;; +let _MIPS_INS_BNE = 23;; +let _MIPS_INS_CFTC1 = 24;; +let _MIPS_INS_CTTC1 = 25;; +let _MIPS_INS_DMUL = 26;; +let _MIPS_INS_DMULO = 27;; +let _MIPS_INS_DMULOU = 28;; +let _MIPS_INS_DROL = 29;; +let _MIPS_INS_DROR = 30;; +let _MIPS_INS_DDIV = 31;; +let _MIPS_INS_DREM = 32;; +let _MIPS_INS_DDIVU = 33;; +let _MIPS_INS_DREMU = 34;; +let _MIPS_INS_JAL = 35;; +let _MIPS_INS_LD = 36;; +let _MIPS_INS_LWM = 37;; +let _MIPS_INS_LA = 38;; +let _MIPS_INS_DLA = 39;; +let _MIPS_INS_LI = 40;; +let _MIPS_INS_DLI = 41;; +let _MIPS_INS_LI_D = 42;; +let _MIPS_INS_LI_S = 43;; +let _MIPS_INS_MFTACX = 44;; +let _MIPS_INS_MFTC0 = 45;; +let _MIPS_INS_MFTC1 = 46;; +let _MIPS_INS_MFTDSP = 47;; +let _MIPS_INS_MFTGPR = 48;; +let _MIPS_INS_MFTHC1 = 49;; +let _MIPS_INS_MFTHI = 50;; +let _MIPS_INS_MFTLO = 51;; +let _MIPS_INS_MTTACX = 52;; +let _MIPS_INS_MTTC0 = 53;; +let _MIPS_INS_MTTC1 = 54;; +let _MIPS_INS_MTTDSP = 55;; +let _MIPS_INS_MTTGPR = 56;; +let _MIPS_INS_MTTHC1 = 57;; +let _MIPS_INS_MTTHI = 58;; +let _MIPS_INS_MTTLO = 59;; +let _MIPS_INS_MUL = 60;; +let _MIPS_INS_MULO = 61;; +let _MIPS_INS_MULOU = 62;; +let _MIPS_INS_NOR = 63;; +let _MIPS_INS_ADDIU = 64;; +let _MIPS_INS_ANDI = 65;; +let _MIPS_INS_SUBU = 66;; +let _MIPS_INS_TRUNC_W_D = 67;; +let _MIPS_INS_TRUNC_W_S = 68;; +let _MIPS_INS_ROL = 69;; +let _MIPS_INS_ROR = 70;; +let _MIPS_INS_S_D = 71;; +let _MIPS_INS_SD = 72;; +let _MIPS_INS_DIV = 73;; +let _MIPS_INS_SEQ = 74;; +let _MIPS_INS_SGE = 75;; +let _MIPS_INS_SGEU = 76;; +let _MIPS_INS_SGT = 77;; +let _MIPS_INS_SGTU = 78;; +let _MIPS_INS_SLE = 79;; +let _MIPS_INS_SLEU = 80;; +let _MIPS_INS_SLT = 81;; +let _MIPS_INS_SLTU = 82;; +let _MIPS_INS_SNE = 83;; +let _MIPS_INS_REM = 84;; +let _MIPS_INS_SWM = 85;; +let _MIPS_INS_SAA = 86;; +let _MIPS_INS_SAAD = 87;; +let _MIPS_INS_DIVU = 88;; +let _MIPS_INS_REMU = 89;; +let _MIPS_INS_ULH = 90;; +let _MIPS_INS_ULHU = 91;; +let _MIPS_INS_ULW = 92;; +let _MIPS_INS_USH = 93;; +let _MIPS_INS_USW = 94;; +let _MIPS_INS_ABSQ_S_PH = 95;; +let _MIPS_INS_ABSQ_S_QB = 96;; +let _MIPS_INS_ABSQ_S_W = 97;; +let _MIPS_INS_ADD = 98;; +let _MIPS_INS_ADDIUPC = 99;; +let _MIPS_INS_ADDIUR1SP = 100;; +let _MIPS_INS_ADDIUR2 = 101;; +let _MIPS_INS_ADDIUS5 = 102;; +let _MIPS_INS_ADDIUSP = 103;; +let _MIPS_INS_ADDQH_PH = 104;; +let _MIPS_INS_ADDQH_R_PH = 105;; +let _MIPS_INS_ADDQH_R_W = 106;; +let _MIPS_INS_ADDQH_W = 107;; +let _MIPS_INS_ADDQ_PH = 108;; +let _MIPS_INS_ADDQ_S_PH = 109;; +let _MIPS_INS_ADDQ_S_W = 110;; +let _MIPS_INS_ADDR_PS = 111;; +let _MIPS_INS_ADDSC = 112;; +let _MIPS_INS_ADDS_A_B = 113;; +let _MIPS_INS_ADDS_A_D = 114;; +let _MIPS_INS_ADDS_A_H = 115;; +let _MIPS_INS_ADDS_A_W = 116;; +let _MIPS_INS_ADDS_S_B = 117;; +let _MIPS_INS_ADDS_S_D = 118;; +let _MIPS_INS_ADDS_S_H = 119;; +let _MIPS_INS_ADDS_S_W = 120;; +let _MIPS_INS_ADDS_U_B = 121;; +let _MIPS_INS_ADDS_U_D = 122;; +let _MIPS_INS_ADDS_U_H = 123;; +let _MIPS_INS_ADDS_U_W = 124;; +let _MIPS_INS_ADDU16 = 125;; +let _MIPS_INS_ADDUH_QB = 126;; +let _MIPS_INS_ADDUH_R_QB = 127;; +let _MIPS_INS_ADDU = 128;; +let _MIPS_INS_ADDU_PH = 129;; +let _MIPS_INS_ADDU_QB = 130;; +let _MIPS_INS_ADDU_S_PH = 131;; +let _MIPS_INS_ADDU_S_QB = 132;; +let _MIPS_INS_ADDVI_B = 133;; +let _MIPS_INS_ADDVI_D = 134;; +let _MIPS_INS_ADDVI_H = 135;; +let _MIPS_INS_ADDVI_W = 136;; +let _MIPS_INS_ADDV_B = 137;; +let _MIPS_INS_ADDV_D = 138;; +let _MIPS_INS_ADDV_H = 139;; +let _MIPS_INS_ADDV_W = 140;; +let _MIPS_INS_ADDWC = 141;; +let _MIPS_INS_ADD_A_B = 142;; +let _MIPS_INS_ADD_A_D = 143;; +let _MIPS_INS_ADD_A_H = 144;; +let _MIPS_INS_ADD_A_W = 145;; +let _MIPS_INS_ADDI = 146;; +let _MIPS_INS_ALUIPC = 147;; +let _MIPS_INS_AND = 148;; +let _MIPS_INS_AND16 = 149;; +let _MIPS_INS_ANDI16 = 150;; +let _MIPS_INS_ANDI_B = 151;; +let _MIPS_INS_AND_V = 152;; +let _MIPS_INS_APPEND = 153;; +let _MIPS_INS_ASUB_S_B = 154;; +let _MIPS_INS_ASUB_S_D = 155;; +let _MIPS_INS_ASUB_S_H = 156;; +let _MIPS_INS_ASUB_S_W = 157;; +let _MIPS_INS_ASUB_U_B = 158;; +let _MIPS_INS_ASUB_U_D = 159;; +let _MIPS_INS_ASUB_U_H = 160;; +let _MIPS_INS_ASUB_U_W = 161;; +let _MIPS_INS_AUI = 162;; +let _MIPS_INS_AUIPC = 163;; +let _MIPS_INS_AVER_S_B = 164;; +let _MIPS_INS_AVER_S_D = 165;; +let _MIPS_INS_AVER_S_H = 166;; +let _MIPS_INS_AVER_S_W = 167;; +let _MIPS_INS_AVER_U_B = 168;; +let _MIPS_INS_AVER_U_D = 169;; +let _MIPS_INS_AVER_U_H = 170;; +let _MIPS_INS_AVER_U_W = 171;; +let _MIPS_INS_AVE_S_B = 172;; +let _MIPS_INS_AVE_S_D = 173;; +let _MIPS_INS_AVE_S_H = 174;; +let _MIPS_INS_AVE_S_W = 175;; +let _MIPS_INS_AVE_U_B = 176;; +let _MIPS_INS_AVE_U_D = 177;; +let _MIPS_INS_AVE_U_H = 178;; +let _MIPS_INS_AVE_U_W = 179;; +let _MIPS_INS_B16 = 180;; +let _MIPS_INS_BADDU = 181;; +let _MIPS_INS_BAL = 182;; +let _MIPS_INS_BALC = 183;; +let _MIPS_INS_BALIGN = 184;; +let _MIPS_INS_BALRSC = 185;; +let _MIPS_INS_BBEQZC = 186;; +let _MIPS_INS_BBIT0 = 187;; +let _MIPS_INS_BBIT032 = 188;; +let _MIPS_INS_BBIT1 = 189;; +let _MIPS_INS_BBIT132 = 190;; +let _MIPS_INS_BBNEZC = 191;; +let _MIPS_INS_BC = 192;; +let _MIPS_INS_BC16 = 193;; +let _MIPS_INS_BC1EQZ = 194;; +let _MIPS_INS_BC1EQZC = 195;; +let _MIPS_INS_BC1F = 196;; +let _MIPS_INS_BC1FL = 197;; +let _MIPS_INS_BC1NEZ = 198;; +let _MIPS_INS_BC1NEZC = 199;; +let _MIPS_INS_BC1T = 200;; +let _MIPS_INS_BC1TL = 201;; +let _MIPS_INS_BC2EQZ = 202;; +let _MIPS_INS_BC2EQZC = 203;; +let _MIPS_INS_BC2NEZ = 204;; +let _MIPS_INS_BC2NEZC = 205;; +let _MIPS_INS_BCLRI_B = 206;; +let _MIPS_INS_BCLRI_D = 207;; +let _MIPS_INS_BCLRI_H = 208;; +let _MIPS_INS_BCLRI_W = 209;; +let _MIPS_INS_BCLR_B = 210;; +let _MIPS_INS_BCLR_D = 211;; +let _MIPS_INS_BCLR_H = 212;; +let _MIPS_INS_BCLR_W = 213;; +let _MIPS_INS_BEQC = 214;; +let _MIPS_INS_BEQIC = 215;; +let _MIPS_INS_BEQZ16 = 216;; +let _MIPS_INS_BEQZALC = 217;; +let _MIPS_INS_BEQZC = 218;; +let _MIPS_INS_BEQZC16 = 219;; +let _MIPS_INS_BGEC = 220;; +let _MIPS_INS_BGEIC = 221;; +let _MIPS_INS_BGEIUC = 222;; +let _MIPS_INS_BGEUC = 223;; +let _MIPS_INS_BGEZ = 224;; +let _MIPS_INS_BGEZAL = 225;; +let _MIPS_INS_BGEZALC = 226;; +let _MIPS_INS_BGEZALL = 227;; +let _MIPS_INS_BGEZALS = 228;; +let _MIPS_INS_BGEZC = 229;; +let _MIPS_INS_BGEZL = 230;; +let _MIPS_INS_BGTZ = 231;; +let _MIPS_INS_BGTZALC = 232;; +let _MIPS_INS_BGTZC = 233;; +let _MIPS_INS_BGTZL = 234;; +let _MIPS_INS_BINSLI_B = 235;; +let _MIPS_INS_BINSLI_D = 236;; +let _MIPS_INS_BINSLI_H = 237;; +let _MIPS_INS_BINSLI_W = 238;; +let _MIPS_INS_BINSL_B = 239;; +let _MIPS_INS_BINSL_D = 240;; +let _MIPS_INS_BINSL_H = 241;; +let _MIPS_INS_BINSL_W = 242;; +let _MIPS_INS_BINSRI_B = 243;; +let _MIPS_INS_BINSRI_D = 244;; +let _MIPS_INS_BINSRI_H = 245;; +let _MIPS_INS_BINSRI_W = 246;; +let _MIPS_INS_BINSR_B = 247;; +let _MIPS_INS_BINSR_D = 248;; +let _MIPS_INS_BINSR_H = 249;; +let _MIPS_INS_BINSR_W = 250;; +let _MIPS_INS_BITREV = 251;; +let _MIPS_INS_BITREVW = 252;; +let _MIPS_INS_BITSWAP = 253;; +let _MIPS_INS_BLEZ = 254;; +let _MIPS_INS_BLEZALC = 255;; +let _MIPS_INS_BLEZC = 256;; +let _MIPS_INS_BLEZL = 257;; +let _MIPS_INS_BLTC = 258;; +let _MIPS_INS_BLTIC = 259;; +let _MIPS_INS_BLTIUC = 260;; +let _MIPS_INS_BLTUC = 261;; +let _MIPS_INS_BLTZ = 262;; +let _MIPS_INS_BLTZAL = 263;; +let _MIPS_INS_BLTZALC = 264;; +let _MIPS_INS_BLTZALL = 265;; +let _MIPS_INS_BLTZALS = 266;; +let _MIPS_INS_BLTZC = 267;; +let _MIPS_INS_BLTZL = 268;; +let _MIPS_INS_BMNZI_B = 269;; +let _MIPS_INS_BMNZ_V = 270;; +let _MIPS_INS_BMZI_B = 271;; +let _MIPS_INS_BMZ_V = 272;; +let _MIPS_INS_BNEC = 273;; +let _MIPS_INS_BNEGI_B = 274;; +let _MIPS_INS_BNEGI_D = 275;; +let _MIPS_INS_BNEGI_H = 276;; +let _MIPS_INS_BNEGI_W = 277;; +let _MIPS_INS_BNEG_B = 278;; +let _MIPS_INS_BNEG_D = 279;; +let _MIPS_INS_BNEG_H = 280;; +let _MIPS_INS_BNEG_W = 281;; +let _MIPS_INS_BNEIC = 282;; +let _MIPS_INS_BNEZ16 = 283;; +let _MIPS_INS_BNEZALC = 284;; +let _MIPS_INS_BNEZC = 285;; +let _MIPS_INS_BNEZC16 = 286;; +let _MIPS_INS_BNVC = 287;; +let _MIPS_INS_BNZ_B = 288;; +let _MIPS_INS_BNZ_D = 289;; +let _MIPS_INS_BNZ_H = 290;; +let _MIPS_INS_BNZ_V = 291;; +let _MIPS_INS_BNZ_W = 292;; +let _MIPS_INS_BOVC = 293;; +let _MIPS_INS_BPOSGE32 = 294;; +let _MIPS_INS_BPOSGE32C = 295;; +let _MIPS_INS_BREAK = 296;; +let _MIPS_INS_BREAK16 = 297;; +let _MIPS_INS_BRSC = 298;; +let _MIPS_INS_BSELI_B = 299;; +let _MIPS_INS_BSEL_V = 300;; +let _MIPS_INS_BSETI_B = 301;; +let _MIPS_INS_BSETI_D = 302;; +let _MIPS_INS_BSETI_H = 303;; +let _MIPS_INS_BSETI_W = 304;; +let _MIPS_INS_BSET_B = 305;; +let _MIPS_INS_BSET_D = 306;; +let _MIPS_INS_BSET_H = 307;; +let _MIPS_INS_BSET_W = 308;; +let _MIPS_INS_BYTEREVW = 309;; +let _MIPS_INS_BZ_B = 310;; +let _MIPS_INS_BZ_D = 311;; +let _MIPS_INS_BZ_H = 312;; +let _MIPS_INS_BZ_V = 313;; +let _MIPS_INS_BZ_W = 314;; +let _MIPS_INS_BEQZ = 315;; +let _MIPS_INS_BNEZ = 316;; +let _MIPS_INS_BTEQZ = 317;; +let _MIPS_INS_BTNEZ = 318;; +let _MIPS_INS_CACHE = 319;; +let _MIPS_INS_CACHEE = 320;; +let _MIPS_INS_CEIL_L_D = 321;; +let _MIPS_INS_CEIL_L_S = 322;; +let _MIPS_INS_CEIL_W_D = 323;; +let _MIPS_INS_CEIL_W_S = 324;; +let _MIPS_INS_CEQI_B = 325;; +let _MIPS_INS_CEQI_D = 326;; +let _MIPS_INS_CEQI_H = 327;; +let _MIPS_INS_CEQI_W = 328;; +let _MIPS_INS_CEQ_B = 329;; +let _MIPS_INS_CEQ_D = 330;; +let _MIPS_INS_CEQ_H = 331;; +let _MIPS_INS_CEQ_W = 332;; +let _MIPS_INS_CFC1 = 333;; +let _MIPS_INS_CFC2 = 334;; +let _MIPS_INS_CFCMSA = 335;; +let _MIPS_INS_CINS = 336;; +let _MIPS_INS_CINS32 = 337;; +let _MIPS_INS_CLASS_D = 338;; +let _MIPS_INS_CLASS_S = 339;; +let _MIPS_INS_CLEI_S_B = 340;; +let _MIPS_INS_CLEI_S_D = 341;; +let _MIPS_INS_CLEI_S_H = 342;; +let _MIPS_INS_CLEI_S_W = 343;; +let _MIPS_INS_CLEI_U_B = 344;; +let _MIPS_INS_CLEI_U_D = 345;; +let _MIPS_INS_CLEI_U_H = 346;; +let _MIPS_INS_CLEI_U_W = 347;; +let _MIPS_INS_CLE_S_B = 348;; +let _MIPS_INS_CLE_S_D = 349;; +let _MIPS_INS_CLE_S_H = 350;; +let _MIPS_INS_CLE_S_W = 351;; +let _MIPS_INS_CLE_U_B = 352;; +let _MIPS_INS_CLE_U_D = 353;; +let _MIPS_INS_CLE_U_H = 354;; +let _MIPS_INS_CLE_U_W = 355;; +let _MIPS_INS_CLO = 356;; +let _MIPS_INS_CLTI_S_B = 357;; +let _MIPS_INS_CLTI_S_D = 358;; +let _MIPS_INS_CLTI_S_H = 359;; +let _MIPS_INS_CLTI_S_W = 360;; +let _MIPS_INS_CLTI_U_B = 361;; +let _MIPS_INS_CLTI_U_D = 362;; +let _MIPS_INS_CLTI_U_H = 363;; +let _MIPS_INS_CLTI_U_W = 364;; +let _MIPS_INS_CLT_S_B = 365;; +let _MIPS_INS_CLT_S_D = 366;; +let _MIPS_INS_CLT_S_H = 367;; +let _MIPS_INS_CLT_S_W = 368;; +let _MIPS_INS_CLT_U_B = 369;; +let _MIPS_INS_CLT_U_D = 370;; +let _MIPS_INS_CLT_U_H = 371;; +let _MIPS_INS_CLT_U_W = 372;; +let _MIPS_INS_CLZ = 373;; +let _MIPS_INS_CMPGDU_EQ_QB = 374;; +let _MIPS_INS_CMPGDU_LE_QB = 375;; +let _MIPS_INS_CMPGDU_LT_QB = 376;; +let _MIPS_INS_CMPGU_EQ_QB = 377;; +let _MIPS_INS_CMPGU_LE_QB = 378;; +let _MIPS_INS_CMPGU_LT_QB = 379;; +let _MIPS_INS_CMPU_EQ_QB = 380;; +let _MIPS_INS_CMPU_LE_QB = 381;; +let _MIPS_INS_CMPU_LT_QB = 382;; +let _MIPS_INS_CMP_AF_D = 383;; +let _MIPS_INS_CMP_AF_S = 384;; +let _MIPS_INS_CMP_EQ_D = 385;; +let _MIPS_INS_CMP_EQ_PH = 386;; +let _MIPS_INS_CMP_EQ_S = 387;; +let _MIPS_INS_CMP_LE_D = 388;; +let _MIPS_INS_CMP_LE_PH = 389;; +let _MIPS_INS_CMP_LE_S = 390;; +let _MIPS_INS_CMP_LT_D = 391;; +let _MIPS_INS_CMP_LT_PH = 392;; +let _MIPS_INS_CMP_LT_S = 393;; +let _MIPS_INS_CMP_SAF_D = 394;; +let _MIPS_INS_CMP_SAF_S = 395;; +let _MIPS_INS_CMP_SEQ_D = 396;; +let _MIPS_INS_CMP_SEQ_S = 397;; +let _MIPS_INS_CMP_SLE_D = 398;; +let _MIPS_INS_CMP_SLE_S = 399;; +let _MIPS_INS_CMP_SLT_D = 400;; +let _MIPS_INS_CMP_SLT_S = 401;; +let _MIPS_INS_CMP_SUEQ_D = 402;; +let _MIPS_INS_CMP_SUEQ_S = 403;; +let _MIPS_INS_CMP_SULE_D = 404;; +let _MIPS_INS_CMP_SULE_S = 405;; +let _MIPS_INS_CMP_SULT_D = 406;; +let _MIPS_INS_CMP_SULT_S = 407;; +let _MIPS_INS_CMP_SUN_D = 408;; +let _MIPS_INS_CMP_SUN_S = 409;; +let _MIPS_INS_CMP_UEQ_D = 410;; +let _MIPS_INS_CMP_UEQ_S = 411;; +let _MIPS_INS_CMP_ULE_D = 412;; +let _MIPS_INS_CMP_ULE_S = 413;; +let _MIPS_INS_CMP_ULT_D = 414;; +let _MIPS_INS_CMP_ULT_S = 415;; +let _MIPS_INS_CMP_UN_D = 416;; +let _MIPS_INS_CMP_UN_S = 417;; +let _MIPS_INS_COPY_S_B = 418;; +let _MIPS_INS_COPY_S_D = 419;; +let _MIPS_INS_COPY_S_H = 420;; +let _MIPS_INS_COPY_S_W = 421;; +let _MIPS_INS_COPY_U_B = 422;; +let _MIPS_INS_COPY_U_H = 423;; +let _MIPS_INS_COPY_U_W = 424;; +let _MIPS_INS_CRC32B = 425;; +let _MIPS_INS_CRC32CB = 426;; +let _MIPS_INS_CRC32CD = 427;; +let _MIPS_INS_CRC32CH = 428;; +let _MIPS_INS_CRC32CW = 429;; +let _MIPS_INS_CRC32D = 430;; +let _MIPS_INS_CRC32H = 431;; +let _MIPS_INS_CRC32W = 432;; +let _MIPS_INS_CTC1 = 433;; +let _MIPS_INS_CTC2 = 434;; +let _MIPS_INS_CTCMSA = 435;; +let _MIPS_INS_CVT_D_S = 436;; +let _MIPS_INS_CVT_D_W = 437;; +let _MIPS_INS_CVT_D_L = 438;; +let _MIPS_INS_CVT_L_D = 439;; +let _MIPS_INS_CVT_L_S = 440;; +let _MIPS_INS_CVT_PS_PW = 441;; +let _MIPS_INS_CVT_PS_S = 442;; +let _MIPS_INS_CVT_PW_PS = 443;; +let _MIPS_INS_CVT_S_D = 444;; +let _MIPS_INS_CVT_S_L = 445;; +let _MIPS_INS_CVT_S_PL = 446;; +let _MIPS_INS_CVT_S_PU = 447;; +let _MIPS_INS_CVT_S_W = 448;; +let _MIPS_INS_CVT_W_D = 449;; +let _MIPS_INS_CVT_W_S = 450;; +let _MIPS_INS_C_EQ_D = 451;; +let _MIPS_INS_C_EQ_S = 452;; +let _MIPS_INS_C_F_D = 453;; +let _MIPS_INS_C_F_S = 454;; +let _MIPS_INS_C_LE_D = 455;; +let _MIPS_INS_C_LE_S = 456;; +let _MIPS_INS_C_LT_D = 457;; +let _MIPS_INS_C_LT_S = 458;; +let _MIPS_INS_C_NGE_D = 459;; +let _MIPS_INS_C_NGE_S = 460;; +let _MIPS_INS_C_NGLE_D = 461;; +let _MIPS_INS_C_NGLE_S = 462;; +let _MIPS_INS_C_NGL_D = 463;; +let _MIPS_INS_C_NGL_S = 464;; +let _MIPS_INS_C_NGT_D = 465;; +let _MIPS_INS_C_NGT_S = 466;; +let _MIPS_INS_C_OLE_D = 467;; +let _MIPS_INS_C_OLE_S = 468;; +let _MIPS_INS_C_OLT_D = 469;; +let _MIPS_INS_C_OLT_S = 470;; +let _MIPS_INS_C_SEQ_D = 471;; +let _MIPS_INS_C_SEQ_S = 472;; +let _MIPS_INS_C_SF_D = 473;; +let _MIPS_INS_C_SF_S = 474;; +let _MIPS_INS_C_UEQ_D = 475;; +let _MIPS_INS_C_UEQ_S = 476;; +let _MIPS_INS_C_ULE_D = 477;; +let _MIPS_INS_C_ULE_S = 478;; +let _MIPS_INS_C_ULT_D = 479;; +let _MIPS_INS_C_ULT_S = 480;; +let _MIPS_INS_C_UN_D = 481;; +let _MIPS_INS_C_UN_S = 482;; +let _MIPS_INS_CMP = 483;; +let _MIPS_INS_CMPI = 484;; +let _MIPS_INS_DADD = 485;; +let _MIPS_INS_DADDI = 486;; +let _MIPS_INS_DADDIU = 487;; +let _MIPS_INS_DADDU = 488;; +let _MIPS_INS_DAHI = 489;; +let _MIPS_INS_DALIGN = 490;; +let _MIPS_INS_DATI = 491;; +let _MIPS_INS_DAUI = 492;; +let _MIPS_INS_DBITSWAP = 493;; +let _MIPS_INS_DCLO = 494;; +let _MIPS_INS_DCLZ = 495;; +let _MIPS_INS_DERET = 496;; +let _MIPS_INS_DEXT = 497;; +let _MIPS_INS_DEXTM = 498;; +let _MIPS_INS_DEXTU = 499;; +let _MIPS_INS_DI = 500;; +let _MIPS_INS_DINS = 501;; +let _MIPS_INS_DINSM = 502;; +let _MIPS_INS_DINSU = 503;; +let _MIPS_INS_DIV_S_B = 504;; +let _MIPS_INS_DIV_S_D = 505;; +let _MIPS_INS_DIV_S_H = 506;; +let _MIPS_INS_DIV_S_W = 507;; +let _MIPS_INS_DIV_U_B = 508;; +let _MIPS_INS_DIV_U_D = 509;; +let _MIPS_INS_DIV_U_H = 510;; +let _MIPS_INS_DIV_U_W = 511;; +let _MIPS_INS_DLSA = 512;; +let _MIPS_INS_DMFC0 = 513;; +let _MIPS_INS_DMFC1 = 514;; +let _MIPS_INS_DMFC2 = 515;; +let _MIPS_INS_DMFGC0 = 516;; +let _MIPS_INS_DMOD = 517;; +let _MIPS_INS_DMODU = 518;; +let _MIPS_INS_DMT = 519;; +let _MIPS_INS_DMTC0 = 520;; +let _MIPS_INS_DMTC1 = 521;; +let _MIPS_INS_DMTC2 = 522;; +let _MIPS_INS_DMTGC0 = 523;; +let _MIPS_INS_DMUH = 524;; +let _MIPS_INS_DMUHU = 525;; +let _MIPS_INS_DMULT = 526;; +let _MIPS_INS_DMULTU = 527;; +let _MIPS_INS_DMULU = 528;; +let _MIPS_INS_DOTP_S_D = 529;; +let _MIPS_INS_DOTP_S_H = 530;; +let _MIPS_INS_DOTP_S_W = 531;; +let _MIPS_INS_DOTP_U_D = 532;; +let _MIPS_INS_DOTP_U_H = 533;; +let _MIPS_INS_DOTP_U_W = 534;; +let _MIPS_INS_DPADD_S_D = 535;; +let _MIPS_INS_DPADD_S_H = 536;; +let _MIPS_INS_DPADD_S_W = 537;; +let _MIPS_INS_DPADD_U_D = 538;; +let _MIPS_INS_DPADD_U_H = 539;; +let _MIPS_INS_DPADD_U_W = 540;; +let _MIPS_INS_DPAQX_SA_W_PH = 541;; +let _MIPS_INS_DPAQX_S_W_PH = 542;; +let _MIPS_INS_DPAQ_SA_L_W = 543;; +let _MIPS_INS_DPAQ_S_W_PH = 544;; +let _MIPS_INS_DPAU_H_QBL = 545;; +let _MIPS_INS_DPAU_H_QBR = 546;; +let _MIPS_INS_DPAX_W_PH = 547;; +let _MIPS_INS_DPA_W_PH = 548;; +let _MIPS_INS_DPOP = 549;; +let _MIPS_INS_DPSQX_SA_W_PH = 550;; +let _MIPS_INS_DPSQX_S_W_PH = 551;; +let _MIPS_INS_DPSQ_SA_L_W = 552;; +let _MIPS_INS_DPSQ_S_W_PH = 553;; +let _MIPS_INS_DPSUB_S_D = 554;; +let _MIPS_INS_DPSUB_S_H = 555;; +let _MIPS_INS_DPSUB_S_W = 556;; +let _MIPS_INS_DPSUB_U_D = 557;; +let _MIPS_INS_DPSUB_U_H = 558;; +let _MIPS_INS_DPSUB_U_W = 559;; +let _MIPS_INS_DPSU_H_QBL = 560;; +let _MIPS_INS_DPSU_H_QBR = 561;; +let _MIPS_INS_DPSX_W_PH = 562;; +let _MIPS_INS_DPS_W_PH = 563;; +let _MIPS_INS_DROTR = 564;; +let _MIPS_INS_DROTR32 = 565;; +let _MIPS_INS_DROTRV = 566;; +let _MIPS_INS_DSBH = 567;; +let _MIPS_INS_DSHD = 568;; +let _MIPS_INS_DSLL = 569;; +let _MIPS_INS_DSLL32 = 570;; +let _MIPS_INS_DSLLV = 571;; +let _MIPS_INS_DSRA = 572;; +let _MIPS_INS_DSRA32 = 573;; +let _MIPS_INS_DSRAV = 574;; +let _MIPS_INS_DSRL = 575;; +let _MIPS_INS_DSRL32 = 576;; +let _MIPS_INS_DSRLV = 577;; +let _MIPS_INS_DSUB = 578;; +let _MIPS_INS_DSUBU = 579;; +let _MIPS_INS_DVP = 580;; +let _MIPS_INS_DVPE = 581;; +let _MIPS_INS_EHB = 582;; +let _MIPS_INS_EI = 583;; +let _MIPS_INS_EMT = 584;; +let _MIPS_INS_ERET = 585;; +let _MIPS_INS_ERETNC = 586;; +let _MIPS_INS_EVP = 587;; +let _MIPS_INS_EVPE = 588;; +let _MIPS_INS_EXT = 589;; +let _MIPS_INS_EXTP = 590;; +let _MIPS_INS_EXTPDP = 591;; +let _MIPS_INS_EXTPDPV = 592;; +let _MIPS_INS_EXTPV = 593;; +let _MIPS_INS_EXTRV_RS_W = 594;; +let _MIPS_INS_EXTRV_R_W = 595;; +let _MIPS_INS_EXTRV_S_H = 596;; +let _MIPS_INS_EXTRV_W = 597;; +let _MIPS_INS_EXTR_RS_W = 598;; +let _MIPS_INS_EXTR_R_W = 599;; +let _MIPS_INS_EXTR_S_H = 600;; +let _MIPS_INS_EXTR_W = 601;; +let _MIPS_INS_EXTS = 602;; +let _MIPS_INS_EXTS32 = 603;; +let _MIPS_INS_EXTW = 604;; +let _MIPS_INS_ABS_D = 605;; +let _MIPS_INS_ABS_S = 606;; +let _MIPS_INS_FADD_D = 607;; +let _MIPS_INS_ADD_D = 608;; +let _MIPS_INS_ADD_PS = 609;; +let _MIPS_INS_ADD_S = 610;; +let _MIPS_INS_FADD_W = 611;; +let _MIPS_INS_FCAF_D = 612;; +let _MIPS_INS_FCAF_W = 613;; +let _MIPS_INS_FCEQ_D = 614;; +let _MIPS_INS_FCEQ_W = 615;; +let _MIPS_INS_FCLASS_D = 616;; +let _MIPS_INS_FCLASS_W = 617;; +let _MIPS_INS_FCLE_D = 618;; +let _MIPS_INS_FCLE_W = 619;; +let _MIPS_INS_FCLT_D = 620;; +let _MIPS_INS_FCLT_W = 621;; +let _MIPS_INS_FCNE_D = 622;; +let _MIPS_INS_FCNE_W = 623;; +let _MIPS_INS_FCOR_D = 624;; +let _MIPS_INS_FCOR_W = 625;; +let _MIPS_INS_FCUEQ_D = 626;; +let _MIPS_INS_FCUEQ_W = 627;; +let _MIPS_INS_FCULE_D = 628;; +let _MIPS_INS_FCULE_W = 629;; +let _MIPS_INS_FCULT_D = 630;; +let _MIPS_INS_FCULT_W = 631;; +let _MIPS_INS_FCUNE_D = 632;; +let _MIPS_INS_FCUNE_W = 633;; +let _MIPS_INS_FCUN_D = 634;; +let _MIPS_INS_FCUN_W = 635;; +let _MIPS_INS_FDIV_D = 636;; +let _MIPS_INS_DIV_D = 637;; +let _MIPS_INS_DIV_S = 638;; +let _MIPS_INS_FDIV_W = 639;; +let _MIPS_INS_FEXDO_H = 640;; +let _MIPS_INS_FEXDO_W = 641;; +let _MIPS_INS_FEXP2_D = 642;; +let _MIPS_INS_FEXP2_W = 643;; +let _MIPS_INS_FEXUPL_D = 644;; +let _MIPS_INS_FEXUPL_W = 645;; +let _MIPS_INS_FEXUPR_D = 646;; +let _MIPS_INS_FEXUPR_W = 647;; +let _MIPS_INS_FFINT_S_D = 648;; +let _MIPS_INS_FFINT_S_W = 649;; +let _MIPS_INS_FFINT_U_D = 650;; +let _MIPS_INS_FFINT_U_W = 651;; +let _MIPS_INS_FFQL_D = 652;; +let _MIPS_INS_FFQL_W = 653;; +let _MIPS_INS_FFQR_D = 654;; +let _MIPS_INS_FFQR_W = 655;; +let _MIPS_INS_FILL_B = 656;; +let _MIPS_INS_FILL_D = 657;; +let _MIPS_INS_FILL_H = 658;; +let _MIPS_INS_FILL_W = 659;; +let _MIPS_INS_FLOG2_D = 660;; +let _MIPS_INS_FLOG2_W = 661;; +let _MIPS_INS_FLOOR_L_D = 662;; +let _MIPS_INS_FLOOR_L_S = 663;; +let _MIPS_INS_FLOOR_W_D = 664;; +let _MIPS_INS_FLOOR_W_S = 665;; +let _MIPS_INS_FMADD_D = 666;; +let _MIPS_INS_FMADD_W = 667;; +let _MIPS_INS_FMAX_A_D = 668;; +let _MIPS_INS_FMAX_A_W = 669;; +let _MIPS_INS_FMAX_D = 670;; +let _MIPS_INS_FMAX_W = 671;; +let _MIPS_INS_FMIN_A_D = 672;; +let _MIPS_INS_FMIN_A_W = 673;; +let _MIPS_INS_FMIN_D = 674;; +let _MIPS_INS_FMIN_W = 675;; +let _MIPS_INS_MOV_D = 676;; +let _MIPS_INS_MOV_S = 677;; +let _MIPS_INS_FMSUB_D = 678;; +let _MIPS_INS_FMSUB_W = 679;; +let _MIPS_INS_FMUL_D = 680;; +let _MIPS_INS_MUL_D = 681;; +let _MIPS_INS_MUL_PS = 682;; +let _MIPS_INS_MUL_S = 683;; +let _MIPS_INS_FMUL_W = 684;; +let _MIPS_INS_NEG_D = 685;; +let _MIPS_INS_NEG_S = 686;; +let _MIPS_INS_FORK = 687;; +let _MIPS_INS_FRCP_D = 688;; +let _MIPS_INS_FRCP_W = 689;; +let _MIPS_INS_FRINT_D = 690;; +let _MIPS_INS_FRINT_W = 691;; +let _MIPS_INS_FRSQRT_D = 692;; +let _MIPS_INS_FRSQRT_W = 693;; +let _MIPS_INS_FSAF_D = 694;; +let _MIPS_INS_FSAF_W = 695;; +let _MIPS_INS_FSEQ_D = 696;; +let _MIPS_INS_FSEQ_W = 697;; +let _MIPS_INS_FSLE_D = 698;; +let _MIPS_INS_FSLE_W = 699;; +let _MIPS_INS_FSLT_D = 700;; +let _MIPS_INS_FSLT_W = 701;; +let _MIPS_INS_FSNE_D = 702;; +let _MIPS_INS_FSNE_W = 703;; +let _MIPS_INS_FSOR_D = 704;; +let _MIPS_INS_FSOR_W = 705;; +let _MIPS_INS_FSQRT_D = 706;; +let _MIPS_INS_SQRT_D = 707;; +let _MIPS_INS_SQRT_S = 708;; +let _MIPS_INS_FSQRT_W = 709;; +let _MIPS_INS_FSUB_D = 710;; +let _MIPS_INS_SUB_D = 711;; +let _MIPS_INS_SUB_PS = 712;; +let _MIPS_INS_SUB_S = 713;; +let _MIPS_INS_FSUB_W = 714;; +let _MIPS_INS_FSUEQ_D = 715;; +let _MIPS_INS_FSUEQ_W = 716;; +let _MIPS_INS_FSULE_D = 717;; +let _MIPS_INS_FSULE_W = 718;; +let _MIPS_INS_FSULT_D = 719;; +let _MIPS_INS_FSULT_W = 720;; +let _MIPS_INS_FSUNE_D = 721;; +let _MIPS_INS_FSUNE_W = 722;; +let _MIPS_INS_FSUN_D = 723;; +let _MIPS_INS_FSUN_W = 724;; +let _MIPS_INS_FTINT_S_D = 725;; +let _MIPS_INS_FTINT_S_W = 726;; +let _MIPS_INS_FTINT_U_D = 727;; +let _MIPS_INS_FTINT_U_W = 728;; +let _MIPS_INS_FTQ_H = 729;; +let _MIPS_INS_FTQ_W = 730;; +let _MIPS_INS_FTRUNC_S_D = 731;; +let _MIPS_INS_FTRUNC_S_W = 732;; +let _MIPS_INS_FTRUNC_U_D = 733;; +let _MIPS_INS_FTRUNC_U_W = 734;; +let _MIPS_INS_GINVI = 735;; +let _MIPS_INS_GINVT = 736;; +let _MIPS_INS_HADD_S_D = 737;; +let _MIPS_INS_HADD_S_H = 738;; +let _MIPS_INS_HADD_S_W = 739;; +let _MIPS_INS_HADD_U_D = 740;; +let _MIPS_INS_HADD_U_H = 741;; +let _MIPS_INS_HADD_U_W = 742;; +let _MIPS_INS_HSUB_S_D = 743;; +let _MIPS_INS_HSUB_S_H = 744;; +let _MIPS_INS_HSUB_S_W = 745;; +let _MIPS_INS_HSUB_U_D = 746;; +let _MIPS_INS_HSUB_U_H = 747;; +let _MIPS_INS_HSUB_U_W = 748;; +let _MIPS_INS_HYPCALL = 749;; +let _MIPS_INS_ILVEV_B = 750;; +let _MIPS_INS_ILVEV_D = 751;; +let _MIPS_INS_ILVEV_H = 752;; +let _MIPS_INS_ILVEV_W = 753;; +let _MIPS_INS_ILVL_B = 754;; +let _MIPS_INS_ILVL_D = 755;; +let _MIPS_INS_ILVL_H = 756;; +let _MIPS_INS_ILVL_W = 757;; +let _MIPS_INS_ILVOD_B = 758;; +let _MIPS_INS_ILVOD_D = 759;; +let _MIPS_INS_ILVOD_H = 760;; +let _MIPS_INS_ILVOD_W = 761;; +let _MIPS_INS_ILVR_B = 762;; +let _MIPS_INS_ILVR_D = 763;; +let _MIPS_INS_ILVR_H = 764;; +let _MIPS_INS_ILVR_W = 765;; +let _MIPS_INS_INS = 766;; +let _MIPS_INS_INSERT_B = 767;; +let _MIPS_INS_INSERT_D = 768;; +let _MIPS_INS_INSERT_H = 769;; +let _MIPS_INS_INSERT_W = 770;; +let _MIPS_INS_INSV = 771;; +let _MIPS_INS_INSVE_B = 772;; +let _MIPS_INS_INSVE_D = 773;; +let _MIPS_INS_INSVE_H = 774;; +let _MIPS_INS_INSVE_W = 775;; +let _MIPS_INS_J = 776;; +let _MIPS_INS_JALR = 777;; +let _MIPS_INS_JALRC = 778;; +let _MIPS_INS_JALRC_HB = 779;; +let _MIPS_INS_JALRS16 = 780;; +let _MIPS_INS_JALRS = 781;; +let _MIPS_INS_JALR_HB = 782;; +let _MIPS_INS_JALS = 783;; +let _MIPS_INS_JALX = 784;; +let _MIPS_INS_JIALC = 785;; +let _MIPS_INS_JIC = 786;; +let _MIPS_INS_JR = 787;; +let _MIPS_INS_JR16 = 788;; +let _MIPS_INS_JRADDIUSP = 789;; +let _MIPS_INS_JRC = 790;; +let _MIPS_INS_JRC16 = 791;; +let _MIPS_INS_JRCADDIUSP = 792;; +let _MIPS_INS_JR_HB = 793;; +let _MIPS_INS_LAPC_H = 794;; +let _MIPS_INS_LAPC_B = 795;; +let _MIPS_INS_LB = 796;; +let _MIPS_INS_LBE = 797;; +let _MIPS_INS_LBU16 = 798;; +let _MIPS_INS_LBU = 799;; +let _MIPS_INS_LBUX = 800;; +let _MIPS_INS_LBX = 801;; +let _MIPS_INS_LBUE = 802;; +let _MIPS_INS_LDC1 = 803;; +let _MIPS_INS_LDC2 = 804;; +let _MIPS_INS_LDC3 = 805;; +let _MIPS_INS_LDI_B = 806;; +let _MIPS_INS_LDI_D = 807;; +let _MIPS_INS_LDI_H = 808;; +let _MIPS_INS_LDI_W = 809;; +let _MIPS_INS_LDL = 810;; +let _MIPS_INS_LDPC = 811;; +let _MIPS_INS_LDR = 812;; +let _MIPS_INS_LDXC1 = 813;; +let _MIPS_INS_LD_B = 814;; +let _MIPS_INS_LD_D = 815;; +let _MIPS_INS_LD_H = 816;; +let _MIPS_INS_LD_W = 817;; +let _MIPS_INS_LH = 818;; +let _MIPS_INS_LHE = 819;; +let _MIPS_INS_LHU16 = 820;; +let _MIPS_INS_LHU = 821;; +let _MIPS_INS_LHUXS = 822;; +let _MIPS_INS_LHUX = 823;; +let _MIPS_INS_LHX = 824;; +let _MIPS_INS_LHXS = 825;; +let _MIPS_INS_LHUE = 826;; +let _MIPS_INS_LI16 = 827;; +let _MIPS_INS_LL = 828;; +let _MIPS_INS_LLD = 829;; +let _MIPS_INS_LLE = 830;; +let _MIPS_INS_LLWP = 831;; +let _MIPS_INS_LSA = 832;; +let _MIPS_INS_LUI = 833;; +let _MIPS_INS_LUXC1 = 834;; +let _MIPS_INS_LW = 835;; +let _MIPS_INS_LW16 = 836;; +let _MIPS_INS_LWC1 = 837;; +let _MIPS_INS_LWC2 = 838;; +let _MIPS_INS_LWC3 = 839;; +let _MIPS_INS_LWE = 840;; +let _MIPS_INS_LWL = 841;; +let _MIPS_INS_LWLE = 842;; +let _MIPS_INS_LWM16 = 843;; +let _MIPS_INS_LWM32 = 844;; +let _MIPS_INS_LWPC = 845;; +let _MIPS_INS_LWP = 846;; +let _MIPS_INS_LWR = 847;; +let _MIPS_INS_LWRE = 848;; +let _MIPS_INS_LWUPC = 849;; +let _MIPS_INS_LWU = 850;; +let _MIPS_INS_LWX = 851;; +let _MIPS_INS_LWXC1 = 852;; +let _MIPS_INS_LWXS = 853;; +let _MIPS_INS_MADD = 854;; +let _MIPS_INS_MADDF_D = 855;; +let _MIPS_INS_MADDF_S = 856;; +let _MIPS_INS_MADDR_Q_H = 857;; +let _MIPS_INS_MADDR_Q_W = 858;; +let _MIPS_INS_MADDU = 859;; +let _MIPS_INS_MADDV_B = 860;; +let _MIPS_INS_MADDV_D = 861;; +let _MIPS_INS_MADDV_H = 862;; +let _MIPS_INS_MADDV_W = 863;; +let _MIPS_INS_MADD_D = 864;; +let _MIPS_INS_MADD_Q_H = 865;; +let _MIPS_INS_MADD_Q_W = 866;; +let _MIPS_INS_MADD_S = 867;; +let _MIPS_INS_MAQ_SA_W_PHL = 868;; +let _MIPS_INS_MAQ_SA_W_PHR = 869;; +let _MIPS_INS_MAQ_S_W_PHL = 870;; +let _MIPS_INS_MAQ_S_W_PHR = 871;; +let _MIPS_INS_MAXA_D = 872;; +let _MIPS_INS_MAXA_S = 873;; +let _MIPS_INS_MAXI_S_B = 874;; +let _MIPS_INS_MAXI_S_D = 875;; +let _MIPS_INS_MAXI_S_H = 876;; +let _MIPS_INS_MAXI_S_W = 877;; +let _MIPS_INS_MAXI_U_B = 878;; +let _MIPS_INS_MAXI_U_D = 879;; +let _MIPS_INS_MAXI_U_H = 880;; +let _MIPS_INS_MAXI_U_W = 881;; +let _MIPS_INS_MAX_A_B = 882;; +let _MIPS_INS_MAX_A_D = 883;; +let _MIPS_INS_MAX_A_H = 884;; +let _MIPS_INS_MAX_A_W = 885;; +let _MIPS_INS_MAX_D = 886;; +let _MIPS_INS_MAX_S = 887;; +let _MIPS_INS_MAX_S_B = 888;; +let _MIPS_INS_MAX_S_D = 889;; +let _MIPS_INS_MAX_S_H = 890;; +let _MIPS_INS_MAX_S_W = 891;; +let _MIPS_INS_MAX_U_B = 892;; +let _MIPS_INS_MAX_U_D = 893;; +let _MIPS_INS_MAX_U_H = 894;; +let _MIPS_INS_MAX_U_W = 895;; +let _MIPS_INS_MFC0 = 896;; +let _MIPS_INS_MFC1 = 897;; +let _MIPS_INS_MFC2 = 898;; +let _MIPS_INS_MFGC0 = 899;; +let _MIPS_INS_MFHC0 = 900;; +let _MIPS_INS_MFHC1 = 901;; +let _MIPS_INS_MFHC2 = 902;; +let _MIPS_INS_MFHGC0 = 903;; +let _MIPS_INS_MFHI = 904;; +let _MIPS_INS_MFHI16 = 905;; +let _MIPS_INS_MFLO = 906;; +let _MIPS_INS_MFLO16 = 907;; +let _MIPS_INS_MFTR = 908;; +let _MIPS_INS_MINA_D = 909;; +let _MIPS_INS_MINA_S = 910;; +let _MIPS_INS_MINI_S_B = 911;; +let _MIPS_INS_MINI_S_D = 912;; +let _MIPS_INS_MINI_S_H = 913;; +let _MIPS_INS_MINI_S_W = 914;; +let _MIPS_INS_MINI_U_B = 915;; +let _MIPS_INS_MINI_U_D = 916;; +let _MIPS_INS_MINI_U_H = 917;; +let _MIPS_INS_MINI_U_W = 918;; +let _MIPS_INS_MIN_A_B = 919;; +let _MIPS_INS_MIN_A_D = 920;; +let _MIPS_INS_MIN_A_H = 921;; +let _MIPS_INS_MIN_A_W = 922;; +let _MIPS_INS_MIN_D = 923;; +let _MIPS_INS_MIN_S = 924;; +let _MIPS_INS_MIN_S_B = 925;; +let _MIPS_INS_MIN_S_D = 926;; +let _MIPS_INS_MIN_S_H = 927;; +let _MIPS_INS_MIN_S_W = 928;; +let _MIPS_INS_MIN_U_B = 929;; +let _MIPS_INS_MIN_U_D = 930;; +let _MIPS_INS_MIN_U_H = 931;; +let _MIPS_INS_MIN_U_W = 932;; +let _MIPS_INS_MOD = 933;; +let _MIPS_INS_MODSUB = 934;; +let _MIPS_INS_MODU = 935;; +let _MIPS_INS_MOD_S_B = 936;; +let _MIPS_INS_MOD_S_D = 937;; +let _MIPS_INS_MOD_S_H = 938;; +let _MIPS_INS_MOD_S_W = 939;; +let _MIPS_INS_MOD_U_B = 940;; +let _MIPS_INS_MOD_U_D = 941;; +let _MIPS_INS_MOD_U_H = 942;; +let _MIPS_INS_MOD_U_W = 943;; +let _MIPS_INS_MOVE = 944;; +let _MIPS_INS_MOVE16 = 945;; +let _MIPS_INS_MOVE_BALC = 946;; +let _MIPS_INS_MOVEP = 947;; +let _MIPS_INS_MOVE_V = 948;; +let _MIPS_INS_MOVF_D = 949;; +let _MIPS_INS_MOVF = 950;; +let _MIPS_INS_MOVF_S = 951;; +let _MIPS_INS_MOVN_D = 952;; +let _MIPS_INS_MOVN = 953;; +let _MIPS_INS_MOVN_S = 954;; +let _MIPS_INS_MOVT_D = 955;; +let _MIPS_INS_MOVT = 956;; +let _MIPS_INS_MOVT_S = 957;; +let _MIPS_INS_MOVZ_D = 958;; +let _MIPS_INS_MOVZ = 959;; +let _MIPS_INS_MOVZ_S = 960;; +let _MIPS_INS_MSUB = 961;; +let _MIPS_INS_MSUBF_D = 962;; +let _MIPS_INS_MSUBF_S = 963;; +let _MIPS_INS_MSUBR_Q_H = 964;; +let _MIPS_INS_MSUBR_Q_W = 965;; +let _MIPS_INS_MSUBU = 966;; +let _MIPS_INS_MSUBV_B = 967;; +let _MIPS_INS_MSUBV_D = 968;; +let _MIPS_INS_MSUBV_H = 969;; +let _MIPS_INS_MSUBV_W = 970;; +let _MIPS_INS_MSUB_D = 971;; +let _MIPS_INS_MSUB_Q_H = 972;; +let _MIPS_INS_MSUB_Q_W = 973;; +let _MIPS_INS_MSUB_S = 974;; +let _MIPS_INS_MTC0 = 975;; +let _MIPS_INS_MTC1 = 976;; +let _MIPS_INS_MTC2 = 977;; +let _MIPS_INS_MTGC0 = 978;; +let _MIPS_INS_MTHC0 = 979;; +let _MIPS_INS_MTHC1 = 980;; +let _MIPS_INS_MTHC2 = 981;; +let _MIPS_INS_MTHGC0 = 982;; +let _MIPS_INS_MTHI = 983;; +let _MIPS_INS_MTHLIP = 984;; +let _MIPS_INS_MTLO = 985;; +let _MIPS_INS_MTM0 = 986;; +let _MIPS_INS_MTM1 = 987;; +let _MIPS_INS_MTM2 = 988;; +let _MIPS_INS_MTP0 = 989;; +let _MIPS_INS_MTP1 = 990;; +let _MIPS_INS_MTP2 = 991;; +let _MIPS_INS_MTTR = 992;; +let _MIPS_INS_MUH = 993;; +let _MIPS_INS_MUHU = 994;; +let _MIPS_INS_MULEQ_S_W_PHL = 995;; +let _MIPS_INS_MULEQ_S_W_PHR = 996;; +let _MIPS_INS_MULEU_S_PH_QBL = 997;; +let _MIPS_INS_MULEU_S_PH_QBR = 998;; +let _MIPS_INS_MULQ_RS_PH = 999;; +let _MIPS_INS_MULQ_RS_W = 1000;; +let _MIPS_INS_MULQ_S_PH = 1001;; +let _MIPS_INS_MULQ_S_W = 1002;; +let _MIPS_INS_MULR_PS = 1003;; +let _MIPS_INS_MULR_Q_H = 1004;; +let _MIPS_INS_MULR_Q_W = 1005;; +let _MIPS_INS_MULSAQ_S_W_PH = 1006;; +let _MIPS_INS_MULSA_W_PH = 1007;; +let _MIPS_INS_MULT = 1008;; +let _MIPS_INS_MULTU = 1009;; +let _MIPS_INS_MULU = 1010;; +let _MIPS_INS_MULV_B = 1011;; +let _MIPS_INS_MULV_D = 1012;; +let _MIPS_INS_MULV_H = 1013;; +let _MIPS_INS_MULV_W = 1014;; +let _MIPS_INS_MUL_PH = 1015;; +let _MIPS_INS_MUL_Q_H = 1016;; +let _MIPS_INS_MUL_Q_W = 1017;; +let _MIPS_INS_MUL_S_PH = 1018;; +let _MIPS_INS_NLOC_B = 1019;; +let _MIPS_INS_NLOC_D = 1020;; +let _MIPS_INS_NLOC_H = 1021;; +let _MIPS_INS_NLOC_W = 1022;; +let _MIPS_INS_NLZC_B = 1023;; +let _MIPS_INS_NLZC_D = 1024;; +let _MIPS_INS_NLZC_H = 1025;; +let _MIPS_INS_NLZC_W = 1026;; +let _MIPS_INS_NMADD_D = 1027;; +let _MIPS_INS_NMADD_S = 1028;; +let _MIPS_INS_NMSUB_D = 1029;; +let _MIPS_INS_NMSUB_S = 1030;; +let _MIPS_INS_NOP32 = 1031;; +let _MIPS_INS_NOP = 1032;; +let _MIPS_INS_NORI_B = 1033;; +let _MIPS_INS_NOR_V = 1034;; +let _MIPS_INS_NOT16 = 1035;; +let _MIPS_INS_NOT = 1036;; +let _MIPS_INS_NEG = 1037;; +let _MIPS_INS_OR = 1038;; +let _MIPS_INS_OR16 = 1039;; +let _MIPS_INS_ORI_B = 1040;; +let _MIPS_INS_ORI = 1041;; +let _MIPS_INS_OR_V = 1042;; +let _MIPS_INS_PACKRL_PH = 1043;; +let _MIPS_INS_PAUSE = 1044;; +let _MIPS_INS_PCKEV_B = 1045;; +let _MIPS_INS_PCKEV_D = 1046;; +let _MIPS_INS_PCKEV_H = 1047;; +let _MIPS_INS_PCKEV_W = 1048;; +let _MIPS_INS_PCKOD_B = 1049;; +let _MIPS_INS_PCKOD_D = 1050;; +let _MIPS_INS_PCKOD_H = 1051;; +let _MIPS_INS_PCKOD_W = 1052;; +let _MIPS_INS_PCNT_B = 1053;; +let _MIPS_INS_PCNT_D = 1054;; +let _MIPS_INS_PCNT_H = 1055;; +let _MIPS_INS_PCNT_W = 1056;; +let _MIPS_INS_PICK_PH = 1057;; +let _MIPS_INS_PICK_QB = 1058;; +let _MIPS_INS_PLL_PS = 1059;; +let _MIPS_INS_PLU_PS = 1060;; +let _MIPS_INS_POP = 1061;; +let _MIPS_INS_PRECEQU_PH_QBL = 1062;; +let _MIPS_INS_PRECEQU_PH_QBLA = 1063;; +let _MIPS_INS_PRECEQU_PH_QBR = 1064;; +let _MIPS_INS_PRECEQU_PH_QBRA = 1065;; +let _MIPS_INS_PRECEQ_W_PHL = 1066;; +let _MIPS_INS_PRECEQ_W_PHR = 1067;; +let _MIPS_INS_PRECEU_PH_QBL = 1068;; +let _MIPS_INS_PRECEU_PH_QBLA = 1069;; +let _MIPS_INS_PRECEU_PH_QBR = 1070;; +let _MIPS_INS_PRECEU_PH_QBRA = 1071;; +let _MIPS_INS_PRECRQU_S_QB_PH = 1072;; +let _MIPS_INS_PRECRQ_PH_W = 1073;; +let _MIPS_INS_PRECRQ_QB_PH = 1074;; +let _MIPS_INS_PRECRQ_RS_PH_W = 1075;; +let _MIPS_INS_PRECR_QB_PH = 1076;; +let _MIPS_INS_PRECR_SRA_PH_W = 1077;; +let _MIPS_INS_PRECR_SRA_R_PH_W = 1078;; +let _MIPS_INS_PREF = 1079;; +let _MIPS_INS_PREFE = 1080;; +let _MIPS_INS_PREFX = 1081;; +let _MIPS_INS_PREPEND = 1082;; +let _MIPS_INS_PUL_PS = 1083;; +let _MIPS_INS_PUU_PS = 1084;; +let _MIPS_INS_RADDU_W_QB = 1085;; +let _MIPS_INS_RDDSP = 1086;; +let _MIPS_INS_RDHWR = 1087;; +let _MIPS_INS_RDPGPR = 1088;; +let _MIPS_INS_RECIP_D = 1089;; +let _MIPS_INS_RECIP_S = 1090;; +let _MIPS_INS_REPLV_PH = 1091;; +let _MIPS_INS_REPLV_QB = 1092;; +let _MIPS_INS_REPL_PH = 1093;; +let _MIPS_INS_REPL_QB = 1094;; +let _MIPS_INS_RESTORE_JRC = 1095;; +let _MIPS_INS_RESTORE = 1096;; +let _MIPS_INS_RINT_D = 1097;; +let _MIPS_INS_RINT_S = 1098;; +let _MIPS_INS_ROTR = 1099;; +let _MIPS_INS_ROTRV = 1100;; +let _MIPS_INS_ROTX = 1101;; +let _MIPS_INS_ROUND_L_D = 1102;; +let _MIPS_INS_ROUND_L_S = 1103;; +let _MIPS_INS_ROUND_W_D = 1104;; +let _MIPS_INS_ROUND_W_S = 1105;; +let _MIPS_INS_RSQRT_D = 1106;; +let _MIPS_INS_RSQRT_S = 1107;; +let _MIPS_INS_SAT_S_B = 1108;; +let _MIPS_INS_SAT_S_D = 1109;; +let _MIPS_INS_SAT_S_H = 1110;; +let _MIPS_INS_SAT_S_W = 1111;; +let _MIPS_INS_SAT_U_B = 1112;; +let _MIPS_INS_SAT_U_D = 1113;; +let _MIPS_INS_SAT_U_H = 1114;; +let _MIPS_INS_SAT_U_W = 1115;; +let _MIPS_INS_SAVE = 1116;; +let _MIPS_INS_SB = 1117;; +let _MIPS_INS_SB16 = 1118;; +let _MIPS_INS_SBE = 1119;; +let _MIPS_INS_SBX = 1120;; +let _MIPS_INS_SC = 1121;; +let _MIPS_INS_SCD = 1122;; +let _MIPS_INS_SCE = 1123;; +let _MIPS_INS_SCWP = 1124;; +let _MIPS_INS_SDBBP = 1125;; +let _MIPS_INS_SDBBP16 = 1126;; +let _MIPS_INS_SDC1 = 1127;; +let _MIPS_INS_SDC2 = 1128;; +let _MIPS_INS_SDC3 = 1129;; +let _MIPS_INS_SDL = 1130;; +let _MIPS_INS_SDR = 1131;; +let _MIPS_INS_SDXC1 = 1132;; +let _MIPS_INS_SEB = 1133;; +let _MIPS_INS_SEH = 1134;; +let _MIPS_INS_SELEQZ = 1135;; +let _MIPS_INS_SELEQZ_D = 1136;; +let _MIPS_INS_SELEQZ_S = 1137;; +let _MIPS_INS_SELNEZ = 1138;; +let _MIPS_INS_SELNEZ_D = 1139;; +let _MIPS_INS_SELNEZ_S = 1140;; +let _MIPS_INS_SEL_D = 1141;; +let _MIPS_INS_SEL_S = 1142;; +let _MIPS_INS_SEQI = 1143;; +let _MIPS_INS_SH = 1144;; +let _MIPS_INS_SH16 = 1145;; +let _MIPS_INS_SHE = 1146;; +let _MIPS_INS_SHF_B = 1147;; +let _MIPS_INS_SHF_H = 1148;; +let _MIPS_INS_SHF_W = 1149;; +let _MIPS_INS_SHILO = 1150;; +let _MIPS_INS_SHILOV = 1151;; +let _MIPS_INS_SHLLV_PH = 1152;; +let _MIPS_INS_SHLLV_QB = 1153;; +let _MIPS_INS_SHLLV_S_PH = 1154;; +let _MIPS_INS_SHLLV_S_W = 1155;; +let _MIPS_INS_SHLL_PH = 1156;; +let _MIPS_INS_SHLL_QB = 1157;; +let _MIPS_INS_SHLL_S_PH = 1158;; +let _MIPS_INS_SHLL_S_W = 1159;; +let _MIPS_INS_SHRAV_PH = 1160;; +let _MIPS_INS_SHRAV_QB = 1161;; +let _MIPS_INS_SHRAV_R_PH = 1162;; +let _MIPS_INS_SHRAV_R_QB = 1163;; +let _MIPS_INS_SHRAV_R_W = 1164;; +let _MIPS_INS_SHRA_PH = 1165;; +let _MIPS_INS_SHRA_QB = 1166;; +let _MIPS_INS_SHRA_R_PH = 1167;; +let _MIPS_INS_SHRA_R_QB = 1168;; +let _MIPS_INS_SHRA_R_W = 1169;; +let _MIPS_INS_SHRLV_PH = 1170;; +let _MIPS_INS_SHRLV_QB = 1171;; +let _MIPS_INS_SHRL_PH = 1172;; +let _MIPS_INS_SHRL_QB = 1173;; +let _MIPS_INS_SHXS = 1174;; +let _MIPS_INS_SHX = 1175;; +let _MIPS_INS_SIGRIE = 1176;; +let _MIPS_INS_SLDI_B = 1177;; +let _MIPS_INS_SLDI_D = 1178;; +let _MIPS_INS_SLDI_H = 1179;; +let _MIPS_INS_SLDI_W = 1180;; +let _MIPS_INS_SLD_B = 1181;; +let _MIPS_INS_SLD_D = 1182;; +let _MIPS_INS_SLD_H = 1183;; +let _MIPS_INS_SLD_W = 1184;; +let _MIPS_INS_SLL = 1185;; +let _MIPS_INS_SLL16 = 1186;; +let _MIPS_INS_SLLI_B = 1187;; +let _MIPS_INS_SLLI_D = 1188;; +let _MIPS_INS_SLLI_H = 1189;; +let _MIPS_INS_SLLI_W = 1190;; +let _MIPS_INS_SLLV = 1191;; +let _MIPS_INS_SLL_B = 1192;; +let _MIPS_INS_SLL_D = 1193;; +let _MIPS_INS_SLL_H = 1194;; +let _MIPS_INS_SLL_W = 1195;; +let _MIPS_INS_SLTIU = 1196;; +let _MIPS_INS_SLTI = 1197;; +let _MIPS_INS_SNEI = 1198;; +let _MIPS_INS_SOV = 1199;; +let _MIPS_INS_SPLATI_B = 1200;; +let _MIPS_INS_SPLATI_D = 1201;; +let _MIPS_INS_SPLATI_H = 1202;; +let _MIPS_INS_SPLATI_W = 1203;; +let _MIPS_INS_SPLAT_B = 1204;; +let _MIPS_INS_SPLAT_D = 1205;; +let _MIPS_INS_SPLAT_H = 1206;; +let _MIPS_INS_SPLAT_W = 1207;; +let _MIPS_INS_SRA = 1208;; +let _MIPS_INS_SRAI_B = 1209;; +let _MIPS_INS_SRAI_D = 1210;; +let _MIPS_INS_SRAI_H = 1211;; +let _MIPS_INS_SRAI_W = 1212;; +let _MIPS_INS_SRARI_B = 1213;; +let _MIPS_INS_SRARI_D = 1214;; +let _MIPS_INS_SRARI_H = 1215;; +let _MIPS_INS_SRARI_W = 1216;; +let _MIPS_INS_SRAR_B = 1217;; +let _MIPS_INS_SRAR_D = 1218;; +let _MIPS_INS_SRAR_H = 1219;; +let _MIPS_INS_SRAR_W = 1220;; +let _MIPS_INS_SRAV = 1221;; +let _MIPS_INS_SRA_B = 1222;; +let _MIPS_INS_SRA_D = 1223;; +let _MIPS_INS_SRA_H = 1224;; +let _MIPS_INS_SRA_W = 1225;; +let _MIPS_INS_SRL = 1226;; +let _MIPS_INS_SRL16 = 1227;; +let _MIPS_INS_SRLI_B = 1228;; +let _MIPS_INS_SRLI_D = 1229;; +let _MIPS_INS_SRLI_H = 1230;; +let _MIPS_INS_SRLI_W = 1231;; +let _MIPS_INS_SRLRI_B = 1232;; +let _MIPS_INS_SRLRI_D = 1233;; +let _MIPS_INS_SRLRI_H = 1234;; +let _MIPS_INS_SRLRI_W = 1235;; +let _MIPS_INS_SRLR_B = 1236;; +let _MIPS_INS_SRLR_D = 1237;; +let _MIPS_INS_SRLR_H = 1238;; +let _MIPS_INS_SRLR_W = 1239;; +let _MIPS_INS_SRLV = 1240;; +let _MIPS_INS_SRL_B = 1241;; +let _MIPS_INS_SRL_D = 1242;; +let _MIPS_INS_SRL_H = 1243;; +let _MIPS_INS_SRL_W = 1244;; +let _MIPS_INS_SSNOP = 1245;; +let _MIPS_INS_ST_B = 1246;; +let _MIPS_INS_ST_D = 1247;; +let _MIPS_INS_ST_H = 1248;; +let _MIPS_INS_ST_W = 1249;; +let _MIPS_INS_SUB = 1250;; +let _MIPS_INS_SUBQH_PH = 1251;; +let _MIPS_INS_SUBQH_R_PH = 1252;; +let _MIPS_INS_SUBQH_R_W = 1253;; +let _MIPS_INS_SUBQH_W = 1254;; +let _MIPS_INS_SUBQ_PH = 1255;; +let _MIPS_INS_SUBQ_S_PH = 1256;; +let _MIPS_INS_SUBQ_S_W = 1257;; +let _MIPS_INS_SUBSUS_U_B = 1258;; +let _MIPS_INS_SUBSUS_U_D = 1259;; +let _MIPS_INS_SUBSUS_U_H = 1260;; +let _MIPS_INS_SUBSUS_U_W = 1261;; +let _MIPS_INS_SUBSUU_S_B = 1262;; +let _MIPS_INS_SUBSUU_S_D = 1263;; +let _MIPS_INS_SUBSUU_S_H = 1264;; +let _MIPS_INS_SUBSUU_S_W = 1265;; +let _MIPS_INS_SUBS_S_B = 1266;; +let _MIPS_INS_SUBS_S_D = 1267;; +let _MIPS_INS_SUBS_S_H = 1268;; +let _MIPS_INS_SUBS_S_W = 1269;; +let _MIPS_INS_SUBS_U_B = 1270;; +let _MIPS_INS_SUBS_U_D = 1271;; +let _MIPS_INS_SUBS_U_H = 1272;; +let _MIPS_INS_SUBS_U_W = 1273;; +let _MIPS_INS_SUBU16 = 1274;; +let _MIPS_INS_SUBUH_QB = 1275;; +let _MIPS_INS_SUBUH_R_QB = 1276;; +let _MIPS_INS_SUBU_PH = 1277;; +let _MIPS_INS_SUBU_QB = 1278;; +let _MIPS_INS_SUBU_S_PH = 1279;; +let _MIPS_INS_SUBU_S_QB = 1280;; +let _MIPS_INS_SUBVI_B = 1281;; +let _MIPS_INS_SUBVI_D = 1282;; +let _MIPS_INS_SUBVI_H = 1283;; +let _MIPS_INS_SUBVI_W = 1284;; +let _MIPS_INS_SUBV_B = 1285;; +let _MIPS_INS_SUBV_D = 1286;; +let _MIPS_INS_SUBV_H = 1287;; +let _MIPS_INS_SUBV_W = 1288;; +let _MIPS_INS_SUXC1 = 1289;; +let _MIPS_INS_SW = 1290;; +let _MIPS_INS_SW16 = 1291;; +let _MIPS_INS_SWC1 = 1292;; +let _MIPS_INS_SWC2 = 1293;; +let _MIPS_INS_SWC3 = 1294;; +let _MIPS_INS_SWE = 1295;; +let _MIPS_INS_SWL = 1296;; +let _MIPS_INS_SWLE = 1297;; +let _MIPS_INS_SWM16 = 1298;; +let _MIPS_INS_SWM32 = 1299;; +let _MIPS_INS_SWPC = 1300;; +let _MIPS_INS_SWP = 1301;; +let _MIPS_INS_SWR = 1302;; +let _MIPS_INS_SWRE = 1303;; +let _MIPS_INS_SWSP = 1304;; +let _MIPS_INS_SWXC1 = 1305;; +let _MIPS_INS_SWXS = 1306;; +let _MIPS_INS_SWX = 1307;; +let _MIPS_INS_SYNC = 1308;; +let _MIPS_INS_SYNCI = 1309;; +let _MIPS_INS_SYSCALL = 1310;; +let _MIPS_INS_TEQ = 1311;; +let _MIPS_INS_TEQI = 1312;; +let _MIPS_INS_TGE = 1313;; +let _MIPS_INS_TGEI = 1314;; +let _MIPS_INS_TGEIU = 1315;; +let _MIPS_INS_TGEU = 1316;; +let _MIPS_INS_TLBGINV = 1317;; +let _MIPS_INS_TLBGINVF = 1318;; +let _MIPS_INS_TLBGP = 1319;; +let _MIPS_INS_TLBGR = 1320;; +let _MIPS_INS_TLBGWI = 1321;; +let _MIPS_INS_TLBGWR = 1322;; +let _MIPS_INS_TLBINV = 1323;; +let _MIPS_INS_TLBINVF = 1324;; +let _MIPS_INS_TLBP = 1325;; +let _MIPS_INS_TLBR = 1326;; +let _MIPS_INS_TLBWI = 1327;; +let _MIPS_INS_TLBWR = 1328;; +let _MIPS_INS_TLT = 1329;; +let _MIPS_INS_TLTI = 1330;; +let _MIPS_INS_TLTIU = 1331;; +let _MIPS_INS_TLTU = 1332;; +let _MIPS_INS_TNE = 1333;; +let _MIPS_INS_TNEI = 1334;; +let _MIPS_INS_TRUNC_L_D = 1335;; +let _MIPS_INS_TRUNC_L_S = 1336;; +let _MIPS_INS_UALH = 1337;; +let _MIPS_INS_UALWM = 1338;; +let _MIPS_INS_UALW = 1339;; +let _MIPS_INS_UASH = 1340;; +let _MIPS_INS_UASWM = 1341;; +let _MIPS_INS_UASW = 1342;; +let _MIPS_INS_V3MULU = 1343;; +let _MIPS_INS_VMM0 = 1344;; +let _MIPS_INS_VMULU = 1345;; +let _MIPS_INS_VSHF_B = 1346;; +let _MIPS_INS_VSHF_D = 1347;; +let _MIPS_INS_VSHF_H = 1348;; +let _MIPS_INS_VSHF_W = 1349;; +let _MIPS_INS_WAIT = 1350;; +let _MIPS_INS_WRDSP = 1351;; +let _MIPS_INS_WRPGPR = 1352;; +let _MIPS_INS_WSBH = 1353;; +let _MIPS_INS_XOR = 1354;; +let _MIPS_INS_XOR16 = 1355;; +let _MIPS_INS_XORI_B = 1356;; +let _MIPS_INS_XORI = 1357;; +let _MIPS_INS_XOR_V = 1358;; +let _MIPS_INS_YIELD = 1359;; +let _MIPS_INS_ENDING = 1360;; +let _MIPS_INS_ALIAS_BEGIN = 1361;; +let _MIPS_INS_ALIAS_ADDIU_B32 = 1362;; +let _MIPS_INS_ALIAS_BITREVB = 1363;; +let _MIPS_INS_ALIAS_BITREVH = 1364;; +let _MIPS_INS_ALIAS_BYTEREVH = 1365;; +let _MIPS_INS_ALIAS_NOT = 1366;; +let _MIPS_INS_ALIAS_RESTORE_JRC = 1367;; +let _MIPS_INS_ALIAS_RESTORE = 1368;; +let _MIPS_INS_ALIAS_SAVE = 1369;; +let _MIPS_INS_ALIAS_MOVE = 1370;; +let _MIPS_INS_ALIAS_BAL = 1371;; +let _MIPS_INS_ALIAS_JALR_HB = 1372;; +let _MIPS_INS_ALIAS_NEG = 1373;; +let _MIPS_INS_ALIAS_NEGU = 1374;; +let _MIPS_INS_ALIAS_NOP = 1375;; +let _MIPS_INS_ALIAS_BNEZL = 1376;; +let _MIPS_INS_ALIAS_BEQZL = 1377;; +let _MIPS_INS_ALIAS_SYSCALL = 1378;; +let _MIPS_INS_ALIAS_BREAK = 1379;; +let _MIPS_INS_ALIAS_EI = 1380;; +let _MIPS_INS_ALIAS_DI = 1381;; +let _MIPS_INS_ALIAS_TEQ = 1382;; +let _MIPS_INS_ALIAS_TGE = 1383;; +let _MIPS_INS_ALIAS_TGEU = 1384;; +let _MIPS_INS_ALIAS_TLT = 1385;; +let _MIPS_INS_ALIAS_TLTU = 1386;; +let _MIPS_INS_ALIAS_TNE = 1387;; +let _MIPS_INS_ALIAS_RDHWR = 1388;; +let _MIPS_INS_ALIAS_SDBBP = 1389;; +let _MIPS_INS_ALIAS_SYNC = 1390;; +let _MIPS_INS_ALIAS_HYPCALL = 1391;; +let _MIPS_INS_ALIAS_NOR = 1392;; +let _MIPS_INS_ALIAS_C_F_S = 1393;; +let _MIPS_INS_ALIAS_C_UN_S = 1394;; +let _MIPS_INS_ALIAS_C_EQ_S = 1395;; +let _MIPS_INS_ALIAS_C_UEQ_S = 1396;; +let _MIPS_INS_ALIAS_C_OLT_S = 1397;; +let _MIPS_INS_ALIAS_C_ULT_S = 1398;; +let _MIPS_INS_ALIAS_C_OLE_S = 1399;; +let _MIPS_INS_ALIAS_C_ULE_S = 1400;; +let _MIPS_INS_ALIAS_C_SF_S = 1401;; +let _MIPS_INS_ALIAS_C_NGLE_S = 1402;; +let _MIPS_INS_ALIAS_C_SEQ_S = 1403;; +let _MIPS_INS_ALIAS_C_NGL_S = 1404;; +let _MIPS_INS_ALIAS_C_LT_S = 1405;; +let _MIPS_INS_ALIAS_C_NGE_S = 1406;; +let _MIPS_INS_ALIAS_C_LE_S = 1407;; +let _MIPS_INS_ALIAS_C_NGT_S = 1408;; +let _MIPS_INS_ALIAS_BC1T = 1409;; +let _MIPS_INS_ALIAS_BC1F = 1410;; +let _MIPS_INS_ALIAS_C_F_D = 1411;; +let _MIPS_INS_ALIAS_C_UN_D = 1412;; +let _MIPS_INS_ALIAS_C_EQ_D = 1413;; +let _MIPS_INS_ALIAS_C_UEQ_D = 1414;; +let _MIPS_INS_ALIAS_C_OLT_D = 1415;; +let _MIPS_INS_ALIAS_C_ULT_D = 1416;; +let _MIPS_INS_ALIAS_C_OLE_D = 1417;; +let _MIPS_INS_ALIAS_C_ULE_D = 1418;; +let _MIPS_INS_ALIAS_C_SF_D = 1419;; +let _MIPS_INS_ALIAS_C_NGLE_D = 1420;; +let _MIPS_INS_ALIAS_C_SEQ_D = 1421;; +let _MIPS_INS_ALIAS_C_NGL_D = 1422;; +let _MIPS_INS_ALIAS_C_LT_D = 1423;; +let _MIPS_INS_ALIAS_C_NGE_D = 1424;; +let _MIPS_INS_ALIAS_C_LE_D = 1425;; +let _MIPS_INS_ALIAS_C_NGT_D = 1426;; +let _MIPS_INS_ALIAS_BC1TL = 1427;; +let _MIPS_INS_ALIAS_BC1FL = 1428;; +let _MIPS_INS_ALIAS_DNEG = 1429;; +let _MIPS_INS_ALIAS_DNEGU = 1430;; +let _MIPS_INS_ALIAS_SLT = 1431;; +let _MIPS_INS_ALIAS_SLTU = 1432;; +let _MIPS_INS_ALIAS_SIGRIE = 1433;; +let _MIPS_INS_ALIAS_JR = 1434;; +let _MIPS_INS_ALIAS_JRC = 1435;; +let _MIPS_INS_ALIAS_JALRC = 1436;; +let _MIPS_INS_ALIAS_DIV = 1437;; +let _MIPS_INS_ALIAS_DIVU = 1438;; +let _MIPS_INS_ALIAS_LAPC = 1439;; +let _MIPS_INS_ALIAS_WRDSP = 1440;; +let _MIPS_INS_ALIAS_WAIT = 1441;; +let _MIPS_INS_ALIAS_SW = 1442;; +let _MIPS_INS_ALIAS_JALRC_HB = 1443;; +let _MIPS_INS_ALIAS_ADDIU_B = 1444;; +let _MIPS_INS_ALIAS_ADDIU_W = 1445;; +let _MIPS_INS_ALIAS_JRC_HB = 1446;; +let _MIPS_INS_ALIAS_BEQC = 1447;; +let _MIPS_INS_ALIAS_BNEC = 1448;; +let _MIPS_INS_ALIAS_BEQZC = 1449;; +let _MIPS_INS_ALIAS_BNEZC = 1450;; +let _MIPS_INS_ALIAS_MFC0 = 1451;; +let _MIPS_INS_ALIAS_MFHC0 = 1452;; +let _MIPS_INS_ALIAS_MTC0 = 1453;; +let _MIPS_INS_ALIAS_MTHC0 = 1454;; +let _MIPS_INS_ALIAS_DMT = 1455;; +let _MIPS_INS_ALIAS_EMT = 1456;; +let _MIPS_INS_ALIAS_DVPE = 1457;; +let _MIPS_INS_ALIAS_EVPE = 1458;; +let _MIPS_INS_ALIAS_YIELD = 1459;; +let _MIPS_INS_ALIAS_MFTC0 = 1460;; +let _MIPS_INS_ALIAS_MFTLO = 1461;; +let _MIPS_INS_ALIAS_MFTHI = 1462;; +let _MIPS_INS_ALIAS_MFTACX = 1463;; +let _MIPS_INS_ALIAS_MTTC0 = 1464;; +let _MIPS_INS_ALIAS_MTTLO = 1465;; +let _MIPS_INS_ALIAS_MTTHI = 1466;; +let _MIPS_INS_ALIAS_MTTACX = 1467;; +let _MIPS_INS_ALIAS_END = 1468;; let _MIPS_GRP_INVALID = 0;; let _MIPS_GRP_JUMP = 1;; @@ -825,37 +2120,60 @@ let _MIPS_GRP_INT = 4;; let _MIPS_GRP_IRET = 5;; let _MIPS_GRP_PRIVILEGE = 6;; let _MIPS_GRP_BRANCH_RELATIVE = 7;; -let _MIPS_GRP_BITCOUNT = 128;; -let _MIPS_GRP_DSP = 129;; -let _MIPS_GRP_DSPR2 = 130;; -let _MIPS_GRP_FPIDX = 131;; -let _MIPS_GRP_MSA = 132;; -let _MIPS_GRP_MIPS32R2 = 133;; -let _MIPS_GRP_MIPS64 = 134;; -let _MIPS_GRP_MIPS64R2 = 135;; -let _MIPS_GRP_SEINREG = 136;; -let _MIPS_GRP_STDENC = 137;; -let _MIPS_GRP_SWAP = 138;; -let _MIPS_GRP_MICROMIPS = 139;; -let _MIPS_GRP_MIPS16MODE = 140;; -let _MIPS_GRP_FP64BIT = 141;; -let _MIPS_GRP_NONANSFPMATH = 142;; -let _MIPS_GRP_NOTFP64BIT = 143;; -let _MIPS_GRP_NOTINMICROMIPS = 144;; -let _MIPS_GRP_NOTNACL = 145;; -let _MIPS_GRP_NOTMIPS32R6 = 146;; -let _MIPS_GRP_NOTMIPS64R6 = 147;; -let _MIPS_GRP_CNMIPS = 148;; -let _MIPS_GRP_MIPS32 = 149;; -let _MIPS_GRP_MIPS32R6 = 150;; -let _MIPS_GRP_MIPS64R6 = 151;; -let _MIPS_GRP_MIPS2 = 152;; -let _MIPS_GRP_MIPS3 = 153;; -let _MIPS_GRP_MIPS3_32 = 154;; -let _MIPS_GRP_MIPS3_32R2 = 155;; -let _MIPS_GRP_MIPS4_32 = 156;; -let _MIPS_GRP_MIPS4_32R2 = 157;; -let _MIPS_GRP_MIPS5_32R2 = 158;; -let _MIPS_GRP_GP32BIT = 159;; -let _MIPS_GRP_GP64BIT = 160;; -let _MIPS_GRP_ENDING = 161;; +let _MIPS_FEATURE_HASMIPS2 = 128;; +let _MIPS_FEATURE_HASMIPS3_32 = 129;; +let _MIPS_FEATURE_HASMIPS3_32R2 = 130;; +let _MIPS_FEATURE_HASMIPS3 = 131;; +let _MIPS_FEATURE_NOTMIPS3 = 132;; +let _MIPS_FEATURE_HASMIPS4_32 = 133;; +let _MIPS_FEATURE_NOTMIPS4_32 = 134;; +let _MIPS_FEATURE_HASMIPS4_32R2 = 135;; +let _MIPS_FEATURE_HASMIPS5_32R2 = 136;; +let _MIPS_FEATURE_HASMIPS32 = 137;; +let _MIPS_FEATURE_HASMIPS32R2 = 138;; +let _MIPS_FEATURE_HASMIPS32R5 = 139;; +let _MIPS_FEATURE_HASMIPS32R6 = 140;; +let _MIPS_FEATURE_NOTMIPS32R6 = 141;; +let _MIPS_FEATURE_HASNANOMIPS = 142;; +let _MIPS_FEATURE_NOTNANOMIPS = 143;; +let _MIPS_FEATURE_ISGP64BIT = 144;; +let _MIPS_FEATURE_ISGP32BIT = 145;; +let _MIPS_FEATURE_ISPTR64BIT = 146;; +let _MIPS_FEATURE_ISPTR32BIT = 147;; +let _MIPS_FEATURE_HASMIPS64 = 148;; +let _MIPS_FEATURE_NOTMIPS64 = 149;; +let _MIPS_FEATURE_HASMIPS64R2 = 150;; +let _MIPS_FEATURE_HASMIPS64R5 = 151;; +let _MIPS_FEATURE_HASMIPS64R6 = 152;; +let _MIPS_FEATURE_NOTMIPS64R6 = 153;; +let _MIPS_FEATURE_INMIPS16MODE = 154;; +let _MIPS_FEATURE_NOTINMIPS16MODE = 155;; +let _MIPS_FEATURE_HASCNMIPS = 156;; +let _MIPS_FEATURE_NOTCNMIPS = 157;; +let _MIPS_FEATURE_HASCNMIPSP = 158;; +let _MIPS_FEATURE_NOTCNMIPSP = 159;; +let _MIPS_FEATURE_ISSYM32 = 160;; +let _MIPS_FEATURE_ISSYM64 = 161;; +let _MIPS_FEATURE_HASSTDENC = 162;; +let _MIPS_FEATURE_INMICROMIPS = 163;; +let _MIPS_FEATURE_NOTINMICROMIPS = 164;; +let _MIPS_FEATURE_HASEVA = 165;; +let _MIPS_FEATURE_HASMSA = 166;; +let _MIPS_FEATURE_HASMADD4 = 167;; +let _MIPS_FEATURE_HASMT = 168;; +let _MIPS_FEATURE_USEINDIRECTJUMPSHAZARD = 169;; +let _MIPS_FEATURE_NOINDIRECTJUMPGUARDS = 170;; +let _MIPS_FEATURE_HASCRC = 171;; +let _MIPS_FEATURE_HASVIRT = 172;; +let _MIPS_FEATURE_HASGINV = 173;; +let _MIPS_FEATURE_HASTLB = 174;; +let _MIPS_FEATURE_ISFP64BIT = 175;; +let _MIPS_FEATURE_NOTFP64BIT = 176;; +let _MIPS_FEATURE_ISSINGLEFLOAT = 177;; +let _MIPS_FEATURE_ISNOTSINGLEFLOAT = 178;; +let _MIPS_FEATURE_ISNOTSOFTFLOAT = 179;; +let _MIPS_FEATURE_HASMIPS3D = 180;; +let _MIPS_FEATURE_HASDSP = 181;; +let _MIPS_FEATURE_HASDSPR2 = 182;; +let _MIPS_FEATURE_HASDSPR3 = 183;; +let _MIPS_GRP_ENDING = 184;; diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py index f70c6e96ea..b0102485f3 100755 --- a/bindings/python/capstone/__init__.py +++ b/bindings/python/capstone/__init__.py @@ -51,24 +51,44 @@ 'CS_MODE_ARM', 'CS_MODE_THUMB', 'CS_MODE_MCLASS', - 'CS_MODE_MICRO', - 'CS_MODE_MIPS3', - 'CS_MODE_MIPS32R6', - 'CS_MODE_MIPS2', 'CS_MODE_V8', 'CS_MODE_V9', 'CS_MODE_QPX', 'CS_MODE_SPE', 'CS_MODE_BOOKE', 'CS_MODE_PS', + 'CS_MODE_MIPS16', + 'CS_MODE_MIPS32', + 'CS_MODE_MIPS64', + 'CS_MODE_MICRO', + 'CS_MODE_MIPS1', + 'CS_MODE_MIPS2', + 'CS_MODE_MIPS32R2', + 'CS_MODE_MIPS32R3', + 'CS_MODE_MIPS32R5', + 'CS_MODE_MIPS32R6', + 'CS_MODE_MIPS3', + 'CS_MODE_MIPS4', + 'CS_MODE_MIPS5', + 'CS_MODE_MIPS64R2', + 'CS_MODE_MIPS64R3', + 'CS_MODE_MIPS64R5', + 'CS_MODE_MIPS64R6', + 'CS_MODE_OCTEON', + 'CS_MODE_OCTEONP', + 'CS_MODE_NANOMIPS', + 'CS_MODE_NMS1', + 'CS_MODE_I7200', + 'CS_MODE_MIPS_NOFLOAT', + 'CS_MODE_MIPS_PTR64', + 'CS_MODE_MICRO32R3', + 'CS_MODE_MICRO32R6', 'CS_MODE_M68K_000', 'CS_MODE_M68K_010', 'CS_MODE_M68K_020', 'CS_MODE_M68K_030', 'CS_MODE_M68K_040', 'CS_MODE_M68K_060', - 'CS_MODE_MIPS32', - 'CS_MODE_MIPS64', 'CS_MODE_M680X_6301', 'CS_MODE_M680X_6309', 'CS_MODE_M680X_6800', @@ -119,8 +139,10 @@ 'CS_OPT_SYNTAX_MASM', 'CS_OPT_SYNTAX_MOTOROLA', 'CS_OPT_SYNTAX_CS_REG_ALIAS', + 'CS_OPT_SYNTAX_NO_DOLLAR', 'CS_OPT_DETAIL', + 'CS_OPT_DETAIL_REAL', 'CS_OPT_MODE', 'CS_OPT_ON', 'CS_OPT_OFF', @@ -257,8 +279,32 @@ CS_MODE_M68K_040 = (1 << 5) # M68K 68040 mode CS_MODE_M68K_060 = (1 << 6) # M68K 68060 mode CS_MODE_BIG_ENDIAN = (1 << 31) # big-endian mode -CS_MODE_MIPS32 = CS_MODE_32 # Mips32 ISA -CS_MODE_MIPS64 = CS_MODE_64 # Mips64 ISA +CS_MODE_MIPS16 = CS_MODE_16 # Generic mips16 +CS_MODE_MIPS32 = CS_MODE_32 # Generic mips32 +CS_MODE_MIPS64 = CS_MODE_64 # Generic mips64 +CS_MODE_MICRO = 1 << 4 # microMips +CS_MODE_MIPS1 = 1 << 5 # Mips I ISA Support +CS_MODE_MIPS2 = 1 << 6 # Mips II ISA Support +CS_MODE_MIPS32R2 = 1 << 7 # Mips32r2 ISA Support +CS_MODE_MIPS32R3 = 1 << 8 # Mips32r3 ISA Support +CS_MODE_MIPS32R5 = 1 << 9 # Mips32r5 ISA Support +CS_MODE_MIPS32R6 = 1 << 10 # Mips32r6 ISA Support +CS_MODE_MIPS3 = 1 << 11 # MIPS III ISA Support +CS_MODE_MIPS4 = 1 << 12 # MIPS IV ISA Support +CS_MODE_MIPS5 = 1 << 13 # MIPS V ISA Support +CS_MODE_MIPS64R2 = 1 << 14 # Mips64r2 ISA Support +CS_MODE_MIPS64R3 = 1 << 15 # Mips64r3 ISA Support +CS_MODE_MIPS64R5 = 1 << 16 # Mips64r5 ISA Support +CS_MODE_MIPS64R6 = 1 << 17 # Mips64r6 ISA Support +CS_MODE_OCTEON = 1 << 18 # Octeon cnMIPS Support +CS_MODE_OCTEONP = 1 << 19 # Octeon+ cnMIPS Support +CS_MODE_NANOMIPS = 1 << 20 # Generic nanomips +CS_MODE_NMS1 = ((1 << 21) | CS_MODE_NANOMIPS) # nanoMips NMS1 +CS_MODE_I7200 = ((1 << 22) | CS_MODE_NANOMIPS) # nanoMips I7200 +CS_MODE_MIPS_NOFLOAT = 1 << 23 # Disable floating points ops +CS_MODE_MIPS_PTR64 = 1 << 24 # Mips pointers are 64-bit +CS_MODE_MICRO32R3 = (CS_MODE_MICRO | CS_MODE_MIPS32R3) # microMips32r3 +CS_MODE_MICRO32R6 = (CS_MODE_MICRO | CS_MODE_MIPS32R6) # microMips32r6 CS_MODE_M680X_6301 = (1 << 1) # M680X HD6301/3 mode CS_MODE_M680X_6309 = (1 << 2) # M680X HD6309 mode CS_MODE_M680X_6800 = (1 << 3) # M680X M6800/2 mode @@ -364,6 +410,7 @@ CS_OPT_SYNTAX_MOTOROLA = (1 << 6) # MOS65XX use $ as hex prefix CS_OPT_SYNTAX_CS_REG_ALIAS = (1 << 7) # Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.) CS_OPT_SYNTAX_PERCENT = (1 << 8) # Prints the % in front of PPC registers. +CS_OPT_SYNTAX_NO_DOLLAR = (1 << 9) # Does not print the $ in front of Mips registers. CS_OPT_DETAIL_REAL = (1 << 1) # If enabled, always sets the real instruction detail.Even if the instruction is an alias. # Capstone error type @@ -501,7 +548,7 @@ class _cs_detail(ctypes.Structure): ('regs_read_count', ctypes.c_ubyte), ('regs_write', ctypes.c_uint16 * 47), ('regs_write_count', ctypes.c_ubyte), - ('groups', ctypes.c_ubyte * 8), + ('groups', ctypes.c_ubyte * 16), ('groups_count', ctypes.c_ubyte), ('writeback', ctypes.c_bool), ('arch', _cs_arch), diff --git a/bindings/python/capstone/mips.py b/bindings/python/capstone/mips.py index 44513d2527..df54fec22b 100644 --- a/bindings/python/capstone/mips.py +++ b/bindings/python/capstone/mips.py @@ -15,6 +15,7 @@ class MipsOpValue(ctypes.Union): _fields_ = ( ('reg', ctypes.c_uint), ('imm', ctypes.c_int64), + ('uimm', ctypes.c_uint64), ('mem', MipsOpMem), ) @@ -22,6 +23,9 @@ class MipsOp(ctypes.Structure): _fields_ = ( ('type', ctypes.c_uint), ('value', MipsOpValue), + ('is_reglist', ctypes.c_bool), + ('is_unsigned', ctypes.c_bool), + ('access', ctypes.c_uint8), ) @property diff --git a/bindings/python/capstone/mips_const.py b/bindings/python/capstone/mips_const.py index f3f2f73881..b48b4ac552 100644 --- a/bindings/python/capstone/mips_const.py +++ b/bindings/python/capstone/mips_const.py @@ -7,816 +7,2111 @@ MIPS_OP_MEM = 3 MIPS_REG_INVALID = 0 -MIPS_REG_PC = 1 -MIPS_REG_0 = 2 -MIPS_REG_1 = 3 -MIPS_REG_2 = 4 -MIPS_REG_3 = 5 -MIPS_REG_4 = 6 -MIPS_REG_5 = 7 -MIPS_REG_6 = 8 -MIPS_REG_7 = 9 -MIPS_REG_8 = 10 -MIPS_REG_9 = 11 -MIPS_REG_10 = 12 -MIPS_REG_11 = 13 -MIPS_REG_12 = 14 -MIPS_REG_13 = 15 -MIPS_REG_14 = 16 -MIPS_REG_15 = 17 -MIPS_REG_16 = 18 -MIPS_REG_17 = 19 -MIPS_REG_18 = 20 -MIPS_REG_19 = 21 -MIPS_REG_20 = 22 -MIPS_REG_21 = 23 -MIPS_REG_22 = 24 -MIPS_REG_23 = 25 -MIPS_REG_24 = 26 -MIPS_REG_25 = 27 -MIPS_REG_26 = 28 -MIPS_REG_27 = 29 -MIPS_REG_28 = 30 -MIPS_REG_29 = 31 -MIPS_REG_30 = 32 -MIPS_REG_31 = 33 -MIPS_REG_DSPCCOND = 34 -MIPS_REG_DSPCARRY = 35 -MIPS_REG_DSPEFI = 36 -MIPS_REG_DSPOUTFLAG = 37 -MIPS_REG_DSPOUTFLAG16_19 = 38 -MIPS_REG_DSPOUTFLAG20 = 39 -MIPS_REG_DSPOUTFLAG21 = 40 -MIPS_REG_DSPOUTFLAG22 = 41 -MIPS_REG_DSPOUTFLAG23 = 42 -MIPS_REG_DSPPOS = 43 -MIPS_REG_DSPSCOUNT = 44 -MIPS_REG_AC0 = 45 -MIPS_REG_AC1 = 46 -MIPS_REG_AC2 = 47 -MIPS_REG_AC3 = 48 -MIPS_REG_CC0 = 49 -MIPS_REG_CC1 = 50 -MIPS_REG_CC2 = 51 -MIPS_REG_CC3 = 52 -MIPS_REG_CC4 = 53 -MIPS_REG_CC5 = 54 -MIPS_REG_CC6 = 55 -MIPS_REG_CC7 = 56 -MIPS_REG_F0 = 57 -MIPS_REG_F1 = 58 -MIPS_REG_F2 = 59 -MIPS_REG_F3 = 60 -MIPS_REG_F4 = 61 -MIPS_REG_F5 = 62 -MIPS_REG_F6 = 63 -MIPS_REG_F7 = 64 -MIPS_REG_F8 = 65 -MIPS_REG_F9 = 66 -MIPS_REG_F10 = 67 -MIPS_REG_F11 = 68 -MIPS_REG_F12 = 69 -MIPS_REG_F13 = 70 -MIPS_REG_F14 = 71 -MIPS_REG_F15 = 72 -MIPS_REG_F16 = 73 -MIPS_REG_F17 = 74 -MIPS_REG_F18 = 75 -MIPS_REG_F19 = 76 -MIPS_REG_F20 = 77 -MIPS_REG_F21 = 78 -MIPS_REG_F22 = 79 -MIPS_REG_F23 = 80 -MIPS_REG_F24 = 81 -MIPS_REG_F25 = 82 -MIPS_REG_F26 = 83 -MIPS_REG_F27 = 84 -MIPS_REG_F28 = 85 -MIPS_REG_F29 = 86 -MIPS_REG_F30 = 87 -MIPS_REG_F31 = 88 -MIPS_REG_FCC0 = 89 -MIPS_REG_FCC1 = 90 -MIPS_REG_FCC2 = 91 -MIPS_REG_FCC3 = 92 -MIPS_REG_FCC4 = 93 -MIPS_REG_FCC5 = 94 -MIPS_REG_FCC6 = 95 -MIPS_REG_FCC7 = 96 -MIPS_REG_W0 = 97 -MIPS_REG_W1 = 98 -MIPS_REG_W2 = 99 -MIPS_REG_W3 = 100 -MIPS_REG_W4 = 101 -MIPS_REG_W5 = 102 -MIPS_REG_W6 = 103 -MIPS_REG_W7 = 104 -MIPS_REG_W8 = 105 -MIPS_REG_W9 = 106 -MIPS_REG_W10 = 107 -MIPS_REG_W11 = 108 -MIPS_REG_W12 = 109 -MIPS_REG_W13 = 110 -MIPS_REG_W14 = 111 -MIPS_REG_W15 = 112 -MIPS_REG_W16 = 113 -MIPS_REG_W17 = 114 -MIPS_REG_W18 = 115 -MIPS_REG_W19 = 116 -MIPS_REG_W20 = 117 -MIPS_REG_W21 = 118 -MIPS_REG_W22 = 119 -MIPS_REG_W23 = 120 -MIPS_REG_W24 = 121 -MIPS_REG_W25 = 122 -MIPS_REG_W26 = 123 -MIPS_REG_W27 = 124 -MIPS_REG_W28 = 125 -MIPS_REG_W29 = 126 -MIPS_REG_W30 = 127 -MIPS_REG_W31 = 128 -MIPS_REG_HI = 129 -MIPS_REG_LO = 130 -MIPS_REG_P0 = 131 -MIPS_REG_P1 = 132 -MIPS_REG_P2 = 133 -MIPS_REG_MPL0 = 134 -MIPS_REG_MPL1 = 135 -MIPS_REG_MPL2 = 136 -MIPS_REG_ENDING = 137 -MIPS_REG_ZERO = MIPS_REG_0 -MIPS_REG_AT = MIPS_REG_1 -MIPS_REG_V0 = MIPS_REG_2 -MIPS_REG_V1 = MIPS_REG_3 -MIPS_REG_A0 = MIPS_REG_4 -MIPS_REG_A1 = MIPS_REG_5 -MIPS_REG_A2 = MIPS_REG_6 -MIPS_REG_A3 = MIPS_REG_7 -MIPS_REG_T0 = MIPS_REG_8 -MIPS_REG_T1 = MIPS_REG_9 -MIPS_REG_T2 = MIPS_REG_10 -MIPS_REG_T3 = MIPS_REG_11 -MIPS_REG_T4 = MIPS_REG_12 -MIPS_REG_T5 = MIPS_REG_13 -MIPS_REG_T6 = MIPS_REG_14 -MIPS_REG_T7 = MIPS_REG_15 -MIPS_REG_S0 = MIPS_REG_16 -MIPS_REG_S1 = MIPS_REG_17 -MIPS_REG_S2 = MIPS_REG_18 -MIPS_REG_S3 = MIPS_REG_19 -MIPS_REG_S4 = MIPS_REG_20 -MIPS_REG_S5 = MIPS_REG_21 -MIPS_REG_S6 = MIPS_REG_22 -MIPS_REG_S7 = MIPS_REG_23 -MIPS_REG_T8 = MIPS_REG_24 -MIPS_REG_T9 = MIPS_REG_25 -MIPS_REG_K0 = MIPS_REG_26 -MIPS_REG_K1 = MIPS_REG_27 -MIPS_REG_GP = MIPS_REG_28 -MIPS_REG_SP = MIPS_REG_29 -MIPS_REG_FP = MIPS_REG_30 -MIPS_REG_S8 = MIPS_REG_30 -MIPS_REG_RA = MIPS_REG_31 -MIPS_REG_HI0 = MIPS_REG_AC0 -MIPS_REG_HI1 = MIPS_REG_AC1 -MIPS_REG_HI2 = MIPS_REG_AC2 -MIPS_REG_HI3 = MIPS_REG_AC3 -MIPS_REG_LO0 = MIPS_REG_HI0 -MIPS_REG_LO1 = MIPS_REG_HI1 -MIPS_REG_LO2 = MIPS_REG_HI2 -MIPS_REG_LO3 = MIPS_REG_HI3 +MIPS_REG_AT = 1 +MIPS_REG_AT_NM = 2 +MIPS_REG_DSPCCOND = 3 +MIPS_REG_DSPCARRY = 4 +MIPS_REG_DSPEFI = 5 +MIPS_REG_DSPOUTFLAG = 6 +MIPS_REG_DSPPOS = 7 +MIPS_REG_DSPSCOUNT = 8 +MIPS_REG_FP = 9 +MIPS_REG_FP_NM = 10 +MIPS_REG_GP = 11 +MIPS_REG_GP_NM = 12 +MIPS_REG_MSAACCESS = 13 +MIPS_REG_MSACSR = 14 +MIPS_REG_MSAIR = 15 +MIPS_REG_MSAMAP = 16 +MIPS_REG_MSAMODIFY = 17 +MIPS_REG_MSAREQUEST = 18 +MIPS_REG_MSASAVE = 19 +MIPS_REG_MSAUNMAP = 20 +MIPS_REG_PC = 21 +MIPS_REG_RA = 22 +MIPS_REG_RA_NM = 23 +MIPS_REG_SP = 24 +MIPS_REG_SP_NM = 25 +MIPS_REG_ZERO = 26 +MIPS_REG_ZERO_NM = 27 +MIPS_REG_A0 = 28 +MIPS_REG_A1 = 29 +MIPS_REG_A2 = 30 +MIPS_REG_A3 = 31 +MIPS_REG_AC0 = 32 +MIPS_REG_AC1 = 33 +MIPS_REG_AC2 = 34 +MIPS_REG_AC3 = 35 +MIPS_REG_AT_64 = 36 +MIPS_REG_COP00 = 37 +MIPS_REG_COP01 = 38 +MIPS_REG_COP02 = 39 +MIPS_REG_COP03 = 40 +MIPS_REG_COP04 = 41 +MIPS_REG_COP05 = 42 +MIPS_REG_COP06 = 43 +MIPS_REG_COP07 = 44 +MIPS_REG_COP08 = 45 +MIPS_REG_COP09 = 46 +MIPS_REG_COP20 = 47 +MIPS_REG_COP21 = 48 +MIPS_REG_COP22 = 49 +MIPS_REG_COP23 = 50 +MIPS_REG_COP24 = 51 +MIPS_REG_COP25 = 52 +MIPS_REG_COP26 = 53 +MIPS_REG_COP27 = 54 +MIPS_REG_COP28 = 55 +MIPS_REG_COP29 = 56 +MIPS_REG_COP30 = 57 +MIPS_REG_COP31 = 58 +MIPS_REG_COP32 = 59 +MIPS_REG_COP33 = 60 +MIPS_REG_COP34 = 61 +MIPS_REG_COP35 = 62 +MIPS_REG_COP36 = 63 +MIPS_REG_COP37 = 64 +MIPS_REG_COP38 = 65 +MIPS_REG_COP39 = 66 +MIPS_REG_COP010 = 67 +MIPS_REG_COP011 = 68 +MIPS_REG_COP012 = 69 +MIPS_REG_COP013 = 70 +MIPS_REG_COP014 = 71 +MIPS_REG_COP015 = 72 +MIPS_REG_COP016 = 73 +MIPS_REG_COP017 = 74 +MIPS_REG_COP018 = 75 +MIPS_REG_COP019 = 76 +MIPS_REG_COP020 = 77 +MIPS_REG_COP021 = 78 +MIPS_REG_COP022 = 79 +MIPS_REG_COP023 = 80 +MIPS_REG_COP024 = 81 +MIPS_REG_COP025 = 82 +MIPS_REG_COP026 = 83 +MIPS_REG_COP027 = 84 +MIPS_REG_COP028 = 85 +MIPS_REG_COP029 = 86 +MIPS_REG_COP030 = 87 +MIPS_REG_COP031 = 88 +MIPS_REG_COP210 = 89 +MIPS_REG_COP211 = 90 +MIPS_REG_COP212 = 91 +MIPS_REG_COP213 = 92 +MIPS_REG_COP214 = 93 +MIPS_REG_COP215 = 94 +MIPS_REG_COP216 = 95 +MIPS_REG_COP217 = 96 +MIPS_REG_COP218 = 97 +MIPS_REG_COP219 = 98 +MIPS_REG_COP220 = 99 +MIPS_REG_COP221 = 100 +MIPS_REG_COP222 = 101 +MIPS_REG_COP223 = 102 +MIPS_REG_COP224 = 103 +MIPS_REG_COP225 = 104 +MIPS_REG_COP226 = 105 +MIPS_REG_COP227 = 106 +MIPS_REG_COP228 = 107 +MIPS_REG_COP229 = 108 +MIPS_REG_COP230 = 109 +MIPS_REG_COP231 = 110 +MIPS_REG_COP310 = 111 +MIPS_REG_COP311 = 112 +MIPS_REG_COP312 = 113 +MIPS_REG_COP313 = 114 +MIPS_REG_COP314 = 115 +MIPS_REG_COP315 = 116 +MIPS_REG_COP316 = 117 +MIPS_REG_COP317 = 118 +MIPS_REG_COP318 = 119 +MIPS_REG_COP319 = 120 +MIPS_REG_COP320 = 121 +MIPS_REG_COP321 = 122 +MIPS_REG_COP322 = 123 +MIPS_REG_COP323 = 124 +MIPS_REG_COP324 = 125 +MIPS_REG_COP325 = 126 +MIPS_REG_COP326 = 127 +MIPS_REG_COP327 = 128 +MIPS_REG_COP328 = 129 +MIPS_REG_COP329 = 130 +MIPS_REG_COP330 = 131 +MIPS_REG_COP331 = 132 +MIPS_REG_D0 = 133 +MIPS_REG_D1 = 134 +MIPS_REG_D2 = 135 +MIPS_REG_D3 = 136 +MIPS_REG_D4 = 137 +MIPS_REG_D5 = 138 +MIPS_REG_D6 = 139 +MIPS_REG_D7 = 140 +MIPS_REG_D8 = 141 +MIPS_REG_D9 = 142 +MIPS_REG_D10 = 143 +MIPS_REG_D11 = 144 +MIPS_REG_D12 = 145 +MIPS_REG_D13 = 146 +MIPS_REG_D14 = 147 +MIPS_REG_D15 = 148 +MIPS_REG_DSPOUTFLAG20 = 149 +MIPS_REG_DSPOUTFLAG21 = 150 +MIPS_REG_DSPOUTFLAG22 = 151 +MIPS_REG_DSPOUTFLAG23 = 152 +MIPS_REG_F0 = 153 +MIPS_REG_F1 = 154 +MIPS_REG_F2 = 155 +MIPS_REG_F3 = 156 +MIPS_REG_F4 = 157 +MIPS_REG_F5 = 158 +MIPS_REG_F6 = 159 +MIPS_REG_F7 = 160 +MIPS_REG_F8 = 161 +MIPS_REG_F9 = 162 +MIPS_REG_F10 = 163 +MIPS_REG_F11 = 164 +MIPS_REG_F12 = 165 +MIPS_REG_F13 = 166 +MIPS_REG_F14 = 167 +MIPS_REG_F15 = 168 +MIPS_REG_F16 = 169 +MIPS_REG_F17 = 170 +MIPS_REG_F18 = 171 +MIPS_REG_F19 = 172 +MIPS_REG_F20 = 173 +MIPS_REG_F21 = 174 +MIPS_REG_F22 = 175 +MIPS_REG_F23 = 176 +MIPS_REG_F24 = 177 +MIPS_REG_F25 = 178 +MIPS_REG_F26 = 179 +MIPS_REG_F27 = 180 +MIPS_REG_F28 = 181 +MIPS_REG_F29 = 182 +MIPS_REG_F30 = 183 +MIPS_REG_F31 = 184 +MIPS_REG_FCC0 = 185 +MIPS_REG_FCC1 = 186 +MIPS_REG_FCC2 = 187 +MIPS_REG_FCC3 = 188 +MIPS_REG_FCC4 = 189 +MIPS_REG_FCC5 = 190 +MIPS_REG_FCC6 = 191 +MIPS_REG_FCC7 = 192 +MIPS_REG_FCR0 = 193 +MIPS_REG_FCR1 = 194 +MIPS_REG_FCR2 = 195 +MIPS_REG_FCR3 = 196 +MIPS_REG_FCR4 = 197 +MIPS_REG_FCR5 = 198 +MIPS_REG_FCR6 = 199 +MIPS_REG_FCR7 = 200 +MIPS_REG_FCR8 = 201 +MIPS_REG_FCR9 = 202 +MIPS_REG_FCR10 = 203 +MIPS_REG_FCR11 = 204 +MIPS_REG_FCR12 = 205 +MIPS_REG_FCR13 = 206 +MIPS_REG_FCR14 = 207 +MIPS_REG_FCR15 = 208 +MIPS_REG_FCR16 = 209 +MIPS_REG_FCR17 = 210 +MIPS_REG_FCR18 = 211 +MIPS_REG_FCR19 = 212 +MIPS_REG_FCR20 = 213 +MIPS_REG_FCR21 = 214 +MIPS_REG_FCR22 = 215 +MIPS_REG_FCR23 = 216 +MIPS_REG_FCR24 = 217 +MIPS_REG_FCR25 = 218 +MIPS_REG_FCR26 = 219 +MIPS_REG_FCR27 = 220 +MIPS_REG_FCR28 = 221 +MIPS_REG_FCR29 = 222 +MIPS_REG_FCR30 = 223 +MIPS_REG_FCR31 = 224 +MIPS_REG_FP_64 = 225 +MIPS_REG_F_HI0 = 226 +MIPS_REG_F_HI1 = 227 +MIPS_REG_F_HI2 = 228 +MIPS_REG_F_HI3 = 229 +MIPS_REG_F_HI4 = 230 +MIPS_REG_F_HI5 = 231 +MIPS_REG_F_HI6 = 232 +MIPS_REG_F_HI7 = 233 +MIPS_REG_F_HI8 = 234 +MIPS_REG_F_HI9 = 235 +MIPS_REG_F_HI10 = 236 +MIPS_REG_F_HI11 = 237 +MIPS_REG_F_HI12 = 238 +MIPS_REG_F_HI13 = 239 +MIPS_REG_F_HI14 = 240 +MIPS_REG_F_HI15 = 241 +MIPS_REG_F_HI16 = 242 +MIPS_REG_F_HI17 = 243 +MIPS_REG_F_HI18 = 244 +MIPS_REG_F_HI19 = 245 +MIPS_REG_F_HI20 = 246 +MIPS_REG_F_HI21 = 247 +MIPS_REG_F_HI22 = 248 +MIPS_REG_F_HI23 = 249 +MIPS_REG_F_HI24 = 250 +MIPS_REG_F_HI25 = 251 +MIPS_REG_F_HI26 = 252 +MIPS_REG_F_HI27 = 253 +MIPS_REG_F_HI28 = 254 +MIPS_REG_F_HI29 = 255 +MIPS_REG_F_HI30 = 256 +MIPS_REG_F_HI31 = 257 +MIPS_REG_GP_64 = 258 +MIPS_REG_HI0 = 259 +MIPS_REG_HI1 = 260 +MIPS_REG_HI2 = 261 +MIPS_REG_HI3 = 262 +MIPS_REG_HWR0 = 263 +MIPS_REG_HWR1 = 264 +MIPS_REG_HWR2 = 265 +MIPS_REG_HWR3 = 266 +MIPS_REG_HWR4 = 267 +MIPS_REG_HWR5 = 268 +MIPS_REG_HWR6 = 269 +MIPS_REG_HWR7 = 270 +MIPS_REG_HWR8 = 271 +MIPS_REG_HWR9 = 272 +MIPS_REG_HWR10 = 273 +MIPS_REG_HWR11 = 274 +MIPS_REG_HWR12 = 275 +MIPS_REG_HWR13 = 276 +MIPS_REG_HWR14 = 277 +MIPS_REG_HWR15 = 278 +MIPS_REG_HWR16 = 279 +MIPS_REG_HWR17 = 280 +MIPS_REG_HWR18 = 281 +MIPS_REG_HWR19 = 282 +MIPS_REG_HWR20 = 283 +MIPS_REG_HWR21 = 284 +MIPS_REG_HWR22 = 285 +MIPS_REG_HWR23 = 286 +MIPS_REG_HWR24 = 287 +MIPS_REG_HWR25 = 288 +MIPS_REG_HWR26 = 289 +MIPS_REG_HWR27 = 290 +MIPS_REG_HWR28 = 291 +MIPS_REG_HWR29 = 292 +MIPS_REG_HWR30 = 293 +MIPS_REG_HWR31 = 294 +MIPS_REG_K0 = 295 +MIPS_REG_K1 = 296 +MIPS_REG_LO0 = 297 +MIPS_REG_LO1 = 298 +MIPS_REG_LO2 = 299 +MIPS_REG_LO3 = 300 +MIPS_REG_MPL0 = 301 +MIPS_REG_MPL1 = 302 +MIPS_REG_MPL2 = 303 +MIPS_REG_MSA8 = 304 +MIPS_REG_MSA9 = 305 +MIPS_REG_MSA10 = 306 +MIPS_REG_MSA11 = 307 +MIPS_REG_MSA12 = 308 +MIPS_REG_MSA13 = 309 +MIPS_REG_MSA14 = 310 +MIPS_REG_MSA15 = 311 +MIPS_REG_MSA16 = 312 +MIPS_REG_MSA17 = 313 +MIPS_REG_MSA18 = 314 +MIPS_REG_MSA19 = 315 +MIPS_REG_MSA20 = 316 +MIPS_REG_MSA21 = 317 +MIPS_REG_MSA22 = 318 +MIPS_REG_MSA23 = 319 +MIPS_REG_MSA24 = 320 +MIPS_REG_MSA25 = 321 +MIPS_REG_MSA26 = 322 +MIPS_REG_MSA27 = 323 +MIPS_REG_MSA28 = 324 +MIPS_REG_MSA29 = 325 +MIPS_REG_MSA30 = 326 +MIPS_REG_MSA31 = 327 +MIPS_REG_P0 = 328 +MIPS_REG_P1 = 329 +MIPS_REG_P2 = 330 +MIPS_REG_RA_64 = 331 +MIPS_REG_S0 = 332 +MIPS_REG_S1 = 333 +MIPS_REG_S2 = 334 +MIPS_REG_S3 = 335 +MIPS_REG_S4 = 336 +MIPS_REG_S5 = 337 +MIPS_REG_S6 = 338 +MIPS_REG_S7 = 339 +MIPS_REG_SP_64 = 340 +MIPS_REG_T0 = 341 +MIPS_REG_T1 = 342 +MIPS_REG_T2 = 343 +MIPS_REG_T3 = 344 +MIPS_REG_T4 = 345 +MIPS_REG_T5 = 346 +MIPS_REG_T6 = 347 +MIPS_REG_T7 = 348 +MIPS_REG_T8 = 349 +MIPS_REG_T9 = 350 +MIPS_REG_V0 = 351 +MIPS_REG_V1 = 352 +MIPS_REG_W0 = 353 +MIPS_REG_W1 = 354 +MIPS_REG_W2 = 355 +MIPS_REG_W3 = 356 +MIPS_REG_W4 = 357 +MIPS_REG_W5 = 358 +MIPS_REG_W6 = 359 +MIPS_REG_W7 = 360 +MIPS_REG_W8 = 361 +MIPS_REG_W9 = 362 +MIPS_REG_W10 = 363 +MIPS_REG_W11 = 364 +MIPS_REG_W12 = 365 +MIPS_REG_W13 = 366 +MIPS_REG_W14 = 367 +MIPS_REG_W15 = 368 +MIPS_REG_W16 = 369 +MIPS_REG_W17 = 370 +MIPS_REG_W18 = 371 +MIPS_REG_W19 = 372 +MIPS_REG_W20 = 373 +MIPS_REG_W21 = 374 +MIPS_REG_W22 = 375 +MIPS_REG_W23 = 376 +MIPS_REG_W24 = 377 +MIPS_REG_W25 = 378 +MIPS_REG_W26 = 379 +MIPS_REG_W27 = 380 +MIPS_REG_W28 = 381 +MIPS_REG_W29 = 382 +MIPS_REG_W30 = 383 +MIPS_REG_W31 = 384 +MIPS_REG_ZERO_64 = 385 +MIPS_REG_A0_NM = 386 +MIPS_REG_A1_NM = 387 +MIPS_REG_A2_NM = 388 +MIPS_REG_A3_NM = 389 +MIPS_REG_A4_NM = 390 +MIPS_REG_A5_NM = 391 +MIPS_REG_A6_NM = 392 +MIPS_REG_A7_NM = 393 +MIPS_REG_COP0SEL_BADINST = 394 +MIPS_REG_COP0SEL_BADINSTRP = 395 +MIPS_REG_COP0SEL_BADINSTRX = 396 +MIPS_REG_COP0SEL_BADVADDR = 397 +MIPS_REG_COP0SEL_BEVVA = 398 +MIPS_REG_COP0SEL_CACHEERR = 399 +MIPS_REG_COP0SEL_CAUSE = 400 +MIPS_REG_COP0SEL_CDMMBASE = 401 +MIPS_REG_COP0SEL_CMGCRBASE = 402 +MIPS_REG_COP0SEL_COMPARE = 403 +MIPS_REG_COP0SEL_CONFIG = 404 +MIPS_REG_COP0SEL_CONTEXT = 405 +MIPS_REG_COP0SEL_CONTEXTCONFIG = 406 +MIPS_REG_COP0SEL_COUNT = 407 +MIPS_REG_COP0SEL_DDATAHI = 408 +MIPS_REG_COP0SEL_DDATALO = 409 +MIPS_REG_COP0SEL_DEBUG = 410 +MIPS_REG_COP0SEL_DEBUGCONTEXTID = 411 +MIPS_REG_COP0SEL_DEPC = 412 +MIPS_REG_COP0SEL_DESAVE = 413 +MIPS_REG_COP0SEL_DTAGHI = 414 +MIPS_REG_COP0SEL_DTAGLO = 415 +MIPS_REG_COP0SEL_EBASE = 416 +MIPS_REG_COP0SEL_ENTRYHI = 417 +MIPS_REG_COP0SEL_EPC = 418 +MIPS_REG_COP0SEL_ERRCTL = 419 +MIPS_REG_COP0SEL_ERROREPC = 420 +MIPS_REG_COP0SEL_GLOBALNUMBER = 421 +MIPS_REG_COP0SEL_GTOFFSET = 422 +MIPS_REG_COP0SEL_HWRENA = 423 +MIPS_REG_COP0SEL_IDATAHI = 424 +MIPS_REG_COP0SEL_IDATALO = 425 +MIPS_REG_COP0SEL_INDEX = 426 +MIPS_REG_COP0SEL_INTCTL = 427 +MIPS_REG_COP0SEL_ITAGHI = 428 +MIPS_REG_COP0SEL_ITAGLO = 429 +MIPS_REG_COP0SEL_LLADDR = 430 +MIPS_REG_COP0SEL_MAAR = 431 +MIPS_REG_COP0SEL_MAARI = 432 +MIPS_REG_COP0SEL_MEMORYMAPID = 433 +MIPS_REG_COP0SEL_MVPCONTROL = 434 +MIPS_REG_COP0SEL_NESTEDEPC = 435 +MIPS_REG_COP0SEL_NESTEDEXC = 436 +MIPS_REG_COP0SEL_PAGEGRAIN = 437 +MIPS_REG_COP0SEL_PAGEMASK = 438 +MIPS_REG_COP0SEL_PRID = 439 +MIPS_REG_COP0SEL_PWBASE = 440 +MIPS_REG_COP0SEL_PWCTL = 441 +MIPS_REG_COP0SEL_PWFIELD = 442 +MIPS_REG_COP0SEL_PWSIZE = 443 +MIPS_REG_COP0SEL_RANDOM = 444 +MIPS_REG_COP0SEL_SRSCTL = 445 +MIPS_REG_COP0SEL_SRSMAP = 446 +MIPS_REG_COP0SEL_STATUS = 447 +MIPS_REG_COP0SEL_TCBIND = 448 +MIPS_REG_COP0SEL_TCCONTEXT = 449 +MIPS_REG_COP0SEL_TCHALT = 450 +MIPS_REG_COP0SEL_TCOPT = 451 +MIPS_REG_COP0SEL_TCRESTART = 452 +MIPS_REG_COP0SEL_TCSCHEDULE = 453 +MIPS_REG_COP0SEL_TCSCHEFBACK = 454 +MIPS_REG_COP0SEL_TCSTATUS = 455 +MIPS_REG_COP0SEL_TRACECONTROL = 456 +MIPS_REG_COP0SEL_TRACEDBPC = 457 +MIPS_REG_COP0SEL_TRACEIBPC = 458 +MIPS_REG_COP0SEL_USERLOCAL = 459 +MIPS_REG_COP0SEL_VIEW_IPL = 460 +MIPS_REG_COP0SEL_VIEW_RIPL = 461 +MIPS_REG_COP0SEL_VPCONTROL = 462 +MIPS_REG_COP0SEL_VPECONTROL = 463 +MIPS_REG_COP0SEL_VPEOPT = 464 +MIPS_REG_COP0SEL_VPESCHEDULE = 465 +MIPS_REG_COP0SEL_VPESCHEFBACK = 466 +MIPS_REG_COP0SEL_WIRED = 467 +MIPS_REG_COP0SEL_XCONTEXT = 468 +MIPS_REG_COP0SEL_XCONTEXTCONFIG = 469 +MIPS_REG_COP0SEL_YQMASK = 470 +MIPS_REG_K0_NM = 471 +MIPS_REG_K1_NM = 472 +MIPS_REG_S0_NM = 473 +MIPS_REG_S1_NM = 474 +MIPS_REG_S2_NM = 475 +MIPS_REG_S3_NM = 476 +MIPS_REG_S4_NM = 477 +MIPS_REG_S5_NM = 478 +MIPS_REG_S6_NM = 479 +MIPS_REG_S7_NM = 480 +MIPS_REG_T0_NM = 481 +MIPS_REG_T1_NM = 482 +MIPS_REG_T2_NM = 483 +MIPS_REG_T3_NM = 484 +MIPS_REG_T4_NM = 485 +MIPS_REG_T5_NM = 486 +MIPS_REG_T8_NM = 487 +MIPS_REG_T9_NM = 488 +MIPS_REG_A0_64 = 489 +MIPS_REG_A1_64 = 490 +MIPS_REG_A2_64 = 491 +MIPS_REG_A3_64 = 492 +MIPS_REG_AC0_64 = 493 +MIPS_REG_COP0SEL_CONFIG1 = 494 +MIPS_REG_COP0SEL_CONFIG2 = 495 +MIPS_REG_COP0SEL_CONFIG3 = 496 +MIPS_REG_COP0SEL_CONFIG4 = 497 +MIPS_REG_COP0SEL_CONFIG5 = 498 +MIPS_REG_COP0SEL_DEBUG2 = 499 +MIPS_REG_COP0SEL_ENTRYLO0 = 500 +MIPS_REG_COP0SEL_ENTRYLO1 = 501 +MIPS_REG_COP0SEL_GUESTCTL0 = 502 +MIPS_REG_COP0SEL_GUESTCTL1 = 503 +MIPS_REG_COP0SEL_GUESTCTL2 = 504 +MIPS_REG_COP0SEL_GUESTCTL3 = 505 +MIPS_REG_COP0SEL_KSCRATCH1 = 506 +MIPS_REG_COP0SEL_KSCRATCH2 = 507 +MIPS_REG_COP0SEL_KSCRATCH3 = 508 +MIPS_REG_COP0SEL_KSCRATCH4 = 509 +MIPS_REG_COP0SEL_KSCRATCH5 = 510 +MIPS_REG_COP0SEL_KSCRATCH6 = 511 +MIPS_REG_COP0SEL_MVPCONF0 = 512 +MIPS_REG_COP0SEL_MVPCONF1 = 513 +MIPS_REG_COP0SEL_PERFCNT0 = 514 +MIPS_REG_COP0SEL_PERFCNT1 = 515 +MIPS_REG_COP0SEL_PERFCNT2 = 516 +MIPS_REG_COP0SEL_PERFCNT3 = 517 +MIPS_REG_COP0SEL_PERFCNT4 = 518 +MIPS_REG_COP0SEL_PERFCNT5 = 519 +MIPS_REG_COP0SEL_PERFCNT6 = 520 +MIPS_REG_COP0SEL_PERFCNT7 = 521 +MIPS_REG_COP0SEL_PERFCTL0 = 522 +MIPS_REG_COP0SEL_PERFCTL1 = 523 +MIPS_REG_COP0SEL_PERFCTL2 = 524 +MIPS_REG_COP0SEL_PERFCTL3 = 525 +MIPS_REG_COP0SEL_PERFCTL4 = 526 +MIPS_REG_COP0SEL_PERFCTL5 = 527 +MIPS_REG_COP0SEL_PERFCTL6 = 528 +MIPS_REG_COP0SEL_PERFCTL7 = 529 +MIPS_REG_COP0SEL_SEGCTL0 = 530 +MIPS_REG_COP0SEL_SEGCTL1 = 531 +MIPS_REG_COP0SEL_SEGCTL2 = 532 +MIPS_REG_COP0SEL_SRSCONF0 = 533 +MIPS_REG_COP0SEL_SRSCONF1 = 534 +MIPS_REG_COP0SEL_SRSCONF2 = 535 +MIPS_REG_COP0SEL_SRSCONF3 = 536 +MIPS_REG_COP0SEL_SRSCONF4 = 537 +MIPS_REG_COP0SEL_SRSMAP2 = 538 +MIPS_REG_COP0SEL_TRACECONTROL2 = 539 +MIPS_REG_COP0SEL_TRACECONTROL3 = 540 +MIPS_REG_COP0SEL_USERTRACEDATA1 = 541 +MIPS_REG_COP0SEL_USERTRACEDATA2 = 542 +MIPS_REG_COP0SEL_VPECONF0 = 543 +MIPS_REG_COP0SEL_VPECONF1 = 544 +MIPS_REG_COP0SEL_WATCHHI0 = 545 +MIPS_REG_COP0SEL_WATCHHI1 = 546 +MIPS_REG_COP0SEL_WATCHHI2 = 547 +MIPS_REG_COP0SEL_WATCHHI3 = 548 +MIPS_REG_COP0SEL_WATCHHI4 = 549 +MIPS_REG_COP0SEL_WATCHHI5 = 550 +MIPS_REG_COP0SEL_WATCHHI6 = 551 +MIPS_REG_COP0SEL_WATCHHI7 = 552 +MIPS_REG_COP0SEL_WATCHHI8 = 553 +MIPS_REG_COP0SEL_WATCHHI9 = 554 +MIPS_REG_COP0SEL_WATCHHI10 = 555 +MIPS_REG_COP0SEL_WATCHHI11 = 556 +MIPS_REG_COP0SEL_WATCHHI12 = 557 +MIPS_REG_COP0SEL_WATCHHI13 = 558 +MIPS_REG_COP0SEL_WATCHHI14 = 559 +MIPS_REG_COP0SEL_WATCHHI15 = 560 +MIPS_REG_COP0SEL_WATCHLO0 = 561 +MIPS_REG_COP0SEL_WATCHLO1 = 562 +MIPS_REG_COP0SEL_WATCHLO2 = 563 +MIPS_REG_COP0SEL_WATCHLO3 = 564 +MIPS_REG_COP0SEL_WATCHLO4 = 565 +MIPS_REG_COP0SEL_WATCHLO5 = 566 +MIPS_REG_COP0SEL_WATCHLO6 = 567 +MIPS_REG_COP0SEL_WATCHLO7 = 568 +MIPS_REG_COP0SEL_WATCHLO8 = 569 +MIPS_REG_COP0SEL_WATCHLO9 = 570 +MIPS_REG_COP0SEL_WATCHLO10 = 571 +MIPS_REG_COP0SEL_WATCHLO11 = 572 +MIPS_REG_COP0SEL_WATCHLO12 = 573 +MIPS_REG_COP0SEL_WATCHLO13 = 574 +MIPS_REG_COP0SEL_WATCHLO14 = 575 +MIPS_REG_COP0SEL_WATCHLO15 = 576 +MIPS_REG_D0_64 = 577 +MIPS_REG_D1_64 = 578 +MIPS_REG_D2_64 = 579 +MIPS_REG_D3_64 = 580 +MIPS_REG_D4_64 = 581 +MIPS_REG_D5_64 = 582 +MIPS_REG_D6_64 = 583 +MIPS_REG_D7_64 = 584 +MIPS_REG_D8_64 = 585 +MIPS_REG_D9_64 = 586 +MIPS_REG_D10_64 = 587 +MIPS_REG_D11_64 = 588 +MIPS_REG_D12_64 = 589 +MIPS_REG_D13_64 = 590 +MIPS_REG_D14_64 = 591 +MIPS_REG_D15_64 = 592 +MIPS_REG_D16_64 = 593 +MIPS_REG_D17_64 = 594 +MIPS_REG_D18_64 = 595 +MIPS_REG_D19_64 = 596 +MIPS_REG_D20_64 = 597 +MIPS_REG_D21_64 = 598 +MIPS_REG_D22_64 = 599 +MIPS_REG_D23_64 = 600 +MIPS_REG_D24_64 = 601 +MIPS_REG_D25_64 = 602 +MIPS_REG_D26_64 = 603 +MIPS_REG_D27_64 = 604 +MIPS_REG_D28_64 = 605 +MIPS_REG_D29_64 = 606 +MIPS_REG_D30_64 = 607 +MIPS_REG_D31_64 = 608 +MIPS_REG_DSPOUTFLAG16_19 = 609 +MIPS_REG_HI0_64 = 610 +MIPS_REG_K0_64 = 611 +MIPS_REG_K1_64 = 612 +MIPS_REG_LO0_64 = 613 +MIPS_REG_S0_64 = 614 +MIPS_REG_S1_64 = 615 +MIPS_REG_S2_64 = 616 +MIPS_REG_S3_64 = 617 +MIPS_REG_S4_64 = 618 +MIPS_REG_S5_64 = 619 +MIPS_REG_S6_64 = 620 +MIPS_REG_S7_64 = 621 +MIPS_REG_T0_64 = 622 +MIPS_REG_T1_64 = 623 +MIPS_REG_T2_64 = 624 +MIPS_REG_T3_64 = 625 +MIPS_REG_T4_64 = 626 +MIPS_REG_T5_64 = 627 +MIPS_REG_T6_64 = 628 +MIPS_REG_T7_64 = 629 +MIPS_REG_T8_64 = 630 +MIPS_REG_T9_64 = 631 +MIPS_REG_V0_64 = 632 +MIPS_REG_V1_64 = 633 +MIPS_REG_COP0SEL_GUESTCTL0EXT = 634 +MIPS_REG_ENDING = 635 MIPS_INS_INVALID = 0 -MIPS_INS_ABSQ_S = 1 -MIPS_INS_ADD = 2 -MIPS_INS_ADDIUPC = 3 -MIPS_INS_ADDIUR1SP = 4 -MIPS_INS_ADDIUR2 = 5 -MIPS_INS_ADDIUS5 = 6 -MIPS_INS_ADDIUSP = 7 -MIPS_INS_ADDQH = 8 -MIPS_INS_ADDQH_R = 9 -MIPS_INS_ADDQ = 10 -MIPS_INS_ADDQ_S = 11 -MIPS_INS_ADDSC = 12 -MIPS_INS_ADDS_A = 13 -MIPS_INS_ADDS_S = 14 -MIPS_INS_ADDS_U = 15 -MIPS_INS_ADDU16 = 16 -MIPS_INS_ADDUH = 17 -MIPS_INS_ADDUH_R = 18 -MIPS_INS_ADDU = 19 -MIPS_INS_ADDU_S = 20 -MIPS_INS_ADDVI = 21 -MIPS_INS_ADDV = 22 -MIPS_INS_ADDWC = 23 -MIPS_INS_ADD_A = 24 -MIPS_INS_ADDI = 25 -MIPS_INS_ADDIU = 26 -MIPS_INS_ALIGN = 27 -MIPS_INS_ALUIPC = 28 -MIPS_INS_AND = 29 -MIPS_INS_AND16 = 30 -MIPS_INS_ANDI16 = 31 -MIPS_INS_ANDI = 32 -MIPS_INS_APPEND = 33 -MIPS_INS_ASUB_S = 34 -MIPS_INS_ASUB_U = 35 -MIPS_INS_AUI = 36 -MIPS_INS_AUIPC = 37 -MIPS_INS_AVER_S = 38 -MIPS_INS_AVER_U = 39 -MIPS_INS_AVE_S = 40 -MIPS_INS_AVE_U = 41 -MIPS_INS_B16 = 42 -MIPS_INS_BADDU = 43 -MIPS_INS_BAL = 44 -MIPS_INS_BALC = 45 -MIPS_INS_BALIGN = 46 -MIPS_INS_BBIT0 = 47 -MIPS_INS_BBIT032 = 48 -MIPS_INS_BBIT1 = 49 -MIPS_INS_BBIT132 = 50 -MIPS_INS_BC = 51 -MIPS_INS_BC0F = 52 -MIPS_INS_BC0FL = 53 -MIPS_INS_BC0T = 54 -MIPS_INS_BC0TL = 55 -MIPS_INS_BC1EQZ = 56 -MIPS_INS_BC1F = 57 -MIPS_INS_BC1FL = 58 -MIPS_INS_BC1NEZ = 59 -MIPS_INS_BC1T = 60 -MIPS_INS_BC1TL = 61 -MIPS_INS_BC2EQZ = 62 -MIPS_INS_BC2F = 63 -MIPS_INS_BC2FL = 64 -MIPS_INS_BC2NEZ = 65 -MIPS_INS_BC2T = 66 -MIPS_INS_BC2TL = 67 -MIPS_INS_BC3F = 68 -MIPS_INS_BC3FL = 69 -MIPS_INS_BC3T = 70 -MIPS_INS_BC3TL = 71 -MIPS_INS_BCLRI = 72 -MIPS_INS_BCLR = 73 -MIPS_INS_BEQ = 74 -MIPS_INS_BEQC = 75 -MIPS_INS_BEQL = 76 -MIPS_INS_BEQZ16 = 77 -MIPS_INS_BEQZALC = 78 -MIPS_INS_BEQZC = 79 -MIPS_INS_BGEC = 80 -MIPS_INS_BGEUC = 81 -MIPS_INS_BGEZ = 82 -MIPS_INS_BGEZAL = 83 -MIPS_INS_BGEZALC = 84 -MIPS_INS_BGEZALL = 85 -MIPS_INS_BGEZALS = 86 -MIPS_INS_BGEZC = 87 -MIPS_INS_BGEZL = 88 -MIPS_INS_BGTZ = 89 -MIPS_INS_BGTZALC = 90 -MIPS_INS_BGTZC = 91 -MIPS_INS_BGTZL = 92 -MIPS_INS_BINSLI = 93 -MIPS_INS_BINSL = 94 -MIPS_INS_BINSRI = 95 -MIPS_INS_BINSR = 96 -MIPS_INS_BITREV = 97 -MIPS_INS_BITSWAP = 98 -MIPS_INS_BLEZ = 99 -MIPS_INS_BLEZALC = 100 -MIPS_INS_BLEZC = 101 -MIPS_INS_BLEZL = 102 -MIPS_INS_BLTC = 103 -MIPS_INS_BLTUC = 104 -MIPS_INS_BLTZ = 105 -MIPS_INS_BLTZAL = 106 -MIPS_INS_BLTZALC = 107 -MIPS_INS_BLTZALL = 108 -MIPS_INS_BLTZALS = 109 -MIPS_INS_BLTZC = 110 -MIPS_INS_BLTZL = 111 -MIPS_INS_BMNZI = 112 -MIPS_INS_BMNZ = 113 -MIPS_INS_BMZI = 114 -MIPS_INS_BMZ = 115 -MIPS_INS_BNE = 116 -MIPS_INS_BNEC = 117 -MIPS_INS_BNEGI = 118 -MIPS_INS_BNEG = 119 -MIPS_INS_BNEL = 120 -MIPS_INS_BNEZ16 = 121 -MIPS_INS_BNEZALC = 122 -MIPS_INS_BNEZC = 123 -MIPS_INS_BNVC = 124 -MIPS_INS_BNZ = 125 -MIPS_INS_BOVC = 126 -MIPS_INS_BPOSGE32 = 127 -MIPS_INS_BREAK = 128 -MIPS_INS_BREAK16 = 129 -MIPS_INS_BSELI = 130 -MIPS_INS_BSEL = 131 -MIPS_INS_BSETI = 132 -MIPS_INS_BSET = 133 -MIPS_INS_BZ = 134 -MIPS_INS_BEQZ = 135 -MIPS_INS_B = 136 -MIPS_INS_BNEZ = 137 -MIPS_INS_BTEQZ = 138 -MIPS_INS_BTNEZ = 139 -MIPS_INS_CACHE = 140 -MIPS_INS_CEIL = 141 -MIPS_INS_CEQI = 142 -MIPS_INS_CEQ = 143 -MIPS_INS_CFC1 = 144 -MIPS_INS_CFCMSA = 145 -MIPS_INS_CINS = 146 -MIPS_INS_CINS32 = 147 -MIPS_INS_CLASS = 148 -MIPS_INS_CLEI_S = 149 -MIPS_INS_CLEI_U = 150 -MIPS_INS_CLE_S = 151 -MIPS_INS_CLE_U = 152 -MIPS_INS_CLO = 153 -MIPS_INS_CLTI_S = 154 -MIPS_INS_CLTI_U = 155 -MIPS_INS_CLT_S = 156 -MIPS_INS_CLT_U = 157 -MIPS_INS_CLZ = 158 -MIPS_INS_CMPGDU = 159 -MIPS_INS_CMPGU = 160 -MIPS_INS_CMPU = 161 -MIPS_INS_CMP = 162 -MIPS_INS_COPY_S = 163 -MIPS_INS_COPY_U = 164 -MIPS_INS_CTC1 = 165 -MIPS_INS_CTCMSA = 166 -MIPS_INS_CVT = 167 -MIPS_INS_C = 168 -MIPS_INS_CMPI = 169 -MIPS_INS_DADD = 170 -MIPS_INS_DADDI = 171 -MIPS_INS_DADDIU = 172 -MIPS_INS_DADDU = 173 -MIPS_INS_DAHI = 174 -MIPS_INS_DALIGN = 175 -MIPS_INS_DATI = 176 -MIPS_INS_DAUI = 177 -MIPS_INS_DBITSWAP = 178 -MIPS_INS_DCLO = 179 -MIPS_INS_DCLZ = 180 -MIPS_INS_DDIV = 181 -MIPS_INS_DDIVU = 182 -MIPS_INS_DERET = 183 -MIPS_INS_DEXT = 184 -MIPS_INS_DEXTM = 185 -MIPS_INS_DEXTU = 186 -MIPS_INS_DI = 187 -MIPS_INS_DINS = 188 -MIPS_INS_DINSM = 189 -MIPS_INS_DINSU = 190 -MIPS_INS_DIV = 191 -MIPS_INS_DIVU = 192 -MIPS_INS_DIV_S = 193 -MIPS_INS_DIV_U = 194 -MIPS_INS_DLSA = 195 -MIPS_INS_DMFC0 = 196 -MIPS_INS_DMFC1 = 197 -MIPS_INS_DMFC2 = 198 -MIPS_INS_DMOD = 199 -MIPS_INS_DMODU = 200 -MIPS_INS_DMTC0 = 201 -MIPS_INS_DMTC1 = 202 -MIPS_INS_DMTC2 = 203 -MIPS_INS_DMUH = 204 -MIPS_INS_DMUHU = 205 -MIPS_INS_DMUL = 206 -MIPS_INS_DMULT = 207 -MIPS_INS_DMULTU = 208 -MIPS_INS_DMULU = 209 -MIPS_INS_DOTP_S = 210 -MIPS_INS_DOTP_U = 211 -MIPS_INS_DPADD_S = 212 -MIPS_INS_DPADD_U = 213 -MIPS_INS_DPAQX_SA = 214 -MIPS_INS_DPAQX_S = 215 -MIPS_INS_DPAQ_SA = 216 -MIPS_INS_DPAQ_S = 217 -MIPS_INS_DPAU = 218 -MIPS_INS_DPAX = 219 -MIPS_INS_DPA = 220 -MIPS_INS_DPOP = 221 -MIPS_INS_DPSQX_SA = 222 -MIPS_INS_DPSQX_S = 223 -MIPS_INS_DPSQ_SA = 224 -MIPS_INS_DPSQ_S = 225 -MIPS_INS_DPSUB_S = 226 -MIPS_INS_DPSUB_U = 227 -MIPS_INS_DPSU = 228 -MIPS_INS_DPSX = 229 -MIPS_INS_DPS = 230 -MIPS_INS_DROTR = 231 -MIPS_INS_DROTR32 = 232 -MIPS_INS_DROTRV = 233 -MIPS_INS_DSBH = 234 -MIPS_INS_DSHD = 235 -MIPS_INS_DSLL = 236 -MIPS_INS_DSLL32 = 237 -MIPS_INS_DSLLV = 238 -MIPS_INS_DSRA = 239 -MIPS_INS_DSRA32 = 240 -MIPS_INS_DSRAV = 241 -MIPS_INS_DSRL = 242 -MIPS_INS_DSRL32 = 243 -MIPS_INS_DSRLV = 244 -MIPS_INS_DSUB = 245 -MIPS_INS_DSUBU = 246 -MIPS_INS_EHB = 247 -MIPS_INS_EI = 248 -MIPS_INS_ERET = 249 -MIPS_INS_EXT = 250 -MIPS_INS_EXTP = 251 -MIPS_INS_EXTPDP = 252 -MIPS_INS_EXTPDPV = 253 -MIPS_INS_EXTPV = 254 -MIPS_INS_EXTRV_RS = 255 -MIPS_INS_EXTRV_R = 256 -MIPS_INS_EXTRV_S = 257 -MIPS_INS_EXTRV = 258 -MIPS_INS_EXTR_RS = 259 -MIPS_INS_EXTR_R = 260 -MIPS_INS_EXTR_S = 261 -MIPS_INS_EXTR = 262 -MIPS_INS_EXTS = 263 -MIPS_INS_EXTS32 = 264 -MIPS_INS_ABS = 265 -MIPS_INS_FADD = 266 -MIPS_INS_FCAF = 267 -MIPS_INS_FCEQ = 268 -MIPS_INS_FCLASS = 269 -MIPS_INS_FCLE = 270 -MIPS_INS_FCLT = 271 -MIPS_INS_FCNE = 272 -MIPS_INS_FCOR = 273 -MIPS_INS_FCUEQ = 274 -MIPS_INS_FCULE = 275 -MIPS_INS_FCULT = 276 -MIPS_INS_FCUNE = 277 -MIPS_INS_FCUN = 278 -MIPS_INS_FDIV = 279 -MIPS_INS_FEXDO = 280 -MIPS_INS_FEXP2 = 281 -MIPS_INS_FEXUPL = 282 -MIPS_INS_FEXUPR = 283 -MIPS_INS_FFINT_S = 284 -MIPS_INS_FFINT_U = 285 -MIPS_INS_FFQL = 286 -MIPS_INS_FFQR = 287 -MIPS_INS_FILL = 288 -MIPS_INS_FLOG2 = 289 -MIPS_INS_FLOOR = 290 -MIPS_INS_FMADD = 291 -MIPS_INS_FMAX_A = 292 -MIPS_INS_FMAX = 293 -MIPS_INS_FMIN_A = 294 -MIPS_INS_FMIN = 295 -MIPS_INS_MOV = 296 -MIPS_INS_FMSUB = 297 -MIPS_INS_FMUL = 298 -MIPS_INS_MUL = 299 -MIPS_INS_NEG = 300 -MIPS_INS_FRCP = 301 -MIPS_INS_FRINT = 302 -MIPS_INS_FRSQRT = 303 -MIPS_INS_FSAF = 304 -MIPS_INS_FSEQ = 305 -MIPS_INS_FSLE = 306 -MIPS_INS_FSLT = 307 -MIPS_INS_FSNE = 308 -MIPS_INS_FSOR = 309 -MIPS_INS_FSQRT = 310 -MIPS_INS_SQRT = 311 -MIPS_INS_FSUB = 312 -MIPS_INS_SUB = 313 -MIPS_INS_FSUEQ = 314 -MIPS_INS_FSULE = 315 -MIPS_INS_FSULT = 316 -MIPS_INS_FSUNE = 317 -MIPS_INS_FSUN = 318 -MIPS_INS_FTINT_S = 319 -MIPS_INS_FTINT_U = 320 -MIPS_INS_FTQ = 321 -MIPS_INS_FTRUNC_S = 322 -MIPS_INS_FTRUNC_U = 323 -MIPS_INS_HADD_S = 324 -MIPS_INS_HADD_U = 325 -MIPS_INS_HSUB_S = 326 -MIPS_INS_HSUB_U = 327 -MIPS_INS_ILVEV = 328 -MIPS_INS_ILVL = 329 -MIPS_INS_ILVOD = 330 -MIPS_INS_ILVR = 331 -MIPS_INS_INS = 332 -MIPS_INS_INSERT = 333 -MIPS_INS_INSV = 334 -MIPS_INS_INSVE = 335 -MIPS_INS_J = 336 -MIPS_INS_JAL = 337 -MIPS_INS_JALR = 338 -MIPS_INS_JALRS16 = 339 -MIPS_INS_JALRS = 340 -MIPS_INS_JALS = 341 -MIPS_INS_JALX = 342 -MIPS_INS_JIALC = 343 -MIPS_INS_JIC = 344 -MIPS_INS_JR = 345 -MIPS_INS_JR16 = 346 -MIPS_INS_JRADDIUSP = 347 -MIPS_INS_JRC = 348 -MIPS_INS_JALRC = 349 -MIPS_INS_LB = 350 -MIPS_INS_LBU16 = 351 -MIPS_INS_LBUX = 352 -MIPS_INS_LBU = 353 -MIPS_INS_LD = 354 -MIPS_INS_LDC1 = 355 -MIPS_INS_LDC2 = 356 -MIPS_INS_LDC3 = 357 -MIPS_INS_LDI = 358 -MIPS_INS_LDL = 359 -MIPS_INS_LDPC = 360 -MIPS_INS_LDR = 361 -MIPS_INS_LDXC1 = 362 -MIPS_INS_LH = 363 -MIPS_INS_LHU16 = 364 -MIPS_INS_LHX = 365 -MIPS_INS_LHU = 366 -MIPS_INS_LI16 = 367 -MIPS_INS_LL = 368 -MIPS_INS_LLD = 369 -MIPS_INS_LSA = 370 -MIPS_INS_LUXC1 = 371 -MIPS_INS_LUI = 372 -MIPS_INS_LW = 373 -MIPS_INS_LW16 = 374 -MIPS_INS_LWC1 = 375 -MIPS_INS_LWC2 = 376 -MIPS_INS_LWC3 = 377 -MIPS_INS_LWL = 378 -MIPS_INS_LWM16 = 379 -MIPS_INS_LWM32 = 380 -MIPS_INS_LWPC = 381 -MIPS_INS_LWP = 382 -MIPS_INS_LWR = 383 -MIPS_INS_LWUPC = 384 -MIPS_INS_LWU = 385 -MIPS_INS_LWX = 386 -MIPS_INS_LWXC1 = 387 -MIPS_INS_LWXS = 388 -MIPS_INS_LI = 389 -MIPS_INS_MADD = 390 -MIPS_INS_MADDF = 391 -MIPS_INS_MADDR_Q = 392 -MIPS_INS_MADDU = 393 -MIPS_INS_MADDV = 394 -MIPS_INS_MADD_Q = 395 -MIPS_INS_MAQ_SA = 396 -MIPS_INS_MAQ_S = 397 -MIPS_INS_MAXA = 398 -MIPS_INS_MAXI_S = 399 -MIPS_INS_MAXI_U = 400 -MIPS_INS_MAX_A = 401 -MIPS_INS_MAX = 402 -MIPS_INS_MAX_S = 403 -MIPS_INS_MAX_U = 404 -MIPS_INS_MFC0 = 405 -MIPS_INS_MFC1 = 406 -MIPS_INS_MFC2 = 407 -MIPS_INS_MFHC1 = 408 -MIPS_INS_MFHI = 409 -MIPS_INS_MFLO = 410 -MIPS_INS_MINA = 411 -MIPS_INS_MINI_S = 412 -MIPS_INS_MINI_U = 413 -MIPS_INS_MIN_A = 414 -MIPS_INS_MIN = 415 -MIPS_INS_MIN_S = 416 -MIPS_INS_MIN_U = 417 -MIPS_INS_MOD = 418 -MIPS_INS_MODSUB = 419 -MIPS_INS_MODU = 420 -MIPS_INS_MOD_S = 421 -MIPS_INS_MOD_U = 422 -MIPS_INS_MOVE = 423 -MIPS_INS_MOVEP = 424 -MIPS_INS_MOVF = 425 -MIPS_INS_MOVN = 426 -MIPS_INS_MOVT = 427 -MIPS_INS_MOVZ = 428 -MIPS_INS_MSUB = 429 -MIPS_INS_MSUBF = 430 -MIPS_INS_MSUBR_Q = 431 -MIPS_INS_MSUBU = 432 -MIPS_INS_MSUBV = 433 -MIPS_INS_MSUB_Q = 434 -MIPS_INS_MTC0 = 435 -MIPS_INS_MTC1 = 436 -MIPS_INS_MTC2 = 437 -MIPS_INS_MTHC1 = 438 -MIPS_INS_MTHI = 439 -MIPS_INS_MTHLIP = 440 -MIPS_INS_MTLO = 441 -MIPS_INS_MTM0 = 442 -MIPS_INS_MTM1 = 443 -MIPS_INS_MTM2 = 444 -MIPS_INS_MTP0 = 445 -MIPS_INS_MTP1 = 446 -MIPS_INS_MTP2 = 447 -MIPS_INS_MUH = 448 -MIPS_INS_MUHU = 449 -MIPS_INS_MULEQ_S = 450 -MIPS_INS_MULEU_S = 451 -MIPS_INS_MULQ_RS = 452 -MIPS_INS_MULQ_S = 453 -MIPS_INS_MULR_Q = 454 -MIPS_INS_MULSAQ_S = 455 -MIPS_INS_MULSA = 456 -MIPS_INS_MULT = 457 -MIPS_INS_MULTU = 458 -MIPS_INS_MULU = 459 -MIPS_INS_MULV = 460 -MIPS_INS_MUL_Q = 461 -MIPS_INS_MUL_S = 462 -MIPS_INS_NLOC = 463 -MIPS_INS_NLZC = 464 -MIPS_INS_NMADD = 465 -MIPS_INS_NMSUB = 466 -MIPS_INS_NOR = 467 -MIPS_INS_NORI = 468 -MIPS_INS_NOT16 = 469 -MIPS_INS_NOT = 470 -MIPS_INS_OR = 471 -MIPS_INS_OR16 = 472 -MIPS_INS_ORI = 473 -MIPS_INS_PACKRL = 474 -MIPS_INS_PAUSE = 475 -MIPS_INS_PCKEV = 476 -MIPS_INS_PCKOD = 477 -MIPS_INS_PCNT = 478 -MIPS_INS_PICK = 479 -MIPS_INS_POP = 480 -MIPS_INS_PRECEQU = 481 -MIPS_INS_PRECEQ = 482 -MIPS_INS_PRECEU = 483 -MIPS_INS_PRECRQU_S = 484 -MIPS_INS_PRECRQ = 485 -MIPS_INS_PRECRQ_RS = 486 -MIPS_INS_PRECR = 487 -MIPS_INS_PRECR_SRA = 488 -MIPS_INS_PRECR_SRA_R = 489 -MIPS_INS_PREF = 490 -MIPS_INS_PREPEND = 491 -MIPS_INS_RADDU = 492 -MIPS_INS_RDDSP = 493 -MIPS_INS_RDHWR = 494 -MIPS_INS_REPLV = 495 -MIPS_INS_REPL = 496 -MIPS_INS_RINT = 497 -MIPS_INS_ROTR = 498 -MIPS_INS_ROTRV = 499 -MIPS_INS_ROUND = 500 -MIPS_INS_SAT_S = 501 -MIPS_INS_SAT_U = 502 -MIPS_INS_SB = 503 -MIPS_INS_SB16 = 504 -MIPS_INS_SC = 505 -MIPS_INS_SCD = 506 -MIPS_INS_SD = 507 -MIPS_INS_SDBBP = 508 -MIPS_INS_SDBBP16 = 509 -MIPS_INS_SDC1 = 510 -MIPS_INS_SDC2 = 511 -MIPS_INS_SDC3 = 512 -MIPS_INS_SDL = 513 -MIPS_INS_SDR = 514 -MIPS_INS_SDXC1 = 515 -MIPS_INS_SEB = 516 -MIPS_INS_SEH = 517 -MIPS_INS_SELEQZ = 518 -MIPS_INS_SELNEZ = 519 -MIPS_INS_SEL = 520 -MIPS_INS_SEQ = 521 -MIPS_INS_SEQI = 522 -MIPS_INS_SH = 523 -MIPS_INS_SH16 = 524 -MIPS_INS_SHF = 525 -MIPS_INS_SHILO = 526 -MIPS_INS_SHILOV = 527 -MIPS_INS_SHLLV = 528 -MIPS_INS_SHLLV_S = 529 -MIPS_INS_SHLL = 530 -MIPS_INS_SHLL_S = 531 -MIPS_INS_SHRAV = 532 -MIPS_INS_SHRAV_R = 533 -MIPS_INS_SHRA = 534 -MIPS_INS_SHRA_R = 535 -MIPS_INS_SHRLV = 536 -MIPS_INS_SHRL = 537 -MIPS_INS_SLDI = 538 -MIPS_INS_SLD = 539 -MIPS_INS_SLL = 540 -MIPS_INS_SLL16 = 541 -MIPS_INS_SLLI = 542 -MIPS_INS_SLLV = 543 -MIPS_INS_SLT = 544 -MIPS_INS_SLTI = 545 -MIPS_INS_SLTIU = 546 -MIPS_INS_SLTU = 547 -MIPS_INS_SNE = 548 -MIPS_INS_SNEI = 549 -MIPS_INS_SPLATI = 550 -MIPS_INS_SPLAT = 551 -MIPS_INS_SRA = 552 -MIPS_INS_SRAI = 553 -MIPS_INS_SRARI = 554 -MIPS_INS_SRAR = 555 -MIPS_INS_SRAV = 556 -MIPS_INS_SRL = 557 -MIPS_INS_SRL16 = 558 -MIPS_INS_SRLI = 559 -MIPS_INS_SRLRI = 560 -MIPS_INS_SRLR = 561 -MIPS_INS_SRLV = 562 -MIPS_INS_SSNOP = 563 -MIPS_INS_ST = 564 -MIPS_INS_SUBQH = 565 -MIPS_INS_SUBQH_R = 566 -MIPS_INS_SUBQ = 567 -MIPS_INS_SUBQ_S = 568 -MIPS_INS_SUBSUS_U = 569 -MIPS_INS_SUBSUU_S = 570 -MIPS_INS_SUBS_S = 571 -MIPS_INS_SUBS_U = 572 -MIPS_INS_SUBU16 = 573 -MIPS_INS_SUBUH = 574 -MIPS_INS_SUBUH_R = 575 -MIPS_INS_SUBU = 576 -MIPS_INS_SUBU_S = 577 -MIPS_INS_SUBVI = 578 -MIPS_INS_SUBV = 579 -MIPS_INS_SUXC1 = 580 -MIPS_INS_SW = 581 -MIPS_INS_SW16 = 582 -MIPS_INS_SWC1 = 583 -MIPS_INS_SWC2 = 584 -MIPS_INS_SWC3 = 585 -MIPS_INS_SWL = 586 -MIPS_INS_SWM16 = 587 -MIPS_INS_SWM32 = 588 -MIPS_INS_SWP = 589 -MIPS_INS_SWR = 590 -MIPS_INS_SWXC1 = 591 -MIPS_INS_SYNC = 592 -MIPS_INS_SYNCI = 593 -MIPS_INS_SYSCALL = 594 -MIPS_INS_TEQ = 595 -MIPS_INS_TEQI = 596 -MIPS_INS_TGE = 597 -MIPS_INS_TGEI = 598 -MIPS_INS_TGEIU = 599 -MIPS_INS_TGEU = 600 -MIPS_INS_TLBP = 601 -MIPS_INS_TLBR = 602 -MIPS_INS_TLBWI = 603 -MIPS_INS_TLBWR = 604 -MIPS_INS_TLT = 605 -MIPS_INS_TLTI = 606 -MIPS_INS_TLTIU = 607 -MIPS_INS_TLTU = 608 -MIPS_INS_TNE = 609 -MIPS_INS_TNEI = 610 -MIPS_INS_TRUNC = 611 -MIPS_INS_V3MULU = 612 -MIPS_INS_VMM0 = 613 -MIPS_INS_VMULU = 614 -MIPS_INS_VSHF = 615 -MIPS_INS_WAIT = 616 -MIPS_INS_WRDSP = 617 -MIPS_INS_WSBH = 618 -MIPS_INS_XOR = 619 -MIPS_INS_XOR16 = 620 -MIPS_INS_XORI = 621 - -# some alias instructions -MIPS_INS_NOP = 622 -MIPS_INS_NEGU = 623 - -# special instructions -MIPS_INS_JALR_HB = 624 -MIPS_INS_JR_HB = 625 -MIPS_INS_ENDING = 626 +MIPS_INS_ABS = 1 +MIPS_INS_ALIGN = 2 +MIPS_INS_BEQL = 3 +MIPS_INS_BGE = 4 +MIPS_INS_BGEL = 5 +MIPS_INS_BGEU = 6 +MIPS_INS_BGEUL = 7 +MIPS_INS_BGT = 8 +MIPS_INS_BGTL = 9 +MIPS_INS_BGTU = 10 +MIPS_INS_BGTUL = 11 +MIPS_INS_BLE = 12 +MIPS_INS_BLEL = 13 +MIPS_INS_BLEU = 14 +MIPS_INS_BLEUL = 15 +MIPS_INS_BLT = 16 +MIPS_INS_BLTL = 17 +MIPS_INS_BLTU = 18 +MIPS_INS_BLTUL = 19 +MIPS_INS_BNEL = 20 +MIPS_INS_B = 21 +MIPS_INS_BEQ = 22 +MIPS_INS_BNE = 23 +MIPS_INS_CFTC1 = 24 +MIPS_INS_CTTC1 = 25 +MIPS_INS_DMUL = 26 +MIPS_INS_DMULO = 27 +MIPS_INS_DMULOU = 28 +MIPS_INS_DROL = 29 +MIPS_INS_DROR = 30 +MIPS_INS_DDIV = 31 +MIPS_INS_DREM = 32 +MIPS_INS_DDIVU = 33 +MIPS_INS_DREMU = 34 +MIPS_INS_JAL = 35 +MIPS_INS_LD = 36 +MIPS_INS_LWM = 37 +MIPS_INS_LA = 38 +MIPS_INS_DLA = 39 +MIPS_INS_LI = 40 +MIPS_INS_DLI = 41 +MIPS_INS_LI_D = 42 +MIPS_INS_LI_S = 43 +MIPS_INS_MFTACX = 44 +MIPS_INS_MFTC0 = 45 +MIPS_INS_MFTC1 = 46 +MIPS_INS_MFTDSP = 47 +MIPS_INS_MFTGPR = 48 +MIPS_INS_MFTHC1 = 49 +MIPS_INS_MFTHI = 50 +MIPS_INS_MFTLO = 51 +MIPS_INS_MTTACX = 52 +MIPS_INS_MTTC0 = 53 +MIPS_INS_MTTC1 = 54 +MIPS_INS_MTTDSP = 55 +MIPS_INS_MTTGPR = 56 +MIPS_INS_MTTHC1 = 57 +MIPS_INS_MTTHI = 58 +MIPS_INS_MTTLO = 59 +MIPS_INS_MUL = 60 +MIPS_INS_MULO = 61 +MIPS_INS_MULOU = 62 +MIPS_INS_NOR = 63 +MIPS_INS_ADDIU = 64 +MIPS_INS_ANDI = 65 +MIPS_INS_SUBU = 66 +MIPS_INS_TRUNC_W_D = 67 +MIPS_INS_TRUNC_W_S = 68 +MIPS_INS_ROL = 69 +MIPS_INS_ROR = 70 +MIPS_INS_S_D = 71 +MIPS_INS_SD = 72 +MIPS_INS_DIV = 73 +MIPS_INS_SEQ = 74 +MIPS_INS_SGE = 75 +MIPS_INS_SGEU = 76 +MIPS_INS_SGT = 77 +MIPS_INS_SGTU = 78 +MIPS_INS_SLE = 79 +MIPS_INS_SLEU = 80 +MIPS_INS_SLT = 81 +MIPS_INS_SLTU = 82 +MIPS_INS_SNE = 83 +MIPS_INS_REM = 84 +MIPS_INS_SWM = 85 +MIPS_INS_SAA = 86 +MIPS_INS_SAAD = 87 +MIPS_INS_DIVU = 88 +MIPS_INS_REMU = 89 +MIPS_INS_ULH = 90 +MIPS_INS_ULHU = 91 +MIPS_INS_ULW = 92 +MIPS_INS_USH = 93 +MIPS_INS_USW = 94 +MIPS_INS_ABSQ_S_PH = 95 +MIPS_INS_ABSQ_S_QB = 96 +MIPS_INS_ABSQ_S_W = 97 +MIPS_INS_ADD = 98 +MIPS_INS_ADDIUPC = 99 +MIPS_INS_ADDIUR1SP = 100 +MIPS_INS_ADDIUR2 = 101 +MIPS_INS_ADDIUS5 = 102 +MIPS_INS_ADDIUSP = 103 +MIPS_INS_ADDQH_PH = 104 +MIPS_INS_ADDQH_R_PH = 105 +MIPS_INS_ADDQH_R_W = 106 +MIPS_INS_ADDQH_W = 107 +MIPS_INS_ADDQ_PH = 108 +MIPS_INS_ADDQ_S_PH = 109 +MIPS_INS_ADDQ_S_W = 110 +MIPS_INS_ADDR_PS = 111 +MIPS_INS_ADDSC = 112 +MIPS_INS_ADDS_A_B = 113 +MIPS_INS_ADDS_A_D = 114 +MIPS_INS_ADDS_A_H = 115 +MIPS_INS_ADDS_A_W = 116 +MIPS_INS_ADDS_S_B = 117 +MIPS_INS_ADDS_S_D = 118 +MIPS_INS_ADDS_S_H = 119 +MIPS_INS_ADDS_S_W = 120 +MIPS_INS_ADDS_U_B = 121 +MIPS_INS_ADDS_U_D = 122 +MIPS_INS_ADDS_U_H = 123 +MIPS_INS_ADDS_U_W = 124 +MIPS_INS_ADDU16 = 125 +MIPS_INS_ADDUH_QB = 126 +MIPS_INS_ADDUH_R_QB = 127 +MIPS_INS_ADDU = 128 +MIPS_INS_ADDU_PH = 129 +MIPS_INS_ADDU_QB = 130 +MIPS_INS_ADDU_S_PH = 131 +MIPS_INS_ADDU_S_QB = 132 +MIPS_INS_ADDVI_B = 133 +MIPS_INS_ADDVI_D = 134 +MIPS_INS_ADDVI_H = 135 +MIPS_INS_ADDVI_W = 136 +MIPS_INS_ADDV_B = 137 +MIPS_INS_ADDV_D = 138 +MIPS_INS_ADDV_H = 139 +MIPS_INS_ADDV_W = 140 +MIPS_INS_ADDWC = 141 +MIPS_INS_ADD_A_B = 142 +MIPS_INS_ADD_A_D = 143 +MIPS_INS_ADD_A_H = 144 +MIPS_INS_ADD_A_W = 145 +MIPS_INS_ADDI = 146 +MIPS_INS_ALUIPC = 147 +MIPS_INS_AND = 148 +MIPS_INS_AND16 = 149 +MIPS_INS_ANDI16 = 150 +MIPS_INS_ANDI_B = 151 +MIPS_INS_AND_V = 152 +MIPS_INS_APPEND = 153 +MIPS_INS_ASUB_S_B = 154 +MIPS_INS_ASUB_S_D = 155 +MIPS_INS_ASUB_S_H = 156 +MIPS_INS_ASUB_S_W = 157 +MIPS_INS_ASUB_U_B = 158 +MIPS_INS_ASUB_U_D = 159 +MIPS_INS_ASUB_U_H = 160 +MIPS_INS_ASUB_U_W = 161 +MIPS_INS_AUI = 162 +MIPS_INS_AUIPC = 163 +MIPS_INS_AVER_S_B = 164 +MIPS_INS_AVER_S_D = 165 +MIPS_INS_AVER_S_H = 166 +MIPS_INS_AVER_S_W = 167 +MIPS_INS_AVER_U_B = 168 +MIPS_INS_AVER_U_D = 169 +MIPS_INS_AVER_U_H = 170 +MIPS_INS_AVER_U_W = 171 +MIPS_INS_AVE_S_B = 172 +MIPS_INS_AVE_S_D = 173 +MIPS_INS_AVE_S_H = 174 +MIPS_INS_AVE_S_W = 175 +MIPS_INS_AVE_U_B = 176 +MIPS_INS_AVE_U_D = 177 +MIPS_INS_AVE_U_H = 178 +MIPS_INS_AVE_U_W = 179 +MIPS_INS_B16 = 180 +MIPS_INS_BADDU = 181 +MIPS_INS_BAL = 182 +MIPS_INS_BALC = 183 +MIPS_INS_BALIGN = 184 +MIPS_INS_BALRSC = 185 +MIPS_INS_BBEQZC = 186 +MIPS_INS_BBIT0 = 187 +MIPS_INS_BBIT032 = 188 +MIPS_INS_BBIT1 = 189 +MIPS_INS_BBIT132 = 190 +MIPS_INS_BBNEZC = 191 +MIPS_INS_BC = 192 +MIPS_INS_BC16 = 193 +MIPS_INS_BC1EQZ = 194 +MIPS_INS_BC1EQZC = 195 +MIPS_INS_BC1F = 196 +MIPS_INS_BC1FL = 197 +MIPS_INS_BC1NEZ = 198 +MIPS_INS_BC1NEZC = 199 +MIPS_INS_BC1T = 200 +MIPS_INS_BC1TL = 201 +MIPS_INS_BC2EQZ = 202 +MIPS_INS_BC2EQZC = 203 +MIPS_INS_BC2NEZ = 204 +MIPS_INS_BC2NEZC = 205 +MIPS_INS_BCLRI_B = 206 +MIPS_INS_BCLRI_D = 207 +MIPS_INS_BCLRI_H = 208 +MIPS_INS_BCLRI_W = 209 +MIPS_INS_BCLR_B = 210 +MIPS_INS_BCLR_D = 211 +MIPS_INS_BCLR_H = 212 +MIPS_INS_BCLR_W = 213 +MIPS_INS_BEQC = 214 +MIPS_INS_BEQIC = 215 +MIPS_INS_BEQZ16 = 216 +MIPS_INS_BEQZALC = 217 +MIPS_INS_BEQZC = 218 +MIPS_INS_BEQZC16 = 219 +MIPS_INS_BGEC = 220 +MIPS_INS_BGEIC = 221 +MIPS_INS_BGEIUC = 222 +MIPS_INS_BGEUC = 223 +MIPS_INS_BGEZ = 224 +MIPS_INS_BGEZAL = 225 +MIPS_INS_BGEZALC = 226 +MIPS_INS_BGEZALL = 227 +MIPS_INS_BGEZALS = 228 +MIPS_INS_BGEZC = 229 +MIPS_INS_BGEZL = 230 +MIPS_INS_BGTZ = 231 +MIPS_INS_BGTZALC = 232 +MIPS_INS_BGTZC = 233 +MIPS_INS_BGTZL = 234 +MIPS_INS_BINSLI_B = 235 +MIPS_INS_BINSLI_D = 236 +MIPS_INS_BINSLI_H = 237 +MIPS_INS_BINSLI_W = 238 +MIPS_INS_BINSL_B = 239 +MIPS_INS_BINSL_D = 240 +MIPS_INS_BINSL_H = 241 +MIPS_INS_BINSL_W = 242 +MIPS_INS_BINSRI_B = 243 +MIPS_INS_BINSRI_D = 244 +MIPS_INS_BINSRI_H = 245 +MIPS_INS_BINSRI_W = 246 +MIPS_INS_BINSR_B = 247 +MIPS_INS_BINSR_D = 248 +MIPS_INS_BINSR_H = 249 +MIPS_INS_BINSR_W = 250 +MIPS_INS_BITREV = 251 +MIPS_INS_BITREVW = 252 +MIPS_INS_BITSWAP = 253 +MIPS_INS_BLEZ = 254 +MIPS_INS_BLEZALC = 255 +MIPS_INS_BLEZC = 256 +MIPS_INS_BLEZL = 257 +MIPS_INS_BLTC = 258 +MIPS_INS_BLTIC = 259 +MIPS_INS_BLTIUC = 260 +MIPS_INS_BLTUC = 261 +MIPS_INS_BLTZ = 262 +MIPS_INS_BLTZAL = 263 +MIPS_INS_BLTZALC = 264 +MIPS_INS_BLTZALL = 265 +MIPS_INS_BLTZALS = 266 +MIPS_INS_BLTZC = 267 +MIPS_INS_BLTZL = 268 +MIPS_INS_BMNZI_B = 269 +MIPS_INS_BMNZ_V = 270 +MIPS_INS_BMZI_B = 271 +MIPS_INS_BMZ_V = 272 +MIPS_INS_BNEC = 273 +MIPS_INS_BNEGI_B = 274 +MIPS_INS_BNEGI_D = 275 +MIPS_INS_BNEGI_H = 276 +MIPS_INS_BNEGI_W = 277 +MIPS_INS_BNEG_B = 278 +MIPS_INS_BNEG_D = 279 +MIPS_INS_BNEG_H = 280 +MIPS_INS_BNEG_W = 281 +MIPS_INS_BNEIC = 282 +MIPS_INS_BNEZ16 = 283 +MIPS_INS_BNEZALC = 284 +MIPS_INS_BNEZC = 285 +MIPS_INS_BNEZC16 = 286 +MIPS_INS_BNVC = 287 +MIPS_INS_BNZ_B = 288 +MIPS_INS_BNZ_D = 289 +MIPS_INS_BNZ_H = 290 +MIPS_INS_BNZ_V = 291 +MIPS_INS_BNZ_W = 292 +MIPS_INS_BOVC = 293 +MIPS_INS_BPOSGE32 = 294 +MIPS_INS_BPOSGE32C = 295 +MIPS_INS_BREAK = 296 +MIPS_INS_BREAK16 = 297 +MIPS_INS_BRSC = 298 +MIPS_INS_BSELI_B = 299 +MIPS_INS_BSEL_V = 300 +MIPS_INS_BSETI_B = 301 +MIPS_INS_BSETI_D = 302 +MIPS_INS_BSETI_H = 303 +MIPS_INS_BSETI_W = 304 +MIPS_INS_BSET_B = 305 +MIPS_INS_BSET_D = 306 +MIPS_INS_BSET_H = 307 +MIPS_INS_BSET_W = 308 +MIPS_INS_BYTEREVW = 309 +MIPS_INS_BZ_B = 310 +MIPS_INS_BZ_D = 311 +MIPS_INS_BZ_H = 312 +MIPS_INS_BZ_V = 313 +MIPS_INS_BZ_W = 314 +MIPS_INS_BEQZ = 315 +MIPS_INS_BNEZ = 316 +MIPS_INS_BTEQZ = 317 +MIPS_INS_BTNEZ = 318 +MIPS_INS_CACHE = 319 +MIPS_INS_CACHEE = 320 +MIPS_INS_CEIL_L_D = 321 +MIPS_INS_CEIL_L_S = 322 +MIPS_INS_CEIL_W_D = 323 +MIPS_INS_CEIL_W_S = 324 +MIPS_INS_CEQI_B = 325 +MIPS_INS_CEQI_D = 326 +MIPS_INS_CEQI_H = 327 +MIPS_INS_CEQI_W = 328 +MIPS_INS_CEQ_B = 329 +MIPS_INS_CEQ_D = 330 +MIPS_INS_CEQ_H = 331 +MIPS_INS_CEQ_W = 332 +MIPS_INS_CFC1 = 333 +MIPS_INS_CFC2 = 334 +MIPS_INS_CFCMSA = 335 +MIPS_INS_CINS = 336 +MIPS_INS_CINS32 = 337 +MIPS_INS_CLASS_D = 338 +MIPS_INS_CLASS_S = 339 +MIPS_INS_CLEI_S_B = 340 +MIPS_INS_CLEI_S_D = 341 +MIPS_INS_CLEI_S_H = 342 +MIPS_INS_CLEI_S_W = 343 +MIPS_INS_CLEI_U_B = 344 +MIPS_INS_CLEI_U_D = 345 +MIPS_INS_CLEI_U_H = 346 +MIPS_INS_CLEI_U_W = 347 +MIPS_INS_CLE_S_B = 348 +MIPS_INS_CLE_S_D = 349 +MIPS_INS_CLE_S_H = 350 +MIPS_INS_CLE_S_W = 351 +MIPS_INS_CLE_U_B = 352 +MIPS_INS_CLE_U_D = 353 +MIPS_INS_CLE_U_H = 354 +MIPS_INS_CLE_U_W = 355 +MIPS_INS_CLO = 356 +MIPS_INS_CLTI_S_B = 357 +MIPS_INS_CLTI_S_D = 358 +MIPS_INS_CLTI_S_H = 359 +MIPS_INS_CLTI_S_W = 360 +MIPS_INS_CLTI_U_B = 361 +MIPS_INS_CLTI_U_D = 362 +MIPS_INS_CLTI_U_H = 363 +MIPS_INS_CLTI_U_W = 364 +MIPS_INS_CLT_S_B = 365 +MIPS_INS_CLT_S_D = 366 +MIPS_INS_CLT_S_H = 367 +MIPS_INS_CLT_S_W = 368 +MIPS_INS_CLT_U_B = 369 +MIPS_INS_CLT_U_D = 370 +MIPS_INS_CLT_U_H = 371 +MIPS_INS_CLT_U_W = 372 +MIPS_INS_CLZ = 373 +MIPS_INS_CMPGDU_EQ_QB = 374 +MIPS_INS_CMPGDU_LE_QB = 375 +MIPS_INS_CMPGDU_LT_QB = 376 +MIPS_INS_CMPGU_EQ_QB = 377 +MIPS_INS_CMPGU_LE_QB = 378 +MIPS_INS_CMPGU_LT_QB = 379 +MIPS_INS_CMPU_EQ_QB = 380 +MIPS_INS_CMPU_LE_QB = 381 +MIPS_INS_CMPU_LT_QB = 382 +MIPS_INS_CMP_AF_D = 383 +MIPS_INS_CMP_AF_S = 384 +MIPS_INS_CMP_EQ_D = 385 +MIPS_INS_CMP_EQ_PH = 386 +MIPS_INS_CMP_EQ_S = 387 +MIPS_INS_CMP_LE_D = 388 +MIPS_INS_CMP_LE_PH = 389 +MIPS_INS_CMP_LE_S = 390 +MIPS_INS_CMP_LT_D = 391 +MIPS_INS_CMP_LT_PH = 392 +MIPS_INS_CMP_LT_S = 393 +MIPS_INS_CMP_SAF_D = 394 +MIPS_INS_CMP_SAF_S = 395 +MIPS_INS_CMP_SEQ_D = 396 +MIPS_INS_CMP_SEQ_S = 397 +MIPS_INS_CMP_SLE_D = 398 +MIPS_INS_CMP_SLE_S = 399 +MIPS_INS_CMP_SLT_D = 400 +MIPS_INS_CMP_SLT_S = 401 +MIPS_INS_CMP_SUEQ_D = 402 +MIPS_INS_CMP_SUEQ_S = 403 +MIPS_INS_CMP_SULE_D = 404 +MIPS_INS_CMP_SULE_S = 405 +MIPS_INS_CMP_SULT_D = 406 +MIPS_INS_CMP_SULT_S = 407 +MIPS_INS_CMP_SUN_D = 408 +MIPS_INS_CMP_SUN_S = 409 +MIPS_INS_CMP_UEQ_D = 410 +MIPS_INS_CMP_UEQ_S = 411 +MIPS_INS_CMP_ULE_D = 412 +MIPS_INS_CMP_ULE_S = 413 +MIPS_INS_CMP_ULT_D = 414 +MIPS_INS_CMP_ULT_S = 415 +MIPS_INS_CMP_UN_D = 416 +MIPS_INS_CMP_UN_S = 417 +MIPS_INS_COPY_S_B = 418 +MIPS_INS_COPY_S_D = 419 +MIPS_INS_COPY_S_H = 420 +MIPS_INS_COPY_S_W = 421 +MIPS_INS_COPY_U_B = 422 +MIPS_INS_COPY_U_H = 423 +MIPS_INS_COPY_U_W = 424 +MIPS_INS_CRC32B = 425 +MIPS_INS_CRC32CB = 426 +MIPS_INS_CRC32CD = 427 +MIPS_INS_CRC32CH = 428 +MIPS_INS_CRC32CW = 429 +MIPS_INS_CRC32D = 430 +MIPS_INS_CRC32H = 431 +MIPS_INS_CRC32W = 432 +MIPS_INS_CTC1 = 433 +MIPS_INS_CTC2 = 434 +MIPS_INS_CTCMSA = 435 +MIPS_INS_CVT_D_S = 436 +MIPS_INS_CVT_D_W = 437 +MIPS_INS_CVT_D_L = 438 +MIPS_INS_CVT_L_D = 439 +MIPS_INS_CVT_L_S = 440 +MIPS_INS_CVT_PS_PW = 441 +MIPS_INS_CVT_PS_S = 442 +MIPS_INS_CVT_PW_PS = 443 +MIPS_INS_CVT_S_D = 444 +MIPS_INS_CVT_S_L = 445 +MIPS_INS_CVT_S_PL = 446 +MIPS_INS_CVT_S_PU = 447 +MIPS_INS_CVT_S_W = 448 +MIPS_INS_CVT_W_D = 449 +MIPS_INS_CVT_W_S = 450 +MIPS_INS_C_EQ_D = 451 +MIPS_INS_C_EQ_S = 452 +MIPS_INS_C_F_D = 453 +MIPS_INS_C_F_S = 454 +MIPS_INS_C_LE_D = 455 +MIPS_INS_C_LE_S = 456 +MIPS_INS_C_LT_D = 457 +MIPS_INS_C_LT_S = 458 +MIPS_INS_C_NGE_D = 459 +MIPS_INS_C_NGE_S = 460 +MIPS_INS_C_NGLE_D = 461 +MIPS_INS_C_NGLE_S = 462 +MIPS_INS_C_NGL_D = 463 +MIPS_INS_C_NGL_S = 464 +MIPS_INS_C_NGT_D = 465 +MIPS_INS_C_NGT_S = 466 +MIPS_INS_C_OLE_D = 467 +MIPS_INS_C_OLE_S = 468 +MIPS_INS_C_OLT_D = 469 +MIPS_INS_C_OLT_S = 470 +MIPS_INS_C_SEQ_D = 471 +MIPS_INS_C_SEQ_S = 472 +MIPS_INS_C_SF_D = 473 +MIPS_INS_C_SF_S = 474 +MIPS_INS_C_UEQ_D = 475 +MIPS_INS_C_UEQ_S = 476 +MIPS_INS_C_ULE_D = 477 +MIPS_INS_C_ULE_S = 478 +MIPS_INS_C_ULT_D = 479 +MIPS_INS_C_ULT_S = 480 +MIPS_INS_C_UN_D = 481 +MIPS_INS_C_UN_S = 482 +MIPS_INS_CMP = 483 +MIPS_INS_CMPI = 484 +MIPS_INS_DADD = 485 +MIPS_INS_DADDI = 486 +MIPS_INS_DADDIU = 487 +MIPS_INS_DADDU = 488 +MIPS_INS_DAHI = 489 +MIPS_INS_DALIGN = 490 +MIPS_INS_DATI = 491 +MIPS_INS_DAUI = 492 +MIPS_INS_DBITSWAP = 493 +MIPS_INS_DCLO = 494 +MIPS_INS_DCLZ = 495 +MIPS_INS_DERET = 496 +MIPS_INS_DEXT = 497 +MIPS_INS_DEXTM = 498 +MIPS_INS_DEXTU = 499 +MIPS_INS_DI = 500 +MIPS_INS_DINS = 501 +MIPS_INS_DINSM = 502 +MIPS_INS_DINSU = 503 +MIPS_INS_DIV_S_B = 504 +MIPS_INS_DIV_S_D = 505 +MIPS_INS_DIV_S_H = 506 +MIPS_INS_DIV_S_W = 507 +MIPS_INS_DIV_U_B = 508 +MIPS_INS_DIV_U_D = 509 +MIPS_INS_DIV_U_H = 510 +MIPS_INS_DIV_U_W = 511 +MIPS_INS_DLSA = 512 +MIPS_INS_DMFC0 = 513 +MIPS_INS_DMFC1 = 514 +MIPS_INS_DMFC2 = 515 +MIPS_INS_DMFGC0 = 516 +MIPS_INS_DMOD = 517 +MIPS_INS_DMODU = 518 +MIPS_INS_DMT = 519 +MIPS_INS_DMTC0 = 520 +MIPS_INS_DMTC1 = 521 +MIPS_INS_DMTC2 = 522 +MIPS_INS_DMTGC0 = 523 +MIPS_INS_DMUH = 524 +MIPS_INS_DMUHU = 525 +MIPS_INS_DMULT = 526 +MIPS_INS_DMULTU = 527 +MIPS_INS_DMULU = 528 +MIPS_INS_DOTP_S_D = 529 +MIPS_INS_DOTP_S_H = 530 +MIPS_INS_DOTP_S_W = 531 +MIPS_INS_DOTP_U_D = 532 +MIPS_INS_DOTP_U_H = 533 +MIPS_INS_DOTP_U_W = 534 +MIPS_INS_DPADD_S_D = 535 +MIPS_INS_DPADD_S_H = 536 +MIPS_INS_DPADD_S_W = 537 +MIPS_INS_DPADD_U_D = 538 +MIPS_INS_DPADD_U_H = 539 +MIPS_INS_DPADD_U_W = 540 +MIPS_INS_DPAQX_SA_W_PH = 541 +MIPS_INS_DPAQX_S_W_PH = 542 +MIPS_INS_DPAQ_SA_L_W = 543 +MIPS_INS_DPAQ_S_W_PH = 544 +MIPS_INS_DPAU_H_QBL = 545 +MIPS_INS_DPAU_H_QBR = 546 +MIPS_INS_DPAX_W_PH = 547 +MIPS_INS_DPA_W_PH = 548 +MIPS_INS_DPOP = 549 +MIPS_INS_DPSQX_SA_W_PH = 550 +MIPS_INS_DPSQX_S_W_PH = 551 +MIPS_INS_DPSQ_SA_L_W = 552 +MIPS_INS_DPSQ_S_W_PH = 553 +MIPS_INS_DPSUB_S_D = 554 +MIPS_INS_DPSUB_S_H = 555 +MIPS_INS_DPSUB_S_W = 556 +MIPS_INS_DPSUB_U_D = 557 +MIPS_INS_DPSUB_U_H = 558 +MIPS_INS_DPSUB_U_W = 559 +MIPS_INS_DPSU_H_QBL = 560 +MIPS_INS_DPSU_H_QBR = 561 +MIPS_INS_DPSX_W_PH = 562 +MIPS_INS_DPS_W_PH = 563 +MIPS_INS_DROTR = 564 +MIPS_INS_DROTR32 = 565 +MIPS_INS_DROTRV = 566 +MIPS_INS_DSBH = 567 +MIPS_INS_DSHD = 568 +MIPS_INS_DSLL = 569 +MIPS_INS_DSLL32 = 570 +MIPS_INS_DSLLV = 571 +MIPS_INS_DSRA = 572 +MIPS_INS_DSRA32 = 573 +MIPS_INS_DSRAV = 574 +MIPS_INS_DSRL = 575 +MIPS_INS_DSRL32 = 576 +MIPS_INS_DSRLV = 577 +MIPS_INS_DSUB = 578 +MIPS_INS_DSUBU = 579 +MIPS_INS_DVP = 580 +MIPS_INS_DVPE = 581 +MIPS_INS_EHB = 582 +MIPS_INS_EI = 583 +MIPS_INS_EMT = 584 +MIPS_INS_ERET = 585 +MIPS_INS_ERETNC = 586 +MIPS_INS_EVP = 587 +MIPS_INS_EVPE = 588 +MIPS_INS_EXT = 589 +MIPS_INS_EXTP = 590 +MIPS_INS_EXTPDP = 591 +MIPS_INS_EXTPDPV = 592 +MIPS_INS_EXTPV = 593 +MIPS_INS_EXTRV_RS_W = 594 +MIPS_INS_EXTRV_R_W = 595 +MIPS_INS_EXTRV_S_H = 596 +MIPS_INS_EXTRV_W = 597 +MIPS_INS_EXTR_RS_W = 598 +MIPS_INS_EXTR_R_W = 599 +MIPS_INS_EXTR_S_H = 600 +MIPS_INS_EXTR_W = 601 +MIPS_INS_EXTS = 602 +MIPS_INS_EXTS32 = 603 +MIPS_INS_EXTW = 604 +MIPS_INS_ABS_D = 605 +MIPS_INS_ABS_S = 606 +MIPS_INS_FADD_D = 607 +MIPS_INS_ADD_D = 608 +MIPS_INS_ADD_PS = 609 +MIPS_INS_ADD_S = 610 +MIPS_INS_FADD_W = 611 +MIPS_INS_FCAF_D = 612 +MIPS_INS_FCAF_W = 613 +MIPS_INS_FCEQ_D = 614 +MIPS_INS_FCEQ_W = 615 +MIPS_INS_FCLASS_D = 616 +MIPS_INS_FCLASS_W = 617 +MIPS_INS_FCLE_D = 618 +MIPS_INS_FCLE_W = 619 +MIPS_INS_FCLT_D = 620 +MIPS_INS_FCLT_W = 621 +MIPS_INS_FCNE_D = 622 +MIPS_INS_FCNE_W = 623 +MIPS_INS_FCOR_D = 624 +MIPS_INS_FCOR_W = 625 +MIPS_INS_FCUEQ_D = 626 +MIPS_INS_FCUEQ_W = 627 +MIPS_INS_FCULE_D = 628 +MIPS_INS_FCULE_W = 629 +MIPS_INS_FCULT_D = 630 +MIPS_INS_FCULT_W = 631 +MIPS_INS_FCUNE_D = 632 +MIPS_INS_FCUNE_W = 633 +MIPS_INS_FCUN_D = 634 +MIPS_INS_FCUN_W = 635 +MIPS_INS_FDIV_D = 636 +MIPS_INS_DIV_D = 637 +MIPS_INS_DIV_S = 638 +MIPS_INS_FDIV_W = 639 +MIPS_INS_FEXDO_H = 640 +MIPS_INS_FEXDO_W = 641 +MIPS_INS_FEXP2_D = 642 +MIPS_INS_FEXP2_W = 643 +MIPS_INS_FEXUPL_D = 644 +MIPS_INS_FEXUPL_W = 645 +MIPS_INS_FEXUPR_D = 646 +MIPS_INS_FEXUPR_W = 647 +MIPS_INS_FFINT_S_D = 648 +MIPS_INS_FFINT_S_W = 649 +MIPS_INS_FFINT_U_D = 650 +MIPS_INS_FFINT_U_W = 651 +MIPS_INS_FFQL_D = 652 +MIPS_INS_FFQL_W = 653 +MIPS_INS_FFQR_D = 654 +MIPS_INS_FFQR_W = 655 +MIPS_INS_FILL_B = 656 +MIPS_INS_FILL_D = 657 +MIPS_INS_FILL_H = 658 +MIPS_INS_FILL_W = 659 +MIPS_INS_FLOG2_D = 660 +MIPS_INS_FLOG2_W = 661 +MIPS_INS_FLOOR_L_D = 662 +MIPS_INS_FLOOR_L_S = 663 +MIPS_INS_FLOOR_W_D = 664 +MIPS_INS_FLOOR_W_S = 665 +MIPS_INS_FMADD_D = 666 +MIPS_INS_FMADD_W = 667 +MIPS_INS_FMAX_A_D = 668 +MIPS_INS_FMAX_A_W = 669 +MIPS_INS_FMAX_D = 670 +MIPS_INS_FMAX_W = 671 +MIPS_INS_FMIN_A_D = 672 +MIPS_INS_FMIN_A_W = 673 +MIPS_INS_FMIN_D = 674 +MIPS_INS_FMIN_W = 675 +MIPS_INS_MOV_D = 676 +MIPS_INS_MOV_S = 677 +MIPS_INS_FMSUB_D = 678 +MIPS_INS_FMSUB_W = 679 +MIPS_INS_FMUL_D = 680 +MIPS_INS_MUL_D = 681 +MIPS_INS_MUL_PS = 682 +MIPS_INS_MUL_S = 683 +MIPS_INS_FMUL_W = 684 +MIPS_INS_NEG_D = 685 +MIPS_INS_NEG_S = 686 +MIPS_INS_FORK = 687 +MIPS_INS_FRCP_D = 688 +MIPS_INS_FRCP_W = 689 +MIPS_INS_FRINT_D = 690 +MIPS_INS_FRINT_W = 691 +MIPS_INS_FRSQRT_D = 692 +MIPS_INS_FRSQRT_W = 693 +MIPS_INS_FSAF_D = 694 +MIPS_INS_FSAF_W = 695 +MIPS_INS_FSEQ_D = 696 +MIPS_INS_FSEQ_W = 697 +MIPS_INS_FSLE_D = 698 +MIPS_INS_FSLE_W = 699 +MIPS_INS_FSLT_D = 700 +MIPS_INS_FSLT_W = 701 +MIPS_INS_FSNE_D = 702 +MIPS_INS_FSNE_W = 703 +MIPS_INS_FSOR_D = 704 +MIPS_INS_FSOR_W = 705 +MIPS_INS_FSQRT_D = 706 +MIPS_INS_SQRT_D = 707 +MIPS_INS_SQRT_S = 708 +MIPS_INS_FSQRT_W = 709 +MIPS_INS_FSUB_D = 710 +MIPS_INS_SUB_D = 711 +MIPS_INS_SUB_PS = 712 +MIPS_INS_SUB_S = 713 +MIPS_INS_FSUB_W = 714 +MIPS_INS_FSUEQ_D = 715 +MIPS_INS_FSUEQ_W = 716 +MIPS_INS_FSULE_D = 717 +MIPS_INS_FSULE_W = 718 +MIPS_INS_FSULT_D = 719 +MIPS_INS_FSULT_W = 720 +MIPS_INS_FSUNE_D = 721 +MIPS_INS_FSUNE_W = 722 +MIPS_INS_FSUN_D = 723 +MIPS_INS_FSUN_W = 724 +MIPS_INS_FTINT_S_D = 725 +MIPS_INS_FTINT_S_W = 726 +MIPS_INS_FTINT_U_D = 727 +MIPS_INS_FTINT_U_W = 728 +MIPS_INS_FTQ_H = 729 +MIPS_INS_FTQ_W = 730 +MIPS_INS_FTRUNC_S_D = 731 +MIPS_INS_FTRUNC_S_W = 732 +MIPS_INS_FTRUNC_U_D = 733 +MIPS_INS_FTRUNC_U_W = 734 +MIPS_INS_GINVI = 735 +MIPS_INS_GINVT = 736 +MIPS_INS_HADD_S_D = 737 +MIPS_INS_HADD_S_H = 738 +MIPS_INS_HADD_S_W = 739 +MIPS_INS_HADD_U_D = 740 +MIPS_INS_HADD_U_H = 741 +MIPS_INS_HADD_U_W = 742 +MIPS_INS_HSUB_S_D = 743 +MIPS_INS_HSUB_S_H = 744 +MIPS_INS_HSUB_S_W = 745 +MIPS_INS_HSUB_U_D = 746 +MIPS_INS_HSUB_U_H = 747 +MIPS_INS_HSUB_U_W = 748 +MIPS_INS_HYPCALL = 749 +MIPS_INS_ILVEV_B = 750 +MIPS_INS_ILVEV_D = 751 +MIPS_INS_ILVEV_H = 752 +MIPS_INS_ILVEV_W = 753 +MIPS_INS_ILVL_B = 754 +MIPS_INS_ILVL_D = 755 +MIPS_INS_ILVL_H = 756 +MIPS_INS_ILVL_W = 757 +MIPS_INS_ILVOD_B = 758 +MIPS_INS_ILVOD_D = 759 +MIPS_INS_ILVOD_H = 760 +MIPS_INS_ILVOD_W = 761 +MIPS_INS_ILVR_B = 762 +MIPS_INS_ILVR_D = 763 +MIPS_INS_ILVR_H = 764 +MIPS_INS_ILVR_W = 765 +MIPS_INS_INS = 766 +MIPS_INS_INSERT_B = 767 +MIPS_INS_INSERT_D = 768 +MIPS_INS_INSERT_H = 769 +MIPS_INS_INSERT_W = 770 +MIPS_INS_INSV = 771 +MIPS_INS_INSVE_B = 772 +MIPS_INS_INSVE_D = 773 +MIPS_INS_INSVE_H = 774 +MIPS_INS_INSVE_W = 775 +MIPS_INS_J = 776 +MIPS_INS_JALR = 777 +MIPS_INS_JALRC = 778 +MIPS_INS_JALRC_HB = 779 +MIPS_INS_JALRS16 = 780 +MIPS_INS_JALRS = 781 +MIPS_INS_JALR_HB = 782 +MIPS_INS_JALS = 783 +MIPS_INS_JALX = 784 +MIPS_INS_JIALC = 785 +MIPS_INS_JIC = 786 +MIPS_INS_JR = 787 +MIPS_INS_JR16 = 788 +MIPS_INS_JRADDIUSP = 789 +MIPS_INS_JRC = 790 +MIPS_INS_JRC16 = 791 +MIPS_INS_JRCADDIUSP = 792 +MIPS_INS_JR_HB = 793 +MIPS_INS_LAPC_H = 794 +MIPS_INS_LAPC_B = 795 +MIPS_INS_LB = 796 +MIPS_INS_LBE = 797 +MIPS_INS_LBU16 = 798 +MIPS_INS_LBU = 799 +MIPS_INS_LBUX = 800 +MIPS_INS_LBX = 801 +MIPS_INS_LBUE = 802 +MIPS_INS_LDC1 = 803 +MIPS_INS_LDC2 = 804 +MIPS_INS_LDC3 = 805 +MIPS_INS_LDI_B = 806 +MIPS_INS_LDI_D = 807 +MIPS_INS_LDI_H = 808 +MIPS_INS_LDI_W = 809 +MIPS_INS_LDL = 810 +MIPS_INS_LDPC = 811 +MIPS_INS_LDR = 812 +MIPS_INS_LDXC1 = 813 +MIPS_INS_LD_B = 814 +MIPS_INS_LD_D = 815 +MIPS_INS_LD_H = 816 +MIPS_INS_LD_W = 817 +MIPS_INS_LH = 818 +MIPS_INS_LHE = 819 +MIPS_INS_LHU16 = 820 +MIPS_INS_LHU = 821 +MIPS_INS_LHUXS = 822 +MIPS_INS_LHUX = 823 +MIPS_INS_LHX = 824 +MIPS_INS_LHXS = 825 +MIPS_INS_LHUE = 826 +MIPS_INS_LI16 = 827 +MIPS_INS_LL = 828 +MIPS_INS_LLD = 829 +MIPS_INS_LLE = 830 +MIPS_INS_LLWP = 831 +MIPS_INS_LSA = 832 +MIPS_INS_LUI = 833 +MIPS_INS_LUXC1 = 834 +MIPS_INS_LW = 835 +MIPS_INS_LW16 = 836 +MIPS_INS_LWC1 = 837 +MIPS_INS_LWC2 = 838 +MIPS_INS_LWC3 = 839 +MIPS_INS_LWE = 840 +MIPS_INS_LWL = 841 +MIPS_INS_LWLE = 842 +MIPS_INS_LWM16 = 843 +MIPS_INS_LWM32 = 844 +MIPS_INS_LWPC = 845 +MIPS_INS_LWP = 846 +MIPS_INS_LWR = 847 +MIPS_INS_LWRE = 848 +MIPS_INS_LWUPC = 849 +MIPS_INS_LWU = 850 +MIPS_INS_LWX = 851 +MIPS_INS_LWXC1 = 852 +MIPS_INS_LWXS = 853 +MIPS_INS_MADD = 854 +MIPS_INS_MADDF_D = 855 +MIPS_INS_MADDF_S = 856 +MIPS_INS_MADDR_Q_H = 857 +MIPS_INS_MADDR_Q_W = 858 +MIPS_INS_MADDU = 859 +MIPS_INS_MADDV_B = 860 +MIPS_INS_MADDV_D = 861 +MIPS_INS_MADDV_H = 862 +MIPS_INS_MADDV_W = 863 +MIPS_INS_MADD_D = 864 +MIPS_INS_MADD_Q_H = 865 +MIPS_INS_MADD_Q_W = 866 +MIPS_INS_MADD_S = 867 +MIPS_INS_MAQ_SA_W_PHL = 868 +MIPS_INS_MAQ_SA_W_PHR = 869 +MIPS_INS_MAQ_S_W_PHL = 870 +MIPS_INS_MAQ_S_W_PHR = 871 +MIPS_INS_MAXA_D = 872 +MIPS_INS_MAXA_S = 873 +MIPS_INS_MAXI_S_B = 874 +MIPS_INS_MAXI_S_D = 875 +MIPS_INS_MAXI_S_H = 876 +MIPS_INS_MAXI_S_W = 877 +MIPS_INS_MAXI_U_B = 878 +MIPS_INS_MAXI_U_D = 879 +MIPS_INS_MAXI_U_H = 880 +MIPS_INS_MAXI_U_W = 881 +MIPS_INS_MAX_A_B = 882 +MIPS_INS_MAX_A_D = 883 +MIPS_INS_MAX_A_H = 884 +MIPS_INS_MAX_A_W = 885 +MIPS_INS_MAX_D = 886 +MIPS_INS_MAX_S = 887 +MIPS_INS_MAX_S_B = 888 +MIPS_INS_MAX_S_D = 889 +MIPS_INS_MAX_S_H = 890 +MIPS_INS_MAX_S_W = 891 +MIPS_INS_MAX_U_B = 892 +MIPS_INS_MAX_U_D = 893 +MIPS_INS_MAX_U_H = 894 +MIPS_INS_MAX_U_W = 895 +MIPS_INS_MFC0 = 896 +MIPS_INS_MFC1 = 897 +MIPS_INS_MFC2 = 898 +MIPS_INS_MFGC0 = 899 +MIPS_INS_MFHC0 = 900 +MIPS_INS_MFHC1 = 901 +MIPS_INS_MFHC2 = 902 +MIPS_INS_MFHGC0 = 903 +MIPS_INS_MFHI = 904 +MIPS_INS_MFHI16 = 905 +MIPS_INS_MFLO = 906 +MIPS_INS_MFLO16 = 907 +MIPS_INS_MFTR = 908 +MIPS_INS_MINA_D = 909 +MIPS_INS_MINA_S = 910 +MIPS_INS_MINI_S_B = 911 +MIPS_INS_MINI_S_D = 912 +MIPS_INS_MINI_S_H = 913 +MIPS_INS_MINI_S_W = 914 +MIPS_INS_MINI_U_B = 915 +MIPS_INS_MINI_U_D = 916 +MIPS_INS_MINI_U_H = 917 +MIPS_INS_MINI_U_W = 918 +MIPS_INS_MIN_A_B = 919 +MIPS_INS_MIN_A_D = 920 +MIPS_INS_MIN_A_H = 921 +MIPS_INS_MIN_A_W = 922 +MIPS_INS_MIN_D = 923 +MIPS_INS_MIN_S = 924 +MIPS_INS_MIN_S_B = 925 +MIPS_INS_MIN_S_D = 926 +MIPS_INS_MIN_S_H = 927 +MIPS_INS_MIN_S_W = 928 +MIPS_INS_MIN_U_B = 929 +MIPS_INS_MIN_U_D = 930 +MIPS_INS_MIN_U_H = 931 +MIPS_INS_MIN_U_W = 932 +MIPS_INS_MOD = 933 +MIPS_INS_MODSUB = 934 +MIPS_INS_MODU = 935 +MIPS_INS_MOD_S_B = 936 +MIPS_INS_MOD_S_D = 937 +MIPS_INS_MOD_S_H = 938 +MIPS_INS_MOD_S_W = 939 +MIPS_INS_MOD_U_B = 940 +MIPS_INS_MOD_U_D = 941 +MIPS_INS_MOD_U_H = 942 +MIPS_INS_MOD_U_W = 943 +MIPS_INS_MOVE = 944 +MIPS_INS_MOVE16 = 945 +MIPS_INS_MOVE_BALC = 946 +MIPS_INS_MOVEP = 947 +MIPS_INS_MOVE_V = 948 +MIPS_INS_MOVF_D = 949 +MIPS_INS_MOVF = 950 +MIPS_INS_MOVF_S = 951 +MIPS_INS_MOVN_D = 952 +MIPS_INS_MOVN = 953 +MIPS_INS_MOVN_S = 954 +MIPS_INS_MOVT_D = 955 +MIPS_INS_MOVT = 956 +MIPS_INS_MOVT_S = 957 +MIPS_INS_MOVZ_D = 958 +MIPS_INS_MOVZ = 959 +MIPS_INS_MOVZ_S = 960 +MIPS_INS_MSUB = 961 +MIPS_INS_MSUBF_D = 962 +MIPS_INS_MSUBF_S = 963 +MIPS_INS_MSUBR_Q_H = 964 +MIPS_INS_MSUBR_Q_W = 965 +MIPS_INS_MSUBU = 966 +MIPS_INS_MSUBV_B = 967 +MIPS_INS_MSUBV_D = 968 +MIPS_INS_MSUBV_H = 969 +MIPS_INS_MSUBV_W = 970 +MIPS_INS_MSUB_D = 971 +MIPS_INS_MSUB_Q_H = 972 +MIPS_INS_MSUB_Q_W = 973 +MIPS_INS_MSUB_S = 974 +MIPS_INS_MTC0 = 975 +MIPS_INS_MTC1 = 976 +MIPS_INS_MTC2 = 977 +MIPS_INS_MTGC0 = 978 +MIPS_INS_MTHC0 = 979 +MIPS_INS_MTHC1 = 980 +MIPS_INS_MTHC2 = 981 +MIPS_INS_MTHGC0 = 982 +MIPS_INS_MTHI = 983 +MIPS_INS_MTHLIP = 984 +MIPS_INS_MTLO = 985 +MIPS_INS_MTM0 = 986 +MIPS_INS_MTM1 = 987 +MIPS_INS_MTM2 = 988 +MIPS_INS_MTP0 = 989 +MIPS_INS_MTP1 = 990 +MIPS_INS_MTP2 = 991 +MIPS_INS_MTTR = 992 +MIPS_INS_MUH = 993 +MIPS_INS_MUHU = 994 +MIPS_INS_MULEQ_S_W_PHL = 995 +MIPS_INS_MULEQ_S_W_PHR = 996 +MIPS_INS_MULEU_S_PH_QBL = 997 +MIPS_INS_MULEU_S_PH_QBR = 998 +MIPS_INS_MULQ_RS_PH = 999 +MIPS_INS_MULQ_RS_W = 1000 +MIPS_INS_MULQ_S_PH = 1001 +MIPS_INS_MULQ_S_W = 1002 +MIPS_INS_MULR_PS = 1003 +MIPS_INS_MULR_Q_H = 1004 +MIPS_INS_MULR_Q_W = 1005 +MIPS_INS_MULSAQ_S_W_PH = 1006 +MIPS_INS_MULSA_W_PH = 1007 +MIPS_INS_MULT = 1008 +MIPS_INS_MULTU = 1009 +MIPS_INS_MULU = 1010 +MIPS_INS_MULV_B = 1011 +MIPS_INS_MULV_D = 1012 +MIPS_INS_MULV_H = 1013 +MIPS_INS_MULV_W = 1014 +MIPS_INS_MUL_PH = 1015 +MIPS_INS_MUL_Q_H = 1016 +MIPS_INS_MUL_Q_W = 1017 +MIPS_INS_MUL_S_PH = 1018 +MIPS_INS_NLOC_B = 1019 +MIPS_INS_NLOC_D = 1020 +MIPS_INS_NLOC_H = 1021 +MIPS_INS_NLOC_W = 1022 +MIPS_INS_NLZC_B = 1023 +MIPS_INS_NLZC_D = 1024 +MIPS_INS_NLZC_H = 1025 +MIPS_INS_NLZC_W = 1026 +MIPS_INS_NMADD_D = 1027 +MIPS_INS_NMADD_S = 1028 +MIPS_INS_NMSUB_D = 1029 +MIPS_INS_NMSUB_S = 1030 +MIPS_INS_NOP32 = 1031 +MIPS_INS_NOP = 1032 +MIPS_INS_NORI_B = 1033 +MIPS_INS_NOR_V = 1034 +MIPS_INS_NOT16 = 1035 +MIPS_INS_NOT = 1036 +MIPS_INS_NEG = 1037 +MIPS_INS_OR = 1038 +MIPS_INS_OR16 = 1039 +MIPS_INS_ORI_B = 1040 +MIPS_INS_ORI = 1041 +MIPS_INS_OR_V = 1042 +MIPS_INS_PACKRL_PH = 1043 +MIPS_INS_PAUSE = 1044 +MIPS_INS_PCKEV_B = 1045 +MIPS_INS_PCKEV_D = 1046 +MIPS_INS_PCKEV_H = 1047 +MIPS_INS_PCKEV_W = 1048 +MIPS_INS_PCKOD_B = 1049 +MIPS_INS_PCKOD_D = 1050 +MIPS_INS_PCKOD_H = 1051 +MIPS_INS_PCKOD_W = 1052 +MIPS_INS_PCNT_B = 1053 +MIPS_INS_PCNT_D = 1054 +MIPS_INS_PCNT_H = 1055 +MIPS_INS_PCNT_W = 1056 +MIPS_INS_PICK_PH = 1057 +MIPS_INS_PICK_QB = 1058 +MIPS_INS_PLL_PS = 1059 +MIPS_INS_PLU_PS = 1060 +MIPS_INS_POP = 1061 +MIPS_INS_PRECEQU_PH_QBL = 1062 +MIPS_INS_PRECEQU_PH_QBLA = 1063 +MIPS_INS_PRECEQU_PH_QBR = 1064 +MIPS_INS_PRECEQU_PH_QBRA = 1065 +MIPS_INS_PRECEQ_W_PHL = 1066 +MIPS_INS_PRECEQ_W_PHR = 1067 +MIPS_INS_PRECEU_PH_QBL = 1068 +MIPS_INS_PRECEU_PH_QBLA = 1069 +MIPS_INS_PRECEU_PH_QBR = 1070 +MIPS_INS_PRECEU_PH_QBRA = 1071 +MIPS_INS_PRECRQU_S_QB_PH = 1072 +MIPS_INS_PRECRQ_PH_W = 1073 +MIPS_INS_PRECRQ_QB_PH = 1074 +MIPS_INS_PRECRQ_RS_PH_W = 1075 +MIPS_INS_PRECR_QB_PH = 1076 +MIPS_INS_PRECR_SRA_PH_W = 1077 +MIPS_INS_PRECR_SRA_R_PH_W = 1078 +MIPS_INS_PREF = 1079 +MIPS_INS_PREFE = 1080 +MIPS_INS_PREFX = 1081 +MIPS_INS_PREPEND = 1082 +MIPS_INS_PUL_PS = 1083 +MIPS_INS_PUU_PS = 1084 +MIPS_INS_RADDU_W_QB = 1085 +MIPS_INS_RDDSP = 1086 +MIPS_INS_RDHWR = 1087 +MIPS_INS_RDPGPR = 1088 +MIPS_INS_RECIP_D = 1089 +MIPS_INS_RECIP_S = 1090 +MIPS_INS_REPLV_PH = 1091 +MIPS_INS_REPLV_QB = 1092 +MIPS_INS_REPL_PH = 1093 +MIPS_INS_REPL_QB = 1094 +MIPS_INS_RESTORE_JRC = 1095 +MIPS_INS_RESTORE = 1096 +MIPS_INS_RINT_D = 1097 +MIPS_INS_RINT_S = 1098 +MIPS_INS_ROTR = 1099 +MIPS_INS_ROTRV = 1100 +MIPS_INS_ROTX = 1101 +MIPS_INS_ROUND_L_D = 1102 +MIPS_INS_ROUND_L_S = 1103 +MIPS_INS_ROUND_W_D = 1104 +MIPS_INS_ROUND_W_S = 1105 +MIPS_INS_RSQRT_D = 1106 +MIPS_INS_RSQRT_S = 1107 +MIPS_INS_SAT_S_B = 1108 +MIPS_INS_SAT_S_D = 1109 +MIPS_INS_SAT_S_H = 1110 +MIPS_INS_SAT_S_W = 1111 +MIPS_INS_SAT_U_B = 1112 +MIPS_INS_SAT_U_D = 1113 +MIPS_INS_SAT_U_H = 1114 +MIPS_INS_SAT_U_W = 1115 +MIPS_INS_SAVE = 1116 +MIPS_INS_SB = 1117 +MIPS_INS_SB16 = 1118 +MIPS_INS_SBE = 1119 +MIPS_INS_SBX = 1120 +MIPS_INS_SC = 1121 +MIPS_INS_SCD = 1122 +MIPS_INS_SCE = 1123 +MIPS_INS_SCWP = 1124 +MIPS_INS_SDBBP = 1125 +MIPS_INS_SDBBP16 = 1126 +MIPS_INS_SDC1 = 1127 +MIPS_INS_SDC2 = 1128 +MIPS_INS_SDC3 = 1129 +MIPS_INS_SDL = 1130 +MIPS_INS_SDR = 1131 +MIPS_INS_SDXC1 = 1132 +MIPS_INS_SEB = 1133 +MIPS_INS_SEH = 1134 +MIPS_INS_SELEQZ = 1135 +MIPS_INS_SELEQZ_D = 1136 +MIPS_INS_SELEQZ_S = 1137 +MIPS_INS_SELNEZ = 1138 +MIPS_INS_SELNEZ_D = 1139 +MIPS_INS_SELNEZ_S = 1140 +MIPS_INS_SEL_D = 1141 +MIPS_INS_SEL_S = 1142 +MIPS_INS_SEQI = 1143 +MIPS_INS_SH = 1144 +MIPS_INS_SH16 = 1145 +MIPS_INS_SHE = 1146 +MIPS_INS_SHF_B = 1147 +MIPS_INS_SHF_H = 1148 +MIPS_INS_SHF_W = 1149 +MIPS_INS_SHILO = 1150 +MIPS_INS_SHILOV = 1151 +MIPS_INS_SHLLV_PH = 1152 +MIPS_INS_SHLLV_QB = 1153 +MIPS_INS_SHLLV_S_PH = 1154 +MIPS_INS_SHLLV_S_W = 1155 +MIPS_INS_SHLL_PH = 1156 +MIPS_INS_SHLL_QB = 1157 +MIPS_INS_SHLL_S_PH = 1158 +MIPS_INS_SHLL_S_W = 1159 +MIPS_INS_SHRAV_PH = 1160 +MIPS_INS_SHRAV_QB = 1161 +MIPS_INS_SHRAV_R_PH = 1162 +MIPS_INS_SHRAV_R_QB = 1163 +MIPS_INS_SHRAV_R_W = 1164 +MIPS_INS_SHRA_PH = 1165 +MIPS_INS_SHRA_QB = 1166 +MIPS_INS_SHRA_R_PH = 1167 +MIPS_INS_SHRA_R_QB = 1168 +MIPS_INS_SHRA_R_W = 1169 +MIPS_INS_SHRLV_PH = 1170 +MIPS_INS_SHRLV_QB = 1171 +MIPS_INS_SHRL_PH = 1172 +MIPS_INS_SHRL_QB = 1173 +MIPS_INS_SHXS = 1174 +MIPS_INS_SHX = 1175 +MIPS_INS_SIGRIE = 1176 +MIPS_INS_SLDI_B = 1177 +MIPS_INS_SLDI_D = 1178 +MIPS_INS_SLDI_H = 1179 +MIPS_INS_SLDI_W = 1180 +MIPS_INS_SLD_B = 1181 +MIPS_INS_SLD_D = 1182 +MIPS_INS_SLD_H = 1183 +MIPS_INS_SLD_W = 1184 +MIPS_INS_SLL = 1185 +MIPS_INS_SLL16 = 1186 +MIPS_INS_SLLI_B = 1187 +MIPS_INS_SLLI_D = 1188 +MIPS_INS_SLLI_H = 1189 +MIPS_INS_SLLI_W = 1190 +MIPS_INS_SLLV = 1191 +MIPS_INS_SLL_B = 1192 +MIPS_INS_SLL_D = 1193 +MIPS_INS_SLL_H = 1194 +MIPS_INS_SLL_W = 1195 +MIPS_INS_SLTIU = 1196 +MIPS_INS_SLTI = 1197 +MIPS_INS_SNEI = 1198 +MIPS_INS_SOV = 1199 +MIPS_INS_SPLATI_B = 1200 +MIPS_INS_SPLATI_D = 1201 +MIPS_INS_SPLATI_H = 1202 +MIPS_INS_SPLATI_W = 1203 +MIPS_INS_SPLAT_B = 1204 +MIPS_INS_SPLAT_D = 1205 +MIPS_INS_SPLAT_H = 1206 +MIPS_INS_SPLAT_W = 1207 +MIPS_INS_SRA = 1208 +MIPS_INS_SRAI_B = 1209 +MIPS_INS_SRAI_D = 1210 +MIPS_INS_SRAI_H = 1211 +MIPS_INS_SRAI_W = 1212 +MIPS_INS_SRARI_B = 1213 +MIPS_INS_SRARI_D = 1214 +MIPS_INS_SRARI_H = 1215 +MIPS_INS_SRARI_W = 1216 +MIPS_INS_SRAR_B = 1217 +MIPS_INS_SRAR_D = 1218 +MIPS_INS_SRAR_H = 1219 +MIPS_INS_SRAR_W = 1220 +MIPS_INS_SRAV = 1221 +MIPS_INS_SRA_B = 1222 +MIPS_INS_SRA_D = 1223 +MIPS_INS_SRA_H = 1224 +MIPS_INS_SRA_W = 1225 +MIPS_INS_SRL = 1226 +MIPS_INS_SRL16 = 1227 +MIPS_INS_SRLI_B = 1228 +MIPS_INS_SRLI_D = 1229 +MIPS_INS_SRLI_H = 1230 +MIPS_INS_SRLI_W = 1231 +MIPS_INS_SRLRI_B = 1232 +MIPS_INS_SRLRI_D = 1233 +MIPS_INS_SRLRI_H = 1234 +MIPS_INS_SRLRI_W = 1235 +MIPS_INS_SRLR_B = 1236 +MIPS_INS_SRLR_D = 1237 +MIPS_INS_SRLR_H = 1238 +MIPS_INS_SRLR_W = 1239 +MIPS_INS_SRLV = 1240 +MIPS_INS_SRL_B = 1241 +MIPS_INS_SRL_D = 1242 +MIPS_INS_SRL_H = 1243 +MIPS_INS_SRL_W = 1244 +MIPS_INS_SSNOP = 1245 +MIPS_INS_ST_B = 1246 +MIPS_INS_ST_D = 1247 +MIPS_INS_ST_H = 1248 +MIPS_INS_ST_W = 1249 +MIPS_INS_SUB = 1250 +MIPS_INS_SUBQH_PH = 1251 +MIPS_INS_SUBQH_R_PH = 1252 +MIPS_INS_SUBQH_R_W = 1253 +MIPS_INS_SUBQH_W = 1254 +MIPS_INS_SUBQ_PH = 1255 +MIPS_INS_SUBQ_S_PH = 1256 +MIPS_INS_SUBQ_S_W = 1257 +MIPS_INS_SUBSUS_U_B = 1258 +MIPS_INS_SUBSUS_U_D = 1259 +MIPS_INS_SUBSUS_U_H = 1260 +MIPS_INS_SUBSUS_U_W = 1261 +MIPS_INS_SUBSUU_S_B = 1262 +MIPS_INS_SUBSUU_S_D = 1263 +MIPS_INS_SUBSUU_S_H = 1264 +MIPS_INS_SUBSUU_S_W = 1265 +MIPS_INS_SUBS_S_B = 1266 +MIPS_INS_SUBS_S_D = 1267 +MIPS_INS_SUBS_S_H = 1268 +MIPS_INS_SUBS_S_W = 1269 +MIPS_INS_SUBS_U_B = 1270 +MIPS_INS_SUBS_U_D = 1271 +MIPS_INS_SUBS_U_H = 1272 +MIPS_INS_SUBS_U_W = 1273 +MIPS_INS_SUBU16 = 1274 +MIPS_INS_SUBUH_QB = 1275 +MIPS_INS_SUBUH_R_QB = 1276 +MIPS_INS_SUBU_PH = 1277 +MIPS_INS_SUBU_QB = 1278 +MIPS_INS_SUBU_S_PH = 1279 +MIPS_INS_SUBU_S_QB = 1280 +MIPS_INS_SUBVI_B = 1281 +MIPS_INS_SUBVI_D = 1282 +MIPS_INS_SUBVI_H = 1283 +MIPS_INS_SUBVI_W = 1284 +MIPS_INS_SUBV_B = 1285 +MIPS_INS_SUBV_D = 1286 +MIPS_INS_SUBV_H = 1287 +MIPS_INS_SUBV_W = 1288 +MIPS_INS_SUXC1 = 1289 +MIPS_INS_SW = 1290 +MIPS_INS_SW16 = 1291 +MIPS_INS_SWC1 = 1292 +MIPS_INS_SWC2 = 1293 +MIPS_INS_SWC3 = 1294 +MIPS_INS_SWE = 1295 +MIPS_INS_SWL = 1296 +MIPS_INS_SWLE = 1297 +MIPS_INS_SWM16 = 1298 +MIPS_INS_SWM32 = 1299 +MIPS_INS_SWPC = 1300 +MIPS_INS_SWP = 1301 +MIPS_INS_SWR = 1302 +MIPS_INS_SWRE = 1303 +MIPS_INS_SWSP = 1304 +MIPS_INS_SWXC1 = 1305 +MIPS_INS_SWXS = 1306 +MIPS_INS_SWX = 1307 +MIPS_INS_SYNC = 1308 +MIPS_INS_SYNCI = 1309 +MIPS_INS_SYSCALL = 1310 +MIPS_INS_TEQ = 1311 +MIPS_INS_TEQI = 1312 +MIPS_INS_TGE = 1313 +MIPS_INS_TGEI = 1314 +MIPS_INS_TGEIU = 1315 +MIPS_INS_TGEU = 1316 +MIPS_INS_TLBGINV = 1317 +MIPS_INS_TLBGINVF = 1318 +MIPS_INS_TLBGP = 1319 +MIPS_INS_TLBGR = 1320 +MIPS_INS_TLBGWI = 1321 +MIPS_INS_TLBGWR = 1322 +MIPS_INS_TLBINV = 1323 +MIPS_INS_TLBINVF = 1324 +MIPS_INS_TLBP = 1325 +MIPS_INS_TLBR = 1326 +MIPS_INS_TLBWI = 1327 +MIPS_INS_TLBWR = 1328 +MIPS_INS_TLT = 1329 +MIPS_INS_TLTI = 1330 +MIPS_INS_TLTIU = 1331 +MIPS_INS_TLTU = 1332 +MIPS_INS_TNE = 1333 +MIPS_INS_TNEI = 1334 +MIPS_INS_TRUNC_L_D = 1335 +MIPS_INS_TRUNC_L_S = 1336 +MIPS_INS_UALH = 1337 +MIPS_INS_UALWM = 1338 +MIPS_INS_UALW = 1339 +MIPS_INS_UASH = 1340 +MIPS_INS_UASWM = 1341 +MIPS_INS_UASW = 1342 +MIPS_INS_V3MULU = 1343 +MIPS_INS_VMM0 = 1344 +MIPS_INS_VMULU = 1345 +MIPS_INS_VSHF_B = 1346 +MIPS_INS_VSHF_D = 1347 +MIPS_INS_VSHF_H = 1348 +MIPS_INS_VSHF_W = 1349 +MIPS_INS_WAIT = 1350 +MIPS_INS_WRDSP = 1351 +MIPS_INS_WRPGPR = 1352 +MIPS_INS_WSBH = 1353 +MIPS_INS_XOR = 1354 +MIPS_INS_XOR16 = 1355 +MIPS_INS_XORI_B = 1356 +MIPS_INS_XORI = 1357 +MIPS_INS_XOR_V = 1358 +MIPS_INS_YIELD = 1359 +MIPS_INS_ENDING = 1360 +MIPS_INS_ALIAS_BEGIN = 1361 +MIPS_INS_ALIAS_ADDIU_B32 = 1362 +MIPS_INS_ALIAS_BITREVB = 1363 +MIPS_INS_ALIAS_BITREVH = 1364 +MIPS_INS_ALIAS_BYTEREVH = 1365 +MIPS_INS_ALIAS_NOT = 1366 +MIPS_INS_ALIAS_RESTORE_JRC = 1367 +MIPS_INS_ALIAS_RESTORE = 1368 +MIPS_INS_ALIAS_SAVE = 1369 +MIPS_INS_ALIAS_MOVE = 1370 +MIPS_INS_ALIAS_BAL = 1371 +MIPS_INS_ALIAS_JALR_HB = 1372 +MIPS_INS_ALIAS_NEG = 1373 +MIPS_INS_ALIAS_NEGU = 1374 +MIPS_INS_ALIAS_NOP = 1375 +MIPS_INS_ALIAS_BNEZL = 1376 +MIPS_INS_ALIAS_BEQZL = 1377 +MIPS_INS_ALIAS_SYSCALL = 1378 +MIPS_INS_ALIAS_BREAK = 1379 +MIPS_INS_ALIAS_EI = 1380 +MIPS_INS_ALIAS_DI = 1381 +MIPS_INS_ALIAS_TEQ = 1382 +MIPS_INS_ALIAS_TGE = 1383 +MIPS_INS_ALIAS_TGEU = 1384 +MIPS_INS_ALIAS_TLT = 1385 +MIPS_INS_ALIAS_TLTU = 1386 +MIPS_INS_ALIAS_TNE = 1387 +MIPS_INS_ALIAS_RDHWR = 1388 +MIPS_INS_ALIAS_SDBBP = 1389 +MIPS_INS_ALIAS_SYNC = 1390 +MIPS_INS_ALIAS_HYPCALL = 1391 +MIPS_INS_ALIAS_NOR = 1392 +MIPS_INS_ALIAS_C_F_S = 1393 +MIPS_INS_ALIAS_C_UN_S = 1394 +MIPS_INS_ALIAS_C_EQ_S = 1395 +MIPS_INS_ALIAS_C_UEQ_S = 1396 +MIPS_INS_ALIAS_C_OLT_S = 1397 +MIPS_INS_ALIAS_C_ULT_S = 1398 +MIPS_INS_ALIAS_C_OLE_S = 1399 +MIPS_INS_ALIAS_C_ULE_S = 1400 +MIPS_INS_ALIAS_C_SF_S = 1401 +MIPS_INS_ALIAS_C_NGLE_S = 1402 +MIPS_INS_ALIAS_C_SEQ_S = 1403 +MIPS_INS_ALIAS_C_NGL_S = 1404 +MIPS_INS_ALIAS_C_LT_S = 1405 +MIPS_INS_ALIAS_C_NGE_S = 1406 +MIPS_INS_ALIAS_C_LE_S = 1407 +MIPS_INS_ALIAS_C_NGT_S = 1408 +MIPS_INS_ALIAS_BC1T = 1409 +MIPS_INS_ALIAS_BC1F = 1410 +MIPS_INS_ALIAS_C_F_D = 1411 +MIPS_INS_ALIAS_C_UN_D = 1412 +MIPS_INS_ALIAS_C_EQ_D = 1413 +MIPS_INS_ALIAS_C_UEQ_D = 1414 +MIPS_INS_ALIAS_C_OLT_D = 1415 +MIPS_INS_ALIAS_C_ULT_D = 1416 +MIPS_INS_ALIAS_C_OLE_D = 1417 +MIPS_INS_ALIAS_C_ULE_D = 1418 +MIPS_INS_ALIAS_C_SF_D = 1419 +MIPS_INS_ALIAS_C_NGLE_D = 1420 +MIPS_INS_ALIAS_C_SEQ_D = 1421 +MIPS_INS_ALIAS_C_NGL_D = 1422 +MIPS_INS_ALIAS_C_LT_D = 1423 +MIPS_INS_ALIAS_C_NGE_D = 1424 +MIPS_INS_ALIAS_C_LE_D = 1425 +MIPS_INS_ALIAS_C_NGT_D = 1426 +MIPS_INS_ALIAS_BC1TL = 1427 +MIPS_INS_ALIAS_BC1FL = 1428 +MIPS_INS_ALIAS_DNEG = 1429 +MIPS_INS_ALIAS_DNEGU = 1430 +MIPS_INS_ALIAS_SLT = 1431 +MIPS_INS_ALIAS_SLTU = 1432 +MIPS_INS_ALIAS_SIGRIE = 1433 +MIPS_INS_ALIAS_JR = 1434 +MIPS_INS_ALIAS_JRC = 1435 +MIPS_INS_ALIAS_JALRC = 1436 +MIPS_INS_ALIAS_DIV = 1437 +MIPS_INS_ALIAS_DIVU = 1438 +MIPS_INS_ALIAS_LAPC = 1439 +MIPS_INS_ALIAS_WRDSP = 1440 +MIPS_INS_ALIAS_WAIT = 1441 +MIPS_INS_ALIAS_SW = 1442 +MIPS_INS_ALIAS_JALRC_HB = 1443 +MIPS_INS_ALIAS_ADDIU_B = 1444 +MIPS_INS_ALIAS_ADDIU_W = 1445 +MIPS_INS_ALIAS_JRC_HB = 1446 +MIPS_INS_ALIAS_BEQC = 1447 +MIPS_INS_ALIAS_BNEC = 1448 +MIPS_INS_ALIAS_BEQZC = 1449 +MIPS_INS_ALIAS_BNEZC = 1450 +MIPS_INS_ALIAS_MFC0 = 1451 +MIPS_INS_ALIAS_MFHC0 = 1452 +MIPS_INS_ALIAS_MTC0 = 1453 +MIPS_INS_ALIAS_MTHC0 = 1454 +MIPS_INS_ALIAS_DMT = 1455 +MIPS_INS_ALIAS_EMT = 1456 +MIPS_INS_ALIAS_DVPE = 1457 +MIPS_INS_ALIAS_EVPE = 1458 +MIPS_INS_ALIAS_YIELD = 1459 +MIPS_INS_ALIAS_MFTC0 = 1460 +MIPS_INS_ALIAS_MFTLO = 1461 +MIPS_INS_ALIAS_MFTHI = 1462 +MIPS_INS_ALIAS_MFTACX = 1463 +MIPS_INS_ALIAS_MTTC0 = 1464 +MIPS_INS_ALIAS_MTTLO = 1465 +MIPS_INS_ALIAS_MTTHI = 1466 +MIPS_INS_ALIAS_MTTACX = 1467 +MIPS_INS_ALIAS_END = 1468 MIPS_GRP_INVALID = 0 MIPS_GRP_JUMP = 1 @@ -826,37 +2121,60 @@ MIPS_GRP_IRET = 5 MIPS_GRP_PRIVILEGE = 6 MIPS_GRP_BRANCH_RELATIVE = 7 -MIPS_GRP_BITCOUNT = 128 -MIPS_GRP_DSP = 129 -MIPS_GRP_DSPR2 = 130 -MIPS_GRP_FPIDX = 131 -MIPS_GRP_MSA = 132 -MIPS_GRP_MIPS32R2 = 133 -MIPS_GRP_MIPS64 = 134 -MIPS_GRP_MIPS64R2 = 135 -MIPS_GRP_SEINREG = 136 -MIPS_GRP_STDENC = 137 -MIPS_GRP_SWAP = 138 -MIPS_GRP_MICROMIPS = 139 -MIPS_GRP_MIPS16MODE = 140 -MIPS_GRP_FP64BIT = 141 -MIPS_GRP_NONANSFPMATH = 142 -MIPS_GRP_NOTFP64BIT = 143 -MIPS_GRP_NOTINMICROMIPS = 144 -MIPS_GRP_NOTNACL = 145 -MIPS_GRP_NOTMIPS32R6 = 146 -MIPS_GRP_NOTMIPS64R6 = 147 -MIPS_GRP_CNMIPS = 148 -MIPS_GRP_MIPS32 = 149 -MIPS_GRP_MIPS32R6 = 150 -MIPS_GRP_MIPS64R6 = 151 -MIPS_GRP_MIPS2 = 152 -MIPS_GRP_MIPS3 = 153 -MIPS_GRP_MIPS3_32 = 154 -MIPS_GRP_MIPS3_32R2 = 155 -MIPS_GRP_MIPS4_32 = 156 -MIPS_GRP_MIPS4_32R2 = 157 -MIPS_GRP_MIPS5_32R2 = 158 -MIPS_GRP_GP32BIT = 159 -MIPS_GRP_GP64BIT = 160 -MIPS_GRP_ENDING = 161 +MIPS_FEATURE_HASMIPS2 = 128 +MIPS_FEATURE_HASMIPS3_32 = 129 +MIPS_FEATURE_HASMIPS3_32R2 = 130 +MIPS_FEATURE_HASMIPS3 = 131 +MIPS_FEATURE_NOTMIPS3 = 132 +MIPS_FEATURE_HASMIPS4_32 = 133 +MIPS_FEATURE_NOTMIPS4_32 = 134 +MIPS_FEATURE_HASMIPS4_32R2 = 135 +MIPS_FEATURE_HASMIPS5_32R2 = 136 +MIPS_FEATURE_HASMIPS32 = 137 +MIPS_FEATURE_HASMIPS32R2 = 138 +MIPS_FEATURE_HASMIPS32R5 = 139 +MIPS_FEATURE_HASMIPS32R6 = 140 +MIPS_FEATURE_NOTMIPS32R6 = 141 +MIPS_FEATURE_HASNANOMIPS = 142 +MIPS_FEATURE_NOTNANOMIPS = 143 +MIPS_FEATURE_ISGP64BIT = 144 +MIPS_FEATURE_ISGP32BIT = 145 +MIPS_FEATURE_ISPTR64BIT = 146 +MIPS_FEATURE_ISPTR32BIT = 147 +MIPS_FEATURE_HASMIPS64 = 148 +MIPS_FEATURE_NOTMIPS64 = 149 +MIPS_FEATURE_HASMIPS64R2 = 150 +MIPS_FEATURE_HASMIPS64R5 = 151 +MIPS_FEATURE_HASMIPS64R6 = 152 +MIPS_FEATURE_NOTMIPS64R6 = 153 +MIPS_FEATURE_INMIPS16MODE = 154 +MIPS_FEATURE_NOTINMIPS16MODE = 155 +MIPS_FEATURE_HASCNMIPS = 156 +MIPS_FEATURE_NOTCNMIPS = 157 +MIPS_FEATURE_HASCNMIPSP = 158 +MIPS_FEATURE_NOTCNMIPSP = 159 +MIPS_FEATURE_ISSYM32 = 160 +MIPS_FEATURE_ISSYM64 = 161 +MIPS_FEATURE_HASSTDENC = 162 +MIPS_FEATURE_INMICROMIPS = 163 +MIPS_FEATURE_NOTINMICROMIPS = 164 +MIPS_FEATURE_HASEVA = 165 +MIPS_FEATURE_HASMSA = 166 +MIPS_FEATURE_HASMADD4 = 167 +MIPS_FEATURE_HASMT = 168 +MIPS_FEATURE_USEINDIRECTJUMPSHAZARD = 169 +MIPS_FEATURE_NOINDIRECTJUMPGUARDS = 170 +MIPS_FEATURE_HASCRC = 171 +MIPS_FEATURE_HASVIRT = 172 +MIPS_FEATURE_HASGINV = 173 +MIPS_FEATURE_HASTLB = 174 +MIPS_FEATURE_ISFP64BIT = 175 +MIPS_FEATURE_NOTFP64BIT = 176 +MIPS_FEATURE_ISSINGLEFLOAT = 177 +MIPS_FEATURE_ISNOTSINGLEFLOAT = 178 +MIPS_FEATURE_ISNOTSOFTFLOAT = 179 +MIPS_FEATURE_HASMIPS3D = 180 +MIPS_FEATURE_HASDSP = 181 +MIPS_FEATURE_HASDSPR2 = 182 +MIPS_FEATURE_HASDSPR3 = 183 +MIPS_GRP_ENDING = 184 diff --git a/bindings/python/cstest_py/src/cstest_py/cs_modes.py b/bindings/python/cstest_py/src/cstest_py/cs_modes.py index 0290bca796..d8ef4219bf 100644 --- a/bindings/python/cstest_py/src/cstest_py/cs_modes.py +++ b/bindings/python/cstest_py/src/cstest_py/cs_modes.py @@ -38,4 +38,8 @@ "type": cs.CS_OPT_SYNTAX, "val": cs.CS_OPT_SYNTAX_PERCENT, }, + "CS_OPT_SYNTAX_NO_DOLLAR": { + "type": cs.CS_OPT_SYNTAX, + "val": cs.CS_OPT_SYNTAX_NO_DOLLAR, + }, } diff --git a/cs.c b/cs.c index 4bb739a407..755b982cd4 100644 --- a/cs.c +++ b/cs.c @@ -100,8 +100,33 @@ typedef struct cs_arch_config { { \ Mips_global_init, \ Mips_option, \ - ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 | CS_MODE_MICRO \ - | CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN | CS_MODE_MIPS2 | CS_MODE_MIPS3), \ + ~(CS_MODE_LITTLE_ENDIAN | \ + CS_MODE_BIG_ENDIAN | \ + CS_MODE_MIPS16 | \ + CS_MODE_MIPS32 | \ + CS_MODE_MIPS64 | \ + CS_MODE_MICRO | \ + CS_MODE_MIPS1 | \ + CS_MODE_MIPS2 | \ + CS_MODE_MIPS32R2 | \ + CS_MODE_MIPS32R3 | \ + CS_MODE_MIPS32R5 | \ + CS_MODE_MIPS32R6 | \ + CS_MODE_MIPS3 | \ + CS_MODE_MIPS4 | \ + CS_MODE_MIPS5 | \ + CS_MODE_MIPS64R2 | \ + CS_MODE_MIPS64R3 | \ + CS_MODE_MIPS64R5 | \ + CS_MODE_MIPS64R6 | \ + CS_MODE_OCTEON | \ + CS_MODE_OCTEONP | \ + CS_MODE_NANOMIPS | \ + CS_MODE_NMS1 | \ + CS_MODE_I7200 | \ + CS_MODE_MIPS_NOFLOAT | \ + CS_MODE_MIPS_PTR64 \ + ), \ } #define CS_ARCH_CONFIG_X86 \ { \ diff --git a/cstool/cstool.c b/cstool/cstool.c index 4951a237c8..2dba612f32 100644 --- a/cstool/cstool.c +++ b/cstool/cstool.c @@ -9,121 +9,210 @@ #include #include "cstool.h" +#ifdef CAPSTONE_AARCH64_COMPAT_HEADER +#define CS_ARCH_AARCH64 CS_ARCH_ARM +#endif + void print_string_hex(const char *comment, unsigned char *str, size_t len); static struct { const char *name; + const char *desc; + cs_arch archs[CS_ARCH_MAX]; + cs_opt_value opt; + cs_mode mode; +} all_opts[] = { + // cs_opt_value only + { "+att", "ATT syntax", { + CS_ARCH_X86, CS_ARCH_MAX }, CS_OPT_SYNTAX_ATT, 0 }, + { "+intel", "Intel syntax", { + CS_ARCH_X86, CS_ARCH_MAX }, CS_OPT_SYNTAX_INTEL, 0 }, + { "+masm", "Intel MASM syntax", { + CS_ARCH_X86, CS_ARCH_MAX }, CS_OPT_SYNTAX_MASM, 0 }, + { "+noregname", "Number only registers", { + CS_ARCH_AARCH64, CS_ARCH_ARM, CS_ARCH_LOONGARCH, + CS_ARCH_MIPS, CS_ARCH_PPC, CS_ARCH_MAX }, + CS_OPT_SYNTAX_NOREGNAME, 0 }, + { "+moto", "Use $ as hex prefix", { + CS_ARCH_MOS65XX, CS_ARCH_MAX }, CS_OPT_SYNTAX_MOTOROLA, 0 }, + { "+regalias", "Use register aliases, like r9 > sb", { + CS_ARCH_ARM, CS_ARCH_AARCH64, CS_ARCH_MAX }, + CS_OPT_SYNTAX_CS_REG_ALIAS, 0 }, + { "+percentage", "Adds % in front of the registers", { + CS_ARCH_PPC, CS_ARCH_MAX }, CS_OPT_SYNTAX_PERCENT, 0 }, + { "+nodollar", "Removes $ in front of the registers", { + CS_ARCH_MIPS, CS_ARCH_MAX }, CS_OPT_SYNTAX_NO_DOLLAR, 0 }, + // cs_mode only + { "+nofloat", "Disables floating point support", { + CS_ARCH_MIPS, CS_ARCH_MAX }, 0, CS_MODE_MIPS_NOFLOAT }, + { "+ptr64", "Enables 64-bit pointers support", { + CS_ARCH_MIPS, CS_ARCH_MAX }, 0, CS_MODE_MIPS_PTR64 }, + { NULL } +}; + +static struct { + const char *name; + const char *desc; cs_arch arch; cs_mode mode; } all_archs[] = { - { "arm", CS_ARCH_ARM, CS_MODE_ARM }, - { "armb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_BIG_ENDIAN }, - { "armbe", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_BIG_ENDIAN }, - { "arml", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_LITTLE_ENDIAN }, - { "armle", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_LITTLE_ENDIAN }, - { "armv8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 }, - { "thumbv8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 }, - { "armv8be", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 | CS_MODE_BIG_ENDIAN }, - { "thumbv8be", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 | CS_MODE_BIG_ENDIAN }, - { "cortexm", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS }, - { "cortexv8m", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS | CS_MODE_V8 }, - { "thumb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB }, - { "thumbbe", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN }, - { "thumble", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_LITTLE_ENDIAN }, - { "aarch64", CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN }, - { "aarch64be", CS_ARCH_AARCH64, CS_MODE_BIG_ENDIAN }, - { "mips", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_LITTLE_ENDIAN }, - { "mipsmicro", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_MICRO }, - { "mipsbemicro", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_MICRO | CS_MODE_BIG_ENDIAN }, - { "mipsbe32r6", CS_ARCH_MIPS, CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN}, - { "mipsbe32r6micro", CS_ARCH_MIPS, CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN | CS_MODE_MICRO }, - { "mips32r6", CS_ARCH_MIPS, CS_MODE_MIPS32R6 }, - { "mips32r6micro", CS_ARCH_MIPS, CS_MODE_MIPS32R6 | CS_MODE_MICRO }, - { "mipsbe", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN }, - { "mips64", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN }, - { "mips64be", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_BIG_ENDIAN }, - { "x16", CS_ARCH_X86, CS_MODE_16 }, // CS_MODE_16 - { "x16att", CS_ARCH_X86, CS_MODE_16 }, // CS_MODE_16 , CS_OPT_SYNTAX_ATT - { "x32", CS_ARCH_X86, CS_MODE_32 }, // CS_MODE_32 - { "x32att", CS_ARCH_X86, CS_MODE_32 }, // CS_MODE_32, CS_OPT_SYNTAX_ATT - { "x64", CS_ARCH_X86, CS_MODE_64 }, // CS_MODE_64 - { "x64att", CS_ARCH_X86, CS_MODE_64 }, // CS_MODE_64, CS_OPT_SYNTAX_ATT - { "ppc32", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_LITTLE_ENDIAN }, - { "ppc32be", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_BIG_ENDIAN }, - { "ppc32qpx", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN }, - { "ppc32beqpx", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN }, - { "ppc32ps", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_PS | CS_MODE_LITTLE_ENDIAN }, - { "ppc32beps", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_PS | CS_MODE_BIG_ENDIAN }, - { "ppc64", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_LITTLE_ENDIAN }, - { "ppc64be", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN }, - { "ppc64qpx", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN }, - { "ppc64beqpx", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN }, - { "sparc", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN }, - { "sparcv9", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN | CS_MODE_V9 }, - { "systemz", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN }, - { "sysz", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN }, - { "s390x", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN }, - { "xcore", CS_ARCH_XCORE, CS_MODE_BIG_ENDIAN }, - { "m68k", CS_ARCH_M68K, CS_MODE_BIG_ENDIAN }, - { "m68k40", CS_ARCH_M68K, CS_MODE_M68K_040 }, - { "tms320c64x", CS_ARCH_TMS320C64X, CS_MODE_BIG_ENDIAN }, - { "m6800", CS_ARCH_M680X, CS_MODE_M680X_6800 }, - { "m6801", CS_ARCH_M680X, CS_MODE_M680X_6801 }, - { "m6805", CS_ARCH_M680X, CS_MODE_M680X_6805 }, - { "m6808", CS_ARCH_M680X, CS_MODE_M680X_6808 }, - { "m6809", CS_ARCH_M680X, CS_MODE_M680X_6809 }, - { "m6811", CS_ARCH_M680X, CS_MODE_M680X_6811 }, - { "cpu12", CS_ARCH_M680X, CS_MODE_M680X_CPU12 }, - { "hd6301", CS_ARCH_M680X, CS_MODE_M680X_6301 }, - { "hd6309", CS_ARCH_M680X, CS_MODE_M680X_6309 }, - { "hcs08", CS_ARCH_M680X, CS_MODE_M680X_HCS08 }, - { "evm", CS_ARCH_EVM, 0 }, - { "wasm", CS_ARCH_WASM, 0 }, - { "bpf", CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC }, - { "bpfbe", CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_CLASSIC }, - { "ebpf", CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED }, - { "ebpfbe", CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_EXTENDED }, - { "riscv32", CS_ARCH_RISCV, CS_MODE_RISCV32 | CS_MODE_RISCVC }, - { "riscv64", CS_ARCH_RISCV, CS_MODE_RISCV64 | CS_MODE_RISCVC }, - { "6502", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_6502 }, - { "65c02", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65C02 }, - { "w65c02", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_W65C02 }, - { "65816", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65816_LONG_MX }, - { "sh", CS_ARCH_SH, CS_MODE_BIG_ENDIAN }, - { "sh2", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_BIG_ENDIAN}, - { "sh2e", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_SHFPU | CS_MODE_BIG_ENDIAN}, - { "sh-dsp", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_SHDSP | CS_MODE_BIG_ENDIAN}, - { "sh2a", CS_ARCH_SH, CS_MODE_SH2A | CS_MODE_BIG_ENDIAN}, - { "sh2a-fpu", CS_ARCH_SH, CS_MODE_SH2A | CS_MODE_SHFPU | CS_MODE_BIG_ENDIAN}, - { "sh3", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 }, - { "sh3be", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 }, - { "sh3e", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 | CS_MODE_SHFPU}, - { "sh3ebe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 | CS_MODE_SHFPU}, - { "sh3-dsp", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 | CS_MODE_SHDSP }, - { "sh3-dspbe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 | CS_MODE_SHDSP }, - { "sh4", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4 | CS_MODE_SHFPU }, - { "sh4be", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4 | CS_MODE_SHFPU }, - { "sh4a", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4A | CS_MODE_SHFPU }, - { "sh4abe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4A | CS_MODE_SHFPU }, - { "sh4al-dsp", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4A | CS_MODE_SHDSP | CS_MODE_SHFPU }, - { "sh4al-dspbe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4A | CS_MODE_SHDSP | CS_MODE_SHFPU }, - { "tc110", CS_ARCH_TRICORE, CS_MODE_TRICORE_110 }, - { "tc120", CS_ARCH_TRICORE, CS_MODE_TRICORE_120 }, - { "tc130", CS_ARCH_TRICORE, CS_MODE_TRICORE_130 }, - { "tc131", CS_ARCH_TRICORE, CS_MODE_TRICORE_131 }, - { "tc160", CS_ARCH_TRICORE, CS_MODE_TRICORE_160 }, - { "tc161", CS_ARCH_TRICORE, CS_MODE_TRICORE_161 }, - { "tc162", CS_ARCH_TRICORE, CS_MODE_TRICORE_162 }, - { "alpha", CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN }, - { "alphabe", CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN }, - { "hppa11", CS_ARCH_HPPA, CS_MODE_HPPA_11 | CS_MODE_LITTLE_ENDIAN }, - { "hppa11be", CS_ARCH_HPPA, CS_MODE_HPPA_11 | CS_MODE_BIG_ENDIAN }, - { "hppa20", CS_ARCH_HPPA, CS_MODE_HPPA_20 | CS_MODE_LITTLE_ENDIAN }, - { "hppa20be", CS_ARCH_HPPA, CS_MODE_HPPA_20 | CS_MODE_BIG_ENDIAN }, - { "hppa20w", CS_ARCH_HPPA, CS_MODE_HPPA_20W | CS_MODE_LITTLE_ENDIAN }, - { "hppa20wbe", CS_ARCH_HPPA, CS_MODE_HPPA_20W | CS_MODE_BIG_ENDIAN }, - { "loongarch32", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH32 }, - { "loongarch64", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64 }, + { "arm", "ARM, little endian", CS_ARCH_ARM, CS_MODE_ARM }, + { "armle", "ARM, little endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_LITTLE_ENDIAN }, + { "armbe", "ARM, big endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_BIG_ENDIAN }, + { "armv8", "ARM v8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 }, + { "armv8be", "ARM v8, big endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 | CS_MODE_BIG_ENDIAN }, + { "cortexm", "ARM Cortex-M Thumb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS }, + { "cortexmv8", "ARM Cortex-M Thumb, v8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS | CS_MODE_V8 }, + { "thumb", "ARM Thumb mode, little endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB }, + { "thumble", "ARM Thumb mode, little endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_LITTLE_ENDIAN }, + { "thumbbe", "ARM Thumb mode, big endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN }, + { "thumbv8", "ARM Thumb v8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 }, + { "thumbv8be", "ARM Thumb v8, big endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 | CS_MODE_BIG_ENDIAN }, + + { "aarch64", "AArch64", CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN }, + { "aarch64be", "AArch64, big endian", CS_ARCH_AARCH64, CS_MODE_BIG_ENDIAN }, + + { "alpha", "Alpha, little endian", CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN }, + { "alphabe", "Alpha, big endian", CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN }, + + { "hppa11", "HPPA V1.1, little endian", CS_ARCH_HPPA, CS_MODE_HPPA_11 | CS_MODE_LITTLE_ENDIAN }, + { "hppa11be", "HPPA V1.1, big endian", CS_ARCH_HPPA, CS_MODE_HPPA_11 | CS_MODE_BIG_ENDIAN }, + { "hppa20", "HPPA V2.0, little endian", CS_ARCH_HPPA, CS_MODE_HPPA_20 | CS_MODE_LITTLE_ENDIAN }, + { "hppa20be", "HPPA V2.0, big endian", CS_ARCH_HPPA, CS_MODE_HPPA_20 | CS_MODE_BIG_ENDIAN }, + { "hppa20w", "HPPA V2.0 wide, little endian", CS_ARCH_HPPA, CS_MODE_HPPA_20W | CS_MODE_LITTLE_ENDIAN }, + { "hppa20wbe", "HPPA V2.0 wide, big endian", CS_ARCH_HPPA, CS_MODE_HPPA_20W | CS_MODE_BIG_ENDIAN }, + + { "mipsel16", "Mips 16-bit (generic), little endian", CS_ARCH_MIPS, CS_MODE_MIPS16 }, + { "mips16", "Mips 16-bit (generic)", CS_ARCH_MIPS, CS_MODE_MIPS16 | CS_MODE_BIG_ENDIAN }, + { "mipsel", "Mips 32-bit (generic), little endian", CS_ARCH_MIPS, CS_MODE_MIPS32 }, + { "mips", "Mips 32-bit (generic)", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN }, + { "mipsel64", "Mips 64-bit (generic), little endian", CS_ARCH_MIPS, CS_MODE_MIPS64 }, + { "mips64", "Mips 64-bit (generic)", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_BIG_ENDIAN }, + { "micromipsel", "MicroMips, little endian", CS_ARCH_MIPS, CS_MODE_MICRO }, + { "micromips", "MicroMips", CS_ARCH_MIPS, CS_MODE_MICRO | CS_MODE_BIG_ENDIAN }, + { "micromipselr3", "MicroMips32r3, little endian", CS_ARCH_MIPS, CS_MODE_MICRO32R3 }, + { "micromipsr3", "MicroMips32r3", CS_ARCH_MIPS, CS_MODE_MICRO32R3 | CS_MODE_BIG_ENDIAN }, + { "micromipselr6", "MicroMips32r6, little endian", CS_ARCH_MIPS, CS_MODE_MICRO32R6 }, + { "micromipsr6", "MicroMips32r6", CS_ARCH_MIPS, CS_MODE_MICRO32R6 | CS_MODE_BIG_ENDIAN }, + { "mipsel1", "Mips I ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS1 }, + { "mips1", "Mips I ISA", CS_ARCH_MIPS, CS_MODE_MIPS1 | CS_MODE_BIG_ENDIAN }, + { "mipsel2", "Mips II ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS2 }, + { "mips2", "Mips II ISA", CS_ARCH_MIPS, CS_MODE_MIPS2 | CS_MODE_BIG_ENDIAN }, + { "mipsel32r2", "Mips32 r2 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS32R2 }, + { "mips32r2", "Mips32 r2 ISA", CS_ARCH_MIPS, CS_MODE_MIPS32R2 | CS_MODE_BIG_ENDIAN }, + { "mipsel32r3", "Mips32 r3 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS32R3 }, + { "mips32r3", "Mips32 r3 ISA", CS_ARCH_MIPS, CS_MODE_MIPS32R3 | CS_MODE_BIG_ENDIAN }, + { "mipsel32r5", "Mips32 r5 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS32R5 }, + { "mips32r5", "Mips32 r5 ISA", CS_ARCH_MIPS, CS_MODE_MIPS32R5 | CS_MODE_BIG_ENDIAN }, + { "mipsel32r6", "Mips32 r6 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS32R6 }, + { "mips32r6", "Mips32 r6 ISA", CS_ARCH_MIPS, CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN }, + { "mipsel3", "Mips III ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS3 }, + { "mips3", "Mips III ISA", CS_ARCH_MIPS, CS_MODE_MIPS3 | CS_MODE_BIG_ENDIAN }, + { "mipsel4", "Mips IV ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS4 }, + { "mips4", "Mips IV ISA", CS_ARCH_MIPS, CS_MODE_MIPS4 | CS_MODE_BIG_ENDIAN }, + { "mipsel5", "Mips V ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS5 }, + { "mips5", "Mips V ISA", CS_ARCH_MIPS, CS_MODE_MIPS5 | CS_MODE_BIG_ENDIAN }, + { "mipsel64r2", "Mips64 r2 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS64R2 }, + { "mips64r2", "Mips64 r2 ISA", CS_ARCH_MIPS, CS_MODE_MIPS64R2 | CS_MODE_BIG_ENDIAN }, + { "mipsel64r3", "Mips64 r3 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS64R3 }, + { "mips64r3", "Mips64 r3 ISA", CS_ARCH_MIPS, CS_MODE_MIPS64R3 | CS_MODE_BIG_ENDIAN }, + { "mipsel64r5", "Mips64 r5 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS64R5 }, + { "mips64r5", "Mips64 r5 ISA", CS_ARCH_MIPS, CS_MODE_MIPS64R5 | CS_MODE_BIG_ENDIAN }, + { "mipsel64r6", "Mips64 r6 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS64R6 }, + { "mips64r6", "Mips64 r6 ISA", CS_ARCH_MIPS, CS_MODE_MIPS64R6 | CS_MODE_BIG_ENDIAN }, + { "octeonle", "Octeon cnMIPS, little endian", CS_ARCH_MIPS, CS_MODE_OCTEON }, + { "octeon", "Octeon cnMIPS", CS_ARCH_MIPS, CS_MODE_OCTEON | CS_MODE_BIG_ENDIAN }, + { "octeonple", "Octeon+ cnMIPS, little endian", CS_ARCH_MIPS, CS_MODE_OCTEONP }, + { "octeonp", "Octeon+ cnMIPS", CS_ARCH_MIPS, CS_MODE_OCTEONP | CS_MODE_BIG_ENDIAN }, + { "nanomips", "nanoMIPS", CS_ARCH_MIPS, CS_MODE_NANOMIPS }, + { "nms1", "nanoMIPS Subset", CS_ARCH_MIPS, CS_MODE_NMS1 }, + { "i7200", "nanoMIPS i7200", CS_ARCH_MIPS, CS_MODE_I7200 }, + + { "x16", "x86 16-bit mode", CS_ARCH_X86, CS_MODE_16 }, // CS_MODE_16 + { "x32", "x86 32-bit mode", CS_ARCH_X86, CS_MODE_32 }, // CS_MODE_32 + { "x64", "x86 64-bit mode", CS_ARCH_X86, CS_MODE_64 }, // CS_MODE_64 + + { "ppc32", "PowerPC 32-bit, little endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_LITTLE_ENDIAN }, + { "ppc32be", "PowerPC 32-bit, big endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_BIG_ENDIAN }, + { "ppc32qpx", "PowerPC 32-bit, qpx, little endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN }, + { "ppc32beqpx", "PowerPC 32-bit, qpx, big endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN }, + { "ppc32ps", "PowerPC 32-bit, ps, little endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_PS | CS_MODE_LITTLE_ENDIAN }, + { "ppc32beps", "PowerPC 32-bit, ps, big endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_PS | CS_MODE_BIG_ENDIAN }, + { "ppc64", "PowerPC 64-bit, little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_LITTLE_ENDIAN }, + { "ppc64be", "PowerPC 64-bit, big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN }, + { "ppc64qpx", "PowerPC 64-bit, qpx, little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN }, + { "ppc64beqpx", "PowerPC 64-bit, qpx, big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN }, + + { "sparc", "Sparc, big endian", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN }, + { "sparcv9", "Sparc v9, big endian", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN | CS_MODE_V9 }, + + { "systemz", "SystemZ, big endian", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN }, + { "s390x", "SystemZ s390x, big endian", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN }, + + { "xcore", "xcore, big endian", CS_ARCH_XCORE, CS_MODE_BIG_ENDIAN }, + + { "m68k", "m68k + big endian", CS_ARCH_M68K, CS_MODE_BIG_ENDIAN }, + { "m68k40", "m68k40", CS_ARCH_M68K, CS_MODE_M68K_040 }, + + { "tms320c64x", "tms320c64x, big endian", CS_ARCH_TMS320C64X, CS_MODE_BIG_ENDIAN }, + + { "m6800", "m680x, M6800/2", CS_ARCH_M680X, CS_MODE_M680X_6800 }, + { "m6801", "m680x, M6801/3", CS_ARCH_M680X, CS_MODE_M680X_6801 }, + { "m6805", "m680x, M6805", CS_ARCH_M680X, CS_MODE_M680X_6805 }, + { "m6808", "m680x, M68HC08", CS_ARCH_M680X, CS_MODE_M680X_6808 }, + { "m6809", "m680x, M6809", CS_ARCH_M680X, CS_MODE_M680X_6809 }, + { "m6811", "m680x, M68HC11", CS_ARCH_M680X, CS_MODE_M680X_6811 }, + { "cpu12", "m680x, M68HC12/HCS12", CS_ARCH_M680X, CS_MODE_M680X_CPU12 }, + { "hd6301", "m680x, HD6301/3", CS_ARCH_M680X, CS_MODE_M680X_6301 }, + { "hd6309", "m680x, HD6309", CS_ARCH_M680X, CS_MODE_M680X_6309 }, + { "hcs08", "m680x, HCS08", CS_ARCH_M680X, CS_MODE_M680X_HCS08 }, + + { "evm", "ethereum virtual machine", CS_ARCH_EVM, 0 }, + + { "wasm", "web assembly", CS_ARCH_WASM, 0 }, + + { "bpf", "Classic BPF, little endian", CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC }, + { "bpfbe", "Classic BPF, big endian", CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_CLASSIC }, + { "ebpf", "Extended BPF, little endian", CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED }, + { "ebpfbe", "Extended BPF, big endian", CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_EXTENDED }, + + { "riscv32", "Risc-V 32-bit, little endian", CS_ARCH_RISCV, CS_MODE_RISCV32 | CS_MODE_RISCVC }, + { "riscv64", "Risc-V 64-bit, little endian", CS_ARCH_RISCV, CS_MODE_RISCV64 | CS_MODE_RISCVC }, + + { "6502", "MOS 6502", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_6502 }, + { "65c02", "WDC 65c02", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65C02 }, + { "w65c02", "WDC w65c02", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_W65C02 }, + { "65816", "WDC 65816 (long m/x)", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65816_LONG_MX }, + + { "sh", "SuperH SH1", CS_ARCH_SH, CS_MODE_BIG_ENDIAN }, + { "sh2", "SuperH SH2", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_BIG_ENDIAN}, + { "sh2e", "SuperH SH2E", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_SHFPU | CS_MODE_BIG_ENDIAN}, + { "sh-dsp", "SuperH SH2-DSP", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_SHDSP | CS_MODE_BIG_ENDIAN}, + { "sh2a", "SuperH SH2A", CS_ARCH_SH, CS_MODE_SH2A | CS_MODE_BIG_ENDIAN}, + { "sh2a-fpu", "SuperH SH2A-FPU", CS_ARCH_SH, CS_MODE_SH2A | CS_MODE_SHFPU | CS_MODE_BIG_ENDIAN}, + { "sh3", "SuperH SH3", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 }, + { "sh3be", "SuperH SH3, big endian", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 }, + { "sh3e", "SuperH SH3E", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 | CS_MODE_SHFPU}, + { "sh3ebe", "SuperH SH3E, big endian", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 | CS_MODE_SHFPU}, + { "sh3-dsp", "SuperH SH3-DSP", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 | CS_MODE_SHDSP }, + { "sh3-dspbe", "SuperH SH3-DSP, big endian", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 | CS_MODE_SHDSP }, + { "sh4", "SuperH SH4", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4 | CS_MODE_SHFPU }, + { "sh4be", "SuperH SH4, big endian", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4 | CS_MODE_SHFPU }, + { "sh4a", "SuperH SH4A", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4A | CS_MODE_SHFPU }, + { "sh4abe", "SuperH SH4A, big endian", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4A | CS_MODE_SHFPU }, + { "sh4al-dsp", "SuperH SH4AL-DSP", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4A | CS_MODE_SHDSP | CS_MODE_SHFPU }, + { "sh4al-dspbe", "SuperH SH4AL-DSP, big endian", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4A | CS_MODE_SHDSP | CS_MODE_SHFPU }, + + { "tc110", "Tricore V1.1", CS_ARCH_TRICORE, CS_MODE_TRICORE_110 }, + { "tc120", "Tricore V1.2", CS_ARCH_TRICORE, CS_MODE_TRICORE_120 }, + { "tc130", "Tricore V1.3", CS_ARCH_TRICORE, CS_MODE_TRICORE_130 }, + { "tc131", "Tricore V1.3.1", CS_ARCH_TRICORE, CS_MODE_TRICORE_131 }, + { "tc160", "Tricore V1.6", CS_ARCH_TRICORE, CS_MODE_TRICORE_160 }, + { "tc161", "Tricore V1.6.1", CS_ARCH_TRICORE, CS_MODE_TRICORE_161 }, + { "tc162", "Tricore V1.6.2", CS_ARCH_TRICORE, CS_MODE_TRICORE_162 }, + + { "loongarch32", "LoongArch 32-bit", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH32 }, + { "loongarch64", "LoongArch 64-bit", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64 }, { NULL } }; @@ -185,168 +274,63 @@ static uint8_t *preprocess(char *code, size_t *size) return result; } -static void usage(char *prog) +static const char *get_arch_name(cs_arch arch) { - printf("Cstool for Capstone Disassembler Engine v%u.%u.%u\n\n", CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA); - printf("Syntax: %s [-d|-a|-r|-s|-u|-v] [start-address-in-hex-format]\n", prog); - printf("\nThe following options are supported:\n"); - - if (cs_support(CS_ARCH_X86)) { - printf(" x16 16-bit mode (X86)\n"); - printf(" x32 32-bit mode (X86)\n"); - printf(" x64 64-bit mode (X86)\n"); - printf(" x16att 16-bit mode (X86), syntax AT&T\n"); - printf(" x32att 32-bit mode (X86), syntax AT&T\n"); - printf(" x64att 64-bit mode (X86), syntax AT&T\n"); - } - - if (cs_support(CS_ARCH_ARM)) { - printf(" arm arm\n"); - printf(" armbe arm + big endian\n"); - printf(" thumb thumb mode\n"); - printf(" thumbbe thumb + big endian\n"); - printf(" cortexm thumb + cortex-m extensions\n"); - printf(" cortexv8m thumb + cortex-m extensions + v8\n"); - printf(" armv8 arm v8\n"); - printf(" thumbv8 thumb v8\n"); - printf(" armv8be arm v8 + big endian\n"); - printf(" thumbv8be thumb v8 + big endian\n"); - } - - if (cs_support(CS_ARCH_AARCH64)) { - printf(" aarch64 aarch64 mode\n"); - printf(" aarch64be aarch64 + big endian\n"); - } - - if (cs_support(CS_ARCH_ALPHA)) { - printf(" alpha alpha + little endian\n"); - printf(" alphabe alpha + big endian\n"); - } - - if (cs_support(CS_ARCH_HPPA)) { - printf(" hppa11 hppa V1.1 + little endian\n"); - printf(" hppa11be hppa V1.1 + big endian\n"); - printf(" hppa20 hppa V2.0 + little endian\n"); - printf(" hppa20be hppa V2.0 + big endian\n"); - printf(" hppa20w hppa V2.0 wide + little endian\n"); - printf(" hppa20wbe hppa V2.0 wide + big endian\n"); - } - - if (cs_support(CS_ARCH_MIPS)) { - printf(" mips mips32 + little endian\n"); - printf(" mipsbe mips32 + big endian\n"); - printf(" mips64 mips64 + little endian\n"); - printf(" mips64be mips64 + big endian\n"); - } - - if (cs_support(CS_ARCH_PPC)) { - printf(" ppc32 ppc32 + little endian\n"); - printf(" ppc32be ppc32 + big endian\n"); - printf(" ppc32qpx ppc32 + qpx + little endian\n"); - printf(" ppc32beqpx ppc32 + qpx + big endian\n"); - printf(" ppc32ps ppc32 + ps + little endian\n"); - printf(" ppc32beps ppc32 + ps + big endian\n"); - printf(" ppc64 ppc64 + little endian\n"); - printf(" ppc64be ppc64 + big endian\n"); - printf(" ppc64qpx ppc64 + qpx + little endian\n"); - printf(" ppc64beqpx ppc64 + qpx + big endian\n"); - } - - if (cs_support(CS_ARCH_SPARC)) { - printf(" sparc sparc\n"); - } - - if (cs_support(CS_ARCH_SYSZ)) { - printf(" systemz systemz (s390x)\n"); - } - - if (cs_support(CS_ARCH_XCORE)) { - printf(" xcore xcore\n"); - } - - if (cs_support(CS_ARCH_M68K)) { - printf(" m68k m68k + big endian\n"); - printf(" m68k40 m68k_040\n"); - } - - if (cs_support(CS_ARCH_TMS320C64X)) { - printf(" tms320c64x TMS320C64x\n"); - } - - if (cs_support(CS_ARCH_M680X)) { - printf(" m6800 M6800/2\n"); - printf(" m6801 M6801/3\n"); - printf(" m6805 M6805\n"); - printf(" m6808 M68HC08\n"); - printf(" m6809 M6809\n"); - printf(" m6811 M68HC11\n"); - printf(" cpu12 M68HC12/HCS12\n"); - printf(" hd6301 HD6301/3\n"); - printf(" hd6309 HD6309\n"); - printf(" hcs08 HCS08\n"); - } - - if (cs_support(CS_ARCH_EVM)) { - printf(" evm Ethereum Virtual Machine\n"); - } - - if (cs_support(CS_ARCH_MOS65XX)) { - printf(" 6502 MOS 6502\n"); - printf(" 65c02 WDC 65c02\n"); - printf(" w65c02 WDC w65c02\n"); - printf(" 65816 WDC 65816 (long m/x)\n"); - } - - if (cs_support(CS_ARCH_WASM)) { - printf(" wasm: Web Assembly\n"); - } - - if (cs_support(CS_ARCH_BPF)) { - printf(" bpf Classic BPF\n"); - printf(" bpfbe Classic BPF + big endian\n"); - printf(" ebpf Extended BPF\n"); - printf(" ebpfbe Extended BPF + big endian\n"); - } - - if (cs_support(CS_ARCH_RISCV)) { - printf(" riscv32 riscv32\n"); - printf(" riscv64 riscv64\n"); + switch(arch) { + case CS_ARCH_ARM: return "ARM"; + case CS_ARCH_AARCH64: return "Arm64"; + case CS_ARCH_MIPS: return "Mips"; + case CS_ARCH_X86: return "x86"; + case CS_ARCH_PPC: return "PowerPC"; + case CS_ARCH_SPARC: return "Sparc"; + case CS_ARCH_SYSZ: return "SysZ"; + case CS_ARCH_XCORE: return "Xcore"; + case CS_ARCH_M68K: return "M68K"; + case CS_ARCH_TMS320C64X: return "TMS320C64X"; + case CS_ARCH_M680X: return "M680X"; + case CS_ARCH_EVM: return "Evm"; + case CS_ARCH_MOS65XX: return "MOS65XX"; + case CS_ARCH_WASM: return "Wasm"; + case CS_ARCH_BPF: return "BPF"; + case CS_ARCH_RISCV: return "RiscV"; + case CS_ARCH_SH: return "SH"; + case CS_ARCH_TRICORE: return "TriCore"; + case CS_ARCH_ALPHA: return "Alpha"; + case CS_ARCH_HPPA: return "HPPA"; + case CS_ARCH_LOONGARCH: return "LoongArch"; + default: return NULL; } +} - if (cs_support(CS_ARCH_SH)) { - printf(" sh superh SH1\n"); - printf(" sh2 superh SH2\n"); - printf(" sh2e superh SH2E\n"); - printf(" sh2dsp superh SH2-DSP\n"); - printf(" sh2a superh SH2A\n"); - printf(" sh2afpu superh SH2A-FPU\n"); - printf(" sh3 superh SH3\n"); - printf(" sh3be superh SH3 big endian\n"); - printf(" sh3e superh SH3E\n"); - printf(" sh3ebe superh SH3E big endian\n"); - printf(" sh3-dsp superh SH3-DSP\n"); - printf(" sh3-dspbe superh SH3-DSP big endian\n"); - printf(" sh4 superh SH4\n"); - printf(" sh4be superh SH4 big endian\n"); - printf(" sh4a superh SH4A\n"); - printf(" sh4abe superh SH4A big endian\n"); - printf(" sh4al-dsp superh SH4AL-DSP\n"); - printf(" sh4al-dspbe superh SH4AL-DSP big endian\n"); - } +static void usage(char *prog) +{ + int i, j; + printf("Cstool for Capstone Disassembler Engine v%u.%u.%u\n\n", CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA); + printf("Syntax: %s [-d|-a|-r|-s|-u|-v] [start-address-in-hex-format]\n", prog); + printf("\nThe following options are supported:\n"); - if (cs_support(CS_ARCH_TRICORE)) { - printf(" tc110 tricore V1.1\n"); - printf(" tc120 tricore V1.2\n"); - printf(" tc130 tricore V1.3\n"); - printf(" tc131 tricore V1.3.1\n"); - printf(" tc160 tricore V1.6\n"); - printf(" tc161 tricore V1.6.1\n"); - printf(" tc162 tricore V1.6.2\n"); + for (i = 0; all_archs[i].name; i++) { + if (cs_support(all_archs[i].arch)) { + printf(" %-16s %s\n", all_archs[i].name, all_archs[i].desc); + } } - if (cs_support(CS_ARCH_LOONGARCH)) { - printf(" loongarch32 LoongArch32\n"); - printf(" loongarch64 LoongArch64\n"); + printf("\nArch specific options:\n"); + for (i = 0; all_opts[i].name; i++) { + printf(" %-16s %s (only: ", all_opts[i].name, all_opts[i].desc); + for (j = 0; j < CS_ARCH_MAX; j++) { + cs_arch arch = all_opts[i].archs[j]; + const char *name = get_arch_name(arch); + if (!name) { + break; + } + if (j > 0) { + printf(", %s", name); + } else { + printf("%s", name); + } + } + printf(")\n"); } printf("\nExtra options:\n"); @@ -494,17 +478,55 @@ static void run_dev_fuzz(csh handle, uint8_t *bytes, uint32_t size) { } } +static cs_mode find_additional_modes(const char *input, cs_arch arch) { + if (!input) { + return 0; + } + cs_mode mode = 0; + int i, j; + for (i = 0; all_opts[i].name; i++) { + if (all_opts[i].opt || !strstr(input, all_opts[i].name)) { + continue; + } + for (j = 0; j < CS_ARCH_MAX; j++) { + if (arch == all_opts[i].archs[j]) { + mode |= all_opts[i].mode; + break; + } + } + } + return mode; +} + +static void enable_additional_options(csh handle, const char *input, cs_arch arch) { + if (!input) { + return; + } + int i, j; + for (i = 0; all_opts[i].name; i++) { + if (all_opts[i].mode || !strstr(input, all_opts[i].name)) { + continue; + } + for (j = 0; j < CS_ARCH_MAX; j++) { + if (arch == all_opts[i].archs[j]) { + cs_option(handle, CS_OPT_SYNTAX, all_opts[i].opt); + break; + } + } + } +} + int main(int argc, char **argv) { int i, c; csh handle; - char *mode; + char *choosen_arch; uint8_t *assembly; size_t count, size; uint64_t address = 0LL; cs_insn *insn; cs_err err; - cs_mode md; + cs_mode mode; cs_arch arch = CS_ARCH_ALL; bool detail_flag = false; bool unsigned_flag = false; @@ -647,7 +669,7 @@ int main(int argc, char **argv) return -1; } - mode = argv[optind]; + choosen_arch = argv[optind]; assembly = preprocess(argv[optind + 1], &size); if (!assembly) { usage(argv[0]); @@ -658,37 +680,46 @@ int main(int argc, char **argv) char *temp, *src = argv[optind + 2]; address = strtoull(src, &temp, 16); if (temp == src || *temp != '\0' || errno == ERANGE) { - printf("ERROR: invalid address argument, quit!\n"); + fprintf(stderr, "ERROR: invalid address argument, quit!\n"); return -2; } } + size_t arch_len = strlen(choosen_arch); + const char *plus = strchr(choosen_arch, '+'); + if (plus) { + arch_len = plus - choosen_arch; + } + for (i = 0; all_archs[i].name; i++) { - if (!strcmp(all_archs[i].name, mode)) { + size_t len = strlen(all_archs[i].name); + if (len == arch_len && !strncmp(all_archs[i].name, choosen_arch, arch_len)) { arch = all_archs[i].arch; - err = cs_open(all_archs[i].arch, all_archs[i].mode, &handle); + mode = all_archs[i].mode; + mode |= find_additional_modes(plus, arch); + + err = cs_open(all_archs[i].arch, mode, &handle); if (!err) { - md = all_archs[i].mode; - if (strstr (mode, "att")) { - cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT); - } + enable_additional_options(handle, plus, arch); // turn on SKIPDATA mode - if (skipdata) + if (skipdata) { cs_option(handle, CS_OPT_SKIPDATA, CS_OPT_ON); + } } break; } } if (arch == CS_ARCH_ALL) { - printf("ERROR: Invalid : \"%s\", quit!\n", mode); + fprintf(stderr, "ERROR: Invalid : \"%s\", quit!\n", choosen_arch); usage(argv[0]); return -1; } if (err) { - printf("ERROR: Failed on cs_open(), quit!\n"); + const char *error = cs_strerror(err); + fprintf(stderr, "ERROR: Failed on cs_open(): %s\n", error); usage(argv[0]); return -1; } @@ -745,14 +776,14 @@ int main(int argc, char **argv) printf(" %s\t%s\n", insn[i].mnemonic, insn[i].op_str); if (detail_flag) { - print_details(handle, arch, md, &insn[i]); + print_details(handle, arch, mode, &insn[i]); } } cs_free(insn, count); free(assembly); } else { - printf("ERROR: invalid assembly code\n"); + fprintf(stderr, "ERROR: invalid assembly code\n"); cs_close(&handle); free(assembly); return(-4); diff --git a/cstool/cstool_mips.c b/cstool/cstool_mips.c index a2d7e35a0d..8b133ea699 100644 --- a/cstool/cstool_mips.c +++ b/cstool/cstool_mips.c @@ -27,9 +27,11 @@ void print_insn_detail_mips(csh handle, cs_insn *ins) break; case MIPS_OP_REG: printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + printf("\t\toperands[%u].is_reglist: %s\n", i, op->is_reglist ? "true" : "false"); break; case MIPS_OP_IMM: printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); + printf("\t\toperands[%u].is_unsigned: %s\n", i, op->is_unsigned ? "true" : "false"); break; case MIPS_OP_MEM: printf("\t\toperands[%u].type: MEM\n", i); diff --git a/docs/cs_v6_release_guide.md b/docs/cs_v6_release_guide.md index bdaf379585..ee94914cdd 100644 --- a/docs/cs_v6_release_guide.md +++ b/docs/cs_v6_release_guide.md @@ -167,6 +167,53 @@ sed -i "s|detail->arm64|detail->aarch64|g" $1 Write it into `rename_arm64.sh` and run it on files with `sh rename_arm64.sh ` + +**Mips** + +| Keyword | Change | Justification | Possible revert | +|---------|--------|---------------|-----------------| +| `CS_OPT_SYNTAX_NO_DOLLAR` | Adds options which removes the `$` (dollar sign) from the register name. | New Feature | Enable option. | +| `CS_OPT_SYNTAX_NOREGNAME` | Implements the options to output raw register numbers (only the standard GPR are numeric). | Was not implemented | Enable option. | +| `cs_mips_op.uimm` | Access for the unsigned immediate value of the IMM operand. | Was missing | None. | +| `cs_mips_op.is_unsigned` | Defines if the IMM operand is signed (when false) or unsigned (when true). | Was missing | None. | +| `cs_mips_op.is_reglist` | Defines if the REG operand is part of a list of registers. | Was missing | None. | +| `cs_mips_op.access` | Defines how is this operand accessed, i.e. READ, WRITE or READ & WRITE. | Was missing | None. | + +**Note about AArch64** + +in `capstone.h` new mips ISA has been added which can be used by themselves. + +``` + CS_MODE_MIPS16 = CS_MODE_16, ///< Generic mips16 + CS_MODE_MIPS32 = CS_MODE_32, ///< Generic mips32 + CS_MODE_MIPS64 = CS_MODE_64, ///< Generic mips64 + CS_MODE_MICRO = 1 << 4, ///< microMips + CS_MODE_MIPS1 = 1 << 5, ///< Mips I ISA Support + CS_MODE_MIPS2 = 1 << 6, ///< Mips II ISA Support + CS_MODE_MIPS32R2 = 1 << 7, ///< Mips32r2 ISA Support + CS_MODE_MIPS32R3 = 1 << 8, ///< Mips32r3 ISA Support + CS_MODE_MIPS32R5 = 1 << 9, ///< Mips32r5 ISA Support + CS_MODE_MIPS32R6 = 1 << 10, ///< Mips32r6 ISA Support + CS_MODE_MIPS3 = 1 << 11, ///< MIPS III ISA Support + CS_MODE_MIPS4 = 1 << 12, ///< MIPS IV ISA Support + CS_MODE_MIPS5 = 1 << 13, ///< MIPS V ISA Support + CS_MODE_MIPS64R2 = 1 << 14, ///< Mips64r2 ISA Support + CS_MODE_MIPS64R3 = 1 << 15, ///< Mips64r3 ISA Support + CS_MODE_MIPS64R5 = 1 << 16, ///< Mips64r5 ISA Support + CS_MODE_MIPS64R6 = 1 << 17, ///< Mips64r6 ISA Support + CS_MODE_OCTEON = 1 << 18, ///< Octeon cnMIPS Support + CS_MODE_OCTEONP = 1 << 19, ///< Octeon+ cnMIPS Support + CS_MODE_NANOMIPS = 1 << 20, ///< Generic nanomips + CS_MODE_NMS1 = ((1 << 21) | CS_MODE_NANOMIPS), ///< nanoMips NMS1 + CS_MODE_I7200 = ((1 << 22) | CS_MODE_NANOMIPS), ///< nanoMips I7200 + CS_MODE_MICRO32R3 = (CS_MODE_MICRO | CS_MODE_MIPS32R3), ///< microMips32r3 + CS_MODE_MICRO32R6 = (CS_MODE_MICRO | CS_MODE_MIPS32R6), ///< microMips32r6 +``` + +It is also possible to disable floating point support by adding `CS_MODE_MIPS_NOFLOAT`. + +**`CS_MODE_MIPS_PTR64` is now required to decode 64-bit pointers**, like jumps and calls (for example: `jal $t0`). + ## New features These features are only supported by `auto-sync`-enabled architectures. @@ -250,3 +297,47 @@ Nonetheless, an alias should never be **decoded** as real instruction. If you find an alias which is decoded as a real instruction, please let us know. Such an instruction is ill-defined in LLVM and should be fixed upstream. + +### Refactoring of cstool + +`cstool` has been refactored to simplify its usage; before you needed to add extra options in the C code to enable features and recompile, but now you can easily decode instructions with different syntaxes or options, by appending after the arch one of the followings values: + +``` ++att ATT syntax (only: x86) ++intel Intel syntax (only: x86) ++masm Intel MASM syntax (only: x86) ++noregname Number only registers (only: Arm64, ARM, LoongArch, Mips, PowerPC) ++moto Use $ as hex prefix (only: MOS65XX) ++regalias Use register aliases, like r9 > sb (only: ARM, Arm64) ++percentage Adds % in front of the registers (only: PowerPC) ++nodollar Removes $ in front of the registers (only: Mips) ++nofloat Disables floating point support (only: Mips) ++ptr64 Enables 64-bit pointers support (only: Mips) +``` + +For example: +``` +$ cstool -s ppc32+percentage 0c100097 + 0 0c 10 00 97 stwu %r24, 0x100c(0) +$ cstool -s ppc32 0c100097 + 0 0c 10 00 97 stwu r24, 0x100c(0) +$ cstool -s x32+att 0c1097 + 0 0c 10 orb $0x10, %al + 2 97 xchgl %eax, %edi +$ cstool -s x32+intel 0c1097 + 0 0c 10 or al, 0x10 + 2 97 xchg edi, eax +$ cstool -s x32+masm 0c1097 + 0 0c 10 or al, 10h + 2 97 xchg edi, eax +$ cstool -s arm+regalias 0c100097000000008fa2000034213456 + 0 0c 10 00 97 strls r1, [r0, -ip] + 4 00 00 00 00 andeq r0, r0, r0 + 8 8f a2 00 00 andeq sl, r0, pc, lsl #5 +10 34 21 34 56 shasxpl r2, r4, r4 +$ cstool -s arm 0c100097000000008fa2000034213456 + 0 0c 10 00 97 strls r1, [r0, -r12] + 4 00 00 00 00 andeq r0, r0, r0 + 8 8f a2 00 00 andeq r10, r0, pc, lsl #5 +10 34 21 34 56 shasxpl r2, r4, r4 +``` \ No newline at end of file diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h index 7de50bfd18..6fa23162ed 100644 --- a/include/capstone/capstone.h +++ b/include/capstone/capstone.h @@ -183,10 +183,6 @@ typedef enum cs_mode { CS_MODE_THUMB = 1 << 4, ///< ARM's Thumb mode, including Thumb-2 CS_MODE_MCLASS = 1 << 5, ///< ARM's Cortex-M series CS_MODE_V8 = 1 << 6, ///< ARMv8 A32 encodings for ARM - CS_MODE_MICRO = 1 << 4, ///< MicroMips mode (MIPS) - CS_MODE_MIPS3 = 1 << 5, ///< Mips III ISA - CS_MODE_MIPS32R6 = 1 << 6, ///< Mips32r6 ISA - CS_MODE_MIPS2 = 1 << 7, ///< Mips II ISA CS_MODE_V9 = 1 << 4, ///< SparcV9 mode (Sparc) CS_MODE_QPX = 1 << 4, ///< Quad Processing eXtensions mode (PPC) CS_MODE_SPE = 1 << 5, ///< Signal Processing Engine mode (PPC) @@ -198,9 +194,33 @@ typedef enum cs_mode { CS_MODE_M68K_030 = 1 << 4, ///< M68K 68030 mode CS_MODE_M68K_040 = 1 << 5, ///< M68K 68040 mode CS_MODE_M68K_060 = 1 << 6, ///< M68K 68060 mode - CS_MODE_BIG_ENDIAN = 1U << 31, ///< big-endian mode - CS_MODE_MIPS32 = CS_MODE_32, ///< Mips32 ISA (Mips) - CS_MODE_MIPS64 = CS_MODE_64, ///< Mips64 ISA (Mips) + CS_MODE_BIG_ENDIAN = 1U << 31, ///< big-endian mode + CS_MODE_MIPS16 = CS_MODE_16, ///< Generic mips16 + CS_MODE_MIPS32 = CS_MODE_32, ///< Generic mips32 + CS_MODE_MIPS64 = CS_MODE_64, ///< Generic mips64 + CS_MODE_MICRO = 1 << 4, ///< microMips + CS_MODE_MIPS1 = 1 << 5, ///< Mips I ISA Support + CS_MODE_MIPS2 = 1 << 6, ///< Mips II ISA Support + CS_MODE_MIPS32R2 = 1 << 7, ///< Mips32r2 ISA Support + CS_MODE_MIPS32R3 = 1 << 8, ///< Mips32r3 ISA Support + CS_MODE_MIPS32R5 = 1 << 9, ///< Mips32r5 ISA Support + CS_MODE_MIPS32R6 = 1 << 10, ///< Mips32r6 ISA Support + CS_MODE_MIPS3 = 1 << 11, ///< MIPS III ISA Support + CS_MODE_MIPS4 = 1 << 12, ///< MIPS IV ISA Support + CS_MODE_MIPS5 = 1 << 13, ///< MIPS V ISA Support + CS_MODE_MIPS64R2 = 1 << 14, ///< Mips64r2 ISA Support + CS_MODE_MIPS64R3 = 1 << 15, ///< Mips64r3 ISA Support + CS_MODE_MIPS64R5 = 1 << 16, ///< Mips64r5 ISA Support + CS_MODE_MIPS64R6 = 1 << 17, ///< Mips64r6 ISA Support + CS_MODE_OCTEON = 1 << 18, ///< Octeon cnMIPS Support + CS_MODE_OCTEONP = 1 << 19, ///< Octeon+ cnMIPS Support + CS_MODE_NANOMIPS = 1 << 20, ///< Generic nanomips + CS_MODE_NMS1 = ((1 << 21) | CS_MODE_NANOMIPS), ///< nanoMips NMS1 + CS_MODE_I7200 = ((1 << 22) | CS_MODE_NANOMIPS), ///< nanoMips I7200 + CS_MODE_MIPS_NOFLOAT = 1 << 23, ///< Disable floating points ops + CS_MODE_MIPS_PTR64 = 1 << 24, ///< Mips pointers are 64-bit + CS_MODE_MICRO32R3 = (CS_MODE_MICRO | CS_MODE_MIPS32R3), ///< microMips32r3 + CS_MODE_MICRO32R6 = (CS_MODE_MICRO | CS_MODE_MIPS32R6), ///< microMips32r6 CS_MODE_M680X_6301 = 1 << 1, ///< M680X Hitachi 6301,6303 mode CS_MODE_M680X_6309 = 1 << 2, ///< M680X Hitachi 6309 mode CS_MODE_M680X_6800 = 1 << 3, ///< M680X Motorola 6800,6802 mode @@ -210,7 +230,7 @@ typedef enum cs_mode { CS_MODE_M680X_6809 = 1 << 7, ///< M680X Motorola 6809 mode CS_MODE_M680X_6811 = 1 << 8, ///< M680X Motorola/Freescale/NXP 68HC11 mode CS_MODE_M680X_CPU12 = 1 << 9, ///< M680X Motorola/Freescale/NXP CPU12 - ///< used on M68HC12/HCS12 + ///< used on M68HC12/HCS12 CS_MODE_M680X_HCS08 = 1 << 10, ///< M680X Freescale/NXP HCS08 mode CS_MODE_BPF_CLASSIC = 0, ///< Classic BPF mode (default) CS_MODE_BPF_EXTENDED = 1 << 0, ///< Extended BPF mode @@ -299,6 +319,7 @@ typedef enum cs_opt_value { CS_OPT_SYNTAX_MOTOROLA = 1 << 6, ///< MOS65XX use $ as hex prefix CS_OPT_SYNTAX_CS_REG_ALIAS = 1 << 7, ///< Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.) CS_OPT_SYNTAX_PERCENT = 1 << 8, ///< Prints the % in front of PPC registers. + CS_OPT_SYNTAX_NO_DOLLAR = 1 << 9, ///< Does not print the $ in front of Mips registers. CS_OPT_DETAIL_REAL = 1 << 1, ///< If enabled, always sets the real instruction detail. Even if the instruction is an alias. } cs_opt_value; @@ -401,7 +422,7 @@ typedef struct cs_opt_skipdata { #define MAX_IMPL_W_REGS 47 #define MAX_IMPL_R_REGS 20 -#define MAX_NUM_GROUPS 8 +#define MAX_NUM_GROUPS 16 /// NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON /// Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH)) diff --git a/include/capstone/cs_operand.h b/include/capstone/cs_operand.h index 17ec7c72e1..3c3f8a9cc7 100644 --- a/include/capstone/cs_operand.h +++ b/include/capstone/cs_operand.h @@ -25,8 +25,7 @@ typedef enum cs_op_type { CS_OP_RESERVED_15 = 15, CS_OP_SPECIAL = 0x10, ///< Special operands from archs CS_OP_BOUND = 0x40, ///< Operand is associated with a previous operand. Used by AArch64 for SME operands. - CS_OP_MEM = - 0x80, ///< Memory operand. Can be ORed with another operand type. + CS_OP_MEM = 0x80, ///< Memory operand. Can be ORed with another operand type. CS_OP_MEM_REG = CS_OP_MEM | CS_OP_REG, ///< Memory referencing register operand. CS_OP_MEM_IMM = CS_OP_MEM | CS_OP_IMM, ///< Memory referencing immediate operand. diff --git a/include/capstone/mips.h b/include/capstone/mips.h index 339445611c..5ab203c7de 100644 --- a/include/capstone/mips.h +++ b/include/capstone/mips.h @@ -28,205 +28,648 @@ typedef enum mips_op_type { /// MIPS registers typedef enum mips_reg { - MIPS_REG_INVALID = 0, - // General purpose registers - MIPS_REG_PC, - - MIPS_REG_0, - MIPS_REG_1, - MIPS_REG_2, - MIPS_REG_3, - MIPS_REG_4, - MIPS_REG_5, - MIPS_REG_6, - MIPS_REG_7, - MIPS_REG_8, - MIPS_REG_9, - MIPS_REG_10, - MIPS_REG_11, - MIPS_REG_12, - MIPS_REG_13, - MIPS_REG_14, - MIPS_REG_15, - MIPS_REG_16, - MIPS_REG_17, - MIPS_REG_18, - MIPS_REG_19, - MIPS_REG_20, - MIPS_REG_21, - MIPS_REG_22, - MIPS_REG_23, - MIPS_REG_24, - MIPS_REG_25, - MIPS_REG_26, - MIPS_REG_27, - MIPS_REG_28, - MIPS_REG_29, - MIPS_REG_30, - MIPS_REG_31, - - // DSP registers - MIPS_REG_DSPCCOND, - MIPS_REG_DSPCARRY, - MIPS_REG_DSPEFI, - MIPS_REG_DSPOUTFLAG, - MIPS_REG_DSPOUTFLAG16_19, - MIPS_REG_DSPOUTFLAG20, - MIPS_REG_DSPOUTFLAG21, - MIPS_REG_DSPOUTFLAG22, - MIPS_REG_DSPOUTFLAG23, - MIPS_REG_DSPPOS, - MIPS_REG_DSPSCOUNT, - - // ACC registers - MIPS_REG_AC0, - MIPS_REG_AC1, - MIPS_REG_AC2, - MIPS_REG_AC3, - - // COP registers - MIPS_REG_CC0, - MIPS_REG_CC1, - MIPS_REG_CC2, - MIPS_REG_CC3, - MIPS_REG_CC4, - MIPS_REG_CC5, - MIPS_REG_CC6, - MIPS_REG_CC7, - - // FPU registers - MIPS_REG_F0, - MIPS_REG_F1, - MIPS_REG_F2, - MIPS_REG_F3, - MIPS_REG_F4, - MIPS_REG_F5, - MIPS_REG_F6, - MIPS_REG_F7, - MIPS_REG_F8, - MIPS_REG_F9, - MIPS_REG_F10, - MIPS_REG_F11, - MIPS_REG_F12, - MIPS_REG_F13, - MIPS_REG_F14, - MIPS_REG_F15, - MIPS_REG_F16, - MIPS_REG_F17, - MIPS_REG_F18, - MIPS_REG_F19, - MIPS_REG_F20, - MIPS_REG_F21, - MIPS_REG_F22, - MIPS_REG_F23, - MIPS_REG_F24, - MIPS_REG_F25, - MIPS_REG_F26, - MIPS_REG_F27, - MIPS_REG_F28, - MIPS_REG_F29, - MIPS_REG_F30, - MIPS_REG_F31, - - MIPS_REG_FCC0, - MIPS_REG_FCC1, - MIPS_REG_FCC2, - MIPS_REG_FCC3, - MIPS_REG_FCC4, - MIPS_REG_FCC5, - MIPS_REG_FCC6, - MIPS_REG_FCC7, - - // AFPR128 - MIPS_REG_W0, - MIPS_REG_W1, - MIPS_REG_W2, - MIPS_REG_W3, - MIPS_REG_W4, - MIPS_REG_W5, - MIPS_REG_W6, - MIPS_REG_W7, - MIPS_REG_W8, - MIPS_REG_W9, - MIPS_REG_W10, - MIPS_REG_W11, - MIPS_REG_W12, - MIPS_REG_W13, - MIPS_REG_W14, - MIPS_REG_W15, - MIPS_REG_W16, - MIPS_REG_W17, - MIPS_REG_W18, - MIPS_REG_W19, - MIPS_REG_W20, - MIPS_REG_W21, - MIPS_REG_W22, - MIPS_REG_W23, - MIPS_REG_W24, - MIPS_REG_W25, - MIPS_REG_W26, - MIPS_REG_W27, - MIPS_REG_W28, - MIPS_REG_W29, - MIPS_REG_W30, - MIPS_REG_W31, - - MIPS_REG_HI, - MIPS_REG_LO, - - MIPS_REG_P0, - MIPS_REG_P1, - MIPS_REG_P2, - - MIPS_REG_MPL0, - MIPS_REG_MPL1, - MIPS_REG_MPL2, - - MIPS_REG_ENDING, // <-- mark the end of the list or registers + // generated content begin + // clang-format off - // alias registers - MIPS_REG_ZERO = MIPS_REG_0, - MIPS_REG_AT = MIPS_REG_1, - MIPS_REG_V0 = MIPS_REG_2, - MIPS_REG_V1 = MIPS_REG_3, - MIPS_REG_A0 = MIPS_REG_4, - MIPS_REG_A1 = MIPS_REG_5, - MIPS_REG_A2 = MIPS_REG_6, - MIPS_REG_A3 = MIPS_REG_7, - MIPS_REG_T0 = MIPS_REG_8, - MIPS_REG_T1 = MIPS_REG_9, - MIPS_REG_T2 = MIPS_REG_10, - MIPS_REG_T3 = MIPS_REG_11, - MIPS_REG_T4 = MIPS_REG_12, - MIPS_REG_T5 = MIPS_REG_13, - MIPS_REG_T6 = MIPS_REG_14, - MIPS_REG_T7 = MIPS_REG_15, - MIPS_REG_S0 = MIPS_REG_16, - MIPS_REG_S1 = MIPS_REG_17, - MIPS_REG_S2 = MIPS_REG_18, - MIPS_REG_S3 = MIPS_REG_19, - MIPS_REG_S4 = MIPS_REG_20, - MIPS_REG_S5 = MIPS_REG_21, - MIPS_REG_S6 = MIPS_REG_22, - MIPS_REG_S7 = MIPS_REG_23, - MIPS_REG_T8 = MIPS_REG_24, - MIPS_REG_T9 = MIPS_REG_25, - MIPS_REG_K0 = MIPS_REG_26, - MIPS_REG_K1 = MIPS_REG_27, - MIPS_REG_GP = MIPS_REG_28, - MIPS_REG_SP = MIPS_REG_29, - MIPS_REG_FP = MIPS_REG_30, MIPS_REG_S8 = MIPS_REG_30, - MIPS_REG_RA = MIPS_REG_31, - - MIPS_REG_HI0 = MIPS_REG_AC0, - MIPS_REG_HI1 = MIPS_REG_AC1, - MIPS_REG_HI2 = MIPS_REG_AC2, - MIPS_REG_HI3 = MIPS_REG_AC3, + MIPS_REG_INVALID = 0, + MIPS_REG_AT = 1, + MIPS_REG_AT_NM = 2, + MIPS_REG_DSPCCOND = 3, + MIPS_REG_DSPCARRY = 4, + MIPS_REG_DSPEFI = 5, + MIPS_REG_DSPOUTFLAG = 6, + MIPS_REG_DSPPOS = 7, + MIPS_REG_DSPSCOUNT = 8, + MIPS_REG_FP = 9, + MIPS_REG_FP_NM = 10, + MIPS_REG_GP = 11, + MIPS_REG_GP_NM = 12, + MIPS_REG_MSAACCESS = 13, + MIPS_REG_MSACSR = 14, + MIPS_REG_MSAIR = 15, + MIPS_REG_MSAMAP = 16, + MIPS_REG_MSAMODIFY = 17, + MIPS_REG_MSAREQUEST = 18, + MIPS_REG_MSASAVE = 19, + MIPS_REG_MSAUNMAP = 20, + MIPS_REG_PC = 21, + MIPS_REG_RA = 22, + MIPS_REG_RA_NM = 23, + MIPS_REG_SP = 24, + MIPS_REG_SP_NM = 25, + MIPS_REG_ZERO = 26, + MIPS_REG_ZERO_NM = 27, + MIPS_REG_A0 = 28, + MIPS_REG_A1 = 29, + MIPS_REG_A2 = 30, + MIPS_REG_A3 = 31, + MIPS_REG_AC0 = 32, + MIPS_REG_AC1 = 33, + MIPS_REG_AC2 = 34, + MIPS_REG_AC3 = 35, + MIPS_REG_AT_64 = 36, + MIPS_REG_COP00 = 37, + MIPS_REG_COP01 = 38, + MIPS_REG_COP02 = 39, + MIPS_REG_COP03 = 40, + MIPS_REG_COP04 = 41, + MIPS_REG_COP05 = 42, + MIPS_REG_COP06 = 43, + MIPS_REG_COP07 = 44, + MIPS_REG_COP08 = 45, + MIPS_REG_COP09 = 46, + MIPS_REG_COP20 = 47, + MIPS_REG_COP21 = 48, + MIPS_REG_COP22 = 49, + MIPS_REG_COP23 = 50, + MIPS_REG_COP24 = 51, + MIPS_REG_COP25 = 52, + MIPS_REG_COP26 = 53, + MIPS_REG_COP27 = 54, + MIPS_REG_COP28 = 55, + MIPS_REG_COP29 = 56, + MIPS_REG_COP30 = 57, + MIPS_REG_COP31 = 58, + MIPS_REG_COP32 = 59, + MIPS_REG_COP33 = 60, + MIPS_REG_COP34 = 61, + MIPS_REG_COP35 = 62, + MIPS_REG_COP36 = 63, + MIPS_REG_COP37 = 64, + MIPS_REG_COP38 = 65, + MIPS_REG_COP39 = 66, + MIPS_REG_COP010 = 67, + MIPS_REG_COP011 = 68, + MIPS_REG_COP012 = 69, + MIPS_REG_COP013 = 70, + MIPS_REG_COP014 = 71, + MIPS_REG_COP015 = 72, + MIPS_REG_COP016 = 73, + MIPS_REG_COP017 = 74, + MIPS_REG_COP018 = 75, + MIPS_REG_COP019 = 76, + MIPS_REG_COP020 = 77, + MIPS_REG_COP021 = 78, + MIPS_REG_COP022 = 79, + MIPS_REG_COP023 = 80, + MIPS_REG_COP024 = 81, + MIPS_REG_COP025 = 82, + MIPS_REG_COP026 = 83, + MIPS_REG_COP027 = 84, + MIPS_REG_COP028 = 85, + MIPS_REG_COP029 = 86, + MIPS_REG_COP030 = 87, + MIPS_REG_COP031 = 88, + MIPS_REG_COP210 = 89, + MIPS_REG_COP211 = 90, + MIPS_REG_COP212 = 91, + MIPS_REG_COP213 = 92, + MIPS_REG_COP214 = 93, + MIPS_REG_COP215 = 94, + MIPS_REG_COP216 = 95, + MIPS_REG_COP217 = 96, + MIPS_REG_COP218 = 97, + MIPS_REG_COP219 = 98, + MIPS_REG_COP220 = 99, + MIPS_REG_COP221 = 100, + MIPS_REG_COP222 = 101, + MIPS_REG_COP223 = 102, + MIPS_REG_COP224 = 103, + MIPS_REG_COP225 = 104, + MIPS_REG_COP226 = 105, + MIPS_REG_COP227 = 106, + MIPS_REG_COP228 = 107, + MIPS_REG_COP229 = 108, + MIPS_REG_COP230 = 109, + MIPS_REG_COP231 = 110, + MIPS_REG_COP310 = 111, + MIPS_REG_COP311 = 112, + MIPS_REG_COP312 = 113, + MIPS_REG_COP313 = 114, + MIPS_REG_COP314 = 115, + MIPS_REG_COP315 = 116, + MIPS_REG_COP316 = 117, + MIPS_REG_COP317 = 118, + MIPS_REG_COP318 = 119, + MIPS_REG_COP319 = 120, + MIPS_REG_COP320 = 121, + MIPS_REG_COP321 = 122, + MIPS_REG_COP322 = 123, + MIPS_REG_COP323 = 124, + MIPS_REG_COP324 = 125, + MIPS_REG_COP325 = 126, + MIPS_REG_COP326 = 127, + MIPS_REG_COP327 = 128, + MIPS_REG_COP328 = 129, + MIPS_REG_COP329 = 130, + MIPS_REG_COP330 = 131, + MIPS_REG_COP331 = 132, + MIPS_REG_D0 = 133, + MIPS_REG_D1 = 134, + MIPS_REG_D2 = 135, + MIPS_REG_D3 = 136, + MIPS_REG_D4 = 137, + MIPS_REG_D5 = 138, + MIPS_REG_D6 = 139, + MIPS_REG_D7 = 140, + MIPS_REG_D8 = 141, + MIPS_REG_D9 = 142, + MIPS_REG_D10 = 143, + MIPS_REG_D11 = 144, + MIPS_REG_D12 = 145, + MIPS_REG_D13 = 146, + MIPS_REG_D14 = 147, + MIPS_REG_D15 = 148, + MIPS_REG_DSPOUTFLAG20 = 149, + MIPS_REG_DSPOUTFLAG21 = 150, + MIPS_REG_DSPOUTFLAG22 = 151, + MIPS_REG_DSPOUTFLAG23 = 152, + MIPS_REG_F0 = 153, + MIPS_REG_F1 = 154, + MIPS_REG_F2 = 155, + MIPS_REG_F3 = 156, + MIPS_REG_F4 = 157, + MIPS_REG_F5 = 158, + MIPS_REG_F6 = 159, + MIPS_REG_F7 = 160, + MIPS_REG_F8 = 161, + MIPS_REG_F9 = 162, + MIPS_REG_F10 = 163, + MIPS_REG_F11 = 164, + MIPS_REG_F12 = 165, + MIPS_REG_F13 = 166, + MIPS_REG_F14 = 167, + MIPS_REG_F15 = 168, + MIPS_REG_F16 = 169, + MIPS_REG_F17 = 170, + MIPS_REG_F18 = 171, + MIPS_REG_F19 = 172, + MIPS_REG_F20 = 173, + MIPS_REG_F21 = 174, + MIPS_REG_F22 = 175, + MIPS_REG_F23 = 176, + MIPS_REG_F24 = 177, + MIPS_REG_F25 = 178, + MIPS_REG_F26 = 179, + MIPS_REG_F27 = 180, + MIPS_REG_F28 = 181, + MIPS_REG_F29 = 182, + MIPS_REG_F30 = 183, + MIPS_REG_F31 = 184, + MIPS_REG_FCC0 = 185, + MIPS_REG_FCC1 = 186, + MIPS_REG_FCC2 = 187, + MIPS_REG_FCC3 = 188, + MIPS_REG_FCC4 = 189, + MIPS_REG_FCC5 = 190, + MIPS_REG_FCC6 = 191, + MIPS_REG_FCC7 = 192, + MIPS_REG_FCR0 = 193, + MIPS_REG_FCR1 = 194, + MIPS_REG_FCR2 = 195, + MIPS_REG_FCR3 = 196, + MIPS_REG_FCR4 = 197, + MIPS_REG_FCR5 = 198, + MIPS_REG_FCR6 = 199, + MIPS_REG_FCR7 = 200, + MIPS_REG_FCR8 = 201, + MIPS_REG_FCR9 = 202, + MIPS_REG_FCR10 = 203, + MIPS_REG_FCR11 = 204, + MIPS_REG_FCR12 = 205, + MIPS_REG_FCR13 = 206, + MIPS_REG_FCR14 = 207, + MIPS_REG_FCR15 = 208, + MIPS_REG_FCR16 = 209, + MIPS_REG_FCR17 = 210, + MIPS_REG_FCR18 = 211, + MIPS_REG_FCR19 = 212, + MIPS_REG_FCR20 = 213, + MIPS_REG_FCR21 = 214, + MIPS_REG_FCR22 = 215, + MIPS_REG_FCR23 = 216, + MIPS_REG_FCR24 = 217, + MIPS_REG_FCR25 = 218, + MIPS_REG_FCR26 = 219, + MIPS_REG_FCR27 = 220, + MIPS_REG_FCR28 = 221, + MIPS_REG_FCR29 = 222, + MIPS_REG_FCR30 = 223, + MIPS_REG_FCR31 = 224, + MIPS_REG_FP_64 = 225, + MIPS_REG_F_HI0 = 226, + MIPS_REG_F_HI1 = 227, + MIPS_REG_F_HI2 = 228, + MIPS_REG_F_HI3 = 229, + MIPS_REG_F_HI4 = 230, + MIPS_REG_F_HI5 = 231, + MIPS_REG_F_HI6 = 232, + MIPS_REG_F_HI7 = 233, + MIPS_REG_F_HI8 = 234, + MIPS_REG_F_HI9 = 235, + MIPS_REG_F_HI10 = 236, + MIPS_REG_F_HI11 = 237, + MIPS_REG_F_HI12 = 238, + MIPS_REG_F_HI13 = 239, + MIPS_REG_F_HI14 = 240, + MIPS_REG_F_HI15 = 241, + MIPS_REG_F_HI16 = 242, + MIPS_REG_F_HI17 = 243, + MIPS_REG_F_HI18 = 244, + MIPS_REG_F_HI19 = 245, + MIPS_REG_F_HI20 = 246, + MIPS_REG_F_HI21 = 247, + MIPS_REG_F_HI22 = 248, + MIPS_REG_F_HI23 = 249, + MIPS_REG_F_HI24 = 250, + MIPS_REG_F_HI25 = 251, + MIPS_REG_F_HI26 = 252, + MIPS_REG_F_HI27 = 253, + MIPS_REG_F_HI28 = 254, + MIPS_REG_F_HI29 = 255, + MIPS_REG_F_HI30 = 256, + MIPS_REG_F_HI31 = 257, + MIPS_REG_GP_64 = 258, + MIPS_REG_HI0 = 259, + MIPS_REG_HI1 = 260, + MIPS_REG_HI2 = 261, + MIPS_REG_HI3 = 262, + MIPS_REG_HWR0 = 263, + MIPS_REG_HWR1 = 264, + MIPS_REG_HWR2 = 265, + MIPS_REG_HWR3 = 266, + MIPS_REG_HWR4 = 267, + MIPS_REG_HWR5 = 268, + MIPS_REG_HWR6 = 269, + MIPS_REG_HWR7 = 270, + MIPS_REG_HWR8 = 271, + MIPS_REG_HWR9 = 272, + MIPS_REG_HWR10 = 273, + MIPS_REG_HWR11 = 274, + MIPS_REG_HWR12 = 275, + MIPS_REG_HWR13 = 276, + MIPS_REG_HWR14 = 277, + MIPS_REG_HWR15 = 278, + MIPS_REG_HWR16 = 279, + MIPS_REG_HWR17 = 280, + MIPS_REG_HWR18 = 281, + MIPS_REG_HWR19 = 282, + MIPS_REG_HWR20 = 283, + MIPS_REG_HWR21 = 284, + MIPS_REG_HWR22 = 285, + MIPS_REG_HWR23 = 286, + MIPS_REG_HWR24 = 287, + MIPS_REG_HWR25 = 288, + MIPS_REG_HWR26 = 289, + MIPS_REG_HWR27 = 290, + MIPS_REG_HWR28 = 291, + MIPS_REG_HWR29 = 292, + MIPS_REG_HWR30 = 293, + MIPS_REG_HWR31 = 294, + MIPS_REG_K0 = 295, + MIPS_REG_K1 = 296, + MIPS_REG_LO0 = 297, + MIPS_REG_LO1 = 298, + MIPS_REG_LO2 = 299, + MIPS_REG_LO3 = 300, + MIPS_REG_MPL0 = 301, + MIPS_REG_MPL1 = 302, + MIPS_REG_MPL2 = 303, + MIPS_REG_MSA8 = 304, + MIPS_REG_MSA9 = 305, + MIPS_REG_MSA10 = 306, + MIPS_REG_MSA11 = 307, + MIPS_REG_MSA12 = 308, + MIPS_REG_MSA13 = 309, + MIPS_REG_MSA14 = 310, + MIPS_REG_MSA15 = 311, + MIPS_REG_MSA16 = 312, + MIPS_REG_MSA17 = 313, + MIPS_REG_MSA18 = 314, + MIPS_REG_MSA19 = 315, + MIPS_REG_MSA20 = 316, + MIPS_REG_MSA21 = 317, + MIPS_REG_MSA22 = 318, + MIPS_REG_MSA23 = 319, + MIPS_REG_MSA24 = 320, + MIPS_REG_MSA25 = 321, + MIPS_REG_MSA26 = 322, + MIPS_REG_MSA27 = 323, + MIPS_REG_MSA28 = 324, + MIPS_REG_MSA29 = 325, + MIPS_REG_MSA30 = 326, + MIPS_REG_MSA31 = 327, + MIPS_REG_P0 = 328, + MIPS_REG_P1 = 329, + MIPS_REG_P2 = 330, + MIPS_REG_RA_64 = 331, + MIPS_REG_S0 = 332, + MIPS_REG_S1 = 333, + MIPS_REG_S2 = 334, + MIPS_REG_S3 = 335, + MIPS_REG_S4 = 336, + MIPS_REG_S5 = 337, + MIPS_REG_S6 = 338, + MIPS_REG_S7 = 339, + MIPS_REG_SP_64 = 340, + MIPS_REG_T0 = 341, + MIPS_REG_T1 = 342, + MIPS_REG_T2 = 343, + MIPS_REG_T3 = 344, + MIPS_REG_T4 = 345, + MIPS_REG_T5 = 346, + MIPS_REG_T6 = 347, + MIPS_REG_T7 = 348, + MIPS_REG_T8 = 349, + MIPS_REG_T9 = 350, + MIPS_REG_V0 = 351, + MIPS_REG_V1 = 352, + MIPS_REG_W0 = 353, + MIPS_REG_W1 = 354, + MIPS_REG_W2 = 355, + MIPS_REG_W3 = 356, + MIPS_REG_W4 = 357, + MIPS_REG_W5 = 358, + MIPS_REG_W6 = 359, + MIPS_REG_W7 = 360, + MIPS_REG_W8 = 361, + MIPS_REG_W9 = 362, + MIPS_REG_W10 = 363, + MIPS_REG_W11 = 364, + MIPS_REG_W12 = 365, + MIPS_REG_W13 = 366, + MIPS_REG_W14 = 367, + MIPS_REG_W15 = 368, + MIPS_REG_W16 = 369, + MIPS_REG_W17 = 370, + MIPS_REG_W18 = 371, + MIPS_REG_W19 = 372, + MIPS_REG_W20 = 373, + MIPS_REG_W21 = 374, + MIPS_REG_W22 = 375, + MIPS_REG_W23 = 376, + MIPS_REG_W24 = 377, + MIPS_REG_W25 = 378, + MIPS_REG_W26 = 379, + MIPS_REG_W27 = 380, + MIPS_REG_W28 = 381, + MIPS_REG_W29 = 382, + MIPS_REG_W30 = 383, + MIPS_REG_W31 = 384, + MIPS_REG_ZERO_64 = 385, + MIPS_REG_A0_NM = 386, + MIPS_REG_A1_NM = 387, + MIPS_REG_A2_NM = 388, + MIPS_REG_A3_NM = 389, + MIPS_REG_A4_NM = 390, + MIPS_REG_A5_NM = 391, + MIPS_REG_A6_NM = 392, + MIPS_REG_A7_NM = 393, + MIPS_REG_COP0SEL_BADINST = 394, + MIPS_REG_COP0SEL_BADINSTRP = 395, + MIPS_REG_COP0SEL_BADINSTRX = 396, + MIPS_REG_COP0SEL_BADVADDR = 397, + MIPS_REG_COP0SEL_BEVVA = 398, + MIPS_REG_COP0SEL_CACHEERR = 399, + MIPS_REG_COP0SEL_CAUSE = 400, + MIPS_REG_COP0SEL_CDMMBASE = 401, + MIPS_REG_COP0SEL_CMGCRBASE = 402, + MIPS_REG_COP0SEL_COMPARE = 403, + MIPS_REG_COP0SEL_CONFIG = 404, + MIPS_REG_COP0SEL_CONTEXT = 405, + MIPS_REG_COP0SEL_CONTEXTCONFIG = 406, + MIPS_REG_COP0SEL_COUNT = 407, + MIPS_REG_COP0SEL_DDATAHI = 408, + MIPS_REG_COP0SEL_DDATALO = 409, + MIPS_REG_COP0SEL_DEBUG = 410, + MIPS_REG_COP0SEL_DEBUGCONTEXTID = 411, + MIPS_REG_COP0SEL_DEPC = 412, + MIPS_REG_COP0SEL_DESAVE = 413, + MIPS_REG_COP0SEL_DTAGHI = 414, + MIPS_REG_COP0SEL_DTAGLO = 415, + MIPS_REG_COP0SEL_EBASE = 416, + MIPS_REG_COP0SEL_ENTRYHI = 417, + MIPS_REG_COP0SEL_EPC = 418, + MIPS_REG_COP0SEL_ERRCTL = 419, + MIPS_REG_COP0SEL_ERROREPC = 420, + MIPS_REG_COP0SEL_GLOBALNUMBER = 421, + MIPS_REG_COP0SEL_GTOFFSET = 422, + MIPS_REG_COP0SEL_HWRENA = 423, + MIPS_REG_COP0SEL_IDATAHI = 424, + MIPS_REG_COP0SEL_IDATALO = 425, + MIPS_REG_COP0SEL_INDEX = 426, + MIPS_REG_COP0SEL_INTCTL = 427, + MIPS_REG_COP0SEL_ITAGHI = 428, + MIPS_REG_COP0SEL_ITAGLO = 429, + MIPS_REG_COP0SEL_LLADDR = 430, + MIPS_REG_COP0SEL_MAAR = 431, + MIPS_REG_COP0SEL_MAARI = 432, + MIPS_REG_COP0SEL_MEMORYMAPID = 433, + MIPS_REG_COP0SEL_MVPCONTROL = 434, + MIPS_REG_COP0SEL_NESTEDEPC = 435, + MIPS_REG_COP0SEL_NESTEDEXC = 436, + MIPS_REG_COP0SEL_PAGEGRAIN = 437, + MIPS_REG_COP0SEL_PAGEMASK = 438, + MIPS_REG_COP0SEL_PRID = 439, + MIPS_REG_COP0SEL_PWBASE = 440, + MIPS_REG_COP0SEL_PWCTL = 441, + MIPS_REG_COP0SEL_PWFIELD = 442, + MIPS_REG_COP0SEL_PWSIZE = 443, + MIPS_REG_COP0SEL_RANDOM = 444, + MIPS_REG_COP0SEL_SRSCTL = 445, + MIPS_REG_COP0SEL_SRSMAP = 446, + MIPS_REG_COP0SEL_STATUS = 447, + MIPS_REG_COP0SEL_TCBIND = 448, + MIPS_REG_COP0SEL_TCCONTEXT = 449, + MIPS_REG_COP0SEL_TCHALT = 450, + MIPS_REG_COP0SEL_TCOPT = 451, + MIPS_REG_COP0SEL_TCRESTART = 452, + MIPS_REG_COP0SEL_TCSCHEDULE = 453, + MIPS_REG_COP0SEL_TCSCHEFBACK = 454, + MIPS_REG_COP0SEL_TCSTATUS = 455, + MIPS_REG_COP0SEL_TRACECONTROL = 456, + MIPS_REG_COP0SEL_TRACEDBPC = 457, + MIPS_REG_COP0SEL_TRACEIBPC = 458, + MIPS_REG_COP0SEL_USERLOCAL = 459, + MIPS_REG_COP0SEL_VIEW_IPL = 460, + MIPS_REG_COP0SEL_VIEW_RIPL = 461, + MIPS_REG_COP0SEL_VPCONTROL = 462, + MIPS_REG_COP0SEL_VPECONTROL = 463, + MIPS_REG_COP0SEL_VPEOPT = 464, + MIPS_REG_COP0SEL_VPESCHEDULE = 465, + MIPS_REG_COP0SEL_VPESCHEFBACK = 466, + MIPS_REG_COP0SEL_WIRED = 467, + MIPS_REG_COP0SEL_XCONTEXT = 468, + MIPS_REG_COP0SEL_XCONTEXTCONFIG = 469, + MIPS_REG_COP0SEL_YQMASK = 470, + MIPS_REG_K0_NM = 471, + MIPS_REG_K1_NM = 472, + MIPS_REG_S0_NM = 473, + MIPS_REG_S1_NM = 474, + MIPS_REG_S2_NM = 475, + MIPS_REG_S3_NM = 476, + MIPS_REG_S4_NM = 477, + MIPS_REG_S5_NM = 478, + MIPS_REG_S6_NM = 479, + MIPS_REG_S7_NM = 480, + MIPS_REG_T0_NM = 481, + MIPS_REG_T1_NM = 482, + MIPS_REG_T2_NM = 483, + MIPS_REG_T3_NM = 484, + MIPS_REG_T4_NM = 485, + MIPS_REG_T5_NM = 486, + MIPS_REG_T8_NM = 487, + MIPS_REG_T9_NM = 488, + MIPS_REG_A0_64 = 489, + MIPS_REG_A1_64 = 490, + MIPS_REG_A2_64 = 491, + MIPS_REG_A3_64 = 492, + MIPS_REG_AC0_64 = 493, + MIPS_REG_COP0SEL_CONFIG1 = 494, + MIPS_REG_COP0SEL_CONFIG2 = 495, + MIPS_REG_COP0SEL_CONFIG3 = 496, + MIPS_REG_COP0SEL_CONFIG4 = 497, + MIPS_REG_COP0SEL_CONFIG5 = 498, + MIPS_REG_COP0SEL_DEBUG2 = 499, + MIPS_REG_COP0SEL_ENTRYLO0 = 500, + MIPS_REG_COP0SEL_ENTRYLO1 = 501, + MIPS_REG_COP0SEL_GUESTCTL0 = 502, + MIPS_REG_COP0SEL_GUESTCTL1 = 503, + MIPS_REG_COP0SEL_GUESTCTL2 = 504, + MIPS_REG_COP0SEL_GUESTCTL3 = 505, + MIPS_REG_COP0SEL_KSCRATCH1 = 506, + MIPS_REG_COP0SEL_KSCRATCH2 = 507, + MIPS_REG_COP0SEL_KSCRATCH3 = 508, + MIPS_REG_COP0SEL_KSCRATCH4 = 509, + MIPS_REG_COP0SEL_KSCRATCH5 = 510, + MIPS_REG_COP0SEL_KSCRATCH6 = 511, + MIPS_REG_COP0SEL_MVPCONF0 = 512, + MIPS_REG_COP0SEL_MVPCONF1 = 513, + MIPS_REG_COP0SEL_PERFCNT0 = 514, + MIPS_REG_COP0SEL_PERFCNT1 = 515, + MIPS_REG_COP0SEL_PERFCNT2 = 516, + MIPS_REG_COP0SEL_PERFCNT3 = 517, + MIPS_REG_COP0SEL_PERFCNT4 = 518, + MIPS_REG_COP0SEL_PERFCNT5 = 519, + MIPS_REG_COP0SEL_PERFCNT6 = 520, + MIPS_REG_COP0SEL_PERFCNT7 = 521, + MIPS_REG_COP0SEL_PERFCTL0 = 522, + MIPS_REG_COP0SEL_PERFCTL1 = 523, + MIPS_REG_COP0SEL_PERFCTL2 = 524, + MIPS_REG_COP0SEL_PERFCTL3 = 525, + MIPS_REG_COP0SEL_PERFCTL4 = 526, + MIPS_REG_COP0SEL_PERFCTL5 = 527, + MIPS_REG_COP0SEL_PERFCTL6 = 528, + MIPS_REG_COP0SEL_PERFCTL7 = 529, + MIPS_REG_COP0SEL_SEGCTL0 = 530, + MIPS_REG_COP0SEL_SEGCTL1 = 531, + MIPS_REG_COP0SEL_SEGCTL2 = 532, + MIPS_REG_COP0SEL_SRSCONF0 = 533, + MIPS_REG_COP0SEL_SRSCONF1 = 534, + MIPS_REG_COP0SEL_SRSCONF2 = 535, + MIPS_REG_COP0SEL_SRSCONF3 = 536, + MIPS_REG_COP0SEL_SRSCONF4 = 537, + MIPS_REG_COP0SEL_SRSMAP2 = 538, + MIPS_REG_COP0SEL_TRACECONTROL2 = 539, + MIPS_REG_COP0SEL_TRACECONTROL3 = 540, + MIPS_REG_COP0SEL_USERTRACEDATA1 = 541, + MIPS_REG_COP0SEL_USERTRACEDATA2 = 542, + MIPS_REG_COP0SEL_VPECONF0 = 543, + MIPS_REG_COP0SEL_VPECONF1 = 544, + MIPS_REG_COP0SEL_WATCHHI0 = 545, + MIPS_REG_COP0SEL_WATCHHI1 = 546, + MIPS_REG_COP0SEL_WATCHHI2 = 547, + MIPS_REG_COP0SEL_WATCHHI3 = 548, + MIPS_REG_COP0SEL_WATCHHI4 = 549, + MIPS_REG_COP0SEL_WATCHHI5 = 550, + MIPS_REG_COP0SEL_WATCHHI6 = 551, + MIPS_REG_COP0SEL_WATCHHI7 = 552, + MIPS_REG_COP0SEL_WATCHHI8 = 553, + MIPS_REG_COP0SEL_WATCHHI9 = 554, + MIPS_REG_COP0SEL_WATCHHI10 = 555, + MIPS_REG_COP0SEL_WATCHHI11 = 556, + MIPS_REG_COP0SEL_WATCHHI12 = 557, + MIPS_REG_COP0SEL_WATCHHI13 = 558, + MIPS_REG_COP0SEL_WATCHHI14 = 559, + MIPS_REG_COP0SEL_WATCHHI15 = 560, + MIPS_REG_COP0SEL_WATCHLO0 = 561, + MIPS_REG_COP0SEL_WATCHLO1 = 562, + MIPS_REG_COP0SEL_WATCHLO2 = 563, + MIPS_REG_COP0SEL_WATCHLO3 = 564, + MIPS_REG_COP0SEL_WATCHLO4 = 565, + MIPS_REG_COP0SEL_WATCHLO5 = 566, + MIPS_REG_COP0SEL_WATCHLO6 = 567, + MIPS_REG_COP0SEL_WATCHLO7 = 568, + MIPS_REG_COP0SEL_WATCHLO8 = 569, + MIPS_REG_COP0SEL_WATCHLO9 = 570, + MIPS_REG_COP0SEL_WATCHLO10 = 571, + MIPS_REG_COP0SEL_WATCHLO11 = 572, + MIPS_REG_COP0SEL_WATCHLO12 = 573, + MIPS_REG_COP0SEL_WATCHLO13 = 574, + MIPS_REG_COP0SEL_WATCHLO14 = 575, + MIPS_REG_COP0SEL_WATCHLO15 = 576, + MIPS_REG_D0_64 = 577, + MIPS_REG_D1_64 = 578, + MIPS_REG_D2_64 = 579, + MIPS_REG_D3_64 = 580, + MIPS_REG_D4_64 = 581, + MIPS_REG_D5_64 = 582, + MIPS_REG_D6_64 = 583, + MIPS_REG_D7_64 = 584, + MIPS_REG_D8_64 = 585, + MIPS_REG_D9_64 = 586, + MIPS_REG_D10_64 = 587, + MIPS_REG_D11_64 = 588, + MIPS_REG_D12_64 = 589, + MIPS_REG_D13_64 = 590, + MIPS_REG_D14_64 = 591, + MIPS_REG_D15_64 = 592, + MIPS_REG_D16_64 = 593, + MIPS_REG_D17_64 = 594, + MIPS_REG_D18_64 = 595, + MIPS_REG_D19_64 = 596, + MIPS_REG_D20_64 = 597, + MIPS_REG_D21_64 = 598, + MIPS_REG_D22_64 = 599, + MIPS_REG_D23_64 = 600, + MIPS_REG_D24_64 = 601, + MIPS_REG_D25_64 = 602, + MIPS_REG_D26_64 = 603, + MIPS_REG_D27_64 = 604, + MIPS_REG_D28_64 = 605, + MIPS_REG_D29_64 = 606, + MIPS_REG_D30_64 = 607, + MIPS_REG_D31_64 = 608, + MIPS_REG_DSPOUTFLAG16_19 = 609, + MIPS_REG_HI0_64 = 610, + MIPS_REG_K0_64 = 611, + MIPS_REG_K1_64 = 612, + MIPS_REG_LO0_64 = 613, + MIPS_REG_S0_64 = 614, + MIPS_REG_S1_64 = 615, + MIPS_REG_S2_64 = 616, + MIPS_REG_S3_64 = 617, + MIPS_REG_S4_64 = 618, + MIPS_REG_S5_64 = 619, + MIPS_REG_S6_64 = 620, + MIPS_REG_S7_64 = 621, + MIPS_REG_T0_64 = 622, + MIPS_REG_T1_64 = 623, + MIPS_REG_T2_64 = 624, + MIPS_REG_T3_64 = 625, + MIPS_REG_T4_64 = 626, + MIPS_REG_T5_64 = 627, + MIPS_REG_T6_64 = 628, + MIPS_REG_T7_64 = 629, + MIPS_REG_T8_64 = 630, + MIPS_REG_T9_64 = 631, + MIPS_REG_V0_64 = 632, + MIPS_REG_V1_64 = 633, + MIPS_REG_COP0SEL_GUESTCTL0EXT = 634, + MIPS_REG_ENDING, // 635 - MIPS_REG_LO0 = MIPS_REG_HI0, - MIPS_REG_LO1 = MIPS_REG_HI1, - MIPS_REG_LO2 = MIPS_REG_HI2, - MIPS_REG_LO3 = MIPS_REG_HI3, + // clang-format on + // generated content end } mips_reg; /// Instruction's operand referring to memory @@ -241,9 +684,16 @@ typedef struct cs_mips_op { mips_op_type type; ///< operand type union { mips_reg reg; ///< register id for REG operand - int64_t imm; ///< immediate value for IMM operand + int64_t imm; ///< signed immediate value for IMM operand + uint64_t uimm; ///< unsigned immediate value for IMM operand mips_op_mem mem; ///< base/index/scale/disp value for MEM operand }; + bool is_reglist; ///< defines if the register is part of a list + bool is_unsigned; ///< when true, the immediate value is unsigned + + /// How is this operand accessed? (READ, WRITE or READ|WRITE) + /// NOTE: this field is irrelevant if engine is compiled in DIET mode. + uint8_t access; } cs_mips_op; /// Instruction structure @@ -256,88 +706,232 @@ typedef struct cs_mips { /// MIPS instruction typedef enum mips_insn { - MIPS_INS_INVALID = 0, + // generated content begin + // clang-format off - MIPS_INS_ABSQ_S, + MIPS_INS_INVALID, + MIPS_INS_ABS, + MIPS_INS_ALIGN, + MIPS_INS_BEQL, + MIPS_INS_BGE, + MIPS_INS_BGEL, + MIPS_INS_BGEU, + MIPS_INS_BGEUL, + MIPS_INS_BGT, + MIPS_INS_BGTL, + MIPS_INS_BGTU, + MIPS_INS_BGTUL, + MIPS_INS_BLE, + MIPS_INS_BLEL, + MIPS_INS_BLEU, + MIPS_INS_BLEUL, + MIPS_INS_BLT, + MIPS_INS_BLTL, + MIPS_INS_BLTU, + MIPS_INS_BLTUL, + MIPS_INS_BNEL, + MIPS_INS_B, + MIPS_INS_BEQ, + MIPS_INS_BNE, + MIPS_INS_CFTC1, + MIPS_INS_CTTC1, + MIPS_INS_DMUL, + MIPS_INS_DMULO, + MIPS_INS_DMULOU, + MIPS_INS_DROL, + MIPS_INS_DROR, + MIPS_INS_DDIV, + MIPS_INS_DREM, + MIPS_INS_DDIVU, + MIPS_INS_DREMU, + MIPS_INS_JAL, + MIPS_INS_LD, + MIPS_INS_LWM, + MIPS_INS_LA, + MIPS_INS_DLA, + MIPS_INS_LI, + MIPS_INS_DLI, + MIPS_INS_LI_D, + MIPS_INS_LI_S, + MIPS_INS_MFTACX, + MIPS_INS_MFTC0, + MIPS_INS_MFTC1, + MIPS_INS_MFTDSP, + MIPS_INS_MFTGPR, + MIPS_INS_MFTHC1, + MIPS_INS_MFTHI, + MIPS_INS_MFTLO, + MIPS_INS_MTTACX, + MIPS_INS_MTTC0, + MIPS_INS_MTTC1, + MIPS_INS_MTTDSP, + MIPS_INS_MTTGPR, + MIPS_INS_MTTHC1, + MIPS_INS_MTTHI, + MIPS_INS_MTTLO, + MIPS_INS_MUL, + MIPS_INS_MULO, + MIPS_INS_MULOU, + MIPS_INS_NOR, + MIPS_INS_ADDIU, + MIPS_INS_ANDI, + MIPS_INS_SUBU, + MIPS_INS_TRUNC_W_D, + MIPS_INS_TRUNC_W_S, + MIPS_INS_ROL, + MIPS_INS_ROR, + MIPS_INS_S_D, + MIPS_INS_SD, + MIPS_INS_DIV, + MIPS_INS_SEQ, + MIPS_INS_SGE, + MIPS_INS_SGEU, + MIPS_INS_SGT, + MIPS_INS_SGTU, + MIPS_INS_SLE, + MIPS_INS_SLEU, + MIPS_INS_SLT, + MIPS_INS_SLTU, + MIPS_INS_SNE, + MIPS_INS_REM, + MIPS_INS_SWM, + MIPS_INS_SAA, + MIPS_INS_SAAD, + MIPS_INS_DIVU, + MIPS_INS_REMU, + MIPS_INS_ULH, + MIPS_INS_ULHU, + MIPS_INS_ULW, + MIPS_INS_USH, + MIPS_INS_USW, + MIPS_INS_ABSQ_S_PH, + MIPS_INS_ABSQ_S_QB, + MIPS_INS_ABSQ_S_W, MIPS_INS_ADD, MIPS_INS_ADDIUPC, MIPS_INS_ADDIUR1SP, MIPS_INS_ADDIUR2, MIPS_INS_ADDIUS5, MIPS_INS_ADDIUSP, - MIPS_INS_ADDQH, - MIPS_INS_ADDQH_R, - MIPS_INS_ADDQ, - MIPS_INS_ADDQ_S, + MIPS_INS_ADDQH_PH, + MIPS_INS_ADDQH_R_PH, + MIPS_INS_ADDQH_R_W, + MIPS_INS_ADDQH_W, + MIPS_INS_ADDQ_PH, + MIPS_INS_ADDQ_S_PH, + MIPS_INS_ADDQ_S_W, + MIPS_INS_ADDR_PS, MIPS_INS_ADDSC, - MIPS_INS_ADDS_A, - MIPS_INS_ADDS_S, - MIPS_INS_ADDS_U, + MIPS_INS_ADDS_A_B, + MIPS_INS_ADDS_A_D, + MIPS_INS_ADDS_A_H, + MIPS_INS_ADDS_A_W, + MIPS_INS_ADDS_S_B, + MIPS_INS_ADDS_S_D, + MIPS_INS_ADDS_S_H, + MIPS_INS_ADDS_S_W, + MIPS_INS_ADDS_U_B, + MIPS_INS_ADDS_U_D, + MIPS_INS_ADDS_U_H, + MIPS_INS_ADDS_U_W, MIPS_INS_ADDU16, - MIPS_INS_ADDUH, - MIPS_INS_ADDUH_R, + MIPS_INS_ADDUH_QB, + MIPS_INS_ADDUH_R_QB, MIPS_INS_ADDU, - MIPS_INS_ADDU_S, - MIPS_INS_ADDVI, - MIPS_INS_ADDV, + MIPS_INS_ADDU_PH, + MIPS_INS_ADDU_QB, + MIPS_INS_ADDU_S_PH, + MIPS_INS_ADDU_S_QB, + MIPS_INS_ADDVI_B, + MIPS_INS_ADDVI_D, + MIPS_INS_ADDVI_H, + MIPS_INS_ADDVI_W, + MIPS_INS_ADDV_B, + MIPS_INS_ADDV_D, + MIPS_INS_ADDV_H, + MIPS_INS_ADDV_W, MIPS_INS_ADDWC, - MIPS_INS_ADD_A, + MIPS_INS_ADD_A_B, + MIPS_INS_ADD_A_D, + MIPS_INS_ADD_A_H, + MIPS_INS_ADD_A_W, MIPS_INS_ADDI, - MIPS_INS_ADDIU, - MIPS_INS_ALIGN, MIPS_INS_ALUIPC, MIPS_INS_AND, MIPS_INS_AND16, MIPS_INS_ANDI16, - MIPS_INS_ANDI, + MIPS_INS_ANDI_B, + MIPS_INS_AND_V, MIPS_INS_APPEND, - MIPS_INS_ASUB_S, - MIPS_INS_ASUB_U, + MIPS_INS_ASUB_S_B, + MIPS_INS_ASUB_S_D, + MIPS_INS_ASUB_S_H, + MIPS_INS_ASUB_S_W, + MIPS_INS_ASUB_U_B, + MIPS_INS_ASUB_U_D, + MIPS_INS_ASUB_U_H, + MIPS_INS_ASUB_U_W, MIPS_INS_AUI, MIPS_INS_AUIPC, - MIPS_INS_AVER_S, - MIPS_INS_AVER_U, - MIPS_INS_AVE_S, - MIPS_INS_AVE_U, + MIPS_INS_AVER_S_B, + MIPS_INS_AVER_S_D, + MIPS_INS_AVER_S_H, + MIPS_INS_AVER_S_W, + MIPS_INS_AVER_U_B, + MIPS_INS_AVER_U_D, + MIPS_INS_AVER_U_H, + MIPS_INS_AVER_U_W, + MIPS_INS_AVE_S_B, + MIPS_INS_AVE_S_D, + MIPS_INS_AVE_S_H, + MIPS_INS_AVE_S_W, + MIPS_INS_AVE_U_B, + MIPS_INS_AVE_U_D, + MIPS_INS_AVE_U_H, + MIPS_INS_AVE_U_W, MIPS_INS_B16, MIPS_INS_BADDU, MIPS_INS_BAL, MIPS_INS_BALC, MIPS_INS_BALIGN, + MIPS_INS_BALRSC, + MIPS_INS_BBEQZC, MIPS_INS_BBIT0, MIPS_INS_BBIT032, MIPS_INS_BBIT1, MIPS_INS_BBIT132, + MIPS_INS_BBNEZC, MIPS_INS_BC, - MIPS_INS_BC0F, - MIPS_INS_BC0FL, - MIPS_INS_BC0T, - MIPS_INS_BC0TL, + MIPS_INS_BC16, MIPS_INS_BC1EQZ, + MIPS_INS_BC1EQZC, MIPS_INS_BC1F, MIPS_INS_BC1FL, MIPS_INS_BC1NEZ, + MIPS_INS_BC1NEZC, MIPS_INS_BC1T, MIPS_INS_BC1TL, MIPS_INS_BC2EQZ, - MIPS_INS_BC2F, - MIPS_INS_BC2FL, + MIPS_INS_BC2EQZC, MIPS_INS_BC2NEZ, - MIPS_INS_BC2T, - MIPS_INS_BC2TL, - MIPS_INS_BC3F, - MIPS_INS_BC3FL, - MIPS_INS_BC3T, - MIPS_INS_BC3TL, - MIPS_INS_BCLRI, - MIPS_INS_BCLR, - MIPS_INS_BEQ, + MIPS_INS_BC2NEZC, + MIPS_INS_BCLRI_B, + MIPS_INS_BCLRI_D, + MIPS_INS_BCLRI_H, + MIPS_INS_BCLRI_W, + MIPS_INS_BCLR_B, + MIPS_INS_BCLR_D, + MIPS_INS_BCLR_H, + MIPS_INS_BCLR_W, MIPS_INS_BEQC, - MIPS_INS_BEQL, + MIPS_INS_BEQIC, MIPS_INS_BEQZ16, MIPS_INS_BEQZALC, MIPS_INS_BEQZC, + MIPS_INS_BEQZC16, MIPS_INS_BGEC, + MIPS_INS_BGEIC, + MIPS_INS_BGEIUC, MIPS_INS_BGEUC, MIPS_INS_BGEZ, MIPS_INS_BGEZAL, @@ -350,17 +944,32 @@ typedef enum mips_insn { MIPS_INS_BGTZALC, MIPS_INS_BGTZC, MIPS_INS_BGTZL, - MIPS_INS_BINSLI, - MIPS_INS_BINSL, - MIPS_INS_BINSRI, - MIPS_INS_BINSR, + MIPS_INS_BINSLI_B, + MIPS_INS_BINSLI_D, + MIPS_INS_BINSLI_H, + MIPS_INS_BINSLI_W, + MIPS_INS_BINSL_B, + MIPS_INS_BINSL_D, + MIPS_INS_BINSL_H, + MIPS_INS_BINSL_W, + MIPS_INS_BINSRI_B, + MIPS_INS_BINSRI_D, + MIPS_INS_BINSRI_H, + MIPS_INS_BINSRI_W, + MIPS_INS_BINSR_B, + MIPS_INS_BINSR_D, + MIPS_INS_BINSR_H, + MIPS_INS_BINSR_W, MIPS_INS_BITREV, + MIPS_INS_BITREVW, MIPS_INS_BITSWAP, MIPS_INS_BLEZ, MIPS_INS_BLEZALC, MIPS_INS_BLEZC, MIPS_INS_BLEZL, MIPS_INS_BLTC, + MIPS_INS_BLTIC, + MIPS_INS_BLTIUC, MIPS_INS_BLTUC, MIPS_INS_BLTZ, MIPS_INS_BLTZAL, @@ -369,63 +978,221 @@ typedef enum mips_insn { MIPS_INS_BLTZALS, MIPS_INS_BLTZC, MIPS_INS_BLTZL, - MIPS_INS_BMNZI, - MIPS_INS_BMNZ, - MIPS_INS_BMZI, - MIPS_INS_BMZ, - MIPS_INS_BNE, + MIPS_INS_BMNZI_B, + MIPS_INS_BMNZ_V, + MIPS_INS_BMZI_B, + MIPS_INS_BMZ_V, MIPS_INS_BNEC, - MIPS_INS_BNEGI, - MIPS_INS_BNEG, - MIPS_INS_BNEL, + MIPS_INS_BNEGI_B, + MIPS_INS_BNEGI_D, + MIPS_INS_BNEGI_H, + MIPS_INS_BNEGI_W, + MIPS_INS_BNEG_B, + MIPS_INS_BNEG_D, + MIPS_INS_BNEG_H, + MIPS_INS_BNEG_W, + MIPS_INS_BNEIC, MIPS_INS_BNEZ16, MIPS_INS_BNEZALC, MIPS_INS_BNEZC, + MIPS_INS_BNEZC16, MIPS_INS_BNVC, - MIPS_INS_BNZ, + MIPS_INS_BNZ_B, + MIPS_INS_BNZ_D, + MIPS_INS_BNZ_H, + MIPS_INS_BNZ_V, + MIPS_INS_BNZ_W, MIPS_INS_BOVC, MIPS_INS_BPOSGE32, + MIPS_INS_BPOSGE32C, MIPS_INS_BREAK, MIPS_INS_BREAK16, - MIPS_INS_BSELI, - MIPS_INS_BSEL, - MIPS_INS_BSETI, - MIPS_INS_BSET, - MIPS_INS_BZ, + MIPS_INS_BRSC, + MIPS_INS_BSELI_B, + MIPS_INS_BSEL_V, + MIPS_INS_BSETI_B, + MIPS_INS_BSETI_D, + MIPS_INS_BSETI_H, + MIPS_INS_BSETI_W, + MIPS_INS_BSET_B, + MIPS_INS_BSET_D, + MIPS_INS_BSET_H, + MIPS_INS_BSET_W, + MIPS_INS_BYTEREVW, + MIPS_INS_BZ_B, + MIPS_INS_BZ_D, + MIPS_INS_BZ_H, + MIPS_INS_BZ_V, + MIPS_INS_BZ_W, MIPS_INS_BEQZ, - MIPS_INS_B, MIPS_INS_BNEZ, MIPS_INS_BTEQZ, MIPS_INS_BTNEZ, MIPS_INS_CACHE, - MIPS_INS_CEIL, - MIPS_INS_CEQI, - MIPS_INS_CEQ, + MIPS_INS_CACHEE, + MIPS_INS_CEIL_L_D, + MIPS_INS_CEIL_L_S, + MIPS_INS_CEIL_W_D, + MIPS_INS_CEIL_W_S, + MIPS_INS_CEQI_B, + MIPS_INS_CEQI_D, + MIPS_INS_CEQI_H, + MIPS_INS_CEQI_W, + MIPS_INS_CEQ_B, + MIPS_INS_CEQ_D, + MIPS_INS_CEQ_H, + MIPS_INS_CEQ_W, MIPS_INS_CFC1, + MIPS_INS_CFC2, MIPS_INS_CFCMSA, MIPS_INS_CINS, MIPS_INS_CINS32, - MIPS_INS_CLASS, - MIPS_INS_CLEI_S, - MIPS_INS_CLEI_U, - MIPS_INS_CLE_S, - MIPS_INS_CLE_U, + MIPS_INS_CLASS_D, + MIPS_INS_CLASS_S, + MIPS_INS_CLEI_S_B, + MIPS_INS_CLEI_S_D, + MIPS_INS_CLEI_S_H, + MIPS_INS_CLEI_S_W, + MIPS_INS_CLEI_U_B, + MIPS_INS_CLEI_U_D, + MIPS_INS_CLEI_U_H, + MIPS_INS_CLEI_U_W, + MIPS_INS_CLE_S_B, + MIPS_INS_CLE_S_D, + MIPS_INS_CLE_S_H, + MIPS_INS_CLE_S_W, + MIPS_INS_CLE_U_B, + MIPS_INS_CLE_U_D, + MIPS_INS_CLE_U_H, + MIPS_INS_CLE_U_W, MIPS_INS_CLO, - MIPS_INS_CLTI_S, - MIPS_INS_CLTI_U, - MIPS_INS_CLT_S, - MIPS_INS_CLT_U, + MIPS_INS_CLTI_S_B, + MIPS_INS_CLTI_S_D, + MIPS_INS_CLTI_S_H, + MIPS_INS_CLTI_S_W, + MIPS_INS_CLTI_U_B, + MIPS_INS_CLTI_U_D, + MIPS_INS_CLTI_U_H, + MIPS_INS_CLTI_U_W, + MIPS_INS_CLT_S_B, + MIPS_INS_CLT_S_D, + MIPS_INS_CLT_S_H, + MIPS_INS_CLT_S_W, + MIPS_INS_CLT_U_B, + MIPS_INS_CLT_U_D, + MIPS_INS_CLT_U_H, + MIPS_INS_CLT_U_W, MIPS_INS_CLZ, - MIPS_INS_CMPGDU, - MIPS_INS_CMPGU, - MIPS_INS_CMPU, - MIPS_INS_CMP, - MIPS_INS_COPY_S, - MIPS_INS_COPY_U, + MIPS_INS_CMPGDU_EQ_QB, + MIPS_INS_CMPGDU_LE_QB, + MIPS_INS_CMPGDU_LT_QB, + MIPS_INS_CMPGU_EQ_QB, + MIPS_INS_CMPGU_LE_QB, + MIPS_INS_CMPGU_LT_QB, + MIPS_INS_CMPU_EQ_QB, + MIPS_INS_CMPU_LE_QB, + MIPS_INS_CMPU_LT_QB, + MIPS_INS_CMP_AF_D, + MIPS_INS_CMP_AF_S, + MIPS_INS_CMP_EQ_D, + MIPS_INS_CMP_EQ_PH, + MIPS_INS_CMP_EQ_S, + MIPS_INS_CMP_LE_D, + MIPS_INS_CMP_LE_PH, + MIPS_INS_CMP_LE_S, + MIPS_INS_CMP_LT_D, + MIPS_INS_CMP_LT_PH, + MIPS_INS_CMP_LT_S, + MIPS_INS_CMP_SAF_D, + MIPS_INS_CMP_SAF_S, + MIPS_INS_CMP_SEQ_D, + MIPS_INS_CMP_SEQ_S, + MIPS_INS_CMP_SLE_D, + MIPS_INS_CMP_SLE_S, + MIPS_INS_CMP_SLT_D, + MIPS_INS_CMP_SLT_S, + MIPS_INS_CMP_SUEQ_D, + MIPS_INS_CMP_SUEQ_S, + MIPS_INS_CMP_SULE_D, + MIPS_INS_CMP_SULE_S, + MIPS_INS_CMP_SULT_D, + MIPS_INS_CMP_SULT_S, + MIPS_INS_CMP_SUN_D, + MIPS_INS_CMP_SUN_S, + MIPS_INS_CMP_UEQ_D, + MIPS_INS_CMP_UEQ_S, + MIPS_INS_CMP_ULE_D, + MIPS_INS_CMP_ULE_S, + MIPS_INS_CMP_ULT_D, + MIPS_INS_CMP_ULT_S, + MIPS_INS_CMP_UN_D, + MIPS_INS_CMP_UN_S, + MIPS_INS_COPY_S_B, + MIPS_INS_COPY_S_D, + MIPS_INS_COPY_S_H, + MIPS_INS_COPY_S_W, + MIPS_INS_COPY_U_B, + MIPS_INS_COPY_U_H, + MIPS_INS_COPY_U_W, + MIPS_INS_CRC32B, + MIPS_INS_CRC32CB, + MIPS_INS_CRC32CD, + MIPS_INS_CRC32CH, + MIPS_INS_CRC32CW, + MIPS_INS_CRC32D, + MIPS_INS_CRC32H, + MIPS_INS_CRC32W, MIPS_INS_CTC1, + MIPS_INS_CTC2, MIPS_INS_CTCMSA, - MIPS_INS_CVT, - MIPS_INS_C, + MIPS_INS_CVT_D_S, + MIPS_INS_CVT_D_W, + MIPS_INS_CVT_D_L, + MIPS_INS_CVT_L_D, + MIPS_INS_CVT_L_S, + MIPS_INS_CVT_PS_PW, + MIPS_INS_CVT_PS_S, + MIPS_INS_CVT_PW_PS, + MIPS_INS_CVT_S_D, + MIPS_INS_CVT_S_L, + MIPS_INS_CVT_S_PL, + MIPS_INS_CVT_S_PU, + MIPS_INS_CVT_S_W, + MIPS_INS_CVT_W_D, + MIPS_INS_CVT_W_S, + MIPS_INS_C_EQ_D, + MIPS_INS_C_EQ_S, + MIPS_INS_C_F_D, + MIPS_INS_C_F_S, + MIPS_INS_C_LE_D, + MIPS_INS_C_LE_S, + MIPS_INS_C_LT_D, + MIPS_INS_C_LT_S, + MIPS_INS_C_NGE_D, + MIPS_INS_C_NGE_S, + MIPS_INS_C_NGLE_D, + MIPS_INS_C_NGLE_S, + MIPS_INS_C_NGL_D, + MIPS_INS_C_NGL_S, + MIPS_INS_C_NGT_D, + MIPS_INS_C_NGT_S, + MIPS_INS_C_OLE_D, + MIPS_INS_C_OLE_S, + MIPS_INS_C_OLT_D, + MIPS_INS_C_OLT_S, + MIPS_INS_C_SEQ_D, + MIPS_INS_C_SEQ_S, + MIPS_INS_C_SF_D, + MIPS_INS_C_SF_S, + MIPS_INS_C_UEQ_D, + MIPS_INS_C_UEQ_S, + MIPS_INS_C_ULE_D, + MIPS_INS_C_ULE_S, + MIPS_INS_C_ULT_D, + MIPS_INS_C_ULT_S, + MIPS_INS_C_UN_D, + MIPS_INS_C_UN_S, + MIPS_INS_CMP, MIPS_INS_CMPI, MIPS_INS_DADD, MIPS_INS_DADDI, @@ -438,8 +1205,6 @@ typedef enum mips_insn { MIPS_INS_DBITSWAP, MIPS_INS_DCLO, MIPS_INS_DCLZ, - MIPS_INS_DDIV, - MIPS_INS_DDIVU, MIPS_INS_DERET, MIPS_INS_DEXT, MIPS_INS_DEXTM, @@ -448,46 +1213,66 @@ typedef enum mips_insn { MIPS_INS_DINS, MIPS_INS_DINSM, MIPS_INS_DINSU, - MIPS_INS_DIV, - MIPS_INS_DIVU, - MIPS_INS_DIV_S, - MIPS_INS_DIV_U, + MIPS_INS_DIV_S_B, + MIPS_INS_DIV_S_D, + MIPS_INS_DIV_S_H, + MIPS_INS_DIV_S_W, + MIPS_INS_DIV_U_B, + MIPS_INS_DIV_U_D, + MIPS_INS_DIV_U_H, + MIPS_INS_DIV_U_W, MIPS_INS_DLSA, MIPS_INS_DMFC0, MIPS_INS_DMFC1, MIPS_INS_DMFC2, + MIPS_INS_DMFGC0, MIPS_INS_DMOD, MIPS_INS_DMODU, + MIPS_INS_DMT, MIPS_INS_DMTC0, MIPS_INS_DMTC1, MIPS_INS_DMTC2, + MIPS_INS_DMTGC0, MIPS_INS_DMUH, MIPS_INS_DMUHU, - MIPS_INS_DMUL, MIPS_INS_DMULT, MIPS_INS_DMULTU, MIPS_INS_DMULU, - MIPS_INS_DOTP_S, - MIPS_INS_DOTP_U, - MIPS_INS_DPADD_S, - MIPS_INS_DPADD_U, - MIPS_INS_DPAQX_SA, - MIPS_INS_DPAQX_S, - MIPS_INS_DPAQ_SA, - MIPS_INS_DPAQ_S, - MIPS_INS_DPAU, - MIPS_INS_DPAX, - MIPS_INS_DPA, + MIPS_INS_DOTP_S_D, + MIPS_INS_DOTP_S_H, + MIPS_INS_DOTP_S_W, + MIPS_INS_DOTP_U_D, + MIPS_INS_DOTP_U_H, + MIPS_INS_DOTP_U_W, + MIPS_INS_DPADD_S_D, + MIPS_INS_DPADD_S_H, + MIPS_INS_DPADD_S_W, + MIPS_INS_DPADD_U_D, + MIPS_INS_DPADD_U_H, + MIPS_INS_DPADD_U_W, + MIPS_INS_DPAQX_SA_W_PH, + MIPS_INS_DPAQX_S_W_PH, + MIPS_INS_DPAQ_SA_L_W, + MIPS_INS_DPAQ_S_W_PH, + MIPS_INS_DPAU_H_QBL, + MIPS_INS_DPAU_H_QBR, + MIPS_INS_DPAX_W_PH, + MIPS_INS_DPA_W_PH, MIPS_INS_DPOP, - MIPS_INS_DPSQX_SA, - MIPS_INS_DPSQX_S, - MIPS_INS_DPSQ_SA, - MIPS_INS_DPSQ_S, - MIPS_INS_DPSUB_S, - MIPS_INS_DPSUB_U, - MIPS_INS_DPSU, - MIPS_INS_DPSX, - MIPS_INS_DPS, + MIPS_INS_DPSQX_SA_W_PH, + MIPS_INS_DPSQX_S_W_PH, + MIPS_INS_DPSQ_SA_L_W, + MIPS_INS_DPSQ_S_W_PH, + MIPS_INS_DPSUB_S_D, + MIPS_INS_DPSUB_S_H, + MIPS_INS_DPSUB_S_W, + MIPS_INS_DPSUB_U_D, + MIPS_INS_DPSUB_U_H, + MIPS_INS_DPSUB_U_W, + MIPS_INS_DPSU_H_QBL, + MIPS_INS_DPSU_H_QBR, + MIPS_INS_DPSX_W_PH, + MIPS_INS_DPS_W_PH, MIPS_INS_DROTR, MIPS_INS_DROTR32, MIPS_INS_DROTRV, @@ -504,100 +1289,209 @@ typedef enum mips_insn { MIPS_INS_DSRLV, MIPS_INS_DSUB, MIPS_INS_DSUBU, + MIPS_INS_DVP, + MIPS_INS_DVPE, MIPS_INS_EHB, MIPS_INS_EI, + MIPS_INS_EMT, MIPS_INS_ERET, + MIPS_INS_ERETNC, + MIPS_INS_EVP, + MIPS_INS_EVPE, MIPS_INS_EXT, MIPS_INS_EXTP, MIPS_INS_EXTPDP, MIPS_INS_EXTPDPV, MIPS_INS_EXTPV, - MIPS_INS_EXTRV_RS, - MIPS_INS_EXTRV_R, - MIPS_INS_EXTRV_S, - MIPS_INS_EXTRV, - MIPS_INS_EXTR_RS, - MIPS_INS_EXTR_R, - MIPS_INS_EXTR_S, - MIPS_INS_EXTR, + MIPS_INS_EXTRV_RS_W, + MIPS_INS_EXTRV_R_W, + MIPS_INS_EXTRV_S_H, + MIPS_INS_EXTRV_W, + MIPS_INS_EXTR_RS_W, + MIPS_INS_EXTR_R_W, + MIPS_INS_EXTR_S_H, + MIPS_INS_EXTR_W, MIPS_INS_EXTS, MIPS_INS_EXTS32, - MIPS_INS_ABS, - MIPS_INS_FADD, - MIPS_INS_FCAF, - MIPS_INS_FCEQ, - MIPS_INS_FCLASS, - MIPS_INS_FCLE, - MIPS_INS_FCLT, - MIPS_INS_FCNE, - MIPS_INS_FCOR, - MIPS_INS_FCUEQ, - MIPS_INS_FCULE, - MIPS_INS_FCULT, - MIPS_INS_FCUNE, - MIPS_INS_FCUN, - MIPS_INS_FDIV, - MIPS_INS_FEXDO, - MIPS_INS_FEXP2, - MIPS_INS_FEXUPL, - MIPS_INS_FEXUPR, - MIPS_INS_FFINT_S, - MIPS_INS_FFINT_U, - MIPS_INS_FFQL, - MIPS_INS_FFQR, - MIPS_INS_FILL, - MIPS_INS_FLOG2, - MIPS_INS_FLOOR, - MIPS_INS_FMADD, - MIPS_INS_FMAX_A, - MIPS_INS_FMAX, - MIPS_INS_FMIN_A, - MIPS_INS_FMIN, - MIPS_INS_MOV, - MIPS_INS_FMSUB, - MIPS_INS_FMUL, - MIPS_INS_MUL, - MIPS_INS_NEG, - MIPS_INS_FRCP, - MIPS_INS_FRINT, - MIPS_INS_FRSQRT, - MIPS_INS_FSAF, - MIPS_INS_FSEQ, - MIPS_INS_FSLE, - MIPS_INS_FSLT, - MIPS_INS_FSNE, - MIPS_INS_FSOR, - MIPS_INS_FSQRT, - MIPS_INS_SQRT, - MIPS_INS_FSUB, - MIPS_INS_SUB, - MIPS_INS_FSUEQ, - MIPS_INS_FSULE, - MIPS_INS_FSULT, - MIPS_INS_FSUNE, - MIPS_INS_FSUN, - MIPS_INS_FTINT_S, - MIPS_INS_FTINT_U, - MIPS_INS_FTQ, - MIPS_INS_FTRUNC_S, - MIPS_INS_FTRUNC_U, - MIPS_INS_HADD_S, - MIPS_INS_HADD_U, - MIPS_INS_HSUB_S, - MIPS_INS_HSUB_U, - MIPS_INS_ILVEV, - MIPS_INS_ILVL, - MIPS_INS_ILVOD, - MIPS_INS_ILVR, + MIPS_INS_EXTW, + MIPS_INS_ABS_D, + MIPS_INS_ABS_S, + MIPS_INS_FADD_D, + MIPS_INS_ADD_D, + MIPS_INS_ADD_PS, + MIPS_INS_ADD_S, + MIPS_INS_FADD_W, + MIPS_INS_FCAF_D, + MIPS_INS_FCAF_W, + MIPS_INS_FCEQ_D, + MIPS_INS_FCEQ_W, + MIPS_INS_FCLASS_D, + MIPS_INS_FCLASS_W, + MIPS_INS_FCLE_D, + MIPS_INS_FCLE_W, + MIPS_INS_FCLT_D, + MIPS_INS_FCLT_W, + MIPS_INS_FCNE_D, + MIPS_INS_FCNE_W, + MIPS_INS_FCOR_D, + MIPS_INS_FCOR_W, + MIPS_INS_FCUEQ_D, + MIPS_INS_FCUEQ_W, + MIPS_INS_FCULE_D, + MIPS_INS_FCULE_W, + MIPS_INS_FCULT_D, + MIPS_INS_FCULT_W, + MIPS_INS_FCUNE_D, + MIPS_INS_FCUNE_W, + MIPS_INS_FCUN_D, + MIPS_INS_FCUN_W, + MIPS_INS_FDIV_D, + MIPS_INS_DIV_D, + MIPS_INS_DIV_S, + MIPS_INS_FDIV_W, + MIPS_INS_FEXDO_H, + MIPS_INS_FEXDO_W, + MIPS_INS_FEXP2_D, + MIPS_INS_FEXP2_W, + MIPS_INS_FEXUPL_D, + MIPS_INS_FEXUPL_W, + MIPS_INS_FEXUPR_D, + MIPS_INS_FEXUPR_W, + MIPS_INS_FFINT_S_D, + MIPS_INS_FFINT_S_W, + MIPS_INS_FFINT_U_D, + MIPS_INS_FFINT_U_W, + MIPS_INS_FFQL_D, + MIPS_INS_FFQL_W, + MIPS_INS_FFQR_D, + MIPS_INS_FFQR_W, + MIPS_INS_FILL_B, + MIPS_INS_FILL_D, + MIPS_INS_FILL_H, + MIPS_INS_FILL_W, + MIPS_INS_FLOG2_D, + MIPS_INS_FLOG2_W, + MIPS_INS_FLOOR_L_D, + MIPS_INS_FLOOR_L_S, + MIPS_INS_FLOOR_W_D, + MIPS_INS_FLOOR_W_S, + MIPS_INS_FMADD_D, + MIPS_INS_FMADD_W, + MIPS_INS_FMAX_A_D, + MIPS_INS_FMAX_A_W, + MIPS_INS_FMAX_D, + MIPS_INS_FMAX_W, + MIPS_INS_FMIN_A_D, + MIPS_INS_FMIN_A_W, + MIPS_INS_FMIN_D, + MIPS_INS_FMIN_W, + MIPS_INS_MOV_D, + MIPS_INS_MOV_S, + MIPS_INS_FMSUB_D, + MIPS_INS_FMSUB_W, + MIPS_INS_FMUL_D, + MIPS_INS_MUL_D, + MIPS_INS_MUL_PS, + MIPS_INS_MUL_S, + MIPS_INS_FMUL_W, + MIPS_INS_NEG_D, + MIPS_INS_NEG_S, + MIPS_INS_FORK, + MIPS_INS_FRCP_D, + MIPS_INS_FRCP_W, + MIPS_INS_FRINT_D, + MIPS_INS_FRINT_W, + MIPS_INS_FRSQRT_D, + MIPS_INS_FRSQRT_W, + MIPS_INS_FSAF_D, + MIPS_INS_FSAF_W, + MIPS_INS_FSEQ_D, + MIPS_INS_FSEQ_W, + MIPS_INS_FSLE_D, + MIPS_INS_FSLE_W, + MIPS_INS_FSLT_D, + MIPS_INS_FSLT_W, + MIPS_INS_FSNE_D, + MIPS_INS_FSNE_W, + MIPS_INS_FSOR_D, + MIPS_INS_FSOR_W, + MIPS_INS_FSQRT_D, + MIPS_INS_SQRT_D, + MIPS_INS_SQRT_S, + MIPS_INS_FSQRT_W, + MIPS_INS_FSUB_D, + MIPS_INS_SUB_D, + MIPS_INS_SUB_PS, + MIPS_INS_SUB_S, + MIPS_INS_FSUB_W, + MIPS_INS_FSUEQ_D, + MIPS_INS_FSUEQ_W, + MIPS_INS_FSULE_D, + MIPS_INS_FSULE_W, + MIPS_INS_FSULT_D, + MIPS_INS_FSULT_W, + MIPS_INS_FSUNE_D, + MIPS_INS_FSUNE_W, + MIPS_INS_FSUN_D, + MIPS_INS_FSUN_W, + MIPS_INS_FTINT_S_D, + MIPS_INS_FTINT_S_W, + MIPS_INS_FTINT_U_D, + MIPS_INS_FTINT_U_W, + MIPS_INS_FTQ_H, + MIPS_INS_FTQ_W, + MIPS_INS_FTRUNC_S_D, + MIPS_INS_FTRUNC_S_W, + MIPS_INS_FTRUNC_U_D, + MIPS_INS_FTRUNC_U_W, + MIPS_INS_GINVI, + MIPS_INS_GINVT, + MIPS_INS_HADD_S_D, + MIPS_INS_HADD_S_H, + MIPS_INS_HADD_S_W, + MIPS_INS_HADD_U_D, + MIPS_INS_HADD_U_H, + MIPS_INS_HADD_U_W, + MIPS_INS_HSUB_S_D, + MIPS_INS_HSUB_S_H, + MIPS_INS_HSUB_S_W, + MIPS_INS_HSUB_U_D, + MIPS_INS_HSUB_U_H, + MIPS_INS_HSUB_U_W, + MIPS_INS_HYPCALL, + MIPS_INS_ILVEV_B, + MIPS_INS_ILVEV_D, + MIPS_INS_ILVEV_H, + MIPS_INS_ILVEV_W, + MIPS_INS_ILVL_B, + MIPS_INS_ILVL_D, + MIPS_INS_ILVL_H, + MIPS_INS_ILVL_W, + MIPS_INS_ILVOD_B, + MIPS_INS_ILVOD_D, + MIPS_INS_ILVOD_H, + MIPS_INS_ILVOD_W, + MIPS_INS_ILVR_B, + MIPS_INS_ILVR_D, + MIPS_INS_ILVR_H, + MIPS_INS_ILVR_W, MIPS_INS_INS, - MIPS_INS_INSERT, + MIPS_INS_INSERT_B, + MIPS_INS_INSERT_D, + MIPS_INS_INSERT_H, + MIPS_INS_INSERT_W, MIPS_INS_INSV, - MIPS_INS_INSVE, + MIPS_INS_INSVE_B, + MIPS_INS_INSVE_D, + MIPS_INS_INSVE_H, + MIPS_INS_INSVE_W, MIPS_INS_J, - MIPS_INS_JAL, MIPS_INS_JALR, + MIPS_INS_JALRC, + MIPS_INS_JALRC_HB, MIPS_INS_JALRS16, MIPS_INS_JALRS, + MIPS_INS_JALR_HB, MIPS_INS_JALS, MIPS_INS_JALX, MIPS_INS_JIALC, @@ -606,96 +1500,198 @@ typedef enum mips_insn { MIPS_INS_JR16, MIPS_INS_JRADDIUSP, MIPS_INS_JRC, - MIPS_INS_JALRC, + MIPS_INS_JRC16, + MIPS_INS_JRCADDIUSP, + MIPS_INS_JR_HB, + MIPS_INS_LAPC_H, + MIPS_INS_LAPC_B, MIPS_INS_LB, + MIPS_INS_LBE, MIPS_INS_LBU16, - MIPS_INS_LBUX, MIPS_INS_LBU, - MIPS_INS_LD, + MIPS_INS_LBUX, + MIPS_INS_LBX, + MIPS_INS_LBUE, MIPS_INS_LDC1, MIPS_INS_LDC2, MIPS_INS_LDC3, - MIPS_INS_LDI, + MIPS_INS_LDI_B, + MIPS_INS_LDI_D, + MIPS_INS_LDI_H, + MIPS_INS_LDI_W, MIPS_INS_LDL, MIPS_INS_LDPC, MIPS_INS_LDR, MIPS_INS_LDXC1, + MIPS_INS_LD_B, + MIPS_INS_LD_D, + MIPS_INS_LD_H, + MIPS_INS_LD_W, MIPS_INS_LH, + MIPS_INS_LHE, MIPS_INS_LHU16, - MIPS_INS_LHX, MIPS_INS_LHU, + MIPS_INS_LHUXS, + MIPS_INS_LHUX, + MIPS_INS_LHX, + MIPS_INS_LHXS, + MIPS_INS_LHUE, MIPS_INS_LI16, MIPS_INS_LL, MIPS_INS_LLD, + MIPS_INS_LLE, + MIPS_INS_LLWP, MIPS_INS_LSA, - MIPS_INS_LUXC1, MIPS_INS_LUI, + MIPS_INS_LUXC1, MIPS_INS_LW, MIPS_INS_LW16, MIPS_INS_LWC1, MIPS_INS_LWC2, MIPS_INS_LWC3, + MIPS_INS_LWE, MIPS_INS_LWL, + MIPS_INS_LWLE, MIPS_INS_LWM16, MIPS_INS_LWM32, MIPS_INS_LWPC, MIPS_INS_LWP, MIPS_INS_LWR, + MIPS_INS_LWRE, MIPS_INS_LWUPC, MIPS_INS_LWU, MIPS_INS_LWX, MIPS_INS_LWXC1, MIPS_INS_LWXS, - MIPS_INS_LI, MIPS_INS_MADD, - MIPS_INS_MADDF, - MIPS_INS_MADDR_Q, + MIPS_INS_MADDF_D, + MIPS_INS_MADDF_S, + MIPS_INS_MADDR_Q_H, + MIPS_INS_MADDR_Q_W, MIPS_INS_MADDU, - MIPS_INS_MADDV, - MIPS_INS_MADD_Q, - MIPS_INS_MAQ_SA, - MIPS_INS_MAQ_S, - MIPS_INS_MAXA, - MIPS_INS_MAXI_S, - MIPS_INS_MAXI_U, - MIPS_INS_MAX_A, - MIPS_INS_MAX, + MIPS_INS_MADDV_B, + MIPS_INS_MADDV_D, + MIPS_INS_MADDV_H, + MIPS_INS_MADDV_W, + MIPS_INS_MADD_D, + MIPS_INS_MADD_Q_H, + MIPS_INS_MADD_Q_W, + MIPS_INS_MADD_S, + MIPS_INS_MAQ_SA_W_PHL, + MIPS_INS_MAQ_SA_W_PHR, + MIPS_INS_MAQ_S_W_PHL, + MIPS_INS_MAQ_S_W_PHR, + MIPS_INS_MAXA_D, + MIPS_INS_MAXA_S, + MIPS_INS_MAXI_S_B, + MIPS_INS_MAXI_S_D, + MIPS_INS_MAXI_S_H, + MIPS_INS_MAXI_S_W, + MIPS_INS_MAXI_U_B, + MIPS_INS_MAXI_U_D, + MIPS_INS_MAXI_U_H, + MIPS_INS_MAXI_U_W, + MIPS_INS_MAX_A_B, + MIPS_INS_MAX_A_D, + MIPS_INS_MAX_A_H, + MIPS_INS_MAX_A_W, + MIPS_INS_MAX_D, MIPS_INS_MAX_S, - MIPS_INS_MAX_U, + MIPS_INS_MAX_S_B, + MIPS_INS_MAX_S_D, + MIPS_INS_MAX_S_H, + MIPS_INS_MAX_S_W, + MIPS_INS_MAX_U_B, + MIPS_INS_MAX_U_D, + MIPS_INS_MAX_U_H, + MIPS_INS_MAX_U_W, MIPS_INS_MFC0, MIPS_INS_MFC1, MIPS_INS_MFC2, + MIPS_INS_MFGC0, + MIPS_INS_MFHC0, MIPS_INS_MFHC1, + MIPS_INS_MFHC2, + MIPS_INS_MFHGC0, MIPS_INS_MFHI, + MIPS_INS_MFHI16, MIPS_INS_MFLO, - MIPS_INS_MINA, - MIPS_INS_MINI_S, - MIPS_INS_MINI_U, - MIPS_INS_MIN_A, - MIPS_INS_MIN, + MIPS_INS_MFLO16, + MIPS_INS_MFTR, + MIPS_INS_MINA_D, + MIPS_INS_MINA_S, + MIPS_INS_MINI_S_B, + MIPS_INS_MINI_S_D, + MIPS_INS_MINI_S_H, + MIPS_INS_MINI_S_W, + MIPS_INS_MINI_U_B, + MIPS_INS_MINI_U_D, + MIPS_INS_MINI_U_H, + MIPS_INS_MINI_U_W, + MIPS_INS_MIN_A_B, + MIPS_INS_MIN_A_D, + MIPS_INS_MIN_A_H, + MIPS_INS_MIN_A_W, + MIPS_INS_MIN_D, MIPS_INS_MIN_S, - MIPS_INS_MIN_U, + MIPS_INS_MIN_S_B, + MIPS_INS_MIN_S_D, + MIPS_INS_MIN_S_H, + MIPS_INS_MIN_S_W, + MIPS_INS_MIN_U_B, + MIPS_INS_MIN_U_D, + MIPS_INS_MIN_U_H, + MIPS_INS_MIN_U_W, MIPS_INS_MOD, MIPS_INS_MODSUB, MIPS_INS_MODU, - MIPS_INS_MOD_S, - MIPS_INS_MOD_U, + MIPS_INS_MOD_S_B, + MIPS_INS_MOD_S_D, + MIPS_INS_MOD_S_H, + MIPS_INS_MOD_S_W, + MIPS_INS_MOD_U_B, + MIPS_INS_MOD_U_D, + MIPS_INS_MOD_U_H, + MIPS_INS_MOD_U_W, MIPS_INS_MOVE, + MIPS_INS_MOVE16, + MIPS_INS_MOVE_BALC, MIPS_INS_MOVEP, + MIPS_INS_MOVE_V, + MIPS_INS_MOVF_D, MIPS_INS_MOVF, + MIPS_INS_MOVF_S, + MIPS_INS_MOVN_D, MIPS_INS_MOVN, + MIPS_INS_MOVN_S, + MIPS_INS_MOVT_D, MIPS_INS_MOVT, + MIPS_INS_MOVT_S, + MIPS_INS_MOVZ_D, MIPS_INS_MOVZ, + MIPS_INS_MOVZ_S, MIPS_INS_MSUB, - MIPS_INS_MSUBF, - MIPS_INS_MSUBR_Q, + MIPS_INS_MSUBF_D, + MIPS_INS_MSUBF_S, + MIPS_INS_MSUBR_Q_H, + MIPS_INS_MSUBR_Q_W, MIPS_INS_MSUBU, - MIPS_INS_MSUBV, - MIPS_INS_MSUB_Q, + MIPS_INS_MSUBV_B, + MIPS_INS_MSUBV_D, + MIPS_INS_MSUBV_H, + MIPS_INS_MSUBV_W, + MIPS_INS_MSUB_D, + MIPS_INS_MSUB_Q_H, + MIPS_INS_MSUB_Q_W, + MIPS_INS_MSUB_S, MIPS_INS_MTC0, MIPS_INS_MTC1, MIPS_INS_MTC2, + MIPS_INS_MTGC0, + MIPS_INS_MTHC0, MIPS_INS_MTHC1, + MIPS_INS_MTHC2, + MIPS_INS_MTHGC0, MIPS_INS_MTHI, MIPS_INS_MTHLIP, MIPS_INS_MTLO, @@ -705,66 +1701,139 @@ typedef enum mips_insn { MIPS_INS_MTP0, MIPS_INS_MTP1, MIPS_INS_MTP2, + MIPS_INS_MTTR, MIPS_INS_MUH, MIPS_INS_MUHU, - MIPS_INS_MULEQ_S, - MIPS_INS_MULEU_S, - MIPS_INS_MULQ_RS, - MIPS_INS_MULQ_S, - MIPS_INS_MULR_Q, - MIPS_INS_MULSAQ_S, - MIPS_INS_MULSA, + MIPS_INS_MULEQ_S_W_PHL, + MIPS_INS_MULEQ_S_W_PHR, + MIPS_INS_MULEU_S_PH_QBL, + MIPS_INS_MULEU_S_PH_QBR, + MIPS_INS_MULQ_RS_PH, + MIPS_INS_MULQ_RS_W, + MIPS_INS_MULQ_S_PH, + MIPS_INS_MULQ_S_W, + MIPS_INS_MULR_PS, + MIPS_INS_MULR_Q_H, + MIPS_INS_MULR_Q_W, + MIPS_INS_MULSAQ_S_W_PH, + MIPS_INS_MULSA_W_PH, MIPS_INS_MULT, MIPS_INS_MULTU, MIPS_INS_MULU, - MIPS_INS_MULV, - MIPS_INS_MUL_Q, - MIPS_INS_MUL_S, - MIPS_INS_NLOC, - MIPS_INS_NLZC, - MIPS_INS_NMADD, - MIPS_INS_NMSUB, - MIPS_INS_NOR, - MIPS_INS_NORI, + MIPS_INS_MULV_B, + MIPS_INS_MULV_D, + MIPS_INS_MULV_H, + MIPS_INS_MULV_W, + MIPS_INS_MUL_PH, + MIPS_INS_MUL_Q_H, + MIPS_INS_MUL_Q_W, + MIPS_INS_MUL_S_PH, + MIPS_INS_NLOC_B, + MIPS_INS_NLOC_D, + MIPS_INS_NLOC_H, + MIPS_INS_NLOC_W, + MIPS_INS_NLZC_B, + MIPS_INS_NLZC_D, + MIPS_INS_NLZC_H, + MIPS_INS_NLZC_W, + MIPS_INS_NMADD_D, + MIPS_INS_NMADD_S, + MIPS_INS_NMSUB_D, + MIPS_INS_NMSUB_S, + MIPS_INS_NOP32, + MIPS_INS_NOP, + MIPS_INS_NORI_B, + MIPS_INS_NOR_V, MIPS_INS_NOT16, MIPS_INS_NOT, + MIPS_INS_NEG, MIPS_INS_OR, MIPS_INS_OR16, + MIPS_INS_ORI_B, MIPS_INS_ORI, - MIPS_INS_PACKRL, + MIPS_INS_OR_V, + MIPS_INS_PACKRL_PH, MIPS_INS_PAUSE, - MIPS_INS_PCKEV, - MIPS_INS_PCKOD, - MIPS_INS_PCNT, - MIPS_INS_PICK, + MIPS_INS_PCKEV_B, + MIPS_INS_PCKEV_D, + MIPS_INS_PCKEV_H, + MIPS_INS_PCKEV_W, + MIPS_INS_PCKOD_B, + MIPS_INS_PCKOD_D, + MIPS_INS_PCKOD_H, + MIPS_INS_PCKOD_W, + MIPS_INS_PCNT_B, + MIPS_INS_PCNT_D, + MIPS_INS_PCNT_H, + MIPS_INS_PCNT_W, + MIPS_INS_PICK_PH, + MIPS_INS_PICK_QB, + MIPS_INS_PLL_PS, + MIPS_INS_PLU_PS, MIPS_INS_POP, - MIPS_INS_PRECEQU, - MIPS_INS_PRECEQ, - MIPS_INS_PRECEU, - MIPS_INS_PRECRQU_S, - MIPS_INS_PRECRQ, - MIPS_INS_PRECRQ_RS, - MIPS_INS_PRECR, - MIPS_INS_PRECR_SRA, - MIPS_INS_PRECR_SRA_R, + MIPS_INS_PRECEQU_PH_QBL, + MIPS_INS_PRECEQU_PH_QBLA, + MIPS_INS_PRECEQU_PH_QBR, + MIPS_INS_PRECEQU_PH_QBRA, + MIPS_INS_PRECEQ_W_PHL, + MIPS_INS_PRECEQ_W_PHR, + MIPS_INS_PRECEU_PH_QBL, + MIPS_INS_PRECEU_PH_QBLA, + MIPS_INS_PRECEU_PH_QBR, + MIPS_INS_PRECEU_PH_QBRA, + MIPS_INS_PRECRQU_S_QB_PH, + MIPS_INS_PRECRQ_PH_W, + MIPS_INS_PRECRQ_QB_PH, + MIPS_INS_PRECRQ_RS_PH_W, + MIPS_INS_PRECR_QB_PH, + MIPS_INS_PRECR_SRA_PH_W, + MIPS_INS_PRECR_SRA_R_PH_W, MIPS_INS_PREF, + MIPS_INS_PREFE, + MIPS_INS_PREFX, MIPS_INS_PREPEND, - MIPS_INS_RADDU, + MIPS_INS_PUL_PS, + MIPS_INS_PUU_PS, + MIPS_INS_RADDU_W_QB, MIPS_INS_RDDSP, MIPS_INS_RDHWR, - MIPS_INS_REPLV, - MIPS_INS_REPL, - MIPS_INS_RINT, + MIPS_INS_RDPGPR, + MIPS_INS_RECIP_D, + MIPS_INS_RECIP_S, + MIPS_INS_REPLV_PH, + MIPS_INS_REPLV_QB, + MIPS_INS_REPL_PH, + MIPS_INS_REPL_QB, + MIPS_INS_RESTORE_JRC, + MIPS_INS_RESTORE, + MIPS_INS_RINT_D, + MIPS_INS_RINT_S, MIPS_INS_ROTR, MIPS_INS_ROTRV, - MIPS_INS_ROUND, - MIPS_INS_SAT_S, - MIPS_INS_SAT_U, + MIPS_INS_ROTX, + MIPS_INS_ROUND_L_D, + MIPS_INS_ROUND_L_S, + MIPS_INS_ROUND_W_D, + MIPS_INS_ROUND_W_S, + MIPS_INS_RSQRT_D, + MIPS_INS_RSQRT_S, + MIPS_INS_SAT_S_B, + MIPS_INS_SAT_S_D, + MIPS_INS_SAT_S_H, + MIPS_INS_SAT_S_W, + MIPS_INS_SAT_U_B, + MIPS_INS_SAT_U_D, + MIPS_INS_SAT_U_H, + MIPS_INS_SAT_U_W, + MIPS_INS_SAVE, MIPS_INS_SB, MIPS_INS_SB16, + MIPS_INS_SBE, + MIPS_INS_SBX, MIPS_INS_SC, MIPS_INS_SCD, - MIPS_INS_SD, + MIPS_INS_SCE, + MIPS_INS_SCWP, MIPS_INS_SDBBP, MIPS_INS_SDBBP16, MIPS_INS_SDC1, @@ -776,79 +1845,178 @@ typedef enum mips_insn { MIPS_INS_SEB, MIPS_INS_SEH, MIPS_INS_SELEQZ, + MIPS_INS_SELEQZ_D, + MIPS_INS_SELEQZ_S, MIPS_INS_SELNEZ, - MIPS_INS_SEL, - MIPS_INS_SEQ, + MIPS_INS_SELNEZ_D, + MIPS_INS_SELNEZ_S, + MIPS_INS_SEL_D, + MIPS_INS_SEL_S, MIPS_INS_SEQI, MIPS_INS_SH, MIPS_INS_SH16, - MIPS_INS_SHF, + MIPS_INS_SHE, + MIPS_INS_SHF_B, + MIPS_INS_SHF_H, + MIPS_INS_SHF_W, MIPS_INS_SHILO, MIPS_INS_SHILOV, - MIPS_INS_SHLLV, - MIPS_INS_SHLLV_S, - MIPS_INS_SHLL, - MIPS_INS_SHLL_S, - MIPS_INS_SHRAV, - MIPS_INS_SHRAV_R, - MIPS_INS_SHRA, - MIPS_INS_SHRA_R, - MIPS_INS_SHRLV, - MIPS_INS_SHRL, - MIPS_INS_SLDI, - MIPS_INS_SLD, + MIPS_INS_SHLLV_PH, + MIPS_INS_SHLLV_QB, + MIPS_INS_SHLLV_S_PH, + MIPS_INS_SHLLV_S_W, + MIPS_INS_SHLL_PH, + MIPS_INS_SHLL_QB, + MIPS_INS_SHLL_S_PH, + MIPS_INS_SHLL_S_W, + MIPS_INS_SHRAV_PH, + MIPS_INS_SHRAV_QB, + MIPS_INS_SHRAV_R_PH, + MIPS_INS_SHRAV_R_QB, + MIPS_INS_SHRAV_R_W, + MIPS_INS_SHRA_PH, + MIPS_INS_SHRA_QB, + MIPS_INS_SHRA_R_PH, + MIPS_INS_SHRA_R_QB, + MIPS_INS_SHRA_R_W, + MIPS_INS_SHRLV_PH, + MIPS_INS_SHRLV_QB, + MIPS_INS_SHRL_PH, + MIPS_INS_SHRL_QB, + MIPS_INS_SHXS, + MIPS_INS_SHX, + MIPS_INS_SIGRIE, + MIPS_INS_SLDI_B, + MIPS_INS_SLDI_D, + MIPS_INS_SLDI_H, + MIPS_INS_SLDI_W, + MIPS_INS_SLD_B, + MIPS_INS_SLD_D, + MIPS_INS_SLD_H, + MIPS_INS_SLD_W, MIPS_INS_SLL, MIPS_INS_SLL16, - MIPS_INS_SLLI, + MIPS_INS_SLLI_B, + MIPS_INS_SLLI_D, + MIPS_INS_SLLI_H, + MIPS_INS_SLLI_W, MIPS_INS_SLLV, - MIPS_INS_SLT, - MIPS_INS_SLTI, + MIPS_INS_SLL_B, + MIPS_INS_SLL_D, + MIPS_INS_SLL_H, + MIPS_INS_SLL_W, MIPS_INS_SLTIU, - MIPS_INS_SLTU, - MIPS_INS_SNE, + MIPS_INS_SLTI, MIPS_INS_SNEI, - MIPS_INS_SPLATI, - MIPS_INS_SPLAT, + MIPS_INS_SOV, + MIPS_INS_SPLATI_B, + MIPS_INS_SPLATI_D, + MIPS_INS_SPLATI_H, + MIPS_INS_SPLATI_W, + MIPS_INS_SPLAT_B, + MIPS_INS_SPLAT_D, + MIPS_INS_SPLAT_H, + MIPS_INS_SPLAT_W, MIPS_INS_SRA, - MIPS_INS_SRAI, - MIPS_INS_SRARI, - MIPS_INS_SRAR, + MIPS_INS_SRAI_B, + MIPS_INS_SRAI_D, + MIPS_INS_SRAI_H, + MIPS_INS_SRAI_W, + MIPS_INS_SRARI_B, + MIPS_INS_SRARI_D, + MIPS_INS_SRARI_H, + MIPS_INS_SRARI_W, + MIPS_INS_SRAR_B, + MIPS_INS_SRAR_D, + MIPS_INS_SRAR_H, + MIPS_INS_SRAR_W, MIPS_INS_SRAV, + MIPS_INS_SRA_B, + MIPS_INS_SRA_D, + MIPS_INS_SRA_H, + MIPS_INS_SRA_W, MIPS_INS_SRL, MIPS_INS_SRL16, - MIPS_INS_SRLI, - MIPS_INS_SRLRI, - MIPS_INS_SRLR, + MIPS_INS_SRLI_B, + MIPS_INS_SRLI_D, + MIPS_INS_SRLI_H, + MIPS_INS_SRLI_W, + MIPS_INS_SRLRI_B, + MIPS_INS_SRLRI_D, + MIPS_INS_SRLRI_H, + MIPS_INS_SRLRI_W, + MIPS_INS_SRLR_B, + MIPS_INS_SRLR_D, + MIPS_INS_SRLR_H, + MIPS_INS_SRLR_W, MIPS_INS_SRLV, + MIPS_INS_SRL_B, + MIPS_INS_SRL_D, + MIPS_INS_SRL_H, + MIPS_INS_SRL_W, MIPS_INS_SSNOP, - MIPS_INS_ST, - MIPS_INS_SUBQH, - MIPS_INS_SUBQH_R, - MIPS_INS_SUBQ, - MIPS_INS_SUBQ_S, - MIPS_INS_SUBSUS_U, - MIPS_INS_SUBSUU_S, - MIPS_INS_SUBS_S, - MIPS_INS_SUBS_U, + MIPS_INS_ST_B, + MIPS_INS_ST_D, + MIPS_INS_ST_H, + MIPS_INS_ST_W, + MIPS_INS_SUB, + MIPS_INS_SUBQH_PH, + MIPS_INS_SUBQH_R_PH, + MIPS_INS_SUBQH_R_W, + MIPS_INS_SUBQH_W, + MIPS_INS_SUBQ_PH, + MIPS_INS_SUBQ_S_PH, + MIPS_INS_SUBQ_S_W, + MIPS_INS_SUBSUS_U_B, + MIPS_INS_SUBSUS_U_D, + MIPS_INS_SUBSUS_U_H, + MIPS_INS_SUBSUS_U_W, + MIPS_INS_SUBSUU_S_B, + MIPS_INS_SUBSUU_S_D, + MIPS_INS_SUBSUU_S_H, + MIPS_INS_SUBSUU_S_W, + MIPS_INS_SUBS_S_B, + MIPS_INS_SUBS_S_D, + MIPS_INS_SUBS_S_H, + MIPS_INS_SUBS_S_W, + MIPS_INS_SUBS_U_B, + MIPS_INS_SUBS_U_D, + MIPS_INS_SUBS_U_H, + MIPS_INS_SUBS_U_W, MIPS_INS_SUBU16, - MIPS_INS_SUBUH, - MIPS_INS_SUBUH_R, - MIPS_INS_SUBU, - MIPS_INS_SUBU_S, - MIPS_INS_SUBVI, - MIPS_INS_SUBV, + MIPS_INS_SUBUH_QB, + MIPS_INS_SUBUH_R_QB, + MIPS_INS_SUBU_PH, + MIPS_INS_SUBU_QB, + MIPS_INS_SUBU_S_PH, + MIPS_INS_SUBU_S_QB, + MIPS_INS_SUBVI_B, + MIPS_INS_SUBVI_D, + MIPS_INS_SUBVI_H, + MIPS_INS_SUBVI_W, + MIPS_INS_SUBV_B, + MIPS_INS_SUBV_D, + MIPS_INS_SUBV_H, + MIPS_INS_SUBV_W, MIPS_INS_SUXC1, MIPS_INS_SW, MIPS_INS_SW16, MIPS_INS_SWC1, MIPS_INS_SWC2, MIPS_INS_SWC3, + MIPS_INS_SWE, MIPS_INS_SWL, + MIPS_INS_SWLE, MIPS_INS_SWM16, MIPS_INS_SWM32, + MIPS_INS_SWPC, MIPS_INS_SWP, MIPS_INS_SWR, + MIPS_INS_SWRE, + MIPS_INS_SWSP, MIPS_INS_SWXC1, + MIPS_INS_SWXS, + MIPS_INS_SWX, MIPS_INS_SYNC, MIPS_INS_SYNCI, MIPS_INS_SYSCALL, @@ -858,6 +2026,14 @@ typedef enum mips_insn { MIPS_INS_TGEI, MIPS_INS_TGEIU, MIPS_INS_TGEU, + MIPS_INS_TLBGINV, + MIPS_INS_TLBGINVF, + MIPS_INS_TLBGP, + MIPS_INS_TLBGR, + MIPS_INS_TLBGWI, + MIPS_INS_TLBGWR, + MIPS_INS_TLBINV, + MIPS_INS_TLBINVF, MIPS_INS_TLBP, MIPS_INS_TLBR, MIPS_INS_TLBWI, @@ -868,27 +2044,150 @@ typedef enum mips_insn { MIPS_INS_TLTU, MIPS_INS_TNE, MIPS_INS_TNEI, - MIPS_INS_TRUNC, + MIPS_INS_TRUNC_L_D, + MIPS_INS_TRUNC_L_S, + MIPS_INS_UALH, + MIPS_INS_UALWM, + MIPS_INS_UALW, + MIPS_INS_UASH, + MIPS_INS_UASWM, + MIPS_INS_UASW, MIPS_INS_V3MULU, MIPS_INS_VMM0, MIPS_INS_VMULU, - MIPS_INS_VSHF, + MIPS_INS_VSHF_B, + MIPS_INS_VSHF_D, + MIPS_INS_VSHF_H, + MIPS_INS_VSHF_W, MIPS_INS_WAIT, MIPS_INS_WRDSP, + MIPS_INS_WRPGPR, MIPS_INS_WSBH, MIPS_INS_XOR, MIPS_INS_XOR16, + MIPS_INS_XORI_B, MIPS_INS_XORI, + MIPS_INS_XOR_V, + MIPS_INS_YIELD, - //> some alias instructions - MIPS_INS_NOP, - MIPS_INS_NEGU, + // clang-format on + // generated content end + MIPS_INS_ENDING, - //> special instructions - MIPS_INS_JALR_HB, // jump and link with Hazard Barrier - MIPS_INS_JR_HB, // jump register with Hazard Barrier + MIPS_INS_ALIAS_BEGIN, + // generated content begin + // clang-format off - MIPS_INS_ENDING, + MIPS_INS_ALIAS_ADDIU_B32, // Real instr.: MIPS_ADDIUGP48_NM + MIPS_INS_ALIAS_BITREVB, // Real instr.: MIPS_ROTX_NM + MIPS_INS_ALIAS_BITREVH, // Real instr.: MIPS_ROTX_NM + MIPS_INS_ALIAS_BYTEREVH, // Real instr.: MIPS_ROTX_NM + MIPS_INS_ALIAS_NOT, // Real instr.: MIPS_NOR_NM + MIPS_INS_ALIAS_RESTORE_JRC, // Real instr.: MIPS_RESTOREJRC16_NM + MIPS_INS_ALIAS_RESTORE, // Real instr.: MIPS_RESTORE_NM + MIPS_INS_ALIAS_SAVE, // Real instr.: MIPS_SAVE16_NM + MIPS_INS_ALIAS_MOVE, // Real instr.: MIPS_OR + MIPS_INS_ALIAS_BAL, // Real instr.: MIPS_BGEZAL + MIPS_INS_ALIAS_JALR_HB, // Real instr.: MIPS_JALR_HB + MIPS_INS_ALIAS_NEG, // Real instr.: MIPS_SUB + MIPS_INS_ALIAS_NEGU, // Real instr.: MIPS_SUBu + MIPS_INS_ALIAS_NOP, // Real instr.: MIPS_SLL + MIPS_INS_ALIAS_BNEZL, // Real instr.: MIPS_BNEL + MIPS_INS_ALIAS_BEQZL, // Real instr.: MIPS_BEQL + MIPS_INS_ALIAS_SYSCALL, // Real instr.: MIPS_SYSCALL + MIPS_INS_ALIAS_BREAK, // Real instr.: MIPS_BREAK + MIPS_INS_ALIAS_EI, // Real instr.: MIPS_EI + MIPS_INS_ALIAS_DI, // Real instr.: MIPS_DI + MIPS_INS_ALIAS_TEQ, // Real instr.: MIPS_TEQ + MIPS_INS_ALIAS_TGE, // Real instr.: MIPS_TGE + MIPS_INS_ALIAS_TGEU, // Real instr.: MIPS_TGEU + MIPS_INS_ALIAS_TLT, // Real instr.: MIPS_TLT + MIPS_INS_ALIAS_TLTU, // Real instr.: MIPS_TLTU + MIPS_INS_ALIAS_TNE, // Real instr.: MIPS_TNE + MIPS_INS_ALIAS_RDHWR, // Real instr.: MIPS_RDHWR + MIPS_INS_ALIAS_SDBBP, // Real instr.: MIPS_SDBBP + MIPS_INS_ALIAS_SYNC, // Real instr.: MIPS_SYNC + MIPS_INS_ALIAS_HYPCALL, // Real instr.: MIPS_HYPCALL + MIPS_INS_ALIAS_NOR, // Real instr.: MIPS_NORImm + MIPS_INS_ALIAS_C_F_S, // Real instr.: MIPS_C_F_S + MIPS_INS_ALIAS_C_UN_S, // Real instr.: MIPS_C_UN_S + MIPS_INS_ALIAS_C_EQ_S, // Real instr.: MIPS_C_EQ_S + MIPS_INS_ALIAS_C_UEQ_S, // Real instr.: MIPS_C_UEQ_S + MIPS_INS_ALIAS_C_OLT_S, // Real instr.: MIPS_C_OLT_S + MIPS_INS_ALIAS_C_ULT_S, // Real instr.: MIPS_C_ULT_S + MIPS_INS_ALIAS_C_OLE_S, // Real instr.: MIPS_C_OLE_S + MIPS_INS_ALIAS_C_ULE_S, // Real instr.: MIPS_C_ULE_S + MIPS_INS_ALIAS_C_SF_S, // Real instr.: MIPS_C_SF_S + MIPS_INS_ALIAS_C_NGLE_S, // Real instr.: MIPS_C_NGLE_S + MIPS_INS_ALIAS_C_SEQ_S, // Real instr.: MIPS_C_SEQ_S + MIPS_INS_ALIAS_C_NGL_S, // Real instr.: MIPS_C_NGL_S + MIPS_INS_ALIAS_C_LT_S, // Real instr.: MIPS_C_LT_S + MIPS_INS_ALIAS_C_NGE_S, // Real instr.: MIPS_C_NGE_S + MIPS_INS_ALIAS_C_LE_S, // Real instr.: MIPS_C_LE_S + MIPS_INS_ALIAS_C_NGT_S, // Real instr.: MIPS_C_NGT_S + MIPS_INS_ALIAS_BC1T, // Real instr.: MIPS_BC1T + MIPS_INS_ALIAS_BC1F, // Real instr.: MIPS_BC1F + MIPS_INS_ALIAS_C_F_D, // Real instr.: MIPS_C_F_D32 + MIPS_INS_ALIAS_C_UN_D, // Real instr.: MIPS_C_UN_D32 + MIPS_INS_ALIAS_C_EQ_D, // Real instr.: MIPS_C_EQ_D32 + MIPS_INS_ALIAS_C_UEQ_D, // Real instr.: MIPS_C_UEQ_D32 + MIPS_INS_ALIAS_C_OLT_D, // Real instr.: MIPS_C_OLT_D32 + MIPS_INS_ALIAS_C_ULT_D, // Real instr.: MIPS_C_ULT_D32 + MIPS_INS_ALIAS_C_OLE_D, // Real instr.: MIPS_C_OLE_D32 + MIPS_INS_ALIAS_C_ULE_D, // Real instr.: MIPS_C_ULE_D32 + MIPS_INS_ALIAS_C_SF_D, // Real instr.: MIPS_C_SF_D32 + MIPS_INS_ALIAS_C_NGLE_D, // Real instr.: MIPS_C_NGLE_D32 + MIPS_INS_ALIAS_C_SEQ_D, // Real instr.: MIPS_C_SEQ_D32 + MIPS_INS_ALIAS_C_NGL_D, // Real instr.: MIPS_C_NGL_D32 + MIPS_INS_ALIAS_C_LT_D, // Real instr.: MIPS_C_LT_D32 + MIPS_INS_ALIAS_C_NGE_D, // Real instr.: MIPS_C_NGE_D32 + MIPS_INS_ALIAS_C_LE_D, // Real instr.: MIPS_C_LE_D32 + MIPS_INS_ALIAS_C_NGT_D, // Real instr.: MIPS_C_NGT_D32 + MIPS_INS_ALIAS_BC1TL, // Real instr.: MIPS_BC1TL + MIPS_INS_ALIAS_BC1FL, // Real instr.: MIPS_BC1FL + MIPS_INS_ALIAS_DNEG, // Real instr.: MIPS_DSUB + MIPS_INS_ALIAS_DNEGU, // Real instr.: MIPS_DSUBu + MIPS_INS_ALIAS_SLT, // Real instr.: MIPS_SLTImm64 + MIPS_INS_ALIAS_SLTU, // Real instr.: MIPS_SLTUImm64 + MIPS_INS_ALIAS_SIGRIE, // Real instr.: MIPS_SIGRIE + MIPS_INS_ALIAS_JR, // Real instr.: MIPS_JALR + MIPS_INS_ALIAS_JRC, // Real instr.: MIPS_JIC + MIPS_INS_ALIAS_JALRC, // Real instr.: MIPS_JIALC + MIPS_INS_ALIAS_DIV, // Real instr.: MIPS_DIV + MIPS_INS_ALIAS_DIVU, // Real instr.: MIPS_DIVU + MIPS_INS_ALIAS_LAPC, // Real instr.: MIPS_ADDIUPC + MIPS_INS_ALIAS_WRDSP, // Real instr.: MIPS_WRDSP + MIPS_INS_ALIAS_WAIT, // Real instr.: MIPS_WAIT_MM + MIPS_INS_ALIAS_SW, // Real instr.: MIPS_SWSP_MM + MIPS_INS_ALIAS_JALRC_HB, // Real instr.: MIPS_JALRC_HB_MMR6 + MIPS_INS_ALIAS_ADDIU_B, // Real instr.: MIPS_ADDIUGPB_NM + MIPS_INS_ALIAS_ADDIU_W, // Real instr.: MIPS_ADDIUGPW_NM + MIPS_INS_ALIAS_JRC_HB, // Real instr.: MIPS_JALRCHB_NM + MIPS_INS_ALIAS_BEQC, // Real instr.: MIPS_BEQC16_NM + MIPS_INS_ALIAS_BNEC, // Real instr.: MIPS_BNEC16_NM + MIPS_INS_ALIAS_BEQZC, // Real instr.: MIPS_BEQC_NM + MIPS_INS_ALIAS_BNEZC, // Real instr.: MIPS_BNEC_NM + MIPS_INS_ALIAS_MFC0, // Real instr.: MIPS_MFC0_NM + MIPS_INS_ALIAS_MFHC0, // Real instr.: MIPS_MFHC0_NM + MIPS_INS_ALIAS_MTC0, // Real instr.: MIPS_MTC0_NM + MIPS_INS_ALIAS_MTHC0, // Real instr.: MIPS_MTHC0_NM + MIPS_INS_ALIAS_DMT, // Real instr.: MIPS_DMT + MIPS_INS_ALIAS_EMT, // Real instr.: MIPS_EMT + MIPS_INS_ALIAS_DVPE, // Real instr.: MIPS_DVPE + MIPS_INS_ALIAS_EVPE, // Real instr.: MIPS_EVPE + MIPS_INS_ALIAS_YIELD, // Real instr.: MIPS_YIELD + MIPS_INS_ALIAS_MFTC0, // Real instr.: MIPS_MFTC0 + MIPS_INS_ALIAS_MFTLO, // Real instr.: MIPS_MFTLO + MIPS_INS_ALIAS_MFTHI, // Real instr.: MIPS_MFTHI + MIPS_INS_ALIAS_MFTACX, // Real instr.: MIPS_MFTACX + MIPS_INS_ALIAS_MTTC0, // Real instr.: MIPS_MTTC0 + MIPS_INS_ALIAS_MTTLO, // Real instr.: MIPS_MTTLO + MIPS_INS_ALIAS_MTTHI, // Real instr.: MIPS_MTTHI + MIPS_INS_ALIAS_MTTACX, // Real instr.: MIPS_MTTACX + + // clang-format on + // generated content end + MIPS_INS_ALIAS_END, } mips_insn; /// Group of MIPS instructions @@ -912,39 +2211,68 @@ typedef enum mips_insn_group { MIPS_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE // Architecture-specific groups - MIPS_GRP_BITCOUNT = 128, - MIPS_GRP_DSP, - MIPS_GRP_DSPR2, - MIPS_GRP_FPIDX, - MIPS_GRP_MSA, - MIPS_GRP_MIPS32R2, - MIPS_GRP_MIPS64, - MIPS_GRP_MIPS64R2, - MIPS_GRP_SEINREG, - MIPS_GRP_STDENC, - MIPS_GRP_SWAP, - MIPS_GRP_MICROMIPS, - MIPS_GRP_MIPS16MODE, - MIPS_GRP_FP64BIT, - MIPS_GRP_NONANSFPMATH, - MIPS_GRP_NOTFP64BIT, - MIPS_GRP_NOTINMICROMIPS, - MIPS_GRP_NOTNACL, - MIPS_GRP_NOTMIPS32R6, - MIPS_GRP_NOTMIPS64R6, - MIPS_GRP_CNMIPS, - MIPS_GRP_MIPS32, - MIPS_GRP_MIPS32R6, - MIPS_GRP_MIPS64R6, - MIPS_GRP_MIPS2, - MIPS_GRP_MIPS3, - MIPS_GRP_MIPS3_32, - MIPS_GRP_MIPS3_32R2, - MIPS_GRP_MIPS4_32, - MIPS_GRP_MIPS4_32R2, - MIPS_GRP_MIPS5_32R2, - MIPS_GRP_GP32BIT, - MIPS_GRP_GP64BIT, + // generated content begin + // clang-format off + + MIPS_FEATURE_HASMIPS2 = 128, + MIPS_FEATURE_HASMIPS3_32, + MIPS_FEATURE_HASMIPS3_32R2, + MIPS_FEATURE_HASMIPS3, + MIPS_FEATURE_NOTMIPS3, + MIPS_FEATURE_HASMIPS4_32, + MIPS_FEATURE_NOTMIPS4_32, + MIPS_FEATURE_HASMIPS4_32R2, + MIPS_FEATURE_HASMIPS5_32R2, + MIPS_FEATURE_HASMIPS32, + MIPS_FEATURE_HASMIPS32R2, + MIPS_FEATURE_HASMIPS32R5, + MIPS_FEATURE_HASMIPS32R6, + MIPS_FEATURE_NOTMIPS32R6, + MIPS_FEATURE_HASNANOMIPS, + MIPS_FEATURE_NOTNANOMIPS, + MIPS_FEATURE_ISGP64BIT, + MIPS_FEATURE_ISGP32BIT, + MIPS_FEATURE_ISPTR64BIT, + MIPS_FEATURE_ISPTR32BIT, + MIPS_FEATURE_HASMIPS64, + MIPS_FEATURE_NOTMIPS64, + MIPS_FEATURE_HASMIPS64R2, + MIPS_FEATURE_HASMIPS64R5, + MIPS_FEATURE_HASMIPS64R6, + MIPS_FEATURE_NOTMIPS64R6, + MIPS_FEATURE_INMIPS16MODE, + MIPS_FEATURE_NOTINMIPS16MODE, + MIPS_FEATURE_HASCNMIPS, + MIPS_FEATURE_NOTCNMIPS, + MIPS_FEATURE_HASCNMIPSP, + MIPS_FEATURE_NOTCNMIPSP, + MIPS_FEATURE_ISSYM32, + MIPS_FEATURE_ISSYM64, + MIPS_FEATURE_HASSTDENC, + MIPS_FEATURE_INMICROMIPS, + MIPS_FEATURE_NOTINMICROMIPS, + MIPS_FEATURE_HASEVA, + MIPS_FEATURE_HASMSA, + MIPS_FEATURE_HASMADD4, + MIPS_FEATURE_HASMT, + MIPS_FEATURE_USEINDIRECTJUMPSHAZARD, + MIPS_FEATURE_NOINDIRECTJUMPGUARDS, + MIPS_FEATURE_HASCRC, + MIPS_FEATURE_HASVIRT, + MIPS_FEATURE_HASGINV, + MIPS_FEATURE_HASTLB, + MIPS_FEATURE_ISFP64BIT, + MIPS_FEATURE_NOTFP64BIT, + MIPS_FEATURE_ISSINGLEFLOAT, + MIPS_FEATURE_ISNOTSINGLEFLOAT, + MIPS_FEATURE_ISNOTSOFTFLOAT, + MIPS_FEATURE_HASMIPS3D, + MIPS_FEATURE_HASDSP, + MIPS_FEATURE_HASDSPR2, + MIPS_FEATURE_HASDSPR3, + + // clang-format on + // generated content end MIPS_GRP_ENDING, } mips_insn_group; diff --git a/suite/MC/Mips/micromips-alu-instructions-EB.s.cs b/suite/MC/Mips/micromips-alu-instructions-EB.s.cs index f4dbe7a8c1..67c00277df 100644 --- a/suite/MC/Mips/micromips-alu-instructions-EB.s.cs +++ b/suite/MC/Mips/micromips-alu-instructions-EB.s.cs @@ -7,8 +7,8 @@ 0x00,0xe6,0x49,0x50 = addu $t1, $a2, $a3 0x00,0xe6,0x49,0x90 = sub $t1, $a2, $a3 0x00,0xa3,0x21,0xd0 = subu $a0, $v1, $a1 -0x00,0xe0,0x31,0x90 = sub $a2, $zero, $a3 -0x00,0xe0,0x31,0xd0 = subu $a2, $zero, $a3 +0x00,0xe0,0x31,0x90 = neg $a2, $a3 +0x00,0xe0,0x31,0xd0 = negu $a2, $a3 0x00,0x08,0x39,0x50 = addu $a3, $t0, $zero 0x00,0xa3,0x1b,0x50 = slt $v1, $v1, $a1 0x90,0x63,0x00,0x67 = slti $v1, $v1, 103 diff --git a/suite/MC/Mips/micromips-alu-instructions.s.cs b/suite/MC/Mips/micromips-alu-instructions.s.cs index 81fe6438c7..2571f8b752 100644 --- a/suite/MC/Mips/micromips-alu-instructions.s.cs +++ b/suite/MC/Mips/micromips-alu-instructions.s.cs @@ -7,8 +7,8 @@ 0xe6,0x00,0x50,0x49 = addu $t1, $a2, $a3 0xe6,0x00,0x90,0x49 = sub $t1, $a2, $a3 0xa3,0x00,0xd0,0x21 = subu $a0, $v1, $a1 -0xe0,0x00,0x90,0x31 = sub $a2, $zero, $a3 -0xe0,0x00,0xd0,0x31 = subu $a2, $zero, $a3 +0xe0,0x00,0x90,0x31 = neg $a2, $a3 +0xe0,0x00,0xd0,0x31 = negu $a2, $a3 0x08,0x00,0x50,0x39 = addu $a3, $t0, $zero 0xa3,0x00,0x50,0x1b = slt $v1, $v1, $a1 0x63,0x90,0x67,0x00 = slti $v1, $v1, 103 diff --git a/suite/MC/Mips/micromips-branch-instructions-EB.s.cs b/suite/MC/Mips/micromips-branch-instructions-EB.s.cs index 947ea25005..be78bff186 100644 --- a/suite/MC/Mips/micromips-branch-instructions-EB.s.cs +++ b/suite/MC/Mips/micromips-branch-instructions-EB.s.cs @@ -1,11 +1,11 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None -0x94,0x00,0x02,0x9a = b 1332 -0x94,0xc9,0x02,0x9a = beq $t1, $a2, 1332 -0x40,0x46,0x02,0x9a = bgez $a2, 1332 -0x40,0x66,0x02,0x9a = bgezal $a2, 1332 -0x40,0x26,0x02,0x9a = bltzal $a2, 1332 -0x40,0xc6,0x02,0x9a = bgtz $a2, 1332 -0x40,0x86,0x02,0x9a = blez $a2, 1332 -0xb4,0xc9,0x02,0x9a = bne $t1, $a2, 1332 -// 0x40,0x60,0x02,0x9a = bal 1332 -0x40,0x06,0x02,0x9a = bltz $a2, 1332 +0x94,0x00,0x02,0x9a = b 0x538 +0x94,0xc9,0x02,0x9a = beq $t1, $a2, 0x538 +0x40,0x46,0x02,0x9a = bgez $a2, 0x538 +0x40,0x66,0x02,0x9a = bgezal $a2, 0x538 +0x40,0x26,0x02,0x9a = bltzal $a2, 0x538 +0x40,0xc6,0x02,0x9a = bgtz $a2, 0x538 +0x40,0x86,0x02,0x9a = blez $a2, 0x538 +0xb4,0xc9,0x02,0x9a = bne $t1, $a2, 0x538 +// 0x40,0x60,0x02,0x9a = bal 0x538 +0x40,0x06,0x02,0x9a = bltz $a2, 0x538 diff --git a/suite/MC/Mips/micromips-branch-instructions.s.cs b/suite/MC/Mips/micromips-branch-instructions.s.cs index 286bc0d94e..43ba3ba0fe 100644 --- a/suite/MC/Mips/micromips-branch-instructions.s.cs +++ b/suite/MC/Mips/micromips-branch-instructions.s.cs @@ -1,11 +1,11 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None -0x00,0x94,0x9a,0x02 = b 1332 -0xc9,0x94,0x9a,0x02 = beq $t1, $a2, 1332 -0x46,0x40,0x9a,0x02 = bgez $a2, 1332 -0x66,0x40,0x9a,0x02 = bgezal $a2, 1332 -0x26,0x40,0x9a,0x02 = bltzal $a2, 1332 -0xc6,0x40,0x9a,0x02 = bgtz $a2, 1332 -0x86,0x40,0x9a,0x02 = blez $a2, 1332 -0xc9,0xb4,0x9a,0x02 = bne $t1, $a2, 1332 -// 0x60,0x40,0x9a,0x02 = bal 1332 -0x06,0x40,0x9a,0x02 = bltz $a2, 1332 +0x00,0x94,0x9a,0x02 = b 0x538 +0xc9,0x94,0x9a,0x02 = beq $t1, $a2, 0x538 +0x46,0x40,0x9a,0x02 = bgez $a2, 0x538 +0x66,0x40,0x9a,0x02 = bgezal $a2, 0x538 +0x26,0x40,0x9a,0x02 = bltzal $a2, 0x538 +0xc6,0x40,0x9a,0x02 = bgtz $a2, 0x538 +0x86,0x40,0x9a,0x02 = blez $a2, 0x538 +0xc9,0xb4,0x9a,0x02 = bne $t1, $a2, 0x538 +// 0x60,0x40,0x9a,0x02 = bal 0x538 +0x06,0x40,0x9a,0x02 = bltz $a2, 0x538 diff --git a/suite/MC/Mips/micromips-expansions.s.cs b/suite/MC/Mips/micromips-expansions.s.cs index b16331bb24..c9a385561b 100644 --- a/suite/MC/Mips/micromips-expansions.s.cs +++ b/suite/MC/Mips/micromips-expansions.s.cs @@ -1,20 +1,25 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None -0xa0,0x50,0x7b,0x00 = ori $a1, $zero, 123 -0xc0,0x30,0xd7,0xf6 = addiu $a2, $zero, -2345 -0xa7,0x41,0x01,0x00 = lui $a3, 1 -0xe7,0x50,0x02,0x00 = ori $a3, $a3, 2 -0x80,0x30,0x14,0x00 = addiu $a0, $zero, 20 -0xa7,0x41,0x01,0x00 = lui $a3, 1 -0xe7,0x50,0x02,0x00 = ori $a3, $a3, 2 -0x85,0x30,0x14,0x00 = addiu $a0, $a1, 20 -0xa7,0x41,0x01,0x00 = lui $a3, 1 -0xe7,0x50,0x02,0x00 = ori $a3, $a3, 2 -0x07,0x01,0x50,0x39 = addu $a3, $a3, $t0 -0x8a,0x00,0x50,0x51 = addu $t2, $t2, $a0 -0x21,0x01,0x50,0x09 = addu $at, $at, $t1 -0xaa,0x41,0x0a,0x00 = lui $t2, 10 -0x8a,0x00,0x50,0x51 = addu $t2, $t2, $a0 -0x4a,0xfd,0x7b,0x00 = lw $t2, 123($t2) -0xa1,0x41,0x02,0x00 = lui $at, 2 -0x21,0x01,0x50,0x09 = addu $at, $at, $t1 -// 0x41,0xf9,0x40,0xe2 = sw $t2, 57920($at) + +0xa0,0x30,0x7b,0x00 == addiu $5, $zero, 123 # encoding: [0xa0,0x30,0x7b,0x00] +0xc0,0x30,0xd7,0xf6 == addiu $6, $zero, -2345 # encoding: [0xc0,0x30,0xd7,0xf6] +0xa7,0x41,0x01,0x00 == lui $7, 1 # encoding: [0xa7,0x41,0x01,0x00] +0xe7,0x50,0x02,0x00 == ori $7, $7, 2 # encoding: [0xe7,0x50,0x02,0x00] +0x80,0x30,0x14,0x00 == addiu $4, $zero, 20 # encoding: [0x80,0x30,0x14,0x00] +0xa7,0x41,0x01,0x00 == lui $7, 1 # encoding: [0xa7,0x41,0x01,0x00] +0xe7,0x50,0x02,0x00 == ori $7, $7, 2 # encoding: [0xe7,0x50,0x02,0x00] +0x85,0x30,0x14,0x00 == addiu $4, $5, 20 # encoding: [0x85,0x30,0x14,0x00] +0xa7,0x41,0x01,0x00 == lui $7, 1 # encoding: [0xa7,0x41,0x01,0x00] +0xe7,0x50,0x02,0x00 == ori $7, $7, 2 # encoding: [0xe7,0x50,0x02,0x00] +0x07,0x01,0x50,0x39 == addu $7, $7, $8 # encoding: [0x07,0x01,0x50,0x39] +0xaa == lui $10, %hi(symbol) # encoding: [0xaa'A',0x41'A',0x00,0x00] +0x8a,0x00,0x50,0x51 == addu $10, $10, $4 # encoding: [0x8a,0x00,0x50,0x51] +0x4a == lw $10, %lo(symbol)($10) # encoding: [0x4a'A',0xfd'A',0x00,0x00] +0xa1 == lui $1, %hi(symbol) # encoding: [0xa1'A',0x41'A',0x00,0x00] +0x21,0x01,0x50,0x09 == addu $1, $1, $9 # encoding: [0x21,0x01,0x50,0x09] +0x41 == sw $10, %lo(symbol)($1) # encoding: [0x41'A',0xf9'A',0x00,0x00] +0xaa,0x41,0x0a,0x00 == lui $10, 10 # encoding: [0xaa,0x41,0x0a,0x00] +0x8a,0x00,0x50,0x51 == addu $10, $10, $4 # encoding: [0x8a,0x00,0x50,0x51] +0x4a,0xfd,0x7b,0x00 == lw $10, 123($10) # encoding: [0x4a,0xfd,0x7b,0x00] +0xa1,0x41,0x02,0x00 == lui $1, 2 # encoding: [0xa1,0x41,0x02,0x00] +0x21,0x01,0x50,0x09 == addu $1, $1, $9 # encoding: [0x21,0x01,0x50,0x09] +0x41,0xf9,0x40,0xe2 == sw $10, -7616($1) # encoding: [0x41,0xf9,0x40,0xe2] diff --git a/suite/MC/Mips/mips-alu-instructions.s.cs b/suite/MC/Mips/mips-alu-instructions.s.cs index 1ee3337f23..cfdf23e33f 100644 --- a/suite/MC/Mips/mips-alu-instructions.s.cs +++ b/suite/MC/Mips/mips-alu-instructions.s.cs @@ -1,53 +1,67 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32, None -0x24,0x48,0xc7,0x00 = and $t1, $a2, $a3 -0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767 -0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767 -0x67,0x45,0x29,0x31 = andi $t1, $t1, 17767 -0x21,0x30,0xe6,0x70 = clo $a2, $a3 -0x20,0x30,0xe6,0x70 = clz $a2, $a3 -0x84,0x61,0x33,0x7d = ins $s3, $t1, 6, 7 -0x27,0x48,0xc7,0x00 = nor $t1, $a2, $a3 -0x25,0x18,0x65,0x00 = or $v1, $v1, $a1 -0x67,0x45,0xa4,0x34 = ori $a0, $a1, 17767 -0x67,0x45,0xc9,0x34 = ori $t1, $a2, 17767 -0x80,0x00,0x6b,0x35 = ori $t3, $t3, 128 -0xc2,0x49,0x26,0x00 = rotr $t1, $a2, 7 -0x46,0x48,0xe6,0x00 = rotrv $t1, $a2, $a3 -0xc0,0x21,0x03,0x00 = sll $a0, $v1, 7 -0x04,0x10,0xa3,0x00 = sllv $v0, $v1, $a1 -0x2a,0x18,0x65,0x00 = slt $v1, $v1, $a1 -0x67,0x00,0x63,0x28 = slti $v1, $v1, 103 -0x67,0x00,0x63,0x28 = slti $v1, $v1, 103 -0x67,0x00,0x63,0x2c = sltiu $v1, $v1, 103 -0x2b,0x18,0x65,0x00 = sltu $v1, $v1, $a1 -0xc3,0x21,0x03,0x00 = sra $a0, $v1, 7 -0x07,0x10,0xa3,0x00 = srav $v0, $v1, $a1 -0xc2,0x21,0x03,0x00 = srl $a0, $v1, 7 -0x06,0x10,0xa3,0x00 = srlv $v0, $v1, $a1 -0x26,0x18,0x65,0x00 = xor $v1, $v1, $a1 -0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767 -0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767 -0x0c,0x00,0x6b,0x39 = xori $t3, $t3, 12 -0xa0,0x30,0x07,0x7c = wsbh $a2, $a3 -0x27,0x38,0x00,0x01 = not $a3, $t0 -0x20,0x48,0xc7,0x00 = add $t1, $a2, $a3 -0x67,0x45,0xc9,0x20 = addi $t1, $a2, 17767 -0x67,0xc5,0xc9,0x24 = addiu $t1, $a2, -15001 -0x67,0x45,0xc9,0x20 = addi $t1, $a2, 17767 -0x67,0x45,0x29,0x21 = addi $t1, $t1, 17767 -0x67,0xc5,0xc9,0x24 = addiu $t1, $a2, -15001 -0x28,0x00,0x6b,0x25 = addiu $t3, $t3, 40 -0x21,0x48,0xc7,0x00 = addu $t1, $a2, $a3 -0x00,0x00,0xc7,0x70 = madd $a2, $a3 -0x01,0x00,0xc7,0x70 = maddu $a2, $a3 -0x04,0x00,0xc7,0x70 = msub $a2, $a3 -0x05,0x00,0xc7,0x70 = msubu $a2, $a3 -0x18,0x00,0x65,0x00 = mult $v1, $a1 -0x19,0x00,0x65,0x00 = multu $v1, $a1 -0x22,0x48,0xc7,0x00 = sub $t1, $a2, $a3 -0xc8,0xff,0xbd,0x23 = addi $sp, $sp, -56 -0x23,0x20,0x65,0x00 = subu $a0, $v1, $a1 -0xd8,0xff,0xbd,0x27 = addiu $sp, $sp, -40 -0x22,0x30,0x07,0x00 = neg $a2, $a3 -0x23,0x30,0x07,0x00 = negu $a2, $a3 -0x21,0x38,0x00,0x01 = move $a3, $t0 + +0x24,0x48,0xc7,0x00 == and $9, $6, $7 # encoding: [0x24,0x48,0xc7,0x00] +0x67,0x45,0xc9,0x30 == andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30] +0x67,0x45,0xc9,0x30 == andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30] +0x67,0x45,0x29,0x31 == andi $9, $9, 17767 # encoding: [0x67,0x45,0x29,0x31] +0x21,0x30,0xe6,0x70 == clo $6, $7 # encoding: [0x21,0x30,0xe6,0x70] +0x20,0x30,0xe6,0x70 == clz $6, $7 # encoding: [0x20,0x30,0xe6,0x70] +0x84,0x61,0x33,0x7d == ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d] +0x27,0x48,0xc7,0x00 == nor $9, $6, $7 # encoding: [0x27,0x48,0xc7,0x00] +0x25,0x18,0x65,0x00 == or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00] +0x67,0x45,0xa4,0x34 == ori $4, $5, 17767 # encoding: [0x67,0x45,0xa4,0x34] +0x67,0x45,0xc9,0x34 == ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34] +0x80,0x00,0x6b,0x35 == ori $11, $11, 128 # encoding: [0x80,0x00,0x6b,0x35] +0xc2,0x49,0x26,0x00 == rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00] +0x46,0x48,0xe6,0x00 == rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00] +0xc0,0x21,0x03,0x00 == sll $4, $3, 7 # encoding: [0xc0,0x21,0x03,0x00] +0x04,0x10,0xa3,0x00 == sllv $2, $3, $5 # encoding: [0x04,0x10,0xa3,0x00] +0x2a,0x18,0x65,0x00 == slt $3, $3, $5 # encoding: [0x2a,0x18,0x65,0x00] +0x67,0x00,0x63,0x28 == slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28] +0x67,0x00,0x63,0x28 == slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28] +0x67,0x00,0x63,0x2c == sltiu $3, $3, 103 # encoding: [0x67,0x00,0x63,0x2c] +0x2b,0x18,0x65,0x00 == sltu $3, $3, $5 # encoding: [0x2b,0x18,0x65,0x00] +0xc3,0x21,0x03,0x00 == sra $4, $3, 7 # encoding: [0xc3,0x21,0x03,0x00] +0x07,0x10,0xa3,0x00 == srav $2, $3, $5 # encoding: [0x07,0x10,0xa3,0x00] +0xc2,0x21,0x03,0x00 == srl $4, $3, 7 # encoding: [0xc2,0x21,0x03,0x00] +0x06,0x10,0xa3,0x00 == srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00] +0x26,0x18,0x65,0x00 == xor $3, $3, $5 # encoding: [0x26,0x18,0x65,0x00] +0x67,0x45,0xc9,0x38 == xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38] +0x67,0x45,0xc9,0x38 == xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38] +0x0c,0x00,0x6b,0x39 == xori $11, $11, 12 # encoding: [0x0c,0x00,0x6b,0x39] +0xa0,0x30,0x07,0x7c == wsbh $6, $7 # encoding: [0xa0,0x30,0x07,0x7c] +0x27,0x38,0x00,0x01 == not $7, $8 # encoding: [0x27,0x38,0x00,0x01] +0x20,0x48,0xc7,0x00 == add $9, $6, $7 # encoding: [0x20,0x48,0xc7,0x00] +0x67,0x45,0xc9,0x20 == addi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x20] +0x67,0xc5,0xc9,0x24 == addiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x24] +0x67,0x45,0xc9,0x20 == addi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x20] +0x67,0x45,0x29,0x21 == addi $9, $9, 17767 # encoding: [0x67,0x45,0x29,0x21] +0x67,0xc5,0xc9,0x24 == addiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x24] +0x28,0x00,0x6b,0x25 == addiu $11, $11, 40 # encoding: [0x28,0x00,0x6b,0x25] +0x21,0x48,0xc7,0x00 == addu $9, $6, $7 # encoding: [0x21,0x48,0xc7,0x00] +0x00,0x00,0xc7,0x70 == madd $6, $7 # encoding: [0x00,0x00,0xc7,0x70] +0x01,0x00,0xc7,0x70 == maddu $6, $7 # encoding: [0x01,0x00,0xc7,0x70] +0x04,0x00,0xc7,0x70 == msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70] +0x05,0x00,0xc7,0x70 == msubu $6, $7 # encoding: [0x05,0x00,0xc7,0x70] +0x18,0x00,0x65,0x00 == mult $3, $5 # encoding: [0x18,0x00,0x65,0x00] +0x19,0x00,0x65,0x00 == multu $3, $5 # encoding: [0x19,0x00,0x65,0x00] +0x22,0x48,0xc7,0x00 == sub $9, $6, $7 # encoding: [0x22,0x48,0xc7,0x00] +0xc8,0xff,0xbd,0x23 == addi $sp, $sp, -56 # encoding: [0xc8,0xff,0xbd,0x23] +0x23,0x20,0x65,0x00 == subu $4, $3, $5 # encoding: [0x23,0x20,0x65,0x00] +0xd8,0xff,0xbd,0x27 == addiu $sp, $sp, -40 # encoding: [0xd8,0xff,0xbd,0x27] +0x22,0x30,0x07,0x00 == neg $6, $7 # encoding: [0x22,0x30,0x07,0x00] +0x23,0x30,0x07,0x00 == negu $6, $7 # encoding: [0x23,0x30,0x07,0x00] +0x25,0x38,0x00,0x01 == move $7, $8 # encoding: [0x25,0x38,0x00,0x01] +0x3b,0xe8,0x05,0x7c == .set pop # encoding: [0x3b,0xe8,0x05,0x7c] +0x20,0x48,0x23,0x01 == add $9, $9, $3 # encoding: [0x20,0x48,0x23,0x01] +0x21,0x48,0x23,0x01 == addu $9, $9, $3 # encoding: [0x21,0x48,0x23,0x01] +0x0a,0x00,0x29,0x21 == addi $9, $9, 10 # encoding: [0x0a,0x00,0x29,0x21] +0x0a,0x00,0x29,0x25 == addiu $9, $9, 10 # encoding: [0x0a,0x00,0x29,0x25] +0x24,0x28,0xa6,0x00 == and $5, $5, $6 # encoding: [0x24,0x28,0xa6,0x00] +0x02,0x48,0x23,0x71 == mul $9, $9, $3 # encoding: [0x02,0x48,0x23,0x71] +0x25,0x10,0x44,0x00 == or $2, $2, $4 # encoding: [0x25,0x10,0x44,0x00] +0x22,0x48,0x23,0x01 == sub $9, $9, $3 # encoding: [0x22,0x48,0x23,0x01] +0x23,0x48,0x23,0x01 == subu $9, $9, $3 # encoding: [0x23,0x48,0x23,0x01] +0xf6,0xff,0x29,0x21 == addi $9, $9, -10 # encoding: [0xf6,0xff,0x29,0x21] +0xf6,0xff,0x29,0x25 == addiu $9, $9, -10 # encoding: [0xf6,0xff,0x29,0x25] +0x26,0x48,0x2a,0x01 == xor $9, $9, $10 # encoding: [0x26,0x48,0x2a,0x01] diff --git a/suite/MC/Mips/mips-control-instructions-64.s.cs b/suite/MC/Mips/mips-control-instructions-64.s.cs index c3478da19b..a0ed98c773 100644 --- a/suite/MC/Mips/mips-control-instructions-64.s.cs +++ b/suite/MC/Mips/mips-control-instructions-64.s.cs @@ -1,4 +1,4 @@ -# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None +# CS_ARCH_MIPS, CS_MODE_MIPS64R2+CS_MODE_BIG_ENDIAN, None 0x00,0x00,0x00,0x0d = break // 0x00,0x07,0x00,0x0d = break 7, 0 0x00,0x07,0x01,0x4d = break 7, 5 diff --git a/suite/MC/Mips/mips-control-instructions.s.cs b/suite/MC/Mips/mips-control-instructions.s.cs index 86c4ad82e6..d2442f214e 100644 --- a/suite/MC/Mips/mips-control-instructions.s.cs +++ b/suite/MC/Mips/mips-control-instructions.s.cs @@ -1,4 +1,4 @@ -# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +# CS_ARCH_MIPS, CS_MODE_MIPS32R2+CS_MODE_BIG_ENDIAN, None 0x00,0x00,0x00,0x0d = break // 0x00,0x07,0x00,0x0d = break 7, 0 0x00,0x07,0x01,0x4d = break 7, 5 diff --git a/suite/MC/Mips/mips-coprocessor-encodings.s.cs b/suite/MC/Mips/mips-coprocessor-encodings.s.cs index d14ddc3bae..c343c9a8f9 100644 --- a/suite/MC/Mips/mips-coprocessor-encodings.s.cs +++ b/suite/MC/Mips/mips-coprocessor-encodings.s.cs @@ -1,17 +1,17 @@ # CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None -0x40,0xac,0x80,0x02 = dmtc0 $t4, $s0, 2 -0x40,0xac,0x80,0x00 = dmtc0 $t4, $s0, 0 -0x40,0x8c,0x80,0x02 = mtc0 $t4, $s0, 2 -0x40,0x8c,0x80,0x00 = mtc0 $t4, $s0, 0 -0x40,0x2c,0x80,0x02 = dmfc0 $t4, $s0, 2 -0x40,0x2c,0x80,0x00 = dmfc0 $t4, $s0, 0 -0x40,0x0c,0x80,0x02 = mfc0 $t4, $s0, 2 -0x40,0x0c,0x80,0x00 = mfc0 $t4, $s0, 0 -0x48,0xac,0x80,0x02 = dmtc2 $t4, $s0, 2 -0x48,0xac,0x80,0x00 = dmtc2 $t4, $s0, 0 -0x48,0x8c,0x80,0x02 = mtc2 $t4, $s0, 2 -0x48,0x8c,0x80,0x00 = mtc2 $t4, $s0, 0 -0x48,0x2c,0x80,0x02 = dmfc2 $t4, $s0, 2 -0x48,0x2c,0x80,0x00 = dmfc2 $t4, $s0, 0 -0x48,0x0c,0x80,0x02 = mfc2 $t4, $s0, 2 -0x48,0x0c,0x80,0x00 = mfc2 $t4, $s0, 0 +0x40,0xac,0x80,0x02 = dmtc0 $t4, $16, 2 +0x40,0xac,0x80,0x00 = dmtc0 $t4, $16, 0 +0x40,0x8c,0x80,0x02 = mtc0 $t4, $16, 2 +0x40,0x8c,0x80,0x00 = mtc0 $t4, $16, 0 +0x40,0x2c,0x80,0x02 = dmfc0 $t4, $16, 2 +0x40,0x2c,0x80,0x00 = dmfc0 $t4, $16, 0 +0x40,0x0c,0x80,0x02 = mfc0 $t4, $16, 2 +0x40,0x0c,0x80,0x00 = mfc0 $t4, $16, 0 +0x48,0xac,0x80,0x02 = dmtc2 $t4, $16, 2 +0x48,0xac,0x80,0x00 = dmtc2 $t4, $16, 0 +0x48,0x8c,0x80,0x02 = mtc2 $t4, $16, 2 +0x48,0x8c,0x80,0x00 = mtc2 $t4, $16, 0 +0x48,0x2c,0x80,0x02 = dmfc2 $t4, $16, 2 +0x48,0x2c,0x80,0x00 = dmfc2 $t4, $16, 0 +0x48,0x0c,0x80,0x02 = mfc2 $t4, $16, 2 +0x48,0x0c,0x80,0x00 = mfc2 $t4, $16, 0 diff --git a/suite/MC/Mips/mips-fpu-instructions.s.cs b/suite/MC/Mips/mips-fpu-instructions.s.cs index 335cd0f2e5..c3a922d79f 100644 --- a/suite/MC/Mips/mips-fpu-instructions.s.cs +++ b/suite/MC/Mips/mips-fpu-instructions.s.cs @@ -1,93 +1,94 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32, None -0x05,0x73,0x20,0x46 = abs.d $f12, $f14 -0x85,0x39,0x00,0x46 = abs.s $f6, $f7 -0x00,0x62,0x2e,0x46 = add.d $f8, $f12, $f14 -0x40,0x32,0x07,0x46 = add.s $f9, $f6, $f7 -0x0f,0x73,0x20,0x46 = floor.w.d $f12, $f14 -0x8f,0x39,0x00,0x46 = floor.w.s $f6, $f7 -0x0e,0x73,0x20,0x46 = ceil.w.d $f12, $f14 -0x8e,0x39,0x00,0x46 = ceil.w.s $f6, $f7 -0x02,0x62,0x2e,0x46 = mul.d $f8, $f12, $f14 -0x42,0x32,0x07,0x46 = mul.s $f9, $f6, $f7 -0x07,0x73,0x20,0x46 = neg.d $f12, $f14 -0x87,0x39,0x00,0x46 = neg.s $f6, $f7 -0x0c,0x73,0x20,0x46 = round.w.d $f12, $f14 -0x8c,0x39,0x00,0x46 = round.w.s $f6, $f7 -0x04,0x73,0x20,0x46 = sqrt.d $f12, $f14 -0x84,0x39,0x00,0x46 = sqrt.s $f6, $f7 -0x01,0x62,0x2e,0x46 = sub.d $f8, $f12, $f14 -0x41,0x32,0x07,0x46 = sub.s $f9, $f6, $f7 -0x0d,0x73,0x20,0x46 = trunc.w.d $f12, $f14 -0x8d,0x39,0x00,0x46 = trunc.w.s $f6, $f7 -0x32,0x60,0x2e,0x46 = c.eq.d $f12, $f14 -0x32,0x30,0x07,0x46 = c.eq.s $f6, $f7 -0x30,0x60,0x2e,0x46 = c.f.d $f12, $f14 -0x30,0x30,0x07,0x46 = c.f.s $f6, $f7 -0x3e,0x60,0x2e,0x46 = c.le.d $f12, $f14 -0x3e,0x30,0x07,0x46 = c.le.s $f6, $f7 -0x3c,0x60,0x2e,0x46 = c.lt.d $f12, $f14 -0x3c,0x30,0x07,0x46 = c.lt.s $f6, $f7 -0x3d,0x60,0x2e,0x46 = c.nge.d $f12, $f14 -0x3d,0x30,0x07,0x46 = c.nge.s $f6, $f7 -0x3b,0x60,0x2e,0x46 = c.ngl.d $f12, $f14 -0x3b,0x30,0x07,0x46 = c.ngl.s $f6, $f7 -0x39,0x60,0x2e,0x46 = c.ngle.d $f12, $f14 -0x39,0x30,0x07,0x46 = c.ngle.s $f6, $f7 -0x3f,0x60,0x2e,0x46 = c.ngt.d $f12, $f14 -0x3f,0x30,0x07,0x46 = c.ngt.s $f6, $f7 -0x36,0x60,0x2e,0x46 = c.ole.d $f12, $f14 -0x36,0x30,0x07,0x46 = c.ole.s $f6, $f7 -0x34,0x60,0x2e,0x46 = c.olt.d $f12, $f14 -0x34,0x30,0x07,0x46 = c.olt.s $f6, $f7 -0x3a,0x60,0x2e,0x46 = c.seq.d $f12, $f14 -0x3a,0x30,0x07,0x46 = c.seq.s $f6, $f7 -0x38,0x60,0x2e,0x46 = c.sf.d $f12, $f14 -0x38,0x30,0x07,0x46 = c.sf.s $f6, $f7 -0x33,0x60,0x2e,0x46 = c.ueq.d $f12, $f14 -0x33,0xe0,0x12,0x46 = c.ueq.s $f28, $f18 -0x37,0x60,0x2e,0x46 = c.ule.d $f12, $f14 -0x37,0x30,0x07,0x46 = c.ule.s $f6, $f7 -0x35,0x60,0x2e,0x46 = c.ult.d $f12, $f14 -0x35,0x30,0x07,0x46 = c.ult.s $f6, $f7 -0x31,0x60,0x2e,0x46 = c.un.d $f12, $f14 -0x31,0x30,0x07,0x46 = c.un.s $f6, $f7 -0xa1,0x39,0x00,0x46 = cvt.d.s $f6, $f7 -0x21,0x73,0x80,0x46 = cvt.d.w $f12, $f14 -0x20,0x73,0x20,0x46 = cvt.s.d $f12, $f14 -0xa0,0x39,0x80,0x46 = cvt.s.w $f6, $f7 -0x24,0x73,0x20,0x46 = cvt.w.d $f12, $f14 -0xa4,0x39,0x00,0x46 = cvt.w.s $f6, $f7 -0x00,0x00,0x46,0x44 = cfc1 $a2, $0 -0x00,0xf8,0xca,0x44 = ctc1 $t2, $31 -0x00,0x38,0x06,0x44 = mfc1 $a2, $f7 -0x10,0x28,0x00,0x00 = mfhi $a1 -0x12,0x28,0x00,0x00 = mflo $a1 -0x86,0x41,0x20,0x46 = mov.d $f6, $f8 -0x86,0x39,0x00,0x46 = mov.s $f6, $f7 -0x00,0x38,0x86,0x44 = mtc1 $a2, $f7 -0x11,0x00,0xe0,0x00 = mthi $a3 -0x13,0x00,0xe0,0x00 = mtlo $a3 -0xc6,0x23,0xe9,0xe4 = swc1 $f9, 9158($a3) -0x00,0x38,0x06,0x40 = mfc0 $a2, $a3, 0 -0x00,0x40,0x89,0x40 = mtc0 $t1, $t0, 0 -0x00,0x38,0x05,0x48 = mfc2 $a1, $a3, 0 -0x00,0x20,0x89,0x48 = mtc2 $t1, $a0, 0 -0x02,0x38,0x06,0x40 = mfc0 $a2, $a3, 2 -0x03,0x40,0x89,0x40 = mtc0 $t1, $t0, 3 -0x04,0x38,0x05,0x48 = mfc2 $a1, $a3, 4 -0x05,0x20,0x89,0x48 = mtc2 $t1, $a0, 5 -0x01,0x10,0x20,0x00 = movf $v0, $at, $fcc0 -0x01,0x10,0x21,0x00 = movt $v0, $at, $fcc0 -0x01,0x20,0xb1,0x00 = movt $a0, $a1, $fcc4 -0x11,0x31,0x28,0x46 = movf.d $f4, $f6, $fcc2 -0x11,0x31,0x14,0x46 = movf.s $f4, $f6, $fcc5 -0x05,0x00,0xa6,0x4c = luxc1 $f0, $a2($a1) -0x0d,0x20,0xb8,0x4c = suxc1 $f4, $t8($a1) -0x00,0x05,0xcc,0x4d = lwxc1 $f20, $t4($t6) -0x08,0xd0,0xd2,0x4e = swxc1 $f26, $s2($s6) -0x00,0x20,0x71,0x44 = mfhc1 $s1, $f4 -0x00,0x30,0xf1,0x44 = mthc1 $s1, $f6 -0x10,0x00,0xa4,0xeb = swc2 $4, 16($sp) -0x10,0x00,0xa4,0xfb = sdc2 $4, 16($sp) -0x0c,0x00,0xeb,0xcb = lwc2 $11, 12($ra) -0x0c,0x00,0xeb,0xdb = ldc2 $11, 12($ra) + +0x05,0x73,0x20,0x46 == abs.d $f12, $f14 # encoding: [0x05,0x73,0x20,0x46] +0x85,0x39,0x00,0x46 == abs.s $f6, $f7 # encoding: [0x85,0x39,0x00,0x46] +0x00,0x62,0x2e,0x46 == add.d $f8, $f12, $f14 # encoding: [0x00,0x62,0x2e,0x46] +0x40,0x32,0x07,0x46 == add.s $f9, $f6, $f7 # encoding: [0x40,0x32,0x07,0x46] +0x0f,0x73,0x20,0x46 == floor.w.d $f12, $f14 # encoding: [0x0f,0x73,0x20,0x46] +0x8f,0x39,0x00,0x46 == floor.w.s $f6, $f7 # encoding: [0x8f,0x39,0x00,0x46] +0x0e,0x73,0x20,0x46 == ceil.w.d $f12, $f14 # encoding: [0x0e,0x73,0x20,0x46] +0x8e,0x39,0x00,0x46 == ceil.w.s $f6, $f7 # encoding: [0x8e,0x39,0x00,0x46] +0x02,0x62,0x2e,0x46 == mul.d $f8, $f12, $f14 # encoding: [0x02,0x62,0x2e,0x46] +0x42,0x32,0x07,0x46 == mul.s $f9, $f6, $f7 # encoding: [0x42,0x32,0x07,0x46] +0x07,0x73,0x20,0x46 == neg.d $f12, $f14 # encoding: [0x07,0x73,0x20,0x46] +0x87,0x39,0x00,0x46 == neg.s $f6, $f7 # encoding: [0x87,0x39,0x00,0x46] +0x0c,0x73,0x20,0x46 == round.w.d $f12, $f14 # encoding: [0x0c,0x73,0x20,0x46] +0x8c,0x39,0x00,0x46 == round.w.s $f6, $f7 # encoding: [0x8c,0x39,0x00,0x46] +0x04,0x73,0x20,0x46 == sqrt.d $f12, $f14 # encoding: [0x04,0x73,0x20,0x46] +0x84,0x39,0x00,0x46 == sqrt.s $f6, $f7 # encoding: [0x84,0x39,0x00,0x46] +0x01,0x62,0x2e,0x46 == sub.d $f8, $f12, $f14 # encoding: [0x01,0x62,0x2e,0x46] +0x41,0x32,0x07,0x46 == sub.s $f9, $f6, $f7 # encoding: [0x41,0x32,0x07,0x46] +0x0d,0x73,0x20,0x46 == trunc.w.d $f12, $f14 # encoding: [0x0d,0x73,0x20,0x46] +0x8d,0x39,0x00,0x46 == trunc.w.s $f6, $f7 # encoding: [0x8d,0x39,0x00,0x46] +0x32,0x60,0x2e,0x46 == c.eq.d $f12, $f14 # encoding: [0x32,0x60,0x2e,0x46] +0x32,0x30,0x07,0x46 == c.eq.s $f6, $f7 # encoding: [0x32,0x30,0x07,0x46] +0x30,0x60,0x2e,0x46 == c.f.d $f12, $f14 # encoding: [0x30,0x60,0x2e,0x46] +0x30,0x30,0x07,0x46 == c.f.s $f6, $f7 # encoding: [0x30,0x30,0x07,0x46] +0x3e,0x60,0x2e,0x46 == c.le.d $f12, $f14 # encoding: [0x3e,0x60,0x2e,0x46] +0x3e,0x30,0x07,0x46 == c.le.s $f6, $f7 # encoding: [0x3e,0x30,0x07,0x46] +0x3c,0x60,0x2e,0x46 == c.lt.d $f12, $f14 # encoding: [0x3c,0x60,0x2e,0x46] +0x3c,0x30,0x07,0x46 == c.lt.s $f6, $f7 # encoding: [0x3c,0x30,0x07,0x46] +0x3d,0x60,0x2e,0x46 == c.nge.d $f12, $f14 # encoding: [0x3d,0x60,0x2e,0x46] +0x3d,0x30,0x07,0x46 == c.nge.s $f6, $f7 # encoding: [0x3d,0x30,0x07,0x46] +0x3b,0x60,0x2e,0x46 == c.ngl.d $f12, $f14 # encoding: [0x3b,0x60,0x2e,0x46] +0x3b,0x30,0x07,0x46 == c.ngl.s $f6, $f7 # encoding: [0x3b,0x30,0x07,0x46] +0x39,0x60,0x2e,0x46 == c.ngle.d $f12, $f14 # encoding: [0x39,0x60,0x2e,0x46] +0x39,0x30,0x07,0x46 == c.ngle.s $f6, $f7 # encoding: [0x39,0x30,0x07,0x46] +0x3f,0x60,0x2e,0x46 == c.ngt.d $f12, $f14 # encoding: [0x3f,0x60,0x2e,0x46] +0x3f,0x30,0x07,0x46 == c.ngt.s $f6, $f7 # encoding: [0x3f,0x30,0x07,0x46] +0x36,0x60,0x2e,0x46 == c.ole.d $f12, $f14 # encoding: [0x36,0x60,0x2e,0x46] +0x36,0x30,0x07,0x46 == c.ole.s $f6, $f7 # encoding: [0x36,0x30,0x07,0x46] +0x34,0x60,0x2e,0x46 == c.olt.d $f12, $f14 # encoding: [0x34,0x60,0x2e,0x46] +0x34,0x30,0x07,0x46 == c.olt.s $f6, $f7 # encoding: [0x34,0x30,0x07,0x46] +0x3a,0x60,0x2e,0x46 == c.seq.d $f12, $f14 # encoding: [0x3a,0x60,0x2e,0x46] +0x3a,0x30,0x07,0x46 == c.seq.s $f6, $f7 # encoding: [0x3a,0x30,0x07,0x46] +0x38,0x60,0x2e,0x46 == c.sf.d $f12, $f14 # encoding: [0x38,0x60,0x2e,0x46] +0x38,0x30,0x07,0x46 == c.sf.s $f6, $f7 # encoding: [0x38,0x30,0x07,0x46] +0x33,0x60,0x2e,0x46 == c.ueq.d $f12, $f14 # encoding: [0x33,0x60,0x2e,0x46] +0x33,0xe0,0x12,0x46 == c.ueq.s $f28, $f18 # encoding: [0x33,0xe0,0x12,0x46] +0x37,0x60,0x2e,0x46 == c.ule.d $f12, $f14 # encoding: [0x37,0x60,0x2e,0x46] +0x37,0x30,0x07,0x46 == c.ule.s $f6, $f7 # encoding: [0x37,0x30,0x07,0x46] +0x35,0x60,0x2e,0x46 == c.ult.d $f12, $f14 # encoding: [0x35,0x60,0x2e,0x46] +0x35,0x30,0x07,0x46 == c.ult.s $f6, $f7 # encoding: [0x35,0x30,0x07,0x46] +0x31,0x60,0x2e,0x46 == c.un.d $f12, $f14 # encoding: [0x31,0x60,0x2e,0x46] +0x31,0x30,0x07,0x46 == c.un.s $f6, $f7 # encoding: [0x31,0x30,0x07,0x46] +0xa1,0x39,0x00,0x46 == cvt.d.s $f6, $f7 # encoding: [0xa1,0x39,0x00,0x46] +0x21,0x73,0x80,0x46 == cvt.d.w $f12, $f14 # encoding: [0x21,0x73,0x80,0x46] +0x20,0x73,0x20,0x46 == cvt.s.d $f12, $f14 # encoding: [0x20,0x73,0x20,0x46] +0xa0,0x39,0x80,0x46 == cvt.s.w $f6, $f7 # encoding: [0xa0,0x39,0x80,0x46] +0x24,0x73,0x20,0x46 == cvt.w.d $f12, $f14 # encoding: [0x24,0x73,0x20,0x46] +0xa4,0x39,0x00,0x46 == cvt.w.s $f6, $f7 # encoding: [0xa4,0x39,0x00,0x46] +0x00,0x00,0x46,0x44 == cfc1 $6, $0 # encoding: [0x00,0x00,0x46,0x44] +0x00,0xf8,0xca,0x44 == ctc1 $10, $31 # encoding: [0x00,0xf8,0xca,0x44] +0x00,0x38,0x06,0x44 == mfc1 $6, $f7 # encoding: [0x00,0x38,0x06,0x44] +0x10,0x28,0x00,0x00 == mfhi $5 # encoding: [0x10,0x28,0x00,0x00] +0x12,0x28,0x00,0x00 == mflo $5 # encoding: [0x12,0x28,0x00,0x00] +0x86,0x41,0x20,0x46 == mov.d $f6, $f8 # encoding: [0x86,0x41,0x20,0x46] +0x86,0x39,0x00,0x46 == mov.s $f6, $f7 # encoding: [0x86,0x39,0x00,0x46] +0x00,0x38,0x86,0x44 == mtc1 $6, $f7 # encoding: [0x00,0x38,0x86,0x44] +0x11,0x00,0xe0,0x00 == mthi $7 # encoding: [0x11,0x00,0xe0,0x00] +0x13,0x00,0xe0,0x00 == mtlo $7 # encoding: [0x13,0x00,0xe0,0x00] +0xc6,0x23,0xe9,0xe4 == swc1 $f9, 9158($7) # encoding: [0xc6,0x23,0xe9,0xe4] +0x00,0x38,0x06,0x40 == mfc0 $6, $7, 0 # encoding: [0x00,0x38,0x06,0x40] +0x00,0x40,0x89,0x40 == mtc0 $9, $8, 0 # encoding: [0x00,0x40,0x89,0x40] +0x00,0x38,0x05,0x48 == mfc2 $5, $7, 0 # encoding: [0x00,0x38,0x05,0x48] +0x00,0x20,0x89,0x48 == mtc2 $9, $4, 0 # encoding: [0x00,0x20,0x89,0x48] +0x02,0x38,0x06,0x40 == mfc0 $6, $7, 2 # encoding: [0x02,0x38,0x06,0x40] +0x03,0x40,0x89,0x40 == mtc0 $9, $8, 3 # encoding: [0x03,0x40,0x89,0x40] +0x04,0x38,0x05,0x48 == mfc2 $5, $7, 4 # encoding: [0x04,0x38,0x05,0x48] +0x05,0x20,0x89,0x48 == mtc2 $9, $4, 5 # encoding: [0x05,0x20,0x89,0x48] +0x01,0x10,0x20,0x00 == movf $2, $1, $fcc0 # encoding: [0x01,0x10,0x20,0x00] +0x01,0x10,0x21,0x00 == movt $2, $1, $fcc0 # encoding: [0x01,0x10,0x21,0x00] +0x01,0x20,0xb1,0x00 == movt $4, $5, $fcc4 # encoding: [0x01,0x20,0xb1,0x00] +0x11,0x31,0x28,0x46 == movf.d $f4, $f6, $fcc2 # encoding: [0x11,0x31,0x28,0x46] +0x11,0x31,0x14,0x46 == movf.s $f4, $f6, $fcc5 # encoding: [0x11,0x31,0x14,0x46] +0x05,0x00,0xa6,0x4c == luxc1 $f0, $6($5) # encoding: [0x05,0x00,0xa6,0x4c] +0x0d,0x20,0xb8,0x4c == suxc1 $f4, $24($5) # encoding: [0x0d,0x20,0xb8,0x4c] +0x00,0x05,0xcc,0x4d == lwxc1 $f20, $12($14) # encoding: [0x00,0x05,0xcc,0x4d] +0x08,0xd0,0xd2,0x4e == swxc1 $f26, $18($22) # encoding: [0x08,0xd0,0xd2,0x4e] +0x00,0x20,0x71,0x44 == mfhc1 $17, $f4 # encoding: [0x00,0x20,0x71,0x44] +0x00,0x30,0xf1,0x44 == mthc1 $17, $f6 # encoding: [0x00,0x30,0xf1,0x44] +0x10,0x00,0xa4,0xeb == swc2 $4, 16($sp) # encoding: [0x10,0x00,0xa4,0xeb] +0x10,0x00,0xa4,0xfb == sdc2 $4, 16($sp) # encoding: [0x10,0x00,0xa4,0xfb] +0x0c,0x00,0xeb,0xcb == lwc2 $11, 12($ra) # encoding: [0x0c,0x00,0xeb,0xcb] +0x0c,0x00,0xeb,0xdb == ldc2 $11, 12($ra) # encoding: [0x0c,0x00,0xeb,0xdb] diff --git a/suite/MC/Mips/mips-memory-instructions.s.cs b/suite/MC/Mips/mips-memory-instructions.s.cs index ac5b3605cb..365cae95ee 100644 --- a/suite/MC/Mips/mips-memory-instructions.s.cs +++ b/suite/MC/Mips/mips-memory-instructions.s.cs @@ -1,17 +1,18 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32, None -0x10,0x00,0xa4,0xa0 = sb $a0, 16($a1) -0x10,0x00,0xa4,0xe0 = sc $a0, 16($a1) -0x10,0x00,0xa4,0xa4 = sh $a0, 16($a1) -0x10,0x00,0xa4,0xac = sw $a0, 16($a1) -0x00,0x00,0xa7,0xac = sw $a3, ($a1) -0x10,0x00,0xa2,0xe4 = swc1 $f2, 16($a1) -0x10,0x00,0xa4,0xa8 = swl $a0, 16($a1) -0x04,0x00,0xa4,0x80 = lb $a0, 4($a1) -0x04,0x00,0xa4,0x8c = lw $a0, 4($a1) -0x04,0x00,0xa4,0x90 = lbu $a0, 4($a1) -0x04,0x00,0xa4,0x84 = lh $a0, 4($a1) -0x04,0x00,0xa4,0x94 = lhu $a0, 4($a1) -0x04,0x00,0xa4,0xc0 = ll $a0, 4($a1) -0x04,0x00,0xa4,0x8c = lw $a0, 4($a1) -0x00,0x00,0xe7,0x8c = lw $a3, ($a3) -0x10,0x00,0xa2,0x8f = lw $v0, 16($sp) + +0x10,0x00,0xa4,0xa0 == sb $4, 16($5) # encoding: [0x10,0x00,0xa4,0xa0] +0x10,0x00,0xa4,0xe0 == sc $4, 16($5) # encoding: [0x10,0x00,0xa4,0xe0] +0x10,0x00,0xa4,0xa4 == sh $4, 16($5) # encoding: [0x10,0x00,0xa4,0xa4] +0x10,0x00,0xa4,0xac == sw $4, 16($5) # encoding: [0x10,0x00,0xa4,0xac] +0x00,0x00,0xa7,0xac == sw $7, 0($5) # encoding: [0x00,0x00,0xa7,0xac] +0x10,0x00,0xa2,0xe4 == swc1 $f2, 16($5) # encoding: [0x10,0x00,0xa2,0xe4] +0x10,0x00,0xa4,0xa8 == swl $4, 16($5) # encoding: [0x10,0x00,0xa4,0xa8] +0x04,0x00,0xa4,0x80 == lb $4, 4($5) # encoding: [0x04,0x00,0xa4,0x80] +0x04,0x00,0xa4,0x8c == lw $4, 4($5) # encoding: [0x04,0x00,0xa4,0x8c] +0x04,0x00,0xa4,0x90 == lbu $4, 4($5) # encoding: [0x04,0x00,0xa4,0x90] +0x04,0x00,0xa4,0x84 == lh $4, 4($5) # encoding: [0x04,0x00,0xa4,0x84] +0x04,0x00,0xa4,0x94 == lhu $4, 4($5) # encoding: [0x04,0x00,0xa4,0x94] +0x04,0x00,0xa4,0xc0 == ll $4, 4($5) # encoding: [0x04,0x00,0xa4,0xc0] +0x04,0x00,0xa4,0x8c == lw $4, 4($5) # encoding: [0x04,0x00,0xa4,0x8c] +0x00,0x00,0xe7,0x8c == lw $7, 0($7) # encoding: [0x00,0x00,0xe7,0x8c] +0x10,0x00,0xa2,0x8f == lw $2, 16($sp) # encoding: [0x10,0x00,0xa2,0x8f] diff --git a/suite/MC/Mips/mips64-alu-instructions.s.cs b/suite/MC/Mips/mips64-alu-instructions.s.cs index eeac44e5e2..aa50b816a7 100644 --- a/suite/MC/Mips/mips64-alu-instructions.s.cs +++ b/suite/MC/Mips/mips64-alu-instructions.s.cs @@ -1,47 +1,66 @@ # CS_ARCH_MIPS, CS_MODE_MIPS64, None -0x24,0x48,0xc7,0x00 = and $t1, $a2, $a3 -0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767 -0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767 -0x21,0x30,0xe6,0x70 = clo $a2, $a3 -0x20,0x30,0xe6,0x70 = clz $a2, $a3 -0x84,0x61,0x33,0x7d = ins $s3, $t1, 6, 7 -0x27,0x48,0xc7,0x00 = nor $t1, $a2, $a3 -0x25,0x18,0x65,0x00 = or $v1, $v1, $a1 -0x67,0x45,0xa4,0x34 = ori $a0, $a1, 17767 -0x67,0x45,0xc9,0x34 = ori $t1, $a2, 17767 -0xc2,0x49,0x26,0x00 = rotr $t1, $a2, 7 -0x46,0x48,0xe6,0x00 = rotrv $t1, $a2, $a3 -0xc0,0x21,0x03,0x00 = sll $a0, $v1, 7 -0x04,0x10,0xa3,0x00 = sllv $v0, $v1, $a1 -0x2a,0x18,0x65,0x00 = slt $v1, $v1, $a1 -0x67,0x00,0x63,0x28 = slti $v1, $v1, 103 -0x67,0x00,0x63,0x28 = slti $v1, $v1, 103 -0x67,0x00,0x63,0x2c = sltiu $v1, $v1, 103 -0x2b,0x18,0x65,0x00 = sltu $v1, $v1, $a1 -0xc3,0x21,0x03,0x00 = sra $a0, $v1, 7 -0x07,0x10,0xa3,0x00 = srav $v0, $v1, $a1 -0xc2,0x21,0x03,0x00 = srl $a0, $v1, 7 -0x06,0x10,0xa3,0x00 = srlv $v0, $v1, $a1 -0x26,0x18,0x65,0x00 = xor $v1, $v1, $a1 -0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767 -0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767 -0xa0,0x30,0x07,0x7c = wsbh $a2, $a3 -0x27,0x38,0x00,0x01 = not $a3, $t0 -0x2c,0x48,0xc7,0x00 = dadd $t1, $a2, $a3 -0x67,0x45,0xc9,0x60 = daddi $t1, $a2, 17767 -0x67,0xc5,0xc9,0x64 = daddiu $t1, $a2, -15001 -0x67,0x45,0xc9,0x60 = daddi $t1, $a2, 17767 -0x67,0x45,0x29,0x61 = daddi $t1, $t1, 17767 -0x67,0xc5,0xc9,0x64 = daddiu $t1, $a2, -15001 -0x67,0xc5,0x29,0x65 = daddiu $t1, $t1, -15001 -0x2d,0x48,0xc7,0x00 = daddu $t1, $a2, $a3 -0x3a,0x4d,0x26,0x00 = drotr $t1, $a2, 20 -// 0x3e,0x4d,0x26,0x00 = drotr32 $t1, $a2, 52 -0x00,0x00,0xc7,0x70 = madd $a2, $a3 -0x01,0x00,0xc7,0x70 = maddu $a2, $a3 -0x04,0x00,0xc7,0x70 = msub $a2, $a3 -0x05,0x00,0xc7,0x70 = msubu $a2, $a3 -0x18,0x00,0x65,0x00 = mult $v1, $a1 -0x19,0x00,0x65,0x00 = multu $v1, $a1 -0x2f,0x20,0x65,0x00 = dsubu $a0, $v1, $a1 -0x2d,0x38,0x00,0x01 = move $a3, $t0 + +0x24,0x48,0xc7,0x00 == and $9, $6, $7 # encoding: [0x24,0x48,0xc7,0x00] +0x67,0x45,0xc9,0x30 == andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30] +0x67,0x45,0xc9,0x30 == andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30] +0x21,0x30,0xe6,0x70 == clo $6, $7 # encoding: [0x21,0x30,0xe6,0x70] +0x20,0x30,0xe6,0x70 == clz $6, $7 # encoding: [0x20,0x30,0xe6,0x70] +0x84,0x61,0x33,0x7d == ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d] +0x27,0x48,0xc7,0x00 == nor $9, $6, $7 # encoding: [0x27,0x48,0xc7,0x00] +0x25,0x18,0x65,0x00 == or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00] +0x67,0x45,0xa4,0x34 == ori $4, $5, 17767 # encoding: [0x67,0x45,0xa4,0x34] +0x67,0x45,0xc9,0x34 == ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34] +0xc2,0x49,0x26,0x00 == rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00] +0x46,0x48,0xe6,0x00 == rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00] +0xc0,0x21,0x03,0x00 == sll $4, $3, 7 # encoding: [0xc0,0x21,0x03,0x00] +0x04,0x10,0xa3,0x00 == sllv $2, $3, $5 # encoding: [0x04,0x10,0xa3,0x00] +0x2a,0x18,0x65,0x00 == slt $3, $3, $5 # encoding: [0x2a,0x18,0x65,0x00] +0x67,0x00,0x63,0x28 == slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28] +0x67,0x00,0x63,0x28 == slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28] +0x67,0x00,0x63,0x2c == sltiu $3, $3, 103 # encoding: [0x67,0x00,0x63,0x2c] +0x2b,0x18,0x65,0x00 == sltu $3, $3, $5 # encoding: [0x2b,0x18,0x65,0x00] +0xc3,0x21,0x03,0x00 == sra $4, $3, 7 # encoding: [0xc3,0x21,0x03,0x00] +0x07,0x10,0xa3,0x00 == srav $2, $3, $5 # encoding: [0x07,0x10,0xa3,0x00] +0xc2,0x21,0x03,0x00 == srl $4, $3, 7 # encoding: [0xc2,0x21,0x03,0x00] +0x06,0x10,0xa3,0x00 == srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00] +0x26,0x18,0x65,0x00 == xor $3, $3, $5 # encoding: [0x26,0x18,0x65,0x00] +0x67,0x45,0xc9,0x38 == xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38] +0x67,0x45,0xc9,0x38 == xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38] +0xa0,0x30,0x07,0x7c == wsbh $6, $7 # encoding: [0xa0,0x30,0x07,0x7c] +0x27,0x38,0x00,0x01 == not $7, $8 # encoding: [0x27,0x38,0x00,0x01] +0x2c,0x48,0xc7,0x00 == dadd $9, $6, $7 # encoding: [0x2c,0x48,0xc7,0x00] +0x67,0x45,0xc9,0x60 == daddi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x60] +0x67,0xc5,0xc9,0x64 == daddiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x64] +0x67,0x45,0xc9,0x60 == daddi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x60] +0x67,0x45,0x29,0x61 == daddi $9, $9, 17767 # encoding: [0x67,0x45,0x29,0x61] +0x67,0xc5,0xc9,0x64 == daddiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x64] +0x67,0xc5,0x29,0x65 == daddiu $9, $9, -15001 # encoding: [0x67,0xc5,0x29,0x65] +0x2d,0x48,0xc7,0x00 == daddu $9, $6, $7 # encoding: [0x2d,0x48,0xc7,0x00] +0x3a,0x4d,0x26,0x00 == drotr $9, $6, 20 # encoding: [0x3a,0x4d,0x26,0x00] +0x3e,0x4d,0x26,0x00 == drotr32 $9, $6, 20 # encoding: [0x3e,0x4d,0x26,0x00] +0x00,0x00,0xc7,0x70 == madd $6, $7 # encoding: [0x00,0x00,0xc7,0x70] +0x01,0x00,0xc7,0x70 == maddu $6, $7 # encoding: [0x01,0x00,0xc7,0x70] +0x04,0x00,0xc7,0x70 == msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70] +0x05,0x00,0xc7,0x70 == msubu $6, $7 # encoding: [0x05,0x00,0xc7,0x70] +0x18,0x00,0x65,0x00 == mult $3, $5 # encoding: [0x18,0x00,0x65,0x00] +0x19,0x00,0x65,0x00 == multu $3, $5 # encoding: [0x19,0x00,0x65,0x00] +0x2e,0x48,0xc7,0x00 == dsub $9, $6, $7 # encoding: [0x2e,0x48,0xc7,0x00] +0x2f,0x20,0x65,0x00 == dsubu $4, $3, $5 # encoding: [0x2f,0x20,0x65,0x00] +0x99,0xba,0xc9,0x64 == daddiu $9, $6, -17767 # encoding: [0x99,0xba,0xc9,0x64] +0x25,0x38,0x00,0x01 == move $7, $8 # encoding: [0x25,0x38,0x00,0x01] +0x3b,0xe8,0x05,0x7c == .set pop # encoding: [0x3b,0xe8,0x05,0x7c] +0x24,0x48,0x23,0x01 == and $9, $9, $3 # encoding: [0x24,0x48,0x23,0x01] +0x2c,0x48,0x23,0x01 == dadd $9, $9, $3 # encoding: [0x2c,0x48,0x23,0x01] +0x2d,0x48,0x23,0x01 == daddu $9, $9, $3 # encoding: [0x2d,0x48,0x23,0x01] +0x0a,0x00,0x29,0x61 == daddi $9, $9, 10 # encoding: [0x0a,0x00,0x29,0x61] +0x0a,0x00,0x29,0x65 == daddiu $9, $9, 10 # encoding: [0x0a,0x00,0x29,0x65] +0x2e,0x48,0x23,0x01 == dsub $9, $9, $3 # encoding: [0x2e,0x48,0x23,0x01] +0x2f,0x48,0x23,0x01 == dsubu $9, $9, $3 # encoding: [0x2f,0x48,0x23,0x01] +0xf6,0xff,0x29,0x61 == daddi $9, $9, -10 # encoding: [0xf6,0xff,0x29,0x61] +0xf6,0xff,0x29,0x65 == daddiu $9, $9, -10 # encoding: [0xf6,0xff,0x29,0x65] +0x25,0x48,0x23,0x01 == or $9, $9, $3 # encoding: [0x25,0x48,0x23,0x01] +0x26,0x48,0x23,0x01 == xor $9, $9, $3 # encoding: [0x26,0x48,0x23,0x01] +0x20,0x00,0x69,0x64 == daddiu $9, $3, 32 # encoding: [0x20,0x00,0x69,0x64] +0x20,0x00,0x69,0x64 == daddiu $9, $3, 32 # encoding: [0x20,0x00,0x69,0x64] +0xe0,0xff,0x69,0x64 == daddiu $9, $3, -32 # encoding: [0xe0,0xff,0x69,0x64] +0xe0,0xff,0x69,0x64 == daddiu $9, $3, -32 # encoding: [0xe0,0xff,0x69,0x64] diff --git a/suite/MC/Mips/mips64-instructions.s.cs b/suite/MC/Mips/mips64-instructions.s.cs index be7cc23a11..85fe34a7d5 100644 --- a/suite/MC/Mips/mips64-instructions.s.cs +++ b/suite/MC/Mips/mips64-instructions.s.cs @@ -1,3 +1,4 @@ # CS_ARCH_MIPS, CS_MODE_MIPS64, None -0x81,0x00,0x42,0x4d = ldxc1 $f2, $v0($t2) -0x09,0x40,0x24,0x4f = sdxc1 $f8, $a0($t9) + +0x81,0x00,0x42,0x4d == ldxc1 $f2, $2($10) # encoding: [0x81,0x00,0x42,0x4d] +0x09,0x40,0x24,0x4f == sdxc1 $f8, $4($25) # encoding: [0x09,0x40,0x24,0x4f] diff --git a/suite/MC/Mips/mips64-register-names-n32-n64.s.cs b/suite/MC/Mips/mips64-register-names-n32-n64.s.cs new file mode 100644 index 0000000000..29ae367ab0 --- /dev/null +++ b/suite/MC/Mips/mips64-register-names-n32-n64.s.cs @@ -0,0 +1,33 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None +0x64,0x00,0x00,0x00 == daddiu $zero, $zero, 0 # encoding: [0x64,0x00,0x00,0x00] +0x64,0x01,0x00,0x00 == daddiu $at, $zero, 0 # encoding: [0x64,0x01,0x00,0x00] +0x64,0x02,0x00,0x00 == daddiu $v0, $zero, 0 # encoding: [0x64,0x02,0x00,0x00] +0x64,0x03,0x00,0x00 == daddiu $v1, $zero, 0 # encoding: [0x64,0x03,0x00,0x00] +0x64,0x04,0x00,0x00 == daddiu $a0, $zero, 0 # encoding: [0x64,0x04,0x00,0x00] +0x64,0x05,0x00,0x00 == daddiu $a1, $zero, 0 # encoding: [0x64,0x05,0x00,0x00] +0x64,0x06,0x00,0x00 == daddiu $a2, $zero, 0 # encoding: [0x64,0x06,0x00,0x00] +0x64,0x07,0x00,0x00 == daddiu $a2, $zero, 0 # encoding: [0x64,0x07,0x00,0x00] +0x64,0x08,0x00,0x00 == daddiu $a4, $zero, 0 # encoding: [0x64,0x08,0x00,0x00] +0x64,0x09,0x00,0x00 == daddiu $a5, $zero, 0 # encoding: [0x64,0x09,0x00,0x00] +0x64,0x0a,0x00,0x00 == daddiu $a6, $zero, 0 # encoding: [0x64,0x0a,0x00,0x00] +0x64,0x0b,0x00,0x00 == daddiu $a7, $zero, 0 # encoding: [0x64,0x0b,0x00,0x00] +0x64,0x0c,0x00,0x00 == daddiu $t4, $zero, 0 # encoding: [0x64,0x0c,0x00,0x00] +0x64,0x0d,0x00,0x00 == daddiu $t5, $zero, 0 # encoding: [0x64,0x0d,0x00,0x00] +0x64,0x0e,0x00,0x00 == daddiu $t6, $zero, 0 # encoding: [0x64,0x0e,0x00,0x00] +0x64,0x0f,0x00,0x00 == daddiu $t7, $zero, 0 # encoding: [0x64,0x0f,0x00,0x00] +0x64,0x10,0x00,0x00 == daddiu $s0, $zero, 0 # encoding: [0x64,0x10,0x00,0x00] +0x64,0x11,0x00,0x00 == daddiu $s1, $zero, 0 # encoding: [0x64,0x11,0x00,0x00] +0x64,0x12,0x00,0x00 == daddiu $s2, $zero, 0 # encoding: [0x64,0x12,0x00,0x00] +0x64,0x13,0x00,0x00 == daddiu $s3, $zero, 0 # encoding: [0x64,0x13,0x00,0x00] +0x64,0x14,0x00,0x00 == daddiu $s4, $zero, 0 # encoding: [0x64,0x14,0x00,0x00] +0x64,0x15,0x00,0x00 == daddiu $s5, $zero, 0 # encoding: [0x64,0x15,0x00,0x00] +0x64,0x16,0x00,0x00 == daddiu $s6, $zero, 0 # encoding: [0x64,0x16,0x00,0x00] +0x64,0x17,0x00,0x00 == daddiu $s7, $zero, 0 # encoding: [0x64,0x17,0x00,0x00] +0x64,0x18,0x00,0x00 == daddiu $t8, $zero, 0 # encoding: [0x64,0x18,0x00,0x00] +0x64,0x19,0x00,0x00 == daddiu $t9, $zero, 0 # encoding: [0x64,0x19,0x00,0x00] +0x64,0x1a,0x00,0x00 == daddiu $kt0, $zero, 0 # encoding: [0x64,0x1a,0x00,0x00] +0x64,0x1b,0x00,0x00 == daddiu $kt1, $zero, 0 # encoding: [0x64,0x1b,0x00,0x00] +0x64,0x1c,0x00,0x00 == daddiu $gp, $zero, 0 # encoding: [0x64,0x1c,0x00,0x00] +0x64,0x1d,0x00,0x00 == daddiu $sp, $zero, 0 # encoding: [0x64,0x1d,0x00,0x00] +0x64,0x1e,0x00,0x00 == daddiu $s8, $zero, 0 # encoding: [0x64,0x1e,0x00,0x00] +0x64,0x1f,0x00,0x00 == daddiu $ra, $zero, 0 # encoding: [0x64,0x1f,0x00,0x00] diff --git a/suite/MC/Mips/mips_directives.s.cs b/suite/MC/Mips/mips_directives.s.cs index 07d10c9713..27428ab965 100644 --- a/suite/MC/Mips/mips_directives.s.cs +++ b/suite/MC/Mips/mips_directives.s.cs @@ -1,12 +1,21 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x10,0x00,0x01,0x4d = b 1336 -0x08,0x00,0x01,0x4c = j 1328 -0x0c,0x00,0x01,0x4c = jal 1328 -0x10,0x00,0x01,0x4d = b 1336 -0x00,0x00,0x00,0x00 = nop -0x08,0x00,0x01,0x4c = j 1328 -0x00,0x00,0x00,0x00 = nop -0x0c,0x00,0x01,0x4c = jal 1328 -0x00,0x00,0x00,0x00 = nop -0x46,0x00,0x39,0x85 = abs.s $f6, $f7 -0x01,0xef,0x18,0x24 = and $v1, $t7, $t7 + +0x10,0x00,0x01,0x4d == b 1332 # encoding: [0x10,0x00,0x01,0x4d] +0x08,0x00,0x01,0x4c == j 1328 # encoding: [0x08,0x00,0x01,0x4c] +0x0c,0x00,0x01,0x4c == jal 1328 # encoding: [0x0c,0x00,0x01,0x4c] +0x10,0x00,0x01,0x4d == b 1332 # encoding: [0x10,0x00,0x01,0x4d] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x08,0x00,0x01,0x4c == j 1328 # encoding: [0x08,0x00,0x01,0x4c] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x0c,0x00,0x01,0x4c == jal 1328 # encoding: [0x0c,0x00,0x01,0x4c] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x46,0x00,0x39,0x85 == abs.s $f6, $f7 # encoding: [0x46,0x00,0x39,0x85] +0x3c,0x01, == lui $1, %hi($tmp7) # encoding: [0x3c,0x01,A,A] +0x4c,0xa0,0x00,0x01 == ldxc1 $f0, $zero($5) # encoding: [0x4c,0xa0,0x00,0x01] +0x4c,0xa6,0x00,0x05 == luxc1 $f0, $6($5) # encoding: [0x4c,0xa6,0x00,0x05] +0x4c,0xa2,0x01,0x80 == lwxc1 $f6, $2($5) # encoding: [0x4c,0xa2,0x01,0x80] +0x00,0x26,0x4f,0xba == drotr $9, $6, 30 # encoding: [0x00,0x26,0x4f,0xba] +0x7d,0x6a,0x39,0x8a == lbux $7, $10($11) # encoding: [0x7d,0x6a,0x39,0x8a] +0x7c,0xe6,0x29,0x0a == lhx $5, $6($7) # encoding: [0x7c,0xe6,0x29,0x0a] +0x7d,0x47,0x10,0x31 == append $7, $10, 2 # encoding: [0x7d,0x47,0x10,0x31] +0x7c,0xc5,0x1c,0x31 == balign $5, $6, 3 # encoding: [0x7c,0xc5,0x1c,0x31] diff --git a/suite/MC/Mips/nabi-regs.s.cs b/suite/MC/Mips/nabi-regs.s.cs index 0d14e2935a..4e56f803fc 100644 --- a/suite/MC/Mips/nabi-regs.s.cs +++ b/suite/MC/Mips/nabi-regs.s.cs @@ -1,12 +1,13 @@ # CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None -0x02,0x04,0x80,0x20 = add $s0, $s0, $a0 -0x02,0x06,0x80,0x20 = add $s0, $s0, $a2 -0x02,0x07,0x80,0x20 = add $s0, $s0, $a3 -0x02,0x08,0x80,0x20 = add $s0, $s0, $t0 -0x02,0x09,0x80,0x20 = add $s0, $s0, $t1 -0x02,0x0a,0x80,0x20 = add $s0, $s0, $t2 -0x02,0x0b,0x80,0x20 = add $s0, $s0, $t3 -0x02,0x0c,0x80,0x20 = add $s0, $s0, $t4 -0x02,0x0d,0x80,0x20 = add $s0, $s0, $t5 -0x02,0x0e,0x80,0x20 = add $s0, $s0, $t6 -0x02,0x0f,0x80,0x20 = add $s0, $s0, $t7 + +0x02,0x04,0x80,0x20 == add $16, $16, $4 # encoding: [0x02,0x04,0x80,0x20] +0x02,0x06,0x80,0x20 == add $16, $16, $6 # encoding: [0x02,0x06,0x80,0x20] +0x02,0x07,0x80,0x20 == add $16, $16, $7 # encoding: [0x02,0x07,0x80,0x20] +0x02,0x08,0x80,0x20 == add $16, $16, $8 # encoding: [0x02,0x08,0x80,0x20] +0x02,0x09,0x80,0x20 == add $16, $16, $9 # encoding: [0x02,0x09,0x80,0x20] +0x02,0x0a,0x80,0x20 == add $16, $16, $10 # encoding: [0x02,0x0a,0x80,0x20] +0x02,0x0b,0x80,0x20 == add $16, $16, $11 # encoding: [0x02,0x0b,0x80,0x20] +0x02,0x0c,0x80,0x20 == add $16, $16, $12 # encoding: [0x02,0x0c,0x80,0x20] +0x02,0x0d,0x80,0x20 == add $16, $16, $13 # encoding: [0x02,0x0d,0x80,0x20] +0x02,0x0e,0x80,0x20 == add $16, $16, $14 # encoding: [0x02,0x0e,0x80,0x20] +0x02,0x0f,0x80,0x20 == add $16, $16, $15 # encoding: [0x02,0x0f,0x80,0x20] diff --git a/suite/MC/Mips/test_2r.s.cs b/suite/MC/Mips/test_2r.s.cs index 94b37bc8e8..0a88e00bcb 100644 --- a/suite/MC/Mips/test_2r.s.cs +++ b/suite/MC/Mips/test_2r.s.cs @@ -1,16 +1,17 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x7b,0x00,0x4f,0x9e = fill.b $w30, $t1 -0x7b,0x01,0xbf,0xde = fill.h $w31, $s7 -0x7b,0x02,0xc4,0x1e = fill.w $w16, $t8 -0x7b,0x08,0x05,0x5e = nloc.b $w21, $w0 -0x7b,0x09,0xfc,0x9e = nloc.h $w18, $w31 -0x7b,0x0a,0xb8,0x9e = nloc.w $w2, $w23 -0x7b,0x0b,0x51,0x1e = nloc.d $w4, $w10 -0x7b,0x0c,0x17,0xde = nlzc.b $w31, $w2 -0x7b,0x0d,0xb6,0xde = nlzc.h $w27, $w22 -0x7b,0x0e,0xea,0x9e = nlzc.w $w10, $w29 -0x7b,0x0f,0x4e,0x5e = nlzc.d $w25, $w9 -0x7b,0x04,0x95,0x1e = pcnt.b $w20, $w18 -0x7b,0x05,0x40,0x1e = pcnt.h $w0, $w8 -0x7b,0x06,0x4d,0xde = pcnt.w $w23, $w9 -0x7b,0x07,0xc5,0x5e = pcnt.d $w21, $w24 + +0x7b,0x00,0x4f,0x9e == fill.b $w30, $9 # encoding: [0x7b,0x00,0x4f,0x9e] +0x7b,0x01,0xbf,0xde == fill.h $w31, $23 # encoding: [0x7b,0x01,0xbf,0xde] +0x7b,0x02,0xc4,0x1e == fill.w $w16, $24 # encoding: [0x7b,0x02,0xc4,0x1e] +0x7b,0x08,0x05,0x5e == nloc.b $w21, $w0 # encoding: [0x7b,0x08,0x05,0x5e] +0x7b,0x09,0xfc,0x9e == nloc.h $w18, $w31 # encoding: [0x7b,0x09,0xfc,0x9e] +0x7b,0x0a,0xb8,0x9e == nloc.w $w2, $w23 # encoding: [0x7b,0x0a,0xb8,0x9e] +0x7b,0x0b,0x51,0x1e == nloc.d $w4, $w10 # encoding: [0x7b,0x0b,0x51,0x1e] +0x7b,0x0c,0x17,0xde == nlzc.b $w31, $w2 # encoding: [0x7b,0x0c,0x17,0xde] +0x7b,0x0d,0xb6,0xde == nlzc.h $w27, $w22 # encoding: [0x7b,0x0d,0xb6,0xde] +0x7b,0x0e,0xea,0x9e == nlzc.w $w10, $w29 # encoding: [0x7b,0x0e,0xea,0x9e] +0x7b,0x0f,0x4e,0x5e == nlzc.d $w25, $w9 # encoding: [0x7b,0x0f,0x4e,0x5e] +0x7b,0x04,0x95,0x1e == pcnt.b $w20, $w18 # encoding: [0x7b,0x04,0x95,0x1e] +0x7b,0x05,0x40,0x1e == pcnt.h $w0, $w8 # encoding: [0x7b,0x05,0x40,0x1e] +0x7b,0x06,0x4d,0xde == pcnt.w $w23, $w9 # encoding: [0x7b,0x06,0x4d,0xde] +0x7b,0x07,0xc5,0x5e == pcnt.d $w21, $w24 # encoding: [0x7b,0x07,0xc5,0x5e] diff --git a/suite/MC/Mips/test_2rf.s.cs b/suite/MC/Mips/test_2rf.s.cs index 2e95606388..689e24c5d3 100644 --- a/suite/MC/Mips/test_2rf.s.cs +++ b/suite/MC/Mips/test_2rf.s.cs @@ -1,33 +1,34 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x7b,0x20,0x66,0x9e = fclass.w $w26, $w12 -0x7b,0x21,0x8e,0x1e = fclass.d $w24, $w17 -0x7b,0x30,0x02,0x1e = fexupl.w $w8, $w0 -0x7b,0x31,0xec,0x5e = fexupl.d $w17, $w29 -0x7b,0x32,0x23,0x5e = fexupr.w $w13, $w4 -0x7b,0x33,0x11,0x5e = fexupr.d $w5, $w2 -0x7b,0x3c,0xed,0x1e = ffint_s.w $w20, $w29 -0x7b,0x3d,0x7b,0x1e = ffint_s.d $w12, $w15 -0x7b,0x3e,0xd9,0xde = ffint_u.w $w7, $w27 -0x7b,0x3f,0x84,0xde = ffint_u.d $w19, $w16 -0x7b,0x34,0x6f,0xde = ffql.w $w31, $w13 -0x7b,0x35,0x6b,0x1e = ffql.d $w12, $w13 -0x7b,0x36,0xf6,0xde = ffqr.w $w27, $w30 -0x7b,0x37,0x7f,0x9e = ffqr.d $w30, $w15 -0x7b,0x2e,0xfe,0x5e = flog2.w $w25, $w31 -0x7b,0x2f,0x54,0x9e = flog2.d $w18, $w10 -0x7b,0x2c,0x79,0xde = frint.w $w7, $w15 -0x7b,0x2d,0xb5,0x5e = frint.d $w21, $w22 -0x7b,0x2a,0x04,0xde = frcp.w $w19, $w0 -0x7b,0x2b,0x71,0x1e = frcp.d $w4, $w14 -0x7b,0x28,0x8b,0x1e = frsqrt.w $w12, $w17 -0x7b,0x29,0x5d,0xde = frsqrt.d $w23, $w11 -0x7b,0x26,0x58,0x1e = fsqrt.w $w0, $w11 -0x7b,0x27,0x63,0xde = fsqrt.d $w15, $w12 -0x7b,0x38,0x2f,0x9e = ftint_s.w $w30, $w5 -0x7b,0x39,0xb9,0x5e = ftint_s.d $w5, $w23 -0x7b,0x3a,0x75,0x1e = ftint_u.w $w20, $w14 -0x7b,0x3b,0xad,0xde = ftint_u.d $w23, $w21 -0x7b,0x22,0x8f,0x5e = ftrunc_s.w $w29, $w17 -0x7b,0x23,0xdb,0x1e = ftrunc_s.d $w12, $w27 -0x7b,0x24,0x7c,0x5e = ftrunc_u.w $w17, $w15 -0x7b,0x25,0xd9,0x5e = ftrunc_u.d $w5, $w27 + +0x7b,0x20,0x66,0x9e == fclass.w $w26, $w12 # encoding: [0x7b,0x20,0x66,0x9e] +0x7b,0x21,0x8e,0x1e == fclass.d $w24, $w17 # encoding: [0x7b,0x21,0x8e,0x1e] +0x7b,0x30,0x02,0x1e == fexupl.w $w8, $w0 # encoding: [0x7b,0x30,0x02,0x1e] +0x7b,0x31,0xec,0x5e == fexupl.d $w17, $w29 # encoding: [0x7b,0x31,0xec,0x5e] +0x7b,0x32,0x23,0x5e == fexupr.w $w13, $w4 # encoding: [0x7b,0x32,0x23,0x5e] +0x7b,0x33,0x11,0x5e == fexupr.d $w5, $w2 # encoding: [0x7b,0x33,0x11,0x5e] +0x7b,0x3c,0xed,0x1e == ffint_s.w $w20, $w29 # encoding: [0x7b,0x3c,0xed,0x1e] +0x7b,0x3d,0x7b,0x1e == ffint_s.d $w12, $w15 # encoding: [0x7b,0x3d,0x7b,0x1e] +0x7b,0x3e,0xd9,0xde == ffint_u.w $w7, $w27 # encoding: [0x7b,0x3e,0xd9,0xde] +0x7b,0x3f,0x84,0xde == ffint_u.d $w19, $w16 # encoding: [0x7b,0x3f,0x84,0xde] +0x7b,0x34,0x6f,0xde == ffql.w $w31, $w13 # encoding: [0x7b,0x34,0x6f,0xde] +0x7b,0x35,0x6b,0x1e == ffql.d $w12, $w13 # encoding: [0x7b,0x35,0x6b,0x1e] +0x7b,0x36,0xf6,0xde == ffqr.w $w27, $w30 # encoding: [0x7b,0x36,0xf6,0xde] +0x7b,0x37,0x7f,0x9e == ffqr.d $w30, $w15 # encoding: [0x7b,0x37,0x7f,0x9e] +0x7b,0x2e,0xfe,0x5e == flog2.w $w25, $w31 # encoding: [0x7b,0x2e,0xfe,0x5e] +0x7b,0x2f,0x54,0x9e == flog2.d $w18, $w10 # encoding: [0x7b,0x2f,0x54,0x9e] +0x7b,0x2c,0x79,0xde == frint.w $w7, $w15 # encoding: [0x7b,0x2c,0x79,0xde] +0x7b,0x2d,0xb5,0x5e == frint.d $w21, $w22 # encoding: [0x7b,0x2d,0xb5,0x5e] +0x7b,0x2a,0x04,0xde == frcp.w $w19, $w0 # encoding: [0x7b,0x2a,0x04,0xde] +0x7b,0x2b,0x71,0x1e == frcp.d $w4, $w14 # encoding: [0x7b,0x2b,0x71,0x1e] +0x7b,0x28,0x8b,0x1e == frsqrt.w $w12, $w17 # encoding: [0x7b,0x28,0x8b,0x1e] +0x7b,0x29,0x5d,0xde == frsqrt.d $w23, $w11 # encoding: [0x7b,0x29,0x5d,0xde] +0x7b,0x26,0x58,0x1e == fsqrt.w $w0, $w11 # encoding: [0x7b,0x26,0x58,0x1e] +0x7b,0x27,0x63,0xde == fsqrt.d $w15, $w12 # encoding: [0x7b,0x27,0x63,0xde] +0x7b,0x38,0x2f,0x9e == ftint_s.w $w30, $w5 # encoding: [0x7b,0x38,0x2f,0x9e] +0x7b,0x39,0xb9,0x5e == ftint_s.d $w5, $w23 # encoding: [0x7b,0x39,0xb9,0x5e] +0x7b,0x3a,0x75,0x1e == ftint_u.w $w20, $w14 # encoding: [0x7b,0x3a,0x75,0x1e] +0x7b,0x3b,0xad,0xde == ftint_u.d $w23, $w21 # encoding: [0x7b,0x3b,0xad,0xde] +0x7b,0x22,0x8f,0x5e == ftrunc_s.w $w29, $w17 # encoding: [0x7b,0x22,0x8f,0x5e] +0x7b,0x23,0xdb,0x1e == ftrunc_s.d $w12, $w27 # encoding: [0x7b,0x23,0xdb,0x1e] +0x7b,0x24,0x7c,0x5e == ftrunc_u.w $w17, $w15 # encoding: [0x7b,0x24,0x7c,0x5e] +0x7b,0x25,0xd9,0x5e == ftrunc_u.d $w5, $w27 # encoding: [0x7b,0x25,0xd9,0x5e] diff --git a/suite/MC/Mips/test_3r.s.cs b/suite/MC/Mips/test_3r.s.cs index 99f5de917f..0b95467139 100644 --- a/suite/MC/Mips/test_3r.s.cs +++ b/suite/MC/Mips/test_3r.s.cs @@ -1,243 +1,244 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x78,0x04,0x4e,0x90 = add_a.b $w26, $w9, $w4 -0x78,0x3f,0xdd,0xd0 = add_a.h $w23, $w27, $w31 -0x78,0x56,0x32,0xd0 = add_a.w $w11, $w6, $w22 -0x78,0x60,0x51,0x90 = add_a.d $w6, $w10, $w0 -0x78,0x93,0xc4,0xd0 = adds_a.b $w19, $w24, $w19 -0x78,0xa4,0x36,0x50 = adds_a.h $w25, $w6, $w4 -0x78,0xdb,0x8e,0x50 = adds_a.w $w25, $w17, $w27 -0x78,0xfa,0x93,0xd0 = adds_a.d $w15, $w18, $w26 -0x79,0x13,0x5f,0x50 = adds_s.b $w29, $w11, $w19 -0x79,0x3a,0xb9,0x50 = adds_s.h $w5, $w23, $w26 -0x79,0x4d,0x74,0x10 = adds_s.w $w16, $w14, $w13 -0x79,0x7c,0x70,0x90 = adds_s.d $w2, $w14, $w28 -0x79,0x8e,0x88,0xd0 = adds_u.b $w3, $w17, $w14 -0x79,0xa4,0xf2,0x90 = adds_u.h $w10, $w30, $w4 -0x79,0xd4,0x93,0xd0 = adds_u.w $w15, $w18, $w20 -0x79,0xe9,0x57,0x90 = adds_u.d $w30, $w10, $w9 -0x78,0x15,0xa6,0x0e = addv.b $w24, $w20, $w21 -0x78,0x3b,0x69,0x0e = addv.h $w4, $w13, $w27 -0x78,0x4e,0x5c,0xce = addv.w $w19, $w11, $w14 -0x78,0x7f,0xa8,0x8e = addv.d $w2, $w21, $w31 -0x7a,0x03,0x85,0xd1 = asub_s.b $w23, $w16, $w3 -0x7a,0x39,0x8d,0x91 = asub_s.h $w22, $w17, $w25 -0x7a,0x49,0x0e,0x11 = asub_s.w $w24, $w1, $w9 -0x7a,0x6c,0x63,0x51 = asub_s.d $w13, $w12, $w12 -0x7a,0x8b,0xea,0x91 = asub_u.b $w10, $w29, $w11 -0x7a,0xaf,0x4c,0x91 = asub_u.h $w18, $w9, $w15 -0x7a,0xdf,0x9a,0x91 = asub_u.w $w10, $w19, $w31 -0x7a,0xe0,0x54,0x51 = asub_u.d $w17, $w10, $w0 -0x7a,0x01,0x28,0x90 = ave_s.b $w2, $w5, $w1 -0x7a,0x29,0x9c,0x10 = ave_s.h $w16, $w19, $w9 -0x7a,0x45,0xfc,0x50 = ave_s.w $w17, $w31, $w5 -0x7a,0x6a,0xce,0xd0 = ave_s.d $w27, $w25, $w10 -0x7a,0x89,0x9c,0x10 = ave_u.b $w16, $w19, $w9 -0x7a,0xab,0xe7,0x10 = ave_u.h $w28, $w28, $w11 -0x7a,0xcb,0x62,0xd0 = ave_u.w $w11, $w12, $w11 -0x7a,0xfc,0x9f,0x90 = ave_u.d $w30, $w19, $w28 -0x7b,0x02,0x86,0x90 = aver_s.b $w26, $w16, $w2 -0x7b,0x3b,0xdf,0xd0 = aver_s.h $w31, $w27, $w27 -0x7b,0x59,0x97,0x10 = aver_s.w $w28, $w18, $w25 -0x7b,0x7b,0xaf,0x50 = aver_s.d $w29, $w21, $w27 -0x7b,0x83,0xd7,0x50 = aver_u.b $w29, $w26, $w3 -0x7b,0xa9,0x94,0x90 = aver_u.h $w18, $w18, $w9 -0x7b,0xdd,0xcc,0x50 = aver_u.w $w17, $w25, $w29 -0x7b,0xf3,0xb5,0x90 = aver_u.d $w22, $w22, $w19 -0x79,0x9d,0x78,0x8d = bclr.b $w2, $w15, $w29 -0x79,0xbc,0xac,0x0d = bclr.h $w16, $w21, $w28 -0x79,0xc9,0x14,0xcd = bclr.w $w19, $w2, $w9 -0x79,0xe4,0xfe,0xcd = bclr.d $w27, $w31, $w4 -0x7b,0x18,0x81,0x4d = binsl.b $w5, $w16, $w24 -0x7b,0x2a,0x2f,0x8d = binsl.h $w30, $w5, $w10 -0x7b,0x4d,0x7b,0x8d = binsl.w $w14, $w15, $w13 -0x7b,0x6c,0xa5,0xcd = binsl.d $w23, $w20, $w12 -0x7b,0x82,0x5d,0x8d = binsr.b $w22, $w11, $w2 -0x7b,0xa6,0xd0,0x0d = binsr.h $w0, $w26, $w6 -0x7b,0xdc,0x1e,0x8d = binsr.w $w26, $w3, $w28 -0x7b,0xf5,0x00,0x0d = binsr.d $w0, $w0, $w21 -0x7a,0x98,0x58,0x0d = bneg.b $w0, $w11, $w24 -0x7a,0xa4,0x87,0x0d = bneg.h $w28, $w16, $w4 -0x7a,0xd3,0xd0,0xcd = bneg.w $w3, $w26, $w19 -0x7a,0xef,0xeb,0x4d = bneg.d $w13, $w29, $w15 -0x7a,0x1f,0x2f,0xcd = bset.b $w31, $w5, $w31 -0x7a,0x26,0x63,0x8d = bset.h $w14, $w12, $w6 -0x7a,0x4c,0x4f,0xcd = bset.w $w31, $w9, $w12 -0x7a,0x65,0xb1,0x4d = bset.d $w5, $w22, $w5 -0x78,0x12,0xff,0xcf = ceq.b $w31, $w31, $w18 -0x78,0x29,0xda,0x8f = ceq.h $w10, $w27, $w9 -0x78,0x4e,0x2a,0x4f = ceq.w $w9, $w5, $w14 -0x78,0x60,0x89,0x4f = ceq.d $w5, $w17, $w0 -0x7a,0x09,0x25,0xcf = cle_s.b $w23, $w4, $w9 -0x7a,0x33,0xdd,0x8f = cle_s.h $w22, $w27, $w19 -0x7a,0x4a,0xd7,0x8f = cle_s.w $w30, $w26, $w10 -0x7a,0x6a,0x2c,0x8f = cle_s.d $w18, $w5, $w10 -0x7a,0x80,0xc8,0x4f = cle_u.b $w1, $w25, $w0 -0x7a,0xbd,0x01,0xcf = cle_u.h $w7, $w0, $w29 -0x7a,0xc1,0x96,0x4f = cle_u.w $w25, $w18, $w1 -0x7a,0xfe,0x01,0x8f = cle_u.d $w6, $w0, $w30 -0x79,0x15,0x16,0x4f = clt_s.b $w25, $w2, $w21 -0x79,0x29,0x98,0x8f = clt_s.h $w2, $w19, $w9 -0x79,0x50,0x45,0xcf = clt_s.w $w23, $w8, $w16 -0x79,0x6c,0xf1,0xcf = clt_s.d $w7, $w30, $w12 -0x79,0x8d,0xf8,0x8f = clt_u.b $w2, $w31, $w13 -0x79,0xb7,0xfc,0x0f = clt_u.h $w16, $w31, $w23 -0x79,0xc9,0xc0,0xcf = clt_u.w $w3, $w24, $w9 -0x79,0xe1,0x01,0xcf = clt_u.d $w7, $w0, $w1 -0x7a,0x12,0x1f,0x52 = div_s.b $w29, $w3, $w18 -0x7a,0x2d,0x84,0x52 = div_s.h $w17, $w16, $w13 -0x7a,0x5e,0xc9,0x12 = div_s.w $w4, $w25, $w30 -0x7a,0x74,0x4f,0xd2 = div_s.d $w31, $w9, $w20 -0x7a,0x8a,0xe9,0x92 = div_u.b $w6, $w29, $w10 -0x7a,0xae,0xae,0x12 = div_u.h $w24, $w21, $w14 -0x7a,0xd9,0x77,0x52 = div_u.w $w29, $w14, $w25 -0x7a,0xf5,0x0f,0xd2 = div_u.d $w31, $w1, $w21 -0x78,0x39,0xb5,0xd3 = dotp_s.h $w23, $w22, $w25 -0x78,0x45,0x75,0x13 = dotp_s.w $w20, $w14, $w5 -0x78,0x76,0x14,0x53 = dotp_s.d $w17, $w2, $w22 -0x78,0xa6,0x13,0x53 = dotp_u.h $w13, $w2, $w6 -0x78,0xd5,0xb3,0xd3 = dotp_u.w $w15, $w22, $w21 -0x78,0xfa,0x81,0x13 = dotp_u.d $w4, $w16, $w26 -0x79,0x36,0xe0,0x53 = dpadd_s.h $w1, $w28, $w22 -0x79,0x4c,0x0a,0x93 = dpadd_s.w $w10, $w1, $w12 -0x79,0x7b,0xa8,0xd3 = dpadd_s.d $w3, $w21, $w27 -0x79,0xb4,0x2c,0x53 = dpadd_u.h $w17, $w5, $w20 -0x79,0xd0,0x46,0x13 = dpadd_u.w $w24, $w8, $w16 -0x79,0xf0,0xeb,0xd3 = dpadd_u.d $w15, $w29, $w16 -0x7a,0x2c,0x59,0x13 = dpsub_s.h $w4, $w11, $w12 -0x7a,0x46,0x39,0x13 = dpsub_s.w $w4, $w7, $w6 -0x7a,0x7c,0x67,0xd3 = dpsub_s.d $w31, $w12, $w28 -0x7a,0xb1,0xc9,0x13 = dpsub_u.h $w4, $w25, $w17 -0x7a,0xd0,0xcc,0xd3 = dpsub_u.w $w19, $w25, $w16 -0x7a,0xfa,0x51,0xd3 = dpsub_u.d $w7, $w10, $w26 -0x7a,0x22,0xc7,0x15 = hadd_s.h $w28, $w24, $w2 -0x7a,0x4b,0x8e,0x15 = hadd_s.w $w24, $w17, $w11 -0x7a,0x74,0x7c,0x55 = hadd_s.d $w17, $w15, $w20 -0x7a,0xb1,0xeb,0x15 = hadd_u.h $w12, $w29, $w17 -0x7a,0xc6,0x2a,0x55 = hadd_u.w $w9, $w5, $w6 -0x7a,0xe6,0xa0,0x55 = hadd_u.d $w1, $w20, $w6 -0x7b,0x3d,0x74,0x15 = hsub_s.h $w16, $w14, $w29 -0x7b,0x4b,0x6a,0x55 = hsub_s.w $w9, $w13, $w11 -0x7b,0x6e,0x97,0x95 = hsub_s.d $w30, $w18, $w14 -0x7b,0xae,0x61,0xd5 = hsub_u.h $w7, $w12, $w14 -0x7b,0xc5,0x2d,0x55 = hsub_u.w $w21, $w5, $w5 -0x7b,0xff,0x62,0xd5 = hsub_u.d $w11, $w12, $w31 -0x7b,0x1e,0x84,0x94 = ilvev.b $w18, $w16, $w30 -0x7b,0x2d,0x03,0x94 = ilvev.h $w14, $w0, $w13 -0x7b,0x56,0xcb,0x14 = ilvev.w $w12, $w25, $w22 -0x7b,0x63,0xdf,0x94 = ilvev.d $w30, $w27, $w3 -0x7a,0x15,0x1f,0x54 = ilvl.b $w29, $w3, $w21 -0x7a,0x31,0x56,0xd4 = ilvl.h $w27, $w10, $w17 -0x7a,0x40,0x09,0x94 = ilvl.w $w6, $w1, $w0 -0x7a,0x78,0x80,0xd4 = ilvl.d $w3, $w16, $w24 -0x7b,0x94,0x2a,0xd4 = ilvod.b $w11, $w5, $w20 -0x7b,0xbf,0x6c,0x94 = ilvod.h $w18, $w13, $w31 -0x7b,0xd8,0x87,0x54 = ilvod.w $w29, $w16, $w24 -0x7b,0xfd,0x65,0x94 = ilvod.d $w22, $w12, $w29 -0x7a,0x86,0xf1,0x14 = ilvr.b $w4, $w30, $w6 -0x7a,0xbd,0x9f,0x14 = ilvr.h $w28, $w19, $w29 -0x7a,0xd5,0xa4,0x94 = ilvr.w $w18, $w20, $w21 -0x7a,0xec,0xf5,0xd4 = ilvr.d $w23, $w30, $w12 -0x78,0x9d,0xfc,0x52 = maddv.b $w17, $w31, $w29 -0x78,0xa9,0xc1,0xd2 = maddv.h $w7, $w24, $w9 -0x78,0xd4,0xb5,0x92 = maddv.w $w22, $w22, $w20 -0x78,0xf4,0xd7,0x92 = maddv.d $w30, $w26, $w20 -0x7b,0x17,0x5d,0xce = max_a.b $w23, $w11, $w23 -0x7b,0x3e,0x2d,0x0e = max_a.h $w20, $w5, $w30 -0x7b,0x5e,0x91,0xce = max_a.w $w7, $w18, $w30 -0x7b,0x7f,0x42,0x0e = max_a.d $w8, $w8, $w31 -0x79,0x13,0x0a,0x8e = max_s.b $w10, $w1, $w19 -0x79,0x31,0xeb,0xce = max_s.h $w15, $w29, $w17 -0x79,0x4e,0xeb,0xce = max_s.w $w15, $w29, $w14 -0x79,0x63,0xc6,0x4e = max_s.d $w25, $w24, $w3 -0x79,0x85,0xc3,0x0e = max_u.b $w12, $w24, $w5 -0x79,0xa7,0x31,0x4e = max_u.h $w5, $w6, $w7 -0x79,0xc7,0x24,0x0e = max_u.w $w16, $w4, $w7 -0x79,0xf8,0x66,0x8e = max_u.d $w26, $w12, $w24 -0x7b,0x81,0xd1,0x0e = min_a.b $w4, $w26, $w1 -0x7b,0xbf,0x6b,0x0e = min_a.h $w12, $w13, $w31 -0x7b,0xc0,0xa7,0x0e = min_a.w $w28, $w20, $w0 -0x7b,0xf3,0xa3,0x0e = min_a.d $w12, $w20, $w19 -0x7a,0x0e,0x1c,0xce = min_s.b $w19, $w3, $w14 -0x7a,0x28,0xae,0xce = min_s.h $w27, $w21, $w8 -0x7a,0x5e,0x70,0x0e = min_s.w $w0, $w14, $w30 -0x7a,0x75,0x41,0x8e = min_s.d $w6, $w8, $w21 -0x7a,0x88,0xd5,0x8e = min_u.b $w22, $w26, $w8 -0x7a,0xac,0xd9,0xce = min_u.h $w7, $w27, $w12 -0x7a,0xce,0xa2,0x0e = min_u.w $w8, $w20, $w14 -0x7a,0xef,0x76,0x8e = min_u.d $w26, $w14, $w15 -0x7b,0x1a,0x0c,0x92 = mod_s.b $w18, $w1, $w26 -0x7b,0x3c,0xf7,0xd2 = mod_s.h $w31, $w30, $w28 -0x7b,0x4d,0x30,0x92 = mod_s.w $w2, $w6, $w13 -0x7b,0x76,0xdd,0x52 = mod_s.d $w21, $w27, $w22 -0x7b,0x8d,0x3c,0x12 = mod_u.b $w16, $w7, $w13 -0x7b,0xa7,0x46,0x12 = mod_u.h $w24, $w8, $w7 -0x7b,0xd1,0x17,0x92 = mod_u.w $w30, $w2, $w17 -0x7b,0xf9,0x17,0xd2 = mod_u.d $w31, $w2, $w25 -0x79,0x0c,0x2b,0x92 = msubv.b $w14, $w5, $w12 -0x79,0x3e,0x39,0x92 = msubv.h $w6, $w7, $w30 -0x79,0x55,0x13,0x52 = msubv.w $w13, $w2, $w21 -0x79,0x7b,0x74,0x12 = msubv.d $w16, $w14, $w27 -0x78,0x0d,0x1d,0x12 = mulv.b $w20, $w3, $w13 -0x78,0x2e,0xd6,0xd2 = mulv.h $w27, $w26, $w14 -0x78,0x43,0xea,0x92 = mulv.w $w10, $w29, $w3 -0x78,0x7d,0x99,0xd2 = mulv.d $w7, $w19, $w29 -0x79,0x07,0xd9,0x54 = pckev.b $w5, $w27, $w7 -0x79,0x3b,0x20,0x54 = pckev.h $w1, $w4, $w27 -0x79,0x40,0xa7,0x94 = pckev.w $w30, $w20, $w0 -0x79,0x6f,0x09,0x94 = pckev.d $w6, $w1, $w15 -0x79,0x9e,0xe4,0x94 = pckod.b $w18, $w28, $w30 -0x79,0xa8,0x2e,0x94 = pckod.h $w26, $w5, $w8 -0x79,0xc2,0x22,0x54 = pckod.w $w9, $w4, $w2 -0x79,0xf4,0xb7,0x94 = pckod.d $w30, $w22, $w20 -0x78,0x0c,0xb9,0x54 = sld.b $w5, $w23[$t4] -0x78,0x23,0xb8,0x54 = sld.h $w1, $w23[$v1] -0x78,0x49,0x45,0x14 = sld.w $w20, $w8[$t1] -0x78,0x7e,0xb9,0xd4 = sld.d $w7, $w23[$fp] -0x78,0x11,0x00,0xcd = sll.b $w3, $w0, $w17 -0x78,0x23,0xdc,0x4d = sll.h $w17, $w27, $w3 -0x78,0x46,0x3c,0x0d = sll.w $w16, $w7, $w6 -0x78,0x7a,0x02,0x4d = sll.d $w9, $w0, $w26 -0x78,0x81,0x0f,0x14 = splat.b $w28, $w1[$at] -0x78,0xab,0x58,0x94 = splat.h $w2, $w11[$t3] -0x78,0xcb,0x05,0x94 = splat.w $w22, $w0[$t3] -0x78,0xe2,0x00,0x14 = splat.d $w0, $w0[$v0] -0x78,0x91,0x27,0x0d = sra.b $w28, $w4, $w17 -0x78,0xa3,0x4b,0x4d = sra.h $w13, $w9, $w3 -0x78,0xd3,0xae,0xcd = sra.w $w27, $w21, $w19 -0x78,0xf7,0x47,0x8d = sra.d $w30, $w8, $w23 -0x78,0x92,0x94,0xd5 = srar.b $w19, $w18, $w18 -0x78,0xa8,0xb9,0xd5 = srar.h $w7, $w23, $w8 -0x78,0xc2,0x60,0x55 = srar.w $w1, $w12, $w2 -0x78,0xee,0x3d,0x55 = srar.d $w21, $w7, $w14 -0x79,0x13,0x1b,0x0d = srl.b $w12, $w3, $w19 -0x79,0x34,0xfd,0xcd = srl.h $w23, $w31, $w20 -0x79,0x4b,0xdc,0x8d = srl.w $w18, $w27, $w11 -0x79,0x7a,0x60,0xcd = srl.d $w3, $w12, $w26 -0x79,0x0b,0xab,0xd5 = srlr.b $w15, $w21, $w11 -0x79,0x33,0x6d,0x55 = srlr.h $w21, $w13, $w19 -0x79,0x43,0xf1,0x95 = srlr.w $w6, $w30, $w3 -0x79,0x6e,0x10,0x55 = srlr.d $w1, $w2, $w14 -0x78,0x01,0x7e,0x51 = subs_s.b $w25, $w15, $w1 -0x78,0x36,0xcf,0x11 = subs_s.h $w28, $w25, $w22 -0x78,0x55,0x62,0x91 = subs_s.w $w10, $w12, $w21 -0x78,0x72,0xa1,0x11 = subs_s.d $w4, $w20, $w18 -0x78,0x99,0x35,0x51 = subs_u.b $w21, $w6, $w25 -0x78,0xa7,0x50,0xd1 = subs_u.h $w3, $w10, $w7 -0x78,0xca,0x7a,0x51 = subs_u.w $w9, $w15, $w10 -0x78,0xea,0x99,0xd1 = subs_u.d $w7, $w19, $w10 -0x79,0x0c,0x39,0x91 = subsus_u.b $w6, $w7, $w12 -0x79,0x33,0xe9,0x91 = subsus_u.h $w6, $w29, $w19 -0x79,0x47,0x79,0xd1 = subsus_u.w $w7, $w15, $w7 -0x79,0x6f,0x1a,0x51 = subsus_u.d $w9, $w3, $w15 -0x79,0x9f,0x1d,0x91 = subsuu_s.b $w22, $w3, $w31 -0x79,0xb6,0xbc,0xd1 = subsuu_s.h $w19, $w23, $w22 -0x79,0xcd,0x52,0x51 = subsuu_s.w $w9, $w10, $w13 -0x79,0xe0,0x31,0x51 = subsuu_s.d $w5, $w6, $w0 -0x78,0x93,0x69,0x8e = subv.b $w6, $w13, $w19 -0x78,0xac,0xc9,0x0e = subv.h $w4, $w25, $w12 -0x78,0xcb,0xde,0xce = subv.w $w27, $w27, $w11 -0x78,0xea,0xc2,0x4e = subv.d $w9, $w24, $w10 -0x78,0x05,0x80,0xd5 = vshf.b $w3, $w16, $w5 -0x78,0x28,0x9d,0x15 = vshf.h $w20, $w19, $w8 -0x78,0x59,0xf4,0x15 = vshf.w $w16, $w30, $w25 -0x78,0x6f,0x5c,0xd5 = vshf.d $w19, $w11, $w15 + +0x78,0x04,0x4e,0x90 == add_a.b $w26, $w9, $w4 # encoding: [0x78,0x04,0x4e,0x90] +0x78,0x3f,0xdd,0xd0 == add_a.h $w23, $w27, $w31 # encoding: [0x78,0x3f,0xdd,0xd0] +0x78,0x56,0x32,0xd0 == add_a.w $w11, $w6, $w22 # encoding: [0x78,0x56,0x32,0xd0] +0x78,0x60,0x51,0x90 == add_a.d $w6, $w10, $w0 # encoding: [0x78,0x60,0x51,0x90] +0x78,0x93,0xc4,0xd0 == adds_a.b $w19, $w24, $w19 # encoding: [0x78,0x93,0xc4,0xd0] +0x78,0xa4,0x36,0x50 == adds_a.h $w25, $w6, $w4 # encoding: [0x78,0xa4,0x36,0x50] +0x78,0xdb,0x8e,0x50 == adds_a.w $w25, $w17, $w27 # encoding: [0x78,0xdb,0x8e,0x50] +0x78,0xfa,0x93,0xd0 == adds_a.d $w15, $w18, $w26 # encoding: [0x78,0xfa,0x93,0xd0] +0x79,0x13,0x5f,0x50 == adds_s.b $w29, $w11, $w19 # encoding: [0x79,0x13,0x5f,0x50] +0x79,0x3a,0xb9,0x50 == adds_s.h $w5, $w23, $w26 # encoding: [0x79,0x3a,0xb9,0x50] +0x79,0x4d,0x74,0x10 == adds_s.w $w16, $w14, $w13 # encoding: [0x79,0x4d,0x74,0x10] +0x79,0x7c,0x70,0x90 == adds_s.d $w2, $w14, $w28 # encoding: [0x79,0x7c,0x70,0x90] +0x79,0x8e,0x88,0xd0 == adds_u.b $w3, $w17, $w14 # encoding: [0x79,0x8e,0x88,0xd0] +0x79,0xa4,0xf2,0x90 == adds_u.h $w10, $w30, $w4 # encoding: [0x79,0xa4,0xf2,0x90] +0x79,0xd4,0x93,0xd0 == adds_u.w $w15, $w18, $w20 # encoding: [0x79,0xd4,0x93,0xd0] +0x79,0xe9,0x57,0x90 == adds_u.d $w30, $w10, $w9 # encoding: [0x79,0xe9,0x57,0x90] +0x78,0x15,0xa6,0x0e == addv.b $w24, $w20, $w21 # encoding: [0x78,0x15,0xa6,0x0e] +0x78,0x3b,0x69,0x0e == addv.h $w4, $w13, $w27 # encoding: [0x78,0x3b,0x69,0x0e] +0x78,0x4e,0x5c,0xce == addv.w $w19, $w11, $w14 # encoding: [0x78,0x4e,0x5c,0xce] +0x78,0x7f,0xa8,0x8e == addv.d $w2, $w21, $w31 # encoding: [0x78,0x7f,0xa8,0x8e] +0x7a,0x03,0x85,0xd1 == asub_s.b $w23, $w16, $w3 # encoding: [0x7a,0x03,0x85,0xd1] +0x7a,0x39,0x8d,0x91 == asub_s.h $w22, $w17, $w25 # encoding: [0x7a,0x39,0x8d,0x91] +0x7a,0x49,0x0e,0x11 == asub_s.w $w24, $w1, $w9 # encoding: [0x7a,0x49,0x0e,0x11] +0x7a,0x6c,0x63,0x51 == asub_s.d $w13, $w12, $w12 # encoding: [0x7a,0x6c,0x63,0x51] +0x7a,0x8b,0xea,0x91 == asub_u.b $w10, $w29, $w11 # encoding: [0x7a,0x8b,0xea,0x91] +0x7a,0xaf,0x4c,0x91 == asub_u.h $w18, $w9, $w15 # encoding: [0x7a,0xaf,0x4c,0x91] +0x7a,0xdf,0x9a,0x91 == asub_u.w $w10, $w19, $w31 # encoding: [0x7a,0xdf,0x9a,0x91] +0x7a,0xe0,0x54,0x51 == asub_u.d $w17, $w10, $w0 # encoding: [0x7a,0xe0,0x54,0x51] +0x7a,0x01,0x28,0x90 == ave_s.b $w2, $w5, $w1 # encoding: [0x7a,0x01,0x28,0x90] +0x7a,0x29,0x9c,0x10 == ave_s.h $w16, $w19, $w9 # encoding: [0x7a,0x29,0x9c,0x10] +0x7a,0x45,0xfc,0x50 == ave_s.w $w17, $w31, $w5 # encoding: [0x7a,0x45,0xfc,0x50] +0x7a,0x6a,0xce,0xd0 == ave_s.d $w27, $w25, $w10 # encoding: [0x7a,0x6a,0xce,0xd0] +0x7a,0x89,0x9c,0x10 == ave_u.b $w16, $w19, $w9 # encoding: [0x7a,0x89,0x9c,0x10] +0x7a,0xab,0xe7,0x10 == ave_u.h $w28, $w28, $w11 # encoding: [0x7a,0xab,0xe7,0x10] +0x7a,0xcb,0x62,0xd0 == ave_u.w $w11, $w12, $w11 # encoding: [0x7a,0xcb,0x62,0xd0] +0x7a,0xfc,0x9f,0x90 == ave_u.d $w30, $w19, $w28 # encoding: [0x7a,0xfc,0x9f,0x90] +0x7b,0x02,0x86,0x90 == aver_s.b $w26, $w16, $w2 # encoding: [0x7b,0x02,0x86,0x90] +0x7b,0x3b,0xdf,0xd0 == aver_s.h $w31, $w27, $w27 # encoding: [0x7b,0x3b,0xdf,0xd0] +0x7b,0x59,0x97,0x10 == aver_s.w $w28, $w18, $w25 # encoding: [0x7b,0x59,0x97,0x10] +0x7b,0x7b,0xaf,0x50 == aver_s.d $w29, $w21, $w27 # encoding: [0x7b,0x7b,0xaf,0x50] +0x7b,0x83,0xd7,0x50 == aver_u.b $w29, $w26, $w3 # encoding: [0x7b,0x83,0xd7,0x50] +0x7b,0xa9,0x94,0x90 == aver_u.h $w18, $w18, $w9 # encoding: [0x7b,0xa9,0x94,0x90] +0x7b,0xdd,0xcc,0x50 == aver_u.w $w17, $w25, $w29 # encoding: [0x7b,0xdd,0xcc,0x50] +0x7b,0xf3,0xb5,0x90 == aver_u.d $w22, $w22, $w19 # encoding: [0x7b,0xf3,0xb5,0x90] +0x79,0x9d,0x78,0x8d == bclr.b $w2, $w15, $w29 # encoding: [0x79,0x9d,0x78,0x8d] +0x79,0xbc,0xac,0x0d == bclr.h $w16, $w21, $w28 # encoding: [0x79,0xbc,0xac,0x0d] +0x79,0xc9,0x14,0xcd == bclr.w $w19, $w2, $w9 # encoding: [0x79,0xc9,0x14,0xcd] +0x79,0xe4,0xfe,0xcd == bclr.d $w27, $w31, $w4 # encoding: [0x79,0xe4,0xfe,0xcd] +0x7b,0x18,0x81,0x4d == binsl.b $w5, $w16, $w24 # encoding: [0x7b,0x18,0x81,0x4d] +0x7b,0x2a,0x2f,0x8d == binsl.h $w30, $w5, $w10 # encoding: [0x7b,0x2a,0x2f,0x8d] +0x7b,0x4d,0x7b,0x8d == binsl.w $w14, $w15, $w13 # encoding: [0x7b,0x4d,0x7b,0x8d] +0x7b,0x6c,0xa5,0xcd == binsl.d $w23, $w20, $w12 # encoding: [0x7b,0x6c,0xa5,0xcd] +0x7b,0x82,0x5d,0x8d == binsr.b $w22, $w11, $w2 # encoding: [0x7b,0x82,0x5d,0x8d] +0x7b,0xa6,0xd0,0x0d == binsr.h $w0, $w26, $w6 # encoding: [0x7b,0xa6,0xd0,0x0d] +0x7b,0xdc,0x1e,0x8d == binsr.w $w26, $w3, $w28 # encoding: [0x7b,0xdc,0x1e,0x8d] +0x7b,0xf5,0x00,0x0d == binsr.d $w0, $w0, $w21 # encoding: [0x7b,0xf5,0x00,0x0d] +0x7a,0x98,0x58,0x0d == bneg.b $w0, $w11, $w24 # encoding: [0x7a,0x98,0x58,0x0d] +0x7a,0xa4,0x87,0x0d == bneg.h $w28, $w16, $w4 # encoding: [0x7a,0xa4,0x87,0x0d] +0x7a,0xd3,0xd0,0xcd == bneg.w $w3, $w26, $w19 # encoding: [0x7a,0xd3,0xd0,0xcd] +0x7a,0xef,0xeb,0x4d == bneg.d $w13, $w29, $w15 # encoding: [0x7a,0xef,0xeb,0x4d] +0x7a,0x1f,0x2f,0xcd == bset.b $w31, $w5, $w31 # encoding: [0x7a,0x1f,0x2f,0xcd] +0x7a,0x26,0x63,0x8d == bset.h $w14, $w12, $w6 # encoding: [0x7a,0x26,0x63,0x8d] +0x7a,0x4c,0x4f,0xcd == bset.w $w31, $w9, $w12 # encoding: [0x7a,0x4c,0x4f,0xcd] +0x7a,0x65,0xb1,0x4d == bset.d $w5, $w22, $w5 # encoding: [0x7a,0x65,0xb1,0x4d] +0x78,0x12,0xff,0xcf == ceq.b $w31, $w31, $w18 # encoding: [0x78,0x12,0xff,0xcf] +0x78,0x29,0xda,0x8f == ceq.h $w10, $w27, $w9 # encoding: [0x78,0x29,0xda,0x8f] +0x78,0x4e,0x2a,0x4f == ceq.w $w9, $w5, $w14 # encoding: [0x78,0x4e,0x2a,0x4f] +0x78,0x60,0x89,0x4f == ceq.d $w5, $w17, $w0 # encoding: [0x78,0x60,0x89,0x4f] +0x7a,0x09,0x25,0xcf == cle_s.b $w23, $w4, $w9 # encoding: [0x7a,0x09,0x25,0xcf] +0x7a,0x33,0xdd,0x8f == cle_s.h $w22, $w27, $w19 # encoding: [0x7a,0x33,0xdd,0x8f] +0x7a,0x4a,0xd7,0x8f == cle_s.w $w30, $w26, $w10 # encoding: [0x7a,0x4a,0xd7,0x8f] +0x7a,0x6a,0x2c,0x8f == cle_s.d $w18, $w5, $w10 # encoding: [0x7a,0x6a,0x2c,0x8f] +0x7a,0x80,0xc8,0x4f == cle_u.b $w1, $w25, $w0 # encoding: [0x7a,0x80,0xc8,0x4f] +0x7a,0xbd,0x01,0xcf == cle_u.h $w7, $w0, $w29 # encoding: [0x7a,0xbd,0x01,0xcf] +0x7a,0xc1,0x96,0x4f == cle_u.w $w25, $w18, $w1 # encoding: [0x7a,0xc1,0x96,0x4f] +0x7a,0xfe,0x01,0x8f == cle_u.d $w6, $w0, $w30 # encoding: [0x7a,0xfe,0x01,0x8f] +0x79,0x15,0x16,0x4f == clt_s.b $w25, $w2, $w21 # encoding: [0x79,0x15,0x16,0x4f] +0x79,0x29,0x98,0x8f == clt_s.h $w2, $w19, $w9 # encoding: [0x79,0x29,0x98,0x8f] +0x79,0x50,0x45,0xcf == clt_s.w $w23, $w8, $w16 # encoding: [0x79,0x50,0x45,0xcf] +0x79,0x6c,0xf1,0xcf == clt_s.d $w7, $w30, $w12 # encoding: [0x79,0x6c,0xf1,0xcf] +0x79,0x8d,0xf8,0x8f == clt_u.b $w2, $w31, $w13 # encoding: [0x79,0x8d,0xf8,0x8f] +0x79,0xb7,0xfc,0x0f == clt_u.h $w16, $w31, $w23 # encoding: [0x79,0xb7,0xfc,0x0f] +0x79,0xc9,0xc0,0xcf == clt_u.w $w3, $w24, $w9 # encoding: [0x79,0xc9,0xc0,0xcf] +0x79,0xe1,0x01,0xcf == clt_u.d $w7, $w0, $w1 # encoding: [0x79,0xe1,0x01,0xcf] +0x7a,0x12,0x1f,0x52 == div_s.b $w29, $w3, $w18 # encoding: [0x7a,0x12,0x1f,0x52] +0x7a,0x2d,0x84,0x52 == div_s.h $w17, $w16, $w13 # encoding: [0x7a,0x2d,0x84,0x52] +0x7a,0x5e,0xc9,0x12 == div_s.w $w4, $w25, $w30 # encoding: [0x7a,0x5e,0xc9,0x12] +0x7a,0x74,0x4f,0xd2 == div_s.d $w31, $w9, $w20 # encoding: [0x7a,0x74,0x4f,0xd2] +0x7a,0x8a,0xe9,0x92 == div_u.b $w6, $w29, $w10 # encoding: [0x7a,0x8a,0xe9,0x92] +0x7a,0xae,0xae,0x12 == div_u.h $w24, $w21, $w14 # encoding: [0x7a,0xae,0xae,0x12] +0x7a,0xd9,0x77,0x52 == div_u.w $w29, $w14, $w25 # encoding: [0x7a,0xd9,0x77,0x52] +0x7a,0xf5,0x0f,0xd2 == div_u.d $w31, $w1, $w21 # encoding: [0x7a,0xf5,0x0f,0xd2] +0x78,0x39,0xb5,0xd3 == dotp_s.h $w23, $w22, $w25 # encoding: [0x78,0x39,0xb5,0xd3] +0x78,0x45,0x75,0x13 == dotp_s.w $w20, $w14, $w5 # encoding: [0x78,0x45,0x75,0x13] +0x78,0x76,0x14,0x53 == dotp_s.d $w17, $w2, $w22 # encoding: [0x78,0x76,0x14,0x53] +0x78,0xa6,0x13,0x53 == dotp_u.h $w13, $w2, $w6 # encoding: [0x78,0xa6,0x13,0x53] +0x78,0xd5,0xb3,0xd3 == dotp_u.w $w15, $w22, $w21 # encoding: [0x78,0xd5,0xb3,0xd3] +0x78,0xfa,0x81,0x13 == dotp_u.d $w4, $w16, $w26 # encoding: [0x78,0xfa,0x81,0x13] +0x79,0x36,0xe0,0x53 == dpadd_s.h $w1, $w28, $w22 # encoding: [0x79,0x36,0xe0,0x53] +0x79,0x4c,0x0a,0x93 == dpadd_s.w $w10, $w1, $w12 # encoding: [0x79,0x4c,0x0a,0x93] +0x79,0x7b,0xa8,0xd3 == dpadd_s.d $w3, $w21, $w27 # encoding: [0x79,0x7b,0xa8,0xd3] +0x79,0xb4,0x2c,0x53 == dpadd_u.h $w17, $w5, $w20 # encoding: [0x79,0xb4,0x2c,0x53] +0x79,0xd0,0x46,0x13 == dpadd_u.w $w24, $w8, $w16 # encoding: [0x79,0xd0,0x46,0x13] +0x79,0xf0,0xeb,0xd3 == dpadd_u.d $w15, $w29, $w16 # encoding: [0x79,0xf0,0xeb,0xd3] +0x7a,0x2c,0x59,0x13 == dpsub_s.h $w4, $w11, $w12 # encoding: [0x7a,0x2c,0x59,0x13] +0x7a,0x46,0x39,0x13 == dpsub_s.w $w4, $w7, $w6 # encoding: [0x7a,0x46,0x39,0x13] +0x7a,0x7c,0x67,0xd3 == dpsub_s.d $w31, $w12, $w28 # encoding: [0x7a,0x7c,0x67,0xd3] +0x7a,0xb1,0xc9,0x13 == dpsub_u.h $w4, $w25, $w17 # encoding: [0x7a,0xb1,0xc9,0x13] +0x7a,0xd0,0xcc,0xd3 == dpsub_u.w $w19, $w25, $w16 # encoding: [0x7a,0xd0,0xcc,0xd3] +0x7a,0xfa,0x51,0xd3 == dpsub_u.d $w7, $w10, $w26 # encoding: [0x7a,0xfa,0x51,0xd3] +0x7a,0x22,0xc7,0x15 == hadd_s.h $w28, $w24, $w2 # encoding: [0x7a,0x22,0xc7,0x15] +0x7a,0x4b,0x8e,0x15 == hadd_s.w $w24, $w17, $w11 # encoding: [0x7a,0x4b,0x8e,0x15] +0x7a,0x74,0x7c,0x55 == hadd_s.d $w17, $w15, $w20 # encoding: [0x7a,0x74,0x7c,0x55] +0x7a,0xb1,0xeb,0x15 == hadd_u.h $w12, $w29, $w17 # encoding: [0x7a,0xb1,0xeb,0x15] +0x7a,0xc6,0x2a,0x55 == hadd_u.w $w9, $w5, $w6 # encoding: [0x7a,0xc6,0x2a,0x55] +0x7a,0xe6,0xa0,0x55 == hadd_u.d $w1, $w20, $w6 # encoding: [0x7a,0xe6,0xa0,0x55] +0x7b,0x3d,0x74,0x15 == hsub_s.h $w16, $w14, $w29 # encoding: [0x7b,0x3d,0x74,0x15] +0x7b,0x4b,0x6a,0x55 == hsub_s.w $w9, $w13, $w11 # encoding: [0x7b,0x4b,0x6a,0x55] +0x7b,0x6e,0x97,0x95 == hsub_s.d $w30, $w18, $w14 # encoding: [0x7b,0x6e,0x97,0x95] +0x7b,0xae,0x61,0xd5 == hsub_u.h $w7, $w12, $w14 # encoding: [0x7b,0xae,0x61,0xd5] +0x7b,0xc5,0x2d,0x55 == hsub_u.w $w21, $w5, $w5 # encoding: [0x7b,0xc5,0x2d,0x55] +0x7b,0xff,0x62,0xd5 == hsub_u.d $w11, $w12, $w31 # encoding: [0x7b,0xff,0x62,0xd5] +0x7b,0x1e,0x84,0x94 == ilvev.b $w18, $w16, $w30 # encoding: [0x7b,0x1e,0x84,0x94] +0x7b,0x2d,0x03,0x94 == ilvev.h $w14, $w0, $w13 # encoding: [0x7b,0x2d,0x03,0x94] +0x7b,0x56,0xcb,0x14 == ilvev.w $w12, $w25, $w22 # encoding: [0x7b,0x56,0xcb,0x14] +0x7b,0x63,0xdf,0x94 == ilvev.d $w30, $w27, $w3 # encoding: [0x7b,0x63,0xdf,0x94] +0x7a,0x15,0x1f,0x54 == ilvl.b $w29, $w3, $w21 # encoding: [0x7a,0x15,0x1f,0x54] +0x7a,0x31,0x56,0xd4 == ilvl.h $w27, $w10, $w17 # encoding: [0x7a,0x31,0x56,0xd4] +0x7a,0x40,0x09,0x94 == ilvl.w $w6, $w1, $w0 # encoding: [0x7a,0x40,0x09,0x94] +0x7a,0x78,0x80,0xd4 == ilvl.d $w3, $w16, $w24 # encoding: [0x7a,0x78,0x80,0xd4] +0x7b,0x94,0x2a,0xd4 == ilvod.b $w11, $w5, $w20 # encoding: [0x7b,0x94,0x2a,0xd4] +0x7b,0xbf,0x6c,0x94 == ilvod.h $w18, $w13, $w31 # encoding: [0x7b,0xbf,0x6c,0x94] +0x7b,0xd8,0x87,0x54 == ilvod.w $w29, $w16, $w24 # encoding: [0x7b,0xd8,0x87,0x54] +0x7b,0xfd,0x65,0x94 == ilvod.d $w22, $w12, $w29 # encoding: [0x7b,0xfd,0x65,0x94] +0x7a,0x86,0xf1,0x14 == ilvr.b $w4, $w30, $w6 # encoding: [0x7a,0x86,0xf1,0x14] +0x7a,0xbd,0x9f,0x14 == ilvr.h $w28, $w19, $w29 # encoding: [0x7a,0xbd,0x9f,0x14] +0x7a,0xd5,0xa4,0x94 == ilvr.w $w18, $w20, $w21 # encoding: [0x7a,0xd5,0xa4,0x94] +0x7a,0xec,0xf5,0xd4 == ilvr.d $w23, $w30, $w12 # encoding: [0x7a,0xec,0xf5,0xd4] +0x78,0x9d,0xfc,0x52 == maddv.b $w17, $w31, $w29 # encoding: [0x78,0x9d,0xfc,0x52] +0x78,0xa9,0xc1,0xd2 == maddv.h $w7, $w24, $w9 # encoding: [0x78,0xa9,0xc1,0xd2] +0x78,0xd4,0xb5,0x92 == maddv.w $w22, $w22, $w20 # encoding: [0x78,0xd4,0xb5,0x92] +0x78,0xf4,0xd7,0x92 == maddv.d $w30, $w26, $w20 # encoding: [0x78,0xf4,0xd7,0x92] +0x7b,0x17,0x5d,0xce == max_a.b $w23, $w11, $w23 # encoding: [0x7b,0x17,0x5d,0xce] +0x7b,0x3e,0x2d,0x0e == max_a.h $w20, $w5, $w30 # encoding: [0x7b,0x3e,0x2d,0x0e] +0x7b,0x5e,0x91,0xce == max_a.w $w7, $w18, $w30 # encoding: [0x7b,0x5e,0x91,0xce] +0x7b,0x7f,0x42,0x0e == max_a.d $w8, $w8, $w31 # encoding: [0x7b,0x7f,0x42,0x0e] +0x79,0x13,0x0a,0x8e == max_s.b $w10, $w1, $w19 # encoding: [0x79,0x13,0x0a,0x8e] +0x79,0x31,0xeb,0xce == max_s.h $w15, $w29, $w17 # encoding: [0x79,0x31,0xeb,0xce] +0x79,0x4e,0xeb,0xce == max_s.w $w15, $w29, $w14 # encoding: [0x79,0x4e,0xeb,0xce] +0x79,0x63,0xc6,0x4e == max_s.d $w25, $w24, $w3 # encoding: [0x79,0x63,0xc6,0x4e] +0x79,0x85,0xc3,0x0e == max_u.b $w12, $w24, $w5 # encoding: [0x79,0x85,0xc3,0x0e] +0x79,0xa7,0x31,0x4e == max_u.h $w5, $w6, $w7 # encoding: [0x79,0xa7,0x31,0x4e] +0x79,0xc7,0x24,0x0e == max_u.w $w16, $w4, $w7 # encoding: [0x79,0xc7,0x24,0x0e] +0x79,0xf8,0x66,0x8e == max_u.d $w26, $w12, $w24 # encoding: [0x79,0xf8,0x66,0x8e] +0x7b,0x81,0xd1,0x0e == min_a.b $w4, $w26, $w1 # encoding: [0x7b,0x81,0xd1,0x0e] +0x7b,0xbf,0x6b,0x0e == min_a.h $w12, $w13, $w31 # encoding: [0x7b,0xbf,0x6b,0x0e] +0x7b,0xc0,0xa7,0x0e == min_a.w $w28, $w20, $w0 # encoding: [0x7b,0xc0,0xa7,0x0e] +0x7b,0xf3,0xa3,0x0e == min_a.d $w12, $w20, $w19 # encoding: [0x7b,0xf3,0xa3,0x0e] +0x7a,0x0e,0x1c,0xce == min_s.b $w19, $w3, $w14 # encoding: [0x7a,0x0e,0x1c,0xce] +0x7a,0x28,0xae,0xce == min_s.h $w27, $w21, $w8 # encoding: [0x7a,0x28,0xae,0xce] +0x7a,0x5e,0x70,0x0e == min_s.w $w0, $w14, $w30 # encoding: [0x7a,0x5e,0x70,0x0e] +0x7a,0x75,0x41,0x8e == min_s.d $w6, $w8, $w21 # encoding: [0x7a,0x75,0x41,0x8e] +0x7a,0x88,0xd5,0x8e == min_u.b $w22, $w26, $w8 # encoding: [0x7a,0x88,0xd5,0x8e] +0x7a,0xac,0xd9,0xce == min_u.h $w7, $w27, $w12 # encoding: [0x7a,0xac,0xd9,0xce] +0x7a,0xce,0xa2,0x0e == min_u.w $w8, $w20, $w14 # encoding: [0x7a,0xce,0xa2,0x0e] +0x7a,0xef,0x76,0x8e == min_u.d $w26, $w14, $w15 # encoding: [0x7a,0xef,0x76,0x8e] +0x7b,0x1a,0x0c,0x92 == mod_s.b $w18, $w1, $w26 # encoding: [0x7b,0x1a,0x0c,0x92] +0x7b,0x3c,0xf7,0xd2 == mod_s.h $w31, $w30, $w28 # encoding: [0x7b,0x3c,0xf7,0xd2] +0x7b,0x4d,0x30,0x92 == mod_s.w $w2, $w6, $w13 # encoding: [0x7b,0x4d,0x30,0x92] +0x7b,0x76,0xdd,0x52 == mod_s.d $w21, $w27, $w22 # encoding: [0x7b,0x76,0xdd,0x52] +0x7b,0x8d,0x3c,0x12 == mod_u.b $w16, $w7, $w13 # encoding: [0x7b,0x8d,0x3c,0x12] +0x7b,0xa7,0x46,0x12 == mod_u.h $w24, $w8, $w7 # encoding: [0x7b,0xa7,0x46,0x12] +0x7b,0xd1,0x17,0x92 == mod_u.w $w30, $w2, $w17 # encoding: [0x7b,0xd1,0x17,0x92] +0x7b,0xf9,0x17,0xd2 == mod_u.d $w31, $w2, $w25 # encoding: [0x7b,0xf9,0x17,0xd2] +0x79,0x0c,0x2b,0x92 == msubv.b $w14, $w5, $w12 # encoding: [0x79,0x0c,0x2b,0x92] +0x79,0x3e,0x39,0x92 == msubv.h $w6, $w7, $w30 # encoding: [0x79,0x3e,0x39,0x92] +0x79,0x55,0x13,0x52 == msubv.w $w13, $w2, $w21 # encoding: [0x79,0x55,0x13,0x52] +0x79,0x7b,0x74,0x12 == msubv.d $w16, $w14, $w27 # encoding: [0x79,0x7b,0x74,0x12] +0x78,0x0d,0x1d,0x12 == mulv.b $w20, $w3, $w13 # encoding: [0x78,0x0d,0x1d,0x12] +0x78,0x2e,0xd6,0xd2 == mulv.h $w27, $w26, $w14 # encoding: [0x78,0x2e,0xd6,0xd2] +0x78,0x43,0xea,0x92 == mulv.w $w10, $w29, $w3 # encoding: [0x78,0x43,0xea,0x92] +0x78,0x7d,0x99,0xd2 == mulv.d $w7, $w19, $w29 # encoding: [0x78,0x7d,0x99,0xd2] +0x79,0x07,0xd9,0x54 == pckev.b $w5, $w27, $w7 # encoding: [0x79,0x07,0xd9,0x54] +0x79,0x3b,0x20,0x54 == pckev.h $w1, $w4, $w27 # encoding: [0x79,0x3b,0x20,0x54] +0x79,0x40,0xa7,0x94 == pckev.w $w30, $w20, $w0 # encoding: [0x79,0x40,0xa7,0x94] +0x79,0x6f,0x09,0x94 == pckev.d $w6, $w1, $w15 # encoding: [0x79,0x6f,0x09,0x94] +0x79,0x9e,0xe4,0x94 == pckod.b $w18, $w28, $w30 # encoding: [0x79,0x9e,0xe4,0x94] +0x79,0xa8,0x2e,0x94 == pckod.h $w26, $w5, $w8 # encoding: [0x79,0xa8,0x2e,0x94] +0x79,0xc2,0x22,0x54 == pckod.w $w9, $w4, $w2 # encoding: [0x79,0xc2,0x22,0x54] +0x79,0xf4,0xb7,0x94 == pckod.d $w30, $w22, $w20 # encoding: [0x79,0xf4,0xb7,0x94] +0x78,0x0c,0xb9,0x54 == sld.b $w5, $w23[$12] # encoding: [0x78,0x0c,0xb9,0x54] +0x78,0x23,0xb8,0x54 == sld.h $w1, $w23[$3] # encoding: [0x78,0x23,0xb8,0x54] +0x78,0x49,0x45,0x14 == sld.w $w20, $w8[$9] # encoding: [0x78,0x49,0x45,0x14] +0x78,0x7e,0xb9,0xd4 == sld.d $w7, $w23[$fp] # encoding: [0x78,0x7e,0xb9,0xd4] +0x78,0x11,0x00,0xcd == sll.b $w3, $w0, $w17 # encoding: [0x78,0x11,0x00,0xcd] +0x78,0x23,0xdc,0x4d == sll.h $w17, $w27, $w3 # encoding: [0x78,0x23,0xdc,0x4d] +0x78,0x46,0x3c,0x0d == sll.w $w16, $w7, $w6 # encoding: [0x78,0x46,0x3c,0x0d] +0x78,0x7a,0x02,0x4d == sll.d $w9, $w0, $w26 # encoding: [0x78,0x7a,0x02,0x4d] +0x78,0x81,0x0f,0x14 == splat.b $w28, $w1[$1] # encoding: [0x78,0x81,0x0f,0x14] +0x78,0xab,0x58,0x94 == splat.h $w2, $w11[$11] # encoding: [0x78,0xab,0x58,0x94] +0x78,0xcb,0x05,0x94 == splat.w $w22, $w0[$11] # encoding: [0x78,0xcb,0x05,0x94] +0x78,0xe2,0x00,0x14 == splat.d $w0, $w0[$2] # encoding: [0x78,0xe2,0x00,0x14] +0x78,0x91,0x27,0x0d == sra.b $w28, $w4, $w17 # encoding: [0x78,0x91,0x27,0x0d] +0x78,0xa3,0x4b,0x4d == sra.h $w13, $w9, $w3 # encoding: [0x78,0xa3,0x4b,0x4d] +0x78,0xd3,0xae,0xcd == sra.w $w27, $w21, $w19 # encoding: [0x78,0xd3,0xae,0xcd] +0x78,0xf7,0x47,0x8d == sra.d $w30, $w8, $w23 # encoding: [0x78,0xf7,0x47,0x8d] +0x78,0x92,0x94,0xd5 == srar.b $w19, $w18, $w18 # encoding: [0x78,0x92,0x94,0xd5] +0x78,0xa8,0xb9,0xd5 == srar.h $w7, $w23, $w8 # encoding: [0x78,0xa8,0xb9,0xd5] +0x78,0xc2,0x60,0x55 == srar.w $w1, $w12, $w2 # encoding: [0x78,0xc2,0x60,0x55] +0x78,0xee,0x3d,0x55 == srar.d $w21, $w7, $w14 # encoding: [0x78,0xee,0x3d,0x55] +0x79,0x13,0x1b,0x0d == srl.b $w12, $w3, $w19 # encoding: [0x79,0x13,0x1b,0x0d] +0x79,0x34,0xfd,0xcd == srl.h $w23, $w31, $w20 # encoding: [0x79,0x34,0xfd,0xcd] +0x79,0x4b,0xdc,0x8d == srl.w $w18, $w27, $w11 # encoding: [0x79,0x4b,0xdc,0x8d] +0x79,0x7a,0x60,0xcd == srl.d $w3, $w12, $w26 # encoding: [0x79,0x7a,0x60,0xcd] +0x79,0x0b,0xab,0xd5 == srlr.b $w15, $w21, $w11 # encoding: [0x79,0x0b,0xab,0xd5] +0x79,0x33,0x6d,0x55 == srlr.h $w21, $w13, $w19 # encoding: [0x79,0x33,0x6d,0x55] +0x79,0x43,0xf1,0x95 == srlr.w $w6, $w30, $w3 # encoding: [0x79,0x43,0xf1,0x95] +0x79,0x6e,0x10,0x55 == srlr.d $w1, $w2, $w14 # encoding: [0x79,0x6e,0x10,0x55] +0x78,0x01,0x7e,0x51 == subs_s.b $w25, $w15, $w1 # encoding: [0x78,0x01,0x7e,0x51] +0x78,0x36,0xcf,0x11 == subs_s.h $w28, $w25, $w22 # encoding: [0x78,0x36,0xcf,0x11] +0x78,0x55,0x62,0x91 == subs_s.w $w10, $w12, $w21 # encoding: [0x78,0x55,0x62,0x91] +0x78,0x72,0xa1,0x11 == subs_s.d $w4, $w20, $w18 # encoding: [0x78,0x72,0xa1,0x11] +0x78,0x99,0x35,0x51 == subs_u.b $w21, $w6, $w25 # encoding: [0x78,0x99,0x35,0x51] +0x78,0xa7,0x50,0xd1 == subs_u.h $w3, $w10, $w7 # encoding: [0x78,0xa7,0x50,0xd1] +0x78,0xca,0x7a,0x51 == subs_u.w $w9, $w15, $w10 # encoding: [0x78,0xca,0x7a,0x51] +0x78,0xea,0x99,0xd1 == subs_u.d $w7, $w19, $w10 # encoding: [0x78,0xea,0x99,0xd1] +0x79,0x0c,0x39,0x91 == subsus_u.b $w6, $w7, $w12 # encoding: [0x79,0x0c,0x39,0x91] +0x79,0x33,0xe9,0x91 == subsus_u.h $w6, $w29, $w19 # encoding: [0x79,0x33,0xe9,0x91] +0x79,0x47,0x79,0xd1 == subsus_u.w $w7, $w15, $w7 # encoding: [0x79,0x47,0x79,0xd1] +0x79,0x6f,0x1a,0x51 == subsus_u.d $w9, $w3, $w15 # encoding: [0x79,0x6f,0x1a,0x51] +0x79,0x9f,0x1d,0x91 == subsuu_s.b $w22, $w3, $w31 # encoding: [0x79,0x9f,0x1d,0x91] +0x79,0xb6,0xbc,0xd1 == subsuu_s.h $w19, $w23, $w22 # encoding: [0x79,0xb6,0xbc,0xd1] +0x79,0xcd,0x52,0x51 == subsuu_s.w $w9, $w10, $w13 # encoding: [0x79,0xcd,0x52,0x51] +0x79,0xe0,0x31,0x51 == subsuu_s.d $w5, $w6, $w0 # encoding: [0x79,0xe0,0x31,0x51] +0x78,0x93,0x69,0x8e == subv.b $w6, $w13, $w19 # encoding: [0x78,0x93,0x69,0x8e] +0x78,0xac,0xc9,0x0e == subv.h $w4, $w25, $w12 # encoding: [0x78,0xac,0xc9,0x0e] +0x78,0xcb,0xde,0xce == subv.w $w27, $w27, $w11 # encoding: [0x78,0xcb,0xde,0xce] +0x78,0xea,0xc2,0x4e == subv.d $w9, $w24, $w10 # encoding: [0x78,0xea,0xc2,0x4e] +0x78,0x05,0x80,0xd5 == vshf.b $w3, $w16, $w5 # encoding: [0x78,0x05,0x80,0xd5] +0x78,0x28,0x9d,0x15 == vshf.h $w20, $w19, $w8 # encoding: [0x78,0x28,0x9d,0x15] +0x78,0x59,0xf4,0x15 == vshf.w $w16, $w30, $w25 # encoding: [0x78,0x59,0xf4,0x15] +0x78,0x6f,0x5c,0xd5 == vshf.d $w19, $w11, $w15 # encoding: [0x78,0x6f,0x5c,0xd5] diff --git a/suite/MC/Mips/test_3rf.s.cs b/suite/MC/Mips/test_3rf.s.cs index 491162d481..7111745f26 100644 --- a/suite/MC/Mips/test_3rf.s.cs +++ b/suite/MC/Mips/test_3rf.s.cs @@ -1,83 +1,84 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x78,0x1c,0x9f,0x1b = fadd.w $w28, $w19, $w28 -0x78,0x3d,0x13,0x5b = fadd.d $w13, $w2, $w29 -0x78,0x19,0x5b,0x9a = fcaf.w $w14, $w11, $w25 -0x78,0x33,0x08,0x5a = fcaf.d $w1, $w1, $w19 -0x78,0x90,0xb8,0x5a = fceq.w $w1, $w23, $w16 -0x78,0xb0,0x40,0x1a = fceq.d $w0, $w8, $w16 -0x79,0x98,0x4c,0x1a = fcle.w $w16, $w9, $w24 -0x79,0xa1,0x76,0xda = fcle.d $w27, $w14, $w1 -0x79,0x08,0x47,0x1a = fclt.w $w28, $w8, $w8 -0x79,0x2b,0xcf,0x9a = fclt.d $w30, $w25, $w11 -0x78,0xd7,0x90,0x9c = fcne.w $w2, $w18, $w23 -0x78,0xef,0xa3,0x9c = fcne.d $w14, $w20, $w15 -0x78,0x59,0x92,0x9c = fcor.w $w10, $w18, $w25 -0x78,0x6b,0xcc,0x5c = fcor.d $w17, $w25, $w11 -0x78,0xd5,0x13,0x9a = fcueq.w $w14, $w2, $w21 -0x78,0xe7,0x1f,0x5a = fcueq.d $w29, $w3, $w7 -0x79,0xc3,0x2c,0x5a = fcule.w $w17, $w5, $w3 -0x79,0xfe,0x0f,0xda = fcule.d $w31, $w1, $w30 -0x79,0x49,0xc9,0x9a = fcult.w $w6, $w25, $w9 -0x79,0x71,0x46,0xda = fcult.d $w27, $w8, $w17 -0x78,0x48,0xa1,0x1a = fcun.w $w4, $w20, $w8 -0x78,0x63,0x5f,0x5a = fcun.d $w29, $w11, $w3 -0x78,0x93,0x93,0x5c = fcune.w $w13, $w18, $w19 -0x78,0xb5,0xd4,0x1c = fcune.d $w16, $w26, $w21 -0x78,0xc2,0xc3,0x5b = fdiv.w $w13, $w24, $w2 -0x78,0xf9,0x24,0xdb = fdiv.d $w19, $w4, $w25 -0x7a,0x10,0x02,0x1b = fexdo.h $w8, $w0, $w16 -0x7a,0x3b,0x68,0x1b = fexdo.w $w0, $w13, $w27 -0x79,0xc3,0x04,0x5b = fexp2.w $w17, $w0, $w3 -0x79,0xea,0x05,0x9b = fexp2.d $w22, $w0, $w10 -0x79,0x17,0x37,0x5b = fmadd.w $w29, $w6, $w23 -0x79,0x35,0xe2,0xdb = fmadd.d $w11, $w28, $w21 -0x7b,0x8d,0xb8,0x1b = fmax.w $w0, $w23, $w13 -0x7b,0xa8,0x96,0x9b = fmax.d $w26, $w18, $w8 -0x7b,0xca,0x82,0x9b = fmax_a.w $w10, $w16, $w10 -0x7b,0xf6,0x4f,0x9b = fmax_a.d $w30, $w9, $w22 -0x7b,0x1e,0x0e,0x1b = fmin.w $w24, $w1, $w30 -0x7b,0x2a,0xde,0xdb = fmin.d $w27, $w27, $w10 -0x7b,0x54,0xea,0x9b = fmin_a.w $w10, $w29, $w20 -0x7b,0x78,0xf3,0x5b = fmin_a.d $w13, $w30, $w24 -0x79,0x40,0xcc,0x5b = fmsub.w $w17, $w25, $w0 -0x79,0x70,0x92,0x1b = fmsub.d $w8, $w18, $w16 -0x78,0x8f,0x78,0xdb = fmul.w $w3, $w15, $w15 -0x78,0xaa,0xf2,0x5b = fmul.d $w9, $w30, $w10 -0x7a,0x0a,0x2e,0x5a = fsaf.w $w25, $w5, $w10 -0x7a,0x3d,0x1e,0x5a = fsaf.d $w25, $w3, $w29 -0x7a,0x8d,0x8a,0xda = fseq.w $w11, $w17, $w13 -0x7a,0xbf,0x07,0x5a = fseq.d $w29, $w0, $w31 -0x7b,0x9f,0xff,0x9a = fsle.w $w30, $w31, $w31 -0x7b,0xb8,0xbc,0x9a = fsle.d $w18, $w23, $w24 -0x7b,0x06,0x2b,0x1a = fslt.w $w12, $w5, $w6 -0x7b,0x35,0xd4,0x1a = fslt.d $w16, $w26, $w21 -0x7a,0xcc,0x0f,0x9c = fsne.w $w30, $w1, $w12 -0x7a,0xf7,0x6b,0x9c = fsne.d $w14, $w13, $w23 -0x7a,0x5b,0x6e,0xdc = fsor.w $w27, $w13, $w27 -0x7a,0x6b,0xc3,0x1c = fsor.d $w12, $w24, $w11 -0x78,0x41,0xd7,0xdb = fsub.w $w31, $w26, $w1 -0x78,0x7b,0x8c,0xdb = fsub.d $w19, $w17, $w27 -0x7a,0xd9,0xc4,0x1a = fsueq.w $w16, $w24, $w25 -0x7a,0xee,0x74,0x9a = fsueq.d $w18, $w14, $w14 -0x7b,0xcd,0xf5,0xda = fsule.w $w23, $w30, $w13 -0x7b,0xfa,0x58,0x9a = fsule.d $w2, $w11, $w26 -0x7b,0x56,0xd2,0xda = fsult.w $w11, $w26, $w22 -0x7b,0x7e,0xb9,0x9a = fsult.d $w6, $w23, $w30 -0x7a,0x5c,0x90,0xda = fsun.w $w3, $w18, $w28 -0x7a,0x73,0x5c,0x9a = fsun.d $w18, $w11, $w19 -0x7a,0x82,0xfc,0x1c = fsune.w $w16, $w31, $w2 -0x7a,0xb1,0xd0,0xdc = fsune.d $w3, $w26, $w17 -0x7a,0x98,0x24,0x1b = ftq.h $w16, $w4, $w24 -0x7a,0xb9,0x29,0x5b = ftq.w $w5, $w5, $w25 -0x79,0x4a,0xa4,0x1c = madd_q.h $w16, $w20, $w10 -0x79,0x69,0x17,0x1c = madd_q.w $w28, $w2, $w9 -0x7b,0x49,0x92,0x1c = maddr_q.h $w8, $w18, $w9 -0x7b,0x70,0x67,0x5c = maddr_q.w $w29, $w12, $w16 -0x79,0x8a,0xd6,0x1c = msub_q.h $w24, $w26, $w10 -0x79,0xbc,0xf3,0x5c = msub_q.w $w13, $w30, $w28 -0x7b,0x8b,0xab,0x1c = msubr_q.h $w12, $w21, $w11 -0x7b,0xb4,0x70,0x5c = msubr_q.w $w1, $w14, $w20 -0x79,0x1e,0x81,0x9c = mul_q.h $w6, $w16, $w30 -0x79,0x24,0x0c,0x1c = mul_q.w $w16, $w1, $w4 -0x7b,0x13,0xa1,0x9c = mulr_q.h $w6, $w20, $w19 -0x7b,0x34,0x0e,0xdc = mulr_q.w $w27, $w1, $w20 + +0x78,0x1c,0x9f,0x1b == fadd.w $w28, $w19, $w28 # encoding: [0x78,0x1c,0x9f,0x1b] +0x78,0x3d,0x13,0x5b == fadd.d $w13, $w2, $w29 # encoding: [0x78,0x3d,0x13,0x5b] +0x78,0x19,0x5b,0x9a == fcaf.w $w14, $w11, $w25 # encoding: [0x78,0x19,0x5b,0x9a] +0x78,0x33,0x08,0x5a == fcaf.d $w1, $w1, $w19 # encoding: [0x78,0x33,0x08,0x5a] +0x78,0x90,0xb8,0x5a == fceq.w $w1, $w23, $w16 # encoding: [0x78,0x90,0xb8,0x5a] +0x78,0xb0,0x40,0x1a == fceq.d $w0, $w8, $w16 # encoding: [0x78,0xb0,0x40,0x1a] +0x79,0x98,0x4c,0x1a == fcle.w $w16, $w9, $w24 # encoding: [0x79,0x98,0x4c,0x1a] +0x79,0xa1,0x76,0xda == fcle.d $w27, $w14, $w1 # encoding: [0x79,0xa1,0x76,0xda] +0x79,0x08,0x47,0x1a == fclt.w $w28, $w8, $w8 # encoding: [0x79,0x08,0x47,0x1a] +0x79,0x2b,0xcf,0x9a == fclt.d $w30, $w25, $w11 # encoding: [0x79,0x2b,0xcf,0x9a] +0x78,0xd7,0x90,0x9c == fcne.w $w2, $w18, $w23 # encoding: [0x78,0xd7,0x90,0x9c] +0x78,0xef,0xa3,0x9c == fcne.d $w14, $w20, $w15 # encoding: [0x78,0xef,0xa3,0x9c] +0x78,0x59,0x92,0x9c == fcor.w $w10, $w18, $w25 # encoding: [0x78,0x59,0x92,0x9c] +0x78,0x6b,0xcc,0x5c == fcor.d $w17, $w25, $w11 # encoding: [0x78,0x6b,0xcc,0x5c] +0x78,0xd5,0x13,0x9a == fcueq.w $w14, $w2, $w21 # encoding: [0x78,0xd5,0x13,0x9a] +0x78,0xe7,0x1f,0x5a == fcueq.d $w29, $w3, $w7 # encoding: [0x78,0xe7,0x1f,0x5a] +0x79,0xc3,0x2c,0x5a == fcule.w $w17, $w5, $w3 # encoding: [0x79,0xc3,0x2c,0x5a] +0x79,0xfe,0x0f,0xda == fcule.d $w31, $w1, $w30 # encoding: [0x79,0xfe,0x0f,0xda] +0x79,0x49,0xc9,0x9a == fcult.w $w6, $w25, $w9 # encoding: [0x79,0x49,0xc9,0x9a] +0x79,0x71,0x46,0xda == fcult.d $w27, $w8, $w17 # encoding: [0x79,0x71,0x46,0xda] +0x78,0x48,0xa1,0x1a == fcun.w $w4, $w20, $w8 # encoding: [0x78,0x48,0xa1,0x1a] +0x78,0x63,0x5f,0x5a == fcun.d $w29, $w11, $w3 # encoding: [0x78,0x63,0x5f,0x5a] +0x78,0x93,0x93,0x5c == fcune.w $w13, $w18, $w19 # encoding: [0x78,0x93,0x93,0x5c] +0x78,0xb5,0xd4,0x1c == fcune.d $w16, $w26, $w21 # encoding: [0x78,0xb5,0xd4,0x1c] +0x78,0xc2,0xc3,0x5b == fdiv.w $w13, $w24, $w2 # encoding: [0x78,0xc2,0xc3,0x5b] +0x78,0xf9,0x24,0xdb == fdiv.d $w19, $w4, $w25 # encoding: [0x78,0xf9,0x24,0xdb] +0x7a,0x10,0x02,0x1b == fexdo.h $w8, $w0, $w16 # encoding: [0x7a,0x10,0x02,0x1b] +0x7a,0x3b,0x68,0x1b == fexdo.w $w0, $w13, $w27 # encoding: [0x7a,0x3b,0x68,0x1b] +0x79,0xc3,0x04,0x5b == fexp2.w $w17, $w0, $w3 # encoding: [0x79,0xc3,0x04,0x5b] +0x79,0xea,0x05,0x9b == fexp2.d $w22, $w0, $w10 # encoding: [0x79,0xea,0x05,0x9b] +0x79,0x17,0x37,0x5b == fmadd.w $w29, $w6, $w23 # encoding: [0x79,0x17,0x37,0x5b] +0x79,0x35,0xe2,0xdb == fmadd.d $w11, $w28, $w21 # encoding: [0x79,0x35,0xe2,0xdb] +0x7b,0x8d,0xb8,0x1b == fmax.w $w0, $w23, $w13 # encoding: [0x7b,0x8d,0xb8,0x1b] +0x7b,0xa8,0x96,0x9b == fmax.d $w26, $w18, $w8 # encoding: [0x7b,0xa8,0x96,0x9b] +0x7b,0xca,0x82,0x9b == fmax_a.w $w10, $w16, $w10 # encoding: [0x7b,0xca,0x82,0x9b] +0x7b,0xf6,0x4f,0x9b == fmax_a.d $w30, $w9, $w22 # encoding: [0x7b,0xf6,0x4f,0x9b] +0x7b,0x1e,0x0e,0x1b == fmin.w $w24, $w1, $w30 # encoding: [0x7b,0x1e,0x0e,0x1b] +0x7b,0x2a,0xde,0xdb == fmin.d $w27, $w27, $w10 # encoding: [0x7b,0x2a,0xde,0xdb] +0x7b,0x54,0xea,0x9b == fmin_a.w $w10, $w29, $w20 # encoding: [0x7b,0x54,0xea,0x9b] +0x7b,0x78,0xf3,0x5b == fmin_a.d $w13, $w30, $w24 # encoding: [0x7b,0x78,0xf3,0x5b] +0x79,0x40,0xcc,0x5b == fmsub.w $w17, $w25, $w0 # encoding: [0x79,0x40,0xcc,0x5b] +0x79,0x70,0x92,0x1b == fmsub.d $w8, $w18, $w16 # encoding: [0x79,0x70,0x92,0x1b] +0x78,0x8f,0x78,0xdb == fmul.w $w3, $w15, $w15 # encoding: [0x78,0x8f,0x78,0xdb] +0x78,0xaa,0xf2,0x5b == fmul.d $w9, $w30, $w10 # encoding: [0x78,0xaa,0xf2,0x5b] +0x7a,0x0a,0x2e,0x5a == fsaf.w $w25, $w5, $w10 # encoding: [0x7a,0x0a,0x2e,0x5a] +0x7a,0x3d,0x1e,0x5a == fsaf.d $w25, $w3, $w29 # encoding: [0x7a,0x3d,0x1e,0x5a] +0x7a,0x8d,0x8a,0xda == fseq.w $w11, $w17, $w13 # encoding: [0x7a,0x8d,0x8a,0xda] +0x7a,0xbf,0x07,0x5a == fseq.d $w29, $w0, $w31 # encoding: [0x7a,0xbf,0x07,0x5a] +0x7b,0x9f,0xff,0x9a == fsle.w $w30, $w31, $w31 # encoding: [0x7b,0x9f,0xff,0x9a] +0x7b,0xb8,0xbc,0x9a == fsle.d $w18, $w23, $w24 # encoding: [0x7b,0xb8,0xbc,0x9a] +0x7b,0x06,0x2b,0x1a == fslt.w $w12, $w5, $w6 # encoding: [0x7b,0x06,0x2b,0x1a] +0x7b,0x35,0xd4,0x1a == fslt.d $w16, $w26, $w21 # encoding: [0x7b,0x35,0xd4,0x1a] +0x7a,0xcc,0x0f,0x9c == fsne.w $w30, $w1, $w12 # encoding: [0x7a,0xcc,0x0f,0x9c] +0x7a,0xf7,0x6b,0x9c == fsne.d $w14, $w13, $w23 # encoding: [0x7a,0xf7,0x6b,0x9c] +0x7a,0x5b,0x6e,0xdc == fsor.w $w27, $w13, $w27 # encoding: [0x7a,0x5b,0x6e,0xdc] +0x7a,0x6b,0xc3,0x1c == fsor.d $w12, $w24, $w11 # encoding: [0x7a,0x6b,0xc3,0x1c] +0x78,0x41,0xd7,0xdb == fsub.w $w31, $w26, $w1 # encoding: [0x78,0x41,0xd7,0xdb] +0x78,0x7b,0x8c,0xdb == fsub.d $w19, $w17, $w27 # encoding: [0x78,0x7b,0x8c,0xdb] +0x7a,0xd9,0xc4,0x1a == fsueq.w $w16, $w24, $w25 # encoding: [0x7a,0xd9,0xc4,0x1a] +0x7a,0xee,0x74,0x9a == fsueq.d $w18, $w14, $w14 # encoding: [0x7a,0xee,0x74,0x9a] +0x7b,0xcd,0xf5,0xda == fsule.w $w23, $w30, $w13 # encoding: [0x7b,0xcd,0xf5,0xda] +0x7b,0xfa,0x58,0x9a == fsule.d $w2, $w11, $w26 # encoding: [0x7b,0xfa,0x58,0x9a] +0x7b,0x56,0xd2,0xda == fsult.w $w11, $w26, $w22 # encoding: [0x7b,0x56,0xd2,0xda] +0x7b,0x7e,0xb9,0x9a == fsult.d $w6, $w23, $w30 # encoding: [0x7b,0x7e,0xb9,0x9a] +0x7a,0x5c,0x90,0xda == fsun.w $w3, $w18, $w28 # encoding: [0x7a,0x5c,0x90,0xda] +0x7a,0x73,0x5c,0x9a == fsun.d $w18, $w11, $w19 # encoding: [0x7a,0x73,0x5c,0x9a] +0x7a,0x82,0xfc,0x1c == fsune.w $w16, $w31, $w2 # encoding: [0x7a,0x82,0xfc,0x1c] +0x7a,0xb1,0xd0,0xdc == fsune.d $w3, $w26, $w17 # encoding: [0x7a,0xb1,0xd0,0xdc] +0x7a,0x98,0x24,0x1b == ftq.h $w16, $w4, $w24 # encoding: [0x7a,0x98,0x24,0x1b] +0x7a,0xb9,0x29,0x5b == ftq.w $w5, $w5, $w25 # encoding: [0x7a,0xb9,0x29,0x5b] +0x79,0x4a,0xa4,0x1c == madd_q.h $w16, $w20, $w10 # encoding: [0x79,0x4a,0xa4,0x1c] +0x79,0x69,0x17,0x1c == madd_q.w $w28, $w2, $w9 # encoding: [0x79,0x69,0x17,0x1c] +0x7b,0x49,0x92,0x1c == maddr_q.h $w8, $w18, $w9 # encoding: [0x7b,0x49,0x92,0x1c] +0x7b,0x70,0x67,0x5c == maddr_q.w $w29, $w12, $w16 # encoding: [0x7b,0x70,0x67,0x5c] +0x79,0x8a,0xd6,0x1c == msub_q.h $w24, $w26, $w10 # encoding: [0x79,0x8a,0xd6,0x1c] +0x79,0xbc,0xf3,0x5c == msub_q.w $w13, $w30, $w28 # encoding: [0x79,0xbc,0xf3,0x5c] +0x7b,0x8b,0xab,0x1c == msubr_q.h $w12, $w21, $w11 # encoding: [0x7b,0x8b,0xab,0x1c] +0x7b,0xb4,0x70,0x5c == msubr_q.w $w1, $w14, $w20 # encoding: [0x7b,0xb4,0x70,0x5c] +0x79,0x1e,0x81,0x9c == mul_q.h $w6, $w16, $w30 # encoding: [0x79,0x1e,0x81,0x9c] +0x79,0x24,0x0c,0x1c == mul_q.w $w16, $w1, $w4 # encoding: [0x79,0x24,0x0c,0x1c] +0x7b,0x13,0xa1,0x9c == mulr_q.h $w6, $w20, $w19 # encoding: [0x7b,0x13,0xa1,0x9c] +0x7b,0x34,0x0e,0xdc == mulr_q.w $w27, $w1, $w20 # encoding: [0x7b,0x34,0x0e,0xdc] diff --git a/suite/MC/Mips/test_bit.s.cs b/suite/MC/Mips/test_bit.s.cs index 882cd90204..1f714a5ebb 100644 --- a/suite/MC/Mips/test_bit.s.cs +++ b/suite/MC/Mips/test_bit.s.cs @@ -1,49 +1,50 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x79,0xf2,0xf5,0x49 = bclri.b $w21, $w30, 2 -0x79,0xe0,0xae,0x09 = bclri.h $w24, $w21, 0 -0x79,0xc3,0xf5,0xc9 = bclri.w $w23, $w30, 3 -0x79,0x80,0x5a,0x49 = bclri.d $w9, $w11, 0 -0x7b,0x71,0x66,0x49 = binsli.b $w25, $w12, 1 -0x7b,0x60,0xb5,0x49 = binsli.h $w21, $w22, 0 -0x7b,0x40,0x25,0x89 = binsli.w $w22, $w4, 0 -0x7b,0x06,0x11,0x89 = binsli.d $w6, $w2, 6 -0x7b,0xf0,0x9b,0xc9 = binsri.b $w15, $w19, 0 -0x7b,0xe1,0xf2,0x09 = binsri.h $w8, $w30, 1 -0x7b,0xc5,0x98,0x89 = binsri.w $w2, $w19, 5 -0x7b,0x81,0xa4,0x89 = binsri.d $w18, $w20, 1 -0x7a,0xf0,0x9e,0x09 = bnegi.b $w24, $w19, 0 -0x7a,0xe3,0x5f,0x09 = bnegi.h $w28, $w11, 3 -0x7a,0xc5,0xd8,0x49 = bnegi.w $w1, $w27, 5 -0x7a,0x81,0xa9,0x09 = bnegi.d $w4, $w21, 1 -0x7a,0x70,0x44,0x89 = bseti.b $w18, $w8, 0 -0x7a,0x62,0x76,0x09 = bseti.h $w24, $w14, 2 -0x7a,0x44,0x92,0x49 = bseti.w $w9, $w18, 4 -0x7a,0x01,0x79,0xc9 = bseti.d $w7, $w15, 1 -0x78,0x72,0xff,0xca = sat_s.b $w31, $w31, 2 -0x78,0x60,0x9c,0xca = sat_s.h $w19, $w19, 0 -0x78,0x40,0xec,0xca = sat_s.w $w19, $w29, 0 -0x78,0x00,0xb2,0xca = sat_s.d $w11, $w22, 0 -0x78,0xf3,0x68,0x4a = sat_u.b $w1, $w13, 3 -0x78,0xe4,0xc7,0x8a = sat_u.h $w30, $w24, 4 -0x78,0xc0,0x6f,0xca = sat_u.w $w31, $w13, 0 -0x78,0x85,0x87,0x4a = sat_u.d $w29, $w16, 5 -0x78,0x71,0x55,0xc9 = slli.b $w23, $w10, 1 -0x78,0x61,0x92,0x49 = slli.h $w9, $w18, 1 -0x78,0x44,0xea,0xc9 = slli.w $w11, $w29, 4 -0x78,0x01,0xa6,0x49 = slli.d $w25, $w20, 1 -0x78,0xf1,0xee,0x09 = srai.b $w24, $w29, 1 -0x78,0xe0,0x30,0x49 = srai.h $w1, $w6, 0 -0x78,0xc1,0xd1,0xc9 = srai.w $w7, $w26, 1 -0x78,0x83,0xcd,0x09 = srai.d $w20, $w25, 3 -0x79,0x70,0xc9,0x4a = srari.b $w5, $w25, 0 -0x79,0x64,0x31,0xca = srari.h $w7, $w6, 4 -0x79,0x45,0x5c,0x4a = srari.w $w17, $w11, 5 -0x79,0x05,0xcd,0x4a = srari.d $w21, $w25, 5 -0x79,0x72,0x00,0x89 = srli.b $w2, $w0, 2 -0x79,0x62,0xff,0xc9 = srli.h $w31, $w31, 2 -0x79,0x44,0x49,0x49 = srli.w $w5, $w9, 4 -0x79,0x05,0xd6,0xc9 = srli.d $w27, $w26, 5 -0x79,0xf0,0x1c,0x8a = srlri.b $w18, $w3, 0 -0x79,0xe3,0x10,0x4a = srlri.h $w1, $w2, 3 -0x79,0xc2,0xb2,0xca = srlri.w $w11, $w22, 2 -0x79,0x86,0x56,0x0a = srlri.d $w24, $w10, 6 + +0x79,0xf2,0xf5,0x49 == bclri.b $w21, $w30, 2 # encoding: [0x79,0xf2,0xf5,0x49] +0x79,0xe0,0xae,0x09 == bclri.h $w24, $w21, 0 # encoding: [0x79,0xe0,0xae,0x09] +0x79,0xc3,0xf5,0xc9 == bclri.w $w23, $w30, 3 # encoding: [0x79,0xc3,0xf5,0xc9] +0x79,0x80,0x5a,0x49 == bclri.d $w9, $w11, 0 # encoding: [0x79,0x80,0x5a,0x49] +0x7b,0x71,0x66,0x49 == binsli.b $w25, $w12, 1 # encoding: [0x7b,0x71,0x66,0x49] +0x7b,0x60,0xb5,0x49 == binsli.h $w21, $w22, 0 # encoding: [0x7b,0x60,0xb5,0x49] +0x7b,0x40,0x25,0x89 == binsli.w $w22, $w4, 0 # encoding: [0x7b,0x40,0x25,0x89] +0x7b,0x06,0x11,0x89 == binsli.d $w6, $w2, 6 # encoding: [0x7b,0x06,0x11,0x89] +0x7b,0xf0,0x9b,0xc9 == binsri.b $w15, $w19, 0 # encoding: [0x7b,0xf0,0x9b,0xc9] +0x7b,0xe1,0xf2,0x09 == binsri.h $w8, $w30, 1 # encoding: [0x7b,0xe1,0xf2,0x09] +0x7b,0xc5,0x98,0x89 == binsri.w $w2, $w19, 5 # encoding: [0x7b,0xc5,0x98,0x89] +0x7b,0x81,0xa4,0x89 == binsri.d $w18, $w20, 1 # encoding: [0x7b,0x81,0xa4,0x89] +0x7a,0xf0,0x9e,0x09 == bnegi.b $w24, $w19, 0 # encoding: [0x7a,0xf0,0x9e,0x09] +0x7a,0xe3,0x5f,0x09 == bnegi.h $w28, $w11, 3 # encoding: [0x7a,0xe3,0x5f,0x09] +0x7a,0xc5,0xd8,0x49 == bnegi.w $w1, $w27, 5 # encoding: [0x7a,0xc5,0xd8,0x49] +0x7a,0x81,0xa9,0x09 == bnegi.d $w4, $w21, 1 # encoding: [0x7a,0x81,0xa9,0x09] +0x7a,0x70,0x44,0x89 == bseti.b $w18, $w8, 0 # encoding: [0x7a,0x70,0x44,0x89] +0x7a,0x62,0x76,0x09 == bseti.h $w24, $w14, 2 # encoding: [0x7a,0x62,0x76,0x09] +0x7a,0x44,0x92,0x49 == bseti.w $w9, $w18, 4 # encoding: [0x7a,0x44,0x92,0x49] +0x7a,0x01,0x79,0xc9 == bseti.d $w7, $w15, 1 # encoding: [0x7a,0x01,0x79,0xc9] +0x78,0x72,0xff,0xca == sat_s.b $w31, $w31, 2 # encoding: [0x78,0x72,0xff,0xca] +0x78,0x60,0x9c,0xca == sat_s.h $w19, $w19, 0 # encoding: [0x78,0x60,0x9c,0xca] +0x78,0x40,0xec,0xca == sat_s.w $w19, $w29, 0 # encoding: [0x78,0x40,0xec,0xca] +0x78,0x00,0xb2,0xca == sat_s.d $w11, $w22, 0 # encoding: [0x78,0x00,0xb2,0xca] +0x78,0xf3,0x68,0x4a == sat_u.b $w1, $w13, 3 # encoding: [0x78,0xf3,0x68,0x4a] +0x78,0xe4,0xc7,0x8a == sat_u.h $w30, $w24, 4 # encoding: [0x78,0xe4,0xc7,0x8a] +0x78,0xc0,0x6f,0xca == sat_u.w $w31, $w13, 0 # encoding: [0x78,0xc0,0x6f,0xca] +0x78,0x85,0x87,0x4a == sat_u.d $w29, $w16, 5 # encoding: [0x78,0x85,0x87,0x4a] +0x78,0x71,0x55,0xc9 == slli.b $w23, $w10, 1 # encoding: [0x78,0x71,0x55,0xc9] +0x78,0x61,0x92,0x49 == slli.h $w9, $w18, 1 # encoding: [0x78,0x61,0x92,0x49] +0x78,0x44,0xea,0xc9 == slli.w $w11, $w29, 4 # encoding: [0x78,0x44,0xea,0xc9] +0x78,0x01,0xa6,0x49 == slli.d $w25, $w20, 1 # encoding: [0x78,0x01,0xa6,0x49] +0x78,0xf1,0xee,0x09 == srai.b $w24, $w29, 1 # encoding: [0x78,0xf1,0xee,0x09] +0x78,0xe0,0x30,0x49 == srai.h $w1, $w6, 0 # encoding: [0x78,0xe0,0x30,0x49] +0x78,0xc1,0xd1,0xc9 == srai.w $w7, $w26, 1 # encoding: [0x78,0xc1,0xd1,0xc9] +0x78,0x83,0xcd,0x09 == srai.d $w20, $w25, 3 # encoding: [0x78,0x83,0xcd,0x09] +0x79,0x70,0xc9,0x4a == srari.b $w5, $w25, 0 # encoding: [0x79,0x70,0xc9,0x4a] +0x79,0x64,0x31,0xca == srari.h $w7, $w6, 4 # encoding: [0x79,0x64,0x31,0xca] +0x79,0x45,0x5c,0x4a == srari.w $w17, $w11, 5 # encoding: [0x79,0x45,0x5c,0x4a] +0x79,0x05,0xcd,0x4a == srari.d $w21, $w25, 5 # encoding: [0x79,0x05,0xcd,0x4a] +0x79,0x72,0x00,0x89 == srli.b $w2, $w0, 2 # encoding: [0x79,0x72,0x00,0x89] +0x79,0x62,0xff,0xc9 == srli.h $w31, $w31, 2 # encoding: [0x79,0x62,0xff,0xc9] +0x79,0x44,0x49,0x49 == srli.w $w5, $w9, 4 # encoding: [0x79,0x44,0x49,0x49] +0x79,0x05,0xd6,0xc9 == srli.d $w27, $w26, 5 # encoding: [0x79,0x05,0xd6,0xc9] +0x79,0xf0,0x1c,0x8a == srlri.b $w18, $w3, 0 # encoding: [0x79,0xf0,0x1c,0x8a] +0x79,0xe3,0x10,0x4a == srlri.h $w1, $w2, 3 # encoding: [0x79,0xe3,0x10,0x4a] +0x79,0xc2,0xb2,0xca == srlri.w $w11, $w22, 2 # encoding: [0x79,0xc2,0xb2,0xca] +0x79,0x86,0x56,0x0a == srlri.d $w24, $w10, 6 # encoding: [0x79,0x86,0x56,0x0a] diff --git a/suite/MC/Mips/test_cbranch.s.cs b/suite/MC/Mips/test_cbranch.s.cs index 92e7cdb044..ee57619c28 100644 --- a/suite/MC/Mips/test_cbranch.s.cs +++ b/suite/MC/Mips/test_cbranch.s.cs @@ -1,11 +1,41 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -// 0x47,0x80,0x00,0x01 = bnz.b $w0, 4 -// 0x47,0xa1,0x00,0x04 = bnz.h $w1, 16 -// 0x47,0xc2,0x00,0x20 = bnz.w $w2, 128 -// 0x47,0xe3,0xff,0xe0 = bnz.d $w3, -128 -// 0x45,0xe0,0x00,0x01 = bnz.v $w0, 4 -// 0x47,0x00,0x00,0x20 = bz.b $w0, 128 -// 0x47,0x21,0x00,0x40 = bz.h $w1, 256 -// 0x47,0x42,0x00,0x80 = bz.w $w2, 512 -// 0x47,0x63,0xff,0x00 = bz.d $w3, -1024 -// 0x45,0x60,0x00,0x01 = bz.v $w0, 4 + +0x47,0x80,0x00,0x01 == bnz.b $w0, 4 # encoding: [0x47,0x80,0x00,0x01] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0xa1,0x00,0x04 == bnz.h $w1, 16 # encoding: [0x47,0xa1,0x00,0x04] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0xc2,0x00,0x20 == bnz.w $w2, 128 # encoding: [0x47,0xc2,0x00,0x20] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0xe3,0xff,0xe0 == bnz.d $w3, -128 # encoding: [0x47,0xe3,0xff,0xe0] +0x47,0x80, == bnz.b $w0, SYMBOL0 # encoding: [0x47,0x80,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0xa1, == bnz.h $w1, SYMBOL1 # encoding: [0x47,0xa1,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0xc2, == bnz.w $w2, SYMBOL2 # encoding: [0x47,0xc2,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0xe3, == bnz.d $w3, SYMBOL3 # encoding: [0x47,0xe3,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x45,0xe0,0x00,0x01 == bnz.v $w0, 4 # encoding: [0x45,0xe0,0x00,0x01] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x45,0xe0, == bnz.v $w0, SYMBOL0 # encoding: [0x45,0xe0,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0x00,0x00,0x20 == bz.b $w0, 128 # encoding: [0x47,0x00,0x00,0x20] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0x21,0x00,0x40 == bz.h $w1, 256 # encoding: [0x47,0x21,0x00,0x40] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0x42,0x00,0x80 == bz.w $w2, 512 # encoding: [0x47,0x42,0x00,0x80] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0x63,0xff,0x00 == bz.d $w3, -1024 # encoding: [0x47,0x63,0xff,0x00] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0x00, == bz.b $w0, SYMBOL0 # encoding: [0x47,0x00,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0x21, == bz.h $w1, SYMBOL1 # encoding: [0x47,0x21,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0x42, == bz.w $w2, SYMBOL2 # encoding: [0x47,0x42,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x47,0x63, == bz.d $w3, SYMBOL3 # encoding: [0x47,0x63,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x45,0x60,0x00,0x01 == bz.v $w0, 4 # encoding: [0x45,0x60,0x00,0x01] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] +0x45,0x60, == bz.v $w0, SYMBOL0 # encoding: [0x45,0x60,A,A] +0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00] diff --git a/suite/MC/Mips/test_ctrlregs.s.cs b/suite/MC/Mips/test_ctrlregs.s.cs index fb587a75fc..555731a366 100644 --- a/suite/MC/Mips/test_ctrlregs.s.cs +++ b/suite/MC/Mips/test_ctrlregs.s.cs @@ -1,33 +1,34 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x78,0x7e,0x00,0x59 = cfcmsa $at, $0 -0x78,0x7e,0x00,0x59 = cfcmsa $at, $0 -0x78,0x7e,0x08,0x99 = cfcmsa $v0, $1 -0x78,0x7e,0x08,0x99 = cfcmsa $v0, $1 -0x78,0x7e,0x10,0xd9 = cfcmsa $v1, $2 -0x78,0x7e,0x10,0xd9 = cfcmsa $v1, $2 -0x78,0x7e,0x19,0x19 = cfcmsa $a0, $3 -0x78,0x7e,0x19,0x19 = cfcmsa $a0, $3 -0x78,0x7e,0x21,0x59 = cfcmsa $a1, $4 -0x78,0x7e,0x21,0x59 = cfcmsa $a1, $4 -0x78,0x7e,0x29,0x99 = cfcmsa $a2, $5 -0x78,0x7e,0x29,0x99 = cfcmsa $a2, $5 -0x78,0x7e,0x31,0xd9 = cfcmsa $a3, $6 -0x78,0x7e,0x31,0xd9 = cfcmsa $a3, $6 -0x78,0x7e,0x3a,0x19 = cfcmsa $t0, $7 -0x78,0x7e,0x3a,0x19 = cfcmsa $t0, $7 -0x78,0x3e,0x08,0x19 = ctcmsa $0, $at -0x78,0x3e,0x08,0x19 = ctcmsa $0, $at -0x78,0x3e,0x10,0x59 = ctcmsa $1, $v0 -0x78,0x3e,0x10,0x59 = ctcmsa $1, $v0 -0x78,0x3e,0x18,0x99 = ctcmsa $2, $v1 -0x78,0x3e,0x18,0x99 = ctcmsa $2, $v1 -0x78,0x3e,0x20,0xd9 = ctcmsa $3, $a0 -0x78,0x3e,0x20,0xd9 = ctcmsa $3, $a0 -0x78,0x3e,0x29,0x19 = ctcmsa $4, $a1 -0x78,0x3e,0x29,0x19 = ctcmsa $4, $a1 -0x78,0x3e,0x31,0x59 = ctcmsa $5, $a2 -0x78,0x3e,0x31,0x59 = ctcmsa $5, $a2 -0x78,0x3e,0x39,0x99 = ctcmsa $6, $a3 -0x78,0x3e,0x39,0x99 = ctcmsa $6, $a3 -0x78,0x3e,0x41,0xd9 = ctcmsa $7, $t0 -0x78,0x3e,0x41,0xd9 = ctcmsa $7, $t0 + +0x78,0x7e,0x00,0x59 == cfcmsa $1, $0 # encoding: [0x78,0x7e,0x00,0x59] +0x78,0x7e,0x00,0x59 == cfcmsa $1, $0 # encoding: [0x78,0x7e,0x00,0x59] +0x78,0x7e,0x08,0x99 == cfcmsa $2, $1 # encoding: [0x78,0x7e,0x08,0x99] +0x78,0x7e,0x08,0x99 == cfcmsa $2, $1 # encoding: [0x78,0x7e,0x08,0x99] +0x78,0x7e,0x10,0xd9 == cfcmsa $3, $2 # encoding: [0x78,0x7e,0x10,0xd9] +0x78,0x7e,0x10,0xd9 == cfcmsa $3, $2 # encoding: [0x78,0x7e,0x10,0xd9] +0x78,0x7e,0x19,0x19 == cfcmsa $4, $3 # encoding: [0x78,0x7e,0x19,0x19] +0x78,0x7e,0x19,0x19 == cfcmsa $4, $3 # encoding: [0x78,0x7e,0x19,0x19] +0x78,0x7e,0x21,0x59 == cfcmsa $5, $4 # encoding: [0x78,0x7e,0x21,0x59] +0x78,0x7e,0x21,0x59 == cfcmsa $5, $4 # encoding: [0x78,0x7e,0x21,0x59] +0x78,0x7e,0x29,0x99 == cfcmsa $6, $5 # encoding: [0x78,0x7e,0x29,0x99] +0x78,0x7e,0x29,0x99 == cfcmsa $6, $5 # encoding: [0x78,0x7e,0x29,0x99] +0x78,0x7e,0x31,0xd9 == cfcmsa $7, $6 # encoding: [0x78,0x7e,0x31,0xd9] +0x78,0x7e,0x31,0xd9 == cfcmsa $7, $6 # encoding: [0x78,0x7e,0x31,0xd9] +0x78,0x7e,0x3a,0x19 == cfcmsa $8, $7 # encoding: [0x78,0x7e,0x3a,0x19] +0x78,0x7e,0x3a,0x19 == cfcmsa $8, $7 # encoding: [0x78,0x7e,0x3a,0x19] +0x78,0x3e,0x08,0x19 == ctcmsa $0, $1 # encoding: [0x78,0x3e,0x08,0x19] +0x78,0x3e,0x08,0x19 == ctcmsa $0, $1 # encoding: [0x78,0x3e,0x08,0x19] +0x78,0x3e,0x10,0x59 == ctcmsa $1, $2 # encoding: [0x78,0x3e,0x10,0x59] +0x78,0x3e,0x10,0x59 == ctcmsa $1, $2 # encoding: [0x78,0x3e,0x10,0x59] +0x78,0x3e,0x18,0x99 == ctcmsa $2, $3 # encoding: [0x78,0x3e,0x18,0x99] +0x78,0x3e,0x18,0x99 == ctcmsa $2, $3 # encoding: [0x78,0x3e,0x18,0x99] +0x78,0x3e,0x20,0xd9 == ctcmsa $3, $4 # encoding: [0x78,0x3e,0x20,0xd9] +0x78,0x3e,0x20,0xd9 == ctcmsa $3, $4 # encoding: [0x78,0x3e,0x20,0xd9] +0x78,0x3e,0x29,0x19 == ctcmsa $4, $5 # encoding: [0x78,0x3e,0x29,0x19] +0x78,0x3e,0x29,0x19 == ctcmsa $4, $5 # encoding: [0x78,0x3e,0x29,0x19] +0x78,0x3e,0x31,0x59 == ctcmsa $5, $6 # encoding: [0x78,0x3e,0x31,0x59] +0x78,0x3e,0x31,0x59 == ctcmsa $5, $6 # encoding: [0x78,0x3e,0x31,0x59] +0x78,0x3e,0x39,0x99 == ctcmsa $6, $7 # encoding: [0x78,0x3e,0x39,0x99] +0x78,0x3e,0x39,0x99 == ctcmsa $6, $7 # encoding: [0x78,0x3e,0x39,0x99] +0x78,0x3e,0x41,0xd9 == ctcmsa $7, $8 # encoding: [0x78,0x3e,0x41,0xd9] +0x78,0x3e,0x41,0xd9 == ctcmsa $7, $8 # encoding: [0x78,0x3e,0x41,0xd9] diff --git a/suite/MC/Mips/test_elm.s.cs b/suite/MC/Mips/test_elm.s.cs index c2ba952570..6297cd700a 100644 --- a/suite/MC/Mips/test_elm.s.cs +++ b/suite/MC/Mips/test_elm.s.cs @@ -1,16 +1,16 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x78,0x82,0x43,0x59 = copy_s.b $t5, $w8[2] -0x78,0xa0,0xc8,0x59 = copy_s.h $at, $w25[0] -0x78,0xb1,0x2d,0x99 = copy_s.w $s6, $w5[1] -0x78,0xc4,0xa5,0x99 = copy_u.b $s6, $w20[4] -0x78,0xe0,0x25,0x19 = copy_u.h $s4, $w4[0] -0x78,0xf2,0x6f,0x99 = copy_u.w $fp, $w13[2] -0x78,0x04,0xe8,0x19 = sldi.b $w0, $w29[4] -0x78,0x20,0x8a,0x19 = sldi.h $w8, $w17[0] -0x78,0x32,0xdd,0x19 = sldi.w $w20, $w27[2] -0x78,0x38,0x61,0x19 = sldi.d $w4, $w12[0] -0x78,0x42,0x1e,0x59 = splati.b $w25, $w3[2] -0x78,0x61,0xe6,0x19 = splati.h $w24, $w28[1] -0x78,0x70,0x93,0x59 = splati.w $w13, $w18[0] -0x78,0x78,0x0f,0x19 = splati.d $w28, $w1[0] -0x78,0xbe,0xc5,0xd9 = move.v $w23, $w24 + +0x78,0x82,0x43,0x59 == copy_s.b $13, $w8[2] # encoding: [0x78,0x82,0x43,0x59] +0x78,0xa0,0xc8,0x59 == copy_s.h $1, $w25[0] # encoding: [0x78,0xa0,0xc8,0x59] +0x78,0xb1,0x2d,0x99 == copy_s.w $22, $w5[1] # encoding: [0x78,0xb1,0x2d,0x99] +0x78,0xc4,0xa5,0x99 == copy_u.b $22, $w20[4] # encoding: [0x78,0xc4,0xa5,0x99] +0x78,0xe0,0x25,0x19 == copy_u.h $20, $w4[0] # encoding: [0x78,0xe0,0x25,0x19] +0x78,0x04,0xe8,0x19 == sldi.b $w0, $w29[4] # encoding: [0x78,0x04,0xe8,0x19] +0x78,0x20,0x8a,0x19 == sldi.h $w8, $w17[0] # encoding: [0x78,0x20,0x8a,0x19] +0x78,0x32,0xdd,0x19 == sldi.w $w20, $w27[2] # encoding: [0x78,0x32,0xdd,0x19] +0x78,0x38,0x61,0x19 == sldi.d $w4, $w12[0] # encoding: [0x78,0x38,0x61,0x19] +0x78,0x42,0x1e,0x59 == splati.b $w25, $w3[2] # encoding: [0x78,0x42,0x1e,0x59] +0x78,0x61,0xe6,0x19 == splati.h $w24, $w28[1] # encoding: [0x78,0x61,0xe6,0x19] +0x78,0x70,0x93,0x59 == splati.w $w13, $w18[0] # encoding: [0x78,0x70,0x93,0x59] +0x78,0x78,0x0f,0x19 == splati.d $w28, $w1[0] # encoding: [0x78,0x78,0x0f,0x19] +0x78,0xbe,0xc5,0xd9 == move.v $w23, $w24 # encoding: [0x78,0xbe,0xc5,0xd9] diff --git a/suite/MC/Mips/test_elm_insert.s.cs b/suite/MC/Mips/test_elm_insert.s.cs index c9edc8e5e7..c5bb89e574 100644 --- a/suite/MC/Mips/test_elm_insert.s.cs +++ b/suite/MC/Mips/test_elm_insert.s.cs @@ -1,4 +1,5 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x79,0x03,0xed,0xd9 = insert.b $w23[3], $sp -0x79,0x22,0x2d,0x19 = insert.h $w20[2], $a1 -0x79,0x32,0x7a,0x19 = insert.w $w8[2], $t7 + +0x79,0x03,0xed,0xd9 == insert.b $w23[3], $sp # encoding: [0x79,0x03,0xed,0xd9] +0x79,0x22,0x2d,0x19 == insert.h $w20[2], $5 # encoding: [0x79,0x22,0x2d,0x19] +0x79,0x32,0x7a,0x19 == insert.w $w8[2], $15 # encoding: [0x79,0x32,0x7a,0x19] diff --git a/suite/MC/Mips/test_elm_insve.s.cs b/suite/MC/Mips/test_elm_insve.s.cs index 7657969b72..c4e0fff333 100644 --- a/suite/MC/Mips/test_elm_insve.s.cs +++ b/suite/MC/Mips/test_elm_insve.s.cs @@ -1,5 +1,6 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x79,0x43,0x4e,0x59 = insve.b $w25[3], $w9[0] -0x79,0x62,0x16,0x19 = insve.h $w24[2], $w2[0] -0x79,0x72,0x68,0x19 = insve.w $w0[2], $w13[0] -0x79,0x78,0x90,0xd9 = insve.d $w3[0], $w18[0] + +0x79,0x43,0x4e,0x59 == insve.b $w25[3], $w9[0] # encoding: [0x79,0x43,0x4e,0x59] +0x79,0x62,0x16,0x19 == insve.h $w24[2], $w2[0] # encoding: [0x79,0x62,0x16,0x19] +0x79,0x72,0x68,0x19 == insve.w $w0[2], $w13[0] # encoding: [0x79,0x72,0x68,0x19] +0x79,0x78,0x90,0xd9 == insve.d $w3[0], $w18[0] # encoding: [0x79,0x78,0x90,0xd9] diff --git a/suite/MC/Mips/test_i10.s.cs b/suite/MC/Mips/test_i10.s.cs index ba799f9d76..58f015d912 100644 --- a/suite/MC/Mips/test_i10.s.cs +++ b/suite/MC/Mips/test_i10.s.cs @@ -1,5 +1,6 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x7b,0x06,0x32,0x07 = ldi.b $w8, 198 -0x7b,0x29,0xcd,0x07 = ldi.h $w20, 313 -0x7b,0x4f,0x66,0x07 = ldi.w $w24, 492 -// 0x7b,0x7a,0x66,0xc7 = ldi.d $w27, -180 + +0x7b,0x06,0x32,0x07 == ldi.b $w8, 198 # encoding: [0x7b,0x06,0x32,0x07] +0x7b,0x29,0xcd,0x07 == ldi.h $w20, 313 # encoding: [0x7b,0x29,0xcd,0x07] +0x7b,0x4f,0x66,0x07 == ldi.w $w24, 492 # encoding: [0x7b,0x4f,0x66,0x07] +0x7b,0x7a,0x66,0xc7 == ldi.d $w27, -180 # encoding: [0x7b,0x7a,0x66,0xc7] diff --git a/suite/MC/Mips/test_i5.s.cs b/suite/MC/Mips/test_i5.s.cs index 57192231b3..ba8825a139 100644 --- a/suite/MC/Mips/test_i5.s.cs +++ b/suite/MC/Mips/test_i5.s.cs @@ -1,45 +1,46 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x78,0x1e,0xf8,0xc6 = addvi.b $w3, $w31, 30 -0x78,0x3a,0x6e,0x06 = addvi.h $w24, $w13, 26 -0x78,0x5a,0xa6,0x86 = addvi.w $w26, $w20, 26 -0x78,0x75,0x0c,0x06 = addvi.d $w16, $w1, 21 -// 0x78,0x18,0xae,0x07 = ceqi.b $w24, $w21, -8 -0x78,0x22,0x7f,0xc7 = ceqi.h $w31, $w15, 2 -// 0x78,0x5f,0x0b,0x07 = ceqi.w $w12, $w1, -1 -0x78,0x67,0xb6,0x07 = ceqi.d $w24, $w22, 7 -0x7a,0x01,0x83,0x07 = clei_s.b $w12, $w16, 1 -// 0x7a,0x37,0x50,0x87 = clei_s.h $w2, $w10, -9 -// 0x7a,0x56,0x59,0x07 = clei_s.w $w4, $w11, -10 -// 0x7a,0x76,0xe8,0x07 = clei_s.d $w0, $w29, -10 -0x7a,0x83,0x8d,0x47 = clei_u.b $w21, $w17, 3 -0x7a,0xb1,0x3f,0x47 = clei_u.h $w29, $w7, 17 -0x7a,0xc2,0x08,0x47 = clei_u.w $w1, $w1, 2 -0x7a,0xfd,0xde,0xc7 = clei_u.d $w27, $w27, 29 -// 0x79,0x19,0x6c,0xc7 = clti_s.b $w19, $w13, -7 -// 0x79,0x34,0x53,0xc7 = clti_s.h $w15, $w10, -12 -0x79,0x4b,0x63,0x07 = clti_s.w $w12, $w12, 11 -// 0x79,0x71,0xa7,0x47 = clti_s.d $w29, $w20, -15 -0x79,0x9d,0x4b,0x87 = clti_u.b $w14, $w9, 29 -0x79,0xb9,0xce,0x07 = clti_u.h $w24, $w25, 25 -0x79,0xd6,0x08,0x47 = clti_u.w $w1, $w1, 22 -0x79,0xe1,0xcd,0x47 = clti_u.d $w21, $w25, 1 -0x79,0x01,0xad,0x86 = maxi_s.b $w22, $w21, 1 -// 0x79,0x38,0x2f,0x46 = maxi_s.h $w29, $w5, -8 -// 0x79,0x54,0x50,0x46 = maxi_s.w $w1, $w10, -12 -// 0x79,0x70,0xeb,0x46 = maxi_s.d $w13, $w29, -16 -0x79,0x8c,0x05,0x06 = maxi_u.b $w20, $w0, 12 -0x79,0xa3,0x70,0x46 = maxi_u.h $w1, $w14, 3 -0x79,0xcb,0xb6,0xc6 = maxi_u.w $w27, $w22, 11 -0x79,0xe4,0x36,0x86 = maxi_u.d $w26, $w6, 4 -0x7a,0x01,0x09,0x06 = mini_s.b $w4, $w1, 1 -// 0x7a,0x37,0xde,0xc6 = mini_s.h $w27, $w27, -9 -0x7a,0x49,0x5f,0x06 = mini_s.w $w28, $w11, 9 -0x7a,0x6a,0x52,0xc6 = mini_s.d $w11, $w10, 10 -0x7a,0x9b,0xbc,0x86 = mini_u.b $w18, $w23, 27 -0x7a,0xb2,0xd1,0xc6 = mini_u.h $w7, $w26, 18 -0x7a,0xda,0x62,0xc6 = mini_u.w $w11, $w12, 26 -0x7a,0xe2,0x7a,0xc6 = mini_u.d $w11, $w15, 2 -0x78,0x93,0xa6,0x06 = subvi.b $w24, $w20, 19 -0x78,0xa4,0x9a,0xc6 = subvi.h $w11, $w19, 4 -0x78,0xcb,0x53,0x06 = subvi.w $w12, $w10, 11 -0x78,0xe7,0x84,0xc6 = subvi.d $w19, $w16, 7 + +0x78,0x1e,0xf8,0xc6 == addvi.b $w3, $w31, 30 # encoding: [0x78,0x1e,0xf8,0xc6] +0x78,0x3a,0x6e,0x06 == addvi.h $w24, $w13, 26 # encoding: [0x78,0x3a,0x6e,0x06] +0x78,0x5a,0xa6,0x86 == addvi.w $w26, $w20, 26 # encoding: [0x78,0x5a,0xa6,0x86] +0x78,0x75,0x0c,0x06 == addvi.d $w16, $w1, 21 # encoding: [0x78,0x75,0x0c,0x06] +0x78,0x18,0xae,0x07 == ceqi.b $w24, $w21, -8 # encoding: [0x78,0x18,0xae,0x07] +0x78,0x22,0x7f,0xc7 == ceqi.h $w31, $w15, 2 # encoding: [0x78,0x22,0x7f,0xc7] +0x78,0x5f,0x0b,0x07 == ceqi.w $w12, $w1, -1 # encoding: [0x78,0x5f,0x0b,0x07] +0x78,0x67,0xb6,0x07 == ceqi.d $w24, $w22, 7 # encoding: [0x78,0x67,0xb6,0x07] +0x7a,0x01,0x83,0x07 == clei_s.b $w12, $w16, 1 # encoding: [0x7a,0x01,0x83,0x07] +0x7a,0x37,0x50,0x87 == clei_s.h $w2, $w10, -9 # encoding: [0x7a,0x37,0x50,0x87] +0x7a,0x56,0x59,0x07 == clei_s.w $w4, $w11, -10 # encoding: [0x7a,0x56,0x59,0x07] +0x7a,0x76,0xe8,0x07 == clei_s.d $w0, $w29, -10 # encoding: [0x7a,0x76,0xe8,0x07] +0x7a,0x83,0x8d,0x47 == clei_u.b $w21, $w17, 3 # encoding: [0x7a,0x83,0x8d,0x47] +0x7a,0xb1,0x3f,0x47 == clei_u.h $w29, $w7, 17 # encoding: [0x7a,0xb1,0x3f,0x47] +0x7a,0xc2,0x08,0x47 == clei_u.w $w1, $w1, 2 # encoding: [0x7a,0xc2,0x08,0x47] +0x7a,0xfd,0xde,0xc7 == clei_u.d $w27, $w27, 29 # encoding: [0x7a,0xfd,0xde,0xc7] +0x79,0x19,0x6c,0xc7 == clti_s.b $w19, $w13, -7 # encoding: [0x79,0x19,0x6c,0xc7] +0x79,0x34,0x53,0xc7 == clti_s.h $w15, $w10, -12 # encoding: [0x79,0x34,0x53,0xc7] +0x79,0x4b,0x63,0x07 == clti_s.w $w12, $w12, 11 # encoding: [0x79,0x4b,0x63,0x07] +0x79,0x71,0xa7,0x47 == clti_s.d $w29, $w20, -15 # encoding: [0x79,0x71,0xa7,0x47] +0x79,0x9d,0x4b,0x87 == clti_u.b $w14, $w9, 29 # encoding: [0x79,0x9d,0x4b,0x87] +0x79,0xb9,0xce,0x07 == clti_u.h $w24, $w25, 25 # encoding: [0x79,0xb9,0xce,0x07] +0x79,0xd6,0x08,0x47 == clti_u.w $w1, $w1, 22 # encoding: [0x79,0xd6,0x08,0x47] +0x79,0xe1,0xcd,0x47 == clti_u.d $w21, $w25, 1 # encoding: [0x79,0xe1,0xcd,0x47] +0x79,0x01,0xad,0x86 == maxi_s.b $w22, $w21, 1 # encoding: [0x79,0x01,0xad,0x86] +0x79,0x38,0x2f,0x46 == maxi_s.h $w29, $w5, -8 # encoding: [0x79,0x38,0x2f,0x46] +0x79,0x54,0x50,0x46 == maxi_s.w $w1, $w10, -12 # encoding: [0x79,0x54,0x50,0x46] +0x79,0x70,0xeb,0x46 == maxi_s.d $w13, $w29, -16 # encoding: [0x79,0x70,0xeb,0x46] +0x79,0x8c,0x05,0x06 == maxi_u.b $w20, $w0, 12 # encoding: [0x79,0x8c,0x05,0x06] +0x79,0xa3,0x70,0x46 == maxi_u.h $w1, $w14, 3 # encoding: [0x79,0xa3,0x70,0x46] +0x79,0xcb,0xb6,0xc6 == maxi_u.w $w27, $w22, 11 # encoding: [0x79,0xcb,0xb6,0xc6] +0x79,0xe4,0x36,0x86 == maxi_u.d $w26, $w6, 4 # encoding: [0x79,0xe4,0x36,0x86] +0x7a,0x01,0x09,0x06 == mini_s.b $w4, $w1, 1 # encoding: [0x7a,0x01,0x09,0x06] +0x7a,0x37,0xde,0xc6 == mini_s.h $w27, $w27, -9 # encoding: [0x7a,0x37,0xde,0xc6] +0x7a,0x49,0x5f,0x06 == mini_s.w $w28, $w11, 9 # encoding: [0x7a,0x49,0x5f,0x06] +0x7a,0x6a,0x52,0xc6 == mini_s.d $w11, $w10, 10 # encoding: [0x7a,0x6a,0x52,0xc6] +0x7a,0x9b,0xbc,0x86 == mini_u.b $w18, $w23, 27 # encoding: [0x7a,0x9b,0xbc,0x86] +0x7a,0xb2,0xd1,0xc6 == mini_u.h $w7, $w26, 18 # encoding: [0x7a,0xb2,0xd1,0xc6] +0x7a,0xda,0x62,0xc6 == mini_u.w $w11, $w12, 26 # encoding: [0x7a,0xda,0x62,0xc6] +0x7a,0xe2,0x7a,0xc6 == mini_u.d $w11, $w15, 2 # encoding: [0x7a,0xe2,0x7a,0xc6] +0x78,0x93,0xa6,0x06 == subvi.b $w24, $w20, 19 # encoding: [0x78,0x93,0xa6,0x06] +0x78,0xa4,0x9a,0xc6 == subvi.h $w11, $w19, 4 # encoding: [0x78,0xa4,0x9a,0xc6] +0x78,0xcb,0x53,0x06 == subvi.w $w12, $w10, 11 # encoding: [0x78,0xcb,0x53,0x06] +0x78,0xe7,0x84,0xc6 == subvi.d $w19, $w16, 7 # encoding: [0x78,0xe7,0x84,0xc6] diff --git a/suite/MC/Mips/test_i8.s.cs b/suite/MC/Mips/test_i8.s.cs index 0b08f63aa8..d1dcb40bbf 100644 --- a/suite/MC/Mips/test_i8.s.cs +++ b/suite/MC/Mips/test_i8.s.cs @@ -1,11 +1,12 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x78,0x30,0xe8,0x80 = andi.b $w2, $w29, 48 -0x78,0x7e,0xb1,0x81 = bmnzi.b $w6, $w22, 126 -0x79,0x58,0x0e,0xc1 = bmzi.b $w27, $w1, 88 -0x7a,0xbd,0x1f,0x41 = bseli.b $w29, $w3, 189 -0x7a,0x38,0x88,0x40 = nori.b $w1, $w17, 56 -0x79,0x87,0xa6,0x80 = ori.b $w26, $w20, 135 -0x78,0x69,0xf4,0xc2 = shf.b $w19, $w30, 105 -0x79,0x4c,0x44,0x42 = shf.h $w17, $w8, 76 -0x7a,0x5d,0x1b,0x82 = shf.w $w14, $w3, 93 -0x7b,0x14,0x54,0x00 = xori.b $w16, $w10, 20 + +0x78,0x30,0xe8,0x80 == andi.b $w2, $w29, 48 # encoding: [0x78,0x30,0xe8,0x80] +0x78,0x7e,0xb1,0x81 == bmnzi.b $w6, $w22, 126 # encoding: [0x78,0x7e,0xb1,0x81] +0x79,0x58,0x0e,0xc1 == bmzi.b $w27, $w1, 88 # encoding: [0x79,0x58,0x0e,0xc1] +0x7a,0xbd,0x1f,0x41 == bseli.b $w29, $w3, 189 # encoding: [0x7a,0xbd,0x1f,0x41] +0x7a,0x38,0x88,0x40 == nori.b $w1, $w17, 56 # encoding: [0x7a,0x38,0x88,0x40] +0x79,0x87,0xa6,0x80 == ori.b $w26, $w20, 135 # encoding: [0x79,0x87,0xa6,0x80] +0x78,0x69,0xf4,0xc2 == shf.b $w19, $w30, 105 # encoding: [0x78,0x69,0xf4,0xc2] +0x79,0x4c,0x44,0x42 == shf.h $w17, $w8, 76 # encoding: [0x79,0x4c,0x44,0x42] +0x7a,0x5d,0x1b,0x82 == shf.w $w14, $w3, 93 # encoding: [0x7a,0x5d,0x1b,0x82] +0x7b,0x14,0x54,0x00 == xori.b $w16, $w10, 20 # encoding: [0x7b,0x14,0x54,0x00] diff --git a/suite/MC/Mips/test_lsa.s.cs b/suite/MC/Mips/test_lsa.s.cs index 098775c049..c59d25ad23 100644 --- a/suite/MC/Mips/test_lsa.s.cs +++ b/suite/MC/Mips/test_lsa.s.cs @@ -1,5 +1,6 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x01,0x2a,0x40,0x05 = lsa $t0, $t1, $t2, 1 -0x01,0x2a,0x40,0x45 = lsa $t0, $t1, $t2, 2 -0x01,0x2a,0x40,0x85 = lsa $t0, $t1, $t2, 3 -0x01,0x2a,0x40,0xc5 = lsa $t0, $t1, $t2, 4 + +0x01,0x2a,0x40,0x05 == lsa $8, $9, $10, 1 # encoding: [0x01,0x2a,0x40,0x05] +0x01,0x2a,0x40,0x45 == lsa $8, $9, $10, 2 # encoding: [0x01,0x2a,0x40,0x45] +0x01,0x2a,0x40,0x85 == lsa $8, $9, $10, 3 # encoding: [0x01,0x2a,0x40,0x85] +0x01,0x2a,0x40,0xc5 == lsa $8, $9, $10, 4 # encoding: [0x01,0x2a,0x40,0xc5] diff --git a/suite/MC/Mips/test_mi10.s.cs b/suite/MC/Mips/test_mi10.s.cs index 54d62c469f..0492cad384 100644 --- a/suite/MC/Mips/test_mi10.s.cs +++ b/suite/MC/Mips/test_mi10.s.cs @@ -1,24 +1,25 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x7a,0x00,0x08,0x20 = ld.b $w0, -512($at) -0x78,0x00,0x10,0x60 = ld.b $w1, ($v0) -0x79,0xff,0x18,0xa0 = ld.b $w2, 511($v1) -0x7a,0x00,0x20,0xe1 = ld.h $w3, -1024($a0) -0x7b,0x00,0x29,0x21 = ld.h $w4, -512($a1) -0x78,0x00,0x31,0x61 = ld.h $w5, ($a2) -0x79,0x00,0x39,0xa1 = ld.h $w6, 512($a3) -0x79,0xff,0x41,0xe1 = ld.h $w7, 1022($t0) -0x7a,0x00,0x4a,0x22 = ld.w $w8, -2048($t1) -0x7b,0x00,0x52,0x62 = ld.w $w9, -1024($t2) -0x7b,0x80,0x5a,0xa2 = ld.w $w10, -512($t3) -0x78,0x80,0x62,0xe2 = ld.w $w11, 512($t4) -0x79,0x00,0x6b,0x22 = ld.w $w12, 1024($t5) -0x79,0xff,0x73,0x62 = ld.w $w13, 2044($t6) -0x7a,0x00,0x7b,0xa3 = ld.d $w14, -4096($t7) -0x7b,0x00,0x83,0xe3 = ld.d $w15, -2048($s0) -0x7b,0x80,0x8c,0x23 = ld.d $w16, -1024($s1) -0x7b,0xc0,0x94,0x63 = ld.d $w17, -512($s2) -0x78,0x00,0x9c,0xa3 = ld.d $w18, ($s3) -0x78,0x40,0xa4,0xe3 = ld.d $w19, 512($s4) -0x78,0x80,0xad,0x23 = ld.d $w20, 1024($s5) -0x79,0x00,0xb5,0x63 = ld.d $w21, 2048($s6) -0x79,0xff,0xbd,0xa3 = ld.d $w22, 4088($s7) + +0x7a,0x00,0x08,0x20 == ld.b $w0, -512($1) # encoding: [0x7a,0x00,0x08,0x20] +0x78,0x00,0x10,0x60 == ld.b $w1, 0($2) # encoding: [0x78,0x00,0x10,0x60] +0x79,0xff,0x18,0xa0 == ld.b $w2, 511($3) # encoding: [0x79,0xff,0x18,0xa0] +0x7a,0x00,0x20,0xe1 == ld.h $w3, -1024($4) # encoding: [0x7a,0x00,0x20,0xe1] +0x7b,0x00,0x29,0x21 == ld.h $w4, -512($5) # encoding: [0x7b,0x00,0x29,0x21] +0x78,0x00,0x31,0x61 == ld.h $w5, 0($6) # encoding: [0x78,0x00,0x31,0x61] +0x79,0x00,0x39,0xa1 == ld.h $w6, 512($7) # encoding: [0x79,0x00,0x39,0xa1] +0x79,0xff,0x41,0xe1 == ld.h $w7, 1022($8) # encoding: [0x79,0xff,0x41,0xe1] +0x7a,0x00,0x4a,0x22 == ld.w $w8, -2048($9) # encoding: [0x7a,0x00,0x4a,0x22] +0x7b,0x00,0x52,0x62 == ld.w $w9, -1024($10) # encoding: [0x7b,0x00,0x52,0x62] +0x7b,0x80,0x5a,0xa2 == ld.w $w10, -512($11) # encoding: [0x7b,0x80,0x5a,0xa2] +0x78,0x80,0x62,0xe2 == ld.w $w11, 512($12) # encoding: [0x78,0x80,0x62,0xe2] +0x79,0x00,0x6b,0x22 == ld.w $w12, 1024($13) # encoding: [0x79,0x00,0x6b,0x22] +0x79,0xff,0x73,0x62 == ld.w $w13, 2044($14) # encoding: [0x79,0xff,0x73,0x62] +0x7a,0x00,0x7b,0xa3 == ld.d $w14, -4096($15) # encoding: [0x7a,0x00,0x7b,0xa3] +0x7b,0x00,0x83,0xe3 == ld.d $w15, -2048($16) # encoding: [0x7b,0x00,0x83,0xe3] +0x7b,0x80,0x8c,0x23 == ld.d $w16, -1024($17) # encoding: [0x7b,0x80,0x8c,0x23] +0x7b,0xc0,0x94,0x63 == ld.d $w17, -512($18) # encoding: [0x7b,0xc0,0x94,0x63] +0x78,0x00,0x9c,0xa3 == ld.d $w18, 0($19) # encoding: [0x78,0x00,0x9c,0xa3] +0x78,0x40,0xa4,0xe3 == ld.d $w19, 512($20) # encoding: [0x78,0x40,0xa4,0xe3] +0x78,0x80,0xad,0x23 == ld.d $w20, 1024($21) # encoding: [0x78,0x80,0xad,0x23] +0x79,0x00,0xb5,0x63 == ld.d $w21, 2048($22) # encoding: [0x79,0x00,0xb5,0x63] +0x79,0xff,0xbd,0xa3 == ld.d $w22, 4088($23) # encoding: [0x79,0xff,0xbd,0xa3] diff --git a/suite/MC/Mips/test_vec.s.cs b/suite/MC/Mips/test_vec.s.cs index 930386823a..b2def58702 100644 --- a/suite/MC/Mips/test_vec.s.cs +++ b/suite/MC/Mips/test_vec.s.cs @@ -1,8 +1,9 @@ # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None -0x78,0x1b,0xa6,0x5e = and.v $w25, $w20, $w27 -0x78,0x87,0x34,0x5e = bmnz.v $w17, $w6, $w7 -0x78,0xa9,0x88,0xde = bmz.v $w3, $w17, $w9 -0x78,0xce,0x02,0x1e = bsel.v $w8, $w0, $w14 -0x78,0x40,0xf9,0xde = nor.v $w7, $w31, $w0 -0x78,0x3e,0xd6,0x1e = or.v $w24, $w26, $w30 -0x78,0x6f,0xd9,0xde = xor.v $w7, $w27, $w15 + +0x78,0x1b,0xa6,0x5e == and.v $w25, $w20, $w27 # encoding: [0x78,0x1b,0xa6,0x5e] +0x78,0x87,0x34,0x5e == bmnz.v $w17, $w6, $w7 # encoding: [0x78,0x87,0x34,0x5e] +0x78,0xa9,0x88,0xde == bmz.v $w3, $w17, $w9 # encoding: [0x78,0xa9,0x88,0xde] +0x78,0xce,0x02,0x1e == bsel.v $w8, $w0, $w14 # encoding: [0x78,0xce,0x02,0x1e] +0x78,0x40,0xf9,0xde == nor.v $w7, $w31, $w0 # encoding: [0x78,0x40,0xf9,0xde] +0x78,0x3e,0xd6,0x1e == or.v $w24, $w26, $w30 # encoding: [0x78,0x3e,0xd6,0x1e] +0x78,0x6f,0xd9,0xde == xor.v $w7, $w27, $w15 # encoding: [0x78,0x6f,0xd9,0xde] diff --git a/suite/auto-sync/pyproject.toml b/suite/auto-sync/pyproject.toml index 907d88ada2..cf560c27a4 100644 --- a/suite/auto-sync/pyproject.toml +++ b/suite/auto-sync/pyproject.toml @@ -8,7 +8,7 @@ version = "0.1.0" dependencies = [ "termcolor >= 2.3.0", "tree_sitter == 0.22.3", - "tree-sitter-cpp >=0.22.0", + "tree-sitter-cpp == 0.22.3", "black >= 24.3.0", "usort >= 1.0.8", "setuptools >= 69.2.0", diff --git a/suite/auto-sync/src/autosync/ASUpdater.py b/suite/auto-sync/src/autosync/ASUpdater.py index a69803001b..15ec433871 100755 --- a/suite/auto-sync/src/autosync/ASUpdater.py +++ b/suite/auto-sync/src/autosync/ASUpdater.py @@ -216,7 +216,7 @@ def parse_args() -> argparse.Namespace: "-a", dest="arch", help="Name of target architecture.", - choices=["ARM", "PPC", "AArch64", "Alpha", "LoongArch"], + choices=["ARM", "PPC", "AArch64", "Alpha", "LoongArch", "Mips"], required=True, ) parser.add_argument( diff --git a/suite/auto-sync/src/autosync/MCUpdater.py b/suite/auto-sync/src/autosync/MCUpdater.py index afc64873c3..c8ee9f4e3b 100755 --- a/suite/auto-sync/src/autosync/MCUpdater.py +++ b/suite/auto-sync/src/autosync/MCUpdater.py @@ -143,6 +143,8 @@ def init_tests(self, unified_test_cases: bool): text_section = 0 # Counts the .text sections asm_pat = f"(?P.+)" enc_pat = r"(\[?(?P(?P((0x[a-fA-F0-9]{1,2}[, ]{0,2}))+)[^, ]?)\]?)" + + dups = [] for line in mc_output.stdout.splitlines(): line = line.decode("utf8") if ".text" in line: @@ -166,6 +168,10 @@ def init_tests(self, unified_test_cases: bool): if not self.valid_byte_seq(enc_bytes): continue + if (enc_bytes + asm_text) in dups: + continue + + dups.append(enc_bytes + asm_text) if text_section in self.tests: if unified_test_cases: self.tests[text_section][0].extend(enc_bytes, asm_text) @@ -262,6 +268,20 @@ def __init__( if self.arch in self.conf["mandatory_options"] else list() ) + self.remove_options: str = ( + self.conf["remove_options"][self.arch] + if self.arch in self.conf["remove_options"] + else list() + ) + self.remove_options = [x.lower() for x in self.remove_options] + self.replace_option_map: str = ( + self.conf["replace_option_map"][self.arch] + if self.arch in self.conf["replace_option_map"] + else {} + ) + self.replace_option_map = { + k.lower(): v for k, v in self.replace_option_map.items() + } self.multi_mode = multi_mode def check_prerequisites(self, paths): @@ -331,17 +351,30 @@ def write_to_build_dir(self): f"See also: https://github.com/capstone-engine/capstone/issues/1992" ) + def build_test_options(self, options): + new_options = [] + self.mandatory_options + for opt in options: + opt = opt.lower() + if opt in self.remove_options: + continue + elif opt in self.replace_option_map: + new_options.append(self.replace_option_map[opt]) + else: + new_options.append(opt) + return new_options + def build_test_files(self, mc_cmds: list[LLVM_MC_Command]) -> list[TestFile]: log.info("Build TestFile objects") test_files = list() n_all = len(mc_cmds) for i, mcc in enumerate(mc_cmds): print(f"{i + 1}/{n_all} {mcc.file.name}", flush=True, end="\r") + opts = self.build_test_options(mcc.get_opts_list()) test_files.append( TestFile( self.arch, mcc.file, - mcc.get_opts_list() + self.mandatory_options, + opts, mcc, self.unified_test_cases, ) diff --git a/suite/auto-sync/src/autosync/cpptranslator/Configurator.py b/suite/auto-sync/src/autosync/cpptranslator/Configurator.py index f50e9d6928..e8e81cba6d 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/Configurator.py +++ b/suite/auto-sync/src/autosync/cpptranslator/Configurator.py @@ -57,6 +57,12 @@ def get_general_config(self) -> dict: self.load_config() return self.config["General"] + def get_patch_config(self) -> dict: + if self.config: + return self.config["General"]["patching"] + self.load_config() + return self.config["General"]["patching"] + def load_config(self) -> None: if not Path.exists(self.config_path): fail_exit(f"Could not load arch config file at '{self.config_path}'") diff --git a/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py b/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py index 6e4992e7c2..38d28adac5 100755 --- a/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py +++ b/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py @@ -382,32 +382,16 @@ def patch_src(self, p_list: [(bytes, Node)]) -> None: def apply_patch(self, patch: Patch) -> bool: """Tests if the given patch should be applied for the current architecture or file.""" - has_apply_only = ( - len(patch.apply_only_to["files"]) > 0 - or len(patch.apply_only_to["archs"]) > 0 - ) - has_do_not_apply = ( - len(patch.do_not_apply["files"]) > 0 or len(patch.do_not_apply["archs"]) > 0 - ) - - if not (has_apply_only or has_do_not_apply): - # Lists empty. + apply_only_to = self.configurator.get_patch_config()["apply_patch_only_to"] + patch_name = patch.__class__.__name__ + if patch_name not in apply_only_to: + # No constraints return True - if has_apply_only: - if self.arch in patch.apply_only_to["archs"]: - return True - elif self.current_src_path_in.name in patch.apply_only_to["files"]: - return True - return False - elif has_do_not_apply: - if self.arch in patch.do_not_apply["archs"]: - return False - elif self.current_src_path_in.name in patch.do_not_apply["files"]: - return False + file_constraints = apply_only_to[patch_name] + if self.current_src_path_in.name in file_constraints["files"]: return True - log.fatal("Logical error.") - exit(1) + return False def translate(self) -> None: for self.current_src_path_in, self.current_src_path_out in zip( diff --git a/suite/auto-sync/src/autosync/cpptranslator/Differ.py b/suite/auto-sync/src/autosync/cpptranslator/Differ.py index 8cc2a39ad0..b65c85b04d 100755 --- a/suite/auto-sync/src/autosync/cpptranslator/Differ.py +++ b/suite/auto-sync/src/autosync/cpptranslator/Differ.py @@ -636,18 +636,21 @@ def diff_nodes( j = old_node_ids.index(self.cur_nid) while j >= 0 and (old_node_ids[j] not in new_nodes.keys()): j -= 1 - ref_new: Node = ( - new_nodes[old_node_ids[j]] - if old_node_ids[j] in new_nodes.keys() - else new_nodes[0] - ) - ref_end_byte = ref_new.start_byte + if j < 0 or old_node_ids[j] not in new_nodes.keys(): + # No new node exists before the old node. + # So just put it to the very beginning. + ref_end_byte = 1 + ref_start_point = (1, 0) + else: + ref_new: Node = new_nodes[old_node_ids[j]] + ref_end_byte = ref_new.start_byte + ref_start_point = ref_new.start_point # We always write to the new file. So we always take he coordinates form it. patch_coord = PatchCoord( ref_end_byte - 1, ref_end_byte - 1, - ref_new.start_point, - ref_new.start_point, + ref_start_point, + ref_start_point, ) save_exists = False @@ -922,7 +925,7 @@ def parse_args() -> argparse.Namespace: "-a", dest="arch", help="Name of target architecture (ignored with -t option)", - choices=["ARM", "PPC", "AArch64", "Alpha", "LoongArch"], + choices=["ARM", "PPC", "AArch64", "Alpha", "LoongArch", "Mips"], required=True, ) parser.add_argument( diff --git a/suite/auto-sync/src/autosync/cpptranslator/TemplateCollector.py b/suite/auto-sync/src/autosync/cpptranslator/TemplateCollector.py index abab53dc5c..24470aad77 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/TemplateCollector.py +++ b/suite/auto-sync/src/autosync/cpptranslator/TemplateCollector.py @@ -107,7 +107,6 @@ def collect(self): tree = self.parser.parse(src, keep_text=True) query: Query = self.lang_cpp.query(self.get_template_pattern()) - self.get_capture_bundles(query, tree) capture_bundles = self.get_capture_bundles(query, tree) for cb in capture_bundles: diff --git a/suite/auto-sync/src/autosync/cpptranslator/Tests/Patches/test_arch_config.json b/suite/auto-sync/src/autosync/cpptranslator/Tests/Patches/test_arch_config.json index 6fc12a6141..276da32d35 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/Tests/Patches/test_arch_config.json +++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/Patches/test_arch_config.json @@ -5,7 +5,30 @@ "diff_color_saved": "yellow", "diff_color_edited": "light_magenta", "patch_editor": "vim", - "nodes_to_diff": [] + "nodes_to_diff": [], + "patching": { + "apply_patch_only_to": { + "AddCSDetail": { + "files": [ + "ARMInstPrinter.cpp", + "PPCInstPrinter.cpp", + "AArch64InstPrinter.cpp", + "LoongArchInstPrinter.cpp", + "MipsInstPrinter.cpp" + ] + }, + "InlineToStaticInline": { + "files": [ + "ARMAddressingModes.h" + ] + }, + "PrintRegImmShift": { + "files": [ + "ARMInstPrinter.cpp" + ] + } + } + } }, "ARCH": { "files_to_translate": [], diff --git a/suite/auto-sync/src/autosync/cpptranslator/Tests/test_unit.py b/suite/auto-sync/src/autosync/cpptranslator/Tests/test_unit.py new file mode 100644 index 0000000000..ee069211b4 --- /dev/null +++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/test_unit.py @@ -0,0 +1,44 @@ +# SPDX-FileCopyrightText: 2024 Rot127 +# SPDX-License-Identifier: BSD-3 + +import unittest +from pathlib import Path + +from autosync.Helper import get_path +from autosync.cpptranslator import CppTranslator +from autosync.cpptranslator.Configurator import Configurator +from autosync.cpptranslator.patches.AddCSDetail import AddCSDetail +from autosync.cpptranslator.patches.InlineToStaticInline import InlineToStaticInline +from autosync.cpptranslator.patches.PrintRegImmShift import PrintRegImmShift +from autosync.cpptranslator.patches.Data import Data + + +class TestCppTranslator(unittest.TestCase): + @classmethod + def setUpClass(cls): + configurator = Configurator("ARCH", get_path("{PATCHES_TEST_CONFIG}")) + cls.translator = CppTranslator.Translator(configurator, False) + + def test_patching_constraints(self): + self.translator.current_src_path_in = Path("Random_file.cpp") + patch_add_cs_detail = AddCSDetail(0, "ARCH") + patch_inline_to_static_inline = InlineToStaticInline(0) + patch_print_reg_imm_shift = PrintRegImmShift(0) + patch_data = Data(0) + + self.assertFalse(self.translator.apply_patch(patch_add_cs_detail)) + self.assertFalse(self.translator.apply_patch(patch_inline_to_static_inline)) + self.assertFalse(self.translator.apply_patch(patch_print_reg_imm_shift)) + self.assertTrue(self.translator.apply_patch(patch_data)) + + self.translator.current_src_path_in = Path("ARMInstPrinter.cpp") + self.assertTrue(self.translator.apply_patch(patch_add_cs_detail)) + self.assertFalse(self.translator.apply_patch(patch_inline_to_static_inline)) + self.assertTrue(self.translator.apply_patch(patch_print_reg_imm_shift)) + self.assertTrue(self.translator.apply_patch(patch_data)) + + self.translator.current_src_path_in = Path("ARMAddressingModes.h") + self.assertFalse(self.translator.apply_patch(patch_add_cs_detail)) + self.assertTrue(self.translator.apply_patch(patch_inline_to_static_inline)) + self.assertFalse(self.translator.apply_patch(patch_print_reg_imm_shift)) + self.assertTrue(self.translator.apply_patch(patch_data)) diff --git a/suite/auto-sync/src/autosync/cpptranslator/arch_config.json b/suite/auto-sync/src/autosync/cpptranslator/arch_config.json index 03e89797d9..3de3c4efe5 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/arch_config.json +++ b/suite/auto-sync/src/autosync/cpptranslator/arch_config.json @@ -5,6 +5,29 @@ "diff_color_saved": "yellow", "diff_color_edited": "light_magenta", "patch_editor": "vim", + "patching": { + "apply_patch_only_to": { + "AddCSDetail": { + "files": [ + "ARMInstPrinter.cpp", + "PPCInstPrinter.cpp", + "AArch64InstPrinter.cpp", + "LoongArchInstPrinter.cpp", + "MipsInstPrinter.cpp" + ] + }, + "InlineToStaticInline": { + "files": [ + "ARMAddressingModes.h" + ] + }, + "PrintRegImmShift": { + "files": [ + "ARMInstPrinter.cpp" + ] + } + } + }, "nodes_to_diff": [ { "node_type": "function_definition", @@ -51,7 +74,7 @@ "{LLVM_ROOT}/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h" ] }, - "PPC": { + "PPC": { "files_to_translate": [ { "in": "{LLVM_ROOT}/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp", @@ -147,7 +170,47 @@ "{LLVM_ROOT}/llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp", "{LLVM_ROOT}/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.cpp" ], + "templates_with_arg_deduction": [], + "manually_edited_files": [] + }, + "Mips": { + "files_to_translate": [ + { + "in": "{LLVM_ROOT}/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp", + "out": "MipsDisassembler.c" + },{ + "in": "{LLVM_ROOT}/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp", + "out": "MipsInstPrinter.c" + },{ + "in": "{LLVM_ROOT}/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h", + "out": "MipsInstPrinter.h" + } + ], + "files_for_template_search": [ + "{CPP_INC_OUT_DIR}/MipsGenDisassemblerTables.inc", + "{LLVM_ROOT}/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp", + "{CPP_INC_OUT_DIR}/MipsGenAsmWriter.inc" + ], "templates_with_arg_deduction": [ + "DecodeINSVE_DF", + "DecodeDAHIDATIMMR6", + "DecodeDAHIDATI", + "DecodeAddiGroupBranch", + "DecodePOP35GroupBranchMMR6", + "DecodeDaddiGroupBranch", + "DecodePOP37GroupBranchMMR6", + "DecodePOP65GroupBranchMMR6", + "DecodePOP75GroupBranchMMR6", + "DecodeBlezlGroupBranch", + "DecodeBgtzlGroupBranch", + "DecodeBgtzGroupBranch", + "DecodeBlezGroupBranch", + "DecodeBgtzGroupBranchMMR6", + "DecodeBlezGroupBranchMMR6", + "DecodeDINS", + "DecodeDEXT", + "DecodeCRC", + "isReg" ], "manually_edited_files": [] } diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py b/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py index fcb5f912bf..84afa6952c 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py @@ -31,6 +31,7 @@ class AddCSDetail(Patch): valid_param_lists = [ b"(MCInst*MI,unsignedOpNum,SStream*O)", # Default printOperand parameters. b"(MCInst*MI,unsignedOpNo,SStream*O)", # ARM - printComplexRotationOp / PPC default + b"(MCInst*MI,intopNum,SStream *O)", # Mips - printMemOperandEA and others b"(SStream*O,ARM_AM::ShiftOpcShOpc,unsignedShImm,boolgetUseMarkup())", # ARM - printRegImmShift b"(MCInst*MI,unsignedOpNo,SStream*O,constchar*Modifier)", # PPC - printPredicateOperand b"(MCInst*MI,uint64_tAddress,unsignedOpNo,SStream*O)", # PPC - printBranchOperand @@ -39,15 +40,6 @@ class AddCSDetail(Patch): def __init__(self, priority: int, arch: str): super().__init__(priority) self.arch = arch - self.apply_only_to = { - "files": [ - "ARMInstPrinter.cpp", - "PPCInstPrinter.cpp", - "AArch64InstPrinter.cpp", - "LoongArchInstPrinter.cpp", - ], - "archs": list(), - } def get_search_pattern(self) -> str: return ( @@ -88,11 +80,15 @@ def get_add_cs_detail( ) # Remove "print" from function id is_template = fcn_def.prev_sibling.type == "template_parameter_list" - op_num_var_name = ( - b"OpNum" - if b"OpNum" in params - else (b"OpNo" if b"OpNo" in params else b"-.-") - ) + if b"OpNum" in params: + op_num_var_name = b"OpNum" + elif b"OpNo" in params: + op_num_var_name = b"OpNo" + elif b"opNum" in params: + op_num_var_name = b"opNum" + else: + raise ValueError("OpNum parameter could not be identified.") + if not is_template and op_num_var_name in params: # Standard printOperand() parameters mcinst_var = get_MCInst_var_name(src, fcn_def) diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py b/suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py index 8133e7b683..58092ea09d 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py @@ -41,9 +41,9 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: # Determine width of instruction by the variable name. if ffi_first_arg_text[-2:] == "32": - inst_width = 4 + inst_width = b"4" elif ffi_first_arg_text[-2:] == "16": - inst_width = 2 + inst_width = b"2" else: # Get the Val/Inst parameter. # Its type determines the instruction width. @@ -55,17 +55,38 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: inst_type = inst_param_text.split(b" ")[0] if inst_type: if inst_type in [b"unsigned", b"uint32_t"]: - inst_width = 4 + inst_width = b"4" elif inst_type in [b"uint16_t"]: - inst_width = 2 + inst_width = b"2" + elif inst_type in [b"InsnType"]: + # Case means the decode function inherits the type from + # a template argument InsnType. The InsnType template argument + # is the type of integer holding the instruction bytes. + # This type is defined in ARCHDisassembler on calling the right macro. + # Hence, we do not know at this point of patching which type it might be. + # It needs to call fieldOfInstruction_X() which detects dynamically which + # integer type might hold the bytes (e.g. a uint32_t or uint16_t). + # You can check it manually in ARCHDisassembler.c, but the script can't. + # + # Here we just create a function with the postfix fieldFromInstruction_w (for width). + # This function must be implemented by hand, and check MCInst for the actual bit width. + # The bit width must be set in the ARCHDisassembler.c. Just add the code there by hand. + # Then call fieldFromInstruction_4, fieldFromInstruction_2 appropriately. + log.warning( + "Variable fieldFromInstruction width detected.\n" + "Please implement fieldFromInstruction_w() and call " + "fieldFromInstruction_4, fieldFromInstruction_2 appropriately.\n" + "In fieldFromInstruction_w() check MCInst for the actual bit width.\n" + "The bit width must be set in the ARCHDisassembler.c. Just add the code there by hand." + ) + inst_width = b"w" else: - log.fatal(f"Type {inst_type} no handled.") - exit(1) + raise ValueError(f"Type {inst_type} not handled.") else: # Needs manual fix return get_text(src, ffi_call.start_byte, ffi_call.end_byte) return re.sub( rb"fieldFromInstruction", - b"fieldFromInstruction_%d" % inst_width, + b"fieldFromInstruction_%s" % inst_width, get_text(src, ffi_call.start_byte, ffi_call.end_byte), ) diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py b/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py index d8bc3e1d63..01b69b5bec 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py @@ -64,6 +64,8 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: return res + get_AArch64_includes(filename) + get_general_macros() case "LoongArch": return res + get_LoongArch_includes(filename) + get_general_macros() + case "Mips": + return res + get_Mips_includes(filename) + get_general_macros() case "TEST_ARCH": return res + b"test_output" case _: @@ -294,6 +296,43 @@ def get_LoongArch_includes(filename: str) -> bytes: exit(1) +def get_Mips_includes(filename: str) -> bytes: + match filename: + case "MipsDisassembler.cpp": + return ( + b'#include "../../MCInst.h"\n' + + b'#include "../../MathExtras.h"\n' + + b'#include "../../MCInstPrinter.h"\n' + + b'#include "../../MCDisassembler.h"\n' + + b'#include "../../MCFixedLenDisassembler.h"\n' + + b'#include "../../cs_priv.h"\n' + + b'#include "../../utils.h"\n' + + b"#define GET_SUBTARGETINFO_ENUM\n" + + b'#include "MipsGenSubtargetInfo.inc"\n\n' + + b"#define GET_INSTRINFO_ENUM\n" + + b'#include "MipsGenInstrInfo.inc"\n\n' + + b"#define GET_REGINFO_ENUM\n" + + b'#include "MipsGenRegisterInfo.inc"\n\n' + ) + case "MipsInstPrinter.cpp": + return ( + b'#include "MipsMapping.h"\n' + + b'#include "MipsInstPrinter.h"\n\n' + + b"#define GET_SUBTARGETINFO_ENUM\n" + + b'#include "MipsGenSubtargetInfo.inc"\n\n' + + b"#define GET_INSTRINFO_ENUM\n" + + b'#include "MipsGenInstrInfo.inc"\n\n' + + b"#define GET_REGINFO_ENUM\n" + + b'#include "MipsGenRegisterInfo.inc"\n\n' + ) + case "MipsInstPrinter.h": + return ( + b'#include "../../MCInstPrinter.h"\n' + b'#include "../../cs_priv.h"\n' + ) + log.fatal(f"No includes given for Mips source file: {filename}") + exit(1) + + def get_general_macros(): return ( b"#define CONCAT(a, b) CONCAT_(a, b)\n" b"#define CONCAT_(a, b) a ## _ ## b\n" diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/InlineToStaticInline.py b/suite/auto-sync/src/autosync/cpptranslator/patches/InlineToStaticInline.py index 8d07e8e099..9c267811ac 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/InlineToStaticInline.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/InlineToStaticInline.py @@ -19,7 +19,6 @@ class InlineToStaticInline(Patch): def __init__(self, priority: int): super().__init__(priority) - self.apply_only_to = {"files": ["ARMAddressingModes.h"], "archs": list()} def get_search_pattern(self) -> str: return ( diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/Patch.py b/suite/auto-sync/src/autosync/cpptranslator/patches/Patch.py index 6f82a0b494..a08cb72ead 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/Patch.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/Patch.py @@ -9,17 +9,6 @@ class Patch: priority: int = None - # List of filenames and architectures this patch applies to or not. - # Order of testing: - # 1. apply_only_to.archs - # 2. apply_only_to.files - # 3. do_not_apply.archs - # 4. do_not_apply.files - # Contains the _in_ filenames and architectures this patch should be applied to. Empty list means all. - apply_only_to = {"files": list(), "archs": list()} - # Contains the _in_ filenames and architectures this patch should NOT be applied to. - do_not_apply = {"files": list(), "archs": list()} - def __init__(self, priority: int = 0): self.priority = priority diff --git a/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json b/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json index ba5380dd0f..6781acfaa5 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json +++ b/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json @@ -2408,5 +2408,887 @@ "new_hash": "02eaaa869cf975da8203666135470c113ad9246dd2f73061dbf6ee1706683299", "edit": "" } + }, + "MipsDisassembler.c": { + "\"../../MCRegisterInfo.h\"": { + "apply_type": "OLD", + "old_hash": "cd51ed81136ebf5690cdb06e839868574304a3f5c949cdde4fd43f2f994d5c17", + "new_hash": "", + "edit": "" + }, + "\"MipsCP0RegisterMap.h\"": { + "apply_type": "OLD", + "old_hash": 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"76974afd5d6e304a422aace7f67390ce9c0c84dbff8eab04b14ed7ce8ce8111d", + "edit": "" + }, + "DecodeAFGR64RegisterClass": { + "apply_type": "OLD", + "old_hash": "2a056147501e4d5f1145853188536fbba956dd3836100fe5d78d5f59929d6c33", + "new_hash": "8e4a1bea8b089e93dee79cc31db2ed7d7aa0e7e489e4aa77430f169c3853e317", + "edit": "" + }, + "DecodeANDI16Imm": { + "apply_type": "OLD", + "old_hash": "8e5683e1b373c36db0dd7986f48106fbb3b5ca838a16f15a38f4ff8e314bd158", + "new_hash": "01a1ccd1faaa59286f22642aa253f0954edd7c99a9eca640ff1794dc69be7dd3", + "edit": "" + }, + "DecodeAddiGroupBranch": { + "apply_type": "OLD", + "old_hash": "09bade65e0befce00b53acb3f02d457ec2278cc46f0daa1190bca480655493d4", + "new_hash": "b43fc4d444b7d2f2ce3d8c8bdd6ad23d184564209c01ada6daf1b79eaef0be2a", + "edit": "" + }, + "DecodeBgtzGroupBranch": { + "apply_type": "OLD", + "old_hash": "48919afd95fa96acccc13339983e281ff8bfe70b5dbdd9478a304e048a263788", + "new_hash": "47188d8de7ccc86f3185b5ad77b7f4845efc9c9f54a39e9b01ee01ba191f6b0d", + "edit": "" + }, + "DecodeBgtzGroupBranchMMR6": { + "apply_type": "OLD", + "old_hash": "dfa41913e0654e9d1953eedbbec7a58de77200b22c81072fa663e8719a6a106e", + "new_hash": "437c10dd2bdd1491398dce2c0938802686659c485c302dcbd2380a1a4750c34f", + "edit": "" + }, + "DecodeBgtzlGroupBranch": { + "apply_type": "OLD", + "old_hash": "a2f93190037f79b6e8df1ab8a5dc65d2644c370c92351725d7d69c3073fb1a22", + "new_hash": "4a47c796517439f5de5b3e0deda2a4a1a72c03e40638564d24d49976cd2c2804", + "edit": "" + }, + "DecodeBlezGroupBranch": { + "apply_type": "OLD", + "old_hash": "881389b72656cfe8f41e6d56b58b0de97a27366c92099dd6655275e8d4f79d64", + "new_hash": "dc0a55c1a9551a8b7d956c529419b849f4fb658974a22546ed9f16a3541cc17b", + "edit": "" + }, + "DecodeBlezGroupBranchMMR6": { + "apply_type": "OLD", + "old_hash": "429dbed22e5fa2ecfaf2de4ee982b8ae786e6e2af15b9c4c857579bbcfbe4c28", + "new_hash": "1cf4577ffd64485bfcffaf9bf2e9f3d53eb9a39a516476595d1a3812c71f51b7", + "edit": "" + }, + "DecodeBlezlGroupBranch": { + "apply_type": "OLD", + "old_hash": "b458eb7370480f44c2cc21a34c8abd7122186d5fadc896bb95e0a0ab587e9e8c", + "new_hash": "e3cfabf394618d99c9b46a7619fc04425354af31c4f96841868308c3454ac4fe", + "edit": "" + }, + "DecodeBranchConflictNM": { + "apply_type": "OLD", + "old_hash": "4dcfebb897eb2f7e4f98bc962f070a385628c212d2439d6a24cab1f65060907d", + "new_hash": "3ae97ba3f294fcb6fdf7ed3e0c0903a5bdf497f67b74de385a17d60cee6209bd", + "edit": "" + }, + "DecodeCCRRegisterClass": { + "apply_type": "OLD", + "old_hash": "7537a7c8cb794bcbce23c25c14fdf5973978ca63dcc2ff907a6cb7dbfe179365", + "new_hash": "ef1a21490da18c7d3efab75e620ee7ac54f9c9786fb8acc75a874957ec9445bc", + "edit": "" + }, + "DecodeCOP0RegisterClass": { + "apply_type": "OLD", + "old_hash": "94a27091bd390ecd0e748c19b51595a32ddfde49eb909d71d124d8be3d325361", + "new_hash": "801f8333392af710747431f8ccdfeca99c9d8699cb3b89220c9fd448fea0298c", + "edit": "" + }, + "DecodeCOP0SelRegisterClass": { + "apply_type": "OLD", + "old_hash": "f5a63d8275a1decb9ba53dd1b5a91ef759108f0a45f0fe147152e12ca8585f2f", + "new_hash": "0ddaf2c039d0eedc9896553b3b690c5455c95f880ace756147d0ee5a97aa6d1e", + "edit": "" + }, + "DecodeCOP2RegisterClass": { + "apply_type": "OLD", + "old_hash": "7d09e567ed79598c6f93ab8e678ec1808aa4dccddae2cd2a6d09f9be8f8d8d81", + "new_hash": "6a86b848a18ab43fd3264f7f59966b376310ced22334abd943b9d3c8b31d3151", + "edit": "" + }, + "DecodeCRC": { + "apply_type": "OLD", + "old_hash": "83c959b6c4320ce29c93314c0ba0e9fca53d28604aacd0b983e8621f89251295", + "new_hash": "dcae12d771467e9460884070a059ead28fcf5af081f895a0426698bcca21d8e7", + "edit": "" + }, + "DecodeCacheOp": { + "apply_type": "OLD", + "old_hash": "e7a01cbfba43657e3d3a30f325c2264cc099ef86e3b5df00b58e1b87689982d1", + "new_hash": "fe6a8c08fe9336648e93488690d6f2f7d9ea71e0a3c1414fa5c7c52dd666d148", + "edit": "" + }, + "DecodeCacheOpMM": { + "apply_type": "OLD", + "old_hash": "40eb48f6ab8caba180df9a1e6981fbe8d3085c4ca6ceb587d6176decf576cf97", + "new_hash": "bef5a5f5370574821798ff32353999e15f8c7d8d1bba7e505134cdc95b3e3012", + "edit": "" + }, + "DecodeCacheeOp_CacheOpR6": { + "apply_type": "OLD", + "old_hash": "5c663ec5a7170ada94098367b760e0e59e136bba2081eccbf81a50542047d000", + "new_hash": "d7f032176fcdb9b572422396d34a7dfa542cd162f1293b636c1f7dfab647889f", + "edit": "" + }, + "DecodeDAHIDATI": { + "apply_type": "OLD", + "old_hash": "101bf5aed677836cafaa3815e8c13c187ccb8e765cb1f24b8f153225897eb465", + "new_hash": "6f04649744c05bb272e11854ae4025b40ef8af8342fa90bf5fc6d9577add83c0", + "edit": "" + }, + "DecodeDAHIDATIMMR6": { + "apply_type": "OLD", + "old_hash": "", + "new_hash": "d1d5a08fc3a0c15f1cc355de848ff0dcb8b55ccbc8bf0a6f7c166f82eb7f6ef7", + "edit": "" + }, + "DecodeDEXT": { + "apply_type": "OLD", + "old_hash": "85e57cd508578717942e5505055d4f68ada5e518ebe5981e9011a9c678681b5f", + "new_hash": "b43132bc601a931f5b319621b9b131b7c05e8a0afbd4e66d58a8e637781346b8", + "edit": "" + }, + "DecodeDINS": { + "apply_type": "OLD", + "old_hash": "c6a174da60d9fe2e1483b5fa12b8d38ed9ccbe6bc6af97ef915a13595b97b738", + "new_hash": "e6f3f842c133553372bba7e0951c187282865e8f6902e596259a09b965b99268", + "edit": "" + }, + "DecodeDaddiGroupBranch": { + "apply_type": "OLD", + "old_hash": "edd7d82241e74bafc0248ec43e87addd7ff2047c6c90c0c5c507306ce4b8734a", + "new_hash": "5bfb532a6c72924403ccd2dc2bf39b53dce36bcf9aa29867696220d3ee50c948", + "edit": "" + }, + "DecodeFCCRegisterClass": { + "apply_type": "OLD", + "old_hash": "8afd27cbb09289193ebf0bf207600cf59cbec2da3ba059dd27524e8aa23ee387", + "new_hash": "a570707a0c0499ac98e8b6c35b85d4dba5e8e0a6987566a899472b4cc5ceb0dc", + "edit": "" + }, + "DecodeFGR32RegisterClass": { + "apply_type": "OLD", + "old_hash": "d1558a16b6cadd0664e83c16ed2e13a85753246c1aac9e9c29866551deb01716", + "new_hash": "0bd9aa50728c2052ae0e7955337e5aca9418a15bd5cc50f4b8dc62aafabcbd74", + "edit": "" + }, + "DecodeFGR64RegisterClass": { + "apply_type": "OLD", + "old_hash": "886427c10e1d4beea2b72599021ee97332de7bcce5f229812f5452c1d34a11cd", + "new_hash": "dd6a5b96d743f6f2fe97473f7d9bf23b584a1fed9adf080cb94a3de87305c527", + "edit": "" + }, + "DecodeFGRCCRegisterClass": { + "apply_type": "OLD", + "old_hash": "0931e013ea0563b6390461fee1e65743dc14dc661113c04934aedb68a712442c", + "new_hash": "ac5d0e09e6f73c19200a3e39d40a3ecf0352667cad05b4011439b8203decc8bd", + "edit": "" + }, + "DecodeFIXMEInstruction": { + "apply_type": "OLD", + "old_hash": "1662f0a3f2d863ca6accd41cff2520a6cab91d2718387d3c50a4a91b0d0ffee0", + "new_hash": "86daf866c09624ad93a971ff3c83f9a5b4b1da23671fa3b3ea775c286cbb0851", + "edit": "" + }, + "DecodeFMem": { + "apply_type": "OLD", + "old_hash": "0622bfe67914aefbbfe7c0e707e0c02002ad6e121008a84bd027bbe56cc3dbc7", + "new_hash": "ce01734d25c2eb5b9c76237433f1a8e9a2d1d5bc9083539392cddf2f25dc2ab0", + "edit": "" + }, + "DecodeFMem2": { + "apply_type": "OLD", + "old_hash": "8aa77160a71cf966de56193a8a0856ff7c7cdc8fb1f33eb0b78ceadc92e18dc8", + "new_hash": "6ed8227bb07a26a147d0915e1cf75e1872b790f74271c52d894f9d713a48ad03", + "edit": "" + }, + "DecodeFMem3": { + "apply_type": "OLD", + "old_hash": "7de68fb557558781dce12417a4908c147f0151b78f13988f99aa1aad5d851ae2", + "new_hash": "b6bdf6a0cadd9e73963c8f77c52f95663c9af7088af555049c26d5b01cb07d38", + "edit": "" + }, + "DecodeFMemCop2MMR6": { + "apply_type": "OLD", + "old_hash": "72a284dcb454804d61a04427aa1fdebdafc1f9ad0ff37e6268b391a6e794f923", + "new_hash": "e02747533bfc65c4929ad44216df14f87a5e712a60386a1bb26a2134de80633f", + "edit": "" + }, + "DecodeFMemCop2R6": { + "apply_type": "OLD", + "old_hash": "e71ce24c072c55707ff0efef16bac1879899f6ac63859cb550ee384eb6024359", + "new_hash": "b4243228a19fd134232d52ec2d31d9599e7b1a775446c21b3af89cf262162597", + "edit": "" + }, + "DecodeFMemMMR2": { + "apply_type": "OLD", + "old_hash": "605544b7fdb0a2a0efcb79b41a7cc9185852234a2800286f8d23c6ad51ffdadb", + "new_hash": "e8b30b55428ae7965497b3d0cd659e19051a8f2cce74c200e6acb4d695b3d385", + "edit": "" + }, + "DecodeGPR32RegisterClass": { + "apply_type": "OLD", + "old_hash": "01fe48927278e9075f5a581553621f4a9dbf92d187eb7688103e008a63d2fd33", + "new_hash": "60c66ad7d0eb9567c0fd2c57adf68d0561f141f782b0f0ec00fca8f4afeb486c", + "edit": "" + }, + "DecodeGPR64RegisterClass": { + "apply_type": "OLD", + "old_hash": "21436e4ab5450d91cf1eaced506301b8f89c7454fca28786e6cb4ea0f3b678d4", + "new_hash": "bfc513cf62ecdc300d7587ccec4681697e716b1b2907ae791add867adea9a0cf", + "edit": "" + }, + "DecodeGPRMM16MovePRegisterClass": { + "apply_type": "OLD", + "old_hash": "f4c9cd17f3fa131e0c1cae7d4029c7f30481a5fd7cdcc203069ac448acd29c1e", + "new_hash": "67b715888f148b8db14ad1d15057054a2627d864960171edecffe65fd18ed289", + "edit": "" + }, + "DecodeGPRMM16RegisterClass": { + "apply_type": "OLD", + "old_hash": "9ff975b1b76c4d33c1e1b2539c9ba7e6fabd087ea0b0abd060b84f396321115b", + "new_hash": "34be26d66002e933e1a5f91c0af0327188101269673e29dd73b2d7f6dccf298c", + "edit": "" + }, + "DecodeGPRMM16ZeroRegisterClass": { + "apply_type": "OLD", + "old_hash": "e1e4b0b36c9a69e6d50ec874e5a3209928486a3774a406bf23377bd1c973183d", + "new_hash": "c55909fe1cb130d3367823187c5340da4f71d5a3b7b9a1705798a7cd130ee192", + "edit": "" + }, + "DecodeGPRNM1R1RegisterClass": { + "apply_type": "OLD", + "old_hash": "b7e713086c0503e8b53091c169d32011b2a8bc07c9827c185e4eeb7b16506c2e", + "new_hash": "4328db38bd47b66c3497b83d210ddae3b5ab3f7087f9d0003e977b23c2beea40", + "edit": "" + }, + "DecodeGPRNM2R1RegisterClass": { + "apply_type": "OLD", + "old_hash": "9009300dc9e11dbdff0644d1341e7820cfd500fb49501beb6c03a937b9ba3377", + "new_hash": "2f190511e928a65b20d65036239615588eaa07cb4e01634b286dad9638ba8969", + "edit": "" + }, + "DecodeGPRNM32NZRegisterClass": { + "apply_type": "OLD", + "old_hash": "0a87149ed0b369827e7a247dfff3a7ad0bed8343135fb42349d6e8bae6f819b5", + "new_hash": "5ee794ae59fca5b28c4221073242e0df99af78fd0e61fdb7cfa3715752b30c3a", + "edit": "" + }, + "DecodeGPRNM32RegisterClass": { + "apply_type": "OLD", + "old_hash": "ebadcfe00840f95ea448bdfe426c404c4e6ea61d7320d33346a0740de900a294", + "new_hash": "abc39a082a14fbe325ef37d65548cb0bae29fb3419a8467ee4492ed352c5943a", + "edit": "" + }, + "DecodeGPRNM3RegisterClass": { + "apply_type": "OLD", + "old_hash": "e19a92a144da863186c78b84cf63271d7b7d31c50e67754fb2ae49032da0115a", + "new_hash": "eb0f15f684e409c9aca72e9e0603eefcba2042eacdf2be40541e5a6cbfdf8084", + "edit": "" + }, + "DecodeGPRNM3ZRegisterClass": { + "apply_type": "OLD", + "old_hash": "6ebf274455dd1960747b9c859aa20aee54b5f36bc87a55a9eb964f676cf6f276", + "new_hash": "8789625cc7cf145f88541a14cd720aba0727d5d5e17d0415b9ed236a8467a9d3", + "edit": "" + }, + "DecodeGPRNM4RegisterClass": { + "apply_type": "OLD", + "old_hash": "ca5dc2096b2fbd356983abe307feea8159f61ebdb680e11ffc45c7b013b4cd4c", + "new_hash": "62455ebbd50323f9b31eeb1a625a008005d397d371e0a06de139f747ce96ea6c", + "edit": "" + }, + "DecodeGPRNM4ZRegisterClass": { + "apply_type": "OLD", + "old_hash": "5a4149c96e82da02bedabacda3feadd990058eb94f06c1b80408e9bc521fc296", + "new_hash": "7dd06b036e8808c5c0c78a56df9d5c9543926d63abec39e60ee9193a1fe5d02b", + "edit": "" + }, + "DecodeHI32DSPRegisterClass": { + "apply_type": "OLD", + "old_hash": "de0ccbf1bc814dc89cc5a46b229685f48a5c0e401dfd70fd9b82180496f33dae", + "new_hash": "2586a565685979245d5dad3499c9b530c1e6441e85ad738591b7994eb787736e", + "edit": "" + }, + "DecodeINSVE_DF": { + "apply_type": "OLD", + "old_hash": "ce6c3f16ea2b2363897a92cc3558793ef7fb039d229a7b27b63464ce01e895b2", + "new_hash": "442c000afb4bacbb41402ab649f6ddef973ba7596bc9ee87dcc51acb8414ef54", + "edit": "" + }, + "DecodeInsSize": { + "apply_type": "OLD", + "old_hash": "196732908c3ea812a585f4917c46529676c9583cb6b660e5dc8b61f55c57b239", + "new_hash": "4a68f7706deff574fd862541e1461b83abc3157afe666e38da9a590a99e4a25e", + "edit": "" + }, + "DecodeJumpTarget": { + "apply_type": "OLD", + "old_hash": "366940aaf77dec2847ea51cef4bc297f8d545d79040157e22ec82337d536e273", + "new_hash": "2e6bc1429c146b2b845a8f4c8f0608defc86796a869442302ceb6741217de4d9", + "edit": "" + }, + "DecodeJumpTargetMM": { + "apply_type": "OLD", + "old_hash": "7e72091982c6d7c26b521f1e9f117938acfd28ceaa6bc1dc070acdac2f92ad80", + "new_hash": "f59cbde6804c7437c267f0a85f620b21026142fc139e48a1cb48089db4b24ff0", + "edit": "" + }, + "DecodeJumpTargetXMM": { + "apply_type": "OLD", + "old_hash": "7cbce5cb38df425c1e5c7b5948d0d4a2db53ad013cd1626562a86f0dc09cd7b4", + "new_hash": "5a415ad2e0d33f700721371e20db013ce11b49fccb966d2dae97ca6b208e2f3e", + "edit": "" + }, + "DecodeLO32DSPRegisterClass": { + "apply_type": "OLD", + "old_hash": "36599d8def43d07474dba6fea03f8a9059d25d9a7e7bacd59749099ba4497c28", + "new_hash": "f4cfd1ca699075b1ca73f0c76e70aa4e8f1e6523c8e0b84d4eb06be697660067", + "edit": "" + }, + "DecodeLoadByte15": { + "apply_type": "OLD", + "old_hash": "f4538c0428b2aacc0f9ff1418022f3b55aa7f17a189734168710e01615dc83f2", + "new_hash": "5119e0e3d50b1dc2dc4dd8d2b54961f54fbf63858b92a3ab505d2b73da6bb76e", + "edit": "" + }, + "DecodeMSA128BRegisterClass": { + "apply_type": "OLD", + "old_hash": "45d120cc3c9a607c653cf6859833981ef0376af1366fefff56123e75496f86bd", + "new_hash": "e75ac1c584d02726e64870b089b9ceb98e52c75d349eb2c978ca0dd563ac1fd3", + "edit": "" + }, + "DecodeMSA128DRegisterClass": { + "apply_type": "OLD", + "old_hash": "ed8b07cdc72075e5084063e93b1caf84cf7b8429a11c81c516a1b9b13717bf2d", + "new_hash": "9e97999e5acfb898a2e020ff5c11669b1f9de64e98d80733637e95d92977a7f4", + "edit": "" + }, + "DecodeMSA128HRegisterClass": { + "apply_type": "OLD", + "old_hash": "6eb6a7417ec9cb16e195f639c5f706eda96d324fbdfc6c5ae309ec209a5162f7", + "new_hash": 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"edit": "" + }, + "DecodeMemEVA": { + "apply_type": "OLD", + "old_hash": "8078301d20e2b3ff72aa5dab4e6513d4f5ad7820887fefe66d319eb8ee9756cc", + "new_hash": "e2f1753fef99a6bd72b806d2191161486eb43d3181b323d19163d241f4fa2c47", + "edit": "" + }, + "DecodeMemMMGPImm7Lsl2": { + "apply_type": "OLD", + "old_hash": "b3887690da17e10aa339bb11ce9f9d93e187e18b8db7965204b4c6a0eb4ebdfc", + "new_hash": "2a99f5f060258909f8a06d02add9c67844031c102d038c9fc62e49df64af0600", + "edit": "" + }, + "DecodeMemMMImm12": { + "apply_type": "OLD", + "old_hash": "59685841408fdb829b77aca41b2622400995fc558c4873f9135f4c95b3a0e4e0", + "new_hash": "1e11b4b9d2fd54c66421697f2630bd7e2a40ddfb484330b608e5240177b2be6f", + "edit": "" + }, + "DecodeMemMMImm16": { + "apply_type": "OLD", + "old_hash": "24e106e9042361fb386dac3ce28284fd7b2f9e2c1ee137fd2f16027f21c7031a", + "new_hash": "c6f231225285b671b142dc4d7d649d8f64aec7469237dfdd8b8c384557dcf89a", + "edit": "" + }, + "DecodeMemMMImm4": { + "apply_type": "OLD", + "old_hash": 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"new_hash": "2f3a1675ad0c890387cb531b3af265ebb5ebe44a3b21b06cb17ea840a91b6854", + "edit": "" + }, + "DecodeMemZeroNM": { + "apply_type": "OLD", + "old_hash": "caa781e926f202d80a7b6b00271965272c3d6905a38de197bad2321865822eb4", + "new_hash": "7725f35131ddb3adfc509ffb5ad06cb67ba3c35aa0a9466c68fefd220ed70fad", + "edit": "" + }, + "DecodeMovePOperands": { + "apply_type": "OLD", + "old_hash": "a96bc6d32db269f13d8d060aa4d159690299a82cefe15ea03f05648b7d986e18", + "new_hash": "4e61793fc14e47113df183f724cd5f7f0d1583cb853065dbc8266f7b089bc632", + "edit": "" + }, + "DecodeNMRegList16Operand": { + "apply_type": "OLD", + "old_hash": "f96dcb8285057e580d1be6b4ede3179b7fc1be0f32c0696fe716e62b9ff04723", + "new_hash": "c7acc6beeba68228f433a8d3fc54c94844e457f8a94d05741ba7cd4a6f086039", + "edit": "" + }, + "DecodeNMRegListOperand": { + "apply_type": "OLD", + "old_hash": "0ba85031a34392847e9b0f499186c6ca365fea840baba36ca5ff27fb45663688", + "new_hash": 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"printHi20PCRel": { + "apply_type": "OLD", + "old_hash": "1e501b0a3f2fd3556a6ba59dcb70ea2b5de37060390d628e952f2fec787360eb", + "new_hash": "d5f95f06aba32b0f3a2920b319c33e69ec3ec1598a35b2462df419aa9a6841a6", + "edit": "" + }, + "printInst": { + "apply_type": "OLD", + "old_hash": "", + "new_hash": "3aec06d252656b5d52191046737785e713ba284069d7877b347c94e25b02a546", + "edit": "" + }, + "printJumpOperand": { + "apply_type": "OLD", + "old_hash": "6d084ada9b6feec97e1548800407bbbe428a8787c514992d9bf8efd73176f717", + "new_hash": "844ffab898f4ad38b9b9467897583d1b6c65cebdae729df0412af73537c97e64", + "edit": "" + }, + "printMemOperand": { + "apply_type": "OLD", + "old_hash": "0bee738dab28731710512bf16fa03f31f10209f777cea83f0d16aa66412e6201", + "new_hash": "b23d985030fe56708a6cb5bb6a433c24fbca10e89f094a24ebfeae33b65af0d3", + "edit": "" + }, + "printMemOperandEA": { + "apply_type": "OLD", + "old_hash": "0629eed2d2eee3a553c38cb62077ce29e4398f601afa06d0233f4cf70c976cea", + "new_hash": "615aacb0ba3bb7bc63c827aaef822bfb7552b9688408181f819a8aaa388dd123", + "edit": "" + }, + "printMemOperandGPRel": { + "apply_type": "OLD", + "old_hash": "", + "new_hash": "03a58352102b07f37da60354963648a2d0c383bfb3755aa06a33b85a0b81364c", + "edit": "" + }, + "printNanoMipsRegisterList": { + "apply_type": "OLD", + "old_hash": "d5e6ad71c9661c2996c8d3fd158d854c7968d994c2443cbb87db4eaf27b38602", + "new_hash": "93f0b35923e7f7079d1a4ad82b9b7bcf75f61bfa7c8b77f745954be739771e0d", + "edit": "" + }, + "printOperand": { + "apply_type": "OLD", + "old_hash": "f82a0d318d803c5e649a76333382391aaf33a5f70111d8097fd1a0e29806f25b", + "new_hash": "2b2d943eefb4583bd34b5019b60892078c38b58e9304d63927d9034ce5d8b2a9", + "edit": "" + }, + "printPCRel": { + "apply_type": "OLD", + "old_hash": "cbea0cd3eeece2e8e35a20a198c68f9dc8768e85225e71c22ec0b41a6fdd45e7", + "new_hash": "56fa496c7e24b743f39d041a74c8625d8c513c239112aff9b2097b5f9365ff46", + "edit": "" + }, + "printRegName": { + "apply_type": "OLD", + "old_hash": "2bb60804f739dbad89ceadcea389c7b4151a11feac690098942a28fc56288beb", + "new_hash": "229be3874bde1bf33bc0120c4b8c6134d789903c49fe21b2e3d33a4185854357", + "edit": "" + }, + "printRegisterList": { + "apply_type": "OLD", + "old_hash": "cbdbe99cacca7a7173ff929ef118be9f3968b1619c58f3f3cb20000a223d3770", + "new_hash": "774bbb5782799c798145d78be150dc2b2c7016ebf4723988122610d034402ada", + "edit": "" + }, + "printSHFMask": { + "apply_type": "OLD", + "old_hash": "", + "new_hash": "6a1963dc458109069478f4474a8158a025c3177263daac00c45504d5da042391", + "edit": "" + }, + "printSaveRestore": { + "apply_type": "OLD", + "old_hash": "", + "new_hash": "f5c17b2b290fa440877c0b85c85bcc9b050891db002932e0c6448b7f5649339d", + "edit": "" + } + }, + "MipsInstPrinter.h": { + "DECLARE_printUImm": { + "apply_type": "OLD", + "old_hash": "faefa6d7d623550d91fcf096238173c734b43b0717806ce8313f4c4ffb549cd8", + "new_hash": "6bae637a74ba6624001e568e7b960417c99cd2b8fa2d310bc30b1328585cd223", + "edit": "" + }, + "DECLARE_printUImm_2": { + "apply_type": "OLD", + "old_hash": "81028329d6713020ee9beb36a8a459f2672dd35838aa2f682f74407c9dda8dc0", + "new_hash": "", + "edit": "" + } } } \ No newline at end of file diff --git a/suite/auto-sync/src/autosync/mcupdater.json b/suite/auto-sync/src/autosync/mcupdater.json index 5e0e26618d..71fb8218d4 100644 --- a/suite/auto-sync/src/autosync/mcupdater.json +++ b/suite/auto-sync/src/autosync/mcupdater.json @@ -1,10 +1,79 @@ { - "additional_mattr": - { - "AArch64": [ "+all" ] - }, - "mandatory_options": - { - "SystemZ": [ "CS_MODE_BIG_ENDIAN" ] - } -} + "additional_mattr": + { + "AArch64": + [ + "+all" + ] + }, + "mandatory_options": + { + "SystemZ": + [ + "CS_MODE_BIG_ENDIAN" + ], + "Mips": + [ + "CS_OPT_SYNTAX_NOREGNAME" + ] + }, + "remove_options": + { + "Mips": + [ + "mips", + "dsp", + "dspr2", + "dspr3", + "mips3d", + "msa", + "eva", + "crc", + "virt", + "ginv", + "fp64", + "+virt", + "mt" + ] + }, + "replace_option_map": + { + "Mips": + { + "mips-unknown-linux": "CS_MODE_BIG_ENDIAN", + "mips-unknown-linux-gnu": "CS_MODE_BIG_ENDIAN", + "mips32-unknown-linux": "CS_MODE_BIG_ENDIAN", + "mips64-unknown-linux": "CS_MODE_BIG_ENDIAN", + "mips64-unknown-linux-gnu": "CS_MODE_BIG_ENDIAN", + "mips64el-unknown-linux": "CS_MODE_LITTLE_ENDIAN", + "mips64el-unknown-linux-gnu": "CS_MODE_LITTLE_ENDIAN", + "mipsel": "CS_MODE_LITTLE_ENDIAN", + "mipsel-unknown-linux": "CS_MODE_LITTLE_ENDIAN", + "mipsel-unknown-linux-gnu": "CS_MODE_LITTLE_ENDIAN", + "mips16": "CS_MODE_MIPS16", + "mips32": "CS_MODE_MIPS32", + "mips64": "CS_MODE_MIPS64", + "micromips": "CS_MODE_MICRO", + "mips1": "CS_MODE_MIPS1", + "mips2": "CS_MODE_MIPS2", + "mips32r2": "CS_MODE_MIPS32R2", + "mips32r3": "CS_MODE_MIPS32R3", + "mips32r5": "CS_MODE_MIPS32R5", + "mips32r6": "CS_MODE_MIPS32R6", + "mips3": "CS_MODE_MIPS3", + "mips4": "CS_MODE_MIPS4", + "mips5": "CS_MODE_MIPS5", + "mips64r2": "CS_MODE_MIPS64R2", + "mips64r3": "CS_MODE_MIPS64R3", + "mips64r5": "CS_MODE_MIPS64R5", + "mips64r6": "CS_MODE_MIPS64R6", + "octeon": "CS_MODE_OCTEON", + "octeon+": "CS_MODE_OCTEONP", + "nanomips": "CS_MODE_NANOMIPS", + "nms1": "CS_MODE_NMS1", + "i7200": "CS_MODE_I7200", + "mips_nofloat": "CS_MODE_MIPS_NOFLOAT", + "mips_ptr64": "CS_MODE_MIPS_PTR64" + } + } +} \ No newline at end of file diff --git a/suite/cstest/include/test_mapping.h b/suite/cstest/include/test_mapping.h index 7ef546b52d..f796840b08 100644 --- a/suite/cstest/include/test_mapping.h +++ b/suite/cstest/include/test_mapping.h @@ -73,6 +73,7 @@ static const cs_enum_id_map test_mode_map[] = { { .str = "CS_MODE_HPPA_11", .val = CS_MODE_HPPA_11 }, { .str = "CS_MODE_HPPA_20", .val = CS_MODE_HPPA_20 }, { .str = "CS_MODE_HPPA_20W", .val = CS_MODE_HPPA_20W }, + { .str = "CS_MODE_I7200", .val = CS_MODE_I7200 }, { .str = "CS_MODE_LITTLE_ENDIAN", .val = CS_MODE_LITTLE_ENDIAN }, { .str = "CS_MODE_LOONGARCH32", .val = CS_MODE_LOONGARCH32 }, { .str = "CS_MODE_LOONGARCH64", .val = CS_MODE_LOONGARCH64 }, @@ -94,11 +95,26 @@ static const cs_enum_id_map test_mode_map[] = { { .str = "CS_MODE_M68K_060", .val = CS_MODE_M68K_060 }, { .str = "CS_MODE_MCLASS", .val = CS_MODE_MCLASS }, { .str = "CS_MODE_MICRO", .val = CS_MODE_MICRO }, + { .str = "CS_MODE_MICRO32R3", .val = CS_MODE_MICRO32R3 }, + { .str = "CS_MODE_MICRO32R6", .val = CS_MODE_MICRO32R6 }, + { .str = "CS_MODE_MIPS1", .val = CS_MODE_MIPS1 }, + { .str = "CS_MODE_MIPS16", .val = CS_MODE_MIPS16 }, { .str = "CS_MODE_MIPS2", .val = CS_MODE_MIPS2 }, { .str = "CS_MODE_MIPS3", .val = CS_MODE_MIPS3 }, { .str = "CS_MODE_MIPS32", .val = CS_MODE_MIPS32 }, + { .str = "CS_MODE_MIPS32R2", .val = CS_MODE_MIPS32R2 }, + { .str = "CS_MODE_MIPS32R3", .val = CS_MODE_MIPS32R3 }, + { .str = "CS_MODE_MIPS32R5", .val = CS_MODE_MIPS32R5 }, { .str = "CS_MODE_MIPS32R6", .val = CS_MODE_MIPS32R6 }, + { .str = "CS_MODE_MIPS4", .val = CS_MODE_MIPS4 }, + { .str = "CS_MODE_MIPS5", .val = CS_MODE_MIPS5 }, { .str = "CS_MODE_MIPS64", .val = CS_MODE_MIPS64 }, + { .str = "CS_MODE_MIPS64R2", .val = CS_MODE_MIPS64R2 }, + { .str = "CS_MODE_MIPS64R3", .val = CS_MODE_MIPS64R3 }, + { .str = "CS_MODE_MIPS64R5", .val = CS_MODE_MIPS64R5 }, + { .str = "CS_MODE_MIPS64R6", .val = CS_MODE_MIPS64R6 }, + { .str = "CS_MODE_MIPS_NOFLOAT", .val = CS_MODE_MIPS_NOFLOAT }, + { .str = "CS_MODE_MIPS_PTR64", .val = CS_MODE_MIPS_PTR64 }, { .str = "CS_MODE_MOS65XX_6502", .val = CS_MODE_MOS65XX_6502 }, { .str = "CS_MODE_MOS65XX_65816", .val = CS_MODE_MOS65XX_65816 }, { .str = "CS_MODE_MOS65XX_65816_LONG_M", @@ -109,6 +125,10 @@ static const cs_enum_id_map test_mode_map[] = { .val = CS_MODE_MOS65XX_65816_LONG_X }, { .str = "CS_MODE_MOS65XX_65C02", .val = CS_MODE_MOS65XX_65C02 }, { .str = "CS_MODE_MOS65XX_W65C02", .val = CS_MODE_MOS65XX_W65C02 }, + { .str = "CS_MODE_NANOMIPS", .val = CS_MODE_NANOMIPS }, + { .str = "CS_MODE_NMS1", .val = CS_MODE_NMS1 }, + { .str = "CS_MODE_OCTEON", .val = CS_MODE_OCTEON }, + { .str = "CS_MODE_OCTEONP", .val = CS_MODE_OCTEONP }, { .str = "CS_MODE_PS", .val = CS_MODE_PS }, { .str = "CS_MODE_QPX", .val = CS_MODE_QPX }, { .str = "CS_MODE_RISCV32", .val = CS_MODE_RISCV32 }, diff --git a/suite/cstest/src/test_run.c b/suite/cstest/src/test_run.c index 36e2b0a593..06919c6c3a 100644 --- a/suite/cstest/src/test_run.c +++ b/suite/cstest/src/test_run.c @@ -102,17 +102,18 @@ static bool parse_input_options(const TestInput *input, cs_arch *arch, } *mode = 0; - bool mode_found = false; size_t opt_idx = 0; char **options = input->options; for (size_t i = 0; i < input->options_count; ++i) { + bool opt_found = false; opt_str = options[i]; val = enum_map_bin_search(test_mode_map, - ARR_SIZE(test_mode_map), opt_str, - &mode_found); - if (mode_found) { + ARR_SIZE(test_mode_map), + opt_str, &opt_found); + + if (opt_found) { *mode |= val; - goto next_option; + continue; } // Might be an option descriptor @@ -126,12 +127,12 @@ static bool parse_input_options(const TestInput *input, cs_arch *arch, return false; } opt_arr[opt_idx++] = test_option_map[k].opt; - goto next_option; + opt_found = true; } } - fprintf(stderr, "[!] Option: '%s' not used\n", opt_str); -next_option: - continue; + if (!opt_found) { + fprintf(stderr, "[!] Option: '%s' not used\n", opt_str); + } } *opt_set = opt_idx; return true; diff --git a/tests/MC/Mips/invalid-xfail.txt.yaml b/tests/MC/Mips/invalid-xfail.txt.yaml new file mode 100644 index 0000000000..39dfbe4424 --- /dev/null +++ b/tests/MC/Mips/invalid-xfail.txt.yaml @@ -0,0 +1,70 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x45, 0x06, 0x00, 0x83 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1fl $fcc1, 528" + + - + input: + bytes: [ 0x45, 0x07, 0xd8, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1tl $fcc1, -40948" + + - + input: + bytes: [ 0x45, 0x08, 0x14, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1f $fcc2, 20496" + + - + input: + bytes: [ 0x45, 0x09, 0x01, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1t $fcc2, 1036" + + - + input: + bytes: [ 0x48, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfc2 $zero, $0, 1" + + - + input: + bytes: [ 0x48, 0x86, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtc2 $6, $0, 4" diff --git a/tests/MC/Mips/invalid.txt.yaml b/tests/MC/Mips/invalid.txt.yaml new file mode 100644 index 0000000000..f2ab6ba782 --- /dev/null +++ b/tests/MC/Mips/invalid.txt.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "nop" diff --git a/tests/MC/Mips/mftr-mttr-aliases.s.yaml b/tests/MC/Mips/mftr-mttr-aliases.s.yaml new file mode 100644 index 0000000000..2b70094018 --- /dev/null +++ b/tests/MC/Mips/mftr-mttr-aliases.s.yaml @@ -0,0 +1,380 @@ +test_cases: + - + input: + bytes: [ 0x41, 0x05, 0x20, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $5, 0, 0, 0" + + - + input: + bytes: [ 0x41, 0x07, 0x30, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $6, $7, 0, 1, 0" + + - + input: + bytes: [ 0x41, 0x09, 0x28, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $5, $9, 1, 0, 0" + + - + input: + bytes: [ 0x41, 0x00, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $zero, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x04, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $4, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x08, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $8, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x0c, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $12, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x01, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $1, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x05, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $5, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x09, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $9, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x0d, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $13, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x02, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $2, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x06, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $6, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x0a, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $10, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x0e, 0x18, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $3, $14, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x10, 0x20, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $16, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x05, 0x20, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $5, 1, 2, 0" + + - + input: + bytes: [ 0x41, 0x05, 0x20, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $5, 1, 2, 1" + + - + input: + bytes: [ 0x41, 0x09, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $9, 1, 3, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x28, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $5, 0, 0, 0" + + - + input: + bytes: [ 0x41, 0x86, 0x38, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $6, $7, 0, 1, 0" + + - + input: + bytes: [ 0x41, 0x85, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $5, $9, 1, 0, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x00, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $zero, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x20, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $4, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x40, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $8, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x60, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $12, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x08, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $1, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x28, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $5, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $9, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x68, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $13, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x10, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $2, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $6, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x50, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $10, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x83, 0x70, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $3, $14, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x80, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $16, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x28, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $5, 1, 2, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x28, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $5, 1, 2, 1" + + - + input: + bytes: [ 0x41, 0x84, 0x48, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $9, 1, 3, 0" diff --git a/tests/MC/Mips/mftr-mttr-reserved-valid.s.yaml b/tests/MC/Mips/mftr-mttr-reserved-valid.s.yaml new file mode 100644 index 0000000000..cc551979cf --- /dev/null +++ b/tests/MC/Mips/mftr-mttr-reserved-valid.s.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x41, 0x1f, 0xf8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $ra, $ra, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x9f, 0xf8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $ra, $ra, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x0d, 0xf8, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $ra, $13, 1, 6, 0" + + - + input: + bytes: [ 0x41, 0x9f, 0x68, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $ra, $13, 1, 6, 0" diff --git a/tests/MC/Mips/micromips-alu-instructions-EB.s.yaml b/tests/MC/Mips/micromips-alu-instructions-EB.s.yaml index 352ff3e9aa..12e38c3096 100644 --- a/tests/MC/Mips/micromips-alu-instructions-EB.s.yaml +++ b/tests/MC/Mips/micromips-alu-instructions-EB.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x00, 0xe6, 0x49, 0x10 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x11, 0x26, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x31, 0x26, 0xc5, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x11, 0x26, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0x31, 0x26, 0xc5, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x00, 0xe6, 0x49, 0x50 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -57,7 +57,7 @@ test_cases: input: bytes: [ 0x00, 0xe6, 0x49, 0x90 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -66,7 +66,7 @@ test_cases: input: bytes: [ 0x00, 0xa3, 0x21, 0xd0 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -75,25 +75,25 @@ test_cases: input: bytes: [ 0x00, 0xe0, 0x31, 0x90 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "sub $a2, $zero, $a3" + asm_text: "neg $a2, $a3" - input: bytes: [ 0x00, 0xe0, 0x31, 0xd0 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "subu $a2, $zero, $a3" + asm_text: "negu $a2, $a3" - input: bytes: [ 0x00, 0x08, 0x39, 0x50 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -102,7 +102,7 @@ test_cases: input: bytes: [ 0x00, 0xa3, 0x1b, 0x50 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -111,7 +111,7 @@ test_cases: input: bytes: [ 0x90, 0x63, 0x00, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -120,7 +120,7 @@ test_cases: input: bytes: [ 0x90, 0x63, 0x00, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -129,7 +129,7 @@ test_cases: input: bytes: [ 0xb0, 0x63, 0x00, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -138,7 +138,7 @@ test_cases: input: bytes: [ 0x00, 0xa3, 0x1b, 0x90 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -147,7 +147,7 @@ test_cases: input: bytes: [ 0x41, 0xa9, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -156,7 +156,7 @@ test_cases: input: bytes: [ 0x00, 0xe6, 0x4a, 0x50 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -165,7 +165,7 @@ test_cases: input: bytes: [ 0xd1, 0x26, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -174,7 +174,7 @@ test_cases: input: bytes: [ 0xd1, 0x26, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -183,7 +183,7 @@ test_cases: input: bytes: [ 0x00, 0xa4, 0x1a, 0x90 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -192,7 +192,7 @@ test_cases: input: bytes: [ 0x51, 0x26, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -201,7 +201,7 @@ test_cases: input: bytes: [ 0x00, 0xa3, 0x1b, 0x10 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -210,7 +210,7 @@ test_cases: input: bytes: [ 0x71, 0x26, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -219,7 +219,7 @@ test_cases: input: bytes: [ 0x71, 0x26, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -228,7 +228,7 @@ test_cases: input: bytes: [ 0x00, 0xe6, 0x4a, 0xd0 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -237,7 +237,7 @@ test_cases: input: bytes: [ 0x00, 0x08, 0x3a, 0xd0 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -246,7 +246,7 @@ test_cases: input: bytes: [ 0x00, 0xe6, 0x4a, 0x10 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -255,7 +255,7 @@ test_cases: input: bytes: [ 0x00, 0xe9, 0x8b, 0x3c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -264,7 +264,7 @@ test_cases: input: bytes: [ 0x00, 0xe9, 0x9b, 0x3c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -273,7 +273,7 @@ test_cases: input: bytes: [ 0x00, 0xe9, 0xab, 0x3c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -282,7 +282,7 @@ test_cases: input: bytes: [ 0x00, 0xe9, 0xbb, 0x3c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - diff --git a/tests/MC/Mips/micromips-alu-instructions.s.yaml b/tests/MC/Mips/micromips-alu-instructions.s.yaml index 116479a58c..7550a57aea 100644 --- a/tests/MC/Mips/micromips-alu-instructions.s.yaml +++ b/tests/MC/Mips/micromips-alu-instructions.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0xe6, 0x00, 0x10, 0x49 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x26, 0x11, 0x67, 0x45 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x26, 0x31, 0x67, 0xc5 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x26, 0x11, 0x67, 0x45 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0x26, 0x31, 0x67, 0xc5 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0xe6, 0x00, 0x50, 0x49 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -57,7 +57,7 @@ test_cases: input: bytes: [ 0xe6, 0x00, 0x90, 0x49 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -66,7 +66,7 @@ test_cases: input: bytes: [ 0xa3, 0x00, 0xd0, 0x21 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -75,25 +75,25 @@ test_cases: input: bytes: [ 0xe0, 0x00, 0x90, 0x31 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "sub $a2, $zero, $a3" + asm_text: "neg $a2, $a3" - input: bytes: [ 0xe0, 0x00, 0xd0, 0x31 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "subu $a2, $zero, $a3" + asm_text: "negu $a2, $a3" - input: bytes: [ 0x08, 0x00, 0x50, 0x39 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -102,7 +102,7 @@ test_cases: input: bytes: [ 0xa3, 0x00, 0x50, 0x1b ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -111,7 +111,7 @@ test_cases: input: bytes: [ 0x63, 0x90, 0x67, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -120,7 +120,7 @@ test_cases: input: bytes: [ 0x63, 0x90, 0x67, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -129,7 +129,7 @@ test_cases: input: bytes: [ 0x63, 0xb0, 0x67, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -138,7 +138,7 @@ test_cases: input: bytes: [ 0xa3, 0x00, 0x90, 0x1b ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -147,7 +147,7 @@ test_cases: input: bytes: [ 0xa9, 0x41, 0x67, 0x45 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -156,7 +156,7 @@ test_cases: input: bytes: [ 0xe6, 0x00, 0x50, 0x4a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -165,7 +165,7 @@ test_cases: input: bytes: [ 0x26, 0xd1, 0x67, 0x45 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -174,7 +174,7 @@ test_cases: input: bytes: [ 0x26, 0xd1, 0x67, 0x45 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -183,7 +183,7 @@ test_cases: input: bytes: [ 0xa4, 0x00, 0x90, 0x1a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -192,7 +192,7 @@ test_cases: input: bytes: [ 0x26, 0x51, 0x67, 0x45 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -201,7 +201,7 @@ test_cases: input: bytes: [ 0xa3, 0x00, 0x10, 0x1b ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -210,7 +210,7 @@ test_cases: input: bytes: [ 0x26, 0x71, 0x67, 0x45 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -219,7 +219,7 @@ test_cases: input: bytes: [ 0x26, 0x71, 0x67, 0x45 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -228,7 +228,7 @@ test_cases: input: bytes: [ 0xe6, 0x00, 0xd0, 0x4a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -237,7 +237,7 @@ test_cases: input: bytes: [ 0x08, 0x00, 0xd0, 0x3a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -246,7 +246,7 @@ test_cases: input: bytes: [ 0xe6, 0x00, 0x10, 0x4a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -255,7 +255,7 @@ test_cases: input: bytes: [ 0xe9, 0x00, 0x3c, 0x8b ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -264,7 +264,7 @@ test_cases: input: bytes: [ 0xe9, 0x00, 0x3c, 0x9b ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -273,7 +273,7 @@ test_cases: input: bytes: [ 0xe9, 0x00, 0x3c, 0xab ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -282,7 +282,7 @@ test_cases: input: bytes: [ 0xe9, 0x00, 0x3c, 0xbb ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ] + options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - diff --git a/tests/MC/Mips/micromips-branch-instructions-EB.s.yaml b/tests/MC/Mips/micromips-branch-instructions-EB.s.yaml index 019ad62292..0fc98c5b26 100644 --- a/tests/MC/Mips/micromips-branch-instructions-EB.s.yaml +++ b/tests/MC/Mips/micromips-branch-instructions-EB.s.yaml @@ -3,80 +3,80 @@ test_cases: input: bytes: [ 0x94, 0x00, 0x02, 0x9a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "b 1332" + asm_text: "b 1336" - input: bytes: [ 0x94, 0xc9, 0x02, 0x9a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "beq $t1, $a2, 1332" + asm_text: "beq $t1, $a2, 1336" - input: bytes: [ 0x40, 0x46, 0x02, 0x9a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "bgez $a2, 1332" + asm_text: "bgez $a2, 1336" - input: bytes: [ 0x40, 0x66, 0x02, 0x9a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "bgezal $a2, 1332" + asm_text: "bgezal $a2, 1336" - input: bytes: [ 0x40, 0x26, 0x02, 0x9a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "bltzal $a2, 1332" + asm_text: "bltzal $a2, 1336" - input: bytes: [ 0x40, 0xc6, 0x02, 0x9a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "bgtz $a2, 1332" + asm_text: "bgtz $a2, 1336" - input: bytes: [ 0x40, 0x86, 0x02, 0x9a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "blez $a2, 1332" + asm_text: "blez $a2, 1336" - input: bytes: [ 0xb4, 0xc9, 0x02, 0x9a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "bne $t1, $a2, 1332" + asm_text: "bne $t1, $a2, 1336" - input: bytes: [ 0x40, 0x06, 0x02, 0x9a ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - - asm_text: "bltz $a2, 1332" + asm_text: "bltz $a2, 1336" diff --git a/tests/MC/Mips/micromips-branch-instructions.s.yaml b/tests/MC/Mips/micromips-branch-instructions.s.yaml index 7da1059436..e117e52835 100644 --- a/tests/MC/Mips/micromips-branch-instructions.s.yaml +++ b/tests/MC/Mips/micromips-branch-instructions.s.yaml @@ -7,7 +7,7 @@ test_cases: expected: insns: - - asm_text: "b 1332" + asm_text: "b 1336" - input: bytes: [ 0xc9, 0x94, 0x9a, 0x02 ] @@ -16,7 +16,7 @@ test_cases: expected: insns: - - asm_text: "beq $t1, $a2, 1332" + asm_text: "beq $t1, $a2, 1336" - input: bytes: [ 0x46, 0x40, 0x9a, 0x02 ] @@ -25,7 +25,7 @@ test_cases: expected: insns: - - asm_text: "bgez $a2, 1332" + asm_text: "bgez $a2, 1336" - input: bytes: [ 0x66, 0x40, 0x9a, 0x02 ] @@ -34,7 +34,7 @@ test_cases: expected: insns: - - asm_text: "bgezal $a2, 1332" + asm_text: "bgezal $a2, 1336" - input: bytes: [ 0x26, 0x40, 0x9a, 0x02 ] @@ -43,7 +43,7 @@ test_cases: expected: insns: - - asm_text: "bltzal $a2, 1332" + asm_text: "bltzal $a2, 1336" - input: bytes: [ 0xc6, 0x40, 0x9a, 0x02 ] @@ -52,7 +52,7 @@ test_cases: expected: insns: - - asm_text: "bgtz $a2, 1332" + asm_text: "bgtz $a2, 1336" - input: bytes: [ 0x86, 0x40, 0x9a, 0x02 ] @@ -61,7 +61,7 @@ test_cases: expected: insns: - - asm_text: "blez $a2, 1332" + asm_text: "blez $a2, 1336" - input: bytes: [ 0xc9, 0xb4, 0x9a, 0x02 ] @@ -70,7 +70,7 @@ test_cases: expected: insns: - - asm_text: "bne $t1, $a2, 1332" + asm_text: "bne $t1, $a2, 1336" - input: bytes: [ 0x06, 0x40, 0x9a, 0x02 ] @@ -79,4 +79,4 @@ test_cases: expected: insns: - - asm_text: "bltz $a2, 1332" + asm_text: "bltz $a2, 1336" diff --git a/tests/MC/Mips/micromips-jump-instructions-EB.s.yaml b/tests/MC/Mips/micromips-jump-instructions-EB.s.yaml index b709a41cc0..0278fcc0bf 100644 --- a/tests/MC/Mips/micromips-jump-instructions-EB.s.yaml +++ b/tests/MC/Mips/micromips-jump-instructions-EB.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0xd4, 0x00, 0x02, 0x98 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0xf4, 0x00, 0x02, 0x98 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x00, 0x07, 0x0f, 0x3c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - diff --git a/tests/MC/Mips/micromips-loadstore-instructions-EB.s.yaml b/tests/MC/Mips/micromips-loadstore-instructions-EB.s.yaml index 2040ea000b..e769af9479 100644 --- a/tests/MC/Mips/micromips-loadstore-instructions-EB.s.yaml +++ b/tests/MC/Mips/micromips-loadstore-instructions-EB.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x1c, 0xa4, 0x00, 0x08 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x14, 0xc4, 0x00, 0x08 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x3c, 0x44, 0x00, 0x08 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x34, 0x82, 0x00, 0x08 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0xfc, 0xc5, 0x00, 0x04 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x18, 0xa4, 0x00, 0x08 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -57,7 +57,7 @@ test_cases: input: bytes: [ 0x38, 0x44, 0x00, 0x08 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -66,7 +66,7 @@ test_cases: input: bytes: [ 0xf8, 0xa6, 0x00, 0x04 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - diff --git a/tests/MC/Mips/micromips-loadstore-unaligned-EB.s.yaml b/tests/MC/Mips/micromips-loadstore-unaligned-EB.s.yaml index 897c1d18db..ca38b1edda 100644 --- a/tests/MC/Mips/micromips-loadstore-unaligned-EB.s.yaml +++ b/tests/MC/Mips/micromips-loadstore-unaligned-EB.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x60, 0x85, 0x00, 0x10 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x60, 0x85, 0x10, 0x10 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x60, 0x85, 0x80, 0x10 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x60, 0x85, 0x90, 0x10 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - diff --git a/tests/MC/Mips/micromips-movcond-instructions-EB.s.yaml b/tests/MC/Mips/micromips-movcond-instructions-EB.s.yaml index 7559e35598..6a0722d01c 100644 --- a/tests/MC/Mips/micromips-movcond-instructions-EB.s.yaml +++ b/tests/MC/Mips/micromips-movcond-instructions-EB.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x00, 0xe6, 0x48, 0x58 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x00, 0xe6, 0x48, 0x18 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x55, 0x26, 0x09, 0x7b ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x55, 0x26, 0x01, 0x7b ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - diff --git a/tests/MC/Mips/micromips-multiply-instructions-EB.s.yaml b/tests/MC/Mips/micromips-multiply-instructions-EB.s.yaml index f5d5e1ebd0..7686b1c012 100644 --- a/tests/MC/Mips/micromips-multiply-instructions-EB.s.yaml +++ b/tests/MC/Mips/micromips-multiply-instructions-EB.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x00, 0xa4, 0xcb, 0x3c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x00, 0xa4, 0xdb, 0x3c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x00, 0xa4, 0xeb, 0x3c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x00, 0xa4, 0xfb, 0x3c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - diff --git a/tests/MC/Mips/micromips-shift-instructions-EB.s.yaml b/tests/MC/Mips/micromips-shift-instructions-EB.s.yaml index c833369cfe..253c046dc7 100644 --- a/tests/MC/Mips/micromips-shift-instructions-EB.s.yaml +++ b/tests/MC/Mips/micromips-shift-instructions-EB.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x00, 0x83, 0x38, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x00, 0x65, 0x10, 0x10 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x00, 0x83, 0x38, 0x80 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x00, 0x65, 0x10, 0x90 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0x00, 0x83, 0x38, 0x40 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x00, 0x65, 0x10, 0x50 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -57,7 +57,7 @@ test_cases: input: bytes: [ 0x01, 0x26, 0x38, 0xc0 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -66,7 +66,7 @@ test_cases: input: bytes: [ 0x00, 0xc7, 0x48, 0xd0 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - diff --git a/tests/MC/Mips/micromips-trap-instructions-EB.s.yaml b/tests/MC/Mips/micromips-trap-instructions-EB.s.yaml index 9f83c760df..3b31c55e3e 100644 --- a/tests/MC/Mips/micromips-trap-instructions-EB.s.yaml +++ b/tests/MC/Mips/micromips-trap-instructions-EB.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x41, 0xc9, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x41, 0x29, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x41, 0x69, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x41, 0x09, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0x41, 0x49, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x41, 0x89, 0x45, 0x67 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ] expected: insns: - diff --git a/tests/MC/Mips/mips-alu-instructions.s.yaml b/tests/MC/Mips/mips-alu-instructions.s.yaml index bf9dbc82c5..37db7bab00 100644 --- a/tests/MC/Mips/mips-alu-instructions.s.yaml +++ b/tests/MC/Mips/mips-alu-instructions.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x24, 0x48, 0xc7, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x30 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x30 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0x29, 0x31 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0x21, 0x30, 0xe6, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x20, 0x30, 0xe6, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -57,7 +57,7 @@ test_cases: input: bytes: [ 0x84, 0x61, 0x33, 0x7d ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -66,7 +66,7 @@ test_cases: input: bytes: [ 0x27, 0x48, 0xc7, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -75,7 +75,7 @@ test_cases: input: bytes: [ 0x25, 0x18, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -84,7 +84,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xa4, 0x34 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -93,7 +93,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x34 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -102,7 +102,7 @@ test_cases: input: bytes: [ 0x80, 0x00, 0x6b, 0x35 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -111,7 +111,7 @@ test_cases: input: bytes: [ 0xc2, 0x49, 0x26, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -120,7 +120,7 @@ test_cases: input: bytes: [ 0x46, 0x48, 0xe6, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -129,7 +129,7 @@ test_cases: input: bytes: [ 0xc0, 0x21, 0x03, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -138,7 +138,7 @@ test_cases: input: bytes: [ 0x04, 0x10, 0xa3, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -147,7 +147,7 @@ test_cases: input: bytes: [ 0x2a, 0x18, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -156,7 +156,7 @@ test_cases: input: bytes: [ 0x67, 0x00, 0x63, 0x28 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -165,7 +165,7 @@ test_cases: input: bytes: [ 0x67, 0x00, 0x63, 0x28 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -174,7 +174,7 @@ test_cases: input: bytes: [ 0x67, 0x00, 0x63, 0x2c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -183,7 +183,7 @@ test_cases: input: bytes: [ 0x2b, 0x18, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -192,7 +192,7 @@ test_cases: input: bytes: [ 0xc3, 0x21, 0x03, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -201,7 +201,7 @@ test_cases: input: bytes: [ 0x07, 0x10, 0xa3, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -210,7 +210,7 @@ test_cases: input: bytes: [ 0xc2, 0x21, 0x03, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -219,7 +219,7 @@ test_cases: input: bytes: [ 0x06, 0x10, 0xa3, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -228,7 +228,7 @@ test_cases: input: bytes: [ 0x26, 0x18, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -237,7 +237,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x38 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -246,7 +246,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x38 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -255,7 +255,7 @@ test_cases: input: bytes: [ 0x0c, 0x00, 0x6b, 0x39 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -264,7 +264,7 @@ test_cases: input: bytes: [ 0xa0, 0x30, 0x07, 0x7c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -273,7 +273,7 @@ test_cases: input: bytes: [ 0x27, 0x38, 0x00, 0x01 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -282,7 +282,7 @@ test_cases: input: bytes: [ 0x20, 0x48, 0xc7, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -291,7 +291,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -300,7 +300,7 @@ test_cases: input: bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -309,7 +309,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -318,7 +318,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0x29, 0x21 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -327,7 +327,7 @@ test_cases: input: bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -336,7 +336,7 @@ test_cases: input: bytes: [ 0x28, 0x00, 0x6b, 0x25 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -345,7 +345,7 @@ test_cases: input: bytes: [ 0x21, 0x48, 0xc7, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -354,7 +354,7 @@ test_cases: input: bytes: [ 0x00, 0x00, 0xc7, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -363,7 +363,7 @@ test_cases: input: bytes: [ 0x01, 0x00, 0xc7, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -372,7 +372,7 @@ test_cases: input: bytes: [ 0x04, 0x00, 0xc7, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -381,7 +381,7 @@ test_cases: input: bytes: [ 0x05, 0x00, 0xc7, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -390,7 +390,7 @@ test_cases: input: bytes: [ 0x18, 0x00, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -399,7 +399,7 @@ test_cases: input: bytes: [ 0x19, 0x00, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -408,7 +408,7 @@ test_cases: input: bytes: [ 0x22, 0x48, 0xc7, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -417,7 +417,7 @@ test_cases: input: bytes: [ 0xc8, 0xff, 0xbd, 0x23 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -426,7 +426,7 @@ test_cases: input: bytes: [ 0x23, 0x20, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -435,7 +435,7 @@ test_cases: input: bytes: [ 0xd8, 0xff, 0xbd, 0x27 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -444,7 +444,7 @@ test_cases: input: bytes: [ 0x22, 0x30, 0x07, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -453,7 +453,7 @@ test_cases: input: bytes: [ 0x23, 0x30, 0x07, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -462,7 +462,7 @@ test_cases: input: bytes: [ 0x21, 0x38, 0x00, 0x01 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - diff --git a/tests/MC/Mips/mips-control-instructions-64.s.yaml b/tests/MC/Mips/mips-control-instructions-64.s.yaml index 4986ca48b1..7980fd7a82 100644 --- a/tests/MC/Mips/mips-control-instructions-64.s.yaml +++ b/tests/MC/Mips/mips-control-instructions-64.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x00, 0x00, 0x00, 0x0d ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x00, 0x07, 0x01, 0x4d ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x00, 0x00, 0x00, 0x0c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x00, 0x0d, 0x15, 0x0c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0x42, 0x00, 0x00, 0x18 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x42, 0x00, 0x00, 0x1f ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -57,7 +57,7 @@ test_cases: input: bytes: [ 0x41, 0x60, 0x60, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -66,7 +66,7 @@ test_cases: input: bytes: [ 0x41, 0x60, 0x60, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -75,7 +75,7 @@ test_cases: input: bytes: [ 0x41, 0x6a, 0x60, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -84,7 +84,7 @@ test_cases: input: bytes: [ 0x41, 0x60, 0x60, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -93,7 +93,7 @@ test_cases: input: bytes: [ 0x41, 0x60, 0x60, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -102,7 +102,7 @@ test_cases: input: bytes: [ 0x41, 0x6a, 0x60, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -111,7 +111,7 @@ test_cases: input: bytes: [ 0x42, 0x00, 0x00, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -120,7 +120,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x34 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -129,7 +129,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x74 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -138,7 +138,7 @@ test_cases: input: bytes: [ 0x04, 0x6c, 0x00, 0x01 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -147,7 +147,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x30 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -156,7 +156,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0xf0 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -165,7 +165,7 @@ test_cases: input: bytes: [ 0x04, 0x68, 0x00, 0x03 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -174,7 +174,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x31 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -183,7 +183,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x01, 0xf1 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -192,7 +192,7 @@ test_cases: input: bytes: [ 0x04, 0x69, 0x00, 0x07 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -201,7 +201,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x32 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -210,7 +210,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x07, 0xf2 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -219,7 +219,7 @@ test_cases: input: bytes: [ 0x04, 0x6a, 0x00, 0x1f ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -228,7 +228,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x33 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -237,7 +237,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x3f, 0xf3 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -246,7 +246,7 @@ test_cases: input: bytes: [ 0x04, 0x6b, 0x00, 0xff ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -255,7 +255,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x36 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -264,7 +264,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0xff, 0xf6 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - @@ -273,7 +273,7 @@ test_cases: input: bytes: [ 0x04, 0x6e, 0x03, 0xff ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] expected: insns: - diff --git a/tests/MC/Mips/mips-control-instructions.s.yaml b/tests/MC/Mips/mips-control-instructions.s.yaml index b526a98334..f6db344048 100644 --- a/tests/MC/Mips/mips-control-instructions.s.yaml +++ b/tests/MC/Mips/mips-control-instructions.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x00, 0x00, 0x00, 0x0d ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x00, 0x07, 0x01, 0x4d ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x00, 0x00, 0x00, 0x0c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x00, 0x0d, 0x15, 0x0c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0x42, 0x00, 0x00, 0x18 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x42, 0x00, 0x00, 0x1f ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -57,7 +57,7 @@ test_cases: input: bytes: [ 0x41, 0x60, 0x60, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -66,7 +66,7 @@ test_cases: input: bytes: [ 0x41, 0x60, 0x60, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -75,7 +75,7 @@ test_cases: input: bytes: [ 0x41, 0x6a, 0x60, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -84,7 +84,7 @@ test_cases: input: bytes: [ 0x41, 0x60, 0x60, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -93,7 +93,7 @@ test_cases: input: bytes: [ 0x41, 0x60, 0x60, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -102,7 +102,7 @@ test_cases: input: bytes: [ 0x41, 0x6a, 0x60, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -111,7 +111,7 @@ test_cases: input: bytes: [ 0x42, 0x00, 0x00, 0x20 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -120,7 +120,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x34 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -129,7 +129,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x74 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -138,7 +138,7 @@ test_cases: input: bytes: [ 0x04, 0x6c, 0x00, 0x01 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -147,7 +147,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x30 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -156,7 +156,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0xf0 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -165,7 +165,7 @@ test_cases: input: bytes: [ 0x04, 0x68, 0x00, 0x03 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -174,7 +174,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x31 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -183,7 +183,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x01, 0xf1 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -192,7 +192,7 @@ test_cases: input: bytes: [ 0x04, 0x69, 0x00, 0x07 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -201,7 +201,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x32 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -210,7 +210,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x07, 0xf2 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -219,7 +219,7 @@ test_cases: input: bytes: [ 0x04, 0x6a, 0x00, 0x1f ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -228,7 +228,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x33 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -237,7 +237,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x3f, 0xf3 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -246,7 +246,7 @@ test_cases: input: bytes: [ 0x04, 0x6b, 0x00, 0xff ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -255,7 +255,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0x00, 0x36 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -264,7 +264,7 @@ test_cases: input: bytes: [ 0x00, 0x03, 0xff, 0xf6 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - @@ -273,7 +273,7 @@ test_cases: input: bytes: [ 0x04, 0x6e, 0x03, 0xff ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS32R5", "CS_MODE_BIG_ENDIAN" ] expected: insns: - diff --git a/tests/MC/Mips/mips-coprocessor-encodings.s.yaml b/tests/MC/Mips/mips-coprocessor-encodings.s.yaml index 805d490ac5..063624f7bc 100644 --- a/tests/MC/Mips/mips-coprocessor-encodings.s.yaml +++ b/tests/MC/Mips/mips-coprocessor-encodings.s.yaml @@ -7,7 +7,7 @@ test_cases: expected: insns: - - asm_text: "dmtc0 $t4, $s0, 2" + asm_text: "dmtc0 $t4, $16, 2" - input: bytes: [ 0x40, 0xac, 0x80, 0x00 ] @@ -16,7 +16,7 @@ test_cases: expected: insns: - - asm_text: "dmtc0 $t4, $s0, 0" + asm_text: "dmtc0 $t4, $16, 0" - input: bytes: [ 0x40, 0x8c, 0x80, 0x02 ] @@ -25,7 +25,7 @@ test_cases: expected: insns: - - asm_text: "mtc0 $t4, $s0, 2" + asm_text: "mtc0 $t4, $16, 2" - input: bytes: [ 0x40, 0x8c, 0x80, 0x00 ] @@ -34,7 +34,7 @@ test_cases: expected: insns: - - asm_text: "mtc0 $t4, $s0, 0" + asm_text: "mtc0 $t4, $16, 0" - input: bytes: [ 0x40, 0x2c, 0x80, 0x02 ] @@ -43,7 +43,7 @@ test_cases: expected: insns: - - asm_text: "dmfc0 $t4, $s0, 2" + asm_text: "dmfc0 $t4, $16, 2" - input: bytes: [ 0x40, 0x2c, 0x80, 0x00 ] @@ -52,7 +52,7 @@ test_cases: expected: insns: - - asm_text: "dmfc0 $t4, $s0, 0" + asm_text: "dmfc0 $t4, $16, 0" - input: bytes: [ 0x40, 0x0c, 0x80, 0x02 ] @@ -61,7 +61,7 @@ test_cases: expected: insns: - - asm_text: "mfc0 $t4, $s0, 2" + asm_text: "mfc0 $t4, $16, 2" - input: bytes: [ 0x40, 0x0c, 0x80, 0x00 ] @@ -70,7 +70,7 @@ test_cases: expected: insns: - - asm_text: "mfc0 $t4, $s0, 0" + asm_text: "mfc0 $t4, $16, 0" - input: bytes: [ 0x48, 0xac, 0x80, 0x02 ] @@ -79,7 +79,7 @@ test_cases: expected: insns: - - asm_text: "dmtc2 $t4, $s0, 2" + asm_text: "dmtc2 $t4, $16, 2" - input: bytes: [ 0x48, 0xac, 0x80, 0x00 ] @@ -88,7 +88,7 @@ test_cases: expected: insns: - - asm_text: "dmtc2 $t4, $s0, 0" + asm_text: "dmtc2 $t4, $16, 0" - input: bytes: [ 0x48, 0x8c, 0x80, 0x02 ] @@ -97,7 +97,7 @@ test_cases: expected: insns: - - asm_text: "mtc2 $t4, $s0, 2" + asm_text: "mtc2 $t4, $16, 2" - input: bytes: [ 0x48, 0x8c, 0x80, 0x00 ] @@ -106,7 +106,7 @@ test_cases: expected: insns: - - asm_text: "mtc2 $t4, $s0, 0" + asm_text: "mtc2 $t4, $16, 0" - input: bytes: [ 0x48, 0x2c, 0x80, 0x02 ] @@ -115,7 +115,7 @@ test_cases: expected: insns: - - asm_text: "dmfc2 $t4, $s0, 2" + asm_text: "dmfc2 $t4, $16, 2" - input: bytes: [ 0x48, 0x2c, 0x80, 0x00 ] @@ -124,7 +124,7 @@ test_cases: expected: insns: - - asm_text: "dmfc2 $t4, $s0, 0" + asm_text: "dmfc2 $t4, $16, 0" - input: bytes: [ 0x48, 0x0c, 0x80, 0x02 ] @@ -133,7 +133,7 @@ test_cases: expected: insns: - - asm_text: "mfc2 $t4, $s0, 2" + asm_text: "mfc2 $t4, $16, 2" - input: bytes: [ 0x48, 0x0c, 0x80, 0x00 ] @@ -142,4 +142,4 @@ test_cases: expected: insns: - - asm_text: "mfc2 $t4, $s0, 0" + asm_text: "mfc2 $t4, $16, 0" diff --git a/tests/MC/Mips/mips-fpu-instructions.s.yaml b/tests/MC/Mips/mips-fpu-instructions.s.yaml index 0ff331ea6f..d17192562e 100644 --- a/tests/MC/Mips/mips-fpu-instructions.s.yaml +++ b/tests/MC/Mips/mips-fpu-instructions.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x05, 0x73, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x85, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x00, 0x62, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x40, 0x32, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0x0f, 0x73, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x8f, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -57,7 +57,7 @@ test_cases: input: bytes: [ 0x0e, 0x73, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -66,7 +66,7 @@ test_cases: input: bytes: [ 0x8e, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -75,7 +75,7 @@ test_cases: input: bytes: [ 0x02, 0x62, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -84,7 +84,7 @@ test_cases: input: bytes: [ 0x42, 0x32, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -93,7 +93,7 @@ test_cases: input: bytes: [ 0x07, 0x73, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -102,7 +102,7 @@ test_cases: input: bytes: [ 0x87, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -111,7 +111,7 @@ test_cases: input: bytes: [ 0x0c, 0x73, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -120,7 +120,7 @@ test_cases: input: bytes: [ 0x8c, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -129,7 +129,7 @@ test_cases: input: bytes: [ 0x04, 0x73, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -138,7 +138,7 @@ test_cases: input: bytes: [ 0x84, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -147,7 +147,7 @@ test_cases: input: bytes: [ 0x01, 0x62, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -156,7 +156,7 @@ test_cases: input: bytes: [ 0x41, 0x32, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -165,7 +165,7 @@ test_cases: input: bytes: [ 0x0d, 0x73, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -174,7 +174,7 @@ test_cases: input: bytes: [ 0x8d, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -183,7 +183,7 @@ test_cases: input: bytes: [ 0x32, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -192,7 +192,7 @@ test_cases: input: bytes: [ 0x32, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -201,7 +201,7 @@ test_cases: input: bytes: [ 0x30, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -210,7 +210,7 @@ test_cases: input: bytes: [ 0x30, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -219,7 +219,7 @@ test_cases: input: bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -228,7 +228,7 @@ test_cases: input: bytes: [ 0x3e, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -237,7 +237,7 @@ test_cases: input: bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -246,7 +246,7 @@ test_cases: input: bytes: [ 0x3c, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -255,7 +255,7 @@ test_cases: input: bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -264,7 +264,7 @@ test_cases: input: bytes: [ 0x3d, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -273,7 +273,7 @@ test_cases: input: bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -282,7 +282,7 @@ test_cases: input: bytes: [ 0x3b, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -291,7 +291,7 @@ test_cases: input: bytes: [ 0x39, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -300,7 +300,7 @@ test_cases: input: bytes: [ 0x39, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -309,7 +309,7 @@ test_cases: input: bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -318,7 +318,7 @@ test_cases: input: bytes: [ 0x3f, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -327,7 +327,7 @@ test_cases: input: bytes: [ 0x36, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -336,7 +336,7 @@ test_cases: input: bytes: [ 0x36, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -345,7 +345,7 @@ test_cases: input: bytes: [ 0x34, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -354,7 +354,7 @@ test_cases: input: bytes: [ 0x34, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -363,7 +363,7 @@ test_cases: input: bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -372,7 +372,7 @@ test_cases: input: bytes: [ 0x3a, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -381,7 +381,7 @@ test_cases: input: bytes: [ 0x38, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -390,7 +390,7 @@ test_cases: input: bytes: [ 0x38, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -399,7 +399,7 @@ test_cases: input: bytes: [ 0x33, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -408,7 +408,7 @@ test_cases: input: bytes: [ 0x33, 0xe0, 0x12, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -417,7 +417,7 @@ test_cases: input: bytes: [ 0x37, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -426,7 +426,7 @@ test_cases: input: bytes: [ 0x37, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -435,7 +435,7 @@ test_cases: input: bytes: [ 0x35, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -444,7 +444,7 @@ test_cases: input: bytes: [ 0x35, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -453,7 +453,7 @@ test_cases: input: bytes: [ 0x31, 0x60, 0x2e, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -462,7 +462,7 @@ test_cases: input: bytes: [ 0x31, 0x30, 0x07, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -471,7 +471,7 @@ test_cases: input: bytes: [ 0xa1, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -480,7 +480,7 @@ test_cases: input: bytes: [ 0x21, 0x73, 0x80, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -489,7 +489,7 @@ test_cases: input: bytes: [ 0x20, 0x73, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -498,7 +498,7 @@ test_cases: input: bytes: [ 0xa0, 0x39, 0x80, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -507,7 +507,7 @@ test_cases: input: bytes: [ 0x24, 0x73, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -516,7 +516,7 @@ test_cases: input: bytes: [ 0xa4, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -525,7 +525,7 @@ test_cases: input: bytes: [ 0x00, 0x00, 0x46, 0x44 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -534,7 +534,7 @@ test_cases: input: bytes: [ 0x00, 0xf8, 0xca, 0x44 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -543,7 +543,7 @@ test_cases: input: bytes: [ 0x00, 0x38, 0x06, 0x44 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -552,7 +552,7 @@ test_cases: input: bytes: [ 0x10, 0x28, 0x00, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -561,7 +561,7 @@ test_cases: input: bytes: [ 0x12, 0x28, 0x00, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -570,7 +570,7 @@ test_cases: input: bytes: [ 0x86, 0x41, 0x20, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -579,7 +579,7 @@ test_cases: input: bytes: [ 0x86, 0x39, 0x00, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -588,7 +588,7 @@ test_cases: input: bytes: [ 0x00, 0x38, 0x86, 0x44 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -597,7 +597,7 @@ test_cases: input: bytes: [ 0x11, 0x00, 0xe0, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -606,7 +606,7 @@ test_cases: input: bytes: [ 0x13, 0x00, 0xe0, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -615,7 +615,7 @@ test_cases: input: bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -624,79 +624,79 @@ test_cases: input: bytes: [ 0x00, 0x38, 0x06, 0x40 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - - asm_text: "mfc0 $a2, $a3, 0" + asm_text: "mfc0 $a2, $7, 0" - input: bytes: [ 0x00, 0x40, 0x89, 0x40 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - - asm_text: "mtc0 $t1, $t0, 0" + asm_text: "mtc0 $t1, $8, 0" - input: bytes: [ 0x00, 0x38, 0x05, 0x48 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - - asm_text: "mfc2 $a1, $a3, 0" + asm_text: "mfc2 $a1, $7, 0" - input: bytes: [ 0x00, 0x20, 0x89, 0x48 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - - asm_text: "mtc2 $t1, $a0, 0" + asm_text: "mtc2 $t1, $4, 0" - input: bytes: [ 0x02, 0x38, 0x06, 0x40 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - - asm_text: "mfc0 $a2, $a3, 2" + asm_text: "mfc0 $a2, $7, 2" - input: bytes: [ 0x03, 0x40, 0x89, 0x40 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - - asm_text: "mtc0 $t1, $t0, 3" + asm_text: "mtc0 $t1, $8, 3" - input: bytes: [ 0x04, 0x38, 0x05, 0x48 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - - asm_text: "mfc2 $a1, $a3, 4" + asm_text: "mfc2 $a1, $7, 4" - input: bytes: [ 0x05, 0x20, 0x89, 0x48 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - - asm_text: "mtc2 $t1, $a0, 5" + asm_text: "mtc2 $t1, $4, 5" - input: bytes: [ 0x01, 0x10, 0x20, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -705,7 +705,7 @@ test_cases: input: bytes: [ 0x01, 0x10, 0x21, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -714,7 +714,7 @@ test_cases: input: bytes: [ 0x01, 0x20, 0xb1, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -723,7 +723,7 @@ test_cases: input: bytes: [ 0x11, 0x31, 0x28, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -732,7 +732,7 @@ test_cases: input: bytes: [ 0x11, 0x31, 0x14, 0x46 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -741,7 +741,7 @@ test_cases: input: bytes: [ 0x05, 0x00, 0xa6, 0x4c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -750,7 +750,7 @@ test_cases: input: bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -759,7 +759,7 @@ test_cases: input: bytes: [ 0x00, 0x05, 0xcc, 0x4d ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -768,7 +768,7 @@ test_cases: input: bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -777,7 +777,7 @@ test_cases: input: bytes: [ 0x00, 0x20, 0x71, 0x44 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -786,7 +786,7 @@ test_cases: input: bytes: [ 0x00, 0x30, 0xf1, 0x44 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -795,7 +795,7 @@ test_cases: input: bytes: [ 0x10, 0x00, 0xa4, 0xeb ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -804,7 +804,7 @@ test_cases: input: bytes: [ 0x10, 0x00, 0xa4, 0xfb ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -813,7 +813,7 @@ test_cases: input: bytes: [ 0x0c, 0x00, 0xeb, 0xcb ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - @@ -822,7 +822,7 @@ test_cases: input: bytes: [ 0x0c, 0x00, 0xeb, 0xdb ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32" ] + options: [ "CS_MODE_MIPS32R5" ] expected: insns: - diff --git a/tests/MC/Mips/mips-memory-instructions.s.yaml b/tests/MC/Mips/mips-memory-instructions.s.yaml index ab3997e12b..d78335b66d 100644 --- a/tests/MC/Mips/mips-memory-instructions.s.yaml +++ b/tests/MC/Mips/mips-memory-instructions.s.yaml @@ -43,7 +43,7 @@ test_cases: expected: insns: - - asm_text: "sw $a3, ($a1)" + asm_text: "sw $a3, 0($a1)" - input: bytes: [ 0x10, 0x00, 0xa2, 0xe4 ] @@ -133,7 +133,7 @@ test_cases: expected: insns: - - asm_text: "lw $a3, ($a3)" + asm_text: "lw $a3, 0($a3)" - input: bytes: [ 0x10, 0x00, 0xa2, 0x8f ] diff --git a/tests/MC/Mips/mips64-alu-instructions.s.yaml b/tests/MC/Mips/mips64-alu-instructions.s.yaml index 258f568304..2ff180dae4 100644 --- a/tests/MC/Mips/mips64-alu-instructions.s.yaml +++ b/tests/MC/Mips/mips64-alu-instructions.s.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x24, 0x48, 0xc7, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -12,7 +12,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x30 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -21,7 +21,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x30 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -30,7 +30,7 @@ test_cases: input: bytes: [ 0x21, 0x30, 0xe6, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -39,7 +39,7 @@ test_cases: input: bytes: [ 0x20, 0x30, 0xe6, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x84, 0x61, 0x33, 0x7d ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -57,7 +57,7 @@ test_cases: input: bytes: [ 0x27, 0x48, 0xc7, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -66,7 +66,7 @@ test_cases: input: bytes: [ 0x25, 0x18, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -75,7 +75,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xa4, 0x34 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -84,7 +84,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x34 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -93,7 +93,7 @@ test_cases: input: bytes: [ 0xc2, 0x49, 0x26, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -102,7 +102,7 @@ test_cases: input: bytes: [ 0x46, 0x48, 0xe6, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -111,7 +111,7 @@ test_cases: input: bytes: [ 0xc0, 0x21, 0x03, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -120,7 +120,7 @@ test_cases: input: bytes: [ 0x04, 0x10, 0xa3, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -129,7 +129,7 @@ test_cases: input: bytes: [ 0x2a, 0x18, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -138,7 +138,7 @@ test_cases: input: bytes: [ 0x67, 0x00, 0x63, 0x28 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -147,7 +147,7 @@ test_cases: input: bytes: [ 0x67, 0x00, 0x63, 0x28 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -156,7 +156,7 @@ test_cases: input: bytes: [ 0x67, 0x00, 0x63, 0x2c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -165,7 +165,7 @@ test_cases: input: bytes: [ 0x2b, 0x18, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -174,7 +174,7 @@ test_cases: input: bytes: [ 0xc3, 0x21, 0x03, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -183,7 +183,7 @@ test_cases: input: bytes: [ 0x07, 0x10, 0xa3, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -192,7 +192,7 @@ test_cases: input: bytes: [ 0xc2, 0x21, 0x03, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -201,7 +201,7 @@ test_cases: input: bytes: [ 0x06, 0x10, 0xa3, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -210,7 +210,7 @@ test_cases: input: bytes: [ 0x26, 0x18, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -219,7 +219,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x38 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -228,7 +228,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x38 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -237,7 +237,7 @@ test_cases: input: bytes: [ 0xa0, 0x30, 0x07, 0x7c ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -246,7 +246,7 @@ test_cases: input: bytes: [ 0x27, 0x38, 0x00, 0x01 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -255,7 +255,7 @@ test_cases: input: bytes: [ 0x2c, 0x48, 0xc7, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -264,7 +264,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x60 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -273,7 +273,7 @@ test_cases: input: bytes: [ 0x67, 0xc5, 0xc9, 0x64 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -282,7 +282,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0xc9, 0x60 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -291,7 +291,7 @@ test_cases: input: bytes: [ 0x67, 0x45, 0x29, 0x61 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -300,7 +300,7 @@ test_cases: input: bytes: [ 0x67, 0xc5, 0xc9, 0x64 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -309,7 +309,7 @@ test_cases: input: bytes: [ 0x67, 0xc5, 0x29, 0x65 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -318,7 +318,7 @@ test_cases: input: bytes: [ 0x2d, 0x48, 0xc7, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -327,7 +327,7 @@ test_cases: input: bytes: [ 0x3a, 0x4d, 0x26, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -336,7 +336,7 @@ test_cases: input: bytes: [ 0x00, 0x00, 0xc7, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -345,7 +345,7 @@ test_cases: input: bytes: [ 0x01, 0x00, 0xc7, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -354,7 +354,7 @@ test_cases: input: bytes: [ 0x04, 0x00, 0xc7, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -363,7 +363,7 @@ test_cases: input: bytes: [ 0x05, 0x00, 0xc7, 0x70 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -372,7 +372,7 @@ test_cases: input: bytes: [ 0x18, 0x00, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -381,7 +381,7 @@ test_cases: input: bytes: [ 0x19, 0x00, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -390,7 +390,7 @@ test_cases: input: bytes: [ 0x2f, 0x20, 0x65, 0x00 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - @@ -399,7 +399,7 @@ test_cases: input: bytes: [ 0x2d, 0x38, 0x00, 0x01 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS64" ] + options: [ "CS_MODE_MIPS64R5" ] expected: insns: - diff --git a/tests/MC/Mips/test_2r.txt.yaml b/tests/MC/Mips/test_2r.txt.yaml new file mode 100644 index 0000000000..de3aa2bc1e --- /dev/null +++ b/tests/MC/Mips/test_2r.txt.yaml @@ -0,0 +1,150 @@ +test_cases: + - + input: + bytes: [ 0x7b, 0x00, 0x4f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fill.b $w30, $9" + + - + input: + bytes: [ 0x7b, 0x01, 0xbf, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fill.h $w31, $23" + + - + input: + bytes: [ 0x7b, 0x02, 0xc4, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fill.w $w16, $24" + + - + input: + bytes: [ 0x7b, 0x08, 0x05, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nloc.b $w21, $w0" + + - + input: + bytes: [ 0x7b, 0x09, 0xfc, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nloc.h $w18, $w31" + + - + input: + bytes: [ 0x7b, 0x0a, 0xb8, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nloc.w $w2, $w23" + + - + input: + bytes: [ 0x7b, 0x0b, 0x51, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nloc.d $w4, $w10" + + - + input: + bytes: [ 0x7b, 0x0c, 0x17, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nlzc.b $w31, $w2" + + - + input: + bytes: [ 0x7b, 0x0d, 0xb6, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nlzc.h $w27, $w22" + + - + input: + bytes: [ 0x7b, 0x0e, 0xea, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nlzc.w $w10, $w29" + + - + input: + bytes: [ 0x7b, 0x0f, 0x4e, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nlzc.d $w25, $w9" + + - + input: + bytes: [ 0x7b, 0x04, 0x95, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pcnt.b $w20, $w18" + + - + input: + bytes: [ 0x7b, 0x05, 0x40, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pcnt.h $w0, $w8" + + - + input: + bytes: [ 0x7b, 0x06, 0x4d, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pcnt.w $w23, $w9" + + - + input: + bytes: [ 0x7b, 0x07, 0xc5, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pcnt.d $w21, $w24" diff --git a/tests/MC/Mips/test_2r_msa64.txt.yaml b/tests/MC/Mips/test_2r_msa64.txt.yaml new file mode 100644 index 0000000000..b9deacfcd2 --- /dev/null +++ b/tests/MC/Mips/test_2r_msa64.txt.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x7b, 0x03, 0x4e, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "fill.d $w27, $9" diff --git a/tests/MC/Mips/test_2rf.txt.yaml b/tests/MC/Mips/test_2rf.txt.yaml new file mode 100644 index 0000000000..ae7476fc1f --- /dev/null +++ b/tests/MC/Mips/test_2rf.txt.yaml @@ -0,0 +1,320 @@ +test_cases: + - + input: + bytes: [ 0x7b, 0x20, 0x66, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fclass.w $w26, $w12" + + - + input: + bytes: [ 0x7b, 0x21, 0x8e, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fclass.d $w24, $w17" + + - + input: + bytes: [ 0x7b, 0x30, 0x02, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fexupl.w $w8, $w0" + + - + input: + bytes: [ 0x7b, 0x31, 0xec, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fexupl.d $w17, $w29" + + - + input: + bytes: [ 0x7b, 0x32, 0x23, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fexupr.w $w13, $w4" + + - + input: + bytes: [ 0x7b, 0x33, 0x11, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fexupr.d $w5, $w2" + + - + input: + bytes: [ 0x7b, 0x3c, 0xed, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ffint_s.w $w20, $w29" + + - + input: + bytes: [ 0x7b, 0x3d, 0x7b, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ffint_s.d $w12, $w15" + + - + input: + bytes: [ 0x7b, 0x3e, 0xd9, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ffint_u.w $w7, $w27" + + - + input: + bytes: [ 0x7b, 0x3f, 0x84, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ffint_u.d $w19, $w16" + + - + input: + bytes: [ 0x7b, 0x34, 0x6f, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ffql.w $w31, $w13" + + - + input: + bytes: [ 0x7b, 0x35, 0x6b, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ffql.d $w12, $w13" + + - + input: + bytes: [ 0x7b, 0x36, 0xf6, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ffqr.w $w27, $w30" + + - + input: + bytes: [ 0x7b, 0x37, 0x7f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ffqr.d $w30, $w15" + + - + input: + bytes: [ 0x7b, 0x2e, 0xfe, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "flog2.w $w25, $w31" + + - + input: + bytes: [ 0x7b, 0x2f, 0x54, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "flog2.d $w18, $w10" + + - + input: + bytes: [ 0x7b, 0x2c, 0x79, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "frint.w $w7, $w15" + + - + input: + bytes: [ 0x7b, 0x2d, 0xb5, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "frint.d $w21, $w22" + + - + input: + bytes: [ 0x7b, 0x2a, 0x04, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "frcp.w $w19, $w0" + + - + input: + bytes: [ 0x7b, 0x2b, 0x71, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "frcp.d $w4, $w14" + + - + input: + bytes: [ 0x7b, 0x28, 0x8b, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "frsqrt.w $w12, $w17" + + - + input: + bytes: [ 0x7b, 0x29, 0x5d, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "frsqrt.d $w23, $w11" + + - + input: + bytes: [ 0x7b, 0x26, 0x58, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsqrt.w $w0, $w11" + + - + input: + bytes: [ 0x7b, 0x27, 0x63, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsqrt.d $w15, $w12" + + - + input: + bytes: [ 0x7b, 0x38, 0x2f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftint_s.w $w30, $w5" + + - + input: + bytes: [ 0x7b, 0x39, 0xb9, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftint_s.d $w5, $w23" + + - + input: + bytes: [ 0x7b, 0x3a, 0x75, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftint_u.w $w20, $w14" + + - + input: + bytes: [ 0x7b, 0x3b, 0xad, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftint_u.d $w23, $w21" + + - + input: + bytes: [ 0x7b, 0x22, 0x8f, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftrunc_s.w $w29, $w17" + + - + input: + bytes: [ 0x7b, 0x23, 0xdb, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftrunc_s.d $w12, $w27" + + - + input: + bytes: [ 0x7b, 0x24, 0x7c, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftrunc_u.w $w17, $w15" + + - + input: + bytes: [ 0x7b, 0x25, 0xd9, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftrunc_u.d $w5, $w27" diff --git a/tests/MC/Mips/test_3r.txt.yaml b/tests/MC/Mips/test_3r.txt.yaml new file mode 100644 index 0000000000..22bee80691 --- /dev/null +++ b/tests/MC/Mips/test_3r.txt.yaml @@ -0,0 +1,2420 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x04, 0x4e, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add_a.b $w26, $w9, $w4" + + - + input: + bytes: [ 0x78, 0x3f, 0xdd, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add_a.h $w23, $w27, $w31" + + - + input: + bytes: [ 0x78, 0x56, 0x32, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add_a.w $w11, $w6, $w22" + + - + input: + bytes: [ 0x78, 0x60, 0x51, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add_a.d $w6, $w10, $w0" + + - + input: + bytes: [ 0x78, 0x93, 0xc4, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_a.b $w19, $w24, $w19" + + - + input: + bytes: [ 0x78, 0xa4, 0x36, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_a.h $w25, $w6, $w4" + + - + input: + bytes: [ 0x78, 0xdb, 0x8e, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_a.w $w25, $w17, $w27" + + - + input: + bytes: [ 0x78, 0xfa, 0x93, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_a.d $w15, $w18, $w26" + + - + input: + bytes: [ 0x79, 0x13, 0x5f, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_s.b $w29, $w11, $w19" + + - + input: + bytes: [ 0x79, 0x3a, 0xb9, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_s.h $w5, $w23, $w26" + + - + input: + bytes: [ 0x79, 0x4d, 0x74, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_s.w $w16, $w14, $w13" + + - + input: + bytes: [ 0x79, 0x7c, 0x70, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_s.d $w2, $w14, $w28" + + - + input: + bytes: [ 0x79, 0x8e, 0x88, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_u.b $w3, $w17, $w14" + + - + input: + bytes: [ 0x79, 0xa4, 0xf2, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_u.h $w10, $w30, $w4" + + - + input: + bytes: [ 0x79, 0xd4, 0x93, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_u.w $w15, $w18, $w20" + + - + input: + bytes: [ 0x79, 0xe9, 0x57, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "adds_u.d $w30, $w10, $w9" + + - + input: + bytes: [ 0x78, 0x15, 0xa6, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addv.b $w24, $w20, $w21" + + - + input: + bytes: [ 0x78, 0x3b, 0x69, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addv.h $w4, $w13, $w27" + + - + input: + bytes: [ 0x78, 0x4e, 0x5c, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addv.w $w19, $w11, $w14" + + - + input: + bytes: [ 0x78, 0x7f, 0xa8, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addv.d $w2, $w21, $w31" + + - + input: + bytes: [ 0x7a, 0x03, 0x85, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "asub_s.b $w23, $w16, $w3" + + - + input: + bytes: [ 0x7a, 0x39, 0x8d, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "asub_s.h $w22, $w17, $w25" + + - + input: + bytes: [ 0x7a, 0x49, 0x0e, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "asub_s.w $w24, $w1, $w9" + + - + input: + bytes: [ 0x7a, 0x6c, 0x63, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "asub_s.d $w13, $w12, $w12" + + - + input: + bytes: [ 0x7a, 0x8b, 0xea, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "asub_u.b $w10, $w29, $w11" + + - + input: + bytes: [ 0x7a, 0xaf, 0x4c, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "asub_u.h $w18, $w9, $w15" + + - + input: + bytes: [ 0x7a, 0xdf, 0x9a, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "asub_u.w $w10, $w19, $w31" + + - + input: + bytes: [ 0x7a, 0xe0, 0x54, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "asub_u.d $w17, $w10, $w0" + + - + input: + bytes: [ 0x7a, 0x01, 0x28, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ave_s.b $w2, $w5, $w1" + + - + input: + bytes: [ 0x7a, 0x29, 0x9c, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ave_s.h $w16, $w19, $w9" + + - + input: + bytes: [ 0x7a, 0x45, 0xfc, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ave_s.w $w17, $w31, $w5" + + - + input: + bytes: [ 0x7a, 0x6a, 0xce, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ave_s.d $w27, $w25, $w10" + + - + input: + bytes: [ 0x7a, 0x89, 0x9c, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ave_u.b $w16, $w19, $w9" + + - + input: + bytes: [ 0x7a, 0xab, 0xe7, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ave_u.h $w28, $w28, $w11" + + - + input: + bytes: [ 0x7a, 0xcb, 0x62, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ave_u.w $w11, $w12, $w11" + + - + input: + bytes: [ 0x7a, 0xfc, 0x9f, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ave_u.d $w30, $w19, $w28" + + - + input: + bytes: [ 0x7b, 0x02, 0x86, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "aver_s.b $w26, $w16, $w2" + + - + input: + bytes: [ 0x7b, 0x3b, 0xdf, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "aver_s.h $w31, $w27, $w27" + + - + input: + bytes: [ 0x7b, 0x59, 0x97, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "aver_s.w $w28, $w18, $w25" + + - + input: + bytes: [ 0x7b, 0x7b, 0xaf, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "aver_s.d $w29, $w21, $w27" + + - + input: + bytes: [ 0x7b, 0x83, 0xd7, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "aver_u.b $w29, $w26, $w3" + + - + input: + bytes: [ 0x7b, 0xa9, 0x94, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "aver_u.h $w18, $w18, $w9" + + - + input: + bytes: [ 0x7b, 0xdd, 0xcc, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "aver_u.w $w17, $w25, $w29" + + - + input: + bytes: [ 0x7b, 0xf3, 0xb5, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "aver_u.d $w22, $w22, $w19" + + - + input: + bytes: [ 0x79, 0x9d, 0x78, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bclr.b $w2, $w15, $w29" + + - + input: + bytes: [ 0x79, 0xbc, 0xac, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bclr.h $w16, $w21, $w28" + + - + input: + bytes: [ 0x79, 0xc9, 0x14, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bclr.w $w19, $w2, $w9" + + - + input: + bytes: [ 0x79, 0xe4, 0xfe, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bclr.d $w27, $w31, $w4" + + - + input: + bytes: [ 0x7b, 0x18, 0x81, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsl.b $w5, $w16, $w24" + + - + input: + bytes: [ 0x7b, 0x2a, 0x2f, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsl.h $w30, $w5, $w10" + + - + input: + bytes: [ 0x7b, 0x4d, 0x7b, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsl.w $w14, $w15, $w13" + + - + input: + bytes: [ 0x7b, 0x6c, 0xa5, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsl.d $w23, $w20, $w12" + + - + input: + bytes: [ 0x7b, 0x82, 0x5d, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsr.b $w22, $w11, $w2" + + - + input: + bytes: [ 0x7b, 0xa6, 0xd0, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsr.h $w0, $w26, $w6" + + - + input: + bytes: [ 0x7b, 0xdc, 0x1e, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsr.w $w26, $w3, $w28" + + - + input: + bytes: [ 0x7b, 0xf5, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsr.d $w0, $w0, $w21" + + - + input: + bytes: [ 0x7a, 0x98, 0x58, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bneg.b $w0, $w11, $w24" + + - + input: + bytes: [ 0x7a, 0xa4, 0x87, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bneg.h $w28, $w16, $w4" + + - + input: + bytes: [ 0x7a, 0xd3, 0xd0, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bneg.w $w3, $w26, $w19" + + - + input: + bytes: [ 0x7a, 0xef, 0xeb, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bneg.d $w13, $w29, $w15" + + - + input: + bytes: [ 0x7a, 0x1f, 0x2f, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bset.b $w31, $w5, $w31" + + - + input: + bytes: [ 0x7a, 0x26, 0x63, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bset.h $w14, $w12, $w6" + + - + input: + bytes: [ 0x7a, 0x4c, 0x4f, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bset.w $w31, $w9, $w12" + + - + input: + bytes: [ 0x7a, 0x65, 0xb1, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bset.d $w5, $w22, $w5" + + - + input: + bytes: [ 0x78, 0x12, 0xff, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceq.b $w31, $w31, $w18" + + - + input: + bytes: [ 0x78, 0x29, 0xda, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceq.h $w10, $w27, $w9" + + - + input: + bytes: [ 0x78, 0x4e, 0x2a, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceq.w $w9, $w5, $w14" + + - + input: + bytes: [ 0x78, 0x60, 0x89, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceq.d $w5, $w17, $w0" + + - + input: + bytes: [ 0x7a, 0x09, 0x25, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cle_s.b $w23, $w4, $w9" + + - + input: + bytes: [ 0x7a, 0x33, 0xdd, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cle_s.h $w22, $w27, $w19" + + - + input: + bytes: [ 0x7a, 0x4a, 0xd7, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cle_s.w $w30, $w26, $w10" + + - + input: + bytes: [ 0x7a, 0x6a, 0x2c, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cle_s.d $w18, $w5, $w10" + + - + input: + bytes: [ 0x7a, 0x80, 0xc8, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cle_u.b $w1, $w25, $w0" + + - + input: + bytes: [ 0x7a, 0xbd, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cle_u.h $w7, $w0, $w29" + + - + input: + bytes: [ 0x7a, 0xc1, 0x96, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cle_u.w $w25, $w18, $w1" + + - + input: + bytes: [ 0x7a, 0xfe, 0x01, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cle_u.d $w6, $w0, $w30" + + - + input: + bytes: [ 0x79, 0x15, 0x16, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clt_s.b $w25, $w2, $w21" + + - + input: + bytes: [ 0x79, 0x29, 0x98, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clt_s.h $w2, $w19, $w9" + + - + input: + bytes: [ 0x79, 0x50, 0x45, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clt_s.w $w23, $w8, $w16" + + - + input: + bytes: [ 0x79, 0x6c, 0xf1, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clt_s.d $w7, $w30, $w12" + + - + input: + bytes: [ 0x79, 0x8d, 0xf8, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clt_u.b $w2, $w31, $w13" + + - + input: + bytes: [ 0x79, 0xb7, 0xfc, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clt_u.h $w16, $w31, $w23" + + - + input: + bytes: [ 0x79, 0xc9, 0xc0, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clt_u.w $w3, $w24, $w9" + + - + input: + bytes: [ 0x79, 0xe1, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clt_u.d $w7, $w0, $w1" + + - + input: + bytes: [ 0x7a, 0x12, 0x1f, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div_s.b $w29, $w3, $w18" + + - + input: + bytes: [ 0x7a, 0x2d, 0x84, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div_s.h $w17, $w16, $w13" + + - + input: + bytes: [ 0x7a, 0x5e, 0xc9, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div_s.w $w4, $w25, $w30" + + - + input: + bytes: [ 0x7a, 0x74, 0x4f, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div_s.d $w31, $w9, $w20" + + - + input: + bytes: [ 0x7a, 0x8a, 0xe9, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div_u.b $w6, $w29, $w10" + + - + input: + bytes: [ 0x7a, 0xae, 0xae, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div_u.h $w24, $w21, $w14" + + - + input: + bytes: [ 0x7a, 0xd9, 0x77, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div_u.w $w29, $w14, $w25" + + - + input: + bytes: [ 0x7a, 0xf5, 0x0f, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div_u.d $w31, $w1, $w21" + + - + input: + bytes: [ 0x78, 0x39, 0xb5, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dotp_s.h $w23, $w22, $w25" + + - + input: + bytes: [ 0x78, 0x45, 0x75, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dotp_s.w $w20, $w14, $w5" + + - + input: + bytes: [ 0x78, 0x76, 0x14, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dotp_s.d $w17, $w2, $w22" + + - + input: + bytes: [ 0x78, 0xa6, 0x13, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dotp_u.h $w13, $w2, $w6" + + - + input: + bytes: [ 0x78, 0xd5, 0xb3, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dotp_u.w $w15, $w22, $w21" + + - + input: + bytes: [ 0x78, 0xfa, 0x81, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dotp_u.d $w4, $w16, $w26" + + - + input: + bytes: [ 0x79, 0x36, 0xe0, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpadd_s.h $w1, $w28, $w22" + + - + input: + bytes: [ 0x79, 0x4c, 0x0a, 0x93 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpadd_s.w $w10, $w1, $w12" + + - + input: + bytes: [ 0x79, 0x7b, 0xa8, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpadd_s.d $w3, $w21, $w27" + + - + input: + bytes: [ 0x79, 0xb4, 0x2c, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpadd_u.h $w17, $w5, $w20" + + - + input: + bytes: [ 0x79, 0xd0, 0x46, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpadd_u.w $w24, $w8, $w16" + + - + input: + bytes: [ 0x79, 0xf0, 0xeb, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpadd_u.d $w15, $w29, $w16" + + - + input: + bytes: [ 0x7a, 0x2c, 0x59, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpsub_s.h $w4, $w11, $w12" + + - + input: + bytes: [ 0x7a, 0x46, 0x39, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpsub_s.w $w4, $w7, $w6" + + - + input: + bytes: [ 0x7a, 0x7c, 0x67, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpsub_s.d $w31, $w12, $w28" + + - + input: + bytes: [ 0x7a, 0xb1, 0xc9, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpsub_u.h $w4, $w25, $w17" + + - + input: + bytes: [ 0x7a, 0xd0, 0xcc, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpsub_u.w $w19, $w25, $w16" + + - + input: + bytes: [ 0x7a, 0xfa, 0x51, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dpsub_u.d $w7, $w10, $w26" + + - + input: + bytes: [ 0x7a, 0x22, 0xc7, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hadd_s.h $w28, $w24, $w2" + + - + input: + bytes: [ 0x7a, 0x4b, 0x8e, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hadd_s.w $w24, $w17, $w11" + + - + input: + bytes: [ 0x7a, 0x74, 0x7c, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hadd_s.d $w17, $w15, $w20" + + - + input: + bytes: [ 0x7a, 0xb1, 0xeb, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hadd_u.h $w12, $w29, $w17" + + - + input: + bytes: [ 0x7a, 0xc6, 0x2a, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hadd_u.w $w9, $w5, $w6" + + - + input: + bytes: [ 0x7a, 0xe6, 0xa0, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hadd_u.d $w1, $w20, $w6" + + - + input: + bytes: [ 0x7b, 0x3d, 0x74, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hsub_s.h $w16, $w14, $w29" + + - + input: + bytes: [ 0x7b, 0x4b, 0x6a, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hsub_s.w $w9, $w13, $w11" + + - + input: + bytes: [ 0x7b, 0x6e, 0x97, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hsub_s.d $w30, $w18, $w14" + + - + input: + bytes: [ 0x7b, 0xae, 0x61, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hsub_u.h $w7, $w12, $w14" + + - + input: + bytes: [ 0x7b, 0xc5, 0x2d, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hsub_u.w $w21, $w5, $w5" + + - + input: + bytes: [ 0x7b, 0xff, 0x62, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "hsub_u.d $w11, $w12, $w31" + + - + input: + bytes: [ 0x7b, 0x1e, 0x84, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvev.b $w18, $w16, $w30" + + - + input: + bytes: [ 0x7b, 0x2d, 0x03, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvev.h $w14, $w0, $w13" + + - + input: + bytes: [ 0x7b, 0x56, 0xcb, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvev.w $w12, $w25, $w22" + + - + input: + bytes: [ 0x7b, 0x63, 0xdf, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvev.d $w30, $w27, $w3" + + - + input: + bytes: [ 0x7a, 0x15, 0x1f, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvl.b $w29, $w3, $w21" + + - + input: + bytes: [ 0x7a, 0x31, 0x56, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvl.h $w27, $w10, $w17" + + - + input: + bytes: [ 0x7a, 0x40, 0x09, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvl.w $w6, $w1, $w0" + + - + input: + bytes: [ 0x7a, 0x78, 0x80, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvl.d $w3, $w16, $w24" + + - + input: + bytes: [ 0x7b, 0x94, 0x2a, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvod.b $w11, $w5, $w20" + + - + input: + bytes: [ 0x7b, 0xbf, 0x6c, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvod.h $w18, $w13, $w31" + + - + input: + bytes: [ 0x7b, 0xd8, 0x87, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvod.w $w29, $w16, $w24" + + - + input: + bytes: [ 0x7b, 0xfd, 0x65, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvod.d $w22, $w12, $w29" + + - + input: + bytes: [ 0x7a, 0x86, 0xf1, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvr.b $w4, $w30, $w6" + + - + input: + bytes: [ 0x7a, 0xbd, 0x9f, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvr.h $w28, $w19, $w29" + + - + input: + bytes: [ 0x7a, 0xd5, 0xa4, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvr.w $w18, $w20, $w21" + + - + input: + bytes: [ 0x7a, 0xec, 0xf5, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ilvr.d $w23, $w30, $w12" + + - + input: + bytes: [ 0x78, 0x9d, 0xfc, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddv.b $w17, $w31, $w29" + + - + input: + bytes: [ 0x78, 0xa9, 0xc1, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddv.h $w7, $w24, $w9" + + - + input: + bytes: [ 0x78, 0xd4, 0xb5, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddv.w $w22, $w22, $w20" + + - + input: + bytes: [ 0x78, 0xf4, 0xd7, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddv.d $w30, $w26, $w20" + + - + input: + bytes: [ 0x7b, 0x17, 0x5d, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_a.b $w23, $w11, $w23" + + - + input: + bytes: [ 0x7b, 0x3e, 0x2d, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_a.h $w20, $w5, $w30" + + - + input: + bytes: [ 0x7b, 0x5e, 0x91, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_a.w $w7, $w18, $w30" + + - + input: + bytes: [ 0x7b, 0x7f, 0x42, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_a.d $w8, $w8, $w31" + + - + input: + bytes: [ 0x79, 0x13, 0x0a, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_s.b $w10, $w1, $w19" + + - + input: + bytes: [ 0x79, 0x31, 0xeb, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_s.h $w15, $w29, $w17" + + - + input: + bytes: [ 0x79, 0x4e, 0xeb, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_s.w $w15, $w29, $w14" + + - + input: + bytes: [ 0x79, 0x63, 0xc6, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_s.d $w25, $w24, $w3" + + - + input: + bytes: [ 0x79, 0x85, 0xc3, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_u.b $w12, $w24, $w5" + + - + input: + bytes: [ 0x79, 0xa7, 0x31, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_u.h $w5, $w6, $w7" + + - + input: + bytes: [ 0x79, 0xc7, 0x24, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_u.w $w16, $w4, $w7" + + - + input: + bytes: [ 0x79, 0xf8, 0x66, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "max_u.d $w26, $w12, $w24" + + - + input: + bytes: [ 0x7b, 0x81, 0xd1, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_a.b $w4, $w26, $w1" + + - + input: + bytes: [ 0x7b, 0xbf, 0x6b, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_a.h $w12, $w13, $w31" + + - + input: + bytes: [ 0x7b, 0xc0, 0xa7, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_a.w $w28, $w20, $w0" + + - + input: + bytes: [ 0x7b, 0xf3, 0xa3, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_a.d $w12, $w20, $w19" + + - + input: + bytes: [ 0x7a, 0x0e, 0x1c, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_s.b $w19, $w3, $w14" + + - + input: + bytes: [ 0x7a, 0x28, 0xae, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_s.h $w27, $w21, $w8" + + - + input: + bytes: [ 0x7a, 0x5e, 0x70, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_s.w $w0, $w14, $w30" + + - + input: + bytes: [ 0x7a, 0x75, 0x41, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_s.d $w6, $w8, $w21" + + - + input: + bytes: [ 0x7a, 0x88, 0xd5, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_u.b $w22, $w26, $w8" + + - + input: + bytes: [ 0x7a, 0xac, 0xd9, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_u.h $w7, $w27, $w12" + + - + input: + bytes: [ 0x7a, 0xce, 0xa2, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_u.w $w8, $w20, $w14" + + - + input: + bytes: [ 0x7a, 0xef, 0x76, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "min_u.d $w26, $w14, $w15" + + - + input: + bytes: [ 0x7b, 0x1a, 0x0c, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mod_s.b $w18, $w1, $w26" + + - + input: + bytes: [ 0x7b, 0x3c, 0xf7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mod_s.h $w31, $w30, $w28" + + - + input: + bytes: [ 0x7b, 0x4d, 0x30, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mod_s.w $w2, $w6, $w13" + + - + input: + bytes: [ 0x7b, 0x76, 0xdd, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mod_s.d $w21, $w27, $w22" + + - + input: + bytes: [ 0x7b, 0x8d, 0x3c, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mod_u.b $w16, $w7, $w13" + + - + input: + bytes: [ 0x7b, 0xa7, 0x46, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mod_u.h $w24, $w8, $w7" + + - + input: + bytes: [ 0x7b, 0xd1, 0x17, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mod_u.w $w30, $w2, $w17" + + - + input: + bytes: [ 0x7b, 0xf9, 0x17, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mod_u.d $w31, $w2, $w25" + + - + input: + bytes: [ 0x79, 0x0c, 0x2b, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubv.b $w14, $w5, $w12" + + - + input: + bytes: [ 0x79, 0x3e, 0x39, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubv.h $w6, $w7, $w30" + + - + input: + bytes: [ 0x79, 0x55, 0x13, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubv.w $w13, $w2, $w21" + + - + input: + bytes: [ 0x79, 0x7b, 0x74, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubv.d $w16, $w14, $w27" + + - + input: + bytes: [ 0x78, 0x0d, 0x1d, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mulv.b $w20, $w3, $w13" + + - + input: + bytes: [ 0x78, 0x2e, 0xd6, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mulv.h $w27, $w26, $w14" + + - + input: + bytes: [ 0x78, 0x43, 0xea, 0x92 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mulv.w $w10, $w29, $w3" + + - + input: + bytes: [ 0x78, 0x7d, 0x99, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mulv.d $w7, $w19, $w29" + + - + input: + bytes: [ 0x79, 0x07, 0xd9, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pckev.b $w5, $w27, $w7" + + - + input: + bytes: [ 0x79, 0x3b, 0x20, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pckev.h $w1, $w4, $w27" + + - + input: + bytes: [ 0x79, 0x40, 0xa7, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pckev.w $w30, $w20, $w0" + + - + input: + bytes: [ 0x79, 0x6f, 0x09, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pckev.d $w6, $w1, $w15" + + - + input: + bytes: [ 0x79, 0x9e, 0xe4, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pckod.b $w18, $w28, $w30" + + - + input: + bytes: [ 0x79, 0xa8, 0x2e, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pckod.h $w26, $w5, $w8" + + - + input: + bytes: [ 0x79, 0xc2, 0x22, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pckod.w $w9, $w4, $w2" + + - + input: + bytes: [ 0x79, 0xf4, 0xb7, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pckod.d $w30, $w22, $w20" + + - + input: + bytes: [ 0x78, 0x0c, 0xb9, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sld.b $w5, $w23[$12]" + + - + input: + bytes: [ 0x78, 0x23, 0xb8, 0x54 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sld.h $w1, $w23[$3]" + + - + input: + bytes: [ 0x78, 0x49, 0x45, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sld.w $w20, $w8[$9]" + + - + input: + bytes: [ 0x78, 0x7e, 0xb9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sld.d $w7, $w23[$fp]" + + - + input: + bytes: [ 0x78, 0x11, 0x00, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll.b $w3, $w0, $w17" + + - + input: + bytes: [ 0x78, 0x23, 0xdc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll.h $w17, $w27, $w3" + + - + input: + bytes: [ 0x78, 0x46, 0x3c, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll.w $w16, $w7, $w6" + + - + input: + bytes: [ 0x78, 0x7a, 0x02, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll.d $w9, $w0, $w26" + + - + input: + bytes: [ 0x78, 0x81, 0x0f, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "splat.b $w28, $w1[$1]" + + - + input: + bytes: [ 0x78, 0xab, 0x58, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "splat.h $w2, $w11[$11]" + + - + input: + bytes: [ 0x78, 0xcb, 0x05, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "splat.w $w22, $w0[$11]" + + - + input: + bytes: [ 0x78, 0xe2, 0x00, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "splat.d $w0, $w0[$2]" + + - + input: + bytes: [ 0x78, 0x91, 0x27, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra.b $w28, $w4, $w17" + + - + input: + bytes: [ 0x78, 0xa3, 0x4b, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra.h $w13, $w9, $w3" + + - + input: + bytes: [ 0x78, 0xd3, 0xae, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra.w $w27, $w21, $w19" + + - + input: + bytes: [ 0x78, 0xf7, 0x47, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra.d $w30, $w8, $w23" + + - + input: + bytes: [ 0x78, 0x92, 0x94, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srar.b $w19, $w18, $w18" + + - + input: + bytes: [ 0x78, 0xa8, 0xb9, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srar.h $w7, $w23, $w8" + + - + input: + bytes: [ 0x78, 0xc2, 0x60, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srar.w $w1, $w12, $w2" + + - + input: + bytes: [ 0x78, 0xee, 0x3d, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srar.d $w21, $w7, $w14" + + - + input: + bytes: [ 0x79, 0x13, 0x1b, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl.b $w12, $w3, $w19" + + - + input: + bytes: [ 0x79, 0x34, 0xfd, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl.h $w23, $w31, $w20" + + - + input: + bytes: [ 0x79, 0x4b, 0xdc, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl.w $w18, $w27, $w11" + + - + input: + bytes: [ 0x79, 0x7a, 0x60, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl.d $w3, $w12, $w26" + + - + input: + bytes: [ 0x79, 0x0b, 0xab, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlr.b $w15, $w21, $w11" + + - + input: + bytes: [ 0x79, 0x33, 0x6d, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlr.h $w21, $w13, $w19" + + - + input: + bytes: [ 0x79, 0x43, 0xf1, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlr.w $w6, $w30, $w3" + + - + input: + bytes: [ 0x79, 0x6e, 0x10, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlr.d $w1, $w2, $w14" + + - + input: + bytes: [ 0x78, 0x01, 0x7e, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subs_s.b $w25, $w15, $w1" + + - + input: + bytes: [ 0x78, 0x36, 0xcf, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subs_s.h $w28, $w25, $w22" + + - + input: + bytes: [ 0x78, 0x55, 0x62, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subs_s.w $w10, $w12, $w21" + + - + input: + bytes: [ 0x78, 0x72, 0xa1, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subs_s.d $w4, $w20, $w18" + + - + input: + bytes: [ 0x78, 0x99, 0x35, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subs_u.b $w21, $w6, $w25" + + - + input: + bytes: [ 0x78, 0xa7, 0x50, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subs_u.h $w3, $w10, $w7" + + - + input: + bytes: [ 0x78, 0xca, 0x7a, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subs_u.w $w9, $w15, $w10" + + - + input: + bytes: [ 0x78, 0xea, 0x99, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subs_u.d $w7, $w19, $w10" + + - + input: + bytes: [ 0x79, 0x0c, 0x39, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subsus_u.b $w6, $w7, $w12" + + - + input: + bytes: [ 0x79, 0x33, 0xe9, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subsus_u.h $w6, $w29, $w19" + + - + input: + bytes: [ 0x79, 0x47, 0x79, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subsus_u.w $w7, $w15, $w7" + + - + input: + bytes: [ 0x79, 0x6f, 0x1a, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subsus_u.d $w9, $w3, $w15" + + - + input: + bytes: [ 0x79, 0x9f, 0x1d, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subsuu_s.b $w22, $w3, $w31" + + - + input: + bytes: [ 0x79, 0xb6, 0xbc, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subsuu_s.h $w19, $w23, $w22" + + - + input: + bytes: [ 0x79, 0xcd, 0x52, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subsuu_s.w $w9, $w10, $w13" + + - + input: + bytes: [ 0x79, 0xe0, 0x31, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subsuu_s.d $w5, $w6, $w0" + + - + input: + bytes: [ 0x78, 0x93, 0x69, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subv.b $w6, $w13, $w19" + + - + input: + bytes: [ 0x78, 0xac, 0xc9, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subv.h $w4, $w25, $w12" + + - + input: + bytes: [ 0x78, 0xcb, 0xde, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subv.w $w27, $w27, $w11" + + - + input: + bytes: [ 0x78, 0xea, 0xc2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subv.d $w9, $w24, $w10" + + - + input: + bytes: [ 0x78, 0x05, 0x80, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "vshf.b $w3, $w16, $w5" + + - + input: + bytes: [ 0x78, 0x28, 0x9d, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "vshf.h $w20, $w19, $w8" + + - + input: + bytes: [ 0x78, 0x59, 0xf4, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "vshf.w $w16, $w30, $w25" + + - + input: + bytes: [ 0x78, 0x6f, 0x5c, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "vshf.d $w19, $w11, $w15" diff --git a/tests/MC/Mips/test_3rf.txt.yaml b/tests/MC/Mips/test_3rf.txt.yaml new file mode 100644 index 0000000000..feae054335 --- /dev/null +++ b/tests/MC/Mips/test_3rf.txt.yaml @@ -0,0 +1,820 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x1c, 0x9f, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fadd.w $w28, $w19, $w28" + + - + input: + bytes: [ 0x78, 0x3d, 0x13, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fadd.d $w13, $w2, $w29" + + - + input: + bytes: [ 0x78, 0x19, 0x5b, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcaf.w $w14, $w11, $w25" + + - + input: + bytes: [ 0x78, 0x33, 0x08, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcaf.d $w1, $w1, $w19" + + - + input: + bytes: [ 0x78, 0x90, 0xb8, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fceq.w $w1, $w23, $w16" + + - + input: + bytes: [ 0x78, 0xb0, 0x40, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fceq.d $w0, $w8, $w16" + + - + input: + bytes: [ 0x79, 0x98, 0x4c, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcle.w $w16, $w9, $w24" + + - + input: + bytes: [ 0x79, 0xa1, 0x76, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcle.d $w27, $w14, $w1" + + - + input: + bytes: [ 0x79, 0x08, 0x47, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fclt.w $w28, $w8, $w8" + + - + input: + bytes: [ 0x79, 0x2b, 0xcf, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fclt.d $w30, $w25, $w11" + + - + input: + bytes: [ 0x78, 0xd7, 0x90, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcne.w $w2, $w18, $w23" + + - + input: + bytes: [ 0x78, 0xef, 0xa3, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcne.d $w14, $w20, $w15" + + - + input: + bytes: [ 0x78, 0x59, 0x92, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcor.w $w10, $w18, $w25" + + - + input: + bytes: [ 0x78, 0x6b, 0xcc, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcor.d $w17, $w25, $w11" + + - + input: + bytes: [ 0x78, 0xd5, 0x13, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcueq.w $w14, $w2, $w21" + + - + input: + bytes: [ 0x78, 0xe7, 0x1f, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcueq.d $w29, $w3, $w7" + + - + input: + bytes: [ 0x79, 0xc3, 0x2c, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcule.w $w17, $w5, $w3" + + - + input: + bytes: [ 0x79, 0xfe, 0x0f, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcule.d $w31, $w1, $w30" + + - + input: + bytes: [ 0x79, 0x49, 0xc9, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcult.w $w6, $w25, $w9" + + - + input: + bytes: [ 0x79, 0x71, 0x46, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcult.d $w27, $w8, $w17" + + - + input: + bytes: [ 0x78, 0x48, 0xa1, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcun.w $w4, $w20, $w8" + + - + input: + bytes: [ 0x78, 0x63, 0x5f, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcun.d $w29, $w11, $w3" + + - + input: + bytes: [ 0x78, 0x93, 0x93, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcune.w $w13, $w18, $w19" + + - + input: + bytes: [ 0x78, 0xb5, 0xd4, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fcune.d $w16, $w26, $w21" + + - + input: + bytes: [ 0x78, 0xc2, 0xc3, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fdiv.w $w13, $w24, $w2" + + - + input: + bytes: [ 0x78, 0xf9, 0x24, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fdiv.d $w19, $w4, $w25" + + - + input: + bytes: [ 0x7a, 0x10, 0x02, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fexdo.h $w8, $w0, $w16" + + - + input: + bytes: [ 0x7a, 0x3b, 0x68, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fexdo.w $w0, $w13, $w27" + + - + input: + bytes: [ 0x79, 0xc3, 0x04, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fexp2.w $w17, $w0, $w3" + + - + input: + bytes: [ 0x79, 0xea, 0x05, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fexp2.d $w22, $w0, $w10" + + - + input: + bytes: [ 0x79, 0x17, 0x37, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmadd.w $w29, $w6, $w23" + + - + input: + bytes: [ 0x79, 0x35, 0xe2, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmadd.d $w11, $w28, $w21" + + - + input: + bytes: [ 0x7b, 0x8d, 0xb8, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmax.w $w0, $w23, $w13" + + - + input: + bytes: [ 0x7b, 0xa8, 0x96, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmax.d $w26, $w18, $w8" + + - + input: + bytes: [ 0x7b, 0xca, 0x82, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmax_a.w $w10, $w16, $w10" + + - + input: + bytes: [ 0x7b, 0xf6, 0x4f, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmax_a.d $w30, $w9, $w22" + + - + input: + bytes: [ 0x7b, 0x1e, 0x0e, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmin.w $w24, $w1, $w30" + + - + input: + bytes: [ 0x7b, 0x2a, 0xde, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmin.d $w27, $w27, $w10" + + - + input: + bytes: [ 0x7b, 0x54, 0xea, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmin_a.w $w10, $w29, $w20" + + - + input: + bytes: [ 0x7b, 0x78, 0xf3, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmin_a.d $w13, $w30, $w24" + + - + input: + bytes: [ 0x79, 0x40, 0xcc, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmsub.w $w17, $w25, $w0" + + - + input: + bytes: [ 0x79, 0x70, 0x92, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmsub.d $w8, $w18, $w16" + + - + input: + bytes: [ 0x78, 0x8f, 0x78, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmul.w $w3, $w15, $w15" + + - + input: + bytes: [ 0x78, 0xaa, 0xf2, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fmul.d $w9, $w30, $w10" + + - + input: + bytes: [ 0x7a, 0x0a, 0x2e, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsaf.w $w25, $w5, $w10" + + - + input: + bytes: [ 0x7a, 0x3d, 0x1e, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsaf.d $w25, $w3, $w29" + + - + input: + bytes: [ 0x7a, 0x8d, 0x8a, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fseq.w $w11, $w17, $w13" + + - + input: + bytes: [ 0x7a, 0xbf, 0x07, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fseq.d $w29, $w0, $w31" + + - + input: + bytes: [ 0x7b, 0x9f, 0xff, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsle.w $w30, $w31, $w31" + + - + input: + bytes: [ 0x7b, 0xb8, 0xbc, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsle.d $w18, $w23, $w24" + + - + input: + bytes: [ 0x7b, 0x06, 0x2b, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fslt.w $w12, $w5, $w6" + + - + input: + bytes: [ 0x7b, 0x35, 0xd4, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fslt.d $w16, $w26, $w21" + + - + input: + bytes: [ 0x7a, 0xcc, 0x0f, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsne.w $w30, $w1, $w12" + + - + input: + bytes: [ 0x7a, 0xf7, 0x6b, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsne.d $w14, $w13, $w23" + + - + input: + bytes: [ 0x7a, 0x5b, 0x6e, 0xdc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsor.w $w27, $w13, $w27" + + - + input: + bytes: [ 0x7a, 0x6b, 0xc3, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsor.d $w12, $w24, $w11" + + - + input: + bytes: [ 0x78, 0x41, 0xd7, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsub.w $w31, $w26, $w1" + + - + input: + bytes: [ 0x78, 0x7b, 0x8c, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsub.d $w19, $w17, $w27" + + - + input: + bytes: [ 0x7a, 0xd9, 0xc4, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsueq.w $w16, $w24, $w25" + + - + input: + bytes: [ 0x7a, 0xee, 0x74, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsueq.d $w18, $w14, $w14" + + - + input: + bytes: [ 0x7b, 0xcd, 0xf5, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsule.w $w23, $w30, $w13" + + - + input: + bytes: [ 0x7b, 0xfa, 0x58, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsule.d $w2, $w11, $w26" + + - + input: + bytes: [ 0x7b, 0x56, 0xd2, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsult.w $w11, $w26, $w22" + + - + input: + bytes: [ 0x7b, 0x7e, 0xb9, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsult.d $w6, $w23, $w30" + + - + input: + bytes: [ 0x7a, 0x5c, 0x90, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsun.w $w3, $w18, $w28" + + - + input: + bytes: [ 0x7a, 0x73, 0x5c, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsun.d $w18, $w11, $w19" + + - + input: + bytes: [ 0x7a, 0x82, 0xfc, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsune.w $w16, $w31, $w2" + + - + input: + bytes: [ 0x7a, 0xb1, 0xd0, 0xdc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fsune.d $w3, $w26, $w17" + + - + input: + bytes: [ 0x7a, 0x98, 0x24, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftq.h $w16, $w4, $w24" + + - + input: + bytes: [ 0x7a, 0xb9, 0x29, 0x5b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ftq.w $w5, $w5, $w25" + + - + input: + bytes: [ 0x79, 0x4a, 0xa4, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd_q.h $w16, $w20, $w10" + + - + input: + bytes: [ 0x79, 0x69, 0x17, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd_q.w $w28, $w2, $w9" + + - + input: + bytes: [ 0x7b, 0x49, 0x92, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddr_q.h $w8, $w18, $w9" + + - + input: + bytes: [ 0x7b, 0x70, 0x67, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddr_q.w $w29, $w12, $w16" + + - + input: + bytes: [ 0x79, 0x8a, 0xd6, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub_q.h $w24, $w26, $w10" + + - + input: + bytes: [ 0x79, 0xbc, 0xf3, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub_q.w $w13, $w30, $w28" + + - + input: + bytes: [ 0x7b, 0x8b, 0xab, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubr_q.h $w12, $w21, $w11" + + - + input: + bytes: [ 0x7b, 0xb4, 0x70, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubr_q.w $w1, $w14, $w20" + + - + input: + bytes: [ 0x79, 0x1e, 0x81, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul_q.h $w6, $w16, $w30" + + - + input: + bytes: [ 0x79, 0x24, 0x0c, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul_q.w $w16, $w1, $w4" + + - + input: + bytes: [ 0x7b, 0x13, 0xa1, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mulr_q.h $w6, $w20, $w19" + + - + input: + bytes: [ 0x7b, 0x34, 0x0e, 0xdc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mulr_q.w $w27, $w1, $w20" diff --git a/tests/MC/Mips/test_bit.txt.yaml b/tests/MC/Mips/test_bit.txt.yaml new file mode 100644 index 0000000000..f6da52255a --- /dev/null +++ b/tests/MC/Mips/test_bit.txt.yaml @@ -0,0 +1,480 @@ +test_cases: + - + input: + bytes: [ 0x79, 0xf2, 0xf5, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bclri.b $w21, $w30, 2" + + - + input: + bytes: [ 0x79, 0xe0, 0xae, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bclri.h $w24, $w21, 0" + + - + input: + bytes: [ 0x79, 0xc3, 0xf5, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bclri.w $w23, $w30, 3" + + - + input: + bytes: [ 0x79, 0x80, 0x5a, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bclri.d $w9, $w11, 0" + + - + input: + bytes: [ 0x7b, 0x71, 0x66, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsli.b $w25, $w12, 1" + + - + input: + bytes: [ 0x7b, 0x60, 0xb5, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsli.h $w21, $w22, 0" + + - + input: + bytes: [ 0x7b, 0x40, 0x25, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsli.w $w22, $w4, 0" + + - + input: + bytes: [ 0x7b, 0x06, 0x11, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsli.d $w6, $w2, 6" + + - + input: + bytes: [ 0x7b, 0xf0, 0x9b, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsri.b $w15, $w19, 0" + + - + input: + bytes: [ 0x7b, 0xe1, 0xf2, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsri.h $w8, $w30, 1" + + - + input: + bytes: [ 0x7b, 0xc5, 0x98, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsri.w $w2, $w19, 5" + + - + input: + bytes: [ 0x7b, 0x81, 0xa4, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "binsri.d $w18, $w20, 1" + + - + input: + bytes: [ 0x7a, 0xf0, 0x9e, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bnegi.b $w24, $w19, 0" + + - + input: + bytes: [ 0x7a, 0xe3, 0x5f, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bnegi.h $w28, $w11, 3" + + - + input: + bytes: [ 0x7a, 0xc5, 0xd8, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bnegi.w $w1, $w27, 5" + + - + input: + bytes: [ 0x7a, 0x81, 0xa9, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bnegi.d $w4, $w21, 1" + + - + input: + bytes: [ 0x7a, 0x70, 0x44, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bseti.b $w18, $w8, 0" + + - + input: + bytes: [ 0x7a, 0x62, 0x76, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bseti.h $w24, $w14, 2" + + - + input: + bytes: [ 0x7a, 0x44, 0x92, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bseti.w $w9, $w18, 4" + + - + input: + bytes: [ 0x7a, 0x01, 0x79, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bseti.d $w7, $w15, 1" + + - + input: + bytes: [ 0x78, 0x72, 0xff, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sat_s.b $w31, $w31, 2" + + - + input: + bytes: [ 0x78, 0x60, 0x9c, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sat_s.h $w19, $w19, 0" + + - + input: + bytes: [ 0x78, 0x40, 0xec, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sat_s.w $w19, $w29, 0" + + - + input: + bytes: [ 0x78, 0x00, 0xb2, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sat_s.d $w11, $w22, 0" + + - + input: + bytes: [ 0x78, 0xf3, 0x68, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sat_u.b $w1, $w13, 3" + + - + input: + bytes: [ 0x78, 0xe4, 0xc7, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sat_u.h $w30, $w24, 4" + + - + input: + bytes: [ 0x78, 0xc0, 0x6f, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sat_u.w $w31, $w13, 0" + + - + input: + bytes: [ 0x78, 0x85, 0x87, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sat_u.d $w29, $w16, 5" + + - + input: + bytes: [ 0x78, 0x71, 0x55, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slli.b $w23, $w10, 1" + + - + input: + bytes: [ 0x78, 0x61, 0x92, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slli.h $w9, $w18, 1" + + - + input: + bytes: [ 0x78, 0x44, 0xea, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slli.w $w11, $w29, 4" + + - + input: + bytes: [ 0x78, 0x01, 0xa6, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slli.d $w25, $w20, 1" + + - + input: + bytes: [ 0x78, 0xf1, 0xee, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srai.b $w24, $w29, 1" + + - + input: + bytes: [ 0x78, 0xe0, 0x30, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srai.h $w1, $w6, 0" + + - + input: + bytes: [ 0x78, 0xc1, 0xd1, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srai.w $w7, $w26, 1" + + - + input: + bytes: [ 0x78, 0x83, 0xcd, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srai.d $w20, $w25, 3" + + - + input: + bytes: [ 0x79, 0x70, 0xc9, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srari.b $w5, $w25, 0" + + - + input: + bytes: [ 0x79, 0x64, 0x31, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srari.h $w7, $w6, 4" + + - + input: + bytes: [ 0x79, 0x45, 0x5c, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srari.w $w17, $w11, 5" + + - + input: + bytes: [ 0x79, 0x05, 0xcd, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srari.d $w21, $w25, 5" + + - + input: + bytes: [ 0x79, 0x72, 0x00, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srli.b $w2, $w0, 2" + + - + input: + bytes: [ 0x79, 0x62, 0xff, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srli.h $w31, $w31, 2" + + - + input: + bytes: [ 0x79, 0x44, 0x49, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srli.w $w5, $w9, 4" + + - + input: + bytes: [ 0x79, 0x05, 0xd6, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srli.d $w27, $w26, 5" + + - + input: + bytes: [ 0x79, 0xf0, 0x1c, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlri.b $w18, $w3, 0" + + - + input: + bytes: [ 0x79, 0xe3, 0x10, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlri.h $w1, $w2, 3" + + - + input: + bytes: [ 0x79, 0xc2, 0xb2, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlri.w $w11, $w22, 2" + + - + input: + bytes: [ 0x79, 0x86, 0x56, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlri.d $w24, $w10, 6" diff --git a/tests/MC/Mips/test_ctrlregs.txt.yaml b/tests/MC/Mips/test_ctrlregs.txt.yaml new file mode 100644 index 0000000000..475435b5dd --- /dev/null +++ b/tests/MC/Mips/test_ctrlregs.txt.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x7e, 0x00, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfcmsa $1, $0" + + - + input: + bytes: [ 0x78, 0x7e, 0x08, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfcmsa $2, $1" + + - + input: + bytes: [ 0x78, 0x7e, 0x10, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfcmsa $3, $2" + + - + input: + bytes: [ 0x78, 0x7e, 0x19, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfcmsa $4, $3" + + - + input: + bytes: [ 0x78, 0x7e, 0x21, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfcmsa $5, $4" + + - + input: + bytes: [ 0x78, 0x7e, 0x29, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfcmsa $6, $5" + + - + input: + bytes: [ 0x78, 0x7e, 0x31, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfcmsa $7, $6" + + - + input: + bytes: [ 0x78, 0x7e, 0x3a, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfcmsa $8, $7" + + - + input: + bytes: [ 0x78, 0x3e, 0x08, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctcmsa $0, $1" + + - + input: + bytes: [ 0x78, 0x3e, 0x10, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctcmsa $1, $2" + + - + input: + bytes: [ 0x78, 0x3e, 0x18, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctcmsa $2, $3" + + - + input: + bytes: [ 0x78, 0x3e, 0x20, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctcmsa $3, $4" + + - + input: + bytes: [ 0x78, 0x3e, 0x29, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctcmsa $4, $5" + + - + input: + bytes: [ 0x78, 0x3e, 0x31, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctcmsa $5, $6" + + - + input: + bytes: [ 0x78, 0x3e, 0x39, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctcmsa $6, $7" + + - + input: + bytes: [ 0x78, 0x3e, 0x41, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctcmsa $7, $8" diff --git a/tests/MC/Mips/test_dlsa.txt.yaml b/tests/MC/Mips/test_dlsa.txt.yaml new file mode 100644 index 0000000000..251190837a --- /dev/null +++ b/tests/MC/Mips/test_dlsa.txt.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dlsa $8, $9, $10, 1" + + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dlsa $8, $9, $10, 2" + + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dlsa $8, $9, $10, 3" + + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dlsa $8, $9, $10, 4" diff --git a/tests/MC/Mips/test_elm.s.yaml b/tests/MC/Mips/test_elm.s.yaml index 9ad7c3d497..82b7a8f967 100644 --- a/tests/MC/Mips/test_elm.s.yaml +++ b/tests/MC/Mips/test_elm.s.yaml @@ -48,7 +48,7 @@ test_cases: input: bytes: [ 0x78, 0xf2, 0x6f, 0x99 ] arch: "CS_ARCH_MIPS" - options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ] + options: [ "CS_MODE_MIPS64", "CS_MODE_BIG_ENDIAN" ] expected: insns: - diff --git a/tests/MC/Mips/test_elm.txt.yaml b/tests/MC/Mips/test_elm.txt.yaml new file mode 100644 index 0000000000..9eadb6a5cf --- /dev/null +++ b/tests/MC/Mips/test_elm.txt.yaml @@ -0,0 +1,140 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x82, 0x43, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "copy_s.b $13, $w8[2]" + + - + input: + bytes: [ 0x78, 0xa0, 0xc8, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "copy_s.h $1, $w25[0]" + + - + input: + bytes: [ 0x78, 0xb1, 0x2d, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "copy_s.w $22, $w5[1]" + + - + input: + bytes: [ 0x78, 0xc4, 0xa5, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "copy_u.b $22, $w20[4]" + + - + input: + bytes: [ 0x78, 0xe0, 0x25, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "copy_u.h $20, $w4[0]" + + - + input: + bytes: [ 0x78, 0x04, 0xe8, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sldi.b $w0, $w29[4]" + + - + input: + bytes: [ 0x78, 0x20, 0x8a, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sldi.h $w8, $w17[0]" + + - + input: + bytes: [ 0x78, 0x32, 0xdd, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sldi.w $w20, $w27[2]" + + - + input: + bytes: [ 0x78, 0x38, 0x61, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sldi.d $w4, $w12[0]" + + - + input: + bytes: [ 0x78, 0x42, 0x1e, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "splati.b $w25, $w3[2]" + + - + input: + bytes: [ 0x78, 0x61, 0xe6, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "splati.h $w24, $w28[1]" + + - + input: + bytes: [ 0x78, 0x70, 0x93, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "splati.w $w13, $w18[0]" + + - + input: + bytes: [ 0x78, 0x78, 0x0f, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "splati.d $w28, $w1[0]" + + - + input: + bytes: [ 0x78, 0xbe, 0xc5, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move.v $w23, $w24" diff --git a/tests/MC/Mips/test_elm_insert.txt.yaml b/tests/MC/Mips/test_elm_insert.txt.yaml new file mode 100644 index 0000000000..92c1850162 --- /dev/null +++ b/tests/MC/Mips/test_elm_insert.txt.yaml @@ -0,0 +1,30 @@ +test_cases: + - + input: + bytes: [ 0x79, 0x03, 0xed, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "insert.b $w23[3], $sp" + + - + input: + bytes: [ 0x79, 0x22, 0x2d, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "insert.h $w20[2], $5" + + - + input: + bytes: [ 0x79, 0x32, 0x7a, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "insert.w $w8[2], $15" diff --git a/tests/MC/Mips/test_elm_insert_msa64.txt.yaml b/tests/MC/Mips/test_elm_insert_msa64.txt.yaml new file mode 100644 index 0000000000..adcc11ac68 --- /dev/null +++ b/tests/MC/Mips/test_elm_insert_msa64.txt.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x79, 0x39, 0xe8, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "insert.d $w1[1], $sp" diff --git a/tests/MC/Mips/test_elm_insve.txt.yaml b/tests/MC/Mips/test_elm_insve.txt.yaml new file mode 100644 index 0000000000..4fbec6986d --- /dev/null +++ b/tests/MC/Mips/test_elm_insve.txt.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x79, 0x43, 0x4e, 0x59 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "insve.b $w25[3], $w9[0]" + + - + input: + bytes: [ 0x79, 0x62, 0x16, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "insve.h $w24[2], $w2[0]" + + - + input: + bytes: [ 0x79, 0x72, 0x68, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "insve.w $w0[2], $w13[0]" + + - + input: + bytes: [ 0x79, 0x78, 0x90, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "insve.d $w3[0], $w18[0]" diff --git a/tests/MC/Mips/test_elm_msa64.txt.yaml b/tests/MC/Mips/test_elm_msa64.txt.yaml new file mode 100644 index 0000000000..818390f5ba --- /dev/null +++ b/tests/MC/Mips/test_elm_msa64.txt.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x78, 0xb8, 0xfc, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "copy_s.d $19, $w31[0]" diff --git a/tests/MC/Mips/test_i10.txt.yaml b/tests/MC/Mips/test_i10.txt.yaml new file mode 100644 index 0000000000..93223de212 --- /dev/null +++ b/tests/MC/Mips/test_i10.txt.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x7b, 0x06, 0x32, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ldi.b $w8, 198" + + - + input: + bytes: [ 0x7b, 0x29, 0xcd, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ldi.h $w20, 313" + + - + input: + bytes: [ 0x7b, 0x4f, 0x66, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ldi.w $w24, 492" + + - + input: + bytes: [ 0x7b, 0x7a, 0x66, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ldi.d $w27, 844" diff --git a/tests/MC/Mips/test_i5.txt.yaml b/tests/MC/Mips/test_i5.txt.yaml new file mode 100644 index 0000000000..07e72f063e --- /dev/null +++ b/tests/MC/Mips/test_i5.txt.yaml @@ -0,0 +1,440 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x1e, 0xf8, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addvi.b $w3, $w31, 30" + + - + input: + bytes: [ 0x78, 0x3a, 0x6e, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addvi.h $w24, $w13, 26" + + - + input: + bytes: [ 0x78, 0x5a, 0xa6, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addvi.w $w26, $w20, 26" + + - + input: + bytes: [ 0x78, 0x75, 0x0c, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addvi.d $w16, $w1, 21" + + - + input: + bytes: [ 0x78, 0x18, 0xae, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceqi.b $w24, $w21, 24" + + - + input: + bytes: [ 0x78, 0x22, 0x7f, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceqi.h $w31, $w15, 2" + + - + input: + bytes: [ 0x78, 0x5f, 0x0b, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceqi.w $w12, $w1, 31" + + - + input: + bytes: [ 0x78, 0x67, 0xb6, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceqi.d $w24, $w22, 7" + + - + input: + bytes: [ 0x7a, 0x01, 0x83, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clei_s.b $w12, $w16, 1" + + - + input: + bytes: [ 0x7a, 0x37, 0x50, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clei_s.h $w2, $w10, 23" + + - + input: + bytes: [ 0x7a, 0x56, 0x59, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clei_s.w $w4, $w11, 22" + + - + input: + bytes: [ 0x7a, 0x76, 0xe8, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clei_s.d $w0, $w29, 22" + + - + input: + bytes: [ 0x7a, 0x83, 0x8d, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clei_u.b $w21, $w17, 3" + + - + input: + bytes: [ 0x7a, 0xb1, 0x3f, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clei_u.h $w29, $w7, 17" + + - + input: + bytes: [ 0x7a, 0xc2, 0x08, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clei_u.w $w1, $w1, 2" + + - + input: + bytes: [ 0x7a, 0xfd, 0xde, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clei_u.d $w27, $w27, 29" + + - + input: + bytes: [ 0x79, 0x19, 0x6c, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clti_s.b $w19, $w13, 25" + + - + input: + bytes: [ 0x79, 0x34, 0x53, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clti_s.h $w15, $w10, 20" + + - + input: + bytes: [ 0x79, 0x4b, 0x63, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clti_s.w $w12, $w12, 11" + + - + input: + bytes: [ 0x79, 0x71, 0xa7, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clti_s.d $w29, $w20, 17" + + - + input: + bytes: [ 0x79, 0x9d, 0x4b, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clti_u.b $w14, $w9, 29" + + - + input: + bytes: [ 0x79, 0xb9, 0xce, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clti_u.h $w24, $w25, 25" + + - + input: + bytes: [ 0x79, 0xd6, 0x08, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clti_u.w $w1, $w1, 22" + + - + input: + bytes: [ 0x79, 0xe1, 0xcd, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clti_u.d $w21, $w25, 1" + + - + input: + bytes: [ 0x79, 0x01, 0xad, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maxi_s.b $w22, $w21, 1" + + - + input: + bytes: [ 0x79, 0x38, 0x2f, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maxi_s.h $w29, $w5, 24" + + - + input: + bytes: [ 0x79, 0x54, 0x50, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maxi_s.w $w1, $w10, 20" + + - + input: + bytes: [ 0x79, 0x70, 0xeb, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maxi_s.d $w13, $w29, 16" + + - + input: + bytes: [ 0x79, 0x8c, 0x05, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maxi_u.b $w20, $w0, 12" + + - + input: + bytes: [ 0x79, 0xa3, 0x70, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maxi_u.h $w1, $w14, 3" + + - + input: + bytes: [ 0x79, 0xcb, 0xb6, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maxi_u.w $w27, $w22, 11" + + - + input: + bytes: [ 0x79, 0xe4, 0x36, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maxi_u.d $w26, $w6, 4" + + - + input: + bytes: [ 0x7a, 0x01, 0x09, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mini_s.b $w4, $w1, 1" + + - + input: + bytes: [ 0x7a, 0x37, 0xde, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mini_s.h $w27, $w27, 23" + + - + input: + bytes: [ 0x7a, 0x49, 0x5f, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mini_s.w $w28, $w11, 9" + + - + input: + bytes: [ 0x7a, 0x6a, 0x52, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mini_s.d $w11, $w10, 10" + + - + input: + bytes: [ 0x7a, 0x9b, 0xbc, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mini_u.b $w18, $w23, 27" + + - + input: + bytes: [ 0x7a, 0xb2, 0xd1, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mini_u.h $w7, $w26, 18" + + - + input: + bytes: [ 0x7a, 0xda, 0x62, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mini_u.w $w11, $w12, 26" + + - + input: + bytes: [ 0x7a, 0xe2, 0x7a, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mini_u.d $w11, $w15, 2" + + - + input: + bytes: [ 0x78, 0x93, 0xa6, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "subvi.b $w24, $w20, 19" + + - + input: + bytes: [ 0x78, 0xa4, 0x9a, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "subvi.h $w11, $w19, 4" + + - + input: + bytes: [ 0x78, 0xcb, 0x53, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "subvi.w $w12, $w10, 11" + + - + input: + bytes: [ 0x78, 0xe7, 0x84, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "subvi.d $w19, $w16, 7" diff --git a/tests/MC/Mips/test_i8.txt.yaml b/tests/MC/Mips/test_i8.txt.yaml new file mode 100644 index 0000000000..eacde3ccfb --- /dev/null +++ b/tests/MC/Mips/test_i8.txt.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x30, 0xe8, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "andi.b $w2, $w29, 48" + + - + input: + bytes: [ 0x78, 0x7e, 0xb1, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bmnzi.b $w6, $w22, 126" + + - + input: + bytes: [ 0x79, 0x58, 0x0e, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bmzi.b $w27, $w1, 88" + + - + input: + bytes: [ 0x7a, 0xbd, 0x1f, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bseli.b $w29, $w3, 189" + + - + input: + bytes: [ 0x7a, 0x38, 0x88, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "nori.b $w1, $w17, 56" + + - + input: + bytes: [ 0x79, 0x87, 0xa6, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ori.b $w26, $w20, 135" + + - + input: + bytes: [ 0x78, 0x69, 0xf4, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "shf.b $w19, $w30, 105" + + - + input: + bytes: [ 0x79, 0x4c, 0x44, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "shf.h $w17, $w8, 76" + + - + input: + bytes: [ 0x7a, 0x5d, 0x1b, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "shf.w $w14, $w3, 93" + + - + input: + bytes: [ 0x7b, 0x14, 0x54, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "xori.b $w16, $w10, 20" diff --git a/tests/MC/Mips/test_lsa.txt.yaml b/tests/MC/Mips/test_lsa.txt.yaml new file mode 100644 index 0000000000..9164cc8fad --- /dev/null +++ b/tests/MC/Mips/test_lsa.txt.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lsa $8, $9, $10, 1" + + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lsa $8, $9, $10, 2" + + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lsa $8, $9, $10, 3" + + - + input: + bytes: [ 0x01, 0x2a, 0x40, 0xc5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lsa $8, $9, $10, 4" diff --git a/tests/MC/Mips/test_mi10.s.yaml b/tests/MC/Mips/test_mi10.s.yaml index 83aeb82f7f..b2646a2845 100644 --- a/tests/MC/Mips/test_mi10.s.yaml +++ b/tests/MC/Mips/test_mi10.s.yaml @@ -16,7 +16,7 @@ test_cases: expected: insns: - - asm_text: "ld.b $w1, ($v0)" + asm_text: "ld.b $w1, 0($v0)" - input: bytes: [ 0x79, 0xff, 0x18, 0xa0 ] @@ -52,7 +52,7 @@ test_cases: expected: insns: - - asm_text: "ld.h $w5, ($a2)" + asm_text: "ld.h $w5, 0($a2)" - input: bytes: [ 0x79, 0x00, 0x39, 0xa1 ] @@ -169,7 +169,7 @@ test_cases: expected: insns: - - asm_text: "ld.d $w18, ($s3)" + asm_text: "ld.d $w18, 0($s3)" - input: bytes: [ 0x78, 0x40, 0xa4, 0xe3 ] diff --git a/tests/MC/Mips/test_mi10.txt.yaml b/tests/MC/Mips/test_mi10.txt.yaml new file mode 100644 index 0000000000..5cb59273d5 --- /dev/null +++ b/tests/MC/Mips/test_mi10.txt.yaml @@ -0,0 +1,230 @@ +test_cases: + - + input: + bytes: [ 0x7a, 0x00, 0x08, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.b $w0, -512($1)" + + - + input: + bytes: [ 0x78, 0x00, 0x10, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.b $w1, 0($2)" + + - + input: + bytes: [ 0x79, 0xff, 0x18, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.b $w2, 511($3)" + + - + input: + bytes: [ 0x7a, 0x00, 0x20, 0xe1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.h $w3, -1024($4)" + + - + input: + bytes: [ 0x7b, 0x00, 0x29, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.h $w4, -512($5)" + + - + input: + bytes: [ 0x78, 0x00, 0x31, 0x61 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.h $w5, 0($6)" + + - + input: + bytes: [ 0x79, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.h $w6, 512($7)" + + - + input: + bytes: [ 0x79, 0xff, 0x41, 0xe1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.h $w7, 1022($8)" + + - + input: + bytes: [ 0x7a, 0x00, 0x4a, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.w $w8, -2048($9)" + + - + input: + bytes: [ 0x7b, 0x00, 0x52, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.w $w9, -1024($10)" + + - + input: + bytes: [ 0x7b, 0x80, 0x5a, 0xa2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.w $w10, -512($11)" + + - + input: + bytes: [ 0x78, 0x80, 0x62, 0xe2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.w $w11, 512($12)" + + - + input: + bytes: [ 0x79, 0x00, 0x6b, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.w $w12, 1024($13)" + + - + input: + bytes: [ 0x79, 0xff, 0x73, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.w $w13, 2044($14)" + + - + input: + bytes: [ 0x7a, 0x00, 0x7b, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.d $w14, -4096($15)" + + - + input: + bytes: [ 0x7b, 0x00, 0x83, 0xe3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.d $w15, -2048($16)" + + - + input: + bytes: [ 0x7b, 0x80, 0x8c, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.d $w16, -1024($17)" + + - + input: + bytes: [ 0x7b, 0xc0, 0x94, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.d $w17, -512($18)" + + - + input: + bytes: [ 0x78, 0x00, 0x9c, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.d $w18, 0($19)" + + - + input: + bytes: [ 0x78, 0x40, 0xa4, 0xe3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.d $w19, 512($20)" + + - + input: + bytes: [ 0x78, 0x80, 0xad, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.d $w20, 1024($21)" + + - + input: + bytes: [ 0x79, 0x00, 0xb5, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.d $w21, 2048($22)" + + - + input: + bytes: [ 0x79, 0xff, 0xbd, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ld.d $w22, 4088($23)" diff --git a/tests/MC/Mips/test_vec.txt.yaml b/tests/MC/Mips/test_vec.txt.yaml new file mode 100644 index 0000000000..ec90f03780 --- /dev/null +++ b/tests/MC/Mips/test_vec.txt.yaml @@ -0,0 +1,70 @@ +test_cases: + - + input: + bytes: [ 0x78, 0x1b, 0xa6, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "and.v $w25, $w20, $w27" + + - + input: + bytes: [ 0x78, 0x87, 0x34, 0x5e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bmnz.v $w17, $w6, $w7" + + - + input: + bytes: [ 0x78, 0xa9, 0x88, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bmz.v $w3, $w17, $w9" + + - + input: + bytes: [ 0x78, 0xce, 0x02, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bsel.v $w8, $w0, $w14" + + - + input: + bytes: [ 0x78, 0x40, 0xf9, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "nor.v $w7, $w31, $w0" + + - + input: + bytes: [ 0x78, 0x3e, 0xd6, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "or.v $w24, $w26, $w30" + + - + input: + bytes: [ 0x78, 0x6f, 0xd9, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "xor.v $w7, $w27, $w15" diff --git a/tests/MC/Mips/valid-32-el.txt.yaml b/tests/MC/Mips/valid-32-el.txt.yaml new file mode 100644 index 0000000000..121fa61661 --- /dev/null +++ b/tests/MC/Mips/valid-32-el.txt.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x28, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfgc0 $4, $5, 0" + + - + input: + bytes: [ 0x02, 0x28, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfgc0 $4, $5, 2" + + - + input: + bytes: [ 0x00, 0x2a, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtgc0 $4, $5, 0" + + - + input: + bytes: [ 0x02, 0x22, 0x65, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtgc0 $5, $4, 2" + + - + input: + bytes: [ 0x00, 0x2c, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhgc0 $4, $5, 0" + + - + input: + bytes: [ 0x04, 0x2c, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhgc0 $4, $5, 4" + + - + input: + bytes: [ 0x00, 0x2e, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthgc0 $4, $5, 0" + + - + input: + bytes: [ 0x04, 0x2e, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthgc0 $4, $5, 4" + + - + input: + bytes: [ 0x28, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "hypcall" + + - + input: + bytes: [ 0x28, 0x50, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "hypcall 10" + + - + input: + bytes: [ 0x0b, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbginv" + + - + input: + bytes: [ 0x0c, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbginvf" + + - + input: + bytes: [ 0x10, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbgp" + + - + input: + bytes: [ 0x09, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbgr" + + - + input: + bytes: [ 0x0a, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbgwi" + + - + input: + bytes: [ 0x0e, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbgwr" diff --git a/tests/MC/Mips/valid-32.txt.yaml b/tests/MC/Mips/valid-32.txt.yaml new file mode 100644 index 0000000000..7517b67b84 --- /dev/null +++ b/tests/MC/Mips/valid-32.txt.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x40, 0x64, 0x28, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfgc0 $4, $5, 0" + + - + input: + bytes: [ 0x40, 0x64, 0x28, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfgc0 $4, $5, 2" + + - + input: + bytes: [ 0x40, 0x64, 0x2a, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtgc0 $4, $5, 0" + + - + input: + bytes: [ 0x40, 0x65, 0x22, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtgc0 $5, $4, 2" + + - + input: + bytes: [ 0x40, 0x64, 0x2c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhgc0 $4, $5, 0" + + - + input: + bytes: [ 0x40, 0x64, 0x2c, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhgc0 $4, $5, 4" + + - + input: + bytes: [ 0x40, 0x64, 0x2e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthgc0 $4, $5, 0" + + - + input: + bytes: [ 0x40, 0x64, 0x2e, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthgc0 $4, $5, 4" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "hypcall" + + - + input: + bytes: [ 0x42, 0x00, 0x50, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "hypcall 10" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbginv" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbginvf" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbgp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbgr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbgwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbgwr" diff --git a/tests/MC/Mips/valid-32r6-el.txt.yaml b/tests/MC/Mips/valid-32r6-el.txt.yaml new file mode 100644 index 0000000000..4929528bb9 --- /dev/null +++ b/tests/MC/Mips/valid-32r6-el.txt.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x0f, 0x00, 0x41, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32b $1, $2, $1" + + - + input: + bytes: [ 0x4f, 0x00, 0xa4, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32h $4, $5, $4" + + - + input: + bytes: [ 0x8f, 0x00, 0x07, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32w $7, $8, $7" + + - + input: + bytes: [ 0x0f, 0x01, 0x41, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32cb $1, $2, $1" + + - + input: + bytes: [ 0x4f, 0x01, 0xa4, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32ch $4, $5, $4" + + - + input: + bytes: [ 0x8f, 0x01, 0x07, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32cw $7, $8, $7" diff --git a/tests/MC/Mips/valid-32r6.txt.yaml b/tests/MC/Mips/valid-32r6.txt.yaml new file mode 100644 index 0000000000..873f569a84 --- /dev/null +++ b/tests/MC/Mips/valid-32r6.txt.yaml @@ -0,0 +1,60 @@ +test_cases: + - + input: + bytes: [ 0x7c, 0x41, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32b $1, $2, $1" + + - + input: + bytes: [ 0x7c, 0xa4, 0x00, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32h $4, $5, $4" + + - + input: + bytes: [ 0x7d, 0x07, 0x00, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32w $7, $8, $7" + + - + input: + bytes: [ 0x7c, 0x41, 0x01, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32cb $1, $2, $1" + + - + input: + bytes: [ 0x7c, 0xa4, 0x01, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32ch $4, $5, $4" + + - + input: + bytes: [ 0x7d, 0x07, 0x01, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "crc32cw $7, $8, $7" diff --git a/tests/MC/Mips/valid-64-el.txt.yaml b/tests/MC/Mips/valid-64-el.txt.yaml new file mode 100644 index 0000000000..07424ab666 --- /dev/null +++ b/tests/MC/Mips/valid-64-el.txt.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x29, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfgc0 $4, $5, 0" + + - + input: + bytes: [ 0x04, 0x29, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfgc0 $4, $5, 4" + + - + input: + bytes: [ 0x00, 0x23, 0x65, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtgc0 $5, $4, 0" + + - + input: + bytes: [ 0x04, 0x2b, 0x64, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtgc0 $4, $5, 4" diff --git a/tests/MC/Mips/valid-64.txt.yaml b/tests/MC/Mips/valid-64.txt.yaml new file mode 100644 index 0000000000..fc4e7a691c --- /dev/null +++ b/tests/MC/Mips/valid-64.txt.yaml @@ -0,0 +1,40 @@ +test_cases: + - + input: + bytes: [ 0x40, 0x64, 0x29, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfgc0 $4, $5, 0" + + - + input: + bytes: [ 0x40, 0x64, 0x29, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfgc0 $4, $5, 4" + + - + input: + bytes: [ 0x40, 0x65, 0x23, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtgc0 $5, $4, 0" + + - + input: + bytes: [ 0x40, 0x64, 0x2b, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtgc0 $4, $5, 4" diff --git a/tests/MC/Mips/valid-64r6-el.txt.yaml b/tests/MC/Mips/valid-64r6-el.txt.yaml new file mode 100644 index 0000000000..ec0e642ead --- /dev/null +++ b/tests/MC/Mips/valid-64r6-el.txt.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x0f, 0x00, 0x41, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32b $1, $2, $1" + + - + input: + bytes: [ 0x4f, 0x00, 0xa4, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32h $4, $5, $4" + + - + input: + bytes: [ 0x8f, 0x00, 0x07, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32w $7, $8, $7" + + - + input: + bytes: [ 0xcf, 0x00, 0x6a, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32d $10, $11, $10" + + - + input: + bytes: [ 0x0f, 0x01, 0x41, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32cb $1, $2, $1" + + - + input: + bytes: [ 0x4f, 0x01, 0xa4, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32ch $4, $5, $4" + + - + input: + bytes: [ 0x8f, 0x01, 0x07, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32cw $7, $8, $7" + + - + input: + bytes: [ 0xcf, 0x01, 0x6a, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32cd $10, $11, $10" diff --git a/tests/MC/Mips/valid-64r6.txt.yaml b/tests/MC/Mips/valid-64r6.txt.yaml new file mode 100644 index 0000000000..d268a21de8 --- /dev/null +++ b/tests/MC/Mips/valid-64r6.txt.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0x7c, 0x41, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32b $1, $2, $1" + + - + input: + bytes: [ 0x7c, 0xa4, 0x00, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32h $4, $5, $4" + + - + input: + bytes: [ 0x7d, 0x07, 0x00, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32w $7, $8, $7" + + - + input: + bytes: [ 0x7d, 0x6a, 0x00, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32d $10, $11, $10" + + - + input: + bytes: [ 0x7c, 0x41, 0x01, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32cb $1, $2, $1" + + - + input: + bytes: [ 0x7c, 0xa4, 0x01, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32ch $4, $5, $4" + + - + input: + bytes: [ 0x7d, 0x07, 0x01, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32cw $7, $8, $7" + + - + input: + bytes: [ 0x7d, 0x6a, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "crc32cd $10, $11, $10" diff --git a/tests/MC/Mips/valid-el.txt.yaml b/tests/MC/Mips/valid-el.txt.yaml new file mode 100644 index 0000000000..34ad444352 --- /dev/null +++ b/tests/MC/Mips/valid-el.txt.yaml @@ -0,0 +1,280 @@ +test_cases: + - + input: + bytes: [ 0x01, 0x00, 0x76, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "bbit0 $19, 22, 8" + + - + input: + bytes: [ 0x28, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "baddu $9, $6, $7" + + - + input: + bytes: [ 0x01, 0x00, 0x0a, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "bbit032 $8, 10, 8" + + - + input: + bytes: [ 0x01, 0x00, 0x7f, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "bbit1 $3, 31, 8" + + - + input: + bytes: [ 0x01, 0x00, 0x0a, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "bbit132 $24, 10, 8" + + - + input: + bytes: [ 0x72, 0xec, 0x29, 0x71 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "cins $9, $9, 17, 29" + + - + input: + bytes: [ 0xb3, 0x44, 0x4f, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "cins32 $15, $2, 18, 8" + + - + input: + bytes: [ 0x03, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "dmul $9, $6, $7" + + - + input: + bytes: [ 0x40, 0x00, 0x22, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "dmfc2 $2, 64" + + - + input: + bytes: [ 0x47, 0x40, 0xa2, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "dmtc2 $2, 16455" + + - + input: + bytes: [ 0x2d, 0x48, 0xc0, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "dpop $9, $6" + + - + input: + bytes: [ 0x7a, 0x34, 0xef, 0x71 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "exts $15, $15, 17, 6" + + - + input: + bytes: [ 0xbb, 0x42, 0xa4, 0x71 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "exts32 $4, $13, 10, 8" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x71 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtm0 $15" + + - + input: + bytes: [ 0x0c, 0x00, 0x00, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtm1 $16" + + - + input: + bytes: [ 0x0d, 0x00, 0x20, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtm2 $17" + + - + input: + bytes: [ 0x09, 0x00, 0x40, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtp0 $18" + + - + input: + bytes: [ 0x0a, 0x00, 0x60, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtp1 $19" + + - + input: + bytes: [ 0x0b, 0x00, 0x80, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtp2 $20" + + - + input: + bytes: [ 0x2c, 0x48, 0xc0, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "pop $9, $6" + + - + input: + bytes: [ 0x2a, 0xc8, 0xf8, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "seq $25, $23, $24" + + - + input: + bytes: [ 0xae, 0x09, 0x10, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "seqi $16, $16, 38" + + - + input: + bytes: [ 0x2b, 0xb8, 0xf4, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "sne $23, $23, $20" + + - + input: + bytes: [ 0xef, 0xb1, 0x04, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "snei $4, $16, -313" + + - + input: + bytes: [ 0x8f, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "sync 6" + + - + input: + bytes: [ 0x11, 0xa8, 0x55, 0x71 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "v3mulu $21, $10, $21" + + - + input: + bytes: [ 0x10, 0x18, 0x70, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "vmm0 $3, $19, $16" + + - + input: + bytes: [ 0x0f, 0xd8, 0x66, 0x73 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "vmulu $27, $27, $6" diff --git a/tests/MC/Mips/valid-fp64-el.txt.yaml b/tests/MC/Mips/valid-fp64-el.txt.yaml new file mode 100644 index 0000000000..de98701aea --- /dev/null +++ b/tests/MC/Mips/valid-fp64-el.txt.yaml @@ -0,0 +1,260 @@ +test_cases: + - + input: + bytes: [ 0x04, 0x60, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f12" + + - + input: + bytes: [ 0x05, 0x60, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "abs.s $f0, $f12" + + - + input: + bytes: [ 0x04, 0x60, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sqrt.d $f0, $f12" + + - + input: + bytes: [ 0x05, 0x60, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "abs.d $f0, $f12" + + - + input: + bytes: [ 0x00, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "add.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x01, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sub.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x02, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mul.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x03, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "div.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x06, 0x10, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mov.d $f0, $f2" + + - + input: + bytes: [ 0x07, 0x10, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "neg.d $f0, $f2" + + - + input: + bytes: [ 0x24, 0x10, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cvt.w.d $f0, $f2" + + - + input: + bytes: [ 0x21, 0x10, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cvt.d.s $f0, $f2" + + - + input: + bytes: [ 0x21, 0x10, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cvt.d.w $f0, $f2" + + - + input: + bytes: [ 0x20, 0x10, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cvt.s.d $f0, $f2" + + - + input: + bytes: [ 0x21, 0x81, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0xa0, 0xd3, 0xc0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.pu $f14, $f26" + + - + input: + bytes: [ 0xa6, 0x90, 0x14, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.ps.s $f2, $f18, $f20" + + - + input: + bytes: [ 0xa8, 0x17, 0xc0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.pl $f30, $f2" + + - + input: + bytes: [ 0x2c, 0x46, 0xde, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pll.ps $f24, $f8, $f30" + + - + input: + bytes: [ 0x2d, 0xd0, 0xdc, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "plu.ps $f0, $f26, $f28" + + - + input: + bytes: [ 0x00, 0x00, 0xe4, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mthc1 $4, $f0" + + - + input: + bytes: [ 0x00, 0x00, 0x64, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mfhc1 $4, $f0" + + - + input: + bytes: [ 0x00, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x02, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x01, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" diff --git a/tests/MC/Mips/valid-fp64.txt.yaml b/tests/MC/Mips/valid-fp64.txt.yaml new file mode 100644 index 0000000000..347edd68fa --- /dev/null +++ b/tests/MC/Mips/valid-fp64.txt.yaml @@ -0,0 +1,260 @@ +test_cases: + - + input: + bytes: [ 0x46, 0x00, 0x60, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f12" + + - + input: + bytes: [ 0x46, 0x00, 0x60, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.s $f0, $f12" + + - + input: + bytes: [ 0x46, 0x20, 0x60, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f0, $f12" + + - + input: + bytes: [ 0x46, 0x20, 0x60, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.d $f0, $f12" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "div.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.d $f0, $f2" + + - + input: + bytes: [ 0x46, 0x20, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.d $f0, $f2" + + - + input: + bytes: [ 0x46, 0x20, 0x10, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f0, $f2" + + - + input: + bytes: [ 0x46, 0x00, 0x10, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f0, $f2" + + - + input: + bytes: [ 0x46, 0x80, 0x10, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f0, $f2" + + - + input: + bytes: [ 0x46, 0x20, 0x10, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f0, $f2" + + - + input: + bytes: [ 0x46, 0xa0, 0x81, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x46, 0xa0, 0xf3, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x46, 0xc0, 0xd3, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.pu $f14, $f26" + + - + input: + bytes: [ 0x46, 0x14, 0x90, 0xa6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.ps.s $f2, $f18, $f20" + + - + input: + bytes: [ 0x46, 0xc0, 0x17, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.pl $f30, $f2" + + - + input: + bytes: [ 0x46, 0xde, 0x46, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pll.ps $f24, $f8, $f30" + + - + input: + bytes: [ 0x46, 0xdc, 0xd0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "plu.ps $f0, $f26, $f28" + + - + input: + bytes: [ 0x44, 0xe4, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthc1 $4, $f0" + + - + input: + bytes: [ 0x44, 0x64, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhc1 $4, $f0" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" diff --git a/tests/MC/Mips/valid-micromips-el.txt.yaml b/tests/MC/Mips/valid-micromips-el.txt.yaml new file mode 100644 index 0000000000..799e5a223a --- /dev/null +++ b/tests/MC/Mips/valid-micromips-el.txt.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x85, 0x00, 0xfc, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mfgc0 $4, $5, 0" + + - + input: + bytes: [ 0x85, 0x00, 0xfc, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mfgc0 $4, $5, 2" + + - + input: + bytes: [ 0xa4, 0x00, 0xfc, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mtgc0 $5, $4, 0" + + - + input: + bytes: [ 0xa4, 0x00, 0xfc, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mtgc0 $5, $4, 2" + + - + input: + bytes: [ 0x85, 0x00, 0xf4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mfhgc0 $4, $5, 0" + + - + input: + bytes: [ 0x85, 0x00, 0xf4, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mfhgc0 $4, $5, 2" + + - + input: + bytes: [ 0xa4, 0x00, 0xf4, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mthgc0 $5, $4, 0" + + - + input: + bytes: [ 0xa4, 0x00, 0xf4, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mthgc0 $5, $4, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x7c, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "hypcall" + + - + input: + bytes: [ 0x0a, 0x00, 0x7c, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "hypcall 10" + + - + input: + bytes: [ 0x00, 0x00, 0x7c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbginv" + + - + input: + bytes: [ 0x00, 0x00, 0x7c, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbginvf" + + - + input: + bytes: [ 0x00, 0x00, 0x7c, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbgp" + + - + input: + bytes: [ 0x00, 0x00, 0x7c, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbgr" + + - + input: + bytes: [ 0x00, 0x00, 0x7c, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbgwi" + + - + input: + bytes: [ 0x00, 0x00, 0x7c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbgwr" diff --git a/tests/MC/Mips/valid-micromips.txt.yaml b/tests/MC/Mips/valid-micromips.txt.yaml new file mode 100644 index 0000000000..8765a25608 --- /dev/null +++ b/tests/MC/Mips/valid-micromips.txt.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x85, 0x04, 0xfc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mfgc0 $4, $5, 0" + + - + input: + bytes: [ 0x00, 0x85, 0x14, 0xfc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mfgc0 $4, $5, 2" + + - + input: + bytes: [ 0x00, 0xa4, 0x06, 0xfc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mtgc0 $5, $4, 0" + + - + input: + bytes: [ 0x00, 0xa4, 0x16, 0xfc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mtgc0 $5, $4, 2" + + - + input: + bytes: [ 0x00, 0x85, 0x04, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mfhgc0 $4, $5, 0" + + - + input: + bytes: [ 0x00, 0x85, 0x14, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mfhgc0 $4, $5, 2" + + - + input: + bytes: [ 0x00, 0xa4, 0x06, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mthgc0 $5, $4, 0" + + - + input: + bytes: [ 0x00, 0xa4, 0x16, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "mthgc0 $5, $4, 2" + + - + input: + bytes: [ 0x00, 0x00, 0xc3, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "hypcall" + + - + input: + bytes: [ 0x00, 0x0a, 0xc3, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "hypcall 10" + + - + input: + bytes: [ 0x00, 0x00, 0x41, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbginv" + + - + input: + bytes: [ 0x00, 0x00, 0x51, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbginvf" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbgp" + + - + input: + bytes: [ 0x00, 0x00, 0x11, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbgr" + + - + input: + bytes: [ 0x00, 0x00, 0x21, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbgwi" + + - + input: + bytes: [ 0x00, 0x00, 0x31, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "tlbgwr" diff --git a/tests/MC/Mips/valid-micromips32r3.txt.yaml b/tests/MC/Mips/valid-micromips32r3.txt.yaml new file mode 100644 index 0000000000..58fda1ce4b --- /dev/null +++ b/tests/MC/Mips/valid-micromips32r3.txt.yaml @@ -0,0 +1,10 @@ +test_cases: + - + input: + bytes: [ 0x43, 0x60, 0x00, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3", "CS_MODE_MICRO" ] + expected: + insns: + - + asm_text: "bposge32 350" diff --git a/tests/MC/Mips/valid-mips1-el.txt.yaml b/tests/MC/Mips/valid-mips1-el.txt.yaml new file mode 100644 index 0000000000..3bcd12634b --- /dev/null +++ b/tests/MC/Mips/valid-mips1-el.txt.yaml @@ -0,0 +1,1060 @@ +test_cases: + - + input: + bytes: [ 0x85, 0xc1, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x45, 0x82, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x20, 0xb8, 0x45, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x00, 0x30, 0x3c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x00, 0xaa, 0x18, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0xd2, 0x66, 0x2d, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0xfe, 0xff, 0x08, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x48, 0x3b, 0xc9, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0xe7, 0xe3, 0x18, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x21, 0x48, 0x86, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x0a, 0x00, 0x29, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x24, 0xb8, 0x4c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x02, 0x00, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x9c, 0x14, 0x11, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x9c, 0x14, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x9c, 0x14, 0xd0, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x3b, 0xe0, 0x3c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x39, 0x00, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x38, 0xf0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x38, 0x70, 0x16, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x00, 0xa8, 0x51, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x00, 0xd0, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0xa1, 0xe5, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0xa1, 0x5e, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0xa0, 0x46, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0xa0, 0x7d, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x24, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x24, 0xc5, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x1a, 0x00, 0x2b, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0xa7, 0x3a, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x03, 0x29, 0x0f, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x1b, 0x00, 0x2f, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x4d, 0xc7, 0x58, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0xf3, 0x75, 0x68, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x94, 0xde, 0xab, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0xbd, 0xa6, 0x53, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0xb3, 0x8b, 0x01, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x3f, 0x8b, 0x00, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x2a, 0x16, 0xa8, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0xf1, 0x27, 0x50, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xb7, 0xfc, 0xd2, 0xc8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xf7, 0x81, 0x4a, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwc3 $10, -32265($26)" + + - + input: + bytes: [ 0x79, 0xef, 0xf4, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x35, 0xb5, 0x80, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0x00, 0xd8, 0x07, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x10, 0x98, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x10, 0xe8, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x12, 0x88, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x06, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x86, 0xd8, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x25, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x25, 0xc8, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x21, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x21, 0xc8, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0x48, 0x9e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x11, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x13, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x13, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x02, 0xa5, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x82, 0x57, 0x02, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x18, 0x00, 0xb4, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x18, 0x00, 0xa2, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x19, 0x00, 0x9a, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x19, 0x00, 0x32, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x23, 0x10, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x23, 0x10, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x87, 0x96, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x47, 0x78, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x27, 0x38, 0x07, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x25, 0x60, 0x1d, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x6f, 0xb2, 0xd6, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xd0, 0xe5, 0xee, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0x80, 0x3c, 0x07, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x80, 0x3c, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x04, 0x38, 0x20, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x2a, 0xb8, 0x7b, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x11, 0x25, 0x51, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x55, 0xc3, 0x39, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x2b, 0xa0, 0xab, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x55, 0xc3, 0x38, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0xc3, 0x8b, 0x11, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0xc3, 0x8b, 0x17, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x07, 0x88, 0xb7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0xc2, 0x11, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x06, 0xc8, 0x94, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x40, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x22, 0xb0, 0x6c, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x36, 0x0c, 0x36, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x90, 0xe6, 0xad, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x81, 0x14, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0xc1, 0xb5, 0x16, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x23, 0xe8, 0xd6, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x50, 0xd8, 0xbf, 0xaf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xef, 0xde, 0x06, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0x30, 0x61, 0x19, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0x7e, 0x35, 0x6f, 0xaa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0x22, 0x98, 0xd1, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x06, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x26, 0x90, 0x9e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" diff --git a/tests/MC/Mips/valid-mips1.txt.yaml b/tests/MC/Mips/valid-mips1.txt.yaml new file mode 100644 index 0000000000..1e18a0e627 --- /dev/null +++ b/tests/MC/Mips/valid-mips1.txt.yaml @@ -0,0 +1,1090 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcf, 0x4a, 0x81, 0xf7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "lwc3 $10, -32265($26)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" diff --git a/tests/MC/Mips/valid-mips2-el.txt.yaml b/tests/MC/Mips/valid-mips2-el.txt.yaml new file mode 100644 index 0000000000..11fa76b4db --- /dev/null +++ b/tests/MC/Mips/valid-mips2-el.txt.yaml @@ -0,0 +1,1550 @@ +test_cases: + - + input: + bytes: [ 0x85, 0xc1, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x45, 0x82, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x20, 0xb8, 0x45, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x48, 0x3b, 0xc9, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0xe7, 0xe3, 0x18, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x00, 0x30, 0x3c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x00, 0xaa, 0x18, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0xd2, 0x66, 0x2d, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0xfe, 0xff, 0x08, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x48, 0x86, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x0a, 0x00, 0x29, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x24, 0xb8, 0x4c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x0d, 0x00, 0x02, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x02, 0x00, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0xf5, 0xf7, 0x03, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x9c, 0x14, 0x11, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x9c, 0x14, 0xd0, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x41, 0x0c, 0xd3, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x4e, 0x01, 0x20, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "beqzl $9, 1340" + + - + input: + bytes: [ 0x20, 0x07, 0x93, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x4e, 0xf9, 0x83, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x5a, 0xfc, 0x40, 0x5d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0xe8, 0x02, 0xc0, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x7b, 0x00, 0xd2, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x46, 0xf6, 0x22, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0xfd, 0x04, 0x94, 0x57 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x4e, 0x01, 0x20, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bnezl $9, 1340" + + - + input: + bytes: [ 0x3b, 0xe0, 0x3c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x39, 0x00, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x38, 0xf0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x38, 0x70, 0x16, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0xce, 0xc2, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x8e, 0xa1, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x00, 0xa8, 0x51, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x00, 0xd0, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0xa1, 0xe5, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0xa1, 0x5e, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0xa0, 0x46, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0xa0, 0x7d, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x24, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x24, 0xc5, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x1a, 0x00, 0x2b, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0xa7, 0x3a, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x03, 0x29, 0x0f, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x1b, 0x00, 0x2f, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0xc0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x8f, 0x53, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x0f, 0x4a, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x4d, 0xc7, 0x58, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0xf3, 0x75, 0x68, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x07, 0x40, 0x0a, 0xd6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0x43, 0xad, 0x28, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0x1b, 0x90, 0x3d, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ldc3 $29, -28645($17)" + + - + input: + bytes: [ 0x94, 0xde, 0xab, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0xbd, 0xa6, 0x53, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0xb3, 0x8b, 0x01, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x3f, 0x8b, 0x00, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x67, 0xe3, 0x42, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0x2a, 0x16, 0xa8, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0xf1, 0x27, 0x50, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xb7, 0xfc, 0xd2, 0xc8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xf7, 0x81, 0x4a, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwc3 $10, -32265($26)" + + - + input: + bytes: [ 0x79, 0xef, 0xf4, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x35, 0xb5, 0x80, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0x00, 0xd8, 0x07, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x10, 0x98, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x10, 0xe8, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x12, 0x88, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x06, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x86, 0xd8, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x21, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x21, 0xc8, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x25, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x25, 0xc8, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0x48, 0x9e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x11, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x13, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x13, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x02, 0xa5, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x82, 0x57, 0x02, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x18, 0x00, 0xb4, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x18, 0x00, 0xa2, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x19, 0x00, 0x9a, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x19, 0x00, 0x32, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x23, 0x10, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x23, 0x10, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x87, 0x96, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x47, 0x78, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x27, 0x38, 0x07, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x25, 0x60, 0x1d, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x8c, 0x21, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0xcc, 0xe6, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x6f, 0xb2, 0xd6, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xd8, 0x49, 0x6f, 0xe2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0x6e, 0x77, 0xbe, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0x75, 0x5a, 0x54, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xcb, 0x16, 0x4c, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sdc3 $12, 5835($10)" + + - + input: + bytes: [ 0xd0, 0xe5, 0xee, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0x80, 0x3c, 0x07, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x80, 0x3c, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x04, 0x38, 0x20, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x2a, 0xb8, 0x7b, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x11, 0x25, 0x51, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x55, 0xc3, 0x39, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x2b, 0xa0, 0xab, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x55, 0xc3, 0x38, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x04, 0xb4, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x04, 0x08, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0xc3, 0x8b, 0x11, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0xc3, 0x8b, 0x17, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x07, 0x88, 0xb7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0xc2, 0x11, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x06, 0xc8, 0x94, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x40, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x22, 0xb0, 0x6c, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x36, 0x0c, 0x36, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x90, 0xe6, 0xad, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x81, 0x14, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0xc1, 0xb5, 0x16, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x23, 0xe8, 0xd6, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x50, 0xd8, 0xbf, 0xaf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xef, 0xde, 0x06, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0x30, 0x61, 0x19, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf7, 0x81, 0x4a, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swc3 $10, -32265($26)" + + - + input: + bytes: [ 0x7e, 0x35, 0x6f, 0xaa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0x22, 0x98, 0xd1, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0x34, 0x00, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x34, 0x9b, 0xa7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0xa0, 0xbb, 0xac, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x30, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x30, 0x55, 0xb3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0xa1, 0x13, 0x28, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x33, 0x90, 0xa9, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x31, 0x00, 0xdc, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0xf1, 0x5e, 0x8e, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x06, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x32, 0x00, 0xed, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x72, 0x21, 0x53, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0xbd, 0xad, 0xca, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x2c, 0xec, 0xeb, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x33, 0x00, 0x70, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x33, 0xfe, 0x1d, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x36, 0x00, 0xd1, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x76, 0xdd, 0xe8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x31, 0x8c, 0x8e, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x8d, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x0d, 0xf7, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x26, 0x90, 0x9e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" diff --git a/tests/MC/Mips/valid-mips2.txt.yaml b/tests/MC/Mips/valid-mips2.txt.yaml new file mode 100644 index 0000000000..fe170ba294 --- /dev/null +++ b/tests/MC/Mips/valid-mips2.txt.yaml @@ -0,0 +1,1760 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x51, 0x20, 0x01, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "beqzl $9, 1344" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x55, 0x20, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bnezl $9, 1340" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcd, 0x28, 0x23, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwc3 $8, 9166($9)" + + - + input: + bytes: [ 0xcf, 0x4a, 0x81, 0xf7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "lwc3 $10, -32265($26)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xdd, 0x07, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ldc3 $7, 9162($8)" + + - + input: + bytes: [ 0xde, 0x3d, 0x90, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "ldc3 $29, -28645($17)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xec, 0xe6, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swc3 $6, 9158($7)" + + - + input: + bytes: [ 0xef, 0x4a, 0x81, 0xf7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "swc3 $10, -32265($26)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xfc, 0xc5, 0x23, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sdc3 $5, 9154($6)" + + - + input: + bytes: [ 0xfd, 0x4c, 0x16, 0xcb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS2" ] + expected: + insns: + - + asm_text: "sdc3 $12, 5835($10)" diff --git a/tests/MC/Mips/valid-mips3-el.txt.yaml b/tests/MC/Mips/valid-mips3-el.txt.yaml new file mode 100644 index 0000000000..20473f709c --- /dev/null +++ b/tests/MC/Mips/valid-mips3-el.txt.yaml @@ -0,0 +1,1960 @@ +test_cases: + - + input: + bytes: [ 0x85, 0xc1, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x45, 0x82, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x20, 0xb8, 0x45, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x48, 0x3b, 0xc9, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0xe7, 0xe3, 0x18, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x00, 0x30, 0x3c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x00, 0xaa, 0x18, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0xd2, 0x66, 0x2d, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0xfe, 0xff, 0x08, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x48, 0x86, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x0a, 0x00, 0x29, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x24, 0xb8, 0x4c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x0d, 0x00, 0x02, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x02, 0x00, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0xf5, 0xf7, 0x03, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x9c, 0x14, 0x11, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x9c, 0x14, 0xd0, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x41, 0x0c, 0xd3, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x20, 0x07, 0x93, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x4e, 0xf9, 0x83, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x5a, 0xfc, 0x40, 0x5d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0xe8, 0x02, 0xc0, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x7b, 0x00, 0xd2, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x46, 0xf6, 0x22, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0xfd, 0x04, 0x94, 0x57 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x08, 0x00, 0xa1, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cache 1, 8($5)" + + - + input: + bytes: [ 0x3b, 0xe0, 0x3c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x39, 0x00, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x38, 0xf0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x38, 0x70, 0x16, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x4a, 0x18, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x8a, 0x6c, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0xce, 0xc2, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x8e, 0xa1, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x00, 0xa8, 0x51, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x00, 0xd0, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0xa1, 0xe5, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0xa1, 0x5e, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x21, 0x81, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x25, 0x7e, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.l.d $f24, $f15" + + - + input: + bytes: [ 0xe5, 0xea, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.l.s $f11, $f29" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0xa0, 0x46, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0xa0, 0x7d, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x24, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x24, 0xc5, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x2c, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0xc7, 0x93, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0xc7, 0x93, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x16, 0xee, 0xda, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x2d, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x9f, 0x46, 0x58, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x3f, 0x69, 0x73, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x1e, 0x00, 0x53, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x1f, 0x00, 0x11, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x1a, 0x00, 0x2b, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0xa7, 0x3a, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x03, 0x29, 0x0f, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x1b, 0x00, 0x2f, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x00, 0x68, 0x2c, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x00, 0x70, 0xb0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x1c, 0x00, 0xe9, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x1d, 0x00, 0xa6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0xb8, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0xb8, 0x04, 0x14, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x14, 0x00, 0x94, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0xbc, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0xbb, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0xbb, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x17, 0xe0, 0x72, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0xbf, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0xbf, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0xfa, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0xfa, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x16, 0x98, 0x86, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0xfe, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0xfe, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x2e, 0x38, 0xc8, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x2f, 0x28, 0xba, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0xc0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x18, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x8f, 0x53, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x0f, 0x4a, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x8b, 0x3e, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x0b, 0x2b, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x4d, 0xc7, 0x58, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0xf3, 0x75, 0x68, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x07, 0x40, 0x0a, 0xd6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0x43, 0xad, 0x28, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0x94, 0xde, 0xab, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0xbd, 0xa6, 0x53, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0xb3, 0x8b, 0x01, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x3f, 0x8b, 0x00, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x67, 0xe3, 0x42, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0x2a, 0x16, 0xa8, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0xf1, 0x27, 0x50, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xb7, 0xfc, 0xd2, 0xc8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0x79, 0xef, 0xf4, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x35, 0xb5, 0x80, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0x00, 0xd8, 0x07, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x10, 0x98, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x10, 0xe8, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x12, 0x88, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x06, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x86, 0xd8, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x21, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x21, 0xc8, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x25, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x25, 0xc8, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0x48, 0x9e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x11, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x13, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x13, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x02, 0xa5, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x82, 0x57, 0x02, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x18, 0x00, 0xb4, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x18, 0x00, 0xa2, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x19, 0x00, 0x9a, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x19, 0x00, 0x32, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x23, 0x10, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x23, 0x10, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x87, 0x96, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x47, 0x78, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x27, 0x38, 0x07, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x25, 0x60, 0x1d, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x08, 0x0b, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x48, 0x2e, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x8c, 0x21, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0xcc, 0xe6, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x6f, 0xb2, 0xd6, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xd8, 0x49, 0x6f, 0xe2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xcd, 0xdf, 0xaf, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xcb, 0x16, 0x4c, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" + + - + input: + bytes: [ 0x1f, 0xae, 0xc7, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0x39, 0xb0, 0x8b, 0xb5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0x6e, 0x77, 0xbe, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0x75, 0x5a, 0x54, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xd0, 0xe5, 0xee, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0x80, 0x3c, 0x07, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x80, 0x3c, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x04, 0x38, 0x20, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x2a, 0xb8, 0x7b, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x11, 0x25, 0x51, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x55, 0xc3, 0x39, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x2b, 0xa0, 0xab, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x55, 0xc3, 0x38, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x04, 0xb4, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x04, 0x08, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0xc3, 0x8b, 0x11, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0xc3, 0x8b, 0x17, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x07, 0x88, 0xb7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0xc2, 0x11, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x06, 0xc8, 0x94, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x40, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x22, 0xb0, 0x6c, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x36, 0x0c, 0x36, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x90, 0xe6, 0xad, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x81, 0x14, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0xc1, 0xb5, 0x16, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x23, 0xe8, 0xd6, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x50, 0xd8, 0xbf, 0xaf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xef, 0xde, 0x06, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0x30, 0x61, 0x19, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0x7e, 0x35, 0x6f, 0xaa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0x22, 0x98, 0xd1, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0x34, 0x00, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x34, 0x9b, 0xa7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0xa0, 0xbb, 0xac, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x30, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x30, 0x55, 0xb3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0xa1, 0x13, 0x28, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x33, 0x90, 0xa9, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x31, 0x00, 0xdc, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0xf1, 0x5e, 0x8e, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x06, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x32, 0x00, 0xed, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x72, 0x21, 0x53, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0xbd, 0xad, 0xca, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x2c, 0xec, 0xeb, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x33, 0x00, 0x70, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x33, 0xfe, 0x1d, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x36, 0x00, 0xd1, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x76, 0xdd, 0xe8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x31, 0x8c, 0x8e, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0xc9, 0xbd, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x09, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x8d, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x0d, 0xf7, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x26, 0x90, 0x9e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" diff --git a/tests/MC/Mips/valid-mips3.txt.yaml b/tests/MC/Mips/valid-mips3.txt.yaml new file mode 100644 index 0000000000..0d2b71010e --- /dev/null +++ b/tests/MC/Mips/valid-mips3.txt.yaml @@ -0,0 +1,2210 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jr $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dneg $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dnegu $2, $3" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x14, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa6, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xba, 0x28, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0x94, 0x00, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x11, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x72, 0xe0, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0x02, 0x86, 0x98, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xc8, 0x38, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x02, 0xe9, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x53, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x3a, 0x00, 0x27, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "xori $zero, $16, 10002" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x2c, 0x68, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xb0, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x2b, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x2e, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x6c, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xea, 0xe5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.l.s $f11, $f29" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x00, 0xff, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0x0b, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x46, 0x20, 0x18, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x3e, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x7e, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.l.d $f24, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xbd, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0xa0, 0x81, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x46, 0xa0, 0xf3, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x62, 0x9d, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x64, 0x58, 0x46, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x66, 0x73, 0x69, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x66, 0xda, 0xee, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb3, 0xc7, 0xae, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0xb5, 0x8b, 0xb0, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0xa1, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cache 1, 8($5)" + + - + input: + bytes: [ 0xbf, 0x00, 0xe2, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "cache 0, -7652($24)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf3, 0xaf, 0xdf, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xfd, 0x4c, 0x16, 0xcb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS3" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" diff --git a/tests/MC/Mips/valid-mips32-el.txt.yaml b/tests/MC/Mips/valid-mips32-el.txt.yaml new file mode 100644 index 0000000000..a7cf8282fa --- /dev/null +++ b/tests/MC/Mips/valid-mips32-el.txt.yaml @@ -0,0 +1,1560 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x21, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x25, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x04, 0x80, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x25, 0x38, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "move $7, $8" + + - + input: + bytes: [ 0x25, 0x18, 0x40, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "move $3, $2" + + - + input: + bytes: [ 0x01, 0x18, 0x5c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x11, 0x11, 0x3c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x11, 0x11, 0x1c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x01, 0x18, 0x5d, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x11, 0x11, 0x3d, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x11, 0x11, 0x1d, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3b, 0xe8, 0x05, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x02, 0x00, 0x61, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0x04, 0x00, 0x43, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xca, 0x23, 0xc8, 0xc8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" diff --git a/tests/MC/Mips/valid-mips32.txt.yaml b/tests/MC/Mips/valid-mips32.txt.yaml new file mode 100644 index 0000000000..5a19d69b77 --- /dev/null +++ b/tests/MC/Mips/valid-mips32.txt.yaml @@ -0,0 +1,3270 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" diff --git a/tests/MC/Mips/valid-mips32r2-el.txt.yaml b/tests/MC/Mips/valid-mips32r2-el.txt.yaml new file mode 100644 index 0000000000..5aa6cc3e5e --- /dev/null +++ b/tests/MC/Mips/valid-mips32r2-el.txt.yaml @@ -0,0 +1,5250 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0xa1, 0xd4, 0x94, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x04, 0x80, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0xa9, 0xf2, 0x52, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0xb1, 0x74, 0x54, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0xb9, 0x87, 0x1e, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x4c, 0x1d, 0x7f, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "synci 7500($19)" + + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0xa1, 0xd4, 0x94, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x04, 0x80, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0xa9, 0xf2, 0x52, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0xb1, 0x74, 0x54, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0xb9, 0x87, 0x1e, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x4c, 0x1d, 0x7f, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "synci 7500($19)" + + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0xa1, 0xd4, 0x94, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x04, 0x80, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0xa9, 0xf2, 0x52, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0xb1, 0x74, 0x54, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0xb9, 0x87, 0x1e, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x4c, 0x1d, 0x7f, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "synci 7500($19)" diff --git a/tests/MC/Mips/valid-mips32r2.txt.yaml b/tests/MC/Mips/valid-mips32r2.txt.yaml new file mode 100644 index 0000000000..092d007062 --- /dev/null +++ b/tests/MC/Mips/valid-mips32r2.txt.yaml @@ -0,0 +1,10830 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xdf, 0xe8, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "synci -6137($fp)" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7d, 0x07, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ext $7, $8, 0, 7" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xdf, 0xe8, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "synci -6137($fp)" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7d, 0x07, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ext $7, $8, 0, 7" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xdf, 0xe8, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "synci -6137($fp)" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7d, 0x07, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ext $7, $8, 0, 7" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" diff --git a/tests/MC/Mips/valid-mips32r3-el.txt.yaml b/tests/MC/Mips/valid-mips32r3-el.txt.yaml new file mode 100644 index 0000000000..ece49526a9 --- /dev/null +++ b/tests/MC/Mips/valid-mips32r3-el.txt.yaml @@ -0,0 +1,3460 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0xa1, 0xd4, 0x94, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0xa9, 0xf2, 0x52, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0xb1, 0x74, 0x54, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0xb9, 0x87, 0x1e, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0xa1, 0xd4, 0x94, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0xa9, 0xf2, 0x52, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0xb1, 0x74, 0x54, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0xb9, 0x87, 0x1e, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" diff --git a/tests/MC/Mips/valid-mips32r3.txt.yaml b/tests/MC/Mips/valid-mips32r3.txt.yaml new file mode 100644 index 0000000000..36a7d4e956 --- /dev/null +++ b/tests/MC/Mips/valid-mips32r3.txt.yaml @@ -0,0 +1,7220 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xdf, 0xe8, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "synci -6137($fp)" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7d, 0x07, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ext $7, $8, 0, 7" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xdf, 0xe8, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "synci -6137($fp)" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7d, 0x07, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ext $7, $8, 0, 7" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" diff --git a/tests/MC/Mips/valid-mips32r5-el.txt.yaml b/tests/MC/Mips/valid-mips32r5-el.txt.yaml new file mode 100644 index 0000000000..e102187d17 --- /dev/null +++ b/tests/MC/Mips/valid-mips32r5-el.txt.yaml @@ -0,0 +1,3460 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0xa1, 0xd4, 0x94, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0xa9, 0xf2, 0x52, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0xb1, 0x74, 0x54, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0xb9, 0x87, 0x1e, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0xa1, 0xd4, 0x94, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0xa9, 0xf2, 0x52, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0xb1, 0x74, 0x54, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0xb9, 0x87, 0x1e, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" diff --git a/tests/MC/Mips/valid-mips32r5.txt.yaml b/tests/MC/Mips/valid-mips32r5.txt.yaml new file mode 100644 index 0000000000..8b105f270e --- /dev/null +++ b/tests/MC/Mips/valid-mips32r5.txt.yaml @@ -0,0 +1,7240 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xdf, 0xe8, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "synci -6137($fp)" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "eretnc" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7d, 0x07, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ext $7, $8, 0, 7" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xdf, 0xe8, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "synci -6137($fp)" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "eretnc" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7d, 0x07, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ext $7, $8, 0, 7" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" diff --git a/tests/MC/Mips/valid-mips32r6-el.txt.yaml b/tests/MC/Mips/valid-mips32r6-el.txt.yaml new file mode 100644 index 0000000000..2588f3da0a --- /dev/null +++ b/tests/MC/Mips/valid-mips32r6-el.txt.yaml @@ -0,0 +1,1730 @@ +test_cases: + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x19, 0x00, 0x80, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lapc $4, 100" + + - + input: + bytes: [ 0x0a, 0x00, 0x29, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0xa0, 0x22, 0x43, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "align $4, $2, $3, 2" + + - + input: + bytes: [ 0x38, 0x00, 0x7f, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "aluipc $3, 56" + + - + input: + bytes: [ 0xe9, 0xff, 0x43, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "aui $3, $2, 65513" + + - + input: + bytes: [ 0xff, 0xff, 0x7e, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "auipc $3, -1" + + - + input: + bytes: [ 0x9c, 0x14, 0x11, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0xb9, 0x96, 0x37, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "balc 14572264" + + - + input: + bytes: [ 0xb9, 0x96, 0x37, 0xc8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc 14572264" + + - + input: + bytes: [ 0x02, 0x00, 0x20, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc1eqz $f0, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x3f, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc1eqz $f31, 12" + + - + input: + bytes: [ 0x02, 0x00, 0xa0, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc1nez $f0, 12" + + - + input: + bytes: [ 0x02, 0x00, 0xbf, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc1nez $f31, 12" + + - + input: + bytes: [ 0x03, 0x00, 0x20, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc2eqz $0, 16" + + - + input: + bytes: [ 0x03, 0x00, 0x3f, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc2eqz $31, 16" + + - + input: + bytes: [ 0x03, 0x00, 0xa0, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc2nez $0, 16" + + - + input: + bytes: [ 0x03, 0x00, 0xbf, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc2nez $31, 16" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x41, 0x00, 0xa6, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "beqc $5, $6, 264" + + - + input: + bytes: [ 0x4e, 0x01, 0x02, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "beqzalc $2, 1340" + + - + input: + bytes: [ 0x41, 0x00, 0xa6, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnec $5, $6, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x43, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnec $2, $3, -16" + + - + input: + bytes: [ 0x4e, 0x01, 0x02, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnezalc $2, 1340" + + - + input: + bytes: [ 0x91, 0x46, 0xa0, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "beqzc $5, 72264" + + - + input: + bytes: [ 0x41, 0x00, 0x43, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgec $2, $3, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x43, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgec $2, $3, -16" + + - + input: + bytes: [ 0x41, 0x00, 0x43, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgeuc $2, $3, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x43, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgeuc $2, $3, -16" + + - + input: + bytes: [ 0x4e, 0x01, 0x42, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgezalc $2, 1340" + + - + input: + bytes: [ 0xfb, 0xff, 0x42, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgezalc $2, -16" + + - + input: + bytes: [ 0x91, 0x46, 0xa0, 0xf8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnezc $5, 72264" + + - + input: + bytes: [ 0x41, 0x00, 0xa5, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltzc $5, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0xa5, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltzc $5, -16" + + - + input: + bytes: [ 0x41, 0x00, 0xa5, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgezc $5, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0xa5, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgezc $5, -16" + + - + input: + bytes: [ 0x4e, 0x01, 0x02, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgtzalc $2, 1340" + + - + input: + bytes: [ 0xfb, 0xff, 0x02, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgtzalc $2, -16" + + - + input: + bytes: [ 0x41, 0x00, 0x05, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "blezc $5, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x05, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "blezc $5, -16" + + - + input: + bytes: [ 0x4e, 0x01, 0x42, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltzalc $2, 1340" + + - + input: + bytes: [ 0xfb, 0xff, 0x42, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltzalc $2, -16" + + - + input: + bytes: [ 0x41, 0x00, 0x05, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgtzc $5, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x05, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgtzc $5, -16" + + - + input: + bytes: [ 0x20, 0x20, 0x02, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bitswap $4, $2" + + - + input: + bytes: [ 0x4e, 0x01, 0x02, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "blezalc $2, 1340" + + - + input: + bytes: [ 0xfb, 0xff, 0x02, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "blezalc $2, -16" + + - + input: + bytes: [ 0x41, 0x00, 0xa6, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltc $5, $6, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0xa6, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltc $5, $6, -16" + + - + input: + bytes: [ 0x41, 0x00, 0xa6, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltuc $5, $6, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0xa6, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltuc $5, $6, -16" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $zero, $zero, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x40, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $2, $zero, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x82, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $4, $2, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $zero, $zero, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x40, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $2, $zero, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x82, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $4, $2, 12" + + - + input: + bytes: [ 0x80, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.af.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x80, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.af.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x81, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.un.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x81, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.un.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x82, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.eq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x82, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.eq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x83, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ueq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x83, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ueq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x84, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.lt.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x84, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.lt.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x85, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ult.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x85, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ult.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x86, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.le.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x86, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.le.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x87, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ule.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x87, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ule.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x88, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.saf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x88, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.saf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x89, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sun.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x89, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sun.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8a, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.seq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8a, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.seq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8b, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sueq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8b, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sueq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8c, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.slt.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8c, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.slt.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8d, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sult.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8d, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sult.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8e, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sle.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8e, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sle.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8f, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sule.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8f, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sule.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x24, 0x00, 0x71, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "dvp $17" + + - + input: + bytes: [ 0x24, 0x00, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "dvp $zero" + + - + input: + bytes: [ 0x9a, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "div $2, $3, $4" + + - + input: + bytes: [ 0x9b, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "divu $2, $3, $4" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x04, 0x00, 0x70, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "evp $16" + + - + input: + bytes: [ 0x04, 0x00, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "evp $zero" + + - + input: + bytes: [ 0xc5, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lsa $2, $3, $4, 4" + + - + input: + bytes: [ 0x43, 0x00, 0x48, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lwpc $2, 268" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0xda, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mod $2, $3, $4" + + - + input: + bytes: [ 0xdb, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "modu $2, $3, $4" + + - + input: + bytes: [ 0x98, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mul $2, $3, $4" + + - + input: + bytes: [ 0xd8, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "muh $2, $3, $4" + + - + input: + bytes: [ 0x99, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mulu $2, $3, $4" + + - + input: + bytes: [ 0xd9, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "muhu $2, $3, $4" + + - + input: + bytes: [ 0x98, 0x18, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "maddf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x98, 0x18, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "maddf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x99, 0x18, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "msubf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x99, 0x18, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "msubf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x10, 0x08, 0x22, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sel.d $f0, $f1, $f2" + + - + input: + bytes: [ 0x10, 0x08, 0x02, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sel.s $f0, $f1, $f2" + + - + input: + bytes: [ 0x35, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "seleqz $2, $3, $4" + + - + input: + bytes: [ 0x37, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "selnez $2, $3, $4" + + - + input: + bytes: [ 0x1d, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "max.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x1d, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "max.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x1c, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "min.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x1c, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "min.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x1f, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "maxa.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x1f, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "maxa.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x1e, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mina.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x1e, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mina.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x14, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "seleqz.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x14, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "seleqz.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x17, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "selnez.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x17, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "selnez.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x9a, 0x20, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "rint.s $f2, $f4" + + - + input: + bytes: [ 0x9a, 0x20, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "rint.d $f2, $f4" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x9b, 0x20, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "class.s $f2, $f4" + + - + input: + bytes: [ 0x9b, 0x20, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "class.d $f2, $f4" + + - + input: + bytes: [ 0x09, 0x04, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jr.hb $4" + + - + input: + bytes: [ 0x00, 0x00, 0x1b, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jrc $27" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0x00, 0x19, 0xf8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jalrc $25" + + - + input: + bytes: [ 0xb6, 0xb3, 0x42, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ll $2, -153($18)" + + - + input: + bytes: [ 0x26, 0xec, 0x6f, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sc $15, -40($19)" + + - + input: + bytes: [ 0x51, 0x58, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "clo $11, $5" + + - + input: + bytes: [ 0x50, 0xe8, 0x80, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "clz $sp, $gp" + + - + input: + bytes: [ 0x40, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x0e, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sdbbp" + + - + input: + bytes: [ 0x8e, 0x08, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sdbbp 34" + + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x4f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sync 1" + + - + input: + bytes: [ 0x34, 0x00, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x34, 0x9b, 0xa7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x30, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x30, 0x55, 0xb3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x31, 0x00, 0xdc, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0xf1, 0x5e, 0x8e, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x32, 0x00, 0xed, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x72, 0x21, 0x53, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x33, 0x00, 0x70, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x33, 0xfe, 0x1d, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x36, 0x00, 0xd1, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x76, 0xdd, 0xe8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x43, 0x0d, 0xc8, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ldc2 $8, -701($1)" + + - + input: + bytes: [ 0xb7, 0x34, 0x52, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0x75, 0x92, 0xf4, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sdc2 $20, 629($18)" + + - + input: + bytes: [ 0x30, 0x81, 0x79, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "swc2 $25, 304($16)" + + - + input: + bytes: [ 0x00, 0x01, 0x05, 0xf8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jialc $5, 256" + + - + input: + bytes: [ 0x00, 0x01, 0x05, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jic $5, 256" + + - + input: + bytes: [ 0x25, 0x04, 0xa1, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cache 1, 8($5)" + + - + input: + bytes: [ 0x35, 0x04, 0xa1, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "pref 1, 8($5)" + + - + input: + bytes: [ 0x05, 0x00, 0x17, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sigrie 5" diff --git a/tests/MC/Mips/valid-mips32r6.txt.yaml b/tests/MC/Mips/valid-mips32r6.txt.yaml new file mode 100644 index 0000000000..4768272786 --- /dev/null +++ b/tests/MC/Mips/valid-mips32r6.txt.yaml @@ -0,0 +1,1780 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sdbbp" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sync 1" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x08, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sdbbp 34" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "seleqz $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "selnez $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mul $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mulu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "div $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "divu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xc5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lsa $2, $3, $4, 4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "muh $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "muhu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mod $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "modu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x80, 0x04, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jr.hb $4" + + - + input: + bytes: [ 0xd8, 0x1b, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jrc $27" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0xf8, 0x19, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jalrc $25" + + - + input: + bytes: [ 0x00, 0xa0, 0x58, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "clo $11, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x80, 0xe8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "clz $sp, $gp" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x18, 0x02, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "blezalc $2, 1340" + + - + input: + bytes: [ 0x18, 0x02, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "blezalc $2, -16" + + - + input: + bytes: [ 0x18, 0x42, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgezalc $2, 1340" + + - + input: + bytes: [ 0x18, 0x42, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgezalc $2, -16" + + - + input: + bytes: [ 0x18, 0x43, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgeuc $2, $3, 264" + + - + input: + bytes: [ 0x18, 0x43, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgeuc $2, $3, -16" + + - + input: + bytes: [ 0x1c, 0x02, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgtzalc $2, 1340" + + - + input: + bytes: [ 0x1c, 0x02, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgtzalc $2, -16" + + - + input: + bytes: [ 0x1c, 0x42, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltzalc $2, 1340" + + - + input: + bytes: [ 0x1c, 0x42, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltzalc $2, -16" + + - + input: + bytes: [ 0x1c, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltuc $5, $6, 264" + + - + input: + bytes: [ 0x1c, 0xa6, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltuc $5, $6, -16" + + - + input: + bytes: [ 0x20, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $zero, $zero, 12" + + - + input: + bytes: [ 0x20, 0x02, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "beqzalc $2, 1340" + + - + input: + bytes: [ 0x20, 0x40, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $2, $zero, 12" + + - + input: + bytes: [ 0x20, 0x82, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $4, $2, 12" + + - + input: + bytes: [ 0x20, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "beqc $5, $6, 264" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x3c, 0x43, 0xff, 0xe9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "aui $3, $2, 65513" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 3" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x60, 0x00, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "dvp $zero" + + - + input: + bytes: [ 0x41, 0x60, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "evp $zero" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x70, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "evp $16" + + - + input: + bytes: [ 0x41, 0x71, 0x00, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "dvp $17" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x45, 0x20, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc1eqz $f0, 12" + + - + input: + bytes: [ 0x45, 0x3f, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc1eqz $f31, 12" + + - + input: + bytes: [ 0x45, 0xa0, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc1nez $f0, 12" + + - + input: + bytes: [ 0x45, 0xbf, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc1nez $f31, 12" + + - + input: + bytes: [ 0x46, 0x00, 0x20, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "rint.s $f2, $f4" + + - + input: + bytes: [ 0x46, 0x00, 0x20, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "class.s $f2, $f4" + + - + input: + bytes: [ 0x46, 0x02, 0x08, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sel.s $f0, $f1, $f2" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "seleqz.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "selnez.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "min.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "max.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mina.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "maxa.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x18, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "maddf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x18, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "msubf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x20, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "rint.d $f2, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x20, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "class.d $f2, $f4" + + - + input: + bytes: [ 0x46, 0x22, 0x08, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sel.d $f0, $f1, $f2" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "seleqz.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "selnez.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "min.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "max.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "mina.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "maxa.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x18, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "maddf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x18, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "msubf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.af.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.un.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.eq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x83 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ueq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.lt.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ult.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.le.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ule.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.saf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sun.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.seq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sueq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.slt.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sult.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sle.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sule.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.af.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.un.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.eq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x83 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ueq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.lt.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ult.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.le.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.ule.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.saf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sun.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.seq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sueq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.slt.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sult.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sle.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cmp.sule.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "eretnc" + + - + input: + bytes: [ 0x49, 0x20, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc2eqz $0, 16" + + - + input: + bytes: [ 0x49, 0x3f, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc2eqz $31, 16" + + - + input: + bytes: [ 0x49, 0x52, 0x34, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0x49, 0x79, 0x81, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "swc2 $25, 304($16)" + + - + input: + bytes: [ 0x49, 0xa0, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc2nez $0, 16" + + - + input: + bytes: [ 0x49, 0xbf, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc2nez $31, 16" + + - + input: + bytes: [ 0x49, 0xc8, 0x0d, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ldc2 $8, -701($1)" + + - + input: + bytes: [ 0x49, 0xf4, 0x92, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sdc2 $20, 629($18)" + + - + input: + bytes: [ 0x58, 0x05, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "blezc $5, 264" + + - + input: + bytes: [ 0x58, 0x05, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "blezc $5, -16" + + - + input: + bytes: [ 0x58, 0x43, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgec $2, $3, 264" + + - + input: + bytes: [ 0x58, 0x43, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgec $2, $3, -16" + + - + input: + bytes: [ 0x58, 0xa5, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgezc $5, 264" + + - + input: + bytes: [ 0x58, 0xa5, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgezc $5, -16" + + - + input: + bytes: [ 0x5c, 0x05, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgtzc $5, 264" + + - + input: + bytes: [ 0x5c, 0x05, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bgtzc $5, -16" + + - + input: + bytes: [ 0x5c, 0xa5, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltzc $5, 264" + + - + input: + bytes: [ 0x5c, 0xa5, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltzc $5, -16" + + - + input: + bytes: [ 0x5c, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltc $5, $6, 264" + + - + input: + bytes: [ 0x5c, 0xa6, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bltc $5, $6, -16" + + - + input: + bytes: [ 0x60, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $zero, $zero, 12" + + - + input: + bytes: [ 0x60, 0x02, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnezalc $2, 1340" + + - + input: + bytes: [ 0x60, 0x40, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $2, $zero, 12" + + - + input: + bytes: [ 0x60, 0x82, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $4, $2, 12" + + - + input: + bytes: [ 0x60, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnec $5, $6, 264" + + - + input: + bytes: [ 0x60, 0x43, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnec $2, $3, -16" + + - + input: + bytes: [ 0x7c, 0x02, 0x20, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bitswap $4, $2" + + - + input: + bytes: [ 0x7c, 0x43, 0x22, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "align $4, $2, $3, 2" + + - + input: + bytes: [ 0x7c, 0xa1, 0x04, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cache 1, 8($5)" + + - + input: + bytes: [ 0x7c, 0xa1, 0x04, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "pref 1, 8($5)" + + - + input: + bytes: [ 0x7e, 0x42, 0xb3, 0xb6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "ll $2, -153($18)" + + - + input: + bytes: [ 0x7e, 0x6f, 0xec, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sc $15, -40($19)" + + - + input: + bytes: [ 0xc8, 0x37, 0x96, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bc 14572264" + + - + input: + bytes: [ 0xd8, 0x05, 0x01, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jic $5, 256" + + - + input: + bytes: [ 0xd8, 0xa0, 0x46, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "beqzc $5, 72264" + + - + input: + bytes: [ 0xd8, 0x5f, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "beqzc $2, -16" + + - + input: + bytes: [ 0xe8, 0x37, 0x96, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "balc 14572264" + + - + input: + bytes: [ 0xec, 0x48, 0x00, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lwpc $2, 268" + + - + input: + bytes: [ 0xec, 0x7e, 0xff, 0xff ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "auipc $3, -1" + + - + input: + bytes: [ 0xec, 0x7f, 0x00, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "aluipc $3, 56" + + - + input: + bytes: [ 0xec, 0x80, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lapc $4, 100" + + - + input: + bytes: [ 0xf8, 0x05, 0x01, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "jialc $5, 256" + + - + input: + bytes: [ 0xf8, 0xa0, 0x46, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnezc $5, 72264" + + - + input: + bytes: [ 0xf8, 0x5f, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnezc $2, -16" + + - + input: + bytes: [ 0x04, 0x17, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sigrie 5" diff --git a/tests/MC/Mips/valid-mips4-el.txt.yaml b/tests/MC/Mips/valid-mips4-el.txt.yaml new file mode 100644 index 0000000000..ca46997e3b --- /dev/null +++ b/tests/MC/Mips/valid-mips4-el.txt.yaml @@ -0,0 +1,2200 @@ +test_cases: + - + input: + bytes: [ 0x85, 0xc1, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x45, 0x82, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x20, 0xb8, 0x45, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x48, 0x3b, 0xc9, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0xe7, 0xe3, 0x18, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x00, 0x30, 0x3c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x00, 0xaa, 0x18, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0xd2, 0x66, 0x2d, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0xfe, 0xff, 0x08, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x48, 0x86, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x0a, 0x00, 0x29, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x24, 0xb8, 0x4c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x01, 0x00, 0x04, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bc1f $fcc1, 8" + + - + input: + bytes: [ 0x07, 0x00, 0x1e, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bc1fl $fcc7, 32" + + - + input: + bytes: [ 0x0d, 0x00, 0x02, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x02, 0x00, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x01, 0x00, 0x05, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bc1t $fcc1, 8" + + - + input: + bytes: [ 0xf5, 0xf7, 0x03, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x07, 0x00, 0x1f, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bc1tl $fcc7, 32" + + - + input: + bytes: [ 0x9c, 0x14, 0x11, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x9c, 0x14, 0xd0, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x41, 0x0c, 0xd3, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x20, 0x07, 0x93, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x4e, 0xf9, 0x83, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x5a, 0xfc, 0x40, 0x5d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0xe8, 0x02, 0xc0, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x7b, 0x00, 0xd2, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x46, 0xf6, 0x22, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0xfd, 0x04, 0x94, 0x57 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x08, 0x00, 0xa1, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cache 1, 8($5)" + + - + input: + bytes: [ 0x3b, 0xe0, 0x3c, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x39, 0x00, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x38, 0xf0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x38, 0x70, 0x16, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x4a, 0x18, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x8a, 0x6c, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0xce, 0xc2, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x8e, 0xa1, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x00, 0xa8, 0x51, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x00, 0xd0, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0xa1, 0xe5, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0xa1, 0x5e, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x21, 0x81, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x25, 0x7e, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.l.d $f24, $f15" + + - + input: + bytes: [ 0xe5, 0xea, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.l.s $f11, $f29" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0xa0, 0x46, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0xa0, 0x7d, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x24, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x24, 0xc5, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x2c, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0xc7, 0x93, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0xc7, 0x93, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x16, 0xee, 0xda, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x2d, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x9f, 0x46, 0x58, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x3f, 0x69, 0x73, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x1e, 0x00, 0x53, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x1f, 0x00, 0x11, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x1a, 0x00, 0x2b, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0xa7, 0x3a, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x03, 0x29, 0x0f, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x1b, 0x00, 0x2f, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x00, 0x68, 0x2c, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x00, 0x70, 0xb0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x1c, 0x00, 0xe9, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x1d, 0x00, 0xa6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0xb8, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0xb8, 0x04, 0x14, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x14, 0x00, 0x94, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0xbc, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0xbb, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0xbb, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x17, 0xe0, 0x72, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0xbf, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0xbf, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0xfa, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0xfa, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x16, 0x98, 0x86, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0xfe, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0xfe, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x2e, 0x38, 0xc8, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x2f, 0x28, 0xba, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0xc0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x18, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x8f, 0x53, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x0f, 0x4a, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x8b, 0x3e, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x0b, 0x2b, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x4d, 0xc7, 0x58, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0xf3, 0x75, 0x68, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x07, 0x40, 0x0a, 0xd6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0x43, 0xad, 0x28, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0x94, 0xde, 0xab, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0xbd, 0xa6, 0x53, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0xb3, 0x8b, 0x01, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x3f, 0x8b, 0x00, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x67, 0xe3, 0x42, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0x2a, 0x16, 0xa8, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0xf1, 0x27, 0x50, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xb7, 0xfc, 0xd2, 0xc8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0x79, 0xef, 0xf4, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x35, 0xb5, 0x80, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0x00, 0x03, 0xd1, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "lwxc1 $f12, $17($fp)" + + - + input: + bytes: [ 0x00, 0xd8, 0x07, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x10, 0x98, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x10, 0xe8, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x12, 0x88, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x06, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x86, 0xd8, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x01, 0xe0, 0x1c, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movf $gp, $8, $fcc7" + + - + input: + bytes: [ 0x91, 0x59, 0x34, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movf.d $f6, $f11, $fcc5" + + - + input: + bytes: [ 0xd1, 0x2d, 0x18, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movf.s $f23, $f5, $fcc6" + + - + input: + bytes: [ 0x21, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x21, 0xc8, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x25, 0xf0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x25, 0xc8, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x0b, 0x18, 0x30, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movn $3, $17, $16" + + - + input: + bytes: [ 0xd3, 0xae, 0x3a, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movn.d $f27, $f21, $26" + + - + input: + bytes: [ 0x13, 0x03, 0x17, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movn.s $f12, $f0, $23" + + - + input: + bytes: [ 0x01, 0x00, 0x95, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movt $zero, $20, $fcc5" + + - + input: + bytes: [ 0x11, 0x10, 0x21, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movt.d $f0, $f2, $fcc0" + + - + input: + bytes: [ 0x91, 0x17, 0x05, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movt.s $f30, $f2, $fcc1" + + - + input: + bytes: [ 0x0a, 0x28, 0xc9, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movz $5, $22, $9" + + - + input: + bytes: [ 0x12, 0xeb, 0x29, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movz.d $f12, $f29, $9" + + - + input: + bytes: [ 0x52, 0x3e, 0x03, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "movz.s $f25, $f7, $3" + + - + input: + bytes: [ 0x00, 0x48, 0x9e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x11, 0x00, 0x20, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x13, 0x00, 0xa0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x13, 0x00, 0x20, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x02, 0xa5, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x82, 0x57, 0x02, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x18, 0x00, 0xb4, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x18, 0x00, 0xa2, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x19, 0x00, 0x9a, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x19, 0x00, 0x32, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x23, 0x10, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x23, 0x10, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x87, 0x96, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x47, 0x78, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x27, 0x38, 0x07, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x25, 0x60, 0x1d, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x08, 0x00, 0xa1, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "pref 1, 8($5)" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x08, 0x0b, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x48, 0x2e, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x8c, 0x21, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0xcc, 0xe6, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x6f, 0xb2, 0xd6, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xd8, 0x49, 0x6f, 0xe2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xcd, 0xdf, 0xaf, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xcb, 0x16, 0x4c, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" + + - + input: + bytes: [ 0x1f, 0xae, 0xc7, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0x39, 0xb0, 0x8b, 0xb5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0x6e, 0x77, 0xbe, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0x75, 0x5a, 0x54, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0x09, 0x58, 0xca, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sdxc1 $f11, $10($14)" + + - + input: + bytes: [ 0xd0, 0xe5, 0xee, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0x80, 0x3c, 0x07, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x80, 0x3c, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x04, 0x38, 0x20, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x2a, 0xb8, 0x7b, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x11, 0x25, 0x51, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x55, 0xc3, 0x39, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x2b, 0xa0, 0xab, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x55, 0xc3, 0x38, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x04, 0xb4, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x04, 0x08, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0xc3, 0x8b, 0x11, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0xc3, 0x8b, 0x17, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x07, 0x88, 0xb7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0xc2, 0x11, 0x02, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x06, 0xc8, 0x94, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x40, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x22, 0xb0, 0x6c, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x36, 0x0c, 0x36, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x90, 0xe6, 0xad, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x81, 0x14, 0x30, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0xc1, 0xb5, 0x16, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x23, 0xe8, 0xd6, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x50, 0xd8, 0xbf, 0xaf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xef, 0xde, 0x06, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0x30, 0x61, 0x19, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0x7e, 0x35, 0x6f, 0xaa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0x22, 0x98, 0xd1, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0x08, 0x98, 0x4c, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "swxc1 $f19, $12($26)" + + - + input: + bytes: [ 0x34, 0x00, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x34, 0x9b, 0xa7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0xa0, 0xbb, 0xac, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x30, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x30, 0x55, 0xb3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0xa1, 0x13, 0x28, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x33, 0x90, 0xa9, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x31, 0x00, 0xdc, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0xf1, 0x5e, 0x8e, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x01, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x06, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x32, 0x00, 0xed, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x72, 0x21, 0x53, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0xbd, 0xad, 0xca, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x2c, 0xec, 0xeb, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x33, 0x00, 0x70, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x33, 0xfe, 0x1d, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x36, 0x00, 0xd1, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x76, 0xdd, 0xe8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x31, 0x8c, 0x8e, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0xc9, 0xbd, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x09, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x8d, 0x75, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x0d, 0xf7, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x26, 0x90, 0x9e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS4" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" diff --git a/tests/MC/Mips/valid-mips4.txt.yaml b/tests/MC/Mips/valid-mips4.txt.yaml new file mode 100644 index 0000000000..9fb9a54155 --- /dev/null +++ b/tests/MC/Mips/valid-mips4.txt.yaml @@ -0,0 +1,2490 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jr $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $5, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dneg $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dnegu $2, $3" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x14, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa6, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xba, 0x28, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x1c, 0xe0, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movf $gp, $8, $fcc7" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0x94, 0x00, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x11, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x30, 0x18, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movn $3, $17, $16" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x72, 0xe0, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0x02, 0x86, 0x98, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0x95, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movt $zero, $20, $fcc5" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xc8, 0x38, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x02, 0xc9, 0x28, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movz $5, $22, $9" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x02, 0xe9, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x53, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x3a, 0x00, 0x27, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "xori $zero, $16, 10002" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x2c, 0x68, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xb0, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x04, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bc1f $fcc1, 8" + + - + input: + bytes: [ 0x45, 0x05, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bc1t $fcc1, 8" + + - + input: + bytes: [ 0x45, 0x1e, 0x00, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bc1fl $fcc7, 32" + + - + input: + bytes: [ 0x45, 0x1f, 0x00, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bc1tl $fcc7, 32" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x2b, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x2e, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x6c, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xea, 0xe5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.l.s $f11, $f29" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x00, 0xff, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x03, 0x3e, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movz.s $f25, $f7, $3" + + - + input: + bytes: [ 0x46, 0x05, 0x17, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movt.s $f30, $f2, $fcc1" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x17, 0x03, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movn.s $f12, $f0, $23" + + - + input: + bytes: [ 0x46, 0x18, 0x2d, 0xd1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movf.s $f23, $f5, $fcc6" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0x0b, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x46, 0x20, 0x18, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x3e, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x7e, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.l.d $f24, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xbd, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x21, 0x10, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movt.d $f0, $f2, $fcc0" + + - + input: + bytes: [ 0x46, 0x29, 0xeb, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movz.d $f12, $f29, $9" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x34, 0x59, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movf.d $f6, $f11, $fcc5" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xae, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "movn.d $f27, $f21, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0xa0, 0x81, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x46, 0xa0, 0xf3, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x4c, 0x20, 0x01, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ldxc1 $f4, $zero($1)" + + - + input: + bytes: [ 0x4c, 0x21, 0x00, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "msub.s $f0, $f1, $f0, $f1" + + - + input: + bytes: [ 0x4d, 0xca, 0x58, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sdxc1 $f11, $10($14)" + + - + input: + bytes: [ 0x4e, 0x20, 0x3e, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "nmsub.d $f26, $f17, $f7, $f0" + + - + input: + bytes: [ 0x4f, 0x4c, 0x98, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "swxc1 $f19, $12($26)" + + - + input: + bytes: [ 0x4f, 0xd1, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lwxc1 $f12, $17($fp)" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x62, 0x9d, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x64, 0x58, 0x46, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x66, 0x73, 0x69, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x66, 0xda, 0xee, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb3, 0xc7, 0xae, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0xb5, 0x8b, 0xb0, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0xa1, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cache 1, 8($5)" + + - + input: + bytes: [ 0xbf, 0x00, 0xe2, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "cache 0, -7652($24)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x20, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "pref 0, 0($1)" + + - + input: + bytes: [ 0xcc, 0xa1, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "pref 1, 8($5)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf3, 0xaf, 0xdf, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xfd, 0x4c, 0x16, 0xcb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "recip.d $f19, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0xd6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "rsqrt.d $f3, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS4", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" diff --git a/tests/MC/Mips/valid-mips64-el.txt.yaml b/tests/MC/Mips/valid-mips64-el.txt.yaml new file mode 100644 index 0000000000..9d89955c8f --- /dev/null +++ b/tests/MC/Mips/valid-mips64-el.txt.yaml @@ -0,0 +1,2420 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x4a, 0x18, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x8a, 0x6c, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x81, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x2c, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0xc7, 0x93, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0xc7, 0x93, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x16, 0xee, 0xda, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x2d, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x9f, 0x46, 0x58, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x3f, 0x69, 0x73, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x25, 0x90, 0xd2, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x24, 0x80, 0x30, 0x73 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x1e, 0x00, 0x53, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x1f, 0x00, 0x11, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x00, 0x50, 0x38, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x00, 0x68, 0x2c, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x00, 0x50, 0xa4, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x00, 0x70, 0xb0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x1c, 0x00, 0xe9, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x1d, 0x00, 0xa6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0xb8, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0xb8, 0x04, 0x14, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x14, 0x00, 0x94, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0xbc, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0xbb, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0xbb, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x17, 0xe0, 0x72, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0xbf, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0xbf, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0xfa, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0xfa, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x16, 0x98, 0x86, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0xfe, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0xfe, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x2e, 0x38, 0xc8, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x39, 0x6c, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x39, 0x6c, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x2f, 0x28, 0xba, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x5f, 0xec, 0x6f, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0xea, 0x11, 0xce, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x8b, 0x3e, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x0b, 0x2b, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xf8, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $7" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x1b, 0x90, 0x3d, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xb9, 0xef, 0x18, 0x6b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6a, 0x89, 0x8e, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x70, 0xc6, 0xe0, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0xc5, 0x04, 0xb6, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "luxc1 $f19, $22($21)" + + - + input: + bytes: [ 0xea, 0xa1, 0x73, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0x00, 0x03, 0xd1, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwxc1 $f12, $17($fp)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x25, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x2d, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x08, 0x0b, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x48, 0x2e, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xcd, 0xdf, 0xaf, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xcb, 0x16, 0x4c, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x1f, 0xae, 0xc7, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0x39, 0xb0, 0x8b, 0xb5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0x09, 0x58, 0xca, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdxc1 $f11, $10($14)" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x0d, 0x60, 0xbb, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "suxc1 $f12, $27($13)" + + - + input: + bytes: [ 0x08, 0x98, 0x4c, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swxc1 $f19, $12($26)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc9, 0xbd, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x09, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3b, 0xe8, 0x05, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x02, 0x00, 0x61, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0x04, 0x00, 0x43, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xca, 0x23, 0xc8, 0xc8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xcd, 0x7c, 0x4b, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $11, $26, 31949" + + - + input: + bytes: [ 0x2d, 0xd0, 0x2b, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddu $26, $1, $11" + + - + input: + bytes: [ 0x1e, 0x00, 0x56, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $22" + + - + input: + bytes: [ 0x1f, 0x00, 0x38, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ddivu $zero, $9, $24" + + - + input: + bytes: [ 0x00, 0x70, 0x22, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmfc1 $2, $f14" + + - + input: + bytes: [ 0x00, 0x28, 0xb7, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmtc1 $23, $f5" + + - + input: + bytes: [ 0x1c, 0x00, 0x7a, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmult $11, $26" + + - + input: + bytes: [ 0x1d, 0x00, 0xed, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmultu $23, $13" + + - + input: + bytes: [ 0x78, 0x1c, 0x18, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsll $3, $24, 17" + + - + input: + bytes: [ 0x14, 0xe0, 0x1b, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsllv $gp, $27, $24" + + - + input: + bytes: [ 0xbb, 0x0f, 0x01, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra $1, $1, 30" + + - + input: + bytes: [ 0x17, 0x08, 0xc1, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrav $1, $1, $fp" + + - + input: + bytes: [ 0x3a, 0x56, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl $10, $gp, 24" + + - + input: + bytes: [ 0x16, 0xe0, 0xea, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrlv $gp, $10, $23" + + - + input: + bytes: [ 0x2f, 0xe0, 0x78, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsubu $gp, $27, $24" + + - + input: + bytes: [ 0xcd, 0xc4, 0x3b, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lw $27, -15155($1)" + + - + input: + bytes: [ 0x01, 0x00, 0x01, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lui $1, 1" + + - + input: + bytes: [ 0x2e, 0xf9, 0x63, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwu $3, -1746($3)" + + - + input: + bytes: [ 0x01, 0x00, 0x1f, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lui $ra, 1" + + - + input: + bytes: [ 0xc9, 0xc4, 0x3a, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sw $26, -15159($1)" + + - + input: + bytes: [ 0x76, 0x0f, 0x1a, 0xdc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ld $26, 3958($zero)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0xfc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sd $6, 17767($zero)" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x81, 0x00, 0x42, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldxc1 $f2, $2($10)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" diff --git a/tests/MC/Mips/valid-mips64-xfail.txt.yaml b/tests/MC/Mips/valid-mips64-xfail.txt.yaml new file mode 100644 index 0000000000..4fb4de0112 --- /dev/null +++ b/tests/MC/Mips/valid-mips64-xfail.txt.yaml @@ -0,0 +1,150 @@ +test_cases: + - + input: + bytes: [ 0x46, 0x11, 0xc5, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.eq.s $fcc5, $f24, $f17" + + - + input: + bytes: [ 0x46, 0x07, 0xf4, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.f.s $fcc4, $f30, $f7" + + - + input: + bytes: [ 0x46, 0x04, 0xc6, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.le.s $fcc6, $f24, $f4" + + - + input: + bytes: [ 0x46, 0x0e, 0x8a, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.lt.s $fcc2, $f17, $f14" + + - + input: + bytes: [ 0x46, 0x08, 0x5b, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.nge.s $fcc3, $f11, $f8" + + - + input: + bytes: [ 0x46, 0x17, 0xfa, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ngl.s $fcc2, $f31, $f23" + + - + input: + bytes: [ 0x46, 0x17, 0x92, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ngle.s $fcc2, $f18, $f23" + + - + input: + bytes: [ 0x46, 0x0d, 0x45, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ngt.s $fcc5, $f8, $f13" + + - + input: + bytes: [ 0x46, 0x14, 0x3b, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ole.s $fcc3, $f7, $f20" + + - + input: + bytes: [ 0x46, 0x07, 0xa6, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.olt.s $fcc6, $f20, $f7" + + - + input: + bytes: [ 0x46, 0x19, 0x0f, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.seq.s $fcc7, $f1, $f25" + + - + input: + bytes: [ 0x46, 0x1e, 0x1e, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ueq.s $fcc6, $f3, $f30" + + - + input: + bytes: [ 0x46, 0x1e, 0xaf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ule.s $fcc7, $f21, $f30" + + - + input: + bytes: [ 0x46, 0x0a, 0xc7, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ult.s $fcc7, $f24, $f10" + + - + input: + bytes: [ 0x46, 0x04, 0xf1, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.un.s $fcc1, $f30, $f4" diff --git a/tests/MC/Mips/valid-mips64.txt.yaml b/tests/MC/Mips/valid-mips64.txt.yaml new file mode 100644 index 0000000000..27056a05ac --- /dev/null +++ b/tests/MC/Mips/valid-mips64.txt.yaml @@ -0,0 +1,4350 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jr $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $5, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x01, 0x0f, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra $1, $1, 30" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dneg $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dnegu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x14, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x18, 0x1c, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsll $3, $24, 17" + + - + input: + bytes: [ 0x00, 0x1c, 0x56, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrl $10, $gp, 24" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x2b, 0xd0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddu $26, $1, $11" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa6, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xba, 0x28, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x38, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ddivu $zero, $9, $24" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7a, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmult $11, $26" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0x94, 0x00, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x11, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x72, 0xe0, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0x02, 0x86, 0x98, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xc8, 0x38, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x02, 0xe9, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x02, 0xea, 0xe0, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrlv $gp, $10, $23" + + - + input: + bytes: [ 0x02, 0xed, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmultu $23, $13" + + - + input: + bytes: [ 0x03, 0x1b, 0xe0, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsllv $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x53, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x03, 0x56, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $22" + + - + input: + bytes: [ 0x03, 0x78, 0xe0, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsubu $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xc1, 0x08, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dsrav $1, $1, $fp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x01, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lui $1, 1" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x3c, 0x1f, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lui $ra, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x38, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x40, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x22, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmfc1 $2, $f14" + + - + input: + bytes: [ 0x44, 0x2c, 0x68, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xb0, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x44, 0xb7, 0x28, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmtc1 $23, $f5" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x2b, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x2e, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x46, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.l.s $f26, $f8" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x6c, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x00, 0xff, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x0b, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x46, 0x20, 0x18, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x3e, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xbd, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "recip.d $f19, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0xd6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "rsqrt.d $f3, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x48, 0x20, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmfc2 $zero, $10, 0" + + - + input: + bytes: [ 0x48, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dmtc2 $4, $10, 0" + + - + input: + bytes: [ 0x4d, 0x0c, 0xe0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "madd.d $f0, $f8, $f28, $f12" + + - + input: + bytes: [ 0x4d, 0xbb, 0x0d, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "madd.s $f23, $f13, $f1, $f27" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x46, 0xa0, 0x81, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x46, 0xa0, 0xf3, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x42, 0x00, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldxc1 $f2, $2($10)" + + - + input: + bytes: [ 0x4d, 0xbb, 0x60, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "suxc1 $f12, $27($13)" + + - + input: + bytes: [ 0x4d, 0xca, 0x58, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdxc1 $f11, $10($14)" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0xb6, 0x04, 0xc5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "luxc1 $f19, $22($21)" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0x4c, 0x98, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swxc1 $f19, $12($26)" + + - + input: + bytes: [ 0x4f, 0xd1, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwxc1 $f12, $17($fp)" + + - + input: + bytes: [ 0x62, 0x9d, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x62, 0x9d, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x64, 0x58, 0x46, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x65, 0x6f, 0xec, 0x5f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0x65, 0xce, 0x11, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x66, 0x73, 0x69, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x66, 0xda, 0xee, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x67, 0x4b, 0x7c, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $11, $26, 31949" + + - + input: + bytes: [ 0x67, 0xbd, 0xff, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "daddiu $sp, $sp, -32" + + - + input: + bytes: [ 0x6b, 0x18, 0xef, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6e, 0x8e, 0x89, 0x6a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xd2, 0x90, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x73, 0x30, 0x80, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0x3b, 0xc4, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lw $27, -15155($1)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0x9c, 0x63, 0xf9, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwu $3, -1746($3)" + + - + input: + bytes: [ 0x9c, 0x73, 0xa1, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0x3a, 0xc4, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sw $26, -15159($1)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb3, 0xc7, 0xae, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0xb5, 0x8b, 0xb0, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd3, 0xe0, 0xc6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xd9, 0x03, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ldc2 $3, 9162($8)" + + - + input: + bytes: [ 0xdc, 0x1a, 0x0f, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ld $26, 3958($zero)" + + - + input: + bytes: [ 0xde, 0x3d, 0x90, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf3, 0xaf, 0xdf, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xf8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdc2 $9, 9158($7)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xfc, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sd $6, 17767($zero)" + + - + input: + bytes: [ 0xfd, 0x4c, 0x16, 0xcb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" diff --git a/tests/MC/Mips/valid-mips64r2-el.txt.yaml b/tests/MC/Mips/valid-mips64r2-el.txt.yaml new file mode 100644 index 0000000000..1e39241a72 --- /dev/null +++ b/tests/MC/Mips/valid-mips64r2-el.txt.yaml @@ -0,0 +1,5360 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x00, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x4a, 0x18, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x8a, 0x6c, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x81, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x2c, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0xc7, 0x93, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0xc7, 0x93, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x16, 0xee, 0xda, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x2d, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x9f, 0x46, 0x58, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x3f, 0x69, 0x73, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x25, 0x90, 0xd2, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x24, 0x80, 0x30, 0x73 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x1e, 0x00, 0x53, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x1f, 0x00, 0x11, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x00, 0x50, 0x38, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x00, 0x68, 0x2c, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x00, 0x50, 0xa4, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x00, 0x70, 0xb0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x1c, 0x00, 0xe9, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x1d, 0x00, 0xa6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0xb8, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0xb8, 0x04, 0x14, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x14, 0x00, 0x94, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0xbc, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0xbc, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0x14, 0x00, 0x94, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0xbb, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0xbb, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x17, 0xe0, 0x72, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0xbf, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0xbf, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0xfa, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0xfa, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x16, 0x98, 0x86, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0xfe, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0xfe, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x2e, 0x38, 0xc8, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0xa4, 0x18, 0x0e, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsbh $3, $14" + + - + input: + bytes: [ 0x64, 0x11, 0x1d, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dshd $2, $sp" + + - + input: + bytes: [ 0x39, 0x6c, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x39, 0x6c, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x2f, 0x28, 0xba, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x5f, 0xec, 0x6f, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0xea, 0x11, 0xce, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0xfa, 0x0b, 0x21, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $1, $1, 15" + + - + input: + bytes: [ 0xfa, 0x0b, 0x2e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $1, $14, 15" + + - + input: + bytes: [ 0xfe, 0x0b, 0x21, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr32 $1, $1, 15" + + - + input: + bytes: [ 0xfe, 0x0b, 0x2e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr32 $1, $14, 15" + + - + input: + bytes: [ 0x56, 0x08, 0xee, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotrv $1, $14, $15" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x8b, 0x3e, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x0b, 0x2b, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x1b, 0x90, 0x3d, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xb9, 0xef, 0x18, 0x6b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6a, 0x89, 0x8e, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x70, 0xc6, 0xe0, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0xea, 0xa1, 0x73, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x25, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x2d, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x02, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x08, 0x0b, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x48, 0x2e, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xcd, 0xdf, 0xaf, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xcb, 0x16, 0x4c, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x1f, 0xae, 0xc7, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0x39, 0xb0, 0x8b, 0xb5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x01, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0xc9, 0xbd, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x09, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0xcd, 0x7c, 0x4b, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $11, $26, 31949" + + - + input: + bytes: [ 0x2d, 0xd0, 0x2b, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddu $26, $1, $11" + + - + input: + bytes: [ 0x1e, 0x00, 0x56, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $22" + + - + input: + bytes: [ 0x1f, 0x00, 0x38, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddivu $zero, $9, $24" + + - + input: + bytes: [ 0x00, 0x70, 0x22, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc1 $2, $f14" + + - + input: + bytes: [ 0x00, 0x28, 0xb7, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc1 $23, $f5" + + - + input: + bytes: [ 0x1c, 0x00, 0x7a, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmult $11, $26" + + - + input: + bytes: [ 0x1d, 0x00, 0xed, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmultu $23, $13" + + - + input: + bytes: [ 0x78, 0x1c, 0x18, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $3, $24, 17" + + - + input: + bytes: [ 0x14, 0xe0, 0x1b, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsllv $gp, $27, $24" + + - + input: + bytes: [ 0xbb, 0x0f, 0x01, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $1, $1, 30" + + - + input: + bytes: [ 0x17, 0x08, 0xc1, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrav $1, $1, $fp" + + - + input: + bytes: [ 0x3a, 0x56, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $10, $gp, 24" + + - + input: + bytes: [ 0x16, 0xe0, 0xea, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrlv $gp, $10, $23" + + - + input: + bytes: [ 0x2f, 0xe0, 0x78, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsubu $gp, $27, $24" + + - + input: + bytes: [ 0xcd, 0xc4, 0x3b, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $27, -15155($1)" + + - + input: + bytes: [ 0x01, 0x00, 0x01, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $1, 1" + + - + input: + bytes: [ 0x2e, 0xf9, 0x63, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwu $3, -1746($3)" + + - + input: + bytes: [ 0x01, 0x00, 0x1f, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $ra, 1" + + - + input: + bytes: [ 0xc9, 0xc4, 0x3a, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $26, -15159($1)" + + - + input: + bytes: [ 0x76, 0x0f, 0x1a, 0xdc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ld $26, 3958($zero)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0xfc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sd $6, 17767($zero)" + + - + input: + bytes: [ 0x25, 0x48, 0x09, 0x73 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclo $9, $24" + + - + input: + bytes: [ 0x24, 0xd0, 0x3a, 0x71 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclz $26, $9" + + - + input: + bytes: [ 0x43, 0xf7, 0x87, 0x7f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dext $7, $gp, 29, 31" + + - + input: + bytes: [ 0xc7, 0x7b, 0x94, 0x7f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dins $20, $gp, 15, 1" + + - + input: + bytes: [ 0xa4, 0x38, 0x1c, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsbh $7, $gp" + + - + input: + bytes: [ 0x64, 0x19, 0x0e, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dshd $3, $14" + + - + input: + bytes: [ 0xba, 0xa1, 0x3b, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $20, $27, 6" + + - + input: + bytes: [ 0x56, 0xc0, 0xb7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotrv $24, $23, $5" + + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x00, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x4a, 0x18, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x8a, 0x6c, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x81, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x2c, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0xc7, 0x93, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0xc7, 0x93, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x16, 0xee, 0xda, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x2d, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x9f, 0x46, 0x58, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x3f, 0x69, 0x73, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x25, 0x90, 0xd2, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x24, 0x80, 0x30, 0x73 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x1e, 0x00, 0x53, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x1f, 0x00, 0x11, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x00, 0x50, 0x38, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x00, 0x68, 0x2c, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x00, 0x50, 0xa4, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x00, 0x70, 0xb0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x1c, 0x00, 0xe9, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x1d, 0x00, 0xa6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0xb8, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0xb8, 0x04, 0x14, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x14, 0x00, 0x94, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0xbc, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0xbb, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0xbb, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x17, 0xe0, 0x72, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0xbf, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0xbf, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0xfa, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0xfa, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x16, 0x98, 0x86, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0xfe, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0xfe, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x2e, 0x38, 0xc8, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0xa4, 0x18, 0x0e, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsbh $3, $14" + + - + input: + bytes: [ 0x64, 0x11, 0x1d, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dshd $2, $sp" + + - + input: + bytes: [ 0x39, 0x6c, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x39, 0x6c, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x2f, 0x28, 0xba, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x5f, 0xec, 0x6f, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0xea, 0x11, 0xce, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0xfa, 0x0b, 0x21, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $1, $1, 15" + + - + input: + bytes: [ 0xfa, 0x0b, 0x2e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $1, $14, 15" + + - + input: + bytes: [ 0xfe, 0x0b, 0x21, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr32 $1, $1, 15" + + - + input: + bytes: [ 0xfe, 0x0b, 0x2e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr32 $1, $14, 15" + + - + input: + bytes: [ 0x56, 0x08, 0xee, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotrv $1, $14, $15" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x8b, 0x3e, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x0b, 0x2b, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x1b, 0x90, 0x3d, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xb9, 0xef, 0x18, 0x6b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6a, 0x89, 0x8e, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x70, 0xc6, 0xe0, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0xea, 0xa1, 0x73, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x25, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x2d, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x02, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x08, 0x0b, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x48, 0x2e, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xcd, 0xdf, 0xaf, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xcb, 0x16, 0x4c, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x1f, 0xae, 0xc7, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0x39, 0xb0, 0x8b, 0xb5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x01, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0xc9, 0xbd, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x09, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0xcd, 0x7c, 0x4b, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $11, $26, 31949" + + - + input: + bytes: [ 0x2d, 0xd0, 0x2b, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddu $26, $1, $11" + + - + input: + bytes: [ 0x1e, 0x00, 0x56, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $22" + + - + input: + bytes: [ 0x1f, 0x00, 0x38, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddivu $zero, $9, $24" + + - + input: + bytes: [ 0x00, 0x70, 0x22, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc1 $2, $f14" + + - + input: + bytes: [ 0x00, 0x28, 0xb7, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc1 $23, $f5" + + - + input: + bytes: [ 0x1c, 0x00, 0x7a, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmult $11, $26" + + - + input: + bytes: [ 0x1d, 0x00, 0xed, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmultu $23, $13" + + - + input: + bytes: [ 0x78, 0x1c, 0x18, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $3, $24, 17" + + - + input: + bytes: [ 0x14, 0xe0, 0x1b, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsllv $gp, $27, $24" + + - + input: + bytes: [ 0xbb, 0x0f, 0x01, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $1, $1, 30" + + - + input: + bytes: [ 0x17, 0x08, 0xc1, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrav $1, $1, $fp" + + - + input: + bytes: [ 0x3a, 0x56, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $10, $gp, 24" + + - + input: + bytes: [ 0x16, 0xe0, 0xea, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrlv $gp, $10, $23" + + - + input: + bytes: [ 0x2f, 0xe0, 0x78, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsubu $gp, $27, $24" + + - + input: + bytes: [ 0xcd, 0xc4, 0x3b, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $27, -15155($1)" + + - + input: + bytes: [ 0x01, 0x00, 0x01, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $1, 1" + + - + input: + bytes: [ 0x2e, 0xf9, 0x63, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwu $3, -1746($3)" + + - + input: + bytes: [ 0x01, 0x00, 0x1f, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $ra, 1" + + - + input: + bytes: [ 0xc9, 0xc4, 0x3a, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $26, -15159($1)" + + - + input: + bytes: [ 0x76, 0x0f, 0x1a, 0xdc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ld $26, 3958($zero)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0xfc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sd $6, 17767($zero)" + + - + input: + bytes: [ 0x25, 0x48, 0x09, 0x73 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclo $9, $24" + + - + input: + bytes: [ 0x24, 0xd0, 0x3a, 0x71 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclz $26, $9" + + - + input: + bytes: [ 0x43, 0xf7, 0x87, 0x7f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dext $7, $gp, 29, 31" + + - + input: + bytes: [ 0xc7, 0x7b, 0x94, 0x7f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dins $20, $gp, 15, 1" + + - + input: + bytes: [ 0xa4, 0x38, 0x1c, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsbh $7, $gp" + + - + input: + bytes: [ 0x64, 0x19, 0x0e, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dshd $3, $14" + + - + input: + bytes: [ 0xba, 0xa1, 0x3b, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $20, $27, 6" + + - + input: + bytes: [ 0x56, 0xc0, 0xb7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotrv $24, $23, $5" diff --git a/tests/MC/Mips/valid-mips64r2.txt.yaml b/tests/MC/Mips/valid-mips64r2.txt.yaml new file mode 100644 index 0000000000..855dd869d1 --- /dev/null +++ b/tests/MC/Mips/valid-mips64r2.txt.yaml @@ -0,0 +1,9440 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jr $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $5, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x01, 0x0f, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $1, $1, 30" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dneg $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dnegu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x14, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x18, 0x1c, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $3, $24, 17" + + - + input: + bytes: [ 0x00, 0x1c, 0x56, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $10, $gp, 24" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x21, 0x0b, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $1, $1, 15" + + - + input: + bytes: [ 0x00, 0x21, 0x0b, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr32 $1, $1, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x2b, 0xd0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddu $26, $1, $11" + + - + input: + bytes: [ 0x00, 0x2e, 0x0b, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $1, $14, 15" + + - + input: + bytes: [ 0x00, 0x2e, 0x0b, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr32 $1, $14, 15" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x3b, 0xa1, 0xba ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $20, $27, 6" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa6, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xb7, 0xc0, 0x56 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotrv $24, $23, $5" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xba, 0x28, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x38, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddivu $zero, $9, $24" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7a, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmult $11, $26" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0x94, 0x00, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x01, 0xee, 0x08, 0x56 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotrv $1, $14, $15" + + - + input: + bytes: [ 0x02, 0x11, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x72, 0xe0, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0x02, 0x86, 0x98, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xc8, 0x38, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x02, 0xe9, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x02, 0xea, 0xe0, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrlv $gp, $10, $23" + + - + input: + bytes: [ 0x02, 0xed, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmultu $23, $13" + + - + input: + bytes: [ 0x03, 0x1b, 0xe0, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsllv $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x53, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x03, 0x56, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $22" + + - + input: + bytes: [ 0x03, 0x78, 0xe0, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsubu $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xc1, 0x08, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrav $1, $1, $fp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x7f, 0x47, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "synci 18368($3)" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x01, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $1, 1" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x3c, 0x1f, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $ra, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x38, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x40, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x22, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc1 $2, $f14" + + - + input: + bytes: [ 0x44, 0x2c, 0x68, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xb0, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x44, 0xb7, 0x28, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc1 $23, $f5" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x2b, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x2e, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x46, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f26, $f8" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x6c, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x00, 0xff, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x0b, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x46, 0x20, 0x18, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x3e, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xbd, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x48, 0x20, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc2 $zero, $10, 0" + + - + input: + bytes: [ 0x48, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc2 $4, $10, 0" + + - + input: + bytes: [ 0x4d, 0x0c, 0xe0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd.d $f0, $f8, $f28, $f12" + + - + input: + bytes: [ 0x4d, 0xbb, 0x0d, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd.s $f23, $f13, $f1, $f27" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x46, 0xa0, 0x81, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x46, 0xa0, 0xf3, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x42, 0x00, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f2, $2($10)" + + - + input: + bytes: [ 0x4d, 0xbb, 0x60, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "suxc1 $f12, $27($13)" + + - + input: + bytes: [ 0x4d, 0xca, 0x58, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f11, $10($14)" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0xb6, 0x04, 0xc5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "luxc1 $f19, $22($21)" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0x4c, 0x98, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swxc1 $f19, $12($26)" + + - + input: + bytes: [ 0x4f, 0xd1, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f12, $17($fp)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x62, 0x9d, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x62, 0x9d, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x64, 0x58, 0x46, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x65, 0x6f, 0xec, 0x5f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0x65, 0xce, 0x11, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x66, 0x73, 0x69, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x66, 0xda, 0xee, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x67, 0x4b, 0x7c, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $11, $26, 31949" + + - + input: + bytes: [ 0x67, 0xbd, 0xff, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $sp, $sp, -32" + + - + input: + bytes: [ 0x6b, 0x18, 0xef, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6e, 0x8e, 0x89, 0x6a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xd2, 0x90, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x71, 0x3a, 0xd0, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclz $26, $9" + + - + input: + bytes: [ 0x73, 0x09, 0x48, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclo $9, $24" + + - + input: + bytes: [ 0x73, 0x30, 0x80, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7c, 0x0e, 0x18, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsbh $3, $14" + + - + input: + bytes: [ 0x7c, 0x0e, 0x19, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dshd $3, $14" + + - + input: + bytes: [ 0x7c, 0x1c, 0x38, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsbh $7, $gp" + + - + input: + bytes: [ 0x7c, 0x1d, 0x11, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dshd $2, $sp" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x7f, 0x87, 0xf7, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dext $7, $gp, 29, 31" + + - + input: + bytes: [ 0x7f, 0x94, 0x7b, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dins $20, $gp, 15, 1" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0x3b, 0xc4, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $27, -15155($1)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0x9c, 0x63, 0xf9, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwu $3, -1746($3)" + + - + input: + bytes: [ 0x9c, 0x73, 0xa1, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0x3a, 0xc4, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $26, -15159($1)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb3, 0xc7, 0xae, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0xb5, 0x8b, 0xb0, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd3, 0xe0, 0xc6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xd9, 0x03, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc2 $3, 9162($8)" + + - + input: + bytes: [ 0xdc, 0x1a, 0x0f, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ld $26, 3958($zero)" + + - + input: + bytes: [ 0xde, 0x3d, 0x90, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf3, 0xaf, 0xdf, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xf8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc2 $9, 9158($7)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xfc, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sd $6, 17767($zero)" + + - + input: + bytes: [ 0xfd, 0x4c, 0x16, 0xcb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jr $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x01, 0x0f, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $1, $1, 30" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dneg $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dnegu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x14, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x18, 0x1c, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsll $3, $24, 17" + + - + input: + bytes: [ 0x00, 0x1c, 0x56, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrl $10, $gp, 24" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x21, 0x0b, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $1, $1, 15" + + - + input: + bytes: [ 0x00, 0x21, 0x0b, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr32 $1, $1, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x2b, 0xd0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddu $26, $1, $11" + + - + input: + bytes: [ 0x00, 0x2e, 0x0b, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $1, $14, 15" + + - + input: + bytes: [ 0x00, 0x2e, 0x0b, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr32 $1, $14, 15" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x3b, 0xa1, 0xba ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotr $20, $27, 6" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa6, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xb7, 0xc0, 0x56 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotrv $24, $23, $5" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xba, 0x28, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x38, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddivu $zero, $9, $24" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7a, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmult $11, $26" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0x94, 0x00, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x01, 0xee, 0x08, 0x56 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "drotrv $1, $14, $15" + + - + input: + bytes: [ 0x02, 0x11, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x72, 0xe0, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0x02, 0x86, 0x98, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xc8, 0x38, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x02, 0xe9, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x02, 0xea, 0xe0, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrlv $gp, $10, $23" + + - + input: + bytes: [ 0x02, 0xed, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmultu $23, $13" + + - + input: + bytes: [ 0x03, 0x1b, 0xe0, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsllv $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x53, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x03, 0x56, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $22" + + - + input: + bytes: [ 0x03, 0x78, 0xe0, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsubu $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xc1, 0x08, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsrav $1, $1, $fp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x7f, 0x47, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "synci 18368($3)" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x01, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $1, 1" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x3c, 0x1f, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lui $ra, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x38, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x40, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x22, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc1 $2, $f14" + + - + input: + bytes: [ 0x44, 0x2c, 0x68, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xb0, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x44, 0xb7, 0x28, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc1 $23, $f5" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x2b, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x2e, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x46, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.s $f26, $f8" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x6c, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x00, 0xff, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x0b, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x46, 0x20, 0x18, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x3e, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xbd, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x48, 0x20, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmfc2 $zero, $10, 0" + + - + input: + bytes: [ 0x48, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dmtc2 $4, $10, 0" + + - + input: + bytes: [ 0x4d, 0x0c, 0xe0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd.d $f0, $f8, $f28, $f12" + + - + input: + bytes: [ 0x4d, 0xbb, 0x0d, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd.s $f23, $f13, $f1, $f27" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x46, 0xa0, 0x81, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x46, 0xa0, 0xf3, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x42, 0x00, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f2, $2($10)" + + - + input: + bytes: [ 0x4d, 0xbb, 0x60, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "suxc1 $f12, $27($13)" + + - + input: + bytes: [ 0x4d, 0xca, 0x58, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f11, $10($14)" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0xb6, 0x04, 0xc5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "luxc1 $f19, $22($21)" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0x4c, 0x98, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swxc1 $f19, $12($26)" + + - + input: + bytes: [ 0x4f, 0xd1, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwxc1 $f12, $17($fp)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x62, 0x9d, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x62, 0x9d, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x64, 0x58, 0x46, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x65, 0x6f, 0xec, 0x5f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0x65, 0xce, 0x11, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x66, 0x73, 0x69, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x66, 0xda, 0xee, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x67, 0x4b, 0x7c, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $11, $26, 31949" + + - + input: + bytes: [ 0x67, 0xbd, 0xff, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "daddiu $sp, $sp, -32" + + - + input: + bytes: [ 0x6b, 0x18, 0xef, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6e, 0x8e, 0x89, 0x6a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xd2, 0x90, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x71, 0x3a, 0xd0, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclz $26, $9" + + - + input: + bytes: [ 0x73, 0x09, 0x48, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclo $9, $24" + + - + input: + bytes: [ 0x73, 0x30, 0x80, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7c, 0x0e, 0x18, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsbh $3, $14" + + - + input: + bytes: [ 0x7c, 0x0e, 0x19, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dshd $3, $14" + + - + input: + bytes: [ 0x7c, 0x1c, 0x38, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dsbh $7, $gp" + + - + input: + bytes: [ 0x7c, 0x1d, 0x11, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dshd $2, $sp" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x7f, 0x87, 0xf7, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dext $7, $gp, 29, 31" + + - + input: + bytes: [ 0x7f, 0x94, 0x7b, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "dins $20, $gp, 15, 1" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0x3b, 0xc4, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $27, -15155($1)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0x9c, 0x63, 0xf9, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwu $3, -1746($3)" + + - + input: + bytes: [ 0x9c, 0x73, 0xa1, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0x3a, 0xc4, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $26, -15159($1)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb3, 0xc7, 0xae, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0xb5, 0x8b, 0xb0, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd3, 0xe0, 0xc6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xd9, 0x03, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ldc2 $3, 9162($8)" + + - + input: + bytes: [ 0xdc, 0x1a, 0x0f, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ld $26, 3958($zero)" + + - + input: + bytes: [ 0xde, 0x3d, 0x90, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf3, 0xaf, 0xdf, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xf8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc2 $9, 9158($7)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xfc, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sd $6, 17767($zero)" + + - + input: + bytes: [ 0xfd, 0x4c, 0x16, 0xcb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" diff --git a/tests/MC/Mips/valid-mips64r3-el.txt.yaml b/tests/MC/Mips/valid-mips64r3-el.txt.yaml new file mode 100644 index 0000000000..cc69d2d7cf --- /dev/null +++ b/tests/MC/Mips/valid-mips64r3-el.txt.yaml @@ -0,0 +1,2380 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x00, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x4a, 0x18, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x8a, 0x6c, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x81, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x2c, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0xc7, 0x93, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0xc7, 0x93, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x16, 0xee, 0xda, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x2d, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x9f, 0x46, 0x58, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x3f, 0x69, 0x73, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x25, 0x90, 0xd2, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x24, 0x80, 0x30, 0x73 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x1e, 0x00, 0x53, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x1f, 0x00, 0x11, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x00, 0x50, 0x38, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x00, 0x68, 0x2c, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x00, 0x50, 0xa4, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x00, 0x70, 0xb0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x1c, 0x00, 0xe9, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x1d, 0x00, 0xa6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0xb8, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0xb8, 0x04, 0x14, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x14, 0x00, 0x94, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0xbc, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0xbb, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0xbb, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x17, 0xe0, 0x72, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0xbf, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0xbf, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0xfa, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0xfa, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x16, 0x98, 0x86, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0xfe, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0xfe, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x2e, 0x38, 0xc8, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0xa4, 0x18, 0x0e, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsbh $3, $14" + + - + input: + bytes: [ 0x64, 0x11, 0x1d, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dshd $2, $sp" + + - + input: + bytes: [ 0x39, 0x6c, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x39, 0x6c, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x2f, 0x28, 0xba, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x5f, 0xec, 0x6f, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0xea, 0x11, 0xce, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0xfa, 0x0b, 0x21, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotr $1, $1, 15" + + - + input: + bytes: [ 0xfa, 0x0b, 0x2e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotr $1, $14, 15" + + - + input: + bytes: [ 0xfe, 0x0b, 0x21, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotr32 $1, $1, 15" + + - + input: + bytes: [ 0xfe, 0x0b, 0x2e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotr32 $1, $14, 15" + + - + input: + bytes: [ 0x56, 0x08, 0xee, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotrv $1, $14, $15" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x8b, 0x3e, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x0b, 0x2b, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xf8, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $7" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x1b, 0x90, 0x3d, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xb9, 0xef, 0x18, 0x6b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6a, 0x89, 0x8e, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x70, 0xc6, 0xe0, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0xea, 0xa1, 0x73, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x25, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x2d, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x02, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x08, 0x0b, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x48, 0x2e, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xcd, 0xdf, 0xaf, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xcb, 0x16, 0x4c, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x1f, 0xae, 0xc7, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0x39, 0xb0, 0x8b, 0xb5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x01, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0xc9, 0xbd, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x09, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" diff --git a/tests/MC/Mips/valid-mips64r3.txt.yaml b/tests/MC/Mips/valid-mips64r3.txt.yaml new file mode 100644 index 0000000000..3b9c3c607f --- /dev/null +++ b/tests/MC/Mips/valid-mips64r3.txt.yaml @@ -0,0 +1,4740 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jr $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $5, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x01, 0x0f, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsra $1, $1, 30" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dneg $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dnegu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x14, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x18, 0x1c, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsll $3, $24, 17" + + - + input: + bytes: [ 0x00, 0x1c, 0x56, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrl $10, $gp, 24" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x21, 0x0b, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotr $1, $1, 15" + + - + input: + bytes: [ 0x00, 0x21, 0x0b, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotr32 $1, $1, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x2b, 0xd0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddu $26, $1, $11" + + - + input: + bytes: [ 0x00, 0x2e, 0x0b, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotr $1, $14, 15" + + - + input: + bytes: [ 0x00, 0x2e, 0x0b, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotr32 $1, $14, 15" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x3b, 0xa1, 0xba ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotr $20, $27, 6" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa6, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xb7, 0xc0, 0x56 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotrv $24, $23, $5" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xba, 0x28, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x38, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ddivu $zero, $9, $24" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7a, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmult $11, $26" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0x94, 0x00, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x01, 0xee, 0x08, 0x56 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "drotrv $1, $14, $15" + + - + input: + bytes: [ 0x02, 0x11, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x72, 0xe0, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0x02, 0x86, 0x98, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xc8, 0x38, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x02, 0xe9, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x02, 0xea, 0xe0, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrlv $gp, $10, $23" + + - + input: + bytes: [ 0x02, 0xed, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmultu $23, $13" + + - + input: + bytes: [ 0x03, 0x1b, 0xe0, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsllv $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x53, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x03, 0x56, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $22" + + - + input: + bytes: [ 0x03, 0x78, 0xe0, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsubu $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xc1, 0x08, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsrav $1, $1, $fp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x7f, 0x47, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "synci 18368($3)" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3a, 0x00, 0x3a, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "xori $zero, $16, 14881" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x01, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lui $1, 1" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x3c, 0x1f, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lui $ra, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x38, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x40, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x22, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmfc1 $2, $f14" + + - + input: + bytes: [ 0x44, 0x2c, 0x68, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xb0, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x44, 0xb7, 0x28, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmtc1 $23, $f5" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x2b, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x2e, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x46, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.l.s $f26, $f8" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x6c, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x00, 0xff, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x0b, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x46, 0x20, 0x18, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x3e, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xbd, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x48, 0x20, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmfc2 $zero, $10, 0" + + - + input: + bytes: [ 0x48, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dmtc2 $4, $10, 0" + + - + input: + bytes: [ 0x4d, 0x0c, 0xe0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "madd.d $f0, $f8, $f28, $f12" + + - + input: + bytes: [ 0x4d, 0xbb, 0x0d, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "madd.s $f23, $f13, $f1, $f27" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x46, 0xa0, 0x81, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x46, 0xa0, 0xf3, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x42, 0x00, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldxc1 $f2, $2($10)" + + - + input: + bytes: [ 0x4d, 0xbb, 0x60, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "suxc1 $f12, $27($13)" + + - + input: + bytes: [ 0x4d, 0xca, 0x58, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdxc1 $f11, $10($14)" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0xb6, 0x04, 0xc5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "luxc1 $f19, $22($21)" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0x4c, 0x98, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swxc1 $f19, $12($26)" + + - + input: + bytes: [ 0x4f, 0xd1, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwxc1 $f12, $17($fp)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x62, 0x9d, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x62, 0x9d, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x64, 0x58, 0x46, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x65, 0x6f, 0xec, 0x5f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0x65, 0xce, 0x11, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x66, 0x73, 0x69, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x66, 0xda, 0xee, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x67, 0x4b, 0x7c, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $11, $26, 31949" + + - + input: + bytes: [ 0x67, 0xbd, 0xff, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "daddiu $sp, $sp, -32" + + - + input: + bytes: [ 0x6b, 0x18, 0xef, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6e, 0x8e, 0x89, 0x6a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xd2, 0x90, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x71, 0x3a, 0xd0, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dclz $26, $9" + + - + input: + bytes: [ 0x73, 0x09, 0x48, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dclo $9, $24" + + - + input: + bytes: [ 0x73, 0x30, 0x80, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7c, 0x0e, 0x18, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsbh $3, $14" + + - + input: + bytes: [ 0x7c, 0x0e, 0x19, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dshd $3, $14" + + - + input: + bytes: [ 0x7c, 0x1c, 0x38, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dsbh $7, $gp" + + - + input: + bytes: [ 0x7c, 0x1d, 0x11, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dshd $2, $sp" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x7f, 0x87, 0xf7, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dext $7, $gp, 29, 31" + + - + input: + bytes: [ 0x7f, 0x94, 0x7b, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "dins $20, $gp, 15, 1" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0x3b, 0xc4, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lw $27, -15155($1)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0x9c, 0x63, 0xf9, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwu $3, -1746($3)" + + - + input: + bytes: [ 0x9c, 0x73, 0xa1, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0x3a, 0xc4, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sw $26, -15159($1)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb3, 0xc7, 0xae, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0xb5, 0x8b, 0xb0, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd3, 0xe0, 0xc6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xd9, 0x03, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ldc2 $3, 9162($8)" + + - + input: + bytes: [ 0xdc, 0x1a, 0x0f, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ld $26, 3958($zero)" + + - + input: + bytes: [ 0xde, 0x3d, 0x90, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf3, 0xaf, 0xdf, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xf8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdc2 $9, 9158($7)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xfc, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sd $6, 17767($zero)" + + - + input: + bytes: [ 0xfd, 0x4c, 0x16, 0xcb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" diff --git a/tests/MC/Mips/valid-mips64r5-el.txt.yaml b/tests/MC/Mips/valid-mips64r5-el.txt.yaml new file mode 100644 index 0000000000..3aa307a40e --- /dev/null +++ b/tests/MC/Mips/valid-mips64r5-el.txt.yaml @@ -0,0 +1,2380 @@ +test_cases: + - + input: + bytes: [ 0x05, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x85, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x20, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x00, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x40, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x67, 0xc5, 0xc9, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x21, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x24, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1c, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x01, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x1d, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xd1, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0xc0, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x4d, 0x01, 0x26, 0x15 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x32, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x32, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x30, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x3e, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x3e, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x3c, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x3c, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x3d, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x3d, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x3b, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x3b, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x39, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x39, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x3f, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x3f, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x36, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x36, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x34, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x34, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x3a, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x3a, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x38, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x38, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x33, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x33, 0xe0, 0x12, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x37, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x37, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x35, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x35, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x31, 0x60, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x31, 0x30, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x4a, 0x18, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x8a, 0x6c, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x0e, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x8e, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x00, 0x38, 0x46, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x20, 0x30, 0xe6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x00, 0x38, 0xc6, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x21, 0x81, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0xa1, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x21, 0x73, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x25, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0xa5, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0xe0, 0xf3, 0xa0, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x20, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0xa0, 0x39, 0x80, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x24, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0xa4, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x2c, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0xc7, 0x93, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0xc7, 0x93, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x16, 0xee, 0xda, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x2d, 0x98, 0x3f, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x9f, 0x46, 0x58, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x3f, 0x69, 0x73, 0x66 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x25, 0x90, 0xd2, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x24, 0x80, 0x30, 0x73 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x1e, 0x00, 0x53, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x1f, 0x00, 0x11, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x00, 0x50, 0x38, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x00, 0x68, 0x2c, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x00, 0x50, 0xa4, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x00, 0x70, 0xb0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x1c, 0x00, 0xe9, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x1d, 0x00, 0xa6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0xb8, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0xb8, 0x04, 0x14, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x14, 0x00, 0x94, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0xbc, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0xbb, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0xbb, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x17, 0xe0, 0x72, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0xbf, 0xe2, 0x1c, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0xbf, 0xe2, 0x12, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0xfa, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0xfa, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x16, 0x98, 0x86, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0xfe, 0x9d, 0x13, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0xfe, 0x9d, 0x06, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x2e, 0x38, 0xc8, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0xa4, 0x18, 0x0e, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsbh $3, $14" + + - + input: + bytes: [ 0x64, 0x11, 0x1d, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dshd $2, $sp" + + - + input: + bytes: [ 0x39, 0x6c, 0x9d, 0x62 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x39, 0x6c, 0xbd, 0x63 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x2f, 0x28, 0xba, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x5f, 0xec, 0x6f, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0xea, 0x11, 0xce, 0x65 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0xfa, 0x0b, 0x21, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotr $1, $1, 15" + + - + input: + bytes: [ 0xfa, 0x0b, 0x2e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotr $1, $14, 15" + + - + input: + bytes: [ 0xfe, 0x0b, 0x21, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotr32 $1, $1, 15" + + - + input: + bytes: [ 0xfe, 0x0b, 0x2e, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotr32 $1, $14, 15" + + - + input: + bytes: [ 0x56, 0x08, 0xee, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotrv $1, $14, $15" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x8b, 0x3e, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x0b, 0x2b, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x0f, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x8f, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x84, 0x61, 0x33, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x4c, 0x01, 0x00, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x09, 0xf8, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $7" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x08, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x1b, 0x90, 0x3d, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xb9, 0xef, 0x18, 0x6b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6a, 0x89, 0x8e, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xd4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x01, 0x02, 0xf7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x0c, 0x00, 0xa4, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0x70, 0xc6, 0xe0, 0xd3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0x67, 0x45, 0x06, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x05, 0x00, 0xa6, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x03, 0x00, 0x82, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x10, 0x00, 0xa3, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x00, 0x05, 0xcc, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0xea, 0xa1, 0x73, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0x00, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x60, 0x98, 0xf9, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x01, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x06, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x10, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0xc0, 0x7e, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x12, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x25, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x2d, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x86, 0x41, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x86, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x04, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x28, 0x53, 0x70, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x05, 0x00, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x00, 0x38, 0x86, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x11, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0x80, 0xe0, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x13, 0x00, 0xe0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x02, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x02, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x42, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x02, 0x48, 0xc7, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x18, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x19, 0x00, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x07, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x87, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x30, 0xc8, 0xac, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x27, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x78, 0x98, 0x04, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x25, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0xc2, 0x49, 0x26, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x46, 0x48, 0xe6, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x08, 0x0b, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x48, 0x2e, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x0c, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x8c, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0x06, 0x00, 0xa4, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xcd, 0xdf, 0xaf, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xcb, 0x16, 0x4c, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xf4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x1f, 0xae, 0xc7, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0x39, 0xb0, 0x8b, 0xb5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0x09, 0x40, 0x24, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x20, 0x34, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x20, 0x36, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0xc6, 0x23, 0xa4, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xc0, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x04, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x2a, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x67, 0x00, 0x63, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2b, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x04, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x84, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0xc3, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x07, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0xc2, 0x21, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x06, 0x10, 0xa3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x01, 0x62, 0x2e, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x01, 0x71, 0xda, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x41, 0x32, 0x07, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x22, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x23, 0x20, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x0d, 0x20, 0xb8, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x18, 0x00, 0xa4, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0x10, 0x00, 0xa4, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0x10, 0x00, 0xe6, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0x08, 0xd0, 0xd2, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0xcf, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0xc9, 0xbd, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x09, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x0d, 0x73, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x8d, 0x39, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0xa0, 0x30, 0x07, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x26, 0x18, 0x65, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x67, 0x45, 0xc9, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" diff --git a/tests/MC/Mips/valid-mips64r5.txt.yaml b/tests/MC/Mips/valid-mips64r5.txt.yaml new file mode 100644 index 0000000000..f1788e926d --- /dev/null +++ b/tests/MC/Mips/valid-mips64r5.txt.yaml @@ -0,0 +1,4750 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jr $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "syscall" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "break" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add $zero, $zero, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sll $zero, $zero, 2" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0xcf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sync 7" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsll $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x04, 0xbc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsll32 $zero, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $5, $zero" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfhi $5" + + - + input: + bytes: [ 0x00, 0x00, 0x28, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mflo $5" + + - + input: + bytes: [ 0x00, 0x00, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sll $7, $zero, 18" + + - + input: + bytes: [ 0x00, 0x00, 0x72, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "break 0, 456" + + - + input: + bytes: [ 0x00, 0x00, 0x88, 0x12 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mflo $17" + + - + input: + bytes: [ 0x00, 0x00, 0x98, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfhi $19" + + - + input: + bytes: [ 0x00, 0x00, 0xe8, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfhi $sp" + + - + input: + bytes: [ 0x00, 0x01, 0x0f, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsra $1, $1, 30" + + - + input: + bytes: [ 0x00, 0x02, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "negu $2, $2" + + - + input: + bytes: [ 0x00, 0x02, 0x11, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "srl $2, $2, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "negu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dneg $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dnegu $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sll $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "srl $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x03, 0x21, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sra $4, $3, 7" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrl $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x06, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $6, 23" + + - + input: + bytes: [ 0x00, 0x07, 0x38, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nor $7, $zero, $7" + + - + input: + bytes: [ 0x00, 0x07, 0x3c, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sll $7, $7, 18" + + - + input: + bytes: [ 0x00, 0x08, 0xe8, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "neg $sp, $8" + + - + input: + bytes: [ 0x00, 0x10, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sll $zero, $16, 2" + + - + input: + bytes: [ 0x00, 0x11, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sra $17, $17, 15" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsra $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x12, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $18, 10" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrl $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x13, 0x9d, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrl32 $19, $19, 23" + + - + input: + bytes: [ 0x00, 0x14, 0x04, 0xb8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsll $zero, $20, 18" + + - + input: + bytes: [ 0x00, 0x17, 0x8b, 0xc3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sra $17, $23, 15" + + - + input: + bytes: [ 0x00, 0x18, 0x1c, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsll $3, $24, 17" + + - + input: + bytes: [ 0x00, 0x1c, 0x56, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrl $10, $gp, 24" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsra $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x1c, 0xe2, 0xbf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsra32 $gp, $gp, 10" + + - + input: + bytes: [ 0x00, 0x21, 0x0b, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotr $1, $1, 15" + + - + input: + bytes: [ 0x00, 0x21, 0x0b, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotr32 $1, $1, 15" + + - + input: + bytes: [ 0x00, 0x26, 0x49, 0xc2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rotr $9, $6, 7" + + - + input: + bytes: [ 0x00, 0x2b, 0xd0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddu $26, $1, $11" + + - + input: + bytes: [ 0x00, 0x2e, 0x0b, 0xfa ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotr $1, $14, 15" + + - + input: + bytes: [ 0x00, 0x2e, 0x0b, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotr32 $1, $14, 15" + + - + input: + bytes: [ 0x00, 0x3a, 0x3a, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "syscall 59627" + + - + input: + bytes: [ 0x00, 0x3b, 0xa1, 0xba ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotr $20, $27, 6" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dadd $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x3f, 0x98, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddu $19, $1, $ra" + + - + input: + bytes: [ 0x00, 0x4c, 0xb8, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "and $23, $2, $12" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x5c, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "movf $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x5d, 0x18, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "movt $3, $2, $fcc7" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mult $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "multu $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "or $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "xor $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "slt $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x18, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sltu $3, $3, $5" + + - + input: + bytes: [ 0x00, 0x65, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "subu $4, $3, $5" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xf0, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "move $fp, $4" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0x86, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addu $9, $4, $6" + + - + input: + bytes: [ 0x00, 0x94, 0xc8, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "srlv $25, $20, $4" + + - + input: + bytes: [ 0x00, 0x9e, 0x90, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "xor $18, $4, $fp" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sllv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "srlv $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa3, 0x10, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "srav $2, $3, $5" + + - + input: + bytes: [ 0x00, 0xa6, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmultu $5, $6" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xb7, 0xc0, 0x56 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotrv $24, $23, $5" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "move $25, $6" + + - + input: + bytes: [ 0x00, 0xc0, 0xc8, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "not $25, $6" + + - + input: + bytes: [ 0x00, 0xba, 0x28, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsubu $5, $5, $26" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addu $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "and $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xc7, 0x48, 0x27 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nor $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mthi $7" + + - + input: + bytes: [ 0x00, 0xe0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtlo $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5", "CS_MODE_MIPS_PTR64" ] + expected: + insns: + - + asm_text: "jalr $7" + + - + input: + bytes: [ 0x00, 0xe0, 0xf8, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "movn $ra, $7, $zero" + + - + input: + bytes: [ 0x00, 0xe6, 0x48, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rotrv $9, $6, $7" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x20, 0x38, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sllv $7, $zero, $9" + + - + input: + bytes: [ 0x01, 0x32, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "multu $9, $18" + + - + input: + bytes: [ 0x01, 0x38, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ddivu $zero, $9, $24" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0x7a, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmult $11, $26" + + - + input: + bytes: [ 0x01, 0x7b, 0xb8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "slt $23, $11, $27" + + - + input: + bytes: [ 0x01, 0x94, 0x00, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsllv $zero, $20, $12" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x01, 0xee, 0x08, 0x56 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "drotrv $1, $14, $15" + + - + input: + bytes: [ 0x02, 0x11, 0x00, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ddivu $zero, $16, $17" + + - + input: + bytes: [ 0x02, 0x1d, 0x60, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "or $12, $16, $sp" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x20, 0x00, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mthi $17" + + - + input: + bytes: [ 0x02, 0x27, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "break 551" + + - + input: + bytes: [ 0x02, 0x45, 0xb8, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add $23, $18, $5" + + - + input: + bytes: [ 0x02, 0x6c, 0xb0, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub $22, $19, $12" + + - + input: + bytes: [ 0x02, 0x72, 0xe0, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrav $gp, $18, $19" + + - + input: + bytes: [ 0x02, 0x86, 0x98, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrlv $19, $6, $20" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xab, 0xa0, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sltu $20, $21, $11" + + - + input: + bytes: [ 0x02, 0xc8, 0x38, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsub $7, $22, $8" + + - + input: + bytes: [ 0x02, 0xd6, 0xe8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "subu $sp, $22, $22" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x02, 0xe9, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmult $23, $9" + + - + input: + bytes: [ 0x02, 0xea, 0xe0, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrlv $gp, $10, $23" + + - + input: + bytes: [ 0x02, 0xed, 0x00, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmultu $23, $13" + + - + input: + bytes: [ 0x03, 0x1b, 0xe0, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsllv $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x20, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtlo $25" + + - + input: + bytes: [ 0x03, 0x2b, 0x00, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "div $zero, $25, $11" + + - + input: + bytes: [ 0x03, 0x2f, 0x00, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "divu $zero, $25, $15" + + - + input: + bytes: [ 0x03, 0x53, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $19" + + - + input: + bytes: [ 0x03, 0x56, 0x00, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ddiv $zero, $26, $22" + + - + input: + bytes: [ 0x03, 0x78, 0xe0, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsubu $gp, $27, $24" + + - + input: + bytes: [ 0x03, 0x9a, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "multu $gp, $26" + + - + input: + bytes: [ 0x03, 0xa0, 0x00, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtlo $sp" + + - + input: + bytes: [ 0x03, 0xa2, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mult $sp, $2" + + - + input: + bytes: [ 0x03, 0xb4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mult $sp, $20" + + - + input: + bytes: [ 0x03, 0xb7, 0x88, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "srav $17, $23, $sp" + + - + input: + bytes: [ 0x03, 0xc1, 0x08, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsrav $1, $1, $fp" + + - + input: + bytes: [ 0x03, 0xcd, 0x23, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "break 973, 143" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x7f, 0x47, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "synci 18368($3)" + + - + input: + bytes: [ 0x04, 0x83, 0xf9, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgezl $4, -6852" + + - + input: + bytes: [ 0x04, 0xc1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgez $6, 1336" + + - + input: + bytes: [ 0x04, 0xd0, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bltzal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd1, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgezal $6, 1336" + + - + input: + bytes: [ 0x04, 0xd1, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgezal $6, 21108" + + - + input: + bytes: [ 0x04, 0xd2, 0x00, 0x7b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bltzall $6, 496" + + - + input: + bytes: [ 0x05, 0x8e, 0x8c, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tnei $12, -29647" + + - + input: + bytes: [ 0x05, 0x93, 0x07, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgezall $12, 7300" + + - + input: + bytes: [ 0x05, 0xca, 0xad, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tlti $14, -21059" + + - + input: + bytes: [ 0x06, 0x22, 0xf6, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bltzl $17, -9956" + + - + input: + bytes: [ 0x06, 0x28, 0x13, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tgei $17, 5025" + + - + input: + bytes: [ 0x06, 0xac, 0xbb, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "teqi $21, -17504" + + - + input: + bytes: [ 0x07, 0xa9, 0x90, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tgeiu $sp, -28621" + + - + input: + bytes: [ 0x07, 0xeb, 0xec, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tltiu $ra, -5076" + + - + input: + bytes: [ 0x08, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "j 4" + + - + input: + bytes: [ 0x08, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "j 1328" + + - + input: + bytes: [ 0x09, 0x33, 0x00, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "j 80478376" + + - + input: + bytes: [ 0x0b, 0x2a, 0xd1, 0x44 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "j 212550928" + + - + input: + bytes: [ 0x0c, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jal 1328" + + - + input: + bytes: [ 0x10, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "b 1336" + + - + input: + bytes: [ 0x11, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "beq $9, $6, 1336" + + - + input: + bytes: [ 0x15, 0x26, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bne $9, $6, 1336" + + - + input: + bytes: [ 0x18, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "blez $6, 1336" + + - + input: + bytes: [ 0x1c, 0xc0, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgtz $6, 1336" + + - + input: + bytes: [ 0x20, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addi $9, $6, 17767" + + - + input: + bytes: [ 0x21, 0x08, 0xff, 0xfe ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addi $8, $8, -2" + + - + input: + bytes: [ 0x21, 0x2d, 0x66, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addi $13, $9, 26322" + + - + input: + bytes: [ 0x21, 0xad, 0xe6, 0x90 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addi $13, $13, -6512" + + - + input: + bytes: [ 0x21, 0xc9, 0x3b, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addi $9, $14, 15176" + + - + input: + bytes: [ 0x22, 0x36, 0x0c, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addi $22, $17, 3126" + + - + input: + bytes: [ 0x23, 0x18, 0xe3, 0xe7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addi $24, $24, -7193" + + - + input: + bytes: [ 0x24, 0x00, 0x8b, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addiu $zero, $zero, -29889" + + - + input: + bytes: [ 0x24, 0x01, 0x8b, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addiu $1, $zero, -29773" + + - + input: + bytes: [ 0x24, 0xc9, 0xc5, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addiu $9, $6, -15001" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x28, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "slti $3, $3, 103" + + - + input: + bytes: [ 0x29, 0x51, 0x25, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "slti $17, $10, 9489" + + - + input: + bytes: [ 0x2c, 0x63, 0x00, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sltiu $3, $3, 103" + + - + input: + bytes: [ 0x2f, 0x38, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sltiu $24, $25, -15531" + + - + input: + bytes: [ 0x2f, 0x39, 0xc3, 0x55 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sltiu $25, $25, -15531" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x30, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "andi $9, $6, 17767" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ori $2, $2, 0" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x34, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ori $9, $6, 17767" + + - + input: + bytes: [ 0x38, 0xc9, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "xori $9, $6, 17767" + + - + input: + bytes: [ 0x3c, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lui $zero, 128" + + - + input: + bytes: [ 0x3c, 0x01, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lui $1, 1" + + - + input: + bytes: [ 0x3c, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lui $6, 17767" + + - + input: + bytes: [ 0x3c, 0x1f, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lui $ra, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 4" + + - + input: + bytes: [ 0x40, 0x38, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x40, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tlbr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tlbwi" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tlbwr" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tlbp" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "eret" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "wait" + + - + input: + bytes: [ 0x44, 0x06, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x07, 0xd8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfc1 $7, $f27" + + - + input: + bytes: [ 0x44, 0x22, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfc1 $2, $f14" + + - + input: + bytes: [ 0x44, 0x2c, 0x68, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfc1 $12, $f13" + + - + input: + bytes: [ 0x44, 0x46, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cfc1 $6, $7" + + - + input: + bytes: [ 0x44, 0x51, 0xa8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cfc1 $17, $21" + + - + input: + bytes: [ 0x44, 0x7e, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mfhc1 $fp, $f24" + + - + input: + bytes: [ 0x44, 0x86, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtc1 $6, $f7" + + - + input: + bytes: [ 0x44, 0x9e, 0x48, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mtc1 $fp, $f9" + + - + input: + bytes: [ 0x44, 0xb0, 0x70, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtc1 $16, $f14" + + - + input: + bytes: [ 0x44, 0xb7, 0x28, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtc1 $23, $f5" + + - + input: + bytes: [ 0x44, 0xc6, 0x38, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ctc1 $6, $7" + + - + input: + bytes: [ 0x44, 0xc6, 0xd0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ctc1 $6, $26" + + - + input: + bytes: [ 0x44, 0xe0, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mthc1 $zero, $f16" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1f 12" + + - + input: + bytes: [ 0x45, 0x00, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1f 1336" + + - + input: + bytes: [ 0x45, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1t 12" + + - + input: + bytes: [ 0x45, 0x01, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1t 1336" + + - + input: + bytes: [ 0x45, 0x02, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1fl 56" + + - + input: + bytes: [ 0x45, 0x03, 0xf7, 0xf5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1tl -8232" + + - + input: + bytes: [ 0x45, 0x1c, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1f $fcc7, 1336" + + - + input: + bytes: [ 0x45, 0x1d, 0x01, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bc1t $fcc7, 1336" + + - + input: + bytes: [ 0x46, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f0, $f1" + + - + input: + bytes: [ 0x46, 0x00, 0x2b, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.l.s $f12, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x2e, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.l.s $f25, $f5" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sqrt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "abs.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mov.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "neg.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.w.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x39, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.l.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x00, 0x46, 0xa5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.l.s $f26, $f8" + + - + input: + bytes: [ 0x46, 0x00, 0x4a, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.w.s $f8, $f9" + + - + input: + bytes: [ 0x46, 0x00, 0x6c, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.l.s $f18, $f13" + + - + input: + bytes: [ 0x46, 0x00, 0x78, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "neg.s $f1, $f15" + + - + input: + bytes: [ 0x46, 0x00, 0x82, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "abs.s $f9, $f16" + + - + input: + bytes: [ 0x46, 0x00, 0xa1, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.w.s $f6, $f20" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.w.s $f20, $f24" + + - + input: + bytes: [ 0x46, 0x00, 0xc5, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "movn.s $f21, $f24, $zero" + + - + input: + bytes: [ 0x46, 0x00, 0xd8, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mov.s $f2, $f27" + + - + input: + bytes: [ 0x46, 0x00, 0xe5, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.d.s $f22, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xe6, 0xcc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.w.s $f27, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0xf7, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.w.s $f28, $f30" + + - + input: + bytes: [ 0x46, 0x00, 0xff, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.l.s $f28, $f31" + + - + input: + bytes: [ 0x46, 0x02, 0x57, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul.s $f30, $f10, $f2" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.f.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.un.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.eq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.olt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ult.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ole.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ule.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.sf.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngle.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.seq.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngl.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.lt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.nge.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.le.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x30, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngt.s $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x07, 0x32, 0x42 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul.s $f9, $f6, $f7" + + - + input: + bytes: [ 0x46, 0x0f, 0x29, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "div.s $f4, $f5, $f15" + + - + input: + bytes: [ 0x46, 0x12, 0xe0, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ueq.s $f28, $f18" + + - + input: + bytes: [ 0x46, 0x16, 0x70, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.sf.s $f14, $f22" + + - + input: + bytes: [ 0x46, 0x16, 0xb5, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub.s $f23, $f22, $f22" + + - + input: + bytes: [ 0x46, 0x18, 0xaa, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add.s $f8, $f21, $f24" + + - + input: + bytes: [ 0x46, 0x1c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "movf.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x1d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "movt.s $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x20, 0x0b, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.l.d $f12, $f1" + + - + input: + bytes: [ 0x46, 0x20, 0x18, 0x4a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.l.d $f1, $f3" + + - + input: + bytes: [ 0x46, 0x20, 0x21, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.w.d $f6, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x3e, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.l.d $f26, $f7" + + - + input: + bytes: [ 0x46, 0x20, 0x41, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mov.d $f6, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x46, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f26, $f8" + + - + input: + bytes: [ 0x46, 0x20, 0x53, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.w.d $f14, $f10" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "abs.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "neg.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "round.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "floor.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x73, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.l.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mov.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.w.d $f20, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x75, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.w.d $f22, $f14" + + - + input: + bytes: [ 0x46, 0x20, 0x96, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "neg.d $f26, $f18" + + - + input: + bytes: [ 0x46, 0x20, 0xb4, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sqrt.d $f16, $f22" + + - + input: + bytes: [ 0x46, 0x20, 0xbd, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "trunc.l.d $f23, $f23" + + - + input: + bytes: [ 0x46, 0x20, 0xc1, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "abs.d $f6, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xc2, 0xce ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ceil.w.d $f11, $f24" + + - + input: + bytes: [ 0x46, 0x20, 0xf0, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.f.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.un.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.eq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ueq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.olt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ult.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ole.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ule.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.sf.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngle.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.seq.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngl.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.lt.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.nge.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.le.d $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x60, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngt.d $f12, $f14" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "eretnc" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0x2e, 0x62, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul.d $f8, $f12, $f14" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0xda, 0x71, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul.ps $f4, $f14, $f26" + + - + input: + bytes: [ 0x46, 0x30, 0x00, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngle.d $f0, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sub.d $f18, $f2, $f16" + + - + input: + bytes: [ 0x46, 0x30, 0xa5, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul.d $f20, $f20, $f16" + + - + input: + bytes: [ 0x46, 0x3a, 0xa7, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "div.d $f28, $f20, $f26" + + - + input: + bytes: [ 0x46, 0x3a, 0xb1, 0x13 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "movn.d $f4, $f22, $26" + + - + input: + bytes: [ 0x46, 0x3c, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "movf.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x3c, 0x30, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "add.d $f0, $f6, $f28" + + - + input: + bytes: [ 0x46, 0x3c, 0xe0, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngl.d $f28, $f28" + + - + input: + bytes: [ 0x46, 0x3d, 0x11, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "movt.d $f4, $f2, $fcc7" + + - + input: + bytes: [ 0x46, 0x80, 0x39, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.w $f6, $f7" + + - + input: + bytes: [ 0x46, 0x80, 0x5e, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f26, $f11" + + - + input: + bytes: [ 0x46, 0x80, 0x73, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.d.w $f12, $f14" + + - + input: + bytes: [ 0x46, 0x80, 0x7d, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.w $f22, $f15" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x48, 0x20, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmfc2 $zero, $10, 0" + + - + input: + bytes: [ 0x48, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dmtc2 $4, $10, 0" + + - + input: + bytes: [ 0x4d, 0x0c, 0xe0, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "madd.d $f0, $f8, $f28, $f12" + + - + input: + bytes: [ 0x4d, 0xbb, 0x0d, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "madd.s $f23, $f13, $f1, $f27" + + - + input: + bytes: [ 0x51, 0xd3, 0x0c, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "beql $14, $19, 12552" + + - + input: + bytes: [ 0x57, 0x94, 0x04, 0xfd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bnel $gp, $20, 5112" + + - + input: + bytes: [ 0x58, 0xc0, 0x02, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "blezl $6, 2980" + + - + input: + bytes: [ 0x5d, 0x40, 0xfc, 0x5a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bgtzl $10, -3732" + + - + input: + bytes: [ 0x46, 0xa0, 0x81, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.d.l $f4, $f16" + + - + input: + bytes: [ 0x46, 0xa0, 0xf3, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.l $f15, $f30" + + - + input: + bytes: [ 0x4c, 0xa6, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "luxc1 $f0, $6($5)" + + - + input: + bytes: [ 0x4c, 0xac, 0xc8, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nmadd.s $f0, $f5, $f25, $f12" + + - + input: + bytes: [ 0x4c, 0xb8, 0x20, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "suxc1 $f4, $24($5)" + + - + input: + bytes: [ 0x4d, 0x42, 0x00, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldxc1 $f2, $2($10)" + + - + input: + bytes: [ 0x4d, 0xbb, 0x60, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "suxc1 $f12, $27($13)" + + - + input: + bytes: [ 0x4d, 0xca, 0x58, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdxc1 $f11, $10($14)" + + - + input: + bytes: [ 0x4d, 0xcc, 0x05, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwxc1 $f20, $12($14)" + + - + input: + bytes: [ 0x4d, 0xf7, 0x02, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldxc1 $f8, $23($15)" + + - + input: + bytes: [ 0x4e, 0x70, 0x53, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "msub.s $f12, $f19, $f10, $f16" + + - + input: + bytes: [ 0x4e, 0xb6, 0x04, 0xc5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "luxc1 $f19, $22($21)" + + - + input: + bytes: [ 0x4e, 0xd2, 0xd0, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swxc1 $f26, $18($22)" + + - + input: + bytes: [ 0x4f, 0x04, 0x98, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nmsub.s $f1, $f24, $f19, $f4" + + - + input: + bytes: [ 0x4f, 0x24, 0x40, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdxc1 $f8, $4($25)" + + - + input: + bytes: [ 0x4f, 0x4c, 0x98, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swxc1 $f19, $12($26)" + + - + input: + bytes: [ 0x4f, 0xd1, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwxc1 $f12, $17($fp)" + + - + input: + bytes: [ 0x4f, 0xf9, 0x98, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "madd.s $f1, $f31, $f19, $f25" + + - + input: + bytes: [ 0x62, 0x9d, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, 27705" + + - + input: + bytes: [ 0x62, 0x9d, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddi $sp, $20, -27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x6c, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, 27705" + + - + input: + bytes: [ 0x63, 0xbd, 0x93, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddi $sp, $sp, -27705" + + - + input: + bytes: [ 0x64, 0x58, 0x46, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x65, 0x6f, 0xec, 0x5f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0x65, 0xce, 0x11, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x66, 0x73, 0x69, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x66, 0xda, 0xee, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $26, $22, -4586" + + - + input: + bytes: [ 0x67, 0x4b, 0x7c, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $11, $26, 31949" + + - + input: + bytes: [ 0x67, 0xbd, 0xff, 0xe0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "daddiu $sp, $sp, -32" + + - + input: + bytes: [ 0x6b, 0x18, 0xef, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldl $24, -4167($24)" + + - + input: + bytes: [ 0x6e, 0x8e, 0x89, 0x6a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldr $14, -30358($20)" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "madd $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "maddu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "msub $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "msubu $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "mul $9, $6, $7" + + - + input: + bytes: [ 0x70, 0xc7, 0x7d, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdbbp 204276" + + - + input: + bytes: [ 0x70, 0xd2, 0x90, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "clz $6, $7" + + - + input: + bytes: [ 0x70, 0xe6, 0x30, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "clo $6, $7" + + - + input: + bytes: [ 0x71, 0x3a, 0xd0, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dclz $26, $9" + + - + input: + bytes: [ 0x73, 0x09, 0x48, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dclo $9, $24" + + - + input: + bytes: [ 0x73, 0x30, 0x80, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x74, 0x00, 0x01, 0x4c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "jalx 1328" + + - + input: + bytes: [ 0x7c, 0x05, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rdhwr $5, $29" + + - + input: + bytes: [ 0x7c, 0x07, 0x30, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "wsbh $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "seb $6, $7" + + - + input: + bytes: [ 0x7c, 0x07, 0x36, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "seh $6, $7" + + - + input: + bytes: [ 0x7c, 0x0e, 0x18, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsbh $3, $14" + + - + input: + bytes: [ 0x7c, 0x0e, 0x19, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dshd $3, $14" + + - + input: + bytes: [ 0x7c, 0x1c, 0x38, 0xa4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dsbh $7, $gp" + + - + input: + bytes: [ 0x7c, 0x1d, 0x11, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dshd $2, $sp" + + - + input: + bytes: [ 0x7d, 0x33, 0x61, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ins $19, $9, 6, 7" + + - + input: + bytes: [ 0x7f, 0x87, 0xf7, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dext $7, $gp, 29, 31" + + - + input: + bytes: [ 0x7f, 0x94, 0x7b, 0xc7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "dins $20, $gp, 15, 1" + + - + input: + bytes: [ 0x80, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lb $4, 9158($5)" + + - + input: + bytes: [ 0x81, 0x58, 0xc7, 0x4d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lb $24, -14515($10)" + + - + input: + bytes: [ 0x84, 0xa4, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lh $4, 12($5)" + + - + input: + bytes: [ 0x86, 0xab, 0xde, 0x94 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lh $11, -8556($21)" + + - + input: + bytes: [ 0x88, 0x82, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwl $2, 3($4)" + + - + input: + bytes: [ 0x89, 0xf4, 0xef, 0x79 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwl $20, -4231($15)" + + - + input: + bytes: [ 0x8c, 0x3b, 0xc4, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lw $27, -15155($1)" + + - + input: + bytes: [ 0x8c, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lw $4, 24($5)" + + - + input: + bytes: [ 0x8c, 0xa8, 0x16, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lw $8, 5674($5)" + + - + input: + bytes: [ 0x90, 0x68, 0x75, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lbu $8, 30195($3)" + + - + input: + bytes: [ 0x90, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lbu $4, 6($5)" + + - + input: + bytes: [ 0x94, 0x53, 0xa6, 0xbd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lhu $19, -22851($2)" + + - + input: + bytes: [ 0x98, 0xa3, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwr $3, 16($5)" + + - + input: + bytes: [ 0x9b, 0x80, 0xb5, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwr $zero, -19147($gp)" + + - + input: + bytes: [ 0x9c, 0x63, 0xf9, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwu $3, -1746($3)" + + - + input: + bytes: [ 0x9c, 0x73, 0xa1, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwu $19, -24086($3)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sb $4, 6($5)" + + - + input: + bytes: [ 0xa0, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sb $4, 9158($5)" + + - + input: + bytes: [ 0xa1, 0xd6, 0xb2, 0x6f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sb $22, -19857($14)" + + - + input: + bytes: [ 0xa4, 0xa4, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sh $4, 9158($5)" + + - + input: + bytes: [ 0xa5, 0xee, 0xe5, 0xd0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sh $14, -6704($15)" + + - + input: + bytes: [ 0xa8, 0xa4, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swl $4, 16($5)" + + - + input: + bytes: [ 0xaa, 0x6f, 0x35, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swl $15, 13694($19)" + + - + input: + bytes: [ 0xac, 0x3a, 0xc4, 0xc9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sw $26, -15159($1)" + + - + input: + bytes: [ 0xac, 0xa4, 0x00, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sw $4, 24($5)" + + - + input: + bytes: [ 0xaf, 0xbf, 0xd8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sw $ra, -10160($sp)" + + - + input: + bytes: [ 0xb3, 0xc7, 0xae, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdl $7, -20961($fp)" + + - + input: + bytes: [ 0xb5, 0x8b, 0xb0, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdr $11, -20423($12)" + + - + input: + bytes: [ 0xb8, 0xe6, 0x00, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swr $6, 16($7)" + + - + input: + bytes: [ 0xb9, 0xd1, 0x98, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swr $17, -26590($14)" + + - + input: + bytes: [ 0xbc, 0x61, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cache 1, 2($3)" + + - + input: + bytes: [ 0xbc, 0x80, 0xb7, 0xd2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cache 0, -18478($4)" + + - + input: + bytes: [ 0xc0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ll $9, 9158($7)" + + - + input: + bytes: [ 0xc2, 0x42, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ll $2, -7321($18)" + + - + input: + bytes: [ 0xc4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xc7, 0x50, 0x27, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwc1 $f16, 10225($26)" + + - + input: + bytes: [ 0xc8, 0xc8, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwc2 $8, 9162($6)" + + - + input: + bytes: [ 0xc8, 0xd2, 0xfc, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0xcc, 0x43, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "pref 3, 4($2)" + + - + input: + bytes: [ 0xcf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "pref 0, 0($24)" + + - + input: + bytes: [ 0xd3, 0xe0, 0xc6, 0x70 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lld $zero, -14736($ra)" + + - + input: + bytes: [ 0xd4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xd6, 0x0a, 0x40, 0x07 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldc1 $f10, 16391($16)" + + - + input: + bytes: [ 0xd8, 0x07, 0x34, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldc2 $7, 13344($zero)" + + - + input: + bytes: [ 0xd8, 0x28, 0xad, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldc2 $8, -21181($1)" + + - + input: + bytes: [ 0xd9, 0x03, 0x23, 0xca ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ldc2 $3, 9162($8)" + + - + input: + bytes: [ 0xdc, 0x1a, 0x0f, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ld $26, 3958($zero)" + + - + input: + bytes: [ 0xde, 0x3d, 0x90, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ld $sp, -28645($17)" + + - + input: + bytes: [ 0xe0, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sc $9, 9158($7)" + + - + input: + bytes: [ 0xe2, 0x6f, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sc $15, 18904($19)" + + - + input: + bytes: [ 0xe4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xe7, 0x06, 0xde, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swc1 $f6, -8465($24)" + + - + input: + bytes: [ 0xe8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swc2 $9, 9158($7)" + + - + input: + bytes: [ 0xea, 0x19, 0x61, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swc2 $25, 24880($16)" + + - + input: + bytes: [ 0xf3, 0xaf, 0xdf, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "scd $15, -8243($sp)" + + - + input: + bytes: [ 0xf4, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdc1 $f9, 9158($7)" + + - + input: + bytes: [ 0xf5, 0xbe, 0x77, 0x6e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdc1 $f30, 30574($13)" + + - + input: + bytes: [ 0xf8, 0xe9, 0x23, 0xc6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdc2 $9, 9158($7)" + + - + input: + bytes: [ 0xfa, 0x54, 0x5a, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sdc2 $20, 23157($18)" + + - + input: + bytes: [ 0xfc, 0x06, 0x45, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sd $6, 17767($zero)" + + - + input: + bytes: [ 0xfd, 0x4c, 0x16, 0xcb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sd $12, 5835($10)" diff --git a/tests/MC/Mips/valid-mips64r6-el.txt.yaml b/tests/MC/Mips/valid-mips64r6-el.txt.yaml new file mode 100644 index 0000000000..46b8921b2e --- /dev/null +++ b/tests/MC/Mips/valid-mips64r6-el.txt.yaml @@ -0,0 +1,1950 @@ +test_cases: + - + input: + bytes: [ 0x0a, 0x00, 0x29, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0xa0, 0x22, 0x43, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "align $4, $2, $3, 2" + + - + input: + bytes: [ 0x38, 0x00, 0x7f, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "aluipc $3, 56" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0xe9, 0xff, 0x43, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "aui $3, $2, 65513" + + - + input: + bytes: [ 0xff, 0xff, 0x7e, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "auipc $3, -1" + + - + input: + bytes: [ 0x9c, 0x14, 0x11, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0xb9, 0x96, 0x37, 0xe8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "balc 14572264" + + - + input: + bytes: [ 0xb9, 0x96, 0x37, 0xc8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc 14572264" + + - + input: + bytes: [ 0x02, 0x00, 0x20, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc1eqz $f0, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x3f, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc1eqz $f31, 12" + + - + input: + bytes: [ 0x02, 0x00, 0xa0, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc1nez $f0, 12" + + - + input: + bytes: [ 0x02, 0x00, 0xbf, 0x45 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc1nez $f31, 12" + + - + input: + bytes: [ 0x03, 0x00, 0x20, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc2eqz $0, 16" + + - + input: + bytes: [ 0x03, 0x00, 0x3f, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc2eqz $31, 16" + + - + input: + bytes: [ 0x03, 0x00, 0xa0, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc2nez $0, 16" + + - + input: + bytes: [ 0x03, 0x00, 0xbf, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc2nez $31, 16" + + - + input: + bytes: [ 0x41, 0x00, 0xa6, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "beqc $5, $6, 264" + + - + input: + bytes: [ 0x40, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x4e, 0x01, 0x02, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "beqzalc $2, 1340" + + - + input: + bytes: [ 0x91, 0x46, 0xa0, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "beqzc $5, 72264" + + - + input: + bytes: [ 0xfb, 0xff, 0x5f, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "beqzc $2, -16" + + - + input: + bytes: [ 0x41, 0x00, 0x43, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgec $2, $3, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x43, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgec $2, $3, -16" + + - + input: + bytes: [ 0x41, 0x00, 0x43, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgeuc $2, $3, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x43, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgeuc $2, $3, -16" + + - + input: + bytes: [ 0x4e, 0x01, 0x42, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgezalc $2, 1340" + + - + input: + bytes: [ 0xfb, 0xff, 0x42, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgezalc $2, -16" + + - + input: + bytes: [ 0x41, 0x00, 0xa5, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgezc $5, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0xa5, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgezc $5, -16" + + - + input: + bytes: [ 0x4e, 0x01, 0x02, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgtzalc $2, 1340" + + - + input: + bytes: [ 0xfb, 0xff, 0x02, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgtzalc $2, -16" + + - + input: + bytes: [ 0x41, 0x00, 0x05, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgtzc $5, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x05, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgtzc $5, -16" + + - + input: + bytes: [ 0x20, 0x20, 0x02, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bitswap $4, $2" + + - + input: + bytes: [ 0x4e, 0x01, 0x02, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "blezalc $2, 1340" + + - + input: + bytes: [ 0xfb, 0xff, 0x02, 0x18 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "blezalc $2, -16" + + - + input: + bytes: [ 0x41, 0x00, 0x05, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "blezc $5, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x05, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "blezc $5, -16" + + - + input: + bytes: [ 0x41, 0x00, 0xa6, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltc $5, $6, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0xa6, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltc $5, $6, -16" + + - + input: + bytes: [ 0x41, 0x00, 0xa6, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltuc $5, $6, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0xa6, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltuc $5, $6, -16" + + - + input: + bytes: [ 0x4e, 0x01, 0x42, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltzalc $2, 1340" + + - + input: + bytes: [ 0xfb, 0xff, 0x42, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltzalc $2, -16" + + - + input: + bytes: [ 0x41, 0x00, 0xa5, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltzc $5, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0xa5, 0x5c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltzc $5, -16" + + - + input: + bytes: [ 0x41, 0x00, 0xa6, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnec $5, $6, 264" + + - + input: + bytes: [ 0xfb, 0xff, 0x43, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnec $2, $3, -16" + + - + input: + bytes: [ 0x4e, 0x01, 0x02, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnezalc $2, 1340" + + - + input: + bytes: [ 0x91, 0x46, 0xa0, 0xf8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnezc $5, 72264" + + - + input: + bytes: [ 0xfb, 0xff, 0x5f, 0xf8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnezc $2, -16" + + - + input: + bytes: [ 0x02, 0x00, 0x40, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $2, $zero, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x82, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $4, $2, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x60 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $zero, $zero, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x40, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $2, $zero, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x82, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $4, $2, 12" + + - + input: + bytes: [ 0x02, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $zero, $zero, 12" + + - + input: + bytes: [ 0x25, 0x04, 0xa1, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cache 1, 8($5)" + + - + input: + bytes: [ 0x9b, 0x20, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "class.d $f2, $f4" + + - + input: + bytes: [ 0x9b, 0x20, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "class.s $f2, $f4" + + - + input: + bytes: [ 0x51, 0x58, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "clo $11, $5" + + - + input: + bytes: [ 0x50, 0xe8, 0x80, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "clz $sp, $gp" + + - + input: + bytes: [ 0x80, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.af.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x80, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.af.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x82, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.eq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x82, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.eq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x86, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.le.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x86, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.le.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x84, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.lt.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x84, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.lt.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x88, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.saf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x88, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.saf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8a, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.seq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8a, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.seq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8e, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sle.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8e, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sle.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8c, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.slt.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8c, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.slt.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8b, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sueq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8b, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sueq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8f, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sule.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8f, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sule.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x8d, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sult.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x8d, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sult.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x89, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sun.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x89, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sun.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x83, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ueq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x83, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ueq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x87, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ule.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x87, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ule.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x85, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ult.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x85, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ult.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x81, 0x18, 0xa4, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.un.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x81, 0x18, 0x84, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.un.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x64, 0x23, 0x43, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dalign $4, $2, $3, 5" + + - + input: + bytes: [ 0x34, 0x12, 0x43, 0x74 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "daui $3, $2, 4660" + + - + input: + bytes: [ 0x24, 0x20, 0x02, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dbitswap $4, $2" + + - + input: + bytes: [ 0x53, 0x90, 0xc0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x52, 0x80, 0x20, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x9e, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ddiv $2, $3, $4" + + - + input: + bytes: [ 0x9f, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ddivu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x00, 0x60, 0x7e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x9a, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "div $2, $3, $4" + + - + input: + bytes: [ 0x9b, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "divu $2, $3, $4" + + - + input: + bytes: [ 0xd5, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dlsa $2, $3, $4, 4" + + - + input: + bytes: [ 0x00, 0x50, 0x38, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0xde, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmod $2, $3, $4" + + - + input: + bytes: [ 0xdf, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmodu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x50, 0xa4, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0xdc, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmuh $2, $3, $4" + + - + input: + bytes: [ 0xdd, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmuhu $2, $3, $4" + + - + input: + bytes: [ 0x9c, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmul $2, $3, $4" + + - + input: + bytes: [ 0x9d, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmulu $2, $3, $4" + + - + input: + bytes: [ 0x24, 0x00, 0x71, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dvp $17" + + - + input: + bytes: [ 0x24, 0x00, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dvp $zero" + + - + input: + bytes: [ 0x20, 0x60, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x20, 0x60, 0x6e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x04, 0x00, 0x70, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "evp $16" + + - + input: + bytes: [ 0x04, 0x00, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "evp $zero" + + - + input: + bytes: [ 0x09, 0xfc, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x09, 0x24, 0xa0, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0x00, 0x00, 0x19, 0xf8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jalrc $25" + + - + input: + bytes: [ 0x00, 0x01, 0x05, 0xf8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jialc $5, 256" + + - + input: + bytes: [ 0x00, 0x01, 0x05, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jic $5, 256" + + - + input: + bytes: [ 0x00, 0x00, 0x1b, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jrc $27" + + - + input: + bytes: [ 0x09, 0x04, 0x80, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jr.hb $4" + + - + input: + bytes: [ 0x19, 0x00, 0x80, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lapc $4, 100" + + - + input: + bytes: [ 0x43, 0x0d, 0xc8, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ldc2 $8, -701($1)" + + - + input: + bytes: [ 0x48, 0x3c, 0x58, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ldpc $2, 123456" + + - + input: + bytes: [ 0xb6, 0xb3, 0x42, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ll $2, -153($18)" + + - + input: + bytes: [ 0x37, 0x38, 0xe0, 0x7f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lld $zero, 112($ra)" + + - + input: + bytes: [ 0xc5, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lsa $2, $3, $4, 4" + + - + input: + bytes: [ 0xb7, 0x34, 0x52, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0x43, 0x00, 0x48, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lwpc $2, 268" + + - + input: + bytes: [ 0x43, 0x00, 0x50, 0xec ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lwupc $2, 268" + + - + input: + bytes: [ 0x98, 0x18, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "maddf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x98, 0x18, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "maddf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x1f, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "maxa.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x1f, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "maxa.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x01, 0x78, 0x08, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x1c, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "min.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x1c, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "min.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x1e, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mina.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x1e, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mina.s $f0, $f2, $f4" + + - + input: + bytes: [ 0xda, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mod $2, $3, $4" + + - + input: + bytes: [ 0xdb, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "modu $2, $3, $4" + + - + input: + bytes: [ 0x25, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x2d, 0x78, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x01, 0x78, 0x89, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x99, 0x18, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "msubf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x99, 0x18, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "msubf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0xd8, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "muh $2, $3, $4" + + - + input: + bytes: [ 0xd9, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "muhu $2, $3, $4" + + - + input: + bytes: [ 0x98, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mul $2, $3, $4" + + - + input: + bytes: [ 0x99, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mulu $2, $3, $4" + + - + input: + bytes: [ 0x04, 0x00, 0x42, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x35, 0x04, 0xa1, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "pref 1, 8($5)" + + - + input: + bytes: [ 0x95, 0x34, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0xd5, 0xf0, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x9a, 0x20, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "rint.d $f2, $f4" + + - + input: + bytes: [ 0x9a, 0x20, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "rint.s $f2, $f4" + + - + input: + bytes: [ 0x96, 0xe0, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x16, 0x41, 0x00, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x26, 0xec, 0x6f, 0x7e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sc $15, -40($19)" + + - + input: + bytes: [ 0xa7, 0xe6, 0xaf, 0x7f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "scd $15, -51($sp)" + + - + input: + bytes: [ 0x0e, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sdbbp" + + - + input: + bytes: [ 0x8e, 0x08, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sdbbp 34" + + - + input: + bytes: [ 0x75, 0x92, 0xf4, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sdc2 $20, 629($18)" + + - + input: + bytes: [ 0x10, 0x08, 0x22, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sel.d $f0, $f1, $f2" + + - + input: + bytes: [ 0x10, 0x08, 0x02, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sel.s $f0, $f1, $f2" + + - + input: + bytes: [ 0x35, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "seleqz $2, $3, $4" + + - + input: + bytes: [ 0x14, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "seleqz.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x14, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "seleqz.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x37, 0x10, 0x64, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "selnez $2, $3, $4" + + - + input: + bytes: [ 0x17, 0x10, 0x24, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "selnez.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x17, 0x10, 0x04, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "selnez.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x40, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x30, 0x81, 0x79, 0x49 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "swc2 $25, 304($16)" + + - + input: + bytes: [ 0x0f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x4f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sync 1" + + - + input: + bytes: [ 0x34, 0x9b, 0xa7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x34, 0x00, 0x03, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x30, 0x55, 0xb3, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x30, 0x00, 0xea, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0xf1, 0x5e, 0x8e, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x31, 0x00, 0xdc, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x32, 0x00, 0xed, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x72, 0x21, 0x53, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x33, 0x00, 0x70, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x33, 0xfe, 0x1d, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x36, 0x00, 0xd1, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x76, 0xdd, 0xe8, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x05, 0x00, 0x17, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sigrie 5" diff --git a/tests/MC/Mips/valid-mips64r6.txt.yaml b/tests/MC/Mips/valid-mips64r6.txt.yaml new file mode 100644 index 0000000000..d30f308d3b --- /dev/null +++ b/tests/MC/Mips/valid-mips64r6.txt.yaml @@ -0,0 +1,2040 @@ +test_cases: + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sdbbp" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sync" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ssnop" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0x4f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sync 1" + + - + input: + bytes: [ 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ehb" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "pause" + + - + input: + bytes: [ 0x00, 0x00, 0x08, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sdbbp 34" + + - + input: + bytes: [ 0x00, 0x03, 0x00, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "teq $zero, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dneg $2, $3" + + - + input: + bytes: [ 0x00, 0x03, 0x10, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dnegu $2, $3" + + - + input: + bytes: [ 0x00, 0x53, 0x21, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tlt $2, $19, 133" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "seleqz $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "selnez $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mul $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mulu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "div $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "divu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmul $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmulu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ddiv $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ddivu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xc5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lsa $2, $3, $4, 4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dlsa $2, $3, $4, 4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "muh $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xd9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "muhu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xda ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mod $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xdb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "modu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xdc ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmuh $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xdd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmuhu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xde ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmod $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x64, 0x10, 0xdf ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmodu $2, $3, $4" + + - + input: + bytes: [ 0x00, 0x80, 0x04, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jr.hb $4" + + - + input: + bytes: [ 0xd8, 0x1b, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jrc $27" + + - + input: + bytes: [ 0x00, 0x80, 0xfc, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jalr.hb $4" + + - + input: + bytes: [ 0x00, 0xa0, 0x24, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jalr.hb $4, $5" + + - + input: + bytes: [ 0xf8, 0x19, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jalrc $25" + + - + input: + bytes: [ 0x00, 0xa0, 0x58, 0x51 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "clo $11, $5" + + - + input: + bytes: [ 0x00, 0xa7, 0x9b, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "teq $5, $7, 620" + + - + input: + bytes: [ 0x00, 0xb3, 0x55, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tge $5, $19, 340" + + - + input: + bytes: [ 0x00, 0xc0, 0x90, 0x53 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dclo $18, $6" + + - + input: + bytes: [ 0x00, 0xd1, 0x00, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tne $6, $17" + + - + input: + bytes: [ 0x00, 0xe8, 0xdd, 0x76 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tne $7, $8, 885" + + - + input: + bytes: [ 0x00, 0xea, 0x00, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tge $7, $10" + + - + input: + bytes: [ 0x01, 0x70, 0x00, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tltu $11, $16" + + - + input: + bytes: [ 0x01, 0xed, 0x00, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tlt $15, $13" + + - + input: + bytes: [ 0x02, 0x1d, 0xfe, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tltu $16, $sp, 1016" + + - + input: + bytes: [ 0x02, 0x8e, 0x5e, 0xf1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tgeu $20, $14, 379" + + - + input: + bytes: [ 0x02, 0xdc, 0x00, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tgeu $22, $gp" + + - + input: + bytes: [ 0x03, 0x20, 0x80, 0x52 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dclz $16, $25" + + - + input: + bytes: [ 0x03, 0x80, 0xe8, 0x50 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "clz $sp, $gp" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x03, 0xe0, 0x78, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "move $15, $ra" + + - + input: + bytes: [ 0x04, 0x11, 0x14, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bal 21108" + + - + input: + bytes: [ 0x04, 0x66, 0x56, 0x78 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dahi $3, $3, 22136" + + - + input: + bytes: [ 0x04, 0x7e, 0xab, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dati $3, $3, 43981" + + - + input: + bytes: [ 0x18, 0x02, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "blezalc $2, 1340" + + - + input: + bytes: [ 0x18, 0x02, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "blezalc $2, -16" + + - + input: + bytes: [ 0x18, 0x42, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgezalc $2, 1340" + + - + input: + bytes: [ 0x18, 0x42, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgezalc $2, -16" + + - + input: + bytes: [ 0x18, 0x43, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgeuc $2, $3, 264" + + - + input: + bytes: [ 0x18, 0x43, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgeuc $2, $3, -16" + + - + input: + bytes: [ 0x1c, 0x02, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgtzalc $2, 1340" + + - + input: + bytes: [ 0x1c, 0x02, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgtzalc $2, -16" + + - + input: + bytes: [ 0x1c, 0x42, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltzalc $2, 1340" + + - + input: + bytes: [ 0x1c, 0x42, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltzalc $2, -16" + + - + input: + bytes: [ 0x1c, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltuc $5, $6, 264" + + - + input: + bytes: [ 0x1c, 0xa6, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltuc $5, $6, -16" + + - + input: + bytes: [ 0x20, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $zero, $zero, 12" + + - + input: + bytes: [ 0x20, 0x02, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "beqzalc $2, 1340" + + - + input: + bytes: [ 0x20, 0x40, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $2, $zero, 12" + + - + input: + bytes: [ 0x20, 0x82, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $4, $2, 12" + + - + input: + bytes: [ 0x20, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "beqc $5, $6, 264" + + - + input: + bytes: [ 0x25, 0x29, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "addiu $9, $9, 10" + + - + input: + bytes: [ 0x30, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "andi $2, $2, 4" + + - + input: + bytes: [ 0x34, 0x42, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ori $2, $2, 4" + + - + input: + bytes: [ 0x3c, 0x43, 0xff, 0xe9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "aui $3, $2, 65513" + + - + input: + bytes: [ 0x40, 0x08, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mfc0 $8, $15, 1" + + - + input: + bytes: [ 0x40, 0x08, 0x80, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mfc0 $8, $16, 3" + + - + input: + bytes: [ 0x40, 0x38, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmfc0 $24, $10, 0" + + - + input: + bytes: [ 0x40, 0x89, 0x78, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mtc0 $9, $15, 1" + + - + input: + bytes: [ 0x40, 0xa4, 0x50, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dmtc0 $4, $10, 0" + + - + input: + bytes: [ 0x41, 0x60, 0x00, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dvp $zero" + + - + input: + bytes: [ 0x41, 0x60, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "evp $zero" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "di" + + - + input: + bytes: [ 0x41, 0x60, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ei" + + - + input: + bytes: [ 0x41, 0x6e, 0x60, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ei $14" + + - + input: + bytes: [ 0x41, 0x70, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "evp $16" + + - + input: + bytes: [ 0x41, 0x71, 0x00, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dvp $17" + + - + input: + bytes: [ 0x41, 0x7e, 0x60, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "di $fp" + + - + input: + bytes: [ 0x45, 0x20, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc1eqz $f0, 12" + + - + input: + bytes: [ 0x45, 0x3f, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc1eqz $f31, 12" + + - + input: + bytes: [ 0x45, 0xa0, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc1nez $f0, 12" + + - + input: + bytes: [ 0x45, 0xbf, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc1nez $f31, 12" + + - + input: + bytes: [ 0x46, 0x00, 0x20, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "rint.s $f2, $f4" + + - + input: + bytes: [ 0x46, 0x00, 0x20, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "class.s $f2, $f4" + + - + input: + bytes: [ 0x46, 0x02, 0x08, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sel.s $f0, $f1, $f2" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "seleqz.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "selnez.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "min.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "max.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mina.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x10, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "maxa.s $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x18, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "maddf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x04, 0x18, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "msubf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x20, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "rint.d $f2, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x20, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "class.d $f2, $f4" + + - + input: + bytes: [ 0x46, 0x22, 0x08, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sel.d $f0, $f1, $f2" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "seleqz.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "selnez.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "min.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "max.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "mina.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x10, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "maxa.d $f0, $f2, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x18, 0x98 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "maddf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x24, 0x18, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "msubf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.af.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.un.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.eq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x83 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ueq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.lt.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ult.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.le.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ule.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.saf.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sun.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.seq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sueq.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.slt.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sult.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sle.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x84, 0x18, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sule.s $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x80 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.af.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x81 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.un.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x82 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.eq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x83 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ueq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x84 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.lt.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x85 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ult.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x86 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.le.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x87 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.ule.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x88 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.saf.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x89 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sun.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.seq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sueq.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.slt.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sult.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sle.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0xa4, 0x18, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cmp.sule.d $f2, $f3, $f4" + + - + input: + bytes: [ 0x46, 0x20, 0x34, 0x95 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "recip.d $f18, $f6" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0xd5 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "recip.s $f3, $f30" + + - + input: + bytes: [ 0x46, 0x20, 0xe0, 0x96 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "rsqrt.d $f2, $f28" + + - + input: + bytes: [ 0x46, 0x00, 0x41, 0x16 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "rsqrt.s $f4, $f8" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "eretnc" + + - + input: + bytes: [ 0x49, 0x20, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc2eqz $0, 16" + + - + input: + bytes: [ 0x49, 0x3f, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc2eqz $31, 16" + + - + input: + bytes: [ 0x49, 0x52, 0x34, 0xb7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lwc2 $18, -841($6)" + + - + input: + bytes: [ 0x49, 0x79, 0x81, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "swc2 $25, 304($16)" + + - + input: + bytes: [ 0x49, 0xa0, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc2nez $0, 16" + + - + input: + bytes: [ 0x49, 0xbf, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc2nez $31, 16" + + - + input: + bytes: [ 0x49, 0xc8, 0x0d, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ldc2 $8, -701($1)" + + - + input: + bytes: [ 0x49, 0xf4, 0x92, 0x75 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sdc2 $20, 629($18)" + + - + input: + bytes: [ 0x58, 0x05, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "blezc $5, 264" + + - + input: + bytes: [ 0x58, 0x05, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "blezc $5, -16" + + - + input: + bytes: [ 0x58, 0x43, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgec $2, $3, 264" + + - + input: + bytes: [ 0x58, 0x43, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgec $2, $3, -16" + + - + input: + bytes: [ 0x58, 0xa5, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgezc $5, 264" + + - + input: + bytes: [ 0x58, 0xa5, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgezc $5, -16" + + - + input: + bytes: [ 0x5c, 0x05, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgtzc $5, 264" + + - + input: + bytes: [ 0x5c, 0x05, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bgtzc $5, -16" + + - + input: + bytes: [ 0x5c, 0xa5, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltzc $5, 264" + + - + input: + bytes: [ 0x5c, 0xa5, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltzc $5, -16" + + - + input: + bytes: [ 0x5c, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltc $5, $6, 264" + + - + input: + bytes: [ 0x5c, 0xa6, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bltc $5, $6, -16" + + - + input: + bytes: [ 0x60, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $zero, $zero, 12" + + - + input: + bytes: [ 0x60, 0x02, 0x01, 0x4e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnezalc $2, 1340" + + - + input: + bytes: [ 0x60, 0x40, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $2, $zero, 12" + + - + input: + bytes: [ 0x60, 0x82, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $4, $2, 12" + + - + input: + bytes: [ 0x60, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnec $5, $6, 264" + + - + input: + bytes: [ 0x60, 0x43, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnec $2, $3, -16" + + - + input: + bytes: [ 0x74, 0x43, 0x12, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "daui $3, $2, 4660" + + - + input: + bytes: [ 0x7c, 0x02, 0x20, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bitswap $4, $2" + + - + input: + bytes: [ 0x7c, 0x02, 0x20, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dbitswap $4, $2" + + - + input: + bytes: [ 0x7c, 0x43, 0x22, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "align $4, $2, $3, 2" + + - + input: + bytes: [ 0x7c, 0x43, 0x23, 0x64 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dalign $4, $2, $3, 5" + + - + input: + bytes: [ 0x7c, 0xa1, 0x04, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cache 1, 8($5)" + + - + input: + bytes: [ 0x7c, 0xa1, 0x04, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "pref 1, 8($5)" + + - + input: + bytes: [ 0x7e, 0x42, 0xb3, 0xb6 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ll $2, -153($18)" + + - + input: + bytes: [ 0x7e, 0x6f, 0xec, 0x26 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sc $15, -40($19)" + + - + input: + bytes: [ 0x7f, 0xaf, 0xe6, 0xa7 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "scd $15, -51($sp)" + + - + input: + bytes: [ 0x7f, 0xe0, 0x38, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lld $zero, 112($ra)" + + - + input: + bytes: [ 0xc8, 0x37, 0x96, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bc 14572264" + + - + input: + bytes: [ 0xd8, 0x05, 0x01, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jic $5, 256" + + - + input: + bytes: [ 0xd8, 0xa0, 0x46, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "beqzc $5, 72264" + + - + input: + bytes: [ 0xd8, 0x5f, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "beqzc $2, -16" + + - + input: + bytes: [ 0xe8, 0x37, 0x96, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "balc 14572264" + + - + input: + bytes: [ 0xec, 0x48, 0x00, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lwpc $2, 268" + + - + input: + bytes: [ 0xec, 0x50, 0x00, 0x43 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lwupc $2, 268" + + - + input: + bytes: [ 0xec, 0x58, 0x3c, 0x48 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "ldpc $2, 123456" + + - + input: + bytes: [ 0xec, 0x7e, 0xff, 0xff ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "auipc $3, -1" + + - + input: + bytes: [ 0xec, 0x7f, 0x00, 0x38 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "aluipc $3, 56" + + - + input: + bytes: [ 0xec, 0x80, 0x00, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lapc $4, 100" + + - + input: + bytes: [ 0xf8, 0x05, 0x01, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "jialc $5, 256" + + - + input: + bytes: [ 0xf8, 0xa0, 0x46, 0x91 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnezc $5, 72264" + + - + input: + bytes: [ 0xf8, 0x5f, 0xff, 0xfb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnezc $2, -16" + + - + input: + bytes: [ 0x04, 0x17, 0x00, 0x05 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sigrie 5" diff --git a/tests/MC/Mips/valid-r2-el.txt.yaml b/tests/MC/Mips/valid-r2-el.txt.yaml new file mode 100644 index 0000000000..8d15ad1244 --- /dev/null +++ b/tests/MC/Mips/valid-r2-el.txt.yaml @@ -0,0 +1,310 @@ +test_cases: + - + input: + bytes: [ 0xc1, 0x0b, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dmt" + + - + input: + bytes: [ 0xc1, 0x0b, 0x65, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dmt $5" + + - + input: + bytes: [ 0xe1, 0x0b, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "emt" + + - + input: + bytes: [ 0xe1, 0x0b, 0x64, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "emt $4" + + - + input: + bytes: [ 0x01, 0x00, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dvpe" + + - + input: + bytes: [ 0x01, 0x00, 0x66, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dvpe $6" + + - + input: + bytes: [ 0x21, 0x00, 0x60, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "evpe" + + - + input: + bytes: [ 0x21, 0x00, 0x64, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "evpe $4" + + - + input: + bytes: [ 0x08, 0x10, 0x65, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fork $2, $3, $5" + + - + input: + bytes: [ 0x09, 0x00, 0x80, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "yield $4" + + - + input: + bytes: [ 0x09, 0x20, 0xa0, 0x7c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "yield $4, $5" + + - + input: + bytes: [ 0x02, 0x20, 0x05, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $5, 0, 2, 0" + + - + input: + bytes: [ 0x20, 0x20, 0x05, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $5, 1, 0, 0" + + - + input: + bytes: [ 0x21, 0x20, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $zero, 1, 1, 0" + + - + input: + bytes: [ 0x21, 0x20, 0x0a, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $10, 1, 1, 0" + + - + input: + bytes: [ 0x22, 0x20, 0x0a, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $10, 1, 2, 0" + + - + input: + bytes: [ 0x32, 0x20, 0x0a, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $10, 1, 2, 1" + + - + input: + bytes: [ 0x23, 0x20, 0x1a, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $26, 1, 3, 0" + + - + input: + bytes: [ 0x23, 0x20, 0x1f, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $ra, 1, 3, 0" + + - + input: + bytes: [ 0x24, 0x20, 0x0e, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $14, 1, 4, 0" + + - + input: + bytes: [ 0x25, 0x20, 0x0f, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $15, 1, 5, 0" + + - + input: + bytes: [ 0x02, 0x28, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $5, 0, 2, 0" + + - + input: + bytes: [ 0x20, 0x28, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $5, 1, 0, 0" + + - + input: + bytes: [ 0x21, 0x00, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $zero, 1, 1, 0" + + - + input: + bytes: [ 0x21, 0x50, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $10, 1, 1, 0" + + - + input: + bytes: [ 0x22, 0x50, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $10, 1, 2, 0" + + - + input: + bytes: [ 0x32, 0x50, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $10, 1, 2, 1" + + - + input: + bytes: [ 0x23, 0xd0, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $26, 1, 3, 0" + + - + input: + bytes: [ 0x23, 0xf8, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $ra, 1, 3, 0" + + - + input: + bytes: [ 0x24, 0x70, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $14, 1, 4, 0" + + - + input: + bytes: [ 0x25, 0x78, 0x84, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $15, 1, 5, 0" diff --git a/tests/MC/Mips/valid-r2.txt.yaml b/tests/MC/Mips/valid-r2.txt.yaml new file mode 100644 index 0000000000..501c37704f --- /dev/null +++ b/tests/MC/Mips/valid-r2.txt.yaml @@ -0,0 +1,310 @@ +test_cases: + - + input: + bytes: [ 0x41, 0x60, 0x0b, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dmt" + + - + input: + bytes: [ 0x41, 0x65, 0x0b, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dmt $5" + + - + input: + bytes: [ 0x41, 0x60, 0x0b, 0xe1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "emt" + + - + input: + bytes: [ 0x41, 0x64, 0x0b, 0xe1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "emt $4" + + - + input: + bytes: [ 0x41, 0x60, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dvpe" + + - + input: + bytes: [ 0x41, 0x66, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dvpe $6" + + - + input: + bytes: [ 0x41, 0x60, 0x00, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "evpe" + + - + input: + bytes: [ 0x41, 0x64, 0x00, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "evpe $4" + + - + input: + bytes: [ 0x7c, 0x65, 0x10, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fork $2, $3, $5" + + - + input: + bytes: [ 0x7c, 0x80, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "yield $4" + + - + input: + bytes: [ 0x7c, 0xa0, 0x20, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "yield $4, $5" + + - + input: + bytes: [ 0x41, 0x05, 0x20, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $5, 0, 2, 0" + + - + input: + bytes: [ 0x41, 0x05, 0x20, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $5, 1, 0, 0" + + - + input: + bytes: [ 0x41, 0x00, 0x20, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $zero, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x0a, 0x20, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $10, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x0a, 0x20, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $10, 1, 2, 0" + + - + input: + bytes: [ 0x41, 0x0a, 0x20, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $10, 1, 2, 1" + + - + input: + bytes: [ 0x41, 0x1a, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $26, 1, 3, 0" + + - + input: + bytes: [ 0x41, 0x1f, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $ra, 1, 3, 0" + + - + input: + bytes: [ 0x41, 0x0e, 0x20, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $14, 1, 4, 0" + + - + input: + bytes: [ 0x41, 0x0f, 0x20, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $15, 1, 5, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x28, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $5, 0, 2, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x28, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $5, 1, 0, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x00, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $zero, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x50, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $10, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x50, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $10, 1, 2, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x50, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $10, 1, 2, 1" + + - + input: + bytes: [ 0x41, 0x84, 0xd0, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $26, 1, 3, 0" + + - + input: + bytes: [ 0x41, 0x84, 0xf8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $ra, 1, 3, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x70, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $14, 1, 4, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x78, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $15, 1, 5, 0" diff --git a/tests/MC/Mips/valid-xfail-mips32.txt.yaml b/tests/MC/Mips/valid-xfail-mips32.txt.yaml new file mode 100644 index 0000000000..4fb4de0112 --- /dev/null +++ b/tests/MC/Mips/valid-xfail-mips32.txt.yaml @@ -0,0 +1,150 @@ +test_cases: + - + input: + bytes: [ 0x46, 0x11, 0xc5, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.eq.s $fcc5, $f24, $f17" + + - + input: + bytes: [ 0x46, 0x07, 0xf4, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.f.s $fcc4, $f30, $f7" + + - + input: + bytes: [ 0x46, 0x04, 0xc6, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.le.s $fcc6, $f24, $f4" + + - + input: + bytes: [ 0x46, 0x0e, 0x8a, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.lt.s $fcc2, $f17, $f14" + + - + input: + bytes: [ 0x46, 0x08, 0x5b, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.nge.s $fcc3, $f11, $f8" + + - + input: + bytes: [ 0x46, 0x17, 0xfa, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ngl.s $fcc2, $f31, $f23" + + - + input: + bytes: [ 0x46, 0x17, 0x92, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ngle.s $fcc2, $f18, $f23" + + - + input: + bytes: [ 0x46, 0x0d, 0x45, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ngt.s $fcc5, $f8, $f13" + + - + input: + bytes: [ 0x46, 0x14, 0x3b, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ole.s $fcc3, $f7, $f20" + + - + input: + bytes: [ 0x46, 0x07, 0xa6, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.olt.s $fcc6, $f20, $f7" + + - + input: + bytes: [ 0x46, 0x19, 0x0f, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.seq.s $fcc7, $f1, $f25" + + - + input: + bytes: [ 0x46, 0x1e, 0x1e, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ueq.s $fcc6, $f3, $f30" + + - + input: + bytes: [ 0x46, 0x1e, 0xaf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ule.s $fcc7, $f21, $f30" + + - + input: + bytes: [ 0x46, 0x0a, 0xc7, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.ult.s $fcc7, $f24, $f10" + + - + input: + bytes: [ 0x46, 0x04, 0xf1, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c.un.s $fcc1, $f30, $f4" diff --git a/tests/MC/Mips/valid-xfail-mips32r2.txt.yaml b/tests/MC/Mips/valid-xfail-mips32r2.txt.yaml new file mode 100644 index 0000000000..22865f65b6 --- /dev/null +++ b/tests/MC/Mips/valid-xfail-mips32r2.txt.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x46, 0x11, 0xc5, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.eq.s $fcc5, $f24, $f17" + + - + input: + bytes: [ 0x46, 0x07, 0xf4, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.f.s $fcc4, $f30, $f7" + + - + input: + bytes: [ 0x46, 0x04, 0xc6, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.le.s $fcc6, $f24, $f4" + + - + input: + bytes: [ 0x46, 0x0e, 0x8a, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.lt.s $fcc2, $f17, $f14" + + - + input: + bytes: [ 0x46, 0x08, 0x5b, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.nge.s $fcc3, $f11, $f8" + + - + input: + bytes: [ 0x46, 0x17, 0xfa, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $fcc2, $f31, $f23" + + - + input: + bytes: [ 0x46, 0x17, 0x92, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $fcc2, $f18, $f23" + + - + input: + bytes: [ 0x46, 0x0d, 0x45, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $fcc5, $f8, $f13" + + - + input: + bytes: [ 0x46, 0x14, 0x3b, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ole.s $fcc3, $f7, $f20" + + - + input: + bytes: [ 0x46, 0x07, 0xa6, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.olt.s $fcc6, $f20, $f7" + + - + input: + bytes: [ 0x46, 0x19, 0x0f, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.seq.s $fcc7, $f1, $f25" + + - + input: + bytes: [ 0x46, 0x1e, 0x1e, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $fcc6, $f3, $f30" + + - + input: + bytes: [ 0x46, 0x1e, 0xaf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ule.s $fcc7, $f21, $f30" + + - + input: + bytes: [ 0x46, 0x0a, 0xc7, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.ult.s $fcc7, $f24, $f10" + + - + input: + bytes: [ 0x46, 0x04, 0xf1, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "c.un.s $fcc1, $f30, $f4" + + - + input: + bytes: [ 0x02, 0xa7, 0x68, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "rotrv $13, $7, $21" diff --git a/tests/MC/Mips/valid-xfail-mips32r3.txt.yaml b/tests/MC/Mips/valid-xfail-mips32r3.txt.yaml new file mode 100644 index 0000000000..da59d822fb --- /dev/null +++ b/tests/MC/Mips/valid-xfail-mips32r3.txt.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x46, 0x11, 0xc5, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.eq.s $fcc5, $f24, $f17" + + - + input: + bytes: [ 0x46, 0x07, 0xf4, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.f.s $fcc4, $f30, $f7" + + - + input: + bytes: [ 0x46, 0x04, 0xc6, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.le.s $fcc6, $f24, $f4" + + - + input: + bytes: [ 0x46, 0x0e, 0x8a, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.lt.s $fcc2, $f17, $f14" + + - + input: + bytes: [ 0x46, 0x08, 0x5b, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.nge.s $fcc3, $f11, $f8" + + - + input: + bytes: [ 0x46, 0x17, 0xfa, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngl.s $fcc2, $f31, $f23" + + - + input: + bytes: [ 0x46, 0x17, 0x92, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngle.s $fcc2, $f18, $f23" + + - + input: + bytes: [ 0x46, 0x0d, 0x45, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ngt.s $fcc5, $f8, $f13" + + - + input: + bytes: [ 0x46, 0x14, 0x3b, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ole.s $fcc3, $f7, $f20" + + - + input: + bytes: [ 0x46, 0x07, 0xa6, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.olt.s $fcc6, $f20, $f7" + + - + input: + bytes: [ 0x46, 0x19, 0x0f, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.seq.s $fcc7, $f1, $f25" + + - + input: + bytes: [ 0x46, 0x1e, 0x1e, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ueq.s $fcc6, $f3, $f30" + + - + input: + bytes: [ 0x46, 0x1e, 0xaf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ule.s $fcc7, $f21, $f30" + + - + input: + bytes: [ 0x46, 0x0a, 0xc7, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.ult.s $fcc7, $f24, $f10" + + - + input: + bytes: [ 0x46, 0x04, 0xf1, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "c.un.s $fcc1, $f30, $f4" + + - + input: + bytes: [ 0x02, 0xa7, 0x68, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "rotrv $13, $7, $21" diff --git a/tests/MC/Mips/valid-xfail-mips32r5.txt.yaml b/tests/MC/Mips/valid-xfail-mips32r5.txt.yaml new file mode 100644 index 0000000000..e1d9613f2c --- /dev/null +++ b/tests/MC/Mips/valid-xfail-mips32r5.txt.yaml @@ -0,0 +1,160 @@ +test_cases: + - + input: + bytes: [ 0x46, 0x11, 0xc5, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.eq.s $fcc5, $f24, $f17" + + - + input: + bytes: [ 0x46, 0x07, 0xf4, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.f.s $fcc4, $f30, $f7" + + - + input: + bytes: [ 0x46, 0x04, 0xc6, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.le.s $fcc6, $f24, $f4" + + - + input: + bytes: [ 0x46, 0x0e, 0x8a, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.lt.s $fcc2, $f17, $f14" + + - + input: + bytes: [ 0x46, 0x08, 0x5b, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.nge.s $fcc3, $f11, $f8" + + - + input: + bytes: [ 0x46, 0x17, 0xfa, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngl.s $fcc2, $f31, $f23" + + - + input: + bytes: [ 0x46, 0x17, 0x92, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngle.s $fcc2, $f18, $f23" + + - + input: + bytes: [ 0x46, 0x0d, 0x45, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ngt.s $fcc5, $f8, $f13" + + - + input: + bytes: [ 0x46, 0x14, 0x3b, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ole.s $fcc3, $f7, $f20" + + - + input: + bytes: [ 0x46, 0x07, 0xa6, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.olt.s $fcc6, $f20, $f7" + + - + input: + bytes: [ 0x46, 0x19, 0x0f, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.seq.s $fcc7, $f1, $f25" + + - + input: + bytes: [ 0x46, 0x1e, 0x1e, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ueq.s $fcc6, $f3, $f30" + + - + input: + bytes: [ 0x46, 0x1e, 0xaf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ule.s $fcc7, $f21, $f30" + + - + input: + bytes: [ 0x46, 0x0a, 0xc7, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.ult.s $fcc7, $f24, $f10" + + - + input: + bytes: [ 0x46, 0x04, 0xf1, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "c.un.s $fcc1, $f30, $f4" + + - + input: + bytes: [ 0x02, 0xa7, 0x68, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "rotrv $13, $7, $21" diff --git a/tests/MC/Mips/valid-xfail-mips32r6.txt.yaml b/tests/MC/Mips/valid-xfail-mips32r6.txt.yaml new file mode 100644 index 0000000000..bf719ace00 --- /dev/null +++ b/tests/MC/Mips/valid-xfail-mips32r6.txt.yaml @@ -0,0 +1,100 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x40, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $2, $zero, 12" + + - + input: + bytes: [ 0x20, 0x82, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $4, $2, 12" + + - + input: + bytes: [ 0x60, 0x40, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $2, $zero, 12" + + - + input: + bytes: [ 0x60, 0x82, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $4, $2, 12" + + - + input: + bytes: [ 0x20, 0xc0, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $6, $zero, 264" + + - + input: + bytes: [ 0x20, 0xa0, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bovc $5, $zero, 264" + + - + input: + bytes: [ 0x20, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "beqc $5, $6, 264" + + - + input: + bytes: [ 0x60, 0xc0, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $6, $zero, 264" + + - + input: + bytes: [ 0x60, 0xa0, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnvc $5, $zero, 264" + + - + input: + bytes: [ 0x60, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "bnec $5, $6, 264" diff --git a/tests/MC/Mips/valid-xfail-mips64r2.txt.yaml b/tests/MC/Mips/valid-xfail-mips64r2.txt.yaml new file mode 100644 index 0000000000..55a34c5834 --- /dev/null +++ b/tests/MC/Mips/valid-xfail-mips64r2.txt.yaml @@ -0,0 +1,390 @@ +test_cases: + - + input: + bytes: [ 0x46, 0x2f, 0x79, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.d $fcc1, $f15, $f15" + + - + input: + bytes: [ 0x46, 0x11, 0xc5, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.eq.s $fcc5, $f24, $f17" + + - + input: + bytes: [ 0x46, 0x35, 0x5c, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.d $fcc4, $f11, $f21" + + - + input: + bytes: [ 0x46, 0x07, 0xf4, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.f.s $fcc4, $f30, $f7" + + - + input: + bytes: [ 0x46, 0x21, 0x94, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.d $fcc4, $f18, $f1" + + - + input: + bytes: [ 0x46, 0x04, 0xc6, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.le.s $fcc6, $f24, $f4" + + - + input: + bytes: [ 0x46, 0x23, 0x4b, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.d $fcc3, $f9, $f3" + + - + input: + bytes: [ 0x46, 0x0e, 0x8a, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.lt.s $fcc2, $f17, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0xad, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.d $fcc5, $f21, $f16" + + - + input: + bytes: [ 0x46, 0x08, 0x5b, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.nge.s $fcc3, $f11, $f8" + + - + input: + bytes: [ 0x46, 0x17, 0xfa, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngl.s $fcc2, $f31, $f23" + + - + input: + bytes: [ 0x46, 0x17, 0x92, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngle.s $fcc2, $f18, $f23" + + - + input: + bytes: [ 0x46, 0x27, 0xc4, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.d $fcc4, $f24, $f7" + + - + input: + bytes: [ 0x46, 0x0d, 0x45, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ngt.s $fcc5, $f8, $f13" + + - + input: + bytes: [ 0x46, 0x3f, 0x82, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.d $fcc2, $f16, $f31" + + - + input: + bytes: [ 0x46, 0x14, 0x3b, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ole.s $fcc3, $f7, $f20" + + - + input: + bytes: [ 0x46, 0x3c, 0x9c, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.d $fcc4, $f19, $f28" + + - + input: + bytes: [ 0x46, 0x07, 0xa6, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.olt.s $fcc6, $f20, $f7" + + - + input: + bytes: [ 0x46, 0x27, 0xfc, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.d $fcc4, $f31, $f7" + + - + input: + bytes: [ 0x46, 0x19, 0x0f, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.seq.s $fcc7, $f1, $f25" + + - + input: + bytes: [ 0x46, 0x39, 0x6c, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.d $fcc4, $f13, $f25" + + - + input: + bytes: [ 0x46, 0x1e, 0x1e, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ueq.s $fcc6, $f3, $f30" + + - + input: + bytes: [ 0x46, 0x32, 0xcf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.d $fcc7, $f25, $f18" + + - + input: + bytes: [ 0x46, 0x1e, 0xaf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ule.s $fcc7, $f21, $f30" + + - + input: + bytes: [ 0x46, 0x31, 0x36, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.d $fcc6, $f6, $f17" + + - + input: + bytes: [ 0x46, 0x0a, 0xc7, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.ult.s $fcc7, $f24, $f10" + + - + input: + bytes: [ 0x46, 0x38, 0xbe, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.d $fcc6, $f23, $f24" + + - + input: + bytes: [ 0x46, 0x04, 0xf1, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "c.un.s $fcc1, $f30, $f4" + + - + input: + bytes: [ 0x46, 0xc0, 0x17, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.pl $f30, $f2" + + - + input: + bytes: [ 0x46, 0xc0, 0xd3, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cvt.s.pu $f14, $f26" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x46, 0xde, 0x46, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pll.ps $f24, $f8, $f30" + + - + input: + bytes: [ 0x46, 0xdc, 0xd0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "plu.ps $f0, $f26, $f28" + + - + input: + bytes: [ 0x46, 0xda, 0xf2, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "pul.ps $f8, $f30, $f26" + + - + input: + bytes: [ 0x46, 0xc2, 0x46, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "puu.ps $f24, $f8, $f2" + + - + input: + bytes: [ 0x02, 0xa7, 0x68, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "rotrv $13, $7, $21" diff --git a/tests/MC/Mips/valid-xfail-mips64r3.txt.yaml b/tests/MC/Mips/valid-xfail-mips64r3.txt.yaml new file mode 100644 index 0000000000..44b114f12e --- /dev/null +++ b/tests/MC/Mips/valid-xfail-mips64r3.txt.yaml @@ -0,0 +1,390 @@ +test_cases: + - + input: + bytes: [ 0x46, 0x2f, 0x79, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.eq.d $fcc1, $f15, $f15" + + - + input: + bytes: [ 0x46, 0x11, 0xc5, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.eq.s $fcc5, $f24, $f17" + + - + input: + bytes: [ 0x46, 0x35, 0x5c, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.f.d $fcc4, $f11, $f21" + + - + input: + bytes: [ 0x46, 0x07, 0xf4, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.f.s $fcc4, $f30, $f7" + + - + input: + bytes: [ 0x46, 0x21, 0x94, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.le.d $fcc4, $f18, $f1" + + - + input: + bytes: [ 0x46, 0x04, 0xc6, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.le.s $fcc6, $f24, $f4" + + - + input: + bytes: [ 0x46, 0x23, 0x4b, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.lt.d $fcc3, $f9, $f3" + + - + input: + bytes: [ 0x46, 0x0e, 0x8a, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.lt.s $fcc2, $f17, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0xad, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.nge.d $fcc5, $f21, $f16" + + - + input: + bytes: [ 0x46, 0x08, 0x5b, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.nge.s $fcc3, $f11, $f8" + + - + input: + bytes: [ 0x46, 0x17, 0xfa, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngl.s $fcc2, $f31, $f23" + + - + input: + bytes: [ 0x46, 0x17, 0x92, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngle.s $fcc2, $f18, $f23" + + - + input: + bytes: [ 0x46, 0x27, 0xc4, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngt.d $fcc4, $f24, $f7" + + - + input: + bytes: [ 0x46, 0x0d, 0x45, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ngt.s $fcc5, $f8, $f13" + + - + input: + bytes: [ 0x46, 0x3f, 0x82, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ole.d $fcc2, $f16, $f31" + + - + input: + bytes: [ 0x46, 0x14, 0x3b, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ole.s $fcc3, $f7, $f20" + + - + input: + bytes: [ 0x46, 0x3c, 0x9c, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.olt.d $fcc4, $f19, $f28" + + - + input: + bytes: [ 0x46, 0x07, 0xa6, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.olt.s $fcc6, $f20, $f7" + + - + input: + bytes: [ 0x46, 0x27, 0xfc, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.seq.d $fcc4, $f31, $f7" + + - + input: + bytes: [ 0x46, 0x19, 0x0f, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.seq.s $fcc7, $f1, $f25" + + - + input: + bytes: [ 0x46, 0x39, 0x6c, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ueq.d $fcc4, $f13, $f25" + + - + input: + bytes: [ 0x46, 0x1e, 0x1e, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ueq.s $fcc6, $f3, $f30" + + - + input: + bytes: [ 0x46, 0x32, 0xcf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ule.d $fcc7, $f25, $f18" + + - + input: + bytes: [ 0x46, 0x1e, 0xaf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ule.s $fcc7, $f21, $f30" + + - + input: + bytes: [ 0x46, 0x31, 0x36, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ult.d $fcc6, $f6, $f17" + + - + input: + bytes: [ 0x46, 0x0a, 0xc7, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.ult.s $fcc7, $f24, $f10" + + - + input: + bytes: [ 0x46, 0x38, 0xbe, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.un.d $fcc6, $f23, $f24" + + - + input: + bytes: [ 0x46, 0x04, 0xf1, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "c.un.s $fcc1, $f30, $f4" + + - + input: + bytes: [ 0x46, 0xc0, 0x17, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.pl $f30, $f2" + + - + input: + bytes: [ 0x46, 0xc0, 0xd3, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cvt.s.pu $f14, $f26" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x46, 0xde, 0x46, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "pll.ps $f24, $f8, $f30" + + - + input: + bytes: [ 0x46, 0xdc, 0xd0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "plu.ps $f0, $f26, $f28" + + - + input: + bytes: [ 0x46, 0xda, 0xf2, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "pul.ps $f8, $f30, $f26" + + - + input: + bytes: [ 0x46, 0xc2, 0x46, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "puu.ps $f24, $f8, $f2" + + - + input: + bytes: [ 0x02, 0xa7, 0x68, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "rotrv $13, $7, $21" diff --git a/tests/MC/Mips/valid-xfail-mips64r5.txt.yaml b/tests/MC/Mips/valid-xfail-mips64r5.txt.yaml new file mode 100644 index 0000000000..9cde0d73be --- /dev/null +++ b/tests/MC/Mips/valid-xfail-mips64r5.txt.yaml @@ -0,0 +1,390 @@ +test_cases: + - + input: + bytes: [ 0x46, 0x2f, 0x79, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.eq.d $fcc1, $f15, $f15" + + - + input: + bytes: [ 0x46, 0x11, 0xc5, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.eq.s $fcc5, $f24, $f17" + + - + input: + bytes: [ 0x46, 0x35, 0x5c, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.f.d $fcc4, $f11, $f21" + + - + input: + bytes: [ 0x46, 0x07, 0xf4, 0x30 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.f.s $fcc4, $f30, $f7" + + - + input: + bytes: [ 0x46, 0x21, 0x94, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.le.d $fcc4, $f18, $f1" + + - + input: + bytes: [ 0x46, 0x04, 0xc6, 0x3e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.le.s $fcc6, $f24, $f4" + + - + input: + bytes: [ 0x46, 0x23, 0x4b, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.lt.d $fcc3, $f9, $f3" + + - + input: + bytes: [ 0x46, 0x0e, 0x8a, 0x3c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.lt.s $fcc2, $f17, $f14" + + - + input: + bytes: [ 0x46, 0x30, 0xad, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.nge.d $fcc5, $f21, $f16" + + - + input: + bytes: [ 0x46, 0x08, 0x5b, 0x3d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.nge.s $fcc3, $f11, $f8" + + - + input: + bytes: [ 0x46, 0x17, 0xfa, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngl.s $fcc2, $f31, $f23" + + - + input: + bytes: [ 0x46, 0x17, 0x92, 0x39 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngle.s $fcc2, $f18, $f23" + + - + input: + bytes: [ 0x46, 0x27, 0xc4, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngt.d $fcc4, $f24, $f7" + + - + input: + bytes: [ 0x46, 0x0d, 0x45, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ngt.s $fcc5, $f8, $f13" + + - + input: + bytes: [ 0x46, 0x3f, 0x82, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ole.d $fcc2, $f16, $f31" + + - + input: + bytes: [ 0x46, 0x14, 0x3b, 0x36 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ole.s $fcc3, $f7, $f20" + + - + input: + bytes: [ 0x46, 0x3c, 0x9c, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.olt.d $fcc4, $f19, $f28" + + - + input: + bytes: [ 0x46, 0x07, 0xa6, 0x34 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.olt.s $fcc6, $f20, $f7" + + - + input: + bytes: [ 0x46, 0x27, 0xfc, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.seq.d $fcc4, $f31, $f7" + + - + input: + bytes: [ 0x46, 0x19, 0x0f, 0x3a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.seq.s $fcc7, $f1, $f25" + + - + input: + bytes: [ 0x46, 0x39, 0x6c, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ueq.d $fcc4, $f13, $f25" + + - + input: + bytes: [ 0x46, 0x1e, 0x1e, 0x33 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ueq.s $fcc6, $f3, $f30" + + - + input: + bytes: [ 0x46, 0x32, 0xcf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ule.d $fcc7, $f25, $f18" + + - + input: + bytes: [ 0x46, 0x1e, 0xaf, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ule.s $fcc7, $f21, $f30" + + - + input: + bytes: [ 0x46, 0x31, 0x36, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ult.d $fcc6, $f6, $f17" + + - + input: + bytes: [ 0x46, 0x0a, 0xc7, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.ult.s $fcc7, $f24, $f10" + + - + input: + bytes: [ 0x46, 0x38, 0xbe, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.un.d $fcc6, $f23, $f24" + + - + input: + bytes: [ 0x46, 0x04, 0xf1, 0x31 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "c.un.s $fcc1, $f30, $f4" + + - + input: + bytes: [ 0x46, 0xc0, 0x17, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.pl $f30, $f2" + + - + input: + bytes: [ 0x46, 0xc0, 0xd3, 0xa0 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cvt.s.pu $f14, $f26" + + - + input: + bytes: [ 0x4e, 0x94, 0xd4, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "madd.d $f18, $f20, $f26, $f20" + + - + input: + bytes: [ 0x4c, 0x52, 0xf2, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "msub.d $f10, $f2, $f30, $f18" + + - + input: + bytes: [ 0x4d, 0x54, 0x74, 0xb1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nmadd.d $f18, $f10, $f14, $f20" + + - + input: + bytes: [ 0x4d, 0x1e, 0x87, 0xb9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "nmsub.d $f30, $f8, $f16, $f30" + + - + input: + bytes: [ 0x46, 0xde, 0x46, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "pll.ps $f24, $f8, $f30" + + - + input: + bytes: [ 0x46, 0xdc, 0xd0, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "plu.ps $f0, $f26, $f28" + + - + input: + bytes: [ 0x46, 0xda, 0xf2, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "pul.ps $f8, $f30, $f26" + + - + input: + bytes: [ 0x46, 0xc2, 0x46, 0x2f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "puu.ps $f24, $f8, $f2" + + - + input: + bytes: [ 0x02, 0xa7, 0x68, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "rotrv $13, $7, $21" diff --git a/tests/MC/Mips/valid-xfail-mips64r6.txt.yaml b/tests/MC/Mips/valid-xfail-mips64r6.txt.yaml new file mode 100644 index 0000000000..59ef200f3e --- /dev/null +++ b/tests/MC/Mips/valid-xfail-mips64r6.txt.yaml @@ -0,0 +1,150 @@ +test_cases: + - + input: + bytes: [ 0x20, 0x40, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $2, $zero, 12" + + - + input: + bytes: [ 0x20, 0x82, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $4, $2, 12" + + - + input: + bytes: [ 0x60, 0x40, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $2, $zero, 12" + + - + input: + bytes: [ 0x60, 0x82, 0x00, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $4, $2, 12" + + - + input: + bytes: [ 0x20, 0xc0, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $6, $zero, 264" + + - + input: + bytes: [ 0x20, 0xa0, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bovc $5, $zero, 264" + + - + input: + bytes: [ 0x20, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "beqc $5, $6, 264" + + - + input: + bytes: [ 0x60, 0xc0, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $6, $zero, 264" + + - + input: + bytes: [ 0x60, 0xa0, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnvc $5, $zero, 264" + + - + input: + bytes: [ 0x60, 0xa6, 0x00, 0x41 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "bnec $5, $6, 264" + + - + input: + bytes: [ 0x64, 0x58, 0x46, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "daddiu $24, $2, 18079" + + - + input: + bytes: [ 0x66, 0x73, 0x69, 0x3f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "daddiu $19, $19, 26943" + + - + input: + bytes: [ 0x65, 0x6f, 0xec, 0x5f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "daddiu $15, $11, -5025" + + - + input: + bytes: [ 0x65, 0xce, 0x11, 0xea ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "daddiu $14, $14, 4586" + + - + input: + bytes: [ 0x04, 0x7e, 0xab, 0xcd ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "dati $3, $3, 43981" diff --git a/tests/MC/Mips/valid-xfail.txt.yaml b/tests/MC/Mips/valid-xfail.txt.yaml new file mode 100644 index 0000000000..bb87efde55 --- /dev/null +++ b/tests/MC/Mips/valid-xfail.txt.yaml @@ -0,0 +1,120 @@ +test_cases: + - + input: + bytes: [ 0x10, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "b 16" + + - + input: + bytes: [ 0x10, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "b 28" + + - + input: + bytes: [ 0x10, 0x00, 0x28, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "b 41004" + + - + input: + bytes: [ 0x10, 0x04, 0x14, 0xe2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "beq $zero, $4, 21388" + + - + input: + bytes: [ 0x11, 0x00, 0x00, 0xc4 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "beqz $8, 788" + + - + input: + bytes: [ 0x12, 0x88, 0x00, 0x17 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "beq $20, $8, 96" + + - + input: + bytes: [ 0x15, 0x00, 0x88, 0x14 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bnez $8, -122796" + + - + input: + bytes: [ 0x15, 0x8a, 0x9f, 0x8a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "bne $12, $10, -98772" + + - + input: + bytes: [ 0x50, 0xc7, 0x07, 0xf3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "beql $6, $7, 8144" + + - + input: + bytes: [ 0x7c, 0x48, 0xc7, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ext $8, $2, 28, 25" + + - + input: + bytes: [ 0xc2, 0x44, 0xe3, 0x67 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "ll $4, -7321($18)" + + - + input: + bytes: [ 0xe2, 0x64, 0x49, 0xd8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sc $4, 18904($19)" diff --git a/tests/MC/Mips/valid.s.yaml b/tests/MC/Mips/valid.s.yaml new file mode 100644 index 0000000000..501c37704f --- /dev/null +++ b/tests/MC/Mips/valid.s.yaml @@ -0,0 +1,310 @@ +test_cases: + - + input: + bytes: [ 0x41, 0x60, 0x0b, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dmt" + + - + input: + bytes: [ 0x41, 0x65, 0x0b, 0xc1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dmt $5" + + - + input: + bytes: [ 0x41, 0x60, 0x0b, 0xe1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "emt" + + - + input: + bytes: [ 0x41, 0x64, 0x0b, 0xe1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "emt $4" + + - + input: + bytes: [ 0x41, 0x60, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dvpe" + + - + input: + bytes: [ 0x41, 0x66, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "dvpe $6" + + - + input: + bytes: [ 0x41, 0x60, 0x00, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "evpe" + + - + input: + bytes: [ 0x41, 0x64, 0x00, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "evpe $4" + + - + input: + bytes: [ 0x7c, 0x65, 0x10, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "fork $2, $3, $5" + + - + input: + bytes: [ 0x7c, 0x80, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "yield $4" + + - + input: + bytes: [ 0x7c, 0xa0, 0x20, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "yield $4, $5" + + - + input: + bytes: [ 0x41, 0x05, 0x20, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $5, 0, 2, 0" + + - + input: + bytes: [ 0x41, 0x05, 0x20, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $5, 1, 0, 0" + + - + input: + bytes: [ 0x41, 0x00, 0x20, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $zero, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x0a, 0x20, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $10, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x0a, 0x20, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $10, 1, 2, 0" + + - + input: + bytes: [ 0x41, 0x0a, 0x20, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $10, 1, 2, 1" + + - + input: + bytes: [ 0x41, 0x1a, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $26, 1, 3, 0" + + - + input: + bytes: [ 0x41, 0x1f, 0x20, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $ra, 1, 3, 0" + + - + input: + bytes: [ 0x41, 0x0e, 0x20, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $14, 1, 4, 0" + + - + input: + bytes: [ 0x41, 0x0f, 0x20, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mftr $4, $15, 1, 5, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x28, 0x02 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $5, 0, 2, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x28, 0x20 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $5, 1, 0, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x00, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $zero, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x50, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $10, 1, 1, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x50, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $10, 1, 2, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x50, 0x32 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $10, 1, 2, 1" + + - + input: + bytes: [ 0x41, 0x84, 0xd0, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $26, 1, 3, 0" + + - + input: + bytes: [ 0x41, 0x84, 0xf8, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $ra, 1, 3, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x70, 0x24 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $14, 1, 4, 0" + + - + input: + bytes: [ 0x41, 0x84, 0x78, 0x25 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "mttr $4, $15, 1, 5, 0" diff --git a/tests/MC/Mips/valid.txt.yaml b/tests/MC/Mips/valid.txt.yaml new file mode 100644 index 0000000000..933101bc8d --- /dev/null +++ b/tests/MC/Mips/valid.txt.yaml @@ -0,0 +1,280 @@ +test_cases: + - + input: + bytes: [ 0xca, 0x76, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "bbit0 $19, 22, 8" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "baddu $9, $6, $7" + + - + input: + bytes: [ 0xd9, 0x0a, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "bbit032 $8, 10, 8" + + - + input: + bytes: [ 0xe8, 0x7f, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "bbit1 $3, 31, 8" + + - + input: + bytes: [ 0xfb, 0x0a, 0x00, 0x01 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "bbit132 $24, 10, 8" + + - + input: + bytes: [ 0x71, 0x29, 0xec, 0x72 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "cins $9, $9, 17, 29" + + - + input: + bytes: [ 0x70, 0x4f, 0x44, 0xb3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "cins32 $15, $2, 18, 8" + + - + input: + bytes: [ 0x70, 0xc7, 0x48, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "dmul $9, $6, $7" + + - + input: + bytes: [ 0x48, 0x22, 0x00, 0x40 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "dmfc2 $2, 64" + + - + input: + bytes: [ 0x48, 0xa2, 0x40, 0x47 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "dmtc2 $2, 16455" + + - + input: + bytes: [ 0x70, 0xc0, 0x48, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "dpop $9, $6" + + - + input: + bytes: [ 0x71, 0xef, 0x34, 0x7a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "exts $15, $15, 17, 6" + + - + input: + bytes: [ 0x71, 0xa4, 0x42, 0xbb ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "exts32 $4, $13, 10, 8" + + - + input: + bytes: [ 0x71, 0xe0, 0x00, 0x08 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtm0 $15" + + - + input: + bytes: [ 0x72, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtm1 $16" + + - + input: + bytes: [ 0x72, 0x20, 0x00, 0x0d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtm2 $17" + + - + input: + bytes: [ 0x72, 0x40, 0x00, 0x09 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtp0 $18" + + - + input: + bytes: [ 0x72, 0x60, 0x00, 0x0a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtp1 $19" + + - + input: + bytes: [ 0x72, 0x80, 0x00, 0x0b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "mtp2 $20" + + - + input: + bytes: [ 0x70, 0xc0, 0x48, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "pop $9, $6" + + - + input: + bytes: [ 0x72, 0xf8, 0xc8, 0x2a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "seq $25, $23, $24" + + - + input: + bytes: [ 0x72, 0x10, 0x09, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "seqi $16, $16, 38" + + - + input: + bytes: [ 0x72, 0xf4, 0xb8, 0x2b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "sne $23, $23, $20" + + - + input: + bytes: [ 0x72, 0x04, 0xb1, 0xef ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "snei $4, $16, -313" + + - + input: + bytes: [ 0x00, 0x00, 0x01, 0x8f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "sync 6" + + - + input: + bytes: [ 0x71, 0x55, 0xa8, 0x11 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "v3mulu $21, $10, $21" + + - + input: + bytes: [ 0x72, 0x70, 0x18, 0x10 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "vmm0 $3, $19, $16" + + - + input: + bytes: [ 0x73, 0x66, 0xd8, 0x0f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_OCTEON" ] + expected: + insns: + - + asm_text: "vmulu $27, $27, $6" diff --git a/tests/MC/Mips/valid_R6-eva.txt.yaml b/tests/MC/Mips/valid_R6-eva.txt.yaml new file mode 100644 index 0000000000..70d1389b3a --- /dev/null +++ b/tests/MC/Mips/valid_R6-eva.txt.yaml @@ -0,0 +1,700 @@ +test_cases: + - + input: + bytes: [ 0x7c, 0xff, 0x7f, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cachee 31, 255($7)" + + - + input: + bytes: [ 0x7c, 0x80, 0x80, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cachee 0, -256($4)" + + - + input: + bytes: [ 0x7c, 0x85, 0xba, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "cachee 5, -140($4)" + + - + input: + bytes: [ 0x7f, 0x2a, 0x80, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lbe $10, -256($25)" + + - + input: + bytes: [ 0x7d, 0xed, 0x7f, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lbe $13, 255($15)" + + - + input: + bytes: [ 0x7d, 0xcb, 0x49, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lbe $11, 146($14)" + + - + input: + bytes: [ 0x7c, 0x6d, 0x80, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lbue $13, -256($3)" + + - + input: + bytes: [ 0x7c, 0x4d, 0x7f, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lbue $13, 255($2)" + + - + input: + bytes: [ 0x7c, 0x6d, 0xa1, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lbue $13, -190($3)" + + - + input: + bytes: [ 0x7e, 0xad, 0x80, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lhe $13, -256($21)" + + - + input: + bytes: [ 0x7e, 0x0c, 0x7f, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lhe $12, 255($16)" + + - + input: + bytes: [ 0x7e, 0x0d, 0x28, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lhe $13, 81($16)" + + - + input: + bytes: [ 0x7c, 0x72, 0x80, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lhue $18, -256($3)" + + - + input: + bytes: [ 0x7c, 0x72, 0x7f, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lhue $18, 255($3)" + + - + input: + bytes: [ 0x7c, 0x56, 0xac, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lhue $22, -168($2)" + + - + input: + bytes: [ 0x7e, 0xa2, 0x80, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lle $2, -256($21)" + + - + input: + bytes: [ 0x7e, 0x63, 0x7f, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lle $3, 255($19)" + + - + input: + bytes: [ 0x7e, 0xc3, 0xdc, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "lle $3, -71($22)" + + - + input: + bytes: [ 0x7c, 0x4e, 0x80, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "prefe 14, -256($2)" + + - + input: + bytes: [ 0x7c, 0x6b, 0x7f, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "prefe 11, 255($3)" + + - + input: + bytes: [ 0x7c, 0x6e, 0xed, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "prefe 14, -37($3)" + + - + input: + bytes: [ 0x7d, 0x71, 0x7f, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sbe $17, 255($11)" + + - + input: + bytes: [ 0x7d, 0x51, 0x80, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sbe $17, -256($10)" + + - + input: + bytes: [ 0x7d, 0xd3, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sbe $19, 0($14)" + + - + input: + bytes: [ 0x7e, 0x49, 0x7f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sce $9, 255($18)" + + - + input: + bytes: [ 0x7e, 0xac, 0x80, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sce $12, -256($21)" + + - + input: + bytes: [ 0x7e, 0xed, 0xf0, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "sce $13, -31($23)" + + - + input: + bytes: [ 0x7d, 0xee, 0x7f, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "she $14, 255($15)" + + - + input: + bytes: [ 0x7d, 0xee, 0x80, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "she $14, -256($15)" + + - + input: + bytes: [ 0x7d, 0x69, 0x75, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "she $9, 235($11)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x7f, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "swe $ra, 255($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x80, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "swe $ra, -256($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0xe5, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "swe $ra, -53($sp)" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tlbinv" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R6" ] + expected: + insns: + - + asm_text: "tlbinvf" + + - + input: + bytes: [ 0x7c, 0xff, 0x7f, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cachee 31, 255($7)" + + - + input: + bytes: [ 0x7c, 0x80, 0x80, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cachee 0, -256($4)" + + - + input: + bytes: [ 0x7c, 0x85, 0xba, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "cachee 5, -140($4)" + + - + input: + bytes: [ 0x7f, 0x2a, 0x80, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lbe $10, -256($25)" + + - + input: + bytes: [ 0x7d, 0xed, 0x7f, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lbe $13, 255($15)" + + - + input: + bytes: [ 0x7d, 0xcb, 0x49, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lbe $11, 146($14)" + + - + input: + bytes: [ 0x7c, 0x6d, 0x80, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lbue $13, -256($3)" + + - + input: + bytes: [ 0x7c, 0x4d, 0x7f, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lbue $13, 255($2)" + + - + input: + bytes: [ 0x7c, 0x6d, 0xa1, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lbue $13, -190($3)" + + - + input: + bytes: [ 0x7e, 0xad, 0x80, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lhe $13, -256($21)" + + - + input: + bytes: [ 0x7e, 0x0c, 0x7f, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lhe $12, 255($16)" + + - + input: + bytes: [ 0x7e, 0x0d, 0x28, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lhe $13, 81($16)" + + - + input: + bytes: [ 0x7c, 0x72, 0x80, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lhue $18, -256($3)" + + - + input: + bytes: [ 0x7c, 0x72, 0x7f, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lhue $18, 255($3)" + + - + input: + bytes: [ 0x7c, 0x56, 0xac, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lhue $22, -168($2)" + + - + input: + bytes: [ 0x7e, 0xa2, 0x80, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lle $2, -256($21)" + + - + input: + bytes: [ 0x7e, 0x63, 0x7f, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lle $3, 255($19)" + + - + input: + bytes: [ 0x7e, 0xc3, 0xdc, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "lle $3, -71($22)" + + - + input: + bytes: [ 0x7c, 0x4e, 0x80, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "prefe 14, -256($2)" + + - + input: + bytes: [ 0x7c, 0x6b, 0x7f, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "prefe 11, 255($3)" + + - + input: + bytes: [ 0x7c, 0x6e, 0xed, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "prefe 14, -37($3)" + + - + input: + bytes: [ 0x7d, 0x71, 0x7f, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sbe $17, 255($11)" + + - + input: + bytes: [ 0x7d, 0x51, 0x80, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sbe $17, -256($10)" + + - + input: + bytes: [ 0x7d, 0xd3, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sbe $19, 0($14)" + + - + input: + bytes: [ 0x7e, 0x49, 0x7f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sce $9, 255($18)" + + - + input: + bytes: [ 0x7e, 0xac, 0x80, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sce $12, -256($21)" + + - + input: + bytes: [ 0x7e, 0xed, 0xf0, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "sce $13, -31($23)" + + - + input: + bytes: [ 0x7d, 0xee, 0x7f, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "she $14, 255($15)" + + - + input: + bytes: [ 0x7d, 0xee, 0x80, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "she $14, -256($15)" + + - + input: + bytes: [ 0x7d, 0x69, 0x75, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "she $9, 235($11)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x7f, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "swe $ra, 255($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x80, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "swe $ra, -256($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0xe5, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "swe $ra, -53($sp)" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tlbinv" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R6" ] + expected: + insns: + - + asm_text: "tlbinvf" diff --git a/tests/MC/Mips/valid_preR6-eva.txt.yaml b/tests/MC/Mips/valid_preR6-eva.txt.yaml new file mode 100644 index 0000000000..3794e9d000 --- /dev/null +++ b/tests/MC/Mips/valid_preR6-eva.txt.yaml @@ -0,0 +1,2820 @@ +test_cases: + - + input: + bytes: [ 0x7c, 0xff, 0x7f, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cachee 31, 255($7)" + + - + input: + bytes: [ 0x7c, 0x80, 0x80, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cachee 0, -256($4)" + + - + input: + bytes: [ 0x7c, 0x85, 0xba, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "cachee 5, -140($4)" + + - + input: + bytes: [ 0x7f, 0x2a, 0x80, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbe $10, -256($25)" + + - + input: + bytes: [ 0x7d, 0xed, 0x7f, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbe $13, 255($15)" + + - + input: + bytes: [ 0x7d, 0xcb, 0x49, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbe $11, 146($14)" + + - + input: + bytes: [ 0x7c, 0x6d, 0x80, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbue $13, -256($3)" + + - + input: + bytes: [ 0x7c, 0x4d, 0x7f, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbue $13, 255($2)" + + - + input: + bytes: [ 0x7c, 0x6d, 0xa1, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lbue $13, -190($3)" + + - + input: + bytes: [ 0x7e, 0xad, 0x80, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lhe $13, -256($21)" + + - + input: + bytes: [ 0x7e, 0x0c, 0x7f, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lhe $12, 255($16)" + + - + input: + bytes: [ 0x7e, 0x0d, 0x28, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lhe $13, 81($16)" + + - + input: + bytes: [ 0x7c, 0x72, 0x80, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lhue $18, -256($3)" + + - + input: + bytes: [ 0x7c, 0x72, 0x7f, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lhue $18, 255($3)" + + - + input: + bytes: [ 0x7c, 0x56, 0xac, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lhue $22, -168($2)" + + - + input: + bytes: [ 0x7e, 0xa2, 0x80, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lle $2, -256($21)" + + - + input: + bytes: [ 0x7e, 0x63, 0x7f, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lle $3, 255($19)" + + - + input: + bytes: [ 0x7e, 0xc3, 0xdc, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lle $3, -71($22)" + + - + input: + bytes: [ 0x7d, 0xf6, 0x7f, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwle $22, 255($15)" + + - + input: + bytes: [ 0x7d, 0x57, 0x80, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwle $23, -256($10)" + + - + input: + bytes: [ 0x7d, 0xb7, 0xa8, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwle $23, -176($13)" + + - + input: + bytes: [ 0x7f, 0x80, 0x7f, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwre $zero, 255($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0x80, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwre $zero, -256($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0xa8, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "lwre $zero, -176($gp)" + + - + input: + bytes: [ 0x7c, 0x4e, 0x80, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "prefe 14, -256($2)" + + - + input: + bytes: [ 0x7c, 0x6b, 0x7f, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "prefe 11, 255($3)" + + - + input: + bytes: [ 0x7c, 0x6e, 0xed, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "prefe 14, -37($3)" + + - + input: + bytes: [ 0x7d, 0x71, 0x7f, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sbe $17, 255($11)" + + - + input: + bytes: [ 0x7d, 0x51, 0x80, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sbe $17, -256($10)" + + - + input: + bytes: [ 0x7d, 0xd3, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sbe $19, 0($14)" + + - + input: + bytes: [ 0x7e, 0x49, 0x7f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sce $9, 255($18)" + + - + input: + bytes: [ 0x7e, 0xac, 0x80, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sce $12, -256($21)" + + - + input: + bytes: [ 0x7e, 0xed, 0xf0, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "sce $13, -31($23)" + + - + input: + bytes: [ 0x7d, 0xee, 0x7f, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "she $14, 255($15)" + + - + input: + bytes: [ 0x7d, 0xee, 0x80, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "she $14, -256($15)" + + - + input: + bytes: [ 0x7d, 0x69, 0x75, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "she $9, 235($11)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x7f, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swe $ra, 255($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x80, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swe $ra, -256($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0xe5, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swe $ra, -53($sp)" + + - + input: + bytes: [ 0x7e, 0x29, 0x7f, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swle $9, 255($17)" + + - + input: + bytes: [ 0x7e, 0x6a, 0x80, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swle $10, -256($19)" + + - + input: + bytes: [ 0x7e, 0xa8, 0x41, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swle $8, 131($21)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x7f, 0xa2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swre $20, 255($13)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x80, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swre $20, -256($13)" + + - + input: + bytes: [ 0x7d, 0xd2, 0x2b, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "swre $18, 86($14)" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbinv" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ] + expected: + insns: + - + asm_text: "tlbinvf" + + - + input: + bytes: [ 0x7c, 0xff, 0x7f, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cachee 31, 255($7)" + + - + input: + bytes: [ 0x7c, 0x80, 0x80, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cachee 0, -256($4)" + + - + input: + bytes: [ 0x7c, 0x85, 0xba, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "cachee 5, -140($4)" + + - + input: + bytes: [ 0x7f, 0x2a, 0x80, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbe $10, -256($25)" + + - + input: + bytes: [ 0x7d, 0xed, 0x7f, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbe $13, 255($15)" + + - + input: + bytes: [ 0x7d, 0xcb, 0x49, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbe $11, 146($14)" + + - + input: + bytes: [ 0x7c, 0x6d, 0x80, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbue $13, -256($3)" + + - + input: + bytes: [ 0x7c, 0x4d, 0x7f, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbue $13, 255($2)" + + - + input: + bytes: [ 0x7c, 0x6d, 0xa1, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lbue $13, -190($3)" + + - + input: + bytes: [ 0x7e, 0xad, 0x80, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lhe $13, -256($21)" + + - + input: + bytes: [ 0x7e, 0x0c, 0x7f, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lhe $12, 255($16)" + + - + input: + bytes: [ 0x7e, 0x0d, 0x28, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lhe $13, 81($16)" + + - + input: + bytes: [ 0x7c, 0x72, 0x80, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lhue $18, -256($3)" + + - + input: + bytes: [ 0x7c, 0x72, 0x7f, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lhue $18, 255($3)" + + - + input: + bytes: [ 0x7c, 0x56, 0xac, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lhue $22, -168($2)" + + - + input: + bytes: [ 0x7e, 0xa2, 0x80, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lle $2, -256($21)" + + - + input: + bytes: [ 0x7e, 0x63, 0x7f, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lle $3, 255($19)" + + - + input: + bytes: [ 0x7e, 0xc3, 0xdc, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lle $3, -71($22)" + + - + input: + bytes: [ 0x7d, 0xf6, 0x7f, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwle $22, 255($15)" + + - + input: + bytes: [ 0x7d, 0x57, 0x80, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwle $23, -256($10)" + + - + input: + bytes: [ 0x7d, 0xb7, 0xa8, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwle $23, -176($13)" + + - + input: + bytes: [ 0x7f, 0x80, 0x7f, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwre $zero, 255($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0x80, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwre $zero, -256($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0xa8, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "lwre $zero, -176($gp)" + + - + input: + bytes: [ 0x7c, 0x4e, 0x80, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "prefe 14, -256($2)" + + - + input: + bytes: [ 0x7c, 0x6b, 0x7f, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "prefe 11, 255($3)" + + - + input: + bytes: [ 0x7c, 0x6e, 0xed, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "prefe 14, -37($3)" + + - + input: + bytes: [ 0x7d, 0x71, 0x7f, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sbe $17, 255($11)" + + - + input: + bytes: [ 0x7d, 0x51, 0x80, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sbe $17, -256($10)" + + - + input: + bytes: [ 0x7d, 0xd3, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sbe $19, 0($14)" + + - + input: + bytes: [ 0x7e, 0x49, 0x7f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sce $9, 255($18)" + + - + input: + bytes: [ 0x7e, 0xac, 0x80, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sce $12, -256($21)" + + - + input: + bytes: [ 0x7e, 0xed, 0xf0, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "sce $13, -31($23)" + + - + input: + bytes: [ 0x7d, 0xee, 0x7f, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "she $14, 255($15)" + + - + input: + bytes: [ 0x7d, 0xee, 0x80, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "she $14, -256($15)" + + - + input: + bytes: [ 0x7d, 0x69, 0x75, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "she $9, 235($11)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x7f, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swe $ra, 255($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x80, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swe $ra, -256($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0xe5, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swe $ra, -53($sp)" + + - + input: + bytes: [ 0x7e, 0x29, 0x7f, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swle $9, 255($17)" + + - + input: + bytes: [ 0x7e, 0x6a, 0x80, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swle $10, -256($19)" + + - + input: + bytes: [ 0x7e, 0xa8, 0x41, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swle $8, 131($21)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x7f, 0xa2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swre $20, 255($13)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x80, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swre $20, -256($13)" + + - + input: + bytes: [ 0x7d, 0xd2, 0x2b, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "swre $18, 86($14)" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbinv" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R3" ] + expected: + insns: + - + asm_text: "tlbinvf" + + - + input: + bytes: [ 0x7c, 0xff, 0x7f, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cachee 31, 255($7)" + + - + input: + bytes: [ 0x7c, 0x80, 0x80, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cachee 0, -256($4)" + + - + input: + bytes: [ 0x7c, 0x85, 0xba, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "cachee 5, -140($4)" + + - + input: + bytes: [ 0x7f, 0x2a, 0x80, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbe $10, -256($25)" + + - + input: + bytes: [ 0x7d, 0xed, 0x7f, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbe $13, 255($15)" + + - + input: + bytes: [ 0x7d, 0xcb, 0x49, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbe $11, 146($14)" + + - + input: + bytes: [ 0x7c, 0x6d, 0x80, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbue $13, -256($3)" + + - + input: + bytes: [ 0x7c, 0x4d, 0x7f, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbue $13, 255($2)" + + - + input: + bytes: [ 0x7c, 0x6d, 0xa1, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lbue $13, -190($3)" + + - + input: + bytes: [ 0x7e, 0xad, 0x80, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lhe $13, -256($21)" + + - + input: + bytes: [ 0x7e, 0x0c, 0x7f, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lhe $12, 255($16)" + + - + input: + bytes: [ 0x7e, 0x0d, 0x28, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lhe $13, 81($16)" + + - + input: + bytes: [ 0x7c, 0x72, 0x80, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lhue $18, -256($3)" + + - + input: + bytes: [ 0x7c, 0x72, 0x7f, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lhue $18, 255($3)" + + - + input: + bytes: [ 0x7c, 0x56, 0xac, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lhue $22, -168($2)" + + - + input: + bytes: [ 0x7e, 0xa2, 0x80, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lle $2, -256($21)" + + - + input: + bytes: [ 0x7e, 0x63, 0x7f, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lle $3, 255($19)" + + - + input: + bytes: [ 0x7e, 0xc3, 0xdc, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lle $3, -71($22)" + + - + input: + bytes: [ 0x7d, 0xf6, 0x7f, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwle $22, 255($15)" + + - + input: + bytes: [ 0x7d, 0x57, 0x80, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwle $23, -256($10)" + + - + input: + bytes: [ 0x7d, 0xb7, 0xa8, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwle $23, -176($13)" + + - + input: + bytes: [ 0x7f, 0x80, 0x7f, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwre $zero, 255($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0x80, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwre $zero, -256($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0xa8, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "lwre $zero, -176($gp)" + + - + input: + bytes: [ 0x7c, 0x4e, 0x80, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "prefe 14, -256($2)" + + - + input: + bytes: [ 0x7c, 0x6b, 0x7f, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "prefe 11, 255($3)" + + - + input: + bytes: [ 0x7c, 0x6e, 0xed, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "prefe 14, -37($3)" + + - + input: + bytes: [ 0x7d, 0x71, 0x7f, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sbe $17, 255($11)" + + - + input: + bytes: [ 0x7d, 0x51, 0x80, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sbe $17, -256($10)" + + - + input: + bytes: [ 0x7d, 0xd3, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sbe $19, 0($14)" + + - + input: + bytes: [ 0x7e, 0x49, 0x7f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sce $9, 255($18)" + + - + input: + bytes: [ 0x7e, 0xac, 0x80, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sce $12, -256($21)" + + - + input: + bytes: [ 0x7e, 0xed, 0xf0, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "sce $13, -31($23)" + + - + input: + bytes: [ 0x7d, 0xee, 0x7f, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "she $14, 255($15)" + + - + input: + bytes: [ 0x7d, 0xee, 0x80, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "she $14, -256($15)" + + - + input: + bytes: [ 0x7d, 0x69, 0x75, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "she $9, 235($11)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x7f, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swe $ra, 255($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x80, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swe $ra, -256($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0xe5, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swe $ra, -53($sp)" + + - + input: + bytes: [ 0x7e, 0x29, 0x7f, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swle $9, 255($17)" + + - + input: + bytes: [ 0x7e, 0x6a, 0x80, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swle $10, -256($19)" + + - + input: + bytes: [ 0x7e, 0xa8, 0x41, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swle $8, 131($21)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x7f, 0xa2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swre $20, 255($13)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x80, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swre $20, -256($13)" + + - + input: + bytes: [ 0x7d, 0xd2, 0x2b, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "swre $18, 86($14)" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbinv" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R5" ] + expected: + insns: + - + asm_text: "tlbinvf" + + - + input: + bytes: [ 0x7c, 0xff, 0x7f, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cachee 31, 255($7)" + + - + input: + bytes: [ 0x7c, 0x80, 0x80, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cachee 0, -256($4)" + + - + input: + bytes: [ 0x7c, 0x85, 0xba, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "cachee 5, -140($4)" + + - + input: + bytes: [ 0x7f, 0x2a, 0x80, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbe $10, -256($25)" + + - + input: + bytes: [ 0x7d, 0xed, 0x7f, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbe $13, 255($15)" + + - + input: + bytes: [ 0x7d, 0xcb, 0x49, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbe $11, 146($14)" + + - + input: + bytes: [ 0x7c, 0x6d, 0x80, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbue $13, -256($3)" + + - + input: + bytes: [ 0x7c, 0x4d, 0x7f, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbue $13, 255($2)" + + - + input: + bytes: [ 0x7c, 0x6d, 0xa1, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lbue $13, -190($3)" + + - + input: + bytes: [ 0x7e, 0xad, 0x80, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lhe $13, -256($21)" + + - + input: + bytes: [ 0x7e, 0x0c, 0x7f, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lhe $12, 255($16)" + + - + input: + bytes: [ 0x7e, 0x0d, 0x28, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lhe $13, 81($16)" + + - + input: + bytes: [ 0x7c, 0x72, 0x80, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lhue $18, -256($3)" + + - + input: + bytes: [ 0x7c, 0x72, 0x7f, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lhue $18, 255($3)" + + - + input: + bytes: [ 0x7c, 0x56, 0xac, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lhue $22, -168($2)" + + - + input: + bytes: [ 0x7e, 0xa2, 0x80, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lle $2, -256($21)" + + - + input: + bytes: [ 0x7e, 0x63, 0x7f, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lle $3, 255($19)" + + - + input: + bytes: [ 0x7e, 0xc3, 0xdc, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lle $3, -71($22)" + + - + input: + bytes: [ 0x7d, 0xf6, 0x7f, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwle $22, 255($15)" + + - + input: + bytes: [ 0x7d, 0x57, 0x80, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwle $23, -256($10)" + + - + input: + bytes: [ 0x7d, 0xb7, 0xa8, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwle $23, -176($13)" + + - + input: + bytes: [ 0x7f, 0x80, 0x7f, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwre $zero, 255($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0x80, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwre $zero, -256($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0xa8, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "lwre $zero, -176($gp)" + + - + input: + bytes: [ 0x7c, 0x4e, 0x80, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "prefe 14, -256($2)" + + - + input: + bytes: [ 0x7c, 0x6b, 0x7f, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "prefe 11, 255($3)" + + - + input: + bytes: [ 0x7c, 0x6e, 0xed, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "prefe 14, -37($3)" + + - + input: + bytes: [ 0x7d, 0x71, 0x7f, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sbe $17, 255($11)" + + - + input: + bytes: [ 0x7d, 0x51, 0x80, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sbe $17, -256($10)" + + - + input: + bytes: [ 0x7d, 0xd3, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sbe $19, 0($14)" + + - + input: + bytes: [ 0x7e, 0x49, 0x7f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sce $9, 255($18)" + + - + input: + bytes: [ 0x7e, 0xac, 0x80, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sce $12, -256($21)" + + - + input: + bytes: [ 0x7e, 0xed, 0xf0, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "sce $13, -31($23)" + + - + input: + bytes: [ 0x7d, 0xee, 0x7f, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "she $14, 255($15)" + + - + input: + bytes: [ 0x7d, 0xee, 0x80, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "she $14, -256($15)" + + - + input: + bytes: [ 0x7d, 0x69, 0x75, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "she $9, 235($11)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x7f, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swe $ra, 255($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x80, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swe $ra, -256($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0xe5, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swe $ra, -53($sp)" + + - + input: + bytes: [ 0x7e, 0x29, 0x7f, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swle $9, 255($17)" + + - + input: + bytes: [ 0x7e, 0x6a, 0x80, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swle $10, -256($19)" + + - + input: + bytes: [ 0x7e, 0xa8, 0x41, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swle $8, 131($21)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x7f, 0xa2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swre $20, 255($13)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x80, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swre $20, -256($13)" + + - + input: + bytes: [ 0x7d, 0xd2, 0x2b, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "swre $18, 86($14)" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbinv" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R2" ] + expected: + insns: + - + asm_text: "tlbinvf" + + - + input: + bytes: [ 0x7c, 0xff, 0x7f, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cachee 31, 255($7)" + + - + input: + bytes: [ 0x7c, 0x80, 0x80, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cachee 0, -256($4)" + + - + input: + bytes: [ 0x7c, 0x85, 0xba, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "cachee 5, -140($4)" + + - + input: + bytes: [ 0x7f, 0x2a, 0x80, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lbe $10, -256($25)" + + - + input: + bytes: [ 0x7d, 0xed, 0x7f, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lbe $13, 255($15)" + + - + input: + bytes: [ 0x7d, 0xcb, 0x49, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lbe $11, 146($14)" + + - + input: + bytes: [ 0x7c, 0x6d, 0x80, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lbue $13, -256($3)" + + - + input: + bytes: [ 0x7c, 0x4d, 0x7f, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lbue $13, 255($2)" + + - + input: + bytes: [ 0x7c, 0x6d, 0xa1, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lbue $13, -190($3)" + + - + input: + bytes: [ 0x7e, 0xad, 0x80, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lhe $13, -256($21)" + + - + input: + bytes: [ 0x7e, 0x0c, 0x7f, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lhe $12, 255($16)" + + - + input: + bytes: [ 0x7e, 0x0d, 0x28, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lhe $13, 81($16)" + + - + input: + bytes: [ 0x7c, 0x72, 0x80, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lhue $18, -256($3)" + + - + input: + bytes: [ 0x7c, 0x72, 0x7f, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lhue $18, 255($3)" + + - + input: + bytes: [ 0x7c, 0x56, 0xac, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lhue $22, -168($2)" + + - + input: + bytes: [ 0x7e, 0xa2, 0x80, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lle $2, -256($21)" + + - + input: + bytes: [ 0x7e, 0x63, 0x7f, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lle $3, 255($19)" + + - + input: + bytes: [ 0x7e, 0xc3, 0xdc, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lle $3, -71($22)" + + - + input: + bytes: [ 0x7d, 0xf6, 0x7f, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwle $22, 255($15)" + + - + input: + bytes: [ 0x7d, 0x57, 0x80, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwle $23, -256($10)" + + - + input: + bytes: [ 0x7d, 0xb7, 0xa8, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwle $23, -176($13)" + + - + input: + bytes: [ 0x7f, 0x80, 0x7f, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwre $zero, 255($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0x80, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwre $zero, -256($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0xa8, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "lwre $zero, -176($gp)" + + - + input: + bytes: [ 0x7c, 0x4e, 0x80, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "prefe 14, -256($2)" + + - + input: + bytes: [ 0x7c, 0x6b, 0x7f, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "prefe 11, 255($3)" + + - + input: + bytes: [ 0x7c, 0x6e, 0xed, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "prefe 14, -37($3)" + + - + input: + bytes: [ 0x7d, 0x71, 0x7f, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sbe $17, 255($11)" + + - + input: + bytes: [ 0x7d, 0x51, 0x80, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sbe $17, -256($10)" + + - + input: + bytes: [ 0x7d, 0xd3, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sbe $19, 0($14)" + + - + input: + bytes: [ 0x7e, 0x49, 0x7f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sce $9, 255($18)" + + - + input: + bytes: [ 0x7e, 0xac, 0x80, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sce $12, -256($21)" + + - + input: + bytes: [ 0x7e, 0xed, 0xf0, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "sce $13, -31($23)" + + - + input: + bytes: [ 0x7d, 0xee, 0x7f, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "she $14, 255($15)" + + - + input: + bytes: [ 0x7d, 0xee, 0x80, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "she $14, -256($15)" + + - + input: + bytes: [ 0x7d, 0x69, 0x75, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "she $9, 235($11)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x7f, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swe $ra, 255($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x80, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swe $ra, -256($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0xe5, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swe $ra, -53($sp)" + + - + input: + bytes: [ 0x7e, 0x29, 0x7f, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swle $9, 255($17)" + + - + input: + bytes: [ 0x7e, 0x6a, 0x80, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swle $10, -256($19)" + + - + input: + bytes: [ 0x7e, 0xa8, 0x41, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swle $8, 131($21)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x7f, 0xa2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swre $20, 255($13)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x80, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swre $20, -256($13)" + + - + input: + bytes: [ 0x7d, 0xd2, 0x2b, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "swre $18, 86($14)" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tlbinv" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R3" ] + expected: + insns: + - + asm_text: "tlbinvf" + + - + input: + bytes: [ 0x7c, 0xff, 0x7f, 0x9b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cachee 31, 255($7)" + + - + input: + bytes: [ 0x7c, 0x80, 0x80, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cachee 0, -256($4)" + + - + input: + bytes: [ 0x7c, 0x85, 0xba, 0x1b ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "cachee 5, -140($4)" + + - + input: + bytes: [ 0x7f, 0x2a, 0x80, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lbe $10, -256($25)" + + - + input: + bytes: [ 0x7d, 0xed, 0x7f, 0xac ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lbe $13, 255($15)" + + - + input: + bytes: [ 0x7d, 0xcb, 0x49, 0x2c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lbe $11, 146($14)" + + - + input: + bytes: [ 0x7c, 0x6d, 0x80, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lbue $13, -256($3)" + + - + input: + bytes: [ 0x7c, 0x4d, 0x7f, 0xa8 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lbue $13, 255($2)" + + - + input: + bytes: [ 0x7c, 0x6d, 0xa1, 0x28 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lbue $13, -190($3)" + + - + input: + bytes: [ 0x7e, 0xad, 0x80, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lhe $13, -256($21)" + + - + input: + bytes: [ 0x7e, 0x0c, 0x7f, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lhe $12, 255($16)" + + - + input: + bytes: [ 0x7e, 0x0d, 0x28, 0xad ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lhe $13, 81($16)" + + - + input: + bytes: [ 0x7c, 0x72, 0x80, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lhue $18, -256($3)" + + - + input: + bytes: [ 0x7c, 0x72, 0x7f, 0xa9 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lhue $18, 255($3)" + + - + input: + bytes: [ 0x7c, 0x56, 0xac, 0x29 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lhue $22, -168($2)" + + - + input: + bytes: [ 0x7e, 0xa2, 0x80, 0x2e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lle $2, -256($21)" + + - + input: + bytes: [ 0x7e, 0x63, 0x7f, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lle $3, 255($19)" + + - + input: + bytes: [ 0x7e, 0xc3, 0xdc, 0xae ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lle $3, -71($22)" + + - + input: + bytes: [ 0x7d, 0xf6, 0x7f, 0x99 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwle $22, 255($15)" + + - + input: + bytes: [ 0x7d, 0x57, 0x80, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwle $23, -256($10)" + + - + input: + bytes: [ 0x7d, 0xb7, 0xa8, 0x19 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwle $23, -176($13)" + + - + input: + bytes: [ 0x7f, 0x80, 0x7f, 0x9a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwre $zero, 255($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0x80, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwre $zero, -256($gp)" + + - + input: + bytes: [ 0x7f, 0x80, 0xa8, 0x1a ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "lwre $zero, -176($gp)" + + - + input: + bytes: [ 0x7c, 0x4e, 0x80, 0x23 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "prefe 14, -256($2)" + + - + input: + bytes: [ 0x7c, 0x6b, 0x7f, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "prefe 11, 255($3)" + + - + input: + bytes: [ 0x7c, 0x6e, 0xed, 0xa3 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "prefe 14, -37($3)" + + - + input: + bytes: [ 0x7d, 0x71, 0x7f, 0x9c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sbe $17, 255($11)" + + - + input: + bytes: [ 0x7d, 0x51, 0x80, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sbe $17, -256($10)" + + - + input: + bytes: [ 0x7d, 0xd3, 0x00, 0x1c ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sbe $19, 0($14)" + + - + input: + bytes: [ 0x7e, 0x49, 0x7f, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sce $9, 255($18)" + + - + input: + bytes: [ 0x7e, 0xac, 0x80, 0x1e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sce $12, -256($21)" + + - + input: + bytes: [ 0x7e, 0xed, 0xf0, 0x9e ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "sce $13, -31($23)" + + - + input: + bytes: [ 0x7d, 0xee, 0x7f, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "she $14, 255($15)" + + - + input: + bytes: [ 0x7d, 0xee, 0x80, 0x1d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "she $14, -256($15)" + + - + input: + bytes: [ 0x7d, 0x69, 0x75, 0x9d ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "she $9, 235($11)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x7f, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swe $ra, 255($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0x80, 0x1f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swe $ra, -256($sp)" + + - + input: + bytes: [ 0x7f, 0xbf, 0xe5, 0x9f ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swe $ra, -53($sp)" + + - + input: + bytes: [ 0x7e, 0x29, 0x7f, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swle $9, 255($17)" + + - + input: + bytes: [ 0x7e, 0x6a, 0x80, 0x21 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swle $10, -256($19)" + + - + input: + bytes: [ 0x7e, 0xa8, 0x41, 0xa1 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swle $8, 131($21)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x7f, 0xa2 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swre $20, 255($13)" + + - + input: + bytes: [ 0x7d, 0xb4, 0x80, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swre $20, -256($13)" + + - + input: + bytes: [ 0x7d, 0xd2, 0x2b, 0x22 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "swre $18, 86($14)" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tlbinv" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_MIPS" + options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ] + expected: + insns: + - + asm_text: "tlbinvf" diff --git a/tests/details/cs_common_details.yaml b/tests/details/cs_common_details.yaml index 4dd602077d..3ed8537eb1 100644 --- a/tests/details/cs_common_details.yaml +++ b/tests/details/cs_common_details.yaml @@ -395,7 +395,7 @@ test_cases: input: bytes: [ 0x0c, 0x10, 0x00, 0x97, 0x00, 0x00, 0x00, 0x00, 0x24, 0x02, 0x00, 0x0c, 0x8f, 0xa2, 0x00, 0x00, 0x34, 0x21, 0x34, 0x56, 0x00, 0x80, 0x04, 0x08 ] arch: "CS_ARCH_MIPS" - options: [ CS_OPT_DETAIL, CS_MODE_MIPS32, CS_MODE_BIG_ENDIAN ] + options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R5, CS_MODE_BIG_ENDIAN ] address: 0x1000 expected: insns: @@ -405,36 +405,36 @@ test_cases: op_str: "0x40025c" details: regs_impl_write: [ ra ] - groups: [ stdenc ] + groups: [ call, HasStdEnc, NotInMicroMips, NotNanoMips ] - asm_text: "nop" mnemonic: "nop" details: - groups: [ stdenc, notinmicromips ] + groups: [ HasStdEnc, NotInMicroMips, NotNanoMips ] - asm_text: "addiu $v0, $zero, 0xc" mnemonic: "addiu" op_str: "$v0, $zero, 0xc" details: - groups: [ stdenc, notinmicromips ] + groups: [ HasStdEnc, NotInMicroMips, NotNanoMips ] - - asm_text: "lw $v0, ($sp)" + asm_text: "lw $v0, 0($sp)" mnemonic: "lw" - op_str: "$v0, ($sp)" + op_str: "$v0, 0($sp)" details: - groups: [ stdenc, notinmicromips ] + groups: [ HasStdEnc, NotInMicroMips, NotNanoMips ] - asm_text: "ori $at, $at, 0x3456" mnemonic: "ori" op_str: "$at, $at, 0x3456" details: - groups: [ stdenc ] + groups: [ HasStdEnc, NotInMicroMips, NotNanoMips ] - asm_text: "jr.hb $a0" mnemonic: "jr.hb" op_str: "$a0" details: - groups: [ stdenc, mips32, notmips32r6, notmips64r6, jump ] + groups: [ jump, HasStdEnc, HasMips32r2, NotMips32r6, NotMips64r6 ] - input: bytes: [ 0x56, 0x34, 0x21, 0x34, 0xc2, 0x17, 0x01, 0x00 ] @@ -448,13 +448,13 @@ test_cases: mnemonic: "ori" op_str: "$at, $at, 0x3456" details: - groups: [ stdenc ] + groups: [ HasStdEnc, NotInMicroMips, NotNanoMips ] - asm_text: "srl $v0, $at, 0x1f" mnemonic: "srl" op_str: "$v0, $at, 0x1f" details: - groups: [ stdenc, notinmicromips ] + groups: [ HasStdEnc, NotInMicroMips, NotNanoMips ] - input: bytes: [ 0x00, 0x07, 0x00, 0x07, 0x00, 0x11, 0x93, 0x7c, 0x01, 0x8c, 0x8b, 0x7c, 0x00, 0xc7, 0x48, 0xd0 ] @@ -468,25 +468,25 @@ test_cases: mnemonic: "break" op_str: "7, 0" details: - groups: [ micromips ] + groups: [ InMicroMips, HasMips32r6 ] - asm_text: "wait 0x11" mnemonic: "wait" op_str: "0x11" details: - groups: [ micromips ] + groups: [ InMicroMips, HasMips32r6 ] - asm_text: "syscall 0x18c" mnemonic: "syscall" op_str: "0x18c" details: - groups: [ micromips, int ] + groups: [ InMicroMips ] - asm_text: "rotrv $t1, $a2, $a3" mnemonic: "rotrv" op_str: "$t1, $a2, $a3" details: - groups: [ micromips ] + groups: [ InMicroMips ] - input: bytes: [ 0xec, 0x80, 0x00, 0x19, 0x7c, 0x43, 0x22, 0xa0 ] @@ -496,17 +496,17 @@ test_cases: expected: insns: - - asm_text: "addiupc $a0, 0x64" - mnemonic: "addiupc" + asm_text: "lapc $a0, 0x64" + mnemonic: "lapc" op_str: "$a0, 0x64" details: - groups: [ stdenc, mips32r6 ] + groups: [ HasStdEnc, HasMips32r6 ] - asm_text: "align $a0, $v0, $v1, 2" mnemonic: "align" op_str: "$a0, $v0, $v1, 2" details: - groups: [ stdenc, mips32r6 ] + groups: [ HasStdEnc, HasMips32r6 ] - input: bytes: [ 0x80, 0x20, 0x00, 0x00, 0x80, 0x3f, 0x00, 0x00, 0x10, 0x43, 0x23, 0x0e, 0xd0, 0x44, 0x00, 0x80, 0x4c, 0x43, 0x22, 0x02, 0x2d, 0x03, 0x00, 0x80, 0x7c, 0x43, 0x20, 0x14, 0x7c, 0x43, 0x20, 0x93, 0x4f, 0x20, 0x00, 0x21, 0x4c, 0xc8, 0x00, 0x21, 0x40, 0x82, 0x00, 0x14 ] diff --git a/tests/details/mips.yaml b/tests/details/mips.yaml index 1695728f89..b7fe354dd9 100644 --- a/tests/details/mips.yaml +++ b/tests/details/mips.yaml @@ -2,8 +2,8 @@ test_cases: - input: bytes: [ 0x0c, 0x10, 0x00, 0x97, 0x00, 0x00, 0x00, 0x00, 0x24, 0x02, 0x00, 0x0c, 0x8f, 0xa2, 0x00, 0x00, 0x34, 0x21, 0x34, 0x56 ] - arch: "mips" - options: [ CS_OPT_DETAIL, CS_MODE_MIPS32, CS_MODE_BIG_ENDIAN ] + arch: "CS_ARCH_MIPS" + options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R5, CS_MODE_BIG_ENDIAN ] address: 0x0 expected: insns: @@ -32,7 +32,7 @@ test_cases: type: MIPS_OP_IMM imm: 0xc - - asm_text: "lw $v0, ($sp)" + asm_text: "lw $v0, 0($sp)" details: mips: operands: @@ -59,7 +59,7 @@ test_cases: - input: bytes: [ 0x56, 0x34, 0x21, 0x34, 0xc2, 0x17, 0x01, 0x00 ] - arch: "mips" + arch: "CS_ARCH_MIPS" options: [ CS_OPT_DETAIL, CS_MODE_MIPS64, CS_MODE_LITTLE_ENDIAN ] address: 0x0 expected: @@ -95,7 +95,7 @@ test_cases: - input: bytes: [ 0x00, 0x07, 0x00, 0x07, 0x00, 0x11, 0x93, 0x7c, 0x01, 0x8c, 0x8b, 0x7c, 0x00, 0xc7, 0x48, 0xd0 ] - arch: "mips" + arch: "CS_ARCH_MIPS" options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R6, CS_MODE_MICRO, CS_MODE_BIG_ENDIAN ] address: 0x0 expected: @@ -144,13 +144,13 @@ test_cases: - input: bytes: [ 0xec, 0x80, 0x00, 0x19, 0x7c, 0x43, 0x22, 0xa0 ] - arch: "mips" + arch: "CS_ARCH_MIPS" options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R6, CS_MODE_BIG_ENDIAN ] address: 0x0 expected: insns: - - asm_text: "addiupc $a0, 0x64" + asm_text: "lapc $a0, 0x64" details: mips: operands: @@ -180,8 +180,8 @@ test_cases: - input: bytes: [ 0x70, 0x00, 0xb2, 0xff ] - arch: "mips" - options: [ CS_MODE_MIPS64, CS_MODE_MIPS2, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_MIPS2, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ] address: 0x0 expected: insns: @@ -192,7 +192,7 @@ test_cases: operands: - type: MIPS_OP_REG - reg: s2 + reg: "18" - type: MIPS_OP_MEM mem_base: sp @@ -200,7 +200,7 @@ test_cases: - input: bytes: [ 0x70, 0x00, 0xb2, 0xff ] - arch: "mips" + arch: "CS_ARCH_MIPS" options: [ CS_OPT_DETAIL, CS_MODE_MIPS64, CS_MODE_LITTLE_ENDIAN] address: 0x0 expected: @@ -218,3 +218,52 @@ test_cases: mem_base: sp mem_disp: 0x70 + - + skip: true + skip_reason: "Capstone python bindings do not handle CS_OPT_DETAIL_REAL." + input: + bytes: [ 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ CS_OPT_DETAIL, CS_OPT_DETAIL_REAL, CS_MODE_MIPS32R6, CS_MODE_BIG_ENDIAN ] + address: 0x0 + expected: + insns: + - + asm_text: "nop" + details: + mips: + operands: + - + type: MIPS_OP_REG + reg: zero + - + type: MIPS_OP_REG + reg: zero + - + type: MIPS_OP_IMM + imm: 0 + + - + skip: true + skip_reason: "Capstone python bindings do not handle CS_OPT_DETAIL_REAL." + input: + bytes: [ 0x38,0xf0,0x20,0x46 ] + arch: "CS_ARCH_MIPS" + options: [ CS_OPT_DETAIL, CS_OPT_DETAIL_REAL, CS_MODE_LITTLE_ENDIAN, CS_MODE_MIPS1 ] + address: 0x0 + expected: + insns: + - + asm_text: "c.sf.d $f30, $f0" + details: + mips: + operands: + - + type: MIPS_OP_REG + reg: fcc0 + - + type: MIPS_OP_REG + reg: f30 + - + type: MIPS_OP_REG + reg: f0 \ No newline at end of file diff --git a/tests/issues/issues.yaml b/tests/issues/issues.yaml index fe7a8c5b12..cc0a17cc6d 100644 --- a/tests/issues/issues.yaml +++ b/tests/issues/issues.yaml @@ -4815,3 +4815,145 @@ test_cases: details: sparc: cc: SPARC_CC_ICC_NE + + - + input: + name: "issue 2448" + bytes: [ 0x04, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_LITTLE_ENDIAN, CS_MODE_MIPS32 ] + address: 0x0 + expected: + insns: + - asm_text: "jal 0x10" + + - + input: + name: "issue 1054" + bytes: [ 0x01, 0x20, 0x10, 0x2d, 0x00, 0x80, 0xe8, 0x2d, 0x40, 0xab, 0x50, 0x00, 0x00, 0xa0, 0x40, 0x2d, 0x00, 0x80, 0x50, 0x2d, 0x01, 0xa0, 0x70, 0x2d, 0x40, 0xac, 0x10, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_BIG_ENDIAN, CS_MODE_MIPS3 ] + address: 0x0 + expected: + insns: + - asm_text: "move $v0, $t1" + - asm_text: "move $sp, $a0" + - asm_text: "dmtc0 $t3, $10, 0" + - asm_text: "move $t0, $a1" + - asm_text: "move $t2, $a0" + - asm_text: "move $t6, $t5" + - asm_text: "dmtc0 $t4, $2, 0" + + - + input: + name: "issue 1133" + bytes: [ 0xb5, 0x06, 0xff, 0x7d ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_LITTLE_ENDIAN, CS_MODE_MIPS32R6 ] + address: 0x0 + expected: + insns: + - asm_text: "pref 0x1f, 0xd($t7)" + + - + input: + name: "issue 1267" + bytes: [ 0x00, 0xc0, 0x50, 0x2d ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_BIG_ENDIAN, CS_MODE_MIPS3 ] + address: 0x0 + expected: + insns: + - asm_text: "move $t2, $a2" + + - + input: + name: "issue 1508" + bytes: [ 0x40, 0x02, 0x10, 0x00 ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_BIG_ENDIAN, CS_MODE_MIPS32R6 ] + address: 0x0 + expected: + insns: + - asm_text: "mfc0 $v0, $2, 0" + + - + input: + name: "issue 1634" + bytes: [ 0x46, 0x20, 0x09, 0x37 ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_BIG_ENDIAN, CS_MODE_MIPS3 ] + address: 0x0 + expected: + insns: + - asm_text: "c.ule.d $fcc1, $f1, $f0" + + - + input: + name: "issue 1673" + bytes: [ 0x03, 0x80, 0x0c, 0x40, 0x80, 0x00, 0x8c, 0x35 ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_LITTLE_ENDIAN, CS_MODE_MIPS64 ] + address: 0x0 + expected: + insns: + - asm_text: "mfc0 $t4, $16, 3" + - asm_text: "ori $t4, $t4, 0x80" + + - + input: + name: "issue 1680" + bytes: [ 0x40, 0x00, 0x00, 0x0c, 0x08, 0x00, 0xe0, 0x03 ] + arch: "CS_ARCH_MIPS" + options: [ CS_OPT_DETAIL, CS_MODE_LITTLE_ENDIAN, CS_MODE_MIPS32 ] + address: 0x0 + expected: + insns: + - asm_text: "jal 0x100" + details: + mips: + operands: + - type: MIPS_OP_IMM + imm: 0x100 + + - asm_text: "jr $ra" + details: + mips: + operands: + - type: MIPS_OP_REG + reg: ra + + - + input: + name: "issue 1780" + bytes: [ 0x7c, 0x03, 0xe8, 0x3b ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_BIG_ENDIAN, CS_MODE_MIPS32 ] + address: 0x0 + expected: + insns: + - asm_text: "rdhwr $v1, $29" + + - + input: + name: "issue 1851" + bytes: [ 0x32, 0xC0, 0x38, 0x46, 0x32, 0x02, 0x20, 0x46, 0x32, 0x03, 0x20, 0x46 ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_LITTLE_ENDIAN, CS_MODE_MIPS64 ] + address: 0x0 + expected: + insns: + - asm_text: "c.eq.d $f24, $f24" + - asm_text: "c.eq.d $fcc2, $f0, $f0" + - asm_text: "c.eq.d $fcc3, $f0, $f0" + + - + input: + name: "issue 1851" + bytes: [ 0x00, 0x00, 0x19, 0xf8 ] + arch: "CS_ARCH_MIPS" + options: [ CS_MODE_LITTLE_ENDIAN, CS_MODE_MIPS32R6 ] + address: 0x0 + expected: + insns: + - asm_text: "jalrc $t9" From af1ed2fb3d9d67926389a71e12531bef76f50482 Mon Sep 17 00:00:00 2001 From: Rot127 <45763064+Rot127@users.noreply.github.com> Date: Sat, 14 Sep 2024 08:57:54 +0000 Subject: [PATCH 4/5] SystemZ Auto-Sync refactor (#2462) --- .github/workflows/CITest.yml | 19 +- .github/workflows/auto-sync.yml | 9 +- CMakeLists.txt | 42 +- COMPILE_CMAKE.TXT | 2 +- MCAsmInfo.h | 19 + MCInst.c | 16 +- MCInst.h | 6 +- Mapping.c | 3 +- Mapping.h | 5 + SStream.c | 165 +- SStream.h | 30 +- arch/ARM/ARMInstPrinter.c | 2 +- arch/SystemZ/SystemZDisassembler.c | 604 +- arch/SystemZ/SystemZDisassembler.h | 17 - arch/SystemZ/SystemZDisassemblerExtension.c | 116 + arch/SystemZ/SystemZDisassemblerExtension.h | 11 + arch/SystemZ/SystemZGenAsmWriter.inc | 13745 ++-- arch/SystemZ/SystemZGenCSAliasMnemMap.inc | 55 + arch/SystemZ/SystemZGenCSFeatureName.inc | 55 + arch/SystemZ/SystemZGenCSMappingInsn.inc | 24272 ++++++ arch/SystemZ/SystemZGenCSMappingInsnName.inc | 2513 + arch/SystemZ/SystemZGenCSMappingInsnOp.inc | 20132 +++++ arch/SystemZ/SystemZGenCSOpGroup.inc | 34 + arch/SystemZ/SystemZGenDisassemblerTables.inc | 18106 ++--- arch/SystemZ/SystemZGenInsnNameMaps.inc | 2348 - arch/SystemZ/SystemZGenInstrInfo.inc | 9970 ++- arch/SystemZ/SystemZGenRegisterInfo.inc | 1258 +- arch/SystemZ/SystemZGenSubtargetInfo.inc | 94 +- arch/SystemZ/SystemZInstPrinter.c | 585 +- arch/SystemZ/SystemZInstPrinter.h | 56 +- arch/SystemZ/SystemZLinkage.h | 22 + arch/SystemZ/SystemZMCTargetDesc.c | 256 +- arch/SystemZ/SystemZMCTargetDesc.h | 90 +- arch/SystemZ/SystemZMapping.c | 722 +- arch/SystemZ/SystemZMapping.h | 41 +- arch/SystemZ/SystemZMappingInsn.inc | 14175 ---- arch/SystemZ/SystemZModule.c | 18 +- bindings/const_generator.py | 16 +- bindings/python/capstone/__init__.py | 51 +- bindings/python/capstone/aarch64_const.py | 4 +- bindings/python/capstone/alpha_const.py | 2 +- bindings/python/capstone/arm_const.py | 2 +- bindings/python/capstone/bpf_const.py | 2 +- bindings/python/capstone/evm_const.py | 2 +- bindings/python/capstone/hppa_const.py | 2 +- bindings/python/capstone/loongarch_const.py | 2 +- bindings/python/capstone/m680x_const.py | 2 +- bindings/python/capstone/m68k_const.py | 2 +- bindings/python/capstone/mips_const.py | 2 +- bindings/python/capstone/mos65xx_const.py | 2 +- bindings/python/capstone/ppc_const.py | 2 +- bindings/python/capstone/riscv_const.py | 2 +- bindings/python/capstone/sh_const.py | 2 +- bindings/python/capstone/sparc_const.py | 2 +- bindings/python/capstone/systemz.py | 21 +- bindings/python/capstone/systemz_const.py | 2903 + bindings/python/capstone/sysz_const.py | 2524 - bindings/python/capstone/tms320c64x_const.py | 2 +- bindings/python/capstone/tricore_const.py | 2 +- bindings/python/capstone/wasm_const.py | 2 +- bindings/python/capstone/x86_const.py | 2 +- bindings/python/capstone/xcore_const.py | 2 +- .../python/cstest_py/src/cstest_py/compare.py | 4 +- .../python/cstest_py/src/cstest_py/details.py | 22 +- bindings/python/tests/test_iter.py | 2 +- bindings/python/tests/test_lite.py | 2 +- cmake.sh | 2 +- ...apstone-generate-GenRegisterInfo.inc.patch | 338 - ...pstone-generate-GenSubtargetInfo.inc.patch | 86 - ...3-capstone-generate-GenInstrInfo.inc.patch | 130 - ...e-generate-GenDisassemblerTables.inc.patch | 472 - ...5-capstone-generate-GenAsmWriter.inc.patch | 225 - ...06-capstone-generate-MappingInsn.inc.patch | 174 - ...apstone-generate-GenInsnNameMaps.inc.patch | 110 - contrib/sysz_update/README.md | 58 - cs.c | 60 +- cstool/cstool.c | 24 +- cstool/cstool.h | 2 +- cstool/cstool_systemz.c | 78 +- docs/cs_v6_release_guide.md | 134 +- include/capstone/capstone.h | 33 +- include/capstone/systemz.h | 5525 +- include/capstone/systemz_compatibility.h | 2966 + suite/auto-sync/.gitignore | 2 +- suite/auto-sync/c_tests/CMakeLists.txt | 16 - suite/auto-sync/pyproject.toml | 3 + suite/auto-sync/src/autosync/ASUpdater.py | 92 +- suite/auto-sync/src/autosync/HeaderPatcher.py | 130 +- suite/auto-sync/src/autosync/Helper.py | 6 - suite/auto-sync/src/autosync/IncGenerator.py | 57 +- suite/auto-sync/src/autosync/MCUpdater.py | 42 +- suite/auto-sync/src/autosync/Targets.py | 25 +- .../SystemZ/test_systemz_mapping.txt | 16 + .../test_systemz_mapping.txt.yaml | 80 + .../src/autosync/Tests/test_header_patcher.py | 25 +- .../src/autosync/Tests/test_mcupdater.py | 127 +- .../src/autosync/Tests/test_systemz_header.h | 142 + .../src/autosync/Tests/test_sysz_header.h | 83 + .../autosync/cpptranslator/CppTranslator.py | 16 + .../src/autosync/cpptranslator/Differ.py | 3 +- .../cpptranslator/Tests/test_patches.py | 32 +- .../autosync/cpptranslator/arch_config.json | 31 +- .../cpptranslator/patches/AddCSDetail.py | 1 + .../autosync/cpptranslator/patches/Assert.py | 11 +- .../cpptranslator/patches/GetOperandRegImm.py | 4 +- .../cpptranslator/patches/Includes.py | 55 + .../cpptranslator/patches/IsRegImm.py | 4 +- .../autosync/cpptranslator/patches/isUInt.py | 45 + .../autosync/cpptranslator/saved_patches.json | 2 +- suite/auto-sync/src/autosync/inc_gen.json | 53 + suite/auto-sync/src/autosync/mcupdater.json | 34 +- suite/auto-sync/src/autosync/path_vars.json | 5 + suite/capstone_get_setup.c | 2 +- suite/cstest/include/test_detail_systemz.h | 16 +- suite/cstest/include/test_mapping.h | 126 +- suite/cstest/include/test_run.h | 2 + suite/cstest/src/cstest.c | 1 + suite/cstest/src/test_detail.c | 2 +- suite/cstest/src/test_detail_systemz.c | 56 +- suite/cstest/src/test_run.c | 9 + suite/cstest/test/CMakeLists.txt | 4 +- suite/cstest/test/src/unit_tests.c | 20 + suite/fuzz.py | 2 +- suite/fuzz/drivermc.c | 2 +- suite/fuzz/fuzz_diff.c | 2 +- suite/fuzz/fuzz_harness.c | 2 +- suite/fuzz/platform.c | 4 +- suite/test_corpus3.py | 4 +- tests/MC/SystemZ/insn-good-z196.s.yaml | 5149 -- tests/MC/SystemZ/insn-good.s.yaml | 20242 ----- tests/MC/SystemZ/insns-z13.txt.yaml | 15890 ++++ tests/MC/SystemZ/insns-z14.txt.yaml | 10830 +++ tests/MC/SystemZ/insns-z15.txt.yaml | 4920 ++ tests/MC/SystemZ/insns-z16.txt.yaml | 1650 + tests/MC/SystemZ/insns.txt.yaml | 62770 ++++++++++++++++ tests/MC/SystemZ/regs-good.s.yaml | 397 - tests/details/cs_common_details.yaml | 12 +- tests/details/systemz.yaml | 82 +- tests/integration/CMakeLists.txt | 17 + .../integration/compat_header}/README.md | 0 .../compat_header/include/compat.h | 5 + tests/integration/compat_header/src/main.c | 16 + .../src/test_arm64_compatibility_header.c | 7 +- .../src/test_sysz_compatibility_header.c | 100 + tests/integration/test_iter.c | 14 +- tests/unit/CMakeLists.txt | 14 + tests/unit/sstream.c | 347 + utils.c | 50 + utils.h | 4 +- windowsce/COMPILE.md | 2 +- 150 files changed, 180831 insertions(+), 68700 deletions(-) create mode 100644 MCAsmInfo.h delete mode 100644 arch/SystemZ/SystemZDisassembler.h create mode 100644 arch/SystemZ/SystemZDisassemblerExtension.c create mode 100644 arch/SystemZ/SystemZDisassemblerExtension.h create mode 100644 arch/SystemZ/SystemZGenCSAliasMnemMap.inc create mode 100644 arch/SystemZ/SystemZGenCSFeatureName.inc create mode 100644 arch/SystemZ/SystemZGenCSMappingInsn.inc create mode 100644 arch/SystemZ/SystemZGenCSMappingInsnName.inc create mode 100644 arch/SystemZ/SystemZGenCSMappingInsnOp.inc create mode 100644 arch/SystemZ/SystemZGenCSOpGroup.inc delete mode 100644 arch/SystemZ/SystemZGenInsnNameMaps.inc create mode 100644 arch/SystemZ/SystemZLinkage.h delete mode 100644 arch/SystemZ/SystemZMappingInsn.inc create mode 100644 bindings/python/capstone/systemz_const.py delete mode 100644 bindings/python/capstone/sysz_const.py delete mode 100644 contrib/sysz_update/0001-capstone-generate-GenRegisterInfo.inc.patch delete mode 100644 contrib/sysz_update/0002-capstone-generate-GenSubtargetInfo.inc.patch delete mode 100644 contrib/sysz_update/0003-capstone-generate-GenInstrInfo.inc.patch delete mode 100644 contrib/sysz_update/0004-capstone-generate-GenDisassemblerTables.inc.patch delete mode 100644 contrib/sysz_update/0005-capstone-generate-GenAsmWriter.inc.patch delete mode 100644 contrib/sysz_update/0006-capstone-generate-MappingInsn.inc.patch delete mode 100644 contrib/sysz_update/0007-capstone-generate-GenInsnNameMaps.inc.patch delete mode 100644 contrib/sysz_update/README.md create mode 100644 include/capstone/systemz_compatibility.h delete mode 100644 suite/auto-sync/c_tests/CMakeLists.txt create mode 100644 suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/SystemZ/test_systemz_mapping.txt create mode 100644 suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/mode_mapping/test_systemz_mapping.txt.yaml create mode 100644 suite/auto-sync/src/autosync/Tests/test_systemz_header.h create mode 100644 suite/auto-sync/src/autosync/Tests/test_sysz_header.h create mode 100644 suite/auto-sync/src/autosync/cpptranslator/patches/isUInt.py create mode 100644 suite/auto-sync/src/autosync/inc_gen.json delete mode 100644 tests/MC/SystemZ/insn-good-z196.s.yaml delete mode 100644 tests/MC/SystemZ/insn-good.s.yaml create mode 100644 tests/MC/SystemZ/insns-z13.txt.yaml create mode 100644 tests/MC/SystemZ/insns-z14.txt.yaml create mode 100644 tests/MC/SystemZ/insns-z15.txt.yaml create mode 100644 tests/MC/SystemZ/insns-z16.txt.yaml create mode 100644 tests/MC/SystemZ/insns.txt.yaml delete mode 100644 tests/MC/SystemZ/regs-good.s.yaml rename {suite/auto-sync/c_tests => tests/integration/compat_header}/README.md (100%) create mode 100644 tests/integration/compat_header/include/compat.h create mode 100644 tests/integration/compat_header/src/main.c rename {suite/auto-sync/c_tests => tests/integration/compat_header}/src/test_arm64_compatibility_header.c (92%) create mode 100644 tests/integration/compat_header/src/test_sysz_compatibility_header.c create mode 100644 tests/unit/sstream.c diff --git a/.github/workflows/CITest.yml b/.github/workflows/CITest.yml index 898abd619f..ff992074f1 100644 --- a/.github/workflows/CITest.yml +++ b/.github/workflows/CITest.yml @@ -92,25 +92,20 @@ jobs: # Work-around ASAN bug https://github.com/google/sanitizers/issues/1716 sudo sysctl vm.mmap_rnd_bits=28 - - name: "Compatibility header test" + - name: unit tests + if: startsWith(matrix.config.build-system, 'cmake') + run: | + ctest --test-dir build --output-on-failure -R unit_* + + - name: "Integration tests" if: startsWith(matrix.config.build-system, 'cmake') && matrix.config.diet-build == 'OFF' run: | - ctest --test-dir build --output-on-failure -R ASCompatibilityHeaderTest + ctest --test-dir build --output-on-failure -R integration_* - name: cstool - reaches disassembler engine run: | sh suite/run_invalid_cstool.sh - - name: cstest unit tests - if: startsWith(matrix.config.build-system, 'cmake') - run: | - ctest --test-dir build --output-on-failure -R UnitCSTest - - - name: cstest integration tests - if: startsWith(matrix.config.build-system, 'cmake') - run: | - ctest --test-dir build --output-on-failure -R IntegrationCSTest - - name: cstest MC if: startsWith(matrix.config.build-system, 'cmake') run: | diff --git a/.github/workflows/auto-sync.yml b/.github/workflows/auto-sync.yml index d1428d0655..4082c0b426 100644 --- a/.github/workflows/auto-sync.yml +++ b/.github/workflows/auto-sync.yml @@ -78,6 +78,7 @@ jobs: ./src/autosync/ASUpdater.py -d -a PPC -s IncGen ./src/autosync/ASUpdater.py -d -a LoongArch -s IncGen ./src/autosync/ASUpdater.py -d -a Mips -s IncGen + ./src/autosync/ASUpdater.py -d -a SystemZ -s IncGen - name: CppTranslator - Patch tests run: | @@ -94,10 +95,4 @@ jobs: ./src/autosync/ASUpdater.py --ci -d -a PPC -s Translate ./src/autosync/ASUpdater.py --ci -d -a LoongArch -s Translate ./src/autosync/ASUpdater.py --ci -d -a Mips -s Translate - - - name: Differ - Test save file is up-to-date - run: | - ./src/autosync/cpptranslator/Differ.py -a AArch64 --check_saved - ./src/autosync/cpptranslator/Differ.py -a ARM --check_saved - ./src/autosync/cpptranslator/Differ.py -a PPC --check_saved - ./src/autosync/cpptranslator/Differ.py -a LoongArch --check_saved + ./src/autosync/ASUpdater.py --ci -d -a SystemZ -s Translate diff --git a/CMakeLists.txt b/CMakeLists.txt index 125f8b639d..635d128fd7 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -89,7 +89,7 @@ if(APPLE AND NOT CAPSTONE_BUILD_MACOS_THIN) set(CMAKE_OSX_ARCHITECTURES "x86_64;arm64") endif() -set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE ALPHA HPPA LOONGARCH) +set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSTEMZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE ALPHA HPPA LOONGARCH) set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore Alpha HPPA LoongArch) # If building for OSX it's best to allow CMake to handle building both architectures @@ -200,6 +200,7 @@ set(HEADERS_COMMON include/capstone/x86.h include/capstone/sparc.h include/capstone/systemz.h + include/capstone/systemz_compatibility.h include/capstone/xcore.h include/capstone/m68k.h include/capstone/tms320c64x.h @@ -412,27 +413,34 @@ if(CAPSTONE_SPARC_SUPPORT) ) endif() -if(CAPSTONE_SYSZ_SUPPORT) - add_definitions(-DCAPSTONE_HAS_SYSZ) - set(SOURCES_SYSZ +if(CAPSTONE_SYSTEMZ_SUPPORT) + add_definitions(-DCAPSTONE_HAS_SYSTEMZ) + set(SOURCES_SYSTEMZ arch/SystemZ/SystemZDisassembler.c + arch/SystemZ/SystemZDisassemblerExtension.c arch/SystemZ/SystemZInstPrinter.c arch/SystemZ/SystemZMapping.c arch/SystemZ/SystemZModule.c arch/SystemZ/SystemZMCTargetDesc.c ) - set(HEADERS_SYSZ - arch/SystemZ/SystemZDisassembler.h + set(HEADERS_SYSTEMZ + arch/SystemZ/SystemZLinkage.h + arch/SystemZ/SystemZDisassemblerExtension.h + arch/SystemZ/SystemZInstPrinter.h + arch/SystemZ/SystemZMCTargetDesc.h + arch/SystemZ/SystemZMapping.h + arch/SystemZ/SystemZModule.h arch/SystemZ/SystemZGenAsmWriter.inc + arch/SystemZ/SystemZGenCSAliasMnemMap.inc + arch/SystemZ/SystemZGenCSFeatureName.inc + arch/SystemZ/SystemZGenCSMappingInsn.inc + arch/SystemZ/SystemZGenCSMappingInsnName.inc + arch/SystemZ/SystemZGenCSMappingInsnOp.inc + arch/SystemZ/SystemZGenCSOpGroup.inc arch/SystemZ/SystemZGenDisassemblerTables.inc - arch/SystemZ/SystemZGenInsnNameMaps.inc arch/SystemZ/SystemZGenInstrInfo.inc arch/SystemZ/SystemZGenRegisterInfo.inc arch/SystemZ/SystemZGenSubtargetInfo.inc - arch/SystemZ/SystemZInstPrinter.h - arch/SystemZ/SystemZMapping.h - arch/SystemZ/SystemZMappingInsn.inc - arch/SystemZ/SystemZMCTargetDesc.h ) endif() @@ -688,7 +696,7 @@ set(ALL_SOURCES ${SOURCES_PPC} ${SOURCES_X86} ${SOURCES_SPARC} - ${SOURCES_SYSZ} + ${SOURCES_SYSTEMZ} ${SOURCES_XCORE} ${SOURCES_M68K} ${SOURCES_TMS320C64X} @@ -714,7 +722,7 @@ set(ALL_HEADERS ${HEADERS_PPC} ${HEADERS_X86} ${HEADERS_SPARC} - ${HEADERS_SYSZ} + ${HEADERS_SYSTEMZ} ${HEADERS_XCORE} ${HEADERS_M68K} ${HEADERS_TMS320C64X} @@ -765,7 +773,7 @@ source_group("Source\\AARCH64" FILES ${SOURCES_AARCH64}) source_group("Source\\Mips" FILES ${SOURCES_MIPS}) source_group("Source\\PowerPC" FILES ${SOURCES_PPC}) source_group("Source\\Sparc" FILES ${SOURCES_SPARC}) -source_group("Source\\SystemZ" FILES ${SOURCES_SYSZ}) +source_group("Source\\SystemZ" FILES ${SOURCES_SYSTEMZ}) source_group("Source\\X86" FILES ${SOURCES_X86}) source_group("Source\\XCore" FILES ${SOURCES_XCORE}) source_group("Source\\M68K" FILES ${SOURCES_M68K}) @@ -789,7 +797,7 @@ source_group("Include\\AARCH64" FILES ${HEADERS_AARCH64}) source_group("Include\\Mips" FILES ${HEADERS_MIPS}) source_group("Include\\PowerPC" FILES ${HEADERS_PPC}) source_group("Include\\Sparc" FILES ${HEADERS_SPARC}) -source_group("Include\\SystemZ" FILES ${HEADERS_SYSZ}) +source_group("Include\\SystemZ" FILES ${HEADERS_SYSTEMZ}) source_group("Include\\X86" FILES ${HEADERS_X86}) source_group("Include\\XCore" FILES ${HEADERS_XCORE}) source_group("Include\\M68K" FILES ${HEADERS_M68K}) @@ -898,8 +906,4 @@ if(CAPSTONE_BUILD_CSTEST) add_subdirectory(${TESTS_INTEGRATION_DIR}) set(TESTS_UNIT_DIR ${PROJECT_SOURCE_DIR}/tests/unit) add_subdirectory(${TESTS_UNIT_DIR}) - - # Unit tests for auto-sync - set(AUTO_SYNC_C_TEST_DIR ${PROJECT_SOURCE_DIR}/suite/auto-sync/c_tests/) - add_subdirectory(${AUTO_SYNC_C_TEST_DIR}) endif() diff --git a/COMPILE_CMAKE.TXT b/COMPILE_CMAKE.TXT index abf143aad4..f6bcc2d74d 100644 --- a/COMPILE_CMAKE.TXT +++ b/COMPILE_CMAKE.TXT @@ -28,7 +28,7 @@ Get CMake for free from http://www.cmake.org. - CAPSTONE_MOS65XX_SUPPORT: support MOS65XX. Run cmake with -DCAPSTONE_MOS65XX_SUPPORT=0 to remove MOS65XX. - CAPSTONE_PPC_SUPPORT: support PPC. Run cmake with -DCAPSTONE_PPC_SUPPORT=0 to remove PPC. - CAPSTONE_SPARC_SUPPORT: support Sparc. Run cmake with -DCAPSTONE_SPARC_SUPPORT=0 to remove Sparc. - - CAPSTONE_SYSZ_SUPPORT: support SystemZ. Run cmake with -DCAPSTONE_SYSZ_SUPPORT=0 to remove SystemZ. + - CAPSTONE_SYSTEMZ_SUPPORT: support SystemZ. Run cmake with -DCAPSTONE_SYSTEMZ_SUPPORT=0 to remove SystemZ. - CAPSTONE_XCORE_SUPPORT: support XCore. Run cmake with -DCAPSTONE_XCORE_SUPPORT=0 to remove XCore. - CAPSTONE_TRICORE_SUPPORT: support TriCore. Run cmake with -DCAPSTONE_TRICORE_SUPPORT=0 to remove TriCore. - CAPSTONE_X86_SUPPORT: support X86. Run cmake with -DCAPSTONE_X86_SUPPORT=0 to remove X86. diff --git a/MCAsmInfo.h b/MCAsmInfo.h new file mode 100644 index 0000000000..5565eaa925 --- /dev/null +++ b/MCAsmInfo.h @@ -0,0 +1,19 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +/// The equivalent of the MCAsmInfo class in LLVM. +/// We save only some flags of the original class here. + +#ifndef CS_MCASMINFO_H +#define CS_MCASMINFO_H + +typedef enum { + SYSTEMZASMDIALECT_AD_ATT = 0, + SYSTEMZASMDIALECT_AD_HLASM = 1, +} MCAsmInfoAssemblerDialect; + +typedef struct { + MCAsmInfoAssemblerDialect assemblerDialect; +} MCAsmInfo; + +#endif // CS_MCASMINFO_H diff --git a/MCInst.c b/MCInst.c index 8ffc2d2dbb..0894a3f00a 100644 --- a/MCInst.c +++ b/MCInst.c @@ -16,7 +16,7 @@ #define MCINST_CACHE (ARR_SIZE(mcInst->Operands) - 1) -void MCInst_Init(MCInst *inst) +void MCInst_Init(MCInst *inst, cs_arch arch) { // unnecessary to initialize in loop . its expensive and inst->size should be honored inst->Operands[0].Kind = kInvalid; @@ -37,6 +37,15 @@ void MCInst_Init(MCInst *inst) inst->isAliasInstr = false; inst->fillDetailOps = false; memset(&inst->hppa_ext, 0, sizeof(inst->hppa_ext)); + + // Set default assembly dialect. + switch (arch) { + default: + break; + case CS_ARCH_SYSTEMZ: + inst->MAI.assemblerDialect = SYSTEMZASMDIALECT_AD_HLASM; + break; + } } void MCInst_clear(MCInst *inst) @@ -150,6 +159,11 @@ int64_t MCOperand_getImm(const MCOperand *op) return op->ImmVal; } +int64_t MCOperand_getExpr(const MCOperand *op) +{ + return op->ImmVal; +} + void MCOperand_setImm(MCOperand *op, int64_t Val) { op->ImmVal = Val; diff --git a/MCInst.h b/MCInst.h index 5d24603abf..1c69c75642 100644 --- a/MCInst.h +++ b/MCInst.h @@ -20,6 +20,7 @@ #define CS_MCINST_H #include "include/capstone/capstone.h" +#include "MCAsmInfo.h" #include "MCInstrDesc.h" #include "MCRegisterInfo.h" @@ -73,6 +74,8 @@ int64_t MCOperand_getImm(const MCOperand *op); void MCOperand_setImm(MCOperand *op, int64_t Val); +int64_t MCOperand_getExpr(const MCOperand *op); + double MCOperand_getFPImm(const MCOperand *op); void MCOperand_setFPImm(MCOperand *op, double Val); @@ -133,9 +136,10 @@ struct MCInst { bool isAliasInstr; // Flag if this MCInst is an alias. bool fillDetailOps; // If set, detail->operands gets filled. hppa_ext hppa_ext; ///< for HPPA operand. Contains info about modifiers and their effect on the instruction + MCAsmInfo MAI; ///< The equivalent to MCAsmInfo in LLVM. It holds flags relevant for the asm style to print. }; -void MCInst_Init(MCInst *inst); +void MCInst_Init(MCInst *inst, cs_arch arch); void MCInst_clear(MCInst *inst); diff --git a/Mapping.c b/Mapping.c index 2548f1cc47..d2ef694d5d 100644 --- a/Mapping.c +++ b/Mapping.c @@ -340,6 +340,7 @@ DEFINE_get_detail_op(hppa, HPPA); DEFINE_get_detail_op(loongarch, LoongArch); DEFINE_get_detail_op(mips, Mips); DEFINE_get_detail_op(riscv, RISCV); +DEFINE_get_detail_op(systemz, SystemZ); /// Returns true if for this architecture the /// alias operands should be filled. @@ -433,7 +434,7 @@ uint64_t enum_map_bin_search(const cs_enum_id_map *map, size_t map_len, } else if (id[i] > map[m].str[j]) { l = m + 1; } - if (m == 0 || (l + r) / 2 >= map_len) { + if ((m == 0 && id[i] < map[m].str[j]) || (l + r) / 2 >= map_len) { // Break before we go out of bounds. break; } diff --git a/Mapping.h b/Mapping.h index 7bbcfec003..473075ea2d 100644 --- a/Mapping.h +++ b/Mapping.h @@ -32,6 +32,7 @@ typedef struct insn_map { ppc_suppl_info ppc; loongarch_suppl_info loongarch; aarch64_suppl_info aarch64; + systemz_suppl_info systemz; } suppl_info; // Supplementary information for each instruction. #endif } insn_map; @@ -140,6 +141,7 @@ DECL_get_detail_op(hppa, HPPA); DECL_get_detail_op(loongarch, LoongArch); DECL_get_detail_op(mips, Mips); DECL_get_detail_op(riscv, RISCV); +DECL_get_detail_op(systemz, SystemZ); /// Increments the detail->arch.op_count by one. #define DEFINE_inc_detail_op_count(arch, ARCH) \ @@ -173,6 +175,8 @@ DEFINE_inc_detail_op_count(mips, Mips); DEFINE_dec_detail_op_count(mips, Mips); DEFINE_inc_detail_op_count(riscv, RISCV); DEFINE_dec_detail_op_count(riscv, RISCV); +DEFINE_inc_detail_op_count(systemz, SystemZ); +DEFINE_dec_detail_op_count(systemz, SystemZ); /// Returns true if a memory operand is currently edited. static inline bool doing_mem(const MCInst *MI) @@ -203,6 +207,7 @@ DEFINE_get_arch_detail(hppa, HPPA); DEFINE_get_arch_detail(loongarch, LoongArch); DEFINE_get_arch_detail(mips, Mips); DEFINE_get_arch_detail(riscv, RISCV); +DEFINE_get_arch_detail(systemz, SystemZ); static inline bool detail_is_set(const MCInst *MI) { diff --git a/SStream.c b/SStream.c index 6c930eb9eb..68c685c051 100644 --- a/SStream.c +++ b/SStream.c @@ -28,6 +28,19 @@ void SStream_Init(SStream *ss) ss->index = 0; ss->buffer[0] = '\0'; ss->is_closed = false; + ss->markup_stream = false; + ss->prefixed_by_markup = false; +} + +/// Empty the stream @ss to given @file (stdin/stderr). +/// @file can be NULL. Then the buffer content is not emitted. +void SStream_Flush(SStream *ss, FILE *file) +{ + assert(ss); + if (file) { + fprintf(file, "%s\n", ss->buffer); + } + SStream_Init(ss); } /** @@ -57,9 +70,17 @@ void SStream_concat0(SStream *ss, const char *s) return; unsigned int len = (unsigned int) strlen(s); + SSTREAM_OVERFLOW_CHECK(ss, len); + memcpy(ss->buffer + ss->index, s, len); ss->index += len; ss->buffer[ss->index] = '\0'; + if (ss->markup_stream && ss->prefixed_by_markup) { + SSTREAM_OVERFLOW_CHECK(ss, 1); + ss->buffer[ss->index] = '>'; + ss->index += 1; + ss->buffer[ss->index] = '\0'; + } #endif } @@ -72,9 +93,17 @@ void SStream_concat1(SStream *ss, const char c) SSTREAM_RETURN_IF_CLOSED(ss); if (c == '\0') return; + + SSTREAM_OVERFLOW_CHECK(ss, 1); + ss->buffer[ss->index] = c; ss->index++; ss->buffer[ss->index] = '\0'; + if (ss->markup_stream && ss->prefixed_by_markup) { + SSTREAM_OVERFLOW_CHECK(ss, 1); + ss->buffer[ss->index] = '>'; + ss->index++; + } #endif } @@ -92,6 +121,11 @@ void SStream_concat(SStream *ss, const char *fmt, ...) ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap); va_end(ap); ss->index += ret; + if (ss->markup_stream && ss->prefixed_by_markup) { + SSTREAM_OVERFLOW_CHECK(ss, 1); + ss->buffer[ss->index] = '>'; + ss->index += 1; + } #endif } @@ -99,29 +133,15 @@ void SStream_concat(SStream *ss, const char *fmt, ...) void printInt64Bang(SStream *O, int64_t val) { SSTREAM_RETURN_IF_CLOSED(O); - if (val >= 0) { - if (val > HEX_THRESHOLD) - SStream_concat(O, "#0x%"PRIx64, val); - else - SStream_concat(O, "#%"PRIu64, val); - } else { - if (val <- HEX_THRESHOLD) { - if (val == LONG_MIN) - SStream_concat(O, "#-0x%"PRIx64, (uint64_t)val); - else - SStream_concat(O, "#-0x%"PRIx64, (uint64_t)-val); - } else - SStream_concat(O, "#-%"PRIu64, -val); - } + SStream_concat1(O, '#'); + printInt64(O, val); } void printUInt64Bang(SStream *O, uint64_t val) { SSTREAM_RETURN_IF_CLOSED(O); - if (val > HEX_THRESHOLD) - SStream_concat(O, "#0x%"PRIx64, val); - else - SStream_concat(O, "#%"PRIu64, val); + SStream_concat1(O, '#'); + printUInt64(O, val); } // print number @@ -134,9 +154,9 @@ void printInt64(SStream *O, int64_t val) else SStream_concat(O, "%"PRIu64, val); } else { - if (val <- HEX_THRESHOLD) { - if (val == LONG_MIN) - SStream_concat(O, "-0x%"PRIx64, (uint64_t)val); + if (val < -HEX_THRESHOLD) { + if (val == INT64_MIN) + SStream_concat(O, "-0x%"PRIx64, (uint64_t) INT64_MAX + 1); else SStream_concat(O, "-0x%"PRIx64, (uint64_t)-val); } else @@ -158,60 +178,82 @@ void printInt32BangDec(SStream *O, int32_t val) { SSTREAM_RETURN_IF_CLOSED(O); if (val >= 0) - SStream_concat(O, "#%u", val); + SStream_concat(O, "#%" PRIu32, val); else { - if (val == INT_MIN) - SStream_concat(O, "#-%u", val); + if (val == INT32_MIN) + SStream_concat(O, "#-%" PRIu32, val); else - SStream_concat(O, "#-%u", (uint32_t)-val); + SStream_concat(O, "#-%" PRIu32, (uint32_t)-val); } } void printInt32Bang(SStream *O, int32_t val) +{ + SSTREAM_RETURN_IF_CLOSED(O); + SStream_concat1(O, '#'); + printInt32(O, val); +} + +void printInt8(SStream *O, int8_t val) { SSTREAM_RETURN_IF_CLOSED(O); if (val >= 0) { if (val > HEX_THRESHOLD) - SStream_concat(O, "#0x%x", val); + SStream_concat(O, "0x%" PRIx8, val); else - SStream_concat(O, "#%u", val); + SStream_concat(O, "%" PRId8, val); } else { - if (val <- HEX_THRESHOLD) { - if (val == INT_MIN) - SStream_concat(O, "#-0x%x", (uint32_t)val); + if (val < -HEX_THRESHOLD) { + if (val == INT8_MIN) + SStream_concat(O, "-0x%" PRIx8, (uint8_t) INT8_MAX + 1); else - SStream_concat(O, "#-0x%x", (uint32_t)-val); + SStream_concat(O, "-0x%" PRIx8, (int8_t)-val); } else - SStream_concat(O, "#-%u", -val); + SStream_concat(O, "-%" PRIu8, -val); } } -void printInt32(SStream *O, int32_t val) +void printInt16(SStream *O, int16_t val) { SSTREAM_RETURN_IF_CLOSED(O); if (val >= 0) { if (val > HEX_THRESHOLD) - SStream_concat(O, "0x%x", val); + SStream_concat(O, "0x%" PRIx16, val); else - SStream_concat(O, "%u", val); + SStream_concat(O, "%" PRId16, val); } else { - if (val <- HEX_THRESHOLD) { - if (val == INT_MIN) - SStream_concat(O, "-0x%x", (uint32_t)val); + if (val < -HEX_THRESHOLD) { + if (val == INT16_MIN) + SStream_concat(O, "-0x%" PRIx16, (uint16_t) INT16_MAX + 1); else - SStream_concat(O, "-0x%x", (uint32_t)-val); + SStream_concat(O, "-0x%" PRIx16, (int16_t)-val); } else - SStream_concat(O, "-%u", -val); + SStream_concat(O, "-%" PRIu16, -val); + } +} + +void printInt32(SStream *O, int32_t val) +{ + SSTREAM_RETURN_IF_CLOSED(O); + if (val >= 0) { + if (val > HEX_THRESHOLD) + SStream_concat(O, "0x%" PRIx32, val); + else + SStream_concat(O, "%" PRId32, val); + } else { + if (val < -HEX_THRESHOLD) { + SStream_concat(O, "-0x%" PRIx32, (uint32_t)-val); + } else { + SStream_concat(O, "-%" PRIu32, (uint32_t)-val); + } } } void printUInt32Bang(SStream *O, uint32_t val) { SSTREAM_RETURN_IF_CLOSED(O); - if (val > HEX_THRESHOLD) - SStream_concat(O, "#0x%x", val); - else - SStream_concat(O, "#%u", val); + SStream_concat1(O, '#'); + printUInt32(O, val); } void printUInt32(SStream *O, uint32_t val) @@ -234,3 +276,38 @@ void printFloatBang(SStream *O, float val) SSTREAM_RETURN_IF_CLOSED(O); SStream_concat(O, "#%e", val); } + +void printExpr(SStream *O, uint64_t val) +{ + SSTREAM_RETURN_IF_CLOSED(O); + SStream_concat(O, "%"PRIu64, val); +} + +SStream *markup_OS(SStream *OS, SStreamMarkup style) { + assert(OS); + + if (OS->is_closed || !OS->markup_stream) { + return OS; + } + OS->markup_stream = false; // Disable temporarily. + switch (style) { + default: + SStream_concat0(OS, "markup_stream = true; + OS->prefixed_by_markup = true; + return OS; +} diff --git a/SStream.h b/SStream.h index 46eca0d419..35c90738d4 100644 --- a/SStream.h +++ b/SStream.h @@ -5,13 +5,33 @@ #define CS_SSTREAM_H_ #include "include/capstone/platform.h" +#include + +typedef enum { + Markup_Immediate, + Markup_Register, + Markup_Target, + Markup_Memory, +} SStreamMarkup; + +#define SSTREAM_BUF_LEN 512 typedef struct SStream { - char buffer[512]; + char buffer[SSTREAM_BUF_LEN]; int index; bool is_closed; + bool markup_stream; ///< If true, markups to the stream are allowed. + bool prefixed_by_markup; ///< Set after the stream wrote a markup for an operand. } SStream; +#define SSTREAM_OVERFLOW_CHECK(OS, len) \ +do { \ + if (OS->index + len + 1 > SSTREAM_BUF_LEN) { \ + fprintf(stderr, "Buffer overflow caught!\n"); \ + return; \ + } \ +} while(0) + #define SSTREAM_RETURN_IF_CLOSED(OS) \ do { \ if (OS->is_closed) \ @@ -20,6 +40,8 @@ do { \ void SStream_Init(SStream *ss); +void SStream_Flush(SStream *ss, FILE *file); + void SStream_Open(SStream *ss); void SStream_Close(SStream *ss); @@ -39,6 +61,8 @@ void printUInt64(SStream *O, uint64_t val); void printInt32Bang(SStream *O, int32_t val); +void printInt8(SStream *O, int8_t val); +void printInt16(SStream *O, int16_t val); void printInt32(SStream *O, int32_t val); void printUInt32Bang(SStream *O, uint32_t val); @@ -52,4 +76,8 @@ void printFloat(SStream *O, float val); void printFloatBang(SStream *O, float val); +void printExpr(SStream *O, uint64_t val); + +SStream *markup_OS(SStream *OS, SStreamMarkup style); + #endif diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c index 677c27a418..4dfbfc0165 100644 --- a/arch/ARM/ARMInstPrinter.c +++ b/arch/ARM/ARMInstPrinter.c @@ -359,7 +359,7 @@ static void printInst(MCInst *MI, SStream *O, void *info) if (MCRegisterClass_contains(MRC, Reg)) { MCInst NewMI; - MCInst_Init(&NewMI); + MCInst_Init(&NewMI, CS_ARCH_ARM); MCInst_setOpcode(&NewMI, Opcode); if (isStore) diff --git a/arch/SystemZ/SystemZDisassembler.c b/arch/SystemZ/SystemZDisassembler.c index a64a85c4d7..359e11be71 100644 --- a/arch/SystemZ/SystemZDisassembler.c +++ b/arch/SystemZ/SystemZDisassembler.c @@ -1,484 +1,408 @@ -//===------ SystemZDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically translated source file from LLVM. */ -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* LLVM-commit: */ +/* LLVM-tag: */ -#ifdef CAPSTONE_HAS_SYSZ +/* Only small edits allowed. */ +/* For multiple similar edits, please create a Patch for the translator. */ -#include // DEBUG -#include -#include +/* Capstone's C++ file translator: */ +/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ -#include "../../cs_priv.h" -#include "../../utils.h" +//===-- SystemZDisassembler.cpp - Disassembler for SystemZ ------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// -#include "SystemZDisassembler.h" +#include +#include +#include +#include #include "../../MCInst.h" -#include "../../MCInstrDesc.h" -#include "../../MCFixedLenDisassembler.h" -#include "../../MCRegisterInfo.h" -#include "../../MCDisassembler.h" #include "../../MathExtras.h" +#include "../../MCInstPrinter.h" +#include "../../MCDisassembler.h" +#include "../../MCFixedLenDisassembler.h" +#include "../../cs_priv.h" +#include "../../utils.h" #include "SystemZMCTargetDesc.h" - -static uint64_t getFeatureBits(int mode) -{ - // support everything - return (uint64_t)-1; -} - -static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, const unsigned *Regs) -{ - //assert(RegNo < 16 && "Invalid register"); - RegNo = Regs[RegNo]; - if (RegNo == 0) - return MCDisassembler_Fail; - - MCOperand_CreateReg0(Inst, (unsigned)RegNo); +#include "SystemZDisassemblerExtension.h" + +#define CONCAT(a, b) CONCAT_(a, b) +#define CONCAT_(a, b) a##_##b + +#define DEBUG_TYPE "systemz-disassembler" + +static DecodeStatus getInstruction(MCInst *Instr, uint16_t *Size, const uint8_t *Bytes, + size_t BytesLen, uint64_t Address, + SStream *CStream); + +/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the +/// immediate Value in the MCInst. +/// +/// @param Value - The immediate Value, has had any PC adjustment made by +/// the caller. +/// @param isBranch - If the instruction is a branch instruction +/// @param Address - The starting address of the instruction +/// @param Offset - The byte offset to this immediate in the instruction +/// @param Width - The byte width of this immediate in the instruction +/// +/// If the getOpInfo() function was set when setupForSymbolicDisassembly() was +/// called then that function is called to get any symbolic information for the +/// immediate in the instruction using the Address, Offset and Width. If that +/// returns non-zero then the symbolic information it returns is used to create +/// an MCExpr and that is added as an operand to the MCInst. If getOpInfo() +/// returns zero and isBranch is true then a symbol look up for immediate Value +/// is done and if a symbol is found an MCExpr is created with that, else +/// an MCExpr with the immediate Value is created. This function returns true +/// if it adds an operand to the MCInst and false otherwise. +static bool tryAddingSymbolicOperand(int64_t Value, bool IsBranch, + uint64_t Address, uint64_t Offset, + uint64_t Width, MCInst *MI, + const void *Decoder) +{ + // return Decoder->tryAddingSymbolicOperand(MI, Value, Address, IsBranch, + // Offset, Width, /*InstSize=*/0); + return false; +} + +static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, + const unsigned *Regs, unsigned Size, + bool IsAddr) +{ + CS_ASSERT((RegNo < Size && "Invalid register")); + if (IsAddr && RegNo == 0) { + RegNo = SystemZ_NoRegister; + } else { + RegNo = Regs[RegNo]; + if (RegNo == 0) + return MCDisassembler_Fail; + } + MCOperand_CreateReg0(Inst, (RegNo)); return MCDisassembler_Success; } static DecodeStatus DecodeGR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) + uint64_t Address, + const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC_GR32Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC_GR32Regs, 16, false); } static DecodeStatus DecodeGRH32BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) + uint64_t Address, + const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC_GRH32Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC_GRH32Regs, 16, false); } static DecodeStatus DecodeGR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) + uint64_t Address, + const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs, 16, false); } static DecodeStatus DecodeGR128BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) + uint64_t Address, + const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, SystemZMC_GR128Regs, 16, false); +} + +static DecodeStatus DecodeADDR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC_GR128Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC_GR32Regs, 16, true); } static DecodeStatus DecodeADDR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) + uint64_t Address, + const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs, 16, true); } static DecodeStatus DecodeFP32BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) + uint64_t Address, + const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC_FP32Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC_FP32Regs, 16, false); } static DecodeStatus DecodeFP64BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) + uint64_t Address, + const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC_FP64Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC_FP64Regs, 16, false); } static DecodeStatus DecodeFP128BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) + uint64_t Address, + const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC_FP128Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC_FP128Regs, 16, false); } static DecodeStatus DecodeVR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) + uint64_t Address, + const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC_VR32Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC_VR32Regs, 32, false); } static DecodeStatus DecodeVR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) + uint64_t Address, + const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC_VR64Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC_VR64Regs, 32, false); } static DecodeStatus DecodeVR128BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) + uint64_t Address, + const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC_VR128Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC_VR128Regs, 32, false); } static DecodeStatus DecodeAR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) + uint64_t Address, + const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, SystemZMC_AR32Regs); + return decodeRegisterClass(Inst, RegNo, SystemZMC_AR32Regs, 16, false); } static DecodeStatus DecodeCR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, SystemZMC_CR64Regs); -} - -static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm) + uint64_t Address, + const void *Decoder) { - //assert(isUInt(Imm) && "Invalid immediate"); - MCOperand_CreateImm0(Inst, Imm); - return MCDisassembler_Success; + return decodeRegisterClass(Inst, RegNo, SystemZMC_CR64Regs, 16, false); } -static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, unsigned N) -{ - //assert(isUInt(Imm) && "Invalid immediate"); - MCOperand_CreateImm0(Inst, SignExtend64(Imm, N)); - return MCDisassembler_Success; -} +#define DEFINE_decodeUImmOperand(N) \ + static DecodeStatus CONCAT(decodeUImmOperand, N)(MCInst * Inst, \ + uint64_t Imm) \ + { \ + if (!isUIntN(N, Imm)) \ + return MCDisassembler_Fail; \ + MCOperand_CreateImm0(Inst, (Imm)); \ + return MCDisassembler_Success; \ + } +DEFINE_decodeUImmOperand(1); +DEFINE_decodeUImmOperand(2); +DEFINE_decodeUImmOperand(3); +DEFINE_decodeUImmOperand(4); +DEFINE_decodeUImmOperand(8); +DEFINE_decodeUImmOperand(12); +DEFINE_decodeUImmOperand(16); +DEFINE_decodeUImmOperand(32); + +#define DEFINE_decodeSImmOperand(N) \ + static DecodeStatus CONCAT(decodeSImmOperand, N)(MCInst * Inst, \ + uint64_t Imm) \ + { \ + if (!isUIntN(N, Imm)) \ + return MCDisassembler_Fail; \ + MCOperand_CreateImm0(Inst, (SignExtend64((Imm), N))); \ + return MCDisassembler_Success; \ + } +DEFINE_decodeSImmOperand(8); +DEFINE_decodeSImmOperand(16); +DEFINE_decodeSImmOperand(20); +DEFINE_decodeSImmOperand(32); static DecodeStatus decodeU1ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) + uint64_t Address, const void *Decoder) { - return decodeUImmOperand(Inst, Imm); + return CONCAT(decodeUImmOperand, 1)(Inst, Imm); } static DecodeStatus decodeU2ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) + uint64_t Address, const void *Decoder) { - return decodeUImmOperand(Inst, Imm); + return CONCAT(decodeUImmOperand, 2)(Inst, Imm); } static DecodeStatus decodeU3ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) + uint64_t Address, const void *Decoder) { - return decodeUImmOperand(Inst, Imm); + return CONCAT(decodeUImmOperand, 3)(Inst, Imm); } static DecodeStatus decodeU4ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) + uint64_t Address, const void *Decoder) { - return decodeUImmOperand(Inst, Imm); -} - -static DecodeStatus decodeU6ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) -{ - return decodeUImmOperand(Inst, Imm); + return CONCAT(decodeUImmOperand, 4)(Inst, Imm); } static DecodeStatus decodeU8ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) + uint64_t Address, const void *Decoder) { - return decodeUImmOperand(Inst, Imm); + return CONCAT(decodeUImmOperand, 8)(Inst, Imm); } static DecodeStatus decodeU12ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) + uint64_t Address, const void *Decoder) { - return decodeUImmOperand(Inst, Imm); + return CONCAT(decodeUImmOperand, 12)(Inst, Imm); } static DecodeStatus decodeU16ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) + uint64_t Address, const void *Decoder) { - return decodeUImmOperand(Inst, Imm); + return CONCAT(decodeUImmOperand, 16)(Inst, Imm); } static DecodeStatus decodeU32ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) + uint64_t Address, const void *Decoder) { - return decodeUImmOperand(Inst, Imm); + return CONCAT(decodeUImmOperand, 32)(Inst, Imm); } static DecodeStatus decodeS8ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) + uint64_t Address, const void *Decoder) { - return decodeSImmOperand(Inst, Imm, 8); + return CONCAT(decodeSImmOperand, 8)(Inst, Imm); } static DecodeStatus decodeS16ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) + uint64_t Address, const void *Decoder) { - return decodeSImmOperand(Inst, Imm, 16); + return CONCAT(decodeSImmOperand, 16)(Inst, Imm); } -static DecodeStatus decodeS32ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) +static DecodeStatus decodeS20ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) { - return decodeSImmOperand(Inst, Imm, 32); + return CONCAT(decodeSImmOperand, 20)(Inst, Imm); } -static DecodeStatus decodePCDBLOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, unsigned N) +static DecodeStatus decodeS32ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) { - //assert(isUInt(Imm) && "Invalid PC-relative offset"); - MCOperand_CreateImm0(Inst, SignExtend64(Imm, N) * 2 + Address); - return MCDisassembler_Success; + return CONCAT(decodeSImmOperand, 32)(Inst, Imm); } +#define DEFINE_decodeLenOperand(N) \ + static DecodeStatus CONCAT(decodeLenOperand, \ + N)(MCInst * Inst, uint64_t Imm, \ + uint64_t Address, const void *Decoder) \ + { \ + if (!isUIntN(N, Imm)) \ + return MCDisassembler_Fail; \ + MCOperand_CreateImm0(Inst, (Imm + 1)); \ + return MCDisassembler_Success; \ + } +DEFINE_decodeLenOperand(8); +DEFINE_decodeLenOperand(4); + +#define DEFINE_decodePCDBLOperand(N) \ + static DecodeStatus CONCAT(decodePCDBLOperand, N)( \ + MCInst * Inst, uint64_t Imm, uint64_t Address, bool isBranch, \ + const void *Decoder) \ + { \ + CS_ASSERT((isUIntN(N, Imm) && "Invalid PC-relative offset")); \ + uint64_t Value = SignExtend64((Imm), N) * 2 + Address; \ +\ + if (!tryAddingSymbolicOperand(Value, isBranch, Address, 2, \ + N / 8, Inst, Decoder)) \ + MCOperand_CreateImm0(Inst, (Value)); \ +\ + return MCDisassembler_Success; \ + } +DEFINE_decodePCDBLOperand(12); +DEFINE_decodePCDBLOperand(16); +DEFINE_decodePCDBLOperand(24); +DEFINE_decodePCDBLOperand(32); + static DecodeStatus decodePC12DBLBranchOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, - const void *Decoder) + uint64_t Address, + const void *Decoder) { - return decodePCDBLOperand(Inst, Imm, Address, 12); + return CONCAT(decodePCDBLOperand, 12)(Inst, Imm, Address, true, + Decoder); } static DecodeStatus decodePC16DBLBranchOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, - const void *Decoder) + uint64_t Address, + const void *Decoder) { - return decodePCDBLOperand(Inst, Imm, Address, 16); + return CONCAT(decodePCDBLOperand, 16)(Inst, Imm, Address, true, + Decoder); } static DecodeStatus decodePC24DBLBranchOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, - const void *Decoder) + uint64_t Address, + const void *Decoder) { - return decodePCDBLOperand(Inst, Imm, Address, 24); + return CONCAT(decodePCDBLOperand, 24)(Inst, Imm, Address, true, + Decoder); } static DecodeStatus decodePC32DBLBranchOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, - const void *Decoder) + uint64_t Address, + const void *Decoder) { - return decodePCDBLOperand(Inst, Imm, Address, 32); + return CONCAT(decodePCDBLOperand, 32)(Inst, Imm, Address, true, + Decoder); } static DecodeStatus decodePC32DBLOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, - const void *Decoder) + uint64_t Address, const void *Decoder) { - return decodePCDBLOperand(Inst, Imm, Address, 32); -} - -static DecodeStatus decodeBDAddr12Operand(MCInst *Inst, uint64_t Field, - const unsigned *Regs) -{ - uint64_t Base = Field >> 12; - uint64_t Disp = Field & 0xfff; - //assert(Base < 16 && "Invalid BDAddr12"); - - MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); - MCOperand_CreateImm0(Inst, Disp); - - return MCDisassembler_Success; -} - -static DecodeStatus decodeBDAddr20Operand(MCInst *Inst, uint64_t Field, - const unsigned *Regs) -{ - uint64_t Base = Field >> 20; - uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff); - //assert(Base < 16 && "Invalid BDAddr20"); - - MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); - MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20)); - return MCDisassembler_Success; -} - -static DecodeStatus decodeBDXAddr12Operand(MCInst *Inst, uint64_t Field, - const unsigned *Regs) -{ - uint64_t Index = Field >> 16; - uint64_t Base = (Field >> 12) & 0xf; - uint64_t Disp = Field & 0xfff; - - //assert(Index < 16 && "Invalid BDXAddr12"); - MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); - MCOperand_CreateImm0(Inst, Disp); - MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]); - - return MCDisassembler_Success; + return CONCAT(decodePCDBLOperand, 32)(Inst, Imm, Address, false, + Decoder); } -static DecodeStatus decodeBDXAddr20Operand(MCInst *Inst, uint64_t Field, - const unsigned *Regs) -{ - uint64_t Index = Field >> 24; - uint64_t Base = (Field >> 20) & 0xf; - uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12); - - //assert(Index < 16 && "Invalid BDXAddr20"); - MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); - MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20)); - MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]); - - return MCDisassembler_Success; -} - -static DecodeStatus decodeBDLAddr12Len8Operand(MCInst *Inst, uint64_t Field, - const unsigned *Regs) -{ - uint64_t Length = Field >> 16; - uint64_t Base = (Field >> 12) & 0xf; - uint64_t Disp = Field & 0xfff; - //assert(Length < 256 && "Invalid BDLAddr12Len8"); - - MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); - MCOperand_CreateImm0(Inst, Disp); - MCOperand_CreateImm0(Inst, Length + 1); - - return MCDisassembler_Success; -} - -static DecodeStatus decodeBDRAddr12Operand(MCInst *Inst, uint64_t Field, - const unsigned *Regs) -{ - uint64_t Length = Field >> 16; - uint64_t Base = (Field >> 12) & 0xf; - uint64_t Disp = Field & 0xfff; - //assert(Length < 16 && "Invalid BDRAddr12"); - - MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); - MCOperand_CreateImm0(Inst, Disp); - MCOperand_CreateReg0(Inst, Regs[Length]); - - return MCDisassembler_Success; -} - -static DecodeStatus decodeBDVAddr12Operand(MCInst *Inst, uint64_t Field, - const unsigned *Regs) -{ - uint64_t Index = Field >> 16; - uint64_t Base = (Field >> 12) & 0xf; - uint64_t Disp = Field & 0xfff; - //assert(Index < 32 && "Invalid BDVAddr12"); - - MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); - MCOperand_CreateImm0(Inst, Disp); - MCOperand_CreateReg0(Inst, SystemZMC_VR128Regs[Index]); - - return MCDisassembler_Success; -} - -static DecodeStatus decodeBDAddr32Disp12Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDAddr12Operand(Inst, Field, SystemZMC_GR32Regs); -} - -static DecodeStatus decodeBDAddr32Disp20Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDAddr20Operand(Inst, Field, SystemZMC_GR32Regs); -} - -static DecodeStatus decodeBDAddr64Disp12Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDAddr12Operand(Inst, Field, SystemZMC_GR64Regs); -} - -static DecodeStatus decodeBDAddr64Disp20Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDAddr20Operand(Inst, Field, SystemZMC_GR64Regs); -} - -static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDXAddr12Operand(Inst, Field, SystemZMC_GR64Regs); -} - -static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDXAddr20Operand(Inst, Field, SystemZMC_GR64Regs); -} - -static DecodeStatus decodeBDLAddr64Disp12Len4Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC_GR64Regs); -} - -static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC_GR64Regs); -} - -static DecodeStatus decodeBDRAddr64Disp12Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDRAddr12Operand(Inst, Field, SystemZMC_GR64Regs); -} - -static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDVAddr12Operand(Inst, Field, SystemZMC_GR64Regs); -} - - -#define GET_SUBTARGETINFO_ENUM -#include "SystemZGenSubtargetInfo.inc" #include "SystemZGenDisassemblerTables.inc" -bool SystemZ_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, - uint16_t *size, uint64_t address, void *info) + +static DecodeStatus getInstruction(MCInst *MI, uint16_t *Size, const uint8_t *Bytes, + size_t BytesLen, uint64_t Address, SStream *CS) { - uint64_t Inst; - const uint8_t *Table; - uint16_t I; + // Get the first two bytes of the instruction. + *Size = 0; + if (BytesLen < 2) + return MCDisassembler_Fail; // The top 2 bits of the first byte specify the size. - if (*code < 0x40) { - *size = 2; + const uint8_t *Table; + uint64_t Inst = 0; + if (Bytes[0] < 0x40) { + *Size = 2; Table = DecoderTable16; - } else if (*code < 0xc0) { - *size = 4; + Inst = readBytes16(MI, Bytes); + } else if (Bytes[0] < 0xc0) { + *Size = 4; Table = DecoderTable32; + Inst = readBytes32(MI, Bytes); } else { - *size = 6; + *Size = 6; Table = DecoderTable48; + Inst = readBytes48(MI, Bytes); } - if (code_len < *size) - // short of input data - return false; - - if (MI->flat_insn->detail) { - memset(MI->flat_insn->detail, 0, offsetof(cs_detail, sysz)+sizeof(cs_sysz)); + // Read any remaining bytes. + if (BytesLen < *Size) { + *Size = BytesLen; + return MCDisassembler_Fail; } - // Construct the instruction. - Inst = 0; - for (I = 0; I < *size; ++I) - Inst = (Inst << 8) | code[I]; - - return decodeInstruction(Table, MI, Inst, address, info, 0); -} - -#define GET_REGINFO_ENUM -#define GET_REGINFO_MC_DESC -#include "SystemZGenRegisterInfo.inc" -void SystemZ_init(MCRegisterInfo *MRI) -{ - /* - InitMCRegisterInfo(SystemZRegDesc, 98, RA, PC, - SystemZMCRegisterClasses, 12, - SystemZRegUnitRoots, - 49, - SystemZRegDiffLists, - SystemZRegStrings, - SystemZSubRegIdxLists, - 7, - SystemZSubRegIdxRanges, - SystemZRegEncodingTable); - */ - - MCRegisterInfo_InitMCRegisterInfo(MRI, SystemZRegDesc, 194, - 0, 0, - SystemZMCRegisterClasses, 21, - 0, 0, - SystemZRegDiffLists, - 0, - SystemZSubRegIdxLists, 7, - 0); -} - -#endif + return decodeInstruction_8(Table, MI, Inst, Address, NULL); +} + +DecodeStatus SystemZ_LLVM_getInstruction(csh handle, const uint8_t *Bytes, + size_t BytesLen, MCInst *MI, + uint16_t *Size, uint64_t Address, + void *Info) +{ + return getInstruction(MI, Size, Bytes, BytesLen, MI->address, NULL); +} diff --git a/arch/SystemZ/SystemZDisassembler.h b/arch/SystemZ/SystemZDisassembler.h deleted file mode 100644 index 8b6e540551..0000000000 --- a/arch/SystemZ/SystemZDisassembler.h +++ /dev/null @@ -1,17 +0,0 @@ -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ - -#ifndef CS_SYSZDISASSEMBLER_H -#define CS_SYSZDISASSEMBLER_H - -#include "capstone/capstone.h" -#include "../../MCRegisterInfo.h" -#include "../../MCInst.h" - -void SystemZ_init(MCRegisterInfo *MRI); - -bool SystemZ_getInstruction(csh ud, const uint8_t *code, size_t code_len, - MCInst *instr, uint16_t *size, uint64_t address, void *info); - -#endif - diff --git a/arch/SystemZ/SystemZDisassemblerExtension.c b/arch/SystemZ/SystemZDisassemblerExtension.c new file mode 100644 index 0000000000..c1a01d6f5e --- /dev/null +++ b/arch/SystemZ/SystemZDisassemblerExtension.c @@ -0,0 +1,116 @@ +/* Capstone Disassembly Engine */ +/* By Rot127 , 2022-2023 */ + +#include +#include "SystemZDisassemblerExtension.h" +#include "../../utils.h" + +#include "SystemZMCTargetDesc.h" + +static int systemz_arch9_features[] = { + SystemZ_FeatureDistinctOps, + SystemZ_FeatureFastSerialization, + SystemZ_FeatureFPExtension, + SystemZ_FeatureHighWord, + SystemZ_FeatureInterlockedAccess1, + SystemZ_FeatureLoadStoreOnCond, + SystemZ_FeaturePopulationCount, + SystemZ_FeatureMessageSecurityAssist3, + SystemZ_FeatureMessageSecurityAssist4, + SystemZ_FeatureResetReferenceBitsMultiple +}; + +static int systemz_arch10_features[] = { + SystemZ_FeatureExecutionHint, + SystemZ_FeatureLoadAndTrap, + SystemZ_FeatureMiscellaneousExtensions, + SystemZ_FeatureProcessorAssist, + SystemZ_FeatureTransactionalExecution, + SystemZ_FeatureDFPZonedConversion, + SystemZ_FeatureEnhancedDAT2 +}; + +static int systemz_arch11_features[] = { + SystemZ_FeatureLoadAndZeroRightmostByte, + SystemZ_FeatureLoadStoreOnCond2, + SystemZ_FeatureMessageSecurityAssist5, + SystemZ_FeatureDFPPackedConversion, + SystemZ_FeatureVector +}; + +static int systemz_arch12_features[] = { + SystemZ_FeatureMiscellaneousExtensions2, + SystemZ_FeatureGuardedStorage, + SystemZ_FeatureMessageSecurityAssist7, + SystemZ_FeatureMessageSecurityAssist8, + SystemZ_FeatureVectorEnhancements1, + SystemZ_FeatureVectorPackedDecimal, + SystemZ_FeatureInsertReferenceBitsMultiple +}; + +static int systemz_arch13_features[] = { + SystemZ_FeatureMiscellaneousExtensions3, + SystemZ_FeatureMessageSecurityAssist9, + SystemZ_FeatureVectorEnhancements2, + SystemZ_FeatureVectorPackedDecimalEnhancement, + SystemZ_FeatureEnhancedSort, + SystemZ_FeatureDeflateConversion +}; + +static int systemz_arch14_features[] = { + SystemZ_FeatureVectorPackedDecimalEnhancement2, + SystemZ_FeatureNNPAssist, + SystemZ_FeatureBEAREnhancement, + SystemZ_FeatureResetDATProtection, + SystemZ_FeatureProcessorActivityInstrumentation +}; + +bool SystemZ_getFeatureBits(unsigned int mode, unsigned int feature) { + switch (mode & ~CS_MODE_BIG_ENDIAN) { + case CS_MODE_SYSTEMZ_ARCH14: + case CS_MODE_SYSTEMZ_Z16: + if (arr_exist_int(systemz_arch14_features, ARR_SIZE(systemz_arch14_features), feature)) { + return true; + } + // fallthrough + case CS_MODE_SYSTEMZ_ARCH13: + case CS_MODE_SYSTEMZ_Z15: + if (arr_exist_int(systemz_arch13_features, ARR_SIZE(systemz_arch13_features), feature)) { + return true; + } + // fallthrough + case CS_MODE_SYSTEMZ_ARCH12: + case CS_MODE_SYSTEMZ_Z14: + if (arr_exist_int(systemz_arch12_features, ARR_SIZE(systemz_arch12_features), feature)) { + return true; + } + // fallthrough + case CS_MODE_SYSTEMZ_ARCH11: + case CS_MODE_SYSTEMZ_Z13: + if (arr_exist_int(systemz_arch11_features, ARR_SIZE(systemz_arch11_features), feature)) { + return true; + } + // fallthrough + case CS_MODE_SYSTEMZ_ARCH10: + case CS_MODE_SYSTEMZ_ZEC12: + if (arr_exist_int(systemz_arch10_features, ARR_SIZE(systemz_arch10_features), feature)) { + return true; + } + // fallthrough + case CS_MODE_SYSTEMZ_ARCH9: + case CS_MODE_SYSTEMZ_Z196: + if (arr_exist_int(systemz_arch9_features, ARR_SIZE(systemz_arch9_features), feature)) { + return true; + } + // fallthrough + case CS_MODE_SYSTEMZ_GENERIC: + case CS_MODE_SYSTEMZ_ARCH8: + case CS_MODE_SYSTEMZ_Z10: + // There are no features defined for Arch8 + return false; + default: + // Default case is the "allow all features", which is normal Capstone behavior + // until https://github.com/capstone-engine/capstone/issues/1992 is implemented. + return true; + } +} diff --git a/arch/SystemZ/SystemZDisassemblerExtension.h b/arch/SystemZ/SystemZDisassemblerExtension.h new file mode 100644 index 0000000000..bd2a88d364 --- /dev/null +++ b/arch/SystemZ/SystemZDisassemblerExtension.h @@ -0,0 +1,11 @@ +/* Capstone Disassembly Engine */ +/* By Rot127 , 2022-2023 */ + +#ifndef CS_SYSTEMZ_DISASSEMBLER_EXTENSION_H +#define CS_SYSTEMZ_DISASSEMBLER_EXTENSION_H + +#include + +bool SystemZ_getFeatureBits(unsigned int mode, unsigned int feature); + +#endif // CS_SYSTEMZ_DISASSEMBLER_EXTENSION_H diff --git a/arch/SystemZ/SystemZGenAsmWriter.inc b/arch/SystemZ/SystemZGenAsmWriter.inc index 182d1c12e1..a02ea2131d 100644 --- a/arch/SystemZ/SystemZGenAsmWriter.inc +++ b/arch/SystemZ/SystemZGenAsmWriter.inc @@ -1,2232 +1,2393 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* Assembly Writer Source Fragment *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* LLVM-commit: */ +/* LLVM-tag: */ -#include // debug -#include +/* Do not edit. */ +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ -/// printInstruction - This method is automatically generated by tablegen +#include +#include + +/// getMnemonic - This method is automatically generated by tablegen /// from the instruction set description. -static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) -{ +static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { - /* 0 */ 'c', 'u', '2', '1', 9, 0, - /* 6 */ 'c', 'u', '4', '1', 9, 0, - /* 12 */ 'c', 'u', '1', '2', 9, 0, - /* 18 */ 'c', 'u', '4', '2', 9, 0, - /* 24 */ 'c', 'u', '1', '4', 9, 0, - /* 30 */ 'c', 'u', '2', '4', 9, 0, - /* 36 */ 't', 'r', 'a', 'p', '4', 9, 0, - /* 43 */ 'l', 'a', 'a', 9, 0, - /* 48 */ 's', 'l', 'd', 'a', 9, 0, - /* 54 */ 's', 'r', 'd', 'a', 9, 0, - /* 60 */ 'e', 's', 'e', 'a', 9, 0, - /* 66 */ 'l', 'p', 't', 'e', 'a', 9, 0, - /* 73 */ 'v', 'f', 'a', 9, 0, - /* 78 */ 's', 'i', 'g', 'a', 9, 0, - /* 84 */ 'e', 'c', 'p', 'g', 'a', 9, 0, - /* 91 */ 'u', 'n', 'p', 'k', 'a', 9, 0, - /* 98 */ 's', 'p', 'k', 'a', 9, 0, - /* 104 */ 's', 'l', 'a', 9, 0, - /* 109 */ 'v', 'g', 'f', 'm', 'a', 9, 0, - /* 116 */ 'v', 'f', 'm', 'a', 9, 0, - /* 122 */ 'k', 'm', 'a', 9, 0, - /* 127 */ 'v', 'f', 'n', 'm', 'a', 9, 0, - /* 134 */ 'p', 'p', 'a', 9, 0, - /* 139 */ 'l', 'e', 'd', 'b', 'r', 'a', 9, 0, - /* 147 */ 'c', 'f', 'd', 'b', 'r', 'a', 9, 0, - /* 155 */ 'c', 'g', 'd', 'b', 'r', 'a', 9, 0, - /* 163 */ 'f', 'i', 'd', 'b', 'r', 'a', 9, 0, - /* 171 */ 'c', 'f', 'e', 'b', 'r', 'a', 9, 0, - /* 179 */ 'c', 'g', 'e', 'b', 'r', 'a', 9, 0, - /* 187 */ 'f', 'i', 'e', 'b', 'r', 'a', 9, 0, - /* 195 */ 'c', 'd', 'f', 'b', 'r', 'a', 9, 0, - /* 203 */ 'c', 'e', 'f', 'b', 'r', 'a', 9, 0, - /* 211 */ 'c', 'x', 'f', 'b', 'r', 'a', 9, 0, - /* 219 */ 'c', 'd', 'g', 'b', 'r', 'a', 9, 0, - /* 227 */ 'c', 'e', 'g', 'b', 'r', 'a', 9, 0, - /* 235 */ 'c', 'x', 'g', 'b', 'r', 'a', 9, 0, - /* 243 */ 'l', 'd', 'x', 'b', 'r', 'a', 9, 0, - /* 251 */ 'l', 'e', 'x', 'b', 'r', 'a', 9, 0, - /* 259 */ 'c', 'f', 'x', 'b', 'r', 'a', 9, 0, - /* 267 */ 'c', 'g', 'x', 'b', 'r', 'a', 9, 0, - /* 275 */ 'f', 'i', 'x', 'b', 'r', 'a', 9, 0, - /* 283 */ 'l', 'r', 'a', 9, 0, - /* 288 */ 'v', 'e', 's', 'r', 'a', 9, 0, - /* 295 */ 'v', 's', 'r', 'a', 9, 0, - /* 301 */ 'a', 'd', 't', 'r', 'a', 9, 0, - /* 308 */ 'd', 'd', 't', 'r', 'a', 9, 0, - /* 315 */ 'c', 'g', 'd', 't', 'r', 'a', 9, 0, - /* 323 */ 'm', 'd', 't', 'r', 'a', 9, 0, - /* 330 */ 's', 'd', 't', 'r', 'a', 9, 0, - /* 337 */ 'c', 'd', 'g', 't', 'r', 'a', 9, 0, - /* 345 */ 'c', 'x', 'g', 't', 'r', 'a', 9, 0, - /* 353 */ 'a', 'x', 't', 'r', 'a', 9, 0, - /* 360 */ 'd', 'x', 't', 'r', 'a', 9, 0, - /* 367 */ 'c', 'g', 'x', 't', 'r', 'a', 9, 0, - /* 375 */ 'm', 'x', 't', 'r', 'a', 9, 0, - /* 382 */ 's', 'x', 't', 'r', 'a', 9, 0, - /* 389 */ 'l', 'u', 'r', 'a', 9, 0, - /* 395 */ 's', 't', 'u', 'r', 'a', 9, 0, - /* 402 */ 'b', 's', 'a', 9, 0, - /* 407 */ 'e', 's', 't', 'a', 9, 0, - /* 413 */ 'm', 's', 't', 'a', 9, 0, - /* 419 */ 'v', 'a', 9, 0, - /* 423 */ 'c', 'p', 'y', 'a', 9, 0, - /* 429 */ 'v', 'g', 'f', 'm', 'a', 'b', 9, 0, - /* 437 */ 'v', 'e', 's', 'r', 'a', 'b', 9, 0, - /* 445 */ 'v', 's', 'r', 'a', 'b', 9, 0, - /* 452 */ 'v', 'a', 'b', 9, 0, - /* 457 */ 'l', 'c', 'b', 'b', 9, 0, - /* 463 */ 'v', 'l', 'b', 'b', 9, 0, - /* 469 */ 'v', 'a', 'c', 'c', 'b', 9, 0, - /* 476 */ 'v', 'e', 'c', 'b', 9, 0, - /* 482 */ 'v', 'l', 'c', 'b', 9, 0, - /* 488 */ 'v', 's', 't', 'r', 'c', 'b', 9, 0, - /* 496 */ 'v', 'f', 'a', 'd', 'b', 9, 0, - /* 503 */ 'w', 'f', 'a', 'd', 'b', 9, 0, - /* 510 */ 'v', 'f', 'm', 'a', 'd', 'b', 9, 0, - /* 518 */ 'w', 'f', 'm', 'a', 'd', 'b', 9, 0, - /* 526 */ 'v', 'f', 'n', 'm', 'a', 'd', 'b', 9, 0, - /* 535 */ 'w', 'f', 'n', 'm', 'a', 'd', 'b', 9, 0, - /* 544 */ 'w', 'f', 'c', 'd', 'b', 9, 0, - /* 551 */ 'v', 'f', 'l', 'c', 'd', 'b', 9, 0, - /* 559 */ 'w', 'f', 'l', 'c', 'd', 'b', 9, 0, - /* 567 */ 't', 'c', 'd', 'b', 9, 0, - /* 573 */ 'v', 'f', 'd', 'd', 'b', 9, 0, - /* 580 */ 'w', 'f', 'd', 'd', 'b', 9, 0, - /* 587 */ 'v', 'f', 'c', 'e', 'd', 'b', 9, 0, - /* 595 */ 'w', 'f', 'c', 'e', 'd', 'b', 9, 0, - /* 603 */ 'v', 'f', 'c', 'h', 'e', 'd', 'b', 9, 0, - /* 612 */ 'w', 'f', 'c', 'h', 'e', 'd', 'b', 9, 0, - /* 621 */ 'v', 'f', 'k', 'h', 'e', 'd', 'b', 9, 0, - /* 630 */ 'w', 'f', 'k', 'h', 'e', 'd', 'b', 9, 0, - /* 639 */ 'v', 'f', 'k', 'e', 'd', 'b', 9, 0, - /* 647 */ 'w', 'f', 'k', 'e', 'd', 'b', 9, 0, - /* 655 */ 'v', 'l', 'e', 'd', 'b', 9, 0, - /* 662 */ 'w', 'l', 'e', 'd', 'b', 9, 0, - /* 669 */ 'v', 'c', 'g', 'd', 'b', 9, 0, - /* 676 */ 'w', 'c', 'g', 'd', 'b', 9, 0, - /* 683 */ 'v', 'c', 'l', 'g', 'd', 'b', 9, 0, - /* 691 */ 'w', 'c', 'l', 'g', 'd', 'b', 9, 0, - /* 699 */ 'v', 'f', 'c', 'h', 'd', 'b', 9, 0, - /* 707 */ 'w', 'f', 'c', 'h', 'd', 'b', 9, 0, - /* 715 */ 'v', 'f', 'k', 'h', 'd', 'b', 9, 0, - /* 723 */ 'w', 'f', 'k', 'h', 'd', 'b', 9, 0, - /* 731 */ 'v', 'f', 't', 'c', 'i', 'd', 'b', 9, 0, - /* 740 */ 'w', 'f', 't', 'c', 'i', 'd', 'b', 9, 0, - /* 749 */ 'v', 'f', 'i', 'd', 'b', 9, 0, - /* 756 */ 'w', 'f', 'i', 'd', 'b', 9, 0, - /* 763 */ 'w', 'f', 'k', 'd', 'b', 9, 0, - /* 770 */ 'v', 's', 'l', 'd', 'b', 9, 0, - /* 777 */ 'v', 'f', 'm', 'd', 'b', 9, 0, - /* 784 */ 'w', 'f', 'm', 'd', 'b', 9, 0, - /* 791 */ 'v', 'f', 'm', 'i', 'n', 'd', 'b', 9, 0, - /* 800 */ 'w', 'f', 'm', 'i', 'n', 'd', 'b', 9, 0, - /* 809 */ 'v', 'f', 'l', 'n', 'd', 'b', 9, 0, - /* 817 */ 'w', 'f', 'l', 'n', 'd', 'b', 9, 0, - /* 825 */ 'v', 'f', 'p', 's', 'o', 'd', 'b', 9, 0, - /* 834 */ 'w', 'f', 'p', 's', 'o', 'd', 'b', 9, 0, - /* 843 */ 'v', 'f', 'l', 'p', 'd', 'b', 9, 0, - /* 851 */ 'w', 'f', 'l', 'p', 'd', 'b', 9, 0, - /* 859 */ 'v', 'f', 's', 'q', 'd', 'b', 9, 0, - /* 867 */ 'w', 'f', 's', 'q', 'd', 'b', 9, 0, - /* 875 */ 'v', 'f', 's', 'd', 'b', 9, 0, - /* 882 */ 'w', 'f', 's', 'd', 'b', 9, 0, - /* 889 */ 'v', 'f', 'm', 's', 'd', 'b', 9, 0, - /* 897 */ 'w', 'f', 'm', 's', 'd', 'b', 9, 0, - /* 905 */ 'v', 'f', 'n', 'm', 's', 'd', 'b', 9, 0, - /* 914 */ 'w', 'f', 'n', 'm', 's', 'd', 'b', 9, 0, - /* 923 */ 'v', 'f', 'm', 'a', 'x', 'd', 'b', 9, 0, - /* 932 */ 'w', 'f', 'm', 'a', 'x', 'd', 'b', 9, 0, - /* 941 */ 'l', 'x', 'd', 'b', 9, 0, - /* 947 */ 'm', 'x', 'd', 'b', 9, 0, - /* 953 */ 'v', 'f', 'a', 'e', 'b', 9, 0, - /* 960 */ 'v', 'm', 'a', 'e', 'b', 9, 0, - /* 967 */ 't', 'c', 'e', 'b', 9, 0, - /* 973 */ 'v', 'l', 'd', 'e', 'b', 9, 0, - /* 980 */ 'w', 'l', 'd', 'e', 'b', 9, 0, - /* 987 */ 'm', 'd', 'e', 'b', 9, 0, - /* 993 */ 'v', 'f', 'e', 'e', 'b', 9, 0, - /* 1000 */ 'm', 'e', 'e', 'b', 9, 0, - /* 1006 */ 'k', 'e', 'b', 9, 0, - /* 1011 */ 'v', 'm', 'a', 'l', 'e', 'b', 9, 0, - /* 1019 */ 'v', 'm', 'l', 'e', 'b', 9, 0, - /* 1026 */ 'v', 'l', 'e', 'b', 9, 0, - /* 1032 */ 'v', 'm', 'e', 'b', 9, 0, - /* 1038 */ 'v', 'f', 'e', 'n', 'e', 'b', 9, 0, - /* 1046 */ 's', 'q', 'e', 'b', 9, 0, - /* 1052 */ 'm', 's', 'e', 'b', 9, 0, - /* 1058 */ 'v', 's', 't', 'e', 'b', 9, 0, - /* 1065 */ 'l', 'x', 'e', 'b', 9, 0, - /* 1071 */ 'v', 'c', 'd', 'g', 'b', 9, 0, - /* 1078 */ 'w', 'c', 'd', 'g', 'b', 9, 0, - /* 1085 */ 'v', 's', 'e', 'g', 'b', 9, 0, - /* 1092 */ 'v', 'c', 'd', 'l', 'g', 'b', 9, 0, - /* 1100 */ 'w', 'c', 'd', 'l', 'g', 'b', 9, 0, - /* 1108 */ 'v', 'a', 'v', 'g', 'b', 9, 0, - /* 1115 */ 'v', 'l', 'v', 'g', 'b', 9, 0, - /* 1122 */ 'v', 'm', 'a', 'h', 'b', 9, 0, - /* 1129 */ 'v', 'c', 'h', 'b', 9, 0, - /* 1135 */ 'v', 'm', 'a', 'l', 'h', 'b', 9, 0, - /* 1143 */ 'v', 'm', 'l', 'h', 'b', 9, 0, - /* 1150 */ 'v', 'u', 'p', 'l', 'h', 'b', 9, 0, - /* 1158 */ 'v', 'm', 'h', 'b', 9, 0, - /* 1164 */ 'v', 'u', 'p', 'h', 'b', 9, 0, - /* 1171 */ 'v', 'm', 'r', 'h', 'b', 9, 0, - /* 1178 */ 'v', 's', 'c', 'b', 'i', 'b', 9, 0, - /* 1186 */ 'c', 'i', 'b', 9, 0, - /* 1191 */ 'v', 'l', 'e', 'i', 'b', 9, 0, - /* 1198 */ 'c', 'g', 'i', 'b', 9, 0, - /* 1204 */ 'c', 'l', 'g', 'i', 'b', 9, 0, - /* 1211 */ 'c', 'l', 'i', 'b', 9, 0, - /* 1217 */ 'v', 'r', 'e', 'p', 'i', 'b', 9, 0, - /* 1225 */ 'v', 'm', 'a', 'l', 'b', 9, 0, - /* 1232 */ 'v', 'e', 'c', 'l', 'b', 9, 0, - /* 1239 */ 'v', 'a', 'v', 'g', 'l', 'b', 9, 0, - /* 1247 */ 'v', 'c', 'h', 'l', 'b', 9, 0, - /* 1254 */ 'v', 'u', 'p', 'l', 'l', 'b', 9, 0, - /* 1262 */ 'v', 'e', 'r', 'l', 'l', 'b', 9, 0, - /* 1270 */ 'v', 'm', 'l', 'b', 9, 0, - /* 1276 */ 'v', 'm', 'n', 'l', 'b', 9, 0, - /* 1283 */ 'v', 'u', 'p', 'l', 'b', 9, 0, - /* 1290 */ 'v', 'm', 'r', 'l', 'b', 9, 0, - /* 1297 */ 'v', 'e', 's', 'r', 'l', 'b', 9, 0, - /* 1305 */ 'v', 's', 'r', 'l', 'b', 9, 0, - /* 1312 */ 'v', 'e', 's', 'l', 'b', 9, 0, - /* 1319 */ 'v', 's', 'l', 'b', 9, 0, - /* 1325 */ 'v', 'm', 'x', 'l', 'b', 9, 0, - /* 1332 */ 'v', 'g', 'f', 'm', 'b', 9, 0, - /* 1339 */ 'v', 'g', 'm', 'b', 9, 0, - /* 1345 */ 'v', 'e', 'r', 'i', 'm', 'b', 9, 0, - /* 1353 */ 's', 'r', 'n', 'm', 'b', 9, 0, - /* 1360 */ 'v', 's', 'u', 'm', 'b', 9, 0, - /* 1367 */ 'v', 'm', 'n', 'b', 9, 0, - /* 1373 */ 'v', 'm', 'a', 'o', 'b', 9, 0, - /* 1380 */ 'v', 'm', 'a', 'l', 'o', 'b', 9, 0, - /* 1388 */ 'v', 'm', 'l', 'o', 'b', 9, 0, - /* 1395 */ 'v', 'm', 'o', 'b', 9, 0, - /* 1401 */ 'v', 'l', 'r', 'e', 'p', 'b', 9, 0, - /* 1409 */ 'v', 'r', 'e', 'p', 'b', 9, 0, - /* 1416 */ 'v', 'l', 'p', 'b', 9, 0, - /* 1422 */ 'v', 'c', 'e', 'q', 'b', 9, 0, - /* 1429 */ 'c', 'r', 'b', 9, 0, - /* 1434 */ 'c', 'g', 'r', 'b', 9, 0, - /* 1440 */ 'c', 'l', 'g', 'r', 'b', 9, 0, - /* 1447 */ 'c', 'l', 'r', 'b', 9, 0, - /* 1453 */ 'v', 'i', 's', 't', 'r', 'b', 9, 0, - /* 1461 */ 'v', 'f', 'a', 's', 'b', 9, 0, - /* 1468 */ 'w', 'f', 'a', 's', 'b', 9, 0, - /* 1475 */ 'v', 'f', 'm', 'a', 's', 'b', 9, 0, - /* 1483 */ 'w', 'f', 'm', 'a', 's', 'b', 9, 0, - /* 1491 */ 'v', 'f', 'n', 'm', 'a', 's', 'b', 9, 0, - /* 1500 */ 'w', 'f', 'n', 'm', 'a', 's', 'b', 9, 0, - /* 1509 */ 'w', 'f', 'c', 's', 'b', 9, 0, - /* 1516 */ 'v', 'f', 'l', 'c', 's', 'b', 9, 0, - /* 1524 */ 'w', 'f', 'l', 'c', 's', 'b', 9, 0, - /* 1532 */ 'v', 'f', 'd', 's', 'b', 9, 0, - /* 1539 */ 'w', 'f', 'd', 's', 'b', 9, 0, - /* 1546 */ 'v', 'f', 'c', 'e', 's', 'b', 9, 0, - /* 1554 */ 'w', 'f', 'c', 'e', 's', 'b', 9, 0, - /* 1562 */ 'v', 'f', 'c', 'h', 'e', 's', 'b', 9, 0, - /* 1571 */ 'w', 'f', 'c', 'h', 'e', 's', 'b', 9, 0, - /* 1580 */ 'v', 'f', 'k', 'h', 'e', 's', 'b', 9, 0, - /* 1589 */ 'w', 'f', 'k', 'h', 'e', 's', 'b', 9, 0, - /* 1598 */ 'v', 'f', 'k', 'e', 's', 'b', 9, 0, - /* 1606 */ 'w', 'f', 'k', 'e', 's', 'b', 9, 0, - /* 1614 */ 'v', 'f', 'c', 'h', 's', 'b', 9, 0, - /* 1622 */ 'w', 'f', 'c', 'h', 's', 'b', 9, 0, - /* 1630 */ 'v', 'f', 'k', 'h', 's', 'b', 9, 0, - /* 1638 */ 'w', 'f', 'k', 'h', 's', 'b', 9, 0, - /* 1646 */ 'v', 'f', 't', 'c', 'i', 's', 'b', 9, 0, - /* 1655 */ 'w', 'f', 't', 'c', 'i', 's', 'b', 9, 0, - /* 1664 */ 'v', 'f', 'i', 's', 'b', 9, 0, - /* 1671 */ 'w', 'f', 'i', 's', 'b', 9, 0, - /* 1678 */ 'w', 'f', 'k', 's', 'b', 9, 0, - /* 1685 */ 'v', 'f', 'm', 's', 'b', 9, 0, - /* 1692 */ 'w', 'f', 'm', 's', 'b', 9, 0, - /* 1699 */ 'v', 'f', 'm', 'i', 'n', 's', 'b', 9, 0, - /* 1708 */ 'w', 'f', 'm', 'i', 'n', 's', 'b', 9, 0, - /* 1717 */ 'v', 'f', 'l', 'n', 's', 'b', 9, 0, - /* 1725 */ 'w', 'f', 'l', 'n', 's', 'b', 9, 0, - /* 1733 */ 'v', 'f', 'p', 's', 'o', 's', 'b', 9, 0, - /* 1742 */ 'w', 'f', 'p', 's', 'o', 's', 'b', 9, 0, - /* 1751 */ 'v', 'f', 'l', 'p', 's', 'b', 9, 0, - /* 1759 */ 'w', 'f', 'l', 'p', 's', 'b', 9, 0, - /* 1767 */ 'v', 'f', 's', 'q', 's', 'b', 9, 0, - /* 1775 */ 'w', 'f', 's', 'q', 's', 'b', 9, 0, - /* 1783 */ 'v', 'f', 's', 's', 'b', 9, 0, - /* 1790 */ 'w', 'f', 's', 's', 'b', 9, 0, - /* 1797 */ 'v', 'f', 'm', 's', 's', 'b', 9, 0, - /* 1805 */ 'w', 'f', 'm', 's', 's', 'b', 9, 0, - /* 1813 */ 'v', 'f', 'n', 'm', 's', 's', 'b', 9, 0, - /* 1822 */ 'w', 'f', 'n', 'm', 's', 's', 'b', 9, 0, - /* 1831 */ 'v', 's', 'b', 9, 0, - /* 1836 */ 'v', 'f', 'm', 'a', 'x', 's', 'b', 9, 0, - /* 1845 */ 'w', 'f', 'm', 'a', 'x', 's', 'b', 9, 0, - /* 1854 */ 'v', 'p', 'o', 'p', 'c', 't', 'b', 9, 0, - /* 1863 */ 'v', 'e', 's', 'r', 'a', 'v', 'b', 9, 0, - /* 1872 */ 'v', 'c', 'v', 'b', 9, 0, - /* 1878 */ 'v', 'l', 'g', 'v', 'b', 9, 0, - /* 1885 */ 'v', 'e', 'r', 'l', 'l', 'v', 'b', 9, 0, - /* 1894 */ 'v', 'e', 's', 'r', 'l', 'v', 'b', 9, 0, - /* 1903 */ 'v', 'e', 's', 'l', 'v', 'b', 9, 0, - /* 1911 */ 'w', 'f', 'a', 'x', 'b', 9, 0, - /* 1918 */ 'w', 'f', 'm', 'a', 'x', 'b', 9, 0, - /* 1926 */ 'w', 'f', 'n', 'm', 'a', 'x', 'b', 9, 0, - /* 1935 */ 'w', 'f', 'c', 'x', 'b', 9, 0, - /* 1942 */ 'w', 'f', 'l', 'c', 'x', 'b', 9, 0, - /* 1950 */ 't', 'c', 'x', 'b', 9, 0, - /* 1956 */ 'w', 'f', 'd', 'x', 'b', 9, 0, - /* 1963 */ 'w', 'f', 'c', 'e', 'x', 'b', 9, 0, - /* 1971 */ 'w', 'f', 'c', 'h', 'e', 'x', 'b', 9, 0, - /* 1980 */ 'w', 'f', 'k', 'h', 'e', 'x', 'b', 9, 0, - /* 1989 */ 'w', 'f', 'k', 'e', 'x', 'b', 9, 0, - /* 1997 */ 'w', 'f', 'c', 'h', 'x', 'b', 9, 0, - /* 2005 */ 'w', 'f', 'k', 'h', 'x', 'b', 9, 0, - /* 2013 */ 'w', 'f', 't', 'c', 'i', 'x', 'b', 9, 0, - /* 2022 */ 'w', 'f', 'i', 'x', 'b', 9, 0, - /* 2029 */ 'w', 'f', 'k', 'x', 'b', 9, 0, - /* 2036 */ 'w', 'f', 'm', 'x', 'b', 9, 0, - /* 2043 */ 'v', 'm', 'x', 'b', 9, 0, - /* 2049 */ 'w', 'f', 'm', 'i', 'n', 'x', 'b', 9, 0, - /* 2058 */ 'w', 'f', 'l', 'n', 'x', 'b', 9, 0, - /* 2066 */ 'w', 'f', 'p', 's', 'o', 'x', 'b', 9, 0, - /* 2075 */ 'w', 'f', 'l', 'p', 'x', 'b', 9, 0, - /* 2083 */ 'w', 'f', 's', 'q', 'x', 'b', 9, 0, - /* 2091 */ 'w', 'f', 's', 'x', 'b', 9, 0, - /* 2098 */ 'w', 'f', 'm', 's', 'x', 'b', 9, 0, - /* 2106 */ 'w', 'f', 'n', 'm', 's', 'x', 'b', 9, 0, - /* 2115 */ 'w', 'f', 'm', 'a', 'x', 'x', 'b', 9, 0, - /* 2124 */ 'v', 's', 't', 'r', 'c', 'z', 'b', 9, 0, - /* 2133 */ 'v', 'f', 'a', 'e', 'z', 'b', 9, 0, - /* 2141 */ 'v', 'f', 'e', 'e', 'z', 'b', 9, 0, - /* 2149 */ 'v', 'l', 'l', 'e', 'z', 'b', 9, 0, - /* 2157 */ 'v', 'f', 'e', 'n', 'e', 'z', 'b', 9, 0, - /* 2166 */ 'v', 'c', 'l', 'z', 'b', 9, 0, - /* 2173 */ 'v', 'c', 't', 'z', 'b', 9, 0, - /* 2180 */ 'i', 'a', 'c', 9, 0, - /* 2185 */ 'k', 'm', 'a', 'c', 9, 0, - /* 2191 */ 's', 'a', 'c', 9, 0, - /* 2196 */ 'v', 'a', 'c', 9, 0, - /* 2201 */ 'b', 'c', 9, 0, - /* 2205 */ 'v', 'a', 'c', 'c', 9, 0, - /* 2211 */ 'v', 'a', 'c', 'c', 'c', 9, 0, - /* 2218 */ 'v', 'e', 'c', 9, 0, - /* 2223 */ 'c', 'f', 'c', 9, 0, - /* 2228 */ 'w', 'f', 'c', 9, 0, - /* 2233 */ 'l', 'l', 'g', 'c', 9, 0, - /* 2239 */ 'm', 's', 'g', 'c', 9, 0, - /* 2245 */ 'b', 'i', 'c', 9, 0, - /* 2250 */ 's', 'c', 'k', 'c', 9, 0, - /* 2256 */ 's', 't', 'c', 'k', 'c', 9, 0, - /* 2263 */ 'm', 's', 'g', 'r', 'k', 'c', 9, 0, - /* 2271 */ 'm', 's', 'r', 'k', 'c', 9, 0, - /* 2278 */ 'a', 'l', 'c', 9, 0, - /* 2283 */ 'c', 'l', 'c', 9, 0, - /* 2288 */ 'l', 'l', 'c', 9, 0, - /* 2293 */ 'v', 'l', 'c', 9, 0, - /* 2298 */ 'k', 'm', 'c', 9, 0, - /* 2303 */ 't', 'b', 'e', 'g', 'i', 'n', 'c', 9, 0, - /* 2312 */ 'v', 'n', 'c', 9, 0, - /* 2317 */ 'l', 'o', 'c', 9, 0, - /* 2322 */ 's', 't', 'o', 'c', 9, 0, - /* 2328 */ 'v', 'o', 'c', 9, 0, - /* 2333 */ 'e', 'f', 'p', 'c', 9, 0, - /* 2339 */ 'l', 'f', 'p', 'c', 9, 0, - /* 2345 */ 's', 'f', 'p', 'c', 9, 0, - /* 2351 */ 's', 't', 'f', 'p', 'c', 9, 0, - /* 2358 */ 'b', 'r', 'c', 9, 0, - /* 2363 */ 'v', 's', 't', 'r', 'c', 9, 0, - /* 2370 */ 'l', 'g', 's', 'c', 9, 0, - /* 2376 */ 's', 't', 'g', 's', 'c', 9, 0, - /* 2383 */ 'm', 's', 'c', 9, 0, - /* 2388 */ 'c', 'm', 'p', 's', 'c', 9, 0, - /* 2395 */ 's', 't', 'c', 9, 0, - /* 2400 */ 'm', 'v', 'c', 9, 0, - /* 2405 */ 's', 'v', 'c', 9, 0, - /* 2410 */ 'x', 'c', 9, 0, - /* 2414 */ 'm', 'a', 'd', 9, 0, - /* 2419 */ 'c', 'd', 9, 0, - /* 2423 */ 'd', 'd', 9, 0, - /* 2427 */ 'v', 'l', 'e', 'd', 9, 0, - /* 2433 */ 'p', 'f', 'd', 9, 0, - /* 2438 */ 'v', 'f', 'd', 9, 0, - /* 2443 */ 'v', 'c', 'g', 'd', 9, 0, - /* 2449 */ 'v', 'c', 'l', 'g', 'd', 9, 0, - /* 2456 */ 'w', 'f', 'l', 'l', 'd', 9, 0, - /* 2463 */ 'k', 'i', 'm', 'd', 9, 0, - /* 2469 */ 'k', 'l', 'm', 'd', 9, 0, - /* 2475 */ 'e', 't', 'n', 'd', 9, 0, - /* 2481 */ 'l', 'p', 'd', 9, 0, - /* 2486 */ 's', 'q', 'd', 9, 0, - /* 2491 */ 'v', 'f', 'l', 'r', 'd', 9, 0, - /* 2498 */ 'w', 'f', 'l', 'r', 'd', 9, 0, - /* 2505 */ 'm', 's', 'd', 9, 0, - /* 2510 */ 's', 't', 'd', 9, 0, - /* 2515 */ 'v', 'c', 'v', 'd', 9, 0, - /* 2521 */ 'l', 'x', 'd', 9, 0, - /* 2526 */ 'm', 'x', 'd', 9, 0, - /* 2531 */ 'v', 'f', 'a', 'e', 9, 0, - /* 2537 */ 'l', 'a', 'e', 9, 0, - /* 2542 */ 'v', 'm', 'a', 'e', 9, 0, - /* 2548 */ 'c', 'i', 'b', 'e', 9, 0, - /* 2554 */ 'c', 'g', 'i', 'b', 'e', 9, 0, - /* 2561 */ 'c', 'l', 'g', 'i', 'b', 'e', 9, 0, - /* 2569 */ 'c', 'l', 'i', 'b', 'e', 9, 0, - /* 2576 */ 'c', 'r', 'b', 'e', 9, 0, - /* 2582 */ 'c', 'g', 'r', 'b', 'e', 9, 0, - /* 2589 */ 'c', 'l', 'g', 'r', 'b', 'e', 9, 0, - /* 2597 */ 'c', 'l', 'r', 'b', 'e', 9, 0, - /* 2604 */ 'r', 'r', 'b', 'e', 9, 0, - /* 2610 */ 't', 'r', 'a', 'c', 'e', 9, 0, - /* 2617 */ 'v', 'f', 'c', 'e', 9, 0, - /* 2623 */ 'l', 'o', 'c', 'e', 9, 0, - /* 2629 */ 's', 't', 'o', 'c', 'e', 9, 0, - /* 2636 */ 'v', 'l', 'd', 'e', 9, 0, - /* 2642 */ 'm', 'd', 'e', 9, 0, - /* 2647 */ 'v', 'f', 'e', 'e', 9, 0, - /* 2653 */ 'm', 'e', 'e', 9, 0, - /* 2658 */ 'l', 'o', 'c', 'g', 'e', 9, 0, - /* 2665 */ 's', 't', 'o', 'c', 'g', 'e', 9, 0, - /* 2673 */ 'j', 'g', 'e', 9, 0, - /* 2678 */ 'c', 'i', 'b', 'h', 'e', 9, 0, - /* 2685 */ 'c', 'g', 'i', 'b', 'h', 'e', 9, 0, - /* 2693 */ 'c', 'l', 'g', 'i', 'b', 'h', 'e', 9, 0, - /* 2702 */ 'c', 'l', 'i', 'b', 'h', 'e', 9, 0, - /* 2710 */ 'c', 'r', 'b', 'h', 'e', 9, 0, - /* 2717 */ 'c', 'g', 'r', 'b', 'h', 'e', 9, 0, - /* 2725 */ 'c', 'l', 'g', 'r', 'b', 'h', 'e', 9, 0, - /* 2734 */ 'c', 'l', 'r', 'b', 'h', 'e', 9, 0, - /* 2742 */ 'v', 'f', 'c', 'h', 'e', 9, 0, - /* 2749 */ 'l', 'o', 'c', 'h', 'e', 9, 0, - /* 2756 */ 's', 't', 'o', 'c', 'h', 'e', 9, 0, - /* 2764 */ 'l', 'o', 'c', 'f', 'h', 'e', 9, 0, - /* 2772 */ 's', 't', 'o', 'c', 'f', 'h', 'e', 9, 0, - /* 2781 */ 'l', 'o', 'c', 'g', 'h', 'e', 9, 0, - /* 2789 */ 's', 't', 'o', 'c', 'g', 'h', 'e', 9, 0, - /* 2798 */ 'j', 'g', 'h', 'e', 9, 0, - /* 2804 */ 'l', 'o', 'c', 'f', 'h', 'h', 'e', 9, 0, - /* 2813 */ 's', 't', 'o', 'c', 'f', 'h', 'h', 'e', 9, 0, - /* 2823 */ 'b', 'i', 'h', 'e', 9, 0, - /* 2829 */ 'l', 'o', 'c', 'h', 'i', 'h', 'e', 9, 0, - /* 2838 */ 'l', 'o', 'c', 'g', 'h', 'i', 'h', 'e', 9, 0, - /* 2848 */ 'l', 'o', 'c', 'h', 'h', 'i', 'h', 'e', 9, 0, - /* 2858 */ 'c', 'i', 'j', 'h', 'e', 9, 0, - /* 2865 */ 'c', 'g', 'i', 'j', 'h', 'e', 9, 0, - /* 2873 */ 'c', 'l', 'g', 'i', 'j', 'h', 'e', 9, 0, - /* 2882 */ 'c', 'l', 'i', 'j', 'h', 'e', 9, 0, - /* 2890 */ 'c', 'r', 'j', 'h', 'e', 9, 0, - /* 2897 */ 'c', 'g', 'r', 'j', 'h', 'e', 9, 0, - /* 2905 */ 'c', 'l', 'g', 'r', 'j', 'h', 'e', 9, 0, - /* 2914 */ 'c', 'l', 'r', 'j', 'h', 'e', 9, 0, - /* 2922 */ 'c', 'i', 'b', 'n', 'h', 'e', 9, 0, - /* 2930 */ 'c', 'g', 'i', 'b', 'n', 'h', 'e', 9, 0, - /* 2939 */ 'c', 'l', 'g', 'i', 'b', 'n', 'h', 'e', 9, 0, - /* 2949 */ 'c', 'l', 'i', 'b', 'n', 'h', 'e', 9, 0, - /* 2958 */ 'c', 'r', 'b', 'n', 'h', 'e', 9, 0, - /* 2966 */ 'c', 'g', 'r', 'b', 'n', 'h', 'e', 9, 0, - /* 2975 */ 'c', 'l', 'g', 'r', 'b', 'n', 'h', 'e', 9, 0, - /* 2985 */ 'c', 'l', 'r', 'b', 'n', 'h', 'e', 9, 0, - /* 2994 */ 'l', 'o', 'c', 'n', 'h', 'e', 9, 0, - /* 3002 */ 's', 't', 'o', 'c', 'n', 'h', 'e', 9, 0, - /* 3011 */ 'l', 'o', 'c', 'g', 'n', 'h', 'e', 9, 0, - /* 3020 */ 's', 't', 'o', 'c', 'g', 'n', 'h', 'e', 9, 0, - /* 3030 */ 'j', 'g', 'n', 'h', 'e', 9, 0, - /* 3037 */ 'l', 'o', 'c', 'f', 'h', 'n', 'h', 'e', 9, 0, - /* 3047 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'h', 'e', 9, 0, - /* 3058 */ 'b', 'i', 'n', 'h', 'e', 9, 0, - /* 3065 */ 'l', 'o', 'c', 'h', 'i', 'n', 'h', 'e', 9, 0, - /* 3075 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'h', 'e', 9, 0, - /* 3086 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'h', 'e', 9, 0, - /* 3097 */ 'c', 'i', 'j', 'n', 'h', 'e', 9, 0, - /* 3105 */ 'c', 'g', 'i', 'j', 'n', 'h', 'e', 9, 0, - /* 3114 */ 'c', 'l', 'g', 'i', 'j', 'n', 'h', 'e', 9, 0, - /* 3124 */ 'c', 'l', 'i', 'j', 'n', 'h', 'e', 9, 0, - /* 3133 */ 'c', 'r', 'j', 'n', 'h', 'e', 9, 0, - /* 3141 */ 'c', 'g', 'r', 'j', 'n', 'h', 'e', 9, 0, - /* 3150 */ 'c', 'l', 'g', 'r', 'j', 'n', 'h', 'e', 9, 0, - /* 3160 */ 'c', 'l', 'r', 'j', 'n', 'h', 'e', 9, 0, - /* 3169 */ 'l', 'o', 'c', 'r', 'n', 'h', 'e', 9, 0, - /* 3178 */ 'l', 'o', 'c', 'g', 'r', 'n', 'h', 'e', 9, 0, - /* 3188 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'h', 'e', 9, 0, - /* 3199 */ 'c', 'l', 'g', 't', 'n', 'h', 'e', 9, 0, - /* 3208 */ 'c', 'i', 't', 'n', 'h', 'e', 9, 0, - /* 3216 */ 'c', 'l', 'f', 'i', 't', 'n', 'h', 'e', 9, 0, - /* 3226 */ 'c', 'g', 'i', 't', 'n', 'h', 'e', 9, 0, - /* 3235 */ 'c', 'l', 'g', 'i', 't', 'n', 'h', 'e', 9, 0, - /* 3245 */ 'c', 'l', 't', 'n', 'h', 'e', 9, 0, - /* 3253 */ 'c', 'r', 't', 'n', 'h', 'e', 9, 0, - /* 3261 */ 'c', 'g', 'r', 't', 'n', 'h', 'e', 9, 0, - /* 3270 */ 'c', 'l', 'g', 'r', 't', 'n', 'h', 'e', 9, 0, - /* 3280 */ 'c', 'l', 'r', 't', 'n', 'h', 'e', 9, 0, - /* 3289 */ 'l', 'o', 'c', 'r', 'h', 'e', 9, 0, - /* 3297 */ 'l', 'o', 'c', 'g', 'r', 'h', 'e', 9, 0, - /* 3306 */ 'l', 'o', 'c', 'f', 'h', 'r', 'h', 'e', 9, 0, - /* 3316 */ 'c', 'l', 'g', 't', 'h', 'e', 9, 0, - /* 3324 */ 'c', 'i', 't', 'h', 'e', 9, 0, - /* 3331 */ 'c', 'l', 'f', 'i', 't', 'h', 'e', 9, 0, - /* 3340 */ 'c', 'g', 'i', 't', 'h', 'e', 9, 0, - /* 3348 */ 'c', 'l', 'g', 'i', 't', 'h', 'e', 9, 0, - /* 3357 */ 'c', 'l', 't', 'h', 'e', 9, 0, - /* 3364 */ 'c', 'r', 't', 'h', 'e', 9, 0, - /* 3371 */ 'c', 'g', 'r', 't', 'h', 'e', 9, 0, - /* 3379 */ 'c', 'l', 'g', 'r', 't', 'h', 'e', 9, 0, - /* 3388 */ 'c', 'l', 'r', 't', 'h', 'e', 9, 0, - /* 3396 */ 'b', 'i', 'e', 9, 0, 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/* 3561 */ 'c', 'l', 'g', 'r', 'b', 'l', 'e', 9, 0, - /* 3570 */ 'c', 'l', 'r', 'b', 'l', 'e', 9, 0, - /* 3578 */ 'c', 'l', 'c', 'l', 'e', 9, 0, - /* 3585 */ 'l', 'o', 'c', 'l', 'e', 9, 0, - /* 3592 */ 's', 't', 'o', 'c', 'l', 'e', 9, 0, - /* 3600 */ 'm', 'v', 'c', 'l', 'e', 9, 0, - /* 3607 */ 's', 't', 'f', 'l', 'e', 9, 0, - /* 3614 */ 'l', 'o', 'c', 'g', 'l', 'e', 9, 0, - /* 3622 */ 's', 't', 'o', 'c', 'g', 'l', 'e', 9, 0, - /* 3631 */ 'j', 'g', 'l', 'e', 9, 0, - /* 3637 */ 'l', 'o', 'c', 'f', 'h', 'l', 'e', 9, 0, - /* 3646 */ 's', 't', 'o', 'c', 'f', 'h', 'l', 'e', 9, 0, - /* 3656 */ 'b', 'i', 'l', 'e', 9, 0, - /* 3662 */ 'l', 'o', 'c', 'h', 'i', 'l', 'e', 9, 0, - /* 3671 */ 'l', 'o', 'c', 'g', 'h', 'i', 'l', 'e', 9, 0, - /* 3681 */ 'l', 'o', 'c', 'h', 'h', 'i', 'l', 'e', 9, 0, - /* 3691 */ 'c', 'i', 'j', 'l', 'e', 9, 0, - /* 3698 */ 'c', 'g', 'i', 'j', 'l', 'e', 9, 0, - /* 3706 */ 'c', 'l', 'g', 'i', 'j', 'l', 'e', 9, 0, - /* 3715 */ 'c', 'l', 'i', 'j', 'l', 'e', 9, 0, - /* 3723 */ 'c', 'r', 'j', 'l', 'e', 9, 0, - /* 3730 */ 'c', 'g', 'r', 'j', 'l', 'e', 9, 0, - /* 3738 */ 'c', 'l', 'g', 'r', 'j', 'l', 'e', 9, 0, - /* 3747 */ 'c', 'l', 'r', 'j', 'l', 'e', 9, 0, - /* 3755 */ 'v', 'm', 'l', 'e', 9, 0, - /* 3761 */ 'c', 'i', 'b', 'n', 'l', 'e', 9, 0, - /* 3769 */ 'c', 'g', 'i', 'b', 'n', 'l', 'e', 9, 0, - /* 3778 */ 'c', 'l', 'g', 'i', 'b', 'n', 'l', 'e', 9, 0, - /* 3788 */ 'c', 'l', 'i', 'b', 'n', 'l', 'e', 9, 0, - /* 3797 */ 'c', 'r', 'b', 'n', 'l', 'e', 9, 0, - /* 3805 */ 'c', 'g', 'r', 'b', 'n', 'l', 'e', 9, 0, - /* 3814 */ 'c', 'l', 'g', 'r', 'b', 'n', 'l', 'e', 9, 0, - /* 3824 */ 'c', 'l', 'r', 'b', 'n', 'l', 'e', 9, 0, - /* 3833 */ 'l', 'o', 'c', 'n', 'l', 'e', 9, 0, - /* 3841 */ 's', 't', 'o', 'c', 'n', 'l', 'e', 9, 0, - /* 3850 */ 'l', 'o', 'c', 'g', 'n', 'l', 'e', 9, 0, - /* 3859 */ 's', 't', 'o', 'c', 'g', 'n', 'l', 'e', 9, 0, - /* 3869 */ 'j', 'g', 'n', 'l', 'e', 9, 0, - /* 3876 */ 'l', 'o', 'c', 'f', 'h', 'n', 'l', 'e', 9, 0, - /* 3886 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'l', 'e', 9, 0, - /* 3897 */ 'b', 'i', 'n', 'l', 'e', 9, 0, - /* 3904 */ 'l', 'o', 'c', 'h', 'i', 'n', 'l', 'e', 9, 0, - /* 3914 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'l', 'e', 9, 0, - /* 3925 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'l', 'e', 9, 0, - /* 3936 */ 'c', 'i', 'j', 'n', 'l', 'e', 9, 0, - /* 3944 */ 'c', 'g', 'i', 'j', 'n', 'l', 'e', 9, 0, - /* 3953 */ 'c', 'l', 'g', 'i', 'j', 'n', 'l', 'e', 9, 0, - /* 3963 */ 'c', 'l', 'i', 'j', 'n', 'l', 'e', 9, 0, - /* 3972 */ 'c', 'r', 'j', 'n', 'l', 'e', 9, 0, - /* 3980 */ 'c', 'g', 'r', 'j', 'n', 'l', 'e', 9, 0, - /* 3989 */ 'c', 'l', 'g', 'r', 'j', 'n', 'l', 'e', 9, 0, - /* 3999 */ 'c', 'l', 'r', 'j', 'n', 'l', 'e', 9, 0, - /* 4008 */ 'l', 'o', 'c', 'r', 'n', 'l', 'e', 9, 0, - /* 4017 */ 'l', 'o', 'c', 'g', 'r', 'n', 'l', 'e', 9, 0, - /* 4027 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'l', 'e', 9, 0, - /* 4038 */ 'c', 'l', 'g', 't', 'n', 'l', 'e', 9, 0, - /* 4047 */ 'c', 'i', 't', 'n', 'l', 'e', 9, 0, - /* 4055 */ 'c', 'l', 'f', 'i', 't', 'n', 'l', 'e', 9, 0, - /* 4065 */ 'c', 'g', 'i', 't', 'n', 'l', 'e', 9, 0, - /* 4074 */ 'c', 'l', 'g', 'i', 't', 'n', 'l', 'e', 9, 0, - /* 4084 */ 'c', 'l', 't', 'n', 'l', 'e', 9, 0, - /* 4092 */ 'c', 'r', 't', 'n', 'l', 'e', 9, 0, - /* 4100 */ 'c', 'g', 'r', 't', 'n', 'l', 'e', 9, 0, - /* 4109 */ 'c', 'l', 'g', 'r', 't', 'n', 'l', 'e', 9, 0, - /* 4119 */ 'c', 'l', 'r', 't', 'n', 'l', 'e', 9, 0, - /* 4128 */ 'l', 'o', 'c', 'r', 'l', 'e', 9, 0, - /* 4136 */ 'l', 'o', 'c', 'g', 'r', 'l', 'e', 9, 0, - /* 4145 */ 'l', 'o', 'c', 'f', 'h', 'r', 'l', 'e', 9, 0, - /* 4155 */ 'c', 'l', 'g', 't', 'l', 'e', 9, 0, - /* 4163 */ 'c', 'i', 't', 'l', 'e', 9, 0, - /* 4170 */ 'c', 'l', 'f', 'i', 't', 'l', 'e', 9, 0, - /* 4179 */ 'c', 'g', 'i', 't', 'l', 'e', 9, 0, - /* 4187 */ 'c', 'l', 'g', 'i', 't', 'l', 'e', 9, 0, - /* 4196 */ 'c', 'l', 't', 'l', 'e', 9, 0, - /* 4203 */ 'c', 'r', 't', 'l', 'e', 9, 0, - /* 4210 */ 'c', 'g', 'r', 't', 'l', 'e', 9, 0, - /* 4218 */ 'c', 'l', 'g', 'r', 't', 'l', 'e', 9, 0, - /* 4227 */ 'c', 'l', 'r', 't', 'l', 'e', 9, 0, - /* 4235 */ 'b', 'x', 'l', 'e', 9, 0, - /* 4241 */ 'b', 'r', 'x', 'l', 'e', 9, 0, - /* 4248 */ 'v', 'm', 'e', 9, 0, - /* 4253 */ 'c', 'i', 'b', 'n', 'e', 9, 0, - /* 4260 */ 'c', 'g', 'i', 'b', 'n', 'e', 9, 0, - /* 4268 */ 'c', 'l', 'g', 'i', 'b', 'n', 'e', 9, 0, - /* 4277 */ 'c', 'l', 'i', 'b', 'n', 'e', 9, 0, - /* 4285 */ 'c', 'r', 'b', 'n', 'e', 9, 0, - /* 4292 */ 'c', 'g', 'r', 'b', 'n', 'e', 9, 0, - /* 4300 */ 'c', 'l', 'g', 'r', 'b', 'n', 'e', 9, 0, - /* 4309 */ 'c', 'l', 'r', 'b', 'n', 'e', 9, 0, - /* 4317 */ 'l', 'o', 'c', 'n', 'e', 9, 0, - /* 4324 */ 's', 't', 'o', 'c', 'n', 'e', 9, 0, - /* 4332 */ 'v', 'f', 'e', 'n', 'e', 9, 0, - /* 4339 */ 'l', 'o', 'c', 'g', 'n', 'e', 9, 0, - /* 4347 */ 's', 't', 'o', 'c', 'g', 'n', 'e', 9, 0, - /* 4356 */ 'j', 'g', 'n', 'e', 9, 0, - /* 4362 */ 'l', 'o', 'c', 'f', 'h', 'n', 'e', 9, 0, - /* 4371 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'e', 9, 0, - /* 4381 */ 'b', 'i', 'n', 'e', 9, 0, - /* 4387 */ 'l', 'o', 'c', 'h', 'i', 'n', 'e', 9, 0, - /* 4396 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'e', 9, 0, - /* 4406 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'e', 9, 0, - /* 4416 */ 'c', 'i', 'j', 'n', 'e', 9, 0, - /* 4423 */ 'c', 'g', 'i', 'j', 'n', 'e', 9, 0, - /* 4431 */ 'c', 'l', 'g', 'i', 'j', 'n', 'e', 9, 0, - /* 4440 */ 'c', 'l', 'i', 'j', 'n', 'e', 9, 0, - /* 4448 */ 'c', 'r', 'j', 'n', 'e', 9, 0, - /* 4455 */ 'c', 'g', 'r', 'j', 'n', 'e', 9, 0, - /* 4463 */ 'c', 'l', 'g', 'r', 'j', 'n', 'e', 9, 0, - /* 4472 */ 'c', 'l', 'r', 'j', 'n', 'e', 9, 0, - /* 4480 */ 'v', 'o', 'n', 'e', 9, 0, - /* 4486 */ 'l', 'o', 'c', 'r', 'n', 'e', 9, 0, - /* 4494 */ 'l', 'o', 'c', 'g', 'r', 'n', 'e', 9, 0, - /* 4503 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'e', 9, 0, - /* 4513 */ 'c', 'l', 'g', 't', 'n', 'e', 9, 0, - /* 4521 */ 'c', 'i', 't', 'n', 'e', 9, 0, - /* 4528 */ 'c', 'l', 'f', 'i', 't', 'n', 'e', 9, 0, - /* 4537 */ 'c', 'g', 'i', 't', 'n', 'e', 9, 0, - /* 4545 */ 'c', 'l', 'g', 'i', 't', 'n', 'e', 9, 0, - /* 4554 */ 'c', 'l', 't', 'n', 'e', 9, 0, - /* 4561 */ 'c', 'r', 't', 'n', 'e', 9, 0, - /* 4568 */ 'c', 'g', 'r', 't', 'n', 'e', 9, 0, - /* 4576 */ 'c', 'l', 'g', 'r', 't', 'n', 'e', 9, 0, - /* 4585 */ 'c', 'l', 'r', 't', 'n', 'e', 9, 0, - /* 4593 */ 's', 'q', 'e', 9, 0, - /* 4598 */ 'l', 'o', 'c', 'r', 'e', 9, 0, - /* 4605 */ 'l', 'o', 'c', 'g', 'r', 'e', 9, 0, - /* 4613 */ 'l', 'o', 'c', 'f', 'h', 'r', 'e', 9, 0, - /* 4622 */ 't', 'r', 't', 'r', 'e', 9, 0, - /* 4629 */ 'm', 's', 'e', 9, 0, - /* 4634 */ 'c', 'u', 's', 'e', 9, 0, - /* 4640 */ 'i', 'd', 't', 'e', 9, 0, - /* 4646 */ 'c', 'r', 'd', 't', 'e', 9, 0, - /* 4653 */ 'c', 'l', 'g', 't', 'e', 9, 0, - /* 4660 */ 'c', 'i', 't', 'e', 9, 0, - /* 4666 */ 'c', 'l', 'f', 'i', 't', 'e', 9, 0, - /* 4674 */ 'c', 'g', 'i', 't', 'e', 9, 0, - /* 4681 */ 'c', 'l', 'g', 'i', 't', 'e', 9, 0, - /* 4689 */ 'c', 'l', 't', 'e', 9, 0, - /* 4695 */ 'i', 'p', 't', 'e', 9, 0, - /* 4701 */ 'c', 'r', 't', 'e', 9, 0, - /* 4707 */ 'c', 'g', 'r', 't', 'e', 9, 0, - /* 4714 */ 'c', 'l', 'g', 'r', 't', 'e', 9, 0, - /* 4722 */ 'c', 'l', 'r', 't', 'e', 9, 0, - /* 4729 */ 't', 'r', 't', 'e', 9, 0, - /* 4735 */ 's', 't', 'e', 9, 0, - /* 4740 */ 'l', 'p', 's', 'w', 'e', 9, 0, - /* 4747 */ 'l', 'x', 'e', 9, 0, - /* 4752 */ 'v', 'g', 'f', 'm', 'a', 'f', 9, 0, - /* 4760 */ 'v', 'e', 's', 'r', 'a', 'f', 9, 0, - /* 4768 */ 'v', 'a', 'f', 9, 0, - /* 4773 */ 's', 'a', 'c', 'f', 9, 0, - /* 4779 */ 'v', 'a', 'c', 'c', 'f', 9, 0, - /* 4786 */ 'v', 'e', 'c', 'f', 9, 0, - /* 4792 */ 'v', 'l', 'c', 'f', 9, 0, - /* 4798 */ 'v', 's', 't', 'r', 'c', 'f', 9, 0, - /* 4806 */ 'v', 'f', 'a', 'e', 'f', 9, 0, - /* 4813 */ 'v', 'm', 'a', 'e', 'f', 9, 0, - /* 4820 */ 'v', 's', 'c', 'e', 'f', 9, 0, - /* 4827 */ 'v', 'f', 'e', 'e', 'f', 9, 0, - /* 4834 */ 'v', 'g', 'e', 'f', 9, 0, - /* 4840 */ 'v', 'm', 'a', 'l', 'e', 'f', 9, 0, - /* 4848 */ 'v', 'm', 'l', 'e', 'f', 9, 0, - /* 4855 */ 'v', 'l', 'e', 'f', 9, 0, - /* 4861 */ 'v', 'm', 'e', 'f', 9, 0, - /* 4867 */ 'v', 'f', 'e', 'n', 'e', 'f', 9, 0, - /* 4875 */ 'v', 's', 't', 'e', 'f', 9, 0, - /* 4882 */ 'a', 'g', 'f', 9, 0, - /* 4887 */ 'c', 'g', 'f', 9, 0, - /* 4892 */ 'v', 's', 'e', 'g', 'f', 9, 0, - /* 4899 */ 'a', 'l', 'g', 'f', 9, 0, - /* 4905 */ 'c', 'l', 'g', 'f', 9, 0, - /* 4911 */ 'l', 'l', 'g', 'f', 9, 0, - /* 4917 */ 's', 'l', 'g', 'f', 9, 0, - /* 4923 */ 'v', 's', 'u', 'm', 'g', 'f', 9, 0, - /* 4931 */ 'l', 'l', 'z', 'r', 'g', 'f', 9, 0, - /* 4939 */ 'd', 's', 'g', 'f', 9, 0, - /* 4945 */ 'm', 's', 'g', 'f', 9, 0, - /* 4951 */ 'l', 't', 'g', 'f', 9, 0, - /* 4957 */ 'v', 'a', 'v', 'g', 'f', 9, 0, - /* 4964 */ 'v', 'l', 'v', 'g', 'f', 9, 0, - /* 4971 */ 'v', 'm', 'a', 'h', 'f', 9, 0, - /* 4978 */ 'v', 'c', 'h', 'f', 9, 0, - /* 4984 */ 'i', 'i', 'h', 'f', 9, 0, - /* 4990 */ 'l', 'l', 'i', 'h', 'f', 9, 0, - /* 4997 */ 'n', 'i', 'h', 'f', 9, 0, - /* 5003 */ 'o', 'i', 'h', 'f', 9, 0, - /* 5009 */ 'x', 'i', 'h', 'f', 9, 0, - /* 5015 */ 'v', 'm', 'a', 'l', 'h', 'f', 9, 0, - /* 5023 */ 'c', 'l', 'h', 'f', 9, 0, - /* 5029 */ 'v', 'm', 'l', 'h', 'f', 9, 0, - /* 5036 */ 'v', 'u', 'p', 'l', 'h', 'f', 9, 0, - /* 5044 */ 'v', 'm', 'h', 'f', 9, 0, - /* 5050 */ 'v', 'u', 'p', 'h', 'f', 9, 0, - /* 5057 */ 'v', 'm', 'r', 'h', 'f', 9, 0, - /* 5064 */ 'v', 's', 'c', 'b', 'i', 'f', 9, 0, - /* 5072 */ 'v', 'l', 'e', 'i', 'f', 9, 0, - /* 5079 */ 'v', 'r', 'e', 'p', 'i', 'f', 9, 0, - /* 5087 */ 's', 't', 'c', 'k', 'f', 9, 0, - /* 5094 */ 'v', 'p', 'k', 'f', 9, 0, - /* 5100 */ 'v', 'm', 'a', 'l', 'f', 9, 0, - /* 5107 */ 'v', 'e', 'c', 'l', 'f', 9, 0, - /* 5114 */ 'v', 'a', 'v', 'g', 'l', 'f', 9, 0, - /* 5122 */ 'v', 'c', 'h', 'l', 'f', 9, 0, - /* 5129 */ 'i', 'i', 'l', 'f', 9, 0, - /* 5135 */ 'l', 'l', 'i', 'l', 'f', 9, 0, - /* 5142 */ 'n', 'i', 'l', 'f', 9, 0, - /* 5148 */ 'o', 'i', 'l', 'f', 9, 0, - /* 5154 */ 'x', 'i', 'l', 'f', 9, 0, - /* 5160 */ 'v', 'u', 'p', 'l', 'l', 'f', 9, 0, - /* 5168 */ 'v', 'e', 'r', 'l', 'l', 'f', 9, 0, - /* 5176 */ 'v', 'm', 'l', 'f', 9, 0, - /* 5182 */ 'v', 'm', 'n', 'l', 'f', 9, 0, - /* 5189 */ 'v', 'u', 'p', 'l', 'f', 9, 0, - /* 5196 */ 'v', 'm', 'r', 'l', 'f', 9, 0, - /* 5203 */ 'v', 'e', 's', 'r', 'l', 'f', 9, 0, - /* 5211 */ 'v', 'e', 's', 'l', 'f', 9, 0, - /* 5218 */ 'v', 'm', 'x', 'l', 'f', 9, 0, - /* 5225 */ 'v', 'l', 'l', 'e', 'z', 'l', 'f', 9, 0, - /* 5234 */ 'v', 'g', 'f', 'm', 'f', 9, 0, - /* 5241 */ 'p', 'f', 'm', 'f', 9, 0, - /* 5247 */ 'v', 'g', 'm', 'f', 9, 0, - /* 5253 */ 'v', 'e', 'r', 'i', 'm', 'f', 9, 0, - /* 5261 */ 'k', 'm', 'f', 9, 0, - /* 5266 */ 'v', 'm', 'n', 'f', 9, 0, - /* 5272 */ 'v', 'm', 'a', 'o', 'f', 9, 0, - /* 5279 */ 'v', 'm', 'a', 'l', 'o', 'f', 9, 0, - /* 5287 */ 'v', 'm', 'l', 'o', 'f', 9, 0, - /* 5294 */ 'v', 'm', 'o', 'f', 9, 0, - /* 5300 */ 'v', 'l', 'r', 'e', 'p', 'f', 9, 0, - /* 5308 */ 'v', 'r', 'e', 'p', 'f', 9, 0, - /* 5315 */ 'v', 'l', 'p', 'f', 9, 0, - /* 5321 */ 'v', 'c', 'e', 'q', 'f', 9, 0, - /* 5328 */ 'v', 's', 'u', 'm', 'q', 'f', 9, 0, - /* 5336 */ 'v', 'i', 's', 't', 'r', 'f', 9, 0, - /* 5344 */ 'l', 'z', 'r', 'f', 9, 0, - /* 5350 */ 'v', 'p', 'k', 's', 'f', 9, 0, - /* 5357 */ 'v', 'p', 'k', 'l', 's', 'f', 9, 0, - /* 5365 */ 'v', 's', 'f', 9, 0, - /* 5370 */ 'v', 'p', 'o', 'p', 'c', 't', 'f', 9, 0, - /* 5379 */ 'p', 't', 'f', 9, 0, - /* 5384 */ 'c', 'u', 'u', 't', 'f', 9, 0, - /* 5391 */ 'v', 'e', 's', 'r', 'a', 'v', 'f', 9, 0, - /* 5400 */ 'v', 'l', 'g', 'v', 'f', 9, 0, - /* 5407 */ 'v', 'e', 'r', 'l', 'l', 'v', 'f', 9, 0, - /* 5416 */ 'v', 'e', 's', 'r', 'l', 'v', 'f', 9, 0, - /* 5425 */ 'v', 'e', 's', 'l', 'v', 'f', 9, 0, - /* 5433 */ 'v', 'm', 'x', 'f', 9, 0, - /* 5439 */ 'v', 's', 't', 'r', 'c', 'z', 'f', 9, 0, - /* 5448 */ 'v', 'f', 'a', 'e', 'z', 'f', 9, 0, - /* 5456 */ 'v', 'f', 'e', 'e', 'z', 'f', 9, 0, - /* 5464 */ 'v', 'l', 'l', 'e', 'z', 'f', 9, 0, - /* 5472 */ 'v', 'f', 'e', 'n', 'e', 'z', 'f', 9, 0, - /* 5481 */ 'v', 'c', 'l', 'z', 'f', 9, 0, - /* 5488 */ 'v', 'c', 't', 'z', 'f', 9, 0, - /* 5495 */ 'l', 'a', 'a', 'g', 9, 0, - /* 5501 */ 'e', 'c', 'a', 'g', 9, 0, - /* 5507 */ 'd', 'i', 'a', 'g', 9, 0, - /* 5513 */ 's', 'l', 'a', 'g', 9, 0, - /* 5519 */ 'v', 'g', 'f', 'm', 'a', 'g', 9, 0, - /* 5527 */ 'l', 'r', 'a', 'g', 9, 0, - /* 5533 */ 'v', 'e', 's', 'r', 'a', 'g', 9, 0, - /* 5541 */ 's', 't', 'r', 'a', 'g', 9, 0, - /* 5548 */ 'l', 'u', 'r', 'a', 'g', 9, 0, - /* 5555 */ 'v', 'a', 'g', 9, 0, - /* 5560 */ 's', 'l', 'b', 'g', 9, 0, - /* 5566 */ 'r', 'i', 's', 'b', 'g', 9, 0, - /* 5573 */ 'r', 'n', 's', 'b', 'g', 9, 0, - /* 5580 */ 'r', 'o', 's', 'b', 'g', 9, 0, - /* 5587 */ 'r', 'x', 's', 'b', 'g', 9, 0, - /* 5594 */ 'v', 'c', 'v', 'b', 'g', 9, 0, - /* 5601 */ 't', 'r', 'a', 'c', 'g', 9, 0, - /* 5608 */ 'v', 'a', 'c', 'c', 'g', 9, 0, - /* 5615 */ 'v', 'e', 'c', 'g', 9, 0, - /* 5621 */ 'a', 'l', 'c', 'g', 9, 0, - /* 5627 */ 'v', 'l', 'c', 'g', 9, 0, - /* 5633 */ 'l', 'o', 'c', 'g', 9, 0, - /* 5639 */ 's', 't', 'o', 'c', 'g', 9, 0, - /* 5646 */ 'v', 'c', 'd', 'g', 9, 0, - /* 5652 */ 'l', 'p', 'd', 'g', 9, 0, - /* 5658 */ 'v', 'c', 'v', 'd', 'g', 9, 0, - /* 5665 */ 'v', 's', 'c', 'e', 'g', 9, 0, - /* 5672 */ 'v', 'g', 'e', 'g', 9, 0, - /* 5678 */ 'v', 'l', 'e', 'g', 9, 0, - /* 5684 */ 'b', 'x', 'l', 'e', 'g', 9, 0, - /* 5691 */ 'e', 'r', 'e', 'g', 9, 0, - /* 5697 */ 'v', 's', 'e', 'g', 9, 0, - /* 5703 */ 'v', 's', 't', 'e', 'g', 9, 0, - /* 5710 */ 'e', 'r', 'e', 'g', 'g', 9, 0, - /* 5717 */ 'l', 'g', 'g', 9, 0, - /* 5722 */ 'v', 'a', 'v', 'g', 'g', 9, 0, - /* 5729 */ 'v', 'l', 'v', 'g', 'g', 9, 0, - /* 5736 */ 'r', 'i', 's', 'b', 'h', 'g', 9, 0, - /* 5744 */ 'v', 'c', 'h', 'g', 9, 0, - /* 5750 */ 'v', 'm', 'r', 'h', 'g', 9, 0, - /* 5757 */ 'b', 'x', 'h', 'g', 9, 0, - /* 5763 */ 'b', 'r', 'x', 'h', 'g', 9, 0, - /* 5770 */ 'v', 's', 'c', 'b', 'i', 'g', 9, 0, - /* 5778 */ 'v', 'l', 'e', 'i', 'g', 9, 0, - /* 5785 */ 'v', 'r', 'e', 'p', 'i', 'g', 9, 0, - /* 5793 */ 'j', 'g', 9, 0, - /* 5797 */ 'v', 'p', 'k', 'g', 9, 0, - /* 5803 */ 'l', 'a', 'a', 'l', 'g', 9, 0, - /* 5810 */ 'r', 'i', 's', 'b', 'l', 'g', 9, 0, - /* 5818 */ 'v', 'e', 'c', 'l', 'g', 9, 0, - /* 5825 */ 'v', 'c', 'd', 'l', 'g', 9, 0, - /* 5832 */ 'v', 'a', 'v', 'g', 'l', 'g', 9, 0, - /* 5840 */ 'v', 'c', 'h', 'l', 'g', 9, 0, - /* 5847 */ 'v', 'e', 'r', 'l', 'l', 'g', 9, 0, - /* 5855 */ 's', 'l', 'l', 'g', 9, 0, - /* 5861 */ 'm', 'l', 'g', 9, 0, - /* 5866 */ 'v', 'm', 'n', 'l', 'g', 9, 0, - /* 5873 */ 'v', 'm', 'r', 'l', 'g', 9, 0, - /* 5880 */ 'v', 'e', 's', 'r', 'l', 'g', 9, 0, - /* 5888 */ 'v', 'e', 's', 'l', 'g', 9, 0, - /* 5895 */ 'v', 'm', 's', 'l', 'g', 9, 0, - /* 5902 */ 'l', 'c', 't', 'l', 'g', 9, 0, - /* 5909 */ 'v', 'm', 'x', 'l', 'g', 9, 0, - /* 5916 */ 'b', 'r', 'x', 'l', 'g', 9, 0, - /* 5923 */ 'v', 'g', 'f', 'm', 'g', 9, 0, - /* 5930 */ 'v', 'g', 'm', 'g', 9, 0, - /* 5936 */ 'v', 'e', 'r', 'i', 'm', 'g', 9, 0, - /* 5944 */ 'l', 'm', 'g', 9, 0, - /* 5949 */ 's', 't', 'm', 'g', 9, 0, - /* 5955 */ 'v', 's', 'u', 'm', 'g', 9, 0, - /* 5962 */ 'l', 'a', 'n', 'g', 9, 0, - /* 5968 */ 'v', 'm', 'n', 'g', 9, 0, - /* 5974 */ 'l', 'a', 'o', 'g', 9, 0, - /* 5980 */ 'v', 'l', 'r', 'e', 'p', 'g', 9, 0, - /* 5988 */ 'v', 'r', 'e', 'p', 'g', 9, 0, - /* 5995 */ 'v', 'l', 'p', 'g', 9, 0, - /* 6001 */ 'c', 's', 'p', 'g', 9, 0, - /* 6007 */ 'm', 'v', 'p', 'g', 9, 0, - /* 6013 */ 'v', 'c', 'e', 'q', 'g', 9, 0, - /* 6020 */ 'v', 's', 'u', 'm', 'q', 'g', 9, 0, - /* 6028 */ 's', 't', 'u', 'r', 'g', 9, 0, - /* 6035 */ 'l', 'z', 'r', 'g', 9, 0, - /* 6041 */ 'b', 's', 'g', 9, 0, - /* 6046 */ 'c', 's', 'g', 9, 0, - /* 6051 */ 'c', 'd', 's', 'g', 9, 0, - /* 6057 */ 'l', 'l', 'g', 'f', 's', 'g', 9, 0, - /* 6065 */ 'v', 'p', 'k', 's', 'g', 9, 0, - /* 6072 */ 'v', 'p', 'k', 'l', 's', 'g', 9, 0, - /* 6080 */ 'm', 's', 'g', 9, 0, - /* 6085 */ 'v', 's', 'g', 9, 0, - /* 6090 */ 'b', 'c', 't', 'g', 9, 0, - /* 6096 */ 'e', 'c', 't', 'g', 9, 0, - /* 6102 */ 'v', 'p', 'o', 'p', 'c', 't', 'g', 9, 0, - /* 6111 */ 'b', 'r', 'c', 't', 'g', 9, 0, - /* 6118 */ 's', 't', 'c', 't', 'g', 9, 0, - /* 6125 */ 'l', 't', 'g', 9, 0, - /* 6130 */ 'n', 't', 's', 't', 'g', 9, 0, - /* 6137 */ 'v', 'e', 's', 'r', 'a', 'v', 'g', 9, 0, - /* 6146 */ 'v', 'a', 'v', 'g', 9, 0, - /* 6152 */ 'v', 'l', 'g', 'v', 'g', 9, 0, - /* 6159 */ 'v', 'e', 'r', 'l', 'l', 'v', 'g', 9, 0, - /* 6168 */ 'v', 'e', 's', 'r', 'l', 'v', 'g', 9, 0, - /* 6177 */ 'v', 'e', 's', 'l', 'v', 'g', 9, 0, - /* 6185 */ 'v', 'l', 'v', 'g', 9, 0, - /* 6191 */ 'l', 'r', 'v', 'g', 9, 0, - /* 6197 */ 's', 't', 'r', 'v', 'g', 9, 0, - /* 6204 */ 'l', 'a', 'x', 'g', 9, 0, - /* 6210 */ 'v', 'm', 'x', 'g', 9, 0, - /* 6216 */ 'v', 'l', 'l', 'e', 'z', 'g', 9, 0, - /* 6224 */ 'v', 'c', 'l', 'z', 'g', 9, 0, - /* 6231 */ 'v', 'c', 't', 'z', 'g', 9, 0, - /* 6238 */ 'v', 'g', 'f', 'm', 'a', 'h', 9, 0, - /* 6246 */ 'v', 'm', 'a', 'h', 9, 0, - /* 6252 */ 'v', 'e', 's', 'r', 'a', 'h', 9, 0, - /* 6260 */ 'v', 'a', 'h', 9, 0, - /* 6265 */ 'c', 'i', 'b', 'h', 9, 0, - /* 6271 */ 'c', 'g', 'i', 'b', 'h', 9, 0, - /* 6278 */ 'c', 'l', 'g', 'i', 'b', 'h', 9, 0, - /* 6286 */ 'c', 'l', 'i', 'b', 'h', 9, 0, - /* 6293 */ 'l', 'b', 'h', 9, 0, - /* 6298 */ 'c', 'r', 'b', 'h', 9, 0, - /* 6304 */ 'c', 'g', 'r', 'b', 'h', 9, 0, - /* 6311 */ 'c', 'l', 'g', 'r', 'b', 'h', 9, 0, - /* 6319 */ 'c', 'l', 'r', 'b', 'h', 9, 0, - /* 6326 */ 'v', 'a', 'c', 'c', 'h', 9, 0, - /* 6333 */ 'v', 'e', 'c', 'h', 9, 0, - /* 6339 */ 'v', 'f', 'c', 'h', 9, 0, - /* 6345 */ 'l', 'l', 'c', 'h', 9, 0, - /* 6351 */ 'v', 'l', 'c', 'h', 9, 0, - /* 6357 */ 'l', 'o', 'c', 'h', 9, 0, - /* 6363 */ 's', 't', 'o', 'c', 'h', 9, 0, - /* 6370 */ 'v', 's', 't', 'r', 'c', 'h', 9, 0, - /* 6378 */ 'm', 's', 'c', 'h', 9, 0, - /* 6384 */ 's', 's', 'c', 'h', 9, 0, - /* 6390 */ 's', 't', 's', 'c', 'h', 9, 0, - /* 6397 */ 's', 't', 'c', 'h', 9, 0, - /* 6403 */ 'v', 'c', 'h', 9, 0, - /* 6408 */ 'v', 'f', 'a', 'e', 'h', 9, 0, - /* 6415 */ 'v', 'm', 'a', 'e', 'h', 9, 0, - /* 6422 */ 'v', 'f', 'e', 'e', 'h', 9, 0, - /* 6429 */ 'v', 'm', 'a', 'l', 'e', 'h', 9, 0, - /* 6437 */ 'v', 'm', 'l', 'e', 'h', 9, 0, - /* 6444 */ 'v', 'l', 'e', 'h', 9, 0, - /* 6450 */ 'v', 'm', 'e', 'h', 9, 0, - /* 6456 */ 'v', 'f', 'e', 'n', 'e', 'h', 9, 0, - /* 6464 */ 'v', 's', 't', 'e', 'h', 9, 0, - /* 6471 */ 'l', 'o', 'c', 'f', 'h', 9, 0, - /* 6478 */ 's', 't', 'o', 'c', 'f', 'h', 9, 0, - /* 6486 */ 'l', 'f', 'h', 9, 0, - /* 6491 */ 's', 't', 'f', 'h', 9, 0, - /* 6497 */ 'a', 'g', 'h', 9, 0, - /* 6502 */ 'l', 'o', 'c', 'g', 'h', 9, 0, - /* 6509 */ 's', 't', 'o', 'c', 'g', 'h', 9, 0, - /* 6517 */ 'v', 's', 'e', 'g', 'h', 9, 0, - /* 6524 */ 'j', 'g', 'h', 9, 0, - /* 6529 */ 'l', 'l', 'g', 'h', 9, 0, - /* 6535 */ 'v', 's', 'u', 'm', 'g', 'h', 9, 0, - /* 6543 */ 's', 'g', 'h', 9, 0, - /* 6548 */ 'v', 'a', 'v', 'g', 'h', 9, 0, - /* 6555 */ 'v', 'l', 'v', 'g', 'h', 9, 0, - /* 6562 */ 'v', 'm', 'a', 'h', 'h', 9, 0, - /* 6569 */ 'v', 'c', 'h', 'h', 9, 0, - /* 6575 */ 'l', 'o', 'c', 'f', 'h', 'h', 9, 0, - /* 6583 */ 's', 't', 'o', 'c', 'f', 'h', 'h', 9, 0, - /* 6592 */ 'i', 'i', 'h', 'h', 9, 0, - /* 6598 */ 'l', 'l', 'i', 'h', 'h', 9, 0, - /* 6605 */ 'n', 'i', 'h', 'h', 9, 0, - /* 6611 */ 'o', 'i', 'h', 'h', 9, 0, - /* 6617 */ 'v', 'm', 'a', 'l', 'h', 'h', 9, 0, - /* 6625 */ 'l', 'l', 'h', 'h', 9, 0, - /* 6631 */ 'v', 'm', 'l', 'h', 'h', 9, 0, - /* 6638 */ 'v', 'u', 'p', 'l', 'h', 'h', 9, 0, - /* 6646 */ 't', 'm', 'h', 'h', 9, 0, - /* 6652 */ 'v', 'm', 'h', 'h', 9, 0, - /* 6658 */ 'v', 'u', 'p', 'h', 'h', 9, 0, - /* 6665 */ 'v', 'm', 'r', 'h', 'h', 9, 0, - /* 6672 */ 's', 't', 'h', 'h', 9, 0, - /* 6678 */ 'a', 'i', 'h', 9, 0, - /* 6683 */ 'v', 's', 'c', 'b', 'i', 'h', 9, 0, - /* 6691 */ 'c', 'i', 'h', 9, 0, - /* 6696 */ 'v', 'l', 'e', 'i', 'h', 9, 0, - /* 6703 */ 'l', 'o', 'c', 'h', 'i', 'h', 9, 0, - /* 6711 */ 'l', 'o', 'c', 'g', 'h', 'i', 'h', 9, 0, - /* 6720 */ 'l', 'o', 'c', 'h', 'h', 'i', 'h', 9, 0, - /* 6729 */ 'c', 'l', 'i', 'h', 9, 0, - /* 6735 */ 'v', 'r', 'e', 'p', 'i', 'h', 9, 0, - /* 6743 */ 'a', 'l', 's', 'i', 'h', 9, 0, - /* 6750 */ 'c', 'i', 'j', 'h', 9, 0, - /* 6756 */ 'c', 'g', 'i', 'j', 'h', 9, 0, - /* 6763 */ 'c', 'l', 'g', 'i', 'j', 'h', 9, 0, - /* 6771 */ 'c', 'l', 'i', 'j', 'h', 9, 0, - /* 6778 */ 'c', 'r', 'j', 'h', 9, 0, - /* 6784 */ 'c', 'g', 'r', 'j', 'h', 9, 0, - /* 6791 */ 'c', 'l', 'g', 'r', 'j', 'h', 9, 0, - /* 6799 */ 'c', 'l', 'r', 'j', 'h', 9, 0, - /* 6806 */ 'v', 'p', 'k', 'h', 9, 0, - /* 6812 */ 'v', 'm', 'a', 'l', 'h', 9, 0, - /* 6819 */ 'c', 'i', 'b', 'l', 'h', 9, 0, - /* 6826 */ 'c', 'g', 'i', 'b', 'l', 'h', 9, 0, - /* 6834 */ 'c', 'l', 'g', 'i', 'b', 'l', 'h', 9, 0, - /* 6843 */ 'c', 'l', 'i', 'b', 'l', 'h', 9, 0, - /* 6851 */ 'c', 'r', 'b', 'l', 'h', 9, 0, - /* 6858 */ 'c', 'g', 'r', 'b', 'l', 'h', 9, 0, - /* 6866 */ 'c', 'l', 'g', 'r', 'b', 'l', 'h', 9, 0, - /* 6875 */ 'c', 'l', 'r', 'b', 'l', 'h', 9, 0, - /* 6883 */ 'v', 'e', 'c', 'l', 'h', 9, 0, - /* 6890 */ 'l', 'o', 'c', 'l', 'h', 9, 0, - /* 6897 */ 's', 't', 'o', 'c', 'l', 'h', 9, 0, - /* 6905 */ 'l', 'o', 'c', 'g', 'l', 'h', 9, 0, - /* 6913 */ 's', 't', 'o', 'c', 'g', 'l', 'h', 9, 0, - /* 6922 */ 'j', 'g', 'l', 'h', 9, 0, - /* 6928 */ 'v', 'a', 'v', 'g', 'l', 'h', 9, 0, - /* 6936 */ 'v', 'c', 'h', 'l', 'h', 9, 0, - /* 6943 */ 'l', 'o', 'c', 'f', 'h', 'l', 'h', 9, 0, - /* 6952 */ 's', 't', 'o', 'c', 'f', 'h', 'l', 'h', 9, 0, - /* 6962 */ 'b', 'i', 'l', 'h', 9, 0, - /* 6968 */ 'l', 'o', 'c', 'h', 'i', 'l', 'h', 9, 0, - /* 6977 */ 'l', 'o', 'c', 'g', 'h', 'i', 'l', 'h', 9, 0, - /* 6987 */ 'l', 'o', 'c', 'h', 'h', 'i', 'l', 'h', 9, 0, - /* 6997 */ 'i', 'i', 'l', 'h', 9, 0, - /* 7003 */ 'l', 'l', 'i', 'l', 'h', 9, 0, - /* 7010 */ 'n', 'i', 'l', 'h', 9, 0, - /* 7016 */ 'o', 'i', 'l', 'h', 9, 0, - /* 7022 */ 'c', 'i', 'j', 'l', 'h', 9, 0, - /* 7029 */ 'c', 'g', 'i', 'j', 'l', 'h', 9, 0, - /* 7037 */ 'c', 'l', 'g', 'i', 'j', 'l', 'h', 9, 0, - /* 7046 */ 'c', 'l', 'i', 'j', 'l', 'h', 9, 0, - /* 7054 */ 'c', 'r', 'j', 'l', 'h', 9, 0, - /* 7061 */ 'c', 'g', 'r', 'j', 'l', 'h', 9, 0, - /* 7069 */ 'c', 'l', 'g', 'r', 'j', 'l', 'h', 9, 0, - /* 7078 */ 'c', 'l', 'r', 'j', 'l', 'h', 9, 0, - /* 7086 */ 'v', 'u', 'p', 'l', 'l', 'h', 9, 0, - /* 7094 */ 'v', 'e', 'r', 'l', 'l', 'h', 9, 0, - /* 7102 */ 't', 'm', 'l', 'h', 9, 0, - /* 7108 */ 'v', 'm', 'l', 'h', 9, 0, - /* 7114 */ 'c', 'i', 'b', 'n', 'l', 'h', 9, 0, - /* 7122 */ 'c', 'g', 'i', 'b', 'n', 'l', 'h', 9, 0, - /* 7131 */ 'c', 'l', 'g', 'i', 'b', 'n', 'l', 'h', 9, 0, - /* 7141 */ 'c', 'l', 'i', 'b', 'n', 'l', 'h', 9, 0, - /* 7150 */ 'c', 'r', 'b', 'n', 'l', 'h', 9, 0, - /* 7158 */ 'c', 'g', 'r', 'b', 'n', 'l', 'h', 9, 0, - /* 7167 */ 'c', 'l', 'g', 'r', 'b', 'n', 'l', 'h', 9, 0, - /* 7177 */ 'c', 'l', 'r', 'b', 'n', 'l', 'h', 9, 0, - /* 7186 */ 'l', 'o', 'c', 'n', 'l', 'h', 9, 0, - /* 7194 */ 's', 't', 'o', 'c', 'n', 'l', 'h', 9, 0, - /* 7203 */ 'l', 'o', 'c', 'g', 'n', 'l', 'h', 9, 0, - /* 7212 */ 's', 't', 'o', 'c', 'g', 'n', 'l', 'h', 9, 0, - /* 7222 */ 'j', 'g', 'n', 'l', 'h', 9, 0, - /* 7229 */ 'l', 'o', 'c', 'f', 'h', 'n', 'l', 'h', 9, 0, - /* 7239 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'l', 'h', 9, 0, - /* 7250 */ 'b', 'i', 'n', 'l', 'h', 9, 0, - /* 7257 */ 'l', 'o', 'c', 'h', 'i', 'n', 'l', 'h', 9, 0, - /* 7267 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'l', 'h', 9, 0, - /* 7278 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'l', 'h', 9, 0, - /* 7289 */ 'c', 'i', 'j', 'n', 'l', 'h', 9, 0, - /* 7297 */ 'c', 'g', 'i', 'j', 'n', 'l', 'h', 9, 0, - /* 7306 */ 'c', 'l', 'g', 'i', 'j', 'n', 'l', 'h', 9, 0, - /* 7316 */ 'c', 'l', 'i', 'j', 'n', 'l', 'h', 9, 0, - /* 7325 */ 'c', 'r', 'j', 'n', 'l', 'h', 9, 0, - /* 7333 */ 'c', 'g', 'r', 'j', 'n', 'l', 'h', 9, 0, - /* 7342 */ 'c', 'l', 'g', 'r', 'j', 'n', 'l', 'h', 9, 0, - /* 7352 */ 'c', 'l', 'r', 'j', 'n', 'l', 'h', 9, 0, - /* 7361 */ 'v', 'm', 'n', 'l', 'h', 9, 0, - /* 7368 */ 'l', 'o', 'c', 'r', 'n', 'l', 'h', 9, 0, - /* 7377 */ 'l', 'o', 'c', 'g', 'r', 'n', 'l', 'h', 9, 0, - /* 7387 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'l', 'h', 9, 0, - /* 7398 */ 'c', 'l', 'g', 't', 'n', 'l', 'h', 9, 0, - /* 7407 */ 'c', 'i', 't', 'n', 'l', 'h', 9, 0, - /* 7415 */ 'c', 'l', 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0, - /* 7745 */ 'c', 'l', 'r', 'b', 'n', 'h', 9, 0, - /* 7753 */ 'l', 'o', 'c', 'n', 'h', 9, 0, - /* 7760 */ 's', 't', 'o', 'c', 'n', 'h', 9, 0, - /* 7768 */ 'l', 'o', 'c', 'g', 'n', 'h', 9, 0, - /* 7776 */ 's', 't', 'o', 'c', 'g', 'n', 'h', 9, 0, - /* 7785 */ 'j', 'g', 'n', 'h', 9, 0, - /* 7791 */ 'l', 'o', 'c', 'f', 'h', 'n', 'h', 9, 0, - /* 7800 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'h', 9, 0, - /* 7810 */ 'b', 'i', 'n', 'h', 9, 0, - /* 7816 */ 'l', 'o', 'c', 'h', 'i', 'n', 'h', 9, 0, - /* 7825 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'h', 9, 0, - /* 7835 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'h', 9, 0, - /* 7845 */ 'c', 'i', 'j', 'n', 'h', 9, 0, - /* 7852 */ 'c', 'g', 'i', 'j', 'n', 'h', 9, 0, - /* 7860 */ 'c', 'l', 'g', 'i', 'j', 'n', 'h', 9, 0, - /* 7869 */ 'c', 'l', 'i', 'j', 'n', 'h', 9, 0, - /* 7877 */ 'c', 'r', 'j', 'n', 'h', 9, 0, - /* 7884 */ 'c', 'g', 'r', 'j', 'n', 'h', 9, 0, - /* 7892 */ 'c', 'l', 'g', 'r', 'j', 'n', 'h', 9, 0, - /* 7901 */ 'c', 'l', 'r', 'j', 'n', 'h', 9, 0, - /* 7909 */ 'v', 'm', 'n', 'h', 9, 0, - /* 7915 */ 'l', 'o', 'c', 'r', 'n', 'h', 9, 0, - /* 7923 */ 'l', 'o', 'c', 'g', 'r', 'n', 'h', 9, 0, - /* 7932 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'h', 9, 0, - /* 7942 */ 'c', 'l', 'g', 't', 'n', 'h', 9, 0, - /* 7950 */ 'c', 'i', 't', 'n', 'h', 9, 0, - /* 7957 */ 'c', 'l', 'f', 'i', 't', 'n', 'h', 9, 0, - /* 7966 */ 'c', 'g', 'i', 't', 'n', 'h', 9, 0, - /* 7974 */ 'c', 'l', 'g', 'i', 't', 'n', 'h', 9, 0, - /* 7983 */ 'c', 'l', 't', 'n', 'h', 9, 0, - /* 7990 */ 'c', 'r', 't', 'n', 'h', 9, 0, - /* 7997 */ 'c', 'g', 'r', 't', 'n', 'h', 9, 0, - /* 8005 */ 'c', 'l', 'g', 'r', 't', 'n', 'h', 9, 0, - /* 8014 */ 'c', 'l', 'r', 't', 'n', 'h', 9, 0, - /* 8022 */ 'v', 'm', 'a', 'o', 'h', 9, 0, - /* 8029 */ 'v', 'm', 'a', 'l', 'o', 'h', 9, 0, - /* 8037 */ 'v', 'm', 'l', 'o', 'h', 9, 0, - /* 8044 */ 'v', 'm', 'o', 'h', 9, 0, - /* 8050 */ 'v', 'l', 'r', 'e', 'p', 'h', 9, 0, - /* 8058 */ 'v', 'r', 'e', 'p', 'h', 9, 0, - /* 8065 */ 'v', 'l', 'p', 'h', 9, 0, - /* 8071 */ 'v', 'u', 'p', 'h', 9, 0, - /* 8077 */ 'v', 'c', 'e', 'q', 'h', 9, 0, - /* 8084 */ 'l', 'o', 'c', 'r', 'h', 9, 0, - /* 8091 */ 'l', 'o', 'c', 'g', 'r', 'h', 9, 0, - /* 8099 */ 'l', 'o', 'c', 'f', 'h', 'r', 'h', 9, 0, - /* 8108 */ 'v', 'm', 'r', 'h', 9, 0, - /* 8114 */ 'v', 'i', 's', 't', 'r', 'h', 9, 0, - /* 8122 */ 'v', 'p', 'k', 's', 'h', 9, 0, - /* 8129 */ 'v', 'p', 'k', 'l', 's', 'h', 9, 0, - /* 8137 */ 'v', 's', 'h', 9, 0, - /* 8142 */ 'v', 'p', 'o', 'p', 'c', 't', 'h', 9, 0, - /* 8151 */ 'b', 'r', 'c', 't', 'h', 9, 0, - /* 8158 */ 'c', 'l', 'g', 't', 'h', 9, 0, - /* 8165 */ 'c', 'i', 't', 'h', 9, 0, - /* 8171 */ 'c', 'l', 'f', 'i', 't', 'h', 9, 0, - /* 8179 */ 'c', 'g', 'i', 't', 'h', 9, 0, - /* 8186 */ 'c', 'l', 'g', 'i', 't', 'h', 9, 0, - /* 8194 */ 'c', 'l', 't', 'h', 9, 0, - /* 8200 */ 'c', 'r', 't', 'h', 9, 0, - /* 8206 */ 'c', 'g', 'r', 't', 'h', 9, 0, - /* 8213 */ 'c', 'l', 'g', 'r', 't', 'h', 9, 0, - /* 8221 */ 'c', 'l', 'r', 't', 'h', 9, 0, - /* 8228 */ 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8544 */ 'm', 'v', 'h', 'h', 'i', 9, 0, - /* 8551 */ 'l', 'h', 'i', 9, 0, - /* 8556 */ 'm', 'h', 'i', 9, 0, - /* 8561 */ 'm', 'v', 'h', 'i', 9, 0, - /* 8567 */ 'c', 'l', 'i', 9, 0, - /* 8572 */ 'n', 'i', 9, 0, - /* 8576 */ 'o', 'i', 9, 0, - /* 8580 */ 'v', 'r', 'e', 'p', 'i', 9, 0, - /* 8587 */ 't', 'p', 'i', 9, 0, - /* 8592 */ 'q', 'c', 't', 'r', 'i', 9, 0, - /* 8599 */ 'a', 's', 'i', 9, 0, - /* 8604 */ 'a', 'g', 's', 'i', 9, 0, - /* 8610 */ 'a', 'l', 'g', 's', 'i', 9, 0, - /* 8617 */ 'c', 'h', 's', 'i', 9, 0, - /* 8623 */ 'c', 'l', 'f', 'h', 's', 'i', 9, 0, - /* 8631 */ 'c', 'g', 'h', 's', 'i', 9, 0, - /* 8638 */ 'c', 'l', 'g', 'h', 's', 'i', 9, 0, - /* 8646 */ 'c', 'h', 'h', 's', 'i', 9, 0, - /* 8653 */ 'c', 'l', 'h', 'h', 's', 'i', 9, 0, - /* 8661 */ 'a', 'l', 's', 'i', 9, 0, - /* 8667 */ 'q', 's', 'i', 9, 0, - /* 8672 */ 's', 't', 's', 'i', 9, 0, - /* 8678 */ 'p', 't', 'i', 9, 0, - /* 8683 */ 'm', 'v', 'i', 9, 0, - /* 8688 */ 'x', 'i', 9, 0, - /* 8692 */ 'c', 'i', 'j', 9, 0, - /* 8697 */ 'c', 'g', 'i', 'j', 9, 0, - /* 8703 */ 'c', 'l', 'g', 'i', 'j', 9, 0, - /* 8710 */ 'c', 'l', 'i', 'j', 9, 0, - /* 8716 */ 'c', 'r', 'j', 9, 0, - /* 8721 */ 'c', 'g', 'r', 'j', 9, 0, - /* 8727 */ 'c', 'l', 'g', 'r', 'j', 9, 0, - /* 8734 */ 'c', 'l', 'r', 'j', 9, 0, - /* 8740 */ 's', 'l', 'a', 'k', 9, 0, - /* 8746 */ 's', 'r', 'a', 'k', 9, 0, - /* 8752 */ 'p', 'a', 'c', 'k', 9, 0, - /* 8758 */ 's', 'c', 'k', 9, 0, - /* 8763 */ 's', 't', 'c', 'k', 9, 0, - /* 8769 */ 'm', 'v', 'c', 'k', 9, 0, - /* 8775 */ 'm', 'v', 'c', 'd', 'k', 9, 0, - /* 8782 */ 'w', 'f', 'k', 9, 0, - /* 8787 */ 'a', 'h', 'i', 'k', 9, 0, - /* 8793 */ 'a', 'g', 'h', 'i', 'k', 9, 0, - /* 8800 */ 'a', 'l', 'g', 'h', 's', 'i', 'k', 9, 0, - /* 8809 */ 'a', 'l', 'h', 's', 'i', 'k', 9, 0, - /* 8817 */ 's', 'l', 'l', 'k', 9, 0, - /* 8823 */ 's', 'r', 'l', 'k', 9, 0, - /* 8829 */ 'e', 'd', 'm', 'k', 9, 0, - /* 8835 */ 'u', 'n', 'p', 'k', 9, 0, - /* 8841 */ 'v', 'p', 'k', 9, 0, - /* 8846 */ 'a', 'r', 'k', 9, 0, - /* 8851 */ 'a', 'g', 'r', 'k', 9, 0, - /* 8857 */ 'a', 'l', 'g', 'r', 'k', 9, 0, - /* 8864 */ 's', 'l', 'g', 'r', 'k', 9, 0, - /* 8871 */ 'm', 'g', 'r', 'k', 9, 0, - /* 8877 */ 'n', 'g', 'r', 'k', 9, 0, - /* 8883 */ 'o', 'g', 'r', 'k', 9, 0, - /* 8889 */ 's', 'g', 'r', 'k', 9, 0, - /* 8895 */ 'x', 'g', 'r', 'k', 9, 0, - /* 8901 */ 'a', 'l', 'r', 'k', 9, 0, - /* 8907 */ 's', 'l', 'r', 'k', 9, 0, - /* 8913 */ 'n', 'r', 'k', 9, 0, - /* 8918 */ 'o', 'r', 'k', 9, 0, - /* 8923 */ 's', 'r', 'k', 9, 0, - /* 8928 */ 'x', 'r', 'k', 9, 0, - /* 8933 */ 'm', 'v', 'c', 's', 'k', 9, 0, - /* 8940 */ 'i', 'v', 's', 'k', 9, 0, - /* 8946 */ 'l', 'a', 'a', 'l', 9, 0, - /* 8952 */ 'b', 'a', 'l', 9, 0, - /* 8957 */ 'v', 'm', 'a', 'l', 9, 0, - /* 8963 */ 'c', 'i', 'b', 'l', 9, 0, - /* 8969 */ 'c', 'g', 'i', 'b', 'l', 9, 0, - /* 8976 */ 'c', 'l', 'g', 'i', 'b', 'l', 9, 0, - /* 8984 */ 'c', 'l', 'i', 'b', 'l', 9, 0, - /* 8991 */ 'c', 'r', 'b', 'l', 9, 0, - /* 8997 */ 'c', 'g', 'r', 'b', 'l', 9, 0, - /* 9004 */ 'c', 'l', 'g', 'r', 'b', 'l', 9, 0, - /* 9012 */ 'c', 'l', 'r', 'b', 'l', 9, 0, - /* 9019 */ 'v', 'e', 'c', 'l', 9, 0, - /* 9025 */ 'c', 'l', 'c', 'l', 9, 0, - /* 9031 */ 'l', 'o', 'c', 'l', 9, 0, - /* 9037 */ 's', 't', 'o', 'c', 'l', 9, 0, - /* 9044 */ 'b', 'r', 'c', 'l', 9, 0, - /* 9050 */ 'm', 'v', 'c', 'l', 9, 0, - /* 9056 */ 's', 'l', 'd', 'l', 9, 0, - /* 9062 */ 's', 'r', 'd', 'l', 9, 0, - /* 9068 */ 'v', 's', 'e', 'l', 9, 0, - /* 9074 */ 's', 't', 'f', 'l', 9, 0, - /* 9080 */ 'l', 'o', 'c', 'g', 'l', 9, 0, - /* 9087 */ 's', 't', 'o', 'c', 'g', 'l', 9, 0, - /* 9095 */ 'j', 'g', 'l', 9, 0, - /* 9100 */ 'v', 'a', 'v', 'g', 'l', 9, 0, - /* 9107 */ 'v', 'c', 'h', 'l', 9, 0, - /* 9113 */ 'l', 'o', 'c', 'f', 'h', 'l', 9, 0, - /* 9121 */ 's', 't', 'o', 'c', 'f', 'h', 'l', 9, 0, - /* 9130 */ 'i', 'i', 'h', 'l', 9, 0, - /* 9136 */ 'l', 'l', 'i', 'h', 'l', 9, 0, - /* 9143 */ 'n', 'i', 'h', 'l', 9, 0, - /* 9149 */ 'o', 'i', 'h', 'l', 9, 0, - /* 9155 */ 't', 'm', 'h', 'l', 9, 0, - /* 9161 */ 'b', 'i', 'l', 9, 0, - /* 9166 */ 'l', 'o', 'c', 'h', 'i', 'l', 9, 0, - /* 9174 */ 'l', 'o', 'c', 'g', 'h', 'i', 'l', 9, 0, - /* 9183 */ 'l', 'o', 'c', 'h', 'h', 'i', 'l', 9, 0, - /* 9192 */ 'c', 'i', 'j', 'l', 9, 0, - /* 9198 */ 'c', 'g', 'i', 'j', 'l', 9, 0, - /* 9205 */ 'c', 'l', 'g', 'i', 'j', 'l', 9, 0, - /* 9213 */ 'c', 'l', 'i', 'j', 'l', 9, 0, - /* 9220 */ 'c', 'r', 'j', 'l', 9, 0, - /* 9226 */ 'c', 'g', 'r', 'j', 'l', 9, 0, - /* 9233 */ 'c', 'l', 'g', 'r', 'j', 'l', 9, 0, - /* 9241 */ 'c', 'l', 'r', 'j', 'l', 9, 0, - /* 9248 */ 'v', 'f', 'l', 'l', 9, 0, - /* 9254 */ 'i', 'i', 'l', 'l', 9, 0, - /* 9260 */ 'l', 'l', 'i', 'l', 'l', 9, 0, - /* 9267 */ 'n', 'i', 'l', 'l', 9, 0, - /* 9273 */ 'o', 'i', 'l', 'l', 9, 0, - /* 9279 */ 't', 'm', 'l', 'l', 9, 0, - /* 9285 */ 'v', 'u', 'p', 'l', 'l', 9, 0, - /* 9292 */ 'v', 'e', 'r', 'l', 'l', 9, 0, - /* 9299 */ 's', 'l', 'l', 9, 0, - /* 9304 */ 'v', 'l', 'l', 9, 0, - /* 9309 */ 'v', 'm', 'l', 9, 0, - /* 9314 */ 'c', 'i', 'b', 'n', 'l', 9, 0, - /* 9321 */ 'c', 'g', 'i', 'b', 'n', 'l', 9, 0, - /* 9329 */ 'c', 'l', 'g', 'i', 'b', 'n', 'l', 9, 0, - /* 9338 */ 'c', 'l', 'i', 'b', 'n', 'l', 9, 0, - /* 9346 */ 'c', 'r', 'b', 'n', 'l', 9, 0, - /* 9353 */ 'c', 'g', 'r', 'b', 'n', 'l', 9, 0, - /* 9361 */ 'c', 'l', 'g', 'r', 'b', 'n', 'l', 9, 0, - /* 9370 */ 'c', 'l', 'r', 'b', 'n', 'l', 9, 0, - /* 9378 */ 'l', 'o', 'c', 'n', 'l', 9, 0, - /* 9385 */ 's', 't', 'o', 'c', 'n', 'l', 9, 0, - /* 9393 */ 'l', 'o', 'c', 'g', 'n', 'l', 9, 0, - /* 9401 */ 's', 't', 'o', 'c', 'g', 'n', 'l', 9, 0, - /* 9410 */ 'j', 'g', 'n', 'l', 9, 0, - /* 9416 */ 'l', 'o', 'c', 'f', 'h', 'n', 'l', 9, 0, - /* 9425 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'l', 9, 0, - /* 9435 */ 'b', 'i', 'n', 'l', 9, 0, - /* 9441 */ 'l', 'o', 'c', 'h', 'i', 'n', 'l', 9, 0, - /* 9450 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'l', 9, 0, - /* 9460 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'l', 9, 0, - /* 9470 */ 'c', 'i', 'j', 'n', 'l', 9, 0, - /* 9477 */ 'c', 'g', 'i', 'j', 'n', 'l', 9, 0, - /* 9485 */ 'c', 'l', 'g', 'i', 'j', 'n', 'l', 9, 0, - /* 9494 */ 'c', 'l', 'i', 'j', 'n', 'l', 9, 0, - /* 9502 */ 'c', 'r', 'j', 'n', 'l', 9, 0, - /* 9509 */ 'c', 'g', 'r', 'j', 'n', 'l', 9, 0, - /* 9517 */ 'c', 'l', 'g', 'r', 'j', 'n', 'l', 9, 0, - /* 9526 */ 'c', 'l', 'r', 'j', 'n', 'l', 9, 0, - /* 9534 */ 'v', 'm', 'n', 'l', 9, 0, - /* 9540 */ 'l', 'o', 'c', 'r', 'n', 'l', 9, 0, - /* 9548 */ 'l', 'o', 'c', 'g', 'r', 'n', 'l', 9, 0, - /* 9557 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'l', 9, 0, - /* 9567 */ 'c', 'l', 'g', 't', 'n', 'l', 9, 0, - /* 9575 */ 'c', 'i', 't', 'n', 'l', 9, 0, - /* 9582 */ 'c', 'l', 'f', 'i', 't', 'n', 'l', 9, 0, - /* 9591 */ 'c', 'g', 'i', 't', 'n', 'l', 9, 0, - /* 9599 */ 'c', 'l', 'g', 'i', 't', 'n', 'l', 9, 0, - /* 9608 */ 'c', 'l', 't', 'n', 'l', 9, 0, - /* 9615 */ 'c', 'r', 't', 'n', 'l', 9, 0, - /* 9622 */ 'c', 'g', 'r', 't', 'n', 'l', 9, 0, - /* 9630 */ 'c', 'l', 'g', 'r', 't', 'n', 'l', 9, 0, - /* 9639 */ 'c', 'l', 'r', 't', 'n', 'l', 9, 0, - /* 9647 */ 'v', 'u', 'p', 'l', 9, 0, - /* 9653 */ 'l', 'a', 'r', 'l', 9, 0, - /* 9659 */ 'l', 'o', 'c', 'r', 'l', 9, 0, - /* 9666 */ 'p', 'f', 'd', 'r', 'l', 9, 0, - /* 9673 */ 'c', 'g', 'f', 'r', 'l', 9, 0, - /* 9680 */ 'c', 'l', 'g', 'f', 'r', 'l', 9, 0, - /* 9688 */ 'l', 'l', 'g', 'f', 'r', 'l', 9, 0, - /* 9696 */ 'l', 'o', 'c', 'g', 'r', 'l', 9, 0, - /* 9704 */ 'c', 'l', 'g', 'r', 'l', 9, 0, - /* 9711 */ 's', 't', 'g', 'r', 'l', 9, 0, - /* 9718 */ 'c', 'h', 'r', 'l', 9, 0, - /* 9724 */ 'l', 'o', 'c', 'f', 'h', 'r', 'l', 9, 0, - /* 9733 */ 'c', 'g', 'h', 'r', 'l', 9, 0, - /* 9740 */ 'c', 'l', 'g', 'h', 'r', 'l', 9, 0, - /* 9748 */ 'l', 'l', 'g', 'h', 'r', 'l', 9, 0, - /* 9756 */ 'c', 'l', 'h', 'r', 'l', 9, 0, - /* 9763 */ 'l', 'l', 'h', 'r', 'l', 9, 0, - /* 9770 */ 's', 't', 'h', 'r', 'l', 9, 0, - /* 9777 */ 'c', 'l', 'r', 'l', 9, 0, - /* 9783 */ 'v', 'l', 'r', 'l', 9, 0, - /* 9789 */ 'v', 'm', 'r', 'l', 9, 0, - /* 9795 */ 'v', 'e', 's', 'r', 'l', 9, 0, - /* 9802 */ 'v', 's', 'r', 'l', 9, 0, - /* 9808 */ 'v', 's', 't', 'r', 'l', 9, 0, - /* 9815 */ 'e', 'x', 'r', 'l', 9, 0, - /* 9821 */ 'b', 'r', 'a', 's', 'l', 9, 0, - /* 9828 */ 'v', 'e', 's', 'l', 9, 0, - /* 9834 */ 'v', 'm', 's', 'l', 9, 0, - /* 9840 */ 'v', 's', 'l', 9, 0, - /* 9845 */ 'l', 'c', 'c', 't', 'l', 9, 0, - /* 9852 */ 'l', 'c', 't', 'l', 9, 0, - /* 9858 */ 'l', 'p', 'c', 't', 'l', 9, 0, - /* 9865 */ 'l', 's', 'c', 't', 'l', 9, 0, - /* 9872 */ 's', 't', 'c', 't', 'l', 9, 0, - /* 9879 */ 'c', 'l', 'g', 't', 'l', 9, 0, - /* 9886 */ 'c', 'i', 't', 'l', 9, 0, - /* 9892 */ 'c', 'l', 'f', 'i', 't', 'l', 9, 0, - /* 9900 */ 'c', 'g', 'i', 't', 'l', 9, 0, - /* 9907 */ 'c', 'l', 'g', 'i', 't', 'l', 9, 0, - /* 9915 */ 'c', 'l', 't', 'l', 9, 0, - /* 9921 */ 'c', 'r', 't', 'l', 9, 0, - /* 9927 */ 'c', 'g', 'r', 't', 'l', 9, 0, - /* 9934 */ 'c', 'l', 'g', 'r', 't', 'l', 9, 0, - /* 9942 */ 'c', 'l', 'r', 't', 'l', 9, 0, - /* 9949 */ 'v', 's', 't', 'l', 9, 0, - /* 9955 */ 'v', 'l', 9, 0, - /* 9959 */ 'v', 'm', 'x', 'l', 9, 0, - /* 9965 */ 'm', 'a', 'y', 'l', 9, 0, - /* 9971 */ 'm', 'y', 'l', 9, 0, - /* 9976 */ 'l', 'a', 'm', 9, 0, - /* 9981 */ 's', 't', 'a', 'm', 9, 0, - /* 9987 */ 'v', 'g', 'b', 'm', 9, 0, - /* 9993 */ 'i', 'r', 'b', 'm', 9, 0, - /* 9999 */ 'r', 'r', 'b', 'm', 9, 0, - /* 10005 */ 'i', 'c', 'm', 9, 0, - /* 10010 */ 'l', 'o', 'c', 'm', 9, 0, - /* 10016 */ 's', 't', 'o', 'c', 'm', 9, 0, - /* 10023 */ 's', 't', 'c', 'm', 9, 0, - /* 10029 */ 'v', 'g', 'f', 'm', 9, 0, - /* 10035 */ 'v', 'f', 'm', 9, 0, - /* 10040 */ 'l', 'o', 'c', 'g', 'm', 9, 0, - /* 10047 */ 's', 't', 'o', 'c', 'g', 'm', 9, 0, - /* 10055 */ 'j', 'g', 'm', 9, 0, - /* 10060 */ 'v', 'g', 'm', 9, 0, - /* 10065 */ 'l', 'o', 'c', 'f', 'h', 'm', 9, 0, - /* 10073 */ 's', 't', 'o', 'c', 'f', 'h', 'm', 9, 0, - /* 10082 */ 'b', 'i', 'm', 9, 0, - /* 10087 */ 'l', 'o', 'c', 'h', 'i', 'm', 9, 0, - /* 10095 */ 'l', 'o', 'c', 'g', 'h', 'i', 'm', 9, 0, - /* 10104 */ 'l', 'o', 'c', 'h', 'h', 'i', 'm', 9, 0, - /* 10113 */ 'v', 'e', 'r', 'i', 'm', 9, 0, - /* 10120 */ 'j', 'm', 9, 0, - /* 10124 */ 'k', 'm', 9, 0, - /* 10128 */ 'c', 'l', 'm', 9, 0, - /* 10133 */ 'v', 'l', 'm', 9, 0, - /* 10138 */ 'b', 'n', 'm', 9, 0, - /* 10143 */ 'l', 'o', 'c', 'n', 'm', 9, 0, - /* 10150 */ 's', 't', 'o', 'c', 'n', 'm', 9, 0, - /* 10158 */ 'l', 'o', 'c', 'g', 'n', 'm', 9, 0, - /* 10166 */ 's', 't', 'o', 'c', 'g', 'n', 'm', 9, 0, - /* 10175 */ 'j', 'g', 'n', 'm', 9, 0, - /* 10181 */ 'l', 'o', 'c', 'f', 'h', 'n', 'm', 9, 0, - /* 10190 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'm', 9, 0, - /* 10200 */ 'b', 'i', 'n', 'm', 9, 0, - /* 10206 */ 'l', 'o', 'c', 'h', 'i', 'n', 'm', 9, 0, - /* 10215 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'm', 9, 0, - /* 10225 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'm', 9, 0, - /* 10235 */ 'j', 'n', 'm', 9, 0, - /* 10240 */ 'l', 'o', 'c', 'r', 'n', 'm', 9, 0, - /* 10248 */ 'l', 'o', 'c', 'g', 'r', 'n', 'm', 9, 0, - /* 10257 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'm', 9, 0, - /* 10267 */ 's', 'r', 'n', 'm', 9, 0, - /* 10273 */ 'i', 'p', 'm', 9, 0, - /* 10278 */ 's', 'p', 'm', 9, 0, - /* 10283 */ 'l', 'o', 'c', 'r', 'm', 9, 0, - /* 10290 */ 'v', 'b', 'p', 'e', 'r', 'm', 9, 0, - /* 10298 */ 'v', 'p', 'e', 'r', 'm', 9, 0, - /* 10305 */ 'l', 'o', 'c', 'g', 'r', 'm', 9, 0, - /* 10313 */ 'l', 'o', 'c', 'f', 'h', 'r', 'm', 9, 0, - /* 10322 */ 'b', 's', 'm', 9, 0, - /* 10327 */ 'v', 'c', 'k', 's', 'm', 9, 0, - /* 10334 */ 's', 't', 'n', 's', 'm', 9, 0, - /* 10341 */ 's', 't', 'o', 's', 'm', 9, 0, - /* 10348 */ 'b', 'a', 's', 's', 'm', 9, 0, - /* 10355 */ 'v', 's', 't', 'm', 9, 0, - /* 10361 */ 'v', 't', 'm', 9, 0, - /* 10366 */ 'v', 's', 'u', 'm', 9, 0, - /* 10372 */ 'l', 'a', 'n', 9, 0, - /* 10377 */ 'r', 'i', 's', 'b', 'g', 'n', 9, 0, - /* 10385 */ 'a', 'l', 's', 'i', 'h', 'n', 9, 0, - /* 10393 */ 'm', 'v', 'c', 'i', 'n', 9, 0, - /* 10400 */ 't', 'b', 'e', 'g', 'i', 'n', 9, 0, - /* 10408 */ 'p', 'g', 'i', 'n', 9, 0, - /* 10414 */ 'v', 'f', 'm', 'i', 'n', 9, 0, - /* 10421 */ 'v', 'm', 'n', 9, 0, - /* 10426 */ 'v', 'n', 'n', 9, 0, - /* 10431 */ 'm', 'v', 'n', 9, 0, - /* 10436 */ 'l', 'a', 'o', 9, 0, - /* 10441 */ 'v', 'm', 'a', 'o', 9, 0, - /* 10447 */ 'b', 'o', 9, 0, - /* 10451 */ 'l', 'o', 'c', 'o', 9, 0, - /* 10457 */ 's', 't', 'o', 'c', 'o', 9, 0, - /* 10464 */ 'l', 'o', 'c', 'g', 'o', 9, 0, - /* 10471 */ 's', 't', 'o', 'c', 'g', 'o', 9, 0, - /* 10479 */ 'j', 'g', 'o', 9, 0, - /* 10484 */ 'l', 'o', 'c', 'f', 'h', 'o', 9, 0, - /* 10492 */ 's', 't', 'o', 'c', 'f', 'h', 'o', 9, 0, - /* 10501 */ 'b', 'i', 'o', 9, 0, - /* 10506 */ 'l', 'o', 'c', 'h', 'i', 'o', 9, 0, - /* 10514 */ 'l', 'o', 'c', 'g', 'h', 'i', 'o', 9, 0, - /* 10523 */ 'l', 'o', 'c', 'h', 'h', 'i', 'o', 9, 0, - /* 10532 */ 'j', 'o', 9, 0, - /* 10536 */ 'v', 'm', 'a', 'l', 'o', 9, 0, - /* 10543 */ 'v', 'm', 'l', 'o', 9, 0, - /* 10549 */ 'p', 'l', 'o', 9, 0, - /* 10554 */ 'k', 'm', 'o', 9, 0, - /* 10559 */ 'v', 'm', 'o', 9, 0, - /* 10564 */ 'b', 'n', 'o', 9, 0, - /* 10569 */ 'l', 'o', 'c', 'n', 'o', 9, 0, - /* 10576 */ 's', 't', 'o', 'c', 'n', 'o', 9, 0, - /* 10584 */ 'l', 'o', 'c', 'g', 'n', 'o', 9, 0, - /* 10592 */ 's', 't', 'o', 'c', 'g', 'n', 'o', 9, 0, - /* 10601 */ 'j', 'g', 'n', 'o', 9, 0, - /* 10607 */ 'l', 'o', 'c', 'f', 'h', 'n', 'o', 9, 0, - /* 10616 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'o', 9, 0, - /* 10626 */ 'b', 'i', 'n', 'o', 9, 0, - /* 10632 */ 'l', 'o', 'c', 'h', 'i', 'n', 'o', 9, 0, - /* 10641 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'o', 9, 0, - /* 10651 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'o', 9, 0, - /* 10661 */ 'j', 'n', 'o', 9, 0, - /* 10666 */ 'p', 'p', 'n', 'o', 9, 0, - /* 10672 */ 'l', 'o', 'c', 'r', 'n', 'o', 9, 0, - /* 10680 */ 'l', 'o', 'c', 'g', 'r', 'n', 'o', 9, 0, - /* 10689 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'o', 9, 0, - /* 10699 */ 'p', 'r', 'n', 'o', 9, 0, - /* 10705 */ 'v', 'n', 'o', 9, 0, - /* 10710 */ 't', 'r', 'o', 'o', 9, 0, - /* 10716 */ 'l', 'o', 'c', 'r', 'o', 9, 0, - /* 10723 */ 'v', 'z', 'e', 'r', 'o', 9, 0, - /* 10730 */ 'l', 'o', 'c', 'g', 'r', 'o', 9, 0, - /* 10738 */ 'l', 'o', 'c', 'f', 'h', 'r', 'o', 9, 0, - /* 10747 */ 'v', 'f', 'p', 's', 'o', 9, 0, - /* 10754 */ 't', 'r', 't', 'o', 9, 0, - /* 10760 */ 'm', 'v', 'o', 9, 0, - /* 10765 */ 's', 't', 'a', 'p', 9, 0, - /* 10771 */ 'v', 'a', 'p', 9, 0, - /* 10776 */ 'z', 'a', 'p', 9, 0, - /* 10781 */ 'b', 'p', 9, 0, - /* 10785 */ 'l', 'o', 'c', 'p', 9, 0, - /* 10791 */ 's', 't', 'o', 'c', 'p', 9, 0, - /* 10798 */ 'm', 'v', 'c', 'p', 9, 0, - /* 10804 */ 's', 't', 'i', 'd', 'p', 9, 0, - /* 10811 */ 'v', 's', 'd', 'p', 9, 0, - /* 10817 */ 'v', 'd', 'p', 9, 0, - /* 10822 */ 'v', 'l', 'r', 'e', 'p', 9, 0, - /* 10829 */ 'v', 'r', 'e', 'p', 9, 0, - /* 10835 */ 'l', 'o', 'c', 'g', 'p', 9, 0, - /* 10842 */ 's', 't', 'o', 'c', 'g', 'p', 9, 0, - /* 10850 */ 's', 'i', 'g', 'p', 9, 0, - /* 10856 */ 'j', 'g', 'p', 9, 0, - /* 10861 */ 'v', 'l', 'v', 'g', 'p', 9, 0, - /* 10868 */ 'l', 'o', 'c', 'f', 'h', 'p', 9, 0, - /* 10876 */ 's', 't', 'o', 'c', 'f', 'h', 'p', 9, 0, - /* 10885 */ 'b', 'i', 'p', 9, 0, - /* 10890 */ 'l', 'o', 'c', 'h', 'i', 'p', 9, 0, - /* 10898 */ 'l', 'o', 'c', 'g', 'h', 'i', 'p', 9, 0, - /* 10907 */ 'l', 'o', 'c', 'h', 'h', 'i', 'p', 9, 0, - /* 10916 */ 'v', 'l', 'i', 'p', 9, 0, - /* 10922 */ 'j', 'p', 9, 0, - /* 10926 */ 'v', 'l', 'p', 9, 0, - /* 10931 */ 'v', 'm', 'p', 9, 0, - /* 10936 */ 'b', 'n', 'p', 9, 0, - /* 10941 */ 'l', 'o', 'c', 'n', 'p', 9, 0, - /* 10948 */ 's', 't', 'o', 'c', 'n', 'p', 9, 0, - /* 10956 */ 'l', 'o', 'c', 'g', 'n', 'p', 9, 0, - /* 10964 */ 's', 't', 'o', 'c', 'g', 'n', 'p', 9, 0, - /* 10973 */ 'j', 'g', 'n', 'p', 9, 0, - /* 10979 */ 'l', 'o', 'c', 'f', 'h', 'n', 'p', 9, 0, - /* 10988 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'p', 9, 0, - /* 10998 */ 'b', 'i', 'n', 'p', 9, 0, - /* 11004 */ 'l', 'o', 'c', 'h', 'i', 'n', 'p', 9, 0, - /* 11013 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'p', 9, 0, - /* 11023 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'p', 9, 0, - /* 11033 */ 'j', 'n', 'p', 9, 0, - /* 11038 */ 'l', 'o', 'c', 'r', 'n', 'p', 9, 0, - /* 11046 */ 'l', 'o', 'c', 'g', 'r', 'n', 'p', 9, 0, - /* 11055 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'p', 9, 0, - /* 11065 */ 'v', 'p', 's', 'o', 'p', 9, 0, - /* 11072 */ 'b', 'p', 'p', 9, 0, - /* 11077 */ 'l', 'p', 'p', 9, 0, - /* 11082 */ 'l', 'o', 'c', 'r', 'p', 9, 0, - /* 11089 */ 'l', 'o', 'c', 'g', 'r', 'p', 9, 0, - /* 11097 */ 'l', 'o', 'c', 'f', 'h', 'r', 'p', 9, 0, - /* 11106 */ 'b', 'p', 'r', 'p', 9, 0, - /* 11112 */ 'v', 's', 'r', 'p', 9, 0, - /* 11118 */ 'v', 'r', 'p', 9, 0, - /* 11123 */ 'l', 'a', 's', 'p', 9, 0, - /* 11129 */ 'c', 's', 'p', 9, 0, - /* 11134 */ 'v', 'm', 's', 'p', 9, 0, - /* 11140 */ 'v', 's', 'p', 9, 0, - /* 11145 */ 'v', 't', 'p', 9, 0, - /* 11150 */ 'v', 'a', 'q', 9, 0, - /* 11155 */ 'v', 'a', 'c', 'q', 9, 0, - /* 11161 */ 'v', 'a', 'c', 'c', 'q', 9, 0, - /* 11168 */ 'v', 'a', 'c', 'c', 'c', 'q', 9, 0, - /* 11176 */ 'v', 'c', 'e', 'q', 9, 0, - /* 11182 */ 'v', 's', 'b', 'c', 'b', 'i', 'q', 9, 0, - /* 11191 */ 'v', 's', 'c', 'b', 'i', 'q', 9, 0, - /* 11199 */ 'v', 's', 'b', 'i', 'q', 9, 0, - /* 11206 */ 'v', 's', 'u', 'm', 'q', 9, 0, - /* 11213 */ 'l', 'p', 'q', 9, 0, - /* 11218 */ 's', 't', 'p', 'q', 9, 0, - /* 11224 */ 'v', 'f', 's', 'q', 9, 0, - /* 11230 */ 'v', 's', 'q', 9, 0, - /* 11235 */ 'e', 'a', 'r', 9, 0, - /* 11240 */ 'e', 'p', 'a', 'r', 9, 0, - /* 11246 */ 'e', 's', 'a', 'r', 9, 0, - /* 11252 */ 's', 's', 'a', 'r', 9, 0, - /* 11258 */ 't', 'a', 'r', 9, 0, - /* 11263 */ 'm', 'a', 'd', 'b', 'r', 9, 0, - /* 11270 */ 'l', 'c', 'd', 'b', 'r', 9, 0, - /* 11277 */ 'd', 'd', 'b', 'r', 9, 0, - /* 11283 */ 'l', 'e', 'd', 'b', 'r', 9, 0, - /* 11290 */ 'c', 'f', 'd', 'b', 'r', 9, 0, - /* 11297 */ 'c', 'l', 'f', 'd', 'b', 'r', 9, 0, - /* 11305 */ 'c', 'g', 'd', 'b', 'r', 9, 0, - /* 11312 */ 'c', 'l', 'g', 'd', 'b', 'r', 9, 0, - /* 11320 */ 'd', 'i', 'd', 'b', 'r', 9, 0, - /* 11327 */ 'f', 'i', 'd', 'b', 'r', 9, 0, - /* 11334 */ 'k', 'd', 'b', 'r', 9, 0, - /* 11340 */ 'm', 'd', 'b', 'r', 9, 0, - /* 11346 */ 'l', 'n', 'd', 'b', 'r', 9, 0, - /* 11353 */ 'l', 'p', 'd', 'b', 'r', 9, 0, - /* 11360 */ 's', 'q', 'd', 'b', 'r', 9, 0, - /* 11367 */ 'm', 's', 'd', 'b', 'r', 9, 0, - /* 11374 */ 'l', 't', 'd', 'b', 'r', 9, 0, - /* 11381 */ 'l', 'x', 'd', 'b', 'r', 9, 0, - /* 11388 */ 'm', 'x', 'd', 'b', 'r', 9, 0, - /* 11395 */ 'm', 'a', 'e', 'b', 'r', 9, 0, - /* 11402 */ 'l', 'c', 'e', 'b', 'r', 9, 0, - /* 11409 */ 'l', 'd', 'e', 'b', 'r', 9, 0, - /* 11416 */ 'm', 'd', 'e', 'b', 'r', 9, 0, - /* 11423 */ 'm', 'e', 'e', 'b', 'r', 9, 0, - /* 11430 */ 'c', 'f', 'e', 'b', 'r', 9, 0, - /* 11437 */ 'c', 'l', 'f', 'e', 'b', 'r', 9, 0, - /* 11445 */ 'c', 'g', 'e', 'b', 'r', 9, 0, - /* 11452 */ 'c', 'l', 'g', 'e', 'b', 'r', 9, 0, - /* 11460 */ 'd', 'i', 'e', 'b', 'r', 9, 0, - /* 11467 */ 'f', 'i', 'e', 'b', 'r', 9, 0, - /* 11474 */ 'k', 'e', 'b', 'r', 9, 0, - /* 11480 */ 'l', 'n', 'e', 'b', 'r', 9, 0, - /* 11487 */ 'l', 'p', 'e', 'b', 'r', 9, 0, - /* 11494 */ 's', 'q', 'e', 'b', 'r', 9, 0, - /* 11501 */ 'm', 's', 'e', 'b', 'r', 9, 0, - /* 11508 */ 'l', 't', 'e', 'b', 'r', 9, 0, - /* 11515 */ 'l', 'x', 'e', 'b', 'r', 9, 0, - /* 11522 */ 'c', 'd', 'f', 'b', 'r', 9, 0, - /* 11529 */ 'c', 'e', 'f', 'b', 'r', 9, 0, - /* 11536 */ 'c', 'd', 'l', 'f', 'b', 'r', 9, 0, - /* 11544 */ 'c', 'e', 'l', 'f', 'b', 'r', 9, 0, - /* 11552 */ 'c', 'x', 'l', 'f', 'b', 'r', 9, 0, - /* 11560 */ 'c', 'x', 'f', 'b', 'r', 9, 0, - /* 11567 */ 'c', 'd', 'g', 'b', 'r', 9, 0, - /* 11574 */ 'c', 'e', 'g', 'b', 'r', 9, 0, - /* 11581 */ 'c', 'd', 'l', 'g', 'b', 'r', 9, 0, - /* 11589 */ 'c', 'e', 'l', 'g', 'b', 'r', 9, 0, - /* 11597 */ 'c', 'x', 'l', 'g', 'b', 'r', 9, 0, - /* 11605 */ 'c', 'x', 'g', 'b', 'r', 9, 0, - /* 11612 */ 's', 'l', 'b', 'r', 9, 0, - /* 11618 */ 'a', 'x', 'b', 'r', 9, 0, - /* 11624 */ 'l', 'c', 'x', 'b', 'r', 9, 0, - /* 11631 */ 'l', 'd', 'x', 'b', 'r', 9, 0, - /* 11638 */ 'l', 'e', 'x', 'b', 'r', 9, 0, - /* 11645 */ 'c', 'f', 'x', 'b', 'r', 9, 0, - /* 11652 */ 'c', 'l', 'f', 'x', 'b', 'r', 9, 0, - /* 11660 */ 'c', 'g', 'x', 'b', 'r', 9, 0, - /* 11667 */ 'c', 'l', 'g', 'x', 'b', 'r', 9, 0, - /* 11675 */ 'f', 'i', 'x', 'b', 'r', 9, 0, - /* 11682 */ 'k', 'x', 'b', 'r', 9, 0, - /* 11688 */ 'm', 'x', 'b', 'r', 9, 0, - /* 11694 */ 'l', 'n', 'x', 'b', 'r', 9, 0, - /* 11701 */ 'l', 'p', 'x', 'b', 'r', 9, 0, - /* 11708 */ 's', 'q', 'x', 'b', 'r', 9, 0, - /* 11715 */ 's', 'x', 'b', 'r', 9, 0, - /* 11721 */ 'l', 't', 'x', 'b', 'r', 9, 0, - /* 11728 */ 'b', 'c', 'r', 9, 0, - /* 11733 */ 'l', 'l', 'g', 'c', 'r', 9, 0, - /* 11740 */ 'a', 'l', 'c', 'r', 9, 0, - /* 11746 */ 'l', 'l', 'c', 'r', 9, 0, - /* 11752 */ 'l', 'o', 'c', 'r', 9, 0, - /* 11758 */ 'm', 'a', 'd', 'r', 9, 0, - /* 11764 */ 't', 'b', 'd', 'r', 9, 0, - /* 11770 */ 'l', 'c', 'd', 'r', 9, 0, - /* 11776 */ 'd', 'd', 'r', 9, 0, - /* 11781 */ 't', 'b', 'e', 'd', 'r', 9, 0, - /* 11788 */ 'l', 'e', 'd', 'r', 9, 0, - /* 11794 */ 'c', 'f', 'd', 'r', 9, 0, - /* 11800 */ 'c', 'g', 'd', 'r', 9, 0, - /* 11806 */ 'l', 'g', 'd', 'r', 9, 0, - /* 11812 */ 't', 'h', 'd', 'r', 9, 0, - /* 11818 */ 'f', 'i', 'd', 'r', 9, 0, - /* 11824 */ 'l', 'd', 'r', 9, 0, - /* 11829 */ 'm', 'd', 'r', 9, 0, - /* 11834 */ 'l', 'n', 'd', 'r', 9, 0, - /* 11840 */ 'l', 'p', 'd', 'r', 9, 0, - /* 11846 */ 's', 'q', 'd', 'r', 9, 0, - /* 11852 */ 'l', 'r', 'd', 'r', 9, 0, - /* 11858 */ 'm', 's', 'd', 'r', 9, 0, - /* 11864 */ 'c', 'p', 's', 'd', 'r', 9, 0, - /* 11871 */ 'l', 't', 'd', 'r', 9, 0, - /* 11877 */ 'l', 'x', 'd', 'r', 9, 0, - /* 11883 */ 'm', 'x', 'd', 'r', 9, 0, - /* 11889 */ 'l', 'z', 'd', 'r', 9, 0, - /* 11895 */ 'm', 'a', 'e', 'r', 9, 0, - /* 11901 */ 'b', 'e', 'r', 9, 0, - /* 11906 */ 'l', 'c', 'e', 'r', 9, 0, - /* 11912 */ 't', 'h', 'd', 'e', 'r', 9, 0, - /* 11919 */ 'l', 'd', 'e', 'r', 9, 0, - /* 11925 */ 'm', 'd', 'e', 'r', 9, 0, - /* 11931 */ 'm', 'e', 'e', 'r', 9, 0, - /* 11937 */ 'c', 'f', 'e', 'r', 9, 0, - /* 11943 */ 'c', 'g', 'e', 'r', 9, 0, - /* 11949 */ 'b', 'h', 'e', 'r', 9, 0, - /* 11955 */ 'b', 'n', 'h', 'e', 'r', 9, 0, - /* 11962 */ 'f', 'i', 'e', 'r', 9, 0, - /* 11968 */ 'b', 'l', 'e', 'r', 9, 0, - /* 11974 */ 'b', 'n', 'l', 'e', 'r', 9, 0, - /* 11981 */ 'm', 'e', 'r', 9, 0, - /* 11986 */ 'b', 'n', 'e', 'r', 9, 0, - /* 11992 */ 'l', 'n', 'e', 'r', 9, 0, - /* 11998 */ 'l', 'p', 'e', 'r', 9, 0, - /* 12004 */ 's', 'q', 'e', 'r', 9, 0, - /* 12010 */ 'l', 'r', 'e', 'r', 9, 0, - /* 12016 */ 'm', 's', 'e', 'r', 9, 0, - /* 12022 */ 'l', 't', 'e', 'r', 9, 0, - /* 12028 */ 'l', 'x', 'e', 'r', 9, 0, - /* 12034 */ 'l', 'z', 'e', 'r', 9, 0, - /* 12040 */ 'l', 'c', 'd', 'f', 'r', 9, 0, - /* 12047 */ 'l', 'n', 'd', 'f', 'r', 9, 0, - /* 12054 */ 'l', 'p', 'd', 'f', 'r', 9, 0, - /* 12061 */ 'c', 'e', 'f', 'r', 9, 0, - /* 12067 */ 'a', 'g', 'f', 'r', 9, 0, - /* 12073 */ 'l', 'c', 'g', 'f', 'r', 9, 0, - /* 12080 */ 'a', 'l', 'g', 'f', 'r', 9, 0, - /* 12087 */ 'c', 'l', 'g', 'f', 'r', 9, 0, - /* 12094 */ 'l', 'l', 'g', 'f', 'r', 9, 0, - /* 12101 */ 's', 'l', 'g', 'f', 'r', 9, 0, - /* 12108 */ 'l', 'n', 'g', 'f', 'r', 9, 0, - /* 12115 */ 'l', 'p', 'g', 'f', 'r', 9, 0, - /* 12122 */ 'd', 's', 'g', 'f', 'r', 9, 0, - /* 12129 */ 'm', 's', 'g', 'f', 'r', 9, 0, - /* 12136 */ 'l', 't', 'g', 'f', 'r', 9, 0, - /* 12143 */ 'c', 'x', 'f', 'r', 9, 0, - /* 12149 */ 'a', 'g', 'r', 9, 0, - /* 12154 */ 's', 'l', 'b', 'g', 'r', 9, 0, - /* 12161 */ 'a', 'l', 'c', 'g', 'r', 9, 0, - /* 12168 */ 'l', 'o', 'c', 'g', 'r', 9, 0, - /* 12175 */ 'c', 'd', 'g', 'r', 9, 0, - /* 12181 */ 'l', 'd', 'g', 'r', 9, 0, - /* 12187 */ 'c', 'e', 'g', 'r', 9, 0, - /* 12193 */ 'a', 'l', 'g', 'r', 9, 0, - /* 12199 */ 'c', 'l', 'g', 'r', 9, 0, - /* 12205 */ 'd', 'l', 'g', 'r', 9, 0, - /* 12211 */ 'm', 'l', 'g', 'r', 9, 0, - /* 12217 */ 's', 'l', 'g', 'r', 9, 0, - /* 12223 */ 'l', 'n', 'g', 'r', 9, 0, - /* 12229 */ 'f', 'l', 'o', 'g', 'r', 9, 0, - /* 12236 */ 'l', 'p', 'g', 'r', 9, 0, - /* 12242 */ 'd', 's', 'g', 'r', 9, 0, - /* 12248 */ 'm', 's', 'g', 'r', 9, 0, - /* 12254 */ 'b', 'c', 't', 'g', 'r', 9, 0, - /* 12261 */ 'l', 't', 'g', 'r', 9, 0, - /* 12267 */ 'l', 'r', 'v', 'g', 'r', 9, 0, - /* 12274 */ 'c', 'x', 'g', 'r', 9, 0, - /* 12280 */ 'b', 'h', 'r', 9, 0, - /* 12285 */ 'l', 'o', 'c', 'f', 'h', 'r', 9, 0, - /* 12293 */ 'l', 'l', 'g', 'h', 'r', 9, 0, - /* 12300 */ 'c', 'h', 'h', 'r', 9, 0, - /* 12306 */ 'a', 'h', 'h', 'h', 'r', 9, 0, - /* 12313 */ 'a', 'l', 'h', 'h', 'h', 'r', 9, 0, - /* 12321 */ 's', 'l', 'h', 'h', 'h', 'r', 9, 0, - /* 12329 */ 's', 'h', 'h', 'h', 'r', 9, 0, - /* 12336 */ 'c', 'l', 'h', 'h', 'r', 9, 0, - /* 12343 */ 'b', 'l', 'h', 'r', 9, 0, - /* 12349 */ 'l', 'l', 'h', 'r', 9, 0, - /* 12355 */ 'b', 'n', 'l', 'h', 'r', 9, 0, - /* 12362 */ 'b', 'n', 'h', 'r', 9, 0, - /* 12368 */ 'm', 'a', 'y', 'h', 'r', 9, 0, - /* 12375 */ 'm', 'y', 'h', 'r', 9, 0, - /* 12381 */ 'e', 'p', 'a', 'i', 'r', 9, 0, - /* 12388 */ 'e', 's', 'a', 'i', 'r', 9, 0, - /* 12395 */ 's', 's', 'a', 'i', 'r', 9, 0, - /* 12402 */ 'b', 'a', 'k', 'r', 9, 0, - /* 12408 */ 'b', 'a', 'l', 'r', 9, 0, - /* 12414 */ 'b', 'l', 'r', 9, 0, - /* 12419 */ 'c', 'l', 'r', 9, 0, - /* 12424 */ 'd', 'l', 'r', 9, 0, - /* 12429 */ 'v', 'f', 'l', 'r', 9, 0, - /* 12435 */ 'c', 'h', 'l', 'r', 9, 0, - /* 12441 */ 'a', 'h', 'h', 'l', 'r', 9, 0, - /* 12448 */ 'a', 'l', 'h', 'h', 'l', 'r', 9, 0, - /* 12456 */ 's', 'l', 'h', 'h', 'l', 'r', 9, 0, - /* 12464 */ 's', 'h', 'h', 'l', 'r', 9, 0, - /* 12471 */ 'c', 'l', 'h', 'l', 'r', 9, 0, - /* 12478 */ 'm', 'l', 'r', 9, 0, - /* 12483 */ 'b', 'n', 'l', 'r', 9, 0, - /* 12489 */ 'v', 'l', 'r', 'l', 'r', 9, 0, - /* 12496 */ 'v', 's', 't', 'r', 'l', 'r', 9, 0, - /* 12504 */ 's', 'l', 'r', 9, 0, - /* 12509 */ 'v', 'l', 'r', 9, 0, - /* 12514 */ 'm', 'a', 'y', 'l', 'r', 9, 0, - /* 12521 */ 'm', 'y', 'l', 'r', 9, 0, - /* 12527 */ 'b', 'm', 'r', 9, 0, - /* 12532 */ 'b', 'n', 'm', 'r', 9, 0, - /* 12538 */ 'l', 'n', 'r', 9, 0, - /* 12543 */ 'b', 'o', 'r', 9, 0, - /* 12548 */ 'b', 'n', 'o', 'r', 9, 0, - /* 12554 */ 'b', 'p', 'r', 9, 0, - /* 12559 */ 'l', 'p', 'r', 9, 0, - /* 12564 */ 'b', 'n', 'p', 'r', 9, 0, - /* 12570 */ 'b', 'a', 's', 'r', 9, 0, - /* 12576 */ 's', 'f', 'a', 's', 'r', 9, 0, - /* 12583 */ 'm', 's', 'r', 9, 0, - /* 12588 */ 'b', 'c', 't', 'r', 9, 0, - /* 12594 */ 'e', 'c', 'c', 't', 'r', 9, 0, - /* 12601 */ 's', 'c', 'c', 't', 'r', 9, 0, - /* 12608 */ 'k', 'm', 'c', 't', 'r', 9, 0, - /* 12615 */ 'e', 'p', 'c', 't', 'r', 9, 0, - /* 12622 */ 's', 'p', 'c', 't', 'r', 9, 0, - /* 12629 */ 'q', 'a', 'd', 't', 'r', 9, 0, - /* 12636 */ 'c', 'd', 't', 'r', 9, 0, - /* 12642 */ 'd', 'd', 't', 'r', 9, 0, - /* 12648 */ 'c', 'e', 'd', 't', 'r', 9, 0, - /* 12655 */ 'e', 'e', 'd', 't', 'r', 9, 0, - /* 12662 */ 'i', 'e', 'd', 't', 'r', 9, 0, - /* 12669 */ 'l', 'e', 'd', 't', 'r', 9, 0, - /* 12676 */ 'c', 'f', 'd', 't', 'r', 9, 0, - /* 12683 */ 'c', 'l', 'f', 'd', 't', 'r', 9, 0, - /* 12691 */ 'c', 'g', 'd', 't', 'r', 9, 0, - /* 12698 */ 'c', 'l', 'g', 'd', 't', 'r', 9, 0, - /* 12706 */ 'f', 'i', 'd', 't', 'r', 9, 0, - /* 12713 */ 'k', 'd', 't', 'r', 9, 0, - /* 12719 */ 'm', 'd', 't', 'r', 9, 0, - /* 12725 */ 'r', 'r', 'd', 't', 'r', 9, 0, - /* 12732 */ 'c', 's', 'd', 't', 'r', 9, 0, - /* 12739 */ 'e', 's', 'd', 't', 'r', 9, 0, - /* 12746 */ 'l', 't', 'd', 't', 'r', 9, 0, - /* 12753 */ 'c', 'u', 'd', 't', 'r', 9, 0, - /* 12760 */ 'l', 'x', 'd', 't', 'r', 9, 0, - /* 12767 */ 'l', 'd', 'e', 't', 'r', 9, 0, - /* 12774 */ 'c', 'd', 'f', 't', 'r', 9, 0, - /* 12781 */ 'c', 'd', 'l', 'f', 't', 'r', 9, 0, - /* 12789 */ 'c', 'x', 'l', 'f', 't', 'r', 9, 0, - /* 12797 */ 'c', 'x', 'f', 't', 'r', 9, 0, - /* 12804 */ 'c', 'd', 'g', 't', 'r', 9, 0, - /* 12811 */ 'c', 'd', 'l', 'g', 't', 'r', 9, 0, - /* 12819 */ 'l', 'l', 'g', 't', 'r', 9, 0, - /* 12826 */ 'c', 'x', 'l', 'g', 't', 'r', 9, 0, - /* 12834 */ 'c', 'x', 'g', 't', 'r', 9, 0, - /* 12841 */ 'l', 't', 'r', 9, 0, - /* 12846 */ 't', 'r', 't', 'r', 9, 0, - /* 12852 */ 'c', 'd', 's', 't', 'r', 9, 0, - /* 12859 */ 'v', 'i', 's', 't', 'r', 9, 0, - /* 12866 */ 'c', 'x', 's', 't', 'r', 9, 0, - /* 12873 */ 'c', 'd', 'u', 't', 'r', 9, 0, - /* 12880 */ 'c', 'x', 'u', 't', 'r', 9, 0, - /* 12887 */ 'q', 'a', 'x', 't', 'r', 9, 0, - /* 12894 */ 'c', 'x', 't', 'r', 9, 0, - /* 12900 */ 'l', 'd', 'x', 't', 'r', 9, 0, - /* 12907 */ 'c', 'e', 'x', 't', 'r', 9, 0, - /* 12914 */ 'e', 'e', 'x', 't', 'r', 9, 0, - /* 12921 */ 'i', 'e', 'x', 't', 'r', 9, 0, - /* 12928 */ 'c', 'f', 'x', 't', 'r', 9, 0, - /* 12935 */ 'c', 'l', 'f', 'x', 't', 'r', 9, 0, - /* 12943 */ 'c', 'g', 'x', 't', 'r', 9, 0, - /* 12950 */ 'c', 'l', 'g', 'x', 't', 'r', 9, 0, - /* 12958 */ 'f', 'i', 'x', 't', 'r', 9, 0, - /* 12965 */ 'k', 'x', 't', 'r', 9, 0, - /* 12971 */ 'm', 'x', 't', 'r', 9, 0, - /* 12977 */ 'r', 'r', 'x', 't', 'r', 9, 0, - /* 12984 */ 'c', 's', 'x', 't', 'r', 9, 0, - /* 12991 */ 'e', 's', 'x', 't', 'r', 9, 0, - /* 12998 */ 'l', 't', 'x', 't', 'r', 9, 0, - /* 13005 */ 'c', 'u', 'x', 't', 'r', 9, 0, - /* 13012 */ 'a', 'u', 'r', 9, 0, - /* 13017 */ 's', 'u', 'r', 9, 0, - /* 13022 */ 'l', 'r', 'v', 'r', 9, 0, - /* 13028 */ 'a', 'w', 'r', 9, 0, - /* 13033 */ 's', 'w', 'r', 9, 0, - /* 13038 */ 'a', 'x', 'r', 9, 0, - /* 13043 */ 'l', 'c', 'x', 'r', 9, 0, - /* 13049 */ 'l', 'd', 'x', 'r', 9, 0, - /* 13055 */ 'l', 'e', 'x', 'r', 9, 0, - /* 13061 */ 'c', 'f', 'x', 'r', 9, 0, - /* 13067 */ 'c', 'g', 'x', 'r', 9, 0, - /* 13073 */ 'f', 'i', 'x', 'r', 9, 0, - /* 13079 */ 'l', 'x', 'r', 9, 0, - /* 13084 */ 'm', 'x', 'r', 9, 0, - /* 13089 */ 'l', 'n', 'x', 'r', 9, 0, - /* 13095 */ 'l', 'p', 'x', 'r', 9, 0, - /* 13101 */ 's', 'q', 'x', 'r', 9, 0, - /* 13107 */ 's', 'x', 'r', 9, 0, - /* 13112 */ 'l', 't', 'x', 'r', 9, 0, - /* 13118 */ 'l', 'z', 'x', 'r', 9, 0, - /* 13124 */ 'm', 'a', 'y', 'r', 9, 0, - /* 13130 */ 'm', 'y', 'r', 9, 0, - /* 13135 */ 'b', 'z', 'r', 9, 0, - /* 13140 */ 'b', 'n', 'z', 'r', 9, 0, - /* 13146 */ 'b', 'a', 's', 9, 0, - /* 13151 */ 'l', 'f', 'a', 's', 9, 0, - /* 13157 */ 'b', 'r', 'a', 's', 9, 0, - /* 13163 */ 'v', 's', 't', 'r', 'c', 'b', 's', 9, 0, - /* 13172 */ 'v', 'f', 'c', 'e', 'd', 'b', 's', 9, 0, - /* 13181 */ 'w', 'f', 'c', 'e', 'd', 'b', 's', 9, 0, - /* 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'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, - /* 15255 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, - /* 15278 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, - /* 15301 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, - /* 15323 */ 's', 'a', 'm', '3', '1', 0, - /* 15329 */ 't', 'r', 'a', 'p', '2', 0, - /* 15335 */ 's', 'a', 'm', '2', '4', 0, - /* 15341 */ 's', 'a', 'm', '6', '4', 0, - /* 15347 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, - /* 15360 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, - /* 15367 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, - /* 15377 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, - /* 15387 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, - /* 15402 */ 'c', 'i', 'b', 0, - /* 15406 */ 'c', 'g', 'i', 'b', 0, - /* 15411 */ 'c', 'l', 'g', 'i', 'b', 0, - /* 15417 */ 'c', 'l', 'i', 'b', 0, - /* 15422 */ 'p', 'a', 'l', 'b', 0, - /* 15427 */ 'p', 't', 'l', 'b', 0, - /* 15432 */ 'c', 'r', 'b', 0, - /* 15436 */ 'c', 'g', 'r', 'b', 0, - /* 15441 */ 'c', 'l', 'g', 'r', 'b', 0, - /* 15447 */ 'c', 'l', 'r', 'b', 0, - /* 15452 */ 'p', 'c', 'c', 0, - /* 15456 */ 'l', 'o', 'c', 0, - /* 15460 */ 's', 't', 'o', 'c', 0, - /* 15465 */ 't', 'e', 'n', 'd', 0, - /* 15470 */ 'p', 't', 'f', 'f', 0, - /* 15475 */ 's', 'c', 'k', 'p', 'f', 0, - /* 15481 */ 'l', 'o', 'c', 'g', 0, - /* 15486 */ 's', 't', 'o', 'c', 'g', 0, - /* 15492 */ 'j', 'g', 0, - /* 15495 */ 'c', 's', 'c', 'h', 0, - /* 15500 */ 'h', 's', 'c', 'h', 0, - /* 15505 */ 'r', 's', 'c', 'h', 0, - /* 15510 */ 'x', 's', 'c', 'h', 0, - /* 15515 */ 'l', 'o', 'c', 'f', 'h', 0, - /* 15521 */ 's', 't', 'o', 'c', 'f', 'h', 0, - /* 15528 */ 'b', 'i', 0, - /* 15531 */ 'l', 'o', 'c', 'h', 'i', 0, - /* 15537 */ 'l', 'o', 'c', 'g', 'h', 'i', 0, - /* 15544 */ 'l', 'o', 'c', 'h', 'h', 'i', 0, - /* 15551 */ 'c', 'i', 'j', 0, - /* 15555 */ 'c', 'g', 'i', 'j', 0, - /* 15560 */ 'c', 'l', 'g', 'i', 'j', 0, - /* 15566 */ 'c', 'l', 'i', 'j', 0, - /* 15571 */ 'c', 'r', 'j', 0, - /* 15575 */ 'c', 'g', 'r', 'j', 0, - /* 15580 */ 'c', 'l', 'g', 'r', 'j', 0, - /* 15586 */ 'c', 'l', 'r', 'j', 0, - /* 15591 */ 'i', 'p', 'k', 0, - /* 15595 */ 's', 'a', 'l', 0, - /* 15599 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, - /* 15613 */ 't', 'a', 'm', 0, - /* 15617 */ 's', 'c', 'h', 'm', 0, - /* 15622 */ 'p', 'c', 'k', 'm', 'o', 0, - /* 15628 */ 'p', 'f', 'p', 'o', 0, - /* 15633 */ 'r', 'c', 'h', 'p', 0, - /* 15638 */ 'l', 'o', 'c', 'r', 0, - /* 15643 */ 'l', 'o', 'c', 'g', 'r', 0, - /* 15649 */ 'l', 'o', 'c', 'f', 'h', 'r', 0, - /* 15656 */ 'p', 'r', 0, - /* 15659 */ 'c', 'l', 'g', 't', 0, - /* 15664 */ 'c', 'i', 't', 0, - /* 15668 */ 'c', 'l', 'f', 'i', 't', 0, - /* 15674 */ 'c', 'g', 'i', 't', 0, - /* 15679 */ 'c', 'l', 'g', 'i', 't', 0, - /* 15685 */ 'c', 'l', 't', 0, - /* 15689 */ 'u', 'p', 't', 0, - /* 15693 */ 'c', 'r', 't', 0, - /* 15697 */ 'c', 'g', 'r', 't', 0, - /* 15702 */ 'c', 'l', 'g', 'r', 't', 0, - /* 15708 */ 'c', 'l', 'r', 't', 0, - }; -#endif + /* 0 */ "cu21\t\0" + /* 6 */ "cu41\t\0" + /* 12 */ "cu12\t\0" + /* 18 */ "cu42\t\0" + /* 24 */ "cu14\t\0" + /* 30 */ "cu24\t\0" + /* 36 */ "trap4\t\0" + /* 43 */ "laa\t\0" + /* 48 */ "slda\t\0" + /* 54 */ "srda\t\0" + /* 60 */ "esea\t\0" + /* 66 */ "lptea\t\0" + /* 73 */ "vfa\t\0" + /* 78 */ "siga\t\0" + /* 84 */ "ecpga\t\0" + /* 91 */ "unpka\t\0" + /* 98 */ "spka\t\0" + /* 104 */ "sla\t\0" + /* 109 */ "vgfma\t\0" + /* 116 */ "vfma\t\0" + /* 122 */ "kma\t\0" + /* 127 */ "vfnma\t\0" + /* 134 */ "ppa\t\0" + /* 139 */ "ledbra\t\0" + /* 147 */ "cfdbra\t\0" + /* 155 */ "cgdbra\t\0" + /* 163 */ "fidbra\t\0" + /* 171 */ "cfebra\t\0" + /* 179 */ "cgebra\t\0" + /* 187 */ "fiebra\t\0" + /* 195 */ "cdfbra\t\0" + /* 203 */ "cefbra\t\0" + /* 211 */ "cxfbra\t\0" + /* 219 */ "cdgbra\t\0" + /* 227 */ "cegbra\t\0" + /* 235 */ "cxgbra\t\0" + /* 243 */ "ldxbra\t\0" + /* 251 */ "lexbra\t\0" + /* 259 */ "cfxbra\t\0" + /* 267 */ "cgxbra\t\0" + /* 275 */ "fixbra\t\0" + /* 283 */ "lra\t\0" + /* 288 */ "vesra\t\0" + /* 295 */ "vsra\t\0" + /* 301 */ "adtra\t\0" + /* 308 */ "ddtra\t\0" + /* 315 */ "cgdtra\t\0" + /* 323 */ "mdtra\t\0" + /* 330 */ "sdtra\t\0" + /* 337 */ "cdgtra\t\0" + /* 345 */ "cxgtra\t\0" + /* 353 */ "axtra\t\0" + /* 360 */ "dxtra\t\0" + /* 367 */ "cgxtra\t\0" + /* 375 */ "mxtra\t\0" + /* 382 */ "sxtra\t\0" + /* 389 */ "lura\t\0" + /* 395 */ "stura\t\0" + /* 402 */ "bsa\t\0" + /* 407 */ "kdsa\t\0" + /* 413 */ "esta\t\0" + /* 419 */ "msta\t\0" + /* 425 */ "va\t\0" + /* 429 */ "cpya\t\0" + /* 435 */ "vgfmab\t\0" + /* 443 */ "vesrab\t\0" + /* 451 */ "vsrab\t\0" + /* 458 */ "vab\t\0" + /* 463 */ "lcbb\t\0" + /* 469 */ "vlbb\t\0" + /* 475 */ "vaccb\t\0" + /* 482 */ "vecb\t\0" + /* 488 */ "vlcb\t\0" + /* 494 */ "vstrcb\t\0" + /* 502 */ "vfadb\t\0" + /* 509 */ "wfadb\t\0" + /* 516 */ "vfmadb\t\0" + /* 524 */ "wfmadb\t\0" + /* 532 */ "vfnmadb\t\0" + /* 541 */ "wfnmadb\t\0" + /* 550 */ "wfcdb\t\0" + /* 557 */ "vflcdb\t\0" + /* 565 */ "wflcdb\t\0" + /* 573 */ "tcdb\t\0" + /* 579 */ "vfddb\t\0" + /* 586 */ "wfddb\t\0" + /* 593 */ "vfcedb\t\0" + /* 601 */ "wfcedb\t\0" + /* 609 */ "vfchedb\t\0" + /* 618 */ "wfchedb\t\0" + /* 627 */ "vfkhedb\t\0" + /* 636 */ "wfkhedb\t\0" + /* 645 */ "vfkedb\t\0" + /* 653 */ "wfkedb\t\0" + /* 661 */ "vledb\t\0" + /* 668 */ "wledb\t\0" + /* 675 */ "vcgdb\t\0" + /* 682 */ "wcgdb\t\0" + /* 689 */ "vclgdb\t\0" + /* 697 */ "wclgdb\t\0" + /* 705 */ "vfchdb\t\0" + /* 713 */ "wfchdb\t\0" + /* 721 */ "vfkhdb\t\0" + /* 729 */ "wfkhdb\t\0" + /* 737 */ "vftcidb\t\0" + /* 746 */ "wftcidb\t\0" + /* 755 */ "vfidb\t\0" + /* 762 */ "wfidb\t\0" + /* 769 */ "wfkdb\t\0" + /* 776 */ "vsldb\t\0" + /* 783 */ "vfmdb\t\0" + /* 790 */ "wfmdb\t\0" + /* 797 */ "vfmindb\t\0" + /* 806 */ "wfmindb\t\0" + /* 815 */ "vflndb\t\0" + /* 823 */ "wflndb\t\0" + /* 831 */ "vfpsodb\t\0" + /* 840 */ "wfpsodb\t\0" + /* 849 */ "vflpdb\t\0" + /* 857 */ "wflpdb\t\0" + /* 865 */ "vfsqdb\t\0" + /* 873 */ "wfsqdb\t\0" + /* 881 */ "vfsdb\t\0" + /* 888 */ "wfsdb\t\0" + /* 895 */ "vfmsdb\t\0" + /* 903 */ "wfmsdb\t\0" + /* 911 */ "vfnmsdb\t\0" + /* 920 */ "wfnmsdb\t\0" + /* 929 */ "vfmaxdb\t\0" + /* 938 */ "wfmaxdb\t\0" + /* 947 */ "lxdb\t\0" + /* 953 */ "mxdb\t\0" + /* 959 */ "vfaeb\t\0" + /* 966 */ "vmaeb\t\0" + /* 973 */ "tceb\t\0" + /* 979 */ "vldeb\t\0" + /* 986 */ "wldeb\t\0" + /* 993 */ "mdeb\t\0" + /* 999 */ "vfeeb\t\0" + /* 1006 */ "meeb\t\0" + /* 1012 */ "vcfeb\t\0" + /* 1019 */ "wcfeb\t\0" + /* 1026 */ "vclfeb\t\0" + /* 1034 */ "wclfeb\t\0" + /* 1042 */ "keb\t\0" + /* 1047 */ "vmaleb\t\0" + /* 1055 */ "vmleb\t\0" + /* 1062 */ "vleb\t\0" + /* 1068 */ "vmeb\t\0" + /* 1074 */ "vfeneb\t\0" + /* 1082 */ "sqeb\t\0" + /* 1088 */ "mseb\t\0" + /* 1094 */ "vsteb\t\0" + /* 1101 */ "lxeb\t\0" + /* 1107 */ "vcefb\t\0" + /* 1114 */ "wcefb\t\0" + /* 1121 */ "vcelfb\t\0" + /* 1129 */ "wcelfb\t\0" + /* 1137 */ "vcdgb\t\0" + /* 1144 */ "wcdgb\t\0" + /* 1151 */ "vsegb\t\0" + /* 1158 */ "vcdlgb\t\0" + /* 1166 */ "wcdlgb\t\0" + /* 1174 */ "vavgb\t\0" + /* 1181 */ "vlvgb\t\0" + /* 1188 */ "vmahb\t\0" + /* 1195 */ "vchb\t\0" + /* 1201 */ "vmalhb\t\0" + /* 1209 */ "vmlhb\t\0" + /* 1216 */ "vuplhb\t\0" + /* 1224 */ "vmhb\t\0" + /* 1230 */ "vuphb\t\0" + /* 1237 */ "vmrhb\t\0" + /* 1244 */ "vscbib\t\0" + /* 1252 */ "cib\t\0" + /* 1257 */ "vleib\t\0" + /* 1264 */ "cgib\t\0" + /* 1270 */ "clgib\t\0" + /* 1277 */ "clib\t\0" + /* 1283 */ "vrepib\t\0" + /* 1291 */ "vmalb\t\0" + /* 1298 */ "veclb\t\0" + /* 1305 */ "vavglb\t\0" + /* 1313 */ "vchlb\t\0" + /* 1320 */ "vupllb\t\0" + /* 1328 */ "verllb\t\0" + /* 1336 */ "vmlb\t\0" + /* 1342 */ "vmnlb\t\0" + /* 1349 */ "vuplb\t\0" + /* 1356 */ "vmrlb\t\0" + /* 1363 */ "vesrlb\t\0" + /* 1371 */ "vsrlb\t\0" + /* 1378 */ "veslb\t\0" + /* 1385 */ "vslb\t\0" + /* 1391 */ "vmxlb\t\0" + /* 1398 */ "vgfmb\t\0" + /* 1405 */ "vgmb\t\0" + /* 1411 */ "verimb\t\0" + /* 1419 */ "srnmb\t\0" + /* 1426 */ "vsumb\t\0" + /* 1433 */ "vmnb\t\0" + /* 1439 */ "vmaob\t\0" + /* 1446 */ "vmalob\t\0" + /* 1454 */ "vmlob\t\0" + /* 1461 */ "vmob\t\0" + /* 1467 */ "vlrepb\t\0" + /* 1475 */ "vrepb\t\0" + /* 1482 */ "vlpb\t\0" + /* 1488 */ "vceqb\t\0" + /* 1495 */ "crb\t\0" + /* 1500 */ "cgrb\t\0" + /* 1506 */ "clgrb\t\0" + /* 1513 */ "clrb\t\0" + /* 1519 */ "vistrb\t\0" + /* 1527 */ "vfasb\t\0" + /* 1534 */ "wfasb\t\0" + /* 1541 */ "vfmasb\t\0" + /* 1549 */ "wfmasb\t\0" + /* 1557 */ "vfnmasb\t\0" + /* 1566 */ "wfnmasb\t\0" + /* 1575 */ "wfcsb\t\0" + /* 1582 */ "vflcsb\t\0" + /* 1590 */ "wflcsb\t\0" + /* 1598 */ "vfdsb\t\0" + /* 1605 */ "wfdsb\t\0" + /* 1612 */ "vfcesb\t\0" + /* 1620 */ "wfcesb\t\0" + /* 1628 */ "vfchesb\t\0" + /* 1637 */ "wfchesb\t\0" + /* 1646 */ "vfkhesb\t\0" + /* 1655 */ "wfkhesb\t\0" + /* 1664 */ "vfkesb\t\0" + /* 1672 */ "wfkesb\t\0" + /* 1680 */ "vfchsb\t\0" + /* 1688 */ "wfchsb\t\0" + /* 1696 */ "vfkhsb\t\0" + /* 1704 */ "wfkhsb\t\0" + /* 1712 */ "vftcisb\t\0" + /* 1721 */ "wftcisb\t\0" + /* 1730 */ "vfisb\t\0" + /* 1737 */ "wfisb\t\0" + /* 1744 */ "wfksb\t\0" + /* 1751 */ "vfmsb\t\0" + /* 1758 */ "wfmsb\t\0" + /* 1765 */ "vfminsb\t\0" + /* 1774 */ "wfminsb\t\0" + /* 1783 */ "vflnsb\t\0" + /* 1791 */ "wflnsb\t\0" + /* 1799 */ "vfpsosb\t\0" + /* 1808 */ "wfpsosb\t\0" + /* 1817 */ "vflpsb\t\0" + /* 1825 */ "wflpsb\t\0" + /* 1833 */ "vfsqsb\t\0" + /* 1841 */ "wfsqsb\t\0" + /* 1849 */ "vstrsb\t\0" + /* 1857 */ "vfssb\t\0" + /* 1864 */ "wfssb\t\0" + /* 1871 */ "vfmssb\t\0" + /* 1879 */ "wfmssb\t\0" + /* 1887 */ "vfnmssb\t\0" + /* 1896 */ "wfnmssb\t\0" + /* 1905 */ "vsb\t\0" + /* 1910 */ "vfmaxsb\t\0" + /* 1919 */ "wfmaxsb\t\0" + /* 1928 */ "vpopctb\t\0" + /* 1937 */ "vesravb\t\0" + /* 1946 */ "vcvb\t\0" + /* 1952 */ "vlgvb\t\0" + /* 1959 */ "verllvb\t\0" + /* 1968 */ "vesrlvb\t\0" + /* 1977 */ "veslvb\t\0" + /* 1985 */ "wfaxb\t\0" + /* 1992 */ "wfmaxb\t\0" + /* 2000 */ "wfnmaxb\t\0" + /* 2009 */ "wfcxb\t\0" + /* 2016 */ "wflcxb\t\0" + /* 2024 */ "tcxb\t\0" + /* 2030 */ "wfdxb\t\0" + /* 2037 */ "wfcexb\t\0" + /* 2045 */ "wfchexb\t\0" + /* 2054 */ "wfkhexb\t\0" + /* 2063 */ "wfkexb\t\0" + /* 2071 */ "wfchxb\t\0" + /* 2079 */ "wfkhxb\t\0" + /* 2087 */ "wftcixb\t\0" + /* 2096 */ "wfixb\t\0" + /* 2103 */ "wfkxb\t\0" + /* 2110 */ "wfmxb\t\0" + /* 2117 */ "vmxb\t\0" + /* 2123 */ "wfminxb\t\0" + /* 2132 */ "wflnxb\t\0" + /* 2140 */ "wfpsoxb\t\0" + /* 2149 */ "wflpxb\t\0" + /* 2157 */ "wfsqxb\t\0" + /* 2165 */ "wfsxb\t\0" + /* 2172 */ "wfmsxb\t\0" + /* 2180 */ "wfnmsxb\t\0" + /* 2189 */ "wfmaxxb\t\0" + /* 2198 */ "vstrczb\t\0" + /* 2207 */ "vfaezb\t\0" + /* 2215 */ "vfeezb\t\0" + /* 2223 */ "vllezb\t\0" + /* 2231 */ "vfenezb\t\0" + /* 2240 */ "vclzb\t\0" + /* 2247 */ "vstrszb\t\0" + /* 2256 */ "vctzb\t\0" + /* 2263 */ "iac\t\0" + /* 2268 */ "kmac\t\0" + /* 2274 */ "sac\t\0" + /* 2279 */ "vac\t\0" + /* 2284 */ "bc\t\0" + /* 2288 */ "vacc\t\0" + /* 2294 */ "vaccc\t\0" + /* 2301 */ "dfltcc\t\0" + /* 2309 */ "vec\t\0" + /* 2314 */ "cfc\t\0" + /* 2319 */ "wfc\t\0" + /* 2324 */ "llgc\t\0" + /* 2330 */ "msgc\t\0" + /* 2336 */ "bic\t\0" + /* 2341 */ "sckc\t\0" + /* 2347 */ "stckc\t\0" + /* 2354 */ "msgrkc\t\0" + /* 2362 */ "msrkc\t\0" + /* 2369 */ "alc\t\0" + /* 2374 */ "clc\t\0" + /* 2379 */ "llc\t\0" + /* 2384 */ "vlc\t\0" + /* 2389 */ "kmc\t\0" + /* 2394 */ "tbeginc\t\0" + /* 2403 */ "vnc\t\0" + /* 2408 */ "loc\t\0" + /* 2413 */ "stoc\t\0" + /* 2419 */ "voc\t\0" + /* 2424 */ "efpc\t\0" + /* 2430 */ "lfpc\t\0" + /* 2436 */ "sfpc\t\0" + /* 2442 */ "stfpc\t\0" + /* 2449 */ "brc\t\0" + /* 2454 */ "vstrc\t\0" + /* 2461 */ "lgsc\t\0" + /* 2467 */ "stgsc\t\0" + /* 2474 */ "msc\t\0" + /* 2479 */ "cmpsc\t\0" + /* 2486 */ "stc\t\0" + /* 2491 */ "mvc\t\0" + /* 2496 */ "svc\t\0" + /* 2501 */ "xc\t\0" + /* 2505 */ "mad\t\0" + /* 2510 */ "cd\t\0" + /* 2514 */ "dd\t\0" + /* 2518 */ "vled\t\0" + /* 2524 */ "pfd\t\0" + /* 2529 */ "vfd\t\0" + /* 2534 */ "vcgd\t\0" + /* 2540 */ "vclgd\t\0" + /* 2547 */ "wflld\t\0" + /* 2554 */ "vsld\t\0" + /* 2560 */ "kimd\t\0" + /* 2566 */ "klmd\t\0" + /* 2572 */ "etnd\t\0" + /* 2578 */ "lpd\t\0" + /* 2583 */ "sqd\t\0" + /* 2588 */ "vflrd\t\0" + /* 2595 */ "wflrd\t\0" + /* 2602 */ "vsrd\t\0" + /* 2608 */ "msd\t\0" + /* 2613 */ "std\t\0" + /* 2618 */ "vcvd\t\0" + /* 2624 */ "lxd\t\0" + /* 2629 */ "mxd\t\0" + /* 2634 */ "vfae\t\0" + /* 2640 */ "lae\t\0" + /* 2645 */ "vmae\t\0" + /* 2651 */ "cibe\t\0" + /* 2657 */ "cgibe\t\0" + /* 2664 */ "clgibe\t\0" + /* 2672 */ "clibe\t\0" + /* 2679 */ "crbe\t\0" + /* 2685 */ "cgrbe\t\0" + /* 2692 */ "clgrbe\t\0" + /* 2700 */ "clrbe\t\0" + /* 2707 */ "rrbe\t\0" + /* 2713 */ "trace\t\0" + /* 2720 */ "vfce\t\0" + /* 2726 */ "loce\t\0" + /* 2732 */ "stoce\t\0" + /* 2739 */ "vlde\t\0" + /* 2745 */ "mde\t\0" + /* 2750 */ "vfee\t\0" + /* 2756 */ "mee\t\0" + /* 2761 */ "locge\t\0" + /* 2768 */ "stocge\t\0" + /* 2776 */ "jge\t\0" + /* 2781 */ "cibhe\t\0" + /* 2788 */ "cgibhe\t\0" + /* 2796 */ "clgibhe\t\0" + /* 2805 */ "clibhe\t\0" + /* 2813 */ "crbhe\t\0" + /* 2820 */ "cgrbhe\t\0" + /* 2828 */ "clgrbhe\t\0" + /* 2837 */ "clrbhe\t\0" + /* 2845 */ "vfche\t\0" + /* 2852 */ "loche\t\0" + /* 2859 */ "stoche\t\0" + /* 2867 */ "locfhe\t\0" + /* 2875 */ "stocfhe\t\0" + /* 2884 */ "locghe\t\0" + /* 2892 */ "stocghe\t\0" + /* 2901 */ "jghe\t\0" + /* 2907 */ "locfhhe\t\0" + /* 2916 */ "stocfhhe\t\0" + /* 2926 */ "bihe\t\0" + /* 2932 */ "lochihe\t\0" + /* 2941 */ "locghihe\t\0" + /* 2951 */ "lochhihe\t\0" + /* 2961 */ "cijhe\t\0" + /* 2968 */ "cgijhe\t\0" + /* 2976 */ "clgijhe\t\0" + /* 2985 */ "clijhe\t\0" + /* 2993 */ "crjhe\t\0" + /* 3000 */ "cgrjhe\t\0" + /* 3008 */ "clgrjhe\t\0" + /* 3017 */ "clrjhe\t\0" + /* 3025 */ "cibnhe\t\0" + /* 3033 */ "cgibnhe\t\0" + /* 3042 */ "clgibnhe\t\0" + /* 3052 */ "clibnhe\t\0" + /* 3061 */ "crbnhe\t\0" + /* 3069 */ "cgrbnhe\t\0" + /* 3078 */ "clgrbnhe\t\0" + /* 3088 */ "clrbnhe\t\0" + /* 3097 */ "locnhe\t\0" + /* 3105 */ "stocnhe\t\0" + /* 3114 */ "locgnhe\t\0" + /* 3123 */ "stocgnhe\t\0" + /* 3133 */ "jgnhe\t\0" + /* 3140 */ "locfhnhe\t\0" + /* 3150 */ "stocfhnhe\t\0" + /* 3161 */ "binhe\t\0" + /* 3168 */ "lochinhe\t\0" + /* 3178 */ "locghinhe\t\0" + /* 3189 */ "lochhinhe\t\0" + /* 3200 */ "cijnhe\t\0" + /* 3208 */ "cgijnhe\t\0" + /* 3217 */ "clgijnhe\t\0" + /* 3227 */ "clijnhe\t\0" + /* 3236 */ "crjnhe\t\0" + /* 3244 */ "cgrjnhe\t\0" + /* 3253 */ "clgrjnhe\t\0" + /* 3263 */ "clrjnhe\t\0" + /* 3272 */ "locrnhe\t\0" + /* 3281 */ "locgrnhe\t\0" + /* 3291 */ "selgrnhe\t\0" + /* 3301 */ "locfhrnhe\t\0" + /* 3312 */ "selfhrnhe\t\0" + /* 3323 */ "selrnhe\t\0" + /* 3332 */ "clgtnhe\t\0" + /* 3341 */ "citnhe\t\0" + /* 3349 */ "clfitnhe\t\0" + /* 3359 */ "cgitnhe\t\0" + /* 3368 */ "clgitnhe\t\0" + /* 3378 */ "cltnhe\t\0" + /* 3386 */ "crtnhe\t\0" + /* 3394 */ "cgrtnhe\t\0" + /* 3403 */ "clgrtnhe\t\0" + /* 3413 */ "clrtnhe\t\0" + /* 3422 */ "locrhe\t\0" + /* 3430 */ "locgrhe\t\0" + /* 3439 */ "selgrhe\t\0" + /* 3448 */ "locfhrhe\t\0" + /* 3458 */ "selfhrhe\t\0" + /* 3468 */ "selrhe\t\0" + /* 3476 */ "clgthe\t\0" + /* 3484 */ "cithe\t\0" + /* 3491 */ "clfithe\t\0" + /* 3500 */ "cgithe\t\0" + /* 3508 */ "clgithe\t\0" + /* 3517 */ "clthe\t\0" + /* 3524 */ "crthe\t\0" + /* 3531 */ "cgrthe\t\0" + /* 3539 */ "clgrthe\t\0" + /* 3548 */ "clrthe\t\0" + /* 3556 */ "bie\t\0" + /* 3561 */ "lochie\t\0" + /* 3569 */ "locghie\t\0" + /* 3578 */ "lochhie\t\0" + /* 3587 */ "sie\t\0" + /* 3592 */ "cije\t\0" + /* 3598 */ "cgije\t\0" + /* 3605 */ "clgije\t\0" + /* 3613 */ "clije\t\0" + /* 3620 */ "crje\t\0" + /* 3626 */ "cgrje\t\0" + /* 3633 */ "clgrje\t\0" + /* 3641 */ "clrje\t\0" + /* 3648 */ "stcke\t\0" + /* 3655 */ "iske\t\0" + /* 3661 */ "sske\t\0" + /* 3667 */ "vmale\t\0" + /* 3674 */ "cible\t\0" + /* 3681 */ "cgible\t\0" + /* 3689 */ "clgible\t\0" + /* 3698 */ "clible\t\0" + /* 3706 */ "crble\t\0" + /* 3713 */ "cgrble\t\0" + /* 3721 */ "clgrble\t\0" + /* 3730 */ "clrble\t\0" + /* 3738 */ "clcle\t\0" + /* 3745 */ "locle\t\0" + /* 3752 */ "stocle\t\0" + /* 3760 */ "mvcle\t\0" + /* 3767 */ "stfle\t\0" + /* 3774 */ "locgle\t\0" + /* 3782 */ "stocgle\t\0" + /* 3791 */ "jgle\t\0" + /* 3797 */ "locfhle\t\0" + /* 3806 */ "stocfhle\t\0" + /* 3816 */ "bile\t\0" + /* 3822 */ "lochile\t\0" + /* 3831 */ "locghile\t\0" + /* 3841 */ "lochhile\t\0" + /* 3851 */ "cijle\t\0" + /* 3858 */ "cgijle\t\0" + /* 3866 */ "clgijle\t\0" + /* 3875 */ "clijle\t\0" + /* 3883 */ "crjle\t\0" + /* 3890 */ "cgrjle\t\0" + /* 3898 */ "clgrjle\t\0" + /* 3907 */ "clrjle\t\0" + /* 3915 */ "vmle\t\0" + /* 3921 */ "cibnle\t\0" + /* 3929 */ "cgibnle\t\0" + /* 3938 */ "clgibnle\t\0" + /* 3948 */ "clibnle\t\0" + /* 3957 */ "crbnle\t\0" + /* 3965 */ "cgrbnle\t\0" + /* 3974 */ "clgrbnle\t\0" + /* 3984 */ "clrbnle\t\0" + /* 3993 */ "locnle\t\0" + /* 4001 */ "stocnle\t\0" + /* 4010 */ "locgnle\t\0" + /* 4019 */ "stocgnle\t\0" + /* 4029 */ "jgnle\t\0" + /* 4036 */ "locfhnle\t\0" + /* 4046 */ "stocfhnle\t\0" + /* 4057 */ "binle\t\0" + /* 4064 */ "lochinle\t\0" + /* 4074 */ "locghinle\t\0" + /* 4085 */ "lochhinle\t\0" + /* 4096 */ "cijnle\t\0" + /* 4104 */ "cgijnle\t\0" + /* 4113 */ "clgijnle\t\0" + /* 4123 */ "clijnle\t\0" + /* 4132 */ "crjnle\t\0" + /* 4140 */ "cgrjnle\t\0" + /* 4149 */ "clgrjnle\t\0" + /* 4159 */ "clrjnle\t\0" + /* 4168 */ "locrnle\t\0" + /* 4177 */ "locgrnle\t\0" + /* 4187 */ "selgrnle\t\0" + /* 4197 */ "locfhrnle\t\0" + /* 4208 */ "selfhrnle\t\0" + /* 4219 */ "selrnle\t\0" + /* 4228 */ "clgtnle\t\0" + /* 4237 */ "citnle\t\0" + /* 4245 */ "clfitnle\t\0" + /* 4255 */ "cgitnle\t\0" + /* 4264 */ "clgitnle\t\0" + /* 4274 */ "cltnle\t\0" + /* 4282 */ "crtnle\t\0" + /* 4290 */ "cgrtnle\t\0" + /* 4299 */ "clgrtnle\t\0" + /* 4309 */ "clrtnle\t\0" + /* 4318 */ "locrle\t\0" + /* 4326 */ "locgrle\t\0" + /* 4335 */ "selgrle\t\0" + /* 4344 */ "locfhrle\t\0" + /* 4354 */ "selfhrle\t\0" + /* 4364 */ "selrle\t\0" + /* 4372 */ "clgtle\t\0" + /* 4380 */ "citle\t\0" + /* 4387 */ "clfitle\t\0" + /* 4396 */ "cgitle\t\0" + /* 4404 */ "clgitle\t\0" + /* 4413 */ "cltle\t\0" + /* 4420 */ "crtle\t\0" + /* 4427 */ "cgrtle\t\0" + /* 4435 */ "clgrtle\t\0" + /* 4444 */ "clrtle\t\0" + /* 4452 */ "bxle\t\0" + /* 4458 */ "brxle\t\0" + /* 4465 */ "vme\t\0" + /* 4470 */ "cibne\t\0" + /* 4477 */ "cgibne\t\0" + /* 4485 */ "clgibne\t\0" + /* 4494 */ "clibne\t\0" + /* 4502 */ "crbne\t\0" + /* 4509 */ "cgrbne\t\0" + /* 4517 */ "clgrbne\t\0" + /* 4526 */ "clrbne\t\0" + /* 4534 */ "locne\t\0" + /* 4541 */ "stocne\t\0" + /* 4549 */ "vfene\t\0" + /* 4556 */ "locgne\t\0" + /* 4564 */ "stocgne\t\0" + /* 4573 */ "jgne\t\0" + /* 4579 */ "locfhne\t\0" + /* 4588 */ "stocfhne\t\0" + /* 4598 */ "bine\t\0" + /* 4604 */ "lochine\t\0" + /* 4613 */ "locghine\t\0" + /* 4623 */ "lochhine\t\0" + /* 4633 */ "cijne\t\0" + /* 4640 */ "cgijne\t\0" + /* 4648 */ "clgijne\t\0" + /* 4657 */ "clijne\t\0" + /* 4665 */ "crjne\t\0" + /* 4672 */ "cgrjne\t\0" + /* 4680 */ "clgrjne\t\0" + /* 4689 */ "clrjne\t\0" + /* 4697 */ "vone\t\0" + /* 4703 */ "locrne\t\0" + /* 4711 */ "locgrne\t\0" + /* 4720 */ "selgrne\t\0" + /* 4729 */ "locfhrne\t\0" + /* 4739 */ "selfhrne\t\0" + /* 4749 */ "selrne\t\0" + /* 4757 */ "clgtne\t\0" + /* 4765 */ "citne\t\0" + /* 4772 */ "clfitne\t\0" + /* 4781 */ "cgitne\t\0" + /* 4789 */ "clgitne\t\0" + /* 4798 */ "cltne\t\0" + /* 4805 */ "crtne\t\0" + /* 4812 */ "cgrtne\t\0" + /* 4820 */ "clgrtne\t\0" + /* 4829 */ "clrtne\t\0" + /* 4837 */ "sqe\t\0" + /* 4842 */ "locre\t\0" + /* 4849 */ "locgre\t\0" + /* 4857 */ "selgre\t\0" + /* 4865 */ "locfhre\t\0" + /* 4874 */ "selfhre\t\0" + /* 4883 */ "selre\t\0" + /* 4890 */ "trtre\t\0" + /* 4897 */ "mse\t\0" + /* 4902 */ "cuse\t\0" + /* 4908 */ "idte\t\0" + /* 4914 */ "crdte\t\0" + /* 4921 */ "clgte\t\0" + /* 4928 */ "cite\t\0" + /* 4934 */ "clfite\t\0" + /* 4942 */ "cgite\t\0" + /* 4949 */ "clgite\t\0" + /* 4957 */ "clte\t\0" + /* 4963 */ "ipte\t\0" + /* 4969 */ "crte\t\0" + /* 4975 */ "cgrte\t\0" + /* 4982 */ "clgrte\t\0" + /* 4990 */ "clrte\t\0" + /* 4997 */ "trte\t\0" + /* 5003 */ "ste\t\0" + /* 5008 */ "lpswe\t\0" + /* 5015 */ "lxe\t\0" + /* 5020 */ "vllebrze\t\0" + /* 5030 */ "vgfmaf\t\0" + /* 5038 */ "vesraf\t\0" + /* 5046 */ "vaf\t\0" + /* 5051 */ "sacf\t\0" + /* 5057 */ "vaccf\t\0" + /* 5064 */ "vecf\t\0" + /* 5070 */ "vlcf\t\0" + /* 5076 */ "vstrcf\t\0" + /* 5084 */ "vfaef\t\0" + /* 5091 */ "vmaef\t\0" + /* 5098 */ "vscef\t\0" + /* 5105 */ "vfeef\t\0" + /* 5112 */ "vgef\t\0" + /* 5118 */ "vmalef\t\0" + /* 5126 */ "vmlef\t\0" + /* 5133 */ "vlef\t\0" + /* 5139 */ "vmef\t\0" + /* 5145 */ "vfenef\t\0" + /* 5153 */ "vstef\t\0" + /* 5160 */ "agf\t\0" + /* 5165 */ "cgf\t\0" + /* 5170 */ "vsegf\t\0" + /* 5177 */ "algf\t\0" + /* 5183 */ "clgf\t\0" + /* 5189 */ "llgf\t\0" + /* 5195 */ "slgf\t\0" + /* 5201 */ "vsumgf\t\0" + /* 5209 */ "llzrgf\t\0" + /* 5217 */ "dsgf\t\0" + /* 5223 */ "msgf\t\0" + /* 5229 */ "ltgf\t\0" + /* 5235 */ "vavgf\t\0" + /* 5242 */ "vlvgf\t\0" + /* 5249 */ "vmahf\t\0" + /* 5256 */ "vchf\t\0" + /* 5262 */ "iihf\t\0" + /* 5268 */ "llihf\t\0" + /* 5275 */ "nihf\t\0" + /* 5281 */ "oihf\t\0" + /* 5287 */ "xihf\t\0" + /* 5293 */ "vmalhf\t\0" + /* 5301 */ "clhf\t\0" + /* 5307 */ "vmlhf\t\0" + /* 5314 */ "vuplhf\t\0" + /* 5322 */ "vmhf\t\0" + /* 5328 */ "vuphf\t\0" + /* 5335 */ "vmrhf\t\0" + /* 5342 */ "vscbif\t\0" + /* 5350 */ "vleif\t\0" + /* 5357 */ "vrepif\t\0" + /* 5365 */ "stckf\t\0" + /* 5372 */ "vpkf\t\0" + /* 5378 */ "vmalf\t\0" + /* 5385 */ "veclf\t\0" + /* 5392 */ "vavglf\t\0" + /* 5400 */ "vchlf\t\0" + /* 5407 */ "iilf\t\0" + /* 5413 */ "llilf\t\0" + /* 5420 */ "nilf\t\0" + /* 5426 */ "oilf\t\0" + /* 5432 */ "xilf\t\0" + /* 5438 */ "vupllf\t\0" + /* 5446 */ "verllf\t\0" + /* 5454 */ "vmlf\t\0" + /* 5460 */ "vmnlf\t\0" + /* 5467 */ "vuplf\t\0" + /* 5474 */ "vmrlf\t\0" + /* 5481 */ "vesrlf\t\0" + /* 5489 */ "veslf\t\0" + /* 5496 */ "vmxlf\t\0" + /* 5503 */ "vllezlf\t\0" + /* 5512 */ "vgfmf\t\0" + /* 5519 */ "pfmf\t\0" + /* 5525 */ "vgmf\t\0" + /* 5531 */ "verimf\t\0" + /* 5539 */ "kmf\t\0" + /* 5544 */ "vcnf\t\0" + /* 5550 */ "vmnf\t\0" + /* 5556 */ "vcrnf\t\0" + /* 5563 */ "vmaof\t\0" + /* 5570 */ "vmalof\t\0" + /* 5578 */ "vmlof\t\0" + /* 5585 */ "vmof\t\0" + /* 5591 */ "vlrepf\t\0" + /* 5599 */ "vlbrrepf\t\0" + /* 5609 */ "vrepf\t\0" + /* 5616 */ "vlpf\t\0" + /* 5622 */ "vceqf\t\0" + /* 5629 */ "vsumqf\t\0" + /* 5637 */ "vlebrf\t\0" + /* 5645 */ "vstebrf\t\0" + /* 5654 */ "vlbrf\t\0" + /* 5661 */ "vstbrf\t\0" + /* 5669 */ "vlerf\t\0" + /* 5676 */ "vsterf\t\0" + /* 5684 */ "vistrf\t\0" + /* 5692 */ "lzrf\t\0" + /* 5698 */ "vpksf\t\0" + /* 5705 */ "vpklsf\t\0" + /* 5713 */ "vstrsf\t\0" + /* 5721 */ "vsf\t\0" + /* 5726 */ "vpopctf\t\0" + /* 5735 */ "ptf\t\0" + /* 5740 */ "cuutf\t\0" + /* 5747 */ "vesravf\t\0" + /* 5756 */ "vlgvf\t\0" + /* 5763 */ "verllvf\t\0" + /* 5772 */ "vesrlvf\t\0" + /* 5781 */ "veslvf\t\0" + /* 5789 */ "vmxf\t\0" + /* 5795 */ "vstrczf\t\0" + /* 5804 */ "vfaezf\t\0" + /* 5812 */ "vfeezf\t\0" + /* 5820 */ "vllezf\t\0" + /* 5828 */ "vfenezf\t\0" + /* 5837 */ "vclzf\t\0" + /* 5844 */ "vllebrzf\t\0" + /* 5854 */ "vstrszf\t\0" + /* 5863 */ "vctzf\t\0" + /* 5870 */ "laag\t\0" + /* 5876 */ "ecag\t\0" + /* 5882 */ "diag\t\0" + /* 5888 */ "slag\t\0" + /* 5894 */ "vgfmag\t\0" + /* 5902 */ "lrag\t\0" + /* 5908 */ "vesrag\t\0" + /* 5916 */ "strag\t\0" + /* 5923 */ "lurag\t\0" + /* 5930 */ "vag\t\0" + /* 5935 */ "slbg\t\0" + /* 5941 */ "risbg\t\0" + /* 5948 */ "rnsbg\t\0" + /* 5955 */ "rosbg\t\0" + /* 5962 */ "rxsbg\t\0" + /* 5969 */ "vcvbg\t\0" + /* 5976 */ "tracg\t\0" + /* 5983 */ "vaccg\t\0" + /* 5990 */ "vecg\t\0" + /* 5996 */ "alcg\t\0" + /* 6002 */ "vlcg\t\0" + /* 6008 */ "locg\t\0" + /* 6014 */ "stocg\t\0" + /* 6021 */ "vcdg\t\0" + /* 6027 */ "lpdg\t\0" + /* 6033 */ "vcvdg\t\0" + /* 6040 */ "vsceg\t\0" + /* 6047 */ "vgeg\t\0" + /* 6053 */ "vleg\t\0" + /* 6059 */ "bxleg\t\0" + /* 6066 */ "ereg\t\0" + /* 6072 */ "vseg\t\0" + /* 6078 */ "vsteg\t\0" + /* 6085 */ "eregg\t\0" + /* 6092 */ "lgg\t\0" + /* 6097 */ "vavgg\t\0" + /* 6104 */ "vlvgg\t\0" + /* 6111 */ "risbhg\t\0" + /* 6119 */ "vchg\t\0" + /* 6125 */ "vmrhg\t\0" + /* 6132 */ "bxhg\t\0" + /* 6138 */ "brxhg\t\0" + /* 6145 */ "vscbig\t\0" + /* 6153 */ "vleig\t\0" + /* 6160 */ "vrepig\t\0" + /* 6168 */ "jg\t\0" + /* 6172 */ "vpkg\t\0" + /* 6178 */ "laalg\t\0" + /* 6185 */ "risblg\t\0" + /* 6193 */ "veclg\t\0" + /* 6200 */ "vcdlg\t\0" + /* 6207 */ "vavglg\t\0" + /* 6215 */ "vchlg\t\0" + /* 6222 */ "verllg\t\0" + /* 6230 */ "sllg\t\0" + /* 6236 */ "mlg\t\0" + /* 6241 */ "vmnlg\t\0" + /* 6248 */ "vmrlg\t\0" + /* 6255 */ "vesrlg\t\0" + /* 6263 */ "veslg\t\0" + /* 6270 */ "vmslg\t\0" + /* 6277 */ "lctlg\t\0" + /* 6284 */ "vmxlg\t\0" + /* 6291 */ "brxlg\t\0" + /* 6298 */ "vgfmg\t\0" + /* 6305 */ "vgmg\t\0" + /* 6311 */ "verimg\t\0" + /* 6319 */ "lmg\t\0" + /* 6324 */ "stmg\t\0" + /* 6330 */ "vsumg\t\0" + /* 6337 */ "lang\t\0" + /* 6343 */ "vmng\t\0" + /* 6349 */ "laog\t\0" + /* 6355 */ "vlrepg\t\0" + /* 6363 */ "vlbrrepg\t\0" + /* 6373 */ "vrepg\t\0" + /* 6380 */ "vlpg\t\0" + /* 6386 */ "cspg\t\0" + /* 6392 */ "mvpg\t\0" + /* 6398 */ "vceqg\t\0" + /* 6405 */ "vsumqg\t\0" + /* 6413 */ "vlebrg\t\0" + /* 6421 */ "vstebrg\t\0" + /* 6430 */ "vlbrg\t\0" + /* 6437 */ "vstbrg\t\0" + /* 6445 */ "vlerg\t\0" + /* 6452 */ "vsterg\t\0" + /* 6460 */ "sturg\t\0" + /* 6467 */ "lzrg\t\0" + /* 6473 */ "bsg\t\0" + /* 6478 */ "csg\t\0" + /* 6483 */ "cdsg\t\0" + /* 6489 */ "llgfsg\t\0" + /* 6497 */ "vpksg\t\0" + /* 6504 */ "vpklsg\t\0" + /* 6512 */ "msg\t\0" + /* 6517 */ "vsg\t\0" + /* 6522 */ "bctg\t\0" + /* 6528 */ "ectg\t\0" + /* 6534 */ "vpopctg\t\0" + /* 6543 */ "brctg\t\0" + /* 6550 */ "stctg\t\0" + /* 6557 */ "ltg\t\0" + /* 6562 */ "ntstg\t\0" + /* 6569 */ "vesravg\t\0" + /* 6578 */ "vavg\t\0" + /* 6584 */ "vlgvg\t\0" + /* 6591 */ "verllvg\t\0" + /* 6600 */ "vesrlvg\t\0" + /* 6609 */ "veslvg\t\0" + /* 6617 */ "vlvg\t\0" + /* 6623 */ "lrvg\t\0" + /* 6629 */ "strvg\t\0" + /* 6636 */ "laxg\t\0" + /* 6642 */ "vmxg\t\0" + /* 6648 */ "vllezg\t\0" + /* 6656 */ "vclzg\t\0" + /* 6663 */ "vllebrzg\t\0" + /* 6673 */ "vctzg\t\0" + /* 6680 */ "vgfmah\t\0" + /* 6688 */ "vmah\t\0" + /* 6694 */ "vesrah\t\0" + /* 6702 */ "vah\t\0" + /* 6707 */ "cibh\t\0" + /* 6713 */ "cgibh\t\0" + /* 6720 */ "clgibh\t\0" + /* 6728 */ "clibh\t\0" + /* 6735 */ "lbh\t\0" + /* 6740 */ "crbh\t\0" + /* 6746 */ "cgrbh\t\0" + /* 6753 */ "clgrbh\t\0" + /* 6761 */ "clrbh\t\0" + /* 6768 */ "vacch\t\0" + /* 6775 */ "vech\t\0" + /* 6781 */ "vfch\t\0" + /* 6787 */ "llch\t\0" + /* 6793 */ "vlch\t\0" + /* 6799 */ "loch\t\0" + /* 6805 */ "stoch\t\0" + /* 6812 */ "vstrch\t\0" + /* 6820 */ "msch\t\0" + /* 6826 */ "ssch\t\0" + /* 6832 */ "stsch\t\0" + /* 6839 */ "stch\t\0" + /* 6845 */ "vch\t\0" + /* 6850 */ "vfaeh\t\0" + /* 6857 */ "vmaeh\t\0" + /* 6864 */ "vfeeh\t\0" + /* 6871 */ "vmaleh\t\0" + /* 6879 */ "vmleh\t\0" + /* 6886 */ "vleh\t\0" + /* 6892 */ "vmeh\t\0" + /* 6898 */ "vfeneh\t\0" + /* 6906 */ "vsteh\t\0" + /* 6913 */ "locfh\t\0" + /* 6920 */ "stocfh\t\0" + /* 6928 */ "lfh\t\0" + /* 6933 */ "stfh\t\0" + /* 6939 */ "agh\t\0" + /* 6944 */ "locgh\t\0" + /* 6951 */ "stocgh\t\0" + /* 6959 */ "vsegh\t\0" + /* 6966 */ "jgh\t\0" + /* 6971 */ "llgh\t\0" + /* 6977 */ "vsumgh\t\0" + /* 6985 */ "sgh\t\0" + /* 6990 */ "vavgh\t\0" + /* 6997 */ "vlvgh\t\0" + /* 7004 */ "vmahh\t\0" + /* 7011 */ "vchh\t\0" + /* 7017 */ "locfhh\t\0" + /* 7025 */ "stocfhh\t\0" + /* 7034 */ "iihh\t\0" + /* 7040 */ "llihh\t\0" + /* 7047 */ "nihh\t\0" + /* 7053 */ "oihh\t\0" + /* 7059 */ "vmalhh\t\0" + /* 7067 */ "llhh\t\0" + /* 7073 */ "vmlhh\t\0" + /* 7080 */ "vuplhh\t\0" + /* 7088 */ "tmhh\t\0" + /* 7094 */ "vmhh\t\0" + /* 7100 */ "vuphh\t\0" + /* 7107 */ "vmrhh\t\0" + /* 7114 */ "sthh\t\0" + /* 7120 */ "aih\t\0" + /* 7125 */ "vscbih\t\0" + /* 7133 */ "cih\t\0" + /* 7138 */ "vleih\t\0" + /* 7145 */ "lochih\t\0" + /* 7153 */ "locghih\t\0" + /* 7162 */ "lochhih\t\0" + /* 7171 */ "clih\t\0" + /* 7177 */ "vrepih\t\0" + /* 7185 */ "alsih\t\0" + /* 7192 */ "cijh\t\0" + /* 7198 */ "cgijh\t\0" + /* 7205 */ "clgijh\t\0" + /* 7213 */ "clijh\t\0" + /* 7220 */ "crjh\t\0" + /* 7226 */ "cgrjh\t\0" + /* 7233 */ "clgrjh\t\0" + /* 7241 */ "clrjh\t\0" + /* 7248 */ "vpkh\t\0" + /* 7254 */ "vmalh\t\0" + /* 7261 */ "ciblh\t\0" + /* 7268 */ "cgiblh\t\0" + /* 7276 */ "clgiblh\t\0" + /* 7285 */ "cliblh\t\0" + /* 7293 */ "crblh\t\0" + /* 7300 */ "cgrblh\t\0" + /* 7308 */ "clgrblh\t\0" + /* 7317 */ "clrblh\t\0" + /* 7325 */ "veclh\t\0" + /* 7332 */ "loclh\t\0" + /* 7339 */ "stoclh\t\0" + /* 7347 */ "locglh\t\0" + /* 7355 */ "stocglh\t\0" + /* 7364 */ "jglh\t\0" + /* 7370 */ "vavglh\t\0" + /* 7378 */ "vchlh\t\0" + /* 7385 */ "locfhlh\t\0" + /* 7394 */ "stocfhlh\t\0" + /* 7404 */ "bilh\t\0" + /* 7410 */ "lochilh\t\0" + /* 7419 */ "locghilh\t\0" + /* 7429 */ "lochhilh\t\0" + /* 7439 */ "iilh\t\0" + /* 7445 */ "llilh\t\0" + /* 7452 */ "nilh\t\0" + /* 7458 */ "oilh\t\0" + /* 7464 */ "cijlh\t\0" + /* 7471 */ "cgijlh\t\0" + /* 7479 */ "clgijlh\t\0" + /* 7488 */ "clijlh\t\0" + /* 7496 */ "crjlh\t\0" + /* 7503 */ "cgrjlh\t\0" + /* 7511 */ "clgrjlh\t\0" + /* 7520 */ "clrjlh\t\0" + /* 7528 */ "vupllh\t\0" + /* 7536 */ "verllh\t\0" + /* 7544 */ "tmlh\t\0" + /* 7550 */ "vmlh\t\0" + /* 7556 */ "cibnlh\t\0" + /* 7564 */ "cgibnlh\t\0" + /* 7573 */ "clgibnlh\t\0" + /* 7583 */ "clibnlh\t\0" + /* 7592 */ "crbnlh\t\0" + /* 7600 */ "cgrbnlh\t\0" + /* 7609 */ "clgrbnlh\t\0" + /* 7619 */ "clrbnlh\t\0" + /* 7628 */ "locnlh\t\0" + /* 7636 */ "stocnlh\t\0" + /* 7645 */ "locgnlh\t\0" + /* 7654 */ "stocgnlh\t\0" + /* 7664 */ "jgnlh\t\0" + /* 7671 */ "locfhnlh\t\0" + /* 7681 */ "stocfhnlh\t\0" + /* 7692 */ "binlh\t\0" + /* 7699 */ "lochinlh\t\0" + /* 7709 */ "locghinlh\t\0" + /* 7720 */ "lochhinlh\t\0" + /* 7731 */ "cijnlh\t\0" + /* 7739 */ "cgijnlh\t\0" + /* 7748 */ "clgijnlh\t\0" + /* 7758 */ "clijnlh\t\0" + /* 7767 */ "crjnlh\t\0" + /* 7775 */ "cgrjnlh\t\0" + /* 7784 */ "clgrjnlh\t\0" + /* 7794 */ "clrjnlh\t\0" + /* 7803 */ "vmnlh\t\0" + /* 7810 */ "locrnlh\t\0" + /* 7819 */ "locgrnlh\t\0" + /* 7829 */ "selgrnlh\t\0" + /* 7839 */ "locfhrnlh\t\0" + /* 7850 */ "selfhrnlh\t\0" + /* 7861 */ "selrnlh\t\0" + /* 7870 */ "clgtnlh\t\0" + /* 7879 */ "citnlh\t\0" + /* 7887 */ "clfitnlh\t\0" + /* 7897 */ "cgitnlh\t\0" + /* 7906 */ "clgitnlh\t\0" + /* 7916 */ "cltnlh\t\0" + /* 7924 */ "crtnlh\t\0" + /* 7932 */ "cgrtnlh\t\0" + /* 7941 */ "clgrtnlh\t\0" + /* 7951 */ "clrtnlh\t\0" + /* 7960 */ "vuplh\t\0" + /* 7967 */ "locrlh\t\0" + /* 7975 */ "locgrlh\t\0" + /* 7984 */ "selgrlh\t\0" + /* 7993 */ "locfhrlh\t\0" + /* 8003 */ "selfhrlh\t\0" + /* 8013 */ "selrlh\t\0" + /* 8021 */ "vmrlh\t\0" + /* 8028 */ "vesrlh\t\0" + /* 8036 */ "veslh\t\0" + /* 8043 */ "clgtlh\t\0" + /* 8051 */ "citlh\t\0" + /* 8058 */ "clfitlh\t\0" + /* 8067 */ "cgitlh\t\0" + /* 8075 */ "clgitlh\t\0" + /* 8084 */ "cltlh\t\0" + /* 8091 */ "crtlh\t\0" + /* 8098 */ "cgrtlh\t\0" + /* 8106 */ "clgrtlh\t\0" + /* 8115 */ "clrtlh\t\0" + /* 8123 */ "vmxlh\t\0" + /* 8130 */ "icmh\t\0" + /* 8136 */ "stcmh\t\0" + /* 8143 */ "vgfmh\t\0" + /* 8150 */ "vgmh\t\0" + /* 8156 */ "verimh\t\0" + /* 8164 */ "clmh\t\0" + /* 8170 */ "stmh\t\0" + /* 8176 */ "vsumh\t\0" + /* 8183 */ "vmh\t\0" + /* 8188 */ "cibnh\t\0" + /* 8195 */ "cgibnh\t\0" + /* 8203 */ "clgibnh\t\0" + /* 8212 */ "clibnh\t\0" + /* 8220 */ "crbnh\t\0" + /* 8227 */ "cgrbnh\t\0" + /* 8235 */ "clgrbnh\t\0" + /* 8244 */ "clrbnh\t\0" + /* 8252 */ "locnh\t\0" + /* 8259 */ "stocnh\t\0" + /* 8267 */ "vclfnh\t\0" + /* 8275 */ "locgnh\t\0" + /* 8283 */ "stocgnh\t\0" + /* 8292 */ "jgnh\t\0" + /* 8298 */ "locfhnh\t\0" + /* 8307 */ "stocfhnh\t\0" + /* 8317 */ "binh\t\0" + /* 8323 */ "lochinh\t\0" + /* 8332 */ "locghinh\t\0" + /* 8342 */ "lochhinh\t\0" + /* 8352 */ "cijnh\t\0" + /* 8359 */ "cgijnh\t\0" + /* 8367 */ "clgijnh\t\0" + /* 8376 */ "clijnh\t\0" + /* 8384 */ "crjnh\t\0" + /* 8391 */ "cgrjnh\t\0" + /* 8399 */ "clgrjnh\t\0" + /* 8408 */ "clrjnh\t\0" + /* 8416 */ "vmnh\t\0" + /* 8422 */ "locrnh\t\0" + /* 8430 */ "locgrnh\t\0" + /* 8439 */ "selgrnh\t\0" + /* 8448 */ "locfhrnh\t\0" + /* 8458 */ "selfhrnh\t\0" + /* 8468 */ "selrnh\t\0" + /* 8476 */ "clgtnh\t\0" + /* 8484 */ "citnh\t\0" + /* 8491 */ "clfitnh\t\0" + /* 8500 */ "cgitnh\t\0" + /* 8508 */ "clgitnh\t\0" + /* 8517 */ "cltnh\t\0" + /* 8524 */ "crtnh\t\0" + /* 8531 */ "cgrtnh\t\0" + /* 8539 */ "clgrtnh\t\0" + /* 8548 */ "clrtnh\t\0" + /* 8556 */ "vmaoh\t\0" + /* 8563 */ "vmaloh\t\0" + /* 8571 */ "vmloh\t\0" + /* 8578 */ "vmoh\t\0" + /* 8584 */ "vlreph\t\0" + /* 8592 */ "vlbrreph\t\0" + /* 8602 */ "vreph\t\0" + /* 8609 */ "vlph\t\0" + /* 8615 */ "vcsph\t\0" + /* 8622 */ "vuph\t\0" + /* 8628 */ "vceqh\t\0" + /* 8635 */ "vlebrh\t\0" + /* 8643 */ "vstebrh\t\0" + /* 8652 */ "vlbrh\t\0" + /* 8659 */ "vstbrh\t\0" + /* 8667 */ "locrh\t\0" + /* 8674 */ "vlerh\t\0" + /* 8681 */ "vsterh\t\0" + /* 8689 */ "locgrh\t\0" + /* 8697 */ "selgrh\t\0" + /* 8705 */ "locfhrh\t\0" + /* 8714 */ "selfhrh\t\0" + /* 8723 */ "selrh\t\0" + /* 8730 */ "vmrh\t\0" + /* 8736 */ "vistrh\t\0" + /* 8744 */ "vpksh\t\0" + /* 8751 */ "vpklsh\t\0" + /* 8759 */ "vstrsh\t\0" + /* 8767 */ "vsh\t\0" + /* 8772 */ "vpopcth\t\0" + /* 8781 */ "brcth\t\0" + /* 8788 */ "clgth\t\0" + /* 8795 */ "cith\t\0" + /* 8801 */ "clfith\t\0" + /* 8809 */ "cgith\t\0" + /* 8816 */ "clgith\t\0" + /* 8824 */ "clth\t\0" + /* 8830 */ "crth\t\0" + /* 8836 */ "cgrth\t\0" + /* 8843 */ "clgrth\t\0" + /* 8851 */ "clrth\t\0" + /* 8858 */ "sth\t\0" + /* 8863 */ "vesravh\t\0" + /* 8872 */ "vlgvh\t\0" + /* 8879 */ "verllvh\t\0" + /* 8888 */ "vesrlvh\t\0" + /* 8897 */ "veslvh\t\0" + /* 8905 */ "lrvh\t\0" + /* 8911 */ "strvh\t\0" + /* 8918 */ "bxh\t\0" + /* 8923 */ "vmxh\t\0" + /* 8929 */ "brxh\t\0" + /* 8935 */ "mayh\t\0" + /* 8941 */ "myh\t\0" + /* 8946 */ "vstrczh\t\0" + /* 8955 */ "vfaezh\t\0" + /* 8963 */ "vfeezh\t\0" + /* 8971 */ "vllezh\t\0" + /* 8979 */ "vfenezh\t\0" + /* 8988 */ "vupkzh\t\0" + /* 8996 */ "vclzh\t\0" + /* 9003 */ "vllebrzh\t\0" + /* 9013 */ "vstrszh\t\0" + /* 9022 */ "vctzh\t\0" + /* 9029 */ "niai\t\0" + /* 9035 */ "vsbcbi\t\0" + /* 9043 */ "vscbi\t\0" + /* 9050 */ "vsbi\t\0" + /* 9056 */ "qpaci\t\0" + /* 9063 */ "vftci\t\0" + /* 9070 */ "vpdi\t\0" + /* 9076 */ "afi\t\0" + /* 9081 */ "cfi\t\0" + /* 9086 */ "agfi\t\0" + /* 9092 */ "cgfi\t\0" + /* 9098 */ "algfi\t\0" + /* 9105 */ "clgfi\t\0" + /* 9112 */ "slgfi\t\0" + /* 9119 */ "msgfi\t\0" + /* 9126 */ "alfi\t\0" + /* 9132 */ "clfi\t\0" + /* 9138 */ "slfi\t\0" + /* 9144 */ "msfi\t\0" + /* 9150 */ "vfi\t\0" + /* 9155 */ "ahi\t\0" + /* 9160 */ "lochi\t\0" + /* 9167 */ "aghi\t\0" + /* 9173 */ "locghi\t\0" + /* 9181 */ "lghi\t\0" + /* 9187 */ "mghi\t\0" + /* 9193 */ "mvghi\t\0" + /* 9200 */ "lochhi\t\0" + /* 9208 */ "mvhhi\t\0" + /* 9215 */ "lhi\t\0" + /* 9220 */ "mhi\t\0" + /* 9225 */ "mvhi\t\0" + /* 9231 */ "cli\t\0" + /* 9236 */ "ni\t\0" + /* 9240 */ "oi\t\0" + /* 9244 */ "vrepi\t\0" + /* 9251 */ "tpi\t\0" + /* 9256 */ "qctri\t\0" + /* 9263 */ "asi\t\0" + /* 9268 */ "agsi\t\0" + /* 9274 */ "algsi\t\0" + /* 9281 */ "chsi\t\0" + /* 9287 */ "clfhsi\t\0" + /* 9295 */ "cghsi\t\0" + /* 9302 */ "clghsi\t\0" + /* 9310 */ "chhsi\t\0" + /* 9317 */ "clhhsi\t\0" + /* 9325 */ "alsi\t\0" + /* 9331 */ "qsi\t\0" + /* 9336 */ "stsi\t\0" + /* 9342 */ "pti\t\0" + /* 9347 */ "mvi\t\0" + /* 9352 */ "xi\t\0" + /* 9356 */ "cij\t\0" + /* 9361 */ "cgij\t\0" + /* 9367 */ "clgij\t\0" + /* 9374 */ "clij\t\0" + /* 9380 */ "crj\t\0" + /* 9385 */ "cgrj\t\0" + /* 9391 */ "clgrj\t\0" + /* 9398 */ "clrj\t\0" + /* 9404 */ "slak\t\0" + /* 9410 */ "srak\t\0" + /* 9416 */ "pack\t\0" + /* 9422 */ "sck\t\0" + /* 9427 */ "stck\t\0" + /* 9433 */ "mvck\t\0" + /* 9439 */ "mvcdk\t\0" + /* 9446 */ "wfk\t\0" + /* 9451 */ "ahik\t\0" + /* 9457 */ "aghik\t\0" + /* 9464 */ "alghsik\t\0" + /* 9473 */ "alhsik\t\0" + /* 9481 */ "sllk\t\0" + /* 9487 */ "srlk\t\0" + /* 9493 */ "edmk\t\0" + /* 9499 */ "unpk\t\0" + /* 9505 */ "vpk\t\0" + /* 9510 */ "ark\t\0" + /* 9515 */ "ncrk\t\0" + /* 9521 */ "ocrk\t\0" + /* 9527 */ "agrk\t\0" + /* 9533 */ "ncgrk\t\0" + /* 9540 */ "ocgrk\t\0" + /* 9547 */ "algrk\t\0" + /* 9554 */ "slgrk\t\0" + /* 9561 */ "mgrk\t\0" + /* 9567 */ "nngrk\t\0" + /* 9574 */ "nogrk\t\0" + /* 9581 */ "sgrk\t\0" + /* 9587 */ "nxgrk\t\0" + /* 9594 */ "alrk\t\0" + /* 9600 */ "slrk\t\0" + /* 9606 */ "nnrk\t\0" + /* 9612 */ "nork\t\0" + /* 9618 */ "srk\t\0" + /* 9623 */ "nxrk\t\0" + /* 9629 */ "mvcsk\t\0" + /* 9636 */ "ivsk\t\0" + /* 9642 */ "laal\t\0" + /* 9648 */ "bal\t\0" + /* 9653 */ "vmal\t\0" + /* 9659 */ "cibl\t\0" + /* 9665 */ "cgibl\t\0" + /* 9672 */ "clgibl\t\0" + /* 9680 */ "clibl\t\0" + /* 9687 */ "crbl\t\0" + /* 9693 */ "cgrbl\t\0" + /* 9700 */ "clgrbl\t\0" + /* 9708 */ "clrbl\t\0" + /* 9715 */ "vecl\t\0" + /* 9721 */ "clcl\t\0" + /* 9727 */ "locl\t\0" + /* 9733 */ "stocl\t\0" + /* 9740 */ "brcl\t\0" + /* 9746 */ "mvcl\t\0" + /* 9752 */ "sldl\t\0" + /* 9758 */ "srdl\t\0" + /* 9764 */ "vsel\t\0" + /* 9770 */ "stfl\t\0" + /* 9776 */ "locgl\t\0" + /* 9783 */ "stocgl\t\0" + /* 9791 */ "jgl\t\0" + /* 9796 */ "vavgl\t\0" + /* 9803 */ "vchl\t\0" + /* 9809 */ "locfhl\t\0" + /* 9817 */ "stocfhl\t\0" + /* 9826 */ "iihl\t\0" + /* 9832 */ "llihl\t\0" + /* 9839 */ "nihl\t\0" + /* 9845 */ "oihl\t\0" + /* 9851 */ "tmhl\t\0" + /* 9857 */ "bil\t\0" + /* 9862 */ "lochil\t\0" + /* 9870 */ "locghil\t\0" + /* 9879 */ "lochhil\t\0" + /* 9888 */ "cijl\t\0" + /* 9894 */ "cgijl\t\0" + /* 9901 */ "clgijl\t\0" + /* 9909 */ "clijl\t\0" + /* 9916 */ "crjl\t\0" + /* 9922 */ "cgrjl\t\0" + /* 9929 */ "clgrjl\t\0" + /* 9937 */ "clrjl\t\0" + /* 9944 */ "vfll\t\0" + /* 9950 */ "iill\t\0" + /* 9956 */ "llill\t\0" + /* 9963 */ "nill\t\0" + /* 9969 */ "oill\t\0" + /* 9975 */ "tmll\t\0" + /* 9981 */ "vupll\t\0" + /* 9988 */ "verll\t\0" + /* 9995 */ "sll\t\0" + /* 10000 */ "vll\t\0" + /* 10005 */ "vml\t\0" + /* 10010 */ "cibnl\t\0" + /* 10017 */ "cgibnl\t\0" + /* 10025 */ "clgibnl\t\0" + /* 10034 */ "clibnl\t\0" + /* 10042 */ "crbnl\t\0" + /* 10049 */ "cgrbnl\t\0" + /* 10057 */ "clgrbnl\t\0" + /* 10066 */ "clrbnl\t\0" + /* 10074 */ "locnl\t\0" + /* 10081 */ "stocnl\t\0" + /* 10089 */ "vclfnl\t\0" + /* 10097 */ "locgnl\t\0" + /* 10105 */ "stocgnl\t\0" + /* 10114 */ "jgnl\t\0" + /* 10120 */ "locfhnl\t\0" + /* 10129 */ "stocfhnl\t\0" + /* 10139 */ "binl\t\0" + /* 10145 */ "lochinl\t\0" + /* 10154 */ "locghinl\t\0" + /* 10164 */ "lochhinl\t\0" + /* 10174 */ "cijnl\t\0" + /* 10181 */ "cgijnl\t\0" + /* 10189 */ "clgijnl\t\0" + /* 10198 */ "clijnl\t\0" + /* 10206 */ "crjnl\t\0" + /* 10213 */ "cgrjnl\t\0" + /* 10221 */ "clgrjnl\t\0" + /* 10230 */ "clrjnl\t\0" + /* 10238 */ "vmnl\t\0" + /* 10244 */ "locrnl\t\0" + /* 10252 */ "locgrnl\t\0" + /* 10261 */ "selgrnl\t\0" + /* 10270 */ "locfhrnl\t\0" + /* 10280 */ "selfhrnl\t\0" + /* 10290 */ "selrnl\t\0" + /* 10298 */ "clgtnl\t\0" + /* 10306 */ "citnl\t\0" + /* 10313 */ "clfitnl\t\0" + /* 10322 */ "cgitnl\t\0" + /* 10330 */ "clgitnl\t\0" + /* 10339 */ "cltnl\t\0" + /* 10346 */ "crtnl\t\0" + /* 10353 */ "cgrtnl\t\0" + /* 10361 */ "clgrtnl\t\0" + /* 10370 */ "clrtnl\t\0" + /* 10378 */ "vcfpl\t\0" + /* 10385 */ "vupl\t\0" + /* 10391 */ "larl\t\0" + /* 10397 */ "locrl\t\0" + /* 10404 */ "mvcrl\t\0" + /* 10411 */ "pfdrl\t\0" + /* 10418 */ "cgfrl\t\0" + /* 10425 */ "clgfrl\t\0" + /* 10433 */ "llgfrl\t\0" + /* 10441 */ "locgrl\t\0" + /* 10449 */ "clgrl\t\0" + /* 10456 */ "selgrl\t\0" + /* 10464 */ "stgrl\t\0" + /* 10471 */ "chrl\t\0" + /* 10477 */ "locfhrl\t\0" + /* 10486 */ "selfhrl\t\0" + /* 10495 */ "cghrl\t\0" + /* 10502 */ "clghrl\t\0" + /* 10510 */ "llghrl\t\0" + /* 10518 */ "clhrl\t\0" + /* 10525 */ "llhrl\t\0" + /* 10532 */ "sthrl\t\0" + /* 10539 */ "clrl\t\0" + /* 10545 */ "selrl\t\0" + /* 10552 */ "vlrl\t\0" + /* 10558 */ "vmrl\t\0" + /* 10564 */ "vesrl\t\0" + /* 10571 */ "vsrl\t\0" + /* 10577 */ "vstrl\t\0" + /* 10584 */ "exrl\t\0" + /* 10590 */ "brasl\t\0" + /* 10597 */ "vesl\t\0" + /* 10603 */ "vmsl\t\0" + /* 10609 */ "vsl\t\0" + /* 10614 */ "lcctl\t\0" + /* 10621 */ "lctl\t\0" + /* 10627 */ "lpctl\t\0" + /* 10634 */ "lsctl\t\0" + /* 10641 */ "stctl\t\0" + /* 10648 */ "clgtl\t\0" + /* 10655 */ "citl\t\0" + /* 10661 */ "clfitl\t\0" + /* 10669 */ "cgitl\t\0" + /* 10676 */ "clgitl\t\0" + /* 10684 */ "cltl\t\0" + /* 10690 */ "crtl\t\0" + /* 10696 */ "cgrtl\t\0" + /* 10703 */ "clgrtl\t\0" + /* 10711 */ "clrtl\t\0" + /* 10718 */ "sortl\t\0" + /* 10725 */ "vstl\t\0" + /* 10731 */ "vl\t\0" + /* 10735 */ "vmxl\t\0" + /* 10741 */ "mayl\t\0" + /* 10747 */ "myl\t\0" + /* 10752 */ "vupkzl\t\0" + /* 10760 */ "lam\t\0" + /* 10765 */ "stam\t\0" + /* 10771 */ "vgbm\t\0" + /* 10777 */ "irbm\t\0" + /* 10783 */ "rrbm\t\0" + /* 10789 */ "icm\t\0" + /* 10794 */ "locm\t\0" + /* 10800 */ "stocm\t\0" + /* 10807 */ "stcm\t\0" + /* 10813 */ "vgfm\t\0" + /* 10819 */ "vfm\t\0" + /* 10824 */ "locgm\t\0" + /* 10831 */ "stocgm\t\0" + /* 10839 */ "jgm\t\0" + /* 10844 */ "vgm\t\0" + /* 10849 */ "locfhm\t\0" + /* 10857 */ "stocfhm\t\0" + /* 10866 */ "bim\t\0" + /* 10871 */ "lochim\t\0" + /* 10879 */ "locghim\t\0" + /* 10888 */ "lochhim\t\0" + /* 10897 */ "verim\t\0" + /* 10904 */ "jm\t\0" + /* 10908 */ "km\t\0" + /* 10912 */ "clm\t\0" + /* 10917 */ "vlm\t\0" + /* 10922 */ "bnm\t\0" + /* 10927 */ "locnm\t\0" + /* 10934 */ "stocnm\t\0" + /* 10942 */ "locgnm\t\0" + /* 10950 */ "stocgnm\t\0" + /* 10959 */ "jgnm\t\0" + /* 10965 */ "locfhnm\t\0" + /* 10974 */ "stocfhnm\t\0" + /* 10984 */ "binm\t\0" + /* 10990 */ "lochinm\t\0" + /* 10999 */ "locghinm\t\0" + /* 11009 */ "lochhinm\t\0" + /* 11019 */ "jnm\t\0" + /* 11024 */ "locrnm\t\0" + /* 11032 */ "locgrnm\t\0" + /* 11041 */ "selgrnm\t\0" + /* 11050 */ "locfhrnm\t\0" + /* 11060 */ "selfhrnm\t\0" + /* 11070 */ "selrnm\t\0" + /* 11078 */ "srnm\t\0" + /* 11084 */ "ipm\t\0" + /* 11089 */ "spm\t\0" + /* 11094 */ "locrm\t\0" + /* 11101 */ "vbperm\t\0" + /* 11109 */ "vperm\t\0" + /* 11116 */ "locgrm\t\0" + /* 11124 */ "selgrm\t\0" + /* 11132 */ "locfhrm\t\0" + /* 11141 */ "selfhrm\t\0" + /* 11150 */ "selrm\t\0" + /* 11157 */ "bsm\t\0" + /* 11162 */ "vcksm\t\0" + /* 11169 */ "stnsm\t\0" + /* 11176 */ "stosm\t\0" + /* 11183 */ "bassm\t\0" + /* 11190 */ "vstm\t\0" + /* 11196 */ "vtm\t\0" + /* 11201 */ "vsum\t\0" + /* 11207 */ "lan\t\0" + /* 11212 */ "vcfn\t\0" + /* 11218 */ "risbgn\t\0" + /* 11226 */ "alsihn\t\0" + /* 11234 */ "mvcin\t\0" + /* 11241 */ "tbegin\t\0" + /* 11249 */ "pgin\t\0" + /* 11255 */ "vfmin\t\0" + /* 11262 */ "vmn\t\0" + /* 11267 */ "vnn\t\0" + /* 11272 */ "mvn\t\0" + /* 11277 */ "lao\t\0" + /* 11282 */ "vmao\t\0" + /* 11288 */ "bo\t\0" + /* 11292 */ "loco\t\0" + /* 11298 */ "stoco\t\0" + /* 11305 */ "locgo\t\0" + /* 11312 */ "stocgo\t\0" + /* 11320 */ "jgo\t\0" + /* 11325 */ "locfho\t\0" + /* 11333 */ "stocfho\t\0" + /* 11342 */ "bio\t\0" + /* 11347 */ "lochio\t\0" + /* 11355 */ "locghio\t\0" + /* 11364 */ "lochhio\t\0" + /* 11373 */ "jo\t\0" + /* 11377 */ "vmalo\t\0" + /* 11384 */ "vmlo\t\0" + /* 11390 */ "plo\t\0" + /* 11395 */ "kmo\t\0" + /* 11400 */ "vmo\t\0" + /* 11405 */ "bno\t\0" + /* 11410 */ "locno\t\0" + /* 11417 */ "stocno\t\0" + /* 11425 */ "locgno\t\0" + /* 11433 */ "stocgno\t\0" + /* 11442 */ "jgno\t\0" + /* 11448 */ "locfhno\t\0" + /* 11457 */ "stocfhno\t\0" + /* 11467 */ "bino\t\0" + /* 11473 */ "lochino\t\0" + /* 11482 */ "locghino\t\0" + /* 11492 */ "lochhino\t\0" + /* 11502 */ "jno\t\0" + /* 11507 */ "ppno\t\0" + /* 11513 */ "locrno\t\0" + /* 11521 */ "locgrno\t\0" + /* 11530 */ "selgrno\t\0" + /* 11539 */ "locfhrno\t\0" + /* 11549 */ "selfhrno\t\0" + /* 11559 */ "selrno\t\0" + /* 11567 */ "prno\t\0" + /* 11573 */ "vno\t\0" + /* 11578 */ "troo\t\0" + /* 11584 */ "locro\t\0" + /* 11591 */ "vzero\t\0" + /* 11598 */ "locgro\t\0" + /* 11606 */ "selgro\t\0" + /* 11614 */ "locfhro\t\0" + /* 11623 */ "selfhro\t\0" + /* 11632 */ "selro\t\0" + /* 11639 */ "vfpso\t\0" + /* 11646 */ "trto\t\0" + /* 11652 */ "mvo\t\0" + /* 11657 */ "stap\t\0" + /* 11663 */ "vap\t\0" + /* 11668 */ "zap\t\0" + /* 11673 */ "bp\t\0" + /* 11677 */ "locp\t\0" + /* 11683 */ "stocp\t\0" + /* 11690 */ "mvcp\t\0" + /* 11696 */ "vschdp\t\0" + /* 11704 */ "stidp\t\0" + /* 11711 */ "rdp\t\0" + /* 11716 */ "vsdp\t\0" + /* 11722 */ "vdp\t\0" + /* 11727 */ "vclzdp\t\0" + /* 11735 */ "vlrep\t\0" + /* 11742 */ "vlbrrep\t\0" + /* 11751 */ "vrep\t\0" + /* 11757 */ "vclfp\t\0" + /* 11764 */ "vcsfp\t\0" + /* 11771 */ "locgp\t\0" + /* 11778 */ "stocgp\t\0" + /* 11786 */ "sigp\t\0" + /* 11792 */ "jgp\t\0" + /* 11797 */ "vlvgp\t\0" + /* 11804 */ "vschp\t\0" + /* 11811 */ "locfhp\t\0" + /* 11819 */ "stocfhp\t\0" + /* 11828 */ "vscshp\t\0" + /* 11836 */ "bip\t\0" + /* 11841 */ "lochip\t\0" + /* 11849 */ "locghip\t\0" + /* 11858 */ "lochhip\t\0" + /* 11867 */ "vlip\t\0" + /* 11873 */ "jp\t\0" + /* 11877 */ "vlp\t\0" + /* 11882 */ "vmp\t\0" + /* 11887 */ "bnp\t\0" + /* 11892 */ "locnp\t\0" + /* 11899 */ "stocnp\t\0" + /* 11907 */ "locgnp\t\0" + /* 11915 */ "stocgnp\t\0" + /* 11924 */ "jgnp\t\0" + /* 11930 */ "locfhnp\t\0" + /* 11939 */ "stocfhnp\t\0" + /* 11949 */ "binp\t\0" + /* 11955 */ "lochinp\t\0" + /* 11964 */ "locghinp\t\0" + /* 11974 */ "lochhinp\t\0" + /* 11984 */ "jnp\t\0" + /* 11989 */ "locrnp\t\0" + /* 11997 */ "locgrnp\t\0" + /* 12006 */ "selgrnp\t\0" + /* 12015 */ "locfhrnp\t\0" + /* 12025 */ "selfhrnp\t\0" + /* 12035 */ "selrnp\t\0" + /* 12043 */ "vpsop\t\0" + /* 12050 */ "bpp\t\0" + /* 12055 */ "lpp\t\0" + /* 12060 */ "locrp\t\0" + /* 12067 */ "locgrp\t\0" + /* 12075 */ "selgrp\t\0" + /* 12083 */ "locfhrp\t\0" + /* 12092 */ "selfhrp\t\0" + /* 12101 */ "selrp\t\0" + /* 12108 */ "bprp\t\0" + /* 12114 */ "vsrp\t\0" + /* 12120 */ "vrp\t\0" + /* 12125 */ "lasp\t\0" + /* 12131 */ "csp\t\0" + /* 12136 */ "vschsp\t\0" + /* 12144 */ "vmsp\t\0" + /* 12150 */ "vsp\t\0" + /* 12155 */ "vtp\t\0" + /* 12160 */ "vschxp\t\0" + /* 12168 */ "vaq\t\0" + /* 12173 */ "vacq\t\0" + /* 12179 */ "vaccq\t\0" + /* 12186 */ "vacccq\t\0" + /* 12194 */ "vceq\t\0" + /* 12200 */ "vsbcbiq\t\0" + /* 12209 */ "vscbiq\t\0" + /* 12217 */ "vsbiq\t\0" + /* 12224 */ "vsumq\t\0" + /* 12231 */ "lpq\t\0" + /* 12236 */ "stpq\t\0" + /* 12242 */ "vlbrq\t\0" + /* 12249 */ "vstbrq\t\0" + /* 12257 */ "vfsq\t\0" + /* 12263 */ "vsq\t\0" + /* 12268 */ "lbear\t\0" + /* 12275 */ "stbear\t\0" + /* 12283 */ "epar\t\0" + /* 12289 */ "esar\t\0" + /* 12295 */ "ssar\t\0" + /* 12301 */ "tar\t\0" + /* 12306 */ "madbr\t\0" + /* 12313 */ "lcdbr\t\0" + /* 12320 */ "ddbr\t\0" + /* 12326 */ "ledbr\t\0" + /* 12333 */ "cfdbr\t\0" + /* 12340 */ "clfdbr\t\0" + /* 12348 */ "cgdbr\t\0" + /* 12355 */ "clgdbr\t\0" + /* 12363 */ "didbr\t\0" + /* 12370 */ "fidbr\t\0" + /* 12377 */ "kdbr\t\0" + /* 12383 */ "mdbr\t\0" + /* 12389 */ "lndbr\t\0" + /* 12396 */ "lpdbr\t\0" + /* 12403 */ "sqdbr\t\0" + /* 12410 */ "msdbr\t\0" + /* 12417 */ "ltdbr\t\0" + /* 12424 */ "lxdbr\t\0" + /* 12431 */ "mxdbr\t\0" + /* 12438 */ "maebr\t\0" + /* 12445 */ "lcebr\t\0" + /* 12452 */ "ldebr\t\0" + /* 12459 */ "mdebr\t\0" + /* 12466 */ "meebr\t\0" + /* 12473 */ "cfebr\t\0" + /* 12480 */ "clfebr\t\0" + /* 12488 */ "cgebr\t\0" + /* 12495 */ "clgebr\t\0" + /* 12503 */ "diebr\t\0" + /* 12510 */ "fiebr\t\0" + /* 12517 */ "kebr\t\0" + /* 12523 */ "lnebr\t\0" + /* 12530 */ "lpebr\t\0" + /* 12537 */ "sqebr\t\0" + /* 12544 */ "msebr\t\0" + /* 12551 */ "ltebr\t\0" + /* 12558 */ "lxebr\t\0" + /* 12565 */ "cdfbr\t\0" + /* 12572 */ "cefbr\t\0" + /* 12579 */ "cdlfbr\t\0" + /* 12587 */ "celfbr\t\0" + /* 12595 */ "cxlfbr\t\0" + /* 12603 */ "cxfbr\t\0" + /* 12610 */ "cdgbr\t\0" + /* 12617 */ "cegbr\t\0" + /* 12624 */ "cdlgbr\t\0" + /* 12632 */ "celgbr\t\0" + /* 12640 */ "cxlgbr\t\0" + /* 12648 */ "cxgbr\t\0" + /* 12655 */ "slbr\t\0" + /* 12661 */ "vlbr\t\0" + /* 12667 */ "vstbr\t\0" + /* 12674 */ "axbr\t\0" + /* 12680 */ "lcxbr\t\0" + /* 12687 */ "ldxbr\t\0" + /* 12694 */ "lexbr\t\0" + /* 12701 */ "cfxbr\t\0" + /* 12708 */ "clfxbr\t\0" + /* 12716 */ "cgxbr\t\0" + /* 12723 */ "clgxbr\t\0" + /* 12731 */ "fixbr\t\0" + /* 12738 */ "kxbr\t\0" + /* 12744 */ "mxbr\t\0" + /* 12750 */ "lnxbr\t\0" + /* 12757 */ "lpxbr\t\0" + /* 12764 */ "sqxbr\t\0" + /* 12771 */ "sxbr\t\0" + /* 12777 */ "ltxbr\t\0" + /* 12784 */ "bcr\t\0" + /* 12789 */ "llgcr\t\0" + /* 12796 */ "alcr\t\0" + /* 12802 */ "llcr\t\0" + /* 12808 */ "locr\t\0" + /* 12814 */ "madr\t\0" + /* 12820 */ "tbdr\t\0" + /* 12826 */ "lcdr\t\0" + /* 12832 */ "ddr\t\0" + /* 12837 */ "tbedr\t\0" + /* 12844 */ "ledr\t\0" + /* 12850 */ "cfdr\t\0" + /* 12856 */ "cgdr\t\0" + /* 12862 */ "lgdr\t\0" + /* 12868 */ "thdr\t\0" + /* 12874 */ "fidr\t\0" + /* 12880 */ "ldr\t\0" + /* 12885 */ "mdr\t\0" + /* 12890 */ "lndr\t\0" + /* 12896 */ "lpdr\t\0" + /* 12902 */ "sqdr\t\0" + /* 12908 */ "lrdr\t\0" + /* 12914 */ "msdr\t\0" + /* 12920 */ "cpsdr\t\0" + /* 12927 */ "ltdr\t\0" + /* 12933 */ "lxdr\t\0" + /* 12939 */ "mxdr\t\0" + /* 12945 */ "lzdr\t\0" + /* 12951 */ "maer\t\0" + /* 12957 */ "ber\t\0" + /* 12962 */ "lcer\t\0" + /* 12968 */ "thder\t\0" + /* 12975 */ "lder\t\0" + /* 12981 */ "mder\t\0" + /* 12987 */ "meer\t\0" + /* 12993 */ "cfer\t\0" + /* 12999 */ "cger\t\0" + /* 13005 */ "bher\t\0" + /* 13011 */ "bnher\t\0" + /* 13018 */ "fier\t\0" + /* 13024 */ "bler\t\0" + /* 13030 */ "bnler\t\0" + /* 13037 */ "vler\t\0" + /* 13043 */ "mer\t\0" + /* 13048 */ "bner\t\0" + /* 13054 */ "lner\t\0" + /* 13060 */ "lper\t\0" + /* 13066 */ "sqer\t\0" + /* 13072 */ "lrer\t\0" + /* 13078 */ "mser\t\0" + /* 13084 */ "lter\t\0" + /* 13090 */ "vster\t\0" + /* 13097 */ "lxer\t\0" + /* 13103 */ "lzer\t\0" + /* 13109 */ "lcdfr\t\0" + /* 13116 */ "lndfr\t\0" + /* 13123 */ "lpdfr\t\0" + /* 13130 */ "cefr\t\0" + /* 13136 */ "agfr\t\0" + /* 13142 */ "lcgfr\t\0" + /* 13149 */ "algfr\t\0" + /* 13156 */ "clgfr\t\0" + /* 13163 */ "llgfr\t\0" + /* 13170 */ "slgfr\t\0" + /* 13177 */ "lngfr\t\0" + /* 13184 */ "lpgfr\t\0" + /* 13191 */ "dsgfr\t\0" + /* 13198 */ "msgfr\t\0" + /* 13205 */ "ltgfr\t\0" + /* 13212 */ "cxfr\t\0" + /* 13218 */ "agr\t\0" + /* 13223 */ "slbgr\t\0" + /* 13230 */ "alcgr\t\0" + /* 13237 */ "locgr\t\0" + /* 13244 */ "cdgr\t\0" + /* 13250 */ "ldgr\t\0" + /* 13256 */ "cegr\t\0" + /* 13262 */ "algr\t\0" + /* 13268 */ "clgr\t\0" + /* 13274 */ "dlgr\t\0" + /* 13280 */ "selgr\t\0" + /* 13287 */ "mlgr\t\0" + /* 13293 */ "slgr\t\0" + /* 13299 */ "lngr\t\0" + /* 13305 */ "flogr\t\0" + /* 13312 */ "lpgr\t\0" + /* 13318 */ "dsgr\t\0" + /* 13324 */ "msgr\t\0" + /* 13330 */ "bctgr\t\0" + /* 13337 */ "ltgr\t\0" + /* 13343 */ "lrvgr\t\0" + /* 13350 */ "cxgr\t\0" + /* 13356 */ "bhr\t\0" + /* 13361 */ "locfhr\t\0" + /* 13369 */ "selfhr\t\0" + /* 13377 */ "llghr\t\0" + /* 13384 */ "chhr\t\0" + /* 13390 */ "ahhhr\t\0" + /* 13397 */ "alhhhr\t\0" + /* 13405 */ "slhhhr\t\0" + /* 13413 */ "shhhr\t\0" + /* 13420 */ "clhhr\t\0" + /* 13427 */ "blhr\t\0" + /* 13433 */ "llhr\t\0" + /* 13439 */ "bnlhr\t\0" + /* 13446 */ "bnhr\t\0" + /* 13452 */ "mayhr\t\0" + /* 13459 */ "myhr\t\0" + /* 13465 */ "epair\t\0" + /* 13472 */ "esair\t\0" + /* 13479 */ "ssair\t\0" + /* 13486 */ "bakr\t\0" + /* 13492 */ "balr\t\0" + /* 13498 */ "blr\t\0" + /* 13503 */ "clr\t\0" + /* 13508 */ "dlr\t\0" + /* 13513 */ "selr\t\0" + /* 13519 */ "vflr\t\0" + /* 13525 */ "chlr\t\0" + /* 13531 */ "ahhlr\t\0" + /* 13538 */ "alhhlr\t\0" + /* 13546 */ "slhhlr\t\0" + /* 13554 */ "shhlr\t\0" + /* 13561 */ "clhlr\t\0" + /* 13568 */ "mlr\t\0" + /* 13573 */ "bnlr\t\0" + /* 13579 */ "vlrlr\t\0" + /* 13586 */ "vstrlr\t\0" + /* 13594 */ "slr\t\0" + /* 13599 */ "vlr\t\0" + /* 13604 */ "maylr\t\0" + /* 13611 */ "mylr\t\0" + /* 13617 */ "bmr\t\0" + /* 13622 */ "bnmr\t\0" + /* 13628 */ "lnr\t\0" + /* 13633 */ "bor\t\0" + /* 13638 */ "bnor\t\0" + /* 13644 */ "bpr\t\0" + /* 13649 */ "lpr\t\0" + /* 13654 */ "bnpr\t\0" + /* 13660 */ "vsrpr\t\0" + /* 13667 */ "basr\t\0" + /* 13673 */ "sfasr\t\0" + /* 13680 */ "msr\t\0" + /* 13685 */ "bctr\t\0" + /* 13691 */ "ecctr\t\0" + /* 13698 */ "scctr\t\0" + /* 13705 */ "kmctr\t\0" + /* 13712 */ "epctr\t\0" + /* 13719 */ "spctr\t\0" + /* 13726 */ "qadtr\t\0" + /* 13733 */ "cdtr\t\0" + /* 13739 */ "ddtr\t\0" + /* 13745 */ "cedtr\t\0" + /* 13752 */ "eedtr\t\0" + /* 13759 */ "iedtr\t\0" + /* 13766 */ "ledtr\t\0" + /* 13773 */ "cfdtr\t\0" + /* 13780 */ "clfdtr\t\0" + /* 13788 */ "cgdtr\t\0" + /* 13795 */ "clgdtr\t\0" + /* 13803 */ "fidtr\t\0" + /* 13810 */ "kdtr\t\0" + /* 13816 */ "mdtr\t\0" + /* 13822 */ "rrdtr\t\0" + /* 13829 */ "csdtr\t\0" + /* 13836 */ "esdtr\t\0" + /* 13843 */ "ltdtr\t\0" + /* 13850 */ "cudtr\t\0" + /* 13857 */ "lxdtr\t\0" + /* 13864 */ "ldetr\t\0" + /* 13871 */ "cdftr\t\0" + /* 13878 */ "cdlftr\t\0" + /* 13886 */ "cxlftr\t\0" + /* 13894 */ "cxftr\t\0" + /* 13901 */ "cdgtr\t\0" + /* 13908 */ "cdlgtr\t\0" + /* 13916 */ "llgtr\t\0" + /* 13923 */ "cxlgtr\t\0" + /* 13931 */ "cxgtr\t\0" + /* 13938 */ "ltr\t\0" + /* 13943 */ "trtr\t\0" + /* 13949 */ "cdstr\t\0" + /* 13956 */ "vistr\t\0" + /* 13963 */ "cxstr\t\0" + /* 13970 */ "cdutr\t\0" + /* 13977 */ "cxutr\t\0" + /* 13984 */ "qaxtr\t\0" + /* 13991 */ "cxtr\t\0" + /* 13997 */ "ldxtr\t\0" + /* 14004 */ "cextr\t\0" + /* 14011 */ "eextr\t\0" + /* 14018 */ "iextr\t\0" + /* 14025 */ "cfxtr\t\0" + /* 14032 */ "clfxtr\t\0" + /* 14040 */ "cgxtr\t\0" + /* 14047 */ "clgxtr\t\0" + /* 14055 */ "fixtr\t\0" + /* 14062 */ "kxtr\t\0" + /* 14068 */ "mxtr\t\0" + /* 14074 */ "rrxtr\t\0" + /* 14081 */ "csxtr\t\0" + /* 14088 */ "esxtr\t\0" + /* 14095 */ "ltxtr\t\0" + /* 14102 */ "cuxtr\t\0" + /* 14109 */ "aur\t\0" + /* 14114 */ "sur\t\0" + /* 14119 */ "lrvr\t\0" + /* 14125 */ "awr\t\0" + /* 14130 */ "swr\t\0" + /* 14135 */ "axr\t\0" + /* 14140 */ "lcxr\t\0" + /* 14146 */ "ldxr\t\0" + /* 14152 */ "lexr\t\0" + /* 14158 */ "cfxr\t\0" + /* 14164 */ "cgxr\t\0" + /* 14170 */ "fixr\t\0" + /* 14176 */ "lxr\t\0" + /* 14181 */ "mxr\t\0" + /* 14186 */ "lnxr\t\0" + /* 14192 */ "lpxr\t\0" + /* 14198 */ "sqxr\t\0" + /* 14204 */ "sxr\t\0" + /* 14209 */ "ltxr\t\0" + /* 14215 */ "lzxr\t\0" + /* 14221 */ "mayr\t\0" + /* 14227 */ "myr\t\0" + /* 14232 */ "bzr\t\0" + /* 14237 */ "vpkzr\t\0" + /* 14244 */ "bnzr\t\0" + /* 14250 */ "bas\t\0" + /* 14255 */ "lfas\t\0" + /* 14261 */ "bras\t\0" + /* 14267 */ "vstrcbs\t\0" + /* 14276 */ "vfcedbs\t\0" + /* 14285 */ "wfcedbs\t\0" + /* 14294 */ "vfchedbs\t\0" + /* 14304 */ "wfchedbs\t\0" + /* 14314 */ "vfkhedbs\t\0" + /* 14324 */ "wfkhedbs\t\0" + /* 14334 */ "vfkedbs\t\0" + /* 14343 */ "wfkedbs\t\0" + /* 14352 */ "vfchdbs\t\0" + /* 14361 */ "wfchdbs\t\0" + /* 14370 */ "vfkhdbs\t\0" + /* 14379 */ "wfkhdbs\t\0" + /* 14388 */ "vfaebs\t\0" + /* 14396 */ "vfeebs\t\0" + /* 14404 */ "vfenebs\t\0" + /* 14413 */ "vchbs\t\0" + /* 14420 */ "vchlbs\t\0" + /* 14428 */ "vceqbs\t\0" + /* 14436 */ "vistrbs\t\0" + /* 14445 */ "vfcesbs\t\0" + /* 14454 */ "wfcesbs\t\0" + /* 14463 */ "vfchesbs\t\0" + /* 14473 */ "wfchesbs\t\0" + /* 14483 */ "vfkhesbs\t\0" + /* 14493 */ "wfkhesbs\t\0" + /* 14503 */ "vfkesbs\t\0" + /* 14512 */ "wfkesbs\t\0" + /* 14521 */ "vfchsbs\t\0" + /* 14530 */ "wfchsbs\t\0" + /* 14539 */ "vfkhsbs\t\0" + /* 14548 */ "wfkhsbs\t\0" + /* 14557 */ "wfcexbs\t\0" + /* 14566 */ "wfchexbs\t\0" + /* 14576 */ "wfkhexbs\t\0" + /* 14586 */ "wfkexbs\t\0" + /* 14595 */ "wfchxbs\t\0" + /* 14604 */ "wfkhxbs\t\0" + /* 14613 */ "vstrczbs\t\0" + /* 14623 */ "vfaezbs\t\0" + /* 14632 */ "vfeezbs\t\0" + /* 14641 */ "vfenezbs\t\0" + /* 14651 */ "mvcs\t\0" + /* 14657 */ "cds\t\0" + /* 14662 */ "vstrcfs\t\0" + /* 14671 */ "vfaefs\t\0" + /* 14679 */ "vfeefs\t\0" + /* 14687 */ "vfenefs\t\0" + /* 14696 */ "vchfs\t\0" + /* 14703 */ "vchlfs\t\0" + /* 14711 */ "vceqfs\t\0" + /* 14719 */ "vistrfs\t\0" + /* 14728 */ "vpksfs\t\0" + /* 14736 */ "vpklsfs\t\0" + /* 14745 */ "vfs\t\0" + /* 14750 */ "vstrczfs\t\0" + /* 14760 */ "vfaezfs\t\0" + /* 14769 */ "vfeezfs\t\0" + /* 14778 */ "vfenezfs\t\0" + /* 14788 */ "vchgs\t\0" + /* 14795 */ "vchlgs\t\0" + /* 14803 */ "vceqgs\t\0" + /* 14811 */ "vpksgs\t\0" + /* 14819 */ "vpklsgs\t\0" + /* 14828 */ "vstrchs\t\0" + /* 14837 */ "vfaehs\t\0" + /* 14845 */ "vfeehs\t\0" + /* 14853 */ "vfenehs\t\0" + /* 14862 */ "vchhs\t\0" + /* 14869 */ "vchlhs\t\0" + /* 14877 */ "vceqhs\t\0" + /* 14885 */ "vistrhs\t\0" + /* 14894 */ "vpkshs\t\0" + /* 14902 */ "vpklshs\t\0" + /* 14911 */ "vstrczhs\t\0" + /* 14921 */ "vfaezhs\t\0" + /* 14930 */ "vfeezhs\t\0" + /* 14939 */ "vfenezhs\t\0" + /* 14949 */ "vpks\t\0" + /* 14955 */ "vpkls\t\0" + /* 14962 */ "vflls\t\0" + /* 14969 */ "wflls\t\0" + /* 14976 */ "vfms\t\0" + /* 14982 */ "vfnms\t\0" + /* 14989 */ "mvcos\t\0" + /* 14996 */ "stcps\t\0" + /* 15003 */ "vcfps\t\0" + /* 15010 */ "vstrs\t\0" + /* 15017 */ "ts\t\0" + /* 15021 */ "vs\t\0" + /* 15025 */ "llgfat\t\0" + /* 15033 */ "lgat\t\0" + /* 15039 */ "lfhat\t\0" + /* 15046 */ "lat\t\0" + /* 15051 */ "llgtat\t\0" + /* 15059 */ "bct\t\0" + /* 15064 */ "vpopct\t\0" + /* 15072 */ "brct\t\0" + /* 15078 */ "tdcdt\t\0" + /* 15085 */ "tdgdt\t\0" + /* 15092 */ "sldt\t\0" + /* 15098 */ "cpdt\t\0" + /* 15104 */ "srdt\t\0" + /* 15110 */ "czdt\t\0" + /* 15116 */ "tdcet\t\0" + /* 15123 */ "tdget\t\0" + /* 15130 */ "clgt\t\0" + /* 15136 */ "llgt\t\0" + /* 15142 */ "cit\t\0" + /* 15147 */ "clfit\t\0" + /* 15154 */ "cgit\t\0" + /* 15160 */ "clgit\t\0" + /* 15167 */ "clt\t\0" + /* 15172 */ "srnmt\t\0" + /* 15179 */ "popcnt\t\0" + /* 15187 */ "tprot\t\0" + /* 15194 */ "trot\t\0" + /* 15200 */ "cdpt\t\0" + /* 15206 */ "spt\t\0" + /* 15211 */ "stpt\t\0" + /* 15217 */ "cxpt\t\0" + /* 15223 */ "crt\t\0" + /* 15228 */ "cgrt\t\0" + /* 15234 */ "clgrt\t\0" + /* 15241 */ "clrt\t\0" + /* 15247 */ "tabort\t\0" + /* 15255 */ "trt\t\0" + /* 15260 */ "clst\t\0" + /* 15266 */ "srst\t\0" + /* 15272 */ "csst\t\0" + /* 15278 */ "mvst\t\0" + /* 15284 */ "trtt\t\0" + /* 15290 */ "pgout\t\0" + /* 15297 */ "tdcxt\t\0" + /* 15304 */ "tdgxt\t\0" + /* 15311 */ "slxt\t\0" + /* 15317 */ "cpxt\t\0" + /* 15323 */ "srxt\t\0" + /* 15329 */ "czxt\t\0" + /* 15335 */ "cdzt\t\0" + /* 15341 */ "cxzt\t\0" + /* 15347 */ "au\t\0" + /* 15351 */ "cutfu\t\0" + /* 15358 */ "unpku\t\0" + /* 15365 */ "clclu\t\0" + /* 15372 */ "mvclu\t\0" + /* 15379 */ "su\t\0" + /* 15383 */ "srstu\t\0" + /* 15390 */ "vesrav\t\0" + /* 15398 */ "vlgv\t\0" + /* 15404 */ "verllv\t\0" + /* 15412 */ "vesrlv\t\0" + /* 15420 */ "veslv\t\0" + /* 15427 */ "lrv\t\0" + /* 15432 */ "strv\t\0" + /* 15438 */ "aw\t\0" + /* 15442 */ "vmalhw\t\0" + /* 15450 */ "vmlhw\t\0" + /* 15457 */ "vuplhw\t\0" + /* 15465 */ "stcrw\t\0" + /* 15472 */ "epsw\t\0" + /* 15478 */ "lpsw\t\0" + /* 15484 */ "lax\t\0" + /* 15489 */ "vfmax\t\0" + /* 15496 */ "ex\t\0" + /* 15500 */ "vmx\t\0" + /* 15505 */ "vnx\t\0" + /* 15510 */ "spx\t\0" + /* 15515 */ "stpx\t\0" + /* 15521 */ "wflrx\t\0" + /* 15528 */ "vx\t\0" + /* 15532 */ "lay\t\0" + /* 15537 */ "may\t\0" + /* 15542 */ "lray\t\0" + /* 15548 */ "cvby\t\0" + /* 15554 */ "icy\t\0" + /* 15559 */ "stcy\t\0" + /* 15565 */ "ldy\t\0" + /* 15570 */ "stdy\t\0" + /* 15576 */ "cvdy\t\0" + /* 15582 */ "laey\t\0" + /* 15588 */ "ley\t\0" + /* 15593 */ "stey\t\0" + /* 15599 */ "lpswey\t\0" + /* 15607 */ "mfy\t\0" + /* 15612 */ "ahy\t\0" + /* 15617 */ "chy\t\0" + /* 15622 */ "lhy\t\0" + /* 15627 */ "mhy\t\0" + /* 15632 */ "shy\t\0" + /* 15637 */ "sthy\t\0" + /* 15643 */ "cliy\t\0" + /* 15649 */ "niy\t\0" + /* 15654 */ "oiy\t\0" + /* 15659 */ "mviy\t\0" + /* 15665 */ "xiy\t\0" + /* 15670 */ "aly\t\0" + /* 15675 */ "cly\t\0" + /* 15680 */ "sly\t\0" + /* 15685 */ "lamy\t\0" + /* 15691 */ "stamy\t\0" + /* 15698 */ "icmy\t\0" + /* 15704 */ "stcmy\t\0" + /* 15711 */ "clmy\t\0" + /* 15717 */ "stmy\t\0" + /* 15723 */ "ny\t\0" + /* 15727 */ "oy\t\0" + /* 15731 */ "csy\t\0" + /* 15736 */ "cdsy\t\0" + /* 15742 */ "msy\t\0" + /* 15747 */ "sty\t\0" + /* 15752 */ "xy\t\0" + /* 15756 */ "bz\t\0" + /* 15760 */ "locz\t\0" + /* 15766 */ "stocz\t\0" + /* 15773 */ "vllez\t\0" + /* 15780 */ "locgz\t\0" + /* 15787 */ "stocgz\t\0" + /* 15795 */ "jgz\t\0" + /* 15800 */ "locfhz\t\0" + /* 15808 */ "stocfhz\t\0" + /* 15817 */ "biz\t\0" + /* 15822 */ "lochiz\t\0" + /* 15830 */ "locghiz\t\0" + /* 15839 */ "lochhiz\t\0" + /* 15848 */ "jz\t\0" + /* 15852 */ "vupkz\t\0" + /* 15859 */ "vpkz\t\0" + /* 15865 */ "vclz\t\0" + /* 15871 */ "bnz\t\0" + /* 15876 */ "locnz\t\0" + /* 15883 */ "stocnz\t\0" + /* 15891 */ "locgnz\t\0" + /* 15899 */ "stocgnz\t\0" + /* 15908 */ "jgnz\t\0" + /* 15914 */ "locfhnz\t\0" + /* 15923 */ "stocfhnz\t\0" + /* 15933 */ "binz\t\0" + /* 15939 */ "lochinz\t\0" + /* 15948 */ "locghinz\t\0" + /* 15958 */ "lochhinz\t\0" + /* 15968 */ "jnz\t\0" + /* 15973 */ "locrnz\t\0" + /* 15981 */ "locgrnz\t\0" + /* 15990 */ "selgrnz\t\0" + /* 15999 */ "locfhrnz\t\0" + /* 16009 */ "selfhrnz\t\0" + /* 16019 */ "selrnz\t\0" + /* 16027 */ "vllebrz\t\0" + /* 16036 */ "locrz\t\0" + /* 16043 */ "locgrz\t\0" + /* 16051 */ "selgrz\t\0" + /* 16059 */ "locfhrz\t\0" + /* 16068 */ "selfhrz\t\0" + /* 16077 */ "selrz\t\0" + /* 16084 */ "vctz\t\0" + /* 16090 */ "mvz\t\0" + /* 16095 */ ".insn e,\0" + /* 16104 */ ".insn rie,\0" + /* 16115 */ ".insn rre,\0" + /* 16126 */ ".insn rse,\0" + /* 16137 */ ".insn sse,\0" + /* 16148 */ ".insn rxe,\0" + /* 16159 */ ".insn rrf,\0" + /* 16170 */ ".insn ssf,\0" + /* 16181 */ ".insn rxf,\0" + /* 16192 */ ".insn ri,\0" + /* 16202 */ ".insn vri,\0" + /* 16213 */ ".insn si,\0" + /* 16223 */ ".insn rsi,\0" + /* 16234 */ ".insn vsi,\0" + /* 16245 */ ".insn ril,\0" + /* 16256 */ ".insn sil,\0" + /* 16267 */ ".insn rr,\0" + /* 16277 */ ".insn vrr,\0" + /* 16288 */ ".insn s,\0" + /* 16297 */ ".insn ris,\0" + /* 16308 */ ".insn rs,\0" + /* 16318 */ ".insn rrs,\0" + /* 16329 */ ".insn vrs,\0" + /* 16340 */ ".insn ss,\0" + /* 16350 */ ".insn rilu,\0" + /* 16362 */ ".insn vrv,\0" + /* 16373 */ ".insn rx,\0" + /* 16383 */ ".insn vrx,\0" + /* 16394 */ ".insn siy,\0" + /* 16405 */ ".insn rsy,\0" + /* 16416 */ ".insn rxy,\0" + /* 16427 */ "# XRay Function Patchable RET.\0" + /* 16458 */ "# XRay Typed Event Log.\0" + /* 16482 */ "# XRay Custom Event Log.\0" + /* 16507 */ "# XRay Function Enter.\0" + /* 16530 */ "# XRay Tail Call Exit.\0" + /* 16553 */ "# XRay Function Exit.\0" + /* 16575 */ "sam31\0" + /* 16581 */ "trap2\0" + /* 16587 */ "sam24\0" + /* 16593 */ "sam64\0" + /* 16599 */ "LIFETIME_END\0" + /* 16612 */ "PSEUDO_PROBE\0" + /* 16625 */ "BUNDLE\0" + /* 16632 */ "DBG_VALUE\0" + /* 16642 */ "DBG_INSTR_REF\0" + /* 16656 */ "DBG_PHI\0" + /* 16664 */ "DBG_LABEL\0" + /* 16674 */ "LIFETIME_START\0" + /* 16689 */ "DBG_VALUE_LIST\0" + /* 16704 */ "nnpa\0" + /* 16709 */ "cib\0" + /* 16713 */ "cgib\0" + /* 16718 */ "clgib\0" + /* 16724 */ "clib\0" + /* 16729 */ "palb\0" + /* 16734 */ "ptlb\0" + /* 16739 */ "crb\0" + /* 16743 */ "cgrb\0" + /* 16748 */ "clgrb\0" + /* 16754 */ "clrb\0" + /* 16759 */ "pcc\0" + /* 16763 */ "loc\0" + /* 16767 */ "stoc\0" + /* 16772 */ "tend\0" + /* 16777 */ "ptff\0" + /* 16782 */ "sckpf\0" + /* 16788 */ "locg\0" + /* 16793 */ "stocg\0" + /* 16799 */ "jg\0" + /* 16802 */ "csch\0" + /* 16807 */ "hsch\0" + /* 16812 */ "rsch\0" + /* 16817 */ "xsch\0" + /* 16822 */ "locfh\0" + /* 16828 */ "stocfh\0" + /* 16835 */ "bi\0" + /* 16838 */ "lochi\0" + /* 16844 */ "locghi\0" + /* 16851 */ "lochhi\0" + /* 16858 */ "cij\0" + /* 16862 */ "cgij\0" + /* 16867 */ "clgij\0" + /* 16873 */ "clij\0" + /* 16878 */ "crj\0" + /* 16882 */ "cgrj\0" + /* 16887 */ "clgrj\0" + /* 16893 */ "clrj\0" + /* 16898 */ "ipk\0" + /* 16902 */ "sal\0" + /* 16906 */ "# FEntry call\0" + /* 16920 */ "tam\0" + /* 16924 */ "schm\0" + /* 16929 */ "pckmo\0" + /* 16935 */ "pfpo\0" + /* 16940 */ "rchp\0" + /* 16945 */ "nop\0" + /* 16949 */ "locr\0" + /* 16954 */ "locgr\0" + /* 16960 */ "selgr\0" + /* 16966 */ "locfhr\0" + /* 16973 */ "selfhr\0" + /* 16980 */ "selr\0" + /* 16985 */ "pr\0" + /* 16988 */ "clgt\0" + /* 16993 */ "cit\0" + /* 16997 */ "clfit\0" + /* 17003 */ "cgit\0" + /* 17008 */ "clgit\0" + /* 17014 */ "clt\0" + /* 17018 */ "upt\0" + /* 17022 */ "crt\0" + /* 17026 */ "cgrt\0" + /* 17031 */ "clgrt\0" + /* 17037 */ "clrt\0" +}; +#endif // CAPSTONE_DIET static const uint32_t OpInfo0[] = { 0U, // PHI 0U, // INLINEASM + 0U, // INLINEASM_BR 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL @@ -2237,28 +2398,40 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS - 15368U, // DBG_VALUE - 15378U, // DBG_LABEL + 16633U, // DBG_VALUE + 16690U, // DBG_VALUE_LIST + 16643U, // DBG_INSTR_REF + 16657U, // DBG_PHI + 16665U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY - 15361U, // BUNDLE - 15388U, // LIFETIME_START - 15348U, // LIFETIME_END + 16626U, // BUNDLE + 16675U, // LIFETIME_START + 16600U, // LIFETIME_END + 16613U, // PSEUDO_PROBE + 0U, // ARITH_FENCE 0U, // STACKMAP - 15600U, // FENTRY_CALL + 16907U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP - 15256U, // PATCHABLE_FUNCTION_ENTER - 15176U, // PATCHABLE_RET - 15302U, // PATCHABLE_FUNCTION_EXIT - 15279U, // PATCHABLE_TAIL_CALL - 15231U, // PATCHABLE_EVENT_CALL - 15207U, // PATCHABLE_TYPED_EVENT_CALL + 16508U, // PATCHABLE_FUNCTION_ENTER + 16428U, // PATCHABLE_RET + 16554U, // PATCHABLE_FUNCTION_EXIT + 16531U, // PATCHABLE_TAIL_CALL + 16483U, // PATCHABLE_EVENT_CALL + 16459U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL + 0U, // MEMBARRIER + 0U, // JUMP_TABLE_DEBUG_INFO + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ASSERT_ALIGN 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL @@ -2266,6 +2439,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR @@ -2273,17 +2448,33 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE + 0U, // G_CONSTANT_POOL 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_CONSTANT_FOLD_BARRIER + 0U, // G_INTRINSIC_FPTRUNC_ROUND + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD 0U, // G_STORE + 0U, // G_INDEXED_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG @@ -2297,10 +2488,21 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_ATOMICRMW_FMAX + 0U, // G_ATOMICRMW_FMIN + 0U, // G_ATOMICRMW_UINC_WRAP + 0U, // G_ATOMICRMW_UDEC_WRAP + 0U, // G_FENCE + 0U, // G_PREFETCH 0U, // G_BRCOND 0U, // G_BRINDIRECT + 0U, // G_INVOKE_REGION_START 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_INTRINSIC_CONVERGENT + 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT @@ -2308,32 +2510,61 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT + 0U, // G_SEXT_INREG 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT + 0U, // G_UADDO 0U, // G_UADDE + 0U, // G_USUBO 0U, // G_USUBE 0U, // G_SADDO + 0U, // G_SADDE 0U, // G_SSUBO + 0U, // G_SSUBE 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA + 0U, // G_FMAD 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW + 0U, // G_FPOWI 0U, // G_FEXP 0U, // G_FEXP2 + 0U, // G_FEXP10 0U, // G_FLOG 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FLDEXP + 0U, // G_FFREXP 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC @@ -2342,21 +2573,103 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS - 0U, // G_GEP - 0U, // G_PTR_MASK + 0U, // G_FCOPYSIGN + 0U, // G_IS_FPCLASS + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_GET_FPENV + 0U, // G_SET_FPENV + 0U, // G_RESET_FPENV + 0U, // G_GET_FPMODE + 0U, // G_SET_FPMODE + 0U, // G_RESET_FPMODE + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND 0U, // G_BR + 0U, // G_BRJT 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STACKSAVE + 0U, // G_STACKRESTORE + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_STRICT_FLDEXP + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_FMAXIMUM + 0U, // G_VECREDUCE_FMINIMUM + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ADA_ENTRY + 0U, // ADA_ENTRY_VALUE + 0U, // ADB_MemFoldPseudo 0U, // ADJCALLSTACKDOWN 0U, // ADJCALLSTACKUP 0U, // ADJDYNALLOC + 0U, // AEB_MemFoldPseudo 0U, // AEXT128 0U, // AFIMux + 0U, // AG_MemFoldPseudo 0U, // AHIMux 0U, // AHIMuxK + 0U, // ALG_MemFoldPseudo + 0U, // AL_MemFoldPseudo 0U, // ATOMIC_CMP_SWAPW 0U, // ATOMIC_LOADW_AFI 0U, // ATOMIC_LOADW_AR @@ -2373,63 +2686,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // ATOMIC_LOADW_UMIN 0U, // ATOMIC_LOADW_XILF 0U, // ATOMIC_LOADW_XR - 0U, // ATOMIC_LOAD_AFI - 0U, // ATOMIC_LOAD_AGFI - 0U, // ATOMIC_LOAD_AGHI - 0U, // ATOMIC_LOAD_AGR - 0U, // ATOMIC_LOAD_AHI - 0U, // ATOMIC_LOAD_AR - 0U, // ATOMIC_LOAD_MAX_32 - 0U, // ATOMIC_LOAD_MAX_64 - 0U, // ATOMIC_LOAD_MIN_32 - 0U, // ATOMIC_LOAD_MIN_64 - 0U, // ATOMIC_LOAD_NGR - 0U, // ATOMIC_LOAD_NGRi - 0U, // ATOMIC_LOAD_NIHF64 - 0U, // ATOMIC_LOAD_NIHF64i - 0U, // ATOMIC_LOAD_NIHH64 - 0U, // ATOMIC_LOAD_NIHH64i - 0U, // ATOMIC_LOAD_NIHL64 - 0U, // ATOMIC_LOAD_NIHL64i - 0U, // ATOMIC_LOAD_NILF - 0U, // ATOMIC_LOAD_NILF64 - 0U, // ATOMIC_LOAD_NILF64i - 0U, // ATOMIC_LOAD_NILFi - 0U, // ATOMIC_LOAD_NILH - 0U, // ATOMIC_LOAD_NILH64 - 0U, // ATOMIC_LOAD_NILH64i - 0U, // ATOMIC_LOAD_NILHi - 0U, // ATOMIC_LOAD_NILL - 0U, // ATOMIC_LOAD_NILL64 - 0U, // ATOMIC_LOAD_NILL64i - 0U, // ATOMIC_LOAD_NILLi - 0U, // ATOMIC_LOAD_NR - 0U, // ATOMIC_LOAD_NRi - 0U, // ATOMIC_LOAD_OGR - 0U, // ATOMIC_LOAD_OIHF64 - 0U, // ATOMIC_LOAD_OIHH64 - 0U, // ATOMIC_LOAD_OIHL64 - 0U, // ATOMIC_LOAD_OILF - 0U, // ATOMIC_LOAD_OILF64 - 0U, // ATOMIC_LOAD_OILH - 0U, // ATOMIC_LOAD_OILH64 - 0U, // ATOMIC_LOAD_OILL - 0U, // ATOMIC_LOAD_OILL64 - 0U, // ATOMIC_LOAD_OR - 0U, // ATOMIC_LOAD_SGR - 0U, // ATOMIC_LOAD_SR - 0U, // ATOMIC_LOAD_UMAX_32 - 0U, // ATOMIC_LOAD_UMAX_64 - 0U, // ATOMIC_LOAD_UMIN_32 - 0U, // ATOMIC_LOAD_UMIN_64 - 0U, // ATOMIC_LOAD_XGR - 0U, // ATOMIC_LOAD_XIHF64 - 0U, // ATOMIC_LOAD_XILF - 0U, // ATOMIC_LOAD_XILF64 - 0U, // ATOMIC_LOAD_XR 0U, // ATOMIC_SWAPW - 0U, // ATOMIC_SWAP_32 - 0U, // ATOMIC_SWAP_64 + 0U, // A_MemFoldPseudo 0U, // CFIMux 0U, // CGIBCall 0U, // CGIBReturn @@ -2438,8 +2696,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CHIMux 0U, // CIBCall 0U, // CIBReturn - 0U, // CLCLoop - 0U, // CLCSequence + 0U, // CLCImm + 0U, // CLCReg 0U, // CLFIMux 0U, // CLGIBCall 0U, // CLGIBReturn @@ -2455,12 +2713,16 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CRBCall 0U, // CRBReturn 0U, // CallBASR + 0U, // CallBASR_STACKEXT + 0U, // CallBASR_XPLINK64 0U, // CallBCR 0U, // CallBR 0U, // CallBRASL + 0U, // CallBRASL_XPLINK64 0U, // CallBRCL 0U, // CallJG 0U, // CondReturn + 0U, // CondReturn_XPLINK 0U, // CondStore16 0U, // CondStore16Inv 0U, // CondStore16Mux @@ -2480,6 +2742,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CondStoreF64 0U, // CondStoreF64Inv 0U, // CondTrap + 0U, // DDB_MemFoldPseudo + 0U, // DEB_MemFoldPseudo + 0U, // EXRL_Pseudo 0U, // GOT 0U, // IIFMux 0U, // IIHF64 @@ -2501,20 +2766,33 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LLHMux 0U, // LLHRMux 0U, // LMux + 0U, // LOCG_MemFoldPseudo 0U, // LOCHIMux 0U, // LOCMux + 0U, // LOCMux_MemFoldPseudo 0U, // LOCRMux - 0U, // LRMux - 0U, // LTDBRCompare_VecPseudo - 0U, // LTEBRCompare_VecPseudo - 0U, // LTXBRCompare_VecPseudo + 0U, // LTDBRCompare_Pseudo + 0U, // LTEBRCompare_Pseudo + 0U, // LTXBRCompare_Pseudo 0U, // LX - 0U, // MVCLoop - 0U, // MVCSequence + 0U, // MADB_MemFoldPseudo + 0U, // MAEB_MemFoldPseudo + 0U, // MDB_MemFoldPseudo + 0U, // MEEB_MemFoldPseudo + 0U, // MSC_MemFoldPseudo + 0U, // MSDB_MemFoldPseudo + 0U, // MSEB_MemFoldPseudo + 0U, // MSGC_MemFoldPseudo + 0U, // MVCImm + 0U, // MVCReg 0U, // MVSTLoop - 0U, // MemBarrier - 0U, // NCLoop - 0U, // NCSequence + 0U, // MemsetImmImm + 0U, // MemsetImmReg + 0U, // MemsetRegImm + 0U, // MemsetRegReg + 0U, // NCImm + 0U, // NCReg + 0U, // NG_MemFoldPseudo 0U, // NIFMux 0U, // NIHF64 0U, // NIHH64 @@ -2524,8 +2802,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // NILH64 0U, // NILL64 0U, // NILMux - 0U, // OCLoop - 0U, // OCSequence + 0U, // N_MemFoldPseudo + 0U, // OCImm + 0U, // OCReg + 0U, // OG_MemFoldPseudo 0U, // OIFMux 0U, // OIHF64 0U, // OIHH64 @@ -2535,13 +2815,24 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // OILH64 0U, // OILL64 0U, // OILMux + 0U, // O_MemFoldPseudo 0U, // PAIR128 + 0U, // PROBED_ALLOCA + 0U, // PROBED_STACKALLOC 0U, // RISBHH 0U, // RISBHL 0U, // RISBLH 0U, // RISBLL 0U, // RISBMux 0U, // Return + 0U, // Return_XPLINK + 0U, // SCmp128Hi + 0U, // SDB_MemFoldPseudo + 0U, // SEB_MemFoldPseudo + 0U, // SELRMux + 0U, // SG_MemFoldPseudo + 0U, // SLG_MemFoldPseudo + 0U, // SL_MemFoldPseudo 0U, // SRSTLoop 0U, // ST128 0U, // STCMux @@ -2549,6 +2840,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // STMux 0U, // STOCMux 0U, // STX + 0U, // S_MemFoldPseudo + 0U, // Select128 0U, // Select32 0U, // Select64 0U, // SelectF128 @@ -2568,6 +2861,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // TMLL64 0U, // TMLMux 0U, // Trap + 0U, // UCmp128Hi 0U, // VL32 0U, // VL64 0U, // VLR32 @@ -2575,2461 +2869,2633 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VLVGP32 0U, // VST32 0U, // VST64 - 0U, // XCLoop - 0U, // XCSequence + 0U, // XCImm + 0U, // XCReg + 0U, // XG_MemFoldPseudo 0U, // XIFMux 0U, // XIHF64 0U, // XILF64 + 0U, // XPLINK_STACKALLOC + 0U, // X_MemFoldPseudo 0U, // ZEXT128 - 16430U, // A - 18800U, // AD - 16883U, // ADB - 16804865U, // ADBR - 16805360U, // ADR - 1107325271U, // ADTR - 1107312942U, // ADTRA - 18918U, // AE - 17340U, // AEB - 16804997U, // AEBR - 16805497U, // AER - 50356445U, // AFI - 21882U, // AG - 21267U, // AGF - 50356455U, // AGFI - 16805668U, // AGFR - 22882U, // AGH - 67133752U, // AGHI - 1107321434U, // AGHIK - 16805750U, // AGR - 1107321492U, // AGRK - 83927453U, // AGSI - 22627U, // AH - 1107324947U, // AHHHR - 1107325082U, // AHHLR - 67133740U, // AHI - 1107321428U, // AHIK - 30871U, // AHY - 50354711U, // AIH - 25333U, // AL - 18663U, // ALC - 22006U, // ALCG - 16805762U, // ALCGR - 16805341U, // ALCR - 100688143U, // ALFI - 22190U, // ALG - 21284U, // ALGF - 100688115U, // ALGFI - 16805681U, // ALGFR - 1107321441U, // ALGHSIK - 16805794U, // ALGR - 1107321498U, // ALGRK - 83927459U, // ALGSI - 1107324954U, // ALHHHR - 1107325089U, // ALHHLR - 1107321450U, // ALHSIK - 16806010U, // ALR - 1107321542U, // ALRK - 83927510U, // ALSI - 50354776U, // ALSIH - 50358418U, // ALSIHN - 30929U, // ALY - 117500432U, // AP - 16804837U, // AR - 1107321487U, // ARK - 83927448U, // ASI - 30614U, // AU - 16806613U, // AUR - 30705U, // AW - 16806629U, // AWR - 16805219U, // AXBR - 16806639U, // AXR - 1107325529U, // AXTR - 1107312994U, // AXTRA - 30800U, // AY - 65971U, // B - 33583219U, // BAKR - 134243065U, // BAL - 33583225U, // BALR - 134247259U, // BAS - 33583387U, // BASR - 33581165U, // BASSM - 68087U, // BAsmE - 71804U, // BAsmH - 68217U, // BAsmHE - 74502U, // BAsmL - 69053U, // BAsmLE - 72358U, // BAsmLH - 75526U, // BAsmM - 69792U, // BAsmNE - 73228U, // BAsmNH - 68461U, // BAsmNHE - 74853U, // BAsmNL - 69300U, // BAsmNLE - 72653U, // BAsmNLH - 75675U, // BAsmNM - 76101U, // BAsmNO - 76473U, // BAsmNP - 80282U, // BAsmNZ - 75984U, // BAsmO - 76318U, // BAsmP - 80167U, // BAsmZ - 621613U, // BC - 1149082U, // BCAsm - 1670189U, // BCR - 153202129U, // BCRAsm - 30326U, // BCT - 22475U, // BCTG - 16805855U, // BCTGR - 16806189U, // BCTR - 73919U, // BI - 68933U, // BIAsmE - 72223U, // BIAsmH - 68360U, // BIAsmHE - 74698U, // BIAsmL - 69193U, // BIAsmLE - 72499U, // BIAsmLH - 75619U, // BIAsmM - 69918U, // BIAsmNE - 73347U, // BIAsmNH - 68595U, // BIAsmNHE - 74972U, // BIAsmNL - 69434U, // BIAsmNLE - 72787U, // BIAsmNLH - 75737U, // BIAsmNM - 76163U, // BIAsmNO - 76535U, // BIAsmNP - 80344U, // BIAsmNZ - 76038U, // BIAsmO - 76422U, // BIAsmP - 80228U, // BIAsmZ - 621737U, // BIC - 1149126U, // BICAsm - 2317986625U, // BPP - 3391728483U, // BPRP - 3173379U, // BR - 184578918U, // BRAS - 184575582U, // BRASL - 3174014U, // BRAsmE - 3174393U, // BRAsmH - 3174062U, // BRAsmHE - 3174527U, // BRAsmL - 3174081U, // BRAsmLE - 3174456U, // BRAsmLH - 3174640U, // BRAsmM - 3174099U, // BRAsmNE - 3174475U, // BRAsmNH - 3174068U, // BRAsmNHE - 3174596U, // BRAsmNL - 3174087U, // BRAsmNLE - 3174468U, // BRAsmNLH - 3174645U, // BRAsmNM - 3174661U, // BRAsmNO - 3174677U, // BRAsmNP - 3175253U, // BRAsmNZ - 3174656U, // BRAsmO - 3174667U, // BRAsmP - 3175248U, // BRAsmZ - 201948354U, // BRC - 153717047U, // BRCAsm - 201948293U, // BRCL - 153723733U, // BRCLAsm - 201356931U, // BRCT - 201349088U, // BRCTG - 201351128U, // BRCTH - 1090543724U, // BRXH - 1090541188U, // BRXHG - 1090539666U, // BRXLE - 1090541341U, // BRXLG - 33571219U, // BSA - 33576858U, // BSG - 33581139U, // BSM - 1090543713U, // BXH - 1090541182U, // BXHG - 1090539660U, // BXLE - 1090541109U, // BXLEG - 134236295U, // C - 134236532U, // CD - 134234659U, // CDB - 33582088U, // CDBR - 33582339U, // CDFBR - 218120388U, // CDFBRA - 33582858U, // CDFR - 218132967U, // CDFTR - 33582384U, // CDGBR - 218120412U, // CDGBRA - 33582992U, // CDGR - 33583621U, // CDGTR - 218120530U, // CDGTRA - 218131729U, // CDLFBR - 218132974U, // CDLFTR - 218131774U, // CDLGBR - 218133004U, // CDLGTR - 234911491U, // CDPT - 33582588U, // CDR - 1090548978U, // CDS - 1090541476U, // CDSG - 33583669U, // CDSTR - 1090550035U, // CDSY - 33583453U, // CDTR - 33583690U, // CDUTR - 234911626U, // CDZT - 134236726U, // CE - 134235081U, // CEB - 33582220U, // CEBR - 33583465U, // CEDTR - 33582346U, // CEFBR - 218120396U, // CEFBRA - 33582878U, // CEFR - 33582391U, // CEGBR - 218120420U, // CEGBRA - 33583004U, // CEGR - 218131737U, // CELFBR - 218131782U, // CELGBR - 33582724U, // CER - 33583724U, // CEXTR - 3180720U, // CFC - 218131483U, // CFDBR - 218120340U, // CFDBRA - 218131987U, // CFDR - 218132869U, // CFDTR - 218131623U, // CFEBR - 218120364U, // CFEBRA - 218132130U, // CFER - 251683042U, // CFI - 218131838U, // CFXBR - 218120452U, // CFXBRA - 218133254U, // CFXR - 218133121U, // CFXTR - 134239717U, // CG - 218131498U, // CGDBR - 218120348U, // CGDBRA - 218131993U, // CGDR - 218132884U, // CGDTR - 218120508U, // CGDTRA - 218131638U, // CGEBR - 218120372U, // CGEBRA - 218132136U, // CGER - 134239000U, // CGF - 251683053U, // CGFI - 33582891U, // CGFR - 268461514U, // CGFRL - 134240617U, // CGH - 285237568U, // CGHI - 268461574U, // CGHRL - 67150264U, // CGHSI - 305789999U, // CGIB - 1392526511U, // CGIBAsm - 2466269691U, // CGIBAsmE - 2466273408U, // CGIBAsmH - 2466269822U, // CGIBAsmHE - 2466276106U, // CGIBAsmL - 2466270658U, // CGIBAsmLE - 2466273963U, // CGIBAsmLH - 2466271397U, // CGIBAsmNE - 2466274833U, // CGIBAsmNH - 2466270067U, // CGIBAsmNHE - 2466276458U, // CGIBAsmNL - 2466270906U, // CGIBAsmNLE - 2466274259U, // CGIBAsmNLH - 339344580U, // CGIJ - 1392534010U, // CGIJAsm - 3540012399U, // CGIJAsmE - 3540015717U, // CGIJAsmH - 3540011826U, // CGIJAsmHE - 3540018159U, // CGIJAsmL - 3540012659U, // CGIJAsmLE - 3540015990U, // CGIJAsmLH - 3540013384U, // CGIJAsmNE - 3540016813U, // CGIJAsmNH - 3540012066U, // CGIJAsmNHE - 3540018438U, // CGIJAsmNL - 3540012905U, // CGIJAsmNLE - 3540016258U, // CGIJAsmNLH - 4324667U, // CGIT - 1358984917U, // CGITAsm - 285233731U, // CGITAsmE - 285237236U, // CGITAsmH - 285232397U, // CGITAsmHE - 285238957U, // CGITAsmL - 285233236U, // CGITAsmLE - 285236625U, // CGITAsmLH - 285233594U, // CGITAsmNE - 285237023U, // CGITAsmNH - 285232283U, // CGITAsmNHE - 285238648U, // CGITAsmNL - 285233122U, // CGITAsmNLE - 285236482U, // CGITAsmNLH - 33582980U, // CGR - 3391224909U, // CGRB - 1107314075U, // CGRBAsm - 1107315223U, // CGRBAsmE - 1107318945U, // CGRBAsmH - 1107315358U, // CGRBAsmHE - 1107321638U, // CGRBAsmL - 1107316194U, // CGRBAsmLE - 1107319499U, // CGRBAsmLH - 1107316933U, // CGRBAsmNE - 1107320369U, // CGRBAsmNH - 1107315607U, // CGRBAsmNHE - 1107321994U, // CGRBAsmNL - 1107316446U, // CGRBAsmNLE - 1107319799U, // CGRBAsmNLH - 169999576U, // CGRJ - 1107321362U, // CGRJAsm - 1107316107U, // CGRJAsmE - 1107319425U, // CGRJAsmH - 1107315538U, // CGRJAsmHE - 1107321867U, // CGRJAsmL - 1107316371U, // CGRJAsmLE - 1107319702U, // CGRJAsmLH - 1107317096U, // CGRJAsmNE - 1107320525U, // CGRJAsmNH - 1107315782U, // CGRJAsmNHE - 1107322150U, // CGRJAsmNL - 1107316621U, // CGRJAsmNLE - 1107319974U, // CGRJAsmNLH - 268461539U, // CGRL - 153222482U, // CGRT - 1107326751U, // CGRTAsm - 33575524U, // CGRTAsmE - 33579023U, // CGRTAsmH - 33574188U, // CGRTAsmHE - 33580744U, // CGRTAsmL - 33575027U, // CGRTAsmLE - 33578416U, // CGRTAsmLH - 33575385U, // CGRTAsmNE - 33578814U, // CGRTAsmNH - 33574078U, // CGRTAsmNHE - 33580439U, // CGRTAsmNL - 33574917U, // CGRTAsmNLE - 33578277U, // CGRTAsmNLH - 218131853U, // CGXBR - 218120460U, // CGXBRA - 218133260U, // CGXR - 218133136U, // CGXTR - 218120560U, // CGXTRA - 134240442U, // CH - 134239092U, // CHF - 33583117U, // CHHR - 67150279U, // CHHSI - 285237555U, // CHI - 33583252U, // CHLR - 268461559U, // CHRL - 67150250U, // CHSI - 134248604U, // CHY - 305789995U, // CIB - 1392526499U, // CIBAsm - 2466269685U, // CIBAsmE - 2466273402U, // CIBAsmH - 2466269815U, // CIBAsmHE - 2466276100U, // CIBAsmL - 2466270651U, // CIBAsmLE - 2466273956U, // CIBAsmLH - 2466271390U, // CIBAsmNE - 2466274826U, // CIBAsmNH - 2466270059U, // CIBAsmNHE - 2466276451U, // CIBAsmNL - 2466270898U, // CIBAsmNLE - 2466274251U, // CIBAsmNLH - 251681316U, // CIH - 339344576U, // CIJ - 1392534005U, // CIJAsm - 3540012393U, // CIJAsmE - 3540015711U, // CIJAsmH - 3540011819U, // CIJAsmHE - 3540018153U, // CIJAsmL - 3540012652U, // CIJAsmLE - 3540015983U, // CIJAsmLH - 3540013377U, // CIJAsmNE - 3540016806U, // CIJAsmNH - 3540012058U, // CIJAsmNHE - 3540018431U, // CIJAsmNL - 3540012897U, // CIJAsmNLE - 3540016250U, // CIJAsmNLH - 4324657U, // CIT - 1358984905U, // CITAsm - 285233717U, // CITAsmE - 285237222U, // CITAsmH - 285232381U, // CITAsmHE - 285238943U, // CITAsmL - 285233220U, // CITAsmLE - 285236609U, // CITAsmLH - 285233578U, // CITAsmNE - 285237007U, // CITAsmNH - 285232265U, // CITAsmNHE - 285238632U, // CITAsmNL - 285233104U, // CITAsmNLE - 285236464U, // CITAsmNLH - 33581145U, // CKSM - 134243134U, // CL - 302041324U, // CLC - 33579842U, // CLCL - 1107316219U, // CLCLE - 1107326888U, // CLCLU - 218131490U, // CLFDBR - 218132876U, // CLFDTR - 218131630U, // CLFEBR - 352362928U, // CLFHSI - 369123605U, // CLFI - 4848949U, // CLFIT - 1459648206U, // CLFITAsm - 385897019U, // CLFITAsmE - 385900524U, // CLFITAsmH - 385895684U, // CLFITAsmHE - 385902245U, // CLFITAsmL - 385896523U, // CLFITAsmLE - 385899912U, // CLFITAsmLH - 385896881U, // CLFITAsmNE - 385900310U, // CLFITAsmNH - 385895569U, // CLFITAsmNHE - 385901935U, // CLFITAsmNL - 385896408U, // CLFITAsmNLE - 385899768U, // CLFITAsmNLH - 218131845U, // CLFXBR - 218133128U, // CLFXTR - 134239933U, // CLG - 218131505U, // CLGDBR - 218132891U, // CLGDTR - 218131645U, // CLGEBR - 134239018U, // CLGF - 369123578U, // CLGFI - 33582904U, // CLGFR - 268461521U, // CLGFRL - 268461581U, // CLGHRL - 352362943U, // CLGHSI - 307362868U, // CLGIB - 1476412597U, // CLGIBAsm - 2550155778U, // CLGIBAsmE - 2550159495U, // CLGIBAsmH - 2550155910U, // CLGIBAsmHE - 2550162193U, // CLGIBAsmL - 2550156746U, // CLGIBAsmLE - 2550160051U, // CLGIBAsmLH - 2550157485U, // CLGIBAsmNE - 2550160921U, // CLGIBAsmNH - 2550156156U, // CLGIBAsmNHE - 2550162546U, // CLGIBAsmNL - 2550156995U, // CLGIBAsmNLE - 2550160348U, // CLGIBAsmNLH - 340917449U, // CLGIJ - 1476420096U, // CLGIJAsm - 3623898486U, // CLGIJAsmE - 3623901804U, // CLGIJAsmH - 3623897914U, // CLGIJAsmHE - 3623904246U, // CLGIJAsmL - 3623898747U, // CLGIJAsmLE - 3623902078U, // CLGIJAsmLH - 3623899472U, // CLGIJAsmNE - 3623902901U, // CLGIJAsmNH - 3623898155U, // CLGIJAsmNHE - 3623904526U, // CLGIJAsmNL - 3623898994U, // CLGIJAsmNLE - 3623902347U, // CLGIJAsmNLH - 4848960U, // CLGIT - 1459648219U, // CLGITAsm - 385897034U, // CLGITAsmE - 385900539U, // CLGITAsmH - 385895701U, // CLGITAsmHE - 385902260U, // CLGITAsmL - 385896540U, // CLGITAsmLE - 385899929U, // CLGITAsmLH - 385896898U, // CLGITAsmNE - 385900327U, // CLGITAsmNH - 385895588U, // CLGITAsmNHE - 385901952U, // CLGITAsmNL - 385896427U, // CLGITAsmNLE - 385899787U, // CLGITAsmNLH - 33583016U, // CLGR - 3391224914U, // CLGRB - 1107314081U, // CLGRBAsm - 1107315230U, // CLGRBAsmE - 1107318952U, // CLGRBAsmH - 1107315366U, // CLGRBAsmHE - 1107321645U, // CLGRBAsmL - 1107316202U, // CLGRBAsmLE - 1107319507U, // CLGRBAsmLH - 1107316941U, // CLGRBAsmNE - 1107320377U, // CLGRBAsmNH - 1107315616U, // CLGRBAsmNHE - 1107322002U, // CLGRBAsmNL - 1107316455U, // CLGRBAsmNLE - 1107319808U, // CLGRBAsmNLH - 169999581U, // CLGRJ - 1107321368U, // CLGRJAsm - 1107316114U, // CLGRJAsmE - 1107319432U, // CLGRJAsmH - 1107315546U, // CLGRJAsmHE - 1107321874U, // CLGRJAsmL - 1107316379U, // CLGRJAsmLE - 1107319710U, // CLGRJAsmLH - 1107317104U, // CLGRJAsmNE - 1107320533U, // CLGRJAsmNH - 1107315791U, // CLGRJAsmNHE - 1107322158U, // CLGRJAsmNL - 1107316630U, // CLGRJAsmNLE - 1107319983U, // CLGRJAsmNLH - 268461545U, // CLGRL - 153222487U, // CLGRT - 1107326757U, // CLGRTAsm - 33575531U, // CLGRTAsmE - 33579030U, // CLGRTAsmH - 33574196U, // CLGRTAsmHE - 33580751U, // CLGRTAsmL - 33575035U, // CLGRTAsmLE - 33578424U, // CLGRTAsmLH - 33575393U, // CLGRTAsmNE - 33578822U, // CLGRTAsmNH - 33574087U, // CLGRTAsmNHE - 33580447U, // CLGRTAsmNL - 33574926U, // CLGRTAsmNLE - 33578286U, // CLGRTAsmNLH - 146732U, // CLGT - 1493202621U, // CLGTAsm - 436228654U, // CLGTAsmE - 436232159U, // CLGTAsmH - 436227317U, // CLGTAsmHE - 436233880U, // CLGTAsmL - 436228156U, // CLGTAsmLE - 436231545U, // CLGTAsmLH - 436228514U, // CLGTAsmNE - 436231943U, // CLGTAsmNH - 436227200U, // CLGTAsmNHE - 436233568U, // CLGTAsmNL - 436228039U, // CLGTAsmNLE - 436231399U, // CLGTAsmNLH - 218131860U, // CLGXBR - 218133143U, // CLGXTR - 134239136U, // CLHF - 33583153U, // CLHHR - 352362958U, // CLHHSI - 33583288U, // CLHLR - 268461597U, // CLHRL - 453026168U, // CLI - 307362874U, // CLIB - 1476412604U, // CLIBAsm - 2550155786U, // CLIBAsmE - 2550159503U, // CLIBAsmH - 2550155919U, // CLIBAsmHE - 2550162201U, // CLIBAsmL - 2550156755U, // CLIBAsmLE - 2550160060U, // CLIBAsmLH - 2550157494U, // CLIBAsmNE - 2550160930U, // CLIBAsmNH - 2550156166U, // CLIBAsmNHE - 2550162555U, // CLIBAsmNL - 2550157005U, // CLIBAsmNLE - 2550160358U, // CLIBAsmNLH - 369121866U, // CLIH - 340917455U, // CLIJ - 1476420103U, // CLIJAsm - 3623898494U, // CLIJAsmE - 3623901812U, // CLIJAsmH - 3623897923U, // CLIJAsmHE - 3623904254U, // CLIJAsmL - 3623898756U, // CLIJAsmLE - 3623902087U, // CLIJAsmLH - 3623899481U, // CLIJAsmNE - 3623902910U, // CLIJAsmNH - 3623898165U, // CLIJAsmNHE - 3623904535U, // CLIJAsmNL - 3623899004U, // CLIJAsmNLE - 3623902357U, // CLIJAsmNLH - 453032118U, // CLIY - 2365613969U, // CLM - 2365611506U, // CLMH - 2365618426U, // CLMY - 33583236U, // CLR - 3391224920U, // CLRB - 1107314088U, // CLRBAsm - 1107315238U, // CLRBAsmE - 1107318960U, // CLRBAsmH - 1107315375U, // CLRBAsmHE - 1107321653U, // CLRBAsmL - 1107316211U, // CLRBAsmLE - 1107319516U, // CLRBAsmLH - 1107316950U, // CLRBAsmNE - 1107320386U, // CLRBAsmNH - 1107315626U, // CLRBAsmNHE - 1107322011U, // CLRBAsmNL - 1107316465U, // CLRBAsmNLE - 1107319818U, // CLRBAsmNLH - 169999587U, // CLRJ - 1107321375U, // CLRJAsm - 1107316122U, // CLRJAsmE - 1107319440U, // CLRJAsmH - 1107315555U, // CLRJAsmHE - 1107321882U, // CLRJAsmL - 1107316388U, // CLRJAsmLE - 1107319719U, // CLRJAsmLH - 1107317113U, // CLRJAsmNE - 1107320542U, // CLRJAsmNH - 1107315801U, // CLRJAsmNHE - 1107322167U, // CLRJAsmNL - 1107316640U, // CLRJAsmNLE - 1107319993U, // CLRJAsmNLH - 268461618U, // CLRL - 153222493U, // CLRT - 1107326764U, // CLRTAsm - 33575539U, // CLRTAsmE - 33579038U, // CLRTAsmH - 33574205U, // CLRTAsmHE - 33580759U, // CLRTAsmL - 33575044U, // CLRTAsmLE - 33578433U, // CLRTAsmLH - 33575402U, // CLRTAsmNE - 33578831U, // CLRTAsmNH - 33574097U, // CLRTAsmNHE - 33580456U, // CLRTAsmNL - 33574936U, // CLRTAsmNLE - 33578296U, // CLRTAsmNLH - 33584959U, // CLST - 146758U, // CLT - 1493202658U, // CLTAsm - 436228690U, // CLTAsmE - 436232195U, // CLTAsmH - 436227358U, // CLTAsmHE - 436233916U, // CLTAsmL - 436228197U, // CLTAsmLE - 436231586U, // CLTAsmLH - 436228555U, // CLTAsmNE - 436231984U, // CLTAsmNH - 436227246U, // CLTAsmNHE - 436233609U, // CLTAsmNL - 436228085U, // CLTAsmNLE - 436231445U, // CLTAsmNLH - 134248662U, // CLY - 33573205U, // CMPSC - 117500452U, // CP - 234911389U, // CPDT - 1090547289U, // CPSDRdd - 1090547289U, // CPSDRds - 1090547289U, // CPSDRsd - 1090547289U, // CPSDRss - 234911608U, // CPXT - 33571240U, // CPYA - 33582546U, // CR - 3391224905U, // CRB - 1107314070U, // CRBAsm - 1107315217U, // CRBAsmE - 1107318939U, // CRBAsmH - 1107315351U, // CRBAsmHE - 1107321632U, // CRBAsmL - 1107316187U, // CRBAsmLE - 1107319492U, // CRBAsmLH - 1107316926U, // CRBAsmNE - 1107320362U, // CRBAsmNH - 1107315599U, // CRBAsmNHE - 1107321987U, // CRBAsmNL - 1107316438U, // CRBAsmNLE - 1107319791U, // CRBAsmNLH - 1090540071U, // CRDTE - 1090540071U, // CRDTEOpt - 169999572U, // CRJ - 1107321357U, // CRJAsm - 1107316101U, // CRJAsmE - 1107319419U, // CRJAsmH - 1107315531U, // CRJAsmHE - 1107321861U, // CRJAsmL - 1107316364U, // CRJAsmLE - 1107319695U, // CRJAsmLH - 1107317089U, // CRJAsmNE - 1107320518U, // CRJAsmNH - 1107315774U, // CRJAsmNHE - 1107322143U, // CRJAsmNL - 1107316613U, // CRJAsmNLE - 1107319966U, // CRJAsmNLH - 268461502U, // CRL - 153222478U, // CRT - 1107326746U, // CRTAsm - 33575518U, // CRTAsmE - 33579017U, // CRTAsmH - 33574181U, // CRTAsmHE - 33580738U, // CRTAsmL - 33575020U, // CRTAsmLE - 33578409U, // CRTAsmLH - 33575378U, // CRTAsmNE - 33578807U, // CRTAsmNH - 33574070U, // CRTAsmNHE - 33580432U, // CRTAsmNL - 33574909U, // CRTAsmNLE - 33578269U, // CRTAsmNLH - 1090548974U, // CS - 15496U, // CSCH - 1107325373U, // CSDTR - 1090541471U, // CSG - 16804730U, // CSP - 16799602U, // CSPG - 1543550795U, // CSST - 1107325625U, // CSXTR - 1090550030U, // CSY - 1107312653U, // CU12 - 33570829U, // CU12Opt - 1107312665U, // CU14 - 33570841U, // CU14Opt - 1107312641U, // CU21 - 33570817U, // CU21Opt - 1107312671U, // CU24 - 33570847U, // CU24Opt - 33570823U, // CU41 - 33570835U, // CU42 - 33583570U, // CUDTR - 33575451U, // CUSE - 1107326874U, // CUTFU - 33585050U, // CUTFUOpt - 1107318025U, // CUUTF - 33576201U, // CUUTFOpt - 33583822U, // CUXTR - 18258U, // CVB - 21980U, // CVBG - 30815U, // CVBY - 134236629U, // CVD - 134239772U, // CVDG - 134248571U, // CVDY - 33582442U, // CXBR - 33582377U, // CXFBR - 218120404U, // CXFBRA - 33582960U, // CXFR - 218132990U, // CXFTR - 33582422U, // CXGBR - 218120428U, // CXGBRA - 33583091U, // CXGR - 33583651U, // CXGTR - 218120538U, // CXGTRA - 218131745U, // CXLFBR - 218132982U, // CXLFTR - 218131790U, // CXLGBR - 218133019U, // CXLGTR - 234911508U, // CXPT - 33583861U, // CXR - 33583683U, // CXSTR - 33583711U, // CXTR - 33583697U, // CXUTR - 234911632U, // CXZT - 134248550U, // CY - 234911401U, // CZDT - 234911620U, // CZXT - 18801U, // D - 18808U, // DD - 16960U, // DDB - 16804878U, // DDBR - 16805377U, // DDR - 1107325283U, // DDTR - 1107312949U, // DDTRA - 19023U, // DE - 17360U, // DEB - 16805011U, // DEBR - 16805515U, // DER - 1107318148U, // DIAG - 1107323961U, // DIDBR - 1107324101U, // DIEBR - 25443U, // DL - 22212U, // DLG - 16805806U, // DLGR - 16806025U, // DLR - 117500472U, // DP - 16805361U, // DR - 22437U, // DSG - 21324U, // DSGF - 16805723U, // DSGFR - 16805843U, // DSGR - 16805233U, // DXBR - 16806651U, // DXR - 1107325542U, // DXTR - 1107313001U, // DXTRA - 33582052U, // EAR - 1107318142U, // ECAG - 33583411U, // ECCTR - 33570901U, // ECPGA - 1543542737U, // ECTG - 302041470U, // ED - 302047870U, // EDMK - 33583472U, // EEDTR - 33583731U, // EEXTR - 3164446U, // EFPC - 3174494U, // EPAIR - 3173353U, // EPAR - 33583432U, // EPCTR - 33585171U, // EPSW - 33576508U, // EREG - 33576527U, // EREGG - 3174501U, // ESAIR - 3173359U, // ESAR - 33583556U, // ESDTR - 3162173U, // ESEA - 33571224U, // ESTA - 33583808U, // ESXTR - 3164588U, // ETND - 134248491U, // EX - 268461656U, // EXRL - 218131520U, // FIDBR - 218120356U, // FIDBRA - 33582635U, // FIDR - 218132899U, // FIDTR - 218131660U, // FIEBR - 218120380U, // FIEBRA - 33582779U, // FIER - 218131868U, // FIXBR - 218120468U, // FIXBRA - 33583890U, // FIXR - 218133151U, // FIXTR - 33583046U, // FLOGR - 33582630U, // HDR - 33582767U, // HER - 15501U, // HSCH - 3164293U, // IAC - 18631U, // IC - 18631U, // IC32 - 30821U, // IC32Y - 486565654U, // ICM - 486563280U, // ICMH - 486570221U, // ICMY - 30821U, // ICY - 1090540065U, // IDTE - 1090540065U, // IDTEOpt - 1090548087U, // IEDTR - 1090548346U, // IEXTR - 369120121U, // IIHF - 352344513U, // IIHH - 352347051U, // IIHL - 369120266U, // IILF - 352344918U, // IILH - 352347175U, // IILL - 15592U, // IPK - 3172386U, // IPM - 1107317336U, // IPTE - 1107317336U, // IPTEOpt - 33575512U, // IPTEOptOpt - 33580810U, // IRBM - 16797096U, // ISKE - 16802541U, // IVSK - 3308094U, // InsnE - 1579334303U, // InsnRI - 505608775U, // InsnRIE - 3726834366U, // InsnRIL - 2653092625U, // InsnRILU - 3726834407U, // InsnRIS - 5929684U, // InsnRR - 505592402U, // InsnRRE - 505592446U, // InsnRRF - 505608956U, // InsnRRS - 505592562U, // InsnRS - 505608797U, // InsnRSE - 505608883U, // InsnRSI - 505609010U, // InsnRSY - 2653076253U, // InsnRX - 2653092467U, // InsnRXE - 505608852U, // InsnRXF - 2653092669U, // InsnRXY - 157465310U, // InsnS - 509786793U, // InsnSI - 1583545033U, // InsnSIL - 2657286951U, // InsnSIY - 7011079U, // InsnSS - 3731028584U, // InsnSSE - 3731028617U, // InsnSSF - 205303U, // J - 200043U, // JAsmE - 203361U, // JAsmH - 199469U, // JAsmHE - 205803U, // JAsmL - 200302U, // JAsmLE - 203633U, // JAsmLH - 206729U, // JAsmM - 201027U, // JAsmNE - 204456U, // JAsmNH - 199708U, // JAsmNHE - 206081U, // JAsmNL - 200547U, // JAsmNLE - 203900U, // JAsmNLH - 206844U, // JAsmNM - 207270U, // JAsmNO - 207642U, // JAsmNP - 211451U, // JAsmNZ - 207141U, // JAsmO - 207531U, // JAsmP - 211331U, // JAsmZ - 202402U, // JG - 199282U, // JGAsmE - 203133U, // JGAsmH - 199407U, // JGAsmHE - 205704U, // JGAsmL - 200240U, // JGAsmLE - 203531U, // JGAsmLH - 206664U, // JGAsmM - 200965U, // JGAsmNE - 204394U, // JGAsmNH - 199639U, // JGAsmNHE - 206019U, // JGAsmNL - 200478U, // JGAsmNLE - 203831U, // JGAsmNLH - 206784U, // JGAsmNM - 207210U, // JGAsmNO - 207582U, // JGAsmNP - 211391U, // JGAsmNZ - 207088U, // JGAsmO - 207465U, // JGAsmP - 211278U, // JGAsmZ - 134234878U, // KDB - 33582151U, // KDBR - 33583530U, // KDTR - 134235119U, // KEB - 33582291U, // KEBR - 3361184U, // KIMD - 3361190U, // KLMD - 33580941U, // KM - 1090535547U, // KMA - 3360906U, // KMAC - 33573115U, // KMC - 1090548033U, // KMCTR - 33576078U, // KMF - 33581371U, // KMO - 33582499U, // KXBR - 33583782U, // KXTR - 134243062U, // L - 134234218U, // LA - 1107312684U, // LAA - 1107318136U, // LAAG - 1107321587U, // LAAL - 1107318444U, // LAALG - 134236650U, // LAE - 134248577U, // LAEY - 1107322617U, // LAM - 1107327200U, // LAMY - 1107323013U, // LAN - 1107318603U, // LANG - 1107323077U, // LAO - 1107318615U, // LAOG - 268461494U, // LARL - 469805940U, // LASP - 134248041U, // LAT - 1107327007U, // LAX - 1107318845U, // LAXG - 134248527U, // LAY - 134235341U, // LB - 134240406U, // LBH - 33582430U, // LBR - 1207976394U, // LCBB - 3188342U, // LCCTL - 33582087U, // LCDBR - 33582857U, // LCDFR - 33582857U, // LCDFR_32 - 33582587U, // LCDR - 33582219U, // LCEBR - 33582723U, // LCER - 33582890U, // LCGFR - 33582979U, // LCGR - 33582558U, // LCR - 1107322493U, // LCTL - 1107318543U, // LCTLG - 33582441U, // LCXBR - 33583860U, // LCXR - 134236572U, // LD - 134236750U, // LDE - 134236750U, // LDE32 - 134235087U, // LDEB - 33582226U, // LDEBR - 33582736U, // LDER - 1107325408U, // LDETR - 33582998U, // LDGR - 33582641U, // LDR - 33582641U, // LDR32 - 33582448U, // LDXBR - 218120436U, // LDXBRA - 33583866U, // LDXR - 218133093U, // LDXTR - 134248560U, // LDY - 134237623U, // LE - 33582100U, // LEDBR - 218120332U, // LEDBRA - 33582605U, // LEDR - 218132862U, // LEDTR - 33582786U, // LER - 33582455U, // LEXBR - 218120444U, // LEXBRA - 33583872U, // LEXR - 134248583U, // LEY - 3191648U, // LFAS - 134240599U, // LFH - 134248034U, // LFHAT - 3180836U, // LFPC - 134239919U, // LG - 134248028U, // LGAT - 134235208U, // LGB - 33582400U, // LGBR - 33582623U, // LGDR - 134239013U, // LGF - 251683060U, // LGFI - 33582898U, // LGFR - 268461522U, // LGFRL - 134239830U, // LGG - 134240643U, // LGH - 285237574U, // LGHI - 33583111U, // LGHR - 268461582U, // LGHRL - 33583011U, // LGR - 268461546U, // LGRL - 134236483U, // LGSC - 134240928U, // LH - 134240733U, // LHH - 285237608U, // LHI - 33583161U, // LHR - 268461598U, // LHRL - 134248609U, // LHY - 134236401U, // LLC - 134240458U, // LLCH - 33582563U, // LLCR - 134236346U, // LLGC - 33582550U, // LLGCR - 134239024U, // LLGF - 134248020U, // LLGFAT - 33582911U, // LLGFR - 268461529U, // LLGFRL - 134240170U, // LLGFSG - 134240642U, // LLGH - 33583110U, // LLGHR - 268461589U, // LLGHRL - 134248131U, // LLGT - 134248046U, // LLGTAT - 33583636U, // LLGTR - 134241202U, // LLH - 134240738U, // LLHH - 33583166U, // LLHR - 268461604U, // LLHRL - 369120127U, // LLIHF - 385898951U, // LLIHH - 385901489U, // LLIHL - 369120272U, // LLILF - 385899356U, // LLILH - 385901613U, // LLILL - 134239044U, // LLZRGF - 1107322770U, // LM - 1107315111U, // LMD - 1107318585U, // LMG - 1107320307U, // LMH - 1107327227U, // LMY - 33582163U, // LNDBR - 33582864U, // LNDFR - 33582864U, // LNDFR_32 - 33582651U, // LNDR - 33582297U, // LNEBR - 33582809U, // LNER - 33582925U, // LNGFR - 33583040U, // LNGR - 33583355U, // LNR - 33582511U, // LNXBR - 33583906U, // LNXR - 244833U, // LOC - 1543522574U, // LOCAsm - 469781056U, // LOCAsmE - 469784790U, // LOCAsmH - 469781182U, // LOCAsmHE - 469787464U, // LOCAsmL - 469782018U, // LOCAsmLE - 469785323U, // LOCAsmLH - 469788443U, // LOCAsmM - 469782750U, // LOCAsmNE - 469786186U, // LOCAsmNH - 469781427U, // LOCAsmNHE - 469787811U, // LOCAsmNL - 469782266U, // LOCAsmNLE - 469785619U, // LOCAsmNLH - 469788576U, // LOCAsmNM - 469789002U, // LOCAsmNO - 469789374U, // LOCAsmNP - 469793183U, // LOCAsmNZ - 469788884U, // LOCAsmO - 469789218U, // LOCAsmP - 469793067U, // LOCAsmZ - 244892U, // LOCFH - 1543526728U, // LOCFHAsm - 469781197U, // LOCFHAsmE - 469785008U, // LOCFHAsmH - 469781237U, // LOCFHAsmHE - 469787546U, // LOCFHAsmL - 469782070U, // LOCFHAsmLE - 469785376U, // LOCFHAsmLH - 469788498U, // LOCFHAsmM - 469782795U, // LOCFHAsmNE - 469786224U, // LOCFHAsmNH - 469781470U, // LOCFHAsmNHE - 469787849U, // LOCFHAsmNL - 469782309U, // LOCFHAsmNLE - 469785662U, // LOCFHAsmNLH - 469788614U, // LOCFHAsmNM - 469789040U, // LOCFHAsmNO - 469789412U, // LOCFHAsmNP - 469793221U, // LOCFHAsmNZ - 469788917U, // LOCFHAsmO - 469789301U, // LOCFHAsmP - 469793107U, // LOCFHAsmZ - 7601442U, // LOCFHR - 1090547710U, // LOCFHRAsm - 16798214U, // LOCFHRAsmE - 16801700U, // LOCFHRAsmH - 16796907U, // LOCFHRAsmHE - 16803325U, // LOCFHRAsmL - 16797746U, // LOCFHRAsmLE - 16801113U, // LOCFHRAsmLH - 16803914U, // LOCFHRAsmM - 16798104U, // LOCFHRAsmNE - 16801533U, // LOCFHRAsmNH - 16796789U, // LOCFHRAsmNHE - 16803158U, // LOCFHRAsmNL - 16797628U, // LOCFHRAsmNLE - 16800988U, // LOCFHRAsmNLH - 16803858U, // LOCFHRAsmNM - 16804290U, // LOCFHRAsmNO - 16804656U, // LOCFHRAsmNP - 16808465U, // LOCFHRAsmNZ - 16804339U, // LOCFHRAsmO - 16804698U, // LOCFHRAsmP - 16808490U, // LOCFHRAsmZ - 244858U, // LOCG - 1543525890U, // LOCGAsm - 469781091U, // LOCGAsmE - 469784935U, // LOCGAsmH - 469781214U, // LOCGAsmHE - 469787513U, // LOCGAsmL - 469782047U, // LOCGAsmLE - 469785338U, // LOCGAsmLH - 469788473U, // LOCGAsmM - 469782772U, // LOCGAsmNE - 469786201U, // LOCGAsmNH - 469781444U, // LOCGAsmNHE - 469787826U, // LOCGAsmNL - 469782283U, // LOCGAsmNLE - 469785636U, // LOCGAsmNLH - 469788591U, // LOCGAsmNM - 469789017U, // LOCGAsmNO - 469789389U, // LOCGAsmNP - 469793198U, // LOCGAsmNZ - 469788897U, // LOCGAsmO - 469789268U, // LOCGAsmP - 469793087U, // LOCGAsmZ - 8125618U, // LOCGHI - 1140875582U, // LOCGHIAsm - 67128658U, // LOCGHIAsmE - 67131960U, // LOCGHIAsmH - 67128087U, // LOCGHIAsmHE - 67134423U, // LOCGHIAsmL - 67128920U, // LOCGHIAsmLE - 67132226U, // LOCGHIAsmLH - 67135344U, // LOCGHIAsmM - 67129645U, // LOCGHIAsmNE - 67133074U, // LOCGHIAsmNH - 67128324U, // LOCGHIAsmNHE - 67134699U, // LOCGHIAsmNL - 67129163U, // LOCGHIAsmNLE - 67132516U, // LOCGHIAsmNLH - 67135464U, // LOCGHIAsmNM - 67135890U, // LOCGHIAsmNO - 67136262U, // LOCGHIAsmNP - 67140071U, // LOCGHIAsmNZ - 67135763U, // LOCGHIAsmO - 67136147U, // LOCGHIAsmP - 67139953U, // LOCGHIAsmZ - 7601436U, // LOCGR - 1090547593U, // LOCGRAsm - 16798206U, // LOCGRAsmE - 16801692U, // LOCGRAsmH - 16796898U, // LOCGRAsmHE - 16803297U, // LOCGRAsmL - 16797737U, // LOCGRAsmLE - 16801104U, // LOCGRAsmLH - 16803906U, // LOCGRAsmM - 16798095U, // LOCGRAsmNE - 16801524U, // LOCGRAsmNH - 16796779U, // LOCGRAsmNHE - 16803149U, // LOCGRAsmNL - 16797618U, // LOCGRAsmNLE - 16800978U, // LOCGRAsmNLH - 16803849U, // LOCGRAsmNM - 16804281U, // LOCGRAsmNO - 16804647U, // LOCGRAsmNP - 16808456U, // LOCGRAsmNZ - 16804331U, // LOCGRAsmO - 16804690U, // LOCGRAsmP - 16808482U, // LOCGRAsmZ - 8125625U, // LOCHHI - 1140875609U, // LOCHHIAsm - 67128667U, // LOCHHIAsmE - 67131969U, // LOCHHIAsmH - 67128097U, // LOCHHIAsmHE - 67134432U, // LOCHHIAsmL - 67128930U, // LOCHHIAsmLE - 67132236U, // LOCHHIAsmLH - 67135353U, // LOCHHIAsmM - 67129655U, // LOCHHIAsmNE - 67133084U, // LOCHHIAsmNH - 67128335U, // LOCHHIAsmNHE - 67134709U, // LOCHHIAsmNL - 67129174U, // LOCHHIAsmNLE - 67132527U, // LOCHHIAsmNLH - 67135474U, // LOCHHIAsmNM - 67135900U, // LOCHHIAsmNO - 67136272U, // LOCHHIAsmNP - 67140081U, // LOCHHIAsmNZ - 67135772U, // LOCHHIAsmO - 67136156U, // LOCHHIAsmP - 67139962U, // LOCHHIAsmZ - 8125612U, // LOCHI - 1140875569U, // LOCHIAsm - 67128650U, // LOCHIAsmE - 67131952U, // LOCHIAsmH - 67128078U, // LOCHIAsmHE - 67134415U, // LOCHIAsmL - 67128911U, // LOCHIAsmLE - 67132217U, // LOCHIAsmLH - 67135336U, // LOCHIAsmM - 67129636U, // LOCHIAsmNE - 67133065U, // LOCHIAsmNH - 67128314U, // LOCHIAsmNHE - 67134690U, // LOCHIAsmNL - 67129153U, // LOCHIAsmNLE - 67132506U, // LOCHIAsmNLH - 67135455U, // LOCHIAsmNM - 67135881U, // LOCHIAsmNO - 67136253U, // LOCHIAsmNP - 67140062U, // LOCHIAsmNZ - 67135755U, // LOCHIAsmO - 67136139U, // LOCHIAsmP - 67139945U, // LOCHIAsmZ - 7601431U, // LOCR - 1090547177U, // LOCRAsm - 16798199U, // LOCRAsmE - 16801685U, // LOCRAsmH - 16796890U, // LOCRAsmHE - 16803260U, // LOCRAsmL - 16797729U, // LOCRAsmLE - 16801096U, // LOCRAsmLH - 16803884U, // LOCRAsmM - 16798087U, // LOCRAsmNE - 16801516U, // LOCRAsmNH - 16796770U, // LOCRAsmNHE - 16803141U, // LOCRAsmNL - 16797609U, // LOCRAsmNLE - 16800969U, // LOCRAsmNLH - 16803841U, // LOCRAsmNM - 16804273U, // LOCRAsmNO - 16804639U, // LOCRAsmNP - 16808448U, // LOCRAsmNZ - 16804317U, // LOCRAsmO - 16804683U, // LOCRAsmP - 16808475U, // LOCRAsmZ - 3188355U, // LPCTL - 1509968306U, // LPD - 33582170U, // LPDBR - 33582871U, // LPDFR - 33582871U, // LPDFR_32 - 1509971477U, // LPDG - 33582657U, // LPDR - 33582304U, // LPEBR - 33582815U, // LPER - 33582932U, // LPGFR - 33583053U, // LPGR - 3189574U, // LPP - 134245326U, // LPQ - 33583376U, // LPR - 3192857U, // LPSW - 3183237U, // LPSWE - 1107312707U, // LPTEA - 33582518U, // LPXBR - 33583912U, // LPXR - 33583227U, // LR - 134234396U, // LRA - 134239640U, // LRAG - 134248537U, // LRAY - 33582669U, // LRDR - 33582827U, // LRER - 268461619U, // LRL - 134248422U, // LRV - 134240304U, // LRVG - 33583084U, // LRVGR - 134242388U, // LRVH - 33583839U, // LRVR - 3188362U, // LSCTL - 134248163U, // LT - 33582191U, // LTDBR - 33582191U, // LTDBRCompare - 33582688U, // LTDR - 33583563U, // LTDTR - 33582325U, // LTEBR - 33582325U, // LTEBRCompare - 33582839U, // LTER - 134240238U, // LTG - 134239064U, // LTGF - 33582953U, // LTGFR - 33583078U, // LTGR - 33583658U, // LTR - 33582538U, // LTXBR - 33582538U, // LTXBRCompare - 33583929U, // LTXR - 33583815U, // LTXTR - 33571206U, // LURA - 33576365U, // LURAG - 134236634U, // LXD - 134235054U, // LXDB - 33582198U, // LXDBR - 33582694U, // LXDR - 1107325401U, // LXDTR - 134238860U, // LXE - 134235178U, // LXEB - 33582332U, // LXEBR - 33582845U, // LXER - 33583896U, // LXR - 134248658U, // LY - 3174002U, // LZDR - 3174147U, // LZER - 134239457U, // LZRF - 134240148U, // LZRG - 3175231U, // LZXR - 26363U, // M - 1090537839U, // MAD - 1090535937U, // MADB - 1090546688U, // MADBR - 1090547183U, // MADR - 1090537968U, // MAE - 1090536386U, // MAEB - 1090546820U, // MAEBR - 1090547320U, // MAER - 1090549844U, // MAY - 1090543730U, // MAYH - 1090547793U, // MAYHR - 1090545390U, // MAYL - 1090547939U, // MAYLR - 1090548549U, // MAYR - 453019900U, // MC - 18850U, // MD - 17164U, // MDB - 16804941U, // MDBR - 19027U, // MDE - 17372U, // MDEB - 16805017U, // MDEBR - 16805526U, // MDER - 16805430U, // MDR - 1107325360U, // MDTR - 1107312964U, // MDTRA - 20634U, // ME - 19038U, // MEE - 17385U, // MEEB - 16805024U, // MEEBR - 16805532U, // MEER - 16805582U, // MER - 30866U, // MFY - 22311U, // MG - 22923U, // MGH - 67133772U, // MGHI - 1107321512U, // MGRK - 24018U, // MH - 67133805U, // MHI - 30886U, // MHY - 25695U, // ML - 22246U, // MLG - 16805812U, // MLGR - 16806079U, // MLR - 117500597U, // MP - 16806129U, // MR - 30259U, // MS - 18768U, // MSC - 3184875U, // MSCH - 1090537930U, // MSD - 1090536316U, // MSDB - 1090546792U, // MSDBR - 1090547283U, // MSDR - 1090540054U, // MSE - 1090536477U, // MSEB - 1090546926U, // MSEBR - 1090547441U, // MSER - 50356513U, // MSFI - 22465U, // MSG - 18624U, // MSGC - 21330U, // MSGF - 50356488U, // MSGFI - 16805730U, // MSGFR - 16805849U, // MSGR - 1107314904U, // MSGRKC - 16806184U, // MSR - 1107314912U, // MSRKC - 3162526U, // MSTA - 31001U, // MSY - 302041441U, // MVC - 469803592U, // MVCDK - 302049434U, // MVCIN - 270914U, // MVCK - 33579867U, // MVCL - 1107316241U, // MVCLE - 1107326895U, // MVCLU - 1543550526U, // MVCOS - 272943U, // MVCP - 275692U, // MVCS - 469803750U, // MVCSK - 67150162U, // MVGHI - 67150177U, // MVHHI - 67150194U, // MVHI - 453026284U, // MVI - 453032134U, // MVIY - 302049472U, // MVN - 117500425U, // MVO - 33576824U, // MVPG - 33584977U, // MVST - 302053945U, // MVZ - 16805289U, // MXBR - 18911U, // MXD - 17332U, // MXDB - 16804989U, // MXDBR - 16805484U, // MXDR - 16806685U, // MXR - 1107325612U, // MXTR - 1107313016U, // MXTRA - 1107327202U, // MY - 1107320952U, // MYH - 1107325016U, // MYHR - 1107322612U, // MYL - 1107325162U, // MYLR - 1107325771U, // MYR - 26759U, // N - 302041349U, // NC - 22349U, // NG - 16805825U, // NGR - 1107321518U, // NGRK - 453026173U, // NI - 8495285U, // NIAI - 100684678U, // NIHF - 352344526U, // NIHH - 352347064U, // NIHL - 100684823U, // NILF - 352344931U, // NILH - 352347188U, // NILL - 453032124U, // NIY - 16806140U, // NR - 1107321554U, // NRK - 134240243U, // NTSTG - 30982U, // NY - 26823U, // O - 302041359U, // OC - 22361U, // OG - 16805832U, // OGR - 1107321524U, // OGRK - 453026177U, // OI - 100684684U, // OIHF - 352344532U, // OIHH - 352347070U, // OIHL - 100684829U, // OILF - 352344937U, // OILH - 352347194U, // OILL - 453032129U, // OIY - 16806145U, // OR - 1107321559U, // ORK - 30986U, // OY - 117498417U, // PACK - 15423U, // PALB - 3180832U, // PC - 15453U, // PCC - 15623U, // PCKMO - 1149314U, // PFD - 153724355U, // PFDRL - 3363962U, // PFMF - 15629U, // PFPO - 33581225U, // PGIN - 33584989U, // PGOUT - 520126558U, // PKA - 520140707U, // PKU - 1509976374U, // PLO - 33584878U, // POPCNT - 1107312775U, // PPA - 33581483U, // PPNO - 15657U, // PR - 33581516U, // PRNO - 33584901U, // PT - 3167492U, // PTF - 15471U, // PTFF - 33579495U, // PTI - 15428U, // PTLB - 1107325270U, // QADTR - 1107325528U, // QAXTR - 3187089U, // QCTRI - 3187164U, // QSI - 15634U, // RCHP - 1090540991U, // RISBG - 1090540991U, // RISBG32 - 1090545802U, // RISBGN - 1090541161U, // RISBHG - 1090541235U, // RISBLG - 1107321935U, // RLL - 1107318490U, // RLLG - 1090540998U, // RNSBG - 1090541005U, // ROSBG - 3189582U, // RP - 33573421U, // RRBE - 33580816U, // RRBM - 1107325366U, // RRDTR - 1107325618U, // RRXTR - 15506U, // RSCH - 1090541012U, // RXSBG - 29533U, // S - 3180688U, // SAC - 3183270U, // SACF - 15596U, // SAL - 15336U, // SAM24 - 15324U, // SAM31 - 15342U, // SAM64 - 33582064U, // SAR - 33583418U, // SCCTR - 15618U, // SCHM - 3187255U, // SCK - 3180747U, // SCKC - 15476U, // SCKPF - 18891U, // SD - 17262U, // SDB - 16804969U, // SDBR - 16805460U, // SDR - 1107325374U, // SDTR - 1107312971U, // SDTRA - 21015U, // SE - 17438U, // SEB - 16805103U, // SEBR - 16805618U, // SER - 3174689U, // SFASR - 3164458U, // SFPC - 22427U, // SG - 21325U, // SGF - 16805724U, // SGFR - 22928U, // SGH - 16805844U, // SGR - 1107321530U, // SGRK - 24510U, // SH - 1107324970U, // SHHHR - 1107325105U, // SHHLR - 30891U, // SHY - 3181924U, // SIE - 3178575U, // SIGA - 1107323491U, // SIGP - 26209U, // SL - 469778537U, // SLA - 1107318154U, // SLAG - 1107321381U, // SLAK - 17699U, // SLB - 21945U, // SLBG - 16805755U, // SLBGR - 16805213U, // SLBR - 469778481U, // SLDA - 469787489U, // SLDL - 1107326615U, // SLDT - 100688155U, // SLFI - 22275U, // SLG - 21302U, // SLGF - 100688129U, // SLGFI - 16805702U, // SLGFR - 16805818U, // SLGR - 1107321505U, // SLGRK - 1107324962U, // SLHHHR - 1107325097U, // SLHHLR - 469787732U, // SLL - 1107318496U, // SLLG - 1107321458U, // SLLK - 16806105U, // SLR - 1107321548U, // SLRK - 1107326834U, // SLXT - 30939U, // SLY - 117500790U, // SP - 33583439U, // SPCTR - 3178595U, // SPKA - 3172391U, // SPM - 3192585U, // SPT - 3192889U, // SPX - 134236599U, // SQD - 134234974U, // SQDB - 33582177U, // SQDBR - 33582663U, // SQDR - 134238706U, // SQE - 134235159U, // SQEB - 33582311U, // SQEBR - 33582821U, // SQER - 33582525U, // SQXBR - 33583918U, // SQXR - 16806173U, // SR - 469778723U, // SRA - 1107318176U, // SRAG - 1107321387U, // SRAK - 469778487U, // SRDA - 469787495U, // SRDL - 1107326627U, // SRDT - 1107321564U, // SRK - 469788230U, // SRL - 1107318523U, // SRLG - 1107321464U, // SRLK - 3188764U, // SRNM - 3179850U, // SRNMB - 3192551U, // SRNMT - 1375791978U, // SRP - 33584965U, // SRST - 33585082U, // SRSTU - 1107326846U, // SRXT - 3174508U, // SSAIR - 3173365U, // SSAR - 3184881U, // SSCH - 1107316142U, // SSKE - 33574318U, // SSKEOpt - 3188847U, // SSM - 134248257U, // ST - 1107322622U, // STAM - 1107327206U, // STAMY - 3189262U, // STAP - 134236508U, // STC - 134240510U, // STCH - 3187260U, // STCK - 3180753U, // STCKC - 3181985U, // STCKE - 3183584U, // STCKF - 2365613864U, // STCM - 2365611478U, // STCMH - 2365618419U, // STCMY - 3192389U, // STCPS - 3192844U, // STCRW - 1107318759U, // STCTG - 1107322513U, // STCTL - 134248554U, // STCY - 134236623U, // STD - 134248565U, // STDY - 134238848U, // STE - 134248588U, // STEY - 134240604U, // STFH - 3187571U, // STFL - 3182104U, // STFLE - 3180848U, // STFPC - 134240245U, // STG - 268461552U, // STGRL - 134236489U, // STGSC - 134242341U, // STH - 134240785U, // STHH - 268461611U, // STHRL - 134248624U, // STHY - 3189301U, // STIDP - 1107322997U, // STM - 1107318590U, // STMG - 1107320312U, // STMH - 1107327232U, // STMY - 453027935U, // STNSM - 157547621U, // STOC - 1509968147U, // STOCAsm - 436226630U, // STOCAsmE - 436230364U, // STOCAsmH - 436226757U, // STOCAsmHE - 436233038U, // STOCAsmL - 436227593U, // STOCAsmLE - 436230898U, // STOCAsmLH - 436234017U, // STOCAsmM - 436228325U, // STOCAsmNE - 436231761U, // STOCAsmNH - 436227003U, // STOCAsmNHE - 436233386U, // STOCAsmNL - 436227842U, // STOCAsmNLE - 436231195U, // STOCAsmNLH - 436234151U, // STOCAsmNM - 436234577U, // STOCAsmNO - 436234949U, // STOCAsmNP - 436238758U, // STOCAsmNZ - 436234458U, // STOCAsmO - 436234792U, // STOCAsmP - 436238641U, // STOCAsmZ - 157547682U, // STOCFH - 1509972303U, // STOCFHAsm - 436226773U, // STOCFHAsmE - 436230584U, // STOCFHAsmH - 436226814U, // STOCFHAsmHE - 436233122U, // STOCFHAsmL - 436227647U, // STOCFHAsmLE - 436230953U, // STOCFHAsmLH - 436234074U, // STOCFHAsmM - 436228372U, // STOCFHAsmNE - 436231801U, // STOCFHAsmNH - 436227048U, // STOCFHAsmNHE - 436233426U, // STOCFHAsmNL - 436227887U, // STOCFHAsmNLE - 436231240U, // STOCFHAsmNLH - 436234191U, // STOCFHAsmNM - 436234617U, // STOCFHAsmNO - 436234989U, // STOCFHAsmNP - 436238798U, // STOCFHAsmNZ - 436234493U, // STOCFHAsmO - 436234877U, // STOCFHAsmP - 436238683U, // STOCFHAsmZ - 157547647U, // STOCG - 1509971464U, // STOCGAsm - 436226666U, // STOCGAsmE - 436230510U, // STOCGAsmH - 436226790U, // STOCGAsmHE - 436233088U, // STOCGAsmL - 436227623U, // STOCGAsmLE - 436230914U, // STOCGAsmLH - 436234048U, // STOCGAsmM - 436228348U, // STOCGAsmNE - 436231777U, // STOCGAsmNH - 436227021U, // STOCGAsmNHE - 436233402U, // STOCGAsmNL - 436227860U, // STOCGAsmNLE - 436231213U, // STOCGAsmNLH - 436234167U, // STOCGAsmNM - 436234593U, // STOCGAsmNO - 436234965U, // STOCGAsmNP - 436238774U, // STOCGAsmNZ - 436234472U, // STOCGAsmO - 436234843U, // STOCGAsmP - 436238662U, // STOCGAsmZ - 453027942U, // STOSM - 134245331U, // STPQ - 3192590U, // STPT - 3192894U, // STPX - 469800358U, // STRAG - 268461650U, // STRL - 134248427U, // STRV - 134240310U, // STRVG - 134242394U, // STRVH - 3184887U, // STSCH - 3187169U, // STSI - 33571212U, // STURA - 33576845U, // STURG - 134248734U, // STY - 30646U, // SU - 16806618U, // SUR - 280934U, // SVC - 30741U, // SW - 16806634U, // SWR - 16805316U, // SXBR - 16806708U, // SXR - 1107325626U, // SXTR - 1107313023U, // SXTRA - 30991U, // SY - 3192626U, // TABORT - 15614U, // TAM - 33582075U, // TAR - 33572676U, // TB - 218131957U, // TBDR - 218131974U, // TBEDR - 352364705U, // TBEGIN - 352356608U, // TBEGINC - 134234680U, // TCDB - 134235080U, // TCEB - 134236063U, // TCXB - 134248073U, // TDCDT - 134248111U, // TDCET - 134248292U, // TDCXT - 134248080U, // TDGDT - 134248118U, // TDGET - 134248299U, // TDGXT - 15466U, // TEND - 33582729U, // THDER - 33582629U, // THDR - 453027958U, // TM - 385898999U, // TMHH - 385901508U, // TMHL - 385899455U, // TMLH - 385901632U, // TMLL - 453032193U, // TMY - 3206027U, // TP - 3187084U, // TPI - 469808886U, // TPROT - 302051631U, // TR - 1107315251U, // TRACE - 1107318242U, // TRACG - 15330U, // TRAP2 - 3178533U, // TRAP4 - 33575441U, // TRE - 1107323351U, // TROO - 33581527U, // TROOOpt - 1107326717U, // TROT - 33584893U, // TROTOpt - 302053178U, // TRT - 419648122U, // TRTE - 3363450U, // TRTEOpt - 1107323395U, // TRTO - 33581571U, // TRTOOpt - 302051887U, // TRTR - 419648015U, // TRTRE - 3363343U, // TRTREOpt - 1107326807U, // TRTT - 33584983U, // TRTTOpt - 3192396U, // TS - 3184888U, // TSCH - 117498500U, // UNPK - 302039132U, // UNPKA - 302053281U, // UNPKU - 15690U, // UPT - 1107313060U, // VA - 1107313093U, // VAB - 1107314837U, // VAC - 1107314846U, // VACC - 1107313110U, // VACCB - 1107314852U, // VACCC - 1107323809U, // VACCCQ - 1107317420U, // VACCF - 1107318249U, // VACCG - 1107318967U, // VACCH - 1107323802U, // VACCQ - 1107323796U, // VACQ - 1107317409U, // VAF - 1107318196U, // VAG - 1107318901U, // VAH - 1107323412U, // VAP - 1107323791U, // VAQ - 1107318787U, // VAVG - 1107313749U, // VAVGB - 1107317598U, // VAVGF - 1107318363U, // VAVGG - 1107319189U, // VAVGH - 1107321741U, // VAVGL - 1107313880U, // VAVGLB - 1107317755U, // VAVGLF - 1107318473U, // VAVGLG - 1107319569U, // VAVGLH - 1107322931U, // VBPERM - 1107318287U, // VCDG - 1107313712U, // VCDGB - 1107318466U, // VCDLG - 1107313733U, // VCDLGB - 1107323817U, // VCEQ - 1107314063U, // VCEQB - 1107325965U, // VCEQBS - 1107317962U, // VCEQF - 1107326248U, // VCEQFS - 1107318654U, // VCEQG - 1107326340U, // VCEQGS - 1107320718U, // VCEQH - 1107326414U, // VCEQHS - 1107315084U, // VCGD - 1107313310U, // VCGDB - 1107319044U, // VCH - 1107313770U, // VCHB - 1107325950U, // VCHBS - 1107317619U, // VCHF - 1107326233U, // VCHFS - 1107318385U, // VCHG - 1107326325U, // VCHGS - 1107319210U, // VCHH - 1107326399U, // VCHHS - 1107321748U, // VCHL - 1107313888U, // VCHLB - 1107325957U, // VCHLBS - 1107317763U, // VCHLF - 1107326240U, // VCHLFS - 1107318481U, // VCHLG - 1107326332U, // VCHLGS - 1107319577U, // VCHLH - 1107326406U, // VCHLHS - 1107322968U, // VCKSM - 1107315090U, // VCLGD - 1107313324U, // VCLGDB - 1107327380U, // VCLZ - 33572983U, // VCLZB - 33576298U, // VCLZF - 33577041U, // VCLZG - 33579175U, // VCLZH - 1107323440U, // VCP - 1107327539U, // VCTZ - 33572990U, // VCTZB - 33576305U, // VCTZF - 33577048U, // VCTZG - 33579182U, // VCTZH - 1107314513U, // VCVB - 1107318235U, // VCVBG - 1107315156U, // VCVD - 1107318299U, // VCVDG - 1107323458U, // VDP - 1107314859U, // VEC - 33571293U, // VECB - 33575603U, // VECF - 33576432U, // VECG - 33577150U, // VECH - 1107321660U, // VECL - 33572049U, // VECLB - 33575924U, // VECLF - 33576635U, // VECLG - 33577700U, // VECLH - 1090545538U, // VERIM - 1090536770U, // VERIMB - 1090540678U, // VERIMF - 1090541361U, // VERIMG - 1090543082U, // VERIMH - 1107321933U, // VERLL - 1107313903U, // VERLLB - 1107317809U, // VERLLF - 1107318488U, // VERLLG - 1107319735U, // VERLLH - 1107326927U, // VERLLV - 1107314526U, // VERLLVB - 1107318048U, // VERLLVF - 1107318800U, // VERLLVG - 1107320890U, // VERLLVH - 1107322469U, // VESL - 1107313953U, // VESLB - 1107317852U, // VESLF - 1107318529U, // VESLG - 1107320178U, // VESLH - 1107326943U, // VESLV - 1107314544U, // VESLVB - 1107318066U, // VESLVF - 1107318818U, // VESLVG - 1107320908U, // VESLVH - 1107312929U, // VESRA - 1107313078U, // VESRAB - 1107317401U, // VESRAF - 1107318174U, // VESRAG - 1107318893U, // VESRAH - 1107326913U, // VESRAV - 1107314504U, // VESRAVB - 1107318032U, // VESRAVF - 1107318778U, // VESRAVG - 1107320874U, // VESRAVH - 1107322436U, // VESRL - 1107313938U, // VESRLB - 1107317844U, // VESRLF - 1107318521U, // VESRLG - 1107320170U, // VESRLH - 1107326935U, // VESRLV - 1107314535U, // VESRLVB - 1107318057U, // VESRLVF - 1107318809U, // VESRLVG - 1107320899U, // VESRLVH - 1107312714U, // VFA - 1107313137U, // VFADB - 1107315172U, // VFAE - 1107313594U, // VFAEB - 1107325925U, // VFAEBS - 1107317447U, // VFAEF - 1107326208U, // VFAEFS - 1107319049U, // VFAEH - 1107326374U, // VFAEHS - 1107314774U, // VFAEZB - 1107326160U, // VFAEZBS - 1107318089U, // VFAEZF - 1107326297U, // VFAEZFS - 1107320966U, // VFAEZH - 1107326458U, // VFAEZHS - 1107314102U, // VFASB - 1107315258U, // VFCE - 1107313228U, // VFCEDB - 1107325813U, // VFCEDBS - 1107314187U, // VFCESB - 1107325982U, // VFCESBS - 1107318980U, // VFCH - 1107313340U, // VFCHDB - 1107325889U, // VFCHDBS - 1107315383U, // VFCHE - 1107313244U, // VFCHEDB - 1107325831U, // VFCHEDBS - 1107314203U, // VFCHESB - 1107326000U, // VFCHESBS - 1107314255U, // VFCHSB - 1107326058U, // VFCHSBS - 1107315079U, // VFD - 1107313214U, // VFDDB - 1107314173U, // VFDSB - 1107315288U, // VFEE - 1107313634U, // VFEEB - 1107325933U, // VFEEBS - 1107317468U, // VFEEF - 1107326216U, // VFEEFS - 1107319063U, // VFEEH - 1107326382U, // VFEEHS - 1107314782U, // VFEEZB - 1107326169U, // VFEEZBS - 1107318097U, // VFEEZF - 1107326306U, // VFEEZFS - 1107320974U, // VFEEZH - 1107326467U, // VFEEZHS - 1107316973U, // VFENE - 1107313679U, // VFENEB - 1107325941U, // VFENEBS - 1107317508U, // VFENEF - 1107326224U, // VFENEFS - 1107319097U, // VFENEH - 1107326390U, // VFENEHS - 1107314798U, // VFENEZB - 1107326178U, // VFENEZBS - 1107318113U, // VFENEZF - 1107326315U, // VFENEZFS - 1107320990U, // VFENEZH - 1107326476U, // VFENEZHS - 1107321127U, // VFI - 1107313390U, // VFIDB - 1107314305U, // VFISB - 1107313280U, // VFKEDB - 1107325871U, // VFKEDBS - 1107314239U, // VFKESB - 1107326040U, // VFKESBS - 1107313356U, // VFKHDB - 1107325907U, // VFKHDBS - 1107313262U, // VFKHEDB - 1107325851U, // VFKHEDBS - 1107314221U, // VFKHESB - 1107326020U, // VFKHESBS - 1107314271U, // VFKHSB - 1107326076U, // VFKHSBS - 33571368U, // VFLCDB - 33572333U, // VFLCSB - 1107321889U, // VFLL - 33584675U, // VFLLS - 33571626U, // VFLNDB - 33572534U, // VFLNSB - 33571660U, // VFLPDB - 33572568U, // VFLPSB - 1107325070U, // VFLR - 1107315132U, // VFLRD - 1107322676U, // VFM - 1107312757U, // VFMA - 1107313151U, // VFMADB - 1107314116U, // VFMASB - 1107327012U, // VFMAX - 1107313564U, // VFMAXDB - 1107314477U, // VFMAXSB - 1107313418U, // VFMDB - 1107323055U, // VFMIN - 1107313432U, // VFMINDB - 1107314340U, // VFMINSB - 1107326513U, // VFMS - 1107314326U, // VFMSB - 1107313530U, // VFMSDB - 1107314438U, // VFMSSB - 1107312768U, // VFNMA - 1107313167U, // VFNMADB - 1107314132U, // VFNMASB - 1107326519U, // VFNMS - 1107313546U, // VFNMSDB - 1107314454U, // VFNMSSB - 1107323388U, // VFPSO - 1107313466U, // VFPSODB - 1107314374U, // VFPSOSB - 1107326282U, // VFS - 1107313516U, // VFSDB - 1107323865U, // VFSQ - 33571676U, // VFSQDB - 33572584U, // VFSQSB - 1107314424U, // VFSSB - 1107321040U, // VFTCI - 1107313372U, // VFTCIDB - 1107314287U, // VFTCISB - 385902340U, // VGBM - 3758117603U, // VGEF - 536892969U, // VGEG - 1107322670U, // VGFM - 1107312750U, // VGFMA - 1107313070U, // VGFMAB - 1107317393U, // VGFMAF - 1107318160U, // VGFMAG - 1107318879U, // VGFMAH - 1107313973U, // VGFMB - 1107317875U, // VGFMF - 1107318564U, // VGFMG - 1107320285U, // VGFMH - 1476421453U, // VGM - 1476412732U, // VGMB - 1476416640U, // VGMF - 1476417323U, // VGMG - 1476419044U, // VGMH - 1107325500U, // VISTR - 1107314094U, // VISTRB - 33584149U, // VISTRBS - 1107317977U, // VISTRF - 33584432U, // VISTRFS - 1107320755U, // VISTRH - 33584598U, // VISTRHS - 134244068U, // VL - 1207976400U, // VLBB - 1107314934U, // VLC - 33571299U, // VLCB - 33575609U, // VLCF - 33576444U, // VLCG - 33577168U, // VLCH - 1107315277U, // VLDE - 33571790U, // VLDEB - 1073759235U, // VLEB - 1107315068U, // VLED - 1107313296U, // VLEDB - 1073763064U, // VLEF - 1073763887U, // VLEG - 1073764653U, // VLEH - 1140868264U, // VLEIB - 1140872145U, // VLEIF - 1140872851U, // VLEIG - 1140873769U, // VLEIH - 1107326921U, // VLGV - 1107314519U, // VLGVB - 1107318041U, // VLGVF - 1107318793U, // VLGVG - 1107320883U, // VLGVH - 1459645093U, // VLIP - 1107321945U, // VLL - 1207990584U, // VLLEZ - 134236262U, // VLLEZB - 134239577U, // VLLEZF - 134240329U, // VLLEZG - 134242454U, // VLLEZH - 134239338U, // VLLEZLF - 1107322774U, // VLM - 1107323567U, // VLP - 33572233U, // VLPB - 33576132U, // VLPF - 33576812U, // VLPG - 33578882U, // VLPH - 33583326U, // VLR - 1207986759U, // VLREP - 134235514U, // VLREPB - 134239413U, // VLREPF - 134240093U, // VLREPG - 134242163U, // VLREPH - 1509975608U, // VLRL - 1107325130U, // VLRLR - 1090541610U, // VLVG - 1090536540U, // VLVGB - 1090540389U, // VLVGF - 1090541154U, // VLVGG - 1090541980U, // VLVGH - 1107323502U, // VLVGP - 1107315183U, // VMAE - 1107313601U, // VMAEB - 1107317454U, // VMAEF - 1107319056U, // VMAEH - 1107318887U, // VMAH - 1107313763U, // VMAHB - 1107317612U, // VMAHF - 1107319203U, // VMAHH - 1107321598U, // VMAL - 1107313866U, // VMALB - 1107316148U, // VMALE - 1107313652U, // VMALEB - 1107317481U, // VMALEF - 1107319070U, // VMALEH - 1107317741U, // VMALF - 1107319453U, // VMALH - 1107313776U, // VMALHB - 1107317656U, // VMALHF - 1107319258U, // VMALHH - 1107326965U, // VMALHW - 1107323177U, // VMALO - 1107314021U, // VMALOB - 1107317920U, // VMALOF - 1107320670U, // VMALOH - 1107323082U, // VMAO - 1107314014U, // VMAOB - 1107317913U, // VMAOF - 1107320663U, // VMAOH - 1107316889U, // VME - 1107313673U, // VMEB - 1107317502U, // VMEF - 1107319091U, // VMEH - 1107320325U, // VMH - 1107313799U, // VMHB - 1107317685U, // VMHF - 1107319293U, // VMHH - 1107321950U, // VML - 1107313911U, // VMLB - 1107316396U, // VMLE - 1107313660U, // VMLEB - 1107317489U, // VMLEF - 1107319078U, // VMLEH - 1107317817U, // VMLF - 1107319749U, // VMLH - 1107313784U, // VMLHB - 1107317670U, // VMLHF - 1107319272U, // VMLHH - 1107326973U, // VMLHW - 1107323184U, // VMLO - 1107314029U, // VMLOB - 1107317928U, // VMLOF - 1107320678U, // VMLOH - 1107323062U, // VMN - 1107314008U, // VMNB - 1107317907U, // VMNF - 1107318609U, // VMNG - 1107320550U, // VMNH - 1107322175U, // VMNL - 1107313917U, // VMNLB - 1107317823U, // VMNLF - 1107318507U, // VMNLG - 1107320002U, // VMNLH - 1107323200U, // VMO - 1107314036U, // VMOB - 1107317935U, // VMOF - 1107320685U, // VMOH - 1107323572U, // VMP - 1107320749U, // VMRH - 1107313812U, // VMRHB - 1107317698U, // VMRHF - 1107318391U, // VMRHG - 1107319306U, // VMRHH - 1107322430U, // VMRL - 1107313931U, // VMRLB - 1107317837U, // VMRLF - 1107318514U, // VMRLG - 1107320163U, // VMRLH - 1107322475U, // VMSL - 1107318536U, // VMSLG - 1107323775U, // VMSP - 1107327023U, // VMX - 1107314684U, // VMXB - 1107318074U, // VMXF - 1107318851U, // VMXG - 1107320934U, // VMXH - 1107322600U, // VMXL - 1107313966U, // VMXLB - 1107317859U, // VMXLF - 1107318550U, // VMXLG - 1107320265U, // VMXLH - 1107323073U, // VN - 1107314953U, // VNC - 1107323067U, // VNN - 1107323346U, // VNO - 1107327028U, // VNX - 1107323402U, // VO - 1107314969U, // VOC - 3166593U, // VONE - 1107321047U, // VPDI - 1107322939U, // VPERM - 1107321482U, // VPK - 1107317735U, // VPKF - 1107318438U, // VPKG - 1107319447U, // VPKH - 1107326492U, // VPKLS - 1107317998U, // VPKLSF - 1107326273U, // VPKLSFS - 1107318713U, // VPKLSG - 1107326356U, // VPKLSGS - 1107320770U, // VPKLSH - 1107326439U, // VPKLSHS - 1107326486U, // VPKS - 1107317991U, // VPKSF - 1107326265U, // VPKSFS - 1107318706U, // VPKSG - 1107326348U, // VPKSGS - 1107320763U, // VPKSH - 1107326431U, // VPKSHS - 1509980558U, // VPKZ - 1107326587U, // VPOPCT - 33572671U, // VPOPCTB - 33576187U, // VPOPCTF - 33576919U, // VPOPCTG - 33578959U, // VPOPCTH - 1107323706U, // VPSOP - 1107323470U, // VREP - 1107314050U, // VREPB - 1107317949U, // VREPF - 1107318629U, // VREPG - 1107320699U, // VREPH - 1358979461U, // VREPI - 285230274U, // VREPIB - 285234136U, // VREPIF - 285234842U, // VREPIG - 285235792U, // VREPIH - 1107323759U, // VRP - 1107326544U, // VS - 1107314472U, // VSB - 1107321019U, // VSBCBI - 1107323823U, // VSBCBIQ - 1107321034U, // VSBI - 1107323840U, // VSBIQ - 1107321027U, // VSCBI - 1107313819U, // VSCBIB - 1107317705U, // VSCBIF - 1107318411U, // VSCBIG - 1107319324U, // VSCBIH - 1107323832U, // VSCBIQ - 2701152981U, // VSCEF - 3774895650U, // VSCEG - 1107323452U, // VSDP - 1107318338U, // VSEG - 33571902U, // VSEGB - 33575709U, // VSEGF - 33577334U, // VSEGH - 1107321709U, // VSEL - 1107318006U, // VSF - 1107318726U, // VSG - 1107320778U, // VSH - 1107322481U, // VSL - 1107313960U, // VSLB - 1107313411U, // VSLDB - 1107323781U, // VSP - 1107323871U, // VSQ - 1107312936U, // VSRA - 1107313086U, // VSRAB - 1107322443U, // VSRL - 1107313946U, // VSRLB - 1107323753U, // VSRP - 134248274U, // VST - 1207976995U, // VSTEB - 1207980812U, // VSTEF - 1207981640U, // VSTEG - 1207982401U, // VSTEH - 1107322590U, // VSTL - 1107322996U, // VSTM - 1107315004U, // VSTRC - 1107313129U, // VSTRCB - 1107325804U, // VSTRCBS - 1107317439U, // VSTRCF - 1107326199U, // VSTRCFS - 1107319011U, // VSTRCH - 1107326365U, // VSTRCHS - 1107314765U, // VSTRCZB - 1107326150U, // VSTRCZBS - 1107318080U, // VSTRCZF - 1107326287U, // VSTRCZFS - 1107320957U, // VSTRCZH - 1107326448U, // VSTRCZHS - 1509975633U, // VSTRL - 1107325137U, // VSTRLR - 1107323007U, // VSUM - 1107314001U, // VSUMB - 1107318596U, // VSUMG - 1107317564U, // VSUMGF - 1107319176U, // VSUMGH - 1107320318U, // VSUMH - 1107323847U, // VSUMQ - 1107317969U, // VSUMQF - 1107318661U, // VSUMQG - 33581178U, // VTM - 3173258U, // VTP - 1107320712U, // VUPH - 33571981U, // VUPHB - 33575867U, // VUPHF - 33577475U, // VUPHH - 1509980551U, // VUPKZ - 1107322288U, // VUPL - 33572100U, // VUPLB - 33576006U, // VUPLF - 1107320129U, // VUPLH - 33571967U, // VUPLHB - 33575853U, // VUPLHF - 33577455U, // VUPLHH - 33585156U, // VUPLHW - 1107321926U, // VUPLL - 33572071U, // VUPLLB - 33575977U, // VUPLLF - 33577903U, // VUPLLH - 1107327051U, // VX - 3172836U, // VZERO - 1107313719U, // WCDGB - 1107313741U, // WCDLGB - 1107313317U, // WCGDB - 1107313332U, // WCLGDB - 1107313144U, // WFADB - 1107314109U, // WFASB - 1107314552U, // WFAXB - 1107314869U, // WFC - 33571361U, // WFCDB - 1107313236U, // WFCEDB - 1107325822U, // WFCEDBS - 1107314195U, // WFCESB - 1107325991U, // WFCESBS - 1107314604U, // WFCEXB - 1107326094U, // WFCEXBS - 1107313348U, // WFCHDB - 1107325898U, // WFCHDBS - 1107313253U, // WFCHEDB - 1107325841U, // WFCHEDBS - 1107314212U, // WFCHESB - 1107326010U, // WFCHESBS - 1107314612U, // WFCHEXB - 1107326103U, // WFCHEXBS - 1107314263U, // WFCHSB - 1107326067U, // WFCHSBS - 1107314638U, // WFCHXB - 1107326132U, // WFCHXBS - 33572326U, // WFCSB - 33572752U, // WFCXB - 1107313221U, // WFDDB - 1107314180U, // WFDSB - 1107314597U, // WFDXB - 1107313397U, // WFIDB - 1107314312U, // WFISB - 1107314663U, // WFIXB - 1107321423U, // WFK - 33571580U, // WFKDB - 1107313288U, // WFKEDB - 1107325880U, // WFKEDBS - 1107314247U, // WFKESB - 1107326049U, // WFKESBS - 1107314630U, // WFKEXB - 1107326123U, // WFKEXBS - 1107313364U, // WFKHDB - 1107325916U, // WFKHDBS - 1107313271U, // WFKHEDB - 1107325861U, // WFKHEDBS - 1107314230U, // WFKHESB - 1107326030U, // WFKHESBS - 1107314621U, // WFKHEXB - 1107326113U, // WFKHEXBS - 1107314279U, // WFKHSB - 1107326085U, // WFKHSBS - 1107314646U, // WFKHXB - 1107326141U, // WFKHXBS - 33572495U, // WFKSB - 33572846U, // WFKXB - 33571376U, // WFLCDB - 33572341U, // WFLCSB - 33572759U, // WFLCXB - 33573273U, // WFLLD - 33584682U, // WFLLS - 33571634U, // WFLNDB - 33572542U, // WFLNSB - 33572875U, // WFLNXB - 33571668U, // WFLPDB - 33572576U, // WFLPSB - 33572892U, // WFLPXB - 1107315139U, // WFLRD - 1107327044U, // WFLRX - 1107313159U, // WFMADB - 1107314124U, // WFMASB - 1107314559U, // WFMAXB - 1107313573U, // WFMAXDB - 1107314486U, // WFMAXSB - 1107314756U, // WFMAXXB - 1107313425U, // WFMDB - 1107313441U, // WFMINDB - 1107314349U, // WFMINSB - 1107314690U, // WFMINXB - 1107314333U, // WFMSB - 1107313538U, // WFMSDB - 1107314446U, // WFMSSB - 1107314739U, // WFMSXB - 1107314677U, // WFMXB - 1107313176U, // WFNMADB - 1107314141U, // WFNMASB - 1107314567U, // WFNMAXB - 1107313555U, // WFNMSDB - 1107314463U, // WFNMSSB - 1107314747U, // WFNMSXB - 1107313475U, // WFPSODB - 1107314383U, // WFPSOSB - 1107314707U, // WFPSOXB - 1107313523U, // WFSDB - 33571684U, // WFSQDB - 33572592U, // WFSQSB - 33572900U, // WFSQXB - 1107314431U, // WFSSB - 1107314732U, // WFSXB - 1107313381U, // WFTCIDB - 1107314296U, // WFTCISB - 1107314654U, // WFTCIXB - 33571797U, // WLDEB - 1107313303U, // WLEDB - 30753U, // X - 302041451U, // XC - 22591U, // XG - 16805876U, // XGR - 1107321536U, // XGRK - 453026289U, // XI - 100684690U, // XIHF - 100684835U, // XILF - 453032140U, // XIY - 16806640U, // XR - 1107321569U, // XRK - 15511U, // XSCH - 31011U, // XY - 117500441U, // ZAP + 32814U, // A + 35275U, // AD + 33273U, // ADB + 33599508U, // ADBR + 33600016U, // ADR + 2214639008U, // ADTR + 2214625582U, // ADTRA + 35405U, // AE + 33730U, // AEB + 33599640U, // AEBR + 33600153U, // AER + 100705141U, // AFI + 38641U, // AG + 37929U, // AGF + 100705151U, // AGFI + 33600337U, // AGFR + 39708U, // AGH + 134259664U, // AGHI + 2214634738U, // AGHIK + 33600419U, // AGR + 2214634808U, // AGRK + 167846965U, // AGSI + 39453U, // AH + 2214638671U, // AHHHR + 2214638812U, // AHHLR + 134259652U, // AHI + 2214634732U, // AHIK + 48381U, // AHY + 100703185U, // AIH + 42413U, // AL + 35138U, // ALC + 38765U, // ALCG + 33600431U, // ALCGR + 33599997U, // ALCR + 201368487U, // ALFI + 38949U, // ALG + 37946U, // ALGF + 201368459U, // ALGFI + 33600350U, // ALGFR + 2214634745U, // ALGHSIK + 33600463U, // ALGR + 2214634828U, // ALGRK + 167846971U, // ALGSI + 2214638678U, // ALHHHR + 2214638819U, // ALHHLR + 2214634754U, // ALHSIK + 33600694U, // ALR + 2214634875U, // ALRK + 167847022U, // ALSI + 100703250U, // ALSIH + 100707291U, // ALSIHN + 48439U, // ALY + 234990988U, // AP + 33599472U, // AR + 2214634791U, // ARK + 167846960U, // ASI + 48116U, // AU + 33601310U, // AUR + 48207U, // AW + 33601326U, // AWR + 33599875U, // AXBR + 33601336U, // AXR + 2214639266U, // AXTR + 2214625634U, // AXTRA + 48302U, // AY + 131513U, // B + 67155119U, // BAKR + 268477873U, // BAL + 67155125U, // BALR + 268482475U, // BAS + 67155300U, // BASR + 67152816U, // BASSM + 133726U, // BAsmE + 137782U, // BAsmH + 133856U, // BAsmHE + 140734U, // BAsmL + 134749U, // BAsmLE + 138336U, // BAsmLH + 141846U, // BAsmM + 135545U, // BAsmNE + 139263U, // BAsmNH + 134100U, // BAsmNHE + 141085U, // BAsmNL + 134996U, // BAsmNLE + 138631U, // BAsmNLH + 141995U, // BAsmNM + 142478U, // BAsmNO + 142960U, // BAsmNP + 146944U, // BAsmNZ + 142361U, // BAsmO + 142746U, // BAsmP + 146829U, // BAsmZ + 1229128U, // BC + 2296045U, // BCAsm + 3326280U, // BCR + 306393585U, // BCRAsm + 47828U, // BCT + 39291U, // BCTG + 33600531U, // BCTGR + 33600886U, // BCTR + 140112U, // BI + 134629U, // BIAsmE + 138201U, // BIAsmH + 133999U, // BIAsmHE + 140930U, // BIAsmL + 134889U, // BIAsmLE + 138477U, // BIAsmLH + 141939U, // BIAsmM + 135671U, // BIAsmNE + 139390U, // BIAsmNH + 134234U, // BIAsmNHE + 141212U, // BIAsmNL + 135130U, // BIAsmNLE + 138765U, // BIAsmNLH + 142057U, // BIAsmNM + 142540U, // BIAsmNO + 143022U, // BIAsmNP + 147006U, // BIAsmNZ + 142415U, // BIAsmO + 142909U, // BIAsmP + 146890U, // BIAsmZ + 1229252U, // BIC + 2296097U, // BICAsm + 340995859U, // BPP + 2488479565U, // BPRP + 6336534U, // BR + 369145782U, // BRAS + 369142111U, // BRASL + 6337182U, // BRAsmE + 6337581U, // BRAsmH + 6337230U, // BRAsmHE + 6337723U, // BRAsmL + 6337249U, // BRAsmLE + 6337652U, // BRAsmLH + 6337842U, // BRAsmM + 6337273U, // BRAsmNE + 6337671U, // BRAsmNH + 6337236U, // BRAsmNHE + 6337798U, // BRAsmNL + 6337255U, // BRAsmNLE + 6337664U, // BRAsmNLH + 6337847U, // BRAsmNM + 6337863U, // BRAsmNO + 6337879U, // BRAsmNP + 6338469U, // BRAsmNZ + 6337858U, // BRAsmO + 6337869U, // BRAsmP + 6338457U, // BRAsmZ + 403882461U, // BRC + 307431826U, // BRCAsm + 403882400U, // BRCL + 307439117U, // BRCLAsm + 402701025U, // BRCT + 402692496U, // BRCTG + 402694734U, // BRCTH + 2181079778U, // BRXH + 2181076987U, // BRXHG + 2181075307U, // BRXLE + 2181077140U, // BRXLG + 67142035U, // BSA + 67148106U, // BSG + 67152790U, // BSM + 2181079767U, // BXH + 2181076981U, // BXHG + 2181075301U, // BXLE + 2181076908U, // BXLEG + 268470490U, // C + 268470735U, // CD + 268468777U, // CDB + 67153947U, // CDBR + 67154198U, // CDFBR + 436240580U, // CDFBRA + 67154743U, // CDFR + 436254256U, // CDFTR + 67154243U, // CDGBR + 436240604U, // CDGBRA + 67154877U, // CDGR + 67155534U, // CDGTR + 436240722U, // CDGTRA + 436252964U, // CDLFBR + 436254263U, // CDLFTR + 436253009U, // CDLGBR + 436254293U, // CDLGTR + 469810017U, // CDPT + 67154460U, // CDR + 2181085506U, // CDS + 2181077332U, // CDSG + 67155582U, // CDSTR + 2181086585U, // CDSY + 67155366U, // CDTR + 67155603U, // CDUTR + 469810152U, // CDZT + 268470941U, // CE + 268469199U, // CEB + 67154079U, // CEBR + 67155378U, // CEDTR + 67154205U, // CEFBR + 436240588U, // CEFBRA + 67154763U, // CEFR + 67154250U, // CEGBR + 436240612U, // CEGBRA + 67154889U, // CEGR + 436252972U, // CELFBR + 436253017U, // CELGBR + 67154596U, // CER + 67155637U, // CEXTR + 6359307U, // CFC + 436252718U, // CFDBR + 436240532U, // CFDBRA + 436253235U, // CFDR + 436254158U, // CFDTR + 436252858U, // CFEBR + 436240556U, // CFEBRA + 436253378U, // CFER + 503358330U, // CFI + 436253086U, // CFXBR + 436240644U, // CFXBRA + 436254543U, // CFXR + 436254410U, // CFXTR + 268474204U, // CG + 436252733U, // CGDBR + 436240540U, // CGDBRA + 436253241U, // CGDR + 436254173U, // CGDTR + 436240700U, // CGDTRA + 436252873U, // CGEBR + 436240564U, // CGEBRA + 436253384U, // CGER + 268473390U, // CGF + 503358341U, // CGFI + 67154776U, // CGFR + 536914099U, // CGFRL + 268475171U, // CGH + 570467288U, // CGHI + 536914176U, // CGHRL + 134292560U, // CGHSI + 611565898U, // CGIB + 2785051889U, // CGIBAsm + 637569634U, // CGIBAsmE + 637573690U, // CGIBAsmH + 637569765U, // CGIBAsmHE + 637576642U, // CGIBAsmL + 637570658U, // CGIBAsmLE + 637574245U, // CGIBAsmLH + 637571454U, // CGIBAsmNE + 637575172U, // CGIBAsmNH + 637570010U, // CGIBAsmNHE + 637576994U, // CGIBAsmNL + 637570906U, // CGIBAsmNLE + 637574541U, // CGIBAsmNLH + 678674911U, // CGIJ + 2785059986U, // CGIJAsm + 2785054223U, // CGIJAsmE + 2785057823U, // CGIJAsmH + 2785053593U, // CGIJAsmHE + 2785060519U, // CGIJAsmL + 2785054483U, // CGIJAsmLE + 2785058096U, // CGIJAsmLH + 2785055265U, // CGIJAsmNE + 2785058984U, // CGIJAsmNH + 2785053833U, // CGIJAsmNHE + 2785060806U, // CGIJAsmNL + 2785054729U, // CGIJAsmNLE + 2785058364U, // CGIJAsmNLH + 8634988U, // CGIT + 2717956915U, // CGITAsm + 570463055U, // CGITAsmE + 570466922U, // CGITAsmH + 570461613U, // CGITAsmHE + 570468782U, // CGITAsmL + 570462509U, // CGITAsmLE + 570466180U, // CGITAsmLH + 570462894U, // CGITAsmNE + 570466613U, // CGITAsmNH + 570461472U, // CGITAsmNHE + 570468435U, // CGITAsmNL + 570462368U, // CGITAsmNLE + 570466010U, // CGITAsmNLH + 67154865U, // CGR + 339984744U, // CGRB + 2214626781U, // CGRBAsm + 2214627966U, // CGRBAsmE + 2214632027U, // CGRBAsmH + 2214628101U, // CGRBAsmHE + 2214634974U, // CGRBAsmL + 2214628994U, // CGRBAsmLE + 2214632581U, // CGRBAsmLH + 2214629790U, // CGRBAsmNE + 2214633508U, // CGRBAsmNH + 2214628350U, // CGRBAsmNHE + 2214635330U, // CGRBAsmNL + 2214629246U, // CGRBAsmNLE + 2214632881U, // CGRBAsmNLH + 2487468531U, // CGRJ + 2214634666U, // CGRJAsm + 2214628907U, // CGRJAsmE + 2214632507U, // CGRJAsmH + 2214628281U, // CGRJAsmHE + 2214635203U, // CGRJAsmL + 2214629171U, // CGRJAsmLE + 2214632784U, // CGRJAsmLH + 2214629953U, // CGRJAsmNE + 2214633672U, // CGRJAsmNH + 2214628525U, // CGRJAsmNHE + 2214635494U, // CGRJAsmNL + 2214629421U, // CGRJAsmNLE + 2214633056U, // CGRJAsmNLH + 536914124U, // CGRL + 306430595U, // CGRT + 2214640509U, // CGRTAsm + 67146608U, // CGRTAsmE + 67150469U, // CGRTAsmH + 67145164U, // CGRTAsmHE + 67152329U, // CGRTAsmL + 67146060U, // CGRTAsmLE + 67149731U, // CGRTAsmLH + 67146445U, // CGRTAsmNE + 67150164U, // CGRTAsmNH + 67145027U, // CGRTAsmNHE + 67151986U, // CGRTAsmNL + 67145923U, // CGRTAsmNLE + 67149565U, // CGRTAsmNLH + 436253101U, // CGXBR + 436240652U, // CGXBRA + 436254549U, // CGXR + 436254425U, // CGXTR + 436240752U, // CGXTRA + 268474996U, // CH + 268473482U, // CHF + 67155017U, // CHHR + 134292575U, // CHHSI + 570467275U, // CHI + 67155158U, // CHLR + 536914152U, // CHRL + 134292546U, // CHSI + 268483842U, // CHY + 611565894U, // CIB + 2785051877U, // CIBAsm + 637569628U, // CIBAsmE + 637573684U, // CIBAsmH + 637569758U, // CIBAsmHE + 637576636U, // CIBAsmL + 637570651U, // CIBAsmLE + 637574238U, // CIBAsmLH + 637571447U, // CIBAsmNE + 637575165U, // CIBAsmNH + 637570002U, // CIBAsmNHE + 637576987U, // CIBAsmNL + 637570898U, // CIBAsmNLE + 637574533U, // CIBAsmNLH + 503356382U, // CIH + 678674907U, // CIJ + 2785059981U, // CIJAsm + 2785054217U, // CIJAsmE + 2785057817U, // CIJAsmH + 2785053586U, // CIJAsmHE + 2785060513U, // CIJAsmL + 2785054476U, // CIJAsmLE + 2785058089U, // CIJAsmLH + 2785055258U, // CIJAsmNE + 2785058977U, // CIJAsmNH + 2785053825U, // CIJAsmNHE + 2785060799U, // CIJAsmNL + 2785054721U, // CIJAsmNLE + 2785058356U, // CIJAsmNLH + 8634978U, // CIT + 2717956903U, // CITAsm + 570463041U, // CITAsmE + 570466908U, // CITAsmH + 570461597U, // CITAsmHE + 570468768U, // CITAsmL + 570462493U, // CITAsmLE + 570466164U, // CITAsmLH + 570462878U, // CITAsmNE + 570466597U, // CITAsmNH + 570461454U, // CITAsmNHE + 570468419U, // CITAsmNL + 570462350U, // CITAsmNLE + 570465992U, // CITAsmNLH + 67152796U, // CKSM + 268477942U, // CL + 604080455U, // CLC + 67151354U, // CLCL + 2214629019U, // CLCLE + 2214640646U, // CLCLU + 436252725U, // CLFDBR + 436254165U, // CLFDTR + 436252865U, // CLFEBR + 704717896U, // CLFHSI + 738239405U, // CLFI + 9683558U, // CLFIT + 2919283500U, // CLFITAsm + 771789639U, // CLFITAsmE + 771793506U, // CLFITAsmH + 771788196U, // CLFITAsmHE + 771795366U, // CLFITAsmL + 771789092U, // CLFITAsmLE + 771792763U, // CLFITAsmLH + 771789477U, // CLFITAsmNE + 771793196U, // CLFITAsmNH + 771788054U, // CLFITAsmNHE + 771795018U, // CLFITAsmNL + 771788950U, // CLFITAsmNLE + 771792592U, // CLFITAsmNLH + 436253093U, // CLFXBR + 436254417U, // CLFXTR + 268474420U, // CLG + 436252740U, // CLGDBR + 436254180U, // CLGDTR + 436252880U, // CLGEBR + 268473408U, // CLGF + 738239378U, // CLGFI + 67154789U, // CLGFR + 536914106U, // CLGFRL + 536914183U, // CLGHRL + 704717911U, // CLGHSI + 614711631U, // CLGIB + 2952824055U, // CLGIBAsm + 805341801U, // CLGIBAsmE + 805345857U, // CLGIBAsmH + 805341933U, // CLGIBAsmHE + 805348809U, // CLGIBAsmL + 805342826U, // CLGIBAsmLE + 805346413U, // CLGIBAsmLH + 805343622U, // CLGIBAsmNE + 805347340U, // CLGIBAsmNH + 805342179U, // CLGIBAsmNHE + 805349162U, // CLGIBAsmNL + 805343075U, // CLGIBAsmNLE + 805346710U, // CLGIBAsmNLH + 681820644U, // CLGIJ + 2952832152U, // CLGIJAsm + 2952826390U, // CLGIJAsmE + 2952829990U, // CLGIJAsmH + 2952825761U, // CLGIJAsmHE + 2952832686U, // CLGIJAsmL + 2952826651U, // CLGIJAsmLE + 2952830264U, // CLGIJAsmLH + 2952827433U, // CLGIJAsmNE + 2952831152U, // CLGIJAsmNH + 2952826002U, // CLGIJAsmNHE + 2952832974U, // CLGIJAsmNL + 2952826898U, // CLGIJAsmNLE + 2952830533U, // CLGIJAsmNLH + 9683569U, // CLGIT + 2919283513U, // CLGITAsm + 771789654U, // CLGITAsmE + 771793521U, // CLGITAsmH + 771788213U, // CLGITAsmHE + 771795381U, // CLGITAsmL + 771789109U, // CLGITAsmLE + 771792780U, // CLGITAsmLH + 771789494U, // CLGITAsmNE + 771793213U, // CLGITAsmNH + 771788073U, // CLGITAsmNHE + 771795035U, // CLGITAsmNL + 771788969U, // CLGITAsmNLE + 771792611U, // CLGITAsmNLH + 67154901U, // CLGR + 339984749U, // CLGRB + 2214626787U, // CLGRBAsm + 2214627973U, // CLGRBAsmE + 2214632034U, // CLGRBAsmH + 2214628109U, // CLGRBAsmHE + 2214634981U, // CLGRBAsmL + 2214629002U, // CLGRBAsmLE + 2214632589U, // CLGRBAsmLH + 2214629798U, // CLGRBAsmNE + 2214633516U, // CLGRBAsmNH + 2214628359U, // CLGRBAsmNHE + 2214635338U, // CLGRBAsmNL + 2214629255U, // CLGRBAsmNLE + 2214632890U, // CLGRBAsmNLH + 2487468536U, // CLGRJ + 2214634672U, // CLGRJAsm + 2214628914U, // CLGRJAsmE + 2214632514U, // CLGRJAsmH + 2214628289U, // CLGRJAsmHE + 2214635210U, // CLGRJAsmL + 2214629179U, // CLGRJAsmLE + 2214632792U, // CLGRJAsmLH + 2214629961U, // CLGRJAsmNE + 2214633680U, // CLGRJAsmNH + 2214628534U, // CLGRJAsmNHE + 2214635502U, // CLGRJAsmNL + 2214629430U, // CLGRJAsmNLE + 2214633065U, // CLGRJAsmNLH + 536914130U, // CLGRL + 306430600U, // CLGRT + 2214640515U, // CLGRTAsm + 67146615U, // CLGRTAsmE + 67150476U, // CLGRTAsmH + 67145172U, // CLGRTAsmHE + 67152336U, // CLGRTAsmL + 67146068U, // CLGRTAsmLE + 67149739U, // CLGRTAsmLH + 67146453U, // CLGRTAsmNE + 67150172U, // CLGRTAsmNH + 67145036U, // CLGRTAsmNHE + 67151994U, // CLGRTAsmNL + 67145932U, // CLGRTAsmNLE + 67149574U, // CLGRTAsmNLH + 279133U, // CLGT + 2986392347U, // CLGTAsm + 872452922U, // CLGTAsmE + 872456789U, // CLGTAsmH + 872451477U, // CLGTAsmHE + 872458649U, // CLGTAsmL + 872452373U, // CLGTAsmLE + 872456044U, // CLGTAsmLH + 872452758U, // CLGTAsmNE + 872456477U, // CLGTAsmNH + 872451333U, // CLGTAsmNHE + 872458299U, // CLGTAsmNL + 872452229U, // CLGTAsmNLE + 872455871U, // CLGTAsmNLH + 436253108U, // CLGXBR + 436254432U, // CLGXTR + 268473526U, // CLHF + 67155053U, // CLHHR + 704717926U, // CLHHSI + 67155194U, // CLHLR + 536914199U, // CLHRL + 906044432U, // CLI + 614711637U, // CLIB + 2952824062U, // CLIBAsm + 805341809U, // CLIBAsmE + 805345865U, // CLIBAsmH + 805341942U, // CLIBAsmHE + 805348817U, // CLIBAsmL + 805342835U, // CLIBAsmLE + 805346422U, // CLIBAsmLH + 805343631U, // CLIBAsmNE + 805347349U, // CLIBAsmNH + 805342189U, // CLIBAsmNHE + 805349171U, // CLIBAsmNL + 805343085U, // CLIBAsmNLE + 805346720U, // CLIBAsmNLH + 738237444U, // CLIH + 681820650U, // CLIJ + 2952832159U, // CLIJAsm + 2952826398U, // CLIJAsmE + 2952829998U, // CLIJAsmH + 2952825770U, // CLIJAsmHE + 2952832694U, // CLIJAsmL + 2952826660U, // CLIJAsmLE + 2952830273U, // CLIJAsmLH + 2952827442U, // CLIJAsmNE + 2952831161U, // CLIJAsmNH + 2952826012U, // CLIJAsmNHE + 2952832983U, // CLIJAsmNL + 2952826908U, // CLIJAsmNLE + 2952830543U, // CLIJAsmNLH + 906050844U, // CLIY + 436251297U, // CLM + 436248549U, // CLMH + 436256096U, // CLMY + 67155136U, // CLR + 339984755U, // CLRB + 2214626794U, // CLRBAsm + 2214627981U, // CLRBAsmE + 2214632042U, // CLRBAsmH + 2214628118U, // CLRBAsmHE + 2214634989U, // CLRBAsmL + 2214629011U, // CLRBAsmLE + 2214632598U, // CLRBAsmLH + 2214629807U, // CLRBAsmNE + 2214633525U, // CLRBAsmNH + 2214628369U, // CLRBAsmNHE + 2214635347U, // CLRBAsmNL + 2214629265U, // CLRBAsmNLE + 2214632900U, // CLRBAsmNLH + 2487468542U, // CLRJ + 2214634679U, // CLRJAsm + 2214628922U, // CLRJAsmE + 2214632522U, // CLRJAsmH + 2214628298U, // CLRJAsmHE + 2214635218U, // CLRJAsmL + 2214629188U, // CLRJAsmLE + 2214632801U, // CLRJAsmLH + 2214629970U, // CLRJAsmNE + 2214633689U, // CLRJAsmNH + 2214628544U, // CLRJAsmNHE + 2214635511U, // CLRJAsmNL + 2214629440U, // CLRJAsmNLE + 2214633075U, // CLRJAsmNLH + 536914220U, // CLRL + 306430606U, // CLRT + 2214640522U, // CLRTAsm + 67146623U, // CLRTAsmE + 67150484U, // CLRTAsmH + 67145181U, // CLRTAsmHE + 67152344U, // CLRTAsmL + 67146077U, // CLRTAsmLE + 67149748U, // CLRTAsmLH + 67146462U, // CLRTAsmNE + 67150181U, // CLRTAsmNH + 67145046U, // CLRTAsmNHE + 67152003U, // CLRTAsmNL + 67145942U, // CLRTAsmNLE + 67149584U, // CLRTAsmNLH + 67156893U, // CLST + 279159U, // CLT + 2986392384U, // CLTAsm + 872452958U, // CLTAsmE + 872456825U, // CLTAsmH + 872451518U, // CLTAsmHE + 872458685U, // CLTAsmL + 872452414U, // CLTAsmLE + 872456085U, // CLTAsmLH + 872452799U, // CLTAsmNE + 872456518U, // CLTAsmNH + 872451379U, // CLTAsmNHE + 872458340U, // CLTAsmNL + 872452275U, // CLTAsmNLE + 872455917U, // CLTAsmNLH + 268483900U, // CLY + 67144112U, // CMPSC + 234991008U, // CP + 469809915U, // CPDT + 2181083769U, // CPSDRdd + 2181083769U, // CPSDRds + 2181083769U, // CPSDRsd + 2181083769U, // CPSDRss + 469810134U, // CPXT + 67142062U, // CPYA + 67154418U, // CR + 339984740U, // CRB + 2214626776U, // CRBAsm + 2214627960U, // CRBAsmE + 2214632021U, // CRBAsmH + 2214628094U, // CRBAsmHE + 2214634968U, // CRBAsmL + 2214628987U, // CRBAsmLE + 2214632574U, // CRBAsmLH + 2214629783U, // CRBAsmNE + 2214633501U, // CRBAsmNH + 2214628342U, // CRBAsmNHE + 2214635323U, // CRBAsmNL + 2214629238U, // CRBAsmNLE + 2214632873U, // CRBAsmNLH + 2181075763U, // CRDTE + 2181075763U, // CRDTEOpt + 2487468527U, // CRJ + 2214634661U, // CRJAsm + 2214628901U, // CRJAsmE + 2214632501U, // CRJAsmH + 2214628274U, // CRJAsmHE + 2214635197U, // CRJAsmL + 2214629164U, // CRJAsmLE + 2214632777U, // CRJAsmLH + 2214629946U, // CRJAsmNE + 2214633665U, // CRJAsmNH + 2214628517U, // CRJAsmNHE + 2214635487U, // CRJAsmNL + 2214629413U, // CRJAsmNLE + 2214633048U, // CRJAsmNLH + 536914080U, // CRL + 306430591U, // CRT + 2214640504U, // CRTAsm + 67146602U, // CRTAsmE + 67150463U, // CRTAsmH + 67145157U, // CRTAsmHE + 67152323U, // CRTAsmL + 67146053U, // CRTAsmLE + 67149724U, // CRTAsmLH + 67146438U, // CRTAsmNE + 67150157U, // CRTAsmNH + 67145019U, // CRTAsmNHE + 67151979U, // CRTAsmNL + 67145915U, // CRTAsmNLE + 67149557U, // CRTAsmNLH + 2181085502U, // CS + 16803U, // CSCH + 2214639110U, // CSDTR + 2181077327U, // CSG + 33599332U, // CSP + 33593587U, // CSPG + 3087088553U, // CSST + 2214639362U, // CSXTR + 2181086580U, // CSY + 2214625293U, // CU12 + 67141645U, // CU12Opt + 2214625305U, // CU14 + 67141657U, // CU14Opt + 2214625281U, // CU21 + 67141633U, // CU21Opt + 2214625311U, // CU24 + 67141663U, // CU24Opt + 67141639U, // CU41 + 67141651U, // CU42 + 67155483U, // CUDTR + 67146535U, // CUSE + 2214640632U, // CUTFU + 67156984U, // CUTFUOpt + 2214631021U, // CUUTF + 67147373U, // CUUTFOpt + 67155735U, // CUXTR + 34716U, // CVB + 38739U, // CVBG + 48317U, // CVBY + 268470844U, // CVD + 268474259U, // CVDG + 268483801U, // CVDY + 67154314U, // CXBR + 67154236U, // CXFBR + 436240596U, // CXFBRA + 67154845U, // CXFR + 436254279U, // CXFTR + 67154281U, // CXGBR + 436240620U, // CXGBRA + 67154983U, // CXGR + 67155564U, // CXGTR + 436240730U, // CXGTRA + 436252980U, // CXLFBR + 436254271U, // CXLFTR + 436253025U, // CXLGBR + 436254308U, // CXLGTR + 469810034U, // CXPT + 67155774U, // CXR + 67155596U, // CXSTR + 67155624U, // CXTR + 67155610U, // CXUTR + 469810158U, // CXZT + 268483780U, // CY + 469809927U, // CZDT + 469810146U, // CZXT + 35276U, // D + 35283U, // DD + 33350U, // DDB + 33599521U, // DDBR + 33600033U, // DDR + 2214639020U, // DDTR + 2214625589U, // DDTRA + 35510U, // DE + 33750U, // DEB + 33599654U, // DEBR + 33600171U, // DER + 2214627582U, // DFLTCC + 2214631163U, // DIAG + 2214637644U, // DIDBR + 2214637784U, // DIEBR + 42523U, // DL + 38971U, // DLG + 33600475U, // DLGR + 33600709U, // DLR + 234991029U, // DP + 33600017U, // DR + 39253U, // DSG + 37986U, // DSGF + 33600392U, // DSGFR + 33600519U, // DSGR + 33599889U, // DXBR + 33601348U, // DXR + 2214639279U, // DXTR + 2214625641U, // DXTRA + 67153903U, // EAR + 2214631157U, // ECAG + 67155324U, // ECCTR + 67141717U, // ECPGA + 3087079809U, // ECTG + 604080601U, // ED + 604087574U, // EDMK + 67155385U, // EEDTR + 67155644U, // EEXTR + 6326649U, // EFPC + 6337690U, // EPAIR + 6336508U, // EPAR + 67155345U, // EPCTR + 67157105U, // EPSW + 67147699U, // EREG + 67147718U, // EREGG + 6337697U, // ESAIR + 6336514U, // ESAR + 67155469U, // ESDTR + 6324285U, // ESEA + 67142046U, // ESTA + 67155721U, // ESXTR + 6326797U, // ETND + 268483721U, // EX + 536914265U, // EXRL + 436252755U, // FIDBR + 436240548U, // FIDBRA + 67154507U, // FIDR + 436254188U, // FIDTR + 436252895U, // FIEBR + 436240572U, // FIEBRA + 67154651U, // FIER + 436253116U, // FIXBR + 436240660U, // FIXBRA + 67155803U, // FIXR + 436254440U, // FIXTR + 67154938U, // FLOGR + 67154502U, // HDR + 67154639U, // HER + 16808U, // HSCH + 6326488U, // IAC + 35106U, // IC + 35106U, // IC32 + 48323U, // IC32Y + 973122086U, // ICM + 973119427U, // ICMH + 973126995U, // ICMY + 48323U, // ICY + 2181075757U, // IDTE + 2181075757U, // IDTEOpt + 2181084608U, // IEDTR + 2181084867U, // IEXTR + 738235535U, // IIHF + 704682875U, // IIHH + 704685667U, // IIHL + 738235680U, // IILF + 704683280U, // IILH + 704685791U, // IILL + 16899U, // IPK + 6335309U, // IPM + 2214630244U, // IPTE + 2214630244U, // IPTEOpt + 67146596U, // IPTEOptOpt + 67152410U, // IRBM + 33590856U, // ISKE + 33596837U, // IVSK + 6602464U, // InsnE + 1011171137U, // InsnRI + 1011203817U, // InsnRIE + 3158687606U, // InsnRIL + 3158687711U, // InsnRILU + 1011204010U, // InsnRIS + 11845516U, // InsnRR + 1011171060U, // InsnRRE + 1011171104U, // InsnRRF + 1011204031U, // InsnRRS + 1011171253U, // InsnRS + 1011203839U, // InsnRSE + 1011203936U, // InsnRSI + 1011204118U, // InsnRSY + 3158654966U, // InsnRX + 3158687509U, // InsnRXE + 1011203894U, // InsnRXF + 3158687777U, // InsnRXY + 314916769U, // InsnS + 1019559766U, // InsnSI + 3167076225U, // InsnSIL + 1019592715U, // InsnSIY + 14008277U, // InsnSS + 1019592458U, // InsnSSE + 1019592491U, // InsnSSF + 1011203915U, // InsnVRI + 1011203990U, // InsnVRR + 15056842U, // InsnVRS + 3158687723U, // InsnVRV + 3158687744U, // InsnVRX + 1011203947U, // InsnVSI + 402575U, // J + 396811U, // JAsmE + 400411U, // JAsmH + 396180U, // JAsmHE + 403107U, // JAsmL + 397070U, // JAsmLE + 400683U, // JAsmLH + 404121U, // JAsmM + 397852U, // JAsmNE + 401571U, // JAsmNH + 396419U, // JAsmNHE + 403393U, // JAsmNL + 397315U, // JAsmNLE + 400950U, // JAsmNLH + 404236U, // JAsmNM + 404719U, // JAsmNO + 405201U, // JAsmNP + 409185U, // JAsmNZ + 404590U, // JAsmO + 405090U, // JAsmP + 409065U, // JAsmZ + 399385U, // JG + 395993U, // JGAsmE + 400183U, // JGAsmH + 396118U, // JGAsmHE + 403008U, // JGAsmL + 397008U, // JGAsmLE + 400581U, // JGAsmLH + 404056U, // JGAsmM + 397790U, // JGAsmNE + 401509U, // JGAsmNH + 396350U, // JGAsmNHE + 403331U, // JGAsmNL + 397246U, // JGAsmNLE + 400881U, // JGAsmNLH + 404176U, // JGAsmNM + 404659U, // JGAsmNO + 405141U, // JGAsmNP + 409125U, // JGAsmNZ + 404537U, // JGAsmO + 405009U, // JGAsmP + 409012U, // JGAsmZ + 268468996U, // KDB + 67154010U, // KDBR + 6717848U, // KDSA + 67155443U, // KDTR + 268469267U, // KEB + 67154150U, // KEBR + 6720001U, // KIMD + 6720007U, // KLMD + 67152541U, // KM + 2181070971U, // KMA + 6719709U, // KMAC + 67144022U, // KMC + 2181084554U, // KMCTR + 67147172U, // KMF + 67153028U, // KMO + 67154371U, // KXBR + 67155695U, // KXTR + 268477870U, // L + 268468330U, // LA + 2214625324U, // LAA + 2214631151U, // LAAG + 2214634923U, // LAAL + 2214631459U, // LAALG + 268470865U, // LAE + 268483807U, // LAEY + 2214636041U, // LAM + 2214640966U, // LAMY + 2214636488U, // LAN + 2214631618U, // LANG + 2214636558U, // LAO + 2214631630U, // LAOG + 536914072U, // LARL + 939601758U, // LASP + 268483271U, // LAT + 2214640765U, // LAX + 2214631917U, // LAXG + 268483757U, // LAY + 268469519U, // LB + 6369261U, // LBEAR + 268474960U, // LBH + 67154289U, // LBR + 2415952336U, // LCBB + 6367607U, // LCCTL + 67153946U, // LCDBR + 67154742U, // LCDFR + 67154742U, // LCDFR_32 + 67154459U, // LCDR + 67154078U, // LCEBR + 67154595U, // LCER + 67154775U, // LCGFR + 67154864U, // LCGR + 67154430U, // LCR + 2214635902U, // LCTL + 2214631558U, // LCTLG + 67154313U, // LCXBR + 67155773U, // LCXR + 268470775U, // LD + 268470965U, // LDE + 268470965U, // LDE32 + 268469205U, // LDEB + 67154085U, // LDEBR + 67154608U, // LDER + 2214639145U, // LDETR + 67154883U, // LDGR + 67154513U, // LDR + 67154513U, // LDR32 + 67154320U, // LDXBR + 436240628U, // LDXBRA + 67155779U, // LDXR + 436254382U, // LDXTR + 268483790U, // LDY + 268471895U, // LE + 67153959U, // LEDBR + 436240524U, // LEDBRA + 67154477U, // LEDR + 436254151U, // LEDTR + 67154658U, // LER + 67154327U, // LEXBR + 436240636U, // LEXBRA + 67155785U, // LEXR + 268483813U, // LEY + 6371248U, // LFAS + 268475153U, // LFH + 268483264U, // LFHAT + 6359423U, // LFPC + 268474406U, // LG + 268483258U, // LGAT + 268469386U, // LGB + 67154259U, // LGBR + 67154495U, // LGDR + 268473403U, // LGF + 503358348U, // LGFI + 67154783U, // LGFR + 536914107U, // LGFRL + 268474317U, // LGG + 268475197U, // LGH + 570467294U, // LGHI + 67155011U, // LGHR + 536914184U, // LGHRL + 67154896U, // LGR + 536914131U, // LGRL + 268470686U, // LGSC + 268475482U, // LH + 268475287U, // LHH + 570467328U, // LHI + 67155061U, // LHR + 536914200U, // LHRL + 268483847U, // LHY + 268470604U, // LLC + 268475012U, // LLCH + 67154435U, // LLCR + 268470549U, // LLGC + 67154422U, // LLGCR + 268473414U, // LLGF + 268483250U, // LLGFAT + 67154796U, // LLGFR + 536914114U, // LLGFRL + 268474714U, // LLGFSG + 268475196U, // LLGH + 67155010U, // LLGHR + 536914191U, // LLGHRL + 268483361U, // LLGT + 268483276U, // LLGTAT + 67155549U, // LLGTR + 268475756U, // LLH + 268475292U, // LLHH + 67155066U, // LLHR + 536914206U, // LLHRL + 738235541U, // LLIHF + 771791745U, // LLIHH + 771794537U, // LLIHL + 738235686U, // LLILF + 771792150U, // LLILH + 771794661U, // LLILL + 268473434U, // LLZRGF + 2214636194U, // LM + 2214627848U, // LMD + 2214631600U, // LMG + 2214633446U, // LMH + 2214640993U, // LMY + 67154022U, // LNDBR + 67154749U, // LNDFR + 67154749U, // LNDFR_32 + 67154523U, // LNDR + 67154156U, // LNEBR + 67154687U, // LNER + 67154810U, // LNGFR + 67154932U, // LNGR + 67155261U, // LNR + 67154383U, // LNXBR + 67155819U, // LNXR + 475516U, // LOC + 3087042921U, // LOCAsm + 939559591U, // LOCAsmE + 939563664U, // LOCAsmH + 939559717U, // LOCAsmHE + 939566592U, // LOCAsmL + 939560610U, // LOCAsmLE + 939564197U, // LOCAsmLH + 939567659U, // LOCAsmM + 939561399U, // LOCAsmNE + 939565117U, // LOCAsmNH + 939559962U, // LOCAsmNHE + 939566939U, // LOCAsmNL + 939560858U, // LOCAsmNLE + 939564493U, // LOCAsmNLH + 939567792U, // LOCAsmNM + 939568275U, // LOCAsmNO + 939568757U, // LOCAsmNP + 939572741U, // LOCAsmNZ + 939568157U, // LOCAsmO + 939568542U, // LOCAsmP + 939572625U, // LOCAsmZ + 475575U, // LOCFH + 3087047426U, // LOCFHAsm + 939559732U, // LOCFHAsmE + 939563882U, // LOCFHAsmH + 939559772U, // LOCFHAsmHE + 939566674U, // LOCFHAsmL + 939560662U, // LOCFHAsmLE + 939564250U, // LOCFHAsmLH + 939567714U, // LOCFHAsmM + 939561444U, // LOCFHAsmNE + 939565163U, // LOCFHAsmNH + 939560005U, // LOCFHAsmNHE + 939566985U, // LOCFHAsmNL + 939560901U, // LOCFHAsmNLE + 939564536U, // LOCFHAsmNLH + 939567830U, // LOCFHAsmNM + 939568313U, // LOCFHAsmNO + 939568795U, // LOCFHAsmNP + 939572779U, // LOCFHAsmNZ + 939568190U, // LOCFHAsmO + 939568676U, // LOCFHAsmP + 939572665U, // LOCFHAsmZ + 318227015U, // LOCFHR + 2181084210U, // LOCFHRAsm + 33592066U, // LOCFHRAsmE + 33595906U, // LOCFHRAsmH + 33590649U, // LOCFHRAsmHE + 33597678U, // LOCFHRAsmL + 33591545U, // LOCFHRAsmLE + 33595194U, // LOCFHRAsmLH + 33598333U, // LOCFHRAsmM + 33591930U, // LOCFHRAsmNE + 33595649U, // LOCFHRAsmNH + 33590502U, // LOCFHRAsmNHE + 33597471U, // LOCFHRAsmNL + 33591398U, // LOCFHRAsmNLE + 33595040U, // LOCFHRAsmNLH + 33598251U, // LOCFHRAsmNM + 33598740U, // LOCFHRAsmNO + 33599216U, // LOCFHRAsmNP + 33603200U, // LOCFHRAsmNZ + 33598815U, // LOCFHRAsmO + 33599284U, // LOCFHRAsmP + 33603260U, // LOCFHRAsmZ + 475541U, // LOCG + 3087046521U, // LOCGAsm + 939559626U, // LOCGAsmE + 939563809U, // LOCGAsmH + 939559749U, // LOCGAsmHE + 939566641U, // LOCGAsmL + 939560639U, // LOCGAsmLE + 939564212U, // LOCGAsmLH + 939567689U, // LOCGAsmM + 939561421U, // LOCGAsmNE + 939565140U, // LOCGAsmNH + 939559979U, // LOCGAsmNHE + 939566962U, // LOCGAsmNL + 939560875U, // LOCGAsmNLE + 939564510U, // LOCGAsmNLH + 939567807U, // LOCGAsmNM + 939568290U, // LOCGAsmNO + 939568772U, // LOCGAsmNP + 939572756U, // LOCGAsmNZ + 939568170U, // LOCGAsmO + 939568636U, // LOCGAsmP + 939572645U, // LOCGAsmZ + 17285581U, // LOCGHI + 2281743318U, // LOCGHIAsm + 134254066U, // LOCGHIAsmE + 134257650U, // LOCGHIAsmH + 134253438U, // LOCGHIAsmHE + 134260367U, // LOCGHIAsmL + 134254328U, // LOCGHIAsmLE + 134257916U, // LOCGHIAsmLH + 134261376U, // LOCGHIAsmM + 134255110U, // LOCGHIAsmNE + 134258829U, // LOCGHIAsmNH + 134253675U, // LOCGHIAsmNHE + 134260651U, // LOCGHIAsmNL + 134254571U, // LOCGHIAsmNLE + 134258206U, // LOCGHIAsmNLH + 134261496U, // LOCGHIAsmNM + 134261979U, // LOCGHIAsmNO + 134262461U, // LOCGHIAsmNP + 134266445U, // LOCGHIAsmNZ + 134261852U, // LOCGHIAsmO + 134262346U, // LOCGHIAsmP + 134266327U, // LOCGHIAsmZ + 318227003U, // LOCGR + 2181084086U, // LOCGRAsm + 33592050U, // LOCGRAsmE + 33595890U, // LOCGRAsmH + 33590631U, // LOCGRAsmHE + 33597642U, // LOCGRAsmL + 33591527U, // LOCGRAsmLE + 33595176U, // LOCGRAsmLH + 33598317U, // LOCGRAsmM + 33591912U, // LOCGRAsmNE + 33595631U, // LOCGRAsmNH + 33590482U, // LOCGRAsmNHE + 33597453U, // LOCGRAsmNL + 33591378U, // LOCGRAsmNLE + 33595020U, // LOCGRAsmNLH + 33598233U, // LOCGRAsmNM + 33598722U, // LOCGRAsmNO + 33599198U, // LOCGRAsmNP + 33603182U, // LOCGRAsmNZ + 33598799U, // LOCGRAsmO + 33599268U, // LOCGRAsmP + 33603244U, // LOCGRAsmZ + 17285588U, // LOCHHI + 2281743345U, // LOCHHIAsm + 134254075U, // LOCHHIAsmE + 134257659U, // LOCHHIAsmH + 134253448U, // LOCHHIAsmHE + 134260376U, // LOCHHIAsmL + 134254338U, // LOCHHIAsmLE + 134257926U, // LOCHHIAsmLH + 134261385U, // LOCHHIAsmM + 134255120U, // LOCHHIAsmNE + 134258839U, // LOCHHIAsmNH + 134253686U, // LOCHHIAsmNHE + 134260661U, // LOCHHIAsmNL + 134254582U, // LOCHHIAsmNLE + 134258217U, // LOCHHIAsmNLH + 134261506U, // LOCHHIAsmNM + 134261989U, // LOCHHIAsmNO + 134262471U, // LOCHHIAsmNP + 134266455U, // LOCHHIAsmNZ + 134261861U, // LOCHHIAsmO + 134262355U, // LOCHHIAsmP + 134266336U, // LOCHHIAsmZ + 17285575U, // LOCHI + 2281743305U, // LOCHIAsm + 134254058U, // LOCHIAsmE + 134257642U, // LOCHIAsmH + 134253429U, // LOCHIAsmHE + 134260359U, // LOCHIAsmL + 134254319U, // LOCHIAsmLE + 134257907U, // LOCHIAsmLH + 134261368U, // LOCHIAsmM + 134255101U, // LOCHIAsmNE + 134258820U, // LOCHIAsmNH + 134253665U, // LOCHIAsmNHE + 134260642U, // LOCHIAsmNL + 134254561U, // LOCHIAsmNLE + 134258196U, // LOCHIAsmNLH + 134261487U, // LOCHIAsmNM + 134261970U, // LOCHIAsmNO + 134262452U, // LOCHIAsmNP + 134266436U, // LOCHIAsmNZ + 134261844U, // LOCHIAsmO + 134262338U, // LOCHIAsmP + 134266319U, // LOCHIAsmZ + 318226998U, // LOCR + 2181083657U, // LOCRAsm + 33592043U, // LOCRAsmE + 33595868U, // LOCRAsmH + 33590623U, // LOCRAsmHE + 33597598U, // LOCRAsmL + 33591519U, // LOCRAsmLE + 33595168U, // LOCRAsmLH + 33598295U, // LOCRAsmM + 33591904U, // LOCRAsmNE + 33595623U, // LOCRAsmNH + 33590473U, // LOCRAsmNHE + 33597445U, // LOCRAsmNL + 33591369U, // LOCRAsmNLE + 33595011U, // LOCRAsmNLH + 33598225U, // LOCRAsmNM + 33598714U, // LOCRAsmNO + 33599190U, // LOCRAsmNP + 33603174U, // LOCRAsmNZ + 33598785U, // LOCRAsmO + 33599261U, // LOCRAsmP + 33603237U, // LOCRAsmZ + 6367620U, // LPCTL + 3019934227U, // LPD + 67154029U, // LPDBR + 67154756U, // LPDFR + 67154756U, // LPDFR_32 + 3019937676U, // LPDG + 67154529U, // LPDR + 67154163U, // LPEBR + 67154693U, // LPER + 67154817U, // LPGFR + 67154945U, // LPGR + 6369048U, // LPP + 268480456U, // LPQ + 67155282U, // LPR + 6372471U, // LPSW + 6362001U, // LPSWE + 6372592U, // LPSWEY + 2214625347U, // LPTEA + 67154390U, // LPXBR + 67155825U, // LPXR + 67155127U, // LR + 268468508U, // LRA + 268474127U, // LRAG + 268483767U, // LRAY + 67154541U, // LRDR + 67154705U, // LRER + 536914221U, // LRL + 268483652U, // LRV + 268474848U, // LRVG + 67154976U, // LRVGR + 268477130U, // LRVH + 67155752U, // LRVR + 6367627U, // LSCTL + 268483393U, // LT + 67154050U, // LTDBR + 67154560U, // LTDR + 67155476U, // LTDTR + 67154184U, // LTEBR + 67154717U, // LTER + 268474782U, // LTG + 268473454U, // LTGF + 67154838U, // LTGFR + 67154970U, // LTGR + 67155571U, // LTR + 67154410U, // LTXBR + 67155842U, // LTXR + 67155728U, // LTXTR + 67142022U, // LURA + 67147556U, // LURAG + 268470849U, // LXD + 268469172U, // LXDB + 67154057U, // LXDBR + 67154566U, // LXDR + 2214639138U, // LXDTR + 268473240U, // LXE + 268469326U, // LXEB + 67154191U, // LXEBR + 67154730U, // LXER + 67155809U, // LXR + 268483896U, // LY + 6337170U, // LZDR + 6337328U, // LZER + 268473917U, // LZRF + 268474692U, // LZRG + 6338440U, // LZXR + 43531U, // M + 2181073354U, // MAD + 2181071367U, // MADB + 2181083155U, // MADBR + 2181083663U, // MADR + 2181073495U, // MAE + 2181071816U, // MAEB + 2181083287U, // MAEBR + 2181083800U, // MAER + 2181086386U, // MAY + 2181079784U, // MAYH + 2181084301U, // MAYHR + 2181081590U, // MAYL + 2181084453U, // MAYLR + 2181085070U, // MAYR + 906037591U, // MC + 35331U, // MD + 33554U, // MDB + 33599584U, // MDBR + 35514U, // MDE + 33762U, // MDEB + 33599660U, // MDEBR + 33600182U, // MDER + 33600086U, // MDR + 2214639097U, // MDTR + 2214625604U, // MDTRA + 37235U, // ME + 35525U, // MEE + 33775U, // MEEB + 33599667U, // MEEBR + 33600188U, // MEER + 33600244U, // MER + 48376U, // MFY + 39070U, // MG + 39749U, // MGH + 134259684U, // MGHI + 2214634842U, // MGRK + 40901U, // MH + 134259717U, // MHI + 48396U, // MHY + 42775U, // ML + 39005U, // MLG + 33600488U, // MLGR + 33600769U, // MLR + 234991212U, // MP + 33600819U, // MR + 47747U, // MS + 35243U, // MSC + 6363813U, // MSCH + 2181073457U, // MSD + 2181071746U, // MSDB + 2181083259U, // MSDBR + 2181083763U, // MSDR + 2181075746U, // MSE + 2181071937U, // MSEB + 2181083393U, // MSEBR + 2181083927U, // MSER + 100705209U, // MSFI + 39281U, // MSG + 35099U, // MSGC + 37992U, // MSGF + 100705184U, // MSGFI + 33600399U, // MSGFR + 33600525U, // MSGR + 2214627635U, // MSGRKC + 33600881U, // MSR + 2214627643U, // MSRKC + 6324644U, // MSTA + 48511U, // MSY + 604080572U, // MVC + 939599072U, // MVCDK + 604089315U, // MVCIN + 533722U, // MVCK + 67151379U, // MVCL + 2214629041U, // MVCLE + 2214640653U, // MVCLU + 3087088270U, // MVCOS + 535979U, // MVCP + 939600037U, // MVCRL + 538940U, // MVCS + 939599262U, // MVCSK + 134292458U, // MVGHI + 134292473U, // MVHHI + 134292490U, // MVHI + 906044548U, // MVI + 906050860U, // MVIY + 604089353U, // MVN + 234990981U, // MVO + 67148025U, // MVPG + 67156911U, // MVST + 604094171U, // MVZ + 33599945U, // MXBR + 35398U, // MXD + 33722U, // MXDB + 33599632U, // MXDBR + 33600140U, // MXDR + 33601382U, // MXR + 2214639349U, // MXTR + 2214625656U, // MXTRA + 2214640968U, // MY + 2214634222U, // MYH + 2214638740U, // MYHR + 2214636028U, // MYL + 2214638892U, // MYLR + 2214639508U, // MYR + 43978U, // N + 604080480U, // NC + 2214634814U, // NCGRK + 2214634796U, // NCRK + 39108U, // NG + 33600501U, // NGR + 2214634849U, // NGRK + 906044437U, // NI + 18031430U, // NIAI + 201364636U, // NIHF + 704682888U, // NIHH + 704685680U, // NIHL + 201364781U, // NILF + 704683293U, // NILH + 704685804U, // NILL + 906050850U, // NIY + 2214634848U, // NNGRK + 16705U, // NNPA + 2214634887U, // NNRK + 2214634855U, // NOGRK + 16946U, // NOP_bare + 2214634893U, // NORK + 33600830U, // NR + 2214634888U, // NRK + 268474787U, // NTSTG + 2214634868U, // NXGRK + 2214634904U, // NXRK + 48492U, // NY + 44048U, // O + 604080490U, // OC + 2214634821U, // OCGRK + 2214634802U, // OCRK + 39120U, // OG + 33600508U, // OGR + 2214634856U, // OGRK + 906044441U, // OI + 201364642U, // OIHF + 704682894U, // OIHH + 704685686U, // OIHL + 201364787U, // OILF + 704683299U, // OILH + 704685810U, // OILL + 906050855U, // OIY + 33600835U, // OR + 2214634894U, // ORK + 48496U, // OY + 234988745U, // PACK + 16730U, // PALB + 6359419U, // PC + 16760U, // PCC + 16930U, // PCKMO + 2296285U, // PFD + 307439788U, // PFDRL + 6722960U, // PFMF + 16936U, // PFPO + 67152882U, // PGIN + 67156923U, // PGOUT + 1040253022U, // PKA + 1040268289U, // PKU + 3019943039U, // PLO + 67156812U, // POPCNT + 2214640460U, // POPCNTOpt + 2214625415U, // PPA + 67153140U, // PPNO + 16986U, // PR + 67153200U, // PRNO + 67156835U, // PT + 6329960U, // PTF + 16778U, // PTFF + 67150975U, // PTI + 16735U, // PTLB + 2214639007U, // QADTR + 2214639265U, // QAXTR + 6366249U, // QCTRI + 6366049U, // QPACI + 6366324U, // QSI + 16941U, // RCHP + 2181082560U, // RDP + 2181082560U, // RDPOpt + 2181076790U, // RISBG + 2181076790U, // RISBG32 + 2181082067U, // RISBGN + 2181076960U, // RISBHG + 2181077034U, // RISBLG + 2214635271U, // RLL + 2214631505U, // RLLG + 2181076797U, // RNSBG + 2181076804U, // ROSBG + 6369056U, // RP + 67144340U, // RRBE + 67152416U, // RRBM + 2214639103U, // RRDTR + 2214639355U, // RRXTR + 16813U, // RSCH + 2181076811U, // RXSBG + 47021U, // S + 6359267U, // SAC + 6362044U, // SACF + 16903U, // SAL + 16588U, // SAM24 + 16576U, // SAM31 + 16594U, // SAM64 + 67153923U, // SAR + 67155331U, // SCCTR + 16925U, // SCHM + 6366415U, // SCK + 6359334U, // SCKC + 16783U, // SCKPF + 35378U, // SD + 33652U, // SDB + 33599612U, // SDBR + 33600116U, // SDR + 2214639111U, // SDTR + 2214625611U, // SDTRA + 37667U, // SE + 33858U, // SEB + 33599746U, // SEBR + 351781454U, // SELFHR + 2181084218U, // SELFHRAsm + 2181075723U, // SELFHRAsmE + 2181079563U, // SELFHRAsmH + 2181074307U, // SELFHRAsmHE + 2181081335U, // SELFHRAsmL + 2181075203U, // SELFHRAsmLE + 2181078852U, // SELFHRAsmLH + 2181081990U, // SELFHRAsmM + 2181075588U, // SELFHRAsmNE + 2181079307U, // SELFHRAsmNH + 2181074161U, // SELFHRAsmNHE + 2181081129U, // SELFHRAsmNL + 2181075057U, // SELFHRAsmNLE + 2181078699U, // SELFHRAsmNLH + 2181081909U, // SELFHRAsmNM + 2181082398U, // SELFHRAsmNO + 2181082874U, // SELFHRAsmNP + 2181086858U, // SELFHRAsmNZ + 2181082472U, // SELFHRAsmO + 2181082941U, // SELFHRAsmP + 2181086917U, // SELFHRAsmZ + 351781441U, // SELGR + 2181084129U, // SELGRAsm + 2181075706U, // SELGRAsmE + 2181079546U, // SELGRAsmH + 2181074288U, // SELGRAsmHE + 2181081305U, // SELGRAsmL + 2181075184U, // SELGRAsmLE + 2181078833U, // SELGRAsmLH + 2181081973U, // SELGRAsmM + 2181075569U, // SELGRAsmNE + 2181079288U, // SELGRAsmNH + 2181074140U, // SELGRAsmNHE + 2181081110U, // SELGRAsmNL + 2181075036U, // SELGRAsmNLE + 2181078678U, // SELGRAsmNLH + 2181081890U, // SELGRAsmNM + 2181082379U, // SELGRAsmNO + 2181082855U, // SELGRAsmNP + 2181086839U, // SELGRAsmNZ + 2181082455U, // SELGRAsmO + 2181082924U, // SELGRAsmP + 2181086900U, // SELGRAsmZ + 351781461U, // SELR + 2181084362U, // SELRAsm + 2181075732U, // SELRAsmE + 2181079572U, // SELRAsmH + 2181074317U, // SELRAsmHE + 2181081394U, // SELRAsmL + 2181075213U, // SELRAsmLE + 2181078862U, // SELRAsmLH + 2181081999U, // SELRAsmM + 2181075598U, // SELRAsmNE + 2181079317U, // SELRAsmNH + 2181074172U, // SELRAsmNHE + 2181081139U, // SELRAsmNL + 2181075068U, // SELRAsmNLE + 2181078710U, // SELRAsmNLH + 2181081919U, // SELRAsmNM + 2181082408U, // SELRAsmNO + 2181082884U, // SELRAsmNP + 2181086868U, // SELRAsmNZ + 2181082481U, // SELRAsmO + 2181082950U, // SELRAsmP + 2181086926U, // SELRAsmZ + 33600280U, // SER + 6337898U, // SFASR + 6326661U, // SFPC + 39243U, // SG + 37987U, // SGF + 33600393U, // SGFR + 39754U, // SGH + 33600520U, // SGR + 2214634862U, // SGRK + 41516U, // SH + 2214638694U, // SHHHR + 2214638835U, // SHHLR + 48401U, // SHY + 6360580U, // SIE + 6357071U, // SIGA + 2214637067U, // SIGP + 43362U, // SL + 939556969U, // SLA + 2214631169U, // SLAG + 2214634685U, // SLAK + 34149U, // SLB + 38704U, // SLBG + 33600424U, // SLBGR + 33599856U, // SLBR + 939556913U, // SLDA + 939566617U, // SLDL + 2214640373U, // SLDT + 201368499U, // SLFI + 39034U, // SLG + 37964U, // SLGF + 201368473U, // SLGFI + 33600371U, // SLGFR + 33600494U, // SLGR + 2214634835U, // SLGRK + 2214638686U, // SLHHHR + 2214638827U, // SLHHLR + 939566860U, // SLL + 2214631511U, // SLLG + 2214634762U, // SLLK + 33600795U, // SLR + 2214634881U, // SLRK + 2214640592U, // SLXT + 48449U, // SLY + 67152351U, // SORTL + 234991456U, // SP + 67155352U, // SPCTR + 6357091U, // SPKA + 6335314U, // SPM + 6372199U, // SPT + 6372503U, // SPX + 268470808U, // SQD + 268469092U, // SQDB + 67154036U, // SQDBR + 67154535U, // SQDR + 268473062U, // SQE + 268469307U, // SQEB + 67154170U, // SQEBR + 67154699U, // SQER + 67154397U, // SQXBR + 67155831U, // SQXR + 33600870U, // SR + 939557155U, // SRA + 2214631191U, // SRAG + 2214634691U, // SRAK + 939556919U, // SRDA + 939566623U, // SRDL + 2214640385U, // SRDT + 2214634899U, // SRK + 939567431U, // SRL + 2214631538U, // SRLG + 2214634768U, // SRLK + 6368071U, // SRNM + 6358412U, // SRNMB + 6372165U, // SRNMT + 2751573844U, // SRP + 67156899U, // SRST + 67157016U, // SRSTU + 2214640604U, // SRXT + 6337704U, // SSAIR + 6336520U, // SSAR + 6363819U, // SSCH + 2214628942U, // SSKE + 67145294U, // SSKEOpt + 6368178U, // SSM + 268483487U, // ST + 2214636046U, // STAM + 2214640972U, // STAMY + 6368650U, // STAP + 6369268U, // STBEAR + 268470711U, // STC + 268475064U, // STCH + 6366420U, // STCK + 6359340U, // STCKC + 6360641U, // STCKE + 6362358U, // STCKF + 436251192U, // STCM + 436248521U, // STCMH + 436256089U, // STCMY + 6371989U, // STCPS + 6372458U, // STCRW + 2214631831U, // STCTG + 2214635922U, // STCTL + 268483784U, // STCY + 268470838U, // STD + 268483795U, // STDY + 268473228U, // STE + 268483818U, // STEY + 268475158U, // STFH + 6366763U, // STFL + 6360760U, // STFLE + 6359435U, // STFPC + 268474789U, // STG + 536914145U, // STGRL + 268470692U, // STGSC + 268477083U, // STH + 268475339U, // STHH + 536914213U, // STHRL + 268483862U, // STHY + 6368697U, // STIDP + 2214636472U, // STM + 2214631605U, // STMG + 2214633451U, // STMH + 2214640998U, // STMY + 906046370U, // STNSM + 315081088U, // STOC + 3019934062U, // STOCAsm + 872450733U, // STOCAsmE + 872454806U, // STOCAsmH + 872450860U, // STOCAsmHE + 872457734U, // STOCAsmL + 872451753U, // STOCAsmLE + 872455340U, // STOCAsmLH + 872458801U, // STOCAsmM + 872452542U, // STOCAsmNE + 872456260U, // STOCAsmNH + 872451106U, // STOCAsmNHE + 872458082U, // STOCAsmNL + 872452002U, // STOCAsmNLE + 872455637U, // STOCAsmNLH + 872458935U, // STOCAsmNM + 872459418U, // STOCAsmNO + 872459900U, // STOCAsmNP + 872463884U, // STOCAsmNZ + 872459299U, // STOCAsmO + 872459684U, // STOCAsmP + 872463767U, // STOCAsmZ + 315081149U, // STOCFH + 3019938569U, // STOCFHAsm + 872450876U, // STOCFHAsmE + 872455026U, // STOCFHAsmH + 872450917U, // STOCFHAsmHE + 872457818U, // STOCFHAsmL + 872451807U, // STOCFHAsmLE + 872455395U, // STOCFHAsmLH + 872458858U, // STOCFHAsmM + 872452589U, // STOCFHAsmNE + 872456308U, // STOCFHAsmNH + 872451151U, // STOCFHAsmNHE + 872458130U, // STOCFHAsmNL + 872452047U, // STOCFHAsmNLE + 872455682U, // STOCFHAsmNLH + 872458975U, // STOCFHAsmNM + 872459458U, // STOCFHAsmNO + 872459940U, // STOCFHAsmNP + 872463924U, // STOCFHAsmNZ + 872459334U, // STOCFHAsmO + 872459820U, // STOCFHAsmP + 872463809U, // STOCFHAsmZ + 315081114U, // STOCG + 3019937663U, // STOCGAsm + 872450769U, // STOCGAsmE + 872454952U, // STOCGAsmH + 872450893U, // STOCGAsmHE + 872457784U, // STOCGAsmL + 872451783U, // STOCGAsmLE + 872455356U, // STOCGAsmLH + 872458832U, // STOCGAsmM + 872452565U, // STOCGAsmNE + 872456284U, // STOCGAsmNH + 872451124U, // STOCGAsmNHE + 872458106U, // STOCGAsmNL + 872452020U, // STOCGAsmNLE + 872455655U, // STOCGAsmNLH + 872458951U, // STOCGAsmNM + 872459434U, // STOCGAsmNO + 872459916U, // STOCGAsmNP + 872463900U, // STOCGAsmNZ + 872459313U, // STOCGAsmO + 872459779U, // STOCGAsmP + 872463788U, // STOCGAsmZ + 906046377U, // STOSM + 268480461U, // STPQ + 6372204U, // STPT + 6372508U, // STPX + 939595549U, // STRAG + 536914259U, // STRL + 268483657U, // STRV + 268474854U, // STRVG + 268477136U, // STRVH + 6363825U, // STSCH + 6366329U, // STSI + 67142028U, // STURA + 67148093U, // STURG + 268483972U, // STY + 48148U, // SU + 33601315U, // SUR + 559553U, // SVC + 48243U, // SW + 33601331U, // SWR + 33599972U, // SXBR + 33601405U, // SXR + 2214639363U, // SXTR + 2214625663U, // SXTRA + 48501U, // SY + 6372240U, // TABORT + 16921U, // TAM + 67153934U, // TAR + 67143566U, // TB + 436253205U, // TBDR + 436253222U, // TBEDR + 704719850U, // TBEGIN + 704711003U, // TBEGINC + 268468798U, // TCDB + 268469198U, // TCEB + 268470249U, // TCXB + 268483303U, // TDCDT + 268483341U, // TDCET + 268483522U, // TDCXT + 268483310U, // TDGDT + 268483348U, // TDGET + 268483529U, // TDGXT + 16773U, // TEND + 67154601U, // THDER + 67154501U, // THDR + 906046393U, // TM + 771791793U, // TMHH + 771794556U, // TMHL + 771792249U, // TMLH + 771794680U, // TMLL + 906050919U, // TMY + 6401917U, // TP + 6366244U, // TPI + 939604820U, // TPROT + 604091768U, // TR + 2214627994U, // TRACE + 2214631257U, // TRACG + 16582U, // TRAP2 + 6357029U, // TRAP4 + 67146525U, // TRE + 2214636859U, // TROO + 67153211U, // TROOOpt + 2214640475U, // TROT + 67156827U, // TROTOpt + 604093336U, // TRT + 839291782U, // TRTE + 6722438U, // TRTEOpt + 2214636927U, // TRTO + 67153279U, // TRTOOpt + 604092024U, // TRTR + 839291675U, // TRTRE + 6722331U, // TRTREOpt + 2214640565U, // TRTT + 67156917U, // TRTTOpt + 6372010U, // TS + 6363826U, // TSCH + 234988828U, // UNPK + 604078172U, // UNPKA + 604093439U, // UNPKU + 17019U, // UPT + 2214625706U, // VA + 2214625739U, // VAB + 2214627560U, // VAC + 2214627569U, // VACC + 2214625756U, // VACCB + 2214627575U, // VACCC + 2214637467U, // VACCCQ + 2214630338U, // VACCF + 2214631264U, // VACCG + 2214632049U, // VACCH + 2214637460U, // VACCQ + 2214637454U, // VACQ + 2214630327U, // VAF + 2214631211U, // VAG + 2214631983U, // VAH + 2214636944U, // VAP + 2214637449U, // VAQ + 2214631859U, // VAVG + 2214626455U, // VAVGB + 2214630516U, // VAVGF + 2214631378U, // VAVGG + 2214632271U, // VAVGH + 2214635077U, // VAVGL + 2214626586U, // VAVGLB + 2214630673U, // VAVGLF + 2214631488U, // VAVGLG + 2214632651U, // VAVGLH + 2214636382U, // VBPERM + 2214631302U, // VCDG + 2214626418U, // VCDGB + 2214631481U, // VCDLG + 2214626439U, // VCDLGB + 2214626388U, // VCEFB + 2214626402U, // VCELFB + 2214637475U, // VCEQ + 2214626769U, // VCEQB + 2214639709U, // VCEQBS + 2214630903U, // VCEQF + 2214639992U, // VCEQFS + 2214631679U, // VCEQG + 2214640084U, // VCEQGS + 2214633909U, // VCEQH + 2214640158U, // VCEQHS + 2214626293U, // VCFEB + 2214636493U, // VCFN + 2214635659U, // VCFPL + 2214640284U, // VCFPS + 2214627815U, // VCGD + 2214625956U, // VCGDB + 2214632126U, // VCH + 2214626476U, // VCHB + 2214639694U, // VCHBS + 2214630537U, // VCHF + 2214639977U, // VCHFS + 2214631400U, // VCHG + 2214640069U, // VCHGS + 2214632292U, // VCHH + 2214640143U, // VCHHS + 2214635084U, // VCHL + 2214626594U, // VCHLB + 2214639701U, // VCHLBS + 2214630681U, // VCHLF + 2214639984U, // VCHLFS + 2214631496U, // VCHLG + 2214640076U, // VCHLGS + 2214632659U, // VCHLH + 2214640150U, // VCHLHS + 2214636443U, // VCKSM + 2214626307U, // VCLFEB + 2214633548U, // VCLFNH + 2214635370U, // VCLFNL + 2214637038U, // VCLFP + 2214627821U, // VCLGD + 2214625970U, // VCLGDB + 2214641146U, // VCLZ + 67143873U, // VCLZB + 2214637008U, // VCLZDP + 67147470U, // VCLZF + 67148289U, // VCLZG + 67150629U, // VCLZH + 2214630825U, // VCNF + 2214636972U, // VCP + 2214630837U, // VCRNF + 2214637045U, // VCSFP + 2214633896U, // VCSPH + 2214641365U, // VCTZ + 67143889U, // VCTZB + 67147496U, // VCTZF + 67148306U, // VCTZG + 67150655U, // VCTZH + 2214627227U, // VCVB + 2214631250U, // VCVBG + 2214631250U, // VCVBGOpt + 2214627227U, // VCVBOpt + 2214627899U, // VCVD + 2214631314U, // VCVDG + 2214637003U, // VDP + 2214627590U, // VEC + 67142115U, // VECB + 67146697U, // VECF + 67147623U, // VECG + 67148408U, // VECH + 2214634996U, // VECL + 67142931U, // VECLB + 67147018U, // VECLF + 67147826U, // VECLG + 67148958U, // VECLH + 2181081746U, // VERIM + 2181072260U, // VERIMB + 2181076380U, // VERIMF + 2181077160U, // VERIMG + 2181079005U, // VERIMH + 2214635269U, // VERLL + 2214626609U, // VERLLB + 2214630727U, // VERLLF + 2214631503U, // VERLLG + 2214632817U, // VERLLH + 2214640685U, // VERLLV + 2214627240U, // VERLLVB + 2214631044U, // VERLLVF + 2214631872U, // VERLLVG + 2214634160U, // VERLLVH + 2214635878U, // VESL + 2214626659U, // VESLB + 2214630770U, // VESLF + 2214631544U, // VESLG + 2214633317U, // VESLH + 2214640701U, // VESLV + 2214627258U, // VESLVB + 2214631062U, // VESLVF + 2214631890U, // VESLVG + 2214634178U, // VESLVH + 2214625569U, // VESRA + 2214625724U, // VESRAB + 2214630319U, // VESRAF + 2214631189U, // VESRAG + 2214631975U, // VESRAH + 2214640671U, // VESRAV + 2214627218U, // VESRAVB + 2214631028U, // VESRAVF + 2214631850U, // VESRAVG + 2214634144U, // VESRAVH + 2214635845U, // VESRL + 2214626644U, // VESRLB + 2214630762U, // VESRLF + 2214631536U, // VESRLG + 2214633309U, // VESRLH + 2214640693U, // VESRLV + 2214627249U, // VESRLVB + 2214631053U, // VESRLVF + 2214631881U, // VESRLVG + 2214634169U, // VESRLVH + 2214625354U, // VFA + 2214625783U, // VFADB + 2214627915U, // VFAE + 2214626240U, // VFAEB + 2214639669U, // VFAEBS + 2214630365U, // VFAEF + 2214639952U, // VFAEFS + 2214632131U, // VFAEH + 2214640118U, // VFAEHS + 2214627488U, // VFAEZB + 2214639904U, // VFAEZBS + 2214631085U, // VFAEZF + 2214640041U, // VFAEZFS + 2214634236U, // VFAEZH + 2214640202U, // VFAEZHS + 2214626808U, // VFASB + 2214628001U, // VFCE + 2214625874U, // VFCEDB + 2214639557U, // VFCEDBS + 2214626893U, // VFCESB + 2214639726U, // VFCESBS + 2214632062U, // VFCH + 2214625986U, // VFCHDB + 2214639633U, // VFCHDBS + 2214628126U, // VFCHE + 2214625890U, // VFCHEDB + 2214639575U, // VFCHEDBS + 2214626909U, // VFCHESB + 2214639744U, // VFCHESBS + 2214626961U, // VFCHSB + 2214639802U, // VFCHSBS + 2214627810U, // VFD + 2214625860U, // VFDDB + 2214626879U, // VFDSB + 2214628031U, // VFEE + 2214626280U, // VFEEB + 2214639677U, // VFEEBS + 2214630386U, // VFEEF + 2214639960U, // VFEEFS + 2214632145U, // VFEEH + 2214640126U, // VFEEHS + 2214627496U, // VFEEZB + 2214639913U, // VFEEZBS + 2214631093U, // VFEEZF + 2214640050U, // VFEEZFS + 2214634244U, // VFEEZH + 2214640211U, // VFEEZHS + 2214629830U, // VFENE + 2214626355U, // VFENEB + 2214639685U, // VFENEBS + 2214630426U, // VFENEF + 2214639968U, // VFENEFS + 2214632179U, // VFENEH + 2214640134U, // VFENEHS + 2214627512U, // VFENEZB + 2214639922U, // VFENEZBS + 2214631109U, // VFENEZF + 2214640059U, // VFENEZFS + 2214634260U, // VFENEZH + 2214640220U, // VFENEZHS + 2214634431U, // VFI + 2214626036U, // VFIDB + 2214627011U, // VFISB + 2214625926U, // VFKEDB + 2214639615U, // VFKEDBS + 2214626945U, // VFKESB + 2214639784U, // VFKESBS + 2214626002U, // VFKHDB + 2214639651U, // VFKHDBS + 2214625908U, // VFKHEDB + 2214639595U, // VFKHEDBS + 2214626927U, // VFKHESB + 2214639764U, // VFKHESBS + 2214626977U, // VFKHSB + 2214639820U, // VFKHSBS + 67142190U, // VFLCDB + 67143215U, // VFLCSB + 2214635225U, // VFLL + 67156595U, // VFLLS + 67142448U, // VFLNDB + 67143416U, // VFLNSB + 67142482U, // VFLPDB + 67143450U, // VFLPSB + 2214638800U, // VFLR + 2214627869U, // VFLRD + 2214636100U, // VFM + 2214625397U, // VFMA + 2214625797U, // VFMADB + 2214626822U, // VFMASB + 2214640770U, // VFMAX + 2214626210U, // VFMAXDB + 2214627191U, // VFMAXSB + 2214626064U, // VFMDB + 2214636536U, // VFMIN + 2214626078U, // VFMINDB + 2214627046U, // VFMINSB + 2214640257U, // VFMS + 2214627032U, // VFMSB + 2214626176U, // VFMSDB + 2214627152U, // VFMSSB + 2214625408U, // VFNMA + 2214625813U, // VFNMADB + 2214626838U, // VFNMASB + 2214640263U, // VFNMS + 2214626192U, // VFNMSDB + 2214627168U, // VFNMSSB + 2214636920U, // VFPSO + 2214626112U, // VFPSODB + 2214627080U, // VFPSOSB + 2214640026U, // VFS + 2214626162U, // VFSDB + 2214637538U, // VFSQ + 67142498U, // VFSQDB + 67143466U, // VFSQSB + 2214627138U, // VFSSB + 2214634344U, // VFTCI + 2214626018U, // VFTCIDB + 2214626993U, // VFTCISB + 771795476U, // VGBM + 3221263353U, // VGEF + 1073780640U, // VGEG + 2214636094U, // VGFM + 2214625390U, // VGFMA + 2214625716U, // VGFMAB + 2214630311U, // VGFMAF + 2214631175U, // VGFMAG + 2214631961U, // VGFMAH + 2214626679U, // VGFMB + 2214630793U, // VGFMF + 2214631579U, // VGFMG + 2214633424U, // VGFMH + 2952833629U, // VGM + 2952824190U, // VGMB + 2952828310U, // VGMF + 2952829090U, // VGMG + 2952830935U, // VGMH + 2214639237U, // VISTR + 2214626800U, // VISTRB + 67156069U, // VISTRBS + 2214630965U, // VISTRF + 67156352U, // VISTRFS + 2214634017U, // VISTRH + 67156518U, // VISTRHS + 268478956U, // VL + 2415962604U, // VLAlign + 2415952342U, // VLBB + 2415964534U, // VLBR + 268473879U, // VLBRF + 268474655U, // VLBRG + 268476877U, // VLBRH + 268480467U, // VLBRQ + 2415963615U, // VLBRREP + 268473824U, // VLBRREPF + 268474588U, // VLBRREPG + 268476817U, // VLBRREPH + 2214627665U, // VLC + 67142121U, // VLCB + 67146703U, // VLCF + 67147635U, // VLCG + 67148426U, // VLCH + 2214628020U, // VLDE + 67142612U, // VLDEB + 2147517479U, // VLEB + 2147522054U, // VLEBRF + 2147522830U, // VLEBRG + 2147525052U, // VLEBRH + 2214627799U, // VLED + 2214625942U, // VLEDB + 2147521550U, // VLEF + 2147522470U, // VLEG + 2147523303U, // VLEH + 2281735402U, // VLEIB + 2281739495U, // VLEIF + 2281740298U, // VLEIG + 2281741283U, // VLEIH + 2415964910U, // VLER + 268473894U, // VLERF + 268474670U, // VLERG + 268476899U, // VLERH + 2214640679U, // VLGV + 2214627233U, // VLGVB + 2214631037U, // VLGVF + 2214631865U, // VLGVG + 2214634153U, // VLGVH + 2919280220U, // VLIP + 2214635281U, // VLL + 2415967900U, // VLLEBRZ + 268473245U, // VLLEBRZE + 268474069U, // VLLEBRZF + 268474888U, // VLLEBRZG + 268477228U, // VLLEBRZH + 2415967646U, // VLLEZ + 268470448U, // VLLEZB + 268474045U, // VLLEZF + 268474873U, // VLLEZG + 268477196U, // VLLEZH + 268473728U, // VLLEZLF + 2214636198U, // VLM + 2214636198U, // VLMAlign + 2214637158U, // VLP + 67143115U, // VLPB + 67147249U, // VLPF + 67148013U, // VLPG + 67150242U, // VLPH + 67155232U, // VLR + 2415963608U, // VLREP + 268469692U, // VLREPB + 268473816U, // VLREPF + 268474580U, // VLREPG + 268476809U, // VLREPH + 3019942201U, // VLRL + 2214638860U, // VLRLR + 2181077466U, // VLVG + 2181072030U, // VLVGB + 2181076091U, // VLVGF + 2181076953U, // VLVGG + 2181077846U, // VLVGH + 2214637078U, // VLVGP + 2214627926U, // VMAE + 2214626247U, // VMAEB + 2214630372U, // VMAEF + 2214632138U, // VMAEH + 2214631969U, // VMAH + 2214626469U, // VMAHB + 2214630530U, // VMAHF + 2214632285U, // VMAHH + 2214634934U, // VMAL + 2214626572U, // VMALB + 2214628948U, // VMALE + 2214626328U, // VMALEB + 2214630399U, // VMALEF + 2214632152U, // VMALEH + 2214630659U, // VMALF + 2214632535U, // VMALH + 2214626482U, // VMALHB + 2214630574U, // VMALHF + 2214632340U, // VMALHH + 2214640723U, // VMALHW + 2214636658U, // VMALO + 2214626727U, // VMALOB + 2214630851U, // VMALOF + 2214633844U, // VMALOH + 2214636563U, // VMAO + 2214626720U, // VMAOB + 2214630844U, // VMAOF + 2214633837U, // VMAOH + 2214629746U, // VME + 2214626349U, // VMEB + 2214630420U, // VMEF + 2214632173U, // VMEH + 2214633464U, // VMH + 2214626505U, // VMHB + 2214630603U, // VMHF + 2214632375U, // VMHH + 2214635286U, // VML + 2214626617U, // VMLB + 2214629196U, // VMLE + 2214626336U, // VMLEB + 2214630407U, // VMLEF + 2214632160U, // VMLEH + 2214630735U, // VMLF + 2214632831U, // VMLH + 2214626490U, // VMLHB + 2214630588U, // VMLHF + 2214632354U, // VMLHH + 2214640731U, // VMLHW + 2214636665U, // VMLO + 2214626735U, // VMLOB + 2214630859U, // VMLOF + 2214633852U, // VMLOH + 2214636543U, // VMN + 2214626714U, // VMNB + 2214630831U, // VMNF + 2214631624U, // VMNG + 2214633697U, // VMNH + 2214635519U, // VMNL + 2214626623U, // VMNLB + 2214630741U, // VMNLF + 2214631522U, // VMNLG + 2214633084U, // VMNLH + 2214636681U, // VMO + 2214626742U, // VMOB + 2214630866U, // VMOF + 2214633859U, // VMOH + 2214637163U, // VMP + 2214634011U, // VMRH + 2214626518U, // VMRHB + 2214630616U, // VMRHF + 2214631406U, // VMRHG + 2214632388U, // VMRHH + 2214635839U, // VMRL + 2214626637U, // VMRLB + 2214630755U, // VMRLF + 2214631529U, // VMRLG + 2214633302U, // VMRLH + 2214635884U, // VMSL + 2214631551U, // VMSLG + 2214637425U, // VMSP + 2214640781U, // VMX + 2214627398U, // VMXB + 2214631070U, // VMXF + 2214631923U, // VMXG + 2214634204U, // VMXH + 2214636016U, // VMXL + 2214626672U, // VMXLB + 2214630777U, // VMXLF + 2214631565U, // VMXLG + 2214633404U, // VMXLH + 2214636554U, // VN + 2214627684U, // VNC + 2214636548U, // VNN + 2214636854U, // VNO + 2214640786U, // VNX + 2214636934U, // VO + 2214627700U, // VOC + 6328922U, // VONE + 2214634351U, // VPDI + 2214636390U, // VPERM + 2214634786U, // VPK + 2214630653U, // VPKF + 2214631453U, // VPKG + 2214632529U, // VPKH + 2214640236U, // VPKLS + 2214630986U, // VPKLSF + 2214640017U, // VPKLSFS + 2214631785U, // VPKLSG + 2214640100U, // VPKLSGS + 2214634032U, // VPKLSH + 2214640183U, // VPKLSHS + 2214640230U, // VPKS + 2214630979U, // VPKSF + 2214640009U, // VPKSFS + 2214631778U, // VPKSG + 2214640092U, // VPKSGS + 2214634025U, // VPKSH + 2214640175U, // VPKSHS + 3019947508U, // VPKZ + 2214639518U, // VPKZR + 2214640345U, // VPOPCT + 67143561U, // VPOPCTB + 67147359U, // VPOPCTF + 67148167U, // VPOPCTG + 67150405U, // VPOPCTH + 2214637324U, // VPSOP + 2214637032U, // VREP + 2214626756U, // VREPB + 2214630890U, // VREPF + 2214631654U, // VREPG + 2214633883U, // VREPH + 2717951005U, // VREPI + 570459396U, // VREPIB + 570463470U, // VREPIF + 570464273U, // VREPIG + 570465290U, // VREPIH + 2214637401U, // VRP + 2214640302U, // VS + 2214627186U, // VSB + 2214634316U, // VSBCBI + 2214637481U, // VSBCBIQ + 2214634331U, // VSBI + 2214637498U, // VSBIQ + 2214634324U, // VSCBI + 2214626525U, // VSCBIB + 2214630623U, // VSCBIF + 2214631426U, // VSCBIG + 2214632406U, // VSCBIH + 2214637490U, // VSCBIQ + 1107334123U, // VSCEF + 3254818713U, // VSCEG + 2214636977U, // VSCHDP + 2214637085U, // VSCHP + 2214637417U, // VSCHSP + 2214637441U, // VSCHXP + 2214637109U, // VSCSHP + 2214636997U, // VSDP + 2214631353U, // VSEG + 67142784U, // VSEGB + 67146803U, // VSEGF + 67148592U, // VSEGH + 2214635045U, // VSEL + 2214631002U, // VSF + 2214631798U, // VSG + 2214634048U, // VSH + 2214635890U, // VSL + 2214626666U, // VSLB + 2214627835U, // VSLD + 2214626057U, // VSLDB + 2214637431U, // VSP + 2214637544U, // VSQ + 2214625576U, // VSRA + 2214625732U, // VSRAB + 2214627883U, // VSRD + 2214635852U, // VSRL + 2214626652U, // VSRLB + 2214637395U, // VSRP + 2214638941U, // VSRPR + 268483504U, // VST + 2415967152U, // VSTAlign + 2415964540U, // VSTBR + 268473886U, // VSTBRF + 268474662U, // VSTBRG + 268476884U, // VSTBRH + 268480474U, // VSTBRQ + 2415952967U, // VSTEB + 2415957518U, // VSTEBRF + 2415958294U, // VSTEBRG + 2415960516U, // VSTEBRH + 2415957026U, // VSTEF + 2415957951U, // VSTEG + 2415958779U, // VSTEH + 2415964963U, // VSTER + 268473901U, // VSTERF + 268474677U, // VSTERG + 268476906U, // VSTERH + 2214636006U, // VSTL + 2214636471U, // VSTM + 2214636471U, // VSTMAlign + 2214627735U, // VSTRC + 2214625775U, // VSTRCB + 2214639548U, // VSTRCBS + 2214630357U, // VSTRCF + 2214639943U, // VSTRCFS + 2214632093U, // VSTRCH + 2214640109U, // VSTRCHS + 2214627479U, // VSTRCZB + 2214639894U, // VSTRCZBS + 2214631076U, // VSTRCZF + 2214640031U, // VSTRCZFS + 2214634227U, // VSTRCZH + 2214640192U, // VSTRCZHS + 3019942226U, // VSTRL + 2214638867U, // VSTRLR + 2214640291U, // VSTRS + 2214627130U, // VSTRSB + 2214630994U, // VSTRSF + 2214634040U, // VSTRSH + 2214627528U, // VSTRSZB + 2214631135U, // VSTRSZF + 2214634294U, // VSTRSZH + 2214636482U, // VSUM + 2214626707U, // VSUMB + 2214631611U, // VSUMG + 2214630482U, // VSUMGF + 2214632258U, // VSUMGH + 2214633457U, // VSUMH + 2214637505U, // VSUMQ + 2214630910U, // VSUMQF + 2214631686U, // VSUMQG + 67152829U, // VTM + 6336380U, // VTP + 2214633903U, // VUPH + 67142863U, // VUPHB + 67146961U, // VUPHF + 67148733U, // VUPHH + 3019947501U, // VUPKZ + 2214634269U, // VUPKZH + 2214636033U, // VUPKZL + 2214635666U, // VUPL + 67142982U, // VUPLB + 67147100U, // VUPLF + 2214633241U, // VUPLH + 67142849U, // VUPLHB + 67146947U, // VUPLHF + 67148713U, // VUPLHH + 67157090U, // VUPLHW + 2214635262U, // VUPLL + 67142953U, // VUPLLB + 67147071U, // VUPLLF + 67149161U, // VUPLLH + 2214640809U, // VX + 6335816U, // VZERO + 2214626425U, // WCDGB + 2214626447U, // WCDLGB + 2214626395U, // WCEFB + 2214626410U, // WCELFB + 2214626300U, // WCFEB + 2214625963U, // WCGDB + 2214626315U, // WCLFEB + 2214625978U, // WCLGDB + 2214625790U, // WFADB + 2214626815U, // WFASB + 2214627266U, // WFAXB + 2214627600U, // WFC + 67142183U, // WFCDB + 2214625882U, // WFCEDB + 2214639566U, // WFCEDBS + 2214626901U, // WFCESB + 2214639735U, // WFCESBS + 2214627318U, // WFCEXB + 2214639838U, // WFCEXBS + 2214625994U, // WFCHDB + 2214639642U, // WFCHDBS + 2214625899U, // WFCHEDB + 2214639585U, // WFCHEDBS + 2214626918U, // WFCHESB + 2214639754U, // WFCHESBS + 2214627326U, // WFCHEXB + 2214639847U, // WFCHEXBS + 2214626969U, // WFCHSB + 2214639811U, // WFCHSBS + 2214627352U, // WFCHXB + 2214639876U, // WFCHXBS + 67143208U, // WFCSB + 67143642U, // WFCXB + 2214625867U, // WFDDB + 2214626886U, // WFDSB + 2214627311U, // WFDXB + 2214626043U, // WFIDB + 2214627018U, // WFISB + 2214627377U, // WFIXB + 2214634727U, // WFK + 67142402U, // WFKDB + 2214625934U, // WFKEDB + 2214639624U, // WFKEDBS + 2214626953U, // WFKESB + 2214639793U, // WFKESBS + 2214627344U, // WFKEXB + 2214639867U, // WFKEXBS + 2214626010U, // WFKHDB + 2214639660U, // WFKHDBS + 2214625917U, // WFKHEDB + 2214639605U, // WFKHEDBS + 2214626936U, // WFKHESB + 2214639774U, // WFKHESBS + 2214627335U, // WFKHEXB + 2214639857U, // WFKHEXBS + 2214626985U, // WFKHSB + 2214639829U, // WFKHSBS + 2214627360U, // WFKHXB + 2214639885U, // WFKHXBS + 67143377U, // WFKSB + 67143736U, // WFKXB + 67142198U, // WFLCDB + 67143223U, // WFLCSB + 67143649U, // WFLCXB + 67144180U, // WFLLD + 67156602U, // WFLLS + 67142456U, // WFLNDB + 67143424U, // WFLNSB + 67143765U, // WFLNXB + 67142490U, // WFLPDB + 67143458U, // WFLPSB + 67143782U, // WFLPXB + 2214627876U, // WFLRD + 2214640802U, // WFLRX + 2214625805U, // WFMADB + 2214626830U, // WFMASB + 2214627273U, // WFMAXB + 2214626219U, // WFMAXDB + 2214627200U, // WFMAXSB + 2214627470U, // WFMAXXB + 2214626071U, // WFMDB + 2214626087U, // WFMINDB + 2214627055U, // WFMINSB + 2214627404U, // WFMINXB + 2214627039U, // WFMSB + 2214626184U, // WFMSDB + 2214627160U, // WFMSSB + 2214627453U, // WFMSXB + 2214627391U, // WFMXB + 2214625822U, // WFNMADB + 2214626847U, // WFNMASB + 2214627281U, // WFNMAXB + 2214626201U, // WFNMSDB + 2214627177U, // WFNMSSB + 2214627461U, // WFNMSXB + 2214626121U, // WFPSODB + 2214627089U, // WFPSOSB + 2214627421U, // WFPSOXB + 2214626169U, // WFSDB + 67142506U, // WFSQDB + 67143474U, // WFSQSB + 67143790U, // WFSQXB + 2214627145U, // WFSSB + 2214627446U, // WFSXB + 2214626027U, // WFTCIDB + 2214627002U, // WFTCISB + 2214627368U, // WFTCIXB + 67142619U, // WLDEB + 2214625949U, // WLEDB + 48255U, // X + 604080582U, // XC + 39407U, // XG + 33600552U, // XGR + 2214634869U, // XGRK + 906044553U, // XI + 201364648U, // XIHF + 201364793U, // XILF + 906050866U, // XIY + 33601337U, // XR + 2214634905U, // XRK + 16818U, // XSCH + 48521U, // XY + 234990997U, // ZAP }; static const uint16_t OpInfo1[] = { 0U, // PHI 0U, // INLINEASM + 0U, // INLINEASM_BR 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL @@ -5041,16 +5507,23 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 0U, // DBG_VALUE + 0U, // DBG_VALUE_LIST + 0U, // DBG_INSTR_REF + 0U, // DBG_PHI 0U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 0U, // BUNDLE 0U, // LIFETIME_START 0U, // LIFETIME_END + 0U, // PSEUDO_PROBE + 0U, // ARITH_FENCE 0U, // STACKMAP 0U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP @@ -5062,6 +5535,11 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // PATCHABLE_EVENT_CALL 0U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL + 0U, // MEMBARRIER + 0U, // JUMP_TABLE_DEBUG_INFO + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ASSERT_ALIGN 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL @@ -5069,6 +5547,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR @@ -5076,17 +5556,33 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE + 0U, // G_CONSTANT_POOL 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_CONSTANT_FOLD_BARRIER + 0U, // G_INTRINSIC_FPTRUNC_ROUND + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD 0U, // G_STORE + 0U, // G_INDEXED_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG @@ -5100,10 +5596,21 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_ATOMICRMW_FMAX + 0U, // G_ATOMICRMW_FMIN + 0U, // G_ATOMICRMW_UINC_WRAP + 0U, // G_ATOMICRMW_UDEC_WRAP + 0U, // G_FENCE + 0U, // G_PREFETCH 0U, // G_BRCOND 0U, // G_BRINDIRECT + 0U, // G_INVOKE_REGION_START 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_INTRINSIC_CONVERGENT + 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT @@ -5111,32 +5618,61 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT + 0U, // G_SEXT_INREG 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT + 0U, // G_UADDO 0U, // G_UADDE + 0U, // G_USUBO 0U, // G_USUBE 0U, // G_SADDO + 0U, // G_SADDE 0U, // G_SSUBO + 0U, // G_SSUBE 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA + 0U, // G_FMAD 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW + 0U, // G_FPOWI 0U, // G_FEXP 0U, // G_FEXP2 + 0U, // G_FEXP10 0U, // G_FLOG 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FLDEXP + 0U, // G_FFREXP 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC @@ -5145,21 +5681,103 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS - 0U, // G_GEP - 0U, // G_PTR_MASK + 0U, // G_FCOPYSIGN + 0U, // G_IS_FPCLASS + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_GET_FPENV + 0U, // G_SET_FPENV + 0U, // G_RESET_FPENV + 0U, // G_GET_FPMODE + 0U, // G_SET_FPMODE + 0U, // G_RESET_FPMODE + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND 0U, // G_BR + 0U, // G_BRJT 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STACKSAVE + 0U, // G_STACKRESTORE + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_STRICT_FLDEXP + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_FMAXIMUM + 0U, // G_VECREDUCE_FMINIMUM + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ADA_ENTRY + 0U, // ADA_ENTRY_VALUE + 0U, // ADB_MemFoldPseudo 0U, // ADJCALLSTACKDOWN 0U, // ADJCALLSTACKUP 0U, // ADJDYNALLOC + 0U, // AEB_MemFoldPseudo 0U, // AEXT128 0U, // AFIMux + 0U, // AG_MemFoldPseudo 0U, // AHIMux 0U, // AHIMuxK + 0U, // ALG_MemFoldPseudo + 0U, // AL_MemFoldPseudo 0U, // ATOMIC_CMP_SWAPW 0U, // ATOMIC_LOADW_AFI 0U, // ATOMIC_LOADW_AR @@ -5176,63 +5794,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // ATOMIC_LOADW_UMIN 0U, // ATOMIC_LOADW_XILF 0U, // ATOMIC_LOADW_XR - 0U, // ATOMIC_LOAD_AFI - 0U, // ATOMIC_LOAD_AGFI - 0U, // ATOMIC_LOAD_AGHI - 0U, // ATOMIC_LOAD_AGR - 0U, // ATOMIC_LOAD_AHI - 0U, // ATOMIC_LOAD_AR - 0U, // ATOMIC_LOAD_MAX_32 - 0U, // ATOMIC_LOAD_MAX_64 - 0U, // ATOMIC_LOAD_MIN_32 - 0U, // ATOMIC_LOAD_MIN_64 - 0U, // ATOMIC_LOAD_NGR - 0U, // ATOMIC_LOAD_NGRi - 0U, // ATOMIC_LOAD_NIHF64 - 0U, // ATOMIC_LOAD_NIHF64i - 0U, // ATOMIC_LOAD_NIHH64 - 0U, // ATOMIC_LOAD_NIHH64i - 0U, // ATOMIC_LOAD_NIHL64 - 0U, // ATOMIC_LOAD_NIHL64i - 0U, // ATOMIC_LOAD_NILF - 0U, // ATOMIC_LOAD_NILF64 - 0U, // ATOMIC_LOAD_NILF64i - 0U, // ATOMIC_LOAD_NILFi - 0U, // ATOMIC_LOAD_NILH - 0U, // ATOMIC_LOAD_NILH64 - 0U, // ATOMIC_LOAD_NILH64i - 0U, // ATOMIC_LOAD_NILHi - 0U, // ATOMIC_LOAD_NILL - 0U, // ATOMIC_LOAD_NILL64 - 0U, // ATOMIC_LOAD_NILL64i - 0U, // ATOMIC_LOAD_NILLi - 0U, // ATOMIC_LOAD_NR - 0U, // ATOMIC_LOAD_NRi - 0U, // ATOMIC_LOAD_OGR - 0U, // ATOMIC_LOAD_OIHF64 - 0U, // ATOMIC_LOAD_OIHH64 - 0U, // ATOMIC_LOAD_OIHL64 - 0U, // ATOMIC_LOAD_OILF - 0U, // ATOMIC_LOAD_OILF64 - 0U, // ATOMIC_LOAD_OILH - 0U, // ATOMIC_LOAD_OILH64 - 0U, // ATOMIC_LOAD_OILL - 0U, // ATOMIC_LOAD_OILL64 - 0U, // ATOMIC_LOAD_OR - 0U, // ATOMIC_LOAD_SGR - 0U, // ATOMIC_LOAD_SR - 0U, // ATOMIC_LOAD_UMAX_32 - 0U, // ATOMIC_LOAD_UMAX_64 - 0U, // ATOMIC_LOAD_UMIN_32 - 0U, // ATOMIC_LOAD_UMIN_64 - 0U, // ATOMIC_LOAD_XGR - 0U, // ATOMIC_LOAD_XIHF64 - 0U, // ATOMIC_LOAD_XILF - 0U, // ATOMIC_LOAD_XILF64 - 0U, // ATOMIC_LOAD_XR 0U, // ATOMIC_SWAPW - 0U, // ATOMIC_SWAP_32 - 0U, // ATOMIC_SWAP_64 + 0U, // A_MemFoldPseudo 0U, // CFIMux 0U, // CGIBCall 0U, // CGIBReturn @@ -5241,8 +5804,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CHIMux 0U, // CIBCall 0U, // CIBReturn - 0U, // CLCLoop - 0U, // CLCSequence + 0U, // CLCImm + 0U, // CLCReg 0U, // CLFIMux 0U, // CLGIBCall 0U, // CLGIBReturn @@ -5258,12 +5821,16 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CRBCall 0U, // CRBReturn 0U, // CallBASR + 0U, // CallBASR_STACKEXT + 0U, // CallBASR_XPLINK64 0U, // CallBCR 0U, // CallBR 0U, // CallBRASL + 0U, // CallBRASL_XPLINK64 0U, // CallBRCL 0U, // CallJG 0U, // CondReturn + 0U, // CondReturn_XPLINK 0U, // CondStore16 0U, // CondStore16Inv 0U, // CondStore16Mux @@ -5283,6 +5850,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CondStoreF64 0U, // CondStoreF64Inv 0U, // CondTrap + 0U, // DDB_MemFoldPseudo + 0U, // DEB_MemFoldPseudo + 0U, // EXRL_Pseudo 0U, // GOT 0U, // IIFMux 0U, // IIHF64 @@ -5304,20 +5874,33 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LLHMux 0U, // LLHRMux 0U, // LMux + 0U, // LOCG_MemFoldPseudo 0U, // LOCHIMux 0U, // LOCMux + 0U, // LOCMux_MemFoldPseudo 0U, // LOCRMux - 0U, // LRMux - 0U, // LTDBRCompare_VecPseudo - 0U, // LTEBRCompare_VecPseudo - 0U, // LTXBRCompare_VecPseudo + 0U, // LTDBRCompare_Pseudo + 0U, // LTEBRCompare_Pseudo + 0U, // LTXBRCompare_Pseudo 0U, // LX - 0U, // MVCLoop - 0U, // MVCSequence + 0U, // MADB_MemFoldPseudo + 0U, // MAEB_MemFoldPseudo + 0U, // MDB_MemFoldPseudo + 0U, // MEEB_MemFoldPseudo + 0U, // MSC_MemFoldPseudo + 0U, // MSDB_MemFoldPseudo + 0U, // MSEB_MemFoldPseudo + 0U, // MSGC_MemFoldPseudo + 0U, // MVCImm + 0U, // MVCReg 0U, // MVSTLoop - 0U, // MemBarrier - 0U, // NCLoop - 0U, // NCSequence + 0U, // MemsetImmImm + 0U, // MemsetImmReg + 0U, // MemsetRegImm + 0U, // MemsetRegReg + 0U, // NCImm + 0U, // NCReg + 0U, // NG_MemFoldPseudo 0U, // NIFMux 0U, // NIHF64 0U, // NIHH64 @@ -5327,8 +5910,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // NILH64 0U, // NILL64 0U, // NILMux - 0U, // OCLoop - 0U, // OCSequence + 0U, // N_MemFoldPseudo + 0U, // OCImm + 0U, // OCReg + 0U, // OG_MemFoldPseudo 0U, // OIFMux 0U, // OIHF64 0U, // OIHH64 @@ -5338,13 +5923,24 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // OILH64 0U, // OILL64 0U, // OILMux + 0U, // O_MemFoldPseudo 0U, // PAIR128 + 0U, // PROBED_ALLOCA + 0U, // PROBED_STACKALLOC 0U, // RISBHH 0U, // RISBHL 0U, // RISBLH 0U, // RISBLL 0U, // RISBMux 0U, // Return + 0U, // Return_XPLINK + 0U, // SCmp128Hi + 0U, // SDB_MemFoldPseudo + 0U, // SEB_MemFoldPseudo + 0U, // SELRMux + 0U, // SG_MemFoldPseudo + 0U, // SLG_MemFoldPseudo + 0U, // SL_MemFoldPseudo 0U, // SRSTLoop 0U, // ST128 0U, // STCMux @@ -5352,6 +5948,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // STMux 0U, // STOCMux 0U, // STX + 0U, // S_MemFoldPseudo + 0U, // Select128 0U, // Select32 0U, // Select64 0U, // SelectF128 @@ -5371,6 +5969,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // TMLL64 0U, // TMLMux 0U, // Trap + 0U, // UCmp128Hi 0U, // VL32 0U, // VL64 0U, // VLR32 @@ -5378,11 +5977,14 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VLVGP32 0U, // VST32 0U, // VST64 - 0U, // XCLoop - 0U, // XCSequence + 0U, // XCImm + 0U, // XCReg + 0U, // XG_MemFoldPseudo 0U, // XIFMux 0U, // XIHF64 0U, // XILF64 + 0U, // XPLINK_STACKALLOC + 0U, // X_MemFoldPseudo 0U, // ZEXT128 0U, // A 0U, // AD @@ -5390,7 +5992,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // ADBR 0U, // ADR 0U, // ADTR - 512U, // ADTRA + 1024U, // ADTRA 0U, // AE 0U, // AEB 0U, // AEBR @@ -5402,7 +6004,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // AGFR 0U, // AGH 0U, // AGHI - 8U, // AGHIK + 16U, // AGHIK 0U, // AGR 0U, // AGRK 0U, // AGSI @@ -5410,7 +6012,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // AHHHR 0U, // AHHLR 0U, // AHI - 8U, // AHIK + 16U, // AHIK 0U, // AHY 0U, // AIH 0U, // AL @@ -5423,13 +6025,13 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // ALGF 0U, // ALGFI 0U, // ALGFR - 8U, // ALGHSIK + 16U, // ALGHSIK 0U, // ALGR 0U, // ALGRK 0U, // ALGSI 0U, // ALHHHR 0U, // ALHHLR - 8U, // ALHSIK + 16U, // ALHSIK 0U, // ALR 0U, // ALRK 0U, // ALSI @@ -5447,7 +6049,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // AXBR 0U, // AXR 0U, // AXTR - 512U, // AXTRA + 1024U, // AXTRA 0U, // AY 0U, // B 0U, // BAKR @@ -5507,8 +6109,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // BIAsmZ 0U, // BIC 0U, // BICAsm - 0U, // BPP - 0U, // BPRP + 33U, // BPP + 1U, // BPRP 0U, // BR 0U, // BRAS 0U, // BRASL @@ -5539,40 +6141,40 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // BRCT 0U, // BRCTG 0U, // BRCTH - 16U, // BRXH - 16U, // BRXHG - 16U, // BRXLE - 16U, // BRXLG + 48U, // BRXH + 48U, // BRXHG + 48U, // BRXLE + 48U, // BRXLG 0U, // BSA 0U, // BSG 0U, // BSM - 24U, // BXH - 24U, // BXHG - 24U, // BXLE - 24U, // BXLEG + 64U, // BXH + 64U, // BXHG + 64U, // BXLE + 64U, // BXLEG 0U, // C 0U, // CD 0U, // CDB 0U, // CDBR 0U, // CDFBR - 33U, // CDFBRA + 82U, // CDFBRA 0U, // CDFR - 33U, // CDFTR + 82U, // CDFTR 0U, // CDGBR - 33U, // CDGBRA + 82U, // CDGBRA 0U, // CDGR 0U, // CDGTR - 33U, // CDGTRA - 33U, // CDLFBR - 33U, // CDLFTR - 33U, // CDLGBR - 33U, // CDLGTR + 82U, // CDGTRA + 82U, // CDLFBR + 82U, // CDLFTR + 82U, // CDLGBR + 82U, // CDLGTR 0U, // CDPT 0U, // CDR - 24U, // CDS - 24U, // CDSG + 64U, // CDS + 64U, // CDSG 0U, // CDSTR - 24U, // CDSY + 64U, // CDSY 0U, // CDTR 0U, // CDUTR 0U, // CDZT @@ -5581,37 +6183,37 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CEBR 0U, // CEDTR 0U, // CEFBR - 33U, // CEFBRA + 82U, // CEFBRA 0U, // CEFR 0U, // CEGBR - 33U, // CEGBRA + 82U, // CEGBRA 0U, // CEGR - 33U, // CELFBR - 33U, // CELGBR + 82U, // CELFBR + 82U, // CELGBR 0U, // CER 0U, // CEXTR 0U, // CFC - 41U, // CFDBR - 33U, // CFDBRA - 41U, // CFDR - 33U, // CFDTR - 41U, // CFEBR - 33U, // CFEBRA - 41U, // CFER + 34U, // CFDBR + 82U, // CFDBRA + 34U, // CFDR + 82U, // CFDTR + 34U, // CFEBR + 82U, // CFEBRA + 34U, // CFER 0U, // CFI - 41U, // CFXBR - 33U, // CFXBRA - 41U, // CFXR - 33U, // CFXTR + 34U, // CFXBR + 82U, // CFXBRA + 34U, // CFXR + 82U, // CFXTR 0U, // CG - 41U, // CGDBR - 33U, // CGDBRA - 41U, // CGDR - 41U, // CGDTR - 33U, // CGDTRA - 41U, // CGEBR - 33U, // CGEBRA - 41U, // CGER + 34U, // CGDBR + 82U, // CGDBRA + 34U, // CGDR + 34U, // CGDTR + 82U, // CGDTRA + 34U, // CGEBR + 82U, // CGEBRA + 34U, // CGER 0U, // CGF 0U, // CGFI 0U, // CGFR @@ -5621,35 +6223,35 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CGHRL 0U, // CGHSI 0U, // CGIB - 25U, // CGIBAsm - 1U, // CGIBAsmE - 1U, // CGIBAsmH - 1U, // CGIBAsmHE - 1U, // CGIBAsmL - 1U, // CGIBAsmLE - 1U, // CGIBAsmLH - 1U, // CGIBAsmNE - 1U, // CGIBAsmNH - 1U, // CGIBAsmNHE - 1U, // CGIBAsmNL - 1U, // CGIBAsmNLE - 1U, // CGIBAsmNLH + 66U, // CGIBAsm + 33U, // CGIBAsmE + 33U, // CGIBAsmH + 33U, // CGIBAsmHE + 33U, // CGIBAsmL + 33U, // CGIBAsmLE + 33U, // CGIBAsmLH + 33U, // CGIBAsmNE + 33U, // CGIBAsmNH + 33U, // CGIBAsmNHE + 33U, // CGIBAsmNL + 33U, // CGIBAsmNLE + 33U, // CGIBAsmNLH 0U, // CGIJ - 17U, // CGIJAsm - 0U, // CGIJAsmE - 0U, // CGIJAsmH - 0U, // CGIJAsmHE - 0U, // CGIJAsmL - 0U, // CGIJAsmLE - 0U, // CGIJAsmLH - 0U, // CGIJAsmNE - 0U, // CGIJAsmNH - 0U, // CGIJAsmNHE - 0U, // CGIJAsmNL - 0U, // CGIJAsmNLE - 0U, // CGIJAsmNLH + 50U, // CGIJAsm + 1U, // CGIJAsmE + 1U, // CGIJAsmH + 1U, // CGIJAsmHE + 1U, // CGIJAsmL + 1U, // CGIJAsmLE + 1U, // CGIJAsmLH + 1U, // CGIJAsmNE + 1U, // CGIJAsmNH + 1U, // CGIJAsmNHE + 1U, // CGIJAsmNL + 1U, // CGIJAsmNLE + 1U, // CGIJAsmNLH 0U, // CGIT - 48U, // CGITAsm + 96U, // CGITAsm 0U, // CGITAsmE 0U, // CGITAsmH 0U, // CGITAsmHE @@ -5663,37 +6265,37 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CGITAsmNLE 0U, // CGITAsmNLH 0U, // CGR - 41U, // CGRB - 8752U, // CGRBAsm - 56U, // CGRBAsmE - 56U, // CGRBAsmH - 56U, // CGRBAsmHE - 56U, // CGRBAsmL - 56U, // CGRBAsmLE - 56U, // CGRBAsmLH - 56U, // CGRBAsmNE - 56U, // CGRBAsmNH - 56U, // CGRBAsmNHE - 56U, // CGRBAsmNL - 56U, // CGRBAsmNLE - 56U, // CGRBAsmNLH - 2U, // CGRJ - 16944U, // CGRJAsm - 64U, // CGRJAsmE - 64U, // CGRJAsmH - 64U, // CGRJAsmHE - 64U, // CGRJAsmL - 64U, // CGRJAsmLE - 64U, // CGRJAsmLH - 64U, // CGRJAsmNE - 64U, // CGRJAsmNH - 64U, // CGRJAsmNHE - 64U, // CGRJAsmNL - 64U, // CGRJAsmNLE - 64U, // CGRJAsmNLH + 35U, // CGRB + 17504U, // CGRBAsm + 112U, // CGRBAsmE + 112U, // CGRBAsmH + 112U, // CGRBAsmHE + 112U, // CGRBAsmL + 112U, // CGRBAsmLE + 112U, // CGRBAsmLH + 112U, // CGRBAsmNE + 112U, // CGRBAsmNH + 112U, // CGRBAsmNHE + 112U, // CGRBAsmNL + 112U, // CGRBAsmNLE + 112U, // CGRBAsmNLH + 3U, // CGRJ + 33888U, // CGRJAsm + 128U, // CGRJAsmE + 128U, // CGRJAsmH + 128U, // CGRJAsmHE + 128U, // CGRJAsmL + 128U, // CGRJAsmLE + 128U, // CGRJAsmLH + 128U, // CGRJAsmNE + 128U, // CGRJAsmNH + 128U, // CGRJAsmNHE + 128U, // CGRJAsmNL + 128U, // CGRJAsmNLE + 128U, // CGRJAsmNLH 0U, // CGRL 0U, // CGRT - 48U, // CGRTAsm + 96U, // CGRTAsm 0U, // CGRTAsmE 0U, // CGRTAsmH 0U, // CGRTAsmHE @@ -5706,11 +6308,11 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CGRTAsmNL 0U, // CGRTAsmNLE 0U, // CGRTAsmNLH - 41U, // CGXBR - 33U, // CGXBRA - 41U, // CGXR - 41U, // CGXTR - 33U, // CGXTRA + 34U, // CGXBR + 82U, // CGXBRA + 34U, // CGXR + 34U, // CGXTR + 82U, // CGXTRA 0U, // CH 0U, // CHF 0U, // CHHR @@ -5721,36 +6323,36 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CHSI 0U, // CHY 0U, // CIB - 25U, // CIBAsm - 1U, // CIBAsmE - 1U, // CIBAsmH - 1U, // CIBAsmHE - 1U, // CIBAsmL - 1U, // CIBAsmLE - 1U, // CIBAsmLH - 1U, // CIBAsmNE - 1U, // CIBAsmNH - 1U, // CIBAsmNHE - 1U, // CIBAsmNL - 1U, // CIBAsmNLE - 1U, // CIBAsmNLH + 66U, // CIBAsm + 33U, // CIBAsmE + 33U, // CIBAsmH + 33U, // CIBAsmHE + 33U, // CIBAsmL + 33U, // CIBAsmLE + 33U, // CIBAsmLH + 33U, // CIBAsmNE + 33U, // CIBAsmNH + 33U, // CIBAsmNHE + 33U, // CIBAsmNL + 33U, // CIBAsmNLE + 33U, // CIBAsmNLH 0U, // CIH 0U, // CIJ - 17U, // CIJAsm - 0U, // CIJAsmE - 0U, // CIJAsmH - 0U, // CIJAsmHE - 0U, // CIJAsmL - 0U, // CIJAsmLE - 0U, // CIJAsmLH - 0U, // CIJAsmNE - 0U, // CIJAsmNH - 0U, // CIJAsmNHE - 0U, // CIJAsmNL - 0U, // CIJAsmNLE - 0U, // CIJAsmNLH + 50U, // CIJAsm + 1U, // CIJAsmE + 1U, // CIJAsmH + 1U, // CIJAsmHE + 1U, // CIJAsmL + 1U, // CIJAsmLE + 1U, // CIJAsmLH + 1U, // CIJAsmNE + 1U, // CIJAsmNH + 1U, // CIJAsmNHE + 1U, // CIJAsmNL + 1U, // CIJAsmNLE + 1U, // CIJAsmNLH 0U, // CIT - 48U, // CITAsm + 96U, // CITAsm 0U, // CITAsmE 0U, // CITAsmH 0U, // CITAsmHE @@ -5767,15 +6369,15 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CL 0U, // CLC 0U, // CLCL - 72U, // CLCLE - 72U, // CLCLU - 33U, // CLFDBR - 33U, // CLFDTR - 33U, // CLFEBR + 144U, // CLCLE + 144U, // CLCLU + 82U, // CLFDBR + 82U, // CLFDTR + 82U, // CLFEBR 0U, // CLFHSI 0U, // CLFI 0U, // CLFIT - 48U, // CLFITAsm + 96U, // CLFITAsm 0U, // CLFITAsmE 0U, // CLFITAsmH 0U, // CLFITAsmHE @@ -5788,12 +6390,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CLFITAsmNL 0U, // CLFITAsmNLE 0U, // CLFITAsmNLH - 33U, // CLFXBR - 33U, // CLFXTR + 82U, // CLFXBR + 82U, // CLFXTR 0U, // CLG - 33U, // CLGDBR - 33U, // CLGDTR - 33U, // CLGEBR + 82U, // CLGDBR + 82U, // CLGDTR + 82U, // CLGEBR 0U, // CLGF 0U, // CLGFI 0U, // CLGFR @@ -5801,35 +6403,35 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CLGHRL 0U, // CLGHSI 0U, // CLGIB - 25U, // CLGIBAsm - 1U, // CLGIBAsmE - 1U, // CLGIBAsmH - 1U, // CLGIBAsmHE - 1U, // CLGIBAsmL - 1U, // CLGIBAsmLE - 1U, // CLGIBAsmLH - 1U, // CLGIBAsmNE - 1U, // CLGIBAsmNH - 1U, // CLGIBAsmNHE - 1U, // CLGIBAsmNL - 1U, // CLGIBAsmNLE - 1U, // CLGIBAsmNLH + 66U, // CLGIBAsm + 33U, // CLGIBAsmE + 33U, // CLGIBAsmH + 33U, // CLGIBAsmHE + 33U, // CLGIBAsmL + 33U, // CLGIBAsmLE + 33U, // CLGIBAsmLH + 33U, // CLGIBAsmNE + 33U, // CLGIBAsmNH + 33U, // CLGIBAsmNHE + 33U, // CLGIBAsmNL + 33U, // CLGIBAsmNLE + 33U, // CLGIBAsmNLH 0U, // CLGIJ - 17U, // CLGIJAsm - 0U, // CLGIJAsmE - 0U, // CLGIJAsmH - 0U, // CLGIJAsmHE - 0U, // CLGIJAsmL - 0U, // CLGIJAsmLE - 0U, // CLGIJAsmLH - 0U, // CLGIJAsmNE - 0U, // CLGIJAsmNH - 0U, // CLGIJAsmNHE - 0U, // CLGIJAsmNL - 0U, // CLGIJAsmNLE - 0U, // CLGIJAsmNLH + 50U, // CLGIJAsm + 1U, // CLGIJAsmE + 1U, // CLGIJAsmH + 1U, // CLGIJAsmHE + 1U, // CLGIJAsmL + 1U, // CLGIJAsmLE + 1U, // CLGIJAsmLH + 1U, // CLGIJAsmNE + 1U, // CLGIJAsmNH + 1U, // CLGIJAsmNHE + 1U, // CLGIJAsmNL + 1U, // CLGIJAsmNLE + 1U, // CLGIJAsmNLH 0U, // CLGIT - 48U, // CLGITAsm + 96U, // CLGITAsm 0U, // CLGITAsmE 0U, // CLGITAsmH 0U, // CLGITAsmHE @@ -5843,37 +6445,37 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CLGITAsmNLE 0U, // CLGITAsmNLH 0U, // CLGR - 41U, // CLGRB - 8752U, // CLGRBAsm - 56U, // CLGRBAsmE - 56U, // CLGRBAsmH - 56U, // CLGRBAsmHE - 56U, // CLGRBAsmL - 56U, // CLGRBAsmLE - 56U, // CLGRBAsmLH - 56U, // CLGRBAsmNE - 56U, // CLGRBAsmNH - 56U, // CLGRBAsmNHE - 56U, // CLGRBAsmNL - 56U, // CLGRBAsmNLE - 56U, // CLGRBAsmNLH - 2U, // CLGRJ - 16944U, // CLGRJAsm - 64U, // CLGRJAsmE - 64U, // CLGRJAsmH - 64U, // CLGRJAsmHE - 64U, // CLGRJAsmL - 64U, // CLGRJAsmLE - 64U, // CLGRJAsmLH - 64U, // CLGRJAsmNE - 64U, // CLGRJAsmNH - 64U, // CLGRJAsmNHE - 64U, // CLGRJAsmNL - 64U, // CLGRJAsmNLE - 64U, // CLGRJAsmNLH + 35U, // CLGRB + 17504U, // CLGRBAsm + 112U, // CLGRBAsmE + 112U, // CLGRBAsmH + 112U, // CLGRBAsmHE + 112U, // CLGRBAsmL + 112U, // CLGRBAsmLE + 112U, // CLGRBAsmLH + 112U, // CLGRBAsmNE + 112U, // CLGRBAsmNH + 112U, // CLGRBAsmNHE + 112U, // CLGRBAsmNL + 112U, // CLGRBAsmNLE + 112U, // CLGRBAsmNLH + 3U, // CLGRJ + 33888U, // CLGRJAsm + 128U, // CLGRJAsmE + 128U, // CLGRJAsmH + 128U, // CLGRJAsmHE + 128U, // CLGRJAsmL + 128U, // CLGRJAsmLE + 128U, // CLGRJAsmLH + 128U, // CLGRJAsmNE + 128U, // CLGRJAsmNH + 128U, // CLGRJAsmNHE + 128U, // CLGRJAsmNL + 128U, // CLGRJAsmNLE + 128U, // CLGRJAsmNLH 0U, // CLGRL 0U, // CLGRT - 48U, // CLGRTAsm + 96U, // CLGRTAsm 0U, // CLGRTAsmE 0U, // CLGRTAsmH 0U, // CLGRTAsmHE @@ -5887,7 +6489,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CLGRTAsmNLE 0U, // CLGRTAsmNLH 0U, // CLGT - 80U, // CLGTAsm + 160U, // CLGTAsm 0U, // CLGTAsmE 0U, // CLGTAsmH 0U, // CLGTAsmHE @@ -5900,8 +6502,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CLGTAsmNL 0U, // CLGTAsmNLE 0U, // CLGTAsmNLH - 33U, // CLGXBR - 33U, // CLGXTR + 82U, // CLGXBR + 82U, // CLGXTR 0U, // CLHF 0U, // CLHHR 0U, // CLHHSI @@ -5909,70 +6511,70 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CLHRL 0U, // CLI 0U, // CLIB - 25U, // CLIBAsm - 1U, // CLIBAsmE - 1U, // CLIBAsmH - 1U, // CLIBAsmHE - 1U, // CLIBAsmL - 1U, // CLIBAsmLE - 1U, // CLIBAsmLH - 1U, // CLIBAsmNE - 1U, // CLIBAsmNH - 1U, // CLIBAsmNHE - 1U, // CLIBAsmNL - 1U, // CLIBAsmNLE - 1U, // CLIBAsmNLH + 66U, // CLIBAsm + 33U, // CLIBAsmE + 33U, // CLIBAsmH + 33U, // CLIBAsmHE + 33U, // CLIBAsmL + 33U, // CLIBAsmLE + 33U, // CLIBAsmLH + 33U, // CLIBAsmNE + 33U, // CLIBAsmNH + 33U, // CLIBAsmNHE + 33U, // CLIBAsmNL + 33U, // CLIBAsmNLE + 33U, // CLIBAsmNLH 0U, // CLIH 0U, // CLIJ - 17U, // CLIJAsm - 0U, // CLIJAsmE - 0U, // CLIJAsmH - 0U, // CLIJAsmHE - 0U, // CLIJAsmL - 0U, // CLIJAsmLE - 0U, // CLIJAsmLH - 0U, // CLIJAsmNE - 0U, // CLIJAsmNH - 0U, // CLIJAsmNHE - 0U, // CLIJAsmNL - 0U, // CLIJAsmNLE - 0U, // CLIJAsmNLH + 50U, // CLIJAsm + 1U, // CLIJAsmE + 1U, // CLIJAsmH + 1U, // CLIJAsmHE + 1U, // CLIJAsmL + 1U, // CLIJAsmLE + 1U, // CLIJAsmLH + 1U, // CLIJAsmNE + 1U, // CLIJAsmNH + 1U, // CLIJAsmNHE + 1U, // CLIJAsmNL + 1U, // CLIJAsmNLE + 1U, // CLIJAsmNLH 0U, // CLIY - 1U, // CLM - 1U, // CLMH - 1U, // CLMY + 33U, // CLM + 33U, // CLMH + 33U, // CLMY 0U, // CLR - 41U, // CLRB - 8752U, // CLRBAsm - 56U, // CLRBAsmE - 56U, // CLRBAsmH - 56U, // CLRBAsmHE - 56U, // CLRBAsmL - 56U, // CLRBAsmLE - 56U, // CLRBAsmLH - 56U, // CLRBAsmNE - 56U, // CLRBAsmNH - 56U, // CLRBAsmNHE - 56U, // CLRBAsmNL - 56U, // CLRBAsmNLE - 56U, // CLRBAsmNLH - 2U, // CLRJ - 16944U, // CLRJAsm - 64U, // CLRJAsmE - 64U, // CLRJAsmH - 64U, // CLRJAsmHE - 64U, // CLRJAsmL - 64U, // CLRJAsmLE - 64U, // CLRJAsmLH - 64U, // CLRJAsmNE - 64U, // CLRJAsmNH - 64U, // CLRJAsmNHE - 64U, // CLRJAsmNL - 64U, // CLRJAsmNLE - 64U, // CLRJAsmNLH + 35U, // CLRB + 17504U, // CLRBAsm + 112U, // CLRBAsmE + 112U, // CLRBAsmH + 112U, // CLRBAsmHE + 112U, // CLRBAsmL + 112U, // CLRBAsmLE + 112U, // CLRBAsmLH + 112U, // CLRBAsmNE + 112U, // CLRBAsmNH + 112U, // CLRBAsmNHE + 112U, // CLRBAsmNL + 112U, // CLRBAsmNLE + 112U, // CLRBAsmNLH + 3U, // CLRJ + 33888U, // CLRJAsm + 128U, // CLRJAsmE + 128U, // CLRJAsmH + 128U, // CLRJAsmHE + 128U, // CLRJAsmL + 128U, // CLRJAsmLE + 128U, // CLRJAsmLH + 128U, // CLRJAsmNE + 128U, // CLRJAsmNH + 128U, // CLRJAsmNHE + 128U, // CLRJAsmNL + 128U, // CLRJAsmNLE + 128U, // CLRJAsmNLH 0U, // CLRL 0U, // CLRT - 48U, // CLRTAsm + 96U, // CLRTAsm 0U, // CLRTAsmE 0U, // CLRTAsmH 0U, // CLRTAsmHE @@ -5987,7 +6589,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CLRTAsmNLH 0U, // CLST 0U, // CLT - 80U, // CLTAsm + 160U, // CLTAsm 0U, // CLTAsmE 0U, // CLTAsmH 0U, // CLTAsmHE @@ -6004,46 +6606,46 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CMPSC 0U, // CP 0U, // CPDT - 88U, // CPSDRdd - 88U, // CPSDRds - 88U, // CPSDRsd - 88U, // CPSDRss + 176U, // CPSDRdd + 176U, // CPSDRds + 176U, // CPSDRsd + 176U, // CPSDRss 0U, // CPXT 0U, // CPYA 0U, // CR - 41U, // CRB - 8752U, // CRBAsm - 56U, // CRBAsmE - 56U, // CRBAsmH - 56U, // CRBAsmHE - 56U, // CRBAsmL - 56U, // CRBAsmLE - 56U, // CRBAsmLH - 56U, // CRBAsmNE - 56U, // CRBAsmNH - 56U, // CRBAsmNHE - 56U, // CRBAsmNL - 56U, // CRBAsmNLE - 56U, // CRBAsmNLH - 600U, // CRDTE - 88U, // CRDTEOpt - 2U, // CRJ - 16944U, // CRJAsm - 64U, // CRJAsmE - 64U, // CRJAsmH - 64U, // CRJAsmHE - 64U, // CRJAsmL - 64U, // CRJAsmLE - 64U, // CRJAsmLH - 64U, // CRJAsmNE - 64U, // CRJAsmNH - 64U, // CRJAsmNHE - 64U, // CRJAsmNL - 64U, // CRJAsmNLE - 64U, // CRJAsmNLH + 35U, // CRB + 17504U, // CRBAsm + 112U, // CRBAsmE + 112U, // CRBAsmH + 112U, // CRBAsmHE + 112U, // CRBAsmL + 112U, // CRBAsmLE + 112U, // CRBAsmLH + 112U, // CRBAsmNE + 112U, // CRBAsmNH + 112U, // CRBAsmNHE + 112U, // CRBAsmNL + 112U, // CRBAsmNLE + 112U, // CRBAsmNLH + 1200U, // CRDTE + 176U, // CRDTEOpt + 3U, // CRJ + 33888U, // CRJAsm + 128U, // CRJAsmE + 128U, // CRJAsmH + 128U, // CRJAsmHE + 128U, // CRJAsmL + 128U, // CRJAsmLE + 128U, // CRJAsmLH + 128U, // CRJAsmNE + 128U, // CRJAsmNH + 128U, // CRJAsmNHE + 128U, // CRJAsmNL + 128U, // CRJAsmNLE + 128U, // CRJAsmNLH 0U, // CRL 0U, // CRT - 48U, // CRTAsm + 96U, // CRTAsm 0U, // CRTAsmE 0U, // CRTAsmH 0U, // CRTAsmHE @@ -6056,30 +6658,30 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CRTAsmNL 0U, // CRTAsmNLE 0U, // CRTAsmNLH - 24U, // CS + 64U, // CS 0U, // CSCH - 48U, // CSDTR - 24U, // CSG + 96U, // CSDTR + 64U, // CSG 0U, // CSP 0U, // CSPG - 96U, // CSST - 48U, // CSXTR - 24U, // CSY - 104U, // CU12 + 192U, // CSST + 96U, // CSXTR + 64U, // CSY + 208U, // CU12 0U, // CU12Opt - 104U, // CU14 + 208U, // CU14 0U, // CU14Opt - 104U, // CU21 + 208U, // CU21 0U, // CU21Opt - 104U, // CU24 + 208U, // CU24 0U, // CU24Opt 0U, // CU41 0U, // CU42 0U, // CUDTR 0U, // CUSE - 104U, // CUTFU + 208U, // CUTFU 0U, // CUTFUOpt - 104U, // CUUTF + 208U, // CUUTF 0U, // CUUTFOpt 0U, // CUXTR 0U, // CVB @@ -6090,18 +6692,18 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CVDY 0U, // CXBR 0U, // CXFBR - 33U, // CXFBRA + 82U, // CXFBRA 0U, // CXFR - 33U, // CXFTR + 82U, // CXFTR 0U, // CXGBR - 33U, // CXGBRA + 82U, // CXGBRA 0U, // CXGR 0U, // CXGTR - 33U, // CXGTRA - 33U, // CXLFBR - 33U, // CXLFTR - 33U, // CXLGBR - 33U, // CXLGTR + 82U, // CXGTRA + 82U, // CXLFBR + 82U, // CXLFTR + 82U, // CXLGBR + 82U, // CXLGTR 0U, // CXPT 0U, // CXR 0U, // CXSTR @@ -6117,14 +6719,15 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // DDBR 0U, // DDR 0U, // DDTR - 512U, // DDTRA + 1024U, // DDTRA 0U, // DE 0U, // DEB 0U, // DEBR 0U, // DER - 56U, // DIAG - 25200U, // DIDBR - 25200U, // DIEBR + 192U, // DFLTCC + 112U, // DIAG + 50400U, // DIDBR + 50400U, // DIEBR 0U, // DL 0U, // DLG 0U, // DLGR @@ -6138,12 +6741,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // DXBR 0U, // DXR 0U, // DXTR - 512U, // DXTRA + 1024U, // DXTRA 0U, // EAR - 56U, // ECAG + 112U, // ECAG 0U, // ECCTR 0U, // ECPGA - 96U, // ECTG + 192U, // ECTG 0U, // ED 0U, // EDMK 0U, // EEDTR @@ -6164,17 +6767,17 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // ETND 0U, // EX 0U, // EXRL - 41U, // FIDBR - 33U, // FIDBRA + 34U, // FIDBR + 82U, // FIDBRA 0U, // FIDR - 33U, // FIDTR - 41U, // FIEBR - 33U, // FIEBRA + 82U, // FIDTR + 34U, // FIEBR + 82U, // FIEBRA 0U, // FIER - 41U, // FIXBR - 33U, // FIXBRA + 34U, // FIXBR + 82U, // FIXBRA 0U, // FIXR - 33U, // FIXTR + 82U, // FIXTR 0U, // FLOGR 0U, // HDR 0U, // HER @@ -6187,10 +6790,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // ICMH 0U, // ICMY 0U, // ICY - 600U, // IDTE - 88U, // IDTEOpt - 88U, // IEDTR - 88U, // IEXTR + 1200U, // IDTE + 176U, // IDTEOpt + 176U, // IEDTR + 176U, // IEXTR 0U, // IIHF 0U, // IIHH 0U, // IIHL @@ -6199,37 +6802,43 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // IILL 0U, // IPK 0U, // IPM - 512U, // IPTE + 1024U, // IPTE 0U, // IPTEOpt 0U, // IPTEOptOpt 0U, // IRBM 0U, // ISKE 0U, // IVSK 0U, // InsnE - 2U, // InsnRI - 1145U, // InsnRIE - 0U, // InsnRIL - 2U, // InsnRILU - 2U, // InsnRIS + 4U, // InsnRI + 2290U, // InsnRIE + 1U, // InsnRIL + 4U, // InsnRILU + 5U, // InsnRIS 0U, // InsnRR - 41U, // InsnRRE - 1657U, // InsnRRF - 34937U, // InsnRRS - 2681U, // InsnRS - 2681U, // InsnRSE - 1145U, // InsnRSI - 2681U, // InsnRSY - 0U, // InsnRX - 0U, // InsnRXE - 3193U, // InsnRXF - 0U, // InsnRXY + 34U, // InsnRRE + 3314U, // InsnRRF + 20722U, // InsnRRS + 5362U, // InsnRS + 5362U, // InsnRSE + 2290U, // InsnRSI + 5362U, // InsnRSY + 37U, // InsnRX + 37U, // InsnRXE + 6386U, // InsnRXF + 37U, // InsnRXY 0U, // InsnS - 3U, // InsnSI - 3U, // InsnSIL - 3U, // InsnSIY + 6U, // InsnSI + 6U, // InsnSIL + 7U, // InsnSIY 0U, // InsnSS - 41U, // InsnSSE - 3705U, // InsnSSF + 35U, // InsnSSE + 7411U, // InsnSSF + 8434U, // InsnVRI + 19698U, // InsnVRR + 0U, // InsnVRS + 7U, // InsnVRV + 9461U, // InsnVRX + 10481U, // InsnVSI 0U, // J 0U, // JAsmE 0U, // JAsmH @@ -6274,44 +6883,46 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // JGAsmZ 0U, // KDB 0U, // KDBR + 0U, // KDSA 0U, // KDTR 0U, // KEB 0U, // KEBR 0U, // KIMD 0U, // KLMD 0U, // KM - 88U, // KMA + 176U, // KMA 0U, // KMAC 0U, // KMC - 88U, // KMCTR + 176U, // KMCTR 0U, // KMF 0U, // KMO 0U, // KXBR 0U, // KXTR 0U, // L 0U, // LA - 56U, // LAA - 56U, // LAAG - 56U, // LAAL - 56U, // LAALG + 112U, // LAA + 112U, // LAAG + 112U, // LAAL + 112U, // LAALG 0U, // LAE 0U, // LAEY - 56U, // LAM - 56U, // LAMY - 56U, // LAN - 56U, // LANG - 56U, // LAO - 56U, // LAOG + 112U, // LAM + 112U, // LAMY + 112U, // LAN + 112U, // LANG + 112U, // LAO + 112U, // LAOG 0U, // LARL 0U, // LASP 0U, // LAT - 56U, // LAX - 56U, // LAXG + 112U, // LAX + 112U, // LAXG 0U, // LAY 0U, // LB + 0U, // LBEAR 0U, // LBH 0U, // LBR - 104U, // LCBB + 208U, // LCBB 0U, // LCCTL 0U, // LCDBR 0U, // LCDFR @@ -6322,8 +6933,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LCGFR 0U, // LCGR 0U, // LCR - 56U, // LCTL - 56U, // LCTLG + 112U, // LCTL + 112U, // LCTLG 0U, // LCXBR 0U, // LCXR 0U, // LD @@ -6332,23 +6943,23 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LDEB 0U, // LDEBR 0U, // LDER - 48U, // LDETR + 96U, // LDETR 0U, // LDGR 0U, // LDR 0U, // LDR32 0U, // LDXBR - 33U, // LDXBRA + 82U, // LDXBRA 0U, // LDXR - 33U, // LDXTR + 82U, // LDXTR 0U, // LDY 0U, // LE 0U, // LEDBR - 33U, // LEDBRA + 82U, // LEDBRA 0U, // LEDR - 33U, // LEDTR + 82U, // LEDTR 0U, // LER 0U, // LEXBR - 33U, // LEXBRA + 82U, // LEXBRA 0U, // LEXR 0U, // LEY 0U, // LFAS @@ -6405,11 +7016,11 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LLILH 0U, // LLILL 0U, // LLZRGF - 56U, // LM - 41528U, // LMD - 56U, // LMG - 56U, // LMH - 56U, // LMY + 112U, // LM + 33904U, // LMD + 112U, // LMG + 112U, // LMH + 112U, // LMY 0U, // LNDBR 0U, // LNDFR 0U, // LNDFR_32 @@ -6422,7 +7033,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LNXBR 0U, // LNXR 0U, // LOC - 104U, // LOCAsm + 208U, // LOCAsm 0U, // LOCAsmE 0U, // LOCAsmH 0U, // LOCAsmHE @@ -6444,7 +7055,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LOCAsmP 0U, // LOCAsmZ 0U, // LOCFH - 104U, // LOCFHAsm + 208U, // LOCFHAsm 0U, // LOCFHAsmE 0U, // LOCFHAsmH 0U, // LOCFHAsmHE @@ -6466,7 +7077,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LOCFHAsmP 0U, // LOCFHAsmZ 0U, // LOCFHR - 128U, // LOCFHRAsm + 256U, // LOCFHRAsm 0U, // LOCFHRAsmE 0U, // LOCFHRAsmH 0U, // LOCFHRAsmHE @@ -6488,7 +7099,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LOCFHRAsmP 0U, // LOCFHRAsmZ 0U, // LOCG - 104U, // LOCGAsm + 208U, // LOCGAsm 0U, // LOCGAsmE 0U, // LOCGAsmH 0U, // LOCGAsmHE @@ -6510,7 +7121,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LOCGAsmP 0U, // LOCGAsmZ 0U, // LOCGHI - 128U, // LOCGHIAsm + 256U, // LOCGHIAsm 0U, // LOCGHIAsmE 0U, // LOCGHIAsmH 0U, // LOCGHIAsmHE @@ -6532,7 +7143,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LOCGHIAsmP 0U, // LOCGHIAsmZ 0U, // LOCGR - 128U, // LOCGRAsm + 256U, // LOCGRAsm 0U, // LOCGRAsmE 0U, // LOCGRAsmH 0U, // LOCGRAsmHE @@ -6554,7 +7165,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LOCGRAsmP 0U, // LOCGRAsmZ 0U, // LOCHHI - 128U, // LOCHHIAsm + 256U, // LOCHHIAsm 0U, // LOCHHIAsmE 0U, // LOCHHIAsmH 0U, // LOCHHIAsmHE @@ -6576,7 +7187,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LOCHHIAsmP 0U, // LOCHHIAsmZ 0U, // LOCHI - 128U, // LOCHIAsm + 256U, // LOCHIAsm 0U, // LOCHIAsmE 0U, // LOCHIAsmH 0U, // LOCHIAsmHE @@ -6598,7 +7209,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LOCHIAsmP 0U, // LOCHIAsmZ 0U, // LOCR - 128U, // LOCRAsm + 256U, // LOCRAsm 0U, // LOCRAsmE 0U, // LOCRAsmH 0U, // LOCRAsmHE @@ -6620,11 +7231,11 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LOCRAsmP 0U, // LOCRAsmZ 0U, // LPCTL - 24U, // LPD + 64U, // LPD 0U, // LPDBR 0U, // LPDFR 0U, // LPDFR_32 - 24U, // LPDG + 64U, // LPDG 0U, // LPDR 0U, // LPEBR 0U, // LPER @@ -6635,7 +7246,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LPR 0U, // LPSW 0U, // LPSWE - 25200U, // LPTEA + 0U, // LPSWEY + 50400U, // LPTEA 0U, // LPXBR 0U, // LPXR 0U, // LR @@ -6653,11 +7265,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LSCTL 0U, // LT 0U, // LTDBR - 0U, // LTDBRCompare 0U, // LTDR 0U, // LTDTR 0U, // LTEBR - 0U, // LTEBRCompare 0U, // LTER 0U, // LTG 0U, // LTGF @@ -6665,7 +7275,6 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LTGR 0U, // LTR 0U, // LTXBR - 0U, // LTXBRCompare 0U, // LTXR 0U, // LTXTR 0U, // LURA @@ -6674,7 +7283,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LXDB 0U, // LXDBR 0U, // LXDR - 48U, // LXDTR + 96U, // LXDTR 0U, // LXE 0U, // LXEB 0U, // LXEBR @@ -6687,20 +7296,20 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LZRG 0U, // LZXR 0U, // M - 136U, // MAD - 136U, // MADB - 112U, // MADBR - 112U, // MADR - 136U, // MAE - 136U, // MAEB - 112U, // MAEBR - 112U, // MAER - 136U, // MAY - 136U, // MAYH - 112U, // MAYHR - 136U, // MAYL - 112U, // MAYLR - 112U, // MAYR + 272U, // MAD + 272U, // MADB + 224U, // MADBR + 224U, // MADR + 272U, // MAE + 272U, // MAEB + 224U, // MAEBR + 224U, // MAER + 272U, // MAY + 272U, // MAYH + 224U, // MAYHR + 272U, // MAYL + 224U, // MAYLR + 224U, // MAYR 0U, // MC 0U, // MD 0U, // MDB @@ -6711,7 +7320,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // MDER 0U, // MDR 0U, // MDTR - 512U, // MDTRA + 1024U, // MDTRA 0U, // ME 0U, // MEE 0U, // MEEB @@ -6735,14 +7344,14 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // MS 0U, // MSC 0U, // MSCH - 136U, // MSD - 136U, // MSDB - 112U, // MSDBR - 112U, // MSDR - 136U, // MSE - 136U, // MSEB - 112U, // MSEBR - 112U, // MSER + 272U, // MSD + 272U, // MSDB + 224U, // MSDBR + 224U, // MSDR + 272U, // MSE + 272U, // MSEB + 224U, // MSEBR + 224U, // MSER 0U, // MSFI 0U, // MSG 0U, // MSGC @@ -6760,10 +7369,11 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // MVCIN 0U, // MVCK 0U, // MVCL - 72U, // MVCLE - 72U, // MVCLU - 96U, // MVCOS + 144U, // MVCLE + 144U, // MVCLU + 192U, // MVCOS 0U, // MVCP + 0U, // MVCRL 0U, // MVCS 0U, // MVCSK 0U, // MVGHI @@ -6783,15 +7393,17 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // MXDR 0U, // MXR 0U, // MXTR - 512U, // MXTRA - 144U, // MY - 144U, // MYH + 1024U, // MXTRA + 288U, // MY + 288U, // MYH 0U, // MYHR - 144U, // MYL + 288U, // MYL 0U, // MYLR 0U, // MYR 0U, // N 0U, // NC + 0U, // NCGRK + 0U, // NCRK 0U, // NG 0U, // NGR 0U, // NGRK @@ -6804,12 +7416,22 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // NILH 0U, // NILL 0U, // NIY + 0U, // NNGRK + 0U, // NNPA + 0U, // NNRK + 0U, // NOGRK + 0U, // NOP_bare + 0U, // NORK 0U, // NR 0U, // NRK 0U, // NTSTG + 0U, // NXGRK + 0U, // NXRK 0U, // NY 0U, // O 0U, // OC + 0U, // OCGRK + 0U, // OCRK 0U, // OG 0U, // OGR 0U, // OGRK @@ -6837,9 +7459,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // PGOUT 0U, // PKA 0U, // PKU - 41584U, // PLO + 34016U, // PLO 0U, // POPCNT - 48U, // PPA + 96U, // POPCNTOpt + 96U, // PPA 0U, // PPNO 0U, // PR 0U, // PRNO @@ -6848,27 +7471,30 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // PTFF 0U, // PTI 0U, // PTLB - 25200U, // QADTR - 25200U, // QAXTR + 50400U, // QADTR + 50400U, // QAXTR 0U, // QCTRI + 0U, // QPACI 0U, // QSI 0U, // RCHP - 49816U, // RISBG - 49816U, // RISBG32 - 49816U, // RISBGN - 49816U, // RISBHG - 49816U, // RISBLG - 56U, // RLL - 56U, // RLLG - 49816U, // RNSBG - 49816U, // ROSBG + 1200U, // RDP + 176U, // RDPOpt + 50480U, // RISBG + 50480U, // RISBG32 + 50480U, // RISBGN + 50480U, // RISBHG + 50480U, // RISBLG + 112U, // RLL + 112U, // RLLG + 50480U, // RNSBG + 50480U, // ROSBG 0U, // RP 0U, // RRBE 0U, // RRBM - 25200U, // RRDTR - 25200U, // RRXTR + 50400U, // RRDTR + 50400U, // RRXTR 0U, // RSCH - 49816U, // RXSBG + 50480U, // RXSBG 0U, // S 0U, // SAC 0U, // SACF @@ -6887,10 +7513,76 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // SDBR 0U, // SDR 0U, // SDTR - 512U, // SDTRA + 1024U, // SDTRA 0U, // SE 0U, // SEB 0U, // SEBR + 8U, // SELFHR + 1200U, // SELFHRAsm + 176U, // SELFHRAsmE + 176U, // SELFHRAsmH + 176U, // SELFHRAsmHE + 176U, // SELFHRAsmL + 176U, // SELFHRAsmLE + 176U, // SELFHRAsmLH + 176U, // SELFHRAsmM + 176U, // SELFHRAsmNE + 176U, // SELFHRAsmNH + 176U, // SELFHRAsmNHE + 176U, // SELFHRAsmNL + 176U, // SELFHRAsmNLE + 176U, // SELFHRAsmNLH + 176U, // SELFHRAsmNM + 176U, // SELFHRAsmNO + 176U, // SELFHRAsmNP + 176U, // SELFHRAsmNZ + 176U, // SELFHRAsmO + 176U, // SELFHRAsmP + 176U, // SELFHRAsmZ + 8U, // SELGR + 1200U, // SELGRAsm + 176U, // SELGRAsmE + 176U, // SELGRAsmH + 176U, // SELGRAsmHE + 176U, // SELGRAsmL + 176U, // SELGRAsmLE + 176U, // SELGRAsmLH + 176U, // SELGRAsmM + 176U, // SELGRAsmNE + 176U, // SELGRAsmNH + 176U, // SELGRAsmNHE + 176U, // SELGRAsmNL + 176U, // SELGRAsmNLE + 176U, // SELGRAsmNLH + 176U, // SELGRAsmNM + 176U, // SELGRAsmNO + 176U, // SELGRAsmNP + 176U, // SELGRAsmNZ + 176U, // SELGRAsmO + 176U, // SELGRAsmP + 176U, // SELGRAsmZ + 8U, // SELR + 1200U, // SELRAsm + 176U, // SELRAsmE + 176U, // SELRAsmH + 176U, // SELRAsmHE + 176U, // SELRAsmL + 176U, // SELRAsmLE + 176U, // SELRAsmLH + 176U, // SELRAsmM + 176U, // SELRAsmNE + 176U, // SELRAsmNH + 176U, // SELRAsmNHE + 176U, // SELRAsmNL + 176U, // SELRAsmNLE + 176U, // SELRAsmNLH + 176U, // SELRAsmNM + 176U, // SELRAsmNO + 176U, // SELRAsmNP + 176U, // SELRAsmNZ + 176U, // SELRAsmO + 176U, // SELRAsmP + 176U, // SELRAsmZ 0U, // SER 0U, // SFASR 0U, // SFPC @@ -6906,18 +7598,18 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // SHY 0U, // SIE 0U, // SIGA - 56U, // SIGP + 112U, // SIGP 0U, // SL 0U, // SLA - 56U, // SLAG - 56U, // SLAK + 112U, // SLAG + 112U, // SLAK 0U, // SLB 0U, // SLBG 0U, // SLBGR 0U, // SLBR 0U, // SLDA 0U, // SLDL - 144U, // SLDT + 288U, // SLDT 0U, // SLFI 0U, // SLG 0U, // SLGF @@ -6928,12 +7620,13 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // SLHHHR 0U, // SLHHLR 0U, // SLL - 56U, // SLLG - 56U, // SLLK + 112U, // SLLG + 112U, // SLLK 0U, // SLR 0U, // SLRK - 144U, // SLXT + 288U, // SLXT 0U, // SLY + 0U, // SORTL 0U, // SP 0U, // SPCTR 0U, // SPKA @@ -6952,45 +7645,46 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // SQXR 0U, // SR 0U, // SRA - 56U, // SRAG - 56U, // SRAK + 112U, // SRAG + 112U, // SRAK 0U, // SRDA 0U, // SRDL - 144U, // SRDT + 288U, // SRDT 0U, // SRK 0U, // SRL - 56U, // SRLG - 56U, // SRLK + 112U, // SRLG + 112U, // SRLK 0U, // SRNM 0U, // SRNMB 0U, // SRNMT - 160U, // SRP + 320U, // SRP 0U, // SRST 0U, // SRSTU - 144U, // SRXT + 288U, // SRXT 0U, // SSAIR 0U, // SSAR 0U, // SSCH - 48U, // SSKE + 96U, // SSKE 0U, // SSKEOpt 0U, // SSM 0U, // ST - 56U, // STAM - 56U, // STAMY + 112U, // STAM + 112U, // STAMY 0U, // STAP + 0U, // STBEAR 0U, // STC 0U, // STCH 0U, // STCK 0U, // STCKC 0U, // STCKE 0U, // STCKF - 1U, // STCM - 1U, // STCMH - 1U, // STCMY + 33U, // STCM + 33U, // STCMH + 33U, // STCMY 0U, // STCPS 0U, // STCRW - 56U, // STCTG - 56U, // STCTL + 112U, // STCTG + 112U, // STCTL 0U, // STCY 0U, // STD 0U, // STDY @@ -7008,13 +7702,13 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // STHRL 0U, // STHY 0U, // STIDP - 56U, // STM - 56U, // STMG - 56U, // STMH - 56U, // STMY + 112U, // STM + 112U, // STMG + 112U, // STMH + 112U, // STMY 0U, // STNSM 0U, // STOC - 128U, // STOCAsm + 256U, // STOCAsm 0U, // STOCAsmE 0U, // STOCAsmH 0U, // STOCAsmHE @@ -7036,7 +7730,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // STOCAsmP 0U, // STOCAsmZ 0U, // STOCFH - 128U, // STOCFHAsm + 256U, // STOCFHAsm 0U, // STOCFHAsmE 0U, // STOCFHAsmH 0U, // STOCFHAsmHE @@ -7058,7 +7752,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // STOCFHAsmP 0U, // STOCFHAsmZ 0U, // STOCG - 128U, // STOCGAsm + 256U, // STOCGAsm 0U, // STOCGAsmE 0U, // STOCGAsmH 0U, // STOCGAsmHE @@ -7101,14 +7795,14 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // SXBR 0U, // SXR 0U, // SXTR - 512U, // SXTRA + 1024U, // SXTRA 0U, // SY 0U, // TABORT 0U, // TAM 0U, // TAR 0U, // TB - 41U, // TBDR - 41U, // TBEDR + 34U, // TBDR + 34U, // TBEDR 0U, // TBEGIN 0U, // TBEGINC 0U, // TCDB @@ -7133,24 +7827,24 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // TPI 0U, // TPROT 0U, // TR - 56U, // TRACE - 56U, // TRACG + 112U, // TRACE + 112U, // TRACG 0U, // TRAP2 0U, // TRAP4 0U, // TRE - 104U, // TROO + 208U, // TROO 0U, // TROOOpt - 104U, // TROT + 208U, // TROT 0U, // TROTOpt 0U, // TRT 0U, // TRTE 0U, // TRTEOpt - 104U, // TRTO + 208U, // TRTO 0U, // TRTOOpt 0U, // TRTR 0U, // TRTRE 0U, // TRTREOpt - 104U, // TRTT + 208U, // TRTT 0U, // TRTTOpt 0U, // TS 0U, // TSCH @@ -7158,39 +7852,41 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // UNPKA 0U, // UNPKU 0U, // UPT - 512U, // VA + 1024U, // VA 0U, // VAB - 57856U, // VAC - 512U, // VACC + 1024U, // VAC + 1024U, // VACC 0U, // VACCB - 57856U, // VACCC - 57856U, // VACCCQ + 1024U, // VACCC + 1024U, // VACCCQ 0U, // VACCF 0U, // VACCG 0U, // VACCH 0U, // VACCQ - 57856U, // VACQ + 1024U, // VACQ 0U, // VAF 0U, // VAG 0U, // VAH - 512U, // VAP + 17408U, // VAP 0U, // VAQ - 512U, // VAVG + 1024U, // VAVG 0U, // VAVGB 0U, // VAVGF 0U, // VAVGG 0U, // VAVGH - 512U, // VAVGL + 1024U, // VAVGL 0U, // VAVGLB 0U, // VAVGLF 0U, // VAVGLG 0U, // VAVGLH 0U, // VBPERM - 560U, // VCDG - 560U, // VCDGB - 560U, // VCDLG - 560U, // VCDLGB - 512U, // VCEQ + 1120U, // VCDG + 1120U, // VCDGB + 1120U, // VCDLG + 1120U, // VCDLGB + 1120U, // VCEFB + 1120U, // VCELFB + 1024U, // VCEQ 0U, // VCEQB 0U, // VCEQBS 0U, // VCEQF @@ -7199,9 +7895,13 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VCEQGS 0U, // VCEQH 0U, // VCEQHS - 560U, // VCGD - 560U, // VCGDB - 512U, // VCH + 1120U, // VCFEB + 1120U, // VCFN + 1120U, // VCFPL + 1120U, // VCFPS + 1120U, // VCGD + 1120U, // VCGDB + 1024U, // VCH 0U, // VCHB 0U, // VCHBS 0U, // VCHF @@ -7210,7 +7910,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VCHGS 0U, // VCHH 0U, // VCHHS - 512U, // VCHL + 1024U, // VCHL 0U, // VCHLB 0U, // VCHLBS 0U, // VCHLF @@ -7220,119 +7920,130 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VCHLH 0U, // VCHLHS 0U, // VCKSM - 560U, // VCLGD - 560U, // VCLGDB - 48U, // VCLZ + 1120U, // VCLFEB + 1120U, // VCLFNH + 1120U, // VCLFNL + 1120U, // VCLFP + 1120U, // VCLGD + 1120U, // VCLGDB + 96U, // VCLZ 0U, // VCLZB + 96U, // VCLZDP 0U, // VCLZF 0U, // VCLZG 0U, // VCLZH - 48U, // VCP - 48U, // VCTZ + 1120U, // VCNF + 96U, // VCP + 1024U, // VCRNF + 1120U, // VCSFP + 1024U, // VCSPH + 96U, // VCTZ 0U, // VCTZB 0U, // VCTZF 0U, // VCTZG 0U, // VCTZH - 48U, // VCVB - 48U, // VCVBG - 10408U, // VCVD - 10408U, // VCVDG - 512U, // VDP - 48U, // VEC + 96U, // VCVB + 96U, // VCVBG + 1120U, // VCVBGOpt + 1120U, // VCVBOpt + 4432U, // VCVD + 4432U, // VCVDG + 17408U, // VDP + 96U, // VEC 0U, // VECB 0U, // VECF 0U, // VECG 0U, // VECH - 48U, // VECL + 96U, // VECL 0U, // VECLB 0U, // VECLF 0U, // VECLG 0U, // VECLH - 49776U, // VERIM - 49776U, // VERIMB - 49776U, // VERIMF - 49776U, // VERIMG - 49776U, // VERIMH - 25144U, // VERLL - 56U, // VERLLB - 56U, // VERLLF - 56U, // VERLLG - 56U, // VERLLH - 512U, // VERLLV + 50400U, // VERIM + 50400U, // VERIMB + 50400U, // VERIMF + 50400U, // VERIMG + 50400U, // VERIMH + 50288U, // VERLL + 112U, // VERLLB + 112U, // VERLLF + 112U, // VERLLG + 112U, // VERLLH + 1024U, // VERLLV 0U, // VERLLVB 0U, // VERLLVF 0U, // VERLLVG 0U, // VERLLVH - 25144U, // VESL - 56U, // VESLB - 56U, // VESLF - 56U, // VESLG - 56U, // VESLH - 512U, // VESLV + 50288U, // VESL + 112U, // VESLB + 112U, // VESLF + 112U, // VESLG + 112U, // VESLH + 1024U, // VESLV 0U, // VESLVB 0U, // VESLVF 0U, // VESLVG 0U, // VESLVH - 25144U, // VESRA - 56U, // VESRAB - 56U, // VESRAF - 56U, // VESRAG - 56U, // VESRAH - 512U, // VESRAV + 50288U, // VESRA + 112U, // VESRAB + 112U, // VESRAF + 112U, // VESRAG + 112U, // VESRAH + 1024U, // VESRAV 0U, // VESRAVB 0U, // VESRAVF 0U, // VESRAVG 0U, // VESRAVH - 25144U, // VESRL - 56U, // VESRLB - 56U, // VESRLF - 56U, // VESRLG - 56U, // VESRLH - 512U, // VESRLV + 50288U, // VESRL + 112U, // VESRLB + 112U, // VESRLF + 112U, // VESRLG + 112U, // VESRLH + 1024U, // VESRLV 0U, // VESRLVB 0U, // VESRLVF 0U, // VESRLVG 0U, // VESRLVH - 512U, // VFA + 1024U, // VFA 0U, // VFADB - 512U, // VFAE - 512U, // VFAEB - 512U, // VFAEBS - 512U, // VFAEF - 512U, // VFAEFS - 512U, // VFAEH - 512U, // VFAEHS - 512U, // VFAEZB - 512U, // VFAEZBS - 512U, // VFAEZF - 512U, // VFAEZFS - 512U, // VFAEZH - 512U, // VFAEZHS + 1024U, // VFAE + 1024U, // VFAEB + 1024U, // VFAEBS + 1024U, // VFAEF + 1024U, // VFAEFS + 1024U, // VFAEH + 1024U, // VFAEHS + 1024U, // VFAEZB + 1024U, // VFAEZBS + 1024U, // VFAEZF + 1024U, // VFAEZFS + 1024U, // VFAEZH + 1024U, // VFAEZHS 0U, // VFASB - 512U, // VFCE + 1024U, // VFCE 0U, // VFCEDB 0U, // VFCEDBS 0U, // VFCESB 0U, // VFCESBS - 512U, // VFCH + 1024U, // VFCH 0U, // VFCHDB 0U, // VFCHDBS - 512U, // VFCHE + 1024U, // VFCHE 0U, // VFCHEDB 0U, // VFCHEDBS 0U, // VFCHESB 0U, // VFCHESBS 0U, // VFCHSB 0U, // VFCHSBS - 512U, // VFD + 1024U, // VFD 0U, // VFDDB 0U, // VFDSB - 512U, // VFEE - 512U, // VFEEB + 1024U, // VFEE + 1024U, // VFEEB 0U, // VFEEBS - 512U, // VFEEF + 1024U, // VFEEF 0U, // VFEEFS - 512U, // VFEEH + 1024U, // VFEEH 0U, // VFEEHS 0U, // VFEEZB 0U, // VFEEZBS @@ -7340,12 +8051,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VFEEZFS 0U, // VFEEZH 0U, // VFEEZHS - 512U, // VFENE - 512U, // VFENEB + 1024U, // VFENE + 1024U, // VFENEB 0U, // VFENEBS - 512U, // VFENEF + 1024U, // VFENEF 0U, // VFENEFS - 512U, // VFENEH + 1024U, // VFENEH 0U, // VFENEHS 0U, // VFENEZB 0U, // VFENEZBS @@ -7353,9 +8064,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VFENEZFS 0U, // VFENEZH 0U, // VFENEZHS - 560U, // VFI - 560U, // VFIDB - 560U, // VFISB + 1120U, // VFI + 1120U, // VFIDB + 1120U, // VFISB 0U, // VFKEDB 0U, // VFKEDBS 0U, // VFKESB @@ -7370,210 +8081,233 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VFKHSBS 0U, // VFLCDB 0U, // VFLCSB - 560U, // VFLL + 1120U, // VFLL 0U, // VFLLS 0U, // VFLNDB 0U, // VFLNSB 0U, // VFLPDB 0U, // VFLPSB - 560U, // VFLR - 560U, // VFLRD - 512U, // VFM - 57856U, // VFMA - 57856U, // VFMADB - 57856U, // VFMASB - 512U, // VFMAX - 512U, // VFMAXDB - 512U, // VFMAXSB + 1120U, // VFLR + 1120U, // VFLRD + 1024U, // VFM + 1024U, // VFMA + 1024U, // VFMADB + 1024U, // VFMASB + 1024U, // VFMAX + 1024U, // VFMAXDB + 1024U, // VFMAXSB 0U, // VFMDB - 512U, // VFMIN - 512U, // VFMINDB - 512U, // VFMINSB - 57856U, // VFMS + 1024U, // VFMIN + 1024U, // VFMINDB + 1024U, // VFMINSB + 1024U, // VFMS 0U, // VFMSB - 57856U, // VFMSDB - 57856U, // VFMSSB - 57856U, // VFNMA - 57856U, // VFNMADB - 57856U, // VFNMASB - 57856U, // VFNMS - 57856U, // VFNMSDB - 57856U, // VFNMSSB - 560U, // VFPSO - 48U, // VFPSODB - 48U, // VFPSOSB - 512U, // VFS + 1024U, // VFMSDB + 1024U, // VFMSSB + 1024U, // VFNMA + 1024U, // VFNMADB + 1024U, // VFNMASB + 1024U, // VFNMS + 1024U, // VFNMSDB + 1024U, // VFNMSSB + 1120U, // VFPSO + 96U, // VFPSODB + 96U, // VFPSOSB + 1024U, // VFS 0U, // VFSDB - 560U, // VFSQ + 1120U, // VFSQ 0U, // VFSQDB 0U, // VFSQSB 0U, // VFSSB - 688U, // VFTCI - 176U, // VFTCIDB - 176U, // VFTCISB + 1376U, // VFTCI + 352U, // VFTCIDB + 352U, // VFTCISB 0U, // VGBM - 3U, // VGEF - 4U, // VGEG - 512U, // VGFM - 57856U, // VGFMA - 57856U, // VGFMAB - 57856U, // VGFMAF - 57856U, // VGFMAG - 57856U, // VGFMAH + 8U, // VGEF + 9U, // VGEG + 1024U, // VGFM + 1024U, // VGFMA + 1024U, // VGFMAB + 1024U, // VGFMAF + 1024U, // VGFMAG + 1024U, // VGFMAH 0U, // VGFMB 0U, // VGFMF 0U, // VGFMG 0U, // VGFMH - 36U, // VGM - 44U, // VGMB - 44U, // VGMF - 44U, // VGMG - 44U, // VGMH - 560U, // VISTR - 48U, // VISTRB + 89U, // VGM + 41U, // VGMB + 41U, // VGMF + 41U, // VGMG + 41U, // VGMH + 1120U, // VISTR + 96U, // VISTRB 0U, // VISTRBS - 48U, // VISTRF + 96U, // VISTRF 0U, // VISTRFS - 48U, // VISTRH + 96U, // VISTRH 0U, // VISTRHS 0U, // VL - 104U, // VLBB - 48U, // VLC + 208U, // VLAlign + 208U, // VLBB + 208U, // VLBR + 0U, // VLBRF + 0U, // VLBRG + 0U, // VLBRH + 0U, // VLBRQ + 208U, // VLBRREP + 0U, // VLBRREPF + 0U, // VLBRREPG + 0U, // VLBRREPH + 96U, // VLC 0U, // VLCB 0U, // VLCF 0U, // VLCG 0U, // VLCH - 560U, // VLDE + 1120U, // VLDE 0U, // VLDEB - 160U, // VLEB - 560U, // VLED - 560U, // VLEDB - 184U, // VLEF - 192U, // VLEG - 200U, // VLEH - 128U, // VLEIB - 208U, // VLEIF - 216U, // VLEIG - 224U, // VLEIH - 25144U, // VLGV - 56U, // VLGVB - 56U, // VLGVF - 56U, // VLGVG - 56U, // VLGVH - 48U, // VLIP - 56U, // VLL - 104U, // VLLEZ + 320U, // VLEB + 368U, // VLEBRF + 384U, // VLEBRG + 400U, // VLEBRH + 1120U, // VLED + 1120U, // VLEDB + 368U, // VLEF + 384U, // VLEG + 400U, // VLEH + 256U, // VLEIB + 416U, // VLEIF + 432U, // VLEIG + 448U, // VLEIH + 208U, // VLER + 0U, // VLERF + 0U, // VLERG + 0U, // VLERH + 50288U, // VLGV + 112U, // VLGVB + 112U, // VLGVF + 112U, // VLGVG + 112U, // VLGVH + 96U, // VLIP + 112U, // VLL + 208U, // VLLEBRZ + 0U, // VLLEBRZE + 0U, // VLLEBRZF + 0U, // VLLEBRZG + 0U, // VLLEBRZH + 208U, // VLLEZ 0U, // VLLEZB 0U, // VLLEZF 0U, // VLLEZG 0U, // VLLEZH 0U, // VLLEZLF - 56U, // VLM - 48U, // VLP + 112U, // VLM + 50288U, // VLMAlign + 96U, // VLP 0U, // VLPB 0U, // VLPF 0U, // VLPG 0U, // VLPH 0U, // VLR - 104U, // VLREP + 208U, // VLREP 0U, // VLREPB 0U, // VLREPF 0U, // VLREPG 0U, // VLREPH - 152U, // VLRL - 56U, // VLRLR - 16920U, // VLVG - 24U, // VLVGB - 24U, // VLVGF - 24U, // VLVGG - 24U, // VLVGH + 304U, // VLRL + 112U, // VLRLR + 33856U, // VLVG + 64U, // VLVGB + 64U, // VLVGF + 64U, // VLVGG + 64U, // VLVGH 0U, // VLVGP - 57856U, // VMAE - 57856U, // VMAEB - 57856U, // VMAEF - 57856U, // VMAEH - 57856U, // VMAH - 57856U, // VMAHB - 57856U, // VMAHF - 57856U, // VMAHH - 57856U, // VMAL - 57856U, // VMALB - 57856U, // VMALE - 57856U, // VMALEB - 57856U, // VMALEF - 57856U, // VMALEH - 57856U, // VMALF - 57856U, // VMALH - 57856U, // VMALHB - 57856U, // VMALHF - 57856U, // VMALHH - 57856U, // VMALHW - 57856U, // VMALO - 57856U, // VMALOB - 57856U, // VMALOF - 57856U, // VMALOH - 57856U, // VMAO - 57856U, // VMAOB - 57856U, // VMAOF - 57856U, // VMAOH - 512U, // VME + 1024U, // VMAE + 1024U, // VMAEB + 1024U, // VMAEF + 1024U, // VMAEH + 1024U, // VMAH + 1024U, // VMAHB + 1024U, // VMAHF + 1024U, // VMAHH + 1024U, // VMAL + 1024U, // VMALB + 1024U, // VMALE + 1024U, // VMALEB + 1024U, // VMALEF + 1024U, // VMALEH + 1024U, // VMALF + 1024U, // VMALH + 1024U, // VMALHB + 1024U, // VMALHF + 1024U, // VMALHH + 1024U, // VMALHW + 1024U, // VMALO + 1024U, // VMALOB + 1024U, // VMALOF + 1024U, // VMALOH + 1024U, // VMAO + 1024U, // VMAOB + 1024U, // VMAOF + 1024U, // VMAOH + 1024U, // VME 0U, // VMEB 0U, // VMEF 0U, // VMEH - 512U, // VMH + 1024U, // VMH 0U, // VMHB 0U, // VMHF 0U, // VMHH - 512U, // VML + 1024U, // VML 0U, // VMLB - 512U, // VMLE + 1024U, // VMLE 0U, // VMLEB 0U, // VMLEF 0U, // VMLEH 0U, // VMLF - 512U, // VMLH + 1024U, // VMLH 0U, // VMLHB 0U, // VMLHF 0U, // VMLHH 0U, // VMLHW - 512U, // VMLO + 1024U, // VMLO 0U, // VMLOB 0U, // VMLOF 0U, // VMLOH - 512U, // VMN + 1024U, // VMN 0U, // VMNB 0U, // VMNF 0U, // VMNG 0U, // VMNH - 512U, // VMNL + 1024U, // VMNL 0U, // VMNLB 0U, // VMNLF 0U, // VMNLG 0U, // VMNLH - 512U, // VMO + 1024U, // VMO 0U, // VMOB 0U, // VMOF 0U, // VMOH - 512U, // VMP - 512U, // VMRH + 17408U, // VMP + 1024U, // VMRH 0U, // VMRHB 0U, // VMRHF 0U, // VMRHG 0U, // VMRHH - 512U, // VMRL + 1024U, // VMRL 0U, // VMRLB 0U, // VMRLF 0U, // VMRLG 0U, // VMRLH - 57856U, // VMSL - 57856U, // VMSLG - 512U, // VMSP - 512U, // VMX + 1024U, // VMSL + 1024U, // VMSLG + 17408U, // VMSP + 1024U, // VMX 0U, // VMXB 0U, // VMXF 0U, // VMXG 0U, // VMXH - 512U, // VMXL + 1024U, // VMXL 0U, // VMXLB 0U, // VMXLF 0U, // VMXLG @@ -7586,137 +8320,173 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VO 0U, // VOC 0U, // VONE - 512U, // VPDI - 57856U, // VPERM - 512U, // VPK + 1024U, // VPDI + 1024U, // VPERM + 1024U, // VPK 0U, // VPKF 0U, // VPKG 0U, // VPKH - 512U, // VPKLS + 1024U, // VPKLS 0U, // VPKLSF 0U, // VPKLSFS 0U, // VPKLSG 0U, // VPKLSGS 0U, // VPKLSH 0U, // VPKLSHS - 512U, // VPKS + 1024U, // VPKS 0U, // VPKSF 0U, // VPKSFS 0U, // VPKSG 0U, // VPKSGS 0U, // VPKSH 0U, // VPKSHS - 152U, // VPKZ - 48U, // VPOPCT + 304U, // VPKZ + 17408U, // VPKZR + 96U, // VPOPCT 0U, // VPOPCTB 0U, // VPOPCTF 0U, // VPOPCTG 0U, // VPOPCTH - 4264U, // VPSOP - 744U, // VREP - 232U, // VREPB - 232U, // VREPF - 232U, // VREPG - 232U, // VREPH - 48U, // VREPI + 11600U, // VPSOP + 1488U, // VREP + 464U, // VREPB + 464U, // VREPF + 464U, // VREPG + 464U, // VREPH + 96U, // VREPI 0U, // VREPIB 0U, // VREPIF 0U, // VREPIG 0U, // VREPIH - 512U, // VRP - 512U, // VS + 17408U, // VRP + 1024U, // VS 0U, // VSB - 57856U, // VSBCBI - 57856U, // VSBCBIQ - 57856U, // VSBI - 57856U, // VSBIQ - 512U, // VSCBI + 1024U, // VSBCBI + 1024U, // VSBCBIQ + 1024U, // VSBI + 1024U, // VSBIQ + 1024U, // VSCBI 0U, // VSCBIB 0U, // VSCBIF 0U, // VSCBIG 0U, // VSCBIH 0U, // VSCBIQ - 4U, // VSCEF - 4U, // VSCEG - 512U, // VSDP - 48U, // VSEG + 10U, // VSCEF + 10U, // VSCEG + 1024U, // VSCHDP + 1024U, // VSCHP + 1024U, // VSCHSP + 1024U, // VSCHXP + 0U, // VSCSHP + 17408U, // VSDP + 96U, // VSEG 0U, // VSEGB 0U, // VSEGF 0U, // VSEGH - 57856U, // VSEL + 1024U, // VSEL 0U, // VSF 0U, // VSG 0U, // VSH 0U, // VSL 0U, // VSLB - 512U, // VSLDB - 512U, // VSP + 17408U, // VSLD + 17408U, // VSLDB + 17408U, // VSP 0U, // VSQ 0U, // VSRA 0U, // VSRAB + 17408U, // VSRD 0U, // VSRL 0U, // VSRLB - 4264U, // VSRP + 11600U, // VSRP + 17408U, // VSRPR 0U, // VST - 104U, // VSTEB - 240U, // VSTEF - 248U, // VSTEG - 256U, // VSTEH - 56U, // VSTL - 56U, // VSTM - 57856U, // VSTRC - 57856U, // VSTRCB - 57856U, // VSTRCBS - 57856U, // VSTRCF - 57856U, // VSTRCFS - 57856U, // VSTRCH - 57856U, // VSTRCHS - 57856U, // VSTRCZB - 57856U, // VSTRCZBS - 57856U, // VSTRCZF - 57856U, // VSTRCZFS - 57856U, // VSTRCZH - 57856U, // VSTRCZHS - 152U, // VSTRL - 56U, // VSTRLR - 512U, // VSUM + 208U, // VSTAlign + 208U, // VSTBR + 0U, // VSTBRF + 0U, // VSTBRG + 0U, // VSTBRH + 0U, // VSTBRQ + 208U, // VSTEB + 480U, // VSTEBRF + 496U, // VSTEBRG + 512U, // VSTEBRH + 480U, // VSTEF + 496U, // VSTEG + 512U, // VSTEH + 208U, // VSTER + 0U, // VSTERF + 0U, // VSTERG + 0U, // VSTERH + 112U, // VSTL + 112U, // VSTM + 50288U, // VSTMAlign + 1024U, // VSTRC + 1024U, // VSTRCB + 1024U, // VSTRCBS + 1024U, // VSTRCF + 1024U, // VSTRCFS + 1024U, // VSTRCH + 1024U, // VSTRCHS + 1024U, // VSTRCZB + 1024U, // VSTRCZBS + 1024U, // VSTRCZF + 1024U, // VSTRCZFS + 1024U, // VSTRCZH + 1024U, // VSTRCZHS + 304U, // VSTRL + 112U, // VSTRLR + 1024U, // VSTRS + 1024U, // VSTRSB + 1024U, // VSTRSF + 1024U, // VSTRSH + 1024U, // VSTRSZB + 1024U, // VSTRSZF + 1024U, // VSTRSZH + 1024U, // VSUM 0U, // VSUMB - 512U, // VSUMG + 1024U, // VSUMG 0U, // VSUMGF 0U, // VSUMGH 0U, // VSUMH - 512U, // VSUMQ + 1024U, // VSUMQ 0U, // VSUMQF 0U, // VSUMQG 0U, // VTM 0U, // VTP - 48U, // VUPH + 96U, // VUPH 0U, // VUPHB 0U, // VUPHF 0U, // VUPHH - 152U, // VUPKZ - 48U, // VUPL + 304U, // VUPKZ + 96U, // VUPKZH + 96U, // VUPKZL + 96U, // VUPL 0U, // VUPLB 0U, // VUPLF - 48U, // VUPLH + 96U, // VUPLH 0U, // VUPLHB 0U, // VUPLHF 0U, // VUPLHH 0U, // VUPLHW - 48U, // VUPLL + 96U, // VUPLL 0U, // VUPLLB 0U, // VUPLLF 0U, // VUPLLH 0U, // VX 0U, // VZERO - 560U, // WCDGB - 560U, // WCDLGB - 560U, // WCGDB - 560U, // WCLGDB + 1120U, // WCDGB + 1120U, // WCDLGB + 1120U, // WCEFB + 1120U, // WCELFB + 1120U, // WCFEB + 1120U, // WCGDB + 1120U, // WCLFEB + 1120U, // WCLGDB 0U, // WFADB 0U, // WFASB 0U, // WFAXB - 560U, // WFC + 1120U, // WFC 0U, // WFCDB 0U, // WFCEDB 0U, // WFCEDBS @@ -7741,10 +8511,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // WFDDB 0U, // WFDSB 0U, // WFDXB - 560U, // WFIDB - 560U, // WFISB - 560U, // WFIXB - 560U, // WFK + 1120U, // WFIDB + 1120U, // WFISB + 1120U, // WFIXB + 1120U, // WFK 0U, // WFKDB 0U, // WFKEDB 0U, // WFKEDBS @@ -7777,43 +8547,43 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // WFLPDB 0U, // WFLPSB 0U, // WFLPXB - 560U, // WFLRD - 560U, // WFLRX - 57856U, // WFMADB - 57856U, // WFMASB - 57856U, // WFMAXB - 512U, // WFMAXDB - 512U, // WFMAXSB - 512U, // WFMAXXB + 1120U, // WFLRD + 1120U, // WFLRX + 1024U, // WFMADB + 1024U, // WFMASB + 1024U, // WFMAXB + 1024U, // WFMAXDB + 1024U, // WFMAXSB + 1024U, // WFMAXXB 0U, // WFMDB - 512U, // WFMINDB - 512U, // WFMINSB - 512U, // WFMINXB + 1024U, // WFMINDB + 1024U, // WFMINSB + 1024U, // WFMINXB 0U, // WFMSB - 57856U, // WFMSDB - 57856U, // WFMSSB - 57856U, // WFMSXB + 1024U, // WFMSDB + 1024U, // WFMSSB + 1024U, // WFMSXB 0U, // WFMXB - 57856U, // WFNMADB - 57856U, // WFNMASB - 57856U, // WFNMAXB - 57856U, // WFNMSDB - 57856U, // WFNMSSB - 57856U, // WFNMSXB - 48U, // WFPSODB - 48U, // WFPSOSB - 48U, // WFPSOXB + 1024U, // WFNMADB + 1024U, // WFNMASB + 1024U, // WFNMAXB + 1024U, // WFNMSDB + 1024U, // WFNMSSB + 1024U, // WFNMSXB + 96U, // WFPSODB + 96U, // WFPSOSB + 96U, // WFPSOXB 0U, // WFSDB 0U, // WFSQDB 0U, // WFSQSB 0U, // WFSQXB 0U, // WFSSB 0U, // WFSXB - 176U, // WFTCIDB - 176U, // WFTCISB - 176U, // WFTCIXB + 352U, // WFTCIDB + 352U, // WFTCISB + 352U, // WFTCIXB 0U, // WLDEB - 560U, // WLEDB + 1120U, // WLEDB 0U, // X 0U, // XC 0U, // XG @@ -7833,6 +8603,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) static const uint8_t OpInfo2[] = { 0U, // PHI 0U, // INLINEASM + 0U, // INLINEASM_BR 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL @@ -7844,16 +8615,23 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 0U, // DBG_VALUE + 0U, // DBG_VALUE_LIST + 0U, // DBG_INSTR_REF + 0U, // DBG_PHI 0U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 0U, // BUNDLE 0U, // LIFETIME_START 0U, // LIFETIME_END + 0U, // PSEUDO_PROBE + 0U, // ARITH_FENCE 0U, // STACKMAP 0U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP @@ -7865,6 +8643,11 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // PATCHABLE_EVENT_CALL 0U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL + 0U, // MEMBARRIER + 0U, // JUMP_TABLE_DEBUG_INFO + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ASSERT_ALIGN 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL @@ -7872,6 +8655,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR @@ -7879,17 +8664,33 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE + 0U, // G_CONSTANT_POOL 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_CONSTANT_FOLD_BARRIER + 0U, // G_INTRINSIC_FPTRUNC_ROUND + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD 0U, // G_STORE + 0U, // G_INDEXED_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG @@ -7903,10 +8704,21 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_ATOMICRMW_FMAX + 0U, // G_ATOMICRMW_FMIN + 0U, // G_ATOMICRMW_UINC_WRAP + 0U, // G_ATOMICRMW_UDEC_WRAP + 0U, // G_FENCE + 0U, // G_PREFETCH 0U, // G_BRCOND 0U, // G_BRINDIRECT + 0U, // G_INVOKE_REGION_START 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_INTRINSIC_CONVERGENT + 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT @@ -7914,32 +8726,61 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT + 0U, // G_SEXT_INREG 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT + 0U, // G_UADDO 0U, // G_UADDE + 0U, // G_USUBO 0U, // G_USUBE 0U, // G_SADDO + 0U, // G_SADDE 0U, // G_SSUBO + 0U, // G_SSUBE 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA + 0U, // G_FMAD 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW + 0U, // G_FPOWI 0U, // G_FEXP 0U, // G_FEXP2 + 0U, // G_FEXP10 0U, // G_FLOG 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FLDEXP + 0U, // G_FFREXP 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC @@ -7948,21 +8789,103 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS - 0U, // G_GEP - 0U, // G_PTR_MASK + 0U, // G_FCOPYSIGN + 0U, // G_IS_FPCLASS + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_GET_FPENV + 0U, // G_SET_FPENV + 0U, // G_RESET_FPENV + 0U, // G_GET_FPMODE + 0U, // G_SET_FPMODE + 0U, // G_RESET_FPMODE + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND 0U, // G_BR + 0U, // G_BRJT 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STACKSAVE + 0U, // G_STACKRESTORE + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_STRICT_FLDEXP + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_FMAXIMUM + 0U, // G_VECREDUCE_FMINIMUM + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ADA_ENTRY + 0U, // ADA_ENTRY_VALUE + 0U, // ADB_MemFoldPseudo 0U, // ADJCALLSTACKDOWN 0U, // ADJCALLSTACKUP 0U, // ADJDYNALLOC + 0U, // AEB_MemFoldPseudo 0U, // AEXT128 0U, // AFIMux + 0U, // AG_MemFoldPseudo 0U, // AHIMux 0U, // AHIMuxK + 0U, // ALG_MemFoldPseudo + 0U, // AL_MemFoldPseudo 0U, // ATOMIC_CMP_SWAPW 0U, // ATOMIC_LOADW_AFI 0U, // ATOMIC_LOADW_AR @@ -7979,63 +8902,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // ATOMIC_LOADW_UMIN 0U, // ATOMIC_LOADW_XILF 0U, // ATOMIC_LOADW_XR - 0U, // ATOMIC_LOAD_AFI - 0U, // ATOMIC_LOAD_AGFI - 0U, // ATOMIC_LOAD_AGHI - 0U, // ATOMIC_LOAD_AGR - 0U, // ATOMIC_LOAD_AHI - 0U, // ATOMIC_LOAD_AR - 0U, // ATOMIC_LOAD_MAX_32 - 0U, // ATOMIC_LOAD_MAX_64 - 0U, // ATOMIC_LOAD_MIN_32 - 0U, // ATOMIC_LOAD_MIN_64 - 0U, // ATOMIC_LOAD_NGR - 0U, // ATOMIC_LOAD_NGRi - 0U, // ATOMIC_LOAD_NIHF64 - 0U, // ATOMIC_LOAD_NIHF64i - 0U, // ATOMIC_LOAD_NIHH64 - 0U, // ATOMIC_LOAD_NIHH64i - 0U, // ATOMIC_LOAD_NIHL64 - 0U, // ATOMIC_LOAD_NIHL64i - 0U, // ATOMIC_LOAD_NILF - 0U, // ATOMIC_LOAD_NILF64 - 0U, // ATOMIC_LOAD_NILF64i - 0U, // ATOMIC_LOAD_NILFi - 0U, // ATOMIC_LOAD_NILH - 0U, // ATOMIC_LOAD_NILH64 - 0U, // ATOMIC_LOAD_NILH64i - 0U, // ATOMIC_LOAD_NILHi - 0U, // ATOMIC_LOAD_NILL - 0U, // ATOMIC_LOAD_NILL64 - 0U, // ATOMIC_LOAD_NILL64i - 0U, // ATOMIC_LOAD_NILLi - 0U, // ATOMIC_LOAD_NR - 0U, // ATOMIC_LOAD_NRi - 0U, // ATOMIC_LOAD_OGR - 0U, // ATOMIC_LOAD_OIHF64 - 0U, // ATOMIC_LOAD_OIHH64 - 0U, // ATOMIC_LOAD_OIHL64 - 0U, // ATOMIC_LOAD_OILF - 0U, // ATOMIC_LOAD_OILF64 - 0U, // ATOMIC_LOAD_OILH - 0U, // ATOMIC_LOAD_OILH64 - 0U, // ATOMIC_LOAD_OILL - 0U, // ATOMIC_LOAD_OILL64 - 0U, // ATOMIC_LOAD_OR - 0U, // ATOMIC_LOAD_SGR - 0U, // ATOMIC_LOAD_SR - 0U, // ATOMIC_LOAD_UMAX_32 - 0U, // ATOMIC_LOAD_UMAX_64 - 0U, // ATOMIC_LOAD_UMIN_32 - 0U, // ATOMIC_LOAD_UMIN_64 - 0U, // ATOMIC_LOAD_XGR - 0U, // ATOMIC_LOAD_XIHF64 - 0U, // ATOMIC_LOAD_XILF - 0U, // ATOMIC_LOAD_XILF64 - 0U, // ATOMIC_LOAD_XR 0U, // ATOMIC_SWAPW - 0U, // ATOMIC_SWAP_32 - 0U, // ATOMIC_SWAP_64 + 0U, // A_MemFoldPseudo 0U, // CFIMux 0U, // CGIBCall 0U, // CGIBReturn @@ -8044,8 +8912,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CHIMux 0U, // CIBCall 0U, // CIBReturn - 0U, // CLCLoop - 0U, // CLCSequence + 0U, // CLCImm + 0U, // CLCReg 0U, // CLFIMux 0U, // CLGIBCall 0U, // CLGIBReturn @@ -8061,12 +8929,16 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CRBCall 0U, // CRBReturn 0U, // CallBASR + 0U, // CallBASR_STACKEXT + 0U, // CallBASR_XPLINK64 0U, // CallBCR 0U, // CallBR 0U, // CallBRASL + 0U, // CallBRASL_XPLINK64 0U, // CallBRCL 0U, // CallJG 0U, // CondReturn + 0U, // CondReturn_XPLINK 0U, // CondStore16 0U, // CondStore16Inv 0U, // CondStore16Mux @@ -8086,6 +8958,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // CondStoreF64 0U, // CondStoreF64Inv 0U, // CondTrap + 0U, // DDB_MemFoldPseudo + 0U, // DEB_MemFoldPseudo + 0U, // EXRL_Pseudo 0U, // GOT 0U, // IIFMux 0U, // IIHF64 @@ -8107,20 +8982,33 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LLHMux 0U, // LLHRMux 0U, // LMux + 0U, // LOCG_MemFoldPseudo 0U, // LOCHIMux 0U, // LOCMux + 0U, // LOCMux_MemFoldPseudo 0U, // LOCRMux - 0U, // LRMux - 0U, // LTDBRCompare_VecPseudo - 0U, // LTEBRCompare_VecPseudo - 0U, // LTXBRCompare_VecPseudo + 0U, // LTDBRCompare_Pseudo + 0U, // LTEBRCompare_Pseudo + 0U, // LTXBRCompare_Pseudo 0U, // LX - 0U, // MVCLoop - 0U, // MVCSequence + 0U, // MADB_MemFoldPseudo + 0U, // MAEB_MemFoldPseudo + 0U, // MDB_MemFoldPseudo + 0U, // MEEB_MemFoldPseudo + 0U, // MSC_MemFoldPseudo + 0U, // MSDB_MemFoldPseudo + 0U, // MSEB_MemFoldPseudo + 0U, // MSGC_MemFoldPseudo + 0U, // MVCImm + 0U, // MVCReg 0U, // MVSTLoop - 0U, // MemBarrier - 0U, // NCLoop - 0U, // NCSequence + 0U, // MemsetImmImm + 0U, // MemsetImmReg + 0U, // MemsetRegImm + 0U, // MemsetRegReg + 0U, // NCImm + 0U, // NCReg + 0U, // NG_MemFoldPseudo 0U, // NIFMux 0U, // NIHF64 0U, // NIHH64 @@ -8130,8 +9018,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // NILH64 0U, // NILL64 0U, // NILMux - 0U, // OCLoop - 0U, // OCSequence + 0U, // N_MemFoldPseudo + 0U, // OCImm + 0U, // OCReg + 0U, // OG_MemFoldPseudo 0U, // OIFMux 0U, // OIHF64 0U, // OIHH64 @@ -8141,13 +9031,24 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // OILH64 0U, // OILL64 0U, // OILMux + 0U, // O_MemFoldPseudo 0U, // PAIR128 + 0U, // PROBED_ALLOCA + 0U, // PROBED_STACKALLOC 0U, // RISBHH 0U, // RISBHL 0U, // RISBLH 0U, // RISBLL 0U, // RISBMux 0U, // Return + 0U, // Return_XPLINK + 0U, // SCmp128Hi + 0U, // SDB_MemFoldPseudo + 0U, // SEB_MemFoldPseudo + 0U, // SELRMux + 0U, // SG_MemFoldPseudo + 0U, // SLG_MemFoldPseudo + 0U, // SL_MemFoldPseudo 0U, // SRSTLoop 0U, // ST128 0U, // STCMux @@ -8155,6 +9056,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // STMux 0U, // STOCMux 0U, // STX + 0U, // S_MemFoldPseudo + 0U, // Select128 0U, // Select32 0U, // Select64 0U, // SelectF128 @@ -8174,6 +9077,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // TMLL64 0U, // TMLMux 0U, // Trap + 0U, // UCmp128Hi 0U, // VL32 0U, // VL64 0U, // VLR32 @@ -8181,11 +9085,14 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VLVGP32 0U, // VST32 0U, // VST64 - 0U, // XCLoop - 0U, // XCSequence + 0U, // XCImm + 0U, // XCReg + 0U, // XG_MemFoldPseudo 0U, // XIFMux 0U, // XIHF64 0U, // XILF64 + 0U, // XPLINK_STACKALLOC + 0U, // X_MemFoldPseudo 0U, // ZEXT128 0U, // A 0U, // AD @@ -8925,6 +9832,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // DEB 0U, // DEBR 0U, // DER + 0U, // DFLTCC 0U, // DIAG 0U, // DIDBR 0U, // DIEBR @@ -9016,8 +9924,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // InsnRIS 0U, // InsnRR 0U, // InsnRRE - 0U, // InsnRRF - 0U, // InsnRRS + 1U, // InsnRRF + 5U, // InsnRRS 0U, // InsnRS 0U, // InsnRSE 0U, // InsnRSI @@ -9033,6 +9941,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // InsnSS 0U, // InsnSSE 0U, // InsnSSF + 0U, // InsnVRI + 9U, // InsnVRR + 0U, // InsnVRS + 0U, // InsnVRV + 0U, // InsnVRX + 0U, // InsnVSI 0U, // J 0U, // JAsmE 0U, // JAsmH @@ -9077,6 +9991,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // JGAsmZ 0U, // KDB 0U, // KDBR + 0U, // KDSA 0U, // KDTR 0U, // KEB 0U, // KEBR @@ -9112,6 +10027,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LAXG 0U, // LAY 0U, // LB + 0U, // LBEAR 0U, // LBH 0U, // LBR 0U, // LCBB @@ -9209,7 +10125,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LLILL 0U, // LLZRGF 0U, // LM - 0U, // LMD + 1U, // LMD 0U, // LMG 0U, // LMH 0U, // LMY @@ -9438,6 +10354,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LPR 0U, // LPSW 0U, // LPSWE + 0U, // LPSWEY 0U, // LPTEA 0U, // LPXBR 0U, // LPXR @@ -9456,11 +10373,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LSCTL 0U, // LT 0U, // LTDBR - 0U, // LTDBRCompare 0U, // LTDR 0U, // LTDTR 0U, // LTEBR - 0U, // LTEBRCompare 0U, // LTER 0U, // LTG 0U, // LTGF @@ -9468,7 +10383,6 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LTGR 0U, // LTR 0U, // LTXBR - 0U, // LTXBRCompare 0U, // LTXR 0U, // LTXTR 0U, // LURA @@ -9567,6 +10481,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // MVCLU 0U, // MVCOS 0U, // MVCP + 0U, // MVCRL 0U, // MVCS 0U, // MVCSK 0U, // MVGHI @@ -9595,6 +10510,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // MYR 0U, // N 0U, // NC + 0U, // NCGRK + 0U, // NCRK 0U, // NG 0U, // NGR 0U, // NGRK @@ -9607,12 +10524,22 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // NILH 0U, // NILL 0U, // NIY + 0U, // NNGRK + 0U, // NNPA + 0U, // NNRK + 0U, // NOGRK + 0U, // NOP_bare + 0U, // NORK 0U, // NR 0U, // NRK 0U, // NTSTG + 0U, // NXGRK + 0U, // NXRK 0U, // NY 0U, // O 0U, // OC + 0U, // OCGRK + 0U, // OCRK 0U, // OG 0U, // OGR 0U, // OGRK @@ -9640,8 +10567,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // PGOUT 0U, // PKA 0U, // PKU - 0U, // PLO + 1U, // PLO 0U, // POPCNT + 0U, // POPCNTOpt 0U, // PPA 0U, // PPNO 0U, // PR @@ -9654,24 +10582,27 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // QADTR 0U, // QAXTR 0U, // QCTRI + 0U, // QPACI 0U, // QSI 0U, // RCHP - 2U, // RISBG - 2U, // RISBG32 - 2U, // RISBGN - 2U, // RISBHG - 2U, // RISBLG + 0U, // RDP + 0U, // RDPOpt + 13U, // RISBG + 13U, // RISBG32 + 13U, // RISBGN + 13U, // RISBHG + 13U, // RISBLG 0U, // RLL 0U, // RLLG - 2U, // RNSBG - 2U, // ROSBG + 13U, // RNSBG + 13U, // ROSBG 0U, // RP 0U, // RRBE 0U, // RRBM 0U, // RRDTR 0U, // RRXTR 0U, // RSCH - 2U, // RXSBG + 13U, // RXSBG 0U, // S 0U, // SAC 0U, // SACF @@ -9694,6 +10625,72 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // SE 0U, // SEB 0U, // SEBR + 0U, // SELFHR + 0U, // SELFHRAsm + 0U, // SELFHRAsmE + 0U, // SELFHRAsmH + 0U, // SELFHRAsmHE + 0U, // SELFHRAsmL + 0U, // SELFHRAsmLE + 0U, // SELFHRAsmLH + 0U, // SELFHRAsmM + 0U, // SELFHRAsmNE + 0U, // SELFHRAsmNH + 0U, // SELFHRAsmNHE + 0U, // SELFHRAsmNL + 0U, // SELFHRAsmNLE + 0U, // SELFHRAsmNLH + 0U, // SELFHRAsmNM + 0U, // SELFHRAsmNO + 0U, // SELFHRAsmNP + 0U, // SELFHRAsmNZ + 0U, // SELFHRAsmO + 0U, // SELFHRAsmP + 0U, // SELFHRAsmZ + 0U, // SELGR + 0U, // SELGRAsm + 0U, // SELGRAsmE + 0U, // SELGRAsmH + 0U, // SELGRAsmHE + 0U, // SELGRAsmL + 0U, // SELGRAsmLE + 0U, // SELGRAsmLH + 0U, // SELGRAsmM + 0U, // SELGRAsmNE + 0U, // SELGRAsmNH + 0U, // SELGRAsmNHE + 0U, // SELGRAsmNL + 0U, // SELGRAsmNLE + 0U, // SELGRAsmNLH + 0U, // SELGRAsmNM + 0U, // SELGRAsmNO + 0U, // SELGRAsmNP + 0U, // SELGRAsmNZ + 0U, // SELGRAsmO + 0U, // SELGRAsmP + 0U, // SELGRAsmZ + 0U, // SELR + 0U, // SELRAsm + 0U, // SELRAsmE + 0U, // SELRAsmH + 0U, // SELRAsmHE + 0U, // SELRAsmL + 0U, // SELRAsmLE + 0U, // SELRAsmLH + 0U, // SELRAsmM + 0U, // SELRAsmNE + 0U, // SELRAsmNH + 0U, // SELRAsmNHE + 0U, // SELRAsmNL + 0U, // SELRAsmNLE + 0U, // SELRAsmNLH + 0U, // SELRAsmNM + 0U, // SELRAsmNO + 0U, // SELRAsmNP + 0U, // SELRAsmNZ + 0U, // SELRAsmO + 0U, // SELRAsmP + 0U, // SELRAsmZ 0U, // SER 0U, // SFASR 0U, // SFPC @@ -9737,6 +10734,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // SLRK 0U, // SLXT 0U, // SLY + 0U, // SORTL 0U, // SP 0U, // SPCTR 0U, // SPKA @@ -9781,6 +10779,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // STAM 0U, // STAMY 0U, // STAP + 0U, // STBEAR 0U, // STC 0U, // STCH 0U, // STCK @@ -9963,20 +10962,20 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // UPT 0U, // VA 0U, // VAB - 6U, // VAC + 30U, // VAC 0U, // VACC 0U, // VACCB - 6U, // VACCC - 0U, // VACCCQ + 30U, // VACCC + 2U, // VACCCQ 0U, // VACCF 0U, // VACCG 0U, // VACCH 0U, // VACCQ - 0U, // VACQ + 2U, // VACQ 0U, // VAF 0U, // VAG 0U, // VAH - 7U, // VAP + 30U, // VAP 0U, // VAQ 0U, // VAVG 0U, // VAVGB @@ -9989,11 +10988,13 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VAVGLG 0U, // VAVGLH 0U, // VBPERM - 6U, // VCDG + 28U, // VCDG 0U, // VCDGB - 6U, // VCDLG + 28U, // VCDLG 0U, // VCDLGB - 6U, // VCEQ + 0U, // VCEFB + 0U, // VCELFB + 28U, // VCEQ 0U, // VCEQB 0U, // VCEQBS 0U, // VCEQF @@ -10002,9 +11003,13 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VCEQGS 0U, // VCEQH 0U, // VCEQHS - 6U, // VCGD + 0U, // VCFEB + 0U, // VCFN + 28U, // VCFPL + 28U, // VCFPS + 28U, // VCGD 0U, // VCGDB - 6U, // VCH + 28U, // VCH 0U, // VCHB 0U, // VCHBS 0U, // VCHF @@ -10013,7 +11018,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VCHGS 0U, // VCHH 0U, // VCHHS - 6U, // VCHL + 28U, // VCHL 0U, // VCHLB 0U, // VCHLBS 0U, // VCHLF @@ -10023,14 +11028,23 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VCHLH 0U, // VCHLHS 0U, // VCKSM - 6U, // VCLGD + 0U, // VCLFEB + 0U, // VCLFNH + 0U, // VCLFNL + 28U, // VCLFP + 28U, // VCLGD 0U, // VCLGDB 0U, // VCLZ 0U, // VCLZB + 0U, // VCLZDP 0U, // VCLZF 0U, // VCLZG 0U, // VCLZH + 0U, // VCNF 0U, // VCP + 28U, // VCRNF + 28U, // VCSFP + 0U, // VCSPH 0U, // VCTZ 0U, // VCTZB 0U, // VCTZF @@ -10038,9 +11052,11 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VCTZH 0U, // VCVB 0U, // VCVBG + 0U, // VCVBGOpt + 0U, // VCVBOpt 1U, // VCVD 1U, // VCVDG - 7U, // VDP + 30U, // VDP 0U, // VEC 0U, // VECB 0U, // VECF @@ -10051,11 +11067,11 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VECLF 0U, // VECLG 0U, // VECLH - 10U, // VERIM - 0U, // VERIMB - 0U, // VERIMF - 0U, // VERIMG - 0U, // VERIMH + 45U, // VERIM + 1U, // VERIMB + 1U, // VERIMF + 1U, // VERIMG + 1U, // VERIMH 0U, // VERLL 0U, // VERLLB 0U, // VERLLF @@ -10096,9 +11112,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VESRLVF 0U, // VESRLVG 0U, // VESRLVH - 6U, // VFA + 28U, // VFA 0U, // VFADB - 6U, // VFAE + 28U, // VFAE 0U, // VFAEB 0U, // VFAEBS 0U, // VFAEF @@ -10112,25 +11128,25 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VFAEZH 0U, // VFAEZHS 0U, // VFASB - 22U, // VFCE + 92U, // VFCE 0U, // VFCEDB 0U, // VFCEDBS 0U, // VFCESB 0U, // VFCESBS - 22U, // VFCH + 92U, // VFCH 0U, // VFCHDB 0U, // VFCHDBS - 22U, // VFCHE + 92U, // VFCHE 0U, // VFCHEDB 0U, // VFCHEDBS 0U, // VFCHESB 0U, // VFCHESBS 0U, // VFCHSB 0U, // VFCHSBS - 6U, // VFD + 28U, // VFD 0U, // VFDDB 0U, // VFDSB - 6U, // VFEE + 28U, // VFEE 0U, // VFEEB 0U, // VFEEBS 0U, // VFEEF @@ -10143,7 +11159,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VFEEZFS 0U, // VFEEZH 0U, // VFEEZHS - 6U, // VFENE + 28U, // VFENE 0U, // VFENEB 0U, // VFENEBS 0U, // VFENEF @@ -10156,7 +11172,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VFENEZFS 0U, // VFENEZH 0U, // VFENEZHS - 6U, // VFI + 28U, // VFI 0U, // VFIDB 0U, // VFISB 0U, // VFKEDB @@ -10179,50 +11195,50 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VFLNSB 0U, // VFLPDB 0U, // VFLPSB - 6U, // VFLR + 28U, // VFLR 0U, // VFLRD - 6U, // VFM - 22U, // VFMA - 0U, // VFMADB - 0U, // VFMASB - 22U, // VFMAX + 28U, // VFM + 94U, // VFMA + 2U, // VFMADB + 2U, // VFMASB + 92U, // VFMAX 0U, // VFMAXDB 0U, // VFMAXSB 0U, // VFMDB - 22U, // VFMIN + 92U, // VFMIN 0U, // VFMINDB 0U, // VFMINSB - 22U, // VFMS + 94U, // VFMS 0U, // VFMSB - 0U, // VFMSDB - 0U, // VFMSSB - 22U, // VFNMA - 0U, // VFNMADB - 0U, // VFNMASB - 22U, // VFNMS - 0U, // VFNMSDB - 0U, // VFNMSSB - 6U, // VFPSO + 2U, // VFMSDB + 2U, // VFMSSB + 94U, // VFNMA + 2U, // VFNMADB + 2U, // VFNMASB + 94U, // VFNMS + 2U, // VFNMSDB + 2U, // VFNMSSB + 28U, // VFPSO 0U, // VFPSODB 0U, // VFPSOSB - 6U, // VFS + 28U, // VFS 0U, // VFSDB 0U, // VFSQ 0U, // VFSQDB 0U, // VFSQSB 0U, // VFSSB - 6U, // VFTCI + 28U, // VFTCI 0U, // VFTCIDB 0U, // VFTCISB 0U, // VGBM 0U, // VGEF 0U, // VGEG 0U, // VGFM - 6U, // VGFMA - 0U, // VGFMAB - 0U, // VGFMAF - 0U, // VGFMAG - 0U, // VGFMAH + 30U, // VGFMA + 2U, // VGFMAB + 2U, // VGFMAF + 2U, // VGFMAG + 2U, // VGFMAH 0U, // VGFMB 0U, // VGFMF 0U, // VGFMG @@ -10240,7 +11256,17 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VISTRH 0U, // VISTRHS 0U, // VL + 0U, // VLAlign 0U, // VLBB + 0U, // VLBR + 0U, // VLBRF + 0U, // VLBRG + 0U, // VLBRH + 0U, // VLBRQ + 0U, // VLBRREP + 0U, // VLBRREPF + 0U, // VLBRREPG + 0U, // VLBRREPH 0U, // VLC 0U, // VLCB 0U, // VLCF @@ -10249,7 +11275,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VLDE 0U, // VLDEB 0U, // VLEB - 6U, // VLED + 0U, // VLEBRF + 0U, // VLEBRG + 0U, // VLEBRH + 28U, // VLED 0U, // VLEDB 0U, // VLEF 0U, // VLEG @@ -10258,6 +11287,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VLEIF 0U, // VLEIG 0U, // VLEIH + 0U, // VLER + 0U, // VLERF + 0U, // VLERG + 0U, // VLERH 0U, // VLGV 0U, // VLGVB 0U, // VLGVF @@ -10265,6 +11298,11 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VLGVH 0U, // VLIP 0U, // VLL + 0U, // VLLEBRZ + 0U, // VLLEBRZE + 0U, // VLLEBRZF + 0U, // VLLEBRZG + 0U, // VLLEBRZH 0U, // VLLEZ 0U, // VLLEZB 0U, // VLLEZF @@ -10272,6 +11310,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VLLEZH 0U, // VLLEZLF 0U, // VLM + 0U, // VLMAlign 0U, // VLP 0U, // VLPB 0U, // VLPF @@ -10285,40 +11324,40 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VLREPH 0U, // VLRL 0U, // VLRLR - 1U, // VLVG + 2U, // VLVG 0U, // VLVGB 0U, // VLVGF 0U, // VLVGG 0U, // VLVGH 0U, // VLVGP - 6U, // VMAE - 0U, // VMAEB - 0U, // VMAEF - 0U, // VMAEH - 6U, // VMAH - 0U, // VMAHB - 0U, // VMAHF - 0U, // VMAHH - 6U, // VMAL - 0U, // VMALB - 6U, // VMALE - 0U, // VMALEB - 0U, // VMALEF - 0U, // VMALEH - 0U, // VMALF - 6U, // VMALH - 0U, // VMALHB - 0U, // VMALHF - 0U, // VMALHH - 0U, // VMALHW - 6U, // VMALO - 0U, // VMALOB - 0U, // VMALOF - 0U, // VMALOH - 6U, // VMAO - 0U, // VMAOB - 0U, // VMAOF - 0U, // VMAOH + 30U, // VMAE + 2U, // VMAEB + 2U, // VMAEF + 2U, // VMAEH + 30U, // VMAH + 2U, // VMAHB + 2U, // VMAHF + 2U, // VMAHH + 30U, // VMAL + 2U, // VMALB + 30U, // VMALE + 2U, // VMALEB + 2U, // VMALEF + 2U, // VMALEH + 2U, // VMALF + 30U, // VMALH + 2U, // VMALHB + 2U, // VMALHF + 2U, // VMALHH + 2U, // VMALHW + 30U, // VMALO + 2U, // VMALOB + 2U, // VMALOF + 2U, // VMALOH + 30U, // VMAO + 2U, // VMAOB + 2U, // VMAOF + 2U, // VMAOH 0U, // VME 0U, // VMEB 0U, // VMEF @@ -10357,7 +11396,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VMOB 0U, // VMOF 0U, // VMOH - 7U, // VMP + 30U, // VMP 0U, // VMRH 0U, // VMRHB 0U, // VMRHF @@ -10368,9 +11407,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VMRLF 0U, // VMRLG 0U, // VMRLH - 22U, // VMSL - 6U, // VMSLG - 7U, // VMSP + 94U, // VMSL + 30U, // VMSLG + 30U, // VMSP 0U, // VMX 0U, // VMXB 0U, // VMXF @@ -10390,19 +11429,19 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VOC 0U, // VONE 0U, // VPDI - 0U, // VPERM + 2U, // VPERM 0U, // VPK 0U, // VPKF 0U, // VPKG 0U, // VPKH - 6U, // VPKLS + 28U, // VPKLS 0U, // VPKLSF 0U, // VPKLSFS 0U, // VPKLSG 0U, // VPKLSGS 0U, // VPKLSH 0U, // VPKLSHS - 6U, // VPKS + 28U, // VPKS 0U, // VPKSF 0U, // VPKSFS 0U, // VPKSG @@ -10410,6 +11449,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VPKSH 0U, // VPKSHS 0U, // VPKZ + 30U, // VPKZR 0U, // VPOPCT 0U, // VPOPCTB 0U, // VPOPCTF @@ -10426,13 +11466,13 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VREPIF 0U, // VREPIG 0U, // VREPIH - 7U, // VRP + 30U, // VRP 0U, // VS 0U, // VSB - 6U, // VSBCBI - 0U, // VSBCBIQ - 6U, // VSBI - 0U, // VSBIQ + 30U, // VSBCBI + 2U, // VSBCBIQ + 30U, // VSBI + 2U, // VSBIQ 0U, // VSCBI 0U, // VSCBIB 0U, // VSCBIF @@ -10441,47 +11481,76 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VSCBIQ 0U, // VSCEF 0U, // VSCEG - 7U, // VSDP + 0U, // VSCHDP + 28U, // VSCHP + 0U, // VSCHSP + 0U, // VSCHXP + 0U, // VSCSHP + 30U, // VSDP 0U, // VSEG 0U, // VSEGB 0U, // VSEGF 0U, // VSEGH - 0U, // VSEL + 2U, // VSEL 0U, // VSF 0U, // VSG 0U, // VSH 0U, // VSL 0U, // VSLB - 1U, // VSLDB - 7U, // VSP + 2U, // VSLD + 2U, // VSLDB + 30U, // VSP 0U, // VSQ 0U, // VSRA 0U, // VSRAB + 2U, // VSRD 0U, // VSRL 0U, // VSRLB 0U, // VSRP + 30U, // VSRPR 0U, // VST + 0U, // VSTAlign + 0U, // VSTBR + 0U, // VSTBRF + 0U, // VSTBRG + 0U, // VSTBRH + 0U, // VSTBRQ 0U, // VSTEB + 0U, // VSTEBRF + 0U, // VSTEBRG + 0U, // VSTEBRH 0U, // VSTEF 0U, // VSTEG 0U, // VSTEH + 0U, // VSTER + 0U, // VSTERF + 0U, // VSTERG + 0U, // VSTERH 0U, // VSTL 0U, // VSTM - 22U, // VSTRC - 6U, // VSTRCB - 6U, // VSTRCBS - 6U, // VSTRCF - 6U, // VSTRCFS - 6U, // VSTRCH - 6U, // VSTRCHS - 6U, // VSTRCZB - 6U, // VSTRCZBS - 6U, // VSTRCZF - 6U, // VSTRCZFS - 6U, // VSTRCZH - 6U, // VSTRCZHS + 0U, // VSTMAlign + 94U, // VSTRC + 30U, // VSTRCB + 30U, // VSTRCBS + 30U, // VSTRCF + 30U, // VSTRCFS + 30U, // VSTRCH + 30U, // VSTRCHS + 30U, // VSTRCZB + 30U, // VSTRCZBS + 30U, // VSTRCZF + 30U, // VSTRCZFS + 30U, // VSTRCZH + 30U, // VSTRCZHS 0U, // VSTRL 0U, // VSTRLR + 94U, // VSTRS + 30U, // VSTRSB + 30U, // VSTRSF + 30U, // VSTRSH + 2U, // VSTRSZB + 2U, // VSTRSZF + 2U, // VSTRSZH 0U, // VSUM 0U, // VSUMB 0U, // VSUMG @@ -10498,6 +11567,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VUPHF 0U, // VUPHH 0U, // VUPKZ + 0U, // VUPKZH + 0U, // VUPKZL 0U, // VUPL 0U, // VUPLB 0U, // VUPLF @@ -10514,7 +11585,11 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // VZERO 0U, // WCDGB 0U, // WCDLGB + 0U, // WCEFB + 0U, // WCELFB + 0U, // WCFEB 0U, // WCGDB + 0U, // WCLFEB 0U, // WCLGDB 0U, // WFADB 0U, // WFASB @@ -10582,9 +11657,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // WFLPXB 0U, // WFLRD 0U, // WFLRX - 0U, // WFMADB - 0U, // WFMASB - 0U, // WFMAXB + 2U, // WFMADB + 2U, // WFMASB + 2U, // WFMAXB 0U, // WFMAXDB 0U, // WFMAXSB 0U, // WFMAXXB @@ -10593,16 +11668,16 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // WFMINSB 0U, // WFMINXB 0U, // WFMSB - 0U, // WFMSDB - 0U, // WFMSSB - 0U, // WFMSXB + 2U, // WFMSDB + 2U, // WFMSSB + 2U, // WFMSXB 0U, // WFMXB - 0U, // WFNMADB - 0U, // WFNMASB - 0U, // WFNMAXB - 0U, // WFNMSDB - 0U, // WFNMSSB - 0U, // WFNMSXB + 2U, // WFNMADB + 2U, // WFNMASB + 2U, // WFNMAXB + 2U, // WFNMSDB + 2U, // WFNMSSB + 2U, // WFNMSXB 0U, // WFPSODB 0U, // WFPSOSB 0U, // WFPSOXB @@ -10638,18 +11713,33 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0; Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32; Bits |= (uint64_t)OpInfo2[MCInst_getOpcode(MI)] << 48; - // assert(Bits != 0 && "Cannot print this instruction."); + MnemonicBitsInfo MBI = { #ifndef CAPSTONE_DIET - SStream_concat0(O, AsmStrs+(Bits & 16383)-1); -#endif + AsmStrs+(Bits & 32767)-1, +#else + NULL, +#endif // CAPSTONE_DIET + Bits + }; + return MBI; +} + +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) { + SStream_concat0(O, ""); + MnemonicBitsInfo MnemonicInfo = getMnemonic(MI, O); + + SStream_concat0(O, MnemonicInfo.first); + uint64_t Bits = MnemonicInfo.second; + assert(Bits != 0 && "Cannot print this instruction."); // Fragment 0 encoded into 5 bits for 18 unique commands. - // printf("Fragment 0 = %" PRIu64 "\n", (Bits >> 14) & 31); - switch ((uint32_t)((Bits >> 14) & 31)) { - default: // llvm_unreachable("Invalid command number."); + switch ((Bits >> 15) & 31) { + default: assert(0 && "Invalid command number."); case 0: - // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... + // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... return; break; case 1: @@ -10701,20 +11791,20 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) case 10: // InsnRI, InsnRRE, InsnRRF, InsnRS, InsnRX, InsnS, InsnSI printU32ImmOperand(MI, 0, O); - SStream_concat0(O, ","); + SStream_concat1(O, ','); break; case 11: // InsnRIE, InsnRIL, InsnRILU, InsnRIS, InsnRRS, InsnRSE, InsnRSI, InsnRS... printU48ImmOperand(MI, 0, O); - SStream_concat0(O, ","); + SStream_concat1(O, ','); break; case 12: // J, JAsmE, JAsmH, JAsmHE, JAsmL, JAsmLE, JAsmLH, JAsmM, JAsmNE, JAsmNH,... - printPCRelOperand(MI, 0, O); + printPCRelOperand(MI, Address, 0, O); return; break; case 13: - // KIMD, KLMD, KMAC, PFMF, TRTE, TRTEOpt, TRTRE, TRTREOpt + // KDSA, KIMD, KLMD, KMAC, PFMF, TRTE, TRTEOpt, TRTRE, TRTREOpt printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); @@ -10729,7 +11819,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) return; break; case 15: - // LOCFHR, LOCGHI, LOCGR, LOCHHI, LOCHI, LOCR, STOC, STOCFH, STOCG + // LOCFHR, LOCGHI, LOCGR, LOCHHI, LOCHI, LOCR, SELFHR, SELGR, SELR, STOC,... printCond4Operand(MI, 4, O); SStream_concat0(O, "\t"); printOperand(MI, 0, O); @@ -10752,10 +11842,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) } - // Fragment 1 encoded into 5 bits for 17 unique commands. - // printf("Fragment 1 = %" PRIu64 "\n", (Bits >> 19) & 31); - switch ((uint32_t)((Bits >> 19) & 31)) { - default: // llvm_unreachable("Invalid command number."); + // Fragment 1 encoded into 5 bits for 18 unique commands. + switch ((Bits >> 20) & 31) { + default: assert(0 && "Invalid command number."); case 0: // A, AD, ADB, ADBR, ADR, ADTR, ADTRA, AE, AEB, AEBR, AER, AFI, AG, AGF, ... SStream_concat0(O, ", "); @@ -10781,7 +11870,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; case 5: // BPP, BPRP, BRCAsm, BRCLAsm, PFDRL - printPCRelOperand(MI, 1, O); + printPCRelOperand(MI, Address, 1, O); break; case 6: // BR, BRAsmE, BRAsmH, BRAsmHE, BRAsmL, BRAsmLE, BRAsmLH, BRAsmM, BRAsmNE... @@ -10809,9 +11898,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; case 11: // InsnRR - SStream_concat0(O, ","); + SStream_concat1(O, ','); printOperand(MI, 1, O); - SStream_concat0(O, ","); + SStream_concat1(O, ','); printOperand(MI, 2, O); return; break; @@ -10822,23 +11911,29 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) case 13: // InsnSS printBDRAddrOperand(MI, 1, O); - SStream_concat0(O, ","); + SStream_concat1(O, ','); printBDAddrOperand(MI, 4, O); - SStream_concat0(O, ","); + SStream_concat1(O, ','); printOperand(MI, 6, O); return; break; case 14: - // LOCFHR, LOCGR, LOCR - printOperand(MI, 2, O); + // InsnVRS + printBDAddrOperand(MI, 3, O); + SStream_concat1(O, ','); + printU4ImmOperand(MI, 5, O); return; break; case 15: + // LOCFHR, LOCGR, LOCR, SELFHR, SELGR, SELR + printOperand(MI, 2, O); + break; + case 16: // LOCGHI, LOCHHI, LOCHI printS16ImmOperand(MI, 2, O); return; break; - case 16: + case 17: // NIAI printU4ImmOperand(MI, 1, O); return; @@ -10847,9 +11942,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) // Fragment 2 encoded into 6 bits for 34 unique commands. - // printf("Fragment 2 = %" PRIu64 "\n", (Bits >> 24) & 63); - switch ((uint32_t)((Bits >> 24) & 63)) { - default: // llvm_unreachable("Invalid command number."); + switch ((Bits >> 25) & 63) { + default: assert(0 && "Invalid command number."); case 0: // A, AD, ADB, AE, AEB, AG, AGF, AGH, AH, AHY, AL, ALC, ALCG, ALG, ALGF, ... printBDXAddrOperand(MI, 2, O); @@ -10891,21 +11985,21 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) printBDXAddrOperand(MI, 1, O); break; case 9: - // BCRAsm, BRCAsm, BRCLAsm, CGRT, CLGRT, CLRT, CRT, InsnS, PFDRL, STOC, S... + // BCRAsm, BRCAsm, BRCLAsm, CGRT, CLGRT, CLRT, CRT, InsnS, LOCFHR, LOCGR,... return; break; case 10: - // BPP, BPRP, CGRB, CGRJ, CLGRB, CLGRJ, CLRB, CLRJ, CRB, CRJ + // BPP, BPRP, CGRB, CGRJ, CLGRB, CLGRJ, CLRB, CLRJ, CRB, CRJ, SELFHR, SEL... SStream_concat0(O, ", "); break; case 11: // BRAS, BRASL - printPCRelTLSOperand(MI, 1, O); + printPCRelTLSOperand(MI, Address, 1, O); return; break; case 12: // BRC, BRCL, BRCT, BRCTG, BRCTH - printPCRelOperand(MI, 2, O); + printPCRelOperand(MI, Address, 2, O); return; break; case 13: @@ -10927,7 +12021,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; case 16: // CGFRL, CGHRL, CGRL, CHRL, CLGFRL, CLGHRL, CLGRL, CLHRL, CLRL, CRL, EXR... - printPCRelOperand(MI, 1, O); + printPCRelOperand(MI, Address, 1, O); return; break; case 17: @@ -10945,7 +12039,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; case 20: // CGIJ, CIJ, CLGIJ, CLIJ - printPCRelOperand(MI, 3, O); + printPCRelOperand(MI, Address, 3, O); return; break; case 21: @@ -10993,7 +12087,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; case 30: // InsnRI, InsnRIE, InsnRIL, InsnRILU, InsnRIS, InsnRRE, InsnRRF, InsnRRS... - SStream_concat0(O, ","); + SStream_concat1(O, ','); break; case 31: // PKA, PKU @@ -11013,10 +12107,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) } - // Fragment 3 encoded into 5 bits for 20 unique commands. - // printf("Fragment 3 = %" PRIu64 "\n", (Bits >> 30) & 31); - switch ((uint32_t)((Bits >> 30) & 31)) { - default: // llvm_unreachable("Invalid command number."); + // Fragment 3 encoded into 5 bits for 22 unique commands. + switch ((Bits >> 31) & 31) { + default: assert(0 && "Invalid command number."); case 0: // A, AD, ADB, ADBR, ADR, AE, AEB, AEBR, AER, AG, AGF, AGFR, AGH, AGHI, A... return; @@ -11026,13 +12119,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) SStream_concat0(O, ", "); break; case 2: - // BPP, InsnRX, InsnRXE, InsnRXY - printBDXAddrOperand(MI, 2, O); - return; + // BPP, CGIBAsmE, CGIBAsmH, CGIBAsmHE, CGIBAsmL, CGIBAsmLE, CGIBAsmLH, CG... + printBDAddrOperand(MI, 2, O); break; case 3: // BPRP, CGIJAsmE, CGIJAsmH, CGIJAsmHE, CGIJAsmL, CGIJAsmLE, CGIJAsmLH, C... - printPCRelOperand(MI, 2, O); + printPCRelOperand(MI, Address, 2, O); return; break; case 4: @@ -11045,38 +12137,37 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) SStream_concat0(O, ", "); break; case 6: - // CGIBAsmE, CGIBAsmH, CGIBAsmHE, CGIBAsmL, CGIBAsmLE, CGIBAsmLH, CGIBAsm... - printBDAddrOperand(MI, 2, O); - return; - break; - case 7: // CGRB, CLGRB, CLRB, CRB, InsnSSE, InsnSSF printBDAddrOperand(MI, 3, O); break; - case 8: + case 7: // CGRJ, CLGRJ, CLRJ, CRJ - printPCRelOperand(MI, 3, O); + printPCRelOperand(MI, Address, 3, O); return; break; - case 9: + case 8: // InsnRI printS16ImmOperand(MI, 2, O); return; break; - case 10: + case 9: // InsnRILU printU32ImmOperand(MI, 2, O); return; break; - case 11: + case 10: // InsnRIS printS8ImmOperand(MI, 2, O); - SStream_concat0(O, ","); + SStream_concat1(O, ','); printU4ImmOperand(MI, 3, O); - SStream_concat0(O, ","); + SStream_concat1(O, ','); printBDAddrOperand(MI, 4, O); return; break; + case 11: + // InsnRX, InsnRXE, InsnRXY, InsnVRX + printBDXAddrOperand(MI, 2, O); + break; case 12: // InsnSI printS8ImmOperand(MI, 3, O); @@ -11093,25 +12184,37 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) return; break; case 15: + // InsnVRV + printBDVAddrOperand(MI, 2, O); + SStream_concat1(O, ','); + printU4ImmOperand(MI, 5, O); + return; + break; + case 16: + // SELFHR, SELGR, SELR + printOperand(MI, 1, O); + return; + break; + case 17: // VGEF printU2ImmOperand(MI, 5, O); return; break; - case 16: + case 18: // VGEG printU1ImmOperand(MI, 5, O); return; break; - case 17: + case 19: // VGM, VGMB, VGMF, VGMG, VGMH printU8ImmOperand(MI, 2, O); break; - case 18: + case 20: // VSCEF printU2ImmOperand(MI, 4, O); return; break; - case 19: + case 21: // VSCEG printU1ImmOperand(MI, 4, O); return; @@ -11120,9 +12223,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) // Fragment 4 encoded into 6 bits for 33 unique commands. - // printf("Fragment 4 = %" PRIu64 "\n", (Bits >> 35) & 63); - switch ((uint32_t)((Bits >> 35) & 63)) { - default: // llvm_unreachable("Invalid command number."); + switch ((Bits >> 36) & 63) { + default: assert(0 && "Invalid command number."); case 0: // ADTR, ADTRA, AGRK, AHHHR, AHHLR, ALGRK, ALHHHR, ALHHLR, ALRK, ARK, AXT... printOperand(MI, 2, O); @@ -11133,24 +12235,24 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) return; break; case 2: - // BRXH, BRXHG, BRXLE, BRXLG, CGIJAsm, CIJAsm, CLGIJAsm, CLIJAsm - printPCRelOperand(MI, 3, O); + // BPP, CFDBR, CFDR, CFEBR, CFER, CFXBR, CFXR, CGDBR, CGDR, CGDTR, CGEBR,... return; break; case 3: + // BRXH, BRXHG, BRXLE, BRXLG, CGIJAsm, CIJAsm, CLGIJAsm, CLIJAsm + printPCRelOperand(MI, Address, 3, O); + return; + break; + case 4: // BXH, BXHG, BXLE, BXLEG, CDS, CDSG, CDSY, CGIBAsm, CIBAsm, CLGIBAsm, CL... printBDAddrOperand(MI, 3, O); break; - case 4: + case 5: // CDFBRA, CDFTR, CDGBRA, CDGTRA, CDLFBR, CDLFTR, CDLGBR, CDLGTR, CEFBRA,... SStream_concat0(O, ", "); printU4ImmOperand(MI, 3, O); return; break; - case 5: - // CFDBR, CFDR, CFEBR, CFER, CFXBR, CFXR, CGDBR, CGDR, CGDTR, CGEBR, CGER... - return; - break; case 6: // CGITAsm, CGRBAsm, CGRJAsm, CGRTAsm, CITAsm, CLFITAsm, CLGITAsm, CLGRBA... printU4ImmOperand(MI, 2, O); @@ -11161,7 +12263,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; case 8: // CGRJAsmE, CGRJAsmH, CGRJAsmHE, CGRJAsmL, CGRJAsmLE, CGRJAsmLH, CGRJAsm... - printPCRelOperand(MI, 2, O); + printPCRelOperand(MI, Address, 2, O); return; break; case 9: @@ -11179,7 +12281,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) printOperand(MI, 1, O); break; case 12: - // CSST, ECTG, MVCOS + // CSST, DFLTCC, ECTG, MVCOS printOperand(MI, 4, O); return; break; @@ -11194,7 +12296,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; case 15: // InsnRIE, InsnRRF, InsnRRS, InsnRS, InsnRSE, InsnRSI, InsnRSY, InsnRXF,... - SStream_concat0(O, ","); + SStream_concat1(O, ','); break; case 16: // LOCFHRAsm, LOCGHIAsm, LOCGRAsm, LOCHHIAsm, LOCHIAsm, LOCRAsm, STOCAsm,... @@ -11230,17 +12332,17 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) printU12ImmOperand(MI, 2, O); break; case 23: - // VLEF + // VLEBRF, VLEF printU2ImmOperand(MI, 5, O); return; break; case 24: - // VLEG + // VLEBRG, VLEG printU1ImmOperand(MI, 5, O); return; break; case 25: - // VLEH + // VLEBRH, VLEH printU3ImmOperand(MI, 5, O); return; break; @@ -11264,27 +12366,26 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) printU16ImmOperand(MI, 2, O); break; case 30: - // VSTEF + // VSTEBRF, VSTEF printU2ImmOperand(MI, 4, O); return; break; case 31: - // VSTEG + // VSTEBRG, VSTEG printU1ImmOperand(MI, 4, O); return; break; case 32: - // VSTEH + // VSTEBRH, VSTEH printU3ImmOperand(MI, 4, O); return; break; } - // Fragment 5 encoded into 4 bits for 9 unique commands. - // printf("Fragment 5 = %" PRIu64 "\n", (Bits >> 41) & 15); - switch ((uint32_t)((Bits >> 41) & 15)) { - default: // llvm_unreachable("Invalid command number."); + // Fragment 5 encoded into 4 bits for 12 unique commands. + switch ((Bits >> 42) & 15) { + default: assert(0 && "Invalid command number."); case 0: // ADTR, AGRK, AHHHR, AHHLR, ALGRK, ALHHHR, ALHHLR, ALRK, ARK, AXTR, BXH,... return; @@ -11295,15 +12396,14 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; case 2: // InsnRIE, InsnRSI - printPCRelOperand(MI, 3, O); + printPCRelOperand(MI, Address, 3, O); return; break; case 3: - // InsnRRF + // InsnRRF, InsnVRR printOperand(MI, 3, O); - SStream_concat0(O, ","); + SStream_concat1(O, ','); printU4ImmOperand(MI, 4, O); - return; break; case 4: // InsnRRS, VCVD, VCVDG @@ -11325,6 +12425,25 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) return; break; case 8: + // InsnVRI + printU12ImmOperand(MI, 3, O); + SStream_concat1(O, ','); + printU4ImmOperand(MI, 4, O); + SStream_concat1(O, ','); + printU4ImmOperand(MI, 5, O); + return; + break; + case 9: + // InsnVRX + printU4ImmOperand(MI, 5, O); + return; + break; + case 10: + // InsnVSI + printU8ImmOperand(MI, 4, O); + return; + break; + case 11: // VPSOP, VSRP printU8ImmOperand(MI, 3, O); SStream_concat0(O, ", "); @@ -11335,11 +12454,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) // Fragment 6 encoded into 4 bits for 11 unique commands. - // printf("Fragment 6 = %" PRIu64 "\n", (Bits >> 45) & 15); - switch ((uint32_t)((Bits >> 45) & 15)) { - default: // llvm_unreachable("Invalid command number."); + switch ((Bits >> 46) & 15) { + default: assert(0 && "Invalid command number."); case 0: - // ADTRA, AXTRA, CRDTE, DDTRA, DXTRA, IDTE, IPTE, MDTRA, MXTRA, SDTRA, SX... + // ADTRA, AXTRA, CRDTE, DDTRA, DXTRA, IDTE, IPTE, MDTRA, MXTRA, RDP, SDTR... printU4ImmOperand(MI, 3, O); break; case 1: @@ -11349,7 +12467,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; case 2: // CGRJAsm, CLGRJAsm, CLRJAsm, CRJAsm - printPCRelOperand(MI, 3, O); + printPCRelOperand(MI, Address, 3, O); return; break; case 3: @@ -11358,31 +12476,29 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) return; break; case 4: - // InsnRRS - SStream_concat0(O, ","); - printBDAddrOperand(MI, 4, O); + // InsnRRF, VCVD, VCVDG return; break; case 5: + // InsnRRS, InsnVRR + SStream_concat1(O, ','); + break; + case 6: // LMD, PLO printBDAddrOperand(MI, 4, O); return; break; - case 6: + case 7: // RISBG, RISBG32, RISBGN, RISBHG, RISBLG, RNSBG, ROSBG, RXSBG, VERIM, VE... printU8ImmOperand(MI, 4, O); break; - case 7: + case 8: // VAC, VACCC, VACCCQ, VACQ, VFMA, VFMADB, VFMASB, VFMS, VFMSDB, VFMSSB, ... printOperand(MI, 3, O); break; - case 8: - // VAP, VDP, VMP, VMSP, VRP, VSDP, VSLDB, VSP - printU8ImmOperand(MI, 3, O); - break; case 9: - // VCVD, VCVDG - return; + // VAP, VDP, VMP, VMSP, VPKZR, VRP, VSDP, VSLD, VSLDB, VSP, VSRD, VSRPR + printU8ImmOperand(MI, 3, O); break; case 10: // VLVG @@ -11392,28 +12508,42 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) } - // Fragment 7 encoded into 1 bits for 2 unique commands. - // printf("Fragment 7 = %" PRIu64 "\n", (Bits >> 49) & 1); - if ((Bits >> 49) & 1) { + // Fragment 7 encoded into 2 bits for 4 unique commands. + switch ((Bits >> 50) & 3) { + default: assert(0 && "Invalid command number."); + case 0: + // ADTRA, AXTRA, CRDTE, DDTRA, DXTRA, IDTE, IPTE, MDTRA, MXTRA, RDP, SDTR... + return; + break; + case 1: + // InsnRRS + printBDAddrOperand(MI, 4, O); + return; + break; + case 2: + // InsnVRR + printU4ImmOperand(MI, 5, O); + SStream_concat1(O, ','); + printU4ImmOperand(MI, 6, O); + return; + break; + case 3: // RISBG, RISBG32, RISBGN, RISBHG, RISBLG, RNSBG, ROSBG, RXSBG, VAC, VACC... SStream_concat0(O, ", "); - } else { - // ADTRA, AXTRA, CRDTE, DDTRA, DXTRA, IDTE, IPTE, MDTRA, MXTRA, SDTRA, SX... - return; + break; } // Fragment 8 encoded into 2 bits for 3 unique commands. - // printf("Fragment 8 = %" PRIu64 "\n", (Bits >> 50) & 3); - switch ((uint32_t)((Bits >> 50) & 3)) { - default: // llvm_unreachable("Invalid command number."); + switch ((Bits >> 52) & 3) { + default: assert(0 && "Invalid command number."); case 0: // RISBG, RISBG32, RISBGN, RISBHG, RISBLG, RNSBG, ROSBG, RXSBG - printU6ImmOperand(MI, 5, O); + printU8ImmOperand(MI, 5, O); return; break; case 1: - // VAC, VACCC, VAP, VCDG, VCDLG, VCEQ, VCGD, VCH, VCHL, VCLGD, VDP, VFA, ... + // VAC, VACCC, VAP, VCDG, VCDLG, VCEQ, VCFPL, VCFPS, VCGD, VCH, VCHL, VCL... printU4ImmOperand(MI, 4, O); break; case 2: @@ -11425,14 +12555,13 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) // Fragment 9 encoded into 1 bits for 2 unique commands. - // printf("Fragment 9 = %" PRIu64 "\n", (Bits >> 52) & 1); - if ((Bits >> 52) & 1) { - // VFCE, VFCH, VFCHE, VFMA, VFMAX, VFMIN, VFMS, VFNMA, VFNMS, VMSL, VSTRC + if ((Bits >> 54) & 1) { + // VFCE, VFCH, VFCHE, VFMA, VFMAX, VFMIN, VFMS, VFNMA, VFNMS, VMSL, VSTRC... SStream_concat0(O, ", "); printU4ImmOperand(MI, 5, O); return; } else { - // VAC, VACCC, VAP, VCDG, VCDLG, VCEQ, VCGD, VCH, VCHL, VCLGD, VDP, VFA, ... + // VAC, VACCC, VAP, VCDG, VCDLG, VCEQ, VCFPL, VCFPS, VCGD, VCH, VCHL, VCL... return; } @@ -11442,134 +12571,622 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. -static const char *getRegisterName(unsigned RegNo) -{ - // assert(RegNo && RegNo < 194 && "Invalid register number!"); - +static const char *getRegisterName(unsigned RegNo) { #ifndef CAPSTONE_DIET - static const char AsmStrs[] = { - /* 0 */ 'a', '1', '0', 0, - /* 4 */ 'c', '1', '0', 0, - /* 8 */ 'f', '1', '0', 0, - /* 12 */ 'r', '1', '0', 0, - /* 16 */ 'v', '1', '0', 0, - /* 20 */ 'v', '2', '0', 0, - /* 24 */ 'v', '3', '0', 0, - /* 28 */ 'a', '0', 0, - /* 31 */ 'c', '0', 0, - /* 34 */ 'f', '0', 0, - /* 37 */ 'r', '0', 0, - /* 40 */ 'v', '0', 0, - /* 43 */ 'a', '1', '1', 0, - /* 47 */ 'c', '1', '1', 0, - /* 51 */ 'f', '1', '1', 0, - /* 55 */ 'r', '1', '1', 0, - /* 59 */ 'v', '1', '1', 0, - /* 63 */ 'v', '2', '1', 0, - /* 67 */ 'v', '3', '1', 0, - /* 71 */ 'a', '1', 0, - /* 74 */ 'c', '1', 0, - /* 77 */ 'f', '1', 0, - /* 80 */ 'r', '1', 0, - /* 83 */ 'v', '1', 0, - /* 86 */ 'a', '1', '2', 0, - /* 90 */ 'c', '1', '2', 0, - /* 94 */ 'f', '1', '2', 0, - /* 98 */ 'r', '1', '2', 0, - /* 102 */ 'v', '1', '2', 0, - /* 106 */ 'v', '2', '2', 0, - /* 110 */ 'a', '2', 0, - /* 113 */ 'c', '2', 0, - /* 116 */ 'f', '2', 0, - /* 119 */ 'r', '2', 0, - /* 122 */ 'v', '2', 0, - /* 125 */ 'a', '1', '3', 0, - /* 129 */ 'c', '1', '3', 0, - /* 133 */ 'f', '1', '3', 0, - /* 137 */ 'r', '1', '3', 0, - /* 141 */ 'v', '1', '3', 0, - /* 145 */ 'v', '2', '3', 0, - /* 149 */ 'a', '3', 0, - /* 152 */ 'c', '3', 0, - /* 155 */ 'f', '3', 0, - /* 158 */ 'r', '3', 0, - /* 161 */ 'v', '3', 0, - /* 164 */ 'a', '1', '4', 0, - /* 168 */ 'c', '1', '4', 0, - /* 172 */ 'f', '1', '4', 0, - /* 176 */ 'r', '1', '4', 0, - /* 180 */ 'v', '1', '4', 0, - /* 184 */ 'v', '2', '4', 0, - /* 188 */ 'a', '4', 0, - /* 191 */ 'c', '4', 0, - /* 194 */ 'f', '4', 0, - /* 197 */ 'r', '4', 0, - /* 200 */ 'v', '4', 0, - /* 203 */ 'a', '1', '5', 0, - /* 207 */ 'c', '1', '5', 0, - /* 211 */ 'f', '1', '5', 0, - /* 215 */ 'r', '1', '5', 0, - /* 219 */ 'v', '1', '5', 0, - /* 223 */ 'v', '2', '5', 0, - /* 227 */ 'a', '5', 0, - /* 230 */ 'c', '5', 0, - /* 233 */ 'f', '5', 0, - /* 236 */ 'r', '5', 0, - /* 239 */ 'v', '5', 0, - /* 242 */ 'v', '1', '6', 0, - /* 246 */ 'v', '2', '6', 0, - /* 250 */ 'a', '6', 0, - /* 253 */ 'c', '6', 0, - /* 256 */ 'f', '6', 0, - /* 259 */ 'r', '6', 0, - /* 262 */ 'v', '6', 0, - /* 265 */ 'v', '1', '7', 0, - /* 269 */ 'v', '2', '7', 0, - /* 273 */ 'a', '7', 0, - /* 276 */ 'c', '7', 0, - /* 279 */ 'f', '7', 0, - /* 282 */ 'r', '7', 0, - /* 285 */ 'v', '7', 0, - /* 288 */ 'v', '1', '8', 0, - /* 292 */ 'v', '2', '8', 0, - /* 296 */ 'a', '8', 0, - /* 299 */ 'c', '8', 0, - /* 302 */ 'f', '8', 0, - /* 305 */ 'r', '8', 0, - /* 308 */ 'v', '8', 0, - /* 311 */ 'v', '1', '9', 0, - /* 315 */ 'v', '2', '9', 0, - /* 319 */ 'a', '9', 0, - /* 322 */ 'c', '9', 0, - /* 325 */ 'f', '9', 0, - /* 328 */ 'r', '9', 0, - /* 331 */ 'v', '9', 0, - /* 334 */ 'c', 'c', 0, - }; + assert(RegNo && RegNo < 195 && "Invalid register number!"); + static const char AsmStrs[] = { + /* 0 */ "a10\0" + /* 4 */ "c10\0" + /* 8 */ "f10\0" + /* 12 */ "r10\0" + /* 16 */ "v10\0" + /* 20 */ "v20\0" + /* 24 */ "v30\0" + /* 28 */ "a0\0" + /* 31 */ "c0\0" + /* 34 */ "f0\0" + /* 37 */ "r0\0" + /* 40 */ "v0\0" + /* 43 */ "a11\0" + /* 47 */ "c11\0" + /* 51 */ "f11\0" + /* 55 */ "r11\0" + /* 59 */ "v11\0" + /* 63 */ "v21\0" + /* 67 */ "v31\0" + /* 71 */ "a1\0" + /* 74 */ "c1\0" + /* 77 */ "f1\0" + /* 80 */ "r1\0" + /* 83 */ "v1\0" + /* 86 */ "a12\0" + /* 90 */ "c12\0" + /* 94 */ "f12\0" + /* 98 */ "r12\0" + /* 102 */ "v12\0" + /* 106 */ "v22\0" + /* 110 */ "a2\0" + /* 113 */ "c2\0" + /* 116 */ "f2\0" + /* 119 */ "r2\0" + /* 122 */ "v2\0" + /* 125 */ "a13\0" + /* 129 */ "c13\0" + /* 133 */ "f13\0" + /* 137 */ "r13\0" + /* 141 */ "v13\0" + /* 145 */ "v23\0" + /* 149 */ "a3\0" + /* 152 */ "c3\0" + /* 155 */ "f3\0" + /* 158 */ "r3\0" + /* 161 */ "v3\0" + /* 164 */ "a14\0" + /* 168 */ "c14\0" + /* 172 */ "f14\0" + /* 176 */ "r14\0" + /* 180 */ "v14\0" + /* 184 */ "v24\0" + /* 188 */ "a4\0" + /* 191 */ "c4\0" + /* 194 */ "f4\0" + /* 197 */ "r4\0" + /* 200 */ "v4\0" + /* 203 */ "a15\0" + /* 207 */ "c15\0" + /* 211 */ "f15\0" + /* 215 */ "r15\0" + /* 219 */ "v15\0" + /* 223 */ "v25\0" + /* 227 */ "a5\0" + /* 230 */ "c5\0" + /* 233 */ "f5\0" + /* 236 */ "r5\0" + /* 239 */ "v5\0" + /* 242 */ "v16\0" + /* 246 */ "v26\0" + /* 250 */ "a6\0" + /* 253 */ "c6\0" + /* 256 */ "f6\0" + /* 259 */ "r6\0" + /* 262 */ "v6\0" + /* 265 */ "v17\0" + /* 269 */ "v27\0" + /* 273 */ "a7\0" + /* 276 */ "c7\0" + /* 279 */ "f7\0" + /* 282 */ "r7\0" + /* 285 */ "v7\0" + /* 288 */ "v18\0" + /* 292 */ "v28\0" + /* 296 */ "a8\0" + /* 299 */ "c8\0" + /* 302 */ "f8\0" + /* 305 */ "r8\0" + /* 308 */ "v8\0" + /* 311 */ "v19\0" + /* 315 */ "v29\0" + /* 319 */ "a9\0" + /* 322 */ "c9\0" + /* 325 */ "f9\0" + /* 328 */ "r9\0" + /* 331 */ "v9\0" + /* 334 */ "cc\0" + /* 337 */ "fpc\0" +}; static const uint16_t RegAsmOffset[] = { - 334, 28, 71, 110, 149, 188, 227, 250, 273, 296, 319, 0, 43, 86, - 125, 164, 203, 31, 74, 113, 152, 191, 230, 253, 276, 299, 322, 4, - 47, 90, 129, 168, 207, 40, 83, 122, 161, 200, 239, 262, 285, 308, - 331, 16, 59, 102, 141, 180, 219, 242, 265, 288, 311, 20, 63, 106, - 145, 184, 223, 246, 269, 292, 315, 24, 67, 34, 77, 116, 155, 194, - 233, 256, 279, 302, 325, 8, 51, 94, 133, 172, 211, 242, 265, 288, - 311, 20, 63, 106, 145, 184, 223, 246, 269, 292, 315, 24, 67, 34, - 77, 194, 233, 302, 325, 94, 133, 34, 77, 116, 155, 194, 233, 256, - 279, 302, 325, 8, 51, 94, 133, 172, 211, 242, 265, 288, 311, 20, - 63, 106, 145, 184, 223, 246, 269, 292, 315, 24, 67, 37, 80, 119, - 158, 197, 236, 259, 282, 305, 328, 12, 55, 98, 137, 176, 215, 37, - 80, 119, 158, 197, 236, 259, 282, 305, 328, 12, 55, 98, 137, 176, - 215, 37, 80, 119, 158, 197, 236, 259, 282, 305, 328, 12, 55, 98, - 137, 176, 215, 37, 119, 197, 259, 305, 12, 98, 176, + 334, 337, 28, 71, 110, 149, 188, 227, 250, 273, 296, 319, 0, 43, + 86, 125, 164, 203, 31, 74, 113, 152, 191, 230, 253, 276, 299, 322, + 4, 47, 90, 129, 168, 207, 40, 83, 122, 161, 200, 239, 262, 285, + 308, 331, 16, 59, 102, 141, 180, 219, 242, 265, 288, 311, 20, 63, + 106, 145, 184, 223, 246, 269, 292, 315, 24, 67, 34, 77, 116, 155, + 194, 233, 256, 279, 302, 325, 8, 51, 94, 133, 172, 211, 242, 265, + 288, 311, 20, 63, 106, 145, 184, 223, 246, 269, 292, 315, 24, 67, + 34, 77, 194, 233, 302, 325, 94, 133, 34, 77, 116, 155, 194, 233, + 256, 279, 302, 325, 8, 51, 94, 133, 172, 211, 242, 265, 288, 311, + 20, 63, 106, 145, 184, 223, 246, 269, 292, 315, 24, 67, 37, 80, + 119, 158, 197, 236, 259, 282, 305, 328, 12, 55, 98, 137, 176, 215, + 37, 80, 119, 158, 197, 236, 259, 282, 305, 328, 12, 55, 98, 137, + 176, 215, 37, 80, 119, 158, 197, 236, 259, 282, 305, 328, 12, 55, + 98, 137, 176, 215, 37, 119, 197, 259, 305, 12, 98, 176, }; - //int i; - //for (i = 0; i < sizeof(RegAsmOffset); i++) - // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); - //printf("*************************\n"); + assert (*(AsmStrs+RegAsmOffset[RegNo-1]) && + "Invalid alt name index for register!"); return AsmStrs+RegAsmOffset[RegNo-1]; #else return NULL; +#endif // CAPSTONE_DIET +} +#ifdef PRINT_ALIAS_INSTR +#undef PRINT_ALIAS_INSTR + +static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) { +#ifndef CAPSTONE_DIET + static const PatternsForOpcode OpToPatterns[] = { + {SystemZ_VFAE, 0, 1 }, + {SystemZ_VFAEB, 1, 1 }, + {SystemZ_VFAEBS, 2, 1 }, + {SystemZ_VFAEF, 3, 1 }, + {SystemZ_VFAEFS, 4, 1 }, + {SystemZ_VFAEH, 5, 1 }, + {SystemZ_VFAEHS, 6, 1 }, + {SystemZ_VFAEZB, 7, 1 }, + {SystemZ_VFAEZBS, 8, 1 }, + {SystemZ_VFAEZF, 9, 1 }, + {SystemZ_VFAEZFS, 10, 1 }, + {SystemZ_VFAEZH, 11, 1 }, + {SystemZ_VFAEZHS, 12, 1 }, + {SystemZ_VFEE, 13, 1 }, + {SystemZ_VFEEB, 14, 1 }, + {SystemZ_VFEEF, 15, 1 }, + {SystemZ_VFEEH, 16, 1 }, + {SystemZ_VFENE, 17, 1 }, + {SystemZ_VFENEB, 18, 1 }, + {SystemZ_VFENEF, 19, 1 }, + {SystemZ_VFENEH, 20, 1 }, + {SystemZ_VISTR, 21, 1 }, + {SystemZ_VISTRB, 22, 1 }, + {SystemZ_VISTRF, 23, 1 }, + {SystemZ_VISTRH, 24, 1 }, + {SystemZ_VSTRC, 25, 1 }, + {SystemZ_VSTRCB, 26, 1 }, + {SystemZ_VSTRCBS, 27, 1 }, + {SystemZ_VSTRCF, 28, 1 }, + {SystemZ_VSTRCFS, 29, 1 }, + {SystemZ_VSTRCH, 30, 1 }, + {SystemZ_VSTRCHS, 31, 1 }, + {SystemZ_VSTRCZB, 32, 1 }, + {SystemZ_VSTRCZBS, 33, 1 }, + {SystemZ_VSTRCZF, 34, 1 }, + {SystemZ_VSTRCZFS, 35, 1 }, + {SystemZ_VSTRCZH, 36, 1 }, + {SystemZ_VSTRCZHS, 37, 1 }, + {SystemZ_VSTRS, 38, 1 }, + {SystemZ_VSTRSB, 39, 1 }, + {SystemZ_VSTRSF, 40, 1 }, + {SystemZ_VSTRSH, 41, 1 }, + {0}, }; + + static const AliasPattern Patterns[] = { + // SystemZ_VFAE - 0 + {0, 0, 5, 5 }, + // SystemZ_VFAEB - 1 + {22, 5, 4, 4 }, + // SystemZ_VFAEBS - 2 + {39, 9, 4, 4 }, + // SystemZ_VFAEF - 3 + {57, 13, 4, 4 }, + // SystemZ_VFAEFS - 4 + {74, 17, 4, 4 }, + // SystemZ_VFAEH - 5 + {92, 21, 4, 4 }, + // SystemZ_VFAEHS - 6 + {109, 25, 4, 4 }, + // SystemZ_VFAEZB - 7 + {127, 29, 4, 4 }, + // SystemZ_VFAEZBS - 8 + {145, 33, 4, 4 }, + // SystemZ_VFAEZF - 9 + {164, 37, 4, 4 }, + // SystemZ_VFAEZFS - 10 + {182, 41, 4, 4 }, + // SystemZ_VFAEZH - 11 + {201, 45, 4, 4 }, + // SystemZ_VFAEZHS - 12 + {219, 49, 4, 4 }, + // SystemZ_VFEE - 13 + {238, 53, 5, 5 }, + // SystemZ_VFEEB - 14 + {260, 58, 4, 4 }, + // SystemZ_VFEEF - 15 + {277, 62, 4, 4 }, + // SystemZ_VFEEH - 16 + {294, 66, 4, 4 }, + // SystemZ_VFENE - 17 + {311, 70, 5, 5 }, + // SystemZ_VFENEB - 18 + {334, 75, 4, 4 }, + // SystemZ_VFENEF - 19 + {352, 79, 4, 4 }, + // SystemZ_VFENEH - 20 + {370, 83, 4, 4 }, + // SystemZ_VISTR - 21 + {388, 87, 4, 4 }, + // SystemZ_VISTRB - 22 + {407, 91, 3, 3 }, + // SystemZ_VISTRF - 23 + {421, 94, 3, 3 }, + // SystemZ_VISTRH - 24 + {435, 97, 3, 3 }, + // SystemZ_VSTRC - 25 + {449, 100, 6, 6 }, + // SystemZ_VSTRCB - 26 + {476, 106, 5, 5 }, + // SystemZ_VSTRCBS - 27 + {498, 111, 5, 5 }, + // SystemZ_VSTRCF - 28 + {521, 116, 5, 5 }, + // SystemZ_VSTRCFS - 29 + {543, 121, 5, 5 }, + // SystemZ_VSTRCH - 30 + {566, 126, 5, 5 }, + // SystemZ_VSTRCHS - 31 + {588, 131, 5, 5 }, + // SystemZ_VSTRCZB - 32 + {611, 136, 5, 5 }, + // SystemZ_VSTRCZBS - 33 + {634, 141, 5, 5 }, + // SystemZ_VSTRCZF - 34 + {658, 146, 5, 5 }, + // SystemZ_VSTRCZFS - 35 + {681, 151, 5, 5 }, + // SystemZ_VSTRCZH - 36 + {705, 156, 5, 5 }, + // SystemZ_VSTRCZHS - 37 + {728, 161, 5, 5 }, + // SystemZ_VSTRS - 38 + {752, 166, 6, 6 }, + // SystemZ_VSTRSB - 39 + {779, 172, 5, 5 }, + // SystemZ_VSTRSF - 40 + {801, 177, 5, 5 }, + // SystemZ_VSTRSH - 41 + {823, 182, 5, 5 }, + {0}, }; + + static const AliasPatternCond Conds[] = { + // (VFAE VR128:$V1, VR128:$V2, VR128:$V3, imm32zx4:$M4, 0) - 0 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEB VR128:$V1, VR128:$V2, VR128:$V3, 0) - 5 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEBS VR128:$V1, VR128:$V2, VR128:$V3, 0) - 9 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEF VR128:$V1, VR128:$V2, VR128:$V3, 0) - 13 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEFS VR128:$V1, VR128:$V2, VR128:$V3, 0) - 17 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEH VR128:$V1, VR128:$V2, VR128:$V3, 0) - 21 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEHS VR128:$V1, VR128:$V2, VR128:$V3, 0) - 25 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEZB VR128:$V1, VR128:$V2, VR128:$V3, 0) - 29 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEZBS VR128:$V1, VR128:$V2, VR128:$V3, 0) - 33 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEZF VR128:$V1, VR128:$V2, VR128:$V3, 0) - 37 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEZFS VR128:$V1, VR128:$V2, VR128:$V3, 0) - 41 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEZH VR128:$V1, VR128:$V2, VR128:$V3, 0) - 45 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEZHS VR128:$V1, VR128:$V2, VR128:$V3, 0) - 49 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFEE VR128:$V1, VR128:$V2, VR128:$V3, imm32zx4:$M4, 0) - 53 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFEEB VR128:$V1, VR128:$V2, VR128:$V3, 0) - 58 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFEEF VR128:$V1, VR128:$V2, VR128:$V3, 0) - 62 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFEEH VR128:$V1, VR128:$V2, VR128:$V3, 0) - 66 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFENE VR128:$V1, VR128:$V2, VR128:$V3, imm32zx4:$M4, 0) - 70 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFENEB VR128:$V1, VR128:$V2, VR128:$V3, 0) - 75 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFENEF VR128:$V1, VR128:$V2, VR128:$V3, 0) - 79 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFENEH VR128:$V1, VR128:$V2, VR128:$V3, 0) - 83 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VISTR VR128:$V1, VR128:$V2, imm32zx4:$M3, 0) - 87 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VISTRB VR128:$V1, VR128:$V2, 0) - 91 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VISTRF VR128:$V1, VR128:$V2, 0) - 94 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VISTRH VR128:$V1, VR128:$V2, 0) - 97 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRC VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4_timm:$M5, 0) - 100 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCB VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 106 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCBS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 111 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCF VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 116 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCFS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 121 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCH VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 126 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCHS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 131 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCZB VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 136 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCZBS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 141 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCZF VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 146 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCZFS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 151 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCZH VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 156 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCZHS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 161 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, 0) - 166 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRSB VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 172 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRSF VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 177 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRSH VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 182 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {0}, }; + + static const char AsmStrings[] = + /* 0 */ "vfae $\x01, $\x02, $\x03, $\xFF\x04\x01\0" + /* 22 */ "vfaeb $\x01, $\x02, $\x03\0" + /* 39 */ "vfaebs $\x01, $\x02, $\x03\0" + /* 57 */ "vfaef $\x01, $\x02, $\x03\0" + /* 74 */ "vfaefs $\x01, $\x02, $\x03\0" + /* 92 */ "vfaeh $\x01, $\x02, $\x03\0" + /* 109 */ "vfaehs $\x01, $\x02, $\x03\0" + /* 127 */ "vfaezb $\x01, $\x02, $\x03\0" + /* 145 */ "vfaezbs $\x01, $\x02, $\x03\0" + /* 164 */ "vfaezf $\x01, $\x02, $\x03\0" + /* 182 */ "vfaezfs $\x01, $\x02, $\x03\0" + /* 201 */ "vfaezh $\x01, $\x02, $\x03\0" + /* 219 */ "vfaezhs $\x01, $\x02, $\x03\0" + /* 238 */ "vfee $\x01, $\x02, $\x03, $\xFF\x04\x01\0" + /* 260 */ "vfeeb $\x01, $\x02, $\x03\0" + /* 277 */ "vfeef $\x01, $\x02, $\x03\0" + /* 294 */ "vfeeh $\x01, $\x02, $\x03\0" + /* 311 */ "vfene $\x01, $\x02, $\x03, $\xFF\x04\x01\0" + /* 334 */ "vfeneb $\x01, $\x02, $\x03\0" + /* 352 */ "vfenef $\x01, $\x02, $\x03\0" + /* 370 */ "vfeneh $\x01, $\x02, $\x03\0" + /* 388 */ "vistr $\x01, $\x02, $\xFF\x03\x01\0" + /* 407 */ "vistrb $\x01, $\x02\0" + /* 421 */ "vistrf $\x01, $\x02\0" + /* 435 */ "vistrh $\x01, $\x02\0" + /* 449 */ "vstrc $\x01, $\x02, $\x03, $\x04, $\xFF\x05\x01\0" + /* 476 */ "vstrcb $\x01, $\x02, $\x03, $\x04\0" + /* 498 */ "vstrcbs $\x01, $\x02, $\x03, $\x04\0" + /* 521 */ "vstrcf $\x01, $\x02, $\x03, $\x04\0" + /* 543 */ "vstrcfs $\x01, $\x02, $\x03, $\x04\0" + /* 566 */ "vstrch $\x01, $\x02, $\x03, $\x04\0" + /* 588 */ "vstrchs $\x01, $\x02, $\x03, $\x04\0" + /* 611 */ "vstrczb $\x01, $\x02, $\x03, $\x04\0" + /* 634 */ "vstrczbs $\x01, $\x02, $\x03, $\x04\0" + /* 658 */ "vstrczf $\x01, $\x02, $\x03, $\x04\0" + /* 681 */ "vstrczfs $\x01, $\x02, $\x03, $\x04\0" + /* 705 */ "vstrczh $\x01, $\x02, $\x03, $\x04\0" + /* 728 */ "vstrczhs $\x01, $\x02, $\x03, $\x04\0" + /* 752 */ "vstrs $\x01, $\x02, $\x03, $\x04, $\xFF\x05\x01\0" + /* 779 */ "vstrsb $\x01, $\x02, $\x03, $\x04\0" + /* 801 */ "vstrsf $\x01, $\x02, $\x03, $\x04\0" + /* 823 */ "vstrsh $\x01, $\x02, $\x03, $\x04\0" + ; + +#ifndef NDEBUG + //static struct SortCheck { + // SortCheck(ArrayRef OpToPatterns) { + // assert(std::is_sorted( + // OpToPatterns.begin(), OpToPatterns.end(), + // [](const PatternsForOpcode &L, const //PatternsForOpcode &R) { + // return L.Opcode < R.Opcode; + // }) && + // "tablegen failed to sort opcode patterns"); + // } + //} sortCheckVar(OpToPatterns); #endif + + AliasMatchingData M = { + OpToPatterns, + Patterns, + Conds, + AsmStrings, + NULL, + }; + const char *AsmString = matchAliasPatterns(MI, &M); + if (!AsmString) return false; + + unsigned I = 0; + while (AsmString[I] != ' ' && AsmString[I] != '\t' && + AsmString[I] != '$' && AsmString[I] != '\0') + ++I; + SStream_concat1(OS, '\t'); + char *substr = malloc(I+1); + memcpy(substr, AsmString, I); + substr[I] = '\0'; + SStream_concat0(OS, substr); + free(substr); + if (AsmString[I] != '\0') { + if (AsmString[I] == ' ' || AsmString[I] == '\t') { + SStream_concat1(OS, '\t'); + ++I; + } + do { + if (AsmString[I] == '$') { + ++I; + if (AsmString[I] == (char)0xff) { + ++I; + int OpIdx = AsmString[I++] - 1; + int PrintMethodIdx = AsmString[I++] - 1; + printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, OS); + } else + printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS); + } else { + SStream_concat1(OS, AsmString[I++]); + } + } while (AsmString[I] != '\0'); + } + + return true; +#else + return false; +#endif // CAPSTONE_DIET } + +static void printCustomAliasOperand( + MCInst *MI, uint64_t Address, unsigned OpIdx, + unsigned PrintMethodIdx, + SStream *OS) { +#ifndef CAPSTONE_DIET + switch (PrintMethodIdx) { + default: + assert(0 && "Unknown PrintMethod kind"); + break; + case 0: + printU4ImmOperand(MI, OpIdx, OS); + break; + } +#endif // CAPSTONE_DIET +} + +#endif // PRINT_ALIAS_INSTR diff --git a/arch/SystemZ/SystemZGenCSAliasMnemMap.inc b/arch/SystemZ/SystemZGenCSAliasMnemMap.inc new file mode 100644 index 0000000000..bdc6aabd81 --- /dev/null +++ b/arch/SystemZ/SystemZGenCSAliasMnemMap.inc @@ -0,0 +1,55 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + + { SYSTEMZ_INS_ALIAS_VISTRB, "vistrb" }, + { SYSTEMZ_INS_ALIAS_VISTR, "vistr" }, + { SYSTEMZ_INS_ALIAS_VFEEB, "vfeeb" }, + { SYSTEMZ_INS_ALIAS_VFEE, "vfee" }, + { SYSTEMZ_INS_ALIAS_VFAEB, "vfaeb" }, + { SYSTEMZ_INS_ALIAS_VFAEBS, "vfaebs" }, + { SYSTEMZ_INS_ALIAS_VFAE, "vfae" }, + { SYSTEMZ_INS_ALIAS_VSTRSB, "vstrsb" }, + { SYSTEMZ_INS_ALIAS_VSTRS, "vstrs" }, + { SYSTEMZ_INS_ALIAS_VSTRCB, "vstrcb" }, + { SYSTEMZ_INS_ALIAS_VSTRCBS, "vstrcbs" }, + { SYSTEMZ_INS_ALIAS_VSTRC, "vstrc" }, + { SYSTEMZ_INS_ALIAS_VFAEH, "vfaeh" }, + { SYSTEMZ_INS_ALIAS_VFAEHS, "vfaehs" }, + { SYSTEMZ_INS_ALIAS_VFAEF, "vfaef" }, + { SYSTEMZ_INS_ALIAS_VFAEFS, "vfaefs" }, + { SYSTEMZ_INS_ALIAS_VFAEZB, "vfaezb" }, + { SYSTEMZ_INS_ALIAS_VFAEZBS, "vfaezbs" }, + { SYSTEMZ_INS_ALIAS_VFAEZH, "vfaezh" }, + { SYSTEMZ_INS_ALIAS_VFAEZHS, "vfaezhs" }, + { SYSTEMZ_INS_ALIAS_VFAEZF, "vfaezf" }, + { SYSTEMZ_INS_ALIAS_VFAEZFS, "vfaezfs" }, + { SYSTEMZ_INS_ALIAS_VFEEH, "vfeeh" }, + { SYSTEMZ_INS_ALIAS_VFEEF, "vfeef" }, + { SYSTEMZ_INS_ALIAS_VFENE, "vfene" }, + { SYSTEMZ_INS_ALIAS_VFENEB, "vfeneb" }, + { SYSTEMZ_INS_ALIAS_VFENEH, "vfeneh" }, + { SYSTEMZ_INS_ALIAS_VFENEF, "vfenef" }, + { SYSTEMZ_INS_ALIAS_VISTRH, "vistrh" }, + { SYSTEMZ_INS_ALIAS_VISTRF, "vistrf" }, + { SYSTEMZ_INS_ALIAS_VSTRCH, "vstrch" }, + { SYSTEMZ_INS_ALIAS_VSTRCHS, "vstrchs" }, + { SYSTEMZ_INS_ALIAS_VSTRCF, "vstrcf" }, + { SYSTEMZ_INS_ALIAS_VSTRCFS, "vstrcfs" }, + { SYSTEMZ_INS_ALIAS_VSTRCZB, "vstrczb" }, + { SYSTEMZ_INS_ALIAS_VSTRCZBS, "vstrczbs" }, + { SYSTEMZ_INS_ALIAS_VSTRCZH, "vstrczh" }, + { SYSTEMZ_INS_ALIAS_VSTRCZHS, "vstrczhs" }, + { SYSTEMZ_INS_ALIAS_VSTRCZF, "vstrczf" }, + { SYSTEMZ_INS_ALIAS_VSTRCZFS, "vstrczfs" }, + { SYSTEMZ_INS_ALIAS_VSTRSH, "vstrsh" }, + { SYSTEMZ_INS_ALIAS_VSTRSF, "vstrsf" }, diff --git a/arch/SystemZ/SystemZGenCSFeatureName.inc b/arch/SystemZ/SystemZGenCSFeatureName.inc new file mode 100644 index 0000000000..24d07a2dd7 --- /dev/null +++ b/arch/SystemZ/SystemZGenCSFeatureName.inc @@ -0,0 +1,55 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +{ SYSTEMZ_FEATURE_FEATURESOFTFLOAT, "FeatureSoftFloat" }, +{ SYSTEMZ_FEATURE_FEATUREBACKCHAIN, "FeatureBackChain" }, +{ SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, "FeatureDistinctOps" }, +{ SYSTEMZ_FEATURE_FEATUREFASTSERIALIZATION, "FeatureFastSerialization" }, +{ SYSTEMZ_FEATURE_FEATUREFPEXTENSION, "FeatureFPExtension" }, +{ SYSTEMZ_FEATURE_FEATUREHIGHWORD, "FeatureHighWord" }, +{ SYSTEMZ_FEATURE_FEATUREINTERLOCKEDACCESS1, "FeatureInterlockedAccess1" }, +{ SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, "FeatureLoadStoreOnCond" }, +{ SYSTEMZ_FEATURE_FEATUREPOPULATIONCOUNT, "FeaturePopulationCount" }, +{ SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST3, "FeatureMessageSecurityAssist3" }, +{ SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST4, "FeatureMessageSecurityAssist4" }, +{ SYSTEMZ_FEATURE_FEATURERESETREFERENCEBITSMULTIPLE, "FeatureResetReferenceBitsMultiple" }, +{ SYSTEMZ_FEATURE_FEATUREEXECUTIONHINT, "FeatureExecutionHint" }, +{ SYSTEMZ_FEATURE_FEATURELOADANDTRAP, "FeatureLoadAndTrap" }, +{ SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, "FeatureMiscellaneousExtensions" }, +{ SYSTEMZ_FEATURE_FEATUREPROCESSORASSIST, "FeatureProcessorAssist" }, +{ SYSTEMZ_FEATURE_FEATURETRANSACTIONALEXECUTION, "FeatureTransactionalExecution" }, +{ SYSTEMZ_FEATURE_FEATUREDFPZONEDCONVERSION, "FeatureDFPZonedConversion" }, +{ SYSTEMZ_FEATURE_FEATUREENHANCEDDAT2, "FeatureEnhancedDAT2" }, +{ SYSTEMZ_FEATURE_FEATURELOADANDZERORIGHTMOSTBYTE, "FeatureLoadAndZeroRightmostByte" }, +{ SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, "FeatureLoadStoreOnCond2" }, +{ SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST5, "FeatureMessageSecurityAssist5" }, +{ SYSTEMZ_FEATURE_FEATUREDFPPACKEDCONVERSION, "FeatureDFPPackedConversion" }, +{ SYSTEMZ_FEATURE_FEATUREVECTOR, "FeatureVector" }, +{ SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, "FeatureMiscellaneousExtensions2" }, +{ SYSTEMZ_FEATURE_FEATUREGUARDEDSTORAGE, "FeatureGuardedStorage" }, +{ SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST7, "FeatureMessageSecurityAssist7" }, +{ SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST8, "FeatureMessageSecurityAssist8" }, +{ SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, "FeatureVectorEnhancements1" }, +{ SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, "FeatureVectorPackedDecimal" }, +{ SYSTEMZ_FEATURE_FEATUREINSERTREFERENCEBITSMULTIPLE, "FeatureInsertReferenceBitsMultiple" }, +{ SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, "FeatureMiscellaneousExtensions3" }, +{ SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST9, "FeatureMessageSecurityAssist9" }, +{ SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, "FeatureVectorEnhancements2" }, +{ SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT, "FeatureVectorPackedDecimalEnhancement" }, +{ SYSTEMZ_FEATURE_FEATUREENHANCEDSORT, "FeatureEnhancedSort" }, +{ SYSTEMZ_FEATURE_FEATUREDEFLATECONVERSION, "FeatureDeflateConversion" }, +{ SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT2, "FeatureVectorPackedDecimalEnhancement2" }, +{ SYSTEMZ_FEATURE_FEATURENNPASSIST, "FeatureNNPAssist" }, +{ SYSTEMZ_FEATURE_FEATUREBEARENHANCEMENT, "FeatureBEAREnhancement" }, +{ SYSTEMZ_FEATURE_FEATURERESETDATPROTECTION, "FeatureResetDATProtection" }, +{ SYSTEMZ_FEATURE_FEATUREPROCESSORACTIVITYINSTRUMENTATION, "FeatureProcessorActivityInstrumentation" }, diff --git a/arch/SystemZ/SystemZGenCSMappingInsn.inc b/arch/SystemZ/SystemZGenCSMappingInsn.inc new file mode 100644 index 0000000000..d7c5b7e82f --- /dev/null +++ b/arch/SystemZ/SystemZGenCSMappingInsn.inc @@ -0,0 +1,24272 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +{ + /* PHINODE */ + SystemZ_PHI /* 0 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_INLINEASM /* 1 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_INLINEASM_BR /* 2 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CFI_INSTRUCTION /* 3 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_EH_LABEL /* 4 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_GC_LABEL /* 5 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ANNOTATION_LABEL /* 6 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_KILL /* 7 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_EXTRACT_SUBREG /* 8 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_INSERT_SUBREG /* 9 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_IMPLICIT_DEF /* 10 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_SUBREG_TO_REG /* 11 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_COPY_TO_REGCLASS /* 12 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_VALUE */ + SystemZ_DBG_VALUE /* 13 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_VALUE_LIST */ + SystemZ_DBG_VALUE_LIST /* 14 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_INSTR_REF */ + SystemZ_DBG_INSTR_REF /* 15 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_PHI */ + SystemZ_DBG_PHI /* 16 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* DBG_LABEL */ + SystemZ_DBG_LABEL /* 17 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_REG_SEQUENCE /* 18 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_COPY /* 19 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* BUNDLE */ + SystemZ_BUNDLE /* 20 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* LIFETIME_START */ + SystemZ_LIFETIME_START /* 21 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* LIFETIME_END */ + SystemZ_LIFETIME_END /* 22 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* PSEUDO_PROBE */ + SystemZ_PSEUDO_PROBE /* 23 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ARITH_FENCE /* 24 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_STACKMAP /* 25 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # FEntry call */ + SystemZ_FENTRY_CALL /* 26 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_PATCHPOINT /* 27 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LOAD_STACK_GUARD /* 28 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_PREALLOCATED_SETUP /* 29 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_PREALLOCATED_ARG /* 30 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_STATEPOINT /* 31 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LOCAL_ESCAPE /* 32 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_FAULTING_OP /* 33 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_PATCHABLE_OP /* 34 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Function Enter. */ + SystemZ_PATCHABLE_FUNCTION_ENTER /* 35 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Function Patchable RET. */ + SystemZ_PATCHABLE_RET /* 36 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Function Exit. */ + SystemZ_PATCHABLE_FUNCTION_EXIT /* 37 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Tail Call Exit. */ + SystemZ_PATCHABLE_TAIL_CALL /* 38 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Custom Event Log. */ + SystemZ_PATCHABLE_EVENT_CALL /* 39 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* # XRay Typed Event Log. */ + SystemZ_PATCHABLE_TYPED_EVENT_CALL /* 40 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ICALL_BRANCH_FUNNEL /* 41 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_MEMBARRIER /* 42 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_JUMP_TABLE_DEBUG_INFO /* 43 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ASSERT_SEXT /* 44 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ASSERT_ZEXT /* 45 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ASSERT_ALIGN /* 46 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ADD /* 47 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SUB /* 48 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_MUL /* 49 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SDIV /* 50 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_UDIV /* 51 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SREM /* 52 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_UREM /* 53 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SDIVREM /* 54 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_UDIVREM /* 55 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_AND /* 56 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_OR /* 57 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_XOR /* 58 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_IMPLICIT_DEF /* 59 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_PHI /* 60 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FRAME_INDEX /* 61 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_GLOBAL_VALUE /* 62 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_CONSTANT_POOL /* 63 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_EXTRACT /* 64 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_UNMERGE_VALUES /* 65 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_INSERT /* 66 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_MERGE_VALUES /* 67 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_BUILD_VECTOR /* 68 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_BUILD_VECTOR_TRUNC /* 69 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_CONCAT_VECTORS /* 70 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_PTRTOINT /* 71 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_INTTOPTR /* 72 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_BITCAST /* 73 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FREEZE /* 74 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_CONSTANT_FOLD_BARRIER /* 75 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_INTRINSIC_FPTRUNC_ROUND /* 76 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_INTRINSIC_TRUNC /* 77 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_INTRINSIC_ROUND /* 78 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_INTRINSIC_LRINT /* 79 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_INTRINSIC_ROUNDEVEN /* 80 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_READCYCLECOUNTER /* 81 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_LOAD /* 82 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SEXTLOAD /* 83 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ZEXTLOAD /* 84 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_INDEXED_LOAD /* 85 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_INDEXED_SEXTLOAD /* 86 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_INDEXED_ZEXTLOAD /* 87 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_STORE /* 88 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_INDEXED_STORE /* 89 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ATOMIC_CMPXCHG_WITH_SUCCESS /* 90 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ATOMIC_CMPXCHG /* 91 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ATOMICRMW_XCHG /* 92 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ATOMICRMW_ADD /* 93 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ATOMICRMW_SUB /* 94 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ATOMICRMW_AND /* 95 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ATOMICRMW_NAND /* 96 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ATOMICRMW_OR /* 97 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ATOMICRMW_XOR /* 98 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ATOMICRMW_MAX /* 99 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ATOMICRMW_MIN /* 100 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ATOMICRMW_UMAX /* 101 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ATOMICRMW_UMIN /* 102 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ATOMICRMW_FADD /* 103 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ATOMICRMW_FSUB /* 104 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ATOMICRMW_FMAX /* 105 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ATOMICRMW_FMIN /* 106 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ATOMICRMW_UINC_WRAP /* 107 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ATOMICRMW_UDEC_WRAP /* 108 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FENCE /* 109 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_PREFETCH /* 110 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_BRCOND /* 111 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_BRINDIRECT /* 112 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_INVOKE_REGION_START /* 113 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_INTRINSIC /* 114 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_INTRINSIC_W_SIDE_EFFECTS /* 115 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_INTRINSIC_CONVERGENT /* 116 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS /* 117 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ANYEXT /* 118 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_TRUNC /* 119 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_CONSTANT /* 120 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FCONSTANT /* 121 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_VASTART /* 122 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_VAARG /* 123 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SEXT /* 124 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SEXT_INREG /* 125 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ZEXT /* 126 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SHL /* 127 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_LSHR /* 128 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ASHR /* 129 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FSHL /* 130 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FSHR /* 131 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ROTR /* 132 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ROTL /* 133 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ICMP /* 134 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FCMP /* 135 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SELECT /* 136 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_UADDO /* 137 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_UADDE /* 138 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_USUBO /* 139 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_USUBE /* 140 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SADDO /* 141 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SADDE /* 142 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SSUBO /* 143 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SSUBE /* 144 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_UMULO /* 145 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SMULO /* 146 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_UMULH /* 147 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SMULH /* 148 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_UADDSAT /* 149 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SADDSAT /* 150 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_USUBSAT /* 151 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SSUBSAT /* 152 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_USHLSAT /* 153 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SSHLSAT /* 154 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SMULFIX /* 155 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_UMULFIX /* 156 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SMULFIXSAT /* 157 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_UMULFIXSAT /* 158 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SDIVFIX /* 159 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_UDIVFIX /* 160 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SDIVFIXSAT /* 161 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_UDIVFIXSAT /* 162 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FADD /* 163 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FSUB /* 164 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FMUL /* 165 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FMA /* 166 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FMAD /* 167 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FDIV /* 168 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FREM /* 169 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FPOW /* 170 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FPOWI /* 171 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FEXP /* 172 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FEXP2 /* 173 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FEXP10 /* 174 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FLOG /* 175 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FLOG2 /* 176 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FLOG10 /* 177 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FLDEXP /* 178 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FFREXP /* 179 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FNEG /* 180 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FPEXT /* 181 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FPTRUNC /* 182 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FPTOSI /* 183 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FPTOUI /* 184 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SITOFP /* 185 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_UITOFP /* 186 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FABS /* 187 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FCOPYSIGN /* 188 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_IS_FPCLASS /* 189 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FCANONICALIZE /* 190 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FMINNUM /* 191 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FMAXNUM /* 192 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FMINNUM_IEEE /* 193 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FMAXNUM_IEEE /* 194 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FMINIMUM /* 195 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FMAXIMUM /* 196 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_GET_FPENV /* 197 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SET_FPENV /* 198 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_RESET_FPENV /* 199 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_GET_FPMODE /* 200 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SET_FPMODE /* 201 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_RESET_FPMODE /* 202 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_PTR_ADD /* 203 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_PTRMASK /* 204 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SMIN /* 205 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SMAX /* 206 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_UMIN /* 207 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_UMAX /* 208 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ABS /* 209 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_LROUND /* 210 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_LLROUND /* 211 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_BR /* 212 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_BRJT /* 213 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_INSERT_VECTOR_ELT /* 214 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_EXTRACT_VECTOR_ELT /* 215 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SHUFFLE_VECTOR /* 216 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_CTTZ /* 217 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_CTTZ_ZERO_UNDEF /* 218 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_CTLZ /* 219 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_CTLZ_ZERO_UNDEF /* 220 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_CTPOP /* 221 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_BSWAP /* 222 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_BITREVERSE /* 223 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FCEIL /* 224 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FCOS /* 225 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FSIN /* 226 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FSQRT /* 227 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FFLOOR /* 228 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FRINT /* 229 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_FNEARBYINT /* 230 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_ADDRSPACE_CAST /* 231 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_BLOCK_ADDR /* 232 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_JUMP_TABLE /* 233 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_DYN_STACKALLOC /* 234 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_STACKSAVE /* 235 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_STACKRESTORE /* 236 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_STRICT_FADD /* 237 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_STRICT_FSUB /* 238 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_STRICT_FMUL /* 239 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_STRICT_FDIV /* 240 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_STRICT_FREM /* 241 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_STRICT_FMA /* 242 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_STRICT_FSQRT /* 243 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_STRICT_FLDEXP /* 244 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_READ_REGISTER /* 245 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_WRITE_REGISTER /* 246 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_MEMCPY /* 247 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_MEMCPY_INLINE /* 248 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_MEMMOVE /* 249 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_MEMSET /* 250 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_BZERO /* 251 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_VECREDUCE_SEQ_FADD /* 252 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_VECREDUCE_SEQ_FMUL /* 253 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_VECREDUCE_FADD /* 254 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_VECREDUCE_FMUL /* 255 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_VECREDUCE_FMAX /* 256 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_VECREDUCE_FMIN /* 257 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_VECREDUCE_FMAXIMUM /* 258 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_VECREDUCE_FMINIMUM /* 259 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_VECREDUCE_ADD /* 260 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_VECREDUCE_MUL /* 261 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_VECREDUCE_AND /* 262 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_VECREDUCE_OR /* 263 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_VECREDUCE_XOR /* 264 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_VECREDUCE_SMAX /* 265 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_VECREDUCE_SMIN /* 266 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_VECREDUCE_UMAX /* 267 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_VECREDUCE_UMIN /* 268 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_SBFX /* 269 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_G_UBFX /* 270 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ADA_ENTRY /* 271 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ADA_ENTRY_VALUE /* 272 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ADB_MemFoldPseudo /* 273 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ADJCALLSTACKDOWN /* 274 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ADJCALLSTACKUP /* 275 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ADJDYNALLOC /* 276 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_AEB_MemFoldPseudo /* 277 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_AEXT128 /* 278 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_AFIMux /* 279 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_AG_MemFoldPseudo /* 280 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_AHIMux /* 281 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_AHIMuxK /* 282 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ALG_MemFoldPseudo /* 283 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_AL_MemFoldPseudo /* 284 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ATOMIC_CMP_SWAPW /* 285 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ATOMIC_LOADW_AFI /* 286 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ATOMIC_LOADW_AR /* 287 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ATOMIC_LOADW_MAX /* 288 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ATOMIC_LOADW_MIN /* 289 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ATOMIC_LOADW_NILH /* 290 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ATOMIC_LOADW_NILHi /* 291 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ATOMIC_LOADW_NR /* 292 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ATOMIC_LOADW_NRi /* 293 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ATOMIC_LOADW_OILH /* 294 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ATOMIC_LOADW_OR /* 295 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ATOMIC_LOADW_SR /* 296 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ATOMIC_LOADW_UMAX /* 297 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ATOMIC_LOADW_UMIN /* 298 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ATOMIC_LOADW_XILF /* 299 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ATOMIC_LOADW_XR /* 300 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ATOMIC_SWAPW /* 301 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_A_MemFoldPseudo /* 302 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CFIMux /* 303 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CGIBCall /* 304 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CGIBReturn /* 305 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CGRBCall /* 306 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CGRBReturn /* 307 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CHIMux /* 308 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CIBCall /* 309 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CIBReturn /* 310 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CLCImm /* 311 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CLCReg /* 312 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CLFIMux /* 313 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CLGIBCall /* 314 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CLGIBReturn /* 315 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CLGRBCall /* 316 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CLGRBReturn /* 317 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CLIBCall /* 318 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CLIBReturn /* 319 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CLMux /* 320 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CLRBCall /* 321 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CLRBReturn /* 322 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CLSTLoop /* 323 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CMux /* 324 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CRBCall /* 325 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CRBReturn /* 326 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CallBASR /* 327 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CallBASR_STACKEXT /* 328 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CallBASR_XPLINK64 /* 329 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CallBCR /* 330 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CallBR /* 331 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CallBRASL /* 332 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CallBRASL_XPLINK64 /* 333 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CallBRCL /* 334 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CallJG /* 335 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondReturn /* 336 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondReturn_XPLINK /* 337 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondStore16 /* 338 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondStore16Inv /* 339 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondStore16Mux /* 340 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondStore16MuxInv /* 341 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondStore32 /* 342 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondStore32Inv /* 343 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondStore32Mux /* 344 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondStore32MuxInv /* 345 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondStore64 /* 346 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondStore64Inv /* 347 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondStore8 /* 348 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondStore8Inv /* 349 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondStore8Mux /* 350 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondStore8MuxInv /* 351 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondStoreF32 /* 352 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondStoreF32Inv /* 353 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondStoreF64 /* 354 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondStoreF64Inv /* 355 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_CondTrap /* 356 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_DDB_MemFoldPseudo /* 357 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_DEB_MemFoldPseudo /* 358 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_EXRL_Pseudo /* 359 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_GOT /* 360 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_IIFMux /* 361 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_IIHF64 /* 362 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_IIHH64 /* 363 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_IIHL64 /* 364 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_IIHMux /* 365 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_IILF64 /* 366 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_IILH64 /* 367 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_IILL64 /* 368 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_IILMux /* 369 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_L128 /* 370 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LBMux /* 371 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LEFR /* 372 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LFER /* 373 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LHIMux /* 374 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LHMux /* 375 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LLCMux /* 376 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LLCRMux /* 377 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LLHMux /* 378 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LLHRMux /* 379 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LMux /* 380 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LOCG_MemFoldPseudo /* 381 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LOCHIMux /* 382 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LOCMux /* 383 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LOCMux_MemFoldPseudo /* 384 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LOCRMux /* 385 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LTDBRCompare_Pseudo /* 386 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LTEBRCompare_Pseudo /* 387 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LTXBRCompare_Pseudo /* 388 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_LX /* 389 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_MADB_MemFoldPseudo /* 390 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_MAEB_MemFoldPseudo /* 391 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_MDB_MemFoldPseudo /* 392 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_MEEB_MemFoldPseudo /* 393 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_MSC_MemFoldPseudo /* 394 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_MSDB_MemFoldPseudo /* 395 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_MSEB_MemFoldPseudo /* 396 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_MSGC_MemFoldPseudo /* 397 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_MVCImm /* 398 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_MVCReg /* 399 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_MVSTLoop /* 400 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_MemsetImmImm /* 401 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_MemsetImmReg /* 402 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_MemsetRegImm /* 403 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_MemsetRegReg /* 404 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_NCImm /* 405 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_NCReg /* 406 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_NG_MemFoldPseudo /* 407 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_NIFMux /* 408 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_NIHF64 /* 409 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_NIHH64 /* 410 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_NIHL64 /* 411 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_NIHMux /* 412 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_NILF64 /* 413 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_NILH64 /* 414 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_NILL64 /* 415 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_NILMux /* 416 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_N_MemFoldPseudo /* 417 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_OCImm /* 418 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_OCReg /* 419 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_OG_MemFoldPseudo /* 420 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_OIFMux /* 421 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_OIHF64 /* 422 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_OIHH64 /* 423 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_OIHL64 /* 424 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_OIHMux /* 425 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_OILF64 /* 426 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_OILH64 /* 427 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_OILL64 /* 428 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_OILMux /* 429 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_O_MemFoldPseudo /* 430 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_PAIR128 /* 431 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_PROBED_ALLOCA /* 432 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_PROBED_STACKALLOC /* 433 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_RISBHH /* 434 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_RISBHL /* 435 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_RISBLH /* 436 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_RISBLL /* 437 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_RISBMux /* 438 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_Return /* 439 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_Return_XPLINK /* 440 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_SCmp128Hi /* 441 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_SDB_MemFoldPseudo /* 442 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_SEB_MemFoldPseudo /* 443 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_SELRMux /* 444 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_SG_MemFoldPseudo /* 445 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_SLG_MemFoldPseudo /* 446 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_SL_MemFoldPseudo /* 447 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_SRSTLoop /* 448 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ST128 /* 449 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_STCMux /* 450 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_STHMux /* 451 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_STMux /* 452 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_STOCMux /* 453 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_STX /* 454 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_S_MemFoldPseudo /* 455 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_Select128 /* 456 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_Select32 /* 457 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_Select64 /* 458 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_SelectF128 /* 459 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_SelectF32 /* 460 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_SelectF64 /* 461 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_SelectVR128 /* 462 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_SelectVR32 /* 463 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_SelectVR64 /* 464 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_Serialize /* 465 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_TBEGIN_nofloat /* 466 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_TLS_GDCALL /* 467 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_TLS_LDCALL /* 468 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_TMHH64 /* 469 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_TMHL64 /* 470 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_TMHMux /* 471 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_TMLH64 /* 472 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_TMLL64 /* 473 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_TMLMux /* 474 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_Trap /* 475 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_UCmp128Hi /* 476 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_VL32 /* 477 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_VL64 /* 478 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_VLR32 /* 479 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_VLR64 /* 480 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_VLVGP32 /* 481 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_VST32 /* 482 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_VST64 /* 483 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_XCImm /* 484 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_XCReg /* 485 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_XG_MemFoldPseudo /* 486 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_XIFMux /* 487 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_XIHF64 /* 488 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_XILF64 /* 489 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_XPLINK_STACKALLOC /* 490 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_X_MemFoldPseudo /* 491 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* */ + SystemZ_ZEXT128 /* 492 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* a $R1, $XBD2 */ + SystemZ_A /* 493 */, SYSTEMZ_INS_A, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* ad $R1, $XBD2 */ + SystemZ_AD /* 494 */, SYSTEMZ_INS_AD, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* adb $R1, $XBD2 */ + SystemZ_ADB /* 495 */, SYSTEMZ_INS_ADB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* adbr $R1, $R2 */ + SystemZ_ADBR /* 496 */, SYSTEMZ_INS_ADBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* adr $R1, $R2 */ + SystemZ_ADR /* 497 */, SYSTEMZ_INS_ADR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* adtr $R1, $R2, $R3 */ + SystemZ_ADTR /* 498 */, SYSTEMZ_INS_ADTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* adtra $R1, $R2, $R3, $M4 */ + SystemZ_ADTRA /* 499 */, SYSTEMZ_INS_ADTRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* ae $R1, $XBD2 */ + SystemZ_AE /* 500 */, SYSTEMZ_INS_AE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* aeb $R1, $XBD2 */ + SystemZ_AEB /* 501 */, SYSTEMZ_INS_AEB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* aebr $R1, $R2 */ + SystemZ_AEBR /* 502 */, SYSTEMZ_INS_AEBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* aer $R1, $R2 */ + SystemZ_AER /* 503 */, SYSTEMZ_INS_AER, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* afi $R1, $I2 */ + SystemZ_AFI /* 504 */, SYSTEMZ_INS_AFI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* ag $R1, $XBD2 */ + SystemZ_AG /* 505 */, SYSTEMZ_INS_AG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* agf $R1, $XBD2 */ + SystemZ_AGF /* 506 */, SYSTEMZ_INS_AGF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* agfi $R1, $I2 */ + SystemZ_AGFI /* 507 */, SYSTEMZ_INS_AGFI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* agfr $R1, $R2 */ + SystemZ_AGFR /* 508 */, SYSTEMZ_INS_AGFR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* agh $R1, $XBD2 */ + SystemZ_AGH /* 509 */, SYSTEMZ_INS_AGH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* aghi $R1, $I2 */ + SystemZ_AGHI /* 510 */, SYSTEMZ_INS_AGHI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* aghik $R1, $R3, $I2 */ + SystemZ_AGHIK /* 511 */, SYSTEMZ_INS_AGHIK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIED }} + + #endif +}, +{ + /* agr $R1, $R2 */ + SystemZ_AGR /* 512 */, SYSTEMZ_INS_AGR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* agrk $R1, $R2, $R3 */ + SystemZ_AGRK /* 513 */, SYSTEMZ_INS_AGRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* agsi $BD1, $I2 */ + SystemZ_AGSI /* 514 */, SYSTEMZ_INS_AGSI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIY }} + + #endif +}, +{ + /* ah $R1, $XBD2 */ + SystemZ_AH /* 515 */, SYSTEMZ_INS_AH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* ahhhr $R1, $R2, $R3 */ + SystemZ_AHHHR /* 516 */, SYSTEMZ_INS_AHHHR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* ahhlr $R1, $R2, $R3 */ + SystemZ_AHHLR /* 517 */, SYSTEMZ_INS_AHHLR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* ahi $R1, $I2 */ + SystemZ_AHI /* 518 */, SYSTEMZ_INS_AHI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* ahik $R1, $R3, $I2 */ + SystemZ_AHIK /* 519 */, SYSTEMZ_INS_AHIK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIED }} + + #endif +}, +{ + /* ahy $R1, $XBD2 */ + SystemZ_AHY /* 520 */, SYSTEMZ_INS_AHY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* aih $R1, $I2 */ + SystemZ_AIH /* 521 */, SYSTEMZ_INS_AIH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* al $R1, $XBD2 */ + SystemZ_AL /* 522 */, SYSTEMZ_INS_AL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* alc $R1, $XBD2 */ + SystemZ_ALC /* 523 */, SYSTEMZ_INS_ALC, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* alcg $R1, $XBD2 */ + SystemZ_ALCG /* 524 */, SYSTEMZ_INS_ALCG, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* alcgr $R1, $R2 */ + SystemZ_ALCGR /* 525 */, SYSTEMZ_INS_ALCGR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* alcr $R1, $R2 */ + SystemZ_ALCR /* 526 */, SYSTEMZ_INS_ALCR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* alfi $R1, $I2 */ + SystemZ_ALFI /* 527 */, SYSTEMZ_INS_ALFI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* alg $R1, $XBD2 */ + SystemZ_ALG /* 528 */, SYSTEMZ_INS_ALG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* algf $R1, $XBD2 */ + SystemZ_ALGF /* 529 */, SYSTEMZ_INS_ALGF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* algfi $R1, $I2 */ + SystemZ_ALGFI /* 530 */, SYSTEMZ_INS_ALGFI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* algfr $R1, $R2 */ + SystemZ_ALGFR /* 531 */, SYSTEMZ_INS_ALGFR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* alghsik $R1, $R3, $I2 */ + SystemZ_ALGHSIK /* 532 */, SYSTEMZ_INS_ALGHSIK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIED }} + + #endif +}, +{ + /* algr $R1, $R2 */ + SystemZ_ALGR /* 533 */, SYSTEMZ_INS_ALGR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* algrk $R1, $R2, $R3 */ + SystemZ_ALGRK /* 534 */, SYSTEMZ_INS_ALGRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* algsi $BD1, $I2 */ + SystemZ_ALGSI /* 535 */, SYSTEMZ_INS_ALGSI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIY }} + + #endif +}, +{ + /* alhhhr $R1, $R2, $R3 */ + SystemZ_ALHHHR /* 536 */, SYSTEMZ_INS_ALHHHR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* alhhlr $R1, $R2, $R3 */ + SystemZ_ALHHLR /* 537 */, SYSTEMZ_INS_ALHHLR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* alhsik $R1, $R3, $I2 */ + SystemZ_ALHSIK /* 538 */, SYSTEMZ_INS_ALHSIK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIED }} + + #endif +}, +{ + /* alr $R1, $R2 */ + SystemZ_ALR /* 539 */, SYSTEMZ_INS_ALR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* alrk $R1, $R2, $R3 */ + SystemZ_ALRK /* 540 */, SYSTEMZ_INS_ALRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* alsi $BD1, $I2 */ + SystemZ_ALSI /* 541 */, SYSTEMZ_INS_ALSI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIY }} + + #endif +}, +{ + /* alsih $R1, $I2 */ + SystemZ_ALSIH /* 542 */, SYSTEMZ_INS_ALSIH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* alsihn $R1, $I2 */ + SystemZ_ALSIHN /* 543 */, SYSTEMZ_INS_ALSIHN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* aly $R1, $XBD2 */ + SystemZ_ALY /* 544 */, SYSTEMZ_INS_ALY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* ap $BDL1, $BDL2 */ + SystemZ_AP /* 545 */, SYSTEMZ_INS_AP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSB }} + + #endif +}, +{ + /* ar $R1, $R2 */ + SystemZ_AR /* 546 */, SYSTEMZ_INS_AR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* ark $R1, $R2, $R3 */ + SystemZ_ARK /* 547 */, SYSTEMZ_INS_ARK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* asi $BD1, $I2 */ + SystemZ_ASI /* 548 */, SYSTEMZ_INS_ASI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIY }} + + #endif +}, +{ + /* au $R1, $XBD2 */ + SystemZ_AU /* 549 */, SYSTEMZ_INS_AU, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* aur $R1, $R2 */ + SystemZ_AUR /* 550 */, SYSTEMZ_INS_AUR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* aw $R1, $XBD2 */ + SystemZ_AW /* 551 */, SYSTEMZ_INS_AW, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* awr $R1, $R2 */ + SystemZ_AWR /* 552 */, SYSTEMZ_INS_AWR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* axbr $R1, $R2 */ + SystemZ_AXBR /* 553 */, SYSTEMZ_INS_AXBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* axr $R1, $R2 */ + SystemZ_AXR /* 554 */, SYSTEMZ_INS_AXR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* axtr $R1, $R2, $R3 */ + SystemZ_AXTR /* 555 */, SYSTEMZ_INS_AXTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* axtra $R1, $R2, $R3, $M4 */ + SystemZ_AXTRA /* 556 */, SYSTEMZ_INS_AXTRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* ay $R1, $XBD2 */ + SystemZ_AY /* 557 */, SYSTEMZ_INS_AY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* b $XBD2 */ + SystemZ_B /* 558 */, SYSTEMZ_INS_B, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* bakr $R1, $R2 */ + SystemZ_BAKR /* 559 */, SYSTEMZ_INS_BAKR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* bal $R1, $XBD2 */ + SystemZ_BAL /* 560 */, SYSTEMZ_INS_BAL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_CALL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* balr $R1, $R2 */ + SystemZ_BALR /* 561 */, SYSTEMZ_INS_BALR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_CALL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bas $R1, $XBD2 */ + SystemZ_BAS /* 562 */, SYSTEMZ_INS_BAS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_CALL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* basr $R1, $R2 */ + SystemZ_BASR /* 563 */, SYSTEMZ_INS_BASR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_CALL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bassm $R1, $R2 */ + SystemZ_BASSM /* 564 */, SYSTEMZ_INS_BASSM, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_CALL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* be $XBD2 */ + SystemZ_BAsmE /* 565 */, SYSTEMZ_INS_BE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* bh $XBD2 */ + SystemZ_BAsmH /* 566 */, SYSTEMZ_INS_BH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* bhe $XBD2 */ + SystemZ_BAsmHE /* 567 */, SYSTEMZ_INS_BHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* bl $XBD2 */ + SystemZ_BAsmL /* 568 */, SYSTEMZ_INS_BL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* ble $XBD2 */ + SystemZ_BAsmLE /* 569 */, SYSTEMZ_INS_BLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* blh $XBD2 */ + SystemZ_BAsmLH /* 570 */, SYSTEMZ_INS_BLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* bm $XBD2 */ + SystemZ_BAsmM /* 571 */, SYSTEMZ_INS_BM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* bne $XBD2 */ + SystemZ_BAsmNE /* 572 */, SYSTEMZ_INS_BNE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* bnh $XBD2 */ + SystemZ_BAsmNH /* 573 */, SYSTEMZ_INS_BNH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* bnhe $XBD2 */ + SystemZ_BAsmNHE /* 574 */, SYSTEMZ_INS_BNHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* bnl $XBD2 */ + SystemZ_BAsmNL /* 575 */, SYSTEMZ_INS_BNL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* bnle $XBD2 */ + SystemZ_BAsmNLE /* 576 */, SYSTEMZ_INS_BNLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* bnlh $XBD2 */ + SystemZ_BAsmNLH /* 577 */, SYSTEMZ_INS_BNLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* bnm $XBD2 */ + SystemZ_BAsmNM /* 578 */, SYSTEMZ_INS_BNM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* bno $XBD2 */ + SystemZ_BAsmNO /* 579 */, SYSTEMZ_INS_BNO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* bnp $XBD2 */ + SystemZ_BAsmNP /* 580 */, SYSTEMZ_INS_BNP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* bnz $XBD2 */ + SystemZ_BAsmNZ /* 581 */, SYSTEMZ_INS_BNZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* bo $XBD2 */ + SystemZ_BAsmO /* 582 */, SYSTEMZ_INS_BO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* bp $XBD2 */ + SystemZ_BAsmP /* 583 */, SYSTEMZ_INS_BP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* bz $XBD2 */ + SystemZ_BAsmZ /* 584 */, SYSTEMZ_INS_BZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* b${M1} $XBD2 */ + SystemZ_BC /* 585 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* bc $M1, $XBD2 */ + SystemZ_BCAsm /* 586 */, SYSTEMZ_INS_BC, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* b${R1}r $R2 */ + SystemZ_BCR /* 587 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* bcr $R1, $R2 */ + SystemZ_BCRAsm /* 588 */, SYSTEMZ_INS_BCR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bct $R1, $XBD2 */ + SystemZ_BCT /* 589 */, SYSTEMZ_INS_BCT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* bctg $R1, $XBD2 */ + SystemZ_BCTG /* 590 */, SYSTEMZ_INS_BCTG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* bctgr $R1, $R2 */ + SystemZ_BCTGR /* 591 */, SYSTEMZ_INS_BCTGR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* bctr $R1, $R2 */ + SystemZ_BCTR /* 592 */, SYSTEMZ_INS_BCTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bi $XBD2 */ + SystemZ_BI /* 593 */, SYSTEMZ_INS_BI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* bie $XBD2 */ + SystemZ_BIAsmE /* 594 */, SYSTEMZ_INS_BIE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* bih $XBD2 */ + SystemZ_BIAsmH /* 595 */, SYSTEMZ_INS_BIH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* bihe $XBD2 */ + SystemZ_BIAsmHE /* 596 */, SYSTEMZ_INS_BIHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* bil $XBD2 */ + SystemZ_BIAsmL /* 597 */, SYSTEMZ_INS_BIL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* bile $XBD2 */ + SystemZ_BIAsmLE /* 598 */, SYSTEMZ_INS_BILE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* bilh $XBD2 */ + SystemZ_BIAsmLH /* 599 */, SYSTEMZ_INS_BILH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* bim $XBD2 */ + SystemZ_BIAsmM /* 600 */, SYSTEMZ_INS_BIM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* bine $XBD2 */ + SystemZ_BIAsmNE /* 601 */, SYSTEMZ_INS_BINE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* binh $XBD2 */ + SystemZ_BIAsmNH /* 602 */, SYSTEMZ_INS_BINH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* binhe $XBD2 */ + SystemZ_BIAsmNHE /* 603 */, SYSTEMZ_INS_BINHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* binl $XBD2 */ + SystemZ_BIAsmNL /* 604 */, SYSTEMZ_INS_BINL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* binle $XBD2 */ + SystemZ_BIAsmNLE /* 605 */, SYSTEMZ_INS_BINLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* binlh $XBD2 */ + SystemZ_BIAsmNLH /* 606 */, SYSTEMZ_INS_BINLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* binm $XBD2 */ + SystemZ_BIAsmNM /* 607 */, SYSTEMZ_INS_BINM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* bino $XBD2 */ + SystemZ_BIAsmNO /* 608 */, SYSTEMZ_INS_BINO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* binp $XBD2 */ + SystemZ_BIAsmNP /* 609 */, SYSTEMZ_INS_BINP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* binz $XBD2 */ + SystemZ_BIAsmNZ /* 610 */, SYSTEMZ_INS_BINZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* bio $XBD2 */ + SystemZ_BIAsmO /* 611 */, SYSTEMZ_INS_BIO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* bip $XBD2 */ + SystemZ_BIAsmP /* 612 */, SYSTEMZ_INS_BIP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* biz $XBD2 */ + SystemZ_BIAsmZ /* 613 */, SYSTEMZ_INS_BIZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* bi${M1} $XBD2 */ + SystemZ_BIC /* 614 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* bic $M1, $XBD2 */ + SystemZ_BICAsm /* 615 */, SYSTEMZ_INS_BIC, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* bpp $M1, $RI2, $BD3 */ + SystemZ_BPP /* 616 */, SYSTEMZ_INS_BPP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREEXECUTIONHINT, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSMI }} + + #endif +}, +{ + /* bprp $M1, $RI2, $RI3 */ + SystemZ_BPRP /* 617 */, SYSTEMZ_INS_BPRP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREEXECUTIONHINT, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTMII }} + + #endif +}, +{ + /* br $R2 */ + SystemZ_BR /* 618 */, SYSTEMZ_INS_BR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bras $R1, $RI2 */ + SystemZ_BRAS /* 619 */, SYSTEMZ_INS_BRAS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_CALL, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIB }} + + #endif +}, +{ + /* brasl $R1, $RI2 */ + SystemZ_BRASL /* 620 */, SYSTEMZ_INS_BRASL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_CALL, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* ber $R2 */ + SystemZ_BRAsmE /* 621 */, SYSTEMZ_INS_BER, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bhr $R2 */ + SystemZ_BRAsmH /* 622 */, SYSTEMZ_INS_BHR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bher $R2 */ + SystemZ_BRAsmHE /* 623 */, SYSTEMZ_INS_BHER, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* blr $R2 */ + SystemZ_BRAsmL /* 624 */, SYSTEMZ_INS_BLR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bler $R2 */ + SystemZ_BRAsmLE /* 625 */, SYSTEMZ_INS_BLER, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* blhr $R2 */ + SystemZ_BRAsmLH /* 626 */, SYSTEMZ_INS_BLHR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bmr $R2 */ + SystemZ_BRAsmM /* 627 */, SYSTEMZ_INS_BMR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bner $R2 */ + SystemZ_BRAsmNE /* 628 */, SYSTEMZ_INS_BNER, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bnhr $R2 */ + SystemZ_BRAsmNH /* 629 */, SYSTEMZ_INS_BNHR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bnher $R2 */ + SystemZ_BRAsmNHE /* 630 */, SYSTEMZ_INS_BNHER, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bnlr $R2 */ + SystemZ_BRAsmNL /* 631 */, SYSTEMZ_INS_BNLR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bnler $R2 */ + SystemZ_BRAsmNLE /* 632 */, SYSTEMZ_INS_BNLER, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bnlhr $R2 */ + SystemZ_BRAsmNLH /* 633 */, SYSTEMZ_INS_BNLHR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bnmr $R2 */ + SystemZ_BRAsmNM /* 634 */, SYSTEMZ_INS_BNMR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bnor $R2 */ + SystemZ_BRAsmNO /* 635 */, SYSTEMZ_INS_BNOR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bnpr $R2 */ + SystemZ_BRAsmNP /* 636 */, SYSTEMZ_INS_BNPR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bnzr $R2 */ + SystemZ_BRAsmNZ /* 637 */, SYSTEMZ_INS_BNZR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bor $R2 */ + SystemZ_BRAsmO /* 638 */, SYSTEMZ_INS_BOR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bpr $R2 */ + SystemZ_BRAsmP /* 639 */, SYSTEMZ_INS_BPR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bzr $R2 */ + SystemZ_BRAsmZ /* 640 */, SYSTEMZ_INS_BZR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* j${M1} $RI2 */ + SystemZ_BRC /* 641 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* brc $M1, $RI2 */ + SystemZ_BRCAsm /* 642 */, SYSTEMZ_INS_BRC, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jg${M1} $RI2 */ + SystemZ_BRCL /* 643 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* brcl $M1, $RI2 */ + SystemZ_BRCLAsm /* 644 */, SYSTEMZ_INS_BRCL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* brct $R1, $RI2 */ + SystemZ_BRCT /* 645 */, SYSTEMZ_INS_BRCT, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIB }} + + #endif +}, +{ + /* brctg $R1, $RI2 */ + SystemZ_BRCTG /* 646 */, SYSTEMZ_INS_BRCTG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIB }} + + #endif +}, +{ + /* brcth $R1, $RI2 */ + SystemZ_BRCTH /* 647 */, SYSTEMZ_INS_BRCTH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* brxh $R1, $R3, $RI2 */ + SystemZ_BRXH /* 648 */, SYSTEMZ_INS_BRXH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSI }} + + #endif +}, +{ + /* brxhg $R1, $R3, $RI2 */ + SystemZ_BRXHG /* 649 */, SYSTEMZ_INS_BRXHG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEE }} + + #endif +}, +{ + /* brxle $R1, $R3, $RI2 */ + SystemZ_BRXLE /* 650 */, SYSTEMZ_INS_BRXLE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSI }} + + #endif +}, +{ + /* brxlg $R1, $R3, $RI2 */ + SystemZ_BRXLG /* 651 */, SYSTEMZ_INS_BRXLG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEE }} + + #endif +}, +{ + /* bsa $R1, $R2 */ + SystemZ_BSA /* 652 */, SYSTEMZ_INS_BSA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* bsg $R1, $R2 */ + SystemZ_BSG /* 653 */, SYSTEMZ_INS_BSG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* bsm $R1, $R2 */ + SystemZ_BSM /* 654 */, SYSTEMZ_INS_BSM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* bxh $R1, $R3, $BD2 */ + SystemZ_BXH /* 655 */, SYSTEMZ_INS_BXH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* bxhg $R1, $R3, $BD2 */ + SystemZ_BXHG /* 656 */, SYSTEMZ_INS_BXHG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* bxle $R1, $R3, $BD2 */ + SystemZ_BXLE /* 657 */, SYSTEMZ_INS_BXLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* bxleg $R1, $R3, $BD2 */ + SystemZ_BXLEG /* 658 */, SYSTEMZ_INS_BXLEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* c $R1, $XBD2 */ + SystemZ_C /* 659 */, SYSTEMZ_INS_C, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* cd $R1, $XBD2 */ + SystemZ_CD /* 660 */, SYSTEMZ_INS_CD, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* cdb $R1, $XBD2 */ + SystemZ_CDB /* 661 */, SYSTEMZ_INS_CDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* cdbr $R1, $R2 */ + SystemZ_CDBR /* 662 */, SYSTEMZ_INS_CDBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cdfbr $R1, $R2 */ + SystemZ_CDFBR /* 663 */, SYSTEMZ_INS_CDFBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cdfbra $R1, $M3, $R2, $M4 */ + SystemZ_CDFBRA /* 664 */, SYSTEMZ_INS_CDFBRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cdfr $R1, $R2 */ + SystemZ_CDFR /* 665 */, SYSTEMZ_INS_CDFR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cdftr $R1, $M3, $R2, $M4 */ + SystemZ_CDFTR /* 666 */, SYSTEMZ_INS_CDFTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cdgbr $R1, $R2 */ + SystemZ_CDGBR /* 667 */, SYSTEMZ_INS_CDGBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cdgbra $R1, $M3, $R2, $M4 */ + SystemZ_CDGBRA /* 668 */, SYSTEMZ_INS_CDGBRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cdgr $R1, $R2 */ + SystemZ_CDGR /* 669 */, SYSTEMZ_INS_CDGR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cdgtr $R1, $R2 */ + SystemZ_CDGTR /* 670 */, SYSTEMZ_INS_CDGTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cdgtra $R1, $M3, $R2, $M4 */ + SystemZ_CDGTRA /* 671 */, SYSTEMZ_INS_CDGTRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cdlfbr $R1, $M3, $R2, $M4 */ + SystemZ_CDLFBR /* 672 */, SYSTEMZ_INS_CDLFBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cdlftr $R1, $M3, $R2, $M4 */ + SystemZ_CDLFTR /* 673 */, SYSTEMZ_INS_CDLFTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cdlgbr $R1, $M3, $R2, $M4 */ + SystemZ_CDLGBR /* 674 */, SYSTEMZ_INS_CDLGBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cdlgtr $R1, $M3, $R2, $M4 */ + SystemZ_CDLGTR /* 675 */, SYSTEMZ_INS_CDLGTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cdpt $R1, $BDL2, $M3 */ + SystemZ_CDPT /* 676 */, SYSTEMZ_INS_CDPT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREDFPPACKEDCONVERSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSLB }} + + #endif +}, +{ + /* cdr $R1, $R2 */ + SystemZ_CDR /* 677 */, SYSTEMZ_INS_CDR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* cds $R1, $R3, $BD2 */ + SystemZ_CDS /* 678 */, SYSTEMZ_INS_CDS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* cdsg $R1, $R3, $BD2 */ + SystemZ_CDSG /* 679 */, SYSTEMZ_INS_CDSG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* cdstr $R1, $R2 */ + SystemZ_CDSTR /* 680 */, SYSTEMZ_INS_CDSTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cdsy $R1, $R3, $BD2 */ + SystemZ_CDSY /* 681 */, SYSTEMZ_INS_CDSY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* cdtr $R1, $R2 */ + SystemZ_CDTR /* 682 */, SYSTEMZ_INS_CDTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cdutr $R1, $R2 */ + SystemZ_CDUTR /* 683 */, SYSTEMZ_INS_CDUTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cdzt $R1, $BDL2, $M3 */ + SystemZ_CDZT /* 684 */, SYSTEMZ_INS_CDZT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREDFPZONEDCONVERSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSLB }} + + #endif +}, +{ + /* ce $R1, $XBD2 */ + SystemZ_CE /* 685 */, SYSTEMZ_INS_CE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* ceb $R1, $XBD2 */ + SystemZ_CEB /* 686 */, SYSTEMZ_INS_CEB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* cebr $R1, $R2 */ + SystemZ_CEBR /* 687 */, SYSTEMZ_INS_CEBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cedtr $R1, $R2 */ + SystemZ_CEDTR /* 688 */, SYSTEMZ_INS_CEDTR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cefbr $R1, $R2 */ + SystemZ_CEFBR /* 689 */, SYSTEMZ_INS_CEFBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cefbra $R1, $M3, $R2, $M4 */ + SystemZ_CEFBRA /* 690 */, SYSTEMZ_INS_CEFBRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cefr $R1, $R2 */ + SystemZ_CEFR /* 691 */, SYSTEMZ_INS_CEFR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cegbr $R1, $R2 */ + SystemZ_CEGBR /* 692 */, SYSTEMZ_INS_CEGBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cegbra $R1, $M3, $R2, $M4 */ + SystemZ_CEGBRA /* 693 */, SYSTEMZ_INS_CEGBRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cegr $R1, $R2 */ + SystemZ_CEGR /* 694 */, SYSTEMZ_INS_CEGR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* celfbr $R1, $M3, $R2, $M4 */ + SystemZ_CELFBR /* 695 */, SYSTEMZ_INS_CELFBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* celgbr $R1, $M3, $R2, $M4 */ + SystemZ_CELGBR /* 696 */, SYSTEMZ_INS_CELGBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cer $R1, $R2 */ + SystemZ_CER /* 697 */, SYSTEMZ_INS_CER, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* cextr $R1, $R2 */ + SystemZ_CEXTR /* 698 */, SYSTEMZ_INS_CEXTR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cfc $BD2 */ + SystemZ_CFC /* 699 */, SYSTEMZ_INS_CFC, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R1D, SYSTEMZ_REG_R2D, SYSTEMZ_REG_R3D, 0 }, { SYSTEMZ_REG_CC, SYSTEMZ_REG_R1D, SYSTEMZ_REG_R2D, SYSTEMZ_REG_R3D, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* cfdbr $R1, $M3, $R2 */ + SystemZ_CFDBR /* 700 */, SYSTEMZ_INS_CFDBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cfdbra $R1, $M3, $R2, $M4 */ + SystemZ_CFDBRA /* 701 */, SYSTEMZ_INS_CFDBRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cfdr $R1, $M3, $R2 */ + SystemZ_CFDR /* 702 */, SYSTEMZ_INS_CFDR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cfdtr $R1, $M3, $R2, $M4 */ + SystemZ_CFDTR /* 703 */, SYSTEMZ_INS_CFDTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cfebr $R1, $M3, $R2 */ + SystemZ_CFEBR /* 704 */, SYSTEMZ_INS_CFEBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cfebra $R1, $M3, $R2, $M4 */ + SystemZ_CFEBRA /* 705 */, SYSTEMZ_INS_CFEBRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cfer $R1, $M3, $R2 */ + SystemZ_CFER /* 706 */, SYSTEMZ_INS_CFER, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cfi $R1, $I2 */ + SystemZ_CFI /* 707 */, SYSTEMZ_INS_CFI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* cfxbr $R1, $M3, $R2 */ + SystemZ_CFXBR /* 708 */, SYSTEMZ_INS_CFXBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cfxbra $R1, $M3, $R2, $M4 */ + SystemZ_CFXBRA /* 709 */, SYSTEMZ_INS_CFXBRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cfxr $R1, $M3, $R2 */ + SystemZ_CFXR /* 710 */, SYSTEMZ_INS_CFXR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cfxtr $R1, $M3, $R2, $M4 */ + SystemZ_CFXTR /* 711 */, SYSTEMZ_INS_CFXTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cg $R1, $XBD2 */ + SystemZ_CG /* 712 */, SYSTEMZ_INS_CG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* cgdbr $R1, $M3, $R2 */ + SystemZ_CGDBR /* 713 */, SYSTEMZ_INS_CGDBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cgdbra $R1, $M3, $R2, $M4 */ + SystemZ_CGDBRA /* 714 */, SYSTEMZ_INS_CGDBRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cgdr $R1, $M3, $R2 */ + SystemZ_CGDR /* 715 */, SYSTEMZ_INS_CGDR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cgdtr $R1, $M3, $R2 */ + SystemZ_CGDTR /* 716 */, SYSTEMZ_INS_CGDTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cgdtra $R1, $M3, $R2, $M4 */ + SystemZ_CGDTRA /* 717 */, SYSTEMZ_INS_CGDTRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cgebr $R1, $M3, $R2 */ + SystemZ_CGEBR /* 718 */, SYSTEMZ_INS_CGEBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cgebra $R1, $M3, $R2, $M4 */ + SystemZ_CGEBRA /* 719 */, SYSTEMZ_INS_CGEBRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cger $R1, $M3, $R2 */ + SystemZ_CGER /* 720 */, SYSTEMZ_INS_CGER, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cgf $R1, $XBD2 */ + SystemZ_CGF /* 721 */, SYSTEMZ_INS_CGF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* cgfi $R1, $I2 */ + SystemZ_CGFI /* 722 */, SYSTEMZ_INS_CGFI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* cgfr $R1, $R2 */ + SystemZ_CGFR /* 723 */, SYSTEMZ_INS_CGFR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cgfrl $R1, $RI2 */ + SystemZ_CGFRL /* 724 */, SYSTEMZ_INS_CGFRL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* cgh $R1, $XBD2 */ + SystemZ_CGH /* 725 */, SYSTEMZ_INS_CGH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* cghi $R1, $I2 */ + SystemZ_CGHI /* 726 */, SYSTEMZ_INS_CGHI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* cghrl $R1, $RI2 */ + SystemZ_CGHRL /* 727 */, SYSTEMZ_INS_CGHRL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* cghsi $BD1, $I2 */ + SystemZ_CGHSI /* 728 */, SYSTEMZ_INS_CGHSI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIL }} + + #endif +}, +{ + /* cgib$M3 $R1, $I2, $BD4 */ + SystemZ_CGIB /* 729 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cgib $R1, $I2, $M3, $BD4 */ + SystemZ_CGIBAsm /* 730 */, SYSTEMZ_INS_CGIB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cgibe $R1, $I2, $BD4 */ + SystemZ_CGIBAsmE /* 731 */, SYSTEMZ_INS_CGIBE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cgibh $R1, $I2, $BD4 */ + SystemZ_CGIBAsmH /* 732 */, SYSTEMZ_INS_CGIBH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cgibhe $R1, $I2, $BD4 */ + SystemZ_CGIBAsmHE /* 733 */, SYSTEMZ_INS_CGIBHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cgibl $R1, $I2, $BD4 */ + SystemZ_CGIBAsmL /* 734 */, SYSTEMZ_INS_CGIBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cgible $R1, $I2, $BD4 */ + SystemZ_CGIBAsmLE /* 735 */, SYSTEMZ_INS_CGIBLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cgiblh $R1, $I2, $BD4 */ + SystemZ_CGIBAsmLH /* 736 */, SYSTEMZ_INS_CGIBLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cgibne $R1, $I2, $BD4 */ + SystemZ_CGIBAsmNE /* 737 */, SYSTEMZ_INS_CGIBNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cgibnh $R1, $I2, $BD4 */ + SystemZ_CGIBAsmNH /* 738 */, SYSTEMZ_INS_CGIBNH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cgibnhe $R1, $I2, $BD4 */ + SystemZ_CGIBAsmNHE /* 739 */, SYSTEMZ_INS_CGIBNHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cgibnl $R1, $I2, $BD4 */ + SystemZ_CGIBAsmNL /* 740 */, SYSTEMZ_INS_CGIBNL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cgibnle $R1, $I2, $BD4 */ + SystemZ_CGIBAsmNLE /* 741 */, SYSTEMZ_INS_CGIBNLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cgibnlh $R1, $I2, $BD4 */ + SystemZ_CGIBAsmNLH /* 742 */, SYSTEMZ_INS_CGIBNLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cgij$M3 $R1, $I2, $RI4 */ + SystemZ_CGIJ /* 743 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cgij $R1, $I2, $M3, $RI4 */ + SystemZ_CGIJAsm /* 744 */, SYSTEMZ_INS_CGIJ, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cgije $R1, $I2, $RI4 */ + SystemZ_CGIJAsmE /* 745 */, SYSTEMZ_INS_CGIJE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cgijh $R1, $I2, $RI4 */ + SystemZ_CGIJAsmH /* 746 */, SYSTEMZ_INS_CGIJH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cgijhe $R1, $I2, $RI4 */ + SystemZ_CGIJAsmHE /* 747 */, SYSTEMZ_INS_CGIJHE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cgijl $R1, $I2, $RI4 */ + SystemZ_CGIJAsmL /* 748 */, SYSTEMZ_INS_CGIJL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cgijle $R1, $I2, $RI4 */ + SystemZ_CGIJAsmLE /* 749 */, SYSTEMZ_INS_CGIJLE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cgijlh $R1, $I2, $RI4 */ + SystemZ_CGIJAsmLH /* 750 */, SYSTEMZ_INS_CGIJLH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cgijne $R1, $I2, $RI4 */ + SystemZ_CGIJAsmNE /* 751 */, SYSTEMZ_INS_CGIJNE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cgijnh $R1, $I2, $RI4 */ + SystemZ_CGIJAsmNH /* 752 */, SYSTEMZ_INS_CGIJNH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cgijnhe $R1, $I2, $RI4 */ + SystemZ_CGIJAsmNHE /* 753 */, SYSTEMZ_INS_CGIJNHE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cgijnl $R1, $I2, $RI4 */ + SystemZ_CGIJAsmNL /* 754 */, SYSTEMZ_INS_CGIJNL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cgijnle $R1, $I2, $RI4 */ + SystemZ_CGIJAsmNLE /* 755 */, SYSTEMZ_INS_CGIJNLE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cgijnlh $R1, $I2, $RI4 */ + SystemZ_CGIJAsmNLH /* 756 */, SYSTEMZ_INS_CGIJNLH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cgit$M3 $R1, $I2 */ + SystemZ_CGIT /* 757 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cgit $R1, $I2, $M3 */ + SystemZ_CGITAsm /* 758 */, SYSTEMZ_INS_CGIT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* cgite $R1, $I2 */ + SystemZ_CGITAsmE /* 759 */, SYSTEMZ_INS_CGITE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* cgith $R1, $I2 */ + SystemZ_CGITAsmH /* 760 */, SYSTEMZ_INS_CGITH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* cgithe $R1, $I2 */ + SystemZ_CGITAsmHE /* 761 */, SYSTEMZ_INS_CGITHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* cgitl $R1, $I2 */ + SystemZ_CGITAsmL /* 762 */, SYSTEMZ_INS_CGITL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* cgitle $R1, $I2 */ + SystemZ_CGITAsmLE /* 763 */, SYSTEMZ_INS_CGITLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* cgitlh $R1, $I2 */ + SystemZ_CGITAsmLH /* 764 */, SYSTEMZ_INS_CGITLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* cgitne $R1, $I2 */ + SystemZ_CGITAsmNE /* 765 */, SYSTEMZ_INS_CGITNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* cgitnh $R1, $I2 */ + SystemZ_CGITAsmNH /* 766 */, SYSTEMZ_INS_CGITNH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* cgitnhe $R1, $I2 */ + SystemZ_CGITAsmNHE /* 767 */, SYSTEMZ_INS_CGITNHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* cgitnl $R1, $I2 */ + SystemZ_CGITAsmNL /* 768 */, SYSTEMZ_INS_CGITNL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* cgitnle $R1, $I2 */ + SystemZ_CGITAsmNLE /* 769 */, SYSTEMZ_INS_CGITNLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* cgitnlh $R1, $I2 */ + SystemZ_CGITAsmNLH /* 770 */, SYSTEMZ_INS_CGITNLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* cgr $R1, $R2 */ + SystemZ_CGR /* 771 */, SYSTEMZ_INS_CGR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cgrb$M3 $R1, $R2, $BD4 */ + SystemZ_CGRB /* 772 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cgrb $R1, $R2, $M3, $BD4 */ + SystemZ_CGRBAsm /* 773 */, SYSTEMZ_INS_CGRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* cgrbe $R1, $R2, $BD4 */ + SystemZ_CGRBAsmE /* 774 */, SYSTEMZ_INS_CGRBE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* cgrbh $R1, $R2, $BD4 */ + SystemZ_CGRBAsmH /* 775 */, SYSTEMZ_INS_CGRBH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* cgrbhe $R1, $R2, $BD4 */ + SystemZ_CGRBAsmHE /* 776 */, SYSTEMZ_INS_CGRBHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* cgrbl $R1, $R2, $BD4 */ + SystemZ_CGRBAsmL /* 777 */, SYSTEMZ_INS_CGRBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* cgrble $R1, $R2, $BD4 */ + SystemZ_CGRBAsmLE /* 778 */, SYSTEMZ_INS_CGRBLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* cgrblh $R1, $R2, $BD4 */ + SystemZ_CGRBAsmLH /* 779 */, SYSTEMZ_INS_CGRBLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* cgrbne $R1, $R2, $BD4 */ + SystemZ_CGRBAsmNE /* 780 */, SYSTEMZ_INS_CGRBNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* cgrbnh $R1, $R2, $BD4 */ + SystemZ_CGRBAsmNH /* 781 */, SYSTEMZ_INS_CGRBNH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* cgrbnhe $R1, $R2, $BD4 */ + SystemZ_CGRBAsmNHE /* 782 */, SYSTEMZ_INS_CGRBNHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* cgrbnl $R1, $R2, $BD4 */ + SystemZ_CGRBAsmNL /* 783 */, SYSTEMZ_INS_CGRBNL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* cgrbnle $R1, $R2, $BD4 */ + SystemZ_CGRBAsmNLE /* 784 */, SYSTEMZ_INS_CGRBNLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* cgrbnlh $R1, $R2, $BD4 */ + SystemZ_CGRBAsmNLH /* 785 */, SYSTEMZ_INS_CGRBNLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* cgrj$M3 $R1, $R2, $RI4 */ + SystemZ_CGRJ /* 786 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cgrj $R1, $R2, $M3, $RI4 */ + SystemZ_CGRJAsm /* 787 */, SYSTEMZ_INS_CGRJ, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* cgrje $R1, $R2, $RI4 */ + SystemZ_CGRJAsmE /* 788 */, SYSTEMZ_INS_CGRJE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* cgrjh $R1, $R2, $RI4 */ + SystemZ_CGRJAsmH /* 789 */, SYSTEMZ_INS_CGRJH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* cgrjhe $R1, $R2, $RI4 */ + SystemZ_CGRJAsmHE /* 790 */, SYSTEMZ_INS_CGRJHE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* cgrjl $R1, $R2, $RI4 */ + SystemZ_CGRJAsmL /* 791 */, SYSTEMZ_INS_CGRJL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* cgrjle $R1, $R2, $RI4 */ + SystemZ_CGRJAsmLE /* 792 */, SYSTEMZ_INS_CGRJLE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* cgrjlh $R1, $R2, $RI4 */ + SystemZ_CGRJAsmLH /* 793 */, SYSTEMZ_INS_CGRJLH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* cgrjne $R1, $R2, $RI4 */ + SystemZ_CGRJAsmNE /* 794 */, SYSTEMZ_INS_CGRJNE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* cgrjnh $R1, $R2, $RI4 */ + SystemZ_CGRJAsmNH /* 795 */, SYSTEMZ_INS_CGRJNH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* cgrjnhe $R1, $R2, $RI4 */ + SystemZ_CGRJAsmNHE /* 796 */, SYSTEMZ_INS_CGRJNHE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* cgrjnl $R1, $R2, $RI4 */ + SystemZ_CGRJAsmNL /* 797 */, SYSTEMZ_INS_CGRJNL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* cgrjnle $R1, $R2, $RI4 */ + SystemZ_CGRJAsmNLE /* 798 */, SYSTEMZ_INS_CGRJNLE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* cgrjnlh $R1, $R2, $RI4 */ + SystemZ_CGRJAsmNLH /* 799 */, SYSTEMZ_INS_CGRJNLH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* cgrl $R1, $RI2 */ + SystemZ_CGRL /* 800 */, SYSTEMZ_INS_CGRL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* cgrt$M3 $R1, $R2 */ + SystemZ_CGRT /* 801 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cgrt $R1, $R2, $M3 */ + SystemZ_CGRTAsm /* 802 */, SYSTEMZ_INS_CGRT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cgrte $R1, $R2 */ + SystemZ_CGRTAsmE /* 803 */, SYSTEMZ_INS_CGRTE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cgrth $R1, $R2 */ + SystemZ_CGRTAsmH /* 804 */, SYSTEMZ_INS_CGRTH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cgrthe $R1, $R2 */ + SystemZ_CGRTAsmHE /* 805 */, SYSTEMZ_INS_CGRTHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cgrtl $R1, $R2 */ + SystemZ_CGRTAsmL /* 806 */, SYSTEMZ_INS_CGRTL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cgrtle $R1, $R2 */ + SystemZ_CGRTAsmLE /* 807 */, SYSTEMZ_INS_CGRTLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cgrtlh $R1, $R2 */ + SystemZ_CGRTAsmLH /* 808 */, SYSTEMZ_INS_CGRTLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cgrtne $R1, $R2 */ + SystemZ_CGRTAsmNE /* 809 */, SYSTEMZ_INS_CGRTNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cgrtnh $R1, $R2 */ + SystemZ_CGRTAsmNH /* 810 */, SYSTEMZ_INS_CGRTNH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cgrtnhe $R1, $R2 */ + SystemZ_CGRTAsmNHE /* 811 */, SYSTEMZ_INS_CGRTNHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cgrtnl $R1, $R2 */ + SystemZ_CGRTAsmNL /* 812 */, SYSTEMZ_INS_CGRTNL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cgrtnle $R1, $R2 */ + SystemZ_CGRTAsmNLE /* 813 */, SYSTEMZ_INS_CGRTNLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cgrtnlh $R1, $R2 */ + SystemZ_CGRTAsmNLH /* 814 */, SYSTEMZ_INS_CGRTNLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cgxbr $R1, $M3, $R2 */ + SystemZ_CGXBR /* 815 */, SYSTEMZ_INS_CGXBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cgxbra $R1, $M3, $R2, $M4 */ + SystemZ_CGXBRA /* 816 */, SYSTEMZ_INS_CGXBRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cgxr $R1, $M3, $R2 */ + SystemZ_CGXR /* 817 */, SYSTEMZ_INS_CGXR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cgxtr $R1, $M3, $R2 */ + SystemZ_CGXTR /* 818 */, SYSTEMZ_INS_CGXTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cgxtra $R1, $M3, $R2, $M4 */ + SystemZ_CGXTRA /* 819 */, SYSTEMZ_INS_CGXTRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* ch $R1, $XBD2 */ + SystemZ_CH /* 820 */, SYSTEMZ_INS_CH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* chf $R1, $XBD2 */ + SystemZ_CHF /* 821 */, SYSTEMZ_INS_CHF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* chhr $R1, $R2 */ + SystemZ_CHHR /* 822 */, SYSTEMZ_INS_CHHR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* chhsi $BD1, $I2 */ + SystemZ_CHHSI /* 823 */, SYSTEMZ_INS_CHHSI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIL }} + + #endif +}, +{ + /* chi $R1, $I2 */ + SystemZ_CHI /* 824 */, SYSTEMZ_INS_CHI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* chlr $R1, $R2 */ + SystemZ_CHLR /* 825 */, SYSTEMZ_INS_CHLR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* chrl $R1, $RI2 */ + SystemZ_CHRL /* 826 */, SYSTEMZ_INS_CHRL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* chsi $BD1, $I2 */ + SystemZ_CHSI /* 827 */, SYSTEMZ_INS_CHSI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIL }} + + #endif +}, +{ + /* chy $R1, $XBD2 */ + SystemZ_CHY /* 828 */, SYSTEMZ_INS_CHY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* cib$M3 $R1, $I2, $BD4 */ + SystemZ_CIB /* 829 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cib $R1, $I2, $M3, $BD4 */ + SystemZ_CIBAsm /* 830 */, SYSTEMZ_INS_CIB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cibe $R1, $I2, $BD4 */ + SystemZ_CIBAsmE /* 831 */, SYSTEMZ_INS_CIBE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cibh $R1, $I2, $BD4 */ + SystemZ_CIBAsmH /* 832 */, SYSTEMZ_INS_CIBH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cibhe $R1, $I2, $BD4 */ + SystemZ_CIBAsmHE /* 833 */, SYSTEMZ_INS_CIBHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cibl $R1, $I2, $BD4 */ + SystemZ_CIBAsmL /* 834 */, SYSTEMZ_INS_CIBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cible $R1, $I2, $BD4 */ + SystemZ_CIBAsmLE /* 835 */, SYSTEMZ_INS_CIBLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* ciblh $R1, $I2, $BD4 */ + SystemZ_CIBAsmLH /* 836 */, SYSTEMZ_INS_CIBLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cibne $R1, $I2, $BD4 */ + SystemZ_CIBAsmNE /* 837 */, SYSTEMZ_INS_CIBNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cibnh $R1, $I2, $BD4 */ + SystemZ_CIBAsmNH /* 838 */, SYSTEMZ_INS_CIBNH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cibnhe $R1, $I2, $BD4 */ + SystemZ_CIBAsmNHE /* 839 */, SYSTEMZ_INS_CIBNHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cibnl $R1, $I2, $BD4 */ + SystemZ_CIBAsmNL /* 840 */, SYSTEMZ_INS_CIBNL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cibnle $R1, $I2, $BD4 */ + SystemZ_CIBAsmNLE /* 841 */, SYSTEMZ_INS_CIBNLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cibnlh $R1, $I2, $BD4 */ + SystemZ_CIBAsmNLH /* 842 */, SYSTEMZ_INS_CIBNLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cih $R1, $I2 */ + SystemZ_CIH /* 843 */, SYSTEMZ_INS_CIH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* cij$M3 $R1, $I2, $RI4 */ + SystemZ_CIJ /* 844 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cij $R1, $I2, $M3, $RI4 */ + SystemZ_CIJAsm /* 845 */, SYSTEMZ_INS_CIJ, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cije $R1, $I2, $RI4 */ + SystemZ_CIJAsmE /* 846 */, SYSTEMZ_INS_CIJE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cijh $R1, $I2, $RI4 */ + SystemZ_CIJAsmH /* 847 */, SYSTEMZ_INS_CIJH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cijhe $R1, $I2, $RI4 */ + SystemZ_CIJAsmHE /* 848 */, SYSTEMZ_INS_CIJHE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cijl $R1, $I2, $RI4 */ + SystemZ_CIJAsmL /* 849 */, SYSTEMZ_INS_CIJL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cijle $R1, $I2, $RI4 */ + SystemZ_CIJAsmLE /* 850 */, SYSTEMZ_INS_CIJLE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cijlh $R1, $I2, $RI4 */ + SystemZ_CIJAsmLH /* 851 */, SYSTEMZ_INS_CIJLH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cijne $R1, $I2, $RI4 */ + SystemZ_CIJAsmNE /* 852 */, SYSTEMZ_INS_CIJNE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cijnh $R1, $I2, $RI4 */ + SystemZ_CIJAsmNH /* 853 */, SYSTEMZ_INS_CIJNH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cijnhe $R1, $I2, $RI4 */ + SystemZ_CIJAsmNHE /* 854 */, SYSTEMZ_INS_CIJNHE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cijnl $R1, $I2, $RI4 */ + SystemZ_CIJAsmNL /* 855 */, SYSTEMZ_INS_CIJNL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cijnle $R1, $I2, $RI4 */ + SystemZ_CIJAsmNLE /* 856 */, SYSTEMZ_INS_CIJNLE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cijnlh $R1, $I2, $RI4 */ + SystemZ_CIJAsmNLH /* 857 */, SYSTEMZ_INS_CIJNLH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cit$M3 $R1, $I2 */ + SystemZ_CIT /* 858 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cit $R1, $I2, $M3 */ + SystemZ_CITAsm /* 859 */, SYSTEMZ_INS_CIT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* cite $R1, $I2 */ + SystemZ_CITAsmE /* 860 */, SYSTEMZ_INS_CITE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* cith $R1, $I2 */ + SystemZ_CITAsmH /* 861 */, SYSTEMZ_INS_CITH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* cithe $R1, $I2 */ + SystemZ_CITAsmHE /* 862 */, SYSTEMZ_INS_CITHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* citl $R1, $I2 */ + SystemZ_CITAsmL /* 863 */, SYSTEMZ_INS_CITL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* citle $R1, $I2 */ + SystemZ_CITAsmLE /* 864 */, SYSTEMZ_INS_CITLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* citlh $R1, $I2 */ + SystemZ_CITAsmLH /* 865 */, SYSTEMZ_INS_CITLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* citne $R1, $I2 */ + SystemZ_CITAsmNE /* 866 */, SYSTEMZ_INS_CITNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* citnh $R1, $I2 */ + SystemZ_CITAsmNH /* 867 */, SYSTEMZ_INS_CITNH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* citnhe $R1, $I2 */ + SystemZ_CITAsmNHE /* 868 */, SYSTEMZ_INS_CITNHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* citnl $R1, $I2 */ + SystemZ_CITAsmNL /* 869 */, SYSTEMZ_INS_CITNL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* citnle $R1, $I2 */ + SystemZ_CITAsmNLE /* 870 */, SYSTEMZ_INS_CITNLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* citnlh $R1, $I2 */ + SystemZ_CITAsmNLH /* 871 */, SYSTEMZ_INS_CITNLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* cksm $R1, $R2 */ + SystemZ_CKSM /* 872 */, SYSTEMZ_INS_CKSM, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cl $R1, $XBD2 */ + SystemZ_CL /* 873 */, SYSTEMZ_INS_CL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* clc $BDL1, $BD2 */ + SystemZ_CLC /* 874 */, SYSTEMZ_INS_CLC, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSA }} + + #endif +}, +{ + /* clcl $R1, $R2 */ + SystemZ_CLCL /* 875 */, SYSTEMZ_INS_CLCL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* clcle $R1, $R3, $BD2 */ + SystemZ_CLCLE /* 876 */, SYSTEMZ_INS_CLCLE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* clclu $R1, $R3, $BD2 */ + SystemZ_CLCLU /* 877 */, SYSTEMZ_INS_CLCLU, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* clfdbr $R1, $M3, $R2, $M4 */ + SystemZ_CLFDBR /* 878 */, SYSTEMZ_INS_CLFDBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* clfdtr $R1, $M3, $R2, $M4 */ + SystemZ_CLFDTR /* 879 */, SYSTEMZ_INS_CLFDTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* clfebr $R1, $M3, $R2, $M4 */ + SystemZ_CLFEBR /* 880 */, SYSTEMZ_INS_CLFEBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* clfhsi $BD1, $I2 */ + SystemZ_CLFHSI /* 881 */, SYSTEMZ_INS_CLFHSI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIL }} + + #endif +}, +{ + /* clfi $R1, $I2 */ + SystemZ_CLFI /* 882 */, SYSTEMZ_INS_CLFI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* clfit$M3 $R1, $I2 */ + SystemZ_CLFIT /* 883 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* clfit $R1, $I2, $M3 */ + SystemZ_CLFITAsm /* 884 */, SYSTEMZ_INS_CLFIT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clfite $R1, $I2 */ + SystemZ_CLFITAsmE /* 885 */, SYSTEMZ_INS_CLFITE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clfith $R1, $I2 */ + SystemZ_CLFITAsmH /* 886 */, SYSTEMZ_INS_CLFITH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clfithe $R1, $I2 */ + SystemZ_CLFITAsmHE /* 887 */, SYSTEMZ_INS_CLFITHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clfitl $R1, $I2 */ + SystemZ_CLFITAsmL /* 888 */, SYSTEMZ_INS_CLFITL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clfitle $R1, $I2 */ + SystemZ_CLFITAsmLE /* 889 */, SYSTEMZ_INS_CLFITLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clfitlh $R1, $I2 */ + SystemZ_CLFITAsmLH /* 890 */, SYSTEMZ_INS_CLFITLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clfitne $R1, $I2 */ + SystemZ_CLFITAsmNE /* 891 */, SYSTEMZ_INS_CLFITNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clfitnh $R1, $I2 */ + SystemZ_CLFITAsmNH /* 892 */, SYSTEMZ_INS_CLFITNH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clfitnhe $R1, $I2 */ + SystemZ_CLFITAsmNHE /* 893 */, SYSTEMZ_INS_CLFITNHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clfitnl $R1, $I2 */ + SystemZ_CLFITAsmNL /* 894 */, SYSTEMZ_INS_CLFITNL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clfitnle $R1, $I2 */ + SystemZ_CLFITAsmNLE /* 895 */, SYSTEMZ_INS_CLFITNLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clfitnlh $R1, $I2 */ + SystemZ_CLFITAsmNLH /* 896 */, SYSTEMZ_INS_CLFITNLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clfxbr $R1, $M3, $R2, $M4 */ + SystemZ_CLFXBR /* 897 */, SYSTEMZ_INS_CLFXBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* clfxtr $R1, $M3, $R2, $M4 */ + SystemZ_CLFXTR /* 898 */, SYSTEMZ_INS_CLFXTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* clg $R1, $XBD2 */ + SystemZ_CLG /* 899 */, SYSTEMZ_INS_CLG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* clgdbr $R1, $M3, $R2, $M4 */ + SystemZ_CLGDBR /* 900 */, SYSTEMZ_INS_CLGDBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* clgdtr $R1, $M3, $R2, $M4 */ + SystemZ_CLGDTR /* 901 */, SYSTEMZ_INS_CLGDTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* clgebr $R1, $M3, $R2, $M4 */ + SystemZ_CLGEBR /* 902 */, SYSTEMZ_INS_CLGEBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* clgf $R1, $XBD2 */ + SystemZ_CLGF /* 903 */, SYSTEMZ_INS_CLGF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* clgfi $R1, $I2 */ + SystemZ_CLGFI /* 904 */, SYSTEMZ_INS_CLGFI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* clgfr $R1, $R2 */ + SystemZ_CLGFR /* 905 */, SYSTEMZ_INS_CLGFR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* clgfrl $R1, $RI2 */ + SystemZ_CLGFRL /* 906 */, SYSTEMZ_INS_CLGFRL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* clghrl $R1, $RI2 */ + SystemZ_CLGHRL /* 907 */, SYSTEMZ_INS_CLGHRL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* clghsi $BD1, $I2 */ + SystemZ_CLGHSI /* 908 */, SYSTEMZ_INS_CLGHSI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIL }} + + #endif +}, +{ + /* clgib$M3 $R1, $I2, $BD4 */ + SystemZ_CLGIB /* 909 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* clgib $R1, $I2, $M3, $BD4 */ + SystemZ_CLGIBAsm /* 910 */, SYSTEMZ_INS_CLGIB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clgibe $R1, $I2, $BD4 */ + SystemZ_CLGIBAsmE /* 911 */, SYSTEMZ_INS_CLGIBE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clgibh $R1, $I2, $BD4 */ + SystemZ_CLGIBAsmH /* 912 */, SYSTEMZ_INS_CLGIBH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clgibhe $R1, $I2, $BD4 */ + SystemZ_CLGIBAsmHE /* 913 */, SYSTEMZ_INS_CLGIBHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clgibl $R1, $I2, $BD4 */ + SystemZ_CLGIBAsmL /* 914 */, SYSTEMZ_INS_CLGIBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clgible $R1, $I2, $BD4 */ + SystemZ_CLGIBAsmLE /* 915 */, SYSTEMZ_INS_CLGIBLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clgiblh $R1, $I2, $BD4 */ + SystemZ_CLGIBAsmLH /* 916 */, SYSTEMZ_INS_CLGIBLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clgibne $R1, $I2, $BD4 */ + SystemZ_CLGIBAsmNE /* 917 */, SYSTEMZ_INS_CLGIBNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clgibnh $R1, $I2, $BD4 */ + SystemZ_CLGIBAsmNH /* 918 */, SYSTEMZ_INS_CLGIBNH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clgibnhe $R1, $I2, $BD4 */ + SystemZ_CLGIBAsmNHE /* 919 */, SYSTEMZ_INS_CLGIBNHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clgibnl $R1, $I2, $BD4 */ + SystemZ_CLGIBAsmNL /* 920 */, SYSTEMZ_INS_CLGIBNL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clgibnle $R1, $I2, $BD4 */ + SystemZ_CLGIBAsmNLE /* 921 */, SYSTEMZ_INS_CLGIBNLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clgibnlh $R1, $I2, $BD4 */ + SystemZ_CLGIBAsmNLH /* 922 */, SYSTEMZ_INS_CLGIBNLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clgij$M3 $R1, $I2, $RI4 */ + SystemZ_CLGIJ /* 923 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* clgij $R1, $I2, $M3, $RI4 */ + SystemZ_CLGIJAsm /* 924 */, SYSTEMZ_INS_CLGIJ, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clgije $R1, $I2, $RI4 */ + SystemZ_CLGIJAsmE /* 925 */, SYSTEMZ_INS_CLGIJE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clgijh $R1, $I2, $RI4 */ + SystemZ_CLGIJAsmH /* 926 */, SYSTEMZ_INS_CLGIJH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clgijhe $R1, $I2, $RI4 */ + SystemZ_CLGIJAsmHE /* 927 */, SYSTEMZ_INS_CLGIJHE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clgijl $R1, $I2, $RI4 */ + SystemZ_CLGIJAsmL /* 928 */, SYSTEMZ_INS_CLGIJL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clgijle $R1, $I2, $RI4 */ + SystemZ_CLGIJAsmLE /* 929 */, SYSTEMZ_INS_CLGIJLE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clgijlh $R1, $I2, $RI4 */ + SystemZ_CLGIJAsmLH /* 930 */, SYSTEMZ_INS_CLGIJLH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clgijne $R1, $I2, $RI4 */ + SystemZ_CLGIJAsmNE /* 931 */, SYSTEMZ_INS_CLGIJNE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clgijnh $R1, $I2, $RI4 */ + SystemZ_CLGIJAsmNH /* 932 */, SYSTEMZ_INS_CLGIJNH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clgijnhe $R1, $I2, $RI4 */ + SystemZ_CLGIJAsmNHE /* 933 */, SYSTEMZ_INS_CLGIJNHE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clgijnl $R1, $I2, $RI4 */ + SystemZ_CLGIJAsmNL /* 934 */, SYSTEMZ_INS_CLGIJNL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clgijnle $R1, $I2, $RI4 */ + SystemZ_CLGIJAsmNLE /* 935 */, SYSTEMZ_INS_CLGIJNLE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clgijnlh $R1, $I2, $RI4 */ + SystemZ_CLGIJAsmNLH /* 936 */, SYSTEMZ_INS_CLGIJNLH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clgit$M3 $R1, $I2 */ + SystemZ_CLGIT /* 937 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* clgit $R1, $I2, $M3 */ + SystemZ_CLGITAsm /* 938 */, SYSTEMZ_INS_CLGIT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clgite $R1, $I2 */ + SystemZ_CLGITAsmE /* 939 */, SYSTEMZ_INS_CLGITE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clgith $R1, $I2 */ + SystemZ_CLGITAsmH /* 940 */, SYSTEMZ_INS_CLGITH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clgithe $R1, $I2 */ + SystemZ_CLGITAsmHE /* 941 */, SYSTEMZ_INS_CLGITHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clgitl $R1, $I2 */ + SystemZ_CLGITAsmL /* 942 */, SYSTEMZ_INS_CLGITL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clgitle $R1, $I2 */ + SystemZ_CLGITAsmLE /* 943 */, SYSTEMZ_INS_CLGITLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clgitlh $R1, $I2 */ + SystemZ_CLGITAsmLH /* 944 */, SYSTEMZ_INS_CLGITLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clgitne $R1, $I2 */ + SystemZ_CLGITAsmNE /* 945 */, SYSTEMZ_INS_CLGITNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clgitnh $R1, $I2 */ + SystemZ_CLGITAsmNH /* 946 */, SYSTEMZ_INS_CLGITNH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clgitnhe $R1, $I2 */ + SystemZ_CLGITAsmNHE /* 947 */, SYSTEMZ_INS_CLGITNHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clgitnl $R1, $I2 */ + SystemZ_CLGITAsmNL /* 948 */, SYSTEMZ_INS_CLGITNL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clgitnle $R1, $I2 */ + SystemZ_CLGITAsmNLE /* 949 */, SYSTEMZ_INS_CLGITNLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clgitnlh $R1, $I2 */ + SystemZ_CLGITAsmNLH /* 950 */, SYSTEMZ_INS_CLGITNLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEA }} + + #endif +}, +{ + /* clgr $R1, $R2 */ + SystemZ_CLGR /* 951 */, SYSTEMZ_INS_CLGR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* clgrb$M3 $R1, $R2, $BD4 */ + SystemZ_CLGRB /* 952 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* clgrb $R1, $R2, $M3, $BD4 */ + SystemZ_CLGRBAsm /* 953 */, SYSTEMZ_INS_CLGRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clgrbe $R1, $R2, $BD4 */ + SystemZ_CLGRBAsmE /* 954 */, SYSTEMZ_INS_CLGRBE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clgrbh $R1, $R2, $BD4 */ + SystemZ_CLGRBAsmH /* 955 */, SYSTEMZ_INS_CLGRBH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clgrbhe $R1, $R2, $BD4 */ + SystemZ_CLGRBAsmHE /* 956 */, SYSTEMZ_INS_CLGRBHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clgrbl $R1, $R2, $BD4 */ + SystemZ_CLGRBAsmL /* 957 */, SYSTEMZ_INS_CLGRBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clgrble $R1, $R2, $BD4 */ + SystemZ_CLGRBAsmLE /* 958 */, SYSTEMZ_INS_CLGRBLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clgrblh $R1, $R2, $BD4 */ + SystemZ_CLGRBAsmLH /* 959 */, SYSTEMZ_INS_CLGRBLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clgrbne $R1, $R2, $BD4 */ + SystemZ_CLGRBAsmNE /* 960 */, SYSTEMZ_INS_CLGRBNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clgrbnh $R1, $R2, $BD4 */ + SystemZ_CLGRBAsmNH /* 961 */, SYSTEMZ_INS_CLGRBNH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clgrbnhe $R1, $R2, $BD4 */ + SystemZ_CLGRBAsmNHE /* 962 */, SYSTEMZ_INS_CLGRBNHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clgrbnl $R1, $R2, $BD4 */ + SystemZ_CLGRBAsmNL /* 963 */, SYSTEMZ_INS_CLGRBNL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clgrbnle $R1, $R2, $BD4 */ + SystemZ_CLGRBAsmNLE /* 964 */, SYSTEMZ_INS_CLGRBNLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clgrbnlh $R1, $R2, $BD4 */ + SystemZ_CLGRBAsmNLH /* 965 */, SYSTEMZ_INS_CLGRBNLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clgrj$M3 $R1, $R2, $RI4 */ + SystemZ_CLGRJ /* 966 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* clgrj $R1, $R2, $M3, $RI4 */ + SystemZ_CLGRJAsm /* 967 */, SYSTEMZ_INS_CLGRJ, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clgrje $R1, $R2, $RI4 */ + SystemZ_CLGRJAsmE /* 968 */, SYSTEMZ_INS_CLGRJE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clgrjh $R1, $R2, $RI4 */ + SystemZ_CLGRJAsmH /* 969 */, SYSTEMZ_INS_CLGRJH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clgrjhe $R1, $R2, $RI4 */ + SystemZ_CLGRJAsmHE /* 970 */, SYSTEMZ_INS_CLGRJHE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clgrjl $R1, $R2, $RI4 */ + SystemZ_CLGRJAsmL /* 971 */, SYSTEMZ_INS_CLGRJL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clgrjle $R1, $R2, $RI4 */ + SystemZ_CLGRJAsmLE /* 972 */, SYSTEMZ_INS_CLGRJLE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clgrjlh $R1, $R2, $RI4 */ + SystemZ_CLGRJAsmLH /* 973 */, SYSTEMZ_INS_CLGRJLH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clgrjne $R1, $R2, $RI4 */ + SystemZ_CLGRJAsmNE /* 974 */, SYSTEMZ_INS_CLGRJNE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clgrjnh $R1, $R2, $RI4 */ + SystemZ_CLGRJAsmNH /* 975 */, SYSTEMZ_INS_CLGRJNH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clgrjnhe $R1, $R2, $RI4 */ + SystemZ_CLGRJAsmNHE /* 976 */, SYSTEMZ_INS_CLGRJNHE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clgrjnl $R1, $R2, $RI4 */ + SystemZ_CLGRJAsmNL /* 977 */, SYSTEMZ_INS_CLGRJNL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clgrjnle $R1, $R2, $RI4 */ + SystemZ_CLGRJAsmNLE /* 978 */, SYSTEMZ_INS_CLGRJNLE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clgrjnlh $R1, $R2, $RI4 */ + SystemZ_CLGRJAsmNLH /* 979 */, SYSTEMZ_INS_CLGRJNLH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clgrl $R1, $RI2 */ + SystemZ_CLGRL /* 980 */, SYSTEMZ_INS_CLGRL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* clgrt$M3 $R1, $R2 */ + SystemZ_CLGRT /* 981 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* clgrt $R1, $R2, $M3 */ + SystemZ_CLGRTAsm /* 982 */, SYSTEMZ_INS_CLGRT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clgrte $R1, $R2 */ + SystemZ_CLGRTAsmE /* 983 */, SYSTEMZ_INS_CLGRTE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clgrth $R1, $R2 */ + SystemZ_CLGRTAsmH /* 984 */, SYSTEMZ_INS_CLGRTH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clgrthe $R1, $R2 */ + SystemZ_CLGRTAsmHE /* 985 */, SYSTEMZ_INS_CLGRTHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clgrtl $R1, $R2 */ + SystemZ_CLGRTAsmL /* 986 */, SYSTEMZ_INS_CLGRTL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clgrtle $R1, $R2 */ + SystemZ_CLGRTAsmLE /* 987 */, SYSTEMZ_INS_CLGRTLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clgrtlh $R1, $R2 */ + SystemZ_CLGRTAsmLH /* 988 */, SYSTEMZ_INS_CLGRTLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clgrtne $R1, $R2 */ + SystemZ_CLGRTAsmNE /* 989 */, SYSTEMZ_INS_CLGRTNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clgrtnh $R1, $R2 */ + SystemZ_CLGRTAsmNH /* 990 */, SYSTEMZ_INS_CLGRTNH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clgrtnhe $R1, $R2 */ + SystemZ_CLGRTAsmNHE /* 991 */, SYSTEMZ_INS_CLGRTNHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clgrtnl $R1, $R2 */ + SystemZ_CLGRTAsmNL /* 992 */, SYSTEMZ_INS_CLGRTNL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clgrtnle $R1, $R2 */ + SystemZ_CLGRTAsmNLE /* 993 */, SYSTEMZ_INS_CLGRTNLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clgrtnlh $R1, $R2 */ + SystemZ_CLGRTAsmNLH /* 994 */, SYSTEMZ_INS_CLGRTNLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clgt$M3 $R1, $BD2 */ + SystemZ_CLGT /* 995 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* clgt $R1, $M3, $BD2 */ + SystemZ_CLGTAsm /* 996 */, SYSTEMZ_INS_CLGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* clgte $R1, $BD2 */ + SystemZ_CLGTAsmE /* 997 */, SYSTEMZ_INS_CLGTE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* clgth $R1, $BD2 */ + SystemZ_CLGTAsmH /* 998 */, SYSTEMZ_INS_CLGTH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* clgthe $R1, $BD2 */ + SystemZ_CLGTAsmHE /* 999 */, SYSTEMZ_INS_CLGTHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* clgtl $R1, $BD2 */ + SystemZ_CLGTAsmL /* 1000 */, SYSTEMZ_INS_CLGTL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* clgtle $R1, $BD2 */ + SystemZ_CLGTAsmLE /* 1001 */, SYSTEMZ_INS_CLGTLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* clgtlh $R1, $BD2 */ + SystemZ_CLGTAsmLH /* 1002 */, SYSTEMZ_INS_CLGTLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* clgtne $R1, $BD2 */ + SystemZ_CLGTAsmNE /* 1003 */, SYSTEMZ_INS_CLGTNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* clgtnh $R1, $BD2 */ + SystemZ_CLGTAsmNH /* 1004 */, SYSTEMZ_INS_CLGTNH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* clgtnhe $R1, $BD2 */ + SystemZ_CLGTAsmNHE /* 1005 */, SYSTEMZ_INS_CLGTNHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* clgtnl $R1, $BD2 */ + SystemZ_CLGTAsmNL /* 1006 */, SYSTEMZ_INS_CLGTNL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* clgtnle $R1, $BD2 */ + SystemZ_CLGTAsmNLE /* 1007 */, SYSTEMZ_INS_CLGTNLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* clgtnlh $R1, $BD2 */ + SystemZ_CLGTAsmNLH /* 1008 */, SYSTEMZ_INS_CLGTNLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* clgxbr $R1, $M3, $R2, $M4 */ + SystemZ_CLGXBR /* 1009 */, SYSTEMZ_INS_CLGXBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* clgxtr $R1, $M3, $R2, $M4 */ + SystemZ_CLGXTR /* 1010 */, SYSTEMZ_INS_CLGXTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* clhf $R1, $XBD2 */ + SystemZ_CLHF /* 1011 */, SYSTEMZ_INS_CLHF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* clhhr $R1, $R2 */ + SystemZ_CLHHR /* 1012 */, SYSTEMZ_INS_CLHHR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* clhhsi $BD1, $I2 */ + SystemZ_CLHHSI /* 1013 */, SYSTEMZ_INS_CLHHSI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIL }} + + #endif +}, +{ + /* clhlr $R1, $R2 */ + SystemZ_CLHLR /* 1014 */, SYSTEMZ_INS_CLHLR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* clhrl $R1, $RI2 */ + SystemZ_CLHRL /* 1015 */, SYSTEMZ_INS_CLHRL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* cli $BD1, $I2 */ + SystemZ_CLI /* 1016 */, SYSTEMZ_INS_CLI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSI }} + + #endif +}, +{ + /* clib$M3 $R1, $I2, $BD4 */ + SystemZ_CLIB /* 1017 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* clib $R1, $I2, $M3, $BD4 */ + SystemZ_CLIBAsm /* 1018 */, SYSTEMZ_INS_CLIB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clibe $R1, $I2, $BD4 */ + SystemZ_CLIBAsmE /* 1019 */, SYSTEMZ_INS_CLIBE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clibh $R1, $I2, $BD4 */ + SystemZ_CLIBAsmH /* 1020 */, SYSTEMZ_INS_CLIBH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clibhe $R1, $I2, $BD4 */ + SystemZ_CLIBAsmHE /* 1021 */, SYSTEMZ_INS_CLIBHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clibl $R1, $I2, $BD4 */ + SystemZ_CLIBAsmL /* 1022 */, SYSTEMZ_INS_CLIBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clible $R1, $I2, $BD4 */ + SystemZ_CLIBAsmLE /* 1023 */, SYSTEMZ_INS_CLIBLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* cliblh $R1, $I2, $BD4 */ + SystemZ_CLIBAsmLH /* 1024 */, SYSTEMZ_INS_CLIBLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clibne $R1, $I2, $BD4 */ + SystemZ_CLIBAsmNE /* 1025 */, SYSTEMZ_INS_CLIBNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clibnh $R1, $I2, $BD4 */ + SystemZ_CLIBAsmNH /* 1026 */, SYSTEMZ_INS_CLIBNH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clibnhe $R1, $I2, $BD4 */ + SystemZ_CLIBAsmNHE /* 1027 */, SYSTEMZ_INS_CLIBNHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clibnl $R1, $I2, $BD4 */ + SystemZ_CLIBAsmNL /* 1028 */, SYSTEMZ_INS_CLIBNL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clibnle $R1, $I2, $BD4 */ + SystemZ_CLIBAsmNLE /* 1029 */, SYSTEMZ_INS_CLIBNLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clibnlh $R1, $I2, $BD4 */ + SystemZ_CLIBAsmNLH /* 1030 */, SYSTEMZ_INS_CLIBNLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIS }} + + #endif +}, +{ + /* clih $R1, $I2 */ + SystemZ_CLIH /* 1031 */, SYSTEMZ_INS_CLIH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* clij$M3 $R1, $I2, $RI4 */ + SystemZ_CLIJ /* 1032 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* clij $R1, $I2, $M3, $RI4 */ + SystemZ_CLIJAsm /* 1033 */, SYSTEMZ_INS_CLIJ, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clije $R1, $I2, $RI4 */ + SystemZ_CLIJAsmE /* 1034 */, SYSTEMZ_INS_CLIJE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clijh $R1, $I2, $RI4 */ + SystemZ_CLIJAsmH /* 1035 */, SYSTEMZ_INS_CLIJH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clijhe $R1, $I2, $RI4 */ + SystemZ_CLIJAsmHE /* 1036 */, SYSTEMZ_INS_CLIJHE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clijl $R1, $I2, $RI4 */ + SystemZ_CLIJAsmL /* 1037 */, SYSTEMZ_INS_CLIJL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clijle $R1, $I2, $RI4 */ + SystemZ_CLIJAsmLE /* 1038 */, SYSTEMZ_INS_CLIJLE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clijlh $R1, $I2, $RI4 */ + SystemZ_CLIJAsmLH /* 1039 */, SYSTEMZ_INS_CLIJLH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clijne $R1, $I2, $RI4 */ + SystemZ_CLIJAsmNE /* 1040 */, SYSTEMZ_INS_CLIJNE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clijnh $R1, $I2, $RI4 */ + SystemZ_CLIJAsmNH /* 1041 */, SYSTEMZ_INS_CLIJNH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clijnhe $R1, $I2, $RI4 */ + SystemZ_CLIJAsmNHE /* 1042 */, SYSTEMZ_INS_CLIJNHE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clijnl $R1, $I2, $RI4 */ + SystemZ_CLIJAsmNL /* 1043 */, SYSTEMZ_INS_CLIJNL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clijnle $R1, $I2, $RI4 */ + SystemZ_CLIJAsmNLE /* 1044 */, SYSTEMZ_INS_CLIJNLE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* clijnlh $R1, $I2, $RI4 */ + SystemZ_CLIJAsmNLH /* 1045 */, SYSTEMZ_INS_CLIJNLH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEC }} + + #endif +}, +{ + /* cliy $BD1, $I2 */ + SystemZ_CLIY /* 1046 */, SYSTEMZ_INS_CLIY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIY }} + + #endif +}, +{ + /* clm $R1, $M3, $BD2 */ + SystemZ_CLM /* 1047 */, SYSTEMZ_INS_CLM, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSB }} + + #endif +}, +{ + /* clmh $R1, $M3, $BD2 */ + SystemZ_CLMH /* 1048 */, SYSTEMZ_INS_CLMH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* clmy $R1, $M3, $BD2 */ + SystemZ_CLMY /* 1049 */, SYSTEMZ_INS_CLMY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* clr $R1, $R2 */ + SystemZ_CLR /* 1050 */, SYSTEMZ_INS_CLR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* clrb$M3 $R1, $R2, $BD4 */ + SystemZ_CLRB /* 1051 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* clrb $R1, $R2, $M3, $BD4 */ + SystemZ_CLRBAsm /* 1052 */, SYSTEMZ_INS_CLRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clrbe $R1, $R2, $BD4 */ + SystemZ_CLRBAsmE /* 1053 */, SYSTEMZ_INS_CLRBE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clrbh $R1, $R2, $BD4 */ + SystemZ_CLRBAsmH /* 1054 */, SYSTEMZ_INS_CLRBH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clrbhe $R1, $R2, $BD4 */ + SystemZ_CLRBAsmHE /* 1055 */, SYSTEMZ_INS_CLRBHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clrbl $R1, $R2, $BD4 */ + SystemZ_CLRBAsmL /* 1056 */, SYSTEMZ_INS_CLRBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clrble $R1, $R2, $BD4 */ + SystemZ_CLRBAsmLE /* 1057 */, SYSTEMZ_INS_CLRBLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clrblh $R1, $R2, $BD4 */ + SystemZ_CLRBAsmLH /* 1058 */, SYSTEMZ_INS_CLRBLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clrbne $R1, $R2, $BD4 */ + SystemZ_CLRBAsmNE /* 1059 */, SYSTEMZ_INS_CLRBNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clrbnh $R1, $R2, $BD4 */ + SystemZ_CLRBAsmNH /* 1060 */, SYSTEMZ_INS_CLRBNH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clrbnhe $R1, $R2, $BD4 */ + SystemZ_CLRBAsmNHE /* 1061 */, SYSTEMZ_INS_CLRBNHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clrbnl $R1, $R2, $BD4 */ + SystemZ_CLRBAsmNL /* 1062 */, SYSTEMZ_INS_CLRBNL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clrbnle $R1, $R2, $BD4 */ + SystemZ_CLRBAsmNLE /* 1063 */, SYSTEMZ_INS_CLRBNLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clrbnlh $R1, $R2, $BD4 */ + SystemZ_CLRBAsmNLH /* 1064 */, SYSTEMZ_INS_CLRBNLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* clrj$M3 $R1, $R2, $RI4 */ + SystemZ_CLRJ /* 1065 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* clrj $R1, $R2, $M3, $RI4 */ + SystemZ_CLRJAsm /* 1066 */, SYSTEMZ_INS_CLRJ, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clrje $R1, $R2, $RI4 */ + SystemZ_CLRJAsmE /* 1067 */, SYSTEMZ_INS_CLRJE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clrjh $R1, $R2, $RI4 */ + SystemZ_CLRJAsmH /* 1068 */, SYSTEMZ_INS_CLRJH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clrjhe $R1, $R2, $RI4 */ + SystemZ_CLRJAsmHE /* 1069 */, SYSTEMZ_INS_CLRJHE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clrjl $R1, $R2, $RI4 */ + SystemZ_CLRJAsmL /* 1070 */, SYSTEMZ_INS_CLRJL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clrjle $R1, $R2, $RI4 */ + SystemZ_CLRJAsmLE /* 1071 */, SYSTEMZ_INS_CLRJLE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clrjlh $R1, $R2, $RI4 */ + SystemZ_CLRJAsmLH /* 1072 */, SYSTEMZ_INS_CLRJLH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clrjne $R1, $R2, $RI4 */ + SystemZ_CLRJAsmNE /* 1073 */, SYSTEMZ_INS_CLRJNE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clrjnh $R1, $R2, $RI4 */ + SystemZ_CLRJAsmNH /* 1074 */, SYSTEMZ_INS_CLRJNH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clrjnhe $R1, $R2, $RI4 */ + SystemZ_CLRJAsmNHE /* 1075 */, SYSTEMZ_INS_CLRJNHE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clrjnl $R1, $R2, $RI4 */ + SystemZ_CLRJAsmNL /* 1076 */, SYSTEMZ_INS_CLRJNL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clrjnle $R1, $R2, $RI4 */ + SystemZ_CLRJAsmNLE /* 1077 */, SYSTEMZ_INS_CLRJNLE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clrjnlh $R1, $R2, $RI4 */ + SystemZ_CLRJAsmNLH /* 1078 */, SYSTEMZ_INS_CLRJNLH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* clrl $R1, $RI2 */ + SystemZ_CLRL /* 1079 */, SYSTEMZ_INS_CLRL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* clrt$M3 $R1, $R2 */ + SystemZ_CLRT /* 1080 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* clrt $R1, $R2, $M3 */ + SystemZ_CLRTAsm /* 1081 */, SYSTEMZ_INS_CLRT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clrte $R1, $R2 */ + SystemZ_CLRTAsmE /* 1082 */, SYSTEMZ_INS_CLRTE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clrth $R1, $R2 */ + SystemZ_CLRTAsmH /* 1083 */, SYSTEMZ_INS_CLRTH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clrthe $R1, $R2 */ + SystemZ_CLRTAsmHE /* 1084 */, SYSTEMZ_INS_CLRTHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clrtl $R1, $R2 */ + SystemZ_CLRTAsmL /* 1085 */, SYSTEMZ_INS_CLRTL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clrtle $R1, $R2 */ + SystemZ_CLRTAsmLE /* 1086 */, SYSTEMZ_INS_CLRTLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clrtlh $R1, $R2 */ + SystemZ_CLRTAsmLH /* 1087 */, SYSTEMZ_INS_CLRTLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clrtne $R1, $R2 */ + SystemZ_CLRTAsmNE /* 1088 */, SYSTEMZ_INS_CLRTNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clrtnh $R1, $R2 */ + SystemZ_CLRTAsmNH /* 1089 */, SYSTEMZ_INS_CLRTNH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clrtnhe $R1, $R2 */ + SystemZ_CLRTAsmNHE /* 1090 */, SYSTEMZ_INS_CLRTNHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clrtnl $R1, $R2 */ + SystemZ_CLRTAsmNL /* 1091 */, SYSTEMZ_INS_CLRTNL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clrtnle $R1, $R2 */ + SystemZ_CLRTAsmNLE /* 1092 */, SYSTEMZ_INS_CLRTNLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clrtnlh $R1, $R2 */ + SystemZ_CLRTAsmNLH /* 1093 */, SYSTEMZ_INS_CLRTNLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* clst $R1, $R2 */ + SystemZ_CLST /* 1094 */, SYSTEMZ_INS_CLST, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* clt$M3 $R1, $BD2 */ + SystemZ_CLT /* 1095 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* clt $R1, $M3, $BD2 */ + SystemZ_CLTAsm /* 1096 */, SYSTEMZ_INS_CLT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* clte $R1, $BD2 */ + SystemZ_CLTAsmE /* 1097 */, SYSTEMZ_INS_CLTE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* clth $R1, $BD2 */ + SystemZ_CLTAsmH /* 1098 */, SYSTEMZ_INS_CLTH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* clthe $R1, $BD2 */ + SystemZ_CLTAsmHE /* 1099 */, SYSTEMZ_INS_CLTHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* cltl $R1, $BD2 */ + SystemZ_CLTAsmL /* 1100 */, SYSTEMZ_INS_CLTL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* cltle $R1, $BD2 */ + SystemZ_CLTAsmLE /* 1101 */, SYSTEMZ_INS_CLTLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* cltlh $R1, $BD2 */ + SystemZ_CLTAsmLH /* 1102 */, SYSTEMZ_INS_CLTLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* cltne $R1, $BD2 */ + SystemZ_CLTAsmNE /* 1103 */, SYSTEMZ_INS_CLTNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* cltnh $R1, $BD2 */ + SystemZ_CLTAsmNH /* 1104 */, SYSTEMZ_INS_CLTNH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* cltnhe $R1, $BD2 */ + SystemZ_CLTAsmNHE /* 1105 */, SYSTEMZ_INS_CLTNHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* cltnl $R1, $BD2 */ + SystemZ_CLTAsmNL /* 1106 */, SYSTEMZ_INS_CLTNL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* cltnle $R1, $BD2 */ + SystemZ_CLTAsmNLE /* 1107 */, SYSTEMZ_INS_CLTNLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* cltnlh $R1, $BD2 */ + SystemZ_CLTAsmNLH /* 1108 */, SYSTEMZ_INS_CLTNLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* cly $R1, $XBD2 */ + SystemZ_CLY /* 1109 */, SYSTEMZ_INS_CLY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* cmpsc $R1, $R2 */ + SystemZ_CMPSC /* 1110 */, SYSTEMZ_INS_CMPSC, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, SYSTEMZ_REG_R1D, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cp $BDL1, $BDL2 */ + SystemZ_CP /* 1111 */, SYSTEMZ_INS_CP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSB }} + + #endif +}, +{ + /* cpdt $R1, $BDL2, $M3 */ + SystemZ_CPDT /* 1112 */, SYSTEMZ_INS_CPDT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREDFPPACKEDCONVERSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSLB }} + + #endif +}, +{ + /* cpsdr $R1, $R3, $R2 */ + SystemZ_CPSDRdd /* 1113 */, SYSTEMZ_INS_CPSDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFB }} + + #endif +}, +{ + /* cpsdr $R1, $R3, $R2 */ + SystemZ_CPSDRds /* 1114 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cpsdr $R1, $R3, $R2 */ + SystemZ_CPSDRsd /* 1115 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cpsdr $R1, $R3, $R2 */ + SystemZ_CPSDRss /* 1116 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* cpxt $R1, $BDL2, $M3 */ + SystemZ_CPXT /* 1117 */, SYSTEMZ_INS_CPXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREDFPPACKEDCONVERSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSLB }} + + #endif +}, +{ + /* cpya $R1, $R2 */ + SystemZ_CPYA /* 1118 */, SYSTEMZ_INS_CPYA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cr $R1, $R2 */ + SystemZ_CR /* 1119 */, SYSTEMZ_INS_CR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* crb$M3 $R1, $R2, $BD4 */ + SystemZ_CRB /* 1120 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* crb $R1, $R2, $M3, $BD4 */ + SystemZ_CRBAsm /* 1121 */, SYSTEMZ_INS_CRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* crbe $R1, $R2, $BD4 */ + SystemZ_CRBAsmE /* 1122 */, SYSTEMZ_INS_CRBE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* crbh $R1, $R2, $BD4 */ + SystemZ_CRBAsmH /* 1123 */, SYSTEMZ_INS_CRBH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* crbhe $R1, $R2, $BD4 */ + SystemZ_CRBAsmHE /* 1124 */, SYSTEMZ_INS_CRBHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* crbl $R1, $R2, $BD4 */ + SystemZ_CRBAsmL /* 1125 */, SYSTEMZ_INS_CRBL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* crble $R1, $R2, $BD4 */ + SystemZ_CRBAsmLE /* 1126 */, SYSTEMZ_INS_CRBLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* crblh $R1, $R2, $BD4 */ + SystemZ_CRBAsmLH /* 1127 */, SYSTEMZ_INS_CRBLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* crbne $R1, $R2, $BD4 */ + SystemZ_CRBAsmNE /* 1128 */, SYSTEMZ_INS_CRBNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* crbnh $R1, $R2, $BD4 */ + SystemZ_CRBAsmNH /* 1129 */, SYSTEMZ_INS_CRBNH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* crbnhe $R1, $R2, $BD4 */ + SystemZ_CRBAsmNHE /* 1130 */, SYSTEMZ_INS_CRBNHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* crbnl $R1, $R2, $BD4 */ + SystemZ_CRBAsmNL /* 1131 */, SYSTEMZ_INS_CRBNL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* crbnle $R1, $R2, $BD4 */ + SystemZ_CRBAsmNLE /* 1132 */, SYSTEMZ_INS_CRBNLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* crbnlh $R1, $R2, $BD4 */ + SystemZ_CRBAsmNLH /* 1133 */, SYSTEMZ_INS_CRBNLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, 0 }, 1, 1, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRS }} + + #endif +}, +{ + /* crdte $R1, $R3, $R2, $M4 */ + SystemZ_CRDTE /* 1134 */, SYSTEMZ_INS_CRDTE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREENHANCEDDAT2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFB }} + + #endif +}, +{ + /* crdte $R1, $R3, $R2 */ + SystemZ_CRDTEOpt /* 1135 */, SYSTEMZ_INS_CRDTE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREENHANCEDDAT2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFB }} + + #endif +}, +{ + /* crj$M3 $R1, $R2, $RI4 */ + SystemZ_CRJ /* 1136 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* crj $R1, $R2, $M3, $RI4 */ + SystemZ_CRJAsm /* 1137 */, SYSTEMZ_INS_CRJ, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* crje $R1, $R2, $RI4 */ + SystemZ_CRJAsmE /* 1138 */, SYSTEMZ_INS_CRJE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* crjh $R1, $R2, $RI4 */ + SystemZ_CRJAsmH /* 1139 */, SYSTEMZ_INS_CRJH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* crjhe $R1, $R2, $RI4 */ + SystemZ_CRJAsmHE /* 1140 */, SYSTEMZ_INS_CRJHE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* crjl $R1, $R2, $RI4 */ + SystemZ_CRJAsmL /* 1141 */, SYSTEMZ_INS_CRJL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* crjle $R1, $R2, $RI4 */ + SystemZ_CRJAsmLE /* 1142 */, SYSTEMZ_INS_CRJLE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* crjlh $R1, $R2, $RI4 */ + SystemZ_CRJAsmLH /* 1143 */, SYSTEMZ_INS_CRJLH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* crjne $R1, $R2, $RI4 */ + SystemZ_CRJAsmNE /* 1144 */, SYSTEMZ_INS_CRJNE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* crjnh $R1, $R2, $RI4 */ + SystemZ_CRJAsmNH /* 1145 */, SYSTEMZ_INS_CRJNH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* crjnhe $R1, $R2, $RI4 */ + SystemZ_CRJAsmNHE /* 1146 */, SYSTEMZ_INS_CRJNHE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* crjnl $R1, $R2, $RI4 */ + SystemZ_CRJAsmNL /* 1147 */, SYSTEMZ_INS_CRJNL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* crjnle $R1, $R2, $RI4 */ + SystemZ_CRJAsmNLE /* 1148 */, SYSTEMZ_INS_CRJNLE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* crjnlh $R1, $R2, $RI4 */ + SystemZ_CRJAsmNLH /* 1149 */, SYSTEMZ_INS_CRJNLH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEB }} + + #endif +}, +{ + /* crl $R1, $RI2 */ + SystemZ_CRL /* 1150 */, SYSTEMZ_INS_CRL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* crt$M3 $R1, $R2 */ + SystemZ_CRT /* 1151 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* crt $R1, $R2, $M3 */ + SystemZ_CRTAsm /* 1152 */, SYSTEMZ_INS_CRT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* crte $R1, $R2 */ + SystemZ_CRTAsmE /* 1153 */, SYSTEMZ_INS_CRTE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* crth $R1, $R2 */ + SystemZ_CRTAsmH /* 1154 */, SYSTEMZ_INS_CRTH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* crthe $R1, $R2 */ + SystemZ_CRTAsmHE /* 1155 */, SYSTEMZ_INS_CRTHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* crtl $R1, $R2 */ + SystemZ_CRTAsmL /* 1156 */, SYSTEMZ_INS_CRTL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* crtle $R1, $R2 */ + SystemZ_CRTAsmLE /* 1157 */, SYSTEMZ_INS_CRTLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* crtlh $R1, $R2 */ + SystemZ_CRTAsmLH /* 1158 */, SYSTEMZ_INS_CRTLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* crtne $R1, $R2 */ + SystemZ_CRTAsmNE /* 1159 */, SYSTEMZ_INS_CRTNE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* crtnh $R1, $R2 */ + SystemZ_CRTAsmNH /* 1160 */, SYSTEMZ_INS_CRTNH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* crtnhe $R1, $R2 */ + SystemZ_CRTAsmNHE /* 1161 */, SYSTEMZ_INS_CRTNHE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* crtnl $R1, $R2 */ + SystemZ_CRTAsmNL /* 1162 */, SYSTEMZ_INS_CRTNL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* crtnle $R1, $R2 */ + SystemZ_CRTAsmNLE /* 1163 */, SYSTEMZ_INS_CRTNLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* crtnlh $R1, $R2 */ + SystemZ_CRTAsmNLH /* 1164 */, SYSTEMZ_INS_CRTNLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cs $R1, $R3, $BD2 */ + SystemZ_CS /* 1165 */, SYSTEMZ_INS_CS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* csch */ + SystemZ_CSCH /* 1166 */, SYSTEMZ_INS_CSCH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R1L, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* csdtr $R1, $R2, $M4 */ + SystemZ_CSDTR /* 1167 */, SYSTEMZ_INS_CSDTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFD }} + + #endif +}, +{ + /* csg $R1, $R3, $BD2 */ + SystemZ_CSG /* 1168 */, SYSTEMZ_INS_CSG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* csp $R1, $R2 */ + SystemZ_CSP /* 1169 */, SYSTEMZ_INS_CSP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cspg $R1, $R2 */ + SystemZ_CSPG /* 1170 */, SYSTEMZ_INS_CSPG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* csst $BD1, $BD2, $R3 */ + SystemZ_CSST /* 1171 */, SYSTEMZ_INS_CSST, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSF }} + + #endif +}, +{ + /* csxtr $R1, $R2, $M4 */ + SystemZ_CSXTR /* 1172 */, SYSTEMZ_INS_CSXTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFD }} + + #endif +}, +{ + /* csy $R1, $R3, $BD2 */ + SystemZ_CSY /* 1173 */, SYSTEMZ_INS_CSY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* cu12 $R1, $R2, $M3 */ + SystemZ_CU12 /* 1174 */, SYSTEMZ_INS_CU12, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cu12 $R1, $R2 */ + SystemZ_CU12Opt /* 1175 */, SYSTEMZ_INS_CU12, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cu14 $R1, $R2, $M3 */ + SystemZ_CU14 /* 1176 */, SYSTEMZ_INS_CU14, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cu14 $R1, $R2 */ + SystemZ_CU14Opt /* 1177 */, SYSTEMZ_INS_CU14, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cu21 $R1, $R2, $M3 */ + SystemZ_CU21 /* 1178 */, SYSTEMZ_INS_CU21, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cu21 $R1, $R2 */ + SystemZ_CU21Opt /* 1179 */, SYSTEMZ_INS_CU21, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cu24 $R1, $R2, $M3 */ + SystemZ_CU24 /* 1180 */, SYSTEMZ_INS_CU24, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cu24 $R1, $R2 */ + SystemZ_CU24Opt /* 1181 */, SYSTEMZ_INS_CU24, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cu41 $R1, $R2 */ + SystemZ_CU41 /* 1182 */, SYSTEMZ_INS_CU41, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cu42 $R1, $R2 */ + SystemZ_CU42 /* 1183 */, SYSTEMZ_INS_CU42, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cudtr $R1, $R2 */ + SystemZ_CUDTR /* 1184 */, SYSTEMZ_INS_CUDTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cuse $R1, $R2 */ + SystemZ_CUSE /* 1185 */, SYSTEMZ_INS_CUSE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1L, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cutfu $R1, $R2, $M3 */ + SystemZ_CUTFU /* 1186 */, SYSTEMZ_INS_CUTFU, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cutfu $R1, $R2 */ + SystemZ_CUTFUOpt /* 1187 */, SYSTEMZ_INS_CUTFU, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cuutf $R1, $R2, $M3 */ + SystemZ_CUUTF /* 1188 */, SYSTEMZ_INS_CUUTF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cuutf $R1, $R2 */ + SystemZ_CUUTFOpt /* 1189 */, SYSTEMZ_INS_CUUTF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* cuxtr $R1, $R2 */ + SystemZ_CUXTR /* 1190 */, SYSTEMZ_INS_CUXTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cvb $R1, $XBD2 */ + SystemZ_CVB /* 1191 */, SYSTEMZ_INS_CVB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* cvbg $R1, $XBD2 */ + SystemZ_CVBG /* 1192 */, SYSTEMZ_INS_CVBG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* cvby $R1, $XBD2 */ + SystemZ_CVBY /* 1193 */, SYSTEMZ_INS_CVBY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* cvd $R1, $XBD2 */ + SystemZ_CVD /* 1194 */, SYSTEMZ_INS_CVD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* cvdg $R1, $XBD2 */ + SystemZ_CVDG /* 1195 */, SYSTEMZ_INS_CVDG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* cvdy $R1, $XBD2 */ + SystemZ_CVDY /* 1196 */, SYSTEMZ_INS_CVDY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* cxbr $R1, $R2 */ + SystemZ_CXBR /* 1197 */, SYSTEMZ_INS_CXBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cxfbr $R1, $R2 */ + SystemZ_CXFBR /* 1198 */, SYSTEMZ_INS_CXFBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cxfbra $R1, $M3, $R2, $M4 */ + SystemZ_CXFBRA /* 1199 */, SYSTEMZ_INS_CXFBRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cxfr $R1, $R2 */ + SystemZ_CXFR /* 1200 */, SYSTEMZ_INS_CXFR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cxftr $R1, $M3, $R2, $M4 */ + SystemZ_CXFTR /* 1201 */, SYSTEMZ_INS_CXFTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cxgbr $R1, $R2 */ + SystemZ_CXGBR /* 1202 */, SYSTEMZ_INS_CXGBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cxgbra $R1, $M3, $R2, $M4 */ + SystemZ_CXGBRA /* 1203 */, SYSTEMZ_INS_CXGBRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cxgr $R1, $R2 */ + SystemZ_CXGR /* 1204 */, SYSTEMZ_INS_CXGR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cxgtr $R1, $R2 */ + SystemZ_CXGTR /* 1205 */, SYSTEMZ_INS_CXGTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cxgtra $R1, $M3, $R2, $M4 */ + SystemZ_CXGTRA /* 1206 */, SYSTEMZ_INS_CXGTRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cxlfbr $R1, $M3, $R2, $M4 */ + SystemZ_CXLFBR /* 1207 */, SYSTEMZ_INS_CXLFBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cxlftr $R1, $M3, $R2, $M4 */ + SystemZ_CXLFTR /* 1208 */, SYSTEMZ_INS_CXLFTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cxlgbr $R1, $M3, $R2, $M4 */ + SystemZ_CXLGBR /* 1209 */, SYSTEMZ_INS_CXLGBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cxlgtr $R1, $M3, $R2, $M4 */ + SystemZ_CXLGTR /* 1210 */, SYSTEMZ_INS_CXLGTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* cxpt $R1, $BDL2, $M3 */ + SystemZ_CXPT /* 1211 */, SYSTEMZ_INS_CXPT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREDFPPACKEDCONVERSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSLB }} + + #endif +}, +{ + /* cxr $R1, $R2 */ + SystemZ_CXR /* 1212 */, SYSTEMZ_INS_CXR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cxstr $R1, $R2 */ + SystemZ_CXSTR /* 1213 */, SYSTEMZ_INS_CXSTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cxtr $R1, $R2 */ + SystemZ_CXTR /* 1214 */, SYSTEMZ_INS_CXTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cxutr $R1, $R2 */ + SystemZ_CXUTR /* 1215 */, SYSTEMZ_INS_CXUTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* cxzt $R1, $BDL2, $M3 */ + SystemZ_CXZT /* 1216 */, SYSTEMZ_INS_CXZT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREDFPZONEDCONVERSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSLB }} + + #endif +}, +{ + /* cy $R1, $XBD2 */ + SystemZ_CY /* 1217 */, SYSTEMZ_INS_CY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* czdt $R1, $BDL2, $M3 */ + SystemZ_CZDT /* 1218 */, SYSTEMZ_INS_CZDT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREDFPZONEDCONVERSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSLB }} + + #endif +}, +{ + /* czxt $R1, $BDL2, $M3 */ + SystemZ_CZXT /* 1219 */, SYSTEMZ_INS_CZXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREDFPZONEDCONVERSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSLB }} + + #endif +}, +{ + /* d $R1, $XBD2 */ + SystemZ_D /* 1220 */, SYSTEMZ_INS_D, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* dd $R1, $XBD2 */ + SystemZ_DD /* 1221 */, SYSTEMZ_INS_DD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* ddb $R1, $XBD2 */ + SystemZ_DDB /* 1222 */, SYSTEMZ_INS_DDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* ddbr $R1, $R2 */ + SystemZ_DDBR /* 1223 */, SYSTEMZ_INS_DDBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ddr $R1, $R2 */ + SystemZ_DDR /* 1224 */, SYSTEMZ_INS_DDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* ddtr $R1, $R2, $R3 */ + SystemZ_DDTR /* 1225 */, SYSTEMZ_INS_DDTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* ddtra $R1, $R2, $R3, $M4 */ + SystemZ_DDTRA /* 1226 */, SYSTEMZ_INS_DDTRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* de $R1, $XBD2 */ + SystemZ_DE /* 1227 */, SYSTEMZ_INS_DE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* deb $R1, $XBD2 */ + SystemZ_DEB /* 1228 */, SYSTEMZ_INS_DEB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* debr $R1, $R2 */ + SystemZ_DEBR /* 1229 */, SYSTEMZ_INS_DEBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* der $R1, $R2 */ + SystemZ_DER /* 1230 */, SYSTEMZ_INS_DER, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* dfltcc $R1, $R2, $R3 */ + SystemZ_DFLTCC /* 1231 */, SYSTEMZ_INS_DFLTCC, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDEFLATECONVERSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* diag $R1, $R3, $BD2 */ + SystemZ_DIAG /* 1232 */, SYSTEMZ_INS_DIAG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_CALL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* didbr $R1, $R3, $R2, $M4 */ + SystemZ_DIDBR /* 1233 */, SYSTEMZ_INS_DIDBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFB }} + + #endif +}, +{ + /* diebr $R1, $R3, $R2, $M4 */ + SystemZ_DIEBR /* 1234 */, SYSTEMZ_INS_DIEBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFB }} + + #endif +}, +{ + /* dl $R1, $XBD2 */ + SystemZ_DL /* 1235 */, SYSTEMZ_INS_DL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* dlg $R1, $XBD2 */ + SystemZ_DLG /* 1236 */, SYSTEMZ_INS_DLG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* dlgr $R1, $R2 */ + SystemZ_DLGR /* 1237 */, SYSTEMZ_INS_DLGR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* dlr $R1, $R2 */ + SystemZ_DLR /* 1238 */, SYSTEMZ_INS_DLR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* dp $BDL1, $BDL2 */ + SystemZ_DP /* 1239 */, SYSTEMZ_INS_DP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSB }} + + #endif +}, +{ + /* dr $R1, $R2 */ + SystemZ_DR /* 1240 */, SYSTEMZ_INS_DR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* dsg $R1, $XBD2 */ + SystemZ_DSG /* 1241 */, SYSTEMZ_INS_DSG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* dsgf $R1, $XBD2 */ + SystemZ_DSGF /* 1242 */, SYSTEMZ_INS_DSGF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* dsgfr $R1, $R2 */ + SystemZ_DSGFR /* 1243 */, SYSTEMZ_INS_DSGFR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* dsgr $R1, $R2 */ + SystemZ_DSGR /* 1244 */, SYSTEMZ_INS_DSGR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* dxbr $R1, $R2 */ + SystemZ_DXBR /* 1245 */, SYSTEMZ_INS_DXBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* dxr $R1, $R2 */ + SystemZ_DXR /* 1246 */, SYSTEMZ_INS_DXR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* dxtr $R1, $R2, $R3 */ + SystemZ_DXTR /* 1247 */, SYSTEMZ_INS_DXTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* dxtra $R1, $R2, $R3, $M4 */ + SystemZ_DXTRA /* 1248 */, SYSTEMZ_INS_DXTRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* ear $R1, $R2 */ + SystemZ_EAR /* 1249 */, SYSTEMZ_INS_EAR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ecag $R1, $R3, $BD2 */ + SystemZ_ECAG /* 1250 */, SYSTEMZ_INS_ECAG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* ecctr $R1, $R2 */ + SystemZ_ECCTR /* 1251 */, SYSTEMZ_INS_ECCTR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ecpga $R1, $R2 */ + SystemZ_ECPGA /* 1252 */, SYSTEMZ_INS_ECPGA, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ectg $BD1, $BD2, $R3 */ + SystemZ_ECTG /* 1253 */, SYSTEMZ_INS_ECTG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_R0D, SYSTEMZ_REG_R1D, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSF }} + + #endif +}, +{ + /* ed $BDL1, $BD2 */ + SystemZ_ED /* 1254 */, SYSTEMZ_INS_ED, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSA }} + + #endif +}, +{ + /* edmk $BDL1, $BD2 */ + SystemZ_EDMK /* 1255 */, SYSTEMZ_INS_EDMK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSA }} + + #endif +}, +{ + /* eedtr $R1, $R2 */ + SystemZ_EEDTR /* 1256 */, SYSTEMZ_INS_EEDTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* eextr $R1, $R2 */ + SystemZ_EEXTR /* 1257 */, SYSTEMZ_INS_EEXTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* efpc $R1 */ + SystemZ_EFPC /* 1258 */, SYSTEMZ_INS_EFPC, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* epair $R1 */ + SystemZ_EPAIR /* 1259 */, SYSTEMZ_INS_EPAIR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* epar $R1 */ + SystemZ_EPAR /* 1260 */, SYSTEMZ_INS_EPAR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* epctr $R1, $R2 */ + SystemZ_EPCTR /* 1261 */, SYSTEMZ_INS_EPCTR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* epsw $R1, $R2 */ + SystemZ_EPSW /* 1262 */, SYSTEMZ_INS_EPSW, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ereg $R1, $R2 */ + SystemZ_EREG /* 1263 */, SYSTEMZ_INS_EREG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* eregg $R1, $R2 */ + SystemZ_EREGG /* 1264 */, SYSTEMZ_INS_EREGG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* esair $R1 */ + SystemZ_ESAIR /* 1265 */, SYSTEMZ_INS_ESAIR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* esar $R1 */ + SystemZ_ESAR /* 1266 */, SYSTEMZ_INS_ESAR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* esdtr $R1, $R2 */ + SystemZ_ESDTR /* 1267 */, SYSTEMZ_INS_ESDTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* esea $R1 */ + SystemZ_ESEA /* 1268 */, SYSTEMZ_INS_ESEA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* esta $R1, $R2 */ + SystemZ_ESTA /* 1269 */, SYSTEMZ_INS_ESTA, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* esxtr $R1, $R2 */ + SystemZ_ESXTR /* 1270 */, SYSTEMZ_INS_ESXTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* etnd $R1 */ + SystemZ_ETND /* 1271 */, SYSTEMZ_INS_ETND, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURETRANSACTIONALEXECUTION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ex $R1, $XBD2 */ + SystemZ_EX /* 1272 */, SYSTEMZ_INS_EX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* exrl $R1, $RI2 */ + SystemZ_EXRL /* 1273 */, SYSTEMZ_INS_EXRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* fidbr $R1, $M3, $R2 */ + SystemZ_FIDBR /* 1274 */, SYSTEMZ_INS_FIDBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* fidbra $R1, $M3, $R2, $M4 */ + SystemZ_FIDBRA /* 1275 */, SYSTEMZ_INS_FIDBRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* fidr $R1, $R2 */ + SystemZ_FIDR /* 1276 */, SYSTEMZ_INS_FIDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* fidtr $R1, $M3, $R2, $M4 */ + SystemZ_FIDTR /* 1277 */, SYSTEMZ_INS_FIDTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* fiebr $R1, $M3, $R2 */ + SystemZ_FIEBR /* 1278 */, SYSTEMZ_INS_FIEBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* fiebra $R1, $M3, $R2, $M4 */ + SystemZ_FIEBRA /* 1279 */, SYSTEMZ_INS_FIEBRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* fier $R1, $R2 */ + SystemZ_FIER /* 1280 */, SYSTEMZ_INS_FIER, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* fixbr $R1, $M3, $R2 */ + SystemZ_FIXBR /* 1281 */, SYSTEMZ_INS_FIXBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* fixbra $R1, $M3, $R2, $M4 */ + SystemZ_FIXBRA /* 1282 */, SYSTEMZ_INS_FIXBRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* fixr $R1, $R2 */ + SystemZ_FIXR /* 1283 */, SYSTEMZ_INS_FIXR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* fixtr $R1, $M3, $R2, $M4 */ + SystemZ_FIXTR /* 1284 */, SYSTEMZ_INS_FIXTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* flogr $R1, $R2 */ + SystemZ_FLOGR /* 1285 */, SYSTEMZ_INS_FLOGR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* hdr $R1, $R2 */ + SystemZ_HDR /* 1286 */, SYSTEMZ_INS_HDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* her $R1, $R2 */ + SystemZ_HER /* 1287 */, SYSTEMZ_INS_HER, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* hsch */ + SystemZ_HSCH /* 1288 */, SYSTEMZ_INS_HSCH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R1L, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* iac $R1 */ + SystemZ_IAC /* 1289 */, SYSTEMZ_INS_IAC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ic $R1, $XBD2 */ + SystemZ_IC /* 1290 */, SYSTEMZ_INS_IC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* ic $R1, $XBD2 */ + SystemZ_IC32 /* 1291 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* icy $R1, $XBD2 */ + SystemZ_IC32Y /* 1292 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* icm $R1, $M3, $BD2 */ + SystemZ_ICM /* 1293 */, SYSTEMZ_INS_ICM, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSB }} + + #endif +}, +{ + /* icmh $R1, $M3, $BD2 */ + SystemZ_ICMH /* 1294 */, SYSTEMZ_INS_ICMH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* icmy $R1, $M3, $BD2 */ + SystemZ_ICMY /* 1295 */, SYSTEMZ_INS_ICMY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* icy $R1, $XBD2 */ + SystemZ_ICY /* 1296 */, SYSTEMZ_INS_ICY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* idte $R1, $R3, $R2, $M4 */ + SystemZ_IDTE /* 1297 */, SYSTEMZ_INS_IDTE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFB }} + + #endif +}, +{ + /* idte $R1, $R3, $R2 */ + SystemZ_IDTEOpt /* 1298 */, SYSTEMZ_INS_IDTE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFB }} + + #endif +}, +{ + /* iedtr $R1, $R3, $R2 */ + SystemZ_IEDTR /* 1299 */, SYSTEMZ_INS_IEDTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFB }} + + #endif +}, +{ + /* iextr $R1, $R3, $R2 */ + SystemZ_IEXTR /* 1300 */, SYSTEMZ_INS_IEXTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFB }} + + #endif +}, +{ + /* iihf $R1, $I2 */ + SystemZ_IIHF /* 1301 */, SYSTEMZ_INS_IIHF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* iihh $R1, $I2 */ + SystemZ_IIHH /* 1302 */, SYSTEMZ_INS_IIHH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* iihl $R1, $I2 */ + SystemZ_IIHL /* 1303 */, SYSTEMZ_INS_IIHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* iilf $R1, $I2 */ + SystemZ_IILF /* 1304 */, SYSTEMZ_INS_IILF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* iilh $R1, $I2 */ + SystemZ_IILH /* 1305 */, SYSTEMZ_INS_IILH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* iill $R1, $I2 */ + SystemZ_IILL /* 1306 */, SYSTEMZ_INS_IILL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* ipk */ + SystemZ_IPK /* 1307 */, SYSTEMZ_INS_IPK, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R2L, 0 }, { SYSTEMZ_REG_R2L, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* ipm $R1 */ + SystemZ_IPM /* 1308 */, SYSTEMZ_INS_IPM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ipte $R1, $R2, $R3, $M4 */ + SystemZ_IPTE /* 1309 */, SYSTEMZ_INS_IPTE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* ipte $R1, $R2, $R3 */ + SystemZ_IPTEOpt /* 1310 */, SYSTEMZ_INS_IPTE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* ipte $R1, $R2 */ + SystemZ_IPTEOptOpt /* 1311 */, SYSTEMZ_INS_IPTE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* irbm $R1, $R2 */ + SystemZ_IRBM /* 1312 */, SYSTEMZ_INS_IRBM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREINSERTREFERENCEBITSMULTIPLE, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* iske $R1, $R2 */ + SystemZ_ISKE /* 1313 */, SYSTEMZ_INS_ISKE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ivsk $R1, $R2 */ + SystemZ_IVSK /* 1314 */, SYSTEMZ_INS_IVSK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* .insn e,$enc */ + SystemZ_InsnE /* 1315 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn ri,$enc,$R1,$I2 */ + SystemZ_InsnRI /* 1316 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn rie,$enc,$R1,$R3,$I2 */ + SystemZ_InsnRIE /* 1317 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn ril,$enc,$R1,$I2 */ + SystemZ_InsnRIL /* 1318 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn rilu,$enc,$R1,$I2 */ + SystemZ_InsnRILU /* 1319 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn ris,$enc,$R1,$I2,$M3,$BD4 */ + SystemZ_InsnRIS /* 1320 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn rr,$enc,$R1,$R2 */ + SystemZ_InsnRR /* 1321 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn rre,$enc,$R1,$R2 */ + SystemZ_InsnRRE /* 1322 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn rrf,$enc,$R1,$R2,$R3,$M4 */ + SystemZ_InsnRRF /* 1323 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn rrs,$enc,$R1,$R2,$M3,$BD4 */ + SystemZ_InsnRRS /* 1324 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn rs,$enc,$R1,$R3,$BD2 */ + SystemZ_InsnRS /* 1325 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn rse,$enc,$R1,$R3,$BD2 */ + SystemZ_InsnRSE /* 1326 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn rsi,$enc,$R1,$R3,$RI2 */ + SystemZ_InsnRSI /* 1327 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn rsy,$enc,$R1,$R3,$BD2 */ + SystemZ_InsnRSY /* 1328 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn rx,$enc,$R1,$XBD2 */ + SystemZ_InsnRX /* 1329 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn rxe,$enc,$R1,$XBD2 */ + SystemZ_InsnRXE /* 1330 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn rxf,$enc,$R1,$R3,$XBD2 */ + SystemZ_InsnRXF /* 1331 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn rxy,$enc,$R1,$XBD2 */ + SystemZ_InsnRXY /* 1332 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn s,$enc,$BD2 */ + SystemZ_InsnS /* 1333 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn si,$enc,$BD1,$I2 */ + SystemZ_InsnSI /* 1334 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn sil,$enc,$BD1,$I2 */ + SystemZ_InsnSIL /* 1335 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn siy,$enc,$BD1,$I2 */ + SystemZ_InsnSIY /* 1336 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn ss,$enc,$RBD1,$BD2,$R3 */ + SystemZ_InsnSS /* 1337 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn sse,$enc,$BD1,$BD2 */ + SystemZ_InsnSSE /* 1338 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn ssf,$enc,$BD1,$BD2,$R3 */ + SystemZ_InsnSSF /* 1339 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn vri,$enc,$V1,$V2,$I3,$M4,$M5 */ + SystemZ_InsnVRI /* 1340 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6 */ + SystemZ_InsnVRR /* 1341 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn vrs,$enc,$BD2,$M4 */ + SystemZ_InsnVRS /* 1342 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn vrv,$enc,$V1,$VBD2,$M3 */ + SystemZ_InsnVRV /* 1343 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn vrx,$enc,$V1,$XBD2,$M3 */ + SystemZ_InsnVRX /* 1344 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* .insn vsi,$enc,$V1,$BD2,$I3 */ + SystemZ_InsnVSI /* 1345 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* j $RI2 */ + SystemZ_J /* 1346 */, SYSTEMZ_INS_J, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* je $RI2 */ + SystemZ_JAsmE /* 1347 */, SYSTEMZ_INS_JE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jh $RI2 */ + SystemZ_JAsmH /* 1348 */, SYSTEMZ_INS_JH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jhe $RI2 */ + SystemZ_JAsmHE /* 1349 */, SYSTEMZ_INS_JHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jl $RI2 */ + SystemZ_JAsmL /* 1350 */, SYSTEMZ_INS_JL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jle $RI2 */ + SystemZ_JAsmLE /* 1351 */, SYSTEMZ_INS_JLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jlh $RI2 */ + SystemZ_JAsmLH /* 1352 */, SYSTEMZ_INS_JLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jm $RI2 */ + SystemZ_JAsmM /* 1353 */, SYSTEMZ_INS_JM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jne $RI2 */ + SystemZ_JAsmNE /* 1354 */, SYSTEMZ_INS_JNE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jnh $RI2 */ + SystemZ_JAsmNH /* 1355 */, SYSTEMZ_INS_JNH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jnhe $RI2 */ + SystemZ_JAsmNHE /* 1356 */, SYSTEMZ_INS_JNHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jnl $RI2 */ + SystemZ_JAsmNL /* 1357 */, SYSTEMZ_INS_JNL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jnle $RI2 */ + SystemZ_JAsmNLE /* 1358 */, SYSTEMZ_INS_JNLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jnlh $RI2 */ + SystemZ_JAsmNLH /* 1359 */, SYSTEMZ_INS_JNLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jnm $RI2 */ + SystemZ_JAsmNM /* 1360 */, SYSTEMZ_INS_JNM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jno $RI2 */ + SystemZ_JAsmNO /* 1361 */, SYSTEMZ_INS_JNO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jnp $RI2 */ + SystemZ_JAsmNP /* 1362 */, SYSTEMZ_INS_JNP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jnz $RI2 */ + SystemZ_JAsmNZ /* 1363 */, SYSTEMZ_INS_JNZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jo $RI2 */ + SystemZ_JAsmO /* 1364 */, SYSTEMZ_INS_JO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jp $RI2 */ + SystemZ_JAsmP /* 1365 */, SYSTEMZ_INS_JP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* jz $RI2 */ + SystemZ_JAsmZ /* 1366 */, SYSTEMZ_INS_JZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIC }} + + #endif +}, +{ + /* j{g|lu} $RI2 */ + SystemZ_JG /* 1367 */, SYSTEMZ_INS_J_G_LU_, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}e $RI2 */ + SystemZ_JGAsmE /* 1368 */, SYSTEMZ_INS_J_G_L_E, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}h $RI2 */ + SystemZ_JGAsmH /* 1369 */, SYSTEMZ_INS_J_G_L_H, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}he $RI2 */ + SystemZ_JGAsmHE /* 1370 */, SYSTEMZ_INS_J_G_L_HE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}l $RI2 */ + SystemZ_JGAsmL /* 1371 */, SYSTEMZ_INS_J_G_L_L, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}le $RI2 */ + SystemZ_JGAsmLE /* 1372 */, SYSTEMZ_INS_J_G_L_LE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}lh $RI2 */ + SystemZ_JGAsmLH /* 1373 */, SYSTEMZ_INS_J_G_L_LH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}m $RI2 */ + SystemZ_JGAsmM /* 1374 */, SYSTEMZ_INS_J_G_L_M, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}ne $RI2 */ + SystemZ_JGAsmNE /* 1375 */, SYSTEMZ_INS_J_G_L_NE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}nh $RI2 */ + SystemZ_JGAsmNH /* 1376 */, SYSTEMZ_INS_J_G_L_NH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}nhe $RI2 */ + SystemZ_JGAsmNHE /* 1377 */, SYSTEMZ_INS_J_G_L_NHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}nl $RI2 */ + SystemZ_JGAsmNL /* 1378 */, SYSTEMZ_INS_J_G_L_NL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}nle $RI2 */ + SystemZ_JGAsmNLE /* 1379 */, SYSTEMZ_INS_J_G_L_NLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}nlh $RI2 */ + SystemZ_JGAsmNLH /* 1380 */, SYSTEMZ_INS_J_G_L_NLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}nm $RI2 */ + SystemZ_JGAsmNM /* 1381 */, SYSTEMZ_INS_J_G_L_NM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}no $RI2 */ + SystemZ_JGAsmNO /* 1382 */, SYSTEMZ_INS_J_G_L_NO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}np $RI2 */ + SystemZ_JGAsmNP /* 1383 */, SYSTEMZ_INS_J_G_L_NP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}nz $RI2 */ + SystemZ_JGAsmNZ /* 1384 */, SYSTEMZ_INS_J_G_L_NZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}o $RI2 */ + SystemZ_JGAsmO /* 1385 */, SYSTEMZ_INS_J_G_L_O, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}p $RI2 */ + SystemZ_JGAsmP /* 1386 */, SYSTEMZ_INS_J_G_L_P, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* j{g|l}z $RI2 */ + SystemZ_JGAsmZ /* 1387 */, SYSTEMZ_INS_J_G_L_Z, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_GRP_JUMP, SYSTEMZ_GRP_BRANCH_RELATIVE, 0 }, 1, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* kdb $R1, $XBD2 */ + SystemZ_KDB /* 1388 */, SYSTEMZ_INS_KDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* kdbr $R1, $R2 */ + SystemZ_KDBR /* 1389 */, SYSTEMZ_INS_KDBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* kdsa $R1, $R2 */ + SystemZ_KDSA /* 1390 */, SYSTEMZ_INS_KDSA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST9, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* kdtr $R1, $R2 */ + SystemZ_KDTR /* 1391 */, SYSTEMZ_INS_KDTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* keb $R1, $XBD2 */ + SystemZ_KEB /* 1392 */, SYSTEMZ_INS_KEB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* kebr $R1, $R2 */ + SystemZ_KEBR /* 1393 */, SYSTEMZ_INS_KEBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* kimd $R1, $R2 */ + SystemZ_KIMD /* 1394 */, SYSTEMZ_INS_KIMD, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* klmd $R1, $R2 */ + SystemZ_KLMD /* 1395 */, SYSTEMZ_INS_KLMD, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* km $R1, $R2 */ + SystemZ_KM /* 1396 */, SYSTEMZ_INS_KM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* kma $R1, $R3, $R2 */ + SystemZ_KMA /* 1397 */, SYSTEMZ_INS_KMA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST8, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFB }} + + #endif +}, +{ + /* kmac $R1, $R2 */ + SystemZ_KMAC /* 1398 */, SYSTEMZ_INS_KMAC, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* kmc $R1, $R2 */ + SystemZ_KMC /* 1399 */, SYSTEMZ_INS_KMC, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* kmctr $R1, $R3, $R2 */ + SystemZ_KMCTR /* 1400 */, SYSTEMZ_INS_KMCTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST4, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFB }} + + #endif +}, +{ + /* kmf $R1, $R2 */ + SystemZ_KMF /* 1401 */, SYSTEMZ_INS_KMF, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST4, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* kmo $R1, $R2 */ + SystemZ_KMO /* 1402 */, SYSTEMZ_INS_KMO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST4, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* kxbr $R1, $R2 */ + SystemZ_KXBR /* 1403 */, SYSTEMZ_INS_KXBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* kxtr $R1, $R2 */ + SystemZ_KXTR /* 1404 */, SYSTEMZ_INS_KXTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* l $R1, $XBD2 */ + SystemZ_L /* 1405 */, SYSTEMZ_INS_L, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* la $R1, $XBD2 */ + SystemZ_LA /* 1406 */, SYSTEMZ_INS_LA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* laa $R1, $R3, $BD2 */ + SystemZ_LAA /* 1407 */, SYSTEMZ_INS_LAA, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREINTERLOCKEDACCESS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* laag $R1, $R3, $BD2 */ + SystemZ_LAAG /* 1408 */, SYSTEMZ_INS_LAAG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREINTERLOCKEDACCESS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* laal $R1, $R3, $BD2 */ + SystemZ_LAAL /* 1409 */, SYSTEMZ_INS_LAAL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREINTERLOCKEDACCESS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* laalg $R1, $R3, $BD2 */ + SystemZ_LAALG /* 1410 */, SYSTEMZ_INS_LAALG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREINTERLOCKEDACCESS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* lae $R1, $XBD2 */ + SystemZ_LAE /* 1411 */, SYSTEMZ_INS_LAE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* laey $R1, $XBD2 */ + SystemZ_LAEY /* 1412 */, SYSTEMZ_INS_LAEY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lam $R1, $R3, $BD2 */ + SystemZ_LAM /* 1413 */, SYSTEMZ_INS_LAM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* lamy $R1, $R3, $BD2 */ + SystemZ_LAMY /* 1414 */, SYSTEMZ_INS_LAMY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* lan $R1, $R3, $BD2 */ + SystemZ_LAN /* 1415 */, SYSTEMZ_INS_LAN, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREINTERLOCKEDACCESS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* lang $R1, $R3, $BD2 */ + SystemZ_LANG /* 1416 */, SYSTEMZ_INS_LANG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREINTERLOCKEDACCESS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* lao $R1, $R3, $BD2 */ + SystemZ_LAO /* 1417 */, SYSTEMZ_INS_LAO, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREINTERLOCKEDACCESS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* laog $R1, $R3, $BD2 */ + SystemZ_LAOG /* 1418 */, SYSTEMZ_INS_LAOG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREINTERLOCKEDACCESS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* larl $R1, $RI2 */ + SystemZ_LARL /* 1419 */, SYSTEMZ_INS_LARL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* lasp $BD1, $BD2 */ + SystemZ_LASP /* 1420 */, SYSTEMZ_INS_LASP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSE }} + + #endif +}, +{ + /* lat $R1, $XBD2 */ + SystemZ_LAT /* 1421 */, SYSTEMZ_INS_LAT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADANDTRAP, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lax $R1, $R3, $BD2 */ + SystemZ_LAX /* 1422 */, SYSTEMZ_INS_LAX, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREINTERLOCKEDACCESS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* laxg $R1, $R3, $BD2 */ + SystemZ_LAXG /* 1423 */, SYSTEMZ_INS_LAXG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREINTERLOCKEDACCESS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* lay $R1, $XBD2 */ + SystemZ_LAY /* 1424 */, SYSTEMZ_INS_LAY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lb $R1, $XBD2 */ + SystemZ_LB /* 1425 */, SYSTEMZ_INS_LB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lbear $BD2 */ + SystemZ_LBEAR /* 1426 */, SYSTEMZ_INS_LBEAR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREBEARENHANCEMENT, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* lbh $R1, $XBD2 */ + SystemZ_LBH /* 1427 */, SYSTEMZ_INS_LBH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lbr $R1, $R2 */ + SystemZ_LBR /* 1428 */, SYSTEMZ_INS_LBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lcbb $R1, $XBD2, $M3 */ + SystemZ_LCBB /* 1429 */, SYSTEMZ_INS_LCBB, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* lcctl $BD2 */ + SystemZ_LCCTL /* 1430 */, SYSTEMZ_INS_LCCTL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* lcdbr $R1, $R2 */ + SystemZ_LCDBR /* 1431 */, SYSTEMZ_INS_LCDBR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lcdfr $R1, $R2 */ + SystemZ_LCDFR /* 1432 */, SYSTEMZ_INS_LCDFR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lcdfr $R1, $R2 */ + SystemZ_LCDFR_32 /* 1433 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lcdr $R1, $R2 */ + SystemZ_LCDR /* 1434 */, SYSTEMZ_INS_LCDR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* lcebr $R1, $R2 */ + SystemZ_LCEBR /* 1435 */, SYSTEMZ_INS_LCEBR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lcer $R1, $R2 */ + SystemZ_LCER /* 1436 */, SYSTEMZ_INS_LCER, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* lcgfr $R1, $R2 */ + SystemZ_LCGFR /* 1437 */, SYSTEMZ_INS_LCGFR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lcgr $R1, $R2 */ + SystemZ_LCGR /* 1438 */, SYSTEMZ_INS_LCGR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lcr $R1, $R2 */ + SystemZ_LCR /* 1439 */, SYSTEMZ_INS_LCR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* lctl $R1, $R3, $BD2 */ + SystemZ_LCTL /* 1440 */, SYSTEMZ_INS_LCTL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* lctlg $R1, $R3, $BD2 */ + SystemZ_LCTLG /* 1441 */, SYSTEMZ_INS_LCTLG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* lcxbr $R1, $R2 */ + SystemZ_LCXBR /* 1442 */, SYSTEMZ_INS_LCXBR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lcxr $R1, $R2 */ + SystemZ_LCXR /* 1443 */, SYSTEMZ_INS_LCXR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ld $R1, $XBD2 */ + SystemZ_LD /* 1444 */, SYSTEMZ_INS_LD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* lde $R1, $XBD2 */ + SystemZ_LDE /* 1445 */, SYSTEMZ_INS_LDE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* lde $R1, $XBD2 */ + SystemZ_LDE32 /* 1446 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* ldeb $R1, $XBD2 */ + SystemZ_LDEB /* 1447 */, SYSTEMZ_INS_LDEB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* ldebr $R1, $R2 */ + SystemZ_LDEBR /* 1448 */, SYSTEMZ_INS_LDEBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lder $R1, $R2 */ + SystemZ_LDER /* 1449 */, SYSTEMZ_INS_LDER, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ldetr $R1, $R2, $M4 */ + SystemZ_LDETR /* 1450 */, SYSTEMZ_INS_LDETR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFD }} + + #endif +}, +{ + /* ldgr $R1, $R2 */ + SystemZ_LDGR /* 1451 */, SYSTEMZ_INS_LDGR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ldr $R1, $R2 */ + SystemZ_LDR /* 1452 */, SYSTEMZ_INS_LDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* ldr $R1, $R2 */ + SystemZ_LDR32 /* 1453 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* ldxbr $R1, $R2 */ + SystemZ_LDXBR /* 1454 */, SYSTEMZ_INS_LDXBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ldxbra $R1, $M3, $R2, $M4 */ + SystemZ_LDXBRA /* 1455 */, SYSTEMZ_INS_LDXBRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* ldxr $R1, $R2 */ + SystemZ_LDXR /* 1456 */, SYSTEMZ_INS_LDXR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* ldxtr $R1, $M3, $R2, $M4 */ + SystemZ_LDXTR /* 1457 */, SYSTEMZ_INS_LDXTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* ldy $R1, $XBD2 */ + SystemZ_LDY /* 1458 */, SYSTEMZ_INS_LDY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* le $R1, $XBD2 */ + SystemZ_LE /* 1459 */, SYSTEMZ_INS_LE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* ledbr $R1, $R2 */ + SystemZ_LEDBR /* 1460 */, SYSTEMZ_INS_LEDBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ledbra $R1, $M3, $R2, $M4 */ + SystemZ_LEDBRA /* 1461 */, SYSTEMZ_INS_LEDBRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* ledr $R1, $R2 */ + SystemZ_LEDR /* 1462 */, SYSTEMZ_INS_LEDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* ledtr $R1, $M3, $R2, $M4 */ + SystemZ_LEDTR /* 1463 */, SYSTEMZ_INS_LEDTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* ler $R1, $R2 */ + SystemZ_LER /* 1464 */, SYSTEMZ_INS_LER, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* lexbr $R1, $R2 */ + SystemZ_LEXBR /* 1465 */, SYSTEMZ_INS_LEXBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lexbra $R1, $M3, $R2, $M4 */ + SystemZ_LEXBRA /* 1466 */, SYSTEMZ_INS_LEXBRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* lexr $R1, $R2 */ + SystemZ_LEXR /* 1467 */, SYSTEMZ_INS_LEXR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ley $R1, $XBD2 */ + SystemZ_LEY /* 1468 */, SYSTEMZ_INS_LEY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lfas $BD2 */ + SystemZ_LFAS /* 1469 */, SYSTEMZ_INS_LFAS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_FPC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* lfh $R1, $XBD2 */ + SystemZ_LFH /* 1470 */, SYSTEMZ_INS_LFH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lfhat $R1, $XBD2 */ + SystemZ_LFHAT /* 1471 */, SYSTEMZ_INS_LFHAT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADANDTRAP, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lfpc $BD2 */ + SystemZ_LFPC /* 1472 */, SYSTEMZ_INS_LFPC, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_FPC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* lg $R1, $XBD2 */ + SystemZ_LG /* 1473 */, SYSTEMZ_INS_LG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lgat $R1, $XBD2 */ + SystemZ_LGAT /* 1474 */, SYSTEMZ_INS_LGAT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADANDTRAP, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lgb $R1, $XBD2 */ + SystemZ_LGB /* 1475 */, SYSTEMZ_INS_LGB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lgbr $R1, $R2 */ + SystemZ_LGBR /* 1476 */, SYSTEMZ_INS_LGBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lgdr $R1, $R2 */ + SystemZ_LGDR /* 1477 */, SYSTEMZ_INS_LGDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lgf $R1, $XBD2 */ + SystemZ_LGF /* 1478 */, SYSTEMZ_INS_LGF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lgfi $R1, $I2 */ + SystemZ_LGFI /* 1479 */, SYSTEMZ_INS_LGFI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* lgfr $R1, $R2 */ + SystemZ_LGFR /* 1480 */, SYSTEMZ_INS_LGFR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lgfrl $R1, $RI2 */ + SystemZ_LGFRL /* 1481 */, SYSTEMZ_INS_LGFRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* lgg $R1, $XBD2 */ + SystemZ_LGG /* 1482 */, SYSTEMZ_INS_LGG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREGUARDEDSTORAGE, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lgh $R1, $XBD2 */ + SystemZ_LGH /* 1483 */, SYSTEMZ_INS_LGH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lghi $R1, $I2 */ + SystemZ_LGHI /* 1484 */, SYSTEMZ_INS_LGHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* lghr $R1, $R2 */ + SystemZ_LGHR /* 1485 */, SYSTEMZ_INS_LGHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lghrl $R1, $RI2 */ + SystemZ_LGHRL /* 1486 */, SYSTEMZ_INS_LGHRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* lgr $R1, $R2 */ + SystemZ_LGR /* 1487 */, SYSTEMZ_INS_LGR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lgrl $R1, $RI2 */ + SystemZ_LGRL /* 1488 */, SYSTEMZ_INS_LGRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* lgsc $R1, $XBD2 */ + SystemZ_LGSC /* 1489 */, SYSTEMZ_INS_LGSC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREGUARDEDSTORAGE, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lh $R1, $XBD2 */ + SystemZ_LH /* 1490 */, SYSTEMZ_INS_LH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* lhh $R1, $XBD2 */ + SystemZ_LHH /* 1491 */, SYSTEMZ_INS_LHH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lhi $R1, $I2 */ + SystemZ_LHI /* 1492 */, SYSTEMZ_INS_LHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* lhr $R1, $R2 */ + SystemZ_LHR /* 1493 */, SYSTEMZ_INS_LHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lhrl $R1, $RI2 */ + SystemZ_LHRL /* 1494 */, SYSTEMZ_INS_LHRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* lhy $R1, $XBD2 */ + SystemZ_LHY /* 1495 */, SYSTEMZ_INS_LHY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* llc $R1, $XBD2 */ + SystemZ_LLC /* 1496 */, SYSTEMZ_INS_LLC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* llch $R1, $XBD2 */ + SystemZ_LLCH /* 1497 */, SYSTEMZ_INS_LLCH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* llcr $R1, $R2 */ + SystemZ_LLCR /* 1498 */, SYSTEMZ_INS_LLCR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* llgc $R1, $XBD2 */ + SystemZ_LLGC /* 1499 */, SYSTEMZ_INS_LLGC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* llgcr $R1, $R2 */ + SystemZ_LLGCR /* 1500 */, SYSTEMZ_INS_LLGCR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* llgf $R1, $XBD2 */ + SystemZ_LLGF /* 1501 */, SYSTEMZ_INS_LLGF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* llgfat $R1, $XBD2 */ + SystemZ_LLGFAT /* 1502 */, SYSTEMZ_INS_LLGFAT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADANDTRAP, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* llgfr $R1, $R2 */ + SystemZ_LLGFR /* 1503 */, SYSTEMZ_INS_LLGFR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* llgfrl $R1, $RI2 */ + SystemZ_LLGFRL /* 1504 */, SYSTEMZ_INS_LLGFRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* llgfsg $R1, $XBD2 */ + SystemZ_LLGFSG /* 1505 */, SYSTEMZ_INS_LLGFSG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREGUARDEDSTORAGE, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* llgh $R1, $XBD2 */ + SystemZ_LLGH /* 1506 */, SYSTEMZ_INS_LLGH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* llghr $R1, $R2 */ + SystemZ_LLGHR /* 1507 */, SYSTEMZ_INS_LLGHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* llghrl $R1, $RI2 */ + SystemZ_LLGHRL /* 1508 */, SYSTEMZ_INS_LLGHRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* llgt $R1, $XBD2 */ + SystemZ_LLGT /* 1509 */, SYSTEMZ_INS_LLGT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* llgtat $R1, $XBD2 */ + SystemZ_LLGTAT /* 1510 */, SYSTEMZ_INS_LLGTAT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADANDTRAP, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* llgtr $R1, $R2 */ + SystemZ_LLGTR /* 1511 */, SYSTEMZ_INS_LLGTR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* llh $R1, $XBD2 */ + SystemZ_LLH /* 1512 */, SYSTEMZ_INS_LLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* llhh $R1, $XBD2 */ + SystemZ_LLHH /* 1513 */, SYSTEMZ_INS_LLHH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* llhr $R1, $R2 */ + SystemZ_LLHR /* 1514 */, SYSTEMZ_INS_LLHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* llhrl $R1, $RI2 */ + SystemZ_LLHRL /* 1515 */, SYSTEMZ_INS_LLHRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* llihf $R1, $I2 */ + SystemZ_LLIHF /* 1516 */, SYSTEMZ_INS_LLIHF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* llihh $R1, $I2 */ + SystemZ_LLIHH /* 1517 */, SYSTEMZ_INS_LLIHH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* llihl $R1, $I2 */ + SystemZ_LLIHL /* 1518 */, SYSTEMZ_INS_LLIHL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* llilf $R1, $I2 */ + SystemZ_LLILF /* 1519 */, SYSTEMZ_INS_LLILF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* llilh $R1, $I2 */ + SystemZ_LLILH /* 1520 */, SYSTEMZ_INS_LLILH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* llill $R1, $I2 */ + SystemZ_LLILL /* 1521 */, SYSTEMZ_INS_LLILL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* llzrgf $R1, $XBD2 */ + SystemZ_LLZRGF /* 1522 */, SYSTEMZ_INS_LLZRGF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADANDZERORIGHTMOSTBYTE, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lm $R1, $R3, $BD2 */ + SystemZ_LM /* 1523 */, SYSTEMZ_INS_LM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* lmd $R1, $R3, $BD2, $BD4 */ + SystemZ_LMD /* 1524 */, SYSTEMZ_INS_LMD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSE }} + + #endif +}, +{ + /* lmg $R1, $R3, $BD2 */ + SystemZ_LMG /* 1525 */, SYSTEMZ_INS_LMG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* lmh $R1, $R3, $BD2 */ + SystemZ_LMH /* 1526 */, SYSTEMZ_INS_LMH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* lmy $R1, $R3, $BD2 */ + SystemZ_LMY /* 1527 */, SYSTEMZ_INS_LMY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* lndbr $R1, $R2 */ + SystemZ_LNDBR /* 1528 */, SYSTEMZ_INS_LNDBR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lndfr $R1, $R2 */ + SystemZ_LNDFR /* 1529 */, SYSTEMZ_INS_LNDFR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lndfr $R1, $R2 */ + SystemZ_LNDFR_32 /* 1530 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lndr $R1, $R2 */ + SystemZ_LNDR /* 1531 */, SYSTEMZ_INS_LNDR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* lnebr $R1, $R2 */ + SystemZ_LNEBR /* 1532 */, SYSTEMZ_INS_LNEBR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lner $R1, $R2 */ + SystemZ_LNER /* 1533 */, SYSTEMZ_INS_LNER, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* lngfr $R1, $R2 */ + SystemZ_LNGFR /* 1534 */, SYSTEMZ_INS_LNGFR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lngr $R1, $R2 */ + SystemZ_LNGR /* 1535 */, SYSTEMZ_INS_LNGR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lnr $R1, $R2 */ + SystemZ_LNR /* 1536 */, SYSTEMZ_INS_LNR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* lnxbr $R1, $R2 */ + SystemZ_LNXBR /* 1537 */, SYSTEMZ_INS_LNXBR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lnxr $R1, $R2 */ + SystemZ_LNXR /* 1538 */, SYSTEMZ_INS_LNXR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* loc$M3 $R1, $BD2 */ + SystemZ_LOC /* 1539 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* loc $R1, $BD2, $M3 */ + SystemZ_LOCAsm /* 1540 */, SYSTEMZ_INS_LOC, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* loce $R1, $BD2 */ + SystemZ_LOCAsmE /* 1541 */, SYSTEMZ_INS_LOCE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* loch $R1, $BD2 */ + SystemZ_LOCAsmH /* 1542 */, SYSTEMZ_INS_LOCH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* loche $R1, $BD2 */ + SystemZ_LOCAsmHE /* 1543 */, SYSTEMZ_INS_LOCHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locl $R1, $BD2 */ + SystemZ_LOCAsmL /* 1544 */, SYSTEMZ_INS_LOCL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locle $R1, $BD2 */ + SystemZ_LOCAsmLE /* 1545 */, SYSTEMZ_INS_LOCLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* loclh $R1, $BD2 */ + SystemZ_LOCAsmLH /* 1546 */, SYSTEMZ_INS_LOCLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locm $R1, $BD2 */ + SystemZ_LOCAsmM /* 1547 */, SYSTEMZ_INS_LOCM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locne $R1, $BD2 */ + SystemZ_LOCAsmNE /* 1548 */, SYSTEMZ_INS_LOCNE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locnh $R1, $BD2 */ + SystemZ_LOCAsmNH /* 1549 */, SYSTEMZ_INS_LOCNH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locnhe $R1, $BD2 */ + SystemZ_LOCAsmNHE /* 1550 */, SYSTEMZ_INS_LOCNHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locnl $R1, $BD2 */ + SystemZ_LOCAsmNL /* 1551 */, SYSTEMZ_INS_LOCNL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locnle $R1, $BD2 */ + SystemZ_LOCAsmNLE /* 1552 */, SYSTEMZ_INS_LOCNLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locnlh $R1, $BD2 */ + SystemZ_LOCAsmNLH /* 1553 */, SYSTEMZ_INS_LOCNLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locnm $R1, $BD2 */ + SystemZ_LOCAsmNM /* 1554 */, SYSTEMZ_INS_LOCNM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locno $R1, $BD2 */ + SystemZ_LOCAsmNO /* 1555 */, SYSTEMZ_INS_LOCNO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locnp $R1, $BD2 */ + SystemZ_LOCAsmNP /* 1556 */, SYSTEMZ_INS_LOCNP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locnz $R1, $BD2 */ + SystemZ_LOCAsmNZ /* 1557 */, SYSTEMZ_INS_LOCNZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* loco $R1, $BD2 */ + SystemZ_LOCAsmO /* 1558 */, SYSTEMZ_INS_LOCO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locp $R1, $BD2 */ + SystemZ_LOCAsmP /* 1559 */, SYSTEMZ_INS_LOCP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locz $R1, $BD2 */ + SystemZ_LOCAsmZ /* 1560 */, SYSTEMZ_INS_LOCZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfh$M3 $R1, $BD2 */ + SystemZ_LOCFH /* 1561 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* locfh $R1, $BD2, $M3 */ + SystemZ_LOCFHAsm /* 1562 */, SYSTEMZ_INS_LOCFH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhe $R1, $BD2 */ + SystemZ_LOCFHAsmE /* 1563 */, SYSTEMZ_INS_LOCFHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhh $R1, $BD2 */ + SystemZ_LOCFHAsmH /* 1564 */, SYSTEMZ_INS_LOCFHH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhhe $R1, $BD2 */ + SystemZ_LOCFHAsmHE /* 1565 */, SYSTEMZ_INS_LOCFHHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhl $R1, $BD2 */ + SystemZ_LOCFHAsmL /* 1566 */, SYSTEMZ_INS_LOCFHL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhle $R1, $BD2 */ + SystemZ_LOCFHAsmLE /* 1567 */, SYSTEMZ_INS_LOCFHLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhlh $R1, $BD2 */ + SystemZ_LOCFHAsmLH /* 1568 */, SYSTEMZ_INS_LOCFHLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhm $R1, $BD2 */ + SystemZ_LOCFHAsmM /* 1569 */, SYSTEMZ_INS_LOCFHM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhne $R1, $BD2 */ + SystemZ_LOCFHAsmNE /* 1570 */, SYSTEMZ_INS_LOCFHNE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhnh $R1, $BD2 */ + SystemZ_LOCFHAsmNH /* 1571 */, SYSTEMZ_INS_LOCFHNH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhnhe $R1, $BD2 */ + SystemZ_LOCFHAsmNHE /* 1572 */, SYSTEMZ_INS_LOCFHNHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhnl $R1, $BD2 */ + SystemZ_LOCFHAsmNL /* 1573 */, SYSTEMZ_INS_LOCFHNL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhnle $R1, $BD2 */ + SystemZ_LOCFHAsmNLE /* 1574 */, SYSTEMZ_INS_LOCFHNLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhnlh $R1, $BD2 */ + SystemZ_LOCFHAsmNLH /* 1575 */, SYSTEMZ_INS_LOCFHNLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhnm $R1, $BD2 */ + SystemZ_LOCFHAsmNM /* 1576 */, SYSTEMZ_INS_LOCFHNM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhno $R1, $BD2 */ + SystemZ_LOCFHAsmNO /* 1577 */, SYSTEMZ_INS_LOCFHNO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhnp $R1, $BD2 */ + SystemZ_LOCFHAsmNP /* 1578 */, SYSTEMZ_INS_LOCFHNP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhnz $R1, $BD2 */ + SystemZ_LOCFHAsmNZ /* 1579 */, SYSTEMZ_INS_LOCFHNZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfho $R1, $BD2 */ + SystemZ_LOCFHAsmO /* 1580 */, SYSTEMZ_INS_LOCFHO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhp $R1, $BD2 */ + SystemZ_LOCFHAsmP /* 1581 */, SYSTEMZ_INS_LOCFHP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhz $R1, $BD2 */ + SystemZ_LOCFHAsmZ /* 1582 */, SYSTEMZ_INS_LOCFHZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locfhr$M3 $R1, $R2 */ + SystemZ_LOCFHR /* 1583 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* locfhr $R1, $R2, $M3 */ + SystemZ_LOCFHRAsm /* 1584 */, SYSTEMZ_INS_LOCFHR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhre $R1, $R2 */ + SystemZ_LOCFHRAsmE /* 1585 */, SYSTEMZ_INS_LOCFHRE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhrh $R1, $R2 */ + SystemZ_LOCFHRAsmH /* 1586 */, SYSTEMZ_INS_LOCFHRH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhrhe $R1, $R2 */ + SystemZ_LOCFHRAsmHE /* 1587 */, SYSTEMZ_INS_LOCFHRHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhrl $R1, $R2 */ + SystemZ_LOCFHRAsmL /* 1588 */, SYSTEMZ_INS_LOCFHRL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhrle $R1, $R2 */ + SystemZ_LOCFHRAsmLE /* 1589 */, SYSTEMZ_INS_LOCFHRLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhrlh $R1, $R2 */ + SystemZ_LOCFHRAsmLH /* 1590 */, SYSTEMZ_INS_LOCFHRLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhrm $R1, $R2 */ + SystemZ_LOCFHRAsmM /* 1591 */, SYSTEMZ_INS_LOCFHRM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhrne $R1, $R2 */ + SystemZ_LOCFHRAsmNE /* 1592 */, SYSTEMZ_INS_LOCFHRNE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhrnh $R1, $R2 */ + SystemZ_LOCFHRAsmNH /* 1593 */, SYSTEMZ_INS_LOCFHRNH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhrnhe $R1, $R2 */ + SystemZ_LOCFHRAsmNHE /* 1594 */, SYSTEMZ_INS_LOCFHRNHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhrnl $R1, $R2 */ + SystemZ_LOCFHRAsmNL /* 1595 */, SYSTEMZ_INS_LOCFHRNL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhrnle $R1, $R2 */ + SystemZ_LOCFHRAsmNLE /* 1596 */, SYSTEMZ_INS_LOCFHRNLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhrnlh $R1, $R2 */ + SystemZ_LOCFHRAsmNLH /* 1597 */, SYSTEMZ_INS_LOCFHRNLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhrnm $R1, $R2 */ + SystemZ_LOCFHRAsmNM /* 1598 */, SYSTEMZ_INS_LOCFHRNM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhrno $R1, $R2 */ + SystemZ_LOCFHRAsmNO /* 1599 */, SYSTEMZ_INS_LOCFHRNO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhrnp $R1, $R2 */ + SystemZ_LOCFHRAsmNP /* 1600 */, SYSTEMZ_INS_LOCFHRNP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhrnz $R1, $R2 */ + SystemZ_LOCFHRAsmNZ /* 1601 */, SYSTEMZ_INS_LOCFHRNZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhro $R1, $R2 */ + SystemZ_LOCFHRAsmO /* 1602 */, SYSTEMZ_INS_LOCFHRO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhrp $R1, $R2 */ + SystemZ_LOCFHRAsmP /* 1603 */, SYSTEMZ_INS_LOCFHRP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locfhrz $R1, $R2 */ + SystemZ_LOCFHRAsmZ /* 1604 */, SYSTEMZ_INS_LOCFHRZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locg$M3 $R1, $BD2 */ + SystemZ_LOCG /* 1605 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* locg $R1, $BD2, $M3 */ + SystemZ_LOCGAsm /* 1606 */, SYSTEMZ_INS_LOCG, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locge $R1, $BD2 */ + SystemZ_LOCGAsmE /* 1607 */, SYSTEMZ_INS_LOCGE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locgh $R1, $BD2 */ + SystemZ_LOCGAsmH /* 1608 */, SYSTEMZ_INS_LOCGH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locghe $R1, $BD2 */ + SystemZ_LOCGAsmHE /* 1609 */, SYSTEMZ_INS_LOCGHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locgl $R1, $BD2 */ + SystemZ_LOCGAsmL /* 1610 */, SYSTEMZ_INS_LOCGL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locgle $R1, $BD2 */ + SystemZ_LOCGAsmLE /* 1611 */, SYSTEMZ_INS_LOCGLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locglh $R1, $BD2 */ + SystemZ_LOCGAsmLH /* 1612 */, SYSTEMZ_INS_LOCGLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locgm $R1, $BD2 */ + SystemZ_LOCGAsmM /* 1613 */, SYSTEMZ_INS_LOCGM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locgne $R1, $BD2 */ + SystemZ_LOCGAsmNE /* 1614 */, SYSTEMZ_INS_LOCGNE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locgnh $R1, $BD2 */ + SystemZ_LOCGAsmNH /* 1615 */, SYSTEMZ_INS_LOCGNH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locgnhe $R1, $BD2 */ + SystemZ_LOCGAsmNHE /* 1616 */, SYSTEMZ_INS_LOCGNHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locgnl $R1, $BD2 */ + SystemZ_LOCGAsmNL /* 1617 */, SYSTEMZ_INS_LOCGNL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locgnle $R1, $BD2 */ + SystemZ_LOCGAsmNLE /* 1618 */, SYSTEMZ_INS_LOCGNLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locgnlh $R1, $BD2 */ + SystemZ_LOCGAsmNLH /* 1619 */, SYSTEMZ_INS_LOCGNLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locgnm $R1, $BD2 */ + SystemZ_LOCGAsmNM /* 1620 */, SYSTEMZ_INS_LOCGNM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locgno $R1, $BD2 */ + SystemZ_LOCGAsmNO /* 1621 */, SYSTEMZ_INS_LOCGNO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locgnp $R1, $BD2 */ + SystemZ_LOCGAsmNP /* 1622 */, SYSTEMZ_INS_LOCGNP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locgnz $R1, $BD2 */ + SystemZ_LOCGAsmNZ /* 1623 */, SYSTEMZ_INS_LOCGNZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locgo $R1, $BD2 */ + SystemZ_LOCGAsmO /* 1624 */, SYSTEMZ_INS_LOCGO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locgp $R1, $BD2 */ + SystemZ_LOCGAsmP /* 1625 */, SYSTEMZ_INS_LOCGP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locgz $R1, $BD2 */ + SystemZ_LOCGAsmZ /* 1626 */, SYSTEMZ_INS_LOCGZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* locghi$M3 $R1, $I2 */ + SystemZ_LOCGHI /* 1627 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* locghi $R1, $I2, $M3 */ + SystemZ_LOCGHIAsm /* 1628 */, SYSTEMZ_INS_LOCGHI, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghie $R1, $I2 */ + SystemZ_LOCGHIAsmE /* 1629 */, SYSTEMZ_INS_LOCGHIE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghih $R1, $I2 */ + SystemZ_LOCGHIAsmH /* 1630 */, SYSTEMZ_INS_LOCGHIH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghihe $R1, $I2 */ + SystemZ_LOCGHIAsmHE /* 1631 */, SYSTEMZ_INS_LOCGHIHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghil $R1, $I2 */ + SystemZ_LOCGHIAsmL /* 1632 */, SYSTEMZ_INS_LOCGHIL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghile $R1, $I2 */ + SystemZ_LOCGHIAsmLE /* 1633 */, SYSTEMZ_INS_LOCGHILE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghilh $R1, $I2 */ + SystemZ_LOCGHIAsmLH /* 1634 */, SYSTEMZ_INS_LOCGHILH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghim $R1, $I2 */ + SystemZ_LOCGHIAsmM /* 1635 */, SYSTEMZ_INS_LOCGHIM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghine $R1, $I2 */ + SystemZ_LOCGHIAsmNE /* 1636 */, SYSTEMZ_INS_LOCGHINE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghinh $R1, $I2 */ + SystemZ_LOCGHIAsmNH /* 1637 */, SYSTEMZ_INS_LOCGHINH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghinhe $R1, $I2 */ + SystemZ_LOCGHIAsmNHE /* 1638 */, SYSTEMZ_INS_LOCGHINHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghinl $R1, $I2 */ + SystemZ_LOCGHIAsmNL /* 1639 */, SYSTEMZ_INS_LOCGHINL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghinle $R1, $I2 */ + SystemZ_LOCGHIAsmNLE /* 1640 */, SYSTEMZ_INS_LOCGHINLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghinlh $R1, $I2 */ + SystemZ_LOCGHIAsmNLH /* 1641 */, SYSTEMZ_INS_LOCGHINLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghinm $R1, $I2 */ + SystemZ_LOCGHIAsmNM /* 1642 */, SYSTEMZ_INS_LOCGHINM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghino $R1, $I2 */ + SystemZ_LOCGHIAsmNO /* 1643 */, SYSTEMZ_INS_LOCGHINO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghinp $R1, $I2 */ + SystemZ_LOCGHIAsmNP /* 1644 */, SYSTEMZ_INS_LOCGHINP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghinz $R1, $I2 */ + SystemZ_LOCGHIAsmNZ /* 1645 */, SYSTEMZ_INS_LOCGHINZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghio $R1, $I2 */ + SystemZ_LOCGHIAsmO /* 1646 */, SYSTEMZ_INS_LOCGHIO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghip $R1, $I2 */ + SystemZ_LOCGHIAsmP /* 1647 */, SYSTEMZ_INS_LOCGHIP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locghiz $R1, $I2 */ + SystemZ_LOCGHIAsmZ /* 1648 */, SYSTEMZ_INS_LOCGHIZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locgr$M3 $R1, $R2 */ + SystemZ_LOCGR /* 1649 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* locgr $R1, $R2, $M3 */ + SystemZ_LOCGRAsm /* 1650 */, SYSTEMZ_INS_LOCGR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgre $R1, $R2 */ + SystemZ_LOCGRAsmE /* 1651 */, SYSTEMZ_INS_LOCGRE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgrh $R1, $R2 */ + SystemZ_LOCGRAsmH /* 1652 */, SYSTEMZ_INS_LOCGRH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgrhe $R1, $R2 */ + SystemZ_LOCGRAsmHE /* 1653 */, SYSTEMZ_INS_LOCGRHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgrl $R1, $R2 */ + SystemZ_LOCGRAsmL /* 1654 */, SYSTEMZ_INS_LOCGRL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgrle $R1, $R2 */ + SystemZ_LOCGRAsmLE /* 1655 */, SYSTEMZ_INS_LOCGRLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgrlh $R1, $R2 */ + SystemZ_LOCGRAsmLH /* 1656 */, SYSTEMZ_INS_LOCGRLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgrm $R1, $R2 */ + SystemZ_LOCGRAsmM /* 1657 */, SYSTEMZ_INS_LOCGRM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgrne $R1, $R2 */ + SystemZ_LOCGRAsmNE /* 1658 */, SYSTEMZ_INS_LOCGRNE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgrnh $R1, $R2 */ + SystemZ_LOCGRAsmNH /* 1659 */, SYSTEMZ_INS_LOCGRNH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgrnhe $R1, $R2 */ + SystemZ_LOCGRAsmNHE /* 1660 */, SYSTEMZ_INS_LOCGRNHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgrnl $R1, $R2 */ + SystemZ_LOCGRAsmNL /* 1661 */, SYSTEMZ_INS_LOCGRNL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgrnle $R1, $R2 */ + SystemZ_LOCGRAsmNLE /* 1662 */, SYSTEMZ_INS_LOCGRNLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgrnlh $R1, $R2 */ + SystemZ_LOCGRAsmNLH /* 1663 */, SYSTEMZ_INS_LOCGRNLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgrnm $R1, $R2 */ + SystemZ_LOCGRAsmNM /* 1664 */, SYSTEMZ_INS_LOCGRNM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgrno $R1, $R2 */ + SystemZ_LOCGRAsmNO /* 1665 */, SYSTEMZ_INS_LOCGRNO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgrnp $R1, $R2 */ + SystemZ_LOCGRAsmNP /* 1666 */, SYSTEMZ_INS_LOCGRNP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgrnz $R1, $R2 */ + SystemZ_LOCGRAsmNZ /* 1667 */, SYSTEMZ_INS_LOCGRNZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgro $R1, $R2 */ + SystemZ_LOCGRAsmO /* 1668 */, SYSTEMZ_INS_LOCGRO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgrp $R1, $R2 */ + SystemZ_LOCGRAsmP /* 1669 */, SYSTEMZ_INS_LOCGRP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locgrz $R1, $R2 */ + SystemZ_LOCGRAsmZ /* 1670 */, SYSTEMZ_INS_LOCGRZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* lochhi$M3 $R1, $I2 */ + SystemZ_LOCHHI /* 1671 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lochhi $R1, $I2, $M3 */ + SystemZ_LOCHHIAsm /* 1672 */, SYSTEMZ_INS_LOCHHI, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhie $R1, $I2 */ + SystemZ_LOCHHIAsmE /* 1673 */, SYSTEMZ_INS_LOCHHIE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhih $R1, $I2 */ + SystemZ_LOCHHIAsmH /* 1674 */, SYSTEMZ_INS_LOCHHIH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhihe $R1, $I2 */ + SystemZ_LOCHHIAsmHE /* 1675 */, SYSTEMZ_INS_LOCHHIHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhil $R1, $I2 */ + SystemZ_LOCHHIAsmL /* 1676 */, SYSTEMZ_INS_LOCHHIL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhile $R1, $I2 */ + SystemZ_LOCHHIAsmLE /* 1677 */, SYSTEMZ_INS_LOCHHILE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhilh $R1, $I2 */ + SystemZ_LOCHHIAsmLH /* 1678 */, SYSTEMZ_INS_LOCHHILH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhim $R1, $I2 */ + SystemZ_LOCHHIAsmM /* 1679 */, SYSTEMZ_INS_LOCHHIM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhine $R1, $I2 */ + SystemZ_LOCHHIAsmNE /* 1680 */, SYSTEMZ_INS_LOCHHINE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhinh $R1, $I2 */ + SystemZ_LOCHHIAsmNH /* 1681 */, SYSTEMZ_INS_LOCHHINH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhinhe $R1, $I2 */ + SystemZ_LOCHHIAsmNHE /* 1682 */, SYSTEMZ_INS_LOCHHINHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhinl $R1, $I2 */ + SystemZ_LOCHHIAsmNL /* 1683 */, SYSTEMZ_INS_LOCHHINL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhinle $R1, $I2 */ + SystemZ_LOCHHIAsmNLE /* 1684 */, SYSTEMZ_INS_LOCHHINLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhinlh $R1, $I2 */ + SystemZ_LOCHHIAsmNLH /* 1685 */, SYSTEMZ_INS_LOCHHINLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhinm $R1, $I2 */ + SystemZ_LOCHHIAsmNM /* 1686 */, SYSTEMZ_INS_LOCHHINM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhino $R1, $I2 */ + SystemZ_LOCHHIAsmNO /* 1687 */, SYSTEMZ_INS_LOCHHINO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhinp $R1, $I2 */ + SystemZ_LOCHHIAsmNP /* 1688 */, SYSTEMZ_INS_LOCHHINP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhinz $R1, $I2 */ + SystemZ_LOCHHIAsmNZ /* 1689 */, SYSTEMZ_INS_LOCHHINZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhio $R1, $I2 */ + SystemZ_LOCHHIAsmO /* 1690 */, SYSTEMZ_INS_LOCHHIO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhip $R1, $I2 */ + SystemZ_LOCHHIAsmP /* 1691 */, SYSTEMZ_INS_LOCHHIP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochhiz $R1, $I2 */ + SystemZ_LOCHHIAsmZ /* 1692 */, SYSTEMZ_INS_LOCHHIZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochi$M3 $R1, $I2 */ + SystemZ_LOCHI /* 1693 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lochi $R1, $I2, $M3 */ + SystemZ_LOCHIAsm /* 1694 */, SYSTEMZ_INS_LOCHI, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochie $R1, $I2 */ + SystemZ_LOCHIAsmE /* 1695 */, SYSTEMZ_INS_LOCHIE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochih $R1, $I2 */ + SystemZ_LOCHIAsmH /* 1696 */, SYSTEMZ_INS_LOCHIH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochihe $R1, $I2 */ + SystemZ_LOCHIAsmHE /* 1697 */, SYSTEMZ_INS_LOCHIHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochil $R1, $I2 */ + SystemZ_LOCHIAsmL /* 1698 */, SYSTEMZ_INS_LOCHIL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochile $R1, $I2 */ + SystemZ_LOCHIAsmLE /* 1699 */, SYSTEMZ_INS_LOCHILE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochilh $R1, $I2 */ + SystemZ_LOCHIAsmLH /* 1700 */, SYSTEMZ_INS_LOCHILH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochim $R1, $I2 */ + SystemZ_LOCHIAsmM /* 1701 */, SYSTEMZ_INS_LOCHIM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochine $R1, $I2 */ + SystemZ_LOCHIAsmNE /* 1702 */, SYSTEMZ_INS_LOCHINE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochinh $R1, $I2 */ + SystemZ_LOCHIAsmNH /* 1703 */, SYSTEMZ_INS_LOCHINH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochinhe $R1, $I2 */ + SystemZ_LOCHIAsmNHE /* 1704 */, SYSTEMZ_INS_LOCHINHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochinl $R1, $I2 */ + SystemZ_LOCHIAsmNL /* 1705 */, SYSTEMZ_INS_LOCHINL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochinle $R1, $I2 */ + SystemZ_LOCHIAsmNLE /* 1706 */, SYSTEMZ_INS_LOCHINLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochinlh $R1, $I2 */ + SystemZ_LOCHIAsmNLH /* 1707 */, SYSTEMZ_INS_LOCHINLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochinm $R1, $I2 */ + SystemZ_LOCHIAsmNM /* 1708 */, SYSTEMZ_INS_LOCHINM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochino $R1, $I2 */ + SystemZ_LOCHIAsmNO /* 1709 */, SYSTEMZ_INS_LOCHINO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochinp $R1, $I2 */ + SystemZ_LOCHIAsmNP /* 1710 */, SYSTEMZ_INS_LOCHINP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochinz $R1, $I2 */ + SystemZ_LOCHIAsmNZ /* 1711 */, SYSTEMZ_INS_LOCHINZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochio $R1, $I2 */ + SystemZ_LOCHIAsmO /* 1712 */, SYSTEMZ_INS_LOCHIO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochip $R1, $I2 */ + SystemZ_LOCHIAsmP /* 1713 */, SYSTEMZ_INS_LOCHIP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* lochiz $R1, $I2 */ + SystemZ_LOCHIAsmZ /* 1714 */, SYSTEMZ_INS_LOCHIZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEG }} + + #endif +}, +{ + /* locr$M3 $R1, $R2 */ + SystemZ_LOCR /* 1715 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* locr $R1, $R2, $M3 */ + SystemZ_LOCRAsm /* 1716 */, SYSTEMZ_INS_LOCR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locre $R1, $R2 */ + SystemZ_LOCRAsmE /* 1717 */, SYSTEMZ_INS_LOCRE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locrh $R1, $R2 */ + SystemZ_LOCRAsmH /* 1718 */, SYSTEMZ_INS_LOCRH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locrhe $R1, $R2 */ + SystemZ_LOCRAsmHE /* 1719 */, SYSTEMZ_INS_LOCRHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locrl $R1, $R2 */ + SystemZ_LOCRAsmL /* 1720 */, SYSTEMZ_INS_LOCRL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locrle $R1, $R2 */ + SystemZ_LOCRAsmLE /* 1721 */, SYSTEMZ_INS_LOCRLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locrlh $R1, $R2 */ + SystemZ_LOCRAsmLH /* 1722 */, SYSTEMZ_INS_LOCRLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locrm $R1, $R2 */ + SystemZ_LOCRAsmM /* 1723 */, SYSTEMZ_INS_LOCRM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locrne $R1, $R2 */ + SystemZ_LOCRAsmNE /* 1724 */, SYSTEMZ_INS_LOCRNE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locrnh $R1, $R2 */ + SystemZ_LOCRAsmNH /* 1725 */, SYSTEMZ_INS_LOCRNH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locrnhe $R1, $R2 */ + SystemZ_LOCRAsmNHE /* 1726 */, SYSTEMZ_INS_LOCRNHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locrnl $R1, $R2 */ + SystemZ_LOCRAsmNL /* 1727 */, SYSTEMZ_INS_LOCRNL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locrnle $R1, $R2 */ + SystemZ_LOCRAsmNLE /* 1728 */, SYSTEMZ_INS_LOCRNLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locrnlh $R1, $R2 */ + SystemZ_LOCRAsmNLH /* 1729 */, SYSTEMZ_INS_LOCRNLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locrnm $R1, $R2 */ + SystemZ_LOCRAsmNM /* 1730 */, SYSTEMZ_INS_LOCRNM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locrno $R1, $R2 */ + SystemZ_LOCRAsmNO /* 1731 */, SYSTEMZ_INS_LOCRNO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locrnp $R1, $R2 */ + SystemZ_LOCRAsmNP /* 1732 */, SYSTEMZ_INS_LOCRNP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locrnz $R1, $R2 */ + SystemZ_LOCRAsmNZ /* 1733 */, SYSTEMZ_INS_LOCRNZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locro $R1, $R2 */ + SystemZ_LOCRAsmO /* 1734 */, SYSTEMZ_INS_LOCRO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locrp $R1, $R2 */ + SystemZ_LOCRAsmP /* 1735 */, SYSTEMZ_INS_LOCRP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* locrz $R1, $R2 */ + SystemZ_LOCRAsmZ /* 1736 */, SYSTEMZ_INS_LOCRZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* lpctl $BD2 */ + SystemZ_LPCTL /* 1737 */, SYSTEMZ_INS_LPCTL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* lpd $R3, $BD1, $BD2 */ + SystemZ_LPD /* 1738 */, SYSTEMZ_INS_LPD, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREINTERLOCKEDACCESS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSF }} + + #endif +}, +{ + /* lpdbr $R1, $R2 */ + SystemZ_LPDBR /* 1739 */, SYSTEMZ_INS_LPDBR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lpdfr $R1, $R2 */ + SystemZ_LPDFR /* 1740 */, SYSTEMZ_INS_LPDFR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lpdfr $R1, $R2 */ + SystemZ_LPDFR_32 /* 1741 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* lpdg $R3, $BD1, $BD2 */ + SystemZ_LPDG /* 1742 */, SYSTEMZ_INS_LPDG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREINTERLOCKEDACCESS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSF }} + + #endif +}, +{ + /* lpdr $R1, $R2 */ + SystemZ_LPDR /* 1743 */, SYSTEMZ_INS_LPDR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* lpebr $R1, $R2 */ + SystemZ_LPEBR /* 1744 */, SYSTEMZ_INS_LPEBR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lper $R1, $R2 */ + SystemZ_LPER /* 1745 */, SYSTEMZ_INS_LPER, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* lpgfr $R1, $R2 */ + SystemZ_LPGFR /* 1746 */, SYSTEMZ_INS_LPGFR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lpgr $R1, $R2 */ + SystemZ_LPGR /* 1747 */, SYSTEMZ_INS_LPGR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lpp $BD2 */ + SystemZ_LPP /* 1748 */, SYSTEMZ_INS_LPP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* lpq $R1, $XBD2 */ + SystemZ_LPQ /* 1749 */, SYSTEMZ_INS_LPQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lpr $R1, $R2 */ + SystemZ_LPR /* 1750 */, SYSTEMZ_INS_LPR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* lpsw $BD2 */ + SystemZ_LPSW /* 1751 */, SYSTEMZ_INS_LPSW, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* lpswe $BD2 */ + SystemZ_LPSWE /* 1752 */, SYSTEMZ_INS_LPSWE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* lpswey $BD1 */ + SystemZ_LPSWEY /* 1753 */, SYSTEMZ_INS_LPSWEY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREBEARENHANCEMENT, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIY }} + + #endif +}, +{ + /* lptea $R1, $R3, $R2, $M4 */ + SystemZ_LPTEA /* 1754 */, SYSTEMZ_INS_LPTEA, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFB }} + + #endif +}, +{ + /* lpxbr $R1, $R2 */ + SystemZ_LPXBR /* 1755 */, SYSTEMZ_INS_LPXBR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lpxr $R1, $R2 */ + SystemZ_LPXR /* 1756 */, SYSTEMZ_INS_LPXR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lr $R1, $R2 */ + SystemZ_LR /* 1757 */, SYSTEMZ_INS_LR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* lra $R1, $XBD2 */ + SystemZ_LRA /* 1758 */, SYSTEMZ_INS_LRA, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* lrag $R1, $XBD2 */ + SystemZ_LRAG /* 1759 */, SYSTEMZ_INS_LRAG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lray $R1, $XBD2 */ + SystemZ_LRAY /* 1760 */, SYSTEMZ_INS_LRAY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lrdr $R1, $R2 */ + SystemZ_LRDR /* 1761 */, SYSTEMZ_INS_LRDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* lrer $R1, $R2 */ + SystemZ_LRER /* 1762 */, SYSTEMZ_INS_LRER, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* lrl $R1, $RI2 */ + SystemZ_LRL /* 1763 */, SYSTEMZ_INS_LRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* lrv $R1, $XBD2 */ + SystemZ_LRV /* 1764 */, SYSTEMZ_INS_LRV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lrvg $R1, $XBD2 */ + SystemZ_LRVG /* 1765 */, SYSTEMZ_INS_LRVG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lrvgr $R1, $R2 */ + SystemZ_LRVGR /* 1766 */, SYSTEMZ_INS_LRVGR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lrvh $R1, $XBD2 */ + SystemZ_LRVH /* 1767 */, SYSTEMZ_INS_LRVH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lrvr $R1, $R2 */ + SystemZ_LRVR /* 1768 */, SYSTEMZ_INS_LRVR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lsctl $BD2 */ + SystemZ_LSCTL /* 1769 */, SYSTEMZ_INS_LSCTL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* lt $R1, $XBD2 */ + SystemZ_LT /* 1770 */, SYSTEMZ_INS_LT, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* ltdbr $R1, $R2 */ + SystemZ_LTDBR /* 1771 */, SYSTEMZ_INS_LTDBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ltdr $R1, $R2 */ + SystemZ_LTDR /* 1772 */, SYSTEMZ_INS_LTDR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* ltdtr $R1, $R2 */ + SystemZ_LTDTR /* 1773 */, SYSTEMZ_INS_LTDTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ltebr $R1, $R2 */ + SystemZ_LTEBR /* 1774 */, SYSTEMZ_INS_LTEBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lter $R1, $R2 */ + SystemZ_LTER /* 1775 */, SYSTEMZ_INS_LTER, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* ltg $R1, $XBD2 */ + SystemZ_LTG /* 1776 */, SYSTEMZ_INS_LTG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* ltgf $R1, $XBD2 */ + SystemZ_LTGF /* 1777 */, SYSTEMZ_INS_LTGF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* ltgfr $R1, $R2 */ + SystemZ_LTGFR /* 1778 */, SYSTEMZ_INS_LTGFR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ltgr $R1, $R2 */ + SystemZ_LTGR /* 1779 */, SYSTEMZ_INS_LTGR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ltr $R1, $R2 */ + SystemZ_LTR /* 1780 */, SYSTEMZ_INS_LTR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* ltxbr $R1, $R2 */ + SystemZ_LTXBR /* 1781 */, SYSTEMZ_INS_LTXBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ltxr $R1, $R2 */ + SystemZ_LTXR /* 1782 */, SYSTEMZ_INS_LTXR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ltxtr $R1, $R2 */ + SystemZ_LTXTR /* 1783 */, SYSTEMZ_INS_LTXTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lura $R1, $R2 */ + SystemZ_LURA /* 1784 */, SYSTEMZ_INS_LURA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lurag $R1, $R2 */ + SystemZ_LURAG /* 1785 */, SYSTEMZ_INS_LURAG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lxd $R1, $XBD2 */ + SystemZ_LXD /* 1786 */, SYSTEMZ_INS_LXD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* lxdb $R1, $XBD2 */ + SystemZ_LXDB /* 1787 */, SYSTEMZ_INS_LXDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* lxdbr $R1, $R2 */ + SystemZ_LXDBR /* 1788 */, SYSTEMZ_INS_LXDBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lxdr $R1, $R2 */ + SystemZ_LXDR /* 1789 */, SYSTEMZ_INS_LXDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lxdtr $R1, $R2, $M4 */ + SystemZ_LXDTR /* 1790 */, SYSTEMZ_INS_LXDTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFD }} + + #endif +}, +{ + /* lxe $R1, $XBD2 */ + SystemZ_LXE /* 1791 */, SYSTEMZ_INS_LXE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* lxeb $R1, $XBD2 */ + SystemZ_LXEB /* 1792 */, SYSTEMZ_INS_LXEB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* lxebr $R1, $R2 */ + SystemZ_LXEBR /* 1793 */, SYSTEMZ_INS_LXEBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lxer $R1, $R2 */ + SystemZ_LXER /* 1794 */, SYSTEMZ_INS_LXER, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lxr $R1, $R2 */ + SystemZ_LXR /* 1795 */, SYSTEMZ_INS_LXR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ly $R1, $XBD2 */ + SystemZ_LY /* 1796 */, SYSTEMZ_INS_LY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lzdr $R1 */ + SystemZ_LZDR /* 1797 */, SYSTEMZ_INS_LZDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lzer $R1 */ + SystemZ_LZER /* 1798 */, SYSTEMZ_INS_LZER, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* lzrf $R1, $XBD2 */ + SystemZ_LZRF /* 1799 */, SYSTEMZ_INS_LZRF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADANDZERORIGHTMOSTBYTE, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lzrg $R1, $XBD2 */ + SystemZ_LZRG /* 1800 */, SYSTEMZ_INS_LZRG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADANDZERORIGHTMOSTBYTE, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* lzxr $R1 */ + SystemZ_LZXR /* 1801 */, SYSTEMZ_INS_LZXR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* m $R1, $XBD2 */ + SystemZ_M /* 1802 */, SYSTEMZ_INS_M, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* mad $R1, $R3, $XBD2 */ + SystemZ_MAD /* 1803 */, SYSTEMZ_INS_MAD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXF }} + + #endif +}, +{ + /* madb $R1, $R3, $XBD2 */ + SystemZ_MADB /* 1804 */, SYSTEMZ_INS_MADB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXF }} + + #endif +}, +{ + /* madbr $R1, $R3, $R2 */ + SystemZ_MADBR /* 1805 */, SYSTEMZ_INS_MADBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRD }} + + #endif +}, +{ + /* madr $R1, $R3, $R2 */ + SystemZ_MADR /* 1806 */, SYSTEMZ_INS_MADR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRD }} + + #endif +}, +{ + /* mae $R1, $R3, $XBD2 */ + SystemZ_MAE /* 1807 */, SYSTEMZ_INS_MAE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXF }} + + #endif +}, +{ + /* maeb $R1, $R3, $XBD2 */ + SystemZ_MAEB /* 1808 */, SYSTEMZ_INS_MAEB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXF }} + + #endif +}, +{ + /* maebr $R1, $R3, $R2 */ + SystemZ_MAEBR /* 1809 */, SYSTEMZ_INS_MAEBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRD }} + + #endif +}, +{ + /* maer $R1, $R3, $R2 */ + SystemZ_MAER /* 1810 */, SYSTEMZ_INS_MAER, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRD }} + + #endif +}, +{ + /* may $R1, $R3, $XBD2 */ + SystemZ_MAY /* 1811 */, SYSTEMZ_INS_MAY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXF }} + + #endif +}, +{ + /* mayh $R1, $R3, $XBD2 */ + SystemZ_MAYH /* 1812 */, SYSTEMZ_INS_MAYH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXF }} + + #endif +}, +{ + /* mayhr $R1, $R3, $R2 */ + SystemZ_MAYHR /* 1813 */, SYSTEMZ_INS_MAYHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRD }} + + #endif +}, +{ + /* mayl $R1, $R3, $XBD2 */ + SystemZ_MAYL /* 1814 */, SYSTEMZ_INS_MAYL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXF }} + + #endif +}, +{ + /* maylr $R1, $R3, $R2 */ + SystemZ_MAYLR /* 1815 */, SYSTEMZ_INS_MAYLR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRD }} + + #endif +}, +{ + /* mayr $R1, $R3, $R2 */ + SystemZ_MAYR /* 1816 */, SYSTEMZ_INS_MAYR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRD }} + + #endif +}, +{ + /* mc $BD1, $I2 */ + SystemZ_MC /* 1817 */, SYSTEMZ_INS_MC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_GRP_CALL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSI }} + + #endif +}, +{ + /* md $R1, $XBD2 */ + SystemZ_MD /* 1818 */, SYSTEMZ_INS_MD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* mdb $R1, $XBD2 */ + SystemZ_MDB /* 1819 */, SYSTEMZ_INS_MDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* mdbr $R1, $R2 */ + SystemZ_MDBR /* 1820 */, SYSTEMZ_INS_MDBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* mde $R1, $XBD2 */ + SystemZ_MDE /* 1821 */, SYSTEMZ_INS_MDE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* mdeb $R1, $XBD2 */ + SystemZ_MDEB /* 1822 */, SYSTEMZ_INS_MDEB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* mdebr $R1, $R2 */ + SystemZ_MDEBR /* 1823 */, SYSTEMZ_INS_MDEBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* mder $R1, $R2 */ + SystemZ_MDER /* 1824 */, SYSTEMZ_INS_MDER, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* mdr $R1, $R2 */ + SystemZ_MDR /* 1825 */, SYSTEMZ_INS_MDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* mdtr $R1, $R2, $R3 */ + SystemZ_MDTR /* 1826 */, SYSTEMZ_INS_MDTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* mdtra $R1, $R2, $R3, $M4 */ + SystemZ_MDTRA /* 1827 */, SYSTEMZ_INS_MDTRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* me $R1, $XBD2 */ + SystemZ_ME /* 1828 */, SYSTEMZ_INS_ME, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* mee $R1, $XBD2 */ + SystemZ_MEE /* 1829 */, SYSTEMZ_INS_MEE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* meeb $R1, $XBD2 */ + SystemZ_MEEB /* 1830 */, SYSTEMZ_INS_MEEB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* meebr $R1, $R2 */ + SystemZ_MEEBR /* 1831 */, SYSTEMZ_INS_MEEBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* meer $R1, $R2 */ + SystemZ_MEER /* 1832 */, SYSTEMZ_INS_MEER, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* mer $R1, $R2 */ + SystemZ_MER /* 1833 */, SYSTEMZ_INS_MER, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* mfy $R1, $XBD2 */ + SystemZ_MFY /* 1834 */, SYSTEMZ_INS_MFY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* mg $R1, $XBD2 */ + SystemZ_MG /* 1835 */, SYSTEMZ_INS_MG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* mgh $R1, $XBD2 */ + SystemZ_MGH /* 1836 */, SYSTEMZ_INS_MGH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* mghi $R1, $I2 */ + SystemZ_MGHI /* 1837 */, SYSTEMZ_INS_MGHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* mgrk $R1, $R2, $R3 */ + SystemZ_MGRK /* 1838 */, SYSTEMZ_INS_MGRK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* mh $R1, $XBD2 */ + SystemZ_MH /* 1839 */, SYSTEMZ_INS_MH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* mhi $R1, $I2 */ + SystemZ_MHI /* 1840 */, SYSTEMZ_INS_MHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* mhy $R1, $XBD2 */ + SystemZ_MHY /* 1841 */, SYSTEMZ_INS_MHY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* ml $R1, $XBD2 */ + SystemZ_ML /* 1842 */, SYSTEMZ_INS_ML, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* mlg $R1, $XBD2 */ + SystemZ_MLG /* 1843 */, SYSTEMZ_INS_MLG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* mlgr $R1, $R2 */ + SystemZ_MLGR /* 1844 */, SYSTEMZ_INS_MLGR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* mlr $R1, $R2 */ + SystemZ_MLR /* 1845 */, SYSTEMZ_INS_MLR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* mp $BDL1, $BDL2 */ + SystemZ_MP /* 1846 */, SYSTEMZ_INS_MP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSB }} + + #endif +}, +{ + /* mr $R1, $R2 */ + SystemZ_MR /* 1847 */, SYSTEMZ_INS_MR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* ms $R1, $XBD2 */ + SystemZ_MS /* 1848 */, SYSTEMZ_INS_MS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* msc $R1, $XBD2 */ + SystemZ_MSC /* 1849 */, SYSTEMZ_INS_MSC, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* msch $BD2 */ + SystemZ_MSCH /* 1850 */, SYSTEMZ_INS_MSCH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R1L, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* msd $R1, $R3, $XBD2 */ + SystemZ_MSD /* 1851 */, SYSTEMZ_INS_MSD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXF }} + + #endif +}, +{ + /* msdb $R1, $R3, $XBD2 */ + SystemZ_MSDB /* 1852 */, SYSTEMZ_INS_MSDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXF }} + + #endif +}, +{ + /* msdbr $R1, $R3, $R2 */ + SystemZ_MSDBR /* 1853 */, SYSTEMZ_INS_MSDBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRD }} + + #endif +}, +{ + /* msdr $R1, $R3, $R2 */ + SystemZ_MSDR /* 1854 */, SYSTEMZ_INS_MSDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRD }} + + #endif +}, +{ + /* mse $R1, $R3, $XBD2 */ + SystemZ_MSE /* 1855 */, SYSTEMZ_INS_MSE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXF }} + + #endif +}, +{ + /* mseb $R1, $R3, $XBD2 */ + SystemZ_MSEB /* 1856 */, SYSTEMZ_INS_MSEB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXF }} + + #endif +}, +{ + /* msebr $R1, $R3, $R2 */ + SystemZ_MSEBR /* 1857 */, SYSTEMZ_INS_MSEBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRD }} + + #endif +}, +{ + /* mser $R1, $R3, $R2 */ + SystemZ_MSER /* 1858 */, SYSTEMZ_INS_MSER, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRD }} + + #endif +}, +{ + /* msfi $R1, $I2 */ + SystemZ_MSFI /* 1859 */, SYSTEMZ_INS_MSFI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* msg $R1, $XBD2 */ + SystemZ_MSG /* 1860 */, SYSTEMZ_INS_MSG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* msgc $R1, $XBD2 */ + SystemZ_MSGC /* 1861 */, SYSTEMZ_INS_MSGC, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* msgf $R1, $XBD2 */ + SystemZ_MSGF /* 1862 */, SYSTEMZ_INS_MSGF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* msgfi $R1, $I2 */ + SystemZ_MSGFI /* 1863 */, SYSTEMZ_INS_MSGFI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* msgfr $R1, $R2 */ + SystemZ_MSGFR /* 1864 */, SYSTEMZ_INS_MSGFR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* msgr $R1, $R2 */ + SystemZ_MSGR /* 1865 */, SYSTEMZ_INS_MSGR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* msgrkc $R1, $R2, $R3 */ + SystemZ_MSGRKC /* 1866 */, SYSTEMZ_INS_MSGRKC, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* msr $R1, $R2 */ + SystemZ_MSR /* 1867 */, SYSTEMZ_INS_MSR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* msrkc $R1, $R2, $R3 */ + SystemZ_MSRKC /* 1868 */, SYSTEMZ_INS_MSRKC, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* msta $R1 */ + SystemZ_MSTA /* 1869 */, SYSTEMZ_INS_MSTA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* msy $R1, $XBD2 */ + SystemZ_MSY /* 1870 */, SYSTEMZ_INS_MSY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* mvc $BDL1, $BD2 */ + SystemZ_MVC /* 1871 */, SYSTEMZ_INS_MVC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSA }} + + #endif +}, +{ + /* mvcdk $BD1, $BD2 */ + SystemZ_MVCDK /* 1872 */, SYSTEMZ_INS_MVCDK, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1L, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSE }} + + #endif +}, +{ + /* mvcin $BDL1, $BD2 */ + SystemZ_MVCIN /* 1873 */, SYSTEMZ_INS_MVCIN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSA }} + + #endif +}, +{ + /* mvck $RBD1, $BD2, $R3 */ + SystemZ_MVCK /* 1874 */, SYSTEMZ_INS_MVCK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSD }} + + #endif +}, +{ + /* mvcl $R1, $R2 */ + SystemZ_MVCL /* 1875 */, SYSTEMZ_INS_MVCL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* mvcle $R1, $R3, $BD2 */ + SystemZ_MVCLE /* 1876 */, SYSTEMZ_INS_MVCLE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* mvclu $R1, $R3, $BD2 */ + SystemZ_MVCLU /* 1877 */, SYSTEMZ_INS_MVCLU, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* mvcos $BD1, $BD2, $R3 */ + SystemZ_MVCOS /* 1878 */, SYSTEMZ_INS_MVCOS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSF }} + + #endif +}, +{ + /* mvcp $RBD1, $BD2, $R3 */ + SystemZ_MVCP /* 1879 */, SYSTEMZ_INS_MVCP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSD }} + + #endif +}, +{ + /* mvcrl $BD1, $BD2 */ + SystemZ_MVCRL /* 1880 */, SYSTEMZ_INS_MVCRL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSE }} + + #endif +}, +{ + /* mvcs $RBD1, $BD2, $R3 */ + SystemZ_MVCS /* 1881 */, SYSTEMZ_INS_MVCS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSD }} + + #endif +}, +{ + /* mvcsk $BD1, $BD2 */ + SystemZ_MVCSK /* 1882 */, SYSTEMZ_INS_MVCSK, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1L, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSE }} + + #endif +}, +{ + /* mvghi $BD1, $I2 */ + SystemZ_MVGHI /* 1883 */, SYSTEMZ_INS_MVGHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIL }} + + #endif +}, +{ + /* mvhhi $BD1, $I2 */ + SystemZ_MVHHI /* 1884 */, SYSTEMZ_INS_MVHHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIL }} + + #endif +}, +{ + /* mvhi $BD1, $I2 */ + SystemZ_MVHI /* 1885 */, SYSTEMZ_INS_MVHI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIL }} + + #endif +}, +{ + /* mvi $BD1, $I2 */ + SystemZ_MVI /* 1886 */, SYSTEMZ_INS_MVI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSI }} + + #endif +}, +{ + /* mviy $BD1, $I2 */ + SystemZ_MVIY /* 1887 */, SYSTEMZ_INS_MVIY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIY }} + + #endif +}, +{ + /* mvn $BDL1, $BD2 */ + SystemZ_MVN /* 1888 */, SYSTEMZ_INS_MVN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSA }} + + #endif +}, +{ + /* mvo $BDL1, $BDL2 */ + SystemZ_MVO /* 1889 */, SYSTEMZ_INS_MVO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSB }} + + #endif +}, +{ + /* mvpg $R1, $R2 */ + SystemZ_MVPG /* 1890 */, SYSTEMZ_INS_MVPG, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* mvst $R1, $R2 */ + SystemZ_MVST /* 1891 */, SYSTEMZ_INS_MVST, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* mvz $BDL1, $BD2 */ + SystemZ_MVZ /* 1892 */, SYSTEMZ_INS_MVZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSA }} + + #endif +}, +{ + /* mxbr $R1, $R2 */ + SystemZ_MXBR /* 1893 */, SYSTEMZ_INS_MXBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* mxd $R1, $XBD2 */ + SystemZ_MXD /* 1894 */, SYSTEMZ_INS_MXD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* mxdb $R1, $XBD2 */ + SystemZ_MXDB /* 1895 */, SYSTEMZ_INS_MXDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* mxdbr $R1, $R2 */ + SystemZ_MXDBR /* 1896 */, SYSTEMZ_INS_MXDBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* mxdr $R1, $R2 */ + SystemZ_MXDR /* 1897 */, SYSTEMZ_INS_MXDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* mxr $R1, $R2 */ + SystemZ_MXR /* 1898 */, SYSTEMZ_INS_MXR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* mxtr $R1, $R2, $R3 */ + SystemZ_MXTR /* 1899 */, SYSTEMZ_INS_MXTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* mxtra $R1, $R2, $R3, $M4 */ + SystemZ_MXTRA /* 1900 */, SYSTEMZ_INS_MXTRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* my $R1, $R3, $XBD2 */ + SystemZ_MY /* 1901 */, SYSTEMZ_INS_MY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXF }} + + #endif +}, +{ + /* myh $R1, $R3, $XBD2 */ + SystemZ_MYH /* 1902 */, SYSTEMZ_INS_MYH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXF }} + + #endif +}, +{ + /* myhr $R1, $R3, $R2 */ + SystemZ_MYHR /* 1903 */, SYSTEMZ_INS_MYHR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRD }} + + #endif +}, +{ + /* myl $R1, $R3, $XBD2 */ + SystemZ_MYL /* 1904 */, SYSTEMZ_INS_MYL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXF }} + + #endif +}, +{ + /* mylr $R1, $R3, $R2 */ + SystemZ_MYLR /* 1905 */, SYSTEMZ_INS_MYLR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRD }} + + #endif +}, +{ + /* myr $R1, $R3, $R2 */ + SystemZ_MYR /* 1906 */, SYSTEMZ_INS_MYR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRD }} + + #endif +}, +{ + /* n $R1, $XBD2 */ + SystemZ_N /* 1907 */, SYSTEMZ_INS_N, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* nc $BDL1, $BD2 */ + SystemZ_NC /* 1908 */, SYSTEMZ_INS_NC, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSA }} + + #endif +}, +{ + /* ncgrk $R1, $R2, $R3 */ + SystemZ_NCGRK /* 1909 */, SYSTEMZ_INS_NCGRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* ncrk $R1, $R2, $R3 */ + SystemZ_NCRK /* 1910 */, SYSTEMZ_INS_NCRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* ng $R1, $XBD2 */ + SystemZ_NG /* 1911 */, SYSTEMZ_INS_NG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* ngr $R1, $R2 */ + SystemZ_NGR /* 1912 */, SYSTEMZ_INS_NGR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ngrk $R1, $R2, $R3 */ + SystemZ_NGRK /* 1913 */, SYSTEMZ_INS_NGRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* ni $BD1, $I2 */ + SystemZ_NI /* 1914 */, SYSTEMZ_INS_NI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSI }} + + #endif +}, +{ + /* niai $I1, $I2 */ + SystemZ_NIAI /* 1915 */, SYSTEMZ_INS_NIAI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREEXECUTIONHINT, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTIE }} + + #endif +}, +{ + /* nihf $R1, $I2 */ + SystemZ_NIHF /* 1916 */, SYSTEMZ_INS_NIHF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* nihh $R1, $I2 */ + SystemZ_NIHH /* 1917 */, SYSTEMZ_INS_NIHH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* nihl $R1, $I2 */ + SystemZ_NIHL /* 1918 */, SYSTEMZ_INS_NIHL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* nilf $R1, $I2 */ + SystemZ_NILF /* 1919 */, SYSTEMZ_INS_NILF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* nilh $R1, $I2 */ + SystemZ_NILH /* 1920 */, SYSTEMZ_INS_NILH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* nill $R1, $I2 */ + SystemZ_NILL /* 1921 */, SYSTEMZ_INS_NILL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* niy $BD1, $I2 */ + SystemZ_NIY /* 1922 */, SYSTEMZ_INS_NIY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIY }} + + #endif +}, +{ + /* nngrk $R1, $R2, $R3 */ + SystemZ_NNGRK /* 1923 */, SYSTEMZ_INS_NNGRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* nnpa */ + SystemZ_NNPA /* 1924 */, SYSTEMZ_INS_NNPA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0D, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_R0D, SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATURENNPASSIST, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* nnrk $R1, $R2, $R3 */ + SystemZ_NNRK /* 1925 */, SYSTEMZ_INS_NNRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* nogrk $R1, $R2, $R3 */ + SystemZ_NOGRK /* 1926 */, SYSTEMZ_INS_NOGRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* nop */ + SystemZ_NOP_bare /* 1927 */, SYSTEMZ_INS_NOP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXB }} + + #endif +}, +{ + /* nork $R1, $R2, $R3 */ + SystemZ_NORK /* 1928 */, SYSTEMZ_INS_NORK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* nr $R1, $R2 */ + SystemZ_NR /* 1929 */, SYSTEMZ_INS_NR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* nrk $R1, $R2, $R3 */ + SystemZ_NRK /* 1930 */, SYSTEMZ_INS_NRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* ntstg $R1, $XBD2 */ + SystemZ_NTSTG /* 1931 */, SYSTEMZ_INS_NTSTG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURETRANSACTIONALEXECUTION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* nxgrk $R1, $R2, $R3 */ + SystemZ_NXGRK /* 1932 */, SYSTEMZ_INS_NXGRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* nxrk $R1, $R2, $R3 */ + SystemZ_NXRK /* 1933 */, SYSTEMZ_INS_NXRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* ny $R1, $XBD2 */ + SystemZ_NY /* 1934 */, SYSTEMZ_INS_NY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* o $R1, $XBD2 */ + SystemZ_O /* 1935 */, SYSTEMZ_INS_O, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* oc $BDL1, $BD2 */ + SystemZ_OC /* 1936 */, SYSTEMZ_INS_OC, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSA }} + + #endif +}, +{ + /* ocgrk $R1, $R2, $R3 */ + SystemZ_OCGRK /* 1937 */, SYSTEMZ_INS_OCGRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* ocrk $R1, $R2, $R3 */ + SystemZ_OCRK /* 1938 */, SYSTEMZ_INS_OCRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* og $R1, $XBD2 */ + SystemZ_OG /* 1939 */, SYSTEMZ_INS_OG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* ogr $R1, $R2 */ + SystemZ_OGR /* 1940 */, SYSTEMZ_INS_OGR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ogrk $R1, $R2, $R3 */ + SystemZ_OGRK /* 1941 */, SYSTEMZ_INS_OGRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* oi $BD1, $I2 */ + SystemZ_OI /* 1942 */, SYSTEMZ_INS_OI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSI }} + + #endif +}, +{ + /* oihf $R1, $I2 */ + SystemZ_OIHF /* 1943 */, SYSTEMZ_INS_OIHF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* oihh $R1, $I2 */ + SystemZ_OIHH /* 1944 */, SYSTEMZ_INS_OIHH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* oihl $R1, $I2 */ + SystemZ_OIHL /* 1945 */, SYSTEMZ_INS_OIHL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* oilf $R1, $I2 */ + SystemZ_OILF /* 1946 */, SYSTEMZ_INS_OILF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* oilh $R1, $I2 */ + SystemZ_OILH /* 1947 */, SYSTEMZ_INS_OILH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* oill $R1, $I2 */ + SystemZ_OILL /* 1948 */, SYSTEMZ_INS_OILL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* oiy $BD1, $I2 */ + SystemZ_OIY /* 1949 */, SYSTEMZ_INS_OIY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIY }} + + #endif +}, +{ + /* or $R1, $R2 */ + SystemZ_OR /* 1950 */, SYSTEMZ_INS_OR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* ork $R1, $R2, $R3 */ + SystemZ_ORK /* 1951 */, SYSTEMZ_INS_ORK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* oy $R1, $XBD2 */ + SystemZ_OY /* 1952 */, SYSTEMZ_INS_OY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* pack $BDL1, $BDL2 */ + SystemZ_PACK /* 1953 */, SYSTEMZ_INS_PACK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSB }} + + #endif +}, +{ + /* palb */ + SystemZ_PALB /* 1954 */, SYSTEMZ_INS_PALB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* pc $BD2 */ + SystemZ_PC /* 1955 */, SYSTEMZ_INS_PC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* pcc */ + SystemZ_PCC /* 1956 */, SYSTEMZ_INS_PCC, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST4, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* pckmo */ + SystemZ_PCKMO /* 1957 */, SYSTEMZ_INS_PCKMO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* pfd $M1, $XBD2 */ + SystemZ_PFD /* 1958 */, SYSTEMZ_INS_PFD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYB }} + + #endif +}, +{ + /* pfdrl $M1, $RI2 */ + SystemZ_PFDRL /* 1959 */, SYSTEMZ_INS_PFDRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILC }} + + #endif +}, +{ + /* pfmf $R1, $R2 */ + SystemZ_PFMF /* 1960 */, SYSTEMZ_INS_PFMF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* pfpo */ + SystemZ_PFPO /* 1961 */, SYSTEMZ_INS_PFPO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, SYSTEMZ_REG_R0L, SYSTEMZ_REG_F4Q, 0 }, { SYSTEMZ_REG_CC, SYSTEMZ_REG_R1L, SYSTEMZ_REG_F0Q, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTE }} + + #endif +}, +{ + /* pgin $R1, $R2 */ + SystemZ_PGIN /* 1962 */, SYSTEMZ_INS_PGIN, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* pgout $R1, $R2 */ + SystemZ_PGOUT /* 1963 */, SYSTEMZ_INS_PGOUT, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* pka $BD1, $BDL2 */ + SystemZ_PKA /* 1964 */, SYSTEMZ_INS_PKA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSF }} + + #endif +}, +{ + /* pku $BD1, $BDL2 */ + SystemZ_PKU /* 1965 */, SYSTEMZ_INS_PKU, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSF }} + + #endif +}, +{ + /* plo $R1, $BD2, $R3, $BD4 */ + SystemZ_PLO /* 1966 */, SYSTEMZ_INS_PLO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSE }} + + #endif +}, +{ + /* popcnt $R1, $R2 */ + SystemZ_POPCNT /* 1967 */, SYSTEMZ_INS_POPCNT, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREPOPULATIONCOUNT, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* popcnt $R1, $R2, $M3 */ + SystemZ_POPCNTOpt /* 1968 */, SYSTEMZ_INS_POPCNT, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* ppa $R1, $R2, $M3 */ + SystemZ_PPA /* 1969 */, SYSTEMZ_INS_PPA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREPROCESSORASSIST, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* ppno $R1, $R2 */ + SystemZ_PPNO /* 1970 */, SYSTEMZ_INS_PPNO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST5, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* pr */ + SystemZ_PR /* 1971 */, SYSTEMZ_INS_PR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTE }} + + #endif +}, +{ + /* prno $R1, $R2 */ + SystemZ_PRNO /* 1972 */, SYSTEMZ_INS_PRNO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST7, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* pt $R1, $R2 */ + SystemZ_PT /* 1973 */, SYSTEMZ_INS_PT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ptf $R1 */ + SystemZ_PTF /* 1974 */, SYSTEMZ_INS_PTF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ptff */ + SystemZ_PTFF /* 1975 */, SYSTEMZ_INS_PTFF, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTE }} + + #endif +}, +{ + /* pti $R1, $R2 */ + SystemZ_PTI /* 1976 */, SYSTEMZ_INS_PTI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ptlb */ + SystemZ_PTLB /* 1977 */, SYSTEMZ_INS_PTLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* qadtr $R1, $R3, $R2, $M4 */ + SystemZ_QADTR /* 1978 */, SYSTEMZ_INS_QADTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFB }} + + #endif +}, +{ + /* qaxtr $R1, $R3, $R2, $M4 */ + SystemZ_QAXTR /* 1979 */, SYSTEMZ_INS_QAXTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFB }} + + #endif +}, +{ + /* qctri $BD2 */ + SystemZ_QCTRI /* 1980 */, SYSTEMZ_INS_QCTRI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* qpaci $BD2 */ + SystemZ_QPACI /* 1981 */, SYSTEMZ_INS_QPACI, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0D, 0 }, { SYSTEMZ_REG_R0D, SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREPROCESSORACTIVITYINSTRUMENTATION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* qsi $BD2 */ + SystemZ_QSI /* 1982 */, SYSTEMZ_INS_QSI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* rchp */ + SystemZ_RCHP /* 1983 */, SYSTEMZ_INS_RCHP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R1L, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* rdp $R1, $R3, $R2, $M4 */ + SystemZ_RDP /* 1984 */, SYSTEMZ_INS_RDP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURERESETDATPROTECTION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFB }} + + #endif +}, +{ + /* rdp $R1, $R3, $R2 */ + SystemZ_RDPOpt /* 1985 */, SYSTEMZ_INS_RDP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURERESETDATPROTECTION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFB }} + + #endif +}, +{ + /* risbg $R1, $R2, $I3, $I4, $I5 */ + SystemZ_RISBG /* 1986 */, SYSTEMZ_INS_RISBG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEF }} + + #endif +}, +{ + /* risbg $R1, $R2, $I3, $I4, $I5 */ + SystemZ_RISBG32 /* 1987 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* risbgn $R1, $R2, $I3, $I4, $I5 */ + SystemZ_RISBGN /* 1988 */, SYSTEMZ_INS_RISBGN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEF }} + + #endif +}, +{ + /* risbhg $R1, $R2, $I3, $I4, $I5 */ + SystemZ_RISBHG /* 1989 */, SYSTEMZ_INS_RISBHG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEF }} + + #endif +}, +{ + /* risblg $R1, $R2, $I3, $I4, $I5 */ + SystemZ_RISBLG /* 1990 */, SYSTEMZ_INS_RISBLG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEF }} + + #endif +}, +{ + /* rll $R1, $R3, $BD2 */ + SystemZ_RLL /* 1991 */, SYSTEMZ_INS_RLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* rllg $R1, $R3, $BD2 */ + SystemZ_RLLG /* 1992 */, SYSTEMZ_INS_RLLG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* rnsbg $R1, $R2, $I3, $I4, $I5 */ + SystemZ_RNSBG /* 1993 */, SYSTEMZ_INS_RNSBG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEF }} + + #endif +}, +{ + /* rosbg $R1, $R2, $I3, $I4, $I5 */ + SystemZ_ROSBG /* 1994 */, SYSTEMZ_INS_ROSBG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEF }} + + #endif +}, +{ + /* rp $BD2 */ + SystemZ_RP /* 1995 */, SYSTEMZ_INS_RP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* rrbe $R1, $R2 */ + SystemZ_RRBE /* 1996 */, SYSTEMZ_INS_RRBE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* rrbm $R1, $R2 */ + SystemZ_RRBM /* 1997 */, SYSTEMZ_INS_RRBM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURERESETREFERENCEBITSMULTIPLE, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* rrdtr $R1, $R3, $R2, $M4 */ + SystemZ_RRDTR /* 1998 */, SYSTEMZ_INS_RRDTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFB }} + + #endif +}, +{ + /* rrxtr $R1, $R3, $R2, $M4 */ + SystemZ_RRXTR /* 1999 */, SYSTEMZ_INS_RRXTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFB }} + + #endif +}, +{ + /* rsch */ + SystemZ_RSCH /* 2000 */, SYSTEMZ_INS_RSCH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R1L, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* rxsbg $R1, $R2, $I3, $I4, $I5 */ + SystemZ_RXSBG /* 2001 */, SYSTEMZ_INS_RXSBG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIEF }} + + #endif +}, +{ + /* s $R1, $XBD2 */ + SystemZ_S /* 2002 */, SYSTEMZ_INS_S, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* sac $BD2 */ + SystemZ_SAC /* 2003 */, SYSTEMZ_INS_SAC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* sacf $BD2 */ + SystemZ_SACF /* 2004 */, SYSTEMZ_INS_SACF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* sal */ + SystemZ_SAL /* 2005 */, SYSTEMZ_INS_SAL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R1L, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* sam24 */ + SystemZ_SAM24 /* 2006 */, SYSTEMZ_INS_SAM24, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTE }} + + #endif +}, +{ + /* sam31 */ + SystemZ_SAM31 /* 2007 */, SYSTEMZ_INS_SAM31, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTE }} + + #endif +}, +{ + /* sam64 */ + SystemZ_SAM64 /* 2008 */, SYSTEMZ_INS_SAM64, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTE }} + + #endif +}, +{ + /* sar $R1, $R2 */ + SystemZ_SAR /* 2009 */, SYSTEMZ_INS_SAR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* scctr $R1, $R2 */ + SystemZ_SCCTR /* 2010 */, SYSTEMZ_INS_SCCTR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* schm */ + SystemZ_SCHM /* 2011 */, SYSTEMZ_INS_SCHM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R1L, SYSTEMZ_REG_R2D, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* sck $BD2 */ + SystemZ_SCK /* 2012 */, SYSTEMZ_INS_SCK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* sckc $BD2 */ + SystemZ_SCKC /* 2013 */, SYSTEMZ_INS_SCKC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* sckpf */ + SystemZ_SCKPF /* 2014 */, SYSTEMZ_INS_SCKPF, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTE }} + + #endif +}, +{ + /* sd $R1, $XBD2 */ + SystemZ_SD /* 2015 */, SYSTEMZ_INS_SD, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* sdb $R1, $XBD2 */ + SystemZ_SDB /* 2016 */, SYSTEMZ_INS_SDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* sdbr $R1, $R2 */ + SystemZ_SDBR /* 2017 */, SYSTEMZ_INS_SDBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* sdr $R1, $R2 */ + SystemZ_SDR /* 2018 */, SYSTEMZ_INS_SDR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* sdtr $R1, $R2, $R3 */ + SystemZ_SDTR /* 2019 */, SYSTEMZ_INS_SDTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* sdtra $R1, $R2, $R3, $M4 */ + SystemZ_SDTRA /* 2020 */, SYSTEMZ_INS_SDTRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* se $R1, $XBD2 */ + SystemZ_SE /* 2021 */, SYSTEMZ_INS_SE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* seb $R1, $XBD2 */ + SystemZ_SEB /* 2022 */, SYSTEMZ_INS_SEB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* sebr $R1, $R2 */ + SystemZ_SEBR /* 2023 */, SYSTEMZ_INS_SEBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* selfhr$M4 $R1, $R2, $R3 */ + SystemZ_SELFHR /* 2024 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* selfhr $R1, $R2, $R3, $M4 */ + SystemZ_SELFHRAsm /* 2025 */, SYSTEMZ_INS_SELFHR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhre $R1, $R2, $R3 */ + SystemZ_SELFHRAsmE /* 2026 */, SYSTEMZ_INS_SELFHRE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhrh $R1, $R2, $R3 */ + SystemZ_SELFHRAsmH /* 2027 */, SYSTEMZ_INS_SELFHRH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhrhe $R1, $R2, $R3 */ + SystemZ_SELFHRAsmHE /* 2028 */, SYSTEMZ_INS_SELFHRHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhrl $R1, $R2, $R3 */ + SystemZ_SELFHRAsmL /* 2029 */, SYSTEMZ_INS_SELFHRL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhrle $R1, $R2, $R3 */ + SystemZ_SELFHRAsmLE /* 2030 */, SYSTEMZ_INS_SELFHRLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhrlh $R1, $R2, $R3 */ + SystemZ_SELFHRAsmLH /* 2031 */, SYSTEMZ_INS_SELFHRLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhrm $R1, $R2, $R3 */ + SystemZ_SELFHRAsmM /* 2032 */, SYSTEMZ_INS_SELFHRM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhrne $R1, $R2, $R3 */ + SystemZ_SELFHRAsmNE /* 2033 */, SYSTEMZ_INS_SELFHRNE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhrnh $R1, $R2, $R3 */ + SystemZ_SELFHRAsmNH /* 2034 */, SYSTEMZ_INS_SELFHRNH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhrnhe $R1, $R2, $R3 */ + SystemZ_SELFHRAsmNHE /* 2035 */, SYSTEMZ_INS_SELFHRNHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhrnl $R1, $R2, $R3 */ + SystemZ_SELFHRAsmNL /* 2036 */, SYSTEMZ_INS_SELFHRNL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhrnle $R1, $R2, $R3 */ + SystemZ_SELFHRAsmNLE /* 2037 */, SYSTEMZ_INS_SELFHRNLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhrnlh $R1, $R2, $R3 */ + SystemZ_SELFHRAsmNLH /* 2038 */, SYSTEMZ_INS_SELFHRNLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhrnm $R1, $R2, $R3 */ + SystemZ_SELFHRAsmNM /* 2039 */, SYSTEMZ_INS_SELFHRNM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhrno $R1, $R2, $R3 */ + SystemZ_SELFHRAsmNO /* 2040 */, SYSTEMZ_INS_SELFHRNO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhrnp $R1, $R2, $R3 */ + SystemZ_SELFHRAsmNP /* 2041 */, SYSTEMZ_INS_SELFHRNP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhrnz $R1, $R2, $R3 */ + SystemZ_SELFHRAsmNZ /* 2042 */, SYSTEMZ_INS_SELFHRNZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhro $R1, $R2, $R3 */ + SystemZ_SELFHRAsmO /* 2043 */, SYSTEMZ_INS_SELFHRO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhrp $R1, $R2, $R3 */ + SystemZ_SELFHRAsmP /* 2044 */, SYSTEMZ_INS_SELFHRP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selfhrz $R1, $R2, $R3 */ + SystemZ_SELFHRAsmZ /* 2045 */, SYSTEMZ_INS_SELFHRZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgr$M4 $R1, $R2, $R3 */ + SystemZ_SELGR /* 2046 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* selgr $R1, $R2, $R3, $M4 */ + SystemZ_SELGRAsm /* 2047 */, SYSTEMZ_INS_SELGR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgre $R1, $R2, $R3 */ + SystemZ_SELGRAsmE /* 2048 */, SYSTEMZ_INS_SELGRE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgrh $R1, $R2, $R3 */ + SystemZ_SELGRAsmH /* 2049 */, SYSTEMZ_INS_SELGRH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgrhe $R1, $R2, $R3 */ + SystemZ_SELGRAsmHE /* 2050 */, SYSTEMZ_INS_SELGRHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgrl $R1, $R2, $R3 */ + SystemZ_SELGRAsmL /* 2051 */, SYSTEMZ_INS_SELGRL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgrle $R1, $R2, $R3 */ + SystemZ_SELGRAsmLE /* 2052 */, SYSTEMZ_INS_SELGRLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgrlh $R1, $R2, $R3 */ + SystemZ_SELGRAsmLH /* 2053 */, SYSTEMZ_INS_SELGRLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgrm $R1, $R2, $R3 */ + SystemZ_SELGRAsmM /* 2054 */, SYSTEMZ_INS_SELGRM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgrne $R1, $R2, $R3 */ + SystemZ_SELGRAsmNE /* 2055 */, SYSTEMZ_INS_SELGRNE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgrnh $R1, $R2, $R3 */ + SystemZ_SELGRAsmNH /* 2056 */, SYSTEMZ_INS_SELGRNH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgrnhe $R1, $R2, $R3 */ + SystemZ_SELGRAsmNHE /* 2057 */, SYSTEMZ_INS_SELGRNHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgrnl $R1, $R2, $R3 */ + SystemZ_SELGRAsmNL /* 2058 */, SYSTEMZ_INS_SELGRNL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgrnle $R1, $R2, $R3 */ + SystemZ_SELGRAsmNLE /* 2059 */, SYSTEMZ_INS_SELGRNLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgrnlh $R1, $R2, $R3 */ + SystemZ_SELGRAsmNLH /* 2060 */, SYSTEMZ_INS_SELGRNLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgrnm $R1, $R2, $R3 */ + SystemZ_SELGRAsmNM /* 2061 */, SYSTEMZ_INS_SELGRNM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgrno $R1, $R2, $R3 */ + SystemZ_SELGRAsmNO /* 2062 */, SYSTEMZ_INS_SELGRNO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgrnp $R1, $R2, $R3 */ + SystemZ_SELGRAsmNP /* 2063 */, SYSTEMZ_INS_SELGRNP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgrnz $R1, $R2, $R3 */ + SystemZ_SELGRAsmNZ /* 2064 */, SYSTEMZ_INS_SELGRNZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgro $R1, $R2, $R3 */ + SystemZ_SELGRAsmO /* 2065 */, SYSTEMZ_INS_SELGRO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgrp $R1, $R2, $R3 */ + SystemZ_SELGRAsmP /* 2066 */, SYSTEMZ_INS_SELGRP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selgrz $R1, $R2, $R3 */ + SystemZ_SELGRAsmZ /* 2067 */, SYSTEMZ_INS_SELGRZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selr$M4 $R1, $R2, $R3 */ + SystemZ_SELR /* 2068 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* selr $R1, $R2, $R3, $M4 */ + SystemZ_SELRAsm /* 2069 */, SYSTEMZ_INS_SELR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selre $R1, $R2, $R3 */ + SystemZ_SELRAsmE /* 2070 */, SYSTEMZ_INS_SELRE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selrh $R1, $R2, $R3 */ + SystemZ_SELRAsmH /* 2071 */, SYSTEMZ_INS_SELRH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selrhe $R1, $R2, $R3 */ + SystemZ_SELRAsmHE /* 2072 */, SYSTEMZ_INS_SELRHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selrl $R1, $R2, $R3 */ + SystemZ_SELRAsmL /* 2073 */, SYSTEMZ_INS_SELRL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selrle $R1, $R2, $R3 */ + SystemZ_SELRAsmLE /* 2074 */, SYSTEMZ_INS_SELRLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selrlh $R1, $R2, $R3 */ + SystemZ_SELRAsmLH /* 2075 */, SYSTEMZ_INS_SELRLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selrm $R1, $R2, $R3 */ + SystemZ_SELRAsmM /* 2076 */, SYSTEMZ_INS_SELRM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selrne $R1, $R2, $R3 */ + SystemZ_SELRAsmNE /* 2077 */, SYSTEMZ_INS_SELRNE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selrnh $R1, $R2, $R3 */ + SystemZ_SELRAsmNH /* 2078 */, SYSTEMZ_INS_SELRNH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selrnhe $R1, $R2, $R3 */ + SystemZ_SELRAsmNHE /* 2079 */, SYSTEMZ_INS_SELRNHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selrnl $R1, $R2, $R3 */ + SystemZ_SELRAsmNL /* 2080 */, SYSTEMZ_INS_SELRNL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selrnle $R1, $R2, $R3 */ + SystemZ_SELRAsmNLE /* 2081 */, SYSTEMZ_INS_SELRNLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selrnlh $R1, $R2, $R3 */ + SystemZ_SELRAsmNLH /* 2082 */, SYSTEMZ_INS_SELRNLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selrnm $R1, $R2, $R3 */ + SystemZ_SELRAsmNM /* 2083 */, SYSTEMZ_INS_SELRNM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selrno $R1, $R2, $R3 */ + SystemZ_SELRAsmNO /* 2084 */, SYSTEMZ_INS_SELRNO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selrnp $R1, $R2, $R3 */ + SystemZ_SELRAsmNP /* 2085 */, SYSTEMZ_INS_SELRNP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selrnz $R1, $R2, $R3 */ + SystemZ_SELRAsmNZ /* 2086 */, SYSTEMZ_INS_SELRNZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selro $R1, $R2, $R3 */ + SystemZ_SELRAsmO /* 2087 */, SYSTEMZ_INS_SELRO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selrp $R1, $R2, $R3 */ + SystemZ_SELRAsmP /* 2088 */, SYSTEMZ_INS_SELRP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* selrz $R1, $R2, $R3 */ + SystemZ_SELRAsmZ /* 2089 */, SYSTEMZ_INS_SELRZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* ser $R1, $R2 */ + SystemZ_SER /* 2090 */, SYSTEMZ_INS_SER, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* sfasr $R1 */ + SystemZ_SFASR /* 2091 */, SYSTEMZ_INS_SFASR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_FPC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* sfpc $R1 */ + SystemZ_SFPC /* 2092 */, SYSTEMZ_INS_SFPC, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_FPC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* sg $R1, $XBD2 */ + SystemZ_SG /* 2093 */, SYSTEMZ_INS_SG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* sgf $R1, $XBD2 */ + SystemZ_SGF /* 2094 */, SYSTEMZ_INS_SGF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* sgfr $R1, $R2 */ + SystemZ_SGFR /* 2095 */, SYSTEMZ_INS_SGFR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* sgh $R1, $XBD2 */ + SystemZ_SGH /* 2096 */, SYSTEMZ_INS_SGH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* sgr $R1, $R2 */ + SystemZ_SGR /* 2097 */, SYSTEMZ_INS_SGR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* sgrk $R1, $R2, $R3 */ + SystemZ_SGRK /* 2098 */, SYSTEMZ_INS_SGRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* sh $R1, $XBD2 */ + SystemZ_SH /* 2099 */, SYSTEMZ_INS_SH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* shhhr $R1, $R2, $R3 */ + SystemZ_SHHHR /* 2100 */, SYSTEMZ_INS_SHHHR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* shhlr $R1, $R2, $R3 */ + SystemZ_SHHLR /* 2101 */, SYSTEMZ_INS_SHHLR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* shy $R1, $XBD2 */ + SystemZ_SHY /* 2102 */, SYSTEMZ_INS_SHY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* sie $BD2 */ + SystemZ_SIE /* 2103 */, SYSTEMZ_INS_SIE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* siga $BD2 */ + SystemZ_SIGA /* 2104 */, SYSTEMZ_INS_SIGA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0D, SYSTEMZ_REG_R1D, SYSTEMZ_REG_R2D, SYSTEMZ_REG_R3D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* sigp $R1, $R3, $BD2 */ + SystemZ_SIGP /* 2105 */, SYSTEMZ_INS_SIGP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* sl $R1, $XBD2 */ + SystemZ_SL /* 2106 */, SYSTEMZ_INS_SL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* sla $R1, $BD2 */ + SystemZ_SLA /* 2107 */, SYSTEMZ_INS_SLA, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* slag $R1, $R3, $BD2 */ + SystemZ_SLAG /* 2108 */, SYSTEMZ_INS_SLAG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* slak $R1, $R3, $BD2 */ + SystemZ_SLAK /* 2109 */, SYSTEMZ_INS_SLAK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* slb $R1, $XBD2 */ + SystemZ_SLB /* 2110 */, SYSTEMZ_INS_SLB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* slbg $R1, $XBD2 */ + SystemZ_SLBG /* 2111 */, SYSTEMZ_INS_SLBG, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* slbgr $R1, $R2 */ + SystemZ_SLBGR /* 2112 */, SYSTEMZ_INS_SLBGR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* slbr $R1, $R2 */ + SystemZ_SLBR /* 2113 */, SYSTEMZ_INS_SLBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* slda $R1, $BD2 */ + SystemZ_SLDA /* 2114 */, SYSTEMZ_INS_SLDA, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* sldl $R1, $BD2 */ + SystemZ_SLDL /* 2115 */, SYSTEMZ_INS_SLDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* sldt $R1, $R3, $XBD2 */ + SystemZ_SLDT /* 2116 */, SYSTEMZ_INS_SLDT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXF }} + + #endif +}, +{ + /* slfi $R1, $I2 */ + SystemZ_SLFI /* 2117 */, SYSTEMZ_INS_SLFI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* slg $R1, $XBD2 */ + SystemZ_SLG /* 2118 */, SYSTEMZ_INS_SLG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* slgf $R1, $XBD2 */ + SystemZ_SLGF /* 2119 */, SYSTEMZ_INS_SLGF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* slgfi $R1, $I2 */ + SystemZ_SLGFI /* 2120 */, SYSTEMZ_INS_SLGFI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* slgfr $R1, $R2 */ + SystemZ_SLGFR /* 2121 */, SYSTEMZ_INS_SLGFR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* slgr $R1, $R2 */ + SystemZ_SLGR /* 2122 */, SYSTEMZ_INS_SLGR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* slgrk $R1, $R2, $R3 */ + SystemZ_SLGRK /* 2123 */, SYSTEMZ_INS_SLGRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* slhhhr $R1, $R2, $R3 */ + SystemZ_SLHHHR /* 2124 */, SYSTEMZ_INS_SLHHHR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* slhhlr $R1, $R2, $R3 */ + SystemZ_SLHHLR /* 2125 */, SYSTEMZ_INS_SLHHLR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* sll $R1, $BD2 */ + SystemZ_SLL /* 2126 */, SYSTEMZ_INS_SLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* sllg $R1, $R3, $BD2 */ + SystemZ_SLLG /* 2127 */, SYSTEMZ_INS_SLLG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* sllk $R1, $R3, $BD2 */ + SystemZ_SLLK /* 2128 */, SYSTEMZ_INS_SLLK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* slr $R1, $R2 */ + SystemZ_SLR /* 2129 */, SYSTEMZ_INS_SLR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* slrk $R1, $R2, $R3 */ + SystemZ_SLRK /* 2130 */, SYSTEMZ_INS_SLRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* slxt $R1, $R3, $XBD2 */ + SystemZ_SLXT /* 2131 */, SYSTEMZ_INS_SLXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXF }} + + #endif +}, +{ + /* sly $R1, $XBD2 */ + SystemZ_SLY /* 2132 */, SYSTEMZ_INS_SLY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* sortl $R1, $R2 */ + SystemZ_SORTL /* 2133 */, SYSTEMZ_INS_SORTL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREENHANCEDSORT, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* sp $BDL1, $BDL2 */ + SystemZ_SP /* 2134 */, SYSTEMZ_INS_SP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSB }} + + #endif +}, +{ + /* spctr $R1, $R2 */ + SystemZ_SPCTR /* 2135 */, SYSTEMZ_INS_SPCTR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* spka $BD2 */ + SystemZ_SPKA /* 2136 */, SYSTEMZ_INS_SPKA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* spm $R1 */ + SystemZ_SPM /* 2137 */, SYSTEMZ_INS_SPM, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* spt $BD2 */ + SystemZ_SPT /* 2138 */, SYSTEMZ_INS_SPT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* spx $BD2 */ + SystemZ_SPX /* 2139 */, SYSTEMZ_INS_SPX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* sqd $R1, $XBD2 */ + SystemZ_SQD /* 2140 */, SYSTEMZ_INS_SQD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* sqdb $R1, $XBD2 */ + SystemZ_SQDB /* 2141 */, SYSTEMZ_INS_SQDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* sqdbr $R1, $R2 */ + SystemZ_SQDBR /* 2142 */, SYSTEMZ_INS_SQDBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* sqdr $R1, $R2 */ + SystemZ_SQDR /* 2143 */, SYSTEMZ_INS_SQDR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* sqe $R1, $XBD2 */ + SystemZ_SQE /* 2144 */, SYSTEMZ_INS_SQE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* sqeb $R1, $XBD2 */ + SystemZ_SQEB /* 2145 */, SYSTEMZ_INS_SQEB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* sqebr $R1, $R2 */ + SystemZ_SQEBR /* 2146 */, SYSTEMZ_INS_SQEBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* sqer $R1, $R2 */ + SystemZ_SQER /* 2147 */, SYSTEMZ_INS_SQER, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* sqxbr $R1, $R2 */ + SystemZ_SQXBR /* 2148 */, SYSTEMZ_INS_SQXBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* sqxr $R1, $R2 */ + SystemZ_SQXR /* 2149 */, SYSTEMZ_INS_SQXR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* sr $R1, $R2 */ + SystemZ_SR /* 2150 */, SYSTEMZ_INS_SR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* sra $R1, $BD2 */ + SystemZ_SRA /* 2151 */, SYSTEMZ_INS_SRA, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* srag $R1, $R3, $BD2 */ + SystemZ_SRAG /* 2152 */, SYSTEMZ_INS_SRAG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* srak $R1, $R3, $BD2 */ + SystemZ_SRAK /* 2153 */, SYSTEMZ_INS_SRAK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* srda $R1, $BD2 */ + SystemZ_SRDA /* 2154 */, SYSTEMZ_INS_SRDA, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* srdl $R1, $BD2 */ + SystemZ_SRDL /* 2155 */, SYSTEMZ_INS_SRDL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* srdt $R1, $R3, $XBD2 */ + SystemZ_SRDT /* 2156 */, SYSTEMZ_INS_SRDT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXF }} + + #endif +}, +{ + /* srk $R1, $R2, $R3 */ + SystemZ_SRK /* 2157 */, SYSTEMZ_INS_SRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* srl $R1, $BD2 */ + SystemZ_SRL /* 2158 */, SYSTEMZ_INS_SRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* srlg $R1, $R3, $BD2 */ + SystemZ_SRLG /* 2159 */, SYSTEMZ_INS_SRLG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* srlk $R1, $R3, $BD2 */ + SystemZ_SRLK /* 2160 */, SYSTEMZ_INS_SRLK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* srnm $BD2 */ + SystemZ_SRNM /* 2161 */, SYSTEMZ_INS_SRNM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_FPC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* srnmb $BD2 */ + SystemZ_SRNMB /* 2162 */, SYSTEMZ_INS_SRNMB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* srnmt $BD2 */ + SystemZ_SRNMT /* 2163 */, SYSTEMZ_INS_SRNMT, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_FPC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* srp $BDL1, $BD2, $I3 */ + SystemZ_SRP /* 2164 */, SYSTEMZ_INS_SRP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSC }} + + #endif +}, +{ + /* srst $R1, $R2 */ + SystemZ_SRST /* 2165 */, SYSTEMZ_INS_SRST, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* srstu $R1, $R2 */ + SystemZ_SRSTU /* 2166 */, SYSTEMZ_INS_SRSTU, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* srxt $R1, $R3, $XBD2 */ + SystemZ_SRXT /* 2167 */, SYSTEMZ_INS_SRXT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXF }} + + #endif +}, +{ + /* ssair $R1 */ + SystemZ_SSAIR /* 2168 */, SYSTEMZ_INS_SSAIR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ssar $R1 */ + SystemZ_SSAR /* 2169 */, SYSTEMZ_INS_SSAR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* ssch $BD2 */ + SystemZ_SSCH /* 2170 */, SYSTEMZ_INS_SSCH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R1L, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* sske $R1, $R2, $M3 */ + SystemZ_SSKE /* 2171 */, SYSTEMZ_INS_SSKE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* sske $R1, $R2 */ + SystemZ_SSKEOpt /* 2172 */, SYSTEMZ_INS_SSKE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* ssm $BD2 */ + SystemZ_SSM /* 2173 */, SYSTEMZ_INS_SSM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* st $R1, $XBD2 */ + SystemZ_ST /* 2174 */, SYSTEMZ_INS_ST, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* stam $R1, $R3, $BD2 */ + SystemZ_STAM /* 2175 */, SYSTEMZ_INS_STAM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* stamy $R1, $R3, $BD2 */ + SystemZ_STAMY /* 2176 */, SYSTEMZ_INS_STAMY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* stap $BD2 */ + SystemZ_STAP /* 2177 */, SYSTEMZ_INS_STAP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* stbear $BD2 */ + SystemZ_STBEAR /* 2178 */, SYSTEMZ_INS_STBEAR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREBEARENHANCEMENT, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* stc $R1, $XBD2 */ + SystemZ_STC /* 2179 */, SYSTEMZ_INS_STC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* stch $R1, $XBD2 */ + SystemZ_STCH /* 2180 */, SYSTEMZ_INS_STCH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* stck $BD2 */ + SystemZ_STCK /* 2181 */, SYSTEMZ_INS_STCK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* stckc $BD2 */ + SystemZ_STCKC /* 2182 */, SYSTEMZ_INS_STCKC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* stcke $BD2 */ + SystemZ_STCKE /* 2183 */, SYSTEMZ_INS_STCKE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* stckf $BD2 */ + SystemZ_STCKF /* 2184 */, SYSTEMZ_INS_STCKF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* stcm $R1, $M3, $BD2 */ + SystemZ_STCM /* 2185 */, SYSTEMZ_INS_STCM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSB }} + + #endif +}, +{ + /* stcmh $R1, $M3, $BD2 */ + SystemZ_STCMH /* 2186 */, SYSTEMZ_INS_STCMH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stcmy $R1, $M3, $BD2 */ + SystemZ_STCMY /* 2187 */, SYSTEMZ_INS_STCMY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stcps $BD2 */ + SystemZ_STCPS /* 2188 */, SYSTEMZ_INS_STCPS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* stcrw $BD2 */ + SystemZ_STCRW /* 2189 */, SYSTEMZ_INS_STCRW, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* stctg $R1, $R3, $BD2 */ + SystemZ_STCTG /* 2190 */, SYSTEMZ_INS_STCTG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* stctl $R1, $R3, $BD2 */ + SystemZ_STCTL /* 2191 */, SYSTEMZ_INS_STCTL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* stcy $R1, $XBD2 */ + SystemZ_STCY /* 2192 */, SYSTEMZ_INS_STCY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* std $R1, $XBD2 */ + SystemZ_STD /* 2193 */, SYSTEMZ_INS_STD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* stdy $R1, $XBD2 */ + SystemZ_STDY /* 2194 */, SYSTEMZ_INS_STDY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* ste $R1, $XBD2 */ + SystemZ_STE /* 2195 */, SYSTEMZ_INS_STE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* stey $R1, $XBD2 */ + SystemZ_STEY /* 2196 */, SYSTEMZ_INS_STEY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* stfh $R1, $XBD2 */ + SystemZ_STFH /* 2197 */, SYSTEMZ_INS_STFH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* stfl $BD2 */ + SystemZ_STFL /* 2198 */, SYSTEMZ_INS_STFL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* stfle $BD2 */ + SystemZ_STFLE /* 2199 */, SYSTEMZ_INS_STFLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0D, 0 }, { SYSTEMZ_REG_R0D, SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* stfpc $BD2 */ + SystemZ_STFPC /* 2200 */, SYSTEMZ_INS_STFPC, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* stg $R1, $XBD2 */ + SystemZ_STG /* 2201 */, SYSTEMZ_INS_STG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* stgrl $R1, $RI2 */ + SystemZ_STGRL /* 2202 */, SYSTEMZ_INS_STGRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* stgsc $R1, $XBD2 */ + SystemZ_STGSC /* 2203 */, SYSTEMZ_INS_STGSC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREGUARDEDSTORAGE, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* sth $R1, $XBD2 */ + SystemZ_STH /* 2204 */, SYSTEMZ_INS_STH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* sthh $R1, $XBD2 */ + SystemZ_STHH /* 2205 */, SYSTEMZ_INS_STHH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREHIGHWORD, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* sthrl $R1, $RI2 */ + SystemZ_STHRL /* 2206 */, SYSTEMZ_INS_STHRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* sthy $R1, $XBD2 */ + SystemZ_STHY /* 2207 */, SYSTEMZ_INS_STHY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* stidp $BD2 */ + SystemZ_STIDP /* 2208 */, SYSTEMZ_INS_STIDP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* stm $R1, $R3, $BD2 */ + SystemZ_STM /* 2209 */, SYSTEMZ_INS_STM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* stmg $R1, $R3, $BD2 */ + SystemZ_STMG /* 2210 */, SYSTEMZ_INS_STMG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* stmh $R1, $R3, $BD2 */ + SystemZ_STMH /* 2211 */, SYSTEMZ_INS_STMH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* stmy $R1, $R3, $BD2 */ + SystemZ_STMY /* 2212 */, SYSTEMZ_INS_STMY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* stnsm $BD1, $I2 */ + SystemZ_STNSM /* 2213 */, SYSTEMZ_INS_STNSM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSI }} + + #endif +}, +{ + /* stoc$M3 $R1, $BD2 */ + SystemZ_STOC /* 2214 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* stoc $R1, $BD2, $M3 */ + SystemZ_STOCAsm /* 2215 */, SYSTEMZ_INS_STOC, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stoce $R1, $BD2 */ + SystemZ_STOCAsmE /* 2216 */, SYSTEMZ_INS_STOCE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stoch $R1, $BD2 */ + SystemZ_STOCAsmH /* 2217 */, SYSTEMZ_INS_STOCH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stoche $R1, $BD2 */ + SystemZ_STOCAsmHE /* 2218 */, SYSTEMZ_INS_STOCHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocl $R1, $BD2 */ + SystemZ_STOCAsmL /* 2219 */, SYSTEMZ_INS_STOCL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocle $R1, $BD2 */ + SystemZ_STOCAsmLE /* 2220 */, SYSTEMZ_INS_STOCLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stoclh $R1, $BD2 */ + SystemZ_STOCAsmLH /* 2221 */, SYSTEMZ_INS_STOCLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocm $R1, $BD2 */ + SystemZ_STOCAsmM /* 2222 */, SYSTEMZ_INS_STOCM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocne $R1, $BD2 */ + SystemZ_STOCAsmNE /* 2223 */, SYSTEMZ_INS_STOCNE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocnh $R1, $BD2 */ + SystemZ_STOCAsmNH /* 2224 */, SYSTEMZ_INS_STOCNH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocnhe $R1, $BD2 */ + SystemZ_STOCAsmNHE /* 2225 */, SYSTEMZ_INS_STOCNHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocnl $R1, $BD2 */ + SystemZ_STOCAsmNL /* 2226 */, SYSTEMZ_INS_STOCNL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocnle $R1, $BD2 */ + SystemZ_STOCAsmNLE /* 2227 */, SYSTEMZ_INS_STOCNLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocnlh $R1, $BD2 */ + SystemZ_STOCAsmNLH /* 2228 */, SYSTEMZ_INS_STOCNLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocnm $R1, $BD2 */ + SystemZ_STOCAsmNM /* 2229 */, SYSTEMZ_INS_STOCNM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocno $R1, $BD2 */ + SystemZ_STOCAsmNO /* 2230 */, SYSTEMZ_INS_STOCNO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocnp $R1, $BD2 */ + SystemZ_STOCAsmNP /* 2231 */, SYSTEMZ_INS_STOCNP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocnz $R1, $BD2 */ + SystemZ_STOCAsmNZ /* 2232 */, SYSTEMZ_INS_STOCNZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stoco $R1, $BD2 */ + SystemZ_STOCAsmO /* 2233 */, SYSTEMZ_INS_STOCO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocp $R1, $BD2 */ + SystemZ_STOCAsmP /* 2234 */, SYSTEMZ_INS_STOCP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocz $R1, $BD2 */ + SystemZ_STOCAsmZ /* 2235 */, SYSTEMZ_INS_STOCZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfh$M3 $R1, $BD2 */ + SystemZ_STOCFH /* 2236 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* stocfh $R1, $BD2, $M3 */ + SystemZ_STOCFHAsm /* 2237 */, SYSTEMZ_INS_STOCFH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfhe $R1, $BD2 */ + SystemZ_STOCFHAsmE /* 2238 */, SYSTEMZ_INS_STOCFHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfhh $R1, $BD2 */ + SystemZ_STOCFHAsmH /* 2239 */, SYSTEMZ_INS_STOCFHH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfhhe $R1, $BD2 */ + SystemZ_STOCFHAsmHE /* 2240 */, SYSTEMZ_INS_STOCFHHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfhl $R1, $BD2 */ + SystemZ_STOCFHAsmL /* 2241 */, SYSTEMZ_INS_STOCFHL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfhle $R1, $BD2 */ + SystemZ_STOCFHAsmLE /* 2242 */, SYSTEMZ_INS_STOCFHLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfhlh $R1, $BD2 */ + SystemZ_STOCFHAsmLH /* 2243 */, SYSTEMZ_INS_STOCFHLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfhm $R1, $BD2 */ + SystemZ_STOCFHAsmM /* 2244 */, SYSTEMZ_INS_STOCFHM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfhne $R1, $BD2 */ + SystemZ_STOCFHAsmNE /* 2245 */, SYSTEMZ_INS_STOCFHNE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfhnh $R1, $BD2 */ + SystemZ_STOCFHAsmNH /* 2246 */, SYSTEMZ_INS_STOCFHNH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfhnhe $R1, $BD2 */ + SystemZ_STOCFHAsmNHE /* 2247 */, SYSTEMZ_INS_STOCFHNHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfhnl $R1, $BD2 */ + SystemZ_STOCFHAsmNL /* 2248 */, SYSTEMZ_INS_STOCFHNL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfhnle $R1, $BD2 */ + SystemZ_STOCFHAsmNLE /* 2249 */, SYSTEMZ_INS_STOCFHNLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfhnlh $R1, $BD2 */ + SystemZ_STOCFHAsmNLH /* 2250 */, SYSTEMZ_INS_STOCFHNLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfhnm $R1, $BD2 */ + SystemZ_STOCFHAsmNM /* 2251 */, SYSTEMZ_INS_STOCFHNM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfhno $R1, $BD2 */ + SystemZ_STOCFHAsmNO /* 2252 */, SYSTEMZ_INS_STOCFHNO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfhnp $R1, $BD2 */ + SystemZ_STOCFHAsmNP /* 2253 */, SYSTEMZ_INS_STOCFHNP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfhnz $R1, $BD2 */ + SystemZ_STOCFHAsmNZ /* 2254 */, SYSTEMZ_INS_STOCFHNZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfho $R1, $BD2 */ + SystemZ_STOCFHAsmO /* 2255 */, SYSTEMZ_INS_STOCFHO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfhp $R1, $BD2 */ + SystemZ_STOCFHAsmP /* 2256 */, SYSTEMZ_INS_STOCFHP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocfhz $R1, $BD2 */ + SystemZ_STOCFHAsmZ /* 2257 */, SYSTEMZ_INS_STOCFHZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocg$M3 $R1, $BD2 */ + SystemZ_STOCG /* 2258 */, SYSTEMZ_INS_INVALID, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }} + #endif +}, +{ + /* stocg $R1, $BD2, $M3 */ + SystemZ_STOCGAsm /* 2259 */, SYSTEMZ_INS_STOCG, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocge $R1, $BD2 */ + SystemZ_STOCGAsmE /* 2260 */, SYSTEMZ_INS_STOCGE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocgh $R1, $BD2 */ + SystemZ_STOCGAsmH /* 2261 */, SYSTEMZ_INS_STOCGH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocghe $R1, $BD2 */ + SystemZ_STOCGAsmHE /* 2262 */, SYSTEMZ_INS_STOCGHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocgl $R1, $BD2 */ + SystemZ_STOCGAsmL /* 2263 */, SYSTEMZ_INS_STOCGL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocgle $R1, $BD2 */ + SystemZ_STOCGAsmLE /* 2264 */, SYSTEMZ_INS_STOCGLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocglh $R1, $BD2 */ + SystemZ_STOCGAsmLH /* 2265 */, SYSTEMZ_INS_STOCGLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocgm $R1, $BD2 */ + SystemZ_STOCGAsmM /* 2266 */, SYSTEMZ_INS_STOCGM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocgne $R1, $BD2 */ + SystemZ_STOCGAsmNE /* 2267 */, SYSTEMZ_INS_STOCGNE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocgnh $R1, $BD2 */ + SystemZ_STOCGAsmNH /* 2268 */, SYSTEMZ_INS_STOCGNH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocgnhe $R1, $BD2 */ + SystemZ_STOCGAsmNHE /* 2269 */, SYSTEMZ_INS_STOCGNHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocgnl $R1, $BD2 */ + SystemZ_STOCGAsmNL /* 2270 */, SYSTEMZ_INS_STOCGNL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocgnle $R1, $BD2 */ + SystemZ_STOCGAsmNLE /* 2271 */, SYSTEMZ_INS_STOCGNLE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocgnlh $R1, $BD2 */ + SystemZ_STOCGAsmNLH /* 2272 */, SYSTEMZ_INS_STOCGNLH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocgnm $R1, $BD2 */ + SystemZ_STOCGAsmNM /* 2273 */, SYSTEMZ_INS_STOCGNM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocgno $R1, $BD2 */ + SystemZ_STOCGAsmNO /* 2274 */, SYSTEMZ_INS_STOCGNO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocgnp $R1, $BD2 */ + SystemZ_STOCGAsmNP /* 2275 */, SYSTEMZ_INS_STOCGNP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocgnz $R1, $BD2 */ + SystemZ_STOCGAsmNZ /* 2276 */, SYSTEMZ_INS_STOCGNZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocgo $R1, $BD2 */ + SystemZ_STOCGAsmO /* 2277 */, SYSTEMZ_INS_STOCGO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocgp $R1, $BD2 */ + SystemZ_STOCGAsmP /* 2278 */, SYSTEMZ_INS_STOCGP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stocgz $R1, $BD2 */ + SystemZ_STOCGAsmZ /* 2279 */, SYSTEMZ_INS_STOCGZ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_CC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYB }} + + #endif +}, +{ + /* stosm $BD1, $I2 */ + SystemZ_STOSM /* 2280 */, SYSTEMZ_INS_STOSM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSI }} + + #endif +}, +{ + /* stpq $R1, $XBD2 */ + SystemZ_STPQ /* 2281 */, SYSTEMZ_INS_STPQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* stpt $BD2 */ + SystemZ_STPT /* 2282 */, SYSTEMZ_INS_STPT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* stpx $BD2 */ + SystemZ_STPX /* 2283 */, SYSTEMZ_INS_STPX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* strag $BD1, $BD2 */ + SystemZ_STRAG /* 2284 */, SYSTEMZ_INS_STRAG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSE }} + + #endif +}, +{ + /* strl $R1, $RI2 */ + SystemZ_STRL /* 2285 */, SYSTEMZ_INS_STRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILB }} + + #endif +}, +{ + /* strv $R1, $XBD2 */ + SystemZ_STRV /* 2286 */, SYSTEMZ_INS_STRV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* strvg $R1, $XBD2 */ + SystemZ_STRVG /* 2287 */, SYSTEMZ_INS_STRVG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* strvh $R1, $XBD2 */ + SystemZ_STRVH /* 2288 */, SYSTEMZ_INS_STRVH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* stsch $BD2 */ + SystemZ_STSCH /* 2289 */, SYSTEMZ_INS_STSCH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R1L, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* stsi $BD2 */ + SystemZ_STSI /* 2290 */, SYSTEMZ_INS_STSI, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1L, 0 }, { SYSTEMZ_REG_R0L, SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* stura $R1, $R2 */ + SystemZ_STURA /* 2291 */, SYSTEMZ_INS_STURA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* sturg $R1, $R2 */ + SystemZ_STURG /* 2292 */, SYSTEMZ_INS_STURG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* sty $R1, $XBD2 */ + SystemZ_STY /* 2293 */, SYSTEMZ_INS_STY, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* su $R1, $XBD2 */ + SystemZ_SU /* 2294 */, SYSTEMZ_INS_SU, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* sur $R1, $R2 */ + SystemZ_SUR /* 2295 */, SYSTEMZ_INS_SUR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* svc $I1 */ + SystemZ_SVC /* 2296 */, SYSTEMZ_INS_SVC, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_GRP_CALL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTI }} + + #endif +}, +{ + /* sw $R1, $XBD2 */ + SystemZ_SW /* 2297 */, SYSTEMZ_INS_SW, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* swr $R1, $R2 */ + SystemZ_SWR /* 2298 */, SYSTEMZ_INS_SWR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* sxbr $R1, $R2 */ + SystemZ_SXBR /* 2299 */, SYSTEMZ_INS_SXBR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* sxr $R1, $R2 */ + SystemZ_SXR /* 2300 */, SYSTEMZ_INS_SXR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* sxtr $R1, $R2, $R3 */ + SystemZ_SXTR /* 2301 */, SYSTEMZ_INS_SXTR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* sxtra $R1, $R2, $R3, $M4 */ + SystemZ_SXTRA /* 2302 */, SYSTEMZ_INS_SXTRA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREFPEXTENSION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* sy $R1, $XBD2 */ + SystemZ_SY /* 2303 */, SYSTEMZ_INS_SY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* tabort $BD2 */ + SystemZ_TABORT /* 2304 */, SYSTEMZ_INS_TABORT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATURETRANSACTIONALEXECUTION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* tam */ + SystemZ_TAM /* 2305 */, SYSTEMZ_INS_TAM, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTE }} + + #endif +}, +{ + /* tar $R1, $R2 */ + SystemZ_TAR /* 2306 */, SYSTEMZ_INS_TAR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* tb $R1, $R2 */ + SystemZ_TB /* 2307 */, SYSTEMZ_INS_TB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0D, 0 }, { SYSTEMZ_REG_R0D, SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* tbdr $R1, $M3, $R2 */ + SystemZ_TBDR /* 2308 */, SYSTEMZ_INS_TBDR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* tbedr $R1, $M3, $R2 */ + SystemZ_TBEDR /* 2309 */, SYSTEMZ_INS_TBEDR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFE }} + + #endif +}, +{ + /* tbegin $BD1, $I2 */ + SystemZ_TBEGIN /* 2310 */, SYSTEMZ_INS_TBEGIN, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATURETRANSACTIONALEXECUTION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIL }} + + #endif +}, +{ + /* tbeginc $BD1, $I2 */ + SystemZ_TBEGINC /* 2311 */, SYSTEMZ_INS_TBEGINC, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATURETRANSACTIONALEXECUTION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIL }} + + #endif +}, +{ + /* tcdb $R1, $XBD2 */ + SystemZ_TCDB /* 2312 */, SYSTEMZ_INS_TCDB, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* tceb $R1, $XBD2 */ + SystemZ_TCEB /* 2313 */, SYSTEMZ_INS_TCEB, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* tcxb $R1, $XBD2 */ + SystemZ_TCXB /* 2314 */, SYSTEMZ_INS_TCXB, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* tdcdt $R1, $XBD2 */ + SystemZ_TDCDT /* 2315 */, SYSTEMZ_INS_TDCDT, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* tdcet $R1, $XBD2 */ + SystemZ_TDCET /* 2316 */, SYSTEMZ_INS_TDCET, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* tdcxt $R1, $XBD2 */ + SystemZ_TDCXT /* 2317 */, SYSTEMZ_INS_TDCXT, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* tdgdt $R1, $XBD2 */ + SystemZ_TDGDT /* 2318 */, SYSTEMZ_INS_TDGDT, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* tdget $R1, $XBD2 */ + SystemZ_TDGET /* 2319 */, SYSTEMZ_INS_TDGET, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* tdgxt $R1, $XBD2 */ + SystemZ_TDGXT /* 2320 */, SYSTEMZ_INS_TDGXT, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXE }} + + #endif +}, +{ + /* tend */ + SystemZ_TEND /* 2321 */, SYSTEMZ_INS_TEND, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATURETRANSACTIONALEXECUTION, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* thder $R1, $R2 */ + SystemZ_THDER /* 2322 */, SYSTEMZ_INS_THDER, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* thdr $R1, $R2 */ + SystemZ_THDR /* 2323 */, SYSTEMZ_INS_THDR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* tm $BD1, $I2 */ + SystemZ_TM /* 2324 */, SYSTEMZ_INS_TM, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSI }} + + #endif +}, +{ + /* tmhh $R1, $I2 */ + SystemZ_TMHH /* 2325 */, SYSTEMZ_INS_TMHH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* tmhl $R1, $I2 */ + SystemZ_TMHL /* 2326 */, SYSTEMZ_INS_TMHL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* tmlh $R1, $I2 */ + SystemZ_TMLH /* 2327 */, SYSTEMZ_INS_TMLH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* tmll $R1, $I2 */ + SystemZ_TMLL /* 2328 */, SYSTEMZ_INS_TMLL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRIA }} + + #endif +}, +{ + /* tmy $BD1, $I2 */ + SystemZ_TMY /* 2329 */, SYSTEMZ_INS_TMY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIY }} + + #endif +}, +{ + /* tp $BDL1 */ + SystemZ_TP /* 2330 */, SYSTEMZ_INS_TP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSLA }} + + #endif +}, +{ + /* tpi $BD2 */ + SystemZ_TPI /* 2331 */, SYSTEMZ_INS_TPI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* tprot $BD1, $BD2 */ + SystemZ_TPROT /* 2332 */, SYSTEMZ_INS_TPROT, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSE }} + + #endif +}, +{ + /* tr $BDL1, $BD2 */ + SystemZ_TR /* 2333 */, SYSTEMZ_INS_TR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSA }} + + #endif +}, +{ + /* trace $R1, $R3, $BD2 */ + SystemZ_TRACE /* 2334 */, SYSTEMZ_INS_TRACE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSA }} + + #endif +}, +{ + /* tracg $R1, $R3, $BD2 */ + SystemZ_TRACG /* 2335 */, SYSTEMZ_INS_TRACG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRSYA }} + + #endif +}, +{ + /* trap2 */ + SystemZ_TRAP2 /* 2336 */, SYSTEMZ_INS_TRAP2, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTE }} + + #endif +}, +{ + /* trap4 $BD2 */ + SystemZ_TRAP4 /* 2337 */, SYSTEMZ_INS_TRAP4, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* tre $R1, $R2 */ + SystemZ_TRE /* 2338 */, SYSTEMZ_INS_TRE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* troo $R1, $R2, $M3 */ + SystemZ_TROO /* 2339 */, SYSTEMZ_INS_TROO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* troo $R1, $R2 */ + SystemZ_TROOOpt /* 2340 */, SYSTEMZ_INS_TROO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* trot $R1, $R2, $M3 */ + SystemZ_TROT /* 2341 */, SYSTEMZ_INS_TROT, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* trot $R1, $R2 */ + SystemZ_TROTOpt /* 2342 */, SYSTEMZ_INS_TROT, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* trt $BDL1, $BD2 */ + SystemZ_TRT /* 2343 */, SYSTEMZ_INS_TRT, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSA }} + + #endif +}, +{ + /* trte $R1, $R2, $M3 */ + SystemZ_TRTE /* 2344 */, SYSTEMZ_INS_TRTE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* trte $R1, $R2 */ + SystemZ_TRTEOpt /* 2345 */, SYSTEMZ_INS_TRTE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* trto $R1, $R2, $M3 */ + SystemZ_TRTO /* 2346 */, SYSTEMZ_INS_TRTO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* trto $R1, $R2 */ + SystemZ_TRTOOpt /* 2347 */, SYSTEMZ_INS_TRTO, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* trtr $BDL1, $BD2 */ + SystemZ_TRTR /* 2348 */, SYSTEMZ_INS_TRTR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSA }} + + #endif +}, +{ + /* trtre $R1, $R2, $M3 */ + SystemZ_TRTRE /* 2349 */, SYSTEMZ_INS_TRTRE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* trtre $R1, $R2 */ + SystemZ_TRTREOpt /* 2350 */, SYSTEMZ_INS_TRTRE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* trtt $R1, $R2, $M3 */ + SystemZ_TRTT /* 2351 */, SYSTEMZ_INS_TRTT, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* trtt $R1, $R2 */ + SystemZ_TRTTOpt /* 2352 */, SYSTEMZ_INS_TRTT, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0L, SYSTEMZ_REG_R1D, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFC }} + + #endif +}, +{ + /* ts $BD2 */ + SystemZ_TS /* 2353 */, SYSTEMZ_INS_TS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* tsch $BD2 */ + SystemZ_TSCH /* 2354 */, SYSTEMZ_INS_TSCH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R1L, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* unpk $BDL1, $BDL2 */ + SystemZ_UNPK /* 2355 */, SYSTEMZ_INS_UNPK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSB }} + + #endif +}, +{ + /* unpka $BDL1, $BD2 */ + SystemZ_UNPKA /* 2356 */, SYSTEMZ_INS_UNPKA, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSA }} + + #endif +}, +{ + /* unpku $BDL1, $BD2 */ + SystemZ_UNPKU /* 2357 */, SYSTEMZ_INS_UNPKU, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSA }} + + #endif +}, +{ + /* upt */ + SystemZ_UPT /* 2358 */, SYSTEMZ_INS_UPT, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R0D, SYSTEMZ_REG_R1D, SYSTEMZ_REG_R2D, SYSTEMZ_REG_R3D, SYSTEMZ_REG_R4D, SYSTEMZ_REG_R5D, 0 }, { SYSTEMZ_REG_CC, SYSTEMZ_REG_R0D, SYSTEMZ_REG_R1D, SYSTEMZ_REG_R2D, SYSTEMZ_REG_R3D, SYSTEMZ_REG_R5D, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTE }} + + #endif +}, +{ + /* va $V1, $V2, $V3, $M4 */ + SystemZ_VA /* 2359 */, SYSTEMZ_INS_VA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vab $V1, $V2, $V3 */ + SystemZ_VAB /* 2360 */, SYSTEMZ_INS_VAB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vac $V1, $V2, $V3, $V4, $M5 */ + SystemZ_VAC /* 2361 */, SYSTEMZ_INS_VAC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vacc $V1, $V2, $V3, $M4 */ + SystemZ_VACC /* 2362 */, SYSTEMZ_INS_VACC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vaccb $V1, $V2, $V3 */ + SystemZ_VACCB /* 2363 */, SYSTEMZ_INS_VACCB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vaccc $V1, $V2, $V3, $V4, $M5 */ + SystemZ_VACCC /* 2364 */, SYSTEMZ_INS_VACCC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vacccq $V1, $V2, $V3, $V4 */ + SystemZ_VACCCQ /* 2365 */, SYSTEMZ_INS_VACCCQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vaccf $V1, $V2, $V3 */ + SystemZ_VACCF /* 2366 */, SYSTEMZ_INS_VACCF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vaccg $V1, $V2, $V3 */ + SystemZ_VACCG /* 2367 */, SYSTEMZ_INS_VACCG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vacch $V1, $V2, $V3 */ + SystemZ_VACCH /* 2368 */, SYSTEMZ_INS_VACCH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vaccq $V1, $V2, $V3 */ + SystemZ_VACCQ /* 2369 */, SYSTEMZ_INS_VACCQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vacq $V1, $V2, $V3, $V4 */ + SystemZ_VACQ /* 2370 */, SYSTEMZ_INS_VACQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vaf $V1, $V2, $V3 */ + SystemZ_VAF /* 2371 */, SYSTEMZ_INS_VAF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vag $V1, $V2, $V3 */ + SystemZ_VAG /* 2372 */, SYSTEMZ_INS_VAG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vah $V1, $V2, $V3 */ + SystemZ_VAH /* 2373 */, SYSTEMZ_INS_VAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vap $V1, $V2, $V3, $I4, $M5 */ + SystemZ_VAP /* 2374 */, SYSTEMZ_INS_VAP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIF }} + + #endif +}, +{ + /* vaq $V1, $V2, $V3 */ + SystemZ_VAQ /* 2375 */, SYSTEMZ_INS_VAQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vavg $V1, $V2, $V3, $M4 */ + SystemZ_VAVG /* 2376 */, SYSTEMZ_INS_VAVG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vavgb $V1, $V2, $V3 */ + SystemZ_VAVGB /* 2377 */, SYSTEMZ_INS_VAVGB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vavgf $V1, $V2, $V3 */ + SystemZ_VAVGF /* 2378 */, SYSTEMZ_INS_VAVGF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vavgg $V1, $V2, $V3 */ + SystemZ_VAVGG /* 2379 */, SYSTEMZ_INS_VAVGG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vavgh $V1, $V2, $V3 */ + SystemZ_VAVGH /* 2380 */, SYSTEMZ_INS_VAVGH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vavgl $V1, $V2, $V3, $M4 */ + SystemZ_VAVGL /* 2381 */, SYSTEMZ_INS_VAVGL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vavglb $V1, $V2, $V3 */ + SystemZ_VAVGLB /* 2382 */, SYSTEMZ_INS_VAVGLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vavglf $V1, $V2, $V3 */ + SystemZ_VAVGLF /* 2383 */, SYSTEMZ_INS_VAVGLF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vavglg $V1, $V2, $V3 */ + SystemZ_VAVGLG /* 2384 */, SYSTEMZ_INS_VAVGLG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vavglh $V1, $V2, $V3 */ + SystemZ_VAVGLH /* 2385 */, SYSTEMZ_INS_VAVGLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vbperm $V1, $V2, $V3 */ + SystemZ_VBPERM /* 2386 */, SYSTEMZ_INS_VBPERM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vcdg $V1, $V2, $M3, $M4, $M5 */ + SystemZ_VCDG /* 2387 */, SYSTEMZ_INS_VCDG, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vcdgb $V1, $V2, $M4, $M5 */ + SystemZ_VCDGB /* 2388 */, SYSTEMZ_INS_VCDGB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vcdlg $V1, $V2, $M3, $M4, $M5 */ + SystemZ_VCDLG /* 2389 */, SYSTEMZ_INS_VCDLG, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vcdlgb $V1, $V2, $M4, $M5 */ + SystemZ_VCDLGB /* 2390 */, SYSTEMZ_INS_VCDLGB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vcefb $V1, $V2, $M4, $M5 */ + SystemZ_VCEFB /* 2391 */, SYSTEMZ_INS_VCEFB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vcelfb $V1, $V2, $M4, $M5 */ + SystemZ_VCELFB /* 2392 */, SYSTEMZ_INS_VCELFB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vceq $V1, $V2, $V3, $M4, $M5 */ + SystemZ_VCEQ /* 2393 */, SYSTEMZ_INS_VCEQ, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vceqb $V1, $V2, $V3 */ + SystemZ_VCEQB /* 2394 */, SYSTEMZ_INS_VCEQB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vceqbs $V1, $V2, $V3 */ + SystemZ_VCEQBS /* 2395 */, SYSTEMZ_INS_VCEQBS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vceqf $V1, $V2, $V3 */ + SystemZ_VCEQF /* 2396 */, SYSTEMZ_INS_VCEQF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vceqfs $V1, $V2, $V3 */ + SystemZ_VCEQFS /* 2397 */, SYSTEMZ_INS_VCEQFS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vceqg $V1, $V2, $V3 */ + SystemZ_VCEQG /* 2398 */, SYSTEMZ_INS_VCEQG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vceqgs $V1, $V2, $V3 */ + SystemZ_VCEQGS /* 2399 */, SYSTEMZ_INS_VCEQGS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vceqh $V1, $V2, $V3 */ + SystemZ_VCEQH /* 2400 */, SYSTEMZ_INS_VCEQH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vceqhs $V1, $V2, $V3 */ + SystemZ_VCEQHS /* 2401 */, SYSTEMZ_INS_VCEQHS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vcfeb $V1, $V2, $M4, $M5 */ + SystemZ_VCFEB /* 2402 */, SYSTEMZ_INS_VCFEB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vcfn $V1, $V2, $M3, $M4 */ + SystemZ_VCFN /* 2403 */, SYSTEMZ_INS_VCFN, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, SYSTEMZ_FEATURE_FEATURENNPASSIST, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vcfpl $V1, $V2, $M3, $M4, $M5 */ + SystemZ_VCFPL /* 2404 */, SYSTEMZ_INS_VCFPL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vcfps $V1, $V2, $M3, $M4, $M5 */ + SystemZ_VCFPS /* 2405 */, SYSTEMZ_INS_VCFPS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vcgd $V1, $V2, $M3, $M4, $M5 */ + SystemZ_VCGD /* 2406 */, SYSTEMZ_INS_VCGD, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vcgdb $V1, $V2, $M4, $M5 */ + SystemZ_VCGDB /* 2407 */, SYSTEMZ_INS_VCGDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vch $V1, $V2, $V3, $M4, $M5 */ + SystemZ_VCH /* 2408 */, SYSTEMZ_INS_VCH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vchb $V1, $V2, $V3 */ + SystemZ_VCHB /* 2409 */, SYSTEMZ_INS_VCHB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vchbs $V1, $V2, $V3 */ + SystemZ_VCHBS /* 2410 */, SYSTEMZ_INS_VCHBS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vchf $V1, $V2, $V3 */ + SystemZ_VCHF /* 2411 */, SYSTEMZ_INS_VCHF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vchfs $V1, $V2, $V3 */ + SystemZ_VCHFS /* 2412 */, SYSTEMZ_INS_VCHFS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vchg $V1, $V2, $V3 */ + SystemZ_VCHG /* 2413 */, SYSTEMZ_INS_VCHG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vchgs $V1, $V2, $V3 */ + SystemZ_VCHGS /* 2414 */, SYSTEMZ_INS_VCHGS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vchh $V1, $V2, $V3 */ + SystemZ_VCHH /* 2415 */, SYSTEMZ_INS_VCHH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vchhs $V1, $V2, $V3 */ + SystemZ_VCHHS /* 2416 */, SYSTEMZ_INS_VCHHS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vchl $V1, $V2, $V3, $M4, $M5 */ + SystemZ_VCHL /* 2417 */, SYSTEMZ_INS_VCHL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vchlb $V1, $V2, $V3 */ + SystemZ_VCHLB /* 2418 */, SYSTEMZ_INS_VCHLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vchlbs $V1, $V2, $V3 */ + SystemZ_VCHLBS /* 2419 */, SYSTEMZ_INS_VCHLBS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vchlf $V1, $V2, $V3 */ + SystemZ_VCHLF /* 2420 */, SYSTEMZ_INS_VCHLF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vchlfs $V1, $V2, $V3 */ + SystemZ_VCHLFS /* 2421 */, SYSTEMZ_INS_VCHLFS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vchlg $V1, $V2, $V3 */ + SystemZ_VCHLG /* 2422 */, SYSTEMZ_INS_VCHLG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vchlgs $V1, $V2, $V3 */ + SystemZ_VCHLGS /* 2423 */, SYSTEMZ_INS_VCHLGS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vchlh $V1, $V2, $V3 */ + SystemZ_VCHLH /* 2424 */, SYSTEMZ_INS_VCHLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vchlhs $V1, $V2, $V3 */ + SystemZ_VCHLHS /* 2425 */, SYSTEMZ_INS_VCHLHS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vcksm $V1, $V2, $V3 */ + SystemZ_VCKSM /* 2426 */, SYSTEMZ_INS_VCKSM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vclfeb $V1, $V2, $M4, $M5 */ + SystemZ_VCLFEB /* 2427 */, SYSTEMZ_INS_VCLFEB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vclfnh $V1, $V2, $M3, $M4 */ + SystemZ_VCLFNH /* 2428 */, SYSTEMZ_INS_VCLFNH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, SYSTEMZ_FEATURE_FEATURENNPASSIST, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vclfnl $V1, $V2, $M3, $M4 */ + SystemZ_VCLFNL /* 2429 */, SYSTEMZ_INS_VCLFNL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, SYSTEMZ_FEATURE_FEATURENNPASSIST, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vclfp $V1, $V2, $M3, $M4, $M5 */ + SystemZ_VCLFP /* 2430 */, SYSTEMZ_INS_VCLFP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vclgd $V1, $V2, $M3, $M4, $M5 */ + SystemZ_VCLGD /* 2431 */, SYSTEMZ_INS_VCLGD, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vclgdb $V1, $V2, $M4, $M5 */ + SystemZ_VCLGDB /* 2432 */, SYSTEMZ_INS_VCLGDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vclz $V1, $V2, $M3 */ + SystemZ_VCLZ /* 2433 */, SYSTEMZ_INS_VCLZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vclzb $V1, $V2 */ + SystemZ_VCLZB /* 2434 */, SYSTEMZ_INS_VCLZB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vclzdp $V1, $V2, $M3 */ + SystemZ_VCLZDP /* 2435 */, SYSTEMZ_INS_VCLZDP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRK }} + + #endif +}, +{ + /* vclzf $V1, $V2 */ + SystemZ_VCLZF /* 2436 */, SYSTEMZ_INS_VCLZF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vclzg $V1, $V2 */ + SystemZ_VCLZG /* 2437 */, SYSTEMZ_INS_VCLZG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vclzh $V1, $V2 */ + SystemZ_VCLZH /* 2438 */, SYSTEMZ_INS_VCLZH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vcnf $V1, $V2, $M3, $M4 */ + SystemZ_VCNF /* 2439 */, SYSTEMZ_INS_VCNF, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, SYSTEMZ_FEATURE_FEATURENNPASSIST, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vcp $V1, $V2, $M3 */ + SystemZ_VCP /* 2440 */, SYSTEMZ_INS_VCP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRH }} + + #endif +}, +{ + /* vcrnf $V1, $V2, $V3, $M4, $M5 */ + SystemZ_VCRNF /* 2441 */, SYSTEMZ_INS_VCRNF, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, SYSTEMZ_FEATURE_FEATURENNPASSIST, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vcsfp $V1, $V2, $M3, $M4, $M5 */ + SystemZ_VCSFP /* 2442 */, SYSTEMZ_INS_VCSFP, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vcsph $V1, $V2, $V3, $M4 */ + SystemZ_VCSPH /* 2443 */, SYSTEMZ_INS_VCSPH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRJ }} + + #endif +}, +{ + /* vctz $V1, $V2, $M3 */ + SystemZ_VCTZ /* 2444 */, SYSTEMZ_INS_VCTZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vctzb $V1, $V2 */ + SystemZ_VCTZB /* 2445 */, SYSTEMZ_INS_VCTZB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vctzf $V1, $V2 */ + SystemZ_VCTZF /* 2446 */, SYSTEMZ_INS_VCTZF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vctzg $V1, $V2 */ + SystemZ_VCTZG /* 2447 */, SYSTEMZ_INS_VCTZG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vctzh $V1, $V2 */ + SystemZ_VCTZH /* 2448 */, SYSTEMZ_INS_VCTZH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vcvb $R1, $V2, $M3 */ + SystemZ_VCVB /* 2449 */, SYSTEMZ_INS_VCVB, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRI }} + + #endif +}, +{ + /* vcvbg $R1, $V2, $M3 */ + SystemZ_VCVBG /* 2450 */, SYSTEMZ_INS_VCVBG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRI }} + + #endif +}, +{ + /* vcvbg $R1, $V2, $M3, $M4 */ + SystemZ_VCVBGOpt /* 2451 */, SYSTEMZ_INS_VCVBG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRI }} + + #endif +}, +{ + /* vcvb $R1, $V2, $M3, $M4 */ + SystemZ_VCVBOpt /* 2452 */, SYSTEMZ_INS_VCVB, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRI }} + + #endif +}, +{ + /* vcvd $V1, $R2, $I3, $M4 */ + SystemZ_VCVD /* 2453 */, SYSTEMZ_INS_VCVD, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRII }} + + #endif +}, +{ + /* vcvdg $V1, $R2, $I3, $M4 */ + SystemZ_VCVDG /* 2454 */, SYSTEMZ_INS_VCVDG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRII }} + + #endif +}, +{ + /* vdp $V1, $V2, $V3, $I4, $M5 */ + SystemZ_VDP /* 2455 */, SYSTEMZ_INS_VDP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIF }} + + #endif +}, +{ + /* vec $V1, $V2, $M3 */ + SystemZ_VEC /* 2456 */, SYSTEMZ_INS_VEC, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vecb $V1, $V2 */ + SystemZ_VECB /* 2457 */, SYSTEMZ_INS_VECB, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vecf $V1, $V2 */ + SystemZ_VECF /* 2458 */, SYSTEMZ_INS_VECF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vecg $V1, $V2 */ + SystemZ_VECG /* 2459 */, SYSTEMZ_INS_VECG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vech $V1, $V2 */ + SystemZ_VECH /* 2460 */, SYSTEMZ_INS_VECH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vecl $V1, $V2, $M3 */ + SystemZ_VECL /* 2461 */, SYSTEMZ_INS_VECL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* veclb $V1, $V2 */ + SystemZ_VECLB /* 2462 */, SYSTEMZ_INS_VECLB, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* veclf $V1, $V2 */ + SystemZ_VECLF /* 2463 */, SYSTEMZ_INS_VECLF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* veclg $V1, $V2 */ + SystemZ_VECLG /* 2464 */, SYSTEMZ_INS_VECLG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* veclh $V1, $V2 */ + SystemZ_VECLH /* 2465 */, SYSTEMZ_INS_VECLH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* verim $V1, $V2, $V3, $I4, $M5 */ + SystemZ_VERIM /* 2466 */, SYSTEMZ_INS_VERIM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRID }} + + #endif +}, +{ + /* verimb $V1, $V2, $V3, $I4 */ + SystemZ_VERIMB /* 2467 */, SYSTEMZ_INS_VERIMB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRID }} + + #endif +}, +{ + /* verimf $V1, $V2, $V3, $I4 */ + SystemZ_VERIMF /* 2468 */, SYSTEMZ_INS_VERIMF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRID }} + + #endif +}, +{ + /* verimg $V1, $V2, $V3, $I4 */ + SystemZ_VERIMG /* 2469 */, SYSTEMZ_INS_VERIMG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRID }} + + #endif +}, +{ + /* verimh $V1, $V2, $V3, $I4 */ + SystemZ_VERIMH /* 2470 */, SYSTEMZ_INS_VERIMH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRID }} + + #endif +}, +{ + /* verll $V1, $V3, $BD2, $M4 */ + SystemZ_VERLL /* 2471 */, SYSTEMZ_INS_VERLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* verllb $V1, $V3, $BD2 */ + SystemZ_VERLLB /* 2472 */, SYSTEMZ_INS_VERLLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* verllf $V1, $V3, $BD2 */ + SystemZ_VERLLF /* 2473 */, SYSTEMZ_INS_VERLLF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* verllg $V1, $V3, $BD2 */ + SystemZ_VERLLG /* 2474 */, SYSTEMZ_INS_VERLLG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* verllh $V1, $V3, $BD2 */ + SystemZ_VERLLH /* 2475 */, SYSTEMZ_INS_VERLLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* verllv $V1, $V2, $V3, $M4 */ + SystemZ_VERLLV /* 2476 */, SYSTEMZ_INS_VERLLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* verllvb $V1, $V2, $V3 */ + SystemZ_VERLLVB /* 2477 */, SYSTEMZ_INS_VERLLVB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* verllvf $V1, $V2, $V3 */ + SystemZ_VERLLVF /* 2478 */, SYSTEMZ_INS_VERLLVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* verllvg $V1, $V2, $V3 */ + SystemZ_VERLLVG /* 2479 */, SYSTEMZ_INS_VERLLVG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* verllvh $V1, $V2, $V3 */ + SystemZ_VERLLVH /* 2480 */, SYSTEMZ_INS_VERLLVH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vesl $V1, $V3, $BD2, $M4 */ + SystemZ_VESL /* 2481 */, SYSTEMZ_INS_VESL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* veslb $V1, $V3, $BD2 */ + SystemZ_VESLB /* 2482 */, SYSTEMZ_INS_VESLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* veslf $V1, $V3, $BD2 */ + SystemZ_VESLF /* 2483 */, SYSTEMZ_INS_VESLF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* veslg $V1, $V3, $BD2 */ + SystemZ_VESLG /* 2484 */, SYSTEMZ_INS_VESLG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* veslh $V1, $V3, $BD2 */ + SystemZ_VESLH /* 2485 */, SYSTEMZ_INS_VESLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* veslv $V1, $V2, $V3, $M4 */ + SystemZ_VESLV /* 2486 */, SYSTEMZ_INS_VESLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* veslvb $V1, $V2, $V3 */ + SystemZ_VESLVB /* 2487 */, SYSTEMZ_INS_VESLVB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* veslvf $V1, $V2, $V3 */ + SystemZ_VESLVF /* 2488 */, SYSTEMZ_INS_VESLVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* veslvg $V1, $V2, $V3 */ + SystemZ_VESLVG /* 2489 */, SYSTEMZ_INS_VESLVG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* veslvh $V1, $V2, $V3 */ + SystemZ_VESLVH /* 2490 */, SYSTEMZ_INS_VESLVH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vesra $V1, $V3, $BD2, $M4 */ + SystemZ_VESRA /* 2491 */, SYSTEMZ_INS_VESRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* vesrab $V1, $V3, $BD2 */ + SystemZ_VESRAB /* 2492 */, SYSTEMZ_INS_VESRAB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* vesraf $V1, $V3, $BD2 */ + SystemZ_VESRAF /* 2493 */, SYSTEMZ_INS_VESRAF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* vesrag $V1, $V3, $BD2 */ + SystemZ_VESRAG /* 2494 */, SYSTEMZ_INS_VESRAG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* vesrah $V1, $V3, $BD2 */ + SystemZ_VESRAH /* 2495 */, SYSTEMZ_INS_VESRAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* vesrav $V1, $V2, $V3, $M4 */ + SystemZ_VESRAV /* 2496 */, SYSTEMZ_INS_VESRAV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vesravb $V1, $V2, $V3 */ + SystemZ_VESRAVB /* 2497 */, SYSTEMZ_INS_VESRAVB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vesravf $V1, $V2, $V3 */ + SystemZ_VESRAVF /* 2498 */, SYSTEMZ_INS_VESRAVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vesravg $V1, $V2, $V3 */ + SystemZ_VESRAVG /* 2499 */, SYSTEMZ_INS_VESRAVG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vesravh $V1, $V2, $V3 */ + SystemZ_VESRAVH /* 2500 */, SYSTEMZ_INS_VESRAVH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vesrl $V1, $V3, $BD2, $M4 */ + SystemZ_VESRL /* 2501 */, SYSTEMZ_INS_VESRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* vesrlb $V1, $V3, $BD2 */ + SystemZ_VESRLB /* 2502 */, SYSTEMZ_INS_VESRLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* vesrlf $V1, $V3, $BD2 */ + SystemZ_VESRLF /* 2503 */, SYSTEMZ_INS_VESRLF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* vesrlg $V1, $V3, $BD2 */ + SystemZ_VESRLG /* 2504 */, SYSTEMZ_INS_VESRLG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* vesrlh $V1, $V3, $BD2 */ + SystemZ_VESRLH /* 2505 */, SYSTEMZ_INS_VESRLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* vesrlv $V1, $V2, $V3, $M4 */ + SystemZ_VESRLV /* 2506 */, SYSTEMZ_INS_VESRLV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vesrlvb $V1, $V2, $V3 */ + SystemZ_VESRLVB /* 2507 */, SYSTEMZ_INS_VESRLVB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vesrlvf $V1, $V2, $V3 */ + SystemZ_VESRLVF /* 2508 */, SYSTEMZ_INS_VESRLVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vesrlvg $V1, $V2, $V3 */ + SystemZ_VESRLVG /* 2509 */, SYSTEMZ_INS_VESRLVG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vesrlvh $V1, $V2, $V3 */ + SystemZ_VESRLVH /* 2510 */, SYSTEMZ_INS_VESRLVH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfa $V1, $V2, $V3, $M4, $M5 */ + SystemZ_VFA /* 2511 */, SYSTEMZ_INS_VFA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfadb $V1, $V2, $V3 */ + SystemZ_VFADB /* 2512 */, SYSTEMZ_INS_VFADB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfae $V1, $V2, $V3, $M4, $M5 */ + SystemZ_VFAE /* 2513 */, SYSTEMZ_INS_VFAE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfaeb $V1, $V2, $V3, $M5 */ + SystemZ_VFAEB /* 2514 */, SYSTEMZ_INS_VFAEB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfaebs $V1, $V2, $V3, $M5 */ + SystemZ_VFAEBS /* 2515 */, SYSTEMZ_INS_VFAEBS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfaef $V1, $V2, $V3, $M5 */ + SystemZ_VFAEF /* 2516 */, SYSTEMZ_INS_VFAEF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfaefs $V1, $V2, $V3, $M5 */ + SystemZ_VFAEFS /* 2517 */, SYSTEMZ_INS_VFAEFS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfaeh $V1, $V2, $V3, $M5 */ + SystemZ_VFAEH /* 2518 */, SYSTEMZ_INS_VFAEH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfaehs $V1, $V2, $V3, $M5 */ + SystemZ_VFAEHS /* 2519 */, SYSTEMZ_INS_VFAEHS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfaezb $V1, $V2, $V3, $M5 */ + SystemZ_VFAEZB /* 2520 */, SYSTEMZ_INS_VFAEZB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfaezbs $V1, $V2, $V3, $M5 */ + SystemZ_VFAEZBS /* 2521 */, SYSTEMZ_INS_VFAEZBS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfaezf $V1, $V2, $V3, $M5 */ + SystemZ_VFAEZF /* 2522 */, SYSTEMZ_INS_VFAEZF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfaezfs $V1, $V2, $V3, $M5 */ + SystemZ_VFAEZFS /* 2523 */, SYSTEMZ_INS_VFAEZFS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfaezh $V1, $V2, $V3, $M5 */ + SystemZ_VFAEZH /* 2524 */, SYSTEMZ_INS_VFAEZH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfaezhs $V1, $V2, $V3, $M5 */ + SystemZ_VFAEZHS /* 2525 */, SYSTEMZ_INS_VFAEZHS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfasb $V1, $V2, $V3 */ + SystemZ_VFASB /* 2526 */, SYSTEMZ_INS_VFASB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfce $V1, $V2, $V3, $M4, $M5, $M6 */ + SystemZ_VFCE /* 2527 */, SYSTEMZ_INS_VFCE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfcedb $V1, $V2, $V3 */ + SystemZ_VFCEDB /* 2528 */, SYSTEMZ_INS_VFCEDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfcedbs $V1, $V2, $V3 */ + SystemZ_VFCEDBS /* 2529 */, SYSTEMZ_INS_VFCEDBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfcesb $V1, $V2, $V3 */ + SystemZ_VFCESB /* 2530 */, SYSTEMZ_INS_VFCESB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfcesbs $V1, $V2, $V3 */ + SystemZ_VFCESBS /* 2531 */, SYSTEMZ_INS_VFCESBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfch $V1, $V2, $V3, $M4, $M5, $M6 */ + SystemZ_VFCH /* 2532 */, SYSTEMZ_INS_VFCH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfchdb $V1, $V2, $V3 */ + SystemZ_VFCHDB /* 2533 */, SYSTEMZ_INS_VFCHDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfchdbs $V1, $V2, $V3 */ + SystemZ_VFCHDBS /* 2534 */, SYSTEMZ_INS_VFCHDBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfche $V1, $V2, $V3, $M4, $M5, $M6 */ + SystemZ_VFCHE /* 2535 */, SYSTEMZ_INS_VFCHE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfchedb $V1, $V2, $V3 */ + SystemZ_VFCHEDB /* 2536 */, SYSTEMZ_INS_VFCHEDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfchedbs $V1, $V2, $V3 */ + SystemZ_VFCHEDBS /* 2537 */, SYSTEMZ_INS_VFCHEDBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfchesb $V1, $V2, $V3 */ + SystemZ_VFCHESB /* 2538 */, SYSTEMZ_INS_VFCHESB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfchesbs $V1, $V2, $V3 */ + SystemZ_VFCHESBS /* 2539 */, SYSTEMZ_INS_VFCHESBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfchsb $V1, $V2, $V3 */ + SystemZ_VFCHSB /* 2540 */, SYSTEMZ_INS_VFCHSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfchsbs $V1, $V2, $V3 */ + SystemZ_VFCHSBS /* 2541 */, SYSTEMZ_INS_VFCHSBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfd $V1, $V2, $V3, $M4, $M5 */ + SystemZ_VFD /* 2542 */, SYSTEMZ_INS_VFD, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfddb $V1, $V2, $V3 */ + SystemZ_VFDDB /* 2543 */, SYSTEMZ_INS_VFDDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfdsb $V1, $V2, $V3 */ + SystemZ_VFDSB /* 2544 */, SYSTEMZ_INS_VFDSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfee $V1, $V2, $V3, $M4, $M5 */ + SystemZ_VFEE /* 2545 */, SYSTEMZ_INS_VFEE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfeeb $V1, $V2, $V3, $M5 */ + SystemZ_VFEEB /* 2546 */, SYSTEMZ_INS_VFEEB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfeebs $V1, $V2, $V3 */ + SystemZ_VFEEBS /* 2547 */, SYSTEMZ_INS_VFEEBS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfeef $V1, $V2, $V3, $M5 */ + SystemZ_VFEEF /* 2548 */, SYSTEMZ_INS_VFEEF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfeefs $V1, $V2, $V3 */ + SystemZ_VFEEFS /* 2549 */, SYSTEMZ_INS_VFEEFS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfeeh $V1, $V2, $V3, $M5 */ + SystemZ_VFEEH /* 2550 */, SYSTEMZ_INS_VFEEH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfeehs $V1, $V2, $V3 */ + SystemZ_VFEEHS /* 2551 */, SYSTEMZ_INS_VFEEHS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfeezb $V1, $V2, $V3 */ + SystemZ_VFEEZB /* 2552 */, SYSTEMZ_INS_VFEEZB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfeezbs $V1, $V2, $V3 */ + SystemZ_VFEEZBS /* 2553 */, SYSTEMZ_INS_VFEEZBS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfeezf $V1, $V2, $V3 */ + SystemZ_VFEEZF /* 2554 */, SYSTEMZ_INS_VFEEZF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfeezfs $V1, $V2, $V3 */ + SystemZ_VFEEZFS /* 2555 */, SYSTEMZ_INS_VFEEZFS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfeezh $V1, $V2, $V3 */ + SystemZ_VFEEZH /* 2556 */, SYSTEMZ_INS_VFEEZH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfeezhs $V1, $V2, $V3 */ + SystemZ_VFEEZHS /* 2557 */, SYSTEMZ_INS_VFEEZHS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfene $V1, $V2, $V3, $M4, $M5 */ + SystemZ_VFENE /* 2558 */, SYSTEMZ_INS_VFENE, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfeneb $V1, $V2, $V3, $M5 */ + SystemZ_VFENEB /* 2559 */, SYSTEMZ_INS_VFENEB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfenebs $V1, $V2, $V3 */ + SystemZ_VFENEBS /* 2560 */, SYSTEMZ_INS_VFENEBS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfenef $V1, $V2, $V3, $M5 */ + SystemZ_VFENEF /* 2561 */, SYSTEMZ_INS_VFENEF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfenefs $V1, $V2, $V3 */ + SystemZ_VFENEFS /* 2562 */, SYSTEMZ_INS_VFENEFS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfeneh $V1, $V2, $V3, $M5 */ + SystemZ_VFENEH /* 2563 */, SYSTEMZ_INS_VFENEH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfenehs $V1, $V2, $V3 */ + SystemZ_VFENEHS /* 2564 */, SYSTEMZ_INS_VFENEHS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfenezb $V1, $V2, $V3 */ + SystemZ_VFENEZB /* 2565 */, SYSTEMZ_INS_VFENEZB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfenezbs $V1, $V2, $V3 */ + SystemZ_VFENEZBS /* 2566 */, SYSTEMZ_INS_VFENEZBS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfenezf $V1, $V2, $V3 */ + SystemZ_VFENEZF /* 2567 */, SYSTEMZ_INS_VFENEZF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfenezfs $V1, $V2, $V3 */ + SystemZ_VFENEZFS /* 2568 */, SYSTEMZ_INS_VFENEZFS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfenezh $V1, $V2, $V3 */ + SystemZ_VFENEZH /* 2569 */, SYSTEMZ_INS_VFENEZH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfenezhs $V1, $V2, $V3 */ + SystemZ_VFENEZHS /* 2570 */, SYSTEMZ_INS_VFENEZHS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vfi $V1, $V2, $M3, $M4, $M5 */ + SystemZ_VFI /* 2571 */, SYSTEMZ_INS_VFI, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vfidb $V1, $V2, $M4, $M5 */ + SystemZ_VFIDB /* 2572 */, SYSTEMZ_INS_VFIDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vfisb $V1, $V2, $M4, $M5 */ + SystemZ_VFISB /* 2573 */, SYSTEMZ_INS_VFISB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vfkedb $V1, $V2, $V3 */ + SystemZ_VFKEDB /* 2574 */, SYSTEMZ_INS_VFKEDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfkedbs $V1, $V2, $V3 */ + SystemZ_VFKEDBS /* 2575 */, SYSTEMZ_INS_VFKEDBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfkesb $V1, $V2, $V3 */ + SystemZ_VFKESB /* 2576 */, SYSTEMZ_INS_VFKESB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfkesbs $V1, $V2, $V3 */ + SystemZ_VFKESBS /* 2577 */, SYSTEMZ_INS_VFKESBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfkhdb $V1, $V2, $V3 */ + SystemZ_VFKHDB /* 2578 */, SYSTEMZ_INS_VFKHDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfkhdbs $V1, $V2, $V3 */ + SystemZ_VFKHDBS /* 2579 */, SYSTEMZ_INS_VFKHDBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfkhedb $V1, $V2, $V3 */ + SystemZ_VFKHEDB /* 2580 */, SYSTEMZ_INS_VFKHEDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfkhedbs $V1, $V2, $V3 */ + SystemZ_VFKHEDBS /* 2581 */, SYSTEMZ_INS_VFKHEDBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfkhesb $V1, $V2, $V3 */ + SystemZ_VFKHESB /* 2582 */, SYSTEMZ_INS_VFKHESB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfkhesbs $V1, $V2, $V3 */ + SystemZ_VFKHESBS /* 2583 */, SYSTEMZ_INS_VFKHESBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfkhsb $V1, $V2, $V3 */ + SystemZ_VFKHSB /* 2584 */, SYSTEMZ_INS_VFKHSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfkhsbs $V1, $V2, $V3 */ + SystemZ_VFKHSBS /* 2585 */, SYSTEMZ_INS_VFKHSBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vflcdb $V1, $V2 */ + SystemZ_VFLCDB /* 2586 */, SYSTEMZ_INS_VFLCDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vflcsb $V1, $V2 */ + SystemZ_VFLCSB /* 2587 */, SYSTEMZ_INS_VFLCSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vfll $V1, $V2, $M3, $M4 */ + SystemZ_VFLL /* 2588 */, SYSTEMZ_INS_VFLL, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vflls $V1, $V2 */ + SystemZ_VFLLS /* 2589 */, SYSTEMZ_INS_VFLLS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vflndb $V1, $V2 */ + SystemZ_VFLNDB /* 2590 */, SYSTEMZ_INS_VFLNDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vflnsb $V1, $V2 */ + SystemZ_VFLNSB /* 2591 */, SYSTEMZ_INS_VFLNSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vflpdb $V1, $V2 */ + SystemZ_VFLPDB /* 2592 */, SYSTEMZ_INS_VFLPDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vflpsb $V1, $V2 */ + SystemZ_VFLPSB /* 2593 */, SYSTEMZ_INS_VFLPSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vflr $V1, $V2, $M3, $M4, $M5 */ + SystemZ_VFLR /* 2594 */, SYSTEMZ_INS_VFLR, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vflrd $V1, $V2, $M4, $M5 */ + SystemZ_VFLRD /* 2595 */, SYSTEMZ_INS_VFLRD, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vfm $V1, $V2, $V3, $M4, $M5 */ + SystemZ_VFM /* 2596 */, SYSTEMZ_INS_VFM, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfma $V1, $V2, $V3, $V4, $M5, $M6 */ + SystemZ_VFMA /* 2597 */, SYSTEMZ_INS_VFMA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* vfmadb $V1, $V2, $V3, $V4 */ + SystemZ_VFMADB /* 2598 */, SYSTEMZ_INS_VFMADB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* vfmasb $V1, $V2, $V3, $V4 */ + SystemZ_VFMASB /* 2599 */, SYSTEMZ_INS_VFMASB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* vfmax $V1, $V2, $V3, $M4, $M5, $M6 */ + SystemZ_VFMAX /* 2600 */, SYSTEMZ_INS_VFMAX, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfmaxdb $V1, $V2, $V3, $M6 */ + SystemZ_VFMAXDB /* 2601 */, SYSTEMZ_INS_VFMAXDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfmaxsb $V1, $V2, $V3, $M6 */ + SystemZ_VFMAXSB /* 2602 */, SYSTEMZ_INS_VFMAXSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfmdb $V1, $V2, $V3 */ + SystemZ_VFMDB /* 2603 */, SYSTEMZ_INS_VFMDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfmin $V1, $V2, $V3, $M4, $M5, $M6 */ + SystemZ_VFMIN /* 2604 */, SYSTEMZ_INS_VFMIN, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfmindb $V1, $V2, $V3, $M6 */ + SystemZ_VFMINDB /* 2605 */, SYSTEMZ_INS_VFMINDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfminsb $V1, $V2, $V3, $M6 */ + SystemZ_VFMINSB /* 2606 */, SYSTEMZ_INS_VFMINSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfms $V1, $V2, $V3, $V4, $M5, $M6 */ + SystemZ_VFMS /* 2607 */, SYSTEMZ_INS_VFMS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* vfmsb $V1, $V2, $V3 */ + SystemZ_VFMSB /* 2608 */, SYSTEMZ_INS_VFMSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfmsdb $V1, $V2, $V3, $V4 */ + SystemZ_VFMSDB /* 2609 */, SYSTEMZ_INS_VFMSDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* vfmssb $V1, $V2, $V3, $V4 */ + SystemZ_VFMSSB /* 2610 */, SYSTEMZ_INS_VFMSSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* vfnma $V1, $V2, $V3, $V4, $M5, $M6 */ + SystemZ_VFNMA /* 2611 */, SYSTEMZ_INS_VFNMA, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* vfnmadb $V1, $V2, $V3, $V4 */ + SystemZ_VFNMADB /* 2612 */, SYSTEMZ_INS_VFNMADB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* vfnmasb $V1, $V2, $V3, $V4 */ + SystemZ_VFNMASB /* 2613 */, SYSTEMZ_INS_VFNMASB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* vfnms $V1, $V2, $V3, $V4, $M5, $M6 */ + SystemZ_VFNMS /* 2614 */, SYSTEMZ_INS_VFNMS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* vfnmsdb $V1, $V2, $V3, $V4 */ + SystemZ_VFNMSDB /* 2615 */, SYSTEMZ_INS_VFNMSDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* vfnmssb $V1, $V2, $V3, $V4 */ + SystemZ_VFNMSSB /* 2616 */, SYSTEMZ_INS_VFNMSSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* vfpso $V1, $V2, $M3, $M4, $M5 */ + SystemZ_VFPSO /* 2617 */, SYSTEMZ_INS_VFPSO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vfpsodb $V1, $V2, $M5 */ + SystemZ_VFPSODB /* 2618 */, SYSTEMZ_INS_VFPSODB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vfpsosb $V1, $V2, $M5 */ + SystemZ_VFPSOSB /* 2619 */, SYSTEMZ_INS_VFPSOSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vfs $V1, $V2, $V3, $M4, $M5 */ + SystemZ_VFS /* 2620 */, SYSTEMZ_INS_VFS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfsdb $V1, $V2, $V3 */ + SystemZ_VFSDB /* 2621 */, SYSTEMZ_INS_VFSDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vfsq $V1, $V2, $M3, $M4 */ + SystemZ_VFSQ /* 2622 */, SYSTEMZ_INS_VFSQ, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vfsqdb $V1, $V2 */ + SystemZ_VFSQDB /* 2623 */, SYSTEMZ_INS_VFSQDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vfsqsb $V1, $V2 */ + SystemZ_VFSQSB /* 2624 */, SYSTEMZ_INS_VFSQSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vfssb $V1, $V2, $V3 */ + SystemZ_VFSSB /* 2625 */, SYSTEMZ_INS_VFSSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vftci $V1, $V2, $I3, $M4, $M5 */ + SystemZ_VFTCI /* 2626 */, SYSTEMZ_INS_VFTCI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIE }} + + #endif +}, +{ + /* vftcidb $V1, $V2, $I3 */ + SystemZ_VFTCIDB /* 2627 */, SYSTEMZ_INS_VFTCIDB, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIE }} + + #endif +}, +{ + /* vftcisb $V1, $V2, $I3 */ + SystemZ_VFTCISB /* 2628 */, SYSTEMZ_INS_VFTCISB, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIE }} + + #endif +}, +{ + /* vgbm $V1, $I2 */ + SystemZ_VGBM /* 2629 */, SYSTEMZ_INS_VGBM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIA }} + + #endif +}, +{ + /* vgef $V1, $VBD2, $M3 */ + SystemZ_VGEF /* 2630 */, SYSTEMZ_INS_VGEF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRV }} + + #endif +}, +{ + /* vgeg $V1, $VBD2, $M3 */ + SystemZ_VGEG /* 2631 */, SYSTEMZ_INS_VGEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRV }} + + #endif +}, +{ + /* vgfm $V1, $V2, $V3, $M4 */ + SystemZ_VGFM /* 2632 */, SYSTEMZ_INS_VGFM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vgfma $V1, $V2, $V3, $V4, $M5 */ + SystemZ_VGFMA /* 2633 */, SYSTEMZ_INS_VGFMA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vgfmab $V1, $V2, $V3, $V4 */ + SystemZ_VGFMAB /* 2634 */, SYSTEMZ_INS_VGFMAB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vgfmaf $V1, $V2, $V3, $V4 */ + SystemZ_VGFMAF /* 2635 */, SYSTEMZ_INS_VGFMAF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vgfmag $V1, $V2, $V3, $V4 */ + SystemZ_VGFMAG /* 2636 */, SYSTEMZ_INS_VGFMAG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vgfmah $V1, $V2, $V3, $V4 */ + SystemZ_VGFMAH /* 2637 */, SYSTEMZ_INS_VGFMAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vgfmb $V1, $V2, $V3 */ + SystemZ_VGFMB /* 2638 */, SYSTEMZ_INS_VGFMB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vgfmf $V1, $V2, $V3 */ + SystemZ_VGFMF /* 2639 */, SYSTEMZ_INS_VGFMF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vgfmg $V1, $V2, $V3 */ + SystemZ_VGFMG /* 2640 */, SYSTEMZ_INS_VGFMG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vgfmh $V1, $V2, $V3 */ + SystemZ_VGFMH /* 2641 */, SYSTEMZ_INS_VGFMH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vgm $V1, $I2, $I3, $M4 */ + SystemZ_VGM /* 2642 */, SYSTEMZ_INS_VGM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIB }} + + #endif +}, +{ + /* vgmb $V1, $I2, $I3 */ + SystemZ_VGMB /* 2643 */, SYSTEMZ_INS_VGMB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIB }} + + #endif +}, +{ + /* vgmf $V1, $I2, $I3 */ + SystemZ_VGMF /* 2644 */, SYSTEMZ_INS_VGMF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIB }} + + #endif +}, +{ + /* vgmg $V1, $I2, $I3 */ + SystemZ_VGMG /* 2645 */, SYSTEMZ_INS_VGMG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIB }} + + #endif +}, +{ + /* vgmh $V1, $I2, $I3 */ + SystemZ_VGMH /* 2646 */, SYSTEMZ_INS_VGMH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIB }} + + #endif +}, +{ + /* vistr $V1, $V2, $M3, $M5 */ + SystemZ_VISTR /* 2647 */, SYSTEMZ_INS_VISTR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vistrb $V1, $V2, $M5 */ + SystemZ_VISTRB /* 2648 */, SYSTEMZ_INS_VISTRB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vistrbs $V1, $V2 */ + SystemZ_VISTRBS /* 2649 */, SYSTEMZ_INS_VISTRBS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vistrf $V1, $V2, $M5 */ + SystemZ_VISTRF /* 2650 */, SYSTEMZ_INS_VISTRF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vistrfs $V1, $V2 */ + SystemZ_VISTRFS /* 2651 */, SYSTEMZ_INS_VISTRFS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vistrh $V1, $V2, $M5 */ + SystemZ_VISTRH /* 2652 */, SYSTEMZ_INS_VISTRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vistrhs $V1, $V2 */ + SystemZ_VISTRHS /* 2653 */, SYSTEMZ_INS_VISTRHS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vl $V1, $XBD2 */ + SystemZ_VL /* 2654 */, SYSTEMZ_INS_VL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vl $V1, $XBD2, $M3 */ + SystemZ_VLAlign /* 2655 */, SYSTEMZ_INS_VL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlbb $V1, $XBD2, $M3 */ + SystemZ_VLBB /* 2656 */, SYSTEMZ_INS_VLBB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlbr $V1, $XBD2, $M3 */ + SystemZ_VLBR /* 2657 */, SYSTEMZ_INS_VLBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlbrf $V1, $XBD2 */ + SystemZ_VLBRF /* 2658 */, SYSTEMZ_INS_VLBRF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlbrg $V1, $XBD2 */ + SystemZ_VLBRG /* 2659 */, SYSTEMZ_INS_VLBRG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlbrh $V1, $XBD2 */ + SystemZ_VLBRH /* 2660 */, SYSTEMZ_INS_VLBRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlbrq $V1, $XBD2 */ + SystemZ_VLBRQ /* 2661 */, SYSTEMZ_INS_VLBRQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlbrrep $V1, $XBD2, $M3 */ + SystemZ_VLBRREP /* 2662 */, SYSTEMZ_INS_VLBRREP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlbrrepf $V1, $XBD2 */ + SystemZ_VLBRREPF /* 2663 */, SYSTEMZ_INS_VLBRREPF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlbrrepg $V1, $XBD2 */ + SystemZ_VLBRREPG /* 2664 */, SYSTEMZ_INS_VLBRREPG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlbrreph $V1, $XBD2 */ + SystemZ_VLBRREPH /* 2665 */, SYSTEMZ_INS_VLBRREPH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlc $V1, $V2, $M3 */ + SystemZ_VLC /* 2666 */, SYSTEMZ_INS_VLC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vlcb $V1, $V2 */ + SystemZ_VLCB /* 2667 */, SYSTEMZ_INS_VLCB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vlcf $V1, $V2 */ + SystemZ_VLCF /* 2668 */, SYSTEMZ_INS_VLCF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vlcg $V1, $V2 */ + SystemZ_VLCG /* 2669 */, SYSTEMZ_INS_VLCG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vlch $V1, $V2 */ + SystemZ_VLCH /* 2670 */, SYSTEMZ_INS_VLCH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vlde $V1, $V2, $M3, $M4 */ + SystemZ_VLDE /* 2671 */, SYSTEMZ_INS_VLDE, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vldeb $V1, $V2 */ + SystemZ_VLDEB /* 2672 */, SYSTEMZ_INS_VLDEB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vleb $V1, $XBD2, $M3 */ + SystemZ_VLEB /* 2673 */, SYSTEMZ_INS_VLEB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlebrf $V1, $XBD2, $M3 */ + SystemZ_VLEBRF /* 2674 */, SYSTEMZ_INS_VLEBRF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlebrg $V1, $XBD2, $M3 */ + SystemZ_VLEBRG /* 2675 */, SYSTEMZ_INS_VLEBRG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlebrh $V1, $XBD2, $M3 */ + SystemZ_VLEBRH /* 2676 */, SYSTEMZ_INS_VLEBRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vled $V1, $V2, $M3, $M4, $M5 */ + SystemZ_VLED /* 2677 */, SYSTEMZ_INS_VLED, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vledb $V1, $V2, $M4, $M5 */ + SystemZ_VLEDB /* 2678 */, SYSTEMZ_INS_VLEDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vlef $V1, $XBD2, $M3 */ + SystemZ_VLEF /* 2679 */, SYSTEMZ_INS_VLEF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vleg $V1, $XBD2, $M3 */ + SystemZ_VLEG /* 2680 */, SYSTEMZ_INS_VLEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vleh $V1, $XBD2, $M3 */ + SystemZ_VLEH /* 2681 */, SYSTEMZ_INS_VLEH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vleib $V1, $I2, $M3 */ + SystemZ_VLEIB /* 2682 */, SYSTEMZ_INS_VLEIB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIA }} + + #endif +}, +{ + /* vleif $V1, $I2, $M3 */ + SystemZ_VLEIF /* 2683 */, SYSTEMZ_INS_VLEIF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIA }} + + #endif +}, +{ + /* vleig $V1, $I2, $M3 */ + SystemZ_VLEIG /* 2684 */, SYSTEMZ_INS_VLEIG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIA }} + + #endif +}, +{ + /* vleih $V1, $I2, $M3 */ + SystemZ_VLEIH /* 2685 */, SYSTEMZ_INS_VLEIH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIA }} + + #endif +}, +{ + /* vler $V1, $XBD2, $M3 */ + SystemZ_VLER /* 2686 */, SYSTEMZ_INS_VLER, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlerf $V1, $XBD2 */ + SystemZ_VLERF /* 2687 */, SYSTEMZ_INS_VLERF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlerg $V1, $XBD2 */ + SystemZ_VLERG /* 2688 */, SYSTEMZ_INS_VLERG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlerh $V1, $XBD2 */ + SystemZ_VLERH /* 2689 */, SYSTEMZ_INS_VLERH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlgv $R1, $V3, $BD2, $M4 */ + SystemZ_VLGV /* 2690 */, SYSTEMZ_INS_VLGV, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSC }} + + #endif +}, +{ + /* vlgvb $R1, $V3, $BD2 */ + SystemZ_VLGVB /* 2691 */, SYSTEMZ_INS_VLGVB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSC }} + + #endif +}, +{ + /* vlgvf $R1, $V3, $BD2 */ + SystemZ_VLGVF /* 2692 */, SYSTEMZ_INS_VLGVF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSC }} + + #endif +}, +{ + /* vlgvg $R1, $V3, $BD2 */ + SystemZ_VLGVG /* 2693 */, SYSTEMZ_INS_VLGVG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSC }} + + #endif +}, +{ + /* vlgvh $R1, $V3, $BD2 */ + SystemZ_VLGVH /* 2694 */, SYSTEMZ_INS_VLGVH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSC }} + + #endif +}, +{ + /* vlip $V1, $I2, $I3 */ + SystemZ_VLIP /* 2695 */, SYSTEMZ_INS_VLIP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIH }} + + #endif +}, +{ + /* vll $V1, $R3, $BD2 */ + SystemZ_VLL /* 2696 */, SYSTEMZ_INS_VLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSB }} + + #endif +}, +{ + /* vllebrz $V1, $XBD2, $M3 */ + SystemZ_VLLEBRZ /* 2697 */, SYSTEMZ_INS_VLLEBRZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vllebrze $V1, $XBD2 */ + SystemZ_VLLEBRZE /* 2698 */, SYSTEMZ_INS_VLLEBRZE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vllebrzf $V1, $XBD2 */ + SystemZ_VLLEBRZF /* 2699 */, SYSTEMZ_INS_VLLEBRZF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vllebrzg $V1, $XBD2 */ + SystemZ_VLLEBRZG /* 2700 */, SYSTEMZ_INS_VLLEBRZG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vllebrzh $V1, $XBD2 */ + SystemZ_VLLEBRZH /* 2701 */, SYSTEMZ_INS_VLLEBRZH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vllez $V1, $XBD2, $M3 */ + SystemZ_VLLEZ /* 2702 */, SYSTEMZ_INS_VLLEZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vllezb $V1, $XBD2 */ + SystemZ_VLLEZB /* 2703 */, SYSTEMZ_INS_VLLEZB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vllezf $V1, $XBD2 */ + SystemZ_VLLEZF /* 2704 */, SYSTEMZ_INS_VLLEZF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vllezg $V1, $XBD2 */ + SystemZ_VLLEZG /* 2705 */, SYSTEMZ_INS_VLLEZG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vllezh $V1, $XBD2 */ + SystemZ_VLLEZH /* 2706 */, SYSTEMZ_INS_VLLEZH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vllezlf $V1, $XBD2 */ + SystemZ_VLLEZLF /* 2707 */, SYSTEMZ_INS_VLLEZLF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlm $V1, $V3, $BD2 */ + SystemZ_VLM /* 2708 */, SYSTEMZ_INS_VLM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* vlm $V1, $V3, $BD2, $M4 */ + SystemZ_VLMAlign /* 2709 */, SYSTEMZ_INS_VLM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* vlp $V1, $V2, $M3 */ + SystemZ_VLP /* 2710 */, SYSTEMZ_INS_VLP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vlpb $V1, $V2 */ + SystemZ_VLPB /* 2711 */, SYSTEMZ_INS_VLPB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vlpf $V1, $V2 */ + SystemZ_VLPF /* 2712 */, SYSTEMZ_INS_VLPF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vlpg $V1, $V2 */ + SystemZ_VLPG /* 2713 */, SYSTEMZ_INS_VLPG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vlph $V1, $V2 */ + SystemZ_VLPH /* 2714 */, SYSTEMZ_INS_VLPH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vlr $V1, $V2 */ + SystemZ_VLR /* 2715 */, SYSTEMZ_INS_VLR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vlrep $V1, $XBD2, $M3 */ + SystemZ_VLREP /* 2716 */, SYSTEMZ_INS_VLREP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlrepb $V1, $XBD2 */ + SystemZ_VLREPB /* 2717 */, SYSTEMZ_INS_VLREPB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlrepf $V1, $XBD2 */ + SystemZ_VLREPF /* 2718 */, SYSTEMZ_INS_VLREPF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlrepg $V1, $XBD2 */ + SystemZ_VLREPG /* 2719 */, SYSTEMZ_INS_VLREPG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlreph $V1, $XBD2 */ + SystemZ_VLREPH /* 2720 */, SYSTEMZ_INS_VLREPH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vlrl $V1, $BD2, $I3 */ + SystemZ_VLRL /* 2721 */, SYSTEMZ_INS_VLRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVSI }} + + #endif +}, +{ + /* vlrlr $V1, $R3, $BD2 */ + SystemZ_VLRLR /* 2722 */, SYSTEMZ_INS_VLRLR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSD }} + + #endif +}, +{ + /* vlvg $V1, $R3, $BD2, $M4 */ + SystemZ_VLVG /* 2723 */, SYSTEMZ_INS_VLVG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSB }} + + #endif +}, +{ + /* vlvgb $V1, $R3, $BD2 */ + SystemZ_VLVGB /* 2724 */, SYSTEMZ_INS_VLVGB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSB }} + + #endif +}, +{ + /* vlvgf $V1, $R3, $BD2 */ + SystemZ_VLVGF /* 2725 */, SYSTEMZ_INS_VLVGF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSB }} + + #endif +}, +{ + /* vlvgg $V1, $R3, $BD2 */ + SystemZ_VLVGG /* 2726 */, SYSTEMZ_INS_VLVGG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSB }} + + #endif +}, +{ + /* vlvgh $V1, $R3, $BD2 */ + SystemZ_VLVGH /* 2727 */, SYSTEMZ_INS_VLVGH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSB }} + + #endif +}, +{ + /* vlvgp $V1, $R2, $R3 */ + SystemZ_VLVGP /* 2728 */, SYSTEMZ_INS_VLVGP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRF }} + + #endif +}, +{ + /* vmae $V1, $V2, $V3, $V4, $M5 */ + SystemZ_VMAE /* 2729 */, SYSTEMZ_INS_VMAE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmaeb $V1, $V2, $V3, $V4 */ + SystemZ_VMAEB /* 2730 */, SYSTEMZ_INS_VMAEB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmaef $V1, $V2, $V3, $V4 */ + SystemZ_VMAEF /* 2731 */, SYSTEMZ_INS_VMAEF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmaeh $V1, $V2, $V3, $V4 */ + SystemZ_VMAEH /* 2732 */, SYSTEMZ_INS_VMAEH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmah $V1, $V2, $V3, $V4, $M5 */ + SystemZ_VMAH /* 2733 */, SYSTEMZ_INS_VMAH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmahb $V1, $V2, $V3, $V4 */ + SystemZ_VMAHB /* 2734 */, SYSTEMZ_INS_VMAHB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmahf $V1, $V2, $V3, $V4 */ + SystemZ_VMAHF /* 2735 */, SYSTEMZ_INS_VMAHF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmahh $V1, $V2, $V3, $V4 */ + SystemZ_VMAHH /* 2736 */, SYSTEMZ_INS_VMAHH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmal $V1, $V2, $V3, $V4, $M5 */ + SystemZ_VMAL /* 2737 */, SYSTEMZ_INS_VMAL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmalb $V1, $V2, $V3, $V4 */ + SystemZ_VMALB /* 2738 */, SYSTEMZ_INS_VMALB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmale $V1, $V2, $V3, $V4, $M5 */ + SystemZ_VMALE /* 2739 */, SYSTEMZ_INS_VMALE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmaleb $V1, $V2, $V3, $V4 */ + SystemZ_VMALEB /* 2740 */, SYSTEMZ_INS_VMALEB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmalef $V1, $V2, $V3, $V4 */ + SystemZ_VMALEF /* 2741 */, SYSTEMZ_INS_VMALEF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmaleh $V1, $V2, $V3, $V4 */ + SystemZ_VMALEH /* 2742 */, SYSTEMZ_INS_VMALEH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmalf $V1, $V2, $V3, $V4 */ + SystemZ_VMALF /* 2743 */, SYSTEMZ_INS_VMALF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmalh $V1, $V2, $V3, $V4, $M5 */ + SystemZ_VMALH /* 2744 */, SYSTEMZ_INS_VMALH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmalhb $V1, $V2, $V3, $V4 */ + SystemZ_VMALHB /* 2745 */, SYSTEMZ_INS_VMALHB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmalhf $V1, $V2, $V3, $V4 */ + SystemZ_VMALHF /* 2746 */, SYSTEMZ_INS_VMALHF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmalhh $V1, $V2, $V3, $V4 */ + SystemZ_VMALHH /* 2747 */, SYSTEMZ_INS_VMALHH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmalhw $V1, $V2, $V3, $V4 */ + SystemZ_VMALHW /* 2748 */, SYSTEMZ_INS_VMALHW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmalo $V1, $V2, $V3, $V4, $M5 */ + SystemZ_VMALO /* 2749 */, SYSTEMZ_INS_VMALO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmalob $V1, $V2, $V3, $V4 */ + SystemZ_VMALOB /* 2750 */, SYSTEMZ_INS_VMALOB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmalof $V1, $V2, $V3, $V4 */ + SystemZ_VMALOF /* 2751 */, SYSTEMZ_INS_VMALOF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmaloh $V1, $V2, $V3, $V4 */ + SystemZ_VMALOH /* 2752 */, SYSTEMZ_INS_VMALOH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmao $V1, $V2, $V3, $V4, $M5 */ + SystemZ_VMAO /* 2753 */, SYSTEMZ_INS_VMAO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmaob $V1, $V2, $V3, $V4 */ + SystemZ_VMAOB /* 2754 */, SYSTEMZ_INS_VMAOB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmaof $V1, $V2, $V3, $V4 */ + SystemZ_VMAOF /* 2755 */, SYSTEMZ_INS_VMAOF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmaoh $V1, $V2, $V3, $V4 */ + SystemZ_VMAOH /* 2756 */, SYSTEMZ_INS_VMAOH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vme $V1, $V2, $V3, $M4 */ + SystemZ_VME /* 2757 */, SYSTEMZ_INS_VME, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmeb $V1, $V2, $V3 */ + SystemZ_VMEB /* 2758 */, SYSTEMZ_INS_VMEB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmef $V1, $V2, $V3 */ + SystemZ_VMEF /* 2759 */, SYSTEMZ_INS_VMEF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmeh $V1, $V2, $V3 */ + SystemZ_VMEH /* 2760 */, SYSTEMZ_INS_VMEH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmh $V1, $V2, $V3, $M4 */ + SystemZ_VMH /* 2761 */, SYSTEMZ_INS_VMH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmhb $V1, $V2, $V3 */ + SystemZ_VMHB /* 2762 */, SYSTEMZ_INS_VMHB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmhf $V1, $V2, $V3 */ + SystemZ_VMHF /* 2763 */, SYSTEMZ_INS_VMHF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmhh $V1, $V2, $V3 */ + SystemZ_VMHH /* 2764 */, SYSTEMZ_INS_VMHH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vml $V1, $V2, $V3, $M4 */ + SystemZ_VML /* 2765 */, SYSTEMZ_INS_VML, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmlb $V1, $V2, $V3 */ + SystemZ_VMLB /* 2766 */, SYSTEMZ_INS_VMLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmle $V1, $V2, $V3, $M4 */ + SystemZ_VMLE /* 2767 */, SYSTEMZ_INS_VMLE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmleb $V1, $V2, $V3 */ + SystemZ_VMLEB /* 2768 */, SYSTEMZ_INS_VMLEB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmlef $V1, $V2, $V3 */ + SystemZ_VMLEF /* 2769 */, SYSTEMZ_INS_VMLEF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmleh $V1, $V2, $V3 */ + SystemZ_VMLEH /* 2770 */, SYSTEMZ_INS_VMLEH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmlf $V1, $V2, $V3 */ + SystemZ_VMLF /* 2771 */, SYSTEMZ_INS_VMLF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmlh $V1, $V2, $V3, $M4 */ + SystemZ_VMLH /* 2772 */, SYSTEMZ_INS_VMLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmlhb $V1, $V2, $V3 */ + SystemZ_VMLHB /* 2773 */, SYSTEMZ_INS_VMLHB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmlhf $V1, $V2, $V3 */ + SystemZ_VMLHF /* 2774 */, SYSTEMZ_INS_VMLHF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmlhh $V1, $V2, $V3 */ + SystemZ_VMLHH /* 2775 */, SYSTEMZ_INS_VMLHH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmlhw $V1, $V2, $V3 */ + SystemZ_VMLHW /* 2776 */, SYSTEMZ_INS_VMLHW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmlo $V1, $V2, $V3, $M4 */ + SystemZ_VMLO /* 2777 */, SYSTEMZ_INS_VMLO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmlob $V1, $V2, $V3 */ + SystemZ_VMLOB /* 2778 */, SYSTEMZ_INS_VMLOB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmlof $V1, $V2, $V3 */ + SystemZ_VMLOF /* 2779 */, SYSTEMZ_INS_VMLOF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmloh $V1, $V2, $V3 */ + SystemZ_VMLOH /* 2780 */, SYSTEMZ_INS_VMLOH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmn $V1, $V2, $V3, $M4 */ + SystemZ_VMN /* 2781 */, SYSTEMZ_INS_VMN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmnb $V1, $V2, $V3 */ + SystemZ_VMNB /* 2782 */, SYSTEMZ_INS_VMNB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmnf $V1, $V2, $V3 */ + SystemZ_VMNF /* 2783 */, SYSTEMZ_INS_VMNF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmng $V1, $V2, $V3 */ + SystemZ_VMNG /* 2784 */, SYSTEMZ_INS_VMNG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmnh $V1, $V2, $V3 */ + SystemZ_VMNH /* 2785 */, SYSTEMZ_INS_VMNH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmnl $V1, $V2, $V3, $M4 */ + SystemZ_VMNL /* 2786 */, SYSTEMZ_INS_VMNL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmnlb $V1, $V2, $V3 */ + SystemZ_VMNLB /* 2787 */, SYSTEMZ_INS_VMNLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmnlf $V1, $V2, $V3 */ + SystemZ_VMNLF /* 2788 */, SYSTEMZ_INS_VMNLF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmnlg $V1, $V2, $V3 */ + SystemZ_VMNLG /* 2789 */, SYSTEMZ_INS_VMNLG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmnlh $V1, $V2, $V3 */ + SystemZ_VMNLH /* 2790 */, SYSTEMZ_INS_VMNLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmo $V1, $V2, $V3, $M4 */ + SystemZ_VMO /* 2791 */, SYSTEMZ_INS_VMO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmob $V1, $V2, $V3 */ + SystemZ_VMOB /* 2792 */, SYSTEMZ_INS_VMOB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmof $V1, $V2, $V3 */ + SystemZ_VMOF /* 2793 */, SYSTEMZ_INS_VMOF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmoh $V1, $V2, $V3 */ + SystemZ_VMOH /* 2794 */, SYSTEMZ_INS_VMOH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmp $V1, $V2, $V3, $I4, $M5 */ + SystemZ_VMP /* 2795 */, SYSTEMZ_INS_VMP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIF }} + + #endif +}, +{ + /* vmrh $V1, $V2, $V3, $M4 */ + SystemZ_VMRH /* 2796 */, SYSTEMZ_INS_VMRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmrhb $V1, $V2, $V3 */ + SystemZ_VMRHB /* 2797 */, SYSTEMZ_INS_VMRHB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmrhf $V1, $V2, $V3 */ + SystemZ_VMRHF /* 2798 */, SYSTEMZ_INS_VMRHF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmrhg $V1, $V2, $V3 */ + SystemZ_VMRHG /* 2799 */, SYSTEMZ_INS_VMRHG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmrhh $V1, $V2, $V3 */ + SystemZ_VMRHH /* 2800 */, SYSTEMZ_INS_VMRHH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmrl $V1, $V2, $V3, $M4 */ + SystemZ_VMRL /* 2801 */, SYSTEMZ_INS_VMRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmrlb $V1, $V2, $V3 */ + SystemZ_VMRLB /* 2802 */, SYSTEMZ_INS_VMRLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmrlf $V1, $V2, $V3 */ + SystemZ_VMRLF /* 2803 */, SYSTEMZ_INS_VMRLF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmrlg $V1, $V2, $V3 */ + SystemZ_VMRLG /* 2804 */, SYSTEMZ_INS_VMRLG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmrlh $V1, $V2, $V3 */ + SystemZ_VMRLH /* 2805 */, SYSTEMZ_INS_VMRLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmsl $V1, $V2, $V3, $V4, $M5, $M6 */ + SystemZ_VMSL /* 2806 */, SYSTEMZ_INS_VMSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmslg $V1, $V2, $V3, $V4, $M6 */ + SystemZ_VMSLG /* 2807 */, SYSTEMZ_INS_VMSLG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vmsp $V1, $V2, $V3, $I4, $M5 */ + SystemZ_VMSP /* 2808 */, SYSTEMZ_INS_VMSP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIF }} + + #endif +}, +{ + /* vmx $V1, $V2, $V3, $M4 */ + SystemZ_VMX /* 2809 */, SYSTEMZ_INS_VMX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmxb $V1, $V2, $V3 */ + SystemZ_VMXB /* 2810 */, SYSTEMZ_INS_VMXB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmxf $V1, $V2, $V3 */ + SystemZ_VMXF /* 2811 */, SYSTEMZ_INS_VMXF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmxg $V1, $V2, $V3 */ + SystemZ_VMXG /* 2812 */, SYSTEMZ_INS_VMXG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmxh $V1, $V2, $V3 */ + SystemZ_VMXH /* 2813 */, SYSTEMZ_INS_VMXH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmxl $V1, $V2, $V3, $M4 */ + SystemZ_VMXL /* 2814 */, SYSTEMZ_INS_VMXL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmxlb $V1, $V2, $V3 */ + SystemZ_VMXLB /* 2815 */, SYSTEMZ_INS_VMXLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmxlf $V1, $V2, $V3 */ + SystemZ_VMXLF /* 2816 */, SYSTEMZ_INS_VMXLF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmxlg $V1, $V2, $V3 */ + SystemZ_VMXLG /* 2817 */, SYSTEMZ_INS_VMXLG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vmxlh $V1, $V2, $V3 */ + SystemZ_VMXLH /* 2818 */, SYSTEMZ_INS_VMXLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vn $V1, $V2, $V3 */ + SystemZ_VN /* 2819 */, SYSTEMZ_INS_VN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vnc $V1, $V2, $V3 */ + SystemZ_VNC /* 2820 */, SYSTEMZ_INS_VNC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vnn $V1, $V2, $V3 */ + SystemZ_VNN /* 2821 */, SYSTEMZ_INS_VNN, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vno $V1, $V2, $V3 */ + SystemZ_VNO /* 2822 */, SYSTEMZ_INS_VNO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vnx $V1, $V2, $V3 */ + SystemZ_VNX /* 2823 */, SYSTEMZ_INS_VNX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vo $V1, $V2, $V3 */ + SystemZ_VO /* 2824 */, SYSTEMZ_INS_VO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* voc $V1, $V2, $V3 */ + SystemZ_VOC /* 2825 */, SYSTEMZ_INS_VOC, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vone $V1 */ + SystemZ_VONE /* 2826 */, SYSTEMZ_INS_VONE, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIA }} + + #endif +}, +{ + /* vpdi $V1, $V2, $V3, $M4 */ + SystemZ_VPDI /* 2827 */, SYSTEMZ_INS_VPDI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vperm $V1, $V2, $V3, $V4 */ + SystemZ_VPERM /* 2828 */, SYSTEMZ_INS_VPERM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* vpk $V1, $V2, $V3, $M4 */ + SystemZ_VPK /* 2829 */, SYSTEMZ_INS_VPK, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vpkf $V1, $V2, $V3 */ + SystemZ_VPKF /* 2830 */, SYSTEMZ_INS_VPKF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vpkg $V1, $V2, $V3 */ + SystemZ_VPKG /* 2831 */, SYSTEMZ_INS_VPKG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vpkh $V1, $V2, $V3 */ + SystemZ_VPKH /* 2832 */, SYSTEMZ_INS_VPKH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vpkls $V1, $V2, $V3, $M4, $M5 */ + SystemZ_VPKLS /* 2833 */, SYSTEMZ_INS_VPKLS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vpklsf $V1, $V2, $V3 */ + SystemZ_VPKLSF /* 2834 */, SYSTEMZ_INS_VPKLSF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vpklsfs $V1, $V2, $V3 */ + SystemZ_VPKLSFS /* 2835 */, SYSTEMZ_INS_VPKLSFS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vpklsg $V1, $V2, $V3 */ + SystemZ_VPKLSG /* 2836 */, SYSTEMZ_INS_VPKLSG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vpklsgs $V1, $V2, $V3 */ + SystemZ_VPKLSGS /* 2837 */, SYSTEMZ_INS_VPKLSGS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vpklsh $V1, $V2, $V3 */ + SystemZ_VPKLSH /* 2838 */, SYSTEMZ_INS_VPKLSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vpklshs $V1, $V2, $V3 */ + SystemZ_VPKLSHS /* 2839 */, SYSTEMZ_INS_VPKLSHS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vpks $V1, $V2, $V3, $M4, $M5 */ + SystemZ_VPKS /* 2840 */, SYSTEMZ_INS_VPKS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vpksf $V1, $V2, $V3 */ + SystemZ_VPKSF /* 2841 */, SYSTEMZ_INS_VPKSF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vpksfs $V1, $V2, $V3 */ + SystemZ_VPKSFS /* 2842 */, SYSTEMZ_INS_VPKSFS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vpksg $V1, $V2, $V3 */ + SystemZ_VPKSG /* 2843 */, SYSTEMZ_INS_VPKSG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vpksgs $V1, $V2, $V3 */ + SystemZ_VPKSGS /* 2844 */, SYSTEMZ_INS_VPKSGS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vpksh $V1, $V2, $V3 */ + SystemZ_VPKSH /* 2845 */, SYSTEMZ_INS_VPKSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vpkshs $V1, $V2, $V3 */ + SystemZ_VPKSHS /* 2846 */, SYSTEMZ_INS_VPKSHS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vpkz $V1, $BD2, $I3 */ + SystemZ_VPKZ /* 2847 */, SYSTEMZ_INS_VPKZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVSI }} + + #endif +}, +{ + /* vpkzr $V1, $V2, $V3, $I4, $M5 */ + SystemZ_VPKZR /* 2848 */, SYSTEMZ_INS_VPKZR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIF }} + + #endif +}, +{ + /* vpopct $V1, $V2, $M3 */ + SystemZ_VPOPCT /* 2849 */, SYSTEMZ_INS_VPOPCT, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vpopctb $V1, $V2 */ + SystemZ_VPOPCTB /* 2850 */, SYSTEMZ_INS_VPOPCTB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vpopctf $V1, $V2 */ + SystemZ_VPOPCTF /* 2851 */, SYSTEMZ_INS_VPOPCTF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vpopctg $V1, $V2 */ + SystemZ_VPOPCTG /* 2852 */, SYSTEMZ_INS_VPOPCTG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vpopcth $V1, $V2 */ + SystemZ_VPOPCTH /* 2853 */, SYSTEMZ_INS_VPOPCTH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vpsop $V1, $V2, $I3, $I4, $M5 */ + SystemZ_VPSOP /* 2854 */, SYSTEMZ_INS_VPSOP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIG }} + + #endif +}, +{ + /* vrep $V1, $V3, $I2, $M4 */ + SystemZ_VREP /* 2855 */, SYSTEMZ_INS_VREP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIC }} + + #endif +}, +{ + /* vrepb $V1, $V3, $I2 */ + SystemZ_VREPB /* 2856 */, SYSTEMZ_INS_VREPB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIC }} + + #endif +}, +{ + /* vrepf $V1, $V3, $I2 */ + SystemZ_VREPF /* 2857 */, SYSTEMZ_INS_VREPF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIC }} + + #endif +}, +{ + /* vrepg $V1, $V3, $I2 */ + SystemZ_VREPG /* 2858 */, SYSTEMZ_INS_VREPG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIC }} + + #endif +}, +{ + /* vreph $V1, $V3, $I2 */ + SystemZ_VREPH /* 2859 */, SYSTEMZ_INS_VREPH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIC }} + + #endif +}, +{ + /* vrepi $V1, $I2, $M3 */ + SystemZ_VREPI /* 2860 */, SYSTEMZ_INS_VREPI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIA }} + + #endif +}, +{ + /* vrepib $V1, $I2 */ + SystemZ_VREPIB /* 2861 */, SYSTEMZ_INS_VREPIB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIA }} + + #endif +}, +{ + /* vrepif $V1, $I2 */ + SystemZ_VREPIF /* 2862 */, SYSTEMZ_INS_VREPIF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIA }} + + #endif +}, +{ + /* vrepig $V1, $I2 */ + SystemZ_VREPIG /* 2863 */, SYSTEMZ_INS_VREPIG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIA }} + + #endif +}, +{ + /* vrepih $V1, $I2 */ + SystemZ_VREPIH /* 2864 */, SYSTEMZ_INS_VREPIH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIA }} + + #endif +}, +{ + /* vrp $V1, $V2, $V3, $I4, $M5 */ + SystemZ_VRP /* 2865 */, SYSTEMZ_INS_VRP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIF }} + + #endif +}, +{ + /* vs $V1, $V2, $V3, $M4 */ + SystemZ_VS /* 2866 */, SYSTEMZ_INS_VS, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vsb $V1, $V2, $V3 */ + SystemZ_VSB /* 2867 */, SYSTEMZ_INS_VSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vsbcbi $V1, $V2, $V3, $V4, $M5 */ + SystemZ_VSBCBI /* 2868 */, SYSTEMZ_INS_VSBCBI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vsbcbiq $V1, $V2, $V3, $V4 */ + SystemZ_VSBCBIQ /* 2869 */, SYSTEMZ_INS_VSBCBIQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vsbi $V1, $V2, $V3, $V4, $M5 */ + SystemZ_VSBI /* 2870 */, SYSTEMZ_INS_VSBI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vsbiq $V1, $V2, $V3, $V4 */ + SystemZ_VSBIQ /* 2871 */, SYSTEMZ_INS_VSBIQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vscbi $V1, $V2, $V3, $M4 */ + SystemZ_VSCBI /* 2872 */, SYSTEMZ_INS_VSCBI, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vscbib $V1, $V2, $V3 */ + SystemZ_VSCBIB /* 2873 */, SYSTEMZ_INS_VSCBIB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vscbif $V1, $V2, $V3 */ + SystemZ_VSCBIF /* 2874 */, SYSTEMZ_INS_VSCBIF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vscbig $V1, $V2, $V3 */ + SystemZ_VSCBIG /* 2875 */, SYSTEMZ_INS_VSCBIG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vscbih $V1, $V2, $V3 */ + SystemZ_VSCBIH /* 2876 */, SYSTEMZ_INS_VSCBIH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vscbiq $V1, $V2, $V3 */ + SystemZ_VSCBIQ /* 2877 */, SYSTEMZ_INS_VSCBIQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vscef $V1, $VBD2, $M3 */ + SystemZ_VSCEF /* 2878 */, SYSTEMZ_INS_VSCEF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRV }} + + #endif +}, +{ + /* vsceg $V1, $VBD2, $M3 */ + SystemZ_VSCEG /* 2879 */, SYSTEMZ_INS_VSCEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRV }} + + #endif +}, +{ + /* vschdp $V1, $V2, $V3, $M5 */ + SystemZ_VSCHDP /* 2880 */, SYSTEMZ_INS_VSCHDP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vschp $V1, $V2, $V3, $M4, $M5 */ + SystemZ_VSCHP /* 2881 */, SYSTEMZ_INS_VSCHP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vschsp $V1, $V2, $V3, $M5 */ + SystemZ_VSCHSP /* 2882 */, SYSTEMZ_INS_VSCHSP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vschxp $V1, $V2, $V3, $M5 */ + SystemZ_VSCHXP /* 2883 */, SYSTEMZ_INS_VSCHXP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vscshp $V1, $V2, $V3 */ + SystemZ_VSCSHP /* 2884 */, SYSTEMZ_INS_VSCSHP, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRB }} + + #endif +}, +{ + /* vsdp $V1, $V2, $V3, $I4, $M5 */ + SystemZ_VSDP /* 2885 */, SYSTEMZ_INS_VSDP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIF }} + + #endif +}, +{ + /* vseg $V1, $V2, $M3 */ + SystemZ_VSEG /* 2886 */, SYSTEMZ_INS_VSEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vsegb $V1, $V2 */ + SystemZ_VSEGB /* 2887 */, SYSTEMZ_INS_VSEGB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vsegf $V1, $V2 */ + SystemZ_VSEGF /* 2888 */, SYSTEMZ_INS_VSEGF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vsegh $V1, $V2 */ + SystemZ_VSEGH /* 2889 */, SYSTEMZ_INS_VSEGH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vsel $V1, $V2, $V3, $V4 */ + SystemZ_VSEL /* 2890 */, SYSTEMZ_INS_VSEL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* vsf $V1, $V2, $V3 */ + SystemZ_VSF /* 2891 */, SYSTEMZ_INS_VSF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vsg $V1, $V2, $V3 */ + SystemZ_VSG /* 2892 */, SYSTEMZ_INS_VSG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vsh $V1, $V2, $V3 */ + SystemZ_VSH /* 2893 */, SYSTEMZ_INS_VSH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vsl $V1, $V2, $V3 */ + SystemZ_VSL /* 2894 */, SYSTEMZ_INS_VSL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vslb $V1, $V2, $V3 */ + SystemZ_VSLB /* 2895 */, SYSTEMZ_INS_VSLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vsld $V1, $V2, $V3, $I4 */ + SystemZ_VSLD /* 2896 */, SYSTEMZ_INS_VSLD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRID }} + + #endif +}, +{ + /* vsldb $V1, $V2, $V3, $I4 */ + SystemZ_VSLDB /* 2897 */, SYSTEMZ_INS_VSLDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRID }} + + #endif +}, +{ + /* vsp $V1, $V2, $V3, $I4, $M5 */ + SystemZ_VSP /* 2898 */, SYSTEMZ_INS_VSP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIF }} + + #endif +}, +{ + /* vsq $V1, $V2, $V3 */ + SystemZ_VSQ /* 2899 */, SYSTEMZ_INS_VSQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vsra $V1, $V2, $V3 */ + SystemZ_VSRA /* 2900 */, SYSTEMZ_INS_VSRA, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vsrab $V1, $V2, $V3 */ + SystemZ_VSRAB /* 2901 */, SYSTEMZ_INS_VSRAB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vsrd $V1, $V2, $V3, $I4 */ + SystemZ_VSRD /* 2902 */, SYSTEMZ_INS_VSRD, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRID }} + + #endif +}, +{ + /* vsrl $V1, $V2, $V3 */ + SystemZ_VSRL /* 2903 */, SYSTEMZ_INS_VSRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vsrlb $V1, $V2, $V3 */ + SystemZ_VSRLB /* 2904 */, SYSTEMZ_INS_VSRLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vsrp $V1, $V2, $I3, $I4, $M5 */ + SystemZ_VSRP /* 2905 */, SYSTEMZ_INS_VSRP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIG }} + + #endif +}, +{ + /* vsrpr $V1, $V2, $V3, $I4, $M5 */ + SystemZ_VSRPR /* 2906 */, SYSTEMZ_INS_VSRPR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIF }} + + #endif +}, +{ + /* vst $V1, $XBD2 */ + SystemZ_VST /* 2907 */, SYSTEMZ_INS_VST, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vst $V1, $XBD2, $M3 */ + SystemZ_VSTAlign /* 2908 */, SYSTEMZ_INS_VST, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vstbr $V1, $XBD2, $M3 */ + SystemZ_VSTBR /* 2909 */, SYSTEMZ_INS_VSTBR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vstbrf $V1, $XBD2 */ + SystemZ_VSTBRF /* 2910 */, SYSTEMZ_INS_VSTBRF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vstbrg $V1, $XBD2 */ + SystemZ_VSTBRG /* 2911 */, SYSTEMZ_INS_VSTBRG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vstbrh $V1, $XBD2 */ + SystemZ_VSTBRH /* 2912 */, SYSTEMZ_INS_VSTBRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vstbrq $V1, $XBD2 */ + SystemZ_VSTBRQ /* 2913 */, SYSTEMZ_INS_VSTBRQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vsteb $V1, $XBD2, $M3 */ + SystemZ_VSTEB /* 2914 */, SYSTEMZ_INS_VSTEB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vstebrf $V1, $XBD2, $M3 */ + SystemZ_VSTEBRF /* 2915 */, SYSTEMZ_INS_VSTEBRF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vstebrg $V1, $XBD2, $M3 */ + SystemZ_VSTEBRG /* 2916 */, SYSTEMZ_INS_VSTEBRG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vstebrh $V1, $XBD2, $M3 */ + SystemZ_VSTEBRH /* 2917 */, SYSTEMZ_INS_VSTEBRH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vstef $V1, $XBD2, $M3 */ + SystemZ_VSTEF /* 2918 */, SYSTEMZ_INS_VSTEF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vsteg $V1, $XBD2, $M3 */ + SystemZ_VSTEG /* 2919 */, SYSTEMZ_INS_VSTEG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vsteh $V1, $XBD2, $M3 */ + SystemZ_VSTEH /* 2920 */, SYSTEMZ_INS_VSTEH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vster $V1, $XBD2, $M3 */ + SystemZ_VSTER /* 2921 */, SYSTEMZ_INS_VSTER, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vsterf $V1, $XBD2 */ + SystemZ_VSTERF /* 2922 */, SYSTEMZ_INS_VSTERF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vsterg $V1, $XBD2 */ + SystemZ_VSTERG /* 2923 */, SYSTEMZ_INS_VSTERG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vsterh $V1, $XBD2 */ + SystemZ_VSTERH /* 2924 */, SYSTEMZ_INS_VSTERH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRX }} + + #endif +}, +{ + /* vstl $V1, $R3, $BD2 */ + SystemZ_VSTL /* 2925 */, SYSTEMZ_INS_VSTL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSB }} + + #endif +}, +{ + /* vstm $V1, $V3, $BD2 */ + SystemZ_VSTM /* 2926 */, SYSTEMZ_INS_VSTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* vstm $V1, $V3, $BD2, $M4 */ + SystemZ_VSTMAlign /* 2927 */, SYSTEMZ_INS_VSTM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSA }} + + #endif +}, +{ + /* vstrc $V1, $V2, $V3, $V4, $M5, $M6 */ + SystemZ_VSTRC /* 2928 */, SYSTEMZ_INS_VSTRC, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vstrcb $V1, $V2, $V3, $V4, $M6 */ + SystemZ_VSTRCB /* 2929 */, SYSTEMZ_INS_VSTRCB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vstrcbs $V1, $V2, $V3, $V4, $M6 */ + SystemZ_VSTRCBS /* 2930 */, SYSTEMZ_INS_VSTRCBS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vstrcf $V1, $V2, $V3, $V4, $M6 */ + SystemZ_VSTRCF /* 2931 */, SYSTEMZ_INS_VSTRCF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vstrcfs $V1, $V2, $V3, $V4, $M6 */ + SystemZ_VSTRCFS /* 2932 */, SYSTEMZ_INS_VSTRCFS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vstrch $V1, $V2, $V3, $V4, $M6 */ + SystemZ_VSTRCH /* 2933 */, SYSTEMZ_INS_VSTRCH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vstrchs $V1, $V2, $V3, $V4, $M6 */ + SystemZ_VSTRCHS /* 2934 */, SYSTEMZ_INS_VSTRCHS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vstrczb $V1, $V2, $V3, $V4, $M6 */ + SystemZ_VSTRCZB /* 2935 */, SYSTEMZ_INS_VSTRCZB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vstrczbs $V1, $V2, $V3, $V4, $M6 */ + SystemZ_VSTRCZBS /* 2936 */, SYSTEMZ_INS_VSTRCZBS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vstrczf $V1, $V2, $V3, $V4, $M6 */ + SystemZ_VSTRCZF /* 2937 */, SYSTEMZ_INS_VSTRCZF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vstrczfs $V1, $V2, $V3, $V4, $M6 */ + SystemZ_VSTRCZFS /* 2938 */, SYSTEMZ_INS_VSTRCZFS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vstrczh $V1, $V2, $V3, $V4, $M6 */ + SystemZ_VSTRCZH /* 2939 */, SYSTEMZ_INS_VSTRCZH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vstrczhs $V1, $V2, $V3, $V4, $M6 */ + SystemZ_VSTRCZHS /* 2940 */, SYSTEMZ_INS_VSTRCZHS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vstrl $V1, $BD2, $I3 */ + SystemZ_VSTRL /* 2941 */, SYSTEMZ_INS_VSTRL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVSI }} + + #endif +}, +{ + /* vstrlr $V1, $R3, $BD2 */ + SystemZ_VSTRLR /* 2942 */, SYSTEMZ_INS_VSTRLR, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRSD }} + + #endif +}, +{ + /* vstrs $V1, $V2, $V3, $V4, $M5, $M6 */ + SystemZ_VSTRS /* 2943 */, SYSTEMZ_INS_VSTRS, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vstrsb $V1, $V2, $V3, $V4, $M6 */ + SystemZ_VSTRSB /* 2944 */, SYSTEMZ_INS_VSTRSB, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vstrsf $V1, $V2, $V3, $V4, $M6 */ + SystemZ_VSTRSF /* 2945 */, SYSTEMZ_INS_VSTRSF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vstrsh $V1, $V2, $V3, $V4, $M6 */ + SystemZ_VSTRSH /* 2946 */, SYSTEMZ_INS_VSTRSH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vstrszb $V1, $V2, $V3, $V4 */ + SystemZ_VSTRSZB /* 2947 */, SYSTEMZ_INS_VSTRSZB, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vstrszf $V1, $V2, $V3, $V4 */ + SystemZ_VSTRSZF /* 2948 */, SYSTEMZ_INS_VSTRSZF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vstrszh $V1, $V2, $V3, $V4 */ + SystemZ_VSTRSZH /* 2949 */, SYSTEMZ_INS_VSTRSZH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRD }} + + #endif +}, +{ + /* vsum $V1, $V2, $V3, $M4 */ + SystemZ_VSUM /* 2950 */, SYSTEMZ_INS_VSUM, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vsumb $V1, $V2, $V3 */ + SystemZ_VSUMB /* 2951 */, SYSTEMZ_INS_VSUMB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vsumg $V1, $V2, $V3, $M4 */ + SystemZ_VSUMG /* 2952 */, SYSTEMZ_INS_VSUMG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vsumgf $V1, $V2, $V3 */ + SystemZ_VSUMGF /* 2953 */, SYSTEMZ_INS_VSUMGF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vsumgh $V1, $V2, $V3 */ + SystemZ_VSUMGH /* 2954 */, SYSTEMZ_INS_VSUMGH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vsumh $V1, $V2, $V3 */ + SystemZ_VSUMH /* 2955 */, SYSTEMZ_INS_VSUMH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vsumq $V1, $V2, $V3, $M4 */ + SystemZ_VSUMQ /* 2956 */, SYSTEMZ_INS_VSUMQ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vsumqf $V1, $V2, $V3 */ + SystemZ_VSUMQF /* 2957 */, SYSTEMZ_INS_VSUMQF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vsumqg $V1, $V2, $V3 */ + SystemZ_VSUMQG /* 2958 */, SYSTEMZ_INS_VSUMQG, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vtm $V1, $V2 */ + SystemZ_VTM /* 2959 */, SYSTEMZ_INS_VTM, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vtp $V1 */ + SystemZ_VTP /* 2960 */, SYSTEMZ_INS_VTP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRG }} + + #endif +}, +{ + /* vuph $V1, $V2, $M3 */ + SystemZ_VUPH /* 2961 */, SYSTEMZ_INS_VUPH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vuphb $V1, $V2 */ + SystemZ_VUPHB /* 2962 */, SYSTEMZ_INS_VUPHB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vuphf $V1, $V2 */ + SystemZ_VUPHF /* 2963 */, SYSTEMZ_INS_VUPHF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vuphh $V1, $V2 */ + SystemZ_VUPHH /* 2964 */, SYSTEMZ_INS_VUPHH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vupkz $V1, $BD2, $I3 */ + SystemZ_VUPKZ /* 2965 */, SYSTEMZ_INS_VUPKZ, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVSI }} + + #endif +}, +{ + /* vupkzh $V1, $V2, $M3 */ + SystemZ_VUPKZH /* 2966 */, SYSTEMZ_INS_VUPKZH, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRK }} + + #endif +}, +{ + /* vupkzl $V1, $V2, $M3 */ + SystemZ_VUPKZL /* 2967 */, SYSTEMZ_INS_VUPKZL, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRK }} + + #endif +}, +{ + /* vupl $V1, $V2, $M3 */ + SystemZ_VUPL /* 2968 */, SYSTEMZ_INS_VUPL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vuplb $V1, $V2 */ + SystemZ_VUPLB /* 2969 */, SYSTEMZ_INS_VUPLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vuplf $V1, $V2 */ + SystemZ_VUPLF /* 2970 */, SYSTEMZ_INS_VUPLF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vuplh $V1, $V2, $M3 */ + SystemZ_VUPLH /* 2971 */, SYSTEMZ_INS_VUPLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vuplhb $V1, $V2 */ + SystemZ_VUPLHB /* 2972 */, SYSTEMZ_INS_VUPLHB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vuplhf $V1, $V2 */ + SystemZ_VUPLHF /* 2973 */, SYSTEMZ_INS_VUPLHF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vuplhh $V1, $V2 */ + SystemZ_VUPLHH /* 2974 */, SYSTEMZ_INS_VUPLHH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vuplhw $V1, $V2 */ + SystemZ_VUPLHW /* 2975 */, SYSTEMZ_INS_VUPLHW, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vupll $V1, $V2, $M3 */ + SystemZ_VUPLL /* 2976 */, SYSTEMZ_INS_VUPLL, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vupllb $V1, $V2 */ + SystemZ_VUPLLB /* 2977 */, SYSTEMZ_INS_VUPLLB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vupllf $V1, $V2 */ + SystemZ_VUPLLF /* 2978 */, SYSTEMZ_INS_VUPLLF, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vupllh $V1, $V2 */ + SystemZ_VUPLLH /* 2979 */, SYSTEMZ_INS_VUPLLH, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* vx $V1, $V2, $V3 */ + SystemZ_VX /* 2980 */, SYSTEMZ_INS_VX, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* vzero $V1 */ + SystemZ_VZERO /* 2981 */, SYSTEMZ_INS_VZERO, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIA }} + + #endif +}, +{ + /* wcdgb $V1, $V2, $M4, $M5 */ + SystemZ_WCDGB /* 2982 */, SYSTEMZ_INS_WCDGB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wcdlgb $V1, $V2, $M4, $M5 */ + SystemZ_WCDLGB /* 2983 */, SYSTEMZ_INS_WCDLGB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wcefb $V1, $V2, $M4, $M5 */ + SystemZ_WCEFB /* 2984 */, SYSTEMZ_INS_WCEFB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wcelfb $V1, $V2, $M4, $M5 */ + SystemZ_WCELFB /* 2985 */, SYSTEMZ_INS_WCELFB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wcfeb $V1, $V2, $M4, $M5 */ + SystemZ_WCFEB /* 2986 */, SYSTEMZ_INS_WCFEB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wcgdb $V1, $V2, $M4, $M5 */ + SystemZ_WCGDB /* 2987 */, SYSTEMZ_INS_WCGDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wclfeb $V1, $V2, $M4, $M5 */ + SystemZ_WCLFEB /* 2988 */, SYSTEMZ_INS_WCLFEB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wclgdb $V1, $V2, $M4, $M5 */ + SystemZ_WCLGDB /* 2989 */, SYSTEMZ_INS_WCLGDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wfadb $V1, $V2, $V3 */ + SystemZ_WFADB /* 2990 */, SYSTEMZ_INS_WFADB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfasb $V1, $V2, $V3 */ + SystemZ_WFASB /* 2991 */, SYSTEMZ_INS_WFASB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfaxb $V1, $V2, $V3 */ + SystemZ_WFAXB /* 2992 */, SYSTEMZ_INS_WFAXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfc $V1, $V2, $M3, $M4 */ + SystemZ_WFC /* 2993 */, SYSTEMZ_INS_WFC, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wfcdb $V1, $V2 */ + SystemZ_WFCDB /* 2994 */, SYSTEMZ_INS_WFCDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wfcedb $V1, $V2, $V3 */ + SystemZ_WFCEDB /* 2995 */, SYSTEMZ_INS_WFCEDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfcedbs $V1, $V2, $V3 */ + SystemZ_WFCEDBS /* 2996 */, SYSTEMZ_INS_WFCEDBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfcesb $V1, $V2, $V3 */ + SystemZ_WFCESB /* 2997 */, SYSTEMZ_INS_WFCESB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfcesbs $V1, $V2, $V3 */ + SystemZ_WFCESBS /* 2998 */, SYSTEMZ_INS_WFCESBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfcexb $V1, $V2, $V3 */ + SystemZ_WFCEXB /* 2999 */, SYSTEMZ_INS_WFCEXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfcexbs $V1, $V2, $V3 */ + SystemZ_WFCEXBS /* 3000 */, SYSTEMZ_INS_WFCEXBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfchdb $V1, $V2, $V3 */ + SystemZ_WFCHDB /* 3001 */, SYSTEMZ_INS_WFCHDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfchdbs $V1, $V2, $V3 */ + SystemZ_WFCHDBS /* 3002 */, SYSTEMZ_INS_WFCHDBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfchedb $V1, $V2, $V3 */ + SystemZ_WFCHEDB /* 3003 */, SYSTEMZ_INS_WFCHEDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfchedbs $V1, $V2, $V3 */ + SystemZ_WFCHEDBS /* 3004 */, SYSTEMZ_INS_WFCHEDBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfchesb $V1, $V2, $V3 */ + SystemZ_WFCHESB /* 3005 */, SYSTEMZ_INS_WFCHESB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfchesbs $V1, $V2, $V3 */ + SystemZ_WFCHESBS /* 3006 */, SYSTEMZ_INS_WFCHESBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfchexb $V1, $V2, $V3 */ + SystemZ_WFCHEXB /* 3007 */, SYSTEMZ_INS_WFCHEXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfchexbs $V1, $V2, $V3 */ + SystemZ_WFCHEXBS /* 3008 */, SYSTEMZ_INS_WFCHEXBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfchsb $V1, $V2, $V3 */ + SystemZ_WFCHSB /* 3009 */, SYSTEMZ_INS_WFCHSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfchsbs $V1, $V2, $V3 */ + SystemZ_WFCHSBS /* 3010 */, SYSTEMZ_INS_WFCHSBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfchxb $V1, $V2, $V3 */ + SystemZ_WFCHXB /* 3011 */, SYSTEMZ_INS_WFCHXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfchxbs $V1, $V2, $V3 */ + SystemZ_WFCHXBS /* 3012 */, SYSTEMZ_INS_WFCHXBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfcsb $V1, $V2 */ + SystemZ_WFCSB /* 3013 */, SYSTEMZ_INS_WFCSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wfcxb $V1, $V2 */ + SystemZ_WFCXB /* 3014 */, SYSTEMZ_INS_WFCXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wfddb $V1, $V2, $V3 */ + SystemZ_WFDDB /* 3015 */, SYSTEMZ_INS_WFDDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfdsb $V1, $V2, $V3 */ + SystemZ_WFDSB /* 3016 */, SYSTEMZ_INS_WFDSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfdxb $V1, $V2, $V3 */ + SystemZ_WFDXB /* 3017 */, SYSTEMZ_INS_WFDXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfidb $V1, $V2, $M4, $M5 */ + SystemZ_WFIDB /* 3018 */, SYSTEMZ_INS_WFIDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wfisb $V1, $V2, $M4, $M5 */ + SystemZ_WFISB /* 3019 */, SYSTEMZ_INS_WFISB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wfixb $V1, $V2, $M4, $M5 */ + SystemZ_WFIXB /* 3020 */, SYSTEMZ_INS_WFIXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wfk $V1, $V2, $M3, $M4 */ + SystemZ_WFK /* 3021 */, SYSTEMZ_INS_WFK, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wfkdb $V1, $V2 */ + SystemZ_WFKDB /* 3022 */, SYSTEMZ_INS_WFKDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wfkedb $V1, $V2, $V3 */ + SystemZ_WFKEDB /* 3023 */, SYSTEMZ_INS_WFKEDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfkedbs $V1, $V2, $V3 */ + SystemZ_WFKEDBS /* 3024 */, SYSTEMZ_INS_WFKEDBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfkesb $V1, $V2, $V3 */ + SystemZ_WFKESB /* 3025 */, SYSTEMZ_INS_WFKESB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfkesbs $V1, $V2, $V3 */ + SystemZ_WFKESBS /* 3026 */, SYSTEMZ_INS_WFKESBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfkexb $V1, $V2, $V3 */ + SystemZ_WFKEXB /* 3027 */, SYSTEMZ_INS_WFKEXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfkexbs $V1, $V2, $V3 */ + SystemZ_WFKEXBS /* 3028 */, SYSTEMZ_INS_WFKEXBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfkhdb $V1, $V2, $V3 */ + SystemZ_WFKHDB /* 3029 */, SYSTEMZ_INS_WFKHDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfkhdbs $V1, $V2, $V3 */ + SystemZ_WFKHDBS /* 3030 */, SYSTEMZ_INS_WFKHDBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfkhedb $V1, $V2, $V3 */ + SystemZ_WFKHEDB /* 3031 */, SYSTEMZ_INS_WFKHEDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfkhedbs $V1, $V2, $V3 */ + SystemZ_WFKHEDBS /* 3032 */, SYSTEMZ_INS_WFKHEDBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfkhesb $V1, $V2, $V3 */ + SystemZ_WFKHESB /* 3033 */, SYSTEMZ_INS_WFKHESB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfkhesbs $V1, $V2, $V3 */ + SystemZ_WFKHESBS /* 3034 */, SYSTEMZ_INS_WFKHESBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfkhexb $V1, $V2, $V3 */ + SystemZ_WFKHEXB /* 3035 */, SYSTEMZ_INS_WFKHEXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfkhexbs $V1, $V2, $V3 */ + SystemZ_WFKHEXBS /* 3036 */, SYSTEMZ_INS_WFKHEXBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfkhsb $V1, $V2, $V3 */ + SystemZ_WFKHSB /* 3037 */, SYSTEMZ_INS_WFKHSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfkhsbs $V1, $V2, $V3 */ + SystemZ_WFKHSBS /* 3038 */, SYSTEMZ_INS_WFKHSBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfkhxb $V1, $V2, $V3 */ + SystemZ_WFKHXB /* 3039 */, SYSTEMZ_INS_WFKHXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfkhxbs $V1, $V2, $V3 */ + SystemZ_WFKHXBS /* 3040 */, SYSTEMZ_INS_WFKHXBS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfksb $V1, $V2 */ + SystemZ_WFKSB /* 3041 */, SYSTEMZ_INS_WFKSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wfkxb $V1, $V2 */ + SystemZ_WFKXB /* 3042 */, SYSTEMZ_INS_WFKXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wflcdb $V1, $V2 */ + SystemZ_WFLCDB /* 3043 */, SYSTEMZ_INS_WFLCDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wflcsb $V1, $V2 */ + SystemZ_WFLCSB /* 3044 */, SYSTEMZ_INS_WFLCSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wflcxb $V1, $V2 */ + SystemZ_WFLCXB /* 3045 */, SYSTEMZ_INS_WFLCXB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wflld $V1, $V2 */ + SystemZ_WFLLD /* 3046 */, SYSTEMZ_INS_WFLLD, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wflls $V1, $V2 */ + SystemZ_WFLLS /* 3047 */, SYSTEMZ_INS_WFLLS, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wflndb $V1, $V2 */ + SystemZ_WFLNDB /* 3048 */, SYSTEMZ_INS_WFLNDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wflnsb $V1, $V2 */ + SystemZ_WFLNSB /* 3049 */, SYSTEMZ_INS_WFLNSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wflnxb $V1, $V2 */ + SystemZ_WFLNXB /* 3050 */, SYSTEMZ_INS_WFLNXB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wflpdb $V1, $V2 */ + SystemZ_WFLPDB /* 3051 */, SYSTEMZ_INS_WFLPDB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wflpsb $V1, $V2 */ + SystemZ_WFLPSB /* 3052 */, SYSTEMZ_INS_WFLPSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wflpxb $V1, $V2 */ + SystemZ_WFLPXB /* 3053 */, SYSTEMZ_INS_WFLPXB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wflrd $V1, $V2, $M4, $M5 */ + SystemZ_WFLRD /* 3054 */, SYSTEMZ_INS_WFLRD, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wflrx $V1, $V2, $M4, $M5 */ + SystemZ_WFLRX /* 3055 */, SYSTEMZ_INS_WFLRX, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wfmadb $V1, $V2, $V3, $V4 */ + SystemZ_WFMADB /* 3056 */, SYSTEMZ_INS_WFMADB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* wfmasb $V1, $V2, $V3, $V4 */ + SystemZ_WFMASB /* 3057 */, SYSTEMZ_INS_WFMASB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* wfmaxb $V1, $V2, $V3, $V4 */ + SystemZ_WFMAXB /* 3058 */, SYSTEMZ_INS_WFMAXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* wfmaxdb $V1, $V2, $V3, $M6 */ + SystemZ_WFMAXDB /* 3059 */, SYSTEMZ_INS_WFMAXDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfmaxsb $V1, $V2, $V3, $M6 */ + SystemZ_WFMAXSB /* 3060 */, SYSTEMZ_INS_WFMAXSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfmaxxb $V1, $V2, $V3, $M6 */ + SystemZ_WFMAXXB /* 3061 */, SYSTEMZ_INS_WFMAXXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfmdb $V1, $V2, $V3 */ + SystemZ_WFMDB /* 3062 */, SYSTEMZ_INS_WFMDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfmindb $V1, $V2, $V3, $M6 */ + SystemZ_WFMINDB /* 3063 */, SYSTEMZ_INS_WFMINDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfminsb $V1, $V2, $V3, $M6 */ + SystemZ_WFMINSB /* 3064 */, SYSTEMZ_INS_WFMINSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfminxb $V1, $V2, $V3, $M6 */ + SystemZ_WFMINXB /* 3065 */, SYSTEMZ_INS_WFMINXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfmsb $V1, $V2, $V3 */ + SystemZ_WFMSB /* 3066 */, SYSTEMZ_INS_WFMSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfmsdb $V1, $V2, $V3, $V4 */ + SystemZ_WFMSDB /* 3067 */, SYSTEMZ_INS_WFMSDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* wfmssb $V1, $V2, $V3, $V4 */ + SystemZ_WFMSSB /* 3068 */, SYSTEMZ_INS_WFMSSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* wfmsxb $V1, $V2, $V3, $V4 */ + SystemZ_WFMSXB /* 3069 */, SYSTEMZ_INS_WFMSXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* wfmxb $V1, $V2, $V3 */ + SystemZ_WFMXB /* 3070 */, SYSTEMZ_INS_WFMXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfnmadb $V1, $V2, $V3, $V4 */ + SystemZ_WFNMADB /* 3071 */, SYSTEMZ_INS_WFNMADB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* wfnmasb $V1, $V2, $V3, $V4 */ + SystemZ_WFNMASB /* 3072 */, SYSTEMZ_INS_WFNMASB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* wfnmaxb $V1, $V2, $V3, $V4 */ + SystemZ_WFNMAXB /* 3073 */, SYSTEMZ_INS_WFNMAXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* wfnmsdb $V1, $V2, $V3, $V4 */ + SystemZ_WFNMSDB /* 3074 */, SYSTEMZ_INS_WFNMSDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* wfnmssb $V1, $V2, $V3, $V4 */ + SystemZ_WFNMSSB /* 3075 */, SYSTEMZ_INS_WFNMSSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* wfnmsxb $V1, $V2, $V3, $V4 */ + SystemZ_WFNMSXB /* 3076 */, SYSTEMZ_INS_WFNMSXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRE }} + + #endif +}, +{ + /* wfpsodb $V1, $V2, $M5 */ + SystemZ_WFPSODB /* 3077 */, SYSTEMZ_INS_WFPSODB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wfpsosb $V1, $V2, $M5 */ + SystemZ_WFPSOSB /* 3078 */, SYSTEMZ_INS_WFPSOSB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wfpsoxb $V1, $V2, $M5 */ + SystemZ_WFPSOXB /* 3079 */, SYSTEMZ_INS_WFPSOXB, + #ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wfsdb $V1, $V2, $V3 */ + SystemZ_WFSDB /* 3080 */, SYSTEMZ_INS_WFSDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfsqdb $V1, $V2 */ + SystemZ_WFSQDB /* 3081 */, SYSTEMZ_INS_WFSQDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wfsqsb $V1, $V2 */ + SystemZ_WFSQSB /* 3082 */, SYSTEMZ_INS_WFSQSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wfsqxb $V1, $V2 */ + SystemZ_WFSQXB /* 3083 */, SYSTEMZ_INS_WFSQXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wfssb $V1, $V2, $V3 */ + SystemZ_WFSSB /* 3084 */, SYSTEMZ_INS_WFSSB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wfsxb $V1, $V2, $V3 */ + SystemZ_WFSXB /* 3085 */, SYSTEMZ_INS_WFSXB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRC }} + + #endif +}, +{ + /* wftcidb $V1, $V2, $I3 */ + SystemZ_WFTCIDB /* 3086 */, SYSTEMZ_INS_WFTCIDB, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIE }} + + #endif +}, +{ + /* wftcisb $V1, $V2, $I3 */ + SystemZ_WFTCISB /* 3087 */, SYSTEMZ_INS_WFTCISB, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIE }} + + #endif +}, +{ + /* wftcixb $V1, $V2, $I3 */ + SystemZ_WFTCIXB /* 3088 */, SYSTEMZ_INS_WFTCIXB, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRIE }} + + #endif +}, +{ + /* wldeb $V1, $V2 */ + SystemZ_WLDEB /* 3089 */, SYSTEMZ_INS_WLDEB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* wledb $V1, $V2, $M4, $M5 */ + SystemZ_WLEDB /* 3090 */, SYSTEMZ_INS_WLEDB, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_FPC, 0 }, { 0 }, { SYSTEMZ_FEATURE_FEATUREVECTOR, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTVRRA }} + + #endif +}, +{ + /* x $R1, $XBD2 */ + SystemZ_X /* 3091 */, SYSTEMZ_INS_X, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXA }} + + #endif +}, +{ + /* xc $BDL1, $BD2 */ + SystemZ_XC /* 3092 */, SYSTEMZ_INS_XC, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSA }} + + #endif +}, +{ + /* xg $R1, $XBD2 */ + SystemZ_XG /* 3093 */, SYSTEMZ_INS_XG, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* xgr $R1, $R2 */ + SystemZ_XGR /* 3094 */, SYSTEMZ_INS_XGR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRE }} + + #endif +}, +{ + /* xgrk $R1, $R2, $R3 */ + SystemZ_XGRK /* 3095 */, SYSTEMZ_INS_XGRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* xi $BD1, $I2 */ + SystemZ_XI /* 3096 */, SYSTEMZ_INS_XI, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSI }} + + #endif +}, +{ + /* xihf $R1, $I2 */ + SystemZ_XIHF /* 3097 */, SYSTEMZ_INS_XIHF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* xilf $R1, $I2 */ + SystemZ_XILF /* 3098 */, SYSTEMZ_INS_XILF, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRILA }} + + #endif +}, +{ + /* xiy $BD1, $I2 */ + SystemZ_XIY /* 3099 */, SYSTEMZ_INS_XIY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSIY }} + + #endif +}, +{ + /* xr $R1, $R2 */ + SystemZ_XR /* 3100 */, SYSTEMZ_INS_XR, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRR }} + + #endif +}, +{ + /* xrk $R1, $R2, $R3 */ + SystemZ_XRK /* 3101 */, SYSTEMZ_INS_XRK, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRRFA }} + + #endif +}, +{ + /* xsch */ + SystemZ_XSCH /* 3102 */, SYSTEMZ_INS_XSCH, + #ifndef CAPSTONE_DIET + { SYSTEMZ_REG_R1L, 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTS }} + + #endif +}, +{ + /* xy $R1, $XBD2 */ + SystemZ_XY /* 3103 */, SYSTEMZ_INS_XY, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTRXYA }} + + #endif +}, +{ + /* zap $BDL1, $BDL2 */ + SystemZ_ZAP /* 3104 */, SYSTEMZ_INS_ZAP, + #ifndef CAPSTONE_DIET + { 0 }, { SYSTEMZ_REG_CC, 0 }, { 0 }, 0, 0, { .systemz = { SYSTEMZ_INSN_FORM_INSTSSB }} + + #endif +}, diff --git a/arch/SystemZ/SystemZGenCSMappingInsnName.inc b/arch/SystemZ/SystemZGenCSMappingInsnName.inc new file mode 100644 index 0000000000..a00f994b09 --- /dev/null +++ b/arch/SystemZ/SystemZGenCSMappingInsnName.inc @@ -0,0 +1,2513 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + + "invalid", // SYSTEMZ_INS_INVALID + "a", // SYSTEMZ_INS_A + "ad", // SYSTEMZ_INS_AD + "adb", // SYSTEMZ_INS_ADB + "adbr", // SYSTEMZ_INS_ADBR + "adr", // SYSTEMZ_INS_ADR + "adtr", // SYSTEMZ_INS_ADTR + "adtra", // SYSTEMZ_INS_ADTRA + "ae", // SYSTEMZ_INS_AE + "aeb", // SYSTEMZ_INS_AEB + "aebr", // SYSTEMZ_INS_AEBR + "aer", // SYSTEMZ_INS_AER + "afi", // SYSTEMZ_INS_AFI + "ag", // SYSTEMZ_INS_AG + "agf", // SYSTEMZ_INS_AGF + "agfi", // SYSTEMZ_INS_AGFI + "agfr", // SYSTEMZ_INS_AGFR + "agh", // SYSTEMZ_INS_AGH + "aghi", // SYSTEMZ_INS_AGHI + "aghik", // SYSTEMZ_INS_AGHIK + "agr", // SYSTEMZ_INS_AGR + "agrk", // SYSTEMZ_INS_AGRK + "agsi", // SYSTEMZ_INS_AGSI + "ah", // SYSTEMZ_INS_AH + "ahhhr", // SYSTEMZ_INS_AHHHR + "ahhlr", // SYSTEMZ_INS_AHHLR + "ahi", // SYSTEMZ_INS_AHI + "ahik", // SYSTEMZ_INS_AHIK + "ahy", // SYSTEMZ_INS_AHY + "aih", // SYSTEMZ_INS_AIH + "al", // SYSTEMZ_INS_AL + "alc", // SYSTEMZ_INS_ALC + "alcg", // SYSTEMZ_INS_ALCG + "alcgr", // SYSTEMZ_INS_ALCGR + "alcr", // SYSTEMZ_INS_ALCR + "alfi", // SYSTEMZ_INS_ALFI + "alg", // SYSTEMZ_INS_ALG + "algf", // SYSTEMZ_INS_ALGF + "algfi", // SYSTEMZ_INS_ALGFI + "algfr", // SYSTEMZ_INS_ALGFR + "alghsik", // SYSTEMZ_INS_ALGHSIK + "algr", // SYSTEMZ_INS_ALGR + "algrk", // SYSTEMZ_INS_ALGRK + "algsi", // SYSTEMZ_INS_ALGSI + "alhhhr", // SYSTEMZ_INS_ALHHHR + "alhhlr", // SYSTEMZ_INS_ALHHLR + "alhsik", // SYSTEMZ_INS_ALHSIK + "alr", // SYSTEMZ_INS_ALR + "alrk", // SYSTEMZ_INS_ALRK + "alsi", // SYSTEMZ_INS_ALSI + "alsih", // SYSTEMZ_INS_ALSIH + "alsihn", // SYSTEMZ_INS_ALSIHN + "aly", // SYSTEMZ_INS_ALY + "ap", // SYSTEMZ_INS_AP + "ar", // SYSTEMZ_INS_AR + "ark", // SYSTEMZ_INS_ARK + "asi", // SYSTEMZ_INS_ASI + "au", // SYSTEMZ_INS_AU + "aur", // SYSTEMZ_INS_AUR + "aw", // SYSTEMZ_INS_AW + "awr", // SYSTEMZ_INS_AWR + "axbr", // SYSTEMZ_INS_AXBR + "axr", // SYSTEMZ_INS_AXR + "axtr", // SYSTEMZ_INS_AXTR + "axtra", // SYSTEMZ_INS_AXTRA + "ay", // SYSTEMZ_INS_AY + "b", // SYSTEMZ_INS_B + "bakr", // SYSTEMZ_INS_BAKR + "bal", // SYSTEMZ_INS_BAL + "balr", // SYSTEMZ_INS_BALR + "bas", // SYSTEMZ_INS_BAS + "basr", // SYSTEMZ_INS_BASR + "bassm", // SYSTEMZ_INS_BASSM + "be", // SYSTEMZ_INS_BE + "bh", // SYSTEMZ_INS_BH + "bhe", // SYSTEMZ_INS_BHE + "bl", // SYSTEMZ_INS_BL + "ble", // SYSTEMZ_INS_BLE + "blh", // SYSTEMZ_INS_BLH + "bm", // SYSTEMZ_INS_BM + "bne", // SYSTEMZ_INS_BNE + "bnh", // SYSTEMZ_INS_BNH + "bnhe", // SYSTEMZ_INS_BNHE + "bnl", // SYSTEMZ_INS_BNL + "bnle", // SYSTEMZ_INS_BNLE + "bnlh", // SYSTEMZ_INS_BNLH + "bnm", // SYSTEMZ_INS_BNM + "bno", // SYSTEMZ_INS_BNO + "bnp", // SYSTEMZ_INS_BNP + "bnz", // SYSTEMZ_INS_BNZ + "bo", // SYSTEMZ_INS_BO + "bp", // SYSTEMZ_INS_BP + "bz", // SYSTEMZ_INS_BZ + "bc", // SYSTEMZ_INS_BC + "bcr", // SYSTEMZ_INS_BCR + "bct", // SYSTEMZ_INS_BCT + "bctg", // SYSTEMZ_INS_BCTG + "bctgr", // SYSTEMZ_INS_BCTGR + "bctr", // SYSTEMZ_INS_BCTR + "bi", // SYSTEMZ_INS_BI + "bie", // SYSTEMZ_INS_BIE + "bih", // SYSTEMZ_INS_BIH + "bihe", // SYSTEMZ_INS_BIHE + "bil", // SYSTEMZ_INS_BIL + "bile", // SYSTEMZ_INS_BILE + "bilh", // SYSTEMZ_INS_BILH + "bim", // SYSTEMZ_INS_BIM + "bine", // SYSTEMZ_INS_BINE + "binh", // SYSTEMZ_INS_BINH + "binhe", // SYSTEMZ_INS_BINHE + "binl", // SYSTEMZ_INS_BINL + "binle", // SYSTEMZ_INS_BINLE + "binlh", // SYSTEMZ_INS_BINLH + "binm", // SYSTEMZ_INS_BINM + "bino", // SYSTEMZ_INS_BINO + "binp", // SYSTEMZ_INS_BINP + "binz", // SYSTEMZ_INS_BINZ + "bio", // SYSTEMZ_INS_BIO + "bip", // SYSTEMZ_INS_BIP + "biz", // SYSTEMZ_INS_BIZ + "bic", // SYSTEMZ_INS_BIC + "bpp", // SYSTEMZ_INS_BPP + "bprp", // SYSTEMZ_INS_BPRP + "br", // SYSTEMZ_INS_BR + "bras", // SYSTEMZ_INS_BRAS + "brasl", // SYSTEMZ_INS_BRASL + "ber", // SYSTEMZ_INS_BER + "bhr", // SYSTEMZ_INS_BHR + "bher", // SYSTEMZ_INS_BHER + "blr", // SYSTEMZ_INS_BLR + "bler", // SYSTEMZ_INS_BLER + "blhr", // SYSTEMZ_INS_BLHR + "bmr", // SYSTEMZ_INS_BMR + "bner", // SYSTEMZ_INS_BNER + "bnhr", // SYSTEMZ_INS_BNHR + "bnher", // SYSTEMZ_INS_BNHER + "bnlr", // SYSTEMZ_INS_BNLR + "bnler", // SYSTEMZ_INS_BNLER + "bnlhr", // SYSTEMZ_INS_BNLHR + "bnmr", // SYSTEMZ_INS_BNMR + "bnor", // SYSTEMZ_INS_BNOR + "bnpr", // SYSTEMZ_INS_BNPR + "bnzr", // SYSTEMZ_INS_BNZR + "bor", // SYSTEMZ_INS_BOR + "bpr", // SYSTEMZ_INS_BPR + "bzr", // SYSTEMZ_INS_BZR + "brc", // SYSTEMZ_INS_BRC + "brcl", // SYSTEMZ_INS_BRCL + "brct", // SYSTEMZ_INS_BRCT + "brctg", // SYSTEMZ_INS_BRCTG + "brcth", // SYSTEMZ_INS_BRCTH + "brxh", // SYSTEMZ_INS_BRXH + "brxhg", // SYSTEMZ_INS_BRXHG + "brxle", // SYSTEMZ_INS_BRXLE + "brxlg", // SYSTEMZ_INS_BRXLG + "bsa", // SYSTEMZ_INS_BSA + "bsg", // SYSTEMZ_INS_BSG + "bsm", // SYSTEMZ_INS_BSM + "bxh", // SYSTEMZ_INS_BXH + "bxhg", // SYSTEMZ_INS_BXHG + "bxle", // SYSTEMZ_INS_BXLE + "bxleg", // SYSTEMZ_INS_BXLEG + "c", // SYSTEMZ_INS_C + "cd", // SYSTEMZ_INS_CD + "cdb", // SYSTEMZ_INS_CDB + "cdbr", // SYSTEMZ_INS_CDBR + "cdfbr", // SYSTEMZ_INS_CDFBR + "cdfbra", // SYSTEMZ_INS_CDFBRA + "cdfr", // SYSTEMZ_INS_CDFR + "cdftr", // SYSTEMZ_INS_CDFTR + "cdgbr", // SYSTEMZ_INS_CDGBR + "cdgbra", // SYSTEMZ_INS_CDGBRA + "cdgr", // SYSTEMZ_INS_CDGR + "cdgtr", // SYSTEMZ_INS_CDGTR + "cdgtra", // SYSTEMZ_INS_CDGTRA + "cdlfbr", // SYSTEMZ_INS_CDLFBR + "cdlftr", // SYSTEMZ_INS_CDLFTR + "cdlgbr", // SYSTEMZ_INS_CDLGBR + "cdlgtr", // SYSTEMZ_INS_CDLGTR + "cdpt", // SYSTEMZ_INS_CDPT + "cdr", // SYSTEMZ_INS_CDR + "cds", // SYSTEMZ_INS_CDS + "cdsg", // SYSTEMZ_INS_CDSG + "cdstr", // SYSTEMZ_INS_CDSTR + "cdsy", // SYSTEMZ_INS_CDSY + "cdtr", // SYSTEMZ_INS_CDTR + "cdutr", // SYSTEMZ_INS_CDUTR + "cdzt", // SYSTEMZ_INS_CDZT + "ce", // SYSTEMZ_INS_CE + "ceb", // SYSTEMZ_INS_CEB + "cebr", // SYSTEMZ_INS_CEBR + "cedtr", // SYSTEMZ_INS_CEDTR + "cefbr", // SYSTEMZ_INS_CEFBR + "cefbra", // SYSTEMZ_INS_CEFBRA + "cefr", // SYSTEMZ_INS_CEFR + "cegbr", // SYSTEMZ_INS_CEGBR + "cegbra", // SYSTEMZ_INS_CEGBRA + "cegr", // SYSTEMZ_INS_CEGR + "celfbr", // SYSTEMZ_INS_CELFBR + "celgbr", // SYSTEMZ_INS_CELGBR + "cer", // SYSTEMZ_INS_CER + "cextr", // SYSTEMZ_INS_CEXTR + "cfc", // SYSTEMZ_INS_CFC + "cfdbr", // SYSTEMZ_INS_CFDBR + "cfdbra", // SYSTEMZ_INS_CFDBRA + "cfdr", // SYSTEMZ_INS_CFDR + "cfdtr", // SYSTEMZ_INS_CFDTR + "cfebr", // SYSTEMZ_INS_CFEBR + "cfebra", // SYSTEMZ_INS_CFEBRA + "cfer", // SYSTEMZ_INS_CFER + "cfi", // SYSTEMZ_INS_CFI + "cfxbr", // SYSTEMZ_INS_CFXBR + "cfxbra", // SYSTEMZ_INS_CFXBRA + "cfxr", // SYSTEMZ_INS_CFXR + "cfxtr", // SYSTEMZ_INS_CFXTR + "cg", // SYSTEMZ_INS_CG + "cgdbr", // SYSTEMZ_INS_CGDBR + "cgdbra", // SYSTEMZ_INS_CGDBRA + "cgdr", // SYSTEMZ_INS_CGDR + "cgdtr", // SYSTEMZ_INS_CGDTR + "cgdtra", // SYSTEMZ_INS_CGDTRA + "cgebr", // SYSTEMZ_INS_CGEBR + "cgebra", // SYSTEMZ_INS_CGEBRA + "cger", // SYSTEMZ_INS_CGER + "cgf", // SYSTEMZ_INS_CGF + "cgfi", // SYSTEMZ_INS_CGFI + "cgfr", // SYSTEMZ_INS_CGFR + "cgfrl", // SYSTEMZ_INS_CGFRL + "cgh", // SYSTEMZ_INS_CGH + "cghi", // SYSTEMZ_INS_CGHI + "cghrl", // SYSTEMZ_INS_CGHRL + "cghsi", // SYSTEMZ_INS_CGHSI + "cgib", // SYSTEMZ_INS_CGIB + "cgibe", // SYSTEMZ_INS_CGIBE + "cgibh", // SYSTEMZ_INS_CGIBH + "cgibhe", // SYSTEMZ_INS_CGIBHE + "cgibl", // SYSTEMZ_INS_CGIBL + "cgible", // SYSTEMZ_INS_CGIBLE + "cgiblh", // SYSTEMZ_INS_CGIBLH + "cgibne", // SYSTEMZ_INS_CGIBNE + "cgibnh", // SYSTEMZ_INS_CGIBNH + "cgibnhe", // SYSTEMZ_INS_CGIBNHE + "cgibnl", // SYSTEMZ_INS_CGIBNL + "cgibnle", // SYSTEMZ_INS_CGIBNLE + "cgibnlh", // SYSTEMZ_INS_CGIBNLH + "cgij", // SYSTEMZ_INS_CGIJ + "cgije", // SYSTEMZ_INS_CGIJE + "cgijh", // SYSTEMZ_INS_CGIJH + "cgijhe", // SYSTEMZ_INS_CGIJHE + "cgijl", // SYSTEMZ_INS_CGIJL + "cgijle", // SYSTEMZ_INS_CGIJLE + "cgijlh", // SYSTEMZ_INS_CGIJLH + "cgijne", // SYSTEMZ_INS_CGIJNE + "cgijnh", // SYSTEMZ_INS_CGIJNH + "cgijnhe", // SYSTEMZ_INS_CGIJNHE + "cgijnl", // SYSTEMZ_INS_CGIJNL + "cgijnle", // SYSTEMZ_INS_CGIJNLE + "cgijnlh", // SYSTEMZ_INS_CGIJNLH + "cgit", // SYSTEMZ_INS_CGIT + "cgite", // SYSTEMZ_INS_CGITE + "cgith", // SYSTEMZ_INS_CGITH + "cgithe", // SYSTEMZ_INS_CGITHE + "cgitl", // SYSTEMZ_INS_CGITL + "cgitle", // SYSTEMZ_INS_CGITLE + "cgitlh", // SYSTEMZ_INS_CGITLH + "cgitne", // SYSTEMZ_INS_CGITNE + "cgitnh", // SYSTEMZ_INS_CGITNH + "cgitnhe", // SYSTEMZ_INS_CGITNHE + "cgitnl", // SYSTEMZ_INS_CGITNL + "cgitnle", // SYSTEMZ_INS_CGITNLE + "cgitnlh", // SYSTEMZ_INS_CGITNLH + "cgr", // SYSTEMZ_INS_CGR + "cgrb", // SYSTEMZ_INS_CGRB + "cgrbe", // SYSTEMZ_INS_CGRBE + "cgrbh", // SYSTEMZ_INS_CGRBH + "cgrbhe", // SYSTEMZ_INS_CGRBHE + "cgrbl", // SYSTEMZ_INS_CGRBL + "cgrble", // SYSTEMZ_INS_CGRBLE + "cgrblh", // SYSTEMZ_INS_CGRBLH + "cgrbne", // SYSTEMZ_INS_CGRBNE + "cgrbnh", // SYSTEMZ_INS_CGRBNH + "cgrbnhe", // SYSTEMZ_INS_CGRBNHE + "cgrbnl", // SYSTEMZ_INS_CGRBNL + "cgrbnle", // SYSTEMZ_INS_CGRBNLE + "cgrbnlh", // SYSTEMZ_INS_CGRBNLH + "cgrj", // SYSTEMZ_INS_CGRJ + "cgrje", // SYSTEMZ_INS_CGRJE + "cgrjh", // SYSTEMZ_INS_CGRJH + "cgrjhe", // SYSTEMZ_INS_CGRJHE + "cgrjl", // SYSTEMZ_INS_CGRJL + "cgrjle", // SYSTEMZ_INS_CGRJLE + "cgrjlh", // SYSTEMZ_INS_CGRJLH + "cgrjne", // SYSTEMZ_INS_CGRJNE + "cgrjnh", // SYSTEMZ_INS_CGRJNH + "cgrjnhe", // SYSTEMZ_INS_CGRJNHE + "cgrjnl", // SYSTEMZ_INS_CGRJNL + "cgrjnle", // SYSTEMZ_INS_CGRJNLE + "cgrjnlh", // SYSTEMZ_INS_CGRJNLH + "cgrl", // SYSTEMZ_INS_CGRL + "cgrt", // SYSTEMZ_INS_CGRT + "cgrte", // SYSTEMZ_INS_CGRTE + "cgrth", // SYSTEMZ_INS_CGRTH + "cgrthe", // SYSTEMZ_INS_CGRTHE + "cgrtl", // SYSTEMZ_INS_CGRTL + "cgrtle", // SYSTEMZ_INS_CGRTLE + "cgrtlh", // SYSTEMZ_INS_CGRTLH + "cgrtne", // SYSTEMZ_INS_CGRTNE + "cgrtnh", // SYSTEMZ_INS_CGRTNH + "cgrtnhe", // SYSTEMZ_INS_CGRTNHE + "cgrtnl", // SYSTEMZ_INS_CGRTNL + "cgrtnle", // SYSTEMZ_INS_CGRTNLE + "cgrtnlh", // SYSTEMZ_INS_CGRTNLH + "cgxbr", // SYSTEMZ_INS_CGXBR + "cgxbra", // SYSTEMZ_INS_CGXBRA + "cgxr", // SYSTEMZ_INS_CGXR + "cgxtr", // SYSTEMZ_INS_CGXTR + "cgxtra", // SYSTEMZ_INS_CGXTRA + "ch", // SYSTEMZ_INS_CH + "chf", // SYSTEMZ_INS_CHF + "chhr", // SYSTEMZ_INS_CHHR + "chhsi", // SYSTEMZ_INS_CHHSI + "chi", // SYSTEMZ_INS_CHI + "chlr", // SYSTEMZ_INS_CHLR + "chrl", // SYSTEMZ_INS_CHRL + "chsi", // SYSTEMZ_INS_CHSI + "chy", // SYSTEMZ_INS_CHY + "cib", // SYSTEMZ_INS_CIB + "cibe", // SYSTEMZ_INS_CIBE + "cibh", // SYSTEMZ_INS_CIBH + "cibhe", // SYSTEMZ_INS_CIBHE + "cibl", // SYSTEMZ_INS_CIBL + "cible", // SYSTEMZ_INS_CIBLE + "ciblh", // SYSTEMZ_INS_CIBLH + "cibne", // SYSTEMZ_INS_CIBNE + "cibnh", // SYSTEMZ_INS_CIBNH + "cibnhe", // SYSTEMZ_INS_CIBNHE + "cibnl", // SYSTEMZ_INS_CIBNL + "cibnle", // SYSTEMZ_INS_CIBNLE + "cibnlh", // SYSTEMZ_INS_CIBNLH + "cih", // SYSTEMZ_INS_CIH + "cij", // SYSTEMZ_INS_CIJ + "cije", // SYSTEMZ_INS_CIJE + "cijh", // SYSTEMZ_INS_CIJH + "cijhe", // SYSTEMZ_INS_CIJHE + "cijl", // SYSTEMZ_INS_CIJL + "cijle", // SYSTEMZ_INS_CIJLE + "cijlh", // SYSTEMZ_INS_CIJLH + "cijne", // SYSTEMZ_INS_CIJNE + "cijnh", // SYSTEMZ_INS_CIJNH + "cijnhe", // SYSTEMZ_INS_CIJNHE + "cijnl", // SYSTEMZ_INS_CIJNL + "cijnle", // SYSTEMZ_INS_CIJNLE + "cijnlh", // SYSTEMZ_INS_CIJNLH + "cit", // SYSTEMZ_INS_CIT + "cite", // SYSTEMZ_INS_CITE + "cith", // SYSTEMZ_INS_CITH + "cithe", // SYSTEMZ_INS_CITHE + "citl", // SYSTEMZ_INS_CITL + "citle", // SYSTEMZ_INS_CITLE + "citlh", // SYSTEMZ_INS_CITLH + "citne", // SYSTEMZ_INS_CITNE + "citnh", // SYSTEMZ_INS_CITNH + "citnhe", // SYSTEMZ_INS_CITNHE + "citnl", // SYSTEMZ_INS_CITNL + "citnle", // SYSTEMZ_INS_CITNLE + "citnlh", // SYSTEMZ_INS_CITNLH + "cksm", // SYSTEMZ_INS_CKSM + "cl", // SYSTEMZ_INS_CL + "clc", // SYSTEMZ_INS_CLC + "clcl", // SYSTEMZ_INS_CLCL + "clcle", // SYSTEMZ_INS_CLCLE + "clclu", // SYSTEMZ_INS_CLCLU + "clfdbr", // SYSTEMZ_INS_CLFDBR + "clfdtr", // SYSTEMZ_INS_CLFDTR + "clfebr", // SYSTEMZ_INS_CLFEBR + "clfhsi", // SYSTEMZ_INS_CLFHSI + "clfi", // SYSTEMZ_INS_CLFI + "clfit", // SYSTEMZ_INS_CLFIT + "clfite", // SYSTEMZ_INS_CLFITE + "clfith", // SYSTEMZ_INS_CLFITH + "clfithe", // SYSTEMZ_INS_CLFITHE + "clfitl", // SYSTEMZ_INS_CLFITL + "clfitle", // SYSTEMZ_INS_CLFITLE + "clfitlh", // SYSTEMZ_INS_CLFITLH + "clfitne", // SYSTEMZ_INS_CLFITNE + "clfitnh", // SYSTEMZ_INS_CLFITNH + "clfitnhe", // SYSTEMZ_INS_CLFITNHE + "clfitnl", // SYSTEMZ_INS_CLFITNL + "clfitnle", // SYSTEMZ_INS_CLFITNLE + "clfitnlh", // SYSTEMZ_INS_CLFITNLH + "clfxbr", // SYSTEMZ_INS_CLFXBR + "clfxtr", // SYSTEMZ_INS_CLFXTR + "clg", // SYSTEMZ_INS_CLG + "clgdbr", // SYSTEMZ_INS_CLGDBR + "clgdtr", // SYSTEMZ_INS_CLGDTR + "clgebr", // SYSTEMZ_INS_CLGEBR + "clgf", // SYSTEMZ_INS_CLGF + "clgfi", // SYSTEMZ_INS_CLGFI + "clgfr", // SYSTEMZ_INS_CLGFR + "clgfrl", // SYSTEMZ_INS_CLGFRL + "clghrl", // SYSTEMZ_INS_CLGHRL + "clghsi", // SYSTEMZ_INS_CLGHSI + "clgib", // SYSTEMZ_INS_CLGIB + "clgibe", // SYSTEMZ_INS_CLGIBE + "clgibh", // SYSTEMZ_INS_CLGIBH + "clgibhe", // SYSTEMZ_INS_CLGIBHE + "clgibl", // SYSTEMZ_INS_CLGIBL + "clgible", // SYSTEMZ_INS_CLGIBLE + "clgiblh", // SYSTEMZ_INS_CLGIBLH + "clgibne", // SYSTEMZ_INS_CLGIBNE + "clgibnh", // SYSTEMZ_INS_CLGIBNH + "clgibnhe", // SYSTEMZ_INS_CLGIBNHE + "clgibnl", // SYSTEMZ_INS_CLGIBNL + "clgibnle", // SYSTEMZ_INS_CLGIBNLE + "clgibnlh", // SYSTEMZ_INS_CLGIBNLH + "clgij", // SYSTEMZ_INS_CLGIJ + "clgije", // SYSTEMZ_INS_CLGIJE + "clgijh", // SYSTEMZ_INS_CLGIJH + "clgijhe", // SYSTEMZ_INS_CLGIJHE + "clgijl", // SYSTEMZ_INS_CLGIJL + "clgijle", // SYSTEMZ_INS_CLGIJLE + "clgijlh", // SYSTEMZ_INS_CLGIJLH + "clgijne", // SYSTEMZ_INS_CLGIJNE + "clgijnh", // SYSTEMZ_INS_CLGIJNH + "clgijnhe", // SYSTEMZ_INS_CLGIJNHE + "clgijnl", // SYSTEMZ_INS_CLGIJNL + "clgijnle", // SYSTEMZ_INS_CLGIJNLE + "clgijnlh", // SYSTEMZ_INS_CLGIJNLH + "clgit", // SYSTEMZ_INS_CLGIT + "clgite", // SYSTEMZ_INS_CLGITE + "clgith", // SYSTEMZ_INS_CLGITH + "clgithe", // SYSTEMZ_INS_CLGITHE + "clgitl", // SYSTEMZ_INS_CLGITL + "clgitle", // SYSTEMZ_INS_CLGITLE + "clgitlh", // SYSTEMZ_INS_CLGITLH + "clgitne", // SYSTEMZ_INS_CLGITNE + "clgitnh", // SYSTEMZ_INS_CLGITNH + "clgitnhe", // SYSTEMZ_INS_CLGITNHE + "clgitnl", // SYSTEMZ_INS_CLGITNL + "clgitnle", // SYSTEMZ_INS_CLGITNLE + "clgitnlh", // SYSTEMZ_INS_CLGITNLH + "clgr", // SYSTEMZ_INS_CLGR + "clgrb", // SYSTEMZ_INS_CLGRB + "clgrbe", // SYSTEMZ_INS_CLGRBE + "clgrbh", // SYSTEMZ_INS_CLGRBH + "clgrbhe", // SYSTEMZ_INS_CLGRBHE + "clgrbl", // SYSTEMZ_INS_CLGRBL + "clgrble", // SYSTEMZ_INS_CLGRBLE + "clgrblh", // SYSTEMZ_INS_CLGRBLH + "clgrbne", // SYSTEMZ_INS_CLGRBNE + "clgrbnh", // SYSTEMZ_INS_CLGRBNH + "clgrbnhe", // SYSTEMZ_INS_CLGRBNHE + "clgrbnl", // SYSTEMZ_INS_CLGRBNL + "clgrbnle", // SYSTEMZ_INS_CLGRBNLE + "clgrbnlh", // SYSTEMZ_INS_CLGRBNLH + "clgrj", // SYSTEMZ_INS_CLGRJ + "clgrje", // SYSTEMZ_INS_CLGRJE + "clgrjh", // SYSTEMZ_INS_CLGRJH + "clgrjhe", // SYSTEMZ_INS_CLGRJHE + "clgrjl", // SYSTEMZ_INS_CLGRJL + "clgrjle", // SYSTEMZ_INS_CLGRJLE + "clgrjlh", // SYSTEMZ_INS_CLGRJLH + "clgrjne", // SYSTEMZ_INS_CLGRJNE + "clgrjnh", // SYSTEMZ_INS_CLGRJNH + "clgrjnhe", // SYSTEMZ_INS_CLGRJNHE + "clgrjnl", // SYSTEMZ_INS_CLGRJNL + "clgrjnle", // SYSTEMZ_INS_CLGRJNLE + "clgrjnlh", // SYSTEMZ_INS_CLGRJNLH + "clgrl", // SYSTEMZ_INS_CLGRL + "clgrt", // SYSTEMZ_INS_CLGRT + "clgrte", // SYSTEMZ_INS_CLGRTE + "clgrth", // SYSTEMZ_INS_CLGRTH + "clgrthe", // SYSTEMZ_INS_CLGRTHE + "clgrtl", // SYSTEMZ_INS_CLGRTL + "clgrtle", // SYSTEMZ_INS_CLGRTLE + "clgrtlh", // SYSTEMZ_INS_CLGRTLH + "clgrtne", // SYSTEMZ_INS_CLGRTNE + "clgrtnh", // SYSTEMZ_INS_CLGRTNH + "clgrtnhe", // SYSTEMZ_INS_CLGRTNHE + "clgrtnl", // SYSTEMZ_INS_CLGRTNL + "clgrtnle", // SYSTEMZ_INS_CLGRTNLE + "clgrtnlh", // SYSTEMZ_INS_CLGRTNLH + "clgt", // SYSTEMZ_INS_CLGT + "clgte", // SYSTEMZ_INS_CLGTE + "clgth", // SYSTEMZ_INS_CLGTH + "clgthe", // SYSTEMZ_INS_CLGTHE + "clgtl", // SYSTEMZ_INS_CLGTL + "clgtle", // SYSTEMZ_INS_CLGTLE + "clgtlh", // SYSTEMZ_INS_CLGTLH + "clgtne", // SYSTEMZ_INS_CLGTNE + "clgtnh", // SYSTEMZ_INS_CLGTNH + "clgtnhe", // SYSTEMZ_INS_CLGTNHE + "clgtnl", // SYSTEMZ_INS_CLGTNL + "clgtnle", // SYSTEMZ_INS_CLGTNLE + "clgtnlh", // SYSTEMZ_INS_CLGTNLH + "clgxbr", // SYSTEMZ_INS_CLGXBR + "clgxtr", // SYSTEMZ_INS_CLGXTR + "clhf", // SYSTEMZ_INS_CLHF + "clhhr", // SYSTEMZ_INS_CLHHR + "clhhsi", // SYSTEMZ_INS_CLHHSI + "clhlr", // SYSTEMZ_INS_CLHLR + "clhrl", // SYSTEMZ_INS_CLHRL + "cli", // SYSTEMZ_INS_CLI + "clib", // SYSTEMZ_INS_CLIB + "clibe", // SYSTEMZ_INS_CLIBE + "clibh", // SYSTEMZ_INS_CLIBH + "clibhe", // SYSTEMZ_INS_CLIBHE + "clibl", // SYSTEMZ_INS_CLIBL + "clible", // SYSTEMZ_INS_CLIBLE + "cliblh", // SYSTEMZ_INS_CLIBLH + "clibne", // SYSTEMZ_INS_CLIBNE + "clibnh", // SYSTEMZ_INS_CLIBNH + "clibnhe", // SYSTEMZ_INS_CLIBNHE + "clibnl", // SYSTEMZ_INS_CLIBNL + "clibnle", // SYSTEMZ_INS_CLIBNLE + "clibnlh", // SYSTEMZ_INS_CLIBNLH + "clih", // SYSTEMZ_INS_CLIH + "clij", // SYSTEMZ_INS_CLIJ + "clije", // SYSTEMZ_INS_CLIJE + "clijh", // SYSTEMZ_INS_CLIJH + "clijhe", // SYSTEMZ_INS_CLIJHE + "clijl", // SYSTEMZ_INS_CLIJL + "clijle", // SYSTEMZ_INS_CLIJLE + "clijlh", // SYSTEMZ_INS_CLIJLH + "clijne", // SYSTEMZ_INS_CLIJNE + "clijnh", // SYSTEMZ_INS_CLIJNH + "clijnhe", // SYSTEMZ_INS_CLIJNHE + "clijnl", // SYSTEMZ_INS_CLIJNL + "clijnle", // SYSTEMZ_INS_CLIJNLE + "clijnlh", // SYSTEMZ_INS_CLIJNLH + "cliy", // SYSTEMZ_INS_CLIY + "clm", // SYSTEMZ_INS_CLM + "clmh", // SYSTEMZ_INS_CLMH + "clmy", // SYSTEMZ_INS_CLMY + "clr", // SYSTEMZ_INS_CLR + "clrb", // SYSTEMZ_INS_CLRB + "clrbe", // SYSTEMZ_INS_CLRBE + "clrbh", // SYSTEMZ_INS_CLRBH + "clrbhe", // SYSTEMZ_INS_CLRBHE + "clrbl", // SYSTEMZ_INS_CLRBL + "clrble", // SYSTEMZ_INS_CLRBLE + "clrblh", // SYSTEMZ_INS_CLRBLH + "clrbne", // SYSTEMZ_INS_CLRBNE + "clrbnh", // SYSTEMZ_INS_CLRBNH + "clrbnhe", // SYSTEMZ_INS_CLRBNHE + "clrbnl", // SYSTEMZ_INS_CLRBNL + "clrbnle", // SYSTEMZ_INS_CLRBNLE + "clrbnlh", // SYSTEMZ_INS_CLRBNLH + "clrj", // SYSTEMZ_INS_CLRJ + "clrje", // SYSTEMZ_INS_CLRJE + "clrjh", // SYSTEMZ_INS_CLRJH + "clrjhe", // SYSTEMZ_INS_CLRJHE + "clrjl", // SYSTEMZ_INS_CLRJL + "clrjle", // SYSTEMZ_INS_CLRJLE + "clrjlh", // SYSTEMZ_INS_CLRJLH + "clrjne", // SYSTEMZ_INS_CLRJNE + "clrjnh", // SYSTEMZ_INS_CLRJNH + "clrjnhe", // SYSTEMZ_INS_CLRJNHE + "clrjnl", // SYSTEMZ_INS_CLRJNL + "clrjnle", // SYSTEMZ_INS_CLRJNLE + "clrjnlh", // SYSTEMZ_INS_CLRJNLH + "clrl", // SYSTEMZ_INS_CLRL + "clrt", // SYSTEMZ_INS_CLRT + "clrte", // SYSTEMZ_INS_CLRTE + "clrth", // SYSTEMZ_INS_CLRTH + "clrthe", // SYSTEMZ_INS_CLRTHE + "clrtl", // SYSTEMZ_INS_CLRTL + "clrtle", // SYSTEMZ_INS_CLRTLE + "clrtlh", // SYSTEMZ_INS_CLRTLH + "clrtne", // SYSTEMZ_INS_CLRTNE + "clrtnh", // SYSTEMZ_INS_CLRTNH + "clrtnhe", // SYSTEMZ_INS_CLRTNHE + "clrtnl", // SYSTEMZ_INS_CLRTNL + "clrtnle", // SYSTEMZ_INS_CLRTNLE + "clrtnlh", // SYSTEMZ_INS_CLRTNLH + "clst", // SYSTEMZ_INS_CLST + "clt", // SYSTEMZ_INS_CLT + "clte", // SYSTEMZ_INS_CLTE + "clth", // SYSTEMZ_INS_CLTH + "clthe", // SYSTEMZ_INS_CLTHE + "cltl", // SYSTEMZ_INS_CLTL + "cltle", // SYSTEMZ_INS_CLTLE + "cltlh", // SYSTEMZ_INS_CLTLH + "cltne", // SYSTEMZ_INS_CLTNE + "cltnh", // SYSTEMZ_INS_CLTNH + "cltnhe", // SYSTEMZ_INS_CLTNHE + "cltnl", // SYSTEMZ_INS_CLTNL + "cltnle", // SYSTEMZ_INS_CLTNLE + "cltnlh", // SYSTEMZ_INS_CLTNLH + "cly", // SYSTEMZ_INS_CLY + "cmpsc", // SYSTEMZ_INS_CMPSC + "cp", // SYSTEMZ_INS_CP + "cpdt", // SYSTEMZ_INS_CPDT + "cpsdr", // SYSTEMZ_INS_CPSDR + "cpxt", // SYSTEMZ_INS_CPXT + "cpya", // SYSTEMZ_INS_CPYA + "cr", // SYSTEMZ_INS_CR + "crb", // SYSTEMZ_INS_CRB + "crbe", // SYSTEMZ_INS_CRBE + "crbh", // SYSTEMZ_INS_CRBH + "crbhe", // SYSTEMZ_INS_CRBHE + "crbl", // SYSTEMZ_INS_CRBL + "crble", // SYSTEMZ_INS_CRBLE + "crblh", // SYSTEMZ_INS_CRBLH + "crbne", // SYSTEMZ_INS_CRBNE + "crbnh", // SYSTEMZ_INS_CRBNH + "crbnhe", // SYSTEMZ_INS_CRBNHE + "crbnl", // SYSTEMZ_INS_CRBNL + "crbnle", // SYSTEMZ_INS_CRBNLE + "crbnlh", // SYSTEMZ_INS_CRBNLH + "crdte", // SYSTEMZ_INS_CRDTE + "crj", // SYSTEMZ_INS_CRJ + "crje", // SYSTEMZ_INS_CRJE + "crjh", // SYSTEMZ_INS_CRJH + "crjhe", // SYSTEMZ_INS_CRJHE + "crjl", // SYSTEMZ_INS_CRJL + "crjle", // SYSTEMZ_INS_CRJLE + "crjlh", // SYSTEMZ_INS_CRJLH + "crjne", // SYSTEMZ_INS_CRJNE + "crjnh", // SYSTEMZ_INS_CRJNH + "crjnhe", // SYSTEMZ_INS_CRJNHE + "crjnl", // SYSTEMZ_INS_CRJNL + "crjnle", // SYSTEMZ_INS_CRJNLE + "crjnlh", // SYSTEMZ_INS_CRJNLH + "crl", // SYSTEMZ_INS_CRL + "crt", // SYSTEMZ_INS_CRT + "crte", // SYSTEMZ_INS_CRTE + "crth", // SYSTEMZ_INS_CRTH + "crthe", // SYSTEMZ_INS_CRTHE + "crtl", // SYSTEMZ_INS_CRTL + "crtle", // SYSTEMZ_INS_CRTLE + "crtlh", // SYSTEMZ_INS_CRTLH + "crtne", // SYSTEMZ_INS_CRTNE + "crtnh", // SYSTEMZ_INS_CRTNH + "crtnhe", // SYSTEMZ_INS_CRTNHE + "crtnl", // SYSTEMZ_INS_CRTNL + "crtnle", // SYSTEMZ_INS_CRTNLE + "crtnlh", // SYSTEMZ_INS_CRTNLH + "cs", // SYSTEMZ_INS_CS + "csch", // SYSTEMZ_INS_CSCH + "csdtr", // SYSTEMZ_INS_CSDTR + "csg", // SYSTEMZ_INS_CSG + "csp", // SYSTEMZ_INS_CSP + "cspg", // SYSTEMZ_INS_CSPG + "csst", // SYSTEMZ_INS_CSST + "csxtr", // SYSTEMZ_INS_CSXTR + "csy", // SYSTEMZ_INS_CSY + "cu12", // SYSTEMZ_INS_CU12 + "cu14", // SYSTEMZ_INS_CU14 + "cu21", // SYSTEMZ_INS_CU21 + "cu24", // SYSTEMZ_INS_CU24 + "cu41", // SYSTEMZ_INS_CU41 + "cu42", // SYSTEMZ_INS_CU42 + "cudtr", // SYSTEMZ_INS_CUDTR + "cuse", // SYSTEMZ_INS_CUSE + "cutfu", // SYSTEMZ_INS_CUTFU + "cuutf", // SYSTEMZ_INS_CUUTF + "cuxtr", // SYSTEMZ_INS_CUXTR + "cvb", // SYSTEMZ_INS_CVB + "cvbg", // SYSTEMZ_INS_CVBG + "cvby", // SYSTEMZ_INS_CVBY + "cvd", // SYSTEMZ_INS_CVD + "cvdg", // SYSTEMZ_INS_CVDG + "cvdy", // SYSTEMZ_INS_CVDY + "cxbr", // SYSTEMZ_INS_CXBR + "cxfbr", // SYSTEMZ_INS_CXFBR + "cxfbra", // SYSTEMZ_INS_CXFBRA + "cxfr", // SYSTEMZ_INS_CXFR + "cxftr", // SYSTEMZ_INS_CXFTR + "cxgbr", // SYSTEMZ_INS_CXGBR + "cxgbra", // SYSTEMZ_INS_CXGBRA + "cxgr", // SYSTEMZ_INS_CXGR + "cxgtr", // SYSTEMZ_INS_CXGTR + "cxgtra", // SYSTEMZ_INS_CXGTRA + "cxlfbr", // SYSTEMZ_INS_CXLFBR + "cxlftr", // SYSTEMZ_INS_CXLFTR + "cxlgbr", // SYSTEMZ_INS_CXLGBR + "cxlgtr", // SYSTEMZ_INS_CXLGTR + "cxpt", // SYSTEMZ_INS_CXPT + "cxr", // SYSTEMZ_INS_CXR + "cxstr", // SYSTEMZ_INS_CXSTR + "cxtr", // SYSTEMZ_INS_CXTR + "cxutr", // SYSTEMZ_INS_CXUTR + "cxzt", // SYSTEMZ_INS_CXZT + "cy", // SYSTEMZ_INS_CY + "czdt", // SYSTEMZ_INS_CZDT + "czxt", // SYSTEMZ_INS_CZXT + "d", // SYSTEMZ_INS_D + "dd", // SYSTEMZ_INS_DD + "ddb", // SYSTEMZ_INS_DDB + "ddbr", // SYSTEMZ_INS_DDBR + "ddr", // SYSTEMZ_INS_DDR + "ddtr", // SYSTEMZ_INS_DDTR + "ddtra", // SYSTEMZ_INS_DDTRA + "de", // SYSTEMZ_INS_DE + "deb", // SYSTEMZ_INS_DEB + "debr", // SYSTEMZ_INS_DEBR + "der", // SYSTEMZ_INS_DER + "dfltcc", // SYSTEMZ_INS_DFLTCC + "diag", // SYSTEMZ_INS_DIAG + "didbr", // SYSTEMZ_INS_DIDBR + "diebr", // SYSTEMZ_INS_DIEBR + "dl", // SYSTEMZ_INS_DL + "dlg", // SYSTEMZ_INS_DLG + "dlgr", // SYSTEMZ_INS_DLGR + "dlr", // SYSTEMZ_INS_DLR + "dp", // SYSTEMZ_INS_DP + "dr", // SYSTEMZ_INS_DR + "dsg", // SYSTEMZ_INS_DSG + "dsgf", // SYSTEMZ_INS_DSGF + "dsgfr", // SYSTEMZ_INS_DSGFR + "dsgr", // SYSTEMZ_INS_DSGR + "dxbr", // SYSTEMZ_INS_DXBR + "dxr", // SYSTEMZ_INS_DXR + "dxtr", // SYSTEMZ_INS_DXTR + "dxtra", // SYSTEMZ_INS_DXTRA + "ear", // SYSTEMZ_INS_EAR + "ecag", // SYSTEMZ_INS_ECAG + "ecctr", // SYSTEMZ_INS_ECCTR + "ecpga", // SYSTEMZ_INS_ECPGA + "ectg", // SYSTEMZ_INS_ECTG + "ed", // SYSTEMZ_INS_ED + "edmk", // SYSTEMZ_INS_EDMK + "eedtr", // SYSTEMZ_INS_EEDTR + "eextr", // SYSTEMZ_INS_EEXTR + "efpc", // SYSTEMZ_INS_EFPC + "epair", // SYSTEMZ_INS_EPAIR + "epar", // SYSTEMZ_INS_EPAR + "epctr", // SYSTEMZ_INS_EPCTR + "epsw", // SYSTEMZ_INS_EPSW + "ereg", // SYSTEMZ_INS_EREG + "eregg", // SYSTEMZ_INS_EREGG + "esair", // SYSTEMZ_INS_ESAIR + "esar", // SYSTEMZ_INS_ESAR + "esdtr", // SYSTEMZ_INS_ESDTR + "esea", // SYSTEMZ_INS_ESEA + "esta", // SYSTEMZ_INS_ESTA + "esxtr", // SYSTEMZ_INS_ESXTR + "etnd", // SYSTEMZ_INS_ETND + "ex", // SYSTEMZ_INS_EX + "exrl", // SYSTEMZ_INS_EXRL + "fidbr", // SYSTEMZ_INS_FIDBR + "fidbra", // SYSTEMZ_INS_FIDBRA + "fidr", // SYSTEMZ_INS_FIDR + "fidtr", // SYSTEMZ_INS_FIDTR + "fiebr", // SYSTEMZ_INS_FIEBR + "fiebra", // SYSTEMZ_INS_FIEBRA + "fier", // SYSTEMZ_INS_FIER + "fixbr", // SYSTEMZ_INS_FIXBR + "fixbra", // SYSTEMZ_INS_FIXBRA + "fixr", // SYSTEMZ_INS_FIXR + "fixtr", // SYSTEMZ_INS_FIXTR + "flogr", // SYSTEMZ_INS_FLOGR + "hdr", // SYSTEMZ_INS_HDR + "her", // SYSTEMZ_INS_HER + "hsch", // SYSTEMZ_INS_HSCH + "iac", // SYSTEMZ_INS_IAC + "ic", // SYSTEMZ_INS_IC + "icm", // SYSTEMZ_INS_ICM + "icmh", // SYSTEMZ_INS_ICMH + "icmy", // SYSTEMZ_INS_ICMY + "icy", // SYSTEMZ_INS_ICY + "idte", // SYSTEMZ_INS_IDTE + "iedtr", // SYSTEMZ_INS_IEDTR + "iextr", // SYSTEMZ_INS_IEXTR + "iihf", // SYSTEMZ_INS_IIHF + "iihh", // SYSTEMZ_INS_IIHH + "iihl", // SYSTEMZ_INS_IIHL + "iilf", // SYSTEMZ_INS_IILF + "iilh", // SYSTEMZ_INS_IILH + "iill", // SYSTEMZ_INS_IILL + "ipk", // SYSTEMZ_INS_IPK + "ipm", // SYSTEMZ_INS_IPM + "ipte", // SYSTEMZ_INS_IPTE + "irbm", // SYSTEMZ_INS_IRBM + "iske", // SYSTEMZ_INS_ISKE + "ivsk", // SYSTEMZ_INS_IVSK + "j", // SYSTEMZ_INS_J + "je", // SYSTEMZ_INS_JE + "jh", // SYSTEMZ_INS_JH + "jhe", // SYSTEMZ_INS_JHE + "jl", // SYSTEMZ_INS_JL + "jle", // SYSTEMZ_INS_JLE + "jlh", // SYSTEMZ_INS_JLH + "jm", // SYSTEMZ_INS_JM + "jne", // SYSTEMZ_INS_JNE + "jnh", // SYSTEMZ_INS_JNH + "jnhe", // SYSTEMZ_INS_JNHE + "jnl", // SYSTEMZ_INS_JNL + "jnle", // SYSTEMZ_INS_JNLE + "jnlh", // SYSTEMZ_INS_JNLH + "jnm", // SYSTEMZ_INS_JNM + "jno", // SYSTEMZ_INS_JNO + "jnp", // SYSTEMZ_INS_JNP + "jnz", // SYSTEMZ_INS_JNZ + "jo", // SYSTEMZ_INS_JO + "jp", // SYSTEMZ_INS_JP + "jz", // SYSTEMZ_INS_JZ + "j_g_lu_", // SYSTEMZ_INS_J_G_LU_ + "j_g_l_e", // SYSTEMZ_INS_J_G_L_E + "j_g_l_h", // SYSTEMZ_INS_J_G_L_H + "j_g_l_he", // SYSTEMZ_INS_J_G_L_HE + "j_g_l_l", // SYSTEMZ_INS_J_G_L_L + "j_g_l_le", // SYSTEMZ_INS_J_G_L_LE + "j_g_l_lh", // SYSTEMZ_INS_J_G_L_LH + "j_g_l_m", // SYSTEMZ_INS_J_G_L_M + "j_g_l_ne", // SYSTEMZ_INS_J_G_L_NE + "j_g_l_nh", // SYSTEMZ_INS_J_G_L_NH + "j_g_l_nhe", // SYSTEMZ_INS_J_G_L_NHE + "j_g_l_nl", // SYSTEMZ_INS_J_G_L_NL + "j_g_l_nle", // SYSTEMZ_INS_J_G_L_NLE + "j_g_l_nlh", // SYSTEMZ_INS_J_G_L_NLH + "j_g_l_nm", // SYSTEMZ_INS_J_G_L_NM + "j_g_l_no", // SYSTEMZ_INS_J_G_L_NO + "j_g_l_np", // SYSTEMZ_INS_J_G_L_NP + "j_g_l_nz", // SYSTEMZ_INS_J_G_L_NZ + "j_g_l_o", // SYSTEMZ_INS_J_G_L_O + "j_g_l_p", // SYSTEMZ_INS_J_G_L_P + "j_g_l_z", // SYSTEMZ_INS_J_G_L_Z + "kdb", // SYSTEMZ_INS_KDB + "kdbr", // SYSTEMZ_INS_KDBR + "kdsa", // SYSTEMZ_INS_KDSA + "kdtr", // SYSTEMZ_INS_KDTR + "keb", // SYSTEMZ_INS_KEB + "kebr", // SYSTEMZ_INS_KEBR + "kimd", // SYSTEMZ_INS_KIMD + "klmd", // SYSTEMZ_INS_KLMD + "km", // SYSTEMZ_INS_KM + "kma", // SYSTEMZ_INS_KMA + "kmac", // SYSTEMZ_INS_KMAC + "kmc", // SYSTEMZ_INS_KMC + "kmctr", // SYSTEMZ_INS_KMCTR + "kmf", // SYSTEMZ_INS_KMF + "kmo", // SYSTEMZ_INS_KMO + "kxbr", // SYSTEMZ_INS_KXBR + "kxtr", // SYSTEMZ_INS_KXTR + "l", // SYSTEMZ_INS_L + "la", // SYSTEMZ_INS_LA + "laa", // SYSTEMZ_INS_LAA + "laag", // SYSTEMZ_INS_LAAG + "laal", // SYSTEMZ_INS_LAAL + "laalg", // SYSTEMZ_INS_LAALG + "lae", // SYSTEMZ_INS_LAE + "laey", // SYSTEMZ_INS_LAEY + "lam", // SYSTEMZ_INS_LAM + "lamy", // SYSTEMZ_INS_LAMY + "lan", // SYSTEMZ_INS_LAN + "lang", // SYSTEMZ_INS_LANG + "lao", // SYSTEMZ_INS_LAO + "laog", // SYSTEMZ_INS_LAOG + "larl", // SYSTEMZ_INS_LARL + "lasp", // SYSTEMZ_INS_LASP + "lat", // SYSTEMZ_INS_LAT + "lax", // SYSTEMZ_INS_LAX + "laxg", // SYSTEMZ_INS_LAXG + "lay", // SYSTEMZ_INS_LAY + "lb", // SYSTEMZ_INS_LB + "lbear", // SYSTEMZ_INS_LBEAR + "lbh", // SYSTEMZ_INS_LBH + "lbr", // SYSTEMZ_INS_LBR + "lcbb", // SYSTEMZ_INS_LCBB + "lcctl", // SYSTEMZ_INS_LCCTL + "lcdbr", // SYSTEMZ_INS_LCDBR + "lcdfr", // SYSTEMZ_INS_LCDFR + "lcdr", // SYSTEMZ_INS_LCDR + "lcebr", // SYSTEMZ_INS_LCEBR + "lcer", // SYSTEMZ_INS_LCER + "lcgfr", // SYSTEMZ_INS_LCGFR + "lcgr", // SYSTEMZ_INS_LCGR + "lcr", // SYSTEMZ_INS_LCR + "lctl", // SYSTEMZ_INS_LCTL + "lctlg", // SYSTEMZ_INS_LCTLG + "lcxbr", // SYSTEMZ_INS_LCXBR + "lcxr", // SYSTEMZ_INS_LCXR + "ld", // SYSTEMZ_INS_LD + "lde", // SYSTEMZ_INS_LDE + "ldeb", // SYSTEMZ_INS_LDEB + "ldebr", // SYSTEMZ_INS_LDEBR + "lder", // SYSTEMZ_INS_LDER + "ldetr", // SYSTEMZ_INS_LDETR + "ldgr", // SYSTEMZ_INS_LDGR + "ldr", // SYSTEMZ_INS_LDR + "ldxbr", // SYSTEMZ_INS_LDXBR + "ldxbra", // SYSTEMZ_INS_LDXBRA + "ldxr", // SYSTEMZ_INS_LDXR + "ldxtr", // SYSTEMZ_INS_LDXTR + "ldy", // SYSTEMZ_INS_LDY + "le", // SYSTEMZ_INS_LE + "ledbr", // SYSTEMZ_INS_LEDBR + "ledbra", // SYSTEMZ_INS_LEDBRA + "ledr", // SYSTEMZ_INS_LEDR + "ledtr", // SYSTEMZ_INS_LEDTR + "ler", // SYSTEMZ_INS_LER + "lexbr", // SYSTEMZ_INS_LEXBR + "lexbra", // SYSTEMZ_INS_LEXBRA + "lexr", // SYSTEMZ_INS_LEXR + "ley", // SYSTEMZ_INS_LEY + "lfas", // SYSTEMZ_INS_LFAS + "lfh", // SYSTEMZ_INS_LFH + "lfhat", // SYSTEMZ_INS_LFHAT + "lfpc", // SYSTEMZ_INS_LFPC + "lg", // SYSTEMZ_INS_LG + "lgat", // SYSTEMZ_INS_LGAT + "lgb", // SYSTEMZ_INS_LGB + "lgbr", // SYSTEMZ_INS_LGBR + "lgdr", // SYSTEMZ_INS_LGDR + "lgf", // SYSTEMZ_INS_LGF + "lgfi", // SYSTEMZ_INS_LGFI + "lgfr", // SYSTEMZ_INS_LGFR + "lgfrl", // SYSTEMZ_INS_LGFRL + "lgg", // SYSTEMZ_INS_LGG + "lgh", // SYSTEMZ_INS_LGH + "lghi", // SYSTEMZ_INS_LGHI + "lghr", // SYSTEMZ_INS_LGHR + "lghrl", // SYSTEMZ_INS_LGHRL + "lgr", // SYSTEMZ_INS_LGR + "lgrl", // SYSTEMZ_INS_LGRL + "lgsc", // SYSTEMZ_INS_LGSC + "lh", // SYSTEMZ_INS_LH + "lhh", // SYSTEMZ_INS_LHH + "lhi", // SYSTEMZ_INS_LHI + "lhr", // SYSTEMZ_INS_LHR + "lhrl", // SYSTEMZ_INS_LHRL + "lhy", // SYSTEMZ_INS_LHY + "llc", // SYSTEMZ_INS_LLC + "llch", // SYSTEMZ_INS_LLCH + "llcr", // SYSTEMZ_INS_LLCR + "llgc", // SYSTEMZ_INS_LLGC + "llgcr", // SYSTEMZ_INS_LLGCR + "llgf", // SYSTEMZ_INS_LLGF + "llgfat", // SYSTEMZ_INS_LLGFAT + "llgfr", // SYSTEMZ_INS_LLGFR + "llgfrl", // SYSTEMZ_INS_LLGFRL + "llgfsg", // SYSTEMZ_INS_LLGFSG + "llgh", // SYSTEMZ_INS_LLGH + "llghr", // SYSTEMZ_INS_LLGHR + "llghrl", // SYSTEMZ_INS_LLGHRL + "llgt", // SYSTEMZ_INS_LLGT + "llgtat", // SYSTEMZ_INS_LLGTAT + "llgtr", // SYSTEMZ_INS_LLGTR + "llh", // SYSTEMZ_INS_LLH + "llhh", // SYSTEMZ_INS_LLHH + "llhr", // SYSTEMZ_INS_LLHR + "llhrl", // SYSTEMZ_INS_LLHRL + "llihf", // SYSTEMZ_INS_LLIHF + "llihh", // SYSTEMZ_INS_LLIHH + "llihl", // SYSTEMZ_INS_LLIHL + "llilf", // SYSTEMZ_INS_LLILF + "llilh", // SYSTEMZ_INS_LLILH + "llill", // SYSTEMZ_INS_LLILL + "llzrgf", // SYSTEMZ_INS_LLZRGF + "lm", // SYSTEMZ_INS_LM + "lmd", // SYSTEMZ_INS_LMD + "lmg", // SYSTEMZ_INS_LMG + "lmh", // SYSTEMZ_INS_LMH + "lmy", // SYSTEMZ_INS_LMY + "lndbr", // SYSTEMZ_INS_LNDBR + "lndfr", // SYSTEMZ_INS_LNDFR + "lndr", // SYSTEMZ_INS_LNDR + "lnebr", // SYSTEMZ_INS_LNEBR + "lner", // SYSTEMZ_INS_LNER + "lngfr", // SYSTEMZ_INS_LNGFR + "lngr", // SYSTEMZ_INS_LNGR + "lnr", // SYSTEMZ_INS_LNR + "lnxbr", // SYSTEMZ_INS_LNXBR + "lnxr", // SYSTEMZ_INS_LNXR + "loc", // SYSTEMZ_INS_LOC + "loce", // SYSTEMZ_INS_LOCE + "loch", // SYSTEMZ_INS_LOCH + "loche", // SYSTEMZ_INS_LOCHE + "locl", // SYSTEMZ_INS_LOCL + "locle", // SYSTEMZ_INS_LOCLE + "loclh", // SYSTEMZ_INS_LOCLH + "locm", // SYSTEMZ_INS_LOCM + "locne", // SYSTEMZ_INS_LOCNE + "locnh", // SYSTEMZ_INS_LOCNH + "locnhe", // SYSTEMZ_INS_LOCNHE + "locnl", // SYSTEMZ_INS_LOCNL + "locnle", // SYSTEMZ_INS_LOCNLE + "locnlh", // SYSTEMZ_INS_LOCNLH + "locnm", // SYSTEMZ_INS_LOCNM + "locno", // SYSTEMZ_INS_LOCNO + "locnp", // SYSTEMZ_INS_LOCNP + "locnz", // SYSTEMZ_INS_LOCNZ + "loco", // SYSTEMZ_INS_LOCO + "locp", // SYSTEMZ_INS_LOCP + "locz", // SYSTEMZ_INS_LOCZ + "locfh", // SYSTEMZ_INS_LOCFH + "locfhe", // SYSTEMZ_INS_LOCFHE + "locfhh", // SYSTEMZ_INS_LOCFHH + "locfhhe", // SYSTEMZ_INS_LOCFHHE + "locfhl", // SYSTEMZ_INS_LOCFHL + "locfhle", // SYSTEMZ_INS_LOCFHLE + "locfhlh", // SYSTEMZ_INS_LOCFHLH + "locfhm", // SYSTEMZ_INS_LOCFHM + "locfhne", // SYSTEMZ_INS_LOCFHNE + "locfhnh", // SYSTEMZ_INS_LOCFHNH + "locfhnhe", // SYSTEMZ_INS_LOCFHNHE + "locfhnl", // SYSTEMZ_INS_LOCFHNL + "locfhnle", // SYSTEMZ_INS_LOCFHNLE + "locfhnlh", // SYSTEMZ_INS_LOCFHNLH + "locfhnm", // SYSTEMZ_INS_LOCFHNM + "locfhno", // SYSTEMZ_INS_LOCFHNO + "locfhnp", // SYSTEMZ_INS_LOCFHNP + "locfhnz", // SYSTEMZ_INS_LOCFHNZ + "locfho", // SYSTEMZ_INS_LOCFHO + "locfhp", // SYSTEMZ_INS_LOCFHP + "locfhz", // SYSTEMZ_INS_LOCFHZ + "locfhr", // SYSTEMZ_INS_LOCFHR + "locfhre", // SYSTEMZ_INS_LOCFHRE + "locfhrh", // SYSTEMZ_INS_LOCFHRH + "locfhrhe", // SYSTEMZ_INS_LOCFHRHE + "locfhrl", // SYSTEMZ_INS_LOCFHRL + "locfhrle", // SYSTEMZ_INS_LOCFHRLE + "locfhrlh", // SYSTEMZ_INS_LOCFHRLH + "locfhrm", // SYSTEMZ_INS_LOCFHRM + "locfhrne", // SYSTEMZ_INS_LOCFHRNE + "locfhrnh", // SYSTEMZ_INS_LOCFHRNH + "locfhrnhe", // SYSTEMZ_INS_LOCFHRNHE + "locfhrnl", // SYSTEMZ_INS_LOCFHRNL + "locfhrnle", // SYSTEMZ_INS_LOCFHRNLE + "locfhrnlh", // SYSTEMZ_INS_LOCFHRNLH + "locfhrnm", // SYSTEMZ_INS_LOCFHRNM + "locfhrno", // SYSTEMZ_INS_LOCFHRNO + "locfhrnp", // SYSTEMZ_INS_LOCFHRNP + "locfhrnz", // SYSTEMZ_INS_LOCFHRNZ + "locfhro", // SYSTEMZ_INS_LOCFHRO + "locfhrp", // SYSTEMZ_INS_LOCFHRP + "locfhrz", // SYSTEMZ_INS_LOCFHRZ + "locg", // SYSTEMZ_INS_LOCG + "locge", // SYSTEMZ_INS_LOCGE + "locgh", // SYSTEMZ_INS_LOCGH + "locghe", // SYSTEMZ_INS_LOCGHE + "locgl", // SYSTEMZ_INS_LOCGL + "locgle", // SYSTEMZ_INS_LOCGLE + "locglh", // SYSTEMZ_INS_LOCGLH + "locgm", // SYSTEMZ_INS_LOCGM + "locgne", // SYSTEMZ_INS_LOCGNE + "locgnh", // SYSTEMZ_INS_LOCGNH + "locgnhe", // SYSTEMZ_INS_LOCGNHE + "locgnl", // SYSTEMZ_INS_LOCGNL + "locgnle", // SYSTEMZ_INS_LOCGNLE + "locgnlh", // SYSTEMZ_INS_LOCGNLH + "locgnm", // SYSTEMZ_INS_LOCGNM + "locgno", // SYSTEMZ_INS_LOCGNO + "locgnp", // SYSTEMZ_INS_LOCGNP + "locgnz", // SYSTEMZ_INS_LOCGNZ + "locgo", // SYSTEMZ_INS_LOCGO + "locgp", // SYSTEMZ_INS_LOCGP + "locgz", // SYSTEMZ_INS_LOCGZ + "locghi", // SYSTEMZ_INS_LOCGHI + "locghie", // SYSTEMZ_INS_LOCGHIE + "locghih", // SYSTEMZ_INS_LOCGHIH + "locghihe", // SYSTEMZ_INS_LOCGHIHE + "locghil", // SYSTEMZ_INS_LOCGHIL + "locghile", // SYSTEMZ_INS_LOCGHILE + "locghilh", // SYSTEMZ_INS_LOCGHILH + "locghim", // SYSTEMZ_INS_LOCGHIM + "locghine", // SYSTEMZ_INS_LOCGHINE + "locghinh", // SYSTEMZ_INS_LOCGHINH + "locghinhe", // SYSTEMZ_INS_LOCGHINHE + "locghinl", // SYSTEMZ_INS_LOCGHINL + "locghinle", // SYSTEMZ_INS_LOCGHINLE + "locghinlh", // SYSTEMZ_INS_LOCGHINLH + "locghinm", // SYSTEMZ_INS_LOCGHINM + "locghino", // SYSTEMZ_INS_LOCGHINO + "locghinp", // SYSTEMZ_INS_LOCGHINP + "locghinz", // SYSTEMZ_INS_LOCGHINZ + "locghio", // SYSTEMZ_INS_LOCGHIO + "locghip", // SYSTEMZ_INS_LOCGHIP + "locghiz", // SYSTEMZ_INS_LOCGHIZ + "locgr", // SYSTEMZ_INS_LOCGR + "locgre", // SYSTEMZ_INS_LOCGRE + "locgrh", // SYSTEMZ_INS_LOCGRH + "locgrhe", // SYSTEMZ_INS_LOCGRHE + "locgrl", // SYSTEMZ_INS_LOCGRL + "locgrle", // SYSTEMZ_INS_LOCGRLE + "locgrlh", // SYSTEMZ_INS_LOCGRLH + "locgrm", // SYSTEMZ_INS_LOCGRM + "locgrne", // SYSTEMZ_INS_LOCGRNE + "locgrnh", // SYSTEMZ_INS_LOCGRNH + "locgrnhe", // SYSTEMZ_INS_LOCGRNHE + "locgrnl", // SYSTEMZ_INS_LOCGRNL + "locgrnle", // SYSTEMZ_INS_LOCGRNLE + "locgrnlh", // SYSTEMZ_INS_LOCGRNLH + "locgrnm", // SYSTEMZ_INS_LOCGRNM + "locgrno", // SYSTEMZ_INS_LOCGRNO + "locgrnp", // SYSTEMZ_INS_LOCGRNP + "locgrnz", // SYSTEMZ_INS_LOCGRNZ + "locgro", // SYSTEMZ_INS_LOCGRO + "locgrp", // SYSTEMZ_INS_LOCGRP + "locgrz", // SYSTEMZ_INS_LOCGRZ + "lochhi", // SYSTEMZ_INS_LOCHHI + "lochhie", // SYSTEMZ_INS_LOCHHIE + "lochhih", // SYSTEMZ_INS_LOCHHIH + "lochhihe", // SYSTEMZ_INS_LOCHHIHE + "lochhil", // SYSTEMZ_INS_LOCHHIL + "lochhile", // SYSTEMZ_INS_LOCHHILE + "lochhilh", // SYSTEMZ_INS_LOCHHILH + "lochhim", // SYSTEMZ_INS_LOCHHIM + "lochhine", // SYSTEMZ_INS_LOCHHINE + "lochhinh", // SYSTEMZ_INS_LOCHHINH + "lochhinhe", // SYSTEMZ_INS_LOCHHINHE + "lochhinl", // SYSTEMZ_INS_LOCHHINL + "lochhinle", // SYSTEMZ_INS_LOCHHINLE + "lochhinlh", // SYSTEMZ_INS_LOCHHINLH + "lochhinm", // SYSTEMZ_INS_LOCHHINM + "lochhino", // SYSTEMZ_INS_LOCHHINO + "lochhinp", // SYSTEMZ_INS_LOCHHINP + "lochhinz", // SYSTEMZ_INS_LOCHHINZ + "lochhio", // SYSTEMZ_INS_LOCHHIO + "lochhip", // SYSTEMZ_INS_LOCHHIP + "lochhiz", // SYSTEMZ_INS_LOCHHIZ + "lochi", // SYSTEMZ_INS_LOCHI + "lochie", // SYSTEMZ_INS_LOCHIE + "lochih", // SYSTEMZ_INS_LOCHIH + "lochihe", // SYSTEMZ_INS_LOCHIHE + "lochil", // SYSTEMZ_INS_LOCHIL + "lochile", // SYSTEMZ_INS_LOCHILE + "lochilh", // SYSTEMZ_INS_LOCHILH + "lochim", // SYSTEMZ_INS_LOCHIM + "lochine", // SYSTEMZ_INS_LOCHINE + "lochinh", // SYSTEMZ_INS_LOCHINH + "lochinhe", // SYSTEMZ_INS_LOCHINHE + "lochinl", // SYSTEMZ_INS_LOCHINL + "lochinle", // SYSTEMZ_INS_LOCHINLE + "lochinlh", // SYSTEMZ_INS_LOCHINLH + "lochinm", // SYSTEMZ_INS_LOCHINM + "lochino", // SYSTEMZ_INS_LOCHINO + "lochinp", // SYSTEMZ_INS_LOCHINP + "lochinz", // SYSTEMZ_INS_LOCHINZ + "lochio", // SYSTEMZ_INS_LOCHIO + "lochip", // SYSTEMZ_INS_LOCHIP + "lochiz", // SYSTEMZ_INS_LOCHIZ + "locr", // SYSTEMZ_INS_LOCR + "locre", // SYSTEMZ_INS_LOCRE + "locrh", // SYSTEMZ_INS_LOCRH + "locrhe", // SYSTEMZ_INS_LOCRHE + "locrl", // SYSTEMZ_INS_LOCRL + "locrle", // SYSTEMZ_INS_LOCRLE + "locrlh", // SYSTEMZ_INS_LOCRLH + "locrm", // SYSTEMZ_INS_LOCRM + "locrne", // SYSTEMZ_INS_LOCRNE + "locrnh", // SYSTEMZ_INS_LOCRNH + "locrnhe", // SYSTEMZ_INS_LOCRNHE + "locrnl", // SYSTEMZ_INS_LOCRNL + "locrnle", // SYSTEMZ_INS_LOCRNLE + "locrnlh", // SYSTEMZ_INS_LOCRNLH + "locrnm", // SYSTEMZ_INS_LOCRNM + "locrno", // SYSTEMZ_INS_LOCRNO + "locrnp", // SYSTEMZ_INS_LOCRNP + "locrnz", // SYSTEMZ_INS_LOCRNZ + "locro", // SYSTEMZ_INS_LOCRO + "locrp", // SYSTEMZ_INS_LOCRP + "locrz", // SYSTEMZ_INS_LOCRZ + "lpctl", // SYSTEMZ_INS_LPCTL + "lpd", // SYSTEMZ_INS_LPD + "lpdbr", // SYSTEMZ_INS_LPDBR + "lpdfr", // SYSTEMZ_INS_LPDFR + "lpdg", // SYSTEMZ_INS_LPDG + "lpdr", // SYSTEMZ_INS_LPDR + "lpebr", // SYSTEMZ_INS_LPEBR + "lper", // SYSTEMZ_INS_LPER + "lpgfr", // SYSTEMZ_INS_LPGFR + "lpgr", // SYSTEMZ_INS_LPGR + "lpp", // SYSTEMZ_INS_LPP + "lpq", // SYSTEMZ_INS_LPQ + "lpr", // SYSTEMZ_INS_LPR + "lpsw", // SYSTEMZ_INS_LPSW + "lpswe", // SYSTEMZ_INS_LPSWE + "lpswey", // SYSTEMZ_INS_LPSWEY + "lptea", // SYSTEMZ_INS_LPTEA + "lpxbr", // SYSTEMZ_INS_LPXBR + "lpxr", // SYSTEMZ_INS_LPXR + "lr", // SYSTEMZ_INS_LR + "lra", // SYSTEMZ_INS_LRA + "lrag", // SYSTEMZ_INS_LRAG + "lray", // SYSTEMZ_INS_LRAY + "lrdr", // SYSTEMZ_INS_LRDR + "lrer", // SYSTEMZ_INS_LRER + "lrl", // SYSTEMZ_INS_LRL + "lrv", // SYSTEMZ_INS_LRV + "lrvg", // SYSTEMZ_INS_LRVG + "lrvgr", // SYSTEMZ_INS_LRVGR + "lrvh", // SYSTEMZ_INS_LRVH + "lrvr", // SYSTEMZ_INS_LRVR + "lsctl", // SYSTEMZ_INS_LSCTL + "lt", // SYSTEMZ_INS_LT + "ltdbr", // SYSTEMZ_INS_LTDBR + "ltdr", // SYSTEMZ_INS_LTDR + "ltdtr", // SYSTEMZ_INS_LTDTR + "ltebr", // SYSTEMZ_INS_LTEBR + "lter", // SYSTEMZ_INS_LTER + "ltg", // SYSTEMZ_INS_LTG + "ltgf", // SYSTEMZ_INS_LTGF + "ltgfr", // SYSTEMZ_INS_LTGFR + "ltgr", // SYSTEMZ_INS_LTGR + "ltr", // SYSTEMZ_INS_LTR + "ltxbr", // SYSTEMZ_INS_LTXBR + "ltxr", // SYSTEMZ_INS_LTXR + "ltxtr", // SYSTEMZ_INS_LTXTR + "lura", // SYSTEMZ_INS_LURA + "lurag", // SYSTEMZ_INS_LURAG + "lxd", // SYSTEMZ_INS_LXD + "lxdb", // SYSTEMZ_INS_LXDB + "lxdbr", // SYSTEMZ_INS_LXDBR + "lxdr", // SYSTEMZ_INS_LXDR + "lxdtr", // SYSTEMZ_INS_LXDTR + "lxe", // SYSTEMZ_INS_LXE + "lxeb", // SYSTEMZ_INS_LXEB + "lxebr", // SYSTEMZ_INS_LXEBR + "lxer", // SYSTEMZ_INS_LXER + "lxr", // SYSTEMZ_INS_LXR + "ly", // SYSTEMZ_INS_LY + "lzdr", // SYSTEMZ_INS_LZDR + "lzer", // SYSTEMZ_INS_LZER + "lzrf", // SYSTEMZ_INS_LZRF + "lzrg", // SYSTEMZ_INS_LZRG + "lzxr", // SYSTEMZ_INS_LZXR + "m", // SYSTEMZ_INS_M + "mad", // SYSTEMZ_INS_MAD + "madb", // SYSTEMZ_INS_MADB + "madbr", // SYSTEMZ_INS_MADBR + "madr", // SYSTEMZ_INS_MADR + "mae", // SYSTEMZ_INS_MAE + "maeb", // SYSTEMZ_INS_MAEB + "maebr", // SYSTEMZ_INS_MAEBR + "maer", // SYSTEMZ_INS_MAER + "may", // SYSTEMZ_INS_MAY + "mayh", // SYSTEMZ_INS_MAYH + "mayhr", // SYSTEMZ_INS_MAYHR + "mayl", // SYSTEMZ_INS_MAYL + "maylr", // SYSTEMZ_INS_MAYLR + "mayr", // SYSTEMZ_INS_MAYR + "mc", // SYSTEMZ_INS_MC + "md", // SYSTEMZ_INS_MD + "mdb", // SYSTEMZ_INS_MDB + "mdbr", // SYSTEMZ_INS_MDBR + "mde", // SYSTEMZ_INS_MDE + "mdeb", // SYSTEMZ_INS_MDEB + "mdebr", // SYSTEMZ_INS_MDEBR + "mder", // SYSTEMZ_INS_MDER + "mdr", // SYSTEMZ_INS_MDR + "mdtr", // SYSTEMZ_INS_MDTR + "mdtra", // SYSTEMZ_INS_MDTRA + "me", // SYSTEMZ_INS_ME + "mee", // SYSTEMZ_INS_MEE + "meeb", // SYSTEMZ_INS_MEEB + "meebr", // SYSTEMZ_INS_MEEBR + "meer", // SYSTEMZ_INS_MEER + "mer", // SYSTEMZ_INS_MER + "mfy", // SYSTEMZ_INS_MFY + "mg", // SYSTEMZ_INS_MG + "mgh", // SYSTEMZ_INS_MGH + "mghi", // SYSTEMZ_INS_MGHI + "mgrk", // SYSTEMZ_INS_MGRK + "mh", // SYSTEMZ_INS_MH + "mhi", // SYSTEMZ_INS_MHI + "mhy", // SYSTEMZ_INS_MHY + "ml", // SYSTEMZ_INS_ML + "mlg", // SYSTEMZ_INS_MLG + "mlgr", // SYSTEMZ_INS_MLGR + "mlr", // SYSTEMZ_INS_MLR + "mp", // SYSTEMZ_INS_MP + "mr", // SYSTEMZ_INS_MR + "ms", // SYSTEMZ_INS_MS + "msc", // SYSTEMZ_INS_MSC + "msch", // SYSTEMZ_INS_MSCH + "msd", // SYSTEMZ_INS_MSD + "msdb", // SYSTEMZ_INS_MSDB + "msdbr", // SYSTEMZ_INS_MSDBR + "msdr", // SYSTEMZ_INS_MSDR + "mse", // SYSTEMZ_INS_MSE + "mseb", // SYSTEMZ_INS_MSEB + "msebr", // SYSTEMZ_INS_MSEBR + "mser", // SYSTEMZ_INS_MSER + "msfi", // SYSTEMZ_INS_MSFI + "msg", // SYSTEMZ_INS_MSG + "msgc", // SYSTEMZ_INS_MSGC + "msgf", // SYSTEMZ_INS_MSGF + "msgfi", // SYSTEMZ_INS_MSGFI + "msgfr", // SYSTEMZ_INS_MSGFR + "msgr", // SYSTEMZ_INS_MSGR + "msgrkc", // SYSTEMZ_INS_MSGRKC + "msr", // SYSTEMZ_INS_MSR + "msrkc", // SYSTEMZ_INS_MSRKC + "msta", // SYSTEMZ_INS_MSTA + "msy", // SYSTEMZ_INS_MSY + "mvc", // SYSTEMZ_INS_MVC + "mvcdk", // SYSTEMZ_INS_MVCDK + "mvcin", // SYSTEMZ_INS_MVCIN + "mvck", // SYSTEMZ_INS_MVCK + "mvcl", // SYSTEMZ_INS_MVCL + "mvcle", // SYSTEMZ_INS_MVCLE + "mvclu", // SYSTEMZ_INS_MVCLU + "mvcos", // SYSTEMZ_INS_MVCOS + "mvcp", // SYSTEMZ_INS_MVCP + "mvcrl", // SYSTEMZ_INS_MVCRL + "mvcs", // SYSTEMZ_INS_MVCS + "mvcsk", // SYSTEMZ_INS_MVCSK + "mvghi", // SYSTEMZ_INS_MVGHI + "mvhhi", // SYSTEMZ_INS_MVHHI + "mvhi", // SYSTEMZ_INS_MVHI + "mvi", // SYSTEMZ_INS_MVI + "mviy", // SYSTEMZ_INS_MVIY + "mvn", // SYSTEMZ_INS_MVN + "mvo", // SYSTEMZ_INS_MVO + "mvpg", // SYSTEMZ_INS_MVPG + "mvst", // SYSTEMZ_INS_MVST + "mvz", // SYSTEMZ_INS_MVZ + "mxbr", // SYSTEMZ_INS_MXBR + "mxd", // SYSTEMZ_INS_MXD + "mxdb", // SYSTEMZ_INS_MXDB + "mxdbr", // SYSTEMZ_INS_MXDBR + "mxdr", // SYSTEMZ_INS_MXDR + "mxr", // SYSTEMZ_INS_MXR + "mxtr", // SYSTEMZ_INS_MXTR + "mxtra", // SYSTEMZ_INS_MXTRA + "my", // SYSTEMZ_INS_MY + "myh", // SYSTEMZ_INS_MYH + "myhr", // SYSTEMZ_INS_MYHR + "myl", // SYSTEMZ_INS_MYL + "mylr", // SYSTEMZ_INS_MYLR + "myr", // SYSTEMZ_INS_MYR + "n", // SYSTEMZ_INS_N + "nc", // SYSTEMZ_INS_NC + "ncgrk", // SYSTEMZ_INS_NCGRK + "ncrk", // SYSTEMZ_INS_NCRK + "ng", // SYSTEMZ_INS_NG + "ngr", // SYSTEMZ_INS_NGR + "ngrk", // SYSTEMZ_INS_NGRK + "ni", // SYSTEMZ_INS_NI + "niai", // SYSTEMZ_INS_NIAI + "nihf", // SYSTEMZ_INS_NIHF + "nihh", // SYSTEMZ_INS_NIHH + "nihl", // SYSTEMZ_INS_NIHL + "nilf", // SYSTEMZ_INS_NILF + "nilh", // SYSTEMZ_INS_NILH + "nill", // SYSTEMZ_INS_NILL + "niy", // SYSTEMZ_INS_NIY + "nngrk", // SYSTEMZ_INS_NNGRK + "nnpa", // SYSTEMZ_INS_NNPA + "nnrk", // SYSTEMZ_INS_NNRK + "nogrk", // SYSTEMZ_INS_NOGRK + "nop", // SYSTEMZ_INS_NOP + "nork", // SYSTEMZ_INS_NORK + "nr", // SYSTEMZ_INS_NR + "nrk", // SYSTEMZ_INS_NRK + "ntstg", // SYSTEMZ_INS_NTSTG + "nxgrk", // SYSTEMZ_INS_NXGRK + "nxrk", // SYSTEMZ_INS_NXRK + "ny", // SYSTEMZ_INS_NY + "o", // SYSTEMZ_INS_O + "oc", // SYSTEMZ_INS_OC + "ocgrk", // SYSTEMZ_INS_OCGRK + "ocrk", // SYSTEMZ_INS_OCRK + "og", // SYSTEMZ_INS_OG + "ogr", // SYSTEMZ_INS_OGR + "ogrk", // SYSTEMZ_INS_OGRK + "oi", // SYSTEMZ_INS_OI + "oihf", // SYSTEMZ_INS_OIHF + "oihh", // SYSTEMZ_INS_OIHH + "oihl", // SYSTEMZ_INS_OIHL + "oilf", // SYSTEMZ_INS_OILF + "oilh", // SYSTEMZ_INS_OILH + "oill", // SYSTEMZ_INS_OILL + "oiy", // SYSTEMZ_INS_OIY + "or", // SYSTEMZ_INS_OR + "ork", // SYSTEMZ_INS_ORK + "oy", // SYSTEMZ_INS_OY + "pack", // SYSTEMZ_INS_PACK + "palb", // SYSTEMZ_INS_PALB + "pc", // SYSTEMZ_INS_PC + "pcc", // SYSTEMZ_INS_PCC + "pckmo", // SYSTEMZ_INS_PCKMO + "pfd", // SYSTEMZ_INS_PFD + "pfdrl", // SYSTEMZ_INS_PFDRL + "pfmf", // SYSTEMZ_INS_PFMF + "pfpo", // SYSTEMZ_INS_PFPO + "pgin", // SYSTEMZ_INS_PGIN + "pgout", // SYSTEMZ_INS_PGOUT + "pka", // SYSTEMZ_INS_PKA + "pku", // SYSTEMZ_INS_PKU + "plo", // SYSTEMZ_INS_PLO + "popcnt", // SYSTEMZ_INS_POPCNT + "ppa", // SYSTEMZ_INS_PPA + "ppno", // SYSTEMZ_INS_PPNO + "pr", // SYSTEMZ_INS_PR + "prno", // SYSTEMZ_INS_PRNO + "pt", // SYSTEMZ_INS_PT + "ptf", // SYSTEMZ_INS_PTF + "ptff", // SYSTEMZ_INS_PTFF + "pti", // SYSTEMZ_INS_PTI + "ptlb", // SYSTEMZ_INS_PTLB + "qadtr", // SYSTEMZ_INS_QADTR + "qaxtr", // SYSTEMZ_INS_QAXTR + "qctri", // SYSTEMZ_INS_QCTRI + "qpaci", // SYSTEMZ_INS_QPACI + "qsi", // SYSTEMZ_INS_QSI + "rchp", // SYSTEMZ_INS_RCHP + "rdp", // SYSTEMZ_INS_RDP + "risbg", // SYSTEMZ_INS_RISBG + "risbgn", // SYSTEMZ_INS_RISBGN + "risbhg", // SYSTEMZ_INS_RISBHG + "risblg", // SYSTEMZ_INS_RISBLG + "rll", // SYSTEMZ_INS_RLL + "rllg", // SYSTEMZ_INS_RLLG + "rnsbg", // SYSTEMZ_INS_RNSBG + "rosbg", // SYSTEMZ_INS_ROSBG + "rp", // SYSTEMZ_INS_RP + "rrbe", // SYSTEMZ_INS_RRBE + "rrbm", // SYSTEMZ_INS_RRBM + "rrdtr", // SYSTEMZ_INS_RRDTR + "rrxtr", // SYSTEMZ_INS_RRXTR + "rsch", // SYSTEMZ_INS_RSCH + "rxsbg", // SYSTEMZ_INS_RXSBG + "s", // SYSTEMZ_INS_S + "sac", // SYSTEMZ_INS_SAC + "sacf", // SYSTEMZ_INS_SACF + "sal", // SYSTEMZ_INS_SAL + "sam24", // SYSTEMZ_INS_SAM24 + "sam31", // SYSTEMZ_INS_SAM31 + "sam64", // SYSTEMZ_INS_SAM64 + "sar", // SYSTEMZ_INS_SAR + "scctr", // SYSTEMZ_INS_SCCTR + "schm", // SYSTEMZ_INS_SCHM + "sck", // SYSTEMZ_INS_SCK + "sckc", // SYSTEMZ_INS_SCKC + "sckpf", // SYSTEMZ_INS_SCKPF + "sd", // SYSTEMZ_INS_SD + "sdb", // SYSTEMZ_INS_SDB + "sdbr", // SYSTEMZ_INS_SDBR + "sdr", // SYSTEMZ_INS_SDR + "sdtr", // SYSTEMZ_INS_SDTR + "sdtra", // SYSTEMZ_INS_SDTRA + "se", // SYSTEMZ_INS_SE + "seb", // SYSTEMZ_INS_SEB + "sebr", // SYSTEMZ_INS_SEBR + "selfhr", // SYSTEMZ_INS_SELFHR + "selfhre", // SYSTEMZ_INS_SELFHRE + "selfhrh", // SYSTEMZ_INS_SELFHRH + "selfhrhe", // SYSTEMZ_INS_SELFHRHE + "selfhrl", // SYSTEMZ_INS_SELFHRL + "selfhrle", // SYSTEMZ_INS_SELFHRLE + "selfhrlh", // SYSTEMZ_INS_SELFHRLH + "selfhrm", // SYSTEMZ_INS_SELFHRM + "selfhrne", // SYSTEMZ_INS_SELFHRNE + "selfhrnh", // SYSTEMZ_INS_SELFHRNH + "selfhrnhe", // SYSTEMZ_INS_SELFHRNHE + "selfhrnl", // SYSTEMZ_INS_SELFHRNL + "selfhrnle", // SYSTEMZ_INS_SELFHRNLE + "selfhrnlh", // SYSTEMZ_INS_SELFHRNLH + "selfhrnm", // SYSTEMZ_INS_SELFHRNM + "selfhrno", // SYSTEMZ_INS_SELFHRNO + "selfhrnp", // SYSTEMZ_INS_SELFHRNP + "selfhrnz", // SYSTEMZ_INS_SELFHRNZ + "selfhro", // SYSTEMZ_INS_SELFHRO + "selfhrp", // SYSTEMZ_INS_SELFHRP + "selfhrz", // SYSTEMZ_INS_SELFHRZ + "selgr", // SYSTEMZ_INS_SELGR + "selgre", // SYSTEMZ_INS_SELGRE + "selgrh", // SYSTEMZ_INS_SELGRH + "selgrhe", // SYSTEMZ_INS_SELGRHE + "selgrl", // SYSTEMZ_INS_SELGRL + "selgrle", // SYSTEMZ_INS_SELGRLE + "selgrlh", // SYSTEMZ_INS_SELGRLH + "selgrm", // SYSTEMZ_INS_SELGRM + "selgrne", // SYSTEMZ_INS_SELGRNE + "selgrnh", // SYSTEMZ_INS_SELGRNH + "selgrnhe", // SYSTEMZ_INS_SELGRNHE + "selgrnl", // SYSTEMZ_INS_SELGRNL + "selgrnle", // SYSTEMZ_INS_SELGRNLE + "selgrnlh", // SYSTEMZ_INS_SELGRNLH + "selgrnm", // SYSTEMZ_INS_SELGRNM + "selgrno", // SYSTEMZ_INS_SELGRNO + "selgrnp", // SYSTEMZ_INS_SELGRNP + "selgrnz", // SYSTEMZ_INS_SELGRNZ + "selgro", // SYSTEMZ_INS_SELGRO + "selgrp", // SYSTEMZ_INS_SELGRP + "selgrz", // SYSTEMZ_INS_SELGRZ + "selr", // SYSTEMZ_INS_SELR + "selre", // SYSTEMZ_INS_SELRE + "selrh", // SYSTEMZ_INS_SELRH + "selrhe", // SYSTEMZ_INS_SELRHE + "selrl", // SYSTEMZ_INS_SELRL + "selrle", // SYSTEMZ_INS_SELRLE + "selrlh", // SYSTEMZ_INS_SELRLH + "selrm", // SYSTEMZ_INS_SELRM + "selrne", // SYSTEMZ_INS_SELRNE + "selrnh", // SYSTEMZ_INS_SELRNH + "selrnhe", // SYSTEMZ_INS_SELRNHE + "selrnl", // SYSTEMZ_INS_SELRNL + "selrnle", // SYSTEMZ_INS_SELRNLE + "selrnlh", // SYSTEMZ_INS_SELRNLH + "selrnm", // SYSTEMZ_INS_SELRNM + "selrno", // SYSTEMZ_INS_SELRNO + "selrnp", // SYSTEMZ_INS_SELRNP + "selrnz", // SYSTEMZ_INS_SELRNZ + "selro", // SYSTEMZ_INS_SELRO + "selrp", // SYSTEMZ_INS_SELRP + "selrz", // SYSTEMZ_INS_SELRZ + "ser", // SYSTEMZ_INS_SER + "sfasr", // SYSTEMZ_INS_SFASR + "sfpc", // SYSTEMZ_INS_SFPC + "sg", // SYSTEMZ_INS_SG + "sgf", // SYSTEMZ_INS_SGF + "sgfr", // SYSTEMZ_INS_SGFR + "sgh", // SYSTEMZ_INS_SGH + "sgr", // SYSTEMZ_INS_SGR + "sgrk", // SYSTEMZ_INS_SGRK + "sh", // SYSTEMZ_INS_SH + "shhhr", // SYSTEMZ_INS_SHHHR + "shhlr", // SYSTEMZ_INS_SHHLR + "shy", // SYSTEMZ_INS_SHY + "sie", // SYSTEMZ_INS_SIE + "siga", // SYSTEMZ_INS_SIGA + "sigp", // SYSTEMZ_INS_SIGP + "sl", // SYSTEMZ_INS_SL + "sla", // SYSTEMZ_INS_SLA + "slag", // SYSTEMZ_INS_SLAG + "slak", // SYSTEMZ_INS_SLAK + "slb", // SYSTEMZ_INS_SLB + "slbg", // SYSTEMZ_INS_SLBG + "slbgr", // SYSTEMZ_INS_SLBGR + "slbr", // SYSTEMZ_INS_SLBR + "slda", // SYSTEMZ_INS_SLDA + "sldl", // SYSTEMZ_INS_SLDL + "sldt", // SYSTEMZ_INS_SLDT + "slfi", // SYSTEMZ_INS_SLFI + "slg", // SYSTEMZ_INS_SLG + "slgf", // SYSTEMZ_INS_SLGF + "slgfi", // SYSTEMZ_INS_SLGFI + "slgfr", // SYSTEMZ_INS_SLGFR + "slgr", // SYSTEMZ_INS_SLGR + "slgrk", // SYSTEMZ_INS_SLGRK + "slhhhr", // SYSTEMZ_INS_SLHHHR + "slhhlr", // SYSTEMZ_INS_SLHHLR + "sll", // SYSTEMZ_INS_SLL + "sllg", // SYSTEMZ_INS_SLLG + "sllk", // SYSTEMZ_INS_SLLK + "slr", // SYSTEMZ_INS_SLR + "slrk", // SYSTEMZ_INS_SLRK + "slxt", // SYSTEMZ_INS_SLXT + "sly", // SYSTEMZ_INS_SLY + "sortl", // SYSTEMZ_INS_SORTL + "sp", // SYSTEMZ_INS_SP + "spctr", // SYSTEMZ_INS_SPCTR + "spka", // SYSTEMZ_INS_SPKA + "spm", // SYSTEMZ_INS_SPM + "spt", // SYSTEMZ_INS_SPT + "spx", // SYSTEMZ_INS_SPX + "sqd", // SYSTEMZ_INS_SQD + "sqdb", // SYSTEMZ_INS_SQDB + "sqdbr", // SYSTEMZ_INS_SQDBR + "sqdr", // SYSTEMZ_INS_SQDR + "sqe", // SYSTEMZ_INS_SQE + "sqeb", // SYSTEMZ_INS_SQEB + "sqebr", // SYSTEMZ_INS_SQEBR + "sqer", // SYSTEMZ_INS_SQER + "sqxbr", // SYSTEMZ_INS_SQXBR + "sqxr", // SYSTEMZ_INS_SQXR + "sr", // SYSTEMZ_INS_SR + "sra", // SYSTEMZ_INS_SRA + "srag", // SYSTEMZ_INS_SRAG + "srak", // SYSTEMZ_INS_SRAK + "srda", // SYSTEMZ_INS_SRDA + "srdl", // SYSTEMZ_INS_SRDL + "srdt", // SYSTEMZ_INS_SRDT + "srk", // SYSTEMZ_INS_SRK + "srl", // SYSTEMZ_INS_SRL + "srlg", // SYSTEMZ_INS_SRLG + "srlk", // SYSTEMZ_INS_SRLK + "srnm", // SYSTEMZ_INS_SRNM + "srnmb", // SYSTEMZ_INS_SRNMB + "srnmt", // SYSTEMZ_INS_SRNMT + "srp", // SYSTEMZ_INS_SRP + "srst", // SYSTEMZ_INS_SRST + "srstu", // SYSTEMZ_INS_SRSTU + "srxt", // SYSTEMZ_INS_SRXT + "ssair", // SYSTEMZ_INS_SSAIR + "ssar", // SYSTEMZ_INS_SSAR + "ssch", // SYSTEMZ_INS_SSCH + "sske", // SYSTEMZ_INS_SSKE + "ssm", // SYSTEMZ_INS_SSM + "st", // SYSTEMZ_INS_ST + "stam", // SYSTEMZ_INS_STAM + "stamy", // SYSTEMZ_INS_STAMY + "stap", // SYSTEMZ_INS_STAP + "stbear", // SYSTEMZ_INS_STBEAR + "stc", // SYSTEMZ_INS_STC + "stch", // SYSTEMZ_INS_STCH + "stck", // SYSTEMZ_INS_STCK + "stckc", // SYSTEMZ_INS_STCKC + "stcke", // SYSTEMZ_INS_STCKE + "stckf", // SYSTEMZ_INS_STCKF + "stcm", // SYSTEMZ_INS_STCM + "stcmh", // SYSTEMZ_INS_STCMH + "stcmy", // SYSTEMZ_INS_STCMY + "stcps", // SYSTEMZ_INS_STCPS + "stcrw", // SYSTEMZ_INS_STCRW + "stctg", // SYSTEMZ_INS_STCTG + "stctl", // SYSTEMZ_INS_STCTL + "stcy", // SYSTEMZ_INS_STCY + "std", // SYSTEMZ_INS_STD + "stdy", // SYSTEMZ_INS_STDY + "ste", // SYSTEMZ_INS_STE + "stey", // SYSTEMZ_INS_STEY + "stfh", // SYSTEMZ_INS_STFH + "stfl", // SYSTEMZ_INS_STFL + "stfle", // SYSTEMZ_INS_STFLE + "stfpc", // SYSTEMZ_INS_STFPC + "stg", // SYSTEMZ_INS_STG + "stgrl", // SYSTEMZ_INS_STGRL + "stgsc", // SYSTEMZ_INS_STGSC + "sth", // SYSTEMZ_INS_STH + "sthh", // SYSTEMZ_INS_STHH + "sthrl", // SYSTEMZ_INS_STHRL + "sthy", // SYSTEMZ_INS_STHY + "stidp", // SYSTEMZ_INS_STIDP + "stm", // SYSTEMZ_INS_STM + "stmg", // SYSTEMZ_INS_STMG + "stmh", // SYSTEMZ_INS_STMH + "stmy", // SYSTEMZ_INS_STMY + "stnsm", // SYSTEMZ_INS_STNSM + "stoc", // SYSTEMZ_INS_STOC + "stoce", // SYSTEMZ_INS_STOCE + "stoch", // SYSTEMZ_INS_STOCH + "stoche", // SYSTEMZ_INS_STOCHE + "stocl", // SYSTEMZ_INS_STOCL + "stocle", // SYSTEMZ_INS_STOCLE + "stoclh", // SYSTEMZ_INS_STOCLH + "stocm", // SYSTEMZ_INS_STOCM + "stocne", // SYSTEMZ_INS_STOCNE + "stocnh", // SYSTEMZ_INS_STOCNH + "stocnhe", // SYSTEMZ_INS_STOCNHE + "stocnl", // SYSTEMZ_INS_STOCNL + "stocnle", // SYSTEMZ_INS_STOCNLE + "stocnlh", // SYSTEMZ_INS_STOCNLH + "stocnm", // SYSTEMZ_INS_STOCNM + "stocno", // SYSTEMZ_INS_STOCNO + "stocnp", // SYSTEMZ_INS_STOCNP + "stocnz", // SYSTEMZ_INS_STOCNZ + "stoco", // SYSTEMZ_INS_STOCO + "stocp", // SYSTEMZ_INS_STOCP + "stocz", // SYSTEMZ_INS_STOCZ + "stocfh", // SYSTEMZ_INS_STOCFH + "stocfhe", // SYSTEMZ_INS_STOCFHE + "stocfhh", // SYSTEMZ_INS_STOCFHH + "stocfhhe", // SYSTEMZ_INS_STOCFHHE + "stocfhl", // SYSTEMZ_INS_STOCFHL + "stocfhle", // SYSTEMZ_INS_STOCFHLE + "stocfhlh", // SYSTEMZ_INS_STOCFHLH + "stocfhm", // SYSTEMZ_INS_STOCFHM + "stocfhne", // SYSTEMZ_INS_STOCFHNE + "stocfhnh", // SYSTEMZ_INS_STOCFHNH + "stocfhnhe", // SYSTEMZ_INS_STOCFHNHE + "stocfhnl", // SYSTEMZ_INS_STOCFHNL + "stocfhnle", // SYSTEMZ_INS_STOCFHNLE + "stocfhnlh", // SYSTEMZ_INS_STOCFHNLH + "stocfhnm", // SYSTEMZ_INS_STOCFHNM + "stocfhno", // SYSTEMZ_INS_STOCFHNO + "stocfhnp", // SYSTEMZ_INS_STOCFHNP + "stocfhnz", // SYSTEMZ_INS_STOCFHNZ + "stocfho", // SYSTEMZ_INS_STOCFHO + "stocfhp", // SYSTEMZ_INS_STOCFHP + "stocfhz", // SYSTEMZ_INS_STOCFHZ + "stocg", // SYSTEMZ_INS_STOCG + "stocge", // SYSTEMZ_INS_STOCGE + "stocgh", // SYSTEMZ_INS_STOCGH + "stocghe", // SYSTEMZ_INS_STOCGHE + "stocgl", // SYSTEMZ_INS_STOCGL + "stocgle", // SYSTEMZ_INS_STOCGLE + "stocglh", // SYSTEMZ_INS_STOCGLH + "stocgm", // SYSTEMZ_INS_STOCGM + "stocgne", // SYSTEMZ_INS_STOCGNE + "stocgnh", // SYSTEMZ_INS_STOCGNH + "stocgnhe", // SYSTEMZ_INS_STOCGNHE + "stocgnl", // SYSTEMZ_INS_STOCGNL + "stocgnle", // SYSTEMZ_INS_STOCGNLE + "stocgnlh", // SYSTEMZ_INS_STOCGNLH + "stocgnm", // SYSTEMZ_INS_STOCGNM + "stocgno", // SYSTEMZ_INS_STOCGNO + "stocgnp", // SYSTEMZ_INS_STOCGNP + "stocgnz", // SYSTEMZ_INS_STOCGNZ + "stocgo", // SYSTEMZ_INS_STOCGO + "stocgp", // SYSTEMZ_INS_STOCGP + "stocgz", // SYSTEMZ_INS_STOCGZ + "stosm", // SYSTEMZ_INS_STOSM + "stpq", // SYSTEMZ_INS_STPQ + "stpt", // SYSTEMZ_INS_STPT + "stpx", // SYSTEMZ_INS_STPX + "strag", // SYSTEMZ_INS_STRAG + "strl", // SYSTEMZ_INS_STRL + "strv", // SYSTEMZ_INS_STRV + "strvg", // SYSTEMZ_INS_STRVG + "strvh", // SYSTEMZ_INS_STRVH + "stsch", // SYSTEMZ_INS_STSCH + "stsi", // SYSTEMZ_INS_STSI + "stura", // SYSTEMZ_INS_STURA + "sturg", // SYSTEMZ_INS_STURG + "sty", // SYSTEMZ_INS_STY + "su", // SYSTEMZ_INS_SU + "sur", // SYSTEMZ_INS_SUR + "svc", // SYSTEMZ_INS_SVC + "sw", // SYSTEMZ_INS_SW + "swr", // SYSTEMZ_INS_SWR + "sxbr", // SYSTEMZ_INS_SXBR + "sxr", // SYSTEMZ_INS_SXR + "sxtr", // SYSTEMZ_INS_SXTR + "sxtra", // SYSTEMZ_INS_SXTRA + "sy", // SYSTEMZ_INS_SY + "tabort", // SYSTEMZ_INS_TABORT + "tam", // SYSTEMZ_INS_TAM + "tar", // SYSTEMZ_INS_TAR + "tb", // SYSTEMZ_INS_TB + "tbdr", // SYSTEMZ_INS_TBDR + "tbedr", // SYSTEMZ_INS_TBEDR + "tbegin", // SYSTEMZ_INS_TBEGIN + "tbeginc", // SYSTEMZ_INS_TBEGINC + "tcdb", // SYSTEMZ_INS_TCDB + "tceb", // SYSTEMZ_INS_TCEB + "tcxb", // SYSTEMZ_INS_TCXB + "tdcdt", // SYSTEMZ_INS_TDCDT + "tdcet", // SYSTEMZ_INS_TDCET + "tdcxt", // SYSTEMZ_INS_TDCXT + "tdgdt", // SYSTEMZ_INS_TDGDT + "tdget", // SYSTEMZ_INS_TDGET + "tdgxt", // SYSTEMZ_INS_TDGXT + "tend", // SYSTEMZ_INS_TEND + "thder", // SYSTEMZ_INS_THDER + "thdr", // SYSTEMZ_INS_THDR + "tm", // SYSTEMZ_INS_TM + "tmhh", // SYSTEMZ_INS_TMHH + "tmhl", // SYSTEMZ_INS_TMHL + "tmlh", // SYSTEMZ_INS_TMLH + "tmll", // SYSTEMZ_INS_TMLL + "tmy", // SYSTEMZ_INS_TMY + "tp", // SYSTEMZ_INS_TP + "tpi", // SYSTEMZ_INS_TPI + "tprot", // SYSTEMZ_INS_TPROT + "tr", // SYSTEMZ_INS_TR + "trace", // SYSTEMZ_INS_TRACE + "tracg", // SYSTEMZ_INS_TRACG + "trap2", // SYSTEMZ_INS_TRAP2 + "trap4", // SYSTEMZ_INS_TRAP4 + "tre", // SYSTEMZ_INS_TRE + "troo", // SYSTEMZ_INS_TROO + "trot", // SYSTEMZ_INS_TROT + "trt", // SYSTEMZ_INS_TRT + "trte", // SYSTEMZ_INS_TRTE + "trto", // SYSTEMZ_INS_TRTO + "trtr", // SYSTEMZ_INS_TRTR + "trtre", // SYSTEMZ_INS_TRTRE + "trtt", // SYSTEMZ_INS_TRTT + "ts", // SYSTEMZ_INS_TS + "tsch", // SYSTEMZ_INS_TSCH + "unpk", // SYSTEMZ_INS_UNPK + "unpka", // SYSTEMZ_INS_UNPKA + "unpku", // SYSTEMZ_INS_UNPKU + "upt", // SYSTEMZ_INS_UPT + "va", // SYSTEMZ_INS_VA + "vab", // SYSTEMZ_INS_VAB + "vac", // SYSTEMZ_INS_VAC + "vacc", // SYSTEMZ_INS_VACC + "vaccb", // SYSTEMZ_INS_VACCB + "vaccc", // SYSTEMZ_INS_VACCC + "vacccq", // SYSTEMZ_INS_VACCCQ + "vaccf", // SYSTEMZ_INS_VACCF + "vaccg", // SYSTEMZ_INS_VACCG + "vacch", // SYSTEMZ_INS_VACCH + "vaccq", // SYSTEMZ_INS_VACCQ + "vacq", // SYSTEMZ_INS_VACQ + "vaf", // SYSTEMZ_INS_VAF + "vag", // SYSTEMZ_INS_VAG + "vah", // SYSTEMZ_INS_VAH + "vap", // SYSTEMZ_INS_VAP + "vaq", // SYSTEMZ_INS_VAQ + "vavg", // SYSTEMZ_INS_VAVG + "vavgb", // SYSTEMZ_INS_VAVGB + "vavgf", // SYSTEMZ_INS_VAVGF + "vavgg", // SYSTEMZ_INS_VAVGG + "vavgh", // SYSTEMZ_INS_VAVGH + "vavgl", // SYSTEMZ_INS_VAVGL + "vavglb", // SYSTEMZ_INS_VAVGLB + "vavglf", // SYSTEMZ_INS_VAVGLF + "vavglg", // SYSTEMZ_INS_VAVGLG + "vavglh", // SYSTEMZ_INS_VAVGLH + "vbperm", // SYSTEMZ_INS_VBPERM + "vcdg", // SYSTEMZ_INS_VCDG + "vcdgb", // SYSTEMZ_INS_VCDGB + "vcdlg", // SYSTEMZ_INS_VCDLG + "vcdlgb", // SYSTEMZ_INS_VCDLGB + "vcefb", // SYSTEMZ_INS_VCEFB + "vcelfb", // SYSTEMZ_INS_VCELFB + "vceq", // SYSTEMZ_INS_VCEQ + "vceqb", // SYSTEMZ_INS_VCEQB + "vceqbs", // SYSTEMZ_INS_VCEQBS + "vceqf", // SYSTEMZ_INS_VCEQF + "vceqfs", // SYSTEMZ_INS_VCEQFS + "vceqg", // SYSTEMZ_INS_VCEQG + "vceqgs", // SYSTEMZ_INS_VCEQGS + "vceqh", // SYSTEMZ_INS_VCEQH + "vceqhs", // SYSTEMZ_INS_VCEQHS + "vcfeb", // SYSTEMZ_INS_VCFEB + "vcfn", // SYSTEMZ_INS_VCFN + "vcfpl", // SYSTEMZ_INS_VCFPL + "vcfps", // SYSTEMZ_INS_VCFPS + "vcgd", // SYSTEMZ_INS_VCGD + "vcgdb", // SYSTEMZ_INS_VCGDB + "vch", // SYSTEMZ_INS_VCH + "vchb", // SYSTEMZ_INS_VCHB + "vchbs", // SYSTEMZ_INS_VCHBS + "vchf", // SYSTEMZ_INS_VCHF + "vchfs", // SYSTEMZ_INS_VCHFS + "vchg", // SYSTEMZ_INS_VCHG + "vchgs", // SYSTEMZ_INS_VCHGS + "vchh", // SYSTEMZ_INS_VCHH + "vchhs", // SYSTEMZ_INS_VCHHS + "vchl", // SYSTEMZ_INS_VCHL + "vchlb", // SYSTEMZ_INS_VCHLB + "vchlbs", // SYSTEMZ_INS_VCHLBS + "vchlf", // SYSTEMZ_INS_VCHLF + "vchlfs", // SYSTEMZ_INS_VCHLFS + "vchlg", // SYSTEMZ_INS_VCHLG + "vchlgs", // SYSTEMZ_INS_VCHLGS + "vchlh", // SYSTEMZ_INS_VCHLH + "vchlhs", // SYSTEMZ_INS_VCHLHS + "vcksm", // SYSTEMZ_INS_VCKSM + "vclfeb", // SYSTEMZ_INS_VCLFEB + "vclfnh", // SYSTEMZ_INS_VCLFNH + "vclfnl", // SYSTEMZ_INS_VCLFNL + "vclfp", // SYSTEMZ_INS_VCLFP + "vclgd", // SYSTEMZ_INS_VCLGD + "vclgdb", // SYSTEMZ_INS_VCLGDB + "vclz", // SYSTEMZ_INS_VCLZ + "vclzb", // SYSTEMZ_INS_VCLZB + "vclzdp", // SYSTEMZ_INS_VCLZDP + "vclzf", // SYSTEMZ_INS_VCLZF + "vclzg", // SYSTEMZ_INS_VCLZG + "vclzh", // SYSTEMZ_INS_VCLZH + "vcnf", // SYSTEMZ_INS_VCNF + "vcp", // SYSTEMZ_INS_VCP + "vcrnf", // SYSTEMZ_INS_VCRNF + "vcsfp", // SYSTEMZ_INS_VCSFP + "vcsph", // SYSTEMZ_INS_VCSPH + "vctz", // SYSTEMZ_INS_VCTZ + "vctzb", // SYSTEMZ_INS_VCTZB + "vctzf", // SYSTEMZ_INS_VCTZF + "vctzg", // SYSTEMZ_INS_VCTZG + "vctzh", // SYSTEMZ_INS_VCTZH + "vcvb", // SYSTEMZ_INS_VCVB + "vcvbg", // SYSTEMZ_INS_VCVBG + "vcvd", // SYSTEMZ_INS_VCVD + "vcvdg", // SYSTEMZ_INS_VCVDG + "vdp", // SYSTEMZ_INS_VDP + "vec", // SYSTEMZ_INS_VEC + "vecb", // SYSTEMZ_INS_VECB + "vecf", // SYSTEMZ_INS_VECF + "vecg", // SYSTEMZ_INS_VECG + "vech", // SYSTEMZ_INS_VECH + "vecl", // SYSTEMZ_INS_VECL + "veclb", // SYSTEMZ_INS_VECLB + "veclf", // SYSTEMZ_INS_VECLF + "veclg", // SYSTEMZ_INS_VECLG + "veclh", // SYSTEMZ_INS_VECLH + "verim", // SYSTEMZ_INS_VERIM + "verimb", // SYSTEMZ_INS_VERIMB + "verimf", // SYSTEMZ_INS_VERIMF + "verimg", // SYSTEMZ_INS_VERIMG + "verimh", // SYSTEMZ_INS_VERIMH + "verll", // SYSTEMZ_INS_VERLL + "verllb", // SYSTEMZ_INS_VERLLB + "verllf", // SYSTEMZ_INS_VERLLF + "verllg", // SYSTEMZ_INS_VERLLG + "verllh", // SYSTEMZ_INS_VERLLH + "verllv", // SYSTEMZ_INS_VERLLV + "verllvb", // SYSTEMZ_INS_VERLLVB + "verllvf", // SYSTEMZ_INS_VERLLVF + "verllvg", // SYSTEMZ_INS_VERLLVG + "verllvh", // SYSTEMZ_INS_VERLLVH + "vesl", // SYSTEMZ_INS_VESL + "veslb", // SYSTEMZ_INS_VESLB + "veslf", // SYSTEMZ_INS_VESLF + "veslg", // SYSTEMZ_INS_VESLG + "veslh", // SYSTEMZ_INS_VESLH + "veslv", // SYSTEMZ_INS_VESLV + "veslvb", // SYSTEMZ_INS_VESLVB + "veslvf", // SYSTEMZ_INS_VESLVF + "veslvg", // SYSTEMZ_INS_VESLVG + "veslvh", // SYSTEMZ_INS_VESLVH + "vesra", // SYSTEMZ_INS_VESRA + "vesrab", // SYSTEMZ_INS_VESRAB + "vesraf", // SYSTEMZ_INS_VESRAF + "vesrag", // SYSTEMZ_INS_VESRAG + "vesrah", // SYSTEMZ_INS_VESRAH + "vesrav", // SYSTEMZ_INS_VESRAV + "vesravb", // SYSTEMZ_INS_VESRAVB + "vesravf", // SYSTEMZ_INS_VESRAVF + "vesravg", // SYSTEMZ_INS_VESRAVG + "vesravh", // SYSTEMZ_INS_VESRAVH + "vesrl", // SYSTEMZ_INS_VESRL + "vesrlb", // SYSTEMZ_INS_VESRLB + "vesrlf", // SYSTEMZ_INS_VESRLF + "vesrlg", // SYSTEMZ_INS_VESRLG + "vesrlh", // SYSTEMZ_INS_VESRLH + "vesrlv", // SYSTEMZ_INS_VESRLV + "vesrlvb", // SYSTEMZ_INS_VESRLVB + "vesrlvf", // SYSTEMZ_INS_VESRLVF + "vesrlvg", // SYSTEMZ_INS_VESRLVG + "vesrlvh", // SYSTEMZ_INS_VESRLVH + "vfa", // SYSTEMZ_INS_VFA + "vfadb", // SYSTEMZ_INS_VFADB + "vfae", // SYSTEMZ_INS_VFAE + "vfaeb", // SYSTEMZ_INS_VFAEB + "vfaebs", // SYSTEMZ_INS_VFAEBS + "vfaef", // SYSTEMZ_INS_VFAEF + "vfaefs", // SYSTEMZ_INS_VFAEFS + "vfaeh", // SYSTEMZ_INS_VFAEH + "vfaehs", // SYSTEMZ_INS_VFAEHS + "vfaezb", // SYSTEMZ_INS_VFAEZB + "vfaezbs", // SYSTEMZ_INS_VFAEZBS + "vfaezf", // SYSTEMZ_INS_VFAEZF + "vfaezfs", // SYSTEMZ_INS_VFAEZFS + "vfaezh", // SYSTEMZ_INS_VFAEZH + "vfaezhs", // SYSTEMZ_INS_VFAEZHS + "vfasb", // SYSTEMZ_INS_VFASB + "vfce", // SYSTEMZ_INS_VFCE + "vfcedb", // SYSTEMZ_INS_VFCEDB + "vfcedbs", // SYSTEMZ_INS_VFCEDBS + "vfcesb", // SYSTEMZ_INS_VFCESB + "vfcesbs", // SYSTEMZ_INS_VFCESBS + "vfch", // SYSTEMZ_INS_VFCH + "vfchdb", // SYSTEMZ_INS_VFCHDB + "vfchdbs", // SYSTEMZ_INS_VFCHDBS + "vfche", // SYSTEMZ_INS_VFCHE + "vfchedb", // SYSTEMZ_INS_VFCHEDB + "vfchedbs", // SYSTEMZ_INS_VFCHEDBS + "vfchesb", // SYSTEMZ_INS_VFCHESB + "vfchesbs", // SYSTEMZ_INS_VFCHESBS + "vfchsb", // SYSTEMZ_INS_VFCHSB + "vfchsbs", // SYSTEMZ_INS_VFCHSBS + "vfd", // SYSTEMZ_INS_VFD + "vfddb", // SYSTEMZ_INS_VFDDB + "vfdsb", // SYSTEMZ_INS_VFDSB + "vfee", // SYSTEMZ_INS_VFEE + "vfeeb", // SYSTEMZ_INS_VFEEB + "vfeebs", // SYSTEMZ_INS_VFEEBS + "vfeef", // SYSTEMZ_INS_VFEEF + "vfeefs", // SYSTEMZ_INS_VFEEFS + "vfeeh", // SYSTEMZ_INS_VFEEH + "vfeehs", // SYSTEMZ_INS_VFEEHS + "vfeezb", // SYSTEMZ_INS_VFEEZB + "vfeezbs", // SYSTEMZ_INS_VFEEZBS + "vfeezf", // SYSTEMZ_INS_VFEEZF + "vfeezfs", // SYSTEMZ_INS_VFEEZFS + "vfeezh", // SYSTEMZ_INS_VFEEZH + "vfeezhs", // SYSTEMZ_INS_VFEEZHS + "vfene", // SYSTEMZ_INS_VFENE + "vfeneb", // SYSTEMZ_INS_VFENEB + "vfenebs", // SYSTEMZ_INS_VFENEBS + "vfenef", // SYSTEMZ_INS_VFENEF + "vfenefs", // SYSTEMZ_INS_VFENEFS + "vfeneh", // SYSTEMZ_INS_VFENEH + "vfenehs", // SYSTEMZ_INS_VFENEHS + "vfenezb", // SYSTEMZ_INS_VFENEZB + "vfenezbs", // SYSTEMZ_INS_VFENEZBS + "vfenezf", // SYSTEMZ_INS_VFENEZF + "vfenezfs", // SYSTEMZ_INS_VFENEZFS + "vfenezh", // SYSTEMZ_INS_VFENEZH + "vfenezhs", // SYSTEMZ_INS_VFENEZHS + "vfi", // SYSTEMZ_INS_VFI + "vfidb", // SYSTEMZ_INS_VFIDB + "vfisb", // SYSTEMZ_INS_VFISB + "vfkedb", // SYSTEMZ_INS_VFKEDB + "vfkedbs", // SYSTEMZ_INS_VFKEDBS + "vfkesb", // SYSTEMZ_INS_VFKESB + "vfkesbs", // SYSTEMZ_INS_VFKESBS + "vfkhdb", // SYSTEMZ_INS_VFKHDB + "vfkhdbs", // SYSTEMZ_INS_VFKHDBS + "vfkhedb", // SYSTEMZ_INS_VFKHEDB + "vfkhedbs", // SYSTEMZ_INS_VFKHEDBS + "vfkhesb", // SYSTEMZ_INS_VFKHESB + "vfkhesbs", // SYSTEMZ_INS_VFKHESBS + "vfkhsb", // SYSTEMZ_INS_VFKHSB + "vfkhsbs", // SYSTEMZ_INS_VFKHSBS + "vflcdb", // SYSTEMZ_INS_VFLCDB + "vflcsb", // SYSTEMZ_INS_VFLCSB + "vfll", // SYSTEMZ_INS_VFLL + "vflls", // SYSTEMZ_INS_VFLLS + "vflndb", // SYSTEMZ_INS_VFLNDB + "vflnsb", // SYSTEMZ_INS_VFLNSB + "vflpdb", // SYSTEMZ_INS_VFLPDB + "vflpsb", // SYSTEMZ_INS_VFLPSB + "vflr", // SYSTEMZ_INS_VFLR + "vflrd", // SYSTEMZ_INS_VFLRD + "vfm", // SYSTEMZ_INS_VFM + "vfma", // SYSTEMZ_INS_VFMA + "vfmadb", // SYSTEMZ_INS_VFMADB + "vfmasb", // SYSTEMZ_INS_VFMASB + "vfmax", // SYSTEMZ_INS_VFMAX + "vfmaxdb", // SYSTEMZ_INS_VFMAXDB + "vfmaxsb", // SYSTEMZ_INS_VFMAXSB + "vfmdb", // SYSTEMZ_INS_VFMDB + "vfmin", // SYSTEMZ_INS_VFMIN + "vfmindb", // SYSTEMZ_INS_VFMINDB + "vfminsb", // SYSTEMZ_INS_VFMINSB + "vfms", // SYSTEMZ_INS_VFMS + "vfmsb", // SYSTEMZ_INS_VFMSB + "vfmsdb", // SYSTEMZ_INS_VFMSDB + "vfmssb", // SYSTEMZ_INS_VFMSSB + "vfnma", // SYSTEMZ_INS_VFNMA + "vfnmadb", // SYSTEMZ_INS_VFNMADB + "vfnmasb", // SYSTEMZ_INS_VFNMASB + "vfnms", // SYSTEMZ_INS_VFNMS + "vfnmsdb", // SYSTEMZ_INS_VFNMSDB + "vfnmssb", // SYSTEMZ_INS_VFNMSSB + "vfpso", // SYSTEMZ_INS_VFPSO + "vfpsodb", // SYSTEMZ_INS_VFPSODB + "vfpsosb", // SYSTEMZ_INS_VFPSOSB + "vfs", // SYSTEMZ_INS_VFS + "vfsdb", // SYSTEMZ_INS_VFSDB + "vfsq", // SYSTEMZ_INS_VFSQ + "vfsqdb", // SYSTEMZ_INS_VFSQDB + "vfsqsb", // SYSTEMZ_INS_VFSQSB + "vfssb", // SYSTEMZ_INS_VFSSB + "vftci", // SYSTEMZ_INS_VFTCI + "vftcidb", // SYSTEMZ_INS_VFTCIDB + "vftcisb", // SYSTEMZ_INS_VFTCISB + "vgbm", // SYSTEMZ_INS_VGBM + "vgef", // SYSTEMZ_INS_VGEF + "vgeg", // SYSTEMZ_INS_VGEG + "vgfm", // SYSTEMZ_INS_VGFM + "vgfma", // SYSTEMZ_INS_VGFMA + "vgfmab", // SYSTEMZ_INS_VGFMAB + "vgfmaf", // SYSTEMZ_INS_VGFMAF + "vgfmag", // SYSTEMZ_INS_VGFMAG + "vgfmah", // SYSTEMZ_INS_VGFMAH + "vgfmb", // SYSTEMZ_INS_VGFMB + "vgfmf", // SYSTEMZ_INS_VGFMF + "vgfmg", // SYSTEMZ_INS_VGFMG + "vgfmh", // SYSTEMZ_INS_VGFMH + "vgm", // SYSTEMZ_INS_VGM + "vgmb", // SYSTEMZ_INS_VGMB + "vgmf", // SYSTEMZ_INS_VGMF + "vgmg", // SYSTEMZ_INS_VGMG + "vgmh", // SYSTEMZ_INS_VGMH + "vistr", // SYSTEMZ_INS_VISTR + "vistrb", // SYSTEMZ_INS_VISTRB + "vistrbs", // SYSTEMZ_INS_VISTRBS + "vistrf", // SYSTEMZ_INS_VISTRF + "vistrfs", // SYSTEMZ_INS_VISTRFS + "vistrh", // SYSTEMZ_INS_VISTRH + "vistrhs", // SYSTEMZ_INS_VISTRHS + "vl", // SYSTEMZ_INS_VL + "vlbb", // SYSTEMZ_INS_VLBB + "vlbr", // SYSTEMZ_INS_VLBR + "vlbrf", // SYSTEMZ_INS_VLBRF + "vlbrg", // SYSTEMZ_INS_VLBRG + "vlbrh", // SYSTEMZ_INS_VLBRH + "vlbrq", // SYSTEMZ_INS_VLBRQ + "vlbrrep", // SYSTEMZ_INS_VLBRREP + "vlbrrepf", // SYSTEMZ_INS_VLBRREPF + "vlbrrepg", // SYSTEMZ_INS_VLBRREPG + "vlbrreph", // SYSTEMZ_INS_VLBRREPH + "vlc", // SYSTEMZ_INS_VLC + "vlcb", // SYSTEMZ_INS_VLCB + "vlcf", // SYSTEMZ_INS_VLCF + "vlcg", // SYSTEMZ_INS_VLCG + "vlch", // SYSTEMZ_INS_VLCH + "vlde", // SYSTEMZ_INS_VLDE + "vldeb", // SYSTEMZ_INS_VLDEB + "vleb", // SYSTEMZ_INS_VLEB + "vlebrf", // SYSTEMZ_INS_VLEBRF + "vlebrg", // SYSTEMZ_INS_VLEBRG + "vlebrh", // SYSTEMZ_INS_VLEBRH + "vled", // SYSTEMZ_INS_VLED + "vledb", // SYSTEMZ_INS_VLEDB + "vlef", // SYSTEMZ_INS_VLEF + "vleg", // SYSTEMZ_INS_VLEG + "vleh", // SYSTEMZ_INS_VLEH + "vleib", // SYSTEMZ_INS_VLEIB + "vleif", // SYSTEMZ_INS_VLEIF + "vleig", // SYSTEMZ_INS_VLEIG + "vleih", // SYSTEMZ_INS_VLEIH + "vler", // SYSTEMZ_INS_VLER + "vlerf", // SYSTEMZ_INS_VLERF + "vlerg", // SYSTEMZ_INS_VLERG + "vlerh", // SYSTEMZ_INS_VLERH + "vlgv", // SYSTEMZ_INS_VLGV + "vlgvb", // SYSTEMZ_INS_VLGVB + "vlgvf", // SYSTEMZ_INS_VLGVF + "vlgvg", // SYSTEMZ_INS_VLGVG + "vlgvh", // SYSTEMZ_INS_VLGVH + "vlip", // SYSTEMZ_INS_VLIP + "vll", // SYSTEMZ_INS_VLL + "vllebrz", // SYSTEMZ_INS_VLLEBRZ + "vllebrze", // SYSTEMZ_INS_VLLEBRZE + "vllebrzf", // SYSTEMZ_INS_VLLEBRZF + "vllebrzg", // SYSTEMZ_INS_VLLEBRZG + "vllebrzh", // SYSTEMZ_INS_VLLEBRZH + "vllez", // SYSTEMZ_INS_VLLEZ + "vllezb", // SYSTEMZ_INS_VLLEZB + "vllezf", // SYSTEMZ_INS_VLLEZF + "vllezg", // SYSTEMZ_INS_VLLEZG + "vllezh", // SYSTEMZ_INS_VLLEZH + "vllezlf", // SYSTEMZ_INS_VLLEZLF + "vlm", // SYSTEMZ_INS_VLM + "vlp", // SYSTEMZ_INS_VLP + "vlpb", // SYSTEMZ_INS_VLPB + "vlpf", // SYSTEMZ_INS_VLPF + "vlpg", // SYSTEMZ_INS_VLPG + "vlph", // SYSTEMZ_INS_VLPH + "vlr", // SYSTEMZ_INS_VLR + "vlrep", // SYSTEMZ_INS_VLREP + "vlrepb", // SYSTEMZ_INS_VLREPB + "vlrepf", // SYSTEMZ_INS_VLREPF + "vlrepg", // SYSTEMZ_INS_VLREPG + "vlreph", // SYSTEMZ_INS_VLREPH + "vlrl", // SYSTEMZ_INS_VLRL + "vlrlr", // SYSTEMZ_INS_VLRLR + "vlvg", // SYSTEMZ_INS_VLVG + "vlvgb", // SYSTEMZ_INS_VLVGB + "vlvgf", // SYSTEMZ_INS_VLVGF + "vlvgg", // SYSTEMZ_INS_VLVGG + "vlvgh", // SYSTEMZ_INS_VLVGH + "vlvgp", // SYSTEMZ_INS_VLVGP + "vmae", // SYSTEMZ_INS_VMAE + "vmaeb", // SYSTEMZ_INS_VMAEB + "vmaef", // SYSTEMZ_INS_VMAEF + "vmaeh", // SYSTEMZ_INS_VMAEH + "vmah", // SYSTEMZ_INS_VMAH + "vmahb", // SYSTEMZ_INS_VMAHB + "vmahf", // SYSTEMZ_INS_VMAHF + "vmahh", // SYSTEMZ_INS_VMAHH + "vmal", // SYSTEMZ_INS_VMAL + "vmalb", // SYSTEMZ_INS_VMALB + "vmale", // SYSTEMZ_INS_VMALE + "vmaleb", // SYSTEMZ_INS_VMALEB + "vmalef", // SYSTEMZ_INS_VMALEF + "vmaleh", // SYSTEMZ_INS_VMALEH + "vmalf", // SYSTEMZ_INS_VMALF + "vmalh", // SYSTEMZ_INS_VMALH + "vmalhb", // SYSTEMZ_INS_VMALHB + "vmalhf", // SYSTEMZ_INS_VMALHF + "vmalhh", // SYSTEMZ_INS_VMALHH + "vmalhw", // SYSTEMZ_INS_VMALHW + "vmalo", // SYSTEMZ_INS_VMALO + "vmalob", // SYSTEMZ_INS_VMALOB + "vmalof", // SYSTEMZ_INS_VMALOF + "vmaloh", // SYSTEMZ_INS_VMALOH + "vmao", // SYSTEMZ_INS_VMAO + "vmaob", // SYSTEMZ_INS_VMAOB + "vmaof", // SYSTEMZ_INS_VMAOF + "vmaoh", // SYSTEMZ_INS_VMAOH + "vme", // SYSTEMZ_INS_VME + "vmeb", // SYSTEMZ_INS_VMEB + "vmef", // SYSTEMZ_INS_VMEF + "vmeh", // SYSTEMZ_INS_VMEH + "vmh", // SYSTEMZ_INS_VMH + "vmhb", // SYSTEMZ_INS_VMHB + "vmhf", // SYSTEMZ_INS_VMHF + "vmhh", // SYSTEMZ_INS_VMHH + "vml", // SYSTEMZ_INS_VML + "vmlb", // SYSTEMZ_INS_VMLB + "vmle", // SYSTEMZ_INS_VMLE + "vmleb", // SYSTEMZ_INS_VMLEB + "vmlef", // SYSTEMZ_INS_VMLEF + "vmleh", // SYSTEMZ_INS_VMLEH + "vmlf", // SYSTEMZ_INS_VMLF + "vmlh", // SYSTEMZ_INS_VMLH + "vmlhb", // SYSTEMZ_INS_VMLHB + "vmlhf", // SYSTEMZ_INS_VMLHF + "vmlhh", // SYSTEMZ_INS_VMLHH + "vmlhw", // SYSTEMZ_INS_VMLHW + "vmlo", // SYSTEMZ_INS_VMLO + "vmlob", // SYSTEMZ_INS_VMLOB + "vmlof", // SYSTEMZ_INS_VMLOF + "vmloh", // SYSTEMZ_INS_VMLOH + "vmn", // SYSTEMZ_INS_VMN + "vmnb", // SYSTEMZ_INS_VMNB + "vmnf", // SYSTEMZ_INS_VMNF + "vmng", // SYSTEMZ_INS_VMNG + "vmnh", // SYSTEMZ_INS_VMNH + "vmnl", // SYSTEMZ_INS_VMNL + "vmnlb", // SYSTEMZ_INS_VMNLB + "vmnlf", // SYSTEMZ_INS_VMNLF + "vmnlg", // SYSTEMZ_INS_VMNLG + "vmnlh", // SYSTEMZ_INS_VMNLH + "vmo", // SYSTEMZ_INS_VMO + "vmob", // SYSTEMZ_INS_VMOB + "vmof", // SYSTEMZ_INS_VMOF + "vmoh", // SYSTEMZ_INS_VMOH + "vmp", // SYSTEMZ_INS_VMP + "vmrh", // SYSTEMZ_INS_VMRH + "vmrhb", // SYSTEMZ_INS_VMRHB + "vmrhf", // SYSTEMZ_INS_VMRHF + "vmrhg", // SYSTEMZ_INS_VMRHG + "vmrhh", // SYSTEMZ_INS_VMRHH + "vmrl", // SYSTEMZ_INS_VMRL + "vmrlb", // SYSTEMZ_INS_VMRLB + "vmrlf", // SYSTEMZ_INS_VMRLF + "vmrlg", // SYSTEMZ_INS_VMRLG + "vmrlh", // SYSTEMZ_INS_VMRLH + "vmsl", // SYSTEMZ_INS_VMSL + "vmslg", // SYSTEMZ_INS_VMSLG + "vmsp", // SYSTEMZ_INS_VMSP + "vmx", // SYSTEMZ_INS_VMX + "vmxb", // SYSTEMZ_INS_VMXB + "vmxf", // SYSTEMZ_INS_VMXF + "vmxg", // SYSTEMZ_INS_VMXG + "vmxh", // SYSTEMZ_INS_VMXH + "vmxl", // SYSTEMZ_INS_VMXL + "vmxlb", // SYSTEMZ_INS_VMXLB + "vmxlf", // SYSTEMZ_INS_VMXLF + "vmxlg", // SYSTEMZ_INS_VMXLG + "vmxlh", // SYSTEMZ_INS_VMXLH + "vn", // SYSTEMZ_INS_VN + "vnc", // SYSTEMZ_INS_VNC + "vnn", // SYSTEMZ_INS_VNN + "vno", // SYSTEMZ_INS_VNO + "vnx", // SYSTEMZ_INS_VNX + "vo", // SYSTEMZ_INS_VO + "voc", // SYSTEMZ_INS_VOC + "vone", // SYSTEMZ_INS_VONE + "vpdi", // SYSTEMZ_INS_VPDI + "vperm", // SYSTEMZ_INS_VPERM + "vpk", // SYSTEMZ_INS_VPK + "vpkf", // SYSTEMZ_INS_VPKF + "vpkg", // SYSTEMZ_INS_VPKG + "vpkh", // SYSTEMZ_INS_VPKH + "vpkls", // SYSTEMZ_INS_VPKLS + "vpklsf", // SYSTEMZ_INS_VPKLSF + "vpklsfs", // SYSTEMZ_INS_VPKLSFS + "vpklsg", // SYSTEMZ_INS_VPKLSG + "vpklsgs", // SYSTEMZ_INS_VPKLSGS + "vpklsh", // SYSTEMZ_INS_VPKLSH + "vpklshs", // SYSTEMZ_INS_VPKLSHS + "vpks", // SYSTEMZ_INS_VPKS + "vpksf", // SYSTEMZ_INS_VPKSF + "vpksfs", // SYSTEMZ_INS_VPKSFS + "vpksg", // SYSTEMZ_INS_VPKSG + "vpksgs", // SYSTEMZ_INS_VPKSGS + "vpksh", // SYSTEMZ_INS_VPKSH + "vpkshs", // SYSTEMZ_INS_VPKSHS + "vpkz", // SYSTEMZ_INS_VPKZ + "vpkzr", // SYSTEMZ_INS_VPKZR + "vpopct", // SYSTEMZ_INS_VPOPCT + "vpopctb", // SYSTEMZ_INS_VPOPCTB + "vpopctf", // SYSTEMZ_INS_VPOPCTF + "vpopctg", // SYSTEMZ_INS_VPOPCTG + "vpopcth", // SYSTEMZ_INS_VPOPCTH + "vpsop", // SYSTEMZ_INS_VPSOP + "vrep", // SYSTEMZ_INS_VREP + "vrepb", // SYSTEMZ_INS_VREPB + "vrepf", // SYSTEMZ_INS_VREPF + "vrepg", // SYSTEMZ_INS_VREPG + "vreph", // SYSTEMZ_INS_VREPH + "vrepi", // SYSTEMZ_INS_VREPI + "vrepib", // SYSTEMZ_INS_VREPIB + "vrepif", // SYSTEMZ_INS_VREPIF + "vrepig", // SYSTEMZ_INS_VREPIG + "vrepih", // SYSTEMZ_INS_VREPIH + "vrp", // SYSTEMZ_INS_VRP + "vs", // SYSTEMZ_INS_VS + "vsb", // SYSTEMZ_INS_VSB + "vsbcbi", // SYSTEMZ_INS_VSBCBI + "vsbcbiq", // SYSTEMZ_INS_VSBCBIQ + "vsbi", // SYSTEMZ_INS_VSBI + "vsbiq", // SYSTEMZ_INS_VSBIQ + "vscbi", // SYSTEMZ_INS_VSCBI + "vscbib", // SYSTEMZ_INS_VSCBIB + "vscbif", // SYSTEMZ_INS_VSCBIF + "vscbig", // SYSTEMZ_INS_VSCBIG + "vscbih", // SYSTEMZ_INS_VSCBIH + "vscbiq", // SYSTEMZ_INS_VSCBIQ + "vscef", // SYSTEMZ_INS_VSCEF + "vsceg", // SYSTEMZ_INS_VSCEG + "vschdp", // SYSTEMZ_INS_VSCHDP + "vschp", // SYSTEMZ_INS_VSCHP + "vschsp", // SYSTEMZ_INS_VSCHSP + "vschxp", // SYSTEMZ_INS_VSCHXP + "vscshp", // SYSTEMZ_INS_VSCSHP + "vsdp", // SYSTEMZ_INS_VSDP + "vseg", // SYSTEMZ_INS_VSEG + "vsegb", // SYSTEMZ_INS_VSEGB + "vsegf", // SYSTEMZ_INS_VSEGF + "vsegh", // SYSTEMZ_INS_VSEGH + "vsel", // SYSTEMZ_INS_VSEL + "vsf", // SYSTEMZ_INS_VSF + "vsg", // SYSTEMZ_INS_VSG + "vsh", // SYSTEMZ_INS_VSH + "vsl", // SYSTEMZ_INS_VSL + "vslb", // SYSTEMZ_INS_VSLB + "vsld", // SYSTEMZ_INS_VSLD + "vsldb", // SYSTEMZ_INS_VSLDB + "vsp", // SYSTEMZ_INS_VSP + "vsq", // SYSTEMZ_INS_VSQ + "vsra", // SYSTEMZ_INS_VSRA + "vsrab", // SYSTEMZ_INS_VSRAB + "vsrd", // SYSTEMZ_INS_VSRD + "vsrl", // SYSTEMZ_INS_VSRL + "vsrlb", // SYSTEMZ_INS_VSRLB + "vsrp", // SYSTEMZ_INS_VSRP + "vsrpr", // SYSTEMZ_INS_VSRPR + "vst", // SYSTEMZ_INS_VST + "vstbr", // SYSTEMZ_INS_VSTBR + "vstbrf", // SYSTEMZ_INS_VSTBRF + "vstbrg", // SYSTEMZ_INS_VSTBRG + "vstbrh", // SYSTEMZ_INS_VSTBRH + "vstbrq", // SYSTEMZ_INS_VSTBRQ + "vsteb", // SYSTEMZ_INS_VSTEB + "vstebrf", // SYSTEMZ_INS_VSTEBRF + "vstebrg", // SYSTEMZ_INS_VSTEBRG + "vstebrh", // SYSTEMZ_INS_VSTEBRH + "vstef", // SYSTEMZ_INS_VSTEF + "vsteg", // SYSTEMZ_INS_VSTEG + "vsteh", // SYSTEMZ_INS_VSTEH + "vster", // SYSTEMZ_INS_VSTER + "vsterf", // SYSTEMZ_INS_VSTERF + "vsterg", // SYSTEMZ_INS_VSTERG + "vsterh", // SYSTEMZ_INS_VSTERH + "vstl", // SYSTEMZ_INS_VSTL + "vstm", // SYSTEMZ_INS_VSTM + "vstrc", // SYSTEMZ_INS_VSTRC + "vstrcb", // SYSTEMZ_INS_VSTRCB + "vstrcbs", // SYSTEMZ_INS_VSTRCBS + "vstrcf", // SYSTEMZ_INS_VSTRCF + "vstrcfs", // SYSTEMZ_INS_VSTRCFS + "vstrch", // SYSTEMZ_INS_VSTRCH + "vstrchs", // SYSTEMZ_INS_VSTRCHS + "vstrczb", // SYSTEMZ_INS_VSTRCZB + "vstrczbs", // SYSTEMZ_INS_VSTRCZBS + "vstrczf", // SYSTEMZ_INS_VSTRCZF + "vstrczfs", // SYSTEMZ_INS_VSTRCZFS + "vstrczh", // SYSTEMZ_INS_VSTRCZH + "vstrczhs", // SYSTEMZ_INS_VSTRCZHS + "vstrl", // SYSTEMZ_INS_VSTRL + "vstrlr", // SYSTEMZ_INS_VSTRLR + "vstrs", // SYSTEMZ_INS_VSTRS + "vstrsb", // SYSTEMZ_INS_VSTRSB + "vstrsf", // SYSTEMZ_INS_VSTRSF + "vstrsh", // SYSTEMZ_INS_VSTRSH + "vstrszb", // SYSTEMZ_INS_VSTRSZB + "vstrszf", // SYSTEMZ_INS_VSTRSZF + "vstrszh", // SYSTEMZ_INS_VSTRSZH + "vsum", // SYSTEMZ_INS_VSUM + "vsumb", // SYSTEMZ_INS_VSUMB + "vsumg", // SYSTEMZ_INS_VSUMG + "vsumgf", // SYSTEMZ_INS_VSUMGF + "vsumgh", // SYSTEMZ_INS_VSUMGH + "vsumh", // SYSTEMZ_INS_VSUMH + "vsumq", // SYSTEMZ_INS_VSUMQ + "vsumqf", // SYSTEMZ_INS_VSUMQF + "vsumqg", // SYSTEMZ_INS_VSUMQG + "vtm", // SYSTEMZ_INS_VTM + "vtp", // SYSTEMZ_INS_VTP + "vuph", // SYSTEMZ_INS_VUPH + "vuphb", // SYSTEMZ_INS_VUPHB + "vuphf", // SYSTEMZ_INS_VUPHF + "vuphh", // SYSTEMZ_INS_VUPHH + "vupkz", // SYSTEMZ_INS_VUPKZ + "vupkzh", // SYSTEMZ_INS_VUPKZH + "vupkzl", // SYSTEMZ_INS_VUPKZL + "vupl", // SYSTEMZ_INS_VUPL + "vuplb", // SYSTEMZ_INS_VUPLB + "vuplf", // SYSTEMZ_INS_VUPLF + "vuplh", // SYSTEMZ_INS_VUPLH + "vuplhb", // SYSTEMZ_INS_VUPLHB + "vuplhf", // SYSTEMZ_INS_VUPLHF + "vuplhh", // SYSTEMZ_INS_VUPLHH + "vuplhw", // SYSTEMZ_INS_VUPLHW + "vupll", // SYSTEMZ_INS_VUPLL + "vupllb", // SYSTEMZ_INS_VUPLLB + "vupllf", // SYSTEMZ_INS_VUPLLF + "vupllh", // SYSTEMZ_INS_VUPLLH + "vx", // SYSTEMZ_INS_VX + "vzero", // SYSTEMZ_INS_VZERO + "wcdgb", // SYSTEMZ_INS_WCDGB + "wcdlgb", // SYSTEMZ_INS_WCDLGB + "wcefb", // SYSTEMZ_INS_WCEFB + "wcelfb", // SYSTEMZ_INS_WCELFB + "wcfeb", // SYSTEMZ_INS_WCFEB + "wcgdb", // SYSTEMZ_INS_WCGDB + "wclfeb", // SYSTEMZ_INS_WCLFEB + "wclgdb", // SYSTEMZ_INS_WCLGDB + "wfadb", // SYSTEMZ_INS_WFADB + "wfasb", // SYSTEMZ_INS_WFASB + "wfaxb", // SYSTEMZ_INS_WFAXB + "wfc", // SYSTEMZ_INS_WFC + "wfcdb", // SYSTEMZ_INS_WFCDB + "wfcedb", // SYSTEMZ_INS_WFCEDB + "wfcedbs", // SYSTEMZ_INS_WFCEDBS + "wfcesb", // SYSTEMZ_INS_WFCESB + "wfcesbs", // SYSTEMZ_INS_WFCESBS + "wfcexb", // SYSTEMZ_INS_WFCEXB + "wfcexbs", // SYSTEMZ_INS_WFCEXBS + "wfchdb", // SYSTEMZ_INS_WFCHDB + "wfchdbs", // SYSTEMZ_INS_WFCHDBS + "wfchedb", // SYSTEMZ_INS_WFCHEDB + "wfchedbs", // SYSTEMZ_INS_WFCHEDBS + "wfchesb", // SYSTEMZ_INS_WFCHESB + "wfchesbs", // SYSTEMZ_INS_WFCHESBS + "wfchexb", // SYSTEMZ_INS_WFCHEXB + "wfchexbs", // SYSTEMZ_INS_WFCHEXBS + "wfchsb", // SYSTEMZ_INS_WFCHSB + "wfchsbs", // SYSTEMZ_INS_WFCHSBS + "wfchxb", // SYSTEMZ_INS_WFCHXB + "wfchxbs", // SYSTEMZ_INS_WFCHXBS + "wfcsb", // SYSTEMZ_INS_WFCSB + "wfcxb", // SYSTEMZ_INS_WFCXB + "wfddb", // SYSTEMZ_INS_WFDDB + "wfdsb", // SYSTEMZ_INS_WFDSB + "wfdxb", // SYSTEMZ_INS_WFDXB + "wfidb", // SYSTEMZ_INS_WFIDB + "wfisb", // SYSTEMZ_INS_WFISB + "wfixb", // SYSTEMZ_INS_WFIXB + "wfk", // SYSTEMZ_INS_WFK + "wfkdb", // SYSTEMZ_INS_WFKDB + "wfkedb", // SYSTEMZ_INS_WFKEDB + "wfkedbs", // SYSTEMZ_INS_WFKEDBS + "wfkesb", // SYSTEMZ_INS_WFKESB + "wfkesbs", // SYSTEMZ_INS_WFKESBS + "wfkexb", // SYSTEMZ_INS_WFKEXB + "wfkexbs", // SYSTEMZ_INS_WFKEXBS + "wfkhdb", // SYSTEMZ_INS_WFKHDB + "wfkhdbs", // SYSTEMZ_INS_WFKHDBS + "wfkhedb", // SYSTEMZ_INS_WFKHEDB + "wfkhedbs", // SYSTEMZ_INS_WFKHEDBS + "wfkhesb", // SYSTEMZ_INS_WFKHESB + "wfkhesbs", // SYSTEMZ_INS_WFKHESBS + "wfkhexb", // SYSTEMZ_INS_WFKHEXB + "wfkhexbs", // SYSTEMZ_INS_WFKHEXBS + "wfkhsb", // SYSTEMZ_INS_WFKHSB + "wfkhsbs", // SYSTEMZ_INS_WFKHSBS + "wfkhxb", // SYSTEMZ_INS_WFKHXB + "wfkhxbs", // SYSTEMZ_INS_WFKHXBS + "wfksb", // SYSTEMZ_INS_WFKSB + "wfkxb", // SYSTEMZ_INS_WFKXB + "wflcdb", // SYSTEMZ_INS_WFLCDB + "wflcsb", // SYSTEMZ_INS_WFLCSB + "wflcxb", // SYSTEMZ_INS_WFLCXB + "wflld", // SYSTEMZ_INS_WFLLD + "wflls", // SYSTEMZ_INS_WFLLS + "wflndb", // SYSTEMZ_INS_WFLNDB + "wflnsb", // SYSTEMZ_INS_WFLNSB + "wflnxb", // SYSTEMZ_INS_WFLNXB + "wflpdb", // SYSTEMZ_INS_WFLPDB + "wflpsb", // SYSTEMZ_INS_WFLPSB + "wflpxb", // SYSTEMZ_INS_WFLPXB + "wflrd", // SYSTEMZ_INS_WFLRD + "wflrx", // SYSTEMZ_INS_WFLRX + "wfmadb", // SYSTEMZ_INS_WFMADB + "wfmasb", // SYSTEMZ_INS_WFMASB + "wfmaxb", // SYSTEMZ_INS_WFMAXB + "wfmaxdb", // SYSTEMZ_INS_WFMAXDB + "wfmaxsb", // SYSTEMZ_INS_WFMAXSB + "wfmaxxb", // SYSTEMZ_INS_WFMAXXB + "wfmdb", // SYSTEMZ_INS_WFMDB + "wfmindb", // SYSTEMZ_INS_WFMINDB + "wfminsb", // SYSTEMZ_INS_WFMINSB + "wfminxb", // SYSTEMZ_INS_WFMINXB + "wfmsb", // SYSTEMZ_INS_WFMSB + "wfmsdb", // SYSTEMZ_INS_WFMSDB + "wfmssb", // SYSTEMZ_INS_WFMSSB + "wfmsxb", // SYSTEMZ_INS_WFMSXB + "wfmxb", // SYSTEMZ_INS_WFMXB + "wfnmadb", // SYSTEMZ_INS_WFNMADB + "wfnmasb", // SYSTEMZ_INS_WFNMASB + "wfnmaxb", // SYSTEMZ_INS_WFNMAXB + "wfnmsdb", // SYSTEMZ_INS_WFNMSDB + "wfnmssb", // SYSTEMZ_INS_WFNMSSB + "wfnmsxb", // SYSTEMZ_INS_WFNMSXB + "wfpsodb", // SYSTEMZ_INS_WFPSODB + "wfpsosb", // SYSTEMZ_INS_WFPSOSB + "wfpsoxb", // SYSTEMZ_INS_WFPSOXB + "wfsdb", // SYSTEMZ_INS_WFSDB + "wfsqdb", // SYSTEMZ_INS_WFSQDB + "wfsqsb", // SYSTEMZ_INS_WFSQSB + "wfsqxb", // SYSTEMZ_INS_WFSQXB + "wfssb", // SYSTEMZ_INS_WFSSB + "wfsxb", // SYSTEMZ_INS_WFSXB + "wftcidb", // SYSTEMZ_INS_WFTCIDB + "wftcisb", // SYSTEMZ_INS_WFTCISB + "wftcixb", // SYSTEMZ_INS_WFTCIXB + "wldeb", // SYSTEMZ_INS_WLDEB + "wledb", // SYSTEMZ_INS_WLEDB + "x", // SYSTEMZ_INS_X + "xc", // SYSTEMZ_INS_XC + "xg", // SYSTEMZ_INS_XG + "xgr", // SYSTEMZ_INS_XGR + "xgrk", // SYSTEMZ_INS_XGRK + "xi", // SYSTEMZ_INS_XI + "xihf", // SYSTEMZ_INS_XIHF + "xilf", // SYSTEMZ_INS_XILF + "xiy", // SYSTEMZ_INS_XIY + "xr", // SYSTEMZ_INS_XR + "xrk", // SYSTEMZ_INS_XRK + "xsch", // SYSTEMZ_INS_XSCH + "xy", // SYSTEMZ_INS_XY + "zap", // SYSTEMZ_INS_ZAP diff --git a/arch/SystemZ/SystemZGenCSMappingInsnOp.inc b/arch/SystemZ/SystemZGenCSMappingInsnOp.inc new file mode 100644 index 0000000000..104131a5de --- /dev/null +++ b/arch/SystemZ/SystemZGenCSMappingInsnOp.inc @@ -0,0 +1,20132 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + +{{{ /* SYSTEMZ_PHI (0) - SYSTEMZ_INS_INVALID - PHINODE */ + 0 +}}}, +{{{ /* SYSTEMZ_INLINEASM (1) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_INLINEASM_BR (2) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CFI_INSTRUCTION (3) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_EH_LABEL (4) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_GC_LABEL (5) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ANNOTATION_LABEL (6) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_KILL (7) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_EXTRACT_SUBREG (8) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_INSERT_SUBREG (9) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_IMPLICIT_DEF (10) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_SUBREG_TO_REG (11) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_COPY_TO_REGCLASS (12) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_DBG_VALUE (13) - SYSTEMZ_INS_INVALID - DBG_VALUE */ + 0 +}}}, +{{{ /* SYSTEMZ_DBG_VALUE_LIST (14) - SYSTEMZ_INS_INVALID - DBG_VALUE_LIST */ + 0 +}}}, +{{{ /* SYSTEMZ_DBG_INSTR_REF (15) - SYSTEMZ_INS_INVALID - DBG_INSTR_REF */ + 0 +}}}, +{{{ /* SYSTEMZ_DBG_PHI (16) - SYSTEMZ_INS_INVALID - DBG_PHI */ + 0 +}}}, +{{{ /* SYSTEMZ_DBG_LABEL (17) - SYSTEMZ_INS_INVALID - DBG_LABEL */ + 0 +}}}, +{{{ /* SYSTEMZ_REG_SEQUENCE (18) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_COPY (19) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_BUNDLE (20) - SYSTEMZ_INS_INVALID - BUNDLE */ + 0 +}}}, +{{{ /* SYSTEMZ_LIFETIME_START (21) - SYSTEMZ_INS_INVALID - LIFETIME_START */ + 0 +}}}, +{{{ /* SYSTEMZ_LIFETIME_END (22) - SYSTEMZ_INS_INVALID - LIFETIME_END */ + 0 +}}}, +{{{ /* SYSTEMZ_PSEUDO_PROBE (23) - SYSTEMZ_INS_INVALID - PSEUDO_PROBE */ + 0 +}}}, +{{{ /* SYSTEMZ_ARITH_FENCE (24) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_STACKMAP (25) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_FENTRY_CALL (26) - SYSTEMZ_INS_INVALID - # FEntry call */ + 0 +}}}, +{{{ /* SYSTEMZ_PATCHPOINT (27) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LOAD_STACK_GUARD (28) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_PREALLOCATED_SETUP (29) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_PREALLOCATED_ARG (30) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_STATEPOINT (31) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LOCAL_ESCAPE (32) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_FAULTING_OP (33) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_PATCHABLE_OP (34) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_PATCHABLE_FUNCTION_ENTER (35) - SYSTEMZ_INS_INVALID - # XRay Function Enter. */ + 0 +}}}, +{{{ /* SYSTEMZ_PATCHABLE_RET (36) - SYSTEMZ_INS_INVALID - # XRay Function Patchable RET. */ + 0 +}}}, +{{{ /* SYSTEMZ_PATCHABLE_FUNCTION_EXIT (37) - SYSTEMZ_INS_INVALID - # XRay Function Exit. */ + 0 +}}}, +{{{ /* SYSTEMZ_PATCHABLE_TAIL_CALL (38) - SYSTEMZ_INS_INVALID - # XRay Tail Call Exit. */ + 0 +}}}, +{{{ /* SYSTEMZ_PATCHABLE_EVENT_CALL (39) - SYSTEMZ_INS_INVALID - # XRay Custom Event Log. */ + 0 +}}}, +{{{ /* SYSTEMZ_PATCHABLE_TYPED_EVENT_CALL (40) - SYSTEMZ_INS_INVALID - # XRay Typed Event Log. */ + 0 +}}}, +{{{ /* SYSTEMZ_ICALL_BRANCH_FUNNEL (41) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_MEMBARRIER (42) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_JUMP_TABLE_DEBUG_INFO (43) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ASSERT_SEXT (44) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ASSERT_ZEXT (45) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ASSERT_ALIGN (46) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ADD (47) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SUB (48) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_MUL (49) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SDIV (50) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_UDIV (51) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SREM (52) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_UREM (53) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SDIVREM (54) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_UDIVREM (55) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_AND (56) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_OR (57) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_XOR (58) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_IMPLICIT_DEF (59) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_PHI (60) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FRAME_INDEX (61) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_GLOBAL_VALUE (62) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_CONSTANT_POOL (63) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_EXTRACT (64) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_UNMERGE_VALUES (65) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_INSERT (66) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_MERGE_VALUES (67) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_BUILD_VECTOR (68) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_BUILD_VECTOR_TRUNC (69) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_CONCAT_VECTORS (70) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_PTRTOINT (71) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_INTTOPTR (72) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_BITCAST (73) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FREEZE (74) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_CONSTANT_FOLD_BARRIER (75) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_INTRINSIC_FPTRUNC_ROUND (76) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_INTRINSIC_TRUNC (77) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_INTRINSIC_ROUND (78) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_INTRINSIC_LRINT (79) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_INTRINSIC_ROUNDEVEN (80) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_READCYCLECOUNTER (81) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_LOAD (82) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SEXTLOAD (83) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ZEXTLOAD (84) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_INDEXED_LOAD (85) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_INDEXED_SEXTLOAD (86) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_INDEXED_ZEXTLOAD (87) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_STORE (88) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_INDEXED_STORE (89) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ATOMIC_CMPXCHG_WITH_SUCCESS (90) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ATOMIC_CMPXCHG (91) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ATOMICRMW_XCHG (92) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ATOMICRMW_ADD (93) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ATOMICRMW_SUB (94) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ATOMICRMW_AND (95) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ATOMICRMW_NAND (96) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ATOMICRMW_OR (97) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ATOMICRMW_XOR (98) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ATOMICRMW_MAX (99) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ATOMICRMW_MIN (100) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ATOMICRMW_UMAX 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SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ASHR (129) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FSHL (130) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FSHR (131) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ROTR (132) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ROTL (133) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ICMP (134) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FCMP (135) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SELECT (136) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_UADDO (137) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_UADDE (138) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_USUBO (139) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_USUBE (140) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SADDO (141) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SADDE (142) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SSUBO (143) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SSUBE (144) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_UMULO (145) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SMULO (146) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_UMULH (147) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SMULH (148) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_UADDSAT (149) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SADDSAT (150) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_USUBSAT (151) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SSUBSAT (152) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_USHLSAT (153) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SSHLSAT (154) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SMULFIX (155) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_UMULFIX (156) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SMULFIXSAT (157) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_UMULFIXSAT (158) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SDIVFIX (159) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_UDIVFIX (160) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SDIVFIXSAT (161) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_UDIVFIXSAT (162) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FADD (163) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FSUB (164) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FMUL (165) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FMA (166) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FMAD (167) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FDIV (168) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FREM (169) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FPOW (170) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FPOWI (171) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FEXP (172) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FEXP2 (173) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FEXP10 (174) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FLOG (175) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FLOG2 (176) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FLOG10 (177) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FLDEXP (178) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FFREXP (179) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FNEG (180) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FPEXT (181) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FPTRUNC (182) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FPTOSI (183) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FPTOUI (184) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SITOFP (185) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_UITOFP (186) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FABS (187) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FCOPYSIGN (188) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_IS_FPCLASS (189) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FCANONICALIZE (190) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FMINNUM (191) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FMAXNUM (192) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FMINNUM_IEEE (193) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FMAXNUM_IEEE (194) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FMINIMUM (195) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_FMAXIMUM (196) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_GET_FPENV (197) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SET_FPENV (198) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_RESET_FPENV (199) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_GET_FPMODE (200) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SET_FPMODE (201) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_RESET_FPMODE (202) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_PTR_ADD (203) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_PTRMASK (204) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SMIN (205) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SMAX (206) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_UMIN (207) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_UMAX (208) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ABS (209) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_LROUND (210) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_LLROUND (211) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_BR (212) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_BRJT (213) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_INSERT_VECTOR_ELT (214) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_EXTRACT_VECTOR_ELT (215) - SYSTEMZ_INS_INVALID - */ + 0 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SYSTEMZ_G_FNEARBYINT (230) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_ADDRSPACE_CAST (231) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_BLOCK_ADDR (232) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_JUMP_TABLE (233) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_DYN_STACKALLOC (234) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_STACKSAVE (235) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_STACKRESTORE (236) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_STRICT_FADD (237) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_STRICT_FSUB (238) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_STRICT_FMUL (239) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_STRICT_FDIV (240) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_STRICT_FREM (241) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_STRICT_FMA (242) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_STRICT_FSQRT (243) - SYSTEMZ_INS_INVALID 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SYSTEMZ_G_VECREDUCE_FMIN (257) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_VECREDUCE_FMAXIMUM (258) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_VECREDUCE_FMINIMUM (259) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_VECREDUCE_ADD (260) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_VECREDUCE_MUL (261) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_VECREDUCE_AND (262) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_VECREDUCE_OR (263) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_VECREDUCE_XOR (264) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_VECREDUCE_SMAX (265) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_VECREDUCE_SMIN (266) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_VECREDUCE_UMAX (267) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_VECREDUCE_UMIN (268) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_SBFX (269) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_G_UBFX (270) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ADA_ENTRY (271) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ADA_ENTRY_VALUE (272) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ADB_MemFoldPseudo (273) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ADJCALLSTACKDOWN (274) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ADJCALLSTACKUP (275) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ADJDYNALLOC (276) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_AEB_MemFoldPseudo (277) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_AEXT128 (278) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_AFIMux (279) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_AG_MemFoldPseudo (280) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_AHIMux (281) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_AHIMuxK (282) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ALG_MemFoldPseudo (283) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_AL_MemFoldPseudo (284) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ATOMIC_CMP_SWAPW (285) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ATOMIC_LOADW_AFI (286) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ATOMIC_LOADW_AR (287) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ATOMIC_LOADW_MAX (288) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ATOMIC_LOADW_MIN (289) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ATOMIC_LOADW_NILH (290) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ATOMIC_LOADW_NILHi (291) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ATOMIC_LOADW_NR (292) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ATOMIC_LOADW_NRi (293) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ATOMIC_LOADW_OILH (294) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ATOMIC_LOADW_OR (295) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ATOMIC_LOADW_SR (296) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ATOMIC_LOADW_UMAX (297) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ATOMIC_LOADW_UMIN (298) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ATOMIC_LOADW_XILF (299) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ATOMIC_LOADW_XR (300) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ATOMIC_SWAPW (301) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_A_MemFoldPseudo (302) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CFIMux (303) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CGIBCall (304) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CGIBReturn (305) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CGRBCall (306) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CGRBReturn (307) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CHIMux (308) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CIBCall (309) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CIBReturn (310) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CLCImm (311) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CLCReg (312) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CLFIMux (313) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CLGIBCall (314) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CLGIBReturn (315) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CLGRBCall (316) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CLGRBReturn (317) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CLIBCall (318) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CLIBReturn (319) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CLMux (320) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CLRBCall (321) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CLRBReturn (322) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CLSTLoop (323) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CMux (324) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CRBCall (325) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CRBReturn (326) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CallBASR (327) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CallBASR_STACKEXT (328) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CallBASR_XPLINK64 (329) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CallBCR (330) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CallBR (331) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CallBRASL (332) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CallBRASL_XPLINK64 (333) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CallBRCL (334) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CallJG (335) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondReturn (336) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondReturn_XPLINK (337) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondStore16 (338) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondStore16Inv (339) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondStore16Mux (340) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondStore16MuxInv (341) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondStore32 (342) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondStore32Inv (343) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondStore32Mux (344) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondStore32MuxInv (345) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondStore64 (346) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondStore64Inv (347) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondStore8 (348) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondStore8Inv (349) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondStore8Mux (350) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondStore8MuxInv (351) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondStoreF32 (352) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondStoreF32Inv (353) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondStoreF64 (354) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondStoreF64Inv (355) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_CondTrap (356) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_DDB_MemFoldPseudo (357) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_DEB_MemFoldPseudo (358) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_EXRL_Pseudo (359) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_GOT (360) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_IIFMux (361) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_IIHF64 (362) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_IIHH64 (363) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_IIHL64 (364) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_IIHMux (365) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_IILF64 (366) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_IILH64 (367) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_IILL64 (368) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_IILMux (369) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_L128 (370) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LBMux (371) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LEFR (372) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LFER (373) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LHIMux (374) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LHMux (375) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LLCMux (376) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LLCRMux (377) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LLHMux (378) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LLHRMux (379) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LMux (380) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LOCG_MemFoldPseudo (381) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LOCHIMux (382) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LOCMux (383) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LOCMux_MemFoldPseudo (384) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LOCRMux (385) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LTDBRCompare_Pseudo (386) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LTEBRCompare_Pseudo (387) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LTXBRCompare_Pseudo (388) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_LX (389) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_MADB_MemFoldPseudo (390) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_MAEB_MemFoldPseudo (391) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_MDB_MemFoldPseudo (392) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_MEEB_MemFoldPseudo (393) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_MSC_MemFoldPseudo (394) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_MSDB_MemFoldPseudo (395) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_MSEB_MemFoldPseudo (396) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_MSGC_MemFoldPseudo (397) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_MVCImm (398) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_MVCReg (399) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_MVSTLoop (400) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_MemsetImmImm (401) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_MemsetImmReg (402) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_MemsetRegImm (403) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_MemsetRegReg (404) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_NCImm (405) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_NCReg (406) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_NG_MemFoldPseudo (407) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_NIFMux (408) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_NIHF64 (409) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_NIHH64 (410) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_NIHL64 (411) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_NIHMux (412) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_NILF64 (413) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_NILH64 (414) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_NILL64 (415) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_NILMux (416) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_N_MemFoldPseudo (417) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_OCImm (418) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_OCReg (419) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_OG_MemFoldPseudo (420) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_OIFMux (421) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_OIHF64 (422) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_OIHH64 (423) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_OIHL64 (424) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_OIHMux (425) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_OILF64 (426) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_OILH64 (427) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_OILL64 (428) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_OILMux (429) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_O_MemFoldPseudo (430) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_PAIR128 (431) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_PROBED_ALLOCA (432) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_PROBED_STACKALLOC (433) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_RISBHH (434) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_RISBHL (435) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_RISBLH (436) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_RISBLL (437) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_RISBMux (438) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_Return (439) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_Return_XPLINK (440) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_SCmp128Hi (441) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_SDB_MemFoldPseudo (442) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_SEB_MemFoldPseudo (443) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_SELRMux (444) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_SG_MemFoldPseudo (445) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_SLG_MemFoldPseudo (446) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_SL_MemFoldPseudo (447) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_SRSTLoop (448) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ST128 (449) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_STCMux (450) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_STHMux (451) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_STMux (452) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_STOCMux (453) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_STX (454) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_S_MemFoldPseudo (455) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_Select128 (456) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_Select32 (457) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_Select64 (458) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_SelectF128 (459) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_SelectF32 (460) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_SelectF64 (461) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_SelectVR128 (462) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_SelectVR32 (463) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_SelectVR64 (464) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_Serialize (465) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_TBEGIN_nofloat (466) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_TLS_GDCALL (467) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_TLS_LDCALL (468) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_TMHH64 (469) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_TMHL64 (470) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_TMHMux (471) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_TMLH64 (472) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_TMLL64 (473) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_TMLMux (474) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_Trap (475) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_UCmp128Hi (476) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_VL32 (477) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_VL64 (478) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_VLR32 (479) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_VLR64 (480) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_VLVGP32 (481) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_VST32 (482) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_VST64 (483) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_XCImm (484) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_XCReg (485) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_XG_MemFoldPseudo (486) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_XIFMux (487) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_XIHF64 (488) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_XILF64 (489) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_XPLINK_STACKALLOC (490) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_X_MemFoldPseudo (491) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{{{ /* SYSTEMZ_ZEXT128 (492) - SYSTEMZ_INS_INVALID - */ + 0 +}}}, +{ /* SYSTEMZ_A (493) - SYSTEMZ_INS_A - a $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_AD (494) - SYSTEMZ_INS_AD - ad $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_ADB (495) - SYSTEMZ_INS_ADB - adb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_ADBR (496) - SYSTEMZ_INS_ADBR - adbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_ADR (497) - SYSTEMZ_INS_ADR - adr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_ADTR (498) - SYSTEMZ_INS_ADTR - adtr $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_ADTRA (499) - SYSTEMZ_INS_ADTRA - adtra $R1, $R2, $R3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_AE (500) - SYSTEMZ_INS_AE - ae $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_AEB (501) - SYSTEMZ_INS_AEB - aeb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_AEBR (502) - SYSTEMZ_INS_AEBR - aebr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_AER (503) - SYSTEMZ_INS_AER - aer $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_AFI (504) - SYSTEMZ_INS_AFI - afi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_AG (505) - SYSTEMZ_INS_AG - ag $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_AGF (506) - SYSTEMZ_INS_AGF - agf $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_AGFI (507) - SYSTEMZ_INS_AGFI - agfi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_AGFR (508) - SYSTEMZ_INS_AGFR - agfr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_AGH (509) - SYSTEMZ_INS_AGH - agh $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_AGHI (510) - SYSTEMZ_INS_AGHI - aghi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_AGHIK (511) - SYSTEMZ_INS_AGHIK - aghik $R1, $R3, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_AGR (512) - SYSTEMZ_INS_AGR - agr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_AGRK (513) - SYSTEMZ_INS_AGRK - agrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_AGSI (514) - SYSTEMZ_INS_AGSI - agsi $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp20imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_AH (515) - SYSTEMZ_INS_AH - ah $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_AHHHR (516) - SYSTEMZ_INS_AHHHR - ahhhr $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_AHHLR (517) - SYSTEMZ_INS_AHHLR - ahhlr $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_AHI (518) - SYSTEMZ_INS_AHI - ahi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_AHIK (519) - SYSTEMZ_INS_AHIK - ahik $R1, $R3, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_AHY (520) - SYSTEMZ_INS_AHY - ahy $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_AIH (521) - SYSTEMZ_INS_AIH - aih $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_AL (522) - SYSTEMZ_INS_AL - al $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_ALC (523) - SYSTEMZ_INS_ALC - alc $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_ALCG (524) - SYSTEMZ_INS_ALCG - alcg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_ALCGR (525) - SYSTEMZ_INS_ALCGR - alcgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_ALCR (526) - SYSTEMZ_INS_ALCR - alcr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_ALFI (527) - SYSTEMZ_INS_ALFI - alfi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_ALG (528) - SYSTEMZ_INS_ALG - alg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_ALGF (529) - SYSTEMZ_INS_ALGF - algf $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_ALGFI (530) - SYSTEMZ_INS_ALGFI - algfi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_ALGFR (531) - SYSTEMZ_INS_ALGFR - algfr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_ALGHSIK (532) - SYSTEMZ_INS_ALGHSIK - alghsik $R1, $R3, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_ALGR (533) - SYSTEMZ_INS_ALGR - algr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_ALGRK (534) - SYSTEMZ_INS_ALGRK - algrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_ALGSI (535) - SYSTEMZ_INS_ALGSI - algsi $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp20imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_ALHHHR (536) - SYSTEMZ_INS_ALHHHR - alhhhr $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_ALHHLR (537) - SYSTEMZ_INS_ALHHLR - alhhlr $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_ALHSIK (538) - SYSTEMZ_INS_ALHSIK - alhsik $R1, $R3, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_ALR (539) - SYSTEMZ_INS_ALR - alr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_ALRK (540) - SYSTEMZ_INS_ALRK - alrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_ALSI (541) - SYSTEMZ_INS_ALSI - alsi $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp20imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_ALSIH (542) - SYSTEMZ_INS_ALSIH - alsih $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_ALSIHN (543) - SYSTEMZ_INS_ALSIHN - alsihn $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_ALY (544) - SYSTEMZ_INS_ALY - aly $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_AP (545) - SYSTEMZ_INS_AP - ap $BDL1, $BDL2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len4imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - len4imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_AR (546) - SYSTEMZ_INS_AR - ar $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_ARK (547) - SYSTEMZ_INS_ARK - ark $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_ASI (548) - SYSTEMZ_INS_ASI - asi $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp20imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_AU (549) - SYSTEMZ_INS_AU - au $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_AUR (550) - SYSTEMZ_INS_AUR - aur $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_AW (551) - SYSTEMZ_INS_AW - aw $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_AWR (552) - SYSTEMZ_INS_AWR - awr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_AXBR (553) - SYSTEMZ_INS_AXBR - axbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_AXR (554) - SYSTEMZ_INS_AXR - axr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_AXTR (555) - SYSTEMZ_INS_AXTR - axtr $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_AXTRA (556) - SYSTEMZ_INS_AXTRA - axtra $R1, $R2, $R3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_AY (557) - SYSTEMZ_INS_AY - ay $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_B (558) - SYSTEMZ_INS_B - b $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAKR (559) - SYSTEMZ_INS_BAKR - bakr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BAL (560) - SYSTEMZ_INS_BAL - bal $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BALR (561) - SYSTEMZ_INS_BALR - balr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BAS (562) - SYSTEMZ_INS_BAS - bas $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BASR (563) - SYSTEMZ_INS_BASR - basr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BASSM (564) - SYSTEMZ_INS_BASSM - bassm $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmE (565) - SYSTEMZ_INS_BE - be $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmH (566) - SYSTEMZ_INS_BH - bh $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmHE (567) - SYSTEMZ_INS_BHE - bhe $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmL (568) - SYSTEMZ_INS_BL - bl $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmLE (569) - SYSTEMZ_INS_BLE - ble $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmLH (570) - SYSTEMZ_INS_BLH - blh $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmM (571) - SYSTEMZ_INS_BM - bm $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmNE (572) - SYSTEMZ_INS_BNE - bne $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmNH (573) - SYSTEMZ_INS_BNH - bnh $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmNHE (574) - SYSTEMZ_INS_BNHE - bnhe $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmNL (575) - SYSTEMZ_INS_BNL - bnl $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmNLE (576) - SYSTEMZ_INS_BNLE - bnle $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmNLH (577) - SYSTEMZ_INS_BNLH - bnlh $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmNM (578) - SYSTEMZ_INS_BNM - bnm $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmNO (579) - SYSTEMZ_INS_BNO - bno $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmNP (580) - SYSTEMZ_INS_BNP - bnp $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmNZ (581) - SYSTEMZ_INS_BNZ - bnz $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmO (582) - SYSTEMZ_INS_BO - bo $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmP (583) - SYSTEMZ_INS_BP - bp $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BAsmZ (584) - SYSTEMZ_INS_BZ - bz $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{{{ /* SYSTEMZ_BC (585) - SYSTEMZ_INS_INVALID - b${M1} $XBD2 */ + 0 +}}}, +{ /* SYSTEMZ_BCAsm (586) - SYSTEMZ_INS_BC - bc $M1, $XBD2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{{{ /* SYSTEMZ_BCR (587) - SYSTEMZ_INS_INVALID - b${R1}r $R2 */ + 0 +}}}, +{ /* SYSTEMZ_BCRAsm (588) - SYSTEMZ_INS_BCR - bcr $R1, $R2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BCT (589) - SYSTEMZ_INS_BCT - bct $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BCTG (590) - SYSTEMZ_INS_BCTG - bctg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BCTGR (591) - SYSTEMZ_INS_BCTGR - bctgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BCTR (592) - SYSTEMZ_INS_BCTR - bctr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BI (593) - SYSTEMZ_INS_BI - bi $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmE (594) - SYSTEMZ_INS_BIE - bie $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmH (595) - SYSTEMZ_INS_BIH - bih $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmHE (596) - SYSTEMZ_INS_BIHE - bihe $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmL (597) - SYSTEMZ_INS_BIL - bil $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmLE (598) - SYSTEMZ_INS_BILE - bile $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmLH (599) - SYSTEMZ_INS_BILH - bilh $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmM (600) - SYSTEMZ_INS_BIM - bim $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmNE (601) - SYSTEMZ_INS_BINE - bine $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmNH (602) - SYSTEMZ_INS_BINH - binh $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmNHE (603) - SYSTEMZ_INS_BINHE - binhe $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmNL (604) - SYSTEMZ_INS_BINL - binl $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmNLE (605) - SYSTEMZ_INS_BINLE - binle $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmNLH (606) - SYSTEMZ_INS_BINLH - binlh $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmNM (607) - SYSTEMZ_INS_BINM - binm $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmNO (608) - SYSTEMZ_INS_BINO - bino $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmNP (609) - SYSTEMZ_INS_BINP - binp $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmNZ (610) - SYSTEMZ_INS_BINZ - binz $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmO (611) - SYSTEMZ_INS_BIO - bio $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmP (612) - SYSTEMZ_INS_BIP - bip $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BIAsmZ (613) - SYSTEMZ_INS_BIZ - biz $XBD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{{{ /* SYSTEMZ_BIC (614) - SYSTEMZ_INS_INVALID - bi${M1} $XBD2 */ + 0 +}}}, +{ /* SYSTEMZ_BICAsm (615) - SYSTEMZ_INS_BIC - bic $M1, $XBD2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_BPP (616) - SYSTEMZ_INS_BPP - bpp $M1, $RI2, $BD3 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD3 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD3 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_BPRP (617) - SYSTEMZ_INS_BPRP - bprp $M1, $RI2, $RI3 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI3 */ + { 0 } +}}, +{ /* SYSTEMZ_BR (618) - SYSTEMZ_INS_BR - br $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAS (619) - SYSTEMZ_INS_BRAS - bras $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 - brtarget16 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - tlssym */ + { 0 } +}}, +{ /* SYSTEMZ_BRASL (620) - SYSTEMZ_INS_BRASL - brasl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 - brtarget32 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - tlssym */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmE (621) - SYSTEMZ_INS_BER - ber $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmH (622) - SYSTEMZ_INS_BHR - bhr $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmHE (623) - SYSTEMZ_INS_BHER - bher $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmL (624) - SYSTEMZ_INS_BLR - blr $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmLE (625) - SYSTEMZ_INS_BLER - bler $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmLH (626) - SYSTEMZ_INS_BLHR - blhr $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmM (627) - SYSTEMZ_INS_BMR - bmr $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmNE (628) - SYSTEMZ_INS_BNER - bner $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmNH (629) - SYSTEMZ_INS_BNHR - bnhr $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmNHE (630) - SYSTEMZ_INS_BNHER - bnher $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmNL (631) - SYSTEMZ_INS_BNLR - bnlr $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmNLE (632) - SYSTEMZ_INS_BNLER - bnler $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmNLH (633) - SYSTEMZ_INS_BNLHR - bnlhr $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmNM (634) - SYSTEMZ_INS_BNMR - bnmr $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmNO (635) - SYSTEMZ_INS_BNOR - bnor $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmNP (636) - SYSTEMZ_INS_BNPR - bnpr $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmNZ (637) - SYSTEMZ_INS_BNZR - bnzr $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmO (638) - SYSTEMZ_INS_BOR - bor $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmP (639) - SYSTEMZ_INS_BPR - bpr $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRAsmZ (640) - SYSTEMZ_INS_BZR - bzr $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_BRC (641) - SYSTEMZ_INS_INVALID - j${M1} $RI2 */ + 0 +}}}, +{ /* SYSTEMZ_BRCAsm (642) - SYSTEMZ_INS_BRC - brc $M1, $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_BRCL (643) - SYSTEMZ_INS_INVALID - jg${M1} $RI2 */ + 0 +}}}, +{ /* SYSTEMZ_BRCLAsm (644) - SYSTEMZ_INS_BRCL - brcl $M1, $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRCT (645) - SYSTEMZ_INS_BRCT - brct $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRCTG (646) - SYSTEMZ_INS_BRCTG - brctg $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRCTH (647) - SYSTEMZ_INS_BRCTH - brcth $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRXH (648) - SYSTEMZ_INS_BRXH - brxh $R1, $R3, $RI2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRXHG (649) - SYSTEMZ_INS_BRXHG - brxhg $R1, $R3, $RI2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRXLE (650) - SYSTEMZ_INS_BRXLE - brxle $R1, $R3, $RI2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_BRXLG (651) - SYSTEMZ_INS_BRXLG - brxlg $R1, $R3, $RI2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_BSA (652) - SYSTEMZ_INS_BSA - bsa $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BSG (653) - SYSTEMZ_INS_BSG - bsg $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BSM (654) - SYSTEMZ_INS_BSM - bsm $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_BXH (655) - SYSTEMZ_INS_BXH - bxh $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_BXHG (656) - SYSTEMZ_INS_BXHG - bxhg $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_BXLE (657) - SYSTEMZ_INS_BXLE - bxle $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_BXLEG (658) - SYSTEMZ_INS_BXLEG - bxleg $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_C (659) - SYSTEMZ_INS_C - c $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CD (660) - SYSTEMZ_INS_CD - cd $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CDB (661) - SYSTEMZ_INS_CDB - cdb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CDBR (662) - SYSTEMZ_INS_CDBR - cdbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CDFBR (663) - SYSTEMZ_INS_CDFBR - cdfbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CDFBRA (664) - SYSTEMZ_INS_CDFBRA - cdfbra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CDFR (665) - SYSTEMZ_INS_CDFR - cdfr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CDFTR (666) - SYSTEMZ_INS_CDFTR - cdftr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CDGBR (667) - SYSTEMZ_INS_CDGBR - cdgbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CDGBRA (668) - SYSTEMZ_INS_CDGBRA - cdgbra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CDGR (669) - SYSTEMZ_INS_CDGR - cdgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CDGTR (670) - SYSTEMZ_INS_CDGTR - cdgtr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CDGTRA (671) - SYSTEMZ_INS_CDGTRA - cdgtra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CDLFBR (672) - SYSTEMZ_INS_CDLFBR - cdlfbr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CDLFTR (673) - SYSTEMZ_INS_CDLFTR - cdlftr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CDLGBR (674) - SYSTEMZ_INS_CDLGBR - cdlgbr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CDLGTR (675) - SYSTEMZ_INS_CDLGTR - cdlgtr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CDPT (676) - SYSTEMZ_INS_CDPT - cdpt $R1, $BDL2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - len8imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CDR (677) - SYSTEMZ_INS_CDR - cdr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CDS (678) - SYSTEMZ_INS_CDS - cds $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CDSG (679) - SYSTEMZ_INS_CDSG - cdsg $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CDSTR (680) - SYSTEMZ_INS_CDSTR - cdstr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CDSY (681) - SYSTEMZ_INS_CDSY - cdsy $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CDTR (682) - SYSTEMZ_INS_CDTR - cdtr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CDUTR (683) - SYSTEMZ_INS_CDUTR - cdutr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CDZT (684) - SYSTEMZ_INS_CDZT - cdzt $R1, $BDL2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - len8imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CE (685) - SYSTEMZ_INS_CE - ce $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CEB (686) - SYSTEMZ_INS_CEB - ceb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CEBR (687) - SYSTEMZ_INS_CEBR - cebr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CEDTR (688) - SYSTEMZ_INS_CEDTR - cedtr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CEFBR (689) - SYSTEMZ_INS_CEFBR - cefbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CEFBRA (690) - SYSTEMZ_INS_CEFBRA - cefbra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CEFR (691) - SYSTEMZ_INS_CEFR - cefr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CEGBR (692) - SYSTEMZ_INS_CEGBR - cegbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CEGBRA (693) - SYSTEMZ_INS_CEGBRA - cegbra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CEGR (694) - SYSTEMZ_INS_CEGR - cegr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CELFBR (695) - SYSTEMZ_INS_CELFBR - celfbr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CELGBR (696) - SYSTEMZ_INS_CELGBR - celgbr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CER (697) - SYSTEMZ_INS_CER - cer $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CEXTR (698) - SYSTEMZ_INS_CEXTR - cextr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CFC (699) - SYSTEMZ_INS_CFC - cfc $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CFDBR (700) - SYSTEMZ_INS_CFDBR - cfdbr $R1, $M3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CFDBRA (701) - SYSTEMZ_INS_CFDBRA - cfdbra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CFDR (702) - SYSTEMZ_INS_CFDR - cfdr $R1, $M3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CFDTR (703) - SYSTEMZ_INS_CFDTR - cfdtr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CFEBR (704) - SYSTEMZ_INS_CFEBR - cfebr $R1, $M3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CFEBRA (705) - SYSTEMZ_INS_CFEBRA - cfebra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CFER (706) - SYSTEMZ_INS_CFER - cfer $R1, $M3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CFI (707) - SYSTEMZ_INS_CFI - cfi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CFXBR (708) - SYSTEMZ_INS_CFXBR - cfxbr $R1, $M3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CFXBRA (709) - SYSTEMZ_INS_CFXBRA - cfxbra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CFXR (710) - SYSTEMZ_INS_CFXR - cfxr $R1, $M3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CFXTR (711) - SYSTEMZ_INS_CFXTR - cfxtr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CG (712) - SYSTEMZ_INS_CG - cg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGDBR (713) - SYSTEMZ_INS_CGDBR - cgdbr $R1, $M3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGDBRA (714) - SYSTEMZ_INS_CGDBRA - cgdbra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGDR (715) - SYSTEMZ_INS_CGDR - cgdr $R1, $M3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGDTR (716) - SYSTEMZ_INS_CGDTR - cgdtr $R1, $M3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGDTRA (717) - SYSTEMZ_INS_CGDTRA - cgdtra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGEBR (718) - SYSTEMZ_INS_CGEBR - cgebr $R1, $M3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGEBRA (719) - SYSTEMZ_INS_CGEBRA - cgebra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGER (720) - SYSTEMZ_INS_CGER - cger $R1, $M3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGF (721) - SYSTEMZ_INS_CGF - cgf $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGFI (722) - SYSTEMZ_INS_CGFI - cgfi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGFR (723) - SYSTEMZ_INS_CGFR - cgfr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGFRL (724) - SYSTEMZ_INS_CGFRL - cgfrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_CGH (725) - SYSTEMZ_INS_CGH - cgh $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGHI (726) - SYSTEMZ_INS_CGHI - cghi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGHRL (727) - SYSTEMZ_INS_CGHRL - cghrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_CGHSI (728) - SYSTEMZ_INS_CGHSI - cghsi $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CGIB (729) - SYSTEMZ_INS_INVALID - cgib$M3 $R1, $I2, $BD4 */ + 0 +}}}, +{ /* SYSTEMZ_CGIBAsm (730) - SYSTEMZ_INS_CGIB - cgib $R1, $I2, $M3, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIBAsmE (731) - SYSTEMZ_INS_CGIBE - cgibe $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIBAsmH (732) - SYSTEMZ_INS_CGIBH - cgibh $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIBAsmHE (733) - SYSTEMZ_INS_CGIBHE - cgibhe $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIBAsmL (734) - SYSTEMZ_INS_CGIBL - cgibl $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIBAsmLE (735) - SYSTEMZ_INS_CGIBLE - cgible $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIBAsmLH (736) - SYSTEMZ_INS_CGIBLH - cgiblh $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIBAsmNE (737) - SYSTEMZ_INS_CGIBNE - cgibne $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIBAsmNH (738) - SYSTEMZ_INS_CGIBNH - cgibnh $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIBAsmNHE (739) - SYSTEMZ_INS_CGIBNHE - cgibnhe $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIBAsmNL (740) - SYSTEMZ_INS_CGIBNL - cgibnl $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIBAsmNLE (741) - SYSTEMZ_INS_CGIBNLE - cgibnle $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIBAsmNLH (742) - SYSTEMZ_INS_CGIBNLH - cgibnlh $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CGIJ (743) - SYSTEMZ_INS_INVALID - cgij$M3 $R1, $I2, $RI4 */ + 0 +}}}, +{ /* SYSTEMZ_CGIJAsm (744) - SYSTEMZ_INS_CGIJ - cgij $R1, $I2, $M3, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIJAsmE (745) - SYSTEMZ_INS_CGIJE - cgije $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIJAsmH (746) - SYSTEMZ_INS_CGIJH - cgijh $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIJAsmHE (747) - SYSTEMZ_INS_CGIJHE - cgijhe $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIJAsmL (748) - SYSTEMZ_INS_CGIJL - cgijl $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIJAsmLE (749) - SYSTEMZ_INS_CGIJLE - cgijle $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIJAsmLH (750) - SYSTEMZ_INS_CGIJLH - cgijlh $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIJAsmNE (751) - SYSTEMZ_INS_CGIJNE - cgijne $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIJAsmNH (752) - SYSTEMZ_INS_CGIJNH - cgijnh $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIJAsmNHE (753) - SYSTEMZ_INS_CGIJNHE - cgijnhe $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIJAsmNL (754) - SYSTEMZ_INS_CGIJNL - cgijnl $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIJAsmNLE (755) - SYSTEMZ_INS_CGIJNLE - cgijnle $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGIJAsmNLH (756) - SYSTEMZ_INS_CGIJNLH - cgijnlh $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CGIT (757) - SYSTEMZ_INS_INVALID - cgit$M3 $R1, $I2 */ + 0 +}}}, +{ /* SYSTEMZ_CGITAsm (758) - SYSTEMZ_INS_CGIT - cgit $R1, $I2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CGITAsmE (759) - SYSTEMZ_INS_CGITE - cgite $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGITAsmH (760) - SYSTEMZ_INS_CGITH - cgith $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGITAsmHE (761) - SYSTEMZ_INS_CGITHE - cgithe $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGITAsmL (762) - SYSTEMZ_INS_CGITL - cgitl $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGITAsmLE (763) - SYSTEMZ_INS_CGITLE - cgitle $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGITAsmLH (764) - SYSTEMZ_INS_CGITLH - cgitlh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGITAsmNE (765) - SYSTEMZ_INS_CGITNE - cgitne $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGITAsmNH (766) - SYSTEMZ_INS_CGITNH - cgitnh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGITAsmNHE (767) - SYSTEMZ_INS_CGITNHE - cgitnhe $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGITAsmNL (768) - SYSTEMZ_INS_CGITNL - cgitnl $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGITAsmNLE (769) - SYSTEMZ_INS_CGITNLE - cgitnle $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGITAsmNLH (770) - SYSTEMZ_INS_CGITNLH - cgitnlh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGR (771) - SYSTEMZ_INS_CGR - cgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CGRB (772) - SYSTEMZ_INS_INVALID - cgrb$M3 $R1, $R2, $BD4 */ + 0 +}}}, +{ /* SYSTEMZ_CGRBAsm (773) - SYSTEMZ_INS_CGRB - cgrb $R1, $R2, $M3, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRBAsmE (774) - SYSTEMZ_INS_CGRBE - cgrbe $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRBAsmH (775) - SYSTEMZ_INS_CGRBH - cgrbh $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRBAsmHE (776) - SYSTEMZ_INS_CGRBHE - cgrbhe $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRBAsmL (777) - SYSTEMZ_INS_CGRBL - cgrbl $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRBAsmLE (778) - SYSTEMZ_INS_CGRBLE - cgrble $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRBAsmLH (779) - SYSTEMZ_INS_CGRBLH - cgrblh $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRBAsmNE (780) - SYSTEMZ_INS_CGRBNE - cgrbne $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRBAsmNH (781) - SYSTEMZ_INS_CGRBNH - cgrbnh $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRBAsmNHE (782) - SYSTEMZ_INS_CGRBNHE - cgrbnhe $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRBAsmNL (783) - SYSTEMZ_INS_CGRBNL - cgrbnl $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRBAsmNLE (784) - SYSTEMZ_INS_CGRBNLE - cgrbnle $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRBAsmNLH (785) - SYSTEMZ_INS_CGRBNLH - cgrbnlh $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CGRJ (786) - SYSTEMZ_INS_INVALID - cgrj$M3 $R1, $R2, $RI4 */ + 0 +}}}, +{ /* SYSTEMZ_CGRJAsm (787) - SYSTEMZ_INS_CGRJ - cgrj $R1, $R2, $M3, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRJAsmE (788) - SYSTEMZ_INS_CGRJE - cgrje $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRJAsmH (789) - SYSTEMZ_INS_CGRJH - cgrjh $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRJAsmHE (790) - SYSTEMZ_INS_CGRJHE - cgrjhe $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRJAsmL (791) - SYSTEMZ_INS_CGRJL - cgrjl $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRJAsmLE (792) - SYSTEMZ_INS_CGRJLE - cgrjle $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRJAsmLH (793) - SYSTEMZ_INS_CGRJLH - cgrjlh $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRJAsmNE (794) - SYSTEMZ_INS_CGRJNE - cgrjne $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRJAsmNH (795) - SYSTEMZ_INS_CGRJNH - cgrjnh $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRJAsmNHE (796) - SYSTEMZ_INS_CGRJNHE - cgrjnhe $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRJAsmNL (797) - SYSTEMZ_INS_CGRJNL - cgrjnl $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRJAsmNLE (798) - SYSTEMZ_INS_CGRJNLE - cgrjnle $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRJAsmNLH (799) - SYSTEMZ_INS_CGRJNLH - cgrjnlh $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRL (800) - SYSTEMZ_INS_CGRL - cgrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CGRT (801) - SYSTEMZ_INS_INVALID - cgrt$M3 $R1, $R2 */ + 0 +}}}, +{ /* SYSTEMZ_CGRTAsm (802) - SYSTEMZ_INS_CGRT - cgrt $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRTAsmE (803) - SYSTEMZ_INS_CGRTE - cgrte $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRTAsmH (804) - SYSTEMZ_INS_CGRTH - cgrth $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRTAsmHE (805) - SYSTEMZ_INS_CGRTHE - cgrthe $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRTAsmL (806) - SYSTEMZ_INS_CGRTL - cgrtl $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRTAsmLE (807) - SYSTEMZ_INS_CGRTLE - cgrtle $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRTAsmLH (808) - SYSTEMZ_INS_CGRTLH - cgrtlh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRTAsmNE (809) - SYSTEMZ_INS_CGRTNE - cgrtne $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRTAsmNH (810) - SYSTEMZ_INS_CGRTNH - cgrtnh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRTAsmNHE (811) - SYSTEMZ_INS_CGRTNHE - cgrtnhe $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRTAsmNL (812) - SYSTEMZ_INS_CGRTNL - cgrtnl $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRTAsmNLE (813) - SYSTEMZ_INS_CGRTNLE - cgrtnle $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGRTAsmNLH (814) - SYSTEMZ_INS_CGRTNLH - cgrtnlh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGXBR (815) - SYSTEMZ_INS_CGXBR - cgxbr $R1, $M3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGXBRA (816) - SYSTEMZ_INS_CGXBRA - cgxbra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CGXR (817) - SYSTEMZ_INS_CGXR - cgxr $R1, $M3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGXTR (818) - SYSTEMZ_INS_CGXTR - cgxtr $R1, $M3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CGXTRA (819) - SYSTEMZ_INS_CGXTRA - cgxtra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CH (820) - SYSTEMZ_INS_CH - ch $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CHF (821) - SYSTEMZ_INS_CHF - chf $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CHHR (822) - SYSTEMZ_INS_CHHR - chhr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CHHSI (823) - SYSTEMZ_INS_CHHSI - chhsi $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CHI (824) - SYSTEMZ_INS_CHI - chi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CHLR (825) - SYSTEMZ_INS_CHLR - chlr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CHRL (826) - SYSTEMZ_INS_CHRL - chrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_CHSI (827) - SYSTEMZ_INS_CHSI - chsi $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CHY (828) - SYSTEMZ_INS_CHY - chy $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CIB (829) - SYSTEMZ_INS_INVALID - cib$M3 $R1, $I2, $BD4 */ + 0 +}}}, +{ /* SYSTEMZ_CIBAsm (830) - SYSTEMZ_INS_CIB - cib $R1, $I2, $M3, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CIBAsmE (831) - SYSTEMZ_INS_CIBE - cibe $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CIBAsmH (832) - SYSTEMZ_INS_CIBH - cibh $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CIBAsmHE (833) - SYSTEMZ_INS_CIBHE - cibhe $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CIBAsmL (834) - SYSTEMZ_INS_CIBL - cibl $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CIBAsmLE (835) - SYSTEMZ_INS_CIBLE - cible $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CIBAsmLH (836) - SYSTEMZ_INS_CIBLH - ciblh $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CIBAsmNE (837) - SYSTEMZ_INS_CIBNE - cibne $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CIBAsmNH (838) - SYSTEMZ_INS_CIBNH - cibnh $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CIBAsmNHE (839) - SYSTEMZ_INS_CIBNHE - cibnhe $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CIBAsmNL (840) - SYSTEMZ_INS_CIBNL - cibnl $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CIBAsmNLE (841) - SYSTEMZ_INS_CIBNLE - cibnle $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CIBAsmNLH (842) - SYSTEMZ_INS_CIBNLH - cibnlh $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CIH (843) - SYSTEMZ_INS_CIH - cih $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CIJ (844) - SYSTEMZ_INS_INVALID - cij$M3 $R1, $I2, $RI4 */ + 0 +}}}, +{ /* SYSTEMZ_CIJAsm (845) - SYSTEMZ_INS_CIJ - cij $R1, $I2, $M3, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CIJAsmE (846) - SYSTEMZ_INS_CIJE - cije $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CIJAsmH (847) - SYSTEMZ_INS_CIJH - cijh $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CIJAsmHE (848) - SYSTEMZ_INS_CIJHE - cijhe $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CIJAsmL (849) - SYSTEMZ_INS_CIJL - cijl $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CIJAsmLE (850) - SYSTEMZ_INS_CIJLE - cijle $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CIJAsmLH (851) - SYSTEMZ_INS_CIJLH - cijlh $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CIJAsmNE (852) - SYSTEMZ_INS_CIJNE - cijne $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CIJAsmNH (853) - SYSTEMZ_INS_CIJNH - cijnh $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CIJAsmNHE (854) - SYSTEMZ_INS_CIJNHE - cijnhe $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CIJAsmNL (855) - SYSTEMZ_INS_CIJNL - cijnl $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CIJAsmNLE (856) - SYSTEMZ_INS_CIJNLE - cijnle $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CIJAsmNLH (857) - SYSTEMZ_INS_CIJNLH - cijnlh $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CIT (858) - SYSTEMZ_INS_INVALID - cit$M3 $R1, $I2 */ + 0 +}}}, +{ /* SYSTEMZ_CITAsm (859) - SYSTEMZ_INS_CIT - cit $R1, $I2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CITAsmE (860) - SYSTEMZ_INS_CITE - cite $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CITAsmH (861) - SYSTEMZ_INS_CITH - cith $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CITAsmHE (862) - SYSTEMZ_INS_CITHE - cithe $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CITAsmL (863) - SYSTEMZ_INS_CITL - citl $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CITAsmLE (864) - SYSTEMZ_INS_CITLE - citle $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CITAsmLH (865) - SYSTEMZ_INS_CITLH - citlh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CITAsmNE (866) - SYSTEMZ_INS_CITNE - citne $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CITAsmNH (867) - SYSTEMZ_INS_CITNH - citnh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CITAsmNHE (868) - SYSTEMZ_INS_CITNHE - citnhe $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CITAsmNL (869) - SYSTEMZ_INS_CITNL - citnl $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CITAsmNLE (870) - SYSTEMZ_INS_CITNLE - citnle $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CITAsmNLH (871) - SYSTEMZ_INS_CITNLH - citnlh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CKSM (872) - SYSTEMZ_INS_CKSM - cksm $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_CL (873) - SYSTEMZ_INS_CL - cl $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLC (874) - SYSTEMZ_INS_CLC - clc $BDL1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len8imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLCL (875) - SYSTEMZ_INS_CLCL - clcl $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_CLCLE (876) - SYSTEMZ_INS_CLCLE - clcle $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R3src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_CLCLU (877) - SYSTEMZ_INS_CLCLU - clclu $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R3src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_CLFDBR (878) - SYSTEMZ_INS_CLFDBR - clfdbr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLFDTR (879) - SYSTEMZ_INS_CLFDTR - clfdtr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLFEBR (880) - SYSTEMZ_INS_CLFEBR - clfebr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLFHSI (881) - SYSTEMZ_INS_CLFHSI - clfhsi $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLFI (882) - SYSTEMZ_INS_CLFI - clfi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CLFIT (883) - SYSTEMZ_INS_INVALID - clfit$M3 $R1, $I2 */ + 0 +}}}, +{ /* SYSTEMZ_CLFITAsm (884) - SYSTEMZ_INS_CLFIT - clfit $R1, $I2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CLFITAsmE (885) - SYSTEMZ_INS_CLFITE - clfite $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLFITAsmH (886) - SYSTEMZ_INS_CLFITH - clfith $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLFITAsmHE (887) - SYSTEMZ_INS_CLFITHE - clfithe $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLFITAsmL (888) - SYSTEMZ_INS_CLFITL - clfitl $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLFITAsmLE (889) - SYSTEMZ_INS_CLFITLE - clfitle $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLFITAsmLH (890) - SYSTEMZ_INS_CLFITLH - clfitlh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLFITAsmNE (891) - SYSTEMZ_INS_CLFITNE - clfitne $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLFITAsmNH (892) - SYSTEMZ_INS_CLFITNH - clfitnh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLFITAsmNHE (893) - SYSTEMZ_INS_CLFITNHE - clfitnhe $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLFITAsmNL (894) - SYSTEMZ_INS_CLFITNL - clfitnl $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLFITAsmNLE (895) - SYSTEMZ_INS_CLFITNLE - clfitnle $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLFITAsmNLH (896) - SYSTEMZ_INS_CLFITNLH - clfitnlh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLFXBR (897) - SYSTEMZ_INS_CLFXBR - clfxbr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLFXTR (898) - SYSTEMZ_INS_CLFXTR - clfxtr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLG (899) - SYSTEMZ_INS_CLG - clg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGDBR (900) - SYSTEMZ_INS_CLGDBR - clgdbr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGDTR (901) - SYSTEMZ_INS_CLGDTR - clgdtr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGEBR (902) - SYSTEMZ_INS_CLGEBR - clgebr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGF (903) - SYSTEMZ_INS_CLGF - clgf $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGFI (904) - SYSTEMZ_INS_CLGFI - clgfi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGFR (905) - SYSTEMZ_INS_CLGFR - clgfr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGFRL (906) - SYSTEMZ_INS_CLGFRL - clgfrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGHRL (907) - SYSTEMZ_INS_CLGHRL - clghrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGHSI (908) - SYSTEMZ_INS_CLGHSI - clghsi $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CLGIB (909) - SYSTEMZ_INS_INVALID - clgib$M3 $R1, $I2, $BD4 */ + 0 +}}}, +{ /* SYSTEMZ_CLGIBAsm (910) - SYSTEMZ_INS_CLGIB - clgib $R1, $I2, $M3, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIBAsmE (911) - SYSTEMZ_INS_CLGIBE - clgibe $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIBAsmH (912) - SYSTEMZ_INS_CLGIBH - clgibh $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIBAsmHE (913) - SYSTEMZ_INS_CLGIBHE - clgibhe $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIBAsmL (914) - SYSTEMZ_INS_CLGIBL - clgibl $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIBAsmLE (915) - SYSTEMZ_INS_CLGIBLE - clgible $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIBAsmLH (916) - SYSTEMZ_INS_CLGIBLH - clgiblh $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIBAsmNE (917) - SYSTEMZ_INS_CLGIBNE - clgibne $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIBAsmNH (918) - SYSTEMZ_INS_CLGIBNH - clgibnh $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIBAsmNHE (919) - SYSTEMZ_INS_CLGIBNHE - clgibnhe $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIBAsmNL (920) - SYSTEMZ_INS_CLGIBNL - clgibnl $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIBAsmNLE (921) - SYSTEMZ_INS_CLGIBNLE - clgibnle $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIBAsmNLH (922) - SYSTEMZ_INS_CLGIBNLH - clgibnlh $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CLGIJ (923) - SYSTEMZ_INS_INVALID - clgij$M3 $R1, $I2, $RI4 */ + 0 +}}}, +{ /* SYSTEMZ_CLGIJAsm (924) - SYSTEMZ_INS_CLGIJ - clgij $R1, $I2, $M3, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIJAsmE (925) - SYSTEMZ_INS_CLGIJE - clgije $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIJAsmH (926) - SYSTEMZ_INS_CLGIJH - clgijh $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIJAsmHE (927) - SYSTEMZ_INS_CLGIJHE - clgijhe $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIJAsmL (928) - SYSTEMZ_INS_CLGIJL - clgijl $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIJAsmLE (929) - SYSTEMZ_INS_CLGIJLE - clgijle $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIJAsmLH (930) - SYSTEMZ_INS_CLGIJLH - clgijlh $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIJAsmNE (931) - SYSTEMZ_INS_CLGIJNE - clgijne $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIJAsmNH (932) - SYSTEMZ_INS_CLGIJNH - clgijnh $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIJAsmNHE (933) - SYSTEMZ_INS_CLGIJNHE - clgijnhe $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIJAsmNL (934) - SYSTEMZ_INS_CLGIJNL - clgijnl $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIJAsmNLE (935) - SYSTEMZ_INS_CLGIJNLE - clgijnle $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGIJAsmNLH (936) - SYSTEMZ_INS_CLGIJNLH - clgijnlh $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CLGIT (937) - SYSTEMZ_INS_INVALID - clgit$M3 $R1, $I2 */ + 0 +}}}, +{ /* SYSTEMZ_CLGITAsm (938) - SYSTEMZ_INS_CLGIT - clgit $R1, $I2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGITAsmE (939) - SYSTEMZ_INS_CLGITE - clgite $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGITAsmH (940) - SYSTEMZ_INS_CLGITH - clgith $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGITAsmHE (941) - SYSTEMZ_INS_CLGITHE - clgithe $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGITAsmL (942) - SYSTEMZ_INS_CLGITL - clgitl $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGITAsmLE (943) - SYSTEMZ_INS_CLGITLE - clgitle $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGITAsmLH (944) - SYSTEMZ_INS_CLGITLH - clgitlh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGITAsmNE (945) - SYSTEMZ_INS_CLGITNE - clgitne $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGITAsmNH (946) - SYSTEMZ_INS_CLGITNH - clgitnh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGITAsmNHE (947) - SYSTEMZ_INS_CLGITNHE - clgitnhe $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGITAsmNL (948) - SYSTEMZ_INS_CLGITNL - clgitnl $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGITAsmNLE (949) - SYSTEMZ_INS_CLGITNLE - clgitnle $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGITAsmNLH (950) - SYSTEMZ_INS_CLGITNLH - clgitnlh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGR (951) - SYSTEMZ_INS_CLGR - clgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CLGRB (952) - SYSTEMZ_INS_INVALID - clgrb$M3 $R1, $R2, $BD4 */ + 0 +}}}, +{ /* SYSTEMZ_CLGRBAsm (953) - SYSTEMZ_INS_CLGRB - clgrb $R1, $R2, $M3, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRBAsmE (954) - SYSTEMZ_INS_CLGRBE - clgrbe $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRBAsmH (955) - SYSTEMZ_INS_CLGRBH - clgrbh $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRBAsmHE (956) - SYSTEMZ_INS_CLGRBHE - clgrbhe $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRBAsmL (957) - SYSTEMZ_INS_CLGRBL - clgrbl $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRBAsmLE (958) - SYSTEMZ_INS_CLGRBLE - clgrble $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRBAsmLH (959) - SYSTEMZ_INS_CLGRBLH - clgrblh $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRBAsmNE (960) - SYSTEMZ_INS_CLGRBNE - clgrbne $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRBAsmNH (961) - SYSTEMZ_INS_CLGRBNH - clgrbnh $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRBAsmNHE (962) - SYSTEMZ_INS_CLGRBNHE - clgrbnhe $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRBAsmNL (963) - SYSTEMZ_INS_CLGRBNL - clgrbnl $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRBAsmNLE (964) - SYSTEMZ_INS_CLGRBNLE - clgrbnle $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRBAsmNLH (965) - SYSTEMZ_INS_CLGRBNLH - clgrbnlh $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CLGRJ (966) - SYSTEMZ_INS_INVALID - clgrj$M3 $R1, $R2, $RI4 */ + 0 +}}}, +{ /* SYSTEMZ_CLGRJAsm (967) - SYSTEMZ_INS_CLGRJ - clgrj $R1, $R2, $M3, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRJAsmE (968) - SYSTEMZ_INS_CLGRJE - clgrje $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRJAsmH (969) - SYSTEMZ_INS_CLGRJH - clgrjh $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRJAsmHE (970) - SYSTEMZ_INS_CLGRJHE - clgrjhe $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRJAsmL (971) - SYSTEMZ_INS_CLGRJL - clgrjl $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRJAsmLE (972) - SYSTEMZ_INS_CLGRJLE - clgrjle $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRJAsmLH (973) - SYSTEMZ_INS_CLGRJLH - clgrjlh $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRJAsmNE (974) - SYSTEMZ_INS_CLGRJNE - clgrjne $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRJAsmNH (975) - SYSTEMZ_INS_CLGRJNH - clgrjnh $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRJAsmNHE (976) - SYSTEMZ_INS_CLGRJNHE - clgrjnhe $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRJAsmNL (977) - SYSTEMZ_INS_CLGRJNL - clgrjnl $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRJAsmNLE (978) - SYSTEMZ_INS_CLGRJNLE - clgrjnle $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRJAsmNLH (979) - SYSTEMZ_INS_CLGRJNLH - clgrjnlh $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRL (980) - SYSTEMZ_INS_CLGRL - clgrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CLGRT (981) - SYSTEMZ_INS_INVALID - clgrt$M3 $R1, $R2 */ + 0 +}}}, +{ /* SYSTEMZ_CLGRTAsm (982) - SYSTEMZ_INS_CLGRT - clgrt $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRTAsmE (983) - SYSTEMZ_INS_CLGRTE - clgrte $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRTAsmH (984) - SYSTEMZ_INS_CLGRTH - clgrth $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRTAsmHE (985) - SYSTEMZ_INS_CLGRTHE - clgrthe $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRTAsmL (986) - SYSTEMZ_INS_CLGRTL - clgrtl $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRTAsmLE (987) - SYSTEMZ_INS_CLGRTLE - clgrtle $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRTAsmLH (988) - SYSTEMZ_INS_CLGRTLH - clgrtlh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRTAsmNE (989) - SYSTEMZ_INS_CLGRTNE - clgrtne $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRTAsmNH (990) - SYSTEMZ_INS_CLGRTNH - clgrtnh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRTAsmNHE (991) - SYSTEMZ_INS_CLGRTNHE - clgrtnhe $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRTAsmNL (992) - SYSTEMZ_INS_CLGRTNL - clgrtnl $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRTAsmNLE (993) - SYSTEMZ_INS_CLGRTNLE - clgrtnle $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGRTAsmNLH (994) - SYSTEMZ_INS_CLGRTNLH - clgrtnlh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CLGT (995) - SYSTEMZ_INS_INVALID - clgt$M3 $R1, $BD2 */ + 0 +}}}, +{ /* SYSTEMZ_CLGTAsm (996) - SYSTEMZ_INS_CLGT - clgt $R1, $M3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGTAsmE (997) - SYSTEMZ_INS_CLGTE - clgte $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGTAsmH (998) - SYSTEMZ_INS_CLGTH - clgth $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGTAsmHE (999) - SYSTEMZ_INS_CLGTHE - clgthe $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGTAsmL (1000) - SYSTEMZ_INS_CLGTL - clgtl $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGTAsmLE (1001) - SYSTEMZ_INS_CLGTLE - clgtle $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGTAsmLH (1002) - SYSTEMZ_INS_CLGTLH - clgtlh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGTAsmNE (1003) - SYSTEMZ_INS_CLGTNE - clgtne $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGTAsmNH (1004) - SYSTEMZ_INS_CLGTNH - clgtnh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGTAsmNHE (1005) - SYSTEMZ_INS_CLGTNHE - clgtnhe $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGTAsmNL (1006) - SYSTEMZ_INS_CLGTNL - clgtnl $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGTAsmNLE (1007) - SYSTEMZ_INS_CLGTNLE - clgtnle $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGTAsmNLH (1008) - SYSTEMZ_INS_CLGTNLH - clgtnlh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGXBR (1009) - SYSTEMZ_INS_CLGXBR - clgxbr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLGXTR (1010) - SYSTEMZ_INS_CLGXTR - clgxtr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLHF (1011) - SYSTEMZ_INS_CLHF - clhf $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLHHR (1012) - SYSTEMZ_INS_CLHHR - clhhr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLHHSI (1013) - SYSTEMZ_INS_CLHHSI - clhhsi $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLHLR (1014) - SYSTEMZ_INS_CLHLR - clhlr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLHRL (1015) - SYSTEMZ_INS_CLHRL - clhrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_CLI (1016) - SYSTEMZ_INS_CLI - cli $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CLIB (1017) - SYSTEMZ_INS_INVALID - clib$M3 $R1, $I2, $BD4 */ + 0 +}}}, +{ /* SYSTEMZ_CLIBAsm (1018) - SYSTEMZ_INS_CLIB - clib $R1, $I2, $M3, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIBAsmE (1019) - SYSTEMZ_INS_CLIBE - clibe $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIBAsmH (1020) - SYSTEMZ_INS_CLIBH - clibh $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIBAsmHE (1021) - SYSTEMZ_INS_CLIBHE - clibhe $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIBAsmL (1022) - SYSTEMZ_INS_CLIBL - clibl $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIBAsmLE (1023) - SYSTEMZ_INS_CLIBLE - clible $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIBAsmLH (1024) - SYSTEMZ_INS_CLIBLH - cliblh $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIBAsmNE (1025) - SYSTEMZ_INS_CLIBNE - clibne $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIBAsmNH (1026) - SYSTEMZ_INS_CLIBNH - clibnh $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIBAsmNHE (1027) - SYSTEMZ_INS_CLIBNHE - clibnhe $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIBAsmNL (1028) - SYSTEMZ_INS_CLIBNL - clibnl $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIBAsmNLE (1029) - SYSTEMZ_INS_CLIBNLE - clibnle $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIBAsmNLH (1030) - SYSTEMZ_INS_CLIBNLH - clibnlh $R1, $I2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIH (1031) - SYSTEMZ_INS_CLIH - clih $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CLIJ (1032) - SYSTEMZ_INS_INVALID - clij$M3 $R1, $I2, $RI4 */ + 0 +}}}, +{ /* SYSTEMZ_CLIJAsm (1033) - SYSTEMZ_INS_CLIJ - clij $R1, $I2, $M3, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIJAsmE (1034) - SYSTEMZ_INS_CLIJE - clije $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIJAsmH (1035) - SYSTEMZ_INS_CLIJH - clijh $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIJAsmHE (1036) - SYSTEMZ_INS_CLIJHE - clijhe $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIJAsmL (1037) - SYSTEMZ_INS_CLIJL - clijl $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIJAsmLE (1038) - SYSTEMZ_INS_CLIJLE - clijle $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIJAsmLH (1039) - SYSTEMZ_INS_CLIJLH - clijlh $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIJAsmNE (1040) - SYSTEMZ_INS_CLIJNE - clijne $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIJAsmNH (1041) - SYSTEMZ_INS_CLIJNH - clijnh $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIJAsmNHE (1042) - SYSTEMZ_INS_CLIJNHE - clijnhe $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIJAsmNL (1043) - SYSTEMZ_INS_CLIJNL - clijnl $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIJAsmNLE (1044) - SYSTEMZ_INS_CLIJNLE - clijnle $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIJAsmNLH (1045) - SYSTEMZ_INS_CLIJNLH - clijnlh $R1, $I2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLIY (1046) - SYSTEMZ_INS_CLIY - cliy $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp20imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLM (1047) - SYSTEMZ_INS_CLM - clm $R1, $M3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLMH (1048) - SYSTEMZ_INS_CLMH - clmh $R1, $M3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLMY (1049) - SYSTEMZ_INS_CLMY - clmy $R1, $M3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLR (1050) - SYSTEMZ_INS_CLR - clr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CLRB (1051) - SYSTEMZ_INS_INVALID - clrb$M3 $R1, $R2, $BD4 */ + 0 +}}}, +{ /* SYSTEMZ_CLRBAsm (1052) - SYSTEMZ_INS_CLRB - clrb $R1, $R2, $M3, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRBAsmE (1053) - SYSTEMZ_INS_CLRBE - clrbe $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRBAsmH (1054) - SYSTEMZ_INS_CLRBH - clrbh $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRBAsmHE (1055) - SYSTEMZ_INS_CLRBHE - clrbhe $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRBAsmL (1056) - SYSTEMZ_INS_CLRBL - clrbl $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRBAsmLE (1057) - SYSTEMZ_INS_CLRBLE - clrble $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRBAsmLH (1058) - SYSTEMZ_INS_CLRBLH - clrblh $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRBAsmNE (1059) - SYSTEMZ_INS_CLRBNE - clrbne $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRBAsmNH (1060) - SYSTEMZ_INS_CLRBNH - clrbnh $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRBAsmNHE (1061) - SYSTEMZ_INS_CLRBNHE - clrbnhe $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRBAsmNL (1062) - SYSTEMZ_INS_CLRBNL - clrbnl $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRBAsmNLE (1063) - SYSTEMZ_INS_CLRBNLE - clrbnle $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRBAsmNLH (1064) - SYSTEMZ_INS_CLRBNLH - clrbnlh $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CLRJ (1065) - SYSTEMZ_INS_INVALID - clrj$M3 $R1, $R2, $RI4 */ + 0 +}}}, +{ /* SYSTEMZ_CLRJAsm (1066) - SYSTEMZ_INS_CLRJ - clrj $R1, $R2, $M3, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRJAsmE (1067) - SYSTEMZ_INS_CLRJE - clrje $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRJAsmH (1068) - SYSTEMZ_INS_CLRJH - clrjh $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRJAsmHE (1069) - SYSTEMZ_INS_CLRJHE - clrjhe $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRJAsmL (1070) - SYSTEMZ_INS_CLRJL - clrjl $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRJAsmLE (1071) - SYSTEMZ_INS_CLRJLE - clrjle $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRJAsmLH (1072) - SYSTEMZ_INS_CLRJLH - clrjlh $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRJAsmNE (1073) - SYSTEMZ_INS_CLRJNE - clrjne $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRJAsmNH (1074) - SYSTEMZ_INS_CLRJNH - clrjnh $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRJAsmNHE (1075) - SYSTEMZ_INS_CLRJNHE - clrjnhe $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRJAsmNL (1076) - SYSTEMZ_INS_CLRJNL - clrjnl $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRJAsmNLE (1077) - SYSTEMZ_INS_CLRJNLE - clrjnle $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRJAsmNLH (1078) - SYSTEMZ_INS_CLRJNLH - clrjnlh $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRL (1079) - SYSTEMZ_INS_CLRL - clrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CLRT (1080) - SYSTEMZ_INS_INVALID - clrt$M3 $R1, $R2 */ + 0 +}}}, +{ /* SYSTEMZ_CLRTAsm (1081) - SYSTEMZ_INS_CLRT - clrt $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRTAsmE (1082) - SYSTEMZ_INS_CLRTE - clrte $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRTAsmH (1083) - SYSTEMZ_INS_CLRTH - clrth $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRTAsmHE (1084) - SYSTEMZ_INS_CLRTHE - clrthe $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRTAsmL (1085) - SYSTEMZ_INS_CLRTL - clrtl $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRTAsmLE (1086) - SYSTEMZ_INS_CLRTLE - clrtle $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRTAsmLH (1087) - SYSTEMZ_INS_CLRTLH - clrtlh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRTAsmNE (1088) - SYSTEMZ_INS_CLRTNE - clrtne $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRTAsmNH (1089) - SYSTEMZ_INS_CLRTNH - clrtnh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRTAsmNHE (1090) - SYSTEMZ_INS_CLRTNHE - clrtnhe $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRTAsmNL (1091) - SYSTEMZ_INS_CLRTNL - clrtnl $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRTAsmNLE (1092) - SYSTEMZ_INS_CLRTNLE - clrtnle $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLRTAsmNLH (1093) - SYSTEMZ_INS_CLRTNLH - clrtnlh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CLST (1094) - SYSTEMZ_INS_CLST - clst $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{{{ /* SYSTEMZ_CLT (1095) - SYSTEMZ_INS_INVALID - clt$M3 $R1, $BD2 */ + 0 +}}}, +{ /* SYSTEMZ_CLTAsm (1096) - SYSTEMZ_INS_CLT - clt $R1, $M3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CLTAsmE (1097) - SYSTEMZ_INS_CLTE - clte $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLTAsmH (1098) - SYSTEMZ_INS_CLTH - clth $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLTAsmHE (1099) - SYSTEMZ_INS_CLTHE - clthe $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLTAsmL (1100) - SYSTEMZ_INS_CLTL - cltl $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLTAsmLE (1101) - SYSTEMZ_INS_CLTLE - cltle $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLTAsmLH (1102) - SYSTEMZ_INS_CLTLH - cltlh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLTAsmNE (1103) - SYSTEMZ_INS_CLTNE - cltne $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLTAsmNH (1104) - SYSTEMZ_INS_CLTNH - cltnh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLTAsmNHE (1105) - SYSTEMZ_INS_CLTNHE - cltnhe $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLTAsmNL (1106) - SYSTEMZ_INS_CLTNL - cltnl $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLTAsmNLE (1107) - SYSTEMZ_INS_CLTNLE - cltnle $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLTAsmNLH (1108) - SYSTEMZ_INS_CLTNLH - cltnlh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CLY (1109) - SYSTEMZ_INS_CLY - cly $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CMPSC (1110) - SYSTEMZ_INS_CMPSC - cmpsc $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_CP (1111) - SYSTEMZ_INS_CP - cp $BDL1, $BDL2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len4imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - len4imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CPDT (1112) - SYSTEMZ_INS_CPDT - cpdt $R1, $BDL2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - len8imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CPSDRdd (1113) - SYSTEMZ_INS_CPSDR - cpsdr $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CPSDRds (1114) - SYSTEMZ_INS_INVALID - cpsdr $R1, $R3, $R2 */ + 0 +}}}, +{{{ /* SYSTEMZ_CPSDRsd (1115) - SYSTEMZ_INS_INVALID - cpsdr $R1, $R3, $R2 */ + 0 +}}}, +{{{ /* SYSTEMZ_CPSDRss (1116) - SYSTEMZ_INS_INVALID - cpsdr $R1, $R3, $R2 */ + 0 +}}}, +{ /* SYSTEMZ_CPXT (1117) - SYSTEMZ_INS_CPXT - cpxt $R1, $BDL2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - len8imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CPYA (1118) - SYSTEMZ_INS_CPYA - cpya $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CR (1119) - SYSTEMZ_INS_CR - cr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CRB (1120) - SYSTEMZ_INS_INVALID - crb$M3 $R1, $R2, $BD4 */ + 0 +}}}, +{ /* SYSTEMZ_CRBAsm (1121) - SYSTEMZ_INS_CRB - crb $R1, $R2, $M3, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CRBAsmE (1122) - SYSTEMZ_INS_CRBE - crbe $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CRBAsmH (1123) - SYSTEMZ_INS_CRBH - crbh $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CRBAsmHE (1124) - SYSTEMZ_INS_CRBHE - crbhe $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CRBAsmL (1125) - SYSTEMZ_INS_CRBL - crbl $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CRBAsmLE (1126) - SYSTEMZ_INS_CRBLE - crble $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CRBAsmLH (1127) - SYSTEMZ_INS_CRBLH - crblh $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CRBAsmNE (1128) - SYSTEMZ_INS_CRBNE - crbne $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CRBAsmNH (1129) - SYSTEMZ_INS_CRBNH - crbnh $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CRBAsmNHE (1130) - SYSTEMZ_INS_CRBNHE - crbnhe $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CRBAsmNL (1131) - SYSTEMZ_INS_CRBNL - crbnl $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CRBAsmNLE (1132) - SYSTEMZ_INS_CRBNLE - crbnle $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CRBAsmNLH (1133) - SYSTEMZ_INS_CRBNLH - crbnlh $R1, $R2, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CRDTE (1134) - SYSTEMZ_INS_CRDTE - crdte $R1, $R3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CRDTEOpt (1135) - SYSTEMZ_INS_CRDTE - crdte $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CRJ (1136) - SYSTEMZ_INS_INVALID - crj$M3 $R1, $R2, $RI4 */ + 0 +}}}, +{ /* SYSTEMZ_CRJAsm (1137) - SYSTEMZ_INS_CRJ - crj $R1, $R2, $M3, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CRJAsmE (1138) - SYSTEMZ_INS_CRJE - crje $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CRJAsmH (1139) - SYSTEMZ_INS_CRJH - crjh $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CRJAsmHE (1140) - SYSTEMZ_INS_CRJHE - crjhe $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CRJAsmL (1141) - SYSTEMZ_INS_CRJL - crjl $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CRJAsmLE (1142) - SYSTEMZ_INS_CRJLE - crjle $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CRJAsmLH (1143) - SYSTEMZ_INS_CRJLH - crjlh $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CRJAsmNE (1144) - SYSTEMZ_INS_CRJNE - crjne $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CRJAsmNH (1145) - SYSTEMZ_INS_CRJNH - crjnh $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CRJAsmNHE (1146) - SYSTEMZ_INS_CRJNHE - crjnhe $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CRJAsmNL (1147) - SYSTEMZ_INS_CRJNL - crjnl $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CRJAsmNLE (1148) - SYSTEMZ_INS_CRJNLE - crjnle $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CRJAsmNLH (1149) - SYSTEMZ_INS_CRJNLH - crjnlh $R1, $R2, $RI4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI4 */ + { 0 } +}}, +{ /* SYSTEMZ_CRL (1150) - SYSTEMZ_INS_CRL - crl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{{{ /* SYSTEMZ_CRT (1151) - SYSTEMZ_INS_INVALID - crt$M3 $R1, $R2 */ + 0 +}}}, +{ /* SYSTEMZ_CRTAsm (1152) - SYSTEMZ_INS_CRT - crt $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CRTAsmE (1153) - SYSTEMZ_INS_CRTE - crte $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CRTAsmH (1154) - SYSTEMZ_INS_CRTH - crth $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CRTAsmHE (1155) - SYSTEMZ_INS_CRTHE - crthe $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CRTAsmL (1156) - SYSTEMZ_INS_CRTL - crtl $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CRTAsmLE (1157) - SYSTEMZ_INS_CRTLE - crtle $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CRTAsmLH (1158) - SYSTEMZ_INS_CRTLH - crtlh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CRTAsmNE (1159) - SYSTEMZ_INS_CRTNE - crtne $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CRTAsmNH (1160) - SYSTEMZ_INS_CRTNH - crtnh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CRTAsmNHE (1161) - SYSTEMZ_INS_CRTNHE - crtnhe $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CRTAsmNL (1162) - SYSTEMZ_INS_CRTNL - crtnl $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CRTAsmNLE (1163) - SYSTEMZ_INS_CRTNLE - crtnle $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CRTAsmNLH (1164) - SYSTEMZ_INS_CRTNLH - crtnlh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CS (1165) - SYSTEMZ_INS_CS - cs $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CSCH (1166) - SYSTEMZ_INS_CSCH - csch */ +{ + { 0 } +}}, +{ /* SYSTEMZ_CSDTR (1167) - SYSTEMZ_INS_CSDTR - csdtr $R1, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CSG (1168) - SYSTEMZ_INS_CSG - csg $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CSP (1169) - SYSTEMZ_INS_CSP - csp $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CSPG (1170) - SYSTEMZ_INS_CSPG - cspg $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CSST (1171) - SYSTEMZ_INS_CSST - csst $BD1, $BD2, $R3 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_CSXTR (1172) - SYSTEMZ_INS_CSXTR - csxtr $R1, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CSY (1173) - SYSTEMZ_INS_CSY - csy $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_CU12 (1174) - SYSTEMZ_INS_CU12 - cu12 $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CU12Opt (1175) - SYSTEMZ_INS_CU12 - cu12 $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_CU14 (1176) - SYSTEMZ_INS_CU14 - cu14 $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CU14Opt (1177) - SYSTEMZ_INS_CU14 - cu14 $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_CU21 (1178) - SYSTEMZ_INS_CU21 - cu21 $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CU21Opt (1179) - SYSTEMZ_INS_CU21 - cu21 $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_CU24 (1180) - SYSTEMZ_INS_CU24 - cu24 $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CU24Opt (1181) - SYSTEMZ_INS_CU24 - cu24 $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_CU41 (1182) - SYSTEMZ_INS_CU41 - cu41 $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_CU42 (1183) - SYSTEMZ_INS_CU42 - cu42 $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_CUDTR (1184) - SYSTEMZ_INS_CUDTR - cudtr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CUSE (1185) - SYSTEMZ_INS_CUSE - cuse $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_CUTFU (1186) - SYSTEMZ_INS_CUTFU - cutfu $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CUTFUOpt (1187) - SYSTEMZ_INS_CUTFU - cutfu $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_CUUTF (1188) - SYSTEMZ_INS_CUUTF - cuutf $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CUUTFOpt (1189) - SYSTEMZ_INS_CUUTF - cuutf $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_CUXTR (1190) - SYSTEMZ_INS_CUXTR - cuxtr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CVB (1191) - SYSTEMZ_INS_CVB - cvb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CVBG (1192) - SYSTEMZ_INS_CVBG - cvbg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CVBY (1193) - SYSTEMZ_INS_CVBY - cvby $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CVD (1194) - SYSTEMZ_INS_CVD - cvd $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CVDG (1195) - SYSTEMZ_INS_CVDG - cvdg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CVDY (1196) - SYSTEMZ_INS_CVDY - cvdy $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CXBR (1197) - SYSTEMZ_INS_CXBR - cxbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CXFBR (1198) - SYSTEMZ_INS_CXFBR - cxfbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CXFBRA (1199) - SYSTEMZ_INS_CXFBRA - cxfbra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CXFR (1200) - SYSTEMZ_INS_CXFR - cxfr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CXFTR (1201) - SYSTEMZ_INS_CXFTR - cxftr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CXGBR (1202) - SYSTEMZ_INS_CXGBR - cxgbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CXGBRA (1203) - SYSTEMZ_INS_CXGBRA - cxgbra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CXGR (1204) - SYSTEMZ_INS_CXGR - cxgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CXGTR (1205) - SYSTEMZ_INS_CXGTR - cxgtr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CXGTRA (1206) - SYSTEMZ_INS_CXGTRA - cxgtra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CXLFBR (1207) - SYSTEMZ_INS_CXLFBR - cxlfbr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CXLFTR (1208) - SYSTEMZ_INS_CXLFTR - cxlftr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CXLGBR (1209) - SYSTEMZ_INS_CXLGBR - cxlgbr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CXLGTR (1210) - SYSTEMZ_INS_CXLGTR - cxlgtr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_CXPT (1211) - SYSTEMZ_INS_CXPT - cxpt $R1, $BDL2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - len8imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CXR (1212) - SYSTEMZ_INS_CXR - cxr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CXSTR (1213) - SYSTEMZ_INS_CXSTR - cxstr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CXTR (1214) - SYSTEMZ_INS_CXTR - cxtr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CXUTR (1215) - SYSTEMZ_INS_CXUTR - cxutr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_CXZT (1216) - SYSTEMZ_INS_CXZT - cxzt $R1, $BDL2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - len8imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CY (1217) - SYSTEMZ_INS_CY - cy $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_CZDT (1218) - SYSTEMZ_INS_CZDT - czdt $R1, $BDL2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - len8imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_CZXT (1219) - SYSTEMZ_INS_CZXT - czxt $R1, $BDL2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - len8imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_D (1220) - SYSTEMZ_INS_D - d $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_DD (1221) - SYSTEMZ_INS_DD - dd $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_DDB (1222) - SYSTEMZ_INS_DDB - ddb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_DDBR (1223) - SYSTEMZ_INS_DDBR - ddbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_DDR (1224) - SYSTEMZ_INS_DDR - ddr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_DDTR (1225) - SYSTEMZ_INS_DDTR - ddtr $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_DDTRA (1226) - SYSTEMZ_INS_DDTRA - ddtra $R1, $R2, $R3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_DE (1227) - SYSTEMZ_INS_DE - de $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_DEB (1228) - SYSTEMZ_INS_DEB - deb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_DEBR (1229) - SYSTEMZ_INS_DEBR - debr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_DER (1230) - SYSTEMZ_INS_DER - der $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_DFLTCC (1231) - SYSTEMZ_INS_DFLTCC - dfltcc $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_DIAG (1232) - SYSTEMZ_INS_DIAG - diag $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_DIDBR (1233) - SYSTEMZ_INS_DIDBR - didbr $R1, $R3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_DIEBR (1234) - SYSTEMZ_INS_DIEBR - diebr $R1, $R3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_DL (1235) - SYSTEMZ_INS_DL - dl $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_DLG (1236) - SYSTEMZ_INS_DLG - dlg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_DLGR (1237) - SYSTEMZ_INS_DLGR - dlgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_DLR (1238) - SYSTEMZ_INS_DLR - dlr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_DP (1239) - SYSTEMZ_INS_DP - dp $BDL1, $BDL2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len4imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - len4imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_DR (1240) - SYSTEMZ_INS_DR - dr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_DSG (1241) - SYSTEMZ_INS_DSG - dsg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_DSGF (1242) - SYSTEMZ_INS_DSGF - dsgf $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_DSGFR (1243) - SYSTEMZ_INS_DSGFR - dsgfr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_DSGR (1244) - SYSTEMZ_INS_DSGR - dsgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_DXBR (1245) - SYSTEMZ_INS_DXBR - dxbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_DXR (1246) - SYSTEMZ_INS_DXR - dxr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_DXTR (1247) - SYSTEMZ_INS_DXTR - dxtr $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_DXTRA (1248) - SYSTEMZ_INS_DXTRA - dxtra $R1, $R2, $R3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_EAR (1249) - SYSTEMZ_INS_EAR - ear $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_ECAG (1250) - SYSTEMZ_INS_ECAG - ecag $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_ECCTR (1251) - SYSTEMZ_INS_ECCTR - ecctr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_ECPGA (1252) - SYSTEMZ_INS_ECPGA - ecpga $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_ECTG (1253) - SYSTEMZ_INS_ECTG - ectg $BD1, $BD2, $R3 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_ED (1254) - SYSTEMZ_INS_ED - ed $BDL1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len8imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_EDMK (1255) - SYSTEMZ_INS_EDMK - edmk $BDL1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len8imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_EEDTR (1256) - SYSTEMZ_INS_EEDTR - eedtr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_EEXTR (1257) - SYSTEMZ_INS_EEXTR - eextr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_EFPC (1258) - SYSTEMZ_INS_EFPC - efpc $R1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { 0 } +}}, +{ /* SYSTEMZ_EPAIR (1259) - SYSTEMZ_INS_EPAIR - epair $R1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { 0 } +}}, +{ /* SYSTEMZ_EPAR (1260) - SYSTEMZ_INS_EPAR - epar $R1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { 0 } +}}, +{ /* SYSTEMZ_EPCTR (1261) - SYSTEMZ_INS_EPCTR - epctr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_EPSW (1262) - SYSTEMZ_INS_EPSW - epsw $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_EREG (1263) - SYSTEMZ_INS_EREG - ereg $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_EREGG (1264) - SYSTEMZ_INS_EREGG - eregg $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_ESAIR (1265) - SYSTEMZ_INS_ESAIR - esair $R1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { 0 } +}}, +{ /* SYSTEMZ_ESAR (1266) - SYSTEMZ_INS_ESAR - esar $R1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { 0 } +}}, +{ /* SYSTEMZ_ESDTR (1267) - SYSTEMZ_INS_ESDTR - esdtr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_ESEA (1268) - SYSTEMZ_INS_ESEA - esea $R1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { 0 } +}}, +{ /* SYSTEMZ_ESTA (1269) - SYSTEMZ_INS_ESTA - esta $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_ESXTR (1270) - SYSTEMZ_INS_ESXTR - esxtr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_ETND (1271) - SYSTEMZ_INS_ETND - etnd $R1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { 0 } +}}, +{ /* SYSTEMZ_EX (1272) - SYSTEMZ_INS_EX - ex $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_EXRL (1273) - SYSTEMZ_INS_EXRL - exrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_FIDBR (1274) - SYSTEMZ_INS_FIDBR - fidbr $R1, $M3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_FIDBRA (1275) - SYSTEMZ_INS_FIDBRA - fidbra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_FIDR (1276) - SYSTEMZ_INS_FIDR - fidr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_FIDTR (1277) - SYSTEMZ_INS_FIDTR - fidtr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_FIEBR (1278) - SYSTEMZ_INS_FIEBR - fiebr $R1, $M3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_FIEBRA (1279) - SYSTEMZ_INS_FIEBRA - fiebra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_FIER (1280) - SYSTEMZ_INS_FIER - fier $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_FIXBR (1281) - SYSTEMZ_INS_FIXBR - fixbr $R1, $M3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_FIXBRA (1282) - SYSTEMZ_INS_FIXBRA - fixbra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_FIXR (1283) - SYSTEMZ_INS_FIXR - fixr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_FIXTR (1284) - SYSTEMZ_INS_FIXTR - fixtr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_FLOGR (1285) - SYSTEMZ_INS_FLOGR - flogr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_HDR (1286) - SYSTEMZ_INS_HDR - hdr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_HER (1287) - SYSTEMZ_INS_HER - her $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_HSCH (1288) - SYSTEMZ_INS_HSCH - hsch */ +{ + { 0 } +}}, +{ /* SYSTEMZ_IAC (1289) - SYSTEMZ_INS_IAC - iac $R1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { 0 } +}}, +{ /* SYSTEMZ_IC (1290) - SYSTEMZ_INS_IC - ic $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{{{ /* SYSTEMZ_IC32 (1291) - SYSTEMZ_INS_INVALID - ic $R1, $XBD2 */ + 0 +}}}, +{{{ /* SYSTEMZ_IC32Y (1292) - SYSTEMZ_INS_INVALID - icy $R1, $XBD2 */ + 0 +}}}, +{ /* SYSTEMZ_ICM (1293) - SYSTEMZ_INS_ICM - icm $R1, $M3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_ICMH (1294) - SYSTEMZ_INS_ICMH - icmh $R1, $M3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_ICMY (1295) - SYSTEMZ_INS_ICMY - icmy $R1, $M3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_ICY (1296) - SYSTEMZ_INS_ICY - icy $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_IDTE (1297) - SYSTEMZ_INS_IDTE - idte $R1, $R3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_IDTEOpt (1298) - SYSTEMZ_INS_IDTE - idte $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_IEDTR (1299) - SYSTEMZ_INS_IEDTR - iedtr $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_IEXTR (1300) - SYSTEMZ_INS_IEXTR - iextr $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_IIHF (1301) - SYSTEMZ_INS_IIHF - iihf $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_IIHH (1302) - SYSTEMZ_INS_IIHH - iihh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_IIHL (1303) - SYSTEMZ_INS_IIHL - iihl $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_IILF (1304) - SYSTEMZ_INS_IILF - iilf $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_IILH (1305) - SYSTEMZ_INS_IILH - iilh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_IILL (1306) - SYSTEMZ_INS_IILL - iill $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_IPK (1307) - SYSTEMZ_INS_IPK - ipk */ +{ + { 0 } +}}, +{ /* SYSTEMZ_IPM (1308) - SYSTEMZ_INS_IPM - ipm $R1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { 0 } +}}, +{ /* SYSTEMZ_IPTE (1309) - SYSTEMZ_INS_IPTE - ipte $R1, $R2, $R3, $M4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_IPTEOpt (1310) - SYSTEMZ_INS_IPTE - ipte $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_IPTEOptOpt (1311) - SYSTEMZ_INS_IPTE - ipte $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_IRBM (1312) - SYSTEMZ_INS_IRBM - irbm $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_ISKE (1313) - SYSTEMZ_INS_ISKE - iske $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_IVSK (1314) - SYSTEMZ_INS_IVSK - ivsk $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_InsnE (1315) - SYSTEMZ_INS_INVALID - .insn e,$enc */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnRI (1316) - SYSTEMZ_INS_INVALID - .insn ri,$enc,$R1,$I2 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnRIE (1317) - SYSTEMZ_INS_INVALID - .insn rie,$enc,$R1,$R3,$I2 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnRIL (1318) - SYSTEMZ_INS_INVALID - .insn ril,$enc,$R1,$I2 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnRILU (1319) - SYSTEMZ_INS_INVALID - .insn rilu,$enc,$R1,$I2 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnRIS (1320) - SYSTEMZ_INS_INVALID - .insn ris,$enc,$R1,$I2,$M3,$BD4 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnRR (1321) - SYSTEMZ_INS_INVALID - .insn rr,$enc,$R1,$R2 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnRRE (1322) - SYSTEMZ_INS_INVALID - .insn rre,$enc,$R1,$R2 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnRRF (1323) - SYSTEMZ_INS_INVALID - .insn rrf,$enc,$R1,$R2,$R3,$M4 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnRRS (1324) - SYSTEMZ_INS_INVALID - .insn rrs,$enc,$R1,$R2,$M3,$BD4 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnRS (1325) - SYSTEMZ_INS_INVALID - .insn rs,$enc,$R1,$R3,$BD2 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnRSE (1326) - SYSTEMZ_INS_INVALID - .insn rse,$enc,$R1,$R3,$BD2 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnRSI (1327) - SYSTEMZ_INS_INVALID - .insn rsi,$enc,$R1,$R3,$RI2 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnRSY (1328) - SYSTEMZ_INS_INVALID - .insn rsy,$enc,$R1,$R3,$BD2 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnRX (1329) - SYSTEMZ_INS_INVALID - .insn rx,$enc,$R1,$XBD2 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnRXE (1330) - SYSTEMZ_INS_INVALID - .insn rxe,$enc,$R1,$XBD2 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnRXF (1331) - SYSTEMZ_INS_INVALID - .insn rxf,$enc,$R1,$R3,$XBD2 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnRXY (1332) - SYSTEMZ_INS_INVALID - .insn rxy,$enc,$R1,$XBD2 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnS (1333) - SYSTEMZ_INS_INVALID - .insn s,$enc,$BD2 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnSI (1334) - SYSTEMZ_INS_INVALID - .insn si,$enc,$BD1,$I2 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnSIL (1335) - SYSTEMZ_INS_INVALID - .insn sil,$enc,$BD1,$I2 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnSIY (1336) - SYSTEMZ_INS_INVALID - .insn siy,$enc,$BD1,$I2 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnSS (1337) - SYSTEMZ_INS_INVALID - .insn ss,$enc,$RBD1,$BD2,$R3 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnSSE (1338) - SYSTEMZ_INS_INVALID - .insn sse,$enc,$BD1,$BD2 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnSSF (1339) - SYSTEMZ_INS_INVALID - .insn ssf,$enc,$BD1,$BD2,$R3 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnVRI (1340) - SYSTEMZ_INS_INVALID - .insn vri,$enc,$V1,$V2,$I3,$M4,$M5 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnVRR (1341) - SYSTEMZ_INS_INVALID - .insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnVRS (1342) - SYSTEMZ_INS_INVALID - .insn vrs,$enc,$BD2,$M4 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnVRV (1343) - SYSTEMZ_INS_INVALID - .insn vrv,$enc,$V1,$VBD2,$M3 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnVRX (1344) - SYSTEMZ_INS_INVALID - .insn vrx,$enc,$V1,$XBD2,$M3 */ + 0 +}}}, +{{{ /* SYSTEMZ_InsnVSI (1345) - SYSTEMZ_INS_INVALID - .insn vsi,$enc,$V1,$BD2,$I3 */ + 0 +}}}, +{ /* SYSTEMZ_J (1346) - SYSTEMZ_INS_J - j $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmE (1347) - SYSTEMZ_INS_JE - je $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmH (1348) - SYSTEMZ_INS_JH - jh $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmHE (1349) - SYSTEMZ_INS_JHE - jhe $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmL (1350) - SYSTEMZ_INS_JL - jl $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmLE (1351) - SYSTEMZ_INS_JLE - jle $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmLH (1352) - SYSTEMZ_INS_JLH - jlh $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmM (1353) - SYSTEMZ_INS_JM - jm $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmNE (1354) - SYSTEMZ_INS_JNE - jne $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmNH (1355) - SYSTEMZ_INS_JNH - jnh $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmNHE (1356) - SYSTEMZ_INS_JNHE - jnhe $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmNL (1357) - SYSTEMZ_INS_JNL - jnl $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmNLE (1358) - SYSTEMZ_INS_JNLE - jnle $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmNLH (1359) - SYSTEMZ_INS_JNLH - jnlh $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmNM (1360) - SYSTEMZ_INS_JNM - jnm $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmNO (1361) - SYSTEMZ_INS_JNO - jno $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmNP (1362) - SYSTEMZ_INS_JNP - jnp $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmNZ (1363) - SYSTEMZ_INS_JNZ - jnz $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmO (1364) - SYSTEMZ_INS_JO - jo $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmP (1365) - SYSTEMZ_INS_JP - jp $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JAsmZ (1366) - SYSTEMZ_INS_JZ - jz $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JG (1367) - SYSTEMZ_INS_J_G_LU_ - j{g|lu} $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmE (1368) - SYSTEMZ_INS_J_G_L_E - j{g|l}e $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmH (1369) - SYSTEMZ_INS_J_G_L_H - j{g|l}h $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmHE (1370) - SYSTEMZ_INS_J_G_L_HE - j{g|l}he $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmL (1371) - SYSTEMZ_INS_J_G_L_L - j{g|l}l $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmLE (1372) - SYSTEMZ_INS_J_G_L_LE - j{g|l}le $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmLH (1373) - SYSTEMZ_INS_J_G_L_LH - j{g|l}lh $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmM (1374) - SYSTEMZ_INS_J_G_L_M - j{g|l}m $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmNE (1375) - SYSTEMZ_INS_J_G_L_NE - j{g|l}ne $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmNH (1376) - SYSTEMZ_INS_J_G_L_NH - j{g|l}nh $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmNHE (1377) - SYSTEMZ_INS_J_G_L_NHE - j{g|l}nhe $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmNL (1378) - SYSTEMZ_INS_J_G_L_NL - j{g|l}nl $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmNLE (1379) - SYSTEMZ_INS_J_G_L_NLE - j{g|l}nle $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmNLH (1380) - SYSTEMZ_INS_J_G_L_NLH - j{g|l}nlh $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmNM (1381) - SYSTEMZ_INS_J_G_L_NM - j{g|l}nm $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmNO (1382) - SYSTEMZ_INS_J_G_L_NO - j{g|l}no $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmNP (1383) - SYSTEMZ_INS_J_G_L_NP - j{g|l}np $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmNZ (1384) - SYSTEMZ_INS_J_G_L_NZ - j{g|l}nz $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmO (1385) - SYSTEMZ_INS_J_G_L_O - j{g|l}o $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmP (1386) - SYSTEMZ_INS_J_G_L_P - j{g|l}p $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_JGAsmZ (1387) - SYSTEMZ_INS_J_G_L_Z - j{g|l}z $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* RI2 */ + { 0 } +}}, +{ /* SYSTEMZ_KDB (1388) - SYSTEMZ_INS_KDB - kdb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_KDBR (1389) - SYSTEMZ_INS_KDBR - kdbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_KDSA (1390) - SYSTEMZ_INS_KDSA - kdsa $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_KDTR (1391) - SYSTEMZ_INS_KDTR - kdtr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_KEB (1392) - SYSTEMZ_INS_KEB - keb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_KEBR (1393) - SYSTEMZ_INS_KEBR - kebr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_KIMD (1394) - SYSTEMZ_INS_KIMD - kimd $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_KLMD (1395) - SYSTEMZ_INS_KLMD - klmd $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_KM (1396) - SYSTEMZ_INS_KM - km $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_KMA (1397) - SYSTEMZ_INS_KMA - kma $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R3src */ + { 0 } +}}, +{ /* SYSTEMZ_KMAC (1398) - SYSTEMZ_INS_KMAC - kmac $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_KMC (1399) - SYSTEMZ_INS_KMC - kmc $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_KMCTR (1400) - SYSTEMZ_INS_KMCTR - kmctr $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R3src */ + { 0 } +}}, +{ /* SYSTEMZ_KMF (1401) - SYSTEMZ_INS_KMF - kmf $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_KMO (1402) - SYSTEMZ_INS_KMO - kmo $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_KXBR (1403) - SYSTEMZ_INS_KXBR - kxbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_KXTR (1404) - SYSTEMZ_INS_KXTR - kxtr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_L (1405) - SYSTEMZ_INS_L - l $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LA (1406) - SYSTEMZ_INS_LA - la $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LAA (1407) - SYSTEMZ_INS_LAA - laa $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LAAG (1408) - SYSTEMZ_INS_LAAG - laag $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LAAL (1409) - SYSTEMZ_INS_LAAL - laal $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LAALG (1410) - SYSTEMZ_INS_LAALG - laalg $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LAE (1411) - SYSTEMZ_INS_LAE - lae $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LAEY (1412) - SYSTEMZ_INS_LAEY - laey $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LAM (1413) - SYSTEMZ_INS_LAM - lam $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LAMY (1414) - SYSTEMZ_INS_LAMY - lamy $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LAN (1415) - SYSTEMZ_INS_LAN - lan $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LANG (1416) - SYSTEMZ_INS_LANG - lang $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LAO (1417) - SYSTEMZ_INS_LAO - lao $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LAOG (1418) - SYSTEMZ_INS_LAOG - laog $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LARL (1419) - SYSTEMZ_INS_LARL - larl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_LASP (1420) - SYSTEMZ_INS_LASP - lasp $BD1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LAT (1421) - SYSTEMZ_INS_LAT - lat $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LAX (1422) - SYSTEMZ_INS_LAX - lax $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LAXG (1423) - SYSTEMZ_INS_LAXG - laxg $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LAY (1424) - SYSTEMZ_INS_LAY - lay $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LB (1425) - SYSTEMZ_INS_LB - lb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LBEAR (1426) - SYSTEMZ_INS_LBEAR - lbear $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LBH (1427) - SYSTEMZ_INS_LBH - lbh $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LBR (1428) - SYSTEMZ_INS_LBR - lbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LCBB (1429) - SYSTEMZ_INS_LCBB - lcbb $R1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_LCCTL (1430) - SYSTEMZ_INS_LCCTL - lcctl $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LCDBR (1431) - SYSTEMZ_INS_LCDBR - lcdbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LCDFR (1432) - SYSTEMZ_INS_LCDFR - lcdfr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_LCDFR_32 (1433) - SYSTEMZ_INS_INVALID - lcdfr $R1, $R2 */ + 0 +}}}, +{ /* SYSTEMZ_LCDR (1434) - SYSTEMZ_INS_LCDR - lcdr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LCEBR (1435) - SYSTEMZ_INS_LCEBR - lcebr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LCER (1436) - SYSTEMZ_INS_LCER - lcer $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LCGFR (1437) - SYSTEMZ_INS_LCGFR - lcgfr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LCGR (1438) - SYSTEMZ_INS_LCGR - lcgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LCR (1439) - SYSTEMZ_INS_LCR - lcr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LCTL (1440) - SYSTEMZ_INS_LCTL - lctl $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LCTLG (1441) - SYSTEMZ_INS_LCTLG - lctlg $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LCXBR (1442) - SYSTEMZ_INS_LCXBR - lcxbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LCXR (1443) - SYSTEMZ_INS_LCXR - lcxr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LD (1444) - SYSTEMZ_INS_LD - ld $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LDE (1445) - SYSTEMZ_INS_LDE - lde $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{{{ /* SYSTEMZ_LDE32 (1446) - SYSTEMZ_INS_INVALID - lde $R1, $XBD2 */ + 0 +}}}, +{ /* SYSTEMZ_LDEB (1447) - SYSTEMZ_INS_LDEB - ldeb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LDEBR (1448) - SYSTEMZ_INS_LDEBR - ldebr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LDER (1449) - SYSTEMZ_INS_LDER - lder $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LDETR (1450) - SYSTEMZ_INS_LDETR - ldetr $R1, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_LDGR (1451) - SYSTEMZ_INS_LDGR - ldgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LDR (1452) - SYSTEMZ_INS_LDR - ldr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_LDR32 (1453) - SYSTEMZ_INS_INVALID - ldr $R1, $R2 */ + 0 +}}}, +{ /* SYSTEMZ_LDXBR (1454) - SYSTEMZ_INS_LDXBR - ldxbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LDXBRA (1455) - SYSTEMZ_INS_LDXBRA - ldxbra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_LDXR (1456) - SYSTEMZ_INS_LDXR - ldxr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LDXTR (1457) - SYSTEMZ_INS_LDXTR - ldxtr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_LDY (1458) - SYSTEMZ_INS_LDY - ldy $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LE (1459) - SYSTEMZ_INS_LE - le $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LEDBR (1460) - SYSTEMZ_INS_LEDBR - ledbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LEDBRA (1461) - SYSTEMZ_INS_LEDBRA - ledbra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_LEDR (1462) - SYSTEMZ_INS_LEDR - ledr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LEDTR (1463) - SYSTEMZ_INS_LEDTR - ledtr $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_LER (1464) - SYSTEMZ_INS_LER - ler $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LEXBR (1465) - SYSTEMZ_INS_LEXBR - lexbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LEXBRA (1466) - SYSTEMZ_INS_LEXBRA - lexbra $R1, $M3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_LEXR (1467) - SYSTEMZ_INS_LEXR - lexr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LEY (1468) - SYSTEMZ_INS_LEY - ley $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LFAS (1469) - SYSTEMZ_INS_LFAS - lfas $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LFH (1470) - SYSTEMZ_INS_LFH - lfh $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LFHAT (1471) - SYSTEMZ_INS_LFHAT - lfhat $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LFPC (1472) - SYSTEMZ_INS_LFPC - lfpc $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LG (1473) - SYSTEMZ_INS_LG - lg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LGAT (1474) - SYSTEMZ_INS_LGAT - lgat $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LGB (1475) - SYSTEMZ_INS_LGB - lgb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LGBR (1476) - SYSTEMZ_INS_LGBR - lgbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LGDR (1477) - SYSTEMZ_INS_LGDR - lgdr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LGF (1478) - SYSTEMZ_INS_LGF - lgf $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LGFI (1479) - SYSTEMZ_INS_LGFI - lgfi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LGFR (1480) - SYSTEMZ_INS_LGFR - lgfr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LGFRL (1481) - SYSTEMZ_INS_LGFRL - lgfrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_LGG (1482) - SYSTEMZ_INS_LGG - lgg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LGH (1483) - SYSTEMZ_INS_LGH - lgh $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LGHI (1484) - SYSTEMZ_INS_LGHI - lghi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LGHR (1485) - SYSTEMZ_INS_LGHR - lghr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LGHRL (1486) - SYSTEMZ_INS_LGHRL - lghrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_LGR (1487) - SYSTEMZ_INS_LGR - lgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LGRL (1488) - SYSTEMZ_INS_LGRL - lgrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_LGSC (1489) - SYSTEMZ_INS_LGSC - lgsc $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LH (1490) - SYSTEMZ_INS_LH - lh $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LHH (1491) - SYSTEMZ_INS_LHH - lhh $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LHI (1492) - SYSTEMZ_INS_LHI - lhi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LHR (1493) - SYSTEMZ_INS_LHR - lhr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LHRL (1494) - SYSTEMZ_INS_LHRL - lhrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_LHY (1495) - SYSTEMZ_INS_LHY - lhy $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LLC (1496) - SYSTEMZ_INS_LLC - llc $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LLCH (1497) - SYSTEMZ_INS_LLCH - llch $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LLCR (1498) - SYSTEMZ_INS_LLCR - llcr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LLGC (1499) - SYSTEMZ_INS_LLGC - llgc $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LLGCR (1500) - SYSTEMZ_INS_LLGCR - llgcr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LLGF (1501) - SYSTEMZ_INS_LLGF - llgf $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LLGFAT (1502) - SYSTEMZ_INS_LLGFAT - llgfat $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LLGFR (1503) - SYSTEMZ_INS_LLGFR - llgfr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LLGFRL (1504) - SYSTEMZ_INS_LLGFRL - llgfrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_LLGFSG (1505) - SYSTEMZ_INS_LLGFSG - llgfsg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LLGH (1506) - SYSTEMZ_INS_LLGH - llgh $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LLGHR (1507) - SYSTEMZ_INS_LLGHR - llghr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LLGHRL (1508) - SYSTEMZ_INS_LLGHRL - llghrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_LLGT (1509) - SYSTEMZ_INS_LLGT - llgt $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LLGTAT (1510) - SYSTEMZ_INS_LLGTAT - llgtat $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LLGTR (1511) - SYSTEMZ_INS_LLGTR - llgtr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LLH (1512) - SYSTEMZ_INS_LLH - llh $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LLHH (1513) - SYSTEMZ_INS_LLHH - llhh $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LLHR (1514) - SYSTEMZ_INS_LLHR - llhr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LLHRL (1515) - SYSTEMZ_INS_LLHRL - llhrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_LLIHF (1516) - SYSTEMZ_INS_LLIHF - llihf $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LLIHH (1517) - SYSTEMZ_INS_LLIHH - llihh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LLIHL (1518) - SYSTEMZ_INS_LLIHL - llihl $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LLILF (1519) - SYSTEMZ_INS_LLILF - llilf $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LLILH (1520) - SYSTEMZ_INS_LLILH - llilh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LLILL (1521) - SYSTEMZ_INS_LLILL - llill $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LLZRGF (1522) - SYSTEMZ_INS_LLZRGF - llzrgf $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LM (1523) - SYSTEMZ_INS_LM - lm $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LMD (1524) - SYSTEMZ_INS_LMD - lmd $R1, $R3, $BD2, $BD4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LMG (1525) - SYSTEMZ_INS_LMG - lmg $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LMH (1526) - SYSTEMZ_INS_LMH - lmh $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LMY (1527) - SYSTEMZ_INS_LMY - lmy $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LNDBR (1528) - SYSTEMZ_INS_LNDBR - lndbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LNDFR (1529) - SYSTEMZ_INS_LNDFR - lndfr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_LNDFR_32 (1530) - SYSTEMZ_INS_INVALID - lndfr $R1, $R2 */ + 0 +}}}, +{ /* SYSTEMZ_LNDR (1531) - SYSTEMZ_INS_LNDR - lndr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LNEBR (1532) - SYSTEMZ_INS_LNEBR - lnebr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LNER (1533) - SYSTEMZ_INS_LNER - lner $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LNGFR (1534) - SYSTEMZ_INS_LNGFR - lngfr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LNGR (1535) - SYSTEMZ_INS_LNGR - lngr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LNR (1536) - SYSTEMZ_INS_LNR - lnr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LNXBR (1537) - SYSTEMZ_INS_LNXBR - lnxbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LNXR (1538) - SYSTEMZ_INS_LNXR - lnxr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_LOC (1539) - SYSTEMZ_INS_INVALID - loc$M3 $R1, $BD2 */ + 0 +}}}, +{ /* SYSTEMZ_LOCAsm (1540) - SYSTEMZ_INS_LOC - loc $R1, $BD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmE (1541) - SYSTEMZ_INS_LOCE - loce $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmH (1542) - SYSTEMZ_INS_LOCH - loch $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmHE (1543) - SYSTEMZ_INS_LOCHE - loche $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmL (1544) - SYSTEMZ_INS_LOCL - locl $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmLE (1545) - SYSTEMZ_INS_LOCLE - locle $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmLH (1546) - SYSTEMZ_INS_LOCLH - loclh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmM (1547) - SYSTEMZ_INS_LOCM - locm $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmNE (1548) - SYSTEMZ_INS_LOCNE - locne $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmNH (1549) - SYSTEMZ_INS_LOCNH - locnh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmNHE (1550) - SYSTEMZ_INS_LOCNHE - locnhe $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmNL (1551) - SYSTEMZ_INS_LOCNL - locnl $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmNLE (1552) - SYSTEMZ_INS_LOCNLE - locnle $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmNLH (1553) - SYSTEMZ_INS_LOCNLH - locnlh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmNM (1554) - SYSTEMZ_INS_LOCNM - locnm $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmNO (1555) - SYSTEMZ_INS_LOCNO - locno $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmNP (1556) - SYSTEMZ_INS_LOCNP - locnp $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmNZ (1557) - SYSTEMZ_INS_LOCNZ - locnz $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmO (1558) - SYSTEMZ_INS_LOCO - loco $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmP (1559) - SYSTEMZ_INS_LOCP - locp $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCAsmZ (1560) - SYSTEMZ_INS_LOCZ - locz $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{{{ /* SYSTEMZ_LOCFH (1561) - SYSTEMZ_INS_INVALID - locfh$M3 $R1, $BD2 */ + 0 +}}}, +{ /* SYSTEMZ_LOCFHAsm (1562) - SYSTEMZ_INS_LOCFH - locfh $R1, $BD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmE (1563) - SYSTEMZ_INS_LOCFHE - locfhe $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmH (1564) - SYSTEMZ_INS_LOCFHH - locfhh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmHE (1565) - SYSTEMZ_INS_LOCFHHE - locfhhe $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmL (1566) - SYSTEMZ_INS_LOCFHL - locfhl $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmLE (1567) - SYSTEMZ_INS_LOCFHLE - locfhle $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmLH (1568) - SYSTEMZ_INS_LOCFHLH - locfhlh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmM (1569) - SYSTEMZ_INS_LOCFHM - locfhm $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmNE (1570) - SYSTEMZ_INS_LOCFHNE - locfhne $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmNH (1571) - SYSTEMZ_INS_LOCFHNH - locfhnh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmNHE (1572) - SYSTEMZ_INS_LOCFHNHE - locfhnhe $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmNL (1573) - SYSTEMZ_INS_LOCFHNL - locfhnl $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmNLE (1574) - SYSTEMZ_INS_LOCFHNLE - locfhnle $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmNLH (1575) - SYSTEMZ_INS_LOCFHNLH - locfhnlh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmNM (1576) - SYSTEMZ_INS_LOCFHNM - locfhnm $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmNO (1577) - SYSTEMZ_INS_LOCFHNO - locfhno $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmNP (1578) - SYSTEMZ_INS_LOCFHNP - locfhnp $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmNZ (1579) - SYSTEMZ_INS_LOCFHNZ - locfhnz $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmO (1580) - SYSTEMZ_INS_LOCFHO - locfho $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmP (1581) - SYSTEMZ_INS_LOCFHP - locfhp $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHAsmZ (1582) - SYSTEMZ_INS_LOCFHZ - locfhz $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{{{ /* SYSTEMZ_LOCFHR (1583) - SYSTEMZ_INS_INVALID - locfhr$M3 $R1, $R2 */ + 0 +}}}, +{ /* SYSTEMZ_LOCFHRAsm (1584) - SYSTEMZ_INS_LOCFHR - locfhr $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmE (1585) - SYSTEMZ_INS_LOCFHRE - locfhre $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmH (1586) - SYSTEMZ_INS_LOCFHRH - locfhrh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmHE (1587) - SYSTEMZ_INS_LOCFHRHE - locfhrhe $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmL (1588) - SYSTEMZ_INS_LOCFHRL - locfhrl $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmLE (1589) - SYSTEMZ_INS_LOCFHRLE - locfhrle $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmLH (1590) - SYSTEMZ_INS_LOCFHRLH - locfhrlh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmM (1591) - SYSTEMZ_INS_LOCFHRM - locfhrm $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmNE (1592) - SYSTEMZ_INS_LOCFHRNE - locfhrne $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmNH (1593) - SYSTEMZ_INS_LOCFHRNH - locfhrnh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmNHE (1594) - SYSTEMZ_INS_LOCFHRNHE - locfhrnhe $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmNL (1595) - SYSTEMZ_INS_LOCFHRNL - locfhrnl $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmNLE (1596) - SYSTEMZ_INS_LOCFHRNLE - locfhrnle $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmNLH (1597) - SYSTEMZ_INS_LOCFHRNLH - locfhrnlh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmNM (1598) - SYSTEMZ_INS_LOCFHRNM - locfhrnm $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmNO (1599) - SYSTEMZ_INS_LOCFHRNO - locfhrno $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmNP (1600) - SYSTEMZ_INS_LOCFHRNP - locfhrnp $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmNZ (1601) - SYSTEMZ_INS_LOCFHRNZ - locfhrnz $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmO (1602) - SYSTEMZ_INS_LOCFHRO - locfhro $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmP (1603) - SYSTEMZ_INS_LOCFHRP - locfhrp $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCFHRAsmZ (1604) - SYSTEMZ_INS_LOCFHRZ - locfhrz $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_LOCG (1605) - SYSTEMZ_INS_INVALID - locg$M3 $R1, $BD2 */ + 0 +}}}, +{ /* SYSTEMZ_LOCGAsm (1606) - SYSTEMZ_INS_LOCG - locg $R1, $BD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmE (1607) - SYSTEMZ_INS_LOCGE - locge $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmH (1608) - SYSTEMZ_INS_LOCGH - locgh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmHE (1609) - SYSTEMZ_INS_LOCGHE - locghe $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmL (1610) - SYSTEMZ_INS_LOCGL - locgl $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmLE (1611) - SYSTEMZ_INS_LOCGLE - locgle $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmLH (1612) - SYSTEMZ_INS_LOCGLH - locglh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmM (1613) - SYSTEMZ_INS_LOCGM - locgm $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmNE (1614) - SYSTEMZ_INS_LOCGNE - locgne $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmNH (1615) - SYSTEMZ_INS_LOCGNH - locgnh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmNHE (1616) - SYSTEMZ_INS_LOCGNHE - locgnhe $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmNL (1617) - SYSTEMZ_INS_LOCGNL - locgnl $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmNLE (1618) - SYSTEMZ_INS_LOCGNLE - locgnle $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmNLH (1619) - SYSTEMZ_INS_LOCGNLH - locgnlh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmNM (1620) - SYSTEMZ_INS_LOCGNM - locgnm $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmNO (1621) - SYSTEMZ_INS_LOCGNO - locgno $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmNP (1622) - SYSTEMZ_INS_LOCGNP - locgnp $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmNZ (1623) - SYSTEMZ_INS_LOCGNZ - locgnz $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmO (1624) - SYSTEMZ_INS_LOCGO - locgo $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmP (1625) - SYSTEMZ_INS_LOCGP - locgp $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGAsmZ (1626) - SYSTEMZ_INS_LOCGZ - locgz $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{{{ /* SYSTEMZ_LOCGHI (1627) - SYSTEMZ_INS_INVALID - locghi$M3 $R1, $I2 */ + 0 +}}}, +{ /* SYSTEMZ_LOCGHIAsm (1628) - SYSTEMZ_INS_LOCGHI - locghi $R1, $I2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmE (1629) - SYSTEMZ_INS_LOCGHIE - locghie $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmH (1630) - SYSTEMZ_INS_LOCGHIH - locghih $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmHE (1631) - SYSTEMZ_INS_LOCGHIHE - locghihe $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmL (1632) - SYSTEMZ_INS_LOCGHIL - locghil $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmLE (1633) - SYSTEMZ_INS_LOCGHILE - locghile $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmLH (1634) - SYSTEMZ_INS_LOCGHILH - locghilh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmM (1635) - SYSTEMZ_INS_LOCGHIM - locghim $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmNE (1636) - SYSTEMZ_INS_LOCGHINE - locghine $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmNH (1637) - SYSTEMZ_INS_LOCGHINH - locghinh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmNHE (1638) - SYSTEMZ_INS_LOCGHINHE - locghinhe $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmNL (1639) - SYSTEMZ_INS_LOCGHINL - locghinl $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmNLE (1640) - SYSTEMZ_INS_LOCGHINLE - locghinle $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmNLH (1641) - SYSTEMZ_INS_LOCGHINLH - locghinlh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmNM (1642) - SYSTEMZ_INS_LOCGHINM - locghinm $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmNO (1643) - SYSTEMZ_INS_LOCGHINO - locghino $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmNP (1644) - SYSTEMZ_INS_LOCGHINP - locghinp $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmNZ (1645) - SYSTEMZ_INS_LOCGHINZ - locghinz $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmO (1646) - SYSTEMZ_INS_LOCGHIO - locghio $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmP (1647) - SYSTEMZ_INS_LOCGHIP - locghip $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGHIAsmZ (1648) - SYSTEMZ_INS_LOCGHIZ - locghiz $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_LOCGR (1649) - SYSTEMZ_INS_INVALID - locgr$M3 $R1, $R2 */ + 0 +}}}, +{ /* SYSTEMZ_LOCGRAsm (1650) - SYSTEMZ_INS_LOCGR - locgr $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmE (1651) - SYSTEMZ_INS_LOCGRE - locgre $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmH (1652) - SYSTEMZ_INS_LOCGRH - locgrh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmHE (1653) - SYSTEMZ_INS_LOCGRHE - locgrhe $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmL (1654) - SYSTEMZ_INS_LOCGRL - locgrl $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmLE (1655) - SYSTEMZ_INS_LOCGRLE - locgrle $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmLH (1656) - SYSTEMZ_INS_LOCGRLH - locgrlh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmM (1657) - SYSTEMZ_INS_LOCGRM - locgrm $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmNE (1658) - SYSTEMZ_INS_LOCGRNE - locgrne $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmNH (1659) - SYSTEMZ_INS_LOCGRNH - locgrnh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmNHE (1660) - SYSTEMZ_INS_LOCGRNHE - locgrnhe $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmNL (1661) - SYSTEMZ_INS_LOCGRNL - locgrnl $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmNLE (1662) - SYSTEMZ_INS_LOCGRNLE - locgrnle $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmNLH (1663) - SYSTEMZ_INS_LOCGRNLH - locgrnlh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmNM (1664) - SYSTEMZ_INS_LOCGRNM - locgrnm $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmNO (1665) - SYSTEMZ_INS_LOCGRNO - locgrno $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmNP (1666) - SYSTEMZ_INS_LOCGRNP - locgrnp $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmNZ (1667) - SYSTEMZ_INS_LOCGRNZ - locgrnz $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmO (1668) - SYSTEMZ_INS_LOCGRO - locgro $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmP (1669) - SYSTEMZ_INS_LOCGRP - locgrp $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCGRAsmZ (1670) - SYSTEMZ_INS_LOCGRZ - locgrz $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_LOCHHI (1671) - SYSTEMZ_INS_INVALID - lochhi$M3 $R1, $I2 */ + 0 +}}}, +{ /* SYSTEMZ_LOCHHIAsm (1672) - SYSTEMZ_INS_LOCHHI - lochhi $R1, $I2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmE (1673) - SYSTEMZ_INS_LOCHHIE - lochhie $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmH (1674) - SYSTEMZ_INS_LOCHHIH - lochhih $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmHE (1675) - SYSTEMZ_INS_LOCHHIHE - lochhihe $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmL (1676) - SYSTEMZ_INS_LOCHHIL - lochhil $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmLE (1677) - SYSTEMZ_INS_LOCHHILE - lochhile $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmLH (1678) - SYSTEMZ_INS_LOCHHILH - lochhilh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmM (1679) - SYSTEMZ_INS_LOCHHIM - lochhim $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmNE (1680) - SYSTEMZ_INS_LOCHHINE - lochhine $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmNH (1681) - SYSTEMZ_INS_LOCHHINH - lochhinh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmNHE (1682) - SYSTEMZ_INS_LOCHHINHE - lochhinhe $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmNL (1683) - SYSTEMZ_INS_LOCHHINL - lochhinl $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmNLE (1684) - SYSTEMZ_INS_LOCHHINLE - lochhinle $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmNLH (1685) - SYSTEMZ_INS_LOCHHINLH - lochhinlh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmNM (1686) - SYSTEMZ_INS_LOCHHINM - lochhinm $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmNO (1687) - SYSTEMZ_INS_LOCHHINO - lochhino $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmNP (1688) - SYSTEMZ_INS_LOCHHINP - lochhinp $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmNZ (1689) - SYSTEMZ_INS_LOCHHINZ - lochhinz $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmO (1690) - SYSTEMZ_INS_LOCHHIO - lochhio $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmP (1691) - SYSTEMZ_INS_LOCHHIP - lochhip $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHHIAsmZ (1692) - SYSTEMZ_INS_LOCHHIZ - lochhiz $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_LOCHI (1693) - SYSTEMZ_INS_INVALID - lochi$M3 $R1, $I2 */ + 0 +}}}, +{ /* SYSTEMZ_LOCHIAsm (1694) - SYSTEMZ_INS_LOCHI - lochi $R1, $I2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmE (1695) - SYSTEMZ_INS_LOCHIE - lochie $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmH (1696) - SYSTEMZ_INS_LOCHIH - lochih $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmHE (1697) - SYSTEMZ_INS_LOCHIHE - lochihe $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmL (1698) - SYSTEMZ_INS_LOCHIL - lochil $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmLE (1699) - SYSTEMZ_INS_LOCHILE - lochile $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmLH (1700) - SYSTEMZ_INS_LOCHILH - lochilh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmM (1701) - SYSTEMZ_INS_LOCHIM - lochim $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmNE (1702) - SYSTEMZ_INS_LOCHINE - lochine $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmNH (1703) - SYSTEMZ_INS_LOCHINH - lochinh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmNHE (1704) - SYSTEMZ_INS_LOCHINHE - lochinhe $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmNL (1705) - SYSTEMZ_INS_LOCHINL - lochinl $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmNLE (1706) - SYSTEMZ_INS_LOCHINLE - lochinle $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmNLH (1707) - SYSTEMZ_INS_LOCHINLH - lochinlh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmNM (1708) - SYSTEMZ_INS_LOCHINM - lochinm $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmNO (1709) - SYSTEMZ_INS_LOCHINO - lochino $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmNP (1710) - SYSTEMZ_INS_LOCHINP - lochinp $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmNZ (1711) - SYSTEMZ_INS_LOCHINZ - lochinz $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmO (1712) - SYSTEMZ_INS_LOCHIO - lochio $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmP (1713) - SYSTEMZ_INS_LOCHIP - lochip $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCHIAsmZ (1714) - SYSTEMZ_INS_LOCHIZ - lochiz $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_LOCR (1715) - SYSTEMZ_INS_INVALID - locr$M3 $R1, $R2 */ + 0 +}}}, +{ /* SYSTEMZ_LOCRAsm (1716) - SYSTEMZ_INS_LOCR - locr $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmE (1717) - SYSTEMZ_INS_LOCRE - locre $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmH (1718) - SYSTEMZ_INS_LOCRH - locrh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmHE (1719) - SYSTEMZ_INS_LOCRHE - locrhe $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmL (1720) - SYSTEMZ_INS_LOCRL - locrl $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmLE (1721) - SYSTEMZ_INS_LOCRLE - locrle $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmLH (1722) - SYSTEMZ_INS_LOCRLH - locrlh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmM (1723) - SYSTEMZ_INS_LOCRM - locrm $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmNE (1724) - SYSTEMZ_INS_LOCRNE - locrne $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmNH (1725) - SYSTEMZ_INS_LOCRNH - locrnh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmNHE (1726) - SYSTEMZ_INS_LOCRNHE - locrnhe $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmNL (1727) - SYSTEMZ_INS_LOCRNL - locrnl $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmNLE (1728) - SYSTEMZ_INS_LOCRNLE - locrnle $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmNLH (1729) - SYSTEMZ_INS_LOCRNLH - locrnlh $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmNM (1730) - SYSTEMZ_INS_LOCRNM - locrnm $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmNO (1731) - SYSTEMZ_INS_LOCRNO - locrno $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmNP (1732) - SYSTEMZ_INS_LOCRNP - locrnp $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmNZ (1733) - SYSTEMZ_INS_LOCRNZ - locrnz $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmO (1734) - SYSTEMZ_INS_LOCRO - locro $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmP (1735) - SYSTEMZ_INS_LOCRP - locrp $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LOCRAsmZ (1736) - SYSTEMZ_INS_LOCRZ - locrz $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LPCTL (1737) - SYSTEMZ_INS_LPCTL - lpctl $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LPD (1738) - SYSTEMZ_INS_LPD - lpd $R3, $BD1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LPDBR (1739) - SYSTEMZ_INS_LPDBR - lpdbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LPDFR (1740) - SYSTEMZ_INS_LPDFR - lpdfr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_LPDFR_32 (1741) - SYSTEMZ_INS_INVALID - lpdfr $R1, $R2 */ + 0 +}}}, +{ /* SYSTEMZ_LPDG (1742) - SYSTEMZ_INS_LPDG - lpdg $R3, $BD1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LPDR (1743) - SYSTEMZ_INS_LPDR - lpdr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LPEBR (1744) - SYSTEMZ_INS_LPEBR - lpebr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LPER (1745) - SYSTEMZ_INS_LPER - lper $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LPGFR (1746) - SYSTEMZ_INS_LPGFR - lpgfr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LPGR (1747) - SYSTEMZ_INS_LPGR - lpgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LPP (1748) - SYSTEMZ_INS_LPP - lpp $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LPQ (1749) - SYSTEMZ_INS_LPQ - lpq $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LPR (1750) - SYSTEMZ_INS_LPR - lpr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LPSW (1751) - SYSTEMZ_INS_LPSW - lpsw $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LPSWE (1752) - SYSTEMZ_INS_LPSWE - lpswe $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LPSWEY (1753) - SYSTEMZ_INS_LPSWEY - lpswey $BD1 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LPTEA (1754) - SYSTEMZ_INS_LPTEA - lptea $R1, $R3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_LPXBR (1755) - SYSTEMZ_INS_LPXBR - lpxbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LPXR (1756) - SYSTEMZ_INS_LPXR - lpxr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LR (1757) - SYSTEMZ_INS_LR - lr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LRA (1758) - SYSTEMZ_INS_LRA - lra $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LRAG (1759) - SYSTEMZ_INS_LRAG - lrag $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LRAY (1760) - SYSTEMZ_INS_LRAY - lray $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LRDR (1761) - SYSTEMZ_INS_LRDR - lrdr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LRER (1762) - SYSTEMZ_INS_LRER - lrer $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LRL (1763) - SYSTEMZ_INS_LRL - lrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_LRV (1764) - SYSTEMZ_INS_LRV - lrv $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LRVG (1765) - SYSTEMZ_INS_LRVG - lrvg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LRVGR (1766) - SYSTEMZ_INS_LRVGR - lrvgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LRVH (1767) - SYSTEMZ_INS_LRVH - lrvh $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LRVR (1768) - SYSTEMZ_INS_LRVR - lrvr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LSCTL (1769) - SYSTEMZ_INS_LSCTL - lsctl $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_LT (1770) - SYSTEMZ_INS_LT - lt $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LTDBR (1771) - SYSTEMZ_INS_LTDBR - ltdbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LTDR (1772) - SYSTEMZ_INS_LTDR - ltdr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LTDTR (1773) - SYSTEMZ_INS_LTDTR - ltdtr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LTEBR (1774) - SYSTEMZ_INS_LTEBR - ltebr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LTER (1775) - SYSTEMZ_INS_LTER - lter $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LTG (1776) - SYSTEMZ_INS_LTG - ltg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LTGF (1777) - SYSTEMZ_INS_LTGF - ltgf $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LTGFR (1778) - SYSTEMZ_INS_LTGFR - ltgfr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LTGR (1779) - SYSTEMZ_INS_LTGR - ltgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LTR (1780) - SYSTEMZ_INS_LTR - ltr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LTXBR (1781) - SYSTEMZ_INS_LTXBR - ltxbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LTXR (1782) - SYSTEMZ_INS_LTXR - ltxr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LTXTR (1783) - SYSTEMZ_INS_LTXTR - ltxtr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LURA (1784) - SYSTEMZ_INS_LURA - lura $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LURAG (1785) - SYSTEMZ_INS_LURAG - lurag $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LXD (1786) - SYSTEMZ_INS_LXD - lxd $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LXDB (1787) - SYSTEMZ_INS_LXDB - lxdb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LXDBR (1788) - SYSTEMZ_INS_LXDBR - lxdbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LXDR (1789) - SYSTEMZ_INS_LXDR - lxdr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LXDTR (1790) - SYSTEMZ_INS_LXDTR - lxdtr $R1, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_LXE (1791) - SYSTEMZ_INS_LXE - lxe $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LXEB (1792) - SYSTEMZ_INS_LXEB - lxeb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LXEBR (1793) - SYSTEMZ_INS_LXEBR - lxebr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LXER (1794) - SYSTEMZ_INS_LXER - lxer $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LXR (1795) - SYSTEMZ_INS_LXR - lxr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_LY (1796) - SYSTEMZ_INS_LY - ly $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LZDR (1797) - SYSTEMZ_INS_LZDR - lzdr $R1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { 0 } +}}, +{ /* SYSTEMZ_LZER (1798) - SYSTEMZ_INS_LZER - lzer $R1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { 0 } +}}, +{ /* SYSTEMZ_LZRF (1799) - SYSTEMZ_INS_LZRF - lzrf $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LZRG (1800) - SYSTEMZ_INS_LZRG - lzrg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_LZXR (1801) - SYSTEMZ_INS_LZXR - lzxr $R1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { 0 } +}}, +{ /* SYSTEMZ_M (1802) - SYSTEMZ_INS_M - m $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MAD (1803) - SYSTEMZ_INS_MAD - mad $R1, $R3, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MADB (1804) - SYSTEMZ_INS_MADB - madb $R1, $R3, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MADBR (1805) - SYSTEMZ_INS_MADBR - madbr $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MADR (1806) - SYSTEMZ_INS_MADR - madr $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MAE (1807) - SYSTEMZ_INS_MAE - mae $R1, $R3, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MAEB (1808) - SYSTEMZ_INS_MAEB - maeb $R1, $R3, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MAEBR (1809) - SYSTEMZ_INS_MAEBR - maebr $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MAER (1810) - SYSTEMZ_INS_MAER - maer $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MAY (1811) - SYSTEMZ_INS_MAY - may $R1, $R3, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MAYH (1812) - SYSTEMZ_INS_MAYH - mayh $R1, $R3, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MAYHR (1813) - SYSTEMZ_INS_MAYHR - mayhr $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MAYL (1814) - SYSTEMZ_INS_MAYL - mayl $R1, $R3, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MAYLR (1815) - SYSTEMZ_INS_MAYLR - maylr $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MAYR (1816) - SYSTEMZ_INS_MAYR - mayr $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MC (1817) - SYSTEMZ_INS_MC - mc $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_MD (1818) - SYSTEMZ_INS_MD - md $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MDB (1819) - SYSTEMZ_INS_MDB - mdb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MDBR (1820) - SYSTEMZ_INS_MDBR - mdbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MDE (1821) - SYSTEMZ_INS_MDE - mde $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MDEB (1822) - SYSTEMZ_INS_MDEB - mdeb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MDEBR (1823) - SYSTEMZ_INS_MDEBR - mdebr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MDER (1824) - SYSTEMZ_INS_MDER - mder $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MDR (1825) - SYSTEMZ_INS_MDR - mdr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MDTR (1826) - SYSTEMZ_INS_MDTR - mdtr $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_MDTRA (1827) - SYSTEMZ_INS_MDTRA - mdtra $R1, $R2, $R3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_ME (1828) - SYSTEMZ_INS_ME - me $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MEE (1829) - SYSTEMZ_INS_MEE - mee $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MEEB (1830) - SYSTEMZ_INS_MEEB - meeb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MEEBR (1831) - SYSTEMZ_INS_MEEBR - meebr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MEER (1832) - SYSTEMZ_INS_MEER - meer $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MER (1833) - SYSTEMZ_INS_MER - mer $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MFY (1834) - SYSTEMZ_INS_MFY - mfy $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MG (1835) - SYSTEMZ_INS_MG - mg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MGH (1836) - SYSTEMZ_INS_MGH - mgh $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MGHI (1837) - SYSTEMZ_INS_MGHI - mghi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_MGRK (1838) - SYSTEMZ_INS_MGRK - mgrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_MH (1839) - SYSTEMZ_INS_MH - mh $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MHI (1840) - SYSTEMZ_INS_MHI - mhi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_MHY (1841) - SYSTEMZ_INS_MHY - mhy $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_ML (1842) - SYSTEMZ_INS_ML - ml $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MLG (1843) - SYSTEMZ_INS_MLG - mlg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MLGR (1844) - SYSTEMZ_INS_MLGR - mlgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MLR (1845) - SYSTEMZ_INS_MLR - mlr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MP (1846) - SYSTEMZ_INS_MP - mp $BDL1, $BDL2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len4imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - len4imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_MR (1847) - SYSTEMZ_INS_MR - mr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MS (1848) - SYSTEMZ_INS_MS - ms $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MSC (1849) - SYSTEMZ_INS_MSC - msc $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MSCH (1850) - SYSTEMZ_INS_MSCH - msch $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_MSD (1851) - SYSTEMZ_INS_MSD - msd $R1, $R3, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MSDB (1852) - SYSTEMZ_INS_MSDB - msdb $R1, $R3, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MSDBR (1853) - SYSTEMZ_INS_MSDBR - msdbr $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MSDR (1854) - SYSTEMZ_INS_MSDR - msdr $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MSE (1855) - SYSTEMZ_INS_MSE - mse $R1, $R3, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MSEB (1856) - SYSTEMZ_INS_MSEB - mseb $R1, $R3, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MSEBR (1857) - SYSTEMZ_INS_MSEBR - msebr $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MSER (1858) - SYSTEMZ_INS_MSER - mser $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MSFI (1859) - SYSTEMZ_INS_MSFI - msfi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_MSG (1860) - SYSTEMZ_INS_MSG - msg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MSGC (1861) - SYSTEMZ_INS_MSGC - msgc $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MSGF (1862) - SYSTEMZ_INS_MSGF - msgf $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MSGFI (1863) - SYSTEMZ_INS_MSGFI - msgfi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_MSGFR (1864) - SYSTEMZ_INS_MSGFR - msgfr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MSGR (1865) - SYSTEMZ_INS_MSGR - msgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MSGRKC (1866) - SYSTEMZ_INS_MSGRKC - msgrkc $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_MSR (1867) - SYSTEMZ_INS_MSR - msr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MSRKC (1868) - SYSTEMZ_INS_MSRKC - msrkc $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_MSTA (1869) - SYSTEMZ_INS_MSTA - msta $R1 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { 0 } +}}, +{ /* SYSTEMZ_MSY (1870) - SYSTEMZ_INS_MSY - msy $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MVC (1871) - SYSTEMZ_INS_MVC - mvc $BDL1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len8imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_MVCDK (1872) - SYSTEMZ_INS_MVCDK - mvcdk $BD1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_MVCIN (1873) - SYSTEMZ_INS_MVCIN - mvcin $BDL1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len8imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_MVCK (1874) - SYSTEMZ_INS_MVCK - mvck $RBD1, $BD2, $R3 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RBD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RBD1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RBD1 - GR64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_MVCL (1875) - SYSTEMZ_INS_MVCL - mvcl $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_MVCLE (1876) - SYSTEMZ_INS_MVCLE - mvcle $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R3src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_MVCLU (1877) - SYSTEMZ_INS_MVCLU - mvclu $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R3src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_MVCOS (1878) - SYSTEMZ_INS_MVCOS - mvcos $BD1, $BD2, $R3 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_MVCP (1879) - SYSTEMZ_INS_MVCP - mvcp $RBD1, $BD2, $R3 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RBD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RBD1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RBD1 - GR64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_MVCRL (1880) - SYSTEMZ_INS_MVCRL - mvcrl $BD1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_MVCS (1881) - SYSTEMZ_INS_MVCS - mvcs $RBD1, $BD2, $R3 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RBD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RBD1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RBD1 - GR64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_MVCSK (1882) - SYSTEMZ_INS_MVCSK - mvcsk $BD1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_MVGHI (1883) - SYSTEMZ_INS_MVGHI - mvghi $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_MVHHI (1884) - SYSTEMZ_INS_MVHHI - mvhhi $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_MVHI (1885) - SYSTEMZ_INS_MVHI - mvhi $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_MVI (1886) - SYSTEMZ_INS_MVI - mvi $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_MVIY (1887) - SYSTEMZ_INS_MVIY - mviy $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp20imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_MVN (1888) - SYSTEMZ_INS_MVN - mvn $BDL1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len8imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_MVO (1889) - SYSTEMZ_INS_MVO - mvo $BDL1, $BDL2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len4imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - len4imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_MVPG (1890) - SYSTEMZ_INS_MVPG - mvpg $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MVST (1891) - SYSTEMZ_INS_MVST - mvst $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_MVZ (1892) - SYSTEMZ_INS_MVZ - mvz $BDL1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len8imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_MXBR (1893) - SYSTEMZ_INS_MXBR - mxbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MXD (1894) - SYSTEMZ_INS_MXD - mxd $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MXDB (1895) - SYSTEMZ_INS_MXDB - mxdb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MXDBR (1896) - SYSTEMZ_INS_MXDBR - mxdbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MXDR (1897) - SYSTEMZ_INS_MXDR - mxdr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MXR (1898) - SYSTEMZ_INS_MXR - mxr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MXTR (1899) - SYSTEMZ_INS_MXTR - mxtr $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_MXTRA (1900) - SYSTEMZ_INS_MXTRA - mxtra $R1, $R2, $R3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_MY (1901) - SYSTEMZ_INS_MY - my $R1, $R3, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MYH (1902) - SYSTEMZ_INS_MYH - myh $R1, $R3, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MYHR (1903) - SYSTEMZ_INS_MYHR - myhr $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MYL (1904) - SYSTEMZ_INS_MYL - myl $R1, $R3, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_MYLR (1905) - SYSTEMZ_INS_MYLR - mylr $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_MYR (1906) - SYSTEMZ_INS_MYR - myr $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_N (1907) - SYSTEMZ_INS_N - n $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_NC (1908) - SYSTEMZ_INS_NC - nc $BDL1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len8imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_NCGRK (1909) - SYSTEMZ_INS_NCGRK - ncgrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_NCRK (1910) - SYSTEMZ_INS_NCRK - ncrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_NG (1911) - SYSTEMZ_INS_NG - ng $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_NGR (1912) - SYSTEMZ_INS_NGR - ngr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_NGRK (1913) - SYSTEMZ_INS_NGRK - ngrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_NI (1914) - SYSTEMZ_INS_NI - ni $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_NIAI (1915) - SYSTEMZ_INS_NIAI - niai $I1, $I2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_NIHF (1916) - SYSTEMZ_INS_NIHF - nihf $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_NIHH (1917) - SYSTEMZ_INS_NIHH - nihh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_NIHL (1918) - SYSTEMZ_INS_NIHL - nihl $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_NILF (1919) - SYSTEMZ_INS_NILF - nilf $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_NILH (1920) - SYSTEMZ_INS_NILH - nilh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_NILL (1921) - SYSTEMZ_INS_NILL - nill $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_NIY (1922) - SYSTEMZ_INS_NIY - niy $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp20imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_NNGRK (1923) - SYSTEMZ_INS_NNGRK - nngrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_NNPA (1924) - SYSTEMZ_INS_NNPA - nnpa */ +{ + { 0 } +}}, +{ /* SYSTEMZ_NNRK (1925) - SYSTEMZ_INS_NNRK - nnrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_NOGRK (1926) - SYSTEMZ_INS_NOGRK - nogrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_NOP_bare (1927) - SYSTEMZ_INS_NOP - nop */ +{ + { 0 } +}}, +{ /* SYSTEMZ_NORK (1928) - SYSTEMZ_INS_NORK - nork $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_NR (1929) - SYSTEMZ_INS_NR - nr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_NRK (1930) - SYSTEMZ_INS_NRK - nrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_NTSTG (1931) - SYSTEMZ_INS_NTSTG - ntstg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_NXGRK (1932) - SYSTEMZ_INS_NXGRK - nxgrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_NXRK (1933) - SYSTEMZ_INS_NXRK - nxrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_NY (1934) - SYSTEMZ_INS_NY - ny $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_O (1935) - SYSTEMZ_INS_O - o $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_OC (1936) - SYSTEMZ_INS_OC - oc $BDL1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len8imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_OCGRK (1937) - SYSTEMZ_INS_OCGRK - ocgrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_OCRK (1938) - SYSTEMZ_INS_OCRK - ocrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_OG (1939) - SYSTEMZ_INS_OG - og $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_OGR (1940) - SYSTEMZ_INS_OGR - ogr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_OGRK (1941) - SYSTEMZ_INS_OGRK - ogrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_OI (1942) - SYSTEMZ_INS_OI - oi $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_OIHF (1943) - SYSTEMZ_INS_OIHF - oihf $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_OIHH (1944) - SYSTEMZ_INS_OIHH - oihh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_OIHL (1945) - SYSTEMZ_INS_OIHL - oihl $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_OILF (1946) - SYSTEMZ_INS_OILF - oilf $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_OILH (1947) - SYSTEMZ_INS_OILH - oilh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_OILL (1948) - SYSTEMZ_INS_OILL - oill $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_OIY (1949) - SYSTEMZ_INS_OIY - oiy $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp20imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_OR (1950) - SYSTEMZ_INS_OR - or $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_ORK (1951) - SYSTEMZ_INS_ORK - ork $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_OY (1952) - SYSTEMZ_INS_OY - oy $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_PACK (1953) - SYSTEMZ_INS_PACK - pack $BDL1, $BDL2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len4imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - len4imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_PALB (1954) - SYSTEMZ_INS_PALB - palb */ +{ + { 0 } +}}, +{ /* SYSTEMZ_PC (1955) - SYSTEMZ_INS_PC - pc $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_PCC (1956) - SYSTEMZ_INS_PCC - pcc */ +{ + { 0 } +}}, +{ /* SYSTEMZ_PCKMO (1957) - SYSTEMZ_INS_PCKMO - pckmo */ +{ + { 0 } +}}, +{ /* SYSTEMZ_PFD (1958) - SYSTEMZ_INS_PFD - pfd $M1, $XBD2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_PFDRL (1959) - SYSTEMZ_INS_PFDRL - pfdrl $M1, $RI2 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_PFMF (1960) - SYSTEMZ_INS_PFMF - pfmf $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_PFPO (1961) - SYSTEMZ_INS_PFPO - pfpo */ +{ + { 0 } +}}, +{ /* SYSTEMZ_PGIN (1962) - SYSTEMZ_INS_PGIN - pgin $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_PGOUT (1963) - SYSTEMZ_INS_PGOUT - pgout $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_PKA (1964) - SYSTEMZ_INS_PKA - pka $BD1, $BDL2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - len8imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_PKU (1965) - SYSTEMZ_INS_PKU - pku $BD1, $BDL2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - len8imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_PLO (1966) - SYSTEMZ_INS_PLO - plo $R1, $BD2, $R3, $BD4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD4 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_POPCNT (1967) - SYSTEMZ_INS_POPCNT - popcnt $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_POPCNTOpt (1968) - SYSTEMZ_INS_POPCNT - popcnt $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_PPA (1969) - SYSTEMZ_INS_PPA - ppa $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_PPNO (1970) - SYSTEMZ_INS_PPNO - ppno $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_PR (1971) - SYSTEMZ_INS_PR - pr */ +{ + { 0 } +}}, +{ /* SYSTEMZ_PRNO (1972) - SYSTEMZ_INS_PRNO - prno $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_PT (1973) - SYSTEMZ_INS_PT - pt $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_PTF (1974) - SYSTEMZ_INS_PTF - ptf $R1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { 0 } +}}, +{ /* SYSTEMZ_PTFF (1975) - SYSTEMZ_INS_PTFF - ptff */ +{ + { 0 } +}}, +{ /* SYSTEMZ_PTI (1976) - SYSTEMZ_INS_PTI - pti $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_PTLB (1977) - SYSTEMZ_INS_PTLB - ptlb */ +{ + { 0 } +}}, +{ /* SYSTEMZ_QADTR (1978) - SYSTEMZ_INS_QADTR - qadtr $R1, $R3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_QAXTR (1979) - SYSTEMZ_INS_QAXTR - qaxtr $R1, $R3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_QCTRI (1980) - SYSTEMZ_INS_QCTRI - qctri $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_QPACI (1981) - SYSTEMZ_INS_QPACI - qpaci $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_QSI (1982) - SYSTEMZ_INS_QSI - qsi $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_RCHP (1983) - SYSTEMZ_INS_RCHP - rchp */ +{ + { 0 } +}}, +{ /* SYSTEMZ_RDP (1984) - SYSTEMZ_INS_RDP - rdp $R1, $R3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_RDPOpt (1985) - SYSTEMZ_INS_RDP - rdp $R1, $R3, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_RISBG (1986) - SYSTEMZ_INS_RISBG - risbg $R1, $R2, $I3, $I4, $I5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I5 */ + { 0 } +}}, +{{{ /* SYSTEMZ_RISBG32 (1987) - SYSTEMZ_INS_INVALID - risbg $R1, $R2, $I3, $I4, $I5 */ + 0 +}}}, +{ /* SYSTEMZ_RISBGN (1988) - SYSTEMZ_INS_RISBGN - risbgn $R1, $R2, $I3, $I4, $I5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I5 */ + { 0 } +}}, +{ /* SYSTEMZ_RISBHG (1989) - SYSTEMZ_INS_RISBHG - risbhg $R1, $R2, $I3, $I4, $I5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I5 */ + { 0 } +}}, +{ /* SYSTEMZ_RISBLG (1990) - SYSTEMZ_INS_RISBLG - risblg $R1, $R2, $I3, $I4, $I5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I5 */ + { 0 } +}}, +{ /* SYSTEMZ_RLL (1991) - SYSTEMZ_INS_RLL - rll $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_RLLG (1992) - SYSTEMZ_INS_RLLG - rllg $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_RNSBG (1993) - SYSTEMZ_INS_RNSBG - rnsbg $R1, $R2, $I3, $I4, $I5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I5 */ + { 0 } +}}, +{ /* SYSTEMZ_ROSBG (1994) - SYSTEMZ_INS_ROSBG - rosbg $R1, $R2, $I3, $I4, $I5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I5 */ + { 0 } +}}, +{ /* SYSTEMZ_RP (1995) - SYSTEMZ_INS_RP - rp $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_RRBE (1996) - SYSTEMZ_INS_RRBE - rrbe $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_RRBM (1997) - SYSTEMZ_INS_RRBM - rrbm $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_RRDTR (1998) - SYSTEMZ_INS_RRDTR - rrdtr $R1, $R3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_RRXTR (1999) - SYSTEMZ_INS_RRXTR - rrxtr $R1, $R3, $R2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_RSCH (2000) - SYSTEMZ_INS_RSCH - rsch */ +{ + { 0 } +}}, +{ /* SYSTEMZ_RXSBG (2001) - SYSTEMZ_INS_RXSBG - rxsbg $R1, $R2, $I3, $I4, $I5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I5 */ + { 0 } +}}, +{ /* SYSTEMZ_S (2002) - SYSTEMZ_INS_S - s $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SAC (2003) - SYSTEMZ_INS_SAC - sac $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_SACF (2004) - SYSTEMZ_INS_SACF - sacf $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_SAL (2005) - SYSTEMZ_INS_SAL - sal */ +{ + { 0 } +}}, +{ /* SYSTEMZ_SAM24 (2006) - SYSTEMZ_INS_SAM24 - sam24 */ +{ + { 0 } +}}, +{ /* SYSTEMZ_SAM31 (2007) - SYSTEMZ_INS_SAM31 - sam31 */ +{ + { 0 } +}}, +{ /* SYSTEMZ_SAM64 (2008) - SYSTEMZ_INS_SAM64 - sam64 */ +{ + { 0 } +}}, +{ /* SYSTEMZ_SAR (2009) - SYSTEMZ_INS_SAR - sar $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SCCTR (2010) - SYSTEMZ_INS_SCCTR - scctr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SCHM (2011) - SYSTEMZ_INS_SCHM - schm */ +{ + { 0 } +}}, +{ /* SYSTEMZ_SCK (2012) - SYSTEMZ_INS_SCK - sck $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_SCKC (2013) - SYSTEMZ_INS_SCKC - sckc $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_SCKPF (2014) - SYSTEMZ_INS_SCKPF - sckpf */ +{ + { 0 } +}}, +{ /* SYSTEMZ_SD (2015) - SYSTEMZ_INS_SD - sd $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SDB (2016) - SYSTEMZ_INS_SDB - sdb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SDBR (2017) - SYSTEMZ_INS_SDBR - sdbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SDR (2018) - SYSTEMZ_INS_SDR - sdr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SDTR (2019) - SYSTEMZ_INS_SDTR - sdtr $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_SDTRA (2020) - SYSTEMZ_INS_SDTRA - sdtra $R1, $R2, $R3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_SE (2021) - SYSTEMZ_INS_SE - se $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SEB (2022) - SYSTEMZ_INS_SEB - seb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SEBR (2023) - SYSTEMZ_INS_SEBR - sebr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_SELFHR (2024) - SYSTEMZ_INS_INVALID - selfhr$M4 $R1, $R2, $R3 */ + 0 +}}}, +{ /* SYSTEMZ_SELFHRAsm (2025) - SYSTEMZ_INS_SELFHR - selfhr $R1, $R2, $R3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmE (2026) - SYSTEMZ_INS_SELFHRE - selfhre $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmH (2027) - SYSTEMZ_INS_SELFHRH - selfhrh $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmHE (2028) - SYSTEMZ_INS_SELFHRHE - selfhrhe $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmL (2029) - SYSTEMZ_INS_SELFHRL - selfhrl $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmLE (2030) - SYSTEMZ_INS_SELFHRLE - selfhrle $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmLH (2031) - SYSTEMZ_INS_SELFHRLH - selfhrlh $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmM (2032) - SYSTEMZ_INS_SELFHRM - selfhrm $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmNE (2033) - SYSTEMZ_INS_SELFHRNE - selfhrne $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmNH (2034) - SYSTEMZ_INS_SELFHRNH - selfhrnh $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmNHE (2035) - SYSTEMZ_INS_SELFHRNHE - selfhrnhe $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmNL (2036) - SYSTEMZ_INS_SELFHRNL - selfhrnl $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmNLE (2037) - SYSTEMZ_INS_SELFHRNLE - selfhrnle $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmNLH (2038) - SYSTEMZ_INS_SELFHRNLH - selfhrnlh $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmNM (2039) - SYSTEMZ_INS_SELFHRNM - selfhrnm $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmNO (2040) - SYSTEMZ_INS_SELFHRNO - selfhrno $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmNP (2041) - SYSTEMZ_INS_SELFHRNP - selfhrnp $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmNZ (2042) - SYSTEMZ_INS_SELFHRNZ - selfhrnz $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmO (2043) - SYSTEMZ_INS_SELFHRO - selfhro $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmP (2044) - SYSTEMZ_INS_SELFHRP - selfhrp $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELFHRAsmZ (2045) - SYSTEMZ_INS_SELFHRZ - selfhrz $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_SELGR (2046) - SYSTEMZ_INS_INVALID - selgr$M4 $R1, $R2, $R3 */ + 0 +}}}, +{ /* SYSTEMZ_SELGRAsm (2047) - SYSTEMZ_INS_SELGR - selgr $R1, $R2, $R3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmE (2048) - SYSTEMZ_INS_SELGRE - selgre $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmH (2049) - SYSTEMZ_INS_SELGRH - selgrh $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmHE (2050) - SYSTEMZ_INS_SELGRHE - selgrhe $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmL (2051) - SYSTEMZ_INS_SELGRL - selgrl $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmLE (2052) - SYSTEMZ_INS_SELGRLE - selgrle $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmLH (2053) - SYSTEMZ_INS_SELGRLH - selgrlh $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmM (2054) - SYSTEMZ_INS_SELGRM - selgrm $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmNE (2055) - SYSTEMZ_INS_SELGRNE - selgrne $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmNH (2056) - SYSTEMZ_INS_SELGRNH - selgrnh $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmNHE (2057) - SYSTEMZ_INS_SELGRNHE - selgrnhe $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmNL (2058) - SYSTEMZ_INS_SELGRNL - selgrnl $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmNLE (2059) - SYSTEMZ_INS_SELGRNLE - selgrnle $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmNLH (2060) - SYSTEMZ_INS_SELGRNLH - selgrnlh $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmNM (2061) - SYSTEMZ_INS_SELGRNM - selgrnm $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmNO (2062) - SYSTEMZ_INS_SELGRNO - selgrno $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmNP (2063) - SYSTEMZ_INS_SELGRNP - selgrnp $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmNZ (2064) - SYSTEMZ_INS_SELGRNZ - selgrnz $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmO (2065) - SYSTEMZ_INS_SELGRO - selgro $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmP (2066) - SYSTEMZ_INS_SELGRP - selgrp $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELGRAsmZ (2067) - SYSTEMZ_INS_SELGRZ - selgrz $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_SELR (2068) - SYSTEMZ_INS_INVALID - selr$M4 $R1, $R2, $R3 */ + 0 +}}}, +{ /* SYSTEMZ_SELRAsm (2069) - SYSTEMZ_INS_SELR - selr $R1, $R2, $R3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmE (2070) - SYSTEMZ_INS_SELRE - selre $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmH (2071) - SYSTEMZ_INS_SELRH - selrh $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmHE (2072) - SYSTEMZ_INS_SELRHE - selrhe $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmL (2073) - SYSTEMZ_INS_SELRL - selrl $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmLE (2074) - SYSTEMZ_INS_SELRLE - selrle $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmLH (2075) - SYSTEMZ_INS_SELRLH - selrlh $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmM (2076) - SYSTEMZ_INS_SELRM - selrm $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmNE (2077) - SYSTEMZ_INS_SELRNE - selrne $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmNH (2078) - SYSTEMZ_INS_SELRNH - selrnh $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmNHE (2079) - SYSTEMZ_INS_SELRNHE - selrnhe $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmNL (2080) - SYSTEMZ_INS_SELRNL - selrnl $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmNLE (2081) - SYSTEMZ_INS_SELRNLE - selrnle $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmNLH (2082) - SYSTEMZ_INS_SELRNLH - selrnlh $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmNM (2083) - SYSTEMZ_INS_SELRNM - selrnm $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmNO (2084) - SYSTEMZ_INS_SELRNO - selrno $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmNP (2085) - SYSTEMZ_INS_SELRNP - selrnp $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmNZ (2086) - SYSTEMZ_INS_SELRNZ - selrnz $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmO (2087) - SYSTEMZ_INS_SELRO - selro $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmP (2088) - SYSTEMZ_INS_SELRP - selrp $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SELRAsmZ (2089) - SYSTEMZ_INS_SELRZ - selrz $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SER (2090) - SYSTEMZ_INS_SER - ser $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SFASR (2091) - SYSTEMZ_INS_SFASR - sfasr $R1 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { 0 } +}}, +{ /* SYSTEMZ_SFPC (2092) - SYSTEMZ_INS_SFPC - sfpc $R1 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { 0 } +}}, +{ /* SYSTEMZ_SG (2093) - SYSTEMZ_INS_SG - sg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SGF (2094) - SYSTEMZ_INS_SGF - sgf $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SGFR (2095) - SYSTEMZ_INS_SGFR - sgfr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SGH (2096) - SYSTEMZ_INS_SGH - sgh $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SGR (2097) - SYSTEMZ_INS_SGR - sgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SGRK (2098) - SYSTEMZ_INS_SGRK - sgrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_SH (2099) - SYSTEMZ_INS_SH - sh $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SHHHR (2100) - SYSTEMZ_INS_SHHHR - shhhr $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_SHHLR (2101) - SYSTEMZ_INS_SHHLR - shhlr $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_SHY (2102) - SYSTEMZ_INS_SHY - shy $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SIE (2103) - SYSTEMZ_INS_SIE - sie $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_SIGA (2104) - SYSTEMZ_INS_SIGA - siga $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_SIGP (2105) - SYSTEMZ_INS_SIGP - sigp $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_SL (2106) - SYSTEMZ_INS_SL - sl $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SLA (2107) - SYSTEMZ_INS_SLA - sla $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_SLAG (2108) - SYSTEMZ_INS_SLAG - slag $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_SLAK (2109) - SYSTEMZ_INS_SLAK - slak $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_SLB (2110) - SYSTEMZ_INS_SLB - slb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SLBG (2111) - SYSTEMZ_INS_SLBG - slbg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SLBGR (2112) - SYSTEMZ_INS_SLBGR - slbgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SLBR (2113) - SYSTEMZ_INS_SLBR - slbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SLDA (2114) - SYSTEMZ_INS_SLDA - slda $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_SLDL (2115) - SYSTEMZ_INS_SLDL - sldl $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_SLDT (2116) - SYSTEMZ_INS_SLDT - sldt $R1, $R3, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SLFI (2117) - SYSTEMZ_INS_SLFI - slfi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_SLG (2118) - SYSTEMZ_INS_SLG - slg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SLGF (2119) - SYSTEMZ_INS_SLGF - slgf $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SLGFI (2120) - SYSTEMZ_INS_SLGFI - slgfi $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_SLGFR (2121) - SYSTEMZ_INS_SLGFR - slgfr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SLGR (2122) - SYSTEMZ_INS_SLGR - slgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SLGRK (2123) - SYSTEMZ_INS_SLGRK - slgrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_SLHHHR (2124) - SYSTEMZ_INS_SLHHHR - slhhhr $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_SLHHLR (2125) - SYSTEMZ_INS_SLHHLR - slhhlr $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_SLL (2126) - SYSTEMZ_INS_SLL - sll $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_SLLG (2127) - SYSTEMZ_INS_SLLG - sllg $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_SLLK (2128) - SYSTEMZ_INS_SLLK - sllk $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_SLR (2129) - SYSTEMZ_INS_SLR - slr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SLRK (2130) - SYSTEMZ_INS_SLRK - slrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_SLXT (2131) - SYSTEMZ_INS_SLXT - slxt $R1, $R3, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SLY (2132) - SYSTEMZ_INS_SLY - sly $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SORTL (2133) - SYSTEMZ_INS_SORTL - sortl $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_SP (2134) - SYSTEMZ_INS_SP - sp $BDL1, $BDL2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len4imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - len4imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_SPCTR (2135) - SYSTEMZ_INS_SPCTR - spctr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SPKA (2136) - SYSTEMZ_INS_SPKA - spka $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_SPM (2137) - SYSTEMZ_INS_SPM - spm $R1 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { 0 } +}}, +{ /* SYSTEMZ_SPT (2138) - SYSTEMZ_INS_SPT - spt $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_SPX (2139) - SYSTEMZ_INS_SPX - spx $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_SQD (2140) - SYSTEMZ_INS_SQD - sqd $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SQDB (2141) - SYSTEMZ_INS_SQDB - sqdb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SQDBR (2142) - SYSTEMZ_INS_SQDBR - sqdbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SQDR (2143) - SYSTEMZ_INS_SQDR - sqdr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SQE (2144) - SYSTEMZ_INS_SQE - sqe $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SQEB (2145) - SYSTEMZ_INS_SQEB - sqeb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SQEBR (2146) - SYSTEMZ_INS_SQEBR - sqebr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SQER (2147) - SYSTEMZ_INS_SQER - sqer $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SQXBR (2148) - SYSTEMZ_INS_SQXBR - sqxbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SQXR (2149) - SYSTEMZ_INS_SQXR - sqxr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SR (2150) - SYSTEMZ_INS_SR - sr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SRA (2151) - SYSTEMZ_INS_SRA - sra $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_SRAG (2152) - SYSTEMZ_INS_SRAG - srag $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_SRAK (2153) - SYSTEMZ_INS_SRAK - srak $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_SRDA (2154) - SYSTEMZ_INS_SRDA - srda $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_SRDL (2155) - SYSTEMZ_INS_SRDL - srdl $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_SRDT (2156) - SYSTEMZ_INS_SRDT - srdt $R1, $R3, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SRK (2157) - SYSTEMZ_INS_SRK - srk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_SRL (2158) - SYSTEMZ_INS_SRL - srl $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_SRLG (2159) - SYSTEMZ_INS_SRLG - srlg $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_SRLK (2160) - SYSTEMZ_INS_SRLK - srlk $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_SRNM (2161) - SYSTEMZ_INS_SRNM - srnm $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_SRNMB (2162) - SYSTEMZ_INS_SRNMB - srnmb $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_SRNMT (2163) - SYSTEMZ_INS_SRNMT - srnmt $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_SRP (2164) - SYSTEMZ_INS_SRP - srp $BDL1, $BD2, $I3 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len4imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { 0 } +}}, +{ /* SYSTEMZ_SRST (2165) - SYSTEMZ_INS_SRST - srst $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_SRSTU (2166) - SYSTEMZ_INS_SRSTU - srstu $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_SRXT (2167) - SYSTEMZ_INS_SRXT - srxt $R1, $R3, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SSAIR (2168) - SYSTEMZ_INS_SSAIR - ssair $R1 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { 0 } +}}, +{ /* SYSTEMZ_SSAR (2169) - SYSTEMZ_INS_SSAR - ssar $R1 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { 0 } +}}, +{ /* SYSTEMZ_SSCH (2170) - SYSTEMZ_INS_SSCH - ssch $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_SSKE (2171) - SYSTEMZ_INS_SSKE - sske $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_SSKEOpt (2172) - SYSTEMZ_INS_SSKE - sske $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SSM (2173) - SYSTEMZ_INS_SSM - ssm $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_ST (2174) - SYSTEMZ_INS_ST - st $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_STAM (2175) - SYSTEMZ_INS_STAM - stam $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STAMY (2176) - SYSTEMZ_INS_STAMY - stamy $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STAP (2177) - SYSTEMZ_INS_STAP - stap $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STBEAR (2178) - SYSTEMZ_INS_STBEAR - stbear $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STC (2179) - SYSTEMZ_INS_STC - stc $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_STCH (2180) - SYSTEMZ_INS_STCH - stch $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_STCK (2181) - SYSTEMZ_INS_STCK - stck $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STCKC (2182) - SYSTEMZ_INS_STCKC - stckc $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STCKE (2183) - SYSTEMZ_INS_STCKE - stcke $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STCKF (2184) - SYSTEMZ_INS_STCKF - stckf $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STCM (2185) - SYSTEMZ_INS_STCM - stcm $R1, $M3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STCMH (2186) - SYSTEMZ_INS_STCMH - stcmh $R1, $M3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STCMY (2187) - SYSTEMZ_INS_STCMY - stcmy $R1, $M3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STCPS (2188) - SYSTEMZ_INS_STCPS - stcps $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STCRW (2189) - SYSTEMZ_INS_STCRW - stcrw $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STCTG (2190) - SYSTEMZ_INS_STCTG - stctg $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STCTL (2191) - SYSTEMZ_INS_STCTL - stctl $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STCY (2192) - SYSTEMZ_INS_STCY - stcy $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_STD (2193) - SYSTEMZ_INS_STD - std $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_STDY (2194) - SYSTEMZ_INS_STDY - stdy $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_STE (2195) - SYSTEMZ_INS_STE - ste $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_STEY (2196) - SYSTEMZ_INS_STEY - stey $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_STFH (2197) - SYSTEMZ_INS_STFH - stfh $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_STFL (2198) - SYSTEMZ_INS_STFL - stfl $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STFLE (2199) - SYSTEMZ_INS_STFLE - stfle $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STFPC (2200) - SYSTEMZ_INS_STFPC - stfpc $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STG (2201) - SYSTEMZ_INS_STG - stg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_STGRL (2202) - SYSTEMZ_INS_STGRL - stgrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_STGSC (2203) - SYSTEMZ_INS_STGSC - stgsc $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_STH (2204) - SYSTEMZ_INS_STH - sth $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_STHH (2205) - SYSTEMZ_INS_STHH - sthh $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_STHRL (2206) - SYSTEMZ_INS_STHRL - sthrl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_STHY (2207) - SYSTEMZ_INS_STHY - sthy $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_STIDP (2208) - SYSTEMZ_INS_STIDP - stidp $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STM (2209) - SYSTEMZ_INS_STM - stm $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STMG (2210) - SYSTEMZ_INS_STMG - stmg $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STMH (2211) - SYSTEMZ_INS_STMH - stmh $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STMY (2212) - SYSTEMZ_INS_STMY - stmy $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STNSM (2213) - SYSTEMZ_INS_STNSM - stnsm $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{{{ /* SYSTEMZ_STOC (2214) - SYSTEMZ_INS_INVALID - stoc$M3 $R1, $BD2 */ + 0 +}}}, +{ /* SYSTEMZ_STOCAsm (2215) - SYSTEMZ_INS_STOC - stoc $R1, $BD2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmE (2216) - SYSTEMZ_INS_STOCE - stoce $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmH (2217) - SYSTEMZ_INS_STOCH - stoch $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmHE (2218) - SYSTEMZ_INS_STOCHE - stoche $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmL (2219) - SYSTEMZ_INS_STOCL - stocl $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmLE (2220) - SYSTEMZ_INS_STOCLE - stocle $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmLH (2221) - SYSTEMZ_INS_STOCLH - stoclh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmM (2222) - SYSTEMZ_INS_STOCM - stocm $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmNE (2223) - SYSTEMZ_INS_STOCNE - stocne $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmNH (2224) - SYSTEMZ_INS_STOCNH - stocnh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmNHE (2225) - SYSTEMZ_INS_STOCNHE - stocnhe $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmNL (2226) - SYSTEMZ_INS_STOCNL - stocnl $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmNLE (2227) - SYSTEMZ_INS_STOCNLE - stocnle $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmNLH (2228) - SYSTEMZ_INS_STOCNLH - stocnlh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmNM (2229) - SYSTEMZ_INS_STOCNM - stocnm $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmNO (2230) - SYSTEMZ_INS_STOCNO - stocno $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmNP (2231) - SYSTEMZ_INS_STOCNP - stocnp $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmNZ (2232) - SYSTEMZ_INS_STOCNZ - stocnz $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmO (2233) - SYSTEMZ_INS_STOCO - stoco $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmP (2234) - SYSTEMZ_INS_STOCP - stocp $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCAsmZ (2235) - SYSTEMZ_INS_STOCZ - stocz $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{{{ /* SYSTEMZ_STOCFH (2236) - SYSTEMZ_INS_INVALID - stocfh$M3 $R1, $BD2 */ + 0 +}}}, +{ /* SYSTEMZ_STOCFHAsm (2237) - SYSTEMZ_INS_STOCFH - stocfh $R1, $BD2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmE (2238) - SYSTEMZ_INS_STOCFHE - stocfhe $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmH (2239) - SYSTEMZ_INS_STOCFHH - stocfhh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmHE (2240) - SYSTEMZ_INS_STOCFHHE - stocfhhe $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmL (2241) - SYSTEMZ_INS_STOCFHL - stocfhl $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmLE (2242) - SYSTEMZ_INS_STOCFHLE - stocfhle $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmLH (2243) - SYSTEMZ_INS_STOCFHLH - stocfhlh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmM (2244) - SYSTEMZ_INS_STOCFHM - stocfhm $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmNE (2245) - SYSTEMZ_INS_STOCFHNE - stocfhne $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmNH (2246) - SYSTEMZ_INS_STOCFHNH - stocfhnh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmNHE (2247) - SYSTEMZ_INS_STOCFHNHE - stocfhnhe $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmNL (2248) - SYSTEMZ_INS_STOCFHNL - stocfhnl $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmNLE (2249) - SYSTEMZ_INS_STOCFHNLE - stocfhnle $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmNLH (2250) - SYSTEMZ_INS_STOCFHNLH - stocfhnlh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmNM (2251) - SYSTEMZ_INS_STOCFHNM - stocfhnm $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmNO (2252) - SYSTEMZ_INS_STOCFHNO - stocfhno $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmNP (2253) - SYSTEMZ_INS_STOCFHNP - stocfhnp $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmNZ (2254) - SYSTEMZ_INS_STOCFHNZ - stocfhnz $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmO (2255) - SYSTEMZ_INS_STOCFHO - stocfho $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmP (2256) - SYSTEMZ_INS_STOCFHP - stocfhp $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCFHAsmZ (2257) - SYSTEMZ_INS_STOCFHZ - stocfhz $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{{{ /* SYSTEMZ_STOCG (2258) - SYSTEMZ_INS_INVALID - stocg$M3 $R1, $BD2 */ + 0 +}}}, +{ /* SYSTEMZ_STOCGAsm (2259) - SYSTEMZ_INS_STOCG - stocg $R1, $BD2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmE (2260) - SYSTEMZ_INS_STOCGE - stocge $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmH (2261) - SYSTEMZ_INS_STOCGH - stocgh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmHE (2262) - SYSTEMZ_INS_STOCGHE - stocghe $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmL (2263) - SYSTEMZ_INS_STOCGL - stocgl $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmLE (2264) - SYSTEMZ_INS_STOCGLE - stocgle $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmLH (2265) - SYSTEMZ_INS_STOCGLH - stocglh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmM (2266) - SYSTEMZ_INS_STOCGM - stocgm $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmNE (2267) - SYSTEMZ_INS_STOCGNE - stocgne $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmNH (2268) - SYSTEMZ_INS_STOCGNH - stocgnh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmNHE (2269) - SYSTEMZ_INS_STOCGNHE - stocgnhe $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmNL (2270) - SYSTEMZ_INS_STOCGNL - stocgnl $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmNLE (2271) - SYSTEMZ_INS_STOCGNLE - stocgnle $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmNLH (2272) - SYSTEMZ_INS_STOCGNLH - stocgnlh $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmNM (2273) - SYSTEMZ_INS_STOCGNM - stocgnm $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmNO (2274) - SYSTEMZ_INS_STOCGNO - stocgno $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmNP (2275) - SYSTEMZ_INS_STOCGNP - stocgnp $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmNZ (2276) - SYSTEMZ_INS_STOCGNZ - stocgnz $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmO (2277) - SYSTEMZ_INS_STOCGO - stocgo $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmP (2278) - SYSTEMZ_INS_STOCGP - stocgp $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOCGAsmZ (2279) - SYSTEMZ_INS_STOCGZ - stocgz $R1, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STOSM (2280) - SYSTEMZ_INS_STOSM - stosm $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_STPQ (2281) - SYSTEMZ_INS_STPQ - stpq $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_STPT (2282) - SYSTEMZ_INS_STPT - stpt $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STPX (2283) - SYSTEMZ_INS_STPX - stpx $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STRAG (2284) - SYSTEMZ_INS_STRAG - strag $BD1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STRL (2285) - SYSTEMZ_INS_STRL - strl $R1, $RI2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* RI2 - pcrel32 */ + { 0 } +}}, +{ /* SYSTEMZ_STRV (2286) - SYSTEMZ_INS_STRV - strv $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_STRVG (2287) - SYSTEMZ_INS_STRVG - strvg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_STRVH (2288) - SYSTEMZ_INS_STRVH - strvh $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_STSCH (2289) - SYSTEMZ_INS_STSCH - stsch $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STSI (2290) - SYSTEMZ_INS_STSI - stsi $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_STURA (2291) - SYSTEMZ_INS_STURA - stura $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_STURG (2292) - SYSTEMZ_INS_STURG - sturg $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_STY (2293) - SYSTEMZ_INS_STY - sty $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SU (2294) - SYSTEMZ_INS_SU - su $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SUR (2295) - SYSTEMZ_INS_SUR - sur $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SVC (2296) - SYSTEMZ_INS_SVC - svc $I1 */ +{ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I1 */ + { 0 } +}}, +{ /* SYSTEMZ_SW (2297) - SYSTEMZ_INS_SW - sw $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_SWR (2298) - SYSTEMZ_INS_SWR - swr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SXBR (2299) - SYSTEMZ_INS_SXBR - sxbr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SXR (2300) - SYSTEMZ_INS_SXR - sxr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_SXTR (2301) - SYSTEMZ_INS_SXTR - sxtr $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_SXTRA (2302) - SYSTEMZ_INS_SXTRA - sxtra $R1, $R2, $R3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_SY (2303) - SYSTEMZ_INS_SY - sy $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_TABORT (2304) - SYSTEMZ_INS_TABORT - tabort $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_TAM (2305) - SYSTEMZ_INS_TAM - tam */ +{ + { 0 } +}}, +{ /* SYSTEMZ_TAR (2306) - SYSTEMZ_INS_TAR - tar $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_TB (2307) - SYSTEMZ_INS_TB - tb $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_TBDR (2308) - SYSTEMZ_INS_TBDR - tbdr $R1, $M3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_TBEDR (2309) - SYSTEMZ_INS_TBEDR - tbedr $R1, $M3, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_TBEGIN (2310) - SYSTEMZ_INS_TBEGIN - tbegin $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_TBEGINC (2311) - SYSTEMZ_INS_TBEGINC - tbeginc $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_TCDB (2312) - SYSTEMZ_INS_TCDB - tcdb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_TCEB (2313) - SYSTEMZ_INS_TCEB - tceb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_TCXB (2314) - SYSTEMZ_INS_TCXB - tcxb $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_TDCDT (2315) - SYSTEMZ_INS_TDCDT - tdcdt $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_TDCET (2316) - SYSTEMZ_INS_TDCET - tdcet $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_TDCXT (2317) - SYSTEMZ_INS_TDCXT - tdcxt $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_TDGDT (2318) - SYSTEMZ_INS_TDGDT - tdgdt $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_TDGET (2319) - SYSTEMZ_INS_TDGET - tdget $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_TDGXT (2320) - SYSTEMZ_INS_TDGXT - tdgxt $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_TEND (2321) - SYSTEMZ_INS_TEND - tend */ +{ + { 0 } +}}, +{ /* SYSTEMZ_THDER (2322) - SYSTEMZ_INS_THDER - thder $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_THDR (2323) - SYSTEMZ_INS_THDR - thdr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_TM (2324) - SYSTEMZ_INS_TM - tm $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_TMHH (2325) - SYSTEMZ_INS_TMHH - tmhh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_TMHL (2326) - SYSTEMZ_INS_TMHL - tmhl $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_TMLH (2327) - SYSTEMZ_INS_TMLH - tmlh $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_TMLL (2328) - SYSTEMZ_INS_TMLL - tmll $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_TMY (2329) - SYSTEMZ_INS_TMY - tmy $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp20imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_TP (2330) - SYSTEMZ_INS_TP - tp $BDL1 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len4imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_TPI (2331) - SYSTEMZ_INS_TPI - tpi $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_TPROT (2332) - SYSTEMZ_INS_TPROT - tprot $BD1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_TR (2333) - SYSTEMZ_INS_TR - tr $BDL1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len8imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_TRACE (2334) - SYSTEMZ_INS_TRACE - trace $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_TRACG (2335) - SYSTEMZ_INS_TRACG - tracg $R1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp20imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_TRAP2 (2336) - SYSTEMZ_INS_TRAP2 - trap2 */ +{ + { 0 } +}}, +{ /* SYSTEMZ_TRAP4 (2337) - SYSTEMZ_INS_TRAP4 - trap4 $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_TRE (2338) - SYSTEMZ_INS_TRE - tre $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_TROO (2339) - SYSTEMZ_INS_TROO - troo $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_TROOOpt (2340) - SYSTEMZ_INS_TROO - troo $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_TROT (2341) - SYSTEMZ_INS_TROT - trot $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_TROTOpt (2342) - SYSTEMZ_INS_TROT - trot $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_TRT (2343) - SYSTEMZ_INS_TRT - trt $BDL1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len8imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_TRTE (2344) - SYSTEMZ_INS_TRTE - trte $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_TRTEOpt (2345) - SYSTEMZ_INS_TRTE - trte $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { 0 } +}}, +{ /* SYSTEMZ_TRTO (2346) - SYSTEMZ_INS_TRTO - trto $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_TRTOOpt (2347) - SYSTEMZ_INS_TRTO - trto $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_TRTR (2348) - SYSTEMZ_INS_TRTR - trtr $BDL1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len8imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_TRTRE (2349) - SYSTEMZ_INS_TRTRE - trtre $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_TRTREOpt (2350) - SYSTEMZ_INS_TRTRE - trtre $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { 0 } +}}, +{ /* SYSTEMZ_TRTT (2351) - SYSTEMZ_INS_TRTT - trtt $R1, $R2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_TRTTOpt (2352) - SYSTEMZ_INS_TRTT - trtt $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2src */ + { 0 } +}}, +{ /* SYSTEMZ_TS (2353) - SYSTEMZ_INS_TS - ts $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_TSCH (2354) - SYSTEMZ_INS_TSCH - tsch $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_UNPK (2355) - SYSTEMZ_INS_UNPK - unpk $BDL1, $BDL2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len4imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - len4imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_UNPKA (2356) - SYSTEMZ_INS_UNPKA - unpka $BDL1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len8imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_UNPKU (2357) - SYSTEMZ_INS_UNPKU - unpku $BDL1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len8imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_UPT (2358) - SYSTEMZ_INS_UPT - upt */ +{ + { 0 } +}}, +{ /* SYSTEMZ_VA (2359) - SYSTEMZ_INS_VA - va $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VAB (2360) - SYSTEMZ_INS_VAB - vab $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VAC (2361) - SYSTEMZ_INS_VAC - vac $V1, $V2, $V3, $V4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VACC (2362) - SYSTEMZ_INS_VACC - vacc $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VACCB (2363) - SYSTEMZ_INS_VACCB - vaccb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VACCC (2364) - SYSTEMZ_INS_VACCC - vaccc $V1, $V2, $V3, $V4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VACCCQ (2365) - SYSTEMZ_INS_VACCCQ - vacccq $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VACCF (2366) - SYSTEMZ_INS_VACCF - vaccf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VACCG (2367) - SYSTEMZ_INS_VACCG - vaccg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VACCH (2368) - SYSTEMZ_INS_VACCH - vacch $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VACCQ (2369) - SYSTEMZ_INS_VACCQ - vaccq $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VACQ (2370) - SYSTEMZ_INS_VACQ - vacq $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VAF (2371) - SYSTEMZ_INS_VAF - vaf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VAG (2372) - SYSTEMZ_INS_VAG - vag $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VAH (2373) - SYSTEMZ_INS_VAH - vah $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VAP (2374) - SYSTEMZ_INS_VAP - vap $V1, $V2, $V3, $I4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VAQ (2375) - SYSTEMZ_INS_VAQ - vaq $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VAVG (2376) - SYSTEMZ_INS_VAVG - vavg $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VAVGB (2377) - SYSTEMZ_INS_VAVGB - vavgb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VAVGF (2378) - SYSTEMZ_INS_VAVGF - vavgf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VAVGG (2379) - SYSTEMZ_INS_VAVGG - vavgg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VAVGH (2380) - SYSTEMZ_INS_VAVGH - vavgh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VAVGL (2381) - SYSTEMZ_INS_VAVGL - vavgl $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VAVGLB (2382) - SYSTEMZ_INS_VAVGLB - vavglb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VAVGLF (2383) - SYSTEMZ_INS_VAVGLF - vavglf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VAVGLG (2384) - SYSTEMZ_INS_VAVGLG - vavglg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VAVGLH (2385) - SYSTEMZ_INS_VAVGLH - vavglh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VBPERM (2386) - SYSTEMZ_INS_VBPERM - vbperm $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCDG (2387) - SYSTEMZ_INS_VCDG - vcdg $V1, $V2, $M3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCDGB (2388) - SYSTEMZ_INS_VCDGB - vcdgb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCDLG (2389) - SYSTEMZ_INS_VCDLG - vcdlg $V1, $V2, $M3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCDLGB (2390) - SYSTEMZ_INS_VCDLGB - vcdlgb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCEFB (2391) - SYSTEMZ_INS_VCEFB - vcefb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCELFB (2392) - SYSTEMZ_INS_VCELFB - vcelfb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCEQ (2393) - SYSTEMZ_INS_VCEQ - vceq $V1, $V2, $V3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCEQB (2394) - SYSTEMZ_INS_VCEQB - vceqb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCEQBS (2395) - SYSTEMZ_INS_VCEQBS - vceqbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCEQF (2396) - SYSTEMZ_INS_VCEQF - vceqf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCEQFS (2397) - SYSTEMZ_INS_VCEQFS - vceqfs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCEQG (2398) - SYSTEMZ_INS_VCEQG - vceqg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCEQGS (2399) - SYSTEMZ_INS_VCEQGS - vceqgs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCEQH (2400) - SYSTEMZ_INS_VCEQH - vceqh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCEQHS (2401) - SYSTEMZ_INS_VCEQHS - vceqhs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCFEB (2402) - SYSTEMZ_INS_VCFEB - vcfeb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCFN (2403) - SYSTEMZ_INS_VCFN - vcfn $V1, $V2, $M3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VCFPL (2404) - SYSTEMZ_INS_VCFPL - vcfpl $V1, $V2, $M3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCFPS (2405) - SYSTEMZ_INS_VCFPS - vcfps $V1, $V2, $M3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCGD (2406) - SYSTEMZ_INS_VCGD - vcgd $V1, $V2, $M3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCGDB (2407) - SYSTEMZ_INS_VCGDB - vcgdb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCH (2408) - SYSTEMZ_INS_VCH - vch $V1, $V2, $V3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCHB (2409) - SYSTEMZ_INS_VCHB - vchb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCHBS (2410) - SYSTEMZ_INS_VCHBS - vchbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCHF (2411) - SYSTEMZ_INS_VCHF - vchf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCHFS (2412) - SYSTEMZ_INS_VCHFS - vchfs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCHG (2413) - SYSTEMZ_INS_VCHG - vchg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCHGS (2414) - SYSTEMZ_INS_VCHGS - vchgs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCHH (2415) - SYSTEMZ_INS_VCHH - vchh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCHHS (2416) - SYSTEMZ_INS_VCHHS - vchhs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCHL (2417) - SYSTEMZ_INS_VCHL - vchl $V1, $V2, $V3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCHLB (2418) - SYSTEMZ_INS_VCHLB - vchlb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCHLBS (2419) - SYSTEMZ_INS_VCHLBS - vchlbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCHLF (2420) - SYSTEMZ_INS_VCHLF - vchlf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCHLFS (2421) - SYSTEMZ_INS_VCHLFS - vchlfs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCHLG (2422) - SYSTEMZ_INS_VCHLG - vchlg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCHLGS (2423) - SYSTEMZ_INS_VCHLGS - vchlgs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCHLH (2424) - SYSTEMZ_INS_VCHLH - vchlh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCHLHS (2425) - SYSTEMZ_INS_VCHLHS - vchlhs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCKSM (2426) - SYSTEMZ_INS_VCKSM - vcksm $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCLFEB (2427) - SYSTEMZ_INS_VCLFEB - vclfeb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCLFNH (2428) - SYSTEMZ_INS_VCLFNH - vclfnh $V1, $V2, $M3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VCLFNL (2429) - SYSTEMZ_INS_VCLFNL - vclfnl $V1, $V2, $M3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VCLFP (2430) - SYSTEMZ_INS_VCLFP - vclfp $V1, $V2, $M3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCLGD (2431) - SYSTEMZ_INS_VCLGD - vclgd $V1, $V2, $M3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCLGDB (2432) - SYSTEMZ_INS_VCLGDB - vclgdb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCLZ (2433) - SYSTEMZ_INS_VCLZ - vclz $V1, $V2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCLZB (2434) - SYSTEMZ_INS_VCLZB - vclzb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VCLZDP (2435) - SYSTEMZ_INS_VCLZDP - vclzdp $V1, $V2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCLZF (2436) - SYSTEMZ_INS_VCLZF - vclzf $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VCLZG (2437) - SYSTEMZ_INS_VCLZG - vclzg $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VCLZH (2438) - SYSTEMZ_INS_VCLZH - vclzh $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VCNF (2439) - SYSTEMZ_INS_VCNF - vcnf $V1, $V2, $M3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VCP (2440) - SYSTEMZ_INS_VCP - vcp $V1, $V2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCRNF (2441) - SYSTEMZ_INS_VCRNF - vcrnf $V1, $V2, $V3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCSFP (2442) - SYSTEMZ_INS_VCSFP - vcsfp $V1, $V2, $M3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VCSPH (2443) - SYSTEMZ_INS_VCSPH - vcsph $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VCTZ (2444) - SYSTEMZ_INS_VCTZ - vctz $V1, $V2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCTZB (2445) - SYSTEMZ_INS_VCTZB - vctzb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VCTZF (2446) - SYSTEMZ_INS_VCTZF - vctzf $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VCTZG (2447) - SYSTEMZ_INS_VCTZG - vctzg $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VCTZH (2448) - SYSTEMZ_INS_VCTZH - vctzh $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VCVB (2449) - SYSTEMZ_INS_VCVB - vcvb $R1, $V2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCVBG (2450) - SYSTEMZ_INS_VCVBG - vcvbg $R1, $V2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VCVBGOpt (2451) - SYSTEMZ_INS_VCVBG - vcvbg $R1, $V2, $M3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VCVBOpt (2452) - SYSTEMZ_INS_VCVB - vcvb $R1, $V2, $M3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VCVD (2453) - SYSTEMZ_INS_VCVD - vcvd $V1, $R2, $I3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VCVDG (2454) - SYSTEMZ_INS_VCVDG - vcvdg $V1, $R2, $I3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VDP (2455) - SYSTEMZ_INS_VDP - vdp $V1, $V2, $V3, $I4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VEC (2456) - SYSTEMZ_INS_VEC - vec $V1, $V2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VECB (2457) - SYSTEMZ_INS_VECB - vecb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VECF (2458) - SYSTEMZ_INS_VECF - vecf $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VECG (2459) - SYSTEMZ_INS_VECG - vecg $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VECH (2460) - SYSTEMZ_INS_VECH - vech $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VECL (2461) - SYSTEMZ_INS_VECL - vecl $V1, $V2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VECLB (2462) - SYSTEMZ_INS_VECLB - veclb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VECLF (2463) - SYSTEMZ_INS_VECLF - veclf $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VECLG (2464) - SYSTEMZ_INS_VECLG - veclg $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VECLH (2465) - SYSTEMZ_INS_VECLH - veclh $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VERIM (2466) - SYSTEMZ_INS_VERIM - verim $V1, $V2, $V3, $I4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VERIMB (2467) - SYSTEMZ_INS_VERIMB - verimb $V1, $V2, $V3, $I4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { 0 } +}}, +{ /* SYSTEMZ_VERIMF (2468) - SYSTEMZ_INS_VERIMF - verimf $V1, $V2, $V3, $I4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { 0 } +}}, +{ /* SYSTEMZ_VERIMG (2469) - SYSTEMZ_INS_VERIMG - verimg $V1, $V2, $V3, $I4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { 0 } +}}, +{ /* SYSTEMZ_VERIMH (2470) - SYSTEMZ_INS_VERIMH - verimh $V1, $V2, $V3, $I4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { 0 } +}}, +{ /* SYSTEMZ_VERLL (2471) - SYSTEMZ_INS_VERLL - verll $V1, $V3, $BD2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VERLLB (2472) - SYSTEMZ_INS_VERLLB - verllb $V1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VERLLF (2473) - SYSTEMZ_INS_VERLLF - verllf $V1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VERLLG (2474) - SYSTEMZ_INS_VERLLG - verllg $V1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VERLLH (2475) - SYSTEMZ_INS_VERLLH - verllh $V1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VERLLV (2476) - SYSTEMZ_INS_VERLLV - verllv $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VERLLVB (2477) - SYSTEMZ_INS_VERLLVB - verllvb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VERLLVF (2478) - SYSTEMZ_INS_VERLLVF - verllvf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VERLLVG (2479) - SYSTEMZ_INS_VERLLVG - verllvg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VERLLVH (2480) - SYSTEMZ_INS_VERLLVH - verllvh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VESL (2481) - SYSTEMZ_INS_VESL - vesl $V1, $V3, $BD2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VESLB (2482) - SYSTEMZ_INS_VESLB - veslb $V1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VESLF (2483) - SYSTEMZ_INS_VESLF - veslf $V1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VESLG (2484) - SYSTEMZ_INS_VESLG - veslg $V1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VESLH (2485) - SYSTEMZ_INS_VESLH - veslh $V1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VESLV (2486) - SYSTEMZ_INS_VESLV - veslv $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VESLVB (2487) - SYSTEMZ_INS_VESLVB - veslvb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VESLVF (2488) - SYSTEMZ_INS_VESLVF - veslvf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VESLVG (2489) - SYSTEMZ_INS_VESLVG - veslvg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VESLVH (2490) - SYSTEMZ_INS_VESLVH - veslvh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRA (2491) - SYSTEMZ_INS_VESRA - vesra $V1, $V3, $BD2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRAB (2492) - SYSTEMZ_INS_VESRAB - vesrab $V1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRAF (2493) - SYSTEMZ_INS_VESRAF - vesraf $V1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRAG (2494) - SYSTEMZ_INS_VESRAG - vesrag $V1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRAH (2495) - SYSTEMZ_INS_VESRAH - vesrah $V1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRAV (2496) - SYSTEMZ_INS_VESRAV - vesrav $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRAVB (2497) - SYSTEMZ_INS_VESRAVB - vesravb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRAVF (2498) - SYSTEMZ_INS_VESRAVF - vesravf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRAVG (2499) - SYSTEMZ_INS_VESRAVG - vesravg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRAVH (2500) - SYSTEMZ_INS_VESRAVH - vesravh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRL (2501) - SYSTEMZ_INS_VESRL - vesrl $V1, $V3, $BD2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRLB (2502) - SYSTEMZ_INS_VESRLB - vesrlb $V1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRLF (2503) - SYSTEMZ_INS_VESRLF - vesrlf $V1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRLG (2504) - SYSTEMZ_INS_VESRLG - vesrlg $V1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRLH (2505) - SYSTEMZ_INS_VESRLH - vesrlh $V1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRLV (2506) - SYSTEMZ_INS_VESRLV - vesrlv $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRLVB (2507) - SYSTEMZ_INS_VESRLVB - vesrlvb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRLVF (2508) - SYSTEMZ_INS_VESRLVF - vesrlvf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRLVG (2509) - SYSTEMZ_INS_VESRLVG - vesrlvg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VESRLVH (2510) - SYSTEMZ_INS_VESRLVH - vesrlvh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFA (2511) - SYSTEMZ_INS_VFA - vfa $V1, $V2, $V3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFADB (2512) - SYSTEMZ_INS_VFADB - vfadb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFAE (2513) - SYSTEMZ_INS_VFAE - vfae $V1, $V2, $V3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFAEB (2514) - SYSTEMZ_INS_VFAEB - vfaeb $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFAEBS (2515) - SYSTEMZ_INS_VFAEBS - vfaebs $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFAEF (2516) - SYSTEMZ_INS_VFAEF - vfaef $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFAEFS (2517) - SYSTEMZ_INS_VFAEFS - vfaefs $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFAEH (2518) - SYSTEMZ_INS_VFAEH - vfaeh $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFAEHS (2519) - SYSTEMZ_INS_VFAEHS - vfaehs $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFAEZB (2520) - SYSTEMZ_INS_VFAEZB - vfaezb $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFAEZBS (2521) - SYSTEMZ_INS_VFAEZBS - vfaezbs $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFAEZF (2522) - SYSTEMZ_INS_VFAEZF - vfaezf $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFAEZFS (2523) - SYSTEMZ_INS_VFAEZFS - vfaezfs $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFAEZH (2524) - SYSTEMZ_INS_VFAEZH - vfaezh $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFAEZHS (2525) - SYSTEMZ_INS_VFAEZHS - vfaezhs $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFASB (2526) - SYSTEMZ_INS_VFASB - vfasb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFCE (2527) - SYSTEMZ_INS_VFCE - vfce $V1, $V2, $V3, $M4, $M5, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VFCEDB (2528) - SYSTEMZ_INS_VFCEDB - vfcedb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFCEDBS (2529) - SYSTEMZ_INS_VFCEDBS - vfcedbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFCESB (2530) - SYSTEMZ_INS_VFCESB - vfcesb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFCESBS (2531) - SYSTEMZ_INS_VFCESBS - vfcesbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFCH (2532) - SYSTEMZ_INS_VFCH - vfch $V1, $V2, $V3, $M4, $M5, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VFCHDB (2533) - SYSTEMZ_INS_VFCHDB - vfchdb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFCHDBS (2534) - SYSTEMZ_INS_VFCHDBS - vfchdbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFCHE (2535) - SYSTEMZ_INS_VFCHE - vfche $V1, $V2, $V3, $M4, $M5, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VFCHEDB (2536) - SYSTEMZ_INS_VFCHEDB - vfchedb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFCHEDBS (2537) - SYSTEMZ_INS_VFCHEDBS - vfchedbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFCHESB (2538) - SYSTEMZ_INS_VFCHESB - vfchesb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFCHESBS (2539) - SYSTEMZ_INS_VFCHESBS - vfchesbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFCHSB (2540) - SYSTEMZ_INS_VFCHSB - vfchsb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFCHSBS (2541) - SYSTEMZ_INS_VFCHSBS - vfchsbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFD (2542) - SYSTEMZ_INS_VFD - vfd $V1, $V2, $V3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFDDB (2543) - SYSTEMZ_INS_VFDDB - vfddb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFDSB (2544) - SYSTEMZ_INS_VFDSB - vfdsb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFEE (2545) - SYSTEMZ_INS_VFEE - vfee $V1, $V2, $V3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFEEB (2546) - SYSTEMZ_INS_VFEEB - vfeeb $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFEEBS (2547) - SYSTEMZ_INS_VFEEBS - vfeebs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFEEF (2548) - SYSTEMZ_INS_VFEEF - vfeef $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFEEFS (2549) - SYSTEMZ_INS_VFEEFS - vfeefs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFEEH (2550) - SYSTEMZ_INS_VFEEH - vfeeh $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFEEHS (2551) - SYSTEMZ_INS_VFEEHS - vfeehs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFEEZB (2552) - SYSTEMZ_INS_VFEEZB - vfeezb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFEEZBS (2553) - SYSTEMZ_INS_VFEEZBS - vfeezbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFEEZF (2554) - SYSTEMZ_INS_VFEEZF - vfeezf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFEEZFS (2555) - SYSTEMZ_INS_VFEEZFS - vfeezfs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFEEZH (2556) - SYSTEMZ_INS_VFEEZH - vfeezh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFEEZHS (2557) - SYSTEMZ_INS_VFEEZHS - vfeezhs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFENE (2558) - SYSTEMZ_INS_VFENE - vfene $V1, $V2, $V3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFENEB (2559) - SYSTEMZ_INS_VFENEB - vfeneb $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFENEBS (2560) - SYSTEMZ_INS_VFENEBS - vfenebs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFENEF (2561) - SYSTEMZ_INS_VFENEF - vfenef $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFENEFS (2562) - SYSTEMZ_INS_VFENEFS - vfenefs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFENEH (2563) - SYSTEMZ_INS_VFENEH - vfeneh $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFENEHS (2564) - SYSTEMZ_INS_VFENEHS - vfenehs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFENEZB (2565) - SYSTEMZ_INS_VFENEZB - vfenezb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFENEZBS (2566) - SYSTEMZ_INS_VFENEZBS - vfenezbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFENEZF (2567) - SYSTEMZ_INS_VFENEZF - vfenezf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFENEZFS (2568) - SYSTEMZ_INS_VFENEZFS - vfenezfs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFENEZH (2569) - SYSTEMZ_INS_VFENEZH - vfenezh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFENEZHS (2570) - SYSTEMZ_INS_VFENEZHS - vfenezhs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFI (2571) - SYSTEMZ_INS_VFI - vfi $V1, $V2, $M3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFIDB (2572) - SYSTEMZ_INS_VFIDB - vfidb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFISB (2573) - SYSTEMZ_INS_VFISB - vfisb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFKEDB (2574) - SYSTEMZ_INS_VFKEDB - vfkedb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFKEDBS (2575) - SYSTEMZ_INS_VFKEDBS - vfkedbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFKESB (2576) - SYSTEMZ_INS_VFKESB - vfkesb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFKESBS (2577) - SYSTEMZ_INS_VFKESBS - vfkesbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFKHDB (2578) - SYSTEMZ_INS_VFKHDB - vfkhdb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFKHDBS (2579) - SYSTEMZ_INS_VFKHDBS - vfkhdbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFKHEDB (2580) - SYSTEMZ_INS_VFKHEDB - vfkhedb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFKHEDBS (2581) - SYSTEMZ_INS_VFKHEDBS - vfkhedbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFKHESB (2582) - SYSTEMZ_INS_VFKHESB - vfkhesb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFKHESBS (2583) - SYSTEMZ_INS_VFKHESBS - vfkhesbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFKHSB (2584) - SYSTEMZ_INS_VFKHSB - vfkhsb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFKHSBS (2585) - SYSTEMZ_INS_VFKHSBS - vfkhsbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFLCDB (2586) - SYSTEMZ_INS_VFLCDB - vflcdb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VFLCSB (2587) - SYSTEMZ_INS_VFLCSB - vflcsb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VFLL (2588) - SYSTEMZ_INS_VFLL - vfll $V1, $V2, $M3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VFLLS (2589) - SYSTEMZ_INS_VFLLS - vflls $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VFLNDB (2590) - SYSTEMZ_INS_VFLNDB - vflndb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VFLNSB (2591) - SYSTEMZ_INS_VFLNSB - vflnsb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VFLPDB (2592) - SYSTEMZ_INS_VFLPDB - vflpdb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VFLPSB (2593) - SYSTEMZ_INS_VFLPSB - vflpsb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VFLR (2594) - SYSTEMZ_INS_VFLR - vflr $V1, $V2, $M3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFLRD (2595) - SYSTEMZ_INS_VFLRD - vflrd $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFM (2596) - SYSTEMZ_INS_VFM - vfm $V1, $V2, $V3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFMA (2597) - SYSTEMZ_INS_VFMA - vfma $V1, $V2, $V3, $V4, $M5, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VFMADB (2598) - SYSTEMZ_INS_VFMADB - vfmadb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VFMASB (2599) - SYSTEMZ_INS_VFMASB - vfmasb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VFMAX (2600) - SYSTEMZ_INS_VFMAX - vfmax $V1, $V2, $V3, $M4, $M5, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VFMAXDB (2601) - SYSTEMZ_INS_VFMAXDB - vfmaxdb $V1, $V2, $V3, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VFMAXSB (2602) - SYSTEMZ_INS_VFMAXSB - vfmaxsb $V1, $V2, $V3, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VFMDB (2603) - SYSTEMZ_INS_VFMDB - vfmdb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFMIN (2604) - SYSTEMZ_INS_VFMIN - vfmin $V1, $V2, $V3, $M4, $M5, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VFMINDB (2605) - SYSTEMZ_INS_VFMINDB - vfmindb $V1, $V2, $V3, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VFMINSB (2606) - SYSTEMZ_INS_VFMINSB - vfminsb $V1, $V2, $V3, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VFMS (2607) - SYSTEMZ_INS_VFMS - vfms $V1, $V2, $V3, $V4, $M5, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VFMSB (2608) - SYSTEMZ_INS_VFMSB - vfmsb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFMSDB (2609) - SYSTEMZ_INS_VFMSDB - vfmsdb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VFMSSB (2610) - SYSTEMZ_INS_VFMSSB - vfmssb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VFNMA (2611) - SYSTEMZ_INS_VFNMA - vfnma $V1, $V2, $V3, $V4, $M5, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VFNMADB (2612) - SYSTEMZ_INS_VFNMADB - vfnmadb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VFNMASB (2613) - SYSTEMZ_INS_VFNMASB - vfnmasb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VFNMS (2614) - SYSTEMZ_INS_VFNMS - vfnms $V1, $V2, $V3, $V4, $M5, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VFNMSDB (2615) - SYSTEMZ_INS_VFNMSDB - vfnmsdb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VFNMSSB (2616) - SYSTEMZ_INS_VFNMSSB - vfnmssb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VFPSO (2617) - SYSTEMZ_INS_VFPSO - vfpso $V1, $V2, $M3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFPSODB (2618) - SYSTEMZ_INS_VFPSODB - vfpsodb $V1, $V2, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFPSOSB (2619) - SYSTEMZ_INS_VFPSOSB - vfpsosb $V1, $V2, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFS (2620) - SYSTEMZ_INS_VFS - vfs $V1, $V2, $V3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFSDB (2621) - SYSTEMZ_INS_VFSDB - vfsdb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFSQ (2622) - SYSTEMZ_INS_VFSQ - vfsq $V1, $V2, $M3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VFSQDB (2623) - SYSTEMZ_INS_VFSQDB - vfsqdb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VFSQSB (2624) - SYSTEMZ_INS_VFSQSB - vfsqsb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VFSSB (2625) - SYSTEMZ_INS_VFSSB - vfssb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFTCI (2626) - SYSTEMZ_INS_VFTCI - vftci $V1, $V2, $I3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VFTCIDB (2627) - SYSTEMZ_INS_VFTCIDB - vftcidb $V1, $V2, $I3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { 0 } +}}, +{ /* SYSTEMZ_VFTCISB (2628) - SYSTEMZ_INS_VFTCISB - vftcisb $V1, $V2, $I3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { 0 } +}}, +{ /* SYSTEMZ_VGBM (2629) - SYSTEMZ_INS_VGBM - vgbm $V1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_VGEF (2630) - SYSTEMZ_INS_VGEF - vgef $V1, $VBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* VBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* VBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* VBD2 - VR128 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VGEG (2631) - SYSTEMZ_INS_VGEG - vgeg $V1, $VBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* VBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* VBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* VBD2 - VR128 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VGFM (2632) - SYSTEMZ_INS_VGFM - vgfm $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VGFMA (2633) - SYSTEMZ_INS_VGFMA - vgfma $V1, $V2, $V3, $V4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VGFMAB (2634) - SYSTEMZ_INS_VGFMAB - vgfmab $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VGFMAF (2635) - SYSTEMZ_INS_VGFMAF - vgfmaf $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VGFMAG (2636) - SYSTEMZ_INS_VGFMAG - vgfmag $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VGFMAH (2637) - SYSTEMZ_INS_VGFMAH - vgfmah $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VGFMB (2638) - SYSTEMZ_INS_VGFMB - vgfmb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VGFMF (2639) - SYSTEMZ_INS_VGFMF - vgfmf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VGFMG (2640) - SYSTEMZ_INS_VGFMG - vgfmg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VGFMH (2641) - SYSTEMZ_INS_VGFMH - vgfmh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VGM (2642) - SYSTEMZ_INS_VGM - vgm $V1, $I2, $I3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VGMB (2643) - SYSTEMZ_INS_VGMB - vgmb $V1, $I2, $I3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { 0 } +}}, +{ /* SYSTEMZ_VGMF (2644) - SYSTEMZ_INS_VGMF - vgmf $V1, $I2, $I3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { 0 } +}}, +{ /* SYSTEMZ_VGMG (2645) - SYSTEMZ_INS_VGMG - vgmg $V1, $I2, $I3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { 0 } +}}, +{ /* SYSTEMZ_VGMH (2646) - SYSTEMZ_INS_VGMH - vgmh $V1, $I2, $I3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { 0 } +}}, +{ /* SYSTEMZ_VISTR (2647) - SYSTEMZ_INS_VISTR - vistr $V1, $V2, $M3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VISTRB (2648) - SYSTEMZ_INS_VISTRB - vistrb $V1, $V2, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VISTRBS (2649) - SYSTEMZ_INS_VISTRBS - vistrbs $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VISTRF (2650) - SYSTEMZ_INS_VISTRF - vistrf $V1, $V2, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VISTRFS (2651) - SYSTEMZ_INS_VISTRFS - vistrfs $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VISTRH (2652) - SYSTEMZ_INS_VISTRH - vistrh $V1, $V2, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VISTRHS (2653) - SYSTEMZ_INS_VISTRHS - vistrhs $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VL (2654) - SYSTEMZ_INS_VL - vl $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLAlign (2655) - SYSTEMZ_INS_VL - vl $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLBB (2656) - SYSTEMZ_INS_VLBB - vlbb $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLBR (2657) - SYSTEMZ_INS_VLBR - vlbr $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLBRF (2658) - SYSTEMZ_INS_VLBRF - vlbrf $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLBRG (2659) - SYSTEMZ_INS_VLBRG - vlbrg $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLBRH (2660) - SYSTEMZ_INS_VLBRH - vlbrh $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLBRQ (2661) - SYSTEMZ_INS_VLBRQ - vlbrq $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLBRREP (2662) - SYSTEMZ_INS_VLBRREP - vlbrrep $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLBRREPF (2663) - SYSTEMZ_INS_VLBRREPF - vlbrrepf $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLBRREPG (2664) - SYSTEMZ_INS_VLBRREPG - vlbrrepg $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLBRREPH (2665) - SYSTEMZ_INS_VLBRREPH - vlbrreph $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLC (2666) - SYSTEMZ_INS_VLC - vlc $V1, $V2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLCB (2667) - SYSTEMZ_INS_VLCB - vlcb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VLCF (2668) - SYSTEMZ_INS_VLCF - vlcf $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VLCG (2669) - SYSTEMZ_INS_VLCG - vlcg $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VLCH (2670) - SYSTEMZ_INS_VLCH - vlch $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VLDE (2671) - SYSTEMZ_INS_VLDE - vlde $V1, $V2, $M3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VLDEB (2672) - SYSTEMZ_INS_VLDEB - vldeb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VLEB (2673) - SYSTEMZ_INS_VLEB - vleb $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLEBRF (2674) - SYSTEMZ_INS_VLEBRF - vlebrf $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLEBRG (2675) - SYSTEMZ_INS_VLEBRG - vlebrg $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLEBRH (2676) - SYSTEMZ_INS_VLEBRH - vlebrh $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLED (2677) - SYSTEMZ_INS_VLED - vled $V1, $V2, $M3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VLEDB (2678) - SYSTEMZ_INS_VLEDB - vledb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VLEF (2679) - SYSTEMZ_INS_VLEF - vlef $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLEG (2680) - SYSTEMZ_INS_VLEG - vleg $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLEH (2681) - SYSTEMZ_INS_VLEH - vleh $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLEIB (2682) - SYSTEMZ_INS_VLEIB - vleib $V1, $I2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLEIF (2683) - SYSTEMZ_INS_VLEIF - vleif $V1, $I2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLEIG (2684) - SYSTEMZ_INS_VLEIG - vleig $V1, $I2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLEIH (2685) - SYSTEMZ_INS_VLEIH - vleih $V1, $I2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLER (2686) - SYSTEMZ_INS_VLER - vler $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLERF (2687) - SYSTEMZ_INS_VLERF - vlerf $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLERG (2688) - SYSTEMZ_INS_VLERG - vlerg $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLERH (2689) - SYSTEMZ_INS_VLERH - vlerh $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLGV (2690) - SYSTEMZ_INS_VLGV - vlgv $R1, $V3, $BD2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VLGVB (2691) - SYSTEMZ_INS_VLGVB - vlgvb $R1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VLGVF (2692) - SYSTEMZ_INS_VLGVF - vlgvf $R1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VLGVG (2693) - SYSTEMZ_INS_VLGVG - vlgvg $R1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VLGVH (2694) - SYSTEMZ_INS_VLGVH - vlgvh $R1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VLIP (2695) - SYSTEMZ_INS_VLIP - vlip $V1, $I2, $I3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLL (2696) - SYSTEMZ_INS_VLL - vll $V1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLLEBRZ (2697) - SYSTEMZ_INS_VLLEBRZ - vllebrz $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLLEBRZE (2698) - SYSTEMZ_INS_VLLEBRZE - vllebrze $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLLEBRZF (2699) - SYSTEMZ_INS_VLLEBRZF - vllebrzf $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLLEBRZG (2700) - SYSTEMZ_INS_VLLEBRZG - vllebrzg $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLLEBRZH (2701) - SYSTEMZ_INS_VLLEBRZH - vllebrzh $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLLEZ (2702) - SYSTEMZ_INS_VLLEZ - vllez $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLLEZB (2703) - SYSTEMZ_INS_VLLEZB - vllezb $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLLEZF (2704) - SYSTEMZ_INS_VLLEZF - vllezf $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLLEZG (2705) - SYSTEMZ_INS_VLLEZG - vllezg $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLLEZH (2706) - SYSTEMZ_INS_VLLEZH - vllezh $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLLEZLF (2707) - SYSTEMZ_INS_VLLEZLF - vllezlf $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLM (2708) - SYSTEMZ_INS_VLM - vlm $V1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLMAlign (2709) - SYSTEMZ_INS_VLM - vlm $V1, $V3, $BD2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VLP (2710) - SYSTEMZ_INS_VLP - vlp $V1, $V2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLPB (2711) - SYSTEMZ_INS_VLPB - vlpb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VLPF (2712) - SYSTEMZ_INS_VLPF - vlpf $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VLPG (2713) - SYSTEMZ_INS_VLPG - vlpg $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VLPH (2714) - SYSTEMZ_INS_VLPH - vlph $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VLR (2715) - SYSTEMZ_INS_VLR - vlr $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VLREP (2716) - SYSTEMZ_INS_VLREP - vlrep $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLREPB (2717) - SYSTEMZ_INS_VLREPB - vlrepb $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLREPF (2718) - SYSTEMZ_INS_VLREPF - vlrepf $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLREPG (2719) - SYSTEMZ_INS_VLREPG - vlrepg $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLREPH (2720) - SYSTEMZ_INS_VLREPH - vlreph $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLRL (2721) - SYSTEMZ_INS_VLRL - vlrl $V1, $BD2, $I3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { 0 } +}}, +{ /* SYSTEMZ_VLRLR (2722) - SYSTEMZ_INS_VLRLR - vlrlr $V1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_VLVG (2723) - SYSTEMZ_INS_VLVG - vlvg $V1, $R3, $BD2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VLVGB (2724) - SYSTEMZ_INS_VLVGB - vlvgb $V1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VLVGF (2725) - SYSTEMZ_INS_VLVGF - vlvgf $V1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VLVGG (2726) - SYSTEMZ_INS_VLVGG - vlvgg $V1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VLVGH (2727) - SYSTEMZ_INS_VLVGH - vlvgh $V1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR32 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm32 */ + { 0 } +}}, +{ /* SYSTEMZ_VLVGP (2728) - SYSTEMZ_INS_VLVGP - vlvgp $V1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMAE (2729) - SYSTEMZ_INS_VMAE - vmae $V1, $V2, $V3, $V4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VMAEB (2730) - SYSTEMZ_INS_VMAEB - vmaeb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMAEF (2731) - SYSTEMZ_INS_VMAEF - vmaef $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMAEH (2732) - SYSTEMZ_INS_VMAEH - vmaeh $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMAH (2733) - SYSTEMZ_INS_VMAH - vmah $V1, $V2, $V3, $V4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VMAHB (2734) - SYSTEMZ_INS_VMAHB - vmahb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMAHF (2735) - SYSTEMZ_INS_VMAHF - vmahf $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMAHH (2736) - SYSTEMZ_INS_VMAHH - vmahh $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMAL (2737) - SYSTEMZ_INS_VMAL - vmal $V1, $V2, $V3, $V4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VMALB (2738) - SYSTEMZ_INS_VMALB - vmalb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMALE (2739) - SYSTEMZ_INS_VMALE - vmale $V1, $V2, $V3, $V4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VMALEB (2740) - SYSTEMZ_INS_VMALEB - vmaleb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMALEF (2741) - SYSTEMZ_INS_VMALEF - vmalef $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMALEH (2742) - SYSTEMZ_INS_VMALEH - vmaleh $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMALF (2743) - SYSTEMZ_INS_VMALF - vmalf $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMALH (2744) - SYSTEMZ_INS_VMALH - vmalh $V1, $V2, $V3, $V4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VMALHB (2745) - SYSTEMZ_INS_VMALHB - vmalhb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMALHF (2746) - SYSTEMZ_INS_VMALHF - vmalhf $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMALHH (2747) - SYSTEMZ_INS_VMALHH - vmalhh $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMALHW (2748) - SYSTEMZ_INS_VMALHW - vmalhw $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMALO (2749) - SYSTEMZ_INS_VMALO - vmalo $V1, $V2, $V3, $V4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VMALOB (2750) - SYSTEMZ_INS_VMALOB - vmalob $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMALOF (2751) - SYSTEMZ_INS_VMALOF - vmalof $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMALOH (2752) - SYSTEMZ_INS_VMALOH - vmaloh $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMAO (2753) - SYSTEMZ_INS_VMAO - vmao $V1, $V2, $V3, $V4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VMAOB (2754) - SYSTEMZ_INS_VMAOB - vmaob $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMAOF (2755) - SYSTEMZ_INS_VMAOF - vmaof $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMAOH (2756) - SYSTEMZ_INS_VMAOH - vmaoh $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VME (2757) - SYSTEMZ_INS_VME - vme $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMEB (2758) - SYSTEMZ_INS_VMEB - vmeb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMEF (2759) - SYSTEMZ_INS_VMEF - vmef $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMEH (2760) - SYSTEMZ_INS_VMEH - vmeh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMH (2761) - SYSTEMZ_INS_VMH - vmh $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMHB (2762) - SYSTEMZ_INS_VMHB - vmhb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMHF (2763) - SYSTEMZ_INS_VMHF - vmhf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMHH (2764) - SYSTEMZ_INS_VMHH - vmhh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VML (2765) - SYSTEMZ_INS_VML - vml $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMLB (2766) - SYSTEMZ_INS_VMLB - vmlb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMLE (2767) - SYSTEMZ_INS_VMLE - vmle $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMLEB (2768) - SYSTEMZ_INS_VMLEB - vmleb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMLEF (2769) - SYSTEMZ_INS_VMLEF - vmlef $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMLEH (2770) - SYSTEMZ_INS_VMLEH - vmleh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMLF (2771) - SYSTEMZ_INS_VMLF - vmlf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMLH (2772) - SYSTEMZ_INS_VMLH - vmlh $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMLHB (2773) - SYSTEMZ_INS_VMLHB - vmlhb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMLHF (2774) - SYSTEMZ_INS_VMLHF - vmlhf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMLHH (2775) - SYSTEMZ_INS_VMLHH - vmlhh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMLHW (2776) - SYSTEMZ_INS_VMLHW - vmlhw $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMLO (2777) - SYSTEMZ_INS_VMLO - vmlo $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMLOB (2778) - SYSTEMZ_INS_VMLOB - vmlob $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMLOF (2779) - SYSTEMZ_INS_VMLOF - vmlof $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMLOH (2780) - SYSTEMZ_INS_VMLOH - vmloh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMN (2781) - SYSTEMZ_INS_VMN - vmn $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMNB (2782) - SYSTEMZ_INS_VMNB - vmnb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMNF (2783) - SYSTEMZ_INS_VMNF - vmnf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMNG (2784) - SYSTEMZ_INS_VMNG - vmng $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMNH (2785) - SYSTEMZ_INS_VMNH - vmnh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMNL (2786) - SYSTEMZ_INS_VMNL - vmnl $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMNLB (2787) - SYSTEMZ_INS_VMNLB - vmnlb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMNLF (2788) - SYSTEMZ_INS_VMNLF - vmnlf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMNLG (2789) - SYSTEMZ_INS_VMNLG - vmnlg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMNLH (2790) - SYSTEMZ_INS_VMNLH - vmnlh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMO (2791) - SYSTEMZ_INS_VMO - vmo $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMOB (2792) - SYSTEMZ_INS_VMOB - vmob $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMOF (2793) - SYSTEMZ_INS_VMOF - vmof $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMOH (2794) - SYSTEMZ_INS_VMOH - vmoh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMP (2795) - SYSTEMZ_INS_VMP - vmp $V1, $V2, $V3, $I4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VMRH (2796) - SYSTEMZ_INS_VMRH - vmrh $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMRHB (2797) - SYSTEMZ_INS_VMRHB - vmrhb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMRHF (2798) - SYSTEMZ_INS_VMRHF - vmrhf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMRHG (2799) - SYSTEMZ_INS_VMRHG - vmrhg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMRHH (2800) - SYSTEMZ_INS_VMRHH - vmrhh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMRL (2801) - SYSTEMZ_INS_VMRL - vmrl $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMRLB (2802) - SYSTEMZ_INS_VMRLB - vmrlb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMRLF (2803) - SYSTEMZ_INS_VMRLF - vmrlf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMRLG (2804) - SYSTEMZ_INS_VMRLG - vmrlg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMRLH (2805) - SYSTEMZ_INS_VMRLH - vmrlh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMSL (2806) - SYSTEMZ_INS_VMSL - vmsl $V1, $V2, $V3, $V4, $M5, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VMSLG (2807) - SYSTEMZ_INS_VMSLG - vmslg $V1, $V2, $V3, $V4, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VMSP (2808) - SYSTEMZ_INS_VMSP - vmsp $V1, $V2, $V3, $I4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VMX (2809) - SYSTEMZ_INS_VMX - vmx $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMXB (2810) - SYSTEMZ_INS_VMXB - vmxb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMXF (2811) - SYSTEMZ_INS_VMXF - vmxf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMXG (2812) - SYSTEMZ_INS_VMXG - vmxg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMXH (2813) - SYSTEMZ_INS_VMXH - vmxh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMXL (2814) - SYSTEMZ_INS_VMXL - vmxl $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VMXLB (2815) - SYSTEMZ_INS_VMXLB - vmxlb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMXLF (2816) - SYSTEMZ_INS_VMXLF - vmxlf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMXLG (2817) - SYSTEMZ_INS_VMXLG - vmxlg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VMXLH (2818) - SYSTEMZ_INS_VMXLH - vmxlh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VN (2819) - SYSTEMZ_INS_VN - vn $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VNC (2820) - SYSTEMZ_INS_VNC - vnc $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VNN (2821) - SYSTEMZ_INS_VNN - vnn $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VNO (2822) - SYSTEMZ_INS_VNO - vno $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VNX (2823) - SYSTEMZ_INS_VNX - vnx $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VO (2824) - SYSTEMZ_INS_VO - vo $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VOC (2825) - SYSTEMZ_INS_VOC - voc $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VONE (2826) - SYSTEMZ_INS_VONE - vone $V1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { 0 } +}}, +{ /* SYSTEMZ_VPDI (2827) - SYSTEMZ_INS_VPDI - vpdi $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VPERM (2828) - SYSTEMZ_INS_VPERM - vperm $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VPK (2829) - SYSTEMZ_INS_VPK - vpk $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VPKF (2830) - SYSTEMZ_INS_VPKF - vpkf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VPKG (2831) - SYSTEMZ_INS_VPKG - vpkg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VPKH (2832) - SYSTEMZ_INS_VPKH - vpkh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VPKLS (2833) - SYSTEMZ_INS_VPKLS - vpkls $V1, $V2, $V3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VPKLSF (2834) - SYSTEMZ_INS_VPKLSF - vpklsf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VPKLSFS (2835) - SYSTEMZ_INS_VPKLSFS - vpklsfs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VPKLSG (2836) - SYSTEMZ_INS_VPKLSG - vpklsg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VPKLSGS (2837) - SYSTEMZ_INS_VPKLSGS - vpklsgs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VPKLSH (2838) - SYSTEMZ_INS_VPKLSH - vpklsh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VPKLSHS (2839) - SYSTEMZ_INS_VPKLSHS - vpklshs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VPKS (2840) - SYSTEMZ_INS_VPKS - vpks $V1, $V2, $V3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VPKSF (2841) - SYSTEMZ_INS_VPKSF - vpksf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VPKSFS (2842) - SYSTEMZ_INS_VPKSFS - vpksfs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VPKSG (2843) - SYSTEMZ_INS_VPKSG - vpksg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VPKSGS (2844) - SYSTEMZ_INS_VPKSGS - vpksgs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VPKSH (2845) - SYSTEMZ_INS_VPKSH - vpksh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VPKSHS (2846) - SYSTEMZ_INS_VPKSHS - vpkshs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VPKZ (2847) - SYSTEMZ_INS_VPKZ - vpkz $V1, $BD2, $I3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { 0 } +}}, +{ /* SYSTEMZ_VPKZR (2848) - SYSTEMZ_INS_VPKZR - vpkzr $V1, $V2, $V3, $I4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VPOPCT (2849) - SYSTEMZ_INS_VPOPCT - vpopct $V1, $V2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VPOPCTB (2850) - SYSTEMZ_INS_VPOPCTB - vpopctb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VPOPCTF (2851) - SYSTEMZ_INS_VPOPCTF - vpopctf $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VPOPCTG (2852) - SYSTEMZ_INS_VPOPCTG - vpopctg $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VPOPCTH (2853) - SYSTEMZ_INS_VPOPCTH - vpopcth $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VPSOP (2854) - SYSTEMZ_INS_VPSOP - vpsop $V1, $V2, $I3, $I4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VREP (2855) - SYSTEMZ_INS_VREP - vrep $V1, $V3, $I2, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VREPB (2856) - SYSTEMZ_INS_VREPB - vrepb $V1, $V3, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_VREPF (2857) - SYSTEMZ_INS_VREPF - vrepf $V1, $V3, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_VREPG (2858) - SYSTEMZ_INS_VREPG - vrepg $V1, $V3, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_VREPH (2859) - SYSTEMZ_INS_VREPH - vreph $V1, $V3, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_VREPI (2860) - SYSTEMZ_INS_VREPI - vrepi $V1, $I2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VREPIB (2861) - SYSTEMZ_INS_VREPIB - vrepib $V1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_VREPIF (2862) - SYSTEMZ_INS_VREPIF - vrepif $V1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_VREPIG (2863) - SYSTEMZ_INS_VREPIG - vrepig $V1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_VREPIH (2864) - SYSTEMZ_INS_VREPIH - vrepih $V1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_VRP (2865) - SYSTEMZ_INS_VRP - vrp $V1, $V2, $V3, $I4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VS (2866) - SYSTEMZ_INS_VS - vs $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VSB (2867) - SYSTEMZ_INS_VSB - vsb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSBCBI (2868) - SYSTEMZ_INS_VSBCBI - vsbcbi $V1, $V2, $V3, $V4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VSBCBIQ (2869) - SYSTEMZ_INS_VSBCBIQ - vsbcbiq $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VSBI (2870) - SYSTEMZ_INS_VSBI - vsbi $V1, $V2, $V3, $V4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VSBIQ (2871) - SYSTEMZ_INS_VSBIQ - vsbiq $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VSCBI (2872) - SYSTEMZ_INS_VSCBI - vscbi $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VSCBIB (2873) - SYSTEMZ_INS_VSCBIB - vscbib $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSCBIF (2874) - SYSTEMZ_INS_VSCBIF - vscbif $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSCBIG (2875) - SYSTEMZ_INS_VSCBIG - vscbig $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSCBIH (2876) - SYSTEMZ_INS_VSCBIH - vscbih $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSCBIQ (2877) - SYSTEMZ_INS_VSCBIQ - vscbiq $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSCEF (2878) - SYSTEMZ_INS_VSCEF - vscef $V1, $VBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* VBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* VBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* VBD2 - VR128 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSCEG (2879) - SYSTEMZ_INS_VSCEG - vsceg $V1, $VBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* VBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* VBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* VBD2 - VR128 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSCHDP (2880) - SYSTEMZ_INS_VSCHDP - vschdp $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VSCHP (2881) - SYSTEMZ_INS_VSCHP - vschp $V1, $V2, $V3, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VSCHSP (2882) - SYSTEMZ_INS_VSCHSP - vschsp $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VSCHXP (2883) - SYSTEMZ_INS_VSCHXP - vschxp $V1, $V2, $V3, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VSCSHP (2884) - SYSTEMZ_INS_VSCSHP - vscshp $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSDP (2885) - SYSTEMZ_INS_VSDP - vsdp $V1, $V2, $V3, $I4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VSEG (2886) - SYSTEMZ_INS_VSEG - vseg $V1, $V2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSEGB (2887) - SYSTEMZ_INS_VSEGB - vsegb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VSEGF (2888) - SYSTEMZ_INS_VSEGF - vsegf $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VSEGH (2889) - SYSTEMZ_INS_VSEGH - vsegh $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VSEL (2890) - SYSTEMZ_INS_VSEL - vsel $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VSF (2891) - SYSTEMZ_INS_VSF - vsf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSG (2892) - SYSTEMZ_INS_VSG - vsg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSH (2893) - SYSTEMZ_INS_VSH - vsh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSL (2894) - SYSTEMZ_INS_VSL - vsl $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSLB (2895) - SYSTEMZ_INS_VSLB - vslb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSLD (2896) - SYSTEMZ_INS_VSLD - vsld $V1, $V2, $V3, $I4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { 0 } +}}, +{ /* SYSTEMZ_VSLDB (2897) - SYSTEMZ_INS_VSLDB - vsldb $V1, $V2, $V3, $I4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { 0 } +}}, +{ /* SYSTEMZ_VSP (2898) - SYSTEMZ_INS_VSP - vsp $V1, $V2, $V3, $I4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VSQ (2899) - SYSTEMZ_INS_VSQ - vsq $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSRA (2900) - SYSTEMZ_INS_VSRA - vsra $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSRAB (2901) - SYSTEMZ_INS_VSRAB - vsrab $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSRD (2902) - SYSTEMZ_INS_VSRD - vsrd $V1, $V2, $V3, $I4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { 0 } +}}, +{ /* SYSTEMZ_VSRL (2903) - SYSTEMZ_INS_VSRL - vsrl $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSRLB (2904) - SYSTEMZ_INS_VSRLB - vsrlb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSRP (2905) - SYSTEMZ_INS_VSRP - vsrp $V1, $V2, $I3, $I4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VSRPR (2906) - SYSTEMZ_INS_VSRPR - vsrpr $V1, $V2, $V3, $I4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_VST (2907) - SYSTEMZ_INS_VST - vst $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTAlign (2908) - SYSTEMZ_INS_VST - vst $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTBR (2909) - SYSTEMZ_INS_VSTBR - vstbr $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTBRF (2910) - SYSTEMZ_INS_VSTBRF - vstbrf $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTBRG (2911) - SYSTEMZ_INS_VSTBRG - vstbrg $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTBRH (2912) - SYSTEMZ_INS_VSTBRH - vstbrh $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTBRQ (2913) - SYSTEMZ_INS_VSTBRQ - vstbrq $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTEB (2914) - SYSTEMZ_INS_VSTEB - vsteb $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTEBRF (2915) - SYSTEMZ_INS_VSTEBRF - vstebrf $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTEBRG (2916) - SYSTEMZ_INS_VSTEBRG - vstebrg $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTEBRH (2917) - SYSTEMZ_INS_VSTEBRH - vstebrh $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTEF (2918) - SYSTEMZ_INS_VSTEF - vstef $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTEG (2919) - SYSTEMZ_INS_VSTEG - vsteg $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTEH (2920) - SYSTEMZ_INS_VSTEH - vsteh $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTER (2921) - SYSTEMZ_INS_VSTER - vster $V1, $XBD2, $M3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTERF (2922) - SYSTEMZ_INS_VSTERF - vsterf $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTERG (2923) - SYSTEMZ_INS_VSTERG - vsterg $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTERH (2924) - SYSTEMZ_INS_VSTERH - vsterh $V1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTL (2925) - SYSTEMZ_INS_VSTL - vstl $V1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTM (2926) - SYSTEMZ_INS_VSTM - vstm $V1, $V3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTMAlign (2927) - SYSTEMZ_INS_VSTM - vstm $V1, $V3, $BD2, $M4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRC (2928) - SYSTEMZ_INS_VSTRC - vstrc $V1, $V2, $V3, $V4, $M5, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRCB (2929) - SYSTEMZ_INS_VSTRCB - vstrcb $V1, $V2, $V3, $V4, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRCBS (2930) - SYSTEMZ_INS_VSTRCBS - vstrcbs $V1, $V2, $V3, $V4, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRCF (2931) - SYSTEMZ_INS_VSTRCF - vstrcf $V1, $V2, $V3, $V4, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRCFS (2932) - SYSTEMZ_INS_VSTRCFS - vstrcfs $V1, $V2, $V3, $V4, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRCH (2933) - SYSTEMZ_INS_VSTRCH - vstrch $V1, $V2, $V3, $V4, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRCHS (2934) - SYSTEMZ_INS_VSTRCHS - vstrchs $V1, $V2, $V3, $V4, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRCZB (2935) - SYSTEMZ_INS_VSTRCZB - vstrczb $V1, $V2, $V3, $V4, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRCZBS (2936) - SYSTEMZ_INS_VSTRCZBS - vstrczbs $V1, $V2, $V3, $V4, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRCZF (2937) - SYSTEMZ_INS_VSTRCZF - vstrczf $V1, $V2, $V3, $V4, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRCZFS (2938) - SYSTEMZ_INS_VSTRCZFS - vstrczfs $V1, $V2, $V3, $V4, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRCZH (2939) - SYSTEMZ_INS_VSTRCZH - vstrczh $V1, $V2, $V3, $V4, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRCZHS (2940) - SYSTEMZ_INS_VSTRCZHS - vstrczhs $V1, $V2, $V3, $V4, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRL (2941) - SYSTEMZ_INS_VSTRL - vstrl $V1, $BD2, $I3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRLR (2942) - SYSTEMZ_INS_VSTRLR - vstrlr $V1, $R3, $BD2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRS (2943) - SYSTEMZ_INS_VSTRS - vstrs $V1, $V2, $V3, $V4, $M5, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRSB (2944) - SYSTEMZ_INS_VSTRSB - vstrsb $V1, $V2, $V3, $V4, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRSF (2945) - SYSTEMZ_INS_VSTRSF - vstrsf $V1, $V2, $V3, $V4, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRSH (2946) - SYSTEMZ_INS_VSTRSH - vstrsh $V1, $V2, $V3, $V4, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRSZB (2947) - SYSTEMZ_INS_VSTRSZB - vstrszb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRSZF (2948) - SYSTEMZ_INS_VSTRSZF - vstrszf $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VSTRSZH (2949) - SYSTEMZ_INS_VSTRSZH - vstrszh $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_VSUM (2950) - SYSTEMZ_INS_VSUM - vsum $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VSUMB (2951) - SYSTEMZ_INS_VSUMB - vsumb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSUMG (2952) - SYSTEMZ_INS_VSUMG - vsumg $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VSUMGF (2953) - SYSTEMZ_INS_VSUMGF - vsumgf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSUMGH (2954) - SYSTEMZ_INS_VSUMGH - vsumgh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSUMH (2955) - SYSTEMZ_INS_VSUMH - vsumh $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSUMQ (2956) - SYSTEMZ_INS_VSUMQ - vsumq $V1, $V2, $V3, $M4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_VSUMQF (2957) - SYSTEMZ_INS_VSUMQF - vsumqf $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VSUMQG (2958) - SYSTEMZ_INS_VSUMQG - vsumqg $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VTM (2959) - SYSTEMZ_INS_VTM - vtm $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VTP (2960) - SYSTEMZ_INS_VTP - vtp $V1 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { 0 } +}}, +{ /* SYSTEMZ_VUPH (2961) - SYSTEMZ_INS_VUPH - vuph $V1, $V2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VUPHB (2962) - SYSTEMZ_INS_VUPHB - vuphb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VUPHF (2963) - SYSTEMZ_INS_VUPHF - vuphf $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VUPHH (2964) - SYSTEMZ_INS_VUPHH - vuphh $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VUPKZ (2965) - SYSTEMZ_INS_VUPKZ - vupkz $V1, $BD2, $I3 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { 0 } +}}, +{ /* SYSTEMZ_VUPKZH (2966) - SYSTEMZ_INS_VUPKZH - vupkzh $V1, $V2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VUPKZL (2967) - SYSTEMZ_INS_VUPKZL - vupkzl $V1, $V2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VUPL (2968) - SYSTEMZ_INS_VUPL - vupl $V1, $V2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VUPLB (2969) - SYSTEMZ_INS_VUPLB - vuplb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VUPLF (2970) - SYSTEMZ_INS_VUPLF - vuplf $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VUPLH (2971) - SYSTEMZ_INS_VUPLH - vuplh $V1, $V2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VUPLHB (2972) - SYSTEMZ_INS_VUPLHB - vuplhb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VUPLHF (2973) - SYSTEMZ_INS_VUPLHF - vuplhf $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VUPLHH (2974) - SYSTEMZ_INS_VUPLHH - vuplhh $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VUPLHW (2975) - SYSTEMZ_INS_VUPLHW - vuplhw $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VUPLL (2976) - SYSTEMZ_INS_VUPLL - vupll $V1, $V2, $M3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { 0 } +}}, +{ /* SYSTEMZ_VUPLLB (2977) - SYSTEMZ_INS_VUPLLB - vupllb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VUPLLF (2978) - SYSTEMZ_INS_VUPLLF - vupllf $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VUPLLH (2979) - SYSTEMZ_INS_VUPLLH - vupllh $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_VX (2980) - SYSTEMZ_INS_VX - vx $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_VZERO (2981) - SYSTEMZ_INS_VZERO - vzero $V1 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { 0 } +}}, +{ /* SYSTEMZ_WCDGB (2982) - SYSTEMZ_INS_WCDGB - wcdgb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_WCDLGB (2983) - SYSTEMZ_INS_WCDLGB - wcdlgb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_WCEFB (2984) - SYSTEMZ_INS_WCEFB - wcefb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_WCELFB (2985) - SYSTEMZ_INS_WCELFB - wcelfb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_WCFEB (2986) - SYSTEMZ_INS_WCFEB - wcfeb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_WCGDB (2987) - SYSTEMZ_INS_WCGDB - wcgdb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_WCLFEB (2988) - SYSTEMZ_INS_WCLFEB - wclfeb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_WCLGDB (2989) - SYSTEMZ_INS_WCLGDB - wclgdb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_WFADB (2990) - SYSTEMZ_INS_WFADB - wfadb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFASB (2991) - SYSTEMZ_INS_WFASB - wfasb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFAXB (2992) - SYSTEMZ_INS_WFAXB - wfaxb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFC (2993) - SYSTEMZ_INS_WFC - wfc $V1, $V2, $M3, $M4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCDB (2994) - SYSTEMZ_INS_WFCDB - wfcdb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCEDB (2995) - SYSTEMZ_INS_WFCEDB - wfcedb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCEDBS (2996) - SYSTEMZ_INS_WFCEDBS - wfcedbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCESB (2997) - SYSTEMZ_INS_WFCESB - wfcesb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCESBS (2998) - SYSTEMZ_INS_WFCESBS - wfcesbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCEXB (2999) - SYSTEMZ_INS_WFCEXB - wfcexb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCEXBS (3000) - SYSTEMZ_INS_WFCEXBS - wfcexbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCHDB (3001) - SYSTEMZ_INS_WFCHDB - wfchdb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCHDBS (3002) - SYSTEMZ_INS_WFCHDBS - wfchdbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCHEDB (3003) - SYSTEMZ_INS_WFCHEDB - wfchedb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCHEDBS (3004) - SYSTEMZ_INS_WFCHEDBS - wfchedbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCHESB (3005) - SYSTEMZ_INS_WFCHESB - wfchesb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCHESBS (3006) - SYSTEMZ_INS_WFCHESBS - wfchesbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCHEXB (3007) - SYSTEMZ_INS_WFCHEXB - wfchexb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCHEXBS (3008) - SYSTEMZ_INS_WFCHEXBS - wfchexbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCHSB (3009) - SYSTEMZ_INS_WFCHSB - wfchsb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCHSBS (3010) - SYSTEMZ_INS_WFCHSBS - wfchsbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCHXB (3011) - SYSTEMZ_INS_WFCHXB - wfchxb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCHXBS (3012) - SYSTEMZ_INS_WFCHXBS - wfchxbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCSB (3013) - SYSTEMZ_INS_WFCSB - wfcsb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFCXB (3014) - SYSTEMZ_INS_WFCXB - wfcxb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFDDB (3015) - SYSTEMZ_INS_WFDDB - wfddb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFDSB (3016) - SYSTEMZ_INS_WFDSB - wfdsb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFDXB (3017) - SYSTEMZ_INS_WFDXB - wfdxb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFIDB (3018) - SYSTEMZ_INS_WFIDB - wfidb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_WFISB (3019) - SYSTEMZ_INS_WFISB - wfisb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_WFIXB (3020) - SYSTEMZ_INS_WFIXB - wfixb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_WFK (3021) - SYSTEMZ_INS_WFK - wfk $V1, $V2, $M3, $M4 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKDB (3022) - SYSTEMZ_INS_WFKDB - wfkdb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKEDB (3023) - SYSTEMZ_INS_WFKEDB - wfkedb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKEDBS (3024) - SYSTEMZ_INS_WFKEDBS - wfkedbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKESB (3025) - SYSTEMZ_INS_WFKESB - wfkesb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKESBS (3026) - SYSTEMZ_INS_WFKESBS - wfkesbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKEXB (3027) - SYSTEMZ_INS_WFKEXB - wfkexb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKEXBS (3028) - SYSTEMZ_INS_WFKEXBS - wfkexbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKHDB (3029) - SYSTEMZ_INS_WFKHDB - wfkhdb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKHDBS (3030) - SYSTEMZ_INS_WFKHDBS - wfkhdbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKHEDB (3031) - SYSTEMZ_INS_WFKHEDB - wfkhedb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKHEDBS (3032) - SYSTEMZ_INS_WFKHEDBS - wfkhedbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKHESB (3033) - SYSTEMZ_INS_WFKHESB - wfkhesb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKHESBS (3034) - SYSTEMZ_INS_WFKHESBS - wfkhesbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKHEXB (3035) - SYSTEMZ_INS_WFKHEXB - wfkhexb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKHEXBS (3036) - SYSTEMZ_INS_WFKHEXBS - wfkhexbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKHSB (3037) - SYSTEMZ_INS_WFKHSB - wfkhsb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKHSBS (3038) - SYSTEMZ_INS_WFKHSBS - wfkhsbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKHXB (3039) - SYSTEMZ_INS_WFKHXB - wfkhxb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKHXBS (3040) - SYSTEMZ_INS_WFKHXBS - wfkhxbs $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKSB (3041) - SYSTEMZ_INS_WFKSB - wfksb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFKXB (3042) - SYSTEMZ_INS_WFKXB - wfkxb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFLCDB (3043) - SYSTEMZ_INS_WFLCDB - wflcdb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFLCSB (3044) - SYSTEMZ_INS_WFLCSB - wflcsb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFLCXB (3045) - SYSTEMZ_INS_WFLCXB - wflcxb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFLLD (3046) - SYSTEMZ_INS_WFLLD - wflld $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFLLS (3047) - SYSTEMZ_INS_WFLLS - wflls $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFLNDB (3048) - SYSTEMZ_INS_WFLNDB - wflndb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFLNSB (3049) - SYSTEMZ_INS_WFLNSB - wflnsb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFLNXB (3050) - SYSTEMZ_INS_WFLNXB - wflnxb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFLPDB (3051) - SYSTEMZ_INS_WFLPDB - wflpdb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFLPSB (3052) - SYSTEMZ_INS_WFLPSB - wflpsb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFLPXB (3053) - SYSTEMZ_INS_WFLPXB - wflpxb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFLRD (3054) - SYSTEMZ_INS_WFLRD - wflrd $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_WFLRX (3055) - SYSTEMZ_INS_WFLRX - wflrx $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_WFMADB (3056) - SYSTEMZ_INS_WFMADB - wfmadb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_WFMASB (3057) - SYSTEMZ_INS_WFMASB - wfmasb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_WFMAXB (3058) - SYSTEMZ_INS_WFMAXB - wfmaxb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_WFMAXDB (3059) - SYSTEMZ_INS_WFMAXDB - wfmaxdb $V1, $V2, $V3, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_WFMAXSB (3060) - SYSTEMZ_INS_WFMAXSB - wfmaxsb $V1, $V2, $V3, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_WFMAXXB (3061) - SYSTEMZ_INS_WFMAXXB - wfmaxxb $V1, $V2, $V3, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_WFMDB (3062) - SYSTEMZ_INS_WFMDB - wfmdb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFMINDB (3063) - SYSTEMZ_INS_WFMINDB - wfmindb $V1, $V2, $V3, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_WFMINSB (3064) - SYSTEMZ_INS_WFMINSB - wfminsb $V1, $V2, $V3, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_WFMINXB (3065) - SYSTEMZ_INS_WFMINXB - wfminxb $V1, $V2, $V3, $M6 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M6 */ + { 0 } +}}, +{ /* SYSTEMZ_WFMSB (3066) - SYSTEMZ_INS_WFMSB - wfmsb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFMSDB (3067) - SYSTEMZ_INS_WFMSDB - wfmsdb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_WFMSSB (3068) - SYSTEMZ_INS_WFMSSB - wfmssb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_WFMSXB (3069) - SYSTEMZ_INS_WFMSXB - wfmsxb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_WFMXB (3070) - SYSTEMZ_INS_WFMXB - wfmxb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFNMADB (3071) - SYSTEMZ_INS_WFNMADB - wfnmadb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_WFNMASB (3072) - SYSTEMZ_INS_WFNMASB - wfnmasb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_WFNMAXB (3073) - SYSTEMZ_INS_WFNMAXB - wfnmaxb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_WFNMSDB (3074) - SYSTEMZ_INS_WFNMSDB - wfnmsdb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_WFNMSSB (3075) - SYSTEMZ_INS_WFNMSSB - wfnmssb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_WFNMSXB (3076) - SYSTEMZ_INS_WFNMSXB - wfnmsxb $V1, $V2, $V3, $V4 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V4 */ + { 0 } +}}, +{ /* SYSTEMZ_WFPSODB (3077) - SYSTEMZ_INS_WFPSODB - wfpsodb $V1, $V2, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_WFPSOSB (3078) - SYSTEMZ_INS_WFPSOSB - wfpsosb $V1, $V2, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_WFPSOXB (3079) - SYSTEMZ_INS_WFPSOXB - wfpsoxb $V1, $V2, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_WFSDB (3080) - SYSTEMZ_INS_WFSDB - wfsdb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFSQDB (3081) - SYSTEMZ_INS_WFSQDB - wfsqdb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFSQSB (3082) - SYSTEMZ_INS_WFSQSB - wfsqsb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFSQXB (3083) - SYSTEMZ_INS_WFSQXB - wfsqxb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WFSSB (3084) - SYSTEMZ_INS_WFSSB - wfssb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFSXB (3085) - SYSTEMZ_INS_WFSXB - wfsxb $V1, $V2, $V3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFTCIDB (3086) - SYSTEMZ_INS_WFTCIDB - wftcidb $V1, $V2, $I3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFTCISB (3087) - SYSTEMZ_INS_WFTCISB - wftcisb $V1, $V2, $I3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { 0 } +}}, +{ /* SYSTEMZ_WFTCIXB (3088) - SYSTEMZ_INS_WFTCIXB - wftcixb $V1, $V2, $I3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_i128, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_f128, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I3 */ + { 0 } +}}, +{ /* SYSTEMZ_WLDEB (3089) - SYSTEMZ_INS_WLDEB - wldeb $V1, $V2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V2 */ + { 0 } +}}, +{ /* SYSTEMZ_WLEDB (3090) - SYSTEMZ_INS_WLEDB - wledb $V1, $V2, $M4, $M5 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_v4i8, CS_DATA_TYPE_v2i16, CS_DATA_TYPE_LAST } }, /* V1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_LAST } }, /* V2 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M4 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* M5 */ + { 0 } +}}, +{ /* SYSTEMZ_X (3091) - SYSTEMZ_INS_X - x $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_XC (3092) - SYSTEMZ_INS_XC - xc $BDL1, $BD2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len8imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD2 - disp12imm64 */ + { 0 } +}}, +{ /* SYSTEMZ_XG (3093) - SYSTEMZ_INS_XG - xg $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_XGR (3094) - SYSTEMZ_INS_XGR - xgr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_XGRK (3095) - SYSTEMZ_INS_XGRK - xgrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_XI (3096) - SYSTEMZ_INS_XI - xi $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp12imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_XIHF (3097) - SYSTEMZ_INS_XIHF - xihf $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_XILF (3098) - SYSTEMZ_INS_XILF - xilf $R1, $I2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_XIY (3099) - SYSTEMZ_INS_XIY - xiy $BD1, $I2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BD1 - disp20imm64 */ + { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* I2 */ + { 0 } +}}, +{ /* SYSTEMZ_XR (3100) - SYSTEMZ_INS_XR - xr $R1, $R2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { 0 } +}}, +{ /* SYSTEMZ_XRK (3101) - SYSTEMZ_INS_XRK - xrk $R1, $R2, $R3 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R2 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R3 */ + { 0 } +}}, +{ /* SYSTEMZ_XSCH (3102) - SYSTEMZ_INS_XSCH - xsch */ +{ + { 0 } +}}, +{ /* SYSTEMZ_XY (3103) - SYSTEMZ_INS_XY - xy $R1, $XBD2 */ +{ + { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1 */ + { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R1src */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - disp20imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* XBD2 - ADDR64 */ + { 0 } +}}, +{ /* SYSTEMZ_ZAP (3104) - SYSTEMZ_INS_ZAP - zap $BDL1, $BDL2 */ +{ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL1 - len4imm64 */ + { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - ADDR64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - disp12imm64 */ + { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST } }, /* BDL2 - len4imm64 */ + { 0 } +}}, diff --git a/arch/SystemZ/SystemZGenCSOpGroup.inc b/arch/SystemZ/SystemZGenCSOpGroup.inc new file mode 100644 index 0000000000..7f25c4eb56 --- /dev/null +++ b/arch/SystemZ/SystemZGenCSOpGroup.inc @@ -0,0 +1,34 @@ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ + + SystemZ_OP_GROUP_Operand = 0, + SystemZ_OP_GROUP_BDXAddrOperand = 1, + SystemZ_OP_GROUP_S32ImmOperand = 2, + SystemZ_OP_GROUP_S16ImmOperand = 3, + SystemZ_OP_GROUP_BDAddrOperand = 4, + SystemZ_OP_GROUP_U32ImmOperand = 5, + SystemZ_OP_GROUP_U16ImmOperand = 6, + SystemZ_OP_GROUP_S8ImmOperand = 7, + SystemZ_OP_GROUP_Cond4Operand = 8, + SystemZ_OP_GROUP_U8ImmOperand = 9, + SystemZ_OP_GROUP_PCRelOperand = 10, + SystemZ_OP_GROUP_U4ImmOperand = 11, + SystemZ_OP_GROUP_BDLAddrOperand = 12, + SystemZ_OP_GROUP_PCRelTLSOperand = 13, + SystemZ_OP_GROUP_U48ImmOperand = 14, + SystemZ_OP_GROUP_BDRAddrOperand = 15, + SystemZ_OP_GROUP_U12ImmOperand = 16, + SystemZ_OP_GROUP_BDVAddrOperand = 17, + SystemZ_OP_GROUP_U2ImmOperand = 18, + SystemZ_OP_GROUP_U1ImmOperand = 19, + SystemZ_OP_GROUP_U3ImmOperand = 20, diff --git a/arch/SystemZ/SystemZGenDisassemblerTables.inc b/arch/SystemZ/SystemZGenDisassemblerTables.inc index b90664ce0c..3ae2fe53f6 100644 --- a/arch/SystemZ/SystemZGenDisassemblerTables.inc +++ b/arch/SystemZ/SystemZGenDisassemblerTables.inc @@ -1,13 +1,15 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* * SystemZ Disassembler *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ #include "../../MCInst.h" #include "../../LEB128.h" @@ -17,10235 +19,11412 @@ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ { \ InsnType fieldMask; \ - if (numBits == sizeof(InsnType)*8) \ + if (numBits == sizeof(InsnType) * 8) \ fieldMask = (InsnType)(-1LL); \ else \ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ return (insn & fieldMask) >> startBit; \ } +static bool Check(DecodeStatus *Out, const DecodeStatus In) { + *Out = (DecodeStatus) (*Out & In); + return *Out != MCDisassembler_Fail; +} + static const uint8_t DecoderTable16[] = { /* 0 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... -/* 3 */ MCD_OPC_FilterValue, 1, 84, 0, // Skip to: 91 -/* 7 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... -/* 10 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 18 -/* 14 */ MCD_OPC_Decode, 149, 14, 0, // Opcode: PR -/* 18 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 26 -/* 22 */ MCD_OPC_Decode, 209, 16, 0, // Opcode: UPT -/* 26 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 34 -/* 30 */ MCD_OPC_Decode, 153, 14, 0, // Opcode: PTFF -/* 34 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 42 -/* 38 */ MCD_OPC_Decode, 189, 14, 0, // Opcode: SCKPF -/* 42 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 50 -/* 46 */ MCD_OPC_Decode, 140, 14, 0, // Opcode: PFPO -/* 50 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 58 -/* 54 */ MCD_OPC_Decode, 156, 16, 0, // Opcode: TAM -/* 58 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 66 -/* 62 */ MCD_OPC_Decode, 181, 14, 0, // Opcode: SAM24 -/* 66 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 74 -/* 70 */ MCD_OPC_Decode, 182, 14, 0, // Opcode: SAM31 -/* 74 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 82 -/* 78 */ MCD_OPC_Decode, 183, 14, 0, // Opcode: SAM64 -/* 82 */ MCD_OPC_FilterValue, 255, 1, 85, 2, // Skip to: 684 -/* 87 */ MCD_OPC_Decode, 187, 16, 0, // Opcode: TRAP2 -/* 91 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 105 -/* 95 */ MCD_OPC_CheckField, 0, 4, 0, 71, 2, // Skip to: 684 -/* 101 */ MCD_OPC_Decode, 245, 14, 1, // Opcode: SPM -/* 105 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 113 -/* 109 */ MCD_OPC_Decode, 168, 3, 2, // Opcode: BALR -/* 113 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 121 -/* 117 */ MCD_OPC_Decode, 199, 3, 3, // Opcode: BCTR -/* 121 */ MCD_OPC_FilterValue, 7, 127, 0, // Skip to: 252 -/* 125 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... -/* 128 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 136 -/* 132 */ MCD_OPC_Decode, 245, 3, 4, // Opcode: BRAsmO -/* 136 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 144 -/* 140 */ MCD_OPC_Decode, 229, 3, 4, // Opcode: BRAsmH -/* 144 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 152 -/* 148 */ MCD_OPC_Decode, 239, 3, 4, // Opcode: BRAsmNLE -/* 152 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 160 -/* 156 */ MCD_OPC_Decode, 231, 3, 4, // Opcode: BRAsmL -/* 160 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 168 -/* 164 */ MCD_OPC_Decode, 237, 3, 4, // Opcode: BRAsmNHE -/* 168 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 176 -/* 172 */ MCD_OPC_Decode, 233, 3, 4, // Opcode: BRAsmLH -/* 176 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 184 -/* 180 */ MCD_OPC_Decode, 235, 3, 4, // Opcode: BRAsmNE -/* 184 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 192 -/* 188 */ MCD_OPC_Decode, 228, 3, 4, // Opcode: BRAsmE -/* 192 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 200 -/* 196 */ MCD_OPC_Decode, 240, 3, 4, // Opcode: BRAsmNLH -/* 200 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 208 -/* 204 */ MCD_OPC_Decode, 230, 3, 4, // Opcode: BRAsmHE -/* 208 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 216 -/* 212 */ MCD_OPC_Decode, 238, 3, 4, // Opcode: BRAsmNL -/* 216 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 224 -/* 220 */ MCD_OPC_Decode, 232, 3, 4, // Opcode: BRAsmLE -/* 224 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 232 -/* 228 */ MCD_OPC_Decode, 236, 3, 4, // Opcode: BRAsmNH -/* 232 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 240 -/* 236 */ MCD_OPC_Decode, 242, 3, 4, // Opcode: BRAsmNO -/* 240 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 248 -/* 244 */ MCD_OPC_Decode, 225, 3, 4, // Opcode: BR -/* 248 */ MCD_OPC_Decode, 195, 3, 5, // Opcode: BCRAsm -/* 252 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 260 -/* 256 */ MCD_OPC_Decode, 147, 16, 6, // Opcode: SVC -/* 260 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 268 -/* 264 */ MCD_OPC_Decode, 133, 4, 2, // Opcode: BSM -/* 268 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 276 -/* 272 */ MCD_OPC_Decode, 171, 3, 2, // Opcode: BASSM -/* 276 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 284 -/* 280 */ MCD_OPC_Decode, 170, 3, 2, // Opcode: BASR -/* 284 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 292 -/* 288 */ MCD_OPC_Decode, 195, 13, 7, // Opcode: MVCL -/* 292 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 300 -/* 296 */ MCD_OPC_Decode, 226, 5, 7, // Opcode: CLCL -/* 300 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 308 -/* 304 */ MCD_OPC_Decode, 196, 12, 8, // Opcode: LPR -/* 308 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 316 -/* 312 */ MCD_OPC_Decode, 238, 10, 8, // Opcode: LNR -/* 316 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 324 -/* 320 */ MCD_OPC_Decode, 227, 12, 8, // Opcode: LTR -/* 324 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 332 -/* 328 */ MCD_OPC_Decode, 141, 10, 8, // Opcode: LCR -/* 332 */ MCD_OPC_FilterValue, 20, 4, 0, // Skip to: 340 -/* 336 */ MCD_OPC_Decode, 240, 13, 9, // Opcode: NR -/* 340 */ MCD_OPC_FilterValue, 21, 4, 0, // Skip to: 348 -/* 344 */ MCD_OPC_Decode, 145, 7, 8, // Opcode: CLR -/* 348 */ MCD_OPC_FilterValue, 22, 4, 0, // Skip to: 356 -/* 352 */ MCD_OPC_Decode, 129, 14, 9, // Opcode: OR -/* 356 */ MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 364 -/* 360 */ MCD_OPC_Decode, 235, 21, 9, // Opcode: XR -/* 364 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 372 -/* 368 */ MCD_OPC_Decode, 202, 12, 8, // Opcode: LR -/* 372 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 380 -/* 376 */ MCD_OPC_Decode, 214, 7, 8, // Opcode: CR -/* 380 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 388 -/* 384 */ MCD_OPC_Decode, 153, 3, 9, // Opcode: AR -/* 388 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 396 -/* 392 */ MCD_OPC_Decode, 130, 15, 9, // Opcode: SR -/* 396 */ MCD_OPC_FilterValue, 28, 4, 0, // Skip to: 404 -/* 400 */ MCD_OPC_Decode, 167, 13, 10, // Opcode: MR -/* 404 */ MCD_OPC_FilterValue, 29, 4, 0, // Skip to: 412 -/* 408 */ MCD_OPC_Decode, 206, 8, 10, // Opcode: DR -/* 412 */ MCD_OPC_FilterValue, 30, 4, 0, // Skip to: 420 -/* 416 */ MCD_OPC_Decode, 146, 3, 9, // Opcode: ALR -/* 420 */ MCD_OPC_FilterValue, 31, 4, 0, // Skip to: 428 -/* 424 */ MCD_OPC_Decode, 238, 14, 9, // Opcode: SLR -/* 428 */ MCD_OPC_FilterValue, 32, 4, 0, // Skip to: 436 -/* 432 */ MCD_OPC_Decode, 189, 12, 11, // Opcode: LPDR -/* 436 */ MCD_OPC_FilterValue, 33, 4, 0, // Skip to: 444 -/* 440 */ MCD_OPC_Decode, 233, 10, 11, // Opcode: LNDR -/* 444 */ MCD_OPC_FilterValue, 34, 4, 0, // Skip to: 452 -/* 448 */ MCD_OPC_Decode, 218, 12, 11, // Opcode: LTDR -/* 452 */ MCD_OPC_FilterValue, 35, 4, 0, // Skip to: 460 -/* 456 */ MCD_OPC_Decode, 136, 10, 11, // Opcode: LCDR -/* 460 */ MCD_OPC_FilterValue, 36, 4, 0, // Skip to: 468 -/* 464 */ MCD_OPC_Decode, 252, 8, 11, // Opcode: HDR -/* 468 */ MCD_OPC_FilterValue, 37, 4, 0, // Skip to: 476 -/* 472 */ MCD_OPC_Decode, 158, 10, 12, // Opcode: LDXR -/* 476 */ MCD_OPC_FilterValue, 38, 4, 0, // Skip to: 484 -/* 480 */ MCD_OPC_Decode, 217, 13, 13, // Opcode: MXR -/* 484 */ MCD_OPC_FilterValue, 39, 4, 0, // Skip to: 492 -/* 488 */ MCD_OPC_Decode, 216, 13, 14, // Opcode: MXDR -/* 492 */ MCD_OPC_FilterValue, 40, 4, 0, // Skip to: 500 -/* 496 */ MCD_OPC_Decode, 154, 10, 11, // Opcode: LDR -/* 500 */ MCD_OPC_FilterValue, 41, 4, 0, // Skip to: 508 -/* 504 */ MCD_OPC_Decode, 156, 4, 11, // Opcode: CDR -/* 508 */ MCD_OPC_FilterValue, 42, 4, 0, // Skip to: 516 -/* 512 */ MCD_OPC_Decode, 232, 2, 15, // Opcode: ADR -/* 516 */ MCD_OPC_FilterValue, 43, 4, 0, // Skip to: 524 -/* 520 */ MCD_OPC_Decode, 193, 14, 15, // Opcode: SDR -/* 524 */ MCD_OPC_FilterValue, 44, 4, 0, // Skip to: 532 -/* 528 */ MCD_OPC_Decode, 145, 13, 15, // Opcode: MDR -/* 532 */ MCD_OPC_FilterValue, 45, 4, 0, // Skip to: 540 -/* 536 */ MCD_OPC_Decode, 191, 8, 15, // Opcode: DDR -/* 540 */ MCD_OPC_FilterValue, 46, 4, 0, // Skip to: 548 -/* 544 */ MCD_OPC_Decode, 159, 3, 15, // Opcode: AWR -/* 548 */ MCD_OPC_FilterValue, 47, 4, 0, // Skip to: 556 -/* 552 */ MCD_OPC_Decode, 149, 16, 15, // Opcode: SWR -/* 556 */ MCD_OPC_FilterValue, 48, 4, 0, // Skip to: 564 -/* 560 */ MCD_OPC_Decode, 191, 12, 16, // Opcode: LPER -/* 564 */ MCD_OPC_FilterValue, 49, 4, 0, // Skip to: 572 -/* 568 */ MCD_OPC_Decode, 235, 10, 16, // Opcode: LNER -/* 572 */ MCD_OPC_FilterValue, 50, 4, 0, // Skip to: 580 -/* 576 */ MCD_OPC_Decode, 222, 12, 16, // Opcode: LTER -/* 580 */ MCD_OPC_FilterValue, 51, 4, 0, // Skip to: 588 -/* 584 */ MCD_OPC_Decode, 138, 10, 16, // Opcode: LCER -/* 588 */ MCD_OPC_FilterValue, 52, 4, 0, // Skip to: 596 -/* 592 */ MCD_OPC_Decode, 253, 8, 16, // Opcode: HER -/* 596 */ MCD_OPC_FilterValue, 53, 4, 0, // Skip to: 604 -/* 600 */ MCD_OPC_Decode, 164, 10, 17, // Opcode: LEDR -/* 604 */ MCD_OPC_FilterValue, 54, 4, 0, // Skip to: 612 -/* 608 */ MCD_OPC_Decode, 161, 3, 13, // Opcode: AXR -/* 612 */ MCD_OPC_FilterValue, 55, 4, 0, // Skip to: 620 -/* 616 */ MCD_OPC_Decode, 151, 16, 13, // Opcode: SXR -/* 620 */ MCD_OPC_FilterValue, 56, 4, 0, // Skip to: 628 -/* 624 */ MCD_OPC_Decode, 166, 10, 16, // Opcode: LER -/* 628 */ MCD_OPC_FilterValue, 57, 4, 0, // Skip to: 636 -/* 632 */ MCD_OPC_Decode, 176, 4, 16, // Opcode: CER -/* 636 */ MCD_OPC_FilterValue, 58, 4, 0, // Skip to: 644 -/* 640 */ MCD_OPC_Decode, 238, 2, 18, // Opcode: AER -/* 644 */ MCD_OPC_FilterValue, 59, 4, 0, // Skip to: 652 -/* 648 */ MCD_OPC_Decode, 199, 14, 18, // Opcode: SER -/* 652 */ MCD_OPC_FilterValue, 60, 4, 0, // Skip to: 660 -/* 656 */ MCD_OPC_Decode, 144, 13, 19, // Opcode: MDER -/* 660 */ MCD_OPC_FilterValue, 61, 4, 0, // Skip to: 668 -/* 664 */ MCD_OPC_Decode, 197, 8, 18, // Opcode: DER -/* 668 */ MCD_OPC_FilterValue, 62, 4, 0, // Skip to: 676 -/* 672 */ MCD_OPC_Decode, 157, 3, 18, // Opcode: AUR -/* 676 */ MCD_OPC_FilterValue, 63, 4, 0, // Skip to: 684 -/* 680 */ MCD_OPC_Decode, 146, 16, 18, // Opcode: SUR -/* 684 */ MCD_OPC_Fail, +/* 3 */ MCD_OPC_FilterValue, 1, 94, 0, 0, // Skip to: 102 +/* 8 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 11 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 20 +/* 16 */ MCD_OPC_Decode, 179, 15, 0, // Opcode: PR +/* 20 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 29 +/* 25 */ MCD_OPC_Decode, 182, 18, 0, // Opcode: UPT +/* 29 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 38 +/* 34 */ MCD_OPC_Decode, 183, 15, 0, // Opcode: PTFF +/* 38 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 47 +/* 43 */ MCD_OPC_Decode, 222, 15, 0, // Opcode: SCKPF +/* 47 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 56 +/* 52 */ MCD_OPC_Decode, 169, 15, 0, // Opcode: PFPO +/* 56 */ MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 65 +/* 61 */ MCD_OPC_Decode, 129, 18, 0, // Opcode: TAM +/* 65 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 74 +/* 70 */ MCD_OPC_Decode, 214, 15, 0, // Opcode: SAM24 +/* 74 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 83 +/* 79 */ MCD_OPC_Decode, 215, 15, 0, // Opcode: SAM31 +/* 83 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 92 +/* 88 */ MCD_OPC_Decode, 216, 15, 0, // Opcode: SAM64 +/* 92 */ MCD_OPC_FilterValue, 255, 1, 159, 2, 0, // Skip to: 769 +/* 98 */ MCD_OPC_Decode, 160, 18, 0, // Opcode: TRAP2 +/* 102 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 118 +/* 107 */ MCD_OPC_CheckField, 0, 4, 0, 143, 2, 0, // Skip to: 769 +/* 114 */ MCD_OPC_Decode, 217, 16, 1, // Opcode: SPM +/* 118 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 127 +/* 123 */ MCD_OPC_Decode, 177, 4, 2, // Opcode: BALR +/* 127 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 136 +/* 132 */ MCD_OPC_Decode, 208, 4, 3, // Opcode: BCTR +/* 136 */ MCD_OPC_FilterValue, 7, 142, 0, 0, // Skip to: 283 +/* 141 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... +/* 144 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 153 +/* 149 */ MCD_OPC_Decode, 254, 4, 4, // Opcode: BRAsmO +/* 153 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 162 +/* 158 */ MCD_OPC_Decode, 238, 4, 4, // Opcode: BRAsmH +/* 162 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 171 +/* 167 */ MCD_OPC_Decode, 248, 4, 4, // Opcode: BRAsmNLE +/* 171 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 180 +/* 176 */ MCD_OPC_Decode, 240, 4, 4, // Opcode: BRAsmL +/* 180 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 189 +/* 185 */ MCD_OPC_Decode, 246, 4, 4, // Opcode: BRAsmNHE +/* 189 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 198 +/* 194 */ MCD_OPC_Decode, 242, 4, 4, // Opcode: BRAsmLH +/* 198 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 207 +/* 203 */ MCD_OPC_Decode, 244, 4, 4, // Opcode: BRAsmNE +/* 207 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 216 +/* 212 */ MCD_OPC_Decode, 237, 4, 4, // Opcode: BRAsmE +/* 216 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 225 +/* 221 */ MCD_OPC_Decode, 249, 4, 4, // Opcode: BRAsmNLH +/* 225 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 234 +/* 230 */ MCD_OPC_Decode, 239, 4, 4, // Opcode: BRAsmHE +/* 234 */ MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 243 +/* 239 */ MCD_OPC_Decode, 247, 4, 4, // Opcode: BRAsmNL +/* 243 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 252 +/* 248 */ MCD_OPC_Decode, 241, 4, 4, // Opcode: BRAsmLE +/* 252 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 261 +/* 257 */ MCD_OPC_Decode, 245, 4, 4, // Opcode: BRAsmNH +/* 261 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 270 +/* 266 */ MCD_OPC_Decode, 251, 4, 4, // Opcode: BRAsmNO +/* 270 */ MCD_OPC_FilterValue, 15, 4, 0, 0, // Skip to: 279 +/* 275 */ MCD_OPC_Decode, 234, 4, 4, // Opcode: BR +/* 279 */ MCD_OPC_Decode, 204, 4, 5, // Opcode: BCRAsm +/* 283 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 292 +/* 288 */ MCD_OPC_Decode, 248, 17, 6, // Opcode: SVC +/* 292 */ MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 301 +/* 297 */ MCD_OPC_Decode, 142, 5, 2, // Opcode: BSM +/* 301 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 310 +/* 306 */ MCD_OPC_Decode, 180, 4, 2, // Opcode: BASSM +/* 310 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 319 +/* 315 */ MCD_OPC_Decode, 179, 4, 2, // Opcode: BASR +/* 319 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 328 +/* 324 */ MCD_OPC_Decode, 211, 14, 7, // Opcode: MVCL +/* 328 */ MCD_OPC_FilterValue, 15, 4, 0, 0, // Skip to: 337 +/* 333 */ MCD_OPC_Decode, 235, 6, 7, // Opcode: CLCL +/* 337 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 346 +/* 342 */ MCD_OPC_Decode, 214, 13, 8, // Opcode: LPR +/* 346 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 355 +/* 351 */ MCD_OPC_Decode, 128, 12, 8, // Opcode: LNR +/* 355 */ MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 364 +/* 360 */ MCD_OPC_Decode, 244, 13, 8, // Opcode: LTR +/* 364 */ MCD_OPC_FilterValue, 19, 4, 0, 0, // Skip to: 373 +/* 369 */ MCD_OPC_Decode, 159, 11, 8, // Opcode: LCR +/* 373 */ MCD_OPC_FilterValue, 20, 4, 0, 0, // Skip to: 382 +/* 378 */ MCD_OPC_Decode, 137, 15, 9, // Opcode: NR +/* 382 */ MCD_OPC_FilterValue, 21, 4, 0, 0, // Skip to: 391 +/* 387 */ MCD_OPC_Decode, 154, 8, 8, // Opcode: CLR +/* 391 */ MCD_OPC_FilterValue, 22, 4, 0, 0, // Skip to: 400 +/* 396 */ MCD_OPC_Decode, 158, 15, 9, // Opcode: OR +/* 400 */ MCD_OPC_FilterValue, 23, 4, 0, 0, // Skip to: 409 +/* 405 */ MCD_OPC_Decode, 156, 24, 9, // Opcode: XR +/* 409 */ MCD_OPC_FilterValue, 24, 4, 0, 0, // Skip to: 418 +/* 414 */ MCD_OPC_Decode, 221, 13, 8, // Opcode: LR +/* 418 */ MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 427 +/* 423 */ MCD_OPC_Decode, 223, 8, 8, // Opcode: CR +/* 427 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 436 +/* 432 */ MCD_OPC_Decode, 162, 4, 9, // Opcode: AR +/* 436 */ MCD_OPC_FilterValue, 27, 4, 0, 0, // Skip to: 445 +/* 441 */ MCD_OPC_Decode, 230, 16, 9, // Opcode: SR +/* 445 */ MCD_OPC_FilterValue, 28, 4, 0, 0, // Skip to: 454 +/* 450 */ MCD_OPC_Decode, 183, 14, 10, // Opcode: MR +/* 454 */ MCD_OPC_FilterValue, 29, 4, 0, 0, // Skip to: 463 +/* 459 */ MCD_OPC_Decode, 216, 9, 10, // Opcode: DR +/* 463 */ MCD_OPC_FilterValue, 30, 4, 0, 0, // Skip to: 472 +/* 468 */ MCD_OPC_Decode, 155, 4, 9, // Opcode: ALR +/* 472 */ MCD_OPC_FilterValue, 31, 4, 0, 0, // Skip to: 481 +/* 477 */ MCD_OPC_Decode, 209, 16, 9, // Opcode: SLR +/* 481 */ MCD_OPC_FilterValue, 32, 4, 0, 0, // Skip to: 490 +/* 486 */ MCD_OPC_Decode, 207, 13, 11, // Opcode: LPDR +/* 490 */ MCD_OPC_FilterValue, 33, 4, 0, 0, // Skip to: 499 +/* 495 */ MCD_OPC_Decode, 251, 11, 11, // Opcode: LNDR +/* 499 */ MCD_OPC_FilterValue, 34, 4, 0, 0, // Skip to: 508 +/* 504 */ MCD_OPC_Decode, 236, 13, 11, // Opcode: LTDR +/* 508 */ MCD_OPC_FilterValue, 35, 4, 0, 0, // Skip to: 517 +/* 513 */ MCD_OPC_Decode, 154, 11, 11, // Opcode: LCDR +/* 517 */ MCD_OPC_FilterValue, 36, 4, 0, 0, // Skip to: 526 +/* 522 */ MCD_OPC_Decode, 134, 10, 11, // Opcode: HDR +/* 526 */ MCD_OPC_FilterValue, 37, 4, 0, 0, // Skip to: 535 +/* 531 */ MCD_OPC_Decode, 176, 11, 12, // Opcode: LDXR +/* 535 */ MCD_OPC_FilterValue, 38, 4, 0, 0, // Skip to: 544 +/* 540 */ MCD_OPC_Decode, 234, 14, 13, // Opcode: MXR +/* 544 */ MCD_OPC_FilterValue, 39, 4, 0, 0, // Skip to: 553 +/* 549 */ MCD_OPC_Decode, 233, 14, 14, // Opcode: MXDR +/* 553 */ MCD_OPC_FilterValue, 40, 4, 0, 0, // Skip to: 562 +/* 558 */ MCD_OPC_Decode, 172, 11, 11, // Opcode: LDR +/* 562 */ MCD_OPC_FilterValue, 41, 4, 0, 0, // Skip to: 571 +/* 567 */ MCD_OPC_Decode, 165, 5, 11, // Opcode: CDR +/* 571 */ MCD_OPC_FilterValue, 42, 4, 0, 0, // Skip to: 580 +/* 576 */ MCD_OPC_Decode, 241, 3, 15, // Opcode: ADR +/* 580 */ MCD_OPC_FilterValue, 43, 4, 0, 0, // Skip to: 589 +/* 585 */ MCD_OPC_Decode, 226, 15, 15, // Opcode: SDR +/* 589 */ MCD_OPC_FilterValue, 44, 4, 0, 0, // Skip to: 598 +/* 594 */ MCD_OPC_Decode, 161, 14, 15, // Opcode: MDR +/* 598 */ MCD_OPC_FilterValue, 45, 4, 0, 0, // Skip to: 607 +/* 603 */ MCD_OPC_Decode, 200, 9, 15, // Opcode: DDR +/* 607 */ MCD_OPC_FilterValue, 46, 4, 0, 0, // Skip to: 616 +/* 612 */ MCD_OPC_Decode, 168, 4, 15, // Opcode: AWR +/* 616 */ MCD_OPC_FilterValue, 47, 4, 0, 0, // Skip to: 625 +/* 621 */ MCD_OPC_Decode, 250, 17, 15, // Opcode: SWR +/* 625 */ MCD_OPC_FilterValue, 48, 4, 0, 0, // Skip to: 634 +/* 630 */ MCD_OPC_Decode, 209, 13, 16, // Opcode: LPER +/* 634 */ MCD_OPC_FilterValue, 49, 4, 0, 0, // Skip to: 643 +/* 639 */ MCD_OPC_Decode, 253, 11, 16, // Opcode: LNER +/* 643 */ MCD_OPC_FilterValue, 50, 4, 0, 0, // Skip to: 652 +/* 648 */ MCD_OPC_Decode, 239, 13, 16, // Opcode: LTER +/* 652 */ MCD_OPC_FilterValue, 51, 4, 0, 0, // Skip to: 661 +/* 657 */ MCD_OPC_Decode, 156, 11, 16, // Opcode: LCER +/* 661 */ MCD_OPC_FilterValue, 52, 4, 0, 0, // Skip to: 670 +/* 666 */ MCD_OPC_Decode, 135, 10, 16, // Opcode: HER +/* 670 */ MCD_OPC_FilterValue, 53, 4, 0, 0, // Skip to: 679 +/* 675 */ MCD_OPC_Decode, 182, 11, 17, // Opcode: LEDR +/* 679 */ MCD_OPC_FilterValue, 54, 4, 0, 0, // Skip to: 688 +/* 684 */ MCD_OPC_Decode, 170, 4, 13, // Opcode: AXR +/* 688 */ MCD_OPC_FilterValue, 55, 4, 0, 0, // Skip to: 697 +/* 693 */ MCD_OPC_Decode, 252, 17, 13, // Opcode: SXR +/* 697 */ MCD_OPC_FilterValue, 56, 4, 0, 0, // Skip to: 706 +/* 702 */ MCD_OPC_Decode, 184, 11, 16, // Opcode: LER +/* 706 */ MCD_OPC_FilterValue, 57, 4, 0, 0, // Skip to: 715 +/* 711 */ MCD_OPC_Decode, 185, 5, 16, // Opcode: CER +/* 715 */ MCD_OPC_FilterValue, 58, 4, 0, 0, // Skip to: 724 +/* 720 */ MCD_OPC_Decode, 247, 3, 18, // Opcode: AER +/* 724 */ MCD_OPC_FilterValue, 59, 4, 0, 0, // Skip to: 733 +/* 729 */ MCD_OPC_Decode, 170, 16, 18, // Opcode: SER +/* 733 */ MCD_OPC_FilterValue, 60, 4, 0, 0, // Skip to: 742 +/* 738 */ MCD_OPC_Decode, 160, 14, 19, // Opcode: MDER +/* 742 */ MCD_OPC_FilterValue, 61, 4, 0, 0, // Skip to: 751 +/* 747 */ MCD_OPC_Decode, 206, 9, 18, // Opcode: DER +/* 751 */ MCD_OPC_FilterValue, 62, 4, 0, 0, // Skip to: 760 +/* 756 */ MCD_OPC_Decode, 166, 4, 18, // Opcode: AUR +/* 760 */ MCD_OPC_FilterValue, 63, 4, 0, 0, // Skip to: 769 +/* 765 */ MCD_OPC_Decode, 247, 17, 18, // Opcode: SUR +/* 769 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTable32[] = { /* 0 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 3 */ MCD_OPC_FilterValue, 64, 4, 0, // Skip to: 11 -/* 7 */ MCD_OPC_Decode, 183, 15, 20, // Opcode: STH -/* 11 */ MCD_OPC_FilterValue, 65, 4, 0, // Skip to: 19 -/* 15 */ MCD_OPC_Decode, 237, 9, 21, // Opcode: LA -/* 19 */ MCD_OPC_FilterValue, 66, 4, 0, // Skip to: 27 -/* 23 */ MCD_OPC_Decode, 158, 15, 20, // Opcode: STC -/* 27 */ MCD_OPC_FilterValue, 67, 4, 0, // Skip to: 35 -/* 31 */ MCD_OPC_Decode, 128, 9, 22, // Opcode: IC -/* 35 */ MCD_OPC_FilterValue, 68, 4, 0, // Skip to: 43 -/* 39 */ MCD_OPC_Decode, 238, 8, 21, // Opcode: EX -/* 43 */ MCD_OPC_FilterValue, 69, 4, 0, // Skip to: 51 -/* 47 */ MCD_OPC_Decode, 167, 3, 21, // Opcode: BAL -/* 51 */ MCD_OPC_FilterValue, 70, 4, 0, // Skip to: 59 -/* 55 */ MCD_OPC_Decode, 196, 3, 23, // Opcode: BCT -/* 59 */ MCD_OPC_FilterValue, 71, 127, 0, // Skip to: 190 -/* 63 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 66 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 74 -/* 70 */ MCD_OPC_Decode, 189, 3, 24, // Opcode: BAsmO -/* 74 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 82 -/* 78 */ MCD_OPC_Decode, 173, 3, 24, // Opcode: BAsmH -/* 82 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 90 -/* 86 */ MCD_OPC_Decode, 183, 3, 24, // Opcode: BAsmNLE -/* 90 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 98 -/* 94 */ MCD_OPC_Decode, 175, 3, 24, // Opcode: BAsmL -/* 98 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 106 -/* 102 */ MCD_OPC_Decode, 181, 3, 24, // Opcode: BAsmNHE -/* 106 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 114 -/* 110 */ MCD_OPC_Decode, 177, 3, 24, // Opcode: BAsmLH -/* 114 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 122 -/* 118 */ MCD_OPC_Decode, 179, 3, 24, // Opcode: BAsmNE -/* 122 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 130 -/* 126 */ MCD_OPC_Decode, 172, 3, 24, // Opcode: BAsmE -/* 130 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 138 -/* 134 */ MCD_OPC_Decode, 184, 3, 24, // Opcode: BAsmNLH -/* 138 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 146 -/* 142 */ MCD_OPC_Decode, 174, 3, 24, // Opcode: BAsmHE -/* 146 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 154 -/* 150 */ MCD_OPC_Decode, 182, 3, 24, // Opcode: BAsmNL -/* 154 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 162 -/* 158 */ MCD_OPC_Decode, 176, 3, 24, // Opcode: BAsmLE -/* 162 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 170 -/* 166 */ MCD_OPC_Decode, 180, 3, 24, // Opcode: BAsmNH -/* 170 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 178 -/* 174 */ MCD_OPC_Decode, 186, 3, 24, // Opcode: BAsmNO -/* 178 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 186 -/* 182 */ MCD_OPC_Decode, 165, 3, 24, // Opcode: B -/* 186 */ MCD_OPC_Decode, 193, 3, 25, // Opcode: BCAsm -/* 190 */ MCD_OPC_FilterValue, 72, 4, 0, // Skip to: 198 -/* 194 */ MCD_OPC_Decode, 192, 10, 20, // Opcode: LH -/* 198 */ MCD_OPC_FilterValue, 73, 4, 0, // Skip to: 206 -/* 202 */ MCD_OPC_Decode, 171, 5, 20, // Opcode: CH -/* 206 */ MCD_OPC_FilterValue, 74, 4, 0, // Skip to: 214 -/* 210 */ MCD_OPC_Decode, 250, 2, 23, // Opcode: AH -/* 214 */ MCD_OPC_FilterValue, 75, 4, 0, // Skip to: 222 -/* 218 */ MCD_OPC_Decode, 208, 14, 23, // Opcode: SH -/* 222 */ MCD_OPC_FilterValue, 76, 4, 0, // Skip to: 230 -/* 226 */ MCD_OPC_Decode, 159, 13, 23, // Opcode: MH -/* 230 */ MCD_OPC_FilterValue, 77, 4, 0, // Skip to: 238 -/* 234 */ MCD_OPC_Decode, 169, 3, 21, // Opcode: BAS -/* 238 */ MCD_OPC_FilterValue, 78, 4, 0, // Skip to: 246 -/* 242 */ MCD_OPC_Decode, 161, 8, 20, // Opcode: CVD -/* 246 */ MCD_OPC_FilterValue, 79, 4, 0, // Skip to: 254 -/* 250 */ MCD_OPC_Decode, 158, 8, 23, // Opcode: CVB -/* 254 */ MCD_OPC_FilterValue, 80, 4, 0, // Skip to: 262 -/* 258 */ MCD_OPC_Decode, 154, 15, 20, // Opcode: ST -/* 262 */ MCD_OPC_FilterValue, 81, 4, 0, // Skip to: 270 -/* 266 */ MCD_OPC_Decode, 242, 9, 21, // Opcode: LAE -/* 270 */ MCD_OPC_FilterValue, 84, 4, 0, // Skip to: 278 -/* 274 */ MCD_OPC_Decode, 226, 13, 23, // Opcode: N -/* 278 */ MCD_OPC_FilterValue, 85, 4, 0, // Skip to: 286 -/* 282 */ MCD_OPC_Decode, 224, 5, 20, // Opcode: CL -/* 286 */ MCD_OPC_FilterValue, 86, 4, 0, // Skip to: 294 -/* 290 */ MCD_OPC_Decode, 244, 13, 23, // Opcode: O -/* 294 */ MCD_OPC_FilterValue, 87, 4, 0, // Skip to: 302 -/* 298 */ MCD_OPC_Decode, 226, 21, 23, // Opcode: X -/* 302 */ MCD_OPC_FilterValue, 88, 4, 0, // Skip to: 310 -/* 306 */ MCD_OPC_Decode, 236, 9, 20, // Opcode: L -/* 310 */ MCD_OPC_FilterValue, 89, 4, 0, // Skip to: 318 -/* 314 */ MCD_OPC_Decode, 138, 4, 20, // Opcode: C -/* 318 */ MCD_OPC_FilterValue, 90, 4, 0, // Skip to: 326 -/* 322 */ MCD_OPC_Decode, 228, 2, 23, // Opcode: A -/* 326 */ MCD_OPC_FilterValue, 91, 4, 0, // Skip to: 334 -/* 330 */ MCD_OPC_Decode, 177, 14, 23, // Opcode: S -/* 334 */ MCD_OPC_FilterValue, 92, 4, 0, // Skip to: 342 -/* 338 */ MCD_OPC_Decode, 250, 12, 26, // Opcode: M -/* 342 */ MCD_OPC_FilterValue, 93, 4, 0, // Skip to: 350 -/* 346 */ MCD_OPC_Decode, 187, 8, 26, // Opcode: D -/* 350 */ MCD_OPC_FilterValue, 94, 4, 0, // Skip to: 358 -/* 354 */ MCD_OPC_Decode, 129, 3, 23, // Opcode: AL -/* 358 */ MCD_OPC_FilterValue, 95, 4, 0, // Skip to: 366 -/* 362 */ MCD_OPC_Decode, 215, 14, 23, // Opcode: SL -/* 366 */ MCD_OPC_FilterValue, 96, 4, 0, // Skip to: 374 -/* 370 */ MCD_OPC_Decode, 172, 15, 27, // Opcode: STD -/* 374 */ MCD_OPC_FilterValue, 103, 4, 0, // Skip to: 382 -/* 378 */ MCD_OPC_Decode, 213, 13, 28, // Opcode: MXD -/* 382 */ MCD_OPC_FilterValue, 104, 4, 0, // Skip to: 390 -/* 386 */ MCD_OPC_Decode, 146, 10, 27, // Opcode: LD -/* 390 */ MCD_OPC_FilterValue, 105, 4, 0, // Skip to: 398 -/* 394 */ MCD_OPC_Decode, 139, 4, 27, // Opcode: CD -/* 398 */ MCD_OPC_FilterValue, 106, 4, 0, // Skip to: 406 -/* 402 */ MCD_OPC_Decode, 229, 2, 29, // Opcode: AD -/* 406 */ MCD_OPC_FilterValue, 107, 4, 0, // Skip to: 414 -/* 410 */ MCD_OPC_Decode, 190, 14, 29, // Opcode: SD -/* 414 */ MCD_OPC_FilterValue, 108, 4, 0, // Skip to: 422 -/* 418 */ MCD_OPC_Decode, 138, 13, 29, // Opcode: MD -/* 422 */ MCD_OPC_FilterValue, 109, 4, 0, // Skip to: 430 -/* 426 */ MCD_OPC_Decode, 188, 8, 29, // Opcode: DD -/* 430 */ MCD_OPC_FilterValue, 110, 4, 0, // Skip to: 438 -/* 434 */ MCD_OPC_Decode, 158, 3, 29, // Opcode: AW -/* 438 */ MCD_OPC_FilterValue, 111, 4, 0, // Skip to: 446 -/* 442 */ MCD_OPC_Decode, 148, 16, 29, // Opcode: SW -/* 446 */ MCD_OPC_FilterValue, 112, 4, 0, // Skip to: 454 -/* 450 */ MCD_OPC_Decode, 174, 15, 30, // Opcode: STE -/* 454 */ MCD_OPC_FilterValue, 113, 4, 0, // Skip to: 462 -/* 458 */ MCD_OPC_Decode, 168, 13, 23, // Opcode: MS -/* 462 */ MCD_OPC_FilterValue, 120, 4, 0, // Skip to: 470 -/* 466 */ MCD_OPC_Decode, 161, 10, 30, // Opcode: LE -/* 470 */ MCD_OPC_FilterValue, 121, 4, 0, // Skip to: 478 -/* 474 */ MCD_OPC_Decode, 164, 4, 30, // Opcode: CE -/* 478 */ MCD_OPC_FilterValue, 122, 4, 0, // Skip to: 486 -/* 482 */ MCD_OPC_Decode, 235, 2, 31, // Opcode: AE -/* 486 */ MCD_OPC_FilterValue, 123, 4, 0, // Skip to: 494 -/* 490 */ MCD_OPC_Decode, 196, 14, 31, // Opcode: SE -/* 494 */ MCD_OPC_FilterValue, 124, 4, 0, // Skip to: 502 -/* 498 */ MCD_OPC_Decode, 141, 13, 29, // Opcode: MDE -/* 502 */ MCD_OPC_FilterValue, 125, 4, 0, // Skip to: 510 -/* 506 */ MCD_OPC_Decode, 194, 8, 31, // Opcode: DE -/* 510 */ MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 518 -/* 514 */ MCD_OPC_Decode, 156, 3, 31, // Opcode: AU -/* 518 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 526 -/* 522 */ MCD_OPC_Decode, 145, 16, 31, // Opcode: SU -/* 526 */ MCD_OPC_FilterValue, 128, 1, 10, 0, // Skip to: 541 -/* 531 */ MCD_OPC_CheckField, 16, 8, 0, 67, 31, // Skip to: 8540 -/* 537 */ MCD_OPC_Decode, 153, 15, 32, // Opcode: SSM -/* 541 */ MCD_OPC_FilterValue, 130, 1, 10, 0, // Skip to: 556 -/* 546 */ MCD_OPC_CheckField, 16, 8, 0, 52, 31, // Skip to: 8540 -/* 552 */ MCD_OPC_Decode, 197, 12, 32, // Opcode: LPSW -/* 556 */ MCD_OPC_FilterValue, 131, 1, 4, 0, // Skip to: 565 -/* 561 */ MCD_OPC_Decode, 198, 8, 33, // Opcode: DIAG -/* 565 */ MCD_OPC_FilterValue, 132, 1, 4, 0, // Skip to: 574 -/* 570 */ MCD_OPC_Decode, 255, 3, 34, // Opcode: BRXH -/* 574 */ MCD_OPC_FilterValue, 133, 1, 4, 0, // Skip to: 583 -/* 579 */ MCD_OPC_Decode, 129, 4, 34, // Opcode: BRXLE -/* 583 */ MCD_OPC_FilterValue, 134, 1, 4, 0, // Skip to: 592 -/* 588 */ MCD_OPC_Decode, 134, 4, 35, // Opcode: BXH -/* 592 */ MCD_OPC_FilterValue, 135, 1, 4, 0, // Skip to: 601 -/* 597 */ MCD_OPC_Decode, 136, 4, 35, // Opcode: BXLE -/* 601 */ MCD_OPC_FilterValue, 136, 1, 10, 0, // Skip to: 616 -/* 606 */ MCD_OPC_CheckField, 16, 4, 0, 248, 30, // Skip to: 8540 -/* 612 */ MCD_OPC_Decode, 138, 15, 36, // Opcode: SRL -/* 616 */ MCD_OPC_FilterValue, 137, 1, 10, 0, // Skip to: 631 -/* 621 */ MCD_OPC_CheckField, 16, 4, 0, 233, 30, // Skip to: 8540 -/* 627 */ MCD_OPC_Decode, 235, 14, 36, // Opcode: SLL -/* 631 */ MCD_OPC_FilterValue, 138, 1, 10, 0, // Skip to: 646 -/* 636 */ MCD_OPC_CheckField, 16, 4, 0, 218, 30, // Skip to: 8540 -/* 642 */ MCD_OPC_Decode, 131, 15, 36, // Opcode: SRA -/* 646 */ MCD_OPC_FilterValue, 139, 1, 10, 0, // Skip to: 661 -/* 651 */ MCD_OPC_CheckField, 16, 4, 0, 203, 30, // Skip to: 8540 -/* 657 */ MCD_OPC_Decode, 216, 14, 36, // Opcode: SLA -/* 661 */ MCD_OPC_FilterValue, 140, 1, 10, 0, // Skip to: 676 -/* 666 */ MCD_OPC_CheckField, 16, 4, 0, 188, 30, // Skip to: 8540 -/* 672 */ MCD_OPC_Decode, 135, 15, 37, // Opcode: SRDL -/* 676 */ MCD_OPC_FilterValue, 141, 1, 10, 0, // Skip to: 691 -/* 681 */ MCD_OPC_CheckField, 16, 4, 0, 173, 30, // Skip to: 8540 -/* 687 */ MCD_OPC_Decode, 224, 14, 37, // Opcode: SLDL -/* 691 */ MCD_OPC_FilterValue, 142, 1, 10, 0, // Skip to: 706 -/* 696 */ MCD_OPC_CheckField, 16, 4, 0, 158, 30, // Skip to: 8540 -/* 702 */ MCD_OPC_Decode, 134, 15, 37, // Opcode: SRDA -/* 706 */ MCD_OPC_FilterValue, 143, 1, 10, 0, // Skip to: 721 -/* 711 */ MCD_OPC_CheckField, 16, 4, 0, 143, 30, // Skip to: 8540 -/* 717 */ MCD_OPC_Decode, 223, 14, 37, // Opcode: SLDA -/* 721 */ MCD_OPC_FilterValue, 144, 1, 4, 0, // Skip to: 730 -/* 726 */ MCD_OPC_Decode, 188, 15, 33, // Opcode: STM -/* 730 */ MCD_OPC_FilterValue, 145, 1, 4, 0, // Skip to: 739 -/* 735 */ MCD_OPC_Decode, 175, 16, 38, // Opcode: TM -/* 739 */ MCD_OPC_FilterValue, 146, 1, 4, 0, // Skip to: 748 -/* 744 */ MCD_OPC_Decode, 205, 13, 38, // Opcode: MVI -/* 748 */ MCD_OPC_FilterValue, 147, 1, 10, 0, // Skip to: 763 -/* 753 */ MCD_OPC_CheckField, 16, 8, 0, 101, 30, // Skip to: 8540 -/* 759 */ MCD_OPC_Decode, 204, 16, 32, // Opcode: TS -/* 763 */ MCD_OPC_FilterValue, 148, 1, 4, 0, // Skip to: 772 -/* 768 */ MCD_OPC_Decode, 231, 13, 38, // Opcode: NI -/* 772 */ MCD_OPC_FilterValue, 149, 1, 4, 0, // Skip to: 781 -/* 777 */ MCD_OPC_Decode, 239, 6, 38, // Opcode: CLI -/* 781 */ MCD_OPC_FilterValue, 150, 1, 4, 0, // Skip to: 790 -/* 786 */ MCD_OPC_Decode, 249, 13, 38, // Opcode: OI -/* 790 */ MCD_OPC_FilterValue, 151, 1, 4, 0, // Skip to: 799 -/* 795 */ MCD_OPC_Decode, 231, 21, 38, // Opcode: XI -/* 799 */ MCD_OPC_FilterValue, 152, 1, 4, 0, // Skip to: 808 -/* 804 */ MCD_OPC_Decode, 225, 10, 33, // Opcode: LM -/* 808 */ MCD_OPC_FilterValue, 153, 1, 4, 0, // Skip to: 817 -/* 813 */ MCD_OPC_Decode, 185, 16, 33, // Opcode: TRACE -/* 817 */ MCD_OPC_FilterValue, 154, 1, 4, 0, // Skip to: 826 -/* 822 */ MCD_OPC_Decode, 244, 9, 39, // Opcode: LAM -/* 826 */ MCD_OPC_FilterValue, 155, 1, 4, 0, // Skip to: 835 -/* 831 */ MCD_OPC_Decode, 155, 15, 39, // Opcode: STAM -/* 835 */ MCD_OPC_FilterValue, 165, 1, 131, 0, // Skip to: 971 -/* 840 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 843 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 851 -/* 847 */ MCD_OPC_Decode, 140, 9, 40, // Opcode: IIHH -/* 851 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 859 -/* 855 */ MCD_OPC_Decode, 141, 9, 40, // Opcode: IIHL -/* 859 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 867 -/* 863 */ MCD_OPC_Decode, 143, 9, 41, // Opcode: IILH -/* 867 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 875 -/* 871 */ MCD_OPC_Decode, 144, 9, 41, // Opcode: IILL -/* 875 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 883 -/* 879 */ MCD_OPC_Decode, 234, 13, 40, // Opcode: NIHH -/* 883 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 891 -/* 887 */ MCD_OPC_Decode, 235, 13, 40, // Opcode: NIHL -/* 891 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 899 -/* 895 */ MCD_OPC_Decode, 237, 13, 41, // Opcode: NILH -/* 899 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 907 -/* 903 */ MCD_OPC_Decode, 238, 13, 41, // Opcode: NILL -/* 907 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 915 -/* 911 */ MCD_OPC_Decode, 251, 13, 40, // Opcode: OIHH -/* 915 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 923 -/* 919 */ MCD_OPC_Decode, 252, 13, 40, // Opcode: OIHL -/* 923 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 931 -/* 927 */ MCD_OPC_Decode, 254, 13, 41, // Opcode: OILH -/* 931 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 939 -/* 935 */ MCD_OPC_Decode, 255, 13, 41, // Opcode: OILL -/* 939 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 947 -/* 943 */ MCD_OPC_Decode, 219, 10, 42, // Opcode: LLIHH -/* 947 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 955 -/* 951 */ MCD_OPC_Decode, 220, 10, 42, // Opcode: LLIHL -/* 955 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 963 -/* 959 */ MCD_OPC_Decode, 222, 10, 42, // Opcode: LLILH -/* 963 */ MCD_OPC_FilterValue, 15, 149, 29, // Skip to: 8540 -/* 967 */ MCD_OPC_Decode, 223, 10, 42, // Opcode: LLILL -/* 971 */ MCD_OPC_FilterValue, 167, 1, 254, 0, // Skip to: 1230 -/* 976 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 979 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 987 -/* 983 */ MCD_OPC_Decode, 178, 16, 43, // Opcode: TMLH -/* 987 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 995 -/* 991 */ MCD_OPC_Decode, 179, 16, 43, // Opcode: TMLL -/* 995 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1003 -/* 999 */ MCD_OPC_Decode, 176, 16, 44, // Opcode: TMHH -/* 1003 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1011 -/* 1007 */ MCD_OPC_Decode, 177, 16, 44, // Opcode: TMHL -/* 1011 */ MCD_OPC_FilterValue, 4, 127, 0, // Skip to: 1142 -/* 1015 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 1018 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1026 -/* 1022 */ MCD_OPC_Decode, 196, 9, 45, // Opcode: JAsmO -/* 1026 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1034 -/* 1030 */ MCD_OPC_Decode, 180, 9, 45, // Opcode: JAsmH -/* 1034 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1042 -/* 1038 */ MCD_OPC_Decode, 190, 9, 45, // Opcode: JAsmNLE -/* 1042 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1050 -/* 1046 */ MCD_OPC_Decode, 182, 9, 45, // Opcode: JAsmL -/* 1050 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1058 -/* 1054 */ MCD_OPC_Decode, 188, 9, 45, // Opcode: JAsmNHE -/* 1058 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 1066 -/* 1062 */ MCD_OPC_Decode, 184, 9, 45, // Opcode: JAsmLH -/* 1066 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 1074 -/* 1070 */ MCD_OPC_Decode, 186, 9, 45, // Opcode: JAsmNE -/* 1074 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 1082 -/* 1078 */ MCD_OPC_Decode, 179, 9, 45, // Opcode: JAsmE -/* 1082 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 1090 -/* 1086 */ MCD_OPC_Decode, 191, 9, 45, // Opcode: JAsmNLH -/* 1090 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 1098 -/* 1094 */ MCD_OPC_Decode, 181, 9, 45, // Opcode: JAsmHE -/* 1098 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 1106 -/* 1102 */ MCD_OPC_Decode, 189, 9, 45, // Opcode: JAsmNL -/* 1106 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 1114 -/* 1110 */ MCD_OPC_Decode, 183, 9, 45, // Opcode: JAsmLE -/* 1114 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 1122 -/* 1118 */ MCD_OPC_Decode, 187, 9, 45, // Opcode: JAsmNH -/* 1122 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 1130 -/* 1126 */ MCD_OPC_Decode, 193, 9, 45, // Opcode: JAsmNO -/* 1130 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 1138 -/* 1134 */ MCD_OPC_Decode, 178, 9, 45, // Opcode: J -/* 1138 */ MCD_OPC_Decode, 249, 3, 46, // Opcode: BRCAsm -/* 1142 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1150 -/* 1146 */ MCD_OPC_Decode, 226, 3, 47, // Opcode: BRAS -/* 1150 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 1158 -/* 1154 */ MCD_OPC_Decode, 252, 3, 48, // Opcode: BRCT -/* 1158 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 1166 -/* 1162 */ MCD_OPC_Decode, 253, 3, 49, // Opcode: BRCTG -/* 1166 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 1174 -/* 1170 */ MCD_OPC_Decode, 194, 10, 50, // Opcode: LHI -/* 1174 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 1182 -/* 1178 */ MCD_OPC_Decode, 186, 10, 51, // Opcode: LGHI -/* 1182 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 1190 -/* 1186 */ MCD_OPC_Decode, 253, 2, 52, // Opcode: AHI -/* 1190 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 1198 -/* 1194 */ MCD_OPC_Decode, 245, 2, 53, // Opcode: AGHI -/* 1198 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 1206 -/* 1202 */ MCD_OPC_Decode, 160, 13, 52, // Opcode: MHI -/* 1206 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 1214 -/* 1210 */ MCD_OPC_Decode, 157, 13, 53, // Opcode: MGHI -/* 1214 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 1222 -/* 1218 */ MCD_OPC_Decode, 175, 5, 50, // Opcode: CHI -/* 1222 */ MCD_OPC_FilterValue, 15, 146, 28, // Skip to: 8540 -/* 1226 */ MCD_OPC_Decode, 205, 4, 51, // Opcode: CGHI -/* 1230 */ MCD_OPC_FilterValue, 168, 1, 4, 0, // Skip to: 1239 -/* 1235 */ MCD_OPC_Decode, 196, 13, 54, // Opcode: MVCLE -/* 1239 */ MCD_OPC_FilterValue, 169, 1, 4, 0, // Skip to: 1248 -/* 1244 */ MCD_OPC_Decode, 227, 5, 54, // Opcode: CLCLE -/* 1248 */ MCD_OPC_FilterValue, 172, 1, 4, 0, // Skip to: 1257 -/* 1253 */ MCD_OPC_Decode, 192, 15, 38, // Opcode: STNSM -/* 1257 */ MCD_OPC_FilterValue, 173, 1, 4, 0, // Skip to: 1266 -/* 1262 */ MCD_OPC_Decode, 131, 16, 38, // Opcode: STOSM -/* 1266 */ MCD_OPC_FilterValue, 174, 1, 4, 0, // Skip to: 1275 -/* 1271 */ MCD_OPC_Decode, 214, 14, 55, // Opcode: SIGP -/* 1275 */ MCD_OPC_FilterValue, 175, 1, 4, 0, // Skip to: 1284 -/* 1280 */ MCD_OPC_Decode, 137, 13, 38, // Opcode: MC -/* 1284 */ MCD_OPC_FilterValue, 177, 1, 4, 0, // Skip to: 1293 -/* 1289 */ MCD_OPC_Decode, 203, 12, 21, // Opcode: LRA -/* 1293 */ MCD_OPC_FilterValue, 178, 1, 65, 5, // Skip to: 2643 -/* 1298 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 1301 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1309 -/* 1305 */ MCD_OPC_Decode, 187, 15, 32, // Opcode: STIDP -/* 1309 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1317 -/* 1313 */ MCD_OPC_Decode, 187, 14, 32, // Opcode: SCK -/* 1317 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1325 -/* 1321 */ MCD_OPC_Decode, 160, 15, 32, // Opcode: STCK -/* 1325 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 1333 -/* 1329 */ MCD_OPC_Decode, 188, 14, 32, // Opcode: SCKC -/* 1333 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 1341 -/* 1337 */ MCD_OPC_Decode, 161, 15, 32, // Opcode: STCKC -/* 1341 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 1349 -/* 1345 */ MCD_OPC_Decode, 246, 14, 32, // Opcode: SPT -/* 1349 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 1357 -/* 1353 */ MCD_OPC_Decode, 133, 16, 32, // Opcode: STPT -/* 1357 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 1365 -/* 1361 */ MCD_OPC_Decode, 244, 14, 32, // Opcode: SPKA -/* 1365 */ MCD_OPC_FilterValue, 11, 10, 0, // Skip to: 1379 -/* 1369 */ MCD_OPC_CheckField, 0, 16, 0, 253, 27, // Skip to: 8540 -/* 1375 */ MCD_OPC_Decode, 145, 9, 0, // Opcode: IPK -/* 1379 */ MCD_OPC_FilterValue, 13, 10, 0, // Skip to: 1393 -/* 1383 */ MCD_OPC_CheckField, 0, 16, 0, 239, 27, // Skip to: 8540 -/* 1389 */ MCD_OPC_Decode, 155, 14, 0, // Opcode: PTLB -/* 1393 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 1401 -/* 1397 */ MCD_OPC_Decode, 247, 14, 32, // Opcode: SPX -/* 1401 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 1409 -/* 1405 */ MCD_OPC_Decode, 134, 16, 32, // Opcode: STPX -/* 1409 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 1417 -/* 1413 */ MCD_OPC_Decode, 157, 15, 32, // Opcode: STAP -/* 1417 */ MCD_OPC_FilterValue, 20, 4, 0, // Skip to: 1425 -/* 1421 */ MCD_OPC_Decode, 212, 14, 32, // Opcode: SIE -/* 1425 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1433 -/* 1429 */ MCD_OPC_Decode, 134, 14, 32, // Opcode: PC -/* 1433 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1441 -/* 1437 */ MCD_OPC_Decode, 178, 14, 32, // Opcode: SAC -/* 1441 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1449 -/* 1445 */ MCD_OPC_Decode, 178, 4, 32, // Opcode: CFC -/* 1449 */ MCD_OPC_FilterValue, 33, 24, 0, // Skip to: 1477 -/* 1453 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 1463 -/* 1459 */ MCD_OPC_Decode, 149, 9, 56, // Opcode: IPTEOptOpt -/* 1463 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 1473 -/* 1469 */ MCD_OPC_Decode, 148, 9, 57, // Opcode: IPTEOpt -/* 1473 */ MCD_OPC_Decode, 147, 9, 58, // Opcode: IPTE -/* 1477 */ MCD_OPC_FilterValue, 34, 16, 0, // Skip to: 1497 -/* 1481 */ MCD_OPC_CheckField, 8, 8, 0, 141, 27, // Skip to: 8540 -/* 1487 */ MCD_OPC_CheckField, 0, 4, 0, 135, 27, // Skip to: 8540 -/* 1493 */ MCD_OPC_Decode, 146, 9, 1, // Opcode: IPM -/* 1497 */ MCD_OPC_FilterValue, 35, 10, 0, // Skip to: 1511 -/* 1501 */ MCD_OPC_CheckField, 8, 8, 0, 121, 27, // Skip to: 8540 -/* 1507 */ MCD_OPC_Decode, 152, 9, 3, // Opcode: IVSK -/* 1511 */ MCD_OPC_FilterValue, 36, 16, 0, // Skip to: 1531 -/* 1515 */ MCD_OPC_CheckField, 8, 8, 0, 107, 27, // Skip to: 8540 -/* 1521 */ MCD_OPC_CheckField, 0, 4, 0, 101, 27, // Skip to: 8540 -/* 1527 */ MCD_OPC_Decode, 255, 8, 1, // Opcode: IAC -/* 1531 */ MCD_OPC_FilterValue, 37, 16, 0, // Skip to: 1551 -/* 1535 */ MCD_OPC_CheckField, 8, 8, 0, 87, 27, // Skip to: 8540 -/* 1541 */ MCD_OPC_CheckField, 0, 4, 0, 81, 27, // Skip to: 8540 -/* 1547 */ MCD_OPC_Decode, 149, 15, 1, // Opcode: SSAR -/* 1551 */ MCD_OPC_FilterValue, 38, 16, 0, // Skip to: 1571 -/* 1555 */ MCD_OPC_CheckField, 8, 8, 0, 67, 27, // Skip to: 8540 -/* 1561 */ MCD_OPC_CheckField, 0, 4, 0, 61, 27, // Skip to: 8540 -/* 1567 */ MCD_OPC_Decode, 226, 8, 1, // Opcode: EPAR -/* 1571 */ MCD_OPC_FilterValue, 39, 16, 0, // Skip to: 1591 -/* 1575 */ MCD_OPC_CheckField, 8, 8, 0, 47, 27, // Skip to: 8540 -/* 1581 */ MCD_OPC_CheckField, 0, 4, 0, 41, 27, // Skip to: 8540 -/* 1587 */ MCD_OPC_Decode, 232, 8, 1, // Opcode: ESAR -/* 1591 */ MCD_OPC_FilterValue, 40, 10, 0, // Skip to: 1605 -/* 1595 */ MCD_OPC_CheckField, 8, 8, 0, 27, 27, // Skip to: 8540 -/* 1601 */ MCD_OPC_Decode, 151, 14, 59, // Opcode: PT -/* 1605 */ MCD_OPC_FilterValue, 41, 10, 0, // Skip to: 1619 -/* 1609 */ MCD_OPC_CheckField, 8, 8, 0, 13, 27, // Skip to: 8540 -/* 1615 */ MCD_OPC_Decode, 151, 9, 3, // Opcode: ISKE -/* 1619 */ MCD_OPC_FilterValue, 42, 10, 0, // Skip to: 1633 -/* 1623 */ MCD_OPC_CheckField, 8, 8, 0, 255, 26, // Skip to: 8540 -/* 1629 */ MCD_OPC_Decode, 171, 14, 59, // Opcode: RRBE -/* 1633 */ MCD_OPC_FilterValue, 43, 21, 0, // Skip to: 1658 -/* 1637 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 1640 */ MCD_OPC_FilterValue, 0, 240, 26, // Skip to: 8540 -/* 1644 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 1654 -/* 1650 */ MCD_OPC_Decode, 152, 15, 59, // Opcode: SSKEOpt -/* 1654 */ MCD_OPC_Decode, 151, 15, 60, // Opcode: SSKE -/* 1658 */ MCD_OPC_FilterValue, 44, 10, 0, // Skip to: 1672 -/* 1662 */ MCD_OPC_CheckField, 8, 8, 0, 216, 26, // Skip to: 8540 -/* 1668 */ MCD_OPC_Decode, 158, 16, 61, // Opcode: TB -/* 1672 */ MCD_OPC_FilterValue, 45, 10, 0, // Skip to: 1686 -/* 1676 */ MCD_OPC_CheckField, 8, 8, 0, 202, 26, // Skip to: 8540 -/* 1682 */ MCD_OPC_Decode, 212, 8, 13, // Opcode: DXR -/* 1686 */ MCD_OPC_FilterValue, 46, 10, 0, // Skip to: 1700 -/* 1690 */ MCD_OPC_CheckField, 8, 8, 0, 188, 26, // Skip to: 8540 -/* 1696 */ MCD_OPC_Decode, 141, 14, 61, // Opcode: PGIN -/* 1700 */ MCD_OPC_FilterValue, 47, 10, 0, // Skip to: 1714 -/* 1704 */ MCD_OPC_CheckField, 8, 8, 0, 174, 26, // Skip to: 8540 -/* 1710 */ MCD_OPC_Decode, 142, 14, 61, // Opcode: PGOUT -/* 1714 */ MCD_OPC_FilterValue, 48, 10, 0, // Skip to: 1728 -/* 1718 */ MCD_OPC_CheckField, 0, 16, 0, 160, 26, // Skip to: 8540 -/* 1724 */ MCD_OPC_Decode, 133, 8, 0, // Opcode: CSCH -/* 1728 */ MCD_OPC_FilterValue, 49, 10, 0, // Skip to: 1742 -/* 1732 */ MCD_OPC_CheckField, 0, 16, 0, 146, 26, // Skip to: 8540 -/* 1738 */ MCD_OPC_Decode, 254, 8, 0, // Opcode: HSCH -/* 1742 */ MCD_OPC_FilterValue, 50, 4, 0, // Skip to: 1750 -/* 1746 */ MCD_OPC_Decode, 170, 13, 32, // Opcode: MSCH -/* 1750 */ MCD_OPC_FilterValue, 51, 4, 0, // Skip to: 1758 -/* 1754 */ MCD_OPC_Decode, 150, 15, 32, // Opcode: SSCH -/* 1758 */ MCD_OPC_FilterValue, 52, 4, 0, // Skip to: 1766 -/* 1762 */ MCD_OPC_Decode, 140, 16, 32, // Opcode: STSCH -/* 1766 */ MCD_OPC_FilterValue, 53, 4, 0, // Skip to: 1774 -/* 1770 */ MCD_OPC_Decode, 205, 16, 32, // Opcode: TSCH -/* 1774 */ MCD_OPC_FilterValue, 54, 4, 0, // Skip to: 1782 -/* 1778 */ MCD_OPC_Decode, 182, 16, 32, // Opcode: TPI -/* 1782 */ MCD_OPC_FilterValue, 55, 10, 0, // Skip to: 1796 -/* 1786 */ MCD_OPC_CheckField, 0, 16, 0, 92, 26, // Skip to: 8540 -/* 1792 */ MCD_OPC_Decode, 180, 14, 0, // Opcode: SAL -/* 1796 */ MCD_OPC_FilterValue, 56, 10, 0, // Skip to: 1810 -/* 1800 */ MCD_OPC_CheckField, 0, 16, 0, 78, 26, // Skip to: 8540 -/* 1806 */ MCD_OPC_Decode, 175, 14, 0, // Opcode: RSCH -/* 1810 */ MCD_OPC_FilterValue, 57, 4, 0, // Skip to: 1818 -/* 1814 */ MCD_OPC_Decode, 168, 15, 32, // Opcode: STCRW -/* 1818 */ MCD_OPC_FilterValue, 58, 4, 0, // Skip to: 1826 -/* 1822 */ MCD_OPC_Decode, 167, 15, 32, // Opcode: STCPS -/* 1826 */ MCD_OPC_FilterValue, 59, 10, 0, // Skip to: 1840 -/* 1830 */ MCD_OPC_CheckField, 0, 16, 0, 48, 26, // Skip to: 8540 -/* 1836 */ MCD_OPC_Decode, 160, 14, 0, // Opcode: RCHP -/* 1840 */ MCD_OPC_FilterValue, 60, 10, 0, // Skip to: 1854 -/* 1844 */ MCD_OPC_CheckField, 0, 16, 0, 34, 26, // Skip to: 8540 -/* 1850 */ MCD_OPC_Decode, 186, 14, 0, // Opcode: SCHM -/* 1854 */ MCD_OPC_FilterValue, 64, 10, 0, // Skip to: 1868 -/* 1858 */ MCD_OPC_CheckField, 8, 8, 0, 20, 26, // Skip to: 8540 -/* 1864 */ MCD_OPC_Decode, 166, 3, 61, // Opcode: BAKR -/* 1868 */ MCD_OPC_FilterValue, 65, 10, 0, // Skip to: 1882 -/* 1872 */ MCD_OPC_CheckField, 8, 8, 0, 6, 26, // Skip to: 8540 -/* 1878 */ MCD_OPC_Decode, 223, 5, 62, // Opcode: CKSM -/* 1882 */ MCD_OPC_FilterValue, 68, 10, 0, // Skip to: 1896 -/* 1886 */ MCD_OPC_CheckField, 8, 8, 0, 248, 25, // Skip to: 8540 -/* 1892 */ MCD_OPC_Decode, 251, 14, 11, // Opcode: SQDR -/* 1896 */ MCD_OPC_FilterValue, 69, 10, 0, // Skip to: 1910 -/* 1900 */ MCD_OPC_CheckField, 8, 8, 0, 234, 25, // Skip to: 8540 -/* 1906 */ MCD_OPC_Decode, 255, 14, 16, // Opcode: SQER -/* 1910 */ MCD_OPC_FilterValue, 70, 10, 0, // Skip to: 1924 -/* 1914 */ MCD_OPC_CheckField, 8, 8, 0, 220, 25, // Skip to: 8540 -/* 1920 */ MCD_OPC_Decode, 142, 16, 59, // Opcode: STURA -/* 1924 */ MCD_OPC_FilterValue, 71, 16, 0, // Skip to: 1944 -/* 1928 */ MCD_OPC_CheckField, 8, 8, 0, 206, 25, // Skip to: 8540 -/* 1934 */ MCD_OPC_CheckField, 0, 4, 0, 200, 25, // Skip to: 8540 -/* 1940 */ MCD_OPC_Decode, 189, 13, 63, // Opcode: MSTA -/* 1944 */ MCD_OPC_FilterValue, 72, 10, 0, // Skip to: 1958 -/* 1948 */ MCD_OPC_CheckField, 0, 16, 0, 186, 25, // Skip to: 8540 -/* 1954 */ MCD_OPC_Decode, 133, 14, 0, // Opcode: PALB -/* 1958 */ MCD_OPC_FilterValue, 73, 10, 0, // Skip to: 1972 -/* 1962 */ MCD_OPC_CheckField, 8, 8, 0, 172, 25, // Skip to: 8540 -/* 1968 */ MCD_OPC_Decode, 229, 8, 8, // Opcode: EREG -/* 1972 */ MCD_OPC_FilterValue, 74, 10, 0, // Skip to: 1986 -/* 1976 */ MCD_OPC_CheckField, 8, 8, 0, 158, 25, // Skip to: 8540 -/* 1982 */ MCD_OPC_Decode, 235, 8, 64, // Opcode: ESTA -/* 1986 */ MCD_OPC_FilterValue, 75, 10, 0, // Skip to: 2000 -/* 1990 */ MCD_OPC_CheckField, 8, 8, 0, 144, 25, // Skip to: 8540 -/* 1996 */ MCD_OPC_Decode, 232, 12, 59, // Opcode: LURA -/* 2000 */ MCD_OPC_FilterValue, 76, 10, 0, // Skip to: 2014 -/* 2004 */ MCD_OPC_CheckField, 8, 8, 0, 130, 25, // Skip to: 8540 -/* 2010 */ MCD_OPC_Decode, 157, 16, 65, // Opcode: TAR -/* 2014 */ MCD_OPC_FilterValue, 77, 10, 0, // Skip to: 2028 -/* 2018 */ MCD_OPC_CheckField, 8, 8, 0, 116, 25, // Skip to: 8540 -/* 2024 */ MCD_OPC_Decode, 213, 7, 66, // Opcode: CPYA -/* 2028 */ MCD_OPC_FilterValue, 78, 10, 0, // Skip to: 2042 -/* 2032 */ MCD_OPC_CheckField, 8, 8, 0, 102, 25, // Skip to: 8540 -/* 2038 */ MCD_OPC_Decode, 184, 14, 65, // Opcode: SAR -/* 2042 */ MCD_OPC_FilterValue, 79, 10, 0, // Skip to: 2056 -/* 2046 */ MCD_OPC_CheckField, 8, 8, 0, 88, 25, // Skip to: 8540 -/* 2052 */ MCD_OPC_Decode, 215, 8, 67, // Opcode: EAR -/* 2056 */ MCD_OPC_FilterValue, 80, 10, 0, // Skip to: 2070 -/* 2060 */ MCD_OPC_CheckField, 8, 8, 0, 74, 25, // Skip to: 8540 -/* 2066 */ MCD_OPC_Decode, 136, 8, 68, // Opcode: CSP -/* 2070 */ MCD_OPC_FilterValue, 82, 10, 0, // Skip to: 2084 -/* 2074 */ MCD_OPC_CheckField, 8, 8, 0, 60, 25, // Skip to: 8540 -/* 2080 */ MCD_OPC_Decode, 187, 13, 9, // Opcode: MSR -/* 2084 */ MCD_OPC_FilterValue, 84, 10, 0, // Skip to: 2098 -/* 2088 */ MCD_OPC_CheckField, 8, 8, 0, 46, 25, // Skip to: 8540 -/* 2094 */ MCD_OPC_Decode, 209, 13, 61, // Opcode: MVPG -/* 2098 */ MCD_OPC_FilterValue, 85, 10, 0, // Skip to: 2112 -/* 2102 */ MCD_OPC_CheckField, 8, 8, 0, 32, 25, // Skip to: 8540 -/* 2108 */ MCD_OPC_Decode, 210, 13, 69, // Opcode: MVST -/* 2112 */ MCD_OPC_FilterValue, 87, 10, 0, // Skip to: 2126 -/* 2116 */ MCD_OPC_CheckField, 8, 8, 0, 18, 25, // Skip to: 8540 -/* 2122 */ MCD_OPC_Decode, 152, 8, 7, // Opcode: CUSE -/* 2126 */ MCD_OPC_FilterValue, 88, 10, 0, // Skip to: 2140 -/* 2130 */ MCD_OPC_CheckField, 8, 8, 0, 4, 25, // Skip to: 8540 -/* 2136 */ MCD_OPC_Decode, 132, 4, 61, // Opcode: BSG -/* 2140 */ MCD_OPC_FilterValue, 90, 10, 0, // Skip to: 2154 -/* 2144 */ MCD_OPC_CheckField, 8, 8, 0, 246, 24, // Skip to: 8540 -/* 2150 */ MCD_OPC_Decode, 131, 4, 61, // Opcode: BSA -/* 2154 */ MCD_OPC_FilterValue, 93, 10, 0, // Skip to: 2168 -/* 2158 */ MCD_OPC_CheckField, 8, 8, 0, 232, 24, // Skip to: 8540 -/* 2164 */ MCD_OPC_Decode, 189, 7, 69, // Opcode: CLST -/* 2168 */ MCD_OPC_FilterValue, 94, 10, 0, // Skip to: 2182 -/* 2172 */ MCD_OPC_CheckField, 8, 8, 0, 218, 24, // Skip to: 8540 -/* 2178 */ MCD_OPC_Decode, 145, 15, 69, // Opcode: SRST -/* 2182 */ MCD_OPC_FilterValue, 99, 10, 0, // Skip to: 2196 -/* 2186 */ MCD_OPC_CheckField, 8, 8, 0, 204, 24, // Skip to: 8540 -/* 2192 */ MCD_OPC_Decode, 205, 7, 7, // Opcode: CMPSC -/* 2196 */ MCD_OPC_FilterValue, 116, 4, 0, // Skip to: 2204 -/* 2200 */ MCD_OPC_Decode, 213, 14, 32, // Opcode: SIGA -/* 2204 */ MCD_OPC_FilterValue, 118, 10, 0, // Skip to: 2218 -/* 2208 */ MCD_OPC_CheckField, 0, 16, 0, 182, 24, // Skip to: 8540 -/* 2214 */ MCD_OPC_Decode, 237, 21, 0, // Opcode: XSCH -/* 2218 */ MCD_OPC_FilterValue, 119, 4, 0, // Skip to: 2226 -/* 2222 */ MCD_OPC_Decode, 170, 14, 32, // Opcode: RP -/* 2226 */ MCD_OPC_FilterValue, 120, 4, 0, // Skip to: 2234 -/* 2230 */ MCD_OPC_Decode, 162, 15, 32, // Opcode: STCKE -/* 2234 */ MCD_OPC_FilterValue, 121, 4, 0, // Skip to: 2242 -/* 2238 */ MCD_OPC_Decode, 179, 14, 32, // Opcode: SACF -/* 2242 */ MCD_OPC_FilterValue, 124, 4, 0, // Skip to: 2250 -/* 2246 */ MCD_OPC_Decode, 163, 15, 32, // Opcode: STCKF -/* 2250 */ MCD_OPC_FilterValue, 125, 4, 0, // Skip to: 2258 -/* 2254 */ MCD_OPC_Decode, 141, 16, 32, // Opcode: STSI -/* 2258 */ MCD_OPC_FilterValue, 128, 1, 4, 0, // Skip to: 2267 -/* 2263 */ MCD_OPC_Decode, 194, 12, 32, // Opcode: LPP -/* 2267 */ MCD_OPC_FilterValue, 132, 1, 4, 0, // Skip to: 2276 -/* 2272 */ MCD_OPC_Decode, 132, 10, 32, // Opcode: LCCTL -/* 2276 */ MCD_OPC_FilterValue, 133, 1, 4, 0, // Skip to: 2285 -/* 2281 */ MCD_OPC_Decode, 183, 12, 32, // Opcode: LPCTL -/* 2285 */ MCD_OPC_FilterValue, 134, 1, 4, 0, // Skip to: 2294 -/* 2290 */ MCD_OPC_Decode, 159, 14, 32, // Opcode: QSI -/* 2294 */ MCD_OPC_FilterValue, 135, 1, 4, 0, // Skip to: 2303 -/* 2299 */ MCD_OPC_Decode, 214, 12, 32, // Opcode: LSCTL -/* 2303 */ MCD_OPC_FilterValue, 142, 1, 4, 0, // Skip to: 2312 -/* 2308 */ MCD_OPC_Decode, 158, 14, 32, // Opcode: QCTRI -/* 2312 */ MCD_OPC_FilterValue, 153, 1, 4, 0, // Skip to: 2321 -/* 2317 */ MCD_OPC_Decode, 141, 15, 70, // Opcode: SRNM -/* 2321 */ MCD_OPC_FilterValue, 156, 1, 4, 0, // Skip to: 2330 -/* 2326 */ MCD_OPC_Decode, 179, 15, 32, // Opcode: STFPC -/* 2330 */ MCD_OPC_FilterValue, 157, 1, 4, 0, // Skip to: 2339 -/* 2335 */ MCD_OPC_Decode, 174, 10, 32, // Opcode: LFPC -/* 2339 */ MCD_OPC_FilterValue, 165, 1, 10, 0, // Skip to: 2354 -/* 2344 */ MCD_OPC_CheckField, 8, 8, 0, 46, 24, // Skip to: 8540 -/* 2350 */ MCD_OPC_Decode, 189, 16, 71, // Opcode: TRE -/* 2354 */ MCD_OPC_FilterValue, 166, 1, 21, 0, // Skip to: 2380 -/* 2359 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 2362 */ MCD_OPC_FilterValue, 0, 30, 24, // Skip to: 8540 -/* 2366 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 2376 -/* 2372 */ MCD_OPC_Decode, 146, 8, 7, // Opcode: CU21Opt -/* 2376 */ MCD_OPC_Decode, 145, 8, 72, // Opcode: CU21 -/* 2380 */ MCD_OPC_FilterValue, 167, 1, 21, 0, // Skip to: 2406 -/* 2385 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 2388 */ MCD_OPC_FilterValue, 0, 4, 24, // Skip to: 8540 -/* 2392 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 2402 -/* 2398 */ MCD_OPC_Decode, 142, 8, 7, // Opcode: CU12Opt -/* 2402 */ MCD_OPC_Decode, 141, 8, 72, // Opcode: CU12 -/* 2406 */ MCD_OPC_FilterValue, 176, 1, 4, 0, // Skip to: 2415 -/* 2411 */ MCD_OPC_Decode, 178, 15, 32, // Opcode: STFLE -/* 2415 */ MCD_OPC_FilterValue, 177, 1, 4, 0, // Skip to: 2424 -/* 2420 */ MCD_OPC_Decode, 177, 15, 32, // Opcode: STFL -/* 2424 */ MCD_OPC_FilterValue, 178, 1, 4, 0, // Skip to: 2433 -/* 2429 */ MCD_OPC_Decode, 198, 12, 32, // Opcode: LPSWE -/* 2433 */ MCD_OPC_FilterValue, 184, 1, 8, 0, // Skip to: 2446 -/* 2438 */ MCD_OPC_CheckPredicate, 0, 210, 23, // Skip to: 8540 -/* 2442 */ MCD_OPC_Decode, 142, 15, 70, // Opcode: SRNMB -/* 2446 */ MCD_OPC_FilterValue, 185, 1, 4, 0, // Skip to: 2455 -/* 2451 */ MCD_OPC_Decode, 143, 15, 70, // Opcode: SRNMT -/* 2455 */ MCD_OPC_FilterValue, 189, 1, 4, 0, // Skip to: 2464 -/* 2460 */ MCD_OPC_Decode, 171, 10, 32, // Opcode: LFAS -/* 2464 */ MCD_OPC_FilterValue, 224, 1, 10, 0, // Skip to: 2479 -/* 2469 */ MCD_OPC_CheckField, 8, 8, 0, 177, 23, // Skip to: 8540 -/* 2475 */ MCD_OPC_Decode, 185, 14, 61, // Opcode: SCCTR -/* 2479 */ MCD_OPC_FilterValue, 225, 1, 10, 0, // Skip to: 2494 -/* 2484 */ MCD_OPC_CheckField, 8, 8, 0, 162, 23, // Skip to: 8540 -/* 2490 */ MCD_OPC_Decode, 243, 14, 61, // Opcode: SPCTR -/* 2494 */ MCD_OPC_FilterValue, 228, 1, 10, 0, // Skip to: 2509 -/* 2499 */ MCD_OPC_CheckField, 8, 8, 0, 147, 23, // Skip to: 8540 -/* 2505 */ MCD_OPC_Decode, 217, 8, 61, // Opcode: ECCTR -/* 2509 */ MCD_OPC_FilterValue, 229, 1, 10, 0, // Skip to: 2524 -/* 2514 */ MCD_OPC_CheckField, 8, 8, 0, 132, 23, // Skip to: 8540 -/* 2520 */ MCD_OPC_Decode, 227, 8, 61, // Opcode: EPCTR -/* 2524 */ MCD_OPC_FilterValue, 232, 1, 14, 0, // Skip to: 2543 -/* 2529 */ MCD_OPC_CheckPredicate, 1, 119, 23, // Skip to: 8540 -/* 2533 */ MCD_OPC_CheckField, 8, 4, 0, 113, 23, // Skip to: 8540 -/* 2539 */ MCD_OPC_Decode, 147, 14, 73, // Opcode: PPA -/* 2543 */ MCD_OPC_FilterValue, 236, 1, 20, 0, // Skip to: 2568 -/* 2548 */ MCD_OPC_CheckPredicate, 2, 100, 23, // Skip to: 8540 -/* 2552 */ MCD_OPC_CheckField, 8, 8, 0, 94, 23, // Skip to: 8540 -/* 2558 */ MCD_OPC_CheckField, 0, 4, 0, 88, 23, // Skip to: 8540 -/* 2564 */ MCD_OPC_Decode, 237, 8, 1, // Opcode: ETND -/* 2568 */ MCD_OPC_FilterValue, 237, 1, 10, 0, // Skip to: 2583 -/* 2573 */ MCD_OPC_CheckField, 8, 8, 0, 73, 23, // Skip to: 8540 -/* 2579 */ MCD_OPC_Decode, 218, 8, 59, // Opcode: ECPGA -/* 2583 */ MCD_OPC_FilterValue, 248, 1, 14, 0, // Skip to: 2602 -/* 2588 */ MCD_OPC_CheckPredicate, 2, 60, 23, // Skip to: 8540 -/* 2592 */ MCD_OPC_CheckField, 0, 16, 0, 54, 23, // Skip to: 8540 -/* 2598 */ MCD_OPC_Decode, 172, 16, 0, // Opcode: TEND -/* 2602 */ MCD_OPC_FilterValue, 250, 1, 14, 0, // Skip to: 2621 -/* 2607 */ MCD_OPC_CheckPredicate, 3, 41, 23, // Skip to: 8540 -/* 2611 */ MCD_OPC_CheckField, 8, 8, 0, 35, 23, // Skip to: 8540 -/* 2617 */ MCD_OPC_Decode, 232, 13, 74, // Opcode: NIAI -/* 2621 */ MCD_OPC_FilterValue, 252, 1, 8, 0, // Skip to: 2634 -/* 2626 */ MCD_OPC_CheckPredicate, 2, 22, 23, // Skip to: 8540 -/* 2630 */ MCD_OPC_Decode, 155, 16, 32, // Opcode: TABORT -/* 2634 */ MCD_OPC_FilterValue, 255, 1, 13, 23, // Skip to: 8540 -/* 2639 */ MCD_OPC_Decode, 188, 16, 32, // Opcode: TRAP4 -/* 2643 */ MCD_OPC_FilterValue, 179, 1, 122, 10, // Skip to: 5330 -/* 2648 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 2651 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 2665 -/* 2655 */ MCD_OPC_CheckField, 8, 8, 0, 247, 22, // Skip to: 8540 -/* 2661 */ MCD_OPC_Decode, 190, 12, 16, // Opcode: LPEBR -/* 2665 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 2679 -/* 2669 */ MCD_OPC_CheckField, 8, 8, 0, 233, 22, // Skip to: 8540 -/* 2675 */ MCD_OPC_Decode, 234, 10, 16, // Opcode: LNEBR -/* 2679 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 2693 -/* 2683 */ MCD_OPC_CheckField, 8, 8, 0, 219, 22, // Skip to: 8540 -/* 2689 */ MCD_OPC_Decode, 220, 12, 16, // Opcode: LTEBR -/* 2693 */ MCD_OPC_FilterValue, 3, 10, 0, // Skip to: 2707 -/* 2697 */ MCD_OPC_CheckField, 8, 8, 0, 205, 22, // Skip to: 8540 -/* 2703 */ MCD_OPC_Decode, 137, 10, 16, // Opcode: LCEBR -/* 2707 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 2721 -/* 2711 */ MCD_OPC_CheckField, 8, 8, 0, 191, 22, // Skip to: 8540 -/* 2717 */ MCD_OPC_Decode, 150, 10, 75, // Opcode: LDEBR -/* 2721 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 2735 -/* 2725 */ MCD_OPC_CheckField, 8, 8, 0, 177, 22, // Skip to: 8540 -/* 2731 */ MCD_OPC_Decode, 236, 12, 76, // Opcode: LXDBR -/* 2735 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 2749 -/* 2739 */ MCD_OPC_CheckField, 8, 8, 0, 163, 22, // Skip to: 8540 -/* 2745 */ MCD_OPC_Decode, 241, 12, 77, // Opcode: LXEBR -/* 2749 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 2763 -/* 2753 */ MCD_OPC_CheckField, 8, 8, 0, 149, 22, // Skip to: 8540 -/* 2759 */ MCD_OPC_Decode, 215, 13, 14, // Opcode: MXDBR -/* 2763 */ MCD_OPC_FilterValue, 8, 10, 0, // Skip to: 2777 -/* 2767 */ MCD_OPC_CheckField, 8, 8, 0, 135, 22, // Skip to: 8540 -/* 2773 */ MCD_OPC_Decode, 224, 9, 16, // Opcode: KEBR -/* 2777 */ MCD_OPC_FilterValue, 9, 10, 0, // Skip to: 2791 -/* 2781 */ MCD_OPC_CheckField, 8, 8, 0, 121, 22, // Skip to: 8540 -/* 2787 */ MCD_OPC_Decode, 166, 4, 16, // Opcode: CEBR -/* 2791 */ MCD_OPC_FilterValue, 10, 10, 0, // Skip to: 2805 -/* 2795 */ MCD_OPC_CheckField, 8, 8, 0, 107, 22, // Skip to: 8540 -/* 2801 */ MCD_OPC_Decode, 237, 2, 18, // Opcode: AEBR -/* 2805 */ MCD_OPC_FilterValue, 11, 10, 0, // Skip to: 2819 -/* 2809 */ MCD_OPC_CheckField, 8, 8, 0, 93, 22, // Skip to: 8540 -/* 2815 */ MCD_OPC_Decode, 198, 14, 18, // Opcode: SEBR -/* 2819 */ MCD_OPC_FilterValue, 12, 10, 0, // Skip to: 2833 -/* 2823 */ MCD_OPC_CheckField, 8, 8, 0, 79, 22, // Skip to: 8540 -/* 2829 */ MCD_OPC_Decode, 143, 13, 19, // Opcode: MDEBR -/* 2833 */ MCD_OPC_FilterValue, 13, 10, 0, // Skip to: 2847 -/* 2837 */ MCD_OPC_CheckField, 8, 8, 0, 65, 22, // Skip to: 8540 -/* 2843 */ MCD_OPC_Decode, 196, 8, 18, // Opcode: DEBR -/* 2847 */ MCD_OPC_FilterValue, 14, 10, 0, // Skip to: 2861 -/* 2851 */ MCD_OPC_CheckField, 8, 4, 0, 51, 22, // Skip to: 8540 -/* 2857 */ MCD_OPC_Decode, 129, 13, 78, // Opcode: MAEBR -/* 2861 */ MCD_OPC_FilterValue, 15, 10, 0, // Skip to: 2875 -/* 2865 */ MCD_OPC_CheckField, 8, 4, 0, 37, 22, // Skip to: 8540 -/* 2871 */ MCD_OPC_Decode, 177, 13, 78, // Opcode: MSEBR -/* 2875 */ MCD_OPC_FilterValue, 16, 10, 0, // Skip to: 2889 -/* 2879 */ MCD_OPC_CheckField, 8, 8, 0, 23, 22, // Skip to: 8540 -/* 2885 */ MCD_OPC_Decode, 185, 12, 11, // Opcode: LPDBR -/* 2889 */ MCD_OPC_FilterValue, 17, 10, 0, // Skip to: 2903 -/* 2893 */ MCD_OPC_CheckField, 8, 8, 0, 9, 22, // Skip to: 8540 -/* 2899 */ MCD_OPC_Decode, 230, 10, 11, // Opcode: LNDBR -/* 2903 */ MCD_OPC_FilterValue, 18, 10, 0, // Skip to: 2917 -/* 2907 */ MCD_OPC_CheckField, 8, 8, 0, 251, 21, // Skip to: 8540 -/* 2913 */ MCD_OPC_Decode, 216, 12, 11, // Opcode: LTDBR -/* 2917 */ MCD_OPC_FilterValue, 19, 10, 0, // Skip to: 2931 -/* 2921 */ MCD_OPC_CheckField, 8, 8, 0, 237, 21, // Skip to: 8540 -/* 2927 */ MCD_OPC_Decode, 133, 10, 11, // Opcode: LCDBR -/* 2931 */ MCD_OPC_FilterValue, 20, 10, 0, // Skip to: 2945 -/* 2935 */ MCD_OPC_CheckField, 8, 8, 0, 223, 21, // Skip to: 8540 -/* 2941 */ MCD_OPC_Decode, 254, 14, 16, // Opcode: SQEBR -/* 2945 */ MCD_OPC_FilterValue, 21, 10, 0, // Skip to: 2959 -/* 2949 */ MCD_OPC_CheckField, 8, 8, 0, 209, 21, // Skip to: 8540 -/* 2955 */ MCD_OPC_Decode, 250, 14, 11, // Opcode: SQDBR -/* 2959 */ MCD_OPC_FilterValue, 22, 10, 0, // Skip to: 2973 -/* 2963 */ MCD_OPC_CheckField, 8, 8, 0, 195, 21, // Skip to: 8540 -/* 2969 */ MCD_OPC_Decode, 128, 15, 79, // Opcode: SQXBR -/* 2973 */ MCD_OPC_FilterValue, 23, 10, 0, // Skip to: 2987 -/* 2977 */ MCD_OPC_CheckField, 8, 8, 0, 181, 21, // Skip to: 8540 -/* 2983 */ MCD_OPC_Decode, 151, 13, 18, // Opcode: MEEBR -/* 2987 */ MCD_OPC_FilterValue, 24, 10, 0, // Skip to: 3001 -/* 2991 */ MCD_OPC_CheckField, 8, 8, 0, 167, 21, // Skip to: 8540 -/* 2997 */ MCD_OPC_Decode, 221, 9, 11, // Opcode: KDBR -/* 3001 */ MCD_OPC_FilterValue, 25, 10, 0, // Skip to: 3015 -/* 3005 */ MCD_OPC_CheckField, 8, 8, 0, 153, 21, // Skip to: 8540 -/* 3011 */ MCD_OPC_Decode, 141, 4, 11, // Opcode: CDBR -/* 3015 */ MCD_OPC_FilterValue, 26, 10, 0, // Skip to: 3029 -/* 3019 */ MCD_OPC_CheckField, 8, 8, 0, 139, 21, // Skip to: 8540 -/* 3025 */ MCD_OPC_Decode, 231, 2, 15, // Opcode: ADBR -/* 3029 */ MCD_OPC_FilterValue, 27, 10, 0, // Skip to: 3043 -/* 3033 */ MCD_OPC_CheckField, 8, 8, 0, 125, 21, // Skip to: 8540 -/* 3039 */ MCD_OPC_Decode, 192, 14, 15, // Opcode: SDBR -/* 3043 */ MCD_OPC_FilterValue, 28, 10, 0, // Skip to: 3057 -/* 3047 */ MCD_OPC_CheckField, 8, 8, 0, 111, 21, // Skip to: 8540 -/* 3053 */ MCD_OPC_Decode, 140, 13, 15, // Opcode: MDBR -/* 3057 */ MCD_OPC_FilterValue, 29, 10, 0, // Skip to: 3071 -/* 3061 */ MCD_OPC_CheckField, 8, 8, 0, 97, 21, // Skip to: 8540 -/* 3067 */ MCD_OPC_Decode, 190, 8, 15, // Opcode: DDBR -/* 3071 */ MCD_OPC_FilterValue, 30, 10, 0, // Skip to: 3085 -/* 3075 */ MCD_OPC_CheckField, 8, 4, 0, 83, 21, // Skip to: 8540 -/* 3081 */ MCD_OPC_Decode, 253, 12, 80, // Opcode: MADBR -/* 3085 */ MCD_OPC_FilterValue, 31, 10, 0, // Skip to: 3099 -/* 3089 */ MCD_OPC_CheckField, 8, 4, 0, 69, 21, // Skip to: 8540 -/* 3095 */ MCD_OPC_Decode, 173, 13, 80, // Opcode: MSDBR -/* 3099 */ MCD_OPC_FilterValue, 36, 10, 0, // Skip to: 3113 -/* 3103 */ MCD_OPC_CheckField, 8, 8, 0, 55, 21, // Skip to: 8540 -/* 3109 */ MCD_OPC_Decode, 151, 10, 75, // Opcode: LDER -/* 3113 */ MCD_OPC_FilterValue, 37, 10, 0, // Skip to: 3127 -/* 3117 */ MCD_OPC_CheckField, 8, 8, 0, 41, 21, // Skip to: 8540 -/* 3123 */ MCD_OPC_Decode, 237, 12, 76, // Opcode: LXDR -/* 3127 */ MCD_OPC_FilterValue, 38, 10, 0, // Skip to: 3141 -/* 3131 */ MCD_OPC_CheckField, 8, 8, 0, 27, 21, // Skip to: 8540 -/* 3137 */ MCD_OPC_Decode, 242, 12, 77, // Opcode: LXER -/* 3141 */ MCD_OPC_FilterValue, 46, 10, 0, // Skip to: 3155 -/* 3145 */ MCD_OPC_CheckField, 8, 4, 0, 13, 21, // Skip to: 8540 -/* 3151 */ MCD_OPC_Decode, 130, 13, 78, // Opcode: MAER -/* 3155 */ MCD_OPC_FilterValue, 47, 10, 0, // Skip to: 3169 -/* 3159 */ MCD_OPC_CheckField, 8, 4, 0, 255, 20, // Skip to: 8540 -/* 3165 */ MCD_OPC_Decode, 178, 13, 78, // Opcode: MSER -/* 3169 */ MCD_OPC_FilterValue, 54, 10, 0, // Skip to: 3183 -/* 3173 */ MCD_OPC_CheckField, 8, 8, 0, 241, 20, // Skip to: 8540 -/* 3179 */ MCD_OPC_Decode, 129, 15, 79, // Opcode: SQXR -/* 3183 */ MCD_OPC_FilterValue, 55, 10, 0, // Skip to: 3197 -/* 3187 */ MCD_OPC_CheckField, 8, 8, 0, 227, 20, // Skip to: 8540 -/* 3193 */ MCD_OPC_Decode, 152, 13, 18, // Opcode: MEER -/* 3197 */ MCD_OPC_FilterValue, 56, 10, 0, // Skip to: 3211 -/* 3201 */ MCD_OPC_CheckField, 8, 4, 0, 213, 20, // Skip to: 8540 -/* 3207 */ MCD_OPC_Decode, 135, 13, 80, // Opcode: MAYLR -/* 3211 */ MCD_OPC_FilterValue, 57, 10, 0, // Skip to: 3225 -/* 3215 */ MCD_OPC_CheckField, 8, 4, 0, 199, 20, // Skip to: 8540 -/* 3221 */ MCD_OPC_Decode, 224, 13, 81, // Opcode: MYLR -/* 3225 */ MCD_OPC_FilterValue, 58, 10, 0, // Skip to: 3239 -/* 3229 */ MCD_OPC_CheckField, 8, 4, 0, 185, 20, // Skip to: 8540 -/* 3235 */ MCD_OPC_Decode, 136, 13, 82, // Opcode: MAYR -/* 3239 */ MCD_OPC_FilterValue, 59, 10, 0, // Skip to: 3253 -/* 3243 */ MCD_OPC_CheckField, 8, 4, 0, 171, 20, // Skip to: 8540 -/* 3249 */ MCD_OPC_Decode, 225, 13, 83, // Opcode: MYR -/* 3253 */ MCD_OPC_FilterValue, 60, 10, 0, // Skip to: 3267 -/* 3257 */ MCD_OPC_CheckField, 8, 4, 0, 157, 20, // Skip to: 8540 -/* 3263 */ MCD_OPC_Decode, 133, 13, 80, // Opcode: MAYHR -/* 3267 */ MCD_OPC_FilterValue, 61, 10, 0, // Skip to: 3281 -/* 3271 */ MCD_OPC_CheckField, 8, 4, 0, 143, 20, // Skip to: 8540 -/* 3277 */ MCD_OPC_Decode, 222, 13, 81, // Opcode: MYHR -/* 3281 */ MCD_OPC_FilterValue, 62, 10, 0, // Skip to: 3295 -/* 3285 */ MCD_OPC_CheckField, 8, 4, 0, 129, 20, // Skip to: 8540 -/* 3291 */ MCD_OPC_Decode, 254, 12, 80, // Opcode: MADR -/* 3295 */ MCD_OPC_FilterValue, 63, 10, 0, // Skip to: 3309 -/* 3299 */ MCD_OPC_CheckField, 8, 4, 0, 115, 20, // Skip to: 8540 -/* 3305 */ MCD_OPC_Decode, 174, 13, 80, // Opcode: MSDR -/* 3309 */ MCD_OPC_FilterValue, 64, 10, 0, // Skip to: 3323 -/* 3313 */ MCD_OPC_CheckField, 8, 8, 0, 101, 20, // Skip to: 8540 -/* 3319 */ MCD_OPC_Decode, 200, 12, 79, // Opcode: LPXBR -/* 3323 */ MCD_OPC_FilterValue, 65, 10, 0, // Skip to: 3337 -/* 3327 */ MCD_OPC_CheckField, 8, 8, 0, 87, 20, // Skip to: 8540 -/* 3333 */ MCD_OPC_Decode, 239, 10, 79, // Opcode: LNXBR -/* 3337 */ MCD_OPC_FilterValue, 66, 10, 0, // Skip to: 3351 -/* 3341 */ MCD_OPC_CheckField, 8, 8, 0, 73, 20, // Skip to: 8540 -/* 3347 */ MCD_OPC_Decode, 228, 12, 79, // Opcode: LTXBR -/* 3351 */ MCD_OPC_FilterValue, 67, 10, 0, // Skip to: 3365 -/* 3355 */ MCD_OPC_CheckField, 8, 8, 0, 59, 20, // Skip to: 8540 -/* 3361 */ MCD_OPC_Decode, 144, 10, 79, // Opcode: LCXBR -/* 3365 */ MCD_OPC_FilterValue, 68, 18, 0, // Skip to: 3387 -/* 3369 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 3379 -/* 3375 */ MCD_OPC_Decode, 162, 10, 17, // Opcode: LEDBR -/* 3379 */ MCD_OPC_CheckPredicate, 0, 37, 20, // Skip to: 8540 -/* 3383 */ MCD_OPC_Decode, 163, 10, 84, // Opcode: LEDBRA -/* 3387 */ MCD_OPC_FilterValue, 69, 18, 0, // Skip to: 3409 -/* 3391 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 3401 -/* 3397 */ MCD_OPC_Decode, 156, 10, 79, // Opcode: LDXBR -/* 3401 */ MCD_OPC_CheckPredicate, 0, 15, 20, // Skip to: 8540 -/* 3405 */ MCD_OPC_Decode, 157, 10, 85, // Opcode: LDXBRA -/* 3409 */ MCD_OPC_FilterValue, 70, 18, 0, // Skip to: 3431 -/* 3413 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 3423 -/* 3419 */ MCD_OPC_Decode, 167, 10, 79, // Opcode: LEXBR -/* 3423 */ MCD_OPC_CheckPredicate, 0, 249, 19, // Skip to: 8540 -/* 3427 */ MCD_OPC_Decode, 168, 10, 85, // Opcode: LEXBRA -/* 3431 */ MCD_OPC_FilterValue, 71, 18, 0, // Skip to: 3453 -/* 3435 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 3445 -/* 3441 */ MCD_OPC_Decode, 247, 8, 86, // Opcode: FIXBR -/* 3445 */ MCD_OPC_CheckPredicate, 0, 227, 19, // Skip to: 8540 -/* 3449 */ MCD_OPC_Decode, 248, 8, 85, // Opcode: FIXBRA -/* 3453 */ MCD_OPC_FilterValue, 72, 10, 0, // Skip to: 3467 -/* 3457 */ MCD_OPC_CheckField, 8, 8, 0, 213, 19, // Skip to: 8540 -/* 3463 */ MCD_OPC_Decode, 234, 9, 79, // Opcode: KXBR -/* 3467 */ MCD_OPC_FilterValue, 73, 10, 0, // Skip to: 3481 -/* 3471 */ MCD_OPC_CheckField, 8, 8, 0, 199, 19, // Skip to: 8540 -/* 3477 */ MCD_OPC_Decode, 164, 8, 79, // Opcode: CXBR -/* 3481 */ MCD_OPC_FilterValue, 74, 10, 0, // Skip to: 3495 -/* 3485 */ MCD_OPC_CheckField, 8, 8, 0, 185, 19, // Skip to: 8540 -/* 3491 */ MCD_OPC_Decode, 160, 3, 13, // Opcode: AXBR -/* 3495 */ MCD_OPC_FilterValue, 75, 10, 0, // Skip to: 3509 -/* 3499 */ MCD_OPC_CheckField, 8, 8, 0, 171, 19, // Skip to: 8540 -/* 3505 */ MCD_OPC_Decode, 150, 16, 13, // Opcode: SXBR -/* 3509 */ MCD_OPC_FilterValue, 76, 10, 0, // Skip to: 3523 -/* 3513 */ MCD_OPC_CheckField, 8, 8, 0, 157, 19, // Skip to: 8540 -/* 3519 */ MCD_OPC_Decode, 212, 13, 13, // Opcode: MXBR -/* 3523 */ MCD_OPC_FilterValue, 77, 10, 0, // Skip to: 3537 -/* 3527 */ MCD_OPC_CheckField, 8, 8, 0, 143, 19, // Skip to: 8540 -/* 3533 */ MCD_OPC_Decode, 211, 8, 13, // Opcode: DXBR -/* 3537 */ MCD_OPC_FilterValue, 80, 10, 0, // Skip to: 3551 -/* 3541 */ MCD_OPC_CheckField, 8, 4, 0, 129, 19, // Skip to: 8540 -/* 3547 */ MCD_OPC_Decode, 160, 16, 87, // Opcode: TBEDR -/* 3551 */ MCD_OPC_FilterValue, 81, 10, 0, // Skip to: 3565 -/* 3555 */ MCD_OPC_CheckField, 8, 4, 0, 115, 19, // Skip to: 8540 -/* 3561 */ MCD_OPC_Decode, 159, 16, 88, // Opcode: TBDR -/* 3565 */ MCD_OPC_FilterValue, 83, 4, 0, // Skip to: 3573 -/* 3569 */ MCD_OPC_Decode, 200, 8, 89, // Opcode: DIEBR -/* 3573 */ MCD_OPC_FilterValue, 87, 18, 0, // Skip to: 3595 -/* 3577 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 3587 -/* 3583 */ MCD_OPC_Decode, 244, 8, 90, // Opcode: FIEBR -/* 3587 */ MCD_OPC_CheckPredicate, 0, 85, 19, // Skip to: 8540 -/* 3591 */ MCD_OPC_Decode, 245, 8, 91, // Opcode: FIEBRA -/* 3595 */ MCD_OPC_FilterValue, 88, 10, 0, // Skip to: 3609 -/* 3599 */ MCD_OPC_CheckField, 8, 8, 0, 71, 19, // Skip to: 8540 -/* 3605 */ MCD_OPC_Decode, 173, 16, 75, // Opcode: THDER -/* 3609 */ MCD_OPC_FilterValue, 89, 10, 0, // Skip to: 3623 -/* 3613 */ MCD_OPC_CheckField, 8, 8, 0, 57, 19, // Skip to: 8540 -/* 3619 */ MCD_OPC_Decode, 174, 16, 11, // Opcode: THDR -/* 3623 */ MCD_OPC_FilterValue, 91, 4, 0, // Skip to: 3631 -/* 3627 */ MCD_OPC_Decode, 199, 8, 92, // Opcode: DIDBR -/* 3631 */ MCD_OPC_FilterValue, 95, 18, 0, // Skip to: 3653 -/* 3635 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 3645 -/* 3641 */ MCD_OPC_Decode, 240, 8, 88, // Opcode: FIDBR -/* 3645 */ MCD_OPC_CheckPredicate, 0, 27, 19, // Skip to: 8540 -/* 3649 */ MCD_OPC_Decode, 241, 8, 93, // Opcode: FIDBRA -/* 3653 */ MCD_OPC_FilterValue, 96, 10, 0, // Skip to: 3667 -/* 3657 */ MCD_OPC_CheckField, 8, 8, 0, 13, 19, // Skip to: 8540 -/* 3663 */ MCD_OPC_Decode, 201, 12, 79, // Opcode: LPXR -/* 3667 */ MCD_OPC_FilterValue, 97, 10, 0, // Skip to: 3681 -/* 3671 */ MCD_OPC_CheckField, 8, 8, 0, 255, 18, // Skip to: 8540 -/* 3677 */ MCD_OPC_Decode, 240, 10, 79, // Opcode: LNXR -/* 3681 */ MCD_OPC_FilterValue, 98, 10, 0, // Skip to: 3695 -/* 3685 */ MCD_OPC_CheckField, 8, 8, 0, 241, 18, // Skip to: 8540 -/* 3691 */ MCD_OPC_Decode, 230, 12, 79, // Opcode: LTXR -/* 3695 */ MCD_OPC_FilterValue, 99, 10, 0, // Skip to: 3709 -/* 3699 */ MCD_OPC_CheckField, 8, 8, 0, 227, 18, // Skip to: 8540 -/* 3705 */ MCD_OPC_Decode, 145, 10, 79, // Opcode: LCXR -/* 3709 */ MCD_OPC_FilterValue, 101, 10, 0, // Skip to: 3723 -/* 3713 */ MCD_OPC_CheckField, 8, 8, 0, 213, 18, // Skip to: 8540 -/* 3719 */ MCD_OPC_Decode, 243, 12, 79, // Opcode: LXR -/* 3723 */ MCD_OPC_FilterValue, 102, 10, 0, // Skip to: 3737 -/* 3727 */ MCD_OPC_CheckField, 8, 8, 0, 199, 18, // Skip to: 8540 -/* 3733 */ MCD_OPC_Decode, 169, 10, 94, // Opcode: LEXR -/* 3737 */ MCD_OPC_FilterValue, 103, 10, 0, // Skip to: 3751 -/* 3741 */ MCD_OPC_CheckField, 8, 8, 0, 185, 18, // Skip to: 8540 -/* 3747 */ MCD_OPC_Decode, 249, 8, 79, // Opcode: FIXR -/* 3751 */ MCD_OPC_FilterValue, 105, 10, 0, // Skip to: 3765 -/* 3755 */ MCD_OPC_CheckField, 8, 8, 0, 171, 18, // Skip to: 8540 -/* 3761 */ MCD_OPC_Decode, 179, 8, 79, // Opcode: CXR -/* 3765 */ MCD_OPC_FilterValue, 112, 10, 0, // Skip to: 3779 -/* 3769 */ MCD_OPC_CheckField, 8, 8, 0, 157, 18, // Skip to: 8540 -/* 3775 */ MCD_OPC_Decode, 186, 12, 11, // Opcode: LPDFR -/* 3779 */ MCD_OPC_FilterValue, 113, 10, 0, // Skip to: 3793 -/* 3783 */ MCD_OPC_CheckField, 8, 8, 0, 143, 18, // Skip to: 8540 -/* 3789 */ MCD_OPC_Decode, 231, 10, 11, // Opcode: LNDFR -/* 3793 */ MCD_OPC_FilterValue, 114, 10, 0, // Skip to: 3807 -/* 3797 */ MCD_OPC_CheckField, 8, 4, 0, 129, 18, // Skip to: 8540 -/* 3803 */ MCD_OPC_Decode, 208, 7, 95, // Opcode: CPSDRdd -/* 3807 */ MCD_OPC_FilterValue, 115, 10, 0, // Skip to: 3821 -/* 3811 */ MCD_OPC_CheckField, 8, 8, 0, 115, 18, // Skip to: 8540 -/* 3817 */ MCD_OPC_Decode, 134, 10, 11, // Opcode: LCDFR -/* 3821 */ MCD_OPC_FilterValue, 116, 16, 0, // Skip to: 3841 -/* 3825 */ MCD_OPC_CheckField, 8, 8, 0, 101, 18, // Skip to: 8540 -/* 3831 */ MCD_OPC_CheckField, 0, 4, 0, 95, 18, // Skip to: 8540 -/* 3837 */ MCD_OPC_Decode, 246, 12, 96, // Opcode: LZER -/* 3841 */ MCD_OPC_FilterValue, 117, 16, 0, // Skip to: 3861 -/* 3845 */ MCD_OPC_CheckField, 8, 8, 0, 81, 18, // Skip to: 8540 -/* 3851 */ MCD_OPC_CheckField, 0, 4, 0, 75, 18, // Skip to: 8540 -/* 3857 */ MCD_OPC_Decode, 245, 12, 97, // Opcode: LZDR -/* 3861 */ MCD_OPC_FilterValue, 118, 16, 0, // Skip to: 3881 -/* 3865 */ MCD_OPC_CheckField, 8, 8, 0, 61, 18, // Skip to: 8540 -/* 3871 */ MCD_OPC_CheckField, 0, 4, 0, 55, 18, // Skip to: 8540 -/* 3877 */ MCD_OPC_Decode, 249, 12, 98, // Opcode: LZXR -/* 3881 */ MCD_OPC_FilterValue, 119, 10, 0, // Skip to: 3895 -/* 3885 */ MCD_OPC_CheckField, 8, 8, 0, 41, 18, // Skip to: 8540 -/* 3891 */ MCD_OPC_Decode, 246, 8, 16, // Opcode: FIER -/* 3895 */ MCD_OPC_FilterValue, 127, 10, 0, // Skip to: 3909 -/* 3899 */ MCD_OPC_CheckField, 8, 8, 0, 27, 18, // Skip to: 8540 -/* 3905 */ MCD_OPC_Decode, 242, 8, 11, // Opcode: FIDR -/* 3909 */ MCD_OPC_FilterValue, 132, 1, 16, 0, // Skip to: 3930 -/* 3914 */ MCD_OPC_CheckField, 8, 8, 0, 12, 18, // Skip to: 8540 -/* 3920 */ MCD_OPC_CheckField, 0, 4, 0, 6, 18, // Skip to: 8540 -/* 3926 */ MCD_OPC_Decode, 201, 14, 1, // Opcode: SFPC -/* 3930 */ MCD_OPC_FilterValue, 133, 1, 16, 0, // Skip to: 3951 -/* 3935 */ MCD_OPC_CheckField, 8, 8, 0, 247, 17, // Skip to: 8540 -/* 3941 */ MCD_OPC_CheckField, 0, 4, 0, 241, 17, // Skip to: 8540 -/* 3947 */ MCD_OPC_Decode, 200, 14, 1, // Opcode: SFASR -/* 3951 */ MCD_OPC_FilterValue, 140, 1, 16, 0, // Skip to: 3972 -/* 3956 */ MCD_OPC_CheckField, 8, 8, 0, 226, 17, // Skip to: 8540 -/* 3962 */ MCD_OPC_CheckField, 0, 4, 0, 220, 17, // Skip to: 8540 -/* 3968 */ MCD_OPC_Decode, 224, 8, 1, // Opcode: EFPC -/* 3972 */ MCD_OPC_FilterValue, 144, 1, 8, 0, // Skip to: 3985 -/* 3977 */ MCD_OPC_CheckPredicate, 0, 207, 17, // Skip to: 8540 -/* 3981 */ MCD_OPC_Decode, 174, 4, 99, // Opcode: CELFBR -/* 3985 */ MCD_OPC_FilterValue, 145, 1, 8, 0, // Skip to: 3998 -/* 3990 */ MCD_OPC_CheckPredicate, 0, 194, 17, // Skip to: 8540 -/* 3994 */ MCD_OPC_Decode, 151, 4, 100, // Opcode: CDLFBR -/* 3998 */ MCD_OPC_FilterValue, 146, 1, 8, 0, // Skip to: 4011 -/* 4003 */ MCD_OPC_CheckPredicate, 0, 181, 17, // Skip to: 8540 -/* 4007 */ MCD_OPC_Decode, 174, 8, 101, // Opcode: CXLFBR -/* 4011 */ MCD_OPC_FilterValue, 148, 1, 18, 0, // Skip to: 4034 -/* 4016 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4026 -/* 4022 */ MCD_OPC_Decode, 168, 4, 102, // Opcode: CEFBR -/* 4026 */ MCD_OPC_CheckPredicate, 0, 158, 17, // Skip to: 8540 -/* 4030 */ MCD_OPC_Decode, 169, 4, 99, // Opcode: CEFBRA -/* 4034 */ MCD_OPC_FilterValue, 149, 1, 18, 0, // Skip to: 4057 -/* 4039 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4049 -/* 4045 */ MCD_OPC_Decode, 142, 4, 103, // Opcode: CDFBR -/* 4049 */ MCD_OPC_CheckPredicate, 0, 135, 17, // Skip to: 8540 -/* 4053 */ MCD_OPC_Decode, 143, 4, 100, // Opcode: CDFBRA -/* 4057 */ MCD_OPC_FilterValue, 150, 1, 18, 0, // Skip to: 4080 -/* 4062 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4072 -/* 4068 */ MCD_OPC_Decode, 165, 8, 104, // Opcode: CXFBR -/* 4072 */ MCD_OPC_CheckPredicate, 0, 112, 17, // Skip to: 8540 -/* 4076 */ MCD_OPC_Decode, 166, 8, 101, // Opcode: CXFBRA -/* 4080 */ MCD_OPC_FilterValue, 152, 1, 18, 0, // Skip to: 4103 -/* 4085 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4095 -/* 4091 */ MCD_OPC_Decode, 183, 4, 105, // Opcode: CFEBR -/* 4095 */ MCD_OPC_CheckPredicate, 0, 89, 17, // Skip to: 8540 -/* 4099 */ MCD_OPC_Decode, 184, 4, 106, // Opcode: CFEBRA -/* 4103 */ MCD_OPC_FilterValue, 153, 1, 18, 0, // Skip to: 4126 -/* 4108 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4118 -/* 4114 */ MCD_OPC_Decode, 179, 4, 107, // Opcode: CFDBR -/* 4118 */ MCD_OPC_CheckPredicate, 0, 66, 17, // Skip to: 8540 -/* 4122 */ MCD_OPC_Decode, 180, 4, 108, // Opcode: CFDBRA -/* 4126 */ MCD_OPC_FilterValue, 154, 1, 18, 0, // Skip to: 4149 -/* 4131 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4141 -/* 4137 */ MCD_OPC_Decode, 187, 4, 109, // Opcode: CFXBR -/* 4141 */ MCD_OPC_CheckPredicate, 0, 43, 17, // Skip to: 8540 -/* 4145 */ MCD_OPC_Decode, 188, 4, 110, // Opcode: CFXBRA -/* 4149 */ MCD_OPC_FilterValue, 156, 1, 8, 0, // Skip to: 4162 -/* 4154 */ MCD_OPC_CheckPredicate, 0, 30, 17, // Skip to: 8540 -/* 4158 */ MCD_OPC_Decode, 231, 5, 106, // Opcode: CLFEBR -/* 4162 */ MCD_OPC_FilterValue, 157, 1, 8, 0, // Skip to: 4175 -/* 4167 */ MCD_OPC_CheckPredicate, 0, 17, 17, // Skip to: 8540 -/* 4171 */ MCD_OPC_Decode, 229, 5, 108, // Opcode: CLFDBR -/* 4175 */ MCD_OPC_FilterValue, 158, 1, 8, 0, // Skip to: 4188 -/* 4180 */ MCD_OPC_CheckPredicate, 0, 4, 17, // Skip to: 8540 -/* 4184 */ MCD_OPC_Decode, 248, 5, 110, // Opcode: CLFXBR -/* 4188 */ MCD_OPC_FilterValue, 160, 1, 8, 0, // Skip to: 4201 -/* 4193 */ MCD_OPC_CheckPredicate, 0, 247, 16, // Skip to: 8540 -/* 4197 */ MCD_OPC_Decode, 175, 4, 111, // Opcode: CELGBR -/* 4201 */ MCD_OPC_FilterValue, 161, 1, 8, 0, // Skip to: 4214 -/* 4206 */ MCD_OPC_CheckPredicate, 0, 234, 16, // Skip to: 8540 -/* 4210 */ MCD_OPC_Decode, 153, 4, 112, // Opcode: CDLGBR -/* 4214 */ MCD_OPC_FilterValue, 162, 1, 8, 0, // Skip to: 4227 -/* 4219 */ MCD_OPC_CheckPredicate, 0, 221, 16, // Skip to: 8540 -/* 4223 */ MCD_OPC_Decode, 176, 8, 113, // Opcode: CXLGBR -/* 4227 */ MCD_OPC_FilterValue, 164, 1, 18, 0, // Skip to: 4250 -/* 4232 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4242 -/* 4238 */ MCD_OPC_Decode, 171, 4, 114, // Opcode: CEGBR -/* 4242 */ MCD_OPC_CheckPredicate, 0, 198, 16, // Skip to: 8540 -/* 4246 */ MCD_OPC_Decode, 172, 4, 111, // Opcode: CEGBRA -/* 4250 */ MCD_OPC_FilterValue, 165, 1, 18, 0, // Skip to: 4273 -/* 4255 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4265 -/* 4261 */ MCD_OPC_Decode, 146, 4, 115, // Opcode: CDGBR -/* 4265 */ MCD_OPC_CheckPredicate, 0, 175, 16, // Skip to: 8540 -/* 4269 */ MCD_OPC_Decode, 147, 4, 112, // Opcode: CDGBRA -/* 4273 */ MCD_OPC_FilterValue, 166, 1, 18, 0, // Skip to: 4296 -/* 4278 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4288 -/* 4284 */ MCD_OPC_Decode, 169, 8, 116, // Opcode: CXGBR -/* 4288 */ MCD_OPC_CheckPredicate, 0, 152, 16, // Skip to: 8540 -/* 4292 */ MCD_OPC_Decode, 170, 8, 113, // Opcode: CXGBRA -/* 4296 */ MCD_OPC_FilterValue, 168, 1, 18, 0, // Skip to: 4319 -/* 4301 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4311 -/* 4307 */ MCD_OPC_Decode, 197, 4, 117, // Opcode: CGEBR -/* 4311 */ MCD_OPC_CheckPredicate, 0, 129, 16, // Skip to: 8540 -/* 4315 */ MCD_OPC_Decode, 198, 4, 118, // Opcode: CGEBRA -/* 4319 */ MCD_OPC_FilterValue, 169, 1, 18, 0, // Skip to: 4342 -/* 4324 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4334 -/* 4330 */ MCD_OPC_Decode, 192, 4, 119, // Opcode: CGDBR -/* 4334 */ MCD_OPC_CheckPredicate, 0, 106, 16, // Skip to: 8540 -/* 4338 */ MCD_OPC_Decode, 193, 4, 120, // Opcode: CGDBRA -/* 4342 */ MCD_OPC_FilterValue, 170, 1, 18, 0, // Skip to: 4365 -/* 4347 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4357 -/* 4353 */ MCD_OPC_Decode, 166, 5, 121, // Opcode: CGXBR -/* 4357 */ MCD_OPC_CheckPredicate, 0, 83, 16, // Skip to: 8540 -/* 4361 */ MCD_OPC_Decode, 167, 5, 122, // Opcode: CGXBRA -/* 4365 */ MCD_OPC_FilterValue, 172, 1, 8, 0, // Skip to: 4378 -/* 4370 */ MCD_OPC_CheckPredicate, 0, 70, 16, // Skip to: 8540 -/* 4374 */ MCD_OPC_Decode, 253, 5, 118, // Opcode: CLGEBR -/* 4378 */ MCD_OPC_FilterValue, 173, 1, 8, 0, // Skip to: 4391 -/* 4383 */ MCD_OPC_CheckPredicate, 0, 57, 16, // Skip to: 8540 -/* 4387 */ MCD_OPC_Decode, 251, 5, 120, // Opcode: CLGDBR -/* 4391 */ MCD_OPC_FilterValue, 174, 1, 8, 0, // Skip to: 4404 -/* 4396 */ MCD_OPC_CheckPredicate, 0, 44, 16, // Skip to: 8540 -/* 4400 */ MCD_OPC_Decode, 232, 6, 122, // Opcode: CLGXBR -/* 4404 */ MCD_OPC_FilterValue, 180, 1, 10, 0, // Skip to: 4419 -/* 4409 */ MCD_OPC_CheckField, 8, 8, 0, 29, 16, // Skip to: 8540 -/* 4415 */ MCD_OPC_Decode, 170, 4, 102, // Opcode: CEFR -/* 4419 */ MCD_OPC_FilterValue, 181, 1, 10, 0, // Skip to: 4434 -/* 4424 */ MCD_OPC_CheckField, 8, 8, 0, 14, 16, // Skip to: 8540 -/* 4430 */ MCD_OPC_Decode, 144, 4, 103, // Opcode: CDFR -/* 4434 */ MCD_OPC_FilterValue, 182, 1, 10, 0, // Skip to: 4449 -/* 4439 */ MCD_OPC_CheckField, 8, 8, 0, 255, 15, // Skip to: 8540 -/* 4445 */ MCD_OPC_Decode, 167, 8, 104, // Opcode: CXFR -/* 4449 */ MCD_OPC_FilterValue, 184, 1, 10, 0, // Skip to: 4464 -/* 4454 */ MCD_OPC_CheckField, 8, 4, 0, 240, 15, // Skip to: 8540 -/* 4460 */ MCD_OPC_Decode, 185, 4, 105, // Opcode: CFER -/* 4464 */ MCD_OPC_FilterValue, 185, 1, 10, 0, // Skip to: 4479 -/* 4469 */ MCD_OPC_CheckField, 8, 4, 0, 225, 15, // Skip to: 8540 -/* 4475 */ MCD_OPC_Decode, 181, 4, 107, // Opcode: CFDR -/* 4479 */ MCD_OPC_FilterValue, 186, 1, 10, 0, // Skip to: 4494 -/* 4484 */ MCD_OPC_CheckField, 8, 4, 0, 210, 15, // Skip to: 8540 -/* 4490 */ MCD_OPC_Decode, 189, 4, 109, // Opcode: CFXR -/* 4494 */ MCD_OPC_FilterValue, 193, 1, 10, 0, // Skip to: 4509 -/* 4499 */ MCD_OPC_CheckField, 8, 8, 0, 195, 15, // Skip to: 8540 -/* 4505 */ MCD_OPC_Decode, 153, 10, 115, // Opcode: LDGR -/* 4509 */ MCD_OPC_FilterValue, 196, 1, 10, 0, // Skip to: 4524 -/* 4514 */ MCD_OPC_CheckField, 8, 8, 0, 180, 15, // Skip to: 8540 -/* 4520 */ MCD_OPC_Decode, 173, 4, 114, // Opcode: CEGR -/* 4524 */ MCD_OPC_FilterValue, 197, 1, 10, 0, // Skip to: 4539 -/* 4529 */ MCD_OPC_CheckField, 8, 8, 0, 165, 15, // Skip to: 8540 -/* 4535 */ MCD_OPC_Decode, 148, 4, 115, // Opcode: CDGR -/* 4539 */ MCD_OPC_FilterValue, 198, 1, 10, 0, // Skip to: 4554 -/* 4544 */ MCD_OPC_CheckField, 8, 8, 0, 150, 15, // Skip to: 8540 -/* 4550 */ MCD_OPC_Decode, 171, 8, 116, // Opcode: CXGR -/* 4554 */ MCD_OPC_FilterValue, 200, 1, 10, 0, // Skip to: 4569 -/* 4559 */ MCD_OPC_CheckField, 8, 4, 0, 135, 15, // Skip to: 8540 -/* 4565 */ MCD_OPC_Decode, 199, 4, 117, // Opcode: CGER -/* 4569 */ MCD_OPC_FilterValue, 201, 1, 10, 0, // Skip to: 4584 -/* 4574 */ MCD_OPC_CheckField, 8, 4, 0, 120, 15, // Skip to: 8540 -/* 4580 */ MCD_OPC_Decode, 194, 4, 119, // Opcode: CGDR -/* 4584 */ MCD_OPC_FilterValue, 202, 1, 10, 0, // Skip to: 4599 -/* 4589 */ MCD_OPC_CheckField, 8, 4, 0, 105, 15, // Skip to: 8540 -/* 4595 */ MCD_OPC_Decode, 168, 5, 121, // Opcode: CGXR -/* 4599 */ MCD_OPC_FilterValue, 205, 1, 10, 0, // Skip to: 4614 -/* 4604 */ MCD_OPC_CheckField, 8, 8, 0, 90, 15, // Skip to: 8540 -/* 4610 */ MCD_OPC_Decode, 179, 10, 123, // Opcode: LGDR -/* 4614 */ MCD_OPC_FilterValue, 208, 1, 18, 0, // Skip to: 4637 -/* 4619 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4629 -/* 4625 */ MCD_OPC_Decode, 146, 13, 95, // Opcode: MDTR -/* 4629 */ MCD_OPC_CheckPredicate, 0, 67, 15, // Skip to: 8540 -/* 4633 */ MCD_OPC_Decode, 147, 13, 124, // Opcode: MDTRA -/* 4637 */ MCD_OPC_FilterValue, 209, 1, 18, 0, // Skip to: 4660 -/* 4642 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4652 -/* 4648 */ MCD_OPC_Decode, 192, 8, 95, // Opcode: DDTR -/* 4652 */ MCD_OPC_CheckPredicate, 0, 44, 15, // Skip to: 8540 -/* 4656 */ MCD_OPC_Decode, 193, 8, 124, // Opcode: DDTRA -/* 4660 */ MCD_OPC_FilterValue, 210, 1, 18, 0, // Skip to: 4683 -/* 4665 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4675 -/* 4671 */ MCD_OPC_Decode, 233, 2, 95, // Opcode: ADTR -/* 4675 */ MCD_OPC_CheckPredicate, 0, 21, 15, // Skip to: 8540 -/* 4679 */ MCD_OPC_Decode, 234, 2, 124, // Opcode: ADTRA -/* 4683 */ MCD_OPC_FilterValue, 211, 1, 18, 0, // Skip to: 4706 -/* 4688 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4698 -/* 4694 */ MCD_OPC_Decode, 194, 14, 95, // Opcode: SDTR -/* 4698 */ MCD_OPC_CheckPredicate, 0, 254, 14, // Skip to: 8540 -/* 4702 */ MCD_OPC_Decode, 195, 14, 124, // Opcode: SDTRA -/* 4706 */ MCD_OPC_FilterValue, 212, 1, 10, 0, // Skip to: 4721 -/* 4711 */ MCD_OPC_CheckField, 12, 4, 0, 239, 14, // Skip to: 8540 -/* 4717 */ MCD_OPC_Decode, 152, 10, 125, // Opcode: LDETR -/* 4721 */ MCD_OPC_FilterValue, 213, 1, 4, 0, // Skip to: 4730 -/* 4726 */ MCD_OPC_Decode, 165, 10, 84, // Opcode: LEDTR -/* 4730 */ MCD_OPC_FilterValue, 214, 1, 10, 0, // Skip to: 4745 -/* 4735 */ MCD_OPC_CheckField, 8, 8, 0, 215, 14, // Skip to: 8540 -/* 4741 */ MCD_OPC_Decode, 219, 12, 11, // Opcode: LTDTR -/* 4745 */ MCD_OPC_FilterValue, 215, 1, 4, 0, // Skip to: 4754 -/* 4750 */ MCD_OPC_Decode, 243, 8, 93, // Opcode: FIDTR -/* 4754 */ MCD_OPC_FilterValue, 216, 1, 18, 0, // Skip to: 4777 -/* 4759 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4769 -/* 4765 */ MCD_OPC_Decode, 218, 13, 126, // Opcode: MXTR -/* 4769 */ MCD_OPC_CheckPredicate, 0, 183, 14, // Skip to: 8540 -/* 4773 */ MCD_OPC_Decode, 219, 13, 127, // Opcode: MXTRA -/* 4777 */ MCD_OPC_FilterValue, 217, 1, 18, 0, // Skip to: 4800 -/* 4782 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4792 -/* 4788 */ MCD_OPC_Decode, 213, 8, 126, // Opcode: DXTR -/* 4792 */ MCD_OPC_CheckPredicate, 0, 160, 14, // Skip to: 8540 -/* 4796 */ MCD_OPC_Decode, 214, 8, 127, // Opcode: DXTRA -/* 4800 */ MCD_OPC_FilterValue, 218, 1, 18, 0, // Skip to: 4823 -/* 4805 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4815 -/* 4811 */ MCD_OPC_Decode, 162, 3, 126, // Opcode: AXTR -/* 4815 */ MCD_OPC_CheckPredicate, 0, 137, 14, // Skip to: 8540 -/* 4819 */ MCD_OPC_Decode, 163, 3, 127, // Opcode: AXTRA -/* 4823 */ MCD_OPC_FilterValue, 219, 1, 18, 0, // Skip to: 4846 -/* 4828 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4838 -/* 4834 */ MCD_OPC_Decode, 152, 16, 126, // Opcode: SXTR -/* 4838 */ MCD_OPC_CheckPredicate, 0, 114, 14, // Skip to: 8540 -/* 4842 */ MCD_OPC_Decode, 153, 16, 127, // Opcode: SXTRA -/* 4846 */ MCD_OPC_FilterValue, 220, 1, 11, 0, // Skip to: 4862 -/* 4851 */ MCD_OPC_CheckField, 12, 4, 0, 99, 14, // Skip to: 8540 -/* 4857 */ MCD_OPC_Decode, 238, 12, 128, 1, // Opcode: LXDTR -/* 4862 */ MCD_OPC_FilterValue, 221, 1, 4, 0, // Skip to: 4871 -/* 4867 */ MCD_OPC_Decode, 159, 10, 85, // Opcode: LDXTR -/* 4871 */ MCD_OPC_FilterValue, 222, 1, 10, 0, // Skip to: 4886 -/* 4876 */ MCD_OPC_CheckField, 8, 8, 0, 74, 14, // Skip to: 8540 -/* 4882 */ MCD_OPC_Decode, 231, 12, 79, // Opcode: LTXTR -/* 4886 */ MCD_OPC_FilterValue, 223, 1, 4, 0, // Skip to: 4895 -/* 4891 */ MCD_OPC_Decode, 250, 8, 85, // Opcode: FIXTR -/* 4895 */ MCD_OPC_FilterValue, 224, 1, 10, 0, // Skip to: 4910 -/* 4900 */ MCD_OPC_CheckField, 8, 8, 0, 50, 14, // Skip to: 8540 -/* 4906 */ MCD_OPC_Decode, 222, 9, 11, // Opcode: KDTR -/* 4910 */ MCD_OPC_FilterValue, 225, 1, 18, 0, // Skip to: 4933 -/* 4915 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4925 -/* 4921 */ MCD_OPC_Decode, 195, 4, 119, // Opcode: CGDTR -/* 4925 */ MCD_OPC_CheckPredicate, 0, 27, 14, // Skip to: 8540 -/* 4929 */ MCD_OPC_Decode, 196, 4, 120, // Opcode: CGDTRA -/* 4933 */ MCD_OPC_FilterValue, 226, 1, 10, 0, // Skip to: 4948 -/* 4938 */ MCD_OPC_CheckField, 8, 8, 0, 12, 14, // Skip to: 8540 -/* 4944 */ MCD_OPC_Decode, 151, 8, 123, // Opcode: CUDTR -/* 4948 */ MCD_OPC_FilterValue, 227, 1, 11, 0, // Skip to: 4964 -/* 4953 */ MCD_OPC_CheckField, 12, 4, 0, 253, 13, // Skip to: 8540 -/* 4959 */ MCD_OPC_Decode, 134, 8, 129, 1, // Opcode: CSDTR -/* 4964 */ MCD_OPC_FilterValue, 228, 1, 10, 0, // Skip to: 4979 -/* 4969 */ MCD_OPC_CheckField, 8, 8, 0, 237, 13, // Skip to: 8540 -/* 4975 */ MCD_OPC_Decode, 161, 4, 11, // Opcode: CDTR -/* 4979 */ MCD_OPC_FilterValue, 229, 1, 10, 0, // Skip to: 4994 -/* 4984 */ MCD_OPC_CheckField, 8, 8, 0, 222, 13, // Skip to: 8540 -/* 4990 */ MCD_OPC_Decode, 222, 8, 11, // Opcode: EEDTR -/* 4994 */ MCD_OPC_FilterValue, 231, 1, 10, 0, // Skip to: 5009 -/* 4999 */ MCD_OPC_CheckField, 8, 8, 0, 207, 13, // Skip to: 8540 -/* 5005 */ MCD_OPC_Decode, 233, 8, 11, // Opcode: ESDTR -/* 5009 */ MCD_OPC_FilterValue, 232, 1, 10, 0, // Skip to: 5024 -/* 5014 */ MCD_OPC_CheckField, 8, 8, 0, 192, 13, // Skip to: 8540 -/* 5020 */ MCD_OPC_Decode, 235, 9, 79, // Opcode: KXTR -/* 5024 */ MCD_OPC_FilterValue, 233, 1, 18, 0, // Skip to: 5047 -/* 5029 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 5039 -/* 5035 */ MCD_OPC_Decode, 169, 5, 121, // Opcode: CGXTR -/* 5039 */ MCD_OPC_CheckPredicate, 0, 169, 13, // Skip to: 8540 -/* 5043 */ MCD_OPC_Decode, 170, 5, 122, // Opcode: CGXTRA -/* 5047 */ MCD_OPC_FilterValue, 234, 1, 11, 0, // Skip to: 5063 -/* 5052 */ MCD_OPC_CheckField, 8, 8, 0, 154, 13, // Skip to: 8540 -/* 5058 */ MCD_OPC_Decode, 157, 8, 130, 1, // Opcode: CUXTR -/* 5063 */ MCD_OPC_FilterValue, 235, 1, 11, 0, // Skip to: 5079 -/* 5068 */ MCD_OPC_CheckField, 12, 4, 0, 138, 13, // Skip to: 8540 -/* 5074 */ MCD_OPC_Decode, 139, 8, 131, 1, // Opcode: CSXTR -/* 5079 */ MCD_OPC_FilterValue, 236, 1, 10, 0, // Skip to: 5094 -/* 5084 */ MCD_OPC_CheckField, 8, 8, 0, 122, 13, // Skip to: 8540 -/* 5090 */ MCD_OPC_Decode, 181, 8, 79, // Opcode: CXTR -/* 5094 */ MCD_OPC_FilterValue, 237, 1, 10, 0, // Skip to: 5109 -/* 5099 */ MCD_OPC_CheckField, 8, 8, 0, 107, 13, // Skip to: 8540 -/* 5105 */ MCD_OPC_Decode, 223, 8, 79, // Opcode: EEXTR -/* 5109 */ MCD_OPC_FilterValue, 239, 1, 10, 0, // Skip to: 5124 -/* 5114 */ MCD_OPC_CheckField, 8, 8, 0, 92, 13, // Skip to: 8540 -/* 5120 */ MCD_OPC_Decode, 236, 8, 79, // Opcode: ESXTR -/* 5124 */ MCD_OPC_FilterValue, 241, 1, 18, 0, // Skip to: 5147 -/* 5129 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 5139 -/* 5135 */ MCD_OPC_Decode, 149, 4, 115, // Opcode: CDGTR -/* 5139 */ MCD_OPC_CheckPredicate, 0, 69, 13, // Skip to: 8540 -/* 5143 */ MCD_OPC_Decode, 150, 4, 112, // Opcode: CDGTRA -/* 5147 */ MCD_OPC_FilterValue, 242, 1, 10, 0, // Skip to: 5162 -/* 5152 */ MCD_OPC_CheckField, 8, 8, 0, 54, 13, // Skip to: 8540 -/* 5158 */ MCD_OPC_Decode, 162, 4, 115, // Opcode: CDUTR -/* 5162 */ MCD_OPC_FilterValue, 243, 1, 10, 0, // Skip to: 5177 -/* 5167 */ MCD_OPC_CheckField, 8, 8, 0, 39, 13, // Skip to: 8540 -/* 5173 */ MCD_OPC_Decode, 159, 4, 115, // Opcode: CDSTR -/* 5177 */ MCD_OPC_FilterValue, 244, 1, 10, 0, // Skip to: 5192 -/* 5182 */ MCD_OPC_CheckField, 8, 8, 0, 24, 13, // Skip to: 8540 -/* 5188 */ MCD_OPC_Decode, 167, 4, 11, // Opcode: CEDTR -/* 5192 */ MCD_OPC_FilterValue, 245, 1, 4, 0, // Skip to: 5201 -/* 5197 */ MCD_OPC_Decode, 156, 14, 92, // Opcode: QADTR -/* 5201 */ MCD_OPC_FilterValue, 246, 1, 10, 0, // Skip to: 5216 -/* 5206 */ MCD_OPC_CheckField, 8, 4, 0, 0, 13, // Skip to: 8540 -/* 5212 */ MCD_OPC_Decode, 137, 9, 95, // Opcode: IEDTR -/* 5216 */ MCD_OPC_FilterValue, 247, 1, 4, 0, // Skip to: 5225 -/* 5221 */ MCD_OPC_Decode, 173, 14, 92, // Opcode: RRDTR -/* 5225 */ MCD_OPC_FilterValue, 249, 1, 18, 0, // Skip to: 5248 -/* 5230 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 5240 -/* 5236 */ MCD_OPC_Decode, 172, 8, 116, // Opcode: CXGTR -/* 5240 */ MCD_OPC_CheckPredicate, 0, 224, 12, // Skip to: 8540 -/* 5244 */ MCD_OPC_Decode, 173, 8, 113, // Opcode: CXGTRA -/* 5248 */ MCD_OPC_FilterValue, 250, 1, 11, 0, // Skip to: 5264 -/* 5253 */ MCD_OPC_CheckField, 8, 8, 0, 209, 12, // Skip to: 8540 -/* 5259 */ MCD_OPC_Decode, 182, 8, 132, 1, // Opcode: CXUTR -/* 5264 */ MCD_OPC_FilterValue, 251, 1, 11, 0, // Skip to: 5280 -/* 5269 */ MCD_OPC_CheckField, 8, 8, 0, 193, 12, // Skip to: 8540 -/* 5275 */ MCD_OPC_Decode, 180, 8, 132, 1, // Opcode: CXSTR -/* 5280 */ MCD_OPC_FilterValue, 252, 1, 10, 0, // Skip to: 5295 -/* 5285 */ MCD_OPC_CheckField, 8, 8, 0, 177, 12, // Skip to: 8540 -/* 5291 */ MCD_OPC_Decode, 177, 4, 79, // Opcode: CEXTR -/* 5295 */ MCD_OPC_FilterValue, 253, 1, 5, 0, // Skip to: 5305 -/* 5300 */ MCD_OPC_Decode, 157, 14, 133, 1, // Opcode: QAXTR -/* 5305 */ MCD_OPC_FilterValue, 254, 1, 10, 0, // Skip to: 5320 -/* 5310 */ MCD_OPC_CheckField, 8, 4, 0, 152, 12, // Skip to: 8540 -/* 5316 */ MCD_OPC_Decode, 138, 9, 126, // Opcode: IEXTR -/* 5320 */ MCD_OPC_FilterValue, 255, 1, 143, 12, // Skip to: 8540 -/* 5325 */ MCD_OPC_Decode, 174, 14, 133, 1, // Opcode: RRXTR -/* 5330 */ MCD_OPC_FilterValue, 182, 1, 5, 0, // Skip to: 5340 -/* 5335 */ MCD_OPC_Decode, 170, 15, 134, 1, // Opcode: STCTL -/* 5340 */ MCD_OPC_FilterValue, 183, 1, 5, 0, // Skip to: 5350 -/* 5345 */ MCD_OPC_Decode, 142, 10, 134, 1, // Opcode: LCTL -/* 5350 */ MCD_OPC_FilterValue, 185, 1, 64, 12, // Skip to: 8491 -/* 5355 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 5358 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5372 -/* 5362 */ MCD_OPC_CheckField, 8, 8, 0, 100, 12, // Skip to: 8540 -/* 5368 */ MCD_OPC_Decode, 193, 12, 61, // Opcode: LPGR -/* 5372 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 5386 -/* 5376 */ MCD_OPC_CheckField, 8, 8, 0, 86, 12, // Skip to: 8540 -/* 5382 */ MCD_OPC_Decode, 237, 10, 61, // Opcode: LNGR -/* 5386 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 5400 -/* 5390 */ MCD_OPC_CheckField, 8, 8, 0, 72, 12, // Skip to: 8540 -/* 5396 */ MCD_OPC_Decode, 226, 12, 61, // Opcode: LTGR -/* 5400 */ MCD_OPC_FilterValue, 3, 10, 0, // Skip to: 5414 -/* 5404 */ MCD_OPC_CheckField, 8, 8, 0, 58, 12, // Skip to: 8540 -/* 5410 */ MCD_OPC_Decode, 140, 10, 61, // Opcode: LCGR -/* 5414 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 5428 -/* 5418 */ MCD_OPC_CheckField, 8, 8, 0, 44, 12, // Skip to: 8540 -/* 5424 */ MCD_OPC_Decode, 189, 10, 61, // Opcode: LGR -/* 5428 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 5442 -/* 5432 */ MCD_OPC_CheckField, 8, 8, 0, 30, 12, // Skip to: 8540 -/* 5438 */ MCD_OPC_Decode, 233, 12, 61, // Opcode: LURAG -/* 5442 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 5456 -/* 5446 */ MCD_OPC_CheckField, 8, 8, 0, 16, 12, // Skip to: 8540 -/* 5452 */ MCD_OPC_Decode, 178, 10, 61, // Opcode: LGBR -/* 5456 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 5470 -/* 5460 */ MCD_OPC_CheckField, 8, 8, 0, 2, 12, // Skip to: 8540 -/* 5466 */ MCD_OPC_Decode, 187, 10, 61, // Opcode: LGHR -/* 5470 */ MCD_OPC_FilterValue, 8, 11, 0, // Skip to: 5485 -/* 5474 */ MCD_OPC_CheckField, 8, 8, 0, 244, 11, // Skip to: 8540 -/* 5480 */ MCD_OPC_Decode, 247, 2, 135, 1, // Opcode: AGR -/* 5485 */ MCD_OPC_FilterValue, 9, 11, 0, // Skip to: 5500 -/* 5489 */ MCD_OPC_CheckField, 8, 8, 0, 229, 11, // Skip to: 8540 -/* 5495 */ MCD_OPC_Decode, 206, 14, 135, 1, // Opcode: SGR -/* 5500 */ MCD_OPC_FilterValue, 10, 11, 0, // Skip to: 5515 -/* 5504 */ MCD_OPC_CheckField, 8, 8, 0, 214, 11, // Skip to: 8540 -/* 5510 */ MCD_OPC_Decode, 140, 3, 135, 1, // Opcode: ALGR -/* 5515 */ MCD_OPC_FilterValue, 11, 11, 0, // Skip to: 5530 -/* 5519 */ MCD_OPC_CheckField, 8, 8, 0, 199, 11, // Skip to: 8540 -/* 5525 */ MCD_OPC_Decode, 231, 14, 135, 1, // Opcode: SLGR -/* 5530 */ MCD_OPC_FilterValue, 12, 11, 0, // Skip to: 5545 -/* 5534 */ MCD_OPC_CheckField, 8, 8, 0, 184, 11, // Skip to: 8540 -/* 5540 */ MCD_OPC_Decode, 185, 13, 135, 1, // Opcode: MSGR -/* 5545 */ MCD_OPC_FilterValue, 13, 10, 0, // Skip to: 5559 -/* 5549 */ MCD_OPC_CheckField, 8, 8, 0, 169, 11, // Skip to: 8540 -/* 5555 */ MCD_OPC_Decode, 210, 8, 68, // Opcode: DSGR -/* 5559 */ MCD_OPC_FilterValue, 14, 10, 0, // Skip to: 5573 -/* 5563 */ MCD_OPC_CheckField, 8, 8, 0, 155, 11, // Skip to: 8540 -/* 5569 */ MCD_OPC_Decode, 230, 8, 61, // Opcode: EREGG -/* 5573 */ MCD_OPC_FilterValue, 15, 10, 0, // Skip to: 5587 -/* 5577 */ MCD_OPC_CheckField, 8, 8, 0, 141, 11, // Skip to: 8540 -/* 5583 */ MCD_OPC_Decode, 211, 12, 61, // Opcode: LRVGR -/* 5587 */ MCD_OPC_FilterValue, 16, 10, 0, // Skip to: 5601 -/* 5591 */ MCD_OPC_CheckField, 8, 8, 0, 127, 11, // Skip to: 8540 -/* 5597 */ MCD_OPC_Decode, 192, 12, 56, // Opcode: LPGFR -/* 5601 */ MCD_OPC_FilterValue, 17, 10, 0, // Skip to: 5615 -/* 5605 */ MCD_OPC_CheckField, 8, 8, 0, 113, 11, // Skip to: 8540 -/* 5611 */ MCD_OPC_Decode, 236, 10, 56, // Opcode: LNGFR -/* 5615 */ MCD_OPC_FilterValue, 18, 10, 0, // Skip to: 5629 -/* 5619 */ MCD_OPC_CheckField, 8, 8, 0, 99, 11, // Skip to: 8540 -/* 5625 */ MCD_OPC_Decode, 225, 12, 56, // Opcode: LTGFR -/* 5629 */ MCD_OPC_FilterValue, 19, 10, 0, // Skip to: 5643 -/* 5633 */ MCD_OPC_CheckField, 8, 8, 0, 85, 11, // Skip to: 8540 -/* 5639 */ MCD_OPC_Decode, 139, 10, 56, // Opcode: LCGFR -/* 5643 */ MCD_OPC_FilterValue, 20, 10, 0, // Skip to: 5657 -/* 5647 */ MCD_OPC_CheckField, 8, 8, 0, 71, 11, // Skip to: 8540 -/* 5653 */ MCD_OPC_Decode, 182, 10, 56, // Opcode: LGFR -/* 5657 */ MCD_OPC_FilterValue, 22, 10, 0, // Skip to: 5671 -/* 5661 */ MCD_OPC_CheckField, 8, 8, 0, 57, 11, // Skip to: 8540 -/* 5667 */ MCD_OPC_Decode, 205, 10, 56, // Opcode: LLGFR -/* 5671 */ MCD_OPC_FilterValue, 23, 10, 0, // Skip to: 5685 -/* 5675 */ MCD_OPC_CheckField, 8, 8, 0, 43, 11, // Skip to: 8540 -/* 5681 */ MCD_OPC_Decode, 213, 10, 61, // Opcode: LLGTR -/* 5685 */ MCD_OPC_FilterValue, 24, 11, 0, // Skip to: 5700 -/* 5689 */ MCD_OPC_CheckField, 8, 8, 0, 29, 11, // Skip to: 8540 -/* 5695 */ MCD_OPC_Decode, 243, 2, 136, 1, // Opcode: AGFR -/* 5700 */ MCD_OPC_FilterValue, 25, 11, 0, // Skip to: 5715 -/* 5704 */ MCD_OPC_CheckField, 8, 8, 0, 14, 11, // Skip to: 8540 -/* 5710 */ MCD_OPC_Decode, 204, 14, 136, 1, // Opcode: SGFR -/* 5715 */ MCD_OPC_FilterValue, 26, 11, 0, // Skip to: 5730 -/* 5719 */ MCD_OPC_CheckField, 8, 8, 0, 255, 10, // Skip to: 8540 -/* 5725 */ MCD_OPC_Decode, 138, 3, 136, 1, // Opcode: ALGFR -/* 5730 */ MCD_OPC_FilterValue, 27, 11, 0, // Skip to: 5745 -/* 5734 */ MCD_OPC_CheckField, 8, 8, 0, 240, 10, // Skip to: 8540 -/* 5740 */ MCD_OPC_Decode, 230, 14, 136, 1, // Opcode: SLGFR -/* 5745 */ MCD_OPC_FilterValue, 28, 11, 0, // Skip to: 5760 -/* 5749 */ MCD_OPC_CheckField, 8, 8, 0, 225, 10, // Skip to: 8540 -/* 5755 */ MCD_OPC_Decode, 184, 13, 136, 1, // Opcode: MSGFR -/* 5760 */ MCD_OPC_FilterValue, 29, 10, 0, // Skip to: 5774 -/* 5764 */ MCD_OPC_CheckField, 8, 8, 0, 210, 10, // Skip to: 8540 -/* 5770 */ MCD_OPC_Decode, 209, 8, 10, // Opcode: DSGFR -/* 5774 */ MCD_OPC_FilterValue, 30, 11, 0, // Skip to: 5789 -/* 5778 */ MCD_OPC_CheckField, 8, 8, 0, 196, 10, // Skip to: 8540 -/* 5784 */ MCD_OPC_Decode, 229, 9, 137, 1, // Opcode: KMAC -/* 5789 */ MCD_OPC_FilterValue, 31, 10, 0, // Skip to: 5803 -/* 5793 */ MCD_OPC_CheckField, 8, 8, 0, 181, 10, // Skip to: 8540 -/* 5799 */ MCD_OPC_Decode, 213, 12, 8, // Opcode: LRVR -/* 5803 */ MCD_OPC_FilterValue, 32, 10, 0, // Skip to: 5817 -/* 5807 */ MCD_OPC_CheckField, 8, 8, 0, 167, 10, // Skip to: 8540 -/* 5813 */ MCD_OPC_Decode, 250, 4, 61, // Opcode: CGR -/* 5817 */ MCD_OPC_FilterValue, 33, 10, 0, // Skip to: 5831 -/* 5821 */ MCD_OPC_CheckField, 8, 8, 0, 153, 10, // Skip to: 8540 -/* 5827 */ MCD_OPC_Decode, 174, 6, 61, // Opcode: CLGR -/* 5831 */ MCD_OPC_FilterValue, 37, 10, 0, // Skip to: 5845 -/* 5835 */ MCD_OPC_CheckField, 8, 8, 0, 139, 10, // Skip to: 8540 -/* 5841 */ MCD_OPC_Decode, 143, 16, 61, // Opcode: STURG -/* 5845 */ MCD_OPC_FilterValue, 38, 10, 0, // Skip to: 5859 -/* 5849 */ MCD_OPC_CheckField, 8, 8, 0, 125, 10, // Skip to: 8540 -/* 5855 */ MCD_OPC_Decode, 130, 10, 8, // Opcode: LBR -/* 5859 */ MCD_OPC_FilterValue, 39, 10, 0, // Skip to: 5873 -/* 5863 */ MCD_OPC_CheckField, 8, 8, 0, 111, 10, // Skip to: 8540 -/* 5869 */ MCD_OPC_Decode, 195, 10, 8, // Opcode: LHR -/* 5873 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 5891 -/* 5877 */ MCD_OPC_CheckPredicate, 4, 99, 10, // Skip to: 8540 -/* 5881 */ MCD_OPC_CheckField, 0, 16, 0, 93, 10, // Skip to: 8540 -/* 5887 */ MCD_OPC_Decode, 136, 14, 0, // Opcode: PCKMO -/* 5891 */ MCD_OPC_FilterValue, 41, 15, 0, // Skip to: 5910 -/* 5895 */ MCD_OPC_CheckPredicate, 5, 81, 10, // Skip to: 8540 -/* 5899 */ MCD_OPC_CheckField, 8, 4, 0, 75, 10, // Skip to: 8540 -/* 5905 */ MCD_OPC_Decode, 228, 9, 138, 1, // Opcode: KMA -/* 5910 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 5928 -/* 5914 */ MCD_OPC_CheckPredicate, 6, 62, 10, // Skip to: 8540 -/* 5918 */ MCD_OPC_CheckField, 8, 8, 0, 56, 10, // Skip to: 8540 -/* 5924 */ MCD_OPC_Decode, 232, 9, 7, // Opcode: KMF -/* 5928 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 5946 -/* 5932 */ MCD_OPC_CheckPredicate, 6, 44, 10, // Skip to: 8540 -/* 5936 */ MCD_OPC_CheckField, 8, 8, 0, 38, 10, // Skip to: 8540 -/* 5942 */ MCD_OPC_Decode, 233, 9, 7, // Opcode: KMO -/* 5946 */ MCD_OPC_FilterValue, 44, 14, 0, // Skip to: 5964 -/* 5950 */ MCD_OPC_CheckPredicate, 6, 26, 10, // Skip to: 8540 -/* 5954 */ MCD_OPC_CheckField, 0, 16, 0, 20, 10, // Skip to: 8540 -/* 5960 */ MCD_OPC_Decode, 135, 14, 0, // Opcode: PCC -/* 5964 */ MCD_OPC_FilterValue, 45, 15, 0, // Skip to: 5983 -/* 5968 */ MCD_OPC_CheckPredicate, 6, 8, 10, // Skip to: 8540 -/* 5972 */ MCD_OPC_CheckField, 8, 4, 0, 2, 10, // Skip to: 8540 -/* 5978 */ MCD_OPC_Decode, 231, 9, 138, 1, // Opcode: KMCTR -/* 5983 */ MCD_OPC_FilterValue, 46, 10, 0, // Skip to: 5997 -/* 5987 */ MCD_OPC_CheckField, 8, 8, 0, 243, 9, // Skip to: 8540 -/* 5993 */ MCD_OPC_Decode, 227, 9, 7, // Opcode: KM -/* 5997 */ MCD_OPC_FilterValue, 47, 10, 0, // Skip to: 6011 -/* 6001 */ MCD_OPC_CheckField, 8, 8, 0, 229, 9, // Skip to: 8540 -/* 6007 */ MCD_OPC_Decode, 230, 9, 7, // Opcode: KMC -/* 6011 */ MCD_OPC_FilterValue, 48, 10, 0, // Skip to: 6025 -/* 6015 */ MCD_OPC_CheckField, 8, 8, 0, 215, 9, // Skip to: 8540 -/* 6021 */ MCD_OPC_Decode, 202, 4, 56, // Opcode: CGFR -/* 6025 */ MCD_OPC_FilterValue, 49, 10, 0, // Skip to: 6039 -/* 6029 */ MCD_OPC_CheckField, 8, 8, 0, 201, 9, // Skip to: 8540 -/* 6035 */ MCD_OPC_Decode, 128, 6, 56, // Opcode: CLGFR -/* 6039 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 6057 -/* 6043 */ MCD_OPC_CheckPredicate, 7, 189, 9, // Skip to: 8540 -/* 6047 */ MCD_OPC_CheckField, 8, 8, 0, 183, 9, // Skip to: 8540 -/* 6053 */ MCD_OPC_Decode, 148, 14, 7, // Opcode: PPNO -/* 6057 */ MCD_OPC_FilterValue, 62, 11, 0, // Skip to: 6072 -/* 6061 */ MCD_OPC_CheckField, 8, 8, 0, 169, 9, // Skip to: 8540 -/* 6067 */ MCD_OPC_Decode, 225, 9, 137, 1, // Opcode: KIMD -/* 6072 */ MCD_OPC_FilterValue, 63, 11, 0, // Skip to: 6087 -/* 6076 */ MCD_OPC_CheckField, 8, 8, 0, 154, 9, // Skip to: 8540 -/* 6082 */ MCD_OPC_Decode, 226, 9, 137, 1, // Opcode: KLMD -/* 6087 */ MCD_OPC_FilterValue, 65, 8, 0, // Skip to: 6099 -/* 6091 */ MCD_OPC_CheckPredicate, 0, 141, 9, // Skip to: 8540 -/* 6095 */ MCD_OPC_Decode, 182, 4, 108, // Opcode: CFDTR -/* 6099 */ MCD_OPC_FilterValue, 66, 8, 0, // Skip to: 6111 -/* 6103 */ MCD_OPC_CheckPredicate, 0, 129, 9, // Skip to: 8540 -/* 6107 */ MCD_OPC_Decode, 252, 5, 120, // Opcode: CLGDTR -/* 6111 */ MCD_OPC_FilterValue, 67, 8, 0, // Skip to: 6123 -/* 6115 */ MCD_OPC_CheckPredicate, 0, 117, 9, // Skip to: 8540 -/* 6119 */ MCD_OPC_Decode, 230, 5, 108, // Opcode: CLFDTR -/* 6123 */ MCD_OPC_FilterValue, 70, 11, 0, // Skip to: 6138 -/* 6127 */ MCD_OPC_CheckField, 8, 8, 0, 103, 9, // Skip to: 8540 -/* 6133 */ MCD_OPC_Decode, 198, 3, 135, 1, // Opcode: BCTGR -/* 6138 */ MCD_OPC_FilterValue, 73, 8, 0, // Skip to: 6150 -/* 6142 */ MCD_OPC_CheckPredicate, 0, 90, 9, // Skip to: 8540 -/* 6146 */ MCD_OPC_Decode, 190, 4, 110, // Opcode: CFXTR -/* 6150 */ MCD_OPC_FilterValue, 74, 8, 0, // Skip to: 6162 -/* 6154 */ MCD_OPC_CheckPredicate, 0, 78, 9, // Skip to: 8540 -/* 6158 */ MCD_OPC_Decode, 233, 6, 122, // Opcode: CLGXTR -/* 6162 */ MCD_OPC_FilterValue, 75, 8, 0, // Skip to: 6174 -/* 6166 */ MCD_OPC_CheckPredicate, 0, 66, 9, // Skip to: 8540 -/* 6170 */ MCD_OPC_Decode, 249, 5, 110, // Opcode: CLFXTR -/* 6174 */ MCD_OPC_FilterValue, 81, 8, 0, // Skip to: 6186 -/* 6178 */ MCD_OPC_CheckPredicate, 0, 54, 9, // Skip to: 8540 -/* 6182 */ MCD_OPC_Decode, 145, 4, 100, // Opcode: CDFTR -/* 6186 */ MCD_OPC_FilterValue, 82, 8, 0, // Skip to: 6198 -/* 6190 */ MCD_OPC_CheckPredicate, 0, 42, 9, // Skip to: 8540 -/* 6194 */ MCD_OPC_Decode, 154, 4, 112, // Opcode: CDLGTR -/* 6198 */ MCD_OPC_FilterValue, 83, 8, 0, // Skip to: 6210 -/* 6202 */ MCD_OPC_CheckPredicate, 0, 30, 9, // Skip to: 8540 -/* 6206 */ MCD_OPC_Decode, 152, 4, 100, // Opcode: CDLFTR -/* 6210 */ MCD_OPC_FilterValue, 89, 8, 0, // Skip to: 6222 -/* 6214 */ MCD_OPC_CheckPredicate, 0, 18, 9, // Skip to: 8540 -/* 6218 */ MCD_OPC_Decode, 168, 8, 101, // Opcode: CXFTR -/* 6222 */ MCD_OPC_FilterValue, 90, 8, 0, // Skip to: 6234 -/* 6226 */ MCD_OPC_CheckPredicate, 0, 6, 9, // Skip to: 8540 -/* 6230 */ MCD_OPC_Decode, 177, 8, 113, // Opcode: CXLGTR -/* 6234 */ MCD_OPC_FilterValue, 91, 8, 0, // Skip to: 6246 -/* 6238 */ MCD_OPC_CheckPredicate, 0, 250, 8, // Skip to: 8540 -/* 6242 */ MCD_OPC_Decode, 175, 8, 101, // Opcode: CXLFTR -/* 6246 */ MCD_OPC_FilterValue, 96, 62, 0, // Skip to: 6312 -/* 6250 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 6253 */ MCD_OPC_FilterValue, 0, 235, 8, // Skip to: 8540 -/* 6257 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 6260 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 6268 -/* 6264 */ MCD_OPC_Decode, 155, 5, 61, // Opcode: CGRTAsmH -/* 6268 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 6276 -/* 6272 */ MCD_OPC_Decode, 157, 5, 61, // Opcode: CGRTAsmL -/* 6276 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 6284 -/* 6280 */ MCD_OPC_Decode, 159, 5, 61, // Opcode: CGRTAsmLH -/* 6284 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 6292 -/* 6288 */ MCD_OPC_Decode, 154, 5, 61, // Opcode: CGRTAsmE -/* 6292 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 6300 -/* 6296 */ MCD_OPC_Decode, 156, 5, 61, // Opcode: CGRTAsmHE -/* 6300 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 6308 -/* 6304 */ MCD_OPC_Decode, 158, 5, 61, // Opcode: CGRTAsmLE -/* 6308 */ MCD_OPC_Decode, 153, 5, 73, // Opcode: CGRTAsm -/* 6312 */ MCD_OPC_FilterValue, 97, 62, 0, // Skip to: 6378 -/* 6316 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 6319 */ MCD_OPC_FilterValue, 0, 169, 8, // Skip to: 8540 -/* 6323 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 6326 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 6334 -/* 6330 */ MCD_OPC_Decode, 207, 6, 61, // Opcode: CLGRTAsmH -/* 6334 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 6342 -/* 6338 */ MCD_OPC_Decode, 209, 6, 61, // Opcode: CLGRTAsmL -/* 6342 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 6350 -/* 6346 */ MCD_OPC_Decode, 211, 6, 61, // Opcode: CLGRTAsmLH -/* 6350 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 6358 -/* 6354 */ MCD_OPC_Decode, 206, 6, 61, // Opcode: CLGRTAsmE -/* 6358 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 6366 -/* 6362 */ MCD_OPC_Decode, 208, 6, 61, // Opcode: CLGRTAsmHE -/* 6366 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 6374 -/* 6370 */ MCD_OPC_Decode, 210, 6, 61, // Opcode: CLGRTAsmLE -/* 6374 */ MCD_OPC_Decode, 205, 6, 73, // Opcode: CLGRTAsm -/* 6378 */ MCD_OPC_FilterValue, 114, 63, 0, // Skip to: 6445 -/* 6382 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 6385 */ MCD_OPC_FilterValue, 0, 103, 8, // Skip to: 8540 -/* 6389 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 6392 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 6400 -/* 6396 */ MCD_OPC_Decode, 249, 7, 8, // Opcode: CRTAsmH -/* 6400 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 6408 -/* 6404 */ MCD_OPC_Decode, 251, 7, 8, // Opcode: CRTAsmL -/* 6408 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 6416 -/* 6412 */ MCD_OPC_Decode, 253, 7, 8, // Opcode: CRTAsmLH -/* 6416 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 6424 -/* 6420 */ MCD_OPC_Decode, 248, 7, 8, // Opcode: CRTAsmE -/* 6424 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 6432 -/* 6428 */ MCD_OPC_Decode, 250, 7, 8, // Opcode: CRTAsmHE -/* 6432 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 6440 -/* 6436 */ MCD_OPC_Decode, 252, 7, 8, // Opcode: CRTAsmLE -/* 6440 */ MCD_OPC_Decode, 247, 7, 139, 1, // Opcode: CRTAsm -/* 6445 */ MCD_OPC_FilterValue, 115, 63, 0, // Skip to: 6512 -/* 6449 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 6452 */ MCD_OPC_FilterValue, 0, 36, 8, // Skip to: 8540 -/* 6456 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 6459 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 6467 -/* 6463 */ MCD_OPC_Decode, 178, 7, 8, // Opcode: CLRTAsmH -/* 6467 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 6475 -/* 6471 */ MCD_OPC_Decode, 180, 7, 8, // Opcode: CLRTAsmL -/* 6475 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 6483 -/* 6479 */ MCD_OPC_Decode, 182, 7, 8, // Opcode: CLRTAsmLH -/* 6483 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 6491 -/* 6487 */ MCD_OPC_Decode, 177, 7, 8, // Opcode: CLRTAsmE -/* 6491 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 6499 -/* 6495 */ MCD_OPC_Decode, 179, 7, 8, // Opcode: CLRTAsmHE -/* 6499 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 6507 -/* 6503 */ MCD_OPC_Decode, 181, 7, 8, // Opcode: CLRTAsmLE -/* 6507 */ MCD_OPC_Decode, 176, 7, 139, 1, // Opcode: CLRTAsm -/* 6512 */ MCD_OPC_FilterValue, 128, 1, 11, 0, // Skip to: 6528 -/* 6517 */ MCD_OPC_CheckField, 8, 8, 0, 225, 7, // Skip to: 8540 -/* 6523 */ MCD_OPC_Decode, 229, 13, 135, 1, // Opcode: NGR -/* 6528 */ MCD_OPC_FilterValue, 129, 1, 11, 0, // Skip to: 6544 -/* 6533 */ MCD_OPC_CheckField, 8, 8, 0, 209, 7, // Skip to: 8540 -/* 6539 */ MCD_OPC_Decode, 247, 13, 135, 1, // Opcode: OGR -/* 6544 */ MCD_OPC_FilterValue, 130, 1, 11, 0, // Skip to: 6560 -/* 6549 */ MCD_OPC_CheckField, 8, 8, 0, 193, 7, // Skip to: 8540 -/* 6555 */ MCD_OPC_Decode, 229, 21, 135, 1, // Opcode: XGR -/* 6560 */ MCD_OPC_FilterValue, 131, 1, 11, 0, // Skip to: 6576 -/* 6565 */ MCD_OPC_CheckField, 8, 8, 0, 177, 7, // Skip to: 8540 -/* 6571 */ MCD_OPC_Decode, 251, 8, 140, 1, // Opcode: FLOGR -/* 6576 */ MCD_OPC_FilterValue, 132, 1, 10, 0, // Skip to: 6591 -/* 6581 */ MCD_OPC_CheckField, 8, 8, 0, 161, 7, // Skip to: 8540 -/* 6587 */ MCD_OPC_Decode, 202, 10, 61, // Opcode: LLGCR -/* 6591 */ MCD_OPC_FilterValue, 133, 1, 10, 0, // Skip to: 6606 -/* 6596 */ MCD_OPC_CheckField, 8, 8, 0, 146, 7, // Skip to: 8540 -/* 6602 */ MCD_OPC_Decode, 209, 10, 61, // Opcode: LLGHR -/* 6606 */ MCD_OPC_FilterValue, 134, 1, 10, 0, // Skip to: 6621 -/* 6611 */ MCD_OPC_CheckField, 8, 8, 0, 131, 7, // Skip to: 8540 -/* 6617 */ MCD_OPC_Decode, 164, 13, 68, // Opcode: MLGR -/* 6621 */ MCD_OPC_FilterValue, 135, 1, 10, 0, // Skip to: 6636 -/* 6626 */ MCD_OPC_CheckField, 8, 8, 0, 116, 7, // Skip to: 8540 -/* 6632 */ MCD_OPC_Decode, 203, 8, 68, // Opcode: DLGR -/* 6636 */ MCD_OPC_FilterValue, 136, 1, 11, 0, // Skip to: 6652 -/* 6641 */ MCD_OPC_CheckField, 8, 8, 0, 101, 7, // Skip to: 8540 -/* 6647 */ MCD_OPC_Decode, 132, 3, 135, 1, // Opcode: ALCGR -/* 6652 */ MCD_OPC_FilterValue, 137, 1, 11, 0, // Skip to: 6668 -/* 6657 */ MCD_OPC_CheckField, 8, 8, 0, 85, 7, // Skip to: 8540 -/* 6663 */ MCD_OPC_Decode, 221, 14, 135, 1, // Opcode: SLBGR -/* 6668 */ MCD_OPC_FilterValue, 138, 1, 10, 0, // Skip to: 6683 -/* 6673 */ MCD_OPC_CheckField, 8, 8, 0, 69, 7, // Skip to: 8540 -/* 6679 */ MCD_OPC_Decode, 137, 8, 68, // Opcode: CSPG -/* 6683 */ MCD_OPC_FilterValue, 141, 1, 10, 0, // Skip to: 6698 -/* 6688 */ MCD_OPC_CheckField, 8, 8, 0, 54, 7, // Skip to: 8540 -/* 6694 */ MCD_OPC_Decode, 228, 8, 8, // Opcode: EPSW -/* 6698 */ MCD_OPC_FilterValue, 142, 1, 16, 0, // Skip to: 6719 -/* 6703 */ MCD_OPC_CheckField, 8, 4, 0, 5, 0, // Skip to: 6714 -/* 6709 */ MCD_OPC_Decode, 136, 9, 141, 1, // Opcode: IDTEOpt -/* 6714 */ MCD_OPC_Decode, 135, 9, 142, 1, // Opcode: IDTE -/* 6719 */ MCD_OPC_FilterValue, 143, 1, 24, 0, // Skip to: 6748 -/* 6724 */ MCD_OPC_CheckPredicate, 8, 11, 0, // Skip to: 6739 -/* 6728 */ MCD_OPC_CheckField, 8, 4, 0, 5, 0, // Skip to: 6739 -/* 6734 */ MCD_OPC_Decode, 230, 7, 143, 1, // Opcode: CRDTEOpt -/* 6739 */ MCD_OPC_CheckPredicate, 8, 5, 7, // Skip to: 8540 -/* 6743 */ MCD_OPC_Decode, 229, 7, 144, 1, // Opcode: CRDTE -/* 6748 */ MCD_OPC_FilterValue, 144, 1, 22, 0, // Skip to: 6775 -/* 6753 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 6756 */ MCD_OPC_FilterValue, 0, 244, 6, // Skip to: 8540 -/* 6760 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 6770 -/* 6766 */ MCD_OPC_Decode, 203, 16, 71, // Opcode: TRTTOpt -/* 6770 */ MCD_OPC_Decode, 202, 16, 145, 1, // Opcode: TRTT -/* 6775 */ MCD_OPC_FilterValue, 145, 1, 22, 0, // Skip to: 6802 -/* 6780 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 6783 */ MCD_OPC_FilterValue, 0, 217, 6, // Skip to: 8540 -/* 6787 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 6797 -/* 6793 */ MCD_OPC_Decode, 198, 16, 71, // Opcode: TRTOOpt -/* 6797 */ MCD_OPC_Decode, 197, 16, 145, 1, // Opcode: TRTO -/* 6802 */ MCD_OPC_FilterValue, 146, 1, 22, 0, // Skip to: 6829 -/* 6807 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 6810 */ MCD_OPC_FilterValue, 0, 190, 6, // Skip to: 8540 -/* 6814 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 6824 -/* 6820 */ MCD_OPC_Decode, 193, 16, 71, // Opcode: TROTOpt -/* 6824 */ MCD_OPC_Decode, 192, 16, 145, 1, // Opcode: TROT -/* 6829 */ MCD_OPC_FilterValue, 147, 1, 22, 0, // Skip to: 6856 -/* 6834 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 6837 */ MCD_OPC_FilterValue, 0, 163, 6, // Skip to: 8540 -/* 6841 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 6851 -/* 6847 */ MCD_OPC_Decode, 191, 16, 71, // Opcode: TROOOpt -/* 6851 */ MCD_OPC_Decode, 190, 16, 145, 1, // Opcode: TROO -/* 6856 */ MCD_OPC_FilterValue, 148, 1, 10, 0, // Skip to: 6871 -/* 6861 */ MCD_OPC_CheckField, 8, 8, 0, 137, 6, // Skip to: 8540 -/* 6867 */ MCD_OPC_Decode, 200, 10, 8, // Opcode: LLCR -/* 6871 */ MCD_OPC_FilterValue, 149, 1, 10, 0, // Skip to: 6886 -/* 6876 */ MCD_OPC_CheckField, 8, 8, 0, 122, 6, // Skip to: 8540 -/* 6882 */ MCD_OPC_Decode, 216, 10, 8, // Opcode: LLHR -/* 6886 */ MCD_OPC_FilterValue, 150, 1, 10, 0, // Skip to: 6901 -/* 6891 */ MCD_OPC_CheckField, 8, 8, 0, 107, 6, // Skip to: 8540 -/* 6897 */ MCD_OPC_Decode, 165, 13, 10, // Opcode: MLR -/* 6901 */ MCD_OPC_FilterValue, 151, 1, 10, 0, // Skip to: 6916 -/* 6906 */ MCD_OPC_CheckField, 8, 8, 0, 92, 6, // Skip to: 8540 -/* 6912 */ MCD_OPC_Decode, 204, 8, 10, // Opcode: DLR -/* 6916 */ MCD_OPC_FilterValue, 152, 1, 10, 0, // Skip to: 6931 -/* 6921 */ MCD_OPC_CheckField, 8, 8, 0, 77, 6, // Skip to: 8540 -/* 6927 */ MCD_OPC_Decode, 133, 3, 9, // Opcode: ALCR -/* 6931 */ MCD_OPC_FilterValue, 153, 1, 10, 0, // Skip to: 6946 -/* 6936 */ MCD_OPC_CheckField, 8, 8, 0, 62, 6, // Skip to: 8540 -/* 6942 */ MCD_OPC_Decode, 222, 14, 9, // Opcode: SLBR -/* 6946 */ MCD_OPC_FilterValue, 154, 1, 17, 0, // Skip to: 6968 -/* 6951 */ MCD_OPC_CheckField, 8, 8, 0, 47, 6, // Skip to: 8540 -/* 6957 */ MCD_OPC_CheckField, 0, 4, 0, 41, 6, // Skip to: 8540 -/* 6963 */ MCD_OPC_Decode, 225, 8, 146, 1, // Opcode: EPAIR -/* 6968 */ MCD_OPC_FilterValue, 155, 1, 17, 0, // Skip to: 6990 -/* 6973 */ MCD_OPC_CheckField, 8, 8, 0, 25, 6, // Skip to: 8540 -/* 6979 */ MCD_OPC_CheckField, 0, 4, 0, 19, 6, // Skip to: 8540 -/* 6985 */ MCD_OPC_Decode, 231, 8, 146, 1, // Opcode: ESAIR -/* 6990 */ MCD_OPC_FilterValue, 157, 1, 17, 0, // Skip to: 7012 -/* 6995 */ MCD_OPC_CheckField, 8, 8, 0, 3, 6, // Skip to: 8540 -/* 7001 */ MCD_OPC_CheckField, 0, 4, 0, 253, 5, // Skip to: 8540 -/* 7007 */ MCD_OPC_Decode, 234, 8, 147, 1, // Opcode: ESEA -/* 7012 */ MCD_OPC_FilterValue, 158, 1, 10, 0, // Skip to: 7027 -/* 7017 */ MCD_OPC_CheckField, 8, 8, 0, 237, 5, // Skip to: 8540 -/* 7023 */ MCD_OPC_Decode, 154, 14, 61, // Opcode: PTI -/* 7027 */ MCD_OPC_FilterValue, 159, 1, 17, 0, // Skip to: 7049 -/* 7032 */ MCD_OPC_CheckField, 8, 8, 0, 222, 5, // Skip to: 8540 -/* 7038 */ MCD_OPC_CheckField, 0, 4, 0, 216, 5, // Skip to: 8540 -/* 7044 */ MCD_OPC_Decode, 148, 15, 146, 1, // Opcode: SSAIR -/* 7049 */ MCD_OPC_FilterValue, 162, 1, 17, 0, // Skip to: 7071 -/* 7054 */ MCD_OPC_CheckField, 8, 8, 0, 200, 5, // Skip to: 8540 -/* 7060 */ MCD_OPC_CheckField, 0, 4, 0, 194, 5, // Skip to: 8540 -/* 7066 */ MCD_OPC_Decode, 152, 14, 148, 1, // Opcode: PTF -/* 7071 */ MCD_OPC_FilterValue, 170, 1, 5, 0, // Skip to: 7081 -/* 7076 */ MCD_OPC_Decode, 199, 12, 149, 1, // Opcode: LPTEA -/* 7081 */ MCD_OPC_FilterValue, 172, 1, 14, 0, // Skip to: 7100 -/* 7086 */ MCD_OPC_CheckPredicate, 9, 170, 5, // Skip to: 8540 -/* 7090 */ MCD_OPC_CheckField, 8, 8, 0, 164, 5, // Skip to: 8540 -/* 7096 */ MCD_OPC_Decode, 150, 9, 61, // Opcode: IRBM -/* 7100 */ MCD_OPC_FilterValue, 174, 1, 14, 0, // Skip to: 7119 -/* 7105 */ MCD_OPC_CheckPredicate, 10, 151, 5, // Skip to: 8540 -/* 7109 */ MCD_OPC_CheckField, 8, 8, 0, 145, 5, // Skip to: 8540 -/* 7115 */ MCD_OPC_Decode, 172, 14, 61, // Opcode: RRBM -/* 7119 */ MCD_OPC_FilterValue, 175, 1, 11, 0, // Skip to: 7135 -/* 7124 */ MCD_OPC_CheckField, 8, 8, 0, 130, 5, // Skip to: 8540 -/* 7130 */ MCD_OPC_Decode, 139, 14, 150, 1, // Opcode: PFMF -/* 7135 */ MCD_OPC_FilterValue, 176, 1, 21, 0, // Skip to: 7161 -/* 7140 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 7143 */ MCD_OPC_FilterValue, 0, 113, 5, // Skip to: 8540 -/* 7147 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 7157 -/* 7153 */ MCD_OPC_Decode, 144, 8, 7, // Opcode: CU14Opt -/* 7157 */ MCD_OPC_Decode, 143, 8, 72, // Opcode: CU14 -/* 7161 */ MCD_OPC_FilterValue, 177, 1, 21, 0, // Skip to: 7187 -/* 7166 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 7169 */ MCD_OPC_FilterValue, 0, 87, 5, // Skip to: 8540 -/* 7173 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 7183 -/* 7179 */ MCD_OPC_Decode, 148, 8, 7, // Opcode: CU24Opt -/* 7183 */ MCD_OPC_Decode, 147, 8, 72, // Opcode: CU24 -/* 7187 */ MCD_OPC_FilterValue, 178, 1, 10, 0, // Skip to: 7202 -/* 7192 */ MCD_OPC_CheckField, 8, 8, 0, 62, 5, // Skip to: 8540 -/* 7198 */ MCD_OPC_Decode, 149, 8, 7, // Opcode: CU41 -/* 7202 */ MCD_OPC_FilterValue, 179, 1, 10, 0, // Skip to: 7217 -/* 7207 */ MCD_OPC_CheckField, 8, 8, 0, 47, 5, // Skip to: 8540 -/* 7213 */ MCD_OPC_Decode, 150, 8, 7, // Opcode: CU42 -/* 7217 */ MCD_OPC_FilterValue, 189, 1, 23, 0, // Skip to: 7245 -/* 7222 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 7225 */ MCD_OPC_FilterValue, 0, 31, 5, // Skip to: 8540 -/* 7229 */ MCD_OPC_CheckField, 12, 4, 0, 5, 0, // Skip to: 7240 -/* 7235 */ MCD_OPC_Decode, 201, 16, 151, 1, // Opcode: TRTREOpt -/* 7240 */ MCD_OPC_Decode, 200, 16, 152, 1, // Opcode: TRTRE -/* 7245 */ MCD_OPC_FilterValue, 190, 1, 10, 0, // Skip to: 7260 -/* 7250 */ MCD_OPC_CheckField, 8, 8, 0, 4, 5, // Skip to: 8540 -/* 7256 */ MCD_OPC_Decode, 146, 15, 69, // Opcode: SRSTU -/* 7260 */ MCD_OPC_FilterValue, 191, 1, 23, 0, // Skip to: 7288 -/* 7265 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 7268 */ MCD_OPC_FilterValue, 0, 244, 4, // Skip to: 8540 -/* 7272 */ MCD_OPC_CheckField, 12, 4, 0, 5, 0, // Skip to: 7283 -/* 7278 */ MCD_OPC_Decode, 196, 16, 151, 1, // Opcode: TRTEOpt -/* 7283 */ MCD_OPC_Decode, 195, 16, 152, 1, // Opcode: TRTE -/* 7288 */ MCD_OPC_FilterValue, 200, 1, 15, 0, // Skip to: 7308 -/* 7293 */ MCD_OPC_CheckPredicate, 11, 219, 4, // Skip to: 8540 -/* 7297 */ MCD_OPC_CheckField, 8, 4, 0, 213, 4, // Skip to: 8540 -/* 7303 */ MCD_OPC_Decode, 251, 2, 153, 1, // Opcode: AHHHR -/* 7308 */ MCD_OPC_FilterValue, 201, 1, 15, 0, // Skip to: 7328 -/* 7313 */ MCD_OPC_CheckPredicate, 11, 199, 4, // Skip to: 8540 -/* 7317 */ MCD_OPC_CheckField, 8, 4, 0, 193, 4, // Skip to: 8540 -/* 7323 */ MCD_OPC_Decode, 209, 14, 153, 1, // Opcode: SHHHR -/* 7328 */ MCD_OPC_FilterValue, 202, 1, 15, 0, // Skip to: 7348 -/* 7333 */ MCD_OPC_CheckPredicate, 11, 179, 4, // Skip to: 8540 -/* 7337 */ MCD_OPC_CheckField, 8, 4, 0, 173, 4, // Skip to: 8540 -/* 7343 */ MCD_OPC_Decode, 143, 3, 153, 1, // Opcode: ALHHHR -/* 7348 */ MCD_OPC_FilterValue, 203, 1, 15, 0, // Skip to: 7368 -/* 7353 */ MCD_OPC_CheckPredicate, 11, 159, 4, // Skip to: 8540 -/* 7357 */ MCD_OPC_CheckField, 8, 4, 0, 153, 4, // Skip to: 8540 -/* 7363 */ MCD_OPC_Decode, 233, 14, 153, 1, // Opcode: SLHHHR -/* 7368 */ MCD_OPC_FilterValue, 205, 1, 15, 0, // Skip to: 7388 -/* 7373 */ MCD_OPC_CheckPredicate, 11, 139, 4, // Skip to: 8540 -/* 7377 */ MCD_OPC_CheckField, 8, 8, 0, 133, 4, // Skip to: 8540 -/* 7383 */ MCD_OPC_Decode, 173, 5, 154, 1, // Opcode: CHHR -/* 7388 */ MCD_OPC_FilterValue, 207, 1, 15, 0, // Skip to: 7408 -/* 7393 */ MCD_OPC_CheckPredicate, 11, 119, 4, // Skip to: 8540 -/* 7397 */ MCD_OPC_CheckField, 8, 8, 0, 113, 4, // Skip to: 8540 -/* 7403 */ MCD_OPC_Decode, 235, 6, 154, 1, // Opcode: CLHHR -/* 7408 */ MCD_OPC_FilterValue, 216, 1, 15, 0, // Skip to: 7428 -/* 7413 */ MCD_OPC_CheckPredicate, 11, 99, 4, // Skip to: 8540 -/* 7417 */ MCD_OPC_CheckField, 8, 4, 0, 93, 4, // Skip to: 8540 -/* 7423 */ MCD_OPC_Decode, 252, 2, 155, 1, // Opcode: AHHLR -/* 7428 */ MCD_OPC_FilterValue, 217, 1, 15, 0, // Skip to: 7448 -/* 7433 */ MCD_OPC_CheckPredicate, 11, 79, 4, // Skip to: 8540 -/* 7437 */ MCD_OPC_CheckField, 8, 4, 0, 73, 4, // Skip to: 8540 -/* 7443 */ MCD_OPC_Decode, 210, 14, 155, 1, // Opcode: SHHLR -/* 7448 */ MCD_OPC_FilterValue, 218, 1, 15, 0, // Skip to: 7468 -/* 7453 */ MCD_OPC_CheckPredicate, 11, 59, 4, // Skip to: 8540 -/* 7457 */ MCD_OPC_CheckField, 8, 4, 0, 53, 4, // Skip to: 8540 -/* 7463 */ MCD_OPC_Decode, 144, 3, 155, 1, // Opcode: ALHHLR -/* 7468 */ MCD_OPC_FilterValue, 219, 1, 15, 0, // Skip to: 7488 -/* 7473 */ MCD_OPC_CheckPredicate, 11, 39, 4, // Skip to: 8540 -/* 7477 */ MCD_OPC_CheckField, 8, 4, 0, 33, 4, // Skip to: 8540 -/* 7483 */ MCD_OPC_Decode, 234, 14, 155, 1, // Opcode: SLHHLR -/* 7488 */ MCD_OPC_FilterValue, 221, 1, 15, 0, // Skip to: 7508 -/* 7493 */ MCD_OPC_CheckPredicate, 11, 19, 4, // Skip to: 8540 -/* 7497 */ MCD_OPC_CheckField, 8, 8, 0, 13, 4, // Skip to: 8540 -/* 7503 */ MCD_OPC_Decode, 176, 5, 156, 1, // Opcode: CHLR -/* 7508 */ MCD_OPC_FilterValue, 223, 1, 15, 0, // Skip to: 7528 -/* 7513 */ MCD_OPC_CheckPredicate, 11, 255, 3, // Skip to: 8540 -/* 7517 */ MCD_OPC_CheckField, 8, 8, 0, 249, 3, // Skip to: 8540 -/* 7523 */ MCD_OPC_Decode, 237, 6, 156, 1, // Opcode: CLHLR -/* 7528 */ MCD_OPC_FilterValue, 224, 1, 201, 0, // Skip to: 7734 -/* 7533 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 7536 */ MCD_OPC_FilterValue, 0, 232, 3, // Skip to: 8540 -/* 7540 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 7543 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7556 -/* 7547 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 7725 -/* 7551 */ MCD_OPC_Decode, 176, 11, 157, 1, // Opcode: LOCFHRAsmO -/* 7556 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7569 -/* 7560 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 7725 -/* 7564 */ MCD_OPC_Decode, 160, 11, 157, 1, // Opcode: LOCFHRAsmH -/* 7569 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7582 -/* 7573 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 7725 -/* 7577 */ MCD_OPC_Decode, 170, 11, 157, 1, // Opcode: LOCFHRAsmNLE -/* 7582 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7595 -/* 7586 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 7725 -/* 7590 */ MCD_OPC_Decode, 162, 11, 157, 1, // Opcode: LOCFHRAsmL -/* 7595 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7608 -/* 7599 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 7725 -/* 7603 */ MCD_OPC_Decode, 168, 11, 157, 1, // Opcode: LOCFHRAsmNHE -/* 7608 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7621 -/* 7612 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 7725 -/* 7616 */ MCD_OPC_Decode, 164, 11, 157, 1, // Opcode: LOCFHRAsmLH -/* 7621 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7634 -/* 7625 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 7725 -/* 7629 */ MCD_OPC_Decode, 166, 11, 157, 1, // Opcode: LOCFHRAsmNE -/* 7634 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7647 -/* 7638 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 7725 -/* 7642 */ MCD_OPC_Decode, 159, 11, 157, 1, // Opcode: LOCFHRAsmE -/* 7647 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7660 -/* 7651 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 7725 -/* 7655 */ MCD_OPC_Decode, 171, 11, 157, 1, // Opcode: LOCFHRAsmNLH -/* 7660 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7673 -/* 7664 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 7725 -/* 7668 */ MCD_OPC_Decode, 161, 11, 157, 1, // Opcode: LOCFHRAsmHE -/* 7673 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7686 -/* 7677 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 7725 -/* 7681 */ MCD_OPC_Decode, 169, 11, 157, 1, // Opcode: LOCFHRAsmNL -/* 7686 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 7699 -/* 7690 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 7725 -/* 7694 */ MCD_OPC_Decode, 163, 11, 157, 1, // Opcode: LOCFHRAsmLE -/* 7699 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7712 -/* 7703 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 7725 -/* 7707 */ MCD_OPC_Decode, 167, 11, 157, 1, // Opcode: LOCFHRAsmNH -/* 7712 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7725 -/* 7716 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 7725 -/* 7720 */ MCD_OPC_Decode, 173, 11, 157, 1, // Opcode: LOCFHRAsmNO -/* 7725 */ MCD_OPC_CheckPredicate, 12, 43, 3, // Skip to: 8540 -/* 7729 */ MCD_OPC_Decode, 158, 11, 158, 1, // Opcode: LOCFHRAsm -/* 7734 */ MCD_OPC_FilterValue, 225, 1, 14, 0, // Skip to: 7753 -/* 7739 */ MCD_OPC_CheckPredicate, 13, 29, 3, // Skip to: 8540 -/* 7743 */ MCD_OPC_CheckField, 8, 8, 0, 23, 3, // Skip to: 8540 -/* 7749 */ MCD_OPC_Decode, 146, 14, 61, // Opcode: POPCNT -/* 7753 */ MCD_OPC_FilterValue, 226, 1, 201, 0, // Skip to: 7959 -/* 7758 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 7761 */ MCD_OPC_FilterValue, 0, 7, 3, // Skip to: 8540 -/* 7765 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 7768 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7781 -/* 7772 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 7950 -/* 7776 */ MCD_OPC_Decode, 242, 11, 135, 1, // Opcode: LOCGRAsmO -/* 7781 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7794 -/* 7785 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 7950 -/* 7789 */ MCD_OPC_Decode, 226, 11, 135, 1, // Opcode: LOCGRAsmH -/* 7794 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7807 -/* 7798 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 7950 -/* 7802 */ MCD_OPC_Decode, 236, 11, 135, 1, // Opcode: LOCGRAsmNLE -/* 7807 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7820 -/* 7811 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 7950 -/* 7815 */ MCD_OPC_Decode, 228, 11, 135, 1, // Opcode: LOCGRAsmL -/* 7820 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7833 -/* 7824 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 7950 -/* 7828 */ MCD_OPC_Decode, 234, 11, 135, 1, // Opcode: LOCGRAsmNHE -/* 7833 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7846 -/* 7837 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 7950 -/* 7841 */ MCD_OPC_Decode, 230, 11, 135, 1, // Opcode: LOCGRAsmLH -/* 7846 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7859 -/* 7850 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 7950 -/* 7854 */ MCD_OPC_Decode, 232, 11, 135, 1, // Opcode: LOCGRAsmNE -/* 7859 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7872 -/* 7863 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 7950 -/* 7867 */ MCD_OPC_Decode, 225, 11, 135, 1, // Opcode: LOCGRAsmE -/* 7872 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7885 -/* 7876 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 7950 -/* 7880 */ MCD_OPC_Decode, 237, 11, 135, 1, // Opcode: LOCGRAsmNLH -/* 7885 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7898 -/* 7889 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 7950 -/* 7893 */ MCD_OPC_Decode, 227, 11, 135, 1, // Opcode: LOCGRAsmHE -/* 7898 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7911 -/* 7902 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 7950 -/* 7906 */ MCD_OPC_Decode, 235, 11, 135, 1, // Opcode: LOCGRAsmNL -/* 7911 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 7924 -/* 7915 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 7950 -/* 7919 */ MCD_OPC_Decode, 229, 11, 135, 1, // Opcode: LOCGRAsmLE -/* 7924 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7937 -/* 7928 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 7950 -/* 7932 */ MCD_OPC_Decode, 233, 11, 135, 1, // Opcode: LOCGRAsmNH -/* 7937 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7950 -/* 7941 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 7950 -/* 7945 */ MCD_OPC_Decode, 239, 11, 135, 1, // Opcode: LOCGRAsmNO -/* 7950 */ MCD_OPC_CheckPredicate, 14, 74, 2, // Skip to: 8540 -/* 7954 */ MCD_OPC_Decode, 224, 11, 159, 1, // Opcode: LOCGRAsm -/* 7959 */ MCD_OPC_FilterValue, 228, 1, 15, 0, // Skip to: 7979 -/* 7964 */ MCD_OPC_CheckPredicate, 15, 60, 2, // Skip to: 8540 -/* 7968 */ MCD_OPC_CheckField, 8, 4, 0, 54, 2, // Skip to: 8540 -/* 7974 */ MCD_OPC_Decode, 230, 13, 141, 1, // Opcode: NGRK -/* 7979 */ MCD_OPC_FilterValue, 230, 1, 15, 0, // Skip to: 7999 -/* 7984 */ MCD_OPC_CheckPredicate, 15, 40, 2, // Skip to: 8540 -/* 7988 */ MCD_OPC_CheckField, 8, 4, 0, 34, 2, // Skip to: 8540 -/* 7994 */ MCD_OPC_Decode, 248, 13, 141, 1, // Opcode: OGRK -/* 7999 */ MCD_OPC_FilterValue, 231, 1, 15, 0, // Skip to: 8019 -/* 8004 */ MCD_OPC_CheckPredicate, 15, 20, 2, // Skip to: 8540 -/* 8008 */ MCD_OPC_CheckField, 8, 4, 0, 14, 2, // Skip to: 8540 -/* 8014 */ MCD_OPC_Decode, 230, 21, 141, 1, // Opcode: XGRK -/* 8019 */ MCD_OPC_FilterValue, 232, 1, 15, 0, // Skip to: 8039 -/* 8024 */ MCD_OPC_CheckPredicate, 15, 0, 2, // Skip to: 8540 -/* 8028 */ MCD_OPC_CheckField, 8, 4, 0, 250, 1, // Skip to: 8540 -/* 8034 */ MCD_OPC_Decode, 248, 2, 141, 1, // Opcode: AGRK -/* 8039 */ MCD_OPC_FilterValue, 233, 1, 15, 0, // Skip to: 8059 -/* 8044 */ MCD_OPC_CheckPredicate, 15, 236, 1, // Skip to: 8540 -/* 8048 */ MCD_OPC_CheckField, 8, 4, 0, 230, 1, // Skip to: 8540 -/* 8054 */ MCD_OPC_Decode, 207, 14, 141, 1, // Opcode: SGRK -/* 8059 */ MCD_OPC_FilterValue, 234, 1, 15, 0, // Skip to: 8079 -/* 8064 */ MCD_OPC_CheckPredicate, 15, 216, 1, // Skip to: 8540 -/* 8068 */ MCD_OPC_CheckField, 8, 4, 0, 210, 1, // Skip to: 8540 -/* 8074 */ MCD_OPC_Decode, 141, 3, 141, 1, // Opcode: ALGRK -/* 8079 */ MCD_OPC_FilterValue, 235, 1, 15, 0, // Skip to: 8099 -/* 8084 */ MCD_OPC_CheckPredicate, 15, 196, 1, // Skip to: 8540 -/* 8088 */ MCD_OPC_CheckField, 8, 4, 0, 190, 1, // Skip to: 8540 -/* 8094 */ MCD_OPC_Decode, 232, 14, 141, 1, // Opcode: SLGRK -/* 8099 */ MCD_OPC_FilterValue, 236, 1, 15, 0, // Skip to: 8119 -/* 8104 */ MCD_OPC_CheckPredicate, 16, 176, 1, // Skip to: 8540 -/* 8108 */ MCD_OPC_CheckField, 8, 4, 0, 170, 1, // Skip to: 8540 -/* 8114 */ MCD_OPC_Decode, 158, 13, 160, 1, // Opcode: MGRK -/* 8119 */ MCD_OPC_FilterValue, 237, 1, 15, 0, // Skip to: 8139 -/* 8124 */ MCD_OPC_CheckPredicate, 16, 156, 1, // Skip to: 8540 -/* 8128 */ MCD_OPC_CheckField, 8, 4, 0, 150, 1, // Skip to: 8540 -/* 8134 */ MCD_OPC_Decode, 186, 13, 141, 1, // Opcode: MSGRKC -/* 8139 */ MCD_OPC_FilterValue, 242, 1, 187, 0, // Skip to: 8331 -/* 8144 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 8147 */ MCD_OPC_FilterValue, 0, 133, 1, // Skip to: 8540 -/* 8151 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 8154 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 8166 -/* 8158 */ MCD_OPC_CheckPredicate, 14, 160, 0, // Skip to: 8322 -/* 8162 */ MCD_OPC_Decode, 180, 12, 9, // Opcode: LOCRAsmO -/* 8166 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 8178 -/* 8170 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 8322 -/* 8174 */ MCD_OPC_Decode, 164, 12, 9, // Opcode: LOCRAsmH -/* 8178 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 8190 -/* 8182 */ MCD_OPC_CheckPredicate, 14, 136, 0, // Skip to: 8322 -/* 8186 */ MCD_OPC_Decode, 174, 12, 9, // Opcode: LOCRAsmNLE -/* 8190 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 8202 -/* 8194 */ MCD_OPC_CheckPredicate, 14, 124, 0, // Skip to: 8322 -/* 8198 */ MCD_OPC_Decode, 166, 12, 9, // Opcode: LOCRAsmL -/* 8202 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 8214 -/* 8206 */ MCD_OPC_CheckPredicate, 14, 112, 0, // Skip to: 8322 -/* 8210 */ MCD_OPC_Decode, 172, 12, 9, // Opcode: LOCRAsmNHE -/* 8214 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 8226 -/* 8218 */ MCD_OPC_CheckPredicate, 14, 100, 0, // Skip to: 8322 -/* 8222 */ MCD_OPC_Decode, 168, 12, 9, // Opcode: LOCRAsmLH -/* 8226 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 8238 -/* 8230 */ MCD_OPC_CheckPredicate, 14, 88, 0, // Skip to: 8322 -/* 8234 */ MCD_OPC_Decode, 170, 12, 9, // Opcode: LOCRAsmNE -/* 8238 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 8250 -/* 8242 */ MCD_OPC_CheckPredicate, 14, 76, 0, // Skip to: 8322 -/* 8246 */ MCD_OPC_Decode, 163, 12, 9, // Opcode: LOCRAsmE -/* 8250 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 8262 -/* 8254 */ MCD_OPC_CheckPredicate, 14, 64, 0, // Skip to: 8322 -/* 8258 */ MCD_OPC_Decode, 175, 12, 9, // Opcode: LOCRAsmNLH -/* 8262 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 8274 -/* 8266 */ MCD_OPC_CheckPredicate, 14, 52, 0, // Skip to: 8322 -/* 8270 */ MCD_OPC_Decode, 165, 12, 9, // Opcode: LOCRAsmHE -/* 8274 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 8286 -/* 8278 */ MCD_OPC_CheckPredicate, 14, 40, 0, // Skip to: 8322 -/* 8282 */ MCD_OPC_Decode, 173, 12, 9, // Opcode: LOCRAsmNL -/* 8286 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 8298 -/* 8290 */ MCD_OPC_CheckPredicate, 14, 28, 0, // Skip to: 8322 -/* 8294 */ MCD_OPC_Decode, 167, 12, 9, // Opcode: LOCRAsmLE -/* 8298 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 8310 -/* 8302 */ MCD_OPC_CheckPredicate, 14, 16, 0, // Skip to: 8322 -/* 8306 */ MCD_OPC_Decode, 171, 12, 9, // Opcode: LOCRAsmNH -/* 8310 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 8322 -/* 8314 */ MCD_OPC_CheckPredicate, 14, 4, 0, // Skip to: 8322 -/* 8318 */ MCD_OPC_Decode, 177, 12, 9, // Opcode: LOCRAsmNO -/* 8322 */ MCD_OPC_CheckPredicate, 14, 214, 0, // Skip to: 8540 -/* 8326 */ MCD_OPC_Decode, 162, 12, 161, 1, // Opcode: LOCRAsm -/* 8331 */ MCD_OPC_FilterValue, 244, 1, 15, 0, // Skip to: 8351 -/* 8336 */ MCD_OPC_CheckPredicate, 15, 200, 0, // Skip to: 8540 -/* 8340 */ MCD_OPC_CheckField, 8, 4, 0, 194, 0, // Skip to: 8540 -/* 8346 */ MCD_OPC_Decode, 241, 13, 162, 1, // Opcode: NRK -/* 8351 */ MCD_OPC_FilterValue, 246, 1, 15, 0, // Skip to: 8371 -/* 8356 */ MCD_OPC_CheckPredicate, 15, 180, 0, // Skip to: 8540 -/* 8360 */ MCD_OPC_CheckField, 8, 4, 0, 174, 0, // Skip to: 8540 -/* 8366 */ MCD_OPC_Decode, 130, 14, 162, 1, // Opcode: ORK -/* 8371 */ MCD_OPC_FilterValue, 247, 1, 15, 0, // Skip to: 8391 -/* 8376 */ MCD_OPC_CheckPredicate, 15, 160, 0, // Skip to: 8540 -/* 8380 */ MCD_OPC_CheckField, 8, 4, 0, 154, 0, // Skip to: 8540 -/* 8386 */ MCD_OPC_Decode, 236, 21, 162, 1, // Opcode: XRK -/* 8391 */ MCD_OPC_FilterValue, 248, 1, 15, 0, // Skip to: 8411 -/* 8396 */ MCD_OPC_CheckPredicate, 15, 140, 0, // Skip to: 8540 -/* 8400 */ MCD_OPC_CheckField, 8, 4, 0, 134, 0, // Skip to: 8540 -/* 8406 */ MCD_OPC_Decode, 154, 3, 162, 1, // Opcode: ARK -/* 8411 */ MCD_OPC_FilterValue, 249, 1, 15, 0, // Skip to: 8431 -/* 8416 */ MCD_OPC_CheckPredicate, 15, 120, 0, // Skip to: 8540 -/* 8420 */ MCD_OPC_CheckField, 8, 4, 0, 114, 0, // Skip to: 8540 -/* 8426 */ MCD_OPC_Decode, 137, 15, 162, 1, // Opcode: SRK -/* 8431 */ MCD_OPC_FilterValue, 250, 1, 15, 0, // Skip to: 8451 -/* 8436 */ MCD_OPC_CheckPredicate, 15, 100, 0, // Skip to: 8540 -/* 8440 */ MCD_OPC_CheckField, 8, 4, 0, 94, 0, // Skip to: 8540 -/* 8446 */ MCD_OPC_Decode, 147, 3, 162, 1, // Opcode: ALRK -/* 8451 */ MCD_OPC_FilterValue, 251, 1, 15, 0, // Skip to: 8471 -/* 8456 */ MCD_OPC_CheckPredicate, 15, 80, 0, // Skip to: 8540 -/* 8460 */ MCD_OPC_CheckField, 8, 4, 0, 74, 0, // Skip to: 8540 -/* 8466 */ MCD_OPC_Decode, 239, 14, 162, 1, // Opcode: SLRK -/* 8471 */ MCD_OPC_FilterValue, 253, 1, 64, 0, // Skip to: 8540 -/* 8476 */ MCD_OPC_CheckPredicate, 16, 60, 0, // Skip to: 8540 -/* 8480 */ MCD_OPC_CheckField, 8, 4, 0, 54, 0, // Skip to: 8540 -/* 8486 */ MCD_OPC_Decode, 188, 13, 162, 1, // Opcode: MSRKC -/* 8491 */ MCD_OPC_FilterValue, 186, 1, 4, 0, // Skip to: 8500 -/* 8496 */ MCD_OPC_Decode, 132, 8, 35, // Opcode: CS -/* 8500 */ MCD_OPC_FilterValue, 187, 1, 5, 0, // Skip to: 8510 -/* 8505 */ MCD_OPC_Decode, 157, 4, 163, 1, // Opcode: CDS -/* 8510 */ MCD_OPC_FilterValue, 189, 1, 5, 0, // Skip to: 8520 -/* 8515 */ MCD_OPC_Decode, 142, 7, 164, 1, // Opcode: CLM -/* 8520 */ MCD_OPC_FilterValue, 190, 1, 5, 0, // Skip to: 8530 -/* 8525 */ MCD_OPC_Decode, 164, 15, 164, 1, // Opcode: STCM -/* 8530 */ MCD_OPC_FilterValue, 191, 1, 5, 0, // Skip to: 8540 -/* 8535 */ MCD_OPC_Decode, 131, 9, 165, 1, // Opcode: ICM -/* 8540 */ MCD_OPC_Fail, +/* 3 */ MCD_OPC_FilterValue, 64, 4, 0, 0, // Skip to: 12 +/* 8 */ MCD_OPC_Decode, 156, 17, 20, // Opcode: STH +/* 12 */ MCD_OPC_FilterValue, 65, 4, 0, 0, // Skip to: 21 +/* 17 */ MCD_OPC_Decode, 254, 10, 21, // Opcode: LA +/* 21 */ MCD_OPC_FilterValue, 66, 4, 0, 0, // Skip to: 30 +/* 26 */ MCD_OPC_Decode, 131, 17, 20, // Opcode: STC +/* 30 */ MCD_OPC_FilterValue, 67, 4, 0, 0, // Skip to: 39 +/* 35 */ MCD_OPC_Decode, 138, 10, 22, // Opcode: IC +/* 39 */ MCD_OPC_FilterValue, 68, 4, 0, 0, // Skip to: 48 +/* 44 */ MCD_OPC_Decode, 248, 9, 23, // Opcode: EX +/* 48 */ MCD_OPC_FilterValue, 69, 4, 0, 0, // Skip to: 57 +/* 53 */ MCD_OPC_Decode, 176, 4, 21, // Opcode: BAL +/* 57 */ MCD_OPC_FilterValue, 70, 4, 0, 0, // Skip to: 66 +/* 62 */ MCD_OPC_Decode, 205, 4, 24, // Opcode: BCT +/* 66 */ MCD_OPC_FilterValue, 71, 142, 0, 0, // Skip to: 213 +/* 71 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 74 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 83 +/* 79 */ MCD_OPC_Decode, 198, 4, 25, // Opcode: BAsmO +/* 83 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 92 +/* 88 */ MCD_OPC_Decode, 182, 4, 25, // Opcode: BAsmH +/* 92 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 101 +/* 97 */ MCD_OPC_Decode, 192, 4, 25, // Opcode: BAsmNLE +/* 101 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 110 +/* 106 */ MCD_OPC_Decode, 184, 4, 25, // Opcode: BAsmL +/* 110 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 119 +/* 115 */ MCD_OPC_Decode, 190, 4, 25, // Opcode: BAsmNHE +/* 119 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 128 +/* 124 */ MCD_OPC_Decode, 186, 4, 25, // Opcode: BAsmLH +/* 128 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 137 +/* 133 */ MCD_OPC_Decode, 188, 4, 25, // Opcode: BAsmNE +/* 137 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 146 +/* 142 */ MCD_OPC_Decode, 181, 4, 25, // Opcode: BAsmE +/* 146 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 155 +/* 151 */ MCD_OPC_Decode, 193, 4, 25, // Opcode: BAsmNLH +/* 155 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 164 +/* 160 */ MCD_OPC_Decode, 183, 4, 25, // Opcode: BAsmHE +/* 164 */ MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 173 +/* 169 */ MCD_OPC_Decode, 191, 4, 25, // Opcode: BAsmNL +/* 173 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 182 +/* 178 */ MCD_OPC_Decode, 185, 4, 25, // Opcode: BAsmLE +/* 182 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 191 +/* 187 */ MCD_OPC_Decode, 189, 4, 25, // Opcode: BAsmNH +/* 191 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 200 +/* 196 */ MCD_OPC_Decode, 195, 4, 25, // Opcode: BAsmNO +/* 200 */ MCD_OPC_FilterValue, 15, 4, 0, 0, // Skip to: 209 +/* 205 */ MCD_OPC_Decode, 174, 4, 25, // Opcode: B +/* 209 */ MCD_OPC_Decode, 202, 4, 26, // Opcode: BCAsm +/* 213 */ MCD_OPC_FilterValue, 72, 4, 0, 0, // Skip to: 222 +/* 218 */ MCD_OPC_Decode, 210, 11, 20, // Opcode: LH +/* 222 */ MCD_OPC_FilterValue, 73, 4, 0, 0, // Skip to: 231 +/* 227 */ MCD_OPC_Decode, 180, 6, 20, // Opcode: CH +/* 231 */ MCD_OPC_FilterValue, 74, 4, 0, 0, // Skip to: 240 +/* 236 */ MCD_OPC_Decode, 131, 4, 24, // Opcode: AH +/* 240 */ MCD_OPC_FilterValue, 75, 4, 0, 0, // Skip to: 249 +/* 245 */ MCD_OPC_Decode, 179, 16, 24, // Opcode: SH +/* 249 */ MCD_OPC_FilterValue, 76, 4, 0, 0, // Skip to: 258 +/* 254 */ MCD_OPC_Decode, 175, 14, 24, // Opcode: MH +/* 258 */ MCD_OPC_FilterValue, 77, 4, 0, 0, // Skip to: 267 +/* 263 */ MCD_OPC_Decode, 178, 4, 21, // Opcode: BAS +/* 267 */ MCD_OPC_FilterValue, 78, 4, 0, 0, // Skip to: 276 +/* 272 */ MCD_OPC_Decode, 170, 9, 20, // Opcode: CVD +/* 276 */ MCD_OPC_FilterValue, 79, 4, 0, 0, // Skip to: 285 +/* 281 */ MCD_OPC_Decode, 167, 9, 24, // Opcode: CVB +/* 285 */ MCD_OPC_FilterValue, 80, 4, 0, 0, // Skip to: 294 +/* 290 */ MCD_OPC_Decode, 254, 16, 20, // Opcode: ST +/* 294 */ MCD_OPC_FilterValue, 81, 4, 0, 0, // Skip to: 303 +/* 299 */ MCD_OPC_Decode, 131, 11, 21, // Opcode: LAE +/* 303 */ MCD_OPC_FilterValue, 84, 4, 0, 0, // Skip to: 312 +/* 308 */ MCD_OPC_Decode, 243, 14, 24, // Opcode: N +/* 312 */ MCD_OPC_FilterValue, 85, 4, 0, 0, // Skip to: 321 +/* 317 */ MCD_OPC_Decode, 233, 6, 20, // Opcode: CL +/* 321 */ MCD_OPC_FilterValue, 86, 4, 0, 0, // Skip to: 330 +/* 326 */ MCD_OPC_Decode, 143, 15, 24, // Opcode: O +/* 330 */ MCD_OPC_FilterValue, 87, 4, 0, 0, // Skip to: 339 +/* 335 */ MCD_OPC_Decode, 147, 24, 24, // Opcode: X +/* 339 */ MCD_OPC_FilterValue, 88, 4, 0, 0, // Skip to: 348 +/* 344 */ MCD_OPC_Decode, 253, 10, 20, // Opcode: L +/* 348 */ MCD_OPC_FilterValue, 89, 4, 0, 0, // Skip to: 357 +/* 353 */ MCD_OPC_Decode, 147, 5, 20, // Opcode: C +/* 357 */ MCD_OPC_FilterValue, 90, 4, 0, 0, // Skip to: 366 +/* 362 */ MCD_OPC_Decode, 237, 3, 24, // Opcode: A +/* 366 */ MCD_OPC_FilterValue, 91, 4, 0, 0, // Skip to: 375 +/* 371 */ MCD_OPC_Decode, 210, 15, 24, // Opcode: S +/* 375 */ MCD_OPC_FilterValue, 92, 4, 0, 0, // Skip to: 384 +/* 380 */ MCD_OPC_Decode, 138, 14, 27, // Opcode: M +/* 384 */ MCD_OPC_FilterValue, 93, 4, 0, 0, // Skip to: 393 +/* 389 */ MCD_OPC_Decode, 196, 9, 27, // Opcode: D +/* 393 */ MCD_OPC_FilterValue, 94, 4, 0, 0, // Skip to: 402 +/* 398 */ MCD_OPC_Decode, 138, 4, 24, // Opcode: AL +/* 402 */ MCD_OPC_FilterValue, 95, 4, 0, 0, // Skip to: 411 +/* 407 */ MCD_OPC_Decode, 186, 16, 24, // Opcode: SL +/* 411 */ MCD_OPC_FilterValue, 96, 4, 0, 0, // Skip to: 420 +/* 416 */ MCD_OPC_Decode, 145, 17, 28, // Opcode: STD +/* 420 */ MCD_OPC_FilterValue, 103, 4, 0, 0, // Skip to: 429 +/* 425 */ MCD_OPC_Decode, 230, 14, 29, // Opcode: MXD +/* 429 */ MCD_OPC_FilterValue, 104, 4, 0, 0, // Skip to: 438 +/* 434 */ MCD_OPC_Decode, 164, 11, 28, // Opcode: LD +/* 438 */ MCD_OPC_FilterValue, 105, 4, 0, 0, // Skip to: 447 +/* 443 */ MCD_OPC_Decode, 148, 5, 28, // Opcode: CD +/* 447 */ MCD_OPC_FilterValue, 106, 4, 0, 0, // Skip to: 456 +/* 452 */ MCD_OPC_Decode, 238, 3, 30, // Opcode: AD +/* 456 */ MCD_OPC_FilterValue, 107, 4, 0, 0, // Skip to: 465 +/* 461 */ MCD_OPC_Decode, 223, 15, 30, // Opcode: SD +/* 465 */ MCD_OPC_FilterValue, 108, 4, 0, 0, // Skip to: 474 +/* 470 */ MCD_OPC_Decode, 154, 14, 30, // Opcode: MD +/* 474 */ MCD_OPC_FilterValue, 109, 4, 0, 0, // Skip to: 483 +/* 479 */ MCD_OPC_Decode, 197, 9, 30, // Opcode: DD +/* 483 */ MCD_OPC_FilterValue, 110, 4, 0, 0, // Skip to: 492 +/* 488 */ MCD_OPC_Decode, 167, 4, 30, // Opcode: AW +/* 492 */ MCD_OPC_FilterValue, 111, 4, 0, 0, // Skip to: 501 +/* 497 */ MCD_OPC_Decode, 249, 17, 30, // Opcode: SW +/* 501 */ MCD_OPC_FilterValue, 112, 4, 0, 0, // Skip to: 510 +/* 506 */ MCD_OPC_Decode, 147, 17, 31, // Opcode: STE +/* 510 */ MCD_OPC_FilterValue, 113, 4, 0, 0, // Skip to: 519 +/* 515 */ MCD_OPC_Decode, 184, 14, 24, // Opcode: MS +/* 519 */ MCD_OPC_FilterValue, 120, 4, 0, 0, // Skip to: 528 +/* 524 */ MCD_OPC_Decode, 179, 11, 31, // Opcode: LE +/* 528 */ MCD_OPC_FilterValue, 121, 4, 0, 0, // Skip to: 537 +/* 533 */ MCD_OPC_Decode, 173, 5, 31, // Opcode: CE +/* 537 */ MCD_OPC_FilterValue, 122, 4, 0, 0, // Skip to: 546 +/* 542 */ MCD_OPC_Decode, 244, 3, 32, // Opcode: AE +/* 546 */ MCD_OPC_FilterValue, 123, 4, 0, 0, // Skip to: 555 +/* 551 */ MCD_OPC_Decode, 229, 15, 32, // Opcode: SE +/* 555 */ MCD_OPC_FilterValue, 124, 4, 0, 0, // Skip to: 564 +/* 560 */ MCD_OPC_Decode, 157, 14, 30, // Opcode: MDE +/* 564 */ MCD_OPC_FilterValue, 125, 4, 0, 0, // Skip to: 573 +/* 569 */ MCD_OPC_Decode, 203, 9, 32, // Opcode: DE +/* 573 */ MCD_OPC_FilterValue, 126, 4, 0, 0, // Skip to: 582 +/* 578 */ MCD_OPC_Decode, 165, 4, 32, // Opcode: AU +/* 582 */ MCD_OPC_FilterValue, 127, 4, 0, 0, // Skip to: 591 +/* 587 */ MCD_OPC_Decode, 246, 17, 32, // Opcode: SU +/* 591 */ MCD_OPC_FilterValue, 128, 1, 11, 0, 0, // Skip to: 608 +/* 597 */ MCD_OPC_CheckField, 16, 8, 0, 207, 39, 0, // Skip to: 10795 +/* 604 */ MCD_OPC_Decode, 253, 16, 33, // Opcode: SSM +/* 608 */ MCD_OPC_FilterValue, 130, 1, 11, 0, 0, // Skip to: 625 +/* 614 */ MCD_OPC_CheckField, 16, 8, 0, 190, 39, 0, // Skip to: 10795 +/* 621 */ MCD_OPC_Decode, 215, 13, 33, // Opcode: LPSW +/* 625 */ MCD_OPC_FilterValue, 131, 1, 4, 0, 0, // Skip to: 635 +/* 631 */ MCD_OPC_Decode, 208, 9, 34, // Opcode: DIAG +/* 635 */ MCD_OPC_FilterValue, 132, 1, 4, 0, 0, // Skip to: 645 +/* 641 */ MCD_OPC_Decode, 136, 5, 35, // Opcode: BRXH +/* 645 */ MCD_OPC_FilterValue, 133, 1, 4, 0, 0, // Skip to: 655 +/* 651 */ MCD_OPC_Decode, 138, 5, 35, // Opcode: BRXLE +/* 655 */ MCD_OPC_FilterValue, 134, 1, 4, 0, 0, // Skip to: 665 +/* 661 */ MCD_OPC_Decode, 143, 5, 36, // Opcode: BXH +/* 665 */ MCD_OPC_FilterValue, 135, 1, 4, 0, 0, // Skip to: 675 +/* 671 */ MCD_OPC_Decode, 145, 5, 36, // Opcode: BXLE +/* 675 */ MCD_OPC_FilterValue, 136, 1, 11, 0, 0, // Skip to: 692 +/* 681 */ MCD_OPC_CheckField, 16, 4, 0, 123, 39, 0, // Skip to: 10795 +/* 688 */ MCD_OPC_Decode, 238, 16, 37, // Opcode: SRL +/* 692 */ MCD_OPC_FilterValue, 137, 1, 11, 0, 0, // Skip to: 709 +/* 698 */ MCD_OPC_CheckField, 16, 4, 0, 106, 39, 0, // Skip to: 10795 +/* 705 */ MCD_OPC_Decode, 206, 16, 37, // Opcode: SLL +/* 709 */ MCD_OPC_FilterValue, 138, 1, 11, 0, 0, // Skip to: 726 +/* 715 */ MCD_OPC_CheckField, 16, 4, 0, 89, 39, 0, // Skip to: 10795 +/* 722 */ MCD_OPC_Decode, 231, 16, 37, // Opcode: SRA +/* 726 */ MCD_OPC_FilterValue, 139, 1, 11, 0, 0, // Skip to: 743 +/* 732 */ MCD_OPC_CheckField, 16, 4, 0, 72, 39, 0, // Skip to: 10795 +/* 739 */ MCD_OPC_Decode, 187, 16, 37, // Opcode: SLA +/* 743 */ MCD_OPC_FilterValue, 140, 1, 11, 0, 0, // Skip to: 760 +/* 749 */ MCD_OPC_CheckField, 16, 4, 0, 55, 39, 0, // Skip to: 10795 +/* 756 */ MCD_OPC_Decode, 235, 16, 38, // Opcode: SRDL +/* 760 */ MCD_OPC_FilterValue, 141, 1, 11, 0, 0, // Skip to: 777 +/* 766 */ MCD_OPC_CheckField, 16, 4, 0, 38, 39, 0, // Skip to: 10795 +/* 773 */ MCD_OPC_Decode, 195, 16, 38, // Opcode: SLDL +/* 777 */ MCD_OPC_FilterValue, 142, 1, 11, 0, 0, // Skip to: 794 +/* 783 */ MCD_OPC_CheckField, 16, 4, 0, 21, 39, 0, // Skip to: 10795 +/* 790 */ MCD_OPC_Decode, 234, 16, 38, // Opcode: SRDA +/* 794 */ MCD_OPC_FilterValue, 143, 1, 11, 0, 0, // Skip to: 811 +/* 800 */ MCD_OPC_CheckField, 16, 4, 0, 4, 39, 0, // Skip to: 10795 +/* 807 */ MCD_OPC_Decode, 194, 16, 38, // Opcode: SLDA +/* 811 */ MCD_OPC_FilterValue, 144, 1, 4, 0, 0, // Skip to: 821 +/* 817 */ MCD_OPC_Decode, 161, 17, 34, // Opcode: STM +/* 821 */ MCD_OPC_FilterValue, 145, 1, 4, 0, 0, // Skip to: 831 +/* 827 */ MCD_OPC_Decode, 148, 18, 39, // Opcode: TM +/* 831 */ MCD_OPC_FilterValue, 146, 1, 4, 0, 0, // Skip to: 841 +/* 837 */ MCD_OPC_Decode, 222, 14, 39, // Opcode: MVI +/* 841 */ MCD_OPC_FilterValue, 147, 1, 11, 0, 0, // Skip to: 858 +/* 847 */ MCD_OPC_CheckField, 16, 8, 0, 213, 38, 0, // Skip to: 10795 +/* 854 */ MCD_OPC_Decode, 177, 18, 33, // Opcode: TS +/* 858 */ MCD_OPC_FilterValue, 148, 1, 4, 0, 0, // Skip to: 868 +/* 864 */ MCD_OPC_Decode, 250, 14, 39, // Opcode: NI +/* 868 */ MCD_OPC_FilterValue, 149, 1, 4, 0, 0, // Skip to: 878 +/* 874 */ MCD_OPC_Decode, 248, 7, 39, // Opcode: CLI +/* 878 */ MCD_OPC_FilterValue, 150, 1, 4, 0, 0, // Skip to: 888 +/* 884 */ MCD_OPC_Decode, 150, 15, 39, // Opcode: OI +/* 888 */ MCD_OPC_FilterValue, 151, 1, 4, 0, 0, // Skip to: 898 +/* 894 */ MCD_OPC_Decode, 152, 24, 39, // Opcode: XI +/* 898 */ MCD_OPC_FilterValue, 152, 1, 4, 0, 0, // Skip to: 908 +/* 904 */ MCD_OPC_Decode, 243, 11, 34, // Opcode: LM +/* 908 */ MCD_OPC_FilterValue, 153, 1, 4, 0, 0, // Skip to: 918 +/* 914 */ MCD_OPC_Decode, 158, 18, 34, // Opcode: TRACE +/* 918 */ MCD_OPC_FilterValue, 154, 1, 4, 0, 0, // Skip to: 928 +/* 924 */ MCD_OPC_Decode, 133, 11, 40, // Opcode: LAM +/* 928 */ MCD_OPC_FilterValue, 155, 1, 4, 0, 0, // Skip to: 938 +/* 934 */ MCD_OPC_Decode, 255, 16, 40, // Opcode: STAM +/* 938 */ MCD_OPC_FilterValue, 165, 1, 147, 0, 0, // Skip to: 1091 +/* 944 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 947 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 956 +/* 952 */ MCD_OPC_Decode, 150, 10, 41, // Opcode: IIHH +/* 956 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 965 +/* 961 */ MCD_OPC_Decode, 151, 10, 41, // Opcode: IIHL +/* 965 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 974 +/* 970 */ MCD_OPC_Decode, 153, 10, 42, // Opcode: IILH +/* 974 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 983 +/* 979 */ MCD_OPC_Decode, 154, 10, 42, // Opcode: IILL +/* 983 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 992 +/* 988 */ MCD_OPC_Decode, 253, 14, 41, // Opcode: NIHH +/* 992 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 1001 +/* 997 */ MCD_OPC_Decode, 254, 14, 41, // Opcode: NIHL +/* 1001 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 1010 +/* 1006 */ MCD_OPC_Decode, 128, 15, 42, // Opcode: NILH +/* 1010 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 1019 +/* 1015 */ MCD_OPC_Decode, 129, 15, 42, // Opcode: NILL +/* 1019 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 1028 +/* 1024 */ MCD_OPC_Decode, 152, 15, 41, // Opcode: OIHH +/* 1028 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 1037 +/* 1033 */ MCD_OPC_Decode, 153, 15, 41, // Opcode: OIHL +/* 1037 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 1046 +/* 1042 */ MCD_OPC_Decode, 155, 15, 42, // Opcode: OILH +/* 1046 */ MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 1055 +/* 1051 */ MCD_OPC_Decode, 156, 15, 42, // Opcode: OILL +/* 1055 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 1064 +/* 1060 */ MCD_OPC_Decode, 237, 11, 43, // Opcode: LLIHH +/* 1064 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 1073 +/* 1069 */ MCD_OPC_Decode, 238, 11, 43, // Opcode: LLIHL +/* 1073 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 1082 +/* 1078 */ MCD_OPC_Decode, 240, 11, 43, // Opcode: LLILH +/* 1082 */ MCD_OPC_FilterValue, 15, 236, 37, 0, // Skip to: 10795 +/* 1087 */ MCD_OPC_Decode, 241, 11, 43, // Opcode: LLILL +/* 1091 */ MCD_OPC_FilterValue, 167, 1, 29, 1, 0, // Skip to: 1382 +/* 1097 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 1100 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1109 +/* 1105 */ MCD_OPC_Decode, 151, 18, 44, // Opcode: TMLH +/* 1109 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 1118 +/* 1114 */ MCD_OPC_Decode, 152, 18, 44, // Opcode: TMLL +/* 1118 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1127 +/* 1123 */ MCD_OPC_Decode, 149, 18, 45, // Opcode: TMHH +/* 1127 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 1136 +/* 1132 */ MCD_OPC_Decode, 150, 18, 45, // Opcode: TMHL +/* 1136 */ MCD_OPC_FilterValue, 4, 142, 0, 0, // Skip to: 1283 +/* 1141 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 1144 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 1153 +/* 1149 */ MCD_OPC_Decode, 212, 10, 46, // Opcode: JAsmO +/* 1153 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1162 +/* 1158 */ MCD_OPC_Decode, 196, 10, 46, // Opcode: JAsmH +/* 1162 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 1171 +/* 1167 */ MCD_OPC_Decode, 206, 10, 46, // Opcode: JAsmNLE +/* 1171 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 1180 +/* 1176 */ MCD_OPC_Decode, 198, 10, 46, // Opcode: JAsmL +/* 1180 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 1189 +/* 1185 */ MCD_OPC_Decode, 204, 10, 46, // Opcode: JAsmNHE +/* 1189 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 1198 +/* 1194 */ MCD_OPC_Decode, 200, 10, 46, // Opcode: JAsmLH +/* 1198 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 1207 +/* 1203 */ MCD_OPC_Decode, 202, 10, 46, // Opcode: JAsmNE +/* 1207 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 1216 +/* 1212 */ MCD_OPC_Decode, 195, 10, 46, // Opcode: JAsmE +/* 1216 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 1225 +/* 1221 */ MCD_OPC_Decode, 207, 10, 46, // Opcode: JAsmNLH +/* 1225 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 1234 +/* 1230 */ MCD_OPC_Decode, 197, 10, 46, // Opcode: JAsmHE +/* 1234 */ MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 1243 +/* 1239 */ MCD_OPC_Decode, 205, 10, 46, // Opcode: JAsmNL +/* 1243 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 1252 +/* 1248 */ MCD_OPC_Decode, 199, 10, 46, // Opcode: JAsmLE +/* 1252 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 1261 +/* 1257 */ MCD_OPC_Decode, 203, 10, 46, // Opcode: JAsmNH +/* 1261 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 1270 +/* 1266 */ MCD_OPC_Decode, 209, 10, 46, // Opcode: JAsmNO +/* 1270 */ MCD_OPC_FilterValue, 15, 4, 0, 0, // Skip to: 1279 +/* 1275 */ MCD_OPC_Decode, 194, 10, 46, // Opcode: J +/* 1279 */ MCD_OPC_Decode, 130, 5, 47, // Opcode: BRCAsm +/* 1283 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 1292 +/* 1288 */ MCD_OPC_Decode, 235, 4, 48, // Opcode: BRAS +/* 1292 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 1301 +/* 1297 */ MCD_OPC_Decode, 133, 5, 49, // Opcode: BRCT +/* 1301 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 1310 +/* 1306 */ MCD_OPC_Decode, 134, 5, 50, // Opcode: BRCTG +/* 1310 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 1319 +/* 1315 */ MCD_OPC_Decode, 212, 11, 51, // Opcode: LHI +/* 1319 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 1328 +/* 1324 */ MCD_OPC_Decode, 204, 11, 52, // Opcode: LGHI +/* 1328 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 1337 +/* 1333 */ MCD_OPC_Decode, 134, 4, 53, // Opcode: AHI +/* 1337 */ MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 1346 +/* 1342 */ MCD_OPC_Decode, 254, 3, 54, // Opcode: AGHI +/* 1346 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 1355 +/* 1351 */ MCD_OPC_Decode, 176, 14, 53, // Opcode: MHI +/* 1355 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 1364 +/* 1360 */ MCD_OPC_Decode, 173, 14, 54, // Opcode: MGHI +/* 1364 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 1373 +/* 1369 */ MCD_OPC_Decode, 184, 6, 51, // Opcode: CHI +/* 1373 */ MCD_OPC_FilterValue, 15, 201, 36, 0, // Skip to: 10795 +/* 1378 */ MCD_OPC_Decode, 214, 5, 52, // Opcode: CGHI +/* 1382 */ MCD_OPC_FilterValue, 168, 1, 4, 0, 0, // Skip to: 1392 +/* 1388 */ MCD_OPC_Decode, 212, 14, 55, // Opcode: MVCLE +/* 1392 */ MCD_OPC_FilterValue, 169, 1, 4, 0, 0, // Skip to: 1402 +/* 1398 */ MCD_OPC_Decode, 236, 6, 55, // Opcode: CLCLE +/* 1402 */ MCD_OPC_FilterValue, 172, 1, 4, 0, 0, // Skip to: 1412 +/* 1408 */ MCD_OPC_Decode, 165, 17, 39, // Opcode: STNSM +/* 1412 */ MCD_OPC_FilterValue, 173, 1, 4, 0, 0, // Skip to: 1422 +/* 1418 */ MCD_OPC_Decode, 232, 17, 39, // Opcode: STOSM +/* 1422 */ MCD_OPC_FilterValue, 174, 1, 4, 0, 0, // Skip to: 1432 +/* 1428 */ MCD_OPC_Decode, 185, 16, 56, // Opcode: SIGP +/* 1432 */ MCD_OPC_FilterValue, 175, 1, 4, 0, 0, // Skip to: 1442 +/* 1438 */ MCD_OPC_Decode, 153, 14, 39, // Opcode: MC +/* 1442 */ MCD_OPC_FilterValue, 177, 1, 4, 0, 0, // Skip to: 1452 +/* 1448 */ MCD_OPC_Decode, 222, 13, 21, // Opcode: LRA +/* 1452 */ MCD_OPC_FilterValue, 178, 1, 34, 6, 0, // Skip to: 3028 +/* 1458 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 1461 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1475 +/* 1466 */ MCD_OPC_CheckPredicate, 0, 108, 36, 0, // Skip to: 10795 +/* 1471 */ MCD_OPC_Decode, 146, 11, 33, // Opcode: LBEAR +/* 1475 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1489 +/* 1480 */ MCD_OPC_CheckPredicate, 0, 94, 36, 0, // Skip to: 10795 +/* 1485 */ MCD_OPC_Decode, 130, 17, 33, // Opcode: STBEAR +/* 1489 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1498 +/* 1494 */ MCD_OPC_Decode, 160, 17, 33, // Opcode: STIDP +/* 1498 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 1507 +/* 1503 */ MCD_OPC_Decode, 220, 15, 33, // Opcode: SCK +/* 1507 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 1516 +/* 1512 */ MCD_OPC_Decode, 133, 17, 33, // Opcode: STCK +/* 1516 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 1525 +/* 1521 */ MCD_OPC_Decode, 221, 15, 33, // Opcode: SCKC +/* 1525 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 1534 +/* 1530 */ MCD_OPC_Decode, 134, 17, 33, // Opcode: STCKC +/* 1534 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 1543 +/* 1539 */ MCD_OPC_Decode, 218, 16, 33, // Opcode: SPT +/* 1543 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 1552 +/* 1548 */ MCD_OPC_Decode, 234, 17, 33, // Opcode: STPT +/* 1552 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 1561 +/* 1557 */ MCD_OPC_Decode, 216, 16, 33, // Opcode: SPKA +/* 1561 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 1577 +/* 1566 */ MCD_OPC_CheckField, 0, 16, 0, 6, 36, 0, // Skip to: 10795 +/* 1573 */ MCD_OPC_Decode, 155, 10, 0, // Opcode: IPK +/* 1577 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 1593 +/* 1582 */ MCD_OPC_CheckField, 0, 16, 0, 246, 35, 0, // Skip to: 10795 +/* 1589 */ MCD_OPC_Decode, 185, 15, 0, // Opcode: PTLB +/* 1593 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 1602 +/* 1598 */ MCD_OPC_Decode, 219, 16, 33, // Opcode: SPX +/* 1602 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 1611 +/* 1607 */ MCD_OPC_Decode, 235, 17, 33, // Opcode: STPX +/* 1611 */ MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 1620 +/* 1616 */ MCD_OPC_Decode, 129, 17, 33, // Opcode: STAP +/* 1620 */ MCD_OPC_FilterValue, 20, 4, 0, 0, // Skip to: 1629 +/* 1625 */ MCD_OPC_Decode, 183, 16, 33, // Opcode: SIE +/* 1629 */ MCD_OPC_FilterValue, 24, 4, 0, 0, // Skip to: 1638 +/* 1634 */ MCD_OPC_Decode, 163, 15, 33, // Opcode: PC +/* 1638 */ MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 1647 +/* 1643 */ MCD_OPC_Decode, 211, 15, 33, // Opcode: SAC +/* 1647 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 1656 +/* 1652 */ MCD_OPC_Decode, 187, 5, 33, // Opcode: CFC +/* 1656 */ MCD_OPC_FilterValue, 33, 26, 0, 0, // Skip to: 1687 +/* 1661 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, 0, // Skip to: 1672 +/* 1668 */ MCD_OPC_Decode, 159, 10, 57, // Opcode: IPTEOptOpt +/* 1672 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 1683 +/* 1679 */ MCD_OPC_Decode, 158, 10, 58, // Opcode: IPTEOpt +/* 1683 */ MCD_OPC_Decode, 157, 10, 59, // Opcode: IPTE +/* 1687 */ MCD_OPC_FilterValue, 34, 18, 0, 0, // Skip to: 1710 +/* 1692 */ MCD_OPC_CheckField, 8, 8, 0, 136, 35, 0, // Skip to: 10795 +/* 1699 */ MCD_OPC_CheckField, 0, 4, 0, 129, 35, 0, // Skip to: 10795 +/* 1706 */ MCD_OPC_Decode, 156, 10, 1, // Opcode: IPM +/* 1710 */ MCD_OPC_FilterValue, 35, 11, 0, 0, // Skip to: 1726 +/* 1715 */ MCD_OPC_CheckField, 8, 8, 0, 113, 35, 0, // Skip to: 10795 +/* 1722 */ MCD_OPC_Decode, 162, 10, 3, // Opcode: IVSK +/* 1726 */ MCD_OPC_FilterValue, 36, 18, 0, 0, // Skip to: 1749 +/* 1731 */ MCD_OPC_CheckField, 8, 8, 0, 97, 35, 0, // Skip to: 10795 +/* 1738 */ MCD_OPC_CheckField, 0, 4, 0, 90, 35, 0, // Skip to: 10795 +/* 1745 */ MCD_OPC_Decode, 137, 10, 1, // Opcode: IAC +/* 1749 */ MCD_OPC_FilterValue, 37, 18, 0, 0, // Skip to: 1772 +/* 1754 */ MCD_OPC_CheckField, 8, 8, 0, 74, 35, 0, // Skip to: 10795 +/* 1761 */ MCD_OPC_CheckField, 0, 4, 0, 67, 35, 0, // Skip to: 10795 +/* 1768 */ MCD_OPC_Decode, 249, 16, 1, // Opcode: SSAR +/* 1772 */ MCD_OPC_FilterValue, 38, 18, 0, 0, // Skip to: 1795 +/* 1777 */ MCD_OPC_CheckField, 8, 8, 0, 51, 35, 0, // Skip to: 10795 +/* 1784 */ MCD_OPC_CheckField, 0, 4, 0, 44, 35, 0, // Skip to: 10795 +/* 1791 */ MCD_OPC_Decode, 236, 9, 1, // Opcode: EPAR +/* 1795 */ MCD_OPC_FilterValue, 39, 18, 0, 0, // Skip to: 1818 +/* 1800 */ MCD_OPC_CheckField, 8, 8, 0, 28, 35, 0, // Skip to: 10795 +/* 1807 */ MCD_OPC_CheckField, 0, 4, 0, 21, 35, 0, // Skip to: 10795 +/* 1814 */ MCD_OPC_Decode, 242, 9, 1, // Opcode: ESAR +/* 1818 */ MCD_OPC_FilterValue, 40, 11, 0, 0, // Skip to: 1834 +/* 1823 */ MCD_OPC_CheckField, 8, 8, 0, 5, 35, 0, // Skip to: 10795 +/* 1830 */ MCD_OPC_Decode, 181, 15, 60, // Opcode: PT +/* 1834 */ MCD_OPC_FilterValue, 41, 11, 0, 0, // Skip to: 1850 +/* 1839 */ MCD_OPC_CheckField, 8, 8, 0, 245, 34, 0, // Skip to: 10795 +/* 1846 */ MCD_OPC_Decode, 161, 10, 3, // Opcode: ISKE +/* 1850 */ MCD_OPC_FilterValue, 42, 11, 0, 0, // Skip to: 1866 +/* 1855 */ MCD_OPC_CheckField, 8, 8, 0, 229, 34, 0, // Skip to: 10795 +/* 1862 */ MCD_OPC_Decode, 204, 15, 60, // Opcode: RRBE +/* 1866 */ MCD_OPC_FilterValue, 43, 23, 0, 0, // Skip to: 1894 +/* 1871 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 1874 */ MCD_OPC_FilterValue, 0, 212, 34, 0, // Skip to: 10795 +/* 1879 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, 0, // Skip to: 1890 +/* 1886 */ MCD_OPC_Decode, 252, 16, 60, // Opcode: SSKEOpt +/* 1890 */ MCD_OPC_Decode, 251, 16, 61, // Opcode: SSKE +/* 1894 */ MCD_OPC_FilterValue, 44, 11, 0, 0, // Skip to: 1910 +/* 1899 */ MCD_OPC_CheckField, 8, 8, 0, 185, 34, 0, // Skip to: 10795 +/* 1906 */ MCD_OPC_Decode, 131, 18, 62, // Opcode: TB +/* 1910 */ MCD_OPC_FilterValue, 45, 11, 0, 0, // Skip to: 1926 +/* 1915 */ MCD_OPC_CheckField, 8, 8, 0, 169, 34, 0, // Skip to: 10795 +/* 1922 */ MCD_OPC_Decode, 222, 9, 13, // Opcode: DXR +/* 1926 */ MCD_OPC_FilterValue, 46, 11, 0, 0, // Skip to: 1942 +/* 1931 */ MCD_OPC_CheckField, 8, 8, 0, 153, 34, 0, // Skip to: 10795 +/* 1938 */ MCD_OPC_Decode, 170, 15, 62, // Opcode: PGIN +/* 1942 */ MCD_OPC_FilterValue, 47, 11, 0, 0, // Skip to: 1958 +/* 1947 */ MCD_OPC_CheckField, 8, 8, 0, 137, 34, 0, // Skip to: 10795 +/* 1954 */ MCD_OPC_Decode, 171, 15, 62, // Opcode: PGOUT +/* 1958 */ MCD_OPC_FilterValue, 48, 11, 0, 0, // Skip to: 1974 +/* 1963 */ MCD_OPC_CheckField, 0, 16, 0, 121, 34, 0, // Skip to: 10795 +/* 1970 */ MCD_OPC_Decode, 142, 9, 0, // Opcode: CSCH +/* 1974 */ MCD_OPC_FilterValue, 49, 11, 0, 0, // Skip to: 1990 +/* 1979 */ MCD_OPC_CheckField, 0, 16, 0, 105, 34, 0, // Skip to: 10795 +/* 1986 */ MCD_OPC_Decode, 136, 10, 0, // Opcode: HSCH +/* 1990 */ MCD_OPC_FilterValue, 50, 4, 0, 0, // Skip to: 1999 +/* 1995 */ MCD_OPC_Decode, 186, 14, 33, // Opcode: MSCH +/* 1999 */ MCD_OPC_FilterValue, 51, 4, 0, 0, // Skip to: 2008 +/* 2004 */ MCD_OPC_Decode, 250, 16, 33, // Opcode: SSCH +/* 2008 */ MCD_OPC_FilterValue, 52, 4, 0, 0, // Skip to: 2017 +/* 2013 */ MCD_OPC_Decode, 241, 17, 33, // Opcode: STSCH +/* 2017 */ MCD_OPC_FilterValue, 53, 4, 0, 0, // Skip to: 2026 +/* 2022 */ MCD_OPC_Decode, 178, 18, 33, // Opcode: TSCH +/* 2026 */ MCD_OPC_FilterValue, 54, 4, 0, 0, // Skip to: 2035 +/* 2031 */ MCD_OPC_Decode, 155, 18, 33, // Opcode: TPI +/* 2035 */ MCD_OPC_FilterValue, 55, 11, 0, 0, // Skip to: 2051 +/* 2040 */ MCD_OPC_CheckField, 0, 16, 0, 44, 34, 0, // Skip to: 10795 +/* 2047 */ MCD_OPC_Decode, 213, 15, 0, // Opcode: SAL +/* 2051 */ MCD_OPC_FilterValue, 56, 11, 0, 0, // Skip to: 2067 +/* 2056 */ MCD_OPC_CheckField, 0, 16, 0, 28, 34, 0, // Skip to: 10795 +/* 2063 */ MCD_OPC_Decode, 208, 15, 0, // Opcode: RSCH +/* 2067 */ MCD_OPC_FilterValue, 57, 4, 0, 0, // Skip to: 2076 +/* 2072 */ MCD_OPC_Decode, 141, 17, 33, // Opcode: STCRW +/* 2076 */ MCD_OPC_FilterValue, 58, 4, 0, 0, // Skip to: 2085 +/* 2081 */ MCD_OPC_Decode, 140, 17, 33, // Opcode: STCPS +/* 2085 */ MCD_OPC_FilterValue, 59, 11, 0, 0, // Skip to: 2101 +/* 2090 */ MCD_OPC_CheckField, 0, 16, 0, 250, 33, 0, // Skip to: 10795 +/* 2097 */ MCD_OPC_Decode, 191, 15, 0, // Opcode: RCHP +/* 2101 */ MCD_OPC_FilterValue, 60, 11, 0, 0, // Skip to: 2117 +/* 2106 */ MCD_OPC_CheckField, 0, 16, 0, 234, 33, 0, // Skip to: 10795 +/* 2113 */ MCD_OPC_Decode, 219, 15, 0, // Opcode: SCHM +/* 2117 */ MCD_OPC_FilterValue, 64, 11, 0, 0, // Skip to: 2133 +/* 2122 */ MCD_OPC_CheckField, 8, 8, 0, 218, 33, 0, // Skip to: 10795 +/* 2129 */ MCD_OPC_Decode, 175, 4, 62, // Opcode: BAKR +/* 2133 */ MCD_OPC_FilterValue, 65, 11, 0, 0, // Skip to: 2149 +/* 2138 */ MCD_OPC_CheckField, 8, 8, 0, 202, 33, 0, // Skip to: 10795 +/* 2145 */ MCD_OPC_Decode, 232, 6, 63, // Opcode: CKSM +/* 2149 */ MCD_OPC_FilterValue, 68, 11, 0, 0, // Skip to: 2165 +/* 2154 */ MCD_OPC_CheckField, 8, 8, 0, 186, 33, 0, // Skip to: 10795 +/* 2161 */ MCD_OPC_Decode, 223, 16, 11, // Opcode: SQDR +/* 2165 */ MCD_OPC_FilterValue, 69, 11, 0, 0, // Skip to: 2181 +/* 2170 */ MCD_OPC_CheckField, 8, 8, 0, 170, 33, 0, // Skip to: 10795 +/* 2177 */ MCD_OPC_Decode, 227, 16, 16, // Opcode: SQER +/* 2181 */ MCD_OPC_FilterValue, 70, 11, 0, 0, // Skip to: 2197 +/* 2186 */ MCD_OPC_CheckField, 8, 8, 0, 154, 33, 0, // Skip to: 10795 +/* 2193 */ MCD_OPC_Decode, 243, 17, 60, // Opcode: STURA +/* 2197 */ MCD_OPC_FilterValue, 71, 18, 0, 0, // Skip to: 2220 +/* 2202 */ MCD_OPC_CheckField, 8, 8, 0, 138, 33, 0, // Skip to: 10795 +/* 2209 */ MCD_OPC_CheckField, 0, 4, 0, 131, 33, 0, // Skip to: 10795 +/* 2216 */ MCD_OPC_Decode, 205, 14, 64, // Opcode: MSTA +/* 2220 */ MCD_OPC_FilterValue, 72, 11, 0, 0, // Skip to: 2236 +/* 2225 */ MCD_OPC_CheckField, 0, 16, 0, 115, 33, 0, // Skip to: 10795 +/* 2232 */ MCD_OPC_Decode, 162, 15, 0, // Opcode: PALB +/* 2236 */ MCD_OPC_FilterValue, 73, 11, 0, 0, // Skip to: 2252 +/* 2241 */ MCD_OPC_CheckField, 8, 8, 0, 99, 33, 0, // Skip to: 10795 +/* 2248 */ MCD_OPC_Decode, 239, 9, 8, // Opcode: EREG +/* 2252 */ MCD_OPC_FilterValue, 74, 11, 0, 0, // Skip to: 2268 +/* 2257 */ MCD_OPC_CheckField, 8, 8, 0, 83, 33, 0, // Skip to: 10795 +/* 2264 */ MCD_OPC_Decode, 245, 9, 65, // Opcode: ESTA +/* 2268 */ MCD_OPC_FilterValue, 75, 11, 0, 0, // Skip to: 2284 +/* 2273 */ MCD_OPC_CheckField, 8, 8, 0, 67, 33, 0, // Skip to: 10795 +/* 2280 */ MCD_OPC_Decode, 248, 13, 60, // Opcode: LURA +/* 2284 */ MCD_OPC_FilterValue, 76, 11, 0, 0, // Skip to: 2300 +/* 2289 */ MCD_OPC_CheckField, 8, 8, 0, 51, 33, 0, // Skip to: 10795 +/* 2296 */ MCD_OPC_Decode, 130, 18, 66, // Opcode: TAR +/* 2300 */ MCD_OPC_FilterValue, 77, 11, 0, 0, // Skip to: 2316 +/* 2305 */ MCD_OPC_CheckField, 8, 8, 0, 35, 33, 0, // Skip to: 10795 +/* 2312 */ MCD_OPC_Decode, 222, 8, 67, // Opcode: CPYA +/* 2316 */ MCD_OPC_FilterValue, 78, 11, 0, 0, // Skip to: 2332 +/* 2321 */ MCD_OPC_CheckField, 8, 8, 0, 19, 33, 0, // Skip to: 10795 +/* 2328 */ MCD_OPC_Decode, 217, 15, 66, // Opcode: SAR +/* 2332 */ MCD_OPC_FilterValue, 79, 11, 0, 0, // Skip to: 2348 +/* 2337 */ MCD_OPC_CheckField, 8, 8, 0, 3, 33, 0, // Skip to: 10795 +/* 2344 */ MCD_OPC_Decode, 225, 9, 68, // Opcode: EAR +/* 2348 */ MCD_OPC_FilterValue, 80, 11, 0, 0, // Skip to: 2364 +/* 2353 */ MCD_OPC_CheckField, 8, 8, 0, 243, 32, 0, // Skip to: 10795 +/* 2360 */ MCD_OPC_Decode, 145, 9, 69, // Opcode: CSP +/* 2364 */ MCD_OPC_FilterValue, 82, 11, 0, 0, // Skip to: 2380 +/* 2369 */ MCD_OPC_CheckField, 8, 8, 0, 227, 32, 0, // Skip to: 10795 +/* 2376 */ MCD_OPC_Decode, 203, 14, 9, // Opcode: MSR +/* 2380 */ MCD_OPC_FilterValue, 84, 11, 0, 0, // Skip to: 2396 +/* 2385 */ MCD_OPC_CheckField, 8, 8, 0, 211, 32, 0, // Skip to: 10795 +/* 2392 */ MCD_OPC_Decode, 226, 14, 62, // Opcode: MVPG +/* 2396 */ MCD_OPC_FilterValue, 85, 11, 0, 0, // Skip to: 2412 +/* 2401 */ MCD_OPC_CheckField, 8, 8, 0, 195, 32, 0, // Skip to: 10795 +/* 2408 */ MCD_OPC_Decode, 227, 14, 70, // Opcode: MVST +/* 2412 */ MCD_OPC_FilterValue, 87, 11, 0, 0, // Skip to: 2428 +/* 2417 */ MCD_OPC_CheckField, 8, 8, 0, 179, 32, 0, // Skip to: 10795 +/* 2424 */ MCD_OPC_Decode, 161, 9, 7, // Opcode: CUSE +/* 2428 */ MCD_OPC_FilterValue, 88, 11, 0, 0, // Skip to: 2444 +/* 2433 */ MCD_OPC_CheckField, 8, 8, 0, 163, 32, 0, // Skip to: 10795 +/* 2440 */ MCD_OPC_Decode, 141, 5, 62, // Opcode: BSG +/* 2444 */ MCD_OPC_FilterValue, 90, 11, 0, 0, // Skip to: 2460 +/* 2449 */ MCD_OPC_CheckField, 8, 8, 0, 147, 32, 0, // Skip to: 10795 +/* 2456 */ MCD_OPC_Decode, 140, 5, 62, // Opcode: BSA +/* 2460 */ MCD_OPC_FilterValue, 93, 11, 0, 0, // Skip to: 2476 +/* 2465 */ MCD_OPC_CheckField, 8, 8, 0, 131, 32, 0, // Skip to: 10795 +/* 2472 */ MCD_OPC_Decode, 198, 8, 70, // Opcode: CLST +/* 2476 */ MCD_OPC_FilterValue, 94, 11, 0, 0, // Skip to: 2492 +/* 2481 */ MCD_OPC_CheckField, 8, 8, 0, 115, 32, 0, // Skip to: 10795 +/* 2488 */ MCD_OPC_Decode, 245, 16, 70, // Opcode: SRST +/* 2492 */ MCD_OPC_FilterValue, 99, 11, 0, 0, // Skip to: 2508 +/* 2497 */ MCD_OPC_CheckField, 8, 8, 0, 99, 32, 0, // Skip to: 10795 +/* 2504 */ MCD_OPC_Decode, 214, 8, 7, // Opcode: CMPSC +/* 2508 */ MCD_OPC_FilterValue, 116, 4, 0, 0, // Skip to: 2517 +/* 2513 */ MCD_OPC_Decode, 184, 16, 33, // Opcode: SIGA +/* 2517 */ MCD_OPC_FilterValue, 118, 11, 0, 0, // Skip to: 2533 +/* 2522 */ MCD_OPC_CheckField, 0, 16, 0, 74, 32, 0, // Skip to: 10795 +/* 2529 */ MCD_OPC_Decode, 158, 24, 0, // Opcode: XSCH +/* 2533 */ MCD_OPC_FilterValue, 119, 4, 0, 0, // Skip to: 2542 +/* 2538 */ MCD_OPC_Decode, 203, 15, 33, // Opcode: RP +/* 2542 */ MCD_OPC_FilterValue, 120, 4, 0, 0, // Skip to: 2551 +/* 2547 */ MCD_OPC_Decode, 135, 17, 33, // Opcode: STCKE +/* 2551 */ MCD_OPC_FilterValue, 121, 4, 0, 0, // Skip to: 2560 +/* 2556 */ MCD_OPC_Decode, 212, 15, 33, // Opcode: SACF +/* 2560 */ MCD_OPC_FilterValue, 124, 4, 0, 0, // Skip to: 2569 +/* 2565 */ MCD_OPC_Decode, 136, 17, 33, // Opcode: STCKF +/* 2569 */ MCD_OPC_FilterValue, 125, 4, 0, 0, // Skip to: 2578 +/* 2574 */ MCD_OPC_Decode, 242, 17, 33, // Opcode: STSI +/* 2578 */ MCD_OPC_FilterValue, 128, 1, 4, 0, 0, // Skip to: 2588 +/* 2584 */ MCD_OPC_Decode, 212, 13, 33, // Opcode: LPP +/* 2588 */ MCD_OPC_FilterValue, 132, 1, 4, 0, 0, // Skip to: 2598 +/* 2594 */ MCD_OPC_Decode, 150, 11, 33, // Opcode: LCCTL +/* 2598 */ MCD_OPC_FilterValue, 133, 1, 4, 0, 0, // Skip to: 2608 +/* 2604 */ MCD_OPC_Decode, 201, 13, 33, // Opcode: LPCTL +/* 2608 */ MCD_OPC_FilterValue, 134, 1, 4, 0, 0, // Skip to: 2618 +/* 2614 */ MCD_OPC_Decode, 190, 15, 33, // Opcode: QSI +/* 2618 */ MCD_OPC_FilterValue, 135, 1, 4, 0, 0, // Skip to: 2628 +/* 2624 */ MCD_OPC_Decode, 233, 13, 33, // Opcode: LSCTL +/* 2628 */ MCD_OPC_FilterValue, 142, 1, 4, 0, 0, // Skip to: 2638 +/* 2634 */ MCD_OPC_Decode, 188, 15, 33, // Opcode: QCTRI +/* 2638 */ MCD_OPC_FilterValue, 143, 1, 9, 0, 0, // Skip to: 2653 +/* 2644 */ MCD_OPC_CheckPredicate, 1, 210, 31, 0, // Skip to: 10795 +/* 2649 */ MCD_OPC_Decode, 189, 15, 33, // Opcode: QPACI +/* 2653 */ MCD_OPC_FilterValue, 153, 1, 4, 0, 0, // Skip to: 2663 +/* 2659 */ MCD_OPC_Decode, 241, 16, 71, // Opcode: SRNM +/* 2663 */ MCD_OPC_FilterValue, 156, 1, 4, 0, 0, // Skip to: 2673 +/* 2669 */ MCD_OPC_Decode, 152, 17, 33, // Opcode: STFPC +/* 2673 */ MCD_OPC_FilterValue, 157, 1, 4, 0, 0, // Skip to: 2683 +/* 2679 */ MCD_OPC_Decode, 192, 11, 33, // Opcode: LFPC +/* 2683 */ MCD_OPC_FilterValue, 165, 1, 11, 0, 0, // Skip to: 2700 +/* 2689 */ MCD_OPC_CheckField, 8, 8, 0, 163, 31, 0, // Skip to: 10795 +/* 2696 */ MCD_OPC_Decode, 162, 18, 72, // Opcode: TRE +/* 2700 */ MCD_OPC_FilterValue, 166, 1, 23, 0, 0, // Skip to: 2729 +/* 2706 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 2709 */ MCD_OPC_FilterValue, 0, 145, 31, 0, // Skip to: 10795 +/* 2714 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, 0, // Skip to: 2725 +/* 2721 */ MCD_OPC_Decode, 155, 9, 7, // Opcode: CU21Opt +/* 2725 */ MCD_OPC_Decode, 154, 9, 73, // Opcode: CU21 +/* 2729 */ MCD_OPC_FilterValue, 167, 1, 23, 0, 0, // Skip to: 2758 +/* 2735 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 2738 */ MCD_OPC_FilterValue, 0, 116, 31, 0, // Skip to: 10795 +/* 2743 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, 0, // Skip to: 2754 +/* 2750 */ MCD_OPC_Decode, 151, 9, 7, // Opcode: CU12Opt +/* 2754 */ MCD_OPC_Decode, 150, 9, 73, // Opcode: CU12 +/* 2758 */ MCD_OPC_FilterValue, 176, 1, 4, 0, 0, // Skip to: 2768 +/* 2764 */ MCD_OPC_Decode, 151, 17, 33, // Opcode: STFLE +/* 2768 */ MCD_OPC_FilterValue, 177, 1, 4, 0, 0, // Skip to: 2778 +/* 2774 */ MCD_OPC_Decode, 150, 17, 33, // Opcode: STFL +/* 2778 */ MCD_OPC_FilterValue, 178, 1, 4, 0, 0, // Skip to: 2788 +/* 2784 */ MCD_OPC_Decode, 216, 13, 33, // Opcode: LPSWE +/* 2788 */ MCD_OPC_FilterValue, 184, 1, 9, 0, 0, // Skip to: 2803 +/* 2794 */ MCD_OPC_CheckPredicate, 2, 60, 31, 0, // Skip to: 10795 +/* 2799 */ MCD_OPC_Decode, 242, 16, 71, // Opcode: SRNMB +/* 2803 */ MCD_OPC_FilterValue, 185, 1, 4, 0, 0, // Skip to: 2813 +/* 2809 */ MCD_OPC_Decode, 243, 16, 71, // Opcode: SRNMT +/* 2813 */ MCD_OPC_FilterValue, 189, 1, 4, 0, 0, // Skip to: 2823 +/* 2819 */ MCD_OPC_Decode, 189, 11, 33, // Opcode: LFAS +/* 2823 */ MCD_OPC_FilterValue, 224, 1, 11, 0, 0, // Skip to: 2840 +/* 2829 */ MCD_OPC_CheckField, 8, 8, 0, 23, 31, 0, // Skip to: 10795 +/* 2836 */ MCD_OPC_Decode, 218, 15, 62, // Opcode: SCCTR +/* 2840 */ MCD_OPC_FilterValue, 225, 1, 11, 0, 0, // Skip to: 2857 +/* 2846 */ MCD_OPC_CheckField, 8, 8, 0, 6, 31, 0, // Skip to: 10795 +/* 2853 */ MCD_OPC_Decode, 215, 16, 62, // Opcode: SPCTR +/* 2857 */ MCD_OPC_FilterValue, 228, 1, 11, 0, 0, // Skip to: 2874 +/* 2863 */ MCD_OPC_CheckField, 8, 8, 0, 245, 30, 0, // Skip to: 10795 +/* 2870 */ MCD_OPC_Decode, 227, 9, 62, // Opcode: ECCTR +/* 2874 */ MCD_OPC_FilterValue, 229, 1, 11, 0, 0, // Skip to: 2891 +/* 2880 */ MCD_OPC_CheckField, 8, 8, 0, 228, 30, 0, // Skip to: 10795 +/* 2887 */ MCD_OPC_Decode, 237, 9, 62, // Opcode: EPCTR +/* 2891 */ MCD_OPC_FilterValue, 232, 1, 16, 0, 0, // Skip to: 2913 +/* 2897 */ MCD_OPC_CheckPredicate, 3, 213, 30, 0, // Skip to: 10795 +/* 2902 */ MCD_OPC_CheckField, 8, 4, 0, 206, 30, 0, // Skip to: 10795 +/* 2909 */ MCD_OPC_Decode, 177, 15, 74, // Opcode: PPA +/* 2913 */ MCD_OPC_FilterValue, 236, 1, 23, 0, 0, // Skip to: 2942 +/* 2919 */ MCD_OPC_CheckPredicate, 4, 191, 30, 0, // Skip to: 10795 +/* 2924 */ MCD_OPC_CheckField, 8, 8, 0, 184, 30, 0, // Skip to: 10795 +/* 2931 */ MCD_OPC_CheckField, 0, 4, 0, 177, 30, 0, // Skip to: 10795 +/* 2938 */ MCD_OPC_Decode, 247, 9, 1, // Opcode: ETND +/* 2942 */ MCD_OPC_FilterValue, 237, 1, 11, 0, 0, // Skip to: 2959 +/* 2948 */ MCD_OPC_CheckField, 8, 8, 0, 160, 30, 0, // Skip to: 10795 +/* 2955 */ MCD_OPC_Decode, 228, 9, 60, // Opcode: ECPGA +/* 2959 */ MCD_OPC_FilterValue, 248, 1, 16, 0, 0, // Skip to: 2981 +/* 2965 */ MCD_OPC_CheckPredicate, 4, 145, 30, 0, // Skip to: 10795 +/* 2970 */ MCD_OPC_CheckField, 0, 16, 0, 138, 30, 0, // Skip to: 10795 +/* 2977 */ MCD_OPC_Decode, 145, 18, 0, // Opcode: TEND +/* 2981 */ MCD_OPC_FilterValue, 250, 1, 16, 0, 0, // Skip to: 3003 +/* 2987 */ MCD_OPC_CheckPredicate, 5, 123, 30, 0, // Skip to: 10795 +/* 2992 */ MCD_OPC_CheckField, 8, 8, 0, 116, 30, 0, // Skip to: 10795 +/* 2999 */ MCD_OPC_Decode, 251, 14, 75, // Opcode: NIAI +/* 3003 */ MCD_OPC_FilterValue, 252, 1, 9, 0, 0, // Skip to: 3018 +/* 3009 */ MCD_OPC_CheckPredicate, 4, 101, 30, 0, // Skip to: 10795 +/* 3014 */ MCD_OPC_Decode, 128, 18, 33, // Opcode: TABORT +/* 3018 */ MCD_OPC_FilterValue, 255, 1, 91, 30, 0, // Skip to: 10795 +/* 3024 */ MCD_OPC_Decode, 161, 18, 33, // Opcode: TRAP4 +/* 3028 */ MCD_OPC_FilterValue, 179, 1, 238, 11, 0, // Skip to: 6088 +/* 3034 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 3037 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3053 +/* 3042 */ MCD_OPC_CheckField, 8, 8, 0, 66, 30, 0, // Skip to: 10795 +/* 3049 */ MCD_OPC_Decode, 208, 13, 16, // Opcode: LPEBR +/* 3053 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 3069 +/* 3058 */ MCD_OPC_CheckField, 8, 8, 0, 50, 30, 0, // Skip to: 10795 +/* 3065 */ MCD_OPC_Decode, 252, 11, 16, // Opcode: LNEBR +/* 3069 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 3085 +/* 3074 */ MCD_OPC_CheckField, 8, 8, 0, 34, 30, 0, // Skip to: 10795 +/* 3081 */ MCD_OPC_Decode, 238, 13, 16, // Opcode: LTEBR +/* 3085 */ MCD_OPC_FilterValue, 3, 11, 0, 0, // Skip to: 3101 +/* 3090 */ MCD_OPC_CheckField, 8, 8, 0, 18, 30, 0, // Skip to: 10795 +/* 3097 */ MCD_OPC_Decode, 155, 11, 16, // Opcode: LCEBR +/* 3101 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 3117 +/* 3106 */ MCD_OPC_CheckField, 8, 8, 0, 2, 30, 0, // Skip to: 10795 +/* 3113 */ MCD_OPC_Decode, 168, 11, 76, // Opcode: LDEBR +/* 3117 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 3133 +/* 3122 */ MCD_OPC_CheckField, 8, 8, 0, 242, 29, 0, // Skip to: 10795 +/* 3129 */ MCD_OPC_Decode, 252, 13, 77, // Opcode: LXDBR +/* 3133 */ MCD_OPC_FilterValue, 6, 11, 0, 0, // Skip to: 3149 +/* 3138 */ MCD_OPC_CheckField, 8, 8, 0, 226, 29, 0, // Skip to: 10795 +/* 3145 */ MCD_OPC_Decode, 129, 14, 78, // Opcode: LXEBR +/* 3149 */ MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 3165 +/* 3154 */ MCD_OPC_CheckField, 8, 8, 0, 210, 29, 0, // Skip to: 10795 +/* 3161 */ MCD_OPC_Decode, 232, 14, 14, // Opcode: MXDBR +/* 3165 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 3181 +/* 3170 */ MCD_OPC_CheckField, 8, 8, 0, 194, 29, 0, // Skip to: 10795 +/* 3177 */ MCD_OPC_Decode, 241, 10, 16, // Opcode: KEBR +/* 3181 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 3197 +/* 3186 */ MCD_OPC_CheckField, 8, 8, 0, 178, 29, 0, // Skip to: 10795 +/* 3193 */ MCD_OPC_Decode, 175, 5, 16, // Opcode: CEBR +/* 3197 */ MCD_OPC_FilterValue, 10, 11, 0, 0, // Skip to: 3213 +/* 3202 */ MCD_OPC_CheckField, 8, 8, 0, 162, 29, 0, // Skip to: 10795 +/* 3209 */ MCD_OPC_Decode, 246, 3, 18, // Opcode: AEBR +/* 3213 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 3229 +/* 3218 */ MCD_OPC_CheckField, 8, 8, 0, 146, 29, 0, // Skip to: 10795 +/* 3225 */ MCD_OPC_Decode, 231, 15, 18, // Opcode: SEBR +/* 3229 */ MCD_OPC_FilterValue, 12, 11, 0, 0, // Skip to: 3245 +/* 3234 */ MCD_OPC_CheckField, 8, 8, 0, 130, 29, 0, // Skip to: 10795 +/* 3241 */ MCD_OPC_Decode, 159, 14, 19, // Opcode: MDEBR +/* 3245 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 3261 +/* 3250 */ MCD_OPC_CheckField, 8, 8, 0, 114, 29, 0, // Skip to: 10795 +/* 3257 */ MCD_OPC_Decode, 205, 9, 18, // Opcode: DEBR +/* 3261 */ MCD_OPC_FilterValue, 14, 11, 0, 0, // Skip to: 3277 +/* 3266 */ MCD_OPC_CheckField, 8, 4, 0, 98, 29, 0, // Skip to: 10795 +/* 3273 */ MCD_OPC_Decode, 145, 14, 79, // Opcode: MAEBR +/* 3277 */ MCD_OPC_FilterValue, 15, 11, 0, 0, // Skip to: 3293 +/* 3282 */ MCD_OPC_CheckField, 8, 4, 0, 82, 29, 0, // Skip to: 10795 +/* 3289 */ MCD_OPC_Decode, 193, 14, 79, // Opcode: MSEBR +/* 3293 */ MCD_OPC_FilterValue, 16, 11, 0, 0, // Skip to: 3309 +/* 3298 */ MCD_OPC_CheckField, 8, 8, 0, 66, 29, 0, // Skip to: 10795 +/* 3305 */ MCD_OPC_Decode, 203, 13, 11, // Opcode: LPDBR +/* 3309 */ MCD_OPC_FilterValue, 17, 11, 0, 0, // Skip to: 3325 +/* 3314 */ MCD_OPC_CheckField, 8, 8, 0, 50, 29, 0, // Skip to: 10795 +/* 3321 */ MCD_OPC_Decode, 248, 11, 11, // Opcode: LNDBR +/* 3325 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 3341 +/* 3330 */ MCD_OPC_CheckField, 8, 8, 0, 34, 29, 0, // Skip to: 10795 +/* 3337 */ MCD_OPC_Decode, 235, 13, 11, // Opcode: LTDBR +/* 3341 */ MCD_OPC_FilterValue, 19, 11, 0, 0, // Skip to: 3357 +/* 3346 */ MCD_OPC_CheckField, 8, 8, 0, 18, 29, 0, // Skip to: 10795 +/* 3353 */ MCD_OPC_Decode, 151, 11, 11, // Opcode: LCDBR +/* 3357 */ MCD_OPC_FilterValue, 20, 11, 0, 0, // Skip to: 3373 +/* 3362 */ MCD_OPC_CheckField, 8, 8, 0, 2, 29, 0, // Skip to: 10795 +/* 3369 */ MCD_OPC_Decode, 226, 16, 16, // Opcode: SQEBR +/* 3373 */ MCD_OPC_FilterValue, 21, 11, 0, 0, // Skip to: 3389 +/* 3378 */ MCD_OPC_CheckField, 8, 8, 0, 242, 28, 0, // Skip to: 10795 +/* 3385 */ MCD_OPC_Decode, 222, 16, 11, // Opcode: SQDBR +/* 3389 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 3405 +/* 3394 */ MCD_OPC_CheckField, 8, 8, 0, 226, 28, 0, // Skip to: 10795 +/* 3401 */ MCD_OPC_Decode, 228, 16, 80, // Opcode: SQXBR +/* 3405 */ MCD_OPC_FilterValue, 23, 11, 0, 0, // Skip to: 3421 +/* 3410 */ MCD_OPC_CheckField, 8, 8, 0, 210, 28, 0, // Skip to: 10795 +/* 3417 */ MCD_OPC_Decode, 167, 14, 18, // Opcode: MEEBR +/* 3421 */ MCD_OPC_FilterValue, 24, 11, 0, 0, // Skip to: 3437 +/* 3426 */ MCD_OPC_CheckField, 8, 8, 0, 194, 28, 0, // Skip to: 10795 +/* 3433 */ MCD_OPC_Decode, 237, 10, 11, // Opcode: KDBR +/* 3437 */ MCD_OPC_FilterValue, 25, 11, 0, 0, // Skip to: 3453 +/* 3442 */ MCD_OPC_CheckField, 8, 8, 0, 178, 28, 0, // Skip to: 10795 +/* 3449 */ MCD_OPC_Decode, 150, 5, 11, // Opcode: CDBR +/* 3453 */ MCD_OPC_FilterValue, 26, 11, 0, 0, // Skip to: 3469 +/* 3458 */ MCD_OPC_CheckField, 8, 8, 0, 162, 28, 0, // Skip to: 10795 +/* 3465 */ MCD_OPC_Decode, 240, 3, 15, // Opcode: ADBR +/* 3469 */ MCD_OPC_FilterValue, 27, 11, 0, 0, // Skip to: 3485 +/* 3474 */ MCD_OPC_CheckField, 8, 8, 0, 146, 28, 0, // Skip to: 10795 +/* 3481 */ MCD_OPC_Decode, 225, 15, 15, // Opcode: SDBR +/* 3485 */ MCD_OPC_FilterValue, 28, 11, 0, 0, // Skip to: 3501 +/* 3490 */ MCD_OPC_CheckField, 8, 8, 0, 130, 28, 0, // Skip to: 10795 +/* 3497 */ MCD_OPC_Decode, 156, 14, 15, // Opcode: MDBR +/* 3501 */ MCD_OPC_FilterValue, 29, 11, 0, 0, // Skip to: 3517 +/* 3506 */ MCD_OPC_CheckField, 8, 8, 0, 114, 28, 0, // Skip to: 10795 +/* 3513 */ MCD_OPC_Decode, 199, 9, 15, // Opcode: DDBR +/* 3517 */ MCD_OPC_FilterValue, 30, 11, 0, 0, // Skip to: 3533 +/* 3522 */ MCD_OPC_CheckField, 8, 4, 0, 98, 28, 0, // Skip to: 10795 +/* 3529 */ MCD_OPC_Decode, 141, 14, 81, // Opcode: MADBR +/* 3533 */ MCD_OPC_FilterValue, 31, 11, 0, 0, // Skip to: 3549 +/* 3538 */ MCD_OPC_CheckField, 8, 4, 0, 82, 28, 0, // Skip to: 10795 +/* 3545 */ MCD_OPC_Decode, 189, 14, 81, // Opcode: MSDBR +/* 3549 */ MCD_OPC_FilterValue, 36, 11, 0, 0, // Skip to: 3565 +/* 3554 */ MCD_OPC_CheckField, 8, 8, 0, 66, 28, 0, // Skip to: 10795 +/* 3561 */ MCD_OPC_Decode, 169, 11, 76, // Opcode: LDER +/* 3565 */ MCD_OPC_FilterValue, 37, 11, 0, 0, // Skip to: 3581 +/* 3570 */ MCD_OPC_CheckField, 8, 8, 0, 50, 28, 0, // Skip to: 10795 +/* 3577 */ MCD_OPC_Decode, 253, 13, 77, // Opcode: LXDR +/* 3581 */ MCD_OPC_FilterValue, 38, 11, 0, 0, // Skip to: 3597 +/* 3586 */ MCD_OPC_CheckField, 8, 8, 0, 34, 28, 0, // Skip to: 10795 +/* 3593 */ MCD_OPC_Decode, 130, 14, 78, // Opcode: LXER +/* 3597 */ MCD_OPC_FilterValue, 46, 11, 0, 0, // Skip to: 3613 +/* 3602 */ MCD_OPC_CheckField, 8, 4, 0, 18, 28, 0, // Skip to: 10795 +/* 3609 */ MCD_OPC_Decode, 146, 14, 79, // Opcode: MAER +/* 3613 */ MCD_OPC_FilterValue, 47, 11, 0, 0, // Skip to: 3629 +/* 3618 */ MCD_OPC_CheckField, 8, 4, 0, 2, 28, 0, // Skip to: 10795 +/* 3625 */ MCD_OPC_Decode, 194, 14, 79, // Opcode: MSER +/* 3629 */ MCD_OPC_FilterValue, 54, 11, 0, 0, // Skip to: 3645 +/* 3634 */ MCD_OPC_CheckField, 8, 8, 0, 242, 27, 0, // Skip to: 10795 +/* 3641 */ MCD_OPC_Decode, 229, 16, 80, // Opcode: SQXR +/* 3645 */ MCD_OPC_FilterValue, 55, 11, 0, 0, // Skip to: 3661 +/* 3650 */ MCD_OPC_CheckField, 8, 8, 0, 226, 27, 0, // Skip to: 10795 +/* 3657 */ MCD_OPC_Decode, 168, 14, 18, // Opcode: MEER +/* 3661 */ MCD_OPC_FilterValue, 56, 11, 0, 0, // Skip to: 3677 +/* 3666 */ MCD_OPC_CheckField, 8, 4, 0, 210, 27, 0, // Skip to: 10795 +/* 3673 */ MCD_OPC_Decode, 151, 14, 81, // Opcode: MAYLR +/* 3677 */ MCD_OPC_FilterValue, 57, 11, 0, 0, // Skip to: 3693 +/* 3682 */ MCD_OPC_CheckField, 8, 4, 0, 194, 27, 0, // Skip to: 10795 +/* 3689 */ MCD_OPC_Decode, 241, 14, 82, // Opcode: MYLR +/* 3693 */ MCD_OPC_FilterValue, 58, 11, 0, 0, // Skip to: 3709 +/* 3698 */ MCD_OPC_CheckField, 8, 4, 0, 178, 27, 0, // Skip to: 10795 +/* 3705 */ MCD_OPC_Decode, 152, 14, 83, // Opcode: MAYR +/* 3709 */ MCD_OPC_FilterValue, 59, 11, 0, 0, // Skip to: 3725 +/* 3714 */ MCD_OPC_CheckField, 8, 4, 0, 162, 27, 0, // Skip to: 10795 +/* 3721 */ MCD_OPC_Decode, 242, 14, 84, // Opcode: MYR +/* 3725 */ MCD_OPC_FilterValue, 60, 11, 0, 0, // Skip to: 3741 +/* 3730 */ MCD_OPC_CheckField, 8, 4, 0, 146, 27, 0, // Skip to: 10795 +/* 3737 */ MCD_OPC_Decode, 149, 14, 81, // Opcode: MAYHR +/* 3741 */ MCD_OPC_FilterValue, 61, 11, 0, 0, // Skip to: 3757 +/* 3746 */ MCD_OPC_CheckField, 8, 4, 0, 130, 27, 0, // Skip to: 10795 +/* 3753 */ MCD_OPC_Decode, 239, 14, 82, // Opcode: MYHR +/* 3757 */ MCD_OPC_FilterValue, 62, 11, 0, 0, // Skip to: 3773 +/* 3762 */ MCD_OPC_CheckField, 8, 4, 0, 114, 27, 0, // Skip to: 10795 +/* 3769 */ MCD_OPC_Decode, 142, 14, 81, // Opcode: MADR +/* 3773 */ MCD_OPC_FilterValue, 63, 11, 0, 0, // Skip to: 3789 +/* 3778 */ MCD_OPC_CheckField, 8, 4, 0, 98, 27, 0, // Skip to: 10795 +/* 3785 */ MCD_OPC_Decode, 190, 14, 81, // Opcode: MSDR +/* 3789 */ MCD_OPC_FilterValue, 64, 11, 0, 0, // Skip to: 3805 +/* 3794 */ MCD_OPC_CheckField, 8, 8, 0, 82, 27, 0, // Skip to: 10795 +/* 3801 */ MCD_OPC_Decode, 219, 13, 80, // Opcode: LPXBR +/* 3805 */ MCD_OPC_FilterValue, 65, 11, 0, 0, // Skip to: 3821 +/* 3810 */ MCD_OPC_CheckField, 8, 8, 0, 66, 27, 0, // Skip to: 10795 +/* 3817 */ MCD_OPC_Decode, 129, 12, 80, // Opcode: LNXBR +/* 3821 */ MCD_OPC_FilterValue, 66, 11, 0, 0, // Skip to: 3837 +/* 3826 */ MCD_OPC_CheckField, 8, 8, 0, 50, 27, 0, // Skip to: 10795 +/* 3833 */ MCD_OPC_Decode, 245, 13, 80, // Opcode: LTXBR +/* 3837 */ MCD_OPC_FilterValue, 67, 11, 0, 0, // Skip to: 3853 +/* 3842 */ MCD_OPC_CheckField, 8, 8, 0, 34, 27, 0, // Skip to: 10795 +/* 3849 */ MCD_OPC_Decode, 162, 11, 80, // Opcode: LCXBR +/* 3853 */ MCD_OPC_FilterValue, 68, 20, 0, 0, // Skip to: 3878 +/* 3858 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, 0, // Skip to: 3869 +/* 3865 */ MCD_OPC_Decode, 180, 11, 17, // Opcode: LEDBR +/* 3869 */ MCD_OPC_CheckPredicate, 2, 9, 27, 0, // Skip to: 10795 +/* 3874 */ MCD_OPC_Decode, 181, 11, 85, // Opcode: LEDBRA +/* 3878 */ MCD_OPC_FilterValue, 69, 20, 0, 0, // Skip to: 3903 +/* 3883 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, 0, // Skip to: 3894 +/* 3890 */ MCD_OPC_Decode, 174, 11, 80, // Opcode: LDXBR +/* 3894 */ MCD_OPC_CheckPredicate, 2, 240, 26, 0, // Skip to: 10795 +/* 3899 */ MCD_OPC_Decode, 175, 11, 86, // Opcode: LDXBRA +/* 3903 */ MCD_OPC_FilterValue, 70, 20, 0, 0, // Skip to: 3928 +/* 3908 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, 0, // Skip to: 3919 +/* 3915 */ MCD_OPC_Decode, 185, 11, 80, // Opcode: LEXBR +/* 3919 */ MCD_OPC_CheckPredicate, 2, 215, 26, 0, // Skip to: 10795 +/* 3924 */ MCD_OPC_Decode, 186, 11, 86, // Opcode: LEXBRA +/* 3928 */ MCD_OPC_FilterValue, 71, 20, 0, 0, // Skip to: 3953 +/* 3933 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 3944 +/* 3940 */ MCD_OPC_Decode, 129, 10, 87, // Opcode: FIXBR +/* 3944 */ MCD_OPC_CheckPredicate, 2, 190, 26, 0, // Skip to: 10795 +/* 3949 */ MCD_OPC_Decode, 130, 10, 86, // Opcode: FIXBRA +/* 3953 */ MCD_OPC_FilterValue, 72, 11, 0, 0, // Skip to: 3969 +/* 3958 */ MCD_OPC_CheckField, 8, 8, 0, 174, 26, 0, // Skip to: 10795 +/* 3965 */ MCD_OPC_Decode, 251, 10, 80, // Opcode: KXBR +/* 3969 */ MCD_OPC_FilterValue, 73, 11, 0, 0, // Skip to: 3985 +/* 3974 */ MCD_OPC_CheckField, 8, 8, 0, 158, 26, 0, // Skip to: 10795 +/* 3981 */ MCD_OPC_Decode, 173, 9, 80, // Opcode: CXBR +/* 3985 */ MCD_OPC_FilterValue, 74, 11, 0, 0, // Skip to: 4001 +/* 3990 */ MCD_OPC_CheckField, 8, 8, 0, 142, 26, 0, // Skip to: 10795 +/* 3997 */ MCD_OPC_Decode, 169, 4, 13, // Opcode: AXBR +/* 4001 */ MCD_OPC_FilterValue, 75, 11, 0, 0, // Skip to: 4017 +/* 4006 */ MCD_OPC_CheckField, 8, 8, 0, 126, 26, 0, // Skip to: 10795 +/* 4013 */ MCD_OPC_Decode, 251, 17, 13, // Opcode: SXBR +/* 4017 */ MCD_OPC_FilterValue, 76, 11, 0, 0, // Skip to: 4033 +/* 4022 */ MCD_OPC_CheckField, 8, 8, 0, 110, 26, 0, // Skip to: 10795 +/* 4029 */ MCD_OPC_Decode, 229, 14, 13, // Opcode: MXBR +/* 4033 */ MCD_OPC_FilterValue, 77, 11, 0, 0, // Skip to: 4049 +/* 4038 */ MCD_OPC_CheckField, 8, 8, 0, 94, 26, 0, // Skip to: 10795 +/* 4045 */ MCD_OPC_Decode, 221, 9, 13, // Opcode: DXBR +/* 4049 */ MCD_OPC_FilterValue, 80, 11, 0, 0, // Skip to: 4065 +/* 4054 */ MCD_OPC_CheckField, 8, 4, 0, 78, 26, 0, // Skip to: 10795 +/* 4061 */ MCD_OPC_Decode, 133, 18, 88, // Opcode: TBEDR +/* 4065 */ MCD_OPC_FilterValue, 81, 11, 0, 0, // Skip to: 4081 +/* 4070 */ MCD_OPC_CheckField, 8, 4, 0, 62, 26, 0, // Skip to: 10795 +/* 4077 */ MCD_OPC_Decode, 132, 18, 89, // Opcode: TBDR +/* 4081 */ MCD_OPC_FilterValue, 83, 4, 0, 0, // Skip to: 4090 +/* 4086 */ MCD_OPC_Decode, 210, 9, 90, // Opcode: DIEBR +/* 4090 */ MCD_OPC_FilterValue, 87, 20, 0, 0, // Skip to: 4115 +/* 4095 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 4106 +/* 4102 */ MCD_OPC_Decode, 254, 9, 91, // Opcode: FIEBR +/* 4106 */ MCD_OPC_CheckPredicate, 2, 28, 26, 0, // Skip to: 10795 +/* 4111 */ MCD_OPC_Decode, 255, 9, 92, // Opcode: FIEBRA +/* 4115 */ MCD_OPC_FilterValue, 88, 11, 0, 0, // Skip to: 4131 +/* 4120 */ MCD_OPC_CheckField, 8, 8, 0, 12, 26, 0, // Skip to: 10795 +/* 4127 */ MCD_OPC_Decode, 146, 18, 76, // Opcode: THDER +/* 4131 */ MCD_OPC_FilterValue, 89, 11, 0, 0, // Skip to: 4147 +/* 4136 */ MCD_OPC_CheckField, 8, 8, 0, 252, 25, 0, // Skip to: 10795 +/* 4143 */ MCD_OPC_Decode, 147, 18, 11, // Opcode: THDR +/* 4147 */ MCD_OPC_FilterValue, 91, 4, 0, 0, // Skip to: 4156 +/* 4152 */ MCD_OPC_Decode, 209, 9, 93, // Opcode: DIDBR +/* 4156 */ MCD_OPC_FilterValue, 95, 20, 0, 0, // Skip to: 4181 +/* 4161 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 4172 +/* 4168 */ MCD_OPC_Decode, 250, 9, 89, // Opcode: FIDBR +/* 4172 */ MCD_OPC_CheckPredicate, 2, 218, 25, 0, // Skip to: 10795 +/* 4177 */ MCD_OPC_Decode, 251, 9, 94, // Opcode: FIDBRA +/* 4181 */ MCD_OPC_FilterValue, 96, 11, 0, 0, // Skip to: 4197 +/* 4186 */ MCD_OPC_CheckField, 8, 8, 0, 202, 25, 0, // Skip to: 10795 +/* 4193 */ MCD_OPC_Decode, 220, 13, 80, // Opcode: LPXR +/* 4197 */ MCD_OPC_FilterValue, 97, 11, 0, 0, // Skip to: 4213 +/* 4202 */ MCD_OPC_CheckField, 8, 8, 0, 186, 25, 0, // Skip to: 10795 +/* 4209 */ MCD_OPC_Decode, 130, 12, 80, // Opcode: LNXR +/* 4213 */ MCD_OPC_FilterValue, 98, 11, 0, 0, // Skip to: 4229 +/* 4218 */ MCD_OPC_CheckField, 8, 8, 0, 170, 25, 0, // Skip to: 10795 +/* 4225 */ MCD_OPC_Decode, 246, 13, 80, // Opcode: LTXR +/* 4229 */ MCD_OPC_FilterValue, 99, 11, 0, 0, // Skip to: 4245 +/* 4234 */ MCD_OPC_CheckField, 8, 8, 0, 154, 25, 0, // Skip to: 10795 +/* 4241 */ MCD_OPC_Decode, 163, 11, 80, // Opcode: LCXR +/* 4245 */ MCD_OPC_FilterValue, 101, 11, 0, 0, // Skip to: 4261 +/* 4250 */ MCD_OPC_CheckField, 8, 8, 0, 138, 25, 0, // Skip to: 10795 +/* 4257 */ MCD_OPC_Decode, 131, 14, 80, // Opcode: LXR +/* 4261 */ MCD_OPC_FilterValue, 102, 11, 0, 0, // Skip to: 4277 +/* 4266 */ MCD_OPC_CheckField, 8, 8, 0, 122, 25, 0, // Skip to: 10795 +/* 4273 */ MCD_OPC_Decode, 187, 11, 95, // Opcode: LEXR +/* 4277 */ MCD_OPC_FilterValue, 103, 11, 0, 0, // Skip to: 4293 +/* 4282 */ MCD_OPC_CheckField, 8, 8, 0, 106, 25, 0, // Skip to: 10795 +/* 4289 */ MCD_OPC_Decode, 131, 10, 80, // Opcode: FIXR +/* 4293 */ MCD_OPC_FilterValue, 105, 11, 0, 0, // Skip to: 4309 +/* 4298 */ MCD_OPC_CheckField, 8, 8, 0, 90, 25, 0, // Skip to: 10795 +/* 4305 */ MCD_OPC_Decode, 188, 9, 80, // Opcode: CXR +/* 4309 */ MCD_OPC_FilterValue, 112, 11, 0, 0, // Skip to: 4325 +/* 4314 */ MCD_OPC_CheckField, 8, 8, 0, 74, 25, 0, // Skip to: 10795 +/* 4321 */ MCD_OPC_Decode, 204, 13, 11, // Opcode: LPDFR +/* 4325 */ MCD_OPC_FilterValue, 113, 11, 0, 0, // Skip to: 4341 +/* 4330 */ MCD_OPC_CheckField, 8, 8, 0, 58, 25, 0, // Skip to: 10795 +/* 4337 */ MCD_OPC_Decode, 249, 11, 11, // Opcode: LNDFR +/* 4341 */ MCD_OPC_FilterValue, 114, 11, 0, 0, // Skip to: 4357 +/* 4346 */ MCD_OPC_CheckField, 8, 4, 0, 42, 25, 0, // Skip to: 10795 +/* 4353 */ MCD_OPC_Decode, 217, 8, 96, // Opcode: CPSDRdd +/* 4357 */ MCD_OPC_FilterValue, 115, 11, 0, 0, // Skip to: 4373 +/* 4362 */ MCD_OPC_CheckField, 8, 8, 0, 26, 25, 0, // Skip to: 10795 +/* 4369 */ MCD_OPC_Decode, 152, 11, 11, // Opcode: LCDFR +/* 4373 */ MCD_OPC_FilterValue, 116, 18, 0, 0, // Skip to: 4396 +/* 4378 */ MCD_OPC_CheckField, 8, 8, 0, 10, 25, 0, // Skip to: 10795 +/* 4385 */ MCD_OPC_CheckField, 0, 4, 0, 3, 25, 0, // Skip to: 10795 +/* 4392 */ MCD_OPC_Decode, 134, 14, 97, // Opcode: LZER +/* 4396 */ MCD_OPC_FilterValue, 117, 18, 0, 0, // Skip to: 4419 +/* 4401 */ MCD_OPC_CheckField, 8, 8, 0, 243, 24, 0, // Skip to: 10795 +/* 4408 */ MCD_OPC_CheckField, 0, 4, 0, 236, 24, 0, // Skip to: 10795 +/* 4415 */ MCD_OPC_Decode, 133, 14, 98, // Opcode: LZDR +/* 4419 */ MCD_OPC_FilterValue, 118, 18, 0, 0, // Skip to: 4442 +/* 4424 */ MCD_OPC_CheckField, 8, 8, 0, 220, 24, 0, // Skip to: 10795 +/* 4431 */ MCD_OPC_CheckField, 0, 4, 0, 213, 24, 0, // Skip to: 10795 +/* 4438 */ MCD_OPC_Decode, 137, 14, 99, // Opcode: LZXR +/* 4442 */ MCD_OPC_FilterValue, 119, 11, 0, 0, // Skip to: 4458 +/* 4447 */ MCD_OPC_CheckField, 8, 8, 0, 197, 24, 0, // Skip to: 10795 +/* 4454 */ MCD_OPC_Decode, 128, 10, 16, // Opcode: FIER +/* 4458 */ MCD_OPC_FilterValue, 127, 11, 0, 0, // Skip to: 4474 +/* 4463 */ MCD_OPC_CheckField, 8, 8, 0, 181, 24, 0, // Skip to: 10795 +/* 4470 */ MCD_OPC_Decode, 252, 9, 11, // Opcode: FIDR +/* 4474 */ MCD_OPC_FilterValue, 132, 1, 18, 0, 0, // Skip to: 4498 +/* 4480 */ MCD_OPC_CheckField, 8, 8, 0, 164, 24, 0, // Skip to: 10795 +/* 4487 */ MCD_OPC_CheckField, 0, 4, 0, 157, 24, 0, // Skip to: 10795 +/* 4494 */ MCD_OPC_Decode, 172, 16, 1, // Opcode: SFPC +/* 4498 */ MCD_OPC_FilterValue, 133, 1, 18, 0, 0, // Skip to: 4522 +/* 4504 */ MCD_OPC_CheckField, 8, 8, 0, 140, 24, 0, // Skip to: 10795 +/* 4511 */ MCD_OPC_CheckField, 0, 4, 0, 133, 24, 0, // Skip to: 10795 +/* 4518 */ MCD_OPC_Decode, 171, 16, 1, // Opcode: SFASR +/* 4522 */ MCD_OPC_FilterValue, 140, 1, 18, 0, 0, // Skip to: 4546 +/* 4528 */ MCD_OPC_CheckField, 8, 8, 0, 116, 24, 0, // Skip to: 10795 +/* 4535 */ MCD_OPC_CheckField, 0, 4, 0, 109, 24, 0, // Skip to: 10795 +/* 4542 */ MCD_OPC_Decode, 234, 9, 1, // Opcode: EFPC +/* 4546 */ MCD_OPC_FilterValue, 144, 1, 9, 0, 0, // Skip to: 4561 +/* 4552 */ MCD_OPC_CheckPredicate, 2, 94, 24, 0, // Skip to: 10795 +/* 4557 */ MCD_OPC_Decode, 183, 5, 100, // Opcode: CELFBR +/* 4561 */ MCD_OPC_FilterValue, 145, 1, 9, 0, 0, // Skip to: 4576 +/* 4567 */ MCD_OPC_CheckPredicate, 2, 79, 24, 0, // Skip to: 10795 +/* 4572 */ MCD_OPC_Decode, 160, 5, 101, // Opcode: CDLFBR +/* 4576 */ MCD_OPC_FilterValue, 146, 1, 9, 0, 0, // Skip to: 4591 +/* 4582 */ MCD_OPC_CheckPredicate, 2, 64, 24, 0, // Skip to: 10795 +/* 4587 */ MCD_OPC_Decode, 183, 9, 102, // Opcode: CXLFBR +/* 4591 */ MCD_OPC_FilterValue, 148, 1, 20, 0, 0, // Skip to: 4617 +/* 4597 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, 0, // Skip to: 4608 +/* 4604 */ MCD_OPC_Decode, 177, 5, 103, // Opcode: CEFBR +/* 4608 */ MCD_OPC_CheckPredicate, 2, 38, 24, 0, // Skip to: 10795 +/* 4613 */ MCD_OPC_Decode, 178, 5, 100, // Opcode: CEFBRA +/* 4617 */ MCD_OPC_FilterValue, 149, 1, 20, 0, 0, // Skip to: 4643 +/* 4623 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, 0, // Skip to: 4634 +/* 4630 */ MCD_OPC_Decode, 151, 5, 104, // Opcode: CDFBR +/* 4634 */ MCD_OPC_CheckPredicate, 2, 12, 24, 0, // Skip to: 10795 +/* 4639 */ MCD_OPC_Decode, 152, 5, 101, // Opcode: CDFBRA +/* 4643 */ MCD_OPC_FilterValue, 150, 1, 20, 0, 0, // Skip to: 4669 +/* 4649 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, 0, // Skip to: 4660 +/* 4656 */ MCD_OPC_Decode, 174, 9, 105, // Opcode: CXFBR +/* 4660 */ MCD_OPC_CheckPredicate, 2, 242, 23, 0, // Skip to: 10795 +/* 4665 */ MCD_OPC_Decode, 175, 9, 102, // Opcode: CXFBRA +/* 4669 */ MCD_OPC_FilterValue, 152, 1, 20, 0, 0, // Skip to: 4695 +/* 4675 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 4686 +/* 4682 */ MCD_OPC_Decode, 192, 5, 106, // Opcode: CFEBR +/* 4686 */ MCD_OPC_CheckPredicate, 2, 216, 23, 0, // Skip to: 10795 +/* 4691 */ MCD_OPC_Decode, 193, 5, 107, // Opcode: CFEBRA +/* 4695 */ MCD_OPC_FilterValue, 153, 1, 20, 0, 0, // Skip to: 4721 +/* 4701 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 4712 +/* 4708 */ MCD_OPC_Decode, 188, 5, 108, // Opcode: CFDBR +/* 4712 */ MCD_OPC_CheckPredicate, 2, 190, 23, 0, // Skip to: 10795 +/* 4717 */ MCD_OPC_Decode, 189, 5, 109, // Opcode: CFDBRA +/* 4721 */ MCD_OPC_FilterValue, 154, 1, 20, 0, 0, // Skip to: 4747 +/* 4727 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 4738 +/* 4734 */ MCD_OPC_Decode, 196, 5, 110, // Opcode: CFXBR +/* 4738 */ MCD_OPC_CheckPredicate, 2, 164, 23, 0, // Skip to: 10795 +/* 4743 */ MCD_OPC_Decode, 197, 5, 111, // Opcode: CFXBRA +/* 4747 */ MCD_OPC_FilterValue, 156, 1, 9, 0, 0, // Skip to: 4762 +/* 4753 */ MCD_OPC_CheckPredicate, 2, 149, 23, 0, // Skip to: 10795 +/* 4758 */ MCD_OPC_Decode, 240, 6, 107, // Opcode: CLFEBR +/* 4762 */ MCD_OPC_FilterValue, 157, 1, 9, 0, 0, // Skip to: 4777 +/* 4768 */ MCD_OPC_CheckPredicate, 2, 134, 23, 0, // Skip to: 10795 +/* 4773 */ MCD_OPC_Decode, 238, 6, 109, // Opcode: CLFDBR +/* 4777 */ MCD_OPC_FilterValue, 158, 1, 9, 0, 0, // Skip to: 4792 +/* 4783 */ MCD_OPC_CheckPredicate, 2, 119, 23, 0, // Skip to: 10795 +/* 4788 */ MCD_OPC_Decode, 129, 7, 111, // Opcode: CLFXBR +/* 4792 */ MCD_OPC_FilterValue, 160, 1, 9, 0, 0, // Skip to: 4807 +/* 4798 */ MCD_OPC_CheckPredicate, 2, 104, 23, 0, // Skip to: 10795 +/* 4803 */ MCD_OPC_Decode, 184, 5, 112, // Opcode: CELGBR +/* 4807 */ MCD_OPC_FilterValue, 161, 1, 9, 0, 0, // Skip to: 4822 +/* 4813 */ MCD_OPC_CheckPredicate, 2, 89, 23, 0, // Skip to: 10795 +/* 4818 */ MCD_OPC_Decode, 162, 5, 113, // Opcode: CDLGBR +/* 4822 */ MCD_OPC_FilterValue, 162, 1, 9, 0, 0, // Skip to: 4837 +/* 4828 */ MCD_OPC_CheckPredicate, 2, 74, 23, 0, // Skip to: 10795 +/* 4833 */ MCD_OPC_Decode, 185, 9, 114, // Opcode: CXLGBR +/* 4837 */ MCD_OPC_FilterValue, 164, 1, 20, 0, 0, // Skip to: 4863 +/* 4843 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, 0, // Skip to: 4854 +/* 4850 */ MCD_OPC_Decode, 180, 5, 115, // Opcode: CEGBR +/* 4854 */ MCD_OPC_CheckPredicate, 2, 48, 23, 0, // Skip to: 10795 +/* 4859 */ MCD_OPC_Decode, 181, 5, 112, // Opcode: CEGBRA +/* 4863 */ MCD_OPC_FilterValue, 165, 1, 20, 0, 0, // Skip to: 4889 +/* 4869 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, 0, // Skip to: 4880 +/* 4876 */ MCD_OPC_Decode, 155, 5, 116, // Opcode: CDGBR +/* 4880 */ MCD_OPC_CheckPredicate, 2, 22, 23, 0, // Skip to: 10795 +/* 4885 */ MCD_OPC_Decode, 156, 5, 113, // Opcode: CDGBRA +/* 4889 */ MCD_OPC_FilterValue, 166, 1, 20, 0, 0, // Skip to: 4915 +/* 4895 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, 0, // Skip to: 4906 +/* 4902 */ MCD_OPC_Decode, 178, 9, 117, // Opcode: CXGBR +/* 4906 */ MCD_OPC_CheckPredicate, 2, 252, 22, 0, // Skip to: 10795 +/* 4911 */ MCD_OPC_Decode, 179, 9, 114, // Opcode: CXGBRA +/* 4915 */ MCD_OPC_FilterValue, 168, 1, 20, 0, 0, // Skip to: 4941 +/* 4921 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 4932 +/* 4928 */ MCD_OPC_Decode, 206, 5, 118, // Opcode: CGEBR +/* 4932 */ MCD_OPC_CheckPredicate, 2, 226, 22, 0, // Skip to: 10795 +/* 4937 */ MCD_OPC_Decode, 207, 5, 119, // Opcode: CGEBRA +/* 4941 */ MCD_OPC_FilterValue, 169, 1, 20, 0, 0, // Skip to: 4967 +/* 4947 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 4958 +/* 4954 */ MCD_OPC_Decode, 201, 5, 120, // Opcode: CGDBR +/* 4958 */ MCD_OPC_CheckPredicate, 2, 200, 22, 0, // Skip to: 10795 +/* 4963 */ MCD_OPC_Decode, 202, 5, 121, // Opcode: CGDBRA +/* 4967 */ MCD_OPC_FilterValue, 170, 1, 20, 0, 0, // Skip to: 4993 +/* 4973 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 4984 +/* 4980 */ MCD_OPC_Decode, 175, 6, 122, // Opcode: CGXBR +/* 4984 */ MCD_OPC_CheckPredicate, 2, 174, 22, 0, // Skip to: 10795 +/* 4989 */ MCD_OPC_Decode, 176, 6, 123, // Opcode: CGXBRA +/* 4993 */ MCD_OPC_FilterValue, 172, 1, 9, 0, 0, // Skip to: 5008 +/* 4999 */ MCD_OPC_CheckPredicate, 2, 159, 22, 0, // Skip to: 10795 +/* 5004 */ MCD_OPC_Decode, 134, 7, 119, // Opcode: CLGEBR +/* 5008 */ MCD_OPC_FilterValue, 173, 1, 9, 0, 0, // Skip to: 5023 +/* 5014 */ MCD_OPC_CheckPredicate, 2, 144, 22, 0, // Skip to: 10795 +/* 5019 */ MCD_OPC_Decode, 132, 7, 121, // Opcode: CLGDBR +/* 5023 */ MCD_OPC_FilterValue, 174, 1, 9, 0, 0, // Skip to: 5038 +/* 5029 */ MCD_OPC_CheckPredicate, 2, 129, 22, 0, // Skip to: 10795 +/* 5034 */ MCD_OPC_Decode, 241, 7, 123, // Opcode: CLGXBR +/* 5038 */ MCD_OPC_FilterValue, 180, 1, 11, 0, 0, // Skip to: 5055 +/* 5044 */ MCD_OPC_CheckField, 8, 8, 0, 112, 22, 0, // Skip to: 10795 +/* 5051 */ MCD_OPC_Decode, 179, 5, 103, // Opcode: CEFR +/* 5055 */ MCD_OPC_FilterValue, 181, 1, 11, 0, 0, // Skip to: 5072 +/* 5061 */ MCD_OPC_CheckField, 8, 8, 0, 95, 22, 0, // Skip to: 10795 +/* 5068 */ MCD_OPC_Decode, 153, 5, 104, // Opcode: CDFR +/* 5072 */ MCD_OPC_FilterValue, 182, 1, 11, 0, 0, // Skip to: 5089 +/* 5078 */ MCD_OPC_CheckField, 8, 8, 0, 78, 22, 0, // Skip to: 10795 +/* 5085 */ MCD_OPC_Decode, 176, 9, 105, // Opcode: CXFR +/* 5089 */ MCD_OPC_FilterValue, 184, 1, 11, 0, 0, // Skip to: 5106 +/* 5095 */ MCD_OPC_CheckField, 8, 4, 0, 61, 22, 0, // Skip to: 10795 +/* 5102 */ MCD_OPC_Decode, 194, 5, 106, // Opcode: CFER +/* 5106 */ MCD_OPC_FilterValue, 185, 1, 11, 0, 0, // Skip to: 5123 +/* 5112 */ MCD_OPC_CheckField, 8, 4, 0, 44, 22, 0, // Skip to: 10795 +/* 5119 */ MCD_OPC_Decode, 190, 5, 108, // Opcode: CFDR +/* 5123 */ MCD_OPC_FilterValue, 186, 1, 11, 0, 0, // Skip to: 5140 +/* 5129 */ MCD_OPC_CheckField, 8, 4, 0, 27, 22, 0, // Skip to: 10795 +/* 5136 */ MCD_OPC_Decode, 198, 5, 110, // Opcode: CFXR +/* 5140 */ MCD_OPC_FilterValue, 193, 1, 11, 0, 0, // Skip to: 5157 +/* 5146 */ MCD_OPC_CheckField, 8, 8, 0, 10, 22, 0, // Skip to: 10795 +/* 5153 */ MCD_OPC_Decode, 171, 11, 116, // Opcode: LDGR +/* 5157 */ MCD_OPC_FilterValue, 196, 1, 11, 0, 0, // Skip to: 5174 +/* 5163 */ MCD_OPC_CheckField, 8, 8, 0, 249, 21, 0, // Skip to: 10795 +/* 5170 */ MCD_OPC_Decode, 182, 5, 115, // Opcode: CEGR +/* 5174 */ MCD_OPC_FilterValue, 197, 1, 11, 0, 0, // Skip to: 5191 +/* 5180 */ MCD_OPC_CheckField, 8, 8, 0, 232, 21, 0, // Skip to: 10795 +/* 5187 */ MCD_OPC_Decode, 157, 5, 116, // Opcode: CDGR +/* 5191 */ MCD_OPC_FilterValue, 198, 1, 11, 0, 0, // Skip to: 5208 +/* 5197 */ MCD_OPC_CheckField, 8, 8, 0, 215, 21, 0, // Skip to: 10795 +/* 5204 */ MCD_OPC_Decode, 180, 9, 117, // Opcode: CXGR +/* 5208 */ MCD_OPC_FilterValue, 200, 1, 11, 0, 0, // Skip to: 5225 +/* 5214 */ MCD_OPC_CheckField, 8, 4, 0, 198, 21, 0, // Skip to: 10795 +/* 5221 */ MCD_OPC_Decode, 208, 5, 118, // Opcode: CGER +/* 5225 */ MCD_OPC_FilterValue, 201, 1, 11, 0, 0, // Skip to: 5242 +/* 5231 */ MCD_OPC_CheckField, 8, 4, 0, 181, 21, 0, // Skip to: 10795 +/* 5238 */ MCD_OPC_Decode, 203, 5, 120, // Opcode: CGDR +/* 5242 */ MCD_OPC_FilterValue, 202, 1, 11, 0, 0, // Skip to: 5259 +/* 5248 */ MCD_OPC_CheckField, 8, 4, 0, 164, 21, 0, // Skip to: 10795 +/* 5255 */ MCD_OPC_Decode, 177, 6, 122, // Opcode: CGXR +/* 5259 */ MCD_OPC_FilterValue, 205, 1, 11, 0, 0, // Skip to: 5276 +/* 5265 */ MCD_OPC_CheckField, 8, 8, 0, 147, 21, 0, // Skip to: 10795 +/* 5272 */ MCD_OPC_Decode, 197, 11, 124, // Opcode: LGDR +/* 5276 */ MCD_OPC_FilterValue, 208, 1, 20, 0, 0, // Skip to: 5302 +/* 5282 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 5293 +/* 5289 */ MCD_OPC_Decode, 162, 14, 96, // Opcode: MDTR +/* 5293 */ MCD_OPC_CheckPredicate, 2, 121, 21, 0, // Skip to: 10795 +/* 5298 */ MCD_OPC_Decode, 163, 14, 125, // Opcode: MDTRA +/* 5302 */ MCD_OPC_FilterValue, 209, 1, 20, 0, 0, // Skip to: 5328 +/* 5308 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 5319 +/* 5315 */ MCD_OPC_Decode, 201, 9, 96, // Opcode: DDTR +/* 5319 */ MCD_OPC_CheckPredicate, 2, 95, 21, 0, // Skip to: 10795 +/* 5324 */ MCD_OPC_Decode, 202, 9, 125, // Opcode: DDTRA +/* 5328 */ MCD_OPC_FilterValue, 210, 1, 20, 0, 0, // Skip to: 5354 +/* 5334 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 5345 +/* 5341 */ MCD_OPC_Decode, 242, 3, 96, // Opcode: ADTR +/* 5345 */ MCD_OPC_CheckPredicate, 2, 69, 21, 0, // Skip to: 10795 +/* 5350 */ MCD_OPC_Decode, 243, 3, 125, // Opcode: ADTRA +/* 5354 */ MCD_OPC_FilterValue, 211, 1, 20, 0, 0, // Skip to: 5380 +/* 5360 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 5371 +/* 5367 */ MCD_OPC_Decode, 227, 15, 96, // Opcode: SDTR +/* 5371 */ MCD_OPC_CheckPredicate, 2, 43, 21, 0, // Skip to: 10795 +/* 5376 */ MCD_OPC_Decode, 228, 15, 125, // Opcode: SDTRA +/* 5380 */ MCD_OPC_FilterValue, 212, 1, 11, 0, 0, // Skip to: 5397 +/* 5386 */ MCD_OPC_CheckField, 12, 4, 0, 26, 21, 0, // Skip to: 10795 +/* 5393 */ MCD_OPC_Decode, 170, 11, 126, // Opcode: LDETR +/* 5397 */ MCD_OPC_FilterValue, 213, 1, 4, 0, 0, // Skip to: 5407 +/* 5403 */ MCD_OPC_Decode, 183, 11, 85, // Opcode: LEDTR +/* 5407 */ MCD_OPC_FilterValue, 214, 1, 11, 0, 0, // Skip to: 5424 +/* 5413 */ MCD_OPC_CheckField, 8, 8, 0, 255, 20, 0, // Skip to: 10795 +/* 5420 */ MCD_OPC_Decode, 237, 13, 11, // Opcode: LTDTR +/* 5424 */ MCD_OPC_FilterValue, 215, 1, 4, 0, 0, // Skip to: 5434 +/* 5430 */ MCD_OPC_Decode, 253, 9, 94, // Opcode: FIDTR +/* 5434 */ MCD_OPC_FilterValue, 216, 1, 21, 0, 0, // Skip to: 5461 +/* 5440 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 5451 +/* 5447 */ MCD_OPC_Decode, 235, 14, 127, // Opcode: MXTR +/* 5451 */ MCD_OPC_CheckPredicate, 2, 219, 20, 0, // Skip to: 10795 +/* 5456 */ MCD_OPC_Decode, 236, 14, 128, 1, // Opcode: MXTRA +/* 5461 */ MCD_OPC_FilterValue, 217, 1, 21, 0, 0, // Skip to: 5488 +/* 5467 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 5478 +/* 5474 */ MCD_OPC_Decode, 223, 9, 127, // Opcode: DXTR +/* 5478 */ MCD_OPC_CheckPredicate, 2, 192, 20, 0, // Skip to: 10795 +/* 5483 */ MCD_OPC_Decode, 224, 9, 128, 1, // Opcode: DXTRA +/* 5488 */ MCD_OPC_FilterValue, 218, 1, 21, 0, 0, // Skip to: 5515 +/* 5494 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 5505 +/* 5501 */ MCD_OPC_Decode, 171, 4, 127, // Opcode: AXTR +/* 5505 */ MCD_OPC_CheckPredicate, 2, 165, 20, 0, // Skip to: 10795 +/* 5510 */ MCD_OPC_Decode, 172, 4, 128, 1, // Opcode: AXTRA +/* 5515 */ MCD_OPC_FilterValue, 219, 1, 21, 0, 0, // Skip to: 5542 +/* 5521 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 5532 +/* 5528 */ MCD_OPC_Decode, 253, 17, 127, // Opcode: SXTR +/* 5532 */ MCD_OPC_CheckPredicate, 2, 138, 20, 0, // Skip to: 10795 +/* 5537 */ MCD_OPC_Decode, 254, 17, 128, 1, // Opcode: SXTRA +/* 5542 */ MCD_OPC_FilterValue, 220, 1, 12, 0, 0, // Skip to: 5560 +/* 5548 */ MCD_OPC_CheckField, 12, 4, 0, 120, 20, 0, // Skip to: 10795 +/* 5555 */ MCD_OPC_Decode, 254, 13, 129, 1, // Opcode: LXDTR +/* 5560 */ MCD_OPC_FilterValue, 221, 1, 4, 0, 0, // Skip to: 5570 +/* 5566 */ MCD_OPC_Decode, 177, 11, 86, // Opcode: LDXTR +/* 5570 */ MCD_OPC_FilterValue, 222, 1, 11, 0, 0, // Skip to: 5587 +/* 5576 */ MCD_OPC_CheckField, 8, 8, 0, 92, 20, 0, // Skip to: 10795 +/* 5583 */ MCD_OPC_Decode, 247, 13, 80, // Opcode: LTXTR +/* 5587 */ MCD_OPC_FilterValue, 223, 1, 4, 0, 0, // Skip to: 5597 +/* 5593 */ MCD_OPC_Decode, 132, 10, 86, // Opcode: FIXTR +/* 5597 */ MCD_OPC_FilterValue, 224, 1, 11, 0, 0, // Skip to: 5614 +/* 5603 */ MCD_OPC_CheckField, 8, 8, 0, 65, 20, 0, // Skip to: 10795 +/* 5610 */ MCD_OPC_Decode, 239, 10, 11, // Opcode: KDTR +/* 5614 */ MCD_OPC_FilterValue, 225, 1, 20, 0, 0, // Skip to: 5640 +/* 5620 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 5631 +/* 5627 */ MCD_OPC_Decode, 204, 5, 120, // Opcode: CGDTR +/* 5631 */ MCD_OPC_CheckPredicate, 2, 39, 20, 0, // Skip to: 10795 +/* 5636 */ MCD_OPC_Decode, 205, 5, 121, // Opcode: CGDTRA +/* 5640 */ MCD_OPC_FilterValue, 226, 1, 11, 0, 0, // Skip to: 5657 +/* 5646 */ MCD_OPC_CheckField, 8, 8, 0, 22, 20, 0, // Skip to: 10795 +/* 5653 */ MCD_OPC_Decode, 160, 9, 124, // Opcode: CUDTR +/* 5657 */ MCD_OPC_FilterValue, 227, 1, 12, 0, 0, // Skip to: 5675 +/* 5663 */ MCD_OPC_CheckField, 12, 4, 0, 5, 20, 0, // Skip to: 10795 +/* 5670 */ MCD_OPC_Decode, 143, 9, 130, 1, // Opcode: CSDTR +/* 5675 */ MCD_OPC_FilterValue, 228, 1, 11, 0, 0, // Skip to: 5692 +/* 5681 */ MCD_OPC_CheckField, 8, 8, 0, 243, 19, 0, // Skip to: 10795 +/* 5688 */ MCD_OPC_Decode, 170, 5, 11, // Opcode: CDTR +/* 5692 */ MCD_OPC_FilterValue, 229, 1, 11, 0, 0, // Skip to: 5709 +/* 5698 */ MCD_OPC_CheckField, 8, 8, 0, 226, 19, 0, // Skip to: 10795 +/* 5705 */ MCD_OPC_Decode, 232, 9, 11, // Opcode: EEDTR +/* 5709 */ MCD_OPC_FilterValue, 231, 1, 11, 0, 0, // Skip to: 5726 +/* 5715 */ MCD_OPC_CheckField, 8, 8, 0, 209, 19, 0, // Skip to: 10795 +/* 5722 */ MCD_OPC_Decode, 243, 9, 11, // Opcode: ESDTR +/* 5726 */ MCD_OPC_FilterValue, 232, 1, 11, 0, 0, // Skip to: 5743 +/* 5732 */ MCD_OPC_CheckField, 8, 8, 0, 192, 19, 0, // Skip to: 10795 +/* 5739 */ MCD_OPC_Decode, 252, 10, 80, // Opcode: KXTR +/* 5743 */ MCD_OPC_FilterValue, 233, 1, 20, 0, 0, // Skip to: 5769 +/* 5749 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 5760 +/* 5756 */ MCD_OPC_Decode, 178, 6, 122, // Opcode: CGXTR +/* 5760 */ MCD_OPC_CheckPredicate, 2, 166, 19, 0, // Skip to: 10795 +/* 5765 */ MCD_OPC_Decode, 179, 6, 123, // Opcode: CGXTRA +/* 5769 */ MCD_OPC_FilterValue, 234, 1, 12, 0, 0, // Skip to: 5787 +/* 5775 */ MCD_OPC_CheckField, 8, 8, 0, 149, 19, 0, // Skip to: 10795 +/* 5782 */ MCD_OPC_Decode, 166, 9, 131, 1, // Opcode: CUXTR +/* 5787 */ MCD_OPC_FilterValue, 235, 1, 12, 0, 0, // Skip to: 5805 +/* 5793 */ MCD_OPC_CheckField, 12, 4, 0, 131, 19, 0, // Skip to: 10795 +/* 5800 */ MCD_OPC_Decode, 148, 9, 132, 1, // Opcode: CSXTR +/* 5805 */ MCD_OPC_FilterValue, 236, 1, 11, 0, 0, // Skip to: 5822 +/* 5811 */ MCD_OPC_CheckField, 8, 8, 0, 113, 19, 0, // Skip to: 10795 +/* 5818 */ MCD_OPC_Decode, 190, 9, 80, // Opcode: CXTR +/* 5822 */ MCD_OPC_FilterValue, 237, 1, 11, 0, 0, // Skip to: 5839 +/* 5828 */ MCD_OPC_CheckField, 8, 8, 0, 96, 19, 0, // Skip to: 10795 +/* 5835 */ MCD_OPC_Decode, 233, 9, 80, // Opcode: EEXTR +/* 5839 */ MCD_OPC_FilterValue, 239, 1, 11, 0, 0, // Skip to: 5856 +/* 5845 */ MCD_OPC_CheckField, 8, 8, 0, 79, 19, 0, // Skip to: 10795 +/* 5852 */ MCD_OPC_Decode, 246, 9, 80, // Opcode: ESXTR +/* 5856 */ MCD_OPC_FilterValue, 241, 1, 20, 0, 0, // Skip to: 5882 +/* 5862 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, 0, // Skip to: 5873 +/* 5869 */ MCD_OPC_Decode, 158, 5, 116, // Opcode: CDGTR +/* 5873 */ MCD_OPC_CheckPredicate, 2, 53, 19, 0, // Skip to: 10795 +/* 5878 */ MCD_OPC_Decode, 159, 5, 113, // Opcode: CDGTRA +/* 5882 */ MCD_OPC_FilterValue, 242, 1, 11, 0, 0, // Skip to: 5899 +/* 5888 */ MCD_OPC_CheckField, 8, 8, 0, 36, 19, 0, // Skip to: 10795 +/* 5895 */ MCD_OPC_Decode, 171, 5, 116, // Opcode: CDUTR +/* 5899 */ MCD_OPC_FilterValue, 243, 1, 11, 0, 0, // Skip to: 5916 +/* 5905 */ MCD_OPC_CheckField, 8, 8, 0, 19, 19, 0, // Skip to: 10795 +/* 5912 */ MCD_OPC_Decode, 168, 5, 116, // Opcode: CDSTR +/* 5916 */ MCD_OPC_FilterValue, 244, 1, 11, 0, 0, // Skip to: 5933 +/* 5922 */ MCD_OPC_CheckField, 8, 8, 0, 2, 19, 0, // Skip to: 10795 +/* 5929 */ MCD_OPC_Decode, 176, 5, 11, // Opcode: CEDTR +/* 5933 */ MCD_OPC_FilterValue, 245, 1, 4, 0, 0, // Skip to: 5943 +/* 5939 */ MCD_OPC_Decode, 186, 15, 93, // Opcode: QADTR +/* 5943 */ MCD_OPC_FilterValue, 246, 1, 11, 0, 0, // Skip to: 5960 +/* 5949 */ MCD_OPC_CheckField, 8, 4, 0, 231, 18, 0, // Skip to: 10795 +/* 5956 */ MCD_OPC_Decode, 147, 10, 96, // Opcode: IEDTR +/* 5960 */ MCD_OPC_FilterValue, 247, 1, 4, 0, 0, // Skip to: 5970 +/* 5966 */ MCD_OPC_Decode, 206, 15, 93, // Opcode: RRDTR +/* 5970 */ MCD_OPC_FilterValue, 249, 1, 20, 0, 0, // Skip to: 5996 +/* 5976 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, 0, // Skip to: 5987 +/* 5983 */ MCD_OPC_Decode, 181, 9, 117, // Opcode: CXGTR +/* 5987 */ MCD_OPC_CheckPredicate, 2, 195, 18, 0, // Skip to: 10795 +/* 5992 */ MCD_OPC_Decode, 182, 9, 114, // Opcode: CXGTRA +/* 5996 */ MCD_OPC_FilterValue, 250, 1, 12, 0, 0, // Skip to: 6014 +/* 6002 */ MCD_OPC_CheckField, 8, 8, 0, 178, 18, 0, // Skip to: 10795 +/* 6009 */ MCD_OPC_Decode, 191, 9, 133, 1, // Opcode: CXUTR +/* 6014 */ MCD_OPC_FilterValue, 251, 1, 12, 0, 0, // Skip to: 6032 +/* 6020 */ MCD_OPC_CheckField, 8, 8, 0, 160, 18, 0, // Skip to: 10795 +/* 6027 */ MCD_OPC_Decode, 189, 9, 133, 1, // Opcode: CXSTR +/* 6032 */ MCD_OPC_FilterValue, 252, 1, 11, 0, 0, // Skip to: 6049 +/* 6038 */ MCD_OPC_CheckField, 8, 8, 0, 142, 18, 0, // Skip to: 10795 +/* 6045 */ MCD_OPC_Decode, 186, 5, 80, // Opcode: CEXTR +/* 6049 */ MCD_OPC_FilterValue, 253, 1, 5, 0, 0, // Skip to: 6060 +/* 6055 */ MCD_OPC_Decode, 187, 15, 134, 1, // Opcode: QAXTR +/* 6060 */ MCD_OPC_FilterValue, 254, 1, 11, 0, 0, // Skip to: 6077 +/* 6066 */ MCD_OPC_CheckField, 8, 4, 0, 114, 18, 0, // Skip to: 10795 +/* 6073 */ MCD_OPC_Decode, 148, 10, 127, // Opcode: IEXTR +/* 6077 */ MCD_OPC_FilterValue, 255, 1, 104, 18, 0, // Skip to: 10795 +/* 6083 */ MCD_OPC_Decode, 207, 15, 134, 1, // Opcode: RRXTR +/* 6088 */ MCD_OPC_FilterValue, 182, 1, 5, 0, 0, // Skip to: 6099 +/* 6094 */ MCD_OPC_Decode, 143, 17, 135, 1, // Opcode: STCTL +/* 6099 */ MCD_OPC_FilterValue, 183, 1, 5, 0, 0, // Skip to: 6110 +/* 6105 */ MCD_OPC_Decode, 160, 11, 135, 1, // Opcode: LCTL +/* 6110 */ MCD_OPC_FilterValue, 185, 1, 17, 18, 0, // Skip to: 10741 +/* 6116 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 6119 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 6135 +/* 6124 */ MCD_OPC_CheckField, 8, 8, 0, 56, 18, 0, // Skip to: 10795 +/* 6131 */ MCD_OPC_Decode, 211, 13, 62, // Opcode: LPGR +/* 6135 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 6151 +/* 6140 */ MCD_OPC_CheckField, 8, 8, 0, 40, 18, 0, // Skip to: 10795 +/* 6147 */ MCD_OPC_Decode, 255, 11, 62, // Opcode: LNGR +/* 6151 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 6167 +/* 6156 */ MCD_OPC_CheckField, 8, 8, 0, 24, 18, 0, // Skip to: 10795 +/* 6163 */ MCD_OPC_Decode, 243, 13, 62, // Opcode: LTGR +/* 6167 */ MCD_OPC_FilterValue, 3, 11, 0, 0, // Skip to: 6183 +/* 6172 */ MCD_OPC_CheckField, 8, 8, 0, 8, 18, 0, // Skip to: 10795 +/* 6179 */ MCD_OPC_Decode, 158, 11, 62, // Opcode: LCGR +/* 6183 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 6199 +/* 6188 */ MCD_OPC_CheckField, 8, 8, 0, 248, 17, 0, // Skip to: 10795 +/* 6195 */ MCD_OPC_Decode, 207, 11, 62, // Opcode: LGR +/* 6199 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 6215 +/* 6204 */ MCD_OPC_CheckField, 8, 8, 0, 232, 17, 0, // Skip to: 10795 +/* 6211 */ MCD_OPC_Decode, 249, 13, 62, // Opcode: LURAG +/* 6215 */ MCD_OPC_FilterValue, 6, 11, 0, 0, // Skip to: 6231 +/* 6220 */ MCD_OPC_CheckField, 8, 8, 0, 216, 17, 0, // Skip to: 10795 +/* 6227 */ MCD_OPC_Decode, 196, 11, 62, // Opcode: LGBR +/* 6231 */ MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 6247 +/* 6236 */ MCD_OPC_CheckField, 8, 8, 0, 200, 17, 0, // Skip to: 10795 +/* 6243 */ MCD_OPC_Decode, 205, 11, 62, // Opcode: LGHR +/* 6247 */ MCD_OPC_FilterValue, 8, 12, 0, 0, // Skip to: 6264 +/* 6252 */ MCD_OPC_CheckField, 8, 8, 0, 184, 17, 0, // Skip to: 10795 +/* 6259 */ MCD_OPC_Decode, 128, 4, 136, 1, // Opcode: AGR +/* 6264 */ MCD_OPC_FilterValue, 9, 12, 0, 0, // Skip to: 6281 +/* 6269 */ MCD_OPC_CheckField, 8, 8, 0, 167, 17, 0, // Skip to: 10795 +/* 6276 */ MCD_OPC_Decode, 177, 16, 136, 1, // Opcode: SGR +/* 6281 */ MCD_OPC_FilterValue, 10, 12, 0, 0, // Skip to: 6298 +/* 6286 */ MCD_OPC_CheckField, 8, 8, 0, 150, 17, 0, // Skip to: 10795 +/* 6293 */ MCD_OPC_Decode, 149, 4, 136, 1, // Opcode: ALGR +/* 6298 */ MCD_OPC_FilterValue, 11, 12, 0, 0, // Skip to: 6315 +/* 6303 */ MCD_OPC_CheckField, 8, 8, 0, 133, 17, 0, // Skip to: 10795 +/* 6310 */ MCD_OPC_Decode, 202, 16, 136, 1, // Opcode: SLGR +/* 6315 */ MCD_OPC_FilterValue, 12, 12, 0, 0, // Skip to: 6332 +/* 6320 */ MCD_OPC_CheckField, 8, 8, 0, 116, 17, 0, // Skip to: 10795 +/* 6327 */ MCD_OPC_Decode, 201, 14, 136, 1, // Opcode: MSGR +/* 6332 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 6348 +/* 6337 */ MCD_OPC_CheckField, 8, 8, 0, 99, 17, 0, // Skip to: 10795 +/* 6344 */ MCD_OPC_Decode, 220, 9, 69, // Opcode: DSGR +/* 6348 */ MCD_OPC_FilterValue, 14, 11, 0, 0, // Skip to: 6364 +/* 6353 */ MCD_OPC_CheckField, 8, 8, 0, 83, 17, 0, // Skip to: 10795 +/* 6360 */ MCD_OPC_Decode, 240, 9, 62, // Opcode: EREGG +/* 6364 */ MCD_OPC_FilterValue, 15, 11, 0, 0, // Skip to: 6380 +/* 6369 */ MCD_OPC_CheckField, 8, 8, 0, 67, 17, 0, // Skip to: 10795 +/* 6376 */ MCD_OPC_Decode, 230, 13, 62, // Opcode: LRVGR +/* 6380 */ MCD_OPC_FilterValue, 16, 11, 0, 0, // Skip to: 6396 +/* 6385 */ MCD_OPC_CheckField, 8, 8, 0, 51, 17, 0, // Skip to: 10795 +/* 6392 */ MCD_OPC_Decode, 210, 13, 57, // Opcode: LPGFR +/* 6396 */ MCD_OPC_FilterValue, 17, 11, 0, 0, // Skip to: 6412 +/* 6401 */ MCD_OPC_CheckField, 8, 8, 0, 35, 17, 0, // Skip to: 10795 +/* 6408 */ MCD_OPC_Decode, 254, 11, 57, // Opcode: LNGFR +/* 6412 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 6428 +/* 6417 */ MCD_OPC_CheckField, 8, 8, 0, 19, 17, 0, // Skip to: 10795 +/* 6424 */ MCD_OPC_Decode, 242, 13, 57, // Opcode: LTGFR +/* 6428 */ MCD_OPC_FilterValue, 19, 11, 0, 0, // Skip to: 6444 +/* 6433 */ MCD_OPC_CheckField, 8, 8, 0, 3, 17, 0, // Skip to: 10795 +/* 6440 */ MCD_OPC_Decode, 157, 11, 57, // Opcode: LCGFR +/* 6444 */ MCD_OPC_FilterValue, 20, 11, 0, 0, // Skip to: 6460 +/* 6449 */ MCD_OPC_CheckField, 8, 8, 0, 243, 16, 0, // Skip to: 10795 +/* 6456 */ MCD_OPC_Decode, 200, 11, 57, // Opcode: LGFR +/* 6460 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 6476 +/* 6465 */ MCD_OPC_CheckField, 8, 8, 0, 227, 16, 0, // Skip to: 10795 +/* 6472 */ MCD_OPC_Decode, 223, 11, 57, // Opcode: LLGFR +/* 6476 */ MCD_OPC_FilterValue, 23, 11, 0, 0, // Skip to: 6492 +/* 6481 */ MCD_OPC_CheckField, 8, 8, 0, 211, 16, 0, // Skip to: 10795 +/* 6488 */ MCD_OPC_Decode, 231, 11, 62, // Opcode: LLGTR +/* 6492 */ MCD_OPC_FilterValue, 24, 12, 0, 0, // Skip to: 6509 +/* 6497 */ MCD_OPC_CheckField, 8, 8, 0, 195, 16, 0, // Skip to: 10795 +/* 6504 */ MCD_OPC_Decode, 252, 3, 137, 1, // Opcode: AGFR +/* 6509 */ MCD_OPC_FilterValue, 25, 12, 0, 0, // Skip to: 6526 +/* 6514 */ MCD_OPC_CheckField, 8, 8, 0, 178, 16, 0, // Skip to: 10795 +/* 6521 */ MCD_OPC_Decode, 175, 16, 137, 1, // Opcode: SGFR +/* 6526 */ MCD_OPC_FilterValue, 26, 12, 0, 0, // Skip to: 6543 +/* 6531 */ MCD_OPC_CheckField, 8, 8, 0, 161, 16, 0, // Skip to: 10795 +/* 6538 */ MCD_OPC_Decode, 147, 4, 137, 1, // Opcode: ALGFR +/* 6543 */ MCD_OPC_FilterValue, 27, 12, 0, 0, // Skip to: 6560 +/* 6548 */ MCD_OPC_CheckField, 8, 8, 0, 144, 16, 0, // Skip to: 10795 +/* 6555 */ MCD_OPC_Decode, 201, 16, 137, 1, // Opcode: SLGFR +/* 6560 */ MCD_OPC_FilterValue, 28, 12, 0, 0, // Skip to: 6577 +/* 6565 */ MCD_OPC_CheckField, 8, 8, 0, 127, 16, 0, // Skip to: 10795 +/* 6572 */ MCD_OPC_Decode, 200, 14, 137, 1, // Opcode: MSGFR +/* 6577 */ MCD_OPC_FilterValue, 29, 11, 0, 0, // Skip to: 6593 +/* 6582 */ MCD_OPC_CheckField, 8, 8, 0, 110, 16, 0, // Skip to: 10795 +/* 6589 */ MCD_OPC_Decode, 219, 9, 10, // Opcode: DSGFR +/* 6593 */ MCD_OPC_FilterValue, 30, 12, 0, 0, // Skip to: 6610 +/* 6598 */ MCD_OPC_CheckField, 8, 8, 0, 94, 16, 0, // Skip to: 10795 +/* 6605 */ MCD_OPC_Decode, 246, 10, 138, 1, // Opcode: KMAC +/* 6610 */ MCD_OPC_FilterValue, 31, 11, 0, 0, // Skip to: 6626 +/* 6615 */ MCD_OPC_CheckField, 8, 8, 0, 77, 16, 0, // Skip to: 10795 +/* 6622 */ MCD_OPC_Decode, 232, 13, 8, // Opcode: LRVR +/* 6626 */ MCD_OPC_FilterValue, 32, 11, 0, 0, // Skip to: 6642 +/* 6631 */ MCD_OPC_CheckField, 8, 8, 0, 61, 16, 0, // Skip to: 10795 +/* 6638 */ MCD_OPC_Decode, 131, 6, 62, // Opcode: CGR +/* 6642 */ MCD_OPC_FilterValue, 33, 11, 0, 0, // Skip to: 6658 +/* 6647 */ MCD_OPC_CheckField, 8, 8, 0, 45, 16, 0, // Skip to: 10795 +/* 6654 */ MCD_OPC_Decode, 183, 7, 62, // Opcode: CLGR +/* 6658 */ MCD_OPC_FilterValue, 37, 11, 0, 0, // Skip to: 6674 +/* 6663 */ MCD_OPC_CheckField, 8, 8, 0, 29, 16, 0, // Skip to: 10795 +/* 6670 */ MCD_OPC_Decode, 244, 17, 62, // Opcode: STURG +/* 6674 */ MCD_OPC_FilterValue, 38, 11, 0, 0, // Skip to: 6690 +/* 6679 */ MCD_OPC_CheckField, 8, 8, 0, 13, 16, 0, // Skip to: 10795 +/* 6686 */ MCD_OPC_Decode, 148, 11, 8, // Opcode: LBR +/* 6690 */ MCD_OPC_FilterValue, 39, 11, 0, 0, // Skip to: 6706 +/* 6695 */ MCD_OPC_CheckField, 8, 8, 0, 253, 15, 0, // Skip to: 10795 +/* 6702 */ MCD_OPC_Decode, 213, 11, 8, // Opcode: LHR +/* 6706 */ MCD_OPC_FilterValue, 40, 16, 0, 0, // Skip to: 6727 +/* 6711 */ MCD_OPC_CheckPredicate, 6, 239, 15, 0, // Skip to: 10795 +/* 6716 */ MCD_OPC_CheckField, 0, 16, 0, 232, 15, 0, // Skip to: 10795 +/* 6723 */ MCD_OPC_Decode, 165, 15, 0, // Opcode: PCKMO +/* 6727 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 6749 +/* 6732 */ MCD_OPC_CheckPredicate, 7, 218, 15, 0, // Skip to: 10795 +/* 6737 */ MCD_OPC_CheckField, 8, 4, 0, 211, 15, 0, // Skip to: 10795 +/* 6744 */ MCD_OPC_Decode, 245, 10, 139, 1, // Opcode: KMA +/* 6749 */ MCD_OPC_FilterValue, 42, 16, 0, 0, // Skip to: 6770 +/* 6754 */ MCD_OPC_CheckPredicate, 8, 196, 15, 0, // Skip to: 10795 +/* 6759 */ MCD_OPC_CheckField, 8, 8, 0, 189, 15, 0, // Skip to: 10795 +/* 6766 */ MCD_OPC_Decode, 249, 10, 7, // Opcode: KMF +/* 6770 */ MCD_OPC_FilterValue, 43, 16, 0, 0, // Skip to: 6791 +/* 6775 */ MCD_OPC_CheckPredicate, 8, 175, 15, 0, // Skip to: 10795 +/* 6780 */ MCD_OPC_CheckField, 8, 8, 0, 168, 15, 0, // Skip to: 10795 +/* 6787 */ MCD_OPC_Decode, 250, 10, 7, // Opcode: KMO +/* 6791 */ MCD_OPC_FilterValue, 44, 16, 0, 0, // Skip to: 6812 +/* 6796 */ MCD_OPC_CheckPredicate, 8, 154, 15, 0, // Skip to: 10795 +/* 6801 */ MCD_OPC_CheckField, 0, 16, 0, 147, 15, 0, // Skip to: 10795 +/* 6808 */ MCD_OPC_Decode, 164, 15, 0, // Opcode: PCC +/* 6812 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 6834 +/* 6817 */ MCD_OPC_CheckPredicate, 8, 133, 15, 0, // Skip to: 10795 +/* 6822 */ MCD_OPC_CheckField, 8, 4, 0, 126, 15, 0, // Skip to: 10795 +/* 6829 */ MCD_OPC_Decode, 248, 10, 139, 1, // Opcode: KMCTR +/* 6834 */ MCD_OPC_FilterValue, 46, 11, 0, 0, // Skip to: 6850 +/* 6839 */ MCD_OPC_CheckField, 8, 8, 0, 109, 15, 0, // Skip to: 10795 +/* 6846 */ MCD_OPC_Decode, 244, 10, 7, // Opcode: KM +/* 6850 */ MCD_OPC_FilterValue, 47, 11, 0, 0, // Skip to: 6866 +/* 6855 */ MCD_OPC_CheckField, 8, 8, 0, 93, 15, 0, // Skip to: 10795 +/* 6862 */ MCD_OPC_Decode, 247, 10, 7, // Opcode: KMC +/* 6866 */ MCD_OPC_FilterValue, 48, 11, 0, 0, // Skip to: 6882 +/* 6871 */ MCD_OPC_CheckField, 8, 8, 0, 77, 15, 0, // Skip to: 10795 +/* 6878 */ MCD_OPC_Decode, 211, 5, 57, // Opcode: CGFR +/* 6882 */ MCD_OPC_FilterValue, 49, 11, 0, 0, // Skip to: 6898 +/* 6887 */ MCD_OPC_CheckField, 8, 8, 0, 61, 15, 0, // Skip to: 10795 +/* 6894 */ MCD_OPC_Decode, 137, 7, 57, // Opcode: CLGFR +/* 6898 */ MCD_OPC_FilterValue, 56, 16, 0, 0, // Skip to: 6919 +/* 6903 */ MCD_OPC_CheckPredicate, 9, 47, 15, 0, // Skip to: 10795 +/* 6908 */ MCD_OPC_CheckField, 8, 8, 0, 40, 15, 0, // Skip to: 10795 +/* 6915 */ MCD_OPC_Decode, 213, 16, 7, // Opcode: SORTL +/* 6919 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 6941 +/* 6924 */ MCD_OPC_CheckPredicate, 10, 26, 15, 0, // Skip to: 10795 +/* 6929 */ MCD_OPC_CheckField, 8, 4, 0, 19, 15, 0, // Skip to: 10795 +/* 6936 */ MCD_OPC_Decode, 207, 9, 140, 1, // Opcode: DFLTCC +/* 6941 */ MCD_OPC_FilterValue, 58, 17, 0, 0, // Skip to: 6963 +/* 6946 */ MCD_OPC_CheckPredicate, 11, 4, 15, 0, // Skip to: 10795 +/* 6951 */ MCD_OPC_CheckField, 8, 8, 0, 253, 14, 0, // Skip to: 10795 +/* 6958 */ MCD_OPC_Decode, 238, 10, 138, 1, // Opcode: KDSA +/* 6963 */ MCD_OPC_FilterValue, 59, 16, 0, 0, // Skip to: 6984 +/* 6968 */ MCD_OPC_CheckPredicate, 12, 238, 14, 0, // Skip to: 10795 +/* 6973 */ MCD_OPC_CheckField, 0, 16, 0, 231, 14, 0, // Skip to: 10795 +/* 6980 */ MCD_OPC_Decode, 132, 15, 0, // Opcode: NNPA +/* 6984 */ MCD_OPC_FilterValue, 60, 16, 0, 0, // Skip to: 7005 +/* 6989 */ MCD_OPC_CheckPredicate, 13, 217, 14, 0, // Skip to: 10795 +/* 6994 */ MCD_OPC_CheckField, 8, 8, 0, 210, 14, 0, // Skip to: 10795 +/* 7001 */ MCD_OPC_Decode, 178, 15, 7, // Opcode: PPNO +/* 7005 */ MCD_OPC_FilterValue, 62, 12, 0, 0, // Skip to: 7022 +/* 7010 */ MCD_OPC_CheckField, 8, 8, 0, 194, 14, 0, // Skip to: 10795 +/* 7017 */ MCD_OPC_Decode, 242, 10, 138, 1, // Opcode: KIMD +/* 7022 */ MCD_OPC_FilterValue, 63, 12, 0, 0, // Skip to: 7039 +/* 7027 */ MCD_OPC_CheckField, 8, 8, 0, 177, 14, 0, // Skip to: 10795 +/* 7034 */ MCD_OPC_Decode, 243, 10, 138, 1, // Opcode: KLMD +/* 7039 */ MCD_OPC_FilterValue, 65, 9, 0, 0, // Skip to: 7053 +/* 7044 */ MCD_OPC_CheckPredicate, 2, 162, 14, 0, // Skip to: 10795 +/* 7049 */ MCD_OPC_Decode, 191, 5, 109, // Opcode: CFDTR +/* 7053 */ MCD_OPC_FilterValue, 66, 9, 0, 0, // Skip to: 7067 +/* 7058 */ MCD_OPC_CheckPredicate, 2, 148, 14, 0, // Skip to: 10795 +/* 7063 */ MCD_OPC_Decode, 133, 7, 121, // Opcode: CLGDTR +/* 7067 */ MCD_OPC_FilterValue, 67, 9, 0, 0, // Skip to: 7081 +/* 7072 */ MCD_OPC_CheckPredicate, 2, 134, 14, 0, // Skip to: 10795 +/* 7077 */ MCD_OPC_Decode, 239, 6, 109, // Opcode: CLFDTR +/* 7081 */ MCD_OPC_FilterValue, 70, 12, 0, 0, // Skip to: 7098 +/* 7086 */ MCD_OPC_CheckField, 8, 8, 0, 118, 14, 0, // Skip to: 10795 +/* 7093 */ MCD_OPC_Decode, 207, 4, 136, 1, // Opcode: BCTGR +/* 7098 */ MCD_OPC_FilterValue, 73, 9, 0, 0, // Skip to: 7112 +/* 7103 */ MCD_OPC_CheckPredicate, 2, 103, 14, 0, // Skip to: 10795 +/* 7108 */ MCD_OPC_Decode, 199, 5, 111, // Opcode: CFXTR +/* 7112 */ MCD_OPC_FilterValue, 74, 9, 0, 0, // Skip to: 7126 +/* 7117 */ MCD_OPC_CheckPredicate, 2, 89, 14, 0, // Skip to: 10795 +/* 7122 */ MCD_OPC_Decode, 242, 7, 123, // Opcode: CLGXTR +/* 7126 */ MCD_OPC_FilterValue, 75, 9, 0, 0, // Skip to: 7140 +/* 7131 */ MCD_OPC_CheckPredicate, 2, 75, 14, 0, // Skip to: 10795 +/* 7136 */ MCD_OPC_Decode, 130, 7, 111, // Opcode: CLFXTR +/* 7140 */ MCD_OPC_FilterValue, 81, 9, 0, 0, // Skip to: 7154 +/* 7145 */ MCD_OPC_CheckPredicate, 2, 61, 14, 0, // Skip to: 10795 +/* 7150 */ MCD_OPC_Decode, 154, 5, 101, // Opcode: CDFTR +/* 7154 */ MCD_OPC_FilterValue, 82, 9, 0, 0, // Skip to: 7168 +/* 7159 */ MCD_OPC_CheckPredicate, 2, 47, 14, 0, // Skip to: 10795 +/* 7164 */ MCD_OPC_Decode, 163, 5, 113, // Opcode: CDLGTR +/* 7168 */ MCD_OPC_FilterValue, 83, 9, 0, 0, // Skip to: 7182 +/* 7173 */ MCD_OPC_CheckPredicate, 2, 33, 14, 0, // Skip to: 10795 +/* 7178 */ MCD_OPC_Decode, 161, 5, 101, // Opcode: CDLFTR +/* 7182 */ MCD_OPC_FilterValue, 89, 9, 0, 0, // Skip to: 7196 +/* 7187 */ MCD_OPC_CheckPredicate, 2, 19, 14, 0, // Skip to: 10795 +/* 7192 */ MCD_OPC_Decode, 177, 9, 102, // Opcode: CXFTR +/* 7196 */ MCD_OPC_FilterValue, 90, 9, 0, 0, // Skip to: 7210 +/* 7201 */ MCD_OPC_CheckPredicate, 2, 5, 14, 0, // Skip to: 10795 +/* 7206 */ MCD_OPC_Decode, 186, 9, 114, // Opcode: CXLGTR +/* 7210 */ MCD_OPC_FilterValue, 91, 9, 0, 0, // Skip to: 7224 +/* 7215 */ MCD_OPC_CheckPredicate, 2, 247, 13, 0, // Skip to: 10795 +/* 7220 */ MCD_OPC_Decode, 184, 9, 102, // Opcode: CXLFTR +/* 7224 */ MCD_OPC_FilterValue, 96, 69, 0, 0, // Skip to: 7298 +/* 7229 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 7232 */ MCD_OPC_FilterValue, 0, 230, 13, 0, // Skip to: 10795 +/* 7237 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7240 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 7249 +/* 7245 */ MCD_OPC_Decode, 164, 6, 62, // Opcode: CGRTAsmH +/* 7249 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 7258 +/* 7254 */ MCD_OPC_Decode, 166, 6, 62, // Opcode: CGRTAsmL +/* 7258 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 7267 +/* 7263 */ MCD_OPC_Decode, 168, 6, 62, // Opcode: CGRTAsmLH +/* 7267 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 7276 +/* 7272 */ MCD_OPC_Decode, 163, 6, 62, // Opcode: CGRTAsmE +/* 7276 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 7285 +/* 7281 */ MCD_OPC_Decode, 165, 6, 62, // Opcode: CGRTAsmHE +/* 7285 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 7294 +/* 7290 */ MCD_OPC_Decode, 167, 6, 62, // Opcode: CGRTAsmLE +/* 7294 */ MCD_OPC_Decode, 162, 6, 74, // Opcode: CGRTAsm +/* 7298 */ MCD_OPC_FilterValue, 97, 69, 0, 0, // Skip to: 7372 +/* 7303 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 7306 */ MCD_OPC_FilterValue, 0, 156, 13, 0, // Skip to: 10795 +/* 7311 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7314 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 7323 +/* 7319 */ MCD_OPC_Decode, 216, 7, 62, // Opcode: CLGRTAsmH +/* 7323 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 7332 +/* 7328 */ MCD_OPC_Decode, 218, 7, 62, // Opcode: CLGRTAsmL +/* 7332 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 7341 +/* 7337 */ MCD_OPC_Decode, 220, 7, 62, // Opcode: CLGRTAsmLH +/* 7341 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 7350 +/* 7346 */ MCD_OPC_Decode, 215, 7, 62, // Opcode: CLGRTAsmE +/* 7350 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 7359 +/* 7355 */ MCD_OPC_Decode, 217, 7, 62, // Opcode: CLGRTAsmHE +/* 7359 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 7368 +/* 7364 */ MCD_OPC_Decode, 219, 7, 62, // Opcode: CLGRTAsmLE +/* 7368 */ MCD_OPC_Decode, 214, 7, 74, // Opcode: CLGRTAsm +/* 7372 */ MCD_OPC_FilterValue, 100, 17, 0, 0, // Skip to: 7394 +/* 7377 */ MCD_OPC_CheckPredicate, 14, 85, 13, 0, // Skip to: 10795 +/* 7382 */ MCD_OPC_CheckField, 8, 4, 0, 78, 13, 0, // Skip to: 10795 +/* 7389 */ MCD_OPC_Decode, 131, 15, 141, 1, // Opcode: NNGRK +/* 7394 */ MCD_OPC_FilterValue, 101, 17, 0, 0, // Skip to: 7416 +/* 7399 */ MCD_OPC_CheckPredicate, 14, 63, 13, 0, // Skip to: 10795 +/* 7404 */ MCD_OPC_CheckField, 8, 4, 0, 56, 13, 0, // Skip to: 10795 +/* 7411 */ MCD_OPC_Decode, 145, 15, 141, 1, // Opcode: OCGRK +/* 7416 */ MCD_OPC_FilterValue, 102, 17, 0, 0, // Skip to: 7438 +/* 7421 */ MCD_OPC_CheckPredicate, 14, 41, 13, 0, // Skip to: 10795 +/* 7426 */ MCD_OPC_CheckField, 8, 4, 0, 34, 13, 0, // Skip to: 10795 +/* 7433 */ MCD_OPC_Decode, 134, 15, 141, 1, // Opcode: NOGRK +/* 7438 */ MCD_OPC_FilterValue, 103, 17, 0, 0, // Skip to: 7460 +/* 7443 */ MCD_OPC_CheckPredicate, 14, 19, 13, 0, // Skip to: 10795 +/* 7448 */ MCD_OPC_CheckField, 8, 4, 0, 12, 13, 0, // Skip to: 10795 +/* 7455 */ MCD_OPC_Decode, 140, 15, 141, 1, // Opcode: NXGRK +/* 7460 */ MCD_OPC_FilterValue, 114, 70, 0, 0, // Skip to: 7535 +/* 7465 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 7468 */ MCD_OPC_FilterValue, 0, 250, 12, 0, // Skip to: 10795 +/* 7473 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7476 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 7485 +/* 7481 */ MCD_OPC_Decode, 130, 9, 8, // Opcode: CRTAsmH +/* 7485 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 7494 +/* 7490 */ MCD_OPC_Decode, 132, 9, 8, // Opcode: CRTAsmL +/* 7494 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 7503 +/* 7499 */ MCD_OPC_Decode, 134, 9, 8, // Opcode: CRTAsmLH +/* 7503 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 7512 +/* 7508 */ MCD_OPC_Decode, 129, 9, 8, // Opcode: CRTAsmE +/* 7512 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 7521 +/* 7517 */ MCD_OPC_Decode, 131, 9, 8, // Opcode: CRTAsmHE +/* 7521 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 7530 +/* 7526 */ MCD_OPC_Decode, 133, 9, 8, // Opcode: CRTAsmLE +/* 7530 */ MCD_OPC_Decode, 128, 9, 142, 1, // Opcode: CRTAsm +/* 7535 */ MCD_OPC_FilterValue, 115, 70, 0, 0, // Skip to: 7610 +/* 7540 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 7543 */ MCD_OPC_FilterValue, 0, 175, 12, 0, // Skip to: 10795 +/* 7548 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7551 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 7560 +/* 7556 */ MCD_OPC_Decode, 187, 8, 8, // Opcode: CLRTAsmH +/* 7560 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 7569 +/* 7565 */ MCD_OPC_Decode, 189, 8, 8, // Opcode: CLRTAsmL +/* 7569 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 7578 +/* 7574 */ MCD_OPC_Decode, 191, 8, 8, // Opcode: CLRTAsmLH +/* 7578 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 7587 +/* 7583 */ MCD_OPC_Decode, 186, 8, 8, // Opcode: CLRTAsmE +/* 7587 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 7596 +/* 7592 */ MCD_OPC_Decode, 188, 8, 8, // Opcode: CLRTAsmHE +/* 7596 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 7605 +/* 7601 */ MCD_OPC_Decode, 190, 8, 8, // Opcode: CLRTAsmLE +/* 7605 */ MCD_OPC_Decode, 185, 8, 142, 1, // Opcode: CLRTAsm +/* 7610 */ MCD_OPC_FilterValue, 116, 17, 0, 0, // Skip to: 7632 +/* 7615 */ MCD_OPC_CheckPredicate, 14, 103, 12, 0, // Skip to: 10795 +/* 7620 */ MCD_OPC_CheckField, 8, 4, 0, 96, 12, 0, // Skip to: 10795 +/* 7627 */ MCD_OPC_Decode, 133, 15, 143, 1, // Opcode: NNRK +/* 7632 */ MCD_OPC_FilterValue, 117, 17, 0, 0, // Skip to: 7654 +/* 7637 */ MCD_OPC_CheckPredicate, 14, 81, 12, 0, // Skip to: 10795 +/* 7642 */ MCD_OPC_CheckField, 8, 4, 0, 74, 12, 0, // Skip to: 10795 +/* 7649 */ MCD_OPC_Decode, 146, 15, 143, 1, // Opcode: OCRK +/* 7654 */ MCD_OPC_FilterValue, 118, 17, 0, 0, // Skip to: 7676 +/* 7659 */ MCD_OPC_CheckPredicate, 14, 59, 12, 0, // Skip to: 10795 +/* 7664 */ MCD_OPC_CheckField, 8, 4, 0, 52, 12, 0, // Skip to: 10795 +/* 7671 */ MCD_OPC_Decode, 136, 15, 143, 1, // Opcode: NORK +/* 7676 */ MCD_OPC_FilterValue, 119, 17, 0, 0, // Skip to: 7698 +/* 7681 */ MCD_OPC_CheckPredicate, 14, 37, 12, 0, // Skip to: 10795 +/* 7686 */ MCD_OPC_CheckField, 8, 4, 0, 30, 12, 0, // Skip to: 10795 +/* 7693 */ MCD_OPC_Decode, 141, 15, 143, 1, // Opcode: NXRK +/* 7698 */ MCD_OPC_FilterValue, 128, 1, 12, 0, 0, // Skip to: 7716 +/* 7704 */ MCD_OPC_CheckField, 8, 8, 0, 12, 12, 0, // Skip to: 10795 +/* 7711 */ MCD_OPC_Decode, 248, 14, 136, 1, // Opcode: NGR +/* 7716 */ MCD_OPC_FilterValue, 129, 1, 12, 0, 0, // Skip to: 7734 +/* 7722 */ MCD_OPC_CheckField, 8, 8, 0, 250, 11, 0, // Skip to: 10795 +/* 7729 */ MCD_OPC_Decode, 148, 15, 136, 1, // Opcode: OGR +/* 7734 */ MCD_OPC_FilterValue, 130, 1, 12, 0, 0, // Skip to: 7752 +/* 7740 */ MCD_OPC_CheckField, 8, 8, 0, 232, 11, 0, // Skip to: 10795 +/* 7747 */ MCD_OPC_Decode, 150, 24, 136, 1, // Opcode: XGR +/* 7752 */ MCD_OPC_FilterValue, 131, 1, 12, 0, 0, // Skip to: 7770 +/* 7758 */ MCD_OPC_CheckField, 8, 8, 0, 214, 11, 0, // Skip to: 10795 +/* 7765 */ MCD_OPC_Decode, 133, 10, 144, 1, // Opcode: FLOGR +/* 7770 */ MCD_OPC_FilterValue, 132, 1, 11, 0, 0, // Skip to: 7787 +/* 7776 */ MCD_OPC_CheckField, 8, 8, 0, 196, 11, 0, // Skip to: 10795 +/* 7783 */ MCD_OPC_Decode, 220, 11, 62, // Opcode: LLGCR +/* 7787 */ MCD_OPC_FilterValue, 133, 1, 11, 0, 0, // Skip to: 7804 +/* 7793 */ MCD_OPC_CheckField, 8, 8, 0, 179, 11, 0, // Skip to: 10795 +/* 7800 */ MCD_OPC_Decode, 227, 11, 62, // Opcode: LLGHR +/* 7804 */ MCD_OPC_FilterValue, 134, 1, 11, 0, 0, // Skip to: 7821 +/* 7810 */ MCD_OPC_CheckField, 8, 8, 0, 162, 11, 0, // Skip to: 10795 +/* 7817 */ MCD_OPC_Decode, 180, 14, 69, // Opcode: MLGR +/* 7821 */ MCD_OPC_FilterValue, 135, 1, 11, 0, 0, // Skip to: 7838 +/* 7827 */ MCD_OPC_CheckField, 8, 8, 0, 145, 11, 0, // Skip to: 10795 +/* 7834 */ MCD_OPC_Decode, 213, 9, 69, // Opcode: DLGR +/* 7838 */ MCD_OPC_FilterValue, 136, 1, 12, 0, 0, // Skip to: 7856 +/* 7844 */ MCD_OPC_CheckField, 8, 8, 0, 128, 11, 0, // Skip to: 10795 +/* 7851 */ MCD_OPC_Decode, 141, 4, 136, 1, // Opcode: ALCGR +/* 7856 */ MCD_OPC_FilterValue, 137, 1, 12, 0, 0, // Skip to: 7874 +/* 7862 */ MCD_OPC_CheckField, 8, 8, 0, 110, 11, 0, // Skip to: 10795 +/* 7869 */ MCD_OPC_Decode, 192, 16, 136, 1, // Opcode: SLBGR +/* 7874 */ MCD_OPC_FilterValue, 138, 1, 11, 0, 0, // Skip to: 7891 +/* 7880 */ MCD_OPC_CheckField, 8, 8, 0, 92, 11, 0, // Skip to: 10795 +/* 7887 */ MCD_OPC_Decode, 146, 9, 69, // Opcode: CSPG +/* 7891 */ MCD_OPC_FilterValue, 139, 1, 27, 0, 0, // Skip to: 7924 +/* 7897 */ MCD_OPC_CheckPredicate, 15, 12, 0, 0, // Skip to: 7914 +/* 7902 */ MCD_OPC_CheckField, 8, 4, 0, 5, 0, 0, // Skip to: 7914 +/* 7909 */ MCD_OPC_Decode, 193, 15, 141, 1, // Opcode: RDPOpt +/* 7914 */ MCD_OPC_CheckPredicate, 15, 60, 11, 0, // Skip to: 10795 +/* 7919 */ MCD_OPC_Decode, 192, 15, 145, 1, // Opcode: RDP +/* 7924 */ MCD_OPC_FilterValue, 141, 1, 11, 0, 0, // Skip to: 7941 +/* 7930 */ MCD_OPC_CheckField, 8, 8, 0, 42, 11, 0, // Skip to: 10795 +/* 7937 */ MCD_OPC_Decode, 238, 9, 8, // Opcode: EPSW +/* 7941 */ MCD_OPC_FilterValue, 142, 1, 17, 0, 0, // Skip to: 7964 +/* 7947 */ MCD_OPC_CheckField, 8, 4, 0, 5, 0, 0, // Skip to: 7959 +/* 7954 */ MCD_OPC_Decode, 146, 10, 141, 1, // Opcode: IDTEOpt +/* 7959 */ MCD_OPC_Decode, 145, 10, 145, 1, // Opcode: IDTE +/* 7964 */ MCD_OPC_FilterValue, 143, 1, 27, 0, 0, // Skip to: 7997 +/* 7970 */ MCD_OPC_CheckPredicate, 16, 12, 0, 0, // Skip to: 7987 +/* 7975 */ MCD_OPC_CheckField, 8, 4, 0, 5, 0, 0, // Skip to: 7987 +/* 7982 */ MCD_OPC_Decode, 239, 8, 146, 1, // Opcode: CRDTEOpt +/* 7987 */ MCD_OPC_CheckPredicate, 16, 243, 10, 0, // Skip to: 10795 +/* 7992 */ MCD_OPC_Decode, 238, 8, 147, 1, // Opcode: CRDTE +/* 7997 */ MCD_OPC_FilterValue, 144, 1, 24, 0, 0, // Skip to: 8027 +/* 8003 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 8006 */ MCD_OPC_FilterValue, 0, 224, 10, 0, // Skip to: 10795 +/* 8011 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, 0, // Skip to: 8022 +/* 8018 */ MCD_OPC_Decode, 176, 18, 72, // Opcode: TRTTOpt +/* 8022 */ MCD_OPC_Decode, 175, 18, 148, 1, // Opcode: TRTT +/* 8027 */ MCD_OPC_FilterValue, 145, 1, 24, 0, 0, // Skip to: 8057 +/* 8033 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 8036 */ MCD_OPC_FilterValue, 0, 194, 10, 0, // Skip to: 10795 +/* 8041 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, 0, // Skip to: 8052 +/* 8048 */ MCD_OPC_Decode, 171, 18, 72, // Opcode: TRTOOpt +/* 8052 */ MCD_OPC_Decode, 170, 18, 148, 1, // Opcode: TRTO +/* 8057 */ MCD_OPC_FilterValue, 146, 1, 24, 0, 0, // Skip to: 8087 +/* 8063 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 8066 */ MCD_OPC_FilterValue, 0, 164, 10, 0, // Skip to: 10795 +/* 8071 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, 0, // Skip to: 8082 +/* 8078 */ MCD_OPC_Decode, 166, 18, 72, // Opcode: TROTOpt +/* 8082 */ MCD_OPC_Decode, 165, 18, 148, 1, // Opcode: TROT +/* 8087 */ MCD_OPC_FilterValue, 147, 1, 24, 0, 0, // Skip to: 8117 +/* 8093 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 8096 */ MCD_OPC_FilterValue, 0, 134, 10, 0, // Skip to: 10795 +/* 8101 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, 0, // Skip to: 8112 +/* 8108 */ MCD_OPC_Decode, 164, 18, 72, // Opcode: TROOOpt +/* 8112 */ MCD_OPC_Decode, 163, 18, 148, 1, // Opcode: TROO +/* 8117 */ MCD_OPC_FilterValue, 148, 1, 11, 0, 0, // Skip to: 8134 +/* 8123 */ MCD_OPC_CheckField, 8, 8, 0, 105, 10, 0, // Skip to: 10795 +/* 8130 */ MCD_OPC_Decode, 218, 11, 8, // Opcode: LLCR +/* 8134 */ MCD_OPC_FilterValue, 149, 1, 11, 0, 0, // Skip to: 8151 +/* 8140 */ MCD_OPC_CheckField, 8, 8, 0, 88, 10, 0, // Skip to: 10795 +/* 8147 */ MCD_OPC_Decode, 234, 11, 8, // Opcode: LLHR +/* 8151 */ MCD_OPC_FilterValue, 150, 1, 11, 0, 0, // Skip to: 8168 +/* 8157 */ MCD_OPC_CheckField, 8, 8, 0, 71, 10, 0, // Skip to: 10795 +/* 8164 */ MCD_OPC_Decode, 181, 14, 10, // Opcode: MLR +/* 8168 */ MCD_OPC_FilterValue, 151, 1, 11, 0, 0, // Skip to: 8185 +/* 8174 */ MCD_OPC_CheckField, 8, 8, 0, 54, 10, 0, // Skip to: 10795 +/* 8181 */ MCD_OPC_Decode, 214, 9, 10, // Opcode: DLR +/* 8185 */ MCD_OPC_FilterValue, 152, 1, 11, 0, 0, // Skip to: 8202 +/* 8191 */ MCD_OPC_CheckField, 8, 8, 0, 37, 10, 0, // Skip to: 10795 +/* 8198 */ MCD_OPC_Decode, 142, 4, 9, // Opcode: ALCR +/* 8202 */ MCD_OPC_FilterValue, 153, 1, 11, 0, 0, // Skip to: 8219 +/* 8208 */ MCD_OPC_CheckField, 8, 8, 0, 20, 10, 0, // Skip to: 10795 +/* 8215 */ MCD_OPC_Decode, 193, 16, 9, // Opcode: SLBR +/* 8219 */ MCD_OPC_FilterValue, 154, 1, 19, 0, 0, // Skip to: 8244 +/* 8225 */ MCD_OPC_CheckField, 8, 8, 0, 3, 10, 0, // Skip to: 10795 +/* 8232 */ MCD_OPC_CheckField, 0, 4, 0, 252, 9, 0, // Skip to: 10795 +/* 8239 */ MCD_OPC_Decode, 235, 9, 149, 1, // Opcode: EPAIR +/* 8244 */ MCD_OPC_FilterValue, 155, 1, 19, 0, 0, // Skip to: 8269 +/* 8250 */ MCD_OPC_CheckField, 8, 8, 0, 234, 9, 0, // Skip to: 10795 +/* 8257 */ MCD_OPC_CheckField, 0, 4, 0, 227, 9, 0, // Skip to: 10795 +/* 8264 */ MCD_OPC_Decode, 241, 9, 149, 1, // Opcode: ESAIR +/* 8269 */ MCD_OPC_FilterValue, 157, 1, 19, 0, 0, // Skip to: 8294 +/* 8275 */ MCD_OPC_CheckField, 8, 8, 0, 209, 9, 0, // Skip to: 10795 +/* 8282 */ MCD_OPC_CheckField, 0, 4, 0, 202, 9, 0, // Skip to: 10795 +/* 8289 */ MCD_OPC_Decode, 244, 9, 150, 1, // Opcode: ESEA +/* 8294 */ MCD_OPC_FilterValue, 158, 1, 11, 0, 0, // Skip to: 8311 +/* 8300 */ MCD_OPC_CheckField, 8, 8, 0, 184, 9, 0, // Skip to: 10795 +/* 8307 */ MCD_OPC_Decode, 184, 15, 62, // Opcode: PTI +/* 8311 */ MCD_OPC_FilterValue, 159, 1, 19, 0, 0, // Skip to: 8336 +/* 8317 */ MCD_OPC_CheckField, 8, 8, 0, 167, 9, 0, // Skip to: 10795 +/* 8324 */ MCD_OPC_CheckField, 0, 4, 0, 160, 9, 0, // Skip to: 10795 +/* 8331 */ MCD_OPC_Decode, 248, 16, 149, 1, // Opcode: SSAIR +/* 8336 */ MCD_OPC_FilterValue, 162, 1, 19, 0, 0, // Skip to: 8361 +/* 8342 */ MCD_OPC_CheckField, 8, 8, 0, 142, 9, 0, // Skip to: 10795 +/* 8349 */ MCD_OPC_CheckField, 0, 4, 0, 135, 9, 0, // Skip to: 10795 +/* 8356 */ MCD_OPC_Decode, 182, 15, 151, 1, // Opcode: PTF +/* 8361 */ MCD_OPC_FilterValue, 170, 1, 5, 0, 0, // Skip to: 8372 +/* 8367 */ MCD_OPC_Decode, 218, 13, 152, 1, // Opcode: LPTEA +/* 8372 */ MCD_OPC_FilterValue, 172, 1, 16, 0, 0, // Skip to: 8394 +/* 8378 */ MCD_OPC_CheckPredicate, 17, 108, 9, 0, // Skip to: 10795 +/* 8383 */ MCD_OPC_CheckField, 8, 8, 0, 101, 9, 0, // Skip to: 10795 +/* 8390 */ MCD_OPC_Decode, 160, 10, 62, // Opcode: IRBM +/* 8394 */ MCD_OPC_FilterValue, 174, 1, 16, 0, 0, // Skip to: 8416 +/* 8400 */ MCD_OPC_CheckPredicate, 18, 86, 9, 0, // Skip to: 10795 +/* 8405 */ MCD_OPC_CheckField, 8, 8, 0, 79, 9, 0, // Skip to: 10795 +/* 8412 */ MCD_OPC_Decode, 205, 15, 62, // Opcode: RRBM +/* 8416 */ MCD_OPC_FilterValue, 175, 1, 12, 0, 0, // Skip to: 8434 +/* 8422 */ MCD_OPC_CheckField, 8, 8, 0, 62, 9, 0, // Skip to: 10795 +/* 8429 */ MCD_OPC_Decode, 168, 15, 153, 1, // Opcode: PFMF +/* 8434 */ MCD_OPC_FilterValue, 176, 1, 23, 0, 0, // Skip to: 8463 +/* 8440 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 8443 */ MCD_OPC_FilterValue, 0, 43, 9, 0, // Skip to: 10795 +/* 8448 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, 0, // Skip to: 8459 +/* 8455 */ MCD_OPC_Decode, 153, 9, 7, // Opcode: CU14Opt +/* 8459 */ MCD_OPC_Decode, 152, 9, 73, // Opcode: CU14 +/* 8463 */ MCD_OPC_FilterValue, 177, 1, 23, 0, 0, // Skip to: 8492 +/* 8469 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 8472 */ MCD_OPC_FilterValue, 0, 14, 9, 0, // Skip to: 10795 +/* 8477 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, 0, // Skip to: 8488 +/* 8484 */ MCD_OPC_Decode, 157, 9, 7, // Opcode: CU24Opt +/* 8488 */ MCD_OPC_Decode, 156, 9, 73, // Opcode: CU24 +/* 8492 */ MCD_OPC_FilterValue, 178, 1, 11, 0, 0, // Skip to: 8509 +/* 8498 */ MCD_OPC_CheckField, 8, 8, 0, 242, 8, 0, // Skip to: 10795 +/* 8505 */ MCD_OPC_Decode, 158, 9, 7, // Opcode: CU41 +/* 8509 */ MCD_OPC_FilterValue, 179, 1, 11, 0, 0, // Skip to: 8526 +/* 8515 */ MCD_OPC_CheckField, 8, 8, 0, 225, 8, 0, // Skip to: 10795 +/* 8522 */ MCD_OPC_Decode, 159, 9, 7, // Opcode: CU42 +/* 8526 */ MCD_OPC_FilterValue, 189, 1, 25, 0, 0, // Skip to: 8557 +/* 8532 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 8535 */ MCD_OPC_FilterValue, 0, 207, 8, 0, // Skip to: 10795 +/* 8540 */ MCD_OPC_CheckField, 12, 4, 0, 5, 0, 0, // Skip to: 8552 +/* 8547 */ MCD_OPC_Decode, 174, 18, 154, 1, // Opcode: TRTREOpt +/* 8552 */ MCD_OPC_Decode, 173, 18, 155, 1, // Opcode: TRTRE +/* 8557 */ MCD_OPC_FilterValue, 190, 1, 11, 0, 0, // Skip to: 8574 +/* 8563 */ MCD_OPC_CheckField, 8, 8, 0, 177, 8, 0, // Skip to: 10795 +/* 8570 */ MCD_OPC_Decode, 246, 16, 70, // Opcode: SRSTU +/* 8574 */ MCD_OPC_FilterValue, 191, 1, 25, 0, 0, // Skip to: 8605 +/* 8580 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 8583 */ MCD_OPC_FilterValue, 0, 159, 8, 0, // Skip to: 10795 +/* 8588 */ MCD_OPC_CheckField, 12, 4, 0, 5, 0, 0, // Skip to: 8600 +/* 8595 */ MCD_OPC_Decode, 169, 18, 154, 1, // Opcode: TRTEOpt +/* 8600 */ MCD_OPC_Decode, 168, 18, 155, 1, // Opcode: TRTE +/* 8605 */ MCD_OPC_FilterValue, 192, 1, 223, 0, 0, // Skip to: 8834 +/* 8611 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 8614 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8629 +/* 8619 */ MCD_OPC_CheckPredicate, 14, 200, 0, 0, // Skip to: 8824 +/* 8624 */ MCD_OPC_Decode, 251, 15, 156, 1, // Opcode: SELFHRAsmO +/* 8629 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8644 +/* 8634 */ MCD_OPC_CheckPredicate, 14, 185, 0, 0, // Skip to: 8824 +/* 8639 */ MCD_OPC_Decode, 235, 15, 156, 1, // Opcode: SELFHRAsmH +/* 8644 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 8659 +/* 8649 */ MCD_OPC_CheckPredicate, 14, 170, 0, 0, // Skip to: 8824 +/* 8654 */ MCD_OPC_Decode, 245, 15, 156, 1, // Opcode: SELFHRAsmNLE +/* 8659 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 8674 +/* 8664 */ MCD_OPC_CheckPredicate, 14, 155, 0, 0, // Skip to: 8824 +/* 8669 */ MCD_OPC_Decode, 237, 15, 156, 1, // Opcode: SELFHRAsmL +/* 8674 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 8689 +/* 8679 */ MCD_OPC_CheckPredicate, 14, 140, 0, 0, // Skip to: 8824 +/* 8684 */ MCD_OPC_Decode, 243, 15, 156, 1, // Opcode: SELFHRAsmNHE +/* 8689 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 8704 +/* 8694 */ MCD_OPC_CheckPredicate, 14, 125, 0, 0, // Skip to: 8824 +/* 8699 */ MCD_OPC_Decode, 239, 15, 156, 1, // Opcode: SELFHRAsmLH +/* 8704 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 8719 +/* 8709 */ MCD_OPC_CheckPredicate, 14, 110, 0, 0, // Skip to: 8824 +/* 8714 */ MCD_OPC_Decode, 241, 15, 156, 1, // Opcode: SELFHRAsmNE +/* 8719 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 8734 +/* 8724 */ MCD_OPC_CheckPredicate, 14, 95, 0, 0, // Skip to: 8824 +/* 8729 */ MCD_OPC_Decode, 234, 15, 156, 1, // Opcode: SELFHRAsmE +/* 8734 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 8749 +/* 8739 */ MCD_OPC_CheckPredicate, 14, 80, 0, 0, // Skip to: 8824 +/* 8744 */ MCD_OPC_Decode, 246, 15, 156, 1, // Opcode: SELFHRAsmNLH +/* 8749 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 8764 +/* 8754 */ MCD_OPC_CheckPredicate, 14, 65, 0, 0, // Skip to: 8824 +/* 8759 */ MCD_OPC_Decode, 236, 15, 156, 1, // Opcode: SELFHRAsmHE +/* 8764 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 8779 +/* 8769 */ MCD_OPC_CheckPredicate, 14, 50, 0, 0, // Skip to: 8824 +/* 8774 */ MCD_OPC_Decode, 244, 15, 156, 1, // Opcode: SELFHRAsmNL +/* 8779 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 8794 +/* 8784 */ MCD_OPC_CheckPredicate, 14, 35, 0, 0, // Skip to: 8824 +/* 8789 */ MCD_OPC_Decode, 238, 15, 156, 1, // Opcode: SELFHRAsmLE +/* 8794 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 8809 +/* 8799 */ MCD_OPC_CheckPredicate, 14, 20, 0, 0, // Skip to: 8824 +/* 8804 */ MCD_OPC_Decode, 242, 15, 156, 1, // Opcode: SELFHRAsmNH +/* 8809 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 8824 +/* 8814 */ MCD_OPC_CheckPredicate, 14, 5, 0, 0, // Skip to: 8824 +/* 8819 */ MCD_OPC_Decode, 248, 15, 156, 1, // Opcode: SELFHRAsmNO +/* 8824 */ MCD_OPC_CheckPredicate, 14, 174, 7, 0, // Skip to: 10795 +/* 8829 */ MCD_OPC_Decode, 233, 15, 157, 1, // Opcode: SELFHRAsm +/* 8834 */ MCD_OPC_FilterValue, 200, 1, 17, 0, 0, // Skip to: 8857 +/* 8840 */ MCD_OPC_CheckPredicate, 19, 158, 7, 0, // Skip to: 10795 +/* 8845 */ MCD_OPC_CheckField, 8, 4, 0, 151, 7, 0, // Skip to: 10795 +/* 8852 */ MCD_OPC_Decode, 132, 4, 158, 1, // Opcode: AHHHR +/* 8857 */ MCD_OPC_FilterValue, 201, 1, 17, 0, 0, // Skip to: 8880 +/* 8863 */ MCD_OPC_CheckPredicate, 19, 135, 7, 0, // Skip to: 10795 +/* 8868 */ MCD_OPC_CheckField, 8, 4, 0, 128, 7, 0, // Skip to: 10795 +/* 8875 */ MCD_OPC_Decode, 180, 16, 158, 1, // Opcode: SHHHR +/* 8880 */ MCD_OPC_FilterValue, 202, 1, 17, 0, 0, // Skip to: 8903 +/* 8886 */ MCD_OPC_CheckPredicate, 19, 112, 7, 0, // Skip to: 10795 +/* 8891 */ MCD_OPC_CheckField, 8, 4, 0, 105, 7, 0, // Skip to: 10795 +/* 8898 */ MCD_OPC_Decode, 152, 4, 158, 1, // Opcode: ALHHHR +/* 8903 */ MCD_OPC_FilterValue, 203, 1, 17, 0, 0, // Skip to: 8926 +/* 8909 */ MCD_OPC_CheckPredicate, 19, 89, 7, 0, // Skip to: 10795 +/* 8914 */ MCD_OPC_CheckField, 8, 4, 0, 82, 7, 0, // Skip to: 10795 +/* 8921 */ MCD_OPC_Decode, 204, 16, 158, 1, // Opcode: SLHHHR +/* 8926 */ MCD_OPC_FilterValue, 205, 1, 17, 0, 0, // Skip to: 8949 +/* 8932 */ MCD_OPC_CheckPredicate, 19, 66, 7, 0, // Skip to: 10795 +/* 8937 */ MCD_OPC_CheckField, 8, 8, 0, 59, 7, 0, // Skip to: 10795 +/* 8944 */ MCD_OPC_Decode, 182, 6, 159, 1, // Opcode: CHHR +/* 8949 */ MCD_OPC_FilterValue, 207, 1, 17, 0, 0, // Skip to: 8972 +/* 8955 */ MCD_OPC_CheckPredicate, 19, 43, 7, 0, // Skip to: 10795 +/* 8960 */ MCD_OPC_CheckField, 8, 8, 0, 36, 7, 0, // Skip to: 10795 +/* 8967 */ MCD_OPC_Decode, 244, 7, 159, 1, // Opcode: CLHHR +/* 8972 */ MCD_OPC_FilterValue, 216, 1, 17, 0, 0, // Skip to: 8995 +/* 8978 */ MCD_OPC_CheckPredicate, 19, 20, 7, 0, // Skip to: 10795 +/* 8983 */ MCD_OPC_CheckField, 8, 4, 0, 13, 7, 0, // Skip to: 10795 +/* 8990 */ MCD_OPC_Decode, 133, 4, 160, 1, // Opcode: AHHLR +/* 8995 */ MCD_OPC_FilterValue, 217, 1, 17, 0, 0, // Skip to: 9018 +/* 9001 */ MCD_OPC_CheckPredicate, 19, 253, 6, 0, // Skip to: 10795 +/* 9006 */ MCD_OPC_CheckField, 8, 4, 0, 246, 6, 0, // Skip to: 10795 +/* 9013 */ MCD_OPC_Decode, 181, 16, 160, 1, // Opcode: SHHLR +/* 9018 */ MCD_OPC_FilterValue, 218, 1, 17, 0, 0, // Skip to: 9041 +/* 9024 */ MCD_OPC_CheckPredicate, 19, 230, 6, 0, // Skip to: 10795 +/* 9029 */ MCD_OPC_CheckField, 8, 4, 0, 223, 6, 0, // Skip to: 10795 +/* 9036 */ MCD_OPC_Decode, 153, 4, 160, 1, // Opcode: ALHHLR +/* 9041 */ MCD_OPC_FilterValue, 219, 1, 17, 0, 0, // Skip to: 9064 +/* 9047 */ MCD_OPC_CheckPredicate, 19, 207, 6, 0, // Skip to: 10795 +/* 9052 */ MCD_OPC_CheckField, 8, 4, 0, 200, 6, 0, // Skip to: 10795 +/* 9059 */ MCD_OPC_Decode, 205, 16, 160, 1, // Opcode: SLHHLR +/* 9064 */ MCD_OPC_FilterValue, 221, 1, 17, 0, 0, // Skip to: 9087 +/* 9070 */ MCD_OPC_CheckPredicate, 19, 184, 6, 0, // Skip to: 10795 +/* 9075 */ MCD_OPC_CheckField, 8, 8, 0, 177, 6, 0, // Skip to: 10795 +/* 9082 */ MCD_OPC_Decode, 185, 6, 161, 1, // Opcode: CHLR +/* 9087 */ MCD_OPC_FilterValue, 223, 1, 17, 0, 0, // Skip to: 9110 +/* 9093 */ MCD_OPC_CheckPredicate, 19, 161, 6, 0, // Skip to: 10795 +/* 9098 */ MCD_OPC_CheckField, 8, 8, 0, 154, 6, 0, // Skip to: 10795 +/* 9105 */ MCD_OPC_Decode, 246, 7, 161, 1, // Opcode: CLHLR +/* 9110 */ MCD_OPC_FilterValue, 224, 1, 231, 0, 0, // Skip to: 9347 +/* 9116 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 9119 */ MCD_OPC_FilterValue, 0, 135, 6, 0, // Skip to: 10795 +/* 9124 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 9127 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9142 +/* 9132 */ MCD_OPC_CheckPredicate, 20, 200, 0, 0, // Skip to: 9337 +/* 9137 */ MCD_OPC_Decode, 194, 12, 162, 1, // Opcode: LOCFHRAsmO +/* 9142 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9157 +/* 9147 */ MCD_OPC_CheckPredicate, 20, 185, 0, 0, // Skip to: 9337 +/* 9152 */ MCD_OPC_Decode, 178, 12, 162, 1, // Opcode: LOCFHRAsmH +/* 9157 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 9172 +/* 9162 */ MCD_OPC_CheckPredicate, 20, 170, 0, 0, // Skip to: 9337 +/* 9167 */ MCD_OPC_Decode, 188, 12, 162, 1, // Opcode: LOCFHRAsmNLE +/* 9172 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 9187 +/* 9177 */ MCD_OPC_CheckPredicate, 20, 155, 0, 0, // Skip to: 9337 +/* 9182 */ MCD_OPC_Decode, 180, 12, 162, 1, // Opcode: LOCFHRAsmL +/* 9187 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 9202 +/* 9192 */ MCD_OPC_CheckPredicate, 20, 140, 0, 0, // Skip to: 9337 +/* 9197 */ MCD_OPC_Decode, 186, 12, 162, 1, // Opcode: LOCFHRAsmNHE +/* 9202 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 9217 +/* 9207 */ MCD_OPC_CheckPredicate, 20, 125, 0, 0, // Skip to: 9337 +/* 9212 */ MCD_OPC_Decode, 182, 12, 162, 1, // Opcode: LOCFHRAsmLH +/* 9217 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 9232 +/* 9222 */ MCD_OPC_CheckPredicate, 20, 110, 0, 0, // Skip to: 9337 +/* 9227 */ MCD_OPC_Decode, 184, 12, 162, 1, // Opcode: LOCFHRAsmNE +/* 9232 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 9247 +/* 9237 */ MCD_OPC_CheckPredicate, 20, 95, 0, 0, // Skip to: 9337 +/* 9242 */ MCD_OPC_Decode, 177, 12, 162, 1, // Opcode: LOCFHRAsmE +/* 9247 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 9262 +/* 9252 */ MCD_OPC_CheckPredicate, 20, 80, 0, 0, // Skip to: 9337 +/* 9257 */ MCD_OPC_Decode, 189, 12, 162, 1, // Opcode: LOCFHRAsmNLH +/* 9262 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 9277 +/* 9267 */ MCD_OPC_CheckPredicate, 20, 65, 0, 0, // Skip to: 9337 +/* 9272 */ MCD_OPC_Decode, 179, 12, 162, 1, // Opcode: LOCFHRAsmHE +/* 9277 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 9292 +/* 9282 */ MCD_OPC_CheckPredicate, 20, 50, 0, 0, // Skip to: 9337 +/* 9287 */ MCD_OPC_Decode, 187, 12, 162, 1, // Opcode: LOCFHRAsmNL +/* 9292 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 9307 +/* 9297 */ MCD_OPC_CheckPredicate, 20, 35, 0, 0, // Skip to: 9337 +/* 9302 */ MCD_OPC_Decode, 181, 12, 162, 1, // Opcode: LOCFHRAsmLE +/* 9307 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 9322 +/* 9312 */ MCD_OPC_CheckPredicate, 20, 20, 0, 0, // Skip to: 9337 +/* 9317 */ MCD_OPC_Decode, 185, 12, 162, 1, // Opcode: LOCFHRAsmNH +/* 9322 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9337 +/* 9327 */ MCD_OPC_CheckPredicate, 20, 5, 0, 0, // Skip to: 9337 +/* 9332 */ MCD_OPC_Decode, 191, 12, 162, 1, // Opcode: LOCFHRAsmNO +/* 9337 */ MCD_OPC_CheckPredicate, 20, 173, 5, 0, // Skip to: 10795 +/* 9342 */ MCD_OPC_Decode, 176, 12, 163, 1, // Opcode: LOCFHRAsm +/* 9347 */ MCD_OPC_FilterValue, 225, 1, 33, 0, 0, // Skip to: 9386 +/* 9353 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 9356 */ MCD_OPC_FilterValue, 0, 154, 5, 0, // Skip to: 10795 +/* 9361 */ MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 9377 +/* 9366 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, 0, // Skip to: 9377 +/* 9373 */ MCD_OPC_Decode, 175, 15, 62, // Opcode: POPCNT +/* 9377 */ MCD_OPC_CheckPredicate, 14, 133, 5, 0, // Skip to: 10795 +/* 9382 */ MCD_OPC_Decode, 176, 15, 74, // Opcode: POPCNTOpt +/* 9386 */ MCD_OPC_FilterValue, 226, 1, 231, 0, 0, // Skip to: 9623 +/* 9392 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 9395 */ MCD_OPC_FilterValue, 0, 115, 5, 0, // Skip to: 10795 +/* 9400 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 9403 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9418 +/* 9408 */ MCD_OPC_CheckPredicate, 22, 200, 0, 0, // Skip to: 9613 +/* 9413 */ MCD_OPC_Decode, 132, 13, 136, 1, // Opcode: LOCGRAsmO +/* 9418 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9433 +/* 9423 */ MCD_OPC_CheckPredicate, 22, 185, 0, 0, // Skip to: 9613 +/* 9428 */ MCD_OPC_Decode, 244, 12, 136, 1, // Opcode: LOCGRAsmH +/* 9433 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 9448 +/* 9438 */ MCD_OPC_CheckPredicate, 22, 170, 0, 0, // Skip to: 9613 +/* 9443 */ MCD_OPC_Decode, 254, 12, 136, 1, // Opcode: LOCGRAsmNLE +/* 9448 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 9463 +/* 9453 */ MCD_OPC_CheckPredicate, 22, 155, 0, 0, // Skip to: 9613 +/* 9458 */ MCD_OPC_Decode, 246, 12, 136, 1, // Opcode: LOCGRAsmL +/* 9463 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 9478 +/* 9468 */ MCD_OPC_CheckPredicate, 22, 140, 0, 0, // Skip to: 9613 +/* 9473 */ MCD_OPC_Decode, 252, 12, 136, 1, // Opcode: LOCGRAsmNHE +/* 9478 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 9493 +/* 9483 */ MCD_OPC_CheckPredicate, 22, 125, 0, 0, // Skip to: 9613 +/* 9488 */ MCD_OPC_Decode, 248, 12, 136, 1, // Opcode: LOCGRAsmLH +/* 9493 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 9508 +/* 9498 */ MCD_OPC_CheckPredicate, 22, 110, 0, 0, // Skip to: 9613 +/* 9503 */ MCD_OPC_Decode, 250, 12, 136, 1, // Opcode: LOCGRAsmNE +/* 9508 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 9523 +/* 9513 */ MCD_OPC_CheckPredicate, 22, 95, 0, 0, // Skip to: 9613 +/* 9518 */ MCD_OPC_Decode, 243, 12, 136, 1, // Opcode: LOCGRAsmE +/* 9523 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 9538 +/* 9528 */ MCD_OPC_CheckPredicate, 22, 80, 0, 0, // Skip to: 9613 +/* 9533 */ MCD_OPC_Decode, 255, 12, 136, 1, // Opcode: LOCGRAsmNLH +/* 9538 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 9553 +/* 9543 */ MCD_OPC_CheckPredicate, 22, 65, 0, 0, // Skip to: 9613 +/* 9548 */ MCD_OPC_Decode, 245, 12, 136, 1, // Opcode: LOCGRAsmHE +/* 9553 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 9568 +/* 9558 */ MCD_OPC_CheckPredicate, 22, 50, 0, 0, // Skip to: 9613 +/* 9563 */ MCD_OPC_Decode, 253, 12, 136, 1, // Opcode: LOCGRAsmNL +/* 9568 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 9583 +/* 9573 */ MCD_OPC_CheckPredicate, 22, 35, 0, 0, // Skip to: 9613 +/* 9578 */ MCD_OPC_Decode, 247, 12, 136, 1, // Opcode: LOCGRAsmLE +/* 9583 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 9598 +/* 9588 */ MCD_OPC_CheckPredicate, 22, 20, 0, 0, // Skip to: 9613 +/* 9593 */ MCD_OPC_Decode, 251, 12, 136, 1, // Opcode: LOCGRAsmNH +/* 9598 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9613 +/* 9603 */ MCD_OPC_CheckPredicate, 22, 5, 0, 0, // Skip to: 9613 +/* 9608 */ MCD_OPC_Decode, 129, 13, 136, 1, // Opcode: LOCGRAsmNO +/* 9613 */ MCD_OPC_CheckPredicate, 22, 153, 4, 0, // Skip to: 10795 +/* 9618 */ MCD_OPC_Decode, 242, 12, 164, 1, // Opcode: LOCGRAsm +/* 9623 */ MCD_OPC_FilterValue, 227, 1, 223, 0, 0, // Skip to: 9852 +/* 9629 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 9632 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9647 +/* 9637 */ MCD_OPC_CheckPredicate, 14, 200, 0, 0, // Skip to: 9842 +/* 9642 */ MCD_OPC_Decode, 145, 16, 165, 1, // Opcode: SELGRAsmO +/* 9647 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9662 +/* 9652 */ MCD_OPC_CheckPredicate, 14, 185, 0, 0, // Skip to: 9842 +/* 9657 */ MCD_OPC_Decode, 129, 16, 165, 1, // Opcode: SELGRAsmH +/* 9662 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 9677 +/* 9667 */ MCD_OPC_CheckPredicate, 14, 170, 0, 0, // Skip to: 9842 +/* 9672 */ MCD_OPC_Decode, 139, 16, 165, 1, // Opcode: SELGRAsmNLE +/* 9677 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 9692 +/* 9682 */ MCD_OPC_CheckPredicate, 14, 155, 0, 0, // Skip to: 9842 +/* 9687 */ MCD_OPC_Decode, 131, 16, 165, 1, // Opcode: SELGRAsmL +/* 9692 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 9707 +/* 9697 */ MCD_OPC_CheckPredicate, 14, 140, 0, 0, // Skip to: 9842 +/* 9702 */ MCD_OPC_Decode, 137, 16, 165, 1, // Opcode: SELGRAsmNHE +/* 9707 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 9722 +/* 9712 */ MCD_OPC_CheckPredicate, 14, 125, 0, 0, // Skip to: 9842 +/* 9717 */ MCD_OPC_Decode, 133, 16, 165, 1, // Opcode: SELGRAsmLH +/* 9722 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 9737 +/* 9727 */ MCD_OPC_CheckPredicate, 14, 110, 0, 0, // Skip to: 9842 +/* 9732 */ MCD_OPC_Decode, 135, 16, 165, 1, // Opcode: SELGRAsmNE +/* 9737 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 9752 +/* 9742 */ MCD_OPC_CheckPredicate, 14, 95, 0, 0, // Skip to: 9842 +/* 9747 */ MCD_OPC_Decode, 128, 16, 165, 1, // Opcode: SELGRAsmE +/* 9752 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 9767 +/* 9757 */ MCD_OPC_CheckPredicate, 14, 80, 0, 0, // Skip to: 9842 +/* 9762 */ MCD_OPC_Decode, 140, 16, 165, 1, // Opcode: SELGRAsmNLH +/* 9767 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 9782 +/* 9772 */ MCD_OPC_CheckPredicate, 14, 65, 0, 0, // Skip to: 9842 +/* 9777 */ MCD_OPC_Decode, 130, 16, 165, 1, // Opcode: SELGRAsmHE +/* 9782 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 9797 +/* 9787 */ MCD_OPC_CheckPredicate, 14, 50, 0, 0, // Skip to: 9842 +/* 9792 */ MCD_OPC_Decode, 138, 16, 165, 1, // Opcode: SELGRAsmNL +/* 9797 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 9812 +/* 9802 */ MCD_OPC_CheckPredicate, 14, 35, 0, 0, // Skip to: 9842 +/* 9807 */ MCD_OPC_Decode, 132, 16, 165, 1, // Opcode: SELGRAsmLE +/* 9812 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 9827 +/* 9817 */ MCD_OPC_CheckPredicate, 14, 20, 0, 0, // Skip to: 9842 +/* 9822 */ MCD_OPC_Decode, 136, 16, 165, 1, // Opcode: SELGRAsmNH +/* 9827 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9842 +/* 9832 */ MCD_OPC_CheckPredicate, 14, 5, 0, 0, // Skip to: 9842 +/* 9837 */ MCD_OPC_Decode, 142, 16, 165, 1, // Opcode: SELGRAsmNO +/* 9842 */ MCD_OPC_CheckPredicate, 14, 180, 3, 0, // Skip to: 10795 +/* 9847 */ MCD_OPC_Decode, 255, 15, 166, 1, // Opcode: SELGRAsm +/* 9852 */ MCD_OPC_FilterValue, 228, 1, 17, 0, 0, // Skip to: 9875 +/* 9858 */ MCD_OPC_CheckPredicate, 23, 164, 3, 0, // Skip to: 10795 +/* 9863 */ MCD_OPC_CheckField, 8, 4, 0, 157, 3, 0, // Skip to: 10795 +/* 9870 */ MCD_OPC_Decode, 249, 14, 141, 1, // Opcode: NGRK +/* 9875 */ MCD_OPC_FilterValue, 229, 1, 17, 0, 0, // Skip to: 9898 +/* 9881 */ MCD_OPC_CheckPredicate, 14, 141, 3, 0, // Skip to: 10795 +/* 9886 */ MCD_OPC_CheckField, 8, 4, 0, 134, 3, 0, // Skip to: 10795 +/* 9893 */ MCD_OPC_Decode, 245, 14, 141, 1, // Opcode: NCGRK +/* 9898 */ MCD_OPC_FilterValue, 230, 1, 17, 0, 0, // Skip to: 9921 +/* 9904 */ MCD_OPC_CheckPredicate, 23, 118, 3, 0, // Skip to: 10795 +/* 9909 */ MCD_OPC_CheckField, 8, 4, 0, 111, 3, 0, // Skip to: 10795 +/* 9916 */ MCD_OPC_Decode, 149, 15, 141, 1, // Opcode: OGRK +/* 9921 */ MCD_OPC_FilterValue, 231, 1, 17, 0, 0, // Skip to: 9944 +/* 9927 */ MCD_OPC_CheckPredicate, 23, 95, 3, 0, // Skip to: 10795 +/* 9932 */ MCD_OPC_CheckField, 8, 4, 0, 88, 3, 0, // Skip to: 10795 +/* 9939 */ MCD_OPC_Decode, 151, 24, 141, 1, // Opcode: XGRK +/* 9944 */ MCD_OPC_FilterValue, 232, 1, 17, 0, 0, // Skip to: 9967 +/* 9950 */ MCD_OPC_CheckPredicate, 23, 72, 3, 0, // Skip to: 10795 +/* 9955 */ MCD_OPC_CheckField, 8, 4, 0, 65, 3, 0, // Skip to: 10795 +/* 9962 */ MCD_OPC_Decode, 129, 4, 141, 1, // Opcode: AGRK +/* 9967 */ MCD_OPC_FilterValue, 233, 1, 17, 0, 0, // Skip to: 9990 +/* 9973 */ MCD_OPC_CheckPredicate, 23, 49, 3, 0, // Skip to: 10795 +/* 9978 */ MCD_OPC_CheckField, 8, 4, 0, 42, 3, 0, // Skip to: 10795 +/* 9985 */ MCD_OPC_Decode, 178, 16, 141, 1, // Opcode: SGRK +/* 9990 */ MCD_OPC_FilterValue, 234, 1, 17, 0, 0, // Skip to: 10013 +/* 9996 */ MCD_OPC_CheckPredicate, 23, 26, 3, 0, // Skip to: 10795 +/* 10001 */ MCD_OPC_CheckField, 8, 4, 0, 19, 3, 0, // Skip to: 10795 +/* 10008 */ MCD_OPC_Decode, 150, 4, 141, 1, // Opcode: ALGRK +/* 10013 */ MCD_OPC_FilterValue, 235, 1, 17, 0, 0, // Skip to: 10036 +/* 10019 */ MCD_OPC_CheckPredicate, 23, 3, 3, 0, // Skip to: 10795 +/* 10024 */ MCD_OPC_CheckField, 8, 4, 0, 252, 2, 0, // Skip to: 10795 +/* 10031 */ MCD_OPC_Decode, 203, 16, 141, 1, // Opcode: SLGRK +/* 10036 */ MCD_OPC_FilterValue, 236, 1, 17, 0, 0, // Skip to: 10059 +/* 10042 */ MCD_OPC_CheckPredicate, 24, 236, 2, 0, // Skip to: 10795 +/* 10047 */ MCD_OPC_CheckField, 8, 4, 0, 229, 2, 0, // Skip to: 10795 +/* 10054 */ MCD_OPC_Decode, 174, 14, 167, 1, // Opcode: MGRK +/* 10059 */ MCD_OPC_FilterValue, 237, 1, 17, 0, 0, // Skip to: 10082 +/* 10065 */ MCD_OPC_CheckPredicate, 24, 213, 2, 0, // Skip to: 10795 +/* 10070 */ MCD_OPC_CheckField, 8, 4, 0, 206, 2, 0, // Skip to: 10795 +/* 10077 */ MCD_OPC_Decode, 202, 14, 141, 1, // Opcode: MSGRKC +/* 10082 */ MCD_OPC_FilterValue, 240, 1, 223, 0, 0, // Skip to: 10311 +/* 10088 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 10091 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 10106 +/* 10096 */ MCD_OPC_CheckPredicate, 14, 200, 0, 0, // Skip to: 10301 +/* 10101 */ MCD_OPC_Decode, 167, 16, 168, 1, // Opcode: SELRAsmO +/* 10106 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 10121 +/* 10111 */ MCD_OPC_CheckPredicate, 14, 185, 0, 0, // Skip to: 10301 +/* 10116 */ MCD_OPC_Decode, 151, 16, 168, 1, // Opcode: SELRAsmH +/* 10121 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 10136 +/* 10126 */ MCD_OPC_CheckPredicate, 14, 170, 0, 0, // Skip to: 10301 +/* 10131 */ MCD_OPC_Decode, 161, 16, 168, 1, // Opcode: SELRAsmNLE +/* 10136 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 10151 +/* 10141 */ MCD_OPC_CheckPredicate, 14, 155, 0, 0, // Skip to: 10301 +/* 10146 */ MCD_OPC_Decode, 153, 16, 168, 1, // Opcode: SELRAsmL +/* 10151 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 10166 +/* 10156 */ MCD_OPC_CheckPredicate, 14, 140, 0, 0, // Skip to: 10301 +/* 10161 */ MCD_OPC_Decode, 159, 16, 168, 1, // Opcode: SELRAsmNHE +/* 10166 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 10181 +/* 10171 */ MCD_OPC_CheckPredicate, 14, 125, 0, 0, // Skip to: 10301 +/* 10176 */ MCD_OPC_Decode, 155, 16, 168, 1, // Opcode: SELRAsmLH +/* 10181 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 10196 +/* 10186 */ MCD_OPC_CheckPredicate, 14, 110, 0, 0, // Skip to: 10301 +/* 10191 */ MCD_OPC_Decode, 157, 16, 168, 1, // Opcode: SELRAsmNE +/* 10196 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 10211 +/* 10201 */ MCD_OPC_CheckPredicate, 14, 95, 0, 0, // Skip to: 10301 +/* 10206 */ MCD_OPC_Decode, 150, 16, 168, 1, // Opcode: SELRAsmE +/* 10211 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 10226 +/* 10216 */ MCD_OPC_CheckPredicate, 14, 80, 0, 0, // Skip to: 10301 +/* 10221 */ MCD_OPC_Decode, 162, 16, 168, 1, // Opcode: SELRAsmNLH +/* 10226 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 10241 +/* 10231 */ MCD_OPC_CheckPredicate, 14, 65, 0, 0, // Skip to: 10301 +/* 10236 */ MCD_OPC_Decode, 152, 16, 168, 1, // Opcode: SELRAsmHE +/* 10241 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 10256 +/* 10246 */ MCD_OPC_CheckPredicate, 14, 50, 0, 0, // Skip to: 10301 +/* 10251 */ MCD_OPC_Decode, 160, 16, 168, 1, // Opcode: SELRAsmNL +/* 10256 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 10271 +/* 10261 */ MCD_OPC_CheckPredicate, 14, 35, 0, 0, // Skip to: 10301 +/* 10266 */ MCD_OPC_Decode, 154, 16, 168, 1, // Opcode: SELRAsmLE +/* 10271 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 10286 +/* 10276 */ MCD_OPC_CheckPredicate, 14, 20, 0, 0, // Skip to: 10301 +/* 10281 */ MCD_OPC_Decode, 158, 16, 168, 1, // Opcode: SELRAsmNH +/* 10286 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 10301 +/* 10291 */ MCD_OPC_CheckPredicate, 14, 5, 0, 0, // Skip to: 10301 +/* 10296 */ MCD_OPC_Decode, 164, 16, 168, 1, // Opcode: SELRAsmNO +/* 10301 */ MCD_OPC_CheckPredicate, 14, 233, 1, 0, // Skip to: 10795 +/* 10306 */ MCD_OPC_Decode, 149, 16, 169, 1, // Opcode: SELRAsm +/* 10311 */ MCD_OPC_FilterValue, 242, 1, 217, 0, 0, // Skip to: 10534 +/* 10317 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 10320 */ MCD_OPC_FilterValue, 0, 214, 1, 0, // Skip to: 10795 +/* 10325 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 10328 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 10342 +/* 10333 */ MCD_OPC_CheckPredicate, 22, 186, 0, 0, // Skip to: 10524 +/* 10338 */ MCD_OPC_Decode, 198, 13, 9, // Opcode: LOCRAsmO +/* 10342 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 10356 +/* 10347 */ MCD_OPC_CheckPredicate, 22, 172, 0, 0, // Skip to: 10524 +/* 10352 */ MCD_OPC_Decode, 182, 13, 9, // Opcode: LOCRAsmH +/* 10356 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 10370 +/* 10361 */ MCD_OPC_CheckPredicate, 22, 158, 0, 0, // Skip to: 10524 +/* 10366 */ MCD_OPC_Decode, 192, 13, 9, // Opcode: LOCRAsmNLE +/* 10370 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 10384 +/* 10375 */ MCD_OPC_CheckPredicate, 22, 144, 0, 0, // Skip to: 10524 +/* 10380 */ MCD_OPC_Decode, 184, 13, 9, // Opcode: LOCRAsmL +/* 10384 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 10398 +/* 10389 */ MCD_OPC_CheckPredicate, 22, 130, 0, 0, // Skip to: 10524 +/* 10394 */ MCD_OPC_Decode, 190, 13, 9, // Opcode: LOCRAsmNHE +/* 10398 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 10412 +/* 10403 */ MCD_OPC_CheckPredicate, 22, 116, 0, 0, // Skip to: 10524 +/* 10408 */ MCD_OPC_Decode, 186, 13, 9, // Opcode: LOCRAsmLH +/* 10412 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 10426 +/* 10417 */ MCD_OPC_CheckPredicate, 22, 102, 0, 0, // Skip to: 10524 +/* 10422 */ MCD_OPC_Decode, 188, 13, 9, // Opcode: LOCRAsmNE +/* 10426 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 10440 +/* 10431 */ MCD_OPC_CheckPredicate, 22, 88, 0, 0, // Skip to: 10524 +/* 10436 */ MCD_OPC_Decode, 181, 13, 9, // Opcode: LOCRAsmE +/* 10440 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 10454 +/* 10445 */ MCD_OPC_CheckPredicate, 22, 74, 0, 0, // Skip to: 10524 +/* 10450 */ MCD_OPC_Decode, 193, 13, 9, // Opcode: LOCRAsmNLH +/* 10454 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 10468 +/* 10459 */ MCD_OPC_CheckPredicate, 22, 60, 0, 0, // Skip to: 10524 +/* 10464 */ MCD_OPC_Decode, 183, 13, 9, // Opcode: LOCRAsmHE +/* 10468 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 10482 +/* 10473 */ MCD_OPC_CheckPredicate, 22, 46, 0, 0, // Skip to: 10524 +/* 10478 */ MCD_OPC_Decode, 191, 13, 9, // Opcode: LOCRAsmNL +/* 10482 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 10496 +/* 10487 */ MCD_OPC_CheckPredicate, 22, 32, 0, 0, // Skip to: 10524 +/* 10492 */ MCD_OPC_Decode, 185, 13, 9, // Opcode: LOCRAsmLE +/* 10496 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 10510 +/* 10501 */ MCD_OPC_CheckPredicate, 22, 18, 0, 0, // Skip to: 10524 +/* 10506 */ MCD_OPC_Decode, 189, 13, 9, // Opcode: LOCRAsmNH +/* 10510 */ MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 10524 +/* 10515 */ MCD_OPC_CheckPredicate, 22, 4, 0, 0, // Skip to: 10524 +/* 10520 */ MCD_OPC_Decode, 195, 13, 9, // Opcode: LOCRAsmNO +/* 10524 */ MCD_OPC_CheckPredicate, 22, 10, 1, 0, // Skip to: 10795 +/* 10529 */ MCD_OPC_Decode, 180, 13, 170, 1, // Opcode: LOCRAsm +/* 10534 */ MCD_OPC_FilterValue, 244, 1, 17, 0, 0, // Skip to: 10557 +/* 10540 */ MCD_OPC_CheckPredicate, 23, 250, 0, 0, // Skip to: 10795 +/* 10545 */ MCD_OPC_CheckField, 8, 4, 0, 243, 0, 0, // Skip to: 10795 +/* 10552 */ MCD_OPC_Decode, 138, 15, 143, 1, // Opcode: NRK +/* 10557 */ MCD_OPC_FilterValue, 245, 1, 17, 0, 0, // Skip to: 10580 +/* 10563 */ MCD_OPC_CheckPredicate, 14, 227, 0, 0, // Skip to: 10795 +/* 10568 */ MCD_OPC_CheckField, 8, 4, 0, 220, 0, 0, // Skip to: 10795 +/* 10575 */ MCD_OPC_Decode, 246, 14, 143, 1, // Opcode: NCRK +/* 10580 */ MCD_OPC_FilterValue, 246, 1, 17, 0, 0, // Skip to: 10603 +/* 10586 */ MCD_OPC_CheckPredicate, 23, 204, 0, 0, // Skip to: 10795 +/* 10591 */ MCD_OPC_CheckField, 8, 4, 0, 197, 0, 0, // Skip to: 10795 +/* 10598 */ MCD_OPC_Decode, 159, 15, 143, 1, // Opcode: ORK +/* 10603 */ MCD_OPC_FilterValue, 247, 1, 17, 0, 0, // Skip to: 10626 +/* 10609 */ MCD_OPC_CheckPredicate, 23, 181, 0, 0, // Skip to: 10795 +/* 10614 */ MCD_OPC_CheckField, 8, 4, 0, 174, 0, 0, // Skip to: 10795 +/* 10621 */ MCD_OPC_Decode, 157, 24, 143, 1, // Opcode: XRK +/* 10626 */ MCD_OPC_FilterValue, 248, 1, 17, 0, 0, // Skip to: 10649 +/* 10632 */ MCD_OPC_CheckPredicate, 23, 158, 0, 0, // Skip to: 10795 +/* 10637 */ MCD_OPC_CheckField, 8, 4, 0, 151, 0, 0, // Skip to: 10795 +/* 10644 */ MCD_OPC_Decode, 163, 4, 143, 1, // Opcode: ARK +/* 10649 */ MCD_OPC_FilterValue, 249, 1, 17, 0, 0, // Skip to: 10672 +/* 10655 */ MCD_OPC_CheckPredicate, 23, 135, 0, 0, // Skip to: 10795 +/* 10660 */ MCD_OPC_CheckField, 8, 4, 0, 128, 0, 0, // Skip to: 10795 +/* 10667 */ MCD_OPC_Decode, 237, 16, 143, 1, // Opcode: SRK +/* 10672 */ MCD_OPC_FilterValue, 250, 1, 17, 0, 0, // Skip to: 10695 +/* 10678 */ MCD_OPC_CheckPredicate, 23, 112, 0, 0, // Skip to: 10795 +/* 10683 */ MCD_OPC_CheckField, 8, 4, 0, 105, 0, 0, // Skip to: 10795 +/* 10690 */ MCD_OPC_Decode, 156, 4, 143, 1, // Opcode: ALRK +/* 10695 */ MCD_OPC_FilterValue, 251, 1, 17, 0, 0, // Skip to: 10718 +/* 10701 */ MCD_OPC_CheckPredicate, 23, 89, 0, 0, // Skip to: 10795 +/* 10706 */ MCD_OPC_CheckField, 8, 4, 0, 82, 0, 0, // Skip to: 10795 +/* 10713 */ MCD_OPC_Decode, 210, 16, 143, 1, // Opcode: SLRK +/* 10718 */ MCD_OPC_FilterValue, 253, 1, 71, 0, 0, // Skip to: 10795 +/* 10724 */ MCD_OPC_CheckPredicate, 24, 66, 0, 0, // Skip to: 10795 +/* 10729 */ MCD_OPC_CheckField, 8, 4, 0, 59, 0, 0, // Skip to: 10795 +/* 10736 */ MCD_OPC_Decode, 204, 14, 143, 1, // Opcode: MSRKC +/* 10741 */ MCD_OPC_FilterValue, 186, 1, 4, 0, 0, // Skip to: 10751 +/* 10747 */ MCD_OPC_Decode, 141, 9, 36, // Opcode: CS +/* 10751 */ MCD_OPC_FilterValue, 187, 1, 5, 0, 0, // Skip to: 10762 +/* 10757 */ MCD_OPC_Decode, 166, 5, 171, 1, // Opcode: CDS +/* 10762 */ MCD_OPC_FilterValue, 189, 1, 5, 0, 0, // Skip to: 10773 +/* 10768 */ MCD_OPC_Decode, 151, 8, 172, 1, // Opcode: CLM +/* 10773 */ MCD_OPC_FilterValue, 190, 1, 5, 0, 0, // Skip to: 10784 +/* 10779 */ MCD_OPC_Decode, 137, 17, 172, 1, // Opcode: STCM +/* 10784 */ MCD_OPC_FilterValue, 191, 1, 5, 0, 0, // Skip to: 10795 +/* 10790 */ MCD_OPC_Decode, 141, 10, 173, 1, // Opcode: ICM +/* 10795 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTable48[] = { /* 0 */ MCD_OPC_ExtractField, 40, 8, // Inst{47-40} ... -/* 3 */ MCD_OPC_FilterValue, 192, 1, 11, 1, // Skip to: 275 -/* 8 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 11 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 20 -/* 15 */ MCD_OPC_Decode, 250, 9, 166, 1, // Opcode: LARL -/* 20 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 29 -/* 24 */ MCD_OPC_Decode, 181, 10, 167, 1, // Opcode: LGFI -/* 29 */ MCD_OPC_FilterValue, 4, 143, 0, // Skip to: 176 -/* 33 */ MCD_OPC_ExtractField, 36, 4, // Inst{39-36} ... -/* 36 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 45 -/* 40 */ MCD_OPC_Decode, 217, 9, 168, 1, // Opcode: JGAsmO -/* 45 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 54 -/* 49 */ MCD_OPC_Decode, 201, 9, 168, 1, // Opcode: JGAsmH -/* 54 */ MCD_OPC_FilterValue, 3, 5, 0, // Skip to: 63 -/* 58 */ MCD_OPC_Decode, 211, 9, 168, 1, // Opcode: JGAsmNLE -/* 63 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 72 -/* 67 */ MCD_OPC_Decode, 203, 9, 168, 1, // Opcode: JGAsmL -/* 72 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 81 -/* 76 */ MCD_OPC_Decode, 209, 9, 168, 1, // Opcode: JGAsmNHE -/* 81 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 90 -/* 85 */ MCD_OPC_Decode, 205, 9, 168, 1, // Opcode: JGAsmLH -/* 90 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 99 -/* 94 */ MCD_OPC_Decode, 207, 9, 168, 1, // Opcode: JGAsmNE -/* 99 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 108 -/* 103 */ MCD_OPC_Decode, 200, 9, 168, 1, // Opcode: JGAsmE -/* 108 */ MCD_OPC_FilterValue, 9, 5, 0, // Skip to: 117 -/* 112 */ MCD_OPC_Decode, 212, 9, 168, 1, // Opcode: JGAsmNLH -/* 117 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 126 -/* 121 */ MCD_OPC_Decode, 202, 9, 168, 1, // Opcode: JGAsmHE -/* 126 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 135 -/* 130 */ MCD_OPC_Decode, 210, 9, 168, 1, // Opcode: JGAsmNL -/* 135 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 144 -/* 139 */ MCD_OPC_Decode, 204, 9, 168, 1, // Opcode: JGAsmLE -/* 144 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 153 -/* 148 */ MCD_OPC_Decode, 208, 9, 168, 1, // Opcode: JGAsmNH -/* 153 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 162 -/* 157 */ MCD_OPC_Decode, 214, 9, 168, 1, // Opcode: JGAsmNO -/* 162 */ MCD_OPC_FilterValue, 15, 5, 0, // Skip to: 171 -/* 166 */ MCD_OPC_Decode, 199, 9, 168, 1, // Opcode: JG -/* 171 */ MCD_OPC_Decode, 251, 3, 169, 1, // Opcode: BRCLAsm -/* 176 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 185 -/* 180 */ MCD_OPC_Decode, 227, 3, 170, 1, // Opcode: BRASL -/* 185 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 194 -/* 189 */ MCD_OPC_Decode, 232, 21, 171, 1, // Opcode: XIHF -/* 194 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 203 -/* 198 */ MCD_OPC_Decode, 233, 21, 172, 1, // Opcode: XILF -/* 203 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 212 -/* 207 */ MCD_OPC_Decode, 139, 9, 173, 1, // Opcode: IIHF -/* 212 */ MCD_OPC_FilterValue, 9, 5, 0, // Skip to: 221 -/* 216 */ MCD_OPC_Decode, 142, 9, 174, 1, // Opcode: IILF -/* 221 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 230 -/* 225 */ MCD_OPC_Decode, 233, 13, 171, 1, // Opcode: NIHF -/* 230 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 239 -/* 234 */ MCD_OPC_Decode, 236, 13, 172, 1, // Opcode: NILF -/* 239 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 248 -/* 243 */ MCD_OPC_Decode, 250, 13, 171, 1, // Opcode: OIHF -/* 248 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 257 -/* 252 */ MCD_OPC_Decode, 253, 13, 172, 1, // Opcode: OILF -/* 257 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 266 -/* 261 */ MCD_OPC_Decode, 218, 10, 175, 1, // Opcode: LLIHF -/* 266 */ MCD_OPC_FilterValue, 15, 133, 73, // Skip to: 19091 -/* 270 */ MCD_OPC_Decode, 221, 10, 175, 1, // Opcode: LLILF -/* 275 */ MCD_OPC_FilterValue, 194, 1, 111, 0, // Skip to: 391 -/* 280 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 283 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 292 -/* 287 */ MCD_OPC_Decode, 183, 13, 176, 1, // Opcode: MSGFI -/* 292 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 301 -/* 296 */ MCD_OPC_Decode, 179, 13, 177, 1, // Opcode: MSFI -/* 301 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 310 -/* 305 */ MCD_OPC_Decode, 229, 14, 178, 1, // Opcode: SLGFI -/* 310 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 319 -/* 314 */ MCD_OPC_Decode, 226, 14, 172, 1, // Opcode: SLFI -/* 319 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 328 -/* 323 */ MCD_OPC_Decode, 242, 2, 176, 1, // Opcode: AGFI -/* 328 */ MCD_OPC_FilterValue, 9, 5, 0, // Skip to: 337 -/* 332 */ MCD_OPC_Decode, 239, 2, 177, 1, // Opcode: AFI -/* 337 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 346 -/* 341 */ MCD_OPC_Decode, 137, 3, 178, 1, // Opcode: ALGFI -/* 346 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 355 -/* 350 */ MCD_OPC_Decode, 134, 3, 172, 1, // Opcode: ALFI -/* 355 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 364 -/* 359 */ MCD_OPC_Decode, 201, 4, 167, 1, // Opcode: CGFI -/* 364 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 373 -/* 368 */ MCD_OPC_Decode, 186, 4, 179, 1, // Opcode: CFI -/* 373 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 382 -/* 377 */ MCD_OPC_Decode, 255, 5, 175, 1, // Opcode: CLGFI -/* 382 */ MCD_OPC_FilterValue, 15, 17, 73, // Skip to: 19091 -/* 386 */ MCD_OPC_Decode, 233, 5, 174, 1, // Opcode: CLFI -/* 391 */ MCD_OPC_FilterValue, 196, 1, 102, 0, // Skip to: 498 -/* 396 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 399 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 408 -/* 403 */ MCD_OPC_Decode, 217, 10, 180, 1, // Opcode: LLHRL -/* 408 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 417 -/* 412 */ MCD_OPC_Decode, 188, 10, 166, 1, // Opcode: LGHRL -/* 417 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 426 -/* 421 */ MCD_OPC_Decode, 196, 10, 180, 1, // Opcode: LHRL -/* 426 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 435 -/* 430 */ MCD_OPC_Decode, 210, 10, 166, 1, // Opcode: LLGHRL -/* 435 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 444 -/* 439 */ MCD_OPC_Decode, 185, 15, 180, 1, // Opcode: STHRL -/* 444 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 453 -/* 448 */ MCD_OPC_Decode, 190, 10, 166, 1, // Opcode: LGRL -/* 453 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 462 -/* 457 */ MCD_OPC_Decode, 181, 15, 166, 1, // Opcode: STGRL -/* 462 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 471 -/* 466 */ MCD_OPC_Decode, 183, 10, 166, 1, // Opcode: LGFRL -/* 471 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 480 -/* 475 */ MCD_OPC_Decode, 208, 12, 180, 1, // Opcode: LRL -/* 480 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 489 -/* 484 */ MCD_OPC_Decode, 206, 10, 166, 1, // Opcode: LLGFRL -/* 489 */ MCD_OPC_FilterValue, 15, 166, 72, // Skip to: 19091 -/* 493 */ MCD_OPC_Decode, 136, 16, 180, 1, // Opcode: STRL -/* 498 */ MCD_OPC_FilterValue, 197, 1, 9, 0, // Skip to: 512 -/* 503 */ MCD_OPC_CheckPredicate, 3, 152, 72, // Skip to: 19091 -/* 507 */ MCD_OPC_Decode, 224, 3, 181, 1, // Opcode: BPRP -/* 512 */ MCD_OPC_FilterValue, 198, 1, 111, 0, // Skip to: 628 -/* 517 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 520 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 529 -/* 524 */ MCD_OPC_Decode, 239, 8, 166, 1, // Opcode: EXRL -/* 529 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 538 -/* 533 */ MCD_OPC_Decode, 138, 14, 182, 1, // Opcode: PFDRL -/* 538 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 547 -/* 542 */ MCD_OPC_Decode, 206, 4, 166, 1, // Opcode: CGHRL -/* 547 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 556 -/* 551 */ MCD_OPC_Decode, 177, 5, 180, 1, // Opcode: CHRL -/* 556 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 565 -/* 560 */ MCD_OPC_Decode, 130, 6, 166, 1, // Opcode: CLGHRL -/* 565 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 574 -/* 569 */ MCD_OPC_Decode, 238, 6, 180, 1, // Opcode: CLHRL -/* 574 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 583 -/* 578 */ MCD_OPC_Decode, 151, 5, 166, 1, // Opcode: CGRL -/* 583 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 592 -/* 587 */ MCD_OPC_Decode, 203, 6, 166, 1, // Opcode: CLGRL -/* 592 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 601 -/* 596 */ MCD_OPC_Decode, 203, 4, 166, 1, // Opcode: CGFRL -/* 601 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 610 -/* 605 */ MCD_OPC_Decode, 245, 7, 180, 1, // Opcode: CRL -/* 610 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 619 -/* 614 */ MCD_OPC_Decode, 129, 6, 166, 1, // Opcode: CLGFRL -/* 619 */ MCD_OPC_FilterValue, 15, 36, 72, // Skip to: 19091 -/* 623 */ MCD_OPC_Decode, 174, 7, 180, 1, // Opcode: CLRL -/* 628 */ MCD_OPC_FilterValue, 199, 1, 15, 0, // Skip to: 648 -/* 633 */ MCD_OPC_CheckPredicate, 3, 22, 72, // Skip to: 19091 -/* 637 */ MCD_OPC_CheckField, 32, 4, 0, 16, 72, // Skip to: 19091 -/* 643 */ MCD_OPC_Decode, 223, 3, 183, 1, // Opcode: BPP -/* 648 */ MCD_OPC_FilterValue, 200, 1, 56, 0, // Skip to: 709 -/* 653 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 656 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 665 -/* 660 */ MCD_OPC_Decode, 198, 13, 184, 1, // Opcode: MVCOS -/* 665 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 674 -/* 669 */ MCD_OPC_Decode, 219, 8, 184, 1, // Opcode: ECTG -/* 674 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 683 -/* 678 */ MCD_OPC_Decode, 138, 8, 184, 1, // Opcode: CSST -/* 683 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 696 -/* 687 */ MCD_OPC_CheckPredicate, 17, 224, 71, // Skip to: 19091 -/* 691 */ MCD_OPC_Decode, 184, 12, 185, 1, // Opcode: LPD -/* 696 */ MCD_OPC_FilterValue, 5, 215, 71, // Skip to: 19091 -/* 700 */ MCD_OPC_CheckPredicate, 17, 211, 71, // Skip to: 19091 -/* 704 */ MCD_OPC_Decode, 188, 12, 185, 1, // Opcode: LPDG -/* 709 */ MCD_OPC_FilterValue, 204, 1, 81, 0, // Skip to: 795 -/* 714 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 717 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 730 -/* 721 */ MCD_OPC_CheckPredicate, 11, 190, 71, // Skip to: 19091 -/* 725 */ MCD_OPC_Decode, 254, 3, 186, 1, // Opcode: BRCTH -/* 730 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 743 -/* 734 */ MCD_OPC_CheckPredicate, 11, 177, 71, // Skip to: 19091 -/* 738 */ MCD_OPC_Decode, 128, 3, 187, 1, // Opcode: AIH -/* 743 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 756 -/* 747 */ MCD_OPC_CheckPredicate, 11, 164, 71, // Skip to: 19091 -/* 751 */ MCD_OPC_Decode, 149, 3, 187, 1, // Opcode: ALSIH -/* 756 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 769 -/* 760 */ MCD_OPC_CheckPredicate, 11, 151, 71, // Skip to: 19091 -/* 764 */ MCD_OPC_Decode, 150, 3, 187, 1, // Opcode: ALSIHN -/* 769 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 782 -/* 773 */ MCD_OPC_CheckPredicate, 11, 138, 71, // Skip to: 19091 -/* 777 */ MCD_OPC_Decode, 194, 5, 188, 1, // Opcode: CIH -/* 782 */ MCD_OPC_FilterValue, 15, 129, 71, // Skip to: 19091 -/* 786 */ MCD_OPC_CheckPredicate, 11, 125, 71, // Skip to: 19091 -/* 790 */ MCD_OPC_Decode, 254, 6, 173, 1, // Opcode: CLIH -/* 795 */ MCD_OPC_FilterValue, 208, 1, 5, 0, // Skip to: 805 -/* 800 */ MCD_OPC_Decode, 199, 16, 189, 1, // Opcode: TRTR -/* 805 */ MCD_OPC_FilterValue, 209, 1, 5, 0, // Skip to: 815 -/* 810 */ MCD_OPC_Decode, 207, 13, 189, 1, // Opcode: MVN -/* 815 */ MCD_OPC_FilterValue, 210, 1, 5, 0, // Skip to: 825 -/* 820 */ MCD_OPC_Decode, 191, 13, 189, 1, // Opcode: MVC -/* 825 */ MCD_OPC_FilterValue, 211, 1, 5, 0, // Skip to: 835 -/* 830 */ MCD_OPC_Decode, 211, 13, 189, 1, // Opcode: MVZ -/* 835 */ MCD_OPC_FilterValue, 212, 1, 5, 0, // Skip to: 845 -/* 840 */ MCD_OPC_Decode, 227, 13, 189, 1, // Opcode: NC -/* 845 */ MCD_OPC_FilterValue, 213, 1, 5, 0, // Skip to: 855 -/* 850 */ MCD_OPC_Decode, 225, 5, 189, 1, // Opcode: CLC -/* 855 */ MCD_OPC_FilterValue, 214, 1, 5, 0, // Skip to: 865 -/* 860 */ MCD_OPC_Decode, 245, 13, 189, 1, // Opcode: OC -/* 865 */ MCD_OPC_FilterValue, 215, 1, 5, 0, // Skip to: 875 -/* 870 */ MCD_OPC_Decode, 227, 21, 189, 1, // Opcode: XC -/* 875 */ MCD_OPC_FilterValue, 217, 1, 5, 0, // Skip to: 885 -/* 880 */ MCD_OPC_Decode, 194, 13, 190, 1, // Opcode: MVCK -/* 885 */ MCD_OPC_FilterValue, 218, 1, 5, 0, // Skip to: 895 -/* 890 */ MCD_OPC_Decode, 199, 13, 190, 1, // Opcode: MVCP -/* 895 */ MCD_OPC_FilterValue, 219, 1, 5, 0, // Skip to: 905 -/* 900 */ MCD_OPC_Decode, 200, 13, 190, 1, // Opcode: MVCS -/* 905 */ MCD_OPC_FilterValue, 220, 1, 5, 0, // Skip to: 915 -/* 910 */ MCD_OPC_Decode, 184, 16, 189, 1, // Opcode: TR -/* 915 */ MCD_OPC_FilterValue, 221, 1, 5, 0, // Skip to: 925 -/* 920 */ MCD_OPC_Decode, 194, 16, 189, 1, // Opcode: TRT -/* 925 */ MCD_OPC_FilterValue, 222, 1, 5, 0, // Skip to: 935 -/* 930 */ MCD_OPC_Decode, 220, 8, 189, 1, // Opcode: ED -/* 935 */ MCD_OPC_FilterValue, 223, 1, 5, 0, // Skip to: 945 -/* 940 */ MCD_OPC_Decode, 221, 8, 189, 1, // Opcode: EDMK -/* 945 */ MCD_OPC_FilterValue, 225, 1, 5, 0, // Skip to: 955 -/* 950 */ MCD_OPC_Decode, 144, 14, 191, 1, // Opcode: PKU -/* 955 */ MCD_OPC_FilterValue, 226, 1, 5, 0, // Skip to: 965 -/* 960 */ MCD_OPC_Decode, 208, 16, 189, 1, // Opcode: UNPKU -/* 965 */ MCD_OPC_FilterValue, 227, 1, 83, 5, // Skip to: 2333 -/* 970 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... -/* 973 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 982 -/* 977 */ MCD_OPC_Decode, 223, 12, 192, 1, // Opcode: LTG -/* 982 */ MCD_OPC_FilterValue, 3, 5, 0, // Skip to: 991 -/* 986 */ MCD_OPC_Decode, 204, 12, 192, 1, // Opcode: LRAG -/* 991 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 1000 -/* 995 */ MCD_OPC_Decode, 175, 10, 192, 1, // Opcode: LG -/* 1000 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 1009 -/* 1004 */ MCD_OPC_Decode, 160, 8, 193, 1, // Opcode: CVBY -/* 1009 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 1018 -/* 1013 */ MCD_OPC_Decode, 240, 2, 194, 1, // Opcode: AG -/* 1018 */ MCD_OPC_FilterValue, 9, 5, 0, // Skip to: 1027 -/* 1022 */ MCD_OPC_Decode, 202, 14, 194, 1, // Opcode: SG -/* 1027 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 1036 -/* 1031 */ MCD_OPC_Decode, 135, 3, 194, 1, // Opcode: ALG -/* 1036 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 1045 -/* 1040 */ MCD_OPC_Decode, 227, 14, 194, 1, // Opcode: SLG -/* 1045 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 1054 -/* 1049 */ MCD_OPC_Decode, 180, 13, 194, 1, // Opcode: MSG -/* 1054 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 1063 -/* 1058 */ MCD_OPC_Decode, 207, 8, 195, 1, // Opcode: DSG -/* 1063 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 1072 -/* 1067 */ MCD_OPC_Decode, 159, 8, 194, 1, // Opcode: CVBG -/* 1072 */ MCD_OPC_FilterValue, 15, 5, 0, // Skip to: 1081 -/* 1076 */ MCD_OPC_Decode, 210, 12, 192, 1, // Opcode: LRVG -/* 1081 */ MCD_OPC_FilterValue, 18, 5, 0, // Skip to: 1090 -/* 1085 */ MCD_OPC_Decode, 215, 12, 196, 1, // Opcode: LT -/* 1090 */ MCD_OPC_FilterValue, 19, 5, 0, // Skip to: 1099 -/* 1094 */ MCD_OPC_Decode, 205, 12, 192, 1, // Opcode: LRAY -/* 1099 */ MCD_OPC_FilterValue, 20, 5, 0, // Skip to: 1108 -/* 1103 */ MCD_OPC_Decode, 180, 10, 192, 1, // Opcode: LGF -/* 1108 */ MCD_OPC_FilterValue, 21, 5, 0, // Skip to: 1117 -/* 1112 */ MCD_OPC_Decode, 185, 10, 192, 1, // Opcode: LGH -/* 1117 */ MCD_OPC_FilterValue, 22, 5, 0, // Skip to: 1126 -/* 1121 */ MCD_OPC_Decode, 203, 10, 192, 1, // Opcode: LLGF -/* 1126 */ MCD_OPC_FilterValue, 23, 5, 0, // Skip to: 1135 -/* 1130 */ MCD_OPC_Decode, 211, 10, 192, 1, // Opcode: LLGT -/* 1135 */ MCD_OPC_FilterValue, 24, 5, 0, // Skip to: 1144 -/* 1139 */ MCD_OPC_Decode, 241, 2, 194, 1, // Opcode: AGF -/* 1144 */ MCD_OPC_FilterValue, 25, 5, 0, // Skip to: 1153 -/* 1148 */ MCD_OPC_Decode, 203, 14, 194, 1, // Opcode: SGF -/* 1153 */ MCD_OPC_FilterValue, 26, 5, 0, // Skip to: 1162 -/* 1157 */ MCD_OPC_Decode, 136, 3, 194, 1, // Opcode: ALGF -/* 1162 */ MCD_OPC_FilterValue, 27, 5, 0, // Skip to: 1171 -/* 1166 */ MCD_OPC_Decode, 228, 14, 194, 1, // Opcode: SLGF -/* 1171 */ MCD_OPC_FilterValue, 28, 5, 0, // Skip to: 1180 -/* 1175 */ MCD_OPC_Decode, 182, 13, 194, 1, // Opcode: MSGF -/* 1180 */ MCD_OPC_FilterValue, 29, 5, 0, // Skip to: 1189 -/* 1184 */ MCD_OPC_Decode, 208, 8, 195, 1, // Opcode: DSGF -/* 1189 */ MCD_OPC_FilterValue, 30, 5, 0, // Skip to: 1198 -/* 1193 */ MCD_OPC_Decode, 209, 12, 196, 1, // Opcode: LRV -/* 1198 */ MCD_OPC_FilterValue, 31, 5, 0, // Skip to: 1207 -/* 1202 */ MCD_OPC_Decode, 212, 12, 196, 1, // Opcode: LRVH -/* 1207 */ MCD_OPC_FilterValue, 32, 5, 0, // Skip to: 1216 -/* 1211 */ MCD_OPC_Decode, 191, 4, 192, 1, // Opcode: CG -/* 1216 */ MCD_OPC_FilterValue, 33, 5, 0, // Skip to: 1225 -/* 1220 */ MCD_OPC_Decode, 250, 5, 192, 1, // Opcode: CLG -/* 1225 */ MCD_OPC_FilterValue, 36, 5, 0, // Skip to: 1234 -/* 1229 */ MCD_OPC_Decode, 180, 15, 192, 1, // Opcode: STG -/* 1234 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 1247 -/* 1238 */ MCD_OPC_CheckPredicate, 2, 185, 69, // Skip to: 19091 -/* 1242 */ MCD_OPC_Decode, 242, 13, 192, 1, // Opcode: NTSTG -/* 1247 */ MCD_OPC_FilterValue, 38, 5, 0, // Skip to: 1256 -/* 1251 */ MCD_OPC_Decode, 163, 8, 196, 1, // Opcode: CVDY -/* 1256 */ MCD_OPC_FilterValue, 42, 9, 0, // Skip to: 1269 -/* 1260 */ MCD_OPC_CheckPredicate, 18, 163, 69, // Skip to: 19091 -/* 1264 */ MCD_OPC_Decode, 248, 12, 192, 1, // Opcode: LZRG -/* 1269 */ MCD_OPC_FilterValue, 46, 5, 0, // Skip to: 1278 -/* 1273 */ MCD_OPC_Decode, 162, 8, 192, 1, // Opcode: CVDG -/* 1278 */ MCD_OPC_FilterValue, 47, 5, 0, // Skip to: 1287 -/* 1282 */ MCD_OPC_Decode, 138, 16, 192, 1, // Opcode: STRVG -/* 1287 */ MCD_OPC_FilterValue, 48, 5, 0, // Skip to: 1296 -/* 1291 */ MCD_OPC_Decode, 200, 4, 192, 1, // Opcode: CGF -/* 1296 */ MCD_OPC_FilterValue, 49, 5, 0, // Skip to: 1305 -/* 1300 */ MCD_OPC_Decode, 254, 5, 192, 1, // Opcode: CLGF -/* 1305 */ MCD_OPC_FilterValue, 50, 5, 0, // Skip to: 1314 -/* 1309 */ MCD_OPC_Decode, 224, 12, 192, 1, // Opcode: LTGF -/* 1314 */ MCD_OPC_FilterValue, 52, 5, 0, // Skip to: 1323 -/* 1318 */ MCD_OPC_Decode, 204, 4, 192, 1, // Opcode: CGH -/* 1323 */ MCD_OPC_FilterValue, 54, 5, 0, // Skip to: 1332 -/* 1327 */ MCD_OPC_Decode, 137, 14, 197, 1, // Opcode: PFD -/* 1332 */ MCD_OPC_FilterValue, 56, 9, 0, // Skip to: 1345 -/* 1336 */ MCD_OPC_CheckPredicate, 16, 87, 69, // Skip to: 19091 -/* 1340 */ MCD_OPC_Decode, 244, 2, 194, 1, // Opcode: AGH -/* 1345 */ MCD_OPC_FilterValue, 57, 9, 0, // Skip to: 1358 -/* 1349 */ MCD_OPC_CheckPredicate, 16, 74, 69, // Skip to: 19091 -/* 1353 */ MCD_OPC_Decode, 205, 14, 194, 1, // Opcode: SGH -/* 1358 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 1371 -/* 1362 */ MCD_OPC_CheckPredicate, 18, 61, 69, // Skip to: 19091 -/* 1366 */ MCD_OPC_Decode, 224, 10, 192, 1, // Opcode: LLZRGF -/* 1371 */ MCD_OPC_FilterValue, 59, 9, 0, // Skip to: 1384 -/* 1375 */ MCD_OPC_CheckPredicate, 18, 48, 69, // Skip to: 19091 -/* 1379 */ MCD_OPC_Decode, 247, 12, 196, 1, // Opcode: LZRF -/* 1384 */ MCD_OPC_FilterValue, 60, 9, 0, // Skip to: 1397 -/* 1388 */ MCD_OPC_CheckPredicate, 16, 35, 69, // Skip to: 19091 -/* 1392 */ MCD_OPC_Decode, 156, 13, 194, 1, // Opcode: MGH -/* 1397 */ MCD_OPC_FilterValue, 62, 5, 0, // Skip to: 1406 -/* 1401 */ MCD_OPC_Decode, 137, 16, 196, 1, // Opcode: STRV -/* 1406 */ MCD_OPC_FilterValue, 63, 5, 0, // Skip to: 1415 -/* 1410 */ MCD_OPC_Decode, 139, 16, 196, 1, // Opcode: STRVH -/* 1415 */ MCD_OPC_FilterValue, 70, 5, 0, // Skip to: 1424 -/* 1419 */ MCD_OPC_Decode, 197, 3, 194, 1, // Opcode: BCTG -/* 1424 */ MCD_OPC_FilterValue, 71, 207, 0, // Skip to: 1635 -/* 1428 */ MCD_OPC_ExtractField, 36, 4, // Inst{39-36} ... -/* 1431 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1444 -/* 1435 */ MCD_OPC_CheckPredicate, 16, 187, 0, // Skip to: 1626 -/* 1439 */ MCD_OPC_Decode, 218, 3, 198, 1, // Opcode: BIAsmO -/* 1444 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1457 -/* 1448 */ MCD_OPC_CheckPredicate, 16, 174, 0, // Skip to: 1626 -/* 1452 */ MCD_OPC_Decode, 202, 3, 198, 1, // Opcode: BIAsmH -/* 1457 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 1470 -/* 1461 */ MCD_OPC_CheckPredicate, 16, 161, 0, // Skip to: 1626 -/* 1465 */ MCD_OPC_Decode, 212, 3, 198, 1, // Opcode: BIAsmNLE -/* 1470 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 1483 -/* 1474 */ MCD_OPC_CheckPredicate, 16, 148, 0, // Skip to: 1626 -/* 1478 */ MCD_OPC_Decode, 204, 3, 198, 1, // Opcode: BIAsmL -/* 1483 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1496 -/* 1487 */ MCD_OPC_CheckPredicate, 16, 135, 0, // Skip to: 1626 -/* 1491 */ MCD_OPC_Decode, 210, 3, 198, 1, // Opcode: BIAsmNHE -/* 1496 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1509 -/* 1500 */ MCD_OPC_CheckPredicate, 16, 122, 0, // Skip to: 1626 -/* 1504 */ MCD_OPC_Decode, 206, 3, 198, 1, // Opcode: BIAsmLH -/* 1509 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1522 -/* 1513 */ MCD_OPC_CheckPredicate, 16, 109, 0, // Skip to: 1626 -/* 1517 */ MCD_OPC_Decode, 208, 3, 198, 1, // Opcode: BIAsmNE -/* 1522 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1535 -/* 1526 */ MCD_OPC_CheckPredicate, 16, 96, 0, // Skip to: 1626 -/* 1530 */ MCD_OPC_Decode, 201, 3, 198, 1, // Opcode: BIAsmE -/* 1535 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1548 -/* 1539 */ MCD_OPC_CheckPredicate, 16, 83, 0, // Skip to: 1626 -/* 1543 */ MCD_OPC_Decode, 213, 3, 198, 1, // Opcode: BIAsmNLH -/* 1548 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1561 -/* 1552 */ MCD_OPC_CheckPredicate, 16, 70, 0, // Skip to: 1626 -/* 1556 */ MCD_OPC_Decode, 203, 3, 198, 1, // Opcode: BIAsmHE -/* 1561 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1574 -/* 1565 */ MCD_OPC_CheckPredicate, 16, 57, 0, // Skip to: 1626 -/* 1569 */ MCD_OPC_Decode, 211, 3, 198, 1, // Opcode: BIAsmNL -/* 1574 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1587 -/* 1578 */ MCD_OPC_CheckPredicate, 16, 44, 0, // Skip to: 1626 -/* 1582 */ MCD_OPC_Decode, 205, 3, 198, 1, // Opcode: BIAsmLE -/* 1587 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1600 -/* 1591 */ MCD_OPC_CheckPredicate, 16, 31, 0, // Skip to: 1626 -/* 1595 */ MCD_OPC_Decode, 209, 3, 198, 1, // Opcode: BIAsmNH -/* 1600 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1613 -/* 1604 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 1626 -/* 1608 */ MCD_OPC_Decode, 215, 3, 198, 1, // Opcode: BIAsmNO -/* 1613 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 1626 -/* 1617 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 1626 -/* 1621 */ MCD_OPC_Decode, 200, 3, 198, 1, // Opcode: BI -/* 1626 */ MCD_OPC_CheckPredicate, 16, 53, 68, // Skip to: 19091 -/* 1630 */ MCD_OPC_Decode, 222, 3, 197, 1, // Opcode: BICAsm -/* 1635 */ MCD_OPC_FilterValue, 72, 9, 0, // Skip to: 1648 -/* 1639 */ MCD_OPC_CheckPredicate, 19, 40, 68, // Skip to: 19091 -/* 1643 */ MCD_OPC_Decode, 207, 10, 192, 1, // Opcode: LLGFSG -/* 1648 */ MCD_OPC_FilterValue, 73, 9, 0, // Skip to: 1661 -/* 1652 */ MCD_OPC_CheckPredicate, 19, 27, 68, // Skip to: 19091 -/* 1656 */ MCD_OPC_Decode, 182, 15, 192, 1, // Opcode: STGSC -/* 1661 */ MCD_OPC_FilterValue, 76, 9, 0, // Skip to: 1674 -/* 1665 */ MCD_OPC_CheckPredicate, 19, 14, 68, // Skip to: 19091 -/* 1669 */ MCD_OPC_Decode, 184, 10, 192, 1, // Opcode: LGG -/* 1674 */ MCD_OPC_FilterValue, 77, 9, 0, // Skip to: 1687 -/* 1678 */ MCD_OPC_CheckPredicate, 19, 1, 68, // Skip to: 19091 -/* 1682 */ MCD_OPC_Decode, 191, 10, 192, 1, // Opcode: LGSC -/* 1687 */ MCD_OPC_FilterValue, 80, 5, 0, // Skip to: 1696 -/* 1691 */ MCD_OPC_Decode, 144, 16, 196, 1, // Opcode: STY -/* 1696 */ MCD_OPC_FilterValue, 81, 5, 0, // Skip to: 1705 -/* 1700 */ MCD_OPC_Decode, 190, 13, 193, 1, // Opcode: MSY -/* 1705 */ MCD_OPC_FilterValue, 83, 9, 0, // Skip to: 1718 -/* 1709 */ MCD_OPC_CheckPredicate, 16, 226, 67, // Skip to: 19091 -/* 1713 */ MCD_OPC_Decode, 169, 13, 193, 1, // Opcode: MSC -/* 1718 */ MCD_OPC_FilterValue, 84, 5, 0, // Skip to: 1727 -/* 1722 */ MCD_OPC_Decode, 243, 13, 193, 1, // Opcode: NY -/* 1727 */ MCD_OPC_FilterValue, 85, 5, 0, // Skip to: 1736 -/* 1731 */ MCD_OPC_Decode, 204, 7, 196, 1, // Opcode: CLY -/* 1736 */ MCD_OPC_FilterValue, 86, 5, 0, // Skip to: 1745 -/* 1740 */ MCD_OPC_Decode, 131, 14, 193, 1, // Opcode: OY -/* 1745 */ MCD_OPC_FilterValue, 87, 5, 0, // Skip to: 1754 -/* 1749 */ MCD_OPC_Decode, 238, 21, 193, 1, // Opcode: XY -/* 1754 */ MCD_OPC_FilterValue, 88, 5, 0, // Skip to: 1763 -/* 1758 */ MCD_OPC_Decode, 244, 12, 196, 1, // Opcode: LY -/* 1763 */ MCD_OPC_FilterValue, 89, 5, 0, // Skip to: 1772 -/* 1767 */ MCD_OPC_Decode, 184, 8, 196, 1, // Opcode: CY -/* 1772 */ MCD_OPC_FilterValue, 90, 5, 0, // Skip to: 1781 -/* 1776 */ MCD_OPC_Decode, 164, 3, 193, 1, // Opcode: AY -/* 1781 */ MCD_OPC_FilterValue, 91, 5, 0, // Skip to: 1790 -/* 1785 */ MCD_OPC_Decode, 154, 16, 193, 1, // Opcode: SY -/* 1790 */ MCD_OPC_FilterValue, 92, 5, 0, // Skip to: 1799 -/* 1794 */ MCD_OPC_Decode, 154, 13, 195, 1, // Opcode: MFY -/* 1799 */ MCD_OPC_FilterValue, 94, 5, 0, // Skip to: 1808 -/* 1803 */ MCD_OPC_Decode, 151, 3, 193, 1, // Opcode: ALY -/* 1808 */ MCD_OPC_FilterValue, 95, 5, 0, // Skip to: 1817 -/* 1812 */ MCD_OPC_Decode, 241, 14, 193, 1, // Opcode: SLY -/* 1817 */ MCD_OPC_FilterValue, 112, 5, 0, // Skip to: 1826 -/* 1821 */ MCD_OPC_Decode, 186, 15, 196, 1, // Opcode: STHY -/* 1826 */ MCD_OPC_FilterValue, 113, 5, 0, // Skip to: 1835 -/* 1830 */ MCD_OPC_Decode, 255, 9, 192, 1, // Opcode: LAY -/* 1835 */ MCD_OPC_FilterValue, 114, 5, 0, // Skip to: 1844 -/* 1839 */ MCD_OPC_Decode, 171, 15, 196, 1, // Opcode: STCY -/* 1844 */ MCD_OPC_FilterValue, 115, 5, 0, // Skip to: 1853 -/* 1848 */ MCD_OPC_Decode, 134, 9, 194, 1, // Opcode: ICY -/* 1853 */ MCD_OPC_FilterValue, 117, 5, 0, // Skip to: 1862 -/* 1857 */ MCD_OPC_Decode, 243, 9, 192, 1, // Opcode: LAEY -/* 1862 */ MCD_OPC_FilterValue, 118, 5, 0, // Skip to: 1871 -/* 1866 */ MCD_OPC_Decode, 128, 10, 196, 1, // Opcode: LB -/* 1871 */ MCD_OPC_FilterValue, 119, 5, 0, // Skip to: 1880 -/* 1875 */ MCD_OPC_Decode, 177, 10, 192, 1, // Opcode: LGB -/* 1880 */ MCD_OPC_FilterValue, 120, 5, 0, // Skip to: 1889 -/* 1884 */ MCD_OPC_Decode, 197, 10, 196, 1, // Opcode: LHY -/* 1889 */ MCD_OPC_FilterValue, 121, 5, 0, // Skip to: 1898 -/* 1893 */ MCD_OPC_Decode, 179, 5, 196, 1, // Opcode: CHY -/* 1898 */ MCD_OPC_FilterValue, 122, 5, 0, // Skip to: 1907 -/* 1902 */ MCD_OPC_Decode, 255, 2, 193, 1, // Opcode: AHY -/* 1907 */ MCD_OPC_FilterValue, 123, 5, 0, // Skip to: 1916 -/* 1911 */ MCD_OPC_Decode, 211, 14, 193, 1, // Opcode: SHY -/* 1916 */ MCD_OPC_FilterValue, 124, 5, 0, // Skip to: 1925 -/* 1920 */ MCD_OPC_Decode, 161, 13, 193, 1, // Opcode: MHY -/* 1925 */ MCD_OPC_FilterValue, 128, 1, 5, 0, // Skip to: 1935 -/* 1930 */ MCD_OPC_Decode, 228, 13, 194, 1, // Opcode: NG -/* 1935 */ MCD_OPC_FilterValue, 129, 1, 5, 0, // Skip to: 1945 -/* 1940 */ MCD_OPC_Decode, 246, 13, 194, 1, // Opcode: OG -/* 1945 */ MCD_OPC_FilterValue, 130, 1, 5, 0, // Skip to: 1955 -/* 1950 */ MCD_OPC_Decode, 228, 21, 194, 1, // Opcode: XG -/* 1955 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 1969 -/* 1960 */ MCD_OPC_CheckPredicate, 16, 231, 66, // Skip to: 19091 -/* 1964 */ MCD_OPC_Decode, 181, 13, 194, 1, // Opcode: MSGC -/* 1969 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 1983 -/* 1974 */ MCD_OPC_CheckPredicate, 16, 217, 66, // Skip to: 19091 -/* 1978 */ MCD_OPC_Decode, 155, 13, 195, 1, // Opcode: MG -/* 1983 */ MCD_OPC_FilterValue, 133, 1, 9, 0, // Skip to: 1997 -/* 1988 */ MCD_OPC_CheckPredicate, 20, 203, 66, // Skip to: 19091 -/* 1992 */ MCD_OPC_Decode, 176, 10, 192, 1, // Opcode: LGAT -/* 1997 */ MCD_OPC_FilterValue, 134, 1, 5, 0, // Skip to: 2007 -/* 2002 */ MCD_OPC_Decode, 163, 13, 195, 1, // Opcode: MLG -/* 2007 */ MCD_OPC_FilterValue, 135, 1, 5, 0, // Skip to: 2017 -/* 2012 */ MCD_OPC_Decode, 202, 8, 195, 1, // Opcode: DLG -/* 2017 */ MCD_OPC_FilterValue, 136, 1, 5, 0, // Skip to: 2027 -/* 2022 */ MCD_OPC_Decode, 131, 3, 194, 1, // Opcode: ALCG -/* 2027 */ MCD_OPC_FilterValue, 137, 1, 5, 0, // Skip to: 2037 -/* 2032 */ MCD_OPC_Decode, 220, 14, 194, 1, // Opcode: SLBG -/* 2037 */ MCD_OPC_FilterValue, 142, 1, 5, 0, // Skip to: 2047 -/* 2042 */ MCD_OPC_Decode, 132, 16, 199, 1, // Opcode: STPQ -/* 2047 */ MCD_OPC_FilterValue, 143, 1, 5, 0, // Skip to: 2057 -/* 2052 */ MCD_OPC_Decode, 195, 12, 199, 1, // Opcode: LPQ -/* 2057 */ MCD_OPC_FilterValue, 144, 1, 5, 0, // Skip to: 2067 -/* 2062 */ MCD_OPC_Decode, 201, 10, 192, 1, // Opcode: LLGC -/* 2067 */ MCD_OPC_FilterValue, 145, 1, 5, 0, // Skip to: 2077 -/* 2072 */ MCD_OPC_Decode, 208, 10, 192, 1, // Opcode: LLGH -/* 2077 */ MCD_OPC_FilterValue, 148, 1, 5, 0, // Skip to: 2087 -/* 2082 */ MCD_OPC_Decode, 198, 10, 196, 1, // Opcode: LLC -/* 2087 */ MCD_OPC_FilterValue, 149, 1, 5, 0, // Skip to: 2097 -/* 2092 */ MCD_OPC_Decode, 214, 10, 196, 1, // Opcode: LLH -/* 2097 */ MCD_OPC_FilterValue, 150, 1, 5, 0, // Skip to: 2107 -/* 2102 */ MCD_OPC_Decode, 162, 13, 195, 1, // Opcode: ML -/* 2107 */ MCD_OPC_FilterValue, 151, 1, 5, 0, // Skip to: 2117 -/* 2112 */ MCD_OPC_Decode, 201, 8, 195, 1, // Opcode: DL -/* 2117 */ MCD_OPC_FilterValue, 152, 1, 5, 0, // Skip to: 2127 -/* 2122 */ MCD_OPC_Decode, 130, 3, 193, 1, // Opcode: ALC -/* 2127 */ MCD_OPC_FilterValue, 153, 1, 5, 0, // Skip to: 2137 -/* 2132 */ MCD_OPC_Decode, 219, 14, 193, 1, // Opcode: SLB -/* 2137 */ MCD_OPC_FilterValue, 156, 1, 9, 0, // Skip to: 2151 -/* 2142 */ MCD_OPC_CheckPredicate, 20, 49, 66, // Skip to: 19091 -/* 2146 */ MCD_OPC_Decode, 212, 10, 192, 1, // Opcode: LLGTAT -/* 2151 */ MCD_OPC_FilterValue, 157, 1, 9, 0, // Skip to: 2165 -/* 2156 */ MCD_OPC_CheckPredicate, 20, 35, 66, // Skip to: 19091 -/* 2160 */ MCD_OPC_Decode, 204, 10, 192, 1, // Opcode: LLGFAT -/* 2165 */ MCD_OPC_FilterValue, 159, 1, 9, 0, // Skip to: 2179 -/* 2170 */ MCD_OPC_CheckPredicate, 20, 21, 66, // Skip to: 19091 -/* 2174 */ MCD_OPC_Decode, 252, 9, 196, 1, // Opcode: LAT -/* 2179 */ MCD_OPC_FilterValue, 192, 1, 9, 0, // Skip to: 2193 -/* 2184 */ MCD_OPC_CheckPredicate, 11, 7, 66, // Skip to: 19091 -/* 2188 */ MCD_OPC_Decode, 129, 10, 200, 1, // Opcode: LBH -/* 2193 */ MCD_OPC_FilterValue, 194, 1, 9, 0, // Skip to: 2207 -/* 2198 */ MCD_OPC_CheckPredicate, 11, 249, 65, // Skip to: 19091 -/* 2202 */ MCD_OPC_Decode, 199, 10, 200, 1, // Opcode: LLCH -/* 2207 */ MCD_OPC_FilterValue, 195, 1, 9, 0, // Skip to: 2221 -/* 2212 */ MCD_OPC_CheckPredicate, 11, 235, 65, // Skip to: 19091 -/* 2216 */ MCD_OPC_Decode, 159, 15, 200, 1, // Opcode: STCH -/* 2221 */ MCD_OPC_FilterValue, 196, 1, 9, 0, // Skip to: 2235 -/* 2226 */ MCD_OPC_CheckPredicate, 11, 221, 65, // Skip to: 19091 -/* 2230 */ MCD_OPC_Decode, 193, 10, 200, 1, // Opcode: LHH -/* 2235 */ MCD_OPC_FilterValue, 198, 1, 9, 0, // Skip to: 2249 -/* 2240 */ MCD_OPC_CheckPredicate, 11, 207, 65, // Skip to: 19091 -/* 2244 */ MCD_OPC_Decode, 215, 10, 200, 1, // Opcode: LLHH -/* 2249 */ MCD_OPC_FilterValue, 199, 1, 9, 0, // Skip to: 2263 -/* 2254 */ MCD_OPC_CheckPredicate, 11, 193, 65, // Skip to: 19091 -/* 2258 */ MCD_OPC_Decode, 184, 15, 200, 1, // Opcode: STHH -/* 2263 */ MCD_OPC_FilterValue, 200, 1, 9, 0, // Skip to: 2277 -/* 2268 */ MCD_OPC_CheckPredicate, 20, 179, 65, // Skip to: 19091 -/* 2272 */ MCD_OPC_Decode, 173, 10, 200, 1, // Opcode: LFHAT -/* 2277 */ MCD_OPC_FilterValue, 202, 1, 9, 0, // Skip to: 2291 -/* 2282 */ MCD_OPC_CheckPredicate, 11, 165, 65, // Skip to: 19091 -/* 2286 */ MCD_OPC_Decode, 172, 10, 200, 1, // Opcode: LFH -/* 2291 */ MCD_OPC_FilterValue, 203, 1, 9, 0, // Skip to: 2305 -/* 2296 */ MCD_OPC_CheckPredicate, 11, 151, 65, // Skip to: 19091 -/* 2300 */ MCD_OPC_Decode, 176, 15, 200, 1, // Opcode: STFH -/* 2305 */ MCD_OPC_FilterValue, 205, 1, 9, 0, // Skip to: 2319 -/* 2310 */ MCD_OPC_CheckPredicate, 11, 137, 65, // Skip to: 19091 -/* 2314 */ MCD_OPC_Decode, 172, 5, 200, 1, // Opcode: CHF -/* 2319 */ MCD_OPC_FilterValue, 207, 1, 127, 65, // Skip to: 19091 -/* 2324 */ MCD_OPC_CheckPredicate, 11, 123, 65, // Skip to: 19091 -/* 2328 */ MCD_OPC_Decode, 234, 6, 200, 1, // Opcode: CLHF -/* 2333 */ MCD_OPC_FilterValue, 229, 1, 155, 0, // Skip to: 2493 -/* 2338 */ MCD_OPC_ExtractField, 32, 8, // Inst{39-32} ... -/* 2341 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 2350 -/* 2345 */ MCD_OPC_Decode, 251, 9, 201, 1, // Opcode: LASP -/* 2350 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 2359 -/* 2354 */ MCD_OPC_Decode, 183, 16, 201, 1, // Opcode: TPROT -/* 2359 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 2368 -/* 2363 */ MCD_OPC_Decode, 135, 16, 201, 1, // Opcode: STRAG -/* 2368 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 2377 -/* 2372 */ MCD_OPC_Decode, 201, 13, 201, 1, // Opcode: MVCSK -/* 2377 */ MCD_OPC_FilterValue, 15, 5, 0, // Skip to: 2386 -/* 2381 */ MCD_OPC_Decode, 192, 13, 201, 1, // Opcode: MVCDK -/* 2386 */ MCD_OPC_FilterValue, 68, 5, 0, // Skip to: 2395 -/* 2390 */ MCD_OPC_Decode, 203, 13, 202, 1, // Opcode: MVHHI -/* 2395 */ MCD_OPC_FilterValue, 72, 5, 0, // Skip to: 2404 -/* 2399 */ MCD_OPC_Decode, 202, 13, 202, 1, // Opcode: MVGHI -/* 2404 */ MCD_OPC_FilterValue, 76, 5, 0, // Skip to: 2413 -/* 2408 */ MCD_OPC_Decode, 204, 13, 202, 1, // Opcode: MVHI -/* 2413 */ MCD_OPC_FilterValue, 84, 5, 0, // Skip to: 2422 -/* 2417 */ MCD_OPC_Decode, 174, 5, 202, 1, // Opcode: CHHSI -/* 2422 */ MCD_OPC_FilterValue, 85, 5, 0, // Skip to: 2431 -/* 2426 */ MCD_OPC_Decode, 236, 6, 203, 1, // Opcode: CLHHSI -/* 2431 */ MCD_OPC_FilterValue, 88, 5, 0, // Skip to: 2440 -/* 2435 */ MCD_OPC_Decode, 207, 4, 202, 1, // Opcode: CGHSI -/* 2440 */ MCD_OPC_FilterValue, 89, 5, 0, // Skip to: 2449 -/* 2444 */ MCD_OPC_Decode, 131, 6, 203, 1, // Opcode: CLGHSI -/* 2449 */ MCD_OPC_FilterValue, 92, 5, 0, // Skip to: 2458 -/* 2453 */ MCD_OPC_Decode, 178, 5, 202, 1, // Opcode: CHSI -/* 2458 */ MCD_OPC_FilterValue, 93, 5, 0, // Skip to: 2467 -/* 2462 */ MCD_OPC_Decode, 232, 5, 203, 1, // Opcode: CLFHSI -/* 2467 */ MCD_OPC_FilterValue, 96, 9, 0, // Skip to: 2480 -/* 2471 */ MCD_OPC_CheckPredicate, 2, 232, 64, // Skip to: 19091 -/* 2475 */ MCD_OPC_Decode, 161, 16, 203, 1, // Opcode: TBEGIN -/* 2480 */ MCD_OPC_FilterValue, 97, 223, 64, // Skip to: 19091 -/* 2484 */ MCD_OPC_CheckPredicate, 2, 219, 64, // Skip to: 19091 -/* 2488 */ MCD_OPC_Decode, 162, 16, 203, 1, // Opcode: TBEGINC -/* 2493 */ MCD_OPC_FilterValue, 230, 1, 35, 2, // Skip to: 3045 -/* 2498 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... -/* 2501 */ MCD_OPC_FilterValue, 52, 15, 0, // Skip to: 2520 -/* 2505 */ MCD_OPC_CheckPredicate, 21, 198, 64, // Skip to: 19091 -/* 2509 */ MCD_OPC_CheckField, 9, 3, 0, 192, 64, // Skip to: 19091 -/* 2515 */ MCD_OPC_Decode, 146, 20, 204, 1, // Opcode: VPKZ -/* 2520 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 2539 -/* 2524 */ MCD_OPC_CheckPredicate, 21, 179, 64, // Skip to: 19091 -/* 2528 */ MCD_OPC_CheckField, 9, 3, 0, 173, 64, // Skip to: 19091 -/* 2534 */ MCD_OPC_Decode, 148, 19, 204, 1, // Opcode: VLRL -/* 2539 */ MCD_OPC_FilterValue, 55, 21, 0, // Skip to: 2564 -/* 2543 */ MCD_OPC_CheckPredicate, 21, 160, 64, // Skip to: 19091 -/* 2547 */ MCD_OPC_CheckField, 36, 4, 0, 154, 64, // Skip to: 19091 -/* 2553 */ MCD_OPC_CheckField, 9, 3, 0, 148, 64, // Skip to: 19091 -/* 2559 */ MCD_OPC_Decode, 149, 19, 205, 1, // Opcode: VLRLR -/* 2564 */ MCD_OPC_FilterValue, 60, 15, 0, // Skip to: 2583 -/* 2568 */ MCD_OPC_CheckPredicate, 21, 135, 64, // Skip to: 19091 -/* 2572 */ MCD_OPC_CheckField, 9, 3, 0, 129, 64, // Skip to: 19091 -/* 2578 */ MCD_OPC_Decode, 234, 20, 204, 1, // Opcode: VUPKZ -/* 2583 */ MCD_OPC_FilterValue, 61, 15, 0, // Skip to: 2602 -/* 2587 */ MCD_OPC_CheckPredicate, 21, 116, 64, // Skip to: 19091 -/* 2591 */ MCD_OPC_CheckField, 9, 3, 0, 110, 64, // Skip to: 19091 -/* 2597 */ MCD_OPC_Decode, 217, 20, 204, 1, // Opcode: VSTRL -/* 2602 */ MCD_OPC_FilterValue, 63, 21, 0, // Skip to: 2627 -/* 2606 */ MCD_OPC_CheckPredicate, 21, 97, 64, // Skip to: 19091 -/* 2610 */ MCD_OPC_CheckField, 36, 4, 0, 91, 64, // Skip to: 19091 -/* 2616 */ MCD_OPC_CheckField, 9, 3, 0, 85, 64, // Skip to: 19091 -/* 2622 */ MCD_OPC_Decode, 218, 20, 205, 1, // Opcode: VSTRLR -/* 2627 */ MCD_OPC_FilterValue, 73, 21, 0, // Skip to: 2652 -/* 2631 */ MCD_OPC_CheckPredicate, 21, 72, 64, // Skip to: 19091 -/* 2635 */ MCD_OPC_CheckField, 32, 4, 0, 66, 64, // Skip to: 19091 -/* 2641 */ MCD_OPC_CheckField, 8, 3, 0, 60, 64, // Skip to: 19091 -/* 2647 */ MCD_OPC_Decode, 128, 19, 206, 1, // Opcode: VLIP -/* 2652 */ MCD_OPC_FilterValue, 80, 27, 0, // Skip to: 2683 -/* 2656 */ MCD_OPC_CheckPredicate, 21, 47, 64, // Skip to: 19091 -/* 2660 */ MCD_OPC_CheckField, 24, 8, 0, 41, 64, // Skip to: 19091 -/* 2666 */ MCD_OPC_CheckField, 11, 9, 0, 35, 64, // Skip to: 19091 -/* 2672 */ MCD_OPC_CheckField, 8, 2, 0, 29, 64, // Skip to: 19091 -/* 2678 */ MCD_OPC_Decode, 157, 17, 207, 1, // Opcode: VCVB -/* 2683 */ MCD_OPC_FilterValue, 82, 27, 0, // Skip to: 2714 -/* 2687 */ MCD_OPC_CheckPredicate, 21, 16, 64, // Skip to: 19091 -/* 2691 */ MCD_OPC_CheckField, 24, 8, 0, 10, 64, // Skip to: 19091 -/* 2697 */ MCD_OPC_CheckField, 11, 9, 0, 4, 64, // Skip to: 19091 -/* 2703 */ MCD_OPC_CheckField, 8, 2, 0, 254, 63, // Skip to: 19091 -/* 2709 */ MCD_OPC_Decode, 158, 17, 208, 1, // Opcode: VCVBG -/* 2714 */ MCD_OPC_FilterValue, 88, 21, 0, // Skip to: 2739 -/* 2718 */ MCD_OPC_CheckPredicate, 21, 241, 63, // Skip to: 19091 -/* 2722 */ MCD_OPC_CheckField, 24, 8, 0, 235, 63, // Skip to: 19091 -/* 2728 */ MCD_OPC_CheckField, 8, 3, 0, 229, 63, // Skip to: 19091 -/* 2734 */ MCD_OPC_Decode, 159, 17, 209, 1, // Opcode: VCVD -/* 2739 */ MCD_OPC_FilterValue, 89, 15, 0, // Skip to: 2758 -/* 2743 */ MCD_OPC_CheckPredicate, 21, 216, 63, // Skip to: 19091 -/* 2747 */ MCD_OPC_CheckField, 8, 2, 0, 210, 63, // Skip to: 19091 -/* 2753 */ MCD_OPC_Decode, 196, 20, 210, 1, // Opcode: VSRP -/* 2758 */ MCD_OPC_FilterValue, 90, 21, 0, // Skip to: 2783 -/* 2762 */ MCD_OPC_CheckPredicate, 21, 197, 63, // Skip to: 19091 -/* 2766 */ MCD_OPC_CheckField, 24, 8, 0, 191, 63, // Skip to: 19091 -/* 2772 */ MCD_OPC_CheckField, 8, 3, 0, 185, 63, // Skip to: 19091 -/* 2778 */ MCD_OPC_Decode, 160, 17, 211, 1, // Opcode: VCVDG -/* 2783 */ MCD_OPC_FilterValue, 91, 15, 0, // Skip to: 2802 -/* 2787 */ MCD_OPC_CheckPredicate, 21, 172, 63, // Skip to: 19091 -/* 2791 */ MCD_OPC_CheckField, 8, 2, 0, 166, 63, // Skip to: 19091 -/* 2797 */ MCD_OPC_Decode, 152, 20, 210, 1, // Opcode: VPSOP -/* 2802 */ MCD_OPC_FilterValue, 95, 27, 0, // Skip to: 2833 -/* 2806 */ MCD_OPC_CheckPredicate, 21, 153, 63, // Skip to: 19091 -/* 2810 */ MCD_OPC_CheckField, 36, 4, 0, 147, 63, // Skip to: 19091 -/* 2816 */ MCD_OPC_CheckField, 11, 21, 0, 141, 63, // Skip to: 19091 -/* 2822 */ MCD_OPC_CheckField, 8, 2, 0, 135, 63, // Skip to: 19091 -/* 2828 */ MCD_OPC_Decode, 229, 20, 212, 1, // Opcode: VTP -/* 2833 */ MCD_OPC_FilterValue, 113, 21, 0, // Skip to: 2858 -/* 2837 */ MCD_OPC_CheckPredicate, 21, 122, 63, // Skip to: 19091 -/* 2841 */ MCD_OPC_CheckField, 24, 4, 0, 116, 63, // Skip to: 19091 -/* 2847 */ MCD_OPC_CheckField, 8, 1, 0, 110, 63, // Skip to: 19091 -/* 2853 */ MCD_OPC_Decode, 225, 16, 213, 1, // Opcode: VAP -/* 2858 */ MCD_OPC_FilterValue, 115, 21, 0, // Skip to: 2883 -/* 2862 */ MCD_OPC_CheckPredicate, 21, 97, 63, // Skip to: 19091 -/* 2866 */ MCD_OPC_CheckField, 24, 4, 0, 91, 63, // Skip to: 19091 -/* 2872 */ MCD_OPC_CheckField, 8, 1, 0, 85, 63, // Skip to: 19091 -/* 2878 */ MCD_OPC_Decode, 190, 20, 213, 1, // Opcode: VSP -/* 2883 */ MCD_OPC_FilterValue, 119, 33, 0, // Skip to: 2920 -/* 2887 */ MCD_OPC_CheckPredicate, 21, 72, 63, // Skip to: 19091 -/* 2891 */ MCD_OPC_CheckField, 36, 4, 0, 66, 63, // Skip to: 19091 -/* 2897 */ MCD_OPC_CheckField, 24, 4, 0, 60, 63, // Skip to: 19091 -/* 2903 */ MCD_OPC_CheckField, 11, 9, 0, 54, 63, // Skip to: 19091 -/* 2909 */ MCD_OPC_CheckField, 8, 1, 0, 48, 63, // Skip to: 19091 -/* 2915 */ MCD_OPC_Decode, 151, 17, 214, 1, // Opcode: VCP -/* 2920 */ MCD_OPC_FilterValue, 120, 21, 0, // Skip to: 2945 -/* 2924 */ MCD_OPC_CheckPredicate, 21, 35, 63, // Skip to: 19091 -/* 2928 */ MCD_OPC_CheckField, 24, 4, 0, 29, 63, // Skip to: 19091 -/* 2934 */ MCD_OPC_CheckField, 8, 1, 0, 23, 63, // Skip to: 19091 -/* 2940 */ MCD_OPC_Decode, 222, 19, 213, 1, // Opcode: VMP -/* 2945 */ MCD_OPC_FilterValue, 121, 21, 0, // Skip to: 2970 -/* 2949 */ MCD_OPC_CheckPredicate, 21, 10, 63, // Skip to: 19091 -/* 2953 */ MCD_OPC_CheckField, 24, 4, 0, 4, 63, // Skip to: 19091 -/* 2959 */ MCD_OPC_CheckField, 8, 1, 0, 254, 62, // Skip to: 19091 -/* 2965 */ MCD_OPC_Decode, 235, 19, 213, 1, // Opcode: VMSP -/* 2970 */ MCD_OPC_FilterValue, 122, 21, 0, // Skip to: 2995 -/* 2974 */ MCD_OPC_CheckPredicate, 21, 241, 62, // Skip to: 19091 -/* 2978 */ MCD_OPC_CheckField, 24, 4, 0, 235, 62, // Skip to: 19091 -/* 2984 */ MCD_OPC_CheckField, 8, 1, 0, 229, 62, // Skip to: 19091 -/* 2990 */ MCD_OPC_Decode, 161, 17, 213, 1, // Opcode: VDP -/* 2995 */ MCD_OPC_FilterValue, 123, 21, 0, // Skip to: 3020 -/* 2999 */ MCD_OPC_CheckPredicate, 21, 216, 62, // Skip to: 19091 -/* 3003 */ MCD_OPC_CheckField, 24, 4, 0, 210, 62, // Skip to: 19091 -/* 3009 */ MCD_OPC_CheckField, 8, 1, 0, 204, 62, // Skip to: 19091 -/* 3015 */ MCD_OPC_Decode, 163, 20, 213, 1, // Opcode: VRP -/* 3020 */ MCD_OPC_FilterValue, 126, 195, 62, // Skip to: 19091 -/* 3024 */ MCD_OPC_CheckPredicate, 21, 191, 62, // Skip to: 19091 -/* 3028 */ MCD_OPC_CheckField, 24, 4, 0, 185, 62, // Skip to: 19091 -/* 3034 */ MCD_OPC_CheckField, 8, 1, 0, 179, 62, // Skip to: 19091 -/* 3040 */ MCD_OPC_Decode, 178, 20, 213, 1, // Opcode: VSDP -/* 3045 */ MCD_OPC_FilterValue, 231, 1, 216, 41, // Skip to: 13762 -/* 3050 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... -/* 3053 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 3072 -/* 3057 */ MCD_OPC_CheckPredicate, 22, 158, 62, // Skip to: 19091 -/* 3061 */ MCD_OPC_CheckField, 8, 3, 0, 152, 62, // Skip to: 19091 -/* 3067 */ MCD_OPC_Decode, 241, 18, 215, 1, // Opcode: VLEB -/* 3072 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 3091 -/* 3076 */ MCD_OPC_CheckPredicate, 22, 139, 62, // Skip to: 19091 -/* 3080 */ MCD_OPC_CheckField, 8, 3, 0, 133, 62, // Skip to: 19091 -/* 3086 */ MCD_OPC_Decode, 246, 18, 216, 1, // Opcode: VLEH -/* 3091 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 3110 -/* 3095 */ MCD_OPC_CheckPredicate, 22, 120, 62, // Skip to: 19091 -/* 3099 */ MCD_OPC_CheckField, 8, 3, 0, 114, 62, // Skip to: 19091 -/* 3105 */ MCD_OPC_Decode, 245, 18, 217, 1, // Opcode: VLEG -/* 3110 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 3129 -/* 3114 */ MCD_OPC_CheckPredicate, 22, 101, 62, // Skip to: 19091 -/* 3118 */ MCD_OPC_CheckField, 8, 3, 0, 95, 62, // Skip to: 19091 -/* 3124 */ MCD_OPC_Decode, 244, 18, 218, 1, // Opcode: VLEF -/* 3129 */ MCD_OPC_FilterValue, 4, 84, 0, // Skip to: 3217 -/* 3133 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 3136 */ MCD_OPC_FilterValue, 0, 79, 62, // Skip to: 19091 -/* 3140 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 3143 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3156 -/* 3147 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 3208 -/* 3151 */ MCD_OPC_Decode, 131, 19, 219, 1, // Opcode: VLLEZB -/* 3156 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3169 -/* 3160 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3208 -/* 3164 */ MCD_OPC_Decode, 134, 19, 219, 1, // Opcode: VLLEZH -/* 3169 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3182 -/* 3173 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3208 -/* 3177 */ MCD_OPC_Decode, 132, 19, 219, 1, // Opcode: VLLEZF -/* 3182 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3195 -/* 3186 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3208 -/* 3190 */ MCD_OPC_Decode, 133, 19, 219, 1, // Opcode: VLLEZG -/* 3195 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 3208 -/* 3199 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 3208 -/* 3203 */ MCD_OPC_Decode, 135, 19, 219, 1, // Opcode: VLLEZLF -/* 3208 */ MCD_OPC_CheckPredicate, 22, 7, 62, // Skip to: 19091 -/* 3212 */ MCD_OPC_Decode, 130, 19, 220, 1, // Opcode: VLLEZ -/* 3217 */ MCD_OPC_FilterValue, 5, 71, 0, // Skip to: 3292 -/* 3221 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 3224 */ MCD_OPC_FilterValue, 0, 247, 61, // Skip to: 19091 -/* 3228 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 3231 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3244 -/* 3235 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3283 -/* 3239 */ MCD_OPC_Decode, 144, 19, 219, 1, // Opcode: VLREPB -/* 3244 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3257 -/* 3248 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3283 -/* 3252 */ MCD_OPC_Decode, 147, 19, 219, 1, // Opcode: VLREPH -/* 3257 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3270 -/* 3261 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3283 -/* 3265 */ MCD_OPC_Decode, 145, 19, 219, 1, // Opcode: VLREPF -/* 3270 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3283 -/* 3274 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3283 -/* 3278 */ MCD_OPC_Decode, 146, 19, 219, 1, // Opcode: VLREPG -/* 3283 */ MCD_OPC_CheckPredicate, 22, 188, 61, // Skip to: 19091 -/* 3287 */ MCD_OPC_Decode, 143, 19, 220, 1, // Opcode: VLREP -/* 3292 */ MCD_OPC_FilterValue, 6, 21, 0, // Skip to: 3317 -/* 3296 */ MCD_OPC_CheckPredicate, 22, 175, 61, // Skip to: 19091 -/* 3300 */ MCD_OPC_CheckField, 12, 4, 0, 169, 61, // Skip to: 19091 -/* 3306 */ MCD_OPC_CheckField, 8, 3, 0, 163, 61, // Skip to: 19091 -/* 3312 */ MCD_OPC_Decode, 232, 18, 219, 1, // Opcode: VL -/* 3317 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 3336 -/* 3321 */ MCD_OPC_CheckPredicate, 22, 150, 61, // Skip to: 19091 -/* 3325 */ MCD_OPC_CheckField, 8, 3, 0, 144, 61, // Skip to: 19091 -/* 3331 */ MCD_OPC_Decode, 233, 18, 220, 1, // Opcode: VLBB -/* 3336 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 3355 -/* 3340 */ MCD_OPC_CheckPredicate, 22, 131, 61, // Skip to: 19091 -/* 3344 */ MCD_OPC_CheckField, 8, 3, 0, 125, 61, // Skip to: 19091 -/* 3350 */ MCD_OPC_Decode, 198, 20, 220, 1, // Opcode: VSTEB -/* 3355 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 3374 -/* 3359 */ MCD_OPC_CheckPredicate, 22, 112, 61, // Skip to: 19091 -/* 3363 */ MCD_OPC_CheckField, 8, 3, 0, 106, 61, // Skip to: 19091 -/* 3369 */ MCD_OPC_Decode, 201, 20, 221, 1, // Opcode: VSTEH -/* 3374 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 3393 -/* 3378 */ MCD_OPC_CheckPredicate, 22, 93, 61, // Skip to: 19091 -/* 3382 */ MCD_OPC_CheckField, 8, 3, 0, 87, 61, // Skip to: 19091 -/* 3388 */ MCD_OPC_Decode, 200, 20, 222, 1, // Opcode: VSTEG -/* 3393 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 3412 -/* 3397 */ MCD_OPC_CheckPredicate, 22, 74, 61, // Skip to: 19091 -/* 3401 */ MCD_OPC_CheckField, 8, 3, 0, 68, 61, // Skip to: 19091 -/* 3407 */ MCD_OPC_Decode, 199, 20, 223, 1, // Opcode: VSTEF -/* 3412 */ MCD_OPC_FilterValue, 14, 21, 0, // Skip to: 3437 -/* 3416 */ MCD_OPC_CheckPredicate, 22, 55, 61, // Skip to: 19091 -/* 3420 */ MCD_OPC_CheckField, 12, 4, 0, 49, 61, // Skip to: 19091 -/* 3426 */ MCD_OPC_CheckField, 8, 3, 0, 43, 61, // Skip to: 19091 -/* 3432 */ MCD_OPC_Decode, 197, 20, 219, 1, // Opcode: VST -/* 3437 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 3456 -/* 3441 */ MCD_OPC_CheckPredicate, 22, 30, 61, // Skip to: 19091 -/* 3445 */ MCD_OPC_CheckField, 8, 2, 0, 24, 61, // Skip to: 19091 -/* 3451 */ MCD_OPC_Decode, 209, 18, 224, 1, // Opcode: VGEG -/* 3456 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 3475 -/* 3460 */ MCD_OPC_CheckPredicate, 22, 11, 61, // Skip to: 19091 -/* 3464 */ MCD_OPC_CheckField, 8, 2, 0, 5, 61, // Skip to: 19091 -/* 3470 */ MCD_OPC_Decode, 208, 18, 225, 1, // Opcode: VGEF -/* 3475 */ MCD_OPC_FilterValue, 26, 15, 0, // Skip to: 3494 -/* 3479 */ MCD_OPC_CheckPredicate, 22, 248, 60, // Skip to: 19091 -/* 3483 */ MCD_OPC_CheckField, 8, 2, 0, 242, 60, // Skip to: 19091 -/* 3489 */ MCD_OPC_Decode, 177, 20, 226, 1, // Opcode: VSCEG -/* 3494 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 3513 -/* 3498 */ MCD_OPC_CheckPredicate, 22, 229, 60, // Skip to: 19091 -/* 3502 */ MCD_OPC_CheckField, 8, 2, 0, 223, 60, // Skip to: 19091 -/* 3508 */ MCD_OPC_Decode, 176, 20, 227, 1, // Opcode: VSCEF -/* 3513 */ MCD_OPC_FilterValue, 33, 78, 0, // Skip to: 3595 -/* 3517 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 3520 */ MCD_OPC_FilterValue, 0, 207, 60, // Skip to: 19091 -/* 3524 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 3527 */ MCD_OPC_FilterValue, 0, 200, 60, // Skip to: 19091 -/* 3531 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 3534 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3547 -/* 3538 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3586 -/* 3542 */ MCD_OPC_Decode, 252, 18, 228, 1, // Opcode: VLGVB -/* 3547 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3560 -/* 3551 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3586 -/* 3555 */ MCD_OPC_Decode, 255, 18, 228, 1, // Opcode: VLGVH -/* 3560 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3573 -/* 3564 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3586 -/* 3568 */ MCD_OPC_Decode, 253, 18, 228, 1, // Opcode: VLGVF -/* 3573 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3586 -/* 3577 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3586 -/* 3581 */ MCD_OPC_Decode, 254, 18, 228, 1, // Opcode: VLGVG -/* 3586 */ MCD_OPC_CheckPredicate, 22, 141, 60, // Skip to: 19091 -/* 3590 */ MCD_OPC_Decode, 251, 18, 229, 1, // Opcode: VLGV -/* 3595 */ MCD_OPC_FilterValue, 34, 71, 0, // Skip to: 3670 -/* 3599 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 3602 */ MCD_OPC_FilterValue, 0, 125, 60, // Skip to: 19091 -/* 3606 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 3609 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3622 -/* 3613 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3661 -/* 3617 */ MCD_OPC_Decode, 151, 19, 230, 1, // Opcode: VLVGB -/* 3622 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3635 -/* 3626 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3661 -/* 3630 */ MCD_OPC_Decode, 154, 19, 230, 1, // Opcode: VLVGH -/* 3635 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3648 -/* 3639 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3661 -/* 3643 */ MCD_OPC_Decode, 152, 19, 230, 1, // Opcode: VLVGF -/* 3648 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3661 -/* 3652 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3661 -/* 3656 */ MCD_OPC_Decode, 153, 19, 231, 1, // Opcode: VLVGG -/* 3661 */ MCD_OPC_CheckPredicate, 22, 66, 60, // Skip to: 19091 -/* 3665 */ MCD_OPC_Decode, 150, 19, 232, 1, // Opcode: VLVG -/* 3670 */ MCD_OPC_FilterValue, 39, 15, 0, // Skip to: 3689 -/* 3674 */ MCD_OPC_CheckPredicate, 22, 53, 60, // Skip to: 19091 -/* 3678 */ MCD_OPC_CheckField, 8, 4, 0, 47, 60, // Skip to: 19091 -/* 3684 */ MCD_OPC_Decode, 131, 10, 233, 1, // Opcode: LCBB -/* 3689 */ MCD_OPC_FilterValue, 48, 71, 0, // Skip to: 3764 -/* 3693 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 3696 */ MCD_OPC_FilterValue, 0, 31, 60, // Skip to: 19091 -/* 3700 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 3703 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3716 -/* 3707 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3755 -/* 3711 */ MCD_OPC_Decode, 188, 17, 234, 1, // Opcode: VESLB -/* 3716 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3729 -/* 3720 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3755 -/* 3724 */ MCD_OPC_Decode, 191, 17, 234, 1, // Opcode: VESLH -/* 3729 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3742 -/* 3733 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3755 -/* 3737 */ MCD_OPC_Decode, 189, 17, 234, 1, // Opcode: VESLF -/* 3742 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3755 -/* 3746 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3755 -/* 3750 */ MCD_OPC_Decode, 190, 17, 234, 1, // Opcode: VESLG -/* 3755 */ MCD_OPC_CheckPredicate, 22, 228, 59, // Skip to: 19091 -/* 3759 */ MCD_OPC_Decode, 187, 17, 235, 1, // Opcode: VESL -/* 3764 */ MCD_OPC_FilterValue, 51, 71, 0, // Skip to: 3839 -/* 3768 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 3771 */ MCD_OPC_FilterValue, 0, 212, 59, // Skip to: 19091 -/* 3775 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 3778 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3791 -/* 3782 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3830 -/* 3786 */ MCD_OPC_Decode, 178, 17, 234, 1, // Opcode: VERLLB -/* 3791 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3804 -/* 3795 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3830 -/* 3799 */ MCD_OPC_Decode, 181, 17, 234, 1, // Opcode: VERLLH -/* 3804 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3817 -/* 3808 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3830 -/* 3812 */ MCD_OPC_Decode, 179, 17, 234, 1, // Opcode: VERLLF -/* 3817 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3830 -/* 3821 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3830 -/* 3825 */ MCD_OPC_Decode, 180, 17, 234, 1, // Opcode: VERLLG -/* 3830 */ MCD_OPC_CheckPredicate, 22, 153, 59, // Skip to: 19091 -/* 3834 */ MCD_OPC_Decode, 177, 17, 235, 1, // Opcode: VERLL -/* 3839 */ MCD_OPC_FilterValue, 54, 21, 0, // Skip to: 3864 -/* 3843 */ MCD_OPC_CheckPredicate, 22, 140, 59, // Skip to: 19091 -/* 3847 */ MCD_OPC_CheckField, 12, 4, 0, 134, 59, // Skip to: 19091 -/* 3853 */ MCD_OPC_CheckField, 8, 2, 0, 128, 59, // Skip to: 19091 -/* 3859 */ MCD_OPC_Decode, 136, 19, 236, 1, // Opcode: VLM -/* 3864 */ MCD_OPC_FilterValue, 55, 21, 0, // Skip to: 3889 -/* 3868 */ MCD_OPC_CheckPredicate, 22, 115, 59, // Skip to: 19091 -/* 3872 */ MCD_OPC_CheckField, 12, 4, 0, 109, 59, // Skip to: 19091 -/* 3878 */ MCD_OPC_CheckField, 8, 3, 0, 103, 59, // Skip to: 19091 -/* 3884 */ MCD_OPC_Decode, 129, 19, 237, 1, // Opcode: VLL -/* 3889 */ MCD_OPC_FilterValue, 56, 71, 0, // Skip to: 3964 -/* 3893 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 3896 */ MCD_OPC_FilterValue, 0, 87, 59, // Skip to: 19091 -/* 3900 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 3903 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3916 -/* 3907 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3955 -/* 3911 */ MCD_OPC_Decode, 208, 17, 234, 1, // Opcode: VESRLB -/* 3916 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3929 -/* 3920 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3955 -/* 3924 */ MCD_OPC_Decode, 211, 17, 234, 1, // Opcode: VESRLH -/* 3929 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3942 -/* 3933 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3955 -/* 3937 */ MCD_OPC_Decode, 209, 17, 234, 1, // Opcode: VESRLF -/* 3942 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3955 -/* 3946 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3955 -/* 3950 */ MCD_OPC_Decode, 210, 17, 234, 1, // Opcode: VESRLG -/* 3955 */ MCD_OPC_CheckPredicate, 22, 28, 59, // Skip to: 19091 -/* 3959 */ MCD_OPC_Decode, 207, 17, 235, 1, // Opcode: VESRL -/* 3964 */ MCD_OPC_FilterValue, 58, 71, 0, // Skip to: 4039 -/* 3968 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 3971 */ MCD_OPC_FilterValue, 0, 12, 59, // Skip to: 19091 -/* 3975 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 3978 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3991 -/* 3982 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4030 -/* 3986 */ MCD_OPC_Decode, 198, 17, 234, 1, // Opcode: VESRAB -/* 3991 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4004 -/* 3995 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4030 -/* 3999 */ MCD_OPC_Decode, 201, 17, 234, 1, // Opcode: VESRAH -/* 4004 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4017 -/* 4008 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4030 -/* 4012 */ MCD_OPC_Decode, 199, 17, 234, 1, // Opcode: VESRAF -/* 4017 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4030 -/* 4021 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4030 -/* 4025 */ MCD_OPC_Decode, 200, 17, 234, 1, // Opcode: VESRAG -/* 4030 */ MCD_OPC_CheckPredicate, 22, 209, 58, // Skip to: 19091 -/* 4034 */ MCD_OPC_Decode, 197, 17, 235, 1, // Opcode: VESRA -/* 4039 */ MCD_OPC_FilterValue, 62, 21, 0, // Skip to: 4064 -/* 4043 */ MCD_OPC_CheckPredicate, 22, 196, 58, // Skip to: 19091 -/* 4047 */ MCD_OPC_CheckField, 12, 4, 0, 190, 58, // Skip to: 19091 -/* 4053 */ MCD_OPC_CheckField, 8, 2, 0, 184, 58, // Skip to: 19091 -/* 4059 */ MCD_OPC_Decode, 203, 20, 236, 1, // Opcode: VSTM -/* 4064 */ MCD_OPC_FilterValue, 63, 21, 0, // Skip to: 4089 -/* 4068 */ MCD_OPC_CheckPredicate, 22, 171, 58, // Skip to: 19091 -/* 4072 */ MCD_OPC_CheckField, 12, 4, 0, 165, 58, // Skip to: 19091 -/* 4078 */ MCD_OPC_CheckField, 8, 3, 0, 159, 58, // Skip to: 19091 -/* 4084 */ MCD_OPC_Decode, 202, 20, 237, 1, // Opcode: VSTL -/* 4089 */ MCD_OPC_FilterValue, 64, 21, 0, // Skip to: 4114 -/* 4093 */ MCD_OPC_CheckPredicate, 22, 146, 58, // Skip to: 19091 -/* 4097 */ MCD_OPC_CheckField, 32, 4, 0, 140, 58, // Skip to: 19091 -/* 4103 */ MCD_OPC_CheckField, 8, 3, 0, 134, 58, // Skip to: 19091 -/* 4109 */ MCD_OPC_Decode, 247, 18, 238, 1, // Opcode: VLEIB -/* 4114 */ MCD_OPC_FilterValue, 65, 21, 0, // Skip to: 4139 -/* 4118 */ MCD_OPC_CheckPredicate, 22, 121, 58, // Skip to: 19091 -/* 4122 */ MCD_OPC_CheckField, 32, 4, 0, 115, 58, // Skip to: 19091 -/* 4128 */ MCD_OPC_CheckField, 8, 3, 0, 109, 58, // Skip to: 19091 -/* 4134 */ MCD_OPC_Decode, 250, 18, 239, 1, // Opcode: VLEIH -/* 4139 */ MCD_OPC_FilterValue, 66, 21, 0, // Skip to: 4164 -/* 4143 */ MCD_OPC_CheckPredicate, 22, 96, 58, // Skip to: 19091 -/* 4147 */ MCD_OPC_CheckField, 32, 4, 0, 90, 58, // Skip to: 19091 -/* 4153 */ MCD_OPC_CheckField, 8, 3, 0, 84, 58, // Skip to: 19091 -/* 4159 */ MCD_OPC_Decode, 249, 18, 240, 1, // Opcode: VLEIG -/* 4164 */ MCD_OPC_FilterValue, 67, 21, 0, // Skip to: 4189 -/* 4168 */ MCD_OPC_CheckPredicate, 22, 71, 58, // Skip to: 19091 -/* 4172 */ MCD_OPC_CheckField, 32, 4, 0, 65, 58, // Skip to: 19091 -/* 4178 */ MCD_OPC_CheckField, 8, 3, 0, 59, 58, // Skip to: 19091 -/* 4184 */ MCD_OPC_Decode, 248, 18, 241, 1, // Opcode: VLEIF -/* 4189 */ MCD_OPC_FilterValue, 68, 61, 0, // Skip to: 4254 -/* 4193 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 4196 */ MCD_OPC_FilterValue, 0, 43, 58, // Skip to: 19091 -/* 4200 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4203 */ MCD_OPC_FilterValue, 0, 36, 58, // Skip to: 19091 -/* 4207 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 4210 */ MCD_OPC_FilterValue, 0, 29, 58, // Skip to: 19091 -/* 4214 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 4217 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4230 -/* 4221 */ MCD_OPC_CheckPredicate, 22, 20, 0, // Skip to: 4245 -/* 4225 */ MCD_OPC_Decode, 248, 20, 242, 1, // Opcode: VZERO -/* 4230 */ MCD_OPC_FilterValue, 255, 255, 3, 9, 0, // Skip to: 4245 -/* 4236 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4245 -/* 4240 */ MCD_OPC_Decode, 253, 19, 242, 1, // Opcode: VONE -/* 4245 */ MCD_OPC_CheckPredicate, 22, 250, 57, // Skip to: 19091 -/* 4249 */ MCD_OPC_Decode, 207, 18, 243, 1, // Opcode: VGBM -/* 4254 */ MCD_OPC_FilterValue, 69, 78, 0, // Skip to: 4336 -/* 4258 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 4261 */ MCD_OPC_FilterValue, 0, 234, 57, // Skip to: 19091 -/* 4265 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 4268 */ MCD_OPC_FilterValue, 0, 227, 57, // Skip to: 19091 -/* 4272 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4275 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4288 -/* 4279 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4327 -/* 4283 */ MCD_OPC_Decode, 159, 20, 244, 1, // Opcode: VREPIB -/* 4288 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4301 -/* 4292 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4327 -/* 4296 */ MCD_OPC_Decode, 162, 20, 244, 1, // Opcode: VREPIH -/* 4301 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4314 -/* 4305 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4327 -/* 4309 */ MCD_OPC_Decode, 160, 20, 244, 1, // Opcode: VREPIF -/* 4314 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4327 -/* 4318 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4327 -/* 4322 */ MCD_OPC_Decode, 161, 20, 244, 1, // Opcode: VREPIG -/* 4327 */ MCD_OPC_CheckPredicate, 22, 168, 57, // Skip to: 19091 -/* 4331 */ MCD_OPC_Decode, 158, 20, 245, 1, // Opcode: VREPI -/* 4336 */ MCD_OPC_FilterValue, 70, 78, 0, // Skip to: 4418 -/* 4340 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 4343 */ MCD_OPC_FilterValue, 0, 152, 57, // Skip to: 19091 -/* 4347 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 4350 */ MCD_OPC_FilterValue, 0, 145, 57, // Skip to: 19091 -/* 4354 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4357 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4370 -/* 4361 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4409 -/* 4365 */ MCD_OPC_Decode, 221, 18, 246, 1, // Opcode: VGMB -/* 4370 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4383 -/* 4374 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4409 -/* 4378 */ MCD_OPC_Decode, 224, 18, 246, 1, // Opcode: VGMH -/* 4383 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4396 -/* 4387 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4409 -/* 4391 */ MCD_OPC_Decode, 222, 18, 246, 1, // Opcode: VGMF -/* 4396 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4409 -/* 4400 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4409 -/* 4404 */ MCD_OPC_Decode, 223, 18, 246, 1, // Opcode: VGMG -/* 4409 */ MCD_OPC_CheckPredicate, 22, 86, 57, // Skip to: 19091 -/* 4413 */ MCD_OPC_Decode, 220, 18, 247, 1, // Opcode: VGM -/* 4418 */ MCD_OPC_FilterValue, 74, 87, 0, // Skip to: 4509 -/* 4422 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 4425 */ MCD_OPC_FilterValue, 0, 70, 57, // Skip to: 19091 -/* 4429 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 4432 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4445 -/* 4436 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 4500 -/* 4440 */ MCD_OPC_Decode, 206, 18, 248, 1, // Opcode: VFTCISB -/* 4445 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4458 -/* 4449 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 4500 -/* 4453 */ MCD_OPC_Decode, 205, 18, 248, 1, // Opcode: VFTCIDB -/* 4458 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 4472 -/* 4463 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 4500 -/* 4467 */ MCD_OPC_Decode, 222, 21, 249, 1, // Opcode: WFTCISB -/* 4472 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 4486 -/* 4477 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 4500 -/* 4481 */ MCD_OPC_Decode, 221, 21, 250, 1, // Opcode: WFTCIDB -/* 4486 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 4500 -/* 4491 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 4500 -/* 4495 */ MCD_OPC_Decode, 223, 21, 248, 1, // Opcode: WFTCIXB -/* 4500 */ MCD_OPC_CheckPredicate, 22, 251, 56, // Skip to: 19091 -/* 4504 */ MCD_OPC_Decode, 204, 18, 251, 1, // Opcode: VFTCI -/* 4509 */ MCD_OPC_FilterValue, 77, 71, 0, // Skip to: 4584 -/* 4513 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 4516 */ MCD_OPC_FilterValue, 0, 235, 56, // Skip to: 19091 -/* 4520 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4523 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4536 -/* 4527 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4575 -/* 4531 */ MCD_OPC_Decode, 154, 20, 252, 1, // Opcode: VREPB -/* 4536 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4549 -/* 4540 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4575 -/* 4544 */ MCD_OPC_Decode, 157, 20, 252, 1, // Opcode: VREPH -/* 4549 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4562 -/* 4553 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4575 -/* 4557 */ MCD_OPC_Decode, 155, 20, 252, 1, // Opcode: VREPF -/* 4562 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4575 -/* 4566 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4575 -/* 4570 */ MCD_OPC_Decode, 156, 20, 252, 1, // Opcode: VREPG -/* 4575 */ MCD_OPC_CheckPredicate, 22, 176, 56, // Skip to: 19091 -/* 4579 */ MCD_OPC_Decode, 153, 20, 253, 1, // Opcode: VREP -/* 4584 */ MCD_OPC_FilterValue, 80, 78, 0, // Skip to: 4666 -/* 4588 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 4591 */ MCD_OPC_FilterValue, 0, 160, 56, // Skip to: 19091 -/* 4595 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 4598 */ MCD_OPC_FilterValue, 0, 153, 56, // Skip to: 19091 -/* 4602 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4605 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4618 -/* 4609 */ MCD_OPC_CheckPredicate, 23, 44, 0, // Skip to: 4657 -/* 4613 */ MCD_OPC_Decode, 148, 20, 254, 1, // Opcode: VPOPCTB -/* 4618 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4631 -/* 4622 */ MCD_OPC_CheckPredicate, 23, 31, 0, // Skip to: 4657 -/* 4626 */ MCD_OPC_Decode, 151, 20, 254, 1, // Opcode: VPOPCTH -/* 4631 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4644 -/* 4635 */ MCD_OPC_CheckPredicate, 23, 18, 0, // Skip to: 4657 -/* 4639 */ MCD_OPC_Decode, 149, 20, 254, 1, // Opcode: VPOPCTF -/* 4644 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4657 -/* 4648 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 4657 -/* 4652 */ MCD_OPC_Decode, 150, 20, 254, 1, // Opcode: VPOPCTG -/* 4657 */ MCD_OPC_CheckPredicate, 22, 94, 56, // Skip to: 19091 -/* 4661 */ MCD_OPC_Decode, 147, 20, 255, 1, // Opcode: VPOPCT -/* 4666 */ MCD_OPC_FilterValue, 82, 78, 0, // Skip to: 4748 -/* 4670 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 4673 */ MCD_OPC_FilterValue, 0, 78, 56, // Skip to: 19091 -/* 4677 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 4680 */ MCD_OPC_FilterValue, 0, 71, 56, // Skip to: 19091 -/* 4684 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4687 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4700 -/* 4691 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4739 -/* 4695 */ MCD_OPC_Decode, 153, 17, 254, 1, // Opcode: VCTZB -/* 4700 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4713 -/* 4704 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4739 -/* 4708 */ MCD_OPC_Decode, 156, 17, 254, 1, // Opcode: VCTZH -/* 4713 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4726 -/* 4717 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4739 -/* 4721 */ MCD_OPC_Decode, 154, 17, 254, 1, // Opcode: VCTZF -/* 4726 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4739 -/* 4730 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4739 -/* 4734 */ MCD_OPC_Decode, 155, 17, 254, 1, // Opcode: VCTZG -/* 4739 */ MCD_OPC_CheckPredicate, 22, 12, 56, // Skip to: 19091 -/* 4743 */ MCD_OPC_Decode, 152, 17, 255, 1, // Opcode: VCTZ -/* 4748 */ MCD_OPC_FilterValue, 83, 78, 0, // Skip to: 4830 -/* 4752 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 4755 */ MCD_OPC_FilterValue, 0, 252, 55, // Skip to: 19091 -/* 4759 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 4762 */ MCD_OPC_FilterValue, 0, 245, 55, // Skip to: 19091 -/* 4766 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4769 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4782 -/* 4773 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4821 -/* 4777 */ MCD_OPC_Decode, 147, 17, 254, 1, // Opcode: VCLZB -/* 4782 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4795 -/* 4786 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4821 -/* 4790 */ MCD_OPC_Decode, 150, 17, 254, 1, // Opcode: VCLZH -/* 4795 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4808 -/* 4799 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4821 -/* 4803 */ MCD_OPC_Decode, 148, 17, 254, 1, // Opcode: VCLZF -/* 4808 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4821 -/* 4812 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4821 -/* 4816 */ MCD_OPC_Decode, 149, 17, 254, 1, // Opcode: VCLZG -/* 4821 */ MCD_OPC_CheckPredicate, 22, 186, 55, // Skip to: 19091 -/* 4825 */ MCD_OPC_Decode, 146, 17, 255, 1, // Opcode: VCLZ -/* 4830 */ MCD_OPC_FilterValue, 86, 21, 0, // Skip to: 4855 -/* 4834 */ MCD_OPC_CheckPredicate, 22, 173, 55, // Skip to: 19091 -/* 4838 */ MCD_OPC_CheckField, 12, 20, 0, 167, 55, // Skip to: 19091 -/* 4844 */ MCD_OPC_CheckField, 8, 2, 0, 161, 55, // Skip to: 19091 -/* 4850 */ MCD_OPC_Decode, 142, 19, 254, 1, // Opcode: VLR -/* 4855 */ MCD_OPC_FilterValue, 92, 117, 0, // Skip to: 4976 -/* 4859 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 4862 */ MCD_OPC_FilterValue, 0, 145, 55, // Skip to: 19091 -/* 4866 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 4869 */ MCD_OPC_FilterValue, 0, 138, 55, // Skip to: 19091 -/* 4873 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 4876 */ MCD_OPC_FilterValue, 0, 131, 55, // Skip to: 19091 -/* 4880 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4883 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 4911 -/* 4887 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 4902 -/* 4891 */ MCD_OPC_CheckField, 20, 4, 1, 5, 0, // Skip to: 4902 -/* 4897 */ MCD_OPC_Decode, 227, 18, 254, 1, // Opcode: VISTRBS -/* 4902 */ MCD_OPC_CheckPredicate, 22, 61, 0, // Skip to: 4967 -/* 4906 */ MCD_OPC_Decode, 226, 18, 128, 2, // Opcode: VISTRB -/* 4911 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 4939 -/* 4915 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 4930 -/* 4919 */ MCD_OPC_CheckField, 20, 4, 1, 5, 0, // Skip to: 4930 -/* 4925 */ MCD_OPC_Decode, 231, 18, 254, 1, // Opcode: VISTRHS -/* 4930 */ MCD_OPC_CheckPredicate, 22, 33, 0, // Skip to: 4967 -/* 4934 */ MCD_OPC_Decode, 230, 18, 128, 2, // Opcode: VISTRH -/* 4939 */ MCD_OPC_FilterValue, 2, 24, 0, // Skip to: 4967 -/* 4943 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 4958 -/* 4947 */ MCD_OPC_CheckField, 20, 4, 1, 5, 0, // Skip to: 4958 -/* 4953 */ MCD_OPC_Decode, 229, 18, 254, 1, // Opcode: VISTRFS -/* 4958 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4967 -/* 4962 */ MCD_OPC_Decode, 228, 18, 128, 2, // Opcode: VISTRF -/* 4967 */ MCD_OPC_CheckPredicate, 22, 40, 55, // Skip to: 19091 -/* 4971 */ MCD_OPC_Decode, 225, 18, 129, 2, // Opcode: VISTR -/* 4976 */ MCD_OPC_FilterValue, 95, 65, 0, // Skip to: 5045 -/* 4980 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 4983 */ MCD_OPC_FilterValue, 0, 24, 55, // Skip to: 19091 -/* 4987 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 4990 */ MCD_OPC_FilterValue, 0, 17, 55, // Skip to: 19091 -/* 4994 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4997 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5010 -/* 5001 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5036 -/* 5005 */ MCD_OPC_Decode, 180, 20, 254, 1, // Opcode: VSEGB -/* 5010 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5023 -/* 5014 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5036 -/* 5018 */ MCD_OPC_Decode, 182, 20, 254, 1, // Opcode: VSEGH -/* 5023 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5036 -/* 5027 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5036 -/* 5031 */ MCD_OPC_Decode, 181, 20, 254, 1, // Opcode: VSEGF -/* 5036 */ MCD_OPC_CheckPredicate, 22, 227, 54, // Skip to: 19091 -/* 5040 */ MCD_OPC_Decode, 179, 20, 255, 1, // Opcode: VSEG -/* 5045 */ MCD_OPC_FilterValue, 96, 78, 0, // Skip to: 5127 -/* 5049 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5052 */ MCD_OPC_FilterValue, 0, 211, 54, // Skip to: 19091 -/* 5056 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 5059 */ MCD_OPC_FilterValue, 0, 204, 54, // Skip to: 19091 -/* 5063 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 5066 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5079 -/* 5070 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5118 -/* 5074 */ MCD_OPC_Decode, 229, 19, 130, 2, // Opcode: VMRLB -/* 5079 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5092 -/* 5083 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5118 -/* 5087 */ MCD_OPC_Decode, 232, 19, 130, 2, // Opcode: VMRLH -/* 5092 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5105 -/* 5096 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5118 -/* 5100 */ MCD_OPC_Decode, 230, 19, 130, 2, // Opcode: VMRLF -/* 5105 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5118 -/* 5109 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5118 -/* 5113 */ MCD_OPC_Decode, 231, 19, 130, 2, // Opcode: VMRLG -/* 5118 */ MCD_OPC_CheckPredicate, 22, 145, 54, // Skip to: 19091 -/* 5122 */ MCD_OPC_Decode, 228, 19, 131, 2, // Opcode: VMRL -/* 5127 */ MCD_OPC_FilterValue, 97, 78, 0, // Skip to: 5209 -/* 5131 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5134 */ MCD_OPC_FilterValue, 0, 129, 54, // Skip to: 19091 -/* 5138 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 5141 */ MCD_OPC_FilterValue, 0, 122, 54, // Skip to: 19091 -/* 5145 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 5148 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5161 -/* 5152 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5200 -/* 5156 */ MCD_OPC_Decode, 224, 19, 130, 2, // Opcode: VMRHB -/* 5161 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5174 -/* 5165 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5200 -/* 5169 */ MCD_OPC_Decode, 227, 19, 130, 2, // Opcode: VMRHH -/* 5174 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5187 -/* 5178 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5200 -/* 5182 */ MCD_OPC_Decode, 225, 19, 130, 2, // Opcode: VMRHF -/* 5187 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5200 -/* 5191 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5200 -/* 5195 */ MCD_OPC_Decode, 226, 19, 130, 2, // Opcode: VMRHG -/* 5200 */ MCD_OPC_CheckPredicate, 22, 63, 54, // Skip to: 19091 -/* 5204 */ MCD_OPC_Decode, 223, 19, 131, 2, // Opcode: VMRH -/* 5209 */ MCD_OPC_FilterValue, 98, 21, 0, // Skip to: 5234 -/* 5213 */ MCD_OPC_CheckPredicate, 22, 50, 54, // Skip to: 19091 -/* 5217 */ MCD_OPC_CheckField, 12, 16, 0, 44, 54, // Skip to: 19091 -/* 5223 */ MCD_OPC_CheckField, 8, 3, 0, 38, 54, // Skip to: 19091 -/* 5229 */ MCD_OPC_Decode, 155, 19, 132, 2, // Opcode: VLVGP -/* 5234 */ MCD_OPC_FilterValue, 100, 52, 0, // Skip to: 5290 -/* 5238 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5241 */ MCD_OPC_FilterValue, 0, 22, 54, // Skip to: 19091 -/* 5245 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 5248 */ MCD_OPC_FilterValue, 0, 15, 54, // Skip to: 19091 -/* 5252 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 5255 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5268 -/* 5259 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5281 -/* 5263 */ MCD_OPC_Decode, 220, 20, 130, 2, // Opcode: VSUMB -/* 5268 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5281 -/* 5272 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5281 -/* 5276 */ MCD_OPC_Decode, 224, 20, 130, 2, // Opcode: VSUMH -/* 5281 */ MCD_OPC_CheckPredicate, 22, 238, 53, // Skip to: 19091 -/* 5285 */ MCD_OPC_Decode, 219, 20, 131, 2, // Opcode: VSUM -/* 5290 */ MCD_OPC_FilterValue, 101, 52, 0, // Skip to: 5346 -/* 5294 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5297 */ MCD_OPC_FilterValue, 0, 222, 53, // Skip to: 19091 -/* 5301 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 5304 */ MCD_OPC_FilterValue, 0, 215, 53, // Skip to: 19091 -/* 5308 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 5311 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5324 -/* 5315 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5337 -/* 5319 */ MCD_OPC_Decode, 223, 20, 130, 2, // Opcode: VSUMGH -/* 5324 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5337 -/* 5328 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5337 -/* 5332 */ MCD_OPC_Decode, 222, 20, 130, 2, // Opcode: VSUMGF -/* 5337 */ MCD_OPC_CheckPredicate, 22, 182, 53, // Skip to: 19091 -/* 5341 */ MCD_OPC_Decode, 221, 20, 131, 2, // Opcode: VSUMG -/* 5346 */ MCD_OPC_FilterValue, 102, 21, 0, // Skip to: 5371 -/* 5350 */ MCD_OPC_CheckPredicate, 22, 169, 53, // Skip to: 19091 -/* 5354 */ MCD_OPC_CheckField, 12, 16, 0, 163, 53, // Skip to: 19091 -/* 5360 */ MCD_OPC_CheckField, 8, 1, 0, 157, 53, // Skip to: 19091 -/* 5366 */ MCD_OPC_Decode, 143, 17, 130, 2, // Opcode: VCKSM -/* 5371 */ MCD_OPC_FilterValue, 103, 52, 0, // Skip to: 5427 -/* 5375 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5378 */ MCD_OPC_FilterValue, 0, 141, 53, // Skip to: 19091 -/* 5382 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 5385 */ MCD_OPC_FilterValue, 0, 134, 53, // Skip to: 19091 -/* 5389 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 5392 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5405 -/* 5396 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5418 -/* 5400 */ MCD_OPC_Decode, 226, 20, 130, 2, // Opcode: VSUMQF -/* 5405 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5418 -/* 5409 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5418 -/* 5413 */ MCD_OPC_Decode, 227, 20, 130, 2, // Opcode: VSUMQG -/* 5418 */ MCD_OPC_CheckPredicate, 22, 101, 53, // Skip to: 19091 -/* 5422 */ MCD_OPC_Decode, 225, 20, 131, 2, // Opcode: VSUMQ -/* 5427 */ MCD_OPC_FilterValue, 104, 21, 0, // Skip to: 5452 -/* 5431 */ MCD_OPC_CheckPredicate, 22, 88, 53, // Skip to: 19091 -/* 5435 */ MCD_OPC_CheckField, 12, 16, 0, 82, 53, // Skip to: 19091 -/* 5441 */ MCD_OPC_CheckField, 8, 1, 0, 76, 53, // Skip to: 19091 -/* 5447 */ MCD_OPC_Decode, 246, 19, 130, 2, // Opcode: VN -/* 5452 */ MCD_OPC_FilterValue, 105, 21, 0, // Skip to: 5477 -/* 5456 */ MCD_OPC_CheckPredicate, 22, 63, 53, // Skip to: 19091 -/* 5460 */ MCD_OPC_CheckField, 12, 16, 0, 57, 53, // Skip to: 19091 -/* 5466 */ MCD_OPC_CheckField, 8, 1, 0, 51, 53, // Skip to: 19091 -/* 5472 */ MCD_OPC_Decode, 247, 19, 130, 2, // Opcode: VNC -/* 5477 */ MCD_OPC_FilterValue, 106, 21, 0, // Skip to: 5502 -/* 5481 */ MCD_OPC_CheckPredicate, 22, 38, 53, // Skip to: 19091 -/* 5485 */ MCD_OPC_CheckField, 12, 16, 0, 32, 53, // Skip to: 19091 -/* 5491 */ MCD_OPC_CheckField, 8, 1, 0, 26, 53, // Skip to: 19091 -/* 5497 */ MCD_OPC_Decode, 251, 19, 130, 2, // Opcode: VO -/* 5502 */ MCD_OPC_FilterValue, 107, 21, 0, // Skip to: 5527 -/* 5506 */ MCD_OPC_CheckPredicate, 22, 13, 53, // Skip to: 19091 -/* 5510 */ MCD_OPC_CheckField, 12, 16, 0, 7, 53, // Skip to: 19091 -/* 5516 */ MCD_OPC_CheckField, 8, 1, 0, 1, 53, // Skip to: 19091 -/* 5522 */ MCD_OPC_Decode, 249, 19, 130, 2, // Opcode: VNO -/* 5527 */ MCD_OPC_FilterValue, 108, 21, 0, // Skip to: 5552 -/* 5531 */ MCD_OPC_CheckPredicate, 23, 244, 52, // Skip to: 19091 -/* 5535 */ MCD_OPC_CheckField, 12, 16, 0, 238, 52, // Skip to: 19091 -/* 5541 */ MCD_OPC_CheckField, 8, 1, 0, 232, 52, // Skip to: 19091 -/* 5547 */ MCD_OPC_Decode, 250, 19, 130, 2, // Opcode: VNX -/* 5552 */ MCD_OPC_FilterValue, 109, 21, 0, // Skip to: 5577 -/* 5556 */ MCD_OPC_CheckPredicate, 22, 219, 52, // Skip to: 19091 -/* 5560 */ MCD_OPC_CheckField, 12, 16, 0, 213, 52, // Skip to: 19091 -/* 5566 */ MCD_OPC_CheckField, 8, 1, 0, 207, 52, // Skip to: 19091 -/* 5572 */ MCD_OPC_Decode, 247, 20, 130, 2, // Opcode: VX -/* 5577 */ MCD_OPC_FilterValue, 110, 21, 0, // Skip to: 5602 -/* 5581 */ MCD_OPC_CheckPredicate, 23, 194, 52, // Skip to: 19091 -/* 5585 */ MCD_OPC_CheckField, 12, 16, 0, 188, 52, // Skip to: 19091 -/* 5591 */ MCD_OPC_CheckField, 8, 1, 0, 182, 52, // Skip to: 19091 -/* 5597 */ MCD_OPC_Decode, 248, 19, 130, 2, // Opcode: VNN -/* 5602 */ MCD_OPC_FilterValue, 111, 21, 0, // Skip to: 5627 -/* 5606 */ MCD_OPC_CheckPredicate, 23, 169, 52, // Skip to: 19091 -/* 5610 */ MCD_OPC_CheckField, 12, 16, 0, 163, 52, // Skip to: 19091 -/* 5616 */ MCD_OPC_CheckField, 8, 1, 0, 157, 52, // Skip to: 19091 -/* 5622 */ MCD_OPC_Decode, 252, 19, 130, 2, // Opcode: VOC -/* 5627 */ MCD_OPC_FilterValue, 112, 78, 0, // Skip to: 5709 -/* 5631 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5634 */ MCD_OPC_FilterValue, 0, 141, 52, // Skip to: 19091 -/* 5638 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 5641 */ MCD_OPC_FilterValue, 0, 134, 52, // Skip to: 19091 -/* 5645 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 5648 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5661 -/* 5652 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5700 -/* 5656 */ MCD_OPC_Decode, 193, 17, 130, 2, // Opcode: VESLVB -/* 5661 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5674 -/* 5665 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5700 -/* 5669 */ MCD_OPC_Decode, 196, 17, 130, 2, // Opcode: VESLVH -/* 5674 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5687 -/* 5678 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5700 -/* 5682 */ MCD_OPC_Decode, 194, 17, 130, 2, // Opcode: VESLVF -/* 5687 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5700 -/* 5691 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5700 -/* 5695 */ MCD_OPC_Decode, 195, 17, 130, 2, // Opcode: VESLVG -/* 5700 */ MCD_OPC_CheckPredicate, 22, 75, 52, // Skip to: 19091 -/* 5704 */ MCD_OPC_Decode, 192, 17, 131, 2, // Opcode: VESLV -/* 5709 */ MCD_OPC_FilterValue, 114, 78, 0, // Skip to: 5791 -/* 5713 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5716 */ MCD_OPC_FilterValue, 0, 59, 52, // Skip to: 19091 -/* 5720 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 5723 */ MCD_OPC_FilterValue, 0, 52, 52, // Skip to: 19091 -/* 5727 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 5730 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5743 -/* 5734 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5782 -/* 5738 */ MCD_OPC_Decode, 173, 17, 133, 2, // Opcode: VERIMB -/* 5743 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5756 -/* 5747 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5782 -/* 5751 */ MCD_OPC_Decode, 176, 17, 133, 2, // Opcode: VERIMH -/* 5756 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5769 -/* 5760 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5782 -/* 5764 */ MCD_OPC_Decode, 174, 17, 133, 2, // Opcode: VERIMF -/* 5769 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5782 -/* 5773 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5782 -/* 5777 */ MCD_OPC_Decode, 175, 17, 133, 2, // Opcode: VERIMG -/* 5782 */ MCD_OPC_CheckPredicate, 22, 249, 51, // Skip to: 19091 -/* 5786 */ MCD_OPC_Decode, 172, 17, 134, 2, // Opcode: VERIM -/* 5791 */ MCD_OPC_FilterValue, 115, 78, 0, // Skip to: 5873 -/* 5795 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5798 */ MCD_OPC_FilterValue, 0, 233, 51, // Skip to: 19091 -/* 5802 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 5805 */ MCD_OPC_FilterValue, 0, 226, 51, // Skip to: 19091 -/* 5809 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 5812 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5825 -/* 5816 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5864 -/* 5820 */ MCD_OPC_Decode, 183, 17, 130, 2, // Opcode: VERLLVB -/* 5825 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5838 -/* 5829 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5864 -/* 5833 */ MCD_OPC_Decode, 186, 17, 130, 2, // Opcode: VERLLVH -/* 5838 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5851 -/* 5842 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5864 -/* 5846 */ MCD_OPC_Decode, 184, 17, 130, 2, // Opcode: VERLLVF -/* 5851 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5864 -/* 5855 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5864 -/* 5859 */ MCD_OPC_Decode, 185, 17, 130, 2, // Opcode: VERLLVG -/* 5864 */ MCD_OPC_CheckPredicate, 22, 167, 51, // Skip to: 19091 -/* 5868 */ MCD_OPC_Decode, 182, 17, 131, 2, // Opcode: VERLLV -/* 5873 */ MCD_OPC_FilterValue, 116, 21, 0, // Skip to: 5898 -/* 5877 */ MCD_OPC_CheckPredicate, 22, 154, 51, // Skip to: 19091 -/* 5881 */ MCD_OPC_CheckField, 12, 16, 0, 148, 51, // Skip to: 19091 -/* 5887 */ MCD_OPC_CheckField, 8, 1, 0, 142, 51, // Skip to: 19091 -/* 5893 */ MCD_OPC_Decode, 187, 20, 130, 2, // Opcode: VSL -/* 5898 */ MCD_OPC_FilterValue, 117, 21, 0, // Skip to: 5923 -/* 5902 */ MCD_OPC_CheckPredicate, 22, 129, 51, // Skip to: 19091 -/* 5906 */ MCD_OPC_CheckField, 12, 16, 0, 123, 51, // Skip to: 19091 -/* 5912 */ MCD_OPC_CheckField, 8, 1, 0, 117, 51, // Skip to: 19091 -/* 5918 */ MCD_OPC_Decode, 188, 20, 130, 2, // Opcode: VSLB -/* 5923 */ MCD_OPC_FilterValue, 119, 27, 0, // Skip to: 5954 -/* 5927 */ MCD_OPC_CheckPredicate, 22, 104, 51, // Skip to: 19091 -/* 5931 */ MCD_OPC_CheckField, 24, 4, 0, 98, 51, // Skip to: 19091 -/* 5937 */ MCD_OPC_CheckField, 12, 4, 0, 92, 51, // Skip to: 19091 -/* 5943 */ MCD_OPC_CheckField, 8, 1, 0, 86, 51, // Skip to: 19091 -/* 5949 */ MCD_OPC_Decode, 189, 20, 135, 2, // Opcode: VSLDB -/* 5954 */ MCD_OPC_FilterValue, 120, 78, 0, // Skip to: 6036 -/* 5958 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5961 */ MCD_OPC_FilterValue, 0, 70, 51, // Skip to: 19091 -/* 5965 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 5968 */ MCD_OPC_FilterValue, 0, 63, 51, // Skip to: 19091 -/* 5972 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 5975 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5988 -/* 5979 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 6027 -/* 5983 */ MCD_OPC_Decode, 213, 17, 130, 2, // Opcode: VESRLVB -/* 5988 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6001 -/* 5992 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6027 -/* 5996 */ MCD_OPC_Decode, 216, 17, 130, 2, // Opcode: VESRLVH -/* 6001 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6014 -/* 6005 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6027 -/* 6009 */ MCD_OPC_Decode, 214, 17, 130, 2, // Opcode: VESRLVF -/* 6014 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6027 -/* 6018 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6027 -/* 6022 */ MCD_OPC_Decode, 215, 17, 130, 2, // Opcode: VESRLVG -/* 6027 */ MCD_OPC_CheckPredicate, 22, 4, 51, // Skip to: 19091 -/* 6031 */ MCD_OPC_Decode, 212, 17, 131, 2, // Opcode: VESRLV -/* 6036 */ MCD_OPC_FilterValue, 122, 78, 0, // Skip to: 6118 -/* 6040 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 6043 */ MCD_OPC_FilterValue, 0, 244, 50, // Skip to: 19091 -/* 6047 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 6050 */ MCD_OPC_FilterValue, 0, 237, 50, // Skip to: 19091 -/* 6054 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 6057 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6070 -/* 6061 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 6109 -/* 6065 */ MCD_OPC_Decode, 203, 17, 130, 2, // Opcode: VESRAVB -/* 6070 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6083 -/* 6074 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6109 -/* 6078 */ MCD_OPC_Decode, 206, 17, 130, 2, // Opcode: VESRAVH -/* 6083 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6096 -/* 6087 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6109 -/* 6091 */ MCD_OPC_Decode, 204, 17, 130, 2, // Opcode: VESRAVF -/* 6096 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6109 -/* 6100 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6109 -/* 6104 */ MCD_OPC_Decode, 205, 17, 130, 2, // Opcode: VESRAVG -/* 6109 */ MCD_OPC_CheckPredicate, 22, 178, 50, // Skip to: 19091 -/* 6113 */ MCD_OPC_Decode, 202, 17, 131, 2, // Opcode: VESRAV -/* 6118 */ MCD_OPC_FilterValue, 124, 21, 0, // Skip to: 6143 -/* 6122 */ MCD_OPC_CheckPredicate, 22, 165, 50, // Skip to: 19091 -/* 6126 */ MCD_OPC_CheckField, 12, 16, 0, 159, 50, // Skip to: 19091 -/* 6132 */ MCD_OPC_CheckField, 8, 1, 0, 153, 50, // Skip to: 19091 -/* 6138 */ MCD_OPC_Decode, 194, 20, 130, 2, // Opcode: VSRL -/* 6143 */ MCD_OPC_FilterValue, 125, 21, 0, // Skip to: 6168 -/* 6147 */ MCD_OPC_CheckPredicate, 22, 140, 50, // Skip to: 19091 -/* 6151 */ MCD_OPC_CheckField, 12, 16, 0, 134, 50, // Skip to: 19091 -/* 6157 */ MCD_OPC_CheckField, 8, 1, 0, 128, 50, // Skip to: 19091 -/* 6163 */ MCD_OPC_Decode, 195, 20, 130, 2, // Opcode: VSRLB -/* 6168 */ MCD_OPC_FilterValue, 126, 21, 0, // Skip to: 6193 -/* 6172 */ MCD_OPC_CheckPredicate, 22, 115, 50, // Skip to: 19091 -/* 6176 */ MCD_OPC_CheckField, 12, 16, 0, 109, 50, // Skip to: 19091 -/* 6182 */ MCD_OPC_CheckField, 8, 1, 0, 103, 50, // Skip to: 19091 -/* 6188 */ MCD_OPC_Decode, 192, 20, 130, 2, // Opcode: VSRA -/* 6193 */ MCD_OPC_FilterValue, 127, 21, 0, // Skip to: 6218 -/* 6197 */ MCD_OPC_CheckPredicate, 22, 90, 50, // Skip to: 19091 -/* 6201 */ MCD_OPC_CheckField, 12, 16, 0, 84, 50, // Skip to: 19091 -/* 6207 */ MCD_OPC_CheckField, 8, 1, 0, 78, 50, // Skip to: 19091 -/* 6213 */ MCD_OPC_Decode, 193, 20, 130, 2, // Opcode: VSRAB -/* 6218 */ MCD_OPC_FilterValue, 128, 1, 198, 0, // Skip to: 6421 -/* 6223 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 6226 */ MCD_OPC_FilterValue, 0, 61, 50, // Skip to: 19091 -/* 6230 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 6233 */ MCD_OPC_FilterValue, 0, 54, 50, // Skip to: 19091 -/* 6237 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 6240 */ MCD_OPC_FilterValue, 0, 47, 50, // Skip to: 19091 -/* 6244 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 6247 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 6302 -/* 6251 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 6254 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6267 -/* 6258 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6293 -/* 6262 */ MCD_OPC_Decode, 253, 17, 130, 2, // Opcode: VFEEBS -/* 6267 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6280 -/* 6271 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6293 -/* 6275 */ MCD_OPC_Decode, 130, 18, 130, 2, // Opcode: VFEEZB -/* 6280 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6293 -/* 6284 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6293 -/* 6288 */ MCD_OPC_Decode, 131, 18, 130, 2, // Opcode: VFEEZBS -/* 6293 */ MCD_OPC_CheckPredicate, 22, 115, 0, // Skip to: 6412 -/* 6297 */ MCD_OPC_Decode, 252, 17, 136, 2, // Opcode: VFEEB -/* 6302 */ MCD_OPC_FilterValue, 1, 51, 0, // Skip to: 6357 -/* 6306 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 6309 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6322 -/* 6313 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6348 -/* 6317 */ MCD_OPC_Decode, 129, 18, 130, 2, // Opcode: VFEEHS -/* 6322 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6335 -/* 6326 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6348 -/* 6330 */ MCD_OPC_Decode, 134, 18, 130, 2, // Opcode: VFEEZH -/* 6335 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6348 -/* 6339 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6348 -/* 6343 */ MCD_OPC_Decode, 135, 18, 130, 2, // Opcode: VFEEZHS -/* 6348 */ MCD_OPC_CheckPredicate, 22, 60, 0, // Skip to: 6412 -/* 6352 */ MCD_OPC_Decode, 128, 18, 136, 2, // Opcode: VFEEH -/* 6357 */ MCD_OPC_FilterValue, 2, 51, 0, // Skip to: 6412 -/* 6361 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 6364 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6377 -/* 6368 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6403 -/* 6372 */ MCD_OPC_Decode, 255, 17, 130, 2, // Opcode: VFEEFS -/* 6377 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6390 -/* 6381 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6403 -/* 6385 */ MCD_OPC_Decode, 132, 18, 130, 2, // Opcode: VFEEZF -/* 6390 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6403 -/* 6394 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6403 -/* 6398 */ MCD_OPC_Decode, 133, 18, 130, 2, // Opcode: VFEEZFS -/* 6403 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6412 -/* 6407 */ MCD_OPC_Decode, 254, 17, 136, 2, // Opcode: VFEEF -/* 6412 */ MCD_OPC_CheckPredicate, 22, 131, 49, // Skip to: 19091 -/* 6416 */ MCD_OPC_Decode, 251, 17, 137, 2, // Opcode: VFEE -/* 6421 */ MCD_OPC_FilterValue, 129, 1, 198, 0, // Skip to: 6624 -/* 6426 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 6429 */ MCD_OPC_FilterValue, 0, 114, 49, // Skip to: 19091 -/* 6433 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 6436 */ MCD_OPC_FilterValue, 0, 107, 49, // Skip to: 19091 -/* 6440 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 6443 */ MCD_OPC_FilterValue, 0, 100, 49, // Skip to: 19091 -/* 6447 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 6450 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 6505 -/* 6454 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 6457 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6470 -/* 6461 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6496 -/* 6465 */ MCD_OPC_Decode, 138, 18, 130, 2, // Opcode: VFENEBS -/* 6470 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6483 -/* 6474 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6496 -/* 6478 */ MCD_OPC_Decode, 143, 18, 130, 2, // Opcode: VFENEZB -/* 6483 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6496 -/* 6487 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6496 -/* 6491 */ MCD_OPC_Decode, 144, 18, 130, 2, // Opcode: VFENEZBS -/* 6496 */ MCD_OPC_CheckPredicate, 22, 115, 0, // Skip to: 6615 -/* 6500 */ MCD_OPC_Decode, 137, 18, 136, 2, // Opcode: VFENEB -/* 6505 */ MCD_OPC_FilterValue, 1, 51, 0, // Skip to: 6560 -/* 6509 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 6512 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6525 -/* 6516 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6551 -/* 6520 */ MCD_OPC_Decode, 142, 18, 130, 2, // Opcode: VFENEHS -/* 6525 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6538 -/* 6529 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6551 -/* 6533 */ MCD_OPC_Decode, 147, 18, 130, 2, // Opcode: VFENEZH -/* 6538 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6551 -/* 6542 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6551 -/* 6546 */ MCD_OPC_Decode, 148, 18, 130, 2, // Opcode: VFENEZHS -/* 6551 */ MCD_OPC_CheckPredicate, 22, 60, 0, // Skip to: 6615 -/* 6555 */ MCD_OPC_Decode, 141, 18, 136, 2, // Opcode: VFENEH -/* 6560 */ MCD_OPC_FilterValue, 2, 51, 0, // Skip to: 6615 -/* 6564 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 6567 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6580 -/* 6571 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6606 -/* 6575 */ MCD_OPC_Decode, 140, 18, 130, 2, // Opcode: VFENEFS -/* 6580 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6593 -/* 6584 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6606 -/* 6588 */ MCD_OPC_Decode, 145, 18, 130, 2, // Opcode: VFENEZF -/* 6593 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6606 -/* 6597 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6606 -/* 6601 */ MCD_OPC_Decode, 146, 18, 130, 2, // Opcode: VFENEZFS -/* 6606 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6615 -/* 6610 */ MCD_OPC_Decode, 139, 18, 136, 2, // Opcode: VFENEF -/* 6615 */ MCD_OPC_CheckPredicate, 22, 184, 48, // Skip to: 19091 -/* 6619 */ MCD_OPC_Decode, 136, 18, 137, 2, // Opcode: VFENE -/* 6624 */ MCD_OPC_FilterValue, 130, 1, 207, 0, // Skip to: 6836 -/* 6629 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 6632 */ MCD_OPC_FilterValue, 0, 167, 48, // Skip to: 19091 -/* 6636 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 6639 */ MCD_OPC_FilterValue, 0, 160, 48, // Skip to: 19091 -/* 6643 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 6646 */ MCD_OPC_FilterValue, 0, 153, 48, // Skip to: 19091 -/* 6650 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 6653 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 6711 -/* 6657 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6672 -/* 6661 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6672 -/* 6667 */ MCD_OPC_Decode, 227, 17, 138, 2, // Opcode: VFAEZBS -/* 6672 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6687 -/* 6676 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6687 -/* 6682 */ MCD_OPC_Decode, 221, 17, 139, 2, // Opcode: VFAEBS -/* 6687 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6702 -/* 6691 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 6702 -/* 6697 */ MCD_OPC_Decode, 226, 17, 140, 2, // Opcode: VFAEZB -/* 6702 */ MCD_OPC_CheckPredicate, 22, 121, 0, // Skip to: 6827 -/* 6706 */ MCD_OPC_Decode, 220, 17, 136, 2, // Opcode: VFAEB -/* 6711 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 6769 -/* 6715 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6730 -/* 6719 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6730 -/* 6725 */ MCD_OPC_Decode, 231, 17, 138, 2, // Opcode: VFAEZHS -/* 6730 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6745 -/* 6734 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6745 -/* 6740 */ MCD_OPC_Decode, 225, 17, 139, 2, // Opcode: VFAEHS -/* 6745 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6760 -/* 6749 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 6760 -/* 6755 */ MCD_OPC_Decode, 230, 17, 140, 2, // Opcode: VFAEZH -/* 6760 */ MCD_OPC_CheckPredicate, 22, 63, 0, // Skip to: 6827 -/* 6764 */ MCD_OPC_Decode, 224, 17, 136, 2, // Opcode: VFAEH -/* 6769 */ MCD_OPC_FilterValue, 2, 54, 0, // Skip to: 6827 -/* 6773 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6788 -/* 6777 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6788 -/* 6783 */ MCD_OPC_Decode, 229, 17, 138, 2, // Opcode: VFAEZFS -/* 6788 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6803 -/* 6792 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6803 -/* 6798 */ MCD_OPC_Decode, 223, 17, 139, 2, // Opcode: VFAEFS -/* 6803 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6818 -/* 6807 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 6818 -/* 6813 */ MCD_OPC_Decode, 228, 17, 140, 2, // Opcode: VFAEZF -/* 6818 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6827 -/* 6822 */ MCD_OPC_Decode, 222, 17, 136, 2, // Opcode: VFAEF -/* 6827 */ MCD_OPC_CheckPredicate, 22, 228, 47, // Skip to: 19091 -/* 6831 */ MCD_OPC_Decode, 219, 17, 137, 2, // Opcode: VFAE -/* 6836 */ MCD_OPC_FilterValue, 132, 1, 21, 0, // Skip to: 6862 -/* 6841 */ MCD_OPC_CheckPredicate, 22, 214, 47, // Skip to: 19091 -/* 6845 */ MCD_OPC_CheckField, 16, 12, 0, 208, 47, // Skip to: 19091 -/* 6851 */ MCD_OPC_CheckField, 8, 1, 0, 202, 47, // Skip to: 19091 -/* 6857 */ MCD_OPC_Decode, 254, 19, 131, 2, // Opcode: VPDI -/* 6862 */ MCD_OPC_FilterValue, 133, 1, 21, 0, // Skip to: 6888 -/* 6867 */ MCD_OPC_CheckPredicate, 23, 188, 47, // Skip to: 19091 -/* 6871 */ MCD_OPC_CheckField, 12, 16, 0, 182, 47, // Skip to: 19091 -/* 6877 */ MCD_OPC_CheckField, 8, 1, 0, 176, 47, // Skip to: 19091 -/* 6883 */ MCD_OPC_Decode, 237, 16, 130, 2, // Opcode: VBPERM -/* 6888 */ MCD_OPC_FilterValue, 138, 1, 193, 0, // Skip to: 7086 -/* 6893 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 6896 */ MCD_OPC_FilterValue, 0, 159, 47, // Skip to: 19091 -/* 6900 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 6903 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 6961 -/* 6907 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6922 -/* 6911 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6922 -/* 6917 */ MCD_OPC_Decode, 212, 20, 141, 2, // Opcode: VSTRCZBS -/* 6922 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6937 -/* 6926 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6937 -/* 6932 */ MCD_OPC_Decode, 206, 20, 142, 2, // Opcode: VSTRCBS -/* 6937 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6952 -/* 6941 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 6952 -/* 6947 */ MCD_OPC_Decode, 211, 20, 143, 2, // Opcode: VSTRCZB -/* 6952 */ MCD_OPC_CheckPredicate, 22, 121, 0, // Skip to: 7077 -/* 6956 */ MCD_OPC_Decode, 205, 20, 144, 2, // Opcode: VSTRCB -/* 6961 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 7019 -/* 6965 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6980 -/* 6969 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6980 -/* 6975 */ MCD_OPC_Decode, 216, 20, 141, 2, // Opcode: VSTRCZHS -/* 6980 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6995 -/* 6984 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6995 -/* 6990 */ MCD_OPC_Decode, 210, 20, 142, 2, // Opcode: VSTRCHS -/* 6995 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 7010 -/* 6999 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 7010 -/* 7005 */ MCD_OPC_Decode, 215, 20, 143, 2, // Opcode: VSTRCZH -/* 7010 */ MCD_OPC_CheckPredicate, 22, 63, 0, // Skip to: 7077 -/* 7014 */ MCD_OPC_Decode, 209, 20, 144, 2, // Opcode: VSTRCH -/* 7019 */ MCD_OPC_FilterValue, 2, 54, 0, // Skip to: 7077 -/* 7023 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 7038 -/* 7027 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 7038 -/* 7033 */ MCD_OPC_Decode, 214, 20, 141, 2, // Opcode: VSTRCZFS -/* 7038 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 7053 -/* 7042 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 7053 -/* 7048 */ MCD_OPC_Decode, 208, 20, 142, 2, // Opcode: VSTRCFS -/* 7053 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 7068 -/* 7057 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 7068 -/* 7063 */ MCD_OPC_Decode, 213, 20, 143, 2, // Opcode: VSTRCZF -/* 7068 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7077 -/* 7072 */ MCD_OPC_Decode, 207, 20, 144, 2, // Opcode: VSTRCF -/* 7077 */ MCD_OPC_CheckPredicate, 22, 234, 46, // Skip to: 19091 -/* 7081 */ MCD_OPC_Decode, 204, 20, 145, 2, // Opcode: VSTRC -/* 7086 */ MCD_OPC_FilterValue, 140, 1, 15, 0, // Skip to: 7106 -/* 7091 */ MCD_OPC_CheckPredicate, 22, 220, 46, // Skip to: 19091 -/* 7095 */ MCD_OPC_CheckField, 16, 12, 0, 214, 46, // Skip to: 19091 -/* 7101 */ MCD_OPC_Decode, 255, 19, 146, 2, // Opcode: VPERM -/* 7106 */ MCD_OPC_FilterValue, 141, 1, 15, 0, // Skip to: 7126 -/* 7111 */ MCD_OPC_CheckPredicate, 22, 200, 46, // Skip to: 19091 -/* 7115 */ MCD_OPC_CheckField, 16, 12, 0, 194, 46, // Skip to: 19091 -/* 7121 */ MCD_OPC_Decode, 183, 20, 146, 2, // Opcode: VSEL -/* 7126 */ MCD_OPC_FilterValue, 142, 1, 104, 0, // Skip to: 7235 -/* 7131 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7134 */ MCD_OPC_FilterValue, 0, 177, 46, // Skip to: 19091 -/* 7138 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 7141 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7174 -/* 7145 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7148 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7161 -/* 7152 */ MCD_OPC_CheckPredicate, 23, 70, 0, // Skip to: 7226 -/* 7156 */ MCD_OPC_Decode, 188, 18, 146, 2, // Opcode: VFMSSB -/* 7161 */ MCD_OPC_FilterValue, 8, 61, 0, // Skip to: 7226 -/* 7165 */ MCD_OPC_CheckPredicate, 23, 57, 0, // Skip to: 7226 -/* 7169 */ MCD_OPC_Decode, 203, 21, 147, 2, // Opcode: WFMSSB -/* 7174 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7207 -/* 7178 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7181 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7194 -/* 7185 */ MCD_OPC_CheckPredicate, 22, 37, 0, // Skip to: 7226 -/* 7189 */ MCD_OPC_Decode, 187, 18, 146, 2, // Opcode: VFMSDB -/* 7194 */ MCD_OPC_FilterValue, 8, 28, 0, // Skip to: 7226 -/* 7198 */ MCD_OPC_CheckPredicate, 22, 24, 0, // Skip to: 7226 -/* 7202 */ MCD_OPC_Decode, 202, 21, 148, 2, // Opcode: WFMSDB -/* 7207 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 7226 -/* 7211 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 7226 -/* 7215 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, // Skip to: 7226 -/* 7221 */ MCD_OPC_Decode, 204, 21, 146, 2, // Opcode: WFMSXB -/* 7226 */ MCD_OPC_CheckPredicate, 22, 85, 46, // Skip to: 19091 -/* 7230 */ MCD_OPC_Decode, 185, 18, 149, 2, // Opcode: VFMS -/* 7235 */ MCD_OPC_FilterValue, 143, 1, 104, 0, // Skip to: 7344 -/* 7240 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7243 */ MCD_OPC_FilterValue, 0, 68, 46, // Skip to: 19091 -/* 7247 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 7250 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7283 -/* 7254 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7257 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7270 -/* 7261 */ MCD_OPC_CheckPredicate, 23, 70, 0, // Skip to: 7335 -/* 7265 */ MCD_OPC_Decode, 177, 18, 146, 2, // Opcode: VFMASB -/* 7270 */ MCD_OPC_FilterValue, 8, 61, 0, // Skip to: 7335 -/* 7274 */ MCD_OPC_CheckPredicate, 23, 57, 0, // Skip to: 7335 -/* 7278 */ MCD_OPC_Decode, 192, 21, 147, 2, // Opcode: WFMASB -/* 7283 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7316 -/* 7287 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7290 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7303 -/* 7294 */ MCD_OPC_CheckPredicate, 22, 37, 0, // Skip to: 7335 -/* 7298 */ MCD_OPC_Decode, 176, 18, 146, 2, // Opcode: VFMADB -/* 7303 */ MCD_OPC_FilterValue, 8, 28, 0, // Skip to: 7335 -/* 7307 */ MCD_OPC_CheckPredicate, 22, 24, 0, // Skip to: 7335 -/* 7311 */ MCD_OPC_Decode, 191, 21, 148, 2, // Opcode: WFMADB -/* 7316 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 7335 -/* 7320 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 7335 -/* 7324 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, // Skip to: 7335 -/* 7330 */ MCD_OPC_Decode, 193, 21, 146, 2, // Opcode: WFMAXB -/* 7335 */ MCD_OPC_CheckPredicate, 22, 232, 45, // Skip to: 19091 -/* 7339 */ MCD_OPC_Decode, 175, 18, 149, 2, // Opcode: VFMA -/* 7344 */ MCD_OPC_FilterValue, 148, 1, 65, 0, // Skip to: 7414 -/* 7349 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 7352 */ MCD_OPC_FilterValue, 0, 215, 45, // Skip to: 19091 -/* 7356 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 7359 */ MCD_OPC_FilterValue, 0, 208, 45, // Skip to: 19091 -/* 7363 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 7366 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7379 -/* 7370 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 7405 -/* 7374 */ MCD_OPC_Decode, 131, 20, 130, 2, // Opcode: VPKH -/* 7379 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7392 -/* 7383 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 7405 -/* 7387 */ MCD_OPC_Decode, 129, 20, 130, 2, // Opcode: VPKF -/* 7392 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7405 -/* 7396 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7405 -/* 7400 */ MCD_OPC_Decode, 130, 20, 130, 2, // Opcode: VPKG -/* 7405 */ MCD_OPC_CheckPredicate, 22, 162, 45, // Skip to: 19091 -/* 7409 */ MCD_OPC_Decode, 128, 20, 131, 2, // Opcode: VPK -/* 7414 */ MCD_OPC_FilterValue, 149, 1, 132, 0, // Skip to: 7551 -/* 7419 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 7422 */ MCD_OPC_FilterValue, 0, 145, 45, // Skip to: 19091 -/* 7426 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7429 */ MCD_OPC_FilterValue, 0, 138, 45, // Skip to: 19091 -/* 7433 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 7436 */ MCD_OPC_FilterValue, 0, 131, 45, // Skip to: 19091 -/* 7440 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 7443 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 7476 -/* 7447 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7450 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7463 -/* 7454 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 7542 -/* 7458 */ MCD_OPC_Decode, 137, 20, 130, 2, // Opcode: VPKLSH -/* 7463 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 7542 -/* 7467 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 7542 -/* 7471 */ MCD_OPC_Decode, 138, 20, 130, 2, // Opcode: VPKLSHS -/* 7476 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7509 -/* 7480 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7483 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7496 -/* 7487 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 7542 -/* 7491 */ MCD_OPC_Decode, 133, 20, 130, 2, // Opcode: VPKLSF -/* 7496 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 7542 -/* 7500 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 7542 -/* 7504 */ MCD_OPC_Decode, 134, 20, 130, 2, // Opcode: VPKLSFS -/* 7509 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7542 -/* 7513 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7516 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7529 -/* 7520 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 7542 -/* 7524 */ MCD_OPC_Decode, 135, 20, 130, 2, // Opcode: VPKLSG -/* 7529 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7542 -/* 7533 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7542 -/* 7537 */ MCD_OPC_Decode, 136, 20, 130, 2, // Opcode: VPKLSGS -/* 7542 */ MCD_OPC_CheckPredicate, 22, 25, 45, // Skip to: 19091 -/* 7546 */ MCD_OPC_Decode, 132, 20, 137, 2, // Opcode: VPKLS -/* 7551 */ MCD_OPC_FilterValue, 151, 1, 132, 0, // Skip to: 7688 -/* 7556 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 7559 */ MCD_OPC_FilterValue, 0, 8, 45, // Skip to: 19091 -/* 7563 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7566 */ MCD_OPC_FilterValue, 0, 1, 45, // Skip to: 19091 -/* 7570 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 7573 */ MCD_OPC_FilterValue, 0, 250, 44, // Skip to: 19091 -/* 7577 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 7580 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 7613 -/* 7584 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7587 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7600 -/* 7591 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 7679 -/* 7595 */ MCD_OPC_Decode, 144, 20, 130, 2, // Opcode: VPKSH -/* 7600 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 7679 -/* 7604 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 7679 -/* 7608 */ MCD_OPC_Decode, 145, 20, 130, 2, // Opcode: VPKSHS -/* 7613 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7646 -/* 7617 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7620 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7633 -/* 7624 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 7679 -/* 7628 */ MCD_OPC_Decode, 140, 20, 130, 2, // Opcode: VPKSF -/* 7633 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 7679 -/* 7637 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 7679 -/* 7641 */ MCD_OPC_Decode, 141, 20, 130, 2, // Opcode: VPKSFS -/* 7646 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7679 -/* 7650 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7653 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7666 -/* 7657 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 7679 -/* 7661 */ MCD_OPC_Decode, 142, 20, 130, 2, // Opcode: VPKSG -/* 7666 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7679 -/* 7670 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7679 -/* 7674 */ MCD_OPC_Decode, 143, 20, 130, 2, // Opcode: VPKSGS -/* 7679 */ MCD_OPC_CheckPredicate, 22, 144, 44, // Skip to: 19091 -/* 7683 */ MCD_OPC_Decode, 139, 20, 137, 2, // Opcode: VPKS -/* 7688 */ MCD_OPC_FilterValue, 158, 1, 104, 0, // Skip to: 7797 -/* 7693 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7696 */ MCD_OPC_FilterValue, 0, 127, 44, // Skip to: 19091 -/* 7700 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 7703 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7736 -/* 7707 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7710 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7723 -/* 7714 */ MCD_OPC_CheckPredicate, 23, 70, 0, // Skip to: 7788 -/* 7718 */ MCD_OPC_Decode, 194, 18, 146, 2, // Opcode: VFNMSSB -/* 7723 */ MCD_OPC_FilterValue, 8, 61, 0, // Skip to: 7788 -/* 7727 */ MCD_OPC_CheckPredicate, 23, 57, 0, // Skip to: 7788 -/* 7731 */ MCD_OPC_Decode, 210, 21, 147, 2, // Opcode: WFNMSSB -/* 7736 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7769 -/* 7740 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7743 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7756 -/* 7747 */ MCD_OPC_CheckPredicate, 23, 37, 0, // Skip to: 7788 -/* 7751 */ MCD_OPC_Decode, 193, 18, 146, 2, // Opcode: VFNMSDB -/* 7756 */ MCD_OPC_FilterValue, 8, 28, 0, // Skip to: 7788 -/* 7760 */ MCD_OPC_CheckPredicate, 23, 24, 0, // Skip to: 7788 -/* 7764 */ MCD_OPC_Decode, 209, 21, 148, 2, // Opcode: WFNMSDB -/* 7769 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 7788 -/* 7773 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 7788 -/* 7777 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, // Skip to: 7788 -/* 7783 */ MCD_OPC_Decode, 211, 21, 146, 2, // Opcode: WFNMSXB -/* 7788 */ MCD_OPC_CheckPredicate, 23, 35, 44, // Skip to: 19091 -/* 7792 */ MCD_OPC_Decode, 192, 18, 149, 2, // Opcode: VFNMS -/* 7797 */ MCD_OPC_FilterValue, 159, 1, 104, 0, // Skip to: 7906 -/* 7802 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7805 */ MCD_OPC_FilterValue, 0, 18, 44, // Skip to: 19091 -/* 7809 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 7812 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7845 -/* 7816 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7819 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7832 -/* 7823 */ MCD_OPC_CheckPredicate, 23, 70, 0, // Skip to: 7897 -/* 7827 */ MCD_OPC_Decode, 191, 18, 146, 2, // Opcode: VFNMASB -/* 7832 */ MCD_OPC_FilterValue, 8, 61, 0, // Skip to: 7897 -/* 7836 */ MCD_OPC_CheckPredicate, 23, 57, 0, // Skip to: 7897 -/* 7840 */ MCD_OPC_Decode, 207, 21, 147, 2, // Opcode: WFNMASB -/* 7845 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7878 -/* 7849 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7852 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7865 -/* 7856 */ MCD_OPC_CheckPredicate, 23, 37, 0, // Skip to: 7897 -/* 7860 */ MCD_OPC_Decode, 190, 18, 146, 2, // Opcode: VFNMADB -/* 7865 */ MCD_OPC_FilterValue, 8, 28, 0, // Skip to: 7897 -/* 7869 */ MCD_OPC_CheckPredicate, 23, 24, 0, // Skip to: 7897 -/* 7873 */ MCD_OPC_Decode, 206, 21, 148, 2, // Opcode: WFNMADB -/* 7878 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 7897 -/* 7882 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 7897 -/* 7886 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, // Skip to: 7897 -/* 7892 */ MCD_OPC_Decode, 208, 21, 146, 2, // Opcode: WFNMAXB -/* 7897 */ MCD_OPC_CheckPredicate, 23, 182, 43, // Skip to: 19091 -/* 7901 */ MCD_OPC_Decode, 189, 18, 149, 2, // Opcode: VFNMA -/* 7906 */ MCD_OPC_FilterValue, 161, 1, 65, 0, // Skip to: 7976 -/* 7911 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 7914 */ MCD_OPC_FilterValue, 0, 165, 43, // Skip to: 19091 -/* 7918 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 7921 */ MCD_OPC_FilterValue, 0, 158, 43, // Skip to: 19091 -/* 7925 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 7928 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7941 -/* 7932 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 7967 -/* 7936 */ MCD_OPC_Decode, 200, 19, 130, 2, // Opcode: VMLHB -/* 7941 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7954 -/* 7945 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 7967 -/* 7949 */ MCD_OPC_Decode, 202, 19, 130, 2, // Opcode: VMLHH -/* 7954 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7967 -/* 7958 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7967 -/* 7962 */ MCD_OPC_Decode, 201, 19, 130, 2, // Opcode: VMLHF -/* 7967 */ MCD_OPC_CheckPredicate, 22, 112, 43, // Skip to: 19091 -/* 7971 */ MCD_OPC_Decode, 199, 19, 131, 2, // Opcode: VMLH -/* 7976 */ MCD_OPC_FilterValue, 162, 1, 65, 0, // Skip to: 8046 -/* 7981 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 7984 */ MCD_OPC_FilterValue, 0, 95, 43, // Skip to: 19091 -/* 7988 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 7991 */ MCD_OPC_FilterValue, 0, 88, 43, // Skip to: 19091 -/* 7995 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 7998 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8011 -/* 8002 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8037 -/* 8006 */ MCD_OPC_Decode, 193, 19, 130, 2, // Opcode: VMLB -/* 8011 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8024 -/* 8015 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8037 -/* 8019 */ MCD_OPC_Decode, 203, 19, 130, 2, // Opcode: VMLHW -/* 8024 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8037 -/* 8028 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8037 -/* 8032 */ MCD_OPC_Decode, 198, 19, 130, 2, // Opcode: VMLF -/* 8037 */ MCD_OPC_CheckPredicate, 22, 42, 43, // Skip to: 19091 -/* 8041 */ MCD_OPC_Decode, 192, 19, 131, 2, // Opcode: VML -/* 8046 */ MCD_OPC_FilterValue, 163, 1, 65, 0, // Skip to: 8116 -/* 8051 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 8054 */ MCD_OPC_FilterValue, 0, 25, 43, // Skip to: 19091 -/* 8058 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 8061 */ MCD_OPC_FilterValue, 0, 18, 43, // Skip to: 19091 -/* 8065 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 8068 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8081 -/* 8072 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8107 -/* 8076 */ MCD_OPC_Decode, 189, 19, 130, 2, // Opcode: VMHB -/* 8081 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8094 -/* 8085 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8107 -/* 8089 */ MCD_OPC_Decode, 191, 19, 130, 2, // Opcode: VMHH -/* 8094 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8107 -/* 8098 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8107 -/* 8102 */ MCD_OPC_Decode, 190, 19, 130, 2, // Opcode: VMHF -/* 8107 */ MCD_OPC_CheckPredicate, 22, 228, 42, // Skip to: 19091 -/* 8111 */ MCD_OPC_Decode, 188, 19, 131, 2, // Opcode: VMH -/* 8116 */ MCD_OPC_FilterValue, 164, 1, 65, 0, // Skip to: 8186 -/* 8121 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 8124 */ MCD_OPC_FilterValue, 0, 211, 42, // Skip to: 19091 -/* 8128 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 8131 */ MCD_OPC_FilterValue, 0, 204, 42, // Skip to: 19091 -/* 8135 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 8138 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8151 -/* 8142 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8177 -/* 8146 */ MCD_OPC_Decode, 195, 19, 130, 2, // Opcode: VMLEB -/* 8151 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8164 -/* 8155 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8177 -/* 8159 */ MCD_OPC_Decode, 197, 19, 130, 2, // Opcode: VMLEH -/* 8164 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8177 -/* 8168 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8177 -/* 8172 */ MCD_OPC_Decode, 196, 19, 130, 2, // Opcode: VMLEF -/* 8177 */ MCD_OPC_CheckPredicate, 22, 158, 42, // Skip to: 19091 -/* 8181 */ MCD_OPC_Decode, 194, 19, 131, 2, // Opcode: VMLE -/* 8186 */ MCD_OPC_FilterValue, 165, 1, 65, 0, // Skip to: 8256 -/* 8191 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 8194 */ MCD_OPC_FilterValue, 0, 141, 42, // Skip to: 19091 -/* 8198 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 8201 */ MCD_OPC_FilterValue, 0, 134, 42, // Skip to: 19091 -/* 8205 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 8208 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8221 -/* 8212 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8247 -/* 8216 */ MCD_OPC_Decode, 205, 19, 130, 2, // Opcode: VMLOB -/* 8221 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8234 -/* 8225 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8247 -/* 8229 */ MCD_OPC_Decode, 207, 19, 130, 2, // Opcode: VMLOH -/* 8234 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8247 -/* 8238 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8247 -/* 8242 */ MCD_OPC_Decode, 206, 19, 130, 2, // Opcode: VMLOF -/* 8247 */ MCD_OPC_CheckPredicate, 22, 88, 42, // Skip to: 19091 -/* 8251 */ MCD_OPC_Decode, 204, 19, 131, 2, // Opcode: VMLO -/* 8256 */ MCD_OPC_FilterValue, 166, 1, 65, 0, // Skip to: 8326 -/* 8261 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 8264 */ MCD_OPC_FilterValue, 0, 71, 42, // Skip to: 19091 -/* 8268 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 8271 */ MCD_OPC_FilterValue, 0, 64, 42, // Skip to: 19091 -/* 8275 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 8278 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8291 -/* 8282 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8317 -/* 8286 */ MCD_OPC_Decode, 185, 19, 130, 2, // Opcode: VMEB -/* 8291 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8304 -/* 8295 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8317 -/* 8299 */ MCD_OPC_Decode, 187, 19, 130, 2, // Opcode: VMEH -/* 8304 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8317 -/* 8308 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8317 -/* 8312 */ MCD_OPC_Decode, 186, 19, 130, 2, // Opcode: VMEF -/* 8317 */ MCD_OPC_CheckPredicate, 22, 18, 42, // Skip to: 19091 -/* 8321 */ MCD_OPC_Decode, 184, 19, 131, 2, // Opcode: VME -/* 8326 */ MCD_OPC_FilterValue, 167, 1, 65, 0, // Skip to: 8396 -/* 8331 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 8334 */ MCD_OPC_FilterValue, 0, 1, 42, // Skip to: 19091 -/* 8338 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 8341 */ MCD_OPC_FilterValue, 0, 250, 41, // Skip to: 19091 -/* 8345 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 8348 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8361 -/* 8352 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8387 -/* 8356 */ MCD_OPC_Decode, 219, 19, 130, 2, // Opcode: VMOB -/* 8361 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8374 -/* 8365 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8387 -/* 8369 */ MCD_OPC_Decode, 221, 19, 130, 2, // Opcode: VMOH -/* 8374 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8387 -/* 8378 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8387 -/* 8382 */ MCD_OPC_Decode, 220, 19, 130, 2, // Opcode: VMOF -/* 8387 */ MCD_OPC_CheckPredicate, 22, 204, 41, // Skip to: 19091 -/* 8391 */ MCD_OPC_Decode, 218, 19, 131, 2, // Opcode: VMO -/* 8396 */ MCD_OPC_FilterValue, 169, 1, 58, 0, // Skip to: 8459 -/* 8401 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 8404 */ MCD_OPC_FilterValue, 0, 187, 41, // Skip to: 19091 -/* 8408 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 8411 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8424 -/* 8415 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8450 -/* 8419 */ MCD_OPC_Decode, 172, 19, 146, 2, // Opcode: VMALHB -/* 8424 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8437 -/* 8428 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8450 -/* 8432 */ MCD_OPC_Decode, 174, 19, 146, 2, // Opcode: VMALHH -/* 8437 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8450 -/* 8441 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8450 -/* 8445 */ MCD_OPC_Decode, 173, 19, 146, 2, // Opcode: VMALHF -/* 8450 */ MCD_OPC_CheckPredicate, 22, 141, 41, // Skip to: 19091 -/* 8454 */ MCD_OPC_Decode, 171, 19, 150, 2, // Opcode: VMALH -/* 8459 */ MCD_OPC_FilterValue, 170, 1, 58, 0, // Skip to: 8522 -/* 8464 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 8467 */ MCD_OPC_FilterValue, 0, 124, 41, // Skip to: 19091 -/* 8471 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 8474 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8487 -/* 8478 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8513 -/* 8482 */ MCD_OPC_Decode, 165, 19, 146, 2, // Opcode: VMALB -/* 8487 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8500 -/* 8491 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8513 -/* 8495 */ MCD_OPC_Decode, 175, 19, 146, 2, // Opcode: VMALHW -/* 8500 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8513 -/* 8504 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8513 -/* 8508 */ MCD_OPC_Decode, 170, 19, 146, 2, // Opcode: VMALF -/* 8513 */ MCD_OPC_CheckPredicate, 22, 78, 41, // Skip to: 19091 -/* 8517 */ MCD_OPC_Decode, 164, 19, 150, 2, // Opcode: VMAL -/* 8522 */ MCD_OPC_FilterValue, 171, 1, 58, 0, // Skip to: 8585 -/* 8527 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 8530 */ MCD_OPC_FilterValue, 0, 61, 41, // Skip to: 19091 -/* 8534 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 8537 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8550 -/* 8541 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8576 -/* 8545 */ MCD_OPC_Decode, 161, 19, 146, 2, // Opcode: VMAHB -/* 8550 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8563 -/* 8554 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8576 -/* 8558 */ MCD_OPC_Decode, 163, 19, 146, 2, // Opcode: VMAHH -/* 8563 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8576 -/* 8567 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8576 -/* 8571 */ MCD_OPC_Decode, 162, 19, 146, 2, // Opcode: VMAHF -/* 8576 */ MCD_OPC_CheckPredicate, 22, 15, 41, // Skip to: 19091 -/* 8580 */ MCD_OPC_Decode, 160, 19, 150, 2, // Opcode: VMAH -/* 8585 */ MCD_OPC_FilterValue, 172, 1, 58, 0, // Skip to: 8648 -/* 8590 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 8593 */ MCD_OPC_FilterValue, 0, 254, 40, // Skip to: 19091 -/* 8597 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 8600 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8613 -/* 8604 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8639 -/* 8608 */ MCD_OPC_Decode, 167, 19, 146, 2, // Opcode: VMALEB -/* 8613 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8626 -/* 8617 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8639 -/* 8621 */ MCD_OPC_Decode, 169, 19, 146, 2, // Opcode: VMALEH -/* 8626 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8639 -/* 8630 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8639 -/* 8634 */ MCD_OPC_Decode, 168, 19, 146, 2, // Opcode: VMALEF -/* 8639 */ MCD_OPC_CheckPredicate, 22, 208, 40, // Skip to: 19091 -/* 8643 */ MCD_OPC_Decode, 166, 19, 150, 2, // Opcode: VMALE -/* 8648 */ MCD_OPC_FilterValue, 173, 1, 58, 0, // Skip to: 8711 -/* 8653 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 8656 */ MCD_OPC_FilterValue, 0, 191, 40, // Skip to: 19091 -/* 8660 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 8663 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8676 -/* 8667 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8702 -/* 8671 */ MCD_OPC_Decode, 177, 19, 146, 2, // Opcode: VMALOB -/* 8676 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8689 -/* 8680 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8702 -/* 8684 */ MCD_OPC_Decode, 179, 19, 146, 2, // Opcode: VMALOH -/* 8689 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8702 -/* 8693 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8702 -/* 8697 */ MCD_OPC_Decode, 178, 19, 146, 2, // Opcode: VMALOF -/* 8702 */ MCD_OPC_CheckPredicate, 22, 145, 40, // Skip to: 19091 -/* 8706 */ MCD_OPC_Decode, 176, 19, 150, 2, // Opcode: VMALO -/* 8711 */ MCD_OPC_FilterValue, 174, 1, 58, 0, // Skip to: 8774 -/* 8716 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 8719 */ MCD_OPC_FilterValue, 0, 128, 40, // Skip to: 19091 -/* 8723 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 8726 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8739 -/* 8730 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8765 -/* 8734 */ MCD_OPC_Decode, 157, 19, 146, 2, // Opcode: VMAEB -/* 8739 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8752 -/* 8743 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8765 -/* 8747 */ MCD_OPC_Decode, 159, 19, 146, 2, // Opcode: VMAEH -/* 8752 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8765 -/* 8756 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8765 -/* 8760 */ MCD_OPC_Decode, 158, 19, 146, 2, // Opcode: VMAEF -/* 8765 */ MCD_OPC_CheckPredicate, 22, 82, 40, // Skip to: 19091 -/* 8769 */ MCD_OPC_Decode, 156, 19, 150, 2, // Opcode: VMAE -/* 8774 */ MCD_OPC_FilterValue, 175, 1, 58, 0, // Skip to: 8837 -/* 8779 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 8782 */ MCD_OPC_FilterValue, 0, 65, 40, // Skip to: 19091 -/* 8786 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 8789 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8802 -/* 8793 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8828 -/* 8797 */ MCD_OPC_Decode, 181, 19, 146, 2, // Opcode: VMAOB -/* 8802 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8815 -/* 8806 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8828 -/* 8810 */ MCD_OPC_Decode, 183, 19, 146, 2, // Opcode: VMAOH -/* 8815 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8828 -/* 8819 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8828 -/* 8823 */ MCD_OPC_Decode, 182, 19, 146, 2, // Opcode: VMAOF -/* 8828 */ MCD_OPC_CheckPredicate, 22, 19, 40, // Skip to: 19091 -/* 8832 */ MCD_OPC_Decode, 180, 19, 150, 2, // Opcode: VMAO -/* 8837 */ MCD_OPC_FilterValue, 180, 1, 78, 0, // Skip to: 8920 -/* 8842 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 8845 */ MCD_OPC_FilterValue, 0, 2, 40, // Skip to: 19091 -/* 8849 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 8852 */ MCD_OPC_FilterValue, 0, 251, 39, // Skip to: 19091 -/* 8856 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 8859 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8872 -/* 8863 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 8911 -/* 8867 */ MCD_OPC_Decode, 216, 18, 130, 2, // Opcode: VGFMB -/* 8872 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8885 -/* 8876 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8911 -/* 8880 */ MCD_OPC_Decode, 219, 18, 130, 2, // Opcode: VGFMH -/* 8885 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8898 -/* 8889 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8911 -/* 8893 */ MCD_OPC_Decode, 217, 18, 130, 2, // Opcode: VGFMF -/* 8898 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 8911 -/* 8902 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8911 -/* 8906 */ MCD_OPC_Decode, 218, 18, 130, 2, // Opcode: VGFMG -/* 8911 */ MCD_OPC_CheckPredicate, 22, 192, 39, // Skip to: 19091 -/* 8915 */ MCD_OPC_Decode, 210, 18, 131, 2, // Opcode: VGFM -/* 8920 */ MCD_OPC_FilterValue, 184, 1, 31, 0, // Skip to: 8956 -/* 8925 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 8928 */ MCD_OPC_FilterValue, 0, 175, 39, // Skip to: 19091 -/* 8932 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 8947 -/* 8936 */ MCD_OPC_CheckField, 24, 4, 3, 5, 0, // Skip to: 8947 -/* 8942 */ MCD_OPC_Decode, 234, 19, 144, 2, // Opcode: VMSLG -/* 8947 */ MCD_OPC_CheckPredicate, 23, 156, 39, // Skip to: 19091 -/* 8951 */ MCD_OPC_Decode, 233, 19, 145, 2, // Opcode: VMSL -/* 8956 */ MCD_OPC_FilterValue, 185, 1, 31, 0, // Skip to: 8992 -/* 8961 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 8964 */ MCD_OPC_FilterValue, 0, 139, 39, // Skip to: 19091 -/* 8968 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 8983 -/* 8972 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, // Skip to: 8983 -/* 8978 */ MCD_OPC_Decode, 216, 16, 146, 2, // Opcode: VACCCQ -/* 8983 */ MCD_OPC_CheckPredicate, 22, 120, 39, // Skip to: 19091 -/* 8987 */ MCD_OPC_Decode, 215, 16, 150, 2, // Opcode: VACCC -/* 8992 */ MCD_OPC_FilterValue, 187, 1, 31, 0, // Skip to: 9028 -/* 8997 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 9000 */ MCD_OPC_FilterValue, 0, 103, 39, // Skip to: 19091 -/* 9004 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9019 -/* 9008 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, // Skip to: 9019 -/* 9014 */ MCD_OPC_Decode, 221, 16, 146, 2, // Opcode: VACQ -/* 9019 */ MCD_OPC_CheckPredicate, 22, 84, 39, // Skip to: 19091 -/* 9023 */ MCD_OPC_Decode, 212, 16, 150, 2, // Opcode: VAC -/* 9028 */ MCD_OPC_FilterValue, 188, 1, 71, 0, // Skip to: 9104 -/* 9033 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 9036 */ MCD_OPC_FilterValue, 0, 67, 39, // Skip to: 19091 -/* 9040 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 9043 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9056 -/* 9047 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 9095 -/* 9051 */ MCD_OPC_Decode, 212, 18, 146, 2, // Opcode: VGFMAB -/* 9056 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9069 -/* 9060 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 9095 -/* 9064 */ MCD_OPC_Decode, 215, 18, 146, 2, // Opcode: VGFMAH -/* 9069 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9082 -/* 9073 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 9095 -/* 9077 */ MCD_OPC_Decode, 213, 18, 146, 2, // Opcode: VGFMAF -/* 9082 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9095 -/* 9086 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9095 -/* 9090 */ MCD_OPC_Decode, 214, 18, 146, 2, // Opcode: VGFMAG -/* 9095 */ MCD_OPC_CheckPredicate, 22, 8, 39, // Skip to: 19091 -/* 9099 */ MCD_OPC_Decode, 211, 18, 150, 2, // Opcode: VGFMA -/* 9104 */ MCD_OPC_FilterValue, 189, 1, 31, 0, // Skip to: 9140 -/* 9109 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 9112 */ MCD_OPC_FilterValue, 0, 247, 38, // Skip to: 19091 -/* 9116 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9131 -/* 9120 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, // Skip to: 9131 -/* 9126 */ MCD_OPC_Decode, 167, 20, 146, 2, // Opcode: VSBCBIQ -/* 9131 */ MCD_OPC_CheckPredicate, 22, 228, 38, // Skip to: 19091 -/* 9135 */ MCD_OPC_Decode, 166, 20, 150, 2, // Opcode: VSBCBI -/* 9140 */ MCD_OPC_FilterValue, 191, 1, 31, 0, // Skip to: 9176 -/* 9145 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 9148 */ MCD_OPC_FilterValue, 0, 211, 38, // Skip to: 19091 -/* 9152 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9167 -/* 9156 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, // Skip to: 9167 -/* 9162 */ MCD_OPC_Decode, 169, 20, 146, 2, // Opcode: VSBIQ -/* 9167 */ MCD_OPC_CheckPredicate, 22, 192, 38, // Skip to: 19091 -/* 9171 */ MCD_OPC_Decode, 168, 20, 150, 2, // Opcode: VSBI -/* 9176 */ MCD_OPC_FilterValue, 192, 1, 54, 0, // Skip to: 9235 -/* 9181 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9184 */ MCD_OPC_FilterValue, 0, 175, 38, // Skip to: 19091 -/* 9188 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 9191 */ MCD_OPC_FilterValue, 0, 168, 38, // Skip to: 19091 -/* 9195 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 9198 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9226 -/* 9202 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9217 -/* 9206 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9217 -/* 9212 */ MCD_OPC_Decode, 252, 20, 151, 2, // Opcode: WCLGDB -/* 9217 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9226 -/* 9221 */ MCD_OPC_Decode, 145, 17, 152, 2, // Opcode: VCLGDB -/* 9226 */ MCD_OPC_CheckPredicate, 22, 133, 38, // Skip to: 19091 -/* 9230 */ MCD_OPC_Decode, 144, 17, 153, 2, // Opcode: VCLGD -/* 9235 */ MCD_OPC_FilterValue, 193, 1, 54, 0, // Skip to: 9294 -/* 9240 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9243 */ MCD_OPC_FilterValue, 0, 116, 38, // Skip to: 19091 -/* 9247 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 9250 */ MCD_OPC_FilterValue, 0, 109, 38, // Skip to: 19091 -/* 9254 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 9257 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9285 -/* 9261 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9276 -/* 9265 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9276 -/* 9271 */ MCD_OPC_Decode, 250, 20, 151, 2, // Opcode: WCDLGB -/* 9276 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9285 -/* 9280 */ MCD_OPC_Decode, 241, 16, 152, 2, // Opcode: VCDLGB -/* 9285 */ MCD_OPC_CheckPredicate, 22, 74, 38, // Skip to: 19091 -/* 9289 */ MCD_OPC_Decode, 240, 16, 153, 2, // Opcode: VCDLG -/* 9294 */ MCD_OPC_FilterValue, 194, 1, 54, 0, // Skip to: 9353 -/* 9299 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9302 */ MCD_OPC_FilterValue, 0, 57, 38, // Skip to: 19091 -/* 9306 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 9309 */ MCD_OPC_FilterValue, 0, 50, 38, // Skip to: 19091 -/* 9313 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 9316 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9344 -/* 9320 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9335 -/* 9324 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9335 -/* 9330 */ MCD_OPC_Decode, 251, 20, 151, 2, // Opcode: WCGDB -/* 9335 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9344 -/* 9339 */ MCD_OPC_Decode, 252, 16, 152, 2, // Opcode: VCGDB -/* 9344 */ MCD_OPC_CheckPredicate, 22, 15, 38, // Skip to: 19091 -/* 9348 */ MCD_OPC_Decode, 251, 16, 153, 2, // Opcode: VCGD -/* 9353 */ MCD_OPC_FilterValue, 195, 1, 54, 0, // Skip to: 9412 -/* 9358 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9361 */ MCD_OPC_FilterValue, 0, 254, 37, // Skip to: 19091 -/* 9365 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 9368 */ MCD_OPC_FilterValue, 0, 247, 37, // Skip to: 19091 -/* 9372 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 9375 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9403 -/* 9379 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9394 -/* 9383 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9394 -/* 9389 */ MCD_OPC_Decode, 249, 20, 151, 2, // Opcode: WCDGB -/* 9394 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9403 -/* 9398 */ MCD_OPC_Decode, 239, 16, 152, 2, // Opcode: VCDGB -/* 9403 */ MCD_OPC_CheckPredicate, 22, 212, 37, // Skip to: 19091 -/* 9407 */ MCD_OPC_Decode, 238, 16, 153, 2, // Opcode: VCDG -/* 9412 */ MCD_OPC_FilterValue, 196, 1, 67, 0, // Skip to: 9484 -/* 9417 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9420 */ MCD_OPC_FilterValue, 0, 195, 37, // Skip to: 19091 -/* 9424 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... -/* 9427 */ MCD_OPC_FilterValue, 0, 188, 37, // Skip to: 19091 -/* 9431 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 9434 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9447 -/* 9438 */ MCD_OPC_CheckPredicate, 22, 33, 0, // Skip to: 9475 -/* 9442 */ MCD_OPC_Decode, 240, 18, 254, 1, // Opcode: VLDEB -/* 9447 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 9461 -/* 9452 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 9475 -/* 9456 */ MCD_OPC_Decode, 224, 21, 154, 2, // Opcode: WLDEB -/* 9461 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 9475 -/* 9466 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 9475 -/* 9470 */ MCD_OPC_Decode, 181, 21, 155, 2, // Opcode: WFLLD -/* 9475 */ MCD_OPC_CheckPredicate, 22, 140, 37, // Skip to: 19091 -/* 9479 */ MCD_OPC_Decode, 239, 18, 156, 2, // Opcode: VLDE -/* 9484 */ MCD_OPC_FilterValue, 197, 1, 73, 0, // Skip to: 9562 -/* 9489 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9492 */ MCD_OPC_FilterValue, 0, 123, 37, // Skip to: 19091 -/* 9496 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 9499 */ MCD_OPC_FilterValue, 0, 116, 37, // Skip to: 19091 -/* 9503 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 9506 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9534 -/* 9510 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9525 -/* 9514 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9525 -/* 9520 */ MCD_OPC_Decode, 225, 21, 157, 2, // Opcode: WLEDB -/* 9525 */ MCD_OPC_CheckPredicate, 22, 24, 0, // Skip to: 9553 -/* 9529 */ MCD_OPC_Decode, 243, 18, 152, 2, // Opcode: VLEDB -/* 9534 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 9553 -/* 9538 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 9553 -/* 9542 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9553 -/* 9548 */ MCD_OPC_Decode, 190, 21, 158, 2, // Opcode: WFLRX -/* 9553 */ MCD_OPC_CheckPredicate, 22, 62, 37, // Skip to: 19091 -/* 9557 */ MCD_OPC_Decode, 242, 18, 153, 2, // Opcode: VLED -/* 9562 */ MCD_OPC_FilterValue, 199, 1, 101, 0, // Skip to: 9668 -/* 9567 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9570 */ MCD_OPC_FilterValue, 0, 45, 37, // Skip to: 19091 -/* 9574 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 9577 */ MCD_OPC_FilterValue, 0, 38, 37, // Skip to: 19091 -/* 9581 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 9584 */ MCD_OPC_FilterValue, 2, 24, 0, // Skip to: 9612 -/* 9588 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 9603 -/* 9592 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9603 -/* 9598 */ MCD_OPC_Decode, 154, 21, 159, 2, // Opcode: WFISB -/* 9603 */ MCD_OPC_CheckPredicate, 23, 52, 0, // Skip to: 9659 -/* 9607 */ MCD_OPC_Decode, 151, 18, 152, 2, // Opcode: VFISB -/* 9612 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9640 -/* 9616 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9631 -/* 9620 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9631 -/* 9626 */ MCD_OPC_Decode, 153, 21, 151, 2, // Opcode: WFIDB -/* 9631 */ MCD_OPC_CheckPredicate, 22, 24, 0, // Skip to: 9659 -/* 9635 */ MCD_OPC_Decode, 150, 18, 152, 2, // Opcode: VFIDB -/* 9640 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 9659 -/* 9644 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 9659 -/* 9648 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9659 -/* 9654 */ MCD_OPC_Decode, 155, 21, 160, 2, // Opcode: WFIXB -/* 9659 */ MCD_OPC_CheckPredicate, 22, 212, 36, // Skip to: 19091 -/* 9663 */ MCD_OPC_Decode, 149, 18, 153, 2, // Opcode: VFI -/* 9668 */ MCD_OPC_FilterValue, 202, 1, 65, 0, // Skip to: 9738 -/* 9673 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9676 */ MCD_OPC_FilterValue, 0, 195, 36, // Skip to: 19091 -/* 9680 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... -/* 9683 */ MCD_OPC_FilterValue, 0, 188, 36, // Skip to: 19091 -/* 9687 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 9690 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9703 -/* 9694 */ MCD_OPC_CheckPredicate, 23, 31, 0, // Skip to: 9729 -/* 9698 */ MCD_OPC_Decode, 176, 21, 161, 2, // Opcode: WFKSB -/* 9703 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9716 -/* 9707 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 9729 -/* 9711 */ MCD_OPC_Decode, 157, 21, 162, 2, // Opcode: WFKDB -/* 9716 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9729 -/* 9720 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 9729 -/* 9724 */ MCD_OPC_Decode, 177, 21, 254, 1, // Opcode: WFKXB -/* 9729 */ MCD_OPC_CheckPredicate, 22, 142, 36, // Skip to: 19091 -/* 9733 */ MCD_OPC_Decode, 156, 21, 163, 2, // Opcode: WFK -/* 9738 */ MCD_OPC_FilterValue, 203, 1, 65, 0, // Skip to: 9808 -/* 9743 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9746 */ MCD_OPC_FilterValue, 0, 125, 36, // Skip to: 19091 -/* 9750 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... -/* 9753 */ MCD_OPC_FilterValue, 0, 118, 36, // Skip to: 19091 -/* 9757 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 9760 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9773 -/* 9764 */ MCD_OPC_CheckPredicate, 23, 31, 0, // Skip to: 9799 -/* 9768 */ MCD_OPC_Decode, 148, 21, 161, 2, // Opcode: WFCSB -/* 9773 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9786 -/* 9777 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 9799 -/* 9781 */ MCD_OPC_Decode, 129, 21, 162, 2, // Opcode: WFCDB -/* 9786 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9799 -/* 9790 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 9799 -/* 9794 */ MCD_OPC_Decode, 149, 21, 254, 1, // Opcode: WFCXB -/* 9799 */ MCD_OPC_CheckPredicate, 22, 72, 36, // Skip to: 19091 -/* 9803 */ MCD_OPC_Decode, 128, 21, 163, 2, // Opcode: WFC -/* 9808 */ MCD_OPC_FilterValue, 204, 1, 49, 1, // Skip to: 10118 -/* 9813 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9816 */ MCD_OPC_FilterValue, 0, 55, 36, // Skip to: 19091 -/* 9820 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 9823 */ MCD_OPC_FilterValue, 0, 48, 36, // Skip to: 19091 -/* 9827 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... -/* 9830 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9843 -/* 9834 */ MCD_OPC_CheckPredicate, 23, 200, 0, // Skip to: 10038 -/* 9838 */ MCD_OPC_Decode, 165, 18, 254, 1, // Opcode: VFLCSB -/* 9843 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9856 -/* 9847 */ MCD_OPC_CheckPredicate, 22, 187, 0, // Skip to: 10038 -/* 9851 */ MCD_OPC_Decode, 164, 18, 254, 1, // Opcode: VFLCDB -/* 9856 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 9870 -/* 9861 */ MCD_OPC_CheckPredicate, 23, 173, 0, // Skip to: 10038 -/* 9865 */ MCD_OPC_Decode, 179, 21, 161, 2, // Opcode: WFLCSB -/* 9870 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 9884 -/* 9875 */ MCD_OPC_CheckPredicate, 22, 159, 0, // Skip to: 10038 -/* 9879 */ MCD_OPC_Decode, 178, 21, 162, 2, // Opcode: WFLCDB -/* 9884 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 9898 -/* 9889 */ MCD_OPC_CheckPredicate, 23, 145, 0, // Skip to: 10038 -/* 9893 */ MCD_OPC_Decode, 180, 21, 254, 1, // Opcode: WFLCXB -/* 9898 */ MCD_OPC_FilterValue, 130, 2, 9, 0, // Skip to: 9912 -/* 9903 */ MCD_OPC_CheckPredicate, 23, 131, 0, // Skip to: 10038 -/* 9907 */ MCD_OPC_Decode, 169, 18, 254, 1, // Opcode: VFLNSB -/* 9912 */ MCD_OPC_FilterValue, 131, 2, 9, 0, // Skip to: 9926 -/* 9917 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 10038 -/* 9921 */ MCD_OPC_Decode, 168, 18, 254, 1, // Opcode: VFLNDB -/* 9926 */ MCD_OPC_FilterValue, 130, 3, 9, 0, // Skip to: 9940 -/* 9931 */ MCD_OPC_CheckPredicate, 23, 103, 0, // Skip to: 10038 -/* 9935 */ MCD_OPC_Decode, 184, 21, 161, 2, // Opcode: WFLNSB -/* 9940 */ MCD_OPC_FilterValue, 131, 3, 9, 0, // Skip to: 9954 -/* 9945 */ MCD_OPC_CheckPredicate, 22, 89, 0, // Skip to: 10038 -/* 9949 */ MCD_OPC_Decode, 183, 21, 162, 2, // Opcode: WFLNDB -/* 9954 */ MCD_OPC_FilterValue, 132, 3, 9, 0, // Skip to: 9968 -/* 9959 */ MCD_OPC_CheckPredicate, 23, 75, 0, // Skip to: 10038 -/* 9963 */ MCD_OPC_Decode, 185, 21, 254, 1, // Opcode: WFLNXB -/* 9968 */ MCD_OPC_FilterValue, 130, 4, 9, 0, // Skip to: 9982 -/* 9973 */ MCD_OPC_CheckPredicate, 23, 61, 0, // Skip to: 10038 -/* 9977 */ MCD_OPC_Decode, 171, 18, 254, 1, // Opcode: VFLPSB -/* 9982 */ MCD_OPC_FilterValue, 131, 4, 9, 0, // Skip to: 9996 -/* 9987 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 10038 -/* 9991 */ MCD_OPC_Decode, 170, 18, 254, 1, // Opcode: VFLPDB -/* 9996 */ MCD_OPC_FilterValue, 130, 5, 9, 0, // Skip to: 10010 -/* 10001 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 10038 -/* 10005 */ MCD_OPC_Decode, 187, 21, 161, 2, // Opcode: WFLPSB -/* 10010 */ MCD_OPC_FilterValue, 131, 5, 9, 0, // Skip to: 10024 -/* 10015 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 10038 -/* 10019 */ MCD_OPC_Decode, 186, 21, 162, 2, // Opcode: WFLPDB -/* 10024 */ MCD_OPC_FilterValue, 132, 5, 9, 0, // Skip to: 10038 -/* 10029 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 10038 -/* 10033 */ MCD_OPC_Decode, 188, 21, 254, 1, // Opcode: WFLPXB -/* 10038 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 10041 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10054 -/* 10045 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 10109 -/* 10049 */ MCD_OPC_Decode, 197, 18, 128, 2, // Opcode: VFPSOSB -/* 10054 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10067 -/* 10058 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 10109 -/* 10062 */ MCD_OPC_Decode, 196, 18, 128, 2, // Opcode: VFPSODB -/* 10067 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 10081 -/* 10072 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 10109 -/* 10076 */ MCD_OPC_Decode, 213, 21, 164, 2, // Opcode: WFPSOSB -/* 10081 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 10095 -/* 10086 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 10109 -/* 10090 */ MCD_OPC_Decode, 212, 21, 165, 2, // Opcode: WFPSODB -/* 10095 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 10109 -/* 10100 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 10109 -/* 10104 */ MCD_OPC_Decode, 214, 21, 128, 2, // Opcode: WFPSOXB -/* 10109 */ MCD_OPC_CheckPredicate, 22, 18, 35, // Skip to: 19091 -/* 10113 */ MCD_OPC_Decode, 195, 18, 153, 2, // Opcode: VFPSO -/* 10118 */ MCD_OPC_FilterValue, 206, 1, 94, 0, // Skip to: 10217 -/* 10123 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 10126 */ MCD_OPC_FilterValue, 0, 1, 35, // Skip to: 19091 -/* 10130 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... -/* 10133 */ MCD_OPC_FilterValue, 0, 250, 34, // Skip to: 19091 -/* 10137 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 10140 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10153 -/* 10144 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 10208 -/* 10148 */ MCD_OPC_Decode, 202, 18, 254, 1, // Opcode: VFSQSB -/* 10153 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10166 -/* 10157 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 10208 -/* 10161 */ MCD_OPC_Decode, 201, 18, 254, 1, // Opcode: VFSQDB -/* 10166 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 10180 -/* 10171 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 10208 -/* 10175 */ MCD_OPC_Decode, 217, 21, 161, 2, // Opcode: WFSQSB -/* 10180 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 10194 -/* 10185 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 10208 -/* 10189 */ MCD_OPC_Decode, 216, 21, 162, 2, // Opcode: WFSQDB -/* 10194 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 10208 -/* 10199 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 10208 -/* 10203 */ MCD_OPC_Decode, 218, 21, 254, 1, // Opcode: WFSQXB -/* 10208 */ MCD_OPC_CheckPredicate, 22, 175, 34, // Skip to: 19091 -/* 10212 */ MCD_OPC_Decode, 200, 18, 156, 2, // Opcode: VFSQ -/* 10217 */ MCD_OPC_FilterValue, 212, 1, 65, 0, // Skip to: 10287 -/* 10222 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 10225 */ MCD_OPC_FilterValue, 0, 158, 34, // Skip to: 19091 -/* 10229 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 10232 */ MCD_OPC_FilterValue, 0, 151, 34, // Skip to: 19091 -/* 10236 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 10239 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10252 -/* 10243 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10278 -/* 10247 */ MCD_OPC_Decode, 244, 20, 254, 1, // Opcode: VUPLLB -/* 10252 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10265 -/* 10256 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10278 -/* 10260 */ MCD_OPC_Decode, 246, 20, 254, 1, // Opcode: VUPLLH -/* 10265 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10278 -/* 10269 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10278 -/* 10273 */ MCD_OPC_Decode, 245, 20, 254, 1, // Opcode: VUPLLF -/* 10278 */ MCD_OPC_CheckPredicate, 22, 105, 34, // Skip to: 19091 -/* 10282 */ MCD_OPC_Decode, 243, 20, 255, 1, // Opcode: VUPLL -/* 10287 */ MCD_OPC_FilterValue, 213, 1, 65, 0, // Skip to: 10357 -/* 10292 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 10295 */ MCD_OPC_FilterValue, 0, 88, 34, // Skip to: 19091 -/* 10299 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 10302 */ MCD_OPC_FilterValue, 0, 81, 34, // Skip to: 19091 -/* 10306 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 10309 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10322 -/* 10313 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10348 -/* 10317 */ MCD_OPC_Decode, 239, 20, 254, 1, // Opcode: VUPLHB -/* 10322 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10335 -/* 10326 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10348 -/* 10330 */ MCD_OPC_Decode, 241, 20, 254, 1, // Opcode: VUPLHH -/* 10335 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10348 -/* 10339 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10348 -/* 10343 */ MCD_OPC_Decode, 240, 20, 254, 1, // Opcode: VUPLHF -/* 10348 */ MCD_OPC_CheckPredicate, 22, 35, 34, // Skip to: 19091 -/* 10352 */ MCD_OPC_Decode, 238, 20, 255, 1, // Opcode: VUPLH -/* 10357 */ MCD_OPC_FilterValue, 214, 1, 65, 0, // Skip to: 10427 -/* 10362 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 10365 */ MCD_OPC_FilterValue, 0, 18, 34, // Skip to: 19091 -/* 10369 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 10372 */ MCD_OPC_FilterValue, 0, 11, 34, // Skip to: 19091 -/* 10376 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 10379 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10392 -/* 10383 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10418 -/* 10387 */ MCD_OPC_Decode, 236, 20, 254, 1, // Opcode: VUPLB -/* 10392 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10405 -/* 10396 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10418 -/* 10400 */ MCD_OPC_Decode, 242, 20, 254, 1, // Opcode: VUPLHW -/* 10405 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10418 -/* 10409 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10418 -/* 10413 */ MCD_OPC_Decode, 237, 20, 254, 1, // Opcode: VUPLF -/* 10418 */ MCD_OPC_CheckPredicate, 22, 221, 33, // Skip to: 19091 -/* 10422 */ MCD_OPC_Decode, 235, 20, 255, 1, // Opcode: VUPL -/* 10427 */ MCD_OPC_FilterValue, 215, 1, 65, 0, // Skip to: 10497 -/* 10432 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 10435 */ MCD_OPC_FilterValue, 0, 204, 33, // Skip to: 19091 -/* 10439 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 10442 */ MCD_OPC_FilterValue, 0, 197, 33, // Skip to: 19091 -/* 10446 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 10449 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10462 -/* 10453 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10488 -/* 10457 */ MCD_OPC_Decode, 231, 20, 254, 1, // Opcode: VUPHB -/* 10462 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10475 -/* 10466 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10488 -/* 10470 */ MCD_OPC_Decode, 233, 20, 254, 1, // Opcode: VUPHH -/* 10475 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10488 -/* 10479 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10488 -/* 10483 */ MCD_OPC_Decode, 232, 20, 254, 1, // Opcode: VUPHF -/* 10488 */ MCD_OPC_CheckPredicate, 22, 151, 33, // Skip to: 19091 -/* 10492 */ MCD_OPC_Decode, 230, 20, 255, 1, // Opcode: VUPH -/* 10497 */ MCD_OPC_FilterValue, 216, 1, 21, 0, // Skip to: 10523 -/* 10502 */ MCD_OPC_CheckPredicate, 22, 137, 33, // Skip to: 19091 -/* 10506 */ MCD_OPC_CheckField, 12, 20, 0, 131, 33, // Skip to: 19091 -/* 10512 */ MCD_OPC_CheckField, 8, 2, 0, 125, 33, // Skip to: 19091 -/* 10518 */ MCD_OPC_Decode, 228, 20, 254, 1, // Opcode: VTM -/* 10523 */ MCD_OPC_FilterValue, 217, 1, 78, 0, // Skip to: 10606 -/* 10528 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 10531 */ MCD_OPC_FilterValue, 0, 108, 33, // Skip to: 19091 -/* 10535 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 10538 */ MCD_OPC_FilterValue, 0, 101, 33, // Skip to: 19091 -/* 10542 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 10545 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10558 -/* 10549 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 10597 -/* 10553 */ MCD_OPC_Decode, 168, 17, 254, 1, // Opcode: VECLB -/* 10558 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10571 -/* 10562 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10597 -/* 10566 */ MCD_OPC_Decode, 171, 17, 254, 1, // Opcode: VECLH -/* 10571 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10584 -/* 10575 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10597 -/* 10579 */ MCD_OPC_Decode, 169, 17, 254, 1, // Opcode: VECLF -/* 10584 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10597 -/* 10588 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10597 -/* 10592 */ MCD_OPC_Decode, 170, 17, 254, 1, // Opcode: VECLG -/* 10597 */ MCD_OPC_CheckPredicate, 22, 42, 33, // Skip to: 19091 -/* 10601 */ MCD_OPC_Decode, 167, 17, 255, 1, // Opcode: VECL -/* 10606 */ MCD_OPC_FilterValue, 219, 1, 78, 0, // Skip to: 10689 -/* 10611 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 10614 */ MCD_OPC_FilterValue, 0, 25, 33, // Skip to: 19091 -/* 10618 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 10621 */ MCD_OPC_FilterValue, 0, 18, 33, // Skip to: 19091 -/* 10625 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 10628 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10641 -/* 10632 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 10680 -/* 10636 */ MCD_OPC_Decode, 163, 17, 254, 1, // Opcode: VECB -/* 10641 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10654 -/* 10645 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10680 -/* 10649 */ MCD_OPC_Decode, 166, 17, 254, 1, // Opcode: VECH -/* 10654 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10667 -/* 10658 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10680 -/* 10662 */ MCD_OPC_Decode, 164, 17, 254, 1, // Opcode: VECF -/* 10667 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10680 -/* 10671 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10680 -/* 10675 */ MCD_OPC_Decode, 165, 17, 254, 1, // Opcode: VECG -/* 10680 */ MCD_OPC_CheckPredicate, 22, 215, 32, // Skip to: 19091 -/* 10684 */ MCD_OPC_Decode, 162, 17, 255, 1, // Opcode: VEC -/* 10689 */ MCD_OPC_FilterValue, 222, 1, 78, 0, // Skip to: 10772 -/* 10694 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 10697 */ MCD_OPC_FilterValue, 0, 198, 32, // Skip to: 19091 -/* 10701 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 10704 */ MCD_OPC_FilterValue, 0, 191, 32, // Skip to: 19091 -/* 10708 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 10711 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10724 -/* 10715 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 10763 -/* 10719 */ MCD_OPC_Decode, 235, 18, 254, 1, // Opcode: VLCB -/* 10724 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10737 -/* 10728 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10763 -/* 10732 */ MCD_OPC_Decode, 238, 18, 254, 1, // Opcode: VLCH -/* 10737 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10750 -/* 10741 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10763 -/* 10745 */ MCD_OPC_Decode, 236, 18, 254, 1, // Opcode: VLCF -/* 10750 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10763 -/* 10754 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10763 -/* 10758 */ MCD_OPC_Decode, 237, 18, 254, 1, // Opcode: VLCG -/* 10763 */ MCD_OPC_CheckPredicate, 22, 132, 32, // Skip to: 19091 -/* 10767 */ MCD_OPC_Decode, 234, 18, 255, 1, // Opcode: VLC -/* 10772 */ MCD_OPC_FilterValue, 223, 1, 78, 0, // Skip to: 10855 -/* 10777 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 10780 */ MCD_OPC_FilterValue, 0, 115, 32, // Skip to: 19091 -/* 10784 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 10787 */ MCD_OPC_FilterValue, 0, 108, 32, // Skip to: 19091 -/* 10791 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 10794 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10807 -/* 10798 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 10846 -/* 10802 */ MCD_OPC_Decode, 138, 19, 254, 1, // Opcode: VLPB -/* 10807 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10820 -/* 10811 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10846 -/* 10815 */ MCD_OPC_Decode, 141, 19, 254, 1, // Opcode: VLPH -/* 10820 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10833 -/* 10824 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10846 -/* 10828 */ MCD_OPC_Decode, 139, 19, 254, 1, // Opcode: VLPF -/* 10833 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10846 -/* 10837 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10846 -/* 10841 */ MCD_OPC_Decode, 140, 19, 254, 1, // Opcode: VLPG -/* 10846 */ MCD_OPC_CheckPredicate, 22, 49, 32, // Skip to: 19091 -/* 10850 */ MCD_OPC_Decode, 137, 19, 255, 1, // Opcode: VLP -/* 10855 */ MCD_OPC_FilterValue, 226, 1, 94, 0, // Skip to: 10954 -/* 10860 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 10863 */ MCD_OPC_FilterValue, 0, 32, 32, // Skip to: 19091 -/* 10867 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... -/* 10870 */ MCD_OPC_FilterValue, 0, 25, 32, // Skip to: 19091 -/* 10874 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 10877 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10890 -/* 10881 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 10945 -/* 10885 */ MCD_OPC_Decode, 203, 18, 130, 2, // Opcode: VFSSB -/* 10890 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10903 -/* 10894 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 10945 -/* 10898 */ MCD_OPC_Decode, 199, 18, 130, 2, // Opcode: VFSDB -/* 10903 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 10917 -/* 10908 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 10945 -/* 10912 */ MCD_OPC_Decode, 219, 21, 166, 2, // Opcode: WFSSB -/* 10917 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 10931 -/* 10922 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 10945 -/* 10926 */ MCD_OPC_Decode, 215, 21, 167, 2, // Opcode: WFSDB -/* 10931 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 10945 -/* 10936 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 10945 -/* 10940 */ MCD_OPC_Decode, 220, 21, 130, 2, // Opcode: WFSXB -/* 10945 */ MCD_OPC_CheckPredicate, 22, 206, 31, // Skip to: 19091 -/* 10949 */ MCD_OPC_Decode, 198, 18, 168, 2, // Opcode: VFS -/* 10954 */ MCD_OPC_FilterValue, 227, 1, 94, 0, // Skip to: 11053 -/* 10959 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 10962 */ MCD_OPC_FilterValue, 0, 189, 31, // Skip to: 19091 -/* 10966 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... -/* 10969 */ MCD_OPC_FilterValue, 0, 182, 31, // Skip to: 19091 -/* 10973 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 10976 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10989 -/* 10980 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 11044 -/* 10984 */ MCD_OPC_Decode, 232, 17, 130, 2, // Opcode: VFASB -/* 10989 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11002 -/* 10993 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 11044 -/* 10997 */ MCD_OPC_Decode, 218, 17, 130, 2, // Opcode: VFADB -/* 11002 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11016 -/* 11007 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11044 -/* 11011 */ MCD_OPC_Decode, 254, 20, 166, 2, // Opcode: WFASB -/* 11016 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11030 -/* 11021 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 11044 -/* 11025 */ MCD_OPC_Decode, 253, 20, 167, 2, // Opcode: WFADB -/* 11030 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11044 -/* 11035 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11044 -/* 11039 */ MCD_OPC_Decode, 255, 20, 130, 2, // Opcode: WFAXB -/* 11044 */ MCD_OPC_CheckPredicate, 22, 107, 31, // Skip to: 19091 -/* 11048 */ MCD_OPC_Decode, 217, 17, 168, 2, // Opcode: VFA -/* 11053 */ MCD_OPC_FilterValue, 229, 1, 94, 0, // Skip to: 11152 -/* 11058 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 11061 */ MCD_OPC_FilterValue, 0, 90, 31, // Skip to: 19091 -/* 11065 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... -/* 11068 */ MCD_OPC_FilterValue, 0, 83, 31, // Skip to: 19091 -/* 11072 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 11075 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11088 -/* 11079 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 11143 -/* 11083 */ MCD_OPC_Decode, 250, 17, 130, 2, // Opcode: VFDSB -/* 11088 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11101 -/* 11092 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 11143 -/* 11096 */ MCD_OPC_Decode, 249, 17, 130, 2, // Opcode: VFDDB -/* 11101 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11115 -/* 11106 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11143 -/* 11110 */ MCD_OPC_Decode, 151, 21, 166, 2, // Opcode: WFDSB -/* 11115 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11129 -/* 11120 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 11143 -/* 11124 */ MCD_OPC_Decode, 150, 21, 167, 2, // Opcode: WFDDB -/* 11129 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11143 -/* 11134 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11143 -/* 11138 */ MCD_OPC_Decode, 152, 21, 130, 2, // Opcode: WFDXB -/* 11143 */ MCD_OPC_CheckPredicate, 22, 8, 31, // Skip to: 19091 -/* 11147 */ MCD_OPC_Decode, 248, 17, 168, 2, // Opcode: VFD -/* 11152 */ MCD_OPC_FilterValue, 231, 1, 94, 0, // Skip to: 11251 -/* 11157 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 11160 */ MCD_OPC_FilterValue, 0, 247, 30, // Skip to: 19091 -/* 11164 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... -/* 11167 */ MCD_OPC_FilterValue, 0, 240, 30, // Skip to: 19091 -/* 11171 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 11174 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11187 -/* 11178 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 11242 -/* 11182 */ MCD_OPC_Decode, 186, 18, 130, 2, // Opcode: VFMSB -/* 11187 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11200 -/* 11191 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 11242 -/* 11195 */ MCD_OPC_Decode, 181, 18, 130, 2, // Opcode: VFMDB -/* 11200 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11214 -/* 11205 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11242 -/* 11209 */ MCD_OPC_Decode, 201, 21, 166, 2, // Opcode: WFMSB -/* 11214 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11228 -/* 11219 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 11242 -/* 11223 */ MCD_OPC_Decode, 197, 21, 167, 2, // Opcode: WFMDB -/* 11228 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11242 -/* 11233 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11242 -/* 11237 */ MCD_OPC_Decode, 205, 21, 130, 2, // Opcode: WFMXB -/* 11242 */ MCD_OPC_CheckPredicate, 22, 165, 30, // Skip to: 19091 -/* 11246 */ MCD_OPC_Decode, 174, 18, 168, 2, // Opcode: VFM -/* 11251 */ MCD_OPC_FilterValue, 232, 1, 46, 1, // Skip to: 11558 -/* 11256 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 11259 */ MCD_OPC_FilterValue, 0, 148, 30, // Skip to: 19091 -/* 11263 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 11266 */ MCD_OPC_FilterValue, 0, 141, 30, // Skip to: 19091 -/* 11270 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... -/* 11273 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11286 -/* 11277 */ MCD_OPC_CheckPredicate, 23, 12, 1, // Skip to: 11549 -/* 11281 */ MCD_OPC_Decode, 236, 17, 130, 2, // Opcode: VFCESB -/* 11286 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11299 -/* 11290 */ MCD_OPC_CheckPredicate, 22, 255, 0, // Skip to: 11549 -/* 11294 */ MCD_OPC_Decode, 234, 17, 130, 2, // Opcode: VFCEDB -/* 11299 */ MCD_OPC_FilterValue, 66, 9, 0, // Skip to: 11312 -/* 11303 */ MCD_OPC_CheckPredicate, 23, 242, 0, // Skip to: 11549 -/* 11307 */ MCD_OPC_Decode, 154, 18, 130, 2, // Opcode: VFKESB -/* 11312 */ MCD_OPC_FilterValue, 67, 9, 0, // Skip to: 11325 -/* 11316 */ MCD_OPC_CheckPredicate, 23, 229, 0, // Skip to: 11549 -/* 11320 */ MCD_OPC_Decode, 152, 18, 130, 2, // Opcode: VFKEDB -/* 11325 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11339 -/* 11330 */ MCD_OPC_CheckPredicate, 23, 215, 0, // Skip to: 11549 -/* 11334 */ MCD_OPC_Decode, 132, 21, 166, 2, // Opcode: WFCESB -/* 11339 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11353 -/* 11344 */ MCD_OPC_CheckPredicate, 22, 201, 0, // Skip to: 11549 -/* 11348 */ MCD_OPC_Decode, 130, 21, 167, 2, // Opcode: WFCEDB -/* 11353 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11367 -/* 11358 */ MCD_OPC_CheckPredicate, 23, 187, 0, // Skip to: 11549 -/* 11362 */ MCD_OPC_Decode, 134, 21, 130, 2, // Opcode: WFCEXB -/* 11367 */ MCD_OPC_FilterValue, 194, 1, 9, 0, // Skip to: 11381 -/* 11372 */ MCD_OPC_CheckPredicate, 23, 173, 0, // Skip to: 11549 -/* 11376 */ MCD_OPC_Decode, 160, 21, 166, 2, // Opcode: WFKESB -/* 11381 */ MCD_OPC_FilterValue, 195, 1, 9, 0, // Skip to: 11395 -/* 11386 */ MCD_OPC_CheckPredicate, 23, 159, 0, // Skip to: 11549 -/* 11390 */ MCD_OPC_Decode, 158, 21, 167, 2, // Opcode: WFKEDB -/* 11395 */ MCD_OPC_FilterValue, 196, 1, 9, 0, // Skip to: 11409 -/* 11400 */ MCD_OPC_CheckPredicate, 23, 145, 0, // Skip to: 11549 -/* 11404 */ MCD_OPC_Decode, 162, 21, 130, 2, // Opcode: WFKEXB -/* 11409 */ MCD_OPC_FilterValue, 130, 2, 9, 0, // Skip to: 11423 -/* 11414 */ MCD_OPC_CheckPredicate, 23, 131, 0, // Skip to: 11549 -/* 11418 */ MCD_OPC_Decode, 237, 17, 130, 2, // Opcode: VFCESBS -/* 11423 */ MCD_OPC_FilterValue, 131, 2, 9, 0, // Skip to: 11437 -/* 11428 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 11549 -/* 11432 */ MCD_OPC_Decode, 235, 17, 130, 2, // Opcode: VFCEDBS -/* 11437 */ MCD_OPC_FilterValue, 194, 2, 9, 0, // Skip to: 11451 -/* 11442 */ MCD_OPC_CheckPredicate, 23, 103, 0, // Skip to: 11549 -/* 11446 */ MCD_OPC_Decode, 155, 18, 130, 2, // Opcode: VFKESBS -/* 11451 */ MCD_OPC_FilterValue, 195, 2, 9, 0, // Skip to: 11465 -/* 11456 */ MCD_OPC_CheckPredicate, 23, 89, 0, // Skip to: 11549 -/* 11460 */ MCD_OPC_Decode, 153, 18, 130, 2, // Opcode: VFKEDBS -/* 11465 */ MCD_OPC_FilterValue, 130, 3, 9, 0, // Skip to: 11479 -/* 11470 */ MCD_OPC_CheckPredicate, 23, 75, 0, // Skip to: 11549 -/* 11474 */ MCD_OPC_Decode, 133, 21, 166, 2, // Opcode: WFCESBS -/* 11479 */ MCD_OPC_FilterValue, 131, 3, 9, 0, // Skip to: 11493 -/* 11484 */ MCD_OPC_CheckPredicate, 22, 61, 0, // Skip to: 11549 -/* 11488 */ MCD_OPC_Decode, 131, 21, 167, 2, // Opcode: WFCEDBS -/* 11493 */ MCD_OPC_FilterValue, 132, 3, 9, 0, // Skip to: 11507 -/* 11498 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 11549 -/* 11502 */ MCD_OPC_Decode, 135, 21, 130, 2, // Opcode: WFCEXBS -/* 11507 */ MCD_OPC_FilterValue, 194, 3, 9, 0, // Skip to: 11521 -/* 11512 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11549 -/* 11516 */ MCD_OPC_Decode, 161, 21, 166, 2, // Opcode: WFKESBS -/* 11521 */ MCD_OPC_FilterValue, 195, 3, 9, 0, // Skip to: 11535 -/* 11526 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 11549 -/* 11530 */ MCD_OPC_Decode, 159, 21, 167, 2, // Opcode: WFKEDBS -/* 11535 */ MCD_OPC_FilterValue, 196, 3, 9, 0, // Skip to: 11549 -/* 11540 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11549 -/* 11544 */ MCD_OPC_Decode, 163, 21, 130, 2, // Opcode: WFKEXBS -/* 11549 */ MCD_OPC_CheckPredicate, 22, 114, 29, // Skip to: 19091 -/* 11553 */ MCD_OPC_Decode, 233, 17, 169, 2, // Opcode: VFCE -/* 11558 */ MCD_OPC_FilterValue, 234, 1, 46, 1, // Skip to: 11865 -/* 11563 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 11566 */ MCD_OPC_FilterValue, 0, 97, 29, // Skip to: 19091 -/* 11570 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 11573 */ MCD_OPC_FilterValue, 0, 90, 29, // Skip to: 19091 -/* 11577 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... -/* 11580 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11593 -/* 11584 */ MCD_OPC_CheckPredicate, 23, 12, 1, // Skip to: 11856 -/* 11588 */ MCD_OPC_Decode, 244, 17, 130, 2, // Opcode: VFCHESB -/* 11593 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11606 -/* 11597 */ MCD_OPC_CheckPredicate, 22, 255, 0, // Skip to: 11856 -/* 11601 */ MCD_OPC_Decode, 242, 17, 130, 2, // Opcode: VFCHEDB -/* 11606 */ MCD_OPC_FilterValue, 66, 9, 0, // Skip to: 11619 -/* 11610 */ MCD_OPC_CheckPredicate, 23, 242, 0, // Skip to: 11856 -/* 11614 */ MCD_OPC_Decode, 160, 18, 130, 2, // Opcode: VFKHESB -/* 11619 */ MCD_OPC_FilterValue, 67, 9, 0, // Skip to: 11632 -/* 11623 */ MCD_OPC_CheckPredicate, 23, 229, 0, // Skip to: 11856 -/* 11627 */ MCD_OPC_Decode, 158, 18, 130, 2, // Opcode: VFKHEDB -/* 11632 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11646 -/* 11637 */ MCD_OPC_CheckPredicate, 23, 215, 0, // Skip to: 11856 -/* 11641 */ MCD_OPC_Decode, 140, 21, 166, 2, // Opcode: WFCHESB -/* 11646 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11660 -/* 11651 */ MCD_OPC_CheckPredicate, 22, 201, 0, // Skip to: 11856 -/* 11655 */ MCD_OPC_Decode, 138, 21, 167, 2, // Opcode: WFCHEDB -/* 11660 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11674 -/* 11665 */ MCD_OPC_CheckPredicate, 23, 187, 0, // Skip to: 11856 -/* 11669 */ MCD_OPC_Decode, 142, 21, 130, 2, // Opcode: WFCHEXB -/* 11674 */ MCD_OPC_FilterValue, 194, 1, 9, 0, // Skip to: 11688 -/* 11679 */ MCD_OPC_CheckPredicate, 23, 173, 0, // Skip to: 11856 -/* 11683 */ MCD_OPC_Decode, 168, 21, 166, 2, // Opcode: WFKHESB -/* 11688 */ MCD_OPC_FilterValue, 195, 1, 9, 0, // Skip to: 11702 -/* 11693 */ MCD_OPC_CheckPredicate, 23, 159, 0, // Skip to: 11856 -/* 11697 */ MCD_OPC_Decode, 166, 21, 167, 2, // Opcode: WFKHEDB -/* 11702 */ MCD_OPC_FilterValue, 196, 1, 9, 0, // Skip to: 11716 -/* 11707 */ MCD_OPC_CheckPredicate, 23, 145, 0, // Skip to: 11856 -/* 11711 */ MCD_OPC_Decode, 170, 21, 130, 2, // Opcode: WFKHEXB -/* 11716 */ MCD_OPC_FilterValue, 130, 2, 9, 0, // Skip to: 11730 -/* 11721 */ MCD_OPC_CheckPredicate, 23, 131, 0, // Skip to: 11856 -/* 11725 */ MCD_OPC_Decode, 245, 17, 130, 2, // Opcode: VFCHESBS -/* 11730 */ MCD_OPC_FilterValue, 131, 2, 9, 0, // Skip to: 11744 -/* 11735 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 11856 -/* 11739 */ MCD_OPC_Decode, 243, 17, 130, 2, // Opcode: VFCHEDBS -/* 11744 */ MCD_OPC_FilterValue, 194, 2, 9, 0, // Skip to: 11758 -/* 11749 */ MCD_OPC_CheckPredicate, 23, 103, 0, // Skip to: 11856 -/* 11753 */ MCD_OPC_Decode, 161, 18, 130, 2, // Opcode: VFKHESBS -/* 11758 */ MCD_OPC_FilterValue, 195, 2, 9, 0, // Skip to: 11772 -/* 11763 */ MCD_OPC_CheckPredicate, 23, 89, 0, // Skip to: 11856 -/* 11767 */ MCD_OPC_Decode, 159, 18, 130, 2, // Opcode: VFKHEDBS -/* 11772 */ MCD_OPC_FilterValue, 130, 3, 9, 0, // Skip to: 11786 -/* 11777 */ MCD_OPC_CheckPredicate, 23, 75, 0, // Skip to: 11856 -/* 11781 */ MCD_OPC_Decode, 141, 21, 166, 2, // Opcode: WFCHESBS -/* 11786 */ MCD_OPC_FilterValue, 131, 3, 9, 0, // Skip to: 11800 -/* 11791 */ MCD_OPC_CheckPredicate, 22, 61, 0, // Skip to: 11856 -/* 11795 */ MCD_OPC_Decode, 139, 21, 167, 2, // Opcode: WFCHEDBS -/* 11800 */ MCD_OPC_FilterValue, 132, 3, 9, 0, // Skip to: 11814 -/* 11805 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 11856 -/* 11809 */ MCD_OPC_Decode, 143, 21, 130, 2, // Opcode: WFCHEXBS -/* 11814 */ MCD_OPC_FilterValue, 194, 3, 9, 0, // Skip to: 11828 -/* 11819 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11856 -/* 11823 */ MCD_OPC_Decode, 169, 21, 166, 2, // Opcode: WFKHESBS -/* 11828 */ MCD_OPC_FilterValue, 195, 3, 9, 0, // Skip to: 11842 -/* 11833 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 11856 -/* 11837 */ MCD_OPC_Decode, 167, 21, 167, 2, // Opcode: WFKHEDBS -/* 11842 */ MCD_OPC_FilterValue, 196, 3, 9, 0, // Skip to: 11856 -/* 11847 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11856 -/* 11851 */ MCD_OPC_Decode, 171, 21, 130, 2, // Opcode: WFKHEXBS -/* 11856 */ MCD_OPC_CheckPredicate, 22, 63, 28, // Skip to: 19091 -/* 11860 */ MCD_OPC_Decode, 241, 17, 169, 2, // Opcode: VFCHE -/* 11865 */ MCD_OPC_FilterValue, 235, 1, 46, 1, // Skip to: 12172 -/* 11870 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 11873 */ MCD_OPC_FilterValue, 0, 46, 28, // Skip to: 19091 -/* 11877 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 11880 */ MCD_OPC_FilterValue, 0, 39, 28, // Skip to: 19091 -/* 11884 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... -/* 11887 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11900 -/* 11891 */ MCD_OPC_CheckPredicate, 23, 12, 1, // Skip to: 12163 -/* 11895 */ MCD_OPC_Decode, 246, 17, 130, 2, // Opcode: VFCHSB -/* 11900 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11913 -/* 11904 */ MCD_OPC_CheckPredicate, 22, 255, 0, // Skip to: 12163 -/* 11908 */ MCD_OPC_Decode, 239, 17, 130, 2, // Opcode: VFCHDB -/* 11913 */ MCD_OPC_FilterValue, 66, 9, 0, // Skip to: 11926 -/* 11917 */ MCD_OPC_CheckPredicate, 23, 242, 0, // Skip to: 12163 -/* 11921 */ MCD_OPC_Decode, 162, 18, 130, 2, // Opcode: VFKHSB -/* 11926 */ MCD_OPC_FilterValue, 67, 9, 0, // Skip to: 11939 -/* 11930 */ MCD_OPC_CheckPredicate, 23, 229, 0, // Skip to: 12163 -/* 11934 */ MCD_OPC_Decode, 156, 18, 130, 2, // Opcode: VFKHDB -/* 11939 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11953 -/* 11944 */ MCD_OPC_CheckPredicate, 23, 215, 0, // Skip to: 12163 -/* 11948 */ MCD_OPC_Decode, 144, 21, 166, 2, // Opcode: WFCHSB -/* 11953 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11967 -/* 11958 */ MCD_OPC_CheckPredicate, 22, 201, 0, // Skip to: 12163 -/* 11962 */ MCD_OPC_Decode, 136, 21, 167, 2, // Opcode: WFCHDB -/* 11967 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11981 -/* 11972 */ MCD_OPC_CheckPredicate, 23, 187, 0, // Skip to: 12163 -/* 11976 */ MCD_OPC_Decode, 146, 21, 130, 2, // Opcode: WFCHXB -/* 11981 */ MCD_OPC_FilterValue, 194, 1, 9, 0, // Skip to: 11995 -/* 11986 */ MCD_OPC_CheckPredicate, 23, 173, 0, // Skip to: 12163 -/* 11990 */ MCD_OPC_Decode, 172, 21, 166, 2, // Opcode: WFKHSB -/* 11995 */ MCD_OPC_FilterValue, 195, 1, 9, 0, // Skip to: 12009 -/* 12000 */ MCD_OPC_CheckPredicate, 23, 159, 0, // Skip to: 12163 -/* 12004 */ MCD_OPC_Decode, 164, 21, 167, 2, // Opcode: WFKHDB -/* 12009 */ MCD_OPC_FilterValue, 196, 1, 9, 0, // Skip to: 12023 -/* 12014 */ MCD_OPC_CheckPredicate, 23, 145, 0, // Skip to: 12163 -/* 12018 */ MCD_OPC_Decode, 174, 21, 130, 2, // Opcode: WFKHXB -/* 12023 */ MCD_OPC_FilterValue, 130, 2, 9, 0, // Skip to: 12037 -/* 12028 */ MCD_OPC_CheckPredicate, 23, 131, 0, // Skip to: 12163 -/* 12032 */ MCD_OPC_Decode, 247, 17, 130, 2, // Opcode: VFCHSBS -/* 12037 */ MCD_OPC_FilterValue, 131, 2, 9, 0, // Skip to: 12051 -/* 12042 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 12163 -/* 12046 */ MCD_OPC_Decode, 240, 17, 130, 2, // Opcode: VFCHDBS -/* 12051 */ MCD_OPC_FilterValue, 194, 2, 9, 0, // Skip to: 12065 -/* 12056 */ MCD_OPC_CheckPredicate, 23, 103, 0, // Skip to: 12163 -/* 12060 */ MCD_OPC_Decode, 163, 18, 130, 2, // Opcode: VFKHSBS -/* 12065 */ MCD_OPC_FilterValue, 195, 2, 9, 0, // Skip to: 12079 -/* 12070 */ MCD_OPC_CheckPredicate, 23, 89, 0, // Skip to: 12163 -/* 12074 */ MCD_OPC_Decode, 157, 18, 130, 2, // Opcode: VFKHDBS -/* 12079 */ MCD_OPC_FilterValue, 130, 3, 9, 0, // Skip to: 12093 -/* 12084 */ MCD_OPC_CheckPredicate, 23, 75, 0, // Skip to: 12163 -/* 12088 */ MCD_OPC_Decode, 145, 21, 166, 2, // Opcode: WFCHSBS -/* 12093 */ MCD_OPC_FilterValue, 131, 3, 9, 0, // Skip to: 12107 -/* 12098 */ MCD_OPC_CheckPredicate, 22, 61, 0, // Skip to: 12163 -/* 12102 */ MCD_OPC_Decode, 137, 21, 167, 2, // Opcode: WFCHDBS -/* 12107 */ MCD_OPC_FilterValue, 132, 3, 9, 0, // Skip to: 12121 -/* 12112 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 12163 -/* 12116 */ MCD_OPC_Decode, 147, 21, 130, 2, // Opcode: WFCHXBS -/* 12121 */ MCD_OPC_FilterValue, 194, 3, 9, 0, // Skip to: 12135 -/* 12126 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 12163 -/* 12130 */ MCD_OPC_Decode, 173, 21, 166, 2, // Opcode: WFKHSBS -/* 12135 */ MCD_OPC_FilterValue, 195, 3, 9, 0, // Skip to: 12149 -/* 12140 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 12163 -/* 12144 */ MCD_OPC_Decode, 165, 21, 167, 2, // Opcode: WFKHDBS -/* 12149 */ MCD_OPC_FilterValue, 196, 3, 9, 0, // Skip to: 12163 -/* 12154 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 12163 -/* 12158 */ MCD_OPC_Decode, 175, 21, 130, 2, // Opcode: WFKHXBS -/* 12163 */ MCD_OPC_CheckPredicate, 22, 12, 27, // Skip to: 19091 -/* 12167 */ MCD_OPC_Decode, 238, 17, 169, 2, // Opcode: VFCH -/* 12172 */ MCD_OPC_FilterValue, 238, 1, 94, 0, // Skip to: 12271 -/* 12177 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 12180 */ MCD_OPC_FilterValue, 0, 251, 26, // Skip to: 19091 -/* 12184 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 12187 */ MCD_OPC_FilterValue, 0, 244, 26, // Skip to: 19091 -/* 12191 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 12194 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12207 -/* 12198 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 12262 -/* 12202 */ MCD_OPC_Decode, 184, 18, 136, 2, // Opcode: VFMINSB -/* 12207 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12220 -/* 12211 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 12262 -/* 12215 */ MCD_OPC_Decode, 183, 18, 136, 2, // Opcode: VFMINDB -/* 12220 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 12234 -/* 12225 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 12262 -/* 12229 */ MCD_OPC_Decode, 199, 21, 170, 2, // Opcode: WFMINSB -/* 12234 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 12248 -/* 12239 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 12262 -/* 12243 */ MCD_OPC_Decode, 198, 21, 171, 2, // Opcode: WFMINDB -/* 12248 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 12262 -/* 12253 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 12262 -/* 12257 */ MCD_OPC_Decode, 200, 21, 136, 2, // Opcode: WFMINXB -/* 12262 */ MCD_OPC_CheckPredicate, 23, 169, 26, // Skip to: 19091 -/* 12266 */ MCD_OPC_Decode, 182, 18, 169, 2, // Opcode: VFMIN -/* 12271 */ MCD_OPC_FilterValue, 239, 1, 94, 0, // Skip to: 12370 -/* 12276 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 12279 */ MCD_OPC_FilterValue, 0, 152, 26, // Skip to: 19091 -/* 12283 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 12286 */ MCD_OPC_FilterValue, 0, 145, 26, // Skip to: 19091 -/* 12290 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 12293 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12306 -/* 12297 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 12361 -/* 12301 */ MCD_OPC_Decode, 180, 18, 136, 2, // Opcode: VFMAXSB -/* 12306 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12319 -/* 12310 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 12361 -/* 12314 */ MCD_OPC_Decode, 179, 18, 136, 2, // Opcode: VFMAXDB -/* 12319 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 12333 -/* 12324 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 12361 -/* 12328 */ MCD_OPC_Decode, 195, 21, 170, 2, // Opcode: WFMAXSB -/* 12333 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 12347 -/* 12338 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 12361 -/* 12342 */ MCD_OPC_Decode, 194, 21, 171, 2, // Opcode: WFMAXDB -/* 12347 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 12361 -/* 12352 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 12361 -/* 12356 */ MCD_OPC_Decode, 196, 21, 136, 2, // Opcode: WFMAXXB -/* 12361 */ MCD_OPC_CheckPredicate, 23, 70, 26, // Skip to: 19091 -/* 12365 */ MCD_OPC_Decode, 178, 18, 169, 2, // Opcode: VFMAX -/* 12370 */ MCD_OPC_FilterValue, 240, 1, 78, 0, // Skip to: 12453 -/* 12375 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 12378 */ MCD_OPC_FilterValue, 0, 53, 26, // Skip to: 19091 -/* 12382 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 12385 */ MCD_OPC_FilterValue, 0, 46, 26, // Skip to: 19091 -/* 12389 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 12392 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12405 -/* 12396 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12444 -/* 12400 */ MCD_OPC_Decode, 233, 16, 130, 2, // Opcode: VAVGLB -/* 12405 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12418 -/* 12409 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12444 -/* 12413 */ MCD_OPC_Decode, 236, 16, 130, 2, // Opcode: VAVGLH -/* 12418 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12431 -/* 12422 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12444 -/* 12426 */ MCD_OPC_Decode, 234, 16, 130, 2, // Opcode: VAVGLF -/* 12431 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12444 -/* 12435 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12444 -/* 12439 */ MCD_OPC_Decode, 235, 16, 130, 2, // Opcode: VAVGLG -/* 12444 */ MCD_OPC_CheckPredicate, 22, 243, 25, // Skip to: 19091 -/* 12448 */ MCD_OPC_Decode, 232, 16, 131, 2, // Opcode: VAVGL -/* 12453 */ MCD_OPC_FilterValue, 241, 1, 91, 0, // Skip to: 12549 -/* 12458 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 12461 */ MCD_OPC_FilterValue, 0, 226, 25, // Skip to: 19091 -/* 12465 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 12468 */ MCD_OPC_FilterValue, 0, 219, 25, // Skip to: 19091 -/* 12472 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 12475 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12488 -/* 12479 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 12540 -/* 12483 */ MCD_OPC_Decode, 214, 16, 130, 2, // Opcode: VACCB -/* 12488 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12501 -/* 12492 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12540 -/* 12496 */ MCD_OPC_Decode, 219, 16, 130, 2, // Opcode: VACCH -/* 12501 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12514 -/* 12505 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12540 -/* 12509 */ MCD_OPC_Decode, 217, 16, 130, 2, // Opcode: VACCF -/* 12514 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12527 -/* 12518 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12540 -/* 12522 */ MCD_OPC_Decode, 218, 16, 130, 2, // Opcode: VACCG -/* 12527 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12540 -/* 12531 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12540 -/* 12535 */ MCD_OPC_Decode, 220, 16, 130, 2, // Opcode: VACCQ -/* 12540 */ MCD_OPC_CheckPredicate, 22, 147, 25, // Skip to: 19091 -/* 12544 */ MCD_OPC_Decode, 213, 16, 131, 2, // Opcode: VACC -/* 12549 */ MCD_OPC_FilterValue, 242, 1, 78, 0, // Skip to: 12632 -/* 12554 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 12557 */ MCD_OPC_FilterValue, 0, 130, 25, // Skip to: 19091 -/* 12561 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 12564 */ MCD_OPC_FilterValue, 0, 123, 25, // Skip to: 19091 -/* 12568 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 12571 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12584 -/* 12575 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12623 -/* 12579 */ MCD_OPC_Decode, 228, 16, 130, 2, // Opcode: VAVGB -/* 12584 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12597 -/* 12588 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12623 -/* 12592 */ MCD_OPC_Decode, 231, 16, 130, 2, // Opcode: VAVGH -/* 12597 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12610 -/* 12601 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12623 -/* 12605 */ MCD_OPC_Decode, 229, 16, 130, 2, // Opcode: VAVGF -/* 12610 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12623 -/* 12614 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12623 -/* 12618 */ MCD_OPC_Decode, 230, 16, 130, 2, // Opcode: VAVGG -/* 12623 */ MCD_OPC_CheckPredicate, 22, 64, 25, // Skip to: 19091 -/* 12627 */ MCD_OPC_Decode, 227, 16, 131, 2, // Opcode: VAVG -/* 12632 */ MCD_OPC_FilterValue, 243, 1, 91, 0, // Skip to: 12728 -/* 12637 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 12640 */ MCD_OPC_FilterValue, 0, 47, 25, // Skip to: 19091 -/* 12644 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 12647 */ MCD_OPC_FilterValue, 0, 40, 25, // Skip to: 19091 -/* 12651 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 12654 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12667 -/* 12658 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 12719 -/* 12662 */ MCD_OPC_Decode, 211, 16, 130, 2, // Opcode: VAB -/* 12667 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12680 -/* 12671 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12719 -/* 12675 */ MCD_OPC_Decode, 224, 16, 130, 2, // Opcode: VAH -/* 12680 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12693 -/* 12684 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12719 -/* 12688 */ MCD_OPC_Decode, 222, 16, 130, 2, // Opcode: VAF -/* 12693 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12706 -/* 12697 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12719 -/* 12701 */ MCD_OPC_Decode, 223, 16, 130, 2, // Opcode: VAG -/* 12706 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12719 -/* 12710 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12719 -/* 12714 */ MCD_OPC_Decode, 226, 16, 130, 2, // Opcode: VAQ -/* 12719 */ MCD_OPC_CheckPredicate, 22, 224, 24, // Skip to: 19091 -/* 12723 */ MCD_OPC_Decode, 210, 16, 131, 2, // Opcode: VA -/* 12728 */ MCD_OPC_FilterValue, 245, 1, 91, 0, // Skip to: 12824 -/* 12733 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 12736 */ MCD_OPC_FilterValue, 0, 207, 24, // Skip to: 19091 -/* 12740 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 12743 */ MCD_OPC_FilterValue, 0, 200, 24, // Skip to: 19091 -/* 12747 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 12750 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12763 -/* 12754 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 12815 -/* 12758 */ MCD_OPC_Decode, 171, 20, 130, 2, // Opcode: VSCBIB -/* 12763 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12776 -/* 12767 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12815 -/* 12771 */ MCD_OPC_Decode, 174, 20, 130, 2, // Opcode: VSCBIH -/* 12776 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12789 -/* 12780 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12815 -/* 12784 */ MCD_OPC_Decode, 172, 20, 130, 2, // Opcode: VSCBIF -/* 12789 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12802 -/* 12793 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12815 -/* 12797 */ MCD_OPC_Decode, 173, 20, 130, 2, // Opcode: VSCBIG -/* 12802 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12815 -/* 12806 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12815 -/* 12810 */ MCD_OPC_Decode, 175, 20, 130, 2, // Opcode: VSCBIQ -/* 12815 */ MCD_OPC_CheckPredicate, 22, 128, 24, // Skip to: 19091 -/* 12819 */ MCD_OPC_Decode, 170, 20, 131, 2, // Opcode: VSCBI -/* 12824 */ MCD_OPC_FilterValue, 247, 1, 91, 0, // Skip to: 12920 -/* 12829 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 12832 */ MCD_OPC_FilterValue, 0, 111, 24, // Skip to: 19091 -/* 12836 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 12839 */ MCD_OPC_FilterValue, 0, 104, 24, // Skip to: 19091 -/* 12843 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 12846 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12859 -/* 12850 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 12911 -/* 12854 */ MCD_OPC_Decode, 165, 20, 130, 2, // Opcode: VSB -/* 12859 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12872 -/* 12863 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12911 -/* 12867 */ MCD_OPC_Decode, 186, 20, 130, 2, // Opcode: VSH -/* 12872 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12885 -/* 12876 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12911 -/* 12880 */ MCD_OPC_Decode, 184, 20, 130, 2, // Opcode: VSF -/* 12885 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12898 -/* 12889 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12911 -/* 12893 */ MCD_OPC_Decode, 185, 20, 130, 2, // Opcode: VSG -/* 12898 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12911 -/* 12902 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12911 -/* 12906 */ MCD_OPC_Decode, 191, 20, 130, 2, // Opcode: VSQ -/* 12911 */ MCD_OPC_CheckPredicate, 22, 32, 24, // Skip to: 19091 -/* 12915 */ MCD_OPC_Decode, 164, 20, 131, 2, // Opcode: VS -/* 12920 */ MCD_OPC_FilterValue, 248, 1, 165, 0, // Skip to: 13090 -/* 12925 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 12928 */ MCD_OPC_FilterValue, 0, 15, 24, // Skip to: 19091 -/* 12932 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 12935 */ MCD_OPC_FilterValue, 0, 8, 24, // Skip to: 19091 -/* 12939 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 12942 */ MCD_OPC_FilterValue, 0, 1, 24, // Skip to: 19091 -/* 12946 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 12949 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 12982 -/* 12953 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 12956 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12969 -/* 12960 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 13081 -/* 12964 */ MCD_OPC_Decode, 243, 16, 130, 2, // Opcode: VCEQB -/* 12969 */ MCD_OPC_FilterValue, 1, 108, 0, // Skip to: 13081 -/* 12973 */ MCD_OPC_CheckPredicate, 22, 104, 0, // Skip to: 13081 -/* 12977 */ MCD_OPC_Decode, 244, 16, 130, 2, // Opcode: VCEQBS -/* 12982 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 13015 -/* 12986 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 12989 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13002 -/* 12993 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 13081 -/* 12997 */ MCD_OPC_Decode, 249, 16, 130, 2, // Opcode: VCEQH -/* 13002 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 13081 -/* 13006 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 13081 -/* 13010 */ MCD_OPC_Decode, 250, 16, 130, 2, // Opcode: VCEQHS -/* 13015 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 13048 -/* 13019 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13022 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13035 -/* 13026 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 13081 -/* 13030 */ MCD_OPC_Decode, 245, 16, 130, 2, // Opcode: VCEQF -/* 13035 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 13081 -/* 13039 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 13081 -/* 13043 */ MCD_OPC_Decode, 246, 16, 130, 2, // Opcode: VCEQFS -/* 13048 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 13081 -/* 13052 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13055 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13068 -/* 13059 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13081 -/* 13063 */ MCD_OPC_Decode, 247, 16, 130, 2, // Opcode: VCEQG -/* 13068 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13081 -/* 13072 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13081 -/* 13076 */ MCD_OPC_Decode, 248, 16, 130, 2, // Opcode: VCEQGS -/* 13081 */ MCD_OPC_CheckPredicate, 22, 118, 23, // Skip to: 19091 -/* 13085 */ MCD_OPC_Decode, 242, 16, 137, 2, // Opcode: VCEQ -/* 13090 */ MCD_OPC_FilterValue, 249, 1, 165, 0, // Skip to: 13260 -/* 13095 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 13098 */ MCD_OPC_FilterValue, 0, 101, 23, // Skip to: 19091 -/* 13102 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 13105 */ MCD_OPC_FilterValue, 0, 94, 23, // Skip to: 19091 -/* 13109 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 13112 */ MCD_OPC_FilterValue, 0, 87, 23, // Skip to: 19091 -/* 13116 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 13119 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 13152 -/* 13123 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13126 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13139 -/* 13130 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 13251 -/* 13134 */ MCD_OPC_Decode, 135, 17, 130, 2, // Opcode: VCHLB -/* 13139 */ MCD_OPC_FilterValue, 1, 108, 0, // Skip to: 13251 -/* 13143 */ MCD_OPC_CheckPredicate, 22, 104, 0, // Skip to: 13251 -/* 13147 */ MCD_OPC_Decode, 136, 17, 130, 2, // Opcode: VCHLBS -/* 13152 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 13185 -/* 13156 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13159 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13172 -/* 13163 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 13251 -/* 13167 */ MCD_OPC_Decode, 141, 17, 130, 2, // Opcode: VCHLH -/* 13172 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 13251 -/* 13176 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 13251 -/* 13180 */ MCD_OPC_Decode, 142, 17, 130, 2, // Opcode: VCHLHS -/* 13185 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 13218 -/* 13189 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13192 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13205 -/* 13196 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 13251 -/* 13200 */ MCD_OPC_Decode, 137, 17, 130, 2, // Opcode: VCHLF -/* 13205 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 13251 -/* 13209 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 13251 -/* 13213 */ MCD_OPC_Decode, 138, 17, 130, 2, // Opcode: VCHLFS -/* 13218 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 13251 -/* 13222 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13225 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13238 -/* 13229 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13251 -/* 13233 */ MCD_OPC_Decode, 139, 17, 130, 2, // Opcode: VCHLG -/* 13238 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13251 -/* 13242 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13251 -/* 13246 */ MCD_OPC_Decode, 140, 17, 130, 2, // Opcode: VCHLGS -/* 13251 */ MCD_OPC_CheckPredicate, 22, 204, 22, // Skip to: 19091 -/* 13255 */ MCD_OPC_Decode, 134, 17, 137, 2, // Opcode: VCHL -/* 13260 */ MCD_OPC_FilterValue, 251, 1, 165, 0, // Skip to: 13430 -/* 13265 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 13268 */ MCD_OPC_FilterValue, 0, 187, 22, // Skip to: 19091 -/* 13272 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 13275 */ MCD_OPC_FilterValue, 0, 180, 22, // Skip to: 19091 -/* 13279 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 13282 */ MCD_OPC_FilterValue, 0, 173, 22, // Skip to: 19091 -/* 13286 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 13289 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 13322 -/* 13293 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13296 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13309 -/* 13300 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 13421 -/* 13304 */ MCD_OPC_Decode, 254, 16, 130, 2, // Opcode: VCHB -/* 13309 */ MCD_OPC_FilterValue, 1, 108, 0, // Skip to: 13421 -/* 13313 */ MCD_OPC_CheckPredicate, 22, 104, 0, // Skip to: 13421 -/* 13317 */ MCD_OPC_Decode, 255, 16, 130, 2, // Opcode: VCHBS -/* 13322 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 13355 -/* 13326 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13329 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13342 -/* 13333 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 13421 -/* 13337 */ MCD_OPC_Decode, 132, 17, 130, 2, // Opcode: VCHH -/* 13342 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 13421 -/* 13346 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 13421 -/* 13350 */ MCD_OPC_Decode, 133, 17, 130, 2, // Opcode: VCHHS -/* 13355 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 13388 -/* 13359 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13362 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13375 -/* 13366 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 13421 -/* 13370 */ MCD_OPC_Decode, 128, 17, 130, 2, // Opcode: VCHF -/* 13375 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 13421 -/* 13379 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 13421 -/* 13383 */ MCD_OPC_Decode, 129, 17, 130, 2, // Opcode: VCHFS -/* 13388 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 13421 -/* 13392 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13395 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13408 -/* 13399 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13421 -/* 13403 */ MCD_OPC_Decode, 130, 17, 130, 2, // Opcode: VCHG -/* 13408 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13421 -/* 13412 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13421 -/* 13416 */ MCD_OPC_Decode, 131, 17, 130, 2, // Opcode: VCHGS -/* 13421 */ MCD_OPC_CheckPredicate, 22, 34, 22, // Skip to: 19091 -/* 13425 */ MCD_OPC_Decode, 253, 16, 137, 2, // Opcode: VCH -/* 13430 */ MCD_OPC_FilterValue, 252, 1, 78, 0, // Skip to: 13513 -/* 13435 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 13438 */ MCD_OPC_FilterValue, 0, 17, 22, // Skip to: 19091 -/* 13442 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 13445 */ MCD_OPC_FilterValue, 0, 10, 22, // Skip to: 19091 -/* 13449 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 13452 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13465 -/* 13456 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 13504 -/* 13460 */ MCD_OPC_Decode, 214, 19, 130, 2, // Opcode: VMNLB -/* 13465 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13478 -/* 13469 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 13504 -/* 13473 */ MCD_OPC_Decode, 217, 19, 130, 2, // Opcode: VMNLH -/* 13478 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13491 -/* 13482 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13504 -/* 13486 */ MCD_OPC_Decode, 215, 19, 130, 2, // Opcode: VMNLF -/* 13491 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 13504 -/* 13495 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13504 -/* 13499 */ MCD_OPC_Decode, 216, 19, 130, 2, // Opcode: VMNLG -/* 13504 */ MCD_OPC_CheckPredicate, 22, 207, 21, // Skip to: 19091 -/* 13508 */ MCD_OPC_Decode, 213, 19, 131, 2, // Opcode: VMNL -/* 13513 */ MCD_OPC_FilterValue, 253, 1, 78, 0, // Skip to: 13596 -/* 13518 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 13521 */ MCD_OPC_FilterValue, 0, 190, 21, // Skip to: 19091 -/* 13525 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 13528 */ MCD_OPC_FilterValue, 0, 183, 21, // Skip to: 19091 -/* 13532 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 13535 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13548 -/* 13539 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 13587 -/* 13543 */ MCD_OPC_Decode, 242, 19, 130, 2, // Opcode: VMXLB -/* 13548 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13561 -/* 13552 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 13587 -/* 13556 */ MCD_OPC_Decode, 245, 19, 130, 2, // Opcode: VMXLH -/* 13561 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13574 -/* 13565 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13587 -/* 13569 */ MCD_OPC_Decode, 243, 19, 130, 2, // Opcode: VMXLF -/* 13574 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 13587 -/* 13578 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13587 -/* 13582 */ MCD_OPC_Decode, 244, 19, 130, 2, // Opcode: VMXLG -/* 13587 */ MCD_OPC_CheckPredicate, 22, 124, 21, // Skip to: 19091 -/* 13591 */ MCD_OPC_Decode, 241, 19, 131, 2, // Opcode: VMXL -/* 13596 */ MCD_OPC_FilterValue, 254, 1, 78, 0, // Skip to: 13679 -/* 13601 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 13604 */ MCD_OPC_FilterValue, 0, 107, 21, // Skip to: 19091 -/* 13608 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 13611 */ MCD_OPC_FilterValue, 0, 100, 21, // Skip to: 19091 -/* 13615 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 13618 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13631 -/* 13622 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 13670 -/* 13626 */ MCD_OPC_Decode, 209, 19, 130, 2, // Opcode: VMNB -/* 13631 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13644 -/* 13635 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 13670 -/* 13639 */ MCD_OPC_Decode, 212, 19, 130, 2, // Opcode: VMNH -/* 13644 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13657 -/* 13648 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13670 -/* 13652 */ MCD_OPC_Decode, 210, 19, 130, 2, // Opcode: VMNF -/* 13657 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 13670 -/* 13661 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13670 -/* 13665 */ MCD_OPC_Decode, 211, 19, 130, 2, // Opcode: VMNG -/* 13670 */ MCD_OPC_CheckPredicate, 22, 41, 21, // Skip to: 19091 -/* 13674 */ MCD_OPC_Decode, 208, 19, 131, 2, // Opcode: VMN -/* 13679 */ MCD_OPC_FilterValue, 255, 1, 31, 21, // Skip to: 19091 -/* 13684 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 13687 */ MCD_OPC_FilterValue, 0, 24, 21, // Skip to: 19091 -/* 13691 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 13694 */ MCD_OPC_FilterValue, 0, 17, 21, // Skip to: 19091 -/* 13698 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 13701 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13714 -/* 13705 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 13753 -/* 13709 */ MCD_OPC_Decode, 237, 19, 130, 2, // Opcode: VMXB -/* 13714 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13727 -/* 13718 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 13753 -/* 13722 */ MCD_OPC_Decode, 240, 19, 130, 2, // Opcode: VMXH -/* 13727 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13740 -/* 13731 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13753 -/* 13735 */ MCD_OPC_Decode, 238, 19, 130, 2, // Opcode: VMXF -/* 13740 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 13753 -/* 13744 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13753 -/* 13748 */ MCD_OPC_Decode, 239, 19, 130, 2, // Opcode: VMXG -/* 13753 */ MCD_OPC_CheckPredicate, 22, 214, 20, // Skip to: 19091 -/* 13757 */ MCD_OPC_Decode, 236, 19, 131, 2, // Opcode: VMX -/* 13762 */ MCD_OPC_FilterValue, 232, 1, 5, 0, // Skip to: 13772 -/* 13767 */ MCD_OPC_Decode, 193, 13, 189, 1, // Opcode: MVCIN -/* 13772 */ MCD_OPC_FilterValue, 233, 1, 5, 0, // Skip to: 13782 -/* 13777 */ MCD_OPC_Decode, 143, 14, 191, 1, // Opcode: PKA -/* 13782 */ MCD_OPC_FilterValue, 234, 1, 5, 0, // Skip to: 13792 -/* 13787 */ MCD_OPC_Decode, 207, 16, 189, 1, // Opcode: UNPKA -/* 13792 */ MCD_OPC_FilterValue, 235, 1, 198, 7, // Skip to: 15787 -/* 13797 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... -/* 13800 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 13809 -/* 13804 */ MCD_OPC_Decode, 227, 10, 172, 2, // Opcode: LMG -/* 13809 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 13818 -/* 13813 */ MCD_OPC_Decode, 132, 15, 173, 2, // Opcode: SRAG -/* 13818 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 13827 -/* 13822 */ MCD_OPC_Decode, 217, 14, 173, 2, // Opcode: SLAG -/* 13827 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 13836 -/* 13831 */ MCD_OPC_Decode, 139, 15, 173, 2, // Opcode: SRLG -/* 13836 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 13845 -/* 13840 */ MCD_OPC_Decode, 236, 14, 173, 2, // Opcode: SLLG -/* 13845 */ MCD_OPC_FilterValue, 15, 5, 0, // Skip to: 13854 -/* 13849 */ MCD_OPC_Decode, 186, 16, 172, 2, // Opcode: TRACG -/* 13854 */ MCD_OPC_FilterValue, 20, 5, 0, // Skip to: 13863 -/* 13858 */ MCD_OPC_Decode, 140, 8, 174, 2, // Opcode: CSY -/* 13863 */ MCD_OPC_FilterValue, 28, 5, 0, // Skip to: 13872 -/* 13867 */ MCD_OPC_Decode, 167, 14, 173, 2, // Opcode: RLLG -/* 13872 */ MCD_OPC_FilterValue, 29, 5, 0, // Skip to: 13881 -/* 13876 */ MCD_OPC_Decode, 166, 14, 175, 2, // Opcode: RLL -/* 13881 */ MCD_OPC_FilterValue, 32, 5, 0, // Skip to: 13890 -/* 13885 */ MCD_OPC_Decode, 143, 7, 176, 2, // Opcode: CLMH -/* 13890 */ MCD_OPC_FilterValue, 33, 5, 0, // Skip to: 13899 -/* 13894 */ MCD_OPC_Decode, 144, 7, 177, 2, // Opcode: CLMY -/* 13899 */ MCD_OPC_FilterValue, 35, 90, 0, // Skip to: 13993 -/* 13903 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 13906 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13919 -/* 13910 */ MCD_OPC_CheckPredicate, 24, 70, 0, // Skip to: 13984 -/* 13914 */ MCD_OPC_Decode, 193, 7, 178, 2, // Opcode: CLTAsmH -/* 13919 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 13932 -/* 13923 */ MCD_OPC_CheckPredicate, 24, 57, 0, // Skip to: 13984 -/* 13927 */ MCD_OPC_Decode, 195, 7, 178, 2, // Opcode: CLTAsmL -/* 13932 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 13945 -/* 13936 */ MCD_OPC_CheckPredicate, 24, 44, 0, // Skip to: 13984 -/* 13940 */ MCD_OPC_Decode, 197, 7, 178, 2, // Opcode: CLTAsmLH -/* 13945 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 13958 -/* 13949 */ MCD_OPC_CheckPredicate, 24, 31, 0, // Skip to: 13984 -/* 13953 */ MCD_OPC_Decode, 192, 7, 178, 2, // Opcode: CLTAsmE -/* 13958 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 13971 -/* 13962 */ MCD_OPC_CheckPredicate, 24, 18, 0, // Skip to: 13984 -/* 13966 */ MCD_OPC_Decode, 194, 7, 178, 2, // Opcode: CLTAsmHE -/* 13971 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 13984 -/* 13975 */ MCD_OPC_CheckPredicate, 24, 5, 0, // Skip to: 13984 -/* 13979 */ MCD_OPC_Decode, 196, 7, 178, 2, // Opcode: CLTAsmLE -/* 13984 */ MCD_OPC_CheckPredicate, 24, 239, 19, // Skip to: 19091 -/* 13988 */ MCD_OPC_Decode, 191, 7, 179, 2, // Opcode: CLTAsm -/* 13993 */ MCD_OPC_FilterValue, 36, 5, 0, // Skip to: 14002 -/* 13997 */ MCD_OPC_Decode, 189, 15, 172, 2, // Opcode: STMG -/* 14002 */ MCD_OPC_FilterValue, 37, 5, 0, // Skip to: 14011 -/* 14006 */ MCD_OPC_Decode, 169, 15, 180, 2, // Opcode: STCTG -/* 14011 */ MCD_OPC_FilterValue, 38, 5, 0, // Skip to: 14020 -/* 14015 */ MCD_OPC_Decode, 190, 15, 181, 2, // Opcode: STMH -/* 14020 */ MCD_OPC_FilterValue, 43, 90, 0, // Skip to: 14114 -/* 14024 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 14027 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 14040 -/* 14031 */ MCD_OPC_CheckPredicate, 24, 70, 0, // Skip to: 14105 -/* 14035 */ MCD_OPC_Decode, 221, 6, 182, 2, // Opcode: CLGTAsmH -/* 14040 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 14053 -/* 14044 */ MCD_OPC_CheckPredicate, 24, 57, 0, // Skip to: 14105 -/* 14048 */ MCD_OPC_Decode, 223, 6, 182, 2, // Opcode: CLGTAsmL -/* 14053 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 14066 -/* 14057 */ MCD_OPC_CheckPredicate, 24, 44, 0, // Skip to: 14105 -/* 14061 */ MCD_OPC_Decode, 225, 6, 182, 2, // Opcode: CLGTAsmLH -/* 14066 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 14079 -/* 14070 */ MCD_OPC_CheckPredicate, 24, 31, 0, // Skip to: 14105 -/* 14074 */ MCD_OPC_Decode, 220, 6, 182, 2, // Opcode: CLGTAsmE -/* 14079 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 14092 -/* 14083 */ MCD_OPC_CheckPredicate, 24, 18, 0, // Skip to: 14105 -/* 14087 */ MCD_OPC_Decode, 222, 6, 182, 2, // Opcode: CLGTAsmHE -/* 14092 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 14105 -/* 14096 */ MCD_OPC_CheckPredicate, 24, 5, 0, // Skip to: 14105 -/* 14100 */ MCD_OPC_Decode, 224, 6, 182, 2, // Opcode: CLGTAsmLE -/* 14105 */ MCD_OPC_CheckPredicate, 24, 118, 19, // Skip to: 19091 -/* 14109 */ MCD_OPC_Decode, 219, 6, 183, 2, // Opcode: CLGTAsm -/* 14114 */ MCD_OPC_FilterValue, 44, 5, 0, // Skip to: 14123 -/* 14118 */ MCD_OPC_Decode, 165, 15, 176, 2, // Opcode: STCMH -/* 14123 */ MCD_OPC_FilterValue, 45, 5, 0, // Skip to: 14132 -/* 14127 */ MCD_OPC_Decode, 166, 15, 177, 2, // Opcode: STCMY -/* 14132 */ MCD_OPC_FilterValue, 47, 5, 0, // Skip to: 14141 -/* 14136 */ MCD_OPC_Decode, 143, 10, 180, 2, // Opcode: LCTLG -/* 14141 */ MCD_OPC_FilterValue, 48, 5, 0, // Skip to: 14150 -/* 14145 */ MCD_OPC_Decode, 135, 8, 184, 2, // Opcode: CSG -/* 14150 */ MCD_OPC_FilterValue, 49, 5, 0, // Skip to: 14159 -/* 14154 */ MCD_OPC_Decode, 160, 4, 185, 2, // Opcode: CDSY -/* 14159 */ MCD_OPC_FilterValue, 62, 5, 0, // Skip to: 14168 -/* 14163 */ MCD_OPC_Decode, 158, 4, 185, 2, // Opcode: CDSG -/* 14168 */ MCD_OPC_FilterValue, 68, 5, 0, // Skip to: 14177 -/* 14172 */ MCD_OPC_Decode, 135, 4, 184, 2, // Opcode: BXHG -/* 14177 */ MCD_OPC_FilterValue, 69, 5, 0, // Skip to: 14186 -/* 14181 */ MCD_OPC_Decode, 137, 4, 184, 2, // Opcode: BXLEG -/* 14186 */ MCD_OPC_FilterValue, 76, 5, 0, // Skip to: 14195 -/* 14190 */ MCD_OPC_Decode, 216, 8, 173, 2, // Opcode: ECAG -/* 14195 */ MCD_OPC_FilterValue, 81, 5, 0, // Skip to: 14204 -/* 14199 */ MCD_OPC_Decode, 180, 16, 186, 2, // Opcode: TMY -/* 14204 */ MCD_OPC_FilterValue, 82, 5, 0, // Skip to: 14213 -/* 14208 */ MCD_OPC_Decode, 206, 13, 186, 2, // Opcode: MVIY -/* 14213 */ MCD_OPC_FilterValue, 84, 5, 0, // Skip to: 14222 -/* 14217 */ MCD_OPC_Decode, 239, 13, 186, 2, // Opcode: NIY -/* 14222 */ MCD_OPC_FilterValue, 85, 5, 0, // Skip to: 14231 -/* 14226 */ MCD_OPC_Decode, 141, 7, 186, 2, // Opcode: CLIY -/* 14231 */ MCD_OPC_FilterValue, 86, 5, 0, // Skip to: 14240 -/* 14235 */ MCD_OPC_Decode, 128, 14, 186, 2, // Opcode: OIY -/* 14240 */ MCD_OPC_FilterValue, 87, 5, 0, // Skip to: 14249 -/* 14244 */ MCD_OPC_Decode, 234, 21, 186, 2, // Opcode: XIY -/* 14249 */ MCD_OPC_FilterValue, 106, 5, 0, // Skip to: 14258 -/* 14253 */ MCD_OPC_Decode, 155, 3, 187, 2, // Opcode: ASI -/* 14258 */ MCD_OPC_FilterValue, 110, 5, 0, // Skip to: 14267 -/* 14262 */ MCD_OPC_Decode, 148, 3, 187, 2, // Opcode: ALSI -/* 14267 */ MCD_OPC_FilterValue, 122, 5, 0, // Skip to: 14276 -/* 14271 */ MCD_OPC_Decode, 249, 2, 187, 2, // Opcode: AGSI -/* 14276 */ MCD_OPC_FilterValue, 126, 5, 0, // Skip to: 14285 -/* 14280 */ MCD_OPC_Decode, 142, 3, 187, 2, // Opcode: ALGSI -/* 14285 */ MCD_OPC_FilterValue, 128, 1, 5, 0, // Skip to: 14295 -/* 14290 */ MCD_OPC_Decode, 132, 9, 188, 2, // Opcode: ICMH -/* 14295 */ MCD_OPC_FilterValue, 129, 1, 5, 0, // Skip to: 14305 -/* 14300 */ MCD_OPC_Decode, 133, 9, 189, 2, // Opcode: ICMY -/* 14305 */ MCD_OPC_FilterValue, 142, 1, 5, 0, // Skip to: 14315 -/* 14310 */ MCD_OPC_Decode, 197, 13, 190, 2, // Opcode: MVCLU -/* 14315 */ MCD_OPC_FilterValue, 143, 1, 5, 0, // Skip to: 14325 -/* 14320 */ MCD_OPC_Decode, 228, 5, 190, 2, // Opcode: CLCLU -/* 14325 */ MCD_OPC_FilterValue, 144, 1, 5, 0, // Skip to: 14335 -/* 14330 */ MCD_OPC_Decode, 191, 15, 191, 2, // Opcode: STMY -/* 14335 */ MCD_OPC_FilterValue, 150, 1, 5, 0, // Skip to: 14345 -/* 14340 */ MCD_OPC_Decode, 228, 10, 181, 2, // Opcode: LMH -/* 14345 */ MCD_OPC_FilterValue, 152, 1, 5, 0, // Skip to: 14355 -/* 14350 */ MCD_OPC_Decode, 229, 10, 191, 2, // Opcode: LMY -/* 14355 */ MCD_OPC_FilterValue, 154, 1, 5, 0, // Skip to: 14365 -/* 14360 */ MCD_OPC_Decode, 245, 9, 192, 2, // Opcode: LAMY -/* 14365 */ MCD_OPC_FilterValue, 155, 1, 5, 0, // Skip to: 14375 -/* 14370 */ MCD_OPC_Decode, 156, 15, 192, 2, // Opcode: STAMY -/* 14375 */ MCD_OPC_FilterValue, 192, 1, 17, 0, // Skip to: 14397 -/* 14380 */ MCD_OPC_CheckField, 32, 4, 0, 97, 18, // Skip to: 19091 -/* 14386 */ MCD_OPC_CheckField, 8, 8, 0, 91, 18, // Skip to: 19091 -/* 14392 */ MCD_OPC_Decode, 181, 16, 193, 2, // Opcode: TP -/* 14397 */ MCD_OPC_FilterValue, 220, 1, 9, 0, // Skip to: 14411 -/* 14402 */ MCD_OPC_CheckPredicate, 15, 77, 18, // Skip to: 19091 -/* 14406 */ MCD_OPC_Decode, 133, 15, 175, 2, // Opcode: SRAK -/* 14411 */ MCD_OPC_FilterValue, 221, 1, 9, 0, // Skip to: 14425 -/* 14416 */ MCD_OPC_CheckPredicate, 15, 63, 18, // Skip to: 19091 -/* 14420 */ MCD_OPC_Decode, 218, 14, 175, 2, // Opcode: SLAK -/* 14425 */ MCD_OPC_FilterValue, 222, 1, 9, 0, // Skip to: 14439 -/* 14430 */ MCD_OPC_CheckPredicate, 15, 49, 18, // Skip to: 19091 -/* 14434 */ MCD_OPC_Decode, 140, 15, 175, 2, // Opcode: SRLK -/* 14439 */ MCD_OPC_FilterValue, 223, 1, 9, 0, // Skip to: 14453 -/* 14444 */ MCD_OPC_CheckPredicate, 15, 35, 18, // Skip to: 19091 -/* 14448 */ MCD_OPC_Decode, 237, 14, 175, 2, // Opcode: SLLK -/* 14453 */ MCD_OPC_FilterValue, 224, 1, 194, 0, // Skip to: 14652 -/* 14458 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 14461 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 14474 -/* 14465 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 14643 -/* 14469 */ MCD_OPC_Decode, 154, 11, 194, 2, // Opcode: LOCFHAsmO -/* 14474 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 14487 -/* 14478 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 14643 -/* 14482 */ MCD_OPC_Decode, 138, 11, 194, 2, // Opcode: LOCFHAsmH -/* 14487 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 14500 -/* 14491 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 14643 -/* 14495 */ MCD_OPC_Decode, 148, 11, 194, 2, // Opcode: LOCFHAsmNLE -/* 14500 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 14513 -/* 14504 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 14643 -/* 14508 */ MCD_OPC_Decode, 140, 11, 194, 2, // Opcode: LOCFHAsmL -/* 14513 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 14526 -/* 14517 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 14643 -/* 14521 */ MCD_OPC_Decode, 146, 11, 194, 2, // Opcode: LOCFHAsmNHE -/* 14526 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 14539 -/* 14530 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 14643 -/* 14534 */ MCD_OPC_Decode, 142, 11, 194, 2, // Opcode: LOCFHAsmLH -/* 14539 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 14552 -/* 14543 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 14643 -/* 14547 */ MCD_OPC_Decode, 144, 11, 194, 2, // Opcode: LOCFHAsmNE -/* 14552 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 14565 -/* 14556 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 14643 -/* 14560 */ MCD_OPC_Decode, 137, 11, 194, 2, // Opcode: LOCFHAsmE -/* 14565 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 14578 -/* 14569 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 14643 -/* 14573 */ MCD_OPC_Decode, 149, 11, 194, 2, // Opcode: LOCFHAsmNLH -/* 14578 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 14591 -/* 14582 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 14643 -/* 14586 */ MCD_OPC_Decode, 139, 11, 194, 2, // Opcode: LOCFHAsmHE -/* 14591 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 14604 -/* 14595 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 14643 -/* 14599 */ MCD_OPC_Decode, 147, 11, 194, 2, // Opcode: LOCFHAsmNL -/* 14604 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 14617 -/* 14608 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 14643 -/* 14612 */ MCD_OPC_Decode, 141, 11, 194, 2, // Opcode: LOCFHAsmLE -/* 14617 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 14630 -/* 14621 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 14643 -/* 14625 */ MCD_OPC_Decode, 145, 11, 194, 2, // Opcode: LOCFHAsmNH -/* 14630 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 14643 -/* 14634 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 14643 -/* 14638 */ MCD_OPC_Decode, 151, 11, 194, 2, // Opcode: LOCFHAsmNO -/* 14643 */ MCD_OPC_CheckPredicate, 12, 92, 17, // Skip to: 19091 -/* 14647 */ MCD_OPC_Decode, 136, 11, 195, 2, // Opcode: LOCFHAsm -/* 14652 */ MCD_OPC_FilterValue, 225, 1, 194, 0, // Skip to: 14851 -/* 14657 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 14660 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 14673 -/* 14664 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 14842 -/* 14668 */ MCD_OPC_Decode, 234, 15, 196, 2, // Opcode: STOCFHAsmO -/* 14673 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 14686 -/* 14677 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 14842 -/* 14681 */ MCD_OPC_Decode, 218, 15, 196, 2, // Opcode: STOCFHAsmH -/* 14686 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 14699 -/* 14690 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 14842 -/* 14694 */ MCD_OPC_Decode, 228, 15, 196, 2, // Opcode: STOCFHAsmNLE -/* 14699 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 14712 -/* 14703 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 14842 -/* 14707 */ MCD_OPC_Decode, 220, 15, 196, 2, // Opcode: STOCFHAsmL -/* 14712 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 14725 -/* 14716 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 14842 -/* 14720 */ MCD_OPC_Decode, 226, 15, 196, 2, // Opcode: STOCFHAsmNHE -/* 14725 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 14738 -/* 14729 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 14842 -/* 14733 */ MCD_OPC_Decode, 222, 15, 196, 2, // Opcode: STOCFHAsmLH -/* 14738 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 14751 -/* 14742 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 14842 -/* 14746 */ MCD_OPC_Decode, 224, 15, 196, 2, // Opcode: STOCFHAsmNE -/* 14751 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 14764 -/* 14755 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 14842 -/* 14759 */ MCD_OPC_Decode, 217, 15, 196, 2, // Opcode: STOCFHAsmE -/* 14764 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 14777 -/* 14768 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 14842 -/* 14772 */ MCD_OPC_Decode, 229, 15, 196, 2, // Opcode: STOCFHAsmNLH -/* 14777 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 14790 -/* 14781 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 14842 -/* 14785 */ MCD_OPC_Decode, 219, 15, 196, 2, // Opcode: STOCFHAsmHE -/* 14790 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 14803 -/* 14794 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 14842 -/* 14798 */ MCD_OPC_Decode, 227, 15, 196, 2, // Opcode: STOCFHAsmNL -/* 14803 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 14816 -/* 14807 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 14842 -/* 14811 */ MCD_OPC_Decode, 221, 15, 196, 2, // Opcode: STOCFHAsmLE -/* 14816 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 14829 -/* 14820 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 14842 -/* 14824 */ MCD_OPC_Decode, 225, 15, 196, 2, // Opcode: STOCFHAsmNH -/* 14829 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 14842 -/* 14833 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 14842 -/* 14837 */ MCD_OPC_Decode, 231, 15, 196, 2, // Opcode: STOCFHAsmNO -/* 14842 */ MCD_OPC_CheckPredicate, 12, 149, 16, // Skip to: 19091 -/* 14846 */ MCD_OPC_Decode, 216, 15, 197, 2, // Opcode: STOCFHAsm -/* 14851 */ MCD_OPC_FilterValue, 226, 1, 194, 0, // Skip to: 15050 -/* 14856 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 14859 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 14872 -/* 14863 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 15041 -/* 14867 */ MCD_OPC_Decode, 198, 11, 198, 2, // Opcode: LOCGAsmO -/* 14872 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 14885 -/* 14876 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 15041 -/* 14880 */ MCD_OPC_Decode, 182, 11, 198, 2, // Opcode: LOCGAsmH -/* 14885 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 14898 -/* 14889 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 15041 -/* 14893 */ MCD_OPC_Decode, 192, 11, 198, 2, // Opcode: LOCGAsmNLE -/* 14898 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 14911 -/* 14902 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 15041 -/* 14906 */ MCD_OPC_Decode, 184, 11, 198, 2, // Opcode: LOCGAsmL -/* 14911 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 14924 -/* 14915 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 15041 -/* 14919 */ MCD_OPC_Decode, 190, 11, 198, 2, // Opcode: LOCGAsmNHE -/* 14924 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 14937 -/* 14928 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 15041 -/* 14932 */ MCD_OPC_Decode, 186, 11, 198, 2, // Opcode: LOCGAsmLH -/* 14937 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 14950 -/* 14941 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 15041 -/* 14945 */ MCD_OPC_Decode, 188, 11, 198, 2, // Opcode: LOCGAsmNE -/* 14950 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 14963 -/* 14954 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 15041 -/* 14958 */ MCD_OPC_Decode, 181, 11, 198, 2, // Opcode: LOCGAsmE -/* 14963 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 14976 -/* 14967 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 15041 -/* 14971 */ MCD_OPC_Decode, 193, 11, 198, 2, // Opcode: LOCGAsmNLH -/* 14976 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 14989 -/* 14980 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 15041 -/* 14984 */ MCD_OPC_Decode, 183, 11, 198, 2, // Opcode: LOCGAsmHE -/* 14989 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15002 -/* 14993 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 15041 -/* 14997 */ MCD_OPC_Decode, 191, 11, 198, 2, // Opcode: LOCGAsmNL -/* 15002 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15015 -/* 15006 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 15041 -/* 15010 */ MCD_OPC_Decode, 185, 11, 198, 2, // Opcode: LOCGAsmLE -/* 15015 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15028 -/* 15019 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 15041 -/* 15023 */ MCD_OPC_Decode, 189, 11, 198, 2, // Opcode: LOCGAsmNH -/* 15028 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15041 -/* 15032 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 15041 -/* 15036 */ MCD_OPC_Decode, 195, 11, 198, 2, // Opcode: LOCGAsmNO -/* 15041 */ MCD_OPC_CheckPredicate, 14, 206, 15, // Skip to: 19091 -/* 15045 */ MCD_OPC_Decode, 180, 11, 199, 2, // Opcode: LOCGAsm -/* 15050 */ MCD_OPC_FilterValue, 227, 1, 194, 0, // Skip to: 15249 -/* 15055 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 15058 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 15071 -/* 15062 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 15240 -/* 15066 */ MCD_OPC_Decode, 128, 16, 182, 2, // Opcode: STOCGAsmO -/* 15071 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 15084 -/* 15075 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 15240 -/* 15079 */ MCD_OPC_Decode, 240, 15, 182, 2, // Opcode: STOCGAsmH -/* 15084 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 15097 -/* 15088 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 15240 -/* 15092 */ MCD_OPC_Decode, 250, 15, 182, 2, // Opcode: STOCGAsmNLE -/* 15097 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 15110 -/* 15101 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 15240 -/* 15105 */ MCD_OPC_Decode, 242, 15, 182, 2, // Opcode: STOCGAsmL -/* 15110 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 15123 -/* 15114 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 15240 -/* 15118 */ MCD_OPC_Decode, 248, 15, 182, 2, // Opcode: STOCGAsmNHE -/* 15123 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 15136 -/* 15127 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 15240 -/* 15131 */ MCD_OPC_Decode, 244, 15, 182, 2, // Opcode: STOCGAsmLH -/* 15136 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 15149 -/* 15140 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 15240 -/* 15144 */ MCD_OPC_Decode, 246, 15, 182, 2, // Opcode: STOCGAsmNE -/* 15149 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 15162 -/* 15153 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 15240 -/* 15157 */ MCD_OPC_Decode, 239, 15, 182, 2, // Opcode: STOCGAsmE -/* 15162 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 15175 -/* 15166 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 15240 -/* 15170 */ MCD_OPC_Decode, 251, 15, 182, 2, // Opcode: STOCGAsmNLH -/* 15175 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 15188 -/* 15179 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 15240 -/* 15183 */ MCD_OPC_Decode, 241, 15, 182, 2, // Opcode: STOCGAsmHE -/* 15188 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15201 -/* 15192 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 15240 -/* 15196 */ MCD_OPC_Decode, 249, 15, 182, 2, // Opcode: STOCGAsmNL -/* 15201 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15214 -/* 15205 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 15240 -/* 15209 */ MCD_OPC_Decode, 243, 15, 182, 2, // Opcode: STOCGAsmLE -/* 15214 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15227 -/* 15218 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 15240 -/* 15222 */ MCD_OPC_Decode, 247, 15, 182, 2, // Opcode: STOCGAsmNH -/* 15227 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15240 -/* 15231 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 15240 -/* 15235 */ MCD_OPC_Decode, 253, 15, 182, 2, // Opcode: STOCGAsmNO -/* 15240 */ MCD_OPC_CheckPredicate, 14, 7, 15, // Skip to: 19091 -/* 15244 */ MCD_OPC_Decode, 238, 15, 183, 2, // Opcode: STOCGAsm -/* 15249 */ MCD_OPC_FilterValue, 228, 1, 9, 0, // Skip to: 15263 -/* 15254 */ MCD_OPC_CheckPredicate, 17, 249, 14, // Skip to: 19091 -/* 15258 */ MCD_OPC_Decode, 247, 9, 172, 2, // Opcode: LANG -/* 15263 */ MCD_OPC_FilterValue, 230, 1, 9, 0, // Skip to: 15277 -/* 15268 */ MCD_OPC_CheckPredicate, 17, 235, 14, // Skip to: 19091 -/* 15272 */ MCD_OPC_Decode, 249, 9, 172, 2, // Opcode: LAOG -/* 15277 */ MCD_OPC_FilterValue, 231, 1, 9, 0, // Skip to: 15291 -/* 15282 */ MCD_OPC_CheckPredicate, 17, 221, 14, // Skip to: 19091 -/* 15286 */ MCD_OPC_Decode, 254, 9, 172, 2, // Opcode: LAXG -/* 15291 */ MCD_OPC_FilterValue, 232, 1, 9, 0, // Skip to: 15305 -/* 15296 */ MCD_OPC_CheckPredicate, 17, 207, 14, // Skip to: 19091 -/* 15300 */ MCD_OPC_Decode, 239, 9, 172, 2, // Opcode: LAAG -/* 15305 */ MCD_OPC_FilterValue, 234, 1, 9, 0, // Skip to: 15319 -/* 15310 */ MCD_OPC_CheckPredicate, 17, 193, 14, // Skip to: 19091 -/* 15314 */ MCD_OPC_Decode, 241, 9, 172, 2, // Opcode: LAALG -/* 15319 */ MCD_OPC_FilterValue, 242, 1, 194, 0, // Skip to: 15518 -/* 15324 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 15327 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 15340 -/* 15331 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 15509 -/* 15335 */ MCD_OPC_Decode, 132, 11, 200, 2, // Opcode: LOCAsmO -/* 15340 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 15353 -/* 15344 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 15509 -/* 15348 */ MCD_OPC_Decode, 244, 10, 200, 2, // Opcode: LOCAsmH -/* 15353 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 15366 -/* 15357 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 15509 -/* 15361 */ MCD_OPC_Decode, 254, 10, 200, 2, // Opcode: LOCAsmNLE -/* 15366 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 15379 -/* 15370 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 15509 -/* 15374 */ MCD_OPC_Decode, 246, 10, 200, 2, // Opcode: LOCAsmL -/* 15379 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 15392 -/* 15383 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 15509 -/* 15387 */ MCD_OPC_Decode, 252, 10, 200, 2, // Opcode: LOCAsmNHE -/* 15392 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 15405 -/* 15396 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 15509 -/* 15400 */ MCD_OPC_Decode, 248, 10, 200, 2, // Opcode: LOCAsmLH -/* 15405 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 15418 -/* 15409 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 15509 -/* 15413 */ MCD_OPC_Decode, 250, 10, 200, 2, // Opcode: LOCAsmNE -/* 15418 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 15431 -/* 15422 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 15509 -/* 15426 */ MCD_OPC_Decode, 243, 10, 200, 2, // Opcode: LOCAsmE -/* 15431 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 15444 -/* 15435 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 15509 -/* 15439 */ MCD_OPC_Decode, 255, 10, 200, 2, // Opcode: LOCAsmNLH -/* 15444 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 15457 -/* 15448 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 15509 -/* 15452 */ MCD_OPC_Decode, 245, 10, 200, 2, // Opcode: LOCAsmHE -/* 15457 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15470 -/* 15461 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 15509 -/* 15465 */ MCD_OPC_Decode, 253, 10, 200, 2, // Opcode: LOCAsmNL -/* 15470 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15483 -/* 15474 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 15509 -/* 15478 */ MCD_OPC_Decode, 247, 10, 200, 2, // Opcode: LOCAsmLE -/* 15483 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15496 -/* 15487 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 15509 -/* 15491 */ MCD_OPC_Decode, 251, 10, 200, 2, // Opcode: LOCAsmNH -/* 15496 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15509 -/* 15500 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 15509 -/* 15504 */ MCD_OPC_Decode, 129, 11, 200, 2, // Opcode: LOCAsmNO -/* 15509 */ MCD_OPC_CheckPredicate, 14, 250, 13, // Skip to: 19091 -/* 15513 */ MCD_OPC_Decode, 242, 10, 201, 2, // Opcode: LOCAsm -/* 15518 */ MCD_OPC_FilterValue, 243, 1, 194, 0, // Skip to: 15717 -/* 15523 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 15526 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 15539 -/* 15530 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 15708 -/* 15534 */ MCD_OPC_Decode, 212, 15, 178, 2, // Opcode: STOCAsmO -/* 15539 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 15552 -/* 15543 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 15708 -/* 15547 */ MCD_OPC_Decode, 196, 15, 178, 2, // Opcode: STOCAsmH -/* 15552 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 15565 -/* 15556 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 15708 -/* 15560 */ MCD_OPC_Decode, 206, 15, 178, 2, // Opcode: STOCAsmNLE -/* 15565 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 15578 -/* 15569 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 15708 -/* 15573 */ MCD_OPC_Decode, 198, 15, 178, 2, // Opcode: STOCAsmL -/* 15578 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 15591 -/* 15582 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 15708 -/* 15586 */ MCD_OPC_Decode, 204, 15, 178, 2, // Opcode: STOCAsmNHE -/* 15591 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 15604 -/* 15595 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 15708 -/* 15599 */ MCD_OPC_Decode, 200, 15, 178, 2, // Opcode: STOCAsmLH -/* 15604 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 15617 -/* 15608 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 15708 -/* 15612 */ MCD_OPC_Decode, 202, 15, 178, 2, // Opcode: STOCAsmNE -/* 15617 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 15630 -/* 15621 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 15708 -/* 15625 */ MCD_OPC_Decode, 195, 15, 178, 2, // Opcode: STOCAsmE -/* 15630 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 15643 -/* 15634 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 15708 -/* 15638 */ MCD_OPC_Decode, 207, 15, 178, 2, // Opcode: STOCAsmNLH -/* 15643 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 15656 -/* 15647 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 15708 -/* 15651 */ MCD_OPC_Decode, 197, 15, 178, 2, // Opcode: STOCAsmHE -/* 15656 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15669 -/* 15660 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 15708 -/* 15664 */ MCD_OPC_Decode, 205, 15, 178, 2, // Opcode: STOCAsmNL -/* 15669 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15682 -/* 15673 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 15708 -/* 15677 */ MCD_OPC_Decode, 199, 15, 178, 2, // Opcode: STOCAsmLE -/* 15682 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15695 -/* 15686 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 15708 -/* 15690 */ MCD_OPC_Decode, 203, 15, 178, 2, // Opcode: STOCAsmNH -/* 15695 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15708 -/* 15699 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 15708 -/* 15703 */ MCD_OPC_Decode, 209, 15, 178, 2, // Opcode: STOCAsmNO -/* 15708 */ MCD_OPC_CheckPredicate, 14, 51, 13, // Skip to: 19091 -/* 15712 */ MCD_OPC_Decode, 194, 15, 179, 2, // Opcode: STOCAsm -/* 15717 */ MCD_OPC_FilterValue, 244, 1, 9, 0, // Skip to: 15731 -/* 15722 */ MCD_OPC_CheckPredicate, 17, 37, 13, // Skip to: 19091 -/* 15726 */ MCD_OPC_Decode, 246, 9, 191, 2, // Opcode: LAN -/* 15731 */ MCD_OPC_FilterValue, 246, 1, 9, 0, // Skip to: 15745 -/* 15736 */ MCD_OPC_CheckPredicate, 17, 23, 13, // Skip to: 19091 -/* 15740 */ MCD_OPC_Decode, 248, 9, 191, 2, // Opcode: LAO -/* 15745 */ MCD_OPC_FilterValue, 247, 1, 9, 0, // Skip to: 15759 -/* 15750 */ MCD_OPC_CheckPredicate, 17, 9, 13, // Skip to: 19091 -/* 15754 */ MCD_OPC_Decode, 253, 9, 191, 2, // Opcode: LAX -/* 15759 */ MCD_OPC_FilterValue, 248, 1, 9, 0, // Skip to: 15773 -/* 15764 */ MCD_OPC_CheckPredicate, 17, 251, 12, // Skip to: 19091 -/* 15768 */ MCD_OPC_Decode, 238, 9, 191, 2, // Opcode: LAA -/* 15773 */ MCD_OPC_FilterValue, 250, 1, 241, 12, // Skip to: 19091 -/* 15778 */ MCD_OPC_CheckPredicate, 17, 237, 12, // Skip to: 19091 -/* 15782 */ MCD_OPC_Decode, 240, 9, 191, 2, // Opcode: LAAL -/* 15787 */ MCD_OPC_FilterValue, 236, 1, 195, 8, // Skip to: 18035 -/* 15792 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... -/* 15795 */ MCD_OPC_FilterValue, 66, 201, 0, // Skip to: 16000 -/* 15799 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... -/* 15802 */ MCD_OPC_FilterValue, 0, 213, 12, // Skip to: 19091 -/* 15806 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 15809 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 15822 -/* 15813 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 15991 -/* 15817 */ MCD_OPC_Decode, 158, 12, 202, 2, // Opcode: LOCHIAsmO -/* 15822 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 15835 -/* 15826 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 15991 -/* 15830 */ MCD_OPC_Decode, 142, 12, 202, 2, // Opcode: LOCHIAsmH -/* 15835 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 15848 -/* 15839 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 15991 -/* 15843 */ MCD_OPC_Decode, 152, 12, 202, 2, // Opcode: LOCHIAsmNLE -/* 15848 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 15861 -/* 15852 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 15991 -/* 15856 */ MCD_OPC_Decode, 144, 12, 202, 2, // Opcode: LOCHIAsmL -/* 15861 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 15874 -/* 15865 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 15991 -/* 15869 */ MCD_OPC_Decode, 150, 12, 202, 2, // Opcode: LOCHIAsmNHE -/* 15874 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 15887 -/* 15878 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 15991 -/* 15882 */ MCD_OPC_Decode, 146, 12, 202, 2, // Opcode: LOCHIAsmLH -/* 15887 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 15900 -/* 15891 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 15991 -/* 15895 */ MCD_OPC_Decode, 148, 12, 202, 2, // Opcode: LOCHIAsmNE -/* 15900 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 15913 -/* 15904 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 15991 -/* 15908 */ MCD_OPC_Decode, 141, 12, 202, 2, // Opcode: LOCHIAsmE -/* 15913 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 15926 -/* 15917 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 15991 -/* 15921 */ MCD_OPC_Decode, 153, 12, 202, 2, // Opcode: LOCHIAsmNLH -/* 15926 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 15939 -/* 15930 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 15991 -/* 15934 */ MCD_OPC_Decode, 143, 12, 202, 2, // Opcode: LOCHIAsmHE -/* 15939 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15952 -/* 15943 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 15991 -/* 15947 */ MCD_OPC_Decode, 151, 12, 202, 2, // Opcode: LOCHIAsmNL -/* 15952 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15965 -/* 15956 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 15991 -/* 15960 */ MCD_OPC_Decode, 145, 12, 202, 2, // Opcode: LOCHIAsmLE -/* 15965 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15978 -/* 15969 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 15991 -/* 15973 */ MCD_OPC_Decode, 149, 12, 202, 2, // Opcode: LOCHIAsmNH -/* 15978 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15991 -/* 15982 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 15991 -/* 15986 */ MCD_OPC_Decode, 155, 12, 202, 2, // Opcode: LOCHIAsmNO -/* 15991 */ MCD_OPC_CheckPredicate, 12, 24, 12, // Skip to: 19091 -/* 15995 */ MCD_OPC_Decode, 140, 12, 203, 2, // Opcode: LOCHIAsm -/* 16000 */ MCD_OPC_FilterValue, 68, 11, 0, // Skip to: 16015 -/* 16004 */ MCD_OPC_CheckField, 8, 8, 0, 9, 12, // Skip to: 19091 -/* 16010 */ MCD_OPC_Decode, 128, 4, 204, 2, // Opcode: BRXHG -/* 16015 */ MCD_OPC_FilterValue, 69, 11, 0, // Skip to: 16030 -/* 16019 */ MCD_OPC_CheckField, 8, 8, 0, 250, 11, // Skip to: 19091 -/* 16025 */ MCD_OPC_Decode, 130, 4, 204, 2, // Opcode: BRXLG -/* 16030 */ MCD_OPC_FilterValue, 70, 201, 0, // Skip to: 16235 -/* 16034 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... -/* 16037 */ MCD_OPC_FilterValue, 0, 234, 11, // Skip to: 19091 -/* 16041 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 16044 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 16057 -/* 16048 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 16226 -/* 16052 */ MCD_OPC_Decode, 220, 11, 205, 2, // Opcode: LOCGHIAsmO -/* 16057 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 16070 -/* 16061 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 16226 -/* 16065 */ MCD_OPC_Decode, 204, 11, 205, 2, // Opcode: LOCGHIAsmH -/* 16070 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 16083 -/* 16074 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 16226 -/* 16078 */ MCD_OPC_Decode, 214, 11, 205, 2, // Opcode: LOCGHIAsmNLE -/* 16083 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 16096 -/* 16087 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 16226 -/* 16091 */ MCD_OPC_Decode, 206, 11, 205, 2, // Opcode: LOCGHIAsmL -/* 16096 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 16109 -/* 16100 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 16226 -/* 16104 */ MCD_OPC_Decode, 212, 11, 205, 2, // Opcode: LOCGHIAsmNHE -/* 16109 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 16122 -/* 16113 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 16226 -/* 16117 */ MCD_OPC_Decode, 208, 11, 205, 2, // Opcode: LOCGHIAsmLH -/* 16122 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 16135 -/* 16126 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 16226 -/* 16130 */ MCD_OPC_Decode, 210, 11, 205, 2, // Opcode: LOCGHIAsmNE -/* 16135 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 16148 -/* 16139 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 16226 -/* 16143 */ MCD_OPC_Decode, 203, 11, 205, 2, // Opcode: LOCGHIAsmE -/* 16148 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 16161 -/* 16152 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 16226 -/* 16156 */ MCD_OPC_Decode, 215, 11, 205, 2, // Opcode: LOCGHIAsmNLH -/* 16161 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 16174 -/* 16165 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 16226 -/* 16169 */ MCD_OPC_Decode, 205, 11, 205, 2, // Opcode: LOCGHIAsmHE -/* 16174 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 16187 -/* 16178 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 16226 -/* 16182 */ MCD_OPC_Decode, 213, 11, 205, 2, // Opcode: LOCGHIAsmNL -/* 16187 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 16200 -/* 16191 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 16226 -/* 16195 */ MCD_OPC_Decode, 207, 11, 205, 2, // Opcode: LOCGHIAsmLE -/* 16200 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 16213 -/* 16204 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 16226 -/* 16208 */ MCD_OPC_Decode, 211, 11, 205, 2, // Opcode: LOCGHIAsmNH -/* 16213 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 16226 -/* 16217 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 16226 -/* 16221 */ MCD_OPC_Decode, 217, 11, 205, 2, // Opcode: LOCGHIAsmNO -/* 16226 */ MCD_OPC_CheckPredicate, 12, 45, 11, // Skip to: 19091 -/* 16230 */ MCD_OPC_Decode, 202, 11, 206, 2, // Opcode: LOCGHIAsm -/* 16235 */ MCD_OPC_FilterValue, 78, 201, 0, // Skip to: 16440 -/* 16239 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... -/* 16242 */ MCD_OPC_FilterValue, 0, 29, 11, // Skip to: 19091 -/* 16246 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 16249 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 16262 -/* 16253 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 16431 -/* 16257 */ MCD_OPC_Decode, 136, 12, 207, 2, // Opcode: LOCHHIAsmO -/* 16262 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 16275 -/* 16266 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 16431 -/* 16270 */ MCD_OPC_Decode, 248, 11, 207, 2, // Opcode: LOCHHIAsmH -/* 16275 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 16288 -/* 16279 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 16431 -/* 16283 */ MCD_OPC_Decode, 130, 12, 207, 2, // Opcode: LOCHHIAsmNLE -/* 16288 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 16301 -/* 16292 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 16431 -/* 16296 */ MCD_OPC_Decode, 250, 11, 207, 2, // Opcode: LOCHHIAsmL -/* 16301 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 16314 -/* 16305 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 16431 -/* 16309 */ MCD_OPC_Decode, 128, 12, 207, 2, // Opcode: LOCHHIAsmNHE -/* 16314 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 16327 -/* 16318 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 16431 -/* 16322 */ MCD_OPC_Decode, 252, 11, 207, 2, // Opcode: LOCHHIAsmLH -/* 16327 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 16340 -/* 16331 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 16431 -/* 16335 */ MCD_OPC_Decode, 254, 11, 207, 2, // Opcode: LOCHHIAsmNE -/* 16340 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 16353 -/* 16344 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 16431 -/* 16348 */ MCD_OPC_Decode, 247, 11, 207, 2, // Opcode: LOCHHIAsmE -/* 16353 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 16366 -/* 16357 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 16431 -/* 16361 */ MCD_OPC_Decode, 131, 12, 207, 2, // Opcode: LOCHHIAsmNLH -/* 16366 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 16379 -/* 16370 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 16431 -/* 16374 */ MCD_OPC_Decode, 249, 11, 207, 2, // Opcode: LOCHHIAsmHE -/* 16379 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 16392 -/* 16383 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 16431 -/* 16387 */ MCD_OPC_Decode, 129, 12, 207, 2, // Opcode: LOCHHIAsmNL -/* 16392 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 16405 -/* 16396 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 16431 -/* 16400 */ MCD_OPC_Decode, 251, 11, 207, 2, // Opcode: LOCHHIAsmLE -/* 16405 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 16418 -/* 16409 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 16431 -/* 16413 */ MCD_OPC_Decode, 255, 11, 207, 2, // Opcode: LOCHHIAsmNH -/* 16418 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 16431 -/* 16422 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 16431 -/* 16426 */ MCD_OPC_Decode, 133, 12, 207, 2, // Opcode: LOCHHIAsmNO -/* 16431 */ MCD_OPC_CheckPredicate, 12, 96, 10, // Skip to: 19091 -/* 16435 */ MCD_OPC_Decode, 246, 11, 208, 2, // Opcode: LOCHHIAsm -/* 16440 */ MCD_OPC_FilterValue, 81, 9, 0, // Skip to: 16453 -/* 16444 */ MCD_OPC_CheckPredicate, 11, 83, 10, // Skip to: 19091 -/* 16448 */ MCD_OPC_Decode, 165, 14, 209, 2, // Opcode: RISBLG -/* 16453 */ MCD_OPC_FilterValue, 84, 5, 0, // Skip to: 16462 -/* 16457 */ MCD_OPC_Decode, 168, 14, 210, 2, // Opcode: RNSBG -/* 16462 */ MCD_OPC_FilterValue, 85, 5, 0, // Skip to: 16471 -/* 16466 */ MCD_OPC_Decode, 161, 14, 210, 2, // Opcode: RISBG -/* 16471 */ MCD_OPC_FilterValue, 86, 5, 0, // Skip to: 16480 -/* 16475 */ MCD_OPC_Decode, 169, 14, 210, 2, // Opcode: ROSBG -/* 16480 */ MCD_OPC_FilterValue, 87, 5, 0, // Skip to: 16489 -/* 16484 */ MCD_OPC_Decode, 176, 14, 210, 2, // Opcode: RXSBG -/* 16489 */ MCD_OPC_FilterValue, 89, 9, 0, // Skip to: 16502 -/* 16493 */ MCD_OPC_CheckPredicate, 24, 34, 10, // Skip to: 19091 -/* 16497 */ MCD_OPC_Decode, 163, 14, 210, 2, // Opcode: RISBGN -/* 16502 */ MCD_OPC_FilterValue, 93, 9, 0, // Skip to: 16515 -/* 16506 */ MCD_OPC_CheckPredicate, 11, 21, 10, // Skip to: 19091 -/* 16510 */ MCD_OPC_Decode, 164, 14, 211, 2, // Opcode: RISBHG -/* 16515 */ MCD_OPC_FilterValue, 100, 69, 0, // Skip to: 16588 -/* 16519 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 16522 */ MCD_OPC_FilterValue, 0, 5, 10, // Skip to: 19091 -/* 16526 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 16529 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16538 -/* 16533 */ MCD_OPC_Decode, 140, 5, 212, 2, // Opcode: CGRJAsmH -/* 16538 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16547 -/* 16542 */ MCD_OPC_Decode, 142, 5, 212, 2, // Opcode: CGRJAsmL -/* 16547 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16556 -/* 16551 */ MCD_OPC_Decode, 144, 5, 212, 2, // Opcode: CGRJAsmLH -/* 16556 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16565 -/* 16560 */ MCD_OPC_Decode, 139, 5, 212, 2, // Opcode: CGRJAsmE -/* 16565 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16574 -/* 16569 */ MCD_OPC_Decode, 141, 5, 212, 2, // Opcode: CGRJAsmHE -/* 16574 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16583 -/* 16578 */ MCD_OPC_Decode, 143, 5, 212, 2, // Opcode: CGRJAsmLE -/* 16583 */ MCD_OPC_Decode, 138, 5, 213, 2, // Opcode: CGRJAsm -/* 16588 */ MCD_OPC_FilterValue, 101, 69, 0, // Skip to: 16661 -/* 16592 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 16595 */ MCD_OPC_FilterValue, 0, 188, 9, // Skip to: 19091 -/* 16599 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 16602 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16611 -/* 16606 */ MCD_OPC_Decode, 192, 6, 212, 2, // Opcode: CLGRJAsmH -/* 16611 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16620 -/* 16615 */ MCD_OPC_Decode, 194, 6, 212, 2, // Opcode: CLGRJAsmL -/* 16620 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16629 -/* 16624 */ MCD_OPC_Decode, 196, 6, 212, 2, // Opcode: CLGRJAsmLH -/* 16629 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16638 -/* 16633 */ MCD_OPC_Decode, 191, 6, 212, 2, // Opcode: CLGRJAsmE -/* 16638 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16647 -/* 16642 */ MCD_OPC_Decode, 193, 6, 212, 2, // Opcode: CLGRJAsmHE -/* 16647 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16656 -/* 16651 */ MCD_OPC_Decode, 195, 6, 212, 2, // Opcode: CLGRJAsmLE -/* 16656 */ MCD_OPC_Decode, 190, 6, 213, 2, // Opcode: CLGRJAsm -/* 16661 */ MCD_OPC_FilterValue, 112, 76, 0, // Skip to: 16741 -/* 16665 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 16668 */ MCD_OPC_FilterValue, 0, 115, 9, // Skip to: 19091 -/* 16672 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 16675 */ MCD_OPC_FilterValue, 0, 108, 9, // Skip to: 19091 -/* 16679 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 16682 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16691 -/* 16686 */ MCD_OPC_Decode, 239, 4, 214, 2, // Opcode: CGITAsmH -/* 16691 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16700 -/* 16695 */ MCD_OPC_Decode, 241, 4, 214, 2, // Opcode: CGITAsmL -/* 16700 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16709 -/* 16704 */ MCD_OPC_Decode, 243, 4, 214, 2, // Opcode: CGITAsmLH -/* 16709 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16718 -/* 16713 */ MCD_OPC_Decode, 238, 4, 214, 2, // Opcode: CGITAsmE -/* 16718 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16727 -/* 16722 */ MCD_OPC_Decode, 240, 4, 214, 2, // Opcode: CGITAsmHE -/* 16727 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16736 -/* 16731 */ MCD_OPC_Decode, 242, 4, 214, 2, // Opcode: CGITAsmLE -/* 16736 */ MCD_OPC_Decode, 237, 4, 215, 2, // Opcode: CGITAsm -/* 16741 */ MCD_OPC_FilterValue, 113, 76, 0, // Skip to: 16821 -/* 16745 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 16748 */ MCD_OPC_FilterValue, 0, 35, 9, // Skip to: 19091 -/* 16752 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 16755 */ MCD_OPC_FilterValue, 0, 28, 9, // Skip to: 19091 -/* 16759 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 16762 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16771 -/* 16766 */ MCD_OPC_Decode, 163, 6, 216, 2, // Opcode: CLGITAsmH -/* 16771 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16780 -/* 16775 */ MCD_OPC_Decode, 165, 6, 216, 2, // Opcode: CLGITAsmL -/* 16780 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16789 -/* 16784 */ MCD_OPC_Decode, 167, 6, 216, 2, // Opcode: CLGITAsmLH -/* 16789 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16798 -/* 16793 */ MCD_OPC_Decode, 162, 6, 216, 2, // Opcode: CLGITAsmE -/* 16798 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16807 -/* 16802 */ MCD_OPC_Decode, 164, 6, 216, 2, // Opcode: CLGITAsmHE -/* 16807 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16816 -/* 16811 */ MCD_OPC_Decode, 166, 6, 216, 2, // Opcode: CLGITAsmLE -/* 16816 */ MCD_OPC_Decode, 161, 6, 217, 2, // Opcode: CLGITAsm -/* 16821 */ MCD_OPC_FilterValue, 114, 76, 0, // Skip to: 16901 -/* 16825 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 16828 */ MCD_OPC_FilterValue, 0, 211, 8, // Skip to: 19091 -/* 16832 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 16835 */ MCD_OPC_FilterValue, 0, 204, 8, // Skip to: 19091 -/* 16839 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 16842 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16851 -/* 16846 */ MCD_OPC_Decode, 212, 5, 218, 2, // Opcode: CITAsmH -/* 16851 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16860 -/* 16855 */ MCD_OPC_Decode, 214, 5, 218, 2, // Opcode: CITAsmL -/* 16860 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16869 -/* 16864 */ MCD_OPC_Decode, 216, 5, 218, 2, // Opcode: CITAsmLH -/* 16869 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16878 -/* 16873 */ MCD_OPC_Decode, 211, 5, 218, 2, // Opcode: CITAsmE -/* 16878 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16887 -/* 16882 */ MCD_OPC_Decode, 213, 5, 218, 2, // Opcode: CITAsmHE -/* 16887 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16896 -/* 16891 */ MCD_OPC_Decode, 215, 5, 218, 2, // Opcode: CITAsmLE -/* 16896 */ MCD_OPC_Decode, 210, 5, 219, 2, // Opcode: CITAsm -/* 16901 */ MCD_OPC_FilterValue, 115, 76, 0, // Skip to: 16981 -/* 16905 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 16908 */ MCD_OPC_FilterValue, 0, 131, 8, // Skip to: 19091 -/* 16912 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 16915 */ MCD_OPC_FilterValue, 0, 124, 8, // Skip to: 19091 -/* 16919 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 16922 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16931 -/* 16926 */ MCD_OPC_Decode, 237, 5, 220, 2, // Opcode: CLFITAsmH -/* 16931 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16940 -/* 16935 */ MCD_OPC_Decode, 239, 5, 220, 2, // Opcode: CLFITAsmL -/* 16940 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16949 -/* 16944 */ MCD_OPC_Decode, 241, 5, 220, 2, // Opcode: CLFITAsmLH -/* 16949 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16958 -/* 16953 */ MCD_OPC_Decode, 236, 5, 220, 2, // Opcode: CLFITAsmE -/* 16958 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16967 -/* 16962 */ MCD_OPC_Decode, 238, 5, 220, 2, // Opcode: CLFITAsmHE -/* 16967 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16976 -/* 16971 */ MCD_OPC_Decode, 240, 5, 220, 2, // Opcode: CLFITAsmLE -/* 16976 */ MCD_OPC_Decode, 235, 5, 221, 2, // Opcode: CLFITAsm -/* 16981 */ MCD_OPC_FilterValue, 118, 69, 0, // Skip to: 17054 -/* 16985 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 16988 */ MCD_OPC_FilterValue, 0, 51, 8, // Skip to: 19091 -/* 16992 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 16995 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17004 -/* 16999 */ MCD_OPC_Decode, 234, 7, 222, 2, // Opcode: CRJAsmH -/* 17004 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17013 -/* 17008 */ MCD_OPC_Decode, 236, 7, 222, 2, // Opcode: CRJAsmL -/* 17013 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17022 -/* 17017 */ MCD_OPC_Decode, 238, 7, 222, 2, // Opcode: CRJAsmLH -/* 17022 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17031 -/* 17026 */ MCD_OPC_Decode, 233, 7, 222, 2, // Opcode: CRJAsmE -/* 17031 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17040 -/* 17035 */ MCD_OPC_Decode, 235, 7, 222, 2, // Opcode: CRJAsmHE -/* 17040 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17049 -/* 17044 */ MCD_OPC_Decode, 237, 7, 222, 2, // Opcode: CRJAsmLE -/* 17049 */ MCD_OPC_Decode, 232, 7, 223, 2, // Opcode: CRJAsm -/* 17054 */ MCD_OPC_FilterValue, 119, 69, 0, // Skip to: 17127 -/* 17058 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 17061 */ MCD_OPC_FilterValue, 0, 234, 7, // Skip to: 19091 -/* 17065 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 17068 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17077 -/* 17072 */ MCD_OPC_Decode, 163, 7, 222, 2, // Opcode: CLRJAsmH -/* 17077 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17086 -/* 17081 */ MCD_OPC_Decode, 165, 7, 222, 2, // Opcode: CLRJAsmL -/* 17086 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17095 -/* 17090 */ MCD_OPC_Decode, 167, 7, 222, 2, // Opcode: CLRJAsmLH -/* 17095 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17104 -/* 17099 */ MCD_OPC_Decode, 162, 7, 222, 2, // Opcode: CLRJAsmE -/* 17104 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17113 -/* 17108 */ MCD_OPC_Decode, 164, 7, 222, 2, // Opcode: CLRJAsmHE -/* 17113 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17122 -/* 17117 */ MCD_OPC_Decode, 166, 7, 222, 2, // Opcode: CLRJAsmLE -/* 17122 */ MCD_OPC_Decode, 161, 7, 223, 2, // Opcode: CLRJAsm -/* 17127 */ MCD_OPC_FilterValue, 124, 62, 0, // Skip to: 17193 -/* 17131 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 17134 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17143 -/* 17138 */ MCD_OPC_Decode, 225, 4, 224, 2, // Opcode: CGIJAsmH -/* 17143 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17152 -/* 17147 */ MCD_OPC_Decode, 227, 4, 224, 2, // Opcode: CGIJAsmL -/* 17152 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17161 -/* 17156 */ MCD_OPC_Decode, 229, 4, 224, 2, // Opcode: CGIJAsmLH -/* 17161 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17170 -/* 17165 */ MCD_OPC_Decode, 224, 4, 224, 2, // Opcode: CGIJAsmE -/* 17170 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17179 -/* 17174 */ MCD_OPC_Decode, 226, 4, 224, 2, // Opcode: CGIJAsmHE -/* 17179 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17188 -/* 17183 */ MCD_OPC_Decode, 228, 4, 224, 2, // Opcode: CGIJAsmLE -/* 17188 */ MCD_OPC_Decode, 223, 4, 225, 2, // Opcode: CGIJAsm -/* 17193 */ MCD_OPC_FilterValue, 125, 62, 0, // Skip to: 17259 -/* 17197 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 17200 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17209 -/* 17204 */ MCD_OPC_Decode, 149, 6, 226, 2, // Opcode: CLGIJAsmH -/* 17209 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17218 -/* 17213 */ MCD_OPC_Decode, 151, 6, 226, 2, // Opcode: CLGIJAsmL -/* 17218 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17227 -/* 17222 */ MCD_OPC_Decode, 153, 6, 226, 2, // Opcode: CLGIJAsmLH -/* 17227 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17236 -/* 17231 */ MCD_OPC_Decode, 148, 6, 226, 2, // Opcode: CLGIJAsmE -/* 17236 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17245 -/* 17240 */ MCD_OPC_Decode, 150, 6, 226, 2, // Opcode: CLGIJAsmHE -/* 17245 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17254 -/* 17249 */ MCD_OPC_Decode, 152, 6, 226, 2, // Opcode: CLGIJAsmLE -/* 17254 */ MCD_OPC_Decode, 147, 6, 227, 2, // Opcode: CLGIJAsm -/* 17259 */ MCD_OPC_FilterValue, 126, 62, 0, // Skip to: 17325 -/* 17263 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 17266 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17275 -/* 17270 */ MCD_OPC_Decode, 198, 5, 228, 2, // Opcode: CIJAsmH -/* 17275 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17284 -/* 17279 */ MCD_OPC_Decode, 200, 5, 228, 2, // Opcode: CIJAsmL -/* 17284 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17293 -/* 17288 */ MCD_OPC_Decode, 202, 5, 228, 2, // Opcode: CIJAsmLH -/* 17293 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17302 -/* 17297 */ MCD_OPC_Decode, 197, 5, 228, 2, // Opcode: CIJAsmE -/* 17302 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17311 -/* 17306 */ MCD_OPC_Decode, 199, 5, 228, 2, // Opcode: CIJAsmHE -/* 17311 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17320 -/* 17315 */ MCD_OPC_Decode, 201, 5, 228, 2, // Opcode: CIJAsmLE -/* 17320 */ MCD_OPC_Decode, 196, 5, 229, 2, // Opcode: CIJAsm -/* 17325 */ MCD_OPC_FilterValue, 127, 62, 0, // Skip to: 17391 -/* 17329 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 17332 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17341 -/* 17336 */ MCD_OPC_Decode, 130, 7, 230, 2, // Opcode: CLIJAsmH -/* 17341 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17350 -/* 17345 */ MCD_OPC_Decode, 132, 7, 230, 2, // Opcode: CLIJAsmL -/* 17350 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17359 -/* 17354 */ MCD_OPC_Decode, 134, 7, 230, 2, // Opcode: CLIJAsmLH -/* 17359 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17368 -/* 17363 */ MCD_OPC_Decode, 129, 7, 230, 2, // Opcode: CLIJAsmE -/* 17368 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17377 -/* 17372 */ MCD_OPC_Decode, 131, 7, 230, 2, // Opcode: CLIJAsmHE -/* 17377 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17386 -/* 17381 */ MCD_OPC_Decode, 133, 7, 230, 2, // Opcode: CLIJAsmLE -/* 17386 */ MCD_OPC_Decode, 128, 7, 231, 2, // Opcode: CLIJAsm -/* 17391 */ MCD_OPC_FilterValue, 216, 1, 15, 0, // Skip to: 17411 -/* 17396 */ MCD_OPC_CheckPredicate, 15, 155, 6, // Skip to: 19091 -/* 17400 */ MCD_OPC_CheckField, 8, 8, 0, 149, 6, // Skip to: 19091 -/* 17406 */ MCD_OPC_Decode, 254, 2, 232, 2, // Opcode: AHIK -/* 17411 */ MCD_OPC_FilterValue, 217, 1, 15, 0, // Skip to: 17431 -/* 17416 */ MCD_OPC_CheckPredicate, 15, 135, 6, // Skip to: 19091 -/* 17420 */ MCD_OPC_CheckField, 8, 8, 0, 129, 6, // Skip to: 19091 -/* 17426 */ MCD_OPC_Decode, 246, 2, 233, 2, // Opcode: AGHIK -/* 17431 */ MCD_OPC_FilterValue, 218, 1, 15, 0, // Skip to: 17451 -/* 17436 */ MCD_OPC_CheckPredicate, 15, 115, 6, // Skip to: 19091 -/* 17440 */ MCD_OPC_CheckField, 8, 8, 0, 109, 6, // Skip to: 19091 -/* 17446 */ MCD_OPC_Decode, 145, 3, 232, 2, // Opcode: ALHSIK -/* 17451 */ MCD_OPC_FilterValue, 219, 1, 15, 0, // Skip to: 17471 -/* 17456 */ MCD_OPC_CheckPredicate, 15, 95, 6, // Skip to: 19091 -/* 17460 */ MCD_OPC_CheckField, 8, 8, 0, 89, 6, // Skip to: 19091 -/* 17466 */ MCD_OPC_Decode, 139, 3, 233, 2, // Opcode: ALGHSIK -/* 17471 */ MCD_OPC_FilterValue, 228, 1, 69, 0, // Skip to: 17545 -/* 17476 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 17479 */ MCD_OPC_FilterValue, 0, 72, 6, // Skip to: 19091 -/* 17483 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 17486 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17495 -/* 17490 */ MCD_OPC_Decode, 254, 4, 234, 2, // Opcode: CGRBAsmH -/* 17495 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17504 -/* 17499 */ MCD_OPC_Decode, 128, 5, 234, 2, // Opcode: CGRBAsmL -/* 17504 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17513 -/* 17508 */ MCD_OPC_Decode, 130, 5, 234, 2, // Opcode: CGRBAsmLH -/* 17513 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17522 -/* 17517 */ MCD_OPC_Decode, 253, 4, 234, 2, // Opcode: CGRBAsmE -/* 17522 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17531 -/* 17526 */ MCD_OPC_Decode, 255, 4, 234, 2, // Opcode: CGRBAsmHE -/* 17531 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17540 -/* 17535 */ MCD_OPC_Decode, 129, 5, 234, 2, // Opcode: CGRBAsmLE -/* 17540 */ MCD_OPC_Decode, 252, 4, 235, 2, // Opcode: CGRBAsm -/* 17545 */ MCD_OPC_FilterValue, 229, 1, 69, 0, // Skip to: 17619 -/* 17550 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 17553 */ MCD_OPC_FilterValue, 0, 254, 5, // Skip to: 19091 -/* 17557 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 17560 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17569 -/* 17564 */ MCD_OPC_Decode, 178, 6, 234, 2, // Opcode: CLGRBAsmH -/* 17569 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17578 -/* 17573 */ MCD_OPC_Decode, 180, 6, 234, 2, // Opcode: CLGRBAsmL -/* 17578 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17587 -/* 17582 */ MCD_OPC_Decode, 182, 6, 234, 2, // Opcode: CLGRBAsmLH -/* 17587 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17596 -/* 17591 */ MCD_OPC_Decode, 177, 6, 234, 2, // Opcode: CLGRBAsmE -/* 17596 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17605 -/* 17600 */ MCD_OPC_Decode, 179, 6, 234, 2, // Opcode: CLGRBAsmHE -/* 17605 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17614 -/* 17609 */ MCD_OPC_Decode, 181, 6, 234, 2, // Opcode: CLGRBAsmLE -/* 17614 */ MCD_OPC_Decode, 176, 6, 235, 2, // Opcode: CLGRBAsm -/* 17619 */ MCD_OPC_FilterValue, 246, 1, 69, 0, // Skip to: 17693 -/* 17624 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 17627 */ MCD_OPC_FilterValue, 0, 180, 5, // Skip to: 19091 -/* 17631 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 17634 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17643 -/* 17638 */ MCD_OPC_Decode, 218, 7, 236, 2, // Opcode: CRBAsmH -/* 17643 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17652 -/* 17647 */ MCD_OPC_Decode, 220, 7, 236, 2, // Opcode: CRBAsmL -/* 17652 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17661 -/* 17656 */ MCD_OPC_Decode, 222, 7, 236, 2, // Opcode: CRBAsmLH -/* 17661 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17670 -/* 17665 */ MCD_OPC_Decode, 217, 7, 236, 2, // Opcode: CRBAsmE -/* 17670 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17679 -/* 17674 */ MCD_OPC_Decode, 219, 7, 236, 2, // Opcode: CRBAsmHE -/* 17679 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17688 -/* 17683 */ MCD_OPC_Decode, 221, 7, 236, 2, // Opcode: CRBAsmLE -/* 17688 */ MCD_OPC_Decode, 216, 7, 237, 2, // Opcode: CRBAsm -/* 17693 */ MCD_OPC_FilterValue, 247, 1, 69, 0, // Skip to: 17767 -/* 17698 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 17701 */ MCD_OPC_FilterValue, 0, 106, 5, // Skip to: 19091 -/* 17705 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 17708 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17717 -/* 17712 */ MCD_OPC_Decode, 149, 7, 236, 2, // Opcode: CLRBAsmH -/* 17717 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17726 -/* 17721 */ MCD_OPC_Decode, 151, 7, 236, 2, // Opcode: CLRBAsmL -/* 17726 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17735 -/* 17730 */ MCD_OPC_Decode, 153, 7, 236, 2, // Opcode: CLRBAsmLH -/* 17735 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17744 -/* 17739 */ MCD_OPC_Decode, 148, 7, 236, 2, // Opcode: CLRBAsmE -/* 17744 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17753 -/* 17748 */ MCD_OPC_Decode, 150, 7, 236, 2, // Opcode: CLRBAsmHE -/* 17753 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17762 -/* 17757 */ MCD_OPC_Decode, 152, 7, 236, 2, // Opcode: CLRBAsmLE -/* 17762 */ MCD_OPC_Decode, 147, 7, 237, 2, // Opcode: CLRBAsm -/* 17767 */ MCD_OPC_FilterValue, 252, 1, 62, 0, // Skip to: 17834 -/* 17772 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 17775 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17784 -/* 17779 */ MCD_OPC_Decode, 211, 4, 238, 2, // Opcode: CGIBAsmH -/* 17784 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17793 -/* 17788 */ MCD_OPC_Decode, 213, 4, 238, 2, // Opcode: CGIBAsmL -/* 17793 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17802 -/* 17797 */ MCD_OPC_Decode, 215, 4, 238, 2, // Opcode: CGIBAsmLH -/* 17802 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17811 -/* 17806 */ MCD_OPC_Decode, 210, 4, 238, 2, // Opcode: CGIBAsmE -/* 17811 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17820 -/* 17815 */ MCD_OPC_Decode, 212, 4, 238, 2, // Opcode: CGIBAsmHE -/* 17820 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17829 -/* 17824 */ MCD_OPC_Decode, 214, 4, 238, 2, // Opcode: CGIBAsmLE -/* 17829 */ MCD_OPC_Decode, 209, 4, 239, 2, // Opcode: CGIBAsm -/* 17834 */ MCD_OPC_FilterValue, 253, 1, 62, 0, // Skip to: 17901 -/* 17839 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 17842 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17851 -/* 17846 */ MCD_OPC_Decode, 135, 6, 240, 2, // Opcode: CLGIBAsmH -/* 17851 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17860 -/* 17855 */ MCD_OPC_Decode, 137, 6, 240, 2, // Opcode: CLGIBAsmL -/* 17860 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17869 -/* 17864 */ MCD_OPC_Decode, 139, 6, 240, 2, // Opcode: CLGIBAsmLH -/* 17869 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17878 -/* 17873 */ MCD_OPC_Decode, 134, 6, 240, 2, // Opcode: CLGIBAsmE -/* 17878 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17887 -/* 17882 */ MCD_OPC_Decode, 136, 6, 240, 2, // Opcode: CLGIBAsmHE -/* 17887 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17896 -/* 17891 */ MCD_OPC_Decode, 138, 6, 240, 2, // Opcode: CLGIBAsmLE -/* 17896 */ MCD_OPC_Decode, 133, 6, 241, 2, // Opcode: CLGIBAsm -/* 17901 */ MCD_OPC_FilterValue, 254, 1, 62, 0, // Skip to: 17968 -/* 17906 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 17909 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17918 -/* 17913 */ MCD_OPC_Decode, 183, 5, 242, 2, // Opcode: CIBAsmH -/* 17918 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17927 -/* 17922 */ MCD_OPC_Decode, 185, 5, 242, 2, // Opcode: CIBAsmL -/* 17927 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17936 -/* 17931 */ MCD_OPC_Decode, 187, 5, 242, 2, // Opcode: CIBAsmLH -/* 17936 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17945 -/* 17940 */ MCD_OPC_Decode, 182, 5, 242, 2, // Opcode: CIBAsmE -/* 17945 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17954 -/* 17949 */ MCD_OPC_Decode, 184, 5, 242, 2, // Opcode: CIBAsmHE -/* 17954 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17963 -/* 17958 */ MCD_OPC_Decode, 186, 5, 242, 2, // Opcode: CIBAsmLE -/* 17963 */ MCD_OPC_Decode, 181, 5, 243, 2, // Opcode: CIBAsm -/* 17968 */ MCD_OPC_FilterValue, 255, 1, 94, 4, // Skip to: 19091 -/* 17973 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 17976 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17985 -/* 17980 */ MCD_OPC_Decode, 243, 6, 244, 2, // Opcode: CLIBAsmH -/* 17985 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17994 -/* 17989 */ MCD_OPC_Decode, 245, 6, 244, 2, // Opcode: CLIBAsmL -/* 17994 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 18003 -/* 17998 */ MCD_OPC_Decode, 247, 6, 244, 2, // Opcode: CLIBAsmLH -/* 18003 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 18012 -/* 18007 */ MCD_OPC_Decode, 242, 6, 244, 2, // Opcode: CLIBAsmE -/* 18012 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 18021 -/* 18016 */ MCD_OPC_Decode, 244, 6, 244, 2, // Opcode: CLIBAsmHE -/* 18021 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 18030 -/* 18025 */ MCD_OPC_Decode, 246, 6, 244, 2, // Opcode: CLIBAsmLE -/* 18030 */ MCD_OPC_Decode, 241, 6, 245, 2, // Opcode: CLIBAsm -/* 18035 */ MCD_OPC_FilterValue, 237, 1, 163, 3, // Skip to: 18971 -/* 18040 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... -/* 18043 */ MCD_OPC_FilterValue, 4, 11, 0, // Skip to: 18058 -/* 18047 */ MCD_OPC_CheckField, 8, 8, 0, 14, 4, // Skip to: 19091 -/* 18053 */ MCD_OPC_Decode, 149, 10, 246, 2, // Opcode: LDEB -/* 18058 */ MCD_OPC_FilterValue, 5, 11, 0, // Skip to: 18073 -/* 18062 */ MCD_OPC_CheckField, 8, 8, 0, 255, 3, // Skip to: 19091 -/* 18068 */ MCD_OPC_Decode, 235, 12, 247, 2, // Opcode: LXDB -/* 18073 */ MCD_OPC_FilterValue, 6, 11, 0, // Skip to: 18088 -/* 18077 */ MCD_OPC_CheckField, 8, 8, 0, 240, 3, // Skip to: 19091 -/* 18083 */ MCD_OPC_Decode, 240, 12, 247, 2, // Opcode: LXEB -/* 18088 */ MCD_OPC_FilterValue, 7, 11, 0, // Skip to: 18103 -/* 18092 */ MCD_OPC_CheckField, 8, 8, 0, 225, 3, // Skip to: 19091 -/* 18098 */ MCD_OPC_Decode, 214, 13, 248, 2, // Opcode: MXDB -/* 18103 */ MCD_OPC_FilterValue, 8, 11, 0, // Skip to: 18118 -/* 18107 */ MCD_OPC_CheckField, 8, 8, 0, 210, 3, // Skip to: 19091 -/* 18113 */ MCD_OPC_Decode, 223, 9, 249, 2, // Opcode: KEB -/* 18118 */ MCD_OPC_FilterValue, 9, 11, 0, // Skip to: 18133 -/* 18122 */ MCD_OPC_CheckField, 8, 8, 0, 195, 3, // Skip to: 19091 -/* 18128 */ MCD_OPC_Decode, 165, 4, 249, 2, // Opcode: CEB -/* 18133 */ MCD_OPC_FilterValue, 10, 11, 0, // Skip to: 18148 -/* 18137 */ MCD_OPC_CheckField, 8, 8, 0, 180, 3, // Skip to: 19091 -/* 18143 */ MCD_OPC_Decode, 236, 2, 250, 2, // Opcode: AEB -/* 18148 */ MCD_OPC_FilterValue, 11, 11, 0, // Skip to: 18163 -/* 18152 */ MCD_OPC_CheckField, 8, 8, 0, 165, 3, // Skip to: 19091 -/* 18158 */ MCD_OPC_Decode, 197, 14, 250, 2, // Opcode: SEB -/* 18163 */ MCD_OPC_FilterValue, 12, 11, 0, // Skip to: 18178 -/* 18167 */ MCD_OPC_CheckField, 8, 8, 0, 150, 3, // Skip to: 19091 -/* 18173 */ MCD_OPC_Decode, 142, 13, 251, 2, // Opcode: MDEB -/* 18178 */ MCD_OPC_FilterValue, 13, 11, 0, // Skip to: 18193 -/* 18182 */ MCD_OPC_CheckField, 8, 8, 0, 135, 3, // Skip to: 19091 -/* 18188 */ MCD_OPC_Decode, 195, 8, 250, 2, // Opcode: DEB -/* 18193 */ MCD_OPC_FilterValue, 14, 11, 0, // Skip to: 18208 -/* 18197 */ MCD_OPC_CheckField, 8, 4, 0, 120, 3, // Skip to: 19091 -/* 18203 */ MCD_OPC_Decode, 128, 13, 252, 2, // Opcode: MAEB -/* 18208 */ MCD_OPC_FilterValue, 15, 11, 0, // Skip to: 18223 -/* 18212 */ MCD_OPC_CheckField, 8, 4, 0, 105, 3, // Skip to: 19091 -/* 18218 */ MCD_OPC_Decode, 176, 13, 252, 2, // Opcode: MSEB -/* 18223 */ MCD_OPC_FilterValue, 16, 11, 0, // Skip to: 18238 -/* 18227 */ MCD_OPC_CheckField, 8, 8, 0, 90, 3, // Skip to: 19091 -/* 18233 */ MCD_OPC_Decode, 164, 16, 249, 2, // Opcode: TCEB -/* 18238 */ MCD_OPC_FilterValue, 17, 11, 0, // Skip to: 18253 -/* 18242 */ MCD_OPC_CheckField, 8, 8, 0, 75, 3, // Skip to: 19091 -/* 18248 */ MCD_OPC_Decode, 163, 16, 246, 2, // Opcode: TCDB -/* 18253 */ MCD_OPC_FilterValue, 18, 11, 0, // Skip to: 18268 -/* 18257 */ MCD_OPC_CheckField, 8, 8, 0, 60, 3, // Skip to: 19091 -/* 18263 */ MCD_OPC_Decode, 165, 16, 247, 2, // Opcode: TCXB -/* 18268 */ MCD_OPC_FilterValue, 20, 11, 0, // Skip to: 18283 -/* 18272 */ MCD_OPC_CheckField, 8, 8, 0, 45, 3, // Skip to: 19091 -/* 18278 */ MCD_OPC_Decode, 253, 14, 249, 2, // Opcode: SQEB -/* 18283 */ MCD_OPC_FilterValue, 21, 11, 0, // Skip to: 18298 -/* 18287 */ MCD_OPC_CheckField, 8, 8, 0, 30, 3, // Skip to: 19091 -/* 18293 */ MCD_OPC_Decode, 249, 14, 246, 2, // Opcode: SQDB -/* 18298 */ MCD_OPC_FilterValue, 23, 11, 0, // Skip to: 18313 -/* 18302 */ MCD_OPC_CheckField, 8, 8, 0, 15, 3, // Skip to: 19091 -/* 18308 */ MCD_OPC_Decode, 150, 13, 250, 2, // Opcode: MEEB -/* 18313 */ MCD_OPC_FilterValue, 24, 11, 0, // Skip to: 18328 -/* 18317 */ MCD_OPC_CheckField, 8, 8, 0, 0, 3, // Skip to: 19091 -/* 18323 */ MCD_OPC_Decode, 220, 9, 246, 2, // Opcode: KDB -/* 18328 */ MCD_OPC_FilterValue, 25, 11, 0, // Skip to: 18343 -/* 18332 */ MCD_OPC_CheckField, 8, 8, 0, 241, 2, // Skip to: 19091 -/* 18338 */ MCD_OPC_Decode, 140, 4, 246, 2, // Opcode: CDB -/* 18343 */ MCD_OPC_FilterValue, 26, 11, 0, // Skip to: 18358 -/* 18347 */ MCD_OPC_CheckField, 8, 8, 0, 226, 2, // Skip to: 19091 -/* 18353 */ MCD_OPC_Decode, 230, 2, 251, 2, // Opcode: ADB -/* 18358 */ MCD_OPC_FilterValue, 27, 11, 0, // Skip to: 18373 -/* 18362 */ MCD_OPC_CheckField, 8, 8, 0, 211, 2, // Skip to: 19091 -/* 18368 */ MCD_OPC_Decode, 191, 14, 251, 2, // Opcode: SDB -/* 18373 */ MCD_OPC_FilterValue, 28, 11, 0, // Skip to: 18388 -/* 18377 */ MCD_OPC_CheckField, 8, 8, 0, 196, 2, // Skip to: 19091 -/* 18383 */ MCD_OPC_Decode, 139, 13, 251, 2, // Opcode: MDB -/* 18388 */ MCD_OPC_FilterValue, 29, 11, 0, // Skip to: 18403 -/* 18392 */ MCD_OPC_CheckField, 8, 8, 0, 181, 2, // Skip to: 19091 -/* 18398 */ MCD_OPC_Decode, 189, 8, 251, 2, // Opcode: DDB -/* 18403 */ MCD_OPC_FilterValue, 30, 11, 0, // Skip to: 18418 -/* 18407 */ MCD_OPC_CheckField, 8, 4, 0, 166, 2, // Skip to: 19091 -/* 18413 */ MCD_OPC_Decode, 252, 12, 253, 2, // Opcode: MADB -/* 18418 */ MCD_OPC_FilterValue, 31, 11, 0, // Skip to: 18433 -/* 18422 */ MCD_OPC_CheckField, 8, 4, 0, 151, 2, // Skip to: 19091 -/* 18428 */ MCD_OPC_Decode, 172, 13, 253, 2, // Opcode: MSDB -/* 18433 */ MCD_OPC_FilterValue, 36, 11, 0, // Skip to: 18448 -/* 18437 */ MCD_OPC_CheckField, 8, 8, 0, 136, 2, // Skip to: 19091 -/* 18443 */ MCD_OPC_Decode, 147, 10, 246, 2, // Opcode: LDE -/* 18448 */ MCD_OPC_FilterValue, 37, 11, 0, // Skip to: 18463 -/* 18452 */ MCD_OPC_CheckField, 8, 8, 0, 121, 2, // Skip to: 19091 -/* 18458 */ MCD_OPC_Decode, 234, 12, 247, 2, // Opcode: LXD -/* 18463 */ MCD_OPC_FilterValue, 38, 11, 0, // Skip to: 18478 -/* 18467 */ MCD_OPC_CheckField, 8, 8, 0, 106, 2, // Skip to: 19091 -/* 18473 */ MCD_OPC_Decode, 239, 12, 247, 2, // Opcode: LXE -/* 18478 */ MCD_OPC_FilterValue, 46, 11, 0, // Skip to: 18493 -/* 18482 */ MCD_OPC_CheckField, 8, 4, 0, 91, 2, // Skip to: 19091 -/* 18488 */ MCD_OPC_Decode, 255, 12, 252, 2, // Opcode: MAE -/* 18493 */ MCD_OPC_FilterValue, 47, 11, 0, // Skip to: 18508 -/* 18497 */ MCD_OPC_CheckField, 8, 4, 0, 76, 2, // Skip to: 19091 -/* 18503 */ MCD_OPC_Decode, 175, 13, 252, 2, // Opcode: MSE -/* 18508 */ MCD_OPC_FilterValue, 52, 11, 0, // Skip to: 18523 -/* 18512 */ MCD_OPC_CheckField, 8, 8, 0, 61, 2, // Skip to: 19091 -/* 18518 */ MCD_OPC_Decode, 252, 14, 249, 2, // Opcode: SQE -/* 18523 */ MCD_OPC_FilterValue, 53, 11, 0, // Skip to: 18538 -/* 18527 */ MCD_OPC_CheckField, 8, 8, 0, 46, 2, // Skip to: 19091 -/* 18533 */ MCD_OPC_Decode, 248, 14, 246, 2, // Opcode: SQD -/* 18538 */ MCD_OPC_FilterValue, 55, 11, 0, // Skip to: 18553 -/* 18542 */ MCD_OPC_CheckField, 8, 8, 0, 31, 2, // Skip to: 19091 -/* 18548 */ MCD_OPC_Decode, 149, 13, 250, 2, // Opcode: MEE -/* 18553 */ MCD_OPC_FilterValue, 56, 11, 0, // Skip to: 18568 -/* 18557 */ MCD_OPC_CheckField, 8, 4, 0, 16, 2, // Skip to: 19091 -/* 18563 */ MCD_OPC_Decode, 134, 13, 253, 2, // Opcode: MAYL -/* 18568 */ MCD_OPC_FilterValue, 57, 11, 0, // Skip to: 18583 -/* 18572 */ MCD_OPC_CheckField, 8, 4, 0, 1, 2, // Skip to: 19091 -/* 18578 */ MCD_OPC_Decode, 223, 13, 254, 2, // Opcode: MYL -/* 18583 */ MCD_OPC_FilterValue, 58, 11, 0, // Skip to: 18598 -/* 18587 */ MCD_OPC_CheckField, 8, 4, 0, 242, 1, // Skip to: 19091 -/* 18593 */ MCD_OPC_Decode, 131, 13, 255, 2, // Opcode: MAY -/* 18598 */ MCD_OPC_FilterValue, 59, 11, 0, // Skip to: 18613 -/* 18602 */ MCD_OPC_CheckField, 8, 4, 0, 227, 1, // Skip to: 19091 -/* 18608 */ MCD_OPC_Decode, 220, 13, 128, 3, // Opcode: MY -/* 18613 */ MCD_OPC_FilterValue, 60, 11, 0, // Skip to: 18628 -/* 18617 */ MCD_OPC_CheckField, 8, 4, 0, 212, 1, // Skip to: 19091 -/* 18623 */ MCD_OPC_Decode, 132, 13, 253, 2, // Opcode: MAYH -/* 18628 */ MCD_OPC_FilterValue, 61, 11, 0, // Skip to: 18643 -/* 18632 */ MCD_OPC_CheckField, 8, 4, 0, 197, 1, // Skip to: 19091 -/* 18638 */ MCD_OPC_Decode, 221, 13, 254, 2, // Opcode: MYH -/* 18643 */ MCD_OPC_FilterValue, 62, 11, 0, // Skip to: 18658 -/* 18647 */ MCD_OPC_CheckField, 8, 4, 0, 182, 1, // Skip to: 19091 -/* 18653 */ MCD_OPC_Decode, 251, 12, 253, 2, // Opcode: MAD -/* 18658 */ MCD_OPC_FilterValue, 63, 11, 0, // Skip to: 18673 -/* 18662 */ MCD_OPC_CheckField, 8, 4, 0, 167, 1, // Skip to: 19091 -/* 18668 */ MCD_OPC_Decode, 171, 13, 253, 2, // Opcode: MSD -/* 18673 */ MCD_OPC_FilterValue, 64, 11, 0, // Skip to: 18688 -/* 18677 */ MCD_OPC_CheckField, 8, 4, 0, 152, 1, // Skip to: 19091 -/* 18683 */ MCD_OPC_Decode, 225, 14, 254, 2, // Opcode: SLDT -/* 18688 */ MCD_OPC_FilterValue, 65, 11, 0, // Skip to: 18703 -/* 18692 */ MCD_OPC_CheckField, 8, 4, 0, 137, 1, // Skip to: 19091 -/* 18698 */ MCD_OPC_Decode, 136, 15, 254, 2, // Opcode: SRDT -/* 18703 */ MCD_OPC_FilterValue, 72, 11, 0, // Skip to: 18718 -/* 18707 */ MCD_OPC_CheckField, 8, 4, 0, 122, 1, // Skip to: 19091 -/* 18713 */ MCD_OPC_Decode, 240, 14, 129, 3, // Opcode: SLXT -/* 18718 */ MCD_OPC_FilterValue, 73, 11, 0, // Skip to: 18733 -/* 18722 */ MCD_OPC_CheckField, 8, 4, 0, 107, 1, // Skip to: 19091 -/* 18728 */ MCD_OPC_Decode, 147, 15, 129, 3, // Opcode: SRXT -/* 18733 */ MCD_OPC_FilterValue, 80, 11, 0, // Skip to: 18748 -/* 18737 */ MCD_OPC_CheckField, 8, 8, 0, 92, 1, // Skip to: 19091 -/* 18743 */ MCD_OPC_Decode, 167, 16, 249, 2, // Opcode: TDCET -/* 18748 */ MCD_OPC_FilterValue, 81, 11, 0, // Skip to: 18763 -/* 18752 */ MCD_OPC_CheckField, 8, 8, 0, 77, 1, // Skip to: 19091 -/* 18758 */ MCD_OPC_Decode, 170, 16, 249, 2, // Opcode: TDGET -/* 18763 */ MCD_OPC_FilterValue, 84, 11, 0, // Skip to: 18778 -/* 18767 */ MCD_OPC_CheckField, 8, 8, 0, 62, 1, // Skip to: 19091 -/* 18773 */ MCD_OPC_Decode, 166, 16, 246, 2, // Opcode: TDCDT -/* 18778 */ MCD_OPC_FilterValue, 85, 11, 0, // Skip to: 18793 -/* 18782 */ MCD_OPC_CheckField, 8, 8, 0, 47, 1, // Skip to: 19091 -/* 18788 */ MCD_OPC_Decode, 169, 16, 246, 2, // Opcode: TDGDT -/* 18793 */ MCD_OPC_FilterValue, 88, 11, 0, // Skip to: 18808 -/* 18797 */ MCD_OPC_CheckField, 8, 8, 0, 32, 1, // Skip to: 19091 -/* 18803 */ MCD_OPC_Decode, 168, 16, 247, 2, // Opcode: TDCXT -/* 18808 */ MCD_OPC_FilterValue, 89, 11, 0, // Skip to: 18823 -/* 18812 */ MCD_OPC_CheckField, 8, 8, 0, 17, 1, // Skip to: 19091 -/* 18818 */ MCD_OPC_Decode, 171, 16, 247, 2, // Opcode: TDGXT -/* 18823 */ MCD_OPC_FilterValue, 100, 5, 0, // Skip to: 18832 -/* 18827 */ MCD_OPC_Decode, 170, 10, 130, 3, // Opcode: LEY -/* 18832 */ MCD_OPC_FilterValue, 101, 5, 0, // Skip to: 18841 -/* 18836 */ MCD_OPC_Decode, 160, 10, 131, 3, // Opcode: LDY -/* 18841 */ MCD_OPC_FilterValue, 102, 5, 0, // Skip to: 18850 -/* 18845 */ MCD_OPC_Decode, 175, 15, 130, 3, // Opcode: STEY -/* 18850 */ MCD_OPC_FilterValue, 103, 5, 0, // Skip to: 18859 -/* 18854 */ MCD_OPC_Decode, 173, 15, 131, 3, // Opcode: STDY -/* 18859 */ MCD_OPC_FilterValue, 168, 1, 9, 0, // Skip to: 18873 -/* 18864 */ MCD_OPC_CheckPredicate, 25, 223, 0, // Skip to: 19091 -/* 18868 */ MCD_OPC_Decode, 185, 8, 132, 3, // Opcode: CZDT -/* 18873 */ MCD_OPC_FilterValue, 169, 1, 9, 0, // Skip to: 18887 -/* 18878 */ MCD_OPC_CheckPredicate, 25, 209, 0, // Skip to: 19091 -/* 18882 */ MCD_OPC_Decode, 186, 8, 133, 3, // Opcode: CZXT -/* 18887 */ MCD_OPC_FilterValue, 170, 1, 9, 0, // Skip to: 18901 -/* 18892 */ MCD_OPC_CheckPredicate, 25, 195, 0, // Skip to: 19091 -/* 18896 */ MCD_OPC_Decode, 163, 4, 132, 3, // Opcode: CDZT -/* 18901 */ MCD_OPC_FilterValue, 171, 1, 9, 0, // Skip to: 18915 -/* 18906 */ MCD_OPC_CheckPredicate, 25, 181, 0, // Skip to: 19091 -/* 18910 */ MCD_OPC_Decode, 183, 8, 133, 3, // Opcode: CXZT -/* 18915 */ MCD_OPC_FilterValue, 172, 1, 9, 0, // Skip to: 18929 -/* 18920 */ MCD_OPC_CheckPredicate, 26, 167, 0, // Skip to: 19091 -/* 18924 */ MCD_OPC_Decode, 207, 7, 132, 3, // Opcode: CPDT -/* 18929 */ MCD_OPC_FilterValue, 173, 1, 9, 0, // Skip to: 18943 -/* 18934 */ MCD_OPC_CheckPredicate, 26, 153, 0, // Skip to: 19091 -/* 18938 */ MCD_OPC_Decode, 212, 7, 133, 3, // Opcode: CPXT -/* 18943 */ MCD_OPC_FilterValue, 174, 1, 9, 0, // Skip to: 18957 -/* 18948 */ MCD_OPC_CheckPredicate, 26, 139, 0, // Skip to: 19091 -/* 18952 */ MCD_OPC_Decode, 155, 4, 132, 3, // Opcode: CDPT -/* 18957 */ MCD_OPC_FilterValue, 175, 1, 129, 0, // Skip to: 19091 -/* 18962 */ MCD_OPC_CheckPredicate, 26, 125, 0, // Skip to: 19091 -/* 18966 */ MCD_OPC_Decode, 178, 8, 133, 3, // Opcode: CXPT -/* 18971 */ MCD_OPC_FilterValue, 238, 1, 5, 0, // Skip to: 18981 -/* 18976 */ MCD_OPC_Decode, 145, 14, 134, 3, // Opcode: PLO -/* 18981 */ MCD_OPC_FilterValue, 239, 1, 5, 0, // Skip to: 18991 -/* 18986 */ MCD_OPC_Decode, 226, 10, 135, 3, // Opcode: LMD -/* 18991 */ MCD_OPC_FilterValue, 240, 1, 5, 0, // Skip to: 19001 -/* 18996 */ MCD_OPC_Decode, 144, 15, 136, 3, // Opcode: SRP -/* 19001 */ MCD_OPC_FilterValue, 241, 1, 5, 0, // Skip to: 19011 -/* 19006 */ MCD_OPC_Decode, 208, 13, 137, 3, // Opcode: MVO -/* 19011 */ MCD_OPC_FilterValue, 242, 1, 5, 0, // Skip to: 19021 -/* 19016 */ MCD_OPC_Decode, 132, 14, 137, 3, // Opcode: PACK -/* 19021 */ MCD_OPC_FilterValue, 243, 1, 5, 0, // Skip to: 19031 -/* 19026 */ MCD_OPC_Decode, 206, 16, 137, 3, // Opcode: UNPK -/* 19031 */ MCD_OPC_FilterValue, 248, 1, 5, 0, // Skip to: 19041 -/* 19036 */ MCD_OPC_Decode, 239, 21, 137, 3, // Opcode: ZAP -/* 19041 */ MCD_OPC_FilterValue, 249, 1, 5, 0, // Skip to: 19051 -/* 19046 */ MCD_OPC_Decode, 206, 7, 137, 3, // Opcode: CP -/* 19051 */ MCD_OPC_FilterValue, 250, 1, 5, 0, // Skip to: 19061 -/* 19056 */ MCD_OPC_Decode, 152, 3, 137, 3, // Opcode: AP -/* 19061 */ MCD_OPC_FilterValue, 251, 1, 5, 0, // Skip to: 19071 -/* 19066 */ MCD_OPC_Decode, 242, 14, 137, 3, // Opcode: SP -/* 19071 */ MCD_OPC_FilterValue, 252, 1, 5, 0, // Skip to: 19081 -/* 19076 */ MCD_OPC_Decode, 166, 13, 137, 3, // Opcode: MP -/* 19081 */ MCD_OPC_FilterValue, 253, 1, 5, 0, // Skip to: 19091 -/* 19086 */ MCD_OPC_Decode, 205, 8, 137, 3, // Opcode: DP -/* 19091 */ MCD_OPC_Fail, +/* 3 */ MCD_OPC_FilterValue, 192, 1, 40, 1, 0, // Skip to: 305 +/* 9 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 12 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 22 +/* 17 */ MCD_OPC_Decode, 139, 11, 174, 1, // Opcode: LARL +/* 22 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 32 +/* 27 */ MCD_OPC_Decode, 199, 11, 175, 1, // Opcode: LGFI +/* 32 */ MCD_OPC_FilterValue, 4, 158, 0, 0, // Skip to: 195 +/* 37 */ MCD_OPC_ExtractField, 36, 4, // Inst{39-36} ... +/* 40 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 50 +/* 45 */ MCD_OPC_Decode, 233, 10, 176, 1, // Opcode: JGAsmO +/* 50 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 60 +/* 55 */ MCD_OPC_Decode, 217, 10, 176, 1, // Opcode: JGAsmH +/* 60 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 70 +/* 65 */ MCD_OPC_Decode, 227, 10, 176, 1, // Opcode: JGAsmNLE +/* 70 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 80 +/* 75 */ MCD_OPC_Decode, 219, 10, 176, 1, // Opcode: JGAsmL +/* 80 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 90 +/* 85 */ MCD_OPC_Decode, 225, 10, 176, 1, // Opcode: JGAsmNHE +/* 90 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 100 +/* 95 */ MCD_OPC_Decode, 221, 10, 176, 1, // Opcode: JGAsmLH +/* 100 */ MCD_OPC_FilterValue, 7, 5, 0, 0, // Skip to: 110 +/* 105 */ MCD_OPC_Decode, 223, 10, 176, 1, // Opcode: JGAsmNE +/* 110 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 120 +/* 115 */ MCD_OPC_Decode, 216, 10, 176, 1, // Opcode: JGAsmE +/* 120 */ MCD_OPC_FilterValue, 9, 5, 0, 0, // Skip to: 130 +/* 125 */ MCD_OPC_Decode, 228, 10, 176, 1, // Opcode: JGAsmNLH +/* 130 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 140 +/* 135 */ MCD_OPC_Decode, 218, 10, 176, 1, // Opcode: JGAsmHE +/* 140 */ MCD_OPC_FilterValue, 11, 5, 0, 0, // Skip to: 150 +/* 145 */ MCD_OPC_Decode, 226, 10, 176, 1, // Opcode: JGAsmNL +/* 150 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 160 +/* 155 */ MCD_OPC_Decode, 220, 10, 176, 1, // Opcode: JGAsmLE +/* 160 */ MCD_OPC_FilterValue, 13, 5, 0, 0, // Skip to: 170 +/* 165 */ MCD_OPC_Decode, 224, 10, 176, 1, // Opcode: JGAsmNH +/* 170 */ MCD_OPC_FilterValue, 14, 5, 0, 0, // Skip to: 180 +/* 175 */ MCD_OPC_Decode, 230, 10, 176, 1, // Opcode: JGAsmNO +/* 180 */ MCD_OPC_FilterValue, 15, 5, 0, 0, // Skip to: 190 +/* 185 */ MCD_OPC_Decode, 215, 10, 176, 1, // Opcode: JG +/* 190 */ MCD_OPC_Decode, 132, 5, 177, 1, // Opcode: BRCLAsm +/* 195 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 205 +/* 200 */ MCD_OPC_Decode, 236, 4, 178, 1, // Opcode: BRASL +/* 205 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 215 +/* 210 */ MCD_OPC_Decode, 153, 24, 179, 1, // Opcode: XIHF +/* 215 */ MCD_OPC_FilterValue, 7, 5, 0, 0, // Skip to: 225 +/* 220 */ MCD_OPC_Decode, 154, 24, 180, 1, // Opcode: XILF +/* 225 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 235 +/* 230 */ MCD_OPC_Decode, 149, 10, 181, 1, // Opcode: IIHF +/* 235 */ MCD_OPC_FilterValue, 9, 5, 0, 0, // Skip to: 245 +/* 240 */ MCD_OPC_Decode, 152, 10, 182, 1, // Opcode: IILF +/* 245 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 255 +/* 250 */ MCD_OPC_Decode, 252, 14, 179, 1, // Opcode: NIHF +/* 255 */ MCD_OPC_FilterValue, 11, 5, 0, 0, // Skip to: 265 +/* 260 */ MCD_OPC_Decode, 255, 14, 180, 1, // Opcode: NILF +/* 265 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 275 +/* 270 */ MCD_OPC_Decode, 151, 15, 179, 1, // Opcode: OIHF +/* 275 */ MCD_OPC_FilterValue, 13, 5, 0, 0, // Skip to: 285 +/* 280 */ MCD_OPC_Decode, 154, 15, 180, 1, // Opcode: OILF +/* 285 */ MCD_OPC_FilterValue, 14, 5, 0, 0, // Skip to: 295 +/* 290 */ MCD_OPC_Decode, 236, 11, 183, 1, // Opcode: LLIHF +/* 295 */ MCD_OPC_FilterValue, 15, 160, 89, 0, // Skip to: 23244 +/* 300 */ MCD_OPC_Decode, 239, 11, 183, 1, // Opcode: LLILF +/* 305 */ MCD_OPC_FilterValue, 194, 1, 123, 0, 0, // Skip to: 434 +/* 311 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 314 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 324 +/* 319 */ MCD_OPC_Decode, 199, 14, 184, 1, // Opcode: MSGFI +/* 324 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 334 +/* 329 */ MCD_OPC_Decode, 195, 14, 185, 1, // Opcode: MSFI +/* 334 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 344 +/* 339 */ MCD_OPC_Decode, 200, 16, 186, 1, // Opcode: SLGFI +/* 344 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 354 +/* 349 */ MCD_OPC_Decode, 197, 16, 180, 1, // Opcode: SLFI +/* 354 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 364 +/* 359 */ MCD_OPC_Decode, 251, 3, 184, 1, // Opcode: AGFI +/* 364 */ MCD_OPC_FilterValue, 9, 5, 0, 0, // Skip to: 374 +/* 369 */ MCD_OPC_Decode, 248, 3, 185, 1, // Opcode: AFI +/* 374 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 384 +/* 379 */ MCD_OPC_Decode, 146, 4, 186, 1, // Opcode: ALGFI +/* 384 */ MCD_OPC_FilterValue, 11, 5, 0, 0, // Skip to: 394 +/* 389 */ MCD_OPC_Decode, 143, 4, 180, 1, // Opcode: ALFI +/* 394 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 404 +/* 399 */ MCD_OPC_Decode, 210, 5, 175, 1, // Opcode: CGFI +/* 404 */ MCD_OPC_FilterValue, 13, 5, 0, 0, // Skip to: 414 +/* 409 */ MCD_OPC_Decode, 195, 5, 187, 1, // Opcode: CFI +/* 414 */ MCD_OPC_FilterValue, 14, 5, 0, 0, // Skip to: 424 +/* 419 */ MCD_OPC_Decode, 136, 7, 183, 1, // Opcode: CLGFI +/* 424 */ MCD_OPC_FilterValue, 15, 31, 89, 0, // Skip to: 23244 +/* 429 */ MCD_OPC_Decode, 242, 6, 182, 1, // Opcode: CLFI +/* 434 */ MCD_OPC_FilterValue, 196, 1, 113, 0, 0, // Skip to: 553 +/* 440 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 443 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 453 +/* 448 */ MCD_OPC_Decode, 235, 11, 188, 1, // Opcode: LLHRL +/* 453 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 463 +/* 458 */ MCD_OPC_Decode, 206, 11, 174, 1, // Opcode: LGHRL +/* 463 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 473 +/* 468 */ MCD_OPC_Decode, 214, 11, 188, 1, // Opcode: LHRL +/* 473 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 483 +/* 478 */ MCD_OPC_Decode, 228, 11, 174, 1, // Opcode: LLGHRL +/* 483 */ MCD_OPC_FilterValue, 7, 5, 0, 0, // Skip to: 493 +/* 488 */ MCD_OPC_Decode, 158, 17, 188, 1, // Opcode: STHRL +/* 493 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 503 +/* 498 */ MCD_OPC_Decode, 208, 11, 174, 1, // Opcode: LGRL +/* 503 */ MCD_OPC_FilterValue, 11, 5, 0, 0, // Skip to: 513 +/* 508 */ MCD_OPC_Decode, 154, 17, 174, 1, // Opcode: STGRL +/* 513 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 523 +/* 518 */ MCD_OPC_Decode, 201, 11, 174, 1, // Opcode: LGFRL +/* 523 */ MCD_OPC_FilterValue, 13, 5, 0, 0, // Skip to: 533 +/* 528 */ MCD_OPC_Decode, 227, 13, 188, 1, // Opcode: LRL +/* 533 */ MCD_OPC_FilterValue, 14, 5, 0, 0, // Skip to: 543 +/* 538 */ MCD_OPC_Decode, 224, 11, 174, 1, // Opcode: LLGFRL +/* 543 */ MCD_OPC_FilterValue, 15, 168, 88, 0, // Skip to: 23244 +/* 548 */ MCD_OPC_Decode, 237, 17, 188, 1, // Opcode: STRL +/* 553 */ MCD_OPC_FilterValue, 197, 1, 10, 0, 0, // Skip to: 569 +/* 559 */ MCD_OPC_CheckPredicate, 5, 152, 88, 0, // Skip to: 23244 +/* 564 */ MCD_OPC_Decode, 233, 4, 189, 1, // Opcode: BPRP +/* 569 */ MCD_OPC_FilterValue, 198, 1, 123, 0, 0, // Skip to: 698 +/* 575 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 578 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 588 +/* 583 */ MCD_OPC_Decode, 249, 9, 190, 1, // Opcode: EXRL +/* 588 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 598 +/* 593 */ MCD_OPC_Decode, 167, 15, 191, 1, // Opcode: PFDRL +/* 598 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 608 +/* 603 */ MCD_OPC_Decode, 215, 5, 174, 1, // Opcode: CGHRL +/* 608 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 618 +/* 613 */ MCD_OPC_Decode, 186, 6, 188, 1, // Opcode: CHRL +/* 618 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 628 +/* 623 */ MCD_OPC_Decode, 139, 7, 174, 1, // Opcode: CLGHRL +/* 628 */ MCD_OPC_FilterValue, 7, 5, 0, 0, // Skip to: 638 +/* 633 */ MCD_OPC_Decode, 247, 7, 188, 1, // Opcode: CLHRL +/* 638 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 648 +/* 643 */ MCD_OPC_Decode, 160, 6, 174, 1, // Opcode: CGRL +/* 648 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 658 +/* 653 */ MCD_OPC_Decode, 212, 7, 174, 1, // Opcode: CLGRL +/* 658 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 668 +/* 663 */ MCD_OPC_Decode, 212, 5, 174, 1, // Opcode: CGFRL +/* 668 */ MCD_OPC_FilterValue, 13, 5, 0, 0, // Skip to: 678 +/* 673 */ MCD_OPC_Decode, 254, 8, 188, 1, // Opcode: CRL +/* 678 */ MCD_OPC_FilterValue, 14, 5, 0, 0, // Skip to: 688 +/* 683 */ MCD_OPC_Decode, 138, 7, 174, 1, // Opcode: CLGFRL +/* 688 */ MCD_OPC_FilterValue, 15, 23, 88, 0, // Skip to: 23244 +/* 693 */ MCD_OPC_Decode, 183, 8, 188, 1, // Opcode: CLRL +/* 698 */ MCD_OPC_FilterValue, 199, 1, 17, 0, 0, // Skip to: 721 +/* 704 */ MCD_OPC_CheckPredicate, 5, 7, 88, 0, // Skip to: 23244 +/* 709 */ MCD_OPC_CheckField, 32, 4, 0, 0, 88, 0, // Skip to: 23244 +/* 716 */ MCD_OPC_Decode, 232, 4, 192, 1, // Opcode: BPP +/* 721 */ MCD_OPC_FilterValue, 200, 1, 63, 0, 0, // Skip to: 790 +/* 727 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 730 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 740 +/* 735 */ MCD_OPC_Decode, 214, 14, 193, 1, // Opcode: MVCOS +/* 740 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 750 +/* 745 */ MCD_OPC_Decode, 229, 9, 193, 1, // Opcode: ECTG +/* 750 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 760 +/* 755 */ MCD_OPC_Decode, 147, 9, 193, 1, // Opcode: CSST +/* 760 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 775 +/* 765 */ MCD_OPC_CheckPredicate, 25, 202, 87, 0, // Skip to: 23244 +/* 770 */ MCD_OPC_Decode, 202, 13, 194, 1, // Opcode: LPD +/* 775 */ MCD_OPC_FilterValue, 5, 192, 87, 0, // Skip to: 23244 +/* 780 */ MCD_OPC_CheckPredicate, 25, 187, 87, 0, // Skip to: 23244 +/* 785 */ MCD_OPC_Decode, 206, 13, 194, 1, // Opcode: LPDG +/* 790 */ MCD_OPC_FilterValue, 204, 1, 93, 0, 0, // Skip to: 889 +/* 796 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 799 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 814 +/* 804 */ MCD_OPC_CheckPredicate, 19, 163, 87, 0, // Skip to: 23244 +/* 809 */ MCD_OPC_Decode, 135, 5, 195, 1, // Opcode: BRCTH +/* 814 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 829 +/* 819 */ MCD_OPC_CheckPredicate, 19, 148, 87, 0, // Skip to: 23244 +/* 824 */ MCD_OPC_Decode, 137, 4, 196, 1, // Opcode: AIH +/* 829 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 844 +/* 834 */ MCD_OPC_CheckPredicate, 19, 133, 87, 0, // Skip to: 23244 +/* 839 */ MCD_OPC_Decode, 158, 4, 196, 1, // Opcode: ALSIH +/* 844 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 859 +/* 849 */ MCD_OPC_CheckPredicate, 19, 118, 87, 0, // Skip to: 23244 +/* 854 */ MCD_OPC_Decode, 159, 4, 196, 1, // Opcode: ALSIHN +/* 859 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 874 +/* 864 */ MCD_OPC_CheckPredicate, 19, 103, 87, 0, // Skip to: 23244 +/* 869 */ MCD_OPC_Decode, 203, 6, 197, 1, // Opcode: CIH +/* 874 */ MCD_OPC_FilterValue, 15, 93, 87, 0, // Skip to: 23244 +/* 879 */ MCD_OPC_CheckPredicate, 19, 88, 87, 0, // Skip to: 23244 +/* 884 */ MCD_OPC_Decode, 135, 8, 181, 1, // Opcode: CLIH +/* 889 */ MCD_OPC_FilterValue, 208, 1, 5, 0, 0, // Skip to: 900 +/* 895 */ MCD_OPC_Decode, 172, 18, 198, 1, // Opcode: TRTR +/* 900 */ MCD_OPC_FilterValue, 209, 1, 5, 0, 0, // Skip to: 911 +/* 906 */ MCD_OPC_Decode, 224, 14, 198, 1, // Opcode: MVN +/* 911 */ MCD_OPC_FilterValue, 210, 1, 5, 0, 0, // Skip to: 922 +/* 917 */ MCD_OPC_Decode, 207, 14, 198, 1, // Opcode: MVC +/* 922 */ MCD_OPC_FilterValue, 211, 1, 5, 0, 0, // Skip to: 933 +/* 928 */ MCD_OPC_Decode, 228, 14, 198, 1, // Opcode: MVZ +/* 933 */ MCD_OPC_FilterValue, 212, 1, 5, 0, 0, // Skip to: 944 +/* 939 */ MCD_OPC_Decode, 244, 14, 198, 1, // Opcode: NC +/* 944 */ MCD_OPC_FilterValue, 213, 1, 5, 0, 0, // Skip to: 955 +/* 950 */ MCD_OPC_Decode, 234, 6, 198, 1, // Opcode: CLC +/* 955 */ MCD_OPC_FilterValue, 214, 1, 5, 0, 0, // Skip to: 966 +/* 961 */ MCD_OPC_Decode, 144, 15, 198, 1, // Opcode: OC +/* 966 */ MCD_OPC_FilterValue, 215, 1, 5, 0, 0, // Skip to: 977 +/* 972 */ MCD_OPC_Decode, 148, 24, 198, 1, // Opcode: XC +/* 977 */ MCD_OPC_FilterValue, 217, 1, 5, 0, 0, // Skip to: 988 +/* 983 */ MCD_OPC_Decode, 210, 14, 199, 1, // Opcode: MVCK +/* 988 */ MCD_OPC_FilterValue, 218, 1, 5, 0, 0, // Skip to: 999 +/* 994 */ MCD_OPC_Decode, 215, 14, 199, 1, // Opcode: MVCP +/* 999 */ MCD_OPC_FilterValue, 219, 1, 5, 0, 0, // Skip to: 1010 +/* 1005 */ MCD_OPC_Decode, 217, 14, 199, 1, // Opcode: MVCS +/* 1010 */ MCD_OPC_FilterValue, 220, 1, 5, 0, 0, // Skip to: 1021 +/* 1016 */ MCD_OPC_Decode, 157, 18, 198, 1, // Opcode: TR +/* 1021 */ MCD_OPC_FilterValue, 221, 1, 5, 0, 0, // Skip to: 1032 +/* 1027 */ MCD_OPC_Decode, 167, 18, 198, 1, // Opcode: TRT +/* 1032 */ MCD_OPC_FilterValue, 222, 1, 5, 0, 0, // Skip to: 1043 +/* 1038 */ MCD_OPC_Decode, 230, 9, 198, 1, // Opcode: ED +/* 1043 */ MCD_OPC_FilterValue, 223, 1, 5, 0, 0, // Skip to: 1054 +/* 1049 */ MCD_OPC_Decode, 231, 9, 198, 1, // Opcode: EDMK +/* 1054 */ MCD_OPC_FilterValue, 225, 1, 5, 0, 0, // Skip to: 1065 +/* 1060 */ MCD_OPC_Decode, 173, 15, 200, 1, // Opcode: PKU +/* 1065 */ MCD_OPC_FilterValue, 226, 1, 5, 0, 0, // Skip to: 1076 +/* 1071 */ MCD_OPC_Decode, 181, 18, 198, 1, // Opcode: UNPKU +/* 1076 */ MCD_OPC_FilterValue, 227, 1, 255, 5, 0, // Skip to: 2617 +/* 1082 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 1085 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 1095 +/* 1090 */ MCD_OPC_Decode, 240, 13, 201, 1, // Opcode: LTG +/* 1095 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 1105 +/* 1100 */ MCD_OPC_Decode, 223, 13, 201, 1, // Opcode: LRAG +/* 1105 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 1115 +/* 1110 */ MCD_OPC_Decode, 193, 11, 201, 1, // Opcode: LG +/* 1115 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 1125 +/* 1120 */ MCD_OPC_Decode, 169, 9, 202, 1, // Opcode: CVBY +/* 1125 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 1135 +/* 1130 */ MCD_OPC_Decode, 249, 3, 203, 1, // Opcode: AG +/* 1135 */ MCD_OPC_FilterValue, 9, 5, 0, 0, // Skip to: 1145 +/* 1140 */ MCD_OPC_Decode, 173, 16, 203, 1, // Opcode: SG +/* 1145 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 1155 +/* 1150 */ MCD_OPC_Decode, 144, 4, 203, 1, // Opcode: ALG +/* 1155 */ MCD_OPC_FilterValue, 11, 5, 0, 0, // Skip to: 1165 +/* 1160 */ MCD_OPC_Decode, 198, 16, 203, 1, // Opcode: SLG +/* 1165 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 1175 +/* 1170 */ MCD_OPC_Decode, 196, 14, 203, 1, // Opcode: MSG +/* 1175 */ MCD_OPC_FilterValue, 13, 5, 0, 0, // Skip to: 1185 +/* 1180 */ MCD_OPC_Decode, 217, 9, 204, 1, // Opcode: DSG +/* 1185 */ MCD_OPC_FilterValue, 14, 5, 0, 0, // Skip to: 1195 +/* 1190 */ MCD_OPC_Decode, 168, 9, 203, 1, // Opcode: CVBG +/* 1195 */ MCD_OPC_FilterValue, 15, 5, 0, 0, // Skip to: 1205 +/* 1200 */ MCD_OPC_Decode, 229, 13, 201, 1, // Opcode: LRVG +/* 1205 */ MCD_OPC_FilterValue, 18, 5, 0, 0, // Skip to: 1215 +/* 1210 */ MCD_OPC_Decode, 234, 13, 205, 1, // Opcode: LT +/* 1215 */ MCD_OPC_FilterValue, 19, 5, 0, 0, // Skip to: 1225 +/* 1220 */ MCD_OPC_Decode, 224, 13, 201, 1, // Opcode: LRAY +/* 1225 */ MCD_OPC_FilterValue, 20, 5, 0, 0, // Skip to: 1235 +/* 1230 */ MCD_OPC_Decode, 198, 11, 201, 1, // Opcode: LGF +/* 1235 */ MCD_OPC_FilterValue, 21, 5, 0, 0, // Skip to: 1245 +/* 1240 */ MCD_OPC_Decode, 203, 11, 201, 1, // Opcode: LGH +/* 1245 */ MCD_OPC_FilterValue, 22, 5, 0, 0, // Skip to: 1255 +/* 1250 */ MCD_OPC_Decode, 221, 11, 201, 1, // Opcode: LLGF +/* 1255 */ MCD_OPC_FilterValue, 23, 5, 0, 0, // Skip to: 1265 +/* 1260 */ MCD_OPC_Decode, 229, 11, 201, 1, // Opcode: LLGT +/* 1265 */ MCD_OPC_FilterValue, 24, 5, 0, 0, // Skip to: 1275 +/* 1270 */ MCD_OPC_Decode, 250, 3, 203, 1, // Opcode: AGF +/* 1275 */ MCD_OPC_FilterValue, 25, 5, 0, 0, // Skip to: 1285 +/* 1280 */ MCD_OPC_Decode, 174, 16, 203, 1, // Opcode: SGF +/* 1285 */ MCD_OPC_FilterValue, 26, 5, 0, 0, // Skip to: 1295 +/* 1290 */ MCD_OPC_Decode, 145, 4, 203, 1, // Opcode: ALGF +/* 1295 */ MCD_OPC_FilterValue, 27, 5, 0, 0, // Skip to: 1305 +/* 1300 */ MCD_OPC_Decode, 199, 16, 203, 1, // Opcode: SLGF +/* 1305 */ MCD_OPC_FilterValue, 28, 5, 0, 0, // Skip to: 1315 +/* 1310 */ MCD_OPC_Decode, 198, 14, 203, 1, // Opcode: MSGF +/* 1315 */ MCD_OPC_FilterValue, 29, 5, 0, 0, // Skip to: 1325 +/* 1320 */ MCD_OPC_Decode, 218, 9, 204, 1, // Opcode: DSGF +/* 1325 */ MCD_OPC_FilterValue, 30, 5, 0, 0, // Skip to: 1335 +/* 1330 */ MCD_OPC_Decode, 228, 13, 205, 1, // Opcode: LRV +/* 1335 */ MCD_OPC_FilterValue, 31, 5, 0, 0, // Skip to: 1345 +/* 1340 */ MCD_OPC_Decode, 231, 13, 205, 1, // Opcode: LRVH +/* 1345 */ MCD_OPC_FilterValue, 32, 5, 0, 0, // Skip to: 1355 +/* 1350 */ MCD_OPC_Decode, 200, 5, 201, 1, // Opcode: CG +/* 1355 */ MCD_OPC_FilterValue, 33, 5, 0, 0, // Skip to: 1365 +/* 1360 */ MCD_OPC_Decode, 131, 7, 201, 1, // Opcode: CLG +/* 1365 */ MCD_OPC_FilterValue, 36, 5, 0, 0, // Skip to: 1375 +/* 1370 */ MCD_OPC_Decode, 153, 17, 201, 1, // Opcode: STG +/* 1375 */ MCD_OPC_FilterValue, 37, 10, 0, 0, // Skip to: 1390 +/* 1380 */ MCD_OPC_CheckPredicate, 4, 99, 85, 0, // Skip to: 23244 +/* 1385 */ MCD_OPC_Decode, 139, 15, 201, 1, // Opcode: NTSTG +/* 1390 */ MCD_OPC_FilterValue, 38, 5, 0, 0, // Skip to: 1400 +/* 1395 */ MCD_OPC_Decode, 172, 9, 205, 1, // Opcode: CVDY +/* 1400 */ MCD_OPC_FilterValue, 42, 10, 0, 0, // Skip to: 1415 +/* 1405 */ MCD_OPC_CheckPredicate, 26, 74, 85, 0, // Skip to: 23244 +/* 1410 */ MCD_OPC_Decode, 136, 14, 201, 1, // Opcode: LZRG +/* 1415 */ MCD_OPC_FilterValue, 46, 5, 0, 0, // Skip to: 1425 +/* 1420 */ MCD_OPC_Decode, 171, 9, 201, 1, // Opcode: CVDG +/* 1425 */ MCD_OPC_FilterValue, 47, 5, 0, 0, // Skip to: 1435 +/* 1430 */ MCD_OPC_Decode, 239, 17, 201, 1, // Opcode: STRVG +/* 1435 */ MCD_OPC_FilterValue, 48, 5, 0, 0, // Skip to: 1445 +/* 1440 */ MCD_OPC_Decode, 209, 5, 201, 1, // Opcode: CGF +/* 1445 */ MCD_OPC_FilterValue, 49, 5, 0, 0, // Skip to: 1455 +/* 1450 */ MCD_OPC_Decode, 135, 7, 201, 1, // Opcode: CLGF +/* 1455 */ MCD_OPC_FilterValue, 50, 5, 0, 0, // Skip to: 1465 +/* 1460 */ MCD_OPC_Decode, 241, 13, 201, 1, // Opcode: LTGF +/* 1465 */ MCD_OPC_FilterValue, 52, 5, 0, 0, // Skip to: 1475 +/* 1470 */ MCD_OPC_Decode, 213, 5, 201, 1, // Opcode: CGH +/* 1475 */ MCD_OPC_FilterValue, 54, 5, 0, 0, // Skip to: 1485 +/* 1480 */ MCD_OPC_Decode, 166, 15, 206, 1, // Opcode: PFD +/* 1485 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 1500 +/* 1490 */ MCD_OPC_CheckPredicate, 24, 245, 84, 0, // Skip to: 23244 +/* 1495 */ MCD_OPC_Decode, 253, 3, 203, 1, // Opcode: AGH +/* 1500 */ MCD_OPC_FilterValue, 57, 10, 0, 0, // Skip to: 1515 +/* 1505 */ MCD_OPC_CheckPredicate, 24, 230, 84, 0, // Skip to: 23244 +/* 1510 */ MCD_OPC_Decode, 176, 16, 203, 1, // Opcode: SGH +/* 1515 */ MCD_OPC_FilterValue, 58, 10, 0, 0, // Skip to: 1530 +/* 1520 */ MCD_OPC_CheckPredicate, 26, 215, 84, 0, // Skip to: 23244 +/* 1525 */ MCD_OPC_Decode, 242, 11, 201, 1, // Opcode: LLZRGF +/* 1530 */ MCD_OPC_FilterValue, 59, 10, 0, 0, // Skip to: 1545 +/* 1535 */ MCD_OPC_CheckPredicate, 26, 200, 84, 0, // Skip to: 23244 +/* 1540 */ MCD_OPC_Decode, 135, 14, 205, 1, // Opcode: LZRF +/* 1545 */ MCD_OPC_FilterValue, 60, 10, 0, 0, // Skip to: 1560 +/* 1550 */ MCD_OPC_CheckPredicate, 24, 185, 84, 0, // Skip to: 23244 +/* 1555 */ MCD_OPC_Decode, 172, 14, 203, 1, // Opcode: MGH +/* 1560 */ MCD_OPC_FilterValue, 62, 5, 0, 0, // Skip to: 1570 +/* 1565 */ MCD_OPC_Decode, 238, 17, 205, 1, // Opcode: STRV +/* 1570 */ MCD_OPC_FilterValue, 63, 5, 0, 0, // Skip to: 1580 +/* 1575 */ MCD_OPC_Decode, 240, 17, 205, 1, // Opcode: STRVH +/* 1580 */ MCD_OPC_FilterValue, 70, 5, 0, 0, // Skip to: 1590 +/* 1585 */ MCD_OPC_Decode, 206, 4, 203, 1, // Opcode: BCTG +/* 1590 */ MCD_OPC_FilterValue, 71, 238, 0, 0, // Skip to: 1833 +/* 1595 */ MCD_OPC_ExtractField, 36, 4, // Inst{39-36} ... +/* 1598 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1613 +/* 1603 */ MCD_OPC_CheckPredicate, 24, 215, 0, 0, // Skip to: 1823 +/* 1608 */ MCD_OPC_Decode, 227, 4, 207, 1, // Opcode: BIAsmO +/* 1613 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1628 +/* 1618 */ MCD_OPC_CheckPredicate, 24, 200, 0, 0, // Skip to: 1823 +/* 1623 */ MCD_OPC_Decode, 211, 4, 207, 1, // Opcode: BIAsmH +/* 1628 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1643 +/* 1633 */ MCD_OPC_CheckPredicate, 24, 185, 0, 0, // Skip to: 1823 +/* 1638 */ MCD_OPC_Decode, 221, 4, 207, 1, // Opcode: BIAsmNLE +/* 1643 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 1658 +/* 1648 */ MCD_OPC_CheckPredicate, 24, 170, 0, 0, // Skip to: 1823 +/* 1653 */ MCD_OPC_Decode, 213, 4, 207, 1, // Opcode: BIAsmL +/* 1658 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1673 +/* 1663 */ MCD_OPC_CheckPredicate, 24, 155, 0, 0, // Skip to: 1823 +/* 1668 */ MCD_OPC_Decode, 219, 4, 207, 1, // Opcode: BIAsmNHE +/* 1673 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 1688 +/* 1678 */ MCD_OPC_CheckPredicate, 24, 140, 0, 0, // Skip to: 1823 +/* 1683 */ MCD_OPC_Decode, 215, 4, 207, 1, // Opcode: BIAsmLH +/* 1688 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 1703 +/* 1693 */ MCD_OPC_CheckPredicate, 24, 125, 0, 0, // Skip to: 1823 +/* 1698 */ MCD_OPC_Decode, 217, 4, 207, 1, // Opcode: BIAsmNE +/* 1703 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 1718 +/* 1708 */ MCD_OPC_CheckPredicate, 24, 110, 0, 0, // Skip to: 1823 +/* 1713 */ MCD_OPC_Decode, 210, 4, 207, 1, // Opcode: BIAsmE +/* 1718 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 1733 +/* 1723 */ MCD_OPC_CheckPredicate, 24, 95, 0, 0, // Skip to: 1823 +/* 1728 */ MCD_OPC_Decode, 222, 4, 207, 1, // Opcode: BIAsmNLH +/* 1733 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1748 +/* 1738 */ MCD_OPC_CheckPredicate, 24, 80, 0, 0, // Skip to: 1823 +/* 1743 */ MCD_OPC_Decode, 212, 4, 207, 1, // Opcode: BIAsmHE +/* 1748 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1763 +/* 1753 */ MCD_OPC_CheckPredicate, 24, 65, 0, 0, // Skip to: 1823 +/* 1758 */ MCD_OPC_Decode, 220, 4, 207, 1, // Opcode: BIAsmNL +/* 1763 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 1778 +/* 1768 */ MCD_OPC_CheckPredicate, 24, 50, 0, 0, // Skip to: 1823 +/* 1773 */ MCD_OPC_Decode, 214, 4, 207, 1, // Opcode: BIAsmLE +/* 1778 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1793 +/* 1783 */ MCD_OPC_CheckPredicate, 24, 35, 0, 0, // Skip to: 1823 +/* 1788 */ MCD_OPC_Decode, 218, 4, 207, 1, // Opcode: BIAsmNH +/* 1793 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1808 +/* 1798 */ MCD_OPC_CheckPredicate, 24, 20, 0, 0, // Skip to: 1823 +/* 1803 */ MCD_OPC_Decode, 224, 4, 207, 1, // Opcode: BIAsmNO +/* 1808 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1823 +/* 1813 */ MCD_OPC_CheckPredicate, 24, 5, 0, 0, // Skip to: 1823 +/* 1818 */ MCD_OPC_Decode, 209, 4, 207, 1, // Opcode: BI +/* 1823 */ MCD_OPC_CheckPredicate, 24, 168, 83, 0, // Skip to: 23244 +/* 1828 */ MCD_OPC_Decode, 231, 4, 206, 1, // Opcode: BICAsm +/* 1833 */ MCD_OPC_FilterValue, 72, 10, 0, 0, // Skip to: 1848 +/* 1838 */ MCD_OPC_CheckPredicate, 27, 153, 83, 0, // Skip to: 23244 +/* 1843 */ MCD_OPC_Decode, 225, 11, 201, 1, // Opcode: LLGFSG +/* 1848 */ MCD_OPC_FilterValue, 73, 10, 0, 0, // Skip to: 1863 +/* 1853 */ MCD_OPC_CheckPredicate, 27, 138, 83, 0, // Skip to: 23244 +/* 1858 */ MCD_OPC_Decode, 155, 17, 201, 1, // Opcode: STGSC +/* 1863 */ MCD_OPC_FilterValue, 76, 10, 0, 0, // Skip to: 1878 +/* 1868 */ MCD_OPC_CheckPredicate, 27, 123, 83, 0, // Skip to: 23244 +/* 1873 */ MCD_OPC_Decode, 202, 11, 201, 1, // Opcode: LGG +/* 1878 */ MCD_OPC_FilterValue, 77, 10, 0, 0, // Skip to: 1893 +/* 1883 */ MCD_OPC_CheckPredicate, 27, 108, 83, 0, // Skip to: 23244 +/* 1888 */ MCD_OPC_Decode, 209, 11, 201, 1, // Opcode: LGSC +/* 1893 */ MCD_OPC_FilterValue, 80, 5, 0, 0, // Skip to: 1903 +/* 1898 */ MCD_OPC_Decode, 245, 17, 205, 1, // Opcode: STY +/* 1903 */ MCD_OPC_FilterValue, 81, 5, 0, 0, // Skip to: 1913 +/* 1908 */ MCD_OPC_Decode, 206, 14, 202, 1, // Opcode: MSY +/* 1913 */ MCD_OPC_FilterValue, 83, 10, 0, 0, // Skip to: 1928 +/* 1918 */ MCD_OPC_CheckPredicate, 24, 73, 83, 0, // Skip to: 23244 +/* 1923 */ MCD_OPC_Decode, 185, 14, 202, 1, // Opcode: MSC +/* 1928 */ MCD_OPC_FilterValue, 84, 5, 0, 0, // Skip to: 1938 +/* 1933 */ MCD_OPC_Decode, 142, 15, 202, 1, // Opcode: NY +/* 1938 */ MCD_OPC_FilterValue, 85, 5, 0, 0, // Skip to: 1948 +/* 1943 */ MCD_OPC_Decode, 213, 8, 205, 1, // Opcode: CLY +/* 1948 */ MCD_OPC_FilterValue, 86, 5, 0, 0, // Skip to: 1958 +/* 1953 */ MCD_OPC_Decode, 160, 15, 202, 1, // Opcode: OY +/* 1958 */ MCD_OPC_FilterValue, 87, 5, 0, 0, // Skip to: 1968 +/* 1963 */ MCD_OPC_Decode, 159, 24, 202, 1, // Opcode: XY +/* 1968 */ MCD_OPC_FilterValue, 88, 5, 0, 0, // Skip to: 1978 +/* 1973 */ MCD_OPC_Decode, 132, 14, 205, 1, // Opcode: LY +/* 1978 */ MCD_OPC_FilterValue, 89, 5, 0, 0, // Skip to: 1988 +/* 1983 */ MCD_OPC_Decode, 193, 9, 205, 1, // Opcode: CY +/* 1988 */ MCD_OPC_FilterValue, 90, 5, 0, 0, // Skip to: 1998 +/* 1993 */ MCD_OPC_Decode, 173, 4, 202, 1, // Opcode: AY +/* 1998 */ MCD_OPC_FilterValue, 91, 5, 0, 0, // Skip to: 2008 +/* 2003 */ MCD_OPC_Decode, 255, 17, 202, 1, // Opcode: SY +/* 2008 */ MCD_OPC_FilterValue, 92, 5, 0, 0, // Skip to: 2018 +/* 2013 */ MCD_OPC_Decode, 170, 14, 204, 1, // Opcode: MFY +/* 2018 */ MCD_OPC_FilterValue, 94, 5, 0, 0, // Skip to: 2028 +/* 2023 */ MCD_OPC_Decode, 160, 4, 202, 1, // Opcode: ALY +/* 2028 */ MCD_OPC_FilterValue, 95, 5, 0, 0, // Skip to: 2038 +/* 2033 */ MCD_OPC_Decode, 212, 16, 202, 1, // Opcode: SLY +/* 2038 */ MCD_OPC_FilterValue, 112, 5, 0, 0, // Skip to: 2048 +/* 2043 */ MCD_OPC_Decode, 159, 17, 205, 1, // Opcode: STHY +/* 2048 */ MCD_OPC_FilterValue, 113, 5, 0, 0, // Skip to: 2058 +/* 2053 */ MCD_OPC_Decode, 144, 11, 201, 1, // Opcode: LAY +/* 2058 */ MCD_OPC_FilterValue, 114, 5, 0, 0, // Skip to: 2068 +/* 2063 */ MCD_OPC_Decode, 144, 17, 205, 1, // Opcode: STCY +/* 2068 */ MCD_OPC_FilterValue, 115, 5, 0, 0, // Skip to: 2078 +/* 2073 */ MCD_OPC_Decode, 144, 10, 203, 1, // Opcode: ICY +/* 2078 */ MCD_OPC_FilterValue, 117, 5, 0, 0, // Skip to: 2088 +/* 2083 */ MCD_OPC_Decode, 132, 11, 201, 1, // Opcode: LAEY +/* 2088 */ MCD_OPC_FilterValue, 118, 5, 0, 0, // Skip to: 2098 +/* 2093 */ MCD_OPC_Decode, 145, 11, 205, 1, // Opcode: LB +/* 2098 */ MCD_OPC_FilterValue, 119, 5, 0, 0, // Skip to: 2108 +/* 2103 */ MCD_OPC_Decode, 195, 11, 201, 1, // Opcode: LGB +/* 2108 */ MCD_OPC_FilterValue, 120, 5, 0, 0, // Skip to: 2118 +/* 2113 */ MCD_OPC_Decode, 215, 11, 205, 1, // Opcode: LHY +/* 2118 */ MCD_OPC_FilterValue, 121, 5, 0, 0, // Skip to: 2128 +/* 2123 */ MCD_OPC_Decode, 188, 6, 205, 1, // Opcode: CHY +/* 2128 */ MCD_OPC_FilterValue, 122, 5, 0, 0, // Skip to: 2138 +/* 2133 */ MCD_OPC_Decode, 136, 4, 202, 1, // Opcode: AHY +/* 2138 */ MCD_OPC_FilterValue, 123, 5, 0, 0, // Skip to: 2148 +/* 2143 */ MCD_OPC_Decode, 182, 16, 202, 1, // Opcode: SHY +/* 2148 */ MCD_OPC_FilterValue, 124, 5, 0, 0, // Skip to: 2158 +/* 2153 */ MCD_OPC_Decode, 177, 14, 202, 1, // Opcode: MHY +/* 2158 */ MCD_OPC_FilterValue, 128, 1, 5, 0, 0, // Skip to: 2169 +/* 2164 */ MCD_OPC_Decode, 247, 14, 203, 1, // Opcode: NG +/* 2169 */ MCD_OPC_FilterValue, 129, 1, 5, 0, 0, // Skip to: 2180 +/* 2175 */ MCD_OPC_Decode, 147, 15, 203, 1, // Opcode: OG +/* 2180 */ MCD_OPC_FilterValue, 130, 1, 5, 0, 0, // Skip to: 2191 +/* 2186 */ MCD_OPC_Decode, 149, 24, 203, 1, // Opcode: XG +/* 2191 */ MCD_OPC_FilterValue, 131, 1, 10, 0, 0, // Skip to: 2207 +/* 2197 */ MCD_OPC_CheckPredicate, 24, 50, 82, 0, // Skip to: 23244 +/* 2202 */ MCD_OPC_Decode, 197, 14, 203, 1, // Opcode: MSGC +/* 2207 */ MCD_OPC_FilterValue, 132, 1, 10, 0, 0, // Skip to: 2223 +/* 2213 */ MCD_OPC_CheckPredicate, 24, 34, 82, 0, // Skip to: 23244 +/* 2218 */ MCD_OPC_Decode, 171, 14, 204, 1, // Opcode: MG +/* 2223 */ MCD_OPC_FilterValue, 133, 1, 10, 0, 0, // Skip to: 2239 +/* 2229 */ MCD_OPC_CheckPredicate, 28, 18, 82, 0, // Skip to: 23244 +/* 2234 */ MCD_OPC_Decode, 194, 11, 201, 1, // Opcode: LGAT +/* 2239 */ MCD_OPC_FilterValue, 134, 1, 5, 0, 0, // Skip to: 2250 +/* 2245 */ MCD_OPC_Decode, 179, 14, 204, 1, // Opcode: MLG +/* 2250 */ MCD_OPC_FilterValue, 135, 1, 5, 0, 0, // Skip to: 2261 +/* 2256 */ MCD_OPC_Decode, 212, 9, 204, 1, // Opcode: DLG +/* 2261 */ MCD_OPC_FilterValue, 136, 1, 5, 0, 0, // Skip to: 2272 +/* 2267 */ MCD_OPC_Decode, 140, 4, 203, 1, // Opcode: ALCG +/* 2272 */ MCD_OPC_FilterValue, 137, 1, 5, 0, 0, // Skip to: 2283 +/* 2278 */ MCD_OPC_Decode, 191, 16, 203, 1, // Opcode: SLBG +/* 2283 */ MCD_OPC_FilterValue, 142, 1, 5, 0, 0, // Skip to: 2294 +/* 2289 */ MCD_OPC_Decode, 233, 17, 208, 1, // Opcode: STPQ +/* 2294 */ MCD_OPC_FilterValue, 143, 1, 5, 0, 0, // Skip to: 2305 +/* 2300 */ MCD_OPC_Decode, 213, 13, 208, 1, // Opcode: LPQ +/* 2305 */ MCD_OPC_FilterValue, 144, 1, 5, 0, 0, // Skip to: 2316 +/* 2311 */ MCD_OPC_Decode, 219, 11, 201, 1, // Opcode: LLGC +/* 2316 */ MCD_OPC_FilterValue, 145, 1, 5, 0, 0, // Skip to: 2327 +/* 2322 */ MCD_OPC_Decode, 226, 11, 201, 1, // Opcode: LLGH +/* 2327 */ MCD_OPC_FilterValue, 148, 1, 5, 0, 0, // Skip to: 2338 +/* 2333 */ MCD_OPC_Decode, 216, 11, 205, 1, // Opcode: LLC +/* 2338 */ MCD_OPC_FilterValue, 149, 1, 5, 0, 0, // Skip to: 2349 +/* 2344 */ MCD_OPC_Decode, 232, 11, 205, 1, // Opcode: LLH +/* 2349 */ MCD_OPC_FilterValue, 150, 1, 5, 0, 0, // Skip to: 2360 +/* 2355 */ MCD_OPC_Decode, 178, 14, 204, 1, // Opcode: ML +/* 2360 */ MCD_OPC_FilterValue, 151, 1, 5, 0, 0, // Skip to: 2371 +/* 2366 */ MCD_OPC_Decode, 211, 9, 204, 1, // Opcode: DL +/* 2371 */ MCD_OPC_FilterValue, 152, 1, 5, 0, 0, // Skip to: 2382 +/* 2377 */ MCD_OPC_Decode, 139, 4, 202, 1, // Opcode: ALC +/* 2382 */ MCD_OPC_FilterValue, 153, 1, 5, 0, 0, // Skip to: 2393 +/* 2388 */ MCD_OPC_Decode, 190, 16, 202, 1, // Opcode: SLB +/* 2393 */ MCD_OPC_FilterValue, 156, 1, 10, 0, 0, // Skip to: 2409 +/* 2399 */ MCD_OPC_CheckPredicate, 28, 104, 81, 0, // Skip to: 23244 +/* 2404 */ MCD_OPC_Decode, 230, 11, 201, 1, // Opcode: LLGTAT +/* 2409 */ MCD_OPC_FilterValue, 157, 1, 10, 0, 0, // Skip to: 2425 +/* 2415 */ MCD_OPC_CheckPredicate, 28, 88, 81, 0, // Skip to: 23244 +/* 2420 */ MCD_OPC_Decode, 222, 11, 201, 1, // Opcode: LLGFAT +/* 2425 */ MCD_OPC_FilterValue, 159, 1, 10, 0, 0, // Skip to: 2441 +/* 2431 */ MCD_OPC_CheckPredicate, 28, 72, 81, 0, // Skip to: 23244 +/* 2436 */ MCD_OPC_Decode, 141, 11, 205, 1, // Opcode: LAT +/* 2441 */ MCD_OPC_FilterValue, 192, 1, 10, 0, 0, // Skip to: 2457 +/* 2447 */ MCD_OPC_CheckPredicate, 19, 56, 81, 0, // Skip to: 23244 +/* 2452 */ MCD_OPC_Decode, 147, 11, 209, 1, // Opcode: LBH +/* 2457 */ MCD_OPC_FilterValue, 194, 1, 10, 0, 0, // Skip to: 2473 +/* 2463 */ MCD_OPC_CheckPredicate, 19, 40, 81, 0, // Skip to: 23244 +/* 2468 */ MCD_OPC_Decode, 217, 11, 209, 1, // Opcode: LLCH +/* 2473 */ MCD_OPC_FilterValue, 195, 1, 10, 0, 0, // Skip to: 2489 +/* 2479 */ MCD_OPC_CheckPredicate, 19, 24, 81, 0, // Skip to: 23244 +/* 2484 */ MCD_OPC_Decode, 132, 17, 209, 1, // Opcode: STCH +/* 2489 */ MCD_OPC_FilterValue, 196, 1, 10, 0, 0, // Skip to: 2505 +/* 2495 */ MCD_OPC_CheckPredicate, 19, 8, 81, 0, // Skip to: 23244 +/* 2500 */ MCD_OPC_Decode, 211, 11, 209, 1, // Opcode: LHH +/* 2505 */ MCD_OPC_FilterValue, 198, 1, 10, 0, 0, // Skip to: 2521 +/* 2511 */ MCD_OPC_CheckPredicate, 19, 248, 80, 0, // Skip to: 23244 +/* 2516 */ MCD_OPC_Decode, 233, 11, 209, 1, // Opcode: LLHH +/* 2521 */ MCD_OPC_FilterValue, 199, 1, 10, 0, 0, // Skip to: 2537 +/* 2527 */ MCD_OPC_CheckPredicate, 19, 232, 80, 0, // Skip to: 23244 +/* 2532 */ MCD_OPC_Decode, 157, 17, 209, 1, // Opcode: STHH +/* 2537 */ MCD_OPC_FilterValue, 200, 1, 10, 0, 0, // Skip to: 2553 +/* 2543 */ MCD_OPC_CheckPredicate, 28, 216, 80, 0, // Skip to: 23244 +/* 2548 */ MCD_OPC_Decode, 191, 11, 209, 1, // Opcode: LFHAT +/* 2553 */ MCD_OPC_FilterValue, 202, 1, 10, 0, 0, // Skip to: 2569 +/* 2559 */ MCD_OPC_CheckPredicate, 19, 200, 80, 0, // Skip to: 23244 +/* 2564 */ MCD_OPC_Decode, 190, 11, 209, 1, // Opcode: LFH +/* 2569 */ MCD_OPC_FilterValue, 203, 1, 10, 0, 0, // Skip to: 2585 +/* 2575 */ MCD_OPC_CheckPredicate, 19, 184, 80, 0, // Skip to: 23244 +/* 2580 */ MCD_OPC_Decode, 149, 17, 209, 1, // Opcode: STFH +/* 2585 */ MCD_OPC_FilterValue, 205, 1, 10, 0, 0, // Skip to: 2601 +/* 2591 */ MCD_OPC_CheckPredicate, 19, 168, 80, 0, // Skip to: 23244 +/* 2596 */ MCD_OPC_Decode, 181, 6, 209, 1, // Opcode: CHF +/* 2601 */ MCD_OPC_FilterValue, 207, 1, 157, 80, 0, // Skip to: 23244 +/* 2607 */ MCD_OPC_CheckPredicate, 19, 152, 80, 0, // Skip to: 23244 +/* 2612 */ MCD_OPC_Decode, 243, 7, 209, 1, // Opcode: CLHF +/* 2617 */ MCD_OPC_FilterValue, 229, 1, 188, 0, 0, // Skip to: 2811 +/* 2623 */ MCD_OPC_ExtractField, 32, 8, // Inst{39-32} ... +/* 2626 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 2636 +/* 2631 */ MCD_OPC_Decode, 140, 11, 210, 1, // Opcode: LASP +/* 2636 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 2646 +/* 2641 */ MCD_OPC_Decode, 156, 18, 210, 1, // Opcode: TPROT +/* 2646 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 2656 +/* 2651 */ MCD_OPC_Decode, 236, 17, 210, 1, // Opcode: STRAG +/* 2656 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 2671 +/* 2661 */ MCD_OPC_CheckPredicate, 14, 98, 80, 0, // Skip to: 23244 +/* 2666 */ MCD_OPC_Decode, 216, 14, 210, 1, // Opcode: MVCRL +/* 2671 */ MCD_OPC_FilterValue, 14, 5, 0, 0, // Skip to: 2681 +/* 2676 */ MCD_OPC_Decode, 218, 14, 210, 1, // Opcode: MVCSK +/* 2681 */ MCD_OPC_FilterValue, 15, 5, 0, 0, // Skip to: 2691 +/* 2686 */ MCD_OPC_Decode, 208, 14, 210, 1, // Opcode: MVCDK +/* 2691 */ MCD_OPC_FilterValue, 68, 5, 0, 0, // Skip to: 2701 +/* 2696 */ MCD_OPC_Decode, 220, 14, 211, 1, // Opcode: MVHHI +/* 2701 */ MCD_OPC_FilterValue, 72, 5, 0, 0, // Skip to: 2711 +/* 2706 */ MCD_OPC_Decode, 219, 14, 211, 1, // Opcode: MVGHI +/* 2711 */ MCD_OPC_FilterValue, 76, 5, 0, 0, // Skip to: 2721 +/* 2716 */ MCD_OPC_Decode, 221, 14, 211, 1, // Opcode: MVHI +/* 2721 */ MCD_OPC_FilterValue, 84, 5, 0, 0, // Skip to: 2731 +/* 2726 */ MCD_OPC_Decode, 183, 6, 211, 1, // Opcode: CHHSI +/* 2731 */ MCD_OPC_FilterValue, 85, 5, 0, 0, // Skip to: 2741 +/* 2736 */ MCD_OPC_Decode, 245, 7, 212, 1, // Opcode: CLHHSI +/* 2741 */ MCD_OPC_FilterValue, 88, 5, 0, 0, // Skip to: 2751 +/* 2746 */ MCD_OPC_Decode, 216, 5, 211, 1, // Opcode: CGHSI +/* 2751 */ MCD_OPC_FilterValue, 89, 5, 0, 0, // Skip to: 2761 +/* 2756 */ MCD_OPC_Decode, 140, 7, 212, 1, // Opcode: CLGHSI +/* 2761 */ MCD_OPC_FilterValue, 92, 5, 0, 0, // Skip to: 2771 +/* 2766 */ MCD_OPC_Decode, 187, 6, 211, 1, // Opcode: CHSI +/* 2771 */ MCD_OPC_FilterValue, 93, 5, 0, 0, // Skip to: 2781 +/* 2776 */ MCD_OPC_Decode, 241, 6, 212, 1, // Opcode: CLFHSI +/* 2781 */ MCD_OPC_FilterValue, 96, 10, 0, 0, // Skip to: 2796 +/* 2786 */ MCD_OPC_CheckPredicate, 4, 229, 79, 0, // Skip to: 23244 +/* 2791 */ MCD_OPC_Decode, 134, 18, 212, 1, // Opcode: TBEGIN +/* 2796 */ MCD_OPC_FilterValue, 97, 219, 79, 0, // Skip to: 23244 +/* 2801 */ MCD_OPC_CheckPredicate, 4, 214, 79, 0, // Skip to: 23244 +/* 2806 */ MCD_OPC_Decode, 135, 18, 212, 1, // Opcode: TBEGINC +/* 2811 */ MCD_OPC_FilterValue, 230, 1, 204, 6, 0, // Skip to: 4557 +/* 2817 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 2820 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 2842 +/* 2825 */ MCD_OPC_CheckPredicate, 29, 190, 79, 0, // Skip to: 23244 +/* 2830 */ MCD_OPC_CheckField, 8, 3, 0, 183, 79, 0, // Skip to: 23244 +/* 2837 */ MCD_OPC_Decode, 244, 20, 213, 1, // Opcode: VLEBRH +/* 2842 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 2864 +/* 2847 */ MCD_OPC_CheckPredicate, 29, 168, 79, 0, // Skip to: 23244 +/* 2852 */ MCD_OPC_CheckField, 8, 3, 0, 161, 79, 0, // Skip to: 23244 +/* 2859 */ MCD_OPC_Decode, 243, 20, 214, 1, // Opcode: VLEBRG +/* 2864 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 2886 +/* 2869 */ MCD_OPC_CheckPredicate, 29, 146, 79, 0, // Skip to: 23244 +/* 2874 */ MCD_OPC_CheckField, 8, 3, 0, 139, 79, 0, // Skip to: 23244 +/* 2881 */ MCD_OPC_Decode, 242, 20, 215, 1, // Opcode: VLEBRF +/* 2886 */ MCD_OPC_FilterValue, 4, 81, 0, 0, // Skip to: 2972 +/* 2891 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 2894 */ MCD_OPC_FilterValue, 0, 121, 79, 0, // Skip to: 23244 +/* 2899 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 2902 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2917 +/* 2907 */ MCD_OPC_CheckPredicate, 29, 50, 0, 0, // Skip to: 2962 +/* 2912 */ MCD_OPC_Decode, 141, 21, 216, 1, // Opcode: VLLEBRZH +/* 2917 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2932 +/* 2922 */ MCD_OPC_CheckPredicate, 29, 35, 0, 0, // Skip to: 2962 +/* 2927 */ MCD_OPC_Decode, 139, 21, 216, 1, // Opcode: VLLEBRZF +/* 2932 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 2947 +/* 2937 */ MCD_OPC_CheckPredicate, 29, 20, 0, 0, // Skip to: 2962 +/* 2942 */ MCD_OPC_Decode, 140, 21, 216, 1, // Opcode: VLLEBRZG +/* 2947 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 2962 +/* 2952 */ MCD_OPC_CheckPredicate, 29, 5, 0, 0, // Skip to: 2962 +/* 2957 */ MCD_OPC_Decode, 138, 21, 216, 1, // Opcode: VLLEBRZE +/* 2962 */ MCD_OPC_CheckPredicate, 29, 53, 79, 0, // Skip to: 23244 +/* 2967 */ MCD_OPC_Decode, 137, 21, 217, 1, // Opcode: VLLEBRZ +/* 2972 */ MCD_OPC_FilterValue, 5, 66, 0, 0, // Skip to: 3043 +/* 2977 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 2980 */ MCD_OPC_FilterValue, 0, 35, 79, 0, // Skip to: 23244 +/* 2985 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 2988 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 3003 +/* 2993 */ MCD_OPC_CheckPredicate, 29, 35, 0, 0, // Skip to: 3033 +/* 2998 */ MCD_OPC_Decode, 233, 20, 216, 1, // Opcode: VLBRREPH +/* 3003 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 3018 +/* 3008 */ MCD_OPC_CheckPredicate, 29, 20, 0, 0, // Skip to: 3033 +/* 3013 */ MCD_OPC_Decode, 231, 20, 216, 1, // Opcode: VLBRREPF +/* 3018 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 3033 +/* 3023 */ MCD_OPC_CheckPredicate, 29, 5, 0, 0, // Skip to: 3033 +/* 3028 */ MCD_OPC_Decode, 232, 20, 216, 1, // Opcode: VLBRREPG +/* 3033 */ MCD_OPC_CheckPredicate, 29, 238, 78, 0, // Skip to: 23244 +/* 3038 */ MCD_OPC_Decode, 230, 20, 217, 1, // Opcode: VLBRREP +/* 3043 */ MCD_OPC_FilterValue, 6, 81, 0, 0, // Skip to: 3129 +/* 3048 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 3051 */ MCD_OPC_FilterValue, 0, 220, 78, 0, // Skip to: 23244 +/* 3056 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 3059 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 3074 +/* 3064 */ MCD_OPC_CheckPredicate, 29, 50, 0, 0, // Skip to: 3119 +/* 3069 */ MCD_OPC_Decode, 228, 20, 216, 1, // Opcode: VLBRH +/* 3074 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 3089 +/* 3079 */ MCD_OPC_CheckPredicate, 29, 35, 0, 0, // Skip to: 3119 +/* 3084 */ MCD_OPC_Decode, 226, 20, 216, 1, // Opcode: VLBRF +/* 3089 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 3104 +/* 3094 */ MCD_OPC_CheckPredicate, 29, 20, 0, 0, // Skip to: 3119 +/* 3099 */ MCD_OPC_Decode, 227, 20, 216, 1, // Opcode: VLBRG +/* 3104 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 3119 +/* 3109 */ MCD_OPC_CheckPredicate, 29, 5, 0, 0, // Skip to: 3119 +/* 3114 */ MCD_OPC_Decode, 229, 20, 216, 1, // Opcode: VLBRQ +/* 3119 */ MCD_OPC_CheckPredicate, 29, 152, 78, 0, // Skip to: 23244 +/* 3124 */ MCD_OPC_Decode, 225, 20, 217, 1, // Opcode: VLBR +/* 3129 */ MCD_OPC_FilterValue, 7, 66, 0, 0, // Skip to: 3200 +/* 3134 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 3137 */ MCD_OPC_FilterValue, 0, 134, 78, 0, // Skip to: 23244 +/* 3142 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 3145 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 3160 +/* 3150 */ MCD_OPC_CheckPredicate, 29, 35, 0, 0, // Skip to: 3190 +/* 3155 */ MCD_OPC_Decode, 129, 21, 216, 1, // Opcode: VLERH +/* 3160 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 3175 +/* 3165 */ MCD_OPC_CheckPredicate, 29, 20, 0, 0, // Skip to: 3190 +/* 3170 */ MCD_OPC_Decode, 255, 20, 216, 1, // Opcode: VLERF +/* 3175 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 3190 +/* 3180 */ MCD_OPC_CheckPredicate, 29, 5, 0, 0, // Skip to: 3190 +/* 3185 */ MCD_OPC_Decode, 128, 21, 216, 1, // Opcode: VLERG +/* 3190 */ MCD_OPC_CheckPredicate, 29, 81, 78, 0, // Skip to: 23244 +/* 3195 */ MCD_OPC_Decode, 254, 20, 217, 1, // Opcode: VLER +/* 3200 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 3222 +/* 3205 */ MCD_OPC_CheckPredicate, 29, 66, 78, 0, // Skip to: 23244 +/* 3210 */ MCD_OPC_CheckField, 8, 3, 0, 59, 78, 0, // Skip to: 23244 +/* 3217 */ MCD_OPC_Decode, 229, 22, 218, 1, // Opcode: VSTEBRH +/* 3222 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 3244 +/* 3227 */ MCD_OPC_CheckPredicate, 29, 44, 78, 0, // Skip to: 23244 +/* 3232 */ MCD_OPC_CheckField, 8, 3, 0, 37, 78, 0, // Skip to: 23244 +/* 3239 */ MCD_OPC_Decode, 228, 22, 219, 1, // Opcode: VSTEBRG +/* 3244 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 3266 +/* 3249 */ MCD_OPC_CheckPredicate, 29, 22, 78, 0, // Skip to: 23244 +/* 3254 */ MCD_OPC_CheckField, 8, 3, 0, 15, 78, 0, // Skip to: 23244 +/* 3261 */ MCD_OPC_Decode, 227, 22, 220, 1, // Opcode: VSTEBRF +/* 3266 */ MCD_OPC_FilterValue, 14, 81, 0, 0, // Skip to: 3352 +/* 3271 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 3274 */ MCD_OPC_FilterValue, 0, 253, 77, 0, // Skip to: 23244 +/* 3279 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 3282 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 3297 +/* 3287 */ MCD_OPC_CheckPredicate, 29, 50, 0, 0, // Skip to: 3342 +/* 3292 */ MCD_OPC_Decode, 224, 22, 216, 1, // Opcode: VSTBRH +/* 3297 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 3312 +/* 3302 */ MCD_OPC_CheckPredicate, 29, 35, 0, 0, // Skip to: 3342 +/* 3307 */ MCD_OPC_Decode, 222, 22, 216, 1, // Opcode: VSTBRF +/* 3312 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 3327 +/* 3317 */ MCD_OPC_CheckPredicate, 29, 20, 0, 0, // Skip to: 3342 +/* 3322 */ MCD_OPC_Decode, 223, 22, 216, 1, // Opcode: VSTBRG +/* 3327 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 3342 +/* 3332 */ MCD_OPC_CheckPredicate, 29, 5, 0, 0, // Skip to: 3342 +/* 3337 */ MCD_OPC_Decode, 225, 22, 216, 1, // Opcode: VSTBRQ +/* 3342 */ MCD_OPC_CheckPredicate, 29, 185, 77, 0, // Skip to: 23244 +/* 3347 */ MCD_OPC_Decode, 221, 22, 217, 1, // Opcode: VSTBR +/* 3352 */ MCD_OPC_FilterValue, 15, 66, 0, 0, // Skip to: 3423 +/* 3357 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 3360 */ MCD_OPC_FilterValue, 0, 167, 77, 0, // Skip to: 23244 +/* 3365 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 3368 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 3383 +/* 3373 */ MCD_OPC_CheckPredicate, 29, 35, 0, 0, // Skip to: 3413 +/* 3378 */ MCD_OPC_Decode, 236, 22, 216, 1, // Opcode: VSTERH +/* 3383 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 3398 +/* 3388 */ MCD_OPC_CheckPredicate, 29, 20, 0, 0, // Skip to: 3413 +/* 3393 */ MCD_OPC_Decode, 234, 22, 216, 1, // Opcode: VSTERF +/* 3398 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 3413 +/* 3403 */ MCD_OPC_CheckPredicate, 29, 5, 0, 0, // Skip to: 3413 +/* 3408 */ MCD_OPC_Decode, 235, 22, 216, 1, // Opcode: VSTERG +/* 3413 */ MCD_OPC_CheckPredicate, 29, 114, 77, 0, // Skip to: 23244 +/* 3418 */ MCD_OPC_Decode, 233, 22, 217, 1, // Opcode: VSTER +/* 3423 */ MCD_OPC_FilterValue, 52, 17, 0, 0, // Skip to: 3445 +/* 3428 */ MCD_OPC_CheckPredicate, 30, 99, 77, 0, // Skip to: 23244 +/* 3433 */ MCD_OPC_CheckField, 9, 3, 0, 92, 77, 0, // Skip to: 23244 +/* 3440 */ MCD_OPC_Decode, 159, 22, 221, 1, // Opcode: VPKZ +/* 3445 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 3467 +/* 3450 */ MCD_OPC_CheckPredicate, 30, 77, 77, 0, // Skip to: 23244 +/* 3455 */ MCD_OPC_CheckField, 9, 3, 0, 70, 77, 0, // Skip to: 23244 +/* 3462 */ MCD_OPC_Decode, 161, 21, 221, 1, // Opcode: VLRL +/* 3467 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 3496 +/* 3472 */ MCD_OPC_CheckPredicate, 30, 55, 77, 0, // Skip to: 23244 +/* 3477 */ MCD_OPC_CheckField, 36, 4, 0, 48, 77, 0, // Skip to: 23244 +/* 3484 */ MCD_OPC_CheckField, 9, 3, 0, 41, 77, 0, // Skip to: 23244 +/* 3491 */ MCD_OPC_Decode, 162, 21, 222, 1, // Opcode: VLRLR +/* 3496 */ MCD_OPC_FilterValue, 60, 17, 0, 0, // Skip to: 3518 +/* 3501 */ MCD_OPC_CheckPredicate, 30, 26, 77, 0, // Skip to: 23244 +/* 3506 */ MCD_OPC_CheckField, 9, 3, 0, 19, 77, 0, // Skip to: 23244 +/* 3513 */ MCD_OPC_Decode, 149, 23, 221, 1, // Opcode: VUPKZ +/* 3518 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 3540 +/* 3523 */ MCD_OPC_CheckPredicate, 30, 4, 77, 0, // Skip to: 23244 +/* 3528 */ MCD_OPC_CheckField, 9, 3, 0, 253, 76, 0, // Skip to: 23244 +/* 3535 */ MCD_OPC_Decode, 253, 22, 221, 1, // Opcode: VSTRL +/* 3540 */ MCD_OPC_FilterValue, 63, 24, 0, 0, // Skip to: 3569 +/* 3545 */ MCD_OPC_CheckPredicate, 30, 238, 76, 0, // Skip to: 23244 +/* 3550 */ MCD_OPC_CheckField, 36, 4, 0, 231, 76, 0, // Skip to: 23244 +/* 3557 */ MCD_OPC_CheckField, 9, 3, 0, 224, 76, 0, // Skip to: 23244 +/* 3564 */ MCD_OPC_Decode, 254, 22, 222, 1, // Opcode: VSTRLR +/* 3569 */ MCD_OPC_FilterValue, 73, 24, 0, 0, // Skip to: 3598 +/* 3574 */ MCD_OPC_CheckPredicate, 30, 209, 76, 0, // Skip to: 23244 +/* 3579 */ MCD_OPC_CheckField, 32, 4, 0, 202, 76, 0, // Skip to: 23244 +/* 3586 */ MCD_OPC_CheckField, 8, 3, 0, 195, 76, 0, // Skip to: 23244 +/* 3593 */ MCD_OPC_Decode, 135, 21, 223, 1, // Opcode: VLIP +/* 3598 */ MCD_OPC_FilterValue, 80, 51, 0, 0, // Skip to: 3654 +/* 3603 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 3606 */ MCD_OPC_FilterValue, 0, 177, 76, 0, // Skip to: 23244 +/* 3611 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 3614 */ MCD_OPC_FilterValue, 0, 169, 76, 0, // Skip to: 23244 +/* 3619 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 3622 */ MCD_OPC_FilterValue, 0, 161, 76, 0, // Skip to: 23244 +/* 3627 */ MCD_OPC_CheckPredicate, 30, 12, 0, 0, // Skip to: 3644 +/* 3632 */ MCD_OPC_CheckField, 16, 4, 0, 5, 0, 0, // Skip to: 3644 +/* 3639 */ MCD_OPC_Decode, 145, 19, 224, 1, // Opcode: VCVB +/* 3644 */ MCD_OPC_CheckPredicate, 31, 139, 76, 0, // Skip to: 23244 +/* 3649 */ MCD_OPC_Decode, 148, 19, 225, 1, // Opcode: VCVBOpt +/* 3654 */ MCD_OPC_FilterValue, 81, 31, 0, 0, // Skip to: 3690 +/* 3659 */ MCD_OPC_CheckPredicate, 32, 124, 76, 0, // Skip to: 23244 +/* 3664 */ MCD_OPC_CheckField, 24, 8, 0, 117, 76, 0, // Skip to: 23244 +/* 3671 */ MCD_OPC_CheckField, 12, 8, 0, 110, 76, 0, // Skip to: 23244 +/* 3678 */ MCD_OPC_CheckField, 8, 2, 0, 103, 76, 0, // Skip to: 23244 +/* 3685 */ MCD_OPC_Decode, 131, 19, 226, 1, // Opcode: VCLZDP +/* 3690 */ MCD_OPC_FilterValue, 82, 51, 0, 0, // Skip to: 3746 +/* 3695 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 3698 */ MCD_OPC_FilterValue, 0, 85, 76, 0, // Skip to: 23244 +/* 3703 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 3706 */ MCD_OPC_FilterValue, 0, 77, 76, 0, // Skip to: 23244 +/* 3711 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 3714 */ MCD_OPC_FilterValue, 0, 69, 76, 0, // Skip to: 23244 +/* 3719 */ MCD_OPC_CheckPredicate, 30, 12, 0, 0, // Skip to: 3736 +/* 3724 */ MCD_OPC_CheckField, 16, 4, 0, 5, 0, 0, // Skip to: 3736 +/* 3731 */ MCD_OPC_Decode, 146, 19, 227, 1, // Opcode: VCVBG +/* 3736 */ MCD_OPC_CheckPredicate, 31, 47, 76, 0, // Skip to: 23244 +/* 3741 */ MCD_OPC_Decode, 147, 19, 228, 1, // Opcode: VCVBGOpt +/* 3746 */ MCD_OPC_FilterValue, 84, 31, 0, 0, // Skip to: 3782 +/* 3751 */ MCD_OPC_CheckPredicate, 32, 32, 76, 0, // Skip to: 23244 +/* 3756 */ MCD_OPC_CheckField, 24, 8, 0, 25, 76, 0, // Skip to: 23244 +/* 3763 */ MCD_OPC_CheckField, 12, 8, 0, 18, 76, 0, // Skip to: 23244 +/* 3770 */ MCD_OPC_CheckField, 8, 2, 0, 11, 76, 0, // Skip to: 23244 +/* 3777 */ MCD_OPC_Decode, 150, 23, 226, 1, // Opcode: VUPKZH +/* 3782 */ MCD_OPC_FilterValue, 85, 24, 0, 0, // Skip to: 3811 +/* 3787 */ MCD_OPC_CheckPredicate, 33, 252, 75, 0, // Skip to: 23244 +/* 3792 */ MCD_OPC_CheckField, 20, 12, 0, 245, 75, 0, // Skip to: 23244 +/* 3799 */ MCD_OPC_CheckField, 8, 2, 0, 238, 75, 0, // Skip to: 23244 +/* 3806 */ MCD_OPC_Decode, 135, 19, 229, 1, // Opcode: VCNF +/* 3811 */ MCD_OPC_FilterValue, 86, 24, 0, 0, // Skip to: 3840 +/* 3816 */ MCD_OPC_CheckPredicate, 33, 223, 75, 0, // Skip to: 23244 +/* 3821 */ MCD_OPC_CheckField, 20, 12, 0, 216, 75, 0, // Skip to: 23244 +/* 3828 */ MCD_OPC_CheckField, 8, 2, 0, 209, 75, 0, // Skip to: 23244 +/* 3835 */ MCD_OPC_Decode, 252, 18, 229, 1, // Opcode: VCLFNH +/* 3840 */ MCD_OPC_FilterValue, 88, 24, 0, 0, // Skip to: 3869 +/* 3845 */ MCD_OPC_CheckPredicate, 30, 194, 75, 0, // Skip to: 23244 +/* 3850 */ MCD_OPC_CheckField, 24, 8, 0, 187, 75, 0, // Skip to: 23244 +/* 3857 */ MCD_OPC_CheckField, 8, 3, 0, 180, 75, 0, // Skip to: 23244 +/* 3864 */ MCD_OPC_Decode, 149, 19, 230, 1, // Opcode: VCVD +/* 3869 */ MCD_OPC_FilterValue, 89, 17, 0, 0, // Skip to: 3891 +/* 3874 */ MCD_OPC_CheckPredicate, 30, 165, 75, 0, // Skip to: 23244 +/* 3879 */ MCD_OPC_CheckField, 8, 2, 0, 158, 75, 0, // Skip to: 23244 +/* 3886 */ MCD_OPC_Decode, 217, 22, 231, 1, // Opcode: VSRP +/* 3891 */ MCD_OPC_FilterValue, 90, 24, 0, 0, // Skip to: 3920 +/* 3896 */ MCD_OPC_CheckPredicate, 30, 143, 75, 0, // Skip to: 23244 +/* 3901 */ MCD_OPC_CheckField, 24, 8, 0, 136, 75, 0, // Skip to: 23244 +/* 3908 */ MCD_OPC_CheckField, 8, 3, 0, 129, 75, 0, // Skip to: 23244 +/* 3915 */ MCD_OPC_Decode, 150, 19, 232, 1, // Opcode: VCVDG +/* 3920 */ MCD_OPC_FilterValue, 91, 17, 0, 0, // Skip to: 3942 +/* 3925 */ MCD_OPC_CheckPredicate, 30, 114, 75, 0, // Skip to: 23244 +/* 3930 */ MCD_OPC_CheckField, 8, 2, 0, 107, 75, 0, // Skip to: 23244 +/* 3937 */ MCD_OPC_Decode, 166, 22, 231, 1, // Opcode: VPSOP +/* 3942 */ MCD_OPC_FilterValue, 92, 31, 0, 0, // Skip to: 3978 +/* 3947 */ MCD_OPC_CheckPredicate, 32, 92, 75, 0, // Skip to: 23244 +/* 3952 */ MCD_OPC_CheckField, 24, 8, 0, 85, 75, 0, // Skip to: 23244 +/* 3959 */ MCD_OPC_CheckField, 12, 8, 0, 78, 75, 0, // Skip to: 23244 +/* 3966 */ MCD_OPC_CheckField, 8, 2, 0, 71, 75, 0, // Skip to: 23244 +/* 3973 */ MCD_OPC_Decode, 151, 23, 226, 1, // Opcode: VUPKZL +/* 3978 */ MCD_OPC_FilterValue, 93, 24, 0, 0, // Skip to: 4007 +/* 3983 */ MCD_OPC_CheckPredicate, 33, 56, 75, 0, // Skip to: 23244 +/* 3988 */ MCD_OPC_CheckField, 20, 12, 0, 49, 75, 0, // Skip to: 23244 +/* 3995 */ MCD_OPC_CheckField, 8, 2, 0, 42, 75, 0, // Skip to: 23244 +/* 4002 */ MCD_OPC_Decode, 227, 18, 229, 1, // Opcode: VCFN +/* 4007 */ MCD_OPC_FilterValue, 94, 24, 0, 0, // Skip to: 4036 +/* 4012 */ MCD_OPC_CheckPredicate, 33, 27, 75, 0, // Skip to: 23244 +/* 4017 */ MCD_OPC_CheckField, 20, 12, 0, 20, 75, 0, // Skip to: 23244 +/* 4024 */ MCD_OPC_CheckField, 8, 2, 0, 13, 75, 0, // Skip to: 23244 +/* 4031 */ MCD_OPC_Decode, 253, 18, 229, 1, // Opcode: VCLFNL +/* 4036 */ MCD_OPC_FilterValue, 95, 31, 0, 0, // Skip to: 4072 +/* 4041 */ MCD_OPC_CheckPredicate, 30, 254, 74, 0, // Skip to: 23244 +/* 4046 */ MCD_OPC_CheckField, 36, 4, 0, 247, 74, 0, // Skip to: 23244 +/* 4053 */ MCD_OPC_CheckField, 11, 21, 0, 240, 74, 0, // Skip to: 23244 +/* 4060 */ MCD_OPC_CheckField, 8, 2, 0, 233, 74, 0, // Skip to: 23244 +/* 4067 */ MCD_OPC_Decode, 144, 23, 233, 1, // Opcode: VTP +/* 4072 */ MCD_OPC_FilterValue, 112, 24, 0, 0, // Skip to: 4101 +/* 4077 */ MCD_OPC_CheckPredicate, 32, 218, 74, 0, // Skip to: 23244 +/* 4082 */ MCD_OPC_CheckField, 24, 4, 0, 211, 74, 0, // Skip to: 23244 +/* 4089 */ MCD_OPC_CheckField, 8, 1, 0, 204, 74, 0, // Skip to: 23244 +/* 4096 */ MCD_OPC_Decode, 160, 22, 234, 1, // Opcode: VPKZR +/* 4101 */ MCD_OPC_FilterValue, 113, 24, 0, 0, // Skip to: 4130 +/* 4106 */ MCD_OPC_CheckPredicate, 30, 189, 74, 0, // Skip to: 23244 +/* 4111 */ MCD_OPC_CheckField, 24, 4, 0, 182, 74, 0, // Skip to: 23244 +/* 4118 */ MCD_OPC_CheckField, 8, 1, 0, 175, 74, 0, // Skip to: 23244 +/* 4125 */ MCD_OPC_Decode, 198, 18, 234, 1, // Opcode: VAP +/* 4130 */ MCD_OPC_FilterValue, 114, 24, 0, 0, // Skip to: 4159 +/* 4135 */ MCD_OPC_CheckPredicate, 32, 160, 74, 0, // Skip to: 23244 +/* 4140 */ MCD_OPC_CheckField, 24, 4, 0, 153, 74, 0, // Skip to: 23244 +/* 4147 */ MCD_OPC_CheckField, 8, 1, 0, 146, 74, 0, // Skip to: 23244 +/* 4154 */ MCD_OPC_Decode, 218, 22, 234, 1, // Opcode: VSRPR +/* 4159 */ MCD_OPC_FilterValue, 115, 24, 0, 0, // Skip to: 4188 +/* 4164 */ MCD_OPC_CheckPredicate, 30, 131, 74, 0, // Skip to: 23244 +/* 4169 */ MCD_OPC_CheckField, 24, 4, 0, 124, 74, 0, // Skip to: 23244 +/* 4176 */ MCD_OPC_CheckField, 8, 1, 0, 117, 74, 0, // Skip to: 23244 +/* 4183 */ MCD_OPC_Decode, 210, 22, 234, 1, // Opcode: VSP +/* 4188 */ MCD_OPC_FilterValue, 116, 82, 0, 0, // Skip to: 4275 +/* 4193 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 4196 */ MCD_OPC_FilterValue, 0, 99, 74, 0, // Skip to: 23244 +/* 4201 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 4204 */ MCD_OPC_FilterValue, 0, 91, 74, 0, // Skip to: 23244 +/* 4209 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 4212 */ MCD_OPC_FilterValue, 0, 83, 74, 0, // Skip to: 23244 +/* 4217 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 4220 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 4235 +/* 4225 */ MCD_OPC_CheckPredicate, 32, 35, 0, 0, // Skip to: 4265 +/* 4230 */ MCD_OPC_Decode, 194, 22, 235, 1, // Opcode: VSCHSP +/* 4235 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 4250 +/* 4240 */ MCD_OPC_CheckPredicate, 32, 20, 0, 0, // Skip to: 4265 +/* 4245 */ MCD_OPC_Decode, 192, 22, 235, 1, // Opcode: VSCHDP +/* 4250 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 4265 +/* 4255 */ MCD_OPC_CheckPredicate, 32, 5, 0, 0, // Skip to: 4265 +/* 4260 */ MCD_OPC_Decode, 195, 22, 235, 1, // Opcode: VSCHXP +/* 4265 */ MCD_OPC_CheckPredicate, 32, 30, 74, 0, // Skip to: 23244 +/* 4270 */ MCD_OPC_Decode, 193, 22, 236, 1, // Opcode: VSCHP +/* 4275 */ MCD_OPC_FilterValue, 117, 24, 0, 0, // Skip to: 4304 +/* 4280 */ MCD_OPC_CheckPredicate, 33, 15, 74, 0, // Skip to: 23244 +/* 4285 */ MCD_OPC_CheckField, 20, 8, 0, 8, 74, 0, // Skip to: 23244 +/* 4292 */ MCD_OPC_CheckField, 8, 1, 0, 1, 74, 0, // Skip to: 23244 +/* 4299 */ MCD_OPC_Decode, 137, 19, 237, 1, // Opcode: VCRNF +/* 4304 */ MCD_OPC_FilterValue, 119, 38, 0, 0, // Skip to: 4347 +/* 4309 */ MCD_OPC_CheckPredicate, 30, 242, 73, 0, // Skip to: 23244 +/* 4314 */ MCD_OPC_CheckField, 36, 4, 0, 235, 73, 0, // Skip to: 23244 +/* 4321 */ MCD_OPC_CheckField, 24, 4, 0, 228, 73, 0, // Skip to: 23244 +/* 4328 */ MCD_OPC_CheckField, 11, 9, 0, 221, 73, 0, // Skip to: 23244 +/* 4335 */ MCD_OPC_CheckField, 8, 1, 0, 214, 73, 0, // Skip to: 23244 +/* 4342 */ MCD_OPC_Decode, 136, 19, 238, 1, // Opcode: VCP +/* 4347 */ MCD_OPC_FilterValue, 120, 24, 0, 0, // Skip to: 4376 +/* 4352 */ MCD_OPC_CheckPredicate, 30, 199, 73, 0, // Skip to: 23244 +/* 4357 */ MCD_OPC_CheckField, 24, 4, 0, 192, 73, 0, // Skip to: 23244 +/* 4364 */ MCD_OPC_CheckField, 8, 1, 0, 185, 73, 0, // Skip to: 23244 +/* 4371 */ MCD_OPC_Decode, 235, 21, 234, 1, // Opcode: VMP +/* 4376 */ MCD_OPC_FilterValue, 121, 24, 0, 0, // Skip to: 4405 +/* 4381 */ MCD_OPC_CheckPredicate, 30, 170, 73, 0, // Skip to: 23244 +/* 4386 */ MCD_OPC_CheckField, 24, 4, 0, 163, 73, 0, // Skip to: 23244 +/* 4393 */ MCD_OPC_CheckField, 8, 1, 0, 156, 73, 0, // Skip to: 23244 +/* 4400 */ MCD_OPC_Decode, 248, 21, 234, 1, // Opcode: VMSP +/* 4405 */ MCD_OPC_FilterValue, 122, 24, 0, 0, // Skip to: 4434 +/* 4410 */ MCD_OPC_CheckPredicate, 30, 141, 73, 0, // Skip to: 23244 +/* 4415 */ MCD_OPC_CheckField, 24, 4, 0, 134, 73, 0, // Skip to: 23244 +/* 4422 */ MCD_OPC_CheckField, 8, 1, 0, 127, 73, 0, // Skip to: 23244 +/* 4429 */ MCD_OPC_Decode, 151, 19, 234, 1, // Opcode: VDP +/* 4434 */ MCD_OPC_FilterValue, 123, 24, 0, 0, // Skip to: 4463 +/* 4439 */ MCD_OPC_CheckPredicate, 30, 112, 73, 0, // Skip to: 23244 +/* 4444 */ MCD_OPC_CheckField, 24, 4, 0, 105, 73, 0, // Skip to: 23244 +/* 4451 */ MCD_OPC_CheckField, 8, 1, 0, 98, 73, 0, // Skip to: 23244 +/* 4458 */ MCD_OPC_Decode, 177, 22, 234, 1, // Opcode: VRP +/* 4463 */ MCD_OPC_FilterValue, 124, 24, 0, 0, // Skip to: 4492 +/* 4468 */ MCD_OPC_CheckPredicate, 32, 83, 73, 0, // Skip to: 23244 +/* 4473 */ MCD_OPC_CheckField, 12, 16, 0, 76, 73, 0, // Skip to: 23244 +/* 4480 */ MCD_OPC_CheckField, 8, 1, 0, 69, 73, 0, // Skip to: 23244 +/* 4487 */ MCD_OPC_Decode, 196, 22, 239, 1, // Opcode: VSCSHP +/* 4492 */ MCD_OPC_FilterValue, 125, 31, 0, 0, // Skip to: 4528 +/* 4497 */ MCD_OPC_CheckPredicate, 32, 54, 73, 0, // Skip to: 23244 +/* 4502 */ MCD_OPC_CheckField, 24, 4, 0, 47, 73, 0, // Skip to: 23244 +/* 4509 */ MCD_OPC_CheckField, 12, 8, 0, 40, 73, 0, // Skip to: 23244 +/* 4516 */ MCD_OPC_CheckField, 8, 1, 0, 33, 73, 0, // Skip to: 23244 +/* 4523 */ MCD_OPC_Decode, 139, 19, 235, 1, // Opcode: VCSPH +/* 4528 */ MCD_OPC_FilterValue, 126, 23, 73, 0, // Skip to: 23244 +/* 4533 */ MCD_OPC_CheckPredicate, 30, 18, 73, 0, // Skip to: 23244 +/* 4538 */ MCD_OPC_CheckField, 24, 4, 0, 11, 73, 0, // Skip to: 23244 +/* 4545 */ MCD_OPC_CheckField, 8, 1, 0, 4, 73, 0, // Skip to: 23244 +/* 4552 */ MCD_OPC_Decode, 197, 22, 234, 1, // Opcode: VSDP +/* 4557 */ MCD_OPC_FilterValue, 231, 1, 88, 49, 0, // Skip to: 17195 +/* 4563 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 4566 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4588 +/* 4571 */ MCD_OPC_CheckPredicate, 34, 236, 72, 0, // Skip to: 23244 +/* 4576 */ MCD_OPC_CheckField, 8, 3, 0, 229, 72, 0, // Skip to: 23244 +/* 4583 */ MCD_OPC_Decode, 241, 20, 240, 1, // Opcode: VLEB +/* 4588 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4610 +/* 4593 */ MCD_OPC_CheckPredicate, 34, 214, 72, 0, // Skip to: 23244 +/* 4598 */ MCD_OPC_CheckField, 8, 3, 0, 207, 72, 0, // Skip to: 23244 +/* 4605 */ MCD_OPC_Decode, 249, 20, 213, 1, // Opcode: VLEH +/* 4610 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4632 +/* 4615 */ MCD_OPC_CheckPredicate, 34, 192, 72, 0, // Skip to: 23244 +/* 4620 */ MCD_OPC_CheckField, 8, 3, 0, 185, 72, 0, // Skip to: 23244 +/* 4627 */ MCD_OPC_Decode, 248, 20, 214, 1, // Opcode: VLEG +/* 4632 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 4654 +/* 4637 */ MCD_OPC_CheckPredicate, 34, 170, 72, 0, // Skip to: 23244 +/* 4642 */ MCD_OPC_CheckField, 8, 3, 0, 163, 72, 0, // Skip to: 23244 +/* 4649 */ MCD_OPC_Decode, 247, 20, 215, 1, // Opcode: VLEF +/* 4654 */ MCD_OPC_FilterValue, 4, 96, 0, 0, // Skip to: 4755 +/* 4659 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 4662 */ MCD_OPC_FilterValue, 0, 145, 72, 0, // Skip to: 23244 +/* 4667 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 4670 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4685 +/* 4675 */ MCD_OPC_CheckPredicate, 34, 65, 0, 0, // Skip to: 4745 +/* 4680 */ MCD_OPC_Decode, 143, 21, 216, 1, // Opcode: VLLEZB +/* 4685 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 4700 +/* 4690 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 4745 +/* 4695 */ MCD_OPC_Decode, 146, 21, 216, 1, // Opcode: VLLEZH +/* 4700 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 4715 +/* 4705 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 4745 +/* 4710 */ MCD_OPC_Decode, 144, 21, 216, 1, // Opcode: VLLEZF +/* 4715 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 4730 +/* 4720 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 4745 +/* 4725 */ MCD_OPC_Decode, 145, 21, 216, 1, // Opcode: VLLEZG +/* 4730 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 4745 +/* 4735 */ MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 4745 +/* 4740 */ MCD_OPC_Decode, 147, 21, 216, 1, // Opcode: VLLEZLF +/* 4745 */ MCD_OPC_CheckPredicate, 34, 62, 72, 0, // Skip to: 23244 +/* 4750 */ MCD_OPC_Decode, 142, 21, 217, 1, // Opcode: VLLEZ +/* 4755 */ MCD_OPC_FilterValue, 5, 81, 0, 0, // Skip to: 4841 +/* 4760 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 4763 */ MCD_OPC_FilterValue, 0, 44, 72, 0, // Skip to: 23244 +/* 4768 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 4771 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4786 +/* 4776 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 4831 +/* 4781 */ MCD_OPC_Decode, 157, 21, 216, 1, // Opcode: VLREPB +/* 4786 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 4801 +/* 4791 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 4831 +/* 4796 */ MCD_OPC_Decode, 160, 21, 216, 1, // Opcode: VLREPH +/* 4801 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 4816 +/* 4806 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 4831 +/* 4811 */ MCD_OPC_Decode, 158, 21, 216, 1, // Opcode: VLREPF +/* 4816 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 4831 +/* 4821 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 4831 +/* 4826 */ MCD_OPC_Decode, 159, 21, 216, 1, // Opcode: VLREPG +/* 4831 */ MCD_OPC_CheckPredicate, 34, 232, 71, 0, // Skip to: 23244 +/* 4836 */ MCD_OPC_Decode, 156, 21, 217, 1, // Opcode: VLREP +/* 4841 */ MCD_OPC_FilterValue, 6, 35, 0, 0, // Skip to: 4881 +/* 4846 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 4849 */ MCD_OPC_FilterValue, 0, 214, 71, 0, // Skip to: 23244 +/* 4854 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 4871 +/* 4859 */ MCD_OPC_CheckField, 12, 4, 0, 5, 0, 0, // Skip to: 4871 +/* 4866 */ MCD_OPC_Decode, 222, 20, 216, 1, // Opcode: VL +/* 4871 */ MCD_OPC_CheckPredicate, 34, 192, 71, 0, // Skip to: 23244 +/* 4876 */ MCD_OPC_Decode, 223, 20, 217, 1, // Opcode: VLAlign +/* 4881 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 4903 +/* 4886 */ MCD_OPC_CheckPredicate, 34, 177, 71, 0, // Skip to: 23244 +/* 4891 */ MCD_OPC_CheckField, 8, 3, 0, 170, 71, 0, // Skip to: 23244 +/* 4898 */ MCD_OPC_Decode, 224, 20, 217, 1, // Opcode: VLBB +/* 4903 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 4925 +/* 4908 */ MCD_OPC_CheckPredicate, 34, 155, 71, 0, // Skip to: 23244 +/* 4913 */ MCD_OPC_CheckField, 8, 3, 0, 148, 71, 0, // Skip to: 23244 +/* 4920 */ MCD_OPC_Decode, 226, 22, 217, 1, // Opcode: VSTEB +/* 4925 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 4947 +/* 4930 */ MCD_OPC_CheckPredicate, 34, 133, 71, 0, // Skip to: 23244 +/* 4935 */ MCD_OPC_CheckField, 8, 3, 0, 126, 71, 0, // Skip to: 23244 +/* 4942 */ MCD_OPC_Decode, 232, 22, 218, 1, // Opcode: VSTEH +/* 4947 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 4969 +/* 4952 */ MCD_OPC_CheckPredicate, 34, 111, 71, 0, // Skip to: 23244 +/* 4957 */ MCD_OPC_CheckField, 8, 3, 0, 104, 71, 0, // Skip to: 23244 +/* 4964 */ MCD_OPC_Decode, 231, 22, 219, 1, // Opcode: VSTEG +/* 4969 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 4991 +/* 4974 */ MCD_OPC_CheckPredicate, 34, 89, 71, 0, // Skip to: 23244 +/* 4979 */ MCD_OPC_CheckField, 8, 3, 0, 82, 71, 0, // Skip to: 23244 +/* 4986 */ MCD_OPC_Decode, 230, 22, 220, 1, // Opcode: VSTEF +/* 4991 */ MCD_OPC_FilterValue, 14, 35, 0, 0, // Skip to: 5031 +/* 4996 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 4999 */ MCD_OPC_FilterValue, 0, 64, 71, 0, // Skip to: 23244 +/* 5004 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 5021 +/* 5009 */ MCD_OPC_CheckField, 12, 4, 0, 5, 0, 0, // Skip to: 5021 +/* 5016 */ MCD_OPC_Decode, 219, 22, 216, 1, // Opcode: VST +/* 5021 */ MCD_OPC_CheckPredicate, 34, 42, 71, 0, // Skip to: 23244 +/* 5026 */ MCD_OPC_Decode, 220, 22, 217, 1, // Opcode: VSTAlign +/* 5031 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 5053 +/* 5036 */ MCD_OPC_CheckPredicate, 34, 27, 71, 0, // Skip to: 23244 +/* 5041 */ MCD_OPC_CheckField, 8, 2, 0, 20, 71, 0, // Skip to: 23244 +/* 5048 */ MCD_OPC_Decode, 199, 20, 241, 1, // Opcode: VGEG +/* 5053 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 5075 +/* 5058 */ MCD_OPC_CheckPredicate, 34, 5, 71, 0, // Skip to: 23244 +/* 5063 */ MCD_OPC_CheckField, 8, 2, 0, 254, 70, 0, // Skip to: 23244 +/* 5070 */ MCD_OPC_Decode, 198, 20, 242, 1, // Opcode: VGEF +/* 5075 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 5097 +/* 5080 */ MCD_OPC_CheckPredicate, 34, 239, 70, 0, // Skip to: 23244 +/* 5085 */ MCD_OPC_CheckField, 8, 2, 0, 232, 70, 0, // Skip to: 23244 +/* 5092 */ MCD_OPC_Decode, 191, 22, 243, 1, // Opcode: VSCEG +/* 5097 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 5119 +/* 5102 */ MCD_OPC_CheckPredicate, 34, 217, 70, 0, // Skip to: 23244 +/* 5107 */ MCD_OPC_CheckField, 8, 2, 0, 210, 70, 0, // Skip to: 23244 +/* 5114 */ MCD_OPC_Decode, 190, 22, 244, 1, // Opcode: VSCEF +/* 5119 */ MCD_OPC_FilterValue, 33, 89, 0, 0, // Skip to: 5213 +/* 5124 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 5127 */ MCD_OPC_FilterValue, 0, 192, 70, 0, // Skip to: 23244 +/* 5132 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 5135 */ MCD_OPC_FilterValue, 0, 184, 70, 0, // Skip to: 23244 +/* 5140 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 5143 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5158 +/* 5148 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 5203 +/* 5153 */ MCD_OPC_Decode, 131, 21, 245, 1, // Opcode: VLGVB +/* 5158 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5173 +/* 5163 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 5203 +/* 5168 */ MCD_OPC_Decode, 134, 21, 245, 1, // Opcode: VLGVH +/* 5173 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 5188 +/* 5178 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 5203 +/* 5183 */ MCD_OPC_Decode, 132, 21, 245, 1, // Opcode: VLGVF +/* 5188 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 5203 +/* 5193 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 5203 +/* 5198 */ MCD_OPC_Decode, 133, 21, 245, 1, // Opcode: VLGVG +/* 5203 */ MCD_OPC_CheckPredicate, 34, 116, 70, 0, // Skip to: 23244 +/* 5208 */ MCD_OPC_Decode, 130, 21, 246, 1, // Opcode: VLGV +/* 5213 */ MCD_OPC_FilterValue, 34, 81, 0, 0, // Skip to: 5299 +/* 5218 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 5221 */ MCD_OPC_FilterValue, 0, 98, 70, 0, // Skip to: 23244 +/* 5226 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 5229 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5244 +/* 5234 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 5289 +/* 5239 */ MCD_OPC_Decode, 164, 21, 247, 1, // Opcode: VLVGB +/* 5244 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5259 +/* 5249 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 5289 +/* 5254 */ MCD_OPC_Decode, 167, 21, 247, 1, // Opcode: VLVGH +/* 5259 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 5274 +/* 5264 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 5289 +/* 5269 */ MCD_OPC_Decode, 165, 21, 247, 1, // Opcode: VLVGF +/* 5274 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 5289 +/* 5279 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 5289 +/* 5284 */ MCD_OPC_Decode, 166, 21, 248, 1, // Opcode: VLVGG +/* 5289 */ MCD_OPC_CheckPredicate, 34, 30, 70, 0, // Skip to: 23244 +/* 5294 */ MCD_OPC_Decode, 163, 21, 249, 1, // Opcode: VLVG +/* 5299 */ MCD_OPC_FilterValue, 39, 17, 0, 0, // Skip to: 5321 +/* 5304 */ MCD_OPC_CheckPredicate, 34, 15, 70, 0, // Skip to: 23244 +/* 5309 */ MCD_OPC_CheckField, 8, 4, 0, 8, 70, 0, // Skip to: 23244 +/* 5316 */ MCD_OPC_Decode, 149, 11, 250, 1, // Opcode: LCBB +/* 5321 */ MCD_OPC_FilterValue, 48, 81, 0, 0, // Skip to: 5407 +/* 5326 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 5329 */ MCD_OPC_FilterValue, 0, 246, 69, 0, // Skip to: 23244 +/* 5334 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 5337 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5352 +/* 5342 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 5397 +/* 5347 */ MCD_OPC_Decode, 178, 19, 251, 1, // Opcode: VESLB +/* 5352 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5367 +/* 5357 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 5397 +/* 5362 */ MCD_OPC_Decode, 181, 19, 251, 1, // Opcode: VESLH +/* 5367 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 5382 +/* 5372 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 5397 +/* 5377 */ MCD_OPC_Decode, 179, 19, 251, 1, // Opcode: VESLF +/* 5382 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 5397 +/* 5387 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 5397 +/* 5392 */ MCD_OPC_Decode, 180, 19, 251, 1, // Opcode: VESLG +/* 5397 */ MCD_OPC_CheckPredicate, 34, 178, 69, 0, // Skip to: 23244 +/* 5402 */ MCD_OPC_Decode, 177, 19, 252, 1, // Opcode: VESL +/* 5407 */ MCD_OPC_FilterValue, 51, 81, 0, 0, // Skip to: 5493 +/* 5412 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 5415 */ MCD_OPC_FilterValue, 0, 160, 69, 0, // Skip to: 23244 +/* 5420 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 5423 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5438 +/* 5428 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 5483 +/* 5433 */ MCD_OPC_Decode, 168, 19, 251, 1, // Opcode: VERLLB +/* 5438 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5453 +/* 5443 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 5483 +/* 5448 */ MCD_OPC_Decode, 171, 19, 251, 1, // Opcode: VERLLH +/* 5453 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 5468 +/* 5458 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 5483 +/* 5463 */ MCD_OPC_Decode, 169, 19, 251, 1, // Opcode: VERLLF +/* 5468 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 5483 +/* 5473 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 5483 +/* 5478 */ MCD_OPC_Decode, 170, 19, 251, 1, // Opcode: VERLLG +/* 5483 */ MCD_OPC_CheckPredicate, 34, 92, 69, 0, // Skip to: 23244 +/* 5488 */ MCD_OPC_Decode, 167, 19, 252, 1, // Opcode: VERLL +/* 5493 */ MCD_OPC_FilterValue, 54, 35, 0, 0, // Skip to: 5533 +/* 5498 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 5501 */ MCD_OPC_FilterValue, 0, 74, 69, 0, // Skip to: 23244 +/* 5506 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 5523 +/* 5511 */ MCD_OPC_CheckField, 12, 4, 0, 5, 0, 0, // Skip to: 5523 +/* 5518 */ MCD_OPC_Decode, 148, 21, 253, 1, // Opcode: VLM +/* 5523 */ MCD_OPC_CheckPredicate, 34, 52, 69, 0, // Skip to: 23244 +/* 5528 */ MCD_OPC_Decode, 149, 21, 254, 1, // Opcode: VLMAlign +/* 5533 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 5562 +/* 5538 */ MCD_OPC_CheckPredicate, 34, 37, 69, 0, // Skip to: 23244 +/* 5543 */ MCD_OPC_CheckField, 12, 4, 0, 30, 69, 0, // Skip to: 23244 +/* 5550 */ MCD_OPC_CheckField, 8, 3, 0, 23, 69, 0, // Skip to: 23244 +/* 5557 */ MCD_OPC_Decode, 136, 21, 255, 1, // Opcode: VLL +/* 5562 */ MCD_OPC_FilterValue, 56, 81, 0, 0, // Skip to: 5648 +/* 5567 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 5570 */ MCD_OPC_FilterValue, 0, 5, 69, 0, // Skip to: 23244 +/* 5575 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 5578 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5593 +/* 5583 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 5638 +/* 5588 */ MCD_OPC_Decode, 198, 19, 251, 1, // Opcode: VESRLB +/* 5593 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5608 +/* 5598 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 5638 +/* 5603 */ MCD_OPC_Decode, 201, 19, 251, 1, // Opcode: VESRLH +/* 5608 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 5623 +/* 5613 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 5638 +/* 5618 */ MCD_OPC_Decode, 199, 19, 251, 1, // Opcode: VESRLF +/* 5623 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 5638 +/* 5628 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 5638 +/* 5633 */ MCD_OPC_Decode, 200, 19, 251, 1, // Opcode: VESRLG +/* 5638 */ MCD_OPC_CheckPredicate, 34, 193, 68, 0, // Skip to: 23244 +/* 5643 */ MCD_OPC_Decode, 197, 19, 252, 1, // Opcode: VESRL +/* 5648 */ MCD_OPC_FilterValue, 58, 81, 0, 0, // Skip to: 5734 +/* 5653 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 5656 */ MCD_OPC_FilterValue, 0, 175, 68, 0, // Skip to: 23244 +/* 5661 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 5664 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5679 +/* 5669 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 5724 +/* 5674 */ MCD_OPC_Decode, 188, 19, 251, 1, // Opcode: VESRAB +/* 5679 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5694 +/* 5684 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 5724 +/* 5689 */ MCD_OPC_Decode, 191, 19, 251, 1, // Opcode: VESRAH +/* 5694 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 5709 +/* 5699 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 5724 +/* 5704 */ MCD_OPC_Decode, 189, 19, 251, 1, // Opcode: VESRAF +/* 5709 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 5724 +/* 5714 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 5724 +/* 5719 */ MCD_OPC_Decode, 190, 19, 251, 1, // Opcode: VESRAG +/* 5724 */ MCD_OPC_CheckPredicate, 34, 107, 68, 0, // Skip to: 23244 +/* 5729 */ MCD_OPC_Decode, 187, 19, 252, 1, // Opcode: VESRA +/* 5734 */ MCD_OPC_FilterValue, 62, 35, 0, 0, // Skip to: 5774 +/* 5739 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 5742 */ MCD_OPC_FilterValue, 0, 89, 68, 0, // Skip to: 23244 +/* 5747 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 5764 +/* 5752 */ MCD_OPC_CheckField, 12, 4, 0, 5, 0, 0, // Skip to: 5764 +/* 5759 */ MCD_OPC_Decode, 238, 22, 253, 1, // Opcode: VSTM +/* 5764 */ MCD_OPC_CheckPredicate, 34, 67, 68, 0, // Skip to: 23244 +/* 5769 */ MCD_OPC_Decode, 239, 22, 254, 1, // Opcode: VSTMAlign +/* 5774 */ MCD_OPC_FilterValue, 63, 24, 0, 0, // Skip to: 5803 +/* 5779 */ MCD_OPC_CheckPredicate, 34, 52, 68, 0, // Skip to: 23244 +/* 5784 */ MCD_OPC_CheckField, 12, 4, 0, 45, 68, 0, // Skip to: 23244 +/* 5791 */ MCD_OPC_CheckField, 8, 3, 0, 38, 68, 0, // Skip to: 23244 +/* 5798 */ MCD_OPC_Decode, 237, 22, 255, 1, // Opcode: VSTL +/* 5803 */ MCD_OPC_FilterValue, 64, 24, 0, 0, // Skip to: 5832 +/* 5808 */ MCD_OPC_CheckPredicate, 34, 23, 68, 0, // Skip to: 23244 +/* 5813 */ MCD_OPC_CheckField, 32, 4, 0, 16, 68, 0, // Skip to: 23244 +/* 5820 */ MCD_OPC_CheckField, 8, 3, 0, 9, 68, 0, // Skip to: 23244 +/* 5827 */ MCD_OPC_Decode, 250, 20, 128, 2, // Opcode: VLEIB +/* 5832 */ MCD_OPC_FilterValue, 65, 24, 0, 0, // Skip to: 5861 +/* 5837 */ MCD_OPC_CheckPredicate, 34, 250, 67, 0, // Skip to: 23244 +/* 5842 */ MCD_OPC_CheckField, 32, 4, 0, 243, 67, 0, // Skip to: 23244 +/* 5849 */ MCD_OPC_CheckField, 8, 3, 0, 236, 67, 0, // Skip to: 23244 +/* 5856 */ MCD_OPC_Decode, 253, 20, 129, 2, // Opcode: VLEIH +/* 5861 */ MCD_OPC_FilterValue, 66, 24, 0, 0, // Skip to: 5890 +/* 5866 */ MCD_OPC_CheckPredicate, 34, 221, 67, 0, // Skip to: 23244 +/* 5871 */ MCD_OPC_CheckField, 32, 4, 0, 214, 67, 0, // Skip to: 23244 +/* 5878 */ MCD_OPC_CheckField, 8, 3, 0, 207, 67, 0, // Skip to: 23244 +/* 5885 */ MCD_OPC_Decode, 252, 20, 130, 2, // Opcode: VLEIG +/* 5890 */ MCD_OPC_FilterValue, 67, 24, 0, 0, // Skip to: 5919 +/* 5895 */ MCD_OPC_CheckPredicate, 34, 192, 67, 0, // Skip to: 23244 +/* 5900 */ MCD_OPC_CheckField, 32, 4, 0, 185, 67, 0, // Skip to: 23244 +/* 5907 */ MCD_OPC_CheckField, 8, 3, 0, 178, 67, 0, // Skip to: 23244 +/* 5914 */ MCD_OPC_Decode, 251, 20, 131, 2, // Opcode: VLEIF +/* 5919 */ MCD_OPC_FilterValue, 68, 69, 0, 0, // Skip to: 5993 +/* 5924 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 5927 */ MCD_OPC_FilterValue, 0, 160, 67, 0, // Skip to: 23244 +/* 5932 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 5935 */ MCD_OPC_FilterValue, 0, 152, 67, 0, // Skip to: 23244 +/* 5940 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 5943 */ MCD_OPC_FilterValue, 0, 144, 67, 0, // Skip to: 23244 +/* 5948 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 5951 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5966 +/* 5956 */ MCD_OPC_CheckPredicate, 34, 22, 0, 0, // Skip to: 5983 +/* 5961 */ MCD_OPC_Decode, 165, 23, 132, 2, // Opcode: VZERO +/* 5966 */ MCD_OPC_FilterValue, 255, 255, 3, 10, 0, 0, // Skip to: 5983 +/* 5973 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 5983 +/* 5978 */ MCD_OPC_Decode, 138, 22, 132, 2, // Opcode: VONE +/* 5983 */ MCD_OPC_CheckPredicate, 34, 104, 67, 0, // Skip to: 23244 +/* 5988 */ MCD_OPC_Decode, 197, 20, 133, 2, // Opcode: VGBM +/* 5993 */ MCD_OPC_FilterValue, 69, 89, 0, 0, // Skip to: 6087 +/* 5998 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 6001 */ MCD_OPC_FilterValue, 0, 86, 67, 0, // Skip to: 23244 +/* 6006 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 6009 */ MCD_OPC_FilterValue, 0, 78, 67, 0, // Skip to: 23244 +/* 6014 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 6017 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6032 +/* 6022 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 6077 +/* 6027 */ MCD_OPC_Decode, 173, 22, 134, 2, // Opcode: VREPIB +/* 6032 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6047 +/* 6037 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 6077 +/* 6042 */ MCD_OPC_Decode, 176, 22, 134, 2, // Opcode: VREPIH +/* 6047 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6062 +/* 6052 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 6077 +/* 6057 */ MCD_OPC_Decode, 174, 22, 134, 2, // Opcode: VREPIF +/* 6062 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 6077 +/* 6067 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 6077 +/* 6072 */ MCD_OPC_Decode, 175, 22, 134, 2, // Opcode: VREPIG +/* 6077 */ MCD_OPC_CheckPredicate, 34, 10, 67, 0, // Skip to: 23244 +/* 6082 */ MCD_OPC_Decode, 172, 22, 135, 2, // Opcode: VREPI +/* 6087 */ MCD_OPC_FilterValue, 70, 89, 0, 0, // Skip to: 6181 +/* 6092 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 6095 */ MCD_OPC_FilterValue, 0, 248, 66, 0, // Skip to: 23244 +/* 6100 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 6103 */ MCD_OPC_FilterValue, 0, 240, 66, 0, // Skip to: 23244 +/* 6108 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 6111 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6126 +/* 6116 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 6171 +/* 6121 */ MCD_OPC_Decode, 211, 20, 136, 2, // Opcode: VGMB +/* 6126 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6141 +/* 6131 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 6171 +/* 6136 */ MCD_OPC_Decode, 214, 20, 136, 2, // Opcode: VGMH +/* 6141 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6156 +/* 6146 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 6171 +/* 6151 */ MCD_OPC_Decode, 212, 20, 136, 2, // Opcode: VGMF +/* 6156 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 6171 +/* 6161 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 6171 +/* 6166 */ MCD_OPC_Decode, 213, 20, 136, 2, // Opcode: VGMG +/* 6171 */ MCD_OPC_CheckPredicate, 34, 172, 66, 0, // Skip to: 23244 +/* 6176 */ MCD_OPC_Decode, 210, 20, 137, 2, // Opcode: VGM +/* 6181 */ MCD_OPC_FilterValue, 74, 99, 0, 0, // Skip to: 6285 +/* 6186 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 6189 */ MCD_OPC_FilterValue, 0, 154, 66, 0, // Skip to: 23244 +/* 6194 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 6197 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6212 +/* 6202 */ MCD_OPC_CheckPredicate, 35, 68, 0, 0, // Skip to: 6275 +/* 6207 */ MCD_OPC_Decode, 196, 20, 138, 2, // Opcode: VFTCISB +/* 6212 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 6227 +/* 6217 */ MCD_OPC_CheckPredicate, 34, 53, 0, 0, // Skip to: 6275 +/* 6222 */ MCD_OPC_Decode, 195, 20, 138, 2, // Opcode: VFTCIDB +/* 6227 */ MCD_OPC_FilterValue, 130, 1, 10, 0, 0, // Skip to: 6243 +/* 6233 */ MCD_OPC_CheckPredicate, 35, 37, 0, 0, // Skip to: 6275 +/* 6238 */ MCD_OPC_Decode, 143, 24, 139, 2, // Opcode: WFTCISB +/* 6243 */ MCD_OPC_FilterValue, 131, 1, 10, 0, 0, // Skip to: 6259 +/* 6249 */ MCD_OPC_CheckPredicate, 34, 21, 0, 0, // Skip to: 6275 +/* 6254 */ MCD_OPC_Decode, 142, 24, 140, 2, // Opcode: WFTCIDB +/* 6259 */ MCD_OPC_FilterValue, 132, 1, 10, 0, 0, // Skip to: 6275 +/* 6265 */ MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 6275 +/* 6270 */ MCD_OPC_Decode, 144, 24, 138, 2, // Opcode: WFTCIXB +/* 6275 */ MCD_OPC_CheckPredicate, 34, 68, 66, 0, // Skip to: 23244 +/* 6280 */ MCD_OPC_Decode, 194, 20, 141, 2, // Opcode: VFTCI +/* 6285 */ MCD_OPC_FilterValue, 77, 81, 0, 0, // Skip to: 6371 +/* 6290 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 6293 */ MCD_OPC_FilterValue, 0, 50, 66, 0, // Skip to: 23244 +/* 6298 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 6301 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6316 +/* 6306 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 6361 +/* 6311 */ MCD_OPC_Decode, 168, 22, 142, 2, // Opcode: VREPB +/* 6316 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6331 +/* 6321 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 6361 +/* 6326 */ MCD_OPC_Decode, 171, 22, 142, 2, // Opcode: VREPH +/* 6331 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6346 +/* 6336 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 6361 +/* 6341 */ MCD_OPC_Decode, 169, 22, 142, 2, // Opcode: VREPF +/* 6346 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 6361 +/* 6351 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 6361 +/* 6356 */ MCD_OPC_Decode, 170, 22, 142, 2, // Opcode: VREPG +/* 6361 */ MCD_OPC_CheckPredicate, 34, 238, 65, 0, // Skip to: 23244 +/* 6366 */ MCD_OPC_Decode, 167, 22, 143, 2, // Opcode: VREP +/* 6371 */ MCD_OPC_FilterValue, 80, 89, 0, 0, // Skip to: 6465 +/* 6376 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 6379 */ MCD_OPC_FilterValue, 0, 220, 65, 0, // Skip to: 23244 +/* 6384 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 6387 */ MCD_OPC_FilterValue, 0, 212, 65, 0, // Skip to: 23244 +/* 6392 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 6395 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6410 +/* 6400 */ MCD_OPC_CheckPredicate, 35, 50, 0, 0, // Skip to: 6455 +/* 6405 */ MCD_OPC_Decode, 162, 22, 144, 2, // Opcode: VPOPCTB +/* 6410 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6425 +/* 6415 */ MCD_OPC_CheckPredicate, 35, 35, 0, 0, // Skip to: 6455 +/* 6420 */ MCD_OPC_Decode, 165, 22, 144, 2, // Opcode: VPOPCTH +/* 6425 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6440 +/* 6430 */ MCD_OPC_CheckPredicate, 35, 20, 0, 0, // Skip to: 6455 +/* 6435 */ MCD_OPC_Decode, 163, 22, 144, 2, // Opcode: VPOPCTF +/* 6440 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 6455 +/* 6445 */ MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 6455 +/* 6450 */ MCD_OPC_Decode, 164, 22, 144, 2, // Opcode: VPOPCTG +/* 6455 */ MCD_OPC_CheckPredicate, 34, 144, 65, 0, // Skip to: 23244 +/* 6460 */ MCD_OPC_Decode, 161, 22, 145, 2, // Opcode: VPOPCT +/* 6465 */ MCD_OPC_FilterValue, 82, 89, 0, 0, // Skip to: 6559 +/* 6470 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 6473 */ MCD_OPC_FilterValue, 0, 126, 65, 0, // Skip to: 23244 +/* 6478 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 6481 */ MCD_OPC_FilterValue, 0, 118, 65, 0, // Skip to: 23244 +/* 6486 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 6489 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6504 +/* 6494 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 6549 +/* 6499 */ MCD_OPC_Decode, 141, 19, 144, 2, // Opcode: VCTZB +/* 6504 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6519 +/* 6509 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 6549 +/* 6514 */ MCD_OPC_Decode, 144, 19, 144, 2, // Opcode: VCTZH +/* 6519 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6534 +/* 6524 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 6549 +/* 6529 */ MCD_OPC_Decode, 142, 19, 144, 2, // Opcode: VCTZF +/* 6534 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 6549 +/* 6539 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 6549 +/* 6544 */ MCD_OPC_Decode, 143, 19, 144, 2, // Opcode: VCTZG +/* 6549 */ MCD_OPC_CheckPredicate, 34, 50, 65, 0, // Skip to: 23244 +/* 6554 */ MCD_OPC_Decode, 140, 19, 145, 2, // Opcode: VCTZ +/* 6559 */ MCD_OPC_FilterValue, 83, 89, 0, 0, // Skip to: 6653 +/* 6564 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 6567 */ MCD_OPC_FilterValue, 0, 32, 65, 0, // Skip to: 23244 +/* 6572 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 6575 */ MCD_OPC_FilterValue, 0, 24, 65, 0, // Skip to: 23244 +/* 6580 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 6583 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6598 +/* 6588 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 6643 +/* 6593 */ MCD_OPC_Decode, 130, 19, 144, 2, // Opcode: VCLZB +/* 6598 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6613 +/* 6603 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 6643 +/* 6608 */ MCD_OPC_Decode, 134, 19, 144, 2, // Opcode: VCLZH +/* 6613 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6628 +/* 6618 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 6643 +/* 6623 */ MCD_OPC_Decode, 132, 19, 144, 2, // Opcode: VCLZF +/* 6628 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 6643 +/* 6633 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 6643 +/* 6638 */ MCD_OPC_Decode, 133, 19, 144, 2, // Opcode: VCLZG +/* 6643 */ MCD_OPC_CheckPredicate, 34, 212, 64, 0, // Skip to: 23244 +/* 6648 */ MCD_OPC_Decode, 129, 19, 145, 2, // Opcode: VCLZ +/* 6653 */ MCD_OPC_FilterValue, 86, 24, 0, 0, // Skip to: 6682 +/* 6658 */ MCD_OPC_CheckPredicate, 34, 197, 64, 0, // Skip to: 23244 +/* 6663 */ MCD_OPC_CheckField, 12, 20, 0, 190, 64, 0, // Skip to: 23244 +/* 6670 */ MCD_OPC_CheckField, 8, 2, 0, 183, 64, 0, // Skip to: 23244 +/* 6677 */ MCD_OPC_Decode, 155, 21, 144, 2, // Opcode: VLR +/* 6682 */ MCD_OPC_FilterValue, 92, 133, 0, 0, // Skip to: 6820 +/* 6687 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 6690 */ MCD_OPC_FilterValue, 0, 165, 64, 0, // Skip to: 23244 +/* 6695 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 6698 */ MCD_OPC_FilterValue, 0, 157, 64, 0, // Skip to: 23244 +/* 6703 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 6706 */ MCD_OPC_FilterValue, 0, 149, 64, 0, // Skip to: 23244 +/* 6711 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 6714 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 6746 +/* 6719 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 6736 +/* 6724 */ MCD_OPC_CheckField, 20, 4, 1, 5, 0, 0, // Skip to: 6736 +/* 6731 */ MCD_OPC_Decode, 217, 20, 144, 2, // Opcode: VISTRBS +/* 6736 */ MCD_OPC_CheckPredicate, 34, 69, 0, 0, // Skip to: 6810 +/* 6741 */ MCD_OPC_Decode, 216, 20, 226, 1, // Opcode: VISTRB +/* 6746 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 6778 +/* 6751 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 6768 +/* 6756 */ MCD_OPC_CheckField, 20, 4, 1, 5, 0, 0, // Skip to: 6768 +/* 6763 */ MCD_OPC_Decode, 221, 20, 144, 2, // Opcode: VISTRHS +/* 6768 */ MCD_OPC_CheckPredicate, 34, 37, 0, 0, // Skip to: 6810 +/* 6773 */ MCD_OPC_Decode, 220, 20, 226, 1, // Opcode: VISTRH +/* 6778 */ MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 6810 +/* 6783 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 6800 +/* 6788 */ MCD_OPC_CheckField, 20, 4, 1, 5, 0, 0, // Skip to: 6800 +/* 6795 */ MCD_OPC_Decode, 219, 20, 144, 2, // Opcode: VISTRFS +/* 6800 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 6810 +/* 6805 */ MCD_OPC_Decode, 218, 20, 226, 1, // Opcode: VISTRF +/* 6810 */ MCD_OPC_CheckPredicate, 34, 45, 64, 0, // Skip to: 23244 +/* 6815 */ MCD_OPC_Decode, 215, 20, 146, 2, // Opcode: VISTR +/* 6820 */ MCD_OPC_FilterValue, 95, 74, 0, 0, // Skip to: 6899 +/* 6825 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 6828 */ MCD_OPC_FilterValue, 0, 27, 64, 0, // Skip to: 23244 +/* 6833 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 6836 */ MCD_OPC_FilterValue, 0, 19, 64, 0, // Skip to: 23244 +/* 6841 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 6844 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6859 +/* 6849 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 6889 +/* 6854 */ MCD_OPC_Decode, 199, 22, 144, 2, // Opcode: VSEGB +/* 6859 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6874 +/* 6864 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 6889 +/* 6869 */ MCD_OPC_Decode, 201, 22, 144, 2, // Opcode: VSEGH +/* 6874 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6889 +/* 6879 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 6889 +/* 6884 */ MCD_OPC_Decode, 200, 22, 144, 2, // Opcode: VSEGF +/* 6889 */ MCD_OPC_CheckPredicate, 34, 222, 63, 0, // Skip to: 23244 +/* 6894 */ MCD_OPC_Decode, 198, 22, 145, 2, // Opcode: VSEG +/* 6899 */ MCD_OPC_FilterValue, 96, 89, 0, 0, // Skip to: 6993 +/* 6904 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 6907 */ MCD_OPC_FilterValue, 0, 204, 63, 0, // Skip to: 23244 +/* 6912 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 6915 */ MCD_OPC_FilterValue, 0, 196, 63, 0, // Skip to: 23244 +/* 6920 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 6923 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6938 +/* 6928 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 6983 +/* 6933 */ MCD_OPC_Decode, 242, 21, 239, 1, // Opcode: VMRLB +/* 6938 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6953 +/* 6943 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 6983 +/* 6948 */ MCD_OPC_Decode, 245, 21, 239, 1, // Opcode: VMRLH +/* 6953 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6968 +/* 6958 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 6983 +/* 6963 */ MCD_OPC_Decode, 243, 21, 239, 1, // Opcode: VMRLF +/* 6968 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 6983 +/* 6973 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 6983 +/* 6978 */ MCD_OPC_Decode, 244, 21, 239, 1, // Opcode: VMRLG +/* 6983 */ MCD_OPC_CheckPredicate, 34, 128, 63, 0, // Skip to: 23244 +/* 6988 */ MCD_OPC_Decode, 241, 21, 147, 2, // Opcode: VMRL +/* 6993 */ MCD_OPC_FilterValue, 97, 89, 0, 0, // Skip to: 7087 +/* 6998 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 7001 */ MCD_OPC_FilterValue, 0, 110, 63, 0, // Skip to: 23244 +/* 7006 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 7009 */ MCD_OPC_FilterValue, 0, 102, 63, 0, // Skip to: 23244 +/* 7014 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7017 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7032 +/* 7022 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 7077 +/* 7027 */ MCD_OPC_Decode, 237, 21, 239, 1, // Opcode: VMRHB +/* 7032 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7047 +/* 7037 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 7077 +/* 7042 */ MCD_OPC_Decode, 240, 21, 239, 1, // Opcode: VMRHH +/* 7047 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7062 +/* 7052 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 7077 +/* 7057 */ MCD_OPC_Decode, 238, 21, 239, 1, // Opcode: VMRHF +/* 7062 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 7077 +/* 7067 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 7077 +/* 7072 */ MCD_OPC_Decode, 239, 21, 239, 1, // Opcode: VMRHG +/* 7077 */ MCD_OPC_CheckPredicate, 34, 34, 63, 0, // Skip to: 23244 +/* 7082 */ MCD_OPC_Decode, 236, 21, 147, 2, // Opcode: VMRH +/* 7087 */ MCD_OPC_FilterValue, 98, 24, 0, 0, // Skip to: 7116 +/* 7092 */ MCD_OPC_CheckPredicate, 34, 19, 63, 0, // Skip to: 23244 +/* 7097 */ MCD_OPC_CheckField, 12, 16, 0, 12, 63, 0, // Skip to: 23244 +/* 7104 */ MCD_OPC_CheckField, 8, 3, 0, 5, 63, 0, // Skip to: 23244 +/* 7111 */ MCD_OPC_Decode, 168, 21, 148, 2, // Opcode: VLVGP +/* 7116 */ MCD_OPC_FilterValue, 100, 59, 0, 0, // Skip to: 7180 +/* 7121 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 7124 */ MCD_OPC_FilterValue, 0, 243, 62, 0, // Skip to: 23244 +/* 7129 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 7132 */ MCD_OPC_FilterValue, 0, 235, 62, 0, // Skip to: 23244 +/* 7137 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7140 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7155 +/* 7145 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 7170 +/* 7150 */ MCD_OPC_Decode, 135, 23, 239, 1, // Opcode: VSUMB +/* 7155 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7170 +/* 7160 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 7170 +/* 7165 */ MCD_OPC_Decode, 139, 23, 239, 1, // Opcode: VSUMH +/* 7170 */ MCD_OPC_CheckPredicate, 34, 197, 62, 0, // Skip to: 23244 +/* 7175 */ MCD_OPC_Decode, 134, 23, 147, 2, // Opcode: VSUM +/* 7180 */ MCD_OPC_FilterValue, 101, 59, 0, 0, // Skip to: 7244 +/* 7185 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 7188 */ MCD_OPC_FilterValue, 0, 179, 62, 0, // Skip to: 23244 +/* 7193 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 7196 */ MCD_OPC_FilterValue, 0, 171, 62, 0, // Skip to: 23244 +/* 7201 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7204 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7219 +/* 7209 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 7234 +/* 7214 */ MCD_OPC_Decode, 138, 23, 239, 1, // Opcode: VSUMGH +/* 7219 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7234 +/* 7224 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 7234 +/* 7229 */ MCD_OPC_Decode, 137, 23, 239, 1, // Opcode: VSUMGF +/* 7234 */ MCD_OPC_CheckPredicate, 34, 133, 62, 0, // Skip to: 23244 +/* 7239 */ MCD_OPC_Decode, 136, 23, 147, 2, // Opcode: VSUMG +/* 7244 */ MCD_OPC_FilterValue, 102, 24, 0, 0, // Skip to: 7273 +/* 7249 */ MCD_OPC_CheckPredicate, 34, 118, 62, 0, // Skip to: 23244 +/* 7254 */ MCD_OPC_CheckField, 12, 16, 0, 111, 62, 0, // Skip to: 23244 +/* 7261 */ MCD_OPC_CheckField, 8, 1, 0, 104, 62, 0, // Skip to: 23244 +/* 7268 */ MCD_OPC_Decode, 250, 18, 239, 1, // Opcode: VCKSM +/* 7273 */ MCD_OPC_FilterValue, 103, 59, 0, 0, // Skip to: 7337 +/* 7278 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 7281 */ MCD_OPC_FilterValue, 0, 86, 62, 0, // Skip to: 23244 +/* 7286 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 7289 */ MCD_OPC_FilterValue, 0, 78, 62, 0, // Skip to: 23244 +/* 7294 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7297 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7312 +/* 7302 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 7327 +/* 7307 */ MCD_OPC_Decode, 141, 23, 239, 1, // Opcode: VSUMQF +/* 7312 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 7327 +/* 7317 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 7327 +/* 7322 */ MCD_OPC_Decode, 142, 23, 239, 1, // Opcode: VSUMQG +/* 7327 */ MCD_OPC_CheckPredicate, 34, 40, 62, 0, // Skip to: 23244 +/* 7332 */ MCD_OPC_Decode, 140, 23, 147, 2, // Opcode: VSUMQ +/* 7337 */ MCD_OPC_FilterValue, 104, 24, 0, 0, // Skip to: 7366 +/* 7342 */ MCD_OPC_CheckPredicate, 34, 25, 62, 0, // Skip to: 23244 +/* 7347 */ MCD_OPC_CheckField, 12, 16, 0, 18, 62, 0, // Skip to: 23244 +/* 7354 */ MCD_OPC_CheckField, 8, 1, 0, 11, 62, 0, // Skip to: 23244 +/* 7361 */ MCD_OPC_Decode, 131, 22, 239, 1, // Opcode: VN +/* 7366 */ MCD_OPC_FilterValue, 105, 24, 0, 0, // Skip to: 7395 +/* 7371 */ MCD_OPC_CheckPredicate, 34, 252, 61, 0, // Skip to: 23244 +/* 7376 */ MCD_OPC_CheckField, 12, 16, 0, 245, 61, 0, // Skip to: 23244 +/* 7383 */ MCD_OPC_CheckField, 8, 1, 0, 238, 61, 0, // Skip to: 23244 +/* 7390 */ MCD_OPC_Decode, 132, 22, 239, 1, // Opcode: VNC +/* 7395 */ MCD_OPC_FilterValue, 106, 24, 0, 0, // Skip to: 7424 +/* 7400 */ MCD_OPC_CheckPredicate, 34, 223, 61, 0, // Skip to: 23244 +/* 7405 */ MCD_OPC_CheckField, 12, 16, 0, 216, 61, 0, // Skip to: 23244 +/* 7412 */ MCD_OPC_CheckField, 8, 1, 0, 209, 61, 0, // Skip to: 23244 +/* 7419 */ MCD_OPC_Decode, 136, 22, 239, 1, // Opcode: VO +/* 7424 */ MCD_OPC_FilterValue, 107, 24, 0, 0, // Skip to: 7453 +/* 7429 */ MCD_OPC_CheckPredicate, 34, 194, 61, 0, // Skip to: 23244 +/* 7434 */ MCD_OPC_CheckField, 12, 16, 0, 187, 61, 0, // Skip to: 23244 +/* 7441 */ MCD_OPC_CheckField, 8, 1, 0, 180, 61, 0, // Skip to: 23244 +/* 7448 */ MCD_OPC_Decode, 134, 22, 239, 1, // Opcode: VNO +/* 7453 */ MCD_OPC_FilterValue, 108, 24, 0, 0, // Skip to: 7482 +/* 7458 */ MCD_OPC_CheckPredicate, 35, 165, 61, 0, // Skip to: 23244 +/* 7463 */ MCD_OPC_CheckField, 12, 16, 0, 158, 61, 0, // Skip to: 23244 +/* 7470 */ MCD_OPC_CheckField, 8, 1, 0, 151, 61, 0, // Skip to: 23244 +/* 7477 */ MCD_OPC_Decode, 135, 22, 239, 1, // Opcode: VNX +/* 7482 */ MCD_OPC_FilterValue, 109, 24, 0, 0, // Skip to: 7511 +/* 7487 */ MCD_OPC_CheckPredicate, 34, 136, 61, 0, // Skip to: 23244 +/* 7492 */ MCD_OPC_CheckField, 12, 16, 0, 129, 61, 0, // Skip to: 23244 +/* 7499 */ MCD_OPC_CheckField, 8, 1, 0, 122, 61, 0, // Skip to: 23244 +/* 7506 */ MCD_OPC_Decode, 164, 23, 239, 1, // Opcode: VX +/* 7511 */ MCD_OPC_FilterValue, 110, 24, 0, 0, // Skip to: 7540 +/* 7516 */ MCD_OPC_CheckPredicate, 35, 107, 61, 0, // Skip to: 23244 +/* 7521 */ MCD_OPC_CheckField, 12, 16, 0, 100, 61, 0, // Skip to: 23244 +/* 7528 */ MCD_OPC_CheckField, 8, 1, 0, 93, 61, 0, // Skip to: 23244 +/* 7535 */ MCD_OPC_Decode, 133, 22, 239, 1, // Opcode: VNN +/* 7540 */ MCD_OPC_FilterValue, 111, 24, 0, 0, // Skip to: 7569 +/* 7545 */ MCD_OPC_CheckPredicate, 35, 78, 61, 0, // Skip to: 23244 +/* 7550 */ MCD_OPC_CheckField, 12, 16, 0, 71, 61, 0, // Skip to: 23244 +/* 7557 */ MCD_OPC_CheckField, 8, 1, 0, 64, 61, 0, // Skip to: 23244 +/* 7564 */ MCD_OPC_Decode, 137, 22, 239, 1, // Opcode: VOC +/* 7569 */ MCD_OPC_FilterValue, 112, 89, 0, 0, // Skip to: 7663 +/* 7574 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 7577 */ MCD_OPC_FilterValue, 0, 46, 61, 0, // Skip to: 23244 +/* 7582 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 7585 */ MCD_OPC_FilterValue, 0, 38, 61, 0, // Skip to: 23244 +/* 7590 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7593 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7608 +/* 7598 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 7653 +/* 7603 */ MCD_OPC_Decode, 183, 19, 239, 1, // Opcode: VESLVB +/* 7608 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7623 +/* 7613 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 7653 +/* 7618 */ MCD_OPC_Decode, 186, 19, 239, 1, // Opcode: VESLVH +/* 7623 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7638 +/* 7628 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 7653 +/* 7633 */ MCD_OPC_Decode, 184, 19, 239, 1, // Opcode: VESLVF +/* 7638 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 7653 +/* 7643 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 7653 +/* 7648 */ MCD_OPC_Decode, 185, 19, 239, 1, // Opcode: VESLVG +/* 7653 */ MCD_OPC_CheckPredicate, 34, 226, 60, 0, // Skip to: 23244 +/* 7658 */ MCD_OPC_Decode, 182, 19, 147, 2, // Opcode: VESLV +/* 7663 */ MCD_OPC_FilterValue, 114, 89, 0, 0, // Skip to: 7757 +/* 7668 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 7671 */ MCD_OPC_FilterValue, 0, 208, 60, 0, // Skip to: 23244 +/* 7676 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 7679 */ MCD_OPC_FilterValue, 0, 200, 60, 0, // Skip to: 23244 +/* 7684 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7687 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7702 +/* 7692 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 7747 +/* 7697 */ MCD_OPC_Decode, 163, 19, 149, 2, // Opcode: VERIMB +/* 7702 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7717 +/* 7707 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 7747 +/* 7712 */ MCD_OPC_Decode, 166, 19, 149, 2, // Opcode: VERIMH +/* 7717 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7732 +/* 7722 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 7747 +/* 7727 */ MCD_OPC_Decode, 164, 19, 149, 2, // Opcode: VERIMF +/* 7732 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 7747 +/* 7737 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 7747 +/* 7742 */ MCD_OPC_Decode, 165, 19, 149, 2, // Opcode: VERIMG +/* 7747 */ MCD_OPC_CheckPredicate, 34, 132, 60, 0, // Skip to: 23244 +/* 7752 */ MCD_OPC_Decode, 162, 19, 150, 2, // Opcode: VERIM +/* 7757 */ MCD_OPC_FilterValue, 115, 89, 0, 0, // Skip to: 7851 +/* 7762 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 7765 */ MCD_OPC_FilterValue, 0, 114, 60, 0, // Skip to: 23244 +/* 7770 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 7773 */ MCD_OPC_FilterValue, 0, 106, 60, 0, // Skip to: 23244 +/* 7778 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7781 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7796 +/* 7786 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 7841 +/* 7791 */ MCD_OPC_Decode, 173, 19, 239, 1, // Opcode: VERLLVB +/* 7796 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7811 +/* 7801 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 7841 +/* 7806 */ MCD_OPC_Decode, 176, 19, 239, 1, // Opcode: VERLLVH +/* 7811 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7826 +/* 7816 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 7841 +/* 7821 */ MCD_OPC_Decode, 174, 19, 239, 1, // Opcode: VERLLVF +/* 7826 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 7841 +/* 7831 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 7841 +/* 7836 */ MCD_OPC_Decode, 175, 19, 239, 1, // Opcode: VERLLVG +/* 7841 */ MCD_OPC_CheckPredicate, 34, 38, 60, 0, // Skip to: 23244 +/* 7846 */ MCD_OPC_Decode, 172, 19, 147, 2, // Opcode: VERLLV +/* 7851 */ MCD_OPC_FilterValue, 116, 24, 0, 0, // Skip to: 7880 +/* 7856 */ MCD_OPC_CheckPredicate, 34, 23, 60, 0, // Skip to: 23244 +/* 7861 */ MCD_OPC_CheckField, 12, 16, 0, 16, 60, 0, // Skip to: 23244 +/* 7868 */ MCD_OPC_CheckField, 8, 1, 0, 9, 60, 0, // Skip to: 23244 +/* 7875 */ MCD_OPC_Decode, 206, 22, 239, 1, // Opcode: VSL +/* 7880 */ MCD_OPC_FilterValue, 117, 24, 0, 0, // Skip to: 7909 +/* 7885 */ MCD_OPC_CheckPredicate, 34, 250, 59, 0, // Skip to: 23244 +/* 7890 */ MCD_OPC_CheckField, 12, 16, 0, 243, 59, 0, // Skip to: 23244 +/* 7897 */ MCD_OPC_CheckField, 8, 1, 0, 236, 59, 0, // Skip to: 23244 +/* 7904 */ MCD_OPC_Decode, 207, 22, 239, 1, // Opcode: VSLB +/* 7909 */ MCD_OPC_FilterValue, 119, 31, 0, 0, // Skip to: 7945 +/* 7914 */ MCD_OPC_CheckPredicate, 34, 221, 59, 0, // Skip to: 23244 +/* 7919 */ MCD_OPC_CheckField, 24, 4, 0, 214, 59, 0, // Skip to: 23244 +/* 7926 */ MCD_OPC_CheckField, 12, 4, 0, 207, 59, 0, // Skip to: 23244 +/* 7933 */ MCD_OPC_CheckField, 8, 1, 0, 200, 59, 0, // Skip to: 23244 +/* 7940 */ MCD_OPC_Decode, 209, 22, 151, 2, // Opcode: VSLDB +/* 7945 */ MCD_OPC_FilterValue, 120, 89, 0, 0, // Skip to: 8039 +/* 7950 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 7953 */ MCD_OPC_FilterValue, 0, 182, 59, 0, // Skip to: 23244 +/* 7958 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 7961 */ MCD_OPC_FilterValue, 0, 174, 59, 0, // Skip to: 23244 +/* 7966 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7969 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7984 +/* 7974 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 8029 +/* 7979 */ MCD_OPC_Decode, 203, 19, 239, 1, // Opcode: VESRLVB +/* 7984 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7999 +/* 7989 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 8029 +/* 7994 */ MCD_OPC_Decode, 206, 19, 239, 1, // Opcode: VESRLVH +/* 7999 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8014 +/* 8004 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 8029 +/* 8009 */ MCD_OPC_Decode, 204, 19, 239, 1, // Opcode: VESRLVF +/* 8014 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 8029 +/* 8019 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 8029 +/* 8024 */ MCD_OPC_Decode, 205, 19, 239, 1, // Opcode: VESRLVG +/* 8029 */ MCD_OPC_CheckPredicate, 34, 106, 59, 0, // Skip to: 23244 +/* 8034 */ MCD_OPC_Decode, 202, 19, 147, 2, // Opcode: VESRLV +/* 8039 */ MCD_OPC_FilterValue, 122, 89, 0, 0, // Skip to: 8133 +/* 8044 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 8047 */ MCD_OPC_FilterValue, 0, 88, 59, 0, // Skip to: 23244 +/* 8052 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 8055 */ MCD_OPC_FilterValue, 0, 80, 59, 0, // Skip to: 23244 +/* 8060 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 8063 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8078 +/* 8068 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 8123 +/* 8073 */ MCD_OPC_Decode, 193, 19, 239, 1, // Opcode: VESRAVB +/* 8078 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8093 +/* 8083 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 8123 +/* 8088 */ MCD_OPC_Decode, 196, 19, 239, 1, // Opcode: VESRAVH +/* 8093 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8108 +/* 8098 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 8123 +/* 8103 */ MCD_OPC_Decode, 194, 19, 239, 1, // Opcode: VESRAVF +/* 8108 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 8123 +/* 8113 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 8123 +/* 8118 */ MCD_OPC_Decode, 195, 19, 239, 1, // Opcode: VESRAVG +/* 8123 */ MCD_OPC_CheckPredicate, 34, 12, 59, 0, // Skip to: 23244 +/* 8128 */ MCD_OPC_Decode, 192, 19, 147, 2, // Opcode: VESRAV +/* 8133 */ MCD_OPC_FilterValue, 124, 24, 0, 0, // Skip to: 8162 +/* 8138 */ MCD_OPC_CheckPredicate, 34, 253, 58, 0, // Skip to: 23244 +/* 8143 */ MCD_OPC_CheckField, 12, 16, 0, 246, 58, 0, // Skip to: 23244 +/* 8150 */ MCD_OPC_CheckField, 8, 1, 0, 239, 58, 0, // Skip to: 23244 +/* 8157 */ MCD_OPC_Decode, 215, 22, 239, 1, // Opcode: VSRL +/* 8162 */ MCD_OPC_FilterValue, 125, 24, 0, 0, // Skip to: 8191 +/* 8167 */ MCD_OPC_CheckPredicate, 34, 224, 58, 0, // Skip to: 23244 +/* 8172 */ MCD_OPC_CheckField, 12, 16, 0, 217, 58, 0, // Skip to: 23244 +/* 8179 */ MCD_OPC_CheckField, 8, 1, 0, 210, 58, 0, // Skip to: 23244 +/* 8186 */ MCD_OPC_Decode, 216, 22, 239, 1, // Opcode: VSRLB +/* 8191 */ MCD_OPC_FilterValue, 126, 24, 0, 0, // Skip to: 8220 +/* 8196 */ MCD_OPC_CheckPredicate, 34, 195, 58, 0, // Skip to: 23244 +/* 8201 */ MCD_OPC_CheckField, 12, 16, 0, 188, 58, 0, // Skip to: 23244 +/* 8208 */ MCD_OPC_CheckField, 8, 1, 0, 181, 58, 0, // Skip to: 23244 +/* 8215 */ MCD_OPC_Decode, 212, 22, 239, 1, // Opcode: VSRA +/* 8220 */ MCD_OPC_FilterValue, 127, 24, 0, 0, // Skip to: 8249 +/* 8225 */ MCD_OPC_CheckPredicate, 34, 166, 58, 0, // Skip to: 23244 +/* 8230 */ MCD_OPC_CheckField, 12, 16, 0, 159, 58, 0, // Skip to: 23244 +/* 8237 */ MCD_OPC_CheckField, 8, 1, 0, 152, 58, 0, // Skip to: 23244 +/* 8244 */ MCD_OPC_Decode, 213, 22, 239, 1, // Opcode: VSRAB +/* 8249 */ MCD_OPC_FilterValue, 128, 1, 226, 0, 0, // Skip to: 8481 +/* 8255 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 8258 */ MCD_OPC_FilterValue, 0, 133, 58, 0, // Skip to: 23244 +/* 8263 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 8266 */ MCD_OPC_FilterValue, 0, 125, 58, 0, // Skip to: 23244 +/* 8271 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 8274 */ MCD_OPC_FilterValue, 0, 117, 58, 0, // Skip to: 23244 +/* 8279 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 8282 */ MCD_OPC_FilterValue, 0, 58, 0, 0, // Skip to: 8345 +/* 8287 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 8290 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8305 +/* 8295 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 8335 +/* 8300 */ MCD_OPC_Decode, 243, 19, 239, 1, // Opcode: VFEEBS +/* 8305 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8320 +/* 8310 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 8335 +/* 8315 */ MCD_OPC_Decode, 248, 19, 239, 1, // Opcode: VFEEZB +/* 8320 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 8335 +/* 8325 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 8335 +/* 8330 */ MCD_OPC_Decode, 249, 19, 239, 1, // Opcode: VFEEZBS +/* 8335 */ MCD_OPC_CheckPredicate, 34, 131, 0, 0, // Skip to: 8471 +/* 8340 */ MCD_OPC_Decode, 242, 19, 235, 1, // Opcode: VFEEB +/* 8345 */ MCD_OPC_FilterValue, 1, 58, 0, 0, // Skip to: 8408 +/* 8350 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 8353 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8368 +/* 8358 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 8398 +/* 8363 */ MCD_OPC_Decode, 247, 19, 239, 1, // Opcode: VFEEHS +/* 8368 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8383 +/* 8373 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 8398 +/* 8378 */ MCD_OPC_Decode, 252, 19, 239, 1, // Opcode: VFEEZH +/* 8383 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 8398 +/* 8388 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 8398 +/* 8393 */ MCD_OPC_Decode, 253, 19, 239, 1, // Opcode: VFEEZHS +/* 8398 */ MCD_OPC_CheckPredicate, 34, 68, 0, 0, // Skip to: 8471 +/* 8403 */ MCD_OPC_Decode, 246, 19, 235, 1, // Opcode: VFEEH +/* 8408 */ MCD_OPC_FilterValue, 2, 58, 0, 0, // Skip to: 8471 +/* 8413 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 8416 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8431 +/* 8421 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 8461 +/* 8426 */ MCD_OPC_Decode, 245, 19, 239, 1, // Opcode: VFEEFS +/* 8431 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8446 +/* 8436 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 8461 +/* 8441 */ MCD_OPC_Decode, 250, 19, 239, 1, // Opcode: VFEEZF +/* 8446 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 8461 +/* 8451 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 8461 +/* 8456 */ MCD_OPC_Decode, 251, 19, 239, 1, // Opcode: VFEEZFS +/* 8461 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 8471 +/* 8466 */ MCD_OPC_Decode, 244, 19, 235, 1, // Opcode: VFEEF +/* 8471 */ MCD_OPC_CheckPredicate, 34, 176, 57, 0, // Skip to: 23244 +/* 8476 */ MCD_OPC_Decode, 241, 19, 236, 1, // Opcode: VFEE +/* 8481 */ MCD_OPC_FilterValue, 129, 1, 226, 0, 0, // Skip to: 8713 +/* 8487 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 8490 */ MCD_OPC_FilterValue, 0, 157, 57, 0, // Skip to: 23244 +/* 8495 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 8498 */ MCD_OPC_FilterValue, 0, 149, 57, 0, // Skip to: 23244 +/* 8503 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 8506 */ MCD_OPC_FilterValue, 0, 141, 57, 0, // Skip to: 23244 +/* 8511 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 8514 */ MCD_OPC_FilterValue, 0, 58, 0, 0, // Skip to: 8577 +/* 8519 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 8522 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8537 +/* 8527 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 8567 +/* 8532 */ MCD_OPC_Decode, 128, 20, 239, 1, // Opcode: VFENEBS +/* 8537 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8552 +/* 8542 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 8567 +/* 8547 */ MCD_OPC_Decode, 133, 20, 239, 1, // Opcode: VFENEZB +/* 8552 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 8567 +/* 8557 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 8567 +/* 8562 */ MCD_OPC_Decode, 134, 20, 239, 1, // Opcode: VFENEZBS +/* 8567 */ MCD_OPC_CheckPredicate, 34, 131, 0, 0, // Skip to: 8703 +/* 8572 */ MCD_OPC_Decode, 255, 19, 235, 1, // Opcode: VFENEB +/* 8577 */ MCD_OPC_FilterValue, 1, 58, 0, 0, // Skip to: 8640 +/* 8582 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 8585 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8600 +/* 8590 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 8630 +/* 8595 */ MCD_OPC_Decode, 132, 20, 239, 1, // Opcode: VFENEHS +/* 8600 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8615 +/* 8605 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 8630 +/* 8610 */ MCD_OPC_Decode, 137, 20, 239, 1, // Opcode: VFENEZH +/* 8615 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 8630 +/* 8620 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 8630 +/* 8625 */ MCD_OPC_Decode, 138, 20, 239, 1, // Opcode: VFENEZHS +/* 8630 */ MCD_OPC_CheckPredicate, 34, 68, 0, 0, // Skip to: 8703 +/* 8635 */ MCD_OPC_Decode, 131, 20, 235, 1, // Opcode: VFENEH +/* 8640 */ MCD_OPC_FilterValue, 2, 58, 0, 0, // Skip to: 8703 +/* 8645 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 8648 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8663 +/* 8653 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 8693 +/* 8658 */ MCD_OPC_Decode, 130, 20, 239, 1, // Opcode: VFENEFS +/* 8663 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8678 +/* 8668 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 8693 +/* 8673 */ MCD_OPC_Decode, 135, 20, 239, 1, // Opcode: VFENEZF +/* 8678 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 8693 +/* 8683 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 8693 +/* 8688 */ MCD_OPC_Decode, 136, 20, 239, 1, // Opcode: VFENEZFS +/* 8693 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 8703 +/* 8698 */ MCD_OPC_Decode, 129, 20, 235, 1, // Opcode: VFENEF +/* 8703 */ MCD_OPC_CheckPredicate, 34, 200, 56, 0, // Skip to: 23244 +/* 8708 */ MCD_OPC_Decode, 254, 19, 236, 1, // Opcode: VFENE +/* 8713 */ MCD_OPC_FilterValue, 130, 1, 235, 0, 0, // Skip to: 8954 +/* 8719 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 8722 */ MCD_OPC_FilterValue, 0, 181, 56, 0, // Skip to: 23244 +/* 8727 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 8730 */ MCD_OPC_FilterValue, 0, 173, 56, 0, // Skip to: 23244 +/* 8735 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 8738 */ MCD_OPC_FilterValue, 0, 165, 56, 0, // Skip to: 23244 +/* 8743 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 8746 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 8812 +/* 8751 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 8768 +/* 8756 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, 0, // Skip to: 8768 +/* 8763 */ MCD_OPC_Decode, 217, 19, 152, 2, // Opcode: VFAEZBS +/* 8768 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 8785 +/* 8773 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, 0, // Skip to: 8785 +/* 8780 */ MCD_OPC_Decode, 211, 19, 153, 2, // Opcode: VFAEBS +/* 8785 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 8802 +/* 8790 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, 0, // Skip to: 8802 +/* 8797 */ MCD_OPC_Decode, 216, 19, 154, 2, // Opcode: VFAEZB +/* 8802 */ MCD_OPC_CheckPredicate, 34, 137, 0, 0, // Skip to: 8944 +/* 8807 */ MCD_OPC_Decode, 210, 19, 235, 1, // Opcode: VFAEB +/* 8812 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 8878 +/* 8817 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 8834 +/* 8822 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, 0, // Skip to: 8834 +/* 8829 */ MCD_OPC_Decode, 221, 19, 152, 2, // Opcode: VFAEZHS +/* 8834 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 8851 +/* 8839 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, 0, // Skip to: 8851 +/* 8846 */ MCD_OPC_Decode, 215, 19, 153, 2, // Opcode: VFAEHS +/* 8851 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 8868 +/* 8856 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, 0, // Skip to: 8868 +/* 8863 */ MCD_OPC_Decode, 220, 19, 154, 2, // Opcode: VFAEZH +/* 8868 */ MCD_OPC_CheckPredicate, 34, 71, 0, 0, // Skip to: 8944 +/* 8873 */ MCD_OPC_Decode, 214, 19, 235, 1, // Opcode: VFAEH +/* 8878 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 8944 +/* 8883 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 8900 +/* 8888 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, 0, // Skip to: 8900 +/* 8895 */ MCD_OPC_Decode, 219, 19, 152, 2, // Opcode: VFAEZFS +/* 8900 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 8917 +/* 8905 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, 0, // Skip to: 8917 +/* 8912 */ MCD_OPC_Decode, 213, 19, 153, 2, // Opcode: VFAEFS +/* 8917 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 8934 +/* 8922 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, 0, // Skip to: 8934 +/* 8929 */ MCD_OPC_Decode, 218, 19, 154, 2, // Opcode: VFAEZF +/* 8934 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 8944 +/* 8939 */ MCD_OPC_Decode, 212, 19, 235, 1, // Opcode: VFAEF +/* 8944 */ MCD_OPC_CheckPredicate, 34, 215, 55, 0, // Skip to: 23244 +/* 8949 */ MCD_OPC_Decode, 209, 19, 236, 1, // Opcode: VFAE +/* 8954 */ MCD_OPC_FilterValue, 132, 1, 24, 0, 0, // Skip to: 8984 +/* 8960 */ MCD_OPC_CheckPredicate, 34, 199, 55, 0, // Skip to: 23244 +/* 8965 */ MCD_OPC_CheckField, 16, 12, 0, 192, 55, 0, // Skip to: 23244 +/* 8972 */ MCD_OPC_CheckField, 8, 1, 0, 185, 55, 0, // Skip to: 23244 +/* 8979 */ MCD_OPC_Decode, 139, 22, 147, 2, // Opcode: VPDI +/* 8984 */ MCD_OPC_FilterValue, 133, 1, 24, 0, 0, // Skip to: 9014 +/* 8990 */ MCD_OPC_CheckPredicate, 35, 169, 55, 0, // Skip to: 23244 +/* 8995 */ MCD_OPC_CheckField, 12, 16, 0, 162, 55, 0, // Skip to: 23244 +/* 9002 */ MCD_OPC_CheckField, 8, 1, 0, 155, 55, 0, // Skip to: 23244 +/* 9009 */ MCD_OPC_Decode, 210, 18, 239, 1, // Opcode: VBPERM +/* 9014 */ MCD_OPC_FilterValue, 134, 1, 31, 0, 0, // Skip to: 9051 +/* 9020 */ MCD_OPC_CheckPredicate, 29, 139, 55, 0, // Skip to: 23244 +/* 9025 */ MCD_OPC_CheckField, 24, 4, 0, 132, 55, 0, // Skip to: 23244 +/* 9032 */ MCD_OPC_CheckField, 12, 4, 0, 125, 55, 0, // Skip to: 23244 +/* 9039 */ MCD_OPC_CheckField, 8, 1, 0, 118, 55, 0, // Skip to: 23244 +/* 9046 */ MCD_OPC_Decode, 208, 22, 151, 2, // Opcode: VSLD +/* 9051 */ MCD_OPC_FilterValue, 135, 1, 31, 0, 0, // Skip to: 9088 +/* 9057 */ MCD_OPC_CheckPredicate, 29, 102, 55, 0, // Skip to: 23244 +/* 9062 */ MCD_OPC_CheckField, 24, 4, 0, 95, 55, 0, // Skip to: 23244 +/* 9069 */ MCD_OPC_CheckField, 12, 4, 0, 88, 55, 0, // Skip to: 23244 +/* 9076 */ MCD_OPC_CheckField, 8, 1, 0, 81, 55, 0, // Skip to: 23244 +/* 9083 */ MCD_OPC_Decode, 214, 22, 151, 2, // Opcode: VSRD +/* 9088 */ MCD_OPC_FilterValue, 138, 1, 219, 0, 0, // Skip to: 9313 +/* 9094 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 9097 */ MCD_OPC_FilterValue, 0, 62, 55, 0, // Skip to: 23244 +/* 9102 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 9105 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 9171 +/* 9110 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 9127 +/* 9115 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, 0, // Skip to: 9127 +/* 9122 */ MCD_OPC_Decode, 248, 22, 155, 2, // Opcode: VSTRCZBS +/* 9127 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 9144 +/* 9132 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, 0, // Skip to: 9144 +/* 9139 */ MCD_OPC_Decode, 242, 22, 156, 2, // Opcode: VSTRCBS +/* 9144 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 9161 +/* 9149 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, 0, // Skip to: 9161 +/* 9156 */ MCD_OPC_Decode, 247, 22, 157, 2, // Opcode: VSTRCZB +/* 9161 */ MCD_OPC_CheckPredicate, 34, 137, 0, 0, // Skip to: 9303 +/* 9166 */ MCD_OPC_Decode, 241, 22, 158, 2, // Opcode: VSTRCB +/* 9171 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 9237 +/* 9176 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 9193 +/* 9181 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, 0, // Skip to: 9193 +/* 9188 */ MCD_OPC_Decode, 252, 22, 155, 2, // Opcode: VSTRCZHS +/* 9193 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 9210 +/* 9198 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, 0, // Skip to: 9210 +/* 9205 */ MCD_OPC_Decode, 246, 22, 156, 2, // Opcode: VSTRCHS +/* 9210 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 9227 +/* 9215 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, 0, // Skip to: 9227 +/* 9222 */ MCD_OPC_Decode, 251, 22, 157, 2, // Opcode: VSTRCZH +/* 9227 */ MCD_OPC_CheckPredicate, 34, 71, 0, 0, // Skip to: 9303 +/* 9232 */ MCD_OPC_Decode, 245, 22, 158, 2, // Opcode: VSTRCH +/* 9237 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 9303 +/* 9242 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 9259 +/* 9247 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, 0, // Skip to: 9259 +/* 9254 */ MCD_OPC_Decode, 250, 22, 155, 2, // Opcode: VSTRCZFS +/* 9259 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 9276 +/* 9264 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, 0, // Skip to: 9276 +/* 9271 */ MCD_OPC_Decode, 244, 22, 156, 2, // Opcode: VSTRCFS +/* 9276 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 9293 +/* 9281 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, 0, // Skip to: 9293 +/* 9288 */ MCD_OPC_Decode, 249, 22, 157, 2, // Opcode: VSTRCZF +/* 9293 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 9303 +/* 9298 */ MCD_OPC_Decode, 243, 22, 158, 2, // Opcode: VSTRCF +/* 9303 */ MCD_OPC_CheckPredicate, 34, 112, 54, 0, // Skip to: 23244 +/* 9308 */ MCD_OPC_Decode, 240, 22, 159, 2, // Opcode: VSTRC +/* 9313 */ MCD_OPC_FilterValue, 139, 1, 114, 0, 0, // Skip to: 9433 +/* 9319 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 9322 */ MCD_OPC_FilterValue, 0, 93, 54, 0, // Skip to: 23244 +/* 9327 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... +/* 9330 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9345 +/* 9335 */ MCD_OPC_CheckPredicate, 29, 35, 0, 0, // Skip to: 9375 +/* 9340 */ MCD_OPC_Decode, 131, 23, 160, 2, // Opcode: VSTRSZB +/* 9345 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 9360 +/* 9350 */ MCD_OPC_CheckPredicate, 29, 20, 0, 0, // Skip to: 9375 +/* 9355 */ MCD_OPC_Decode, 133, 23, 160, 2, // Opcode: VSTRSZH +/* 9360 */ MCD_OPC_FilterValue, 34, 10, 0, 0, // Skip to: 9375 +/* 9365 */ MCD_OPC_CheckPredicate, 29, 5, 0, 0, // Skip to: 9375 +/* 9370 */ MCD_OPC_Decode, 132, 23, 160, 2, // Opcode: VSTRSZF +/* 9375 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 9378 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9393 +/* 9383 */ MCD_OPC_CheckPredicate, 29, 35, 0, 0, // Skip to: 9423 +/* 9388 */ MCD_OPC_Decode, 128, 23, 158, 2, // Opcode: VSTRSB +/* 9393 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9408 +/* 9398 */ MCD_OPC_CheckPredicate, 29, 20, 0, 0, // Skip to: 9423 +/* 9403 */ MCD_OPC_Decode, 130, 23, 158, 2, // Opcode: VSTRSH +/* 9408 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9423 +/* 9413 */ MCD_OPC_CheckPredicate, 29, 5, 0, 0, // Skip to: 9423 +/* 9418 */ MCD_OPC_Decode, 129, 23, 158, 2, // Opcode: VSTRSF +/* 9423 */ MCD_OPC_CheckPredicate, 29, 248, 53, 0, // Skip to: 23244 +/* 9428 */ MCD_OPC_Decode, 255, 22, 159, 2, // Opcode: VSTRS +/* 9433 */ MCD_OPC_FilterValue, 140, 1, 17, 0, 0, // Skip to: 9456 +/* 9439 */ MCD_OPC_CheckPredicate, 34, 232, 53, 0, // Skip to: 23244 +/* 9444 */ MCD_OPC_CheckField, 16, 12, 0, 225, 53, 0, // Skip to: 23244 +/* 9451 */ MCD_OPC_Decode, 140, 22, 160, 2, // Opcode: VPERM +/* 9456 */ MCD_OPC_FilterValue, 141, 1, 17, 0, 0, // Skip to: 9479 +/* 9462 */ MCD_OPC_CheckPredicate, 34, 209, 53, 0, // Skip to: 23244 +/* 9467 */ MCD_OPC_CheckField, 16, 12, 0, 202, 53, 0, // Skip to: 23244 +/* 9474 */ MCD_OPC_Decode, 202, 22, 160, 2, // Opcode: VSEL +/* 9479 */ MCD_OPC_FilterValue, 142, 1, 119, 0, 0, // Skip to: 9604 +/* 9485 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 9488 */ MCD_OPC_FilterValue, 0, 183, 53, 0, // Skip to: 23244 +/* 9493 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 9496 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 9534 +/* 9501 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 9504 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9519 +/* 9509 */ MCD_OPC_CheckPredicate, 35, 80, 0, 0, // Skip to: 9594 +/* 9514 */ MCD_OPC_Decode, 178, 20, 160, 2, // Opcode: VFMSSB +/* 9519 */ MCD_OPC_FilterValue, 8, 70, 0, 0, // Skip to: 9594 +/* 9524 */ MCD_OPC_CheckPredicate, 35, 65, 0, 0, // Skip to: 9594 +/* 9529 */ MCD_OPC_Decode, 252, 23, 161, 2, // Opcode: WFMSSB +/* 9534 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 9572 +/* 9539 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 9542 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9557 +/* 9547 */ MCD_OPC_CheckPredicate, 34, 42, 0, 0, // Skip to: 9594 +/* 9552 */ MCD_OPC_Decode, 177, 20, 160, 2, // Opcode: VFMSDB +/* 9557 */ MCD_OPC_FilterValue, 8, 32, 0, 0, // Skip to: 9594 +/* 9562 */ MCD_OPC_CheckPredicate, 34, 27, 0, 0, // Skip to: 9594 +/* 9567 */ MCD_OPC_Decode, 251, 23, 162, 2, // Opcode: WFMSDB +/* 9572 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 9594 +/* 9577 */ MCD_OPC_CheckPredicate, 35, 12, 0, 0, // Skip to: 9594 +/* 9582 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, 0, // Skip to: 9594 +/* 9589 */ MCD_OPC_Decode, 253, 23, 160, 2, // Opcode: WFMSXB +/* 9594 */ MCD_OPC_CheckPredicate, 34, 77, 53, 0, // Skip to: 23244 +/* 9599 */ MCD_OPC_Decode, 175, 20, 163, 2, // Opcode: VFMS +/* 9604 */ MCD_OPC_FilterValue, 143, 1, 119, 0, 0, // Skip to: 9729 +/* 9610 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 9613 */ MCD_OPC_FilterValue, 0, 58, 53, 0, // Skip to: 23244 +/* 9618 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 9621 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 9659 +/* 9626 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 9629 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9644 +/* 9634 */ MCD_OPC_CheckPredicate, 35, 80, 0, 0, // Skip to: 9719 +/* 9639 */ MCD_OPC_Decode, 167, 20, 160, 2, // Opcode: VFMASB +/* 9644 */ MCD_OPC_FilterValue, 8, 70, 0, 0, // Skip to: 9719 +/* 9649 */ MCD_OPC_CheckPredicate, 35, 65, 0, 0, // Skip to: 9719 +/* 9654 */ MCD_OPC_Decode, 241, 23, 161, 2, // Opcode: WFMASB +/* 9659 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 9697 +/* 9664 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 9667 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9682 +/* 9672 */ MCD_OPC_CheckPredicate, 34, 42, 0, 0, // Skip to: 9719 +/* 9677 */ MCD_OPC_Decode, 166, 20, 160, 2, // Opcode: VFMADB +/* 9682 */ MCD_OPC_FilterValue, 8, 32, 0, 0, // Skip to: 9719 +/* 9687 */ MCD_OPC_CheckPredicate, 34, 27, 0, 0, // Skip to: 9719 +/* 9692 */ MCD_OPC_Decode, 240, 23, 162, 2, // Opcode: WFMADB +/* 9697 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 9719 +/* 9702 */ MCD_OPC_CheckPredicate, 35, 12, 0, 0, // Skip to: 9719 +/* 9707 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, 0, // Skip to: 9719 +/* 9714 */ MCD_OPC_Decode, 242, 23, 160, 2, // Opcode: WFMAXB +/* 9719 */ MCD_OPC_CheckPredicate, 34, 208, 52, 0, // Skip to: 23244 +/* 9724 */ MCD_OPC_Decode, 165, 20, 163, 2, // Opcode: VFMA +/* 9729 */ MCD_OPC_FilterValue, 148, 1, 74, 0, 0, // Skip to: 9809 +/* 9735 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 9738 */ MCD_OPC_FilterValue, 0, 189, 52, 0, // Skip to: 23244 +/* 9743 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 9746 */ MCD_OPC_FilterValue, 0, 181, 52, 0, // Skip to: 23244 +/* 9751 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 9754 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9769 +/* 9759 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 9799 +/* 9764 */ MCD_OPC_Decode, 144, 22, 239, 1, // Opcode: VPKH +/* 9769 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9784 +/* 9774 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 9799 +/* 9779 */ MCD_OPC_Decode, 142, 22, 239, 1, // Opcode: VPKF +/* 9784 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 9799 +/* 9789 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 9799 +/* 9794 */ MCD_OPC_Decode, 143, 22, 239, 1, // Opcode: VPKG +/* 9799 */ MCD_OPC_CheckPredicate, 34, 128, 52, 0, // Skip to: 23244 +/* 9804 */ MCD_OPC_Decode, 141, 22, 147, 2, // Opcode: VPK +/* 9809 */ MCD_OPC_FilterValue, 149, 1, 151, 0, 0, // Skip to: 9966 +/* 9815 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 9818 */ MCD_OPC_FilterValue, 0, 109, 52, 0, // Skip to: 23244 +/* 9823 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 9826 */ MCD_OPC_FilterValue, 0, 101, 52, 0, // Skip to: 23244 +/* 9831 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 9834 */ MCD_OPC_FilterValue, 0, 93, 52, 0, // Skip to: 23244 +/* 9839 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 9842 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 9880 +/* 9847 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 9850 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9865 +/* 9855 */ MCD_OPC_CheckPredicate, 34, 96, 0, 0, // Skip to: 9956 +/* 9860 */ MCD_OPC_Decode, 150, 22, 239, 1, // Opcode: VPKLSH +/* 9865 */ MCD_OPC_FilterValue, 1, 86, 0, 0, // Skip to: 9956 +/* 9870 */ MCD_OPC_CheckPredicate, 34, 81, 0, 0, // Skip to: 9956 +/* 9875 */ MCD_OPC_Decode, 151, 22, 239, 1, // Opcode: VPKLSHS +/* 9880 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 9918 +/* 9885 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 9888 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9903 +/* 9893 */ MCD_OPC_CheckPredicate, 34, 58, 0, 0, // Skip to: 9956 +/* 9898 */ MCD_OPC_Decode, 146, 22, 239, 1, // Opcode: VPKLSF +/* 9903 */ MCD_OPC_FilterValue, 1, 48, 0, 0, // Skip to: 9956 +/* 9908 */ MCD_OPC_CheckPredicate, 34, 43, 0, 0, // Skip to: 9956 +/* 9913 */ MCD_OPC_Decode, 147, 22, 239, 1, // Opcode: VPKLSFS +/* 9918 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 9956 +/* 9923 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 9926 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9941 +/* 9931 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 9956 +/* 9936 */ MCD_OPC_Decode, 148, 22, 239, 1, // Opcode: VPKLSG +/* 9941 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9956 +/* 9946 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 9956 +/* 9951 */ MCD_OPC_Decode, 149, 22, 239, 1, // Opcode: VPKLSGS +/* 9956 */ MCD_OPC_CheckPredicate, 34, 227, 51, 0, // Skip to: 23244 +/* 9961 */ MCD_OPC_Decode, 145, 22, 236, 1, // Opcode: VPKLS +/* 9966 */ MCD_OPC_FilterValue, 151, 1, 151, 0, 0, // Skip to: 10123 +/* 9972 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 9975 */ MCD_OPC_FilterValue, 0, 208, 51, 0, // Skip to: 23244 +/* 9980 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 9983 */ MCD_OPC_FilterValue, 0, 200, 51, 0, // Skip to: 23244 +/* 9988 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 9991 */ MCD_OPC_FilterValue, 0, 192, 51, 0, // Skip to: 23244 +/* 9996 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 9999 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10037 +/* 10004 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 10007 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10022 +/* 10012 */ MCD_OPC_CheckPredicate, 34, 96, 0, 0, // Skip to: 10113 +/* 10017 */ MCD_OPC_Decode, 157, 22, 239, 1, // Opcode: VPKSH +/* 10022 */ MCD_OPC_FilterValue, 1, 86, 0, 0, // Skip to: 10113 +/* 10027 */ MCD_OPC_CheckPredicate, 34, 81, 0, 0, // Skip to: 10113 +/* 10032 */ MCD_OPC_Decode, 158, 22, 239, 1, // Opcode: VPKSHS +/* 10037 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 10075 +/* 10042 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 10045 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10060 +/* 10050 */ MCD_OPC_CheckPredicate, 34, 58, 0, 0, // Skip to: 10113 +/* 10055 */ MCD_OPC_Decode, 153, 22, 239, 1, // Opcode: VPKSF +/* 10060 */ MCD_OPC_FilterValue, 1, 48, 0, 0, // Skip to: 10113 +/* 10065 */ MCD_OPC_CheckPredicate, 34, 43, 0, 0, // Skip to: 10113 +/* 10070 */ MCD_OPC_Decode, 154, 22, 239, 1, // Opcode: VPKSFS +/* 10075 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 10113 +/* 10080 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 10083 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10098 +/* 10088 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 10113 +/* 10093 */ MCD_OPC_Decode, 155, 22, 239, 1, // Opcode: VPKSG +/* 10098 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 10113 +/* 10103 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 10113 +/* 10108 */ MCD_OPC_Decode, 156, 22, 239, 1, // Opcode: VPKSGS +/* 10113 */ MCD_OPC_CheckPredicate, 34, 70, 51, 0, // Skip to: 23244 +/* 10118 */ MCD_OPC_Decode, 152, 22, 236, 1, // Opcode: VPKS +/* 10123 */ MCD_OPC_FilterValue, 158, 1, 119, 0, 0, // Skip to: 10248 +/* 10129 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 10132 */ MCD_OPC_FilterValue, 0, 51, 51, 0, // Skip to: 23244 +/* 10137 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 10140 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 10178 +/* 10145 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 10148 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10163 +/* 10153 */ MCD_OPC_CheckPredicate, 35, 80, 0, 0, // Skip to: 10238 +/* 10158 */ MCD_OPC_Decode, 184, 20, 160, 2, // Opcode: VFNMSSB +/* 10163 */ MCD_OPC_FilterValue, 8, 70, 0, 0, // Skip to: 10238 +/* 10168 */ MCD_OPC_CheckPredicate, 35, 65, 0, 0, // Skip to: 10238 +/* 10173 */ MCD_OPC_Decode, 131, 24, 161, 2, // Opcode: WFNMSSB +/* 10178 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 10216 +/* 10183 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 10186 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10201 +/* 10191 */ MCD_OPC_CheckPredicate, 35, 42, 0, 0, // Skip to: 10238 +/* 10196 */ MCD_OPC_Decode, 183, 20, 160, 2, // Opcode: VFNMSDB +/* 10201 */ MCD_OPC_FilterValue, 8, 32, 0, 0, // Skip to: 10238 +/* 10206 */ MCD_OPC_CheckPredicate, 35, 27, 0, 0, // Skip to: 10238 +/* 10211 */ MCD_OPC_Decode, 130, 24, 162, 2, // Opcode: WFNMSDB +/* 10216 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 10238 +/* 10221 */ MCD_OPC_CheckPredicate, 35, 12, 0, 0, // Skip to: 10238 +/* 10226 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, 0, // Skip to: 10238 +/* 10233 */ MCD_OPC_Decode, 132, 24, 160, 2, // Opcode: WFNMSXB +/* 10238 */ MCD_OPC_CheckPredicate, 35, 201, 50, 0, // Skip to: 23244 +/* 10243 */ MCD_OPC_Decode, 182, 20, 163, 2, // Opcode: VFNMS +/* 10248 */ MCD_OPC_FilterValue, 159, 1, 119, 0, 0, // Skip to: 10373 +/* 10254 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 10257 */ MCD_OPC_FilterValue, 0, 182, 50, 0, // Skip to: 23244 +/* 10262 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 10265 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 10303 +/* 10270 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 10273 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10288 +/* 10278 */ MCD_OPC_CheckPredicate, 35, 80, 0, 0, // Skip to: 10363 +/* 10283 */ MCD_OPC_Decode, 181, 20, 160, 2, // Opcode: VFNMASB +/* 10288 */ MCD_OPC_FilterValue, 8, 70, 0, 0, // Skip to: 10363 +/* 10293 */ MCD_OPC_CheckPredicate, 35, 65, 0, 0, // Skip to: 10363 +/* 10298 */ MCD_OPC_Decode, 128, 24, 161, 2, // Opcode: WFNMASB +/* 10303 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 10341 +/* 10308 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 10311 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10326 +/* 10316 */ MCD_OPC_CheckPredicate, 35, 42, 0, 0, // Skip to: 10363 +/* 10321 */ MCD_OPC_Decode, 180, 20, 160, 2, // Opcode: VFNMADB +/* 10326 */ MCD_OPC_FilterValue, 8, 32, 0, 0, // Skip to: 10363 +/* 10331 */ MCD_OPC_CheckPredicate, 35, 27, 0, 0, // Skip to: 10363 +/* 10336 */ MCD_OPC_Decode, 255, 23, 162, 2, // Opcode: WFNMADB +/* 10341 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 10363 +/* 10346 */ MCD_OPC_CheckPredicate, 35, 12, 0, 0, // Skip to: 10363 +/* 10351 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, 0, // Skip to: 10363 +/* 10358 */ MCD_OPC_Decode, 129, 24, 160, 2, // Opcode: WFNMAXB +/* 10363 */ MCD_OPC_CheckPredicate, 35, 76, 50, 0, // Skip to: 23244 +/* 10368 */ MCD_OPC_Decode, 179, 20, 163, 2, // Opcode: VFNMA +/* 10373 */ MCD_OPC_FilterValue, 161, 1, 74, 0, 0, // Skip to: 10453 +/* 10379 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 10382 */ MCD_OPC_FilterValue, 0, 57, 50, 0, // Skip to: 23244 +/* 10387 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 10390 */ MCD_OPC_FilterValue, 0, 49, 50, 0, // Skip to: 23244 +/* 10395 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 10398 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10413 +/* 10403 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 10443 +/* 10408 */ MCD_OPC_Decode, 213, 21, 239, 1, // Opcode: VMLHB +/* 10413 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 10428 +/* 10418 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 10443 +/* 10423 */ MCD_OPC_Decode, 215, 21, 239, 1, // Opcode: VMLHH +/* 10428 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 10443 +/* 10433 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 10443 +/* 10438 */ MCD_OPC_Decode, 214, 21, 239, 1, // Opcode: VMLHF +/* 10443 */ MCD_OPC_CheckPredicate, 34, 252, 49, 0, // Skip to: 23244 +/* 10448 */ MCD_OPC_Decode, 212, 21, 147, 2, // Opcode: VMLH +/* 10453 */ MCD_OPC_FilterValue, 162, 1, 74, 0, 0, // Skip to: 10533 +/* 10459 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 10462 */ MCD_OPC_FilterValue, 0, 233, 49, 0, // Skip to: 23244 +/* 10467 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 10470 */ MCD_OPC_FilterValue, 0, 225, 49, 0, // Skip to: 23244 +/* 10475 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 10478 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10493 +/* 10483 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 10523 +/* 10488 */ MCD_OPC_Decode, 206, 21, 239, 1, // Opcode: VMLB +/* 10493 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 10508 +/* 10498 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 10523 +/* 10503 */ MCD_OPC_Decode, 216, 21, 239, 1, // Opcode: VMLHW +/* 10508 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 10523 +/* 10513 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 10523 +/* 10518 */ MCD_OPC_Decode, 211, 21, 239, 1, // Opcode: VMLF +/* 10523 */ MCD_OPC_CheckPredicate, 34, 172, 49, 0, // Skip to: 23244 +/* 10528 */ MCD_OPC_Decode, 205, 21, 147, 2, // Opcode: VML +/* 10533 */ MCD_OPC_FilterValue, 163, 1, 74, 0, 0, // Skip to: 10613 +/* 10539 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 10542 */ MCD_OPC_FilterValue, 0, 153, 49, 0, // Skip to: 23244 +/* 10547 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 10550 */ MCD_OPC_FilterValue, 0, 145, 49, 0, // Skip to: 23244 +/* 10555 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 10558 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10573 +/* 10563 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 10603 +/* 10568 */ MCD_OPC_Decode, 202, 21, 239, 1, // Opcode: VMHB +/* 10573 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 10588 +/* 10578 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 10603 +/* 10583 */ MCD_OPC_Decode, 204, 21, 239, 1, // Opcode: VMHH +/* 10588 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 10603 +/* 10593 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 10603 +/* 10598 */ MCD_OPC_Decode, 203, 21, 239, 1, // Opcode: VMHF +/* 10603 */ MCD_OPC_CheckPredicate, 34, 92, 49, 0, // Skip to: 23244 +/* 10608 */ MCD_OPC_Decode, 201, 21, 147, 2, // Opcode: VMH +/* 10613 */ MCD_OPC_FilterValue, 164, 1, 74, 0, 0, // Skip to: 10693 +/* 10619 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 10622 */ MCD_OPC_FilterValue, 0, 73, 49, 0, // Skip to: 23244 +/* 10627 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 10630 */ MCD_OPC_FilterValue, 0, 65, 49, 0, // Skip to: 23244 +/* 10635 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 10638 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10653 +/* 10643 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 10683 +/* 10648 */ MCD_OPC_Decode, 208, 21, 239, 1, // Opcode: VMLEB +/* 10653 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 10668 +/* 10658 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 10683 +/* 10663 */ MCD_OPC_Decode, 210, 21, 239, 1, // Opcode: VMLEH +/* 10668 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 10683 +/* 10673 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 10683 +/* 10678 */ MCD_OPC_Decode, 209, 21, 239, 1, // Opcode: VMLEF +/* 10683 */ MCD_OPC_CheckPredicate, 34, 12, 49, 0, // Skip to: 23244 +/* 10688 */ MCD_OPC_Decode, 207, 21, 147, 2, // Opcode: VMLE +/* 10693 */ MCD_OPC_FilterValue, 165, 1, 74, 0, 0, // Skip to: 10773 +/* 10699 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 10702 */ MCD_OPC_FilterValue, 0, 249, 48, 0, // Skip to: 23244 +/* 10707 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 10710 */ MCD_OPC_FilterValue, 0, 241, 48, 0, // Skip to: 23244 +/* 10715 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 10718 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10733 +/* 10723 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 10763 +/* 10728 */ MCD_OPC_Decode, 218, 21, 239, 1, // Opcode: VMLOB +/* 10733 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 10748 +/* 10738 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 10763 +/* 10743 */ MCD_OPC_Decode, 220, 21, 239, 1, // Opcode: VMLOH +/* 10748 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 10763 +/* 10753 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 10763 +/* 10758 */ MCD_OPC_Decode, 219, 21, 239, 1, // Opcode: VMLOF +/* 10763 */ MCD_OPC_CheckPredicate, 34, 188, 48, 0, // Skip to: 23244 +/* 10768 */ MCD_OPC_Decode, 217, 21, 147, 2, // Opcode: VMLO +/* 10773 */ MCD_OPC_FilterValue, 166, 1, 74, 0, 0, // Skip to: 10853 +/* 10779 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 10782 */ MCD_OPC_FilterValue, 0, 169, 48, 0, // Skip to: 23244 +/* 10787 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 10790 */ MCD_OPC_FilterValue, 0, 161, 48, 0, // Skip to: 23244 +/* 10795 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 10798 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10813 +/* 10803 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 10843 +/* 10808 */ MCD_OPC_Decode, 198, 21, 239, 1, // Opcode: VMEB +/* 10813 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 10828 +/* 10818 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 10843 +/* 10823 */ MCD_OPC_Decode, 200, 21, 239, 1, // Opcode: VMEH +/* 10828 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 10843 +/* 10833 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 10843 +/* 10838 */ MCD_OPC_Decode, 199, 21, 239, 1, // Opcode: VMEF +/* 10843 */ MCD_OPC_CheckPredicate, 34, 108, 48, 0, // Skip to: 23244 +/* 10848 */ MCD_OPC_Decode, 197, 21, 147, 2, // Opcode: VME +/* 10853 */ MCD_OPC_FilterValue, 167, 1, 74, 0, 0, // Skip to: 10933 +/* 10859 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 10862 */ MCD_OPC_FilterValue, 0, 89, 48, 0, // Skip to: 23244 +/* 10867 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 10870 */ MCD_OPC_FilterValue, 0, 81, 48, 0, // Skip to: 23244 +/* 10875 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 10878 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10893 +/* 10883 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 10923 +/* 10888 */ MCD_OPC_Decode, 232, 21, 239, 1, // Opcode: VMOB +/* 10893 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 10908 +/* 10898 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 10923 +/* 10903 */ MCD_OPC_Decode, 234, 21, 239, 1, // Opcode: VMOH +/* 10908 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 10923 +/* 10913 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 10923 +/* 10918 */ MCD_OPC_Decode, 233, 21, 239, 1, // Opcode: VMOF +/* 10923 */ MCD_OPC_CheckPredicate, 34, 28, 48, 0, // Skip to: 23244 +/* 10928 */ MCD_OPC_Decode, 231, 21, 147, 2, // Opcode: VMO +/* 10933 */ MCD_OPC_FilterValue, 169, 1, 66, 0, 0, // Skip to: 11005 +/* 10939 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 10942 */ MCD_OPC_FilterValue, 0, 9, 48, 0, // Skip to: 23244 +/* 10947 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 10950 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10965 +/* 10955 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 10995 +/* 10960 */ MCD_OPC_Decode, 185, 21, 160, 2, // Opcode: VMALHB +/* 10965 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 10980 +/* 10970 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 10995 +/* 10975 */ MCD_OPC_Decode, 187, 21, 160, 2, // Opcode: VMALHH +/* 10980 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 10995 +/* 10985 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 10995 +/* 10990 */ MCD_OPC_Decode, 186, 21, 160, 2, // Opcode: VMALHF +/* 10995 */ MCD_OPC_CheckPredicate, 34, 212, 47, 0, // Skip to: 23244 +/* 11000 */ MCD_OPC_Decode, 184, 21, 164, 2, // Opcode: VMALH +/* 11005 */ MCD_OPC_FilterValue, 170, 1, 66, 0, 0, // Skip to: 11077 +/* 11011 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 11014 */ MCD_OPC_FilterValue, 0, 193, 47, 0, // Skip to: 23244 +/* 11019 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 11022 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11037 +/* 11027 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 11067 +/* 11032 */ MCD_OPC_Decode, 178, 21, 160, 2, // Opcode: VMALB +/* 11037 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 11052 +/* 11042 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 11067 +/* 11047 */ MCD_OPC_Decode, 188, 21, 160, 2, // Opcode: VMALHW +/* 11052 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 11067 +/* 11057 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 11067 +/* 11062 */ MCD_OPC_Decode, 183, 21, 160, 2, // Opcode: VMALF +/* 11067 */ MCD_OPC_CheckPredicate, 34, 140, 47, 0, // Skip to: 23244 +/* 11072 */ MCD_OPC_Decode, 177, 21, 164, 2, // Opcode: VMAL +/* 11077 */ MCD_OPC_FilterValue, 171, 1, 66, 0, 0, // Skip to: 11149 +/* 11083 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 11086 */ MCD_OPC_FilterValue, 0, 121, 47, 0, // Skip to: 23244 +/* 11091 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 11094 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11109 +/* 11099 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 11139 +/* 11104 */ MCD_OPC_Decode, 174, 21, 160, 2, // Opcode: VMAHB +/* 11109 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 11124 +/* 11114 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 11139 +/* 11119 */ MCD_OPC_Decode, 176, 21, 160, 2, // Opcode: VMAHH +/* 11124 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 11139 +/* 11129 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 11139 +/* 11134 */ MCD_OPC_Decode, 175, 21, 160, 2, // Opcode: VMAHF +/* 11139 */ MCD_OPC_CheckPredicate, 34, 68, 47, 0, // Skip to: 23244 +/* 11144 */ MCD_OPC_Decode, 173, 21, 164, 2, // Opcode: VMAH +/* 11149 */ MCD_OPC_FilterValue, 172, 1, 66, 0, 0, // Skip to: 11221 +/* 11155 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 11158 */ MCD_OPC_FilterValue, 0, 49, 47, 0, // Skip to: 23244 +/* 11163 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 11166 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11181 +/* 11171 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 11211 +/* 11176 */ MCD_OPC_Decode, 180, 21, 160, 2, // Opcode: VMALEB +/* 11181 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 11196 +/* 11186 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 11211 +/* 11191 */ MCD_OPC_Decode, 182, 21, 160, 2, // Opcode: VMALEH +/* 11196 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 11211 +/* 11201 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 11211 +/* 11206 */ MCD_OPC_Decode, 181, 21, 160, 2, // Opcode: VMALEF +/* 11211 */ MCD_OPC_CheckPredicate, 34, 252, 46, 0, // Skip to: 23244 +/* 11216 */ MCD_OPC_Decode, 179, 21, 164, 2, // Opcode: VMALE +/* 11221 */ MCD_OPC_FilterValue, 173, 1, 66, 0, 0, // Skip to: 11293 +/* 11227 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 11230 */ MCD_OPC_FilterValue, 0, 233, 46, 0, // Skip to: 23244 +/* 11235 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 11238 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11253 +/* 11243 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 11283 +/* 11248 */ MCD_OPC_Decode, 190, 21, 160, 2, // Opcode: VMALOB +/* 11253 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 11268 +/* 11258 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 11283 +/* 11263 */ MCD_OPC_Decode, 192, 21, 160, 2, // Opcode: VMALOH +/* 11268 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 11283 +/* 11273 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 11283 +/* 11278 */ MCD_OPC_Decode, 191, 21, 160, 2, // Opcode: VMALOF +/* 11283 */ MCD_OPC_CheckPredicate, 34, 180, 46, 0, // Skip to: 23244 +/* 11288 */ MCD_OPC_Decode, 189, 21, 164, 2, // Opcode: VMALO +/* 11293 */ MCD_OPC_FilterValue, 174, 1, 66, 0, 0, // Skip to: 11365 +/* 11299 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 11302 */ MCD_OPC_FilterValue, 0, 161, 46, 0, // Skip to: 23244 +/* 11307 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 11310 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11325 +/* 11315 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 11355 +/* 11320 */ MCD_OPC_Decode, 170, 21, 160, 2, // Opcode: VMAEB +/* 11325 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 11340 +/* 11330 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 11355 +/* 11335 */ MCD_OPC_Decode, 172, 21, 160, 2, // Opcode: VMAEH +/* 11340 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 11355 +/* 11345 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 11355 +/* 11350 */ MCD_OPC_Decode, 171, 21, 160, 2, // Opcode: VMAEF +/* 11355 */ MCD_OPC_CheckPredicate, 34, 108, 46, 0, // Skip to: 23244 +/* 11360 */ MCD_OPC_Decode, 169, 21, 164, 2, // Opcode: VMAE +/* 11365 */ MCD_OPC_FilterValue, 175, 1, 66, 0, 0, // Skip to: 11437 +/* 11371 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 11374 */ MCD_OPC_FilterValue, 0, 89, 46, 0, // Skip to: 23244 +/* 11379 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 11382 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11397 +/* 11387 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 11427 +/* 11392 */ MCD_OPC_Decode, 194, 21, 160, 2, // Opcode: VMAOB +/* 11397 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 11412 +/* 11402 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 11427 +/* 11407 */ MCD_OPC_Decode, 196, 21, 160, 2, // Opcode: VMAOH +/* 11412 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 11427 +/* 11417 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 11427 +/* 11422 */ MCD_OPC_Decode, 195, 21, 160, 2, // Opcode: VMAOF +/* 11427 */ MCD_OPC_CheckPredicate, 34, 36, 46, 0, // Skip to: 23244 +/* 11432 */ MCD_OPC_Decode, 193, 21, 164, 2, // Opcode: VMAO +/* 11437 */ MCD_OPC_FilterValue, 180, 1, 89, 0, 0, // Skip to: 11532 +/* 11443 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 11446 */ MCD_OPC_FilterValue, 0, 17, 46, 0, // Skip to: 23244 +/* 11451 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 11454 */ MCD_OPC_FilterValue, 0, 9, 46, 0, // Skip to: 23244 +/* 11459 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 11462 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11477 +/* 11467 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 11522 +/* 11472 */ MCD_OPC_Decode, 206, 20, 239, 1, // Opcode: VGFMB +/* 11477 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 11492 +/* 11482 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 11522 +/* 11487 */ MCD_OPC_Decode, 209, 20, 239, 1, // Opcode: VGFMH +/* 11492 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 11507 +/* 11497 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 11522 +/* 11502 */ MCD_OPC_Decode, 207, 20, 239, 1, // Opcode: VGFMF +/* 11507 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 11522 +/* 11512 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 11522 +/* 11517 */ MCD_OPC_Decode, 208, 20, 239, 1, // Opcode: VGFMG +/* 11522 */ MCD_OPC_CheckPredicate, 34, 197, 45, 0, // Skip to: 23244 +/* 11527 */ MCD_OPC_Decode, 200, 20, 147, 2, // Opcode: VGFM +/* 11532 */ MCD_OPC_FilterValue, 184, 1, 35, 0, 0, // Skip to: 11573 +/* 11538 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 11541 */ MCD_OPC_FilterValue, 0, 178, 45, 0, // Skip to: 23244 +/* 11546 */ MCD_OPC_CheckPredicate, 35, 12, 0, 0, // Skip to: 11563 +/* 11551 */ MCD_OPC_CheckField, 24, 4, 3, 5, 0, 0, // Skip to: 11563 +/* 11558 */ MCD_OPC_Decode, 247, 21, 158, 2, // Opcode: VMSLG +/* 11563 */ MCD_OPC_CheckPredicate, 35, 156, 45, 0, // Skip to: 23244 +/* 11568 */ MCD_OPC_Decode, 246, 21, 159, 2, // Opcode: VMSL +/* 11573 */ MCD_OPC_FilterValue, 185, 1, 35, 0, 0, // Skip to: 11614 +/* 11579 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 11582 */ MCD_OPC_FilterValue, 0, 137, 45, 0, // Skip to: 23244 +/* 11587 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 11604 +/* 11592 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, 0, // Skip to: 11604 +/* 11599 */ MCD_OPC_Decode, 189, 18, 160, 2, // Opcode: VACCCQ +/* 11604 */ MCD_OPC_CheckPredicate, 34, 115, 45, 0, // Skip to: 23244 +/* 11609 */ MCD_OPC_Decode, 188, 18, 164, 2, // Opcode: VACCC +/* 11614 */ MCD_OPC_FilterValue, 187, 1, 35, 0, 0, // Skip to: 11655 +/* 11620 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 11623 */ MCD_OPC_FilterValue, 0, 96, 45, 0, // Skip to: 23244 +/* 11628 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 11645 +/* 11633 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, 0, // Skip to: 11645 +/* 11640 */ MCD_OPC_Decode, 194, 18, 160, 2, // Opcode: VACQ +/* 11645 */ MCD_OPC_CheckPredicate, 34, 74, 45, 0, // Skip to: 23244 +/* 11650 */ MCD_OPC_Decode, 185, 18, 164, 2, // Opcode: VAC +/* 11655 */ MCD_OPC_FilterValue, 188, 1, 81, 0, 0, // Skip to: 11742 +/* 11661 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 11664 */ MCD_OPC_FilterValue, 0, 55, 45, 0, // Skip to: 23244 +/* 11669 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 11672 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11687 +/* 11677 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 11732 +/* 11682 */ MCD_OPC_Decode, 202, 20, 160, 2, // Opcode: VGFMAB +/* 11687 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 11702 +/* 11692 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 11732 +/* 11697 */ MCD_OPC_Decode, 205, 20, 160, 2, // Opcode: VGFMAH +/* 11702 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 11717 +/* 11707 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 11732 +/* 11712 */ MCD_OPC_Decode, 203, 20, 160, 2, // Opcode: VGFMAF +/* 11717 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 11732 +/* 11722 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 11732 +/* 11727 */ MCD_OPC_Decode, 204, 20, 160, 2, // Opcode: VGFMAG +/* 11732 */ MCD_OPC_CheckPredicate, 34, 243, 44, 0, // Skip to: 23244 +/* 11737 */ MCD_OPC_Decode, 201, 20, 164, 2, // Opcode: VGFMA +/* 11742 */ MCD_OPC_FilterValue, 189, 1, 35, 0, 0, // Skip to: 11783 +/* 11748 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 11751 */ MCD_OPC_FilterValue, 0, 224, 44, 0, // Skip to: 23244 +/* 11756 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 11773 +/* 11761 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, 0, // Skip to: 11773 +/* 11768 */ MCD_OPC_Decode, 181, 22, 160, 2, // Opcode: VSBCBIQ +/* 11773 */ MCD_OPC_CheckPredicate, 34, 202, 44, 0, // Skip to: 23244 +/* 11778 */ MCD_OPC_Decode, 180, 22, 164, 2, // Opcode: VSBCBI +/* 11783 */ MCD_OPC_FilterValue, 191, 1, 35, 0, 0, // Skip to: 11824 +/* 11789 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 11792 */ MCD_OPC_FilterValue, 0, 183, 44, 0, // Skip to: 23244 +/* 11797 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 11814 +/* 11802 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, 0, // Skip to: 11814 +/* 11809 */ MCD_OPC_Decode, 183, 22, 160, 2, // Opcode: VSBIQ +/* 11814 */ MCD_OPC_CheckPredicate, 34, 161, 44, 0, // Skip to: 23244 +/* 11819 */ MCD_OPC_Decode, 182, 22, 164, 2, // Opcode: VSBI +/* 11824 */ MCD_OPC_FilterValue, 192, 1, 93, 0, 0, // Skip to: 11923 +/* 11830 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 11833 */ MCD_OPC_FilterValue, 0, 142, 44, 0, // Skip to: 23244 +/* 11838 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11841 */ MCD_OPC_FilterValue, 0, 134, 44, 0, // Skip to: 23244 +/* 11846 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 11849 */ MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 11881 +/* 11854 */ MCD_OPC_CheckPredicate, 29, 12, 0, 0, // Skip to: 11871 +/* 11859 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, 0, // Skip to: 11871 +/* 11866 */ MCD_OPC_Decode, 172, 23, 165, 2, // Opcode: WCLFEB +/* 11871 */ MCD_OPC_CheckPredicate, 29, 37, 0, 0, // Skip to: 11913 +/* 11876 */ MCD_OPC_Decode, 251, 18, 166, 2, // Opcode: VCLFEB +/* 11881 */ MCD_OPC_FilterValue, 3, 27, 0, 0, // Skip to: 11913 +/* 11886 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 11903 +/* 11891 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, 0, // Skip to: 11903 +/* 11898 */ MCD_OPC_Decode, 173, 23, 167, 2, // Opcode: WCLGDB +/* 11903 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 11913 +/* 11908 */ MCD_OPC_Decode, 128, 19, 166, 2, // Opcode: VCLGDB +/* 11913 */ MCD_OPC_CheckPredicate, 34, 62, 44, 0, // Skip to: 23244 +/* 11918 */ MCD_OPC_Decode, 255, 18, 168, 2, // Opcode: VCLGD +/* 11923 */ MCD_OPC_FilterValue, 193, 1, 93, 0, 0, // Skip to: 12022 +/* 11929 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 11932 */ MCD_OPC_FilterValue, 0, 43, 44, 0, // Skip to: 23244 +/* 11937 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11940 */ MCD_OPC_FilterValue, 0, 35, 44, 0, // Skip to: 23244 +/* 11945 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 11948 */ MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 11980 +/* 11953 */ MCD_OPC_CheckPredicate, 29, 12, 0, 0, // Skip to: 11970 +/* 11958 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, 0, // Skip to: 11970 +/* 11965 */ MCD_OPC_Decode, 169, 23, 165, 2, // Opcode: WCELFB +/* 11970 */ MCD_OPC_CheckPredicate, 29, 37, 0, 0, // Skip to: 12012 +/* 11975 */ MCD_OPC_Decode, 216, 18, 166, 2, // Opcode: VCELFB +/* 11980 */ MCD_OPC_FilterValue, 3, 27, 0, 0, // Skip to: 12012 +/* 11985 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 12002 +/* 11990 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, 0, // Skip to: 12002 +/* 11997 */ MCD_OPC_Decode, 167, 23, 167, 2, // Opcode: WCDLGB +/* 12002 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 12012 +/* 12007 */ MCD_OPC_Decode, 214, 18, 166, 2, // Opcode: VCDLGB +/* 12012 */ MCD_OPC_CheckPredicate, 34, 219, 43, 0, // Skip to: 23244 +/* 12017 */ MCD_OPC_Decode, 213, 18, 168, 2, // Opcode: VCDLG +/* 12022 */ MCD_OPC_FilterValue, 194, 1, 93, 0, 0, // Skip to: 12121 +/* 12028 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 12031 */ MCD_OPC_FilterValue, 0, 200, 43, 0, // Skip to: 23244 +/* 12036 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 12039 */ MCD_OPC_FilterValue, 0, 192, 43, 0, // Skip to: 23244 +/* 12044 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 12047 */ MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 12079 +/* 12052 */ MCD_OPC_CheckPredicate, 29, 12, 0, 0, // Skip to: 12069 +/* 12057 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, 0, // Skip to: 12069 +/* 12064 */ MCD_OPC_Decode, 170, 23, 165, 2, // Opcode: WCFEB +/* 12069 */ MCD_OPC_CheckPredicate, 29, 37, 0, 0, // Skip to: 12111 +/* 12074 */ MCD_OPC_Decode, 226, 18, 166, 2, // Opcode: VCFEB +/* 12079 */ MCD_OPC_FilterValue, 3, 27, 0, 0, // Skip to: 12111 +/* 12084 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 12101 +/* 12089 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, 0, // Skip to: 12101 +/* 12096 */ MCD_OPC_Decode, 171, 23, 167, 2, // Opcode: WCGDB +/* 12101 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 12111 +/* 12106 */ MCD_OPC_Decode, 231, 18, 166, 2, // Opcode: VCGDB +/* 12111 */ MCD_OPC_CheckPredicate, 34, 120, 43, 0, // Skip to: 23244 +/* 12116 */ MCD_OPC_Decode, 230, 18, 168, 2, // Opcode: VCGD +/* 12121 */ MCD_OPC_FilterValue, 195, 1, 93, 0, 0, // Skip to: 12220 +/* 12127 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 12130 */ MCD_OPC_FilterValue, 0, 101, 43, 0, // Skip to: 23244 +/* 12135 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 12138 */ MCD_OPC_FilterValue, 0, 93, 43, 0, // Skip to: 23244 +/* 12143 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 12146 */ MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 12178 +/* 12151 */ MCD_OPC_CheckPredicate, 29, 12, 0, 0, // Skip to: 12168 +/* 12156 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, 0, // Skip to: 12168 +/* 12163 */ MCD_OPC_Decode, 168, 23, 165, 2, // Opcode: WCEFB +/* 12168 */ MCD_OPC_CheckPredicate, 29, 37, 0, 0, // Skip to: 12210 +/* 12173 */ MCD_OPC_Decode, 215, 18, 166, 2, // Opcode: VCEFB +/* 12178 */ MCD_OPC_FilterValue, 3, 27, 0, 0, // Skip to: 12210 +/* 12183 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 12200 +/* 12188 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, 0, // Skip to: 12200 +/* 12195 */ MCD_OPC_Decode, 166, 23, 167, 2, // Opcode: WCDGB +/* 12200 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 12210 +/* 12205 */ MCD_OPC_Decode, 212, 18, 166, 2, // Opcode: VCDGB +/* 12210 */ MCD_OPC_CheckPredicate, 34, 21, 43, 0, // Skip to: 23244 +/* 12215 */ MCD_OPC_Decode, 211, 18, 168, 2, // Opcode: VCDG +/* 12220 */ MCD_OPC_FilterValue, 196, 1, 76, 0, 0, // Skip to: 12302 +/* 12226 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 12229 */ MCD_OPC_FilterValue, 0, 2, 43, 0, // Skip to: 23244 +/* 12234 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... +/* 12237 */ MCD_OPC_FilterValue, 0, 250, 42, 0, // Skip to: 23244 +/* 12242 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 12245 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 12260 +/* 12250 */ MCD_OPC_CheckPredicate, 34, 37, 0, 0, // Skip to: 12292 +/* 12255 */ MCD_OPC_Decode, 240, 20, 144, 2, // Opcode: VLDEB +/* 12260 */ MCD_OPC_FilterValue, 130, 1, 10, 0, 0, // Skip to: 12276 +/* 12266 */ MCD_OPC_CheckPredicate, 34, 21, 0, 0, // Skip to: 12292 +/* 12271 */ MCD_OPC_Decode, 145, 24, 169, 2, // Opcode: WLDEB +/* 12276 */ MCD_OPC_FilterValue, 131, 1, 10, 0, 0, // Skip to: 12292 +/* 12282 */ MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 12292 +/* 12287 */ MCD_OPC_Decode, 230, 23, 170, 2, // Opcode: WFLLD +/* 12292 */ MCD_OPC_CheckPredicate, 34, 195, 42, 0, // Skip to: 23244 +/* 12297 */ MCD_OPC_Decode, 239, 20, 229, 1, // Opcode: VLDE +/* 12302 */ MCD_OPC_FilterValue, 197, 1, 83, 0, 0, // Skip to: 12391 +/* 12308 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 12311 */ MCD_OPC_FilterValue, 0, 176, 42, 0, // Skip to: 23244 +/* 12316 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 12319 */ MCD_OPC_FilterValue, 0, 168, 42, 0, // Skip to: 23244 +/* 12324 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 12327 */ MCD_OPC_FilterValue, 3, 27, 0, 0, // Skip to: 12359 +/* 12332 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 12349 +/* 12337 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, 0, // Skip to: 12349 +/* 12344 */ MCD_OPC_Decode, 146, 24, 171, 2, // Opcode: WLEDB +/* 12349 */ MCD_OPC_CheckPredicate, 34, 27, 0, 0, // Skip to: 12381 +/* 12354 */ MCD_OPC_Decode, 246, 20, 166, 2, // Opcode: VLEDB +/* 12359 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 12381 +/* 12364 */ MCD_OPC_CheckPredicate, 35, 12, 0, 0, // Skip to: 12381 +/* 12369 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, 0, // Skip to: 12381 +/* 12376 */ MCD_OPC_Decode, 239, 23, 172, 2, // Opcode: WFLRX +/* 12381 */ MCD_OPC_CheckPredicate, 34, 106, 42, 0, // Skip to: 23244 +/* 12386 */ MCD_OPC_Decode, 245, 20, 168, 2, // Opcode: VLED +/* 12391 */ MCD_OPC_FilterValue, 199, 1, 115, 0, 0, // Skip to: 12512 +/* 12397 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 12400 */ MCD_OPC_FilterValue, 0, 87, 42, 0, // Skip to: 23244 +/* 12405 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 12408 */ MCD_OPC_FilterValue, 0, 79, 42, 0, // Skip to: 23244 +/* 12413 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 12416 */ MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 12448 +/* 12421 */ MCD_OPC_CheckPredicate, 35, 12, 0, 0, // Skip to: 12438 +/* 12426 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, 0, // Skip to: 12438 +/* 12433 */ MCD_OPC_Decode, 203, 23, 165, 2, // Opcode: WFISB +/* 12438 */ MCD_OPC_CheckPredicate, 35, 59, 0, 0, // Skip to: 12502 +/* 12443 */ MCD_OPC_Decode, 141, 20, 166, 2, // Opcode: VFISB +/* 12448 */ MCD_OPC_FilterValue, 3, 27, 0, 0, // Skip to: 12480 +/* 12453 */ MCD_OPC_CheckPredicate, 34, 12, 0, 0, // Skip to: 12470 +/* 12458 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, 0, // Skip to: 12470 +/* 12465 */ MCD_OPC_Decode, 202, 23, 167, 2, // Opcode: WFIDB +/* 12470 */ MCD_OPC_CheckPredicate, 34, 27, 0, 0, // Skip to: 12502 +/* 12475 */ MCD_OPC_Decode, 140, 20, 166, 2, // Opcode: VFIDB +/* 12480 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 12502 +/* 12485 */ MCD_OPC_CheckPredicate, 35, 12, 0, 0, // Skip to: 12502 +/* 12490 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, 0, // Skip to: 12502 +/* 12497 */ MCD_OPC_Decode, 204, 23, 173, 2, // Opcode: WFIXB +/* 12502 */ MCD_OPC_CheckPredicate, 34, 241, 41, 0, // Skip to: 23244 +/* 12507 */ MCD_OPC_Decode, 139, 20, 168, 2, // Opcode: VFI +/* 12512 */ MCD_OPC_FilterValue, 202, 1, 74, 0, 0, // Skip to: 12592 +/* 12518 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 12521 */ MCD_OPC_FilterValue, 0, 222, 41, 0, // Skip to: 23244 +/* 12526 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... +/* 12529 */ MCD_OPC_FilterValue, 0, 214, 41, 0, // Skip to: 23244 +/* 12534 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 12537 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 12552 +/* 12542 */ MCD_OPC_CheckPredicate, 35, 35, 0, 0, // Skip to: 12582 +/* 12547 */ MCD_OPC_Decode, 225, 23, 174, 2, // Opcode: WFKSB +/* 12552 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 12567 +/* 12557 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 12582 +/* 12562 */ MCD_OPC_Decode, 206, 23, 175, 2, // Opcode: WFKDB +/* 12567 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 12582 +/* 12572 */ MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 12582 +/* 12577 */ MCD_OPC_Decode, 226, 23, 144, 2, // Opcode: WFKXB +/* 12582 */ MCD_OPC_CheckPredicate, 34, 161, 41, 0, // Skip to: 23244 +/* 12587 */ MCD_OPC_Decode, 205, 23, 176, 2, // Opcode: WFK +/* 12592 */ MCD_OPC_FilterValue, 203, 1, 74, 0, 0, // Skip to: 12672 +/* 12598 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 12601 */ MCD_OPC_FilterValue, 0, 142, 41, 0, // Skip to: 23244 +/* 12606 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... +/* 12609 */ MCD_OPC_FilterValue, 0, 134, 41, 0, // Skip to: 23244 +/* 12614 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 12617 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 12632 +/* 12622 */ MCD_OPC_CheckPredicate, 35, 35, 0, 0, // Skip to: 12662 +/* 12627 */ MCD_OPC_Decode, 197, 23, 174, 2, // Opcode: WFCSB +/* 12632 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 12647 +/* 12637 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 12662 +/* 12642 */ MCD_OPC_Decode, 178, 23, 175, 2, // Opcode: WFCDB +/* 12647 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 12662 +/* 12652 */ MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 12662 +/* 12657 */ MCD_OPC_Decode, 198, 23, 144, 2, // Opcode: WFCXB +/* 12662 */ MCD_OPC_CheckPredicate, 34, 81, 41, 0, // Skip to: 23244 +/* 12667 */ MCD_OPC_Decode, 177, 23, 176, 2, // Opcode: WFC +/* 12672 */ MCD_OPC_FilterValue, 204, 1, 92, 1, 0, // Skip to: 13026 +/* 12678 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 12681 */ MCD_OPC_FilterValue, 0, 62, 41, 0, // Skip to: 23244 +/* 12686 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 12689 */ MCD_OPC_FilterValue, 0, 54, 41, 0, // Skip to: 23244 +/* 12694 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... +/* 12697 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 12712 +/* 12702 */ MCD_OPC_CheckPredicate, 35, 228, 0, 0, // Skip to: 12935 +/* 12707 */ MCD_OPC_Decode, 155, 20, 144, 2, // Opcode: VFLCSB +/* 12712 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 12727 +/* 12717 */ MCD_OPC_CheckPredicate, 34, 213, 0, 0, // Skip to: 12935 +/* 12722 */ MCD_OPC_Decode, 154, 20, 144, 2, // Opcode: VFLCDB +/* 12727 */ MCD_OPC_FilterValue, 130, 1, 10, 0, 0, // Skip to: 12743 +/* 12733 */ MCD_OPC_CheckPredicate, 35, 197, 0, 0, // Skip to: 12935 +/* 12738 */ MCD_OPC_Decode, 228, 23, 174, 2, // Opcode: WFLCSB +/* 12743 */ MCD_OPC_FilterValue, 131, 1, 10, 0, 0, // Skip to: 12759 +/* 12749 */ MCD_OPC_CheckPredicate, 34, 181, 0, 0, // Skip to: 12935 +/* 12754 */ MCD_OPC_Decode, 227, 23, 175, 2, // Opcode: WFLCDB +/* 12759 */ MCD_OPC_FilterValue, 132, 1, 10, 0, 0, // Skip to: 12775 +/* 12765 */ MCD_OPC_CheckPredicate, 35, 165, 0, 0, // Skip to: 12935 +/* 12770 */ MCD_OPC_Decode, 229, 23, 144, 2, // Opcode: WFLCXB +/* 12775 */ MCD_OPC_FilterValue, 130, 2, 10, 0, 0, // Skip to: 12791 +/* 12781 */ MCD_OPC_CheckPredicate, 35, 149, 0, 0, // Skip to: 12935 +/* 12786 */ MCD_OPC_Decode, 159, 20, 144, 2, // Opcode: VFLNSB +/* 12791 */ MCD_OPC_FilterValue, 131, 2, 10, 0, 0, // Skip to: 12807 +/* 12797 */ MCD_OPC_CheckPredicate, 34, 133, 0, 0, // Skip to: 12935 +/* 12802 */ MCD_OPC_Decode, 158, 20, 144, 2, // Opcode: VFLNDB +/* 12807 */ MCD_OPC_FilterValue, 130, 3, 10, 0, 0, // Skip to: 12823 +/* 12813 */ MCD_OPC_CheckPredicate, 35, 117, 0, 0, // Skip to: 12935 +/* 12818 */ MCD_OPC_Decode, 233, 23, 174, 2, // Opcode: WFLNSB +/* 12823 */ MCD_OPC_FilterValue, 131, 3, 10, 0, 0, // Skip to: 12839 +/* 12829 */ MCD_OPC_CheckPredicate, 34, 101, 0, 0, // Skip to: 12935 +/* 12834 */ MCD_OPC_Decode, 232, 23, 175, 2, // Opcode: WFLNDB +/* 12839 */ MCD_OPC_FilterValue, 132, 3, 10, 0, 0, // Skip to: 12855 +/* 12845 */ MCD_OPC_CheckPredicate, 35, 85, 0, 0, // Skip to: 12935 +/* 12850 */ MCD_OPC_Decode, 234, 23, 144, 2, // Opcode: WFLNXB +/* 12855 */ MCD_OPC_FilterValue, 130, 4, 10, 0, 0, // Skip to: 12871 +/* 12861 */ MCD_OPC_CheckPredicate, 35, 69, 0, 0, // Skip to: 12935 +/* 12866 */ MCD_OPC_Decode, 161, 20, 144, 2, // Opcode: VFLPSB +/* 12871 */ MCD_OPC_FilterValue, 131, 4, 10, 0, 0, // Skip to: 12887 +/* 12877 */ MCD_OPC_CheckPredicate, 34, 53, 0, 0, // Skip to: 12935 +/* 12882 */ MCD_OPC_Decode, 160, 20, 144, 2, // Opcode: VFLPDB +/* 12887 */ MCD_OPC_FilterValue, 130, 5, 10, 0, 0, // Skip to: 12903 +/* 12893 */ MCD_OPC_CheckPredicate, 35, 37, 0, 0, // Skip to: 12935 +/* 12898 */ MCD_OPC_Decode, 236, 23, 174, 2, // Opcode: WFLPSB +/* 12903 */ MCD_OPC_FilterValue, 131, 5, 10, 0, 0, // Skip to: 12919 +/* 12909 */ MCD_OPC_CheckPredicate, 34, 21, 0, 0, // Skip to: 12935 +/* 12914 */ MCD_OPC_Decode, 235, 23, 175, 2, // Opcode: WFLPDB +/* 12919 */ MCD_OPC_FilterValue, 132, 5, 10, 0, 0, // Skip to: 12935 +/* 12925 */ MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 12935 +/* 12930 */ MCD_OPC_Decode, 237, 23, 144, 2, // Opcode: WFLPXB +/* 12935 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 12938 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 12953 +/* 12943 */ MCD_OPC_CheckPredicate, 35, 68, 0, 0, // Skip to: 13016 +/* 12948 */ MCD_OPC_Decode, 187, 20, 226, 1, // Opcode: VFPSOSB +/* 12953 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 12968 +/* 12958 */ MCD_OPC_CheckPredicate, 34, 53, 0, 0, // Skip to: 13016 +/* 12963 */ MCD_OPC_Decode, 186, 20, 226, 1, // Opcode: VFPSODB +/* 12968 */ MCD_OPC_FilterValue, 130, 1, 10, 0, 0, // Skip to: 12984 +/* 12974 */ MCD_OPC_CheckPredicate, 35, 37, 0, 0, // Skip to: 13016 +/* 12979 */ MCD_OPC_Decode, 134, 24, 177, 2, // Opcode: WFPSOSB +/* 12984 */ MCD_OPC_FilterValue, 131, 1, 10, 0, 0, // Skip to: 13000 +/* 12990 */ MCD_OPC_CheckPredicate, 34, 21, 0, 0, // Skip to: 13016 +/* 12995 */ MCD_OPC_Decode, 133, 24, 178, 2, // Opcode: WFPSODB +/* 13000 */ MCD_OPC_FilterValue, 132, 1, 10, 0, 0, // Skip to: 13016 +/* 13006 */ MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 13016 +/* 13011 */ MCD_OPC_Decode, 135, 24, 226, 1, // Opcode: WFPSOXB +/* 13016 */ MCD_OPC_CheckPredicate, 34, 239, 39, 0, // Skip to: 23244 +/* 13021 */ MCD_OPC_Decode, 185, 20, 168, 2, // Opcode: VFPSO +/* 13026 */ MCD_OPC_FilterValue, 206, 1, 107, 0, 0, // Skip to: 13139 +/* 13032 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 13035 */ MCD_OPC_FilterValue, 0, 220, 39, 0, // Skip to: 23244 +/* 13040 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... +/* 13043 */ MCD_OPC_FilterValue, 0, 212, 39, 0, // Skip to: 23244 +/* 13048 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 13051 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 13066 +/* 13056 */ MCD_OPC_CheckPredicate, 35, 68, 0, 0, // Skip to: 13129 +/* 13061 */ MCD_OPC_Decode, 192, 20, 144, 2, // Opcode: VFSQSB +/* 13066 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 13081 +/* 13071 */ MCD_OPC_CheckPredicate, 34, 53, 0, 0, // Skip to: 13129 +/* 13076 */ MCD_OPC_Decode, 191, 20, 144, 2, // Opcode: VFSQDB +/* 13081 */ MCD_OPC_FilterValue, 130, 1, 10, 0, 0, // Skip to: 13097 +/* 13087 */ MCD_OPC_CheckPredicate, 35, 37, 0, 0, // Skip to: 13129 +/* 13092 */ MCD_OPC_Decode, 138, 24, 174, 2, // Opcode: WFSQSB +/* 13097 */ MCD_OPC_FilterValue, 131, 1, 10, 0, 0, // Skip to: 13113 +/* 13103 */ MCD_OPC_CheckPredicate, 34, 21, 0, 0, // Skip to: 13129 +/* 13108 */ MCD_OPC_Decode, 137, 24, 175, 2, // Opcode: WFSQDB +/* 13113 */ MCD_OPC_FilterValue, 132, 1, 10, 0, 0, // Skip to: 13129 +/* 13119 */ MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 13129 +/* 13124 */ MCD_OPC_Decode, 139, 24, 144, 2, // Opcode: WFSQXB +/* 13129 */ MCD_OPC_CheckPredicate, 34, 126, 39, 0, // Skip to: 23244 +/* 13134 */ MCD_OPC_Decode, 190, 20, 229, 1, // Opcode: VFSQ +/* 13139 */ MCD_OPC_FilterValue, 212, 1, 74, 0, 0, // Skip to: 13219 +/* 13145 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 13148 */ MCD_OPC_FilterValue, 0, 107, 39, 0, // Skip to: 23244 +/* 13153 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 13156 */ MCD_OPC_FilterValue, 0, 99, 39, 0, // Skip to: 23244 +/* 13161 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 13164 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13179 +/* 13169 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 13209 +/* 13174 */ MCD_OPC_Decode, 161, 23, 144, 2, // Opcode: VUPLLB +/* 13179 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 13194 +/* 13184 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 13209 +/* 13189 */ MCD_OPC_Decode, 163, 23, 144, 2, // Opcode: VUPLLH +/* 13194 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 13209 +/* 13199 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 13209 +/* 13204 */ MCD_OPC_Decode, 162, 23, 144, 2, // Opcode: VUPLLF +/* 13209 */ MCD_OPC_CheckPredicate, 34, 46, 39, 0, // Skip to: 23244 +/* 13214 */ MCD_OPC_Decode, 160, 23, 145, 2, // Opcode: VUPLL +/* 13219 */ MCD_OPC_FilterValue, 213, 1, 74, 0, 0, // Skip to: 13299 +/* 13225 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 13228 */ MCD_OPC_FilterValue, 0, 27, 39, 0, // Skip to: 23244 +/* 13233 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 13236 */ MCD_OPC_FilterValue, 0, 19, 39, 0, // Skip to: 23244 +/* 13241 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 13244 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13259 +/* 13249 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 13289 +/* 13254 */ MCD_OPC_Decode, 156, 23, 144, 2, // Opcode: VUPLHB +/* 13259 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 13274 +/* 13264 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 13289 +/* 13269 */ MCD_OPC_Decode, 158, 23, 144, 2, // Opcode: VUPLHH +/* 13274 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 13289 +/* 13279 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 13289 +/* 13284 */ MCD_OPC_Decode, 157, 23, 144, 2, // Opcode: VUPLHF +/* 13289 */ MCD_OPC_CheckPredicate, 34, 222, 38, 0, // Skip to: 23244 +/* 13294 */ MCD_OPC_Decode, 155, 23, 145, 2, // Opcode: VUPLH +/* 13299 */ MCD_OPC_FilterValue, 214, 1, 74, 0, 0, // Skip to: 13379 +/* 13305 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 13308 */ MCD_OPC_FilterValue, 0, 203, 38, 0, // Skip to: 23244 +/* 13313 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 13316 */ MCD_OPC_FilterValue, 0, 195, 38, 0, // Skip to: 23244 +/* 13321 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 13324 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13339 +/* 13329 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 13369 +/* 13334 */ MCD_OPC_Decode, 153, 23, 144, 2, // Opcode: VUPLB +/* 13339 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 13354 +/* 13344 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 13369 +/* 13349 */ MCD_OPC_Decode, 159, 23, 144, 2, // Opcode: VUPLHW +/* 13354 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 13369 +/* 13359 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 13369 +/* 13364 */ MCD_OPC_Decode, 154, 23, 144, 2, // Opcode: VUPLF +/* 13369 */ MCD_OPC_CheckPredicate, 34, 142, 38, 0, // Skip to: 23244 +/* 13374 */ MCD_OPC_Decode, 152, 23, 145, 2, // Opcode: VUPL +/* 13379 */ MCD_OPC_FilterValue, 215, 1, 74, 0, 0, // Skip to: 13459 +/* 13385 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 13388 */ MCD_OPC_FilterValue, 0, 123, 38, 0, // Skip to: 23244 +/* 13393 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 13396 */ MCD_OPC_FilterValue, 0, 115, 38, 0, // Skip to: 23244 +/* 13401 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 13404 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13419 +/* 13409 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 13449 +/* 13414 */ MCD_OPC_Decode, 146, 23, 144, 2, // Opcode: VUPHB +/* 13419 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 13434 +/* 13424 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 13449 +/* 13429 */ MCD_OPC_Decode, 148, 23, 144, 2, // Opcode: VUPHH +/* 13434 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 13449 +/* 13439 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 13449 +/* 13444 */ MCD_OPC_Decode, 147, 23, 144, 2, // Opcode: VUPHF +/* 13449 */ MCD_OPC_CheckPredicate, 34, 62, 38, 0, // Skip to: 23244 +/* 13454 */ MCD_OPC_Decode, 145, 23, 145, 2, // Opcode: VUPH +/* 13459 */ MCD_OPC_FilterValue, 216, 1, 24, 0, 0, // Skip to: 13489 +/* 13465 */ MCD_OPC_CheckPredicate, 34, 46, 38, 0, // Skip to: 23244 +/* 13470 */ MCD_OPC_CheckField, 12, 20, 0, 39, 38, 0, // Skip to: 23244 +/* 13477 */ MCD_OPC_CheckField, 8, 2, 0, 32, 38, 0, // Skip to: 23244 +/* 13484 */ MCD_OPC_Decode, 143, 23, 144, 2, // Opcode: VTM +/* 13489 */ MCD_OPC_FilterValue, 217, 1, 89, 0, 0, // Skip to: 13584 +/* 13495 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 13498 */ MCD_OPC_FilterValue, 0, 13, 38, 0, // Skip to: 23244 +/* 13503 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 13506 */ MCD_OPC_FilterValue, 0, 5, 38, 0, // Skip to: 23244 +/* 13511 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 13514 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13529 +/* 13519 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 13574 +/* 13524 */ MCD_OPC_Decode, 158, 19, 144, 2, // Opcode: VECLB +/* 13529 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 13544 +/* 13534 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 13574 +/* 13539 */ MCD_OPC_Decode, 161, 19, 144, 2, // Opcode: VECLH +/* 13544 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 13559 +/* 13549 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 13574 +/* 13554 */ MCD_OPC_Decode, 159, 19, 144, 2, // Opcode: VECLF +/* 13559 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 13574 +/* 13564 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 13574 +/* 13569 */ MCD_OPC_Decode, 160, 19, 144, 2, // Opcode: VECLG +/* 13574 */ MCD_OPC_CheckPredicate, 34, 193, 37, 0, // Skip to: 23244 +/* 13579 */ MCD_OPC_Decode, 157, 19, 145, 2, // Opcode: VECL +/* 13584 */ MCD_OPC_FilterValue, 219, 1, 89, 0, 0, // Skip to: 13679 +/* 13590 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 13593 */ MCD_OPC_FilterValue, 0, 174, 37, 0, // Skip to: 23244 +/* 13598 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 13601 */ MCD_OPC_FilterValue, 0, 166, 37, 0, // Skip to: 23244 +/* 13606 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 13609 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13624 +/* 13614 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 13669 +/* 13619 */ MCD_OPC_Decode, 153, 19, 144, 2, // Opcode: VECB +/* 13624 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 13639 +/* 13629 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 13669 +/* 13634 */ MCD_OPC_Decode, 156, 19, 144, 2, // Opcode: VECH +/* 13639 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 13654 +/* 13644 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 13669 +/* 13649 */ MCD_OPC_Decode, 154, 19, 144, 2, // Opcode: VECF +/* 13654 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 13669 +/* 13659 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 13669 +/* 13664 */ MCD_OPC_Decode, 155, 19, 144, 2, // Opcode: VECG +/* 13669 */ MCD_OPC_CheckPredicate, 34, 98, 37, 0, // Skip to: 23244 +/* 13674 */ MCD_OPC_Decode, 152, 19, 145, 2, // Opcode: VEC +/* 13679 */ MCD_OPC_FilterValue, 222, 1, 89, 0, 0, // Skip to: 13774 +/* 13685 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 13688 */ MCD_OPC_FilterValue, 0, 79, 37, 0, // Skip to: 23244 +/* 13693 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 13696 */ MCD_OPC_FilterValue, 0, 71, 37, 0, // Skip to: 23244 +/* 13701 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 13704 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13719 +/* 13709 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 13764 +/* 13714 */ MCD_OPC_Decode, 235, 20, 144, 2, // Opcode: VLCB +/* 13719 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 13734 +/* 13724 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 13764 +/* 13729 */ MCD_OPC_Decode, 238, 20, 144, 2, // Opcode: VLCH +/* 13734 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 13749 +/* 13739 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 13764 +/* 13744 */ MCD_OPC_Decode, 236, 20, 144, 2, // Opcode: VLCF +/* 13749 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 13764 +/* 13754 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 13764 +/* 13759 */ MCD_OPC_Decode, 237, 20, 144, 2, // Opcode: VLCG +/* 13764 */ MCD_OPC_CheckPredicate, 34, 3, 37, 0, // Skip to: 23244 +/* 13769 */ MCD_OPC_Decode, 234, 20, 145, 2, // Opcode: VLC +/* 13774 */ MCD_OPC_FilterValue, 223, 1, 89, 0, 0, // Skip to: 13869 +/* 13780 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 13783 */ MCD_OPC_FilterValue, 0, 240, 36, 0, // Skip to: 23244 +/* 13788 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 13791 */ MCD_OPC_FilterValue, 0, 232, 36, 0, // Skip to: 23244 +/* 13796 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 13799 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13814 +/* 13804 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 13859 +/* 13809 */ MCD_OPC_Decode, 151, 21, 144, 2, // Opcode: VLPB +/* 13814 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 13829 +/* 13819 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 13859 +/* 13824 */ MCD_OPC_Decode, 154, 21, 144, 2, // Opcode: VLPH +/* 13829 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 13844 +/* 13834 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 13859 +/* 13839 */ MCD_OPC_Decode, 152, 21, 144, 2, // Opcode: VLPF +/* 13844 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 13859 +/* 13849 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 13859 +/* 13854 */ MCD_OPC_Decode, 153, 21, 144, 2, // Opcode: VLPG +/* 13859 */ MCD_OPC_CheckPredicate, 34, 164, 36, 0, // Skip to: 23244 +/* 13864 */ MCD_OPC_Decode, 150, 21, 145, 2, // Opcode: VLP +/* 13869 */ MCD_OPC_FilterValue, 226, 1, 107, 0, 0, // Skip to: 13982 +/* 13875 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 13878 */ MCD_OPC_FilterValue, 0, 145, 36, 0, // Skip to: 23244 +/* 13883 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... +/* 13886 */ MCD_OPC_FilterValue, 0, 137, 36, 0, // Skip to: 23244 +/* 13891 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 13894 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 13909 +/* 13899 */ MCD_OPC_CheckPredicate, 35, 68, 0, 0, // Skip to: 13972 +/* 13904 */ MCD_OPC_Decode, 193, 20, 239, 1, // Opcode: VFSSB +/* 13909 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 13924 +/* 13914 */ MCD_OPC_CheckPredicate, 34, 53, 0, 0, // Skip to: 13972 +/* 13919 */ MCD_OPC_Decode, 189, 20, 239, 1, // Opcode: VFSDB +/* 13924 */ MCD_OPC_FilterValue, 130, 1, 10, 0, 0, // Skip to: 13940 +/* 13930 */ MCD_OPC_CheckPredicate, 35, 37, 0, 0, // Skip to: 13972 +/* 13935 */ MCD_OPC_Decode, 140, 24, 179, 2, // Opcode: WFSSB +/* 13940 */ MCD_OPC_FilterValue, 131, 1, 10, 0, 0, // Skip to: 13956 +/* 13946 */ MCD_OPC_CheckPredicate, 34, 21, 0, 0, // Skip to: 13972 +/* 13951 */ MCD_OPC_Decode, 136, 24, 180, 2, // Opcode: WFSDB +/* 13956 */ MCD_OPC_FilterValue, 132, 1, 10, 0, 0, // Skip to: 13972 +/* 13962 */ MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 13972 +/* 13967 */ MCD_OPC_Decode, 141, 24, 239, 1, // Opcode: WFSXB +/* 13972 */ MCD_OPC_CheckPredicate, 34, 51, 36, 0, // Skip to: 23244 +/* 13977 */ MCD_OPC_Decode, 188, 20, 237, 1, // Opcode: VFS +/* 13982 */ MCD_OPC_FilterValue, 227, 1, 107, 0, 0, // Skip to: 14095 +/* 13988 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 13991 */ MCD_OPC_FilterValue, 0, 32, 36, 0, // Skip to: 23244 +/* 13996 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... +/* 13999 */ MCD_OPC_FilterValue, 0, 24, 36, 0, // Skip to: 23244 +/* 14004 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 14007 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 14022 +/* 14012 */ MCD_OPC_CheckPredicate, 35, 68, 0, 0, // Skip to: 14085 +/* 14017 */ MCD_OPC_Decode, 222, 19, 239, 1, // Opcode: VFASB +/* 14022 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 14037 +/* 14027 */ MCD_OPC_CheckPredicate, 34, 53, 0, 0, // Skip to: 14085 +/* 14032 */ MCD_OPC_Decode, 208, 19, 239, 1, // Opcode: VFADB +/* 14037 */ MCD_OPC_FilterValue, 130, 1, 10, 0, 0, // Skip to: 14053 +/* 14043 */ MCD_OPC_CheckPredicate, 35, 37, 0, 0, // Skip to: 14085 +/* 14048 */ MCD_OPC_Decode, 175, 23, 179, 2, // Opcode: WFASB +/* 14053 */ MCD_OPC_FilterValue, 131, 1, 10, 0, 0, // Skip to: 14069 +/* 14059 */ MCD_OPC_CheckPredicate, 34, 21, 0, 0, // Skip to: 14085 +/* 14064 */ MCD_OPC_Decode, 174, 23, 180, 2, // Opcode: WFADB +/* 14069 */ MCD_OPC_FilterValue, 132, 1, 10, 0, 0, // Skip to: 14085 +/* 14075 */ MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 14085 +/* 14080 */ MCD_OPC_Decode, 176, 23, 239, 1, // Opcode: WFAXB +/* 14085 */ MCD_OPC_CheckPredicate, 34, 194, 35, 0, // Skip to: 23244 +/* 14090 */ MCD_OPC_Decode, 207, 19, 237, 1, // Opcode: VFA +/* 14095 */ MCD_OPC_FilterValue, 229, 1, 107, 0, 0, // Skip to: 14208 +/* 14101 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 14104 */ MCD_OPC_FilterValue, 0, 175, 35, 0, // Skip to: 23244 +/* 14109 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... +/* 14112 */ MCD_OPC_FilterValue, 0, 167, 35, 0, // Skip to: 23244 +/* 14117 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 14120 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 14135 +/* 14125 */ MCD_OPC_CheckPredicate, 35, 68, 0, 0, // Skip to: 14198 +/* 14130 */ MCD_OPC_Decode, 240, 19, 239, 1, // Opcode: VFDSB +/* 14135 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 14150 +/* 14140 */ MCD_OPC_CheckPredicate, 34, 53, 0, 0, // Skip to: 14198 +/* 14145 */ MCD_OPC_Decode, 239, 19, 239, 1, // Opcode: VFDDB +/* 14150 */ MCD_OPC_FilterValue, 130, 1, 10, 0, 0, // Skip to: 14166 +/* 14156 */ MCD_OPC_CheckPredicate, 35, 37, 0, 0, // Skip to: 14198 +/* 14161 */ MCD_OPC_Decode, 200, 23, 179, 2, // Opcode: WFDSB +/* 14166 */ MCD_OPC_FilterValue, 131, 1, 10, 0, 0, // Skip to: 14182 +/* 14172 */ MCD_OPC_CheckPredicate, 34, 21, 0, 0, // Skip to: 14198 +/* 14177 */ MCD_OPC_Decode, 199, 23, 180, 2, // Opcode: WFDDB +/* 14182 */ MCD_OPC_FilterValue, 132, 1, 10, 0, 0, // Skip to: 14198 +/* 14188 */ MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 14198 +/* 14193 */ MCD_OPC_Decode, 201, 23, 239, 1, // Opcode: WFDXB +/* 14198 */ MCD_OPC_CheckPredicate, 34, 81, 35, 0, // Skip to: 23244 +/* 14203 */ MCD_OPC_Decode, 238, 19, 237, 1, // Opcode: VFD +/* 14208 */ MCD_OPC_FilterValue, 231, 1, 107, 0, 0, // Skip to: 14321 +/* 14214 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 14217 */ MCD_OPC_FilterValue, 0, 62, 35, 0, // Skip to: 23244 +/* 14222 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... +/* 14225 */ MCD_OPC_FilterValue, 0, 54, 35, 0, // Skip to: 23244 +/* 14230 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 14233 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 14248 +/* 14238 */ MCD_OPC_CheckPredicate, 35, 68, 0, 0, // Skip to: 14311 +/* 14243 */ MCD_OPC_Decode, 176, 20, 239, 1, // Opcode: VFMSB +/* 14248 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 14263 +/* 14253 */ MCD_OPC_CheckPredicate, 34, 53, 0, 0, // Skip to: 14311 +/* 14258 */ MCD_OPC_Decode, 171, 20, 239, 1, // Opcode: VFMDB +/* 14263 */ MCD_OPC_FilterValue, 130, 1, 10, 0, 0, // Skip to: 14279 +/* 14269 */ MCD_OPC_CheckPredicate, 35, 37, 0, 0, // Skip to: 14311 +/* 14274 */ MCD_OPC_Decode, 250, 23, 179, 2, // Opcode: WFMSB +/* 14279 */ MCD_OPC_FilterValue, 131, 1, 10, 0, 0, // Skip to: 14295 +/* 14285 */ MCD_OPC_CheckPredicate, 34, 21, 0, 0, // Skip to: 14311 +/* 14290 */ MCD_OPC_Decode, 246, 23, 180, 2, // Opcode: WFMDB +/* 14295 */ MCD_OPC_FilterValue, 132, 1, 10, 0, 0, // Skip to: 14311 +/* 14301 */ MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 14311 +/* 14306 */ MCD_OPC_Decode, 254, 23, 239, 1, // Opcode: WFMXB +/* 14311 */ MCD_OPC_CheckPredicate, 34, 224, 34, 0, // Skip to: 23244 +/* 14316 */ MCD_OPC_Decode, 164, 20, 237, 1, // Opcode: VFM +/* 14321 */ MCD_OPC_FilterValue, 232, 1, 89, 1, 0, // Skip to: 14672 +/* 14327 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 14330 */ MCD_OPC_FilterValue, 0, 205, 34, 0, // Skip to: 23244 +/* 14335 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 14338 */ MCD_OPC_FilterValue, 0, 197, 34, 0, // Skip to: 23244 +/* 14343 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... +/* 14346 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 14361 +/* 14351 */ MCD_OPC_CheckPredicate, 35, 50, 1, 0, // Skip to: 14662 +/* 14356 */ MCD_OPC_Decode, 226, 19, 239, 1, // Opcode: VFCESB +/* 14361 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 14376 +/* 14366 */ MCD_OPC_CheckPredicate, 34, 35, 1, 0, // Skip to: 14662 +/* 14371 */ MCD_OPC_Decode, 224, 19, 239, 1, // Opcode: VFCEDB +/* 14376 */ MCD_OPC_FilterValue, 66, 10, 0, 0, // Skip to: 14391 +/* 14381 */ MCD_OPC_CheckPredicate, 35, 20, 1, 0, // Skip to: 14662 +/* 14386 */ MCD_OPC_Decode, 144, 20, 239, 1, // Opcode: VFKESB +/* 14391 */ MCD_OPC_FilterValue, 67, 10, 0, 0, // Skip to: 14406 +/* 14396 */ MCD_OPC_CheckPredicate, 35, 5, 1, 0, // Skip to: 14662 +/* 14401 */ MCD_OPC_Decode, 142, 20, 239, 1, // Opcode: VFKEDB +/* 14406 */ MCD_OPC_FilterValue, 130, 1, 10, 0, 0, // Skip to: 14422 +/* 14412 */ MCD_OPC_CheckPredicate, 35, 245, 0, 0, // Skip to: 14662 +/* 14417 */ MCD_OPC_Decode, 181, 23, 179, 2, // Opcode: WFCESB +/* 14422 */ MCD_OPC_FilterValue, 131, 1, 10, 0, 0, // Skip to: 14438 +/* 14428 */ MCD_OPC_CheckPredicate, 34, 229, 0, 0, // Skip to: 14662 +/* 14433 */ MCD_OPC_Decode, 179, 23, 180, 2, // Opcode: WFCEDB +/* 14438 */ MCD_OPC_FilterValue, 132, 1, 10, 0, 0, // Skip to: 14454 +/* 14444 */ MCD_OPC_CheckPredicate, 35, 213, 0, 0, // Skip to: 14662 +/* 14449 */ MCD_OPC_Decode, 183, 23, 239, 1, // Opcode: WFCEXB +/* 14454 */ MCD_OPC_FilterValue, 194, 1, 10, 0, 0, // Skip to: 14470 +/* 14460 */ MCD_OPC_CheckPredicate, 35, 197, 0, 0, // Skip to: 14662 +/* 14465 */ MCD_OPC_Decode, 209, 23, 179, 2, // Opcode: WFKESB +/* 14470 */ MCD_OPC_FilterValue, 195, 1, 10, 0, 0, // Skip to: 14486 +/* 14476 */ MCD_OPC_CheckPredicate, 35, 181, 0, 0, // Skip to: 14662 +/* 14481 */ MCD_OPC_Decode, 207, 23, 180, 2, // Opcode: WFKEDB +/* 14486 */ MCD_OPC_FilterValue, 196, 1, 10, 0, 0, // Skip to: 14502 +/* 14492 */ MCD_OPC_CheckPredicate, 35, 165, 0, 0, // Skip to: 14662 +/* 14497 */ MCD_OPC_Decode, 211, 23, 239, 1, // Opcode: WFKEXB +/* 14502 */ MCD_OPC_FilterValue, 130, 2, 10, 0, 0, // Skip to: 14518 +/* 14508 */ MCD_OPC_CheckPredicate, 35, 149, 0, 0, // Skip to: 14662 +/* 14513 */ MCD_OPC_Decode, 227, 19, 239, 1, // Opcode: VFCESBS +/* 14518 */ MCD_OPC_FilterValue, 131, 2, 10, 0, 0, // Skip to: 14534 +/* 14524 */ MCD_OPC_CheckPredicate, 34, 133, 0, 0, // Skip to: 14662 +/* 14529 */ MCD_OPC_Decode, 225, 19, 239, 1, // Opcode: VFCEDBS +/* 14534 */ MCD_OPC_FilterValue, 194, 2, 10, 0, 0, // Skip to: 14550 +/* 14540 */ MCD_OPC_CheckPredicate, 35, 117, 0, 0, // Skip to: 14662 +/* 14545 */ MCD_OPC_Decode, 145, 20, 239, 1, // Opcode: VFKESBS +/* 14550 */ MCD_OPC_FilterValue, 195, 2, 10, 0, 0, // Skip to: 14566 +/* 14556 */ MCD_OPC_CheckPredicate, 35, 101, 0, 0, // Skip to: 14662 +/* 14561 */ MCD_OPC_Decode, 143, 20, 239, 1, // Opcode: VFKEDBS +/* 14566 */ MCD_OPC_FilterValue, 130, 3, 10, 0, 0, // Skip to: 14582 +/* 14572 */ MCD_OPC_CheckPredicate, 35, 85, 0, 0, // Skip to: 14662 +/* 14577 */ MCD_OPC_Decode, 182, 23, 179, 2, // Opcode: WFCESBS +/* 14582 */ MCD_OPC_FilterValue, 131, 3, 10, 0, 0, // Skip to: 14598 +/* 14588 */ MCD_OPC_CheckPredicate, 34, 69, 0, 0, // Skip to: 14662 +/* 14593 */ MCD_OPC_Decode, 180, 23, 180, 2, // Opcode: WFCEDBS +/* 14598 */ MCD_OPC_FilterValue, 132, 3, 10, 0, 0, // Skip to: 14614 +/* 14604 */ MCD_OPC_CheckPredicate, 35, 53, 0, 0, // Skip to: 14662 +/* 14609 */ MCD_OPC_Decode, 184, 23, 239, 1, // Opcode: WFCEXBS +/* 14614 */ MCD_OPC_FilterValue, 194, 3, 10, 0, 0, // Skip to: 14630 +/* 14620 */ MCD_OPC_CheckPredicate, 35, 37, 0, 0, // Skip to: 14662 +/* 14625 */ MCD_OPC_Decode, 210, 23, 179, 2, // Opcode: WFKESBS +/* 14630 */ MCD_OPC_FilterValue, 195, 3, 10, 0, 0, // Skip to: 14646 +/* 14636 */ MCD_OPC_CheckPredicate, 35, 21, 0, 0, // Skip to: 14662 +/* 14641 */ MCD_OPC_Decode, 208, 23, 180, 2, // Opcode: WFKEDBS +/* 14646 */ MCD_OPC_FilterValue, 196, 3, 10, 0, 0, // Skip to: 14662 +/* 14652 */ MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 14662 +/* 14657 */ MCD_OPC_Decode, 212, 23, 239, 1, // Opcode: WFKEXBS +/* 14662 */ MCD_OPC_CheckPredicate, 34, 129, 33, 0, // Skip to: 23244 +/* 14667 */ MCD_OPC_Decode, 223, 19, 181, 2, // Opcode: VFCE +/* 14672 */ MCD_OPC_FilterValue, 234, 1, 89, 1, 0, // Skip to: 15023 +/* 14678 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 14681 */ MCD_OPC_FilterValue, 0, 110, 33, 0, // Skip to: 23244 +/* 14686 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 14689 */ MCD_OPC_FilterValue, 0, 102, 33, 0, // Skip to: 23244 +/* 14694 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... +/* 14697 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 14712 +/* 14702 */ MCD_OPC_CheckPredicate, 35, 50, 1, 0, // Skip to: 15013 +/* 14707 */ MCD_OPC_Decode, 234, 19, 239, 1, // Opcode: VFCHESB +/* 14712 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 14727 +/* 14717 */ MCD_OPC_CheckPredicate, 34, 35, 1, 0, // Skip to: 15013 +/* 14722 */ MCD_OPC_Decode, 232, 19, 239, 1, // Opcode: VFCHEDB +/* 14727 */ MCD_OPC_FilterValue, 66, 10, 0, 0, // Skip to: 14742 +/* 14732 */ MCD_OPC_CheckPredicate, 35, 20, 1, 0, // Skip to: 15013 +/* 14737 */ MCD_OPC_Decode, 150, 20, 239, 1, // Opcode: VFKHESB +/* 14742 */ MCD_OPC_FilterValue, 67, 10, 0, 0, // Skip to: 14757 +/* 14747 */ MCD_OPC_CheckPredicate, 35, 5, 1, 0, // Skip to: 15013 +/* 14752 */ MCD_OPC_Decode, 148, 20, 239, 1, // Opcode: VFKHEDB +/* 14757 */ MCD_OPC_FilterValue, 130, 1, 10, 0, 0, // Skip to: 14773 +/* 14763 */ MCD_OPC_CheckPredicate, 35, 245, 0, 0, // Skip to: 15013 +/* 14768 */ MCD_OPC_Decode, 189, 23, 179, 2, // Opcode: WFCHESB +/* 14773 */ MCD_OPC_FilterValue, 131, 1, 10, 0, 0, // Skip to: 14789 +/* 14779 */ MCD_OPC_CheckPredicate, 34, 229, 0, 0, // Skip to: 15013 +/* 14784 */ MCD_OPC_Decode, 187, 23, 180, 2, // Opcode: WFCHEDB +/* 14789 */ MCD_OPC_FilterValue, 132, 1, 10, 0, 0, // Skip to: 14805 +/* 14795 */ MCD_OPC_CheckPredicate, 35, 213, 0, 0, // Skip to: 15013 +/* 14800 */ MCD_OPC_Decode, 191, 23, 239, 1, // Opcode: WFCHEXB +/* 14805 */ MCD_OPC_FilterValue, 194, 1, 10, 0, 0, // Skip to: 14821 +/* 14811 */ MCD_OPC_CheckPredicate, 35, 197, 0, 0, // Skip to: 15013 +/* 14816 */ MCD_OPC_Decode, 217, 23, 179, 2, // Opcode: WFKHESB +/* 14821 */ MCD_OPC_FilterValue, 195, 1, 10, 0, 0, // Skip to: 14837 +/* 14827 */ MCD_OPC_CheckPredicate, 35, 181, 0, 0, // Skip to: 15013 +/* 14832 */ MCD_OPC_Decode, 215, 23, 180, 2, // Opcode: WFKHEDB +/* 14837 */ MCD_OPC_FilterValue, 196, 1, 10, 0, 0, // Skip to: 14853 +/* 14843 */ MCD_OPC_CheckPredicate, 35, 165, 0, 0, // Skip to: 15013 +/* 14848 */ MCD_OPC_Decode, 219, 23, 239, 1, // Opcode: WFKHEXB +/* 14853 */ MCD_OPC_FilterValue, 130, 2, 10, 0, 0, // Skip to: 14869 +/* 14859 */ MCD_OPC_CheckPredicate, 35, 149, 0, 0, // Skip to: 15013 +/* 14864 */ MCD_OPC_Decode, 235, 19, 239, 1, // Opcode: VFCHESBS +/* 14869 */ MCD_OPC_FilterValue, 131, 2, 10, 0, 0, // Skip to: 14885 +/* 14875 */ MCD_OPC_CheckPredicate, 34, 133, 0, 0, // Skip to: 15013 +/* 14880 */ MCD_OPC_Decode, 233, 19, 239, 1, // Opcode: VFCHEDBS +/* 14885 */ MCD_OPC_FilterValue, 194, 2, 10, 0, 0, // Skip to: 14901 +/* 14891 */ MCD_OPC_CheckPredicate, 35, 117, 0, 0, // Skip to: 15013 +/* 14896 */ MCD_OPC_Decode, 151, 20, 239, 1, // Opcode: VFKHESBS +/* 14901 */ MCD_OPC_FilterValue, 195, 2, 10, 0, 0, // Skip to: 14917 +/* 14907 */ MCD_OPC_CheckPredicate, 35, 101, 0, 0, // Skip to: 15013 +/* 14912 */ MCD_OPC_Decode, 149, 20, 239, 1, // Opcode: VFKHEDBS +/* 14917 */ MCD_OPC_FilterValue, 130, 3, 10, 0, 0, // Skip to: 14933 +/* 14923 */ MCD_OPC_CheckPredicate, 35, 85, 0, 0, // Skip to: 15013 +/* 14928 */ MCD_OPC_Decode, 190, 23, 179, 2, // Opcode: WFCHESBS +/* 14933 */ MCD_OPC_FilterValue, 131, 3, 10, 0, 0, // Skip to: 14949 +/* 14939 */ MCD_OPC_CheckPredicate, 34, 69, 0, 0, // Skip to: 15013 +/* 14944 */ MCD_OPC_Decode, 188, 23, 180, 2, // Opcode: WFCHEDBS +/* 14949 */ MCD_OPC_FilterValue, 132, 3, 10, 0, 0, // Skip to: 14965 +/* 14955 */ MCD_OPC_CheckPredicate, 35, 53, 0, 0, // Skip to: 15013 +/* 14960 */ MCD_OPC_Decode, 192, 23, 239, 1, // Opcode: WFCHEXBS +/* 14965 */ MCD_OPC_FilterValue, 194, 3, 10, 0, 0, // Skip to: 14981 +/* 14971 */ MCD_OPC_CheckPredicate, 35, 37, 0, 0, // Skip to: 15013 +/* 14976 */ MCD_OPC_Decode, 218, 23, 179, 2, // Opcode: WFKHESBS +/* 14981 */ MCD_OPC_FilterValue, 195, 3, 10, 0, 0, // Skip to: 14997 +/* 14987 */ MCD_OPC_CheckPredicate, 35, 21, 0, 0, // Skip to: 15013 +/* 14992 */ MCD_OPC_Decode, 216, 23, 180, 2, // Opcode: WFKHEDBS +/* 14997 */ MCD_OPC_FilterValue, 196, 3, 10, 0, 0, // Skip to: 15013 +/* 15003 */ MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 15013 +/* 15008 */ MCD_OPC_Decode, 220, 23, 239, 1, // Opcode: WFKHEXBS +/* 15013 */ MCD_OPC_CheckPredicate, 34, 34, 32, 0, // Skip to: 23244 +/* 15018 */ MCD_OPC_Decode, 231, 19, 181, 2, // Opcode: VFCHE +/* 15023 */ MCD_OPC_FilterValue, 235, 1, 89, 1, 0, // Skip to: 15374 +/* 15029 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 15032 */ MCD_OPC_FilterValue, 0, 15, 32, 0, // Skip to: 23244 +/* 15037 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 15040 */ MCD_OPC_FilterValue, 0, 7, 32, 0, // Skip to: 23244 +/* 15045 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... +/* 15048 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 15063 +/* 15053 */ MCD_OPC_CheckPredicate, 35, 50, 1, 0, // Skip to: 15364 +/* 15058 */ MCD_OPC_Decode, 236, 19, 239, 1, // Opcode: VFCHSB +/* 15063 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 15078 +/* 15068 */ MCD_OPC_CheckPredicate, 34, 35, 1, 0, // Skip to: 15364 +/* 15073 */ MCD_OPC_Decode, 229, 19, 239, 1, // Opcode: VFCHDB +/* 15078 */ MCD_OPC_FilterValue, 66, 10, 0, 0, // Skip to: 15093 +/* 15083 */ MCD_OPC_CheckPredicate, 35, 20, 1, 0, // Skip to: 15364 +/* 15088 */ MCD_OPC_Decode, 152, 20, 239, 1, // Opcode: VFKHSB +/* 15093 */ MCD_OPC_FilterValue, 67, 10, 0, 0, // Skip to: 15108 +/* 15098 */ MCD_OPC_CheckPredicate, 35, 5, 1, 0, // Skip to: 15364 +/* 15103 */ MCD_OPC_Decode, 146, 20, 239, 1, // Opcode: VFKHDB +/* 15108 */ MCD_OPC_FilterValue, 130, 1, 10, 0, 0, // Skip to: 15124 +/* 15114 */ MCD_OPC_CheckPredicate, 35, 245, 0, 0, // Skip to: 15364 +/* 15119 */ MCD_OPC_Decode, 193, 23, 179, 2, // Opcode: WFCHSB +/* 15124 */ MCD_OPC_FilterValue, 131, 1, 10, 0, 0, // Skip to: 15140 +/* 15130 */ MCD_OPC_CheckPredicate, 34, 229, 0, 0, // Skip to: 15364 +/* 15135 */ MCD_OPC_Decode, 185, 23, 180, 2, // Opcode: WFCHDB +/* 15140 */ MCD_OPC_FilterValue, 132, 1, 10, 0, 0, // Skip to: 15156 +/* 15146 */ MCD_OPC_CheckPredicate, 35, 213, 0, 0, // Skip to: 15364 +/* 15151 */ MCD_OPC_Decode, 195, 23, 239, 1, // Opcode: WFCHXB +/* 15156 */ MCD_OPC_FilterValue, 194, 1, 10, 0, 0, // Skip to: 15172 +/* 15162 */ MCD_OPC_CheckPredicate, 35, 197, 0, 0, // Skip to: 15364 +/* 15167 */ MCD_OPC_Decode, 221, 23, 179, 2, // Opcode: WFKHSB +/* 15172 */ MCD_OPC_FilterValue, 195, 1, 10, 0, 0, // Skip to: 15188 +/* 15178 */ MCD_OPC_CheckPredicate, 35, 181, 0, 0, // Skip to: 15364 +/* 15183 */ MCD_OPC_Decode, 213, 23, 180, 2, // Opcode: WFKHDB +/* 15188 */ MCD_OPC_FilterValue, 196, 1, 10, 0, 0, // Skip to: 15204 +/* 15194 */ MCD_OPC_CheckPredicate, 35, 165, 0, 0, // Skip to: 15364 +/* 15199 */ MCD_OPC_Decode, 223, 23, 239, 1, // Opcode: WFKHXB +/* 15204 */ MCD_OPC_FilterValue, 130, 2, 10, 0, 0, // Skip to: 15220 +/* 15210 */ MCD_OPC_CheckPredicate, 35, 149, 0, 0, // Skip to: 15364 +/* 15215 */ MCD_OPC_Decode, 237, 19, 239, 1, // Opcode: VFCHSBS +/* 15220 */ MCD_OPC_FilterValue, 131, 2, 10, 0, 0, // Skip to: 15236 +/* 15226 */ MCD_OPC_CheckPredicate, 34, 133, 0, 0, // Skip to: 15364 +/* 15231 */ MCD_OPC_Decode, 230, 19, 239, 1, // Opcode: VFCHDBS +/* 15236 */ MCD_OPC_FilterValue, 194, 2, 10, 0, 0, // Skip to: 15252 +/* 15242 */ MCD_OPC_CheckPredicate, 35, 117, 0, 0, // Skip to: 15364 +/* 15247 */ MCD_OPC_Decode, 153, 20, 239, 1, // Opcode: VFKHSBS +/* 15252 */ MCD_OPC_FilterValue, 195, 2, 10, 0, 0, // Skip to: 15268 +/* 15258 */ MCD_OPC_CheckPredicate, 35, 101, 0, 0, // Skip to: 15364 +/* 15263 */ MCD_OPC_Decode, 147, 20, 239, 1, // Opcode: VFKHDBS +/* 15268 */ MCD_OPC_FilterValue, 130, 3, 10, 0, 0, // Skip to: 15284 +/* 15274 */ MCD_OPC_CheckPredicate, 35, 85, 0, 0, // Skip to: 15364 +/* 15279 */ MCD_OPC_Decode, 194, 23, 179, 2, // Opcode: WFCHSBS +/* 15284 */ MCD_OPC_FilterValue, 131, 3, 10, 0, 0, // Skip to: 15300 +/* 15290 */ MCD_OPC_CheckPredicate, 34, 69, 0, 0, // Skip to: 15364 +/* 15295 */ MCD_OPC_Decode, 186, 23, 180, 2, // Opcode: WFCHDBS +/* 15300 */ MCD_OPC_FilterValue, 132, 3, 10, 0, 0, // Skip to: 15316 +/* 15306 */ MCD_OPC_CheckPredicate, 35, 53, 0, 0, // Skip to: 15364 +/* 15311 */ MCD_OPC_Decode, 196, 23, 239, 1, // Opcode: WFCHXBS +/* 15316 */ MCD_OPC_FilterValue, 194, 3, 10, 0, 0, // Skip to: 15332 +/* 15322 */ MCD_OPC_CheckPredicate, 35, 37, 0, 0, // Skip to: 15364 +/* 15327 */ MCD_OPC_Decode, 222, 23, 179, 2, // Opcode: WFKHSBS +/* 15332 */ MCD_OPC_FilterValue, 195, 3, 10, 0, 0, // Skip to: 15348 +/* 15338 */ MCD_OPC_CheckPredicate, 35, 21, 0, 0, // Skip to: 15364 +/* 15343 */ MCD_OPC_Decode, 214, 23, 180, 2, // Opcode: WFKHDBS +/* 15348 */ MCD_OPC_FilterValue, 196, 3, 10, 0, 0, // Skip to: 15364 +/* 15354 */ MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 15364 +/* 15359 */ MCD_OPC_Decode, 224, 23, 239, 1, // Opcode: WFKHXBS +/* 15364 */ MCD_OPC_CheckPredicate, 34, 195, 30, 0, // Skip to: 23244 +/* 15369 */ MCD_OPC_Decode, 228, 19, 181, 2, // Opcode: VFCH +/* 15374 */ MCD_OPC_FilterValue, 238, 1, 107, 0, 0, // Skip to: 15487 +/* 15380 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 15383 */ MCD_OPC_FilterValue, 0, 176, 30, 0, // Skip to: 23244 +/* 15388 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 15391 */ MCD_OPC_FilterValue, 0, 168, 30, 0, // Skip to: 23244 +/* 15396 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 15399 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 15414 +/* 15404 */ MCD_OPC_CheckPredicate, 35, 68, 0, 0, // Skip to: 15477 +/* 15409 */ MCD_OPC_Decode, 174, 20, 235, 1, // Opcode: VFMINSB +/* 15414 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 15429 +/* 15419 */ MCD_OPC_CheckPredicate, 35, 53, 0, 0, // Skip to: 15477 +/* 15424 */ MCD_OPC_Decode, 173, 20, 235, 1, // Opcode: VFMINDB +/* 15429 */ MCD_OPC_FilterValue, 130, 1, 10, 0, 0, // Skip to: 15445 +/* 15435 */ MCD_OPC_CheckPredicate, 35, 37, 0, 0, // Skip to: 15477 +/* 15440 */ MCD_OPC_Decode, 248, 23, 182, 2, // Opcode: WFMINSB +/* 15445 */ MCD_OPC_FilterValue, 131, 1, 10, 0, 0, // Skip to: 15461 +/* 15451 */ MCD_OPC_CheckPredicate, 35, 21, 0, 0, // Skip to: 15477 +/* 15456 */ MCD_OPC_Decode, 247, 23, 183, 2, // Opcode: WFMINDB +/* 15461 */ MCD_OPC_FilterValue, 132, 1, 10, 0, 0, // Skip to: 15477 +/* 15467 */ MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 15477 +/* 15472 */ MCD_OPC_Decode, 249, 23, 235, 1, // Opcode: WFMINXB +/* 15477 */ MCD_OPC_CheckPredicate, 35, 82, 30, 0, // Skip to: 23244 +/* 15482 */ MCD_OPC_Decode, 172, 20, 181, 2, // Opcode: VFMIN +/* 15487 */ MCD_OPC_FilterValue, 239, 1, 107, 0, 0, // Skip to: 15600 +/* 15493 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 15496 */ MCD_OPC_FilterValue, 0, 63, 30, 0, // Skip to: 23244 +/* 15501 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 15504 */ MCD_OPC_FilterValue, 0, 55, 30, 0, // Skip to: 23244 +/* 15509 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 15512 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 15527 +/* 15517 */ MCD_OPC_CheckPredicate, 35, 68, 0, 0, // Skip to: 15590 +/* 15522 */ MCD_OPC_Decode, 170, 20, 235, 1, // Opcode: VFMAXSB +/* 15527 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 15542 +/* 15532 */ MCD_OPC_CheckPredicate, 35, 53, 0, 0, // Skip to: 15590 +/* 15537 */ MCD_OPC_Decode, 169, 20, 235, 1, // Opcode: VFMAXDB +/* 15542 */ MCD_OPC_FilterValue, 130, 1, 10, 0, 0, // Skip to: 15558 +/* 15548 */ MCD_OPC_CheckPredicate, 35, 37, 0, 0, // Skip to: 15590 +/* 15553 */ MCD_OPC_Decode, 244, 23, 182, 2, // Opcode: WFMAXSB +/* 15558 */ MCD_OPC_FilterValue, 131, 1, 10, 0, 0, // Skip to: 15574 +/* 15564 */ MCD_OPC_CheckPredicate, 35, 21, 0, 0, // Skip to: 15590 +/* 15569 */ MCD_OPC_Decode, 243, 23, 183, 2, // Opcode: WFMAXDB +/* 15574 */ MCD_OPC_FilterValue, 132, 1, 10, 0, 0, // Skip to: 15590 +/* 15580 */ MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 15590 +/* 15585 */ MCD_OPC_Decode, 245, 23, 235, 1, // Opcode: WFMAXXB +/* 15590 */ MCD_OPC_CheckPredicate, 35, 225, 29, 0, // Skip to: 23244 +/* 15595 */ MCD_OPC_Decode, 168, 20, 181, 2, // Opcode: VFMAX +/* 15600 */ MCD_OPC_FilterValue, 240, 1, 89, 0, 0, // Skip to: 15695 +/* 15606 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 15609 */ MCD_OPC_FilterValue, 0, 206, 29, 0, // Skip to: 23244 +/* 15614 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 15617 */ MCD_OPC_FilterValue, 0, 198, 29, 0, // Skip to: 23244 +/* 15622 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 15625 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 15640 +/* 15630 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 15685 +/* 15635 */ MCD_OPC_Decode, 206, 18, 239, 1, // Opcode: VAVGLB +/* 15640 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 15655 +/* 15645 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 15685 +/* 15650 */ MCD_OPC_Decode, 209, 18, 239, 1, // Opcode: VAVGLH +/* 15655 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 15670 +/* 15660 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 15685 +/* 15665 */ MCD_OPC_Decode, 207, 18, 239, 1, // Opcode: VAVGLF +/* 15670 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 15685 +/* 15675 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 15685 +/* 15680 */ MCD_OPC_Decode, 208, 18, 239, 1, // Opcode: VAVGLG +/* 15685 */ MCD_OPC_CheckPredicate, 34, 130, 29, 0, // Skip to: 23244 +/* 15690 */ MCD_OPC_Decode, 205, 18, 147, 2, // Opcode: VAVGL +/* 15695 */ MCD_OPC_FilterValue, 241, 1, 104, 0, 0, // Skip to: 15805 +/* 15701 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 15704 */ MCD_OPC_FilterValue, 0, 111, 29, 0, // Skip to: 23244 +/* 15709 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 15712 */ MCD_OPC_FilterValue, 0, 103, 29, 0, // Skip to: 23244 +/* 15717 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 15720 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 15735 +/* 15725 */ MCD_OPC_CheckPredicate, 34, 65, 0, 0, // Skip to: 15795 +/* 15730 */ MCD_OPC_Decode, 187, 18, 239, 1, // Opcode: VACCB +/* 15735 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 15750 +/* 15740 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 15795 +/* 15745 */ MCD_OPC_Decode, 192, 18, 239, 1, // Opcode: VACCH +/* 15750 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 15765 +/* 15755 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 15795 +/* 15760 */ MCD_OPC_Decode, 190, 18, 239, 1, // Opcode: VACCF +/* 15765 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 15780 +/* 15770 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 15795 +/* 15775 */ MCD_OPC_Decode, 191, 18, 239, 1, // Opcode: VACCG +/* 15780 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 15795 +/* 15785 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 15795 +/* 15790 */ MCD_OPC_Decode, 193, 18, 239, 1, // Opcode: VACCQ +/* 15795 */ MCD_OPC_CheckPredicate, 34, 20, 29, 0, // Skip to: 23244 +/* 15800 */ MCD_OPC_Decode, 186, 18, 147, 2, // Opcode: VACC +/* 15805 */ MCD_OPC_FilterValue, 242, 1, 89, 0, 0, // Skip to: 15900 +/* 15811 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 15814 */ MCD_OPC_FilterValue, 0, 1, 29, 0, // Skip to: 23244 +/* 15819 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 15822 */ MCD_OPC_FilterValue, 0, 249, 28, 0, // Skip to: 23244 +/* 15827 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 15830 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 15845 +/* 15835 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 15890 +/* 15840 */ MCD_OPC_Decode, 201, 18, 239, 1, // Opcode: VAVGB +/* 15845 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 15860 +/* 15850 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 15890 +/* 15855 */ MCD_OPC_Decode, 204, 18, 239, 1, // Opcode: VAVGH +/* 15860 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 15875 +/* 15865 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 15890 +/* 15870 */ MCD_OPC_Decode, 202, 18, 239, 1, // Opcode: VAVGF +/* 15875 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 15890 +/* 15880 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 15890 +/* 15885 */ MCD_OPC_Decode, 203, 18, 239, 1, // Opcode: VAVGG +/* 15890 */ MCD_OPC_CheckPredicate, 34, 181, 28, 0, // Skip to: 23244 +/* 15895 */ MCD_OPC_Decode, 200, 18, 147, 2, // Opcode: VAVG +/* 15900 */ MCD_OPC_FilterValue, 243, 1, 104, 0, 0, // Skip to: 16010 +/* 15906 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 15909 */ MCD_OPC_FilterValue, 0, 162, 28, 0, // Skip to: 23244 +/* 15914 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 15917 */ MCD_OPC_FilterValue, 0, 154, 28, 0, // Skip to: 23244 +/* 15922 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 15925 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 15940 +/* 15930 */ MCD_OPC_CheckPredicate, 34, 65, 0, 0, // Skip to: 16000 +/* 15935 */ MCD_OPC_Decode, 184, 18, 239, 1, // Opcode: VAB +/* 15940 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 15955 +/* 15945 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 16000 +/* 15950 */ MCD_OPC_Decode, 197, 18, 239, 1, // Opcode: VAH +/* 15955 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 15970 +/* 15960 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 16000 +/* 15965 */ MCD_OPC_Decode, 195, 18, 239, 1, // Opcode: VAF +/* 15970 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 15985 +/* 15975 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 16000 +/* 15980 */ MCD_OPC_Decode, 196, 18, 239, 1, // Opcode: VAG +/* 15985 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 16000 +/* 15990 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 16000 +/* 15995 */ MCD_OPC_Decode, 199, 18, 239, 1, // Opcode: VAQ +/* 16000 */ MCD_OPC_CheckPredicate, 34, 71, 28, 0, // Skip to: 23244 +/* 16005 */ MCD_OPC_Decode, 183, 18, 147, 2, // Opcode: VA +/* 16010 */ MCD_OPC_FilterValue, 245, 1, 104, 0, 0, // Skip to: 16120 +/* 16016 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 16019 */ MCD_OPC_FilterValue, 0, 52, 28, 0, // Skip to: 23244 +/* 16024 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 16027 */ MCD_OPC_FilterValue, 0, 44, 28, 0, // Skip to: 23244 +/* 16032 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 16035 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16050 +/* 16040 */ MCD_OPC_CheckPredicate, 34, 65, 0, 0, // Skip to: 16110 +/* 16045 */ MCD_OPC_Decode, 185, 22, 239, 1, // Opcode: VSCBIB +/* 16050 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 16065 +/* 16055 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 16110 +/* 16060 */ MCD_OPC_Decode, 188, 22, 239, 1, // Opcode: VSCBIH +/* 16065 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 16080 +/* 16070 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 16110 +/* 16075 */ MCD_OPC_Decode, 186, 22, 239, 1, // Opcode: VSCBIF +/* 16080 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 16095 +/* 16085 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 16110 +/* 16090 */ MCD_OPC_Decode, 187, 22, 239, 1, // Opcode: VSCBIG +/* 16095 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 16110 +/* 16100 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 16110 +/* 16105 */ MCD_OPC_Decode, 189, 22, 239, 1, // Opcode: VSCBIQ +/* 16110 */ MCD_OPC_CheckPredicate, 34, 217, 27, 0, // Skip to: 23244 +/* 16115 */ MCD_OPC_Decode, 184, 22, 147, 2, // Opcode: VSCBI +/* 16120 */ MCD_OPC_FilterValue, 247, 1, 104, 0, 0, // Skip to: 16230 +/* 16126 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 16129 */ MCD_OPC_FilterValue, 0, 198, 27, 0, // Skip to: 23244 +/* 16134 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 16137 */ MCD_OPC_FilterValue, 0, 190, 27, 0, // Skip to: 23244 +/* 16142 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 16145 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16160 +/* 16150 */ MCD_OPC_CheckPredicate, 34, 65, 0, 0, // Skip to: 16220 +/* 16155 */ MCD_OPC_Decode, 179, 22, 239, 1, // Opcode: VSB +/* 16160 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 16175 +/* 16165 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 16220 +/* 16170 */ MCD_OPC_Decode, 205, 22, 239, 1, // Opcode: VSH +/* 16175 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 16190 +/* 16180 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 16220 +/* 16185 */ MCD_OPC_Decode, 203, 22, 239, 1, // Opcode: VSF +/* 16190 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 16205 +/* 16195 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 16220 +/* 16200 */ MCD_OPC_Decode, 204, 22, 239, 1, // Opcode: VSG +/* 16205 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 16220 +/* 16210 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 16220 +/* 16215 */ MCD_OPC_Decode, 211, 22, 239, 1, // Opcode: VSQ +/* 16220 */ MCD_OPC_CheckPredicate, 34, 107, 27, 0, // Skip to: 23244 +/* 16225 */ MCD_OPC_Decode, 178, 22, 147, 2, // Opcode: VS +/* 16230 */ MCD_OPC_FilterValue, 248, 1, 189, 0, 0, // Skip to: 16425 +/* 16236 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 16239 */ MCD_OPC_FilterValue, 0, 88, 27, 0, // Skip to: 23244 +/* 16244 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 16247 */ MCD_OPC_FilterValue, 0, 80, 27, 0, // Skip to: 23244 +/* 16252 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 16255 */ MCD_OPC_FilterValue, 0, 72, 27, 0, // Skip to: 23244 +/* 16260 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 16263 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 16301 +/* 16268 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 16271 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16286 +/* 16276 */ MCD_OPC_CheckPredicate, 34, 134, 0, 0, // Skip to: 16415 +/* 16281 */ MCD_OPC_Decode, 218, 18, 239, 1, // Opcode: VCEQB +/* 16286 */ MCD_OPC_FilterValue, 1, 124, 0, 0, // Skip to: 16415 +/* 16291 */ MCD_OPC_CheckPredicate, 34, 119, 0, 0, // Skip to: 16415 +/* 16296 */ MCD_OPC_Decode, 219, 18, 239, 1, // Opcode: VCEQBS +/* 16301 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 16339 +/* 16306 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 16309 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16324 +/* 16314 */ MCD_OPC_CheckPredicate, 34, 96, 0, 0, // Skip to: 16415 +/* 16319 */ MCD_OPC_Decode, 224, 18, 239, 1, // Opcode: VCEQH +/* 16324 */ MCD_OPC_FilterValue, 1, 86, 0, 0, // Skip to: 16415 +/* 16329 */ MCD_OPC_CheckPredicate, 34, 81, 0, 0, // Skip to: 16415 +/* 16334 */ MCD_OPC_Decode, 225, 18, 239, 1, // Opcode: VCEQHS +/* 16339 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 16377 +/* 16344 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 16347 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16362 +/* 16352 */ MCD_OPC_CheckPredicate, 34, 58, 0, 0, // Skip to: 16415 +/* 16357 */ MCD_OPC_Decode, 220, 18, 239, 1, // Opcode: VCEQF +/* 16362 */ MCD_OPC_FilterValue, 1, 48, 0, 0, // Skip to: 16415 +/* 16367 */ MCD_OPC_CheckPredicate, 34, 43, 0, 0, // Skip to: 16415 +/* 16372 */ MCD_OPC_Decode, 221, 18, 239, 1, // Opcode: VCEQFS +/* 16377 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 16415 +/* 16382 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 16385 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16400 +/* 16390 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 16415 +/* 16395 */ MCD_OPC_Decode, 222, 18, 239, 1, // Opcode: VCEQG +/* 16400 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 16415 +/* 16405 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 16415 +/* 16410 */ MCD_OPC_Decode, 223, 18, 239, 1, // Opcode: VCEQGS +/* 16415 */ MCD_OPC_CheckPredicate, 34, 168, 26, 0, // Skip to: 23244 +/* 16420 */ MCD_OPC_Decode, 217, 18, 236, 1, // Opcode: VCEQ +/* 16425 */ MCD_OPC_FilterValue, 249, 1, 189, 0, 0, // Skip to: 16620 +/* 16431 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 16434 */ MCD_OPC_FilterValue, 0, 149, 26, 0, // Skip to: 23244 +/* 16439 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 16442 */ MCD_OPC_FilterValue, 0, 141, 26, 0, // Skip to: 23244 +/* 16447 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 16450 */ MCD_OPC_FilterValue, 0, 133, 26, 0, // Skip to: 23244 +/* 16455 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 16458 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 16496 +/* 16463 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 16466 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16481 +/* 16471 */ MCD_OPC_CheckPredicate, 34, 134, 0, 0, // Skip to: 16610 +/* 16476 */ MCD_OPC_Decode, 242, 18, 239, 1, // Opcode: VCHLB +/* 16481 */ MCD_OPC_FilterValue, 1, 124, 0, 0, // Skip to: 16610 +/* 16486 */ MCD_OPC_CheckPredicate, 34, 119, 0, 0, // Skip to: 16610 +/* 16491 */ MCD_OPC_Decode, 243, 18, 239, 1, // Opcode: VCHLBS +/* 16496 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 16534 +/* 16501 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 16504 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16519 +/* 16509 */ MCD_OPC_CheckPredicate, 34, 96, 0, 0, // Skip to: 16610 +/* 16514 */ MCD_OPC_Decode, 248, 18, 239, 1, // Opcode: VCHLH +/* 16519 */ MCD_OPC_FilterValue, 1, 86, 0, 0, // Skip to: 16610 +/* 16524 */ MCD_OPC_CheckPredicate, 34, 81, 0, 0, // Skip to: 16610 +/* 16529 */ MCD_OPC_Decode, 249, 18, 239, 1, // Opcode: VCHLHS +/* 16534 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 16572 +/* 16539 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 16542 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16557 +/* 16547 */ MCD_OPC_CheckPredicate, 34, 58, 0, 0, // Skip to: 16610 +/* 16552 */ MCD_OPC_Decode, 244, 18, 239, 1, // Opcode: VCHLF +/* 16557 */ MCD_OPC_FilterValue, 1, 48, 0, 0, // Skip to: 16610 +/* 16562 */ MCD_OPC_CheckPredicate, 34, 43, 0, 0, // Skip to: 16610 +/* 16567 */ MCD_OPC_Decode, 245, 18, 239, 1, // Opcode: VCHLFS +/* 16572 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 16610 +/* 16577 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 16580 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16595 +/* 16585 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 16610 +/* 16590 */ MCD_OPC_Decode, 246, 18, 239, 1, // Opcode: VCHLG +/* 16595 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 16610 +/* 16600 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 16610 +/* 16605 */ MCD_OPC_Decode, 247, 18, 239, 1, // Opcode: VCHLGS +/* 16610 */ MCD_OPC_CheckPredicate, 34, 229, 25, 0, // Skip to: 23244 +/* 16615 */ MCD_OPC_Decode, 241, 18, 236, 1, // Opcode: VCHL +/* 16620 */ MCD_OPC_FilterValue, 251, 1, 189, 0, 0, // Skip to: 16815 +/* 16626 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 16629 */ MCD_OPC_FilterValue, 0, 210, 25, 0, // Skip to: 23244 +/* 16634 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 16637 */ MCD_OPC_FilterValue, 0, 202, 25, 0, // Skip to: 23244 +/* 16642 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 16645 */ MCD_OPC_FilterValue, 0, 194, 25, 0, // Skip to: 23244 +/* 16650 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 16653 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 16691 +/* 16658 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 16661 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16676 +/* 16666 */ MCD_OPC_CheckPredicate, 34, 134, 0, 0, // Skip to: 16805 +/* 16671 */ MCD_OPC_Decode, 233, 18, 239, 1, // Opcode: VCHB +/* 16676 */ MCD_OPC_FilterValue, 1, 124, 0, 0, // Skip to: 16805 +/* 16681 */ MCD_OPC_CheckPredicate, 34, 119, 0, 0, // Skip to: 16805 +/* 16686 */ MCD_OPC_Decode, 234, 18, 239, 1, // Opcode: VCHBS +/* 16691 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 16729 +/* 16696 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 16699 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16714 +/* 16704 */ MCD_OPC_CheckPredicate, 34, 96, 0, 0, // Skip to: 16805 +/* 16709 */ MCD_OPC_Decode, 239, 18, 239, 1, // Opcode: VCHH +/* 16714 */ MCD_OPC_FilterValue, 1, 86, 0, 0, // Skip to: 16805 +/* 16719 */ MCD_OPC_CheckPredicate, 34, 81, 0, 0, // Skip to: 16805 +/* 16724 */ MCD_OPC_Decode, 240, 18, 239, 1, // Opcode: VCHHS +/* 16729 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 16767 +/* 16734 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 16737 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16752 +/* 16742 */ MCD_OPC_CheckPredicate, 34, 58, 0, 0, // Skip to: 16805 +/* 16747 */ MCD_OPC_Decode, 235, 18, 239, 1, // Opcode: VCHF +/* 16752 */ MCD_OPC_FilterValue, 1, 48, 0, 0, // Skip to: 16805 +/* 16757 */ MCD_OPC_CheckPredicate, 34, 43, 0, 0, // Skip to: 16805 +/* 16762 */ MCD_OPC_Decode, 236, 18, 239, 1, // Opcode: VCHFS +/* 16767 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 16805 +/* 16772 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 16775 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16790 +/* 16780 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 16805 +/* 16785 */ MCD_OPC_Decode, 237, 18, 239, 1, // Opcode: VCHG +/* 16790 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 16805 +/* 16795 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 16805 +/* 16800 */ MCD_OPC_Decode, 238, 18, 239, 1, // Opcode: VCHGS +/* 16805 */ MCD_OPC_CheckPredicate, 34, 34, 25, 0, // Skip to: 23244 +/* 16810 */ MCD_OPC_Decode, 232, 18, 236, 1, // Opcode: VCH +/* 16815 */ MCD_OPC_FilterValue, 252, 1, 89, 0, 0, // Skip to: 16910 +/* 16821 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 16824 */ MCD_OPC_FilterValue, 0, 15, 25, 0, // Skip to: 23244 +/* 16829 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 16832 */ MCD_OPC_FilterValue, 0, 7, 25, 0, // Skip to: 23244 +/* 16837 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 16840 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16855 +/* 16845 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 16900 +/* 16850 */ MCD_OPC_Decode, 227, 21, 239, 1, // Opcode: VMNLB +/* 16855 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 16870 +/* 16860 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 16900 +/* 16865 */ MCD_OPC_Decode, 230, 21, 239, 1, // Opcode: VMNLH +/* 16870 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 16885 +/* 16875 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 16900 +/* 16880 */ MCD_OPC_Decode, 228, 21, 239, 1, // Opcode: VMNLF +/* 16885 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 16900 +/* 16890 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 16900 +/* 16895 */ MCD_OPC_Decode, 229, 21, 239, 1, // Opcode: VMNLG +/* 16900 */ MCD_OPC_CheckPredicate, 34, 195, 24, 0, // Skip to: 23244 +/* 16905 */ MCD_OPC_Decode, 226, 21, 147, 2, // Opcode: VMNL +/* 16910 */ MCD_OPC_FilterValue, 253, 1, 89, 0, 0, // Skip to: 17005 +/* 16916 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 16919 */ MCD_OPC_FilterValue, 0, 176, 24, 0, // Skip to: 23244 +/* 16924 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 16927 */ MCD_OPC_FilterValue, 0, 168, 24, 0, // Skip to: 23244 +/* 16932 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 16935 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16950 +/* 16940 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 16995 +/* 16945 */ MCD_OPC_Decode, 255, 21, 239, 1, // Opcode: VMXLB +/* 16950 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 16965 +/* 16955 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 16995 +/* 16960 */ MCD_OPC_Decode, 130, 22, 239, 1, // Opcode: VMXLH +/* 16965 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 16980 +/* 16970 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 16995 +/* 16975 */ MCD_OPC_Decode, 128, 22, 239, 1, // Opcode: VMXLF +/* 16980 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 16995 +/* 16985 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 16995 +/* 16990 */ MCD_OPC_Decode, 129, 22, 239, 1, // Opcode: VMXLG +/* 16995 */ MCD_OPC_CheckPredicate, 34, 100, 24, 0, // Skip to: 23244 +/* 17000 */ MCD_OPC_Decode, 254, 21, 147, 2, // Opcode: VMXL +/* 17005 */ MCD_OPC_FilterValue, 254, 1, 89, 0, 0, // Skip to: 17100 +/* 17011 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 17014 */ MCD_OPC_FilterValue, 0, 81, 24, 0, // Skip to: 23244 +/* 17019 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 17022 */ MCD_OPC_FilterValue, 0, 73, 24, 0, // Skip to: 23244 +/* 17027 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 17030 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17045 +/* 17035 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 17090 +/* 17040 */ MCD_OPC_Decode, 222, 21, 239, 1, // Opcode: VMNB +/* 17045 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 17060 +/* 17050 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 17090 +/* 17055 */ MCD_OPC_Decode, 225, 21, 239, 1, // Opcode: VMNH +/* 17060 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 17075 +/* 17065 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 17090 +/* 17070 */ MCD_OPC_Decode, 223, 21, 239, 1, // Opcode: VMNF +/* 17075 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 17090 +/* 17080 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 17090 +/* 17085 */ MCD_OPC_Decode, 224, 21, 239, 1, // Opcode: VMNG +/* 17090 */ MCD_OPC_CheckPredicate, 34, 5, 24, 0, // Skip to: 23244 +/* 17095 */ MCD_OPC_Decode, 221, 21, 147, 2, // Opcode: VMN +/* 17100 */ MCD_OPC_FilterValue, 255, 1, 250, 23, 0, // Skip to: 23244 +/* 17106 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 17109 */ MCD_OPC_FilterValue, 0, 242, 23, 0, // Skip to: 23244 +/* 17114 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 17117 */ MCD_OPC_FilterValue, 0, 234, 23, 0, // Skip to: 23244 +/* 17122 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 17125 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17140 +/* 17130 */ MCD_OPC_CheckPredicate, 34, 50, 0, 0, // Skip to: 17185 +/* 17135 */ MCD_OPC_Decode, 250, 21, 239, 1, // Opcode: VMXB +/* 17140 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 17155 +/* 17145 */ MCD_OPC_CheckPredicate, 34, 35, 0, 0, // Skip to: 17185 +/* 17150 */ MCD_OPC_Decode, 253, 21, 239, 1, // Opcode: VMXH +/* 17155 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 17170 +/* 17160 */ MCD_OPC_CheckPredicate, 34, 20, 0, 0, // Skip to: 17185 +/* 17165 */ MCD_OPC_Decode, 251, 21, 239, 1, // Opcode: VMXF +/* 17170 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 17185 +/* 17175 */ MCD_OPC_CheckPredicate, 34, 5, 0, 0, // Skip to: 17185 +/* 17180 */ MCD_OPC_Decode, 252, 21, 239, 1, // Opcode: VMXG +/* 17185 */ MCD_OPC_CheckPredicate, 34, 166, 23, 0, // Skip to: 23244 +/* 17190 */ MCD_OPC_Decode, 249, 21, 147, 2, // Opcode: VMX +/* 17195 */ MCD_OPC_FilterValue, 232, 1, 5, 0, 0, // Skip to: 17206 +/* 17201 */ MCD_OPC_Decode, 209, 14, 198, 1, // Opcode: MVCIN +/* 17206 */ MCD_OPC_FilterValue, 233, 1, 5, 0, 0, // Skip to: 17217 +/* 17212 */ MCD_OPC_Decode, 172, 15, 200, 1, // Opcode: PKA +/* 17217 */ MCD_OPC_FilterValue, 234, 1, 5, 0, 0, // Skip to: 17228 +/* 17223 */ MCD_OPC_Decode, 180, 18, 198, 1, // Opcode: UNPKA +/* 17228 */ MCD_OPC_FilterValue, 235, 1, 245, 8, 0, // Skip to: 19527 +/* 17234 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 17237 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 17247 +/* 17242 */ MCD_OPC_Decode, 245, 11, 184, 2, // Opcode: LMG +/* 17247 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 17257 +/* 17252 */ MCD_OPC_Decode, 232, 16, 185, 2, // Opcode: SRAG +/* 17257 */ MCD_OPC_FilterValue, 11, 5, 0, 0, // Skip to: 17267 +/* 17262 */ MCD_OPC_Decode, 188, 16, 185, 2, // Opcode: SLAG +/* 17267 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 17277 +/* 17272 */ MCD_OPC_Decode, 239, 16, 185, 2, // Opcode: SRLG +/* 17277 */ MCD_OPC_FilterValue, 13, 5, 0, 0, // Skip to: 17287 +/* 17282 */ MCD_OPC_Decode, 207, 16, 185, 2, // Opcode: SLLG +/* 17287 */ MCD_OPC_FilterValue, 15, 5, 0, 0, // Skip to: 17297 +/* 17292 */ MCD_OPC_Decode, 159, 18, 184, 2, // Opcode: TRACG +/* 17297 */ MCD_OPC_FilterValue, 20, 5, 0, 0, // Skip to: 17307 +/* 17302 */ MCD_OPC_Decode, 149, 9, 186, 2, // Opcode: CSY +/* 17307 */ MCD_OPC_FilterValue, 28, 5, 0, 0, // Skip to: 17317 +/* 17312 */ MCD_OPC_Decode, 200, 15, 185, 2, // Opcode: RLLG +/* 17317 */ MCD_OPC_FilterValue, 29, 5, 0, 0, // Skip to: 17327 +/* 17322 */ MCD_OPC_Decode, 199, 15, 187, 2, // Opcode: RLL +/* 17327 */ MCD_OPC_FilterValue, 32, 5, 0, 0, // Skip to: 17337 +/* 17332 */ MCD_OPC_Decode, 152, 8, 188, 2, // Opcode: CLMH +/* 17337 */ MCD_OPC_FilterValue, 33, 5, 0, 0, // Skip to: 17347 +/* 17342 */ MCD_OPC_Decode, 153, 8, 189, 2, // Opcode: CLMY +/* 17347 */ MCD_OPC_FilterValue, 35, 103, 0, 0, // Skip to: 17455 +/* 17352 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 17355 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 17370 +/* 17360 */ MCD_OPC_CheckPredicate, 36, 80, 0, 0, // Skip to: 17445 +/* 17365 */ MCD_OPC_Decode, 202, 8, 190, 2, // Opcode: CLTAsmH +/* 17370 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 17385 +/* 17375 */ MCD_OPC_CheckPredicate, 36, 65, 0, 0, // Skip to: 17445 +/* 17380 */ MCD_OPC_Decode, 204, 8, 190, 2, // Opcode: CLTAsmL +/* 17385 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 17400 +/* 17390 */ MCD_OPC_CheckPredicate, 36, 50, 0, 0, // Skip to: 17445 +/* 17395 */ MCD_OPC_Decode, 206, 8, 190, 2, // Opcode: CLTAsmLH +/* 17400 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 17415 +/* 17405 */ MCD_OPC_CheckPredicate, 36, 35, 0, 0, // Skip to: 17445 +/* 17410 */ MCD_OPC_Decode, 201, 8, 190, 2, // Opcode: CLTAsmE +/* 17415 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 17430 +/* 17420 */ MCD_OPC_CheckPredicate, 36, 20, 0, 0, // Skip to: 17445 +/* 17425 */ MCD_OPC_Decode, 203, 8, 190, 2, // Opcode: CLTAsmHE +/* 17430 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 17445 +/* 17435 */ MCD_OPC_CheckPredicate, 36, 5, 0, 0, // Skip to: 17445 +/* 17440 */ MCD_OPC_Decode, 205, 8, 190, 2, // Opcode: CLTAsmLE +/* 17445 */ MCD_OPC_CheckPredicate, 36, 162, 22, 0, // Skip to: 23244 +/* 17450 */ MCD_OPC_Decode, 200, 8, 191, 2, // Opcode: CLTAsm +/* 17455 */ MCD_OPC_FilterValue, 36, 5, 0, 0, // Skip to: 17465 +/* 17460 */ MCD_OPC_Decode, 162, 17, 184, 2, // Opcode: STMG +/* 17465 */ MCD_OPC_FilterValue, 37, 5, 0, 0, // Skip to: 17475 +/* 17470 */ MCD_OPC_Decode, 142, 17, 192, 2, // Opcode: STCTG +/* 17475 */ MCD_OPC_FilterValue, 38, 5, 0, 0, // Skip to: 17485 +/* 17480 */ MCD_OPC_Decode, 163, 17, 193, 2, // Opcode: STMH +/* 17485 */ MCD_OPC_FilterValue, 43, 103, 0, 0, // Skip to: 17593 +/* 17490 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 17493 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 17508 +/* 17498 */ MCD_OPC_CheckPredicate, 36, 80, 0, 0, // Skip to: 17583 +/* 17503 */ MCD_OPC_Decode, 230, 7, 194, 2, // Opcode: CLGTAsmH +/* 17508 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 17523 +/* 17513 */ MCD_OPC_CheckPredicate, 36, 65, 0, 0, // Skip to: 17583 +/* 17518 */ MCD_OPC_Decode, 232, 7, 194, 2, // Opcode: CLGTAsmL +/* 17523 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 17538 +/* 17528 */ MCD_OPC_CheckPredicate, 36, 50, 0, 0, // Skip to: 17583 +/* 17533 */ MCD_OPC_Decode, 234, 7, 194, 2, // Opcode: CLGTAsmLH +/* 17538 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 17553 +/* 17543 */ MCD_OPC_CheckPredicate, 36, 35, 0, 0, // Skip to: 17583 +/* 17548 */ MCD_OPC_Decode, 229, 7, 194, 2, // Opcode: CLGTAsmE +/* 17553 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 17568 +/* 17558 */ MCD_OPC_CheckPredicate, 36, 20, 0, 0, // Skip to: 17583 +/* 17563 */ MCD_OPC_Decode, 231, 7, 194, 2, // Opcode: CLGTAsmHE +/* 17568 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 17583 +/* 17573 */ MCD_OPC_CheckPredicate, 36, 5, 0, 0, // Skip to: 17583 +/* 17578 */ MCD_OPC_Decode, 233, 7, 194, 2, // Opcode: CLGTAsmLE +/* 17583 */ MCD_OPC_CheckPredicate, 36, 24, 22, 0, // Skip to: 23244 +/* 17588 */ MCD_OPC_Decode, 228, 7, 195, 2, // Opcode: CLGTAsm +/* 17593 */ MCD_OPC_FilterValue, 44, 5, 0, 0, // Skip to: 17603 +/* 17598 */ MCD_OPC_Decode, 138, 17, 188, 2, // Opcode: STCMH +/* 17603 */ MCD_OPC_FilterValue, 45, 5, 0, 0, // Skip to: 17613 +/* 17608 */ MCD_OPC_Decode, 139, 17, 189, 2, // Opcode: STCMY +/* 17613 */ MCD_OPC_FilterValue, 47, 5, 0, 0, // Skip to: 17623 +/* 17618 */ MCD_OPC_Decode, 161, 11, 192, 2, // Opcode: LCTLG +/* 17623 */ MCD_OPC_FilterValue, 48, 5, 0, 0, // Skip to: 17633 +/* 17628 */ MCD_OPC_Decode, 144, 9, 196, 2, // Opcode: CSG +/* 17633 */ MCD_OPC_FilterValue, 49, 5, 0, 0, // Skip to: 17643 +/* 17638 */ MCD_OPC_Decode, 169, 5, 197, 2, // Opcode: CDSY +/* 17643 */ MCD_OPC_FilterValue, 62, 5, 0, 0, // Skip to: 17653 +/* 17648 */ MCD_OPC_Decode, 167, 5, 197, 2, // Opcode: CDSG +/* 17653 */ MCD_OPC_FilterValue, 68, 5, 0, 0, // Skip to: 17663 +/* 17658 */ MCD_OPC_Decode, 144, 5, 196, 2, // Opcode: BXHG +/* 17663 */ MCD_OPC_FilterValue, 69, 5, 0, 0, // Skip to: 17673 +/* 17668 */ MCD_OPC_Decode, 146, 5, 196, 2, // Opcode: BXLEG +/* 17673 */ MCD_OPC_FilterValue, 76, 5, 0, 0, // Skip to: 17683 +/* 17678 */ MCD_OPC_Decode, 226, 9, 185, 2, // Opcode: ECAG +/* 17683 */ MCD_OPC_FilterValue, 81, 5, 0, 0, // Skip to: 17693 +/* 17688 */ MCD_OPC_Decode, 153, 18, 198, 2, // Opcode: TMY +/* 17693 */ MCD_OPC_FilterValue, 82, 5, 0, 0, // Skip to: 17703 +/* 17698 */ MCD_OPC_Decode, 223, 14, 198, 2, // Opcode: MVIY +/* 17703 */ MCD_OPC_FilterValue, 84, 5, 0, 0, // Skip to: 17713 +/* 17708 */ MCD_OPC_Decode, 130, 15, 198, 2, // Opcode: NIY +/* 17713 */ MCD_OPC_FilterValue, 85, 5, 0, 0, // Skip to: 17723 +/* 17718 */ MCD_OPC_Decode, 150, 8, 198, 2, // Opcode: CLIY +/* 17723 */ MCD_OPC_FilterValue, 86, 5, 0, 0, // Skip to: 17733 +/* 17728 */ MCD_OPC_Decode, 157, 15, 198, 2, // Opcode: OIY +/* 17733 */ MCD_OPC_FilterValue, 87, 5, 0, 0, // Skip to: 17743 +/* 17738 */ MCD_OPC_Decode, 155, 24, 198, 2, // Opcode: XIY +/* 17743 */ MCD_OPC_FilterValue, 106, 5, 0, 0, // Skip to: 17753 +/* 17748 */ MCD_OPC_Decode, 164, 4, 199, 2, // Opcode: ASI +/* 17753 */ MCD_OPC_FilterValue, 110, 5, 0, 0, // Skip to: 17763 +/* 17758 */ MCD_OPC_Decode, 157, 4, 199, 2, // Opcode: ALSI +/* 17763 */ MCD_OPC_FilterValue, 113, 17, 0, 0, // Skip to: 17785 +/* 17768 */ MCD_OPC_CheckPredicate, 0, 95, 21, 0, // Skip to: 23244 +/* 17773 */ MCD_OPC_CheckField, 32, 8, 0, 88, 21, 0, // Skip to: 23244 +/* 17780 */ MCD_OPC_Decode, 217, 13, 200, 2, // Opcode: LPSWEY +/* 17785 */ MCD_OPC_FilterValue, 122, 5, 0, 0, // Skip to: 17795 +/* 17790 */ MCD_OPC_Decode, 130, 4, 199, 2, // Opcode: AGSI +/* 17795 */ MCD_OPC_FilterValue, 126, 5, 0, 0, // Skip to: 17805 +/* 17800 */ MCD_OPC_Decode, 151, 4, 199, 2, // Opcode: ALGSI +/* 17805 */ MCD_OPC_FilterValue, 128, 1, 5, 0, 0, // Skip to: 17816 +/* 17811 */ MCD_OPC_Decode, 142, 10, 201, 2, // Opcode: ICMH +/* 17816 */ MCD_OPC_FilterValue, 129, 1, 5, 0, 0, // Skip to: 17827 +/* 17822 */ MCD_OPC_Decode, 143, 10, 202, 2, // Opcode: ICMY +/* 17827 */ MCD_OPC_FilterValue, 142, 1, 5, 0, 0, // Skip to: 17838 +/* 17833 */ MCD_OPC_Decode, 213, 14, 203, 2, // Opcode: MVCLU +/* 17838 */ MCD_OPC_FilterValue, 143, 1, 5, 0, 0, // Skip to: 17849 +/* 17844 */ MCD_OPC_Decode, 237, 6, 203, 2, // Opcode: CLCLU +/* 17849 */ MCD_OPC_FilterValue, 144, 1, 5, 0, 0, // Skip to: 17860 +/* 17855 */ MCD_OPC_Decode, 164, 17, 204, 2, // Opcode: STMY +/* 17860 */ MCD_OPC_FilterValue, 150, 1, 5, 0, 0, // Skip to: 17871 +/* 17866 */ MCD_OPC_Decode, 246, 11, 193, 2, // Opcode: LMH +/* 17871 */ MCD_OPC_FilterValue, 152, 1, 5, 0, 0, // Skip to: 17882 +/* 17877 */ MCD_OPC_Decode, 247, 11, 204, 2, // Opcode: LMY +/* 17882 */ MCD_OPC_FilterValue, 154, 1, 5, 0, 0, // Skip to: 17893 +/* 17888 */ MCD_OPC_Decode, 134, 11, 205, 2, // Opcode: LAMY +/* 17893 */ MCD_OPC_FilterValue, 155, 1, 5, 0, 0, // Skip to: 17904 +/* 17899 */ MCD_OPC_Decode, 128, 17, 205, 2, // Opcode: STAMY +/* 17904 */ MCD_OPC_FilterValue, 192, 1, 19, 0, 0, // Skip to: 17929 +/* 17910 */ MCD_OPC_CheckField, 32, 4, 0, 207, 20, 0, // Skip to: 23244 +/* 17917 */ MCD_OPC_CheckField, 8, 8, 0, 200, 20, 0, // Skip to: 23244 +/* 17924 */ MCD_OPC_Decode, 154, 18, 206, 2, // Opcode: TP +/* 17929 */ MCD_OPC_FilterValue, 220, 1, 10, 0, 0, // Skip to: 17945 +/* 17935 */ MCD_OPC_CheckPredicate, 23, 184, 20, 0, // Skip to: 23244 +/* 17940 */ MCD_OPC_Decode, 233, 16, 187, 2, // Opcode: SRAK +/* 17945 */ MCD_OPC_FilterValue, 221, 1, 10, 0, 0, // Skip to: 17961 +/* 17951 */ MCD_OPC_CheckPredicate, 23, 168, 20, 0, // Skip to: 23244 +/* 17956 */ MCD_OPC_Decode, 189, 16, 187, 2, // Opcode: SLAK +/* 17961 */ MCD_OPC_FilterValue, 222, 1, 10, 0, 0, // Skip to: 17977 +/* 17967 */ MCD_OPC_CheckPredicate, 23, 152, 20, 0, // Skip to: 23244 +/* 17972 */ MCD_OPC_Decode, 240, 16, 187, 2, // Opcode: SRLK +/* 17977 */ MCD_OPC_FilterValue, 223, 1, 10, 0, 0, // Skip to: 17993 +/* 17983 */ MCD_OPC_CheckPredicate, 23, 136, 20, 0, // Skip to: 23244 +/* 17988 */ MCD_OPC_Decode, 208, 16, 187, 2, // Opcode: SLLK +/* 17993 */ MCD_OPC_FilterValue, 224, 1, 223, 0, 0, // Skip to: 18222 +/* 17999 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 18002 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 18017 +/* 18007 */ MCD_OPC_CheckPredicate, 20, 200, 0, 0, // Skip to: 18212 +/* 18012 */ MCD_OPC_Decode, 172, 12, 207, 2, // Opcode: LOCFHAsmO +/* 18017 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 18032 +/* 18022 */ MCD_OPC_CheckPredicate, 20, 185, 0, 0, // Skip to: 18212 +/* 18027 */ MCD_OPC_Decode, 156, 12, 207, 2, // Opcode: LOCFHAsmH +/* 18032 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 18047 +/* 18037 */ MCD_OPC_CheckPredicate, 20, 170, 0, 0, // Skip to: 18212 +/* 18042 */ MCD_OPC_Decode, 166, 12, 207, 2, // Opcode: LOCFHAsmNLE +/* 18047 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 18062 +/* 18052 */ MCD_OPC_CheckPredicate, 20, 155, 0, 0, // Skip to: 18212 +/* 18057 */ MCD_OPC_Decode, 158, 12, 207, 2, // Opcode: LOCFHAsmL +/* 18062 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 18077 +/* 18067 */ MCD_OPC_CheckPredicate, 20, 140, 0, 0, // Skip to: 18212 +/* 18072 */ MCD_OPC_Decode, 164, 12, 207, 2, // Opcode: LOCFHAsmNHE +/* 18077 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 18092 +/* 18082 */ MCD_OPC_CheckPredicate, 20, 125, 0, 0, // Skip to: 18212 +/* 18087 */ MCD_OPC_Decode, 160, 12, 207, 2, // Opcode: LOCFHAsmLH +/* 18092 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 18107 +/* 18097 */ MCD_OPC_CheckPredicate, 20, 110, 0, 0, // Skip to: 18212 +/* 18102 */ MCD_OPC_Decode, 162, 12, 207, 2, // Opcode: LOCFHAsmNE +/* 18107 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 18122 +/* 18112 */ MCD_OPC_CheckPredicate, 20, 95, 0, 0, // Skip to: 18212 +/* 18117 */ MCD_OPC_Decode, 155, 12, 207, 2, // Opcode: LOCFHAsmE +/* 18122 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 18137 +/* 18127 */ MCD_OPC_CheckPredicate, 20, 80, 0, 0, // Skip to: 18212 +/* 18132 */ MCD_OPC_Decode, 167, 12, 207, 2, // Opcode: LOCFHAsmNLH +/* 18137 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 18152 +/* 18142 */ MCD_OPC_CheckPredicate, 20, 65, 0, 0, // Skip to: 18212 +/* 18147 */ MCD_OPC_Decode, 157, 12, 207, 2, // Opcode: LOCFHAsmHE +/* 18152 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 18167 +/* 18157 */ MCD_OPC_CheckPredicate, 20, 50, 0, 0, // Skip to: 18212 +/* 18162 */ MCD_OPC_Decode, 165, 12, 207, 2, // Opcode: LOCFHAsmNL +/* 18167 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 18182 +/* 18172 */ MCD_OPC_CheckPredicate, 20, 35, 0, 0, // Skip to: 18212 +/* 18177 */ MCD_OPC_Decode, 159, 12, 207, 2, // Opcode: LOCFHAsmLE +/* 18182 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 18197 +/* 18187 */ MCD_OPC_CheckPredicate, 20, 20, 0, 0, // Skip to: 18212 +/* 18192 */ MCD_OPC_Decode, 163, 12, 207, 2, // Opcode: LOCFHAsmNH +/* 18197 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 18212 +/* 18202 */ MCD_OPC_CheckPredicate, 20, 5, 0, 0, // Skip to: 18212 +/* 18207 */ MCD_OPC_Decode, 169, 12, 207, 2, // Opcode: LOCFHAsmNO +/* 18212 */ MCD_OPC_CheckPredicate, 20, 163, 19, 0, // Skip to: 23244 +/* 18217 */ MCD_OPC_Decode, 154, 12, 208, 2, // Opcode: LOCFHAsm +/* 18222 */ MCD_OPC_FilterValue, 225, 1, 223, 0, 0, // Skip to: 18451 +/* 18228 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 18231 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 18246 +/* 18236 */ MCD_OPC_CheckPredicate, 20, 200, 0, 0, // Skip to: 18441 +/* 18241 */ MCD_OPC_Decode, 207, 17, 209, 2, // Opcode: STOCFHAsmO +/* 18246 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 18261 +/* 18251 */ MCD_OPC_CheckPredicate, 20, 185, 0, 0, // Skip to: 18441 +/* 18256 */ MCD_OPC_Decode, 191, 17, 209, 2, // Opcode: STOCFHAsmH +/* 18261 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 18276 +/* 18266 */ MCD_OPC_CheckPredicate, 20, 170, 0, 0, // Skip to: 18441 +/* 18271 */ MCD_OPC_Decode, 201, 17, 209, 2, // Opcode: STOCFHAsmNLE +/* 18276 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 18291 +/* 18281 */ MCD_OPC_CheckPredicate, 20, 155, 0, 0, // Skip to: 18441 +/* 18286 */ MCD_OPC_Decode, 193, 17, 209, 2, // Opcode: STOCFHAsmL +/* 18291 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 18306 +/* 18296 */ MCD_OPC_CheckPredicate, 20, 140, 0, 0, // Skip to: 18441 +/* 18301 */ MCD_OPC_Decode, 199, 17, 209, 2, // Opcode: STOCFHAsmNHE +/* 18306 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 18321 +/* 18311 */ MCD_OPC_CheckPredicate, 20, 125, 0, 0, // Skip to: 18441 +/* 18316 */ MCD_OPC_Decode, 195, 17, 209, 2, // Opcode: STOCFHAsmLH +/* 18321 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 18336 +/* 18326 */ MCD_OPC_CheckPredicate, 20, 110, 0, 0, // Skip to: 18441 +/* 18331 */ MCD_OPC_Decode, 197, 17, 209, 2, // Opcode: STOCFHAsmNE +/* 18336 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 18351 +/* 18341 */ MCD_OPC_CheckPredicate, 20, 95, 0, 0, // Skip to: 18441 +/* 18346 */ MCD_OPC_Decode, 190, 17, 209, 2, // Opcode: STOCFHAsmE +/* 18351 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 18366 +/* 18356 */ MCD_OPC_CheckPredicate, 20, 80, 0, 0, // Skip to: 18441 +/* 18361 */ MCD_OPC_Decode, 202, 17, 209, 2, // Opcode: STOCFHAsmNLH +/* 18366 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 18381 +/* 18371 */ MCD_OPC_CheckPredicate, 20, 65, 0, 0, // Skip to: 18441 +/* 18376 */ MCD_OPC_Decode, 192, 17, 209, 2, // Opcode: STOCFHAsmHE +/* 18381 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 18396 +/* 18386 */ MCD_OPC_CheckPredicate, 20, 50, 0, 0, // Skip to: 18441 +/* 18391 */ MCD_OPC_Decode, 200, 17, 209, 2, // Opcode: STOCFHAsmNL +/* 18396 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 18411 +/* 18401 */ MCD_OPC_CheckPredicate, 20, 35, 0, 0, // Skip to: 18441 +/* 18406 */ MCD_OPC_Decode, 194, 17, 209, 2, // Opcode: STOCFHAsmLE +/* 18411 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 18426 +/* 18416 */ MCD_OPC_CheckPredicate, 20, 20, 0, 0, // Skip to: 18441 +/* 18421 */ MCD_OPC_Decode, 198, 17, 209, 2, // Opcode: STOCFHAsmNH +/* 18426 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 18441 +/* 18431 */ MCD_OPC_CheckPredicate, 20, 5, 0, 0, // Skip to: 18441 +/* 18436 */ MCD_OPC_Decode, 204, 17, 209, 2, // Opcode: STOCFHAsmNO +/* 18441 */ MCD_OPC_CheckPredicate, 20, 190, 18, 0, // Skip to: 23244 +/* 18446 */ MCD_OPC_Decode, 189, 17, 210, 2, // Opcode: STOCFHAsm +/* 18451 */ MCD_OPC_FilterValue, 226, 1, 223, 0, 0, // Skip to: 18680 +/* 18457 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 18460 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 18475 +/* 18465 */ MCD_OPC_CheckPredicate, 22, 200, 0, 0, // Skip to: 18670 +/* 18470 */ MCD_OPC_Decode, 216, 12, 211, 2, // Opcode: LOCGAsmO +/* 18475 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 18490 +/* 18480 */ MCD_OPC_CheckPredicate, 22, 185, 0, 0, // Skip to: 18670 +/* 18485 */ MCD_OPC_Decode, 200, 12, 211, 2, // Opcode: LOCGAsmH +/* 18490 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 18505 +/* 18495 */ MCD_OPC_CheckPredicate, 22, 170, 0, 0, // Skip to: 18670 +/* 18500 */ MCD_OPC_Decode, 210, 12, 211, 2, // Opcode: LOCGAsmNLE +/* 18505 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 18520 +/* 18510 */ MCD_OPC_CheckPredicate, 22, 155, 0, 0, // Skip to: 18670 +/* 18515 */ MCD_OPC_Decode, 202, 12, 211, 2, // Opcode: LOCGAsmL +/* 18520 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 18535 +/* 18525 */ MCD_OPC_CheckPredicate, 22, 140, 0, 0, // Skip to: 18670 +/* 18530 */ MCD_OPC_Decode, 208, 12, 211, 2, // Opcode: LOCGAsmNHE +/* 18535 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 18550 +/* 18540 */ MCD_OPC_CheckPredicate, 22, 125, 0, 0, // Skip to: 18670 +/* 18545 */ MCD_OPC_Decode, 204, 12, 211, 2, // Opcode: LOCGAsmLH +/* 18550 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 18565 +/* 18555 */ MCD_OPC_CheckPredicate, 22, 110, 0, 0, // Skip to: 18670 +/* 18560 */ MCD_OPC_Decode, 206, 12, 211, 2, // Opcode: LOCGAsmNE +/* 18565 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 18580 +/* 18570 */ MCD_OPC_CheckPredicate, 22, 95, 0, 0, // Skip to: 18670 +/* 18575 */ MCD_OPC_Decode, 199, 12, 211, 2, // Opcode: LOCGAsmE +/* 18580 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 18595 +/* 18585 */ MCD_OPC_CheckPredicate, 22, 80, 0, 0, // Skip to: 18670 +/* 18590 */ MCD_OPC_Decode, 211, 12, 211, 2, // Opcode: LOCGAsmNLH +/* 18595 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 18610 +/* 18600 */ MCD_OPC_CheckPredicate, 22, 65, 0, 0, // Skip to: 18670 +/* 18605 */ MCD_OPC_Decode, 201, 12, 211, 2, // Opcode: LOCGAsmHE +/* 18610 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 18625 +/* 18615 */ MCD_OPC_CheckPredicate, 22, 50, 0, 0, // Skip to: 18670 +/* 18620 */ MCD_OPC_Decode, 209, 12, 211, 2, // Opcode: LOCGAsmNL +/* 18625 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 18640 +/* 18630 */ MCD_OPC_CheckPredicate, 22, 35, 0, 0, // Skip to: 18670 +/* 18635 */ MCD_OPC_Decode, 203, 12, 211, 2, // Opcode: LOCGAsmLE +/* 18640 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 18655 +/* 18645 */ MCD_OPC_CheckPredicate, 22, 20, 0, 0, // Skip to: 18670 +/* 18650 */ MCD_OPC_Decode, 207, 12, 211, 2, // Opcode: LOCGAsmNH +/* 18655 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 18670 +/* 18660 */ MCD_OPC_CheckPredicate, 22, 5, 0, 0, // Skip to: 18670 +/* 18665 */ MCD_OPC_Decode, 213, 12, 211, 2, // Opcode: LOCGAsmNO +/* 18670 */ MCD_OPC_CheckPredicate, 22, 217, 17, 0, // Skip to: 23244 +/* 18675 */ MCD_OPC_Decode, 198, 12, 212, 2, // Opcode: LOCGAsm +/* 18680 */ MCD_OPC_FilterValue, 227, 1, 223, 0, 0, // Skip to: 18909 +/* 18686 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 18689 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 18704 +/* 18694 */ MCD_OPC_CheckPredicate, 22, 200, 0, 0, // Skip to: 18899 +/* 18699 */ MCD_OPC_Decode, 229, 17, 194, 2, // Opcode: STOCGAsmO +/* 18704 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 18719 +/* 18709 */ MCD_OPC_CheckPredicate, 22, 185, 0, 0, // Skip to: 18899 +/* 18714 */ MCD_OPC_Decode, 213, 17, 194, 2, // Opcode: STOCGAsmH +/* 18719 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 18734 +/* 18724 */ MCD_OPC_CheckPredicate, 22, 170, 0, 0, // Skip to: 18899 +/* 18729 */ MCD_OPC_Decode, 223, 17, 194, 2, // Opcode: STOCGAsmNLE +/* 18734 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 18749 +/* 18739 */ MCD_OPC_CheckPredicate, 22, 155, 0, 0, // Skip to: 18899 +/* 18744 */ MCD_OPC_Decode, 215, 17, 194, 2, // Opcode: STOCGAsmL +/* 18749 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 18764 +/* 18754 */ MCD_OPC_CheckPredicate, 22, 140, 0, 0, // Skip to: 18899 +/* 18759 */ MCD_OPC_Decode, 221, 17, 194, 2, // Opcode: STOCGAsmNHE +/* 18764 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 18779 +/* 18769 */ MCD_OPC_CheckPredicate, 22, 125, 0, 0, // Skip to: 18899 +/* 18774 */ MCD_OPC_Decode, 217, 17, 194, 2, // Opcode: STOCGAsmLH +/* 18779 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 18794 +/* 18784 */ MCD_OPC_CheckPredicate, 22, 110, 0, 0, // Skip to: 18899 +/* 18789 */ MCD_OPC_Decode, 219, 17, 194, 2, // Opcode: STOCGAsmNE +/* 18794 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 18809 +/* 18799 */ MCD_OPC_CheckPredicate, 22, 95, 0, 0, // Skip to: 18899 +/* 18804 */ MCD_OPC_Decode, 212, 17, 194, 2, // Opcode: STOCGAsmE +/* 18809 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 18824 +/* 18814 */ MCD_OPC_CheckPredicate, 22, 80, 0, 0, // Skip to: 18899 +/* 18819 */ MCD_OPC_Decode, 224, 17, 194, 2, // Opcode: STOCGAsmNLH +/* 18824 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 18839 +/* 18829 */ MCD_OPC_CheckPredicate, 22, 65, 0, 0, // Skip to: 18899 +/* 18834 */ MCD_OPC_Decode, 214, 17, 194, 2, // Opcode: STOCGAsmHE +/* 18839 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 18854 +/* 18844 */ MCD_OPC_CheckPredicate, 22, 50, 0, 0, // Skip to: 18899 +/* 18849 */ MCD_OPC_Decode, 222, 17, 194, 2, // Opcode: STOCGAsmNL +/* 18854 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 18869 +/* 18859 */ MCD_OPC_CheckPredicate, 22, 35, 0, 0, // Skip to: 18899 +/* 18864 */ MCD_OPC_Decode, 216, 17, 194, 2, // Opcode: STOCGAsmLE +/* 18869 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 18884 +/* 18874 */ MCD_OPC_CheckPredicate, 22, 20, 0, 0, // Skip to: 18899 +/* 18879 */ MCD_OPC_Decode, 220, 17, 194, 2, // Opcode: STOCGAsmNH +/* 18884 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 18899 +/* 18889 */ MCD_OPC_CheckPredicate, 22, 5, 0, 0, // Skip to: 18899 +/* 18894 */ MCD_OPC_Decode, 226, 17, 194, 2, // Opcode: STOCGAsmNO +/* 18899 */ MCD_OPC_CheckPredicate, 22, 244, 16, 0, // Skip to: 23244 +/* 18904 */ MCD_OPC_Decode, 211, 17, 195, 2, // Opcode: STOCGAsm +/* 18909 */ MCD_OPC_FilterValue, 228, 1, 10, 0, 0, // Skip to: 18925 +/* 18915 */ MCD_OPC_CheckPredicate, 25, 228, 16, 0, // Skip to: 23244 +/* 18920 */ MCD_OPC_Decode, 136, 11, 184, 2, // Opcode: LANG +/* 18925 */ MCD_OPC_FilterValue, 230, 1, 10, 0, 0, // Skip to: 18941 +/* 18931 */ MCD_OPC_CheckPredicate, 25, 212, 16, 0, // Skip to: 23244 +/* 18936 */ MCD_OPC_Decode, 138, 11, 184, 2, // Opcode: LAOG +/* 18941 */ MCD_OPC_FilterValue, 231, 1, 10, 0, 0, // Skip to: 18957 +/* 18947 */ MCD_OPC_CheckPredicate, 25, 196, 16, 0, // Skip to: 23244 +/* 18952 */ MCD_OPC_Decode, 143, 11, 184, 2, // Opcode: LAXG +/* 18957 */ MCD_OPC_FilterValue, 232, 1, 10, 0, 0, // Skip to: 18973 +/* 18963 */ MCD_OPC_CheckPredicate, 25, 180, 16, 0, // Skip to: 23244 +/* 18968 */ MCD_OPC_Decode, 128, 11, 184, 2, // Opcode: LAAG +/* 18973 */ MCD_OPC_FilterValue, 234, 1, 10, 0, 0, // Skip to: 18989 +/* 18979 */ MCD_OPC_CheckPredicate, 25, 164, 16, 0, // Skip to: 23244 +/* 18984 */ MCD_OPC_Decode, 130, 11, 184, 2, // Opcode: LAALG +/* 18989 */ MCD_OPC_FilterValue, 242, 1, 223, 0, 0, // Skip to: 19218 +/* 18995 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 18998 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 19013 +/* 19003 */ MCD_OPC_CheckPredicate, 22, 200, 0, 0, // Skip to: 19208 +/* 19008 */ MCD_OPC_Decode, 150, 12, 213, 2, // Opcode: LOCAsmO +/* 19013 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 19028 +/* 19018 */ MCD_OPC_CheckPredicate, 22, 185, 0, 0, // Skip to: 19208 +/* 19023 */ MCD_OPC_Decode, 134, 12, 213, 2, // Opcode: LOCAsmH +/* 19028 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 19043 +/* 19033 */ MCD_OPC_CheckPredicate, 22, 170, 0, 0, // Skip to: 19208 +/* 19038 */ MCD_OPC_Decode, 144, 12, 213, 2, // Opcode: LOCAsmNLE +/* 19043 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 19058 +/* 19048 */ MCD_OPC_CheckPredicate, 22, 155, 0, 0, // Skip to: 19208 +/* 19053 */ MCD_OPC_Decode, 136, 12, 213, 2, // Opcode: LOCAsmL +/* 19058 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 19073 +/* 19063 */ MCD_OPC_CheckPredicate, 22, 140, 0, 0, // Skip to: 19208 +/* 19068 */ MCD_OPC_Decode, 142, 12, 213, 2, // Opcode: LOCAsmNHE +/* 19073 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 19088 +/* 19078 */ MCD_OPC_CheckPredicate, 22, 125, 0, 0, // Skip to: 19208 +/* 19083 */ MCD_OPC_Decode, 138, 12, 213, 2, // Opcode: LOCAsmLH +/* 19088 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 19103 +/* 19093 */ MCD_OPC_CheckPredicate, 22, 110, 0, 0, // Skip to: 19208 +/* 19098 */ MCD_OPC_Decode, 140, 12, 213, 2, // Opcode: LOCAsmNE +/* 19103 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 19118 +/* 19108 */ MCD_OPC_CheckPredicate, 22, 95, 0, 0, // Skip to: 19208 +/* 19113 */ MCD_OPC_Decode, 133, 12, 213, 2, // Opcode: LOCAsmE +/* 19118 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 19133 +/* 19123 */ MCD_OPC_CheckPredicate, 22, 80, 0, 0, // Skip to: 19208 +/* 19128 */ MCD_OPC_Decode, 145, 12, 213, 2, // Opcode: LOCAsmNLH +/* 19133 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 19148 +/* 19138 */ MCD_OPC_CheckPredicate, 22, 65, 0, 0, // Skip to: 19208 +/* 19143 */ MCD_OPC_Decode, 135, 12, 213, 2, // Opcode: LOCAsmHE +/* 19148 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 19163 +/* 19153 */ MCD_OPC_CheckPredicate, 22, 50, 0, 0, // Skip to: 19208 +/* 19158 */ MCD_OPC_Decode, 143, 12, 213, 2, // Opcode: LOCAsmNL +/* 19163 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 19178 +/* 19168 */ MCD_OPC_CheckPredicate, 22, 35, 0, 0, // Skip to: 19208 +/* 19173 */ MCD_OPC_Decode, 137, 12, 213, 2, // Opcode: LOCAsmLE +/* 19178 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 19193 +/* 19183 */ MCD_OPC_CheckPredicate, 22, 20, 0, 0, // Skip to: 19208 +/* 19188 */ MCD_OPC_Decode, 141, 12, 213, 2, // Opcode: LOCAsmNH +/* 19193 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 19208 +/* 19198 */ MCD_OPC_CheckPredicate, 22, 5, 0, 0, // Skip to: 19208 +/* 19203 */ MCD_OPC_Decode, 147, 12, 213, 2, // Opcode: LOCAsmNO +/* 19208 */ MCD_OPC_CheckPredicate, 22, 191, 15, 0, // Skip to: 23244 +/* 19213 */ MCD_OPC_Decode, 132, 12, 214, 2, // Opcode: LOCAsm +/* 19218 */ MCD_OPC_FilterValue, 243, 1, 223, 0, 0, // Skip to: 19447 +/* 19224 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 19227 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 19242 +/* 19232 */ MCD_OPC_CheckPredicate, 22, 200, 0, 0, // Skip to: 19437 +/* 19237 */ MCD_OPC_Decode, 185, 17, 190, 2, // Opcode: STOCAsmO +/* 19242 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 19257 +/* 19247 */ MCD_OPC_CheckPredicate, 22, 185, 0, 0, // Skip to: 19437 +/* 19252 */ MCD_OPC_Decode, 169, 17, 190, 2, // Opcode: STOCAsmH +/* 19257 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 19272 +/* 19262 */ MCD_OPC_CheckPredicate, 22, 170, 0, 0, // Skip to: 19437 +/* 19267 */ MCD_OPC_Decode, 179, 17, 190, 2, // Opcode: STOCAsmNLE +/* 19272 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 19287 +/* 19277 */ MCD_OPC_CheckPredicate, 22, 155, 0, 0, // Skip to: 19437 +/* 19282 */ MCD_OPC_Decode, 171, 17, 190, 2, // Opcode: STOCAsmL +/* 19287 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 19302 +/* 19292 */ MCD_OPC_CheckPredicate, 22, 140, 0, 0, // Skip to: 19437 +/* 19297 */ MCD_OPC_Decode, 177, 17, 190, 2, // Opcode: STOCAsmNHE +/* 19302 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 19317 +/* 19307 */ MCD_OPC_CheckPredicate, 22, 125, 0, 0, // Skip to: 19437 +/* 19312 */ MCD_OPC_Decode, 173, 17, 190, 2, // Opcode: STOCAsmLH +/* 19317 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 19332 +/* 19322 */ MCD_OPC_CheckPredicate, 22, 110, 0, 0, // Skip to: 19437 +/* 19327 */ MCD_OPC_Decode, 175, 17, 190, 2, // Opcode: STOCAsmNE +/* 19332 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 19347 +/* 19337 */ MCD_OPC_CheckPredicate, 22, 95, 0, 0, // Skip to: 19437 +/* 19342 */ MCD_OPC_Decode, 168, 17, 190, 2, // Opcode: STOCAsmE +/* 19347 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 19362 +/* 19352 */ MCD_OPC_CheckPredicate, 22, 80, 0, 0, // Skip to: 19437 +/* 19357 */ MCD_OPC_Decode, 180, 17, 190, 2, // Opcode: STOCAsmNLH +/* 19362 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 19377 +/* 19367 */ MCD_OPC_CheckPredicate, 22, 65, 0, 0, // Skip to: 19437 +/* 19372 */ MCD_OPC_Decode, 170, 17, 190, 2, // Opcode: STOCAsmHE +/* 19377 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 19392 +/* 19382 */ MCD_OPC_CheckPredicate, 22, 50, 0, 0, // Skip to: 19437 +/* 19387 */ MCD_OPC_Decode, 178, 17, 190, 2, // Opcode: STOCAsmNL +/* 19392 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 19407 +/* 19397 */ MCD_OPC_CheckPredicate, 22, 35, 0, 0, // Skip to: 19437 +/* 19402 */ MCD_OPC_Decode, 172, 17, 190, 2, // Opcode: STOCAsmLE +/* 19407 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 19422 +/* 19412 */ MCD_OPC_CheckPredicate, 22, 20, 0, 0, // Skip to: 19437 +/* 19417 */ MCD_OPC_Decode, 176, 17, 190, 2, // Opcode: STOCAsmNH +/* 19422 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 19437 +/* 19427 */ MCD_OPC_CheckPredicate, 22, 5, 0, 0, // Skip to: 19437 +/* 19432 */ MCD_OPC_Decode, 182, 17, 190, 2, // Opcode: STOCAsmNO +/* 19437 */ MCD_OPC_CheckPredicate, 22, 218, 14, 0, // Skip to: 23244 +/* 19442 */ MCD_OPC_Decode, 167, 17, 191, 2, // Opcode: STOCAsm +/* 19447 */ MCD_OPC_FilterValue, 244, 1, 10, 0, 0, // Skip to: 19463 +/* 19453 */ MCD_OPC_CheckPredicate, 25, 202, 14, 0, // Skip to: 23244 +/* 19458 */ MCD_OPC_Decode, 135, 11, 204, 2, // Opcode: LAN +/* 19463 */ MCD_OPC_FilterValue, 246, 1, 10, 0, 0, // Skip to: 19479 +/* 19469 */ MCD_OPC_CheckPredicate, 25, 186, 14, 0, // Skip to: 23244 +/* 19474 */ MCD_OPC_Decode, 137, 11, 204, 2, // Opcode: LAO +/* 19479 */ MCD_OPC_FilterValue, 247, 1, 10, 0, 0, // Skip to: 19495 +/* 19485 */ MCD_OPC_CheckPredicate, 25, 170, 14, 0, // Skip to: 23244 +/* 19490 */ MCD_OPC_Decode, 142, 11, 204, 2, // Opcode: LAX +/* 19495 */ MCD_OPC_FilterValue, 248, 1, 10, 0, 0, // Skip to: 19511 +/* 19501 */ MCD_OPC_CheckPredicate, 25, 154, 14, 0, // Skip to: 23244 +/* 19506 */ MCD_OPC_Decode, 255, 10, 204, 2, // Opcode: LAA +/* 19511 */ MCD_OPC_FilterValue, 250, 1, 143, 14, 0, // Skip to: 23244 +/* 19517 */ MCD_OPC_CheckPredicate, 25, 138, 14, 0, // Skip to: 23244 +/* 19522 */ MCD_OPC_Decode, 129, 11, 204, 2, // Opcode: LAAL +/* 19527 */ MCD_OPC_FilterValue, 236, 1, 214, 9, 0, // Skip to: 22051 +/* 19533 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 19536 */ MCD_OPC_FilterValue, 66, 231, 0, 0, // Skip to: 19772 +/* 19541 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... +/* 19544 */ MCD_OPC_FilterValue, 0, 111, 14, 0, // Skip to: 23244 +/* 19549 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 19552 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 19567 +/* 19557 */ MCD_OPC_CheckPredicate, 20, 200, 0, 0, // Skip to: 19762 +/* 19562 */ MCD_OPC_Decode, 176, 13, 215, 2, // Opcode: LOCHIAsmO +/* 19567 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 19582 +/* 19572 */ MCD_OPC_CheckPredicate, 20, 185, 0, 0, // Skip to: 19762 +/* 19577 */ MCD_OPC_Decode, 160, 13, 215, 2, // Opcode: LOCHIAsmH +/* 19582 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 19597 +/* 19587 */ MCD_OPC_CheckPredicate, 20, 170, 0, 0, // Skip to: 19762 +/* 19592 */ MCD_OPC_Decode, 170, 13, 215, 2, // Opcode: LOCHIAsmNLE +/* 19597 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 19612 +/* 19602 */ MCD_OPC_CheckPredicate, 20, 155, 0, 0, // Skip to: 19762 +/* 19607 */ MCD_OPC_Decode, 162, 13, 215, 2, // Opcode: LOCHIAsmL +/* 19612 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 19627 +/* 19617 */ MCD_OPC_CheckPredicate, 20, 140, 0, 0, // Skip to: 19762 +/* 19622 */ MCD_OPC_Decode, 168, 13, 215, 2, // Opcode: LOCHIAsmNHE +/* 19627 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 19642 +/* 19632 */ MCD_OPC_CheckPredicate, 20, 125, 0, 0, // Skip to: 19762 +/* 19637 */ MCD_OPC_Decode, 164, 13, 215, 2, // Opcode: LOCHIAsmLH +/* 19642 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 19657 +/* 19647 */ MCD_OPC_CheckPredicate, 20, 110, 0, 0, // Skip to: 19762 +/* 19652 */ MCD_OPC_Decode, 166, 13, 215, 2, // Opcode: LOCHIAsmNE +/* 19657 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 19672 +/* 19662 */ MCD_OPC_CheckPredicate, 20, 95, 0, 0, // Skip to: 19762 +/* 19667 */ MCD_OPC_Decode, 159, 13, 215, 2, // Opcode: LOCHIAsmE +/* 19672 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 19687 +/* 19677 */ MCD_OPC_CheckPredicate, 20, 80, 0, 0, // Skip to: 19762 +/* 19682 */ MCD_OPC_Decode, 171, 13, 215, 2, // Opcode: LOCHIAsmNLH +/* 19687 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 19702 +/* 19692 */ MCD_OPC_CheckPredicate, 20, 65, 0, 0, // Skip to: 19762 +/* 19697 */ MCD_OPC_Decode, 161, 13, 215, 2, // Opcode: LOCHIAsmHE +/* 19702 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 19717 +/* 19707 */ MCD_OPC_CheckPredicate, 20, 50, 0, 0, // Skip to: 19762 +/* 19712 */ MCD_OPC_Decode, 169, 13, 215, 2, // Opcode: LOCHIAsmNL +/* 19717 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 19732 +/* 19722 */ MCD_OPC_CheckPredicate, 20, 35, 0, 0, // Skip to: 19762 +/* 19727 */ MCD_OPC_Decode, 163, 13, 215, 2, // Opcode: LOCHIAsmLE +/* 19732 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 19747 +/* 19737 */ MCD_OPC_CheckPredicate, 20, 20, 0, 0, // Skip to: 19762 +/* 19742 */ MCD_OPC_Decode, 167, 13, 215, 2, // Opcode: LOCHIAsmNH +/* 19747 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 19762 +/* 19752 */ MCD_OPC_CheckPredicate, 20, 5, 0, 0, // Skip to: 19762 +/* 19757 */ MCD_OPC_Decode, 173, 13, 215, 2, // Opcode: LOCHIAsmNO +/* 19762 */ MCD_OPC_CheckPredicate, 20, 149, 13, 0, // Skip to: 23244 +/* 19767 */ MCD_OPC_Decode, 158, 13, 216, 2, // Opcode: LOCHIAsm +/* 19772 */ MCD_OPC_FilterValue, 68, 12, 0, 0, // Skip to: 19789 +/* 19777 */ MCD_OPC_CheckField, 8, 8, 0, 132, 13, 0, // Skip to: 23244 +/* 19784 */ MCD_OPC_Decode, 137, 5, 217, 2, // Opcode: BRXHG +/* 19789 */ MCD_OPC_FilterValue, 69, 12, 0, 0, // Skip to: 19806 +/* 19794 */ MCD_OPC_CheckField, 8, 8, 0, 115, 13, 0, // Skip to: 23244 +/* 19801 */ MCD_OPC_Decode, 139, 5, 217, 2, // Opcode: BRXLG +/* 19806 */ MCD_OPC_FilterValue, 70, 231, 0, 0, // Skip to: 20042 +/* 19811 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... +/* 19814 */ MCD_OPC_FilterValue, 0, 97, 13, 0, // Skip to: 23244 +/* 19819 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 19822 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 19837 +/* 19827 */ MCD_OPC_CheckPredicate, 20, 200, 0, 0, // Skip to: 20032 +/* 19832 */ MCD_OPC_Decode, 238, 12, 218, 2, // Opcode: LOCGHIAsmO +/* 19837 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 19852 +/* 19842 */ MCD_OPC_CheckPredicate, 20, 185, 0, 0, // Skip to: 20032 +/* 19847 */ MCD_OPC_Decode, 222, 12, 218, 2, // Opcode: LOCGHIAsmH +/* 19852 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 19867 +/* 19857 */ MCD_OPC_CheckPredicate, 20, 170, 0, 0, // Skip to: 20032 +/* 19862 */ MCD_OPC_Decode, 232, 12, 218, 2, // Opcode: LOCGHIAsmNLE +/* 19867 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 19882 +/* 19872 */ MCD_OPC_CheckPredicate, 20, 155, 0, 0, // Skip to: 20032 +/* 19877 */ MCD_OPC_Decode, 224, 12, 218, 2, // Opcode: LOCGHIAsmL +/* 19882 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 19897 +/* 19887 */ MCD_OPC_CheckPredicate, 20, 140, 0, 0, // Skip to: 20032 +/* 19892 */ MCD_OPC_Decode, 230, 12, 218, 2, // Opcode: LOCGHIAsmNHE +/* 19897 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 19912 +/* 19902 */ MCD_OPC_CheckPredicate, 20, 125, 0, 0, // Skip to: 20032 +/* 19907 */ MCD_OPC_Decode, 226, 12, 218, 2, // Opcode: LOCGHIAsmLH +/* 19912 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 19927 +/* 19917 */ MCD_OPC_CheckPredicate, 20, 110, 0, 0, // Skip to: 20032 +/* 19922 */ MCD_OPC_Decode, 228, 12, 218, 2, // Opcode: LOCGHIAsmNE +/* 19927 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 19942 +/* 19932 */ MCD_OPC_CheckPredicate, 20, 95, 0, 0, // Skip to: 20032 +/* 19937 */ MCD_OPC_Decode, 221, 12, 218, 2, // Opcode: LOCGHIAsmE +/* 19942 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 19957 +/* 19947 */ MCD_OPC_CheckPredicate, 20, 80, 0, 0, // Skip to: 20032 +/* 19952 */ MCD_OPC_Decode, 233, 12, 218, 2, // Opcode: LOCGHIAsmNLH +/* 19957 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 19972 +/* 19962 */ MCD_OPC_CheckPredicate, 20, 65, 0, 0, // Skip to: 20032 +/* 19967 */ MCD_OPC_Decode, 223, 12, 218, 2, // Opcode: LOCGHIAsmHE +/* 19972 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 19987 +/* 19977 */ MCD_OPC_CheckPredicate, 20, 50, 0, 0, // Skip to: 20032 +/* 19982 */ MCD_OPC_Decode, 231, 12, 218, 2, // Opcode: LOCGHIAsmNL +/* 19987 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 20002 +/* 19992 */ MCD_OPC_CheckPredicate, 20, 35, 0, 0, // Skip to: 20032 +/* 19997 */ MCD_OPC_Decode, 225, 12, 218, 2, // Opcode: LOCGHIAsmLE +/* 20002 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 20017 +/* 20007 */ MCD_OPC_CheckPredicate, 20, 20, 0, 0, // Skip to: 20032 +/* 20012 */ MCD_OPC_Decode, 229, 12, 218, 2, // Opcode: LOCGHIAsmNH +/* 20017 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 20032 +/* 20022 */ MCD_OPC_CheckPredicate, 20, 5, 0, 0, // Skip to: 20032 +/* 20027 */ MCD_OPC_Decode, 235, 12, 218, 2, // Opcode: LOCGHIAsmNO +/* 20032 */ MCD_OPC_CheckPredicate, 20, 135, 12, 0, // Skip to: 23244 +/* 20037 */ MCD_OPC_Decode, 220, 12, 219, 2, // Opcode: LOCGHIAsm +/* 20042 */ MCD_OPC_FilterValue, 78, 231, 0, 0, // Skip to: 20278 +/* 20047 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... +/* 20050 */ MCD_OPC_FilterValue, 0, 117, 12, 0, // Skip to: 23244 +/* 20055 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 20058 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 20073 +/* 20063 */ MCD_OPC_CheckPredicate, 20, 200, 0, 0, // Skip to: 20268 +/* 20068 */ MCD_OPC_Decode, 154, 13, 220, 2, // Opcode: LOCHHIAsmO +/* 20073 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 20088 +/* 20078 */ MCD_OPC_CheckPredicate, 20, 185, 0, 0, // Skip to: 20268 +/* 20083 */ MCD_OPC_Decode, 138, 13, 220, 2, // Opcode: LOCHHIAsmH +/* 20088 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 20103 +/* 20093 */ MCD_OPC_CheckPredicate, 20, 170, 0, 0, // Skip to: 20268 +/* 20098 */ MCD_OPC_Decode, 148, 13, 220, 2, // Opcode: LOCHHIAsmNLE +/* 20103 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 20118 +/* 20108 */ MCD_OPC_CheckPredicate, 20, 155, 0, 0, // Skip to: 20268 +/* 20113 */ MCD_OPC_Decode, 140, 13, 220, 2, // Opcode: LOCHHIAsmL +/* 20118 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 20133 +/* 20123 */ MCD_OPC_CheckPredicate, 20, 140, 0, 0, // Skip to: 20268 +/* 20128 */ MCD_OPC_Decode, 146, 13, 220, 2, // Opcode: LOCHHIAsmNHE +/* 20133 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 20148 +/* 20138 */ MCD_OPC_CheckPredicate, 20, 125, 0, 0, // Skip to: 20268 +/* 20143 */ MCD_OPC_Decode, 142, 13, 220, 2, // Opcode: LOCHHIAsmLH +/* 20148 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 20163 +/* 20153 */ MCD_OPC_CheckPredicate, 20, 110, 0, 0, // Skip to: 20268 +/* 20158 */ MCD_OPC_Decode, 144, 13, 220, 2, // Opcode: LOCHHIAsmNE +/* 20163 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 20178 +/* 20168 */ MCD_OPC_CheckPredicate, 20, 95, 0, 0, // Skip to: 20268 +/* 20173 */ MCD_OPC_Decode, 137, 13, 220, 2, // Opcode: LOCHHIAsmE +/* 20178 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 20193 +/* 20183 */ MCD_OPC_CheckPredicate, 20, 80, 0, 0, // Skip to: 20268 +/* 20188 */ MCD_OPC_Decode, 149, 13, 220, 2, // Opcode: LOCHHIAsmNLH +/* 20193 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 20208 +/* 20198 */ MCD_OPC_CheckPredicate, 20, 65, 0, 0, // Skip to: 20268 +/* 20203 */ MCD_OPC_Decode, 139, 13, 220, 2, // Opcode: LOCHHIAsmHE +/* 20208 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 20223 +/* 20213 */ MCD_OPC_CheckPredicate, 20, 50, 0, 0, // Skip to: 20268 +/* 20218 */ MCD_OPC_Decode, 147, 13, 220, 2, // Opcode: LOCHHIAsmNL +/* 20223 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 20238 +/* 20228 */ MCD_OPC_CheckPredicate, 20, 35, 0, 0, // Skip to: 20268 +/* 20233 */ MCD_OPC_Decode, 141, 13, 220, 2, // Opcode: LOCHHIAsmLE +/* 20238 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 20253 +/* 20243 */ MCD_OPC_CheckPredicate, 20, 20, 0, 0, // Skip to: 20268 +/* 20248 */ MCD_OPC_Decode, 145, 13, 220, 2, // Opcode: LOCHHIAsmNH +/* 20253 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 20268 +/* 20258 */ MCD_OPC_CheckPredicate, 20, 5, 0, 0, // Skip to: 20268 +/* 20263 */ MCD_OPC_Decode, 151, 13, 220, 2, // Opcode: LOCHHIAsmNO +/* 20268 */ MCD_OPC_CheckPredicate, 20, 155, 11, 0, // Skip to: 23244 +/* 20273 */ MCD_OPC_Decode, 136, 13, 221, 2, // Opcode: LOCHHIAsm +/* 20278 */ MCD_OPC_FilterValue, 81, 10, 0, 0, // Skip to: 20293 +/* 20283 */ MCD_OPC_CheckPredicate, 19, 140, 11, 0, // Skip to: 23244 +/* 20288 */ MCD_OPC_Decode, 198, 15, 222, 2, // Opcode: RISBLG +/* 20293 */ MCD_OPC_FilterValue, 84, 5, 0, 0, // Skip to: 20303 +/* 20298 */ MCD_OPC_Decode, 201, 15, 223, 2, // Opcode: RNSBG +/* 20303 */ MCD_OPC_FilterValue, 85, 5, 0, 0, // Skip to: 20313 +/* 20308 */ MCD_OPC_Decode, 194, 15, 223, 2, // Opcode: RISBG +/* 20313 */ MCD_OPC_FilterValue, 86, 5, 0, 0, // Skip to: 20323 +/* 20318 */ MCD_OPC_Decode, 202, 15, 223, 2, // Opcode: ROSBG +/* 20323 */ MCD_OPC_FilterValue, 87, 5, 0, 0, // Skip to: 20333 +/* 20328 */ MCD_OPC_Decode, 209, 15, 223, 2, // Opcode: RXSBG +/* 20333 */ MCD_OPC_FilterValue, 89, 10, 0, 0, // Skip to: 20348 +/* 20338 */ MCD_OPC_CheckPredicate, 36, 85, 11, 0, // Skip to: 23244 +/* 20343 */ MCD_OPC_Decode, 196, 15, 223, 2, // Opcode: RISBGN +/* 20348 */ MCD_OPC_FilterValue, 93, 10, 0, 0, // Skip to: 20363 +/* 20353 */ MCD_OPC_CheckPredicate, 19, 70, 11, 0, // Skip to: 23244 +/* 20358 */ MCD_OPC_Decode, 197, 15, 224, 2, // Opcode: RISBHG +/* 20363 */ MCD_OPC_FilterValue, 100, 76, 0, 0, // Skip to: 20444 +/* 20368 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 20371 */ MCD_OPC_FilterValue, 0, 52, 11, 0, // Skip to: 23244 +/* 20376 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 20379 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 20389 +/* 20384 */ MCD_OPC_Decode, 149, 6, 225, 2, // Opcode: CGRJAsmH +/* 20389 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 20399 +/* 20394 */ MCD_OPC_Decode, 151, 6, 225, 2, // Opcode: CGRJAsmL +/* 20399 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 20409 +/* 20404 */ MCD_OPC_Decode, 153, 6, 225, 2, // Opcode: CGRJAsmLH +/* 20409 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 20419 +/* 20414 */ MCD_OPC_Decode, 148, 6, 225, 2, // Opcode: CGRJAsmE +/* 20419 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 20429 +/* 20424 */ MCD_OPC_Decode, 150, 6, 225, 2, // Opcode: CGRJAsmHE +/* 20429 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 20439 +/* 20434 */ MCD_OPC_Decode, 152, 6, 225, 2, // Opcode: CGRJAsmLE +/* 20439 */ MCD_OPC_Decode, 147, 6, 226, 2, // Opcode: CGRJAsm +/* 20444 */ MCD_OPC_FilterValue, 101, 76, 0, 0, // Skip to: 20525 +/* 20449 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 20452 */ MCD_OPC_FilterValue, 0, 227, 10, 0, // Skip to: 23244 +/* 20457 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 20460 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 20470 +/* 20465 */ MCD_OPC_Decode, 201, 7, 225, 2, // Opcode: CLGRJAsmH +/* 20470 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 20480 +/* 20475 */ MCD_OPC_Decode, 203, 7, 225, 2, // Opcode: CLGRJAsmL +/* 20480 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 20490 +/* 20485 */ MCD_OPC_Decode, 205, 7, 225, 2, // Opcode: CLGRJAsmLH +/* 20490 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 20500 +/* 20495 */ MCD_OPC_Decode, 200, 7, 225, 2, // Opcode: CLGRJAsmE +/* 20500 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 20510 +/* 20505 */ MCD_OPC_Decode, 202, 7, 225, 2, // Opcode: CLGRJAsmHE +/* 20510 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 20520 +/* 20515 */ MCD_OPC_Decode, 204, 7, 225, 2, // Opcode: CLGRJAsmLE +/* 20520 */ MCD_OPC_Decode, 199, 7, 226, 2, // Opcode: CLGRJAsm +/* 20525 */ MCD_OPC_FilterValue, 112, 84, 0, 0, // Skip to: 20614 +/* 20530 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 20533 */ MCD_OPC_FilterValue, 0, 146, 10, 0, // Skip to: 23244 +/* 20538 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 20541 */ MCD_OPC_FilterValue, 0, 138, 10, 0, // Skip to: 23244 +/* 20546 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 20549 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 20559 +/* 20554 */ MCD_OPC_Decode, 248, 5, 227, 2, // Opcode: CGITAsmH +/* 20559 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 20569 +/* 20564 */ MCD_OPC_Decode, 250, 5, 227, 2, // Opcode: CGITAsmL +/* 20569 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 20579 +/* 20574 */ MCD_OPC_Decode, 252, 5, 227, 2, // Opcode: CGITAsmLH +/* 20579 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 20589 +/* 20584 */ MCD_OPC_Decode, 247, 5, 227, 2, // Opcode: CGITAsmE +/* 20589 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 20599 +/* 20594 */ MCD_OPC_Decode, 249, 5, 227, 2, // Opcode: CGITAsmHE +/* 20599 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 20609 +/* 20604 */ MCD_OPC_Decode, 251, 5, 227, 2, // Opcode: CGITAsmLE +/* 20609 */ MCD_OPC_Decode, 246, 5, 228, 2, // Opcode: CGITAsm +/* 20614 */ MCD_OPC_FilterValue, 113, 84, 0, 0, // Skip to: 20703 +/* 20619 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 20622 */ MCD_OPC_FilterValue, 0, 57, 10, 0, // Skip to: 23244 +/* 20627 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 20630 */ MCD_OPC_FilterValue, 0, 49, 10, 0, // Skip to: 23244 +/* 20635 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 20638 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 20648 +/* 20643 */ MCD_OPC_Decode, 172, 7, 229, 2, // Opcode: CLGITAsmH +/* 20648 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 20658 +/* 20653 */ MCD_OPC_Decode, 174, 7, 229, 2, // Opcode: CLGITAsmL +/* 20658 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 20668 +/* 20663 */ MCD_OPC_Decode, 176, 7, 229, 2, // Opcode: CLGITAsmLH +/* 20668 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 20678 +/* 20673 */ MCD_OPC_Decode, 171, 7, 229, 2, // Opcode: CLGITAsmE +/* 20678 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 20688 +/* 20683 */ MCD_OPC_Decode, 173, 7, 229, 2, // Opcode: CLGITAsmHE +/* 20688 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 20698 +/* 20693 */ MCD_OPC_Decode, 175, 7, 229, 2, // Opcode: CLGITAsmLE +/* 20698 */ MCD_OPC_Decode, 170, 7, 230, 2, // Opcode: CLGITAsm +/* 20703 */ MCD_OPC_FilterValue, 114, 84, 0, 0, // Skip to: 20792 +/* 20708 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 20711 */ MCD_OPC_FilterValue, 0, 224, 9, 0, // Skip to: 23244 +/* 20716 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 20719 */ MCD_OPC_FilterValue, 0, 216, 9, 0, // Skip to: 23244 +/* 20724 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 20727 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 20737 +/* 20732 */ MCD_OPC_Decode, 221, 6, 231, 2, // Opcode: CITAsmH +/* 20737 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 20747 +/* 20742 */ MCD_OPC_Decode, 223, 6, 231, 2, // Opcode: CITAsmL +/* 20747 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 20757 +/* 20752 */ MCD_OPC_Decode, 225, 6, 231, 2, // Opcode: CITAsmLH +/* 20757 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 20767 +/* 20762 */ MCD_OPC_Decode, 220, 6, 231, 2, // Opcode: CITAsmE +/* 20767 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 20777 +/* 20772 */ MCD_OPC_Decode, 222, 6, 231, 2, // Opcode: CITAsmHE +/* 20777 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 20787 +/* 20782 */ MCD_OPC_Decode, 224, 6, 231, 2, // Opcode: CITAsmLE +/* 20787 */ MCD_OPC_Decode, 219, 6, 232, 2, // Opcode: CITAsm +/* 20792 */ MCD_OPC_FilterValue, 115, 84, 0, 0, // Skip to: 20881 +/* 20797 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 20800 */ MCD_OPC_FilterValue, 0, 135, 9, 0, // Skip to: 23244 +/* 20805 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 20808 */ MCD_OPC_FilterValue, 0, 127, 9, 0, // Skip to: 23244 +/* 20813 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 20816 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 20826 +/* 20821 */ MCD_OPC_Decode, 246, 6, 233, 2, // Opcode: CLFITAsmH +/* 20826 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 20836 +/* 20831 */ MCD_OPC_Decode, 248, 6, 233, 2, // Opcode: CLFITAsmL +/* 20836 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 20846 +/* 20841 */ MCD_OPC_Decode, 250, 6, 233, 2, // Opcode: CLFITAsmLH +/* 20846 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 20856 +/* 20851 */ MCD_OPC_Decode, 245, 6, 233, 2, // Opcode: CLFITAsmE +/* 20856 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 20866 +/* 20861 */ MCD_OPC_Decode, 247, 6, 233, 2, // Opcode: CLFITAsmHE +/* 20866 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 20876 +/* 20871 */ MCD_OPC_Decode, 249, 6, 233, 2, // Opcode: CLFITAsmLE +/* 20876 */ MCD_OPC_Decode, 244, 6, 234, 2, // Opcode: CLFITAsm +/* 20881 */ MCD_OPC_FilterValue, 118, 76, 0, 0, // Skip to: 20962 +/* 20886 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 20889 */ MCD_OPC_FilterValue, 0, 46, 9, 0, // Skip to: 23244 +/* 20894 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 20897 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 20907 +/* 20902 */ MCD_OPC_Decode, 243, 8, 235, 2, // Opcode: CRJAsmH +/* 20907 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 20917 +/* 20912 */ MCD_OPC_Decode, 245, 8, 235, 2, // Opcode: CRJAsmL +/* 20917 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 20927 +/* 20922 */ MCD_OPC_Decode, 247, 8, 235, 2, // Opcode: CRJAsmLH +/* 20927 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 20937 +/* 20932 */ MCD_OPC_Decode, 242, 8, 235, 2, // Opcode: CRJAsmE +/* 20937 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 20947 +/* 20942 */ MCD_OPC_Decode, 244, 8, 235, 2, // Opcode: CRJAsmHE +/* 20947 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 20957 +/* 20952 */ MCD_OPC_Decode, 246, 8, 235, 2, // Opcode: CRJAsmLE +/* 20957 */ MCD_OPC_Decode, 241, 8, 236, 2, // Opcode: CRJAsm +/* 20962 */ MCD_OPC_FilterValue, 119, 76, 0, 0, // Skip to: 21043 +/* 20967 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 20970 */ MCD_OPC_FilterValue, 0, 221, 8, 0, // Skip to: 23244 +/* 20975 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 20978 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 20988 +/* 20983 */ MCD_OPC_Decode, 172, 8, 235, 2, // Opcode: CLRJAsmH +/* 20988 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 20998 +/* 20993 */ MCD_OPC_Decode, 174, 8, 235, 2, // Opcode: CLRJAsmL +/* 20998 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 21008 +/* 21003 */ MCD_OPC_Decode, 176, 8, 235, 2, // Opcode: CLRJAsmLH +/* 21008 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 21018 +/* 21013 */ MCD_OPC_Decode, 171, 8, 235, 2, // Opcode: CLRJAsmE +/* 21018 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 21028 +/* 21023 */ MCD_OPC_Decode, 173, 8, 235, 2, // Opcode: CLRJAsmHE +/* 21028 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 21038 +/* 21033 */ MCD_OPC_Decode, 175, 8, 235, 2, // Opcode: CLRJAsmLE +/* 21038 */ MCD_OPC_Decode, 170, 8, 236, 2, // Opcode: CLRJAsm +/* 21043 */ MCD_OPC_FilterValue, 124, 68, 0, 0, // Skip to: 21116 +/* 21048 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 21051 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 21061 +/* 21056 */ MCD_OPC_Decode, 234, 5, 237, 2, // Opcode: CGIJAsmH +/* 21061 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 21071 +/* 21066 */ MCD_OPC_Decode, 236, 5, 237, 2, // Opcode: CGIJAsmL +/* 21071 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 21081 +/* 21076 */ MCD_OPC_Decode, 238, 5, 237, 2, // Opcode: CGIJAsmLH +/* 21081 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 21091 +/* 21086 */ MCD_OPC_Decode, 233, 5, 237, 2, // Opcode: CGIJAsmE +/* 21091 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 21101 +/* 21096 */ MCD_OPC_Decode, 235, 5, 237, 2, // Opcode: CGIJAsmHE +/* 21101 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 21111 +/* 21106 */ MCD_OPC_Decode, 237, 5, 237, 2, // Opcode: CGIJAsmLE +/* 21111 */ MCD_OPC_Decode, 232, 5, 238, 2, // Opcode: CGIJAsm +/* 21116 */ MCD_OPC_FilterValue, 125, 68, 0, 0, // Skip to: 21189 +/* 21121 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 21124 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 21134 +/* 21129 */ MCD_OPC_Decode, 158, 7, 239, 2, // Opcode: CLGIJAsmH +/* 21134 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 21144 +/* 21139 */ MCD_OPC_Decode, 160, 7, 239, 2, // Opcode: CLGIJAsmL +/* 21144 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 21154 +/* 21149 */ MCD_OPC_Decode, 162, 7, 239, 2, // Opcode: CLGIJAsmLH +/* 21154 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 21164 +/* 21159 */ MCD_OPC_Decode, 157, 7, 239, 2, // Opcode: CLGIJAsmE +/* 21164 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 21174 +/* 21169 */ MCD_OPC_Decode, 159, 7, 239, 2, // Opcode: CLGIJAsmHE +/* 21174 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 21184 +/* 21179 */ MCD_OPC_Decode, 161, 7, 239, 2, // Opcode: CLGIJAsmLE +/* 21184 */ MCD_OPC_Decode, 156, 7, 240, 2, // Opcode: CLGIJAsm +/* 21189 */ MCD_OPC_FilterValue, 126, 68, 0, 0, // Skip to: 21262 +/* 21194 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 21197 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 21207 +/* 21202 */ MCD_OPC_Decode, 207, 6, 241, 2, // Opcode: CIJAsmH +/* 21207 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 21217 +/* 21212 */ MCD_OPC_Decode, 209, 6, 241, 2, // Opcode: CIJAsmL +/* 21217 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 21227 +/* 21222 */ MCD_OPC_Decode, 211, 6, 241, 2, // Opcode: CIJAsmLH +/* 21227 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 21237 +/* 21232 */ MCD_OPC_Decode, 206, 6, 241, 2, // Opcode: CIJAsmE +/* 21237 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 21247 +/* 21242 */ MCD_OPC_Decode, 208, 6, 241, 2, // Opcode: CIJAsmHE +/* 21247 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 21257 +/* 21252 */ MCD_OPC_Decode, 210, 6, 241, 2, // Opcode: CIJAsmLE +/* 21257 */ MCD_OPC_Decode, 205, 6, 242, 2, // Opcode: CIJAsm +/* 21262 */ MCD_OPC_FilterValue, 127, 68, 0, 0, // Skip to: 21335 +/* 21267 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 21270 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 21280 +/* 21275 */ MCD_OPC_Decode, 139, 8, 243, 2, // Opcode: CLIJAsmH +/* 21280 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 21290 +/* 21285 */ MCD_OPC_Decode, 141, 8, 243, 2, // Opcode: CLIJAsmL +/* 21290 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 21300 +/* 21295 */ MCD_OPC_Decode, 143, 8, 243, 2, // Opcode: CLIJAsmLH +/* 21300 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 21310 +/* 21305 */ MCD_OPC_Decode, 138, 8, 243, 2, // Opcode: CLIJAsmE +/* 21310 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 21320 +/* 21315 */ MCD_OPC_Decode, 140, 8, 243, 2, // Opcode: CLIJAsmHE +/* 21320 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 21330 +/* 21325 */ MCD_OPC_Decode, 142, 8, 243, 2, // Opcode: CLIJAsmLE +/* 21330 */ MCD_OPC_Decode, 137, 8, 244, 2, // Opcode: CLIJAsm +/* 21335 */ MCD_OPC_FilterValue, 216, 1, 17, 0, 0, // Skip to: 21358 +/* 21341 */ MCD_OPC_CheckPredicate, 23, 106, 7, 0, // Skip to: 23244 +/* 21346 */ MCD_OPC_CheckField, 8, 8, 0, 99, 7, 0, // Skip to: 23244 +/* 21353 */ MCD_OPC_Decode, 135, 4, 245, 2, // Opcode: AHIK +/* 21358 */ MCD_OPC_FilterValue, 217, 1, 17, 0, 0, // Skip to: 21381 +/* 21364 */ MCD_OPC_CheckPredicate, 23, 83, 7, 0, // Skip to: 23244 +/* 21369 */ MCD_OPC_CheckField, 8, 8, 0, 76, 7, 0, // Skip to: 23244 +/* 21376 */ MCD_OPC_Decode, 255, 3, 246, 2, // Opcode: AGHIK +/* 21381 */ MCD_OPC_FilterValue, 218, 1, 17, 0, 0, // Skip to: 21404 +/* 21387 */ MCD_OPC_CheckPredicate, 23, 60, 7, 0, // Skip to: 23244 +/* 21392 */ MCD_OPC_CheckField, 8, 8, 0, 53, 7, 0, // Skip to: 23244 +/* 21399 */ MCD_OPC_Decode, 154, 4, 245, 2, // Opcode: ALHSIK +/* 21404 */ MCD_OPC_FilterValue, 219, 1, 17, 0, 0, // Skip to: 21427 +/* 21410 */ MCD_OPC_CheckPredicate, 23, 37, 7, 0, // Skip to: 23244 +/* 21415 */ MCD_OPC_CheckField, 8, 8, 0, 30, 7, 0, // Skip to: 23244 +/* 21422 */ MCD_OPC_Decode, 148, 4, 246, 2, // Opcode: ALGHSIK +/* 21427 */ MCD_OPC_FilterValue, 228, 1, 76, 0, 0, // Skip to: 21509 +/* 21433 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 21436 */ MCD_OPC_FilterValue, 0, 11, 7, 0, // Skip to: 23244 +/* 21441 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 21444 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 21454 +/* 21449 */ MCD_OPC_Decode, 135, 6, 247, 2, // Opcode: CGRBAsmH +/* 21454 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 21464 +/* 21459 */ MCD_OPC_Decode, 137, 6, 247, 2, // Opcode: CGRBAsmL +/* 21464 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 21474 +/* 21469 */ MCD_OPC_Decode, 139, 6, 247, 2, // Opcode: CGRBAsmLH +/* 21474 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 21484 +/* 21479 */ MCD_OPC_Decode, 134, 6, 247, 2, // Opcode: CGRBAsmE +/* 21484 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 21494 +/* 21489 */ MCD_OPC_Decode, 136, 6, 247, 2, // Opcode: CGRBAsmHE +/* 21494 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 21504 +/* 21499 */ MCD_OPC_Decode, 138, 6, 247, 2, // Opcode: CGRBAsmLE +/* 21504 */ MCD_OPC_Decode, 133, 6, 248, 2, // Opcode: CGRBAsm +/* 21509 */ MCD_OPC_FilterValue, 229, 1, 76, 0, 0, // Skip to: 21591 +/* 21515 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 21518 */ MCD_OPC_FilterValue, 0, 185, 6, 0, // Skip to: 23244 +/* 21523 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 21526 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 21536 +/* 21531 */ MCD_OPC_Decode, 187, 7, 247, 2, // Opcode: CLGRBAsmH +/* 21536 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 21546 +/* 21541 */ MCD_OPC_Decode, 189, 7, 247, 2, // Opcode: CLGRBAsmL +/* 21546 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 21556 +/* 21551 */ MCD_OPC_Decode, 191, 7, 247, 2, // Opcode: CLGRBAsmLH +/* 21556 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 21566 +/* 21561 */ MCD_OPC_Decode, 186, 7, 247, 2, // Opcode: CLGRBAsmE +/* 21566 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 21576 +/* 21571 */ MCD_OPC_Decode, 188, 7, 247, 2, // Opcode: CLGRBAsmHE +/* 21576 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 21586 +/* 21581 */ MCD_OPC_Decode, 190, 7, 247, 2, // Opcode: CLGRBAsmLE +/* 21586 */ MCD_OPC_Decode, 185, 7, 248, 2, // Opcode: CLGRBAsm +/* 21591 */ MCD_OPC_FilterValue, 246, 1, 76, 0, 0, // Skip to: 21673 +/* 21597 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 21600 */ MCD_OPC_FilterValue, 0, 103, 6, 0, // Skip to: 23244 +/* 21605 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 21608 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 21618 +/* 21613 */ MCD_OPC_Decode, 227, 8, 249, 2, // Opcode: CRBAsmH +/* 21618 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 21628 +/* 21623 */ MCD_OPC_Decode, 229, 8, 249, 2, // Opcode: CRBAsmL +/* 21628 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 21638 +/* 21633 */ MCD_OPC_Decode, 231, 8, 249, 2, // Opcode: CRBAsmLH +/* 21638 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 21648 +/* 21643 */ MCD_OPC_Decode, 226, 8, 249, 2, // Opcode: CRBAsmE +/* 21648 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 21658 +/* 21653 */ MCD_OPC_Decode, 228, 8, 249, 2, // Opcode: CRBAsmHE +/* 21658 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 21668 +/* 21663 */ MCD_OPC_Decode, 230, 8, 249, 2, // Opcode: CRBAsmLE +/* 21668 */ MCD_OPC_Decode, 225, 8, 250, 2, // Opcode: CRBAsm +/* 21673 */ MCD_OPC_FilterValue, 247, 1, 76, 0, 0, // Skip to: 21755 +/* 21679 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 21682 */ MCD_OPC_FilterValue, 0, 21, 6, 0, // Skip to: 23244 +/* 21687 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 21690 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 21700 +/* 21695 */ MCD_OPC_Decode, 158, 8, 249, 2, // Opcode: CLRBAsmH +/* 21700 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 21710 +/* 21705 */ MCD_OPC_Decode, 160, 8, 249, 2, // Opcode: CLRBAsmL +/* 21710 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 21720 +/* 21715 */ MCD_OPC_Decode, 162, 8, 249, 2, // Opcode: CLRBAsmLH +/* 21720 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 21730 +/* 21725 */ MCD_OPC_Decode, 157, 8, 249, 2, // Opcode: CLRBAsmE +/* 21730 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 21740 +/* 21735 */ MCD_OPC_Decode, 159, 8, 249, 2, // Opcode: CLRBAsmHE +/* 21740 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 21750 +/* 21745 */ MCD_OPC_Decode, 161, 8, 249, 2, // Opcode: CLRBAsmLE +/* 21750 */ MCD_OPC_Decode, 156, 8, 250, 2, // Opcode: CLRBAsm +/* 21755 */ MCD_OPC_FilterValue, 252, 1, 68, 0, 0, // Skip to: 21829 +/* 21761 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 21764 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 21774 +/* 21769 */ MCD_OPC_Decode, 220, 5, 251, 2, // Opcode: CGIBAsmH +/* 21774 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 21784 +/* 21779 */ MCD_OPC_Decode, 222, 5, 251, 2, // Opcode: CGIBAsmL +/* 21784 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 21794 +/* 21789 */ MCD_OPC_Decode, 224, 5, 251, 2, // Opcode: CGIBAsmLH +/* 21794 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 21804 +/* 21799 */ MCD_OPC_Decode, 219, 5, 251, 2, // Opcode: CGIBAsmE +/* 21804 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 21814 +/* 21809 */ MCD_OPC_Decode, 221, 5, 251, 2, // Opcode: CGIBAsmHE +/* 21814 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 21824 +/* 21819 */ MCD_OPC_Decode, 223, 5, 251, 2, // Opcode: CGIBAsmLE +/* 21824 */ MCD_OPC_Decode, 218, 5, 252, 2, // Opcode: CGIBAsm +/* 21829 */ MCD_OPC_FilterValue, 253, 1, 68, 0, 0, // Skip to: 21903 +/* 21835 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 21838 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 21848 +/* 21843 */ MCD_OPC_Decode, 144, 7, 253, 2, // Opcode: CLGIBAsmH +/* 21848 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 21858 +/* 21853 */ MCD_OPC_Decode, 146, 7, 253, 2, // Opcode: CLGIBAsmL +/* 21858 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 21868 +/* 21863 */ MCD_OPC_Decode, 148, 7, 253, 2, // Opcode: CLGIBAsmLH +/* 21868 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 21878 +/* 21873 */ MCD_OPC_Decode, 143, 7, 253, 2, // Opcode: CLGIBAsmE +/* 21878 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 21888 +/* 21883 */ MCD_OPC_Decode, 145, 7, 253, 2, // Opcode: CLGIBAsmHE +/* 21888 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 21898 +/* 21893 */ MCD_OPC_Decode, 147, 7, 253, 2, // Opcode: CLGIBAsmLE +/* 21898 */ MCD_OPC_Decode, 142, 7, 254, 2, // Opcode: CLGIBAsm +/* 21903 */ MCD_OPC_FilterValue, 254, 1, 68, 0, 0, // Skip to: 21977 +/* 21909 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 21912 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 21922 +/* 21917 */ MCD_OPC_Decode, 192, 6, 255, 2, // Opcode: CIBAsmH +/* 21922 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 21932 +/* 21927 */ MCD_OPC_Decode, 194, 6, 255, 2, // Opcode: CIBAsmL +/* 21932 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 21942 +/* 21937 */ MCD_OPC_Decode, 196, 6, 255, 2, // Opcode: CIBAsmLH +/* 21942 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 21952 +/* 21947 */ MCD_OPC_Decode, 191, 6, 255, 2, // Opcode: CIBAsmE +/* 21952 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 21962 +/* 21957 */ MCD_OPC_Decode, 193, 6, 255, 2, // Opcode: CIBAsmHE +/* 21962 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 21972 +/* 21967 */ MCD_OPC_Decode, 195, 6, 255, 2, // Opcode: CIBAsmLE +/* 21972 */ MCD_OPC_Decode, 190, 6, 128, 3, // Opcode: CIBAsm +/* 21977 */ MCD_OPC_FilterValue, 255, 1, 237, 4, 0, // Skip to: 23244 +/* 21983 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 21986 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 21996 +/* 21991 */ MCD_OPC_Decode, 252, 7, 129, 3, // Opcode: CLIBAsmH +/* 21996 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 22006 +/* 22001 */ MCD_OPC_Decode, 254, 7, 129, 3, // Opcode: CLIBAsmL +/* 22006 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 22016 +/* 22011 */ MCD_OPC_Decode, 128, 8, 129, 3, // Opcode: CLIBAsmLH +/* 22016 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 22026 +/* 22021 */ MCD_OPC_Decode, 251, 7, 129, 3, // Opcode: CLIBAsmE +/* 22026 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 22036 +/* 22031 */ MCD_OPC_Decode, 253, 7, 129, 3, // Opcode: CLIBAsmHE +/* 22036 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 22046 +/* 22041 */ MCD_OPC_Decode, 255, 7, 129, 3, // Opcode: CLIBAsmLE +/* 22046 */ MCD_OPC_Decode, 250, 7, 130, 3, // Opcode: CLIBAsm +/* 22051 */ MCD_OPC_FilterValue, 237, 1, 31, 4, 0, // Skip to: 23112 +/* 22057 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 22060 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 22077 +/* 22065 */ MCD_OPC_CheckField, 8, 8, 0, 148, 4, 0, // Skip to: 23244 +/* 22072 */ MCD_OPC_Decode, 167, 11, 131, 3, // Opcode: LDEB +/* 22077 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 22094 +/* 22082 */ MCD_OPC_CheckField, 8, 8, 0, 131, 4, 0, // Skip to: 23244 +/* 22089 */ MCD_OPC_Decode, 251, 13, 132, 3, // Opcode: LXDB +/* 22094 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 22111 +/* 22099 */ MCD_OPC_CheckField, 8, 8, 0, 114, 4, 0, // Skip to: 23244 +/* 22106 */ MCD_OPC_Decode, 128, 14, 132, 3, // Opcode: LXEB +/* 22111 */ MCD_OPC_FilterValue, 7, 12, 0, 0, // Skip to: 22128 +/* 22116 */ MCD_OPC_CheckField, 8, 8, 0, 97, 4, 0, // Skip to: 23244 +/* 22123 */ MCD_OPC_Decode, 231, 14, 133, 3, // Opcode: MXDB +/* 22128 */ MCD_OPC_FilterValue, 8, 12, 0, 0, // Skip to: 22145 +/* 22133 */ MCD_OPC_CheckField, 8, 8, 0, 80, 4, 0, // Skip to: 23244 +/* 22140 */ MCD_OPC_Decode, 240, 10, 134, 3, // Opcode: KEB +/* 22145 */ MCD_OPC_FilterValue, 9, 12, 0, 0, // Skip to: 22162 +/* 22150 */ MCD_OPC_CheckField, 8, 8, 0, 63, 4, 0, // Skip to: 23244 +/* 22157 */ MCD_OPC_Decode, 174, 5, 134, 3, // Opcode: CEB +/* 22162 */ MCD_OPC_FilterValue, 10, 12, 0, 0, // Skip to: 22179 +/* 22167 */ MCD_OPC_CheckField, 8, 8, 0, 46, 4, 0, // Skip to: 23244 +/* 22174 */ MCD_OPC_Decode, 245, 3, 135, 3, // Opcode: AEB +/* 22179 */ MCD_OPC_FilterValue, 11, 12, 0, 0, // Skip to: 22196 +/* 22184 */ MCD_OPC_CheckField, 8, 8, 0, 29, 4, 0, // Skip to: 23244 +/* 22191 */ MCD_OPC_Decode, 230, 15, 135, 3, // Opcode: SEB +/* 22196 */ MCD_OPC_FilterValue, 12, 12, 0, 0, // Skip to: 22213 +/* 22201 */ MCD_OPC_CheckField, 8, 8, 0, 12, 4, 0, // Skip to: 23244 +/* 22208 */ MCD_OPC_Decode, 158, 14, 136, 3, // Opcode: MDEB +/* 22213 */ MCD_OPC_FilterValue, 13, 12, 0, 0, // Skip to: 22230 +/* 22218 */ MCD_OPC_CheckField, 8, 8, 0, 251, 3, 0, // Skip to: 23244 +/* 22225 */ MCD_OPC_Decode, 204, 9, 135, 3, // Opcode: DEB +/* 22230 */ MCD_OPC_FilterValue, 14, 12, 0, 0, // Skip to: 22247 +/* 22235 */ MCD_OPC_CheckField, 8, 4, 0, 234, 3, 0, // Skip to: 23244 +/* 22242 */ MCD_OPC_Decode, 144, 14, 137, 3, // Opcode: MAEB +/* 22247 */ MCD_OPC_FilterValue, 15, 12, 0, 0, // Skip to: 22264 +/* 22252 */ MCD_OPC_CheckField, 8, 4, 0, 217, 3, 0, // Skip to: 23244 +/* 22259 */ MCD_OPC_Decode, 192, 14, 137, 3, // Opcode: MSEB +/* 22264 */ MCD_OPC_FilterValue, 16, 12, 0, 0, // Skip to: 22281 +/* 22269 */ MCD_OPC_CheckField, 8, 8, 0, 200, 3, 0, // Skip to: 23244 +/* 22276 */ MCD_OPC_Decode, 137, 18, 134, 3, // Opcode: TCEB +/* 22281 */ MCD_OPC_FilterValue, 17, 12, 0, 0, // Skip to: 22298 +/* 22286 */ MCD_OPC_CheckField, 8, 8, 0, 183, 3, 0, // Skip to: 23244 +/* 22293 */ MCD_OPC_Decode, 136, 18, 131, 3, // Opcode: TCDB +/* 22298 */ MCD_OPC_FilterValue, 18, 12, 0, 0, // Skip to: 22315 +/* 22303 */ MCD_OPC_CheckField, 8, 8, 0, 166, 3, 0, // Skip to: 23244 +/* 22310 */ MCD_OPC_Decode, 138, 18, 132, 3, // Opcode: TCXB +/* 22315 */ MCD_OPC_FilterValue, 20, 12, 0, 0, // Skip to: 22332 +/* 22320 */ MCD_OPC_CheckField, 8, 8, 0, 149, 3, 0, // Skip to: 23244 +/* 22327 */ MCD_OPC_Decode, 225, 16, 134, 3, // Opcode: SQEB +/* 22332 */ MCD_OPC_FilterValue, 21, 12, 0, 0, // Skip to: 22349 +/* 22337 */ MCD_OPC_CheckField, 8, 8, 0, 132, 3, 0, // Skip to: 23244 +/* 22344 */ MCD_OPC_Decode, 221, 16, 131, 3, // Opcode: SQDB +/* 22349 */ MCD_OPC_FilterValue, 23, 12, 0, 0, // Skip to: 22366 +/* 22354 */ MCD_OPC_CheckField, 8, 8, 0, 115, 3, 0, // Skip to: 23244 +/* 22361 */ MCD_OPC_Decode, 166, 14, 135, 3, // Opcode: MEEB +/* 22366 */ MCD_OPC_FilterValue, 24, 12, 0, 0, // Skip to: 22383 +/* 22371 */ MCD_OPC_CheckField, 8, 8, 0, 98, 3, 0, // Skip to: 23244 +/* 22378 */ MCD_OPC_Decode, 236, 10, 131, 3, // Opcode: KDB +/* 22383 */ MCD_OPC_FilterValue, 25, 12, 0, 0, // Skip to: 22400 +/* 22388 */ MCD_OPC_CheckField, 8, 8, 0, 81, 3, 0, // Skip to: 23244 +/* 22395 */ MCD_OPC_Decode, 149, 5, 131, 3, // Opcode: CDB +/* 22400 */ MCD_OPC_FilterValue, 26, 12, 0, 0, // Skip to: 22417 +/* 22405 */ MCD_OPC_CheckField, 8, 8, 0, 64, 3, 0, // Skip to: 23244 +/* 22412 */ MCD_OPC_Decode, 239, 3, 136, 3, // Opcode: ADB +/* 22417 */ MCD_OPC_FilterValue, 27, 12, 0, 0, // Skip to: 22434 +/* 22422 */ MCD_OPC_CheckField, 8, 8, 0, 47, 3, 0, // Skip to: 23244 +/* 22429 */ MCD_OPC_Decode, 224, 15, 136, 3, // Opcode: SDB +/* 22434 */ MCD_OPC_FilterValue, 28, 12, 0, 0, // Skip to: 22451 +/* 22439 */ MCD_OPC_CheckField, 8, 8, 0, 30, 3, 0, // Skip to: 23244 +/* 22446 */ MCD_OPC_Decode, 155, 14, 136, 3, // Opcode: MDB +/* 22451 */ MCD_OPC_FilterValue, 29, 12, 0, 0, // Skip to: 22468 +/* 22456 */ MCD_OPC_CheckField, 8, 8, 0, 13, 3, 0, // Skip to: 23244 +/* 22463 */ MCD_OPC_Decode, 198, 9, 136, 3, // Opcode: DDB +/* 22468 */ MCD_OPC_FilterValue, 30, 12, 0, 0, // Skip to: 22485 +/* 22473 */ MCD_OPC_CheckField, 8, 4, 0, 252, 2, 0, // Skip to: 23244 +/* 22480 */ MCD_OPC_Decode, 140, 14, 138, 3, // Opcode: MADB +/* 22485 */ MCD_OPC_FilterValue, 31, 12, 0, 0, // Skip to: 22502 +/* 22490 */ MCD_OPC_CheckField, 8, 4, 0, 235, 2, 0, // Skip to: 23244 +/* 22497 */ MCD_OPC_Decode, 188, 14, 138, 3, // Opcode: MSDB +/* 22502 */ MCD_OPC_FilterValue, 36, 12, 0, 0, // Skip to: 22519 +/* 22507 */ MCD_OPC_CheckField, 8, 8, 0, 218, 2, 0, // Skip to: 23244 +/* 22514 */ MCD_OPC_Decode, 165, 11, 131, 3, // Opcode: LDE +/* 22519 */ MCD_OPC_FilterValue, 37, 12, 0, 0, // Skip to: 22536 +/* 22524 */ MCD_OPC_CheckField, 8, 8, 0, 201, 2, 0, // Skip to: 23244 +/* 22531 */ MCD_OPC_Decode, 250, 13, 132, 3, // Opcode: LXD +/* 22536 */ MCD_OPC_FilterValue, 38, 12, 0, 0, // Skip to: 22553 +/* 22541 */ MCD_OPC_CheckField, 8, 8, 0, 184, 2, 0, // Skip to: 23244 +/* 22548 */ MCD_OPC_Decode, 255, 13, 132, 3, // Opcode: LXE +/* 22553 */ MCD_OPC_FilterValue, 46, 12, 0, 0, // Skip to: 22570 +/* 22558 */ MCD_OPC_CheckField, 8, 4, 0, 167, 2, 0, // Skip to: 23244 +/* 22565 */ MCD_OPC_Decode, 143, 14, 137, 3, // Opcode: MAE +/* 22570 */ MCD_OPC_FilterValue, 47, 12, 0, 0, // Skip to: 22587 +/* 22575 */ MCD_OPC_CheckField, 8, 4, 0, 150, 2, 0, // Skip to: 23244 +/* 22582 */ MCD_OPC_Decode, 191, 14, 137, 3, // Opcode: MSE +/* 22587 */ MCD_OPC_FilterValue, 52, 12, 0, 0, // Skip to: 22604 +/* 22592 */ MCD_OPC_CheckField, 8, 8, 0, 133, 2, 0, // Skip to: 23244 +/* 22599 */ MCD_OPC_Decode, 224, 16, 134, 3, // Opcode: SQE +/* 22604 */ MCD_OPC_FilterValue, 53, 12, 0, 0, // Skip to: 22621 +/* 22609 */ MCD_OPC_CheckField, 8, 8, 0, 116, 2, 0, // Skip to: 23244 +/* 22616 */ MCD_OPC_Decode, 220, 16, 131, 3, // Opcode: SQD +/* 22621 */ MCD_OPC_FilterValue, 55, 12, 0, 0, // Skip to: 22638 +/* 22626 */ MCD_OPC_CheckField, 8, 8, 0, 99, 2, 0, // Skip to: 23244 +/* 22633 */ MCD_OPC_Decode, 165, 14, 135, 3, // Opcode: MEE +/* 22638 */ MCD_OPC_FilterValue, 56, 12, 0, 0, // Skip to: 22655 +/* 22643 */ MCD_OPC_CheckField, 8, 4, 0, 82, 2, 0, // Skip to: 23244 +/* 22650 */ MCD_OPC_Decode, 150, 14, 138, 3, // Opcode: MAYL +/* 22655 */ MCD_OPC_FilterValue, 57, 12, 0, 0, // Skip to: 22672 +/* 22660 */ MCD_OPC_CheckField, 8, 4, 0, 65, 2, 0, // Skip to: 23244 +/* 22667 */ MCD_OPC_Decode, 240, 14, 139, 3, // Opcode: MYL +/* 22672 */ MCD_OPC_FilterValue, 58, 12, 0, 0, // Skip to: 22689 +/* 22677 */ MCD_OPC_CheckField, 8, 4, 0, 48, 2, 0, // Skip to: 23244 +/* 22684 */ MCD_OPC_Decode, 147, 14, 140, 3, // Opcode: MAY +/* 22689 */ MCD_OPC_FilterValue, 59, 12, 0, 0, // Skip to: 22706 +/* 22694 */ MCD_OPC_CheckField, 8, 4, 0, 31, 2, 0, // Skip to: 23244 +/* 22701 */ MCD_OPC_Decode, 237, 14, 141, 3, // Opcode: MY +/* 22706 */ MCD_OPC_FilterValue, 60, 12, 0, 0, // Skip to: 22723 +/* 22711 */ MCD_OPC_CheckField, 8, 4, 0, 14, 2, 0, // Skip to: 23244 +/* 22718 */ MCD_OPC_Decode, 148, 14, 138, 3, // Opcode: MAYH +/* 22723 */ MCD_OPC_FilterValue, 61, 12, 0, 0, // Skip to: 22740 +/* 22728 */ MCD_OPC_CheckField, 8, 4, 0, 253, 1, 0, // Skip to: 23244 +/* 22735 */ MCD_OPC_Decode, 238, 14, 139, 3, // Opcode: MYH +/* 22740 */ MCD_OPC_FilterValue, 62, 12, 0, 0, // Skip to: 22757 +/* 22745 */ MCD_OPC_CheckField, 8, 4, 0, 236, 1, 0, // Skip to: 23244 +/* 22752 */ MCD_OPC_Decode, 139, 14, 138, 3, // Opcode: MAD +/* 22757 */ MCD_OPC_FilterValue, 63, 12, 0, 0, // Skip to: 22774 +/* 22762 */ MCD_OPC_CheckField, 8, 4, 0, 219, 1, 0, // Skip to: 23244 +/* 22769 */ MCD_OPC_Decode, 187, 14, 138, 3, // Opcode: MSD +/* 22774 */ MCD_OPC_FilterValue, 64, 12, 0, 0, // Skip to: 22791 +/* 22779 */ MCD_OPC_CheckField, 8, 4, 0, 202, 1, 0, // Skip to: 23244 +/* 22786 */ MCD_OPC_Decode, 196, 16, 139, 3, // Opcode: SLDT +/* 22791 */ MCD_OPC_FilterValue, 65, 12, 0, 0, // Skip to: 22808 +/* 22796 */ MCD_OPC_CheckField, 8, 4, 0, 185, 1, 0, // Skip to: 23244 +/* 22803 */ MCD_OPC_Decode, 236, 16, 139, 3, // Opcode: SRDT +/* 22808 */ MCD_OPC_FilterValue, 72, 12, 0, 0, // Skip to: 22825 +/* 22813 */ MCD_OPC_CheckField, 8, 4, 0, 168, 1, 0, // Skip to: 23244 +/* 22820 */ MCD_OPC_Decode, 211, 16, 142, 3, // Opcode: SLXT +/* 22825 */ MCD_OPC_FilterValue, 73, 12, 0, 0, // Skip to: 22842 +/* 22830 */ MCD_OPC_CheckField, 8, 4, 0, 151, 1, 0, // Skip to: 23244 +/* 22837 */ MCD_OPC_Decode, 247, 16, 142, 3, // Opcode: SRXT +/* 22842 */ MCD_OPC_FilterValue, 80, 12, 0, 0, // Skip to: 22859 +/* 22847 */ MCD_OPC_CheckField, 8, 8, 0, 134, 1, 0, // Skip to: 23244 +/* 22854 */ MCD_OPC_Decode, 140, 18, 134, 3, // Opcode: TDCET +/* 22859 */ MCD_OPC_FilterValue, 81, 12, 0, 0, // Skip to: 22876 +/* 22864 */ MCD_OPC_CheckField, 8, 8, 0, 117, 1, 0, // Skip to: 23244 +/* 22871 */ MCD_OPC_Decode, 143, 18, 134, 3, // Opcode: TDGET +/* 22876 */ MCD_OPC_FilterValue, 84, 12, 0, 0, // Skip to: 22893 +/* 22881 */ MCD_OPC_CheckField, 8, 8, 0, 100, 1, 0, // Skip to: 23244 +/* 22888 */ MCD_OPC_Decode, 139, 18, 131, 3, // Opcode: TDCDT +/* 22893 */ MCD_OPC_FilterValue, 85, 12, 0, 0, // Skip to: 22910 +/* 22898 */ MCD_OPC_CheckField, 8, 8, 0, 83, 1, 0, // Skip to: 23244 +/* 22905 */ MCD_OPC_Decode, 142, 18, 131, 3, // Opcode: TDGDT +/* 22910 */ MCD_OPC_FilterValue, 88, 12, 0, 0, // Skip to: 22927 +/* 22915 */ MCD_OPC_CheckField, 8, 8, 0, 66, 1, 0, // Skip to: 23244 +/* 22922 */ MCD_OPC_Decode, 141, 18, 132, 3, // Opcode: TDCXT +/* 22927 */ MCD_OPC_FilterValue, 89, 12, 0, 0, // Skip to: 22944 +/* 22932 */ MCD_OPC_CheckField, 8, 8, 0, 49, 1, 0, // Skip to: 23244 +/* 22939 */ MCD_OPC_Decode, 144, 18, 132, 3, // Opcode: TDGXT +/* 22944 */ MCD_OPC_FilterValue, 100, 5, 0, 0, // Skip to: 22954 +/* 22949 */ MCD_OPC_Decode, 188, 11, 143, 3, // Opcode: LEY +/* 22954 */ MCD_OPC_FilterValue, 101, 5, 0, 0, // Skip to: 22964 +/* 22959 */ MCD_OPC_Decode, 178, 11, 144, 3, // Opcode: LDY +/* 22964 */ MCD_OPC_FilterValue, 102, 5, 0, 0, // Skip to: 22974 +/* 22969 */ MCD_OPC_Decode, 148, 17, 143, 3, // Opcode: STEY +/* 22974 */ MCD_OPC_FilterValue, 103, 5, 0, 0, // Skip to: 22984 +/* 22979 */ MCD_OPC_Decode, 146, 17, 144, 3, // Opcode: STDY +/* 22984 */ MCD_OPC_FilterValue, 168, 1, 10, 0, 0, // Skip to: 23000 +/* 22990 */ MCD_OPC_CheckPredicate, 37, 249, 0, 0, // Skip to: 23244 +/* 22995 */ MCD_OPC_Decode, 194, 9, 145, 3, // Opcode: CZDT +/* 23000 */ MCD_OPC_FilterValue, 169, 1, 10, 0, 0, // Skip to: 23016 +/* 23006 */ MCD_OPC_CheckPredicate, 37, 233, 0, 0, // Skip to: 23244 +/* 23011 */ MCD_OPC_Decode, 195, 9, 146, 3, // Opcode: CZXT +/* 23016 */ MCD_OPC_FilterValue, 170, 1, 10, 0, 0, // Skip to: 23032 +/* 23022 */ MCD_OPC_CheckPredicate, 37, 217, 0, 0, // Skip to: 23244 +/* 23027 */ MCD_OPC_Decode, 172, 5, 145, 3, // Opcode: CDZT +/* 23032 */ MCD_OPC_FilterValue, 171, 1, 10, 0, 0, // Skip to: 23048 +/* 23038 */ MCD_OPC_CheckPredicate, 37, 201, 0, 0, // Skip to: 23244 +/* 23043 */ MCD_OPC_Decode, 192, 9, 146, 3, // Opcode: CXZT +/* 23048 */ MCD_OPC_FilterValue, 172, 1, 10, 0, 0, // Skip to: 23064 +/* 23054 */ MCD_OPC_CheckPredicate, 38, 185, 0, 0, // Skip to: 23244 +/* 23059 */ MCD_OPC_Decode, 216, 8, 145, 3, // Opcode: CPDT +/* 23064 */ MCD_OPC_FilterValue, 173, 1, 10, 0, 0, // Skip to: 23080 +/* 23070 */ MCD_OPC_CheckPredicate, 38, 169, 0, 0, // Skip to: 23244 +/* 23075 */ MCD_OPC_Decode, 221, 8, 146, 3, // Opcode: CPXT +/* 23080 */ MCD_OPC_FilterValue, 174, 1, 10, 0, 0, // Skip to: 23096 +/* 23086 */ MCD_OPC_CheckPredicate, 38, 153, 0, 0, // Skip to: 23244 +/* 23091 */ MCD_OPC_Decode, 164, 5, 145, 3, // Opcode: CDPT +/* 23096 */ MCD_OPC_FilterValue, 175, 1, 142, 0, 0, // Skip to: 23244 +/* 23102 */ MCD_OPC_CheckPredicate, 38, 137, 0, 0, // Skip to: 23244 +/* 23107 */ MCD_OPC_Decode, 187, 9, 146, 3, // Opcode: CXPT +/* 23112 */ MCD_OPC_FilterValue, 238, 1, 5, 0, 0, // Skip to: 23123 +/* 23118 */ MCD_OPC_Decode, 174, 15, 147, 3, // Opcode: PLO +/* 23123 */ MCD_OPC_FilterValue, 239, 1, 5, 0, 0, // Skip to: 23134 +/* 23129 */ MCD_OPC_Decode, 244, 11, 148, 3, // Opcode: LMD +/* 23134 */ MCD_OPC_FilterValue, 240, 1, 5, 0, 0, // Skip to: 23145 +/* 23140 */ MCD_OPC_Decode, 244, 16, 149, 3, // Opcode: SRP +/* 23145 */ MCD_OPC_FilterValue, 241, 1, 5, 0, 0, // Skip to: 23156 +/* 23151 */ MCD_OPC_Decode, 225, 14, 150, 3, // Opcode: MVO +/* 23156 */ MCD_OPC_FilterValue, 242, 1, 5, 0, 0, // Skip to: 23167 +/* 23162 */ MCD_OPC_Decode, 161, 15, 150, 3, // Opcode: PACK +/* 23167 */ MCD_OPC_FilterValue, 243, 1, 5, 0, 0, // Skip to: 23178 +/* 23173 */ MCD_OPC_Decode, 179, 18, 150, 3, // Opcode: UNPK +/* 23178 */ MCD_OPC_FilterValue, 248, 1, 5, 0, 0, // Skip to: 23189 +/* 23184 */ MCD_OPC_Decode, 160, 24, 150, 3, // Opcode: ZAP +/* 23189 */ MCD_OPC_FilterValue, 249, 1, 5, 0, 0, // Skip to: 23200 +/* 23195 */ MCD_OPC_Decode, 215, 8, 150, 3, // Opcode: CP +/* 23200 */ MCD_OPC_FilterValue, 250, 1, 5, 0, 0, // Skip to: 23211 +/* 23206 */ MCD_OPC_Decode, 161, 4, 150, 3, // Opcode: AP +/* 23211 */ MCD_OPC_FilterValue, 251, 1, 5, 0, 0, // Skip to: 23222 +/* 23217 */ MCD_OPC_Decode, 214, 16, 150, 3, // Opcode: SP +/* 23222 */ MCD_OPC_FilterValue, 252, 1, 5, 0, 0, // Skip to: 23233 +/* 23228 */ MCD_OPC_Decode, 182, 14, 150, 3, // Opcode: MP +/* 23233 */ MCD_OPC_FilterValue, 253, 1, 5, 0, 0, // Skip to: 23244 +/* 23239 */ MCD_OPC_Decode, 215, 9, 150, 3, // Opcode: DP +/* 23244 */ MCD_OPC_Fail, 0 }; -static bool getbool(uint64_t b) -{ - return b != 0; -} - -static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) -{ +static bool checkDecoderPredicate(MCInst *Inst, unsigned Idx) { switch (Idx) { - default: // llvm_unreachable("Invalid index!"); + default: /* llvm_unreachable("Invalid index!"); */ case 0: - return getbool((Bits & SystemZ_FeatureFPExtension)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureBEAREnhancement)); case 1: - return getbool((Bits & SystemZ_FeatureProcessorAssist)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureProcessorActivityInstrumentation)); case 2: - return getbool((Bits & SystemZ_FeatureTransactionalExecution)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureFPExtension)); case 3: - return getbool((Bits & SystemZ_FeatureExecutionHint)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureProcessorAssist)); case 4: - return getbool((Bits & SystemZ_FeatureMessageSecurityAssist3)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureTransactionalExecution)); case 5: - return getbool((Bits & SystemZ_FeatureMessageSecurityAssist8)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureExecutionHint)); case 6: - return getbool((Bits & SystemZ_FeatureMessageSecurityAssist4)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureMessageSecurityAssist3)); case 7: - return getbool((Bits & SystemZ_FeatureMessageSecurityAssist5)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureMessageSecurityAssist8)); case 8: - return getbool((Bits & SystemZ_FeatureEnhancedDAT2)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureMessageSecurityAssist4)); case 9: - return getbool((Bits & SystemZ_FeatureInsertReferenceBitsMultiple)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureEnhancedSort)); case 10: - return getbool((Bits & SystemZ_FeatureResetReferenceBitsMultiple)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureDeflateConversion)); case 11: - return getbool((Bits & SystemZ_FeatureHighWord)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureMessageSecurityAssist9)); case 12: - return getbool((Bits & SystemZ_FeatureLoadStoreOnCond2)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureNNPAssist)); case 13: - return getbool((Bits & SystemZ_FeaturePopulationCount)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureMessageSecurityAssist5)); case 14: - return getbool((Bits & SystemZ_FeatureLoadStoreOnCond)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureMiscellaneousExtensions3)); case 15: - return getbool((Bits & SystemZ_FeatureDistinctOps)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureResetDATProtection)); case 16: - return getbool((Bits & SystemZ_FeatureMiscellaneousExtensions2)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureEnhancedDAT2)); case 17: - return getbool((Bits & SystemZ_FeatureInterlockedAccess1)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureInsertReferenceBitsMultiple)); case 18: - return getbool((Bits & SystemZ_FeatureLoadAndZeroRightmostByte)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureResetReferenceBitsMultiple)); case 19: - return getbool((Bits & SystemZ_FeatureGuardedStorage)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureHighWord)); case 20: - return getbool((Bits & SystemZ_FeatureLoadAndTrap)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureLoadStoreOnCond2)); case 21: - return getbool((Bits & SystemZ_FeatureVectorPackedDecimal)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeaturePopulationCount)); case 22: - return getbool((Bits & SystemZ_FeatureVector)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureLoadStoreOnCond)); case 23: - return getbool((Bits & SystemZ_FeatureVectorEnhancements1)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureDistinctOps)); case 24: - return getbool((Bits & SystemZ_FeatureMiscellaneousExtensions)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureMiscellaneousExtensions2)); case 25: - return getbool((Bits & SystemZ_FeatureDFPZonedConversion)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureInterlockedAccess1)); case 26: - return getbool((Bits & SystemZ_FeatureDFPPackedConversion)); + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureLoadAndZeroRightmostByte)); + case 27: + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureGuardedStorage)); + case 28: + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureLoadAndTrap)); + case 29: + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureVectorEnhancements2)); + case 30: + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureVectorPackedDecimal)); + case 31: + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureVectorPackedDecimalEnhancement)); + case 32: + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureVectorPackedDecimalEnhancement2)); + case 33: + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureVector) && SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureNNPAssist)); + case 34: + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureVector)); + case 35: + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureVectorEnhancements1)); + case 36: + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureMiscellaneousExtensions)); + case 37: + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureDFPZonedConversion)); + case 38: + return (SystemZ_getFeatureBits(Inst->csh->mode, SystemZ_FeatureDFPPackedConversion)); } } -#define DecodeToMCInst(fname,fieldname, InsnType) \ +#define DecodeToMCInst(fname, fieldname, InsnType) \ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ - uint64_t Address, const void *Decoder) \ + uint64_t Address, const void *Decoder, bool *DecodeComplete) \ { \ + *DecodeComplete = true; \ InsnType tmp; \ switch (Idx) { \ - default: \ + default: /* llvm_unreachable("Invalid index!"); */ \ case 0: \ return S; \ case 1: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 2: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 3: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 4: \ tmp = fieldname(insn, 0, 4); \ - if (DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 5: \ tmp = fieldname(insn, 4, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 6: \ tmp = fieldname(insn, 0, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 7: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 8: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 9: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 10: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 11: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 12: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 13: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 14: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 15: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 16: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 17: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 18: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 19: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 20: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 21: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 22: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 23: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 24: \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 25: \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 26: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 27: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 28: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 29: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 30: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 31: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 32: \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 33: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 33: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 34: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 35: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 36: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 37: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 38: \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 39: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 8); \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 40: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 41: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 42: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 43: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 44: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 45: \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 46: \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 47: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 48: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 49: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 50: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 51: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 52: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 53: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 54: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 55: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 56: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 57: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 58: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 59: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 60: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 61: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 62: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 63: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 64: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 65: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 66: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 67: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 68: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 69: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 70: \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 71: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 71: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 72: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 73: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 74: \ tmp = fieldname(insn, 4, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 75: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 76: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 77: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 78: \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 79: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 80: \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 81: \ tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 82: \ tmp = fieldname(insn, 12, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 83: \ tmp = fieldname(insn, 12, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 84: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 85: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 86: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 87: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 88: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 89: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 90: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 91: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 92: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 93: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 94: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 95: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 96: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 97: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 98: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 99: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 100: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 101: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 102: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 103: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 104: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 105: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 106: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 107: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 108: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 109: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 110: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 111: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 112: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 113: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 114: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 115: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 116: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 117: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 118: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 119: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 120: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 121: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 122: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 123: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 124: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 125: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 126: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 127: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 128: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 129: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 130: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 131: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 132: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 133: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 134: \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 134: \ + case 135: \ tmp = fieldname(insn, 20, 4); \ - if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ - if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 135: \ + case 136: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 136: \ + case 137: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 137: \ + case 138: \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 138: \ + case 139: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 139: \ + case 140: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 140: \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 141: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 142: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 143: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 144: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 145: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 146: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 147: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 148: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 149: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 150: \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 151: \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 152: \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 153: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 154: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 155: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 156: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 157: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 158: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 159: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 160: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 161: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 162: \ tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 163: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 164: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 165: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ case 166: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodePC32DBLOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 167: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 168: \ - tmp = fieldname(insn, 0, 32); \ - if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 169: \ - tmp = fieldname(insn, 36, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 170: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 171: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 172: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 173: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 174: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 32); \ - if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC32DBLOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 175: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 32); \ - if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS32ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 176: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 32); \ - if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC32DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 177: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 32); \ - if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC32DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 178: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 32); \ - if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC32DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 179: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 32); \ - if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU32ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 180: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 32); \ - if (decodePC32DBLOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU32ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 181: \ tmp = fieldname(insn, 36, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 24, 12); \ - if (decodePC12DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 24); \ - if (decodePC24DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 32); \ + if (!Check(&S, decodeU32ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 182: \ tmp = fieldname(insn, 36, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 32); \ - if (decodePC32DBLOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU32ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 183: \ tmp = fieldname(insn, 36, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 32); \ + if (!Check(&S, decodeU32ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 184: \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 32); \ + if (!Check(&S, decodeS32ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 185: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 32); \ + if (!Check(&S, decodeS32ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 186: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 32); \ - if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU32ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 187: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 32); \ - if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS32ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 188: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 32); \ - if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC32DBLOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 189: \ - tmp = fieldname(insn, 16, 24); \ - if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 24, 12); \ + if (!Check(&S, decodePC12DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 24); \ + if (!Check(&S, decodePC24DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 190: \ - tmp = 0; \ - tmp |= fieldname(insn, 16, 16) << 0; \ - tmp |= fieldname(insn, 36, 4) << 16; \ - if (decodeBDRAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 32); \ + if (!Check(&S, decodePC32DBLOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 191: \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 16) << 0; \ - tmp |= fieldname(insn, 32, 8) << 16; \ - if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 32); \ + if (!Check(&S, decodePC32DBLOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 192: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 193: \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 194: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 195: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 32); \ + if (!Check(&S, decodePC32DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 196: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 32); \ + if (!Check(&S, decodeS32ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 197: \ tmp = fieldname(insn, 36, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 32); \ + if (!Check(&S, decodeS32ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 198: \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 8); \ + if (!Check(&S, decodeLenOperand_8(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 199: \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 200: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 8); \ + if (!Check(&S, decodeLenOperand_8(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 201: \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 202: \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 203: \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 204: \ - tmp = 0; \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 205: \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 206: \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 207: \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 208: \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 209: \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 210: \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 211: \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 212: \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, decodeU16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 213: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU3ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 214: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU1ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 215: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU2ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 216: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 217: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 218: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU3ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 219: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU1ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 220: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU2ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 221: \ + tmp = 0x0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 205: \ - tmp = 0; \ + case 222: \ + tmp = 0x0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 206: \ - tmp = 0; \ + case 223: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 207: \ + case 224: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 208: \ + case 225: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 209: \ - tmp = 0; \ + case 226: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 227: \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 228: \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 229: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 230: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 210: \ - tmp = 0; \ + case 231: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 24, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 211: \ - tmp = 0; \ + case 232: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 212: \ - tmp = 0; \ + case 233: \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 213: \ - tmp = 0; \ + case 234: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 214: \ - tmp = 0; \ + case 235: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 215: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 216: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU3ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 217: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + case 236: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 218: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + case 237: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 219: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 220: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 238: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 221: \ - tmp = 0; \ + case 239: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU3ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 222: \ - tmp = 0; \ + case 240: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 223: \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 224: \ - tmp = 0; \ + case 241: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 20; \ - tmp |= fieldname(insn, 16, 20) << 0; \ - if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU1ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 225: \ - tmp = 0; \ + case 242: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 20; \ - tmp |= fieldname(insn, 16, 20) << 0; \ - if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU2ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 226: \ - tmp = 0; \ + case 243: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 20; \ - tmp |= fieldname(insn, 16, 20) << 0; \ - if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU1ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 227: \ - tmp = 0; \ + case 244: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 20; \ - tmp |= fieldname(insn, 16, 20) << 0; \ - if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU2ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 228: \ + case 245: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 229: \ + case 246: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 230: \ - tmp = 0; \ + case 247: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 231: \ - tmp = 0; \ + case 248: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 232: \ - tmp = 0; \ + case 249: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 233: \ + case 250: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 234: \ - tmp = 0; \ + case 251: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 235: \ - tmp = 0; \ + case 252: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 236: \ - tmp = 0; \ + case 253: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 237: \ - tmp = 0; \ + case 254: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 255: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 238: \ - tmp = 0; \ + case 256: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 239: \ - tmp = 0; \ + case 257: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU3ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU3ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 240: \ - tmp = 0; \ + case 258: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU1ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 241: \ - tmp = 0; \ + case 259: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU2ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 242: \ - tmp = 0; \ + case 260: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 243: \ - tmp = 0; \ + case 261: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 244: \ - tmp = 0; \ + case 262: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 245: \ - tmp = 0; \ + case 263: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 246: \ - tmp = 0; \ + case 264: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 24, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 247: \ - tmp = 0; \ + case 265: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 24, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 248: \ - tmp = 0; \ + case 266: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 12); \ - if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 249: \ - tmp = 0; \ + case 267: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 12); \ - if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 250: \ - tmp = 0; \ + case 268: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 12); \ - if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 251: \ - tmp = 0; \ + case 269: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 12); \ - if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 252: \ - tmp = 0; \ + case 270: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 253: \ - tmp = 0; \ + case 271: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 254: \ - tmp = 0; \ + case 272: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 255: \ - tmp = 0; \ + case 273: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 256: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 257: \ - tmp = 0; \ + case 274: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 258: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 259: \ - tmp = 0; \ + case 275: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 260: \ - tmp = 0; \ + case 276: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 261: \ - tmp = 0; \ + case 277: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 262: \ - tmp = 0; \ + case 278: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 263: \ - tmp = 0; \ + case 279: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 264: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 265: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 266: \ - tmp = 0; \ + case 280: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 22, 2) << 2; \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 267: \ - tmp = 0; \ + case 281: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 3) << 1; \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 268: \ - tmp = 0; \ + case 282: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 20, 1) << 0; \ tmp |= fieldname(insn, 22, 2) << 2; \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 269: \ - tmp = 0; \ + case 283: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 22, 2) << 2; \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 270: \ - tmp = 0; \ + case 284: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 3) << 1; \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 271: \ - tmp = 0; \ + case 285: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 20, 1) << 0; \ tmp |= fieldname(insn, 22, 2) << 2; \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 272: \ - tmp = 0; \ + case 286: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 273: \ - tmp = 0; \ + case 287: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 24, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 274: \ - tmp = 0; \ + case 288: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 275: \ - tmp = 0; \ + case 289: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 276: \ - tmp = 0; \ + case 290: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 277: \ - tmp = 0; \ + case 291: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 24, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 278: \ - tmp = 0; \ + case 292: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 24, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 279: \ - tmp = 0; \ + case 293: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 280: \ - tmp = 0; \ + case 294: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 281: \ - tmp = 0; \ + case 295: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 282: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 283: \ - tmp = 0; \ + case 296: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 284: \ - tmp = 0; \ + case 297: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 285: \ - tmp = 0; \ + case 298: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 286: \ - tmp = 0; \ + case 299: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 287: \ - tmp = 0; \ + case 300: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 288: \ - tmp = 0; \ + case 301: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 289: \ - tmp = 0; \ + case 302: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 290: \ - tmp = 0; \ + case 303: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 291: \ - tmp = 0; \ + case 304: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 292: \ - tmp = 0; \ + case 305: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 293: \ - tmp = 0; \ + case 306: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 294: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 295: \ - tmp = 0; \ + case 307: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 296: \ - tmp = 0; \ + case 308: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 297: \ - tmp = 0; \ + case 309: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 298: \ - tmp = 0; \ + case 310: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 299: \ - tmp = 0; \ + case 311: \ + tmp = 0x0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 300: \ + case 312: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 301: \ + case 313: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr32Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 302: \ + case 314: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 303: \ + case 315: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr32Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 304: \ + case 316: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 305: \ + case 317: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 306: \ + case 318: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 307: \ + case 319: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 308: \ + case 320: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 309: \ + case 321: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 310: \ + case 322: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 311: \ + case 323: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 312: \ + case 324: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 313: \ + case 325: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 314: \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 326: \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 315: \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 327: \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 8); \ - if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 316: \ + case 328: \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 329: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 317: \ + case 330: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 318: \ + case 331: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr32Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 319: \ + case 332: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 320: \ + case 333: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 321: \ - tmp = 0; \ - tmp |= fieldname(insn, 16, 16) << 0; \ - tmp |= fieldname(insn, 36, 4) << 16; \ - if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 334: \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, decodeLenOperand_4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 322: \ + case 335: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 323: \ + case 336: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 324: \ + case 337: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 325: \ + case 338: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 326: \ + case 339: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 327: \ + case 340: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 328: \ + case 341: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 329: \ + case 342: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 330: \ + case 343: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 331: \ + case 344: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 332: \ + case 345: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 333: \ + case 346: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 334: \ + case 347: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 335: \ + case 348: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 336: \ + case 349: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 337: \ + case 350: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 24, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 8); \ - if (decodeU6ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 338: \ + case 351: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 24, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 8); \ - if (decodeU6ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 339: \ + case 352: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 24, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 8); \ - if (decodeU6ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 340: \ + case 353: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 341: \ + case 354: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 342: \ + case 355: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 343: \ + case 356: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 344: \ + case 357: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 345: \ + case 358: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 346: \ + case 359: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 347: \ + case 360: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 348: \ + case 361: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 349: \ + case 362: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 350: \ + case 363: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 351: \ + case 364: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 352: \ + case 365: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 8); \ - if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 353: \ + case 366: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 8); \ - if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 354: \ + case 367: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 355: \ + case 368: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 356: \ + case 369: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 8); \ - if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 357: \ + case 370: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 8); \ - if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 358: \ + case 371: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 359: \ + case 372: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodePC16DBLBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 360: \ + case 373: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 361: \ + case 374: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS16ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 362: \ + case 375: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 363: \ + case 376: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 364: \ + case 377: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 365: \ + case 378: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 366: \ + case 379: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 8); \ - if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 367: \ + case 380: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 8); \ - if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 368: \ + case 381: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 369: \ + case 382: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 370: \ + case 383: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 8); \ - if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 371: \ + case 384: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 8); \ - if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeS8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 372: \ + case 385: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 373: \ + case 386: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU8ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 374: \ + case 387: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 375: \ + case 388: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 376: \ + case 389: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 377: \ + case 390: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 378: \ + case 391: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 379: \ + case 392: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 380: \ + case 393: \ tmp = fieldname(insn, 12, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 381: \ + case 394: \ tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 382: \ + case 395: \ tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 383: \ + case 396: \ tmp = fieldname(insn, 12, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 384: \ + case 397: \ tmp = fieldname(insn, 12, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 385: \ + case 398: \ tmp = fieldname(insn, 12, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 36, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 386: \ + case 399: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 387: \ + case 400: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 8) << 12; \ + tmp |= fieldname(insn, 16, 12) << 0; \ + if (!Check(&S, decodeS20ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 388: \ + case 401: \ tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 24); \ - if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 8); \ + if (!Check(&S, decodeLenOperand_8(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 389: \ + case 402: \ tmp = fieldname(insn, 12, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 24); \ - if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 8); \ + if (!Check(&S, decodeLenOperand_8(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 390: \ + case 403: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 391: \ + case 404: \ tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 392: \ - tmp = 0; \ - tmp |= fieldname(insn, 16, 16) << 0; \ - tmp |= fieldname(insn, 36, 4) << 16; \ - if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 405: \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, decodeLenOperand_4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR32BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + if (!Check(&S, decodeU4ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 393: \ - tmp = 0; \ - tmp |= fieldname(insn, 16, 16) << 0; \ - tmp |= fieldname(insn, 36, 4) << 16; \ - if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 16) << 0; \ - tmp |= fieldname(insn, 32, 4) << 16; \ - if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + case 406: \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 36, 4); \ + if (!Check(&S, decodeLenOperand_4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + if (!Check(&S, decodeU12ImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 32, 4); \ + if (!Check(&S, decodeLenOperand_4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ } \ } #define DecodeInstruction(fname, fieldname, decoder, InsnType) \ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ - InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \ -{ \ - uint64_t Bits = getFeatureBits(feature); \ + InsnType insn, uint64_t Address, const void *Decoder) { \ const uint8_t *Ptr = DecodeTable; \ - uint32_t CurFieldValue = 0, ExpectedValue; \ + uint64_t CurFieldValue = 0; \ DecodeStatus S = MCDisassembler_Success; \ - unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ - InsnType Val, FieldValue, PositiveMask, NegativeMask; \ - bool Pred, Fail; \ - for (;;) { \ + while (true) { \ switch (*Ptr) { \ default: \ return MCDisassembler_Fail; \ case MCD_OPC_ExtractField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ + unsigned Start = *++Ptr; \ + unsigned Len = *++Ptr; \ ++Ptr; \ - CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ + CurFieldValue = fieldname(insn, Start, Len); \ break; \ } \ case MCD_OPC_FilterValue: { \ - Val = (InsnType)decodeULEB128(++Ptr, &Len); \ + /* Decode the field value. */ \ + unsigned Len; \ + uint64_t Val = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ - NumToSkip = *Ptr++; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the filter operation. */ \ if (Val != CurFieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ - FieldValue = fieldname(insn, Start, Len); \ - ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NumToSkip = *Ptr++; \ + unsigned Start = *++Ptr; \ + unsigned Len = *++Ptr; \ + uint64_t FieldValue = fieldname(insn, Start, Len); \ + /* Decode the field value. */ \ + unsigned PtrLen = 0; \ + uint64_t ExpectedValue = decodeULEB128(++Ptr, &PtrLen); \ + Ptr += PtrLen; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* If the actual and expected values don't match, skip. */ \ if (ExpectedValue != FieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckPredicate: { \ - PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ + unsigned Len; \ + /* Decode the Predicate Index value. */ \ + unsigned PIdx = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ - NumToSkip = *Ptr++; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ - Pred = checkDecoderPredicate(PIdx, Bits); \ + NumToSkip |= (*Ptr++) << 16; \ + /* Check the predicate. */ \ + bool Pred = checkDecoderPredicate(MI, PIdx); \ if (!Pred) \ Ptr += NumToSkip; \ - (void)Pred; \ break; \ } \ case MCD_OPC_Decode: { \ - Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ + unsigned Len; \ + /* Decode the Opcode value. */ \ + unsigned Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_clear(MI); \ + MCInst_setOpcode(MI, Opc); \ + bool DecodeComplete; \ + S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \ + return S; \ + } \ + case MCD_OPC_TryDecode: { \ + unsigned Len; \ + /* Decode the Opcode value. */ \ + unsigned Opc = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ - DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ + unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \ Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + unsigned NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the decode operation. */ \ MCInst_setOpcode(MI, Opc); \ - return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ + bool DecodeComplete; \ + S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \ + if (DecodeComplete) { \ + /* Decoding complete. */ \ + return S; \ + } else { \ + /* LLVM uses a MCInst on the stack, but for our use case, */ \ + /* it is enough for now to reset the op counter. */ \ + MCInst_clear(MI); \ + /* If the decoding was incomplete, skip. */ \ + Ptr += NumToSkip; \ + /* Reset decode status. This also drops a SoftFail status that could be */ \ + /* set before the decode attempt. */ \ + S = MCDisassembler_Success; \ + } \ + break; \ } \ case MCD_OPC_SoftFail: { \ - PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ + /* Decode the mask values. */ \ + unsigned Len; \ + uint64_t PositiveMask = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ - NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ + uint64_t NegativeMask = decodeULEB128(Ptr, &Len); \ Ptr += Len; \ - Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + bool Fail = (insn & PositiveMask) != 0 || (~insn & NegativeMask) != 0; \ if (Fail) \ S = MCDisassembler_SoftFail; \ break; \ @@ -10255,8 +11434,9 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ } \ } \ } \ + /* Bogisity detected in disassembler state machine! */ \ } -FieldFromInstruction(fieldFromInstruction, uint64_t) -DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint64_t) -DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint64_t) +FieldFromInstruction(fieldFromInstruction_8, uint64_t) +DecodeToMCInst(decodeToMCInst_8, fieldFromInstruction_8, uint64_t) +DecodeInstruction(decodeInstruction_8, fieldFromInstruction_8, decodeToMCInst_8, uint64_t) diff --git a/arch/SystemZ/SystemZGenInsnNameMaps.inc b/arch/SystemZ/SystemZGenInsnNameMaps.inc deleted file mode 100644 index c4d605ab18..0000000000 --- a/arch/SystemZ/SystemZGenInsnNameMaps.inc +++ /dev/null @@ -1,2348 +0,0 @@ -// This is auto-gen data for Capstone engine (www.capstone-engine.org) -// By Nguyen Anh Quynh - - { SYSZ_INS_A, "a" }, - { SYSZ_INS_ADB, "adb" }, - { SYSZ_INS_ADBR, "adbr" }, - { SYSZ_INS_AEB, "aeb" }, - { SYSZ_INS_AEBR, "aebr" }, - { SYSZ_INS_AFI, "afi" }, - { SYSZ_INS_AG, "ag" }, - { SYSZ_INS_AGF, "agf" }, - { SYSZ_INS_AGFI, "agfi" }, - { SYSZ_INS_AGFR, "agfr" }, - { SYSZ_INS_AGHI, "aghi" }, - { SYSZ_INS_AGHIK, "aghik" }, - { SYSZ_INS_AGR, "agr" }, - { SYSZ_INS_AGRK, "agrk" }, - { SYSZ_INS_AGSI, "agsi" }, - { SYSZ_INS_AH, "ah" }, - { SYSZ_INS_AHI, "ahi" }, - { SYSZ_INS_AHIK, "ahik" }, - { SYSZ_INS_AHY, "ahy" }, - { SYSZ_INS_AIH, "aih" }, - { SYSZ_INS_AL, "al" }, - { SYSZ_INS_ALC, "alc" }, - { SYSZ_INS_ALCG, "alcg" }, - { SYSZ_INS_ALCGR, "alcgr" }, - { SYSZ_INS_ALCR, "alcr" }, - { SYSZ_INS_ALFI, "alfi" }, - { SYSZ_INS_ALG, "alg" }, - { SYSZ_INS_ALGF, "algf" }, - { SYSZ_INS_ALGFI, "algfi" }, - { SYSZ_INS_ALGFR, "algfr" }, - { SYSZ_INS_ALGHSIK, "alghsik" }, - { SYSZ_INS_ALGR, "algr" }, - { SYSZ_INS_ALGRK, "algrk" }, - { SYSZ_INS_ALHSIK, "alhsik" }, - { SYSZ_INS_ALR, "alr" }, - { SYSZ_INS_ALRK, "alrk" }, - { SYSZ_INS_ALY, "aly" }, - { SYSZ_INS_AR, "ar" }, - { SYSZ_INS_ARK, "ark" }, - { SYSZ_INS_ASI, "asi" }, - { SYSZ_INS_AXBR, "axbr" }, - { SYSZ_INS_AY, "ay" }, - { SYSZ_INS_BCR, "bcr" }, - { SYSZ_INS_BRC, "brc" }, - { SYSZ_INS_BRCL, "brcl" }, - { SYSZ_INS_CGIJ, "cgij" }, - { SYSZ_INS_CGRJ, "cgrj" }, - { SYSZ_INS_CIJ, "cij" }, - { SYSZ_INS_CLGIJ, "clgij" }, - { SYSZ_INS_CLGRJ, "clgrj" }, - { SYSZ_INS_CLIJ, "clij" }, - { SYSZ_INS_CLRJ, "clrj" }, - { SYSZ_INS_CRJ, "crj" }, - { SYSZ_INS_BER, "ber" }, - { SYSZ_INS_JE, "je" }, - { SYSZ_INS_JGE, "jge" }, - { SYSZ_INS_LOCE, "loce" }, - { SYSZ_INS_LOCGE, "locge" }, - { SYSZ_INS_LOCGRE, "locgre" }, - { SYSZ_INS_LOCRE, "locre" }, - { SYSZ_INS_STOCE, "stoce" }, - { SYSZ_INS_STOCGE, "stocge" }, - { SYSZ_INS_BHR, "bhr" }, - { SYSZ_INS_BHER, "bher" }, - { SYSZ_INS_JHE, "jhe" }, - { SYSZ_INS_JGHE, "jghe" }, - { SYSZ_INS_LOCHE, "loche" }, - { SYSZ_INS_LOCGHE, "locghe" }, - { SYSZ_INS_LOCGRHE, "locgrhe" }, - { SYSZ_INS_LOCRHE, "locrhe" }, - { SYSZ_INS_STOCHE, "stoche" }, - { SYSZ_INS_STOCGHE, "stocghe" }, - { SYSZ_INS_JH, "jh" }, - { SYSZ_INS_JGH, "jgh" }, - { SYSZ_INS_LOCH, "loch" }, - { SYSZ_INS_LOCGH, "locgh" }, - { SYSZ_INS_LOCGRH, "locgrh" }, - { SYSZ_INS_LOCRH, "locrh" }, - { SYSZ_INS_STOCH, "stoch" }, - { SYSZ_INS_STOCGH, "stocgh" }, - { SYSZ_INS_CGIJNLH, "cgijnlh" }, - { SYSZ_INS_CGRJNLH, "cgrjnlh" }, - { SYSZ_INS_CIJNLH, "cijnlh" }, - { SYSZ_INS_CLGIJNLH, "clgijnlh" }, - { SYSZ_INS_CLGRJNLH, "clgrjnlh" }, - { SYSZ_INS_CLIJNLH, "clijnlh" }, - { SYSZ_INS_CLRJNLH, "clrjnlh" }, - { SYSZ_INS_CRJNLH, "crjnlh" }, - { SYSZ_INS_CGIJE, "cgije" }, - { SYSZ_INS_CGRJE, "cgrje" }, - { SYSZ_INS_CIJE, "cije" }, - { SYSZ_INS_CLGIJE, "clgije" }, - { SYSZ_INS_CLGRJE, "clgrje" }, - { SYSZ_INS_CLIJE, "clije" }, - { SYSZ_INS_CLRJE, "clrje" }, - { SYSZ_INS_CRJE, "crje" }, - { SYSZ_INS_CGIJNLE, "cgijnle" }, - { SYSZ_INS_CGRJNLE, "cgrjnle" }, - { SYSZ_INS_CIJNLE, "cijnle" }, - { SYSZ_INS_CLGIJNLE, "clgijnle" }, - { SYSZ_INS_CLGRJNLE, "clgrjnle" }, - { SYSZ_INS_CLIJNLE, "clijnle" }, - { SYSZ_INS_CLRJNLE, "clrjnle" }, - { SYSZ_INS_CRJNLE, "crjnle" }, - { SYSZ_INS_CGIJH, "cgijh" }, - { SYSZ_INS_CGRJH, "cgrjh" }, - { SYSZ_INS_CIJH, "cijh" }, - { SYSZ_INS_CLGIJH, "clgijh" }, - { SYSZ_INS_CLGRJH, "clgrjh" }, - { SYSZ_INS_CLIJH, "clijh" }, - { SYSZ_INS_CLRJH, "clrjh" }, - { SYSZ_INS_CRJH, "crjh" }, - { SYSZ_INS_CGIJNL, "cgijnl" }, - { SYSZ_INS_CGRJNL, "cgrjnl" }, - { SYSZ_INS_CIJNL, "cijnl" }, - { SYSZ_INS_CLGIJNL, "clgijnl" }, - { SYSZ_INS_CLGRJNL, "clgrjnl" }, - { SYSZ_INS_CLIJNL, "clijnl" }, - { SYSZ_INS_CLRJNL, "clrjnl" }, - { SYSZ_INS_CRJNL, "crjnl" }, - { SYSZ_INS_CGIJHE, "cgijhe" }, - { SYSZ_INS_CGRJHE, "cgrjhe" }, - { SYSZ_INS_CIJHE, "cijhe" }, - { SYSZ_INS_CLGIJHE, "clgijhe" }, - { SYSZ_INS_CLGRJHE, "clgrjhe" }, - { SYSZ_INS_CLIJHE, "clijhe" }, - { SYSZ_INS_CLRJHE, "clrjhe" }, - { SYSZ_INS_CRJHE, "crjhe" }, - { SYSZ_INS_CGIJNHE, "cgijnhe" }, - { SYSZ_INS_CGRJNHE, "cgrjnhe" }, - { SYSZ_INS_CIJNHE, "cijnhe" }, - { SYSZ_INS_CLGIJNHE, "clgijnhe" }, - { SYSZ_INS_CLGRJNHE, "clgrjnhe" }, - { SYSZ_INS_CLIJNHE, "clijnhe" }, - { SYSZ_INS_CLRJNHE, "clrjnhe" }, - { SYSZ_INS_CRJNHE, "crjnhe" }, - { SYSZ_INS_CGIJL, "cgijl" }, - { SYSZ_INS_CGRJL, "cgrjl" }, - { SYSZ_INS_CIJL, "cijl" }, - { SYSZ_INS_CLGIJL, "clgijl" }, - { SYSZ_INS_CLGRJL, "clgrjl" }, - { SYSZ_INS_CLIJL, "clijl" }, - { SYSZ_INS_CLRJL, "clrjl" }, - { SYSZ_INS_CRJL, "crjl" }, - { SYSZ_INS_CGIJNH, "cgijnh" }, - { SYSZ_INS_CGRJNH, "cgrjnh" }, - { SYSZ_INS_CIJNH, "cijnh" }, - { SYSZ_INS_CLGIJNH, "clgijnh" }, - { SYSZ_INS_CLGRJNH, "clgrjnh" }, - { SYSZ_INS_CLIJNH, "clijnh" }, - { SYSZ_INS_CLRJNH, "clrjnh" }, - { SYSZ_INS_CRJNH, "crjnh" }, - { SYSZ_INS_CGIJLE, "cgijle" }, - { SYSZ_INS_CGRJLE, "cgrjle" }, - { SYSZ_INS_CIJLE, "cijle" }, - { SYSZ_INS_CLGIJLE, "clgijle" }, - { SYSZ_INS_CLGRJLE, "clgrjle" }, - { SYSZ_INS_CLIJLE, "clijle" }, - { SYSZ_INS_CLRJLE, "clrjle" }, - { SYSZ_INS_CRJLE, "crjle" }, - { SYSZ_INS_CGIJNE, "cgijne" }, - { SYSZ_INS_CGRJNE, "cgrjne" }, - { SYSZ_INS_CIJNE, "cijne" }, - { SYSZ_INS_CLGIJNE, "clgijne" }, - { SYSZ_INS_CLGRJNE, "clgrjne" }, - { SYSZ_INS_CLIJNE, "clijne" }, - { SYSZ_INS_CLRJNE, "clrjne" }, - { SYSZ_INS_CRJNE, "crjne" }, - { SYSZ_INS_CGIJLH, "cgijlh" }, - { SYSZ_INS_CGRJLH, "cgrjlh" }, - { SYSZ_INS_CIJLH, "cijlh" }, - { SYSZ_INS_CLGIJLH, "clgijlh" }, - { SYSZ_INS_CLGRJLH, "clgrjlh" }, - { SYSZ_INS_CLIJLH, "clijlh" }, - { SYSZ_INS_CLRJLH, "clrjlh" }, - { SYSZ_INS_CRJLH, "crjlh" }, - { SYSZ_INS_BLR, "blr" }, - { SYSZ_INS_BLER, "bler" }, - { SYSZ_INS_JLE, "jle" }, - { SYSZ_INS_JGLE, "jgle" }, - { SYSZ_INS_LOCLE, "locle" }, - { SYSZ_INS_LOCGLE, "locgle" }, - { SYSZ_INS_LOCGRLE, "locgrle" }, - { SYSZ_INS_LOCRLE, "locrle" }, - { SYSZ_INS_STOCLE, "stocle" }, - { SYSZ_INS_STOCGLE, "stocgle" }, - { SYSZ_INS_BLHR, "blhr" }, - { SYSZ_INS_JLH, "jlh" }, - { SYSZ_INS_JGLH, "jglh" }, - { SYSZ_INS_LOCLH, "loclh" }, - { SYSZ_INS_LOCGLH, "locglh" }, - { SYSZ_INS_LOCGRLH, "locgrlh" }, - { SYSZ_INS_LOCRLH, "locrlh" }, - { SYSZ_INS_STOCLH, "stoclh" }, - { SYSZ_INS_STOCGLH, "stocglh" }, - { SYSZ_INS_JL, "jl" }, - { SYSZ_INS_JGL, "jgl" }, - { SYSZ_INS_LOCL, "locl" }, - { SYSZ_INS_LOCGL, "locgl" }, - { SYSZ_INS_LOCGRL, "locgrl" }, - { SYSZ_INS_LOCRL, "locrl" }, - { SYSZ_INS_LOC, "loc" }, - { SYSZ_INS_LOCG, "locg" }, - { SYSZ_INS_LOCGR, "locgr" }, - { SYSZ_INS_LOCR, "locr" }, - { SYSZ_INS_STOCL, "stocl" }, - { SYSZ_INS_STOCGL, "stocgl" }, - { SYSZ_INS_BNER, "bner" }, - { SYSZ_INS_JNE, "jne" }, - { SYSZ_INS_JGNE, "jgne" }, - { SYSZ_INS_LOCNE, "locne" }, - { SYSZ_INS_LOCGNE, "locgne" }, - { SYSZ_INS_LOCGRNE, "locgrne" }, - { SYSZ_INS_LOCRNE, "locrne" }, - { SYSZ_INS_STOCNE, "stocne" }, - { SYSZ_INS_STOCGNE, "stocgne" }, - { SYSZ_INS_BNHR, "bnhr" }, - { SYSZ_INS_BNHER, "bnher" }, - { SYSZ_INS_JNHE, "jnhe" }, - { SYSZ_INS_JGNHE, "jgnhe" }, - { SYSZ_INS_LOCNHE, "locnhe" }, - { SYSZ_INS_LOCGNHE, "locgnhe" }, - { SYSZ_INS_LOCGRNHE, "locgrnhe" }, - { SYSZ_INS_LOCRNHE, "locrnhe" }, - { SYSZ_INS_STOCNHE, "stocnhe" }, - { SYSZ_INS_STOCGNHE, "stocgnhe" }, - { SYSZ_INS_JNH, "jnh" }, - { SYSZ_INS_JGNH, "jgnh" }, - { SYSZ_INS_LOCNH, "locnh" }, - { SYSZ_INS_LOCGNH, "locgnh" }, - { SYSZ_INS_LOCGRNH, "locgrnh" }, - { SYSZ_INS_LOCRNH, "locrnh" }, - { SYSZ_INS_STOCNH, "stocnh" }, - { SYSZ_INS_STOCGNH, "stocgnh" }, - { SYSZ_INS_BNLR, "bnlr" }, - { SYSZ_INS_BNLER, "bnler" }, - { SYSZ_INS_JNLE, "jnle" }, - { SYSZ_INS_JGNLE, "jgnle" }, - { SYSZ_INS_LOCNLE, "locnle" }, - { SYSZ_INS_LOCGNLE, "locgnle" }, - { SYSZ_INS_LOCGRNLE, "locgrnle" }, - { SYSZ_INS_LOCRNLE, "locrnle" }, - { SYSZ_INS_STOCNLE, "stocnle" }, - { SYSZ_INS_STOCGNLE, "stocgnle" }, - { SYSZ_INS_BNLHR, "bnlhr" }, - { SYSZ_INS_JNLH, "jnlh" }, - { SYSZ_INS_JGNLH, "jgnlh" }, - { SYSZ_INS_LOCNLH, "locnlh" }, - { SYSZ_INS_LOCGNLH, "locgnlh" }, - { SYSZ_INS_LOCGRNLH, "locgrnlh" }, - { SYSZ_INS_LOCRNLH, "locrnlh" }, - { SYSZ_INS_STOCNLH, "stocnlh" }, - { SYSZ_INS_STOCGNLH, "stocgnlh" }, - { SYSZ_INS_JNL, "jnl" }, - { SYSZ_INS_JGNL, "jgnl" }, - { SYSZ_INS_LOCNL, "locnl" }, - { SYSZ_INS_LOCGNL, "locgnl" }, - { SYSZ_INS_LOCGRNL, "locgrnl" }, - { SYSZ_INS_LOCRNL, "locrnl" }, - { SYSZ_INS_STOCNL, "stocnl" }, - { SYSZ_INS_STOCGNL, "stocgnl" }, - { SYSZ_INS_BNOR, "bnor" }, - { SYSZ_INS_JNO, "jno" }, - { SYSZ_INS_JGNO, "jgno" }, - { SYSZ_INS_LOCNO, "locno" }, - { SYSZ_INS_LOCGNO, "locgno" }, - { SYSZ_INS_LOCGRNO, "locgrno" }, - { SYSZ_INS_LOCRNO, "locrno" }, - { SYSZ_INS_STOCNO, "stocno" }, - { SYSZ_INS_STOCGNO, "stocgno" }, - { SYSZ_INS_BOR, "bor" }, - { SYSZ_INS_JO, "jo" }, - { SYSZ_INS_JGO, "jgo" }, - { SYSZ_INS_LOCO, "loco" }, - { SYSZ_INS_LOCGO, "locgo" }, - { SYSZ_INS_LOCGRO, "locgro" }, - { SYSZ_INS_LOCRO, "locro" }, - { SYSZ_INS_STOCO, "stoco" }, - { SYSZ_INS_STOCGO, "stocgo" }, - { SYSZ_INS_STOC, "stoc" }, - { SYSZ_INS_STOCG, "stocg" }, - { SYSZ_INS_BASR, "basr" }, - { SYSZ_INS_BR, "br" }, - { SYSZ_INS_BRAS, "bras" }, - { SYSZ_INS_BRASL, "brasl" }, - { SYSZ_INS_J, "j" }, - { SYSZ_INS_JG, "jg" }, - { SYSZ_INS_BRCT, "brct" }, - { SYSZ_INS_BRCTG, "brctg" }, - { SYSZ_INS_C, "c" }, - { SYSZ_INS_CDB, "cdb" }, - { SYSZ_INS_CDBR, "cdbr" }, - { SYSZ_INS_CDFBR, "cdfbr" }, - { SYSZ_INS_CDGBR, "cdgbr" }, - { SYSZ_INS_CDLFBR, "cdlfbr" }, - { SYSZ_INS_CDLGBR, "cdlgbr" }, - { SYSZ_INS_CEB, "ceb" }, - { SYSZ_INS_CEBR, "cebr" }, - { SYSZ_INS_CEFBR, "cefbr" }, - { SYSZ_INS_CEGBR, "cegbr" }, - { SYSZ_INS_CELFBR, "celfbr" }, - { SYSZ_INS_CELGBR, "celgbr" }, - { SYSZ_INS_CFDBR, "cfdbr" }, - { SYSZ_INS_CFEBR, "cfebr" }, - { SYSZ_INS_CFI, "cfi" }, - { SYSZ_INS_CFXBR, "cfxbr" }, - { SYSZ_INS_CG, "cg" }, - { SYSZ_INS_CGDBR, "cgdbr" }, - { SYSZ_INS_CGEBR, "cgebr" }, - { SYSZ_INS_CGF, "cgf" }, - { SYSZ_INS_CGFI, "cgfi" }, - { SYSZ_INS_CGFR, "cgfr" }, - { SYSZ_INS_CGFRL, "cgfrl" }, - { SYSZ_INS_CGH, "cgh" }, - { SYSZ_INS_CGHI, "cghi" }, - { SYSZ_INS_CGHRL, "cghrl" }, - { SYSZ_INS_CGHSI, "cghsi" }, - { SYSZ_INS_CGR, "cgr" }, - { SYSZ_INS_CGRL, "cgrl" }, - { SYSZ_INS_CGXBR, "cgxbr" }, - { SYSZ_INS_CH, "ch" }, - { SYSZ_INS_CHF, "chf" }, - { SYSZ_INS_CHHSI, "chhsi" }, - { SYSZ_INS_CHI, "chi" }, - { SYSZ_INS_CHRL, "chrl" }, - { SYSZ_INS_CHSI, "chsi" }, - { SYSZ_INS_CHY, "chy" }, - { SYSZ_INS_CIH, "cih" }, - { SYSZ_INS_CL, "cl" }, - { SYSZ_INS_CLC, "clc" }, - { SYSZ_INS_CLFDBR, "clfdbr" }, - { SYSZ_INS_CLFEBR, "clfebr" }, - { SYSZ_INS_CLFHSI, "clfhsi" }, - { SYSZ_INS_CLFI, "clfi" }, - { SYSZ_INS_CLFXBR, "clfxbr" }, - { SYSZ_INS_CLG, "clg" }, - { SYSZ_INS_CLGDBR, "clgdbr" }, - { SYSZ_INS_CLGEBR, "clgebr" }, - { SYSZ_INS_CLGF, "clgf" }, - { SYSZ_INS_CLGFI, "clgfi" }, - { SYSZ_INS_CLGFR, "clgfr" }, - { SYSZ_INS_CLGFRL, "clgfrl" }, - { SYSZ_INS_CLGHRL, "clghrl" }, - { SYSZ_INS_CLGHSI, "clghsi" }, - { SYSZ_INS_CLGR, "clgr" }, - { SYSZ_INS_CLGRL, "clgrl" }, - { SYSZ_INS_CLGXBR, "clgxbr" }, - { SYSZ_INS_CLHF, "clhf" }, - { SYSZ_INS_CLHHSI, "clhhsi" }, - { SYSZ_INS_CLHRL, "clhrl" }, - { SYSZ_INS_CLI, "cli" }, - { SYSZ_INS_CLIH, "clih" }, - { SYSZ_INS_CLIY, "cliy" }, - { SYSZ_INS_CLR, "clr" }, - { SYSZ_INS_CLRL, "clrl" }, - { SYSZ_INS_CLST, "clst" }, - { SYSZ_INS_CLY, "cly" }, - { SYSZ_INS_CPSDR, "cpsdr" }, - { SYSZ_INS_CR, "cr" }, - { SYSZ_INS_CRL, "crl" }, - { SYSZ_INS_CS, "cs" }, - { SYSZ_INS_CSG, "csg" }, - { SYSZ_INS_CSY, "csy" }, - { SYSZ_INS_CXBR, "cxbr" }, - { SYSZ_INS_CXFBR, "cxfbr" }, - { SYSZ_INS_CXGBR, "cxgbr" }, - { SYSZ_INS_CXLFBR, "cxlfbr" }, - { SYSZ_INS_CXLGBR, "cxlgbr" }, - { SYSZ_INS_CY, "cy" }, - { SYSZ_INS_DDB, "ddb" }, - { SYSZ_INS_DDBR, "ddbr" }, - { SYSZ_INS_DEB, "deb" }, - { SYSZ_INS_DEBR, "debr" }, - { SYSZ_INS_DL, "dl" }, - { SYSZ_INS_DLG, "dlg" }, - { SYSZ_INS_DLGR, "dlgr" }, - { SYSZ_INS_DLR, "dlr" }, - { SYSZ_INS_DSG, "dsg" }, - { SYSZ_INS_DSGF, "dsgf" }, - { SYSZ_INS_DSGFR, "dsgfr" }, - { SYSZ_INS_DSGR, "dsgr" }, - { SYSZ_INS_DXBR, "dxbr" }, - { SYSZ_INS_EAR, "ear" }, - { SYSZ_INS_FIDBR, "fidbr" }, - { SYSZ_INS_FIDBRA, "fidbra" }, - { SYSZ_INS_FIEBR, "fiebr" }, - { SYSZ_INS_FIEBRA, "fiebra" }, - { SYSZ_INS_FIXBR, "fixbr" }, - { SYSZ_INS_FIXBRA, "fixbra" }, - { SYSZ_INS_FLOGR, "flogr" }, - { SYSZ_INS_IC, "ic" }, - { SYSZ_INS_ICY, "icy" }, - { SYSZ_INS_IIHF, "iihf" }, - { SYSZ_INS_IIHH, "iihh" }, - { SYSZ_INS_IIHL, "iihl" }, - { SYSZ_INS_IILF, "iilf" }, - { SYSZ_INS_IILH, "iilh" }, - { SYSZ_INS_IILL, "iill" }, - { SYSZ_INS_IPM, "ipm" }, - { SYSZ_INS_L, "l" }, - { SYSZ_INS_LA, "la" }, - { SYSZ_INS_LAA, "laa" }, - { SYSZ_INS_LAAG, "laag" }, - { SYSZ_INS_LAAL, "laal" }, - { SYSZ_INS_LAALG, "laalg" }, - { SYSZ_INS_LAN, "lan" }, - { SYSZ_INS_LANG, "lang" }, - { SYSZ_INS_LAO, "lao" }, - { SYSZ_INS_LAOG, "laog" }, - { SYSZ_INS_LARL, "larl" }, - { SYSZ_INS_LAX, "lax" }, - { SYSZ_INS_LAXG, "laxg" }, - { SYSZ_INS_LAY, "lay" }, - { SYSZ_INS_LB, "lb" }, - { SYSZ_INS_LBH, "lbh" }, - { SYSZ_INS_LBR, "lbr" }, - { SYSZ_INS_LCDBR, "lcdbr" }, - { SYSZ_INS_LCEBR, "lcebr" }, - { SYSZ_INS_LCGFR, "lcgfr" }, - { SYSZ_INS_LCGR, "lcgr" }, - { SYSZ_INS_LCR, "lcr" }, - { SYSZ_INS_LCXBR, "lcxbr" }, - { SYSZ_INS_LD, "ld" }, - { SYSZ_INS_LDEB, "ldeb" }, - { SYSZ_INS_LDEBR, "ldebr" }, - { SYSZ_INS_LDGR, "ldgr" }, - { SYSZ_INS_LDR, "ldr" }, - { SYSZ_INS_LDXBR, "ldxbr" }, - { SYSZ_INS_LDXBRA, "ldxbra" }, - { SYSZ_INS_LDY, "ldy" }, - { SYSZ_INS_LE, "le" }, - { SYSZ_INS_LEDBR, "ledbr" }, - { SYSZ_INS_LEDBRA, "ledbra" }, - { SYSZ_INS_LER, "ler" }, - { SYSZ_INS_LEXBR, "lexbr" }, - { SYSZ_INS_LEXBRA, "lexbra" }, - { SYSZ_INS_LEY, "ley" }, - { SYSZ_INS_LFH, "lfh" }, - { SYSZ_INS_LG, "lg" }, - { SYSZ_INS_LGB, "lgb" }, - { SYSZ_INS_LGBR, "lgbr" }, - { SYSZ_INS_LGDR, "lgdr" }, - { SYSZ_INS_LGF, "lgf" }, - { SYSZ_INS_LGFI, "lgfi" }, - { SYSZ_INS_LGFR, "lgfr" }, - { SYSZ_INS_LGFRL, "lgfrl" }, - { SYSZ_INS_LGH, "lgh" }, - { SYSZ_INS_LGHI, "lghi" }, - { SYSZ_INS_LGHR, "lghr" }, - { SYSZ_INS_LGHRL, "lghrl" }, - { SYSZ_INS_LGR, "lgr" }, - { SYSZ_INS_LGRL, "lgrl" }, - { SYSZ_INS_LH, "lh" }, - { SYSZ_INS_LHH, "lhh" }, - { SYSZ_INS_LHI, "lhi" }, - { SYSZ_INS_LHR, "lhr" }, - { SYSZ_INS_LHRL, "lhrl" }, - { SYSZ_INS_LHY, "lhy" }, - { SYSZ_INS_LLC, "llc" }, - { SYSZ_INS_LLCH, "llch" }, - { SYSZ_INS_LLCR, "llcr" }, - { SYSZ_INS_LLGC, "llgc" }, - { SYSZ_INS_LLGCR, "llgcr" }, - { SYSZ_INS_LLGF, "llgf" }, - { SYSZ_INS_LLGFR, "llgfr" }, - { SYSZ_INS_LLGFRL, "llgfrl" }, - { SYSZ_INS_LLGH, "llgh" }, - { SYSZ_INS_LLGHR, "llghr" }, - { SYSZ_INS_LLGHRL, "llghrl" }, - { SYSZ_INS_LLH, "llh" }, - { SYSZ_INS_LLHH, "llhh" }, - { SYSZ_INS_LLHR, "llhr" }, - { SYSZ_INS_LLHRL, "llhrl" }, - { SYSZ_INS_LLIHF, "llihf" }, - { SYSZ_INS_LLIHH, "llihh" }, - { SYSZ_INS_LLIHL, "llihl" }, - { SYSZ_INS_LLILF, "llilf" }, - { SYSZ_INS_LLILH, "llilh" }, - { SYSZ_INS_LLILL, "llill" }, - { SYSZ_INS_LMG, "lmg" }, - { SYSZ_INS_LNDBR, "lndbr" }, - { SYSZ_INS_LNEBR, "lnebr" }, - { SYSZ_INS_LNGFR, "lngfr" }, - { SYSZ_INS_LNGR, "lngr" }, - { SYSZ_INS_LNR, "lnr" }, - { SYSZ_INS_LNXBR, "lnxbr" }, - { SYSZ_INS_LPDBR, "lpdbr" }, - { SYSZ_INS_LPEBR, "lpebr" }, - { SYSZ_INS_LPGFR, "lpgfr" }, - { SYSZ_INS_LPGR, "lpgr" }, - { SYSZ_INS_LPR, "lpr" }, - { SYSZ_INS_LPXBR, "lpxbr" }, - { SYSZ_INS_LR, "lr" }, - { SYSZ_INS_LRL, "lrl" }, - { SYSZ_INS_LRV, "lrv" }, - { SYSZ_INS_LRVG, "lrvg" }, - { SYSZ_INS_LRVGR, "lrvgr" }, - { SYSZ_INS_LRVR, "lrvr" }, - { SYSZ_INS_LT, "lt" }, - { SYSZ_INS_LTDBR, "ltdbr" }, - { SYSZ_INS_LTEBR, "ltebr" }, - { SYSZ_INS_LTG, "ltg" }, - { SYSZ_INS_LTGF, "ltgf" }, - { SYSZ_INS_LTGFR, "ltgfr" }, - { SYSZ_INS_LTGR, "ltgr" }, - { SYSZ_INS_LTR, "ltr" }, - { SYSZ_INS_LTXBR, "ltxbr" }, - { SYSZ_INS_LXDB, "lxdb" }, - { SYSZ_INS_LXDBR, "lxdbr" }, - { SYSZ_INS_LXEB, "lxeb" }, - { SYSZ_INS_LXEBR, "lxebr" }, - { SYSZ_INS_LXR, "lxr" }, - { SYSZ_INS_LY, "ly" }, - { SYSZ_INS_LZDR, "lzdr" }, - { SYSZ_INS_LZER, "lzer" }, - { SYSZ_INS_LZXR, "lzxr" }, - { SYSZ_INS_MADB, "madb" }, - { SYSZ_INS_MADBR, "madbr" }, - { SYSZ_INS_MAEB, "maeb" }, - { SYSZ_INS_MAEBR, "maebr" }, - { SYSZ_INS_MDB, "mdb" }, - { SYSZ_INS_MDBR, "mdbr" }, - { SYSZ_INS_MDEB, "mdeb" }, - { SYSZ_INS_MDEBR, "mdebr" }, - { SYSZ_INS_MEEB, "meeb" }, - { SYSZ_INS_MEEBR, "meebr" }, - { SYSZ_INS_MGHI, "mghi" }, - { SYSZ_INS_MH, "mh" }, - { SYSZ_INS_MHI, "mhi" }, - { SYSZ_INS_MHY, "mhy" }, - { SYSZ_INS_MLG, "mlg" }, - { SYSZ_INS_MLGR, "mlgr" }, - { SYSZ_INS_MS, "ms" }, - { SYSZ_INS_MSDB, "msdb" }, - { SYSZ_INS_MSDBR, "msdbr" }, - { SYSZ_INS_MSEB, "mseb" }, - { SYSZ_INS_MSEBR, "msebr" }, - { SYSZ_INS_MSFI, "msfi" }, - { SYSZ_INS_MSG, "msg" }, - { SYSZ_INS_MSGF, "msgf" }, - { SYSZ_INS_MSGFI, "msgfi" }, - { SYSZ_INS_MSGFR, "msgfr" }, - { SYSZ_INS_MSGR, "msgr" }, - { SYSZ_INS_MSR, "msr" }, - { SYSZ_INS_MSY, "msy" }, - { SYSZ_INS_MVC, "mvc" }, - { SYSZ_INS_MVGHI, "mvghi" }, - { SYSZ_INS_MVHHI, "mvhhi" }, - { SYSZ_INS_MVHI, "mvhi" }, - { SYSZ_INS_MVI, "mvi" }, - { SYSZ_INS_MVIY, "mviy" }, - { SYSZ_INS_MVST, "mvst" }, - { SYSZ_INS_MXBR, "mxbr" }, - { SYSZ_INS_MXDB, "mxdb" }, - { SYSZ_INS_MXDBR, "mxdbr" }, - { SYSZ_INS_N, "n" }, - { SYSZ_INS_NC, "nc" }, - { SYSZ_INS_NG, "ng" }, - { SYSZ_INS_NGR, "ngr" }, - { SYSZ_INS_NGRK, "ngrk" }, - { SYSZ_INS_NI, "ni" }, - { SYSZ_INS_NIHF, "nihf" }, - { SYSZ_INS_NIHH, "nihh" }, - { SYSZ_INS_NIHL, "nihl" }, - { SYSZ_INS_NILF, "nilf" }, - { SYSZ_INS_NILH, "nilh" }, - { SYSZ_INS_NILL, "nill" }, - { SYSZ_INS_NIY, "niy" }, - { SYSZ_INS_NR, "nr" }, - { SYSZ_INS_NRK, "nrk" }, - { SYSZ_INS_NY, "ny" }, - { SYSZ_INS_O, "o" }, - { SYSZ_INS_OC, "oc" }, - { SYSZ_INS_OG, "og" }, - { SYSZ_INS_OGR, "ogr" }, - { SYSZ_INS_OGRK, "ogrk" }, - { SYSZ_INS_OI, "oi" }, - { SYSZ_INS_OIHF, "oihf" }, - { SYSZ_INS_OIHH, "oihh" }, - { SYSZ_INS_OIHL, "oihl" }, - { SYSZ_INS_OILF, "oilf" }, - { SYSZ_INS_OILH, "oilh" }, - { SYSZ_INS_OILL, "oill" }, - { SYSZ_INS_OIY, "oiy" }, - { SYSZ_INS_OR, "or" }, - { SYSZ_INS_ORK, "ork" }, - { SYSZ_INS_OY, "oy" }, - { SYSZ_INS_PFD, "pfd" }, - { SYSZ_INS_PFDRL, "pfdrl" }, - { SYSZ_INS_RISBG, "risbg" }, - { SYSZ_INS_RISBHG, "risbhg" }, - { SYSZ_INS_RISBLG, "risblg" }, - { SYSZ_INS_RLL, "rll" }, - { SYSZ_INS_RLLG, "rllg" }, - { SYSZ_INS_RNSBG, "rnsbg" }, - { SYSZ_INS_ROSBG, "rosbg" }, - { SYSZ_INS_RXSBG, "rxsbg" }, - { SYSZ_INS_S, "s" }, - { SYSZ_INS_SDB, "sdb" }, - { SYSZ_INS_SDBR, "sdbr" }, - { SYSZ_INS_SEB, "seb" }, - { SYSZ_INS_SEBR, "sebr" }, - { SYSZ_INS_SG, "sg" }, - { SYSZ_INS_SGF, "sgf" }, - { SYSZ_INS_SGFR, "sgfr" }, - { SYSZ_INS_SGR, "sgr" }, - { SYSZ_INS_SGRK, "sgrk" }, - { SYSZ_INS_SH, "sh" }, - { SYSZ_INS_SHY, "shy" }, - { SYSZ_INS_SL, "sl" }, - { SYSZ_INS_SLB, "slb" }, - { SYSZ_INS_SLBG, "slbg" }, - { SYSZ_INS_SLBR, "slbr" }, - { SYSZ_INS_SLFI, "slfi" }, - { SYSZ_INS_SLG, "slg" }, - { SYSZ_INS_SLBGR, "slbgr" }, - { SYSZ_INS_SLGF, "slgf" }, - { SYSZ_INS_SLGFI, "slgfi" }, - { SYSZ_INS_SLGFR, "slgfr" }, - { SYSZ_INS_SLGR, "slgr" }, - { SYSZ_INS_SLGRK, "slgrk" }, - { SYSZ_INS_SLL, "sll" }, - { SYSZ_INS_SLLG, "sllg" }, - { SYSZ_INS_SLLK, "sllk" }, - { SYSZ_INS_SLR, "slr" }, - { SYSZ_INS_SLRK, "slrk" }, - { SYSZ_INS_SLY, "sly" }, - { SYSZ_INS_SQDB, "sqdb" }, - { SYSZ_INS_SQDBR, "sqdbr" }, - { SYSZ_INS_SQEB, "sqeb" }, - { SYSZ_INS_SQEBR, "sqebr" }, - { SYSZ_INS_SQXBR, "sqxbr" }, - { SYSZ_INS_SR, "sr" }, - { SYSZ_INS_SRA, "sra" }, - { SYSZ_INS_SRAG, "srag" }, - { SYSZ_INS_SRAK, "srak" }, - { SYSZ_INS_SRK, "srk" }, - { SYSZ_INS_SRL, "srl" }, - { SYSZ_INS_SRLG, "srlg" }, - { SYSZ_INS_SRLK, "srlk" }, - { SYSZ_INS_SRST, "srst" }, - { SYSZ_INS_ST, "st" }, - { SYSZ_INS_STC, "stc" }, - { SYSZ_INS_STCH, "stch" }, - { SYSZ_INS_STCY, "stcy" }, - { SYSZ_INS_STD, "std" }, - { SYSZ_INS_STDY, "stdy" }, - { SYSZ_INS_STE, "ste" }, - { SYSZ_INS_STEY, "stey" }, - { SYSZ_INS_STFH, "stfh" }, - { SYSZ_INS_STG, "stg" }, - { SYSZ_INS_STGRL, "stgrl" }, - { SYSZ_INS_STH, "sth" }, - { SYSZ_INS_STHH, "sthh" }, - { SYSZ_INS_STHRL, "sthrl" }, - { SYSZ_INS_STHY, "sthy" }, - { SYSZ_INS_STMG, "stmg" }, - { SYSZ_INS_STRL, "strl" }, - { SYSZ_INS_STRV, "strv" }, - { SYSZ_INS_STRVG, "strvg" }, - { SYSZ_INS_STY, "sty" }, - { SYSZ_INS_SXBR, "sxbr" }, - { SYSZ_INS_SY, "sy" }, - { SYSZ_INS_TM, "tm" }, - { SYSZ_INS_TMHH, "tmhh" }, - { SYSZ_INS_TMHL, "tmhl" }, - { SYSZ_INS_TMLH, "tmlh" }, - { SYSZ_INS_TMLL, "tmll" }, - { SYSZ_INS_TMY, "tmy" }, - { SYSZ_INS_X, "x" }, - { SYSZ_INS_XC, "xc" }, - { SYSZ_INS_XG, "xg" }, - { SYSZ_INS_XGR, "xgr" }, - { SYSZ_INS_XGRK, "xgrk" }, - { SYSZ_INS_XI, "xi" }, - { SYSZ_INS_XIHF, "xihf" }, - { SYSZ_INS_XILF, "xilf" }, - { SYSZ_INS_XIY, "xiy" }, - { SYSZ_INS_XR, "xr" }, - { SYSZ_INS_XRK, "xrk" }, - { SYSZ_INS_XY, "xy" }, - { SYSZ_INS_AD, "ad" }, - { SYSZ_INS_ADR, "adr" }, - { SYSZ_INS_ADTR, "adtr" }, - { SYSZ_INS_ADTRA, "adtra" }, - { SYSZ_INS_AE, "ae" }, - { SYSZ_INS_AER, "aer" }, - { SYSZ_INS_AGH, "agh" }, - { SYSZ_INS_AHHHR, "ahhhr" }, - { SYSZ_INS_AHHLR, "ahhlr" }, - { SYSZ_INS_ALGSI, "algsi" }, - { SYSZ_INS_ALHHHR, "alhhhr" }, - { SYSZ_INS_ALHHLR, "alhhlr" }, - { SYSZ_INS_ALSI, "alsi" }, - { SYSZ_INS_ALSIH, "alsih" }, - { SYSZ_INS_ALSIHN, "alsihn" }, - { SYSZ_INS_AP, "ap" }, - { SYSZ_INS_AU, "au" }, - { SYSZ_INS_AUR, "aur" }, - { SYSZ_INS_AW, "aw" }, - { SYSZ_INS_AWR, "awr" }, - { SYSZ_INS_AXR, "axr" }, - { SYSZ_INS_AXTR, "axtr" }, - { SYSZ_INS_AXTRA, "axtra" }, - { SYSZ_INS_B, "b" }, - { SYSZ_INS_BAKR, "bakr" }, - { SYSZ_INS_BAL, "bal" }, - { SYSZ_INS_BALR, "balr" }, - { SYSZ_INS_BAS, "bas" }, - { SYSZ_INS_BASSM, "bassm" }, - { SYSZ_INS_BC, "bc" }, - { SYSZ_INS_BCT, "bct" }, - { SYSZ_INS_BCTG, "bctg" }, - { SYSZ_INS_BCTGR, "bctgr" }, - { SYSZ_INS_BCTR, "bctr" }, - { SYSZ_INS_BE, "be" }, - { SYSZ_INS_BH, "bh" }, - { SYSZ_INS_BHE, "bhe" }, - { SYSZ_INS_BI, "bi" }, - { SYSZ_INS_BIC, "bic" }, - { SYSZ_INS_BIE, "bie" }, - { SYSZ_INS_BIH, "bih" }, - { SYSZ_INS_BIHE, "bihe" }, - { SYSZ_INS_BIL, "bil" }, - { SYSZ_INS_BILE, "bile" }, - { SYSZ_INS_BILH, "bilh" }, - { SYSZ_INS_BIM, "bim" }, - { SYSZ_INS_BINE, "bine" }, - { SYSZ_INS_BINH, "binh" }, - { SYSZ_INS_BINHE, "binhe" }, - { SYSZ_INS_BINL, "binl" }, - { SYSZ_INS_BINLE, "binle" }, - { SYSZ_INS_BINLH, "binlh" }, - { SYSZ_INS_BINM, "binm" }, - { SYSZ_INS_BINO, "bino" }, - { SYSZ_INS_BINP, "binp" }, - { SYSZ_INS_BINZ, "binz" }, - { SYSZ_INS_BIO, "bio" }, - { SYSZ_INS_BIP, "bip" }, - { SYSZ_INS_BIZ, "biz" }, - { SYSZ_INS_BL, "bl" }, - { SYSZ_INS_BLE, "ble" }, - { SYSZ_INS_BLH, "blh" }, - { SYSZ_INS_BM, "bm" }, - { SYSZ_INS_BMR, "bmr" }, - { SYSZ_INS_BNE, "bne" }, - { SYSZ_INS_BNH, "bnh" }, - { SYSZ_INS_BNHE, "bnhe" }, - { SYSZ_INS_BNL, "bnl" }, - { SYSZ_INS_BNLE, "bnle" }, - { SYSZ_INS_BNLH, "bnlh" }, - { SYSZ_INS_BNM, "bnm" }, - { SYSZ_INS_BNMR, "bnmr" }, - { SYSZ_INS_BNO, "bno" }, - { SYSZ_INS_BNP, "bnp" }, - { SYSZ_INS_BNPR, "bnpr" }, - { SYSZ_INS_BNZ, "bnz" }, - { SYSZ_INS_BNZR, "bnzr" }, - { SYSZ_INS_BO, "bo" }, - { SYSZ_INS_BP, "bp" }, - { SYSZ_INS_BPP, "bpp" }, - { SYSZ_INS_BPR, "bpr" }, - { SYSZ_INS_BPRP, "bprp" }, - { SYSZ_INS_BRCTH, "brcth" }, - { SYSZ_INS_BRXH, "brxh" }, - { SYSZ_INS_BRXHG, "brxhg" }, - { SYSZ_INS_BRXLE, "brxle" }, - { SYSZ_INS_BRXLG, "brxlg" }, - { SYSZ_INS_BSA, "bsa" }, - { SYSZ_INS_BSG, "bsg" }, - { SYSZ_INS_BSM, "bsm" }, - { SYSZ_INS_BXH, "bxh" }, - { SYSZ_INS_BXHG, "bxhg" }, - { SYSZ_INS_BXLE, "bxle" }, - { SYSZ_INS_BXLEG, "bxleg" }, - { SYSZ_INS_BZ, "bz" }, - { SYSZ_INS_BZR, "bzr" }, - { SYSZ_INS_CD, "cd" }, - { SYSZ_INS_CDFBRA, "cdfbra" }, - { SYSZ_INS_CDFR, "cdfr" }, - { SYSZ_INS_CDFTR, "cdftr" }, - { SYSZ_INS_CDGBRA, "cdgbra" }, - { SYSZ_INS_CDGR, "cdgr" }, - { SYSZ_INS_CDGTR, "cdgtr" }, - { SYSZ_INS_CDGTRA, "cdgtra" }, - { SYSZ_INS_CDLFTR, "cdlftr" }, - { SYSZ_INS_CDLGTR, "cdlgtr" }, - { SYSZ_INS_CDPT, "cdpt" }, - { SYSZ_INS_CDR, "cdr" }, - { SYSZ_INS_CDS, "cds" }, - { SYSZ_INS_CDSG, "cdsg" }, - { SYSZ_INS_CDSTR, "cdstr" }, - { SYSZ_INS_CDSY, "cdsy" }, - { SYSZ_INS_CDTR, "cdtr" }, - { SYSZ_INS_CDUTR, "cdutr" }, - { SYSZ_INS_CDZT, "cdzt" }, - { SYSZ_INS_CE, "ce" }, - { SYSZ_INS_CEDTR, "cedtr" }, - { SYSZ_INS_CEFBRA, "cefbra" }, - { SYSZ_INS_CEFR, "cefr" }, - { SYSZ_INS_CEGBRA, "cegbra" }, - { SYSZ_INS_CEGR, "cegr" }, - { SYSZ_INS_CER, "cer" }, - { SYSZ_INS_CEXTR, "cextr" }, - { SYSZ_INS_CFC, "cfc" }, - { SYSZ_INS_CFDBRA, "cfdbra" }, - { SYSZ_INS_CFDR, "cfdr" }, - { SYSZ_INS_CFDTR, "cfdtr" }, - { SYSZ_INS_CFEBRA, "cfebra" }, - { SYSZ_INS_CFER, "cfer" }, - { SYSZ_INS_CFXBRA, "cfxbra" }, - { SYSZ_INS_CFXR, "cfxr" }, - { SYSZ_INS_CFXTR, "cfxtr" }, - { SYSZ_INS_CGDBRA, "cgdbra" }, - { SYSZ_INS_CGDR, "cgdr" }, - { SYSZ_INS_CGDTR, "cgdtr" }, - { SYSZ_INS_CGDTRA, "cgdtra" }, - { SYSZ_INS_CGEBRA, "cgebra" }, - { SYSZ_INS_CGER, "cger" }, - { SYSZ_INS_CGIB, "cgib" }, - { SYSZ_INS_CGIBE, "cgibe" }, - { SYSZ_INS_CGIBH, "cgibh" }, - { SYSZ_INS_CGIBHE, "cgibhe" }, - { SYSZ_INS_CGIBL, "cgibl" }, - { SYSZ_INS_CGIBLE, "cgible" }, - { SYSZ_INS_CGIBLH, "cgiblh" }, - { SYSZ_INS_CGIBNE, "cgibne" }, - { SYSZ_INS_CGIBNH, "cgibnh" }, - { SYSZ_INS_CGIBNHE, "cgibnhe" }, - { SYSZ_INS_CGIBNL, "cgibnl" }, - { SYSZ_INS_CGIBNLE, "cgibnle" }, - { SYSZ_INS_CGIBNLH, "cgibnlh" }, - { SYSZ_INS_CGIT, "cgit" }, - { SYSZ_INS_CGITE, "cgite" }, - { SYSZ_INS_CGITH, "cgith" }, - { SYSZ_INS_CGITHE, "cgithe" }, - { SYSZ_INS_CGITL, "cgitl" }, - { SYSZ_INS_CGITLE, "cgitle" }, - { SYSZ_INS_CGITLH, "cgitlh" }, - { SYSZ_INS_CGITNE, "cgitne" }, - { SYSZ_INS_CGITNH, "cgitnh" }, - { SYSZ_INS_CGITNHE, "cgitnhe" }, - { SYSZ_INS_CGITNL, "cgitnl" }, - { SYSZ_INS_CGITNLE, "cgitnle" }, - { SYSZ_INS_CGITNLH, "cgitnlh" }, - { SYSZ_INS_CGRB, "cgrb" }, - { SYSZ_INS_CGRBE, "cgrbe" }, - { SYSZ_INS_CGRBH, "cgrbh" }, - { SYSZ_INS_CGRBHE, "cgrbhe" }, - { SYSZ_INS_CGRBL, "cgrbl" }, - { SYSZ_INS_CGRBLE, "cgrble" }, - { SYSZ_INS_CGRBLH, "cgrblh" }, - { SYSZ_INS_CGRBNE, "cgrbne" }, - { SYSZ_INS_CGRBNH, "cgrbnh" }, - { SYSZ_INS_CGRBNHE, "cgrbnhe" }, - { SYSZ_INS_CGRBNL, "cgrbnl" }, - { SYSZ_INS_CGRBNLE, "cgrbnle" }, - { SYSZ_INS_CGRBNLH, "cgrbnlh" }, - { SYSZ_INS_CGRT, "cgrt" }, - { SYSZ_INS_CGRTE, "cgrte" }, - { SYSZ_INS_CGRTH, "cgrth" }, - { SYSZ_INS_CGRTHE, "cgrthe" }, - { SYSZ_INS_CGRTL, "cgrtl" }, - { SYSZ_INS_CGRTLE, "cgrtle" }, - { SYSZ_INS_CGRTLH, "cgrtlh" }, - { SYSZ_INS_CGRTNE, "cgrtne" }, - { SYSZ_INS_CGRTNH, "cgrtnh" }, - { SYSZ_INS_CGRTNHE, "cgrtnhe" }, - { SYSZ_INS_CGRTNL, "cgrtnl" }, - { SYSZ_INS_CGRTNLE, "cgrtnle" }, - { SYSZ_INS_CGRTNLH, "cgrtnlh" }, - { SYSZ_INS_CGXBRA, "cgxbra" }, - { SYSZ_INS_CGXR, "cgxr" }, - { SYSZ_INS_CGXTR, "cgxtr" }, - { SYSZ_INS_CGXTRA, "cgxtra" }, - { SYSZ_INS_CHHR, "chhr" }, - { SYSZ_INS_CHLR, "chlr" }, - { SYSZ_INS_CIB, "cib" }, - { SYSZ_INS_CIBE, "cibe" }, - { SYSZ_INS_CIBH, "cibh" }, - { SYSZ_INS_CIBHE, "cibhe" }, - { SYSZ_INS_CIBL, "cibl" }, - { SYSZ_INS_CIBLE, "cible" }, - { SYSZ_INS_CIBLH, "ciblh" }, - { SYSZ_INS_CIBNE, "cibne" }, - { SYSZ_INS_CIBNH, "cibnh" }, - { SYSZ_INS_CIBNHE, "cibnhe" }, - { SYSZ_INS_CIBNL, "cibnl" }, - { SYSZ_INS_CIBNLE, "cibnle" }, - { SYSZ_INS_CIBNLH, "cibnlh" }, - { SYSZ_INS_CIT, "cit" }, - { SYSZ_INS_CITE, "cite" }, - { SYSZ_INS_CITH, "cith" }, - { SYSZ_INS_CITHE, "cithe" }, - { SYSZ_INS_CITL, "citl" }, - { SYSZ_INS_CITLE, "citle" }, - { SYSZ_INS_CITLH, "citlh" }, - { SYSZ_INS_CITNE, "citne" }, - { SYSZ_INS_CITNH, "citnh" }, - { SYSZ_INS_CITNHE, "citnhe" }, - { SYSZ_INS_CITNL, "citnl" }, - { SYSZ_INS_CITNLE, "citnle" }, - { SYSZ_INS_CITNLH, "citnlh" }, - { SYSZ_INS_CKSM, "cksm" }, - { SYSZ_INS_CLCL, "clcl" }, - { SYSZ_INS_CLCLE, "clcle" }, - { SYSZ_INS_CLCLU, "clclu" }, - { SYSZ_INS_CLFDTR, "clfdtr" }, - { SYSZ_INS_CLFIT, "clfit" }, - { SYSZ_INS_CLFITE, "clfite" }, - { SYSZ_INS_CLFITH, "clfith" }, - { SYSZ_INS_CLFITHE, "clfithe" }, - { SYSZ_INS_CLFITL, "clfitl" }, - { SYSZ_INS_CLFITLE, "clfitle" }, - { SYSZ_INS_CLFITLH, "clfitlh" }, - { SYSZ_INS_CLFITNE, "clfitne" }, - { SYSZ_INS_CLFITNH, "clfitnh" }, - { SYSZ_INS_CLFITNHE, "clfitnhe" }, - { SYSZ_INS_CLFITNL, "clfitnl" }, - { SYSZ_INS_CLFITNLE, "clfitnle" }, - { SYSZ_INS_CLFITNLH, "clfitnlh" }, - { SYSZ_INS_CLFXTR, "clfxtr" }, - { SYSZ_INS_CLGDTR, "clgdtr" }, - { SYSZ_INS_CLGIB, "clgib" }, - { SYSZ_INS_CLGIBE, "clgibe" }, - { SYSZ_INS_CLGIBH, "clgibh" }, - { SYSZ_INS_CLGIBHE, "clgibhe" }, - { SYSZ_INS_CLGIBL, "clgibl" }, - { SYSZ_INS_CLGIBLE, "clgible" }, - { SYSZ_INS_CLGIBLH, "clgiblh" }, - { SYSZ_INS_CLGIBNE, "clgibne" }, - { SYSZ_INS_CLGIBNH, "clgibnh" }, - { SYSZ_INS_CLGIBNHE, "clgibnhe" }, - { SYSZ_INS_CLGIBNL, "clgibnl" }, - { SYSZ_INS_CLGIBNLE, "clgibnle" }, - { SYSZ_INS_CLGIBNLH, "clgibnlh" }, - { SYSZ_INS_CLGIT, "clgit" }, - { SYSZ_INS_CLGITE, "clgite" }, - { SYSZ_INS_CLGITH, "clgith" }, - { SYSZ_INS_CLGITHE, "clgithe" }, - { SYSZ_INS_CLGITL, "clgitl" }, - { SYSZ_INS_CLGITLE, "clgitle" }, - { SYSZ_INS_CLGITLH, "clgitlh" }, - { SYSZ_INS_CLGITNE, "clgitne" }, - { SYSZ_INS_CLGITNH, "clgitnh" }, - { SYSZ_INS_CLGITNHE, "clgitnhe" }, - { SYSZ_INS_CLGITNL, "clgitnl" }, - { SYSZ_INS_CLGITNLE, "clgitnle" }, - { SYSZ_INS_CLGITNLH, "clgitnlh" }, - { SYSZ_INS_CLGRB, "clgrb" }, - { SYSZ_INS_CLGRBE, "clgrbe" }, - { SYSZ_INS_CLGRBH, "clgrbh" }, - { SYSZ_INS_CLGRBHE, "clgrbhe" }, - { SYSZ_INS_CLGRBL, "clgrbl" }, - { SYSZ_INS_CLGRBLE, "clgrble" }, - { SYSZ_INS_CLGRBLH, "clgrblh" }, - { SYSZ_INS_CLGRBNE, "clgrbne" }, - { SYSZ_INS_CLGRBNH, "clgrbnh" }, - { SYSZ_INS_CLGRBNHE, "clgrbnhe" }, - { SYSZ_INS_CLGRBNL, "clgrbnl" }, - { SYSZ_INS_CLGRBNLE, "clgrbnle" }, - { SYSZ_INS_CLGRBNLH, "clgrbnlh" }, - { SYSZ_INS_CLGRT, "clgrt" }, - { SYSZ_INS_CLGRTE, "clgrte" }, - { SYSZ_INS_CLGRTH, "clgrth" }, - { SYSZ_INS_CLGRTHE, "clgrthe" }, - { SYSZ_INS_CLGRTL, "clgrtl" }, - { SYSZ_INS_CLGRTLE, "clgrtle" }, - { SYSZ_INS_CLGRTLH, "clgrtlh" }, - { SYSZ_INS_CLGRTNE, "clgrtne" }, - { SYSZ_INS_CLGRTNH, "clgrtnh" }, - { SYSZ_INS_CLGRTNHE, "clgrtnhe" }, - { SYSZ_INS_CLGRTNL, "clgrtnl" }, - { SYSZ_INS_CLGRTNLE, "clgrtnle" }, - { SYSZ_INS_CLGRTNLH, "clgrtnlh" }, - { SYSZ_INS_CLGT, "clgt" }, - { SYSZ_INS_CLGTE, "clgte" }, - { SYSZ_INS_CLGTH, "clgth" }, - { SYSZ_INS_CLGTHE, "clgthe" }, - { SYSZ_INS_CLGTL, "clgtl" }, - { SYSZ_INS_CLGTLE, "clgtle" }, - { SYSZ_INS_CLGTLH, "clgtlh" }, - { SYSZ_INS_CLGTNE, "clgtne" }, - { SYSZ_INS_CLGTNH, "clgtnh" }, - { SYSZ_INS_CLGTNHE, "clgtnhe" }, - { SYSZ_INS_CLGTNL, "clgtnl" }, - { SYSZ_INS_CLGTNLE, "clgtnle" }, - { SYSZ_INS_CLGTNLH, "clgtnlh" }, - { SYSZ_INS_CLGXTR, "clgxtr" }, - { SYSZ_INS_CLHHR, "clhhr" }, - { SYSZ_INS_CLHLR, "clhlr" }, - { SYSZ_INS_CLIB, "clib" }, - { SYSZ_INS_CLIBE, "clibe" }, - { SYSZ_INS_CLIBH, "clibh" }, - { SYSZ_INS_CLIBHE, "clibhe" }, - { SYSZ_INS_CLIBL, "clibl" }, - { SYSZ_INS_CLIBLE, "clible" }, - { SYSZ_INS_CLIBLH, "cliblh" }, - { SYSZ_INS_CLIBNE, "clibne" }, - { SYSZ_INS_CLIBNH, "clibnh" }, - { SYSZ_INS_CLIBNHE, "clibnhe" }, - { SYSZ_INS_CLIBNL, "clibnl" }, - { SYSZ_INS_CLIBNLE, "clibnle" }, - { SYSZ_INS_CLIBNLH, "clibnlh" }, - { SYSZ_INS_CLM, "clm" }, - { SYSZ_INS_CLMH, "clmh" }, - { SYSZ_INS_CLMY, "clmy" }, - { SYSZ_INS_CLRB, "clrb" }, - { SYSZ_INS_CLRBE, "clrbe" }, - { SYSZ_INS_CLRBH, "clrbh" }, - { SYSZ_INS_CLRBHE, "clrbhe" }, - { SYSZ_INS_CLRBL, "clrbl" }, - { SYSZ_INS_CLRBLE, "clrble" }, - { SYSZ_INS_CLRBLH, "clrblh" }, - { SYSZ_INS_CLRBNE, "clrbne" }, - { SYSZ_INS_CLRBNH, "clrbnh" }, - { SYSZ_INS_CLRBNHE, "clrbnhe" }, - { SYSZ_INS_CLRBNL, "clrbnl" }, - { SYSZ_INS_CLRBNLE, "clrbnle" }, - { SYSZ_INS_CLRBNLH, "clrbnlh" }, - { SYSZ_INS_CLRT, "clrt" }, - { SYSZ_INS_CLRTE, "clrte" }, - { SYSZ_INS_CLRTH, "clrth" }, - { SYSZ_INS_CLRTHE, "clrthe" }, - { SYSZ_INS_CLRTL, "clrtl" }, - { SYSZ_INS_CLRTLE, "clrtle" }, - { SYSZ_INS_CLRTLH, "clrtlh" }, - { SYSZ_INS_CLRTNE, "clrtne" }, - { SYSZ_INS_CLRTNH, "clrtnh" }, - { SYSZ_INS_CLRTNHE, "clrtnhe" }, - { SYSZ_INS_CLRTNL, "clrtnl" }, - { SYSZ_INS_CLRTNLE, "clrtnle" }, - { SYSZ_INS_CLRTNLH, "clrtnlh" }, - { SYSZ_INS_CLT, "clt" }, - { SYSZ_INS_CLTE, "clte" }, - { SYSZ_INS_CLTH, "clth" }, - { SYSZ_INS_CLTHE, "clthe" }, - { SYSZ_INS_CLTL, "cltl" }, - { SYSZ_INS_CLTLE, "cltle" }, - { SYSZ_INS_CLTLH, "cltlh" }, - { SYSZ_INS_CLTNE, "cltne" }, - { SYSZ_INS_CLTNH, "cltnh" }, - { SYSZ_INS_CLTNHE, "cltnhe" }, - { SYSZ_INS_CLTNL, "cltnl" }, - { SYSZ_INS_CLTNLE, "cltnle" }, - { SYSZ_INS_CLTNLH, "cltnlh" }, - { SYSZ_INS_CMPSC, "cmpsc" }, - { SYSZ_INS_CP, "cp" }, - { SYSZ_INS_CPDT, "cpdt" }, - { SYSZ_INS_CPXT, "cpxt" }, - { SYSZ_INS_CPYA, "cpya" }, - { SYSZ_INS_CRB, "crb" }, - { SYSZ_INS_CRBE, "crbe" }, - { SYSZ_INS_CRBH, "crbh" }, - { SYSZ_INS_CRBHE, "crbhe" }, - { SYSZ_INS_CRBL, "crbl" }, - { SYSZ_INS_CRBLE, "crble" }, - { SYSZ_INS_CRBLH, "crblh" }, - { SYSZ_INS_CRBNE, "crbne" }, - { SYSZ_INS_CRBNH, "crbnh" }, - { SYSZ_INS_CRBNHE, "crbnhe" }, - { SYSZ_INS_CRBNL, "crbnl" }, - { SYSZ_INS_CRBNLE, "crbnle" }, - { SYSZ_INS_CRBNLH, "crbnlh" }, - { SYSZ_INS_CRDTE, "crdte" }, - { SYSZ_INS_CRT, "crt" }, - { SYSZ_INS_CRTE, "crte" }, - { SYSZ_INS_CRTH, "crth" }, - { SYSZ_INS_CRTHE, "crthe" }, - { SYSZ_INS_CRTL, "crtl" }, - { SYSZ_INS_CRTLE, "crtle" }, - { SYSZ_INS_CRTLH, "crtlh" }, - { SYSZ_INS_CRTNE, "crtne" }, - { SYSZ_INS_CRTNH, "crtnh" }, - { SYSZ_INS_CRTNHE, "crtnhe" }, - { SYSZ_INS_CRTNL, "crtnl" }, - { SYSZ_INS_CRTNLE, "crtnle" }, - { SYSZ_INS_CRTNLH, "crtnlh" }, - { SYSZ_INS_CSCH, "csch" }, - { SYSZ_INS_CSDTR, "csdtr" }, - { SYSZ_INS_CSP, "csp" }, - { SYSZ_INS_CSPG, "cspg" }, - { SYSZ_INS_CSST, "csst" }, - { SYSZ_INS_CSXTR, "csxtr" }, - { SYSZ_INS_CU12, "cu12" }, - { SYSZ_INS_CU14, "cu14" }, - { SYSZ_INS_CU21, "cu21" }, - { SYSZ_INS_CU24, "cu24" }, - { SYSZ_INS_CU41, "cu41" }, - { SYSZ_INS_CU42, "cu42" }, - { SYSZ_INS_CUDTR, "cudtr" }, - { SYSZ_INS_CUSE, "cuse" }, - { SYSZ_INS_CUTFU, "cutfu" }, - { SYSZ_INS_CUUTF, "cuutf" }, - { SYSZ_INS_CUXTR, "cuxtr" }, - { SYSZ_INS_CVB, "cvb" }, - { SYSZ_INS_CVBG, "cvbg" }, - { SYSZ_INS_CVBY, "cvby" }, - { SYSZ_INS_CVD, "cvd" }, - { SYSZ_INS_CVDG, "cvdg" }, - { SYSZ_INS_CVDY, "cvdy" }, - { SYSZ_INS_CXFBRA, "cxfbra" }, - { SYSZ_INS_CXFR, "cxfr" }, - { SYSZ_INS_CXFTR, "cxftr" }, - { SYSZ_INS_CXGBRA, "cxgbra" }, - { SYSZ_INS_CXGR, "cxgr" }, - { SYSZ_INS_CXGTR, "cxgtr" }, - { SYSZ_INS_CXGTRA, "cxgtra" }, - { SYSZ_INS_CXLFTR, "cxlftr" }, - { SYSZ_INS_CXLGTR, "cxlgtr" }, - { SYSZ_INS_CXPT, "cxpt" }, - { SYSZ_INS_CXR, "cxr" }, - { SYSZ_INS_CXSTR, "cxstr" }, - { SYSZ_INS_CXTR, "cxtr" }, - { SYSZ_INS_CXUTR, "cxutr" }, - { SYSZ_INS_CXZT, "cxzt" }, - { SYSZ_INS_CZDT, "czdt" }, - { SYSZ_INS_CZXT, "czxt" }, - { SYSZ_INS_D, "d" }, - { SYSZ_INS_DD, "dd" }, - { SYSZ_INS_DDR, "ddr" }, - { SYSZ_INS_DDTR, "ddtr" }, - { SYSZ_INS_DDTRA, "ddtra" }, - { SYSZ_INS_DE, "de" }, - { SYSZ_INS_DER, "der" }, - { SYSZ_INS_DIAG, "diag" }, - { SYSZ_INS_DIDBR, "didbr" }, - { SYSZ_INS_DIEBR, "diebr" }, - { SYSZ_INS_DP, "dp" }, - { SYSZ_INS_DR, "dr" }, - { SYSZ_INS_DXR, "dxr" }, - { SYSZ_INS_DXTR, "dxtr" }, - { SYSZ_INS_DXTRA, "dxtra" }, - { SYSZ_INS_ECAG, "ecag" }, - { SYSZ_INS_ECCTR, "ecctr" }, - { SYSZ_INS_ECPGA, "ecpga" }, - { SYSZ_INS_ECTG, "ectg" }, - { SYSZ_INS_ED, "ed" }, - { SYSZ_INS_EDMK, "edmk" }, - { SYSZ_INS_EEDTR, "eedtr" }, - { SYSZ_INS_EEXTR, "eextr" }, - { SYSZ_INS_EFPC, "efpc" }, - { SYSZ_INS_EPAIR, "epair" }, - { SYSZ_INS_EPAR, "epar" }, - { SYSZ_INS_EPCTR, "epctr" }, - { SYSZ_INS_EPSW, "epsw" }, - { SYSZ_INS_EREG, "ereg" }, - { SYSZ_INS_EREGG, "eregg" }, - { SYSZ_INS_ESAIR, "esair" }, - { SYSZ_INS_ESAR, "esar" }, - { SYSZ_INS_ESDTR, "esdtr" }, - { SYSZ_INS_ESEA, "esea" }, - { SYSZ_INS_ESTA, "esta" }, - { SYSZ_INS_ESXTR, "esxtr" }, - { SYSZ_INS_ETND, "etnd" }, - { SYSZ_INS_EX, "ex" }, - { SYSZ_INS_EXRL, "exrl" }, - { SYSZ_INS_FIDR, "fidr" }, - { SYSZ_INS_FIDTR, "fidtr" }, - { SYSZ_INS_FIER, "fier" }, - { SYSZ_INS_FIXR, "fixr" }, - { SYSZ_INS_FIXTR, "fixtr" }, - { SYSZ_INS_HDR, "hdr" }, - { SYSZ_INS_HER, "her" }, - { SYSZ_INS_HSCH, "hsch" }, - { SYSZ_INS_IAC, "iac" }, - { SYSZ_INS_ICM, "icm" }, - { SYSZ_INS_ICMH, "icmh" }, - { SYSZ_INS_ICMY, "icmy" }, - { SYSZ_INS_IDTE, "idte" }, - { SYSZ_INS_IEDTR, "iedtr" }, - { SYSZ_INS_IEXTR, "iextr" }, - { SYSZ_INS_IPK, "ipk" }, - { SYSZ_INS_IPTE, "ipte" }, - { SYSZ_INS_IRBM, "irbm" }, - { SYSZ_INS_ISKE, "iske" }, - { SYSZ_INS_IVSK, "ivsk" }, - { SYSZ_INS_JGM, "jgm" }, - { SYSZ_INS_JGNM, "jgnm" }, - { SYSZ_INS_JGNP, "jgnp" }, - { SYSZ_INS_JGNZ, "jgnz" }, - { SYSZ_INS_JGP, "jgp" }, - { SYSZ_INS_JGZ, "jgz" }, - { SYSZ_INS_JM, "jm" }, - { SYSZ_INS_JNM, "jnm" }, - { SYSZ_INS_JNP, "jnp" }, - { SYSZ_INS_JNZ, "jnz" }, - { SYSZ_INS_JP, "jp" }, - { SYSZ_INS_JZ, "jz" }, - { SYSZ_INS_KDB, "kdb" }, - { SYSZ_INS_KDBR, "kdbr" }, - { SYSZ_INS_KDTR, "kdtr" }, - { SYSZ_INS_KEB, "keb" }, - { SYSZ_INS_KEBR, "kebr" }, - { SYSZ_INS_KIMD, "kimd" }, - { SYSZ_INS_KLMD, "klmd" }, - { SYSZ_INS_KM, "km" }, - { SYSZ_INS_KMA, "kma" }, - { SYSZ_INS_KMAC, "kmac" }, - { SYSZ_INS_KMC, "kmc" }, - { SYSZ_INS_KMCTR, "kmctr" }, - { SYSZ_INS_KMF, "kmf" }, - { SYSZ_INS_KMO, "kmo" }, - { SYSZ_INS_KXBR, "kxbr" }, - { SYSZ_INS_KXTR, "kxtr" }, - { SYSZ_INS_LAE, "lae" }, - { SYSZ_INS_LAEY, "laey" }, - { SYSZ_INS_LAM, "lam" }, - { SYSZ_INS_LAMY, "lamy" }, - { SYSZ_INS_LASP, "lasp" }, - { SYSZ_INS_LAT, "lat" }, - { SYSZ_INS_LCBB, "lcbb" }, - { SYSZ_INS_LCCTL, "lcctl" }, - { SYSZ_INS_LCDFR, "lcdfr" }, - { SYSZ_INS_LCDR, "lcdr" }, - { SYSZ_INS_LCER, "lcer" }, - { SYSZ_INS_LCTL, "lctl" }, - { SYSZ_INS_LCTLG, "lctlg" }, - { SYSZ_INS_LCXR, "lcxr" }, - { SYSZ_INS_LDE, "lde" }, - { SYSZ_INS_LDER, "lder" }, - { SYSZ_INS_LDETR, "ldetr" }, - { SYSZ_INS_LDXR, "ldxr" }, - { SYSZ_INS_LDXTR, "ldxtr" }, - { SYSZ_INS_LEDR, "ledr" }, - { SYSZ_INS_LEDTR, "ledtr" }, - { SYSZ_INS_LEXR, "lexr" }, - { SYSZ_INS_LFAS, "lfas" }, - { SYSZ_INS_LFHAT, "lfhat" }, - { SYSZ_INS_LFPC, "lfpc" }, - { SYSZ_INS_LGAT, "lgat" }, - { SYSZ_INS_LGG, "lgg" }, - { SYSZ_INS_LGSC, "lgsc" }, - { SYSZ_INS_LLGFAT, "llgfat" }, - { SYSZ_INS_LLGFSG, "llgfsg" }, - { SYSZ_INS_LLGT, "llgt" }, - { SYSZ_INS_LLGTAT, "llgtat" }, - { SYSZ_INS_LLGTR, "llgtr" }, - { SYSZ_INS_LLZRGF, "llzrgf" }, - { SYSZ_INS_LM, "lm" }, - { SYSZ_INS_LMD, "lmd" }, - { SYSZ_INS_LMH, "lmh" }, - { SYSZ_INS_LMY, "lmy" }, - { SYSZ_INS_LNDFR, "lndfr" }, - { SYSZ_INS_LNDR, "lndr" }, - { SYSZ_INS_LNER, "lner" }, - { SYSZ_INS_LNXR, "lnxr" }, - { SYSZ_INS_LOCFH, "locfh" }, - { SYSZ_INS_LOCFHE, "locfhe" }, - { SYSZ_INS_LOCFHH, "locfhh" }, - { SYSZ_INS_LOCFHHE, "locfhhe" }, - { SYSZ_INS_LOCFHL, "locfhl" }, - { SYSZ_INS_LOCFHLE, "locfhle" }, - { SYSZ_INS_LOCFHLH, "locfhlh" }, - { SYSZ_INS_LOCFHM, "locfhm" }, - { SYSZ_INS_LOCFHNE, "locfhne" }, - { SYSZ_INS_LOCFHNH, "locfhnh" }, - { SYSZ_INS_LOCFHNHE, "locfhnhe" }, - { SYSZ_INS_LOCFHNL, "locfhnl" }, - { SYSZ_INS_LOCFHNLE, "locfhnle" }, - { SYSZ_INS_LOCFHNLH, "locfhnlh" }, - { SYSZ_INS_LOCFHNM, "locfhnm" }, - { SYSZ_INS_LOCFHNO, "locfhno" }, - { SYSZ_INS_LOCFHNP, "locfhnp" }, - { SYSZ_INS_LOCFHNZ, "locfhnz" }, - { SYSZ_INS_LOCFHO, "locfho" }, - { SYSZ_INS_LOCFHP, "locfhp" }, - { SYSZ_INS_LOCFHR, "locfhr" }, - { SYSZ_INS_LOCFHRE, "locfhre" }, - { SYSZ_INS_LOCFHRH, "locfhrh" }, - { SYSZ_INS_LOCFHRHE, "locfhrhe" }, - { SYSZ_INS_LOCFHRL, "locfhrl" }, - { SYSZ_INS_LOCFHRLE, "locfhrle" }, - { SYSZ_INS_LOCFHRLH, "locfhrlh" }, - { SYSZ_INS_LOCFHRM, "locfhrm" }, - { SYSZ_INS_LOCFHRNE, "locfhrne" }, - { SYSZ_INS_LOCFHRNH, "locfhrnh" }, - { SYSZ_INS_LOCFHRNHE, "locfhrnhe" }, - { SYSZ_INS_LOCFHRNL, "locfhrnl" }, - { SYSZ_INS_LOCFHRNLE, "locfhrnle" }, - { SYSZ_INS_LOCFHRNLH, "locfhrnlh" }, - { SYSZ_INS_LOCFHRNM, "locfhrnm" }, - { SYSZ_INS_LOCFHRNO, "locfhrno" }, - { SYSZ_INS_LOCFHRNP, "locfhrnp" }, - { SYSZ_INS_LOCFHRNZ, "locfhrnz" }, - { SYSZ_INS_LOCFHRO, "locfhro" }, - { SYSZ_INS_LOCFHRP, "locfhrp" }, - { SYSZ_INS_LOCFHRZ, "locfhrz" }, - { SYSZ_INS_LOCFHZ, "locfhz" }, - { SYSZ_INS_LOCGHI, "locghi" }, - { SYSZ_INS_LOCGHIE, "locghie" }, - { SYSZ_INS_LOCGHIH, "locghih" }, - { SYSZ_INS_LOCGHIHE, "locghihe" }, - { SYSZ_INS_LOCGHIL, "locghil" }, - { SYSZ_INS_LOCGHILE, "locghile" }, - { SYSZ_INS_LOCGHILH, "locghilh" }, - { SYSZ_INS_LOCGHIM, "locghim" }, - { SYSZ_INS_LOCGHINE, "locghine" }, - { SYSZ_INS_LOCGHINH, "locghinh" }, - { SYSZ_INS_LOCGHINHE, "locghinhe" }, - { SYSZ_INS_LOCGHINL, "locghinl" }, - { SYSZ_INS_LOCGHINLE, "locghinle" }, - { SYSZ_INS_LOCGHINLH, "locghinlh" }, - { SYSZ_INS_LOCGHINM, "locghinm" }, - { SYSZ_INS_LOCGHINO, "locghino" }, - { SYSZ_INS_LOCGHINP, "locghinp" }, - { SYSZ_INS_LOCGHINZ, "locghinz" }, - { SYSZ_INS_LOCGHIO, "locghio" }, - { SYSZ_INS_LOCGHIP, "locghip" }, - { SYSZ_INS_LOCGHIZ, "locghiz" }, - { SYSZ_INS_LOCGM, "locgm" }, - { SYSZ_INS_LOCGNM, "locgnm" }, - { SYSZ_INS_LOCGNP, "locgnp" }, - { SYSZ_INS_LOCGNZ, "locgnz" }, - { SYSZ_INS_LOCGP, "locgp" }, - { SYSZ_INS_LOCGRM, "locgrm" }, - { SYSZ_INS_LOCGRNM, "locgrnm" }, - { SYSZ_INS_LOCGRNP, "locgrnp" }, - { SYSZ_INS_LOCGRNZ, "locgrnz" }, - { SYSZ_INS_LOCGRP, "locgrp" }, - { SYSZ_INS_LOCGRZ, "locgrz" }, - { SYSZ_INS_LOCGZ, "locgz" }, - { SYSZ_INS_LOCHHI, "lochhi" }, - { SYSZ_INS_LOCHHIE, "lochhie" }, - { SYSZ_INS_LOCHHIH, "lochhih" }, - { SYSZ_INS_LOCHHIHE, "lochhihe" }, - { SYSZ_INS_LOCHHIL, "lochhil" }, - { SYSZ_INS_LOCHHILE, "lochhile" }, - { SYSZ_INS_LOCHHILH, "lochhilh" }, - { SYSZ_INS_LOCHHIM, "lochhim" }, - { SYSZ_INS_LOCHHINE, "lochhine" }, - { SYSZ_INS_LOCHHINH, "lochhinh" }, - { SYSZ_INS_LOCHHINHE, "lochhinhe" }, - { SYSZ_INS_LOCHHINL, "lochhinl" }, - { SYSZ_INS_LOCHHINLE, "lochhinle" }, - { SYSZ_INS_LOCHHINLH, "lochhinlh" }, - { SYSZ_INS_LOCHHINM, "lochhinm" }, - { SYSZ_INS_LOCHHINO, "lochhino" }, - { SYSZ_INS_LOCHHINP, "lochhinp" }, - { SYSZ_INS_LOCHHINZ, "lochhinz" }, - { SYSZ_INS_LOCHHIO, "lochhio" }, - { SYSZ_INS_LOCHHIP, "lochhip" }, - { SYSZ_INS_LOCHHIZ, "lochhiz" }, - { SYSZ_INS_LOCHI, "lochi" }, - { SYSZ_INS_LOCHIE, "lochie" }, - { SYSZ_INS_LOCHIH, "lochih" }, - { SYSZ_INS_LOCHIHE, "lochihe" }, - { SYSZ_INS_LOCHIL, "lochil" }, - { SYSZ_INS_LOCHILE, "lochile" }, - { SYSZ_INS_LOCHILH, "lochilh" }, - { SYSZ_INS_LOCHIM, "lochim" }, - { SYSZ_INS_LOCHINE, "lochine" }, - { SYSZ_INS_LOCHINH, "lochinh" }, - { SYSZ_INS_LOCHINHE, "lochinhe" }, - { SYSZ_INS_LOCHINL, "lochinl" }, - { SYSZ_INS_LOCHINLE, "lochinle" }, - { SYSZ_INS_LOCHINLH, "lochinlh" }, - { SYSZ_INS_LOCHINM, "lochinm" }, - { SYSZ_INS_LOCHINO, "lochino" }, - { SYSZ_INS_LOCHINP, "lochinp" }, - { SYSZ_INS_LOCHINZ, "lochinz" }, - { SYSZ_INS_LOCHIO, "lochio" }, - { SYSZ_INS_LOCHIP, "lochip" }, - { SYSZ_INS_LOCHIZ, "lochiz" }, - { SYSZ_INS_LOCM, "locm" }, - { SYSZ_INS_LOCNM, "locnm" }, - { SYSZ_INS_LOCNP, "locnp" }, - { SYSZ_INS_LOCNZ, "locnz" }, - { SYSZ_INS_LOCP, "locp" }, - { SYSZ_INS_LOCRM, "locrm" }, - { SYSZ_INS_LOCRNM, "locrnm" }, - { SYSZ_INS_LOCRNP, "locrnp" }, - { SYSZ_INS_LOCRNZ, "locrnz" }, - { SYSZ_INS_LOCRP, "locrp" }, - { SYSZ_INS_LOCRZ, "locrz" }, - { SYSZ_INS_LOCZ, "locz" }, - { SYSZ_INS_LPCTL, "lpctl" }, - { SYSZ_INS_LPD, "lpd" }, - { SYSZ_INS_LPDFR, "lpdfr" }, - { SYSZ_INS_LPDG, "lpdg" }, - { SYSZ_INS_LPDR, "lpdr" }, - { SYSZ_INS_LPER, "lper" }, - { SYSZ_INS_LPP, "lpp" }, - { SYSZ_INS_LPQ, "lpq" }, - { SYSZ_INS_LPSW, "lpsw" }, - { SYSZ_INS_LPSWE, "lpswe" }, - { SYSZ_INS_LPTEA, "lptea" }, - { SYSZ_INS_LPXR, "lpxr" }, - { SYSZ_INS_LRA, "lra" }, - { SYSZ_INS_LRAG, "lrag" }, - { SYSZ_INS_LRAY, "lray" }, - { SYSZ_INS_LRDR, "lrdr" }, - { SYSZ_INS_LRER, "lrer" }, - { SYSZ_INS_LRVH, "lrvh" }, - { SYSZ_INS_LSCTL, "lsctl" }, - { SYSZ_INS_LTDR, "ltdr" }, - { SYSZ_INS_LTDTR, "ltdtr" }, - { SYSZ_INS_LTER, "lter" }, - { SYSZ_INS_LTXR, "ltxr" }, - { SYSZ_INS_LTXTR, "ltxtr" }, - { SYSZ_INS_LURA, "lura" }, - { SYSZ_INS_LURAG, "lurag" }, - { SYSZ_INS_LXD, "lxd" }, - { SYSZ_INS_LXDR, "lxdr" }, - { SYSZ_INS_LXDTR, "lxdtr" }, - { SYSZ_INS_LXE, "lxe" }, - { SYSZ_INS_LXER, "lxer" }, - { SYSZ_INS_LZRF, "lzrf" }, - { SYSZ_INS_LZRG, "lzrg" }, - { SYSZ_INS_M, "m" }, - { SYSZ_INS_MAD, "mad" }, - { SYSZ_INS_MADR, "madr" }, - { SYSZ_INS_MAE, "mae" }, - { SYSZ_INS_MAER, "maer" }, - { SYSZ_INS_MAY, "may" }, - { SYSZ_INS_MAYH, "mayh" }, - { SYSZ_INS_MAYHR, "mayhr" }, - { SYSZ_INS_MAYL, "mayl" }, - { SYSZ_INS_MAYLR, "maylr" }, - { SYSZ_INS_MAYR, "mayr" }, - { SYSZ_INS_MC, "mc" }, - { SYSZ_INS_MD, "md" }, - { SYSZ_INS_MDE, "mde" }, - { SYSZ_INS_MDER, "mder" }, - { SYSZ_INS_MDR, "mdr" }, - { SYSZ_INS_MDTR, "mdtr" }, - { SYSZ_INS_MDTRA, "mdtra" }, - { SYSZ_INS_ME, "me" }, - { SYSZ_INS_MEE, "mee" }, - { SYSZ_INS_MEER, "meer" }, - { SYSZ_INS_MER, "mer" }, - { SYSZ_INS_MFY, "mfy" }, - { SYSZ_INS_MG, "mg" }, - { SYSZ_INS_MGH, "mgh" }, - { SYSZ_INS_MGRK, "mgrk" }, - { SYSZ_INS_ML, "ml" }, - { SYSZ_INS_MLR, "mlr" }, - { SYSZ_INS_MP, "mp" }, - { SYSZ_INS_MR, "mr" }, - { SYSZ_INS_MSC, "msc" }, - { SYSZ_INS_MSCH, "msch" }, - { SYSZ_INS_MSD, "msd" }, - { SYSZ_INS_MSDR, "msdr" }, - { SYSZ_INS_MSE, "mse" }, - { SYSZ_INS_MSER, "mser" }, - { SYSZ_INS_MSGC, "msgc" }, - { SYSZ_INS_MSGRKC, "msgrkc" }, - { SYSZ_INS_MSRKC, "msrkc" }, - { SYSZ_INS_MSTA, "msta" }, - { SYSZ_INS_MVCDK, "mvcdk" }, - { SYSZ_INS_MVCIN, "mvcin" }, - { SYSZ_INS_MVCK, "mvck" }, - { SYSZ_INS_MVCL, "mvcl" }, - { SYSZ_INS_MVCLE, "mvcle" }, - { SYSZ_INS_MVCLU, "mvclu" }, - { SYSZ_INS_MVCOS, "mvcos" }, - { SYSZ_INS_MVCP, "mvcp" }, - { SYSZ_INS_MVCS, "mvcs" }, - { SYSZ_INS_MVCSK, "mvcsk" }, - { SYSZ_INS_MVN, "mvn" }, - { SYSZ_INS_MVO, "mvo" }, - { SYSZ_INS_MVPG, "mvpg" }, - { SYSZ_INS_MVZ, "mvz" }, - { SYSZ_INS_MXD, "mxd" }, - { SYSZ_INS_MXDR, "mxdr" }, - { SYSZ_INS_MXR, "mxr" }, - { SYSZ_INS_MXTR, "mxtr" }, - { SYSZ_INS_MXTRA, "mxtra" }, - { SYSZ_INS_MY, "my" }, - { SYSZ_INS_MYH, "myh" }, - { SYSZ_INS_MYHR, "myhr" }, - { SYSZ_INS_MYL, "myl" }, - { SYSZ_INS_MYLR, "mylr" }, - { SYSZ_INS_MYR, "myr" }, - { SYSZ_INS_NIAI, "niai" }, - { SYSZ_INS_NTSTG, "ntstg" }, - { SYSZ_INS_PACK, "pack" }, - { SYSZ_INS_PALB, "palb" }, - { SYSZ_INS_PC, "pc" }, - { SYSZ_INS_PCC, "pcc" }, - { SYSZ_INS_PCKMO, "pckmo" }, - { SYSZ_INS_PFMF, "pfmf" }, - { SYSZ_INS_PFPO, "pfpo" }, - { SYSZ_INS_PGIN, "pgin" }, - { SYSZ_INS_PGOUT, "pgout" }, - { SYSZ_INS_PKA, "pka" }, - { SYSZ_INS_PKU, "pku" }, - { SYSZ_INS_PLO, "plo" }, - { SYSZ_INS_POPCNT, "popcnt" }, - { SYSZ_INS_PPA, "ppa" }, - { SYSZ_INS_PPNO, "ppno" }, - { SYSZ_INS_PR, "pr" }, - { SYSZ_INS_PRNO, "prno" }, - { SYSZ_INS_PT, "pt" }, - { SYSZ_INS_PTF, "ptf" }, - { SYSZ_INS_PTFF, "ptff" }, - { SYSZ_INS_PTI, "pti" }, - { SYSZ_INS_PTLB, "ptlb" }, - { SYSZ_INS_QADTR, "qadtr" }, - { SYSZ_INS_QAXTR, "qaxtr" }, - { SYSZ_INS_QCTRI, "qctri" }, - { SYSZ_INS_QSI, "qsi" }, - { SYSZ_INS_RCHP, "rchp" }, - { SYSZ_INS_RISBGN, "risbgn" }, - { SYSZ_INS_RP, "rp" }, - { SYSZ_INS_RRBE, "rrbe" }, - { SYSZ_INS_RRBM, "rrbm" }, - { SYSZ_INS_RRDTR, "rrdtr" }, - { SYSZ_INS_RRXTR, "rrxtr" }, - { SYSZ_INS_RSCH, "rsch" }, - { SYSZ_INS_SAC, "sac" }, - { SYSZ_INS_SACF, "sacf" }, - { SYSZ_INS_SAL, "sal" }, - { SYSZ_INS_SAM24, "sam24" }, - { SYSZ_INS_SAM31, "sam31" }, - { SYSZ_INS_SAM64, "sam64" }, - { SYSZ_INS_SAR, "sar" }, - { SYSZ_INS_SCCTR, "scctr" }, - { SYSZ_INS_SCHM, "schm" }, - { SYSZ_INS_SCK, "sck" }, - { SYSZ_INS_SCKC, "sckc" }, - { SYSZ_INS_SCKPF, "sckpf" }, - { SYSZ_INS_SD, "sd" }, - { SYSZ_INS_SDR, "sdr" }, - { SYSZ_INS_SDTR, "sdtr" }, - { SYSZ_INS_SDTRA, "sdtra" }, - { SYSZ_INS_SE, "se" }, - { SYSZ_INS_SER, "ser" }, - { SYSZ_INS_SFASR, "sfasr" }, - { SYSZ_INS_SFPC, "sfpc" }, - { SYSZ_INS_SGH, "sgh" }, - { SYSZ_INS_SHHHR, "shhhr" }, - { SYSZ_INS_SHHLR, "shhlr" }, - { SYSZ_INS_SIE, "sie" }, - { SYSZ_INS_SIGA, "siga" }, - { SYSZ_INS_SIGP, "sigp" }, - { SYSZ_INS_SLA, "sla" }, - { SYSZ_INS_SLAG, "slag" }, - { SYSZ_INS_SLAK, "slak" }, - { SYSZ_INS_SLDA, "slda" }, - { SYSZ_INS_SLDL, "sldl" }, - { SYSZ_INS_SLDT, "sldt" }, - { SYSZ_INS_SLHHHR, "slhhhr" }, - { SYSZ_INS_SLHHLR, "slhhlr" }, - { SYSZ_INS_SLXT, "slxt" }, - { SYSZ_INS_SP, "sp" }, - { SYSZ_INS_SPCTR, "spctr" }, - { SYSZ_INS_SPKA, "spka" }, - { SYSZ_INS_SPM, "spm" }, - { SYSZ_INS_SPT, "spt" }, - { SYSZ_INS_SPX, "spx" }, - { SYSZ_INS_SQD, "sqd" }, - { SYSZ_INS_SQDR, "sqdr" }, - { SYSZ_INS_SQE, "sqe" }, - { SYSZ_INS_SQER, "sqer" }, - { SYSZ_INS_SQXR, "sqxr" }, - { SYSZ_INS_SRDA, "srda" }, - { SYSZ_INS_SRDL, "srdl" }, - { SYSZ_INS_SRDT, "srdt" }, - { SYSZ_INS_SRNM, "srnm" }, - { SYSZ_INS_SRNMB, "srnmb" }, - { SYSZ_INS_SRNMT, "srnmt" }, - { SYSZ_INS_SRP, "srp" }, - { SYSZ_INS_SRSTU, "srstu" }, - { SYSZ_INS_SRXT, "srxt" }, - { SYSZ_INS_SSAIR, "ssair" }, - { SYSZ_INS_SSAR, "ssar" }, - { SYSZ_INS_SSCH, "ssch" }, - { SYSZ_INS_SSKE, "sske" }, - { SYSZ_INS_SSM, "ssm" }, - { SYSZ_INS_STAM, "stam" }, - { SYSZ_INS_STAMY, "stamy" }, - { SYSZ_INS_STAP, "stap" }, - { SYSZ_INS_STCK, "stck" }, - { SYSZ_INS_STCKC, "stckc" }, - { SYSZ_INS_STCKE, "stcke" }, - { SYSZ_INS_STCKF, "stckf" }, - { SYSZ_INS_STCM, "stcm" }, - { SYSZ_INS_STCMH, "stcmh" }, - { SYSZ_INS_STCMY, "stcmy" }, - { SYSZ_INS_STCPS, "stcps" }, - { SYSZ_INS_STCRW, "stcrw" }, - { SYSZ_INS_STCTG, "stctg" }, - { SYSZ_INS_STCTL, "stctl" }, - { SYSZ_INS_STFL, "stfl" }, - { SYSZ_INS_STFLE, "stfle" }, - { SYSZ_INS_STFPC, "stfpc" }, - { SYSZ_INS_STGSC, "stgsc" }, - { SYSZ_INS_STIDP, "stidp" }, - { SYSZ_INS_STM, "stm" }, - { SYSZ_INS_STMH, "stmh" }, - { SYSZ_INS_STMY, "stmy" }, - { SYSZ_INS_STNSM, "stnsm" }, - { SYSZ_INS_STOCFH, "stocfh" }, - { SYSZ_INS_STOCFHE, "stocfhe" }, - { SYSZ_INS_STOCFHH, "stocfhh" }, - { SYSZ_INS_STOCFHHE, "stocfhhe" }, - { SYSZ_INS_STOCFHL, "stocfhl" }, - { SYSZ_INS_STOCFHLE, "stocfhle" }, - { SYSZ_INS_STOCFHLH, "stocfhlh" }, - { SYSZ_INS_STOCFHM, "stocfhm" }, - { SYSZ_INS_STOCFHNE, "stocfhne" }, - { SYSZ_INS_STOCFHNH, "stocfhnh" }, - { SYSZ_INS_STOCFHNHE, "stocfhnhe" }, - { SYSZ_INS_STOCFHNL, "stocfhnl" }, - { SYSZ_INS_STOCFHNLE, "stocfhnle" }, - { SYSZ_INS_STOCFHNLH, "stocfhnlh" }, - { SYSZ_INS_STOCFHNM, "stocfhnm" }, - { SYSZ_INS_STOCFHNO, "stocfhno" }, - { SYSZ_INS_STOCFHNP, "stocfhnp" }, - { SYSZ_INS_STOCFHNZ, "stocfhnz" }, - { SYSZ_INS_STOCFHO, "stocfho" }, - { SYSZ_INS_STOCFHP, "stocfhp" }, - { SYSZ_INS_STOCFHZ, "stocfhz" }, - { SYSZ_INS_STOCGM, "stocgm" }, - { SYSZ_INS_STOCGNM, "stocgnm" }, - { SYSZ_INS_STOCGNP, "stocgnp" }, - { SYSZ_INS_STOCGNZ, "stocgnz" }, - { SYSZ_INS_STOCGP, "stocgp" }, - { SYSZ_INS_STOCGZ, "stocgz" }, - { SYSZ_INS_STOCM, "stocm" }, - { SYSZ_INS_STOCNM, "stocnm" }, - { SYSZ_INS_STOCNP, "stocnp" }, - { SYSZ_INS_STOCNZ, "stocnz" }, - { SYSZ_INS_STOCP, "stocp" }, - { SYSZ_INS_STOCZ, "stocz" }, - { SYSZ_INS_STOSM, "stosm" }, - { SYSZ_INS_STPQ, "stpq" }, - { SYSZ_INS_STPT, "stpt" }, - { SYSZ_INS_STPX, "stpx" }, - { SYSZ_INS_STRAG, "strag" }, - { SYSZ_INS_STRVH, "strvh" }, - { SYSZ_INS_STSCH, "stsch" }, - { SYSZ_INS_STSI, "stsi" }, - { SYSZ_INS_STURA, "stura" }, - { SYSZ_INS_STURG, "sturg" }, - { SYSZ_INS_SU, "su" }, - { SYSZ_INS_SUR, "sur" }, - { SYSZ_INS_SVC, "svc" }, - { SYSZ_INS_SW, "sw" }, - { SYSZ_INS_SWR, "swr" }, - { SYSZ_INS_SXR, "sxr" }, - { SYSZ_INS_SXTR, "sxtr" }, - { SYSZ_INS_SXTRA, "sxtra" }, - { SYSZ_INS_TABORT, "tabort" }, - { SYSZ_INS_TAM, "tam" }, - { SYSZ_INS_TAR, "tar" }, - { SYSZ_INS_TB, "tb" }, - { SYSZ_INS_TBDR, "tbdr" }, - { SYSZ_INS_TBEDR, "tbedr" }, - { SYSZ_INS_TBEGIN, "tbegin" }, - { SYSZ_INS_TBEGINC, "tbeginc" }, - { SYSZ_INS_TCDB, "tcdb" }, - { SYSZ_INS_TCEB, "tceb" }, - { SYSZ_INS_TCXB, "tcxb" }, - { SYSZ_INS_TDCDT, "tdcdt" }, - { SYSZ_INS_TDCET, "tdcet" }, - { SYSZ_INS_TDCXT, "tdcxt" }, - { SYSZ_INS_TDGDT, "tdgdt" }, - { SYSZ_INS_TDGET, "tdget" }, - { SYSZ_INS_TDGXT, "tdgxt" }, - { SYSZ_INS_TEND, "tend" }, - { SYSZ_INS_THDER, "thder" }, - { SYSZ_INS_THDR, "thdr" }, - { SYSZ_INS_TP, "tp" }, - { SYSZ_INS_TPI, "tpi" }, - { SYSZ_INS_TPROT, "tprot" }, - { SYSZ_INS_TR, "tr" }, - { SYSZ_INS_TRACE, "trace" }, - { SYSZ_INS_TRACG, "tracg" }, - { SYSZ_INS_TRAP2, "trap2" }, - { SYSZ_INS_TRAP4, "trap4" }, - { SYSZ_INS_TRE, "tre" }, - { SYSZ_INS_TROO, "troo" }, - { SYSZ_INS_TROT, "trot" }, - { SYSZ_INS_TRT, "trt" }, - { SYSZ_INS_TRTE, "trte" }, - { SYSZ_INS_TRTO, "trto" }, - { SYSZ_INS_TRTR, "trtr" }, - { SYSZ_INS_TRTRE, "trtre" }, - { SYSZ_INS_TRTT, "trtt" }, - { SYSZ_INS_TS, "ts" }, - { SYSZ_INS_TSCH, "tsch" }, - { SYSZ_INS_UNPK, "unpk" }, - { SYSZ_INS_UNPKA, "unpka" }, - { SYSZ_INS_UNPKU, "unpku" }, - { SYSZ_INS_UPT, "upt" }, - { SYSZ_INS_VA, "va" }, - { SYSZ_INS_VAB, "vab" }, - { SYSZ_INS_VAC, "vac" }, - { SYSZ_INS_VACC, "vacc" }, - { SYSZ_INS_VACCB, "vaccb" }, - { SYSZ_INS_VACCC, "vaccc" }, - { SYSZ_INS_VACCCQ, "vacccq" }, - { SYSZ_INS_VACCF, "vaccf" }, - { SYSZ_INS_VACCG, "vaccg" }, - { SYSZ_INS_VACCH, "vacch" }, - { SYSZ_INS_VACCQ, "vaccq" }, - { SYSZ_INS_VACQ, "vacq" }, - { SYSZ_INS_VAF, "vaf" }, - { SYSZ_INS_VAG, "vag" }, - { SYSZ_INS_VAH, "vah" }, - { SYSZ_INS_VAP, "vap" }, - { SYSZ_INS_VAQ, "vaq" }, - { SYSZ_INS_VAVG, "vavg" }, - { SYSZ_INS_VAVGB, "vavgb" }, - { SYSZ_INS_VAVGF, "vavgf" }, - { SYSZ_INS_VAVGG, "vavgg" }, - { SYSZ_INS_VAVGH, "vavgh" }, - { SYSZ_INS_VAVGL, "vavgl" }, - { SYSZ_INS_VAVGLB, "vavglb" }, - { SYSZ_INS_VAVGLF, "vavglf" }, - { SYSZ_INS_VAVGLG, "vavglg" }, - { SYSZ_INS_VAVGLH, "vavglh" }, - { SYSZ_INS_VBPERM, "vbperm" }, - { SYSZ_INS_VCDG, "vcdg" }, - { SYSZ_INS_VCDGB, "vcdgb" }, - { SYSZ_INS_VCDLG, "vcdlg" }, - { SYSZ_INS_VCDLGB, "vcdlgb" }, - { SYSZ_INS_VCEQ, "vceq" }, - { SYSZ_INS_VCEQB, "vceqb" }, - { SYSZ_INS_VCEQBS, "vceqbs" }, - { SYSZ_INS_VCEQF, "vceqf" }, - { SYSZ_INS_VCEQFS, "vceqfs" }, - { SYSZ_INS_VCEQG, "vceqg" }, - { SYSZ_INS_VCEQGS, "vceqgs" }, - { SYSZ_INS_VCEQH, "vceqh" }, - { SYSZ_INS_VCEQHS, "vceqhs" }, - { SYSZ_INS_VCGD, "vcgd" }, - { SYSZ_INS_VCGDB, "vcgdb" }, - { SYSZ_INS_VCH, "vch" }, - { SYSZ_INS_VCHB, "vchb" }, - { SYSZ_INS_VCHBS, "vchbs" }, - { SYSZ_INS_VCHF, "vchf" }, - { SYSZ_INS_VCHFS, "vchfs" }, - { SYSZ_INS_VCHG, "vchg" }, - { SYSZ_INS_VCHGS, "vchgs" }, - { SYSZ_INS_VCHH, "vchh" }, - { SYSZ_INS_VCHHS, "vchhs" }, - { SYSZ_INS_VCHL, "vchl" }, - { SYSZ_INS_VCHLB, "vchlb" }, - { SYSZ_INS_VCHLBS, "vchlbs" }, - { SYSZ_INS_VCHLF, "vchlf" }, - { SYSZ_INS_VCHLFS, "vchlfs" }, - { SYSZ_INS_VCHLG, "vchlg" }, - { SYSZ_INS_VCHLGS, "vchlgs" }, - { SYSZ_INS_VCHLH, "vchlh" }, - { SYSZ_INS_VCHLHS, "vchlhs" }, - { SYSZ_INS_VCKSM, "vcksm" }, - { SYSZ_INS_VCLGD, "vclgd" }, - { SYSZ_INS_VCLGDB, "vclgdb" }, - { SYSZ_INS_VCLZ, "vclz" }, - { SYSZ_INS_VCLZB, "vclzb" }, - { SYSZ_INS_VCLZF, "vclzf" }, - { SYSZ_INS_VCLZG, "vclzg" }, - { SYSZ_INS_VCLZH, "vclzh" }, - { SYSZ_INS_VCP, "vcp" }, - { SYSZ_INS_VCTZ, "vctz" }, - { SYSZ_INS_VCTZB, "vctzb" }, - { SYSZ_INS_VCTZF, "vctzf" }, - { SYSZ_INS_VCTZG, "vctzg" }, - { SYSZ_INS_VCTZH, "vctzh" }, - { SYSZ_INS_VCVB, "vcvb" }, - { SYSZ_INS_VCVBG, "vcvbg" }, - { SYSZ_INS_VCVD, "vcvd" }, - { SYSZ_INS_VCVDG, "vcvdg" }, - { SYSZ_INS_VDP, "vdp" }, - { SYSZ_INS_VEC, "vec" }, - { SYSZ_INS_VECB, "vecb" }, - { SYSZ_INS_VECF, "vecf" }, - { SYSZ_INS_VECG, "vecg" }, - { SYSZ_INS_VECH, "vech" }, - { SYSZ_INS_VECL, "vecl" }, - { SYSZ_INS_VECLB, "veclb" }, - { SYSZ_INS_VECLF, "veclf" }, - { SYSZ_INS_VECLG, "veclg" }, - { SYSZ_INS_VECLH, "veclh" }, - { SYSZ_INS_VERIM, "verim" }, - { SYSZ_INS_VERIMB, "verimb" }, - { SYSZ_INS_VERIMF, "verimf" }, - { SYSZ_INS_VERIMG, "verimg" }, - { SYSZ_INS_VERIMH, "verimh" }, - { SYSZ_INS_VERLL, "verll" }, - { SYSZ_INS_VERLLB, "verllb" }, - { SYSZ_INS_VERLLF, "verllf" }, - { SYSZ_INS_VERLLG, "verllg" }, - { SYSZ_INS_VERLLH, "verllh" }, - { SYSZ_INS_VERLLV, "verllv" }, - { SYSZ_INS_VERLLVB, "verllvb" }, - { SYSZ_INS_VERLLVF, "verllvf" }, - { SYSZ_INS_VERLLVG, "verllvg" }, - { SYSZ_INS_VERLLVH, "verllvh" }, - { SYSZ_INS_VESL, "vesl" }, - { SYSZ_INS_VESLB, "veslb" }, - { SYSZ_INS_VESLF, "veslf" }, - { SYSZ_INS_VESLG, "veslg" }, - { SYSZ_INS_VESLH, "veslh" }, - { SYSZ_INS_VESLV, "veslv" }, - { SYSZ_INS_VESLVB, "veslvb" }, - { SYSZ_INS_VESLVF, "veslvf" }, - { SYSZ_INS_VESLVG, "veslvg" }, - { SYSZ_INS_VESLVH, "veslvh" }, - { SYSZ_INS_VESRA, "vesra" }, - { SYSZ_INS_VESRAB, "vesrab" }, - { SYSZ_INS_VESRAF, "vesraf" }, - { SYSZ_INS_VESRAG, "vesrag" }, - { SYSZ_INS_VESRAH, "vesrah" }, - { SYSZ_INS_VESRAV, "vesrav" }, - { SYSZ_INS_VESRAVB, "vesravb" }, - { SYSZ_INS_VESRAVF, "vesravf" }, - { SYSZ_INS_VESRAVG, "vesravg" }, - { SYSZ_INS_VESRAVH, "vesravh" }, - { SYSZ_INS_VESRL, "vesrl" }, - { SYSZ_INS_VESRLB, "vesrlb" }, - { SYSZ_INS_VESRLF, "vesrlf" }, - { SYSZ_INS_VESRLG, "vesrlg" }, - { SYSZ_INS_VESRLH, "vesrlh" }, - { SYSZ_INS_VESRLV, "vesrlv" }, - { SYSZ_INS_VESRLVB, "vesrlvb" }, - { SYSZ_INS_VESRLVF, "vesrlvf" }, - { SYSZ_INS_VESRLVG, "vesrlvg" }, - { SYSZ_INS_VESRLVH, "vesrlvh" }, - { SYSZ_INS_VFA, "vfa" }, - { SYSZ_INS_VFADB, "vfadb" }, - { SYSZ_INS_VFAE, "vfae" }, - { SYSZ_INS_VFAEB, "vfaeb" }, - { SYSZ_INS_VFAEBS, "vfaebs" }, - { SYSZ_INS_VFAEF, "vfaef" }, - { SYSZ_INS_VFAEFS, "vfaefs" }, - { SYSZ_INS_VFAEH, "vfaeh" }, - { SYSZ_INS_VFAEHS, "vfaehs" }, - { SYSZ_INS_VFAEZB, "vfaezb" }, - { SYSZ_INS_VFAEZBS, "vfaezbs" }, - { SYSZ_INS_VFAEZF, "vfaezf" }, - { SYSZ_INS_VFAEZFS, "vfaezfs" }, - { SYSZ_INS_VFAEZH, "vfaezh" }, - { SYSZ_INS_VFAEZHS, "vfaezhs" }, - { SYSZ_INS_VFASB, "vfasb" }, - { SYSZ_INS_VFCE, "vfce" }, - { SYSZ_INS_VFCEDB, "vfcedb" }, - { SYSZ_INS_VFCEDBS, "vfcedbs" }, - { SYSZ_INS_VFCESB, "vfcesb" }, - { SYSZ_INS_VFCESBS, "vfcesbs" }, - { SYSZ_INS_VFCH, "vfch" }, - { SYSZ_INS_VFCHDB, "vfchdb" }, - { SYSZ_INS_VFCHDBS, "vfchdbs" }, - { SYSZ_INS_VFCHE, "vfche" }, - { SYSZ_INS_VFCHEDB, "vfchedb" }, - { SYSZ_INS_VFCHEDBS, "vfchedbs" }, - { SYSZ_INS_VFCHESB, "vfchesb" }, - { SYSZ_INS_VFCHESBS, "vfchesbs" }, - { SYSZ_INS_VFCHSB, "vfchsb" }, - { SYSZ_INS_VFCHSBS, "vfchsbs" }, - { SYSZ_INS_VFD, "vfd" }, - { SYSZ_INS_VFDDB, "vfddb" }, - { SYSZ_INS_VFDSB, "vfdsb" }, - { SYSZ_INS_VFEE, "vfee" }, - { SYSZ_INS_VFEEB, "vfeeb" }, - { SYSZ_INS_VFEEBS, "vfeebs" }, - { SYSZ_INS_VFEEF, "vfeef" }, - { SYSZ_INS_VFEEFS, "vfeefs" }, - { SYSZ_INS_VFEEH, "vfeeh" }, - { SYSZ_INS_VFEEHS, "vfeehs" }, - { SYSZ_INS_VFEEZB, "vfeezb" }, - { SYSZ_INS_VFEEZBS, "vfeezbs" }, - { SYSZ_INS_VFEEZF, "vfeezf" }, - { SYSZ_INS_VFEEZFS, "vfeezfs" }, - { SYSZ_INS_VFEEZH, "vfeezh" }, - { SYSZ_INS_VFEEZHS, "vfeezhs" }, - { SYSZ_INS_VFENE, "vfene" }, - { SYSZ_INS_VFENEB, "vfeneb" }, - { SYSZ_INS_VFENEBS, "vfenebs" }, - { SYSZ_INS_VFENEF, "vfenef" }, - { SYSZ_INS_VFENEFS, "vfenefs" }, - { SYSZ_INS_VFENEH, "vfeneh" }, - { SYSZ_INS_VFENEHS, "vfenehs" }, - { SYSZ_INS_VFENEZB, "vfenezb" }, - { SYSZ_INS_VFENEZBS, "vfenezbs" }, - { SYSZ_INS_VFENEZF, "vfenezf" }, - { SYSZ_INS_VFENEZFS, "vfenezfs" }, - { SYSZ_INS_VFENEZH, "vfenezh" }, - { SYSZ_INS_VFENEZHS, "vfenezhs" }, - { SYSZ_INS_VFI, "vfi" }, - { SYSZ_INS_VFIDB, "vfidb" }, - { SYSZ_INS_VFISB, "vfisb" }, - { SYSZ_INS_VFKEDB, "vfkedb" }, - { SYSZ_INS_VFKEDBS, "vfkedbs" }, - { SYSZ_INS_VFKESB, "vfkesb" }, - { SYSZ_INS_VFKESBS, "vfkesbs" }, - { SYSZ_INS_VFKHDB, "vfkhdb" }, - { SYSZ_INS_VFKHDBS, "vfkhdbs" }, - { SYSZ_INS_VFKHEDB, "vfkhedb" }, - { SYSZ_INS_VFKHEDBS, "vfkhedbs" }, - { SYSZ_INS_VFKHESB, "vfkhesb" }, - { SYSZ_INS_VFKHESBS, "vfkhesbs" }, - { SYSZ_INS_VFKHSB, "vfkhsb" }, - { SYSZ_INS_VFKHSBS, "vfkhsbs" }, - { SYSZ_INS_VFLCDB, "vflcdb" }, - { SYSZ_INS_VFLCSB, "vflcsb" }, - { SYSZ_INS_VFLL, "vfll" }, - { SYSZ_INS_VFLLS, "vflls" }, - { SYSZ_INS_VFLNDB, "vflndb" }, - { SYSZ_INS_VFLNSB, "vflnsb" }, - { SYSZ_INS_VFLPDB, "vflpdb" }, - { SYSZ_INS_VFLPSB, "vflpsb" }, - { SYSZ_INS_VFLR, "vflr" }, - { SYSZ_INS_VFLRD, "vflrd" }, - { SYSZ_INS_VFM, "vfm" }, - { SYSZ_INS_VFMA, "vfma" }, - { SYSZ_INS_VFMADB, "vfmadb" }, - { SYSZ_INS_VFMASB, "vfmasb" }, - { SYSZ_INS_VFMAX, "vfmax" }, - { SYSZ_INS_VFMAXDB, "vfmaxdb" }, - { SYSZ_INS_VFMAXSB, "vfmaxsb" }, - { SYSZ_INS_VFMDB, "vfmdb" }, - { SYSZ_INS_VFMIN, "vfmin" }, - { SYSZ_INS_VFMINDB, "vfmindb" }, - { SYSZ_INS_VFMINSB, "vfminsb" }, - { SYSZ_INS_VFMS, "vfms" }, - { SYSZ_INS_VFMSB, "vfmsb" }, - { SYSZ_INS_VFMSDB, "vfmsdb" }, - { SYSZ_INS_VFMSSB, "vfmssb" }, - { SYSZ_INS_VFNMA, "vfnma" }, - { SYSZ_INS_VFNMADB, "vfnmadb" }, - { SYSZ_INS_VFNMASB, "vfnmasb" }, - { SYSZ_INS_VFNMS, "vfnms" }, - { SYSZ_INS_VFNMSDB, "vfnmsdb" }, - { SYSZ_INS_VFNMSSB, "vfnmssb" }, - { SYSZ_INS_VFPSO, "vfpso" }, - { SYSZ_INS_VFPSODB, "vfpsodb" }, - { SYSZ_INS_VFPSOSB, "vfpsosb" }, - { SYSZ_INS_VFS, "vfs" }, - { SYSZ_INS_VFSDB, "vfsdb" }, - { SYSZ_INS_VFSQ, "vfsq" }, - { SYSZ_INS_VFSQDB, "vfsqdb" }, - { SYSZ_INS_VFSQSB, "vfsqsb" }, - { SYSZ_INS_VFSSB, "vfssb" }, - { SYSZ_INS_VFTCI, "vftci" }, - { SYSZ_INS_VFTCIDB, "vftcidb" }, - { SYSZ_INS_VFTCISB, "vftcisb" }, - { SYSZ_INS_VGBM, "vgbm" }, - { SYSZ_INS_VGEF, "vgef" }, - { SYSZ_INS_VGEG, "vgeg" }, - { SYSZ_INS_VGFM, "vgfm" }, - { SYSZ_INS_VGFMA, "vgfma" }, - { SYSZ_INS_VGFMAB, "vgfmab" }, - { SYSZ_INS_VGFMAF, "vgfmaf" }, - { SYSZ_INS_VGFMAG, "vgfmag" }, - { SYSZ_INS_VGFMAH, "vgfmah" }, - { SYSZ_INS_VGFMB, "vgfmb" }, - { SYSZ_INS_VGFMF, "vgfmf" }, - { SYSZ_INS_VGFMG, "vgfmg" }, - { SYSZ_INS_VGFMH, "vgfmh" }, - { SYSZ_INS_VGM, "vgm" }, - { SYSZ_INS_VGMB, "vgmb" }, - { SYSZ_INS_VGMF, "vgmf" }, - { SYSZ_INS_VGMG, "vgmg" }, - { SYSZ_INS_VGMH, "vgmh" }, - { SYSZ_INS_VISTR, "vistr" }, - { SYSZ_INS_VISTRB, "vistrb" }, - { SYSZ_INS_VISTRBS, "vistrbs" }, - { SYSZ_INS_VISTRF, "vistrf" }, - { SYSZ_INS_VISTRFS, "vistrfs" }, - { SYSZ_INS_VISTRH, "vistrh" }, - { SYSZ_INS_VISTRHS, "vistrhs" }, - { SYSZ_INS_VL, "vl" }, - { SYSZ_INS_VLBB, "vlbb" }, - { SYSZ_INS_VLC, "vlc" }, - { SYSZ_INS_VLCB, "vlcb" }, - { SYSZ_INS_VLCF, "vlcf" }, - { SYSZ_INS_VLCG, "vlcg" }, - { SYSZ_INS_VLCH, "vlch" }, - { SYSZ_INS_VLDE, "vlde" }, - { SYSZ_INS_VLDEB, "vldeb" }, - { SYSZ_INS_VLEB, "vleb" }, - { SYSZ_INS_VLED, "vled" }, - { SYSZ_INS_VLEDB, "vledb" }, - { SYSZ_INS_VLEF, "vlef" }, - { SYSZ_INS_VLEG, "vleg" }, - { SYSZ_INS_VLEH, "vleh" }, - { SYSZ_INS_VLEIB, "vleib" }, - { SYSZ_INS_VLEIF, "vleif" }, - { SYSZ_INS_VLEIG, "vleig" }, - { SYSZ_INS_VLEIH, "vleih" }, - { SYSZ_INS_VLGV, "vlgv" }, - { SYSZ_INS_VLGVB, "vlgvb" }, - { SYSZ_INS_VLGVF, "vlgvf" }, - { SYSZ_INS_VLGVG, "vlgvg" }, - { SYSZ_INS_VLGVH, "vlgvh" }, - { SYSZ_INS_VLIP, "vlip" }, - { SYSZ_INS_VLL, "vll" }, - { SYSZ_INS_VLLEZ, "vllez" }, - { SYSZ_INS_VLLEZB, "vllezb" }, - { SYSZ_INS_VLLEZF, "vllezf" }, - { SYSZ_INS_VLLEZG, "vllezg" }, - { SYSZ_INS_VLLEZH, "vllezh" }, - { SYSZ_INS_VLLEZLF, "vllezlf" }, - { SYSZ_INS_VLM, "vlm" }, - { SYSZ_INS_VLP, "vlp" }, - { SYSZ_INS_VLPB, "vlpb" }, - { SYSZ_INS_VLPF, "vlpf" }, - { SYSZ_INS_VLPG, "vlpg" }, - { SYSZ_INS_VLPH, "vlph" }, - { SYSZ_INS_VLR, "vlr" }, - { SYSZ_INS_VLREP, "vlrep" }, - { SYSZ_INS_VLREPB, "vlrepb" }, - { SYSZ_INS_VLREPF, "vlrepf" }, - { SYSZ_INS_VLREPG, "vlrepg" }, - { SYSZ_INS_VLREPH, "vlreph" }, - { SYSZ_INS_VLRL, "vlrl" }, - { SYSZ_INS_VLRLR, "vlrlr" }, - { SYSZ_INS_VLVG, "vlvg" }, - { SYSZ_INS_VLVGB, "vlvgb" }, - { SYSZ_INS_VLVGF, "vlvgf" }, - { SYSZ_INS_VLVGG, "vlvgg" }, - { SYSZ_INS_VLVGH, "vlvgh" }, - { SYSZ_INS_VLVGP, "vlvgp" }, - { SYSZ_INS_VMAE, "vmae" }, - { SYSZ_INS_VMAEB, "vmaeb" }, - { SYSZ_INS_VMAEF, "vmaef" }, - { SYSZ_INS_VMAEH, "vmaeh" }, - { SYSZ_INS_VMAH, "vmah" }, - { SYSZ_INS_VMAHB, "vmahb" }, - { SYSZ_INS_VMAHF, "vmahf" }, - { SYSZ_INS_VMAHH, "vmahh" }, - { SYSZ_INS_VMAL, "vmal" }, - { SYSZ_INS_VMALB, "vmalb" }, - { SYSZ_INS_VMALE, "vmale" }, - { SYSZ_INS_VMALEB, "vmaleb" }, - { SYSZ_INS_VMALEF, "vmalef" }, - { SYSZ_INS_VMALEH, "vmaleh" }, - { SYSZ_INS_VMALF, "vmalf" }, - { SYSZ_INS_VMALH, "vmalh" }, - { SYSZ_INS_VMALHB, "vmalhb" }, - { SYSZ_INS_VMALHF, "vmalhf" }, - { SYSZ_INS_VMALHH, "vmalhh" }, - { SYSZ_INS_VMALHW, "vmalhw" }, - { SYSZ_INS_VMALO, "vmalo" }, - { SYSZ_INS_VMALOB, "vmalob" }, - { SYSZ_INS_VMALOF, "vmalof" }, - { SYSZ_INS_VMALOH, "vmaloh" }, - { SYSZ_INS_VMAO, "vmao" }, - { SYSZ_INS_VMAOB, "vmaob" }, - { SYSZ_INS_VMAOF, "vmaof" }, - { SYSZ_INS_VMAOH, "vmaoh" }, - { SYSZ_INS_VME, "vme" }, - { SYSZ_INS_VMEB, "vmeb" }, - { SYSZ_INS_VMEF, "vmef" }, - { SYSZ_INS_VMEH, "vmeh" }, - { SYSZ_INS_VMH, "vmh" }, - { SYSZ_INS_VMHB, "vmhb" }, - { SYSZ_INS_VMHF, "vmhf" }, - { SYSZ_INS_VMHH, "vmhh" }, - { SYSZ_INS_VML, "vml" }, - { SYSZ_INS_VMLB, "vmlb" }, - { SYSZ_INS_VMLE, "vmle" }, - { SYSZ_INS_VMLEB, "vmleb" }, - { SYSZ_INS_VMLEF, "vmlef" }, - { SYSZ_INS_VMLEH, "vmleh" }, - { SYSZ_INS_VMLF, "vmlf" }, - { SYSZ_INS_VMLH, "vmlh" }, - { SYSZ_INS_VMLHB, "vmlhb" }, - { SYSZ_INS_VMLHF, "vmlhf" }, - { SYSZ_INS_VMLHH, "vmlhh" }, - { SYSZ_INS_VMLHW, "vmlhw" }, - { SYSZ_INS_VMLO, "vmlo" }, - { SYSZ_INS_VMLOB, "vmlob" }, - { SYSZ_INS_VMLOF, "vmlof" }, - { SYSZ_INS_VMLOH, "vmloh" }, - { SYSZ_INS_VMN, "vmn" }, - { SYSZ_INS_VMNB, "vmnb" }, - { SYSZ_INS_VMNF, "vmnf" }, - { SYSZ_INS_VMNG, "vmng" }, - { SYSZ_INS_VMNH, "vmnh" }, - { SYSZ_INS_VMNL, "vmnl" }, - { SYSZ_INS_VMNLB, "vmnlb" }, - { SYSZ_INS_VMNLF, "vmnlf" }, - { SYSZ_INS_VMNLG, "vmnlg" }, - { SYSZ_INS_VMNLH, "vmnlh" }, - { SYSZ_INS_VMO, "vmo" }, - { SYSZ_INS_VMOB, "vmob" }, - { SYSZ_INS_VMOF, "vmof" }, - { SYSZ_INS_VMOH, "vmoh" }, - { SYSZ_INS_VMP, "vmp" }, - { SYSZ_INS_VMRH, "vmrh" }, - { SYSZ_INS_VMRHB, "vmrhb" }, - { SYSZ_INS_VMRHF, "vmrhf" }, - { SYSZ_INS_VMRHG, "vmrhg" }, - { SYSZ_INS_VMRHH, "vmrhh" }, - { SYSZ_INS_VMRL, "vmrl" }, - { SYSZ_INS_VMRLB, "vmrlb" }, - { SYSZ_INS_VMRLF, "vmrlf" }, - { SYSZ_INS_VMRLG, "vmrlg" }, - { SYSZ_INS_VMRLH, "vmrlh" }, - { SYSZ_INS_VMSL, "vmsl" }, - { SYSZ_INS_VMSLG, "vmslg" }, - { SYSZ_INS_VMSP, "vmsp" }, - { SYSZ_INS_VMX, "vmx" }, - { SYSZ_INS_VMXB, "vmxb" }, - { SYSZ_INS_VMXF, "vmxf" }, - { SYSZ_INS_VMXG, "vmxg" }, - { SYSZ_INS_VMXH, "vmxh" }, - { SYSZ_INS_VMXL, "vmxl" }, - { SYSZ_INS_VMXLB, "vmxlb" }, - { SYSZ_INS_VMXLF, "vmxlf" }, - { SYSZ_INS_VMXLG, "vmxlg" }, - { SYSZ_INS_VMXLH, "vmxlh" }, - { SYSZ_INS_VN, "vn" }, - { SYSZ_INS_VNC, "vnc" }, - { SYSZ_INS_VNN, "vnn" }, - { SYSZ_INS_VNO, "vno" }, - { SYSZ_INS_VNX, "vnx" }, - { SYSZ_INS_VO, "vo" }, - { SYSZ_INS_VOC, "voc" }, - { SYSZ_INS_VONE, "vone" }, - { SYSZ_INS_VPDI, "vpdi" }, - { SYSZ_INS_VPERM, "vperm" }, - { SYSZ_INS_VPK, "vpk" }, - { SYSZ_INS_VPKF, "vpkf" }, - { SYSZ_INS_VPKG, "vpkg" }, - { SYSZ_INS_VPKH, "vpkh" }, - { SYSZ_INS_VPKLS, "vpkls" }, - { SYSZ_INS_VPKLSF, "vpklsf" }, - { SYSZ_INS_VPKLSFS, "vpklsfs" }, - { SYSZ_INS_VPKLSG, "vpklsg" }, - { SYSZ_INS_VPKLSGS, "vpklsgs" }, - { SYSZ_INS_VPKLSH, "vpklsh" }, - { SYSZ_INS_VPKLSHS, "vpklshs" }, - { SYSZ_INS_VPKS, "vpks" }, - { SYSZ_INS_VPKSF, "vpksf" }, - { SYSZ_INS_VPKSFS, "vpksfs" }, - { SYSZ_INS_VPKSG, "vpksg" }, - { SYSZ_INS_VPKSGS, "vpksgs" }, - { SYSZ_INS_VPKSH, "vpksh" }, - { SYSZ_INS_VPKSHS, "vpkshs" }, - { SYSZ_INS_VPKZ, "vpkz" }, - { SYSZ_INS_VPOPCT, "vpopct" }, - { SYSZ_INS_VPOPCTB, "vpopctb" }, - { SYSZ_INS_VPOPCTF, "vpopctf" }, - { SYSZ_INS_VPOPCTG, "vpopctg" }, - { SYSZ_INS_VPOPCTH, "vpopcth" }, - { SYSZ_INS_VPSOP, "vpsop" }, - { SYSZ_INS_VREP, "vrep" }, - { SYSZ_INS_VREPB, "vrepb" }, - { SYSZ_INS_VREPF, "vrepf" }, - { SYSZ_INS_VREPG, "vrepg" }, - { SYSZ_INS_VREPH, "vreph" }, - { SYSZ_INS_VREPI, "vrepi" }, - { SYSZ_INS_VREPIB, "vrepib" }, - { SYSZ_INS_VREPIF, "vrepif" }, - { SYSZ_INS_VREPIG, "vrepig" }, - { SYSZ_INS_VREPIH, "vrepih" }, - { SYSZ_INS_VRP, "vrp" }, - { SYSZ_INS_VS, "vs" }, - { SYSZ_INS_VSB, "vsb" }, - { SYSZ_INS_VSBCBI, "vsbcbi" }, - { SYSZ_INS_VSBCBIQ, "vsbcbiq" }, - { SYSZ_INS_VSBI, "vsbi" }, - { SYSZ_INS_VSBIQ, "vsbiq" }, - { SYSZ_INS_VSCBI, "vscbi" }, - { SYSZ_INS_VSCBIB, "vscbib" }, - { SYSZ_INS_VSCBIF, "vscbif" }, - { SYSZ_INS_VSCBIG, "vscbig" }, - { SYSZ_INS_VSCBIH, "vscbih" }, - { SYSZ_INS_VSCBIQ, "vscbiq" }, - { SYSZ_INS_VSCEF, "vscef" }, - { SYSZ_INS_VSCEG, "vsceg" }, - { SYSZ_INS_VSDP, "vsdp" }, - { SYSZ_INS_VSEG, "vseg" }, - { SYSZ_INS_VSEGB, "vsegb" }, - { SYSZ_INS_VSEGF, "vsegf" }, - { SYSZ_INS_VSEGH, "vsegh" }, - { SYSZ_INS_VSEL, "vsel" }, - { SYSZ_INS_VSF, "vsf" }, - { SYSZ_INS_VSG, "vsg" }, - { SYSZ_INS_VSH, "vsh" }, - { SYSZ_INS_VSL, "vsl" }, - { SYSZ_INS_VSLB, "vslb" }, - { SYSZ_INS_VSLDB, "vsldb" }, - { SYSZ_INS_VSP, "vsp" }, - { SYSZ_INS_VSQ, "vsq" }, - { SYSZ_INS_VSRA, "vsra" }, - { SYSZ_INS_VSRAB, "vsrab" }, - { SYSZ_INS_VSRL, "vsrl" }, - { SYSZ_INS_VSRLB, "vsrlb" }, - { SYSZ_INS_VSRP, "vsrp" }, - { SYSZ_INS_VST, "vst" }, - { SYSZ_INS_VSTEB, "vsteb" }, - { SYSZ_INS_VSTEF, "vstef" }, - { SYSZ_INS_VSTEG, "vsteg" }, - { SYSZ_INS_VSTEH, "vsteh" }, - { SYSZ_INS_VSTL, "vstl" }, - { SYSZ_INS_VSTM, "vstm" }, - { SYSZ_INS_VSTRC, "vstrc" }, - { SYSZ_INS_VSTRCB, "vstrcb" }, - { SYSZ_INS_VSTRCBS, "vstrcbs" }, - { SYSZ_INS_VSTRCF, "vstrcf" }, - { SYSZ_INS_VSTRCFS, "vstrcfs" }, - { SYSZ_INS_VSTRCH, "vstrch" }, - { SYSZ_INS_VSTRCHS, "vstrchs" }, - { SYSZ_INS_VSTRCZB, "vstrczb" }, - { SYSZ_INS_VSTRCZBS, "vstrczbs" }, - { SYSZ_INS_VSTRCZF, "vstrczf" }, - { SYSZ_INS_VSTRCZFS, "vstrczfs" }, - { SYSZ_INS_VSTRCZH, "vstrczh" }, - { SYSZ_INS_VSTRCZHS, "vstrczhs" }, - { SYSZ_INS_VSTRL, "vstrl" }, - { SYSZ_INS_VSTRLR, "vstrlr" }, - { SYSZ_INS_VSUM, "vsum" }, - { SYSZ_INS_VSUMB, "vsumb" }, - { SYSZ_INS_VSUMG, "vsumg" }, - { SYSZ_INS_VSUMGF, "vsumgf" }, - { SYSZ_INS_VSUMGH, "vsumgh" }, - { SYSZ_INS_VSUMH, "vsumh" }, - { SYSZ_INS_VSUMQ, "vsumq" }, - { SYSZ_INS_VSUMQF, "vsumqf" }, - { SYSZ_INS_VSUMQG, "vsumqg" }, - { SYSZ_INS_VTM, "vtm" }, - { SYSZ_INS_VTP, "vtp" }, - { SYSZ_INS_VUPH, "vuph" }, - { SYSZ_INS_VUPHB, "vuphb" }, - { SYSZ_INS_VUPHF, "vuphf" }, - { SYSZ_INS_VUPHH, "vuphh" }, - { SYSZ_INS_VUPKZ, "vupkz" }, - { SYSZ_INS_VUPL, "vupl" }, - { SYSZ_INS_VUPLB, "vuplb" }, - { SYSZ_INS_VUPLF, "vuplf" }, - { SYSZ_INS_VUPLH, "vuplh" }, - { SYSZ_INS_VUPLHB, "vuplhb" }, - { SYSZ_INS_VUPLHF, "vuplhf" }, - { SYSZ_INS_VUPLHH, "vuplhh" }, - { SYSZ_INS_VUPLHW, "vuplhw" }, - { SYSZ_INS_VUPLL, "vupll" }, - { SYSZ_INS_VUPLLB, "vupllb" }, - { SYSZ_INS_VUPLLF, "vupllf" }, - { SYSZ_INS_VUPLLH, "vupllh" }, - { SYSZ_INS_VX, "vx" }, - { SYSZ_INS_VZERO, "vzero" }, - { SYSZ_INS_WCDGB, "wcdgb" }, - { SYSZ_INS_WCDLGB, "wcdlgb" }, - { SYSZ_INS_WCGDB, "wcgdb" }, - { SYSZ_INS_WCLGDB, "wclgdb" }, - { SYSZ_INS_WFADB, "wfadb" }, - { SYSZ_INS_WFASB, "wfasb" }, - { SYSZ_INS_WFAXB, "wfaxb" }, - { SYSZ_INS_WFC, "wfc" }, - { SYSZ_INS_WFCDB, "wfcdb" }, - { SYSZ_INS_WFCEDB, "wfcedb" }, - { SYSZ_INS_WFCEDBS, "wfcedbs" }, - { SYSZ_INS_WFCESB, "wfcesb" }, - { SYSZ_INS_WFCESBS, "wfcesbs" }, - { SYSZ_INS_WFCEXB, "wfcexb" }, - { SYSZ_INS_WFCEXBS, "wfcexbs" }, - { SYSZ_INS_WFCHDB, "wfchdb" }, - { SYSZ_INS_WFCHDBS, "wfchdbs" }, - { SYSZ_INS_WFCHEDB, "wfchedb" }, - { SYSZ_INS_WFCHEDBS, "wfchedbs" }, - { SYSZ_INS_WFCHESB, "wfchesb" }, - { SYSZ_INS_WFCHESBS, "wfchesbs" }, - { SYSZ_INS_WFCHEXB, "wfchexb" }, - { SYSZ_INS_WFCHEXBS, "wfchexbs" }, - { SYSZ_INS_WFCHSB, "wfchsb" }, - { SYSZ_INS_WFCHSBS, "wfchsbs" }, - { SYSZ_INS_WFCHXB, "wfchxb" }, - { SYSZ_INS_WFCHXBS, "wfchxbs" }, - { SYSZ_INS_WFCSB, "wfcsb" }, - { SYSZ_INS_WFCXB, "wfcxb" }, - { SYSZ_INS_WFDDB, "wfddb" }, - { SYSZ_INS_WFDSB, "wfdsb" }, - { SYSZ_INS_WFDXB, "wfdxb" }, - { SYSZ_INS_WFIDB, "wfidb" }, - { SYSZ_INS_WFISB, "wfisb" }, - { SYSZ_INS_WFIXB, "wfixb" }, - { SYSZ_INS_WFK, "wfk" }, - { SYSZ_INS_WFKDB, "wfkdb" }, - { SYSZ_INS_WFKEDB, "wfkedb" }, - { SYSZ_INS_WFKEDBS, "wfkedbs" }, - { SYSZ_INS_WFKESB, "wfkesb" }, - { SYSZ_INS_WFKESBS, "wfkesbs" }, - { SYSZ_INS_WFKEXB, "wfkexb" }, - { SYSZ_INS_WFKEXBS, "wfkexbs" }, - { SYSZ_INS_WFKHDB, "wfkhdb" }, - { SYSZ_INS_WFKHDBS, "wfkhdbs" }, - { SYSZ_INS_WFKHEDB, "wfkhedb" }, - { SYSZ_INS_WFKHEDBS, "wfkhedbs" }, - { SYSZ_INS_WFKHESB, "wfkhesb" }, - { SYSZ_INS_WFKHESBS, "wfkhesbs" }, - { SYSZ_INS_WFKHEXB, "wfkhexb" }, - { SYSZ_INS_WFKHEXBS, "wfkhexbs" }, - { SYSZ_INS_WFKHSB, "wfkhsb" }, - { SYSZ_INS_WFKHSBS, "wfkhsbs" }, - { SYSZ_INS_WFKHXB, "wfkhxb" }, - { SYSZ_INS_WFKHXBS, "wfkhxbs" }, - { SYSZ_INS_WFKSB, "wfksb" }, - { SYSZ_INS_WFKXB, "wfkxb" }, - { SYSZ_INS_WFLCDB, "wflcdb" }, - { SYSZ_INS_WFLCSB, "wflcsb" }, - { SYSZ_INS_WFLCXB, "wflcxb" }, - { SYSZ_INS_WFLLD, "wflld" }, - { SYSZ_INS_WFLLS, "wflls" }, - { SYSZ_INS_WFLNDB, "wflndb" }, - { SYSZ_INS_WFLNSB, "wflnsb" }, - { SYSZ_INS_WFLNXB, "wflnxb" }, - { SYSZ_INS_WFLPDB, "wflpdb" }, - { SYSZ_INS_WFLPSB, "wflpsb" }, - { SYSZ_INS_WFLPXB, "wflpxb" }, - { SYSZ_INS_WFLRD, "wflrd" }, - { SYSZ_INS_WFLRX, "wflrx" }, - { SYSZ_INS_WFMADB, "wfmadb" }, - { SYSZ_INS_WFMASB, "wfmasb" }, - { SYSZ_INS_WFMAXB, "wfmaxb" }, - { SYSZ_INS_WFMAXDB, "wfmaxdb" }, - { SYSZ_INS_WFMAXSB, "wfmaxsb" }, - { SYSZ_INS_WFMAXXB, "wfmaxxb" }, - { SYSZ_INS_WFMDB, "wfmdb" }, - { SYSZ_INS_WFMINDB, "wfmindb" }, - { SYSZ_INS_WFMINSB, "wfminsb" }, - { SYSZ_INS_WFMINXB, "wfminxb" }, - { SYSZ_INS_WFMSB, "wfmsb" }, - { SYSZ_INS_WFMSDB, "wfmsdb" }, - { SYSZ_INS_WFMSSB, "wfmssb" }, - { SYSZ_INS_WFMSXB, "wfmsxb" }, - { SYSZ_INS_WFMXB, "wfmxb" }, - { SYSZ_INS_WFNMADB, "wfnmadb" }, - { SYSZ_INS_WFNMASB, "wfnmasb" }, - { SYSZ_INS_WFNMAXB, "wfnmaxb" }, - { SYSZ_INS_WFNMSDB, "wfnmsdb" }, - { SYSZ_INS_WFNMSSB, "wfnmssb" }, - { SYSZ_INS_WFNMSXB, "wfnmsxb" }, - { SYSZ_INS_WFPSODB, "wfpsodb" }, - { SYSZ_INS_WFPSOSB, "wfpsosb" }, - { SYSZ_INS_WFPSOXB, "wfpsoxb" }, - { SYSZ_INS_WFSDB, "wfsdb" }, - { SYSZ_INS_WFSQDB, "wfsqdb" }, - { SYSZ_INS_WFSQSB, "wfsqsb" }, - { SYSZ_INS_WFSQXB, "wfsqxb" }, - { SYSZ_INS_WFSSB, "wfssb" }, - { SYSZ_INS_WFSXB, "wfsxb" }, - { SYSZ_INS_WFTCIDB, "wftcidb" }, - { SYSZ_INS_WFTCISB, "wftcisb" }, - { SYSZ_INS_WFTCIXB, "wftcixb" }, - { SYSZ_INS_WLDEB, "wldeb" }, - { SYSZ_INS_WLEDB, "wledb" }, - { SYSZ_INS_XSCH, "xsch" }, - { SYSZ_INS_ZAP, "zap" }, diff --git a/arch/SystemZ/SystemZGenInstrInfo.inc b/arch/SystemZ/SystemZGenInstrInfo.inc index 0f23556af9..b1d1bb35b3 100644 --- a/arch/SystemZ/SystemZGenInstrInfo.inc +++ b/arch/SystemZ/SystemZGenInstrInfo.inc @@ -1,2820 +1,7172 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* Target Instruction Enum Values and Descriptors *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* LLVM-commit: */ +/* LLVM-tag: */ +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM -enum { + enum { SystemZ_PHI = 0, SystemZ_INLINEASM = 1, - SystemZ_CFI_INSTRUCTION = 2, - SystemZ_EH_LABEL = 3, - SystemZ_GC_LABEL = 4, - SystemZ_ANNOTATION_LABEL = 5, - SystemZ_KILL = 6, - SystemZ_EXTRACT_SUBREG = 7, - SystemZ_INSERT_SUBREG = 8, - SystemZ_IMPLICIT_DEF = 9, - SystemZ_SUBREG_TO_REG = 10, - SystemZ_COPY_TO_REGCLASS = 11, - SystemZ_DBG_VALUE = 12, - SystemZ_DBG_LABEL = 13, - SystemZ_REG_SEQUENCE = 14, - SystemZ_COPY = 15, - SystemZ_BUNDLE = 16, - SystemZ_LIFETIME_START = 17, - SystemZ_LIFETIME_END = 18, - SystemZ_STACKMAP = 19, - SystemZ_FENTRY_CALL = 20, - SystemZ_PATCHPOINT = 21, - SystemZ_LOAD_STACK_GUARD = 22, - SystemZ_STATEPOINT = 23, - SystemZ_LOCAL_ESCAPE = 24, - SystemZ_FAULTING_OP = 25, - SystemZ_PATCHABLE_OP = 26, - SystemZ_PATCHABLE_FUNCTION_ENTER = 27, - SystemZ_PATCHABLE_RET = 28, - SystemZ_PATCHABLE_FUNCTION_EXIT = 29, - SystemZ_PATCHABLE_TAIL_CALL = 30, - SystemZ_PATCHABLE_EVENT_CALL = 31, - SystemZ_PATCHABLE_TYPED_EVENT_CALL = 32, - SystemZ_ICALL_BRANCH_FUNNEL = 33, - SystemZ_G_ADD = 34, - SystemZ_G_SUB = 35, - SystemZ_G_MUL = 36, - SystemZ_G_SDIV = 37, - SystemZ_G_UDIV = 38, - SystemZ_G_SREM = 39, - SystemZ_G_UREM = 40, - SystemZ_G_AND = 41, - SystemZ_G_OR = 42, - SystemZ_G_XOR = 43, - SystemZ_G_IMPLICIT_DEF = 44, - SystemZ_G_PHI = 45, - SystemZ_G_FRAME_INDEX = 46, - SystemZ_G_GLOBAL_VALUE = 47, - SystemZ_G_EXTRACT = 48, - SystemZ_G_UNMERGE_VALUES = 49, - SystemZ_G_INSERT = 50, - SystemZ_G_MERGE_VALUES = 51, - SystemZ_G_PTRTOINT = 52, - SystemZ_G_INTTOPTR = 53, - SystemZ_G_BITCAST = 54, - SystemZ_G_LOAD = 55, - SystemZ_G_SEXTLOAD = 56, - SystemZ_G_ZEXTLOAD = 57, - SystemZ_G_STORE = 58, - SystemZ_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59, - SystemZ_G_ATOMIC_CMPXCHG = 60, - SystemZ_G_ATOMICRMW_XCHG = 61, - SystemZ_G_ATOMICRMW_ADD = 62, - SystemZ_G_ATOMICRMW_SUB = 63, - SystemZ_G_ATOMICRMW_AND = 64, - SystemZ_G_ATOMICRMW_NAND = 65, - SystemZ_G_ATOMICRMW_OR = 66, - SystemZ_G_ATOMICRMW_XOR = 67, - SystemZ_G_ATOMICRMW_MAX = 68, - SystemZ_G_ATOMICRMW_MIN = 69, - SystemZ_G_ATOMICRMW_UMAX = 70, - SystemZ_G_ATOMICRMW_UMIN = 71, - SystemZ_G_BRCOND = 72, - SystemZ_G_BRINDIRECT = 73, - SystemZ_G_INTRINSIC = 74, - SystemZ_G_INTRINSIC_W_SIDE_EFFECTS = 75, - SystemZ_G_ANYEXT = 76, - SystemZ_G_TRUNC = 77, - SystemZ_G_CONSTANT = 78, - SystemZ_G_FCONSTANT = 79, - SystemZ_G_VASTART = 80, - SystemZ_G_VAARG = 81, - SystemZ_G_SEXT = 82, - SystemZ_G_ZEXT = 83, - SystemZ_G_SHL = 84, - SystemZ_G_LSHR = 85, - SystemZ_G_ASHR = 86, - SystemZ_G_ICMP = 87, - SystemZ_G_FCMP = 88, - SystemZ_G_SELECT = 89, - SystemZ_G_UADDE = 90, - SystemZ_G_USUBE = 91, - SystemZ_G_SADDO = 92, - SystemZ_G_SSUBO = 93, - SystemZ_G_UMULO = 94, - SystemZ_G_SMULO = 95, - SystemZ_G_UMULH = 96, - SystemZ_G_SMULH = 97, - SystemZ_G_FADD = 98, - SystemZ_G_FSUB = 99, - SystemZ_G_FMUL = 100, - SystemZ_G_FMA = 101, - SystemZ_G_FDIV = 102, - SystemZ_G_FREM = 103, - SystemZ_G_FPOW = 104, - SystemZ_G_FEXP = 105, - SystemZ_G_FEXP2 = 106, - SystemZ_G_FLOG = 107, - SystemZ_G_FLOG2 = 108, - SystemZ_G_FNEG = 109, - SystemZ_G_FPEXT = 110, - SystemZ_G_FPTRUNC = 111, - SystemZ_G_FPTOSI = 112, - SystemZ_G_FPTOUI = 113, - SystemZ_G_SITOFP = 114, - SystemZ_G_UITOFP = 115, - SystemZ_G_FABS = 116, - SystemZ_G_GEP = 117, - SystemZ_G_PTR_MASK = 118, - SystemZ_G_BR = 119, - SystemZ_G_INSERT_VECTOR_ELT = 120, - SystemZ_G_EXTRACT_VECTOR_ELT = 121, - SystemZ_G_SHUFFLE_VECTOR = 122, - SystemZ_G_BSWAP = 123, - SystemZ_G_ADDRSPACE_CAST = 124, - SystemZ_ADJCALLSTACKDOWN = 125, - SystemZ_ADJCALLSTACKUP = 126, - SystemZ_ADJDYNALLOC = 127, - SystemZ_AEXT128 = 128, - SystemZ_AFIMux = 129, - SystemZ_AHIMux = 130, - SystemZ_AHIMuxK = 131, - SystemZ_ATOMIC_CMP_SWAPW = 132, - SystemZ_ATOMIC_LOADW_AFI = 133, - SystemZ_ATOMIC_LOADW_AR = 134, - SystemZ_ATOMIC_LOADW_MAX = 135, - SystemZ_ATOMIC_LOADW_MIN = 136, - SystemZ_ATOMIC_LOADW_NILH = 137, - SystemZ_ATOMIC_LOADW_NILHi = 138, - SystemZ_ATOMIC_LOADW_NR = 139, - SystemZ_ATOMIC_LOADW_NRi = 140, - SystemZ_ATOMIC_LOADW_OILH = 141, - SystemZ_ATOMIC_LOADW_OR = 142, - SystemZ_ATOMIC_LOADW_SR = 143, - SystemZ_ATOMIC_LOADW_UMAX = 144, - SystemZ_ATOMIC_LOADW_UMIN = 145, - SystemZ_ATOMIC_LOADW_XILF = 146, - SystemZ_ATOMIC_LOADW_XR = 147, - SystemZ_ATOMIC_LOAD_AFI = 148, - SystemZ_ATOMIC_LOAD_AGFI = 149, - SystemZ_ATOMIC_LOAD_AGHI = 150, - SystemZ_ATOMIC_LOAD_AGR = 151, - SystemZ_ATOMIC_LOAD_AHI = 152, - SystemZ_ATOMIC_LOAD_AR = 153, - SystemZ_ATOMIC_LOAD_MAX_32 = 154, - SystemZ_ATOMIC_LOAD_MAX_64 = 155, - SystemZ_ATOMIC_LOAD_MIN_32 = 156, - SystemZ_ATOMIC_LOAD_MIN_64 = 157, - SystemZ_ATOMIC_LOAD_NGR = 158, - SystemZ_ATOMIC_LOAD_NGRi = 159, - SystemZ_ATOMIC_LOAD_NIHF64 = 160, - SystemZ_ATOMIC_LOAD_NIHF64i = 161, - SystemZ_ATOMIC_LOAD_NIHH64 = 162, - SystemZ_ATOMIC_LOAD_NIHH64i = 163, - SystemZ_ATOMIC_LOAD_NIHL64 = 164, - SystemZ_ATOMIC_LOAD_NIHL64i = 165, - SystemZ_ATOMIC_LOAD_NILF = 166, - SystemZ_ATOMIC_LOAD_NILF64 = 167, - SystemZ_ATOMIC_LOAD_NILF64i = 168, - SystemZ_ATOMIC_LOAD_NILFi = 169, - SystemZ_ATOMIC_LOAD_NILH = 170, - SystemZ_ATOMIC_LOAD_NILH64 = 171, - SystemZ_ATOMIC_LOAD_NILH64i = 172, - SystemZ_ATOMIC_LOAD_NILHi = 173, - SystemZ_ATOMIC_LOAD_NILL = 174, - SystemZ_ATOMIC_LOAD_NILL64 = 175, - SystemZ_ATOMIC_LOAD_NILL64i = 176, - SystemZ_ATOMIC_LOAD_NILLi = 177, - SystemZ_ATOMIC_LOAD_NR = 178, - SystemZ_ATOMIC_LOAD_NRi = 179, - SystemZ_ATOMIC_LOAD_OGR = 180, - SystemZ_ATOMIC_LOAD_OIHF64 = 181, - SystemZ_ATOMIC_LOAD_OIHH64 = 182, - SystemZ_ATOMIC_LOAD_OIHL64 = 183, - SystemZ_ATOMIC_LOAD_OILF = 184, - SystemZ_ATOMIC_LOAD_OILF64 = 185, - SystemZ_ATOMIC_LOAD_OILH = 186, - SystemZ_ATOMIC_LOAD_OILH64 = 187, - SystemZ_ATOMIC_LOAD_OILL = 188, - SystemZ_ATOMIC_LOAD_OILL64 = 189, - SystemZ_ATOMIC_LOAD_OR = 190, - SystemZ_ATOMIC_LOAD_SGR = 191, - SystemZ_ATOMIC_LOAD_SR = 192, - SystemZ_ATOMIC_LOAD_UMAX_32 = 193, - SystemZ_ATOMIC_LOAD_UMAX_64 = 194, - SystemZ_ATOMIC_LOAD_UMIN_32 = 195, - SystemZ_ATOMIC_LOAD_UMIN_64 = 196, - SystemZ_ATOMIC_LOAD_XGR = 197, - SystemZ_ATOMIC_LOAD_XIHF64 = 198, - SystemZ_ATOMIC_LOAD_XILF = 199, - SystemZ_ATOMIC_LOAD_XILF64 = 200, - SystemZ_ATOMIC_LOAD_XR = 201, - SystemZ_ATOMIC_SWAPW = 202, - SystemZ_ATOMIC_SWAP_32 = 203, - SystemZ_ATOMIC_SWAP_64 = 204, - SystemZ_CFIMux = 205, - SystemZ_CGIBCall = 206, - SystemZ_CGIBReturn = 207, - SystemZ_CGRBCall = 208, - SystemZ_CGRBReturn = 209, - SystemZ_CHIMux = 210, - SystemZ_CIBCall = 211, - SystemZ_CIBReturn = 212, - SystemZ_CLCLoop = 213, - SystemZ_CLCSequence = 214, - SystemZ_CLFIMux = 215, - SystemZ_CLGIBCall = 216, - SystemZ_CLGIBReturn = 217, - SystemZ_CLGRBCall = 218, - SystemZ_CLGRBReturn = 219, - SystemZ_CLIBCall = 220, - SystemZ_CLIBReturn = 221, - SystemZ_CLMux = 222, - SystemZ_CLRBCall = 223, - SystemZ_CLRBReturn = 224, - SystemZ_CLSTLoop = 225, - SystemZ_CMux = 226, - SystemZ_CRBCall = 227, - SystemZ_CRBReturn = 228, - SystemZ_CallBASR = 229, - SystemZ_CallBCR = 230, - SystemZ_CallBR = 231, - SystemZ_CallBRASL = 232, - SystemZ_CallBRCL = 233, - SystemZ_CallJG = 234, - SystemZ_CondReturn = 235, - SystemZ_CondStore16 = 236, - SystemZ_CondStore16Inv = 237, - SystemZ_CondStore16Mux = 238, - SystemZ_CondStore16MuxInv = 239, - SystemZ_CondStore32 = 240, - SystemZ_CondStore32Inv = 241, - SystemZ_CondStore32Mux = 242, - SystemZ_CondStore32MuxInv = 243, - SystemZ_CondStore64 = 244, - SystemZ_CondStore64Inv = 245, - SystemZ_CondStore8 = 246, - SystemZ_CondStore8Inv = 247, - SystemZ_CondStore8Mux = 248, - SystemZ_CondStore8MuxInv = 249, - SystemZ_CondStoreF32 = 250, - SystemZ_CondStoreF32Inv = 251, - SystemZ_CondStoreF64 = 252, - SystemZ_CondStoreF64Inv = 253, - SystemZ_CondTrap = 254, - SystemZ_GOT = 255, - SystemZ_IIFMux = 256, - SystemZ_IIHF64 = 257, - SystemZ_IIHH64 = 258, - SystemZ_IIHL64 = 259, - SystemZ_IIHMux = 260, - SystemZ_IILF64 = 261, - SystemZ_IILH64 = 262, - SystemZ_IILL64 = 263, - SystemZ_IILMux = 264, - SystemZ_L128 = 265, - SystemZ_LBMux = 266, - SystemZ_LEFR = 267, - SystemZ_LFER = 268, - SystemZ_LHIMux = 269, - SystemZ_LHMux = 270, - SystemZ_LLCMux = 271, - SystemZ_LLCRMux = 272, - SystemZ_LLHMux = 273, - SystemZ_LLHRMux = 274, - SystemZ_LMux = 275, - SystemZ_LOCHIMux = 276, - SystemZ_LOCMux = 277, - SystemZ_LOCRMux = 278, - SystemZ_LRMux = 279, - SystemZ_LTDBRCompare_VecPseudo = 280, - SystemZ_LTEBRCompare_VecPseudo = 281, - SystemZ_LTXBRCompare_VecPseudo = 282, - SystemZ_LX = 283, - SystemZ_MVCLoop = 284, - SystemZ_MVCSequence = 285, - SystemZ_MVSTLoop = 286, - SystemZ_MemBarrier = 287, - SystemZ_NCLoop = 288, - SystemZ_NCSequence = 289, - SystemZ_NIFMux = 290, - SystemZ_NIHF64 = 291, - SystemZ_NIHH64 = 292, - SystemZ_NIHL64 = 293, - SystemZ_NIHMux = 294, - SystemZ_NILF64 = 295, - SystemZ_NILH64 = 296, - SystemZ_NILL64 = 297, - SystemZ_NILMux = 298, - SystemZ_OCLoop = 299, - SystemZ_OCSequence = 300, - SystemZ_OIFMux = 301, - SystemZ_OIHF64 = 302, - SystemZ_OIHH64 = 303, - SystemZ_OIHL64 = 304, - SystemZ_OIHMux = 305, - SystemZ_OILF64 = 306, - SystemZ_OILH64 = 307, - SystemZ_OILL64 = 308, - SystemZ_OILMux = 309, - SystemZ_PAIR128 = 310, - SystemZ_RISBHH = 311, - SystemZ_RISBHL = 312, - SystemZ_RISBLH = 313, - SystemZ_RISBLL = 314, - SystemZ_RISBMux = 315, - SystemZ_Return = 316, - SystemZ_SRSTLoop = 317, - SystemZ_ST128 = 318, - SystemZ_STCMux = 319, - SystemZ_STHMux = 320, - SystemZ_STMux = 321, - SystemZ_STOCMux = 322, - SystemZ_STX = 323, - SystemZ_Select32 = 324, - SystemZ_Select64 = 325, - SystemZ_SelectF128 = 326, - SystemZ_SelectF32 = 327, - SystemZ_SelectF64 = 328, - SystemZ_SelectVR128 = 329, - SystemZ_SelectVR32 = 330, - SystemZ_SelectVR64 = 331, - SystemZ_Serialize = 332, - SystemZ_TBEGIN_nofloat = 333, - SystemZ_TLS_GDCALL = 334, - SystemZ_TLS_LDCALL = 335, - SystemZ_TMHH64 = 336, - SystemZ_TMHL64 = 337, - SystemZ_TMHMux = 338, - SystemZ_TMLH64 = 339, - SystemZ_TMLL64 = 340, - SystemZ_TMLMux = 341, - SystemZ_Trap = 342, - SystemZ_VL32 = 343, - SystemZ_VL64 = 344, - SystemZ_VLR32 = 345, - SystemZ_VLR64 = 346, - SystemZ_VLVGP32 = 347, - SystemZ_VST32 = 348, - SystemZ_VST64 = 349, - SystemZ_XCLoop = 350, - SystemZ_XCSequence = 351, - SystemZ_XIFMux = 352, - SystemZ_XIHF64 = 353, - SystemZ_XILF64 = 354, - SystemZ_ZEXT128 = 355, - SystemZ_A = 356, - SystemZ_AD = 357, - SystemZ_ADB = 358, - SystemZ_ADBR = 359, - SystemZ_ADR = 360, - SystemZ_ADTR = 361, - SystemZ_ADTRA = 362, - SystemZ_AE = 363, - SystemZ_AEB = 364, - SystemZ_AEBR = 365, - SystemZ_AER = 366, - SystemZ_AFI = 367, - SystemZ_AG = 368, - SystemZ_AGF = 369, - SystemZ_AGFI = 370, - SystemZ_AGFR = 371, - SystemZ_AGH = 372, - SystemZ_AGHI = 373, - SystemZ_AGHIK = 374, - SystemZ_AGR = 375, - SystemZ_AGRK = 376, - SystemZ_AGSI = 377, - SystemZ_AH = 378, - SystemZ_AHHHR = 379, - SystemZ_AHHLR = 380, - SystemZ_AHI = 381, - SystemZ_AHIK = 382, - SystemZ_AHY = 383, - SystemZ_AIH = 384, - SystemZ_AL = 385, - SystemZ_ALC = 386, - SystemZ_ALCG = 387, - SystemZ_ALCGR = 388, - SystemZ_ALCR = 389, - SystemZ_ALFI = 390, - SystemZ_ALG = 391, - SystemZ_ALGF = 392, - SystemZ_ALGFI = 393, - SystemZ_ALGFR = 394, - SystemZ_ALGHSIK = 395, - SystemZ_ALGR = 396, - SystemZ_ALGRK = 397, - SystemZ_ALGSI = 398, - SystemZ_ALHHHR = 399, - SystemZ_ALHHLR = 400, - SystemZ_ALHSIK = 401, - SystemZ_ALR = 402, - SystemZ_ALRK = 403, - SystemZ_ALSI = 404, - SystemZ_ALSIH = 405, - SystemZ_ALSIHN = 406, - SystemZ_ALY = 407, - SystemZ_AP = 408, - SystemZ_AR = 409, - SystemZ_ARK = 410, - SystemZ_ASI = 411, - SystemZ_AU = 412, - SystemZ_AUR = 413, - SystemZ_AW = 414, - SystemZ_AWR = 415, - SystemZ_AXBR = 416, - SystemZ_AXR = 417, - SystemZ_AXTR = 418, - SystemZ_AXTRA = 419, - SystemZ_AY = 420, - SystemZ_B = 421, - SystemZ_BAKR = 422, - SystemZ_BAL = 423, - SystemZ_BALR = 424, - SystemZ_BAS = 425, - SystemZ_BASR = 426, - SystemZ_BASSM = 427, - SystemZ_BAsmE = 428, - SystemZ_BAsmH = 429, - SystemZ_BAsmHE = 430, - SystemZ_BAsmL = 431, - SystemZ_BAsmLE = 432, - SystemZ_BAsmLH = 433, - SystemZ_BAsmM = 434, - SystemZ_BAsmNE = 435, - SystemZ_BAsmNH = 436, - SystemZ_BAsmNHE = 437, - SystemZ_BAsmNL = 438, - SystemZ_BAsmNLE = 439, - SystemZ_BAsmNLH = 440, - SystemZ_BAsmNM = 441, - SystemZ_BAsmNO = 442, - SystemZ_BAsmNP = 443, - SystemZ_BAsmNZ = 444, - SystemZ_BAsmO = 445, - SystemZ_BAsmP = 446, - SystemZ_BAsmZ = 447, - SystemZ_BC = 448, - SystemZ_BCAsm = 449, - SystemZ_BCR = 450, - SystemZ_BCRAsm = 451, - SystemZ_BCT = 452, - SystemZ_BCTG = 453, - SystemZ_BCTGR = 454, - SystemZ_BCTR = 455, - SystemZ_BI = 456, - SystemZ_BIAsmE = 457, - SystemZ_BIAsmH = 458, - SystemZ_BIAsmHE = 459, - SystemZ_BIAsmL = 460, - SystemZ_BIAsmLE = 461, - SystemZ_BIAsmLH = 462, - SystemZ_BIAsmM = 463, - SystemZ_BIAsmNE = 464, - SystemZ_BIAsmNH = 465, - SystemZ_BIAsmNHE = 466, - SystemZ_BIAsmNL = 467, - SystemZ_BIAsmNLE = 468, - SystemZ_BIAsmNLH = 469, - SystemZ_BIAsmNM = 470, - SystemZ_BIAsmNO = 471, - SystemZ_BIAsmNP = 472, - SystemZ_BIAsmNZ = 473, - SystemZ_BIAsmO = 474, - SystemZ_BIAsmP = 475, - SystemZ_BIAsmZ = 476, - SystemZ_BIC = 477, - SystemZ_BICAsm = 478, - SystemZ_BPP = 479, - SystemZ_BPRP = 480, - SystemZ_BR = 481, - SystemZ_BRAS = 482, - SystemZ_BRASL = 483, - SystemZ_BRAsmE = 484, - SystemZ_BRAsmH = 485, - SystemZ_BRAsmHE = 486, - SystemZ_BRAsmL = 487, - SystemZ_BRAsmLE = 488, - SystemZ_BRAsmLH = 489, - SystemZ_BRAsmM = 490, - SystemZ_BRAsmNE = 491, - SystemZ_BRAsmNH = 492, - SystemZ_BRAsmNHE = 493, - SystemZ_BRAsmNL = 494, - SystemZ_BRAsmNLE = 495, - SystemZ_BRAsmNLH = 496, - SystemZ_BRAsmNM = 497, - SystemZ_BRAsmNO = 498, - SystemZ_BRAsmNP = 499, - SystemZ_BRAsmNZ = 500, - SystemZ_BRAsmO = 501, - SystemZ_BRAsmP = 502, - SystemZ_BRAsmZ = 503, - SystemZ_BRC = 504, - SystemZ_BRCAsm = 505, - SystemZ_BRCL = 506, - SystemZ_BRCLAsm = 507, - SystemZ_BRCT = 508, - SystemZ_BRCTG = 509, - SystemZ_BRCTH = 510, - SystemZ_BRXH = 511, - SystemZ_BRXHG = 512, - SystemZ_BRXLE = 513, - SystemZ_BRXLG = 514, - SystemZ_BSA = 515, - SystemZ_BSG = 516, - SystemZ_BSM = 517, - SystemZ_BXH = 518, - SystemZ_BXHG = 519, - SystemZ_BXLE = 520, - SystemZ_BXLEG = 521, - SystemZ_C = 522, - SystemZ_CD = 523, - SystemZ_CDB = 524, - SystemZ_CDBR = 525, - SystemZ_CDFBR = 526, - SystemZ_CDFBRA = 527, - SystemZ_CDFR = 528, - SystemZ_CDFTR = 529, - SystemZ_CDGBR = 530, - SystemZ_CDGBRA = 531, - SystemZ_CDGR = 532, - SystemZ_CDGTR = 533, - SystemZ_CDGTRA = 534, - SystemZ_CDLFBR = 535, - SystemZ_CDLFTR = 536, - SystemZ_CDLGBR = 537, - SystemZ_CDLGTR = 538, - SystemZ_CDPT = 539, - SystemZ_CDR = 540, - SystemZ_CDS = 541, - SystemZ_CDSG = 542, - SystemZ_CDSTR = 543, - SystemZ_CDSY = 544, - SystemZ_CDTR = 545, - SystemZ_CDUTR = 546, - SystemZ_CDZT = 547, - SystemZ_CE = 548, - SystemZ_CEB = 549, - SystemZ_CEBR = 550, - SystemZ_CEDTR = 551, - SystemZ_CEFBR = 552, - SystemZ_CEFBRA = 553, - SystemZ_CEFR = 554, - SystemZ_CEGBR = 555, - SystemZ_CEGBRA = 556, - SystemZ_CEGR = 557, - SystemZ_CELFBR = 558, - SystemZ_CELGBR = 559, - SystemZ_CER = 560, - SystemZ_CEXTR = 561, - SystemZ_CFC = 562, - SystemZ_CFDBR = 563, - SystemZ_CFDBRA = 564, - SystemZ_CFDR = 565, - SystemZ_CFDTR = 566, - SystemZ_CFEBR = 567, - SystemZ_CFEBRA = 568, - SystemZ_CFER = 569, - SystemZ_CFI = 570, - SystemZ_CFXBR = 571, - SystemZ_CFXBRA = 572, - SystemZ_CFXR = 573, - SystemZ_CFXTR = 574, - SystemZ_CG = 575, - SystemZ_CGDBR = 576, - SystemZ_CGDBRA = 577, - SystemZ_CGDR = 578, - SystemZ_CGDTR = 579, - SystemZ_CGDTRA = 580, - SystemZ_CGEBR = 581, - SystemZ_CGEBRA = 582, - SystemZ_CGER = 583, - SystemZ_CGF = 584, - SystemZ_CGFI = 585, - SystemZ_CGFR = 586, - SystemZ_CGFRL = 587, - SystemZ_CGH = 588, - SystemZ_CGHI = 589, - SystemZ_CGHRL = 590, - SystemZ_CGHSI = 591, - SystemZ_CGIB = 592, - SystemZ_CGIBAsm = 593, - SystemZ_CGIBAsmE = 594, - SystemZ_CGIBAsmH = 595, - SystemZ_CGIBAsmHE = 596, - SystemZ_CGIBAsmL = 597, - SystemZ_CGIBAsmLE = 598, - SystemZ_CGIBAsmLH = 599, - SystemZ_CGIBAsmNE = 600, - SystemZ_CGIBAsmNH = 601, - SystemZ_CGIBAsmNHE = 602, - SystemZ_CGIBAsmNL = 603, - SystemZ_CGIBAsmNLE = 604, - SystemZ_CGIBAsmNLH = 605, - SystemZ_CGIJ = 606, - SystemZ_CGIJAsm = 607, - SystemZ_CGIJAsmE = 608, - SystemZ_CGIJAsmH = 609, - SystemZ_CGIJAsmHE = 610, - SystemZ_CGIJAsmL = 611, - SystemZ_CGIJAsmLE = 612, - SystemZ_CGIJAsmLH = 613, - SystemZ_CGIJAsmNE = 614, - SystemZ_CGIJAsmNH = 615, - SystemZ_CGIJAsmNHE = 616, - SystemZ_CGIJAsmNL = 617, - SystemZ_CGIJAsmNLE = 618, - SystemZ_CGIJAsmNLH = 619, - SystemZ_CGIT = 620, - SystemZ_CGITAsm = 621, - SystemZ_CGITAsmE = 622, - SystemZ_CGITAsmH = 623, - SystemZ_CGITAsmHE = 624, - SystemZ_CGITAsmL = 625, - SystemZ_CGITAsmLE = 626, - SystemZ_CGITAsmLH = 627, - SystemZ_CGITAsmNE = 628, - SystemZ_CGITAsmNH = 629, - SystemZ_CGITAsmNHE = 630, - SystemZ_CGITAsmNL = 631, - SystemZ_CGITAsmNLE = 632, - SystemZ_CGITAsmNLH = 633, - SystemZ_CGR = 634, - SystemZ_CGRB = 635, - SystemZ_CGRBAsm = 636, - SystemZ_CGRBAsmE = 637, - SystemZ_CGRBAsmH = 638, - SystemZ_CGRBAsmHE = 639, - SystemZ_CGRBAsmL = 640, - SystemZ_CGRBAsmLE = 641, - SystemZ_CGRBAsmLH = 642, - SystemZ_CGRBAsmNE = 643, - SystemZ_CGRBAsmNH = 644, - SystemZ_CGRBAsmNHE = 645, - SystemZ_CGRBAsmNL = 646, - SystemZ_CGRBAsmNLE = 647, - SystemZ_CGRBAsmNLH = 648, - SystemZ_CGRJ = 649, - SystemZ_CGRJAsm = 650, - SystemZ_CGRJAsmE = 651, - SystemZ_CGRJAsmH = 652, - SystemZ_CGRJAsmHE = 653, - SystemZ_CGRJAsmL = 654, - SystemZ_CGRJAsmLE = 655, - SystemZ_CGRJAsmLH = 656, - SystemZ_CGRJAsmNE = 657, - SystemZ_CGRJAsmNH = 658, - SystemZ_CGRJAsmNHE = 659, - SystemZ_CGRJAsmNL = 660, - SystemZ_CGRJAsmNLE = 661, - SystemZ_CGRJAsmNLH = 662, - SystemZ_CGRL = 663, - SystemZ_CGRT = 664, - SystemZ_CGRTAsm = 665, - SystemZ_CGRTAsmE = 666, - SystemZ_CGRTAsmH = 667, - SystemZ_CGRTAsmHE = 668, - SystemZ_CGRTAsmL = 669, - SystemZ_CGRTAsmLE = 670, - SystemZ_CGRTAsmLH = 671, - SystemZ_CGRTAsmNE = 672, - SystemZ_CGRTAsmNH = 673, - SystemZ_CGRTAsmNHE = 674, - SystemZ_CGRTAsmNL = 675, - SystemZ_CGRTAsmNLE = 676, - SystemZ_CGRTAsmNLH = 677, - SystemZ_CGXBR = 678, - SystemZ_CGXBRA = 679, - SystemZ_CGXR = 680, - SystemZ_CGXTR = 681, - SystemZ_CGXTRA = 682, - SystemZ_CH = 683, - SystemZ_CHF = 684, - SystemZ_CHHR = 685, - SystemZ_CHHSI = 686, - SystemZ_CHI = 687, - SystemZ_CHLR = 688, - SystemZ_CHRL = 689, - SystemZ_CHSI = 690, - SystemZ_CHY = 691, - SystemZ_CIB = 692, - SystemZ_CIBAsm = 693, - SystemZ_CIBAsmE = 694, - SystemZ_CIBAsmH = 695, - SystemZ_CIBAsmHE = 696, - SystemZ_CIBAsmL = 697, - SystemZ_CIBAsmLE = 698, - SystemZ_CIBAsmLH = 699, - SystemZ_CIBAsmNE = 700, - SystemZ_CIBAsmNH = 701, - SystemZ_CIBAsmNHE = 702, - SystemZ_CIBAsmNL = 703, - SystemZ_CIBAsmNLE = 704, - SystemZ_CIBAsmNLH = 705, - SystemZ_CIH = 706, - SystemZ_CIJ = 707, - SystemZ_CIJAsm = 708, - SystemZ_CIJAsmE = 709, - SystemZ_CIJAsmH = 710, - SystemZ_CIJAsmHE = 711, - SystemZ_CIJAsmL = 712, - SystemZ_CIJAsmLE = 713, - SystemZ_CIJAsmLH = 714, - SystemZ_CIJAsmNE = 715, - SystemZ_CIJAsmNH = 716, - SystemZ_CIJAsmNHE = 717, - SystemZ_CIJAsmNL = 718, - SystemZ_CIJAsmNLE = 719, - SystemZ_CIJAsmNLH = 720, - SystemZ_CIT = 721, - SystemZ_CITAsm = 722, - SystemZ_CITAsmE = 723, - SystemZ_CITAsmH = 724, - SystemZ_CITAsmHE = 725, - SystemZ_CITAsmL = 726, - SystemZ_CITAsmLE = 727, - SystemZ_CITAsmLH = 728, - SystemZ_CITAsmNE = 729, - SystemZ_CITAsmNH = 730, - SystemZ_CITAsmNHE = 731, - SystemZ_CITAsmNL = 732, - SystemZ_CITAsmNLE = 733, - SystemZ_CITAsmNLH = 734, - SystemZ_CKSM = 735, - SystemZ_CL = 736, - SystemZ_CLC = 737, - SystemZ_CLCL = 738, - SystemZ_CLCLE = 739, - SystemZ_CLCLU = 740, - SystemZ_CLFDBR = 741, - SystemZ_CLFDTR = 742, - SystemZ_CLFEBR = 743, - SystemZ_CLFHSI = 744, - SystemZ_CLFI = 745, - SystemZ_CLFIT = 746, - SystemZ_CLFITAsm = 747, - SystemZ_CLFITAsmE = 748, - SystemZ_CLFITAsmH = 749, - SystemZ_CLFITAsmHE = 750, - SystemZ_CLFITAsmL = 751, - SystemZ_CLFITAsmLE = 752, - SystemZ_CLFITAsmLH = 753, - SystemZ_CLFITAsmNE = 754, - SystemZ_CLFITAsmNH = 755, - SystemZ_CLFITAsmNHE = 756, - SystemZ_CLFITAsmNL = 757, - SystemZ_CLFITAsmNLE = 758, - SystemZ_CLFITAsmNLH = 759, - SystemZ_CLFXBR = 760, - SystemZ_CLFXTR = 761, - SystemZ_CLG = 762, - SystemZ_CLGDBR = 763, - SystemZ_CLGDTR = 764, - SystemZ_CLGEBR = 765, - SystemZ_CLGF = 766, - SystemZ_CLGFI = 767, - SystemZ_CLGFR = 768, - SystemZ_CLGFRL = 769, - SystemZ_CLGHRL = 770, - SystemZ_CLGHSI = 771, - SystemZ_CLGIB = 772, - SystemZ_CLGIBAsm = 773, - SystemZ_CLGIBAsmE = 774, - SystemZ_CLGIBAsmH = 775, - SystemZ_CLGIBAsmHE = 776, - SystemZ_CLGIBAsmL = 777, - SystemZ_CLGIBAsmLE = 778, - SystemZ_CLGIBAsmLH = 779, - SystemZ_CLGIBAsmNE = 780, - SystemZ_CLGIBAsmNH = 781, - SystemZ_CLGIBAsmNHE = 782, - SystemZ_CLGIBAsmNL = 783, - SystemZ_CLGIBAsmNLE = 784, - SystemZ_CLGIBAsmNLH = 785, - SystemZ_CLGIJ = 786, - SystemZ_CLGIJAsm = 787, - SystemZ_CLGIJAsmE = 788, - SystemZ_CLGIJAsmH = 789, - SystemZ_CLGIJAsmHE = 790, - SystemZ_CLGIJAsmL = 791, - SystemZ_CLGIJAsmLE = 792, - SystemZ_CLGIJAsmLH = 793, - SystemZ_CLGIJAsmNE = 794, - SystemZ_CLGIJAsmNH = 795, - SystemZ_CLGIJAsmNHE = 796, - SystemZ_CLGIJAsmNL = 797, - SystemZ_CLGIJAsmNLE = 798, - SystemZ_CLGIJAsmNLH = 799, - SystemZ_CLGIT = 800, - SystemZ_CLGITAsm = 801, - SystemZ_CLGITAsmE = 802, - SystemZ_CLGITAsmH = 803, - SystemZ_CLGITAsmHE = 804, - SystemZ_CLGITAsmL = 805, - SystemZ_CLGITAsmLE = 806, - SystemZ_CLGITAsmLH = 807, - SystemZ_CLGITAsmNE = 808, - SystemZ_CLGITAsmNH = 809, - SystemZ_CLGITAsmNHE = 810, - SystemZ_CLGITAsmNL = 811, - SystemZ_CLGITAsmNLE = 812, - SystemZ_CLGITAsmNLH = 813, - SystemZ_CLGR = 814, - SystemZ_CLGRB = 815, - SystemZ_CLGRBAsm = 816, - SystemZ_CLGRBAsmE = 817, - SystemZ_CLGRBAsmH = 818, - SystemZ_CLGRBAsmHE = 819, - SystemZ_CLGRBAsmL = 820, - SystemZ_CLGRBAsmLE = 821, - SystemZ_CLGRBAsmLH = 822, - SystemZ_CLGRBAsmNE = 823, - SystemZ_CLGRBAsmNH = 824, - SystemZ_CLGRBAsmNHE = 825, - SystemZ_CLGRBAsmNL = 826, - SystemZ_CLGRBAsmNLE = 827, - SystemZ_CLGRBAsmNLH = 828, - SystemZ_CLGRJ = 829, - SystemZ_CLGRJAsm = 830, - SystemZ_CLGRJAsmE = 831, - SystemZ_CLGRJAsmH = 832, - SystemZ_CLGRJAsmHE = 833, - SystemZ_CLGRJAsmL = 834, - SystemZ_CLGRJAsmLE = 835, - SystemZ_CLGRJAsmLH = 836, - SystemZ_CLGRJAsmNE = 837, - SystemZ_CLGRJAsmNH = 838, - SystemZ_CLGRJAsmNHE = 839, - SystemZ_CLGRJAsmNL = 840, - SystemZ_CLGRJAsmNLE = 841, - SystemZ_CLGRJAsmNLH = 842, - SystemZ_CLGRL = 843, - SystemZ_CLGRT = 844, - SystemZ_CLGRTAsm = 845, - SystemZ_CLGRTAsmE = 846, - SystemZ_CLGRTAsmH = 847, - SystemZ_CLGRTAsmHE = 848, - SystemZ_CLGRTAsmL = 849, - SystemZ_CLGRTAsmLE = 850, - SystemZ_CLGRTAsmLH = 851, - SystemZ_CLGRTAsmNE = 852, - SystemZ_CLGRTAsmNH = 853, - SystemZ_CLGRTAsmNHE = 854, - SystemZ_CLGRTAsmNL = 855, - SystemZ_CLGRTAsmNLE = 856, - SystemZ_CLGRTAsmNLH = 857, - SystemZ_CLGT = 858, - SystemZ_CLGTAsm = 859, - SystemZ_CLGTAsmE = 860, - SystemZ_CLGTAsmH = 861, - SystemZ_CLGTAsmHE = 862, - SystemZ_CLGTAsmL = 863, - SystemZ_CLGTAsmLE = 864, - SystemZ_CLGTAsmLH = 865, - SystemZ_CLGTAsmNE = 866, - SystemZ_CLGTAsmNH = 867, - SystemZ_CLGTAsmNHE = 868, - SystemZ_CLGTAsmNL = 869, - SystemZ_CLGTAsmNLE = 870, - SystemZ_CLGTAsmNLH = 871, - SystemZ_CLGXBR = 872, - SystemZ_CLGXTR = 873, - SystemZ_CLHF = 874, - SystemZ_CLHHR = 875, - SystemZ_CLHHSI = 876, - SystemZ_CLHLR = 877, - SystemZ_CLHRL = 878, - SystemZ_CLI = 879, - SystemZ_CLIB = 880, - SystemZ_CLIBAsm = 881, - SystemZ_CLIBAsmE = 882, - SystemZ_CLIBAsmH = 883, - SystemZ_CLIBAsmHE = 884, - SystemZ_CLIBAsmL = 885, - SystemZ_CLIBAsmLE = 886, - SystemZ_CLIBAsmLH = 887, - SystemZ_CLIBAsmNE = 888, - SystemZ_CLIBAsmNH = 889, - SystemZ_CLIBAsmNHE = 890, - SystemZ_CLIBAsmNL = 891, - SystemZ_CLIBAsmNLE = 892, - SystemZ_CLIBAsmNLH = 893, - SystemZ_CLIH = 894, - SystemZ_CLIJ = 895, - SystemZ_CLIJAsm = 896, - SystemZ_CLIJAsmE = 897, - SystemZ_CLIJAsmH = 898, - SystemZ_CLIJAsmHE = 899, - SystemZ_CLIJAsmL = 900, - SystemZ_CLIJAsmLE = 901, - SystemZ_CLIJAsmLH = 902, - SystemZ_CLIJAsmNE = 903, - SystemZ_CLIJAsmNH = 904, - SystemZ_CLIJAsmNHE = 905, - SystemZ_CLIJAsmNL = 906, - SystemZ_CLIJAsmNLE = 907, - SystemZ_CLIJAsmNLH = 908, - SystemZ_CLIY = 909, - SystemZ_CLM = 910, - SystemZ_CLMH = 911, - SystemZ_CLMY = 912, - SystemZ_CLR = 913, - SystemZ_CLRB = 914, - SystemZ_CLRBAsm = 915, - SystemZ_CLRBAsmE = 916, - SystemZ_CLRBAsmH = 917, - SystemZ_CLRBAsmHE = 918, - SystemZ_CLRBAsmL = 919, - SystemZ_CLRBAsmLE = 920, - SystemZ_CLRBAsmLH = 921, - SystemZ_CLRBAsmNE = 922, - SystemZ_CLRBAsmNH = 923, - SystemZ_CLRBAsmNHE = 924, - SystemZ_CLRBAsmNL = 925, - SystemZ_CLRBAsmNLE = 926, - SystemZ_CLRBAsmNLH = 927, - SystemZ_CLRJ = 928, - SystemZ_CLRJAsm = 929, - SystemZ_CLRJAsmE = 930, - SystemZ_CLRJAsmH = 931, - SystemZ_CLRJAsmHE = 932, - SystemZ_CLRJAsmL = 933, - SystemZ_CLRJAsmLE = 934, - SystemZ_CLRJAsmLH = 935, - SystemZ_CLRJAsmNE = 936, - SystemZ_CLRJAsmNH = 937, - SystemZ_CLRJAsmNHE = 938, - SystemZ_CLRJAsmNL = 939, - SystemZ_CLRJAsmNLE = 940, - SystemZ_CLRJAsmNLH = 941, - SystemZ_CLRL = 942, - SystemZ_CLRT = 943, - SystemZ_CLRTAsm = 944, - SystemZ_CLRTAsmE = 945, - SystemZ_CLRTAsmH = 946, - SystemZ_CLRTAsmHE = 947, - SystemZ_CLRTAsmL = 948, - SystemZ_CLRTAsmLE = 949, - SystemZ_CLRTAsmLH = 950, - SystemZ_CLRTAsmNE = 951, - SystemZ_CLRTAsmNH = 952, - SystemZ_CLRTAsmNHE = 953, - SystemZ_CLRTAsmNL = 954, - SystemZ_CLRTAsmNLE = 955, - SystemZ_CLRTAsmNLH = 956, - SystemZ_CLST = 957, - SystemZ_CLT = 958, - SystemZ_CLTAsm = 959, - SystemZ_CLTAsmE = 960, - SystemZ_CLTAsmH = 961, - SystemZ_CLTAsmHE = 962, - SystemZ_CLTAsmL = 963, - SystemZ_CLTAsmLE = 964, - SystemZ_CLTAsmLH = 965, - SystemZ_CLTAsmNE = 966, - SystemZ_CLTAsmNH = 967, - SystemZ_CLTAsmNHE = 968, - SystemZ_CLTAsmNL = 969, - SystemZ_CLTAsmNLE = 970, - SystemZ_CLTAsmNLH = 971, - SystemZ_CLY = 972, - SystemZ_CMPSC = 973, - SystemZ_CP = 974, - SystemZ_CPDT = 975, - SystemZ_CPSDRdd = 976, - SystemZ_CPSDRds = 977, - SystemZ_CPSDRsd = 978, - SystemZ_CPSDRss = 979, - SystemZ_CPXT = 980, - SystemZ_CPYA = 981, - SystemZ_CR = 982, - SystemZ_CRB = 983, - SystemZ_CRBAsm = 984, - SystemZ_CRBAsmE = 985, - SystemZ_CRBAsmH = 986, - SystemZ_CRBAsmHE = 987, - SystemZ_CRBAsmL = 988, - SystemZ_CRBAsmLE = 989, - SystemZ_CRBAsmLH = 990, - SystemZ_CRBAsmNE = 991, - SystemZ_CRBAsmNH = 992, - SystemZ_CRBAsmNHE = 993, - SystemZ_CRBAsmNL = 994, - SystemZ_CRBAsmNLE = 995, - SystemZ_CRBAsmNLH = 996, - SystemZ_CRDTE = 997, - SystemZ_CRDTEOpt = 998, - SystemZ_CRJ = 999, - SystemZ_CRJAsm = 1000, - SystemZ_CRJAsmE = 1001, - SystemZ_CRJAsmH = 1002, - SystemZ_CRJAsmHE = 1003, - SystemZ_CRJAsmL = 1004, - SystemZ_CRJAsmLE = 1005, - SystemZ_CRJAsmLH = 1006, - SystemZ_CRJAsmNE = 1007, - SystemZ_CRJAsmNH = 1008, - SystemZ_CRJAsmNHE = 1009, - SystemZ_CRJAsmNL = 1010, - SystemZ_CRJAsmNLE = 1011, - SystemZ_CRJAsmNLH = 1012, - SystemZ_CRL = 1013, - SystemZ_CRT = 1014, - SystemZ_CRTAsm = 1015, - SystemZ_CRTAsmE = 1016, - SystemZ_CRTAsmH = 1017, - SystemZ_CRTAsmHE = 1018, - SystemZ_CRTAsmL = 1019, - SystemZ_CRTAsmLE = 1020, - SystemZ_CRTAsmLH = 1021, - SystemZ_CRTAsmNE = 1022, - SystemZ_CRTAsmNH = 1023, - SystemZ_CRTAsmNHE = 1024, - SystemZ_CRTAsmNL = 1025, - SystemZ_CRTAsmNLE = 1026, - SystemZ_CRTAsmNLH = 1027, - SystemZ_CS = 1028, - SystemZ_CSCH = 1029, - SystemZ_CSDTR = 1030, - SystemZ_CSG = 1031, - SystemZ_CSP = 1032, - SystemZ_CSPG = 1033, - SystemZ_CSST = 1034, - SystemZ_CSXTR = 1035, - SystemZ_CSY = 1036, - SystemZ_CU12 = 1037, - SystemZ_CU12Opt = 1038, - SystemZ_CU14 = 1039, - SystemZ_CU14Opt = 1040, - SystemZ_CU21 = 1041, - SystemZ_CU21Opt = 1042, - SystemZ_CU24 = 1043, - SystemZ_CU24Opt = 1044, - SystemZ_CU41 = 1045, - SystemZ_CU42 = 1046, - SystemZ_CUDTR = 1047, - SystemZ_CUSE = 1048, - SystemZ_CUTFU = 1049, - SystemZ_CUTFUOpt = 1050, - SystemZ_CUUTF = 1051, - SystemZ_CUUTFOpt = 1052, - SystemZ_CUXTR = 1053, - SystemZ_CVB = 1054, - SystemZ_CVBG = 1055, - SystemZ_CVBY = 1056, - SystemZ_CVD = 1057, - SystemZ_CVDG = 1058, - SystemZ_CVDY = 1059, - SystemZ_CXBR = 1060, - SystemZ_CXFBR = 1061, - SystemZ_CXFBRA = 1062, - SystemZ_CXFR = 1063, - SystemZ_CXFTR = 1064, - SystemZ_CXGBR = 1065, - SystemZ_CXGBRA = 1066, - SystemZ_CXGR = 1067, - SystemZ_CXGTR = 1068, - SystemZ_CXGTRA = 1069, - SystemZ_CXLFBR = 1070, - SystemZ_CXLFTR = 1071, - SystemZ_CXLGBR = 1072, - SystemZ_CXLGTR = 1073, - SystemZ_CXPT = 1074, - SystemZ_CXR = 1075, - SystemZ_CXSTR = 1076, - SystemZ_CXTR = 1077, - SystemZ_CXUTR = 1078, - SystemZ_CXZT = 1079, - SystemZ_CY = 1080, - SystemZ_CZDT = 1081, - SystemZ_CZXT = 1082, - SystemZ_D = 1083, - SystemZ_DD = 1084, - SystemZ_DDB = 1085, - SystemZ_DDBR = 1086, - SystemZ_DDR = 1087, - SystemZ_DDTR = 1088, - SystemZ_DDTRA = 1089, - SystemZ_DE = 1090, - SystemZ_DEB = 1091, - SystemZ_DEBR = 1092, - SystemZ_DER = 1093, - SystemZ_DIAG = 1094, - SystemZ_DIDBR = 1095, - SystemZ_DIEBR = 1096, - SystemZ_DL = 1097, - SystemZ_DLG = 1098, - SystemZ_DLGR = 1099, - SystemZ_DLR = 1100, - SystemZ_DP = 1101, - SystemZ_DR = 1102, - SystemZ_DSG = 1103, - SystemZ_DSGF = 1104, - SystemZ_DSGFR = 1105, - SystemZ_DSGR = 1106, - SystemZ_DXBR = 1107, - SystemZ_DXR = 1108, - SystemZ_DXTR = 1109, - SystemZ_DXTRA = 1110, - SystemZ_EAR = 1111, - SystemZ_ECAG = 1112, - SystemZ_ECCTR = 1113, - SystemZ_ECPGA = 1114, - SystemZ_ECTG = 1115, - SystemZ_ED = 1116, - SystemZ_EDMK = 1117, - SystemZ_EEDTR = 1118, - SystemZ_EEXTR = 1119, - SystemZ_EFPC = 1120, - SystemZ_EPAIR = 1121, - SystemZ_EPAR = 1122, - SystemZ_EPCTR = 1123, - SystemZ_EPSW = 1124, - SystemZ_EREG = 1125, - SystemZ_EREGG = 1126, - SystemZ_ESAIR = 1127, - SystemZ_ESAR = 1128, - SystemZ_ESDTR = 1129, - SystemZ_ESEA = 1130, - SystemZ_ESTA = 1131, - SystemZ_ESXTR = 1132, - SystemZ_ETND = 1133, - SystemZ_EX = 1134, - SystemZ_EXRL = 1135, - SystemZ_FIDBR = 1136, - SystemZ_FIDBRA = 1137, - SystemZ_FIDR = 1138, - SystemZ_FIDTR = 1139, - SystemZ_FIEBR = 1140, - SystemZ_FIEBRA = 1141, - SystemZ_FIER = 1142, - SystemZ_FIXBR = 1143, - SystemZ_FIXBRA = 1144, - SystemZ_FIXR = 1145, - SystemZ_FIXTR = 1146, - SystemZ_FLOGR = 1147, - SystemZ_HDR = 1148, - SystemZ_HER = 1149, - SystemZ_HSCH = 1150, - SystemZ_IAC = 1151, - SystemZ_IC = 1152, - SystemZ_IC32 = 1153, - SystemZ_IC32Y = 1154, - SystemZ_ICM = 1155, - SystemZ_ICMH = 1156, - SystemZ_ICMY = 1157, - SystemZ_ICY = 1158, - SystemZ_IDTE = 1159, - SystemZ_IDTEOpt = 1160, - SystemZ_IEDTR = 1161, - SystemZ_IEXTR = 1162, - SystemZ_IIHF = 1163, - SystemZ_IIHH = 1164, - SystemZ_IIHL = 1165, - SystemZ_IILF = 1166, - SystemZ_IILH = 1167, - SystemZ_IILL = 1168, - SystemZ_IPK = 1169, - SystemZ_IPM = 1170, - SystemZ_IPTE = 1171, - SystemZ_IPTEOpt = 1172, - SystemZ_IPTEOptOpt = 1173, - SystemZ_IRBM = 1174, - SystemZ_ISKE = 1175, - SystemZ_IVSK = 1176, - SystemZ_InsnE = 1177, - SystemZ_InsnRI = 1178, - SystemZ_InsnRIE = 1179, - SystemZ_InsnRIL = 1180, - SystemZ_InsnRILU = 1181, - SystemZ_InsnRIS = 1182, - SystemZ_InsnRR = 1183, - SystemZ_InsnRRE = 1184, - SystemZ_InsnRRF = 1185, - SystemZ_InsnRRS = 1186, - SystemZ_InsnRS = 1187, - SystemZ_InsnRSE = 1188, - SystemZ_InsnRSI = 1189, - SystemZ_InsnRSY = 1190, - SystemZ_InsnRX = 1191, - SystemZ_InsnRXE = 1192, - SystemZ_InsnRXF = 1193, - SystemZ_InsnRXY = 1194, - SystemZ_InsnS = 1195, - SystemZ_InsnSI = 1196, - SystemZ_InsnSIL = 1197, - SystemZ_InsnSIY = 1198, - SystemZ_InsnSS = 1199, - SystemZ_InsnSSE = 1200, - SystemZ_InsnSSF = 1201, - SystemZ_J = 1202, - SystemZ_JAsmE = 1203, - SystemZ_JAsmH = 1204, - SystemZ_JAsmHE = 1205, - SystemZ_JAsmL = 1206, - SystemZ_JAsmLE = 1207, - SystemZ_JAsmLH = 1208, - SystemZ_JAsmM = 1209, - SystemZ_JAsmNE = 1210, - SystemZ_JAsmNH = 1211, - SystemZ_JAsmNHE = 1212, - SystemZ_JAsmNL = 1213, - SystemZ_JAsmNLE = 1214, - SystemZ_JAsmNLH = 1215, - SystemZ_JAsmNM = 1216, - SystemZ_JAsmNO = 1217, - SystemZ_JAsmNP = 1218, - SystemZ_JAsmNZ = 1219, - SystemZ_JAsmO = 1220, - SystemZ_JAsmP = 1221, - SystemZ_JAsmZ = 1222, - SystemZ_JG = 1223, - SystemZ_JGAsmE = 1224, - SystemZ_JGAsmH = 1225, - SystemZ_JGAsmHE = 1226, - SystemZ_JGAsmL = 1227, - SystemZ_JGAsmLE = 1228, - SystemZ_JGAsmLH = 1229, - SystemZ_JGAsmM = 1230, - SystemZ_JGAsmNE = 1231, - SystemZ_JGAsmNH = 1232, - SystemZ_JGAsmNHE = 1233, - SystemZ_JGAsmNL = 1234, - SystemZ_JGAsmNLE = 1235, - SystemZ_JGAsmNLH = 1236, - SystemZ_JGAsmNM = 1237, - SystemZ_JGAsmNO = 1238, - SystemZ_JGAsmNP = 1239, - SystemZ_JGAsmNZ = 1240, - SystemZ_JGAsmO = 1241, - SystemZ_JGAsmP = 1242, - SystemZ_JGAsmZ = 1243, - SystemZ_KDB = 1244, - SystemZ_KDBR = 1245, - SystemZ_KDTR = 1246, - SystemZ_KEB = 1247, - SystemZ_KEBR = 1248, - SystemZ_KIMD = 1249, - SystemZ_KLMD = 1250, - SystemZ_KM = 1251, - SystemZ_KMA = 1252, - SystemZ_KMAC = 1253, - SystemZ_KMC = 1254, - SystemZ_KMCTR = 1255, - SystemZ_KMF = 1256, - SystemZ_KMO = 1257, - SystemZ_KXBR = 1258, - SystemZ_KXTR = 1259, - SystemZ_L = 1260, - SystemZ_LA = 1261, - SystemZ_LAA = 1262, - SystemZ_LAAG = 1263, - SystemZ_LAAL = 1264, - SystemZ_LAALG = 1265, - SystemZ_LAE = 1266, - SystemZ_LAEY = 1267, - SystemZ_LAM = 1268, - SystemZ_LAMY = 1269, - SystemZ_LAN = 1270, - SystemZ_LANG = 1271, - SystemZ_LAO = 1272, - SystemZ_LAOG = 1273, - SystemZ_LARL = 1274, - SystemZ_LASP = 1275, - SystemZ_LAT = 1276, - SystemZ_LAX = 1277, - SystemZ_LAXG = 1278, - SystemZ_LAY = 1279, - SystemZ_LB = 1280, - SystemZ_LBH = 1281, - SystemZ_LBR = 1282, - SystemZ_LCBB = 1283, - SystemZ_LCCTL = 1284, - SystemZ_LCDBR = 1285, - SystemZ_LCDFR = 1286, - SystemZ_LCDFR_32 = 1287, - SystemZ_LCDR = 1288, - SystemZ_LCEBR = 1289, - SystemZ_LCER = 1290, - SystemZ_LCGFR = 1291, - SystemZ_LCGR = 1292, - SystemZ_LCR = 1293, - SystemZ_LCTL = 1294, - SystemZ_LCTLG = 1295, - SystemZ_LCXBR = 1296, - SystemZ_LCXR = 1297, - SystemZ_LD = 1298, - SystemZ_LDE = 1299, - SystemZ_LDE32 = 1300, - SystemZ_LDEB = 1301, - SystemZ_LDEBR = 1302, - SystemZ_LDER = 1303, - SystemZ_LDETR = 1304, - SystemZ_LDGR = 1305, - SystemZ_LDR = 1306, - SystemZ_LDR32 = 1307, - SystemZ_LDXBR = 1308, - SystemZ_LDXBRA = 1309, - SystemZ_LDXR = 1310, - SystemZ_LDXTR = 1311, - SystemZ_LDY = 1312, - SystemZ_LE = 1313, - SystemZ_LEDBR = 1314, - SystemZ_LEDBRA = 1315, - SystemZ_LEDR = 1316, - SystemZ_LEDTR = 1317, - SystemZ_LER = 1318, - SystemZ_LEXBR = 1319, - SystemZ_LEXBRA = 1320, - SystemZ_LEXR = 1321, - SystemZ_LEY = 1322, - SystemZ_LFAS = 1323, - SystemZ_LFH = 1324, - SystemZ_LFHAT = 1325, - SystemZ_LFPC = 1326, - SystemZ_LG = 1327, - SystemZ_LGAT = 1328, - SystemZ_LGB = 1329, - SystemZ_LGBR = 1330, - SystemZ_LGDR = 1331, - SystemZ_LGF = 1332, - SystemZ_LGFI = 1333, - SystemZ_LGFR = 1334, - SystemZ_LGFRL = 1335, - SystemZ_LGG = 1336, - SystemZ_LGH = 1337, - SystemZ_LGHI = 1338, - SystemZ_LGHR = 1339, - SystemZ_LGHRL = 1340, - SystemZ_LGR = 1341, - SystemZ_LGRL = 1342, - SystemZ_LGSC = 1343, - SystemZ_LH = 1344, - SystemZ_LHH = 1345, - SystemZ_LHI = 1346, - SystemZ_LHR = 1347, - SystemZ_LHRL = 1348, - SystemZ_LHY = 1349, - SystemZ_LLC = 1350, - SystemZ_LLCH = 1351, - SystemZ_LLCR = 1352, - SystemZ_LLGC = 1353, - SystemZ_LLGCR = 1354, - SystemZ_LLGF = 1355, - SystemZ_LLGFAT = 1356, - SystemZ_LLGFR = 1357, - SystemZ_LLGFRL = 1358, - SystemZ_LLGFSG = 1359, - SystemZ_LLGH = 1360, - SystemZ_LLGHR = 1361, - SystemZ_LLGHRL = 1362, - SystemZ_LLGT = 1363, - SystemZ_LLGTAT = 1364, - SystemZ_LLGTR = 1365, - SystemZ_LLH = 1366, - SystemZ_LLHH = 1367, - SystemZ_LLHR = 1368, - SystemZ_LLHRL = 1369, - SystemZ_LLIHF = 1370, - SystemZ_LLIHH = 1371, - SystemZ_LLIHL = 1372, - SystemZ_LLILF = 1373, - SystemZ_LLILH = 1374, - SystemZ_LLILL = 1375, - SystemZ_LLZRGF = 1376, - SystemZ_LM = 1377, - SystemZ_LMD = 1378, - SystemZ_LMG = 1379, - SystemZ_LMH = 1380, - SystemZ_LMY = 1381, - SystemZ_LNDBR = 1382, - SystemZ_LNDFR = 1383, - SystemZ_LNDFR_32 = 1384, - SystemZ_LNDR = 1385, - SystemZ_LNEBR = 1386, - SystemZ_LNER = 1387, - SystemZ_LNGFR = 1388, - SystemZ_LNGR = 1389, - SystemZ_LNR = 1390, - SystemZ_LNXBR = 1391, - SystemZ_LNXR = 1392, - SystemZ_LOC = 1393, - SystemZ_LOCAsm = 1394, - SystemZ_LOCAsmE = 1395, - SystemZ_LOCAsmH = 1396, - SystemZ_LOCAsmHE = 1397, - SystemZ_LOCAsmL = 1398, - SystemZ_LOCAsmLE = 1399, - SystemZ_LOCAsmLH = 1400, - SystemZ_LOCAsmM = 1401, - SystemZ_LOCAsmNE = 1402, - SystemZ_LOCAsmNH = 1403, - SystemZ_LOCAsmNHE = 1404, - SystemZ_LOCAsmNL = 1405, - SystemZ_LOCAsmNLE = 1406, - SystemZ_LOCAsmNLH = 1407, - SystemZ_LOCAsmNM = 1408, - SystemZ_LOCAsmNO = 1409, - SystemZ_LOCAsmNP = 1410, - SystemZ_LOCAsmNZ = 1411, - SystemZ_LOCAsmO = 1412, - SystemZ_LOCAsmP = 1413, - SystemZ_LOCAsmZ = 1414, - SystemZ_LOCFH = 1415, - SystemZ_LOCFHAsm = 1416, - SystemZ_LOCFHAsmE = 1417, - SystemZ_LOCFHAsmH = 1418, - SystemZ_LOCFHAsmHE = 1419, - SystemZ_LOCFHAsmL = 1420, - SystemZ_LOCFHAsmLE = 1421, - SystemZ_LOCFHAsmLH = 1422, - SystemZ_LOCFHAsmM = 1423, - SystemZ_LOCFHAsmNE = 1424, - SystemZ_LOCFHAsmNH = 1425, - SystemZ_LOCFHAsmNHE = 1426, - SystemZ_LOCFHAsmNL = 1427, - SystemZ_LOCFHAsmNLE = 1428, - SystemZ_LOCFHAsmNLH = 1429, - SystemZ_LOCFHAsmNM = 1430, - SystemZ_LOCFHAsmNO = 1431, - SystemZ_LOCFHAsmNP = 1432, - SystemZ_LOCFHAsmNZ = 1433, - SystemZ_LOCFHAsmO = 1434, - SystemZ_LOCFHAsmP = 1435, - SystemZ_LOCFHAsmZ = 1436, - SystemZ_LOCFHR = 1437, - SystemZ_LOCFHRAsm = 1438, - SystemZ_LOCFHRAsmE = 1439, - SystemZ_LOCFHRAsmH = 1440, - SystemZ_LOCFHRAsmHE = 1441, - SystemZ_LOCFHRAsmL = 1442, - SystemZ_LOCFHRAsmLE = 1443, - SystemZ_LOCFHRAsmLH = 1444, - SystemZ_LOCFHRAsmM = 1445, - SystemZ_LOCFHRAsmNE = 1446, - SystemZ_LOCFHRAsmNH = 1447, - SystemZ_LOCFHRAsmNHE = 1448, - SystemZ_LOCFHRAsmNL = 1449, - SystemZ_LOCFHRAsmNLE = 1450, - SystemZ_LOCFHRAsmNLH = 1451, - SystemZ_LOCFHRAsmNM = 1452, - SystemZ_LOCFHRAsmNO = 1453, - SystemZ_LOCFHRAsmNP = 1454, - SystemZ_LOCFHRAsmNZ = 1455, - SystemZ_LOCFHRAsmO = 1456, - SystemZ_LOCFHRAsmP = 1457, - SystemZ_LOCFHRAsmZ = 1458, - SystemZ_LOCG = 1459, - SystemZ_LOCGAsm = 1460, - SystemZ_LOCGAsmE = 1461, - SystemZ_LOCGAsmH = 1462, - SystemZ_LOCGAsmHE = 1463, - SystemZ_LOCGAsmL = 1464, - SystemZ_LOCGAsmLE = 1465, - SystemZ_LOCGAsmLH = 1466, - SystemZ_LOCGAsmM = 1467, - SystemZ_LOCGAsmNE = 1468, - SystemZ_LOCGAsmNH = 1469, - SystemZ_LOCGAsmNHE = 1470, - SystemZ_LOCGAsmNL = 1471, - SystemZ_LOCGAsmNLE = 1472, - SystemZ_LOCGAsmNLH = 1473, - SystemZ_LOCGAsmNM = 1474, - SystemZ_LOCGAsmNO = 1475, - SystemZ_LOCGAsmNP = 1476, - SystemZ_LOCGAsmNZ = 1477, - SystemZ_LOCGAsmO = 1478, - SystemZ_LOCGAsmP = 1479, - SystemZ_LOCGAsmZ = 1480, - SystemZ_LOCGHI = 1481, - SystemZ_LOCGHIAsm = 1482, - SystemZ_LOCGHIAsmE = 1483, - SystemZ_LOCGHIAsmH = 1484, - SystemZ_LOCGHIAsmHE = 1485, - SystemZ_LOCGHIAsmL = 1486, - SystemZ_LOCGHIAsmLE = 1487, - SystemZ_LOCGHIAsmLH = 1488, - SystemZ_LOCGHIAsmM = 1489, - SystemZ_LOCGHIAsmNE = 1490, - SystemZ_LOCGHIAsmNH = 1491, - SystemZ_LOCGHIAsmNHE = 1492, - SystemZ_LOCGHIAsmNL = 1493, - SystemZ_LOCGHIAsmNLE = 1494, - SystemZ_LOCGHIAsmNLH = 1495, - SystemZ_LOCGHIAsmNM = 1496, - SystemZ_LOCGHIAsmNO = 1497, - SystemZ_LOCGHIAsmNP = 1498, - SystemZ_LOCGHIAsmNZ = 1499, - SystemZ_LOCGHIAsmO = 1500, - SystemZ_LOCGHIAsmP = 1501, - SystemZ_LOCGHIAsmZ = 1502, - SystemZ_LOCGR = 1503, - SystemZ_LOCGRAsm = 1504, - SystemZ_LOCGRAsmE = 1505, - SystemZ_LOCGRAsmH = 1506, - SystemZ_LOCGRAsmHE = 1507, - SystemZ_LOCGRAsmL = 1508, - SystemZ_LOCGRAsmLE = 1509, - SystemZ_LOCGRAsmLH = 1510, - SystemZ_LOCGRAsmM = 1511, - SystemZ_LOCGRAsmNE = 1512, - SystemZ_LOCGRAsmNH = 1513, - SystemZ_LOCGRAsmNHE = 1514, - SystemZ_LOCGRAsmNL = 1515, - SystemZ_LOCGRAsmNLE = 1516, - SystemZ_LOCGRAsmNLH = 1517, - SystemZ_LOCGRAsmNM = 1518, - SystemZ_LOCGRAsmNO = 1519, - SystemZ_LOCGRAsmNP = 1520, - SystemZ_LOCGRAsmNZ = 1521, - SystemZ_LOCGRAsmO = 1522, - SystemZ_LOCGRAsmP = 1523, - SystemZ_LOCGRAsmZ = 1524, - SystemZ_LOCHHI = 1525, - SystemZ_LOCHHIAsm = 1526, - SystemZ_LOCHHIAsmE = 1527, - SystemZ_LOCHHIAsmH = 1528, - SystemZ_LOCHHIAsmHE = 1529, - SystemZ_LOCHHIAsmL = 1530, - SystemZ_LOCHHIAsmLE = 1531, - SystemZ_LOCHHIAsmLH = 1532, - SystemZ_LOCHHIAsmM = 1533, - SystemZ_LOCHHIAsmNE = 1534, - SystemZ_LOCHHIAsmNH = 1535, - SystemZ_LOCHHIAsmNHE = 1536, - SystemZ_LOCHHIAsmNL = 1537, - SystemZ_LOCHHIAsmNLE = 1538, - SystemZ_LOCHHIAsmNLH = 1539, - SystemZ_LOCHHIAsmNM = 1540, - SystemZ_LOCHHIAsmNO = 1541, - SystemZ_LOCHHIAsmNP = 1542, - SystemZ_LOCHHIAsmNZ = 1543, - SystemZ_LOCHHIAsmO = 1544, - SystemZ_LOCHHIAsmP = 1545, - SystemZ_LOCHHIAsmZ = 1546, - SystemZ_LOCHI = 1547, - SystemZ_LOCHIAsm = 1548, - SystemZ_LOCHIAsmE = 1549, - SystemZ_LOCHIAsmH = 1550, - SystemZ_LOCHIAsmHE = 1551, - SystemZ_LOCHIAsmL = 1552, - SystemZ_LOCHIAsmLE = 1553, - SystemZ_LOCHIAsmLH = 1554, - SystemZ_LOCHIAsmM = 1555, - SystemZ_LOCHIAsmNE = 1556, - SystemZ_LOCHIAsmNH = 1557, - SystemZ_LOCHIAsmNHE = 1558, - SystemZ_LOCHIAsmNL = 1559, - SystemZ_LOCHIAsmNLE = 1560, - SystemZ_LOCHIAsmNLH = 1561, - SystemZ_LOCHIAsmNM = 1562, - SystemZ_LOCHIAsmNO = 1563, - SystemZ_LOCHIAsmNP = 1564, - SystemZ_LOCHIAsmNZ = 1565, - SystemZ_LOCHIAsmO = 1566, - SystemZ_LOCHIAsmP = 1567, - SystemZ_LOCHIAsmZ = 1568, - SystemZ_LOCR = 1569, - SystemZ_LOCRAsm = 1570, - SystemZ_LOCRAsmE = 1571, - SystemZ_LOCRAsmH = 1572, - SystemZ_LOCRAsmHE = 1573, - SystemZ_LOCRAsmL = 1574, - SystemZ_LOCRAsmLE = 1575, - SystemZ_LOCRAsmLH = 1576, - SystemZ_LOCRAsmM = 1577, - SystemZ_LOCRAsmNE = 1578, - SystemZ_LOCRAsmNH = 1579, - SystemZ_LOCRAsmNHE = 1580, - SystemZ_LOCRAsmNL = 1581, - SystemZ_LOCRAsmNLE = 1582, - SystemZ_LOCRAsmNLH = 1583, - SystemZ_LOCRAsmNM = 1584, - SystemZ_LOCRAsmNO = 1585, - SystemZ_LOCRAsmNP = 1586, - SystemZ_LOCRAsmNZ = 1587, - SystemZ_LOCRAsmO = 1588, - SystemZ_LOCRAsmP = 1589, - SystemZ_LOCRAsmZ = 1590, - SystemZ_LPCTL = 1591, - SystemZ_LPD = 1592, - SystemZ_LPDBR = 1593, - SystemZ_LPDFR = 1594, - SystemZ_LPDFR_32 = 1595, - SystemZ_LPDG = 1596, - SystemZ_LPDR = 1597, - SystemZ_LPEBR = 1598, - SystemZ_LPER = 1599, - SystemZ_LPGFR = 1600, - SystemZ_LPGR = 1601, - SystemZ_LPP = 1602, - SystemZ_LPQ = 1603, - SystemZ_LPR = 1604, - SystemZ_LPSW = 1605, - SystemZ_LPSWE = 1606, - SystemZ_LPTEA = 1607, - SystemZ_LPXBR = 1608, - SystemZ_LPXR = 1609, - SystemZ_LR = 1610, - SystemZ_LRA = 1611, - SystemZ_LRAG = 1612, - SystemZ_LRAY = 1613, - SystemZ_LRDR = 1614, - SystemZ_LRER = 1615, - SystemZ_LRL = 1616, - SystemZ_LRV = 1617, - SystemZ_LRVG = 1618, - SystemZ_LRVGR = 1619, - SystemZ_LRVH = 1620, - SystemZ_LRVR = 1621, - SystemZ_LSCTL = 1622, - SystemZ_LT = 1623, - SystemZ_LTDBR = 1624, - SystemZ_LTDBRCompare = 1625, - SystemZ_LTDR = 1626, - SystemZ_LTDTR = 1627, - SystemZ_LTEBR = 1628, - SystemZ_LTEBRCompare = 1629, - SystemZ_LTER = 1630, - SystemZ_LTG = 1631, - SystemZ_LTGF = 1632, - SystemZ_LTGFR = 1633, - SystemZ_LTGR = 1634, - SystemZ_LTR = 1635, - SystemZ_LTXBR = 1636, - SystemZ_LTXBRCompare = 1637, - SystemZ_LTXR = 1638, - SystemZ_LTXTR = 1639, - SystemZ_LURA = 1640, - SystemZ_LURAG = 1641, - SystemZ_LXD = 1642, - SystemZ_LXDB = 1643, - SystemZ_LXDBR = 1644, - SystemZ_LXDR = 1645, - SystemZ_LXDTR = 1646, - SystemZ_LXE = 1647, - SystemZ_LXEB = 1648, - SystemZ_LXEBR = 1649, - SystemZ_LXER = 1650, - SystemZ_LXR = 1651, - SystemZ_LY = 1652, - SystemZ_LZDR = 1653, - SystemZ_LZER = 1654, - SystemZ_LZRF = 1655, - SystemZ_LZRG = 1656, - SystemZ_LZXR = 1657, - SystemZ_M = 1658, - SystemZ_MAD = 1659, - SystemZ_MADB = 1660, - SystemZ_MADBR = 1661, - SystemZ_MADR = 1662, - SystemZ_MAE = 1663, - SystemZ_MAEB = 1664, - SystemZ_MAEBR = 1665, - SystemZ_MAER = 1666, - SystemZ_MAY = 1667, - SystemZ_MAYH = 1668, - SystemZ_MAYHR = 1669, - SystemZ_MAYL = 1670, - SystemZ_MAYLR = 1671, - SystemZ_MAYR = 1672, - SystemZ_MC = 1673, - SystemZ_MD = 1674, - SystemZ_MDB = 1675, - SystemZ_MDBR = 1676, - SystemZ_MDE = 1677, - SystemZ_MDEB = 1678, - SystemZ_MDEBR = 1679, - SystemZ_MDER = 1680, - SystemZ_MDR = 1681, - SystemZ_MDTR = 1682, - SystemZ_MDTRA = 1683, - SystemZ_ME = 1684, - SystemZ_MEE = 1685, - SystemZ_MEEB = 1686, - SystemZ_MEEBR = 1687, - SystemZ_MEER = 1688, - SystemZ_MER = 1689, - SystemZ_MFY = 1690, - SystemZ_MG = 1691, - SystemZ_MGH = 1692, - SystemZ_MGHI = 1693, - SystemZ_MGRK = 1694, - SystemZ_MH = 1695, - SystemZ_MHI = 1696, - SystemZ_MHY = 1697, - SystemZ_ML = 1698, - SystemZ_MLG = 1699, - SystemZ_MLGR = 1700, - SystemZ_MLR = 1701, - SystemZ_MP = 1702, - SystemZ_MR = 1703, - SystemZ_MS = 1704, - SystemZ_MSC = 1705, - SystemZ_MSCH = 1706, - SystemZ_MSD = 1707, - SystemZ_MSDB = 1708, - SystemZ_MSDBR = 1709, - SystemZ_MSDR = 1710, - SystemZ_MSE = 1711, - SystemZ_MSEB = 1712, - SystemZ_MSEBR = 1713, - SystemZ_MSER = 1714, - SystemZ_MSFI = 1715, - SystemZ_MSG = 1716, - SystemZ_MSGC = 1717, - SystemZ_MSGF = 1718, - SystemZ_MSGFI = 1719, - SystemZ_MSGFR = 1720, - SystemZ_MSGR = 1721, - SystemZ_MSGRKC = 1722, - SystemZ_MSR = 1723, - SystemZ_MSRKC = 1724, - SystemZ_MSTA = 1725, - SystemZ_MSY = 1726, - SystemZ_MVC = 1727, - SystemZ_MVCDK = 1728, - SystemZ_MVCIN = 1729, - SystemZ_MVCK = 1730, - SystemZ_MVCL = 1731, - SystemZ_MVCLE = 1732, - SystemZ_MVCLU = 1733, - SystemZ_MVCOS = 1734, - SystemZ_MVCP = 1735, - SystemZ_MVCS = 1736, - SystemZ_MVCSK = 1737, - SystemZ_MVGHI = 1738, - SystemZ_MVHHI = 1739, - SystemZ_MVHI = 1740, - SystemZ_MVI = 1741, - SystemZ_MVIY = 1742, - SystemZ_MVN = 1743, - SystemZ_MVO = 1744, - SystemZ_MVPG = 1745, - SystemZ_MVST = 1746, - SystemZ_MVZ = 1747, - SystemZ_MXBR = 1748, - SystemZ_MXD = 1749, - SystemZ_MXDB = 1750, - SystemZ_MXDBR = 1751, - SystemZ_MXDR = 1752, - SystemZ_MXR = 1753, - SystemZ_MXTR = 1754, - SystemZ_MXTRA = 1755, - SystemZ_MY = 1756, - SystemZ_MYH = 1757, - SystemZ_MYHR = 1758, - SystemZ_MYL = 1759, - SystemZ_MYLR = 1760, - SystemZ_MYR = 1761, - SystemZ_N = 1762, - SystemZ_NC = 1763, - SystemZ_NG = 1764, - SystemZ_NGR = 1765, - SystemZ_NGRK = 1766, - SystemZ_NI = 1767, - SystemZ_NIAI = 1768, - SystemZ_NIHF = 1769, - SystemZ_NIHH = 1770, - SystemZ_NIHL = 1771, - SystemZ_NILF = 1772, - SystemZ_NILH = 1773, - SystemZ_NILL = 1774, - SystemZ_NIY = 1775, - SystemZ_NR = 1776, - SystemZ_NRK = 1777, - SystemZ_NTSTG = 1778, - SystemZ_NY = 1779, - SystemZ_O = 1780, - SystemZ_OC = 1781, - SystemZ_OG = 1782, - SystemZ_OGR = 1783, - SystemZ_OGRK = 1784, - SystemZ_OI = 1785, - SystemZ_OIHF = 1786, - SystemZ_OIHH = 1787, - SystemZ_OIHL = 1788, - SystemZ_OILF = 1789, - SystemZ_OILH = 1790, - SystemZ_OILL = 1791, - SystemZ_OIY = 1792, - SystemZ_OR = 1793, - SystemZ_ORK = 1794, - SystemZ_OY = 1795, - SystemZ_PACK = 1796, - SystemZ_PALB = 1797, - SystemZ_PC = 1798, - SystemZ_PCC = 1799, - SystemZ_PCKMO = 1800, - SystemZ_PFD = 1801, - SystemZ_PFDRL = 1802, - SystemZ_PFMF = 1803, - SystemZ_PFPO = 1804, - SystemZ_PGIN = 1805, - SystemZ_PGOUT = 1806, - SystemZ_PKA = 1807, - SystemZ_PKU = 1808, - SystemZ_PLO = 1809, - SystemZ_POPCNT = 1810, - SystemZ_PPA = 1811, - SystemZ_PPNO = 1812, - SystemZ_PR = 1813, - SystemZ_PRNO = 1814, - SystemZ_PT = 1815, - SystemZ_PTF = 1816, - SystemZ_PTFF = 1817, - SystemZ_PTI = 1818, - SystemZ_PTLB = 1819, - SystemZ_QADTR = 1820, - SystemZ_QAXTR = 1821, - SystemZ_QCTRI = 1822, - SystemZ_QSI = 1823, - SystemZ_RCHP = 1824, - SystemZ_RISBG = 1825, - SystemZ_RISBG32 = 1826, - SystemZ_RISBGN = 1827, - SystemZ_RISBHG = 1828, - SystemZ_RISBLG = 1829, - SystemZ_RLL = 1830, - SystemZ_RLLG = 1831, - SystemZ_RNSBG = 1832, - SystemZ_ROSBG = 1833, - SystemZ_RP = 1834, - SystemZ_RRBE = 1835, - SystemZ_RRBM = 1836, - SystemZ_RRDTR = 1837, - SystemZ_RRXTR = 1838, - SystemZ_RSCH = 1839, - SystemZ_RXSBG = 1840, - SystemZ_S = 1841, - SystemZ_SAC = 1842, - SystemZ_SACF = 1843, - SystemZ_SAL = 1844, - SystemZ_SAM24 = 1845, - SystemZ_SAM31 = 1846, - SystemZ_SAM64 = 1847, - SystemZ_SAR = 1848, - SystemZ_SCCTR = 1849, - SystemZ_SCHM = 1850, - SystemZ_SCK = 1851, - SystemZ_SCKC = 1852, - SystemZ_SCKPF = 1853, - SystemZ_SD = 1854, - SystemZ_SDB = 1855, - SystemZ_SDBR = 1856, - SystemZ_SDR = 1857, - SystemZ_SDTR = 1858, - SystemZ_SDTRA = 1859, - SystemZ_SE = 1860, - SystemZ_SEB = 1861, - SystemZ_SEBR = 1862, - SystemZ_SER = 1863, - SystemZ_SFASR = 1864, - SystemZ_SFPC = 1865, - SystemZ_SG = 1866, - SystemZ_SGF = 1867, - SystemZ_SGFR = 1868, - SystemZ_SGH = 1869, - SystemZ_SGR = 1870, - SystemZ_SGRK = 1871, - SystemZ_SH = 1872, - SystemZ_SHHHR = 1873, - SystemZ_SHHLR = 1874, - SystemZ_SHY = 1875, - SystemZ_SIE = 1876, - SystemZ_SIGA = 1877, - SystemZ_SIGP = 1878, - SystemZ_SL = 1879, - SystemZ_SLA = 1880, - SystemZ_SLAG = 1881, - SystemZ_SLAK = 1882, - SystemZ_SLB = 1883, - SystemZ_SLBG = 1884, - SystemZ_SLBGR = 1885, - SystemZ_SLBR = 1886, - SystemZ_SLDA = 1887, - SystemZ_SLDL = 1888, - SystemZ_SLDT = 1889, - SystemZ_SLFI = 1890, - SystemZ_SLG = 1891, - SystemZ_SLGF = 1892, - SystemZ_SLGFI = 1893, - SystemZ_SLGFR = 1894, - SystemZ_SLGR = 1895, - SystemZ_SLGRK = 1896, - SystemZ_SLHHHR = 1897, - SystemZ_SLHHLR = 1898, - SystemZ_SLL = 1899, - SystemZ_SLLG = 1900, - SystemZ_SLLK = 1901, - SystemZ_SLR = 1902, - SystemZ_SLRK = 1903, - SystemZ_SLXT = 1904, - SystemZ_SLY = 1905, - SystemZ_SP = 1906, - SystemZ_SPCTR = 1907, - SystemZ_SPKA = 1908, - SystemZ_SPM = 1909, - SystemZ_SPT = 1910, - SystemZ_SPX = 1911, - SystemZ_SQD = 1912, - SystemZ_SQDB = 1913, - SystemZ_SQDBR = 1914, - SystemZ_SQDR = 1915, - SystemZ_SQE = 1916, - SystemZ_SQEB = 1917, - SystemZ_SQEBR = 1918, - SystemZ_SQER = 1919, - SystemZ_SQXBR = 1920, - SystemZ_SQXR = 1921, - SystemZ_SR = 1922, - SystemZ_SRA = 1923, - SystemZ_SRAG = 1924, - SystemZ_SRAK = 1925, - SystemZ_SRDA = 1926, - SystemZ_SRDL = 1927, - SystemZ_SRDT = 1928, - SystemZ_SRK = 1929, - SystemZ_SRL = 1930, - SystemZ_SRLG = 1931, - SystemZ_SRLK = 1932, - SystemZ_SRNM = 1933, - SystemZ_SRNMB = 1934, - SystemZ_SRNMT = 1935, - SystemZ_SRP = 1936, - SystemZ_SRST = 1937, - SystemZ_SRSTU = 1938, - SystemZ_SRXT = 1939, - SystemZ_SSAIR = 1940, - SystemZ_SSAR = 1941, - SystemZ_SSCH = 1942, - SystemZ_SSKE = 1943, - SystemZ_SSKEOpt = 1944, - SystemZ_SSM = 1945, - SystemZ_ST = 1946, - SystemZ_STAM = 1947, - SystemZ_STAMY = 1948, - SystemZ_STAP = 1949, - SystemZ_STC = 1950, - SystemZ_STCH = 1951, - SystemZ_STCK = 1952, - SystemZ_STCKC = 1953, - SystemZ_STCKE = 1954, - SystemZ_STCKF = 1955, - SystemZ_STCM = 1956, - SystemZ_STCMH = 1957, - SystemZ_STCMY = 1958, - SystemZ_STCPS = 1959, - SystemZ_STCRW = 1960, - SystemZ_STCTG = 1961, - SystemZ_STCTL = 1962, - SystemZ_STCY = 1963, - SystemZ_STD = 1964, - SystemZ_STDY = 1965, - SystemZ_STE = 1966, - SystemZ_STEY = 1967, - SystemZ_STFH = 1968, - SystemZ_STFL = 1969, - SystemZ_STFLE = 1970, - SystemZ_STFPC = 1971, - SystemZ_STG = 1972, - SystemZ_STGRL = 1973, - SystemZ_STGSC = 1974, - SystemZ_STH = 1975, - SystemZ_STHH = 1976, - SystemZ_STHRL = 1977, - SystemZ_STHY = 1978, - SystemZ_STIDP = 1979, - SystemZ_STM = 1980, - SystemZ_STMG = 1981, - SystemZ_STMH = 1982, - SystemZ_STMY = 1983, - SystemZ_STNSM = 1984, - SystemZ_STOC = 1985, - SystemZ_STOCAsm = 1986, - SystemZ_STOCAsmE = 1987, - SystemZ_STOCAsmH = 1988, - SystemZ_STOCAsmHE = 1989, - SystemZ_STOCAsmL = 1990, - SystemZ_STOCAsmLE = 1991, - SystemZ_STOCAsmLH = 1992, - SystemZ_STOCAsmM = 1993, - SystemZ_STOCAsmNE = 1994, - SystemZ_STOCAsmNH = 1995, - SystemZ_STOCAsmNHE = 1996, - SystemZ_STOCAsmNL = 1997, - SystemZ_STOCAsmNLE = 1998, - SystemZ_STOCAsmNLH = 1999, - SystemZ_STOCAsmNM = 2000, - SystemZ_STOCAsmNO = 2001, - SystemZ_STOCAsmNP = 2002, - SystemZ_STOCAsmNZ = 2003, - SystemZ_STOCAsmO = 2004, - SystemZ_STOCAsmP = 2005, - SystemZ_STOCAsmZ = 2006, - SystemZ_STOCFH = 2007, - SystemZ_STOCFHAsm = 2008, - SystemZ_STOCFHAsmE = 2009, - SystemZ_STOCFHAsmH = 2010, - SystemZ_STOCFHAsmHE = 2011, - SystemZ_STOCFHAsmL = 2012, - SystemZ_STOCFHAsmLE = 2013, - SystemZ_STOCFHAsmLH = 2014, - SystemZ_STOCFHAsmM = 2015, - SystemZ_STOCFHAsmNE = 2016, - SystemZ_STOCFHAsmNH = 2017, - SystemZ_STOCFHAsmNHE = 2018, - SystemZ_STOCFHAsmNL = 2019, - SystemZ_STOCFHAsmNLE = 2020, - SystemZ_STOCFHAsmNLH = 2021, - SystemZ_STOCFHAsmNM = 2022, - SystemZ_STOCFHAsmNO = 2023, - SystemZ_STOCFHAsmNP = 2024, - SystemZ_STOCFHAsmNZ = 2025, - SystemZ_STOCFHAsmO = 2026, - SystemZ_STOCFHAsmP = 2027, - SystemZ_STOCFHAsmZ = 2028, - SystemZ_STOCG = 2029, - SystemZ_STOCGAsm = 2030, - SystemZ_STOCGAsmE = 2031, - SystemZ_STOCGAsmH = 2032, - SystemZ_STOCGAsmHE = 2033, - SystemZ_STOCGAsmL = 2034, - SystemZ_STOCGAsmLE = 2035, - SystemZ_STOCGAsmLH = 2036, - SystemZ_STOCGAsmM = 2037, - SystemZ_STOCGAsmNE = 2038, - SystemZ_STOCGAsmNH = 2039, - SystemZ_STOCGAsmNHE = 2040, - SystemZ_STOCGAsmNL = 2041, - SystemZ_STOCGAsmNLE = 2042, - SystemZ_STOCGAsmNLH = 2043, - SystemZ_STOCGAsmNM = 2044, - SystemZ_STOCGAsmNO = 2045, - SystemZ_STOCGAsmNP = 2046, - SystemZ_STOCGAsmNZ = 2047, - SystemZ_STOCGAsmO = 2048, - SystemZ_STOCGAsmP = 2049, - SystemZ_STOCGAsmZ = 2050, - SystemZ_STOSM = 2051, - SystemZ_STPQ = 2052, - SystemZ_STPT = 2053, - SystemZ_STPX = 2054, - SystemZ_STRAG = 2055, - SystemZ_STRL = 2056, - SystemZ_STRV = 2057, - SystemZ_STRVG = 2058, - SystemZ_STRVH = 2059, - SystemZ_STSCH = 2060, - SystemZ_STSI = 2061, - SystemZ_STURA = 2062, - SystemZ_STURG = 2063, - SystemZ_STY = 2064, - SystemZ_SU = 2065, - SystemZ_SUR = 2066, - SystemZ_SVC = 2067, - SystemZ_SW = 2068, - SystemZ_SWR = 2069, - SystemZ_SXBR = 2070, - SystemZ_SXR = 2071, - SystemZ_SXTR = 2072, - SystemZ_SXTRA = 2073, - SystemZ_SY = 2074, - SystemZ_TABORT = 2075, - SystemZ_TAM = 2076, - SystemZ_TAR = 2077, - SystemZ_TB = 2078, - SystemZ_TBDR = 2079, - SystemZ_TBEDR = 2080, - SystemZ_TBEGIN = 2081, - SystemZ_TBEGINC = 2082, - SystemZ_TCDB = 2083, - SystemZ_TCEB = 2084, - SystemZ_TCXB = 2085, - SystemZ_TDCDT = 2086, - SystemZ_TDCET = 2087, - SystemZ_TDCXT = 2088, - SystemZ_TDGDT = 2089, - SystemZ_TDGET = 2090, - SystemZ_TDGXT = 2091, - SystemZ_TEND = 2092, - SystemZ_THDER = 2093, - SystemZ_THDR = 2094, - SystemZ_TM = 2095, - SystemZ_TMHH = 2096, - SystemZ_TMHL = 2097, - SystemZ_TMLH = 2098, - SystemZ_TMLL = 2099, - SystemZ_TMY = 2100, - SystemZ_TP = 2101, - SystemZ_TPI = 2102, - SystemZ_TPROT = 2103, - SystemZ_TR = 2104, - SystemZ_TRACE = 2105, - SystemZ_TRACG = 2106, - SystemZ_TRAP2 = 2107, - SystemZ_TRAP4 = 2108, - SystemZ_TRE = 2109, - SystemZ_TROO = 2110, - SystemZ_TROOOpt = 2111, - SystemZ_TROT = 2112, - SystemZ_TROTOpt = 2113, - SystemZ_TRT = 2114, - SystemZ_TRTE = 2115, - SystemZ_TRTEOpt = 2116, - SystemZ_TRTO = 2117, - SystemZ_TRTOOpt = 2118, - SystemZ_TRTR = 2119, - SystemZ_TRTRE = 2120, - SystemZ_TRTREOpt = 2121, - SystemZ_TRTT = 2122, - SystemZ_TRTTOpt = 2123, - SystemZ_TS = 2124, - SystemZ_TSCH = 2125, - SystemZ_UNPK = 2126, - SystemZ_UNPKA = 2127, - SystemZ_UNPKU = 2128, - SystemZ_UPT = 2129, - SystemZ_VA = 2130, - SystemZ_VAB = 2131, - SystemZ_VAC = 2132, - SystemZ_VACC = 2133, - SystemZ_VACCB = 2134, - SystemZ_VACCC = 2135, - SystemZ_VACCCQ = 2136, - SystemZ_VACCF = 2137, - SystemZ_VACCG = 2138, - SystemZ_VACCH = 2139, - SystemZ_VACCQ = 2140, - SystemZ_VACQ = 2141, - SystemZ_VAF = 2142, - SystemZ_VAG = 2143, - SystemZ_VAH = 2144, - SystemZ_VAP = 2145, - SystemZ_VAQ = 2146, - SystemZ_VAVG = 2147, - SystemZ_VAVGB = 2148, - SystemZ_VAVGF = 2149, - SystemZ_VAVGG = 2150, - SystemZ_VAVGH = 2151, - SystemZ_VAVGL = 2152, - SystemZ_VAVGLB = 2153, - SystemZ_VAVGLF = 2154, - SystemZ_VAVGLG = 2155, - SystemZ_VAVGLH = 2156, - SystemZ_VBPERM = 2157, - SystemZ_VCDG = 2158, - SystemZ_VCDGB = 2159, - SystemZ_VCDLG = 2160, - SystemZ_VCDLGB = 2161, - SystemZ_VCEQ = 2162, - SystemZ_VCEQB = 2163, - SystemZ_VCEQBS = 2164, - SystemZ_VCEQF = 2165, - SystemZ_VCEQFS = 2166, - SystemZ_VCEQG = 2167, - SystemZ_VCEQGS = 2168, - SystemZ_VCEQH = 2169, - SystemZ_VCEQHS = 2170, - SystemZ_VCGD = 2171, - SystemZ_VCGDB = 2172, - SystemZ_VCH = 2173, - SystemZ_VCHB = 2174, - SystemZ_VCHBS = 2175, - SystemZ_VCHF = 2176, - SystemZ_VCHFS = 2177, - SystemZ_VCHG = 2178, - SystemZ_VCHGS = 2179, - SystemZ_VCHH = 2180, - SystemZ_VCHHS = 2181, - SystemZ_VCHL = 2182, - SystemZ_VCHLB = 2183, - SystemZ_VCHLBS = 2184, - SystemZ_VCHLF = 2185, - SystemZ_VCHLFS = 2186, - SystemZ_VCHLG = 2187, - SystemZ_VCHLGS = 2188, - SystemZ_VCHLH = 2189, - SystemZ_VCHLHS = 2190, - SystemZ_VCKSM = 2191, - SystemZ_VCLGD = 2192, - SystemZ_VCLGDB = 2193, - SystemZ_VCLZ = 2194, - SystemZ_VCLZB = 2195, - SystemZ_VCLZF = 2196, - SystemZ_VCLZG = 2197, - SystemZ_VCLZH = 2198, - SystemZ_VCP = 2199, - SystemZ_VCTZ = 2200, - SystemZ_VCTZB = 2201, - SystemZ_VCTZF = 2202, - SystemZ_VCTZG = 2203, - SystemZ_VCTZH = 2204, - SystemZ_VCVB = 2205, - SystemZ_VCVBG = 2206, - SystemZ_VCVD = 2207, - SystemZ_VCVDG = 2208, - SystemZ_VDP = 2209, - SystemZ_VEC = 2210, - SystemZ_VECB = 2211, - SystemZ_VECF = 2212, - SystemZ_VECG = 2213, - SystemZ_VECH = 2214, - SystemZ_VECL = 2215, - SystemZ_VECLB = 2216, - SystemZ_VECLF = 2217, - SystemZ_VECLG = 2218, - SystemZ_VECLH = 2219, - SystemZ_VERIM = 2220, - SystemZ_VERIMB = 2221, - SystemZ_VERIMF = 2222, - SystemZ_VERIMG = 2223, - SystemZ_VERIMH = 2224, - SystemZ_VERLL = 2225, - SystemZ_VERLLB = 2226, - SystemZ_VERLLF = 2227, - SystemZ_VERLLG = 2228, - SystemZ_VERLLH = 2229, - SystemZ_VERLLV = 2230, - SystemZ_VERLLVB = 2231, - SystemZ_VERLLVF = 2232, - SystemZ_VERLLVG = 2233, - SystemZ_VERLLVH = 2234, - SystemZ_VESL = 2235, - SystemZ_VESLB = 2236, - SystemZ_VESLF = 2237, - SystemZ_VESLG = 2238, - SystemZ_VESLH = 2239, - SystemZ_VESLV = 2240, - SystemZ_VESLVB = 2241, - SystemZ_VESLVF = 2242, - SystemZ_VESLVG = 2243, - SystemZ_VESLVH = 2244, - SystemZ_VESRA = 2245, - SystemZ_VESRAB = 2246, - SystemZ_VESRAF = 2247, - SystemZ_VESRAG = 2248, - SystemZ_VESRAH = 2249, - SystemZ_VESRAV = 2250, - SystemZ_VESRAVB = 2251, - SystemZ_VESRAVF = 2252, - SystemZ_VESRAVG = 2253, - SystemZ_VESRAVH = 2254, - SystemZ_VESRL = 2255, - SystemZ_VESRLB = 2256, - SystemZ_VESRLF = 2257, - SystemZ_VESRLG = 2258, - SystemZ_VESRLH = 2259, - SystemZ_VESRLV = 2260, - SystemZ_VESRLVB = 2261, - SystemZ_VESRLVF = 2262, - SystemZ_VESRLVG = 2263, - SystemZ_VESRLVH = 2264, - SystemZ_VFA = 2265, - SystemZ_VFADB = 2266, - SystemZ_VFAE = 2267, - SystemZ_VFAEB = 2268, - SystemZ_VFAEBS = 2269, - SystemZ_VFAEF = 2270, - SystemZ_VFAEFS = 2271, - SystemZ_VFAEH = 2272, - SystemZ_VFAEHS = 2273, - SystemZ_VFAEZB = 2274, - SystemZ_VFAEZBS = 2275, - SystemZ_VFAEZF = 2276, - SystemZ_VFAEZFS = 2277, - SystemZ_VFAEZH = 2278, - SystemZ_VFAEZHS = 2279, - SystemZ_VFASB = 2280, - SystemZ_VFCE = 2281, - SystemZ_VFCEDB = 2282, - SystemZ_VFCEDBS = 2283, - SystemZ_VFCESB = 2284, - SystemZ_VFCESBS = 2285, - SystemZ_VFCH = 2286, - SystemZ_VFCHDB = 2287, - SystemZ_VFCHDBS = 2288, - SystemZ_VFCHE = 2289, - SystemZ_VFCHEDB = 2290, - SystemZ_VFCHEDBS = 2291, - SystemZ_VFCHESB = 2292, - SystemZ_VFCHESBS = 2293, - SystemZ_VFCHSB = 2294, - SystemZ_VFCHSBS = 2295, - SystemZ_VFD = 2296, - SystemZ_VFDDB = 2297, - SystemZ_VFDSB = 2298, - SystemZ_VFEE = 2299, - SystemZ_VFEEB = 2300, - SystemZ_VFEEBS = 2301, - SystemZ_VFEEF = 2302, - SystemZ_VFEEFS = 2303, - SystemZ_VFEEH = 2304, - SystemZ_VFEEHS = 2305, - SystemZ_VFEEZB = 2306, - SystemZ_VFEEZBS = 2307, - SystemZ_VFEEZF = 2308, - SystemZ_VFEEZFS = 2309, - SystemZ_VFEEZH = 2310, - SystemZ_VFEEZHS = 2311, - SystemZ_VFENE = 2312, - SystemZ_VFENEB = 2313, - SystemZ_VFENEBS = 2314, - SystemZ_VFENEF = 2315, - SystemZ_VFENEFS = 2316, - SystemZ_VFENEH = 2317, - SystemZ_VFENEHS = 2318, - SystemZ_VFENEZB = 2319, - SystemZ_VFENEZBS = 2320, - SystemZ_VFENEZF = 2321, - SystemZ_VFENEZFS = 2322, - SystemZ_VFENEZH = 2323, - SystemZ_VFENEZHS = 2324, - SystemZ_VFI = 2325, - SystemZ_VFIDB = 2326, - SystemZ_VFISB = 2327, - SystemZ_VFKEDB = 2328, - SystemZ_VFKEDBS = 2329, - SystemZ_VFKESB = 2330, - SystemZ_VFKESBS = 2331, - SystemZ_VFKHDB = 2332, - SystemZ_VFKHDBS = 2333, - SystemZ_VFKHEDB = 2334, - SystemZ_VFKHEDBS = 2335, - SystemZ_VFKHESB = 2336, - SystemZ_VFKHESBS = 2337, - SystemZ_VFKHSB = 2338, - SystemZ_VFKHSBS = 2339, - SystemZ_VFLCDB = 2340, - SystemZ_VFLCSB = 2341, - SystemZ_VFLL = 2342, - SystemZ_VFLLS = 2343, - SystemZ_VFLNDB = 2344, - SystemZ_VFLNSB = 2345, - SystemZ_VFLPDB = 2346, - SystemZ_VFLPSB = 2347, - SystemZ_VFLR = 2348, - SystemZ_VFLRD = 2349, - SystemZ_VFM = 2350, - SystemZ_VFMA = 2351, - SystemZ_VFMADB = 2352, - SystemZ_VFMASB = 2353, - SystemZ_VFMAX = 2354, - SystemZ_VFMAXDB = 2355, - SystemZ_VFMAXSB = 2356, - SystemZ_VFMDB = 2357, - SystemZ_VFMIN = 2358, - SystemZ_VFMINDB = 2359, - SystemZ_VFMINSB = 2360, - SystemZ_VFMS = 2361, - SystemZ_VFMSB = 2362, - SystemZ_VFMSDB = 2363, - SystemZ_VFMSSB = 2364, - SystemZ_VFNMA = 2365, - SystemZ_VFNMADB = 2366, - SystemZ_VFNMASB = 2367, - SystemZ_VFNMS = 2368, - SystemZ_VFNMSDB = 2369, - SystemZ_VFNMSSB = 2370, - SystemZ_VFPSO = 2371, - SystemZ_VFPSODB = 2372, - SystemZ_VFPSOSB = 2373, - SystemZ_VFS = 2374, - SystemZ_VFSDB = 2375, - SystemZ_VFSQ = 2376, - SystemZ_VFSQDB = 2377, - SystemZ_VFSQSB = 2378, - SystemZ_VFSSB = 2379, - SystemZ_VFTCI = 2380, - SystemZ_VFTCIDB = 2381, - SystemZ_VFTCISB = 2382, - SystemZ_VGBM = 2383, - SystemZ_VGEF = 2384, - SystemZ_VGEG = 2385, - SystemZ_VGFM = 2386, - SystemZ_VGFMA = 2387, - SystemZ_VGFMAB = 2388, - SystemZ_VGFMAF = 2389, - SystemZ_VGFMAG = 2390, - SystemZ_VGFMAH = 2391, - SystemZ_VGFMB = 2392, - SystemZ_VGFMF = 2393, - SystemZ_VGFMG = 2394, - SystemZ_VGFMH = 2395, - SystemZ_VGM = 2396, - SystemZ_VGMB = 2397, - SystemZ_VGMF = 2398, - SystemZ_VGMG = 2399, - SystemZ_VGMH = 2400, - SystemZ_VISTR = 2401, - SystemZ_VISTRB = 2402, - SystemZ_VISTRBS = 2403, - SystemZ_VISTRF = 2404, - SystemZ_VISTRFS = 2405, - SystemZ_VISTRH = 2406, - SystemZ_VISTRHS = 2407, - SystemZ_VL = 2408, - SystemZ_VLBB = 2409, - SystemZ_VLC = 2410, - SystemZ_VLCB = 2411, - SystemZ_VLCF = 2412, - SystemZ_VLCG = 2413, - SystemZ_VLCH = 2414, - SystemZ_VLDE = 2415, - SystemZ_VLDEB = 2416, - SystemZ_VLEB = 2417, - SystemZ_VLED = 2418, - SystemZ_VLEDB = 2419, - SystemZ_VLEF = 2420, - SystemZ_VLEG = 2421, - SystemZ_VLEH = 2422, - SystemZ_VLEIB = 2423, - SystemZ_VLEIF = 2424, - SystemZ_VLEIG = 2425, - SystemZ_VLEIH = 2426, - SystemZ_VLGV = 2427, - SystemZ_VLGVB = 2428, - SystemZ_VLGVF = 2429, - SystemZ_VLGVG = 2430, - SystemZ_VLGVH = 2431, - SystemZ_VLIP = 2432, - SystemZ_VLL = 2433, - SystemZ_VLLEZ = 2434, - SystemZ_VLLEZB = 2435, - SystemZ_VLLEZF = 2436, - SystemZ_VLLEZG = 2437, - SystemZ_VLLEZH = 2438, - SystemZ_VLLEZLF = 2439, - SystemZ_VLM = 2440, - SystemZ_VLP = 2441, - SystemZ_VLPB = 2442, - SystemZ_VLPF = 2443, - SystemZ_VLPG = 2444, - SystemZ_VLPH = 2445, - SystemZ_VLR = 2446, - SystemZ_VLREP = 2447, - SystemZ_VLREPB = 2448, - SystemZ_VLREPF = 2449, - SystemZ_VLREPG = 2450, - SystemZ_VLREPH = 2451, - SystemZ_VLRL = 2452, - SystemZ_VLRLR = 2453, - SystemZ_VLVG = 2454, - SystemZ_VLVGB = 2455, - SystemZ_VLVGF = 2456, - SystemZ_VLVGG = 2457, - SystemZ_VLVGH = 2458, - SystemZ_VLVGP = 2459, - SystemZ_VMAE = 2460, - SystemZ_VMAEB = 2461, - SystemZ_VMAEF = 2462, - SystemZ_VMAEH = 2463, - SystemZ_VMAH = 2464, - SystemZ_VMAHB = 2465, - SystemZ_VMAHF = 2466, - SystemZ_VMAHH = 2467, - SystemZ_VMAL = 2468, - SystemZ_VMALB = 2469, - SystemZ_VMALE = 2470, - SystemZ_VMALEB = 2471, - SystemZ_VMALEF = 2472, - SystemZ_VMALEH = 2473, - SystemZ_VMALF = 2474, - SystemZ_VMALH = 2475, - SystemZ_VMALHB = 2476, - SystemZ_VMALHF = 2477, - SystemZ_VMALHH = 2478, - SystemZ_VMALHW = 2479, - SystemZ_VMALO = 2480, - SystemZ_VMALOB = 2481, - SystemZ_VMALOF = 2482, - SystemZ_VMALOH = 2483, - SystemZ_VMAO = 2484, - SystemZ_VMAOB = 2485, - SystemZ_VMAOF = 2486, - SystemZ_VMAOH = 2487, - SystemZ_VME = 2488, - SystemZ_VMEB = 2489, - SystemZ_VMEF = 2490, - SystemZ_VMEH = 2491, - SystemZ_VMH = 2492, - SystemZ_VMHB = 2493, - SystemZ_VMHF = 2494, - SystemZ_VMHH = 2495, - SystemZ_VML = 2496, - SystemZ_VMLB = 2497, - SystemZ_VMLE = 2498, - SystemZ_VMLEB = 2499, - SystemZ_VMLEF = 2500, - SystemZ_VMLEH = 2501, - SystemZ_VMLF = 2502, - SystemZ_VMLH = 2503, - SystemZ_VMLHB = 2504, - SystemZ_VMLHF = 2505, - SystemZ_VMLHH = 2506, - SystemZ_VMLHW = 2507, - SystemZ_VMLO = 2508, - SystemZ_VMLOB = 2509, - SystemZ_VMLOF = 2510, - SystemZ_VMLOH = 2511, - SystemZ_VMN = 2512, - SystemZ_VMNB = 2513, - SystemZ_VMNF = 2514, - SystemZ_VMNG = 2515, - SystemZ_VMNH = 2516, - SystemZ_VMNL = 2517, - SystemZ_VMNLB = 2518, - SystemZ_VMNLF = 2519, - SystemZ_VMNLG = 2520, - SystemZ_VMNLH = 2521, - SystemZ_VMO = 2522, - SystemZ_VMOB = 2523, - SystemZ_VMOF = 2524, - SystemZ_VMOH = 2525, - SystemZ_VMP = 2526, - SystemZ_VMRH = 2527, - SystemZ_VMRHB = 2528, - SystemZ_VMRHF = 2529, - SystemZ_VMRHG = 2530, - SystemZ_VMRHH = 2531, - SystemZ_VMRL = 2532, - SystemZ_VMRLB = 2533, - SystemZ_VMRLF = 2534, - SystemZ_VMRLG = 2535, - SystemZ_VMRLH = 2536, - SystemZ_VMSL = 2537, - SystemZ_VMSLG = 2538, - SystemZ_VMSP = 2539, - SystemZ_VMX = 2540, - SystemZ_VMXB = 2541, - SystemZ_VMXF = 2542, - SystemZ_VMXG = 2543, - SystemZ_VMXH = 2544, - SystemZ_VMXL = 2545, - SystemZ_VMXLB = 2546, - SystemZ_VMXLF = 2547, - SystemZ_VMXLG = 2548, - SystemZ_VMXLH = 2549, - SystemZ_VN = 2550, - SystemZ_VNC = 2551, - SystemZ_VNN = 2552, - SystemZ_VNO = 2553, - SystemZ_VNX = 2554, - SystemZ_VO = 2555, - SystemZ_VOC = 2556, - SystemZ_VONE = 2557, - SystemZ_VPDI = 2558, - SystemZ_VPERM = 2559, - SystemZ_VPK = 2560, - SystemZ_VPKF = 2561, - SystemZ_VPKG = 2562, - SystemZ_VPKH = 2563, - SystemZ_VPKLS = 2564, - SystemZ_VPKLSF = 2565, - SystemZ_VPKLSFS = 2566, - SystemZ_VPKLSG = 2567, - SystemZ_VPKLSGS = 2568, - SystemZ_VPKLSH = 2569, - SystemZ_VPKLSHS = 2570, - SystemZ_VPKS = 2571, - SystemZ_VPKSF = 2572, - SystemZ_VPKSFS = 2573, - SystemZ_VPKSG = 2574, - SystemZ_VPKSGS = 2575, - SystemZ_VPKSH = 2576, - SystemZ_VPKSHS = 2577, - SystemZ_VPKZ = 2578, - SystemZ_VPOPCT = 2579, - SystemZ_VPOPCTB = 2580, - SystemZ_VPOPCTF = 2581, - SystemZ_VPOPCTG = 2582, - SystemZ_VPOPCTH = 2583, - SystemZ_VPSOP = 2584, - SystemZ_VREP = 2585, - SystemZ_VREPB = 2586, - SystemZ_VREPF = 2587, - SystemZ_VREPG = 2588, - SystemZ_VREPH = 2589, - SystemZ_VREPI = 2590, - SystemZ_VREPIB = 2591, - SystemZ_VREPIF = 2592, - SystemZ_VREPIG = 2593, - SystemZ_VREPIH = 2594, - SystemZ_VRP = 2595, - SystemZ_VS = 2596, - SystemZ_VSB = 2597, - SystemZ_VSBCBI = 2598, - SystemZ_VSBCBIQ = 2599, - SystemZ_VSBI = 2600, - SystemZ_VSBIQ = 2601, - SystemZ_VSCBI = 2602, - SystemZ_VSCBIB = 2603, - SystemZ_VSCBIF = 2604, - SystemZ_VSCBIG = 2605, - SystemZ_VSCBIH = 2606, - SystemZ_VSCBIQ = 2607, - SystemZ_VSCEF = 2608, - SystemZ_VSCEG = 2609, - SystemZ_VSDP = 2610, - SystemZ_VSEG = 2611, - SystemZ_VSEGB = 2612, - SystemZ_VSEGF = 2613, - SystemZ_VSEGH = 2614, - SystemZ_VSEL = 2615, - SystemZ_VSF = 2616, - SystemZ_VSG = 2617, - SystemZ_VSH = 2618, - SystemZ_VSL = 2619, - SystemZ_VSLB = 2620, - SystemZ_VSLDB = 2621, - SystemZ_VSP = 2622, - SystemZ_VSQ = 2623, - SystemZ_VSRA = 2624, - SystemZ_VSRAB = 2625, - SystemZ_VSRL = 2626, - SystemZ_VSRLB = 2627, - SystemZ_VSRP = 2628, - SystemZ_VST = 2629, - SystemZ_VSTEB = 2630, - SystemZ_VSTEF = 2631, - SystemZ_VSTEG = 2632, - SystemZ_VSTEH = 2633, - SystemZ_VSTL = 2634, - SystemZ_VSTM = 2635, - SystemZ_VSTRC = 2636, - SystemZ_VSTRCB = 2637, - SystemZ_VSTRCBS = 2638, - SystemZ_VSTRCF = 2639, - SystemZ_VSTRCFS = 2640, - SystemZ_VSTRCH = 2641, - SystemZ_VSTRCHS = 2642, - SystemZ_VSTRCZB = 2643, - SystemZ_VSTRCZBS = 2644, - SystemZ_VSTRCZF = 2645, - SystemZ_VSTRCZFS = 2646, - SystemZ_VSTRCZH = 2647, - SystemZ_VSTRCZHS = 2648, - SystemZ_VSTRL = 2649, - SystemZ_VSTRLR = 2650, - SystemZ_VSUM = 2651, - SystemZ_VSUMB = 2652, - SystemZ_VSUMG = 2653, - SystemZ_VSUMGF = 2654, - SystemZ_VSUMGH = 2655, - SystemZ_VSUMH = 2656, - SystemZ_VSUMQ = 2657, - SystemZ_VSUMQF = 2658, - SystemZ_VSUMQG = 2659, - SystemZ_VTM = 2660, - SystemZ_VTP = 2661, - SystemZ_VUPH = 2662, - SystemZ_VUPHB = 2663, - SystemZ_VUPHF = 2664, - SystemZ_VUPHH = 2665, - SystemZ_VUPKZ = 2666, - SystemZ_VUPL = 2667, - SystemZ_VUPLB = 2668, - SystemZ_VUPLF = 2669, - SystemZ_VUPLH = 2670, - SystemZ_VUPLHB = 2671, - SystemZ_VUPLHF = 2672, - SystemZ_VUPLHH = 2673, - SystemZ_VUPLHW = 2674, - SystemZ_VUPLL = 2675, - SystemZ_VUPLLB = 2676, - SystemZ_VUPLLF = 2677, - SystemZ_VUPLLH = 2678, - SystemZ_VX = 2679, - SystemZ_VZERO = 2680, - SystemZ_WCDGB = 2681, - SystemZ_WCDLGB = 2682, - SystemZ_WCGDB = 2683, - SystemZ_WCLGDB = 2684, - SystemZ_WFADB = 2685, - SystemZ_WFASB = 2686, - SystemZ_WFAXB = 2687, - SystemZ_WFC = 2688, - SystemZ_WFCDB = 2689, - SystemZ_WFCEDB = 2690, - SystemZ_WFCEDBS = 2691, - SystemZ_WFCESB = 2692, - SystemZ_WFCESBS = 2693, - SystemZ_WFCEXB = 2694, - SystemZ_WFCEXBS = 2695, - SystemZ_WFCHDB = 2696, - SystemZ_WFCHDBS = 2697, - SystemZ_WFCHEDB = 2698, - SystemZ_WFCHEDBS = 2699, - SystemZ_WFCHESB = 2700, - SystemZ_WFCHESBS = 2701, - SystemZ_WFCHEXB = 2702, - SystemZ_WFCHEXBS = 2703, - SystemZ_WFCHSB = 2704, - SystemZ_WFCHSBS = 2705, - SystemZ_WFCHXB = 2706, - SystemZ_WFCHXBS = 2707, - SystemZ_WFCSB = 2708, - SystemZ_WFCXB = 2709, - SystemZ_WFDDB = 2710, - SystemZ_WFDSB = 2711, - SystemZ_WFDXB = 2712, - SystemZ_WFIDB = 2713, - SystemZ_WFISB = 2714, - SystemZ_WFIXB = 2715, - SystemZ_WFK = 2716, - SystemZ_WFKDB = 2717, - SystemZ_WFKEDB = 2718, - SystemZ_WFKEDBS = 2719, - SystemZ_WFKESB = 2720, - SystemZ_WFKESBS = 2721, - SystemZ_WFKEXB = 2722, - SystemZ_WFKEXBS = 2723, - SystemZ_WFKHDB = 2724, - SystemZ_WFKHDBS = 2725, - SystemZ_WFKHEDB = 2726, - SystemZ_WFKHEDBS = 2727, - SystemZ_WFKHESB = 2728, - SystemZ_WFKHESBS = 2729, - SystemZ_WFKHEXB = 2730, - SystemZ_WFKHEXBS = 2731, - SystemZ_WFKHSB = 2732, - SystemZ_WFKHSBS = 2733, - SystemZ_WFKHXB = 2734, - SystemZ_WFKHXBS = 2735, - SystemZ_WFKSB = 2736, - SystemZ_WFKXB = 2737, - SystemZ_WFLCDB = 2738, - SystemZ_WFLCSB = 2739, - SystemZ_WFLCXB = 2740, - SystemZ_WFLLD = 2741, - SystemZ_WFLLS = 2742, - SystemZ_WFLNDB = 2743, - SystemZ_WFLNSB = 2744, - SystemZ_WFLNXB = 2745, - SystemZ_WFLPDB = 2746, - SystemZ_WFLPSB = 2747, - SystemZ_WFLPXB = 2748, - SystemZ_WFLRD = 2749, - SystemZ_WFLRX = 2750, - SystemZ_WFMADB = 2751, - SystemZ_WFMASB = 2752, - SystemZ_WFMAXB = 2753, - SystemZ_WFMAXDB = 2754, - SystemZ_WFMAXSB = 2755, - SystemZ_WFMAXXB = 2756, - SystemZ_WFMDB = 2757, - SystemZ_WFMINDB = 2758, - SystemZ_WFMINSB = 2759, - SystemZ_WFMINXB = 2760, - SystemZ_WFMSB = 2761, - SystemZ_WFMSDB = 2762, - SystemZ_WFMSSB = 2763, - SystemZ_WFMSXB = 2764, - SystemZ_WFMXB = 2765, - SystemZ_WFNMADB = 2766, - SystemZ_WFNMASB = 2767, - SystemZ_WFNMAXB = 2768, - SystemZ_WFNMSDB = 2769, - SystemZ_WFNMSSB = 2770, - SystemZ_WFNMSXB = 2771, - SystemZ_WFPSODB = 2772, - SystemZ_WFPSOSB = 2773, - SystemZ_WFPSOXB = 2774, - SystemZ_WFSDB = 2775, - SystemZ_WFSQDB = 2776, - SystemZ_WFSQSB = 2777, - SystemZ_WFSQXB = 2778, - SystemZ_WFSSB = 2779, - SystemZ_WFSXB = 2780, - SystemZ_WFTCIDB = 2781, - SystemZ_WFTCISB = 2782, - SystemZ_WFTCIXB = 2783, - SystemZ_WLDEB = 2784, - SystemZ_WLEDB = 2785, - SystemZ_X = 2786, - SystemZ_XC = 2787, - SystemZ_XG = 2788, - SystemZ_XGR = 2789, - SystemZ_XGRK = 2790, - SystemZ_XI = 2791, - SystemZ_XIHF = 2792, - SystemZ_XILF = 2793, - SystemZ_XIY = 2794, - SystemZ_XR = 2795, - SystemZ_XRK = 2796, - SystemZ_XSCH = 2797, - SystemZ_XY = 2798, - SystemZ_ZAP = 2799, - SystemZ_INSTRUCTION_LIST_END = 2800 + SystemZ_INLINEASM_BR = 2, + SystemZ_CFI_INSTRUCTION = 3, + SystemZ_EH_LABEL = 4, + SystemZ_GC_LABEL = 5, + SystemZ_ANNOTATION_LABEL = 6, + SystemZ_KILL = 7, + SystemZ_EXTRACT_SUBREG = 8, + SystemZ_INSERT_SUBREG = 9, + SystemZ_IMPLICIT_DEF = 10, + SystemZ_SUBREG_TO_REG = 11, + SystemZ_COPY_TO_REGCLASS = 12, + SystemZ_DBG_VALUE = 13, + SystemZ_DBG_VALUE_LIST = 14, + SystemZ_DBG_INSTR_REF = 15, + SystemZ_DBG_PHI = 16, + SystemZ_DBG_LABEL = 17, + SystemZ_REG_SEQUENCE = 18, + SystemZ_COPY = 19, + SystemZ_BUNDLE = 20, + SystemZ_LIFETIME_START = 21, + SystemZ_LIFETIME_END = 22, + SystemZ_PSEUDO_PROBE = 23, + SystemZ_ARITH_FENCE = 24, + SystemZ_STACKMAP = 25, + SystemZ_FENTRY_CALL = 26, + SystemZ_PATCHPOINT = 27, + SystemZ_LOAD_STACK_GUARD = 28, + SystemZ_PREALLOCATED_SETUP = 29, + SystemZ_PREALLOCATED_ARG = 30, + SystemZ_STATEPOINT = 31, + SystemZ_LOCAL_ESCAPE = 32, + SystemZ_FAULTING_OP = 33, + SystemZ_PATCHABLE_OP = 34, + SystemZ_PATCHABLE_FUNCTION_ENTER = 35, + SystemZ_PATCHABLE_RET = 36, + SystemZ_PATCHABLE_FUNCTION_EXIT = 37, + SystemZ_PATCHABLE_TAIL_CALL = 38, + SystemZ_PATCHABLE_EVENT_CALL = 39, + SystemZ_PATCHABLE_TYPED_EVENT_CALL = 40, + SystemZ_ICALL_BRANCH_FUNNEL = 41, + SystemZ_MEMBARRIER = 42, + SystemZ_JUMP_TABLE_DEBUG_INFO = 43, + SystemZ_G_ASSERT_SEXT = 44, + SystemZ_G_ASSERT_ZEXT = 45, + SystemZ_G_ASSERT_ALIGN = 46, + SystemZ_G_ADD = 47, + SystemZ_G_SUB = 48, + SystemZ_G_MUL = 49, + SystemZ_G_SDIV = 50, + SystemZ_G_UDIV = 51, + SystemZ_G_SREM = 52, + SystemZ_G_UREM = 53, + SystemZ_G_SDIVREM = 54, + SystemZ_G_UDIVREM = 55, + SystemZ_G_AND = 56, + SystemZ_G_OR = 57, + SystemZ_G_XOR = 58, + SystemZ_G_IMPLICIT_DEF = 59, + SystemZ_G_PHI = 60, + SystemZ_G_FRAME_INDEX = 61, + SystemZ_G_GLOBAL_VALUE = 62, + SystemZ_G_CONSTANT_POOL = 63, + SystemZ_G_EXTRACT = 64, + SystemZ_G_UNMERGE_VALUES = 65, + SystemZ_G_INSERT = 66, + SystemZ_G_MERGE_VALUES = 67, + SystemZ_G_BUILD_VECTOR = 68, + SystemZ_G_BUILD_VECTOR_TRUNC = 69, + SystemZ_G_CONCAT_VECTORS = 70, + SystemZ_G_PTRTOINT = 71, + SystemZ_G_INTTOPTR = 72, + SystemZ_G_BITCAST = 73, + SystemZ_G_FREEZE = 74, + SystemZ_G_CONSTANT_FOLD_BARRIER = 75, + SystemZ_G_INTRINSIC_FPTRUNC_ROUND = 76, + SystemZ_G_INTRINSIC_TRUNC = 77, + SystemZ_G_INTRINSIC_ROUND = 78, + SystemZ_G_INTRINSIC_LRINT = 79, + SystemZ_G_INTRINSIC_ROUNDEVEN = 80, + SystemZ_G_READCYCLECOUNTER = 81, + SystemZ_G_LOAD = 82, + SystemZ_G_SEXTLOAD = 83, + SystemZ_G_ZEXTLOAD = 84, + SystemZ_G_INDEXED_LOAD = 85, + SystemZ_G_INDEXED_SEXTLOAD = 86, + SystemZ_G_INDEXED_ZEXTLOAD = 87, + SystemZ_G_STORE = 88, + SystemZ_G_INDEXED_STORE = 89, + SystemZ_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90, + SystemZ_G_ATOMIC_CMPXCHG = 91, + SystemZ_G_ATOMICRMW_XCHG = 92, + SystemZ_G_ATOMICRMW_ADD = 93, + SystemZ_G_ATOMICRMW_SUB = 94, + SystemZ_G_ATOMICRMW_AND = 95, + SystemZ_G_ATOMICRMW_NAND = 96, + SystemZ_G_ATOMICRMW_OR = 97, + SystemZ_G_ATOMICRMW_XOR = 98, + SystemZ_G_ATOMICRMW_MAX = 99, + SystemZ_G_ATOMICRMW_MIN = 100, + SystemZ_G_ATOMICRMW_UMAX = 101, + SystemZ_G_ATOMICRMW_UMIN = 102, + SystemZ_G_ATOMICRMW_FADD = 103, + SystemZ_G_ATOMICRMW_FSUB = 104, + SystemZ_G_ATOMICRMW_FMAX = 105, + SystemZ_G_ATOMICRMW_FMIN = 106, + SystemZ_G_ATOMICRMW_UINC_WRAP = 107, + SystemZ_G_ATOMICRMW_UDEC_WRAP = 108, + SystemZ_G_FENCE = 109, + SystemZ_G_PREFETCH = 110, + SystemZ_G_BRCOND = 111, + SystemZ_G_BRINDIRECT = 112, + SystemZ_G_INVOKE_REGION_START = 113, + SystemZ_G_INTRINSIC = 114, + SystemZ_G_INTRINSIC_W_SIDE_EFFECTS = 115, + SystemZ_G_INTRINSIC_CONVERGENT = 116, + SystemZ_G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117, + SystemZ_G_ANYEXT = 118, + SystemZ_G_TRUNC = 119, + SystemZ_G_CONSTANT = 120, + SystemZ_G_FCONSTANT = 121, + SystemZ_G_VASTART = 122, + SystemZ_G_VAARG = 123, + SystemZ_G_SEXT = 124, + SystemZ_G_SEXT_INREG = 125, + SystemZ_G_ZEXT = 126, + SystemZ_G_SHL = 127, + SystemZ_G_LSHR = 128, + SystemZ_G_ASHR = 129, + SystemZ_G_FSHL = 130, + SystemZ_G_FSHR = 131, + SystemZ_G_ROTR = 132, + SystemZ_G_ROTL = 133, + SystemZ_G_ICMP = 134, + SystemZ_G_FCMP = 135, + SystemZ_G_SELECT = 136, + SystemZ_G_UADDO = 137, + SystemZ_G_UADDE = 138, + SystemZ_G_USUBO = 139, + SystemZ_G_USUBE = 140, + SystemZ_G_SADDO = 141, + SystemZ_G_SADDE = 142, + SystemZ_G_SSUBO = 143, + SystemZ_G_SSUBE = 144, + SystemZ_G_UMULO = 145, + SystemZ_G_SMULO = 146, + SystemZ_G_UMULH = 147, + SystemZ_G_SMULH = 148, + SystemZ_G_UADDSAT = 149, + SystemZ_G_SADDSAT = 150, + SystemZ_G_USUBSAT = 151, + SystemZ_G_SSUBSAT = 152, + SystemZ_G_USHLSAT = 153, + SystemZ_G_SSHLSAT = 154, + SystemZ_G_SMULFIX = 155, + SystemZ_G_UMULFIX = 156, + SystemZ_G_SMULFIXSAT = 157, + SystemZ_G_UMULFIXSAT = 158, + SystemZ_G_SDIVFIX = 159, + SystemZ_G_UDIVFIX = 160, + SystemZ_G_SDIVFIXSAT = 161, + SystemZ_G_UDIVFIXSAT = 162, + SystemZ_G_FADD = 163, + SystemZ_G_FSUB = 164, + SystemZ_G_FMUL = 165, + SystemZ_G_FMA = 166, + SystemZ_G_FMAD = 167, + SystemZ_G_FDIV = 168, + SystemZ_G_FREM = 169, + SystemZ_G_FPOW = 170, + SystemZ_G_FPOWI = 171, + SystemZ_G_FEXP = 172, + SystemZ_G_FEXP2 = 173, + SystemZ_G_FEXP10 = 174, + SystemZ_G_FLOG = 175, + SystemZ_G_FLOG2 = 176, + SystemZ_G_FLOG10 = 177, + SystemZ_G_FLDEXP = 178, + SystemZ_G_FFREXP = 179, + SystemZ_G_FNEG = 180, + SystemZ_G_FPEXT = 181, + SystemZ_G_FPTRUNC = 182, + SystemZ_G_FPTOSI = 183, + SystemZ_G_FPTOUI = 184, + SystemZ_G_SITOFP = 185, + SystemZ_G_UITOFP = 186, + SystemZ_G_FABS = 187, + SystemZ_G_FCOPYSIGN = 188, + SystemZ_G_IS_FPCLASS = 189, + SystemZ_G_FCANONICALIZE = 190, + SystemZ_G_FMINNUM = 191, + SystemZ_G_FMAXNUM = 192, + SystemZ_G_FMINNUM_IEEE = 193, + SystemZ_G_FMAXNUM_IEEE = 194, + SystemZ_G_FMINIMUM = 195, + SystemZ_G_FMAXIMUM = 196, + SystemZ_G_GET_FPENV = 197, + SystemZ_G_SET_FPENV = 198, + SystemZ_G_RESET_FPENV = 199, + SystemZ_G_GET_FPMODE = 200, + SystemZ_G_SET_FPMODE = 201, + SystemZ_G_RESET_FPMODE = 202, + SystemZ_G_PTR_ADD = 203, + SystemZ_G_PTRMASK = 204, + SystemZ_G_SMIN = 205, + SystemZ_G_SMAX = 206, + SystemZ_G_UMIN = 207, + SystemZ_G_UMAX = 208, + SystemZ_G_ABS = 209, + SystemZ_G_LROUND = 210, + SystemZ_G_LLROUND = 211, + SystemZ_G_BR = 212, + SystemZ_G_BRJT = 213, + SystemZ_G_INSERT_VECTOR_ELT = 214, + SystemZ_G_EXTRACT_VECTOR_ELT = 215, + SystemZ_G_SHUFFLE_VECTOR = 216, + SystemZ_G_CTTZ = 217, + SystemZ_G_CTTZ_ZERO_UNDEF = 218, + SystemZ_G_CTLZ = 219, + SystemZ_G_CTLZ_ZERO_UNDEF = 220, + SystemZ_G_CTPOP = 221, + SystemZ_G_BSWAP = 222, + SystemZ_G_BITREVERSE = 223, + SystemZ_G_FCEIL = 224, + SystemZ_G_FCOS = 225, + SystemZ_G_FSIN = 226, + SystemZ_G_FSQRT = 227, + SystemZ_G_FFLOOR = 228, + SystemZ_G_FRINT = 229, + SystemZ_G_FNEARBYINT = 230, + SystemZ_G_ADDRSPACE_CAST = 231, + SystemZ_G_BLOCK_ADDR = 232, + SystemZ_G_JUMP_TABLE = 233, + SystemZ_G_DYN_STACKALLOC = 234, + SystemZ_G_STACKSAVE = 235, + SystemZ_G_STACKRESTORE = 236, + SystemZ_G_STRICT_FADD = 237, + SystemZ_G_STRICT_FSUB = 238, + SystemZ_G_STRICT_FMUL = 239, + SystemZ_G_STRICT_FDIV = 240, + SystemZ_G_STRICT_FREM = 241, + SystemZ_G_STRICT_FMA = 242, + SystemZ_G_STRICT_FSQRT = 243, + SystemZ_G_STRICT_FLDEXP = 244, + SystemZ_G_READ_REGISTER = 245, + SystemZ_G_WRITE_REGISTER = 246, + SystemZ_G_MEMCPY = 247, + SystemZ_G_MEMCPY_INLINE = 248, + SystemZ_G_MEMMOVE = 249, + SystemZ_G_MEMSET = 250, + SystemZ_G_BZERO = 251, + SystemZ_G_VECREDUCE_SEQ_FADD = 252, + SystemZ_G_VECREDUCE_SEQ_FMUL = 253, + SystemZ_G_VECREDUCE_FADD = 254, + SystemZ_G_VECREDUCE_FMUL = 255, + SystemZ_G_VECREDUCE_FMAX = 256, + SystemZ_G_VECREDUCE_FMIN = 257, + SystemZ_G_VECREDUCE_FMAXIMUM = 258, + SystemZ_G_VECREDUCE_FMINIMUM = 259, + SystemZ_G_VECREDUCE_ADD = 260, + SystemZ_G_VECREDUCE_MUL = 261, + SystemZ_G_VECREDUCE_AND = 262, + SystemZ_G_VECREDUCE_OR = 263, + SystemZ_G_VECREDUCE_XOR = 264, + SystemZ_G_VECREDUCE_SMAX = 265, + SystemZ_G_VECREDUCE_SMIN = 266, + SystemZ_G_VECREDUCE_UMAX = 267, + SystemZ_G_VECREDUCE_UMIN = 268, + SystemZ_G_SBFX = 269, + SystemZ_G_UBFX = 270, + SystemZ_ADA_ENTRY = 271, + SystemZ_ADA_ENTRY_VALUE = 272, + SystemZ_ADB_MemFoldPseudo = 273, + SystemZ_ADJCALLSTACKDOWN = 274, + SystemZ_ADJCALLSTACKUP = 275, + SystemZ_ADJDYNALLOC = 276, + SystemZ_AEB_MemFoldPseudo = 277, + SystemZ_AEXT128 = 278, + SystemZ_AFIMux = 279, + SystemZ_AG_MemFoldPseudo = 280, + SystemZ_AHIMux = 281, + SystemZ_AHIMuxK = 282, + SystemZ_ALG_MemFoldPseudo = 283, + SystemZ_AL_MemFoldPseudo = 284, + SystemZ_ATOMIC_CMP_SWAPW = 285, + SystemZ_ATOMIC_LOADW_AFI = 286, + SystemZ_ATOMIC_LOADW_AR = 287, + SystemZ_ATOMIC_LOADW_MAX = 288, + SystemZ_ATOMIC_LOADW_MIN = 289, + SystemZ_ATOMIC_LOADW_NILH = 290, + SystemZ_ATOMIC_LOADW_NILHi = 291, + SystemZ_ATOMIC_LOADW_NR = 292, + SystemZ_ATOMIC_LOADW_NRi = 293, + SystemZ_ATOMIC_LOADW_OILH = 294, + SystemZ_ATOMIC_LOADW_OR = 295, + SystemZ_ATOMIC_LOADW_SR = 296, + SystemZ_ATOMIC_LOADW_UMAX = 297, + SystemZ_ATOMIC_LOADW_UMIN = 298, + SystemZ_ATOMIC_LOADW_XILF = 299, + SystemZ_ATOMIC_LOADW_XR = 300, + SystemZ_ATOMIC_SWAPW = 301, + SystemZ_A_MemFoldPseudo = 302, + SystemZ_CFIMux = 303, + SystemZ_CGIBCall = 304, + SystemZ_CGIBReturn = 305, + SystemZ_CGRBCall = 306, + SystemZ_CGRBReturn = 307, + SystemZ_CHIMux = 308, + SystemZ_CIBCall = 309, + SystemZ_CIBReturn = 310, + SystemZ_CLCImm = 311, + SystemZ_CLCReg = 312, + SystemZ_CLFIMux = 313, + SystemZ_CLGIBCall = 314, + SystemZ_CLGIBReturn = 315, + SystemZ_CLGRBCall = 316, + SystemZ_CLGRBReturn = 317, + SystemZ_CLIBCall = 318, + SystemZ_CLIBReturn = 319, + SystemZ_CLMux = 320, + SystemZ_CLRBCall = 321, + SystemZ_CLRBReturn = 322, + SystemZ_CLSTLoop = 323, + SystemZ_CMux = 324, + SystemZ_CRBCall = 325, + SystemZ_CRBReturn = 326, + SystemZ_CallBASR = 327, + SystemZ_CallBASR_STACKEXT = 328, + SystemZ_CallBASR_XPLINK64 = 329, + SystemZ_CallBCR = 330, + SystemZ_CallBR = 331, + SystemZ_CallBRASL = 332, + SystemZ_CallBRASL_XPLINK64 = 333, + SystemZ_CallBRCL = 334, + SystemZ_CallJG = 335, + SystemZ_CondReturn = 336, + SystemZ_CondReturn_XPLINK = 337, + SystemZ_CondStore16 = 338, + SystemZ_CondStore16Inv = 339, + SystemZ_CondStore16Mux = 340, + SystemZ_CondStore16MuxInv = 341, + SystemZ_CondStore32 = 342, + SystemZ_CondStore32Inv = 343, + SystemZ_CondStore32Mux = 344, + SystemZ_CondStore32MuxInv = 345, + SystemZ_CondStore64 = 346, + SystemZ_CondStore64Inv = 347, + SystemZ_CondStore8 = 348, + SystemZ_CondStore8Inv = 349, + SystemZ_CondStore8Mux = 350, + SystemZ_CondStore8MuxInv = 351, + SystemZ_CondStoreF32 = 352, + SystemZ_CondStoreF32Inv = 353, + SystemZ_CondStoreF64 = 354, + SystemZ_CondStoreF64Inv = 355, + SystemZ_CondTrap = 356, + SystemZ_DDB_MemFoldPseudo = 357, + SystemZ_DEB_MemFoldPseudo = 358, + SystemZ_EXRL_Pseudo = 359, + SystemZ_GOT = 360, + SystemZ_IIFMux = 361, + SystemZ_IIHF64 = 362, + SystemZ_IIHH64 = 363, + SystemZ_IIHL64 = 364, + SystemZ_IIHMux = 365, + SystemZ_IILF64 = 366, + SystemZ_IILH64 = 367, + SystemZ_IILL64 = 368, + SystemZ_IILMux = 369, + SystemZ_L128 = 370, + SystemZ_LBMux = 371, + SystemZ_LEFR = 372, + SystemZ_LFER = 373, + SystemZ_LHIMux = 374, + SystemZ_LHMux = 375, + SystemZ_LLCMux = 376, + SystemZ_LLCRMux = 377, + SystemZ_LLHMux = 378, + SystemZ_LLHRMux = 379, + SystemZ_LMux = 380, + SystemZ_LOCG_MemFoldPseudo = 381, + SystemZ_LOCHIMux = 382, + SystemZ_LOCMux = 383, + SystemZ_LOCMux_MemFoldPseudo = 384, + SystemZ_LOCRMux = 385, + SystemZ_LTDBRCompare_Pseudo = 386, + SystemZ_LTEBRCompare_Pseudo = 387, + SystemZ_LTXBRCompare_Pseudo = 388, + SystemZ_LX = 389, + SystemZ_MADB_MemFoldPseudo = 390, + SystemZ_MAEB_MemFoldPseudo = 391, + SystemZ_MDB_MemFoldPseudo = 392, + SystemZ_MEEB_MemFoldPseudo = 393, + SystemZ_MSC_MemFoldPseudo = 394, + SystemZ_MSDB_MemFoldPseudo = 395, + SystemZ_MSEB_MemFoldPseudo = 396, + SystemZ_MSGC_MemFoldPseudo = 397, + SystemZ_MVCImm = 398, + SystemZ_MVCReg = 399, + SystemZ_MVSTLoop = 400, + SystemZ_MemsetImmImm = 401, + SystemZ_MemsetImmReg = 402, + SystemZ_MemsetRegImm = 403, + SystemZ_MemsetRegReg = 404, + SystemZ_NCImm = 405, + SystemZ_NCReg = 406, + SystemZ_NG_MemFoldPseudo = 407, + SystemZ_NIFMux = 408, + SystemZ_NIHF64 = 409, + SystemZ_NIHH64 = 410, + SystemZ_NIHL64 = 411, + SystemZ_NIHMux = 412, + SystemZ_NILF64 = 413, + SystemZ_NILH64 = 414, + SystemZ_NILL64 = 415, + SystemZ_NILMux = 416, + SystemZ_N_MemFoldPseudo = 417, + SystemZ_OCImm = 418, + SystemZ_OCReg = 419, + SystemZ_OG_MemFoldPseudo = 420, + SystemZ_OIFMux = 421, + SystemZ_OIHF64 = 422, + SystemZ_OIHH64 = 423, + SystemZ_OIHL64 = 424, + SystemZ_OIHMux = 425, + SystemZ_OILF64 = 426, + SystemZ_OILH64 = 427, + SystemZ_OILL64 = 428, + SystemZ_OILMux = 429, + SystemZ_O_MemFoldPseudo = 430, + SystemZ_PAIR128 = 431, + SystemZ_PROBED_ALLOCA = 432, + SystemZ_PROBED_STACKALLOC = 433, + SystemZ_RISBHH = 434, + SystemZ_RISBHL = 435, + SystemZ_RISBLH = 436, + SystemZ_RISBLL = 437, + SystemZ_RISBMux = 438, + SystemZ_Return = 439, + SystemZ_Return_XPLINK = 440, + SystemZ_SCmp128Hi = 441, + SystemZ_SDB_MemFoldPseudo = 442, + SystemZ_SEB_MemFoldPseudo = 443, + SystemZ_SELRMux = 444, + SystemZ_SG_MemFoldPseudo = 445, + SystemZ_SLG_MemFoldPseudo = 446, + SystemZ_SL_MemFoldPseudo = 447, + SystemZ_SRSTLoop = 448, + SystemZ_ST128 = 449, + SystemZ_STCMux = 450, + SystemZ_STHMux = 451, + SystemZ_STMux = 452, + SystemZ_STOCMux = 453, + SystemZ_STX = 454, + SystemZ_S_MemFoldPseudo = 455, + SystemZ_Select128 = 456, + SystemZ_Select32 = 457, + SystemZ_Select64 = 458, + SystemZ_SelectF128 = 459, + SystemZ_SelectF32 = 460, + SystemZ_SelectF64 = 461, + SystemZ_SelectVR128 = 462, + SystemZ_SelectVR32 = 463, + SystemZ_SelectVR64 = 464, + SystemZ_Serialize = 465, + SystemZ_TBEGIN_nofloat = 466, + SystemZ_TLS_GDCALL = 467, + SystemZ_TLS_LDCALL = 468, + SystemZ_TMHH64 = 469, + SystemZ_TMHL64 = 470, + SystemZ_TMHMux = 471, + SystemZ_TMLH64 = 472, + SystemZ_TMLL64 = 473, + SystemZ_TMLMux = 474, + SystemZ_Trap = 475, + SystemZ_UCmp128Hi = 476, + SystemZ_VL32 = 477, + SystemZ_VL64 = 478, + SystemZ_VLR32 = 479, + SystemZ_VLR64 = 480, + SystemZ_VLVGP32 = 481, + SystemZ_VST32 = 482, + SystemZ_VST64 = 483, + SystemZ_XCImm = 484, + SystemZ_XCReg = 485, + SystemZ_XG_MemFoldPseudo = 486, + SystemZ_XIFMux = 487, + SystemZ_XIHF64 = 488, + SystemZ_XILF64 = 489, + SystemZ_XPLINK_STACKALLOC = 490, + SystemZ_X_MemFoldPseudo = 491, + SystemZ_ZEXT128 = 492, + SystemZ_A = 493, + SystemZ_AD = 494, + SystemZ_ADB = 495, + SystemZ_ADBR = 496, + SystemZ_ADR = 497, + SystemZ_ADTR = 498, + SystemZ_ADTRA = 499, + SystemZ_AE = 500, + SystemZ_AEB = 501, + SystemZ_AEBR = 502, + SystemZ_AER = 503, + SystemZ_AFI = 504, + SystemZ_AG = 505, + SystemZ_AGF = 506, + SystemZ_AGFI = 507, + SystemZ_AGFR = 508, + SystemZ_AGH = 509, + SystemZ_AGHI = 510, + SystemZ_AGHIK = 511, + SystemZ_AGR = 512, + SystemZ_AGRK = 513, + SystemZ_AGSI = 514, + SystemZ_AH = 515, + SystemZ_AHHHR = 516, + SystemZ_AHHLR = 517, + SystemZ_AHI = 518, + SystemZ_AHIK = 519, + SystemZ_AHY = 520, + SystemZ_AIH = 521, + SystemZ_AL = 522, + SystemZ_ALC = 523, + SystemZ_ALCG = 524, + SystemZ_ALCGR = 525, + SystemZ_ALCR = 526, + SystemZ_ALFI = 527, + SystemZ_ALG = 528, + SystemZ_ALGF = 529, + SystemZ_ALGFI = 530, + SystemZ_ALGFR = 531, + SystemZ_ALGHSIK = 532, + SystemZ_ALGR = 533, + SystemZ_ALGRK = 534, + SystemZ_ALGSI = 535, + SystemZ_ALHHHR = 536, + SystemZ_ALHHLR = 537, + SystemZ_ALHSIK = 538, + SystemZ_ALR = 539, + SystemZ_ALRK = 540, + SystemZ_ALSI = 541, + SystemZ_ALSIH = 542, + SystemZ_ALSIHN = 543, + SystemZ_ALY = 544, + SystemZ_AP = 545, + SystemZ_AR = 546, + SystemZ_ARK = 547, + SystemZ_ASI = 548, + SystemZ_AU = 549, + SystemZ_AUR = 550, + SystemZ_AW = 551, + SystemZ_AWR = 552, + SystemZ_AXBR = 553, + SystemZ_AXR = 554, + SystemZ_AXTR = 555, + SystemZ_AXTRA = 556, + SystemZ_AY = 557, + SystemZ_B = 558, + SystemZ_BAKR = 559, + SystemZ_BAL = 560, + SystemZ_BALR = 561, + SystemZ_BAS = 562, + SystemZ_BASR = 563, + SystemZ_BASSM = 564, + SystemZ_BAsmE = 565, + SystemZ_BAsmH = 566, + SystemZ_BAsmHE = 567, + SystemZ_BAsmL = 568, + SystemZ_BAsmLE = 569, + SystemZ_BAsmLH = 570, + SystemZ_BAsmM = 571, + SystemZ_BAsmNE = 572, + SystemZ_BAsmNH = 573, + SystemZ_BAsmNHE = 574, + SystemZ_BAsmNL = 575, + SystemZ_BAsmNLE = 576, + SystemZ_BAsmNLH = 577, + SystemZ_BAsmNM = 578, + SystemZ_BAsmNO = 579, + SystemZ_BAsmNP = 580, + SystemZ_BAsmNZ = 581, + SystemZ_BAsmO = 582, + SystemZ_BAsmP = 583, + SystemZ_BAsmZ = 584, + SystemZ_BC = 585, + SystemZ_BCAsm = 586, + SystemZ_BCR = 587, + SystemZ_BCRAsm = 588, + SystemZ_BCT = 589, + SystemZ_BCTG = 590, + SystemZ_BCTGR = 591, + SystemZ_BCTR = 592, + SystemZ_BI = 593, + SystemZ_BIAsmE = 594, + SystemZ_BIAsmH = 595, + SystemZ_BIAsmHE = 596, + SystemZ_BIAsmL = 597, + SystemZ_BIAsmLE = 598, + SystemZ_BIAsmLH = 599, + SystemZ_BIAsmM = 600, + SystemZ_BIAsmNE = 601, + SystemZ_BIAsmNH = 602, + SystemZ_BIAsmNHE = 603, + SystemZ_BIAsmNL = 604, + SystemZ_BIAsmNLE = 605, + SystemZ_BIAsmNLH = 606, + SystemZ_BIAsmNM = 607, + SystemZ_BIAsmNO = 608, + SystemZ_BIAsmNP = 609, + SystemZ_BIAsmNZ = 610, + SystemZ_BIAsmO = 611, + SystemZ_BIAsmP = 612, + SystemZ_BIAsmZ = 613, + SystemZ_BIC = 614, + SystemZ_BICAsm = 615, + SystemZ_BPP = 616, + SystemZ_BPRP = 617, + SystemZ_BR = 618, + SystemZ_BRAS = 619, + SystemZ_BRASL = 620, + SystemZ_BRAsmE = 621, + SystemZ_BRAsmH = 622, + SystemZ_BRAsmHE = 623, + SystemZ_BRAsmL = 624, + SystemZ_BRAsmLE = 625, + SystemZ_BRAsmLH = 626, + SystemZ_BRAsmM = 627, + SystemZ_BRAsmNE = 628, + SystemZ_BRAsmNH = 629, + SystemZ_BRAsmNHE = 630, + SystemZ_BRAsmNL = 631, + SystemZ_BRAsmNLE = 632, + SystemZ_BRAsmNLH = 633, + SystemZ_BRAsmNM = 634, + SystemZ_BRAsmNO = 635, + SystemZ_BRAsmNP = 636, + SystemZ_BRAsmNZ = 637, + SystemZ_BRAsmO = 638, + SystemZ_BRAsmP = 639, + SystemZ_BRAsmZ = 640, + SystemZ_BRC = 641, + SystemZ_BRCAsm = 642, + SystemZ_BRCL = 643, + SystemZ_BRCLAsm = 644, + SystemZ_BRCT = 645, + SystemZ_BRCTG = 646, + SystemZ_BRCTH = 647, + SystemZ_BRXH = 648, + SystemZ_BRXHG = 649, + SystemZ_BRXLE = 650, + SystemZ_BRXLG = 651, + SystemZ_BSA = 652, + SystemZ_BSG = 653, + SystemZ_BSM = 654, + SystemZ_BXH = 655, + SystemZ_BXHG = 656, + SystemZ_BXLE = 657, + SystemZ_BXLEG = 658, + SystemZ_C = 659, + SystemZ_CD = 660, + SystemZ_CDB = 661, + SystemZ_CDBR = 662, + SystemZ_CDFBR = 663, + SystemZ_CDFBRA = 664, + SystemZ_CDFR = 665, + SystemZ_CDFTR = 666, + SystemZ_CDGBR = 667, + SystemZ_CDGBRA = 668, + SystemZ_CDGR = 669, + SystemZ_CDGTR = 670, + SystemZ_CDGTRA = 671, + SystemZ_CDLFBR = 672, + SystemZ_CDLFTR = 673, + SystemZ_CDLGBR = 674, + SystemZ_CDLGTR = 675, + SystemZ_CDPT = 676, + SystemZ_CDR = 677, + SystemZ_CDS = 678, + SystemZ_CDSG = 679, + SystemZ_CDSTR = 680, + SystemZ_CDSY = 681, + SystemZ_CDTR = 682, + SystemZ_CDUTR = 683, + SystemZ_CDZT = 684, + SystemZ_CE = 685, + SystemZ_CEB = 686, + SystemZ_CEBR = 687, + SystemZ_CEDTR = 688, + SystemZ_CEFBR = 689, + SystemZ_CEFBRA = 690, + SystemZ_CEFR = 691, + SystemZ_CEGBR = 692, + SystemZ_CEGBRA = 693, + SystemZ_CEGR = 694, + SystemZ_CELFBR = 695, + SystemZ_CELGBR = 696, + SystemZ_CER = 697, + SystemZ_CEXTR = 698, + SystemZ_CFC = 699, + SystemZ_CFDBR = 700, + SystemZ_CFDBRA = 701, + SystemZ_CFDR = 702, + SystemZ_CFDTR = 703, + SystemZ_CFEBR = 704, + SystemZ_CFEBRA = 705, + SystemZ_CFER = 706, + SystemZ_CFI = 707, + SystemZ_CFXBR = 708, + SystemZ_CFXBRA = 709, + SystemZ_CFXR = 710, + SystemZ_CFXTR = 711, + SystemZ_CG = 712, + SystemZ_CGDBR = 713, + SystemZ_CGDBRA = 714, + SystemZ_CGDR = 715, + SystemZ_CGDTR = 716, + SystemZ_CGDTRA = 717, + SystemZ_CGEBR = 718, + SystemZ_CGEBRA = 719, + SystemZ_CGER = 720, + SystemZ_CGF = 721, + SystemZ_CGFI = 722, + SystemZ_CGFR = 723, + SystemZ_CGFRL = 724, + SystemZ_CGH = 725, + SystemZ_CGHI = 726, + SystemZ_CGHRL = 727, + SystemZ_CGHSI = 728, + SystemZ_CGIB = 729, + SystemZ_CGIBAsm = 730, + SystemZ_CGIBAsmE = 731, + SystemZ_CGIBAsmH = 732, + SystemZ_CGIBAsmHE = 733, + SystemZ_CGIBAsmL = 734, + SystemZ_CGIBAsmLE = 735, + SystemZ_CGIBAsmLH = 736, + SystemZ_CGIBAsmNE = 737, + SystemZ_CGIBAsmNH = 738, + SystemZ_CGIBAsmNHE = 739, + SystemZ_CGIBAsmNL = 740, + SystemZ_CGIBAsmNLE = 741, + SystemZ_CGIBAsmNLH = 742, + SystemZ_CGIJ = 743, + SystemZ_CGIJAsm = 744, + SystemZ_CGIJAsmE = 745, + SystemZ_CGIJAsmH = 746, + SystemZ_CGIJAsmHE = 747, + SystemZ_CGIJAsmL = 748, + SystemZ_CGIJAsmLE = 749, + SystemZ_CGIJAsmLH = 750, + SystemZ_CGIJAsmNE = 751, + SystemZ_CGIJAsmNH = 752, + SystemZ_CGIJAsmNHE = 753, + SystemZ_CGIJAsmNL = 754, + SystemZ_CGIJAsmNLE = 755, + SystemZ_CGIJAsmNLH = 756, + SystemZ_CGIT = 757, + SystemZ_CGITAsm = 758, + SystemZ_CGITAsmE = 759, + SystemZ_CGITAsmH = 760, + SystemZ_CGITAsmHE = 761, + SystemZ_CGITAsmL = 762, + SystemZ_CGITAsmLE = 763, + SystemZ_CGITAsmLH = 764, + SystemZ_CGITAsmNE = 765, + SystemZ_CGITAsmNH = 766, + SystemZ_CGITAsmNHE = 767, + SystemZ_CGITAsmNL = 768, + SystemZ_CGITAsmNLE = 769, + SystemZ_CGITAsmNLH = 770, + SystemZ_CGR = 771, + SystemZ_CGRB = 772, + SystemZ_CGRBAsm = 773, + SystemZ_CGRBAsmE = 774, + SystemZ_CGRBAsmH = 775, + SystemZ_CGRBAsmHE = 776, + SystemZ_CGRBAsmL = 777, + SystemZ_CGRBAsmLE = 778, + SystemZ_CGRBAsmLH = 779, + SystemZ_CGRBAsmNE = 780, + SystemZ_CGRBAsmNH = 781, + SystemZ_CGRBAsmNHE = 782, + SystemZ_CGRBAsmNL = 783, + SystemZ_CGRBAsmNLE = 784, + SystemZ_CGRBAsmNLH = 785, + SystemZ_CGRJ = 786, + SystemZ_CGRJAsm = 787, + SystemZ_CGRJAsmE = 788, + SystemZ_CGRJAsmH = 789, + SystemZ_CGRJAsmHE = 790, + SystemZ_CGRJAsmL = 791, + SystemZ_CGRJAsmLE = 792, + SystemZ_CGRJAsmLH = 793, + SystemZ_CGRJAsmNE = 794, + SystemZ_CGRJAsmNH = 795, + SystemZ_CGRJAsmNHE = 796, + SystemZ_CGRJAsmNL = 797, + SystemZ_CGRJAsmNLE = 798, + SystemZ_CGRJAsmNLH = 799, + SystemZ_CGRL = 800, + SystemZ_CGRT = 801, + SystemZ_CGRTAsm = 802, + SystemZ_CGRTAsmE = 803, + SystemZ_CGRTAsmH = 804, + SystemZ_CGRTAsmHE = 805, + SystemZ_CGRTAsmL = 806, + SystemZ_CGRTAsmLE = 807, + SystemZ_CGRTAsmLH = 808, + SystemZ_CGRTAsmNE = 809, + SystemZ_CGRTAsmNH = 810, + SystemZ_CGRTAsmNHE = 811, + SystemZ_CGRTAsmNL = 812, + SystemZ_CGRTAsmNLE = 813, + SystemZ_CGRTAsmNLH = 814, + SystemZ_CGXBR = 815, + SystemZ_CGXBRA = 816, + SystemZ_CGXR = 817, + SystemZ_CGXTR = 818, + SystemZ_CGXTRA = 819, + SystemZ_CH = 820, + SystemZ_CHF = 821, + SystemZ_CHHR = 822, + SystemZ_CHHSI = 823, + SystemZ_CHI = 824, + SystemZ_CHLR = 825, + SystemZ_CHRL = 826, + SystemZ_CHSI = 827, + SystemZ_CHY = 828, + SystemZ_CIB = 829, + SystemZ_CIBAsm = 830, + SystemZ_CIBAsmE = 831, + SystemZ_CIBAsmH = 832, + SystemZ_CIBAsmHE = 833, + SystemZ_CIBAsmL = 834, + SystemZ_CIBAsmLE = 835, + SystemZ_CIBAsmLH = 836, + SystemZ_CIBAsmNE = 837, + SystemZ_CIBAsmNH = 838, + SystemZ_CIBAsmNHE = 839, + SystemZ_CIBAsmNL = 840, + SystemZ_CIBAsmNLE = 841, + SystemZ_CIBAsmNLH = 842, + SystemZ_CIH = 843, + SystemZ_CIJ = 844, + SystemZ_CIJAsm = 845, + SystemZ_CIJAsmE = 846, + SystemZ_CIJAsmH = 847, + SystemZ_CIJAsmHE = 848, + SystemZ_CIJAsmL = 849, + SystemZ_CIJAsmLE = 850, + SystemZ_CIJAsmLH = 851, + SystemZ_CIJAsmNE = 852, + SystemZ_CIJAsmNH = 853, + SystemZ_CIJAsmNHE = 854, + SystemZ_CIJAsmNL = 855, + SystemZ_CIJAsmNLE = 856, + SystemZ_CIJAsmNLH = 857, + SystemZ_CIT = 858, + SystemZ_CITAsm = 859, + SystemZ_CITAsmE = 860, + SystemZ_CITAsmH = 861, + SystemZ_CITAsmHE = 862, + SystemZ_CITAsmL = 863, + SystemZ_CITAsmLE = 864, + SystemZ_CITAsmLH = 865, + SystemZ_CITAsmNE = 866, + SystemZ_CITAsmNH = 867, + SystemZ_CITAsmNHE = 868, + SystemZ_CITAsmNL = 869, + SystemZ_CITAsmNLE = 870, + SystemZ_CITAsmNLH = 871, + SystemZ_CKSM = 872, + SystemZ_CL = 873, + SystemZ_CLC = 874, + SystemZ_CLCL = 875, + SystemZ_CLCLE = 876, + SystemZ_CLCLU = 877, + SystemZ_CLFDBR = 878, + SystemZ_CLFDTR = 879, + SystemZ_CLFEBR = 880, + SystemZ_CLFHSI = 881, + SystemZ_CLFI = 882, + SystemZ_CLFIT = 883, + SystemZ_CLFITAsm = 884, + SystemZ_CLFITAsmE = 885, + SystemZ_CLFITAsmH = 886, + SystemZ_CLFITAsmHE = 887, + SystemZ_CLFITAsmL = 888, + SystemZ_CLFITAsmLE = 889, + SystemZ_CLFITAsmLH = 890, + SystemZ_CLFITAsmNE = 891, + SystemZ_CLFITAsmNH = 892, + SystemZ_CLFITAsmNHE = 893, + SystemZ_CLFITAsmNL = 894, + SystemZ_CLFITAsmNLE = 895, + SystemZ_CLFITAsmNLH = 896, + SystemZ_CLFXBR = 897, + SystemZ_CLFXTR = 898, + SystemZ_CLG = 899, + SystemZ_CLGDBR = 900, + SystemZ_CLGDTR = 901, + SystemZ_CLGEBR = 902, + SystemZ_CLGF = 903, + SystemZ_CLGFI = 904, + SystemZ_CLGFR = 905, + SystemZ_CLGFRL = 906, + SystemZ_CLGHRL = 907, + SystemZ_CLGHSI = 908, + SystemZ_CLGIB = 909, + SystemZ_CLGIBAsm = 910, + SystemZ_CLGIBAsmE = 911, + SystemZ_CLGIBAsmH = 912, + SystemZ_CLGIBAsmHE = 913, + SystemZ_CLGIBAsmL = 914, + SystemZ_CLGIBAsmLE = 915, + SystemZ_CLGIBAsmLH = 916, + SystemZ_CLGIBAsmNE = 917, + SystemZ_CLGIBAsmNH = 918, + SystemZ_CLGIBAsmNHE = 919, + SystemZ_CLGIBAsmNL = 920, + SystemZ_CLGIBAsmNLE = 921, + SystemZ_CLGIBAsmNLH = 922, + SystemZ_CLGIJ = 923, + SystemZ_CLGIJAsm = 924, + SystemZ_CLGIJAsmE = 925, + SystemZ_CLGIJAsmH = 926, + SystemZ_CLGIJAsmHE = 927, + SystemZ_CLGIJAsmL = 928, + SystemZ_CLGIJAsmLE = 929, + SystemZ_CLGIJAsmLH = 930, + SystemZ_CLGIJAsmNE = 931, + SystemZ_CLGIJAsmNH = 932, + SystemZ_CLGIJAsmNHE = 933, + SystemZ_CLGIJAsmNL = 934, + SystemZ_CLGIJAsmNLE = 935, + SystemZ_CLGIJAsmNLH = 936, + SystemZ_CLGIT = 937, + SystemZ_CLGITAsm = 938, + SystemZ_CLGITAsmE = 939, + SystemZ_CLGITAsmH = 940, + SystemZ_CLGITAsmHE = 941, + SystemZ_CLGITAsmL = 942, + SystemZ_CLGITAsmLE = 943, + SystemZ_CLGITAsmLH = 944, + SystemZ_CLGITAsmNE = 945, + SystemZ_CLGITAsmNH = 946, + SystemZ_CLGITAsmNHE = 947, + SystemZ_CLGITAsmNL = 948, + SystemZ_CLGITAsmNLE = 949, + SystemZ_CLGITAsmNLH = 950, + SystemZ_CLGR = 951, + SystemZ_CLGRB = 952, + SystemZ_CLGRBAsm = 953, + SystemZ_CLGRBAsmE = 954, + SystemZ_CLGRBAsmH = 955, + SystemZ_CLGRBAsmHE = 956, + SystemZ_CLGRBAsmL = 957, + SystemZ_CLGRBAsmLE = 958, + SystemZ_CLGRBAsmLH = 959, + SystemZ_CLGRBAsmNE = 960, + SystemZ_CLGRBAsmNH = 961, + SystemZ_CLGRBAsmNHE = 962, + SystemZ_CLGRBAsmNL = 963, + SystemZ_CLGRBAsmNLE = 964, + SystemZ_CLGRBAsmNLH = 965, + SystemZ_CLGRJ = 966, + SystemZ_CLGRJAsm = 967, + SystemZ_CLGRJAsmE = 968, + SystemZ_CLGRJAsmH = 969, + SystemZ_CLGRJAsmHE = 970, + SystemZ_CLGRJAsmL = 971, + SystemZ_CLGRJAsmLE = 972, + SystemZ_CLGRJAsmLH = 973, + SystemZ_CLGRJAsmNE = 974, + SystemZ_CLGRJAsmNH = 975, + SystemZ_CLGRJAsmNHE = 976, + SystemZ_CLGRJAsmNL = 977, + SystemZ_CLGRJAsmNLE = 978, + SystemZ_CLGRJAsmNLH = 979, + SystemZ_CLGRL = 980, + SystemZ_CLGRT = 981, + SystemZ_CLGRTAsm = 982, + SystemZ_CLGRTAsmE = 983, + SystemZ_CLGRTAsmH = 984, + SystemZ_CLGRTAsmHE = 985, + SystemZ_CLGRTAsmL = 986, + SystemZ_CLGRTAsmLE = 987, + SystemZ_CLGRTAsmLH = 988, + SystemZ_CLGRTAsmNE = 989, + SystemZ_CLGRTAsmNH = 990, + SystemZ_CLGRTAsmNHE = 991, + SystemZ_CLGRTAsmNL = 992, + SystemZ_CLGRTAsmNLE = 993, + SystemZ_CLGRTAsmNLH = 994, + SystemZ_CLGT = 995, + SystemZ_CLGTAsm = 996, + SystemZ_CLGTAsmE = 997, + SystemZ_CLGTAsmH = 998, + SystemZ_CLGTAsmHE = 999, + SystemZ_CLGTAsmL = 1000, + SystemZ_CLGTAsmLE = 1001, + SystemZ_CLGTAsmLH = 1002, + SystemZ_CLGTAsmNE = 1003, + SystemZ_CLGTAsmNH = 1004, + SystemZ_CLGTAsmNHE = 1005, + SystemZ_CLGTAsmNL = 1006, + SystemZ_CLGTAsmNLE = 1007, + SystemZ_CLGTAsmNLH = 1008, + SystemZ_CLGXBR = 1009, + SystemZ_CLGXTR = 1010, + SystemZ_CLHF = 1011, + SystemZ_CLHHR = 1012, + SystemZ_CLHHSI = 1013, + SystemZ_CLHLR = 1014, + SystemZ_CLHRL = 1015, + SystemZ_CLI = 1016, + SystemZ_CLIB = 1017, + SystemZ_CLIBAsm = 1018, + SystemZ_CLIBAsmE = 1019, + SystemZ_CLIBAsmH = 1020, + SystemZ_CLIBAsmHE = 1021, + SystemZ_CLIBAsmL = 1022, + SystemZ_CLIBAsmLE = 1023, + SystemZ_CLIBAsmLH = 1024, + SystemZ_CLIBAsmNE = 1025, + SystemZ_CLIBAsmNH = 1026, + SystemZ_CLIBAsmNHE = 1027, + SystemZ_CLIBAsmNL = 1028, + SystemZ_CLIBAsmNLE = 1029, + SystemZ_CLIBAsmNLH = 1030, + SystemZ_CLIH = 1031, + SystemZ_CLIJ = 1032, + SystemZ_CLIJAsm = 1033, + SystemZ_CLIJAsmE = 1034, + SystemZ_CLIJAsmH = 1035, + SystemZ_CLIJAsmHE = 1036, + SystemZ_CLIJAsmL = 1037, + SystemZ_CLIJAsmLE = 1038, + SystemZ_CLIJAsmLH = 1039, + SystemZ_CLIJAsmNE = 1040, + SystemZ_CLIJAsmNH = 1041, + SystemZ_CLIJAsmNHE = 1042, + SystemZ_CLIJAsmNL = 1043, + SystemZ_CLIJAsmNLE = 1044, + SystemZ_CLIJAsmNLH = 1045, + SystemZ_CLIY = 1046, + SystemZ_CLM = 1047, + SystemZ_CLMH = 1048, + SystemZ_CLMY = 1049, + SystemZ_CLR = 1050, + SystemZ_CLRB = 1051, + SystemZ_CLRBAsm = 1052, + SystemZ_CLRBAsmE = 1053, + SystemZ_CLRBAsmH = 1054, + SystemZ_CLRBAsmHE = 1055, + SystemZ_CLRBAsmL = 1056, + SystemZ_CLRBAsmLE = 1057, + SystemZ_CLRBAsmLH = 1058, + SystemZ_CLRBAsmNE = 1059, + SystemZ_CLRBAsmNH = 1060, + SystemZ_CLRBAsmNHE = 1061, + SystemZ_CLRBAsmNL = 1062, + SystemZ_CLRBAsmNLE = 1063, + SystemZ_CLRBAsmNLH = 1064, + SystemZ_CLRJ = 1065, + SystemZ_CLRJAsm = 1066, + SystemZ_CLRJAsmE = 1067, + SystemZ_CLRJAsmH = 1068, + SystemZ_CLRJAsmHE = 1069, + SystemZ_CLRJAsmL = 1070, + SystemZ_CLRJAsmLE = 1071, + SystemZ_CLRJAsmLH = 1072, + SystemZ_CLRJAsmNE = 1073, + SystemZ_CLRJAsmNH = 1074, + SystemZ_CLRJAsmNHE = 1075, + SystemZ_CLRJAsmNL = 1076, + SystemZ_CLRJAsmNLE = 1077, + SystemZ_CLRJAsmNLH = 1078, + SystemZ_CLRL = 1079, + SystemZ_CLRT = 1080, + SystemZ_CLRTAsm = 1081, + SystemZ_CLRTAsmE = 1082, + SystemZ_CLRTAsmH = 1083, + SystemZ_CLRTAsmHE = 1084, + SystemZ_CLRTAsmL = 1085, + SystemZ_CLRTAsmLE = 1086, + SystemZ_CLRTAsmLH = 1087, + SystemZ_CLRTAsmNE = 1088, + SystemZ_CLRTAsmNH = 1089, + SystemZ_CLRTAsmNHE = 1090, + SystemZ_CLRTAsmNL = 1091, + SystemZ_CLRTAsmNLE = 1092, + SystemZ_CLRTAsmNLH = 1093, + SystemZ_CLST = 1094, + SystemZ_CLT = 1095, + SystemZ_CLTAsm = 1096, + SystemZ_CLTAsmE = 1097, + SystemZ_CLTAsmH = 1098, + SystemZ_CLTAsmHE = 1099, + SystemZ_CLTAsmL = 1100, + SystemZ_CLTAsmLE = 1101, + SystemZ_CLTAsmLH = 1102, + SystemZ_CLTAsmNE = 1103, + SystemZ_CLTAsmNH = 1104, + SystemZ_CLTAsmNHE = 1105, + SystemZ_CLTAsmNL = 1106, + SystemZ_CLTAsmNLE = 1107, + SystemZ_CLTAsmNLH = 1108, + SystemZ_CLY = 1109, + SystemZ_CMPSC = 1110, + SystemZ_CP = 1111, + SystemZ_CPDT = 1112, + SystemZ_CPSDRdd = 1113, + SystemZ_CPSDRds = 1114, + SystemZ_CPSDRsd = 1115, + SystemZ_CPSDRss = 1116, + SystemZ_CPXT = 1117, + SystemZ_CPYA = 1118, + SystemZ_CR = 1119, + SystemZ_CRB = 1120, + SystemZ_CRBAsm = 1121, + SystemZ_CRBAsmE = 1122, + SystemZ_CRBAsmH = 1123, + SystemZ_CRBAsmHE = 1124, + SystemZ_CRBAsmL = 1125, + SystemZ_CRBAsmLE = 1126, + SystemZ_CRBAsmLH = 1127, + SystemZ_CRBAsmNE = 1128, + SystemZ_CRBAsmNH = 1129, + SystemZ_CRBAsmNHE = 1130, + SystemZ_CRBAsmNL = 1131, + SystemZ_CRBAsmNLE = 1132, + SystemZ_CRBAsmNLH = 1133, + SystemZ_CRDTE = 1134, + SystemZ_CRDTEOpt = 1135, + SystemZ_CRJ = 1136, + SystemZ_CRJAsm = 1137, + SystemZ_CRJAsmE = 1138, + SystemZ_CRJAsmH = 1139, + SystemZ_CRJAsmHE = 1140, + SystemZ_CRJAsmL = 1141, + SystemZ_CRJAsmLE = 1142, + SystemZ_CRJAsmLH = 1143, + SystemZ_CRJAsmNE = 1144, + SystemZ_CRJAsmNH = 1145, + SystemZ_CRJAsmNHE = 1146, + SystemZ_CRJAsmNL = 1147, + SystemZ_CRJAsmNLE = 1148, + SystemZ_CRJAsmNLH = 1149, + SystemZ_CRL = 1150, + SystemZ_CRT = 1151, + SystemZ_CRTAsm = 1152, + SystemZ_CRTAsmE = 1153, + SystemZ_CRTAsmH = 1154, + SystemZ_CRTAsmHE = 1155, + SystemZ_CRTAsmL = 1156, + SystemZ_CRTAsmLE = 1157, + SystemZ_CRTAsmLH = 1158, + SystemZ_CRTAsmNE = 1159, + SystemZ_CRTAsmNH = 1160, + SystemZ_CRTAsmNHE = 1161, + SystemZ_CRTAsmNL = 1162, + SystemZ_CRTAsmNLE = 1163, + SystemZ_CRTAsmNLH = 1164, + SystemZ_CS = 1165, + SystemZ_CSCH = 1166, + SystemZ_CSDTR = 1167, + SystemZ_CSG = 1168, + SystemZ_CSP = 1169, + SystemZ_CSPG = 1170, + SystemZ_CSST = 1171, + SystemZ_CSXTR = 1172, + SystemZ_CSY = 1173, + SystemZ_CU12 = 1174, + SystemZ_CU12Opt = 1175, + SystemZ_CU14 = 1176, + SystemZ_CU14Opt = 1177, + SystemZ_CU21 = 1178, + SystemZ_CU21Opt = 1179, + SystemZ_CU24 = 1180, + SystemZ_CU24Opt = 1181, + SystemZ_CU41 = 1182, + SystemZ_CU42 = 1183, + SystemZ_CUDTR = 1184, + SystemZ_CUSE = 1185, + SystemZ_CUTFU = 1186, + SystemZ_CUTFUOpt = 1187, + SystemZ_CUUTF = 1188, + SystemZ_CUUTFOpt = 1189, + SystemZ_CUXTR = 1190, + SystemZ_CVB = 1191, + SystemZ_CVBG = 1192, + SystemZ_CVBY = 1193, + SystemZ_CVD = 1194, + SystemZ_CVDG = 1195, + SystemZ_CVDY = 1196, + SystemZ_CXBR = 1197, + SystemZ_CXFBR = 1198, + SystemZ_CXFBRA = 1199, + SystemZ_CXFR = 1200, + SystemZ_CXFTR = 1201, + SystemZ_CXGBR = 1202, + SystemZ_CXGBRA = 1203, + SystemZ_CXGR = 1204, + SystemZ_CXGTR = 1205, + SystemZ_CXGTRA = 1206, + SystemZ_CXLFBR = 1207, + SystemZ_CXLFTR = 1208, + SystemZ_CXLGBR = 1209, + SystemZ_CXLGTR = 1210, + SystemZ_CXPT = 1211, + SystemZ_CXR = 1212, + SystemZ_CXSTR = 1213, + SystemZ_CXTR = 1214, + SystemZ_CXUTR = 1215, + SystemZ_CXZT = 1216, + SystemZ_CY = 1217, + SystemZ_CZDT = 1218, + SystemZ_CZXT = 1219, + SystemZ_D = 1220, + SystemZ_DD = 1221, + SystemZ_DDB = 1222, + SystemZ_DDBR = 1223, + SystemZ_DDR = 1224, + SystemZ_DDTR = 1225, + SystemZ_DDTRA = 1226, + SystemZ_DE = 1227, + SystemZ_DEB = 1228, + SystemZ_DEBR = 1229, + SystemZ_DER = 1230, + SystemZ_DFLTCC = 1231, + SystemZ_DIAG = 1232, + SystemZ_DIDBR = 1233, + SystemZ_DIEBR = 1234, + SystemZ_DL = 1235, + SystemZ_DLG = 1236, + SystemZ_DLGR = 1237, + SystemZ_DLR = 1238, + SystemZ_DP = 1239, + SystemZ_DR = 1240, + SystemZ_DSG = 1241, + SystemZ_DSGF = 1242, + SystemZ_DSGFR = 1243, + SystemZ_DSGR = 1244, + SystemZ_DXBR = 1245, + SystemZ_DXR = 1246, + SystemZ_DXTR = 1247, + SystemZ_DXTRA = 1248, + SystemZ_EAR = 1249, + SystemZ_ECAG = 1250, + SystemZ_ECCTR = 1251, + SystemZ_ECPGA = 1252, + SystemZ_ECTG = 1253, + SystemZ_ED = 1254, + SystemZ_EDMK = 1255, + SystemZ_EEDTR = 1256, + SystemZ_EEXTR = 1257, + SystemZ_EFPC = 1258, + SystemZ_EPAIR = 1259, + SystemZ_EPAR = 1260, + SystemZ_EPCTR = 1261, + SystemZ_EPSW = 1262, + SystemZ_EREG = 1263, + SystemZ_EREGG = 1264, + SystemZ_ESAIR = 1265, + SystemZ_ESAR = 1266, + SystemZ_ESDTR = 1267, + SystemZ_ESEA = 1268, + SystemZ_ESTA = 1269, + SystemZ_ESXTR = 1270, + SystemZ_ETND = 1271, + SystemZ_EX = 1272, + SystemZ_EXRL = 1273, + SystemZ_FIDBR = 1274, + SystemZ_FIDBRA = 1275, + SystemZ_FIDR = 1276, + SystemZ_FIDTR = 1277, + SystemZ_FIEBR = 1278, + SystemZ_FIEBRA = 1279, + SystemZ_FIER = 1280, + SystemZ_FIXBR = 1281, + SystemZ_FIXBRA = 1282, + SystemZ_FIXR = 1283, + SystemZ_FIXTR = 1284, + SystemZ_FLOGR = 1285, + SystemZ_HDR = 1286, + SystemZ_HER = 1287, + SystemZ_HSCH = 1288, + SystemZ_IAC = 1289, + SystemZ_IC = 1290, + SystemZ_IC32 = 1291, + SystemZ_IC32Y = 1292, + SystemZ_ICM = 1293, + SystemZ_ICMH = 1294, + SystemZ_ICMY = 1295, + SystemZ_ICY = 1296, + SystemZ_IDTE = 1297, + SystemZ_IDTEOpt = 1298, + SystemZ_IEDTR = 1299, + SystemZ_IEXTR = 1300, + SystemZ_IIHF = 1301, + SystemZ_IIHH = 1302, + SystemZ_IIHL = 1303, + SystemZ_IILF = 1304, + SystemZ_IILH = 1305, + SystemZ_IILL = 1306, + SystemZ_IPK = 1307, + SystemZ_IPM = 1308, + SystemZ_IPTE = 1309, + SystemZ_IPTEOpt = 1310, + SystemZ_IPTEOptOpt = 1311, + SystemZ_IRBM = 1312, + SystemZ_ISKE = 1313, + SystemZ_IVSK = 1314, + SystemZ_InsnE = 1315, + SystemZ_InsnRI = 1316, + SystemZ_InsnRIE = 1317, + SystemZ_InsnRIL = 1318, + SystemZ_InsnRILU = 1319, + SystemZ_InsnRIS = 1320, + SystemZ_InsnRR = 1321, + SystemZ_InsnRRE = 1322, + SystemZ_InsnRRF = 1323, + SystemZ_InsnRRS = 1324, + SystemZ_InsnRS = 1325, + SystemZ_InsnRSE = 1326, + SystemZ_InsnRSI = 1327, + SystemZ_InsnRSY = 1328, + SystemZ_InsnRX = 1329, + SystemZ_InsnRXE = 1330, + SystemZ_InsnRXF = 1331, + SystemZ_InsnRXY = 1332, + SystemZ_InsnS = 1333, + SystemZ_InsnSI = 1334, + SystemZ_InsnSIL = 1335, + SystemZ_InsnSIY = 1336, + SystemZ_InsnSS = 1337, + SystemZ_InsnSSE = 1338, + SystemZ_InsnSSF = 1339, + SystemZ_InsnVRI = 1340, + SystemZ_InsnVRR = 1341, + SystemZ_InsnVRS = 1342, + SystemZ_InsnVRV = 1343, + SystemZ_InsnVRX = 1344, + SystemZ_InsnVSI = 1345, + SystemZ_J = 1346, + SystemZ_JAsmE = 1347, + SystemZ_JAsmH = 1348, + SystemZ_JAsmHE = 1349, + SystemZ_JAsmL = 1350, + SystemZ_JAsmLE = 1351, + SystemZ_JAsmLH = 1352, + SystemZ_JAsmM = 1353, + SystemZ_JAsmNE = 1354, + SystemZ_JAsmNH = 1355, + SystemZ_JAsmNHE = 1356, + SystemZ_JAsmNL = 1357, + SystemZ_JAsmNLE = 1358, + SystemZ_JAsmNLH = 1359, + SystemZ_JAsmNM = 1360, + SystemZ_JAsmNO = 1361, + SystemZ_JAsmNP = 1362, + SystemZ_JAsmNZ = 1363, + SystemZ_JAsmO = 1364, + SystemZ_JAsmP = 1365, + SystemZ_JAsmZ = 1366, + SystemZ_JG = 1367, + SystemZ_JGAsmE = 1368, + SystemZ_JGAsmH = 1369, + SystemZ_JGAsmHE = 1370, + SystemZ_JGAsmL = 1371, + SystemZ_JGAsmLE = 1372, + SystemZ_JGAsmLH = 1373, + SystemZ_JGAsmM = 1374, + SystemZ_JGAsmNE = 1375, + SystemZ_JGAsmNH = 1376, + SystemZ_JGAsmNHE = 1377, + SystemZ_JGAsmNL = 1378, + SystemZ_JGAsmNLE = 1379, + SystemZ_JGAsmNLH = 1380, + SystemZ_JGAsmNM = 1381, + SystemZ_JGAsmNO = 1382, + SystemZ_JGAsmNP = 1383, + SystemZ_JGAsmNZ = 1384, + SystemZ_JGAsmO = 1385, + SystemZ_JGAsmP = 1386, + SystemZ_JGAsmZ = 1387, + SystemZ_KDB = 1388, + SystemZ_KDBR = 1389, + SystemZ_KDSA = 1390, + SystemZ_KDTR = 1391, + SystemZ_KEB = 1392, + SystemZ_KEBR = 1393, + SystemZ_KIMD = 1394, + SystemZ_KLMD = 1395, + SystemZ_KM = 1396, + SystemZ_KMA = 1397, + SystemZ_KMAC = 1398, + SystemZ_KMC = 1399, + SystemZ_KMCTR = 1400, + SystemZ_KMF = 1401, + SystemZ_KMO = 1402, + SystemZ_KXBR = 1403, + SystemZ_KXTR = 1404, + SystemZ_L = 1405, + SystemZ_LA = 1406, + SystemZ_LAA = 1407, + SystemZ_LAAG = 1408, + SystemZ_LAAL = 1409, + SystemZ_LAALG = 1410, + SystemZ_LAE = 1411, + SystemZ_LAEY = 1412, + SystemZ_LAM = 1413, + SystemZ_LAMY = 1414, + SystemZ_LAN = 1415, + SystemZ_LANG = 1416, + SystemZ_LAO = 1417, + SystemZ_LAOG = 1418, + SystemZ_LARL = 1419, + SystemZ_LASP = 1420, + SystemZ_LAT = 1421, + SystemZ_LAX = 1422, + SystemZ_LAXG = 1423, + SystemZ_LAY = 1424, + SystemZ_LB = 1425, + SystemZ_LBEAR = 1426, + SystemZ_LBH = 1427, + SystemZ_LBR = 1428, + SystemZ_LCBB = 1429, + SystemZ_LCCTL = 1430, + SystemZ_LCDBR = 1431, + SystemZ_LCDFR = 1432, + SystemZ_LCDFR_32 = 1433, + SystemZ_LCDR = 1434, + SystemZ_LCEBR = 1435, + SystemZ_LCER = 1436, + SystemZ_LCGFR = 1437, + SystemZ_LCGR = 1438, + SystemZ_LCR = 1439, + SystemZ_LCTL = 1440, + SystemZ_LCTLG = 1441, + SystemZ_LCXBR = 1442, + SystemZ_LCXR = 1443, + SystemZ_LD = 1444, + SystemZ_LDE = 1445, + SystemZ_LDE32 = 1446, + SystemZ_LDEB = 1447, + SystemZ_LDEBR = 1448, + SystemZ_LDER = 1449, + SystemZ_LDETR = 1450, + SystemZ_LDGR = 1451, + SystemZ_LDR = 1452, + SystemZ_LDR32 = 1453, + SystemZ_LDXBR = 1454, + SystemZ_LDXBRA = 1455, + SystemZ_LDXR = 1456, + SystemZ_LDXTR = 1457, + SystemZ_LDY = 1458, + SystemZ_LE = 1459, + SystemZ_LEDBR = 1460, + SystemZ_LEDBRA = 1461, + SystemZ_LEDR = 1462, + SystemZ_LEDTR = 1463, + SystemZ_LER = 1464, + SystemZ_LEXBR = 1465, + SystemZ_LEXBRA = 1466, + SystemZ_LEXR = 1467, + SystemZ_LEY = 1468, + SystemZ_LFAS = 1469, + SystemZ_LFH = 1470, + SystemZ_LFHAT = 1471, + SystemZ_LFPC = 1472, + SystemZ_LG = 1473, + SystemZ_LGAT = 1474, + SystemZ_LGB = 1475, + SystemZ_LGBR = 1476, + SystemZ_LGDR = 1477, + SystemZ_LGF = 1478, + SystemZ_LGFI = 1479, + SystemZ_LGFR = 1480, + SystemZ_LGFRL = 1481, + SystemZ_LGG = 1482, + SystemZ_LGH = 1483, + SystemZ_LGHI = 1484, + SystemZ_LGHR = 1485, + SystemZ_LGHRL = 1486, + SystemZ_LGR = 1487, + SystemZ_LGRL = 1488, + SystemZ_LGSC = 1489, + SystemZ_LH = 1490, + SystemZ_LHH = 1491, + SystemZ_LHI = 1492, + SystemZ_LHR = 1493, + SystemZ_LHRL = 1494, + SystemZ_LHY = 1495, + SystemZ_LLC = 1496, + SystemZ_LLCH = 1497, + SystemZ_LLCR = 1498, + SystemZ_LLGC = 1499, + SystemZ_LLGCR = 1500, + SystemZ_LLGF = 1501, + SystemZ_LLGFAT = 1502, + SystemZ_LLGFR = 1503, + SystemZ_LLGFRL = 1504, + SystemZ_LLGFSG = 1505, + SystemZ_LLGH = 1506, + SystemZ_LLGHR = 1507, + SystemZ_LLGHRL = 1508, + SystemZ_LLGT = 1509, + SystemZ_LLGTAT = 1510, + SystemZ_LLGTR = 1511, + SystemZ_LLH = 1512, + SystemZ_LLHH = 1513, + SystemZ_LLHR = 1514, + SystemZ_LLHRL = 1515, + SystemZ_LLIHF = 1516, + SystemZ_LLIHH = 1517, + SystemZ_LLIHL = 1518, + SystemZ_LLILF = 1519, + SystemZ_LLILH = 1520, + SystemZ_LLILL = 1521, + SystemZ_LLZRGF = 1522, + SystemZ_LM = 1523, + SystemZ_LMD = 1524, + SystemZ_LMG = 1525, + SystemZ_LMH = 1526, + SystemZ_LMY = 1527, + SystemZ_LNDBR = 1528, + SystemZ_LNDFR = 1529, + SystemZ_LNDFR_32 = 1530, + SystemZ_LNDR = 1531, + SystemZ_LNEBR = 1532, + SystemZ_LNER = 1533, + SystemZ_LNGFR = 1534, + SystemZ_LNGR = 1535, + SystemZ_LNR = 1536, + SystemZ_LNXBR = 1537, + SystemZ_LNXR = 1538, + SystemZ_LOC = 1539, + SystemZ_LOCAsm = 1540, + SystemZ_LOCAsmE = 1541, + SystemZ_LOCAsmH = 1542, + SystemZ_LOCAsmHE = 1543, + SystemZ_LOCAsmL = 1544, + SystemZ_LOCAsmLE = 1545, + SystemZ_LOCAsmLH = 1546, + SystemZ_LOCAsmM = 1547, + SystemZ_LOCAsmNE = 1548, + SystemZ_LOCAsmNH = 1549, + SystemZ_LOCAsmNHE = 1550, + SystemZ_LOCAsmNL = 1551, + SystemZ_LOCAsmNLE = 1552, + SystemZ_LOCAsmNLH = 1553, + SystemZ_LOCAsmNM = 1554, + SystemZ_LOCAsmNO = 1555, + SystemZ_LOCAsmNP = 1556, + SystemZ_LOCAsmNZ = 1557, + SystemZ_LOCAsmO = 1558, + SystemZ_LOCAsmP = 1559, + SystemZ_LOCAsmZ = 1560, + SystemZ_LOCFH = 1561, + SystemZ_LOCFHAsm = 1562, + SystemZ_LOCFHAsmE = 1563, + SystemZ_LOCFHAsmH = 1564, + SystemZ_LOCFHAsmHE = 1565, + SystemZ_LOCFHAsmL = 1566, + SystemZ_LOCFHAsmLE = 1567, + SystemZ_LOCFHAsmLH = 1568, + SystemZ_LOCFHAsmM = 1569, + SystemZ_LOCFHAsmNE = 1570, + SystemZ_LOCFHAsmNH = 1571, + SystemZ_LOCFHAsmNHE = 1572, + SystemZ_LOCFHAsmNL = 1573, + SystemZ_LOCFHAsmNLE = 1574, + SystemZ_LOCFHAsmNLH = 1575, + SystemZ_LOCFHAsmNM = 1576, + SystemZ_LOCFHAsmNO = 1577, + SystemZ_LOCFHAsmNP = 1578, + SystemZ_LOCFHAsmNZ = 1579, + SystemZ_LOCFHAsmO = 1580, + SystemZ_LOCFHAsmP = 1581, + SystemZ_LOCFHAsmZ = 1582, + SystemZ_LOCFHR = 1583, + SystemZ_LOCFHRAsm = 1584, + SystemZ_LOCFHRAsmE = 1585, + SystemZ_LOCFHRAsmH = 1586, + SystemZ_LOCFHRAsmHE = 1587, + SystemZ_LOCFHRAsmL = 1588, + SystemZ_LOCFHRAsmLE = 1589, + SystemZ_LOCFHRAsmLH = 1590, + SystemZ_LOCFHRAsmM = 1591, + SystemZ_LOCFHRAsmNE = 1592, + SystemZ_LOCFHRAsmNH = 1593, + SystemZ_LOCFHRAsmNHE = 1594, + SystemZ_LOCFHRAsmNL = 1595, + SystemZ_LOCFHRAsmNLE = 1596, + SystemZ_LOCFHRAsmNLH = 1597, + SystemZ_LOCFHRAsmNM = 1598, + SystemZ_LOCFHRAsmNO = 1599, + SystemZ_LOCFHRAsmNP = 1600, + SystemZ_LOCFHRAsmNZ = 1601, + SystemZ_LOCFHRAsmO = 1602, + SystemZ_LOCFHRAsmP = 1603, + SystemZ_LOCFHRAsmZ = 1604, + SystemZ_LOCG = 1605, + SystemZ_LOCGAsm = 1606, + SystemZ_LOCGAsmE = 1607, + SystemZ_LOCGAsmH = 1608, + SystemZ_LOCGAsmHE = 1609, + SystemZ_LOCGAsmL = 1610, + SystemZ_LOCGAsmLE = 1611, + SystemZ_LOCGAsmLH = 1612, + SystemZ_LOCGAsmM = 1613, + SystemZ_LOCGAsmNE = 1614, + SystemZ_LOCGAsmNH = 1615, + SystemZ_LOCGAsmNHE = 1616, + SystemZ_LOCGAsmNL = 1617, + SystemZ_LOCGAsmNLE = 1618, + SystemZ_LOCGAsmNLH = 1619, + SystemZ_LOCGAsmNM = 1620, + SystemZ_LOCGAsmNO = 1621, + SystemZ_LOCGAsmNP = 1622, + SystemZ_LOCGAsmNZ = 1623, + SystemZ_LOCGAsmO = 1624, + SystemZ_LOCGAsmP = 1625, + SystemZ_LOCGAsmZ = 1626, + SystemZ_LOCGHI = 1627, + SystemZ_LOCGHIAsm = 1628, + SystemZ_LOCGHIAsmE = 1629, + SystemZ_LOCGHIAsmH = 1630, + SystemZ_LOCGHIAsmHE = 1631, + SystemZ_LOCGHIAsmL = 1632, + SystemZ_LOCGHIAsmLE = 1633, + SystemZ_LOCGHIAsmLH = 1634, + SystemZ_LOCGHIAsmM = 1635, + SystemZ_LOCGHIAsmNE = 1636, + SystemZ_LOCGHIAsmNH = 1637, + SystemZ_LOCGHIAsmNHE = 1638, + SystemZ_LOCGHIAsmNL = 1639, + SystemZ_LOCGHIAsmNLE = 1640, + SystemZ_LOCGHIAsmNLH = 1641, + SystemZ_LOCGHIAsmNM = 1642, + SystemZ_LOCGHIAsmNO = 1643, + SystemZ_LOCGHIAsmNP = 1644, + SystemZ_LOCGHIAsmNZ = 1645, + SystemZ_LOCGHIAsmO = 1646, + SystemZ_LOCGHIAsmP = 1647, + SystemZ_LOCGHIAsmZ = 1648, + SystemZ_LOCGR = 1649, + SystemZ_LOCGRAsm = 1650, + SystemZ_LOCGRAsmE = 1651, + SystemZ_LOCGRAsmH = 1652, + SystemZ_LOCGRAsmHE = 1653, + SystemZ_LOCGRAsmL = 1654, + SystemZ_LOCGRAsmLE = 1655, + SystemZ_LOCGRAsmLH = 1656, + SystemZ_LOCGRAsmM = 1657, + SystemZ_LOCGRAsmNE = 1658, + SystemZ_LOCGRAsmNH = 1659, + SystemZ_LOCGRAsmNHE = 1660, + SystemZ_LOCGRAsmNL = 1661, + SystemZ_LOCGRAsmNLE = 1662, + SystemZ_LOCGRAsmNLH = 1663, + SystemZ_LOCGRAsmNM = 1664, + SystemZ_LOCGRAsmNO = 1665, + SystemZ_LOCGRAsmNP = 1666, + SystemZ_LOCGRAsmNZ = 1667, + SystemZ_LOCGRAsmO = 1668, + SystemZ_LOCGRAsmP = 1669, + SystemZ_LOCGRAsmZ = 1670, + SystemZ_LOCHHI = 1671, + SystemZ_LOCHHIAsm = 1672, + SystemZ_LOCHHIAsmE = 1673, + SystemZ_LOCHHIAsmH = 1674, + SystemZ_LOCHHIAsmHE = 1675, + SystemZ_LOCHHIAsmL = 1676, + SystemZ_LOCHHIAsmLE = 1677, + SystemZ_LOCHHIAsmLH = 1678, + SystemZ_LOCHHIAsmM = 1679, + SystemZ_LOCHHIAsmNE = 1680, + SystemZ_LOCHHIAsmNH = 1681, + SystemZ_LOCHHIAsmNHE = 1682, + SystemZ_LOCHHIAsmNL = 1683, + SystemZ_LOCHHIAsmNLE = 1684, + SystemZ_LOCHHIAsmNLH = 1685, + SystemZ_LOCHHIAsmNM = 1686, + SystemZ_LOCHHIAsmNO = 1687, + SystemZ_LOCHHIAsmNP = 1688, + SystemZ_LOCHHIAsmNZ = 1689, + SystemZ_LOCHHIAsmO = 1690, + SystemZ_LOCHHIAsmP = 1691, + SystemZ_LOCHHIAsmZ = 1692, + SystemZ_LOCHI = 1693, + SystemZ_LOCHIAsm = 1694, + SystemZ_LOCHIAsmE = 1695, + SystemZ_LOCHIAsmH = 1696, + SystemZ_LOCHIAsmHE = 1697, + SystemZ_LOCHIAsmL = 1698, + SystemZ_LOCHIAsmLE = 1699, + SystemZ_LOCHIAsmLH = 1700, + SystemZ_LOCHIAsmM = 1701, + SystemZ_LOCHIAsmNE = 1702, + SystemZ_LOCHIAsmNH = 1703, + SystemZ_LOCHIAsmNHE = 1704, + SystemZ_LOCHIAsmNL = 1705, + SystemZ_LOCHIAsmNLE = 1706, + SystemZ_LOCHIAsmNLH = 1707, + SystemZ_LOCHIAsmNM = 1708, + SystemZ_LOCHIAsmNO = 1709, + SystemZ_LOCHIAsmNP = 1710, + SystemZ_LOCHIAsmNZ = 1711, + SystemZ_LOCHIAsmO = 1712, + SystemZ_LOCHIAsmP = 1713, + SystemZ_LOCHIAsmZ = 1714, + SystemZ_LOCR = 1715, + SystemZ_LOCRAsm = 1716, + SystemZ_LOCRAsmE = 1717, + SystemZ_LOCRAsmH = 1718, + SystemZ_LOCRAsmHE = 1719, + SystemZ_LOCRAsmL = 1720, + SystemZ_LOCRAsmLE = 1721, + SystemZ_LOCRAsmLH = 1722, + SystemZ_LOCRAsmM = 1723, + SystemZ_LOCRAsmNE = 1724, + SystemZ_LOCRAsmNH = 1725, + SystemZ_LOCRAsmNHE = 1726, + SystemZ_LOCRAsmNL = 1727, + SystemZ_LOCRAsmNLE = 1728, + SystemZ_LOCRAsmNLH = 1729, + SystemZ_LOCRAsmNM = 1730, + SystemZ_LOCRAsmNO = 1731, + SystemZ_LOCRAsmNP = 1732, + SystemZ_LOCRAsmNZ = 1733, + SystemZ_LOCRAsmO = 1734, + SystemZ_LOCRAsmP = 1735, + SystemZ_LOCRAsmZ = 1736, + SystemZ_LPCTL = 1737, + SystemZ_LPD = 1738, + SystemZ_LPDBR = 1739, + SystemZ_LPDFR = 1740, + SystemZ_LPDFR_32 = 1741, + SystemZ_LPDG = 1742, + SystemZ_LPDR = 1743, + SystemZ_LPEBR = 1744, + SystemZ_LPER = 1745, + SystemZ_LPGFR = 1746, + SystemZ_LPGR = 1747, + SystemZ_LPP = 1748, + SystemZ_LPQ = 1749, + SystemZ_LPR = 1750, + SystemZ_LPSW = 1751, + SystemZ_LPSWE = 1752, + SystemZ_LPSWEY = 1753, + SystemZ_LPTEA = 1754, + SystemZ_LPXBR = 1755, + SystemZ_LPXR = 1756, + SystemZ_LR = 1757, + SystemZ_LRA = 1758, + SystemZ_LRAG = 1759, + SystemZ_LRAY = 1760, + SystemZ_LRDR = 1761, + SystemZ_LRER = 1762, + SystemZ_LRL = 1763, + SystemZ_LRV = 1764, + SystemZ_LRVG = 1765, + SystemZ_LRVGR = 1766, + SystemZ_LRVH = 1767, + SystemZ_LRVR = 1768, + SystemZ_LSCTL = 1769, + SystemZ_LT = 1770, + SystemZ_LTDBR = 1771, + SystemZ_LTDR = 1772, + SystemZ_LTDTR = 1773, + SystemZ_LTEBR = 1774, + SystemZ_LTER = 1775, + SystemZ_LTG = 1776, + SystemZ_LTGF = 1777, + SystemZ_LTGFR = 1778, + SystemZ_LTGR = 1779, + SystemZ_LTR = 1780, + SystemZ_LTXBR = 1781, + SystemZ_LTXR = 1782, + SystemZ_LTXTR = 1783, + SystemZ_LURA = 1784, + SystemZ_LURAG = 1785, + SystemZ_LXD = 1786, + SystemZ_LXDB = 1787, + SystemZ_LXDBR = 1788, + SystemZ_LXDR = 1789, + SystemZ_LXDTR = 1790, + SystemZ_LXE = 1791, + SystemZ_LXEB = 1792, + SystemZ_LXEBR = 1793, + SystemZ_LXER = 1794, + SystemZ_LXR = 1795, + SystemZ_LY = 1796, + SystemZ_LZDR = 1797, + SystemZ_LZER = 1798, + SystemZ_LZRF = 1799, + SystemZ_LZRG = 1800, + SystemZ_LZXR = 1801, + SystemZ_M = 1802, + SystemZ_MAD = 1803, + SystemZ_MADB = 1804, + SystemZ_MADBR = 1805, + SystemZ_MADR = 1806, + SystemZ_MAE = 1807, + SystemZ_MAEB = 1808, + SystemZ_MAEBR = 1809, + SystemZ_MAER = 1810, + SystemZ_MAY = 1811, + SystemZ_MAYH = 1812, + SystemZ_MAYHR = 1813, + SystemZ_MAYL = 1814, + SystemZ_MAYLR = 1815, + SystemZ_MAYR = 1816, + SystemZ_MC = 1817, + SystemZ_MD = 1818, + SystemZ_MDB = 1819, + SystemZ_MDBR = 1820, + SystemZ_MDE = 1821, + SystemZ_MDEB = 1822, + SystemZ_MDEBR = 1823, + SystemZ_MDER = 1824, + SystemZ_MDR = 1825, + SystemZ_MDTR = 1826, + SystemZ_MDTRA = 1827, + SystemZ_ME = 1828, + SystemZ_MEE = 1829, + SystemZ_MEEB = 1830, + SystemZ_MEEBR = 1831, + SystemZ_MEER = 1832, + SystemZ_MER = 1833, + SystemZ_MFY = 1834, + SystemZ_MG = 1835, + SystemZ_MGH = 1836, + SystemZ_MGHI = 1837, + SystemZ_MGRK = 1838, + SystemZ_MH = 1839, + SystemZ_MHI = 1840, + SystemZ_MHY = 1841, + SystemZ_ML = 1842, + SystemZ_MLG = 1843, + SystemZ_MLGR = 1844, + SystemZ_MLR = 1845, + SystemZ_MP = 1846, + SystemZ_MR = 1847, + SystemZ_MS = 1848, + SystemZ_MSC = 1849, + SystemZ_MSCH = 1850, + SystemZ_MSD = 1851, + SystemZ_MSDB = 1852, + SystemZ_MSDBR = 1853, + SystemZ_MSDR = 1854, + SystemZ_MSE = 1855, + SystemZ_MSEB = 1856, + SystemZ_MSEBR = 1857, + SystemZ_MSER = 1858, + SystemZ_MSFI = 1859, + SystemZ_MSG = 1860, + SystemZ_MSGC = 1861, + SystemZ_MSGF = 1862, + SystemZ_MSGFI = 1863, + SystemZ_MSGFR = 1864, + SystemZ_MSGR = 1865, + SystemZ_MSGRKC = 1866, + SystemZ_MSR = 1867, + SystemZ_MSRKC = 1868, + SystemZ_MSTA = 1869, + SystemZ_MSY = 1870, + SystemZ_MVC = 1871, + SystemZ_MVCDK = 1872, + SystemZ_MVCIN = 1873, + SystemZ_MVCK = 1874, + SystemZ_MVCL = 1875, + SystemZ_MVCLE = 1876, + SystemZ_MVCLU = 1877, + SystemZ_MVCOS = 1878, + SystemZ_MVCP = 1879, + SystemZ_MVCRL = 1880, + SystemZ_MVCS = 1881, + SystemZ_MVCSK = 1882, + SystemZ_MVGHI = 1883, + SystemZ_MVHHI = 1884, + SystemZ_MVHI = 1885, + SystemZ_MVI = 1886, + SystemZ_MVIY = 1887, + SystemZ_MVN = 1888, + SystemZ_MVO = 1889, + SystemZ_MVPG = 1890, + SystemZ_MVST = 1891, + SystemZ_MVZ = 1892, + SystemZ_MXBR = 1893, + SystemZ_MXD = 1894, + SystemZ_MXDB = 1895, + SystemZ_MXDBR = 1896, + SystemZ_MXDR = 1897, + SystemZ_MXR = 1898, + SystemZ_MXTR = 1899, + SystemZ_MXTRA = 1900, + SystemZ_MY = 1901, + SystemZ_MYH = 1902, + SystemZ_MYHR = 1903, + SystemZ_MYL = 1904, + SystemZ_MYLR = 1905, + SystemZ_MYR = 1906, + SystemZ_N = 1907, + SystemZ_NC = 1908, + SystemZ_NCGRK = 1909, + SystemZ_NCRK = 1910, + SystemZ_NG = 1911, + SystemZ_NGR = 1912, + SystemZ_NGRK = 1913, + SystemZ_NI = 1914, + SystemZ_NIAI = 1915, + SystemZ_NIHF = 1916, + SystemZ_NIHH = 1917, + SystemZ_NIHL = 1918, + SystemZ_NILF = 1919, + SystemZ_NILH = 1920, + SystemZ_NILL = 1921, + SystemZ_NIY = 1922, + SystemZ_NNGRK = 1923, + SystemZ_NNPA = 1924, + SystemZ_NNRK = 1925, + SystemZ_NOGRK = 1926, + SystemZ_NOP_bare = 1927, + SystemZ_NORK = 1928, + SystemZ_NR = 1929, + SystemZ_NRK = 1930, + SystemZ_NTSTG = 1931, + SystemZ_NXGRK = 1932, + SystemZ_NXRK = 1933, + SystemZ_NY = 1934, + SystemZ_O = 1935, + SystemZ_OC = 1936, + SystemZ_OCGRK = 1937, + SystemZ_OCRK = 1938, + SystemZ_OG = 1939, + SystemZ_OGR = 1940, + SystemZ_OGRK = 1941, + SystemZ_OI = 1942, + SystemZ_OIHF = 1943, + SystemZ_OIHH = 1944, + SystemZ_OIHL = 1945, + SystemZ_OILF = 1946, + SystemZ_OILH = 1947, + SystemZ_OILL = 1948, + SystemZ_OIY = 1949, + SystemZ_OR = 1950, + SystemZ_ORK = 1951, + SystemZ_OY = 1952, + SystemZ_PACK = 1953, + SystemZ_PALB = 1954, + SystemZ_PC = 1955, + SystemZ_PCC = 1956, + SystemZ_PCKMO = 1957, + SystemZ_PFD = 1958, + SystemZ_PFDRL = 1959, + SystemZ_PFMF = 1960, + SystemZ_PFPO = 1961, + SystemZ_PGIN = 1962, + SystemZ_PGOUT = 1963, + SystemZ_PKA = 1964, + SystemZ_PKU = 1965, + SystemZ_PLO = 1966, + SystemZ_POPCNT = 1967, + SystemZ_POPCNTOpt = 1968, + SystemZ_PPA = 1969, + SystemZ_PPNO = 1970, + SystemZ_PR = 1971, + SystemZ_PRNO = 1972, + SystemZ_PT = 1973, + SystemZ_PTF = 1974, + SystemZ_PTFF = 1975, + SystemZ_PTI = 1976, + SystemZ_PTLB = 1977, + SystemZ_QADTR = 1978, + SystemZ_QAXTR = 1979, + SystemZ_QCTRI = 1980, + SystemZ_QPACI = 1981, + SystemZ_QSI = 1982, + SystemZ_RCHP = 1983, + SystemZ_RDP = 1984, + SystemZ_RDPOpt = 1985, + SystemZ_RISBG = 1986, + SystemZ_RISBG32 = 1987, + SystemZ_RISBGN = 1988, + SystemZ_RISBHG = 1989, + SystemZ_RISBLG = 1990, + SystemZ_RLL = 1991, + SystemZ_RLLG = 1992, + SystemZ_RNSBG = 1993, + SystemZ_ROSBG = 1994, + SystemZ_RP = 1995, + SystemZ_RRBE = 1996, + SystemZ_RRBM = 1997, + SystemZ_RRDTR = 1998, + SystemZ_RRXTR = 1999, + SystemZ_RSCH = 2000, + SystemZ_RXSBG = 2001, + SystemZ_S = 2002, + SystemZ_SAC = 2003, + SystemZ_SACF = 2004, + SystemZ_SAL = 2005, + SystemZ_SAM24 = 2006, + SystemZ_SAM31 = 2007, + SystemZ_SAM64 = 2008, + SystemZ_SAR = 2009, + SystemZ_SCCTR = 2010, + SystemZ_SCHM = 2011, + SystemZ_SCK = 2012, + SystemZ_SCKC = 2013, + SystemZ_SCKPF = 2014, + SystemZ_SD = 2015, + SystemZ_SDB = 2016, + SystemZ_SDBR = 2017, + SystemZ_SDR = 2018, + SystemZ_SDTR = 2019, + SystemZ_SDTRA = 2020, + SystemZ_SE = 2021, + SystemZ_SEB = 2022, + SystemZ_SEBR = 2023, + SystemZ_SELFHR = 2024, + SystemZ_SELFHRAsm = 2025, + SystemZ_SELFHRAsmE = 2026, + SystemZ_SELFHRAsmH = 2027, + SystemZ_SELFHRAsmHE = 2028, + SystemZ_SELFHRAsmL = 2029, + SystemZ_SELFHRAsmLE = 2030, + SystemZ_SELFHRAsmLH = 2031, + SystemZ_SELFHRAsmM = 2032, + SystemZ_SELFHRAsmNE = 2033, + SystemZ_SELFHRAsmNH = 2034, + SystemZ_SELFHRAsmNHE = 2035, + SystemZ_SELFHRAsmNL = 2036, + SystemZ_SELFHRAsmNLE = 2037, + SystemZ_SELFHRAsmNLH = 2038, + SystemZ_SELFHRAsmNM = 2039, + SystemZ_SELFHRAsmNO = 2040, + SystemZ_SELFHRAsmNP = 2041, + SystemZ_SELFHRAsmNZ = 2042, + SystemZ_SELFHRAsmO = 2043, + SystemZ_SELFHRAsmP = 2044, + SystemZ_SELFHRAsmZ = 2045, + SystemZ_SELGR = 2046, + SystemZ_SELGRAsm = 2047, + SystemZ_SELGRAsmE = 2048, + SystemZ_SELGRAsmH = 2049, + SystemZ_SELGRAsmHE = 2050, + SystemZ_SELGRAsmL = 2051, + SystemZ_SELGRAsmLE = 2052, + SystemZ_SELGRAsmLH = 2053, + SystemZ_SELGRAsmM = 2054, + SystemZ_SELGRAsmNE = 2055, + SystemZ_SELGRAsmNH = 2056, + SystemZ_SELGRAsmNHE = 2057, + SystemZ_SELGRAsmNL = 2058, + SystemZ_SELGRAsmNLE = 2059, + SystemZ_SELGRAsmNLH = 2060, + SystemZ_SELGRAsmNM = 2061, + SystemZ_SELGRAsmNO = 2062, + SystemZ_SELGRAsmNP = 2063, + SystemZ_SELGRAsmNZ = 2064, + SystemZ_SELGRAsmO = 2065, + SystemZ_SELGRAsmP = 2066, + SystemZ_SELGRAsmZ = 2067, + SystemZ_SELR = 2068, + SystemZ_SELRAsm = 2069, + SystemZ_SELRAsmE = 2070, + SystemZ_SELRAsmH = 2071, + SystemZ_SELRAsmHE = 2072, + SystemZ_SELRAsmL = 2073, + SystemZ_SELRAsmLE = 2074, + SystemZ_SELRAsmLH = 2075, + SystemZ_SELRAsmM = 2076, + SystemZ_SELRAsmNE = 2077, + SystemZ_SELRAsmNH = 2078, + SystemZ_SELRAsmNHE = 2079, + SystemZ_SELRAsmNL = 2080, + SystemZ_SELRAsmNLE = 2081, + SystemZ_SELRAsmNLH = 2082, + SystemZ_SELRAsmNM = 2083, + SystemZ_SELRAsmNO = 2084, + SystemZ_SELRAsmNP = 2085, + SystemZ_SELRAsmNZ = 2086, + SystemZ_SELRAsmO = 2087, + SystemZ_SELRAsmP = 2088, + SystemZ_SELRAsmZ = 2089, + SystemZ_SER = 2090, + SystemZ_SFASR = 2091, + SystemZ_SFPC = 2092, + SystemZ_SG = 2093, + SystemZ_SGF = 2094, + SystemZ_SGFR = 2095, + SystemZ_SGH = 2096, + SystemZ_SGR = 2097, + SystemZ_SGRK = 2098, + SystemZ_SH = 2099, + SystemZ_SHHHR = 2100, + SystemZ_SHHLR = 2101, + SystemZ_SHY = 2102, + SystemZ_SIE = 2103, + SystemZ_SIGA = 2104, + SystemZ_SIGP = 2105, + SystemZ_SL = 2106, + SystemZ_SLA = 2107, + SystemZ_SLAG = 2108, + SystemZ_SLAK = 2109, + SystemZ_SLB = 2110, + SystemZ_SLBG = 2111, + SystemZ_SLBGR = 2112, + SystemZ_SLBR = 2113, + SystemZ_SLDA = 2114, + SystemZ_SLDL = 2115, + SystemZ_SLDT = 2116, + SystemZ_SLFI = 2117, + SystemZ_SLG = 2118, + SystemZ_SLGF = 2119, + SystemZ_SLGFI = 2120, + SystemZ_SLGFR = 2121, + SystemZ_SLGR = 2122, + SystemZ_SLGRK = 2123, + SystemZ_SLHHHR = 2124, + SystemZ_SLHHLR = 2125, + SystemZ_SLL = 2126, + SystemZ_SLLG = 2127, + SystemZ_SLLK = 2128, + SystemZ_SLR = 2129, + SystemZ_SLRK = 2130, + SystemZ_SLXT = 2131, + SystemZ_SLY = 2132, + SystemZ_SORTL = 2133, + SystemZ_SP = 2134, + SystemZ_SPCTR = 2135, + SystemZ_SPKA = 2136, + SystemZ_SPM = 2137, + SystemZ_SPT = 2138, + SystemZ_SPX = 2139, + SystemZ_SQD = 2140, + SystemZ_SQDB = 2141, + SystemZ_SQDBR = 2142, + SystemZ_SQDR = 2143, + SystemZ_SQE = 2144, + SystemZ_SQEB = 2145, + SystemZ_SQEBR = 2146, + SystemZ_SQER = 2147, + SystemZ_SQXBR = 2148, + SystemZ_SQXR = 2149, + SystemZ_SR = 2150, + SystemZ_SRA = 2151, + SystemZ_SRAG = 2152, + SystemZ_SRAK = 2153, + SystemZ_SRDA = 2154, + SystemZ_SRDL = 2155, + SystemZ_SRDT = 2156, + SystemZ_SRK = 2157, + SystemZ_SRL = 2158, + SystemZ_SRLG = 2159, + SystemZ_SRLK = 2160, + SystemZ_SRNM = 2161, + SystemZ_SRNMB = 2162, + SystemZ_SRNMT = 2163, + SystemZ_SRP = 2164, + SystemZ_SRST = 2165, + SystemZ_SRSTU = 2166, + SystemZ_SRXT = 2167, + SystemZ_SSAIR = 2168, + SystemZ_SSAR = 2169, + SystemZ_SSCH = 2170, + SystemZ_SSKE = 2171, + SystemZ_SSKEOpt = 2172, + SystemZ_SSM = 2173, + SystemZ_ST = 2174, + SystemZ_STAM = 2175, + SystemZ_STAMY = 2176, + SystemZ_STAP = 2177, + SystemZ_STBEAR = 2178, + SystemZ_STC = 2179, + SystemZ_STCH = 2180, + SystemZ_STCK = 2181, + SystemZ_STCKC = 2182, + SystemZ_STCKE = 2183, + SystemZ_STCKF = 2184, + SystemZ_STCM = 2185, + SystemZ_STCMH = 2186, + SystemZ_STCMY = 2187, + SystemZ_STCPS = 2188, + SystemZ_STCRW = 2189, + SystemZ_STCTG = 2190, + SystemZ_STCTL = 2191, + SystemZ_STCY = 2192, + SystemZ_STD = 2193, + SystemZ_STDY = 2194, + SystemZ_STE = 2195, + SystemZ_STEY = 2196, + SystemZ_STFH = 2197, + SystemZ_STFL = 2198, + SystemZ_STFLE = 2199, + SystemZ_STFPC = 2200, + SystemZ_STG = 2201, + SystemZ_STGRL = 2202, + SystemZ_STGSC = 2203, + SystemZ_STH = 2204, + SystemZ_STHH = 2205, + SystemZ_STHRL = 2206, + SystemZ_STHY = 2207, + SystemZ_STIDP = 2208, + SystemZ_STM = 2209, + SystemZ_STMG = 2210, + SystemZ_STMH = 2211, + SystemZ_STMY = 2212, + SystemZ_STNSM = 2213, + SystemZ_STOC = 2214, + SystemZ_STOCAsm = 2215, + SystemZ_STOCAsmE = 2216, + SystemZ_STOCAsmH = 2217, + SystemZ_STOCAsmHE = 2218, + SystemZ_STOCAsmL = 2219, + SystemZ_STOCAsmLE = 2220, + SystemZ_STOCAsmLH = 2221, + SystemZ_STOCAsmM = 2222, + SystemZ_STOCAsmNE = 2223, + SystemZ_STOCAsmNH = 2224, + SystemZ_STOCAsmNHE = 2225, + SystemZ_STOCAsmNL = 2226, + SystemZ_STOCAsmNLE = 2227, + SystemZ_STOCAsmNLH = 2228, + SystemZ_STOCAsmNM = 2229, + SystemZ_STOCAsmNO = 2230, + SystemZ_STOCAsmNP = 2231, + SystemZ_STOCAsmNZ = 2232, + SystemZ_STOCAsmO = 2233, + SystemZ_STOCAsmP = 2234, + SystemZ_STOCAsmZ = 2235, + SystemZ_STOCFH = 2236, + SystemZ_STOCFHAsm = 2237, + SystemZ_STOCFHAsmE = 2238, + SystemZ_STOCFHAsmH = 2239, + SystemZ_STOCFHAsmHE = 2240, + SystemZ_STOCFHAsmL = 2241, + SystemZ_STOCFHAsmLE = 2242, + SystemZ_STOCFHAsmLH = 2243, + SystemZ_STOCFHAsmM = 2244, + SystemZ_STOCFHAsmNE = 2245, + SystemZ_STOCFHAsmNH = 2246, + SystemZ_STOCFHAsmNHE = 2247, + SystemZ_STOCFHAsmNL = 2248, + SystemZ_STOCFHAsmNLE = 2249, + SystemZ_STOCFHAsmNLH = 2250, + SystemZ_STOCFHAsmNM = 2251, + SystemZ_STOCFHAsmNO = 2252, + SystemZ_STOCFHAsmNP = 2253, + SystemZ_STOCFHAsmNZ = 2254, + SystemZ_STOCFHAsmO = 2255, + SystemZ_STOCFHAsmP = 2256, + SystemZ_STOCFHAsmZ = 2257, + SystemZ_STOCG = 2258, + SystemZ_STOCGAsm = 2259, + SystemZ_STOCGAsmE = 2260, + SystemZ_STOCGAsmH = 2261, + SystemZ_STOCGAsmHE = 2262, + SystemZ_STOCGAsmL = 2263, + SystemZ_STOCGAsmLE = 2264, + SystemZ_STOCGAsmLH = 2265, + SystemZ_STOCGAsmM = 2266, + SystemZ_STOCGAsmNE = 2267, + SystemZ_STOCGAsmNH = 2268, + SystemZ_STOCGAsmNHE = 2269, + SystemZ_STOCGAsmNL = 2270, + SystemZ_STOCGAsmNLE = 2271, + SystemZ_STOCGAsmNLH = 2272, + SystemZ_STOCGAsmNM = 2273, + SystemZ_STOCGAsmNO = 2274, + SystemZ_STOCGAsmNP = 2275, + SystemZ_STOCGAsmNZ = 2276, + SystemZ_STOCGAsmO = 2277, + SystemZ_STOCGAsmP = 2278, + SystemZ_STOCGAsmZ = 2279, + SystemZ_STOSM = 2280, + SystemZ_STPQ = 2281, + SystemZ_STPT = 2282, + SystemZ_STPX = 2283, + SystemZ_STRAG = 2284, + SystemZ_STRL = 2285, + SystemZ_STRV = 2286, + SystemZ_STRVG = 2287, + SystemZ_STRVH = 2288, + SystemZ_STSCH = 2289, + SystemZ_STSI = 2290, + SystemZ_STURA = 2291, + SystemZ_STURG = 2292, + SystemZ_STY = 2293, + SystemZ_SU = 2294, + SystemZ_SUR = 2295, + SystemZ_SVC = 2296, + SystemZ_SW = 2297, + SystemZ_SWR = 2298, + SystemZ_SXBR = 2299, + SystemZ_SXR = 2300, + SystemZ_SXTR = 2301, + SystemZ_SXTRA = 2302, + SystemZ_SY = 2303, + SystemZ_TABORT = 2304, + SystemZ_TAM = 2305, + SystemZ_TAR = 2306, + SystemZ_TB = 2307, + SystemZ_TBDR = 2308, + SystemZ_TBEDR = 2309, + SystemZ_TBEGIN = 2310, + SystemZ_TBEGINC = 2311, + SystemZ_TCDB = 2312, + SystemZ_TCEB = 2313, + SystemZ_TCXB = 2314, + SystemZ_TDCDT = 2315, + SystemZ_TDCET = 2316, + SystemZ_TDCXT = 2317, + SystemZ_TDGDT = 2318, + SystemZ_TDGET = 2319, + SystemZ_TDGXT = 2320, + SystemZ_TEND = 2321, + SystemZ_THDER = 2322, + SystemZ_THDR = 2323, + SystemZ_TM = 2324, + SystemZ_TMHH = 2325, + SystemZ_TMHL = 2326, + SystemZ_TMLH = 2327, + SystemZ_TMLL = 2328, + SystemZ_TMY = 2329, + SystemZ_TP = 2330, + SystemZ_TPI = 2331, + SystemZ_TPROT = 2332, + SystemZ_TR = 2333, + SystemZ_TRACE = 2334, + SystemZ_TRACG = 2335, + SystemZ_TRAP2 = 2336, + SystemZ_TRAP4 = 2337, + SystemZ_TRE = 2338, + SystemZ_TROO = 2339, + SystemZ_TROOOpt = 2340, + SystemZ_TROT = 2341, + SystemZ_TROTOpt = 2342, + SystemZ_TRT = 2343, + SystemZ_TRTE = 2344, + SystemZ_TRTEOpt = 2345, + SystemZ_TRTO = 2346, + SystemZ_TRTOOpt = 2347, + SystemZ_TRTR = 2348, + SystemZ_TRTRE = 2349, + SystemZ_TRTREOpt = 2350, + SystemZ_TRTT = 2351, + SystemZ_TRTTOpt = 2352, + SystemZ_TS = 2353, + SystemZ_TSCH = 2354, + SystemZ_UNPK = 2355, + SystemZ_UNPKA = 2356, + SystemZ_UNPKU = 2357, + SystemZ_UPT = 2358, + SystemZ_VA = 2359, + SystemZ_VAB = 2360, + SystemZ_VAC = 2361, + SystemZ_VACC = 2362, + SystemZ_VACCB = 2363, + SystemZ_VACCC = 2364, + SystemZ_VACCCQ = 2365, + SystemZ_VACCF = 2366, + SystemZ_VACCG = 2367, + SystemZ_VACCH = 2368, + SystemZ_VACCQ = 2369, + SystemZ_VACQ = 2370, + SystemZ_VAF = 2371, + SystemZ_VAG = 2372, + SystemZ_VAH = 2373, + SystemZ_VAP = 2374, + SystemZ_VAQ = 2375, + SystemZ_VAVG = 2376, + SystemZ_VAVGB = 2377, + SystemZ_VAVGF = 2378, + SystemZ_VAVGG = 2379, + SystemZ_VAVGH = 2380, + SystemZ_VAVGL = 2381, + SystemZ_VAVGLB = 2382, + SystemZ_VAVGLF = 2383, + SystemZ_VAVGLG = 2384, + SystemZ_VAVGLH = 2385, + SystemZ_VBPERM = 2386, + SystemZ_VCDG = 2387, + SystemZ_VCDGB = 2388, + SystemZ_VCDLG = 2389, + SystemZ_VCDLGB = 2390, + SystemZ_VCEFB = 2391, + SystemZ_VCELFB = 2392, + SystemZ_VCEQ = 2393, + SystemZ_VCEQB = 2394, + SystemZ_VCEQBS = 2395, + SystemZ_VCEQF = 2396, + SystemZ_VCEQFS = 2397, + SystemZ_VCEQG = 2398, + SystemZ_VCEQGS = 2399, + SystemZ_VCEQH = 2400, + SystemZ_VCEQHS = 2401, + SystemZ_VCFEB = 2402, + SystemZ_VCFN = 2403, + SystemZ_VCFPL = 2404, + SystemZ_VCFPS = 2405, + SystemZ_VCGD = 2406, + SystemZ_VCGDB = 2407, + SystemZ_VCH = 2408, + SystemZ_VCHB = 2409, + SystemZ_VCHBS = 2410, + SystemZ_VCHF = 2411, + SystemZ_VCHFS = 2412, + SystemZ_VCHG = 2413, + SystemZ_VCHGS = 2414, + SystemZ_VCHH = 2415, + SystemZ_VCHHS = 2416, + SystemZ_VCHL = 2417, + SystemZ_VCHLB = 2418, + SystemZ_VCHLBS = 2419, + SystemZ_VCHLF = 2420, + SystemZ_VCHLFS = 2421, + SystemZ_VCHLG = 2422, + SystemZ_VCHLGS = 2423, + SystemZ_VCHLH = 2424, + SystemZ_VCHLHS = 2425, + SystemZ_VCKSM = 2426, + SystemZ_VCLFEB = 2427, + SystemZ_VCLFNH = 2428, + SystemZ_VCLFNL = 2429, + SystemZ_VCLFP = 2430, + SystemZ_VCLGD = 2431, + SystemZ_VCLGDB = 2432, + SystemZ_VCLZ = 2433, + SystemZ_VCLZB = 2434, + SystemZ_VCLZDP = 2435, + SystemZ_VCLZF = 2436, + SystemZ_VCLZG = 2437, + SystemZ_VCLZH = 2438, + SystemZ_VCNF = 2439, + SystemZ_VCP = 2440, + SystemZ_VCRNF = 2441, + SystemZ_VCSFP = 2442, + SystemZ_VCSPH = 2443, + SystemZ_VCTZ = 2444, + SystemZ_VCTZB = 2445, + SystemZ_VCTZF = 2446, + SystemZ_VCTZG = 2447, + SystemZ_VCTZH = 2448, + SystemZ_VCVB = 2449, + SystemZ_VCVBG = 2450, + SystemZ_VCVBGOpt = 2451, + SystemZ_VCVBOpt = 2452, + SystemZ_VCVD = 2453, + SystemZ_VCVDG = 2454, + SystemZ_VDP = 2455, + SystemZ_VEC = 2456, + SystemZ_VECB = 2457, + SystemZ_VECF = 2458, + SystemZ_VECG = 2459, + SystemZ_VECH = 2460, + SystemZ_VECL = 2461, + SystemZ_VECLB = 2462, + SystemZ_VECLF = 2463, + SystemZ_VECLG = 2464, + SystemZ_VECLH = 2465, + SystemZ_VERIM = 2466, + SystemZ_VERIMB = 2467, + SystemZ_VERIMF = 2468, + SystemZ_VERIMG = 2469, + SystemZ_VERIMH = 2470, + SystemZ_VERLL = 2471, + SystemZ_VERLLB = 2472, + SystemZ_VERLLF = 2473, + SystemZ_VERLLG = 2474, + SystemZ_VERLLH = 2475, + SystemZ_VERLLV = 2476, + SystemZ_VERLLVB = 2477, + SystemZ_VERLLVF = 2478, + SystemZ_VERLLVG = 2479, + SystemZ_VERLLVH = 2480, + SystemZ_VESL = 2481, + SystemZ_VESLB = 2482, + SystemZ_VESLF = 2483, + SystemZ_VESLG = 2484, + SystemZ_VESLH = 2485, + SystemZ_VESLV = 2486, + SystemZ_VESLVB = 2487, + SystemZ_VESLVF = 2488, + SystemZ_VESLVG = 2489, + SystemZ_VESLVH = 2490, + SystemZ_VESRA = 2491, + SystemZ_VESRAB = 2492, + SystemZ_VESRAF = 2493, + SystemZ_VESRAG = 2494, + SystemZ_VESRAH = 2495, + SystemZ_VESRAV = 2496, + SystemZ_VESRAVB = 2497, + SystemZ_VESRAVF = 2498, + SystemZ_VESRAVG = 2499, + SystemZ_VESRAVH = 2500, + SystemZ_VESRL = 2501, + SystemZ_VESRLB = 2502, + SystemZ_VESRLF = 2503, + SystemZ_VESRLG = 2504, + SystemZ_VESRLH = 2505, + SystemZ_VESRLV = 2506, + SystemZ_VESRLVB = 2507, + SystemZ_VESRLVF = 2508, + SystemZ_VESRLVG = 2509, + SystemZ_VESRLVH = 2510, + SystemZ_VFA = 2511, + SystemZ_VFADB = 2512, + SystemZ_VFAE = 2513, + SystemZ_VFAEB = 2514, + SystemZ_VFAEBS = 2515, + SystemZ_VFAEF = 2516, + SystemZ_VFAEFS = 2517, + SystemZ_VFAEH = 2518, + SystemZ_VFAEHS = 2519, + SystemZ_VFAEZB = 2520, + SystemZ_VFAEZBS = 2521, + SystemZ_VFAEZF = 2522, + SystemZ_VFAEZFS = 2523, + SystemZ_VFAEZH = 2524, + SystemZ_VFAEZHS = 2525, + SystemZ_VFASB = 2526, + SystemZ_VFCE = 2527, + SystemZ_VFCEDB = 2528, + SystemZ_VFCEDBS = 2529, + SystemZ_VFCESB = 2530, + SystemZ_VFCESBS = 2531, + SystemZ_VFCH = 2532, + SystemZ_VFCHDB = 2533, + SystemZ_VFCHDBS = 2534, + SystemZ_VFCHE = 2535, + SystemZ_VFCHEDB = 2536, + SystemZ_VFCHEDBS = 2537, + SystemZ_VFCHESB = 2538, + SystemZ_VFCHESBS = 2539, + SystemZ_VFCHSB = 2540, + SystemZ_VFCHSBS = 2541, + SystemZ_VFD = 2542, + SystemZ_VFDDB = 2543, + SystemZ_VFDSB = 2544, + SystemZ_VFEE = 2545, + SystemZ_VFEEB = 2546, + SystemZ_VFEEBS = 2547, + SystemZ_VFEEF = 2548, + SystemZ_VFEEFS = 2549, + SystemZ_VFEEH = 2550, + SystemZ_VFEEHS = 2551, + SystemZ_VFEEZB = 2552, + SystemZ_VFEEZBS = 2553, + SystemZ_VFEEZF = 2554, + SystemZ_VFEEZFS = 2555, + SystemZ_VFEEZH = 2556, + SystemZ_VFEEZHS = 2557, + SystemZ_VFENE = 2558, + SystemZ_VFENEB = 2559, + SystemZ_VFENEBS = 2560, + SystemZ_VFENEF = 2561, + SystemZ_VFENEFS = 2562, + SystemZ_VFENEH = 2563, + SystemZ_VFENEHS = 2564, + SystemZ_VFENEZB = 2565, + SystemZ_VFENEZBS = 2566, + SystemZ_VFENEZF = 2567, + SystemZ_VFENEZFS = 2568, + SystemZ_VFENEZH = 2569, + SystemZ_VFENEZHS = 2570, + SystemZ_VFI = 2571, + SystemZ_VFIDB = 2572, + SystemZ_VFISB = 2573, + SystemZ_VFKEDB = 2574, + SystemZ_VFKEDBS = 2575, + SystemZ_VFKESB = 2576, + SystemZ_VFKESBS = 2577, + SystemZ_VFKHDB = 2578, + SystemZ_VFKHDBS = 2579, + SystemZ_VFKHEDB = 2580, + SystemZ_VFKHEDBS = 2581, + SystemZ_VFKHESB = 2582, + SystemZ_VFKHESBS = 2583, + SystemZ_VFKHSB = 2584, + SystemZ_VFKHSBS = 2585, + SystemZ_VFLCDB = 2586, + SystemZ_VFLCSB = 2587, + SystemZ_VFLL = 2588, + SystemZ_VFLLS = 2589, + SystemZ_VFLNDB = 2590, + SystemZ_VFLNSB = 2591, + SystemZ_VFLPDB = 2592, + SystemZ_VFLPSB = 2593, + SystemZ_VFLR = 2594, + SystemZ_VFLRD = 2595, + SystemZ_VFM = 2596, + SystemZ_VFMA = 2597, + SystemZ_VFMADB = 2598, + SystemZ_VFMASB = 2599, + SystemZ_VFMAX = 2600, + SystemZ_VFMAXDB = 2601, + SystemZ_VFMAXSB = 2602, + SystemZ_VFMDB = 2603, + SystemZ_VFMIN = 2604, + SystemZ_VFMINDB = 2605, + SystemZ_VFMINSB = 2606, + SystemZ_VFMS = 2607, + SystemZ_VFMSB = 2608, + SystemZ_VFMSDB = 2609, + SystemZ_VFMSSB = 2610, + SystemZ_VFNMA = 2611, + SystemZ_VFNMADB = 2612, + SystemZ_VFNMASB = 2613, + SystemZ_VFNMS = 2614, + SystemZ_VFNMSDB = 2615, + SystemZ_VFNMSSB = 2616, + SystemZ_VFPSO = 2617, + SystemZ_VFPSODB = 2618, + SystemZ_VFPSOSB = 2619, + SystemZ_VFS = 2620, + SystemZ_VFSDB = 2621, + SystemZ_VFSQ = 2622, + SystemZ_VFSQDB = 2623, + SystemZ_VFSQSB = 2624, + SystemZ_VFSSB = 2625, + SystemZ_VFTCI = 2626, + SystemZ_VFTCIDB = 2627, + SystemZ_VFTCISB = 2628, + SystemZ_VGBM = 2629, + SystemZ_VGEF = 2630, + SystemZ_VGEG = 2631, + SystemZ_VGFM = 2632, + SystemZ_VGFMA = 2633, + SystemZ_VGFMAB = 2634, + SystemZ_VGFMAF = 2635, + SystemZ_VGFMAG = 2636, + SystemZ_VGFMAH = 2637, + SystemZ_VGFMB = 2638, + SystemZ_VGFMF = 2639, + SystemZ_VGFMG = 2640, + SystemZ_VGFMH = 2641, + SystemZ_VGM = 2642, + SystemZ_VGMB = 2643, + SystemZ_VGMF = 2644, + SystemZ_VGMG = 2645, + SystemZ_VGMH = 2646, + SystemZ_VISTR = 2647, + SystemZ_VISTRB = 2648, + SystemZ_VISTRBS = 2649, + SystemZ_VISTRF = 2650, + SystemZ_VISTRFS = 2651, + SystemZ_VISTRH = 2652, + SystemZ_VISTRHS = 2653, + SystemZ_VL = 2654, + SystemZ_VLAlign = 2655, + SystemZ_VLBB = 2656, + SystemZ_VLBR = 2657, + SystemZ_VLBRF = 2658, + SystemZ_VLBRG = 2659, + SystemZ_VLBRH = 2660, + SystemZ_VLBRQ = 2661, + SystemZ_VLBRREP = 2662, + SystemZ_VLBRREPF = 2663, + SystemZ_VLBRREPG = 2664, + SystemZ_VLBRREPH = 2665, + SystemZ_VLC = 2666, + SystemZ_VLCB = 2667, + SystemZ_VLCF = 2668, + SystemZ_VLCG = 2669, + SystemZ_VLCH = 2670, + SystemZ_VLDE = 2671, + SystemZ_VLDEB = 2672, + SystemZ_VLEB = 2673, + SystemZ_VLEBRF = 2674, + SystemZ_VLEBRG = 2675, + SystemZ_VLEBRH = 2676, + SystemZ_VLED = 2677, + SystemZ_VLEDB = 2678, + SystemZ_VLEF = 2679, + SystemZ_VLEG = 2680, + SystemZ_VLEH = 2681, + SystemZ_VLEIB = 2682, + SystemZ_VLEIF = 2683, + SystemZ_VLEIG = 2684, + SystemZ_VLEIH = 2685, + SystemZ_VLER = 2686, + SystemZ_VLERF = 2687, + SystemZ_VLERG = 2688, + SystemZ_VLERH = 2689, + SystemZ_VLGV = 2690, + SystemZ_VLGVB = 2691, + SystemZ_VLGVF = 2692, + SystemZ_VLGVG = 2693, + SystemZ_VLGVH = 2694, + SystemZ_VLIP = 2695, + SystemZ_VLL = 2696, + SystemZ_VLLEBRZ = 2697, + SystemZ_VLLEBRZE = 2698, + SystemZ_VLLEBRZF = 2699, + SystemZ_VLLEBRZG = 2700, + SystemZ_VLLEBRZH = 2701, + SystemZ_VLLEZ = 2702, + SystemZ_VLLEZB = 2703, + SystemZ_VLLEZF = 2704, + SystemZ_VLLEZG = 2705, + SystemZ_VLLEZH = 2706, + SystemZ_VLLEZLF = 2707, + SystemZ_VLM = 2708, + SystemZ_VLMAlign = 2709, + SystemZ_VLP = 2710, + SystemZ_VLPB = 2711, + SystemZ_VLPF = 2712, + SystemZ_VLPG = 2713, + SystemZ_VLPH = 2714, + SystemZ_VLR = 2715, + SystemZ_VLREP = 2716, + SystemZ_VLREPB = 2717, + SystemZ_VLREPF = 2718, + SystemZ_VLREPG = 2719, + SystemZ_VLREPH = 2720, + SystemZ_VLRL = 2721, + SystemZ_VLRLR = 2722, + SystemZ_VLVG = 2723, + SystemZ_VLVGB = 2724, + SystemZ_VLVGF = 2725, + SystemZ_VLVGG = 2726, + SystemZ_VLVGH = 2727, + SystemZ_VLVGP = 2728, + SystemZ_VMAE = 2729, + SystemZ_VMAEB = 2730, + SystemZ_VMAEF = 2731, + SystemZ_VMAEH = 2732, + SystemZ_VMAH = 2733, + SystemZ_VMAHB = 2734, + SystemZ_VMAHF = 2735, + SystemZ_VMAHH = 2736, + SystemZ_VMAL = 2737, + SystemZ_VMALB = 2738, + SystemZ_VMALE = 2739, + SystemZ_VMALEB = 2740, + SystemZ_VMALEF = 2741, + SystemZ_VMALEH = 2742, + SystemZ_VMALF = 2743, + SystemZ_VMALH = 2744, + SystemZ_VMALHB = 2745, + SystemZ_VMALHF = 2746, + SystemZ_VMALHH = 2747, + SystemZ_VMALHW = 2748, + SystemZ_VMALO = 2749, + SystemZ_VMALOB = 2750, + SystemZ_VMALOF = 2751, + SystemZ_VMALOH = 2752, + SystemZ_VMAO = 2753, + SystemZ_VMAOB = 2754, + SystemZ_VMAOF = 2755, + SystemZ_VMAOH = 2756, + SystemZ_VME = 2757, + SystemZ_VMEB = 2758, + SystemZ_VMEF = 2759, + SystemZ_VMEH = 2760, + SystemZ_VMH = 2761, + SystemZ_VMHB = 2762, + SystemZ_VMHF = 2763, + SystemZ_VMHH = 2764, + SystemZ_VML = 2765, + SystemZ_VMLB = 2766, + SystemZ_VMLE = 2767, + SystemZ_VMLEB = 2768, + SystemZ_VMLEF = 2769, + SystemZ_VMLEH = 2770, + SystemZ_VMLF = 2771, + SystemZ_VMLH = 2772, + SystemZ_VMLHB = 2773, + SystemZ_VMLHF = 2774, + SystemZ_VMLHH = 2775, + SystemZ_VMLHW = 2776, + SystemZ_VMLO = 2777, + SystemZ_VMLOB = 2778, + SystemZ_VMLOF = 2779, + SystemZ_VMLOH = 2780, + SystemZ_VMN = 2781, + SystemZ_VMNB = 2782, + SystemZ_VMNF = 2783, + SystemZ_VMNG = 2784, + SystemZ_VMNH = 2785, + SystemZ_VMNL = 2786, + SystemZ_VMNLB = 2787, + SystemZ_VMNLF = 2788, + SystemZ_VMNLG = 2789, + SystemZ_VMNLH = 2790, + SystemZ_VMO = 2791, + SystemZ_VMOB = 2792, + SystemZ_VMOF = 2793, + SystemZ_VMOH = 2794, + SystemZ_VMP = 2795, + SystemZ_VMRH = 2796, + SystemZ_VMRHB = 2797, + SystemZ_VMRHF = 2798, + SystemZ_VMRHG = 2799, + SystemZ_VMRHH = 2800, + SystemZ_VMRL = 2801, + SystemZ_VMRLB = 2802, + SystemZ_VMRLF = 2803, + SystemZ_VMRLG = 2804, + SystemZ_VMRLH = 2805, + SystemZ_VMSL = 2806, + SystemZ_VMSLG = 2807, + SystemZ_VMSP = 2808, + SystemZ_VMX = 2809, + SystemZ_VMXB = 2810, + SystemZ_VMXF = 2811, + SystemZ_VMXG = 2812, + SystemZ_VMXH = 2813, + SystemZ_VMXL = 2814, + SystemZ_VMXLB = 2815, + SystemZ_VMXLF = 2816, + SystemZ_VMXLG = 2817, + SystemZ_VMXLH = 2818, + SystemZ_VN = 2819, + SystemZ_VNC = 2820, + SystemZ_VNN = 2821, + SystemZ_VNO = 2822, + SystemZ_VNX = 2823, + SystemZ_VO = 2824, + SystemZ_VOC = 2825, + SystemZ_VONE = 2826, + SystemZ_VPDI = 2827, + SystemZ_VPERM = 2828, + SystemZ_VPK = 2829, + SystemZ_VPKF = 2830, + SystemZ_VPKG = 2831, + SystemZ_VPKH = 2832, + SystemZ_VPKLS = 2833, + SystemZ_VPKLSF = 2834, + SystemZ_VPKLSFS = 2835, + SystemZ_VPKLSG = 2836, + SystemZ_VPKLSGS = 2837, + SystemZ_VPKLSH = 2838, + SystemZ_VPKLSHS = 2839, + SystemZ_VPKS = 2840, + SystemZ_VPKSF = 2841, + SystemZ_VPKSFS = 2842, + SystemZ_VPKSG = 2843, + SystemZ_VPKSGS = 2844, + SystemZ_VPKSH = 2845, + SystemZ_VPKSHS = 2846, + SystemZ_VPKZ = 2847, + SystemZ_VPKZR = 2848, + SystemZ_VPOPCT = 2849, + SystemZ_VPOPCTB = 2850, + SystemZ_VPOPCTF = 2851, + SystemZ_VPOPCTG = 2852, + SystemZ_VPOPCTH = 2853, + SystemZ_VPSOP = 2854, + SystemZ_VREP = 2855, + SystemZ_VREPB = 2856, + SystemZ_VREPF = 2857, + SystemZ_VREPG = 2858, + SystemZ_VREPH = 2859, + SystemZ_VREPI = 2860, + SystemZ_VREPIB = 2861, + SystemZ_VREPIF = 2862, + SystemZ_VREPIG = 2863, + SystemZ_VREPIH = 2864, + SystemZ_VRP = 2865, + SystemZ_VS = 2866, + SystemZ_VSB = 2867, + SystemZ_VSBCBI = 2868, + SystemZ_VSBCBIQ = 2869, + SystemZ_VSBI = 2870, + SystemZ_VSBIQ = 2871, + SystemZ_VSCBI = 2872, + SystemZ_VSCBIB = 2873, + SystemZ_VSCBIF = 2874, + SystemZ_VSCBIG = 2875, + SystemZ_VSCBIH = 2876, + SystemZ_VSCBIQ = 2877, + SystemZ_VSCEF = 2878, + SystemZ_VSCEG = 2879, + SystemZ_VSCHDP = 2880, + SystemZ_VSCHP = 2881, + SystemZ_VSCHSP = 2882, + SystemZ_VSCHXP = 2883, + SystemZ_VSCSHP = 2884, + SystemZ_VSDP = 2885, + SystemZ_VSEG = 2886, + SystemZ_VSEGB = 2887, + SystemZ_VSEGF = 2888, + SystemZ_VSEGH = 2889, + SystemZ_VSEL = 2890, + SystemZ_VSF = 2891, + SystemZ_VSG = 2892, + SystemZ_VSH = 2893, + SystemZ_VSL = 2894, + SystemZ_VSLB = 2895, + SystemZ_VSLD = 2896, + SystemZ_VSLDB = 2897, + SystemZ_VSP = 2898, + SystemZ_VSQ = 2899, + SystemZ_VSRA = 2900, + SystemZ_VSRAB = 2901, + SystemZ_VSRD = 2902, + SystemZ_VSRL = 2903, + SystemZ_VSRLB = 2904, + SystemZ_VSRP = 2905, + SystemZ_VSRPR = 2906, + SystemZ_VST = 2907, + SystemZ_VSTAlign = 2908, + SystemZ_VSTBR = 2909, + SystemZ_VSTBRF = 2910, + SystemZ_VSTBRG = 2911, + SystemZ_VSTBRH = 2912, + SystemZ_VSTBRQ = 2913, + SystemZ_VSTEB = 2914, + SystemZ_VSTEBRF = 2915, + SystemZ_VSTEBRG = 2916, + SystemZ_VSTEBRH = 2917, + SystemZ_VSTEF = 2918, + SystemZ_VSTEG = 2919, + SystemZ_VSTEH = 2920, + SystemZ_VSTER = 2921, + SystemZ_VSTERF = 2922, + SystemZ_VSTERG = 2923, + SystemZ_VSTERH = 2924, + SystemZ_VSTL = 2925, + SystemZ_VSTM = 2926, + SystemZ_VSTMAlign = 2927, + SystemZ_VSTRC = 2928, + SystemZ_VSTRCB = 2929, + SystemZ_VSTRCBS = 2930, + SystemZ_VSTRCF = 2931, + SystemZ_VSTRCFS = 2932, + SystemZ_VSTRCH = 2933, + SystemZ_VSTRCHS = 2934, + SystemZ_VSTRCZB = 2935, + SystemZ_VSTRCZBS = 2936, + SystemZ_VSTRCZF = 2937, + SystemZ_VSTRCZFS = 2938, + SystemZ_VSTRCZH = 2939, + SystemZ_VSTRCZHS = 2940, + SystemZ_VSTRL = 2941, + SystemZ_VSTRLR = 2942, + SystemZ_VSTRS = 2943, + SystemZ_VSTRSB = 2944, + SystemZ_VSTRSF = 2945, + SystemZ_VSTRSH = 2946, + SystemZ_VSTRSZB = 2947, + SystemZ_VSTRSZF = 2948, + SystemZ_VSTRSZH = 2949, + SystemZ_VSUM = 2950, + SystemZ_VSUMB = 2951, + SystemZ_VSUMG = 2952, + SystemZ_VSUMGF = 2953, + SystemZ_VSUMGH = 2954, + SystemZ_VSUMH = 2955, + SystemZ_VSUMQ = 2956, + SystemZ_VSUMQF = 2957, + SystemZ_VSUMQG = 2958, + SystemZ_VTM = 2959, + SystemZ_VTP = 2960, + SystemZ_VUPH = 2961, + SystemZ_VUPHB = 2962, + SystemZ_VUPHF = 2963, + SystemZ_VUPHH = 2964, + SystemZ_VUPKZ = 2965, + SystemZ_VUPKZH = 2966, + SystemZ_VUPKZL = 2967, + SystemZ_VUPL = 2968, + SystemZ_VUPLB = 2969, + SystemZ_VUPLF = 2970, + SystemZ_VUPLH = 2971, + SystemZ_VUPLHB = 2972, + SystemZ_VUPLHF = 2973, + SystemZ_VUPLHH = 2974, + SystemZ_VUPLHW = 2975, + SystemZ_VUPLL = 2976, + SystemZ_VUPLLB = 2977, + SystemZ_VUPLLF = 2978, + SystemZ_VUPLLH = 2979, + SystemZ_VX = 2980, + SystemZ_VZERO = 2981, + SystemZ_WCDGB = 2982, + SystemZ_WCDLGB = 2983, + SystemZ_WCEFB = 2984, + SystemZ_WCELFB = 2985, + SystemZ_WCFEB = 2986, + SystemZ_WCGDB = 2987, + SystemZ_WCLFEB = 2988, + SystemZ_WCLGDB = 2989, + SystemZ_WFADB = 2990, + SystemZ_WFASB = 2991, + SystemZ_WFAXB = 2992, + SystemZ_WFC = 2993, + SystemZ_WFCDB = 2994, + SystemZ_WFCEDB = 2995, + SystemZ_WFCEDBS = 2996, + SystemZ_WFCESB = 2997, + SystemZ_WFCESBS = 2998, + SystemZ_WFCEXB = 2999, + SystemZ_WFCEXBS = 3000, + SystemZ_WFCHDB = 3001, + SystemZ_WFCHDBS = 3002, + SystemZ_WFCHEDB = 3003, + SystemZ_WFCHEDBS = 3004, + SystemZ_WFCHESB = 3005, + SystemZ_WFCHESBS = 3006, + SystemZ_WFCHEXB = 3007, + SystemZ_WFCHEXBS = 3008, + SystemZ_WFCHSB = 3009, + SystemZ_WFCHSBS = 3010, + SystemZ_WFCHXB = 3011, + SystemZ_WFCHXBS = 3012, + SystemZ_WFCSB = 3013, + SystemZ_WFCXB = 3014, + SystemZ_WFDDB = 3015, + SystemZ_WFDSB = 3016, + SystemZ_WFDXB = 3017, + SystemZ_WFIDB = 3018, + SystemZ_WFISB = 3019, + SystemZ_WFIXB = 3020, + SystemZ_WFK = 3021, + SystemZ_WFKDB = 3022, + SystemZ_WFKEDB = 3023, + SystemZ_WFKEDBS = 3024, + SystemZ_WFKESB = 3025, + SystemZ_WFKESBS = 3026, + SystemZ_WFKEXB = 3027, + SystemZ_WFKEXBS = 3028, + SystemZ_WFKHDB = 3029, + SystemZ_WFKHDBS = 3030, + SystemZ_WFKHEDB = 3031, + SystemZ_WFKHEDBS = 3032, + SystemZ_WFKHESB = 3033, + SystemZ_WFKHESBS = 3034, + SystemZ_WFKHEXB = 3035, + SystemZ_WFKHEXBS = 3036, + SystemZ_WFKHSB = 3037, + SystemZ_WFKHSBS = 3038, + SystemZ_WFKHXB = 3039, + SystemZ_WFKHXBS = 3040, + SystemZ_WFKSB = 3041, + SystemZ_WFKXB = 3042, + SystemZ_WFLCDB = 3043, + SystemZ_WFLCSB = 3044, + SystemZ_WFLCXB = 3045, + SystemZ_WFLLD = 3046, + SystemZ_WFLLS = 3047, + SystemZ_WFLNDB = 3048, + SystemZ_WFLNSB = 3049, + SystemZ_WFLNXB = 3050, + SystemZ_WFLPDB = 3051, + SystemZ_WFLPSB = 3052, + SystemZ_WFLPXB = 3053, + SystemZ_WFLRD = 3054, + SystemZ_WFLRX = 3055, + SystemZ_WFMADB = 3056, + SystemZ_WFMASB = 3057, + SystemZ_WFMAXB = 3058, + SystemZ_WFMAXDB = 3059, + SystemZ_WFMAXSB = 3060, + SystemZ_WFMAXXB = 3061, + SystemZ_WFMDB = 3062, + SystemZ_WFMINDB = 3063, + SystemZ_WFMINSB = 3064, + SystemZ_WFMINXB = 3065, + SystemZ_WFMSB = 3066, + SystemZ_WFMSDB = 3067, + SystemZ_WFMSSB = 3068, + SystemZ_WFMSXB = 3069, + SystemZ_WFMXB = 3070, + SystemZ_WFNMADB = 3071, + SystemZ_WFNMASB = 3072, + SystemZ_WFNMAXB = 3073, + SystemZ_WFNMSDB = 3074, + SystemZ_WFNMSSB = 3075, + SystemZ_WFNMSXB = 3076, + SystemZ_WFPSODB = 3077, + SystemZ_WFPSOSB = 3078, + SystemZ_WFPSOXB = 3079, + SystemZ_WFSDB = 3080, + SystemZ_WFSQDB = 3081, + SystemZ_WFSQSB = 3082, + SystemZ_WFSQXB = 3083, + SystemZ_WFSSB = 3084, + SystemZ_WFSXB = 3085, + SystemZ_WFTCIDB = 3086, + SystemZ_WFTCISB = 3087, + SystemZ_WFTCIXB = 3088, + SystemZ_WLDEB = 3089, + SystemZ_WLEDB = 3090, + SystemZ_X = 3091, + SystemZ_XC = 3092, + SystemZ_XG = 3093, + SystemZ_XGR = 3094, + SystemZ_XGRK = 3095, + SystemZ_XI = 3096, + SystemZ_XIHF = 3097, + SystemZ_XILF = 3098, + SystemZ_XIY = 3099, + SystemZ_XR = 3100, + SystemZ_XRK = 3101, + SystemZ_XSCH = 3102, + SystemZ_XY = 3103, + SystemZ_ZAP = 3104, + INSTRUCTION_LIST_END = 3105 }; #endif // GET_INSTRINFO_ENUM + +#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) +typedef struct SystemZInstrTable { + MCInstrDesc Insts[3105]; + MCOperandInfo OperandInfo[1650]; + MCPhysReg ImplicitOps[102]; +} SystemZInstrTable; + +#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) + +#ifdef GET_INSTRINFO_MC_DESC +#undef GET_INSTRINFO_MC_DESC + +static const unsigned SystemZImpOpBase = sizeof(MCOperandInfo) / (sizeof(MCPhysReg)); + +static const SystemZInstrTable SystemZDescs = { + { + { 6, &SystemZDescs.OperandInfo[532] }, // Inst #3104 = ZAP + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #3103 = XY + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #3102 = XSCH + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #3101 = XRK + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #3100 = XR + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #3099 = XIY + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #3098 = XILF + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #3097 = XIHF + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #3096 = XI + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #3095 = XGRK + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #3094 = XGR + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #3093 = XG + { 5, &SystemZDescs.OperandInfo[777] }, // Inst #3092 = XC + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #3091 = X + { 4, &SystemZDescs.OperandInfo[1620] }, // Inst #3090 = WLEDB + { 2, &SystemZDescs.OperandInfo[1618] }, // Inst #3089 = WLDEB + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #3088 = WFTCIXB + { 3, &SystemZDescs.OperandInfo[1647] }, // Inst #3087 = WFTCISB + { 3, &SystemZDescs.OperandInfo[1644] }, // Inst #3086 = WFTCIDB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #3085 = WFSXB + { 3, &SystemZDescs.OperandInfo[1613] }, // Inst #3084 = WFSSB + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #3083 = WFSQXB + { 2, &SystemZDescs.OperandInfo[468] }, // Inst #3082 = WFSQSB + { 2, &SystemZDescs.OperandInfo[470] }, // Inst #3081 = WFSQDB + { 3, &SystemZDescs.OperandInfo[1610] }, // Inst #3080 = WFSDB + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #3079 = WFPSOXB + { 3, &SystemZDescs.OperandInfo[1647] }, // Inst #3078 = WFPSOSB + { 3, &SystemZDescs.OperandInfo[1644] }, // Inst #3077 = WFPSODB + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #3076 = WFNMSXB + { 4, &SystemZDescs.OperandInfo[1632] }, // Inst #3075 = WFNMSSB + { 4, &SystemZDescs.OperandInfo[1628] }, // Inst #3074 = WFNMSDB + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #3073 = WFNMAXB + { 4, &SystemZDescs.OperandInfo[1632] }, // Inst #3072 = WFNMASB + { 4, &SystemZDescs.OperandInfo[1628] }, // Inst #3071 = WFNMADB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #3070 = WFMXB + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #3069 = WFMSXB + { 4, &SystemZDescs.OperandInfo[1632] }, // Inst #3068 = WFMSSB + { 4, &SystemZDescs.OperandInfo[1628] }, // Inst #3067 = WFMSDB + { 3, &SystemZDescs.OperandInfo[1613] }, // Inst #3066 = WFMSB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #3065 = WFMINXB + { 4, &SystemZDescs.OperandInfo[1640] }, // Inst #3064 = WFMINSB + { 4, &SystemZDescs.OperandInfo[1636] }, // Inst #3063 = WFMINDB + { 3, &SystemZDescs.OperandInfo[1610] }, // Inst #3062 = WFMDB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #3061 = WFMAXXB + { 4, &SystemZDescs.OperandInfo[1640] }, // Inst #3060 = WFMAXSB + { 4, &SystemZDescs.OperandInfo[1636] }, // Inst #3059 = WFMAXDB + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #3058 = WFMAXB + { 4, &SystemZDescs.OperandInfo[1632] }, // Inst #3057 = WFMASB + { 4, &SystemZDescs.OperandInfo[1628] }, // Inst #3056 = WFMADB + { 4, &SystemZDescs.OperandInfo[1624] }, // Inst #3055 = WFLRX + { 4, &SystemZDescs.OperandInfo[1620] }, // Inst #3054 = WFLRD + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #3053 = WFLPXB + { 2, &SystemZDescs.OperandInfo[468] }, // Inst #3052 = WFLPSB + { 2, &SystemZDescs.OperandInfo[470] }, // Inst #3051 = WFLPDB + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #3050 = WFLNXB + { 2, &SystemZDescs.OperandInfo[468] }, // Inst #3049 = WFLNSB + { 2, &SystemZDescs.OperandInfo[470] }, // Inst #3048 = WFLNDB + { 2, &SystemZDescs.OperandInfo[1618] }, // Inst #3047 = WFLLS + { 2, &SystemZDescs.OperandInfo[1616] }, // Inst #3046 = WFLLD + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #3045 = WFLCXB + { 2, &SystemZDescs.OperandInfo[468] }, // Inst #3044 = WFLCSB + { 2, &SystemZDescs.OperandInfo[470] }, // Inst #3043 = WFLCDB + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #3042 = WFKXB + { 2, &SystemZDescs.OperandInfo[468] }, // Inst #3041 = WFKSB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #3040 = WFKHXBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #3039 = WFKHXB + { 3, &SystemZDescs.OperandInfo[1613] }, // Inst #3038 = WFKHSBS + { 3, &SystemZDescs.OperandInfo[1613] }, // Inst #3037 = WFKHSB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #3036 = WFKHEXBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #3035 = WFKHEXB + { 3, &SystemZDescs.OperandInfo[1613] }, // Inst #3034 = WFKHESBS + { 3, &SystemZDescs.OperandInfo[1613] }, // Inst #3033 = WFKHESB + { 3, &SystemZDescs.OperandInfo[1610] }, // Inst #3032 = WFKHEDBS + { 3, &SystemZDescs.OperandInfo[1610] }, // Inst #3031 = WFKHEDB + { 3, &SystemZDescs.OperandInfo[1610] }, // Inst #3030 = WFKHDBS + { 3, &SystemZDescs.OperandInfo[1610] }, // Inst #3029 = WFKHDB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #3028 = WFKEXBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #3027 = WFKEXB + { 3, &SystemZDescs.OperandInfo[1613] }, // Inst #3026 = WFKESBS + { 3, &SystemZDescs.OperandInfo[1613] }, // Inst #3025 = WFKESB + { 3, &SystemZDescs.OperandInfo[1610] }, // Inst #3024 = WFKEDBS + { 3, &SystemZDescs.OperandInfo[1610] }, // Inst #3023 = WFKEDB + { 2, &SystemZDescs.OperandInfo[470] }, // Inst #3022 = WFKDB + { 4, &SystemZDescs.OperandInfo[1602] }, // Inst #3021 = WFK + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #3020 = WFIXB + { 4, &SystemZDescs.OperandInfo[1606] }, // Inst #3019 = WFISB + { 4, &SystemZDescs.OperandInfo[1602] }, // Inst #3018 = WFIDB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #3017 = WFDXB + { 3, &SystemZDescs.OperandInfo[1613] }, // Inst #3016 = WFDSB + { 3, &SystemZDescs.OperandInfo[1610] }, // Inst #3015 = WFDDB + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #3014 = WFCXB + { 2, &SystemZDescs.OperandInfo[468] }, // Inst #3013 = WFCSB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #3012 = WFCHXBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #3011 = WFCHXB + { 3, &SystemZDescs.OperandInfo[1613] }, // Inst #3010 = WFCHSBS + { 3, &SystemZDescs.OperandInfo[1613] }, // Inst #3009 = WFCHSB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #3008 = WFCHEXBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #3007 = WFCHEXB + { 3, &SystemZDescs.OperandInfo[1613] }, // Inst #3006 = WFCHESBS + { 3, &SystemZDescs.OperandInfo[1613] }, // Inst #3005 = WFCHESB + { 3, &SystemZDescs.OperandInfo[1610] }, // Inst #3004 = WFCHEDBS + { 3, &SystemZDescs.OperandInfo[1610] }, // Inst #3003 = WFCHEDB + { 3, &SystemZDescs.OperandInfo[1610] }, // Inst #3002 = WFCHDBS + { 3, &SystemZDescs.OperandInfo[1610] }, // Inst #3001 = WFCHDB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #3000 = WFCEXBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2999 = WFCEXB + { 3, &SystemZDescs.OperandInfo[1613] }, // Inst #2998 = WFCESBS + { 3, &SystemZDescs.OperandInfo[1613] }, // Inst #2997 = WFCESB + { 3, &SystemZDescs.OperandInfo[1610] }, // Inst #2996 = WFCEDBS + { 3, &SystemZDescs.OperandInfo[1610] }, // Inst #2995 = WFCEDB + { 2, &SystemZDescs.OperandInfo[470] }, // Inst #2994 = WFCDB + { 4, &SystemZDescs.OperandInfo[1602] }, // Inst #2993 = WFC + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2992 = WFAXB + { 3, &SystemZDescs.OperandInfo[1613] }, // Inst #2991 = WFASB + { 3, &SystemZDescs.OperandInfo[1610] }, // Inst #2990 = WFADB + { 4, &SystemZDescs.OperandInfo[1602] }, // Inst #2989 = WCLGDB + { 4, &SystemZDescs.OperandInfo[1606] }, // Inst #2988 = WCLFEB + { 4, &SystemZDescs.OperandInfo[1602] }, // Inst #2987 = WCGDB + { 4, &SystemZDescs.OperandInfo[1606] }, // Inst #2986 = WCFEB + { 4, &SystemZDescs.OperandInfo[1606] }, // Inst #2985 = WCELFB + { 4, &SystemZDescs.OperandInfo[1606] }, // Inst #2984 = WCEFB + { 4, &SystemZDescs.OperandInfo[1602] }, // Inst #2983 = WCDLGB + { 4, &SystemZDescs.OperandInfo[1602] }, // Inst #2982 = WCDGB + { 1, &SystemZDescs.OperandInfo[1596] }, // Inst #2981 = VZERO + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2980 = VX + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2979 = VUPLLH + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2978 = VUPLLF + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2977 = VUPLLB + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2976 = VUPLL + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2975 = VUPLHW + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2974 = VUPLHH + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2973 = VUPLHF + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2972 = VUPLHB + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2971 = VUPLH + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2970 = VUPLF + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2969 = VUPLB + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2968 = VUPL + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2967 = VUPKZL + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2966 = VUPKZH + { 4, &SystemZDescs.OperandInfo[1573] }, // Inst #2965 = VUPKZ + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2964 = VUPHH + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2963 = VUPHF + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2962 = VUPHB + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2961 = VUPH + { 1, &SystemZDescs.OperandInfo[1596] }, // Inst #2960 = VTP + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2959 = VTM + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2958 = VSUMQG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2957 = VSUMQF + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2956 = VSUMQ + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2955 = VSUMH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2954 = VSUMGH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2953 = VSUMGF + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2952 = VSUMG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2951 = VSUMB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2950 = VSUM + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2949 = VSTRSZH + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2948 = VSTRSZF + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2947 = VSTRSZB + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2946 = VSTRSH + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2945 = VSTRSF + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2944 = VSTRSB + { 6, &SystemZDescs.OperandInfo[1511] }, // Inst #2943 = VSTRS + { 4, &SystemZDescs.OperandInfo[1560] }, // Inst #2942 = VSTRLR + { 4, &SystemZDescs.OperandInfo[1573] }, // Inst #2941 = VSTRL + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2940 = VSTRCZHS + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2939 = VSTRCZH + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2938 = VSTRCZFS + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2937 = VSTRCZF + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2936 = VSTRCZBS + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2935 = VSTRCZB + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2934 = VSTRCHS + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2933 = VSTRCH + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2932 = VSTRCFS + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2931 = VSTRCF + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2930 = VSTRCBS + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2929 = VSTRCB + { 6, &SystemZDescs.OperandInfo[1511] }, // Inst #2928 = VSTRC + { 5, &SystemZDescs.OperandInfo[1568] }, // Inst #2927 = VSTMAlign + { 4, &SystemZDescs.OperandInfo[1564] }, // Inst #2926 = VSTM + { 4, &SystemZDescs.OperandInfo[1560] }, // Inst #2925 = VSTL + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2924 = VSTERH + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2923 = VSTERG + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2922 = VSTERF + { 5, &SystemZDescs.OperandInfo[1536] }, // Inst #2921 = VSTER + { 5, &SystemZDescs.OperandInfo[1536] }, // Inst #2920 = VSTEH + { 5, &SystemZDescs.OperandInfo[1536] }, // Inst #2919 = VSTEG + { 5, &SystemZDescs.OperandInfo[1536] }, // Inst #2918 = VSTEF + { 5, &SystemZDescs.OperandInfo[1536] }, // Inst #2917 = VSTEBRH + { 5, &SystemZDescs.OperandInfo[1536] }, // Inst #2916 = VSTEBRG + { 5, &SystemZDescs.OperandInfo[1536] }, // Inst #2915 = VSTEBRF + { 5, &SystemZDescs.OperandInfo[1536] }, // Inst #2914 = VSTEB + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2913 = VSTBRQ + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2912 = VSTBRH + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2911 = VSTBRG + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2910 = VSTBRF + { 5, &SystemZDescs.OperandInfo[1536] }, // Inst #2909 = VSTBR + { 5, &SystemZDescs.OperandInfo[1536] }, // Inst #2908 = VSTAlign + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2907 = VST + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2906 = VSRPR + { 5, &SystemZDescs.OperandInfo[1451] }, // Inst #2905 = VSRP + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2904 = VSRLB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2903 = VSRL + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2902 = VSRD + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2901 = VSRAB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2900 = VSRA + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2899 = VSQ + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2898 = VSP + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2897 = VSLDB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2896 = VSLD + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2895 = VSLB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2894 = VSL + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2893 = VSH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2892 = VSG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2891 = VSF + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2890 = VSEL + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2889 = VSEGH + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2888 = VSEGF + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2887 = VSEGB + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2886 = VSEG + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2885 = VSDP + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2884 = VSCSHP + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2883 = VSCHXP + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2882 = VSCHSP + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2881 = VSCHP + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2880 = VSCHDP + { 5, &SystemZDescs.OperandInfo[1597] }, // Inst #2879 = VSCEG + { 5, &SystemZDescs.OperandInfo[1597] }, // Inst #2878 = VSCEF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2877 = VSCBIQ + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2876 = VSCBIH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2875 = VSCBIG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2874 = VSCBIF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2873 = VSCBIB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2872 = VSCBI + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2871 = VSBIQ + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2870 = VSBI + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2869 = VSBCBIQ + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2868 = VSBCBI + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2867 = VSB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2866 = VS + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2865 = VRP + { 2, &SystemZDescs.OperandInfo[1517] }, // Inst #2864 = VREPIH + { 2, &SystemZDescs.OperandInfo[1517] }, // Inst #2863 = VREPIG + { 2, &SystemZDescs.OperandInfo[1517] }, // Inst #2862 = VREPIF + { 2, &SystemZDescs.OperandInfo[1517] }, // Inst #2861 = VREPIB + { 3, &SystemZDescs.OperandInfo[1529] }, // Inst #2860 = VREPI + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2859 = VREPH + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2858 = VREPG + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2857 = VREPF + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2856 = VREPB + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2855 = VREP + { 5, &SystemZDescs.OperandInfo[1451] }, // Inst #2854 = VPSOP + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2853 = VPOPCTH + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2852 = VPOPCTG + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2851 = VPOPCTF + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2850 = VPOPCTB + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2849 = VPOPCT + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2848 = VPKZR + { 4, &SystemZDescs.OperandInfo[1573] }, // Inst #2847 = VPKZ + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2846 = VPKSHS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2845 = VPKSH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2844 = VPKSGS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2843 = VPKSG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2842 = VPKSFS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2841 = VPKSF + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2840 = VPKS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2839 = VPKLSHS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2838 = VPKLSH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2837 = VPKLSGS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2836 = VPKLSG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2835 = VPKLSFS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2834 = VPKLSF + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2833 = VPKLS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2832 = VPKH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2831 = VPKG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2830 = VPKF + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2829 = VPK + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2828 = VPERM + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2827 = VPDI + { 1, &SystemZDescs.OperandInfo[1596] }, // Inst #2826 = VONE + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2825 = VOC + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2824 = VO + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2823 = VNX + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2822 = VNO + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2821 = VNN + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2820 = VNC + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2819 = VN + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2818 = VMXLH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2817 = VMXLG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2816 = VMXLF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2815 = VMXLB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2814 = VMXL + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2813 = VMXH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2812 = VMXG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2811 = VMXF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2810 = VMXB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2809 = VMX + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2808 = VMSP + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2807 = VMSLG + { 6, &SystemZDescs.OperandInfo[1511] }, // Inst #2806 = VMSL + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2805 = VMRLH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2804 = VMRLG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2803 = VMRLF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2802 = VMRLB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2801 = VMRL + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2800 = VMRHH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2799 = VMRHG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2798 = VMRHF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2797 = VMRHB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2796 = VMRH + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2795 = VMP + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2794 = VMOH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2793 = VMOF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2792 = VMOB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2791 = VMO + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2790 = VMNLH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2789 = VMNLG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2788 = VMNLF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2787 = VMNLB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2786 = VMNL + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2785 = VMNH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2784 = VMNG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2783 = VMNF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2782 = VMNB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2781 = VMN + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2780 = VMLOH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2779 = VMLOF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2778 = VMLOB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2777 = VMLO + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2776 = VMLHW + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2775 = VMLHH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2774 = VMLHF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2773 = VMLHB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2772 = VMLH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2771 = VMLF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2770 = VMLEH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2769 = VMLEF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2768 = VMLEB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2767 = VMLE + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2766 = VMLB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2765 = VML + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2764 = VMHH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2763 = VMHF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2762 = VMHB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2761 = VMH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2760 = VMEH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2759 = VMEF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2758 = VMEB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2757 = VME + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2756 = VMAOH + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2755 = VMAOF + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2754 = VMAOB + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2753 = VMAO + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2752 = VMALOH + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2751 = VMALOF + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2750 = VMALOB + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2749 = VMALO + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2748 = VMALHW + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2747 = VMALHH + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2746 = VMALHF + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2745 = VMALHB + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2744 = VMALH + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2743 = VMALF + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2742 = VMALEH + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2741 = VMALEF + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2740 = VMALEB + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2739 = VMALE + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2738 = VMALB + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2737 = VMAL + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2736 = VMAHH + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2735 = VMAHF + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2734 = VMAHB + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2733 = VMAH + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2732 = VMAEH + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2731 = VMAEF + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2730 = VMAEB + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2729 = VMAE + { 3, &SystemZDescs.OperandInfo[1593] }, // Inst #2728 = VLVGP + { 5, &SystemZDescs.OperandInfo[1583] }, // Inst #2727 = VLVGH + { 5, &SystemZDescs.OperandInfo[1588] }, // Inst #2726 = VLVGG + { 5, &SystemZDescs.OperandInfo[1583] }, // Inst #2725 = VLVGF + { 5, &SystemZDescs.OperandInfo[1583] }, // Inst #2724 = VLVGB + { 6, &SystemZDescs.OperandInfo[1577] }, // Inst #2723 = VLVG + { 4, &SystemZDescs.OperandInfo[1560] }, // Inst #2722 = VLRLR + { 4, &SystemZDescs.OperandInfo[1573] }, // Inst #2721 = VLRL + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2720 = VLREPH + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2719 = VLREPG + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2718 = VLREPF + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2717 = VLREPB + { 5, &SystemZDescs.OperandInfo[1536] }, // Inst #2716 = VLREP + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2715 = VLR + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2714 = VLPH + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2713 = VLPG + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2712 = VLPF + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2711 = VLPB + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2710 = VLP + { 5, &SystemZDescs.OperandInfo[1568] }, // Inst #2709 = VLMAlign + { 4, &SystemZDescs.OperandInfo[1564] }, // Inst #2708 = VLM + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2707 = VLLEZLF + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2706 = VLLEZH + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2705 = VLLEZG + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2704 = VLLEZF + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2703 = VLLEZB + { 5, &SystemZDescs.OperandInfo[1536] }, // Inst #2702 = VLLEZ + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2701 = VLLEBRZH + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2700 = VLLEBRZG + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2699 = VLLEBRZF + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2698 = VLLEBRZE + { 5, &SystemZDescs.OperandInfo[1536] }, // Inst #2697 = VLLEBRZ + { 4, &SystemZDescs.OperandInfo[1560] }, // Inst #2696 = VLL + { 3, &SystemZDescs.OperandInfo[1529] }, // Inst #2695 = VLIP + { 4, &SystemZDescs.OperandInfo[1556] }, // Inst #2694 = VLGVH + { 4, &SystemZDescs.OperandInfo[1556] }, // Inst #2693 = VLGVG + { 4, &SystemZDescs.OperandInfo[1556] }, // Inst #2692 = VLGVF + { 4, &SystemZDescs.OperandInfo[1556] }, // Inst #2691 = VLGVB + { 5, &SystemZDescs.OperandInfo[1551] }, // Inst #2690 = VLGV + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2689 = VLERH + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2688 = VLERG + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2687 = VLERF + { 5, &SystemZDescs.OperandInfo[1536] }, // Inst #2686 = VLER + { 4, &SystemZDescs.OperandInfo[1547] }, // Inst #2685 = VLEIH + { 4, &SystemZDescs.OperandInfo[1547] }, // Inst #2684 = VLEIG + { 4, &SystemZDescs.OperandInfo[1547] }, // Inst #2683 = VLEIF + { 4, &SystemZDescs.OperandInfo[1547] }, // Inst #2682 = VLEIB + { 6, &SystemZDescs.OperandInfo[1541] }, // Inst #2681 = VLEH + { 6, &SystemZDescs.OperandInfo[1541] }, // Inst #2680 = VLEG + { 6, &SystemZDescs.OperandInfo[1541] }, // Inst #2679 = VLEF + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2678 = VLEDB + { 5, &SystemZDescs.OperandInfo[1451] }, // Inst #2677 = VLED + { 6, &SystemZDescs.OperandInfo[1541] }, // Inst #2676 = VLEBRH + { 6, &SystemZDescs.OperandInfo[1541] }, // Inst #2675 = VLEBRG + { 6, &SystemZDescs.OperandInfo[1541] }, // Inst #2674 = VLEBRF + { 6, &SystemZDescs.OperandInfo[1541] }, // Inst #2673 = VLEB + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2672 = VLDEB + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2671 = VLDE + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2670 = VLCH + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2669 = VLCG + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2668 = VLCF + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2667 = VLCB + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2666 = VLC + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2665 = VLBRREPH + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2664 = VLBRREPG + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2663 = VLBRREPF + { 5, &SystemZDescs.OperandInfo[1536] }, // Inst #2662 = VLBRREP + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2661 = VLBRQ + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2660 = VLBRH + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2659 = VLBRG + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2658 = VLBRF + { 5, &SystemZDescs.OperandInfo[1536] }, // Inst #2657 = VLBR + { 5, &SystemZDescs.OperandInfo[1536] }, // Inst #2656 = VLBB + { 5, &SystemZDescs.OperandInfo[1536] }, // Inst #2655 = VLAlign + { 4, &SystemZDescs.OperandInfo[1532] }, // Inst #2654 = VL + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2653 = VISTRHS + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2652 = VISTRH + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2651 = VISTRFS + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2650 = VISTRF + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2649 = VISTRBS + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2648 = VISTRB + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2647 = VISTR + { 3, &SystemZDescs.OperandInfo[1529] }, // Inst #2646 = VGMH + { 3, &SystemZDescs.OperandInfo[1529] }, // Inst #2645 = VGMG + { 3, &SystemZDescs.OperandInfo[1529] }, // Inst #2644 = VGMF + { 3, &SystemZDescs.OperandInfo[1529] }, // Inst #2643 = VGMB + { 4, &SystemZDescs.OperandInfo[1525] }, // Inst #2642 = VGM + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2641 = VGFMH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2640 = VGFMG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2639 = VGFMF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2638 = VGFMB + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2637 = VGFMAH + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2636 = VGFMAG + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2635 = VGFMAF + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2634 = VGFMAB + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2633 = VGFMA + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2632 = VGFM + { 6, &SystemZDescs.OperandInfo[1519] }, // Inst #2631 = VGEG + { 6, &SystemZDescs.OperandInfo[1519] }, // Inst #2630 = VGEF + { 2, &SystemZDescs.OperandInfo[1517] }, // Inst #2629 = VGBM + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2628 = VFTCISB + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2627 = VFTCIDB + { 5, &SystemZDescs.OperandInfo[1451] }, // Inst #2626 = VFTCI + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2625 = VFSSB + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2624 = VFSQSB + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2623 = VFSQDB + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2622 = VFSQ + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2621 = VFSDB + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2620 = VFS + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2619 = VFPSOSB + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2618 = VFPSODB + { 5, &SystemZDescs.OperandInfo[1451] }, // Inst #2617 = VFPSO + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2616 = VFNMSSB + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2615 = VFNMSDB + { 6, &SystemZDescs.OperandInfo[1511] }, // Inst #2614 = VFNMS + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2613 = VFNMASB + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2612 = VFNMADB + { 6, &SystemZDescs.OperandInfo[1511] }, // Inst #2611 = VFNMA + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2610 = VFMSSB + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2609 = VFMSDB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2608 = VFMSB + { 6, &SystemZDescs.OperandInfo[1511] }, // Inst #2607 = VFMS + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2606 = VFMINSB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2605 = VFMINDB + { 6, &SystemZDescs.OperandInfo[1505] }, // Inst #2604 = VFMIN + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2603 = VFMDB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2602 = VFMAXSB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2601 = VFMAXDB + { 6, &SystemZDescs.OperandInfo[1505] }, // Inst #2600 = VFMAX + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2599 = VFMASB + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2598 = VFMADB + { 6, &SystemZDescs.OperandInfo[1511] }, // Inst #2597 = VFMA + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2596 = VFM + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2595 = VFLRD + { 5, &SystemZDescs.OperandInfo[1451] }, // Inst #2594 = VFLR + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2593 = VFLPSB + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2592 = VFLPDB + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2591 = VFLNSB + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2590 = VFLNDB + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2589 = VFLLS + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2588 = VFLL + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2587 = VFLCSB + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2586 = VFLCDB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2585 = VFKHSBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2584 = VFKHSB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2583 = VFKHESBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2582 = VFKHESB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2581 = VFKHEDBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2580 = VFKHEDB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2579 = VFKHDBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2578 = VFKHDB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2577 = VFKESBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2576 = VFKESB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2575 = VFKEDBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2574 = VFKEDB + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2573 = VFISB + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2572 = VFIDB + { 5, &SystemZDescs.OperandInfo[1451] }, // Inst #2571 = VFI + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2570 = VFENEZHS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2569 = VFENEZH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2568 = VFENEZFS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2567 = VFENEZF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2566 = VFENEZBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2565 = VFENEZB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2564 = VFENEHS + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2563 = VFENEH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2562 = VFENEFS + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2561 = VFENEF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2560 = VFENEBS + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2559 = VFENEB + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2558 = VFENE + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2557 = VFEEZHS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2556 = VFEEZH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2555 = VFEEZFS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2554 = VFEEZF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2553 = VFEEZBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2552 = VFEEZB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2551 = VFEEHS + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2550 = VFEEH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2549 = VFEEFS + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2548 = VFEEF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2547 = VFEEBS + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2546 = VFEEB + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2545 = VFEE + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2544 = VFDSB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2543 = VFDDB + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2542 = VFD + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2541 = VFCHSBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2540 = VFCHSB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2539 = VFCHESBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2538 = VFCHESB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2537 = VFCHEDBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2536 = VFCHEDB + { 6, &SystemZDescs.OperandInfo[1505] }, // Inst #2535 = VFCHE + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2534 = VFCHDBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2533 = VFCHDB + { 6, &SystemZDescs.OperandInfo[1505] }, // Inst #2532 = VFCH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2531 = VFCESBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2530 = VFCESB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2529 = VFCEDBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2528 = VFCEDB + { 6, &SystemZDescs.OperandInfo[1505] }, // Inst #2527 = VFCE + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2526 = VFASB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2525 = VFAEZHS + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2524 = VFAEZH + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2523 = VFAEZFS + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2522 = VFAEZF + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2521 = VFAEZBS + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2520 = VFAEZB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2519 = VFAEHS + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2518 = VFAEH + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2517 = VFAEFS + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2516 = VFAEF + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2515 = VFAEBS + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2514 = VFAEB + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2513 = VFAE + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2512 = VFADB + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2511 = VFA + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2510 = VESRLVH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2509 = VESRLVG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2508 = VESRLVF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2507 = VESRLVB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2506 = VESRLV + { 4, &SystemZDescs.OperandInfo[1501] }, // Inst #2505 = VESRLH + { 4, &SystemZDescs.OperandInfo[1501] }, // Inst #2504 = VESRLG + { 4, &SystemZDescs.OperandInfo[1501] }, // Inst #2503 = VESRLF + { 4, &SystemZDescs.OperandInfo[1501] }, // Inst #2502 = VESRLB + { 5, &SystemZDescs.OperandInfo[1496] }, // Inst #2501 = VESRL + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2500 = VESRAVH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2499 = VESRAVG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2498 = VESRAVF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2497 = VESRAVB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2496 = VESRAV + { 4, &SystemZDescs.OperandInfo[1501] }, // Inst #2495 = VESRAH + { 4, &SystemZDescs.OperandInfo[1501] }, // Inst #2494 = VESRAG + { 4, &SystemZDescs.OperandInfo[1501] }, // Inst #2493 = VESRAF + { 4, &SystemZDescs.OperandInfo[1501] }, // Inst #2492 = VESRAB + { 5, &SystemZDescs.OperandInfo[1496] }, // Inst #2491 = VESRA + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2490 = VESLVH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2489 = VESLVG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2488 = VESLVF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2487 = VESLVB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2486 = VESLV + { 4, &SystemZDescs.OperandInfo[1501] }, // Inst #2485 = VESLH + { 4, &SystemZDescs.OperandInfo[1501] }, // Inst #2484 = VESLG + { 4, &SystemZDescs.OperandInfo[1501] }, // Inst #2483 = VESLF + { 4, &SystemZDescs.OperandInfo[1501] }, // Inst #2482 = VESLB + { 5, &SystemZDescs.OperandInfo[1496] }, // Inst #2481 = VESL + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2480 = VERLLVH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2479 = VERLLVG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2478 = VERLLVF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2477 = VERLLVB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2476 = VERLLV + { 4, &SystemZDescs.OperandInfo[1501] }, // Inst #2475 = VERLLH + { 4, &SystemZDescs.OperandInfo[1501] }, // Inst #2474 = VERLLG + { 4, &SystemZDescs.OperandInfo[1501] }, // Inst #2473 = VERLLF + { 4, &SystemZDescs.OperandInfo[1501] }, // Inst #2472 = VERLLB + { 5, &SystemZDescs.OperandInfo[1496] }, // Inst #2471 = VERLL + { 5, &SystemZDescs.OperandInfo[1491] }, // Inst #2470 = VERIMH + { 5, &SystemZDescs.OperandInfo[1491] }, // Inst #2469 = VERIMG + { 5, &SystemZDescs.OperandInfo[1491] }, // Inst #2468 = VERIMF + { 5, &SystemZDescs.OperandInfo[1491] }, // Inst #2467 = VERIMB + { 6, &SystemZDescs.OperandInfo[1485] }, // Inst #2466 = VERIM + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2465 = VECLH + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2464 = VECLG + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2463 = VECLF + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2462 = VECLB + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2461 = VECL + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2460 = VECH + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2459 = VECG + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2458 = VECF + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2457 = VECB + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2456 = VEC + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2455 = VDP + { 4, &SystemZDescs.OperandInfo[1481] }, // Inst #2454 = VCVDG + { 4, &SystemZDescs.OperandInfo[1477] }, // Inst #2453 = VCVD + { 4, &SystemZDescs.OperandInfo[1473] }, // Inst #2452 = VCVBOpt + { 4, &SystemZDescs.OperandInfo[1469] }, // Inst #2451 = VCVBGOpt + { 3, &SystemZDescs.OperandInfo[1466] }, // Inst #2450 = VCVBG + { 3, &SystemZDescs.OperandInfo[1463] }, // Inst #2449 = VCVB + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2448 = VCTZH + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2447 = VCTZG + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2446 = VCTZF + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2445 = VCTZB + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2444 = VCTZ + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2443 = VCSPH + { 5, &SystemZDescs.OperandInfo[1451] }, // Inst #2442 = VCSFP + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2441 = VCRNF + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2440 = VCP + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2439 = VCNF + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2438 = VCLZH + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2437 = VCLZG + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2436 = VCLZF + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2435 = VCLZDP + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #2434 = VCLZB + { 3, &SystemZDescs.OperandInfo[1460] }, // Inst #2433 = VCLZ + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2432 = VCLGDB + { 5, &SystemZDescs.OperandInfo[1451] }, // Inst #2431 = VCLGD + { 5, &SystemZDescs.OperandInfo[1451] }, // Inst #2430 = VCLFP + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2429 = VCLFNL + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2428 = VCLFNH + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2427 = VCLFEB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2426 = VCKSM + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2425 = VCHLHS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2424 = VCHLH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2423 = VCHLGS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2422 = VCHLG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2421 = VCHLFS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2420 = VCHLF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2419 = VCHLBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2418 = VCHLB + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2417 = VCHL + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2416 = VCHHS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2415 = VCHH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2414 = VCHGS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2413 = VCHG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2412 = VCHFS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2411 = VCHF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2410 = VCHBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2409 = VCHB + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2408 = VCH + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2407 = VCGDB + { 5, &SystemZDescs.OperandInfo[1451] }, // Inst #2406 = VCGD + { 5, &SystemZDescs.OperandInfo[1451] }, // Inst #2405 = VCFPS + { 5, &SystemZDescs.OperandInfo[1451] }, // Inst #2404 = VCFPL + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2403 = VCFN + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2402 = VCFEB + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2401 = VCEQHS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2400 = VCEQH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2399 = VCEQGS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2398 = VCEQG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2397 = VCEQFS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2396 = VCEQF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2395 = VCEQBS + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2394 = VCEQB + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2393 = VCEQ + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2392 = VCELFB + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2391 = VCEFB + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2390 = VCDLGB + { 5, &SystemZDescs.OperandInfo[1451] }, // Inst #2389 = VCDLG + { 4, &SystemZDescs.OperandInfo[1456] }, // Inst #2388 = VCDGB + { 5, &SystemZDescs.OperandInfo[1451] }, // Inst #2387 = VCDG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2386 = VBPERM + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2385 = VAVGLH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2384 = VAVGLG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2383 = VAVGLF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2382 = VAVGLB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2381 = VAVGL + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2380 = VAVGH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2379 = VAVGG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2378 = VAVGF + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2377 = VAVGB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2376 = VAVG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2375 = VAQ + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #2374 = VAP + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2373 = VAH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2372 = VAG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2371 = VAF + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2370 = VACQ + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2369 = VACCQ + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2368 = VACCH + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2367 = VACCG + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2366 = VACCF + { 4, &SystemZDescs.OperandInfo[1447] }, // Inst #2365 = VACCCQ + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2364 = VACCC + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2363 = VACCB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2362 = VACC + { 5, &SystemZDescs.OperandInfo[1442] }, // Inst #2361 = VAC + { 3, &SystemZDescs.OperandInfo[1439] }, // Inst #2360 = VAB + { 4, &SystemZDescs.OperandInfo[1435] }, // Inst #2359 = VA + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #2358 = UPT + { 5, &SystemZDescs.OperandInfo[777] }, // Inst #2357 = UNPKU + { 5, &SystemZDescs.OperandInfo[777] }, // Inst #2356 = UNPKA + { 6, &SystemZDescs.OperandInfo[532] }, // Inst #2355 = UNPK + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2354 = TSCH + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2353 = TS + { 4, &SystemZDescs.OperandInfo[1419] }, // Inst #2352 = TRTTOpt + { 5, &SystemZDescs.OperandInfo[1423] }, // Inst #2351 = TRTT + { 3, &SystemZDescs.OperandInfo[1432] }, // Inst #2350 = TRTREOpt + { 4, &SystemZDescs.OperandInfo[1428] }, // Inst #2349 = TRTRE + { 5, &SystemZDescs.OperandInfo[777] }, // Inst #2348 = TRTR + { 4, &SystemZDescs.OperandInfo[1419] }, // Inst #2347 = TRTOOpt + { 5, &SystemZDescs.OperandInfo[1423] }, // Inst #2346 = TRTO + { 3, &SystemZDescs.OperandInfo[1432] }, // Inst #2345 = TRTEOpt + { 4, &SystemZDescs.OperandInfo[1428] }, // Inst #2344 = TRTE + { 5, &SystemZDescs.OperandInfo[777] }, // Inst #2343 = TRT + { 4, &SystemZDescs.OperandInfo[1419] }, // Inst #2342 = TROTOpt + { 5, &SystemZDescs.OperandInfo[1423] }, // Inst #2341 = TROT + { 4, &SystemZDescs.OperandInfo[1419] }, // Inst #2340 = TROOOpt + { 5, &SystemZDescs.OperandInfo[1423] }, // Inst #2339 = TROO + { 4, &SystemZDescs.OperandInfo[1419] }, // Inst #2338 = TRE + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2337 = TRAP4 + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #2336 = TRAP2 + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #2335 = TRACG + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #2334 = TRACE + { 5, &SystemZDescs.OperandInfo[777] }, // Inst #2333 = TR + { 4, &SystemZDescs.OperandInfo[1096] }, // Inst #2332 = TPROT + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2331 = TPI + { 3, &SystemZDescs.OperandInfo[1416] }, // Inst #2330 = TP + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #2329 = TMY + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #2328 = TMLL + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #2327 = TMLH + { 2, &SystemZDescs.OperandInfo[764] }, // Inst #2326 = TMHL + { 2, &SystemZDescs.OperandInfo[764] }, // Inst #2325 = TMHH + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #2324 = TM + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #2323 = THDR + { 2, &SystemZDescs.OperandInfo[1109] }, // Inst #2322 = THDER + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #2321 = TEND + { 4, &SystemZDescs.OperandInfo[335] }, // Inst #2320 = TDGXT + { 4, &SystemZDescs.OperandInfo[643] }, // Inst #2319 = TDGET + { 4, &SystemZDescs.OperandInfo[615] }, // Inst #2318 = TDGDT + { 4, &SystemZDescs.OperandInfo[335] }, // Inst #2317 = TDCXT + { 4, &SystemZDescs.OperandInfo[643] }, // Inst #2316 = TDCET + { 4, &SystemZDescs.OperandInfo[615] }, // Inst #2315 = TDCDT + { 4, &SystemZDescs.OperandInfo[335] }, // Inst #2314 = TCXB + { 4, &SystemZDescs.OperandInfo[643] }, // Inst #2313 = TCEB + { 4, &SystemZDescs.OperandInfo[615] }, // Inst #2312 = TCDB + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #2311 = TBEGINC + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #2310 = TBEGIN + { 3, &SystemZDescs.OperandInfo[1413] }, // Inst #2309 = TBEDR + { 3, &SystemZDescs.OperandInfo[934] }, // Inst #2308 = TBDR + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #2307 = TB + { 2, &SystemZDescs.OperandInfo[1352] }, // Inst #2306 = TAR + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #2305 = TAM + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2304 = TABORT + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #2303 = SY + { 4, &SystemZDescs.OperandInfo[544] }, // Inst #2302 = SXTRA + { 3, &SystemZDescs.OperandInfo[541] }, // Inst #2301 = SXTR + { 3, &SystemZDescs.OperandInfo[538] }, // Inst #2300 = SXR + { 3, &SystemZDescs.OperandInfo[538] }, // Inst #2299 = SXBR + { 3, &SystemZDescs.OperandInfo[485] }, // Inst #2298 = SWR + { 5, &SystemZDescs.OperandInfo[480] }, // Inst #2297 = SW + { 1, &SystemZDescs.OperandInfo[1] }, // Inst #2296 = SVC + { 3, &SystemZDescs.OperandInfo[500] }, // Inst #2295 = SUR + { 5, &SystemZDescs.OperandInfo[495] }, // Inst #2294 = SU + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #2293 = STY + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #2292 = STURG + { 2, &SystemZDescs.OperandInfo[921] }, // Inst #2291 = STURA + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2290 = STSI + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2289 = STSCH + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #2288 = STRVH + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #2287 = STRVG + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #2286 = STRV + { 2, &SystemZDescs.OperandInfo[753] }, // Inst #2285 = STRL + { 4, &SystemZDescs.OperandInfo[1096] }, // Inst #2284 = STRAG + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2283 = STPX + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2282 = STPT + { 4, &SystemZDescs.OperandInfo[294] }, // Inst #2281 = STPQ + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #2280 = STOSM + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2279 = STOCGAsmZ + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2278 = STOCGAsmP + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2277 = STOCGAsmO + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2276 = STOCGAsmNZ + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2275 = STOCGAsmNP + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2274 = STOCGAsmNO + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2273 = STOCGAsmNM + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2272 = STOCGAsmNLH + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2271 = STOCGAsmNLE + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2270 = STOCGAsmNL + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2269 = STOCGAsmNHE + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2268 = STOCGAsmNH + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2267 = STOCGAsmNE + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2266 = STOCGAsmM + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2265 = STOCGAsmLH + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2264 = STOCGAsmLE + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2263 = STOCGAsmL + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2262 = STOCGAsmHE + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2261 = STOCGAsmH + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #2260 = STOCGAsmE + { 4, &SystemZDescs.OperandInfo[792] }, // Inst #2259 = STOCGAsm + { 5, &SystemZDescs.OperandInfo[1408] }, // Inst #2258 = STOCG + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2257 = STOCFHAsmZ + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2256 = STOCFHAsmP + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2255 = STOCFHAsmO + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2254 = STOCFHAsmNZ + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2253 = STOCFHAsmNP + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2252 = STOCFHAsmNO + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2251 = STOCFHAsmNM + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2250 = STOCFHAsmNLH + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2249 = STOCFHAsmNLE + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2248 = STOCFHAsmNL + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2247 = STOCFHAsmNHE + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2246 = STOCFHAsmNH + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2245 = STOCFHAsmNE + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2244 = STOCFHAsmM + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2243 = STOCFHAsmLH + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2242 = STOCFHAsmLE + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2241 = STOCFHAsmL + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2240 = STOCFHAsmHE + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2239 = STOCFHAsmH + { 3, &SystemZDescs.OperandInfo[1405] }, // Inst #2238 = STOCFHAsmE + { 4, &SystemZDescs.OperandInfo[1401] }, // Inst #2237 = STOCFHAsm + { 5, &SystemZDescs.OperandInfo[1396] }, // Inst #2236 = STOCFH + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2235 = STOCAsmZ + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2234 = STOCAsmP + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2233 = STOCAsmO + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2232 = STOCAsmNZ + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2231 = STOCAsmNP + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2230 = STOCAsmNO + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2229 = STOCAsmNM + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2228 = STOCAsmNLH + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2227 = STOCAsmNLE + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2226 = STOCAsmNL + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2225 = STOCAsmNHE + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2224 = STOCAsmNH + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2223 = STOCAsmNE + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2222 = STOCAsmM + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2221 = STOCAsmLH + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2220 = STOCAsmLE + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2219 = STOCAsmL + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2218 = STOCAsmHE + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2217 = STOCAsmH + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #2216 = STOCAsmE + { 4, &SystemZDescs.OperandInfo[825] }, // Inst #2215 = STOCAsm + { 5, &SystemZDescs.OperandInfo[1391] }, // Inst #2214 = STOC + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #2213 = STNSM + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #2212 = STMY + { 4, &SystemZDescs.OperandInfo[1130] }, // Inst #2211 = STMH + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #2210 = STMG + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #2209 = STM + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2208 = STIDP + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #2207 = STHY + { 2, &SystemZDescs.OperandInfo[753] }, // Inst #2206 = STHRL + { 4, &SystemZDescs.OperandInfo[745] }, // Inst #2205 = STHH + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #2204 = STH + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #2203 = STGSC + { 2, &SystemZDescs.OperandInfo[704] }, // Inst #2202 = STGRL + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #2201 = STG + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2200 = STFPC + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2199 = STFLE + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2198 = STFL + { 4, &SystemZDescs.OperandInfo[745] }, // Inst #2197 = STFH + { 4, &SystemZDescs.OperandInfo[643] }, // Inst #2196 = STEY + { 4, &SystemZDescs.OperandInfo[643] }, // Inst #2195 = STE + { 4, &SystemZDescs.OperandInfo[615] }, // Inst #2194 = STDY + { 4, &SystemZDescs.OperandInfo[615] }, // Inst #2193 = STD + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #2192 = STCY + { 4, &SystemZDescs.OperandInfo[1105] }, // Inst #2191 = STCTL + { 4, &SystemZDescs.OperandInfo[1105] }, // Inst #2190 = STCTG + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2189 = STCRW + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2188 = STCPS + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #2187 = STCMY + { 4, &SystemZDescs.OperandInfo[799] }, // Inst #2186 = STCMH + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #2185 = STCM + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2184 = STCKF + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2183 = STCKE + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2182 = STCKC + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2181 = STCK + { 4, &SystemZDescs.OperandInfo[745] }, // Inst #2180 = STCH + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #2179 = STC + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2178 = STBEAR + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2177 = STAP + { 4, &SystemZDescs.OperandInfo[1092] }, // Inst #2176 = STAMY + { 4, &SystemZDescs.OperandInfo[1092] }, // Inst #2175 = STAM + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #2174 = ST + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2173 = SSM + { 2, &SystemZDescs.OperandInfo[921] }, // Inst #2172 = SSKEOpt + { 3, &SystemZDescs.OperandInfo[1388] }, // Inst #2171 = SSKE + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2170 = SSCH + { 1, &SystemZDescs.OperandInfo[923] }, // Inst #2169 = SSAR + { 1, &SystemZDescs.OperandInfo[290] }, // Inst #2168 = SSAIR + { 5, &SystemZDescs.OperandInfo[1375] }, // Inst #2167 = SRXT + { 4, &SystemZDescs.OperandInfo[821] }, // Inst #2166 = SRSTU + { 4, &SystemZDescs.OperandInfo[821] }, // Inst #2165 = SRST + { 6, &SystemZDescs.OperandInfo[1382] }, // Inst #2164 = SRP + { 2, &SystemZDescs.OperandInfo[1380] }, // Inst #2163 = SRNMT + { 2, &SystemZDescs.OperandInfo[1380] }, // Inst #2162 = SRNMB + { 2, &SystemZDescs.OperandInfo[1380] }, // Inst #2161 = SRNM + { 4, &SystemZDescs.OperandInfo[1348] }, // Inst #2160 = SRLK + { 4, &SystemZDescs.OperandInfo[917] }, // Inst #2159 = SRLG + { 4, &SystemZDescs.OperandInfo[1367] }, // Inst #2158 = SRL + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2157 = SRK + { 5, &SystemZDescs.OperandInfo[144] }, // Inst #2156 = SRDT + { 4, &SystemZDescs.OperandInfo[1371] }, // Inst #2155 = SRDL + { 4, &SystemZDescs.OperandInfo[1371] }, // Inst #2154 = SRDA + { 4, &SystemZDescs.OperandInfo[1348] }, // Inst #2153 = SRAK + { 4, &SystemZDescs.OperandInfo[917] }, // Inst #2152 = SRAG + { 4, &SystemZDescs.OperandInfo[1367] }, // Inst #2151 = SRA + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #2150 = SR + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #2149 = SQXR + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #2148 = SQXBR + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #2147 = SQER + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #2146 = SQEBR + { 4, &SystemZDescs.OperandInfo[643] }, // Inst #2145 = SQEB + { 4, &SystemZDescs.OperandInfo[643] }, // Inst #2144 = SQE + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #2143 = SQDR + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #2142 = SQDBR + { 4, &SystemZDescs.OperandInfo[615] }, // Inst #2141 = SQDB + { 4, &SystemZDescs.OperandInfo[615] }, // Inst #2140 = SQD + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2139 = SPX + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2138 = SPT + { 1, &SystemZDescs.OperandInfo[923] }, // Inst #2137 = SPM + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2136 = SPKA + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #2135 = SPCTR + { 6, &SystemZDescs.OperandInfo[532] }, // Inst #2134 = SP + { 4, &SystemZDescs.OperandInfo[782] }, // Inst #2133 = SORTL + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #2132 = SLY + { 5, &SystemZDescs.OperandInfo[1375] }, // Inst #2131 = SLXT + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2130 = SLRK + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #2129 = SLR + { 4, &SystemZDescs.OperandInfo[1348] }, // Inst #2128 = SLLK + { 4, &SystemZDescs.OperandInfo[917] }, // Inst #2127 = SLLG + { 4, &SystemZDescs.OperandInfo[1367] }, // Inst #2126 = SLL + { 3, &SystemZDescs.OperandInfo[520] }, // Inst #2125 = SLHHLR + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2124 = SLHHHR + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2123 = SLGRK + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #2122 = SLGR + { 3, &SystemZDescs.OperandInfo[511] }, // Inst #2121 = SLGFR + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #2120 = SLGFI + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #2119 = SLGF + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #2118 = SLG + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #2117 = SLFI + { 5, &SystemZDescs.OperandInfo[144] }, // Inst #2116 = SLDT + { 4, &SystemZDescs.OperandInfo[1371] }, // Inst #2115 = SLDL + { 4, &SystemZDescs.OperandInfo[1371] }, // Inst #2114 = SLDA + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #2113 = SLBR + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #2112 = SLBGR + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #2111 = SLBG + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #2110 = SLB + { 4, &SystemZDescs.OperandInfo[1348] }, // Inst #2109 = SLAK + { 4, &SystemZDescs.OperandInfo[917] }, // Inst #2108 = SLAG + { 4, &SystemZDescs.OperandInfo[1367] }, // Inst #2107 = SLA + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #2106 = SL + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #2105 = SIGP + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2104 = SIGA + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2103 = SIE + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #2102 = SHY + { 3, &SystemZDescs.OperandInfo[520] }, // Inst #2101 = SHHLR + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2100 = SHHHR + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #2099 = SH + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2098 = SGRK + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #2097 = SGR + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #2096 = SGH + { 3, &SystemZDescs.OperandInfo[511] }, // Inst #2095 = SGFR + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #2094 = SGF + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #2093 = SG + { 1, &SystemZDescs.OperandInfo[923] }, // Inst #2092 = SFPC + { 1, &SystemZDescs.OperandInfo[923] }, // Inst #2091 = SFASR + { 3, &SystemZDescs.OperandInfo[500] }, // Inst #2090 = SER + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2089 = SELRAsmZ + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2088 = SELRAsmP + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2087 = SELRAsmO + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2086 = SELRAsmNZ + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2085 = SELRAsmNP + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2084 = SELRAsmNO + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2083 = SELRAsmNM + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2082 = SELRAsmNLH + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2081 = SELRAsmNLE + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2080 = SELRAsmNL + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2079 = SELRAsmNHE + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2078 = SELRAsmNH + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2077 = SELRAsmNE + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2076 = SELRAsmM + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2075 = SELRAsmLH + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2074 = SELRAsmLE + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2073 = SELRAsmL + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2072 = SELRAsmHE + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2071 = SELRAsmH + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #2070 = SELRAsmE + { 4, &SystemZDescs.OperandInfo[1363] }, // Inst #2069 = SELRAsm + { 5, &SystemZDescs.OperandInfo[420] }, // Inst #2068 = SELR + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2067 = SELGRAsmZ + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2066 = SELGRAsmP + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2065 = SELGRAsmO + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2064 = SELGRAsmNZ + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2063 = SELGRAsmNP + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2062 = SELGRAsmNO + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2061 = SELGRAsmNM + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2060 = SELGRAsmNLH + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2059 = SELGRAsmNLE + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2058 = SELGRAsmNL + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2057 = SELGRAsmNHE + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2056 = SELGRAsmNH + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2055 = SELGRAsmNE + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2054 = SELGRAsmM + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2053 = SELGRAsmLH + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2052 = SELGRAsmLE + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2051 = SELGRAsmL + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2050 = SELGRAsmHE + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2049 = SELGRAsmH + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #2048 = SELGRAsmE + { 4, &SystemZDescs.OperandInfo[965] }, // Inst #2047 = SELGRAsm + { 5, &SystemZDescs.OperandInfo[425] }, // Inst #2046 = SELGR + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2045 = SELFHRAsmZ + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2044 = SELFHRAsmP + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2043 = SELFHRAsmO + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2042 = SELFHRAsmNZ + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2041 = SELFHRAsmNP + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2040 = SELFHRAsmNO + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2039 = SELFHRAsmNM + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2038 = SELFHRAsmNLH + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2037 = SELFHRAsmNLE + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2036 = SELFHRAsmNL + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2035 = SELFHRAsmNHE + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2034 = SELFHRAsmNH + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2033 = SELFHRAsmNE + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2032 = SELFHRAsmM + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2031 = SELFHRAsmLH + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2030 = SELFHRAsmLE + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2029 = SELFHRAsmL + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2028 = SELFHRAsmHE + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2027 = SELFHRAsmH + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #2026 = SELFHRAsmE + { 4, &SystemZDescs.OperandInfo[1359] }, // Inst #2025 = SELFHRAsm + { 5, &SystemZDescs.OperandInfo[1354] }, // Inst #2024 = SELFHR + { 3, &SystemZDescs.OperandInfo[500] }, // Inst #2023 = SEBR + { 5, &SystemZDescs.OperandInfo[495] }, // Inst #2022 = SEB + { 5, &SystemZDescs.OperandInfo[495] }, // Inst #2021 = SE + { 4, &SystemZDescs.OperandInfo[491] }, // Inst #2020 = SDTRA + { 3, &SystemZDescs.OperandInfo[488] }, // Inst #2019 = SDTR + { 3, &SystemZDescs.OperandInfo[485] }, // Inst #2018 = SDR + { 3, &SystemZDescs.OperandInfo[485] }, // Inst #2017 = SDBR + { 5, &SystemZDescs.OperandInfo[480] }, // Inst #2016 = SDB + { 5, &SystemZDescs.OperandInfo[480] }, // Inst #2015 = SD + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #2014 = SCKPF + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2013 = SCKC + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2012 = SCK + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #2011 = SCHM + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #2010 = SCCTR + { 2, &SystemZDescs.OperandInfo[1352] }, // Inst #2009 = SAR + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #2008 = SAM64 + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #2007 = SAM31 + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #2006 = SAM24 + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #2005 = SAL + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2004 = SACF + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #2003 = SAC + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #2002 = S + { 6, &SystemZDescs.OperandInfo[1330] }, // Inst #2001 = RXSBG + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #2000 = RSCH + { 5, &SystemZDescs.OperandInfo[1325] }, // Inst #1999 = RRXTR + { 5, &SystemZDescs.OperandInfo[902] }, // Inst #1998 = RRDTR + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1997 = RRBM + { 2, &SystemZDescs.OperandInfo[921] }, // Inst #1996 = RRBE + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #1995 = RP + { 6, &SystemZDescs.OperandInfo[1330] }, // Inst #1994 = ROSBG + { 6, &SystemZDescs.OperandInfo[1330] }, // Inst #1993 = RNSBG + { 4, &SystemZDescs.OperandInfo[917] }, // Inst #1992 = RLLG + { 4, &SystemZDescs.OperandInfo[1348] }, // Inst #1991 = RLL + { 6, &SystemZDescs.OperandInfo[1342] }, // Inst #1990 = RISBLG + { 6, &SystemZDescs.OperandInfo[1336] }, // Inst #1989 = RISBHG + { 6, &SystemZDescs.OperandInfo[1330] }, // Inst #1988 = RISBGN + { 6, &SystemZDescs.OperandInfo[391] }, // Inst #1987 = RISBG32 + { 6, &SystemZDescs.OperandInfo[1330] }, // Inst #1986 = RISBG + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #1985 = RDPOpt + { 4, &SystemZDescs.OperandInfo[965] }, // Inst #1984 = RDP + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #1983 = RCHP + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #1982 = QSI + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #1981 = QPACI + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #1980 = QCTRI + { 5, &SystemZDescs.OperandInfo[1325] }, // Inst #1979 = QAXTR + { 5, &SystemZDescs.OperandInfo[902] }, // Inst #1978 = QADTR + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #1977 = PTLB + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1976 = PTI + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #1975 = PTFF + { 2, &SystemZDescs.OperandInfo[1323] }, // Inst #1974 = PTF + { 2, &SystemZDescs.OperandInfo[921] }, // Inst #1973 = PT + { 4, &SystemZDescs.OperandInfo[782] }, // Inst #1972 = PRNO + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #1971 = PR + { 4, &SystemZDescs.OperandInfo[782] }, // Inst #1970 = PPNO + { 3, &SystemZDescs.OperandInfo[211] }, // Inst #1969 = PPA + { 3, &SystemZDescs.OperandInfo[211] }, // Inst #1968 = POPCNTOpt + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1967 = POPCNT + { 6, &SystemZDescs.OperandInfo[1317] }, // Inst #1966 = PLO + { 5, &SystemZDescs.OperandInfo[1312] }, // Inst #1965 = PKU + { 5, &SystemZDescs.OperandInfo[1312] }, // Inst #1964 = PKA + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1963 = PGOUT + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1962 = PGIN + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #1961 = PFPO + { 3, &SystemZDescs.OperandInfo[1309] }, // Inst #1960 = PFMF + { 2, &SystemZDescs.OperandInfo[582] }, // Inst #1959 = PFDRL + { 4, &SystemZDescs.OperandInfo[560] }, // Inst #1958 = PFD + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #1957 = PCKMO + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #1956 = PCC + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #1955 = PC + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #1954 = PALB + { 6, &SystemZDescs.OperandInfo[532] }, // Inst #1953 = PACK + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #1952 = OY + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #1951 = ORK + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1950 = OR + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #1949 = OIY + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1948 = OILL + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1947 = OILH + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1946 = OILF + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1945 = OIHL + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1944 = OIHH + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1943 = OIHF + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #1942 = OI + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #1941 = OGRK + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1940 = OGR + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #1939 = OG + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #1938 = OCRK + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #1937 = OCGRK + { 5, &SystemZDescs.OperandInfo[777] }, // Inst #1936 = OC + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #1935 = O + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #1934 = NY + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #1933 = NXRK + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #1932 = NXGRK + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1931 = NTSTG + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #1930 = NRK + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1929 = NR + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #1928 = NORK + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #1927 = NOP_bare + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #1926 = NOGRK + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #1925 = NNRK + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #1924 = NNPA + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #1923 = NNGRK + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #1922 = NIY + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1921 = NILL + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1920 = NILH + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1919 = NILF + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1918 = NIHL + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1917 = NIHH + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1916 = NIHF + { 2, &SystemZDescs.OperandInfo[21] }, // Inst #1915 = NIAI + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #1914 = NI + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #1913 = NGRK + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1912 = NGR + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #1911 = NG + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #1910 = NCRK + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #1909 = NCGRK + { 5, &SystemZDescs.OperandInfo[777] }, // Inst #1908 = NC + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #1907 = N + { 3, &SystemZDescs.OperandInfo[1306] }, // Inst #1906 = MYR + { 3, &SystemZDescs.OperandInfo[488] }, // Inst #1905 = MYLR + { 5, &SystemZDescs.OperandInfo[144] }, // Inst #1904 = MYL + { 3, &SystemZDescs.OperandInfo[488] }, // Inst #1903 = MYHR + { 5, &SystemZDescs.OperandInfo[144] }, // Inst #1902 = MYH + { 5, &SystemZDescs.OperandInfo[1301] }, // Inst #1901 = MY + { 4, &SystemZDescs.OperandInfo[544] }, // Inst #1900 = MXTRA + { 3, &SystemZDescs.OperandInfo[541] }, // Inst #1899 = MXTR + { 3, &SystemZDescs.OperandInfo[538] }, // Inst #1898 = MXR + { 3, &SystemZDescs.OperandInfo[1298] }, // Inst #1897 = MXDR + { 3, &SystemZDescs.OperandInfo[1298] }, // Inst #1896 = MXDBR + { 5, &SystemZDescs.OperandInfo[1293] }, // Inst #1895 = MXDB + { 5, &SystemZDescs.OperandInfo[1293] }, // Inst #1894 = MXD + { 3, &SystemZDescs.OperandInfo[538] }, // Inst #1893 = MXBR + { 5, &SystemZDescs.OperandInfo[777] }, // Inst #1892 = MVZ + { 4, &SystemZDescs.OperandInfo[821] }, // Inst #1891 = MVST + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1890 = MVPG + { 6, &SystemZDescs.OperandInfo[532] }, // Inst #1889 = MVO + { 5, &SystemZDescs.OperandInfo[777] }, // Inst #1888 = MVN + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #1887 = MVIY + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #1886 = MVI + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #1885 = MVHI + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #1884 = MVHHI + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #1883 = MVGHI + { 4, &SystemZDescs.OperandInfo[1096] }, // Inst #1882 = MVCSK + { 6, &SystemZDescs.OperandInfo[1287] }, // Inst #1881 = MVCS + { 4, &SystemZDescs.OperandInfo[1096] }, // Inst #1880 = MVCRL + { 6, &SystemZDescs.OperandInfo[1287] }, // Inst #1879 = MVCP + { 5, &SystemZDescs.OperandInfo[861] }, // Inst #1878 = MVCOS + { 6, &SystemZDescs.OperandInfo[786] }, // Inst #1877 = MVCLU + { 6, &SystemZDescs.OperandInfo[786] }, // Inst #1876 = MVCLE + { 4, &SystemZDescs.OperandInfo[782] }, // Inst #1875 = MVCL + { 6, &SystemZDescs.OperandInfo[1287] }, // Inst #1874 = MVCK + { 5, &SystemZDescs.OperandInfo[777] }, // Inst #1873 = MVCIN + { 4, &SystemZDescs.OperandInfo[1096] }, // Inst #1872 = MVCDK + { 5, &SystemZDescs.OperandInfo[777] }, // Inst #1871 = MVC + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #1870 = MSY + { 1, &SystemZDescs.OperandInfo[1286] }, // Inst #1869 = MSTA + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #1868 = MSRKC + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1867 = MSR + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #1866 = MSGRKC + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1865 = MSGR + { 3, &SystemZDescs.OperandInfo[511] }, // Inst #1864 = MSGFR + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1863 = MSGFI + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #1862 = MSGF + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #1861 = MSGC + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #1860 = MSG + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1859 = MSFI + { 4, &SystemZDescs.OperandInfo[1269] }, // Inst #1858 = MSER + { 4, &SystemZDescs.OperandInfo[1269] }, // Inst #1857 = MSEBR + { 6, &SystemZDescs.OperandInfo[1263] }, // Inst #1856 = MSEB + { 6, &SystemZDescs.OperandInfo[1263] }, // Inst #1855 = MSE + { 4, &SystemZDescs.OperandInfo[1259] }, // Inst #1854 = MSDR + { 4, &SystemZDescs.OperandInfo[1259] }, // Inst #1853 = MSDBR + { 6, &SystemZDescs.OperandInfo[1253] }, // Inst #1852 = MSDB + { 6, &SystemZDescs.OperandInfo[1253] }, // Inst #1851 = MSD + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #1850 = MSCH + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #1849 = MSC + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #1848 = MS + { 3, &SystemZDescs.OperandInfo[912] }, // Inst #1847 = MR + { 6, &SystemZDescs.OperandInfo[532] }, // Inst #1846 = MP + { 3, &SystemZDescs.OperandInfo[912] }, // Inst #1845 = MLR + { 3, &SystemZDescs.OperandInfo[858] }, // Inst #1844 = MLGR + { 5, &SystemZDescs.OperandInfo[892] }, // Inst #1843 = MLG + { 5, &SystemZDescs.OperandInfo[892] }, // Inst #1842 = ML + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #1841 = MHY + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1840 = MHI + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #1839 = MH + { 3, &SystemZDescs.OperandInfo[367] }, // Inst #1838 = MGRK + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1837 = MGHI + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #1836 = MGH + { 5, &SystemZDescs.OperandInfo[892] }, // Inst #1835 = MG + { 5, &SystemZDescs.OperandInfo[892] }, // Inst #1834 = MFY + { 3, &SystemZDescs.OperandInfo[1283] }, // Inst #1833 = MER + { 3, &SystemZDescs.OperandInfo[500] }, // Inst #1832 = MEER + { 3, &SystemZDescs.OperandInfo[500] }, // Inst #1831 = MEEBR + { 5, &SystemZDescs.OperandInfo[495] }, // Inst #1830 = MEEB + { 5, &SystemZDescs.OperandInfo[495] }, // Inst #1829 = MEE + { 5, &SystemZDescs.OperandInfo[480] }, // Inst #1828 = ME + { 4, &SystemZDescs.OperandInfo[491] }, // Inst #1827 = MDTRA + { 3, &SystemZDescs.OperandInfo[488] }, // Inst #1826 = MDTR + { 3, &SystemZDescs.OperandInfo[485] }, // Inst #1825 = MDR + { 3, &SystemZDescs.OperandInfo[1283] }, // Inst #1824 = MDER + { 3, &SystemZDescs.OperandInfo[1283] }, // Inst #1823 = MDEBR + { 5, &SystemZDescs.OperandInfo[480] }, // Inst #1822 = MDEB + { 5, &SystemZDescs.OperandInfo[480] }, // Inst #1821 = MDE + { 3, &SystemZDescs.OperandInfo[485] }, // Inst #1820 = MDBR + { 5, &SystemZDescs.OperandInfo[480] }, // Inst #1819 = MDB + { 5, &SystemZDescs.OperandInfo[480] }, // Inst #1818 = MD + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #1817 = MC + { 4, &SystemZDescs.OperandInfo[1279] }, // Inst #1816 = MAYR + { 4, &SystemZDescs.OperandInfo[1259] }, // Inst #1815 = MAYLR + { 6, &SystemZDescs.OperandInfo[1253] }, // Inst #1814 = MAYL + { 4, &SystemZDescs.OperandInfo[1259] }, // Inst #1813 = MAYHR + { 6, &SystemZDescs.OperandInfo[1253] }, // Inst #1812 = MAYH + { 6, &SystemZDescs.OperandInfo[1273] }, // Inst #1811 = MAY + { 4, &SystemZDescs.OperandInfo[1269] }, // Inst #1810 = MAER + { 4, &SystemZDescs.OperandInfo[1269] }, // Inst #1809 = MAEBR + { 6, &SystemZDescs.OperandInfo[1263] }, // Inst #1808 = MAEB + { 6, &SystemZDescs.OperandInfo[1263] }, // Inst #1807 = MAE + { 4, &SystemZDescs.OperandInfo[1259] }, // Inst #1806 = MADR + { 4, &SystemZDescs.OperandInfo[1259] }, // Inst #1805 = MADBR + { 6, &SystemZDescs.OperandInfo[1253] }, // Inst #1804 = MADB + { 6, &SystemZDescs.OperandInfo[1253] }, // Inst #1803 = MAD + { 5, &SystemZDescs.OperandInfo[892] }, // Inst #1802 = M + { 1, &SystemZDescs.OperandInfo[334] }, // Inst #1801 = LZXR + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1800 = LZRG + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #1799 = LZRF + { 1, &SystemZDescs.OperandInfo[333] }, // Inst #1798 = LZER + { 1, &SystemZDescs.OperandInfo[332] }, // Inst #1797 = LZDR + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #1796 = LY + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1795 = LXR + { 2, &SystemZDescs.OperandInfo[1251] }, // Inst #1794 = LXER + { 2, &SystemZDescs.OperandInfo[1251] }, // Inst #1793 = LXEBR + { 4, &SystemZDescs.OperandInfo[335] }, // Inst #1792 = LXEB + { 4, &SystemZDescs.OperandInfo[335] }, // Inst #1791 = LXE + { 3, &SystemZDescs.OperandInfo[1248] }, // Inst #1790 = LXDTR + { 2, &SystemZDescs.OperandInfo[1246] }, // Inst #1789 = LXDR + { 2, &SystemZDescs.OperandInfo[1246] }, // Inst #1788 = LXDBR + { 4, &SystemZDescs.OperandInfo[335] }, // Inst #1787 = LXDB + { 4, &SystemZDescs.OperandInfo[335] }, // Inst #1786 = LXD + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1785 = LURAG + { 2, &SystemZDescs.OperandInfo[921] }, // Inst #1784 = LURA + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1783 = LTXTR + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1782 = LTXR + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1781 = LTXBR + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1780 = LTR + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1779 = LTGR + { 2, &SystemZDescs.OperandInfo[702] }, // Inst #1778 = LTGFR + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1777 = LTGF + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1776 = LTG + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #1775 = LTER + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #1774 = LTEBR + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #1773 = LTDTR + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #1772 = LTDR + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #1771 = LTDBR + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #1770 = LT + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #1769 = LSCTL + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1768 = LRVR + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #1767 = LRVH + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1766 = LRVGR + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1765 = LRVG + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #1764 = LRV + { 2, &SystemZDescs.OperandInfo[753] }, // Inst #1763 = LRL + { 2, &SystemZDescs.OperandInfo[1116] }, // Inst #1762 = LRER + { 2, &SystemZDescs.OperandInfo[1114] }, // Inst #1761 = LRDR + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1760 = LRAY + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1759 = LRAG + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1758 = LRA + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1757 = LR + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1756 = LPXR + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1755 = LPXBR + { 5, &SystemZDescs.OperandInfo[1241] }, // Inst #1754 = LPTEA + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #1753 = LPSWEY + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #1752 = LPSWE + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #1751 = LPSW + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1750 = LPR + { 4, &SystemZDescs.OperandInfo[294] }, // Inst #1749 = LPQ + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #1748 = LPP + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1747 = LPGR + { 2, &SystemZDescs.OperandInfo[702] }, // Inst #1746 = LPGFR + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #1745 = LPER + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #1744 = LPEBR + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #1743 = LPDR + { 5, &SystemZDescs.OperandInfo[1236] }, // Inst #1742 = LPDG + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #1741 = LPDFR_32 + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #1740 = LPDFR + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #1739 = LPDBR + { 5, &SystemZDescs.OperandInfo[1236] }, // Inst #1738 = LPD + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #1737 = LPCTL + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1736 = LOCRAsmZ + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1735 = LOCRAsmP + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1734 = LOCRAsmO + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1733 = LOCRAsmNZ + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1732 = LOCRAsmNP + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1731 = LOCRAsmNO + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1730 = LOCRAsmNM + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1729 = LOCRAsmNLH + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1728 = LOCRAsmNLE + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1727 = LOCRAsmNL + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1726 = LOCRAsmNHE + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1725 = LOCRAsmNH + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1724 = LOCRAsmNE + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1723 = LOCRAsmM + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1722 = LOCRAsmLH + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1721 = LOCRAsmLE + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1720 = LOCRAsmL + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1719 = LOCRAsmHE + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1718 = LOCRAsmH + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #1717 = LOCRAsmE + { 4, &SystemZDescs.OperandInfo[1232] }, // Inst #1716 = LOCRAsm + { 5, &SystemZDescs.OperandInfo[1227] }, // Inst #1715 = LOCR + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1714 = LOCHIAsmZ + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1713 = LOCHIAsmP + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1712 = LOCHIAsmO + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1711 = LOCHIAsmNZ + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1710 = LOCHIAsmNP + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1709 = LOCHIAsmNO + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1708 = LOCHIAsmNM + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1707 = LOCHIAsmNLH + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1706 = LOCHIAsmNLE + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1705 = LOCHIAsmNL + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1704 = LOCHIAsmNHE + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1703 = LOCHIAsmNH + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1702 = LOCHIAsmNE + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1701 = LOCHIAsmM + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1700 = LOCHIAsmLH + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1699 = LOCHIAsmLE + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1698 = LOCHIAsmL + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1697 = LOCHIAsmHE + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1696 = LOCHIAsmH + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1695 = LOCHIAsmE + { 4, &SystemZDescs.OperandInfo[1223] }, // Inst #1694 = LOCHIAsm + { 5, &SystemZDescs.OperandInfo[1218] }, // Inst #1693 = LOCHI + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1692 = LOCHHIAsmZ + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1691 = LOCHHIAsmP + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1690 = LOCHHIAsmO + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1689 = LOCHHIAsmNZ + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1688 = LOCHHIAsmNP + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1687 = LOCHHIAsmNO + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1686 = LOCHHIAsmNM + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1685 = LOCHHIAsmNLH + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1684 = LOCHHIAsmNLE + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1683 = LOCHHIAsmNL + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1682 = LOCHHIAsmNHE + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1681 = LOCHHIAsmNH + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1680 = LOCHHIAsmNE + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1679 = LOCHHIAsmM + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1678 = LOCHHIAsmLH + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1677 = LOCHHIAsmLE + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1676 = LOCHHIAsmL + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1675 = LOCHHIAsmHE + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1674 = LOCHHIAsmH + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1673 = LOCHHIAsmE + { 4, &SystemZDescs.OperandInfo[1214] }, // Inst #1672 = LOCHHIAsm + { 5, &SystemZDescs.OperandInfo[1209] }, // Inst #1671 = LOCHHI + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1670 = LOCGRAsmZ + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1669 = LOCGRAsmP + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1668 = LOCGRAsmO + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1667 = LOCGRAsmNZ + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1666 = LOCGRAsmNP + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1665 = LOCGRAsmNO + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1664 = LOCGRAsmNM + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1663 = LOCGRAsmNLH + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1662 = LOCGRAsmNLE + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1661 = LOCGRAsmNL + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1660 = LOCGRAsmNHE + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1659 = LOCGRAsmNH + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1658 = LOCGRAsmNE + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1657 = LOCGRAsmM + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1656 = LOCGRAsmLH + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1655 = LOCGRAsmLE + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1654 = LOCGRAsmL + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1653 = LOCGRAsmHE + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1652 = LOCGRAsmH + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #1651 = LOCGRAsmE + { 4, &SystemZDescs.OperandInfo[1205] }, // Inst #1650 = LOCGRAsm + { 5, &SystemZDescs.OperandInfo[1200] }, // Inst #1649 = LOCGR + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1648 = LOCGHIAsmZ + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1647 = LOCGHIAsmP + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1646 = LOCGHIAsmO + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1645 = LOCGHIAsmNZ + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1644 = LOCGHIAsmNP + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1643 = LOCGHIAsmNO + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1642 = LOCGHIAsmNM + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1641 = LOCGHIAsmNLH + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1640 = LOCGHIAsmNLE + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1639 = LOCGHIAsmNL + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1638 = LOCGHIAsmNHE + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1637 = LOCGHIAsmNH + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1636 = LOCGHIAsmNE + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1635 = LOCGHIAsmM + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1634 = LOCGHIAsmLH + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1633 = LOCGHIAsmLE + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1632 = LOCGHIAsmL + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1631 = LOCGHIAsmHE + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1630 = LOCGHIAsmH + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #1629 = LOCGHIAsmE + { 4, &SystemZDescs.OperandInfo[1196] }, // Inst #1628 = LOCGHIAsm + { 5, &SystemZDescs.OperandInfo[1191] }, // Inst #1627 = LOCGHI + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1626 = LOCGAsmZ + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1625 = LOCGAsmP + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1624 = LOCGAsmO + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1623 = LOCGAsmNZ + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1622 = LOCGAsmNP + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1621 = LOCGAsmNO + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1620 = LOCGAsmNM + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1619 = LOCGAsmNLH + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1618 = LOCGAsmNLE + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1617 = LOCGAsmNL + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1616 = LOCGAsmNHE + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1615 = LOCGAsmNH + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1614 = LOCGAsmNE + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1613 = LOCGAsmM + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1612 = LOCGAsmLH + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1611 = LOCGAsmLE + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1610 = LOCGAsmL + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1609 = LOCGAsmHE + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1608 = LOCGAsmH + { 4, &SystemZDescs.OperandInfo[1187] }, // Inst #1607 = LOCGAsmE + { 5, &SystemZDescs.OperandInfo[1182] }, // Inst #1606 = LOCGAsm + { 6, &SystemZDescs.OperandInfo[1176] }, // Inst #1605 = LOCG + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1604 = LOCFHRAsmZ + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1603 = LOCFHRAsmP + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1602 = LOCFHRAsmO + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1601 = LOCFHRAsmNZ + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1600 = LOCFHRAsmNP + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1599 = LOCFHRAsmNO + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1598 = LOCFHRAsmNM + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1597 = LOCFHRAsmNLH + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1596 = LOCFHRAsmNLE + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1595 = LOCFHRAsmNL + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1594 = LOCFHRAsmNHE + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1593 = LOCFHRAsmNH + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1592 = LOCFHRAsmNE + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1591 = LOCFHRAsmM + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1590 = LOCFHRAsmLH + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1589 = LOCFHRAsmLE + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1588 = LOCFHRAsmL + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1587 = LOCFHRAsmHE + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1586 = LOCFHRAsmH + { 3, &SystemZDescs.OperandInfo[1173] }, // Inst #1585 = LOCFHRAsmE + { 4, &SystemZDescs.OperandInfo[1169] }, // Inst #1584 = LOCFHRAsm + { 5, &SystemZDescs.OperandInfo[1164] }, // Inst #1583 = LOCFHR + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1582 = LOCFHAsmZ + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1581 = LOCFHAsmP + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1580 = LOCFHAsmO + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1579 = LOCFHAsmNZ + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1578 = LOCFHAsmNP + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1577 = LOCFHAsmNO + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1576 = LOCFHAsmNM + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1575 = LOCFHAsmNLH + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1574 = LOCFHAsmNLE + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1573 = LOCFHAsmNL + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1572 = LOCFHAsmNHE + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1571 = LOCFHAsmNH + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1570 = LOCFHAsmNE + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1569 = LOCFHAsmM + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1568 = LOCFHAsmLH + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1567 = LOCFHAsmLE + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1566 = LOCFHAsmL + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1565 = LOCFHAsmHE + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1564 = LOCFHAsmH + { 4, &SystemZDescs.OperandInfo[1160] }, // Inst #1563 = LOCFHAsmE + { 5, &SystemZDescs.OperandInfo[1155] }, // Inst #1562 = LOCFHAsm + { 6, &SystemZDescs.OperandInfo[1149] }, // Inst #1561 = LOCFH + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1560 = LOCAsmZ + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1559 = LOCAsmP + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1558 = LOCAsmO + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1557 = LOCAsmNZ + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1556 = LOCAsmNP + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1555 = LOCAsmNO + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1554 = LOCAsmNM + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1553 = LOCAsmNLH + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1552 = LOCAsmNLE + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1551 = LOCAsmNL + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1550 = LOCAsmNHE + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1549 = LOCAsmNH + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1548 = LOCAsmNE + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1547 = LOCAsmM + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1546 = LOCAsmLH + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1545 = LOCAsmLE + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1544 = LOCAsmL + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1543 = LOCAsmHE + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1542 = LOCAsmH + { 4, &SystemZDescs.OperandInfo[1145] }, // Inst #1541 = LOCAsmE + { 5, &SystemZDescs.OperandInfo[1140] }, // Inst #1540 = LOCAsm + { 6, &SystemZDescs.OperandInfo[1134] }, // Inst #1539 = LOC + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1538 = LNXR + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1537 = LNXBR + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1536 = LNR + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1535 = LNGR + { 2, &SystemZDescs.OperandInfo[702] }, // Inst #1534 = LNGFR + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #1533 = LNER + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #1532 = LNEBR + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #1531 = LNDR + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #1530 = LNDFR_32 + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #1529 = LNDFR + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #1528 = LNDBR + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1527 = LMY + { 4, &SystemZDescs.OperandInfo[1130] }, // Inst #1526 = LMH + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #1525 = LMG + { 6, &SystemZDescs.OperandInfo[1124] }, // Inst #1524 = LMD + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1523 = LM + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1522 = LLZRGF + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #1521 = LLILL + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #1520 = LLILH + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #1519 = LLILF + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #1518 = LLIHL + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #1517 = LLIHH + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #1516 = LLIHF + { 2, &SystemZDescs.OperandInfo[753] }, // Inst #1515 = LLHRL + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1514 = LLHR + { 4, &SystemZDescs.OperandInfo[745] }, // Inst #1513 = LLHH + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #1512 = LLH + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1511 = LLGTR + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1510 = LLGTAT + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1509 = LLGT + { 2, &SystemZDescs.OperandInfo[704] }, // Inst #1508 = LLGHRL + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1507 = LLGHR + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1506 = LLGH + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1505 = LLGFSG + { 2, &SystemZDescs.OperandInfo[704] }, // Inst #1504 = LLGFRL + { 2, &SystemZDescs.OperandInfo[702] }, // Inst #1503 = LLGFR + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1502 = LLGFAT + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1501 = LLGF + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1500 = LLGCR + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1499 = LLGC + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1498 = LLCR + { 4, &SystemZDescs.OperandInfo[745] }, // Inst #1497 = LLCH + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #1496 = LLC + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #1495 = LHY + { 2, &SystemZDescs.OperandInfo[753] }, // Inst #1494 = LHRL + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1493 = LHR + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #1492 = LHI + { 4, &SystemZDescs.OperandInfo[745] }, // Inst #1491 = LHH + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #1490 = LH + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1489 = LGSC + { 2, &SystemZDescs.OperandInfo[704] }, // Inst #1488 = LGRL + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1487 = LGR + { 2, &SystemZDescs.OperandInfo[704] }, // Inst #1486 = LGHRL + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1485 = LGHR + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #1484 = LGHI + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1483 = LGH + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1482 = LGG + { 2, &SystemZDescs.OperandInfo[704] }, // Inst #1481 = LGFRL + { 2, &SystemZDescs.OperandInfo[702] }, // Inst #1480 = LGFR + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #1479 = LGFI + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1478 = LGF + { 2, &SystemZDescs.OperandInfo[874] }, // Inst #1477 = LGDR + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1476 = LGBR + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1475 = LGB + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1474 = LGAT + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1473 = LG + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #1472 = LFPC + { 4, &SystemZDescs.OperandInfo[745] }, // Inst #1471 = LFHAT + { 4, &SystemZDescs.OperandInfo[745] }, // Inst #1470 = LFH + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #1469 = LFAS + { 4, &SystemZDescs.OperandInfo[643] }, // Inst #1468 = LEY + { 2, &SystemZDescs.OperandInfo[1122] }, // Inst #1467 = LEXR + { 4, &SystemZDescs.OperandInfo[951] }, // Inst #1466 = LEXBRA + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1465 = LEXBR + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #1464 = LER + { 4, &SystemZDescs.OperandInfo[1118] }, // Inst #1463 = LEDTR + { 2, &SystemZDescs.OperandInfo[1116] }, // Inst #1462 = LEDR + { 4, &SystemZDescs.OperandInfo[1118] }, // Inst #1461 = LEDBRA + { 2, &SystemZDescs.OperandInfo[1116] }, // Inst #1460 = LEDBR + { 4, &SystemZDescs.OperandInfo[643] }, // Inst #1459 = LE + { 4, &SystemZDescs.OperandInfo[615] }, // Inst #1458 = LDY + { 4, &SystemZDescs.OperandInfo[951] }, // Inst #1457 = LDXTR + { 2, &SystemZDescs.OperandInfo[1114] }, // Inst #1456 = LDXR + { 4, &SystemZDescs.OperandInfo[951] }, // Inst #1455 = LDXBRA + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1454 = LDXBR + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #1453 = LDR32 + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #1452 = LDR + { 2, &SystemZDescs.OperandInfo[627] }, // Inst #1451 = LDGR + { 3, &SystemZDescs.OperandInfo[1111] }, // Inst #1450 = LDETR + { 2, &SystemZDescs.OperandInfo[1109] }, // Inst #1449 = LDER + { 2, &SystemZDescs.OperandInfo[1109] }, // Inst #1448 = LDEBR + { 4, &SystemZDescs.OperandInfo[615] }, // Inst #1447 = LDEB + { 4, &SystemZDescs.OperandInfo[643] }, // Inst #1446 = LDE32 + { 4, &SystemZDescs.OperandInfo[615] }, // Inst #1445 = LDE + { 4, &SystemZDescs.OperandInfo[615] }, // Inst #1444 = LD + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1443 = LCXR + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1442 = LCXBR + { 4, &SystemZDescs.OperandInfo[1105] }, // Inst #1441 = LCTLG + { 4, &SystemZDescs.OperandInfo[1105] }, // Inst #1440 = LCTL + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1439 = LCR + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1438 = LCGR + { 2, &SystemZDescs.OperandInfo[702] }, // Inst #1437 = LCGFR + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #1436 = LCER + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #1435 = LCEBR + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #1434 = LCDR + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #1433 = LCDFR_32 + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #1432 = LCDFR + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #1431 = LCDBR + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #1430 = LCCTL + { 5, &SystemZDescs.OperandInfo[1100] }, // Inst #1429 = LCBB + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1428 = LBR + { 4, &SystemZDescs.OperandInfo[745] }, // Inst #1427 = LBH + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #1426 = LBEAR + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #1425 = LB + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1424 = LAY + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #1423 = LAXG + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1422 = LAX + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #1421 = LAT + { 4, &SystemZDescs.OperandInfo[1096] }, // Inst #1420 = LASP + { 2, &SystemZDescs.OperandInfo[704] }, // Inst #1419 = LARL + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #1418 = LAOG + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1417 = LAO + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #1416 = LANG + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1415 = LAN + { 4, &SystemZDescs.OperandInfo[1092] }, // Inst #1414 = LAMY + { 4, &SystemZDescs.OperandInfo[1092] }, // Inst #1413 = LAM + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1412 = LAEY + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1411 = LAE + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #1410 = LAALG + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1409 = LAAL + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #1408 = LAAG + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1407 = LAA + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1406 = LA + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #1405 = L + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1404 = KXTR + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1403 = KXBR + { 4, &SystemZDescs.OperandInfo[782] }, // Inst #1402 = KMO + { 4, &SystemZDescs.OperandInfo[782] }, // Inst #1401 = KMF + { 6, &SystemZDescs.OperandInfo[1086] }, // Inst #1400 = KMCTR + { 4, &SystemZDescs.OperandInfo[782] }, // Inst #1399 = KMC + { 3, &SystemZDescs.OperandInfo[1083] }, // Inst #1398 = KMAC + { 6, &SystemZDescs.OperandInfo[1086] }, // Inst #1397 = KMA + { 4, &SystemZDescs.OperandInfo[782] }, // Inst #1396 = KM + { 3, &SystemZDescs.OperandInfo[1083] }, // Inst #1395 = KLMD + { 3, &SystemZDescs.OperandInfo[1083] }, // Inst #1394 = KIMD + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #1393 = KEBR + { 4, &SystemZDescs.OperandInfo[643] }, // Inst #1392 = KEB + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #1391 = KDTR + { 3, &SystemZDescs.OperandInfo[1083] }, // Inst #1390 = KDSA + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #1389 = KDBR + { 4, &SystemZDescs.OperandInfo[615] }, // Inst #1388 = KDB + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1387 = JGAsmZ + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1386 = JGAsmP + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1385 = JGAsmO + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1384 = JGAsmNZ + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1383 = JGAsmNP + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1382 = JGAsmNO + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1381 = JGAsmNM + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1380 = JGAsmNLH + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1379 = JGAsmNLE + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1378 = JGAsmNL + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1377 = JGAsmNHE + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1376 = JGAsmNH + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1375 = JGAsmNE + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1374 = JGAsmM + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1373 = JGAsmLH + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1372 = JGAsmLE + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1371 = JGAsmL + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1370 = JGAsmHE + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1369 = JGAsmH + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1368 = JGAsmE + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1367 = JG + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1366 = JAsmZ + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1365 = JAsmP + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1364 = JAsmO + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1363 = JAsmNZ + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1362 = JAsmNP + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1361 = JAsmNO + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1360 = JAsmNM + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1359 = JAsmNLH + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1358 = JAsmNLE + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1357 = JAsmNL + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1356 = JAsmNHE + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1355 = JAsmNH + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1354 = JAsmNE + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1353 = JAsmM + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1352 = JAsmLH + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1351 = JAsmLE + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1350 = JAsmL + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1349 = JAsmHE + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1348 = JAsmH + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1347 = JAsmE + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #1346 = J + { 5, &SystemZDescs.OperandInfo[1078] }, // Inst #1345 = InsnVSI + { 6, &SystemZDescs.OperandInfo[1072] }, // Inst #1344 = InsnVRX + { 6, &SystemZDescs.OperandInfo[1066] }, // Inst #1343 = InsnVRV + { 6, &SystemZDescs.OperandInfo[1060] }, // Inst #1342 = InsnVRS + { 7, &SystemZDescs.OperandInfo[1053] }, // Inst #1341 = InsnVRR + { 6, &SystemZDescs.OperandInfo[1047] }, // Inst #1340 = InsnVRI + { 6, &SystemZDescs.OperandInfo[1041] }, // Inst #1339 = InsnSSF + { 5, &SystemZDescs.OperandInfo[1036] }, // Inst #1338 = InsnSSE + { 7, &SystemZDescs.OperandInfo[1029] }, // Inst #1337 = InsnSS + { 4, &SystemZDescs.OperandInfo[1025] }, // Inst #1336 = InsnSIY + { 4, &SystemZDescs.OperandInfo[1025] }, // Inst #1335 = InsnSIL + { 4, &SystemZDescs.OperandInfo[1025] }, // Inst #1334 = InsnSI + { 3, &SystemZDescs.OperandInfo[1022] }, // Inst #1333 = InsnS + { 5, &SystemZDescs.OperandInfo[1011] }, // Inst #1332 = InsnRXY + { 6, &SystemZDescs.OperandInfo[1016] }, // Inst #1331 = InsnRXF + { 5, &SystemZDescs.OperandInfo[1011] }, // Inst #1330 = InsnRXE + { 5, &SystemZDescs.OperandInfo[1011] }, // Inst #1329 = InsnRX + { 5, &SystemZDescs.OperandInfo[1006] }, // Inst #1328 = InsnRSY + { 4, &SystemZDescs.OperandInfo[979] }, // Inst #1327 = InsnRSI + { 5, &SystemZDescs.OperandInfo[1006] }, // Inst #1326 = InsnRSE + { 5, &SystemZDescs.OperandInfo[1006] }, // Inst #1325 = InsnRS + { 6, &SystemZDescs.OperandInfo[1000] }, // Inst #1324 = InsnRRS + { 5, &SystemZDescs.OperandInfo[995] }, // Inst #1323 = InsnRRF + { 3, &SystemZDescs.OperandInfo[992] }, // Inst #1322 = InsnRRE + { 3, &SystemZDescs.OperandInfo[992] }, // Inst #1321 = InsnRR + { 6, &SystemZDescs.OperandInfo[986] }, // Inst #1320 = InsnRIS + { 3, &SystemZDescs.OperandInfo[976] }, // Inst #1319 = InsnRILU + { 3, &SystemZDescs.OperandInfo[983] }, // Inst #1318 = InsnRIL + { 4, &SystemZDescs.OperandInfo[979] }, // Inst #1317 = InsnRIE + { 3, &SystemZDescs.OperandInfo[976] }, // Inst #1316 = InsnRI + { 1, &SystemZDescs.OperandInfo[1] }, // Inst #1315 = InsnE + { 3, &SystemZDescs.OperandInfo[569] }, // Inst #1314 = IVSK + { 3, &SystemZDescs.OperandInfo[569] }, // Inst #1313 = ISKE + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1312 = IRBM + { 2, &SystemZDescs.OperandInfo[702] }, // Inst #1311 = IPTEOptOpt + { 3, &SystemZDescs.OperandInfo[973] }, // Inst #1310 = IPTEOpt + { 4, &SystemZDescs.OperandInfo[969] }, // Inst #1309 = IPTE + { 1, &SystemZDescs.OperandInfo[923] }, // Inst #1308 = IPM + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #1307 = IPK + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1306 = IILL + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #1305 = IILH + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #1304 = IILF + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1303 = IIHL + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #1302 = IIHH + { 2, &SystemZDescs.OperandInfo[764] }, // Inst #1301 = IIHF + { 3, &SystemZDescs.OperandInfo[541] }, // Inst #1300 = IEXTR + { 3, &SystemZDescs.OperandInfo[488] }, // Inst #1299 = IEDTR + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #1298 = IDTEOpt + { 4, &SystemZDescs.OperandInfo[965] }, // Inst #1297 = IDTE + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #1296 = ICY + { 5, &SystemZDescs.OperandInfo[955] }, // Inst #1295 = ICMY + { 5, &SystemZDescs.OperandInfo[960] }, // Inst #1294 = ICMH + { 5, &SystemZDescs.OperandInfo[955] }, // Inst #1293 = ICM + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #1292 = IC32Y + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #1291 = IC32 + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #1290 = IC + { 1, &SystemZDescs.OperandInfo[923] }, // Inst #1289 = IAC + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #1288 = HSCH + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #1287 = HER + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #1286 = HDR + { 2, &SystemZDescs.OperandInfo[158] }, // Inst #1285 = FLOGR + { 4, &SystemZDescs.OperandInfo[951] }, // Inst #1284 = FIXTR + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1283 = FIXR + { 4, &SystemZDescs.OperandInfo[951] }, // Inst #1282 = FIXBRA + { 3, &SystemZDescs.OperandInfo[948] }, // Inst #1281 = FIXBR + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #1280 = FIER + { 4, &SystemZDescs.OperandInfo[944] }, // Inst #1279 = FIEBRA + { 3, &SystemZDescs.OperandInfo[941] }, // Inst #1278 = FIEBR + { 4, &SystemZDescs.OperandInfo[937] }, // Inst #1277 = FIDTR + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #1276 = FIDR + { 4, &SystemZDescs.OperandInfo[937] }, // Inst #1275 = FIDBRA + { 3, &SystemZDescs.OperandInfo[934] }, // Inst #1274 = FIDBR + { 2, &SystemZDescs.OperandInfo[932] }, // Inst #1273 = EXRL + { 4, &SystemZDescs.OperandInfo[928] }, // Inst #1272 = EX + { 1, &SystemZDescs.OperandInfo[923] }, // Inst #1271 = ETND + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1270 = ESXTR + { 2, &SystemZDescs.OperandInfo[926] }, // Inst #1269 = ESTA + { 2, &SystemZDescs.OperandInfo[924] }, // Inst #1268 = ESEA + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #1267 = ESDTR + { 1, &SystemZDescs.OperandInfo[923] }, // Inst #1266 = ESAR + { 1, &SystemZDescs.OperandInfo[290] }, // Inst #1265 = ESAIR + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1264 = EREGG + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1263 = EREG + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1262 = EPSW + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1261 = EPCTR + { 1, &SystemZDescs.OperandInfo[923] }, // Inst #1260 = EPAR + { 1, &SystemZDescs.OperandInfo[290] }, // Inst #1259 = EPAIR + { 1, &SystemZDescs.OperandInfo[923] }, // Inst #1258 = EFPC + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1257 = EEXTR + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #1256 = EEDTR + { 5, &SystemZDescs.OperandInfo[777] }, // Inst #1255 = EDMK + { 5, &SystemZDescs.OperandInfo[777] }, // Inst #1254 = ED + { 5, &SystemZDescs.OperandInfo[861] }, // Inst #1253 = ECTG + { 2, &SystemZDescs.OperandInfo[921] }, // Inst #1252 = ECPGA + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #1251 = ECCTR + { 4, &SystemZDescs.OperandInfo[917] }, // Inst #1250 = ECAG + { 2, &SystemZDescs.OperandInfo[915] }, // Inst #1249 = EAR + { 4, &SystemZDescs.OperandInfo[544] }, // Inst #1248 = DXTRA + { 3, &SystemZDescs.OperandInfo[541] }, // Inst #1247 = DXTR + { 3, &SystemZDescs.OperandInfo[538] }, // Inst #1246 = DXR + { 3, &SystemZDescs.OperandInfo[538] }, // Inst #1245 = DXBR + { 3, &SystemZDescs.OperandInfo[858] }, // Inst #1244 = DSGR + { 3, &SystemZDescs.OperandInfo[912] }, // Inst #1243 = DSGFR + { 5, &SystemZDescs.OperandInfo[892] }, // Inst #1242 = DSGF + { 5, &SystemZDescs.OperandInfo[892] }, // Inst #1241 = DSG + { 3, &SystemZDescs.OperandInfo[912] }, // Inst #1240 = DR + { 6, &SystemZDescs.OperandInfo[532] }, // Inst #1239 = DP + { 3, &SystemZDescs.OperandInfo[912] }, // Inst #1238 = DLR + { 3, &SystemZDescs.OperandInfo[858] }, // Inst #1237 = DLGR + { 5, &SystemZDescs.OperandInfo[892] }, // Inst #1236 = DLG + { 5, &SystemZDescs.OperandInfo[892] }, // Inst #1235 = DL + { 5, &SystemZDescs.OperandInfo[907] }, // Inst #1234 = DIEBR + { 5, &SystemZDescs.OperandInfo[902] }, // Inst #1233 = DIDBR + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1232 = DIAG + { 5, &SystemZDescs.OperandInfo[897] }, // Inst #1231 = DFLTCC + { 3, &SystemZDescs.OperandInfo[500] }, // Inst #1230 = DER + { 3, &SystemZDescs.OperandInfo[500] }, // Inst #1229 = DEBR + { 5, &SystemZDescs.OperandInfo[495] }, // Inst #1228 = DEB + { 5, &SystemZDescs.OperandInfo[495] }, // Inst #1227 = DE + { 4, &SystemZDescs.OperandInfo[491] }, // Inst #1226 = DDTRA + { 3, &SystemZDescs.OperandInfo[488] }, // Inst #1225 = DDTR + { 3, &SystemZDescs.OperandInfo[485] }, // Inst #1224 = DDR + { 3, &SystemZDescs.OperandInfo[485] }, // Inst #1223 = DDBR + { 5, &SystemZDescs.OperandInfo[480] }, // Inst #1222 = DDB + { 5, &SystemZDescs.OperandInfo[480] }, // Inst #1221 = DD + { 5, &SystemZDescs.OperandInfo[892] }, // Inst #1220 = D + { 5, &SystemZDescs.OperandInfo[841] }, // Inst #1219 = CZXT + { 5, &SystemZDescs.OperandInfo[633] }, // Inst #1218 = CZDT + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #1217 = CY + { 5, &SystemZDescs.OperandInfo[841] }, // Inst #1216 = CXZT + { 2, &SystemZDescs.OperandInfo[890] }, // Inst #1215 = CXUTR + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1214 = CXTR + { 2, &SystemZDescs.OperandInfo[890] }, // Inst #1213 = CXSTR + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1212 = CXR + { 5, &SystemZDescs.OperandInfo[841] }, // Inst #1211 = CXPT + { 4, &SystemZDescs.OperandInfo[886] }, // Inst #1210 = CXLGTR + { 4, &SystemZDescs.OperandInfo[886] }, // Inst #1209 = CXLGBR + { 4, &SystemZDescs.OperandInfo[880] }, // Inst #1208 = CXLFTR + { 4, &SystemZDescs.OperandInfo[880] }, // Inst #1207 = CXLFBR + { 4, &SystemZDescs.OperandInfo[886] }, // Inst #1206 = CXGTRA + { 2, &SystemZDescs.OperandInfo[884] }, // Inst #1205 = CXGTR + { 2, &SystemZDescs.OperandInfo[884] }, // Inst #1204 = CXGR + { 4, &SystemZDescs.OperandInfo[886] }, // Inst #1203 = CXGBRA + { 2, &SystemZDescs.OperandInfo[884] }, // Inst #1202 = CXGBR + { 4, &SystemZDescs.OperandInfo[880] }, // Inst #1201 = CXFTR + { 2, &SystemZDescs.OperandInfo[878] }, // Inst #1200 = CXFR + { 4, &SystemZDescs.OperandInfo[880] }, // Inst #1199 = CXFBRA + { 2, &SystemZDescs.OperandInfo[878] }, // Inst #1198 = CXFBR + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #1197 = CXBR + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #1196 = CVDY + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #1195 = CVDG + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #1194 = CVD + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #1193 = CVBY + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #1192 = CVBG + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #1191 = CVB + { 2, &SystemZDescs.OperandInfo[876] }, // Inst #1190 = CUXTR + { 4, &SystemZDescs.OperandInfo[782] }, // Inst #1189 = CUUTFOpt + { 5, &SystemZDescs.OperandInfo[869] }, // Inst #1188 = CUUTF + { 4, &SystemZDescs.OperandInfo[782] }, // Inst #1187 = CUTFUOpt + { 5, &SystemZDescs.OperandInfo[869] }, // Inst #1186 = CUTFU + { 4, &SystemZDescs.OperandInfo[782] }, // Inst #1185 = CUSE + { 2, &SystemZDescs.OperandInfo[874] }, // Inst #1184 = CUDTR + { 4, &SystemZDescs.OperandInfo[782] }, // Inst #1183 = CU42 + { 4, &SystemZDescs.OperandInfo[782] }, // Inst #1182 = CU41 + { 4, &SystemZDescs.OperandInfo[782] }, // Inst #1181 = CU24Opt + { 5, &SystemZDescs.OperandInfo[869] }, // Inst #1180 = CU24 + { 4, &SystemZDescs.OperandInfo[782] }, // Inst #1179 = CU21Opt + { 5, &SystemZDescs.OperandInfo[869] }, // Inst #1178 = CU21 + { 4, &SystemZDescs.OperandInfo[782] }, // Inst #1177 = CU14Opt + { 5, &SystemZDescs.OperandInfo[869] }, // Inst #1176 = CU14 + { 4, &SystemZDescs.OperandInfo[782] }, // Inst #1175 = CU12Opt + { 5, &SystemZDescs.OperandInfo[869] }, // Inst #1174 = CU12 + { 5, &SystemZDescs.OperandInfo[601] }, // Inst #1173 = CSY + { 3, &SystemZDescs.OperandInfo[866] }, // Inst #1172 = CSXTR + { 5, &SystemZDescs.OperandInfo[861] }, // Inst #1171 = CSST + { 3, &SystemZDescs.OperandInfo[858] }, // Inst #1170 = CSPG + { 3, &SystemZDescs.OperandInfo[858] }, // Inst #1169 = CSP + { 5, &SystemZDescs.OperandInfo[606] }, // Inst #1168 = CSG + { 3, &SystemZDescs.OperandInfo[855] }, // Inst #1167 = CSDTR + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #1166 = CSCH + { 5, &SystemZDescs.OperandInfo[601] }, // Inst #1165 = CS + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1164 = CRTAsmNLH + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1163 = CRTAsmNLE + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1162 = CRTAsmNL + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1161 = CRTAsmNHE + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1160 = CRTAsmNH + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1159 = CRTAsmNE + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1158 = CRTAsmLH + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1157 = CRTAsmLE + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1156 = CRTAsmL + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1155 = CRTAsmHE + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1154 = CRTAsmH + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1153 = CRTAsmE + { 3, &SystemZDescs.OperandInfo[239] }, // Inst #1152 = CRTAsm + { 3, &SystemZDescs.OperandInfo[239] }, // Inst #1151 = CRT + { 2, &SystemZDescs.OperandInfo[753] }, // Inst #1150 = CRL + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1149 = CRJAsmNLH + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1148 = CRJAsmNLE + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1147 = CRJAsmNL + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1146 = CRJAsmNHE + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1145 = CRJAsmNH + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1144 = CRJAsmNE + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1143 = CRJAsmLH + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1142 = CRJAsmLE + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1141 = CRJAsmL + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1140 = CRJAsmHE + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1139 = CRJAsmH + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1138 = CRJAsmE + { 4, &SystemZDescs.OperandInfo[814] }, // Inst #1137 = CRJAsm + { 4, &SystemZDescs.OperandInfo[814] }, // Inst #1136 = CRJ + { 3, &SystemZDescs.OperandInfo[852] }, // Inst #1135 = CRDTEOpt + { 4, &SystemZDescs.OperandInfo[848] }, // Inst #1134 = CRDTE + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1133 = CRBAsmNLH + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1132 = CRBAsmNLE + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1131 = CRBAsmNL + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1130 = CRBAsmNHE + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1129 = CRBAsmNH + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1128 = CRBAsmNE + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1127 = CRBAsmLH + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1126 = CRBAsmLE + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1125 = CRBAsmL + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1124 = CRBAsmHE + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1123 = CRBAsmH + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1122 = CRBAsmE + { 5, &SystemZDescs.OperandInfo[805] }, // Inst #1121 = CRBAsm + { 5, &SystemZDescs.OperandInfo[805] }, // Inst #1120 = CRB + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1119 = CR + { 2, &SystemZDescs.OperandInfo[846] }, // Inst #1118 = CPYA + { 5, &SystemZDescs.OperandInfo[841] }, // Inst #1117 = CPXT + { 3, &SystemZDescs.OperandInfo[838] }, // Inst #1116 = CPSDRss + { 3, &SystemZDescs.OperandInfo[835] }, // Inst #1115 = CPSDRsd + { 3, &SystemZDescs.OperandInfo[832] }, // Inst #1114 = CPSDRds + { 3, &SystemZDescs.OperandInfo[488] }, // Inst #1113 = CPSDRdd + { 5, &SystemZDescs.OperandInfo[633] }, // Inst #1112 = CPDT + { 6, &SystemZDescs.OperandInfo[532] }, // Inst #1111 = CP + { 4, &SystemZDescs.OperandInfo[782] }, // Inst #1110 = CMPSC + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #1109 = CLY + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #1108 = CLTAsmNLH + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #1107 = CLTAsmNLE + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #1106 = CLTAsmNL + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #1105 = CLTAsmNHE + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #1104 = CLTAsmNH + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #1103 = CLTAsmNE + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #1102 = CLTAsmLH + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #1101 = CLTAsmLE + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #1100 = CLTAsmL + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #1099 = CLTAsmHE + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #1098 = CLTAsmH + { 3, &SystemZDescs.OperandInfo[829] }, // Inst #1097 = CLTAsmE + { 4, &SystemZDescs.OperandInfo[825] }, // Inst #1096 = CLTAsm + { 4, &SystemZDescs.OperandInfo[825] }, // Inst #1095 = CLT + { 4, &SystemZDescs.OperandInfo[821] }, // Inst #1094 = CLST + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1093 = CLRTAsmNLH + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1092 = CLRTAsmNLE + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1091 = CLRTAsmNL + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1090 = CLRTAsmNHE + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1089 = CLRTAsmNH + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1088 = CLRTAsmNE + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1087 = CLRTAsmLH + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1086 = CLRTAsmLE + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1085 = CLRTAsmL + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1084 = CLRTAsmHE + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1083 = CLRTAsmH + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1082 = CLRTAsmE + { 3, &SystemZDescs.OperandInfo[239] }, // Inst #1081 = CLRTAsm + { 3, &SystemZDescs.OperandInfo[239] }, // Inst #1080 = CLRT + { 2, &SystemZDescs.OperandInfo[753] }, // Inst #1079 = CLRL + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1078 = CLRJAsmNLH + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1077 = CLRJAsmNLE + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1076 = CLRJAsmNL + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1075 = CLRJAsmNHE + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1074 = CLRJAsmNH + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1073 = CLRJAsmNE + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1072 = CLRJAsmLH + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1071 = CLRJAsmLE + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1070 = CLRJAsmL + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1069 = CLRJAsmHE + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1068 = CLRJAsmH + { 3, &SystemZDescs.OperandInfo[818] }, // Inst #1067 = CLRJAsmE + { 4, &SystemZDescs.OperandInfo[814] }, // Inst #1066 = CLRJAsm + { 4, &SystemZDescs.OperandInfo[814] }, // Inst #1065 = CLRJ + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1064 = CLRBAsmNLH + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1063 = CLRBAsmNLE + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1062 = CLRBAsmNL + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1061 = CLRBAsmNHE + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1060 = CLRBAsmNH + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1059 = CLRBAsmNE + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1058 = CLRBAsmLH + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1057 = CLRBAsmLE + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1056 = CLRBAsmL + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1055 = CLRBAsmHE + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1054 = CLRBAsmH + { 4, &SystemZDescs.OperandInfo[810] }, // Inst #1053 = CLRBAsmE + { 5, &SystemZDescs.OperandInfo[805] }, // Inst #1052 = CLRBAsm + { 5, &SystemZDescs.OperandInfo[805] }, // Inst #1051 = CLRB + { 2, &SystemZDescs.OperandInfo[803] }, // Inst #1050 = CLR + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #1049 = CLMY + { 4, &SystemZDescs.OperandInfo[799] }, // Inst #1048 = CLMH + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #1047 = CLM + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #1046 = CLIY + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #1045 = CLIJAsmNLH + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #1044 = CLIJAsmNLE + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #1043 = CLIJAsmNL + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #1042 = CLIJAsmNHE + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #1041 = CLIJAsmNH + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #1040 = CLIJAsmNE + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #1039 = CLIJAsmLH + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #1038 = CLIJAsmLE + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #1037 = CLIJAsmL + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #1036 = CLIJAsmHE + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #1035 = CLIJAsmH + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #1034 = CLIJAsmE + { 4, &SystemZDescs.OperandInfo[766] }, // Inst #1033 = CLIJAsm + { 4, &SystemZDescs.OperandInfo[766] }, // Inst #1032 = CLIJ + { 2, &SystemZDescs.OperandInfo[764] }, // Inst #1031 = CLIH + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #1030 = CLIBAsmNLH + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #1029 = CLIBAsmNLE + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #1028 = CLIBAsmNL + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #1027 = CLIBAsmNHE + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #1026 = CLIBAsmNH + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #1025 = CLIBAsmNE + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #1024 = CLIBAsmLH + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #1023 = CLIBAsmLE + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #1022 = CLIBAsmL + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #1021 = CLIBAsmHE + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #1020 = CLIBAsmH + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #1019 = CLIBAsmE + { 5, &SystemZDescs.OperandInfo[755] }, // Inst #1018 = CLIBAsm + { 5, &SystemZDescs.OperandInfo[755] }, // Inst #1017 = CLIB + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #1016 = CLI + { 2, &SystemZDescs.OperandInfo[753] }, // Inst #1015 = CLHRL + { 2, &SystemZDescs.OperandInfo[751] }, // Inst #1014 = CLHLR + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #1013 = CLHHSI + { 2, &SystemZDescs.OperandInfo[749] }, // Inst #1012 = CLHHR + { 4, &SystemZDescs.OperandInfo[745] }, // Inst #1011 = CLHF + { 4, &SystemZDescs.OperandInfo[741] }, // Inst #1010 = CLGXTR + { 4, &SystemZDescs.OperandInfo[741] }, // Inst #1009 = CLGXBR + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #1008 = CLGTAsmNLH + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #1007 = CLGTAsmNLE + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #1006 = CLGTAsmNL + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #1005 = CLGTAsmNHE + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #1004 = CLGTAsmNH + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #1003 = CLGTAsmNE + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #1002 = CLGTAsmLH + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #1001 = CLGTAsmLE + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #1000 = CLGTAsmL + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #999 = CLGTAsmHE + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #998 = CLGTAsmH + { 3, &SystemZDescs.OperandInfo[796] }, // Inst #997 = CLGTAsmE + { 4, &SystemZDescs.OperandInfo[792] }, // Inst #996 = CLGTAsm + { 4, &SystemZDescs.OperandInfo[792] }, // Inst #995 = CLGT + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #994 = CLGRTAsmNLH + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #993 = CLGRTAsmNLE + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #992 = CLGRTAsmNL + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #991 = CLGRTAsmNHE + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #990 = CLGRTAsmNH + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #989 = CLGRTAsmNE + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #988 = CLGRTAsmLH + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #987 = CLGRTAsmLE + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #986 = CLGRTAsmL + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #985 = CLGRTAsmHE + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #984 = CLGRTAsmH + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #983 = CLGRTAsmE + { 3, &SystemZDescs.OperandInfo[211] }, // Inst #982 = CLGRTAsm + { 3, &SystemZDescs.OperandInfo[211] }, // Inst #981 = CLGRT + { 2, &SystemZDescs.OperandInfo[704] }, // Inst #980 = CLGRL + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #979 = CLGRJAsmNLH + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #978 = CLGRJAsmNLE + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #977 = CLGRJAsmNL + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #976 = CLGRJAsmNHE + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #975 = CLGRJAsmNH + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #974 = CLGRJAsmNE + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #973 = CLGRJAsmLH + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #972 = CLGRJAsmLE + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #971 = CLGRJAsmL + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #970 = CLGRJAsmHE + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #969 = CLGRJAsmH + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #968 = CLGRJAsmE + { 4, &SystemZDescs.OperandInfo[731] }, // Inst #967 = CLGRJAsm + { 4, &SystemZDescs.OperandInfo[731] }, // Inst #966 = CLGRJ + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #965 = CLGRBAsmNLH + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #964 = CLGRBAsmNLE + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #963 = CLGRBAsmNL + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #962 = CLGRBAsmNHE + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #961 = CLGRBAsmNH + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #960 = CLGRBAsmNE + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #959 = CLGRBAsmLH + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #958 = CLGRBAsmLE + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #957 = CLGRBAsmL + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #956 = CLGRBAsmHE + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #955 = CLGRBAsmH + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #954 = CLGRBAsmE + { 5, &SystemZDescs.OperandInfo[722] }, // Inst #953 = CLGRBAsm + { 5, &SystemZDescs.OperandInfo[722] }, // Inst #952 = CLGRB + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #951 = CLGR + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #950 = CLGITAsmNLH + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #949 = CLGITAsmNLE + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #948 = CLGITAsmNL + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #947 = CLGITAsmNHE + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #946 = CLGITAsmNH + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #945 = CLGITAsmNE + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #944 = CLGITAsmLH + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #943 = CLGITAsmLE + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #942 = CLGITAsmL + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #941 = CLGITAsmHE + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #940 = CLGITAsmH + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #939 = CLGITAsmE + { 3, &SystemZDescs.OperandInfo[204] }, // Inst #938 = CLGITAsm + { 3, &SystemZDescs.OperandInfo[204] }, // Inst #937 = CLGIT + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #936 = CLGIJAsmNLH + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #935 = CLGIJAsmNLE + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #934 = CLGIJAsmNL + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #933 = CLGIJAsmNHE + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #932 = CLGIJAsmNH + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #931 = CLGIJAsmNE + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #930 = CLGIJAsmLH + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #929 = CLGIJAsmLE + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #928 = CLGIJAsmL + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #927 = CLGIJAsmHE + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #926 = CLGIJAsmH + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #925 = CLGIJAsmE + { 4, &SystemZDescs.OperandInfo[715] }, // Inst #924 = CLGIJAsm + { 4, &SystemZDescs.OperandInfo[715] }, // Inst #923 = CLGIJ + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #922 = CLGIBAsmNLH + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #921 = CLGIBAsmNLE + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #920 = CLGIBAsmNL + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #919 = CLGIBAsmNHE + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #918 = CLGIBAsmNH + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #917 = CLGIBAsmNE + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #916 = CLGIBAsmLH + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #915 = CLGIBAsmLE + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #914 = CLGIBAsmL + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #913 = CLGIBAsmHE + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #912 = CLGIBAsmH + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #911 = CLGIBAsmE + { 5, &SystemZDescs.OperandInfo[706] }, // Inst #910 = CLGIBAsm + { 5, &SystemZDescs.OperandInfo[706] }, // Inst #909 = CLGIB + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #908 = CLGHSI + { 2, &SystemZDescs.OperandInfo[704] }, // Inst #907 = CLGHRL + { 2, &SystemZDescs.OperandInfo[704] }, // Inst #906 = CLGFRL + { 2, &SystemZDescs.OperandInfo[702] }, // Inst #905 = CLGFR + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #904 = CLGFI + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #903 = CLGF + { 4, &SystemZDescs.OperandInfo[698] }, // Inst #902 = CLGEBR + { 4, &SystemZDescs.OperandInfo[691] }, // Inst #901 = CLGDTR + { 4, &SystemZDescs.OperandInfo[691] }, // Inst #900 = CLGDBR + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #899 = CLG + { 4, &SystemZDescs.OperandInfo[684] }, // Inst #898 = CLFXTR + { 4, &SystemZDescs.OperandInfo[684] }, // Inst #897 = CLFXBR + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #896 = CLFITAsmNLH + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #895 = CLFITAsmNLE + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #894 = CLFITAsmNL + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #893 = CLFITAsmNHE + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #892 = CLFITAsmNH + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #891 = CLFITAsmNE + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #890 = CLFITAsmLH + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #889 = CLFITAsmLE + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #888 = CLFITAsmL + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #887 = CLFITAsmHE + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #886 = CLFITAsmH + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #885 = CLFITAsmE + { 3, &SystemZDescs.OperandInfo[218] }, // Inst #884 = CLFITAsm + { 3, &SystemZDescs.OperandInfo[218] }, // Inst #883 = CLFIT + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #882 = CLFI + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #881 = CLFHSI + { 4, &SystemZDescs.OperandInfo[675] }, // Inst #880 = CLFEBR + { 4, &SystemZDescs.OperandInfo[668] }, // Inst #879 = CLFDTR + { 4, &SystemZDescs.OperandInfo[668] }, // Inst #878 = CLFDBR + { 6, &SystemZDescs.OperandInfo[786] }, // Inst #877 = CLCLU + { 6, &SystemZDescs.OperandInfo[786] }, // Inst #876 = CLCLE + { 4, &SystemZDescs.OperandInfo[782] }, // Inst #875 = CLCL + { 5, &SystemZDescs.OperandInfo[777] }, // Inst #874 = CLC + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #873 = CL + { 4, &SystemZDescs.OperandInfo[773] }, // Inst #872 = CKSM + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #871 = CITAsmNLH + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #870 = CITAsmNLE + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #869 = CITAsmNL + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #868 = CITAsmNHE + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #867 = CITAsmNH + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #866 = CITAsmNE + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #865 = CITAsmLH + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #864 = CITAsmLE + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #863 = CITAsmL + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #862 = CITAsmHE + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #861 = CITAsmH + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #860 = CITAsmE + { 3, &SystemZDescs.OperandInfo[218] }, // Inst #859 = CITAsm + { 3, &SystemZDescs.OperandInfo[218] }, // Inst #858 = CIT + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #857 = CIJAsmNLH + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #856 = CIJAsmNLE + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #855 = CIJAsmNL + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #854 = CIJAsmNHE + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #853 = CIJAsmNH + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #852 = CIJAsmNE + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #851 = CIJAsmLH + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #850 = CIJAsmLE + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #849 = CIJAsmL + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #848 = CIJAsmHE + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #847 = CIJAsmH + { 3, &SystemZDescs.OperandInfo[770] }, // Inst #846 = CIJAsmE + { 4, &SystemZDescs.OperandInfo[766] }, // Inst #845 = CIJAsm + { 4, &SystemZDescs.OperandInfo[766] }, // Inst #844 = CIJ + { 2, &SystemZDescs.OperandInfo[764] }, // Inst #843 = CIH + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #842 = CIBAsmNLH + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #841 = CIBAsmNLE + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #840 = CIBAsmNL + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #839 = CIBAsmNHE + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #838 = CIBAsmNH + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #837 = CIBAsmNE + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #836 = CIBAsmLH + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #835 = CIBAsmLE + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #834 = CIBAsmL + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #833 = CIBAsmHE + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #832 = CIBAsmH + { 4, &SystemZDescs.OperandInfo[760] }, // Inst #831 = CIBAsmE + { 5, &SystemZDescs.OperandInfo[755] }, // Inst #830 = CIBAsm + { 5, &SystemZDescs.OperandInfo[755] }, // Inst #829 = CIB + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #828 = CHY + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #827 = CHSI + { 2, &SystemZDescs.OperandInfo[753] }, // Inst #826 = CHRL + { 2, &SystemZDescs.OperandInfo[751] }, // Inst #825 = CHLR + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #824 = CHI + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #823 = CHHSI + { 2, &SystemZDescs.OperandInfo[749] }, // Inst #822 = CHHR + { 4, &SystemZDescs.OperandInfo[745] }, // Inst #821 = CHF + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #820 = CH + { 4, &SystemZDescs.OperandInfo[741] }, // Inst #819 = CGXTRA + { 3, &SystemZDescs.OperandInfo[738] }, // Inst #818 = CGXTR + { 3, &SystemZDescs.OperandInfo[738] }, // Inst #817 = CGXR + { 4, &SystemZDescs.OperandInfo[741] }, // Inst #816 = CGXBRA + { 3, &SystemZDescs.OperandInfo[738] }, // Inst #815 = CGXBR + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #814 = CGRTAsmNLH + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #813 = CGRTAsmNLE + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #812 = CGRTAsmNL + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #811 = CGRTAsmNHE + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #810 = CGRTAsmNH + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #809 = CGRTAsmNE + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #808 = CGRTAsmLH + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #807 = CGRTAsmLE + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #806 = CGRTAsmL + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #805 = CGRTAsmHE + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #804 = CGRTAsmH + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #803 = CGRTAsmE + { 3, &SystemZDescs.OperandInfo[211] }, // Inst #802 = CGRTAsm + { 3, &SystemZDescs.OperandInfo[211] }, // Inst #801 = CGRT + { 2, &SystemZDescs.OperandInfo[704] }, // Inst #800 = CGRL + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #799 = CGRJAsmNLH + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #798 = CGRJAsmNLE + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #797 = CGRJAsmNL + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #796 = CGRJAsmNHE + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #795 = CGRJAsmNH + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #794 = CGRJAsmNE + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #793 = CGRJAsmLH + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #792 = CGRJAsmLE + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #791 = CGRJAsmL + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #790 = CGRJAsmHE + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #789 = CGRJAsmH + { 3, &SystemZDescs.OperandInfo[735] }, // Inst #788 = CGRJAsmE + { 4, &SystemZDescs.OperandInfo[731] }, // Inst #787 = CGRJAsm + { 4, &SystemZDescs.OperandInfo[731] }, // Inst #786 = CGRJ + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #785 = CGRBAsmNLH + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #784 = CGRBAsmNLE + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #783 = CGRBAsmNL + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #782 = CGRBAsmNHE + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #781 = CGRBAsmNH + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #780 = CGRBAsmNE + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #779 = CGRBAsmLH + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #778 = CGRBAsmLE + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #777 = CGRBAsmL + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #776 = CGRBAsmHE + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #775 = CGRBAsmH + { 4, &SystemZDescs.OperandInfo[727] }, // Inst #774 = CGRBAsmE + { 5, &SystemZDescs.OperandInfo[722] }, // Inst #773 = CGRBAsm + { 5, &SystemZDescs.OperandInfo[722] }, // Inst #772 = CGRB + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #771 = CGR + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #770 = CGITAsmNLH + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #769 = CGITAsmNLE + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #768 = CGITAsmNL + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #767 = CGITAsmNHE + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #766 = CGITAsmNH + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #765 = CGITAsmNE + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #764 = CGITAsmLH + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #763 = CGITAsmLE + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #762 = CGITAsmL + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #761 = CGITAsmHE + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #760 = CGITAsmH + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #759 = CGITAsmE + { 3, &SystemZDescs.OperandInfo[204] }, // Inst #758 = CGITAsm + { 3, &SystemZDescs.OperandInfo[204] }, // Inst #757 = CGIT + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #756 = CGIJAsmNLH + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #755 = CGIJAsmNLE + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #754 = CGIJAsmNL + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #753 = CGIJAsmNHE + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #752 = CGIJAsmNH + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #751 = CGIJAsmNE + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #750 = CGIJAsmLH + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #749 = CGIJAsmLE + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #748 = CGIJAsmL + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #747 = CGIJAsmHE + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #746 = CGIJAsmH + { 3, &SystemZDescs.OperandInfo[719] }, // Inst #745 = CGIJAsmE + { 4, &SystemZDescs.OperandInfo[715] }, // Inst #744 = CGIJAsm + { 4, &SystemZDescs.OperandInfo[715] }, // Inst #743 = CGIJ + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #742 = CGIBAsmNLH + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #741 = CGIBAsmNLE + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #740 = CGIBAsmNL + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #739 = CGIBAsmNHE + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #738 = CGIBAsmNH + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #737 = CGIBAsmNE + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #736 = CGIBAsmLH + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #735 = CGIBAsmLE + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #734 = CGIBAsmL + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #733 = CGIBAsmHE + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #732 = CGIBAsmH + { 4, &SystemZDescs.OperandInfo[711] }, // Inst #731 = CGIBAsmE + { 5, &SystemZDescs.OperandInfo[706] }, // Inst #730 = CGIBAsm + { 5, &SystemZDescs.OperandInfo[706] }, // Inst #729 = CGIB + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #728 = CGHSI + { 2, &SystemZDescs.OperandInfo[704] }, // Inst #727 = CGHRL + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #726 = CGHI + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #725 = CGH + { 2, &SystemZDescs.OperandInfo[704] }, // Inst #724 = CGFRL + { 2, &SystemZDescs.OperandInfo[702] }, // Inst #723 = CGFR + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #722 = CGFI + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #721 = CGF + { 3, &SystemZDescs.OperandInfo[695] }, // Inst #720 = CGER + { 4, &SystemZDescs.OperandInfo[698] }, // Inst #719 = CGEBRA + { 3, &SystemZDescs.OperandInfo[695] }, // Inst #718 = CGEBR + { 4, &SystemZDescs.OperandInfo[691] }, // Inst #717 = CGDTRA + { 3, &SystemZDescs.OperandInfo[688] }, // Inst #716 = CGDTR + { 3, &SystemZDescs.OperandInfo[688] }, // Inst #715 = CGDR + { 4, &SystemZDescs.OperandInfo[691] }, // Inst #714 = CGDBRA + { 3, &SystemZDescs.OperandInfo[688] }, // Inst #713 = CGDBR + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #712 = CG + { 4, &SystemZDescs.OperandInfo[684] }, // Inst #711 = CFXTR + { 3, &SystemZDescs.OperandInfo[681] }, // Inst #710 = CFXR + { 4, &SystemZDescs.OperandInfo[684] }, // Inst #709 = CFXBRA + { 3, &SystemZDescs.OperandInfo[681] }, // Inst #708 = CFXBR + { 2, &SystemZDescs.OperandInfo[679] }, // Inst #707 = CFI + { 3, &SystemZDescs.OperandInfo[672] }, // Inst #706 = CFER + { 4, &SystemZDescs.OperandInfo[675] }, // Inst #705 = CFEBRA + { 3, &SystemZDescs.OperandInfo[672] }, // Inst #704 = CFEBR + { 4, &SystemZDescs.OperandInfo[668] }, // Inst #703 = CFDTR + { 3, &SystemZDescs.OperandInfo[665] }, // Inst #702 = CFDR + { 4, &SystemZDescs.OperandInfo[668] }, // Inst #701 = CFDBRA + { 3, &SystemZDescs.OperandInfo[665] }, // Inst #700 = CFDBR + { 2, &SystemZDescs.OperandInfo[663] }, // Inst #699 = CFC + { 2, &SystemZDescs.OperandInfo[661] }, // Inst #698 = CEXTR + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #697 = CER + { 4, &SystemZDescs.OperandInfo[657] }, // Inst #696 = CELGBR + { 4, &SystemZDescs.OperandInfo[651] }, // Inst #695 = CELFBR + { 2, &SystemZDescs.OperandInfo[655] }, // Inst #694 = CEGR + { 4, &SystemZDescs.OperandInfo[657] }, // Inst #693 = CEGBRA + { 2, &SystemZDescs.OperandInfo[655] }, // Inst #692 = CEGBR + { 2, &SystemZDescs.OperandInfo[649] }, // Inst #691 = CEFR + { 4, &SystemZDescs.OperandInfo[651] }, // Inst #690 = CEFBRA + { 2, &SystemZDescs.OperandInfo[649] }, // Inst #689 = CEFBR + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #688 = CEDTR + { 2, &SystemZDescs.OperandInfo[647] }, // Inst #687 = CEBR + { 4, &SystemZDescs.OperandInfo[643] }, // Inst #686 = CEB + { 4, &SystemZDescs.OperandInfo[643] }, // Inst #685 = CE + { 5, &SystemZDescs.OperandInfo[633] }, // Inst #684 = CDZT + { 2, &SystemZDescs.OperandInfo[627] }, // Inst #683 = CDUTR + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #682 = CDTR + { 5, &SystemZDescs.OperandInfo[638] }, // Inst #681 = CDSY + { 2, &SystemZDescs.OperandInfo[627] }, // Inst #680 = CDSTR + { 5, &SystemZDescs.OperandInfo[638] }, // Inst #679 = CDSG + { 5, &SystemZDescs.OperandInfo[638] }, // Inst #678 = CDS + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #677 = CDR + { 5, &SystemZDescs.OperandInfo[633] }, // Inst #676 = CDPT + { 4, &SystemZDescs.OperandInfo[629] }, // Inst #675 = CDLGTR + { 4, &SystemZDescs.OperandInfo[629] }, // Inst #674 = CDLGBR + { 4, &SystemZDescs.OperandInfo[623] }, // Inst #673 = CDLFTR + { 4, &SystemZDescs.OperandInfo[623] }, // Inst #672 = CDLFBR + { 4, &SystemZDescs.OperandInfo[629] }, // Inst #671 = CDGTRA + { 2, &SystemZDescs.OperandInfo[627] }, // Inst #670 = CDGTR + { 2, &SystemZDescs.OperandInfo[627] }, // Inst #669 = CDGR + { 4, &SystemZDescs.OperandInfo[629] }, // Inst #668 = CDGBRA + { 2, &SystemZDescs.OperandInfo[627] }, // Inst #667 = CDGBR + { 4, &SystemZDescs.OperandInfo[623] }, // Inst #666 = CDFTR + { 2, &SystemZDescs.OperandInfo[621] }, // Inst #665 = CDFR + { 4, &SystemZDescs.OperandInfo[623] }, // Inst #664 = CDFBRA + { 2, &SystemZDescs.OperandInfo[621] }, // Inst #663 = CDFBR + { 2, &SystemZDescs.OperandInfo[619] }, // Inst #662 = CDBR + { 4, &SystemZDescs.OperandInfo[615] }, // Inst #661 = CDB + { 4, &SystemZDescs.OperandInfo[615] }, // Inst #660 = CD + { 4, &SystemZDescs.OperandInfo[611] }, // Inst #659 = C + { 5, &SystemZDescs.OperandInfo[606] }, // Inst #658 = BXLEG + { 5, &SystemZDescs.OperandInfo[601] }, // Inst #657 = BXLE + { 5, &SystemZDescs.OperandInfo[606] }, // Inst #656 = BXHG + { 5, &SystemZDescs.OperandInfo[601] }, // Inst #655 = BXH + { 2, &SystemZDescs.OperandInfo[553] }, // Inst #654 = BSM + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #653 = BSG + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #652 = BSA + { 4, &SystemZDescs.OperandInfo[597] }, // Inst #651 = BRXLG + { 4, &SystemZDescs.OperandInfo[593] }, // Inst #650 = BRXLE + { 4, &SystemZDescs.OperandInfo[597] }, // Inst #649 = BRXHG + { 4, &SystemZDescs.OperandInfo[593] }, // Inst #648 = BRXH + { 3, &SystemZDescs.OperandInfo[590] }, // Inst #647 = BRCTH + { 3, &SystemZDescs.OperandInfo[587] }, // Inst #646 = BRCTG + { 3, &SystemZDescs.OperandInfo[584] }, // Inst #645 = BRCT + { 2, &SystemZDescs.OperandInfo[582] }, // Inst #644 = BRCLAsm + { 3, &SystemZDescs.OperandInfo[251] }, // Inst #643 = BRCL + { 2, &SystemZDescs.OperandInfo[582] }, // Inst #642 = BRCAsm + { 3, &SystemZDescs.OperandInfo[251] }, // Inst #641 = BRC + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #640 = BRAsmZ + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #639 = BRAsmP + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #638 = BRAsmO + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #637 = BRAsmNZ + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #636 = BRAsmNP + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #635 = BRAsmNO + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #634 = BRAsmNM + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #633 = BRAsmNLH + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #632 = BRAsmNLE + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #631 = BRAsmNL + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #630 = BRAsmNHE + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #629 = BRAsmNH + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #628 = BRAsmNE + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #627 = BRAsmM + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #626 = BRAsmLH + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #625 = BRAsmLE + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #624 = BRAsmL + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #623 = BRAsmHE + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #622 = BRAsmH + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #621 = BRAsmE + { 3, &SystemZDescs.OperandInfo[579] }, // Inst #620 = BRASL + { 3, &SystemZDescs.OperandInfo[579] }, // Inst #619 = BRAS + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #618 = BR + { 3, &SystemZDescs.OperandInfo[576] }, // Inst #617 = BPRP + { 4, &SystemZDescs.OperandInfo[572] }, // Inst #616 = BPP + { 4, &SystemZDescs.OperandInfo[560] }, // Inst #615 = BICAsm + { 5, &SystemZDescs.OperandInfo[555] }, // Inst #614 = BIC + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #613 = BIAsmZ + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #612 = BIAsmP + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #611 = BIAsmO + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #610 = BIAsmNZ + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #609 = BIAsmNP + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #608 = BIAsmNO + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #607 = BIAsmNM + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #606 = BIAsmNLH + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #605 = BIAsmNLE + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #604 = BIAsmNL + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #603 = BIAsmNHE + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #602 = BIAsmNH + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #601 = BIAsmNE + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #600 = BIAsmM + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #599 = BIAsmLH + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #598 = BIAsmLE + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #597 = BIAsmL + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #596 = BIAsmHE + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #595 = BIAsmH + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #594 = BIAsmE + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #593 = BI + { 3, &SystemZDescs.OperandInfo[569] }, // Inst #592 = BCTR + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #591 = BCTGR + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #590 = BCTG + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #589 = BCT + { 2, &SystemZDescs.OperandInfo[567] }, // Inst #588 = BCRAsm + { 3, &SystemZDescs.OperandInfo[564] }, // Inst #587 = BCR + { 4, &SystemZDescs.OperandInfo[560] }, // Inst #586 = BCAsm + { 5, &SystemZDescs.OperandInfo[555] }, // Inst #585 = BC + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #584 = BAsmZ + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #583 = BAsmP + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #582 = BAsmO + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #581 = BAsmNZ + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #580 = BAsmNP + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #579 = BAsmNO + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #578 = BAsmNM + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #577 = BAsmNLH + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #576 = BAsmNLE + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #575 = BAsmNL + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #574 = BAsmNHE + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #573 = BAsmNH + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #572 = BAsmNE + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #571 = BAsmM + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #570 = BAsmLH + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #569 = BAsmLE + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #568 = BAsmL + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #567 = BAsmHE + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #566 = BAsmH + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #565 = BAsmE + { 2, &SystemZDescs.OperandInfo[553] }, // Inst #564 = BASSM + { 2, &SystemZDescs.OperandInfo[553] }, // Inst #563 = BASR + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #562 = BAS + { 2, &SystemZDescs.OperandInfo[553] }, // Inst #561 = BALR + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #560 = BAL + { 2, &SystemZDescs.OperandInfo[551] }, // Inst #559 = BAKR + { 3, &SystemZDescs.OperandInfo[548] }, // Inst #558 = B + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #557 = AY + { 4, &SystemZDescs.OperandInfo[544] }, // Inst #556 = AXTRA + { 3, &SystemZDescs.OperandInfo[541] }, // Inst #555 = AXTR + { 3, &SystemZDescs.OperandInfo[538] }, // Inst #554 = AXR + { 3, &SystemZDescs.OperandInfo[538] }, // Inst #553 = AXBR + { 3, &SystemZDescs.OperandInfo[485] }, // Inst #552 = AWR + { 5, &SystemZDescs.OperandInfo[480] }, // Inst #551 = AW + { 3, &SystemZDescs.OperandInfo[500] }, // Inst #550 = AUR + { 5, &SystemZDescs.OperandInfo[495] }, // Inst #549 = AU + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #548 = ASI + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #547 = ARK + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #546 = AR + { 6, &SystemZDescs.OperandInfo[532] }, // Inst #545 = AP + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #544 = ALY + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #543 = ALSIHN + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #542 = ALSIH + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #541 = ALSI + { 3, &SystemZDescs.OperandInfo[529] }, // Inst #540 = ALRK + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #539 = ALR + { 3, &SystemZDescs.OperandInfo[239] }, // Inst #538 = ALHSIK + { 3, &SystemZDescs.OperandInfo[520] }, // Inst #537 = ALHHLR + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #536 = ALHHHR + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #535 = ALGSI + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #534 = ALGRK + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #533 = ALGR + { 3, &SystemZDescs.OperandInfo[211] }, // Inst #532 = ALGHSIK + { 3, &SystemZDescs.OperandInfo[511] }, // Inst #531 = ALGFR + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #530 = ALGFI + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #529 = ALGF + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #528 = ALG + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #527 = ALFI + { 3, &SystemZDescs.OperandInfo[526] }, // Inst #526 = ALCR + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #525 = ALCGR + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #524 = ALCG + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #523 = ALC + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #522 = AL + { 3, &SystemZDescs.OperandInfo[523] }, // Inst #521 = AIH + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #520 = AHY + { 3, &SystemZDescs.OperandInfo[239] }, // Inst #519 = AHIK + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #518 = AHI + { 3, &SystemZDescs.OperandInfo[520] }, // Inst #517 = AHHLR + { 3, &SystemZDescs.OperandInfo[517] }, // Inst #516 = AHHHR + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #515 = AH + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #514 = AGSI + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #513 = AGRK + { 3, &SystemZDescs.OperandInfo[514] }, // Inst #512 = AGR + { 3, &SystemZDescs.OperandInfo[211] }, // Inst #511 = AGHIK + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #510 = AGHI + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #509 = AGH + { 3, &SystemZDescs.OperandInfo[511] }, // Inst #508 = AGFR + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #507 = AGFI + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #506 = AGF + { 5, &SystemZDescs.OperandInfo[506] }, // Inst #505 = AG + { 3, &SystemZDescs.OperandInfo[503] }, // Inst #504 = AFI + { 3, &SystemZDescs.OperandInfo[500] }, // Inst #503 = AER + { 3, &SystemZDescs.OperandInfo[500] }, // Inst #502 = AEBR + { 5, &SystemZDescs.OperandInfo[495] }, // Inst #501 = AEB + { 5, &SystemZDescs.OperandInfo[495] }, // Inst #500 = AE + { 4, &SystemZDescs.OperandInfo[491] }, // Inst #499 = ADTRA + { 3, &SystemZDescs.OperandInfo[488] }, // Inst #498 = ADTR + { 3, &SystemZDescs.OperandInfo[485] }, // Inst #497 = ADR + { 3, &SystemZDescs.OperandInfo[485] }, // Inst #496 = ADBR + { 5, &SystemZDescs.OperandInfo[480] }, // Inst #495 = ADB + { 5, &SystemZDescs.OperandInfo[480] }, // Inst #494 = AD + { 5, &SystemZDescs.OperandInfo[475] }, // Inst #493 = A + { 2, &SystemZDescs.OperandInfo[158] }, // Inst #492 = ZEXT128 + { 5, &SystemZDescs.OperandInfo[171] }, // Inst #491 = X_MemFoldPseudo + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #490 = XPLINK_STACKALLOC + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #489 = XILF64 + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #488 = XIHF64 + { 3, &SystemZDescs.OperandInfo[160] }, // Inst #487 = XIFMux + { 5, &SystemZDescs.OperandInfo[163] }, // Inst #486 = XG_MemFoldPseudo + { 5, &SystemZDescs.OperandInfo[226] }, // Inst #485 = XCReg + { 5, &SystemZDescs.OperandInfo[221] }, // Inst #484 = XCImm + { 4, &SystemZDescs.OperandInfo[464] }, // Inst #483 = VST64 + { 4, &SystemZDescs.OperandInfo[460] }, // Inst #482 = VST32 + { 3, &SystemZDescs.OperandInfo[472] }, // Inst #481 = VLVGP32 + { 2, &SystemZDescs.OperandInfo[470] }, // Inst #480 = VLR64 + { 2, &SystemZDescs.OperandInfo[468] }, // Inst #479 = VLR32 + { 4, &SystemZDescs.OperandInfo[464] }, // Inst #478 = VL64 + { 4, &SystemZDescs.OperandInfo[460] }, // Inst #477 = VL32 + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #476 = UCmp128Hi + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #475 = Trap + { 2, &SystemZDescs.OperandInfo[198] }, // Inst #474 = TMLMux + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #473 = TMLL64 + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #472 = TMLH64 + { 2, &SystemZDescs.OperandInfo[198] }, // Inst #471 = TMHMux + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #470 = TMHL64 + { 2, &SystemZDescs.OperandInfo[458] }, // Inst #469 = TMHH64 + { 1, &SystemZDescs.OperandInfo[0] }, // Inst #468 = TLS_LDCALL + { 1, &SystemZDescs.OperandInfo[0] }, // Inst #467 = TLS_GDCALL + { 3, &SystemZDescs.OperandInfo[455] }, // Inst #466 = TBEGIN_nofloat + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #465 = Serialize + { 5, &SystemZDescs.OperandInfo[450] }, // Inst #464 = SelectVR64 + { 5, &SystemZDescs.OperandInfo[445] }, // Inst #463 = SelectVR32 + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #462 = SelectVR128 + { 5, &SystemZDescs.OperandInfo[440] }, // Inst #461 = SelectF64 + { 5, &SystemZDescs.OperandInfo[435] }, // Inst #460 = SelectF32 + { 5, &SystemZDescs.OperandInfo[430] }, // Inst #459 = SelectF128 + { 5, &SystemZDescs.OperandInfo[425] }, // Inst #458 = Select64 + { 5, &SystemZDescs.OperandInfo[420] }, // Inst #457 = Select32 + { 5, &SystemZDescs.OperandInfo[415] }, // Inst #456 = Select128 + { 5, &SystemZDescs.OperandInfo[171] }, // Inst #455 = S_MemFoldPseudo + { 4, &SystemZDescs.OperandInfo[335] }, // Inst #454 = STX + { 5, &SystemZDescs.OperandInfo[410] }, // Inst #453 = STOCMux + { 4, &SystemZDescs.OperandInfo[231] }, // Inst #452 = STMux + { 4, &SystemZDescs.OperandInfo[231] }, // Inst #451 = STHMux + { 4, &SystemZDescs.OperandInfo[231] }, // Inst #450 = STCMux + { 4, &SystemZDescs.OperandInfo[294] }, // Inst #449 = ST128 + { 4, &SystemZDescs.OperandInfo[242] }, // Inst #448 = SRSTLoop + { 5, &SystemZDescs.OperandInfo[171] }, // Inst #447 = SL_MemFoldPseudo + { 5, &SystemZDescs.OperandInfo[163] }, // Inst #446 = SLG_MemFoldPseudo + { 5, &SystemZDescs.OperandInfo[163] }, // Inst #445 = SG_MemFoldPseudo + { 5, &SystemZDescs.OperandInfo[405] }, // Inst #444 = SELRMux + { 5, &SystemZDescs.OperandInfo[153] }, // Inst #443 = SEB_MemFoldPseudo + { 5, &SystemZDescs.OperandInfo[144] }, // Inst #442 = SDB_MemFoldPseudo + { 2, &SystemZDescs.OperandInfo[403] }, // Inst #441 = SCmp128Hi + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #440 = Return_XPLINK + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #439 = Return + { 6, &SystemZDescs.OperandInfo[397] }, // Inst #438 = RISBMux + { 6, &SystemZDescs.OperandInfo[391] }, // Inst #437 = RISBLL + { 6, &SystemZDescs.OperandInfo[385] }, // Inst #436 = RISBLH + { 6, &SystemZDescs.OperandInfo[379] }, // Inst #435 = RISBHL + { 6, &SystemZDescs.OperandInfo[373] }, // Inst #434 = RISBHH + { 1, &SystemZDescs.OperandInfo[1] }, // Inst #433 = PROBED_STACKALLOC + { 3, &SystemZDescs.OperandInfo[370] }, // Inst #432 = PROBED_ALLOCA + { 3, &SystemZDescs.OperandInfo[367] }, // Inst #431 = PAIR128 + { 5, &SystemZDescs.OperandInfo[171] }, // Inst #430 = O_MemFoldPseudo + { 3, &SystemZDescs.OperandInfo[160] }, // Inst #429 = OILMux + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #428 = OILL64 + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #427 = OILH64 + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #426 = OILF64 + { 3, &SystemZDescs.OperandInfo[160] }, // Inst #425 = OIHMux + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #424 = OIHL64 + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #423 = OIHH64 + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #422 = OIHF64 + { 3, &SystemZDescs.OperandInfo[160] }, // Inst #421 = OIFMux + { 5, &SystemZDescs.OperandInfo[163] }, // Inst #420 = OG_MemFoldPseudo + { 5, &SystemZDescs.OperandInfo[226] }, // Inst #419 = OCReg + { 5, &SystemZDescs.OperandInfo[221] }, // Inst #418 = OCImm + { 5, &SystemZDescs.OperandInfo[171] }, // Inst #417 = N_MemFoldPseudo + { 3, &SystemZDescs.OperandInfo[160] }, // Inst #416 = NILMux + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #415 = NILL64 + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #414 = NILH64 + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #413 = NILF64 + { 3, &SystemZDescs.OperandInfo[160] }, // Inst #412 = NIHMux + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #411 = NIHL64 + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #410 = NIHH64 + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #409 = NIHF64 + { 3, &SystemZDescs.OperandInfo[160] }, // Inst #408 = NIFMux + { 5, &SystemZDescs.OperandInfo[163] }, // Inst #407 = NG_MemFoldPseudo + { 5, &SystemZDescs.OperandInfo[226] }, // Inst #406 = NCReg + { 5, &SystemZDescs.OperandInfo[221] }, // Inst #405 = NCImm + { 4, &SystemZDescs.OperandInfo[363] }, // Inst #404 = MemsetRegReg + { 4, &SystemZDescs.OperandInfo[359] }, // Inst #403 = MemsetRegImm + { 4, &SystemZDescs.OperandInfo[355] }, // Inst #402 = MemsetImmReg + { 4, &SystemZDescs.OperandInfo[351] }, // Inst #401 = MemsetImmImm + { 4, &SystemZDescs.OperandInfo[242] }, // Inst #400 = MVSTLoop + { 5, &SystemZDescs.OperandInfo[226] }, // Inst #399 = MVCReg + { 5, &SystemZDescs.OperandInfo[221] }, // Inst #398 = MVCImm + { 5, &SystemZDescs.OperandInfo[163] }, // Inst #397 = MSGC_MemFoldPseudo + { 6, &SystemZDescs.OperandInfo[345] }, // Inst #396 = MSEB_MemFoldPseudo + { 6, &SystemZDescs.OperandInfo[339] }, // Inst #395 = MSDB_MemFoldPseudo + { 5, &SystemZDescs.OperandInfo[171] }, // Inst #394 = MSC_MemFoldPseudo + { 5, &SystemZDescs.OperandInfo[153] }, // Inst #393 = MEEB_MemFoldPseudo + { 5, &SystemZDescs.OperandInfo[144] }, // Inst #392 = MDB_MemFoldPseudo + { 6, &SystemZDescs.OperandInfo[345] }, // Inst #391 = MAEB_MemFoldPseudo + { 6, &SystemZDescs.OperandInfo[339] }, // Inst #390 = MADB_MemFoldPseudo + { 4, &SystemZDescs.OperandInfo[335] }, // Inst #389 = LX + { 1, &SystemZDescs.OperandInfo[334] }, // Inst #388 = LTXBRCompare_Pseudo + { 1, &SystemZDescs.OperandInfo[333] }, // Inst #387 = LTEBRCompare_Pseudo + { 1, &SystemZDescs.OperandInfo[332] }, // Inst #386 = LTDBRCompare_Pseudo + { 5, &SystemZDescs.OperandInfo[327] }, // Inst #385 = LOCRMux + { 6, &SystemZDescs.OperandInfo[321] }, // Inst #384 = LOCMux_MemFoldPseudo + { 6, &SystemZDescs.OperandInfo[315] }, // Inst #383 = LOCMux + { 5, &SystemZDescs.OperandInfo[310] }, // Inst #382 = LOCHIMux + { 6, &SystemZDescs.OperandInfo[304] }, // Inst #381 = LOCG_MemFoldPseudo + { 4, &SystemZDescs.OperandInfo[231] }, // Inst #380 = LMux + { 2, &SystemZDescs.OperandInfo[302] }, // Inst #379 = LLHRMux + { 4, &SystemZDescs.OperandInfo[231] }, // Inst #378 = LLHMux + { 2, &SystemZDescs.OperandInfo[302] }, // Inst #377 = LLCRMux + { 4, &SystemZDescs.OperandInfo[231] }, // Inst #376 = LLCMux + { 4, &SystemZDescs.OperandInfo[231] }, // Inst #375 = LHMux + { 2, &SystemZDescs.OperandInfo[198] }, // Inst #374 = LHIMux + { 2, &SystemZDescs.OperandInfo[300] }, // Inst #373 = LFER + { 2, &SystemZDescs.OperandInfo[298] }, // Inst #372 = LEFR + { 4, &SystemZDescs.OperandInfo[231] }, // Inst #371 = LBMux + { 4, &SystemZDescs.OperandInfo[294] }, // Inst #370 = L128 + { 3, &SystemZDescs.OperandInfo[160] }, // Inst #369 = IILMux + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #368 = IILL64 + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #367 = IILH64 + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #366 = IILF64 + { 3, &SystemZDescs.OperandInfo[160] }, // Inst #365 = IIHMux + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #364 = IIHL64 + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #363 = IIHH64 + { 3, &SystemZDescs.OperandInfo[291] }, // Inst #362 = IIHF64 + { 2, &SystemZDescs.OperandInfo[198] }, // Inst #361 = IIFMux + { 1, &SystemZDescs.OperandInfo[290] }, // Inst #360 = GOT + { 6, &SystemZDescs.OperandInfo[284] }, // Inst #359 = EXRL_Pseudo + { 5, &SystemZDescs.OperandInfo[153] }, // Inst #358 = DEB_MemFoldPseudo + { 5, &SystemZDescs.OperandInfo[144] }, // Inst #357 = DDB_MemFoldPseudo + { 2, &SystemZDescs.OperandInfo[21] }, // Inst #356 = CondTrap + { 6, &SystemZDescs.OperandInfo[278] }, // Inst #355 = CondStoreF64Inv + { 6, &SystemZDescs.OperandInfo[278] }, // Inst #354 = CondStoreF64 + { 6, &SystemZDescs.OperandInfo[272] }, // Inst #353 = CondStoreF32Inv + { 6, &SystemZDescs.OperandInfo[272] }, // Inst #352 = CondStoreF32 + { 6, &SystemZDescs.OperandInfo[260] }, // Inst #351 = CondStore8MuxInv + { 6, &SystemZDescs.OperandInfo[260] }, // Inst #350 = CondStore8Mux + { 6, &SystemZDescs.OperandInfo[254] }, // Inst #349 = CondStore8Inv + { 6, &SystemZDescs.OperandInfo[254] }, // Inst #348 = CondStore8 + { 6, &SystemZDescs.OperandInfo[266] }, // Inst #347 = CondStore64Inv + { 6, &SystemZDescs.OperandInfo[266] }, // Inst #346 = CondStore64 + { 6, &SystemZDescs.OperandInfo[260] }, // Inst #345 = CondStore32MuxInv + { 6, &SystemZDescs.OperandInfo[260] }, // Inst #344 = CondStore32Mux + { 6, &SystemZDescs.OperandInfo[254] }, // Inst #343 = CondStore32Inv + { 6, &SystemZDescs.OperandInfo[254] }, // Inst #342 = CondStore32 + { 6, &SystemZDescs.OperandInfo[260] }, // Inst #341 = CondStore16MuxInv + { 6, &SystemZDescs.OperandInfo[260] }, // Inst #340 = CondStore16Mux + { 6, &SystemZDescs.OperandInfo[254] }, // Inst #339 = CondStore16Inv + { 6, &SystemZDescs.OperandInfo[254] }, // Inst #338 = CondStore16 + { 2, &SystemZDescs.OperandInfo[21] }, // Inst #337 = CondReturn_XPLINK + { 2, &SystemZDescs.OperandInfo[21] }, // Inst #336 = CondReturn + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #335 = CallJG + { 3, &SystemZDescs.OperandInfo[251] }, // Inst #334 = CallBRCL + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #333 = CallBRASL_XPLINK64 + { 1, &SystemZDescs.OperandInfo[250] }, // Inst #332 = CallBRASL + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #331 = CallBR + { 3, &SystemZDescs.OperandInfo[247] }, // Inst #330 = CallBCR + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #329 = CallBASR_XPLINK64 + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #328 = CallBASR_STACKEXT + { 1, &SystemZDescs.OperandInfo[246] }, // Inst #327 = CallBASR + { 3, &SystemZDescs.OperandInfo[239] }, // Inst #326 = CRBReturn + { 4, &SystemZDescs.OperandInfo[235] }, // Inst #325 = CRBCall + { 4, &SystemZDescs.OperandInfo[231] }, // Inst #324 = CMux + { 4, &SystemZDescs.OperandInfo[242] }, // Inst #323 = CLSTLoop + { 3, &SystemZDescs.OperandInfo[239] }, // Inst #322 = CLRBReturn + { 4, &SystemZDescs.OperandInfo[235] }, // Inst #321 = CLRBCall + { 4, &SystemZDescs.OperandInfo[231] }, // Inst #320 = CLMux + { 3, &SystemZDescs.OperandInfo[218] }, // Inst #319 = CLIBReturn + { 4, &SystemZDescs.OperandInfo[214] }, // Inst #318 = CLIBCall + { 3, &SystemZDescs.OperandInfo[211] }, // Inst #317 = CLGRBReturn + { 4, &SystemZDescs.OperandInfo[207] }, // Inst #316 = CLGRBCall + { 3, &SystemZDescs.OperandInfo[204] }, // Inst #315 = CLGIBReturn + { 4, &SystemZDescs.OperandInfo[200] }, // Inst #314 = CLGIBCall + { 2, &SystemZDescs.OperandInfo[198] }, // Inst #313 = CLFIMux + { 5, &SystemZDescs.OperandInfo[226] }, // Inst #312 = CLCReg + { 5, &SystemZDescs.OperandInfo[221] }, // Inst #311 = CLCImm + { 3, &SystemZDescs.OperandInfo[218] }, // Inst #310 = CIBReturn + { 4, &SystemZDescs.OperandInfo[214] }, // Inst #309 = CIBCall + { 2, &SystemZDescs.OperandInfo[198] }, // Inst #308 = CHIMux + { 3, &SystemZDescs.OperandInfo[211] }, // Inst #307 = CGRBReturn + { 4, &SystemZDescs.OperandInfo[207] }, // Inst #306 = CGRBCall + { 3, &SystemZDescs.OperandInfo[204] }, // Inst #305 = CGIBReturn + { 4, &SystemZDescs.OperandInfo[200] }, // Inst #304 = CGIBCall + { 2, &SystemZDescs.OperandInfo[198] }, // Inst #303 = CFIMux + { 5, &SystemZDescs.OperandInfo[171] }, // Inst #302 = A_MemFoldPseudo + { 7, &SystemZDescs.OperandInfo[191] }, // Inst #301 = ATOMIC_SWAPW + { 7, &SystemZDescs.OperandInfo[191] }, // Inst #300 = ATOMIC_LOADW_XR + { 7, &SystemZDescs.OperandInfo[184] }, // Inst #299 = ATOMIC_LOADW_XILF + { 7, &SystemZDescs.OperandInfo[191] }, // Inst #298 = ATOMIC_LOADW_UMIN + { 7, &SystemZDescs.OperandInfo[191] }, // Inst #297 = ATOMIC_LOADW_UMAX + { 7, &SystemZDescs.OperandInfo[191] }, // Inst #296 = ATOMIC_LOADW_SR + { 7, &SystemZDescs.OperandInfo[191] }, // Inst #295 = ATOMIC_LOADW_OR + { 7, &SystemZDescs.OperandInfo[184] }, // Inst #294 = ATOMIC_LOADW_OILH + { 7, &SystemZDescs.OperandInfo[191] }, // Inst #293 = ATOMIC_LOADW_NRi + { 7, &SystemZDescs.OperandInfo[191] }, // Inst #292 = ATOMIC_LOADW_NR + { 7, &SystemZDescs.OperandInfo[184] }, // Inst #291 = ATOMIC_LOADW_NILHi + { 7, &SystemZDescs.OperandInfo[184] }, // Inst #290 = ATOMIC_LOADW_NILH + { 7, &SystemZDescs.OperandInfo[191] }, // Inst #289 = ATOMIC_LOADW_MIN + { 7, &SystemZDescs.OperandInfo[191] }, // Inst #288 = ATOMIC_LOADW_MAX + { 7, &SystemZDescs.OperandInfo[191] }, // Inst #287 = ATOMIC_LOADW_AR + { 7, &SystemZDescs.OperandInfo[184] }, // Inst #286 = ATOMIC_LOADW_AFI + { 8, &SystemZDescs.OperandInfo[176] }, // Inst #285 = ATOMIC_CMP_SWAPW + { 5, &SystemZDescs.OperandInfo[171] }, // Inst #284 = AL_MemFoldPseudo + { 5, &SystemZDescs.OperandInfo[163] }, // Inst #283 = ALG_MemFoldPseudo + { 3, &SystemZDescs.OperandInfo[168] }, // Inst #282 = AHIMuxK + { 3, &SystemZDescs.OperandInfo[160] }, // Inst #281 = AHIMux + { 5, &SystemZDescs.OperandInfo[163] }, // Inst #280 = AG_MemFoldPseudo + { 3, &SystemZDescs.OperandInfo[160] }, // Inst #279 = AFIMux + { 2, &SystemZDescs.OperandInfo[158] }, // Inst #278 = AEXT128 + { 5, &SystemZDescs.OperandInfo[153] }, // Inst #277 = AEB_MemFoldPseudo + { 4, &SystemZDescs.OperandInfo[149] }, // Inst #276 = ADJDYNALLOC + { 2, &SystemZDescs.OperandInfo[21] }, // Inst #275 = ADJCALLSTACKUP + { 2, &SystemZDescs.OperandInfo[21] }, // Inst #274 = ADJCALLSTACKDOWN + { 5, &SystemZDescs.OperandInfo[144] }, // Inst #273 = ADB_MemFoldPseudo + { 4, &SystemZDescs.OperandInfo[140] }, // Inst #272 = ADA_ENTRY_VALUE + { 4, &SystemZDescs.OperandInfo[140] }, // Inst #271 = ADA_ENTRY + { 4, &SystemZDescs.OperandInfo[136] }, // Inst #270 = G_UBFX + { 4, &SystemZDescs.OperandInfo[136] }, // Inst #269 = G_SBFX + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #268 = G_VECREDUCE_UMIN + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #267 = G_VECREDUCE_UMAX + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #266 = G_VECREDUCE_SMIN + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #265 = G_VECREDUCE_SMAX + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #264 = G_VECREDUCE_XOR + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #263 = G_VECREDUCE_OR + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #262 = G_VECREDUCE_AND + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #261 = G_VECREDUCE_MUL + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #260 = G_VECREDUCE_ADD + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #259 = G_VECREDUCE_FMINIMUM + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #258 = G_VECREDUCE_FMAXIMUM + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #257 = G_VECREDUCE_FMIN + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #256 = G_VECREDUCE_FMAX + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #255 = G_VECREDUCE_FMUL + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #254 = G_VECREDUCE_FADD + { 3, &SystemZDescs.OperandInfo[123] }, // Inst #253 = G_VECREDUCE_SEQ_FMUL + { 3, &SystemZDescs.OperandInfo[123] }, // Inst #252 = G_VECREDUCE_SEQ_FADD + { 3, &SystemZDescs.OperandInfo[53] }, // Inst #251 = G_BZERO + { 4, &SystemZDescs.OperandInfo[132] }, // Inst #250 = G_MEMSET + { 4, &SystemZDescs.OperandInfo[132] }, // Inst #249 = G_MEMMOVE + { 3, &SystemZDescs.OperandInfo[123] }, // Inst #248 = G_MEMCPY_INLINE + { 4, &SystemZDescs.OperandInfo[132] }, // Inst #247 = G_MEMCPY + { 2, &SystemZDescs.OperandInfo[130] }, // Inst #246 = G_WRITE_REGISTER + { 2, &SystemZDescs.OperandInfo[51] }, // Inst #245 = G_READ_REGISTER + { 3, &SystemZDescs.OperandInfo[96] }, // Inst #244 = G_STRICT_FLDEXP + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #243 = G_STRICT_FSQRT + { 4, &SystemZDescs.OperandInfo[46] }, // Inst #242 = G_STRICT_FMA + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #241 = G_STRICT_FREM + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #240 = G_STRICT_FDIV + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #239 = G_STRICT_FMUL + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #238 = G_STRICT_FSUB + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #237 = G_STRICT_FADD + { 1, &SystemZDescs.OperandInfo[50] }, // Inst #236 = G_STACKRESTORE + { 1, &SystemZDescs.OperandInfo[50] }, // Inst #235 = G_STACKSAVE + { 3, &SystemZDescs.OperandInfo[64] }, // Inst #234 = G_DYN_STACKALLOC + { 2, &SystemZDescs.OperandInfo[51] }, // Inst #233 = G_JUMP_TABLE + { 2, &SystemZDescs.OperandInfo[51] }, // Inst #232 = G_BLOCK_ADDR + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #231 = G_ADDRSPACE_CAST + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #230 = G_FNEARBYINT + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #229 = G_FRINT + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #228 = G_FFLOOR + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #227 = G_FSQRT + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #226 = G_FSIN + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #225 = G_FCOS + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #224 = G_FCEIL + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #223 = G_BITREVERSE + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #222 = G_BSWAP + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #221 = G_CTPOP + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #220 = G_CTLZ_ZERO_UNDEF + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #219 = G_CTLZ + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #218 = G_CTTZ_ZERO_UNDEF + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #217 = G_CTTZ + { 4, &SystemZDescs.OperandInfo[126] }, // Inst #216 = G_SHUFFLE_VECTOR + { 3, &SystemZDescs.OperandInfo[123] }, // Inst #215 = G_EXTRACT_VECTOR_ELT + { 4, &SystemZDescs.OperandInfo[119] }, // Inst #214 = G_INSERT_VECTOR_ELT + { 3, &SystemZDescs.OperandInfo[116] }, // Inst #213 = G_BRJT + { 1, &SystemZDescs.OperandInfo[0] }, // Inst #212 = G_BR + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #211 = G_LLROUND + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #210 = G_LROUND + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #209 = G_ABS + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #208 = G_UMAX + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #207 = G_UMIN + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #206 = G_SMAX + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #205 = G_SMIN + { 3, &SystemZDescs.OperandInfo[96] }, // Inst #204 = G_PTRMASK + { 3, &SystemZDescs.OperandInfo[96] }, // Inst #203 = G_PTR_ADD + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #202 = G_RESET_FPMODE + { 1, &SystemZDescs.OperandInfo[50] }, // Inst #201 = G_SET_FPMODE + { 1, &SystemZDescs.OperandInfo[50] }, // Inst #200 = G_GET_FPMODE + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #199 = G_RESET_FPENV + { 1, &SystemZDescs.OperandInfo[50] }, // Inst #198 = G_SET_FPENV + { 1, &SystemZDescs.OperandInfo[50] }, // Inst #197 = G_GET_FPENV + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #196 = G_FMAXIMUM + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #195 = G_FMINIMUM + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #194 = G_FMAXNUM_IEEE + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #193 = G_FMINNUM_IEEE + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #192 = G_FMAXNUM + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #191 = G_FMINNUM + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #190 = G_FCANONICALIZE + { 3, &SystemZDescs.OperandInfo[93] }, // Inst #189 = G_IS_FPCLASS + { 3, &SystemZDescs.OperandInfo[96] }, // Inst #188 = G_FCOPYSIGN + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #187 = G_FABS + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #186 = G_UITOFP + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #185 = G_SITOFP + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #184 = G_FPTOUI + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #183 = G_FPTOSI + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #182 = G_FPTRUNC + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #181 = G_FPEXT + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #180 = G_FNEG + { 3, &SystemZDescs.OperandInfo[86] }, // Inst #179 = G_FFREXP + { 3, &SystemZDescs.OperandInfo[96] }, // Inst #178 = G_FLDEXP + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #177 = G_FLOG10 + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #176 = G_FLOG2 + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #175 = G_FLOG + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #174 = G_FEXP10 + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #173 = G_FEXP2 + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #172 = G_FEXP + { 3, &SystemZDescs.OperandInfo[96] }, // Inst #171 = G_FPOWI + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #170 = G_FPOW + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #169 = G_FREM + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #168 = G_FDIV + { 4, &SystemZDescs.OperandInfo[46] }, // Inst #167 = G_FMAD + { 4, &SystemZDescs.OperandInfo[46] }, // Inst #166 = G_FMA + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #165 = G_FMUL + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #164 = G_FSUB + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #163 = G_FADD + { 4, &SystemZDescs.OperandInfo[112] }, // Inst #162 = G_UDIVFIXSAT + { 4, &SystemZDescs.OperandInfo[112] }, // Inst #161 = G_SDIVFIXSAT + { 4, &SystemZDescs.OperandInfo[112] }, // Inst #160 = G_UDIVFIX + { 4, &SystemZDescs.OperandInfo[112] }, // Inst #159 = G_SDIVFIX + { 4, &SystemZDescs.OperandInfo[112] }, // Inst #158 = G_UMULFIXSAT + { 4, &SystemZDescs.OperandInfo[112] }, // Inst #157 = G_SMULFIXSAT + { 4, &SystemZDescs.OperandInfo[112] }, // Inst #156 = G_UMULFIX + { 4, &SystemZDescs.OperandInfo[112] }, // Inst #155 = G_SMULFIX + { 3, &SystemZDescs.OperandInfo[96] }, // Inst #154 = G_SSHLSAT + { 3, &SystemZDescs.OperandInfo[96] }, // Inst #153 = G_USHLSAT + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #152 = G_SSUBSAT + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #151 = G_USUBSAT + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #150 = G_SADDSAT + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #149 = G_UADDSAT + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #148 = G_SMULH + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #147 = G_UMULH + { 4, &SystemZDescs.OperandInfo[82] }, // Inst #146 = G_SMULO + { 4, &SystemZDescs.OperandInfo[82] }, // Inst #145 = G_UMULO + { 5, &SystemZDescs.OperandInfo[107] }, // Inst #144 = G_SSUBE + { 4, &SystemZDescs.OperandInfo[82] }, // Inst #143 = G_SSUBO + { 5, &SystemZDescs.OperandInfo[107] }, // Inst #142 = G_SADDE + { 4, &SystemZDescs.OperandInfo[82] }, // Inst #141 = G_SADDO + { 5, &SystemZDescs.OperandInfo[107] }, // Inst #140 = G_USUBE + { 4, &SystemZDescs.OperandInfo[82] }, // Inst #139 = G_USUBO + { 5, &SystemZDescs.OperandInfo[107] }, // Inst #138 = G_UADDE + { 4, &SystemZDescs.OperandInfo[82] }, // Inst #137 = G_UADDO + { 4, &SystemZDescs.OperandInfo[82] }, // Inst #136 = G_SELECT + { 4, &SystemZDescs.OperandInfo[103] }, // Inst #135 = G_FCMP + { 4, &SystemZDescs.OperandInfo[103] }, // Inst #134 = G_ICMP + { 3, &SystemZDescs.OperandInfo[96] }, // Inst #133 = G_ROTL + { 3, &SystemZDescs.OperandInfo[96] }, // Inst #132 = G_ROTR + { 4, &SystemZDescs.OperandInfo[99] }, // Inst #131 = G_FSHR + { 4, &SystemZDescs.OperandInfo[99] }, // Inst #130 = G_FSHL + { 3, &SystemZDescs.OperandInfo[96] }, // Inst #129 = G_ASHR + { 3, &SystemZDescs.OperandInfo[96] }, // Inst #128 = G_LSHR + { 3, &SystemZDescs.OperandInfo[96] }, // Inst #127 = G_SHL + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #126 = G_ZEXT + { 3, &SystemZDescs.OperandInfo[40] }, // Inst #125 = G_SEXT_INREG + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #124 = G_SEXT + { 3, &SystemZDescs.OperandInfo[93] }, // Inst #123 = G_VAARG + { 1, &SystemZDescs.OperandInfo[50] }, // Inst #122 = G_VASTART + { 2, &SystemZDescs.OperandInfo[51] }, // Inst #121 = G_FCONSTANT + { 2, &SystemZDescs.OperandInfo[51] }, // Inst #120 = G_CONSTANT + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #119 = G_TRUNC + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #118 = G_ANYEXT + { 1, &SystemZDescs.OperandInfo[0] }, // Inst #117 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS + { 1, &SystemZDescs.OperandInfo[0] }, // Inst #116 = G_INTRINSIC_CONVERGENT + { 1, &SystemZDescs.OperandInfo[0] }, // Inst #115 = G_INTRINSIC_W_SIDE_EFFECTS + { 1, &SystemZDescs.OperandInfo[0] }, // Inst #114 = G_INTRINSIC + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #113 = G_INVOKE_REGION_START + { 1, &SystemZDescs.OperandInfo[50] }, // Inst #112 = G_BRINDIRECT + { 2, &SystemZDescs.OperandInfo[51] }, // Inst #111 = G_BRCOND + { 4, &SystemZDescs.OperandInfo[89] }, // Inst #110 = G_PREFETCH + { 2, &SystemZDescs.OperandInfo[21] }, // Inst #109 = G_FENCE + { 3, &SystemZDescs.OperandInfo[86] }, // Inst #108 = G_ATOMICRMW_UDEC_WRAP + { 3, &SystemZDescs.OperandInfo[86] }, // Inst #107 = G_ATOMICRMW_UINC_WRAP + { 3, &SystemZDescs.OperandInfo[86] }, // Inst #106 = G_ATOMICRMW_FMIN + { 3, &SystemZDescs.OperandInfo[86] }, // Inst #105 = G_ATOMICRMW_FMAX + { 3, &SystemZDescs.OperandInfo[86] }, // Inst #104 = G_ATOMICRMW_FSUB + { 3, &SystemZDescs.OperandInfo[86] }, // Inst #103 = G_ATOMICRMW_FADD + { 3, &SystemZDescs.OperandInfo[86] }, // Inst #102 = G_ATOMICRMW_UMIN + { 3, &SystemZDescs.OperandInfo[86] }, // Inst #101 = G_ATOMICRMW_UMAX + { 3, &SystemZDescs.OperandInfo[86] }, // Inst #100 = G_ATOMICRMW_MIN + { 3, &SystemZDescs.OperandInfo[86] }, // Inst #99 = G_ATOMICRMW_MAX + { 3, &SystemZDescs.OperandInfo[86] }, // Inst #98 = G_ATOMICRMW_XOR + { 3, &SystemZDescs.OperandInfo[86] }, // Inst #97 = G_ATOMICRMW_OR + { 3, &SystemZDescs.OperandInfo[86] }, // Inst #96 = G_ATOMICRMW_NAND + { 3, &SystemZDescs.OperandInfo[86] }, // Inst #95 = G_ATOMICRMW_AND + { 3, &SystemZDescs.OperandInfo[86] }, // Inst #94 = G_ATOMICRMW_SUB + { 3, &SystemZDescs.OperandInfo[86] }, // Inst #93 = G_ATOMICRMW_ADD + { 3, &SystemZDescs.OperandInfo[86] }, // Inst #92 = G_ATOMICRMW_XCHG + { 4, &SystemZDescs.OperandInfo[82] }, // Inst #91 = G_ATOMIC_CMPXCHG + { 5, &SystemZDescs.OperandInfo[77] }, // Inst #90 = G_ATOMIC_CMPXCHG_WITH_SUCCESS + { 5, &SystemZDescs.OperandInfo[72] }, // Inst #89 = G_INDEXED_STORE + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #88 = G_STORE + { 5, &SystemZDescs.OperandInfo[67] }, // Inst #87 = G_INDEXED_ZEXTLOAD + { 5, &SystemZDescs.OperandInfo[67] }, // Inst #86 = G_INDEXED_SEXTLOAD + { 5, &SystemZDescs.OperandInfo[67] }, // Inst #85 = G_INDEXED_LOAD + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #84 = G_ZEXTLOAD + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #83 = G_SEXTLOAD + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #82 = G_LOAD + { 1, &SystemZDescs.OperandInfo[50] }, // Inst #81 = G_READCYCLECOUNTER + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #80 = G_INTRINSIC_ROUNDEVEN + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #79 = G_INTRINSIC_LRINT + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #78 = G_INTRINSIC_ROUND + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #77 = G_INTRINSIC_TRUNC + { 3, &SystemZDescs.OperandInfo[64] }, // Inst #76 = G_INTRINSIC_FPTRUNC_ROUND + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #75 = G_CONSTANT_FOLD_BARRIER + { 2, &SystemZDescs.OperandInfo[62] }, // Inst #74 = G_FREEZE + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #73 = G_BITCAST + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #72 = G_INTTOPTR + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #71 = G_PTRTOINT + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #70 = G_CONCAT_VECTORS + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #69 = G_BUILD_VECTOR_TRUNC + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #68 = G_BUILD_VECTOR + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #67 = G_MERGE_VALUES + { 4, &SystemZDescs.OperandInfo[58] }, // Inst #66 = G_INSERT + { 2, &SystemZDescs.OperandInfo[56] }, // Inst #65 = G_UNMERGE_VALUES + { 3, &SystemZDescs.OperandInfo[53] }, // Inst #64 = G_EXTRACT + { 2, &SystemZDescs.OperandInfo[51] }, // Inst #63 = G_CONSTANT_POOL + { 2, &SystemZDescs.OperandInfo[51] }, // Inst #62 = G_GLOBAL_VALUE + { 2, &SystemZDescs.OperandInfo[51] }, // Inst #61 = G_FRAME_INDEX + { 1, &SystemZDescs.OperandInfo[50] }, // Inst #60 = G_PHI + { 1, &SystemZDescs.OperandInfo[50] }, // Inst #59 = G_IMPLICIT_DEF + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #58 = G_XOR + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #57 = G_OR + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #56 = G_AND + { 4, &SystemZDescs.OperandInfo[46] }, // Inst #55 = G_UDIVREM + { 4, &SystemZDescs.OperandInfo[46] }, // Inst #54 = G_SDIVREM + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #53 = G_UREM + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #52 = G_SREM + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #51 = G_UDIV + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #50 = G_SDIV + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #49 = G_MUL + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #48 = G_SUB + { 3, &SystemZDescs.OperandInfo[43] }, // Inst #47 = G_ADD + { 3, &SystemZDescs.OperandInfo[40] }, // Inst #46 = G_ASSERT_ALIGN + { 3, &SystemZDescs.OperandInfo[40] }, // Inst #45 = G_ASSERT_ZEXT + { 3, &SystemZDescs.OperandInfo[40] }, // Inst #44 = G_ASSERT_SEXT + { 1, &SystemZDescs.OperandInfo[1] }, // Inst #43 = JUMP_TABLE_DEBUG_INFO + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #42 = MEMBARRIER + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #41 = ICALL_BRANCH_FUNNEL + { 3, &SystemZDescs.OperandInfo[37] }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL + { 2, &SystemZDescs.OperandInfo[35] }, // Inst #39 = PATCHABLE_EVENT_CALL + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #38 = PATCHABLE_TAIL_CALL + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #37 = PATCHABLE_FUNCTION_EXIT + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #36 = PATCHABLE_RET + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #35 = PATCHABLE_FUNCTION_ENTER + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #34 = PATCHABLE_OP + { 1, &SystemZDescs.OperandInfo[0] }, // Inst #33 = FAULTING_OP + { 2, &SystemZDescs.OperandInfo[33] }, // Inst #32 = LOCAL_ESCAPE + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #31 = STATEPOINT + { 3, &SystemZDescs.OperandInfo[30] }, // Inst #30 = PREALLOCATED_ARG + { 1, &SystemZDescs.OperandInfo[1] }, // Inst #29 = PREALLOCATED_SETUP + { 1, &SystemZDescs.OperandInfo[29] }, // Inst #28 = LOAD_STACK_GUARD + { 6, &SystemZDescs.OperandInfo[23] }, // Inst #27 = PATCHPOINT + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #26 = FENTRY_CALL + { 2, &SystemZDescs.OperandInfo[21] }, // Inst #25 = STACKMAP + { 2, &SystemZDescs.OperandInfo[19] }, // Inst #24 = ARITH_FENCE + { 4, &SystemZDescs.OperandInfo[15] }, // Inst #23 = PSEUDO_PROBE + { 1, &SystemZDescs.OperandInfo[1] }, // Inst #22 = LIFETIME_END + { 1, &SystemZDescs.OperandInfo[1] }, // Inst #21 = LIFETIME_START + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #20 = BUNDLE + { 2, &SystemZDescs.OperandInfo[13] }, // Inst #19 = COPY + { 2, &SystemZDescs.OperandInfo[13] }, // Inst #18 = REG_SEQUENCE + { 1, &SystemZDescs.OperandInfo[0] }, // Inst #17 = DBG_LABEL + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #16 = DBG_PHI + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #15 = DBG_INSTR_REF + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #14 = DBG_VALUE_LIST + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #13 = DBG_VALUE + { 3, &SystemZDescs.OperandInfo[2] }, // Inst #12 = COPY_TO_REGCLASS + { 4, &SystemZDescs.OperandInfo[9] }, // Inst #11 = SUBREG_TO_REG + { 1, &SystemZDescs.OperandInfo[0] }, // Inst #10 = IMPLICIT_DEF + { 4, &SystemZDescs.OperandInfo[5] }, // Inst #9 = INSERT_SUBREG + { 3, &SystemZDescs.OperandInfo[2] }, // Inst #8 = EXTRACT_SUBREG + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #7 = KILL + { 1, &SystemZDescs.OperandInfo[1] }, // Inst #6 = ANNOTATION_LABEL + { 1, &SystemZDescs.OperandInfo[1] }, // Inst #5 = GC_LABEL + { 1, &SystemZDescs.OperandInfo[1] }, // Inst #4 = EH_LABEL + { 1, &SystemZDescs.OperandInfo[1] }, // Inst #3 = CFI_INSTRUCTION + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #2 = INLINEASM_BR + { 0, &SystemZDescs.OperandInfo[1] }, // Inst #1 = INLINEASM + { 1, &SystemZDescs.OperandInfo[0] }, // Inst #0 = PHI + }, { + /* 0 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 1 */ + /* 1 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 2 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 5 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 9 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 13 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, + /* 15 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 19 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) }, + /* 21 */ { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 23 */ { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, + /* 29 */ { 0, 0|(1<, 2013-2019 */ - - #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM enum { SystemZ_NoRegister, SystemZ_CC = 1, - SystemZ_A0 = 2, - SystemZ_A1 = 3, - SystemZ_A2 = 4, - SystemZ_A3 = 5, - SystemZ_A4 = 6, - SystemZ_A5 = 7, - SystemZ_A6 = 8, - SystemZ_A7 = 9, - SystemZ_A8 = 10, - SystemZ_A9 = 11, - SystemZ_A10 = 12, - SystemZ_A11 = 13, - SystemZ_A12 = 14, - SystemZ_A13 = 15, - SystemZ_A14 = 16, - SystemZ_A15 = 17, - SystemZ_C0 = 18, - SystemZ_C1 = 19, - SystemZ_C2 = 20, - SystemZ_C3 = 21, - SystemZ_C4 = 22, - SystemZ_C5 = 23, - SystemZ_C6 = 24, - SystemZ_C7 = 25, - SystemZ_C8 = 26, - SystemZ_C9 = 27, - SystemZ_C10 = 28, - SystemZ_C11 = 29, - SystemZ_C12 = 30, - SystemZ_C13 = 31, - SystemZ_C14 = 32, - SystemZ_C15 = 33, - SystemZ_V0 = 34, - SystemZ_V1 = 35, - SystemZ_V2 = 36, - SystemZ_V3 = 37, - SystemZ_V4 = 38, - SystemZ_V5 = 39, - SystemZ_V6 = 40, - SystemZ_V7 = 41, - SystemZ_V8 = 42, - SystemZ_V9 = 43, - SystemZ_V10 = 44, - SystemZ_V11 = 45, - SystemZ_V12 = 46, - SystemZ_V13 = 47, - SystemZ_V14 = 48, - SystemZ_V15 = 49, - SystemZ_V16 = 50, - SystemZ_V17 = 51, - SystemZ_V18 = 52, - SystemZ_V19 = 53, - SystemZ_V20 = 54, - SystemZ_V21 = 55, - SystemZ_V22 = 56, - SystemZ_V23 = 57, - SystemZ_V24 = 58, - SystemZ_V25 = 59, - SystemZ_V26 = 60, - SystemZ_V27 = 61, - SystemZ_V28 = 62, - SystemZ_V29 = 63, - SystemZ_V30 = 64, - SystemZ_V31 = 65, - SystemZ_F0D = 66, - SystemZ_F1D = 67, - SystemZ_F2D = 68, - SystemZ_F3D = 69, - SystemZ_F4D = 70, - SystemZ_F5D = 71, - SystemZ_F6D = 72, - SystemZ_F7D = 73, - SystemZ_F8D = 74, - SystemZ_F9D = 75, - SystemZ_F10D = 76, - SystemZ_F11D = 77, - SystemZ_F12D = 78, - SystemZ_F13D = 79, - SystemZ_F14D = 80, - SystemZ_F15D = 81, - SystemZ_F16D = 82, - SystemZ_F17D = 83, - SystemZ_F18D = 84, - SystemZ_F19D = 85, - SystemZ_F20D = 86, - SystemZ_F21D = 87, - SystemZ_F22D = 88, - SystemZ_F23D = 89, - SystemZ_F24D = 90, - SystemZ_F25D = 91, - SystemZ_F26D = 92, - SystemZ_F27D = 93, - SystemZ_F28D = 94, - SystemZ_F29D = 95, - SystemZ_F30D = 96, - SystemZ_F31D = 97, - SystemZ_F0Q = 98, - SystemZ_F1Q = 99, - SystemZ_F4Q = 100, - SystemZ_F5Q = 101, - SystemZ_F8Q = 102, - SystemZ_F9Q = 103, - SystemZ_F12Q = 104, - SystemZ_F13Q = 105, - SystemZ_F0S = 106, - SystemZ_F1S = 107, - SystemZ_F2S = 108, - SystemZ_F3S = 109, - SystemZ_F4S = 110, - SystemZ_F5S = 111, - SystemZ_F6S = 112, - SystemZ_F7S = 113, - SystemZ_F8S = 114, - SystemZ_F9S = 115, - SystemZ_F10S = 116, - SystemZ_F11S = 117, - SystemZ_F12S = 118, - SystemZ_F13S = 119, - SystemZ_F14S = 120, - SystemZ_F15S = 121, - SystemZ_F16S = 122, - SystemZ_F17S = 123, - SystemZ_F18S = 124, - SystemZ_F19S = 125, - SystemZ_F20S = 126, - SystemZ_F21S = 127, - SystemZ_F22S = 128, - SystemZ_F23S = 129, - SystemZ_F24S = 130, - SystemZ_F25S = 131, - SystemZ_F26S = 132, - SystemZ_F27S = 133, - SystemZ_F28S = 134, - SystemZ_F29S = 135, - SystemZ_F30S = 136, - SystemZ_F31S = 137, - SystemZ_R0D = 138, - SystemZ_R1D = 139, - SystemZ_R2D = 140, - SystemZ_R3D = 141, - SystemZ_R4D = 142, - SystemZ_R5D = 143, - SystemZ_R6D = 144, - SystemZ_R7D = 145, - SystemZ_R8D = 146, - SystemZ_R9D = 147, - SystemZ_R10D = 148, - SystemZ_R11D = 149, - SystemZ_R12D = 150, - SystemZ_R13D = 151, - SystemZ_R14D = 152, - SystemZ_R15D = 153, - SystemZ_R0H = 154, - SystemZ_R1H = 155, - SystemZ_R2H = 156, - SystemZ_R3H = 157, - SystemZ_R4H = 158, - SystemZ_R5H = 159, - SystemZ_R6H = 160, - SystemZ_R7H = 161, - SystemZ_R8H = 162, - SystemZ_R9H = 163, - SystemZ_R10H = 164, - SystemZ_R11H = 165, - SystemZ_R12H = 166, - SystemZ_R13H = 167, - SystemZ_R14H = 168, - SystemZ_R15H = 169, - SystemZ_R0L = 170, - SystemZ_R1L = 171, - SystemZ_R2L = 172, - SystemZ_R3L = 173, - SystemZ_R4L = 174, - SystemZ_R5L = 175, - SystemZ_R6L = 176, - SystemZ_R7L = 177, - SystemZ_R8L = 178, - SystemZ_R9L = 179, - SystemZ_R10L = 180, - SystemZ_R11L = 181, - SystemZ_R12L = 182, - SystemZ_R13L = 183, - SystemZ_R14L = 184, - SystemZ_R15L = 185, - SystemZ_R0Q = 186, - SystemZ_R2Q = 187, - SystemZ_R4Q = 188, - SystemZ_R6Q = 189, - SystemZ_R8Q = 190, - SystemZ_R10Q = 191, - SystemZ_R12Q = 192, - SystemZ_R14Q = 193, - SystemZ_NUM_TARGET_REGS // 194 + SystemZ_FPC = 2, + SystemZ_A0 = 3, + SystemZ_A1 = 4, + SystemZ_A2 = 5, + SystemZ_A3 = 6, + SystemZ_A4 = 7, + SystemZ_A5 = 8, + SystemZ_A6 = 9, + SystemZ_A7 = 10, + SystemZ_A8 = 11, + SystemZ_A9 = 12, + SystemZ_A10 = 13, + SystemZ_A11 = 14, + SystemZ_A12 = 15, + SystemZ_A13 = 16, + SystemZ_A14 = 17, + SystemZ_A15 = 18, + SystemZ_C0 = 19, + SystemZ_C1 = 20, + SystemZ_C2 = 21, + SystemZ_C3 = 22, + SystemZ_C4 = 23, + SystemZ_C5 = 24, + SystemZ_C6 = 25, + SystemZ_C7 = 26, + SystemZ_C8 = 27, + SystemZ_C9 = 28, + SystemZ_C10 = 29, + SystemZ_C11 = 30, + SystemZ_C12 = 31, + SystemZ_C13 = 32, + SystemZ_C14 = 33, + SystemZ_C15 = 34, + SystemZ_V0 = 35, + SystemZ_V1 = 36, + SystemZ_V2 = 37, + SystemZ_V3 = 38, + SystemZ_V4 = 39, + SystemZ_V5 = 40, + SystemZ_V6 = 41, + SystemZ_V7 = 42, + SystemZ_V8 = 43, + SystemZ_V9 = 44, + SystemZ_V10 = 45, + SystemZ_V11 = 46, + SystemZ_V12 = 47, + SystemZ_V13 = 48, + SystemZ_V14 = 49, + SystemZ_V15 = 50, + SystemZ_V16 = 51, + SystemZ_V17 = 52, + SystemZ_V18 = 53, + SystemZ_V19 = 54, + SystemZ_V20 = 55, + SystemZ_V21 = 56, + SystemZ_V22 = 57, + SystemZ_V23 = 58, + SystemZ_V24 = 59, + SystemZ_V25 = 60, + SystemZ_V26 = 61, + SystemZ_V27 = 62, + SystemZ_V28 = 63, + SystemZ_V29 = 64, + SystemZ_V30 = 65, + SystemZ_V31 = 66, + SystemZ_F0D = 67, + SystemZ_F1D = 68, + SystemZ_F2D = 69, + SystemZ_F3D = 70, + SystemZ_F4D = 71, + SystemZ_F5D = 72, + SystemZ_F6D = 73, + SystemZ_F7D = 74, + SystemZ_F8D = 75, + SystemZ_F9D = 76, + SystemZ_F10D = 77, + SystemZ_F11D = 78, + SystemZ_F12D = 79, + SystemZ_F13D = 80, + SystemZ_F14D = 81, + SystemZ_F15D = 82, + SystemZ_F16D = 83, + SystemZ_F17D = 84, + SystemZ_F18D = 85, + SystemZ_F19D = 86, + SystemZ_F20D = 87, + SystemZ_F21D = 88, + SystemZ_F22D = 89, + SystemZ_F23D = 90, + SystemZ_F24D = 91, + SystemZ_F25D = 92, + SystemZ_F26D = 93, + SystemZ_F27D = 94, + SystemZ_F28D = 95, + SystemZ_F29D = 96, + SystemZ_F30D = 97, + SystemZ_F31D = 98, + SystemZ_F0Q = 99, + SystemZ_F1Q = 100, + SystemZ_F4Q = 101, + SystemZ_F5Q = 102, + SystemZ_F8Q = 103, + SystemZ_F9Q = 104, + SystemZ_F12Q = 105, + SystemZ_F13Q = 106, + SystemZ_F0S = 107, + SystemZ_F1S = 108, + SystemZ_F2S = 109, + SystemZ_F3S = 110, + SystemZ_F4S = 111, + SystemZ_F5S = 112, + SystemZ_F6S = 113, + SystemZ_F7S = 114, + SystemZ_F8S = 115, + SystemZ_F9S = 116, + SystemZ_F10S = 117, + SystemZ_F11S = 118, + SystemZ_F12S = 119, + SystemZ_F13S = 120, + SystemZ_F14S = 121, + SystemZ_F15S = 122, + SystemZ_F16S = 123, + SystemZ_F17S = 124, + SystemZ_F18S = 125, + SystemZ_F19S = 126, + SystemZ_F20S = 127, + SystemZ_F21S = 128, + SystemZ_F22S = 129, + SystemZ_F23S = 130, + SystemZ_F24S = 131, + SystemZ_F25S = 132, + SystemZ_F26S = 133, + SystemZ_F27S = 134, + SystemZ_F28S = 135, + SystemZ_F29S = 136, + SystemZ_F30S = 137, + SystemZ_F31S = 138, + SystemZ_R0D = 139, + SystemZ_R1D = 140, + SystemZ_R2D = 141, + SystemZ_R3D = 142, + SystemZ_R4D = 143, + SystemZ_R5D = 144, + SystemZ_R6D = 145, + SystemZ_R7D = 146, + SystemZ_R8D = 147, + SystemZ_R9D = 148, + SystemZ_R10D = 149, + SystemZ_R11D = 150, + SystemZ_R12D = 151, + SystemZ_R13D = 152, + SystemZ_R14D = 153, + SystemZ_R15D = 154, + SystemZ_R0H = 155, + SystemZ_R1H = 156, + SystemZ_R2H = 157, + SystemZ_R3H = 158, + SystemZ_R4H = 159, + SystemZ_R5H = 160, + SystemZ_R6H = 161, + SystemZ_R7H = 162, + SystemZ_R8H = 163, + SystemZ_R9H = 164, + SystemZ_R10H = 165, + SystemZ_R11H = 166, + SystemZ_R12H = 167, + SystemZ_R13H = 168, + SystemZ_R14H = 169, + SystemZ_R15H = 170, + SystemZ_R0L = 171, + SystemZ_R1L = 172, + SystemZ_R2L = 173, + SystemZ_R3L = 174, + SystemZ_R4L = 175, + SystemZ_R5L = 176, + SystemZ_R6L = 177, + SystemZ_R7L = 178, + SystemZ_R8L = 179, + SystemZ_R9L = 180, + SystemZ_R10L = 181, + SystemZ_R11L = 182, + SystemZ_R12L = 183, + SystemZ_R13L = 184, + SystemZ_R14L = 185, + SystemZ_R15L = 186, + SystemZ_R0Q = 187, + SystemZ_R2Q = 188, + SystemZ_R4Q = 189, + SystemZ_R6Q = 190, + SystemZ_R8Q = 191, + SystemZ_R10Q = 192, + SystemZ_R12Q = 193, + SystemZ_R14Q = 194, + NUM_TARGET_REGS // 195 }; // Register classes + enum { SystemZ_GRX32BitRegClassID = 0, SystemZ_VR32BitRegClassID = 1, @@ -221,497 +211,518 @@ enum { SystemZ_GRH32BitRegClassID = 5, SystemZ_ADDR32BitRegClassID = 6, SystemZ_CCRRegClassID = 7, - SystemZ_AnyRegBitRegClassID = 8, - SystemZ_AnyRegBit_with_subreg_r32RegClassID = 9, - SystemZ_VR64BitRegClassID = 10, - SystemZ_AnyRegBit_with_subreg_r64RegClassID = 11, - SystemZ_CR64BitRegClassID = 12, - SystemZ_FP64BitRegClassID = 13, - SystemZ_GR64BitRegClassID = 14, - SystemZ_ADDR64BitRegClassID = 15, - SystemZ_VR128BitRegClassID = 16, - SystemZ_VF128BitRegClassID = 17, - SystemZ_FP128BitRegClassID = 18, - SystemZ_GR128BitRegClassID = 19, - SystemZ_ADDR128BitRegClassID = 20, + SystemZ_FPCRegsRegClassID = 8, + SystemZ_AnyRegBitRegClassID = 9, + SystemZ_AnyRegBit_with_subreg_h32_in_FP32BitRegClassID = 10, + SystemZ_VR64BitRegClassID = 11, + SystemZ_AnyRegBit_with_subreg_h64RegClassID = 12, + SystemZ_CR64BitRegClassID = 13, + SystemZ_FP64BitRegClassID = 14, + SystemZ_GR64BitRegClassID = 15, + SystemZ_ADDR64BitRegClassID = 16, + SystemZ_VR128BitRegClassID = 17, + SystemZ_VF128BitRegClassID = 18, + SystemZ_FP128BitRegClassID = 19, + SystemZ_GR128BitRegClassID = 20, + SystemZ_ADDR128BitRegClassID = 21, + +}; + +// Subregister indices + +enum { + SystemZ_NoSubRegister, + SystemZ_subreg_h32, // 1 + SystemZ_subreg_h64, // 2 + SystemZ_subreg_l32, // 3 + SystemZ_subreg_l64, // 4 + SystemZ_subreg_lh32, // 5 + SystemZ_subreg_ll32, // 6 + SystemZ_NUM_TARGET_SUBREGS }; #endif // GET_REGINFO_ENUM -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* MC Register Information *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC static const MCPhysReg SystemZRegDiffLists[] = { - /* 0 */ -679, 1, 1, 1, 0, - /* 5 */ -211, 1, 0, - /* 8 */ -65, 2, 0, - /* 11 */ -63, 2, 0, - /* 14 */ -61, 2, 0, - /* 17 */ -59, 2, 0, - /* 20 */ 32, 40, 0, - /* 23 */ -30, 40, -42, 40, 0, - /* 28 */ -28, 40, -42, 40, 0, - /* 33 */ -26, 40, -42, 40, 0, - /* 38 */ -24, 40, -42, 40, 0, - /* 43 */ -32, 40, 0, - /* 46 */ -16, 40, 0, - /* 49 */ -32, 41, 0, - /* 52 */ -16, 41, 0, - /* 55 */ -32, 42, 0, - /* 58 */ -16, 42, 0, - /* 61 */ -32, 43, 0, - /* 64 */ -16, 43, 0, - /* 67 */ -32, 44, 0, - /* 70 */ -16, 44, 0, - /* 73 */ -32, 45, 0, - /* 76 */ -16, 45, 0, - /* 79 */ -32, 46, 0, - /* 82 */ -16, 46, 0, - /* 85 */ -32, 47, 0, - /* 88 */ -16, 47, 0, - /* 91 */ -32, 48, 0, - /* 94 */ -16, 48, 0, - /* 97 */ -40, -32, 56, 0, - /* 101 */ -40, -32, 58, 0, - /* 105 */ -40, -32, 60, 0, - /* 109 */ -40, -32, 62, 0, - /* 113 */ -40, -32, 64, 0, - /* 117 */ -275, 0, - /* 119 */ -242, 0, - /* 121 */ -73, 0, - /* 123 */ -33, 0, - /* 125 */ -40, -32, 0, - /* 128 */ -47, 32, -16, -17, 32, -16, 0, - /* 135 */ -46, 32, -16, -17, 32, -16, 0, - /* 142 */ -45, 32, -16, -17, 32, -16, 0, - /* 149 */ -44, 32, -16, -17, 32, -16, 0, - /* 156 */ -43, 32, -16, -17, 32, -16, 0, - /* 163 */ -42, 32, -16, -17, 32, -16, 0, - /* 170 */ -41, 32, -16, -17, 32, -16, 0, - /* 177 */ -40, 32, -16, -17, 32, -16, 0, - /* 184 */ -1, 0, + /* 0 */ -40, -32, 0, + /* 3 */ -48, 32, -16, -15, 32, -16, 0, + /* 10 */ -47, 32, -16, -15, 32, -16, 0, + /* 17 */ -46, 32, -16, -15, 32, -16, 0, + /* 24 */ -45, 32, -16, -15, 32, -16, 0, + /* 31 */ -44, 32, -16, -15, 32, -16, 0, + /* 38 */ -43, 32, -16, -15, 32, -16, 0, + /* 45 */ -42, 32, -16, -15, 32, -16, 0, + /* 52 */ -41, 32, -16, -15, 32, -16, 0, + /* 59 */ 1, 1, 1, 0, + /* 63 */ 2, 0, + /* 65 */ -32, 40, -38, 40, 0, + /* 70 */ -30, 40, -38, 40, 0, + /* 75 */ -28, 40, -38, 40, 0, + /* 80 */ -26, 40, -38, 40, 0, + /* 85 */ -32, 40, 0, + /* 88 */ -16, 40, 0, + /* 91 */ 32, 40, 0, + /* 94 */ -32, 41, 0, + /* 97 */ -16, 41, 0, + /* 100 */ -32, 42, 0, + /* 103 */ -16, 42, 0, + /* 106 */ -32, 43, 0, + /* 109 */ -16, 43, 0, + /* 112 */ -32, 44, 0, + /* 115 */ -16, 44, 0, + /* 118 */ -32, 45, 0, + /* 121 */ -16, 45, 0, + /* 124 */ -32, 46, 0, + /* 127 */ -16, 46, 0, + /* 130 */ -32, 47, 0, + /* 133 */ -16, 47, 0, + /* 136 */ -32, 48, 0, + /* 139 */ -16, 48, 0, + /* 142 */ -40, -32, 56, 0, + /* 146 */ -40, -32, 58, 0, + /* 150 */ -40, -32, 60, 0, + /* 154 */ -40, -32, 62, 0, + /* 158 */ -40, -32, 64, 0, }; static const uint16_t SystemZSubRegIdxLists[] = { - /* 0 */ 6, 1, 0, - /* 3 */ 7, 6, 1, 2, 4, 3, 0, - /* 10 */ 7, 8, 2, 5, 0, - /* 15 */ 9, 8, 0, + /* 0 */ 2, 1, 0, + /* 3 */ 3, 1, 0, + /* 6 */ 2, 1, 4, 5, 0, + /* 11 */ 2, 3, 1, 4, 6, 5, 0, }; static const MCRegisterDesc SystemZRegDesc[] = { // Descriptors { 3, 0, 0, 0, 0, 0 }, - { 226, 4, 4, 2, 2945, 0 }, - { 20, 4, 4, 2, 2945, 0 }, - { 49, 4, 4, 2, 2945, 0 }, - { 74, 4, 4, 2, 2945, 0 }, - { 99, 4, 4, 2, 2945, 0 }, - { 124, 4, 4, 2, 2945, 0 }, - { 149, 4, 4, 2, 2945, 0 }, - { 166, 4, 4, 2, 2945, 0 }, - { 183, 4, 4, 2, 2945, 0 }, - { 200, 4, 4, 2, 2945, 0 }, - { 217, 4, 4, 2, 2945, 0 }, - { 0, 4, 4, 2, 2945, 0 }, - { 29, 4, 4, 2, 2945, 0 }, - { 58, 4, 4, 2, 2945, 0 }, - { 83, 4, 4, 2, 2945, 0 }, - { 108, 4, 4, 2, 2945, 0 }, - { 133, 4, 4, 2, 2945, 0 }, - { 23, 4, 4, 2, 2945, 0 }, - { 52, 4, 4, 2, 2945, 0 }, - { 77, 4, 4, 2, 2945, 0 }, - { 102, 4, 4, 2, 2945, 0 }, - { 127, 4, 4, 2, 2945, 0 }, - { 152, 4, 4, 2, 2945, 0 }, - { 169, 4, 4, 2, 2945, 0 }, - { 186, 4, 4, 2, 2945, 0 }, - { 203, 4, 4, 2, 2945, 0 }, - { 220, 4, 4, 2, 2945, 0 }, - { 4, 4, 4, 2, 2945, 0 }, - { 33, 4, 4, 2, 2945, 0 }, - { 62, 4, 4, 2, 2945, 0 }, - { 87, 4, 4, 2, 2945, 0 }, - { 112, 4, 4, 2, 2945, 0 }, - { 137, 4, 4, 2, 2945, 0 }, - { 26, 20, 4, 15, 2945, 8 }, - { 55, 20, 4, 15, 2945, 8 }, - { 80, 20, 4, 15, 2945, 8 }, - { 105, 20, 4, 15, 2945, 8 }, - { 130, 20, 4, 15, 2945, 8 }, - { 155, 20, 4, 15, 2945, 8 }, - { 172, 20, 4, 15, 2945, 8 }, - { 189, 20, 4, 15, 2945, 8 }, - { 206, 20, 4, 15, 2945, 8 }, - { 223, 20, 4, 15, 2945, 8 }, - { 8, 20, 4, 15, 2945, 8 }, - { 37, 20, 4, 15, 2945, 8 }, - { 66, 20, 4, 15, 2945, 8 }, - { 91, 20, 4, 15, 2945, 8 }, - { 116, 20, 4, 15, 2945, 8 }, - { 141, 20, 4, 15, 2945, 8 }, - { 158, 20, 4, 15, 2945, 8 }, - { 175, 20, 4, 15, 2945, 8 }, - { 192, 20, 4, 15, 2945, 8 }, - { 209, 20, 4, 15, 2945, 8 }, - { 12, 20, 4, 15, 2945, 8 }, - { 41, 20, 4, 15, 2945, 8 }, - { 70, 20, 4, 15, 2945, 8 }, - { 95, 20, 4, 15, 2945, 8 }, - { 120, 20, 4, 15, 2945, 8 }, - { 145, 20, 4, 15, 2945, 8 }, - { 162, 20, 4, 15, 2945, 8 }, - { 179, 20, 4, 15, 2945, 8 }, - { 196, 20, 4, 15, 2945, 8 }, - { 213, 20, 4, 15, 2945, 8 }, - { 16, 20, 4, 15, 2945, 8 }, - { 45, 20, 4, 15, 2945, 8 }, - { 249, 21, 114, 16, 1969, 8 }, - { 277, 21, 114, 16, 1969, 8 }, - { 300, 21, 110, 16, 1969, 8 }, - { 323, 21, 110, 16, 1969, 8 }, - { 346, 21, 110, 16, 1969, 8 }, - { 369, 21, 110, 16, 1969, 8 }, - { 387, 21, 106, 16, 1969, 8 }, - { 405, 21, 106, 16, 1969, 8 }, - { 423, 21, 106, 16, 1969, 8 }, - { 441, 21, 106, 16, 1969, 8 }, - { 229, 21, 102, 16, 1969, 8 }, - { 257, 21, 102, 16, 1969, 8 }, - { 285, 21, 102, 16, 1969, 8 }, - { 308, 21, 102, 16, 1969, 8 }, - { 331, 21, 98, 16, 1969, 8 }, - { 354, 21, 98, 16, 1969, 8 }, - { 377, 21, 126, 16, 1969, 8 }, - { 395, 21, 126, 16, 1969, 8 }, - { 413, 21, 126, 16, 1969, 8 }, - { 431, 21, 126, 16, 1969, 8 }, - { 239, 21, 126, 16, 1969, 8 }, - { 267, 21, 126, 16, 1969, 8 }, - { 295, 21, 126, 16, 1969, 8 }, - { 318, 21, 126, 16, 1969, 8 }, - { 341, 21, 126, 16, 1969, 8 }, - { 364, 21, 126, 16, 1969, 8 }, - { 382, 21, 126, 16, 1969, 8 }, - { 400, 21, 126, 16, 1969, 8 }, - { 418, 21, 126, 16, 1969, 8 }, - { 436, 21, 126, 16, 1969, 8 }, - { 244, 21, 126, 16, 1969, 8 }, - { 272, 21, 126, 16, 1969, 8 }, - { 594, 23, 4, 10, 129, 7 }, - { 602, 23, 4, 10, 129, 7 }, - { 630, 28, 4, 10, 177, 7 }, - { 638, 28, 4, 10, 177, 7 }, - { 646, 33, 4, 10, 225, 7 }, - { 654, 33, 4, 10, 225, 7 }, - { 606, 38, 4, 10, 273, 7 }, - { 620, 38, 4, 10, 273, 7 }, - { 673, 4, 113, 2, 1937, 0 }, - { 692, 4, 113, 2, 1937, 0 }, - { 706, 4, 109, 2, 1937, 0 }, - { 720, 4, 109, 2, 1937, 0 }, - { 734, 4, 109, 2, 1937, 0 }, - { 748, 4, 109, 2, 1937, 0 }, - { 762, 4, 105, 2, 1937, 0 }, - { 776, 4, 105, 2, 1937, 0 }, - { 790, 4, 105, 2, 1937, 0 }, - { 804, 4, 105, 2, 1937, 0 }, - { 658, 4, 101, 2, 1937, 0 }, - { 677, 4, 101, 2, 1937, 0 }, - { 696, 4, 101, 2, 1937, 0 }, - { 710, 4, 101, 2, 1937, 0 }, - { 724, 4, 97, 2, 1937, 0 }, - { 738, 4, 97, 2, 1937, 0 }, - { 752, 4, 125, 2, 1937, 0 }, - { 766, 4, 125, 2, 1937, 0 }, - { 780, 4, 125, 2, 1937, 0 }, - { 794, 4, 125, 2, 1937, 0 }, - { 663, 4, 125, 2, 1937, 0 }, - { 682, 4, 125, 2, 1937, 0 }, - { 701, 4, 125, 2, 1937, 0 }, - { 715, 4, 125, 2, 1937, 0 }, - { 729, 4, 125, 2, 1937, 0 }, - { 743, 4, 125, 2, 1937, 0 }, - { 757, 4, 125, 2, 1937, 0 }, - { 771, 4, 125, 2, 1937, 0 }, - { 785, 4, 125, 2, 1937, 0 }, - { 799, 4, 125, 2, 1937, 0 }, - { 668, 4, 125, 2, 1937, 0 }, - { 687, 4, 125, 2, 1937, 0 }, - { 253, 132, 92, 0, 82, 4 }, - { 281, 132, 86, 0, 82, 4 }, - { 304, 132, 86, 0, 82, 4 }, - { 327, 132, 80, 0, 82, 4 }, - { 350, 132, 80, 0, 82, 4 }, - { 373, 132, 74, 0, 82, 4 }, - { 391, 132, 74, 0, 82, 4 }, - { 409, 132, 68, 0, 82, 4 }, - { 427, 132, 68, 0, 82, 4 }, - { 445, 132, 62, 0, 82, 4 }, - { 234, 132, 62, 0, 82, 4 }, - { 262, 132, 56, 0, 82, 4 }, - { 290, 132, 56, 0, 82, 4 }, - { 313, 132, 50, 0, 82, 4 }, - { 336, 132, 50, 0, 82, 4 }, - { 359, 132, 21, 0, 82, 4 }, - { 454, 4, 94, 2, 1906, 0 }, - { 463, 4, 88, 2, 1906, 0 }, - { 472, 4, 88, 2, 1906, 0 }, - { 481, 4, 82, 2, 1906, 0 }, - { 490, 4, 82, 2, 1906, 0 }, - { 499, 4, 76, 2, 1906, 0 }, - { 503, 4, 76, 2, 1906, 0 }, - { 507, 4, 70, 2, 1906, 0 }, - { 511, 4, 70, 2, 1906, 0 }, - { 515, 4, 64, 2, 1906, 0 }, - { 449, 4, 64, 2, 1906, 0 }, - { 458, 4, 58, 2, 1906, 0 }, - { 467, 4, 58, 2, 1906, 0 }, - { 476, 4, 52, 2, 1906, 0 }, - { 485, 4, 52, 2, 1906, 0 }, - { 494, 4, 46, 2, 1906, 0 }, - { 524, 4, 91, 2, 1874, 0 }, - { 533, 4, 85, 2, 1874, 0 }, - { 542, 4, 85, 2, 1874, 0 }, - { 551, 4, 79, 2, 1874, 0 }, - { 560, 4, 79, 2, 1874, 0 }, - { 569, 4, 73, 2, 1874, 0 }, - { 573, 4, 73, 2, 1874, 0 }, - { 577, 4, 67, 2, 1874, 0 }, - { 581, 4, 67, 2, 1874, 0 }, - { 585, 4, 61, 2, 1874, 0 }, - { 519, 4, 61, 2, 1874, 0 }, - { 528, 4, 55, 2, 1874, 0 }, - { 537, 4, 55, 2, 1874, 0 }, - { 546, 4, 49, 2, 1874, 0 }, - { 555, 4, 49, 2, 1874, 0 }, - { 564, 4, 43, 2, 1874, 0 }, - { 598, 128, 4, 3, 4, 2 }, - { 616, 135, 4, 3, 4, 2 }, - { 634, 142, 4, 3, 4, 2 }, - { 642, 149, 4, 3, 4, 2 }, - { 650, 156, 4, 3, 4, 2 }, - { 589, 163, 4, 3, 4, 2 }, - { 611, 170, 4, 3, 4, 2 }, - { 625, 177, 4, 3, 4, 2 }, + { 226, 2, 2, 2, 8192, 11 }, + { 229, 2, 2, 2, 8193, 11 }, + { 20, 2, 2, 2, 8194, 11 }, + { 49, 2, 2, 2, 8195, 11 }, + { 74, 2, 2, 2, 8196, 11 }, + { 99, 2, 2, 2, 8197, 11 }, + { 124, 2, 2, 2, 8198, 11 }, + { 149, 2, 2, 2, 8199, 11 }, + { 166, 2, 2, 2, 8200, 11 }, + { 183, 2, 2, 2, 8201, 11 }, + { 200, 2, 2, 2, 8202, 11 }, + { 217, 2, 2, 2, 8203, 11 }, + { 0, 2, 2, 2, 8204, 11 }, + { 29, 2, 2, 2, 8205, 11 }, + { 58, 2, 2, 2, 8206, 11 }, + { 83, 2, 2, 2, 8207, 11 }, + { 108, 2, 2, 2, 8208, 11 }, + { 133, 2, 2, 2, 8209, 11 }, + { 23, 2, 2, 2, 8210, 11 }, + { 52, 2, 2, 2, 8211, 11 }, + { 77, 2, 2, 2, 8212, 11 }, + { 102, 2, 2, 2, 8213, 11 }, + { 127, 2, 2, 2, 8214, 11 }, + { 152, 2, 2, 2, 8215, 11 }, + { 169, 2, 2, 2, 8216, 11 }, + { 186, 2, 2, 2, 8217, 11 }, + { 203, 2, 2, 2, 8218, 11 }, + { 220, 2, 2, 2, 8219, 11 }, + { 4, 2, 2, 2, 8220, 11 }, + { 33, 2, 2, 2, 8221, 11 }, + { 62, 2, 2, 2, 8222, 11 }, + { 87, 2, 2, 2, 8223, 11 }, + { 112, 2, 2, 2, 8224, 11 }, + { 137, 2, 2, 2, 8225, 11 }, + { 26, 91, 2, 0, 8226, 1 }, + { 55, 91, 2, 0, 8227, 1 }, + { 80, 91, 2, 0, 8228, 1 }, + { 105, 91, 2, 0, 8229, 1 }, + { 130, 91, 2, 0, 8230, 1 }, + { 155, 91, 2, 0, 8231, 1 }, + { 172, 91, 2, 0, 8232, 1 }, + { 189, 91, 2, 0, 8233, 1 }, + { 206, 91, 2, 0, 8234, 1 }, + { 223, 91, 2, 0, 8235, 1 }, + { 8, 91, 2, 0, 8236, 1 }, + { 37, 91, 2, 0, 8237, 1 }, + { 66, 91, 2, 0, 8238, 1 }, + { 91, 91, 2, 0, 8239, 1 }, + { 116, 91, 2, 0, 8240, 1 }, + { 141, 91, 2, 0, 8241, 1 }, + { 158, 91, 2, 0, 8242, 1 }, + { 175, 91, 2, 0, 8243, 1 }, + { 192, 91, 2, 0, 8244, 1 }, + { 209, 91, 2, 0, 8245, 1 }, + { 12, 91, 2, 0, 8246, 1 }, + { 41, 91, 2, 0, 8247, 1 }, + { 70, 91, 2, 0, 8248, 1 }, + { 95, 91, 2, 0, 8249, 1 }, + { 120, 91, 2, 0, 8250, 1 }, + { 145, 91, 2, 0, 8251, 1 }, + { 162, 91, 2, 0, 8252, 1 }, + { 179, 91, 2, 0, 8253, 1 }, + { 196, 91, 2, 0, 8254, 1 }, + { 213, 91, 2, 0, 8255, 1 }, + { 16, 91, 2, 0, 8256, 1 }, + { 45, 91, 2, 0, 8257, 1 }, + { 253, 68, 159, 1, 8226, 1 }, + { 281, 68, 159, 1, 8227, 1 }, + { 304, 68, 155, 1, 8228, 1 }, + { 327, 68, 155, 1, 8229, 1 }, + { 350, 68, 155, 1, 8230, 1 }, + { 373, 68, 155, 1, 8231, 1 }, + { 391, 68, 151, 1, 8232, 1 }, + { 409, 68, 151, 1, 8233, 1 }, + { 427, 68, 151, 1, 8234, 1 }, + { 445, 68, 151, 1, 8235, 1 }, + { 233, 68, 147, 1, 8236, 1 }, + { 261, 68, 147, 1, 8237, 1 }, + { 289, 68, 147, 1, 8238, 1 }, + { 312, 68, 147, 1, 8239, 1 }, + { 335, 68, 143, 1, 8240, 1 }, + { 358, 68, 143, 1, 8241, 1 }, + { 381, 68, 1, 1, 8242, 1 }, + { 399, 68, 1, 1, 8243, 1 }, + { 417, 68, 1, 1, 8244, 1 }, + { 435, 68, 1, 1, 8245, 1 }, + { 243, 68, 1, 1, 8246, 1 }, + { 271, 68, 1, 1, 8247, 1 }, + { 299, 68, 1, 1, 8248, 1 }, + { 322, 68, 1, 1, 8249, 1 }, + { 345, 68, 1, 1, 8250, 1 }, + { 368, 68, 1, 1, 8251, 1 }, + { 386, 68, 1, 1, 8252, 1 }, + { 404, 68, 1, 1, 8253, 1 }, + { 422, 68, 1, 1, 8254, 1 }, + { 440, 68, 1, 1, 8255, 1 }, + { 248, 68, 1, 1, 8256, 1 }, + { 276, 68, 1, 1, 8257, 1 }, + { 598, 65, 2, 6, 258082, 3 }, + { 606, 65, 2, 6, 258083, 3 }, + { 634, 70, 2, 6, 258086, 3 }, + { 642, 70, 2, 6, 258087, 3 }, + { 650, 75, 2, 6, 258090, 3 }, + { 658, 75, 2, 6, 258091, 3 }, + { 610, 80, 2, 6, 258094, 3 }, + { 624, 80, 2, 6, 258095, 3 }, + { 677, 2, 158, 2, 8226, 11 }, + { 696, 2, 158, 2, 8227, 11 }, + { 710, 2, 154, 2, 8228, 11 }, + { 724, 2, 154, 2, 8229, 11 }, + { 738, 2, 154, 2, 8230, 11 }, + { 752, 2, 154, 2, 8231, 11 }, + { 766, 2, 150, 2, 8232, 11 }, + { 780, 2, 150, 2, 8233, 11 }, + { 794, 2, 150, 2, 8234, 11 }, + { 808, 2, 150, 2, 8235, 11 }, + { 662, 2, 146, 2, 8236, 11 }, + { 681, 2, 146, 2, 8237, 11 }, + { 700, 2, 146, 2, 8238, 11 }, + { 714, 2, 146, 2, 8239, 11 }, + { 728, 2, 142, 2, 8240, 11 }, + { 742, 2, 142, 2, 8241, 11 }, + { 756, 2, 0, 2, 8242, 11 }, + { 770, 2, 0, 2, 8243, 11 }, + { 784, 2, 0, 2, 8244, 11 }, + { 798, 2, 0, 2, 8245, 11 }, + { 667, 2, 0, 2, 8246, 11 }, + { 686, 2, 0, 2, 8247, 11 }, + { 705, 2, 0, 2, 8248, 11 }, + { 719, 2, 0, 2, 8249, 11 }, + { 733, 2, 0, 2, 8250, 11 }, + { 747, 2, 0, 2, 8251, 11 }, + { 761, 2, 0, 2, 8252, 11 }, + { 775, 2, 0, 2, 8253, 11 }, + { 789, 2, 0, 2, 8254, 11 }, + { 803, 2, 0, 2, 8255, 11 }, + { 672, 2, 0, 2, 8256, 11 }, + { 691, 2, 0, 2, 8257, 11 }, + { 257, 7, 137, 3, 249922, 0 }, + { 285, 7, 131, 3, 249924, 0 }, + { 308, 7, 131, 3, 249926, 0 }, + { 331, 7, 125, 3, 249928, 0 }, + { 354, 7, 125, 3, 249930, 0 }, + { 377, 7, 119, 3, 249932, 0 }, + { 395, 7, 119, 3, 249934, 0 }, + { 413, 7, 113, 3, 249936, 0 }, + { 431, 7, 113, 3, 249938, 0 }, + { 449, 7, 107, 3, 249940, 0 }, + { 238, 7, 107, 3, 249942, 0 }, + { 266, 7, 101, 3, 249944, 0 }, + { 294, 7, 101, 3, 249946, 0 }, + { 317, 7, 95, 3, 249948, 0 }, + { 340, 7, 95, 3, 249950, 0 }, + { 363, 7, 68, 3, 249952, 0 }, + { 458, 2, 139, 2, 8259, 11 }, + { 467, 2, 133, 2, 8261, 11 }, + { 476, 2, 133, 2, 8263, 11 }, + { 485, 2, 127, 2, 8265, 11 }, + { 494, 2, 127, 2, 8267, 11 }, + { 503, 2, 121, 2, 8269, 11 }, + { 507, 2, 121, 2, 8271, 11 }, + { 511, 2, 115, 2, 8273, 11 }, + { 515, 2, 115, 2, 8275, 11 }, + { 519, 2, 109, 2, 8277, 11 }, + { 453, 2, 109, 2, 8279, 11 }, + { 462, 2, 103, 2, 8281, 11 }, + { 471, 2, 103, 2, 8283, 11 }, + { 480, 2, 97, 2, 8285, 11 }, + { 489, 2, 97, 2, 8287, 11 }, + { 498, 2, 88, 2, 8289, 11 }, + { 528, 2, 136, 2, 8258, 11 }, + { 537, 2, 130, 2, 8260, 11 }, + { 546, 2, 130, 2, 8262, 11 }, + { 555, 2, 124, 2, 8264, 11 }, + { 564, 2, 124, 2, 8266, 11 }, + { 573, 2, 118, 2, 8268, 11 }, + { 577, 2, 118, 2, 8270, 11 }, + { 581, 2, 112, 2, 8272, 11 }, + { 585, 2, 112, 2, 8274, 11 }, + { 589, 2, 106, 2, 8276, 11 }, + { 523, 2, 106, 2, 8278, 11 }, + { 532, 2, 100, 2, 8280, 11 }, + { 541, 2, 100, 2, 8282, 11 }, + { 550, 2, 94, 2, 8284, 11 }, + { 559, 2, 94, 2, 8286, 11 }, + { 568, 2, 85, 2, 8288, 11 }, + { 602, 3, 2, 11, 241730, 6 }, + { 620, 10, 2, 11, 241734, 6 }, + { 638, 17, 2, 11, 241738, 6 }, + { 646, 24, 2, 11, 241742, 6 }, + { 654, 31, 2, 11, 241746, 6 }, + { 593, 38, 2, 11, 241750, 6 }, + { 615, 45, 2, 11, 241754, 6 }, + { 629, 52, 2, 11, 241758, 6 }, }; // GRX32Bit Register Class... static const MCPhysReg GRX32Bit[] = { - SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15L, SystemZ_R15H, SystemZ_R14L, SystemZ_R14H, SystemZ_R13L, SystemZ_R13H, SystemZ_R12L, SystemZ_R12H, SystemZ_R11L, SystemZ_R11H, SystemZ_R10L, SystemZ_R10H, SystemZ_R9L, SystemZ_R9H, SystemZ_R8L, SystemZ_R8H, SystemZ_R7L, SystemZ_R7H, SystemZ_R6L, SystemZ_R6H, + SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15L, SystemZ_R15H, SystemZ_R14L, SystemZ_R14H, SystemZ_R13L, SystemZ_R13H, SystemZ_R12L, SystemZ_R12H, SystemZ_R11L, SystemZ_R11H, SystemZ_R10L, SystemZ_R10H, SystemZ_R9L, SystemZ_R9H, SystemZ_R8L, SystemZ_R8H, SystemZ_R7L, SystemZ_R7H, SystemZ_R6L, SystemZ_R6H, }; // GRX32Bit Bit set. static const uint8_t GRX32BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // VR32Bit Register Class... static const MCPhysReg VR32Bit[] = { - SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S, SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S, SystemZ_F24S, SystemZ_F25S, SystemZ_F26S, SystemZ_F27S, SystemZ_F28S, SystemZ_F29S, SystemZ_F30S, SystemZ_F31S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S, + SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S, SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S, SystemZ_F24S, SystemZ_F25S, SystemZ_F26S, SystemZ_F27S, SystemZ_F28S, SystemZ_F29S, SystemZ_F30S, SystemZ_F31S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S, }; // VR32Bit Bit set. static const uint8_t VR32BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // AR32Bit Register Class... static const MCPhysReg AR32Bit[] = { - SystemZ_A0, SystemZ_A1, SystemZ_A2, SystemZ_A3, SystemZ_A4, SystemZ_A5, SystemZ_A6, SystemZ_A7, SystemZ_A8, SystemZ_A9, SystemZ_A10, SystemZ_A11, SystemZ_A12, SystemZ_A13, SystemZ_A14, SystemZ_A15, + SystemZ_A0, SystemZ_A1, SystemZ_A2, SystemZ_A3, SystemZ_A4, SystemZ_A5, SystemZ_A6, SystemZ_A7, SystemZ_A8, SystemZ_A9, SystemZ_A10, SystemZ_A11, SystemZ_A12, SystemZ_A13, SystemZ_A14, SystemZ_A15, }; // AR32Bit Bit set. static const uint8_t AR32BitBits[] = { - 0xfc, 0xff, 0x03, + 0xf8, 0xff, 0x07, }; // FP32Bit Register Class... static const MCPhysReg FP32Bit[] = { - SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S, + SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S, }; // FP32Bit Bit set. static const uint8_t FP32BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, }; // GR32Bit Register Class... static const MCPhysReg GR32Bit[] = { - SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L, + SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L, }; // GR32Bit Bit set. static const uint8_t GR32BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, }; // GRH32Bit Register Class... static const MCPhysReg GRH32Bit[] = { - SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15H, SystemZ_R14H, SystemZ_R13H, SystemZ_R12H, SystemZ_R11H, SystemZ_R10H, SystemZ_R9H, SystemZ_R8H, SystemZ_R7H, SystemZ_R6H, + SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15H, SystemZ_R14H, SystemZ_R13H, SystemZ_R12H, SystemZ_R11H, SystemZ_R10H, SystemZ_R9H, SystemZ_R8H, SystemZ_R7H, SystemZ_R6H, }; // GRH32Bit Bit set. static const uint8_t GRH32BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, }; // ADDR32Bit Register Class... static const MCPhysReg ADDR32Bit[] = { - SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L, + SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L, }; // ADDR32Bit Bit set. static const uint8_t ADDR32BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, }; // CCR Register Class... static const MCPhysReg CCR[] = { - SystemZ_CC, + SystemZ_CC, }; // CCR Bit set. static const uint8_t CCRBits[] = { - 0x02, + 0x02, + }; + + // FPCRegs Register Class... + static const MCPhysReg FPCRegs[] = { + SystemZ_FPC, + }; + + // FPCRegs Bit set. + static const uint8_t FPCRegsBits[] = { + 0x04, }; // AnyRegBit Register Class... static const MCPhysReg AnyRegBit[] = { - SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R6D, SystemZ_R7D, SystemZ_R8D, SystemZ_R9D, SystemZ_R10D, SystemZ_R11D, SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, SystemZ_R15D, SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, + SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R6D, SystemZ_R7D, SystemZ_R8D, SystemZ_R9D, SystemZ_R10D, SystemZ_R11D, SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, SystemZ_R15D, SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, }; // AnyRegBit Bit set. static const uint8_t AnyRegBitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, + 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, 0x00, 0xf8, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, }; - // AnyRegBit_with_subreg_r32 Register Class... - static const MCPhysReg AnyRegBit_with_subreg_r32[] = { - SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, + // AnyRegBit_with_subreg_h32_in_FP32Bit Register Class... + static const MCPhysReg AnyRegBit_with_subreg_h32_in_FP32Bit[] = { + SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, }; - // AnyRegBit_with_subreg_r32 Bit set. - static const uint8_t AnyRegBit_with_subreg_r32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0xfc, 0xff, 0x03, + // AnyRegBit_with_subreg_h32_in_FP32Bit Bit set. + static const uint8_t AnyRegBit_with_subreg_h32_in_FP32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, 0x00, 0xf8, 0xff, 0x07, }; // VR64Bit Register Class... static const MCPhysReg VR64Bit[] = { - SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D, SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D, SystemZ_F24D, SystemZ_F25D, SystemZ_F26D, SystemZ_F27D, SystemZ_F28D, SystemZ_F29D, SystemZ_F30D, SystemZ_F31D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, + SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D, SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D, SystemZ_F24D, SystemZ_F25D, SystemZ_F26D, SystemZ_F27D, SystemZ_F28D, SystemZ_F29D, SystemZ_F30D, SystemZ_F31D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, }; // VR64Bit Bit set. static const uint8_t VR64BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; - // AnyRegBit_with_subreg_r64 Register Class... - static const MCPhysReg AnyRegBit_with_subreg_r64[] = { - SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, + // AnyRegBit_with_subreg_h64 Register Class... + static const MCPhysReg AnyRegBit_with_subreg_h64[] = { + SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, }; - // AnyRegBit_with_subreg_r64 Bit set. - static const uint8_t AnyRegBit_with_subreg_r64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, + // AnyRegBit_with_subreg_h64 Bit set. + static const uint8_t AnyRegBit_with_subreg_h64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, }; // CR64Bit Register Class... static const MCPhysReg CR64Bit[] = { - SystemZ_C0, SystemZ_C1, SystemZ_C2, SystemZ_C3, SystemZ_C4, SystemZ_C5, SystemZ_C6, SystemZ_C7, SystemZ_C8, SystemZ_C9, SystemZ_C10, SystemZ_C11, SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15, + SystemZ_C0, SystemZ_C1, SystemZ_C2, SystemZ_C3, SystemZ_C4, SystemZ_C5, SystemZ_C6, SystemZ_C7, SystemZ_C8, SystemZ_C9, SystemZ_C10, SystemZ_C11, SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15, }; // CR64Bit Bit set. static const uint8_t CR64BitBits[] = { - 0x00, 0x00, 0xfc, 0xff, 0x03, + 0x00, 0x00, 0xf8, 0xff, 0x07, }; // FP64Bit Register Class... static const MCPhysReg FP64Bit[] = { - SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, + SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, }; // FP64Bit Bit set. static const uint8_t FP64BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, }; // GR64Bit Register Class... static const MCPhysReg GR64Bit[] = { - SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D, + SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D, }; // GR64Bit Bit set. static const uint8_t GR64BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, }; // ADDR64Bit Register Class... static const MCPhysReg ADDR64Bit[] = { - SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D, + SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D, }; // ADDR64Bit Bit set. static const uint8_t ADDR64BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, }; // VR128Bit Register Class... static const MCPhysReg VR128Bit[] = { - SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19, SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23, SystemZ_V24, SystemZ_V25, SystemZ_V26, SystemZ_V27, SystemZ_V28, SystemZ_V29, SystemZ_V30, SystemZ_V31, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, + SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19, SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23, SystemZ_V24, SystemZ_V25, SystemZ_V26, SystemZ_V27, SystemZ_V28, SystemZ_V29, SystemZ_V30, SystemZ_V31, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, }; // VR128Bit Bit set. static const uint8_t VR128BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, + 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // VF128Bit Register Class... static const MCPhysReg VF128Bit[] = { - SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, + SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, }; // VF128Bit Bit set. static const uint8_t VF128BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, + 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, }; // FP128Bit Register Class... static const MCPhysReg FP128Bit[] = { - SystemZ_F0Q, SystemZ_F1Q, SystemZ_F4Q, SystemZ_F5Q, SystemZ_F8Q, SystemZ_F9Q, SystemZ_F12Q, SystemZ_F13Q, + SystemZ_F0Q, SystemZ_F1Q, SystemZ_F4Q, SystemZ_F5Q, SystemZ_F8Q, SystemZ_F9Q, SystemZ_F12Q, SystemZ_F13Q, }; // FP128Bit Bit set. static const uint8_t FP128BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, }; // GR128Bit Register Class... static const MCPhysReg GR128Bit[] = { - SystemZ_R0Q, SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q, + SystemZ_R0Q, SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q, }; // GR128Bit Bit set. static const uint8_t GR128BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, }; // ADDR128Bit Register Class... static const MCPhysReg ADDR128Bit[] = { - SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q, + SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q, }; // ADDR128Bit Bit set. static const uint8_t ADDR128BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, }; static const MCRegisterClass SystemZMCRegisterClasses[] = { @@ -723,10 +734,11 @@ static const MCRegisterClass SystemZMCRegisterClasses[] = { { GRH32Bit, GRH32BitBits, sizeof(GRH32BitBits) }, { ADDR32Bit, ADDR32BitBits, sizeof(ADDR32BitBits) }, { CCR, CCRBits, sizeof(CCRBits) }, + { FPCRegs, FPCRegsBits, sizeof(FPCRegsBits) }, { AnyRegBit, AnyRegBitBits, sizeof(AnyRegBitBits) }, - { AnyRegBit_with_subreg_r32, AnyRegBit_with_subreg_r32Bits, sizeof(AnyRegBit_with_subreg_r32Bits) }, + { AnyRegBit_with_subreg_h32_in_FP32Bit, AnyRegBit_with_subreg_h32_in_FP32BitBits, sizeof(AnyRegBit_with_subreg_h32_in_FP32BitBits) }, { VR64Bit, VR64BitBits, sizeof(VR64BitBits) }, - { AnyRegBit_with_subreg_r64, AnyRegBit_with_subreg_r64Bits, sizeof(AnyRegBit_with_subreg_r64Bits) }, + { AnyRegBit_with_subreg_h64, AnyRegBit_with_subreg_h64Bits, sizeof(AnyRegBit_with_subreg_h64Bits) }, { CR64Bit, CR64BitBits, sizeof(CR64BitBits) }, { FP64Bit, FP64BitBits, sizeof(FP64BitBits) }, { GR64Bit, GR64BitBits, sizeof(GR64BitBits) }, @@ -738,4 +750,204 @@ static const MCRegisterClass SystemZMCRegisterClasses[] = { { ADDR128Bit, ADDR128BitBits, sizeof(ADDR128BitBits) }, }; -#endif // GET_REGINFO_MC_DESC \ No newline at end of file +static const uint16_t SystemZRegEncodingTable[] = { + 0, + 0, + 0, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 0, + 1, + 4, + 5, + 8, + 9, + 12, + 13, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 0, + 2, + 4, + 6, + 8, + 10, + 12, + 14, +}; +#endif // GET_REGINFO_MC_DESC + + + diff --git a/arch/SystemZ/SystemZGenSubtargetInfo.inc b/arch/SystemZ/SystemZGenSubtargetInfo.inc index 4d62b7295c..366a34c3f1 100644 --- a/arch/SystemZ/SystemZGenSubtargetInfo.inc +++ b/arch/SystemZ/SystemZGenSubtargetInfo.inc @@ -1,49 +1,65 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* Subtarget Enumeration Source Fragment *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ +/* Capstone Disassembly Engine, https://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2024 */ +/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* LLVM-commit: */ +/* LLVM-tag: */ +/* Do not edit. */ + +/* Capstone's LLVM TableGen Backends: */ +/* https://github.com/capstone-engine/llvm-capstone */ #ifdef GET_SUBTARGETINFO_ENUM #undef GET_SUBTARGETINFO_ENUM enum { - SystemZ_FeatureDFPPackedConversion = 1ULL << 0, - SystemZ_FeatureDFPZonedConversion = 1ULL << 1, - SystemZ_FeatureDistinctOps = 1ULL << 2, - SystemZ_FeatureEnhancedDAT2 = 1ULL << 3, - SystemZ_FeatureExecutionHint = 1ULL << 4, - SystemZ_FeatureFPExtension = 1ULL << 5, - SystemZ_FeatureFastSerialization = 1ULL << 6, - SystemZ_FeatureGuardedStorage = 1ULL << 7, - SystemZ_FeatureHighWord = 1ULL << 8, - SystemZ_FeatureInsertReferenceBitsMultiple = 1ULL << 9, - SystemZ_FeatureInterlockedAccess1 = 1ULL << 10, - SystemZ_FeatureLoadAndTrap = 1ULL << 11, - SystemZ_FeatureLoadAndZeroRightmostByte = 1ULL << 12, - SystemZ_FeatureLoadStoreOnCond = 1ULL << 13, - SystemZ_FeatureLoadStoreOnCond2 = 1ULL << 14, - SystemZ_FeatureMessageSecurityAssist3 = 1ULL << 15, - SystemZ_FeatureMessageSecurityAssist4 = 1ULL << 16, - SystemZ_FeatureMessageSecurityAssist5 = 1ULL << 17, - SystemZ_FeatureMessageSecurityAssist7 = 1ULL << 18, - SystemZ_FeatureMessageSecurityAssist8 = 1ULL << 19, - SystemZ_FeatureMiscellaneousExtensions = 1ULL << 20, - SystemZ_FeatureMiscellaneousExtensions2 = 1ULL << 21, - SystemZ_FeaturePopulationCount = 1ULL << 22, - SystemZ_FeatureProcessorAssist = 1ULL << 23, - SystemZ_FeatureResetReferenceBitsMultiple = 1ULL << 24, - SystemZ_FeatureTransactionalExecution = 1ULL << 25, - SystemZ_FeatureVector = 1ULL << 26, - SystemZ_FeatureVectorEnhancements1 = 1ULL << 27, - SystemZ_FeatureVectorPackedDecimal = 1ULL << 28, + SystemZ_FeatureBEAREnhancement = 0, + SystemZ_FeatureBackChain = 1, + SystemZ_FeatureDFPPackedConversion = 2, + SystemZ_FeatureDFPZonedConversion = 3, + SystemZ_FeatureDeflateConversion = 4, + SystemZ_FeatureDistinctOps = 5, + SystemZ_FeatureEnhancedDAT2 = 6, + SystemZ_FeatureEnhancedSort = 7, + SystemZ_FeatureExecutionHint = 8, + SystemZ_FeatureFPExtension = 9, + SystemZ_FeatureFastSerialization = 10, + SystemZ_FeatureGuardedStorage = 11, + SystemZ_FeatureHighWord = 12, + SystemZ_FeatureInsertReferenceBitsMultiple = 13, + SystemZ_FeatureInterlockedAccess1 = 14, + SystemZ_FeatureLoadAndTrap = 15, + SystemZ_FeatureLoadAndZeroRightmostByte = 16, + SystemZ_FeatureLoadStoreOnCond = 17, + SystemZ_FeatureLoadStoreOnCond2 = 18, + SystemZ_FeatureMessageSecurityAssist3 = 19, + SystemZ_FeatureMessageSecurityAssist4 = 20, + SystemZ_FeatureMessageSecurityAssist5 = 21, + SystemZ_FeatureMessageSecurityAssist7 = 22, + SystemZ_FeatureMessageSecurityAssist8 = 23, + SystemZ_FeatureMessageSecurityAssist9 = 24, + SystemZ_FeatureMiscellaneousExtensions = 25, + SystemZ_FeatureMiscellaneousExtensions2 = 26, + SystemZ_FeatureMiscellaneousExtensions3 = 27, + SystemZ_FeatureNNPAssist = 28, + SystemZ_FeaturePopulationCount = 29, + SystemZ_FeatureProcessorActivityInstrumentation = 30, + SystemZ_FeatureProcessorAssist = 31, + SystemZ_FeatureResetDATProtection = 32, + SystemZ_FeatureResetReferenceBitsMultiple = 33, + SystemZ_FeatureSoftFloat = 34, + SystemZ_FeatureTransactionalExecution = 35, + SystemZ_FeatureVector = 36, + SystemZ_FeatureVectorEnhancements1 = 37, + SystemZ_FeatureVectorEnhancements2 = 38, + SystemZ_FeatureVectorPackedDecimal = 39, + SystemZ_FeatureVectorPackedDecimalEnhancement = 40, + SystemZ_FeatureVectorPackedDecimalEnhancement2 = 41, + SystemZ_NumSubtargetFeatures = 42 }; - #endif // GET_SUBTARGETINFO_ENUM + + diff --git a/arch/SystemZ/SystemZInstPrinter.c b/arch/SystemZ/SystemZInstPrinter.c index 9687c4aab0..c0dc60c437 100644 --- a/arch/SystemZ/SystemZInstPrinter.c +++ b/arch/SystemZ/SystemZInstPrinter.c @@ -1,433 +1,384 @@ -//===-- SystemZInstPrinter.cpp - Convert SystemZ MCInst to assembly syntax --------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically translated source file from LLVM. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Only small edits allowed. */ +/* For multiple similar edits, please create a Patch for the translator. */ + +/* Capstone's C++ file translator: */ +/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ + +//===- SystemZInstPrinter.cpp - Convert SystemZ MCInst to assembly syntax -===// // -// This class prints an SystemZ MCInst to a .s file. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ - -#ifdef CAPSTONE_HAS_SYSZ - +#include #include -#include #include +#include #include -#include "SystemZInstPrinter.h" -#include "../../MCInst.h" -#include "../../utils.h" -#include "../../SStream.h" -#include "../../MCRegisterInfo.h" -#include "../../MathExtras.h" -#include "SystemZMapping.h" +#include "../../MCAsmInfo.h" -static const char *getRegisterName(unsigned RegNo); +#include "SystemZMapping.h" +#include "SystemZInstPrinter.h" +#include "SystemZMCTargetDesc.h" + +#define CONCAT(a, b) CONCAT_(a, b) +#define CONCAT_(a, b) a##_##b + +static void printAddress(const MCAsmInfo *MAI, MCRegister Base, + const MCOperand *DispMO, MCRegister Index, SStream *O); +static void printMCOperandMAI(const MCOperand *MO, const MCAsmInfo *MAI, + SStream *O); +static void printRegName(const MCInst *MI, SStream *O, MCRegister Reg); +static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O); +static void printOperand(MCInst *MI, int OpNum, SStream *O); +static void printU1ImmOperand(MCInst *MI, int OpNum, SStream *O); +static void printU2ImmOperand(MCInst *MI, int OpNum, SStream *O); +static void printU3ImmOperand(MCInst *MI, int OpNum, SStream *O); +static void printU4ImmOperand(MCInst *MI, int OpNum, SStream *O); +static void printS8ImmOperand(MCInst *MI, int OpNum, SStream *O); +static void printU8ImmOperand(MCInst *MI, int OpNum, SStream *O); +static void printU12ImmOperand(MCInst *MI, int OpNum, SStream *O); +static void printS16ImmOperand(MCInst *MI, int OpNum, SStream *O); +static void printU16ImmOperand(MCInst *MI, int OpNum, SStream *O); +static void printS32ImmOperand(MCInst *MI, int OpNum, SStream *O); +static void printU32ImmOperand(MCInst *MI, int OpNum, SStream *O); +static void printU48ImmOperand(MCInst *MI, int OpNum, SStream *O); +static void printBDAddrOperand(MCInst *MI, int OpNum, SStream *O); +static void printBDXAddrOperand(MCInst *MI, int OpNum, SStream *O); +static void printBDLAddrOperand(MCInst *MI, int OpNum, SStream *O); +static void printBDRAddrOperand(MCInst *MI, int OpNum, SStream *O); +static void printBDVAddrOperand(MCInst *MI, int OpNum, SStream *O); +static void printPCRelOperand(MCInst *MI, uint64_t Address, int OpNum, SStream *O); +static void printPCRelTLSOperand(MCInst *MI, uint64_t Address, int OpNum, SStream *O); +// This forms part of the instruction name rather than the operand list. +// Print the mnemonic for a condition-code mask ("ne", "lh", etc.) +static void printCond4Operand(MCInst *MI, int OpNum, SStream *O); -void SystemZ_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) -{ - /* - if (((cs_struct *)ud)->detail != CS_OPT_ON) - return; - */ -} +#include "SystemZGenAsmWriter.inc" -static void printAddress(MCInst *MI, unsigned Base, int64_t Disp, unsigned Index, SStream *O) +#define DECLARE_printUImmOperand(N) \ + static void CONCAT(printUImmOperand, N)(MCInst * MI, int OpNum, SStream *O); +DECLARE_printUImmOperand(1); +DECLARE_printUImmOperand(2); +DECLARE_printUImmOperand(3); +DECLARE_printUImmOperand(4); +DECLARE_printUImmOperand(8); +DECLARE_printUImmOperand(12); +DECLARE_printUImmOperand(16); +DECLARE_printUImmOperand(32); +DECLARE_printUImmOperand(48); + +#define DECLARE_printSImmOperand(N) \ + static void CONCAT(printSImmOperand, N)(MCInst * MI, int OpNum, SStream *O); +DECLARE_printSImmOperand(8); +DECLARE_printSImmOperand(16); +DECLARE_printSImmOperand(32); + +static void printAddress(const MCAsmInfo *MAI, MCRegister Base, + const MCOperand *DispMO, MCRegister Index, SStream *O) { - printInt64(O, Disp); - - if (Base) { + printMCOperandMAI(DispMO, MAI, O); + if (Base || Index) { SStream_concat0(O, "("); - if (Index) - SStream_concat(O, "%%%s, ", getRegisterName(Index)); - SStream_concat(O, "%%%s)", getRegisterName(Base)); - - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base); - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)SystemZ_map_register(Index); - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = Disp; - MI->flat_insn->detail->sysz.op_count++; - } - } else if (!Index) { - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Disp; - MI->flat_insn->detail->sysz.op_count++; - } - } else { - SStream_concat(O, "(%%%s)", getRegisterName(Index)); - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base); - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)SystemZ_map_register(Index); - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = Disp; - MI->flat_insn->detail->sysz.op_count++; + + if (Index) { + printFormattedRegName(MAI, Index, O); + SStream_concat0(O, ","); } + if (Base) + printFormattedRegName(MAI, Base, O); + else + SStream_concat0(O, "0"); + + SStream_concat0(O, ")"); } } -static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O) +static void printMCOperandMAI(const MCOperand *MO, const MCAsmInfo *MAI, + SStream *O) { + if (MCOperand_isReg(MO)) { + if (!MCOperand_getReg(MO)) + SStream_concat1(O, '0'); + else + printFormattedRegName(MAI, MCOperand_getReg(MO), O); + } + else if (MCOperand_isImm(MO)) + printInt64(markup_OS(O, Markup_Immediate), MCOperand_getImm(MO)); + else if (MCOperand_isExpr(MO)) + printExpr(O, MCOperand_getExpr(MO)); + else + CS_ASSERT(0 && "Invalid operand"); +} + +static void printMCOperand(const MCInst *MI, const MCOperand *MO, SStream *O) { if (MCOperand_isReg(MO)) { - unsigned reg; + if (!MCOperand_getReg(MO)) + SStream_concat0(O, "0"); - reg = MCOperand_getReg(MO); - SStream_concat(O, "%%%s", getRegisterName(reg)); - reg = SystemZ_map_register(reg); + else + printFormattedRegName(&MI->MAI, MCOperand_getReg(MO), O); + } else if (MCOperand_isImm(MO)) + printInt64(markup_OS(O, Markup_Immediate), + MCOperand_getImm(MO)); + else if (MCOperand_isExpr(MO)) + printExpr(O, MCOperand_getExpr(MO)); \ + else + assert(0 && "Invalid operand"); +} - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_REG; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].reg = reg; - MI->flat_insn->detail->sysz.op_count++; - } - } else if (MCOperand_isImm(MO)) { - int64_t Imm = MCOperand_getImm(MO); +void printFormattedRegName(const MCAsmInfo *MAI, MCRegister Reg, SStream *O) +{ + const char *RegName = getRegisterName(Reg); + if (MAI->assemblerDialect == SYSTEMZASMDIALECT_AD_ATT) { + // Skip register prefix so that only register number is left + CS_ASSERT((isalpha(RegName[0]) && isdigit(RegName[1]))); + SStream_concat0(markup_OS(O, Markup_Register), (RegName + 1)); + } else + SStream_concat1(markup_OS(O, Markup_Register), '%'); + SStream_concat0(markup_OS(O, Markup_Register), RegName); +} + +static void printRegName(const MCInst *MI, SStream *O, MCRegister Reg) +{ + printFormattedRegName(&MI->MAI, Reg, O); +} - printInt64(O, Imm); +static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O) +{ + printInstruction(MI, Address, O); +} - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Imm; - MI->flat_insn->detail->sysz.op_count++; - } +#define DEFINE_printUImmOperand(N) \ + void CONCAT(printUImmOperand, N)(MCInst * MI, int OpNum, SStream *O) \ + { \ + MCOperand *MO = MCInst_getOperand(MI, (OpNum)); \ + if (MCOperand_isExpr(MO)) { \ + printExpr(O, MCOperand_getExpr(MO)); \ + return; \ + } \ + uint64_t Value = (uint64_t)(MCOperand_getImm(MO)); \ + CS_ASSERT((isUIntN(N, Value) && "Invalid uimm argument")); \ + printUInt64(markup_OS(O, Markup_Immediate), Value); \ } -} +DEFINE_printUImmOperand(1); +DEFINE_printUImmOperand(2); +DEFINE_printUImmOperand(3); +DEFINE_printUImmOperand(4); +DEFINE_printUImmOperand(8); +DEFINE_printUImmOperand(12); +DEFINE_printUImmOperand(16); +DEFINE_printUImmOperand(32); +DEFINE_printUImmOperand(48); + +#define DEFINE_printSImmOperand(N) \ + void CONCAT(printSImmOperand, N)(MCInst * MI, int OpNum, SStream *O) \ + { \ + MCOperand *MO = MCInst_getOperand(MI, (OpNum)); \ + if (MCOperand_isExpr(MO)) { \ + printExpr(O, MCOperand_getExpr(MO)); \ + return; \ + } \ + int64_t Value = \ + MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \ + CS_ASSERT( \ + (CONCAT(isInt, N)(Value) && "Invalid simm argument")); \ + if (N == 8) \ + printInt8(markup_OS(O, Markup_Immediate), Value); \ + else if (N == 16) \ + printInt16(markup_OS(O, Markup_Immediate), Value); \ + else if (N == 32) \ + printInt32(markup_OS(O, Markup_Immediate), Value); \ + else \ + CS_ASSERT(0 && "Unreachable"); \ + } +DEFINE_printSImmOperand(8); +DEFINE_printSImmOperand(16); +DEFINE_printSImmOperand(32); static void printU1ImmOperand(MCInst *MI, int OpNum, SStream *O) { - int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<1>(Value) && "Invalid u1imm argument"); - printInt64(O, Value); - - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; - MI->flat_insn->detail->sysz.op_count++; - } + add_cs_detail(MI, SystemZ_OP_GROUP_U1ImmOperand, OpNum); + CONCAT(printUImmOperand, 1)(MI, OpNum, O); } static void printU2ImmOperand(MCInst *MI, int OpNum, SStream *O) { - int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<2>(Value) && "Invalid u2imm argument"); - printInt64(O, Value); - - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; - MI->flat_insn->detail->sysz.op_count++; - } + add_cs_detail(MI, SystemZ_OP_GROUP_U2ImmOperand, OpNum); + CONCAT(printUImmOperand, 2)(MI, OpNum, O); } static void printU3ImmOperand(MCInst *MI, int OpNum, SStream *O) { - int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<3>(Value) && "Invalid u4imm argument"); - printInt64(O, Value); - - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; - MI->flat_insn->detail->sysz.op_count++; - } + add_cs_detail(MI, SystemZ_OP_GROUP_U3ImmOperand, OpNum); + CONCAT(printUImmOperand, 3)(MI, OpNum, O); } static void printU4ImmOperand(MCInst *MI, int OpNum, SStream *O) { - int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<4>(Value) && "Invalid u4imm argument"); - printInt64(O, Value); - - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; - MI->flat_insn->detail->sysz.op_count++; - } -} - -static void printU6ImmOperand(MCInst *MI, int OpNum, SStream *O) -{ - uint32_t Value = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<6>(Value) && "Invalid u6imm argument"); - - printUInt32(O, Value); - - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; - MI->flat_insn->detail->sysz.op_count++; - } + add_cs_detail(MI, SystemZ_OP_GROUP_U4ImmOperand, OpNum); + CONCAT(printUImmOperand, 4)(MI, OpNum, O); } static void printS8ImmOperand(MCInst *MI, int OpNum, SStream *O) { - int8_t Value = (int8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isInt<8>(Value) && "Invalid s8imm argument"); - - if (Value >= 0) { - if (Value > HEX_THRESHOLD) - SStream_concat(O, "0x%x", Value); - else - SStream_concat(O, "%u", Value); - } else { - if (Value < -HEX_THRESHOLD) - SStream_concat(O, "-0x%x", -Value); - else - SStream_concat(O, "-%u", -Value); - } - - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; - MI->flat_insn->detail->sysz.op_count++; - } + add_cs_detail(MI, SystemZ_OP_GROUP_S8ImmOperand, OpNum); + CONCAT(printSImmOperand, 8)(MI, OpNum, O); } static void printU8ImmOperand(MCInst *MI, int OpNum, SStream *O) { - uint8_t Value = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<8>(Value) && "Invalid u8imm argument"); - - if (Value > HEX_THRESHOLD) - SStream_concat(O, "0x%x", Value); - else - SStream_concat(O, "%u", Value); - - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; - MI->flat_insn->detail->sysz.op_count++; - } + add_cs_detail(MI, SystemZ_OP_GROUP_U8ImmOperand, OpNum); + CONCAT(printUImmOperand, 8)(MI, OpNum, O); } static void printU12ImmOperand(MCInst *MI, int OpNum, SStream *O) { - int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<12>(Value) && "Invalid u12imm argument"); - printInt64(O, Value); - - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; - MI->flat_insn->detail->sysz.op_count++; - } + add_cs_detail(MI, SystemZ_OP_GROUP_U12ImmOperand, OpNum); + CONCAT(printUImmOperand, 12)(MI, OpNum, O); } static void printS16ImmOperand(MCInst *MI, int OpNum, SStream *O) { - int16_t Value = (int16_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isInt<16>(Value) && "Invalid s16imm argument"); - - if (Value >= 0) { - if (Value > HEX_THRESHOLD) - SStream_concat(O, "0x%x", Value); - else - SStream_concat(O, "%u", Value); - } else { - if (Value < -HEX_THRESHOLD) - SStream_concat(O, "-0x%x", -Value); - else - SStream_concat(O, "-%u", -Value); - } - - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; - MI->flat_insn->detail->sysz.op_count++; - } + add_cs_detail(MI, SystemZ_OP_GROUP_S16ImmOperand, OpNum); + CONCAT(printSImmOperand, 16)(MI, OpNum, O); } static void printU16ImmOperand(MCInst *MI, int OpNum, SStream *O) { - uint16_t Value = (uint16_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<16>(Value) && "Invalid u16imm argument"); - - if (Value > HEX_THRESHOLD) - SStream_concat(O, "0x%x", Value); - else - SStream_concat(O, "%u", Value); - - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; - MI->flat_insn->detail->sysz.op_count++; - } + add_cs_detail(MI, SystemZ_OP_GROUP_U16ImmOperand, OpNum); + CONCAT(printUImmOperand, 16)(MI, OpNum, O); } static void printS32ImmOperand(MCInst *MI, int OpNum, SStream *O) { - int32_t Value = (int32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isInt<32>(Value) && "Invalid s32imm argument"); - - printInt32(O, Value); - - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; - MI->flat_insn->detail->sysz.op_count++; - } + add_cs_detail(MI, SystemZ_OP_GROUP_S32ImmOperand, OpNum); + CONCAT(printSImmOperand, 32)(MI, OpNum, O); } static void printU32ImmOperand(MCInst *MI, int OpNum, SStream *O) { - uint32_t Value = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<32>(Value) && "Invalid u32imm argument"); - - printUInt32(O, Value); - - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; - MI->flat_insn->detail->sysz.op_count++; - } + add_cs_detail(MI, SystemZ_OP_GROUP_U32ImmOperand, OpNum); + CONCAT(printUImmOperand, 32)(MI, OpNum, O); } static void printU48ImmOperand(MCInst *MI, int OpNum, SStream *O) { - int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<48>(Value) && "Invalid u48imm argument"); - printInt64(O, Value); - - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; - MI->flat_insn->detail->sysz.op_count++; - } + add_cs_detail(MI, SystemZ_OP_GROUP_U48ImmOperand, OpNum); + CONCAT(printUImmOperand, 48)(MI, OpNum, O); } -static void printPCRelOperand(MCInst *MI, int OpNum, SStream *O) +static void printPCRelOperand(MCInst *MI, uint64_t Address, int OpNum, SStream *O) { - MCOperand *MO = MCInst_getOperand(MI, OpNum); - + add_cs_detail(MI, SystemZ_OP_GROUP_PCRelOperand, OpNum); + MCOperand *MO = MCInst_getOperand(MI, (OpNum)); if (MCOperand_isImm(MO)) { - int64_t imm = (int64_t)MCOperand_getImm(MO); - - printInt64(O, imm); - - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = imm; - MI->flat_insn->detail->sysz.op_count++; - } - } + printInt64(O, MCOperand_getImm(MO)); + } else + printExpr(O, MCOperand_getExpr(MO)); } -static void printPCRelTLSOperand(MCInst *MI, int OpNum, SStream *O) +static void printPCRelTLSOperand(MCInst *MI, uint64_t Address, int OpNum, SStream *O) { // Output the PC-relative operand. - printPCRelOperand(MI, OpNum, O); + printPCRelOperand(MI, MI->address, OpNum, O); + + // Output the TLS marker if present. + if ((unsigned)OpNum + 1 < MCInst_getNumOperands(MI)) { + // Expressions not supported + } } static void printOperand(MCInst *MI, int OpNum, SStream *O) { - _printOperand(MI, MCInst_getOperand(MI, OpNum), O); + add_cs_detail(MI, SystemZ_OP_GROUP_Operand, OpNum); + printMCOperand(MI, MCInst_getOperand(MI, (OpNum)), O); } static void printBDAddrOperand(MCInst *MI, int OpNum, SStream *O) { - printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)), - MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)), 0, O); + add_cs_detail(MI, SystemZ_OP_GROUP_BDAddrOperand, OpNum); + printAddress(&MI->MAI, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))), + MCInst_getOperand(MI, (OpNum + 1)), 0, O); } static void printBDXAddrOperand(MCInst *MI, int OpNum, SStream *O) { - printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)), - MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)), - MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)), O); + add_cs_detail(MI, SystemZ_OP_GROUP_BDXAddrOperand, OpNum); + printAddress(&MI->MAI, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))), + MCInst_getOperand(MI, (OpNum + 1)), + MCOperand_getReg(MCInst_getOperand(MI, (OpNum + 2))), O); } static void printBDLAddrOperand(MCInst *MI, int OpNum, SStream *O) { - unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); - uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); - uint64_t Length = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 2)); - - if (Disp > HEX_THRESHOLD) - SStream_concat(O, "0x%"PRIx64, Disp); - else - SStream_concat(O, "%"PRIu64, Disp); - - if (Length > HEX_THRESHOLD) - SStream_concat(O, "(0x%"PRIx64, Length); - else - SStream_concat(O, "(%"PRIu64, Length); - - if (Base) - SStream_concat(O, ", %%%s", getRegisterName(Base)); - SStream_concat0(O, ")"); - - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base); - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.length = Length; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = (int64_t)Disp; - MI->flat_insn->detail->sysz.op_count++; + add_cs_detail(MI, SystemZ_OP_GROUP_BDLAddrOperand, OpNum); + unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); + MCOperand *DispMO = MCInst_getOperand(MI, (OpNum + 1)); + uint64_t Length = MCOperand_getImm(MCInst_getOperand(MI, (OpNum + 2))); + printMCOperandMAI(DispMO, &MI->MAI, O); + SStream_concat1(O, '('); + printUInt64(O, Length); + if (Base) { + SStream_concat0(O, ","); + printRegName(MI, O, Base); } + SStream_concat0(O, ")"); } static void printBDRAddrOperand(MCInst *MI, int OpNum, SStream *O) { - unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); - uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); - uint64_t Length = MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)); - - if (Disp > HEX_THRESHOLD) - SStream_concat(O, "0x%"PRIx64, Disp); - else - SStream_concat(O, "%"PRIu64, Disp); - + add_cs_detail(MI, SystemZ_OP_GROUP_BDRAddrOperand, OpNum); + unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); + MCOperand *DispMO = MCInst_getOperand(MI, (OpNum + 1)); + unsigned Length = MCOperand_getReg(MCInst_getOperand(MI, (OpNum + 2))); + printMCOperandMAI(DispMO, &MI->MAI, O); SStream_concat0(O, "("); - SStream_concat(O, "%%%s", getRegisterName(Length)); - - if (Base) - SStream_concat(O, ", %%%s", getRegisterName(Base)); - SStream_concat0(O, ")"); - - if (MI->csh->detail_opt) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base); - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.length = (uint8_t)SystemZ_map_register(Length); - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = (int64_t)Disp; - MI->flat_insn->detail->sysz.op_count++; + printRegName(MI, O, Length); + if (Base) { + SStream_concat0(O, ","); + printRegName(MI, O, Base); } + SStream_concat0(O, ")"); } static void printBDVAddrOperand(MCInst *MI, int OpNum, SStream *O) { - printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)), - MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)), - MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)), O); + add_cs_detail(MI, SystemZ_OP_GROUP_BDVAddrOperand, OpNum); + printAddress(&MI->MAI, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))), + MCInst_getOperand(MI, (OpNum + 1)), + MCOperand_getReg(MCInst_getOperand(MI, (OpNum + 2))), O); } static void printCond4Operand(MCInst *MI, int OpNum, SStream *O) { - static const char *const CondNames[] = { - "o", "h", "nle", "l", "nhe", "lh", "ne", - "e", "nlh", "he", "nl", "le", "nh", "no" - }; - - uint64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(Imm > 0 && Imm < 15 && "Invalid condition"); + add_cs_detail(MI, SystemZ_OP_GROUP_Cond4Operand, OpNum); + static const char *const CondNames[] = { "o", "h", "nle", "l", + "nhe", "lh", "ne", "e", + "nlh", "he", "nl", "le", + "nh", "no" }; + uint64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); + CS_ASSERT((Imm > 0 && Imm < 15 && "Invalid condition")); SStream_concat0(O, CondNames[Imm - 1]); - - if (MI->csh->detail_opt) - MI->flat_insn->detail->sysz.cc = (sysz_cc)Imm; } -#define PRINT_ALIAS_INSTR -#include "SystemZGenAsmWriter.inc" - -void SystemZ_printInst(MCInst *MI, SStream *O, void *Info) +const char *SystemZ_LLVM_getRegisterName(unsigned RegNo) { - printInstruction(MI, O, Info); + return getRegisterName(RegNo); } -#endif +void SystemZ_LLVM_printInstruction(MCInst *MI, const char *Annotation, SStream *O) +{ + printInst(MI, MI->address, Annotation, O); +} diff --git a/arch/SystemZ/SystemZInstPrinter.h b/arch/SystemZ/SystemZInstPrinter.h index 68367accb0..8e14a77408 100644 --- a/arch/SystemZ/SystemZInstPrinter.h +++ b/arch/SystemZ/SystemZInstPrinter.h @@ -1,15 +1,51 @@ -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically translated source file from LLVM. */ -#ifndef CS_SYSZINSTPRINTER_H -#define CS_SYSZINSTPRINTER_H +/* LLVM-commit: */ +/* LLVM-tag: */ -#include "../../MCInst.h" -#include "../../MCRegisterInfo.h" -#include "../../SStream.h" +/* Only small edits allowed. */ +/* For multiple similar edits, please create a Patch for the translator. */ -void SystemZ_printInst(MCInst *MI, SStream *O, void *Info); +/* Capstone's C++ file translator: */ +/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ -void SystemZ_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); +//==- SystemZInstPrinter.h - Convert SystemZ MCInst to assembly --*- C++ -*-==// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This class prints a SystemZ MCInst to a .s file. +// +//===----------------------------------------------------------------------===// -#endif +#ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZINSTPRINTER_H +#define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZINSTPRINTER_H + +#include +#include +#include +#include + +#include "../../MCInstPrinter.h" +#include "../../cs_priv.h" +#define CONCAT(a, b) CONCAT_(a, b) +#define CONCAT_(a, b) a##_##b + +// +// All function declarations are moved for now to the C file to make them static. +// +void printOperandAsmInfo(const MCOperand *MO, const MCAsmInfo *MAI, SStream *O); +void printFormattedRegName(const MCAsmInfo *MAI, MCRegister Reg, SStream *O); + +// Print various types of operand. +; + +// end namespace llvm + +#endif // LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZINSTPRINTER_H diff --git a/arch/SystemZ/SystemZLinkage.h b/arch/SystemZ/SystemZLinkage.h new file mode 100644 index 0000000000..8f096467c4 --- /dev/null +++ b/arch/SystemZ/SystemZLinkage.h @@ -0,0 +1,22 @@ +/* Capstone Disassembly Engine */ +/* By Rot127 2022-2023 */ + +#ifndef CS_SYSTEMZ_LINKAGE_H +#define CS_SYSTEMZ_LINKAGE_H + +// Function definitions to call static LLVM functions. + +#include "../../MCDisassembler.h" +#include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include "../../SStream.h" +#include "capstone/capstone.h" + +DecodeStatus SystemZ_LLVM_getInstruction(csh handle, const uint8_t *Bytes, + size_t ByteLen, MCInst *MI, uint16_t *Size, + uint64_t Address, void *Info); +const char *SystemZ_LLVM_getRegisterName(unsigned RegNo); +void SystemZ_LLVM_printInstruction(MCInst *MI, const char *Annot, + SStream *O); + +#endif // CS_SYSTEMZ_LINKAGE_H diff --git a/arch/SystemZ/SystemZMCTargetDesc.c b/arch/SystemZ/SystemZMCTargetDesc.c index 538550e1b4..a01db768ad 100644 --- a/arch/SystemZ/SystemZMCTargetDesc.c +++ b/arch/SystemZ/SystemZMCTargetDesc.c @@ -1,195 +1,157 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically translated source file from LLVM. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Only small edits allowed. */ +/* For multiple similar edits, please create a Patch for the translator. */ + +/* Capstone's C++ file translator: */ +/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ + //===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ - -#ifdef CAPSTONE_HAS_SYSZ - +#include +#include +#include #include + +#include "../../MCInst.h" +#include "../../MCRegisterInfo.h" #include "SystemZMCTargetDesc.h" +#include "SystemZInstPrinter.h" -#define GET_REGINFO_ENUM +#define GET_INSTRINFO_MC_DESC +#define ENABLE_INSTR_PREDICATE_VERIFIER +#include "SystemZGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_MC_DESC +#include "SystemZGenSubtargetInfo.inc" + +#define GET_REGINFO_MC_DESC #include "SystemZGenRegisterInfo.inc" +#define CONCAT(a, b) CONCAT_(a, b) +#define CONCAT_(a, b) a##_##b const unsigned SystemZMC_GR32Regs[16] = { - SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, - SystemZ_R4L, SystemZ_R5L, SystemZ_R6L, SystemZ_R7L, - SystemZ_R8L, SystemZ_R9L, SystemZ_R10L, SystemZ_R11L, + SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, + SystemZ_R4L, SystemZ_R5L, SystemZ_R6L, SystemZ_R7L, + SystemZ_R8L, SystemZ_R9L, SystemZ_R10L, SystemZ_R11L, SystemZ_R12L, SystemZ_R13L, SystemZ_R14L, SystemZ_R15L }; const unsigned SystemZMC_GRH32Regs[16] = { - SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, - SystemZ_R4H, SystemZ_R5H, SystemZ_R6H, SystemZ_R7H, - SystemZ_R8H, SystemZ_R9H, SystemZ_R10H, SystemZ_R11H, + SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, + SystemZ_R4H, SystemZ_R5H, SystemZ_R6H, SystemZ_R7H, + SystemZ_R8H, SystemZ_R9H, SystemZ_R10H, SystemZ_R11H, SystemZ_R12H, SystemZ_R13H, SystemZ_R14H, SystemZ_R15H }; const unsigned SystemZMC_GR64Regs[16] = { - SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, - SystemZ_R4D, SystemZ_R5D, SystemZ_R6D, SystemZ_R7D, - SystemZ_R8D, SystemZ_R9D, SystemZ_R10D, SystemZ_R11D, + SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, + SystemZ_R4D, SystemZ_R5D, SystemZ_R6D, SystemZ_R7D, + SystemZ_R8D, SystemZ_R9D, SystemZ_R10D, SystemZ_R11D, SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, SystemZ_R15D }; -const unsigned SystemZMC_GR128Regs[16] = { - SystemZ_R0Q, 0, SystemZ_R2Q, 0, - SystemZ_R4Q, 0, SystemZ_R6Q, 0, - SystemZ_R8Q, 0, SystemZ_R10Q, 0, - SystemZ_R12Q, 0, SystemZ_R14Q, 0 -}; +const unsigned SystemZMC_GR128Regs[16] = { SystemZ_R0Q, 0, SystemZ_R2Q, 0, + SystemZ_R4Q, 0, SystemZ_R6Q, 0, + SystemZ_R8Q, 0, SystemZ_R10Q, 0, + SystemZ_R12Q, 0, SystemZ_R14Q, 0 }; const unsigned SystemZMC_FP32Regs[16] = { - SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, - SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, - SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, + SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, + SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, + SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S }; const unsigned SystemZMC_FP64Regs[16] = { - SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, - SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, - SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, + SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, + SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, + SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D }; -const unsigned SystemZMC_FP128Regs[16] = { - SystemZ_F0Q, SystemZ_F1Q, 0, 0, - SystemZ_F4Q, SystemZ_F5Q, 0, 0, - SystemZ_F8Q, SystemZ_F9Q, 0, 0, - SystemZ_F12Q, SystemZ_F13Q, 0, 0 -}; +const unsigned SystemZMC_FP128Regs[16] = { SystemZ_F0Q, SystemZ_F1Q, 0, 0, + SystemZ_F4Q, SystemZ_F5Q, 0, 0, + SystemZ_F8Q, SystemZ_F9Q, 0, 0, + SystemZ_F12Q, SystemZ_F13Q, 0, 0 }; const unsigned SystemZMC_VR32Regs[32] = { - SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, - SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, - SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, - SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S, - SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S, - SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S, - SystemZ_F24S, SystemZ_F25S, SystemZ_F26S, SystemZ_F27S, - SystemZ_F28S, SystemZ_F29S, SystemZ_F30S, SystemZ_F31S + SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, + SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F8S, SystemZ_F9S, + SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, + SystemZ_F15S, SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S, + SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S, SystemZ_F24S, + SystemZ_F25S, SystemZ_F26S, SystemZ_F27S, SystemZ_F28S, SystemZ_F29S, + SystemZ_F30S, SystemZ_F31S }; const unsigned SystemZMC_VR64Regs[32] = { - SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, - SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, - SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, - SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, - SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D, - SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D, - SystemZ_F24D, SystemZ_F25D, SystemZ_F26D, SystemZ_F27D, - SystemZ_F28D, SystemZ_F29D, SystemZ_F30D, SystemZ_F31D + SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, + SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, + SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, + SystemZ_F15D, SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D, + SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D, SystemZ_F24D, + SystemZ_F25D, SystemZ_F26D, SystemZ_F27D, SystemZ_F28D, SystemZ_F29D, + SystemZ_F30D, SystemZ_F31D }; const unsigned SystemZMC_VR128Regs[32] = { - SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, - SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, - SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, - SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, - SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19, - SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23, - SystemZ_V24, SystemZ_V25, SystemZ_V26, SystemZ_V27, - SystemZ_V28, SystemZ_V29, SystemZ_V30, SystemZ_V31 + SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, + SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, + SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, + SystemZ_V15, SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19, + SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23, SystemZ_V24, + SystemZ_V25, SystemZ_V26, SystemZ_V27, SystemZ_V28, SystemZ_V29, + SystemZ_V30, SystemZ_V31 }; -const unsigned SystemZMC_AR32Regs[16] = { - SystemZ_A0, SystemZ_A1, SystemZ_A2, SystemZ_A3, - SystemZ_A4, SystemZ_A5, SystemZ_A6, SystemZ_A7, - SystemZ_A8, SystemZ_A9, SystemZ_A10, SystemZ_A11, - SystemZ_A12, SystemZ_A13, SystemZ_A14, SystemZ_A15 -}; - -const unsigned SystemZMC_CR64Regs[16] = { - SystemZ_C0, SystemZ_C1, SystemZ_C2, SystemZ_C3, - SystemZ_C4, SystemZ_C5, SystemZ_C6, SystemZ_C7, - SystemZ_C8, SystemZ_C9, SystemZ_C10, SystemZ_C11, - SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15 -}; +const unsigned SystemZMC_AR32Regs[16] = { SystemZ_A0, SystemZ_A1, SystemZ_A2, + SystemZ_A3, SystemZ_A4, SystemZ_A5, + SystemZ_A6, SystemZ_A7, SystemZ_A8, + SystemZ_A9, SystemZ_A10, SystemZ_A11, + SystemZ_A12, SystemZ_A13, SystemZ_A14, + SystemZ_A15 }; -/* All register classes that have 0-15. */ -#define DEF_REG16(N) \ - [SystemZ_R ## N ## L] = N, \ - [SystemZ_R ## N ## H] = N, \ - [SystemZ_R ## N ## D] = N, \ - [SystemZ_F ## N ## S] = N, \ - [SystemZ_F ## N ## D] = N, \ - [SystemZ_V ## N] = N, \ - [SystemZ_A ## N] = N, \ - [SystemZ_C ## N] = N - -/* All register classes that (also) have 16-31. */ -#define DEF_REG32(N) \ - [SystemZ_F ## N ## S] = N, \ - [SystemZ_F ## N ## D] = N, \ - [SystemZ_V ## N] = N - -static const uint8_t Map[SystemZ_NUM_TARGET_REGS] = { - DEF_REG16(0), - DEF_REG16(1), - DEF_REG16(2), - DEF_REG16(3), - DEF_REG16(4), - DEF_REG16(5), - DEF_REG16(6), - DEF_REG16(8), - DEF_REG16(9), - DEF_REG16(10), - DEF_REG16(11), - DEF_REG16(12), - DEF_REG16(13), - DEF_REG16(14), - DEF_REG16(15), - - DEF_REG32(16), - DEF_REG32(17), - DEF_REG32(18), - DEF_REG32(19), - DEF_REG32(20), - DEF_REG32(21), - DEF_REG32(22), - DEF_REG32(23), - DEF_REG32(24), - DEF_REG32(25), - DEF_REG32(26), - DEF_REG32(27), - DEF_REG32(28), - DEF_REG32(29), - DEF_REG32(30), - DEF_REG32(31), - - /* The float Q registers are non-sequential. */ - [SystemZ_F0Q] = 0, - [SystemZ_F1Q] = 1, - [SystemZ_F4Q] = 4, - [SystemZ_F5Q] = 5, - [SystemZ_F8Q] = 8, - [SystemZ_F9Q] = 9, - [SystemZ_F12Q] = 12, - [SystemZ_F13Q] = 13, - - /* The integer Q registers are all even. */ - [SystemZ_R0Q] = 0, - [SystemZ_R2Q] = 2, - [SystemZ_R4Q] = 4, - [SystemZ_R6Q] = 6, - [SystemZ_R8Q] = 8, - [SystemZ_R10Q] = 10, - [SystemZ_R12Q] = 12, - [SystemZ_R14Q] = 14, -}; +const unsigned SystemZMC_CR64Regs[16] = { SystemZ_C0, SystemZ_C1, SystemZ_C2, + SystemZ_C3, SystemZ_C4, SystemZ_C5, + SystemZ_C6, SystemZ_C7, SystemZ_C8, + SystemZ_C9, SystemZ_C10, SystemZ_C11, + SystemZ_C12, SystemZ_C13, SystemZ_C14, + SystemZ_C15 }; unsigned SystemZMC_getFirstReg(unsigned Reg) { - // assert(Reg < SystemZ_NUM_TARGET_REGS); + static unsigned Map[NUM_TARGET_REGS]; + static bool Initialized = false; + if (!Initialized) { + for (unsigned I = 0; I < 16; ++I) { + Map[SystemZMC_GR32Regs[I]] = I; + Map[SystemZMC_GRH32Regs[I]] = I; + Map[SystemZMC_GR64Regs[I]] = I; + Map[SystemZMC_GR128Regs[I]] = I; + Map[SystemZMC_FP128Regs[I]] = I; + Map[SystemZMC_AR32Regs[I]] = I; + } + for (unsigned I = 0; I < 32; ++I) { + Map[SystemZMC_VR32Regs[I]] = I; + Map[SystemZMC_VR64Regs[I]] = I; + Map[SystemZMC_VR128Regs[I]] = I; + } + } + CS_ASSERT((Reg < SystemZ_NUM_TARGET_REGS)); return Map[Reg]; } -#endif +// end namespace diff --git a/arch/SystemZ/SystemZMCTargetDesc.h b/arch/SystemZ/SystemZMCTargetDesc.h index 972a7e2964..0441a65800 100644 --- a/arch/SystemZ/SystemZMCTargetDesc.h +++ b/arch/SystemZ/SystemZMCTargetDesc.h @@ -1,17 +1,39 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2022, */ +/* Rot127 2022-2023 */ +/* Automatically translated source file from LLVM. */ + +/* LLVM-commit: */ +/* LLVM-tag: */ + +/* Only small edits allowed. */ +/* For multiple similar edits, please create a Patch for the translator. */ + +/* Capstone's C++ file translator: */ +/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ + //===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ +#ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H +#define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H + +#include +#include +#include +#include -#ifndef CS_SYSTEMZMCTARGETDESC_H -#define CS_SYSTEMZMCTARGETDESC_H +#include "../../MCInstPrinter.h" +#include "../../cs_priv.h" +#define CONCAT(a, b) CONCAT_(a, b) +#define CONCAT_(a, b) a##_##b + +// CS namespace begin: SystemZMC // Maps of asm register numbers to LLVM register numbers, with 0 indicating // an invalid register. In principle we could use 32-bit and 64-bit register @@ -20,32 +42,72 @@ // as %r0-%r15. It seems better to provide the same interface for // all classes though. extern const unsigned SystemZMC_GR32Regs[16]; + extern const unsigned SystemZMC_GRH32Regs[16]; + extern const unsigned SystemZMC_GR64Regs[16]; + extern const unsigned SystemZMC_GR128Regs[16]; + extern const unsigned SystemZMC_FP32Regs[16]; + extern const unsigned SystemZMC_FP64Regs[16]; + extern const unsigned SystemZMC_FP128Regs[16]; + extern const unsigned SystemZMC_VR32Regs[32]; + extern const unsigned SystemZMC_VR64Regs[32]; + extern const unsigned SystemZMC_VR128Regs[32]; + extern const unsigned SystemZMC_AR32Regs[16]; + extern const unsigned SystemZMC_CR64Regs[16]; // Return the 0-based number of the first architectural register that // contains the given LLVM register. E.g. R1D -> 1. unsigned SystemZMC_getFirstReg(unsigned Reg); +// Return the given register as a GR64. +inline unsigned SystemZMC_getRegAsGR64(unsigned Reg) +{ + return SystemZMC_GR64Regs[SystemZMC_getFirstReg(Reg)]; +} + +// Return the given register as a low GR32. +inline unsigned SystemZMC_getRegAsGR32(unsigned Reg) +{ + return SystemZMC_GR32Regs[SystemZMC_getFirstReg(Reg)]; +} + +// Return the given register as a high GR32. +inline unsigned SystemZMC_getRegAsGRH32(unsigned Reg) +{ + return SystemZMC_GRH32Regs[SystemZMC_getFirstReg(Reg)]; +} + +// Return the given register as a VR128. +inline unsigned SystemZMC_getRegAsVR128(unsigned Reg) +{ + return SystemZMC_VR128Regs[SystemZMC_getFirstReg(Reg)]; +} + +// CS namespace end: SystemZMC + +// end namespace SystemZMC + // Defines symbolic names for SystemZ registers. // This defines a mapping from register name to register number. -//#define GET_REGINFO_ENUM -//#include "SystemZGenRegisterInfo.inc" +#define GET_REGINFO_ENUM +#include "SystemZGenRegisterInfo.inc" // Defines symbolic names for the SystemZ instructions. -//#define GET_INSTRINFO_ENUM -//#include "SystemZGenInstrInfo.inc" +#define GET_INSTRINFO_ENUM +#define GET_INSTRINFO_MC_HELPER_DECLS +#include "SystemZGenInstrInfo.inc" -//#define GET_SUBTARGETINFO_ENUM -//#include "SystemZGenSubtargetInfo.inc" +#define GET_SUBTARGETINFO_ENUM +#include "SystemZGenSubtargetInfo.inc" #endif diff --git a/arch/SystemZ/SystemZMapping.c b/arch/SystemZ/SystemZMapping.c index 71f1017230..5cef93ba69 100644 --- a/arch/SystemZ/SystemZMapping.c +++ b/arch/SystemZ/SystemZMapping.c @@ -1,224 +1,130 @@ /* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* By Rot127 2022-2023 */ -#ifdef CAPSTONE_HAS_SYSZ +#ifdef CAPSTONE_HAS_SYSTEMZ #include // debug #include #include "../../Mapping.h" #include "../../utils.h" +#include "../../cs_simple_types.h" +#include +#include "SystemZMCTargetDesc.h" #include "SystemZMapping.h" +#include "SystemZLinkage.h" -#define GET_INSTRINFO_ENUM -#include "SystemZGenInstrInfo.inc" #ifndef CAPSTONE_DIET -static const name_map reg_name_maps[] = { - { SYSZ_REG_INVALID, NULL }, - - { SYSZ_REG_0, "0" }, - { SYSZ_REG_1, "1" }, - { SYSZ_REG_2, "2" }, - { SYSZ_REG_3, "3" }, - { SYSZ_REG_4, "4" }, - { SYSZ_REG_5, "5" }, - { SYSZ_REG_6, "6" }, - { SYSZ_REG_7, "7" }, - { SYSZ_REG_8, "8" }, - { SYSZ_REG_9, "9" }, - { SYSZ_REG_10, "10" }, - { SYSZ_REG_11, "11" }, - { SYSZ_REG_12, "12" }, - { SYSZ_REG_13, "13" }, - { SYSZ_REG_14, "14" }, - { SYSZ_REG_15, "15" }, - { SYSZ_REG_CC, "cc"}, - { SYSZ_REG_F0, "f0" }, - { SYSZ_REG_F1, "f1" }, - { SYSZ_REG_F2, "f2" }, - { SYSZ_REG_F3, "f3" }, - { SYSZ_REG_F4, "f4" }, - { SYSZ_REG_F5, "f5" }, - { SYSZ_REG_F6, "f6" }, - { SYSZ_REG_F7, "f7" }, - { SYSZ_REG_F8, "f8" }, - { SYSZ_REG_F9, "f9" }, - { SYSZ_REG_F10, "f10" }, - { SYSZ_REG_F11, "f11" }, - { SYSZ_REG_F12, "f12" }, - { SYSZ_REG_F13, "f13" }, - { SYSZ_REG_F14, "f14" }, - { SYSZ_REG_F15, "f15" }, - { SYSZ_REG_R0L, "r0l" }, - { SYSZ_REG_A0, "a0" }, - { SYSZ_REG_A1, "a1" }, - { SYSZ_REG_A2, "a2" }, - { SYSZ_REG_A3, "a3" }, - { SYSZ_REG_A4, "a4" }, - { SYSZ_REG_A5, "a5" }, - { SYSZ_REG_A6, "a6" }, - { SYSZ_REG_A7, "a7" }, - { SYSZ_REG_A8, "a8" }, - { SYSZ_REG_A9, "a9" }, - { SYSZ_REG_A10, "a10" }, - { SYSZ_REG_A11, "a11" }, - { SYSZ_REG_A12, "a12" }, - { SYSZ_REG_A13, "a13" }, - { SYSZ_REG_A14, "a14" }, - { SYSZ_REG_A15, "a15" }, - { SYSZ_REG_C0, "c0" }, - { SYSZ_REG_C1, "c1" }, - { SYSZ_REG_C2, "c2" }, - { SYSZ_REG_C3, "c3" }, - { SYSZ_REG_C4, "c4" }, - { SYSZ_REG_C5, "c5" }, - { SYSZ_REG_C6, "c6" }, - { SYSZ_REG_C7, "c7" }, - { SYSZ_REG_C8, "c8" }, - { SYSZ_REG_C9, "c9" }, - { SYSZ_REG_C10, "c10" }, - { SYSZ_REG_C11, "c11" }, - { SYSZ_REG_C12, "c12" }, - { SYSZ_REG_C13, "c13" }, - { SYSZ_REG_C14, "c14" }, - { SYSZ_REG_C15, "c15" }, - { SYSZ_REG_V0, "v0" }, - { SYSZ_REG_V1, "v1" }, - { SYSZ_REG_V2, "v2" }, - { SYSZ_REG_V3, "v3" }, - { SYSZ_REG_V4, "v4" }, - { SYSZ_REG_V5, "v5" }, - { SYSZ_REG_V6, "v6" }, - { SYSZ_REG_V7, "v7" }, - { SYSZ_REG_V8, "v8" }, - { SYSZ_REG_V9, "v9" }, - { SYSZ_REG_V10, "v10" }, - { SYSZ_REG_V11, "v11" }, - { SYSZ_REG_V12, "v12" }, - { SYSZ_REG_V13, "v13" }, - { SYSZ_REG_V14, "v14" }, - { SYSZ_REG_V15, "v15" }, - { SYSZ_REG_V16, "v16" }, - { SYSZ_REG_V17, "v17" }, - { SYSZ_REG_V18, "v18" }, - { SYSZ_REG_V19, "v19" }, - { SYSZ_REG_V20, "v20" }, - { SYSZ_REG_V21, "v21" }, - { SYSZ_REG_V22, "v22" }, - { SYSZ_REG_V23, "v23" }, - { SYSZ_REG_V24, "v24" }, - { SYSZ_REG_V25, "v25" }, - { SYSZ_REG_V26, "v26" }, - { SYSZ_REG_V27, "v27" }, - { SYSZ_REG_V28, "v28" }, - { SYSZ_REG_V29, "v29" }, - { SYSZ_REG_V30, "v30" }, - { SYSZ_REG_V31, "v31" }, - { SYSZ_REG_F16, "f16" }, - { SYSZ_REG_F17, "f17" }, - { SYSZ_REG_F18, "f18" }, - { SYSZ_REG_F19, "f19" }, - { SYSZ_REG_F20, "f20" }, - { SYSZ_REG_F21, "f21" }, - { SYSZ_REG_F22, "f22" }, - { SYSZ_REG_F23, "f23" }, - { SYSZ_REG_F24, "f24" }, - { SYSZ_REG_F25, "f25" }, - { SYSZ_REG_F26, "f26" }, - { SYSZ_REG_F27, "f27" }, - { SYSZ_REG_F28, "f28" }, - { SYSZ_REG_F29, "f29" }, - { SYSZ_REG_F30, "f30" }, - { SYSZ_REG_F31, "f31" }, - { SYSZ_REG_F0Q, "f0q" }, - { SYSZ_REG_F4Q, "f4q" }, + +static const char *const insn_name_maps[] = { +#include "SystemZGenCSMappingInsnName.inc" }; -#endif -const char *SystemZ_reg_name(csh handle, unsigned int reg) -{ -#ifndef CAPSTONE_DIET - if (reg >= ARR_SIZE(reg_name_maps)) - return NULL; +static const name_map insn_alias_mnem_map[] = { +#include "SystemZGenCSAliasMnemMap.inc" + { SYSTEMZ_INS_ALIAS_END, NULL }, +}; - return reg_name_maps[reg].name; -#else - return NULL; -#endif -} +static const map_insn_ops insn_operands[] = { +#include "SystemZGenCSMappingInsnOp.inc" +}; -static const insn_map insns[] = { - // dummy item - { - 0, 0, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 #endif - }, -#include "SystemZMappingInsn.inc" +#define GET_REGINFO_MC_DESC +#include "SystemZGenRegisterInfo.inc" + +const insn_map systemz_insns[] = { +#include "SystemZGenCSMappingInsn.inc" }; -// given internal insn id, return public instruction info -void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) +void SystemZ_set_instr_map_data(MCInst *MI, const uint8_t *Bytes, size_t BytesLen) { - unsigned short i; - - i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); - if (i != 0) { - insn->id = insns[i].mapid; - - if (h->detail_opt) { -#ifndef CAPSTONE_DIET - memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); - insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); + map_cs_id(MI, systemz_insns, ARR_SIZE(systemz_insns)); + map_implicit_reads(MI, systemz_insns); + map_implicit_writes(MI, systemz_insns); + map_groups(MI, systemz_insns); + const systemz_suppl_info *suppl_info = + map_get_suppl_info(MI, systemz_insns); + if (suppl_info) { + SystemZ_get_detail(MI)->format = suppl_info->form; + } +} - memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); - insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); +void SystemZ_init_mri(MCRegisterInfo *MRI) +{ + MCRegisterInfo_InitMCRegisterInfo( + MRI, SystemZRegDesc, AARCH64_REG_ENDING, 0, 0, + SystemZMCRegisterClasses, ARR_SIZE(SystemZMCRegisterClasses), 0, + 0, SystemZRegDiffLists, 0, SystemZSubRegIdxLists, + ARR_SIZE(SystemZSubRegIdxLists), 0); +} - memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); - insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); +const char *SystemZ_reg_name(csh handle, unsigned int reg) +{ + return SystemZ_LLVM_getRegisterName(reg); +} - if (insns[i].branch || insns[i].indirect_branch) { - // this insn also belongs to JUMP group. add JUMP group - insn->detail->groups[insn->detail->groups_count] = SYSZ_GRP_JUMP; - insn->detail->groups_count++; - } +void SystemZ_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info) +{ + MI->MRI = (MCRegisterInfo *)info; + MI->fillDetailOps = detail_is_set(MI); + SystemZ_LLVM_printInstruction(MI, "", O); +#ifndef CAPSTONE_DIET + map_set_alias_id(MI, O, insn_alias_mnem_map, + ARR_SIZE(insn_alias_mnem_map)); #endif - } - } } -#ifndef CAPSTONE_DIET -static const name_map insn_name_maps[] = { - { SYSZ_INS_INVALID, NULL }, +void SystemZ_init_cs_detail(MCInst *MI) { + if (!detail_is_set(MI)) { + return; + } + memset(get_detail(MI), 0, sizeof(cs_detail)); + if (detail_is_set(MI)) { + SystemZ_get_detail(MI)->cc = SYSTEMZ_CC_INVALID; + } +} -#include "SystemZGenInsnNameMaps.inc" -}; +bool SystemZ_getInstruction(csh handle, const uint8_t *bytes, size_t bytes_len, + MCInst *MI, uint16_t *size, uint64_t address, + void *info) +{ + SystemZ_init_cs_detail(MI); + MI->MRI = (MCRegisterInfo *)info; + DecodeStatus result = SystemZ_LLVM_getInstruction( + handle, bytes, bytes_len, MI, size, address, info); + SystemZ_set_instr_map_data(MI, bytes, bytes_len); + return result != MCDisassembler_Fail; +} -// special alias insn -static const name_map alias_insn_names[] = { - { 0, NULL } -}; -#endif +// given internal insn id, return public instruction info +void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) +{ + // We do this after Instruction disassembly. +} const char *SystemZ_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - unsigned int i; + if (id < SYSTEMZ_INS_ALIAS_END && id > SYSTEMZ_INS_ALIAS_BEGIN) { + if (id - SYSTEMZ_INS_ALIAS_BEGIN >= + ARR_SIZE(insn_alias_mnem_map)) + return NULL; - if (id >= SYSZ_INS_ENDING) + return insn_alias_mnem_map[id - SYSTEMZ_INS_ALIAS_BEGIN - 1] + .name; + } + if (id >= SYSTEMZ_INS_ENDING) return NULL; - // handle special alias first - for (i = 0; i < ARR_SIZE(alias_insn_names); i++) { - if (alias_insn_names[i].id == id) - return alias_insn_names[i].name; - } + if (id < ARR_SIZE(insn_name_maps)) + return insn_name_maps[id]; - return insn_name_maps[id].name; + // not found + return NULL; #else return NULL; #endif @@ -227,38 +133,16 @@ const char *SystemZ_insn_name(csh handle, unsigned int id) #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { // generic groups - { SYSZ_GRP_INVALID, NULL }, - { SYSZ_GRP_JUMP, "jump" }, - - // architecture-specific groups - { SYSZ_GRP_DFPPACKEDCONVERSION, "dfppackedconversion" }, - { SYSZ_GRP_DFPZONEDCONVERSION, "dfpzonedconversion" }, - { SYSZ_GRP_DISTINCTOPS, "distinctops" }, - { SYSZ_GRP_ENHANCEDDAT2, "enhanceddat2" }, - { SYSZ_GRP_EXECUTIONHINT, "executionhint" }, - { SYSZ_GRP_FPEXTENSION, "fpextension" }, - { SYSZ_GRP_GUARDEDSTORAGE, "guardedstorage" }, - { SYSZ_GRP_HIGHWORD, "highword" }, - { SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE, "insertreferencebitsmultiple" }, - { SYSZ_GRP_INTERLOCKEDACCESS1, "interlockedaccess1" }, - { SYSZ_GRP_LOADANDTRAP, "loadandtrap" }, - { SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, "loadandzerorightmostbyte" }, - { SYSZ_GRP_LOADSTOREONCOND, "loadstoreoncond" }, - { SYSZ_GRP_LOADSTOREONCOND2, "loadstoreoncond2" }, - { SYSZ_GRP_MESSAGESECURITYASSIST3, "messagesecurityassist3" }, - { SYSZ_GRP_MESSAGESECURITYASSIST4, "messagesecurityassist4" }, - { SYSZ_GRP_MESSAGESECURITYASSIST5, "messagesecurityassist5" }, - { SYSZ_GRP_MESSAGESECURITYASSIST7, "messagesecurityassist7" }, - { SYSZ_GRP_MESSAGESECURITYASSIST8, "messagesecurityassist8" }, - { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, "miscellaneousextensions" }, - { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, "miscellaneousextensions2" }, - { SYSZ_GRP_POPULATIONCOUNT, "populationcount" }, - { SYSZ_GRP_PROCESSORASSIST, "processorassist" }, - { SYSZ_GRP_RESETREFERENCEBITSMULTIPLE, "resetreferencebitsmultiple" }, - { SYSZ_GRP_TRANSACTIONALEXECUTION, "transactionalexecution" }, - { SYSZ_GRP_VECTOR, "vector" }, - { SYSZ_GRP_VECTORENHANCEMENTS1, "vectorenhancements1" }, - { SYSZ_GRP_VECTORPACKEDDECIMAL, "vectorpackeddecimal" }, + { SYSTEMZ_GRP_INVALID, NULL }, + { SYSTEMZ_GRP_JUMP, "jump" }, + { SYSTEMZ_GRP_CALL, "call" }, + { SYSTEMZ_GRP_RET, "return" }, + { SYSTEMZ_GRP_INT, "int" }, + { SYSTEMZ_GRP_IRET, "iret" }, + { SYSTEMZ_GRP_PRIVILEGE, "privilege" }, + { SYSTEMZ_GRP_BRANCH_RELATIVE, "branch_relative" }, + + #include "SystemZGenCSFeatureName.inc" }; #endif @@ -271,210 +155,212 @@ const char *SystemZ_group_name(csh handle, unsigned int id) #endif } -// map internal raw register to 'public' register -sysz_reg SystemZ_map_register(unsigned int r) +void SystemZ_add_cs_detail(MCInst *MI, int /* aarch64_op_group */ op_group, + va_list args) +{ +#ifndef CAPSTONE_DIET + if (!detail_is_set(MI) || !map_fill_detail_ops(MI)) + return; + + unsigned op_num = va_arg(args, unsigned); + + switch (op_group) { + default: + printf("Operand group %d not handled\n", op_group); + break; + case SystemZ_OP_GROUP_Operand: { + CS_ASSERT(!(op_type & CS_OP_MEM) && "Mem op passed to prinOperand"); + cs_op_type secondary_op_type = map_get_op_type(MI, op_num) & + ~(CS_OP_MEM | CS_OP_BOUND); + if (secondary_op_type == CS_OP_IMM) { + SystemZ_set_detail_op_imm(MI, op_num, + MCInst_getOpVal(MI, op_num), 0); + } else if (secondary_op_type == CS_OP_REG) { + SystemZ_set_detail_op_reg(MI, op_num, + MCInst_getOpVal(MI, op_num)); + } else { + assert(0 && "Op type not handled."); + } + break; + } + case SystemZ_OP_GROUP_Cond4Operand: { + systemz_cc cc = MCInst_getOpVal(MI, op_num); + SystemZ_get_detail(MI)->cc = cc; + break; + } + case SystemZ_OP_GROUP_BDAddrOperand: + assert(map_get_op_type(MI, (op_num)) & CS_OP_MEM); + assert(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM); + assert(MCOperand_isReg(MCInst_getOperand(MI, (op_num)))); + assert(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1)))); + SystemZ_set_detail_op_mem(MI, + op_num, + MCInst_getOpVal(MI, (op_num)), + MCInst_getOpVal(MI, (op_num + 1)), + 0, + 0, + SYSTEMZ_AM_BD + ); + break; + case SystemZ_OP_GROUP_BDVAddrOperand: + case SystemZ_OP_GROUP_BDXAddrOperand: { + CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM); + CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM); + CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM); + CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num)))); + CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1)))); + CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num + 2)))); + SystemZ_set_detail_op_mem(MI, + op_num, + MCInst_getOpVal(MI, (op_num)), + MCInst_getOpVal(MI, (op_num + 1)), + 0, + MCInst_getOpVal(MI, (op_num + 2)), + (op_group == SystemZ_OP_GROUP_BDXAddrOperand ? SYSTEMZ_AM_BDX : SYSTEMZ_AM_BDV) + ); + break; + } + case SystemZ_OP_GROUP_BDLAddrOperand: + CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM); + CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM); + CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM); + CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num)))); + CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1)))); + CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 2)))); + SystemZ_set_detail_op_mem(MI, + op_num, + MCInst_getOpVal(MI, (op_num)), + MCInst_getOpVal(MI, (op_num + 1)), + MCInst_getOpVal(MI, (op_num + 2)), + 0, + SYSTEMZ_AM_BDL + ); + break; + case SystemZ_OP_GROUP_BDRAddrOperand: + CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM); + CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM); + CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM); + CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num)))); + CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1)))); + CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num + 2)))); + SystemZ_set_detail_op_mem(MI, + op_num, + MCInst_getOpVal(MI, (op_num)), + MCInst_getOpVal(MI, (op_num + 1)), + MCInst_getOpVal(MI, (op_num + 2)), + 0, + SYSTEMZ_AM_BDL + ); + break; + case SystemZ_OP_GROUP_PCRelOperand: + SystemZ_set_detail_op_imm(MI, op_num, + MCInst_getOpVal(MI, op_num), 0); + break; + case SystemZ_OP_GROUP_U1ImmOperand: + SystemZ_set_detail_op_imm(MI, op_num, + MCInst_getOpVal(MI, op_num), 1); + break; + case SystemZ_OP_GROUP_U2ImmOperand: + SystemZ_set_detail_op_imm(MI, op_num, + MCInst_getOpVal(MI, op_num), 2); + break; + case SystemZ_OP_GROUP_U3ImmOperand: + SystemZ_set_detail_op_imm(MI, op_num, + MCInst_getOpVal(MI, op_num), 3); + break; + case SystemZ_OP_GROUP_U4ImmOperand: + SystemZ_set_detail_op_imm(MI, op_num, + MCInst_getOpVal(MI, op_num), 4); + break; + case SystemZ_OP_GROUP_U8ImmOperand: + case SystemZ_OP_GROUP_S8ImmOperand: + SystemZ_set_detail_op_imm(MI, op_num, + MCInst_getOpVal(MI, op_num), 8); + break; + case SystemZ_OP_GROUP_U12ImmOperand: + SystemZ_set_detail_op_imm(MI, op_num, + MCInst_getOpVal(MI, op_num), 12); + break; + case SystemZ_OP_GROUP_U16ImmOperand: + case SystemZ_OP_GROUP_S16ImmOperand: + SystemZ_set_detail_op_imm(MI, op_num, + MCInst_getOpVal(MI, op_num), 16); + break; + case SystemZ_OP_GROUP_U32ImmOperand: + case SystemZ_OP_GROUP_S32ImmOperand: + SystemZ_set_detail_op_imm(MI, op_num, + MCInst_getOpVal(MI, op_num), 32); + break; + case SystemZ_OP_GROUP_U48ImmOperand: + SystemZ_set_detail_op_imm(MI, op_num, + MCInst_getOpVal(MI, op_num), 48); + break; + } +#endif +} + +#ifndef CAPSTONE_DIET + +void SystemZ_set_detail_op_imm(MCInst *MI, unsigned op_num, int64_t Imm, size_t width) +{ + if (!detail_is_set(MI)) + return; + CS_ASSERT((map_get_op_type(MI, op_num) & ~CS_OP_MEM) == CS_OP_IMM); + + SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_IMM; + SystemZ_get_detail_op(MI, 0)->imm = Imm; + SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num); + SystemZ_get_detail_op(MI, 0)->imm_width = width; + SystemZ_inc_op_count(MI); +} + +void SystemZ_set_detail_op_reg(MCInst *MI, unsigned op_num, systemz_reg Reg) { - static const unsigned int map[] = { 0, - /* SystemZ_CC = 1 */ SYSZ_REG_CC, - /* SystemZ_A0 = 2 */ SYSZ_REG_A0, - /* SystemZ_A1 = 3 */ SYSZ_REG_A1, - /* SystemZ_A2 = 4 */ SYSZ_REG_A2, - /* SystemZ_A3 = 5 */ SYSZ_REG_A3, - /* SystemZ_A4 = 6 */ SYSZ_REG_A4, - /* SystemZ_A5 = 7 */ SYSZ_REG_A5, - /* SystemZ_A6 = 8 */ SYSZ_REG_A6, - /* SystemZ_A7 = 9 */ SYSZ_REG_A7, - /* SystemZ_A8 = 10 */ SYSZ_REG_A8, - /* SystemZ_A9 = 11 */ SYSZ_REG_A9, - /* SystemZ_A10 = 12 */ SYSZ_REG_A10, - /* SystemZ_A11 = 13 */ SYSZ_REG_A11, - /* SystemZ_A12 = 14 */ SYSZ_REG_A12, - /* SystemZ_A13 = 15 */ SYSZ_REG_A13, - /* SystemZ_A14 = 16 */ SYSZ_REG_A14, - /* SystemZ_A15 = 17 */ SYSZ_REG_A15, - /* SystemZ_C0 = 18 */ SYSZ_REG_C0, - /* SystemZ_C1 = 19 */ SYSZ_REG_C1, - /* SystemZ_C2 = 20 */ SYSZ_REG_C2, - /* SystemZ_C3 = 21 */ SYSZ_REG_C3, - /* SystemZ_C4 = 22 */ SYSZ_REG_C4, - /* SystemZ_C5 = 23 */ SYSZ_REG_C5, - /* SystemZ_C6 = 24 */ SYSZ_REG_C6, - /* SystemZ_C7 = 25 */ SYSZ_REG_C7, - /* SystemZ_C8 = 26 */ SYSZ_REG_C8, - /* SystemZ_C9 = 27 */ SYSZ_REG_C9, - /* SystemZ_C10 = 28 */ SYSZ_REG_C10, - /* SystemZ_C11 = 29 */ SYSZ_REG_C11, - /* SystemZ_C12 = 30 */ SYSZ_REG_C12, - /* SystemZ_C13 = 31 */ SYSZ_REG_C13, - /* SystemZ_C14 = 32 */ SYSZ_REG_C14, - /* SystemZ_C15 = 33 */ SYSZ_REG_C15, - /* SystemZ_V0 = 34 */ SYSZ_REG_V0, - /* SystemZ_V1 = 35 */ SYSZ_REG_V1, - /* SystemZ_V2 = 36 */ SYSZ_REG_V2, - /* SystemZ_V3 = 37 */ SYSZ_REG_V3, - /* SystemZ_V4 = 38 */ SYSZ_REG_V4, - /* SystemZ_V5 = 39 */ SYSZ_REG_V5, - /* SystemZ_V6 = 40 */ SYSZ_REG_V6, - /* SystemZ_V7 = 41 */ SYSZ_REG_V7, - /* SystemZ_V8 = 42 */ SYSZ_REG_V8, - /* SystemZ_V9 = 43 */ SYSZ_REG_V9, - /* SystemZ_V10 = 44 */ SYSZ_REG_V10, - /* SystemZ_V11 = 45 */ SYSZ_REG_V11, - /* SystemZ_V12 = 46 */ SYSZ_REG_V12, - /* SystemZ_V13 = 47 */ SYSZ_REG_V13, - /* SystemZ_V14 = 48 */ SYSZ_REG_V14, - /* SystemZ_V15 = 49 */ SYSZ_REG_V15, - /* SystemZ_V16 = 50 */ SYSZ_REG_V16, - /* SystemZ_V17 = 51 */ SYSZ_REG_V17, - /* SystemZ_V18 = 52 */ SYSZ_REG_V18, - /* SystemZ_V19 = 53 */ SYSZ_REG_V19, - /* SystemZ_V20 = 54 */ SYSZ_REG_V20, - /* SystemZ_V21 = 55 */ SYSZ_REG_V21, - /* SystemZ_V22 = 56 */ SYSZ_REG_V22, - /* SystemZ_V23 = 57 */ SYSZ_REG_V23, - /* SystemZ_V24 = 58 */ SYSZ_REG_V24, - /* SystemZ_V25 = 59 */ SYSZ_REG_V25, - /* SystemZ_V26 = 60 */ SYSZ_REG_V26, - /* SystemZ_V27 = 61 */ SYSZ_REG_V27, - /* SystemZ_V28 = 62 */ SYSZ_REG_V28, - /* SystemZ_V29 = 63 */ SYSZ_REG_V29, - /* SystemZ_V30 = 64 */ SYSZ_REG_V30, - /* SystemZ_V31 = 65 */ SYSZ_REG_V31, - /* SystemZ_F0D = 66 */ SYSZ_REG_F0, - /* SystemZ_F1D = 67 */ SYSZ_REG_F1, - /* SystemZ_F2D = 68 */ SYSZ_REG_F2, - /* SystemZ_F3D = 69 */ SYSZ_REG_F3, - /* SystemZ_F4D = 70 */ SYSZ_REG_F4, - /* SystemZ_F5D = 71 */ SYSZ_REG_F5, - /* SystemZ_F6D = 72 */ SYSZ_REG_F6, - /* SystemZ_F7D = 73 */ SYSZ_REG_F7, - /* SystemZ_F8D = 74 */ SYSZ_REG_F8, - /* SystemZ_F9D = 75 */ SYSZ_REG_F9, - /* SystemZ_F10D = 76 */ SYSZ_REG_F10, - /* SystemZ_F11D = 77 */ SYSZ_REG_F11, - /* SystemZ_F12D = 78 */ SYSZ_REG_F12, - /* SystemZ_F13D = 79 */ SYSZ_REG_F13, - /* SystemZ_F14D = 80 */ SYSZ_REG_F14, - /* SystemZ_F15D = 81 */ SYSZ_REG_F15, - /* SystemZ_F16D = 82 */ SYSZ_REG_F16, - /* SystemZ_F17D = 83 */ SYSZ_REG_F17, - /* SystemZ_F18D = 84 */ SYSZ_REG_F18, - /* SystemZ_F19D = 85 */ SYSZ_REG_F19, - /* SystemZ_F20D = 86 */ SYSZ_REG_F20, - /* SystemZ_F21D = 87 */ SYSZ_REG_F21, - /* SystemZ_F22D = 88 */ SYSZ_REG_F22, - /* SystemZ_F23D = 89 */ SYSZ_REG_F23, - /* SystemZ_F24D = 90 */ SYSZ_REG_F24, - /* SystemZ_F25D = 91 */ SYSZ_REG_F25, - /* SystemZ_F26D = 92 */ SYSZ_REG_F26, - /* SystemZ_F27D = 93 */ SYSZ_REG_F27, - /* SystemZ_F28D = 94 */ SYSZ_REG_F28, - /* SystemZ_F29D = 95 */ SYSZ_REG_F29, - /* SystemZ_F30D = 96 */ SYSZ_REG_F30, - /* SystemZ_F31D = 97 */ SYSZ_REG_F31, - /* SystemZ_F0Q = 98 */ SYSZ_REG_F0, - /* SystemZ_F1Q = 99 */ SYSZ_REG_F1, - /* SystemZ_F4Q = 100 */ SYSZ_REG_F4, - /* SystemZ_F5Q = 101 */ SYSZ_REG_F5, - /* SystemZ_F8Q = 102 */ SYSZ_REG_F8, - /* SystemZ_F9Q = 103 */ SYSZ_REG_F9, - /* SystemZ_F12Q = 104 */ SYSZ_REG_F12, - /* SystemZ_F13Q = 105 */ SYSZ_REG_F13, - /* SystemZ_F0S = 106 */ SYSZ_REG_F0, - /* SystemZ_F1S = 107 */ SYSZ_REG_F1, - /* SystemZ_F2S = 108 */ SYSZ_REG_F2, - /* SystemZ_F3S = 109 */ SYSZ_REG_F3, - /* SystemZ_F4S = 110 */ SYSZ_REG_F4, - /* SystemZ_F5S = 111 */ SYSZ_REG_F5, - /* SystemZ_F6S = 112 */ SYSZ_REG_F6, - /* SystemZ_F7S = 113 */ SYSZ_REG_F7, - /* SystemZ_F8S = 114 */ SYSZ_REG_F8, - /* SystemZ_F9S = 115 */ SYSZ_REG_F9, - /* SystemZ_F10S = 116 */ SYSZ_REG_F10, - /* SystemZ_F11S = 117 */ SYSZ_REG_F11, - /* SystemZ_F12S = 118 */ SYSZ_REG_F12, - /* SystemZ_F13S = 119 */ SYSZ_REG_F13, - /* SystemZ_F14S = 120 */ SYSZ_REG_F14, - /* SystemZ_F15S = 121 */ SYSZ_REG_F15, - /* SystemZ_F16S = 122 */ SYSZ_REG_F16, - /* SystemZ_F17S = 123 */ SYSZ_REG_F17, - /* SystemZ_F18S = 124 */ SYSZ_REG_F18, - /* SystemZ_F19S = 125 */ SYSZ_REG_F19, - /* SystemZ_F20S = 126 */ SYSZ_REG_F20, - /* SystemZ_F21S = 127 */ SYSZ_REG_F21, - /* SystemZ_F22S = 128 */ SYSZ_REG_F22, - /* SystemZ_F23S = 129 */ SYSZ_REG_F23, - /* SystemZ_F24S = 130 */ SYSZ_REG_F24, - /* SystemZ_F25S = 131 */ SYSZ_REG_F25, - /* SystemZ_F26S = 132 */ SYSZ_REG_F26, - /* SystemZ_F27S = 133 */ SYSZ_REG_F27, - /* SystemZ_F28S = 134 */ SYSZ_REG_F28, - /* SystemZ_F29S = 135 */ SYSZ_REG_F29, - /* SystemZ_F30S = 136 */ SYSZ_REG_F30, - /* SystemZ_F31S = 137 */ SYSZ_REG_F31, - /* SystemZ_R0D = 138 */ SYSZ_REG_0, - /* SystemZ_R1D = 139 */ SYSZ_REG_1, - /* SystemZ_R2D = 140 */ SYSZ_REG_2, - /* SystemZ_R3D = 141 */ SYSZ_REG_3, - /* SystemZ_R4D = 142 */ SYSZ_REG_4, - /* SystemZ_R5D = 143 */ SYSZ_REG_5, - /* SystemZ_R6D = 144 */ SYSZ_REG_6, - /* SystemZ_R7D = 145 */ SYSZ_REG_7, - /* SystemZ_R8D = 146 */ SYSZ_REG_8, - /* SystemZ_R9D = 147 */ SYSZ_REG_9, - /* SystemZ_R10D = 148 */ SYSZ_REG_10, - /* SystemZ_R11D = 149 */ SYSZ_REG_11, - /* SystemZ_R12D = 150 */ SYSZ_REG_12, - /* SystemZ_R13D = 151 */ SYSZ_REG_13, - /* SystemZ_R14D = 152 */ SYSZ_REG_14, - /* SystemZ_R15D = 153 */ SYSZ_REG_15, - /* SystemZ_R0H = 154 */ SYSZ_REG_0, - /* SystemZ_R1H = 155 */ SYSZ_REG_1, - /* SystemZ_R2H = 156 */ SYSZ_REG_2, - /* SystemZ_R3H = 157 */ SYSZ_REG_3, - /* SystemZ_R4H = 158 */ SYSZ_REG_4, - /* SystemZ_R5H = 159 */ SYSZ_REG_5, - /* SystemZ_R6H = 160 */ SYSZ_REG_6, - /* SystemZ_R7H = 161 */ SYSZ_REG_7, - /* SystemZ_R8H = 162 */ SYSZ_REG_8, - /* SystemZ_R9H = 163 */ SYSZ_REG_9, - /* SystemZ_R10H = 164 */ SYSZ_REG_10, - /* SystemZ_R11H = 165 */ SYSZ_REG_11, - /* SystemZ_R12H = 166 */ SYSZ_REG_12, - /* SystemZ_R13H = 167 */ SYSZ_REG_13, - /* SystemZ_R14H = 168 */ SYSZ_REG_14, - /* SystemZ_R15H = 169 */ SYSZ_REG_15, - /* SystemZ_R0L = 170 */ SYSZ_REG_0, - /* SystemZ_R1L = 171 */ SYSZ_REG_1, - /* SystemZ_R2L = 172 */ SYSZ_REG_2, - /* SystemZ_R3L = 173 */ SYSZ_REG_3, - /* SystemZ_R4L = 174 */ SYSZ_REG_4, - /* SystemZ_R5L = 175 */ SYSZ_REG_5, - /* SystemZ_R6L = 176 */ SYSZ_REG_6, - /* SystemZ_R7L = 177 */ SYSZ_REG_7, - /* SystemZ_R8L = 178 */ SYSZ_REG_8, - /* SystemZ_R9L = 179 */ SYSZ_REG_9, - /* SystemZ_R10L = 180 */ SYSZ_REG_10, - /* SystemZ_R11L = 181 */ SYSZ_REG_11, - /* SystemZ_R12L = 182 */ SYSZ_REG_12, - /* SystemZ_R13L = 183 */ SYSZ_REG_13, - /* SystemZ_R14L = 184 */ SYSZ_REG_14, - /* SystemZ_R15L = 185 */ SYSZ_REG_15, - /* SystemZ_R0Q = 186 */ SYSZ_REG_0, - /* SystemZ_R2Q = 187 */ SYSZ_REG_2, - /* SystemZ_R4Q = 188 */ SYSZ_REG_4, - /* SystemZ_R6Q = 189 */ SYSZ_REG_6, - /* SystemZ_R8Q = 190 */ SYSZ_REG_8, - /* SystemZ_R10Q = 191 */ SYSZ_REG_10, - /* SystemZ_R12Q = 192 */ SYSZ_REG_12, - /* SystemZ_R14Q = 193 */ SYSZ_REG_14, - }; - - if (r < ARR_SIZE(map)) - return map[r]; - - // cannot find this register - return 0; + if (!detail_is_set(MI)) + return; + CS_ASSERT((map_get_op_type(MI, op_num) & ~CS_OP_MEM) == CS_OP_REG); + + SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_REG; + SystemZ_get_detail_op(MI, 0)->reg = Reg; + SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num); + SystemZ_inc_op_count(MI); } +void SystemZ_set_detail_op_mem(MCInst *MI, unsigned op_num, systemz_reg base, int64_t disp, uint64_t length, systemz_reg index, systemz_addr_mode am) +{ + if (!detail_is_set(MI)) + return; + SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_MEM; + SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num); + SystemZ_get_detail_op(MI, 0)->mem.am = am; + switch(am) { + default: + CS_ASSERT(0 && "Address mode not handled\n"); + break; + case SYSTEMZ_AM_BD: + SystemZ_get_detail_op(MI, 0)->mem.base = base; + SystemZ_get_detail_op(MI, 0)->mem.disp = disp; + break; + case SYSTEMZ_AM_BDX: + case SYSTEMZ_AM_BDV: + SystemZ_get_detail_op(MI, 0)->mem.base = base; + SystemZ_get_detail_op(MI, 0)->mem.disp = disp; + SystemZ_get_detail_op(MI, 0)->mem.index = index; + break; + case SYSTEMZ_AM_BDL: + SystemZ_get_detail_op(MI, 0)->mem.base = base; + SystemZ_get_detail_op(MI, 0)->mem.disp = disp; + SystemZ_get_detail_op(MI, 0)->mem.length = length; + break; + case SYSTEMZ_AM_BDR: + SystemZ_get_detail_op(MI, 0)->mem.base = base; + SystemZ_get_detail_op(MI, 0)->mem.disp = disp; + SystemZ_get_detail_op(MI, 0)->mem.length = length; + break; + } + SystemZ_inc_op_count(MI); +} + +#endif + #endif diff --git a/arch/SystemZ/SystemZMapping.h b/arch/SystemZ/SystemZMapping.h index 0f8909cea2..30ec2627c5 100644 --- a/arch/SystemZ/SystemZMapping.h +++ b/arch/SystemZ/SystemZMapping.h @@ -1,10 +1,16 @@ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ -#ifndef CS_SYSZ_MAP_H -#define CS_SYSZ_MAP_H +#ifndef CS_SYSTEMZ_MAP_H +#define CS_SYSTEMZ_MAP_H -#include "capstone/capstone.h" +#include + +#include "../../cs_priv.h" + +typedef enum { +#include "SystemZGenCSOpGroup.inc" +} systemz_op_group; // return name of register in friendly string const char *SystemZ_reg_name(csh handle, unsigned int reg); @@ -16,8 +22,29 @@ const char *SystemZ_insn_name(csh handle, unsigned int id); const char *SystemZ_group_name(csh handle, unsigned int id); -// map internal raw register to 'public' register -sysz_reg SystemZ_map_register(unsigned int r); - -#endif +void SystemZ_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info); +bool SystemZ_getInstruction(csh handle, const uint8_t *bytes, size_t bytes_len, + MCInst *MI, uint16_t *size, uint64_t address, + void *info); +void SystemZ_init_mri(MCRegisterInfo *MRI); +void SystemZ_init_cs_detail(MCInst *MI); + +void SystemZ_set_detail_op_reg(MCInst *MI, unsigned op_num, systemz_reg Reg); +void SystemZ_set_detail_op_imm(MCInst *MI, unsigned op_num, int64_t Imm, size_t width); +void SystemZ_set_detail_op_mem(MCInst *MI, unsigned op_num, systemz_reg base, int64_t disp, uint64_t length, systemz_reg index, systemz_addr_mode am); +void SystemZ_add_cs_detail(MCInst *MI, int /* systemz_op_group */ op_group, + va_list args); + +static inline void add_cs_detail(MCInst *MI, + int /* aarch64_op_group */ op_group, ...) +{ + if (!MI->flat_insn->detail) + return; + va_list args; + va_start(args, op_group); + SystemZ_add_cs_detail(MI, op_group, args); + va_end(args); +} + +#endif // CS_SYSTEMZ_MAP_H diff --git a/arch/SystemZ/SystemZMappingInsn.inc b/arch/SystemZ/SystemZMappingInsn.inc deleted file mode 100644 index 949b65b6db..0000000000 --- a/arch/SystemZ/SystemZMappingInsn.inc +++ /dev/null @@ -1,14175 +0,0 @@ -// This is auto-gen data for Capstone engine (www.capstone-engine.org) -// By Nguyen Anh Quynh - -{ - SystemZ_A, SYSZ_INS_A, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AD, SYSZ_INS_AD, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ADB, SYSZ_INS_ADB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ADBR, SYSZ_INS_ADBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ADR, SYSZ_INS_ADR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ADTR, SYSZ_INS_ADTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ADTRA, SYSZ_INS_ADTRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_AE, SYSZ_INS_AE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AEB, SYSZ_INS_AEB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AEBR, SYSZ_INS_AEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AER, SYSZ_INS_AER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AFI, SYSZ_INS_AFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AG, SYSZ_INS_AG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AGF, SYSZ_INS_AGF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AGFI, SYSZ_INS_AGFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AGFR, SYSZ_INS_AGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AGH, SYSZ_INS_AGH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_AGHI, SYSZ_INS_AGHI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AGHIK, SYSZ_INS_AGHIK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_AGR, SYSZ_INS_AGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AGRK, SYSZ_INS_AGRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_AGSI, SYSZ_INS_AGSI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AH, SYSZ_INS_AH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AHHHR, SYSZ_INS_AHHHR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_AHHLR, SYSZ_INS_AHHLR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_AHI, SYSZ_INS_AHI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AHIK, SYSZ_INS_AHIK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_AHY, SYSZ_INS_AHY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AIH, SYSZ_INS_AIH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_AL, SYSZ_INS_AL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALC, SYSZ_INS_ALC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALCG, SYSZ_INS_ALCG, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALCGR, SYSZ_INS_ALCGR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALCR, SYSZ_INS_ALCR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALFI, SYSZ_INS_ALFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALG, SYSZ_INS_ALG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALGF, SYSZ_INS_ALGF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALGFI, SYSZ_INS_ALGFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALGFR, SYSZ_INS_ALGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALGHSIK, SYSZ_INS_ALGHSIK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALGR, SYSZ_INS_ALGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALGRK, SYSZ_INS_ALGRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALGSI, SYSZ_INS_ALGSI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALHHHR, SYSZ_INS_ALHHHR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALHHLR, SYSZ_INS_ALHHLR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALHSIK, SYSZ_INS_ALHSIK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALR, SYSZ_INS_ALR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALRK, SYSZ_INS_ALRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALSI, SYSZ_INS_ALSI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALSIH, SYSZ_INS_ALSIH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALSIHN, SYSZ_INS_ALSIHN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALY, SYSZ_INS_ALY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AP, SYSZ_INS_AP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AR, SYSZ_INS_AR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ARK, SYSZ_INS_ARK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ASI, SYSZ_INS_ASI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AU, SYSZ_INS_AU, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AUR, SYSZ_INS_AUR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AW, SYSZ_INS_AW, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AWR, SYSZ_INS_AWR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AXBR, SYSZ_INS_AXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AXR, SYSZ_INS_AXR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AXTR, SYSZ_INS_AXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AXTRA, SYSZ_INS_AXTRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_AY, SYSZ_INS_AY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_B, SYSZ_INS_B, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAKR, SYSZ_INS_BAKR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BAL, SYSZ_INS_BAL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BALR, SYSZ_INS_BALR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BAS, SYSZ_INS_BAS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BASR, SYSZ_INS_BASR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BASSM, SYSZ_INS_BASSM, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BAsmE, SYSZ_INS_BE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmH, SYSZ_INS_BH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmHE, SYSZ_INS_BHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmL, SYSZ_INS_BL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmLE, SYSZ_INS_BLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmLH, SYSZ_INS_BLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmM, SYSZ_INS_BM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNE, SYSZ_INS_BNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNH, SYSZ_INS_BNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNHE, SYSZ_INS_BNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNL, SYSZ_INS_BNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNLE, SYSZ_INS_BNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNLH, SYSZ_INS_BNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNM, SYSZ_INS_BNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNO, SYSZ_INS_BNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNP, SYSZ_INS_BNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNZ, SYSZ_INS_BNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmO, SYSZ_INS_BO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmP, SYSZ_INS_BP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmZ, SYSZ_INS_BZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BCAsm, SYSZ_INS_BC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BCRAsm, SYSZ_INS_BCR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BCT, SYSZ_INS_BCT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BCTG, SYSZ_INS_BCTG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BCTGR, SYSZ_INS_BCTGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BCTR, SYSZ_INS_BCTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BI, SYSZ_INS_BI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmE, SYSZ_INS_BIE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmH, SYSZ_INS_BIH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmHE, SYSZ_INS_BIHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmL, SYSZ_INS_BIL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmLE, SYSZ_INS_BILE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmLH, SYSZ_INS_BILH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmM, SYSZ_INS_BIM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNE, SYSZ_INS_BINE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNH, SYSZ_INS_BINH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNHE, SYSZ_INS_BINHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNL, SYSZ_INS_BINL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNLE, SYSZ_INS_BINLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNLH, SYSZ_INS_BINLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNM, SYSZ_INS_BINM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNO, SYSZ_INS_BINO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNP, SYSZ_INS_BINP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNZ, SYSZ_INS_BINZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmO, SYSZ_INS_BIO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmP, SYSZ_INS_BIP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmZ, SYSZ_INS_BIZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BICAsm, SYSZ_INS_BIC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BPP, SYSZ_INS_BPP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_EXECUTIONHINT, 0 }, 0, 0 -#endif -}, -{ - SystemZ_BPRP, SYSZ_INS_BPRP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_EXECUTIONHINT, 0 }, 0, 0 -#endif -}, -{ - SystemZ_BR, SYSZ_INS_BR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAS, SYSZ_INS_BRAS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BRASL, SYSZ_INS_BRASL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BRAsmE, SYSZ_INS_BER, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmH, SYSZ_INS_BHR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmHE, SYSZ_INS_BHER, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmL, SYSZ_INS_BLR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmLE, SYSZ_INS_BLER, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmLH, SYSZ_INS_BLHR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmM, SYSZ_INS_BMR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNE, SYSZ_INS_BNER, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNH, SYSZ_INS_BNHR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNHE, SYSZ_INS_BNHER, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNL, SYSZ_INS_BNLR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNLE, SYSZ_INS_BNLER, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNLH, SYSZ_INS_BNLHR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNM, SYSZ_INS_BNMR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNO, SYSZ_INS_BNOR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNP, SYSZ_INS_BNPR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNZ, SYSZ_INS_BNZR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmO, SYSZ_INS_BOR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmP, SYSZ_INS_BPR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmZ, SYSZ_INS_BZR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRCAsm, SYSZ_INS_BRC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BRCLAsm, SYSZ_INS_BRCL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BRCT, SYSZ_INS_BRCT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BRCTG, SYSZ_INS_BRCTG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BRCTH, SYSZ_INS_BRCTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 1, 0 -#endif -}, -{ - SystemZ_BRXH, SYSZ_INS_BRXH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BRXHG, SYSZ_INS_BRXHG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BRXLE, SYSZ_INS_BRXLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BRXLG, SYSZ_INS_BRXLG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BSA, SYSZ_INS_BSA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BSG, SYSZ_INS_BSG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BSM, SYSZ_INS_BSM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BXH, SYSZ_INS_BXH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BXHG, SYSZ_INS_BXHG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BXLE, SYSZ_INS_BXLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BXLEG, SYSZ_INS_BXLEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_C, SYSZ_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CD, SYSZ_INS_CD, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDB, SYSZ_INS_CDB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDBR, SYSZ_INS_CDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDFBR, SYSZ_INS_CDFBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDFBRA, SYSZ_INS_CDFBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDFR, SYSZ_INS_CDFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDFTR, SYSZ_INS_CDFTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDGBR, SYSZ_INS_CDGBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDGBRA, SYSZ_INS_CDGBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDGR, SYSZ_INS_CDGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDGTR, SYSZ_INS_CDGTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDGTRA, SYSZ_INS_CDGTRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDLFBR, SYSZ_INS_CDLFBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDLFTR, SYSZ_INS_CDLFTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDLGBR, SYSZ_INS_CDLGBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDLGTR, SYSZ_INS_CDLGTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDPT, SYSZ_INS_CDPT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DFPPACKEDCONVERSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDR, SYSZ_INS_CDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDS, SYSZ_INS_CDS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDSG, SYSZ_INS_CDSG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDSTR, SYSZ_INS_CDSTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDSY, SYSZ_INS_CDSY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDTR, SYSZ_INS_CDTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDUTR, SYSZ_INS_CDUTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDZT, SYSZ_INS_CDZT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DFPZONEDCONVERSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CE, SYSZ_INS_CE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEB, SYSZ_INS_CEB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEBR, SYSZ_INS_CEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEDTR, SYSZ_INS_CEDTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEFBR, SYSZ_INS_CEFBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEFBRA, SYSZ_INS_CEFBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEFR, SYSZ_INS_CEFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEGBR, SYSZ_INS_CEGBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEGBRA, SYSZ_INS_CEGBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEGR, SYSZ_INS_CEGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CELFBR, SYSZ_INS_CELFBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CELGBR, SYSZ_INS_CELGBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CER, SYSZ_INS_CER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEXTR, SYSZ_INS_CEXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFC, SYSZ_INS_CFC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, 0 }, { SYSZ_REG_CC, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFDBR, SYSZ_INS_CFDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFDBRA, SYSZ_INS_CFDBRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFDR, SYSZ_INS_CFDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFDTR, SYSZ_INS_CFDTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFEBR, SYSZ_INS_CFEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFEBRA, SYSZ_INS_CFEBRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFER, SYSZ_INS_CFER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFI, SYSZ_INS_CFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFXBR, SYSZ_INS_CFXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFXBRA, SYSZ_INS_CFXBRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFXR, SYSZ_INS_CFXR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFXTR, SYSZ_INS_CFXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CG, SYSZ_INS_CG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGDBR, SYSZ_INS_CGDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGDBRA, SYSZ_INS_CGDBRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGDR, SYSZ_INS_CGDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGDTR, SYSZ_INS_CGDTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGDTRA, SYSZ_INS_CGDTRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGEBR, SYSZ_INS_CGEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGEBRA, SYSZ_INS_CGEBRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGER, SYSZ_INS_CGER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGF, SYSZ_INS_CGF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGFI, SYSZ_INS_CGFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGFR, SYSZ_INS_CGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGFRL, SYSZ_INS_CGFRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGH, SYSZ_INS_CGH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGHI, SYSZ_INS_CGHI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGHRL, SYSZ_INS_CGHRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGHSI, SYSZ_INS_CGHSI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGIBAsm, SYSZ_INS_CGIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmE, SYSZ_INS_CGIBE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmH, SYSZ_INS_CGIBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmHE, SYSZ_INS_CGIBHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmL, SYSZ_INS_CGIBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmLE, SYSZ_INS_CGIBLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmLH, SYSZ_INS_CGIBLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmNE, SYSZ_INS_CGIBNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmNH, SYSZ_INS_CGIBNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmNHE, SYSZ_INS_CGIBNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmNL, SYSZ_INS_CGIBNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmNLE, SYSZ_INS_CGIBNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmNLH, SYSZ_INS_CGIBNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIJAsm, SYSZ_INS_CGIJ, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmE, SYSZ_INS_CGIJE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmH, SYSZ_INS_CGIJH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmHE, SYSZ_INS_CGIJHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmL, SYSZ_INS_CGIJL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmLE, SYSZ_INS_CGIJLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmLH, SYSZ_INS_CGIJLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmNE, SYSZ_INS_CGIJNE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmNH, SYSZ_INS_CGIJNH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmNHE, SYSZ_INS_CGIJNHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmNL, SYSZ_INS_CGIJNL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmNLE, SYSZ_INS_CGIJNLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmNLH, SYSZ_INS_CGIJNLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGITAsm, SYSZ_INS_CGIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmE, SYSZ_INS_CGITE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmH, SYSZ_INS_CGITH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmHE, SYSZ_INS_CGITHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmL, SYSZ_INS_CGITL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmLE, SYSZ_INS_CGITLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmLH, SYSZ_INS_CGITLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmNE, SYSZ_INS_CGITNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmNH, SYSZ_INS_CGITNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmNHE, SYSZ_INS_CGITNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmNL, SYSZ_INS_CGITNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmNLE, SYSZ_INS_CGITNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmNLH, SYSZ_INS_CGITNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGR, SYSZ_INS_CGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRBAsm, SYSZ_INS_CGRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmE, SYSZ_INS_CGRBE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmH, SYSZ_INS_CGRBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmHE, SYSZ_INS_CGRBHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmL, SYSZ_INS_CGRBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmLE, SYSZ_INS_CGRBLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmLH, SYSZ_INS_CGRBLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmNE, SYSZ_INS_CGRBNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmNH, SYSZ_INS_CGRBNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmNHE, SYSZ_INS_CGRBNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmNL, SYSZ_INS_CGRBNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmNLE, SYSZ_INS_CGRBNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmNLH, SYSZ_INS_CGRBNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRJAsm, SYSZ_INS_CGRJ, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmE, SYSZ_INS_CGRJE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmH, SYSZ_INS_CGRJH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmHE, SYSZ_INS_CGRJHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmL, SYSZ_INS_CGRJL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmLE, SYSZ_INS_CGRJLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmLH, SYSZ_INS_CGRJLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmNE, SYSZ_INS_CGRJNE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmNH, SYSZ_INS_CGRJNH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmNHE, SYSZ_INS_CGRJNHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmNL, SYSZ_INS_CGRJNL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmNLE, SYSZ_INS_CGRJNLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmNLH, SYSZ_INS_CGRJNLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRL, SYSZ_INS_CGRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsm, SYSZ_INS_CGRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmE, SYSZ_INS_CGRTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmH, SYSZ_INS_CGRTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmHE, SYSZ_INS_CGRTHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmL, SYSZ_INS_CGRTL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmLE, SYSZ_INS_CGRTLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmLH, SYSZ_INS_CGRTLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmNE, SYSZ_INS_CGRTNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmNH, SYSZ_INS_CGRTNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmNHE, SYSZ_INS_CGRTNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmNL, SYSZ_INS_CGRTNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmNLE, SYSZ_INS_CGRTNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmNLH, SYSZ_INS_CGRTNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGXBR, SYSZ_INS_CGXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGXBRA, SYSZ_INS_CGXBRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGXR, SYSZ_INS_CGXR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGXTR, SYSZ_INS_CGXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGXTRA, SYSZ_INS_CGXTRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CH, SYSZ_INS_CH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CHF, SYSZ_INS_CHF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CHHR, SYSZ_INS_CHHR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CHHSI, SYSZ_INS_CHHSI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CHI, SYSZ_INS_CHI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CHLR, SYSZ_INS_CHLR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CHRL, SYSZ_INS_CHRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CHSI, SYSZ_INS_CHSI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CHY, SYSZ_INS_CHY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CIBAsm, SYSZ_INS_CIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmE, SYSZ_INS_CIBE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmH, SYSZ_INS_CIBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmHE, SYSZ_INS_CIBHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmL, SYSZ_INS_CIBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmLE, SYSZ_INS_CIBLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmLH, SYSZ_INS_CIBLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmNE, SYSZ_INS_CIBNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmNH, SYSZ_INS_CIBNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmNHE, SYSZ_INS_CIBNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmNL, SYSZ_INS_CIBNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmNLE, SYSZ_INS_CIBNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmNLH, SYSZ_INS_CIBNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIH, SYSZ_INS_CIH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CIJAsm, SYSZ_INS_CIJ, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmE, SYSZ_INS_CIJE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmH, SYSZ_INS_CIJH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmHE, SYSZ_INS_CIJHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmL, SYSZ_INS_CIJL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmLE, SYSZ_INS_CIJLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmLH, SYSZ_INS_CIJLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmNE, SYSZ_INS_CIJNE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmNH, SYSZ_INS_CIJNH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmNHE, SYSZ_INS_CIJNHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmNL, SYSZ_INS_CIJNL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmNLE, SYSZ_INS_CIJNLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmNLH, SYSZ_INS_CIJNLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CITAsm, SYSZ_INS_CIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmE, SYSZ_INS_CITE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmH, SYSZ_INS_CITH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmHE, SYSZ_INS_CITHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmL, SYSZ_INS_CITL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmLE, SYSZ_INS_CITLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmLH, SYSZ_INS_CITLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmNE, SYSZ_INS_CITNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmNH, SYSZ_INS_CITNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmNHE, SYSZ_INS_CITNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmNL, SYSZ_INS_CITNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmNLE, SYSZ_INS_CITNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmNLH, SYSZ_INS_CITNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CKSM, SYSZ_INS_CKSM, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CL, SYSZ_INS_CL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLC, SYSZ_INS_CLC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLCL, SYSZ_INS_CLCL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLCLE, SYSZ_INS_CLCLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLCLU, SYSZ_INS_CLCLU, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFDBR, SYSZ_INS_CLFDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFDTR, SYSZ_INS_CLFDTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFEBR, SYSZ_INS_CLFEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFHSI, SYSZ_INS_CLFHSI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFI, SYSZ_INS_CLFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsm, SYSZ_INS_CLFIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmE, SYSZ_INS_CLFITE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmH, SYSZ_INS_CLFITH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmHE, SYSZ_INS_CLFITHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmL, SYSZ_INS_CLFITL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmLE, SYSZ_INS_CLFITLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmLH, SYSZ_INS_CLFITLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmNE, SYSZ_INS_CLFITNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmNH, SYSZ_INS_CLFITNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmNHE, SYSZ_INS_CLFITNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmNL, SYSZ_INS_CLFITNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmNLE, SYSZ_INS_CLFITNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmNLH, SYSZ_INS_CLFITNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFXBR, SYSZ_INS_CLFXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFXTR, SYSZ_INS_CLFXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLG, SYSZ_INS_CLG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGDBR, SYSZ_INS_CLGDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGDTR, SYSZ_INS_CLGDTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGEBR, SYSZ_INS_CLGEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGF, SYSZ_INS_CLGF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGFI, SYSZ_INS_CLGFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGFR, SYSZ_INS_CLGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGFRL, SYSZ_INS_CLGFRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGHRL, SYSZ_INS_CLGHRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGHSI, SYSZ_INS_CLGHSI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGIBAsm, SYSZ_INS_CLGIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmE, SYSZ_INS_CLGIBE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmH, SYSZ_INS_CLGIBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmHE, SYSZ_INS_CLGIBHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmL, SYSZ_INS_CLGIBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmLE, SYSZ_INS_CLGIBLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmLH, SYSZ_INS_CLGIBLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmNE, SYSZ_INS_CLGIBNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmNH, SYSZ_INS_CLGIBNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmNHE, SYSZ_INS_CLGIBNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmNL, SYSZ_INS_CLGIBNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmNLE, SYSZ_INS_CLGIBNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmNLH, SYSZ_INS_CLGIBNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIJAsm, SYSZ_INS_CLGIJ, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmE, SYSZ_INS_CLGIJE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmH, SYSZ_INS_CLGIJH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmHE, SYSZ_INS_CLGIJHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmL, SYSZ_INS_CLGIJL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmLE, SYSZ_INS_CLGIJLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmLH, SYSZ_INS_CLGIJLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmNE, SYSZ_INS_CLGIJNE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmNH, SYSZ_INS_CLGIJNH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmNHE, SYSZ_INS_CLGIJNHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmNL, SYSZ_INS_CLGIJNL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmNLE, SYSZ_INS_CLGIJNLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmNLH, SYSZ_INS_CLGIJNLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGITAsm, SYSZ_INS_CLGIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmE, SYSZ_INS_CLGITE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmH, SYSZ_INS_CLGITH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmHE, SYSZ_INS_CLGITHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmL, SYSZ_INS_CLGITL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmLE, SYSZ_INS_CLGITLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmLH, SYSZ_INS_CLGITLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmNE, SYSZ_INS_CLGITNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmNH, SYSZ_INS_CLGITNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmNHE, SYSZ_INS_CLGITNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmNL, SYSZ_INS_CLGITNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmNLE, SYSZ_INS_CLGITNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmNLH, SYSZ_INS_CLGITNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGR, SYSZ_INS_CLGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRBAsm, SYSZ_INS_CLGRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmE, SYSZ_INS_CLGRBE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmH, SYSZ_INS_CLGRBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmHE, SYSZ_INS_CLGRBHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmL, SYSZ_INS_CLGRBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmLE, SYSZ_INS_CLGRBLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmLH, SYSZ_INS_CLGRBLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmNE, SYSZ_INS_CLGRBNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmNH, SYSZ_INS_CLGRBNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmNHE, SYSZ_INS_CLGRBNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmNL, SYSZ_INS_CLGRBNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmNLE, SYSZ_INS_CLGRBNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmNLH, SYSZ_INS_CLGRBNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRJAsm, SYSZ_INS_CLGRJ, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmE, SYSZ_INS_CLGRJE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmH, SYSZ_INS_CLGRJH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmHE, SYSZ_INS_CLGRJHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmL, SYSZ_INS_CLGRJL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmLE, SYSZ_INS_CLGRJLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmLH, SYSZ_INS_CLGRJLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmNE, SYSZ_INS_CLGRJNE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmNH, SYSZ_INS_CLGRJNH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmNHE, SYSZ_INS_CLGRJNHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmNL, SYSZ_INS_CLGRJNL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmNLE, SYSZ_INS_CLGRJNLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmNLH, SYSZ_INS_CLGRJNLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRL, SYSZ_INS_CLGRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsm, SYSZ_INS_CLGRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmE, SYSZ_INS_CLGRTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmH, SYSZ_INS_CLGRTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmHE, SYSZ_INS_CLGRTHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmL, SYSZ_INS_CLGRTL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmLE, SYSZ_INS_CLGRTLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmLH, SYSZ_INS_CLGRTLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmNE, SYSZ_INS_CLGRTNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmNH, SYSZ_INS_CLGRTNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmNHE, SYSZ_INS_CLGRTNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmNL, SYSZ_INS_CLGRTNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmNLE, SYSZ_INS_CLGRTNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmNLH, SYSZ_INS_CLGRTNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsm, SYSZ_INS_CLGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmE, SYSZ_INS_CLGTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmH, SYSZ_INS_CLGTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmHE, SYSZ_INS_CLGTHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmL, SYSZ_INS_CLGTL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmLE, SYSZ_INS_CLGTLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmLH, SYSZ_INS_CLGTLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmNE, SYSZ_INS_CLGTNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmNH, SYSZ_INS_CLGTNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmNHE, SYSZ_INS_CLGTNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmNL, SYSZ_INS_CLGTNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmNLE, SYSZ_INS_CLGTNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmNLH, SYSZ_INS_CLGTNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGXBR, SYSZ_INS_CLGXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGXTR, SYSZ_INS_CLGXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLHF, SYSZ_INS_CLHF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLHHR, SYSZ_INS_CLHHR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLHHSI, SYSZ_INS_CLHHSI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLHLR, SYSZ_INS_CLHLR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLHRL, SYSZ_INS_CLHRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLI, SYSZ_INS_CLI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLIBAsm, SYSZ_INS_CLIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmE, SYSZ_INS_CLIBE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmH, SYSZ_INS_CLIBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmHE, SYSZ_INS_CLIBHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmL, SYSZ_INS_CLIBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmLE, SYSZ_INS_CLIBLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmLH, SYSZ_INS_CLIBLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmNE, SYSZ_INS_CLIBNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmNH, SYSZ_INS_CLIBNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmNHE, SYSZ_INS_CLIBNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmNL, SYSZ_INS_CLIBNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmNLE, SYSZ_INS_CLIBNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmNLH, SYSZ_INS_CLIBNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIH, SYSZ_INS_CLIH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLIJAsm, SYSZ_INS_CLIJ, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmE, SYSZ_INS_CLIJE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmH, SYSZ_INS_CLIJH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmHE, SYSZ_INS_CLIJHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmL, SYSZ_INS_CLIJL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmLE, SYSZ_INS_CLIJLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmLH, SYSZ_INS_CLIJLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmNE, SYSZ_INS_CLIJNE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmNH, SYSZ_INS_CLIJNH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmNHE, SYSZ_INS_CLIJNHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmNL, SYSZ_INS_CLIJNL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmNLE, SYSZ_INS_CLIJNLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmNLH, SYSZ_INS_CLIJNLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIY, SYSZ_INS_CLIY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLM, SYSZ_INS_CLM, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLMH, SYSZ_INS_CLMH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLMY, SYSZ_INS_CLMY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLR, SYSZ_INS_CLR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRBAsm, SYSZ_INS_CLRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmE, SYSZ_INS_CLRBE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmH, SYSZ_INS_CLRBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmHE, SYSZ_INS_CLRBHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmL, SYSZ_INS_CLRBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmLE, SYSZ_INS_CLRBLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmLH, SYSZ_INS_CLRBLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmNE, SYSZ_INS_CLRBNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmNH, SYSZ_INS_CLRBNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmNHE, SYSZ_INS_CLRBNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmNL, SYSZ_INS_CLRBNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmNLE, SYSZ_INS_CLRBNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmNLH, SYSZ_INS_CLRBNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRJAsm, SYSZ_INS_CLRJ, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmE, SYSZ_INS_CLRJE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmH, SYSZ_INS_CLRJH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmHE, SYSZ_INS_CLRJHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmL, SYSZ_INS_CLRJL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmLE, SYSZ_INS_CLRJLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmLH, SYSZ_INS_CLRJLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmNE, SYSZ_INS_CLRJNE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmNH, SYSZ_INS_CLRJNH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmNHE, SYSZ_INS_CLRJNHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmNL, SYSZ_INS_CLRJNL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmNLE, SYSZ_INS_CLRJNLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmNLH, SYSZ_INS_CLRJNLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRL, SYSZ_INS_CLRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsm, SYSZ_INS_CLRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmE, SYSZ_INS_CLRTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmH, SYSZ_INS_CLRTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmHE, SYSZ_INS_CLRTHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmL, SYSZ_INS_CLRTL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmLE, SYSZ_INS_CLRTLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmLH, SYSZ_INS_CLRTLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmNE, SYSZ_INS_CLRTNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmNH, SYSZ_INS_CLRTNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmNHE, SYSZ_INS_CLRTNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmNL, SYSZ_INS_CLRTNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmNLE, SYSZ_INS_CLRTNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmNLH, SYSZ_INS_CLRTNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLST, SYSZ_INS_CLST, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsm, SYSZ_INS_CLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmE, SYSZ_INS_CLTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmH, SYSZ_INS_CLTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmHE, SYSZ_INS_CLTHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmL, SYSZ_INS_CLTL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmLE, SYSZ_INS_CLTLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmLH, SYSZ_INS_CLTLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmNE, SYSZ_INS_CLTNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmNH, SYSZ_INS_CLTNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmNHE, SYSZ_INS_CLTNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmNL, SYSZ_INS_CLTNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmNLE, SYSZ_INS_CLTNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmNLH, SYSZ_INS_CLTNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLY, SYSZ_INS_CLY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CMPSC, SYSZ_INS_CMPSC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, SYSZ_REG_1, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CP, SYSZ_INS_CP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CPDT, SYSZ_INS_CPDT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DFPPACKEDCONVERSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CPSDRdd, SYSZ_INS_CPSDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CPXT, SYSZ_INS_CPXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DFPPACKEDCONVERSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CPYA, SYSZ_INS_CPYA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CR, SYSZ_INS_CR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRBAsm, SYSZ_INS_CRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmE, SYSZ_INS_CRBE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmH, SYSZ_INS_CRBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmHE, SYSZ_INS_CRBHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmL, SYSZ_INS_CRBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmLE, SYSZ_INS_CRBLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmLH, SYSZ_INS_CRBLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmNE, SYSZ_INS_CRBNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmNH, SYSZ_INS_CRBNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmNHE, SYSZ_INS_CRBNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmNL, SYSZ_INS_CRBNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmNLE, SYSZ_INS_CRBNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmNLH, SYSZ_INS_CRBNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRDTE, SYSZ_INS_CRDTE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_ENHANCEDDAT2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRDTEOpt, SYSZ_INS_CRDTE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_ENHANCEDDAT2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRJAsm, SYSZ_INS_CRJ, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmE, SYSZ_INS_CRJE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmH, SYSZ_INS_CRJH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmHE, SYSZ_INS_CRJHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmL, SYSZ_INS_CRJL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmLE, SYSZ_INS_CRJLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmLH, SYSZ_INS_CRJLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmNE, SYSZ_INS_CRJNE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmNH, SYSZ_INS_CRJNH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmNHE, SYSZ_INS_CRJNHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmNL, SYSZ_INS_CRJNL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmNLE, SYSZ_INS_CRJNLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmNLH, SYSZ_INS_CRJNLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRL, SYSZ_INS_CRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsm, SYSZ_INS_CRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmE, SYSZ_INS_CRTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmH, SYSZ_INS_CRTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmHE, SYSZ_INS_CRTHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmL, SYSZ_INS_CRTL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmLE, SYSZ_INS_CRTLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmLH, SYSZ_INS_CRTLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmNE, SYSZ_INS_CRTNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmNH, SYSZ_INS_CRTNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmNHE, SYSZ_INS_CRTNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmNL, SYSZ_INS_CRTNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmNLE, SYSZ_INS_CRTNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmNLH, SYSZ_INS_CRTNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CS, SYSZ_INS_CS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CSCH, SYSZ_INS_CSCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CSDTR, SYSZ_INS_CSDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CSG, SYSZ_INS_CSG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CSP, SYSZ_INS_CSP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CSPG, SYSZ_INS_CSPG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CSST, SYSZ_INS_CSST, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CSXTR, SYSZ_INS_CSXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CSY, SYSZ_INS_CSY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU12, SYSZ_INS_CU12, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU12Opt, SYSZ_INS_CU12, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU14, SYSZ_INS_CU14, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU14Opt, SYSZ_INS_CU14, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU21, SYSZ_INS_CU21, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU21Opt, SYSZ_INS_CU21, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU24, SYSZ_INS_CU24, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU24Opt, SYSZ_INS_CU24, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU41, SYSZ_INS_CU41, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU42, SYSZ_INS_CU42, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CUDTR, SYSZ_INS_CUDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CUSE, SYSZ_INS_CUSE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CUTFU, SYSZ_INS_CUTFU, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CUTFUOpt, SYSZ_INS_CUTFU, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CUUTF, SYSZ_INS_CUUTF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CUUTFOpt, SYSZ_INS_CUUTF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CUXTR, SYSZ_INS_CUXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CVB, SYSZ_INS_CVB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CVBG, SYSZ_INS_CVBG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CVBY, SYSZ_INS_CVBY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CVD, SYSZ_INS_CVD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CVDG, SYSZ_INS_CVDG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CVDY, SYSZ_INS_CVDY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXBR, SYSZ_INS_CXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXFBR, SYSZ_INS_CXFBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXFBRA, SYSZ_INS_CXFBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXFR, SYSZ_INS_CXFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXFTR, SYSZ_INS_CXFTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXGBR, SYSZ_INS_CXGBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXGBRA, SYSZ_INS_CXGBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXGR, SYSZ_INS_CXGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXGTR, SYSZ_INS_CXGTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXGTRA, SYSZ_INS_CXGTRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXLFBR, SYSZ_INS_CXLFBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXLFTR, SYSZ_INS_CXLFTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXLGBR, SYSZ_INS_CXLGBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXLGTR, SYSZ_INS_CXLGTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXPT, SYSZ_INS_CXPT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DFPPACKEDCONVERSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXR, SYSZ_INS_CXR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXSTR, SYSZ_INS_CXSTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXTR, SYSZ_INS_CXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXUTR, SYSZ_INS_CXUTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXZT, SYSZ_INS_CXZT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DFPZONEDCONVERSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CY, SYSZ_INS_CY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CZDT, SYSZ_INS_CZDT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DFPZONEDCONVERSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CZXT, SYSZ_INS_CZXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DFPZONEDCONVERSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_D, SYSZ_INS_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DD, SYSZ_INS_DD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DDB, SYSZ_INS_DDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DDBR, SYSZ_INS_DDBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DDR, SYSZ_INS_DDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DDTR, SYSZ_INS_DDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DDTRA, SYSZ_INS_DDTRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_DE, SYSZ_INS_DE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DEB, SYSZ_INS_DEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DEBR, SYSZ_INS_DEBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DER, SYSZ_INS_DER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DIAG, SYSZ_INS_DIAG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DIDBR, SYSZ_INS_DIDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DIEBR, SYSZ_INS_DIEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DL, SYSZ_INS_DL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DLG, SYSZ_INS_DLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DLGR, SYSZ_INS_DLGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DLR, SYSZ_INS_DLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DP, SYSZ_INS_DP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DR, SYSZ_INS_DR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DSG, SYSZ_INS_DSG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DSGF, SYSZ_INS_DSGF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DSGFR, SYSZ_INS_DSGFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DSGR, SYSZ_INS_DSGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DXBR, SYSZ_INS_DXBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DXR, SYSZ_INS_DXR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DXTR, SYSZ_INS_DXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DXTRA, SYSZ_INS_DXTRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_EAR, SYSZ_INS_EAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ECAG, SYSZ_INS_ECAG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ECCTR, SYSZ_INS_ECCTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ECPGA, SYSZ_INS_ECPGA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ECTG, SYSZ_INS_ECTG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ED, SYSZ_INS_ED, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EDMK, SYSZ_INS_EDMK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EEDTR, SYSZ_INS_EEDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EEXTR, SYSZ_INS_EEXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EFPC, SYSZ_INS_EFPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EPAIR, SYSZ_INS_EPAIR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EPAR, SYSZ_INS_EPAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EPCTR, SYSZ_INS_EPCTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EPSW, SYSZ_INS_EPSW, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EREG, SYSZ_INS_EREG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EREGG, SYSZ_INS_EREGG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ESAIR, SYSZ_INS_ESAIR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ESAR, SYSZ_INS_ESAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ESDTR, SYSZ_INS_ESDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ESEA, SYSZ_INS_ESEA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ESTA, SYSZ_INS_ESTA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ESXTR, SYSZ_INS_ESXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ETND, SYSZ_INS_ETND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_EX, SYSZ_INS_EX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EXRL, SYSZ_INS_EXRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIDBR, SYSZ_INS_FIDBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIDBRA, SYSZ_INS_FIDBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIDR, SYSZ_INS_FIDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIDTR, SYSZ_INS_FIDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIEBR, SYSZ_INS_FIEBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIEBRA, SYSZ_INS_FIEBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIER, SYSZ_INS_FIER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIXBR, SYSZ_INS_FIXBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIXBRA, SYSZ_INS_FIXBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIXR, SYSZ_INS_FIXR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIXTR, SYSZ_INS_FIXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_FLOGR, SYSZ_INS_FLOGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_HDR, SYSZ_INS_HDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_HER, SYSZ_INS_HER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_HSCH, SYSZ_INS_HSCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IAC, SYSZ_INS_IAC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IC, SYSZ_INS_IC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ICM, SYSZ_INS_ICM, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ICMH, SYSZ_INS_ICMH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ICMY, SYSZ_INS_ICMY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ICY, SYSZ_INS_ICY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IDTE, SYSZ_INS_IDTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IDTEOpt, SYSZ_INS_IDTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IEDTR, SYSZ_INS_IEDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IEXTR, SYSZ_INS_IEXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IIHF, SYSZ_INS_IIHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IIHH, SYSZ_INS_IIHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IIHL, SYSZ_INS_IIHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IILF, SYSZ_INS_IILF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IILH, SYSZ_INS_IILH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IILL, SYSZ_INS_IILL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IPK, SYSZ_INS_IPK, -#ifndef CAPSTONE_DIET - { SYSZ_REG_2, 0 }, { SYSZ_REG_2, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IPM, SYSZ_INS_IPM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IPTE, SYSZ_INS_IPTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IPTEOpt, SYSZ_INS_IPTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IPTEOptOpt, SYSZ_INS_IPTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IRBM, SYSZ_INS_IRBM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ISKE, SYSZ_INS_ISKE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IVSK, SYSZ_INS_IVSK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_J, SYSZ_INS_J, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmE, SYSZ_INS_JE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmH, SYSZ_INS_JH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmHE, SYSZ_INS_JHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmL, SYSZ_INS_JL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmLE, SYSZ_INS_JLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmLH, SYSZ_INS_JLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmM, SYSZ_INS_JM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNE, SYSZ_INS_JNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNH, SYSZ_INS_JNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNHE, SYSZ_INS_JNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNL, SYSZ_INS_JNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNLE, SYSZ_INS_JNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNLH, SYSZ_INS_JNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNM, SYSZ_INS_JNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNO, SYSZ_INS_JNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNP, SYSZ_INS_JNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNZ, SYSZ_INS_JNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmO, SYSZ_INS_JO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmP, SYSZ_INS_JP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmZ, SYSZ_INS_JZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JG, SYSZ_INS_JG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmE, SYSZ_INS_JGE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmH, SYSZ_INS_JGH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmHE, SYSZ_INS_JGHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmL, SYSZ_INS_JGL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmLE, SYSZ_INS_JGLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmLH, SYSZ_INS_JGLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmM, SYSZ_INS_JGM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNE, SYSZ_INS_JGNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNH, SYSZ_INS_JGNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNHE, SYSZ_INS_JGNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNL, SYSZ_INS_JGNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNLE, SYSZ_INS_JGNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNLH, SYSZ_INS_JGNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNM, SYSZ_INS_JGNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNO, SYSZ_INS_JGNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNP, SYSZ_INS_JGNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNZ, SYSZ_INS_JGNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmO, SYSZ_INS_JGO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmP, SYSZ_INS_JGP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmZ, SYSZ_INS_JGZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_KDB, SYSZ_INS_KDB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KDBR, SYSZ_INS_KDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KDTR, SYSZ_INS_KDTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KEB, SYSZ_INS_KEB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KEBR, SYSZ_INS_KEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KIMD, SYSZ_INS_KIMD, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KLMD, SYSZ_INS_KLMD, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KM, SYSZ_INS_KM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KMA, SYSZ_INS_KMA, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST8, 0 }, 0, 0 -#endif -}, -{ - SystemZ_KMAC, SYSZ_INS_KMAC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KMC, SYSZ_INS_KMC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KMCTR, SYSZ_INS_KMCTR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST4, 0 }, 0, 0 -#endif -}, -{ - SystemZ_KMF, SYSZ_INS_KMF, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST4, 0 }, 0, 0 -#endif -}, -{ - SystemZ_KMO, SYSZ_INS_KMO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST4, 0 }, 0, 0 -#endif -}, -{ - SystemZ_KXBR, SYSZ_INS_KXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KXTR, SYSZ_INS_KXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_L, SYSZ_INS_L, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LA, SYSZ_INS_LA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAA, SYSZ_INS_LAA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAAG, SYSZ_INS_LAAG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAAL, SYSZ_INS_LAAL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAALG, SYSZ_INS_LAALG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAE, SYSZ_INS_LAE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAEY, SYSZ_INS_LAEY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAM, SYSZ_INS_LAM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAMY, SYSZ_INS_LAMY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAN, SYSZ_INS_LAN, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LANG, SYSZ_INS_LANG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAO, SYSZ_INS_LAO, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAOG, SYSZ_INS_LAOG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LARL, SYSZ_INS_LARL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LASP, SYSZ_INS_LASP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAT, SYSZ_INS_LAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAX, SYSZ_INS_LAX, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAXG, SYSZ_INS_LAXG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAY, SYSZ_INS_LAY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LB, SYSZ_INS_LB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LBH, SYSZ_INS_LBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LBR, SYSZ_INS_LBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCBB, SYSZ_INS_LCBB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCCTL, SYSZ_INS_LCCTL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCDBR, SYSZ_INS_LCDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCDFR, SYSZ_INS_LCDFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCDR, SYSZ_INS_LCDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCEBR, SYSZ_INS_LCEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCER, SYSZ_INS_LCER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCGFR, SYSZ_INS_LCGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCGR, SYSZ_INS_LCGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCR, SYSZ_INS_LCR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCTL, SYSZ_INS_LCTL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCTLG, SYSZ_INS_LCTLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCXBR, SYSZ_INS_LCXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCXR, SYSZ_INS_LCXR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LD, SYSZ_INS_LD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDE, SYSZ_INS_LDE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDEB, SYSZ_INS_LDEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDEBR, SYSZ_INS_LDEBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDER, SYSZ_INS_LDER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDETR, SYSZ_INS_LDETR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDGR, SYSZ_INS_LDGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDR, SYSZ_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDXBR, SYSZ_INS_LDXBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDXBRA, SYSZ_INS_LDXBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDXR, SYSZ_INS_LDXR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDXTR, SYSZ_INS_LDXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDY, SYSZ_INS_LDY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LE, SYSZ_INS_LE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LEDBR, SYSZ_INS_LEDBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LEDBRA, SYSZ_INS_LEDBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LEDR, SYSZ_INS_LEDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LEDTR, SYSZ_INS_LEDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LER, SYSZ_INS_LER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LEXBR, SYSZ_INS_LEXBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LEXBRA, SYSZ_INS_LEXBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LEXR, SYSZ_INS_LEXR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LEY, SYSZ_INS_LEY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LFAS, SYSZ_INS_LFAS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LFH, SYSZ_INS_LFH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LFHAT, SYSZ_INS_LFHAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LFPC, SYSZ_INS_LFPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LG, SYSZ_INS_LG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGAT, SYSZ_INS_LGAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGB, SYSZ_INS_LGB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGBR, SYSZ_INS_LGBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGDR, SYSZ_INS_LGDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGF, SYSZ_INS_LGF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGFI, SYSZ_INS_LGFI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGFR, SYSZ_INS_LGFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGFRL, SYSZ_INS_LGFRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGG, SYSZ_INS_LGG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_GUARDEDSTORAGE, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGH, SYSZ_INS_LGH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGHI, SYSZ_INS_LGHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGHR, SYSZ_INS_LGHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGHRL, SYSZ_INS_LGHRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGR, SYSZ_INS_LGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGRL, SYSZ_INS_LGRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGSC, SYSZ_INS_LGSC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_GUARDEDSTORAGE, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LH, SYSZ_INS_LH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LHH, SYSZ_INS_LHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LHI, SYSZ_INS_LHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LHR, SYSZ_INS_LHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LHRL, SYSZ_INS_LHRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LHY, SYSZ_INS_LHY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLC, SYSZ_INS_LLC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLCH, SYSZ_INS_LLCH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLCR, SYSZ_INS_LLCR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGC, SYSZ_INS_LLGC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGCR, SYSZ_INS_LLGCR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGF, SYSZ_INS_LLGF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGFAT, SYSZ_INS_LLGFAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGFR, SYSZ_INS_LLGFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGFRL, SYSZ_INS_LLGFRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGFSG, SYSZ_INS_LLGFSG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_GUARDEDSTORAGE, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGH, SYSZ_INS_LLGH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGHR, SYSZ_INS_LLGHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGHRL, SYSZ_INS_LLGHRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGT, SYSZ_INS_LLGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGTAT, SYSZ_INS_LLGTAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGTR, SYSZ_INS_LLGTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLH, SYSZ_INS_LLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLHH, SYSZ_INS_LLHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLHR, SYSZ_INS_LLHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLHRL, SYSZ_INS_LLHRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLIHF, SYSZ_INS_LLIHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLIHH, SYSZ_INS_LLIHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLIHL, SYSZ_INS_LLIHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLILF, SYSZ_INS_LLILF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLILH, SYSZ_INS_LLILH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLILL, SYSZ_INS_LLILL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLZRGF, SYSZ_INS_LLZRGF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LM, SYSZ_INS_LM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LMD, SYSZ_INS_LMD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LMG, SYSZ_INS_LMG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LMH, SYSZ_INS_LMH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LMY, SYSZ_INS_LMY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNDBR, SYSZ_INS_LNDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNDFR, SYSZ_INS_LNDFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNDR, SYSZ_INS_LNDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNEBR, SYSZ_INS_LNEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNER, SYSZ_INS_LNER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNGFR, SYSZ_INS_LNGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNGR, SYSZ_INS_LNGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNR, SYSZ_INS_LNR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNXBR, SYSZ_INS_LNXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNXR, SYSZ_INS_LNXR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsm, SYSZ_INS_LOC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmE, SYSZ_INS_LOCE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmH, SYSZ_INS_LOCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmHE, SYSZ_INS_LOCHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmL, SYSZ_INS_LOCL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmLE, SYSZ_INS_LOCLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmLH, SYSZ_INS_LOCLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmM, SYSZ_INS_LOCM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNE, SYSZ_INS_LOCNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNH, SYSZ_INS_LOCNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNHE, SYSZ_INS_LOCNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNL, SYSZ_INS_LOCNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNLE, SYSZ_INS_LOCNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNLH, SYSZ_INS_LOCNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNM, SYSZ_INS_LOCNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNO, SYSZ_INS_LOCNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNP, SYSZ_INS_LOCNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNZ, SYSZ_INS_LOCNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmO, SYSZ_INS_LOCO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmP, SYSZ_INS_LOCP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmZ, SYSZ_INS_LOCZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsm, SYSZ_INS_LOCFH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmE, SYSZ_INS_LOCFHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmH, SYSZ_INS_LOCFHH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmHE, SYSZ_INS_LOCFHHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmL, SYSZ_INS_LOCFHL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmLE, SYSZ_INS_LOCFHLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmLH, SYSZ_INS_LOCFHLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmM, SYSZ_INS_LOCFHM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNE, SYSZ_INS_LOCFHNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNH, SYSZ_INS_LOCFHNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNHE, SYSZ_INS_LOCFHNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNL, SYSZ_INS_LOCFHNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNLE, SYSZ_INS_LOCFHNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNLH, SYSZ_INS_LOCFHNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNM, SYSZ_INS_LOCFHNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNO, SYSZ_INS_LOCFHNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNP, SYSZ_INS_LOCFHNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNZ, SYSZ_INS_LOCFHNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmO, SYSZ_INS_LOCFHO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmP, SYSZ_INS_LOCFHP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmZ, SYSZ_INS_LOCFHZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsm, SYSZ_INS_LOCFHR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmE, SYSZ_INS_LOCFHRE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmH, SYSZ_INS_LOCFHRH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmHE, SYSZ_INS_LOCFHRHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmL, SYSZ_INS_LOCFHRL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmLE, SYSZ_INS_LOCFHRLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmLH, SYSZ_INS_LOCFHRLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmM, SYSZ_INS_LOCFHRM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNE, SYSZ_INS_LOCFHRNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNH, SYSZ_INS_LOCFHRNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNHE, SYSZ_INS_LOCFHRNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNL, SYSZ_INS_LOCFHRNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNLE, SYSZ_INS_LOCFHRNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNLH, SYSZ_INS_LOCFHRNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNM, SYSZ_INS_LOCFHRNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNO, SYSZ_INS_LOCFHRNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNP, SYSZ_INS_LOCFHRNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNZ, SYSZ_INS_LOCFHRNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmO, SYSZ_INS_LOCFHRO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmP, SYSZ_INS_LOCFHRP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmZ, SYSZ_INS_LOCFHRZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsm, SYSZ_INS_LOCG, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmE, SYSZ_INS_LOCGE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmH, SYSZ_INS_LOCGH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmHE, SYSZ_INS_LOCGHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmL, SYSZ_INS_LOCGL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmLE, SYSZ_INS_LOCGLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmLH, SYSZ_INS_LOCGLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmM, SYSZ_INS_LOCGM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNE, SYSZ_INS_LOCGNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNH, SYSZ_INS_LOCGNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNHE, SYSZ_INS_LOCGNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNL, SYSZ_INS_LOCGNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNLE, SYSZ_INS_LOCGNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNLH, SYSZ_INS_LOCGNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNM, SYSZ_INS_LOCGNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNO, SYSZ_INS_LOCGNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNP, SYSZ_INS_LOCGNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNZ, SYSZ_INS_LOCGNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmO, SYSZ_INS_LOCGO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmP, SYSZ_INS_LOCGP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmZ, SYSZ_INS_LOCGZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsm, SYSZ_INS_LOCGHI, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmE, SYSZ_INS_LOCGHIE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmH, SYSZ_INS_LOCGHIH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmHE, SYSZ_INS_LOCGHIHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmL, SYSZ_INS_LOCGHIL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmLE, SYSZ_INS_LOCGHILE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmLH, SYSZ_INS_LOCGHILH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmM, SYSZ_INS_LOCGHIM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNE, SYSZ_INS_LOCGHINE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNH, SYSZ_INS_LOCGHINH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNHE, SYSZ_INS_LOCGHINHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNL, SYSZ_INS_LOCGHINL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNLE, SYSZ_INS_LOCGHINLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNLH, SYSZ_INS_LOCGHINLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNM, SYSZ_INS_LOCGHINM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNO, SYSZ_INS_LOCGHINO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNP, SYSZ_INS_LOCGHINP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNZ, SYSZ_INS_LOCGHINZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmO, SYSZ_INS_LOCGHIO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmP, SYSZ_INS_LOCGHIP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmZ, SYSZ_INS_LOCGHIZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsm, SYSZ_INS_LOCGR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmE, SYSZ_INS_LOCGRE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmH, SYSZ_INS_LOCGRH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmHE, SYSZ_INS_LOCGRHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmL, SYSZ_INS_LOCGRL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmLE, SYSZ_INS_LOCGRLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmLH, SYSZ_INS_LOCGRLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmM, SYSZ_INS_LOCGRM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNE, SYSZ_INS_LOCGRNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNH, SYSZ_INS_LOCGRNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNHE, SYSZ_INS_LOCGRNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNL, SYSZ_INS_LOCGRNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNLE, SYSZ_INS_LOCGRNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNLH, SYSZ_INS_LOCGRNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNM, SYSZ_INS_LOCGRNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNO, SYSZ_INS_LOCGRNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNP, SYSZ_INS_LOCGRNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNZ, SYSZ_INS_LOCGRNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmO, SYSZ_INS_LOCGRO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmP, SYSZ_INS_LOCGRP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmZ, SYSZ_INS_LOCGRZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsm, SYSZ_INS_LOCHHI, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmE, SYSZ_INS_LOCHHIE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmH, SYSZ_INS_LOCHHIH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmHE, SYSZ_INS_LOCHHIHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmL, SYSZ_INS_LOCHHIL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmLE, SYSZ_INS_LOCHHILE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmLH, SYSZ_INS_LOCHHILH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmM, SYSZ_INS_LOCHHIM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNE, SYSZ_INS_LOCHHINE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNH, SYSZ_INS_LOCHHINH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNHE, SYSZ_INS_LOCHHINHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNL, SYSZ_INS_LOCHHINL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNLE, SYSZ_INS_LOCHHINLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNLH, SYSZ_INS_LOCHHINLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNM, SYSZ_INS_LOCHHINM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNO, SYSZ_INS_LOCHHINO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNP, SYSZ_INS_LOCHHINP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNZ, SYSZ_INS_LOCHHINZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmO, SYSZ_INS_LOCHHIO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmP, SYSZ_INS_LOCHHIP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmZ, SYSZ_INS_LOCHHIZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsm, SYSZ_INS_LOCHI, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmE, SYSZ_INS_LOCHIE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmH, SYSZ_INS_LOCHIH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmHE, SYSZ_INS_LOCHIHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmL, SYSZ_INS_LOCHIL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmLE, SYSZ_INS_LOCHILE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmLH, SYSZ_INS_LOCHILH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmM, SYSZ_INS_LOCHIM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNE, SYSZ_INS_LOCHINE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNH, SYSZ_INS_LOCHINH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNHE, SYSZ_INS_LOCHINHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNL, SYSZ_INS_LOCHINL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNLE, SYSZ_INS_LOCHINLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNLH, SYSZ_INS_LOCHINLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNM, SYSZ_INS_LOCHINM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNO, SYSZ_INS_LOCHINO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNP, SYSZ_INS_LOCHINP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNZ, SYSZ_INS_LOCHINZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmO, SYSZ_INS_LOCHIO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmP, SYSZ_INS_LOCHIP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmZ, SYSZ_INS_LOCHIZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsm, SYSZ_INS_LOCR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmE, SYSZ_INS_LOCRE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmH, SYSZ_INS_LOCRH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmHE, SYSZ_INS_LOCRHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmL, SYSZ_INS_LOCRL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmLE, SYSZ_INS_LOCRLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmLH, SYSZ_INS_LOCRLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmM, SYSZ_INS_LOCRM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNE, SYSZ_INS_LOCRNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNH, SYSZ_INS_LOCRNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNHE, SYSZ_INS_LOCRNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNL, SYSZ_INS_LOCRNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNLE, SYSZ_INS_LOCRNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNLH, SYSZ_INS_LOCRNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNM, SYSZ_INS_LOCRNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNO, SYSZ_INS_LOCRNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNP, SYSZ_INS_LOCRNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNZ, SYSZ_INS_LOCRNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmO, SYSZ_INS_LOCRO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmP, SYSZ_INS_LOCRP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmZ, SYSZ_INS_LOCRZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPCTL, SYSZ_INS_LPCTL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPD, SYSZ_INS_LPD, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPDBR, SYSZ_INS_LPDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPDFR, SYSZ_INS_LPDFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPDG, SYSZ_INS_LPDG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPDR, SYSZ_INS_LPDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPEBR, SYSZ_INS_LPEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPER, SYSZ_INS_LPER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPGFR, SYSZ_INS_LPGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPGR, SYSZ_INS_LPGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPP, SYSZ_INS_LPP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPQ, SYSZ_INS_LPQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPR, SYSZ_INS_LPR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPSW, SYSZ_INS_LPSW, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPSWE, SYSZ_INS_LPSWE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPTEA, SYSZ_INS_LPTEA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPXBR, SYSZ_INS_LPXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPXR, SYSZ_INS_LPXR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LR, SYSZ_INS_LR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRA, SYSZ_INS_LRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRAG, SYSZ_INS_LRAG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRAY, SYSZ_INS_LRAY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRDR, SYSZ_INS_LRDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRER, SYSZ_INS_LRER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRL, SYSZ_INS_LRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRV, SYSZ_INS_LRV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRVG, SYSZ_INS_LRVG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRVGR, SYSZ_INS_LRVGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRVH, SYSZ_INS_LRVH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRVR, SYSZ_INS_LRVR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LSCTL, SYSZ_INS_LSCTL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LT, SYSZ_INS_LT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTDBR, SYSZ_INS_LTDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTDR, SYSZ_INS_LTDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTDTR, SYSZ_INS_LTDTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTEBR, SYSZ_INS_LTEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTER, SYSZ_INS_LTER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTG, SYSZ_INS_LTG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTGF, SYSZ_INS_LTGF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTGFR, SYSZ_INS_LTGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTGR, SYSZ_INS_LTGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTR, SYSZ_INS_LTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTXBR, SYSZ_INS_LTXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTXR, SYSZ_INS_LTXR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTXTR, SYSZ_INS_LTXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LURA, SYSZ_INS_LURA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LURAG, SYSZ_INS_LURAG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXD, SYSZ_INS_LXD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXDB, SYSZ_INS_LXDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXDBR, SYSZ_INS_LXDBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXDR, SYSZ_INS_LXDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXDTR, SYSZ_INS_LXDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXE, SYSZ_INS_LXE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXEB, SYSZ_INS_LXEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXEBR, SYSZ_INS_LXEBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXER, SYSZ_INS_LXER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXR, SYSZ_INS_LXR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LY, SYSZ_INS_LY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LZDR, SYSZ_INS_LZDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LZER, SYSZ_INS_LZER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LZRF, SYSZ_INS_LZRF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LZRG, SYSZ_INS_LZRG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LZXR, SYSZ_INS_LZXR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_M, SYSZ_INS_M, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAD, SYSZ_INS_MAD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MADB, SYSZ_INS_MADB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MADBR, SYSZ_INS_MADBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MADR, SYSZ_INS_MADR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAE, SYSZ_INS_MAE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAEB, SYSZ_INS_MAEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAEBR, SYSZ_INS_MAEBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAER, SYSZ_INS_MAER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAY, SYSZ_INS_MAY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAYH, SYSZ_INS_MAYH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAYHR, SYSZ_INS_MAYHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAYL, SYSZ_INS_MAYL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAYLR, SYSZ_INS_MAYLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAYR, SYSZ_INS_MAYR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MC, SYSZ_INS_MC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MD, SYSZ_INS_MD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MDB, SYSZ_INS_MDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MDBR, SYSZ_INS_MDBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MDE, SYSZ_INS_MDE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MDEB, SYSZ_INS_MDEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MDEBR, SYSZ_INS_MDEBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MDER, SYSZ_INS_MDER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MDR, SYSZ_INS_MDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MDTR, SYSZ_INS_MDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MDTRA, SYSZ_INS_MDTRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ME, SYSZ_INS_ME, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MEE, SYSZ_INS_MEE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MEEB, SYSZ_INS_MEEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MEEBR, SYSZ_INS_MEEBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MEER, SYSZ_INS_MEER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MER, SYSZ_INS_MER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MFY, SYSZ_INS_MFY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MG, SYSZ_INS_MG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_MGH, SYSZ_INS_MGH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_MGHI, SYSZ_INS_MGHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MGRK, SYSZ_INS_MGRK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_MH, SYSZ_INS_MH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MHI, SYSZ_INS_MHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MHY, SYSZ_INS_MHY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ML, SYSZ_INS_ML, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MLG, SYSZ_INS_MLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MLGR, SYSZ_INS_MLGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MLR, SYSZ_INS_MLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MP, SYSZ_INS_MP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MR, SYSZ_INS_MR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MS, SYSZ_INS_MS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSC, SYSZ_INS_MSC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSCH, SYSZ_INS_MSCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSD, SYSZ_INS_MSD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSDB, SYSZ_INS_MSDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSDBR, SYSZ_INS_MSDBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSDR, SYSZ_INS_MSDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSE, SYSZ_INS_MSE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSEB, SYSZ_INS_MSEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSEBR, SYSZ_INS_MSEBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSER, SYSZ_INS_MSER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSFI, SYSZ_INS_MSFI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSG, SYSZ_INS_MSG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSGC, SYSZ_INS_MSGC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSGF, SYSZ_INS_MSGF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSGFI, SYSZ_INS_MSGFI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSGFR, SYSZ_INS_MSGFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSGR, SYSZ_INS_MSGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSGRKC, SYSZ_INS_MSGRKC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSR, SYSZ_INS_MSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSRKC, SYSZ_INS_MSRKC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSTA, SYSZ_INS_MSTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSY, SYSZ_INS_MSY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVC, SYSZ_INS_MVC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCDK, SYSZ_INS_MVCDK, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCIN, SYSZ_INS_MVCIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCK, SYSZ_INS_MVCK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCL, SYSZ_INS_MVCL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCLE, SYSZ_INS_MVCLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCLU, SYSZ_INS_MVCLU, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCOS, SYSZ_INS_MVCOS, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCP, SYSZ_INS_MVCP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCS, SYSZ_INS_MVCS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCSK, SYSZ_INS_MVCSK, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVGHI, SYSZ_INS_MVGHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVHHI, SYSZ_INS_MVHHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVHI, SYSZ_INS_MVHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVI, SYSZ_INS_MVI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVIY, SYSZ_INS_MVIY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVN, SYSZ_INS_MVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVO, SYSZ_INS_MVO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVPG, SYSZ_INS_MVPG, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVST, SYSZ_INS_MVST, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVZ, SYSZ_INS_MVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MXBR, SYSZ_INS_MXBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MXD, SYSZ_INS_MXD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MXDB, SYSZ_INS_MXDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MXDBR, SYSZ_INS_MXDBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MXDR, SYSZ_INS_MXDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MXR, SYSZ_INS_MXR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MXTR, SYSZ_INS_MXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MXTRA, SYSZ_INS_MXTRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_MY, SYSZ_INS_MY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MYH, SYSZ_INS_MYH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MYHR, SYSZ_INS_MYHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MYL, SYSZ_INS_MYL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MYLR, SYSZ_INS_MYLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MYR, SYSZ_INS_MYR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_N, SYSZ_INS_N, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NC, SYSZ_INS_NC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NG, SYSZ_INS_NG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NGR, SYSZ_INS_NGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NGRK, SYSZ_INS_NGRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_NI, SYSZ_INS_NI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NIAI, SYSZ_INS_NIAI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_EXECUTIONHINT, 0 }, 0, 0 -#endif -}, -{ - SystemZ_NIHF, SYSZ_INS_NIHF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NIHH, SYSZ_INS_NIHH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NIHL, SYSZ_INS_NIHL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NILF, SYSZ_INS_NILF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NILH, SYSZ_INS_NILH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NILL, SYSZ_INS_NILL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NIY, SYSZ_INS_NIY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NR, SYSZ_INS_NR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NRK, SYSZ_INS_NRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_NTSTG, SYSZ_INS_NTSTG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_NY, SYSZ_INS_NY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_O, SYSZ_INS_O, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OC, SYSZ_INS_OC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OG, SYSZ_INS_OG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OGR, SYSZ_INS_OGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OGRK, SYSZ_INS_OGRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_OI, SYSZ_INS_OI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OIHF, SYSZ_INS_OIHF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OIHH, SYSZ_INS_OIHH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OIHL, SYSZ_INS_OIHL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OILF, SYSZ_INS_OILF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OILH, SYSZ_INS_OILH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OILL, SYSZ_INS_OILL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OIY, SYSZ_INS_OIY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OR, SYSZ_INS_OR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ORK, SYSZ_INS_ORK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_OY, SYSZ_INS_OY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PACK, SYSZ_INS_PACK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PALB, SYSZ_INS_PALB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PC, SYSZ_INS_PC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PCC, SYSZ_INS_PCC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST4, 0 }, 0, 0 -#endif -}, -{ - SystemZ_PCKMO, SYSZ_INS_PCKMO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST3, 0 }, 0, 0 -#endif -}, -{ - SystemZ_PFD, SYSZ_INS_PFD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PFDRL, SYSZ_INS_PFDRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PFMF, SYSZ_INS_PFMF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PFPO, SYSZ_INS_PFPO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_F4Q, 0 }, { SYSZ_REG_CC, SYSZ_REG_1, SYSZ_REG_F0Q, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PGIN, SYSZ_INS_PGIN, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PGOUT, SYSZ_INS_PGOUT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PKA, SYSZ_INS_PKA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PKU, SYSZ_INS_PKU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PLO, SYSZ_INS_PLO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_POPCNT, SYSZ_INS_POPCNT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_POPULATIONCOUNT, 0 }, 0, 0 -#endif -}, -{ - SystemZ_PPA, SYSZ_INS_PPA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_PROCESSORASSIST, 0 }, 0, 0 -#endif -}, -{ - SystemZ_PPNO, SYSZ_INS_PPNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST5, 0 }, 0, 0 -#endif -}, -{ - SystemZ_PR, SYSZ_INS_PR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PRNO, SYSZ_INS_PRNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST7, 0 }, 0, 0 -#endif -}, -{ - SystemZ_PT, SYSZ_INS_PT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PTF, SYSZ_INS_PTF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PTFF, SYSZ_INS_PTFF, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PTI, SYSZ_INS_PTI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PTLB, SYSZ_INS_PTLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_QADTR, SYSZ_INS_QADTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_QAXTR, SYSZ_INS_QAXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_QCTRI, SYSZ_INS_QCTRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_QSI, SYSZ_INS_QSI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RCHP, SYSZ_INS_RCHP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RISBG, SYSZ_INS_RISBG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RISBGN, SYSZ_INS_RISBGN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_RISBHG, SYSZ_INS_RISBHG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_RISBLG, SYSZ_INS_RISBLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_RLL, SYSZ_INS_RLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RLLG, SYSZ_INS_RLLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RNSBG, SYSZ_INS_RNSBG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ROSBG, SYSZ_INS_ROSBG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RP, SYSZ_INS_RP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RRBE, SYSZ_INS_RRBE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RRBM, SYSZ_INS_RRBM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_RESETREFERENCEBITSMULTIPLE, 0 }, 0, 0 -#endif -}, -{ - SystemZ_RRDTR, SYSZ_INS_RRDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RRXTR, SYSZ_INS_RRXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RSCH, SYSZ_INS_RSCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RXSBG, SYSZ_INS_RXSBG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_S, SYSZ_INS_S, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SAC, SYSZ_INS_SAC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SACF, SYSZ_INS_SACF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SAL, SYSZ_INS_SAL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SAM24, SYSZ_INS_SAM24, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SAM31, SYSZ_INS_SAM31, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SAM64, SYSZ_INS_SAM64, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SAR, SYSZ_INS_SAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SCCTR, SYSZ_INS_SCCTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SCHM, SYSZ_INS_SCHM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, SYSZ_REG_2, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SCK, SYSZ_INS_SCK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SCKC, SYSZ_INS_SCKC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SCKPF, SYSZ_INS_SCKPF, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SD, SYSZ_INS_SD, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SDB, SYSZ_INS_SDB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SDBR, SYSZ_INS_SDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SDR, SYSZ_INS_SDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SDTR, SYSZ_INS_SDTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SDTRA, SYSZ_INS_SDTRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SE, SYSZ_INS_SE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SEB, SYSZ_INS_SEB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SEBR, SYSZ_INS_SEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SER, SYSZ_INS_SER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SFASR, SYSZ_INS_SFASR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SFPC, SYSZ_INS_SFPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SG, SYSZ_INS_SG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SGF, SYSZ_INS_SGF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SGFR, SYSZ_INS_SGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SGH, SYSZ_INS_SGH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SGR, SYSZ_INS_SGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SGRK, SYSZ_INS_SGRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SH, SYSZ_INS_SH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SHHHR, SYSZ_INS_SHHHR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SHHLR, SYSZ_INS_SHHLR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SHY, SYSZ_INS_SHY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SIE, SYSZ_INS_SIE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SIGA, SYSZ_INS_SIGA, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SIGP, SYSZ_INS_SIGP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SL, SYSZ_INS_SL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLA, SYSZ_INS_SLA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLAG, SYSZ_INS_SLAG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLAK, SYSZ_INS_SLAK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLB, SYSZ_INS_SLB, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLBG, SYSZ_INS_SLBG, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLBGR, SYSZ_INS_SLBGR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLBR, SYSZ_INS_SLBR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLDA, SYSZ_INS_SLDA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLDL, SYSZ_INS_SLDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLDT, SYSZ_INS_SLDT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLFI, SYSZ_INS_SLFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLG, SYSZ_INS_SLG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLGF, SYSZ_INS_SLGF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLGFI, SYSZ_INS_SLGFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLGFR, SYSZ_INS_SLGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLGR, SYSZ_INS_SLGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLGRK, SYSZ_INS_SLGRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLHHHR, SYSZ_INS_SLHHHR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLHHLR, SYSZ_INS_SLHHLR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLL, SYSZ_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLLG, SYSZ_INS_SLLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLLK, SYSZ_INS_SLLK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLR, SYSZ_INS_SLR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLRK, SYSZ_INS_SLRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLXT, SYSZ_INS_SLXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLY, SYSZ_INS_SLY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SP, SYSZ_INS_SP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SPCTR, SYSZ_INS_SPCTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SPKA, SYSZ_INS_SPKA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SPM, SYSZ_INS_SPM, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SPT, SYSZ_INS_SPT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SPX, SYSZ_INS_SPX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQD, SYSZ_INS_SQD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQDB, SYSZ_INS_SQDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQDBR, SYSZ_INS_SQDBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQDR, SYSZ_INS_SQDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQE, SYSZ_INS_SQE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQEB, SYSZ_INS_SQEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQEBR, SYSZ_INS_SQEBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQER, SYSZ_INS_SQER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQXBR, SYSZ_INS_SQXBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQXR, SYSZ_INS_SQXR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SR, SYSZ_INS_SR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRA, SYSZ_INS_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRAG, SYSZ_INS_SRAG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRAK, SYSZ_INS_SRAK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRDA, SYSZ_INS_SRDA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRDL, SYSZ_INS_SRDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRDT, SYSZ_INS_SRDT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRK, SYSZ_INS_SRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRL, SYSZ_INS_SRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRLG, SYSZ_INS_SRLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRLK, SYSZ_INS_SRLK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRNM, SYSZ_INS_SRNM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRNMB, SYSZ_INS_SRNMB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRNMT, SYSZ_INS_SRNMT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRP, SYSZ_INS_SRP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRST, SYSZ_INS_SRST, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRSTU, SYSZ_INS_SRSTU, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRXT, SYSZ_INS_SRXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SSAIR, SYSZ_INS_SSAIR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SSAR, SYSZ_INS_SSAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SSCH, SYSZ_INS_SSCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SSKE, SYSZ_INS_SSKE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SSKEOpt, SYSZ_INS_SSKE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SSM, SYSZ_INS_SSM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ST, SYSZ_INS_ST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STAM, SYSZ_INS_STAM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STAMY, SYSZ_INS_STAMY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STAP, SYSZ_INS_STAP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STC, SYSZ_INS_STC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCH, SYSZ_INS_STCH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCK, SYSZ_INS_STCK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCKC, SYSZ_INS_STCKC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCKE, SYSZ_INS_STCKE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCKF, SYSZ_INS_STCKF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCM, SYSZ_INS_STCM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCMH, SYSZ_INS_STCMH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCMY, SYSZ_INS_STCMY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCPS, SYSZ_INS_STCPS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCRW, SYSZ_INS_STCRW, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCTG, SYSZ_INS_STCTG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCTL, SYSZ_INS_STCTL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCY, SYSZ_INS_STCY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STD, SYSZ_INS_STD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STDY, SYSZ_INS_STDY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STE, SYSZ_INS_STE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STEY, SYSZ_INS_STEY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STFH, SYSZ_INS_STFH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STFL, SYSZ_INS_STFL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STFLE, SYSZ_INS_STFLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { SYSZ_REG_0, SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STFPC, SYSZ_INS_STFPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STG, SYSZ_INS_STG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STGRL, SYSZ_INS_STGRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STGSC, SYSZ_INS_STGSC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_GUARDEDSTORAGE, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STH, SYSZ_INS_STH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STHH, SYSZ_INS_STHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STHRL, SYSZ_INS_STHRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STHY, SYSZ_INS_STHY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STIDP, SYSZ_INS_STIDP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STM, SYSZ_INS_STM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STMG, SYSZ_INS_STMG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STMH, SYSZ_INS_STMH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STMY, SYSZ_INS_STMY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STNSM, SYSZ_INS_STNSM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsm, SYSZ_INS_STOC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmE, SYSZ_INS_STOCE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmH, SYSZ_INS_STOCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmHE, SYSZ_INS_STOCHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmL, SYSZ_INS_STOCL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmLE, SYSZ_INS_STOCLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmLH, SYSZ_INS_STOCLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmM, SYSZ_INS_STOCM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNE, SYSZ_INS_STOCNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNH, SYSZ_INS_STOCNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNHE, SYSZ_INS_STOCNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNL, SYSZ_INS_STOCNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNLE, SYSZ_INS_STOCNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNLH, SYSZ_INS_STOCNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNM, SYSZ_INS_STOCNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNO, SYSZ_INS_STOCNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNP, SYSZ_INS_STOCNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNZ, SYSZ_INS_STOCNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmO, SYSZ_INS_STOCO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmP, SYSZ_INS_STOCP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmZ, SYSZ_INS_STOCZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsm, SYSZ_INS_STOCFH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmE, SYSZ_INS_STOCFHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmH, SYSZ_INS_STOCFHH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmHE, SYSZ_INS_STOCFHHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmL, SYSZ_INS_STOCFHL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmLE, SYSZ_INS_STOCFHLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmLH, SYSZ_INS_STOCFHLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmM, SYSZ_INS_STOCFHM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNE, SYSZ_INS_STOCFHNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNH, SYSZ_INS_STOCFHNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNHE, SYSZ_INS_STOCFHNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNL, SYSZ_INS_STOCFHNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNLE, SYSZ_INS_STOCFHNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNLH, SYSZ_INS_STOCFHNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNM, SYSZ_INS_STOCFHNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNO, SYSZ_INS_STOCFHNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNP, SYSZ_INS_STOCFHNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNZ, SYSZ_INS_STOCFHNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmO, SYSZ_INS_STOCFHO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmP, SYSZ_INS_STOCFHP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmZ, SYSZ_INS_STOCFHZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsm, SYSZ_INS_STOCG, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmE, SYSZ_INS_STOCGE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmH, SYSZ_INS_STOCGH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmHE, SYSZ_INS_STOCGHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmL, SYSZ_INS_STOCGL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmLE, SYSZ_INS_STOCGLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmLH, SYSZ_INS_STOCGLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmM, SYSZ_INS_STOCGM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNE, SYSZ_INS_STOCGNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNH, SYSZ_INS_STOCGNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNHE, SYSZ_INS_STOCGNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNL, SYSZ_INS_STOCGNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNLE, SYSZ_INS_STOCGNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNLH, SYSZ_INS_STOCGNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNM, SYSZ_INS_STOCGNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNO, SYSZ_INS_STOCGNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNP, SYSZ_INS_STOCGNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNZ, SYSZ_INS_STOCGNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmO, SYSZ_INS_STOCGO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmP, SYSZ_INS_STOCGP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmZ, SYSZ_INS_STOCGZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOSM, SYSZ_INS_STOSM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STPQ, SYSZ_INS_STPQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STPT, SYSZ_INS_STPT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STPX, SYSZ_INS_STPX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STRAG, SYSZ_INS_STRAG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STRL, SYSZ_INS_STRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STRV, SYSZ_INS_STRV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STRVG, SYSZ_INS_STRVG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STRVH, SYSZ_INS_STRVH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STSCH, SYSZ_INS_STSCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STSI, SYSZ_INS_STSI, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_0, SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STURA, SYSZ_INS_STURA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STURG, SYSZ_INS_STURG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STY, SYSZ_INS_STY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SU, SYSZ_INS_SU, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SUR, SYSZ_INS_SUR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SVC, SYSZ_INS_SVC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SW, SYSZ_INS_SW, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SWR, SYSZ_INS_SWR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SXBR, SYSZ_INS_SXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SXR, SYSZ_INS_SXR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SXTR, SYSZ_INS_SXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SXTRA, SYSZ_INS_SXTRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SY, SYSZ_INS_SY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TABORT, SYSZ_INS_TABORT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_TAM, SYSZ_INS_TAM, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TAR, SYSZ_INS_TAR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TB, SYSZ_INS_TB, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { SYSZ_REG_0, SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TBDR, SYSZ_INS_TBDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TBEDR, SYSZ_INS_TBEDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TBEGIN, SYSZ_INS_TBEGIN, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_TBEGINC, SYSZ_INS_TBEGINC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_TCDB, SYSZ_INS_TCDB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TCEB, SYSZ_INS_TCEB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TCXB, SYSZ_INS_TCXB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TDCDT, SYSZ_INS_TDCDT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TDCET, SYSZ_INS_TDCET, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TDCXT, SYSZ_INS_TDCXT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TDGDT, SYSZ_INS_TDGDT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TDGET, SYSZ_INS_TDGET, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TDGXT, SYSZ_INS_TDGXT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TEND, SYSZ_INS_TEND, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_THDER, SYSZ_INS_THDER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_THDR, SYSZ_INS_THDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TM, SYSZ_INS_TM, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TMHH, SYSZ_INS_TMHH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TMHL, SYSZ_INS_TMHL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TMLH, SYSZ_INS_TMLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TMLL, SYSZ_INS_TMLL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TMY, SYSZ_INS_TMY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TP, SYSZ_INS_TP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TPI, SYSZ_INS_TPI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TPROT, SYSZ_INS_TPROT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TR, SYSZ_INS_TR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRACE, SYSZ_INS_TRACE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRACG, SYSZ_INS_TRACG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRAP2, SYSZ_INS_TRAP2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRAP4, SYSZ_INS_TRAP4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRE, SYSZ_INS_TRE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TROO, SYSZ_INS_TROO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TROOOpt, SYSZ_INS_TROO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TROT, SYSZ_INS_TROT, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TROTOpt, SYSZ_INS_TROT, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRT, SYSZ_INS_TRT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRTE, SYSZ_INS_TRTE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRTEOpt, SYSZ_INS_TRTE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRTO, SYSZ_INS_TRTO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRTOOpt, SYSZ_INS_TRTO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRTR, SYSZ_INS_TRTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRTRE, SYSZ_INS_TRTRE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRTREOpt, SYSZ_INS_TRTRE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRTT, SYSZ_INS_TRTT, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRTTOpt, SYSZ_INS_TRTT, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TS, SYSZ_INS_TS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TSCH, SYSZ_INS_TSCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_UNPK, SYSZ_INS_UNPK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_UNPKA, SYSZ_INS_UNPKA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_UNPKU, SYSZ_INS_UNPKU, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_UPT, SYSZ_INS_UPT, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, SYSZ_REG_4, SYSZ_REG_5, 0 }, { SYSZ_REG_CC, SYSZ_REG_0, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, SYSZ_REG_5, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_VA, SYSZ_INS_VA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAB, SYSZ_INS_VAB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAC, SYSZ_INS_VAC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VACC, SYSZ_INS_VACC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VACCB, SYSZ_INS_VACCB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VACCC, SYSZ_INS_VACCC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VACCCQ, SYSZ_INS_VACCCQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VACCF, SYSZ_INS_VACCF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VACCG, SYSZ_INS_VACCG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VACCH, SYSZ_INS_VACCH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VACCQ, SYSZ_INS_VACCQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VACQ, SYSZ_INS_VACQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAF, SYSZ_INS_VAF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAG, SYSZ_INS_VAG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAH, SYSZ_INS_VAH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAP, SYSZ_INS_VAP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAQ, SYSZ_INS_VAQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVG, SYSZ_INS_VAVG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVGB, SYSZ_INS_VAVGB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVGF, SYSZ_INS_VAVGF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVGG, SYSZ_INS_VAVGG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVGH, SYSZ_INS_VAVGH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVGL, SYSZ_INS_VAVGL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVGLB, SYSZ_INS_VAVGLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVGLF, SYSZ_INS_VAVGLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVGLG, SYSZ_INS_VAVGLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVGLH, SYSZ_INS_VAVGLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VBPERM, SYSZ_INS_VBPERM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCDG, SYSZ_INS_VCDG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCDGB, SYSZ_INS_VCDGB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCDLG, SYSZ_INS_VCDLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCDLGB, SYSZ_INS_VCDLGB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCEQ, SYSZ_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCEQB, SYSZ_INS_VCEQB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCEQBS, SYSZ_INS_VCEQBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCEQF, SYSZ_INS_VCEQF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCEQFS, SYSZ_INS_VCEQFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCEQG, SYSZ_INS_VCEQG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCEQGS, SYSZ_INS_VCEQGS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCEQH, SYSZ_INS_VCEQH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCEQHS, SYSZ_INS_VCEQHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCGD, SYSZ_INS_VCGD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCGDB, SYSZ_INS_VCGDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCH, SYSZ_INS_VCH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHB, SYSZ_INS_VCHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHBS, SYSZ_INS_VCHBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHF, SYSZ_INS_VCHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHFS, SYSZ_INS_VCHFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHG, SYSZ_INS_VCHG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHGS, SYSZ_INS_VCHGS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHH, SYSZ_INS_VCHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHHS, SYSZ_INS_VCHHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHL, SYSZ_INS_VCHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHLB, SYSZ_INS_VCHLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHLBS, SYSZ_INS_VCHLBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHLF, SYSZ_INS_VCHLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHLFS, SYSZ_INS_VCHLFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHLG, SYSZ_INS_VCHLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHLGS, SYSZ_INS_VCHLGS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHLH, SYSZ_INS_VCHLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHLHS, SYSZ_INS_VCHLHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCKSM, SYSZ_INS_VCKSM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCLGD, SYSZ_INS_VCLGD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCLGDB, SYSZ_INS_VCLGDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCLZ, SYSZ_INS_VCLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCLZB, SYSZ_INS_VCLZB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCLZF, SYSZ_INS_VCLZF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCLZG, SYSZ_INS_VCLZG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCLZH, SYSZ_INS_VCLZH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCP, SYSZ_INS_VCP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCTZ, SYSZ_INS_VCTZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCTZB, SYSZ_INS_VCTZB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCTZF, SYSZ_INS_VCTZF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCTZG, SYSZ_INS_VCTZG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCTZH, SYSZ_INS_VCTZH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCVB, SYSZ_INS_VCVB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCVBG, SYSZ_INS_VCVBG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCVD, SYSZ_INS_VCVD, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCVDG, SYSZ_INS_VCVDG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VDP, SYSZ_INS_VDP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VEC, SYSZ_INS_VEC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VECB, SYSZ_INS_VECB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VECF, SYSZ_INS_VECF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VECG, SYSZ_INS_VECG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VECH, SYSZ_INS_VECH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VECL, SYSZ_INS_VECL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VECLB, SYSZ_INS_VECLB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VECLF, SYSZ_INS_VECLF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VECLG, SYSZ_INS_VECLG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VECLH, SYSZ_INS_VECLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERIM, SYSZ_INS_VERIM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERIMB, SYSZ_INS_VERIMB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERIMF, SYSZ_INS_VERIMF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERIMG, SYSZ_INS_VERIMG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERIMH, SYSZ_INS_VERIMH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLL, SYSZ_INS_VERLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLLB, SYSZ_INS_VERLLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLLF, SYSZ_INS_VERLLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLLG, SYSZ_INS_VERLLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLLH, SYSZ_INS_VERLLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLLV, SYSZ_INS_VERLLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLLVB, SYSZ_INS_VERLLVB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLLVF, SYSZ_INS_VERLLVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLLVG, SYSZ_INS_VERLLVG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLLVH, SYSZ_INS_VERLLVH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESL, SYSZ_INS_VESL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESLB, SYSZ_INS_VESLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESLF, SYSZ_INS_VESLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESLG, SYSZ_INS_VESLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESLH, SYSZ_INS_VESLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESLV, SYSZ_INS_VESLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESLVB, SYSZ_INS_VESLVB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESLVF, SYSZ_INS_VESLVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESLVG, SYSZ_INS_VESLVG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESLVH, SYSZ_INS_VESLVH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRA, SYSZ_INS_VESRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRAB, SYSZ_INS_VESRAB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRAF, SYSZ_INS_VESRAF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRAG, SYSZ_INS_VESRAG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRAH, SYSZ_INS_VESRAH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRAV, SYSZ_INS_VESRAV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRAVB, SYSZ_INS_VESRAVB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRAVF, SYSZ_INS_VESRAVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRAVG, SYSZ_INS_VESRAVG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRAVH, SYSZ_INS_VESRAVH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRL, SYSZ_INS_VESRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRLB, SYSZ_INS_VESRLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRLF, SYSZ_INS_VESRLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRLG, SYSZ_INS_VESRLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRLH, SYSZ_INS_VESRLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRLV, SYSZ_INS_VESRLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRLVB, SYSZ_INS_VESRLVB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRLVF, SYSZ_INS_VESRLVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRLVG, SYSZ_INS_VESRLVG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRLVH, SYSZ_INS_VESRLVH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFA, SYSZ_INS_VFA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFADB, SYSZ_INS_VFADB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAE, SYSZ_INS_VFAE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEB, SYSZ_INS_VFAEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEBS, SYSZ_INS_VFAEBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEF, SYSZ_INS_VFAEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEFS, SYSZ_INS_VFAEFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEH, SYSZ_INS_VFAEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEHS, SYSZ_INS_VFAEHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEZB, SYSZ_INS_VFAEZB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEZBS, SYSZ_INS_VFAEZBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEZF, SYSZ_INS_VFAEZF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEZFS, SYSZ_INS_VFAEZFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEZH, SYSZ_INS_VFAEZH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEZHS, SYSZ_INS_VFAEZHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFASB, SYSZ_INS_VFASB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCE, SYSZ_INS_VFCE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCEDB, SYSZ_INS_VFCEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCEDBS, SYSZ_INS_VFCEDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCESB, SYSZ_INS_VFCESB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCESBS, SYSZ_INS_VFCESBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCH, SYSZ_INS_VFCH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCHDB, SYSZ_INS_VFCHDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCHDBS, SYSZ_INS_VFCHDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCHE, SYSZ_INS_VFCHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCHEDB, SYSZ_INS_VFCHEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCHEDBS, SYSZ_INS_VFCHEDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCHESB, SYSZ_INS_VFCHESB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCHESBS, SYSZ_INS_VFCHESBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCHSB, SYSZ_INS_VFCHSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCHSBS, SYSZ_INS_VFCHSBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFD, SYSZ_INS_VFD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFDDB, SYSZ_INS_VFDDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFDSB, SYSZ_INS_VFDSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEE, SYSZ_INS_VFEE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEB, SYSZ_INS_VFEEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEBS, SYSZ_INS_VFEEBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEF, SYSZ_INS_VFEEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEFS, SYSZ_INS_VFEEFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEH, SYSZ_INS_VFEEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEHS, SYSZ_INS_VFEEHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEZB, SYSZ_INS_VFEEZB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEZBS, SYSZ_INS_VFEEZBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEZF, SYSZ_INS_VFEEZF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEZFS, SYSZ_INS_VFEEZFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEZH, SYSZ_INS_VFEEZH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEZHS, SYSZ_INS_VFEEZHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENE, SYSZ_INS_VFENE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEB, SYSZ_INS_VFENEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEBS, SYSZ_INS_VFENEBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEF, SYSZ_INS_VFENEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEFS, SYSZ_INS_VFENEFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEH, SYSZ_INS_VFENEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEHS, SYSZ_INS_VFENEHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEZB, SYSZ_INS_VFENEZB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEZBS, SYSZ_INS_VFENEZBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEZF, SYSZ_INS_VFENEZF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEZFS, SYSZ_INS_VFENEZFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEZH, SYSZ_INS_VFENEZH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEZHS, SYSZ_INS_VFENEZHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFI, SYSZ_INS_VFI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFIDB, SYSZ_INS_VFIDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFISB, SYSZ_INS_VFISB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKEDB, SYSZ_INS_VFKEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKEDBS, SYSZ_INS_VFKEDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKESB, SYSZ_INS_VFKESB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKESBS, SYSZ_INS_VFKESBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKHDB, SYSZ_INS_VFKHDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKHDBS, SYSZ_INS_VFKHDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKHEDB, SYSZ_INS_VFKHEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKHEDBS, SYSZ_INS_VFKHEDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKHESB, SYSZ_INS_VFKHESB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKHESBS, SYSZ_INS_VFKHESBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKHSB, SYSZ_INS_VFKHSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKHSBS, SYSZ_INS_VFKHSBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLCDB, SYSZ_INS_VFLCDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLCSB, SYSZ_INS_VFLCSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLL, SYSZ_INS_VFLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLLS, SYSZ_INS_VFLLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLNDB, SYSZ_INS_VFLNDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLNSB, SYSZ_INS_VFLNSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLPDB, SYSZ_INS_VFLPDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLPSB, SYSZ_INS_VFLPSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLR, SYSZ_INS_VFLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLRD, SYSZ_INS_VFLRD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFM, SYSZ_INS_VFM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMA, SYSZ_INS_VFMA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMADB, SYSZ_INS_VFMADB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMASB, SYSZ_INS_VFMASB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMAX, SYSZ_INS_VFMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMAXDB, SYSZ_INS_VFMAXDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMAXSB, SYSZ_INS_VFMAXSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMDB, SYSZ_INS_VFMDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMIN, SYSZ_INS_VFMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMINDB, SYSZ_INS_VFMINDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMINSB, SYSZ_INS_VFMINSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMS, SYSZ_INS_VFMS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMSB, SYSZ_INS_VFMSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMSDB, SYSZ_INS_VFMSDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMSSB, SYSZ_INS_VFMSSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFNMA, SYSZ_INS_VFNMA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFNMADB, SYSZ_INS_VFNMADB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFNMASB, SYSZ_INS_VFNMASB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFNMS, SYSZ_INS_VFNMS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFNMSDB, SYSZ_INS_VFNMSDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFNMSSB, SYSZ_INS_VFNMSSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFPSO, SYSZ_INS_VFPSO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFPSODB, SYSZ_INS_VFPSODB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFPSOSB, SYSZ_INS_VFPSOSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFS, SYSZ_INS_VFS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFSDB, SYSZ_INS_VFSDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFSQ, SYSZ_INS_VFSQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFSQDB, SYSZ_INS_VFSQDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFSQSB, SYSZ_INS_VFSQSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFSSB, SYSZ_INS_VFSSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFTCI, SYSZ_INS_VFTCI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFTCIDB, SYSZ_INS_VFTCIDB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFTCISB, SYSZ_INS_VFTCISB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGBM, SYSZ_INS_VGBM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGEF, SYSZ_INS_VGEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGEG, SYSZ_INS_VGEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFM, SYSZ_INS_VGFM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFMA, SYSZ_INS_VGFMA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFMAB, SYSZ_INS_VGFMAB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFMAF, SYSZ_INS_VGFMAF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFMAG, SYSZ_INS_VGFMAG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFMAH, SYSZ_INS_VGFMAH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFMB, SYSZ_INS_VGFMB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFMF, SYSZ_INS_VGFMF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFMG, SYSZ_INS_VGFMG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFMH, SYSZ_INS_VGFMH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGM, SYSZ_INS_VGM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGMB, SYSZ_INS_VGMB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGMF, SYSZ_INS_VGMF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGMG, SYSZ_INS_VGMG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGMH, SYSZ_INS_VGMH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VISTR, SYSZ_INS_VISTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VISTRB, SYSZ_INS_VISTRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VISTRBS, SYSZ_INS_VISTRBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VISTRF, SYSZ_INS_VISTRF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VISTRFS, SYSZ_INS_VISTRFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VISTRH, SYSZ_INS_VISTRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VISTRHS, SYSZ_INS_VISTRHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VL, SYSZ_INS_VL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLBB, SYSZ_INS_VLBB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLC, SYSZ_INS_VLC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLCB, SYSZ_INS_VLCB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLCF, SYSZ_INS_VLCF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLCG, SYSZ_INS_VLCG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLCH, SYSZ_INS_VLCH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLDE, SYSZ_INS_VLDE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLDEB, SYSZ_INS_VLDEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLEB, SYSZ_INS_VLEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLED, SYSZ_INS_VLED, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLEDB, SYSZ_INS_VLEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLEF, SYSZ_INS_VLEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLEG, SYSZ_INS_VLEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLEH, SYSZ_INS_VLEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLEIB, SYSZ_INS_VLEIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLEIF, SYSZ_INS_VLEIF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLEIG, SYSZ_INS_VLEIG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLEIH, SYSZ_INS_VLEIH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLGV, SYSZ_INS_VLGV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLGVB, SYSZ_INS_VLGVB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLGVF, SYSZ_INS_VLGVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLGVG, SYSZ_INS_VLGVG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLGVH, SYSZ_INS_VLGVH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLIP, SYSZ_INS_VLIP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLL, SYSZ_INS_VLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLLEZ, SYSZ_INS_VLLEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLLEZB, SYSZ_INS_VLLEZB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLLEZF, SYSZ_INS_VLLEZF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLLEZG, SYSZ_INS_VLLEZG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLLEZH, SYSZ_INS_VLLEZH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLLEZLF, SYSZ_INS_VLLEZLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLM, SYSZ_INS_VLM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLP, SYSZ_INS_VLP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLPB, SYSZ_INS_VLPB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLPF, SYSZ_INS_VLPF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLPG, SYSZ_INS_VLPG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLPH, SYSZ_INS_VLPH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLR, SYSZ_INS_VLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLREP, SYSZ_INS_VLREP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLREPB, SYSZ_INS_VLREPB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLREPF, SYSZ_INS_VLREPF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLREPG, SYSZ_INS_VLREPG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLREPH, SYSZ_INS_VLREPH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLRL, SYSZ_INS_VLRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLRLR, SYSZ_INS_VLRLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLVG, SYSZ_INS_VLVG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLVGB, SYSZ_INS_VLVGB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLVGF, SYSZ_INS_VLVGF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLVGG, SYSZ_INS_VLVGG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLVGH, SYSZ_INS_VLVGH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLVGP, SYSZ_INS_VLVGP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAE, SYSZ_INS_VMAE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAEB, SYSZ_INS_VMAEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAEF, SYSZ_INS_VMAEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAEH, SYSZ_INS_VMAEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAH, SYSZ_INS_VMAH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAHB, SYSZ_INS_VMAHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAHF, SYSZ_INS_VMAHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAHH, SYSZ_INS_VMAHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAL, SYSZ_INS_VMAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALB, SYSZ_INS_VMALB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALE, SYSZ_INS_VMALE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALEB, SYSZ_INS_VMALEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALEF, SYSZ_INS_VMALEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALEH, SYSZ_INS_VMALEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALF, SYSZ_INS_VMALF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALH, SYSZ_INS_VMALH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALHB, SYSZ_INS_VMALHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALHF, SYSZ_INS_VMALHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALHH, SYSZ_INS_VMALHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALHW, SYSZ_INS_VMALHW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALO, SYSZ_INS_VMALO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALOB, SYSZ_INS_VMALOB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALOF, SYSZ_INS_VMALOF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALOH, SYSZ_INS_VMALOH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAO, SYSZ_INS_VMAO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAOB, SYSZ_INS_VMAOB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAOF, SYSZ_INS_VMAOF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAOH, SYSZ_INS_VMAOH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VME, SYSZ_INS_VME, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMEB, SYSZ_INS_VMEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMEF, SYSZ_INS_VMEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMEH, SYSZ_INS_VMEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMH, SYSZ_INS_VMH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMHB, SYSZ_INS_VMHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMHF, SYSZ_INS_VMHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMHH, SYSZ_INS_VMHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VML, SYSZ_INS_VML, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLB, SYSZ_INS_VMLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLE, SYSZ_INS_VMLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLEB, SYSZ_INS_VMLEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLEF, SYSZ_INS_VMLEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLEH, SYSZ_INS_VMLEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLF, SYSZ_INS_VMLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLH, SYSZ_INS_VMLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLHB, SYSZ_INS_VMLHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLHF, SYSZ_INS_VMLHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLHH, SYSZ_INS_VMLHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLHW, SYSZ_INS_VMLHW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLO, SYSZ_INS_VMLO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLOB, SYSZ_INS_VMLOB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLOF, SYSZ_INS_VMLOF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLOH, SYSZ_INS_VMLOH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMN, SYSZ_INS_VMN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMNB, SYSZ_INS_VMNB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMNF, SYSZ_INS_VMNF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMNG, SYSZ_INS_VMNG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMNH, SYSZ_INS_VMNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMNL, SYSZ_INS_VMNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMNLB, SYSZ_INS_VMNLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMNLF, SYSZ_INS_VMNLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMNLG, SYSZ_INS_VMNLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMNLH, SYSZ_INS_VMNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMO, SYSZ_INS_VMO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMOB, SYSZ_INS_VMOB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMOF, SYSZ_INS_VMOF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMOH, SYSZ_INS_VMOH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMP, SYSZ_INS_VMP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRH, SYSZ_INS_VMRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRHB, SYSZ_INS_VMRHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRHF, SYSZ_INS_VMRHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRHG, SYSZ_INS_VMRHG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRHH, SYSZ_INS_VMRHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRL, SYSZ_INS_VMRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRLB, SYSZ_INS_VMRLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRLF, SYSZ_INS_VMRLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRLG, SYSZ_INS_VMRLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRLH, SYSZ_INS_VMRLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMSL, SYSZ_INS_VMSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMSLG, SYSZ_INS_VMSLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMSP, SYSZ_INS_VMSP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMX, SYSZ_INS_VMX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMXB, SYSZ_INS_VMXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMXF, SYSZ_INS_VMXF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMXG, SYSZ_INS_VMXG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMXH, SYSZ_INS_VMXH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMXL, SYSZ_INS_VMXL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMXLB, SYSZ_INS_VMXLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMXLF, SYSZ_INS_VMXLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMXLG, SYSZ_INS_VMXLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMXLH, SYSZ_INS_VMXLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VN, SYSZ_INS_VN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VNC, SYSZ_INS_VNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VNN, SYSZ_INS_VNN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VNO, SYSZ_INS_VNO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VNX, SYSZ_INS_VNX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VO, SYSZ_INS_VO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VOC, SYSZ_INS_VOC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VONE, SYSZ_INS_VONE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPDI, SYSZ_INS_VPDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPERM, SYSZ_INS_VPERM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPK, SYSZ_INS_VPK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKF, SYSZ_INS_VPKF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKG, SYSZ_INS_VPKG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKH, SYSZ_INS_VPKH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKLS, SYSZ_INS_VPKLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKLSF, SYSZ_INS_VPKLSF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKLSFS, SYSZ_INS_VPKLSFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKLSG, SYSZ_INS_VPKLSG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKLSGS, SYSZ_INS_VPKLSGS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKLSH, SYSZ_INS_VPKLSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKLSHS, SYSZ_INS_VPKLSHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKS, SYSZ_INS_VPKS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKSF, SYSZ_INS_VPKSF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKSFS, SYSZ_INS_VPKSFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKSG, SYSZ_INS_VPKSG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKSGS, SYSZ_INS_VPKSGS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKSH, SYSZ_INS_VPKSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKSHS, SYSZ_INS_VPKSHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKZ, SYSZ_INS_VPKZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPOPCT, SYSZ_INS_VPOPCT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPOPCTB, SYSZ_INS_VPOPCTB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPOPCTF, SYSZ_INS_VPOPCTF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPOPCTG, SYSZ_INS_VPOPCTG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPOPCTH, SYSZ_INS_VPOPCTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPSOP, SYSZ_INS_VPSOP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREP, SYSZ_INS_VREP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREPB, SYSZ_INS_VREPB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREPF, SYSZ_INS_VREPF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREPG, SYSZ_INS_VREPG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREPH, SYSZ_INS_VREPH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREPI, SYSZ_INS_VREPI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREPIB, SYSZ_INS_VREPIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREPIF, SYSZ_INS_VREPIF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREPIG, SYSZ_INS_VREPIG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREPIH, SYSZ_INS_VREPIH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VRP, SYSZ_INS_VRP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VS, SYSZ_INS_VS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSB, SYSZ_INS_VSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSBCBI, SYSZ_INS_VSBCBI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSBCBIQ, SYSZ_INS_VSBCBIQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSBI, SYSZ_INS_VSBI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSBIQ, SYSZ_INS_VSBIQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSCBI, SYSZ_INS_VSCBI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSCBIB, SYSZ_INS_VSCBIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSCBIF, SYSZ_INS_VSCBIF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSCBIG, SYSZ_INS_VSCBIG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSCBIH, SYSZ_INS_VSCBIH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSCBIQ, SYSZ_INS_VSCBIQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSCEF, SYSZ_INS_VSCEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSCEG, SYSZ_INS_VSCEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSDP, SYSZ_INS_VSDP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSEG, SYSZ_INS_VSEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSEGB, SYSZ_INS_VSEGB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSEGF, SYSZ_INS_VSEGF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSEGH, SYSZ_INS_VSEGH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSEL, SYSZ_INS_VSEL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSF, SYSZ_INS_VSF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSG, SYSZ_INS_VSG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSH, SYSZ_INS_VSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSL, SYSZ_INS_VSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSLB, SYSZ_INS_VSLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSLDB, SYSZ_INS_VSLDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSP, SYSZ_INS_VSP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSQ, SYSZ_INS_VSQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSRA, SYSZ_INS_VSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSRAB, SYSZ_INS_VSRAB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSRL, SYSZ_INS_VSRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSRLB, SYSZ_INS_VSRLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSRP, SYSZ_INS_VSRP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VST, SYSZ_INS_VST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTEB, SYSZ_INS_VSTEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTEF, SYSZ_INS_VSTEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTEG, SYSZ_INS_VSTEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTEH, SYSZ_INS_VSTEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTL, SYSZ_INS_VSTL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTM, SYSZ_INS_VSTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRC, SYSZ_INS_VSTRC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCB, SYSZ_INS_VSTRCB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCBS, SYSZ_INS_VSTRCBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCF, SYSZ_INS_VSTRCF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCFS, SYSZ_INS_VSTRCFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCH, SYSZ_INS_VSTRCH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCHS, SYSZ_INS_VSTRCHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCZB, SYSZ_INS_VSTRCZB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCZBS, SYSZ_INS_VSTRCZBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCZF, SYSZ_INS_VSTRCZF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCZFS, SYSZ_INS_VSTRCZFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCZH, SYSZ_INS_VSTRCZH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCZHS, SYSZ_INS_VSTRCZHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRL, SYSZ_INS_VSTRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRLR, SYSZ_INS_VSTRLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSUM, SYSZ_INS_VSUM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSUMB, SYSZ_INS_VSUMB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSUMG, SYSZ_INS_VSUMG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSUMGF, SYSZ_INS_VSUMGF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSUMGH, SYSZ_INS_VSUMGH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSUMH, SYSZ_INS_VSUMH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSUMQ, SYSZ_INS_VSUMQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSUMQF, SYSZ_INS_VSUMQF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSUMQG, SYSZ_INS_VSUMQG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VTM, SYSZ_INS_VTM, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VTP, SYSZ_INS_VTP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPH, SYSZ_INS_VUPH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPHB, SYSZ_INS_VUPHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPHF, SYSZ_INS_VUPHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPHH, SYSZ_INS_VUPHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPKZ, SYSZ_INS_VUPKZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPL, SYSZ_INS_VUPL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLB, SYSZ_INS_VUPLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLF, SYSZ_INS_VUPLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLH, SYSZ_INS_VUPLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLHB, SYSZ_INS_VUPLHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLHF, SYSZ_INS_VUPLHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLHH, SYSZ_INS_VUPLHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLHW, SYSZ_INS_VUPLHW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLL, SYSZ_INS_VUPLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLLB, SYSZ_INS_VUPLLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLLF, SYSZ_INS_VUPLLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLLH, SYSZ_INS_VUPLLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VX, SYSZ_INS_VX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VZERO, SYSZ_INS_VZERO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WCDGB, SYSZ_INS_WCDGB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WCDLGB, SYSZ_INS_WCDLGB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WCGDB, SYSZ_INS_WCGDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WCLGDB, SYSZ_INS_WCLGDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFADB, SYSZ_INS_WFADB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFASB, SYSZ_INS_WFASB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFAXB, SYSZ_INS_WFAXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFC, SYSZ_INS_WFC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCDB, SYSZ_INS_WFCDB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCEDB, SYSZ_INS_WFCEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCEDBS, SYSZ_INS_WFCEDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCESB, SYSZ_INS_WFCESB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCESBS, SYSZ_INS_WFCESBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCEXB, SYSZ_INS_WFCEXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCEXBS, SYSZ_INS_WFCEXBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHDB, SYSZ_INS_WFCHDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHDBS, SYSZ_INS_WFCHDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHEDB, SYSZ_INS_WFCHEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHEDBS, SYSZ_INS_WFCHEDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHESB, SYSZ_INS_WFCHESB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHESBS, SYSZ_INS_WFCHESBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHEXB, SYSZ_INS_WFCHEXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHEXBS, SYSZ_INS_WFCHEXBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHSB, SYSZ_INS_WFCHSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHSBS, SYSZ_INS_WFCHSBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHXB, SYSZ_INS_WFCHXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHXBS, SYSZ_INS_WFCHXBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCSB, SYSZ_INS_WFCSB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCXB, SYSZ_INS_WFCXB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFDDB, SYSZ_INS_WFDDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFDSB, SYSZ_INS_WFDSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFDXB, SYSZ_INS_WFDXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFIDB, SYSZ_INS_WFIDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFISB, SYSZ_INS_WFISB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFIXB, SYSZ_INS_WFIXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFK, SYSZ_INS_WFK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKDB, SYSZ_INS_WFKDB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKEDB, SYSZ_INS_WFKEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKEDBS, SYSZ_INS_WFKEDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKESB, SYSZ_INS_WFKESB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKESBS, SYSZ_INS_WFKESBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKEXB, SYSZ_INS_WFKEXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKEXBS, SYSZ_INS_WFKEXBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHDB, SYSZ_INS_WFKHDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHDBS, SYSZ_INS_WFKHDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHEDB, SYSZ_INS_WFKHEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHEDBS, SYSZ_INS_WFKHEDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHESB, SYSZ_INS_WFKHESB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHESBS, SYSZ_INS_WFKHESBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHEXB, SYSZ_INS_WFKHEXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHEXBS, SYSZ_INS_WFKHEXBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHSB, SYSZ_INS_WFKHSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHSBS, SYSZ_INS_WFKHSBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHXB, SYSZ_INS_WFKHXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHXBS, SYSZ_INS_WFKHXBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKSB, SYSZ_INS_WFKSB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKXB, SYSZ_INS_WFKXB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLCDB, SYSZ_INS_WFLCDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLCSB, SYSZ_INS_WFLCSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLCXB, SYSZ_INS_WFLCXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLLD, SYSZ_INS_WFLLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLLS, SYSZ_INS_WFLLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLNDB, SYSZ_INS_WFLNDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLNSB, SYSZ_INS_WFLNSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLNXB, SYSZ_INS_WFLNXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLPDB, SYSZ_INS_WFLPDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLPSB, SYSZ_INS_WFLPSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLPXB, SYSZ_INS_WFLPXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLRD, SYSZ_INS_WFLRD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLRX, SYSZ_INS_WFLRX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMADB, SYSZ_INS_WFMADB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMASB, SYSZ_INS_WFMASB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMAXB, SYSZ_INS_WFMAXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMAXDB, SYSZ_INS_WFMAXDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMAXSB, SYSZ_INS_WFMAXSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMAXXB, SYSZ_INS_WFMAXXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMDB, SYSZ_INS_WFMDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMINDB, SYSZ_INS_WFMINDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMINSB, SYSZ_INS_WFMINSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMINXB, SYSZ_INS_WFMINXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMSB, SYSZ_INS_WFMSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMSDB, SYSZ_INS_WFMSDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMSSB, SYSZ_INS_WFMSSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMSXB, SYSZ_INS_WFMSXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMXB, SYSZ_INS_WFMXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFNMADB, SYSZ_INS_WFNMADB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFNMASB, SYSZ_INS_WFNMASB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFNMAXB, SYSZ_INS_WFNMAXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFNMSDB, SYSZ_INS_WFNMSDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFNMSSB, SYSZ_INS_WFNMSSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFNMSXB, SYSZ_INS_WFNMSXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFPSODB, SYSZ_INS_WFPSODB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFPSOSB, SYSZ_INS_WFPSOSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFPSOXB, SYSZ_INS_WFPSOXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFSDB, SYSZ_INS_WFSDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFSQDB, SYSZ_INS_WFSQDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFSQSB, SYSZ_INS_WFSQSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFSQXB, SYSZ_INS_WFSQXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFSSB, SYSZ_INS_WFSSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFSXB, SYSZ_INS_WFSXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFTCIDB, SYSZ_INS_WFTCIDB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFTCISB, SYSZ_INS_WFTCISB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFTCIXB, SYSZ_INS_WFTCIXB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WLDEB, SYSZ_INS_WLDEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WLEDB, SYSZ_INS_WLEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_X, SYSZ_INS_X, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XC, SYSZ_INS_XC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XG, SYSZ_INS_XG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XGR, SYSZ_INS_XGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XGRK, SYSZ_INS_XGRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_XI, SYSZ_INS_XI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XIHF, SYSZ_INS_XIHF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XILF, SYSZ_INS_XILF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XIY, SYSZ_INS_XIY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XR, SYSZ_INS_XR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XRK, SYSZ_INS_XRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_XSCH, SYSZ_INS_XSCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XY, SYSZ_INS_XY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ZAP, SYSZ_INS_ZAP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, diff --git a/arch/SystemZ/SystemZModule.c b/arch/SystemZ/SystemZModule.c index bc510688bd..282df2bc72 100644 --- a/arch/SystemZ/SystemZModule.c +++ b/arch/SystemZ/SystemZModule.c @@ -1,12 +1,10 @@ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ -#ifdef CAPSTONE_HAS_SYSZ +#ifdef CAPSTONE_HAS_SYSTEMZ #include "../../utils.h" #include "../../MCRegisterInfo.h" -#include "SystemZDisassembler.h" -#include "SystemZInstPrinter.h" #include "SystemZMapping.h" #include "SystemZModule.h" @@ -15,12 +13,12 @@ cs_err SystemZ_global_init(cs_struct *ud) MCRegisterInfo *mri; mri = cs_mem_malloc(sizeof(*mri)); - SystemZ_init(mri); - ud->printer = SystemZ_printInst; + SystemZ_init_mri(mri); + ud->printer = SystemZ_printer; ud->printer_info = mri; ud->getinsn_info = mri; ud->disasm = SystemZ_getInstruction; - ud->post_printer = SystemZ_post_printer; + ud->post_printer = NULL; ud->reg_name = SystemZ_reg_name; ud->insn_id = SystemZ_get_insn_id; @@ -32,11 +30,11 @@ cs_err SystemZ_global_init(cs_struct *ud) cs_err SystemZ_option(cs_struct *handle, cs_opt_type type, size_t value) { - if (type == CS_OPT_SYNTAX) + if (type == CS_OPT_SYNTAX) { handle->syntax = (int) value; - - // Do not set mode because only CS_MODE_BIG_ENDIAN is valid; we cannot - // test for CS_MODE_LITTLE_ENDIAN because it is 0 + } else if (type == CS_OPT_MODE) { + handle->mode |= (cs_mode)value; + } return CS_ERR_OK; } diff --git a/bindings/const_generator.py b/bindings/const_generator.py index e164e62a93..c56c0db6f7 100644 --- a/bindings/const_generator.py +++ b/bindings/const_generator.py @@ -21,7 +21,7 @@ 'x86.h': 'X86', 'ppc.h': 'Ppc', 'sparc.h': 'Sparc', - 'systemz.h': 'Sysz', + 'systemz.h': 'Systemz', 'xcore.h': 'Xcore', 'tms320c64x.h': 'TMS320C64x', 'm680x.h': 'M680x', @@ -31,8 +31,10 @@ 'comment_close': '', }, 'python': { - 'header': "from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX\n" - "# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%s_const.py]\n", + 'header': ( + "from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX\n" + "# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%s_const.py]\n" + ), 'footer': "", 'line_format': '%s = %s\n', 'out_file': './python/capstone/%s_const.py', @@ -44,7 +46,7 @@ 'x86.h': 'x86', 'ppc.h': 'ppc', 'sparc.h': 'sparc', - 'systemz.h': 'sysz', + 'systemz.h': 'systemz', 'xcore.h': 'xcore', 'tms320c64x.h': 'tms320c64x', 'm680x.h': 'm680x', @@ -73,7 +75,7 @@ 'x86.h': 'x86', 'ppc.h': 'ppc', 'sparc.h': 'sparc', - 'systemz.h': 'sysz', + 'systemz.h': 'systemz', 'xcore.h': 'xcore', 'tms320c64x.h': 'tms320c64x', 'm680x.h': 'm680x', @@ -175,7 +177,7 @@ def gen(lang): if line.startswith('#define '): line = line[8:] #cut off define - xline = re.split('\s+', line, 1) #split to at most 2 express + xline = re.split(r'\s+', line, 1) #split to at most 2 express if len(xline) != 2: continue if '(' in xline[0] or ')' in xline[0]: #does it look like a function @@ -201,7 +203,7 @@ def has_special_arch_prefix(x): # hacky: remove type cast (uint64_t) t = t.replace('(uint64_t)', '') t = re.sub(r'\((\d+)ULL << (\d+)\)', r'\1 << \2', t) # (1ULL<<1) to 1 << 1 - f = re.split('\s+', t) + f = re.split(r'\s+', t) if not has_special_arch_prefix(f[0]): continue diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py index b0102485f3..ce3d026945 100755 --- a/bindings/python/capstone/__init__.py +++ b/bindings/python/capstone/__init__.py @@ -26,7 +26,7 @@ 'CS_ARCH_X86', 'CS_ARCH_PPC', 'CS_ARCH_SPARC', - 'CS_ARCH_SYSZ', + 'CS_ARCH_SYSTEMZ', 'CS_ARCH_XCORE', 'CS_ARCH_M68K', 'CS_ARCH_TMS320C64X', @@ -130,6 +130,21 @@ 'CS_MODE_HPPA_20W', 'CS_MODE_LOONGARCH32', 'CS_MODE_LOONGARCH64', + 'CS_MODE_SYSTEMZ_ARCH8', + 'CS_MODE_SYSTEMZ_ARCH9', + 'CS_MODE_SYSTEMZ_ARCH10', + 'CS_MODE_SYSTEMZ_ARCH11', + 'CS_MODE_SYSTEMZ_ARCH12', + 'CS_MODE_SYSTEMZ_ARCH13', + 'CS_MODE_SYSTEMZ_ARCH14', + 'CS_MODE_SYSTEMZ_Z10', + 'CS_MODE_SYSTEMZ_Z196', + 'CS_MODE_SYSTEMZ_ZEC12', + 'CS_MODE_SYSTEMZ_Z13', + 'CS_MODE_SYSTEMZ_Z14', + 'CS_MODE_SYSTEMZ_Z15', + 'CS_MODE_SYSTEMZ_Z16', + 'CS_MODE_SYSTEMZ_GENERIC', 'CS_OPT_SYNTAX', 'CS_OPT_SYNTAX_DEFAULT', @@ -214,6 +229,7 @@ '__version__', ] +UINT8_MAX = 0xff UINT16_MAX = 0xffff # Capstone C interface @@ -232,11 +248,11 @@ # architectures CS_ARCH_ARM = 0 CS_ARCH_AARCH64 = 1 -CS_ARCH_MIPS = 2 -CS_ARCH_X86 = 3 -CS_ARCH_PPC = 4 -CS_ARCH_SPARC = 5 -CS_ARCH_SYSZ = 6 +CS_ARCH_SYSTEMZ = 2 +CS_ARCH_MIPS = 3 +CS_ARCH_X86 = 4 +CS_ARCH_PPC = 5 +CS_ARCH_SPARC = 6 CS_ARCH_XCORE = 7 CS_ARCH_M68K = 8 CS_ARCH_TMS320C64X = 9 @@ -346,6 +362,21 @@ CS_MODE_HPPA_20W = CS_MODE_HPPA_20 | (1 << 3) # HPPA 2.0 wide CS_MODE_LOONGARCH32 = 1 << 0 CS_MODE_LOONGARCH64 = 1 << 1 +CS_MODE_SYSTEMZ_ARCH8 = 1 << 1 +CS_MODE_SYSTEMZ_ARCH9 = 1 << 2 +CS_MODE_SYSTEMZ_ARCH10 = 1 << 3 +CS_MODE_SYSTEMZ_ARCH11 = 1 << 4 +CS_MODE_SYSTEMZ_ARCH12 = 1 << 5 +CS_MODE_SYSTEMZ_ARCH13 = 1 << 6 +CS_MODE_SYSTEMZ_ARCH14 = 1 << 7 +CS_MODE_SYSTEMZ_Z10 = 1 << 8 +CS_MODE_SYSTEMZ_Z196 = 1 << 9 +CS_MODE_SYSTEMZ_ZEC12 = 1 << 10 +CS_MODE_SYSTEMZ_Z13 = 1 << 11 +CS_MODE_SYSTEMZ_Z14 = 1 << 12 +CS_MODE_SYSTEMZ_Z15 = 1 << 13 +CS_MODE_SYSTEMZ_Z16 = 1 << 14 +CS_MODE_SYSTEMZ_GENERIC = 1 << 15 # Capstone option type CS_OPT_INVALID = 0 # No option specified @@ -526,7 +557,7 @@ class _cs_arch(ctypes.Union): ('x86', x86.CsX86), ('ppc', ppc.CsPpc), ('sparc', sparc.CsSparc), - ('sysz', systemz.CsSysz), + ('systemz', systemz.CsSystemZ), ('xcore', xcore.CsXcore), ('tms320c64x', tms320c64x.CsTMS320C64x), ('m680x', m680x.CsM680x), @@ -877,8 +908,8 @@ def __gen_detail(self): ppc.get_arch_info(self._raw.detail.contents.arch.ppc) elif arch == CS_ARCH_SPARC: (self.cc, self.hint, self.operands) = sparc.get_arch_info(self._raw.detail.contents.arch.sparc) - elif arch == CS_ARCH_SYSZ: - (self.cc, self.operands) = systemz.get_arch_info(self._raw.detail.contents.arch.sysz) + elif arch == CS_ARCH_SYSTEMZ: + (self.cc, self.format, self.operands) = systemz.get_arch_info(self._raw.detail.contents.arch.systemz) elif arch == CS_ARCH_XCORE: (self.operands) = xcore.get_arch_info(self._raw.detail.contents.arch.xcore) elif arch == CS_ARCH_TMS320C64X: @@ -1397,7 +1428,7 @@ def debug(): archs = { "arm": CS_ARCH_ARM, "aarch64": CS_ARCH_AARCH64, "m68k": CS_ARCH_M68K, "mips": CS_ARCH_MIPS, "ppc": CS_ARCH_PPC, "sparc": CS_ARCH_SPARC, - "sysz": CS_ARCH_SYSZ, 'xcore': CS_ARCH_XCORE, "tms320c64x": CS_ARCH_TMS320C64X, + "systemz": CS_ARCH_SYSTEMZ, 'xcore': CS_ARCH_XCORE, "tms320c64x": CS_ARCH_TMS320C64X, "m680x": CS_ARCH_M680X, 'evm': CS_ARCH_EVM, 'mos65xx': CS_ARCH_MOS65XX, 'bpf': CS_ARCH_BPF, 'riscv': CS_ARCH_RISCV, 'tricore': CS_ARCH_TRICORE, 'wasm': CS_ARCH_WASM, 'sh': CS_ARCH_SH, 'alpha': CS_ARCH_ALPHA, diff --git a/bindings/python/capstone/aarch64_const.py b/bindings/python/capstone/aarch64_const.py index 4831adb6d9..756d774e2e 100644 --- a/bindings/python/capstone/aarch64_const.py +++ b/bindings/python/capstone/aarch64_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [aarch64_const.py] AARCH64_SFT_INVALID = 0 @@ -2368,6 +2368,8 @@ AARCH64_SME_OP_INVALID = 0 AARCH64_SME_OP_TILE = 1 AARCH64_SME_OP_TILE_VEC = 2 +AARCH64_SLICE_IMM_INVALID = UINT16_MAX +AARCH64_SLICE_IMM_RANGE_INVALID = UINT8_MAX AARCH64_INS_INVALID = 0 AARCH64_INS_ABS = 1 diff --git a/bindings/python/capstone/alpha_const.py b/bindings/python/capstone/alpha_const.py index f6e5892fb6..14b8c18d39 100644 --- a/bindings/python/capstone/alpha_const.py +++ b/bindings/python/capstone/alpha_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [alpha_const.py] # Operand type for instruction's operands diff --git a/bindings/python/capstone/arm_const.py b/bindings/python/capstone/arm_const.py index 804481bc49..dbc09e3bd9 100644 --- a/bindings/python/capstone/arm_const.py +++ b/bindings/python/capstone/arm_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.py] ARMCC_EQ = 0 diff --git a/bindings/python/capstone/bpf_const.py b/bindings/python/capstone/bpf_const.py index 8e302be7db..88bc5a45fe 100644 --- a/bindings/python/capstone/bpf_const.py +++ b/bindings/python/capstone/bpf_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [bpf_const.py] BPF_OP_INVALID = 0 diff --git a/bindings/python/capstone/evm_const.py b/bindings/python/capstone/evm_const.py index c933ff6728..e029eef0b8 100644 --- a/bindings/python/capstone/evm_const.py +++ b/bindings/python/capstone/evm_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [evm_const.py] EVM_INS_STOP = 0 diff --git a/bindings/python/capstone/hppa_const.py b/bindings/python/capstone/hppa_const.py index 4e5c78e6f6..e5bca15446 100644 --- a/bindings/python/capstone/hppa_const.py +++ b/bindings/python/capstone/hppa_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [hppa_const.py] HPPA_MAX_OPS = 5 HPPA_STR_MODIFIER_LEN = 8 diff --git a/bindings/python/capstone/loongarch_const.py b/bindings/python/capstone/loongarch_const.py index c2c953d427..08019be23b 100644 --- a/bindings/python/capstone/loongarch_const.py +++ b/bindings/python/capstone/loongarch_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [loongarch_const.py] LOONGARCH_OP_INVALID = CS_OP_INVALID LOONGARCH_OP_REG = CS_OP_REG diff --git a/bindings/python/capstone/m680x_const.py b/bindings/python/capstone/m680x_const.py index 8b0205a692..f543517cc2 100644 --- a/bindings/python/capstone/m680x_const.py +++ b/bindings/python/capstone/m680x_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m680x_const.py] M680X_OPERAND_COUNT = 9 diff --git a/bindings/python/capstone/m68k_const.py b/bindings/python/capstone/m68k_const.py index 2d5d16f423..de702afe9a 100644 --- a/bindings/python/capstone/m68k_const.py +++ b/bindings/python/capstone/m68k_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.py] M68K_OPERAND_COUNT = 4 diff --git a/bindings/python/capstone/mips_const.py b/bindings/python/capstone/mips_const.py index b48b4ac552..5f6cc8c1b7 100644 --- a/bindings/python/capstone/mips_const.py +++ b/bindings/python/capstone/mips_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.py] MIPS_OP_INVALID = 0 diff --git a/bindings/python/capstone/mos65xx_const.py b/bindings/python/capstone/mos65xx_const.py index 3503801221..bd1e914a77 100644 --- a/bindings/python/capstone/mos65xx_const.py +++ b/bindings/python/capstone/mos65xx_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mos65xx_const.py] MOS65XX_REG_INVALID = 0 diff --git a/bindings/python/capstone/ppc_const.py b/bindings/python/capstone/ppc_const.py index 2feba7cc95..c8c5bed34e 100644 --- a/bindings/python/capstone/ppc_const.py +++ b/bindings/python/capstone/ppc_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppc_const.py] PPC_PRED_INVALID = 0xffff PPC_PRED_LT = (0<<5)|12 diff --git a/bindings/python/capstone/riscv_const.py b/bindings/python/capstone/riscv_const.py index 437ae006b2..16aa8b634f 100644 --- a/bindings/python/capstone/riscv_const.py +++ b/bindings/python/capstone/riscv_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [riscv_const.py] # Operand type for instruction's operands diff --git a/bindings/python/capstone/sh_const.py b/bindings/python/capstone/sh_const.py index 5a1f05193b..3d7faf4e31 100644 --- a/bindings/python/capstone/sh_const.py +++ b/bindings/python/capstone/sh_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sh_const.py] SH_REG_INVALID = 0 diff --git a/bindings/python/capstone/sparc_const.py b/bindings/python/capstone/sparc_const.py index 19de48d73f..5f757bf146 100644 --- a/bindings/python/capstone/sparc_const.py +++ b/bindings/python/capstone/sparc_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.py] SPARC_CC_INVALID = 0 diff --git a/bindings/python/capstone/systemz.py b/bindings/python/capstone/systemz.py index 398018b251..0f73c5fd38 100644 --- a/bindings/python/capstone/systemz.py +++ b/bindings/python/capstone/systemz.py @@ -2,28 +2,30 @@ import ctypes from . import copy_ctypes_list -from .sysz_const import * # define the API -class SyszOpMem(ctypes.Structure): +class SystemZOpMem(ctypes.Structure): _fields_ = ( + ('am', ctypes.c_int), ('base', ctypes.c_uint8), ('index', ctypes.c_uint8), ('length', ctypes.c_uint64), ('disp', ctypes.c_int64), ) -class SyszOpValue(ctypes.Union): +class SystemZOpValue(ctypes.Union): _fields_ = ( ('reg', ctypes.c_uint), ('imm', ctypes.c_int64), - ('mem', SyszOpMem), + ('mem', SystemZOpMem), ) -class SyszOp(ctypes.Structure): +class SystemZOp(ctypes.Structure): _fields_ = ( ('type', ctypes.c_uint), - ('value', SyszOpValue), + ('value', SystemZOpValue), + ('access', ctypes.c_int), + ('imm_width', ctypes.c_uint8), ) @property @@ -39,13 +41,14 @@ def mem(self): return self.value.mem -class CsSysz(ctypes.Structure): +class CsSystemZ(ctypes.Structure): _fields_ = ( ('cc', ctypes.c_uint), + ('format', ctypes.c_int), ('op_count', ctypes.c_uint8), - ('operands', SyszOp * 6), + ('operands', SystemZOp * 6), ) def get_arch_info(a): - return (a.cc, copy_ctypes_list(a.operands[:a.op_count])) + return a.cc, a.format, copy_ctypes_list(a.operands[:a.op_count]) diff --git a/bindings/python/capstone/systemz_const.py b/bindings/python/capstone/systemz_const.py new file mode 100644 index 0000000000..5a72b5878e --- /dev/null +++ b/bindings/python/capstone/systemz_const.py @@ -0,0 +1,2903 @@ +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX +# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [systemz_const.py] + +SYSTEMZ_CC_O = 0 +SYSTEMZ_CC_H = 1 +SYSTEMZ_CC_NLE = 2 +SYSTEMZ_CC_L = 3 +SYSTEMZ_CC_NHE = 4 +SYSTEMZ_CC_LH = 5 +SYSTEMZ_CC_NE = 6 +SYSTEMZ_CC_E = 7 +SYSTEMZ_CC_NLH = 8 +SYSTEMZ_CC_HE = 9 +SYSTEMZ_CC_NL = 10 +SYSTEMZ_CC_LE = 11 +SYSTEMZ_CC_NH = 12 +SYSTEMZ_CC_NO = 13 +SYSTEMZ_OP_INVALID = CS_OP_INVALID +SYSTEMZ_OP_REG = CS_OP_REG +SYSTEMZ_OP_IMM = CS_OP_IMM +SYSTEMZ_OP_MEM = CS_OP_MEM + +SYSTEMZ_REG_INVALID = 0 +SYSTEMZ_REG_CC = 1 +SYSTEMZ_REG_FPC = 2 +SYSTEMZ_REG_A0 = 3 +SYSTEMZ_REG_A1 = 4 +SYSTEMZ_REG_A2 = 5 +SYSTEMZ_REG_A3 = 6 +SYSTEMZ_REG_A4 = 7 +SYSTEMZ_REG_A5 = 8 +SYSTEMZ_REG_A6 = 9 +SYSTEMZ_REG_A7 = 10 +SYSTEMZ_REG_A8 = 11 +SYSTEMZ_REG_A9 = 12 +SYSTEMZ_REG_A10 = 13 +SYSTEMZ_REG_A11 = 14 +SYSTEMZ_REG_A12 = 15 +SYSTEMZ_REG_A13 = 16 +SYSTEMZ_REG_A14 = 17 +SYSTEMZ_REG_A15 = 18 +SYSTEMZ_REG_C0 = 19 +SYSTEMZ_REG_C1 = 20 +SYSTEMZ_REG_C2 = 21 +SYSTEMZ_REG_C3 = 22 +SYSTEMZ_REG_C4 = 23 +SYSTEMZ_REG_C5 = 24 +SYSTEMZ_REG_C6 = 25 +SYSTEMZ_REG_C7 = 26 +SYSTEMZ_REG_C8 = 27 +SYSTEMZ_REG_C9 = 28 +SYSTEMZ_REG_C10 = 29 +SYSTEMZ_REG_C11 = 30 +SYSTEMZ_REG_C12 = 31 +SYSTEMZ_REG_C13 = 32 +SYSTEMZ_REG_C14 = 33 +SYSTEMZ_REG_C15 = 34 +SYSTEMZ_REG_V0 = 35 +SYSTEMZ_REG_V1 = 36 +SYSTEMZ_REG_V2 = 37 +SYSTEMZ_REG_V3 = 38 +SYSTEMZ_REG_V4 = 39 +SYSTEMZ_REG_V5 = 40 +SYSTEMZ_REG_V6 = 41 +SYSTEMZ_REG_V7 = 42 +SYSTEMZ_REG_V8 = 43 +SYSTEMZ_REG_V9 = 44 +SYSTEMZ_REG_V10 = 45 +SYSTEMZ_REG_V11 = 46 +SYSTEMZ_REG_V12 = 47 +SYSTEMZ_REG_V13 = 48 +SYSTEMZ_REG_V14 = 49 +SYSTEMZ_REG_V15 = 50 +SYSTEMZ_REG_V16 = 51 +SYSTEMZ_REG_V17 = 52 +SYSTEMZ_REG_V18 = 53 +SYSTEMZ_REG_V19 = 54 +SYSTEMZ_REG_V20 = 55 +SYSTEMZ_REG_V21 = 56 +SYSTEMZ_REG_V22 = 57 +SYSTEMZ_REG_V23 = 58 +SYSTEMZ_REG_V24 = 59 +SYSTEMZ_REG_V25 = 60 +SYSTEMZ_REG_V26 = 61 +SYSTEMZ_REG_V27 = 62 +SYSTEMZ_REG_V28 = 63 +SYSTEMZ_REG_V29 = 64 +SYSTEMZ_REG_V30 = 65 +SYSTEMZ_REG_V31 = 66 +SYSTEMZ_REG_F0D = 67 +SYSTEMZ_REG_F1D = 68 +SYSTEMZ_REG_F2D = 69 +SYSTEMZ_REG_F3D = 70 +SYSTEMZ_REG_F4D = 71 +SYSTEMZ_REG_F5D = 72 +SYSTEMZ_REG_F6D = 73 +SYSTEMZ_REG_F7D = 74 +SYSTEMZ_REG_F8D = 75 +SYSTEMZ_REG_F9D = 76 +SYSTEMZ_REG_F10D = 77 +SYSTEMZ_REG_F11D = 78 +SYSTEMZ_REG_F12D = 79 +SYSTEMZ_REG_F13D = 80 +SYSTEMZ_REG_F14D = 81 +SYSTEMZ_REG_F15D = 82 +SYSTEMZ_REG_F16D = 83 +SYSTEMZ_REG_F17D = 84 +SYSTEMZ_REG_F18D = 85 +SYSTEMZ_REG_F19D = 86 +SYSTEMZ_REG_F20D = 87 +SYSTEMZ_REG_F21D = 88 +SYSTEMZ_REG_F22D = 89 +SYSTEMZ_REG_F23D = 90 +SYSTEMZ_REG_F24D = 91 +SYSTEMZ_REG_F25D = 92 +SYSTEMZ_REG_F26D = 93 +SYSTEMZ_REG_F27D = 94 +SYSTEMZ_REG_F28D = 95 +SYSTEMZ_REG_F29D = 96 +SYSTEMZ_REG_F30D = 97 +SYSTEMZ_REG_F31D = 98 +SYSTEMZ_REG_F0Q = 99 +SYSTEMZ_REG_F1Q = 100 +SYSTEMZ_REG_F4Q = 101 +SYSTEMZ_REG_F5Q = 102 +SYSTEMZ_REG_F8Q = 103 +SYSTEMZ_REG_F9Q = 104 +SYSTEMZ_REG_F12Q = 105 +SYSTEMZ_REG_F13Q = 106 +SYSTEMZ_REG_F0S = 107 +SYSTEMZ_REG_F1S = 108 +SYSTEMZ_REG_F2S = 109 +SYSTEMZ_REG_F3S = 110 +SYSTEMZ_REG_F4S = 111 +SYSTEMZ_REG_F5S = 112 +SYSTEMZ_REG_F6S = 113 +SYSTEMZ_REG_F7S = 114 +SYSTEMZ_REG_F8S = 115 +SYSTEMZ_REG_F9S = 116 +SYSTEMZ_REG_F10S = 117 +SYSTEMZ_REG_F11S = 118 +SYSTEMZ_REG_F12S = 119 +SYSTEMZ_REG_F13S = 120 +SYSTEMZ_REG_F14S = 121 +SYSTEMZ_REG_F15S = 122 +SYSTEMZ_REG_F16S = 123 +SYSTEMZ_REG_F17S = 124 +SYSTEMZ_REG_F18S = 125 +SYSTEMZ_REG_F19S = 126 +SYSTEMZ_REG_F20S = 127 +SYSTEMZ_REG_F21S = 128 +SYSTEMZ_REG_F22S = 129 +SYSTEMZ_REG_F23S = 130 +SYSTEMZ_REG_F24S = 131 +SYSTEMZ_REG_F25S = 132 +SYSTEMZ_REG_F26S = 133 +SYSTEMZ_REG_F27S = 134 +SYSTEMZ_REG_F28S = 135 +SYSTEMZ_REG_F29S = 136 +SYSTEMZ_REG_F30S = 137 +SYSTEMZ_REG_F31S = 138 +SYSTEMZ_REG_R0D = 139 +SYSTEMZ_REG_R1D = 140 +SYSTEMZ_REG_R2D = 141 +SYSTEMZ_REG_R3D = 142 +SYSTEMZ_REG_R4D = 143 +SYSTEMZ_REG_R5D = 144 +SYSTEMZ_REG_R6D = 145 +SYSTEMZ_REG_R7D = 146 +SYSTEMZ_REG_R8D = 147 +SYSTEMZ_REG_R9D = 148 +SYSTEMZ_REG_R10D = 149 +SYSTEMZ_REG_R11D = 150 +SYSTEMZ_REG_R12D = 151 +SYSTEMZ_REG_R13D = 152 +SYSTEMZ_REG_R14D = 153 +SYSTEMZ_REG_R15D = 154 +SYSTEMZ_REG_R0H = 155 +SYSTEMZ_REG_R1H = 156 +SYSTEMZ_REG_R2H = 157 +SYSTEMZ_REG_R3H = 158 +SYSTEMZ_REG_R4H = 159 +SYSTEMZ_REG_R5H = 160 +SYSTEMZ_REG_R6H = 161 +SYSTEMZ_REG_R7H = 162 +SYSTEMZ_REG_R8H = 163 +SYSTEMZ_REG_R9H = 164 +SYSTEMZ_REG_R10H = 165 +SYSTEMZ_REG_R11H = 166 +SYSTEMZ_REG_R12H = 167 +SYSTEMZ_REG_R13H = 168 +SYSTEMZ_REG_R14H = 169 +SYSTEMZ_REG_R15H = 170 +SYSTEMZ_REG_R0L = 171 +SYSTEMZ_REG_R1L = 172 +SYSTEMZ_REG_R2L = 173 +SYSTEMZ_REG_R3L = 174 +SYSTEMZ_REG_R4L = 175 +SYSTEMZ_REG_R5L = 176 +SYSTEMZ_REG_R6L = 177 +SYSTEMZ_REG_R7L = 178 +SYSTEMZ_REG_R8L = 179 +SYSTEMZ_REG_R9L = 180 +SYSTEMZ_REG_R10L = 181 +SYSTEMZ_REG_R11L = 182 +SYSTEMZ_REG_R12L = 183 +SYSTEMZ_REG_R13L = 184 +SYSTEMZ_REG_R14L = 185 +SYSTEMZ_REG_R15L = 186 +SYSTEMZ_REG_R0Q = 187 +SYSTEMZ_REG_R2Q = 188 +SYSTEMZ_REG_R4Q = 189 +SYSTEMZ_REG_R6Q = 190 +SYSTEMZ_REG_R8Q = 191 +SYSTEMZ_REG_R10Q = 192 +SYSTEMZ_REG_R12Q = 193 +SYSTEMZ_REG_R14Q = 194 +SYSTEMZ_REG_ENDING = 195 + +SYSTEMZ_INSN_FORM_INVALID = 0 +SYSTEMZ_INSN_FORM_INSTRXA = 1 +SYSTEMZ_INSN_FORM_INSTRXE = 2 +SYSTEMZ_INSN_FORM_INSTRRE = 3 +SYSTEMZ_INSN_FORM_INSTRR = 4 +SYSTEMZ_INSN_FORM_INSTRRFA = 5 +SYSTEMZ_INSN_FORM_INSTRILA = 6 +SYSTEMZ_INSN_FORM_INSTRXYA = 7 +SYSTEMZ_INSN_FORM_INSTRIA = 8 +SYSTEMZ_INSN_FORM_INSTRIED = 9 +SYSTEMZ_INSN_FORM_INSTSIY = 10 +SYSTEMZ_INSN_FORM_INSTSSB = 11 +SYSTEMZ_INSN_FORM_INSTRXB = 12 +SYSTEMZ_INSN_FORM_INSTRXYB = 13 +SYSTEMZ_INSN_FORM_INSTSMI = 14 +SYSTEMZ_INSN_FORM_INSTMII = 15 +SYSTEMZ_INSN_FORM_INSTRIB = 16 +SYSTEMZ_INSN_FORM_INSTRILB = 17 +SYSTEMZ_INSN_FORM_INSTRIC = 18 +SYSTEMZ_INSN_FORM_INSTRILC = 19 +SYSTEMZ_INSN_FORM_INSTRSI = 20 +SYSTEMZ_INSN_FORM_INSTRIEE = 21 +SYSTEMZ_INSN_FORM_INSTRSA = 22 +SYSTEMZ_INSN_FORM_INSTRSYA = 23 +SYSTEMZ_INSN_FORM_INSTRRFE = 24 +SYSTEMZ_INSN_FORM_INSTRSLB = 25 +SYSTEMZ_INSN_FORM_INSTS = 26 +SYSTEMZ_INSN_FORM_INSTSIL = 27 +SYSTEMZ_INSN_FORM_INSTRIS = 28 +SYSTEMZ_INSN_FORM_INSTRIEC = 29 +SYSTEMZ_INSN_FORM_INSTRIEA = 30 +SYSTEMZ_INSN_FORM_INSTRRS = 31 +SYSTEMZ_INSN_FORM_INSTRIEB = 32 +SYSTEMZ_INSN_FORM_INSTRRFC = 33 +SYSTEMZ_INSN_FORM_INSTSSA = 34 +SYSTEMZ_INSN_FORM_INSTRSYB = 35 +SYSTEMZ_INSN_FORM_INSTSI = 36 +SYSTEMZ_INSN_FORM_INSTRSB = 37 +SYSTEMZ_INSN_FORM_INSTRRFB = 38 +SYSTEMZ_INSN_FORM_INSTRRFD = 39 +SYSTEMZ_INSN_FORM_INSTSSF = 40 +SYSTEMZ_INSN_FORM_INSTSSE = 41 +SYSTEMZ_INSN_FORM_INSTRIEG = 42 +SYSTEMZ_INSN_FORM_INSTRXF = 43 +SYSTEMZ_INSN_FORM_INSTRRD = 44 +SYSTEMZ_INSN_FORM_INSTSSD = 45 +SYSTEMZ_INSN_FORM_INSTIE = 46 +SYSTEMZ_INSN_FORM_INSTE = 47 +SYSTEMZ_INSN_FORM_INSTRIEF = 48 +SYSTEMZ_INSN_FORM_INSTSSC = 49 +SYSTEMZ_INSN_FORM_INSTI = 50 +SYSTEMZ_INSN_FORM_INSTRSLA = 51 +SYSTEMZ_INSN_FORM_INSTVRRC = 52 +SYSTEMZ_INSN_FORM_INSTVRRD = 53 +SYSTEMZ_INSN_FORM_INSTVRIF = 54 +SYSTEMZ_INSN_FORM_INSTVRRA = 55 +SYSTEMZ_INSN_FORM_INSTVRRB = 56 +SYSTEMZ_INSN_FORM_INSTVRRK = 57 +SYSTEMZ_INSN_FORM_INSTVRRH = 58 +SYSTEMZ_INSN_FORM_INSTVRRJ = 59 +SYSTEMZ_INSN_FORM_INSTVRRI = 60 +SYSTEMZ_INSN_FORM_INSTVRII = 61 +SYSTEMZ_INSN_FORM_INSTVRID = 62 +SYSTEMZ_INSN_FORM_INSTVRSA = 63 +SYSTEMZ_INSN_FORM_INSTVRRE = 64 +SYSTEMZ_INSN_FORM_INSTVRIE = 65 +SYSTEMZ_INSN_FORM_INSTVRIA = 66 +SYSTEMZ_INSN_FORM_INSTVRV = 67 +SYSTEMZ_INSN_FORM_INSTVRIB = 68 +SYSTEMZ_INSN_FORM_INSTVRX = 69 +SYSTEMZ_INSN_FORM_INSTVRSC = 70 +SYSTEMZ_INSN_FORM_INSTVRIH = 71 +SYSTEMZ_INSN_FORM_INSTVRSB = 72 +SYSTEMZ_INSN_FORM_INSTVSI = 73 +SYSTEMZ_INSN_FORM_INSTVRSD = 74 +SYSTEMZ_INSN_FORM_INSTVRRF = 75 +SYSTEMZ_INSN_FORM_INSTVRIG = 76 +SYSTEMZ_INSN_FORM_INSTVRIC = 77 +SYSTEMZ_INSN_FORM_INSTVRRG = 78 + +SYSTEMZ_AM_INVALID = 0 +SYSTEMZ_AM_BD = 1 +SYSTEMZ_AM_BDX = 2 +SYSTEMZ_AM_BDL = 3 +SYSTEMZ_AM_BDR = 4 +SYSTEMZ_AM_BDV = 5 + +SYSTEMZ_INS_INVALID = 0 +SYSTEMZ_INS_A = 1 +SYSTEMZ_INS_AD = 2 +SYSTEMZ_INS_ADB = 3 +SYSTEMZ_INS_ADBR = 4 +SYSTEMZ_INS_ADR = 5 +SYSTEMZ_INS_ADTR = 6 +SYSTEMZ_INS_ADTRA = 7 +SYSTEMZ_INS_AE = 8 +SYSTEMZ_INS_AEB = 9 +SYSTEMZ_INS_AEBR = 10 +SYSTEMZ_INS_AER = 11 +SYSTEMZ_INS_AFI = 12 +SYSTEMZ_INS_AG = 13 +SYSTEMZ_INS_AGF = 14 +SYSTEMZ_INS_AGFI = 15 +SYSTEMZ_INS_AGFR = 16 +SYSTEMZ_INS_AGH = 17 +SYSTEMZ_INS_AGHI = 18 +SYSTEMZ_INS_AGHIK = 19 +SYSTEMZ_INS_AGR = 20 +SYSTEMZ_INS_AGRK = 21 +SYSTEMZ_INS_AGSI = 22 +SYSTEMZ_INS_AH = 23 +SYSTEMZ_INS_AHHHR = 24 +SYSTEMZ_INS_AHHLR = 25 +SYSTEMZ_INS_AHI = 26 +SYSTEMZ_INS_AHIK = 27 +SYSTEMZ_INS_AHY = 28 +SYSTEMZ_INS_AIH = 29 +SYSTEMZ_INS_AL = 30 +SYSTEMZ_INS_ALC = 31 +SYSTEMZ_INS_ALCG = 32 +SYSTEMZ_INS_ALCGR = 33 +SYSTEMZ_INS_ALCR = 34 +SYSTEMZ_INS_ALFI = 35 +SYSTEMZ_INS_ALG = 36 +SYSTEMZ_INS_ALGF = 37 +SYSTEMZ_INS_ALGFI = 38 +SYSTEMZ_INS_ALGFR = 39 +SYSTEMZ_INS_ALGHSIK = 40 +SYSTEMZ_INS_ALGR = 41 +SYSTEMZ_INS_ALGRK = 42 +SYSTEMZ_INS_ALGSI = 43 +SYSTEMZ_INS_ALHHHR = 44 +SYSTEMZ_INS_ALHHLR = 45 +SYSTEMZ_INS_ALHSIK = 46 +SYSTEMZ_INS_ALR = 47 +SYSTEMZ_INS_ALRK = 48 +SYSTEMZ_INS_ALSI = 49 +SYSTEMZ_INS_ALSIH = 50 +SYSTEMZ_INS_ALSIHN = 51 +SYSTEMZ_INS_ALY = 52 +SYSTEMZ_INS_AP = 53 +SYSTEMZ_INS_AR = 54 +SYSTEMZ_INS_ARK = 55 +SYSTEMZ_INS_ASI = 56 +SYSTEMZ_INS_AU = 57 +SYSTEMZ_INS_AUR = 58 +SYSTEMZ_INS_AW = 59 +SYSTEMZ_INS_AWR = 60 +SYSTEMZ_INS_AXBR = 61 +SYSTEMZ_INS_AXR = 62 +SYSTEMZ_INS_AXTR = 63 +SYSTEMZ_INS_AXTRA = 64 +SYSTEMZ_INS_AY = 65 +SYSTEMZ_INS_B = 66 +SYSTEMZ_INS_BAKR = 67 +SYSTEMZ_INS_BAL = 68 +SYSTEMZ_INS_BALR = 69 +SYSTEMZ_INS_BAS = 70 +SYSTEMZ_INS_BASR = 71 +SYSTEMZ_INS_BASSM = 72 +SYSTEMZ_INS_BE = 73 +SYSTEMZ_INS_BH = 74 +SYSTEMZ_INS_BHE = 75 +SYSTEMZ_INS_BL = 76 +SYSTEMZ_INS_BLE = 77 +SYSTEMZ_INS_BLH = 78 +SYSTEMZ_INS_BM = 79 +SYSTEMZ_INS_BNE = 80 +SYSTEMZ_INS_BNH = 81 +SYSTEMZ_INS_BNHE = 82 +SYSTEMZ_INS_BNL = 83 +SYSTEMZ_INS_BNLE = 84 +SYSTEMZ_INS_BNLH = 85 +SYSTEMZ_INS_BNM = 86 +SYSTEMZ_INS_BNO = 87 +SYSTEMZ_INS_BNP = 88 +SYSTEMZ_INS_BNZ = 89 +SYSTEMZ_INS_BO = 90 +SYSTEMZ_INS_BP = 91 +SYSTEMZ_INS_BZ = 92 +SYSTEMZ_INS_BC = 93 +SYSTEMZ_INS_BCR = 94 +SYSTEMZ_INS_BCT = 95 +SYSTEMZ_INS_BCTG = 96 +SYSTEMZ_INS_BCTGR = 97 +SYSTEMZ_INS_BCTR = 98 +SYSTEMZ_INS_BI = 99 +SYSTEMZ_INS_BIE = 100 +SYSTEMZ_INS_BIH = 101 +SYSTEMZ_INS_BIHE = 102 +SYSTEMZ_INS_BIL = 103 +SYSTEMZ_INS_BILE = 104 +SYSTEMZ_INS_BILH = 105 +SYSTEMZ_INS_BIM = 106 +SYSTEMZ_INS_BINE = 107 +SYSTEMZ_INS_BINH = 108 +SYSTEMZ_INS_BINHE = 109 +SYSTEMZ_INS_BINL = 110 +SYSTEMZ_INS_BINLE = 111 +SYSTEMZ_INS_BINLH = 112 +SYSTEMZ_INS_BINM = 113 +SYSTEMZ_INS_BINO = 114 +SYSTEMZ_INS_BINP = 115 +SYSTEMZ_INS_BINZ = 116 +SYSTEMZ_INS_BIO = 117 +SYSTEMZ_INS_BIP = 118 +SYSTEMZ_INS_BIZ = 119 +SYSTEMZ_INS_BIC = 120 +SYSTEMZ_INS_BPP = 121 +SYSTEMZ_INS_BPRP = 122 +SYSTEMZ_INS_BR = 123 +SYSTEMZ_INS_BRAS = 124 +SYSTEMZ_INS_BRASL = 125 +SYSTEMZ_INS_BER = 126 +SYSTEMZ_INS_BHR = 127 +SYSTEMZ_INS_BHER = 128 +SYSTEMZ_INS_BLR = 129 +SYSTEMZ_INS_BLER = 130 +SYSTEMZ_INS_BLHR = 131 +SYSTEMZ_INS_BMR = 132 +SYSTEMZ_INS_BNER = 133 +SYSTEMZ_INS_BNHR = 134 +SYSTEMZ_INS_BNHER = 135 +SYSTEMZ_INS_BNLR = 136 +SYSTEMZ_INS_BNLER = 137 +SYSTEMZ_INS_BNLHR = 138 +SYSTEMZ_INS_BNMR = 139 +SYSTEMZ_INS_BNOR = 140 +SYSTEMZ_INS_BNPR = 141 +SYSTEMZ_INS_BNZR = 142 +SYSTEMZ_INS_BOR = 143 +SYSTEMZ_INS_BPR = 144 +SYSTEMZ_INS_BZR = 145 +SYSTEMZ_INS_BRC = 146 +SYSTEMZ_INS_BRCL = 147 +SYSTEMZ_INS_BRCT = 148 +SYSTEMZ_INS_BRCTG = 149 +SYSTEMZ_INS_BRCTH = 150 +SYSTEMZ_INS_BRXH = 151 +SYSTEMZ_INS_BRXHG = 152 +SYSTEMZ_INS_BRXLE = 153 +SYSTEMZ_INS_BRXLG = 154 +SYSTEMZ_INS_BSA = 155 +SYSTEMZ_INS_BSG = 156 +SYSTEMZ_INS_BSM = 157 +SYSTEMZ_INS_BXH = 158 +SYSTEMZ_INS_BXHG = 159 +SYSTEMZ_INS_BXLE = 160 +SYSTEMZ_INS_BXLEG = 161 +SYSTEMZ_INS_C = 162 +SYSTEMZ_INS_CD = 163 +SYSTEMZ_INS_CDB = 164 +SYSTEMZ_INS_CDBR = 165 +SYSTEMZ_INS_CDFBR = 166 +SYSTEMZ_INS_CDFBRA = 167 +SYSTEMZ_INS_CDFR = 168 +SYSTEMZ_INS_CDFTR = 169 +SYSTEMZ_INS_CDGBR = 170 +SYSTEMZ_INS_CDGBRA = 171 +SYSTEMZ_INS_CDGR = 172 +SYSTEMZ_INS_CDGTR = 173 +SYSTEMZ_INS_CDGTRA = 174 +SYSTEMZ_INS_CDLFBR = 175 +SYSTEMZ_INS_CDLFTR = 176 +SYSTEMZ_INS_CDLGBR = 177 +SYSTEMZ_INS_CDLGTR = 178 +SYSTEMZ_INS_CDPT = 179 +SYSTEMZ_INS_CDR = 180 +SYSTEMZ_INS_CDS = 181 +SYSTEMZ_INS_CDSG = 182 +SYSTEMZ_INS_CDSTR = 183 +SYSTEMZ_INS_CDSY = 184 +SYSTEMZ_INS_CDTR = 185 +SYSTEMZ_INS_CDUTR = 186 +SYSTEMZ_INS_CDZT = 187 +SYSTEMZ_INS_CE = 188 +SYSTEMZ_INS_CEB = 189 +SYSTEMZ_INS_CEBR = 190 +SYSTEMZ_INS_CEDTR = 191 +SYSTEMZ_INS_CEFBR = 192 +SYSTEMZ_INS_CEFBRA = 193 +SYSTEMZ_INS_CEFR = 194 +SYSTEMZ_INS_CEGBR = 195 +SYSTEMZ_INS_CEGBRA = 196 +SYSTEMZ_INS_CEGR = 197 +SYSTEMZ_INS_CELFBR = 198 +SYSTEMZ_INS_CELGBR = 199 +SYSTEMZ_INS_CER = 200 +SYSTEMZ_INS_CEXTR = 201 +SYSTEMZ_INS_CFC = 202 +SYSTEMZ_INS_CFDBR = 203 +SYSTEMZ_INS_CFDBRA = 204 +SYSTEMZ_INS_CFDR = 205 +SYSTEMZ_INS_CFDTR = 206 +SYSTEMZ_INS_CFEBR = 207 +SYSTEMZ_INS_CFEBRA = 208 +SYSTEMZ_INS_CFER = 209 +SYSTEMZ_INS_CFI = 210 +SYSTEMZ_INS_CFXBR = 211 +SYSTEMZ_INS_CFXBRA = 212 +SYSTEMZ_INS_CFXR = 213 +SYSTEMZ_INS_CFXTR = 214 +SYSTEMZ_INS_CG = 215 +SYSTEMZ_INS_CGDBR = 216 +SYSTEMZ_INS_CGDBRA = 217 +SYSTEMZ_INS_CGDR = 218 +SYSTEMZ_INS_CGDTR = 219 +SYSTEMZ_INS_CGDTRA = 220 +SYSTEMZ_INS_CGEBR = 221 +SYSTEMZ_INS_CGEBRA = 222 +SYSTEMZ_INS_CGER = 223 +SYSTEMZ_INS_CGF = 224 +SYSTEMZ_INS_CGFI = 225 +SYSTEMZ_INS_CGFR = 226 +SYSTEMZ_INS_CGFRL = 227 +SYSTEMZ_INS_CGH = 228 +SYSTEMZ_INS_CGHI = 229 +SYSTEMZ_INS_CGHRL = 230 +SYSTEMZ_INS_CGHSI = 231 +SYSTEMZ_INS_CGIB = 232 +SYSTEMZ_INS_CGIBE = 233 +SYSTEMZ_INS_CGIBH = 234 +SYSTEMZ_INS_CGIBHE = 235 +SYSTEMZ_INS_CGIBL = 236 +SYSTEMZ_INS_CGIBLE = 237 +SYSTEMZ_INS_CGIBLH = 238 +SYSTEMZ_INS_CGIBNE = 239 +SYSTEMZ_INS_CGIBNH = 240 +SYSTEMZ_INS_CGIBNHE = 241 +SYSTEMZ_INS_CGIBNL = 242 +SYSTEMZ_INS_CGIBNLE = 243 +SYSTEMZ_INS_CGIBNLH = 244 +SYSTEMZ_INS_CGIJ = 245 +SYSTEMZ_INS_CGIJE = 246 +SYSTEMZ_INS_CGIJH = 247 +SYSTEMZ_INS_CGIJHE = 248 +SYSTEMZ_INS_CGIJL = 249 +SYSTEMZ_INS_CGIJLE = 250 +SYSTEMZ_INS_CGIJLH = 251 +SYSTEMZ_INS_CGIJNE = 252 +SYSTEMZ_INS_CGIJNH = 253 +SYSTEMZ_INS_CGIJNHE = 254 +SYSTEMZ_INS_CGIJNL = 255 +SYSTEMZ_INS_CGIJNLE = 256 +SYSTEMZ_INS_CGIJNLH = 257 +SYSTEMZ_INS_CGIT = 258 +SYSTEMZ_INS_CGITE = 259 +SYSTEMZ_INS_CGITH = 260 +SYSTEMZ_INS_CGITHE = 261 +SYSTEMZ_INS_CGITL = 262 +SYSTEMZ_INS_CGITLE = 263 +SYSTEMZ_INS_CGITLH = 264 +SYSTEMZ_INS_CGITNE = 265 +SYSTEMZ_INS_CGITNH = 266 +SYSTEMZ_INS_CGITNHE = 267 +SYSTEMZ_INS_CGITNL = 268 +SYSTEMZ_INS_CGITNLE = 269 +SYSTEMZ_INS_CGITNLH = 270 +SYSTEMZ_INS_CGR = 271 +SYSTEMZ_INS_CGRB = 272 +SYSTEMZ_INS_CGRBE = 273 +SYSTEMZ_INS_CGRBH = 274 +SYSTEMZ_INS_CGRBHE = 275 +SYSTEMZ_INS_CGRBL = 276 +SYSTEMZ_INS_CGRBLE = 277 +SYSTEMZ_INS_CGRBLH = 278 +SYSTEMZ_INS_CGRBNE = 279 +SYSTEMZ_INS_CGRBNH = 280 +SYSTEMZ_INS_CGRBNHE = 281 +SYSTEMZ_INS_CGRBNL = 282 +SYSTEMZ_INS_CGRBNLE = 283 +SYSTEMZ_INS_CGRBNLH = 284 +SYSTEMZ_INS_CGRJ = 285 +SYSTEMZ_INS_CGRJE = 286 +SYSTEMZ_INS_CGRJH = 287 +SYSTEMZ_INS_CGRJHE = 288 +SYSTEMZ_INS_CGRJL = 289 +SYSTEMZ_INS_CGRJLE = 290 +SYSTEMZ_INS_CGRJLH = 291 +SYSTEMZ_INS_CGRJNE = 292 +SYSTEMZ_INS_CGRJNH = 293 +SYSTEMZ_INS_CGRJNHE = 294 +SYSTEMZ_INS_CGRJNL = 295 +SYSTEMZ_INS_CGRJNLE = 296 +SYSTEMZ_INS_CGRJNLH = 297 +SYSTEMZ_INS_CGRL = 298 +SYSTEMZ_INS_CGRT = 299 +SYSTEMZ_INS_CGRTE = 300 +SYSTEMZ_INS_CGRTH = 301 +SYSTEMZ_INS_CGRTHE = 302 +SYSTEMZ_INS_CGRTL = 303 +SYSTEMZ_INS_CGRTLE = 304 +SYSTEMZ_INS_CGRTLH = 305 +SYSTEMZ_INS_CGRTNE = 306 +SYSTEMZ_INS_CGRTNH = 307 +SYSTEMZ_INS_CGRTNHE = 308 +SYSTEMZ_INS_CGRTNL = 309 +SYSTEMZ_INS_CGRTNLE = 310 +SYSTEMZ_INS_CGRTNLH = 311 +SYSTEMZ_INS_CGXBR = 312 +SYSTEMZ_INS_CGXBRA = 313 +SYSTEMZ_INS_CGXR = 314 +SYSTEMZ_INS_CGXTR = 315 +SYSTEMZ_INS_CGXTRA = 316 +SYSTEMZ_INS_CH = 317 +SYSTEMZ_INS_CHF = 318 +SYSTEMZ_INS_CHHR = 319 +SYSTEMZ_INS_CHHSI = 320 +SYSTEMZ_INS_CHI = 321 +SYSTEMZ_INS_CHLR = 322 +SYSTEMZ_INS_CHRL = 323 +SYSTEMZ_INS_CHSI = 324 +SYSTEMZ_INS_CHY = 325 +SYSTEMZ_INS_CIB = 326 +SYSTEMZ_INS_CIBE = 327 +SYSTEMZ_INS_CIBH = 328 +SYSTEMZ_INS_CIBHE = 329 +SYSTEMZ_INS_CIBL = 330 +SYSTEMZ_INS_CIBLE = 331 +SYSTEMZ_INS_CIBLH = 332 +SYSTEMZ_INS_CIBNE = 333 +SYSTEMZ_INS_CIBNH = 334 +SYSTEMZ_INS_CIBNHE = 335 +SYSTEMZ_INS_CIBNL = 336 +SYSTEMZ_INS_CIBNLE = 337 +SYSTEMZ_INS_CIBNLH = 338 +SYSTEMZ_INS_CIH = 339 +SYSTEMZ_INS_CIJ = 340 +SYSTEMZ_INS_CIJE = 341 +SYSTEMZ_INS_CIJH = 342 +SYSTEMZ_INS_CIJHE = 343 +SYSTEMZ_INS_CIJL = 344 +SYSTEMZ_INS_CIJLE = 345 +SYSTEMZ_INS_CIJLH = 346 +SYSTEMZ_INS_CIJNE = 347 +SYSTEMZ_INS_CIJNH = 348 +SYSTEMZ_INS_CIJNHE = 349 +SYSTEMZ_INS_CIJNL = 350 +SYSTEMZ_INS_CIJNLE = 351 +SYSTEMZ_INS_CIJNLH = 352 +SYSTEMZ_INS_CIT = 353 +SYSTEMZ_INS_CITE = 354 +SYSTEMZ_INS_CITH = 355 +SYSTEMZ_INS_CITHE = 356 +SYSTEMZ_INS_CITL = 357 +SYSTEMZ_INS_CITLE = 358 +SYSTEMZ_INS_CITLH = 359 +SYSTEMZ_INS_CITNE = 360 +SYSTEMZ_INS_CITNH = 361 +SYSTEMZ_INS_CITNHE = 362 +SYSTEMZ_INS_CITNL = 363 +SYSTEMZ_INS_CITNLE = 364 +SYSTEMZ_INS_CITNLH = 365 +SYSTEMZ_INS_CKSM = 366 +SYSTEMZ_INS_CL = 367 +SYSTEMZ_INS_CLC = 368 +SYSTEMZ_INS_CLCL = 369 +SYSTEMZ_INS_CLCLE = 370 +SYSTEMZ_INS_CLCLU = 371 +SYSTEMZ_INS_CLFDBR = 372 +SYSTEMZ_INS_CLFDTR = 373 +SYSTEMZ_INS_CLFEBR = 374 +SYSTEMZ_INS_CLFHSI = 375 +SYSTEMZ_INS_CLFI = 376 +SYSTEMZ_INS_CLFIT = 377 +SYSTEMZ_INS_CLFITE = 378 +SYSTEMZ_INS_CLFITH = 379 +SYSTEMZ_INS_CLFITHE = 380 +SYSTEMZ_INS_CLFITL = 381 +SYSTEMZ_INS_CLFITLE = 382 +SYSTEMZ_INS_CLFITLH = 383 +SYSTEMZ_INS_CLFITNE = 384 +SYSTEMZ_INS_CLFITNH = 385 +SYSTEMZ_INS_CLFITNHE = 386 +SYSTEMZ_INS_CLFITNL = 387 +SYSTEMZ_INS_CLFITNLE = 388 +SYSTEMZ_INS_CLFITNLH = 389 +SYSTEMZ_INS_CLFXBR = 390 +SYSTEMZ_INS_CLFXTR = 391 +SYSTEMZ_INS_CLG = 392 +SYSTEMZ_INS_CLGDBR = 393 +SYSTEMZ_INS_CLGDTR = 394 +SYSTEMZ_INS_CLGEBR = 395 +SYSTEMZ_INS_CLGF = 396 +SYSTEMZ_INS_CLGFI = 397 +SYSTEMZ_INS_CLGFR = 398 +SYSTEMZ_INS_CLGFRL = 399 +SYSTEMZ_INS_CLGHRL = 400 +SYSTEMZ_INS_CLGHSI = 401 +SYSTEMZ_INS_CLGIB = 402 +SYSTEMZ_INS_CLGIBE = 403 +SYSTEMZ_INS_CLGIBH = 404 +SYSTEMZ_INS_CLGIBHE = 405 +SYSTEMZ_INS_CLGIBL = 406 +SYSTEMZ_INS_CLGIBLE = 407 +SYSTEMZ_INS_CLGIBLH = 408 +SYSTEMZ_INS_CLGIBNE = 409 +SYSTEMZ_INS_CLGIBNH = 410 +SYSTEMZ_INS_CLGIBNHE = 411 +SYSTEMZ_INS_CLGIBNL = 412 +SYSTEMZ_INS_CLGIBNLE = 413 +SYSTEMZ_INS_CLGIBNLH = 414 +SYSTEMZ_INS_CLGIJ = 415 +SYSTEMZ_INS_CLGIJE = 416 +SYSTEMZ_INS_CLGIJH = 417 +SYSTEMZ_INS_CLGIJHE = 418 +SYSTEMZ_INS_CLGIJL = 419 +SYSTEMZ_INS_CLGIJLE = 420 +SYSTEMZ_INS_CLGIJLH = 421 +SYSTEMZ_INS_CLGIJNE = 422 +SYSTEMZ_INS_CLGIJNH = 423 +SYSTEMZ_INS_CLGIJNHE = 424 +SYSTEMZ_INS_CLGIJNL = 425 +SYSTEMZ_INS_CLGIJNLE = 426 +SYSTEMZ_INS_CLGIJNLH = 427 +SYSTEMZ_INS_CLGIT = 428 +SYSTEMZ_INS_CLGITE = 429 +SYSTEMZ_INS_CLGITH = 430 +SYSTEMZ_INS_CLGITHE = 431 +SYSTEMZ_INS_CLGITL = 432 +SYSTEMZ_INS_CLGITLE = 433 +SYSTEMZ_INS_CLGITLH = 434 +SYSTEMZ_INS_CLGITNE = 435 +SYSTEMZ_INS_CLGITNH = 436 +SYSTEMZ_INS_CLGITNHE = 437 +SYSTEMZ_INS_CLGITNL = 438 +SYSTEMZ_INS_CLGITNLE = 439 +SYSTEMZ_INS_CLGITNLH = 440 +SYSTEMZ_INS_CLGR = 441 +SYSTEMZ_INS_CLGRB = 442 +SYSTEMZ_INS_CLGRBE = 443 +SYSTEMZ_INS_CLGRBH = 444 +SYSTEMZ_INS_CLGRBHE = 445 +SYSTEMZ_INS_CLGRBL = 446 +SYSTEMZ_INS_CLGRBLE = 447 +SYSTEMZ_INS_CLGRBLH = 448 +SYSTEMZ_INS_CLGRBNE = 449 +SYSTEMZ_INS_CLGRBNH = 450 +SYSTEMZ_INS_CLGRBNHE = 451 +SYSTEMZ_INS_CLGRBNL = 452 +SYSTEMZ_INS_CLGRBNLE = 453 +SYSTEMZ_INS_CLGRBNLH = 454 +SYSTEMZ_INS_CLGRJ = 455 +SYSTEMZ_INS_CLGRJE = 456 +SYSTEMZ_INS_CLGRJH = 457 +SYSTEMZ_INS_CLGRJHE = 458 +SYSTEMZ_INS_CLGRJL = 459 +SYSTEMZ_INS_CLGRJLE = 460 +SYSTEMZ_INS_CLGRJLH = 461 +SYSTEMZ_INS_CLGRJNE = 462 +SYSTEMZ_INS_CLGRJNH = 463 +SYSTEMZ_INS_CLGRJNHE = 464 +SYSTEMZ_INS_CLGRJNL = 465 +SYSTEMZ_INS_CLGRJNLE = 466 +SYSTEMZ_INS_CLGRJNLH = 467 +SYSTEMZ_INS_CLGRL = 468 +SYSTEMZ_INS_CLGRT = 469 +SYSTEMZ_INS_CLGRTE = 470 +SYSTEMZ_INS_CLGRTH = 471 +SYSTEMZ_INS_CLGRTHE = 472 +SYSTEMZ_INS_CLGRTL = 473 +SYSTEMZ_INS_CLGRTLE = 474 +SYSTEMZ_INS_CLGRTLH = 475 +SYSTEMZ_INS_CLGRTNE = 476 +SYSTEMZ_INS_CLGRTNH = 477 +SYSTEMZ_INS_CLGRTNHE = 478 +SYSTEMZ_INS_CLGRTNL = 479 +SYSTEMZ_INS_CLGRTNLE = 480 +SYSTEMZ_INS_CLGRTNLH = 481 +SYSTEMZ_INS_CLGT = 482 +SYSTEMZ_INS_CLGTE = 483 +SYSTEMZ_INS_CLGTH = 484 +SYSTEMZ_INS_CLGTHE = 485 +SYSTEMZ_INS_CLGTL = 486 +SYSTEMZ_INS_CLGTLE = 487 +SYSTEMZ_INS_CLGTLH = 488 +SYSTEMZ_INS_CLGTNE = 489 +SYSTEMZ_INS_CLGTNH = 490 +SYSTEMZ_INS_CLGTNHE = 491 +SYSTEMZ_INS_CLGTNL = 492 +SYSTEMZ_INS_CLGTNLE = 493 +SYSTEMZ_INS_CLGTNLH = 494 +SYSTEMZ_INS_CLGXBR = 495 +SYSTEMZ_INS_CLGXTR = 496 +SYSTEMZ_INS_CLHF = 497 +SYSTEMZ_INS_CLHHR = 498 +SYSTEMZ_INS_CLHHSI = 499 +SYSTEMZ_INS_CLHLR = 500 +SYSTEMZ_INS_CLHRL = 501 +SYSTEMZ_INS_CLI = 502 +SYSTEMZ_INS_CLIB = 503 +SYSTEMZ_INS_CLIBE = 504 +SYSTEMZ_INS_CLIBH = 505 +SYSTEMZ_INS_CLIBHE = 506 +SYSTEMZ_INS_CLIBL = 507 +SYSTEMZ_INS_CLIBLE = 508 +SYSTEMZ_INS_CLIBLH = 509 +SYSTEMZ_INS_CLIBNE = 510 +SYSTEMZ_INS_CLIBNH = 511 +SYSTEMZ_INS_CLIBNHE = 512 +SYSTEMZ_INS_CLIBNL = 513 +SYSTEMZ_INS_CLIBNLE = 514 +SYSTEMZ_INS_CLIBNLH = 515 +SYSTEMZ_INS_CLIH = 516 +SYSTEMZ_INS_CLIJ = 517 +SYSTEMZ_INS_CLIJE = 518 +SYSTEMZ_INS_CLIJH = 519 +SYSTEMZ_INS_CLIJHE = 520 +SYSTEMZ_INS_CLIJL = 521 +SYSTEMZ_INS_CLIJLE = 522 +SYSTEMZ_INS_CLIJLH = 523 +SYSTEMZ_INS_CLIJNE = 524 +SYSTEMZ_INS_CLIJNH = 525 +SYSTEMZ_INS_CLIJNHE = 526 +SYSTEMZ_INS_CLIJNL = 527 +SYSTEMZ_INS_CLIJNLE = 528 +SYSTEMZ_INS_CLIJNLH = 529 +SYSTEMZ_INS_CLIY = 530 +SYSTEMZ_INS_CLM = 531 +SYSTEMZ_INS_CLMH = 532 +SYSTEMZ_INS_CLMY = 533 +SYSTEMZ_INS_CLR = 534 +SYSTEMZ_INS_CLRB = 535 +SYSTEMZ_INS_CLRBE = 536 +SYSTEMZ_INS_CLRBH = 537 +SYSTEMZ_INS_CLRBHE = 538 +SYSTEMZ_INS_CLRBL = 539 +SYSTEMZ_INS_CLRBLE = 540 +SYSTEMZ_INS_CLRBLH = 541 +SYSTEMZ_INS_CLRBNE = 542 +SYSTEMZ_INS_CLRBNH = 543 +SYSTEMZ_INS_CLRBNHE = 544 +SYSTEMZ_INS_CLRBNL = 545 +SYSTEMZ_INS_CLRBNLE = 546 +SYSTEMZ_INS_CLRBNLH = 547 +SYSTEMZ_INS_CLRJ = 548 +SYSTEMZ_INS_CLRJE = 549 +SYSTEMZ_INS_CLRJH = 550 +SYSTEMZ_INS_CLRJHE = 551 +SYSTEMZ_INS_CLRJL = 552 +SYSTEMZ_INS_CLRJLE = 553 +SYSTEMZ_INS_CLRJLH = 554 +SYSTEMZ_INS_CLRJNE = 555 +SYSTEMZ_INS_CLRJNH = 556 +SYSTEMZ_INS_CLRJNHE = 557 +SYSTEMZ_INS_CLRJNL = 558 +SYSTEMZ_INS_CLRJNLE = 559 +SYSTEMZ_INS_CLRJNLH = 560 +SYSTEMZ_INS_CLRL = 561 +SYSTEMZ_INS_CLRT = 562 +SYSTEMZ_INS_CLRTE = 563 +SYSTEMZ_INS_CLRTH = 564 +SYSTEMZ_INS_CLRTHE = 565 +SYSTEMZ_INS_CLRTL = 566 +SYSTEMZ_INS_CLRTLE = 567 +SYSTEMZ_INS_CLRTLH = 568 +SYSTEMZ_INS_CLRTNE = 569 +SYSTEMZ_INS_CLRTNH = 570 +SYSTEMZ_INS_CLRTNHE = 571 +SYSTEMZ_INS_CLRTNL = 572 +SYSTEMZ_INS_CLRTNLE = 573 +SYSTEMZ_INS_CLRTNLH = 574 +SYSTEMZ_INS_CLST = 575 +SYSTEMZ_INS_CLT = 576 +SYSTEMZ_INS_CLTE = 577 +SYSTEMZ_INS_CLTH = 578 +SYSTEMZ_INS_CLTHE = 579 +SYSTEMZ_INS_CLTL = 580 +SYSTEMZ_INS_CLTLE = 581 +SYSTEMZ_INS_CLTLH = 582 +SYSTEMZ_INS_CLTNE = 583 +SYSTEMZ_INS_CLTNH = 584 +SYSTEMZ_INS_CLTNHE = 585 +SYSTEMZ_INS_CLTNL = 586 +SYSTEMZ_INS_CLTNLE = 587 +SYSTEMZ_INS_CLTNLH = 588 +SYSTEMZ_INS_CLY = 589 +SYSTEMZ_INS_CMPSC = 590 +SYSTEMZ_INS_CP = 591 +SYSTEMZ_INS_CPDT = 592 +SYSTEMZ_INS_CPSDR = 593 +SYSTEMZ_INS_CPXT = 594 +SYSTEMZ_INS_CPYA = 595 +SYSTEMZ_INS_CR = 596 +SYSTEMZ_INS_CRB = 597 +SYSTEMZ_INS_CRBE = 598 +SYSTEMZ_INS_CRBH = 599 +SYSTEMZ_INS_CRBHE = 600 +SYSTEMZ_INS_CRBL = 601 +SYSTEMZ_INS_CRBLE = 602 +SYSTEMZ_INS_CRBLH = 603 +SYSTEMZ_INS_CRBNE = 604 +SYSTEMZ_INS_CRBNH = 605 +SYSTEMZ_INS_CRBNHE = 606 +SYSTEMZ_INS_CRBNL = 607 +SYSTEMZ_INS_CRBNLE = 608 +SYSTEMZ_INS_CRBNLH = 609 +SYSTEMZ_INS_CRDTE = 610 +SYSTEMZ_INS_CRJ = 611 +SYSTEMZ_INS_CRJE = 612 +SYSTEMZ_INS_CRJH = 613 +SYSTEMZ_INS_CRJHE = 614 +SYSTEMZ_INS_CRJL = 615 +SYSTEMZ_INS_CRJLE = 616 +SYSTEMZ_INS_CRJLH = 617 +SYSTEMZ_INS_CRJNE = 618 +SYSTEMZ_INS_CRJNH = 619 +SYSTEMZ_INS_CRJNHE = 620 +SYSTEMZ_INS_CRJNL = 621 +SYSTEMZ_INS_CRJNLE = 622 +SYSTEMZ_INS_CRJNLH = 623 +SYSTEMZ_INS_CRL = 624 +SYSTEMZ_INS_CRT = 625 +SYSTEMZ_INS_CRTE = 626 +SYSTEMZ_INS_CRTH = 627 +SYSTEMZ_INS_CRTHE = 628 +SYSTEMZ_INS_CRTL = 629 +SYSTEMZ_INS_CRTLE = 630 +SYSTEMZ_INS_CRTLH = 631 +SYSTEMZ_INS_CRTNE = 632 +SYSTEMZ_INS_CRTNH = 633 +SYSTEMZ_INS_CRTNHE = 634 +SYSTEMZ_INS_CRTNL = 635 +SYSTEMZ_INS_CRTNLE = 636 +SYSTEMZ_INS_CRTNLH = 637 +SYSTEMZ_INS_CS = 638 +SYSTEMZ_INS_CSCH = 639 +SYSTEMZ_INS_CSDTR = 640 +SYSTEMZ_INS_CSG = 641 +SYSTEMZ_INS_CSP = 642 +SYSTEMZ_INS_CSPG = 643 +SYSTEMZ_INS_CSST = 644 +SYSTEMZ_INS_CSXTR = 645 +SYSTEMZ_INS_CSY = 646 +SYSTEMZ_INS_CU12 = 647 +SYSTEMZ_INS_CU14 = 648 +SYSTEMZ_INS_CU21 = 649 +SYSTEMZ_INS_CU24 = 650 +SYSTEMZ_INS_CU41 = 651 +SYSTEMZ_INS_CU42 = 652 +SYSTEMZ_INS_CUDTR = 653 +SYSTEMZ_INS_CUSE = 654 +SYSTEMZ_INS_CUTFU = 655 +SYSTEMZ_INS_CUUTF = 656 +SYSTEMZ_INS_CUXTR = 657 +SYSTEMZ_INS_CVB = 658 +SYSTEMZ_INS_CVBG = 659 +SYSTEMZ_INS_CVBY = 660 +SYSTEMZ_INS_CVD = 661 +SYSTEMZ_INS_CVDG = 662 +SYSTEMZ_INS_CVDY = 663 +SYSTEMZ_INS_CXBR = 664 +SYSTEMZ_INS_CXFBR = 665 +SYSTEMZ_INS_CXFBRA = 666 +SYSTEMZ_INS_CXFR = 667 +SYSTEMZ_INS_CXFTR = 668 +SYSTEMZ_INS_CXGBR = 669 +SYSTEMZ_INS_CXGBRA = 670 +SYSTEMZ_INS_CXGR = 671 +SYSTEMZ_INS_CXGTR = 672 +SYSTEMZ_INS_CXGTRA = 673 +SYSTEMZ_INS_CXLFBR = 674 +SYSTEMZ_INS_CXLFTR = 675 +SYSTEMZ_INS_CXLGBR = 676 +SYSTEMZ_INS_CXLGTR = 677 +SYSTEMZ_INS_CXPT = 678 +SYSTEMZ_INS_CXR = 679 +SYSTEMZ_INS_CXSTR = 680 +SYSTEMZ_INS_CXTR = 681 +SYSTEMZ_INS_CXUTR = 682 +SYSTEMZ_INS_CXZT = 683 +SYSTEMZ_INS_CY = 684 +SYSTEMZ_INS_CZDT = 685 +SYSTEMZ_INS_CZXT = 686 +SYSTEMZ_INS_D = 687 +SYSTEMZ_INS_DD = 688 +SYSTEMZ_INS_DDB = 689 +SYSTEMZ_INS_DDBR = 690 +SYSTEMZ_INS_DDR = 691 +SYSTEMZ_INS_DDTR = 692 +SYSTEMZ_INS_DDTRA = 693 +SYSTEMZ_INS_DE = 694 +SYSTEMZ_INS_DEB = 695 +SYSTEMZ_INS_DEBR = 696 +SYSTEMZ_INS_DER = 697 +SYSTEMZ_INS_DFLTCC = 698 +SYSTEMZ_INS_DIAG = 699 +SYSTEMZ_INS_DIDBR = 700 +SYSTEMZ_INS_DIEBR = 701 +SYSTEMZ_INS_DL = 702 +SYSTEMZ_INS_DLG = 703 +SYSTEMZ_INS_DLGR = 704 +SYSTEMZ_INS_DLR = 705 +SYSTEMZ_INS_DP = 706 +SYSTEMZ_INS_DR = 707 +SYSTEMZ_INS_DSG = 708 +SYSTEMZ_INS_DSGF = 709 +SYSTEMZ_INS_DSGFR = 710 +SYSTEMZ_INS_DSGR = 711 +SYSTEMZ_INS_DXBR = 712 +SYSTEMZ_INS_DXR = 713 +SYSTEMZ_INS_DXTR = 714 +SYSTEMZ_INS_DXTRA = 715 +SYSTEMZ_INS_EAR = 716 +SYSTEMZ_INS_ECAG = 717 +SYSTEMZ_INS_ECCTR = 718 +SYSTEMZ_INS_ECPGA = 719 +SYSTEMZ_INS_ECTG = 720 +SYSTEMZ_INS_ED = 721 +SYSTEMZ_INS_EDMK = 722 +SYSTEMZ_INS_EEDTR = 723 +SYSTEMZ_INS_EEXTR = 724 +SYSTEMZ_INS_EFPC = 725 +SYSTEMZ_INS_EPAIR = 726 +SYSTEMZ_INS_EPAR = 727 +SYSTEMZ_INS_EPCTR = 728 +SYSTEMZ_INS_EPSW = 729 +SYSTEMZ_INS_EREG = 730 +SYSTEMZ_INS_EREGG = 731 +SYSTEMZ_INS_ESAIR = 732 +SYSTEMZ_INS_ESAR = 733 +SYSTEMZ_INS_ESDTR = 734 +SYSTEMZ_INS_ESEA = 735 +SYSTEMZ_INS_ESTA = 736 +SYSTEMZ_INS_ESXTR = 737 +SYSTEMZ_INS_ETND = 738 +SYSTEMZ_INS_EX = 739 +SYSTEMZ_INS_EXRL = 740 +SYSTEMZ_INS_FIDBR = 741 +SYSTEMZ_INS_FIDBRA = 742 +SYSTEMZ_INS_FIDR = 743 +SYSTEMZ_INS_FIDTR = 744 +SYSTEMZ_INS_FIEBR = 745 +SYSTEMZ_INS_FIEBRA = 746 +SYSTEMZ_INS_FIER = 747 +SYSTEMZ_INS_FIXBR = 748 +SYSTEMZ_INS_FIXBRA = 749 +SYSTEMZ_INS_FIXR = 750 +SYSTEMZ_INS_FIXTR = 751 +SYSTEMZ_INS_FLOGR = 752 +SYSTEMZ_INS_HDR = 753 +SYSTEMZ_INS_HER = 754 +SYSTEMZ_INS_HSCH = 755 +SYSTEMZ_INS_IAC = 756 +SYSTEMZ_INS_IC = 757 +SYSTEMZ_INS_ICM = 758 +SYSTEMZ_INS_ICMH = 759 +SYSTEMZ_INS_ICMY = 760 +SYSTEMZ_INS_ICY = 761 +SYSTEMZ_INS_IDTE = 762 +SYSTEMZ_INS_IEDTR = 763 +SYSTEMZ_INS_IEXTR = 764 +SYSTEMZ_INS_IIHF = 765 +SYSTEMZ_INS_IIHH = 766 +SYSTEMZ_INS_IIHL = 767 +SYSTEMZ_INS_IILF = 768 +SYSTEMZ_INS_IILH = 769 +SYSTEMZ_INS_IILL = 770 +SYSTEMZ_INS_IPK = 771 +SYSTEMZ_INS_IPM = 772 +SYSTEMZ_INS_IPTE = 773 +SYSTEMZ_INS_IRBM = 774 +SYSTEMZ_INS_ISKE = 775 +SYSTEMZ_INS_IVSK = 776 +SYSTEMZ_INS_J = 777 +SYSTEMZ_INS_JE = 778 +SYSTEMZ_INS_JH = 779 +SYSTEMZ_INS_JHE = 780 +SYSTEMZ_INS_JL = 781 +SYSTEMZ_INS_JLE = 782 +SYSTEMZ_INS_JLH = 783 +SYSTEMZ_INS_JM = 784 +SYSTEMZ_INS_JNE = 785 +SYSTEMZ_INS_JNH = 786 +SYSTEMZ_INS_JNHE = 787 +SYSTEMZ_INS_JNL = 788 +SYSTEMZ_INS_JNLE = 789 +SYSTEMZ_INS_JNLH = 790 +SYSTEMZ_INS_JNM = 791 +SYSTEMZ_INS_JNO = 792 +SYSTEMZ_INS_JNP = 793 +SYSTEMZ_INS_JNZ = 794 +SYSTEMZ_INS_JO = 795 +SYSTEMZ_INS_JP = 796 +SYSTEMZ_INS_JZ = 797 +SYSTEMZ_INS_J_G_LU_ = 798 +SYSTEMZ_INS_J_G_L_E = 799 +SYSTEMZ_INS_J_G_L_H = 800 +SYSTEMZ_INS_J_G_L_HE = 801 +SYSTEMZ_INS_J_G_L_L = 802 +SYSTEMZ_INS_J_G_L_LE = 803 +SYSTEMZ_INS_J_G_L_LH = 804 +SYSTEMZ_INS_J_G_L_M = 805 +SYSTEMZ_INS_J_G_L_NE = 806 +SYSTEMZ_INS_J_G_L_NH = 807 +SYSTEMZ_INS_J_G_L_NHE = 808 +SYSTEMZ_INS_J_G_L_NL = 809 +SYSTEMZ_INS_J_G_L_NLE = 810 +SYSTEMZ_INS_J_G_L_NLH = 811 +SYSTEMZ_INS_J_G_L_NM = 812 +SYSTEMZ_INS_J_G_L_NO = 813 +SYSTEMZ_INS_J_G_L_NP = 814 +SYSTEMZ_INS_J_G_L_NZ = 815 +SYSTEMZ_INS_J_G_L_O = 816 +SYSTEMZ_INS_J_G_L_P = 817 +SYSTEMZ_INS_J_G_L_Z = 818 +SYSTEMZ_INS_KDB = 819 +SYSTEMZ_INS_KDBR = 820 +SYSTEMZ_INS_KDSA = 821 +SYSTEMZ_INS_KDTR = 822 +SYSTEMZ_INS_KEB = 823 +SYSTEMZ_INS_KEBR = 824 +SYSTEMZ_INS_KIMD = 825 +SYSTEMZ_INS_KLMD = 826 +SYSTEMZ_INS_KM = 827 +SYSTEMZ_INS_KMA = 828 +SYSTEMZ_INS_KMAC = 829 +SYSTEMZ_INS_KMC = 830 +SYSTEMZ_INS_KMCTR = 831 +SYSTEMZ_INS_KMF = 832 +SYSTEMZ_INS_KMO = 833 +SYSTEMZ_INS_KXBR = 834 +SYSTEMZ_INS_KXTR = 835 +SYSTEMZ_INS_L = 836 +SYSTEMZ_INS_LA = 837 +SYSTEMZ_INS_LAA = 838 +SYSTEMZ_INS_LAAG = 839 +SYSTEMZ_INS_LAAL = 840 +SYSTEMZ_INS_LAALG = 841 +SYSTEMZ_INS_LAE = 842 +SYSTEMZ_INS_LAEY = 843 +SYSTEMZ_INS_LAM = 844 +SYSTEMZ_INS_LAMY = 845 +SYSTEMZ_INS_LAN = 846 +SYSTEMZ_INS_LANG = 847 +SYSTEMZ_INS_LAO = 848 +SYSTEMZ_INS_LAOG = 849 +SYSTEMZ_INS_LARL = 850 +SYSTEMZ_INS_LASP = 851 +SYSTEMZ_INS_LAT = 852 +SYSTEMZ_INS_LAX = 853 +SYSTEMZ_INS_LAXG = 854 +SYSTEMZ_INS_LAY = 855 +SYSTEMZ_INS_LB = 856 +SYSTEMZ_INS_LBEAR = 857 +SYSTEMZ_INS_LBH = 858 +SYSTEMZ_INS_LBR = 859 +SYSTEMZ_INS_LCBB = 860 +SYSTEMZ_INS_LCCTL = 861 +SYSTEMZ_INS_LCDBR = 862 +SYSTEMZ_INS_LCDFR = 863 +SYSTEMZ_INS_LCDR = 864 +SYSTEMZ_INS_LCEBR = 865 +SYSTEMZ_INS_LCER = 866 +SYSTEMZ_INS_LCGFR = 867 +SYSTEMZ_INS_LCGR = 868 +SYSTEMZ_INS_LCR = 869 +SYSTEMZ_INS_LCTL = 870 +SYSTEMZ_INS_LCTLG = 871 +SYSTEMZ_INS_LCXBR = 872 +SYSTEMZ_INS_LCXR = 873 +SYSTEMZ_INS_LD = 874 +SYSTEMZ_INS_LDE = 875 +SYSTEMZ_INS_LDEB = 876 +SYSTEMZ_INS_LDEBR = 877 +SYSTEMZ_INS_LDER = 878 +SYSTEMZ_INS_LDETR = 879 +SYSTEMZ_INS_LDGR = 880 +SYSTEMZ_INS_LDR = 881 +SYSTEMZ_INS_LDXBR = 882 +SYSTEMZ_INS_LDXBRA = 883 +SYSTEMZ_INS_LDXR = 884 +SYSTEMZ_INS_LDXTR = 885 +SYSTEMZ_INS_LDY = 886 +SYSTEMZ_INS_LE = 887 +SYSTEMZ_INS_LEDBR = 888 +SYSTEMZ_INS_LEDBRA = 889 +SYSTEMZ_INS_LEDR = 890 +SYSTEMZ_INS_LEDTR = 891 +SYSTEMZ_INS_LER = 892 +SYSTEMZ_INS_LEXBR = 893 +SYSTEMZ_INS_LEXBRA = 894 +SYSTEMZ_INS_LEXR = 895 +SYSTEMZ_INS_LEY = 896 +SYSTEMZ_INS_LFAS = 897 +SYSTEMZ_INS_LFH = 898 +SYSTEMZ_INS_LFHAT = 899 +SYSTEMZ_INS_LFPC = 900 +SYSTEMZ_INS_LG = 901 +SYSTEMZ_INS_LGAT = 902 +SYSTEMZ_INS_LGB = 903 +SYSTEMZ_INS_LGBR = 904 +SYSTEMZ_INS_LGDR = 905 +SYSTEMZ_INS_LGF = 906 +SYSTEMZ_INS_LGFI = 907 +SYSTEMZ_INS_LGFR = 908 +SYSTEMZ_INS_LGFRL = 909 +SYSTEMZ_INS_LGG = 910 +SYSTEMZ_INS_LGH = 911 +SYSTEMZ_INS_LGHI = 912 +SYSTEMZ_INS_LGHR = 913 +SYSTEMZ_INS_LGHRL = 914 +SYSTEMZ_INS_LGR = 915 +SYSTEMZ_INS_LGRL = 916 +SYSTEMZ_INS_LGSC = 917 +SYSTEMZ_INS_LH = 918 +SYSTEMZ_INS_LHH = 919 +SYSTEMZ_INS_LHI = 920 +SYSTEMZ_INS_LHR = 921 +SYSTEMZ_INS_LHRL = 922 +SYSTEMZ_INS_LHY = 923 +SYSTEMZ_INS_LLC = 924 +SYSTEMZ_INS_LLCH = 925 +SYSTEMZ_INS_LLCR = 926 +SYSTEMZ_INS_LLGC = 927 +SYSTEMZ_INS_LLGCR = 928 +SYSTEMZ_INS_LLGF = 929 +SYSTEMZ_INS_LLGFAT = 930 +SYSTEMZ_INS_LLGFR = 931 +SYSTEMZ_INS_LLGFRL = 932 +SYSTEMZ_INS_LLGFSG = 933 +SYSTEMZ_INS_LLGH = 934 +SYSTEMZ_INS_LLGHR = 935 +SYSTEMZ_INS_LLGHRL = 936 +SYSTEMZ_INS_LLGT = 937 +SYSTEMZ_INS_LLGTAT = 938 +SYSTEMZ_INS_LLGTR = 939 +SYSTEMZ_INS_LLH = 940 +SYSTEMZ_INS_LLHH = 941 +SYSTEMZ_INS_LLHR = 942 +SYSTEMZ_INS_LLHRL = 943 +SYSTEMZ_INS_LLIHF = 944 +SYSTEMZ_INS_LLIHH = 945 +SYSTEMZ_INS_LLIHL = 946 +SYSTEMZ_INS_LLILF = 947 +SYSTEMZ_INS_LLILH = 948 +SYSTEMZ_INS_LLILL = 949 +SYSTEMZ_INS_LLZRGF = 950 +SYSTEMZ_INS_LM = 951 +SYSTEMZ_INS_LMD = 952 +SYSTEMZ_INS_LMG = 953 +SYSTEMZ_INS_LMH = 954 +SYSTEMZ_INS_LMY = 955 +SYSTEMZ_INS_LNDBR = 956 +SYSTEMZ_INS_LNDFR = 957 +SYSTEMZ_INS_LNDR = 958 +SYSTEMZ_INS_LNEBR = 959 +SYSTEMZ_INS_LNER = 960 +SYSTEMZ_INS_LNGFR = 961 +SYSTEMZ_INS_LNGR = 962 +SYSTEMZ_INS_LNR = 963 +SYSTEMZ_INS_LNXBR = 964 +SYSTEMZ_INS_LNXR = 965 +SYSTEMZ_INS_LOC = 966 +SYSTEMZ_INS_LOCE = 967 +SYSTEMZ_INS_LOCH = 968 +SYSTEMZ_INS_LOCHE = 969 +SYSTEMZ_INS_LOCL = 970 +SYSTEMZ_INS_LOCLE = 971 +SYSTEMZ_INS_LOCLH = 972 +SYSTEMZ_INS_LOCM = 973 +SYSTEMZ_INS_LOCNE = 974 +SYSTEMZ_INS_LOCNH = 975 +SYSTEMZ_INS_LOCNHE = 976 +SYSTEMZ_INS_LOCNL = 977 +SYSTEMZ_INS_LOCNLE = 978 +SYSTEMZ_INS_LOCNLH = 979 +SYSTEMZ_INS_LOCNM = 980 +SYSTEMZ_INS_LOCNO = 981 +SYSTEMZ_INS_LOCNP = 982 +SYSTEMZ_INS_LOCNZ = 983 +SYSTEMZ_INS_LOCO = 984 +SYSTEMZ_INS_LOCP = 985 +SYSTEMZ_INS_LOCZ = 986 +SYSTEMZ_INS_LOCFH = 987 +SYSTEMZ_INS_LOCFHE = 988 +SYSTEMZ_INS_LOCFHH = 989 +SYSTEMZ_INS_LOCFHHE = 990 +SYSTEMZ_INS_LOCFHL = 991 +SYSTEMZ_INS_LOCFHLE = 992 +SYSTEMZ_INS_LOCFHLH = 993 +SYSTEMZ_INS_LOCFHM = 994 +SYSTEMZ_INS_LOCFHNE = 995 +SYSTEMZ_INS_LOCFHNH = 996 +SYSTEMZ_INS_LOCFHNHE = 997 +SYSTEMZ_INS_LOCFHNL = 998 +SYSTEMZ_INS_LOCFHNLE = 999 +SYSTEMZ_INS_LOCFHNLH = 1000 +SYSTEMZ_INS_LOCFHNM = 1001 +SYSTEMZ_INS_LOCFHNO = 1002 +SYSTEMZ_INS_LOCFHNP = 1003 +SYSTEMZ_INS_LOCFHNZ = 1004 +SYSTEMZ_INS_LOCFHO = 1005 +SYSTEMZ_INS_LOCFHP = 1006 +SYSTEMZ_INS_LOCFHZ = 1007 +SYSTEMZ_INS_LOCFHR = 1008 +SYSTEMZ_INS_LOCFHRE = 1009 +SYSTEMZ_INS_LOCFHRH = 1010 +SYSTEMZ_INS_LOCFHRHE = 1011 +SYSTEMZ_INS_LOCFHRL = 1012 +SYSTEMZ_INS_LOCFHRLE = 1013 +SYSTEMZ_INS_LOCFHRLH = 1014 +SYSTEMZ_INS_LOCFHRM = 1015 +SYSTEMZ_INS_LOCFHRNE = 1016 +SYSTEMZ_INS_LOCFHRNH = 1017 +SYSTEMZ_INS_LOCFHRNHE = 1018 +SYSTEMZ_INS_LOCFHRNL = 1019 +SYSTEMZ_INS_LOCFHRNLE = 1020 +SYSTEMZ_INS_LOCFHRNLH = 1021 +SYSTEMZ_INS_LOCFHRNM = 1022 +SYSTEMZ_INS_LOCFHRNO = 1023 +SYSTEMZ_INS_LOCFHRNP = 1024 +SYSTEMZ_INS_LOCFHRNZ = 1025 +SYSTEMZ_INS_LOCFHRO = 1026 +SYSTEMZ_INS_LOCFHRP = 1027 +SYSTEMZ_INS_LOCFHRZ = 1028 +SYSTEMZ_INS_LOCG = 1029 +SYSTEMZ_INS_LOCGE = 1030 +SYSTEMZ_INS_LOCGH = 1031 +SYSTEMZ_INS_LOCGHE = 1032 +SYSTEMZ_INS_LOCGL = 1033 +SYSTEMZ_INS_LOCGLE = 1034 +SYSTEMZ_INS_LOCGLH = 1035 +SYSTEMZ_INS_LOCGM = 1036 +SYSTEMZ_INS_LOCGNE = 1037 +SYSTEMZ_INS_LOCGNH = 1038 +SYSTEMZ_INS_LOCGNHE = 1039 +SYSTEMZ_INS_LOCGNL = 1040 +SYSTEMZ_INS_LOCGNLE = 1041 +SYSTEMZ_INS_LOCGNLH = 1042 +SYSTEMZ_INS_LOCGNM = 1043 +SYSTEMZ_INS_LOCGNO = 1044 +SYSTEMZ_INS_LOCGNP = 1045 +SYSTEMZ_INS_LOCGNZ = 1046 +SYSTEMZ_INS_LOCGO = 1047 +SYSTEMZ_INS_LOCGP = 1048 +SYSTEMZ_INS_LOCGZ = 1049 +SYSTEMZ_INS_LOCGHI = 1050 +SYSTEMZ_INS_LOCGHIE = 1051 +SYSTEMZ_INS_LOCGHIH = 1052 +SYSTEMZ_INS_LOCGHIHE = 1053 +SYSTEMZ_INS_LOCGHIL = 1054 +SYSTEMZ_INS_LOCGHILE = 1055 +SYSTEMZ_INS_LOCGHILH = 1056 +SYSTEMZ_INS_LOCGHIM = 1057 +SYSTEMZ_INS_LOCGHINE = 1058 +SYSTEMZ_INS_LOCGHINH = 1059 +SYSTEMZ_INS_LOCGHINHE = 1060 +SYSTEMZ_INS_LOCGHINL = 1061 +SYSTEMZ_INS_LOCGHINLE = 1062 +SYSTEMZ_INS_LOCGHINLH = 1063 +SYSTEMZ_INS_LOCGHINM = 1064 +SYSTEMZ_INS_LOCGHINO = 1065 +SYSTEMZ_INS_LOCGHINP = 1066 +SYSTEMZ_INS_LOCGHINZ = 1067 +SYSTEMZ_INS_LOCGHIO = 1068 +SYSTEMZ_INS_LOCGHIP = 1069 +SYSTEMZ_INS_LOCGHIZ = 1070 +SYSTEMZ_INS_LOCGR = 1071 +SYSTEMZ_INS_LOCGRE = 1072 +SYSTEMZ_INS_LOCGRH = 1073 +SYSTEMZ_INS_LOCGRHE = 1074 +SYSTEMZ_INS_LOCGRL = 1075 +SYSTEMZ_INS_LOCGRLE = 1076 +SYSTEMZ_INS_LOCGRLH = 1077 +SYSTEMZ_INS_LOCGRM = 1078 +SYSTEMZ_INS_LOCGRNE = 1079 +SYSTEMZ_INS_LOCGRNH = 1080 +SYSTEMZ_INS_LOCGRNHE = 1081 +SYSTEMZ_INS_LOCGRNL = 1082 +SYSTEMZ_INS_LOCGRNLE = 1083 +SYSTEMZ_INS_LOCGRNLH = 1084 +SYSTEMZ_INS_LOCGRNM = 1085 +SYSTEMZ_INS_LOCGRNO = 1086 +SYSTEMZ_INS_LOCGRNP = 1087 +SYSTEMZ_INS_LOCGRNZ = 1088 +SYSTEMZ_INS_LOCGRO = 1089 +SYSTEMZ_INS_LOCGRP = 1090 +SYSTEMZ_INS_LOCGRZ = 1091 +SYSTEMZ_INS_LOCHHI = 1092 +SYSTEMZ_INS_LOCHHIE = 1093 +SYSTEMZ_INS_LOCHHIH = 1094 +SYSTEMZ_INS_LOCHHIHE = 1095 +SYSTEMZ_INS_LOCHHIL = 1096 +SYSTEMZ_INS_LOCHHILE = 1097 +SYSTEMZ_INS_LOCHHILH = 1098 +SYSTEMZ_INS_LOCHHIM = 1099 +SYSTEMZ_INS_LOCHHINE = 1100 +SYSTEMZ_INS_LOCHHINH = 1101 +SYSTEMZ_INS_LOCHHINHE = 1102 +SYSTEMZ_INS_LOCHHINL = 1103 +SYSTEMZ_INS_LOCHHINLE = 1104 +SYSTEMZ_INS_LOCHHINLH = 1105 +SYSTEMZ_INS_LOCHHINM = 1106 +SYSTEMZ_INS_LOCHHINO = 1107 +SYSTEMZ_INS_LOCHHINP = 1108 +SYSTEMZ_INS_LOCHHINZ = 1109 +SYSTEMZ_INS_LOCHHIO = 1110 +SYSTEMZ_INS_LOCHHIP = 1111 +SYSTEMZ_INS_LOCHHIZ = 1112 +SYSTEMZ_INS_LOCHI = 1113 +SYSTEMZ_INS_LOCHIE = 1114 +SYSTEMZ_INS_LOCHIH = 1115 +SYSTEMZ_INS_LOCHIHE = 1116 +SYSTEMZ_INS_LOCHIL = 1117 +SYSTEMZ_INS_LOCHILE = 1118 +SYSTEMZ_INS_LOCHILH = 1119 +SYSTEMZ_INS_LOCHIM = 1120 +SYSTEMZ_INS_LOCHINE = 1121 +SYSTEMZ_INS_LOCHINH = 1122 +SYSTEMZ_INS_LOCHINHE = 1123 +SYSTEMZ_INS_LOCHINL = 1124 +SYSTEMZ_INS_LOCHINLE = 1125 +SYSTEMZ_INS_LOCHINLH = 1126 +SYSTEMZ_INS_LOCHINM = 1127 +SYSTEMZ_INS_LOCHINO = 1128 +SYSTEMZ_INS_LOCHINP = 1129 +SYSTEMZ_INS_LOCHINZ = 1130 +SYSTEMZ_INS_LOCHIO = 1131 +SYSTEMZ_INS_LOCHIP = 1132 +SYSTEMZ_INS_LOCHIZ = 1133 +SYSTEMZ_INS_LOCR = 1134 +SYSTEMZ_INS_LOCRE = 1135 +SYSTEMZ_INS_LOCRH = 1136 +SYSTEMZ_INS_LOCRHE = 1137 +SYSTEMZ_INS_LOCRL = 1138 +SYSTEMZ_INS_LOCRLE = 1139 +SYSTEMZ_INS_LOCRLH = 1140 +SYSTEMZ_INS_LOCRM = 1141 +SYSTEMZ_INS_LOCRNE = 1142 +SYSTEMZ_INS_LOCRNH = 1143 +SYSTEMZ_INS_LOCRNHE = 1144 +SYSTEMZ_INS_LOCRNL = 1145 +SYSTEMZ_INS_LOCRNLE = 1146 +SYSTEMZ_INS_LOCRNLH = 1147 +SYSTEMZ_INS_LOCRNM = 1148 +SYSTEMZ_INS_LOCRNO = 1149 +SYSTEMZ_INS_LOCRNP = 1150 +SYSTEMZ_INS_LOCRNZ = 1151 +SYSTEMZ_INS_LOCRO = 1152 +SYSTEMZ_INS_LOCRP = 1153 +SYSTEMZ_INS_LOCRZ = 1154 +SYSTEMZ_INS_LPCTL = 1155 +SYSTEMZ_INS_LPD = 1156 +SYSTEMZ_INS_LPDBR = 1157 +SYSTEMZ_INS_LPDFR = 1158 +SYSTEMZ_INS_LPDG = 1159 +SYSTEMZ_INS_LPDR = 1160 +SYSTEMZ_INS_LPEBR = 1161 +SYSTEMZ_INS_LPER = 1162 +SYSTEMZ_INS_LPGFR = 1163 +SYSTEMZ_INS_LPGR = 1164 +SYSTEMZ_INS_LPP = 1165 +SYSTEMZ_INS_LPQ = 1166 +SYSTEMZ_INS_LPR = 1167 +SYSTEMZ_INS_LPSW = 1168 +SYSTEMZ_INS_LPSWE = 1169 +SYSTEMZ_INS_LPSWEY = 1170 +SYSTEMZ_INS_LPTEA = 1171 +SYSTEMZ_INS_LPXBR = 1172 +SYSTEMZ_INS_LPXR = 1173 +SYSTEMZ_INS_LR = 1174 +SYSTEMZ_INS_LRA = 1175 +SYSTEMZ_INS_LRAG = 1176 +SYSTEMZ_INS_LRAY = 1177 +SYSTEMZ_INS_LRDR = 1178 +SYSTEMZ_INS_LRER = 1179 +SYSTEMZ_INS_LRL = 1180 +SYSTEMZ_INS_LRV = 1181 +SYSTEMZ_INS_LRVG = 1182 +SYSTEMZ_INS_LRVGR = 1183 +SYSTEMZ_INS_LRVH = 1184 +SYSTEMZ_INS_LRVR = 1185 +SYSTEMZ_INS_LSCTL = 1186 +SYSTEMZ_INS_LT = 1187 +SYSTEMZ_INS_LTDBR = 1188 +SYSTEMZ_INS_LTDR = 1189 +SYSTEMZ_INS_LTDTR = 1190 +SYSTEMZ_INS_LTEBR = 1191 +SYSTEMZ_INS_LTER = 1192 +SYSTEMZ_INS_LTG = 1193 +SYSTEMZ_INS_LTGF = 1194 +SYSTEMZ_INS_LTGFR = 1195 +SYSTEMZ_INS_LTGR = 1196 +SYSTEMZ_INS_LTR = 1197 +SYSTEMZ_INS_LTXBR = 1198 +SYSTEMZ_INS_LTXR = 1199 +SYSTEMZ_INS_LTXTR = 1200 +SYSTEMZ_INS_LURA = 1201 +SYSTEMZ_INS_LURAG = 1202 +SYSTEMZ_INS_LXD = 1203 +SYSTEMZ_INS_LXDB = 1204 +SYSTEMZ_INS_LXDBR = 1205 +SYSTEMZ_INS_LXDR = 1206 +SYSTEMZ_INS_LXDTR = 1207 +SYSTEMZ_INS_LXE = 1208 +SYSTEMZ_INS_LXEB = 1209 +SYSTEMZ_INS_LXEBR = 1210 +SYSTEMZ_INS_LXER = 1211 +SYSTEMZ_INS_LXR = 1212 +SYSTEMZ_INS_LY = 1213 +SYSTEMZ_INS_LZDR = 1214 +SYSTEMZ_INS_LZER = 1215 +SYSTEMZ_INS_LZRF = 1216 +SYSTEMZ_INS_LZRG = 1217 +SYSTEMZ_INS_LZXR = 1218 +SYSTEMZ_INS_M = 1219 +SYSTEMZ_INS_MAD = 1220 +SYSTEMZ_INS_MADB = 1221 +SYSTEMZ_INS_MADBR = 1222 +SYSTEMZ_INS_MADR = 1223 +SYSTEMZ_INS_MAE = 1224 +SYSTEMZ_INS_MAEB = 1225 +SYSTEMZ_INS_MAEBR = 1226 +SYSTEMZ_INS_MAER = 1227 +SYSTEMZ_INS_MAY = 1228 +SYSTEMZ_INS_MAYH = 1229 +SYSTEMZ_INS_MAYHR = 1230 +SYSTEMZ_INS_MAYL = 1231 +SYSTEMZ_INS_MAYLR = 1232 +SYSTEMZ_INS_MAYR = 1233 +SYSTEMZ_INS_MC = 1234 +SYSTEMZ_INS_MD = 1235 +SYSTEMZ_INS_MDB = 1236 +SYSTEMZ_INS_MDBR = 1237 +SYSTEMZ_INS_MDE = 1238 +SYSTEMZ_INS_MDEB = 1239 +SYSTEMZ_INS_MDEBR = 1240 +SYSTEMZ_INS_MDER = 1241 +SYSTEMZ_INS_MDR = 1242 +SYSTEMZ_INS_MDTR = 1243 +SYSTEMZ_INS_MDTRA = 1244 +SYSTEMZ_INS_ME = 1245 +SYSTEMZ_INS_MEE = 1246 +SYSTEMZ_INS_MEEB = 1247 +SYSTEMZ_INS_MEEBR = 1248 +SYSTEMZ_INS_MEER = 1249 +SYSTEMZ_INS_MER = 1250 +SYSTEMZ_INS_MFY = 1251 +SYSTEMZ_INS_MG = 1252 +SYSTEMZ_INS_MGH = 1253 +SYSTEMZ_INS_MGHI = 1254 +SYSTEMZ_INS_MGRK = 1255 +SYSTEMZ_INS_MH = 1256 +SYSTEMZ_INS_MHI = 1257 +SYSTEMZ_INS_MHY = 1258 +SYSTEMZ_INS_ML = 1259 +SYSTEMZ_INS_MLG = 1260 +SYSTEMZ_INS_MLGR = 1261 +SYSTEMZ_INS_MLR = 1262 +SYSTEMZ_INS_MP = 1263 +SYSTEMZ_INS_MR = 1264 +SYSTEMZ_INS_MS = 1265 +SYSTEMZ_INS_MSC = 1266 +SYSTEMZ_INS_MSCH = 1267 +SYSTEMZ_INS_MSD = 1268 +SYSTEMZ_INS_MSDB = 1269 +SYSTEMZ_INS_MSDBR = 1270 +SYSTEMZ_INS_MSDR = 1271 +SYSTEMZ_INS_MSE = 1272 +SYSTEMZ_INS_MSEB = 1273 +SYSTEMZ_INS_MSEBR = 1274 +SYSTEMZ_INS_MSER = 1275 +SYSTEMZ_INS_MSFI = 1276 +SYSTEMZ_INS_MSG = 1277 +SYSTEMZ_INS_MSGC = 1278 +SYSTEMZ_INS_MSGF = 1279 +SYSTEMZ_INS_MSGFI = 1280 +SYSTEMZ_INS_MSGFR = 1281 +SYSTEMZ_INS_MSGR = 1282 +SYSTEMZ_INS_MSGRKC = 1283 +SYSTEMZ_INS_MSR = 1284 +SYSTEMZ_INS_MSRKC = 1285 +SYSTEMZ_INS_MSTA = 1286 +SYSTEMZ_INS_MSY = 1287 +SYSTEMZ_INS_MVC = 1288 +SYSTEMZ_INS_MVCDK = 1289 +SYSTEMZ_INS_MVCIN = 1290 +SYSTEMZ_INS_MVCK = 1291 +SYSTEMZ_INS_MVCL = 1292 +SYSTEMZ_INS_MVCLE = 1293 +SYSTEMZ_INS_MVCLU = 1294 +SYSTEMZ_INS_MVCOS = 1295 +SYSTEMZ_INS_MVCP = 1296 +SYSTEMZ_INS_MVCRL = 1297 +SYSTEMZ_INS_MVCS = 1298 +SYSTEMZ_INS_MVCSK = 1299 +SYSTEMZ_INS_MVGHI = 1300 +SYSTEMZ_INS_MVHHI = 1301 +SYSTEMZ_INS_MVHI = 1302 +SYSTEMZ_INS_MVI = 1303 +SYSTEMZ_INS_MVIY = 1304 +SYSTEMZ_INS_MVN = 1305 +SYSTEMZ_INS_MVO = 1306 +SYSTEMZ_INS_MVPG = 1307 +SYSTEMZ_INS_MVST = 1308 +SYSTEMZ_INS_MVZ = 1309 +SYSTEMZ_INS_MXBR = 1310 +SYSTEMZ_INS_MXD = 1311 +SYSTEMZ_INS_MXDB = 1312 +SYSTEMZ_INS_MXDBR = 1313 +SYSTEMZ_INS_MXDR = 1314 +SYSTEMZ_INS_MXR = 1315 +SYSTEMZ_INS_MXTR = 1316 +SYSTEMZ_INS_MXTRA = 1317 +SYSTEMZ_INS_MY = 1318 +SYSTEMZ_INS_MYH = 1319 +SYSTEMZ_INS_MYHR = 1320 +SYSTEMZ_INS_MYL = 1321 +SYSTEMZ_INS_MYLR = 1322 +SYSTEMZ_INS_MYR = 1323 +SYSTEMZ_INS_N = 1324 +SYSTEMZ_INS_NC = 1325 +SYSTEMZ_INS_NCGRK = 1326 +SYSTEMZ_INS_NCRK = 1327 +SYSTEMZ_INS_NG = 1328 +SYSTEMZ_INS_NGR = 1329 +SYSTEMZ_INS_NGRK = 1330 +SYSTEMZ_INS_NI = 1331 +SYSTEMZ_INS_NIAI = 1332 +SYSTEMZ_INS_NIHF = 1333 +SYSTEMZ_INS_NIHH = 1334 +SYSTEMZ_INS_NIHL = 1335 +SYSTEMZ_INS_NILF = 1336 +SYSTEMZ_INS_NILH = 1337 +SYSTEMZ_INS_NILL = 1338 +SYSTEMZ_INS_NIY = 1339 +SYSTEMZ_INS_NNGRK = 1340 +SYSTEMZ_INS_NNPA = 1341 +SYSTEMZ_INS_NNRK = 1342 +SYSTEMZ_INS_NOGRK = 1343 +SYSTEMZ_INS_NOP = 1344 +SYSTEMZ_INS_NORK = 1345 +SYSTEMZ_INS_NR = 1346 +SYSTEMZ_INS_NRK = 1347 +SYSTEMZ_INS_NTSTG = 1348 +SYSTEMZ_INS_NXGRK = 1349 +SYSTEMZ_INS_NXRK = 1350 +SYSTEMZ_INS_NY = 1351 +SYSTEMZ_INS_O = 1352 +SYSTEMZ_INS_OC = 1353 +SYSTEMZ_INS_OCGRK = 1354 +SYSTEMZ_INS_OCRK = 1355 +SYSTEMZ_INS_OG = 1356 +SYSTEMZ_INS_OGR = 1357 +SYSTEMZ_INS_OGRK = 1358 +SYSTEMZ_INS_OI = 1359 +SYSTEMZ_INS_OIHF = 1360 +SYSTEMZ_INS_OIHH = 1361 +SYSTEMZ_INS_OIHL = 1362 +SYSTEMZ_INS_OILF = 1363 +SYSTEMZ_INS_OILH = 1364 +SYSTEMZ_INS_OILL = 1365 +SYSTEMZ_INS_OIY = 1366 +SYSTEMZ_INS_OR = 1367 +SYSTEMZ_INS_ORK = 1368 +SYSTEMZ_INS_OY = 1369 +SYSTEMZ_INS_PACK = 1370 +SYSTEMZ_INS_PALB = 1371 +SYSTEMZ_INS_PC = 1372 +SYSTEMZ_INS_PCC = 1373 +SYSTEMZ_INS_PCKMO = 1374 +SYSTEMZ_INS_PFD = 1375 +SYSTEMZ_INS_PFDRL = 1376 +SYSTEMZ_INS_PFMF = 1377 +SYSTEMZ_INS_PFPO = 1378 +SYSTEMZ_INS_PGIN = 1379 +SYSTEMZ_INS_PGOUT = 1380 +SYSTEMZ_INS_PKA = 1381 +SYSTEMZ_INS_PKU = 1382 +SYSTEMZ_INS_PLO = 1383 +SYSTEMZ_INS_POPCNT = 1384 +SYSTEMZ_INS_PPA = 1385 +SYSTEMZ_INS_PPNO = 1386 +SYSTEMZ_INS_PR = 1387 +SYSTEMZ_INS_PRNO = 1388 +SYSTEMZ_INS_PT = 1389 +SYSTEMZ_INS_PTF = 1390 +SYSTEMZ_INS_PTFF = 1391 +SYSTEMZ_INS_PTI = 1392 +SYSTEMZ_INS_PTLB = 1393 +SYSTEMZ_INS_QADTR = 1394 +SYSTEMZ_INS_QAXTR = 1395 +SYSTEMZ_INS_QCTRI = 1396 +SYSTEMZ_INS_QPACI = 1397 +SYSTEMZ_INS_QSI = 1398 +SYSTEMZ_INS_RCHP = 1399 +SYSTEMZ_INS_RDP = 1400 +SYSTEMZ_INS_RISBG = 1401 +SYSTEMZ_INS_RISBGN = 1402 +SYSTEMZ_INS_RISBHG = 1403 +SYSTEMZ_INS_RISBLG = 1404 +SYSTEMZ_INS_RLL = 1405 +SYSTEMZ_INS_RLLG = 1406 +SYSTEMZ_INS_RNSBG = 1407 +SYSTEMZ_INS_ROSBG = 1408 +SYSTEMZ_INS_RP = 1409 +SYSTEMZ_INS_RRBE = 1410 +SYSTEMZ_INS_RRBM = 1411 +SYSTEMZ_INS_RRDTR = 1412 +SYSTEMZ_INS_RRXTR = 1413 +SYSTEMZ_INS_RSCH = 1414 +SYSTEMZ_INS_RXSBG = 1415 +SYSTEMZ_INS_S = 1416 +SYSTEMZ_INS_SAC = 1417 +SYSTEMZ_INS_SACF = 1418 +SYSTEMZ_INS_SAL = 1419 +SYSTEMZ_INS_SAM24 = 1420 +SYSTEMZ_INS_SAM31 = 1421 +SYSTEMZ_INS_SAM64 = 1422 +SYSTEMZ_INS_SAR = 1423 +SYSTEMZ_INS_SCCTR = 1424 +SYSTEMZ_INS_SCHM = 1425 +SYSTEMZ_INS_SCK = 1426 +SYSTEMZ_INS_SCKC = 1427 +SYSTEMZ_INS_SCKPF = 1428 +SYSTEMZ_INS_SD = 1429 +SYSTEMZ_INS_SDB = 1430 +SYSTEMZ_INS_SDBR = 1431 +SYSTEMZ_INS_SDR = 1432 +SYSTEMZ_INS_SDTR = 1433 +SYSTEMZ_INS_SDTRA = 1434 +SYSTEMZ_INS_SE = 1435 +SYSTEMZ_INS_SEB = 1436 +SYSTEMZ_INS_SEBR = 1437 +SYSTEMZ_INS_SELFHR = 1438 +SYSTEMZ_INS_SELFHRE = 1439 +SYSTEMZ_INS_SELFHRH = 1440 +SYSTEMZ_INS_SELFHRHE = 1441 +SYSTEMZ_INS_SELFHRL = 1442 +SYSTEMZ_INS_SELFHRLE = 1443 +SYSTEMZ_INS_SELFHRLH = 1444 +SYSTEMZ_INS_SELFHRM = 1445 +SYSTEMZ_INS_SELFHRNE = 1446 +SYSTEMZ_INS_SELFHRNH = 1447 +SYSTEMZ_INS_SELFHRNHE = 1448 +SYSTEMZ_INS_SELFHRNL = 1449 +SYSTEMZ_INS_SELFHRNLE = 1450 +SYSTEMZ_INS_SELFHRNLH = 1451 +SYSTEMZ_INS_SELFHRNM = 1452 +SYSTEMZ_INS_SELFHRNO = 1453 +SYSTEMZ_INS_SELFHRNP = 1454 +SYSTEMZ_INS_SELFHRNZ = 1455 +SYSTEMZ_INS_SELFHRO = 1456 +SYSTEMZ_INS_SELFHRP = 1457 +SYSTEMZ_INS_SELFHRZ = 1458 +SYSTEMZ_INS_SELGR = 1459 +SYSTEMZ_INS_SELGRE = 1460 +SYSTEMZ_INS_SELGRH = 1461 +SYSTEMZ_INS_SELGRHE = 1462 +SYSTEMZ_INS_SELGRL = 1463 +SYSTEMZ_INS_SELGRLE = 1464 +SYSTEMZ_INS_SELGRLH = 1465 +SYSTEMZ_INS_SELGRM = 1466 +SYSTEMZ_INS_SELGRNE = 1467 +SYSTEMZ_INS_SELGRNH = 1468 +SYSTEMZ_INS_SELGRNHE = 1469 +SYSTEMZ_INS_SELGRNL = 1470 +SYSTEMZ_INS_SELGRNLE = 1471 +SYSTEMZ_INS_SELGRNLH = 1472 +SYSTEMZ_INS_SELGRNM = 1473 +SYSTEMZ_INS_SELGRNO = 1474 +SYSTEMZ_INS_SELGRNP = 1475 +SYSTEMZ_INS_SELGRNZ = 1476 +SYSTEMZ_INS_SELGRO = 1477 +SYSTEMZ_INS_SELGRP = 1478 +SYSTEMZ_INS_SELGRZ = 1479 +SYSTEMZ_INS_SELR = 1480 +SYSTEMZ_INS_SELRE = 1481 +SYSTEMZ_INS_SELRH = 1482 +SYSTEMZ_INS_SELRHE = 1483 +SYSTEMZ_INS_SELRL = 1484 +SYSTEMZ_INS_SELRLE = 1485 +SYSTEMZ_INS_SELRLH = 1486 +SYSTEMZ_INS_SELRM = 1487 +SYSTEMZ_INS_SELRNE = 1488 +SYSTEMZ_INS_SELRNH = 1489 +SYSTEMZ_INS_SELRNHE = 1490 +SYSTEMZ_INS_SELRNL = 1491 +SYSTEMZ_INS_SELRNLE = 1492 +SYSTEMZ_INS_SELRNLH = 1493 +SYSTEMZ_INS_SELRNM = 1494 +SYSTEMZ_INS_SELRNO = 1495 +SYSTEMZ_INS_SELRNP = 1496 +SYSTEMZ_INS_SELRNZ = 1497 +SYSTEMZ_INS_SELRO = 1498 +SYSTEMZ_INS_SELRP = 1499 +SYSTEMZ_INS_SELRZ = 1500 +SYSTEMZ_INS_SER = 1501 +SYSTEMZ_INS_SFASR = 1502 +SYSTEMZ_INS_SFPC = 1503 +SYSTEMZ_INS_SG = 1504 +SYSTEMZ_INS_SGF = 1505 +SYSTEMZ_INS_SGFR = 1506 +SYSTEMZ_INS_SGH = 1507 +SYSTEMZ_INS_SGR = 1508 +SYSTEMZ_INS_SGRK = 1509 +SYSTEMZ_INS_SH = 1510 +SYSTEMZ_INS_SHHHR = 1511 +SYSTEMZ_INS_SHHLR = 1512 +SYSTEMZ_INS_SHY = 1513 +SYSTEMZ_INS_SIE = 1514 +SYSTEMZ_INS_SIGA = 1515 +SYSTEMZ_INS_SIGP = 1516 +SYSTEMZ_INS_SL = 1517 +SYSTEMZ_INS_SLA = 1518 +SYSTEMZ_INS_SLAG = 1519 +SYSTEMZ_INS_SLAK = 1520 +SYSTEMZ_INS_SLB = 1521 +SYSTEMZ_INS_SLBG = 1522 +SYSTEMZ_INS_SLBGR = 1523 +SYSTEMZ_INS_SLBR = 1524 +SYSTEMZ_INS_SLDA = 1525 +SYSTEMZ_INS_SLDL = 1526 +SYSTEMZ_INS_SLDT = 1527 +SYSTEMZ_INS_SLFI = 1528 +SYSTEMZ_INS_SLG = 1529 +SYSTEMZ_INS_SLGF = 1530 +SYSTEMZ_INS_SLGFI = 1531 +SYSTEMZ_INS_SLGFR = 1532 +SYSTEMZ_INS_SLGR = 1533 +SYSTEMZ_INS_SLGRK = 1534 +SYSTEMZ_INS_SLHHHR = 1535 +SYSTEMZ_INS_SLHHLR = 1536 +SYSTEMZ_INS_SLL = 1537 +SYSTEMZ_INS_SLLG = 1538 +SYSTEMZ_INS_SLLK = 1539 +SYSTEMZ_INS_SLR = 1540 +SYSTEMZ_INS_SLRK = 1541 +SYSTEMZ_INS_SLXT = 1542 +SYSTEMZ_INS_SLY = 1543 +SYSTEMZ_INS_SORTL = 1544 +SYSTEMZ_INS_SP = 1545 +SYSTEMZ_INS_SPCTR = 1546 +SYSTEMZ_INS_SPKA = 1547 +SYSTEMZ_INS_SPM = 1548 +SYSTEMZ_INS_SPT = 1549 +SYSTEMZ_INS_SPX = 1550 +SYSTEMZ_INS_SQD = 1551 +SYSTEMZ_INS_SQDB = 1552 +SYSTEMZ_INS_SQDBR = 1553 +SYSTEMZ_INS_SQDR = 1554 +SYSTEMZ_INS_SQE = 1555 +SYSTEMZ_INS_SQEB = 1556 +SYSTEMZ_INS_SQEBR = 1557 +SYSTEMZ_INS_SQER = 1558 +SYSTEMZ_INS_SQXBR = 1559 +SYSTEMZ_INS_SQXR = 1560 +SYSTEMZ_INS_SR = 1561 +SYSTEMZ_INS_SRA = 1562 +SYSTEMZ_INS_SRAG = 1563 +SYSTEMZ_INS_SRAK = 1564 +SYSTEMZ_INS_SRDA = 1565 +SYSTEMZ_INS_SRDL = 1566 +SYSTEMZ_INS_SRDT = 1567 +SYSTEMZ_INS_SRK = 1568 +SYSTEMZ_INS_SRL = 1569 +SYSTEMZ_INS_SRLG = 1570 +SYSTEMZ_INS_SRLK = 1571 +SYSTEMZ_INS_SRNM = 1572 +SYSTEMZ_INS_SRNMB = 1573 +SYSTEMZ_INS_SRNMT = 1574 +SYSTEMZ_INS_SRP = 1575 +SYSTEMZ_INS_SRST = 1576 +SYSTEMZ_INS_SRSTU = 1577 +SYSTEMZ_INS_SRXT = 1578 +SYSTEMZ_INS_SSAIR = 1579 +SYSTEMZ_INS_SSAR = 1580 +SYSTEMZ_INS_SSCH = 1581 +SYSTEMZ_INS_SSKE = 1582 +SYSTEMZ_INS_SSM = 1583 +SYSTEMZ_INS_ST = 1584 +SYSTEMZ_INS_STAM = 1585 +SYSTEMZ_INS_STAMY = 1586 +SYSTEMZ_INS_STAP = 1587 +SYSTEMZ_INS_STBEAR = 1588 +SYSTEMZ_INS_STC = 1589 +SYSTEMZ_INS_STCH = 1590 +SYSTEMZ_INS_STCK = 1591 +SYSTEMZ_INS_STCKC = 1592 +SYSTEMZ_INS_STCKE = 1593 +SYSTEMZ_INS_STCKF = 1594 +SYSTEMZ_INS_STCM = 1595 +SYSTEMZ_INS_STCMH = 1596 +SYSTEMZ_INS_STCMY = 1597 +SYSTEMZ_INS_STCPS = 1598 +SYSTEMZ_INS_STCRW = 1599 +SYSTEMZ_INS_STCTG = 1600 +SYSTEMZ_INS_STCTL = 1601 +SYSTEMZ_INS_STCY = 1602 +SYSTEMZ_INS_STD = 1603 +SYSTEMZ_INS_STDY = 1604 +SYSTEMZ_INS_STE = 1605 +SYSTEMZ_INS_STEY = 1606 +SYSTEMZ_INS_STFH = 1607 +SYSTEMZ_INS_STFL = 1608 +SYSTEMZ_INS_STFLE = 1609 +SYSTEMZ_INS_STFPC = 1610 +SYSTEMZ_INS_STG = 1611 +SYSTEMZ_INS_STGRL = 1612 +SYSTEMZ_INS_STGSC = 1613 +SYSTEMZ_INS_STH = 1614 +SYSTEMZ_INS_STHH = 1615 +SYSTEMZ_INS_STHRL = 1616 +SYSTEMZ_INS_STHY = 1617 +SYSTEMZ_INS_STIDP = 1618 +SYSTEMZ_INS_STM = 1619 +SYSTEMZ_INS_STMG = 1620 +SYSTEMZ_INS_STMH = 1621 +SYSTEMZ_INS_STMY = 1622 +SYSTEMZ_INS_STNSM = 1623 +SYSTEMZ_INS_STOC = 1624 +SYSTEMZ_INS_STOCE = 1625 +SYSTEMZ_INS_STOCH = 1626 +SYSTEMZ_INS_STOCHE = 1627 +SYSTEMZ_INS_STOCL = 1628 +SYSTEMZ_INS_STOCLE = 1629 +SYSTEMZ_INS_STOCLH = 1630 +SYSTEMZ_INS_STOCM = 1631 +SYSTEMZ_INS_STOCNE = 1632 +SYSTEMZ_INS_STOCNH = 1633 +SYSTEMZ_INS_STOCNHE = 1634 +SYSTEMZ_INS_STOCNL = 1635 +SYSTEMZ_INS_STOCNLE = 1636 +SYSTEMZ_INS_STOCNLH = 1637 +SYSTEMZ_INS_STOCNM = 1638 +SYSTEMZ_INS_STOCNO = 1639 +SYSTEMZ_INS_STOCNP = 1640 +SYSTEMZ_INS_STOCNZ = 1641 +SYSTEMZ_INS_STOCO = 1642 +SYSTEMZ_INS_STOCP = 1643 +SYSTEMZ_INS_STOCZ = 1644 +SYSTEMZ_INS_STOCFH = 1645 +SYSTEMZ_INS_STOCFHE = 1646 +SYSTEMZ_INS_STOCFHH = 1647 +SYSTEMZ_INS_STOCFHHE = 1648 +SYSTEMZ_INS_STOCFHL = 1649 +SYSTEMZ_INS_STOCFHLE = 1650 +SYSTEMZ_INS_STOCFHLH = 1651 +SYSTEMZ_INS_STOCFHM = 1652 +SYSTEMZ_INS_STOCFHNE = 1653 +SYSTEMZ_INS_STOCFHNH = 1654 +SYSTEMZ_INS_STOCFHNHE = 1655 +SYSTEMZ_INS_STOCFHNL = 1656 +SYSTEMZ_INS_STOCFHNLE = 1657 +SYSTEMZ_INS_STOCFHNLH = 1658 +SYSTEMZ_INS_STOCFHNM = 1659 +SYSTEMZ_INS_STOCFHNO = 1660 +SYSTEMZ_INS_STOCFHNP = 1661 +SYSTEMZ_INS_STOCFHNZ = 1662 +SYSTEMZ_INS_STOCFHO = 1663 +SYSTEMZ_INS_STOCFHP = 1664 +SYSTEMZ_INS_STOCFHZ = 1665 +SYSTEMZ_INS_STOCG = 1666 +SYSTEMZ_INS_STOCGE = 1667 +SYSTEMZ_INS_STOCGH = 1668 +SYSTEMZ_INS_STOCGHE = 1669 +SYSTEMZ_INS_STOCGL = 1670 +SYSTEMZ_INS_STOCGLE = 1671 +SYSTEMZ_INS_STOCGLH = 1672 +SYSTEMZ_INS_STOCGM = 1673 +SYSTEMZ_INS_STOCGNE = 1674 +SYSTEMZ_INS_STOCGNH = 1675 +SYSTEMZ_INS_STOCGNHE = 1676 +SYSTEMZ_INS_STOCGNL = 1677 +SYSTEMZ_INS_STOCGNLE = 1678 +SYSTEMZ_INS_STOCGNLH = 1679 +SYSTEMZ_INS_STOCGNM = 1680 +SYSTEMZ_INS_STOCGNO = 1681 +SYSTEMZ_INS_STOCGNP = 1682 +SYSTEMZ_INS_STOCGNZ = 1683 +SYSTEMZ_INS_STOCGO = 1684 +SYSTEMZ_INS_STOCGP = 1685 +SYSTEMZ_INS_STOCGZ = 1686 +SYSTEMZ_INS_STOSM = 1687 +SYSTEMZ_INS_STPQ = 1688 +SYSTEMZ_INS_STPT = 1689 +SYSTEMZ_INS_STPX = 1690 +SYSTEMZ_INS_STRAG = 1691 +SYSTEMZ_INS_STRL = 1692 +SYSTEMZ_INS_STRV = 1693 +SYSTEMZ_INS_STRVG = 1694 +SYSTEMZ_INS_STRVH = 1695 +SYSTEMZ_INS_STSCH = 1696 +SYSTEMZ_INS_STSI = 1697 +SYSTEMZ_INS_STURA = 1698 +SYSTEMZ_INS_STURG = 1699 +SYSTEMZ_INS_STY = 1700 +SYSTEMZ_INS_SU = 1701 +SYSTEMZ_INS_SUR = 1702 +SYSTEMZ_INS_SVC = 1703 +SYSTEMZ_INS_SW = 1704 +SYSTEMZ_INS_SWR = 1705 +SYSTEMZ_INS_SXBR = 1706 +SYSTEMZ_INS_SXR = 1707 +SYSTEMZ_INS_SXTR = 1708 +SYSTEMZ_INS_SXTRA = 1709 +SYSTEMZ_INS_SY = 1710 +SYSTEMZ_INS_TABORT = 1711 +SYSTEMZ_INS_TAM = 1712 +SYSTEMZ_INS_TAR = 1713 +SYSTEMZ_INS_TB = 1714 +SYSTEMZ_INS_TBDR = 1715 +SYSTEMZ_INS_TBEDR = 1716 +SYSTEMZ_INS_TBEGIN = 1717 +SYSTEMZ_INS_TBEGINC = 1718 +SYSTEMZ_INS_TCDB = 1719 +SYSTEMZ_INS_TCEB = 1720 +SYSTEMZ_INS_TCXB = 1721 +SYSTEMZ_INS_TDCDT = 1722 +SYSTEMZ_INS_TDCET = 1723 +SYSTEMZ_INS_TDCXT = 1724 +SYSTEMZ_INS_TDGDT = 1725 +SYSTEMZ_INS_TDGET = 1726 +SYSTEMZ_INS_TDGXT = 1727 +SYSTEMZ_INS_TEND = 1728 +SYSTEMZ_INS_THDER = 1729 +SYSTEMZ_INS_THDR = 1730 +SYSTEMZ_INS_TM = 1731 +SYSTEMZ_INS_TMHH = 1732 +SYSTEMZ_INS_TMHL = 1733 +SYSTEMZ_INS_TMLH = 1734 +SYSTEMZ_INS_TMLL = 1735 +SYSTEMZ_INS_TMY = 1736 +SYSTEMZ_INS_TP = 1737 +SYSTEMZ_INS_TPI = 1738 +SYSTEMZ_INS_TPROT = 1739 +SYSTEMZ_INS_TR = 1740 +SYSTEMZ_INS_TRACE = 1741 +SYSTEMZ_INS_TRACG = 1742 +SYSTEMZ_INS_TRAP2 = 1743 +SYSTEMZ_INS_TRAP4 = 1744 +SYSTEMZ_INS_TRE = 1745 +SYSTEMZ_INS_TROO = 1746 +SYSTEMZ_INS_TROT = 1747 +SYSTEMZ_INS_TRT = 1748 +SYSTEMZ_INS_TRTE = 1749 +SYSTEMZ_INS_TRTO = 1750 +SYSTEMZ_INS_TRTR = 1751 +SYSTEMZ_INS_TRTRE = 1752 +SYSTEMZ_INS_TRTT = 1753 +SYSTEMZ_INS_TS = 1754 +SYSTEMZ_INS_TSCH = 1755 +SYSTEMZ_INS_UNPK = 1756 +SYSTEMZ_INS_UNPKA = 1757 +SYSTEMZ_INS_UNPKU = 1758 +SYSTEMZ_INS_UPT = 1759 +SYSTEMZ_INS_VA = 1760 +SYSTEMZ_INS_VAB = 1761 +SYSTEMZ_INS_VAC = 1762 +SYSTEMZ_INS_VACC = 1763 +SYSTEMZ_INS_VACCB = 1764 +SYSTEMZ_INS_VACCC = 1765 +SYSTEMZ_INS_VACCCQ = 1766 +SYSTEMZ_INS_VACCF = 1767 +SYSTEMZ_INS_VACCG = 1768 +SYSTEMZ_INS_VACCH = 1769 +SYSTEMZ_INS_VACCQ = 1770 +SYSTEMZ_INS_VACQ = 1771 +SYSTEMZ_INS_VAF = 1772 +SYSTEMZ_INS_VAG = 1773 +SYSTEMZ_INS_VAH = 1774 +SYSTEMZ_INS_VAP = 1775 +SYSTEMZ_INS_VAQ = 1776 +SYSTEMZ_INS_VAVG = 1777 +SYSTEMZ_INS_VAVGB = 1778 +SYSTEMZ_INS_VAVGF = 1779 +SYSTEMZ_INS_VAVGG = 1780 +SYSTEMZ_INS_VAVGH = 1781 +SYSTEMZ_INS_VAVGL = 1782 +SYSTEMZ_INS_VAVGLB = 1783 +SYSTEMZ_INS_VAVGLF = 1784 +SYSTEMZ_INS_VAVGLG = 1785 +SYSTEMZ_INS_VAVGLH = 1786 +SYSTEMZ_INS_VBPERM = 1787 +SYSTEMZ_INS_VCDG = 1788 +SYSTEMZ_INS_VCDGB = 1789 +SYSTEMZ_INS_VCDLG = 1790 +SYSTEMZ_INS_VCDLGB = 1791 +SYSTEMZ_INS_VCEFB = 1792 +SYSTEMZ_INS_VCELFB = 1793 +SYSTEMZ_INS_VCEQ = 1794 +SYSTEMZ_INS_VCEQB = 1795 +SYSTEMZ_INS_VCEQBS = 1796 +SYSTEMZ_INS_VCEQF = 1797 +SYSTEMZ_INS_VCEQFS = 1798 +SYSTEMZ_INS_VCEQG = 1799 +SYSTEMZ_INS_VCEQGS = 1800 +SYSTEMZ_INS_VCEQH = 1801 +SYSTEMZ_INS_VCEQHS = 1802 +SYSTEMZ_INS_VCFEB = 1803 +SYSTEMZ_INS_VCFN = 1804 +SYSTEMZ_INS_VCFPL = 1805 +SYSTEMZ_INS_VCFPS = 1806 +SYSTEMZ_INS_VCGD = 1807 +SYSTEMZ_INS_VCGDB = 1808 +SYSTEMZ_INS_VCH = 1809 +SYSTEMZ_INS_VCHB = 1810 +SYSTEMZ_INS_VCHBS = 1811 +SYSTEMZ_INS_VCHF = 1812 +SYSTEMZ_INS_VCHFS = 1813 +SYSTEMZ_INS_VCHG = 1814 +SYSTEMZ_INS_VCHGS = 1815 +SYSTEMZ_INS_VCHH = 1816 +SYSTEMZ_INS_VCHHS = 1817 +SYSTEMZ_INS_VCHL = 1818 +SYSTEMZ_INS_VCHLB = 1819 +SYSTEMZ_INS_VCHLBS = 1820 +SYSTEMZ_INS_VCHLF = 1821 +SYSTEMZ_INS_VCHLFS = 1822 +SYSTEMZ_INS_VCHLG = 1823 +SYSTEMZ_INS_VCHLGS = 1824 +SYSTEMZ_INS_VCHLH = 1825 +SYSTEMZ_INS_VCHLHS = 1826 +SYSTEMZ_INS_VCKSM = 1827 +SYSTEMZ_INS_VCLFEB = 1828 +SYSTEMZ_INS_VCLFNH = 1829 +SYSTEMZ_INS_VCLFNL = 1830 +SYSTEMZ_INS_VCLFP = 1831 +SYSTEMZ_INS_VCLGD = 1832 +SYSTEMZ_INS_VCLGDB = 1833 +SYSTEMZ_INS_VCLZ = 1834 +SYSTEMZ_INS_VCLZB = 1835 +SYSTEMZ_INS_VCLZDP = 1836 +SYSTEMZ_INS_VCLZF = 1837 +SYSTEMZ_INS_VCLZG = 1838 +SYSTEMZ_INS_VCLZH = 1839 +SYSTEMZ_INS_VCNF = 1840 +SYSTEMZ_INS_VCP = 1841 +SYSTEMZ_INS_VCRNF = 1842 +SYSTEMZ_INS_VCSFP = 1843 +SYSTEMZ_INS_VCSPH = 1844 +SYSTEMZ_INS_VCTZ = 1845 +SYSTEMZ_INS_VCTZB = 1846 +SYSTEMZ_INS_VCTZF = 1847 +SYSTEMZ_INS_VCTZG = 1848 +SYSTEMZ_INS_VCTZH = 1849 +SYSTEMZ_INS_VCVB = 1850 +SYSTEMZ_INS_VCVBG = 1851 +SYSTEMZ_INS_VCVD = 1852 +SYSTEMZ_INS_VCVDG = 1853 +SYSTEMZ_INS_VDP = 1854 +SYSTEMZ_INS_VEC = 1855 +SYSTEMZ_INS_VECB = 1856 +SYSTEMZ_INS_VECF = 1857 +SYSTEMZ_INS_VECG = 1858 +SYSTEMZ_INS_VECH = 1859 +SYSTEMZ_INS_VECL = 1860 +SYSTEMZ_INS_VECLB = 1861 +SYSTEMZ_INS_VECLF = 1862 +SYSTEMZ_INS_VECLG = 1863 +SYSTEMZ_INS_VECLH = 1864 +SYSTEMZ_INS_VERIM = 1865 +SYSTEMZ_INS_VERIMB = 1866 +SYSTEMZ_INS_VERIMF = 1867 +SYSTEMZ_INS_VERIMG = 1868 +SYSTEMZ_INS_VERIMH = 1869 +SYSTEMZ_INS_VERLL = 1870 +SYSTEMZ_INS_VERLLB = 1871 +SYSTEMZ_INS_VERLLF = 1872 +SYSTEMZ_INS_VERLLG = 1873 +SYSTEMZ_INS_VERLLH = 1874 +SYSTEMZ_INS_VERLLV = 1875 +SYSTEMZ_INS_VERLLVB = 1876 +SYSTEMZ_INS_VERLLVF = 1877 +SYSTEMZ_INS_VERLLVG = 1878 +SYSTEMZ_INS_VERLLVH = 1879 +SYSTEMZ_INS_VESL = 1880 +SYSTEMZ_INS_VESLB = 1881 +SYSTEMZ_INS_VESLF = 1882 +SYSTEMZ_INS_VESLG = 1883 +SYSTEMZ_INS_VESLH = 1884 +SYSTEMZ_INS_VESLV = 1885 +SYSTEMZ_INS_VESLVB = 1886 +SYSTEMZ_INS_VESLVF = 1887 +SYSTEMZ_INS_VESLVG = 1888 +SYSTEMZ_INS_VESLVH = 1889 +SYSTEMZ_INS_VESRA = 1890 +SYSTEMZ_INS_VESRAB = 1891 +SYSTEMZ_INS_VESRAF = 1892 +SYSTEMZ_INS_VESRAG = 1893 +SYSTEMZ_INS_VESRAH = 1894 +SYSTEMZ_INS_VESRAV = 1895 +SYSTEMZ_INS_VESRAVB = 1896 +SYSTEMZ_INS_VESRAVF = 1897 +SYSTEMZ_INS_VESRAVG = 1898 +SYSTEMZ_INS_VESRAVH = 1899 +SYSTEMZ_INS_VESRL = 1900 +SYSTEMZ_INS_VESRLB = 1901 +SYSTEMZ_INS_VESRLF = 1902 +SYSTEMZ_INS_VESRLG = 1903 +SYSTEMZ_INS_VESRLH = 1904 +SYSTEMZ_INS_VESRLV = 1905 +SYSTEMZ_INS_VESRLVB = 1906 +SYSTEMZ_INS_VESRLVF = 1907 +SYSTEMZ_INS_VESRLVG = 1908 +SYSTEMZ_INS_VESRLVH = 1909 +SYSTEMZ_INS_VFA = 1910 +SYSTEMZ_INS_VFADB = 1911 +SYSTEMZ_INS_VFAE = 1912 +SYSTEMZ_INS_VFAEB = 1913 +SYSTEMZ_INS_VFAEBS = 1914 +SYSTEMZ_INS_VFAEF = 1915 +SYSTEMZ_INS_VFAEFS = 1916 +SYSTEMZ_INS_VFAEH = 1917 +SYSTEMZ_INS_VFAEHS = 1918 +SYSTEMZ_INS_VFAEZB = 1919 +SYSTEMZ_INS_VFAEZBS = 1920 +SYSTEMZ_INS_VFAEZF = 1921 +SYSTEMZ_INS_VFAEZFS = 1922 +SYSTEMZ_INS_VFAEZH = 1923 +SYSTEMZ_INS_VFAEZHS = 1924 +SYSTEMZ_INS_VFASB = 1925 +SYSTEMZ_INS_VFCE = 1926 +SYSTEMZ_INS_VFCEDB = 1927 +SYSTEMZ_INS_VFCEDBS = 1928 +SYSTEMZ_INS_VFCESB = 1929 +SYSTEMZ_INS_VFCESBS = 1930 +SYSTEMZ_INS_VFCH = 1931 +SYSTEMZ_INS_VFCHDB = 1932 +SYSTEMZ_INS_VFCHDBS = 1933 +SYSTEMZ_INS_VFCHE = 1934 +SYSTEMZ_INS_VFCHEDB = 1935 +SYSTEMZ_INS_VFCHEDBS = 1936 +SYSTEMZ_INS_VFCHESB = 1937 +SYSTEMZ_INS_VFCHESBS = 1938 +SYSTEMZ_INS_VFCHSB = 1939 +SYSTEMZ_INS_VFCHSBS = 1940 +SYSTEMZ_INS_VFD = 1941 +SYSTEMZ_INS_VFDDB = 1942 +SYSTEMZ_INS_VFDSB = 1943 +SYSTEMZ_INS_VFEE = 1944 +SYSTEMZ_INS_VFEEB = 1945 +SYSTEMZ_INS_VFEEBS = 1946 +SYSTEMZ_INS_VFEEF = 1947 +SYSTEMZ_INS_VFEEFS = 1948 +SYSTEMZ_INS_VFEEH = 1949 +SYSTEMZ_INS_VFEEHS = 1950 +SYSTEMZ_INS_VFEEZB = 1951 +SYSTEMZ_INS_VFEEZBS = 1952 +SYSTEMZ_INS_VFEEZF = 1953 +SYSTEMZ_INS_VFEEZFS = 1954 +SYSTEMZ_INS_VFEEZH = 1955 +SYSTEMZ_INS_VFEEZHS = 1956 +SYSTEMZ_INS_VFENE = 1957 +SYSTEMZ_INS_VFENEB = 1958 +SYSTEMZ_INS_VFENEBS = 1959 +SYSTEMZ_INS_VFENEF = 1960 +SYSTEMZ_INS_VFENEFS = 1961 +SYSTEMZ_INS_VFENEH = 1962 +SYSTEMZ_INS_VFENEHS = 1963 +SYSTEMZ_INS_VFENEZB = 1964 +SYSTEMZ_INS_VFENEZBS = 1965 +SYSTEMZ_INS_VFENEZF = 1966 +SYSTEMZ_INS_VFENEZFS = 1967 +SYSTEMZ_INS_VFENEZH = 1968 +SYSTEMZ_INS_VFENEZHS = 1969 +SYSTEMZ_INS_VFI = 1970 +SYSTEMZ_INS_VFIDB = 1971 +SYSTEMZ_INS_VFISB = 1972 +SYSTEMZ_INS_VFKEDB = 1973 +SYSTEMZ_INS_VFKEDBS = 1974 +SYSTEMZ_INS_VFKESB = 1975 +SYSTEMZ_INS_VFKESBS = 1976 +SYSTEMZ_INS_VFKHDB = 1977 +SYSTEMZ_INS_VFKHDBS = 1978 +SYSTEMZ_INS_VFKHEDB = 1979 +SYSTEMZ_INS_VFKHEDBS = 1980 +SYSTEMZ_INS_VFKHESB = 1981 +SYSTEMZ_INS_VFKHESBS = 1982 +SYSTEMZ_INS_VFKHSB = 1983 +SYSTEMZ_INS_VFKHSBS = 1984 +SYSTEMZ_INS_VFLCDB = 1985 +SYSTEMZ_INS_VFLCSB = 1986 +SYSTEMZ_INS_VFLL = 1987 +SYSTEMZ_INS_VFLLS = 1988 +SYSTEMZ_INS_VFLNDB = 1989 +SYSTEMZ_INS_VFLNSB = 1990 +SYSTEMZ_INS_VFLPDB = 1991 +SYSTEMZ_INS_VFLPSB = 1992 +SYSTEMZ_INS_VFLR = 1993 +SYSTEMZ_INS_VFLRD = 1994 +SYSTEMZ_INS_VFM = 1995 +SYSTEMZ_INS_VFMA = 1996 +SYSTEMZ_INS_VFMADB = 1997 +SYSTEMZ_INS_VFMASB = 1998 +SYSTEMZ_INS_VFMAX = 1999 +SYSTEMZ_INS_VFMAXDB = 2000 +SYSTEMZ_INS_VFMAXSB = 2001 +SYSTEMZ_INS_VFMDB = 2002 +SYSTEMZ_INS_VFMIN = 2003 +SYSTEMZ_INS_VFMINDB = 2004 +SYSTEMZ_INS_VFMINSB = 2005 +SYSTEMZ_INS_VFMS = 2006 +SYSTEMZ_INS_VFMSB = 2007 +SYSTEMZ_INS_VFMSDB = 2008 +SYSTEMZ_INS_VFMSSB = 2009 +SYSTEMZ_INS_VFNMA = 2010 +SYSTEMZ_INS_VFNMADB = 2011 +SYSTEMZ_INS_VFNMASB = 2012 +SYSTEMZ_INS_VFNMS = 2013 +SYSTEMZ_INS_VFNMSDB = 2014 +SYSTEMZ_INS_VFNMSSB = 2015 +SYSTEMZ_INS_VFPSO = 2016 +SYSTEMZ_INS_VFPSODB = 2017 +SYSTEMZ_INS_VFPSOSB = 2018 +SYSTEMZ_INS_VFS = 2019 +SYSTEMZ_INS_VFSDB = 2020 +SYSTEMZ_INS_VFSQ = 2021 +SYSTEMZ_INS_VFSQDB = 2022 +SYSTEMZ_INS_VFSQSB = 2023 +SYSTEMZ_INS_VFSSB = 2024 +SYSTEMZ_INS_VFTCI = 2025 +SYSTEMZ_INS_VFTCIDB = 2026 +SYSTEMZ_INS_VFTCISB = 2027 +SYSTEMZ_INS_VGBM = 2028 +SYSTEMZ_INS_VGEF = 2029 +SYSTEMZ_INS_VGEG = 2030 +SYSTEMZ_INS_VGFM = 2031 +SYSTEMZ_INS_VGFMA = 2032 +SYSTEMZ_INS_VGFMAB = 2033 +SYSTEMZ_INS_VGFMAF = 2034 +SYSTEMZ_INS_VGFMAG = 2035 +SYSTEMZ_INS_VGFMAH = 2036 +SYSTEMZ_INS_VGFMB = 2037 +SYSTEMZ_INS_VGFMF = 2038 +SYSTEMZ_INS_VGFMG = 2039 +SYSTEMZ_INS_VGFMH = 2040 +SYSTEMZ_INS_VGM = 2041 +SYSTEMZ_INS_VGMB = 2042 +SYSTEMZ_INS_VGMF = 2043 +SYSTEMZ_INS_VGMG = 2044 +SYSTEMZ_INS_VGMH = 2045 +SYSTEMZ_INS_VISTR = 2046 +SYSTEMZ_INS_VISTRB = 2047 +SYSTEMZ_INS_VISTRBS = 2048 +SYSTEMZ_INS_VISTRF = 2049 +SYSTEMZ_INS_VISTRFS = 2050 +SYSTEMZ_INS_VISTRH = 2051 +SYSTEMZ_INS_VISTRHS = 2052 +SYSTEMZ_INS_VL = 2053 +SYSTEMZ_INS_VLBB = 2054 +SYSTEMZ_INS_VLBR = 2055 +SYSTEMZ_INS_VLBRF = 2056 +SYSTEMZ_INS_VLBRG = 2057 +SYSTEMZ_INS_VLBRH = 2058 +SYSTEMZ_INS_VLBRQ = 2059 +SYSTEMZ_INS_VLBRREP = 2060 +SYSTEMZ_INS_VLBRREPF = 2061 +SYSTEMZ_INS_VLBRREPG = 2062 +SYSTEMZ_INS_VLBRREPH = 2063 +SYSTEMZ_INS_VLC = 2064 +SYSTEMZ_INS_VLCB = 2065 +SYSTEMZ_INS_VLCF = 2066 +SYSTEMZ_INS_VLCG = 2067 +SYSTEMZ_INS_VLCH = 2068 +SYSTEMZ_INS_VLDE = 2069 +SYSTEMZ_INS_VLDEB = 2070 +SYSTEMZ_INS_VLEB = 2071 +SYSTEMZ_INS_VLEBRF = 2072 +SYSTEMZ_INS_VLEBRG = 2073 +SYSTEMZ_INS_VLEBRH = 2074 +SYSTEMZ_INS_VLED = 2075 +SYSTEMZ_INS_VLEDB = 2076 +SYSTEMZ_INS_VLEF = 2077 +SYSTEMZ_INS_VLEG = 2078 +SYSTEMZ_INS_VLEH = 2079 +SYSTEMZ_INS_VLEIB = 2080 +SYSTEMZ_INS_VLEIF = 2081 +SYSTEMZ_INS_VLEIG = 2082 +SYSTEMZ_INS_VLEIH = 2083 +SYSTEMZ_INS_VLER = 2084 +SYSTEMZ_INS_VLERF = 2085 +SYSTEMZ_INS_VLERG = 2086 +SYSTEMZ_INS_VLERH = 2087 +SYSTEMZ_INS_VLGV = 2088 +SYSTEMZ_INS_VLGVB = 2089 +SYSTEMZ_INS_VLGVF = 2090 +SYSTEMZ_INS_VLGVG = 2091 +SYSTEMZ_INS_VLGVH = 2092 +SYSTEMZ_INS_VLIP = 2093 +SYSTEMZ_INS_VLL = 2094 +SYSTEMZ_INS_VLLEBRZ = 2095 +SYSTEMZ_INS_VLLEBRZE = 2096 +SYSTEMZ_INS_VLLEBRZF = 2097 +SYSTEMZ_INS_VLLEBRZG = 2098 +SYSTEMZ_INS_VLLEBRZH = 2099 +SYSTEMZ_INS_VLLEZ = 2100 +SYSTEMZ_INS_VLLEZB = 2101 +SYSTEMZ_INS_VLLEZF = 2102 +SYSTEMZ_INS_VLLEZG = 2103 +SYSTEMZ_INS_VLLEZH = 2104 +SYSTEMZ_INS_VLLEZLF = 2105 +SYSTEMZ_INS_VLM = 2106 +SYSTEMZ_INS_VLP = 2107 +SYSTEMZ_INS_VLPB = 2108 +SYSTEMZ_INS_VLPF = 2109 +SYSTEMZ_INS_VLPG = 2110 +SYSTEMZ_INS_VLPH = 2111 +SYSTEMZ_INS_VLR = 2112 +SYSTEMZ_INS_VLREP = 2113 +SYSTEMZ_INS_VLREPB = 2114 +SYSTEMZ_INS_VLREPF = 2115 +SYSTEMZ_INS_VLREPG = 2116 +SYSTEMZ_INS_VLREPH = 2117 +SYSTEMZ_INS_VLRL = 2118 +SYSTEMZ_INS_VLRLR = 2119 +SYSTEMZ_INS_VLVG = 2120 +SYSTEMZ_INS_VLVGB = 2121 +SYSTEMZ_INS_VLVGF = 2122 +SYSTEMZ_INS_VLVGG = 2123 +SYSTEMZ_INS_VLVGH = 2124 +SYSTEMZ_INS_VLVGP = 2125 +SYSTEMZ_INS_VMAE = 2126 +SYSTEMZ_INS_VMAEB = 2127 +SYSTEMZ_INS_VMAEF = 2128 +SYSTEMZ_INS_VMAEH = 2129 +SYSTEMZ_INS_VMAH = 2130 +SYSTEMZ_INS_VMAHB = 2131 +SYSTEMZ_INS_VMAHF = 2132 +SYSTEMZ_INS_VMAHH = 2133 +SYSTEMZ_INS_VMAL = 2134 +SYSTEMZ_INS_VMALB = 2135 +SYSTEMZ_INS_VMALE = 2136 +SYSTEMZ_INS_VMALEB = 2137 +SYSTEMZ_INS_VMALEF = 2138 +SYSTEMZ_INS_VMALEH = 2139 +SYSTEMZ_INS_VMALF = 2140 +SYSTEMZ_INS_VMALH = 2141 +SYSTEMZ_INS_VMALHB = 2142 +SYSTEMZ_INS_VMALHF = 2143 +SYSTEMZ_INS_VMALHH = 2144 +SYSTEMZ_INS_VMALHW = 2145 +SYSTEMZ_INS_VMALO = 2146 +SYSTEMZ_INS_VMALOB = 2147 +SYSTEMZ_INS_VMALOF = 2148 +SYSTEMZ_INS_VMALOH = 2149 +SYSTEMZ_INS_VMAO = 2150 +SYSTEMZ_INS_VMAOB = 2151 +SYSTEMZ_INS_VMAOF = 2152 +SYSTEMZ_INS_VMAOH = 2153 +SYSTEMZ_INS_VME = 2154 +SYSTEMZ_INS_VMEB = 2155 +SYSTEMZ_INS_VMEF = 2156 +SYSTEMZ_INS_VMEH = 2157 +SYSTEMZ_INS_VMH = 2158 +SYSTEMZ_INS_VMHB = 2159 +SYSTEMZ_INS_VMHF = 2160 +SYSTEMZ_INS_VMHH = 2161 +SYSTEMZ_INS_VML = 2162 +SYSTEMZ_INS_VMLB = 2163 +SYSTEMZ_INS_VMLE = 2164 +SYSTEMZ_INS_VMLEB = 2165 +SYSTEMZ_INS_VMLEF = 2166 +SYSTEMZ_INS_VMLEH = 2167 +SYSTEMZ_INS_VMLF = 2168 +SYSTEMZ_INS_VMLH = 2169 +SYSTEMZ_INS_VMLHB = 2170 +SYSTEMZ_INS_VMLHF = 2171 +SYSTEMZ_INS_VMLHH = 2172 +SYSTEMZ_INS_VMLHW = 2173 +SYSTEMZ_INS_VMLO = 2174 +SYSTEMZ_INS_VMLOB = 2175 +SYSTEMZ_INS_VMLOF = 2176 +SYSTEMZ_INS_VMLOH = 2177 +SYSTEMZ_INS_VMN = 2178 +SYSTEMZ_INS_VMNB = 2179 +SYSTEMZ_INS_VMNF = 2180 +SYSTEMZ_INS_VMNG = 2181 +SYSTEMZ_INS_VMNH = 2182 +SYSTEMZ_INS_VMNL = 2183 +SYSTEMZ_INS_VMNLB = 2184 +SYSTEMZ_INS_VMNLF = 2185 +SYSTEMZ_INS_VMNLG = 2186 +SYSTEMZ_INS_VMNLH = 2187 +SYSTEMZ_INS_VMO = 2188 +SYSTEMZ_INS_VMOB = 2189 +SYSTEMZ_INS_VMOF = 2190 +SYSTEMZ_INS_VMOH = 2191 +SYSTEMZ_INS_VMP = 2192 +SYSTEMZ_INS_VMRH = 2193 +SYSTEMZ_INS_VMRHB = 2194 +SYSTEMZ_INS_VMRHF = 2195 +SYSTEMZ_INS_VMRHG = 2196 +SYSTEMZ_INS_VMRHH = 2197 +SYSTEMZ_INS_VMRL = 2198 +SYSTEMZ_INS_VMRLB = 2199 +SYSTEMZ_INS_VMRLF = 2200 +SYSTEMZ_INS_VMRLG = 2201 +SYSTEMZ_INS_VMRLH = 2202 +SYSTEMZ_INS_VMSL = 2203 +SYSTEMZ_INS_VMSLG = 2204 +SYSTEMZ_INS_VMSP = 2205 +SYSTEMZ_INS_VMX = 2206 +SYSTEMZ_INS_VMXB = 2207 +SYSTEMZ_INS_VMXF = 2208 +SYSTEMZ_INS_VMXG = 2209 +SYSTEMZ_INS_VMXH = 2210 +SYSTEMZ_INS_VMXL = 2211 +SYSTEMZ_INS_VMXLB = 2212 +SYSTEMZ_INS_VMXLF = 2213 +SYSTEMZ_INS_VMXLG = 2214 +SYSTEMZ_INS_VMXLH = 2215 +SYSTEMZ_INS_VN = 2216 +SYSTEMZ_INS_VNC = 2217 +SYSTEMZ_INS_VNN = 2218 +SYSTEMZ_INS_VNO = 2219 +SYSTEMZ_INS_VNX = 2220 +SYSTEMZ_INS_VO = 2221 +SYSTEMZ_INS_VOC = 2222 +SYSTEMZ_INS_VONE = 2223 +SYSTEMZ_INS_VPDI = 2224 +SYSTEMZ_INS_VPERM = 2225 +SYSTEMZ_INS_VPK = 2226 +SYSTEMZ_INS_VPKF = 2227 +SYSTEMZ_INS_VPKG = 2228 +SYSTEMZ_INS_VPKH = 2229 +SYSTEMZ_INS_VPKLS = 2230 +SYSTEMZ_INS_VPKLSF = 2231 +SYSTEMZ_INS_VPKLSFS = 2232 +SYSTEMZ_INS_VPKLSG = 2233 +SYSTEMZ_INS_VPKLSGS = 2234 +SYSTEMZ_INS_VPKLSH = 2235 +SYSTEMZ_INS_VPKLSHS = 2236 +SYSTEMZ_INS_VPKS = 2237 +SYSTEMZ_INS_VPKSF = 2238 +SYSTEMZ_INS_VPKSFS = 2239 +SYSTEMZ_INS_VPKSG = 2240 +SYSTEMZ_INS_VPKSGS = 2241 +SYSTEMZ_INS_VPKSH = 2242 +SYSTEMZ_INS_VPKSHS = 2243 +SYSTEMZ_INS_VPKZ = 2244 +SYSTEMZ_INS_VPKZR = 2245 +SYSTEMZ_INS_VPOPCT = 2246 +SYSTEMZ_INS_VPOPCTB = 2247 +SYSTEMZ_INS_VPOPCTF = 2248 +SYSTEMZ_INS_VPOPCTG = 2249 +SYSTEMZ_INS_VPOPCTH = 2250 +SYSTEMZ_INS_VPSOP = 2251 +SYSTEMZ_INS_VREP = 2252 +SYSTEMZ_INS_VREPB = 2253 +SYSTEMZ_INS_VREPF = 2254 +SYSTEMZ_INS_VREPG = 2255 +SYSTEMZ_INS_VREPH = 2256 +SYSTEMZ_INS_VREPI = 2257 +SYSTEMZ_INS_VREPIB = 2258 +SYSTEMZ_INS_VREPIF = 2259 +SYSTEMZ_INS_VREPIG = 2260 +SYSTEMZ_INS_VREPIH = 2261 +SYSTEMZ_INS_VRP = 2262 +SYSTEMZ_INS_VS = 2263 +SYSTEMZ_INS_VSB = 2264 +SYSTEMZ_INS_VSBCBI = 2265 +SYSTEMZ_INS_VSBCBIQ = 2266 +SYSTEMZ_INS_VSBI = 2267 +SYSTEMZ_INS_VSBIQ = 2268 +SYSTEMZ_INS_VSCBI = 2269 +SYSTEMZ_INS_VSCBIB = 2270 +SYSTEMZ_INS_VSCBIF = 2271 +SYSTEMZ_INS_VSCBIG = 2272 +SYSTEMZ_INS_VSCBIH = 2273 +SYSTEMZ_INS_VSCBIQ = 2274 +SYSTEMZ_INS_VSCEF = 2275 +SYSTEMZ_INS_VSCEG = 2276 +SYSTEMZ_INS_VSCHDP = 2277 +SYSTEMZ_INS_VSCHP = 2278 +SYSTEMZ_INS_VSCHSP = 2279 +SYSTEMZ_INS_VSCHXP = 2280 +SYSTEMZ_INS_VSCSHP = 2281 +SYSTEMZ_INS_VSDP = 2282 +SYSTEMZ_INS_VSEG = 2283 +SYSTEMZ_INS_VSEGB = 2284 +SYSTEMZ_INS_VSEGF = 2285 +SYSTEMZ_INS_VSEGH = 2286 +SYSTEMZ_INS_VSEL = 2287 +SYSTEMZ_INS_VSF = 2288 +SYSTEMZ_INS_VSG = 2289 +SYSTEMZ_INS_VSH = 2290 +SYSTEMZ_INS_VSL = 2291 +SYSTEMZ_INS_VSLB = 2292 +SYSTEMZ_INS_VSLD = 2293 +SYSTEMZ_INS_VSLDB = 2294 +SYSTEMZ_INS_VSP = 2295 +SYSTEMZ_INS_VSQ = 2296 +SYSTEMZ_INS_VSRA = 2297 +SYSTEMZ_INS_VSRAB = 2298 +SYSTEMZ_INS_VSRD = 2299 +SYSTEMZ_INS_VSRL = 2300 +SYSTEMZ_INS_VSRLB = 2301 +SYSTEMZ_INS_VSRP = 2302 +SYSTEMZ_INS_VSRPR = 2303 +SYSTEMZ_INS_VST = 2304 +SYSTEMZ_INS_VSTBR = 2305 +SYSTEMZ_INS_VSTBRF = 2306 +SYSTEMZ_INS_VSTBRG = 2307 +SYSTEMZ_INS_VSTBRH = 2308 +SYSTEMZ_INS_VSTBRQ = 2309 +SYSTEMZ_INS_VSTEB = 2310 +SYSTEMZ_INS_VSTEBRF = 2311 +SYSTEMZ_INS_VSTEBRG = 2312 +SYSTEMZ_INS_VSTEBRH = 2313 +SYSTEMZ_INS_VSTEF = 2314 +SYSTEMZ_INS_VSTEG = 2315 +SYSTEMZ_INS_VSTEH = 2316 +SYSTEMZ_INS_VSTER = 2317 +SYSTEMZ_INS_VSTERF = 2318 +SYSTEMZ_INS_VSTERG = 2319 +SYSTEMZ_INS_VSTERH = 2320 +SYSTEMZ_INS_VSTL = 2321 +SYSTEMZ_INS_VSTM = 2322 +SYSTEMZ_INS_VSTRC = 2323 +SYSTEMZ_INS_VSTRCB = 2324 +SYSTEMZ_INS_VSTRCBS = 2325 +SYSTEMZ_INS_VSTRCF = 2326 +SYSTEMZ_INS_VSTRCFS = 2327 +SYSTEMZ_INS_VSTRCH = 2328 +SYSTEMZ_INS_VSTRCHS = 2329 +SYSTEMZ_INS_VSTRCZB = 2330 +SYSTEMZ_INS_VSTRCZBS = 2331 +SYSTEMZ_INS_VSTRCZF = 2332 +SYSTEMZ_INS_VSTRCZFS = 2333 +SYSTEMZ_INS_VSTRCZH = 2334 +SYSTEMZ_INS_VSTRCZHS = 2335 +SYSTEMZ_INS_VSTRL = 2336 +SYSTEMZ_INS_VSTRLR = 2337 +SYSTEMZ_INS_VSTRS = 2338 +SYSTEMZ_INS_VSTRSB = 2339 +SYSTEMZ_INS_VSTRSF = 2340 +SYSTEMZ_INS_VSTRSH = 2341 +SYSTEMZ_INS_VSTRSZB = 2342 +SYSTEMZ_INS_VSTRSZF = 2343 +SYSTEMZ_INS_VSTRSZH = 2344 +SYSTEMZ_INS_VSUM = 2345 +SYSTEMZ_INS_VSUMB = 2346 +SYSTEMZ_INS_VSUMG = 2347 +SYSTEMZ_INS_VSUMGF = 2348 +SYSTEMZ_INS_VSUMGH = 2349 +SYSTEMZ_INS_VSUMH = 2350 +SYSTEMZ_INS_VSUMQ = 2351 +SYSTEMZ_INS_VSUMQF = 2352 +SYSTEMZ_INS_VSUMQG = 2353 +SYSTEMZ_INS_VTM = 2354 +SYSTEMZ_INS_VTP = 2355 +SYSTEMZ_INS_VUPH = 2356 +SYSTEMZ_INS_VUPHB = 2357 +SYSTEMZ_INS_VUPHF = 2358 +SYSTEMZ_INS_VUPHH = 2359 +SYSTEMZ_INS_VUPKZ = 2360 +SYSTEMZ_INS_VUPKZH = 2361 +SYSTEMZ_INS_VUPKZL = 2362 +SYSTEMZ_INS_VUPL = 2363 +SYSTEMZ_INS_VUPLB = 2364 +SYSTEMZ_INS_VUPLF = 2365 +SYSTEMZ_INS_VUPLH = 2366 +SYSTEMZ_INS_VUPLHB = 2367 +SYSTEMZ_INS_VUPLHF = 2368 +SYSTEMZ_INS_VUPLHH = 2369 +SYSTEMZ_INS_VUPLHW = 2370 +SYSTEMZ_INS_VUPLL = 2371 +SYSTEMZ_INS_VUPLLB = 2372 +SYSTEMZ_INS_VUPLLF = 2373 +SYSTEMZ_INS_VUPLLH = 2374 +SYSTEMZ_INS_VX = 2375 +SYSTEMZ_INS_VZERO = 2376 +SYSTEMZ_INS_WCDGB = 2377 +SYSTEMZ_INS_WCDLGB = 2378 +SYSTEMZ_INS_WCEFB = 2379 +SYSTEMZ_INS_WCELFB = 2380 +SYSTEMZ_INS_WCFEB = 2381 +SYSTEMZ_INS_WCGDB = 2382 +SYSTEMZ_INS_WCLFEB = 2383 +SYSTEMZ_INS_WCLGDB = 2384 +SYSTEMZ_INS_WFADB = 2385 +SYSTEMZ_INS_WFASB = 2386 +SYSTEMZ_INS_WFAXB = 2387 +SYSTEMZ_INS_WFC = 2388 +SYSTEMZ_INS_WFCDB = 2389 +SYSTEMZ_INS_WFCEDB = 2390 +SYSTEMZ_INS_WFCEDBS = 2391 +SYSTEMZ_INS_WFCESB = 2392 +SYSTEMZ_INS_WFCESBS = 2393 +SYSTEMZ_INS_WFCEXB = 2394 +SYSTEMZ_INS_WFCEXBS = 2395 +SYSTEMZ_INS_WFCHDB = 2396 +SYSTEMZ_INS_WFCHDBS = 2397 +SYSTEMZ_INS_WFCHEDB = 2398 +SYSTEMZ_INS_WFCHEDBS = 2399 +SYSTEMZ_INS_WFCHESB = 2400 +SYSTEMZ_INS_WFCHESBS = 2401 +SYSTEMZ_INS_WFCHEXB = 2402 +SYSTEMZ_INS_WFCHEXBS = 2403 +SYSTEMZ_INS_WFCHSB = 2404 +SYSTEMZ_INS_WFCHSBS = 2405 +SYSTEMZ_INS_WFCHXB = 2406 +SYSTEMZ_INS_WFCHXBS = 2407 +SYSTEMZ_INS_WFCSB = 2408 +SYSTEMZ_INS_WFCXB = 2409 +SYSTEMZ_INS_WFDDB = 2410 +SYSTEMZ_INS_WFDSB = 2411 +SYSTEMZ_INS_WFDXB = 2412 +SYSTEMZ_INS_WFIDB = 2413 +SYSTEMZ_INS_WFISB = 2414 +SYSTEMZ_INS_WFIXB = 2415 +SYSTEMZ_INS_WFK = 2416 +SYSTEMZ_INS_WFKDB = 2417 +SYSTEMZ_INS_WFKEDB = 2418 +SYSTEMZ_INS_WFKEDBS = 2419 +SYSTEMZ_INS_WFKESB = 2420 +SYSTEMZ_INS_WFKESBS = 2421 +SYSTEMZ_INS_WFKEXB = 2422 +SYSTEMZ_INS_WFKEXBS = 2423 +SYSTEMZ_INS_WFKHDB = 2424 +SYSTEMZ_INS_WFKHDBS = 2425 +SYSTEMZ_INS_WFKHEDB = 2426 +SYSTEMZ_INS_WFKHEDBS = 2427 +SYSTEMZ_INS_WFKHESB = 2428 +SYSTEMZ_INS_WFKHESBS = 2429 +SYSTEMZ_INS_WFKHEXB = 2430 +SYSTEMZ_INS_WFKHEXBS = 2431 +SYSTEMZ_INS_WFKHSB = 2432 +SYSTEMZ_INS_WFKHSBS = 2433 +SYSTEMZ_INS_WFKHXB = 2434 +SYSTEMZ_INS_WFKHXBS = 2435 +SYSTEMZ_INS_WFKSB = 2436 +SYSTEMZ_INS_WFKXB = 2437 +SYSTEMZ_INS_WFLCDB = 2438 +SYSTEMZ_INS_WFLCSB = 2439 +SYSTEMZ_INS_WFLCXB = 2440 +SYSTEMZ_INS_WFLLD = 2441 +SYSTEMZ_INS_WFLLS = 2442 +SYSTEMZ_INS_WFLNDB = 2443 +SYSTEMZ_INS_WFLNSB = 2444 +SYSTEMZ_INS_WFLNXB = 2445 +SYSTEMZ_INS_WFLPDB = 2446 +SYSTEMZ_INS_WFLPSB = 2447 +SYSTEMZ_INS_WFLPXB = 2448 +SYSTEMZ_INS_WFLRD = 2449 +SYSTEMZ_INS_WFLRX = 2450 +SYSTEMZ_INS_WFMADB = 2451 +SYSTEMZ_INS_WFMASB = 2452 +SYSTEMZ_INS_WFMAXB = 2453 +SYSTEMZ_INS_WFMAXDB = 2454 +SYSTEMZ_INS_WFMAXSB = 2455 +SYSTEMZ_INS_WFMAXXB = 2456 +SYSTEMZ_INS_WFMDB = 2457 +SYSTEMZ_INS_WFMINDB = 2458 +SYSTEMZ_INS_WFMINSB = 2459 +SYSTEMZ_INS_WFMINXB = 2460 +SYSTEMZ_INS_WFMSB = 2461 +SYSTEMZ_INS_WFMSDB = 2462 +SYSTEMZ_INS_WFMSSB = 2463 +SYSTEMZ_INS_WFMSXB = 2464 +SYSTEMZ_INS_WFMXB = 2465 +SYSTEMZ_INS_WFNMADB = 2466 +SYSTEMZ_INS_WFNMASB = 2467 +SYSTEMZ_INS_WFNMAXB = 2468 +SYSTEMZ_INS_WFNMSDB = 2469 +SYSTEMZ_INS_WFNMSSB = 2470 +SYSTEMZ_INS_WFNMSXB = 2471 +SYSTEMZ_INS_WFPSODB = 2472 +SYSTEMZ_INS_WFPSOSB = 2473 +SYSTEMZ_INS_WFPSOXB = 2474 +SYSTEMZ_INS_WFSDB = 2475 +SYSTEMZ_INS_WFSQDB = 2476 +SYSTEMZ_INS_WFSQSB = 2477 +SYSTEMZ_INS_WFSQXB = 2478 +SYSTEMZ_INS_WFSSB = 2479 +SYSTEMZ_INS_WFSXB = 2480 +SYSTEMZ_INS_WFTCIDB = 2481 +SYSTEMZ_INS_WFTCISB = 2482 +SYSTEMZ_INS_WFTCIXB = 2483 +SYSTEMZ_INS_WLDEB = 2484 +SYSTEMZ_INS_WLEDB = 2485 +SYSTEMZ_INS_X = 2486 +SYSTEMZ_INS_XC = 2487 +SYSTEMZ_INS_XG = 2488 +SYSTEMZ_INS_XGR = 2489 +SYSTEMZ_INS_XGRK = 2490 +SYSTEMZ_INS_XI = 2491 +SYSTEMZ_INS_XIHF = 2492 +SYSTEMZ_INS_XILF = 2493 +SYSTEMZ_INS_XIY = 2494 +SYSTEMZ_INS_XR = 2495 +SYSTEMZ_INS_XRK = 2496 +SYSTEMZ_INS_XSCH = 2497 +SYSTEMZ_INS_XY = 2498 +SYSTEMZ_INS_ZAP = 2499 +SYSTEMZ_INS_ENDING = 2500 +SYSTEMZ_INS_ALIAS_BEGIN = 2501 +SYSTEMZ_INS_ALIAS_VISTRB = 2502 +SYSTEMZ_INS_ALIAS_VISTR = 2503 +SYSTEMZ_INS_ALIAS_VFEEB = 2504 +SYSTEMZ_INS_ALIAS_VFEE = 2505 +SYSTEMZ_INS_ALIAS_VFAEB = 2506 +SYSTEMZ_INS_ALIAS_VFAEBS = 2507 +SYSTEMZ_INS_ALIAS_VFAE = 2508 +SYSTEMZ_INS_ALIAS_VSTRSB = 2509 +SYSTEMZ_INS_ALIAS_VSTRS = 2510 +SYSTEMZ_INS_ALIAS_VSTRCB = 2511 +SYSTEMZ_INS_ALIAS_VSTRCBS = 2512 +SYSTEMZ_INS_ALIAS_VSTRC = 2513 +SYSTEMZ_INS_ALIAS_VFAEH = 2514 +SYSTEMZ_INS_ALIAS_VFAEHS = 2515 +SYSTEMZ_INS_ALIAS_VFAEF = 2516 +SYSTEMZ_INS_ALIAS_VFAEFS = 2517 +SYSTEMZ_INS_ALIAS_VFAEZB = 2518 +SYSTEMZ_INS_ALIAS_VFAEZBS = 2519 +SYSTEMZ_INS_ALIAS_VFAEZH = 2520 +SYSTEMZ_INS_ALIAS_VFAEZHS = 2521 +SYSTEMZ_INS_ALIAS_VFAEZF = 2522 +SYSTEMZ_INS_ALIAS_VFAEZFS = 2523 +SYSTEMZ_INS_ALIAS_VFEEH = 2524 +SYSTEMZ_INS_ALIAS_VFEEF = 2525 +SYSTEMZ_INS_ALIAS_VFENE = 2526 +SYSTEMZ_INS_ALIAS_VFENEB = 2527 +SYSTEMZ_INS_ALIAS_VFENEH = 2528 +SYSTEMZ_INS_ALIAS_VFENEF = 2529 +SYSTEMZ_INS_ALIAS_VISTRH = 2530 +SYSTEMZ_INS_ALIAS_VISTRF = 2531 +SYSTEMZ_INS_ALIAS_VSTRCH = 2532 +SYSTEMZ_INS_ALIAS_VSTRCHS = 2533 +SYSTEMZ_INS_ALIAS_VSTRCF = 2534 +SYSTEMZ_INS_ALIAS_VSTRCFS = 2535 +SYSTEMZ_INS_ALIAS_VSTRCZB = 2536 +SYSTEMZ_INS_ALIAS_VSTRCZBS = 2537 +SYSTEMZ_INS_ALIAS_VSTRCZH = 2538 +SYSTEMZ_INS_ALIAS_VSTRCZHS = 2539 +SYSTEMZ_INS_ALIAS_VSTRCZF = 2540 +SYSTEMZ_INS_ALIAS_VSTRCZFS = 2541 +SYSTEMZ_INS_ALIAS_VSTRSH = 2542 +SYSTEMZ_INS_ALIAS_VSTRSF = 2543 +SYSTEMZ_INS_ALIAS_END = 2544 + +SYSTEMZ_GRP_INVALID = 0 +SYSTEMZ_GRP_JUMP = 1 +SYSTEMZ_GRP_CALL = 2 +SYSTEMZ_GRP_RET = 3 +SYSTEMZ_GRP_INT = 4 +SYSTEMZ_GRP_IRET = 5 +SYSTEMZ_GRP_PRIVILEGE = 6 +SYSTEMZ_GRP_BRANCH_RELATIVE = 7 +SYSTEMZ_FEATURE_FEATURESOFTFLOAT = 128 +SYSTEMZ_FEATURE_FEATUREBACKCHAIN = 129 +SYSTEMZ_FEATURE_FEATUREDISTINCTOPS = 130 +SYSTEMZ_FEATURE_FEATUREFASTSERIALIZATION = 131 +SYSTEMZ_FEATURE_FEATUREFPEXTENSION = 132 +SYSTEMZ_FEATURE_FEATUREHIGHWORD = 133 +SYSTEMZ_FEATURE_FEATUREINTERLOCKEDACCESS1 = 134 +SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND = 135 +SYSTEMZ_FEATURE_FEATUREPOPULATIONCOUNT = 136 +SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST3 = 137 +SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST4 = 138 +SYSTEMZ_FEATURE_FEATURERESETREFERENCEBITSMULTIPLE = 139 +SYSTEMZ_FEATURE_FEATUREEXECUTIONHINT = 140 +SYSTEMZ_FEATURE_FEATURELOADANDTRAP = 141 +SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS = 142 +SYSTEMZ_FEATURE_FEATUREPROCESSORASSIST = 143 +SYSTEMZ_FEATURE_FEATURETRANSACTIONALEXECUTION = 144 +SYSTEMZ_FEATURE_FEATUREDFPZONEDCONVERSION = 145 +SYSTEMZ_FEATURE_FEATUREENHANCEDDAT2 = 146 +SYSTEMZ_FEATURE_FEATURELOADANDZERORIGHTMOSTBYTE = 147 +SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2 = 148 +SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST5 = 149 +SYSTEMZ_FEATURE_FEATUREDFPPACKEDCONVERSION = 150 +SYSTEMZ_FEATURE_FEATUREVECTOR = 151 +SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2 = 152 +SYSTEMZ_FEATURE_FEATUREGUARDEDSTORAGE = 153 +SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST7 = 154 +SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST8 = 155 +SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1 = 156 +SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL = 157 +SYSTEMZ_FEATURE_FEATUREINSERTREFERENCEBITSMULTIPLE = 158 +SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3 = 159 +SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST9 = 160 +SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2 = 161 +SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT = 162 +SYSTEMZ_FEATURE_FEATUREENHANCEDSORT = 163 +SYSTEMZ_FEATURE_FEATUREDEFLATECONVERSION = 164 +SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT2 = 165 +SYSTEMZ_FEATURE_FEATURENNPASSIST = 166 +SYSTEMZ_FEATURE_FEATUREBEARENHANCEMENT = 167 +SYSTEMZ_FEATURE_FEATURERESETDATPROTECTION = 168 +SYSTEMZ_FEATURE_FEATUREPROCESSORACTIVITYINSTRUMENTATION = 169 +SYSTEMZ_GRP_ENDING = 170 diff --git a/bindings/python/capstone/sysz_const.py b/bindings/python/capstone/sysz_const.py deleted file mode 100644 index ebe3610051..0000000000 --- a/bindings/python/capstone/sysz_const.py +++ /dev/null @@ -1,2524 +0,0 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX -# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sysz_const.py] - -SYSZ_CC_INVALID = 0 -SYSZ_CC_O = 1 -SYSZ_CC_H = 2 -SYSZ_CC_NLE = 3 -SYSZ_CC_L = 4 -SYSZ_CC_NHE = 5 -SYSZ_CC_LH = 6 -SYSZ_CC_NE = 7 -SYSZ_CC_E = 8 -SYSZ_CC_NLH = 9 -SYSZ_CC_HE = 10 -SYSZ_CC_NL = 11 -SYSZ_CC_LE = 12 -SYSZ_CC_NH = 13 -SYSZ_CC_NO = 14 - -SYSZ_OP_INVALID = 0 -SYSZ_OP_REG = 1 -SYSZ_OP_IMM = 2 -SYSZ_OP_MEM = 3 -SYSZ_OP_ACREG = 64 - -SYSZ_REG_INVALID = 0 -SYSZ_REG_0 = 1 -SYSZ_REG_1 = 2 -SYSZ_REG_2 = 3 -SYSZ_REG_3 = 4 -SYSZ_REG_4 = 5 -SYSZ_REG_5 = 6 -SYSZ_REG_6 = 7 -SYSZ_REG_7 = 8 -SYSZ_REG_8 = 9 -SYSZ_REG_9 = 10 -SYSZ_REG_10 = 11 -SYSZ_REG_11 = 12 -SYSZ_REG_12 = 13 -SYSZ_REG_13 = 14 -SYSZ_REG_14 = 15 -SYSZ_REG_15 = 16 -SYSZ_REG_CC = 17 -SYSZ_REG_F0 = 18 -SYSZ_REG_F1 = 19 -SYSZ_REG_F2 = 20 -SYSZ_REG_F3 = 21 -SYSZ_REG_F4 = 22 -SYSZ_REG_F5 = 23 -SYSZ_REG_F6 = 24 -SYSZ_REG_F7 = 25 -SYSZ_REG_F8 = 26 -SYSZ_REG_F9 = 27 -SYSZ_REG_F10 = 28 -SYSZ_REG_F11 = 29 -SYSZ_REG_F12 = 30 -SYSZ_REG_F13 = 31 -SYSZ_REG_F14 = 32 -SYSZ_REG_F15 = 33 -SYSZ_REG_R0L = 34 -SYSZ_REG_A0 = 35 -SYSZ_REG_A1 = 36 -SYSZ_REG_A2 = 37 -SYSZ_REG_A3 = 38 -SYSZ_REG_A4 = 39 -SYSZ_REG_A5 = 40 -SYSZ_REG_A6 = 41 -SYSZ_REG_A7 = 42 -SYSZ_REG_A8 = 43 -SYSZ_REG_A9 = 44 -SYSZ_REG_A10 = 45 -SYSZ_REG_A11 = 46 -SYSZ_REG_A12 = 47 -SYSZ_REG_A13 = 48 -SYSZ_REG_A14 = 49 -SYSZ_REG_A15 = 50 -SYSZ_REG_C0 = 51 -SYSZ_REG_C1 = 52 -SYSZ_REG_C2 = 53 -SYSZ_REG_C3 = 54 -SYSZ_REG_C4 = 55 -SYSZ_REG_C5 = 56 -SYSZ_REG_C6 = 57 -SYSZ_REG_C7 = 58 -SYSZ_REG_C8 = 59 -SYSZ_REG_C9 = 60 -SYSZ_REG_C10 = 61 -SYSZ_REG_C11 = 62 -SYSZ_REG_C12 = 63 -SYSZ_REG_C13 = 64 -SYSZ_REG_C14 = 65 -SYSZ_REG_C15 = 66 -SYSZ_REG_V0 = 67 -SYSZ_REG_V1 = 68 -SYSZ_REG_V2 = 69 -SYSZ_REG_V3 = 70 -SYSZ_REG_V4 = 71 -SYSZ_REG_V5 = 72 -SYSZ_REG_V6 = 73 -SYSZ_REG_V7 = 74 -SYSZ_REG_V8 = 75 -SYSZ_REG_V9 = 76 -SYSZ_REG_V10 = 77 -SYSZ_REG_V11 = 78 -SYSZ_REG_V12 = 79 -SYSZ_REG_V13 = 80 -SYSZ_REG_V14 = 81 -SYSZ_REG_V15 = 82 -SYSZ_REG_V16 = 83 -SYSZ_REG_V17 = 84 -SYSZ_REG_V18 = 85 -SYSZ_REG_V19 = 86 -SYSZ_REG_V20 = 87 -SYSZ_REG_V21 = 88 -SYSZ_REG_V22 = 89 -SYSZ_REG_V23 = 90 -SYSZ_REG_V24 = 91 -SYSZ_REG_V25 = 92 -SYSZ_REG_V26 = 93 -SYSZ_REG_V27 = 94 -SYSZ_REG_V28 = 95 -SYSZ_REG_V29 = 96 -SYSZ_REG_V30 = 97 -SYSZ_REG_V31 = 98 -SYSZ_REG_F16 = 99 -SYSZ_REG_F17 = 100 -SYSZ_REG_F18 = 101 -SYSZ_REG_F19 = 102 -SYSZ_REG_F20 = 103 -SYSZ_REG_F21 = 104 -SYSZ_REG_F22 = 105 -SYSZ_REG_F23 = 106 -SYSZ_REG_F24 = 107 -SYSZ_REG_F25 = 108 -SYSZ_REG_F26 = 109 -SYSZ_REG_F27 = 110 -SYSZ_REG_F28 = 111 -SYSZ_REG_F29 = 112 -SYSZ_REG_F30 = 113 -SYSZ_REG_F31 = 114 -SYSZ_REG_F0Q = 115 -SYSZ_REG_F4Q = 116 -SYSZ_REG_ENDING = 117 - -SYSZ_INS_INVALID = 0 -SYSZ_INS_A = 1 -SYSZ_INS_ADB = 2 -SYSZ_INS_ADBR = 3 -SYSZ_INS_AEB = 4 -SYSZ_INS_AEBR = 5 -SYSZ_INS_AFI = 6 -SYSZ_INS_AG = 7 -SYSZ_INS_AGF = 8 -SYSZ_INS_AGFI = 9 -SYSZ_INS_AGFR = 10 -SYSZ_INS_AGHI = 11 -SYSZ_INS_AGHIK = 12 -SYSZ_INS_AGR = 13 -SYSZ_INS_AGRK = 14 -SYSZ_INS_AGSI = 15 -SYSZ_INS_AH = 16 -SYSZ_INS_AHI = 17 -SYSZ_INS_AHIK = 18 -SYSZ_INS_AHY = 19 -SYSZ_INS_AIH = 20 -SYSZ_INS_AL = 21 -SYSZ_INS_ALC = 22 -SYSZ_INS_ALCG = 23 -SYSZ_INS_ALCGR = 24 -SYSZ_INS_ALCR = 25 -SYSZ_INS_ALFI = 26 -SYSZ_INS_ALG = 27 -SYSZ_INS_ALGF = 28 -SYSZ_INS_ALGFI = 29 -SYSZ_INS_ALGFR = 30 -SYSZ_INS_ALGHSIK = 31 -SYSZ_INS_ALGR = 32 -SYSZ_INS_ALGRK = 33 -SYSZ_INS_ALHSIK = 34 -SYSZ_INS_ALR = 35 -SYSZ_INS_ALRK = 36 -SYSZ_INS_ALY = 37 -SYSZ_INS_AR = 38 -SYSZ_INS_ARK = 39 -SYSZ_INS_ASI = 40 -SYSZ_INS_AXBR = 41 -SYSZ_INS_AY = 42 -SYSZ_INS_BCR = 43 -SYSZ_INS_BRC = 44 -SYSZ_INS_BRCL = 45 -SYSZ_INS_CGIJ = 46 -SYSZ_INS_CGRJ = 47 -SYSZ_INS_CIJ = 48 -SYSZ_INS_CLGIJ = 49 -SYSZ_INS_CLGRJ = 50 -SYSZ_INS_CLIJ = 51 -SYSZ_INS_CLRJ = 52 -SYSZ_INS_CRJ = 53 -SYSZ_INS_BER = 54 -SYSZ_INS_JE = 55 -SYSZ_INS_JGE = 56 -SYSZ_INS_LOCE = 57 -SYSZ_INS_LOCGE = 58 -SYSZ_INS_LOCGRE = 59 -SYSZ_INS_LOCRE = 60 -SYSZ_INS_STOCE = 61 -SYSZ_INS_STOCGE = 62 -SYSZ_INS_BHR = 63 -SYSZ_INS_BHER = 64 -SYSZ_INS_JHE = 65 -SYSZ_INS_JGHE = 66 -SYSZ_INS_LOCHE = 67 -SYSZ_INS_LOCGHE = 68 -SYSZ_INS_LOCGRHE = 69 -SYSZ_INS_LOCRHE = 70 -SYSZ_INS_STOCHE = 71 -SYSZ_INS_STOCGHE = 72 -SYSZ_INS_JH = 73 -SYSZ_INS_JGH = 74 -SYSZ_INS_LOCH = 75 -SYSZ_INS_LOCGH = 76 -SYSZ_INS_LOCGRH = 77 -SYSZ_INS_LOCRH = 78 -SYSZ_INS_STOCH = 79 -SYSZ_INS_STOCGH = 80 -SYSZ_INS_CGIJNLH = 81 -SYSZ_INS_CGRJNLH = 82 -SYSZ_INS_CIJNLH = 83 -SYSZ_INS_CLGIJNLH = 84 -SYSZ_INS_CLGRJNLH = 85 -SYSZ_INS_CLIJNLH = 86 -SYSZ_INS_CLRJNLH = 87 -SYSZ_INS_CRJNLH = 88 -SYSZ_INS_CGIJE = 89 -SYSZ_INS_CGRJE = 90 -SYSZ_INS_CIJE = 91 -SYSZ_INS_CLGIJE = 92 -SYSZ_INS_CLGRJE = 93 -SYSZ_INS_CLIJE = 94 -SYSZ_INS_CLRJE = 95 -SYSZ_INS_CRJE = 96 -SYSZ_INS_CGIJNLE = 97 -SYSZ_INS_CGRJNLE = 98 -SYSZ_INS_CIJNLE = 99 -SYSZ_INS_CLGIJNLE = 100 -SYSZ_INS_CLGRJNLE = 101 -SYSZ_INS_CLIJNLE = 102 -SYSZ_INS_CLRJNLE = 103 -SYSZ_INS_CRJNLE = 104 -SYSZ_INS_CGIJH = 105 -SYSZ_INS_CGRJH = 106 -SYSZ_INS_CIJH = 107 -SYSZ_INS_CLGIJH = 108 -SYSZ_INS_CLGRJH = 109 -SYSZ_INS_CLIJH = 110 -SYSZ_INS_CLRJH = 111 -SYSZ_INS_CRJH = 112 -SYSZ_INS_CGIJNL = 113 -SYSZ_INS_CGRJNL = 114 -SYSZ_INS_CIJNL = 115 -SYSZ_INS_CLGIJNL = 116 -SYSZ_INS_CLGRJNL = 117 -SYSZ_INS_CLIJNL = 118 -SYSZ_INS_CLRJNL = 119 -SYSZ_INS_CRJNL = 120 -SYSZ_INS_CGIJHE = 121 -SYSZ_INS_CGRJHE = 122 -SYSZ_INS_CIJHE = 123 -SYSZ_INS_CLGIJHE = 124 -SYSZ_INS_CLGRJHE = 125 -SYSZ_INS_CLIJHE = 126 -SYSZ_INS_CLRJHE = 127 -SYSZ_INS_CRJHE = 128 -SYSZ_INS_CGIJNHE = 129 -SYSZ_INS_CGRJNHE = 130 -SYSZ_INS_CIJNHE = 131 -SYSZ_INS_CLGIJNHE = 132 -SYSZ_INS_CLGRJNHE = 133 -SYSZ_INS_CLIJNHE = 134 -SYSZ_INS_CLRJNHE = 135 -SYSZ_INS_CRJNHE = 136 -SYSZ_INS_CGIJL = 137 -SYSZ_INS_CGRJL = 138 -SYSZ_INS_CIJL = 139 -SYSZ_INS_CLGIJL = 140 -SYSZ_INS_CLGRJL = 141 -SYSZ_INS_CLIJL = 142 -SYSZ_INS_CLRJL = 143 -SYSZ_INS_CRJL = 144 -SYSZ_INS_CGIJNH = 145 -SYSZ_INS_CGRJNH = 146 -SYSZ_INS_CIJNH = 147 -SYSZ_INS_CLGIJNH = 148 -SYSZ_INS_CLGRJNH = 149 -SYSZ_INS_CLIJNH = 150 -SYSZ_INS_CLRJNH = 151 -SYSZ_INS_CRJNH = 152 -SYSZ_INS_CGIJLE = 153 -SYSZ_INS_CGRJLE = 154 -SYSZ_INS_CIJLE = 155 -SYSZ_INS_CLGIJLE = 156 -SYSZ_INS_CLGRJLE = 157 -SYSZ_INS_CLIJLE = 158 -SYSZ_INS_CLRJLE = 159 -SYSZ_INS_CRJLE = 160 -SYSZ_INS_CGIJNE = 161 -SYSZ_INS_CGRJNE = 162 -SYSZ_INS_CIJNE = 163 -SYSZ_INS_CLGIJNE = 164 -SYSZ_INS_CLGRJNE = 165 -SYSZ_INS_CLIJNE = 166 -SYSZ_INS_CLRJNE = 167 -SYSZ_INS_CRJNE = 168 -SYSZ_INS_CGIJLH = 169 -SYSZ_INS_CGRJLH = 170 -SYSZ_INS_CIJLH = 171 -SYSZ_INS_CLGIJLH = 172 -SYSZ_INS_CLGRJLH = 173 -SYSZ_INS_CLIJLH = 174 -SYSZ_INS_CLRJLH = 175 -SYSZ_INS_CRJLH = 176 -SYSZ_INS_BLR = 177 -SYSZ_INS_BLER = 178 -SYSZ_INS_JLE = 179 -SYSZ_INS_JGLE = 180 -SYSZ_INS_LOCLE = 181 -SYSZ_INS_LOCGLE = 182 -SYSZ_INS_LOCGRLE = 183 -SYSZ_INS_LOCRLE = 184 -SYSZ_INS_STOCLE = 185 -SYSZ_INS_STOCGLE = 186 -SYSZ_INS_BLHR = 187 -SYSZ_INS_JLH = 188 -SYSZ_INS_JGLH = 189 -SYSZ_INS_LOCLH = 190 -SYSZ_INS_LOCGLH = 191 -SYSZ_INS_LOCGRLH = 192 -SYSZ_INS_LOCRLH = 193 -SYSZ_INS_STOCLH = 194 -SYSZ_INS_STOCGLH = 195 -SYSZ_INS_JL = 196 -SYSZ_INS_JGL = 197 -SYSZ_INS_LOCL = 198 -SYSZ_INS_LOCGL = 199 -SYSZ_INS_LOCGRL = 200 -SYSZ_INS_LOCRL = 201 -SYSZ_INS_LOC = 202 -SYSZ_INS_LOCG = 203 -SYSZ_INS_LOCGR = 204 -SYSZ_INS_LOCR = 205 -SYSZ_INS_STOCL = 206 -SYSZ_INS_STOCGL = 207 -SYSZ_INS_BNER = 208 -SYSZ_INS_JNE = 209 -SYSZ_INS_JGNE = 210 -SYSZ_INS_LOCNE = 211 -SYSZ_INS_LOCGNE = 212 -SYSZ_INS_LOCGRNE = 213 -SYSZ_INS_LOCRNE = 214 -SYSZ_INS_STOCNE = 215 -SYSZ_INS_STOCGNE = 216 -SYSZ_INS_BNHR = 217 -SYSZ_INS_BNHER = 218 -SYSZ_INS_JNHE = 219 -SYSZ_INS_JGNHE = 220 -SYSZ_INS_LOCNHE = 221 -SYSZ_INS_LOCGNHE = 222 -SYSZ_INS_LOCGRNHE = 223 -SYSZ_INS_LOCRNHE = 224 -SYSZ_INS_STOCNHE = 225 -SYSZ_INS_STOCGNHE = 226 -SYSZ_INS_JNH = 227 -SYSZ_INS_JGNH = 228 -SYSZ_INS_LOCNH = 229 -SYSZ_INS_LOCGNH = 230 -SYSZ_INS_LOCGRNH = 231 -SYSZ_INS_LOCRNH = 232 -SYSZ_INS_STOCNH = 233 -SYSZ_INS_STOCGNH = 234 -SYSZ_INS_BNLR = 235 -SYSZ_INS_BNLER = 236 -SYSZ_INS_JNLE = 237 -SYSZ_INS_JGNLE = 238 -SYSZ_INS_LOCNLE = 239 -SYSZ_INS_LOCGNLE = 240 -SYSZ_INS_LOCGRNLE = 241 -SYSZ_INS_LOCRNLE = 242 -SYSZ_INS_STOCNLE = 243 -SYSZ_INS_STOCGNLE = 244 -SYSZ_INS_BNLHR = 245 -SYSZ_INS_JNLH = 246 -SYSZ_INS_JGNLH = 247 -SYSZ_INS_LOCNLH = 248 -SYSZ_INS_LOCGNLH = 249 -SYSZ_INS_LOCGRNLH = 250 -SYSZ_INS_LOCRNLH = 251 -SYSZ_INS_STOCNLH = 252 -SYSZ_INS_STOCGNLH = 253 -SYSZ_INS_JNL = 254 -SYSZ_INS_JGNL = 255 -SYSZ_INS_LOCNL = 256 -SYSZ_INS_LOCGNL = 257 -SYSZ_INS_LOCGRNL = 258 -SYSZ_INS_LOCRNL = 259 -SYSZ_INS_STOCNL = 260 -SYSZ_INS_STOCGNL = 261 -SYSZ_INS_BNOR = 262 -SYSZ_INS_JNO = 263 -SYSZ_INS_JGNO = 264 -SYSZ_INS_LOCNO = 265 -SYSZ_INS_LOCGNO = 266 -SYSZ_INS_LOCGRNO = 267 -SYSZ_INS_LOCRNO = 268 -SYSZ_INS_STOCNO = 269 -SYSZ_INS_STOCGNO = 270 -SYSZ_INS_BOR = 271 -SYSZ_INS_JO = 272 -SYSZ_INS_JGO = 273 -SYSZ_INS_LOCO = 274 -SYSZ_INS_LOCGO = 275 -SYSZ_INS_LOCGRO = 276 -SYSZ_INS_LOCRO = 277 -SYSZ_INS_STOCO = 278 -SYSZ_INS_STOCGO = 279 -SYSZ_INS_STOC = 280 -SYSZ_INS_STOCG = 281 -SYSZ_INS_BASR = 282 -SYSZ_INS_BR = 283 -SYSZ_INS_BRAS = 284 -SYSZ_INS_BRASL = 285 -SYSZ_INS_J = 286 -SYSZ_INS_JG = 287 -SYSZ_INS_BRCT = 288 -SYSZ_INS_BRCTG = 289 -SYSZ_INS_C = 290 -SYSZ_INS_CDB = 291 -SYSZ_INS_CDBR = 292 -SYSZ_INS_CDFBR = 293 -SYSZ_INS_CDGBR = 294 -SYSZ_INS_CDLFBR = 295 -SYSZ_INS_CDLGBR = 296 -SYSZ_INS_CEB = 297 -SYSZ_INS_CEBR = 298 -SYSZ_INS_CEFBR = 299 -SYSZ_INS_CEGBR = 300 -SYSZ_INS_CELFBR = 301 -SYSZ_INS_CELGBR = 302 -SYSZ_INS_CFDBR = 303 -SYSZ_INS_CFEBR = 304 -SYSZ_INS_CFI = 305 -SYSZ_INS_CFXBR = 306 -SYSZ_INS_CG = 307 -SYSZ_INS_CGDBR = 308 -SYSZ_INS_CGEBR = 309 -SYSZ_INS_CGF = 310 -SYSZ_INS_CGFI = 311 -SYSZ_INS_CGFR = 312 -SYSZ_INS_CGFRL = 313 -SYSZ_INS_CGH = 314 -SYSZ_INS_CGHI = 315 -SYSZ_INS_CGHRL = 316 -SYSZ_INS_CGHSI = 317 -SYSZ_INS_CGR = 318 -SYSZ_INS_CGRL = 319 -SYSZ_INS_CGXBR = 320 -SYSZ_INS_CH = 321 -SYSZ_INS_CHF = 322 -SYSZ_INS_CHHSI = 323 -SYSZ_INS_CHI = 324 -SYSZ_INS_CHRL = 325 -SYSZ_INS_CHSI = 326 -SYSZ_INS_CHY = 327 -SYSZ_INS_CIH = 328 -SYSZ_INS_CL = 329 -SYSZ_INS_CLC = 330 -SYSZ_INS_CLFDBR = 331 -SYSZ_INS_CLFEBR = 332 -SYSZ_INS_CLFHSI = 333 -SYSZ_INS_CLFI = 334 -SYSZ_INS_CLFXBR = 335 -SYSZ_INS_CLG = 336 -SYSZ_INS_CLGDBR = 337 -SYSZ_INS_CLGEBR = 338 -SYSZ_INS_CLGF = 339 -SYSZ_INS_CLGFI = 340 -SYSZ_INS_CLGFR = 341 -SYSZ_INS_CLGFRL = 342 -SYSZ_INS_CLGHRL = 343 -SYSZ_INS_CLGHSI = 344 -SYSZ_INS_CLGR = 345 -SYSZ_INS_CLGRL = 346 -SYSZ_INS_CLGXBR = 347 -SYSZ_INS_CLHF = 348 -SYSZ_INS_CLHHSI = 349 -SYSZ_INS_CLHRL = 350 -SYSZ_INS_CLI = 351 -SYSZ_INS_CLIH = 352 -SYSZ_INS_CLIY = 353 -SYSZ_INS_CLR = 354 -SYSZ_INS_CLRL = 355 -SYSZ_INS_CLST = 356 -SYSZ_INS_CLY = 357 -SYSZ_INS_CPSDR = 358 -SYSZ_INS_CR = 359 -SYSZ_INS_CRL = 360 -SYSZ_INS_CS = 361 -SYSZ_INS_CSG = 362 -SYSZ_INS_CSY = 363 -SYSZ_INS_CXBR = 364 -SYSZ_INS_CXFBR = 365 -SYSZ_INS_CXGBR = 366 -SYSZ_INS_CXLFBR = 367 -SYSZ_INS_CXLGBR = 368 -SYSZ_INS_CY = 369 -SYSZ_INS_DDB = 370 -SYSZ_INS_DDBR = 371 -SYSZ_INS_DEB = 372 -SYSZ_INS_DEBR = 373 -SYSZ_INS_DL = 374 -SYSZ_INS_DLG = 375 -SYSZ_INS_DLGR = 376 -SYSZ_INS_DLR = 377 -SYSZ_INS_DSG = 378 -SYSZ_INS_DSGF = 379 -SYSZ_INS_DSGFR = 380 -SYSZ_INS_DSGR = 381 -SYSZ_INS_DXBR = 382 -SYSZ_INS_EAR = 383 -SYSZ_INS_FIDBR = 384 -SYSZ_INS_FIDBRA = 385 -SYSZ_INS_FIEBR = 386 -SYSZ_INS_FIEBRA = 387 -SYSZ_INS_FIXBR = 388 -SYSZ_INS_FIXBRA = 389 -SYSZ_INS_FLOGR = 390 -SYSZ_INS_IC = 391 -SYSZ_INS_ICY = 392 -SYSZ_INS_IIHF = 393 -SYSZ_INS_IIHH = 394 -SYSZ_INS_IIHL = 395 -SYSZ_INS_IILF = 396 -SYSZ_INS_IILH = 397 -SYSZ_INS_IILL = 398 -SYSZ_INS_IPM = 399 -SYSZ_INS_L = 400 -SYSZ_INS_LA = 401 -SYSZ_INS_LAA = 402 -SYSZ_INS_LAAG = 403 -SYSZ_INS_LAAL = 404 -SYSZ_INS_LAALG = 405 -SYSZ_INS_LAN = 406 -SYSZ_INS_LANG = 407 -SYSZ_INS_LAO = 408 -SYSZ_INS_LAOG = 409 -SYSZ_INS_LARL = 410 -SYSZ_INS_LAX = 411 -SYSZ_INS_LAXG = 412 -SYSZ_INS_LAY = 413 -SYSZ_INS_LB = 414 -SYSZ_INS_LBH = 415 -SYSZ_INS_LBR = 416 -SYSZ_INS_LCDBR = 417 -SYSZ_INS_LCEBR = 418 -SYSZ_INS_LCGFR = 419 -SYSZ_INS_LCGR = 420 -SYSZ_INS_LCR = 421 -SYSZ_INS_LCXBR = 422 -SYSZ_INS_LD = 423 -SYSZ_INS_LDEB = 424 -SYSZ_INS_LDEBR = 425 -SYSZ_INS_LDGR = 426 -SYSZ_INS_LDR = 427 -SYSZ_INS_LDXBR = 428 -SYSZ_INS_LDXBRA = 429 -SYSZ_INS_LDY = 430 -SYSZ_INS_LE = 431 -SYSZ_INS_LEDBR = 432 -SYSZ_INS_LEDBRA = 433 -SYSZ_INS_LER = 434 -SYSZ_INS_LEXBR = 435 -SYSZ_INS_LEXBRA = 436 -SYSZ_INS_LEY = 437 -SYSZ_INS_LFH = 438 -SYSZ_INS_LG = 439 -SYSZ_INS_LGB = 440 -SYSZ_INS_LGBR = 441 -SYSZ_INS_LGDR = 442 -SYSZ_INS_LGF = 443 -SYSZ_INS_LGFI = 444 -SYSZ_INS_LGFR = 445 -SYSZ_INS_LGFRL = 446 -SYSZ_INS_LGH = 447 -SYSZ_INS_LGHI = 448 -SYSZ_INS_LGHR = 449 -SYSZ_INS_LGHRL = 450 -SYSZ_INS_LGR = 451 -SYSZ_INS_LGRL = 452 -SYSZ_INS_LH = 453 -SYSZ_INS_LHH = 454 -SYSZ_INS_LHI = 455 -SYSZ_INS_LHR = 456 -SYSZ_INS_LHRL = 457 -SYSZ_INS_LHY = 458 -SYSZ_INS_LLC = 459 -SYSZ_INS_LLCH = 460 -SYSZ_INS_LLCR = 461 -SYSZ_INS_LLGC = 462 -SYSZ_INS_LLGCR = 463 -SYSZ_INS_LLGF = 464 -SYSZ_INS_LLGFR = 465 -SYSZ_INS_LLGFRL = 466 -SYSZ_INS_LLGH = 467 -SYSZ_INS_LLGHR = 468 -SYSZ_INS_LLGHRL = 469 -SYSZ_INS_LLH = 470 -SYSZ_INS_LLHH = 471 -SYSZ_INS_LLHR = 472 -SYSZ_INS_LLHRL = 473 -SYSZ_INS_LLIHF = 474 -SYSZ_INS_LLIHH = 475 -SYSZ_INS_LLIHL = 476 -SYSZ_INS_LLILF = 477 -SYSZ_INS_LLILH = 478 -SYSZ_INS_LLILL = 479 -SYSZ_INS_LMG = 480 -SYSZ_INS_LNDBR = 481 -SYSZ_INS_LNEBR = 482 -SYSZ_INS_LNGFR = 483 -SYSZ_INS_LNGR = 484 -SYSZ_INS_LNR = 485 -SYSZ_INS_LNXBR = 486 -SYSZ_INS_LPDBR = 487 -SYSZ_INS_LPEBR = 488 -SYSZ_INS_LPGFR = 489 -SYSZ_INS_LPGR = 490 -SYSZ_INS_LPR = 491 -SYSZ_INS_LPXBR = 492 -SYSZ_INS_LR = 493 -SYSZ_INS_LRL = 494 -SYSZ_INS_LRV = 495 -SYSZ_INS_LRVG = 496 -SYSZ_INS_LRVGR = 497 -SYSZ_INS_LRVR = 498 -SYSZ_INS_LT = 499 -SYSZ_INS_LTDBR = 500 -SYSZ_INS_LTEBR = 501 -SYSZ_INS_LTG = 502 -SYSZ_INS_LTGF = 503 -SYSZ_INS_LTGFR = 504 -SYSZ_INS_LTGR = 505 -SYSZ_INS_LTR = 506 -SYSZ_INS_LTXBR = 507 -SYSZ_INS_LXDB = 508 -SYSZ_INS_LXDBR = 509 -SYSZ_INS_LXEB = 510 -SYSZ_INS_LXEBR = 511 -SYSZ_INS_LXR = 512 -SYSZ_INS_LY = 513 -SYSZ_INS_LZDR = 514 -SYSZ_INS_LZER = 515 -SYSZ_INS_LZXR = 516 -SYSZ_INS_MADB = 517 -SYSZ_INS_MADBR = 518 -SYSZ_INS_MAEB = 519 -SYSZ_INS_MAEBR = 520 -SYSZ_INS_MDB = 521 -SYSZ_INS_MDBR = 522 -SYSZ_INS_MDEB = 523 -SYSZ_INS_MDEBR = 524 -SYSZ_INS_MEEB = 525 -SYSZ_INS_MEEBR = 526 -SYSZ_INS_MGHI = 527 -SYSZ_INS_MH = 528 -SYSZ_INS_MHI = 529 -SYSZ_INS_MHY = 530 -SYSZ_INS_MLG = 531 -SYSZ_INS_MLGR = 532 -SYSZ_INS_MS = 533 -SYSZ_INS_MSDB = 534 -SYSZ_INS_MSDBR = 535 -SYSZ_INS_MSEB = 536 -SYSZ_INS_MSEBR = 537 -SYSZ_INS_MSFI = 538 -SYSZ_INS_MSG = 539 -SYSZ_INS_MSGF = 540 -SYSZ_INS_MSGFI = 541 -SYSZ_INS_MSGFR = 542 -SYSZ_INS_MSGR = 543 -SYSZ_INS_MSR = 544 -SYSZ_INS_MSY = 545 -SYSZ_INS_MVC = 546 -SYSZ_INS_MVGHI = 547 -SYSZ_INS_MVHHI = 548 -SYSZ_INS_MVHI = 549 -SYSZ_INS_MVI = 550 -SYSZ_INS_MVIY = 551 -SYSZ_INS_MVST = 552 -SYSZ_INS_MXBR = 553 -SYSZ_INS_MXDB = 554 -SYSZ_INS_MXDBR = 555 -SYSZ_INS_N = 556 -SYSZ_INS_NC = 557 -SYSZ_INS_NG = 558 -SYSZ_INS_NGR = 559 -SYSZ_INS_NGRK = 560 -SYSZ_INS_NI = 561 -SYSZ_INS_NIHF = 562 -SYSZ_INS_NIHH = 563 -SYSZ_INS_NIHL = 564 -SYSZ_INS_NILF = 565 -SYSZ_INS_NILH = 566 -SYSZ_INS_NILL = 567 -SYSZ_INS_NIY = 568 -SYSZ_INS_NR = 569 -SYSZ_INS_NRK = 570 -SYSZ_INS_NY = 571 -SYSZ_INS_O = 572 -SYSZ_INS_OC = 573 -SYSZ_INS_OG = 574 -SYSZ_INS_OGR = 575 -SYSZ_INS_OGRK = 576 -SYSZ_INS_OI = 577 -SYSZ_INS_OIHF = 578 -SYSZ_INS_OIHH = 579 -SYSZ_INS_OIHL = 580 -SYSZ_INS_OILF = 581 -SYSZ_INS_OILH = 582 -SYSZ_INS_OILL = 583 -SYSZ_INS_OIY = 584 -SYSZ_INS_OR = 585 -SYSZ_INS_ORK = 586 -SYSZ_INS_OY = 587 -SYSZ_INS_PFD = 588 -SYSZ_INS_PFDRL = 589 -SYSZ_INS_RISBG = 590 -SYSZ_INS_RISBHG = 591 -SYSZ_INS_RISBLG = 592 -SYSZ_INS_RLL = 593 -SYSZ_INS_RLLG = 594 -SYSZ_INS_RNSBG = 595 -SYSZ_INS_ROSBG = 596 -SYSZ_INS_RXSBG = 597 -SYSZ_INS_S = 598 -SYSZ_INS_SDB = 599 -SYSZ_INS_SDBR = 600 -SYSZ_INS_SEB = 601 -SYSZ_INS_SEBR = 602 -SYSZ_INS_SG = 603 -SYSZ_INS_SGF = 604 -SYSZ_INS_SGFR = 605 -SYSZ_INS_SGR = 606 -SYSZ_INS_SGRK = 607 -SYSZ_INS_SH = 608 -SYSZ_INS_SHY = 609 -SYSZ_INS_SL = 610 -SYSZ_INS_SLB = 611 -SYSZ_INS_SLBG = 612 -SYSZ_INS_SLBR = 613 -SYSZ_INS_SLFI = 614 -SYSZ_INS_SLG = 615 -SYSZ_INS_SLBGR = 616 -SYSZ_INS_SLGF = 617 -SYSZ_INS_SLGFI = 618 -SYSZ_INS_SLGFR = 619 -SYSZ_INS_SLGR = 620 -SYSZ_INS_SLGRK = 621 -SYSZ_INS_SLL = 622 -SYSZ_INS_SLLG = 623 -SYSZ_INS_SLLK = 624 -SYSZ_INS_SLR = 625 -SYSZ_INS_SLRK = 626 -SYSZ_INS_SLY = 627 -SYSZ_INS_SQDB = 628 -SYSZ_INS_SQDBR = 629 -SYSZ_INS_SQEB = 630 -SYSZ_INS_SQEBR = 631 -SYSZ_INS_SQXBR = 632 -SYSZ_INS_SR = 633 -SYSZ_INS_SRA = 634 -SYSZ_INS_SRAG = 635 -SYSZ_INS_SRAK = 636 -SYSZ_INS_SRK = 637 -SYSZ_INS_SRL = 638 -SYSZ_INS_SRLG = 639 -SYSZ_INS_SRLK = 640 -SYSZ_INS_SRST = 641 -SYSZ_INS_ST = 642 -SYSZ_INS_STC = 643 -SYSZ_INS_STCH = 644 -SYSZ_INS_STCY = 645 -SYSZ_INS_STD = 646 -SYSZ_INS_STDY = 647 -SYSZ_INS_STE = 648 -SYSZ_INS_STEY = 649 -SYSZ_INS_STFH = 650 -SYSZ_INS_STG = 651 -SYSZ_INS_STGRL = 652 -SYSZ_INS_STH = 653 -SYSZ_INS_STHH = 654 -SYSZ_INS_STHRL = 655 -SYSZ_INS_STHY = 656 -SYSZ_INS_STMG = 657 -SYSZ_INS_STRL = 658 -SYSZ_INS_STRV = 659 -SYSZ_INS_STRVG = 660 -SYSZ_INS_STY = 661 -SYSZ_INS_SXBR = 662 -SYSZ_INS_SY = 663 -SYSZ_INS_TM = 664 -SYSZ_INS_TMHH = 665 -SYSZ_INS_TMHL = 666 -SYSZ_INS_TMLH = 667 -SYSZ_INS_TMLL = 668 -SYSZ_INS_TMY = 669 -SYSZ_INS_X = 670 -SYSZ_INS_XC = 671 -SYSZ_INS_XG = 672 -SYSZ_INS_XGR = 673 -SYSZ_INS_XGRK = 674 -SYSZ_INS_XI = 675 -SYSZ_INS_XIHF = 676 -SYSZ_INS_XILF = 677 -SYSZ_INS_XIY = 678 -SYSZ_INS_XR = 679 -SYSZ_INS_XRK = 680 -SYSZ_INS_XY = 681 -SYSZ_INS_AD = 682 -SYSZ_INS_ADR = 683 -SYSZ_INS_ADTR = 684 -SYSZ_INS_ADTRA = 685 -SYSZ_INS_AE = 686 -SYSZ_INS_AER = 687 -SYSZ_INS_AGH = 688 -SYSZ_INS_AHHHR = 689 -SYSZ_INS_AHHLR = 690 -SYSZ_INS_ALGSI = 691 -SYSZ_INS_ALHHHR = 692 -SYSZ_INS_ALHHLR = 693 -SYSZ_INS_ALSI = 694 -SYSZ_INS_ALSIH = 695 -SYSZ_INS_ALSIHN = 696 -SYSZ_INS_AP = 697 -SYSZ_INS_AU = 698 -SYSZ_INS_AUR = 699 -SYSZ_INS_AW = 700 -SYSZ_INS_AWR = 701 -SYSZ_INS_AXR = 702 -SYSZ_INS_AXTR = 703 -SYSZ_INS_AXTRA = 704 -SYSZ_INS_B = 705 -SYSZ_INS_BAKR = 706 -SYSZ_INS_BAL = 707 -SYSZ_INS_BALR = 708 -SYSZ_INS_BAS = 709 -SYSZ_INS_BASSM = 710 -SYSZ_INS_BC = 711 -SYSZ_INS_BCT = 712 -SYSZ_INS_BCTG = 713 -SYSZ_INS_BCTGR = 714 -SYSZ_INS_BCTR = 715 -SYSZ_INS_BE = 716 -SYSZ_INS_BH = 717 -SYSZ_INS_BHE = 718 -SYSZ_INS_BI = 719 -SYSZ_INS_BIC = 720 -SYSZ_INS_BIE = 721 -SYSZ_INS_BIH = 722 -SYSZ_INS_BIHE = 723 -SYSZ_INS_BIL = 724 -SYSZ_INS_BILE = 725 -SYSZ_INS_BILH = 726 -SYSZ_INS_BIM = 727 -SYSZ_INS_BINE = 728 -SYSZ_INS_BINH = 729 -SYSZ_INS_BINHE = 730 -SYSZ_INS_BINL = 731 -SYSZ_INS_BINLE = 732 -SYSZ_INS_BINLH = 733 -SYSZ_INS_BINM = 734 -SYSZ_INS_BINO = 735 -SYSZ_INS_BINP = 736 -SYSZ_INS_BINZ = 737 -SYSZ_INS_BIO = 738 -SYSZ_INS_BIP = 739 -SYSZ_INS_BIZ = 740 -SYSZ_INS_BL = 741 -SYSZ_INS_BLE = 742 -SYSZ_INS_BLH = 743 -SYSZ_INS_BM = 744 -SYSZ_INS_BMR = 745 -SYSZ_INS_BNE = 746 -SYSZ_INS_BNH = 747 -SYSZ_INS_BNHE = 748 -SYSZ_INS_BNL = 749 -SYSZ_INS_BNLE = 750 -SYSZ_INS_BNLH = 751 -SYSZ_INS_BNM = 752 -SYSZ_INS_BNMR = 753 -SYSZ_INS_BNO = 754 -SYSZ_INS_BNP = 755 -SYSZ_INS_BNPR = 756 -SYSZ_INS_BNZ = 757 -SYSZ_INS_BNZR = 758 -SYSZ_INS_BO = 759 -SYSZ_INS_BP = 760 -SYSZ_INS_BPP = 761 -SYSZ_INS_BPR = 762 -SYSZ_INS_BPRP = 763 -SYSZ_INS_BRCTH = 764 -SYSZ_INS_BRXH = 765 -SYSZ_INS_BRXHG = 766 -SYSZ_INS_BRXLE = 767 -SYSZ_INS_BRXLG = 768 -SYSZ_INS_BSA = 769 -SYSZ_INS_BSG = 770 -SYSZ_INS_BSM = 771 -SYSZ_INS_BXH = 772 -SYSZ_INS_BXHG = 773 -SYSZ_INS_BXLE = 774 -SYSZ_INS_BXLEG = 775 -SYSZ_INS_BZ = 776 -SYSZ_INS_BZR = 777 -SYSZ_INS_CD = 778 -SYSZ_INS_CDFBRA = 779 -SYSZ_INS_CDFR = 780 -SYSZ_INS_CDFTR = 781 -SYSZ_INS_CDGBRA = 782 -SYSZ_INS_CDGR = 783 -SYSZ_INS_CDGTR = 784 -SYSZ_INS_CDGTRA = 785 -SYSZ_INS_CDLFTR = 786 -SYSZ_INS_CDLGTR = 787 -SYSZ_INS_CDPT = 788 -SYSZ_INS_CDR = 789 -SYSZ_INS_CDS = 790 -SYSZ_INS_CDSG = 791 -SYSZ_INS_CDSTR = 792 -SYSZ_INS_CDSY = 793 -SYSZ_INS_CDTR = 794 -SYSZ_INS_CDUTR = 795 -SYSZ_INS_CDZT = 796 -SYSZ_INS_CE = 797 -SYSZ_INS_CEDTR = 798 -SYSZ_INS_CEFBRA = 799 -SYSZ_INS_CEFR = 800 -SYSZ_INS_CEGBRA = 801 -SYSZ_INS_CEGR = 802 -SYSZ_INS_CER = 803 -SYSZ_INS_CEXTR = 804 -SYSZ_INS_CFC = 805 -SYSZ_INS_CFDBRA = 806 -SYSZ_INS_CFDR = 807 -SYSZ_INS_CFDTR = 808 -SYSZ_INS_CFEBRA = 809 -SYSZ_INS_CFER = 810 -SYSZ_INS_CFXBRA = 811 -SYSZ_INS_CFXR = 812 -SYSZ_INS_CFXTR = 813 -SYSZ_INS_CGDBRA = 814 -SYSZ_INS_CGDR = 815 -SYSZ_INS_CGDTR = 816 -SYSZ_INS_CGDTRA = 817 -SYSZ_INS_CGEBRA = 818 -SYSZ_INS_CGER = 819 -SYSZ_INS_CGIB = 820 -SYSZ_INS_CGIBE = 821 -SYSZ_INS_CGIBH = 822 -SYSZ_INS_CGIBHE = 823 -SYSZ_INS_CGIBL = 824 -SYSZ_INS_CGIBLE = 825 -SYSZ_INS_CGIBLH = 826 -SYSZ_INS_CGIBNE = 827 -SYSZ_INS_CGIBNH = 828 -SYSZ_INS_CGIBNHE = 829 -SYSZ_INS_CGIBNL = 830 -SYSZ_INS_CGIBNLE = 831 -SYSZ_INS_CGIBNLH = 832 -SYSZ_INS_CGIT = 833 -SYSZ_INS_CGITE = 834 -SYSZ_INS_CGITH = 835 -SYSZ_INS_CGITHE = 836 -SYSZ_INS_CGITL = 837 -SYSZ_INS_CGITLE = 838 -SYSZ_INS_CGITLH = 839 -SYSZ_INS_CGITNE = 840 -SYSZ_INS_CGITNH = 841 -SYSZ_INS_CGITNHE = 842 -SYSZ_INS_CGITNL = 843 -SYSZ_INS_CGITNLE = 844 -SYSZ_INS_CGITNLH = 845 -SYSZ_INS_CGRB = 846 -SYSZ_INS_CGRBE = 847 -SYSZ_INS_CGRBH = 848 -SYSZ_INS_CGRBHE = 849 -SYSZ_INS_CGRBL = 850 -SYSZ_INS_CGRBLE = 851 -SYSZ_INS_CGRBLH = 852 -SYSZ_INS_CGRBNE = 853 -SYSZ_INS_CGRBNH = 854 -SYSZ_INS_CGRBNHE = 855 -SYSZ_INS_CGRBNL = 856 -SYSZ_INS_CGRBNLE = 857 -SYSZ_INS_CGRBNLH = 858 -SYSZ_INS_CGRT = 859 -SYSZ_INS_CGRTE = 860 -SYSZ_INS_CGRTH = 861 -SYSZ_INS_CGRTHE = 862 -SYSZ_INS_CGRTL = 863 -SYSZ_INS_CGRTLE = 864 -SYSZ_INS_CGRTLH = 865 -SYSZ_INS_CGRTNE = 866 -SYSZ_INS_CGRTNH = 867 -SYSZ_INS_CGRTNHE = 868 -SYSZ_INS_CGRTNL = 869 -SYSZ_INS_CGRTNLE = 870 -SYSZ_INS_CGRTNLH = 871 -SYSZ_INS_CGXBRA = 872 -SYSZ_INS_CGXR = 873 -SYSZ_INS_CGXTR = 874 -SYSZ_INS_CGXTRA = 875 -SYSZ_INS_CHHR = 876 -SYSZ_INS_CHLR = 877 -SYSZ_INS_CIB = 878 -SYSZ_INS_CIBE = 879 -SYSZ_INS_CIBH = 880 -SYSZ_INS_CIBHE = 881 -SYSZ_INS_CIBL = 882 -SYSZ_INS_CIBLE = 883 -SYSZ_INS_CIBLH = 884 -SYSZ_INS_CIBNE = 885 -SYSZ_INS_CIBNH = 886 -SYSZ_INS_CIBNHE = 887 -SYSZ_INS_CIBNL = 888 -SYSZ_INS_CIBNLE = 889 -SYSZ_INS_CIBNLH = 890 -SYSZ_INS_CIT = 891 -SYSZ_INS_CITE = 892 -SYSZ_INS_CITH = 893 -SYSZ_INS_CITHE = 894 -SYSZ_INS_CITL = 895 -SYSZ_INS_CITLE = 896 -SYSZ_INS_CITLH = 897 -SYSZ_INS_CITNE = 898 -SYSZ_INS_CITNH = 899 -SYSZ_INS_CITNHE = 900 -SYSZ_INS_CITNL = 901 -SYSZ_INS_CITNLE = 902 -SYSZ_INS_CITNLH = 903 -SYSZ_INS_CKSM = 904 -SYSZ_INS_CLCL = 905 -SYSZ_INS_CLCLE = 906 -SYSZ_INS_CLCLU = 907 -SYSZ_INS_CLFDTR = 908 -SYSZ_INS_CLFIT = 909 -SYSZ_INS_CLFITE = 910 -SYSZ_INS_CLFITH = 911 -SYSZ_INS_CLFITHE = 912 -SYSZ_INS_CLFITL = 913 -SYSZ_INS_CLFITLE = 914 -SYSZ_INS_CLFITLH = 915 -SYSZ_INS_CLFITNE = 916 -SYSZ_INS_CLFITNH = 917 -SYSZ_INS_CLFITNHE = 918 -SYSZ_INS_CLFITNL = 919 -SYSZ_INS_CLFITNLE = 920 -SYSZ_INS_CLFITNLH = 921 -SYSZ_INS_CLFXTR = 922 -SYSZ_INS_CLGDTR = 923 -SYSZ_INS_CLGIB = 924 -SYSZ_INS_CLGIBE = 925 -SYSZ_INS_CLGIBH = 926 -SYSZ_INS_CLGIBHE = 927 -SYSZ_INS_CLGIBL = 928 -SYSZ_INS_CLGIBLE = 929 -SYSZ_INS_CLGIBLH = 930 -SYSZ_INS_CLGIBNE = 931 -SYSZ_INS_CLGIBNH = 932 -SYSZ_INS_CLGIBNHE = 933 -SYSZ_INS_CLGIBNL = 934 -SYSZ_INS_CLGIBNLE = 935 -SYSZ_INS_CLGIBNLH = 936 -SYSZ_INS_CLGIT = 937 -SYSZ_INS_CLGITE = 938 -SYSZ_INS_CLGITH = 939 -SYSZ_INS_CLGITHE = 940 -SYSZ_INS_CLGITL = 941 -SYSZ_INS_CLGITLE = 942 -SYSZ_INS_CLGITLH = 943 -SYSZ_INS_CLGITNE = 944 -SYSZ_INS_CLGITNH = 945 -SYSZ_INS_CLGITNHE = 946 -SYSZ_INS_CLGITNL = 947 -SYSZ_INS_CLGITNLE = 948 -SYSZ_INS_CLGITNLH = 949 -SYSZ_INS_CLGRB = 950 -SYSZ_INS_CLGRBE = 951 -SYSZ_INS_CLGRBH = 952 -SYSZ_INS_CLGRBHE = 953 -SYSZ_INS_CLGRBL = 954 -SYSZ_INS_CLGRBLE = 955 -SYSZ_INS_CLGRBLH = 956 -SYSZ_INS_CLGRBNE = 957 -SYSZ_INS_CLGRBNH = 958 -SYSZ_INS_CLGRBNHE = 959 -SYSZ_INS_CLGRBNL = 960 -SYSZ_INS_CLGRBNLE = 961 -SYSZ_INS_CLGRBNLH = 962 -SYSZ_INS_CLGRT = 963 -SYSZ_INS_CLGRTE = 964 -SYSZ_INS_CLGRTH = 965 -SYSZ_INS_CLGRTHE = 966 -SYSZ_INS_CLGRTL = 967 -SYSZ_INS_CLGRTLE = 968 -SYSZ_INS_CLGRTLH = 969 -SYSZ_INS_CLGRTNE = 970 -SYSZ_INS_CLGRTNH = 971 -SYSZ_INS_CLGRTNHE = 972 -SYSZ_INS_CLGRTNL = 973 -SYSZ_INS_CLGRTNLE = 974 -SYSZ_INS_CLGRTNLH = 975 -SYSZ_INS_CLGT = 976 -SYSZ_INS_CLGTE = 977 -SYSZ_INS_CLGTH = 978 -SYSZ_INS_CLGTHE = 979 -SYSZ_INS_CLGTL = 980 -SYSZ_INS_CLGTLE = 981 -SYSZ_INS_CLGTLH = 982 -SYSZ_INS_CLGTNE = 983 -SYSZ_INS_CLGTNH = 984 -SYSZ_INS_CLGTNHE = 985 -SYSZ_INS_CLGTNL = 986 -SYSZ_INS_CLGTNLE = 987 -SYSZ_INS_CLGTNLH = 988 -SYSZ_INS_CLGXTR = 989 -SYSZ_INS_CLHHR = 990 -SYSZ_INS_CLHLR = 991 -SYSZ_INS_CLIB = 992 -SYSZ_INS_CLIBE = 993 -SYSZ_INS_CLIBH = 994 -SYSZ_INS_CLIBHE = 995 -SYSZ_INS_CLIBL = 996 -SYSZ_INS_CLIBLE = 997 -SYSZ_INS_CLIBLH = 998 -SYSZ_INS_CLIBNE = 999 -SYSZ_INS_CLIBNH = 1000 -SYSZ_INS_CLIBNHE = 1001 -SYSZ_INS_CLIBNL = 1002 -SYSZ_INS_CLIBNLE = 1003 -SYSZ_INS_CLIBNLH = 1004 -SYSZ_INS_CLM = 1005 -SYSZ_INS_CLMH = 1006 -SYSZ_INS_CLMY = 1007 -SYSZ_INS_CLRB = 1008 -SYSZ_INS_CLRBE = 1009 -SYSZ_INS_CLRBH = 1010 -SYSZ_INS_CLRBHE = 1011 -SYSZ_INS_CLRBL = 1012 -SYSZ_INS_CLRBLE = 1013 -SYSZ_INS_CLRBLH = 1014 -SYSZ_INS_CLRBNE = 1015 -SYSZ_INS_CLRBNH = 1016 -SYSZ_INS_CLRBNHE = 1017 -SYSZ_INS_CLRBNL = 1018 -SYSZ_INS_CLRBNLE = 1019 -SYSZ_INS_CLRBNLH = 1020 -SYSZ_INS_CLRT = 1021 -SYSZ_INS_CLRTE = 1022 -SYSZ_INS_CLRTH = 1023 -SYSZ_INS_CLRTHE = 1024 -SYSZ_INS_CLRTL = 1025 -SYSZ_INS_CLRTLE = 1026 -SYSZ_INS_CLRTLH = 1027 -SYSZ_INS_CLRTNE = 1028 -SYSZ_INS_CLRTNH = 1029 -SYSZ_INS_CLRTNHE = 1030 -SYSZ_INS_CLRTNL = 1031 -SYSZ_INS_CLRTNLE = 1032 -SYSZ_INS_CLRTNLH = 1033 -SYSZ_INS_CLT = 1034 -SYSZ_INS_CLTE = 1035 -SYSZ_INS_CLTH = 1036 -SYSZ_INS_CLTHE = 1037 -SYSZ_INS_CLTL = 1038 -SYSZ_INS_CLTLE = 1039 -SYSZ_INS_CLTLH = 1040 -SYSZ_INS_CLTNE = 1041 -SYSZ_INS_CLTNH = 1042 -SYSZ_INS_CLTNHE = 1043 -SYSZ_INS_CLTNL = 1044 -SYSZ_INS_CLTNLE = 1045 -SYSZ_INS_CLTNLH = 1046 -SYSZ_INS_CMPSC = 1047 -SYSZ_INS_CP = 1048 -SYSZ_INS_CPDT = 1049 -SYSZ_INS_CPXT = 1050 -SYSZ_INS_CPYA = 1051 -SYSZ_INS_CRB = 1052 -SYSZ_INS_CRBE = 1053 -SYSZ_INS_CRBH = 1054 -SYSZ_INS_CRBHE = 1055 -SYSZ_INS_CRBL = 1056 -SYSZ_INS_CRBLE = 1057 -SYSZ_INS_CRBLH = 1058 -SYSZ_INS_CRBNE = 1059 -SYSZ_INS_CRBNH = 1060 -SYSZ_INS_CRBNHE = 1061 -SYSZ_INS_CRBNL = 1062 -SYSZ_INS_CRBNLE = 1063 -SYSZ_INS_CRBNLH = 1064 -SYSZ_INS_CRDTE = 1065 -SYSZ_INS_CRT = 1066 -SYSZ_INS_CRTE = 1067 -SYSZ_INS_CRTH = 1068 -SYSZ_INS_CRTHE = 1069 -SYSZ_INS_CRTL = 1070 -SYSZ_INS_CRTLE = 1071 -SYSZ_INS_CRTLH = 1072 -SYSZ_INS_CRTNE = 1073 -SYSZ_INS_CRTNH = 1074 -SYSZ_INS_CRTNHE = 1075 -SYSZ_INS_CRTNL = 1076 -SYSZ_INS_CRTNLE = 1077 -SYSZ_INS_CRTNLH = 1078 -SYSZ_INS_CSCH = 1079 -SYSZ_INS_CSDTR = 1080 -SYSZ_INS_CSP = 1081 -SYSZ_INS_CSPG = 1082 -SYSZ_INS_CSST = 1083 -SYSZ_INS_CSXTR = 1084 -SYSZ_INS_CU12 = 1085 -SYSZ_INS_CU14 = 1086 -SYSZ_INS_CU21 = 1087 -SYSZ_INS_CU24 = 1088 -SYSZ_INS_CU41 = 1089 -SYSZ_INS_CU42 = 1090 -SYSZ_INS_CUDTR = 1091 -SYSZ_INS_CUSE = 1092 -SYSZ_INS_CUTFU = 1093 -SYSZ_INS_CUUTF = 1094 -SYSZ_INS_CUXTR = 1095 -SYSZ_INS_CVB = 1096 -SYSZ_INS_CVBG = 1097 -SYSZ_INS_CVBY = 1098 -SYSZ_INS_CVD = 1099 -SYSZ_INS_CVDG = 1100 -SYSZ_INS_CVDY = 1101 -SYSZ_INS_CXFBRA = 1102 -SYSZ_INS_CXFR = 1103 -SYSZ_INS_CXFTR = 1104 -SYSZ_INS_CXGBRA = 1105 -SYSZ_INS_CXGR = 1106 -SYSZ_INS_CXGTR = 1107 -SYSZ_INS_CXGTRA = 1108 -SYSZ_INS_CXLFTR = 1109 -SYSZ_INS_CXLGTR = 1110 -SYSZ_INS_CXPT = 1111 -SYSZ_INS_CXR = 1112 -SYSZ_INS_CXSTR = 1113 -SYSZ_INS_CXTR = 1114 -SYSZ_INS_CXUTR = 1115 -SYSZ_INS_CXZT = 1116 -SYSZ_INS_CZDT = 1117 -SYSZ_INS_CZXT = 1118 -SYSZ_INS_D = 1119 -SYSZ_INS_DD = 1120 -SYSZ_INS_DDR = 1121 -SYSZ_INS_DDTR = 1122 -SYSZ_INS_DDTRA = 1123 -SYSZ_INS_DE = 1124 -SYSZ_INS_DER = 1125 -SYSZ_INS_DIAG = 1126 -SYSZ_INS_DIDBR = 1127 -SYSZ_INS_DIEBR = 1128 -SYSZ_INS_DP = 1129 -SYSZ_INS_DR = 1130 -SYSZ_INS_DXR = 1131 -SYSZ_INS_DXTR = 1132 -SYSZ_INS_DXTRA = 1133 -SYSZ_INS_ECAG = 1134 -SYSZ_INS_ECCTR = 1135 -SYSZ_INS_ECPGA = 1136 -SYSZ_INS_ECTG = 1137 -SYSZ_INS_ED = 1138 -SYSZ_INS_EDMK = 1139 -SYSZ_INS_EEDTR = 1140 -SYSZ_INS_EEXTR = 1141 -SYSZ_INS_EFPC = 1142 -SYSZ_INS_EPAIR = 1143 -SYSZ_INS_EPAR = 1144 -SYSZ_INS_EPCTR = 1145 -SYSZ_INS_EPSW = 1146 -SYSZ_INS_EREG = 1147 -SYSZ_INS_EREGG = 1148 -SYSZ_INS_ESAIR = 1149 -SYSZ_INS_ESAR = 1150 -SYSZ_INS_ESDTR = 1151 -SYSZ_INS_ESEA = 1152 -SYSZ_INS_ESTA = 1153 -SYSZ_INS_ESXTR = 1154 -SYSZ_INS_ETND = 1155 -SYSZ_INS_EX = 1156 -SYSZ_INS_EXRL = 1157 -SYSZ_INS_FIDR = 1158 -SYSZ_INS_FIDTR = 1159 -SYSZ_INS_FIER = 1160 -SYSZ_INS_FIXR = 1161 -SYSZ_INS_FIXTR = 1162 -SYSZ_INS_HDR = 1163 -SYSZ_INS_HER = 1164 -SYSZ_INS_HSCH = 1165 -SYSZ_INS_IAC = 1166 -SYSZ_INS_ICM = 1167 -SYSZ_INS_ICMH = 1168 -SYSZ_INS_ICMY = 1169 -SYSZ_INS_IDTE = 1170 -SYSZ_INS_IEDTR = 1171 -SYSZ_INS_IEXTR = 1172 -SYSZ_INS_IPK = 1173 -SYSZ_INS_IPTE = 1174 -SYSZ_INS_IRBM = 1175 -SYSZ_INS_ISKE = 1176 -SYSZ_INS_IVSK = 1177 -SYSZ_INS_JGM = 1178 -SYSZ_INS_JGNM = 1179 -SYSZ_INS_JGNP = 1180 -SYSZ_INS_JGNZ = 1181 -SYSZ_INS_JGP = 1182 -SYSZ_INS_JGZ = 1183 -SYSZ_INS_JM = 1184 -SYSZ_INS_JNM = 1185 -SYSZ_INS_JNP = 1186 -SYSZ_INS_JNZ = 1187 -SYSZ_INS_JP = 1188 -SYSZ_INS_JZ = 1189 -SYSZ_INS_KDB = 1190 -SYSZ_INS_KDBR = 1191 -SYSZ_INS_KDTR = 1192 -SYSZ_INS_KEB = 1193 -SYSZ_INS_KEBR = 1194 -SYSZ_INS_KIMD = 1195 -SYSZ_INS_KLMD = 1196 -SYSZ_INS_KM = 1197 -SYSZ_INS_KMA = 1198 -SYSZ_INS_KMAC = 1199 -SYSZ_INS_KMC = 1200 -SYSZ_INS_KMCTR = 1201 -SYSZ_INS_KMF = 1202 -SYSZ_INS_KMO = 1203 -SYSZ_INS_KXBR = 1204 -SYSZ_INS_KXTR = 1205 -SYSZ_INS_LAE = 1206 -SYSZ_INS_LAEY = 1207 -SYSZ_INS_LAM = 1208 -SYSZ_INS_LAMY = 1209 -SYSZ_INS_LASP = 1210 -SYSZ_INS_LAT = 1211 -SYSZ_INS_LCBB = 1212 -SYSZ_INS_LCCTL = 1213 -SYSZ_INS_LCDFR = 1214 -SYSZ_INS_LCDR = 1215 -SYSZ_INS_LCER = 1216 -SYSZ_INS_LCTL = 1217 -SYSZ_INS_LCTLG = 1218 -SYSZ_INS_LCXR = 1219 -SYSZ_INS_LDE = 1220 -SYSZ_INS_LDER = 1221 -SYSZ_INS_LDETR = 1222 -SYSZ_INS_LDXR = 1223 -SYSZ_INS_LDXTR = 1224 -SYSZ_INS_LEDR = 1225 -SYSZ_INS_LEDTR = 1226 -SYSZ_INS_LEXR = 1227 -SYSZ_INS_LFAS = 1228 -SYSZ_INS_LFHAT = 1229 -SYSZ_INS_LFPC = 1230 -SYSZ_INS_LGAT = 1231 -SYSZ_INS_LGG = 1232 -SYSZ_INS_LGSC = 1233 -SYSZ_INS_LLGFAT = 1234 -SYSZ_INS_LLGFSG = 1235 -SYSZ_INS_LLGT = 1236 -SYSZ_INS_LLGTAT = 1237 -SYSZ_INS_LLGTR = 1238 -SYSZ_INS_LLZRGF = 1239 -SYSZ_INS_LM = 1240 -SYSZ_INS_LMD = 1241 -SYSZ_INS_LMH = 1242 -SYSZ_INS_LMY = 1243 -SYSZ_INS_LNDFR = 1244 -SYSZ_INS_LNDR = 1245 -SYSZ_INS_LNER = 1246 -SYSZ_INS_LNXR = 1247 -SYSZ_INS_LOCFH = 1248 -SYSZ_INS_LOCFHE = 1249 -SYSZ_INS_LOCFHH = 1250 -SYSZ_INS_LOCFHHE = 1251 -SYSZ_INS_LOCFHL = 1252 -SYSZ_INS_LOCFHLE = 1253 -SYSZ_INS_LOCFHLH = 1254 -SYSZ_INS_LOCFHM = 1255 -SYSZ_INS_LOCFHNE = 1256 -SYSZ_INS_LOCFHNH = 1257 -SYSZ_INS_LOCFHNHE = 1258 -SYSZ_INS_LOCFHNL = 1259 -SYSZ_INS_LOCFHNLE = 1260 -SYSZ_INS_LOCFHNLH = 1261 -SYSZ_INS_LOCFHNM = 1262 -SYSZ_INS_LOCFHNO = 1263 -SYSZ_INS_LOCFHNP = 1264 -SYSZ_INS_LOCFHNZ = 1265 -SYSZ_INS_LOCFHO = 1266 -SYSZ_INS_LOCFHP = 1267 -SYSZ_INS_LOCFHR = 1268 -SYSZ_INS_LOCFHRE = 1269 -SYSZ_INS_LOCFHRH = 1270 -SYSZ_INS_LOCFHRHE = 1271 -SYSZ_INS_LOCFHRL = 1272 -SYSZ_INS_LOCFHRLE = 1273 -SYSZ_INS_LOCFHRLH = 1274 -SYSZ_INS_LOCFHRM = 1275 -SYSZ_INS_LOCFHRNE = 1276 -SYSZ_INS_LOCFHRNH = 1277 -SYSZ_INS_LOCFHRNHE = 1278 -SYSZ_INS_LOCFHRNL = 1279 -SYSZ_INS_LOCFHRNLE = 1280 -SYSZ_INS_LOCFHRNLH = 1281 -SYSZ_INS_LOCFHRNM = 1282 -SYSZ_INS_LOCFHRNO = 1283 -SYSZ_INS_LOCFHRNP = 1284 -SYSZ_INS_LOCFHRNZ = 1285 -SYSZ_INS_LOCFHRO = 1286 -SYSZ_INS_LOCFHRP = 1287 -SYSZ_INS_LOCFHRZ = 1288 -SYSZ_INS_LOCFHZ = 1289 -SYSZ_INS_LOCGHI = 1290 -SYSZ_INS_LOCGHIE = 1291 -SYSZ_INS_LOCGHIH = 1292 -SYSZ_INS_LOCGHIHE = 1293 -SYSZ_INS_LOCGHIL = 1294 -SYSZ_INS_LOCGHILE = 1295 -SYSZ_INS_LOCGHILH = 1296 -SYSZ_INS_LOCGHIM = 1297 -SYSZ_INS_LOCGHINE = 1298 -SYSZ_INS_LOCGHINH = 1299 -SYSZ_INS_LOCGHINHE = 1300 -SYSZ_INS_LOCGHINL = 1301 -SYSZ_INS_LOCGHINLE = 1302 -SYSZ_INS_LOCGHINLH = 1303 -SYSZ_INS_LOCGHINM = 1304 -SYSZ_INS_LOCGHINO = 1305 -SYSZ_INS_LOCGHINP = 1306 -SYSZ_INS_LOCGHINZ = 1307 -SYSZ_INS_LOCGHIO = 1308 -SYSZ_INS_LOCGHIP = 1309 -SYSZ_INS_LOCGHIZ = 1310 -SYSZ_INS_LOCGM = 1311 -SYSZ_INS_LOCGNM = 1312 -SYSZ_INS_LOCGNP = 1313 -SYSZ_INS_LOCGNZ = 1314 -SYSZ_INS_LOCGP = 1315 -SYSZ_INS_LOCGRM = 1316 -SYSZ_INS_LOCGRNM = 1317 -SYSZ_INS_LOCGRNP = 1318 -SYSZ_INS_LOCGRNZ = 1319 -SYSZ_INS_LOCGRP = 1320 -SYSZ_INS_LOCGRZ = 1321 -SYSZ_INS_LOCGZ = 1322 -SYSZ_INS_LOCHHI = 1323 -SYSZ_INS_LOCHHIE = 1324 -SYSZ_INS_LOCHHIH = 1325 -SYSZ_INS_LOCHHIHE = 1326 -SYSZ_INS_LOCHHIL = 1327 -SYSZ_INS_LOCHHILE = 1328 -SYSZ_INS_LOCHHILH = 1329 -SYSZ_INS_LOCHHIM = 1330 -SYSZ_INS_LOCHHINE = 1331 -SYSZ_INS_LOCHHINH = 1332 -SYSZ_INS_LOCHHINHE = 1333 -SYSZ_INS_LOCHHINL = 1334 -SYSZ_INS_LOCHHINLE = 1335 -SYSZ_INS_LOCHHINLH = 1336 -SYSZ_INS_LOCHHINM = 1337 -SYSZ_INS_LOCHHINO = 1338 -SYSZ_INS_LOCHHINP = 1339 -SYSZ_INS_LOCHHINZ = 1340 -SYSZ_INS_LOCHHIO = 1341 -SYSZ_INS_LOCHHIP = 1342 -SYSZ_INS_LOCHHIZ = 1343 -SYSZ_INS_LOCHI = 1344 -SYSZ_INS_LOCHIE = 1345 -SYSZ_INS_LOCHIH = 1346 -SYSZ_INS_LOCHIHE = 1347 -SYSZ_INS_LOCHIL = 1348 -SYSZ_INS_LOCHILE = 1349 -SYSZ_INS_LOCHILH = 1350 -SYSZ_INS_LOCHIM = 1351 -SYSZ_INS_LOCHINE = 1352 -SYSZ_INS_LOCHINH = 1353 -SYSZ_INS_LOCHINHE = 1354 -SYSZ_INS_LOCHINL = 1355 -SYSZ_INS_LOCHINLE = 1356 -SYSZ_INS_LOCHINLH = 1357 -SYSZ_INS_LOCHINM = 1358 -SYSZ_INS_LOCHINO = 1359 -SYSZ_INS_LOCHINP = 1360 -SYSZ_INS_LOCHINZ = 1361 -SYSZ_INS_LOCHIO = 1362 -SYSZ_INS_LOCHIP = 1363 -SYSZ_INS_LOCHIZ = 1364 -SYSZ_INS_LOCM = 1365 -SYSZ_INS_LOCNM = 1366 -SYSZ_INS_LOCNP = 1367 -SYSZ_INS_LOCNZ = 1368 -SYSZ_INS_LOCP = 1369 -SYSZ_INS_LOCRM = 1370 -SYSZ_INS_LOCRNM = 1371 -SYSZ_INS_LOCRNP = 1372 -SYSZ_INS_LOCRNZ = 1373 -SYSZ_INS_LOCRP = 1374 -SYSZ_INS_LOCRZ = 1375 -SYSZ_INS_LOCZ = 1376 -SYSZ_INS_LPCTL = 1377 -SYSZ_INS_LPD = 1378 -SYSZ_INS_LPDFR = 1379 -SYSZ_INS_LPDG = 1380 -SYSZ_INS_LPDR = 1381 -SYSZ_INS_LPER = 1382 -SYSZ_INS_LPP = 1383 -SYSZ_INS_LPQ = 1384 -SYSZ_INS_LPSW = 1385 -SYSZ_INS_LPSWE = 1386 -SYSZ_INS_LPTEA = 1387 -SYSZ_INS_LPXR = 1388 -SYSZ_INS_LRA = 1389 -SYSZ_INS_LRAG = 1390 -SYSZ_INS_LRAY = 1391 -SYSZ_INS_LRDR = 1392 -SYSZ_INS_LRER = 1393 -SYSZ_INS_LRVH = 1394 -SYSZ_INS_LSCTL = 1395 -SYSZ_INS_LTDR = 1396 -SYSZ_INS_LTDTR = 1397 -SYSZ_INS_LTER = 1398 -SYSZ_INS_LTXR = 1399 -SYSZ_INS_LTXTR = 1400 -SYSZ_INS_LURA = 1401 -SYSZ_INS_LURAG = 1402 -SYSZ_INS_LXD = 1403 -SYSZ_INS_LXDR = 1404 -SYSZ_INS_LXDTR = 1405 -SYSZ_INS_LXE = 1406 -SYSZ_INS_LXER = 1407 -SYSZ_INS_LZRF = 1408 -SYSZ_INS_LZRG = 1409 -SYSZ_INS_M = 1410 -SYSZ_INS_MAD = 1411 -SYSZ_INS_MADR = 1412 -SYSZ_INS_MAE = 1413 -SYSZ_INS_MAER = 1414 -SYSZ_INS_MAY = 1415 -SYSZ_INS_MAYH = 1416 -SYSZ_INS_MAYHR = 1417 -SYSZ_INS_MAYL = 1418 -SYSZ_INS_MAYLR = 1419 -SYSZ_INS_MAYR = 1420 -SYSZ_INS_MC = 1421 -SYSZ_INS_MD = 1422 -SYSZ_INS_MDE = 1423 -SYSZ_INS_MDER = 1424 -SYSZ_INS_MDR = 1425 -SYSZ_INS_MDTR = 1426 -SYSZ_INS_MDTRA = 1427 -SYSZ_INS_ME = 1428 -SYSZ_INS_MEE = 1429 -SYSZ_INS_MEER = 1430 -SYSZ_INS_MER = 1431 -SYSZ_INS_MFY = 1432 -SYSZ_INS_MG = 1433 -SYSZ_INS_MGH = 1434 -SYSZ_INS_MGRK = 1435 -SYSZ_INS_ML = 1436 -SYSZ_INS_MLR = 1437 -SYSZ_INS_MP = 1438 -SYSZ_INS_MR = 1439 -SYSZ_INS_MSC = 1440 -SYSZ_INS_MSCH = 1441 -SYSZ_INS_MSD = 1442 -SYSZ_INS_MSDR = 1443 -SYSZ_INS_MSE = 1444 -SYSZ_INS_MSER = 1445 -SYSZ_INS_MSGC = 1446 -SYSZ_INS_MSGRKC = 1447 -SYSZ_INS_MSRKC = 1448 -SYSZ_INS_MSTA = 1449 -SYSZ_INS_MVCDK = 1450 -SYSZ_INS_MVCIN = 1451 -SYSZ_INS_MVCK = 1452 -SYSZ_INS_MVCL = 1453 -SYSZ_INS_MVCLE = 1454 -SYSZ_INS_MVCLU = 1455 -SYSZ_INS_MVCOS = 1456 -SYSZ_INS_MVCP = 1457 -SYSZ_INS_MVCS = 1458 -SYSZ_INS_MVCSK = 1459 -SYSZ_INS_MVN = 1460 -SYSZ_INS_MVO = 1461 -SYSZ_INS_MVPG = 1462 -SYSZ_INS_MVZ = 1463 -SYSZ_INS_MXD = 1464 -SYSZ_INS_MXDR = 1465 -SYSZ_INS_MXR = 1466 -SYSZ_INS_MXTR = 1467 -SYSZ_INS_MXTRA = 1468 -SYSZ_INS_MY = 1469 -SYSZ_INS_MYH = 1470 -SYSZ_INS_MYHR = 1471 -SYSZ_INS_MYL = 1472 -SYSZ_INS_MYLR = 1473 -SYSZ_INS_MYR = 1474 -SYSZ_INS_NIAI = 1475 -SYSZ_INS_NTSTG = 1476 -SYSZ_INS_PACK = 1477 -SYSZ_INS_PALB = 1478 -SYSZ_INS_PC = 1479 -SYSZ_INS_PCC = 1480 -SYSZ_INS_PCKMO = 1481 -SYSZ_INS_PFMF = 1482 -SYSZ_INS_PFPO = 1483 -SYSZ_INS_PGIN = 1484 -SYSZ_INS_PGOUT = 1485 -SYSZ_INS_PKA = 1486 -SYSZ_INS_PKU = 1487 -SYSZ_INS_PLO = 1488 -SYSZ_INS_POPCNT = 1489 -SYSZ_INS_PPA = 1490 -SYSZ_INS_PPNO = 1491 -SYSZ_INS_PR = 1492 -SYSZ_INS_PRNO = 1493 -SYSZ_INS_PT = 1494 -SYSZ_INS_PTF = 1495 -SYSZ_INS_PTFF = 1496 -SYSZ_INS_PTI = 1497 -SYSZ_INS_PTLB = 1498 -SYSZ_INS_QADTR = 1499 -SYSZ_INS_QAXTR = 1500 -SYSZ_INS_QCTRI = 1501 -SYSZ_INS_QSI = 1502 -SYSZ_INS_RCHP = 1503 -SYSZ_INS_RISBGN = 1504 -SYSZ_INS_RP = 1505 -SYSZ_INS_RRBE = 1506 -SYSZ_INS_RRBM = 1507 -SYSZ_INS_RRDTR = 1508 -SYSZ_INS_RRXTR = 1509 -SYSZ_INS_RSCH = 1510 -SYSZ_INS_SAC = 1511 -SYSZ_INS_SACF = 1512 -SYSZ_INS_SAL = 1513 -SYSZ_INS_SAM24 = 1514 -SYSZ_INS_SAM31 = 1515 -SYSZ_INS_SAM64 = 1516 -SYSZ_INS_SAR = 1517 -SYSZ_INS_SCCTR = 1518 -SYSZ_INS_SCHM = 1519 -SYSZ_INS_SCK = 1520 -SYSZ_INS_SCKC = 1521 -SYSZ_INS_SCKPF = 1522 -SYSZ_INS_SD = 1523 -SYSZ_INS_SDR = 1524 -SYSZ_INS_SDTR = 1525 -SYSZ_INS_SDTRA = 1526 -SYSZ_INS_SE = 1527 -SYSZ_INS_SER = 1528 -SYSZ_INS_SFASR = 1529 -SYSZ_INS_SFPC = 1530 -SYSZ_INS_SGH = 1531 -SYSZ_INS_SHHHR = 1532 -SYSZ_INS_SHHLR = 1533 -SYSZ_INS_SIE = 1534 -SYSZ_INS_SIGA = 1535 -SYSZ_INS_SIGP = 1536 -SYSZ_INS_SLA = 1537 -SYSZ_INS_SLAG = 1538 -SYSZ_INS_SLAK = 1539 -SYSZ_INS_SLDA = 1540 -SYSZ_INS_SLDL = 1541 -SYSZ_INS_SLDT = 1542 -SYSZ_INS_SLHHHR = 1543 -SYSZ_INS_SLHHLR = 1544 -SYSZ_INS_SLXT = 1545 -SYSZ_INS_SP = 1546 -SYSZ_INS_SPCTR = 1547 -SYSZ_INS_SPKA = 1548 -SYSZ_INS_SPM = 1549 -SYSZ_INS_SPT = 1550 -SYSZ_INS_SPX = 1551 -SYSZ_INS_SQD = 1552 -SYSZ_INS_SQDR = 1553 -SYSZ_INS_SQE = 1554 -SYSZ_INS_SQER = 1555 -SYSZ_INS_SQXR = 1556 -SYSZ_INS_SRDA = 1557 -SYSZ_INS_SRDL = 1558 -SYSZ_INS_SRDT = 1559 -SYSZ_INS_SRNM = 1560 -SYSZ_INS_SRNMB = 1561 -SYSZ_INS_SRNMT = 1562 -SYSZ_INS_SRP = 1563 -SYSZ_INS_SRSTU = 1564 -SYSZ_INS_SRXT = 1565 -SYSZ_INS_SSAIR = 1566 -SYSZ_INS_SSAR = 1567 -SYSZ_INS_SSCH = 1568 -SYSZ_INS_SSKE = 1569 -SYSZ_INS_SSM = 1570 -SYSZ_INS_STAM = 1571 -SYSZ_INS_STAMY = 1572 -SYSZ_INS_STAP = 1573 -SYSZ_INS_STCK = 1574 -SYSZ_INS_STCKC = 1575 -SYSZ_INS_STCKE = 1576 -SYSZ_INS_STCKF = 1577 -SYSZ_INS_STCM = 1578 -SYSZ_INS_STCMH = 1579 -SYSZ_INS_STCMY = 1580 -SYSZ_INS_STCPS = 1581 -SYSZ_INS_STCRW = 1582 -SYSZ_INS_STCTG = 1583 -SYSZ_INS_STCTL = 1584 -SYSZ_INS_STFL = 1585 -SYSZ_INS_STFLE = 1586 -SYSZ_INS_STFPC = 1587 -SYSZ_INS_STGSC = 1588 -SYSZ_INS_STIDP = 1589 -SYSZ_INS_STM = 1590 -SYSZ_INS_STMH = 1591 -SYSZ_INS_STMY = 1592 -SYSZ_INS_STNSM = 1593 -SYSZ_INS_STOCFH = 1594 -SYSZ_INS_STOCFHE = 1595 -SYSZ_INS_STOCFHH = 1596 -SYSZ_INS_STOCFHHE = 1597 -SYSZ_INS_STOCFHL = 1598 -SYSZ_INS_STOCFHLE = 1599 -SYSZ_INS_STOCFHLH = 1600 -SYSZ_INS_STOCFHM = 1601 -SYSZ_INS_STOCFHNE = 1602 -SYSZ_INS_STOCFHNH = 1603 -SYSZ_INS_STOCFHNHE = 1604 -SYSZ_INS_STOCFHNL = 1605 -SYSZ_INS_STOCFHNLE = 1606 -SYSZ_INS_STOCFHNLH = 1607 -SYSZ_INS_STOCFHNM = 1608 -SYSZ_INS_STOCFHNO = 1609 -SYSZ_INS_STOCFHNP = 1610 -SYSZ_INS_STOCFHNZ = 1611 -SYSZ_INS_STOCFHO = 1612 -SYSZ_INS_STOCFHP = 1613 -SYSZ_INS_STOCFHZ = 1614 -SYSZ_INS_STOCGM = 1615 -SYSZ_INS_STOCGNM = 1616 -SYSZ_INS_STOCGNP = 1617 -SYSZ_INS_STOCGNZ = 1618 -SYSZ_INS_STOCGP = 1619 -SYSZ_INS_STOCGZ = 1620 -SYSZ_INS_STOCM = 1621 -SYSZ_INS_STOCNM = 1622 -SYSZ_INS_STOCNP = 1623 -SYSZ_INS_STOCNZ = 1624 -SYSZ_INS_STOCP = 1625 -SYSZ_INS_STOCZ = 1626 -SYSZ_INS_STOSM = 1627 -SYSZ_INS_STPQ = 1628 -SYSZ_INS_STPT = 1629 -SYSZ_INS_STPX = 1630 -SYSZ_INS_STRAG = 1631 -SYSZ_INS_STRVH = 1632 -SYSZ_INS_STSCH = 1633 -SYSZ_INS_STSI = 1634 -SYSZ_INS_STURA = 1635 -SYSZ_INS_STURG = 1636 -SYSZ_INS_SU = 1637 -SYSZ_INS_SUR = 1638 -SYSZ_INS_SVC = 1639 -SYSZ_INS_SW = 1640 -SYSZ_INS_SWR = 1641 -SYSZ_INS_SXR = 1642 -SYSZ_INS_SXTR = 1643 -SYSZ_INS_SXTRA = 1644 -SYSZ_INS_TABORT = 1645 -SYSZ_INS_TAM = 1646 -SYSZ_INS_TAR = 1647 -SYSZ_INS_TB = 1648 -SYSZ_INS_TBDR = 1649 -SYSZ_INS_TBEDR = 1650 -SYSZ_INS_TBEGIN = 1651 -SYSZ_INS_TBEGINC = 1652 -SYSZ_INS_TCDB = 1653 -SYSZ_INS_TCEB = 1654 -SYSZ_INS_TCXB = 1655 -SYSZ_INS_TDCDT = 1656 -SYSZ_INS_TDCET = 1657 -SYSZ_INS_TDCXT = 1658 -SYSZ_INS_TDGDT = 1659 -SYSZ_INS_TDGET = 1660 -SYSZ_INS_TDGXT = 1661 -SYSZ_INS_TEND = 1662 -SYSZ_INS_THDER = 1663 -SYSZ_INS_THDR = 1664 -SYSZ_INS_TP = 1665 -SYSZ_INS_TPI = 1666 -SYSZ_INS_TPROT = 1667 -SYSZ_INS_TR = 1668 -SYSZ_INS_TRACE = 1669 -SYSZ_INS_TRACG = 1670 -SYSZ_INS_TRAP2 = 1671 -SYSZ_INS_TRAP4 = 1672 -SYSZ_INS_TRE = 1673 -SYSZ_INS_TROO = 1674 -SYSZ_INS_TROT = 1675 -SYSZ_INS_TRT = 1676 -SYSZ_INS_TRTE = 1677 -SYSZ_INS_TRTO = 1678 -SYSZ_INS_TRTR = 1679 -SYSZ_INS_TRTRE = 1680 -SYSZ_INS_TRTT = 1681 -SYSZ_INS_TS = 1682 -SYSZ_INS_TSCH = 1683 -SYSZ_INS_UNPK = 1684 -SYSZ_INS_UNPKA = 1685 -SYSZ_INS_UNPKU = 1686 -SYSZ_INS_UPT = 1687 -SYSZ_INS_VA = 1688 -SYSZ_INS_VAB = 1689 -SYSZ_INS_VAC = 1690 -SYSZ_INS_VACC = 1691 -SYSZ_INS_VACCB = 1692 -SYSZ_INS_VACCC = 1693 -SYSZ_INS_VACCCQ = 1694 -SYSZ_INS_VACCF = 1695 -SYSZ_INS_VACCG = 1696 -SYSZ_INS_VACCH = 1697 -SYSZ_INS_VACCQ = 1698 -SYSZ_INS_VACQ = 1699 -SYSZ_INS_VAF = 1700 -SYSZ_INS_VAG = 1701 -SYSZ_INS_VAH = 1702 -SYSZ_INS_VAP = 1703 -SYSZ_INS_VAQ = 1704 -SYSZ_INS_VAVG = 1705 -SYSZ_INS_VAVGB = 1706 -SYSZ_INS_VAVGF = 1707 -SYSZ_INS_VAVGG = 1708 -SYSZ_INS_VAVGH = 1709 -SYSZ_INS_VAVGL = 1710 -SYSZ_INS_VAVGLB = 1711 -SYSZ_INS_VAVGLF = 1712 -SYSZ_INS_VAVGLG = 1713 -SYSZ_INS_VAVGLH = 1714 -SYSZ_INS_VBPERM = 1715 -SYSZ_INS_VCDG = 1716 -SYSZ_INS_VCDGB = 1717 -SYSZ_INS_VCDLG = 1718 -SYSZ_INS_VCDLGB = 1719 -SYSZ_INS_VCEQ = 1720 -SYSZ_INS_VCEQB = 1721 -SYSZ_INS_VCEQBS = 1722 -SYSZ_INS_VCEQF = 1723 -SYSZ_INS_VCEQFS = 1724 -SYSZ_INS_VCEQG = 1725 -SYSZ_INS_VCEQGS = 1726 -SYSZ_INS_VCEQH = 1727 -SYSZ_INS_VCEQHS = 1728 -SYSZ_INS_VCGD = 1729 -SYSZ_INS_VCGDB = 1730 -SYSZ_INS_VCH = 1731 -SYSZ_INS_VCHB = 1732 -SYSZ_INS_VCHBS = 1733 -SYSZ_INS_VCHF = 1734 -SYSZ_INS_VCHFS = 1735 -SYSZ_INS_VCHG = 1736 -SYSZ_INS_VCHGS = 1737 -SYSZ_INS_VCHH = 1738 -SYSZ_INS_VCHHS = 1739 -SYSZ_INS_VCHL = 1740 -SYSZ_INS_VCHLB = 1741 -SYSZ_INS_VCHLBS = 1742 -SYSZ_INS_VCHLF = 1743 -SYSZ_INS_VCHLFS = 1744 -SYSZ_INS_VCHLG = 1745 -SYSZ_INS_VCHLGS = 1746 -SYSZ_INS_VCHLH = 1747 -SYSZ_INS_VCHLHS = 1748 -SYSZ_INS_VCKSM = 1749 -SYSZ_INS_VCLGD = 1750 -SYSZ_INS_VCLGDB = 1751 -SYSZ_INS_VCLZ = 1752 -SYSZ_INS_VCLZB = 1753 -SYSZ_INS_VCLZF = 1754 -SYSZ_INS_VCLZG = 1755 -SYSZ_INS_VCLZH = 1756 -SYSZ_INS_VCP = 1757 -SYSZ_INS_VCTZ = 1758 -SYSZ_INS_VCTZB = 1759 -SYSZ_INS_VCTZF = 1760 -SYSZ_INS_VCTZG = 1761 -SYSZ_INS_VCTZH = 1762 -SYSZ_INS_VCVB = 1763 -SYSZ_INS_VCVBG = 1764 -SYSZ_INS_VCVD = 1765 -SYSZ_INS_VCVDG = 1766 -SYSZ_INS_VDP = 1767 -SYSZ_INS_VEC = 1768 -SYSZ_INS_VECB = 1769 -SYSZ_INS_VECF = 1770 -SYSZ_INS_VECG = 1771 -SYSZ_INS_VECH = 1772 -SYSZ_INS_VECL = 1773 -SYSZ_INS_VECLB = 1774 -SYSZ_INS_VECLF = 1775 -SYSZ_INS_VECLG = 1776 -SYSZ_INS_VECLH = 1777 -SYSZ_INS_VERIM = 1778 -SYSZ_INS_VERIMB = 1779 -SYSZ_INS_VERIMF = 1780 -SYSZ_INS_VERIMG = 1781 -SYSZ_INS_VERIMH = 1782 -SYSZ_INS_VERLL = 1783 -SYSZ_INS_VERLLB = 1784 -SYSZ_INS_VERLLF = 1785 -SYSZ_INS_VERLLG = 1786 -SYSZ_INS_VERLLH = 1787 -SYSZ_INS_VERLLV = 1788 -SYSZ_INS_VERLLVB = 1789 -SYSZ_INS_VERLLVF = 1790 -SYSZ_INS_VERLLVG = 1791 -SYSZ_INS_VERLLVH = 1792 -SYSZ_INS_VESL = 1793 -SYSZ_INS_VESLB = 1794 -SYSZ_INS_VESLF = 1795 -SYSZ_INS_VESLG = 1796 -SYSZ_INS_VESLH = 1797 -SYSZ_INS_VESLV = 1798 -SYSZ_INS_VESLVB = 1799 -SYSZ_INS_VESLVF = 1800 -SYSZ_INS_VESLVG = 1801 -SYSZ_INS_VESLVH = 1802 -SYSZ_INS_VESRA = 1803 -SYSZ_INS_VESRAB = 1804 -SYSZ_INS_VESRAF = 1805 -SYSZ_INS_VESRAG = 1806 -SYSZ_INS_VESRAH = 1807 -SYSZ_INS_VESRAV = 1808 -SYSZ_INS_VESRAVB = 1809 -SYSZ_INS_VESRAVF = 1810 -SYSZ_INS_VESRAVG = 1811 -SYSZ_INS_VESRAVH = 1812 -SYSZ_INS_VESRL = 1813 -SYSZ_INS_VESRLB = 1814 -SYSZ_INS_VESRLF = 1815 -SYSZ_INS_VESRLG = 1816 -SYSZ_INS_VESRLH = 1817 -SYSZ_INS_VESRLV = 1818 -SYSZ_INS_VESRLVB = 1819 -SYSZ_INS_VESRLVF = 1820 -SYSZ_INS_VESRLVG = 1821 -SYSZ_INS_VESRLVH = 1822 -SYSZ_INS_VFA = 1823 -SYSZ_INS_VFADB = 1824 -SYSZ_INS_VFAE = 1825 -SYSZ_INS_VFAEB = 1826 -SYSZ_INS_VFAEBS = 1827 -SYSZ_INS_VFAEF = 1828 -SYSZ_INS_VFAEFS = 1829 -SYSZ_INS_VFAEH = 1830 -SYSZ_INS_VFAEHS = 1831 -SYSZ_INS_VFAEZB = 1832 -SYSZ_INS_VFAEZBS = 1833 -SYSZ_INS_VFAEZF = 1834 -SYSZ_INS_VFAEZFS = 1835 -SYSZ_INS_VFAEZH = 1836 -SYSZ_INS_VFAEZHS = 1837 -SYSZ_INS_VFASB = 1838 -SYSZ_INS_VFCE = 1839 -SYSZ_INS_VFCEDB = 1840 -SYSZ_INS_VFCEDBS = 1841 -SYSZ_INS_VFCESB = 1842 -SYSZ_INS_VFCESBS = 1843 -SYSZ_INS_VFCH = 1844 -SYSZ_INS_VFCHDB = 1845 -SYSZ_INS_VFCHDBS = 1846 -SYSZ_INS_VFCHE = 1847 -SYSZ_INS_VFCHEDB = 1848 -SYSZ_INS_VFCHEDBS = 1849 -SYSZ_INS_VFCHESB = 1850 -SYSZ_INS_VFCHESBS = 1851 -SYSZ_INS_VFCHSB = 1852 -SYSZ_INS_VFCHSBS = 1853 -SYSZ_INS_VFD = 1854 -SYSZ_INS_VFDDB = 1855 -SYSZ_INS_VFDSB = 1856 -SYSZ_INS_VFEE = 1857 -SYSZ_INS_VFEEB = 1858 -SYSZ_INS_VFEEBS = 1859 -SYSZ_INS_VFEEF = 1860 -SYSZ_INS_VFEEFS = 1861 -SYSZ_INS_VFEEH = 1862 -SYSZ_INS_VFEEHS = 1863 -SYSZ_INS_VFEEZB = 1864 -SYSZ_INS_VFEEZBS = 1865 -SYSZ_INS_VFEEZF = 1866 -SYSZ_INS_VFEEZFS = 1867 -SYSZ_INS_VFEEZH = 1868 -SYSZ_INS_VFEEZHS = 1869 -SYSZ_INS_VFENE = 1870 -SYSZ_INS_VFENEB = 1871 -SYSZ_INS_VFENEBS = 1872 -SYSZ_INS_VFENEF = 1873 -SYSZ_INS_VFENEFS = 1874 -SYSZ_INS_VFENEH = 1875 -SYSZ_INS_VFENEHS = 1876 -SYSZ_INS_VFENEZB = 1877 -SYSZ_INS_VFENEZBS = 1878 -SYSZ_INS_VFENEZF = 1879 -SYSZ_INS_VFENEZFS = 1880 -SYSZ_INS_VFENEZH = 1881 -SYSZ_INS_VFENEZHS = 1882 -SYSZ_INS_VFI = 1883 -SYSZ_INS_VFIDB = 1884 -SYSZ_INS_VFISB = 1885 -SYSZ_INS_VFKEDB = 1886 -SYSZ_INS_VFKEDBS = 1887 -SYSZ_INS_VFKESB = 1888 -SYSZ_INS_VFKESBS = 1889 -SYSZ_INS_VFKHDB = 1890 -SYSZ_INS_VFKHDBS = 1891 -SYSZ_INS_VFKHEDB = 1892 -SYSZ_INS_VFKHEDBS = 1893 -SYSZ_INS_VFKHESB = 1894 -SYSZ_INS_VFKHESBS = 1895 -SYSZ_INS_VFKHSB = 1896 -SYSZ_INS_VFKHSBS = 1897 -SYSZ_INS_VFLCDB = 1898 -SYSZ_INS_VFLCSB = 1899 -SYSZ_INS_VFLL = 1900 -SYSZ_INS_VFLLS = 1901 -SYSZ_INS_VFLNDB = 1902 -SYSZ_INS_VFLNSB = 1903 -SYSZ_INS_VFLPDB = 1904 -SYSZ_INS_VFLPSB = 1905 -SYSZ_INS_VFLR = 1906 -SYSZ_INS_VFLRD = 1907 -SYSZ_INS_VFM = 1908 -SYSZ_INS_VFMA = 1909 -SYSZ_INS_VFMADB = 1910 -SYSZ_INS_VFMASB = 1911 -SYSZ_INS_VFMAX = 1912 -SYSZ_INS_VFMAXDB = 1913 -SYSZ_INS_VFMAXSB = 1914 -SYSZ_INS_VFMDB = 1915 -SYSZ_INS_VFMIN = 1916 -SYSZ_INS_VFMINDB = 1917 -SYSZ_INS_VFMINSB = 1918 -SYSZ_INS_VFMS = 1919 -SYSZ_INS_VFMSB = 1920 -SYSZ_INS_VFMSDB = 1921 -SYSZ_INS_VFMSSB = 1922 -SYSZ_INS_VFNMA = 1923 -SYSZ_INS_VFNMADB = 1924 -SYSZ_INS_VFNMASB = 1925 -SYSZ_INS_VFNMS = 1926 -SYSZ_INS_VFNMSDB = 1927 -SYSZ_INS_VFNMSSB = 1928 -SYSZ_INS_VFPSO = 1929 -SYSZ_INS_VFPSODB = 1930 -SYSZ_INS_VFPSOSB = 1931 -SYSZ_INS_VFS = 1932 -SYSZ_INS_VFSDB = 1933 -SYSZ_INS_VFSQ = 1934 -SYSZ_INS_VFSQDB = 1935 -SYSZ_INS_VFSQSB = 1936 -SYSZ_INS_VFSSB = 1937 -SYSZ_INS_VFTCI = 1938 -SYSZ_INS_VFTCIDB = 1939 -SYSZ_INS_VFTCISB = 1940 -SYSZ_INS_VGBM = 1941 -SYSZ_INS_VGEF = 1942 -SYSZ_INS_VGEG = 1943 -SYSZ_INS_VGFM = 1944 -SYSZ_INS_VGFMA = 1945 -SYSZ_INS_VGFMAB = 1946 -SYSZ_INS_VGFMAF = 1947 -SYSZ_INS_VGFMAG = 1948 -SYSZ_INS_VGFMAH = 1949 -SYSZ_INS_VGFMB = 1950 -SYSZ_INS_VGFMF = 1951 -SYSZ_INS_VGFMG = 1952 -SYSZ_INS_VGFMH = 1953 -SYSZ_INS_VGM = 1954 -SYSZ_INS_VGMB = 1955 -SYSZ_INS_VGMF = 1956 -SYSZ_INS_VGMG = 1957 -SYSZ_INS_VGMH = 1958 -SYSZ_INS_VISTR = 1959 -SYSZ_INS_VISTRB = 1960 -SYSZ_INS_VISTRBS = 1961 -SYSZ_INS_VISTRF = 1962 -SYSZ_INS_VISTRFS = 1963 -SYSZ_INS_VISTRH = 1964 -SYSZ_INS_VISTRHS = 1965 -SYSZ_INS_VL = 1966 -SYSZ_INS_VLBB = 1967 -SYSZ_INS_VLC = 1968 -SYSZ_INS_VLCB = 1969 -SYSZ_INS_VLCF = 1970 -SYSZ_INS_VLCG = 1971 -SYSZ_INS_VLCH = 1972 -SYSZ_INS_VLDE = 1973 -SYSZ_INS_VLDEB = 1974 -SYSZ_INS_VLEB = 1975 -SYSZ_INS_VLED = 1976 -SYSZ_INS_VLEDB = 1977 -SYSZ_INS_VLEF = 1978 -SYSZ_INS_VLEG = 1979 -SYSZ_INS_VLEH = 1980 -SYSZ_INS_VLEIB = 1981 -SYSZ_INS_VLEIF = 1982 -SYSZ_INS_VLEIG = 1983 -SYSZ_INS_VLEIH = 1984 -SYSZ_INS_VLGV = 1985 -SYSZ_INS_VLGVB = 1986 -SYSZ_INS_VLGVF = 1987 -SYSZ_INS_VLGVG = 1988 -SYSZ_INS_VLGVH = 1989 -SYSZ_INS_VLIP = 1990 -SYSZ_INS_VLL = 1991 -SYSZ_INS_VLLEZ = 1992 -SYSZ_INS_VLLEZB = 1993 -SYSZ_INS_VLLEZF = 1994 -SYSZ_INS_VLLEZG = 1995 -SYSZ_INS_VLLEZH = 1996 -SYSZ_INS_VLLEZLF = 1997 -SYSZ_INS_VLM = 1998 -SYSZ_INS_VLP = 1999 -SYSZ_INS_VLPB = 2000 -SYSZ_INS_VLPF = 2001 -SYSZ_INS_VLPG = 2002 -SYSZ_INS_VLPH = 2003 -SYSZ_INS_VLR = 2004 -SYSZ_INS_VLREP = 2005 -SYSZ_INS_VLREPB = 2006 -SYSZ_INS_VLREPF = 2007 -SYSZ_INS_VLREPG = 2008 -SYSZ_INS_VLREPH = 2009 -SYSZ_INS_VLRL = 2010 -SYSZ_INS_VLRLR = 2011 -SYSZ_INS_VLVG = 2012 -SYSZ_INS_VLVGB = 2013 -SYSZ_INS_VLVGF = 2014 -SYSZ_INS_VLVGG = 2015 -SYSZ_INS_VLVGH = 2016 -SYSZ_INS_VLVGP = 2017 -SYSZ_INS_VMAE = 2018 -SYSZ_INS_VMAEB = 2019 -SYSZ_INS_VMAEF = 2020 -SYSZ_INS_VMAEH = 2021 -SYSZ_INS_VMAH = 2022 -SYSZ_INS_VMAHB = 2023 -SYSZ_INS_VMAHF = 2024 -SYSZ_INS_VMAHH = 2025 -SYSZ_INS_VMAL = 2026 -SYSZ_INS_VMALB = 2027 -SYSZ_INS_VMALE = 2028 -SYSZ_INS_VMALEB = 2029 -SYSZ_INS_VMALEF = 2030 -SYSZ_INS_VMALEH = 2031 -SYSZ_INS_VMALF = 2032 -SYSZ_INS_VMALH = 2033 -SYSZ_INS_VMALHB = 2034 -SYSZ_INS_VMALHF = 2035 -SYSZ_INS_VMALHH = 2036 -SYSZ_INS_VMALHW = 2037 -SYSZ_INS_VMALO = 2038 -SYSZ_INS_VMALOB = 2039 -SYSZ_INS_VMALOF = 2040 -SYSZ_INS_VMALOH = 2041 -SYSZ_INS_VMAO = 2042 -SYSZ_INS_VMAOB = 2043 -SYSZ_INS_VMAOF = 2044 -SYSZ_INS_VMAOH = 2045 -SYSZ_INS_VME = 2046 -SYSZ_INS_VMEB = 2047 -SYSZ_INS_VMEF = 2048 -SYSZ_INS_VMEH = 2049 -SYSZ_INS_VMH = 2050 -SYSZ_INS_VMHB = 2051 -SYSZ_INS_VMHF = 2052 -SYSZ_INS_VMHH = 2053 -SYSZ_INS_VML = 2054 -SYSZ_INS_VMLB = 2055 -SYSZ_INS_VMLE = 2056 -SYSZ_INS_VMLEB = 2057 -SYSZ_INS_VMLEF = 2058 -SYSZ_INS_VMLEH = 2059 -SYSZ_INS_VMLF = 2060 -SYSZ_INS_VMLH = 2061 -SYSZ_INS_VMLHB = 2062 -SYSZ_INS_VMLHF = 2063 -SYSZ_INS_VMLHH = 2064 -SYSZ_INS_VMLHW = 2065 -SYSZ_INS_VMLO = 2066 -SYSZ_INS_VMLOB = 2067 -SYSZ_INS_VMLOF = 2068 -SYSZ_INS_VMLOH = 2069 -SYSZ_INS_VMN = 2070 -SYSZ_INS_VMNB = 2071 -SYSZ_INS_VMNF = 2072 -SYSZ_INS_VMNG = 2073 -SYSZ_INS_VMNH = 2074 -SYSZ_INS_VMNL = 2075 -SYSZ_INS_VMNLB = 2076 -SYSZ_INS_VMNLF = 2077 -SYSZ_INS_VMNLG = 2078 -SYSZ_INS_VMNLH = 2079 -SYSZ_INS_VMO = 2080 -SYSZ_INS_VMOB = 2081 -SYSZ_INS_VMOF = 2082 -SYSZ_INS_VMOH = 2083 -SYSZ_INS_VMP = 2084 -SYSZ_INS_VMRH = 2085 -SYSZ_INS_VMRHB = 2086 -SYSZ_INS_VMRHF = 2087 -SYSZ_INS_VMRHG = 2088 -SYSZ_INS_VMRHH = 2089 -SYSZ_INS_VMRL = 2090 -SYSZ_INS_VMRLB = 2091 -SYSZ_INS_VMRLF = 2092 -SYSZ_INS_VMRLG = 2093 -SYSZ_INS_VMRLH = 2094 -SYSZ_INS_VMSL = 2095 -SYSZ_INS_VMSLG = 2096 -SYSZ_INS_VMSP = 2097 -SYSZ_INS_VMX = 2098 -SYSZ_INS_VMXB = 2099 -SYSZ_INS_VMXF = 2100 -SYSZ_INS_VMXG = 2101 -SYSZ_INS_VMXH = 2102 -SYSZ_INS_VMXL = 2103 -SYSZ_INS_VMXLB = 2104 -SYSZ_INS_VMXLF = 2105 -SYSZ_INS_VMXLG = 2106 -SYSZ_INS_VMXLH = 2107 -SYSZ_INS_VN = 2108 -SYSZ_INS_VNC = 2109 -SYSZ_INS_VNN = 2110 -SYSZ_INS_VNO = 2111 -SYSZ_INS_VNX = 2112 -SYSZ_INS_VO = 2113 -SYSZ_INS_VOC = 2114 -SYSZ_INS_VONE = 2115 -SYSZ_INS_VPDI = 2116 -SYSZ_INS_VPERM = 2117 -SYSZ_INS_VPK = 2118 -SYSZ_INS_VPKF = 2119 -SYSZ_INS_VPKG = 2120 -SYSZ_INS_VPKH = 2121 -SYSZ_INS_VPKLS = 2122 -SYSZ_INS_VPKLSF = 2123 -SYSZ_INS_VPKLSFS = 2124 -SYSZ_INS_VPKLSG = 2125 -SYSZ_INS_VPKLSGS = 2126 -SYSZ_INS_VPKLSH = 2127 -SYSZ_INS_VPKLSHS = 2128 -SYSZ_INS_VPKS = 2129 -SYSZ_INS_VPKSF = 2130 -SYSZ_INS_VPKSFS = 2131 -SYSZ_INS_VPKSG = 2132 -SYSZ_INS_VPKSGS = 2133 -SYSZ_INS_VPKSH = 2134 -SYSZ_INS_VPKSHS = 2135 -SYSZ_INS_VPKZ = 2136 -SYSZ_INS_VPOPCT = 2137 -SYSZ_INS_VPOPCTB = 2138 -SYSZ_INS_VPOPCTF = 2139 -SYSZ_INS_VPOPCTG = 2140 -SYSZ_INS_VPOPCTH = 2141 -SYSZ_INS_VPSOP = 2142 -SYSZ_INS_VREP = 2143 -SYSZ_INS_VREPB = 2144 -SYSZ_INS_VREPF = 2145 -SYSZ_INS_VREPG = 2146 -SYSZ_INS_VREPH = 2147 -SYSZ_INS_VREPI = 2148 -SYSZ_INS_VREPIB = 2149 -SYSZ_INS_VREPIF = 2150 -SYSZ_INS_VREPIG = 2151 -SYSZ_INS_VREPIH = 2152 -SYSZ_INS_VRP = 2153 -SYSZ_INS_VS = 2154 -SYSZ_INS_VSB = 2155 -SYSZ_INS_VSBCBI = 2156 -SYSZ_INS_VSBCBIQ = 2157 -SYSZ_INS_VSBI = 2158 -SYSZ_INS_VSBIQ = 2159 -SYSZ_INS_VSCBI = 2160 -SYSZ_INS_VSCBIB = 2161 -SYSZ_INS_VSCBIF = 2162 -SYSZ_INS_VSCBIG = 2163 -SYSZ_INS_VSCBIH = 2164 -SYSZ_INS_VSCBIQ = 2165 -SYSZ_INS_VSCEF = 2166 -SYSZ_INS_VSCEG = 2167 -SYSZ_INS_VSDP = 2168 -SYSZ_INS_VSEG = 2169 -SYSZ_INS_VSEGB = 2170 -SYSZ_INS_VSEGF = 2171 -SYSZ_INS_VSEGH = 2172 -SYSZ_INS_VSEL = 2173 -SYSZ_INS_VSF = 2174 -SYSZ_INS_VSG = 2175 -SYSZ_INS_VSH = 2176 -SYSZ_INS_VSL = 2177 -SYSZ_INS_VSLB = 2178 -SYSZ_INS_VSLDB = 2179 -SYSZ_INS_VSP = 2180 -SYSZ_INS_VSQ = 2181 -SYSZ_INS_VSRA = 2182 -SYSZ_INS_VSRAB = 2183 -SYSZ_INS_VSRL = 2184 -SYSZ_INS_VSRLB = 2185 -SYSZ_INS_VSRP = 2186 -SYSZ_INS_VST = 2187 -SYSZ_INS_VSTEB = 2188 -SYSZ_INS_VSTEF = 2189 -SYSZ_INS_VSTEG = 2190 -SYSZ_INS_VSTEH = 2191 -SYSZ_INS_VSTL = 2192 -SYSZ_INS_VSTM = 2193 -SYSZ_INS_VSTRC = 2194 -SYSZ_INS_VSTRCB = 2195 -SYSZ_INS_VSTRCBS = 2196 -SYSZ_INS_VSTRCF = 2197 -SYSZ_INS_VSTRCFS = 2198 -SYSZ_INS_VSTRCH = 2199 -SYSZ_INS_VSTRCHS = 2200 -SYSZ_INS_VSTRCZB = 2201 -SYSZ_INS_VSTRCZBS = 2202 -SYSZ_INS_VSTRCZF = 2203 -SYSZ_INS_VSTRCZFS = 2204 -SYSZ_INS_VSTRCZH = 2205 -SYSZ_INS_VSTRCZHS = 2206 -SYSZ_INS_VSTRL = 2207 -SYSZ_INS_VSTRLR = 2208 -SYSZ_INS_VSUM = 2209 -SYSZ_INS_VSUMB = 2210 -SYSZ_INS_VSUMG = 2211 -SYSZ_INS_VSUMGF = 2212 -SYSZ_INS_VSUMGH = 2213 -SYSZ_INS_VSUMH = 2214 -SYSZ_INS_VSUMQ = 2215 -SYSZ_INS_VSUMQF = 2216 -SYSZ_INS_VSUMQG = 2217 -SYSZ_INS_VTM = 2218 -SYSZ_INS_VTP = 2219 -SYSZ_INS_VUPH = 2220 -SYSZ_INS_VUPHB = 2221 -SYSZ_INS_VUPHF = 2222 -SYSZ_INS_VUPHH = 2223 -SYSZ_INS_VUPKZ = 2224 -SYSZ_INS_VUPL = 2225 -SYSZ_INS_VUPLB = 2226 -SYSZ_INS_VUPLF = 2227 -SYSZ_INS_VUPLH = 2228 -SYSZ_INS_VUPLHB = 2229 -SYSZ_INS_VUPLHF = 2230 -SYSZ_INS_VUPLHH = 2231 -SYSZ_INS_VUPLHW = 2232 -SYSZ_INS_VUPLL = 2233 -SYSZ_INS_VUPLLB = 2234 -SYSZ_INS_VUPLLF = 2235 -SYSZ_INS_VUPLLH = 2236 -SYSZ_INS_VX = 2237 -SYSZ_INS_VZERO = 2238 -SYSZ_INS_WCDGB = 2239 -SYSZ_INS_WCDLGB = 2240 -SYSZ_INS_WCGDB = 2241 -SYSZ_INS_WCLGDB = 2242 -SYSZ_INS_WFADB = 2243 -SYSZ_INS_WFASB = 2244 -SYSZ_INS_WFAXB = 2245 -SYSZ_INS_WFC = 2246 -SYSZ_INS_WFCDB = 2247 -SYSZ_INS_WFCEDB = 2248 -SYSZ_INS_WFCEDBS = 2249 -SYSZ_INS_WFCESB = 2250 -SYSZ_INS_WFCESBS = 2251 -SYSZ_INS_WFCEXB = 2252 -SYSZ_INS_WFCEXBS = 2253 -SYSZ_INS_WFCHDB = 2254 -SYSZ_INS_WFCHDBS = 2255 -SYSZ_INS_WFCHEDB = 2256 -SYSZ_INS_WFCHEDBS = 2257 -SYSZ_INS_WFCHESB = 2258 -SYSZ_INS_WFCHESBS = 2259 -SYSZ_INS_WFCHEXB = 2260 -SYSZ_INS_WFCHEXBS = 2261 -SYSZ_INS_WFCHSB = 2262 -SYSZ_INS_WFCHSBS = 2263 -SYSZ_INS_WFCHXB = 2264 -SYSZ_INS_WFCHXBS = 2265 -SYSZ_INS_WFCSB = 2266 -SYSZ_INS_WFCXB = 2267 -SYSZ_INS_WFDDB = 2268 -SYSZ_INS_WFDSB = 2269 -SYSZ_INS_WFDXB = 2270 -SYSZ_INS_WFIDB = 2271 -SYSZ_INS_WFISB = 2272 -SYSZ_INS_WFIXB = 2273 -SYSZ_INS_WFK = 2274 -SYSZ_INS_WFKDB = 2275 -SYSZ_INS_WFKEDB = 2276 -SYSZ_INS_WFKEDBS = 2277 -SYSZ_INS_WFKESB = 2278 -SYSZ_INS_WFKESBS = 2279 -SYSZ_INS_WFKEXB = 2280 -SYSZ_INS_WFKEXBS = 2281 -SYSZ_INS_WFKHDB = 2282 -SYSZ_INS_WFKHDBS = 2283 -SYSZ_INS_WFKHEDB = 2284 -SYSZ_INS_WFKHEDBS = 2285 -SYSZ_INS_WFKHESB = 2286 -SYSZ_INS_WFKHESBS = 2287 -SYSZ_INS_WFKHEXB = 2288 -SYSZ_INS_WFKHEXBS = 2289 -SYSZ_INS_WFKHSB = 2290 -SYSZ_INS_WFKHSBS = 2291 -SYSZ_INS_WFKHXB = 2292 -SYSZ_INS_WFKHXBS = 2293 -SYSZ_INS_WFKSB = 2294 -SYSZ_INS_WFKXB = 2295 -SYSZ_INS_WFLCDB = 2296 -SYSZ_INS_WFLCSB = 2297 -SYSZ_INS_WFLCXB = 2298 -SYSZ_INS_WFLLD = 2299 -SYSZ_INS_WFLLS = 2300 -SYSZ_INS_WFLNDB = 2301 -SYSZ_INS_WFLNSB = 2302 -SYSZ_INS_WFLNXB = 2303 -SYSZ_INS_WFLPDB = 2304 -SYSZ_INS_WFLPSB = 2305 -SYSZ_INS_WFLPXB = 2306 -SYSZ_INS_WFLRD = 2307 -SYSZ_INS_WFLRX = 2308 -SYSZ_INS_WFMADB = 2309 -SYSZ_INS_WFMASB = 2310 -SYSZ_INS_WFMAXB = 2311 -SYSZ_INS_WFMAXDB = 2312 -SYSZ_INS_WFMAXSB = 2313 -SYSZ_INS_WFMAXXB = 2314 -SYSZ_INS_WFMDB = 2315 -SYSZ_INS_WFMINDB = 2316 -SYSZ_INS_WFMINSB = 2317 -SYSZ_INS_WFMINXB = 2318 -SYSZ_INS_WFMSB = 2319 -SYSZ_INS_WFMSDB = 2320 -SYSZ_INS_WFMSSB = 2321 -SYSZ_INS_WFMSXB = 2322 -SYSZ_INS_WFMXB = 2323 -SYSZ_INS_WFNMADB = 2324 -SYSZ_INS_WFNMASB = 2325 -SYSZ_INS_WFNMAXB = 2326 -SYSZ_INS_WFNMSDB = 2327 -SYSZ_INS_WFNMSSB = 2328 -SYSZ_INS_WFNMSXB = 2329 -SYSZ_INS_WFPSODB = 2330 -SYSZ_INS_WFPSOSB = 2331 -SYSZ_INS_WFPSOXB = 2332 -SYSZ_INS_WFSDB = 2333 -SYSZ_INS_WFSQDB = 2334 -SYSZ_INS_WFSQSB = 2335 -SYSZ_INS_WFSQXB = 2336 -SYSZ_INS_WFSSB = 2337 -SYSZ_INS_WFSXB = 2338 -SYSZ_INS_WFTCIDB = 2339 -SYSZ_INS_WFTCISB = 2340 -SYSZ_INS_WFTCIXB = 2341 -SYSZ_INS_WLDEB = 2342 -SYSZ_INS_WLEDB = 2343 -SYSZ_INS_XSCH = 2344 -SYSZ_INS_ZAP = 2345 -SYSZ_INS_ENDING = 2346 - -SYSZ_GRP_INVALID = 0 -SYSZ_GRP_JUMP = 1 -SYSZ_GRP_DISTINCTOPS = 128 -SYSZ_GRP_FPEXTENSION = 129 -SYSZ_GRP_HIGHWORD = 130 -SYSZ_GRP_INTERLOCKEDACCESS1 = 131 -SYSZ_GRP_LOADSTOREONCOND = 132 -SYSZ_GRP_DFPPACKEDCONVERSION = 133 -SYSZ_GRP_DFPZONEDCONVERSION = 134 -SYSZ_GRP_ENHANCEDDAT2 = 135 -SYSZ_GRP_EXECUTIONHINT = 136 -SYSZ_GRP_GUARDEDSTORAGE = 137 -SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE = 138 -SYSZ_GRP_LOADANDTRAP = 139 -SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE = 140 -SYSZ_GRP_LOADSTOREONCOND2 = 141 -SYSZ_GRP_MESSAGESECURITYASSIST3 = 142 -SYSZ_GRP_MESSAGESECURITYASSIST4 = 143 -SYSZ_GRP_MESSAGESECURITYASSIST5 = 144 -SYSZ_GRP_MESSAGESECURITYASSIST7 = 145 -SYSZ_GRP_MESSAGESECURITYASSIST8 = 146 -SYSZ_GRP_MISCELLANEOUSEXTENSIONS = 147 -SYSZ_GRP_MISCELLANEOUSEXTENSIONS2 = 148 -SYSZ_GRP_NOVECTOR = 149 -SYSZ_GRP_POPULATIONCOUNT = 150 -SYSZ_GRP_PROCESSORASSIST = 151 -SYSZ_GRP_RESETREFERENCEBITSMULTIPLE = 152 -SYSZ_GRP_TRANSACTIONALEXECUTION = 153 -SYSZ_GRP_VECTOR = 154 -SYSZ_GRP_VECTORENHANCEMENTS1 = 155 -SYSZ_GRP_VECTORPACKEDDECIMAL = 156 -SYSZ_GRP_ENDING = 157 diff --git a/bindings/python/capstone/tms320c64x_const.py b/bindings/python/capstone/tms320c64x_const.py index 0117d83edb..0ca24b315c 100644 --- a/bindings/python/capstone/tms320c64x_const.py +++ b/bindings/python/capstone/tms320c64x_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [tms320c64x_const.py] TMS320C64X_OP_INVALID = 0 diff --git a/bindings/python/capstone/tricore_const.py b/bindings/python/capstone/tricore_const.py index 3353f32093..cb0fdf709e 100644 --- a/bindings/python/capstone/tricore_const.py +++ b/bindings/python/capstone/tricore_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [tricore_const.py] TRICORE_OP_INVALID = CS_OP_INVALID TRICORE_OP_REG = CS_OP_REG diff --git a/bindings/python/capstone/wasm_const.py b/bindings/python/capstone/wasm_const.py index 5aa4bf34e0..c2d08d4937 100644 --- a/bindings/python/capstone/wasm_const.py +++ b/bindings/python/capstone/wasm_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [wasm_const.py] WASM_OP_INVALID = 0 diff --git a/bindings/python/capstone/x86_const.py b/bindings/python/capstone/x86_const.py index ae3f93c30e..ef3e3acce5 100644 --- a/bindings/python/capstone/x86_const.py +++ b/bindings/python/capstone/x86_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.py] X86_REG_INVALID = 0 diff --git a/bindings/python/capstone/xcore_const.py b/bindings/python/capstone/xcore_const.py index b6c63978cd..3d32f65d2b 100644 --- a/bindings/python/capstone/xcore_const.py +++ b/bindings/python/capstone/xcore_const.py @@ -1,4 +1,4 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [xcore_const.py] XCORE_OP_INVALID = 0 diff --git a/bindings/python/cstest_py/src/cstest_py/compare.py b/bindings/python/cstest_py/src/cstest_py/compare.py index 7e679ec552..6200463e34 100644 --- a/bindings/python/cstest_py/src/cstest_py/compare.py +++ b/bindings/python/cstest_py/src/cstest_py/compare.py @@ -13,7 +13,7 @@ from capstone import mips_const from capstone import ppc_const from capstone import sparc_const -from capstone import sysz_const +from capstone import systemz_const from capstone import x86_const from capstone import xcore_const from capstone import tms320c64x_const @@ -52,7 +52,7 @@ def cs_const_getattr(identifier: str): attr = getattr(sparc_const, identifier, None) if attr is not None: return attr - attr = getattr(sysz_const, identifier, None) + attr = getattr(systemz_const, identifier, None) if attr is not None: return attr attr = getattr(x86_const, identifier, None) diff --git a/bindings/python/cstest_py/src/cstest_py/details.py b/bindings/python/cstest_py/src/cstest_py/details.py index e5236495b0..67f5e00989 100644 --- a/bindings/python/cstest_py/src/cstest_py/details.py +++ b/bindings/python/cstest_py/src/cstest_py/details.py @@ -69,7 +69,7 @@ from capstone.riscv_const import RISCV_OP_MEM, RISCV_OP_IMM, RISCV_OP_REG from capstone.sh_const import SH_OP_REG, SH_OP_MEM, SH_OP_IMM from capstone.sparc_const import SPARC_OP_REG, SPARC_OP_IMM, SPARC_OP_MEM -from capstone.sysz_const import SYSZ_OP_REG, SYSZ_OP_IMM, SYSZ_OP_MEM +from capstone.systemz_const import SYSTEMZ_OP_REG, SYSTEMZ_OP_IMM, SYSTEMZ_OP_MEM from capstone.tms320c64x_const import ( TMS320C64X_OP_REG, TMS320C64X_OP_REGPAIR, @@ -245,7 +245,7 @@ def compare_details(insn: CsInsn, expected: dict) -> bool: elif "xcore" in expected: return test_expected_xcore(actual, expected["xcore"]) elif "systemz" in expected: - return test_expected_sysz(actual, expected["systemz"]) + return test_expected_SystemZ(actual, expected["systemz"]) elif "sparc" in expected: return test_expected_sparc(actual, expected["sparc"]) elif "sh" in expected: @@ -1349,25 +1349,35 @@ def test_expected_mips(actual: CsInsn, expected: dict) -> bool: return True -def test_expected_sysz(actual: CsInsn, expected: dict) -> bool: +def test_expected_SystemZ(actual: CsInsn, expected: dict) -> bool: if "operands" not in expected: return True elif not compare_uint32( len(actual.operands), len(expected.get("operands")), "operands_count" ): return False + elif not compare_enum( + actual.format, expected.get("format"), "format" + ): + return False for aop, eop in zip(actual.operands, expected["operands"]): if not compare_enum(aop.type, eop.get("type"), "type"): return False + if not compare_enum(aop.access, eop.get("access"), "access"): + return False - if aop.type == SYSZ_OP_REG: + if aop.type == SYSTEMZ_OP_REG: if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): return False - elif aop.type == SYSZ_OP_IMM: + elif aop.type == SYSTEMZ_OP_IMM: if not compare_int64(aop.imm, eop.get("imm"), "imm"): return False - elif aop.type == SYSZ_OP_MEM: + if not compare_int64(aop.imm_width, eop.get("imm_width"), "imm_width"): + return False + elif aop.type == SYSTEMZ_OP_MEM: + if not compare_enum(aop.mem.am, eop.get("mem_am"), "mem_am"): + return False if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"): return False if not compare_reg( diff --git a/bindings/python/tests/test_iter.py b/bindings/python/tests/test_iter.py index 26ae93bc43..0303a13ce3 100755 --- a/bindings/python/tests/test_iter.py +++ b/bindings/python/tests/test_iter.py @@ -56,7 +56,7 @@ (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", CS_OPT_SYNTAX_NOREGNAME), (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", None), (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", None), - (CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", None), + (CS_ARCH_SYSTEMZ, 0, SYSZ_CODE, "SystemZ", None), (CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None), (CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K (68040)", None), (CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None), diff --git a/bindings/python/tests/test_lite.py b/bindings/python/tests/test_lite.py index 524372043f..2b0791e27d 100755 --- a/bindings/python/tests/test_lite.py +++ b/bindings/python/tests/test_lite.py @@ -50,7 +50,7 @@ (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", CS_OPT_SYNTAX_NOREGNAME), (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", None), (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", None), - (CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", None), + (CS_ARCH_SYSTEMZ, 0, SYSZ_CODE, "SystemZ", None), (CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None), (CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K (68040)", None), (CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None), diff --git a/cmake.sh b/cmake.sh index 23f765ca5f..819d708dae 100755 --- a/cmake.sh +++ b/cmake.sh @@ -31,7 +31,7 @@ case $1 in ARCH=SPARC ;; SystemZ) - ARCH=SYSZ + ARCH=SYSTEMZ ;; XCore) ARCH=XCORE diff --git a/contrib/sysz_update/0001-capstone-generate-GenRegisterInfo.inc.patch b/contrib/sysz_update/0001-capstone-generate-GenRegisterInfo.inc.patch deleted file mode 100644 index b51aa515ab..0000000000 --- a/contrib/sysz_update/0001-capstone-generate-GenRegisterInfo.inc.patch +++ /dev/null @@ -1,338 +0,0 @@ -From 5d631cb16e7ba5dd0380ff1ee9dda192b1cdad18 Mon Sep 17 00:00:00 2001 -From: mephi42 -Date: Tue, 7 Aug 2018 17:02:40 +0200 -Subject: [PATCH 1/7] capstone: generate *GenRegisterInfo.inc - ---- - utils/TableGen/RegisterInfoEmitter.cpp | 130 ++++++++++++++++++++++--- - 1 file changed, 115 insertions(+), 15 deletions(-) - -diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp -index 49016cca799..6ebb7148b1b 100644 ---- a/utils/TableGen/RegisterInfoEmitter.cpp -+++ b/utils/TableGen/RegisterInfoEmitter.cpp -@@ -99,6 +99,12 @@ private: - - } // end anonymous namespace - -+#ifdef CAPSTONE -+#define NAME_PREFIX Target.getName() << "_" << -+#else -+#define NAME_PREFIX -+#endif -+ - // runEnums - Print out enum values for all of the registers. - void RegisterInfoEmitter::runEnums(raw_ostream &OS, - CodeGenTarget &Target, CodeGenRegBank &Bank) { -@@ -107,13 +113,22 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, - // Register enums are stored as uint16_t in the tables. Make sure we'll fit. - assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); - -+#ifndef CAPSTONE - StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace"); -+#endif - - emitSourceFileHeader("Target Register Enum Values", OS); - -+#ifdef CAPSTONE -+ OS << "/* Capstone Disassembly Engine */\n" -+ "/* By Nguyen Anh Quynh , 2013-2015 */\n" -+ "\n"; -+#endif -+ - OS << "\n#ifdef GET_REGINFO_ENUM\n"; - OS << "#undef GET_REGINFO_ENUM\n\n"; - -+#ifndef CAPSTONE - OS << "namespace llvm {\n\n"; - - OS << "class MCRegisterClass;\n" -@@ -122,16 +137,20 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, - - if (!Namespace.empty()) - OS << "namespace " << Namespace << " {\n"; -- OS << "enum {\n NoRegister,\n"; -+#endif -+ -+ OS << "enum {\n " << NAME_PREFIX "NoRegister,\n"; - - for (const auto &Reg : Registers) -- OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; -+ OS << " " << NAME_PREFIX Reg.getName() << " = " << Reg.EnumValue << ",\n"; - assert(Registers.size() == Registers.back().EnumValue && - "Register enum value mismatch!"); -- OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; -+ OS << " " << NAME_PREFIX "NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; - OS << "};\n"; -+#ifndef CAPSTONE - if (!Namespace.empty()) - OS << "} // end namespace " << Namespace << "\n"; -+#endif - - const auto &RegisterClasses = Bank.getRegClasses(); - if (!RegisterClasses.empty()) { -@@ -140,18 +159,29 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, - assert(RegisterClasses.size() <= 0xffff && - "Too many register classes to fit in tables"); - -- OS << "\n// Register classes\n\n"; -+ OS << "\n// Register classes\n"; -+#ifndef CAPSTONE -+ OS << "\n"; - if (!Namespace.empty()) - OS << "namespace " << Namespace << " {\n"; -+#endif - OS << "enum {\n"; - for (const auto &RC : RegisterClasses) -- OS << " " << RC.getName() << "RegClassID" -+ OS << " " << NAME_PREFIX RC.getName() << "RegClassID" - << " = " << RC.EnumValue << ",\n"; -- OS << "\n };\n"; -+#ifdef CAPSTONE -+ OS -+#else -+ OS << "\n " -+#endif -+ << "};\n"; -+#ifndef CAPSTONE - if (!Namespace.empty()) - OS << "} // end namespace " << Namespace << "\n\n"; -+#endif - } - -+#ifndef CAPSTONE - const std::vector &RegAltNameIndices = Target.getRegAltNameIndices(); - // If the only definition is the default NoRegAltName, we don't need to - // emit anything. -@@ -182,8 +212,11 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, - if (!Namespace.empty()) - OS << "} // end namespace " << Namespace << "\n\n"; - } -+#endif - -+#ifndef CAPSTONE - OS << "} // end namespace llvm\n\n"; -+#endif - OS << "#endif // GET_REGINFO_ENUM\n\n"; - } - -@@ -830,7 +863,9 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, - - const auto &Regs = RegBank.getRegisters(); - -+#ifndef CAPSTONE - auto &SubRegIndices = RegBank.getSubRegIndices(); -+#endif - // The lists of sub-registers and super-registers go in the same array. That - // allows us to share suffixes. - typedef std::vector RegVec; -@@ -922,25 +957,40 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, - LaneMaskSeqs.layout(); - SubRegIdxSeqs.layout(); - -+#ifndef CAPSTONE - OS << "namespace llvm {\n\n"; -+#endif - - const std::string &TargetName = Target.getName(); - - // Emit the shared table of differential lists. -- OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; -+#ifdef CAPSTONE -+ OS << "static" -+#else -+ OS << "extern" -+#endif -+ << " const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; - DiffSeqs.emit(OS, printDiff16); - OS << "};\n\n"; - -+#ifndef CAPSTONE - // Emit the shared table of regunit lane mask sequences. - OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; - LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()"); - OS << "};\n\n"; -+#endif - - // Emit the table of sub-register indexes. -- OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; -+#ifdef CAPSTONE -+ OS << "static" -+#else -+ OS << "extern" -+#endif -+ << " const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; - SubRegIdxSeqs.emit(OS, printSubRegIndex); - OS << "};\n\n"; - -+#ifndef CAPSTONE - // Emit the table of sub-register index sizes. - OS << "extern const MCRegisterInfo::SubRegCoveredBits " - << TargetName << "SubRegIdxRanges[] = {\n"; -@@ -950,14 +1000,22 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, - << Idx.getName() << "\n"; - } - OS << "};\n\n"; -+#endif - - // Emit the string table. - RegStrings.layout(); -+#ifndef CAPSTONE - OS << "extern const char " << TargetName << "RegStrings[] = {\n"; - RegStrings.emit(OS, printChar); - OS << "};\n\n"; -+#endif - -- OS << "extern const MCRegisterDesc " << TargetName -+#ifdef CAPSTONE -+ OS << "static" -+#else -+ OS << "extern" -+#endif -+ << " const MCRegisterDesc " << TargetName - << "RegDesc[] = { // Descriptors\n"; - OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; - -@@ -973,6 +1031,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, - } - OS << "};\n\n"; // End of register descriptors... - -+#ifndef CAPSTONE - // Emit the table of register unit roots. Each regunit has one or two root - // registers. - OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; -@@ -986,11 +1045,14 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, - OS << " },\n"; - } - OS << "};\n\n"; -+#endif - - const auto &RegisterClasses = RegBank.getRegClasses(); - - // Loop over all of the register classes... emitting each one. -+#ifndef CAPSTONE - OS << "namespace { // Register classes...\n"; -+#endif - - SequenceToOffsetTable RegClassStrings; - -@@ -1005,15 +1067,28 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, - - // Emit the register list now. - OS << " // " << Name << " Register Class...\n" -- << " const MCPhysReg " << Name -+ << " " -+#ifdef CAPSTONE -+ << "static " -+#endif -+ << "const MCPhysReg " << Name - << "[] = {\n "; - for (Record *Reg : Order) { -- OS << getQualifiedName(Reg) << ", "; -+#ifdef CAPSTONE -+ OS << NAME_PREFIX Reg->getName() -+#else -+ OS << getQualifiedName(Reg) -+#endif -+ << ", "; - } - OS << "\n };\n\n"; - - OS << " // " << Name << " Bit set.\n" -- << " const uint8_t " << Name -+ << " " -+#ifdef CAPSTONE -+ << "static " -+#endif -+ << "const uint8_t " << Name - << "Bits[] = {\n "; - BitVectorEmitter BVE; - for (Record *Reg : Order) { -@@ -1023,14 +1098,23 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, - OS << "\n };\n\n"; - - } -+#ifndef CAPSTONE - OS << "} // end anonymous namespace\n\n"; -+#endif - - RegClassStrings.layout(); -+#ifndef CAPSTONE - OS << "extern const char " << TargetName << "RegClassStrings[] = {\n"; - RegClassStrings.emit(OS, printChar); - OS << "};\n\n"; -+#endif - -- OS << "extern const MCRegisterClass " << TargetName -+#ifdef CAPSTONE -+ OS << "static" -+#else -+ OS << "extern" -+#endif -+ << " const MCRegisterClass " << TargetName - << "MCRegisterClasses[] = {\n"; - - for (const auto &RC : RegisterClasses) { -@@ -1041,7 +1125,12 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, - OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " - << RegClassStrings.get(RC.getName()) << ", " - << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " -- << RC.getQualifiedName() + "RegClassID" << ", " -+#ifdef CAPSTONE -+ << NAME_PREFIX RC.getName() -+#else -+ << RC.getQualifiedName() -+#endif -+ << "RegClassID" << ", " - << RegSize/8 << ", " - << RC.CopyCost << ", " - << ( RC.Allocatable ? "true" : "false" ) << " },\n"; -@@ -1049,6 +1138,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, - - OS << "};\n\n"; - -+#ifndef CAPSTONE - EmitRegMappingTables(OS, Regs, false); - - // Emit Reg encoding table -@@ -1067,7 +1157,9 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, - OS << " " << Value << ",\n"; - } - OS << "};\n"; // End of HW encoding table -+#endif - -+#ifndef CAPSTONE - // MCRegisterInfo initialization routine. - OS << "static inline void Init" << TargetName - << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " -@@ -1088,7 +1180,12 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, - OS << "}\n\n"; - - OS << "} // end namespace llvm\n\n"; -- OS << "#endif // GET_REGINFO_MC_DESC\n\n"; -+#endif -+ OS << "#endif // GET_REGINFO_MC_DESC\n" -+#ifndef CAPSTONE -+ << "\n" -+#endif -+ ; - } - - void -@@ -1568,10 +1665,13 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, - - void RegisterInfoEmitter::run(raw_ostream &OS) { - CodeGenRegBank &RegBank = Target.getRegBank(); -+ - runEnums(OS, Target, RegBank); - runMCDesc(OS, Target, RegBank); -+#ifndef CAPSTONE - runTargetHeader(OS, Target, RegBank); - runTargetDesc(OS, Target, RegBank); -+#endif - - if (RegisterInfoDebug) - debugDump(errs()); --- -2.19.1 - diff --git a/contrib/sysz_update/0002-capstone-generate-GenSubtargetInfo.inc.patch b/contrib/sysz_update/0002-capstone-generate-GenSubtargetInfo.inc.patch deleted file mode 100644 index 56ad28256c..0000000000 --- a/contrib/sysz_update/0002-capstone-generate-GenSubtargetInfo.inc.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 46ca491e1bbbc9ace2a91fe6a7b112c83b9b88cc Mon Sep 17 00:00:00 2001 -From: mephi42 -Date: Tue, 7 Aug 2018 17:42:59 +0200 -Subject: [PATCH 2/7] capstone: generate *GenSubtargetInfo.inc - ---- - utils/TableGen/SubtargetEmitter.cpp | 28 +++++++++++++++++++++++++++- - 1 file changed, 27 insertions(+), 1 deletion(-) - -diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp -index c5da8d8142f..98ab3240472 100644 ---- a/utils/TableGen/SubtargetEmitter.cpp -+++ b/utils/TableGen/SubtargetEmitter.cpp -@@ -147,7 +147,9 @@ void SubtargetEmitter::Enumeration(raw_ostream &OS) { - if (N > MAX_SUBTARGET_FEATURES) - PrintFatalError("Too many subtarget features! Bump MAX_SUBTARGET_FEATURES."); - -+#ifndef CAPSTONE - OS << "namespace " << Target << " {\n"; -+#endif - - // Open enumeration. - OS << "enum {\n"; -@@ -158,12 +160,22 @@ void SubtargetEmitter::Enumeration(raw_ostream &OS) { - Record *Def = DefList[i]; - - // Get and emit name -- OS << " " << Def->getName() << " = " << i << ",\n"; -+ OS << " " -+#ifdef CAPSTONE -+ << Target << "_" -+#endif -+ << Def->getName() << " = " -+#ifdef CAPSTONE -+ << "1ULL << " -+#endif -+ << i << ",\n"; - } - - // Close enumeration and namespace - OS << "};\n"; -+#ifndef CAPSTONE - OS << "} // end namespace " << Target << "\n"; -+#endif - } - - // -@@ -1709,14 +1721,27 @@ void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) { - void SubtargetEmitter::run(raw_ostream &OS) { - emitSourceFileHeader("Subtarget Enumeration Source Fragment", OS); - -+#ifdef CAPSTONE -+ OS << "/* Capstone Disassembly Engine, http://www.capstone-engine.org */\n" -+ "/* By Nguyen Anh Quynh , 2013-2015 */\n" -+ "\n"; -+#endif -+ - OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n"; - OS << "#undef GET_SUBTARGETINFO_ENUM\n\n"; - -+#ifndef CAPSTONE - OS << "namespace llvm {\n"; -+#endif - Enumeration(OS); -+#ifdef CAPSTONE -+ OS << "\n"; -+#else - OS << "} // end namespace llvm\n\n"; -+#endif - OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n"; - -+#ifndef CAPSTONE - OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n"; - OS << "#undef GET_SUBTARGETINFO_MC_DESC\n\n"; - -@@ -1857,6 +1882,7 @@ void SubtargetEmitter::run(raw_ostream &OS) { - OS << "} // end namespace llvm\n\n"; - - OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n"; -+#endif - } - - namespace llvm { --- -2.19.1 - diff --git a/contrib/sysz_update/0003-capstone-generate-GenInstrInfo.inc.patch b/contrib/sysz_update/0003-capstone-generate-GenInstrInfo.inc.patch deleted file mode 100644 index 2baa59fc9c..0000000000 --- a/contrib/sysz_update/0003-capstone-generate-GenInstrInfo.inc.patch +++ /dev/null @@ -1,130 +0,0 @@ -From a73fe8ac18d3ca81fa7a8d8c404cd7e0faf92ddc Mon Sep 17 00:00:00 2001 -From: mephi42 -Date: Tue, 7 Aug 2018 17:59:43 +0200 -Subject: [PATCH 3/7] capstone: generate *GenInstrInfo.inc - ---- - utils/TableGen/InstrInfoEmitter.cpp | 49 ++++++++++++++++++++++++++--- - 1 file changed, 44 insertions(+), 5 deletions(-) - -diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp -index 0aff1aa6f94..2f3a2729262 100644 ---- a/utils/TableGen/InstrInfoEmitter.cpp -+++ b/utils/TableGen/InstrInfoEmitter.cpp -@@ -92,6 +92,7 @@ private: - - } // end anonymous namespace - -+#ifndef CAPSTONE - static void PrintDefList(const std::vector &Uses, - unsigned Num, raw_ostream &OS) { - OS << "static const MCPhysReg ImplicitList" << Num << "[] = { "; -@@ -99,6 +100,7 @@ static void PrintDefList(const std::vector &Uses, - OS << getQualifiedName(U) << ", "; - OS << "0 };\n"; - } -+#endif - - //===----------------------------------------------------------------------===// - // Operand Info Emission. -@@ -426,8 +428,17 @@ void InstrInfoEmitter::emitTIIHelperMethods(raw_ostream &OS) { - // run - Emit the main instruction description records for the target... - void InstrInfoEmitter::run(raw_ostream &OS) { - emitSourceFileHeader("Target Instruction Enum Values and Descriptors", OS); -+ -+#ifdef CAPSTONE -+ OS << "/* Capstone Disassembly Engine */\n" -+ "/* By Nguyen Anh Quynh , 2013-2015 */\n" -+ "\n" -+ "\n"; -+#endif -+ - emitEnums(OS); - -+#ifndef CAPSTONE - OS << "#ifdef GET_INSTRINFO_MC_DESC\n"; - OS << "#undef GET_INSTRINFO_MC_DESC\n"; - -@@ -545,6 +556,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) { - emitOperandTypesEnum(OS, Target); - - emitMCIIHelperMethods(OS); -+#endif - } - - void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, -@@ -659,7 +671,9 @@ void InstrInfoEmitter::emitEnums(raw_ostream &OS) { - OS << "#ifdef GET_INSTRINFO_ENUM\n"; - OS << "#undef GET_INSTRINFO_ENUM\n"; - -+#ifndef CAPSTONE - OS << "namespace llvm {\n\n"; -+#endif - - CodeGenTarget Target(Records); - -@@ -669,17 +683,39 @@ void InstrInfoEmitter::emitEnums(raw_ostream &OS) { - if (Namespace.empty()) - PrintFatalError("No instructions defined!"); - -+#ifndef CAPSTONE - OS << "namespace " << Namespace << " {\n"; -- OS << " enum {\n"; -+#endif -+#ifdef CAPSTONE -+ OS << "\n" -+#else -+ OS << " " -+#endif -+ << "enum {\n"; - unsigned Num = 0; - for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) -- OS << " " << Inst->TheDef->getName() << "\t= " << Num++ << ",\n"; -- OS << " INSTRUCTION_LIST_END = " << Num << "\n"; -+ OS << " " -+#ifdef CAPSTONE -+ << Target.getName() << "_" -+#endif -+ << Inst->TheDef->getName() << "\t= " << Num++ << ",\n"; -+ OS << " " -+#ifdef CAPSTONE -+ << Target.getName() << "_" -+#endif -+ << "INSTRUCTION_LIST_END = " << Num << "\n"; - OS << " };\n\n"; -+#ifndef CAPSTONE - OS << "} // end " << Namespace << " namespace\n"; - OS << "} // end llvm namespace\n"; -- OS << "#endif // GET_INSTRINFO_ENUM\n\n"; -- -+#endif -+ OS << "#endif // GET_INSTRINFO_ENUM\n" -+#ifndef CAPSTONE -+ << "\n" -+#endif -+ ; -+ -+#ifndef CAPSTONE - OS << "#ifdef GET_INSTRINFO_SCHED_ENUM\n"; - OS << "#undef GET_INSTRINFO_SCHED_ENUM\n"; - OS << "namespace llvm {\n\n"; -@@ -696,13 +732,16 @@ void InstrInfoEmitter::emitEnums(raw_ostream &OS) { - OS << "} // end llvm namespace\n"; - - OS << "#endif // GET_INSTRINFO_SCHED_ENUM\n\n"; -+#endif - } - - namespace llvm { - - void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) { - InstrInfoEmitter(RK).run(OS); -+#ifndef CAPSTONE - EmitMapTable(RK, OS); -+#endif - } - - } // end llvm namespace --- -2.19.1 - diff --git a/contrib/sysz_update/0004-capstone-generate-GenDisassemblerTables.inc.patch b/contrib/sysz_update/0004-capstone-generate-GenDisassemblerTables.inc.patch deleted file mode 100644 index 0002b81b4d..0000000000 --- a/contrib/sysz_update/0004-capstone-generate-GenDisassemblerTables.inc.patch +++ /dev/null @@ -1,472 +0,0 @@ -From 29da4c6929679b8ac4019767ab4ebcd83c9894b4 Mon Sep 17 00:00:00 2001 -From: mephi42 -Date: Tue, 7 Aug 2018 18:20:17 +0200 -Subject: [PATCH 4/7] capstone: generate *GenDisassemblerTables.inc - ---- - utils/TableGen/DisassemblerEmitter.cpp | 12 +- - utils/TableGen/FixedLenDecoderEmitter.cpp | 248 ++++++++++++++++++++-- - 2 files changed, 239 insertions(+), 21 deletions(-) - -diff --git a/utils/TableGen/DisassemblerEmitter.cpp b/utils/TableGen/DisassemblerEmitter.cpp -index b99a0a973a2..2ac6d89645c 100644 ---- a/utils/TableGen/DisassemblerEmitter.cpp -+++ b/utils/TableGen/DisassemblerEmitter.cpp -@@ -106,6 +106,11 @@ extern void EmitFixedLenDecoder(RecordKeeper &RK, raw_ostream &OS, - void EmitDisassembler(RecordKeeper &Records, raw_ostream &OS) { - CodeGenTarget Target(Records); - emitSourceFileHeader(" * " + Target.getName().str() + " Disassembler", OS); -+#ifdef CAPSTONE -+ OS << "/* Capstone Disassembly Engine */\n" -+ "/* By Nguyen Anh Quynh , 2013-2015 */\n" -+ "\n"; -+#endif - - // X86 uses a custom disassembler. - if (Target.getName() == "X86") { -@@ -150,7 +155,12 @@ void EmitDisassembler(RecordKeeper &Records, raw_ostream &OS) { - } - - EmitFixedLenDecoder(Records, OS, Target.getName(), -- "if (", " == MCDisassembler::Fail)", -+ "if (", -+#ifdef CAPSTONE -+ " == MCDisassembler_Fail)", -+#else -+ " == MCDisassembler::Fail)", -+#endif - "MCDisassembler::Success", "MCDisassembler::Fail", ""); - } - -diff --git a/utils/TableGen/FixedLenDecoderEmitter.cpp b/utils/TableGen/FixedLenDecoderEmitter.cpp -index fcecc764d44..36845d960d8 100644 ---- a/utils/TableGen/FixedLenDecoderEmitter.cpp -+++ b/utils/TableGen/FixedLenDecoderEmitter.cpp -@@ -730,7 +730,13 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, - ++I; - unsigned Start = *I++; - unsigned Len = *I++; -- OS.indent(Indentation) << "MCD::OPC_ExtractField, " << Start << ", " -+ OS.indent(Indentation) -+#ifdef CAPSTONE -+ << "MCD_OPC_ExtractField" -+#else -+ << "MCD::OPC_ExtractField" -+#endif -+ << ", " << Start << ", " - << Len << ", // Inst{"; - if (Len > 1) - OS << (Start + Len - 1) << "-"; -@@ -739,7 +745,13 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, - } - case MCD::OPC_FilterValue: { - ++I; -- OS.indent(Indentation) << "MCD::OPC_FilterValue, "; -+ OS.indent(Indentation) -+#ifdef CAPSTONE -+ << "MCD_OPC_FilterValue" -+#else -+ << "MCD::OPC_FilterValue" -+#endif -+ << ", "; - // The filter value is ULEB128 encoded. - while (*I >= 128) - OS << (unsigned)*I++ << ", "; -@@ -759,7 +771,13 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, - ++I; - unsigned Start = *I++; - unsigned Len = *I++; -- OS.indent(Indentation) << "MCD::OPC_CheckField, " << Start << ", " -+ OS.indent(Indentation) -+#ifdef CAPSTONE -+ << "MCD_OPC_CheckField" -+#else -+ << "MCD::OPC_CheckField" -+#endif -+ << ", " << Start << ", " - << Len << ", ";// << Val << ", " << NumToSkip << ",\n"; - // ULEB128 encoded field value. - for (; *I >= 128; ++I) -@@ -777,7 +795,13 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, - } - case MCD::OPC_CheckPredicate: { - ++I; -- OS.indent(Indentation) << "MCD::OPC_CheckPredicate, "; -+ OS.indent(Indentation) -+#ifdef CAPSTONE -+ << "MCD_OPC_CheckPredicate" -+#else -+ << "MCD::OPC_CheckPredicate" -+#endif -+ << ", "; - for (; *I >= 128; ++I) - OS << (unsigned)*I << ", "; - OS << (unsigned)*I++ << ", "; -@@ -803,7 +827,13 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, - && "ULEB128 value too large!"); - // Decode the Opcode value. - unsigned Opc = decodeULEB128(Buffer); -- OS.indent(Indentation) << "MCD::OPC_" << (IsTry ? "Try" : "") -+ OS.indent(Indentation) -+#ifdef CAPSTONE -+ << "MCD_OPC_" -+#else -+ << "MCD::OPC_" -+#endif -+ << (IsTry ? "Try" : "") - << "Decode, "; - for (p = Buffer; *p >= 128; ++p) - OS << (unsigned)*p << ", "; -@@ -837,7 +867,12 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, - } - case MCD::OPC_SoftFail: { - ++I; -- OS.indent(Indentation) << "MCD::OPC_SoftFail"; -+ OS.indent(Indentation) -+#ifdef CAPSTONE -+ << "MCD_OPC_SoftFail"; -+#else -+ << "MCD::OPC_SoftFail"; -+#endif - // Positive mask - uint64_t Value = 0; - unsigned Shift = 0; -@@ -869,7 +904,13 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, - } - case MCD::OPC_Fail: { - ++I; -- OS.indent(Indentation) << "MCD::OPC_Fail,\n"; -+ OS.indent(Indentation) -+#ifdef CAPSTONE -+ << "MCD_OPC_Fail" -+#else -+ << "MCD::OPC_Fail" -+#endif -+ << ",\n"; - break; - } - } -@@ -884,23 +925,46 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, - void FixedLenDecoderEmitter:: - emitPredicateFunction(formatted_raw_ostream &OS, PredicateSet &Predicates, - unsigned Indentation) const { -+#ifdef CAPSTONE -+ OS.indent(Indentation) << "static bool getbool(uint64_t b)\n"; -+ OS.indent(Indentation) << "{\n"; -+ OS.indent(Indentation) << "\treturn b != 0;\n"; -+ OS.indent(Indentation) << "}\n\n"; -+#endif -+ - // The predicate function is just a big switch statement based on the - // input predicate index. - OS.indent(Indentation) << "static bool checkDecoderPredicate(unsigned Idx, " -+#ifdef CAPSTONE -+ << "uint64_t Bits)\n{\n"; -+#else - << "const FeatureBitset& Bits) {\n"; -+#endif - Indentation += 2; - if (!Predicates.empty()) { - OS.indent(Indentation) << "switch (Idx) {\n"; -- OS.indent(Indentation) << "default: llvm_unreachable(\"Invalid index!\");\n"; -+ OS.indent(Indentation) << "default: " -+#ifdef CAPSTONE -+ << "// " -+#endif -+ << "llvm_unreachable(\"Invalid index!\");\n"; - unsigned Index = 0; - for (const auto &Predicate : Predicates) { - OS.indent(Indentation) << "case " << Index++ << ":\n"; -- OS.indent(Indentation+2) << "return (" << Predicate << ");\n"; -+ OS.indent(Indentation+2) << "return " -+#ifdef CAPSTONE -+ << "getbool" -+#endif -+ << "(" << Predicate << ");\n"; - } - OS.indent(Indentation) << "}\n"; - } else { - // No case statement to emit -- OS.indent(Indentation) << "llvm_unreachable(\"Invalid index!\");\n"; -+ OS.indent(Indentation) -+#ifdef CAPSTONE -+ << "// " -+#endif -+ << "llvm_unreachable(\"Invalid index!\");\n"; - } - Indentation -= 2; - OS.indent(Indentation) << "}\n\n"; -@@ -911,23 +975,39 @@ emitDecoderFunction(formatted_raw_ostream &OS, DecoderSet &Decoders, - unsigned Indentation) const { - // The decoder function is just a big switch statement based on the - // input decoder index. -+#ifdef CAPSTONE -+#define EDF_EOL " \\\n" -+ OS.indent(Indentation) << "#define DecodeToMCInst(fname,fieldname, InsnType) \\\n"; -+ OS.indent(Indentation) << "static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \\\n"; -+ OS.indent(Indentation) << " uint64_t Address, const void *Decoder) \\\n"; -+ OS.indent(Indentation) << "{ \\\n"; -+#else -+#define EDF_EOL "\n" - OS.indent(Indentation) << "template\n"; - OS.indent(Indentation) << "static DecodeStatus decodeToMCInst(DecodeStatus S," - << " unsigned Idx, InsnType insn, MCInst &MI,\n"; - OS.indent(Indentation) << " uint64_t " - << "Address, const void *Decoder, bool &DecodeComplete) {\n"; -+#endif - Indentation += 2; -+#ifndef CAPSTONE - OS.indent(Indentation) << "DecodeComplete = true;\n"; -- OS.indent(Indentation) << "InsnType tmp;\n"; -- OS.indent(Indentation) << "switch (Idx) {\n"; -- OS.indent(Indentation) << "default: llvm_unreachable(\"Invalid index!\");\n"; -+#endif -+ OS.indent(Indentation) << "InsnType tmp;" EDF_EOL; -+ OS.indent(Indentation) << "switch (Idx) {" EDF_EOL; -+ OS.indent(Indentation) << "default:" -+#ifndef CAPSTONE -+ << " llvm_unreachable(\"Invalid index!\");\n"; -+#else -+ << " \\\n"; -+#endif - unsigned Index = 0; - for (const auto &Decoder : Decoders) { -- OS.indent(Indentation) << "case " << Index++ << ":\n"; -+ OS.indent(Indentation) << "case " << Index++ << ":" EDF_EOL; - OS << Decoder; -- OS.indent(Indentation+2) << "return S;\n"; -+ OS.indent(Indentation+2) << "return S;" EDF_EOL; - } -- OS.indent(Indentation) << "}\n"; -+ OS.indent(Indentation) << "}" EDF_EOL; - Indentation -= 2; - OS.indent(Indentation) << "}\n\n"; - } -@@ -1054,16 +1134,21 @@ void FilterChooser::emitBinaryParser(raw_ostream &o, unsigned &Indentation, - const std::string &Decoder = OpInfo.Decoder; - - if (OpInfo.numFields() != 1) -- o.indent(Indentation) << "tmp = 0;\n"; -+ o.indent(Indentation) << "tmp = 0;" EDF_EOL; - - for (const EncodingField &EF : OpInfo) { - o.indent(Indentation) << "tmp "; - if (OpInfo.numFields() != 1) o << '|'; -- o << "= fieldFromInstruction" -+ o << "= " -+#ifdef CAPSTONE -+ << "fieldname" -+#else -+ << "fieldFromInstruction" -+#endif - << "(insn, " << EF.Base << ", " << EF.Width << ')'; - if (OpInfo.numFields() != 1 || EF.Offset != 0) - o << " << " << EF.Offset; -- o << ";\n"; -+ o << ";" EDF_EOL; - } - - if (Decoder != "") { -@@ -1071,8 +1156,12 @@ void FilterChooser::emitBinaryParser(raw_ostream &o, unsigned &Indentation, - o.indent(Indentation) << Emitter->GuardPrefix << Decoder - << "(MI, tmp, Address, Decoder)" - << Emitter->GuardPostfix -+#ifdef CAPSTONE -+ << " return MCDisassembler_Fail; \\\n"; -+#else - << " { " << (OpHasCompleteDecoder ? "" : "DecodeComplete = false; ") - << "return MCDisassembler::Fail; }\n"; -+#endif - } else { - OpHasCompleteDecoder = true; - o.indent(Indentation) << "MI.addOperand(MCOperand::createImm(tmp));\n"; -@@ -1091,7 +1180,13 @@ void FilterChooser::emitDecoder(raw_ostream &OS, unsigned Indentation, - << "(MI, insn, Address, Decoder)" - << Emitter->GuardPostfix - << " { " << (HasCompleteDecoder ? "" : "DecodeComplete = false; ") -- << "return MCDisassembler::Fail; }\n"; -+ << "return " -+#ifdef CAPSTONE -+ << "MCDisassembler_Fail" -+#else -+ << "MCDisassembler::Fail" -+#endif -+ << "; }\n"; - break; - } - -@@ -1129,10 +1224,19 @@ unsigned FilterChooser::getDecoderIndex(DecoderSet &Decoders, - static void emitSinglePredicateMatch(raw_ostream &o, StringRef str, - const std::string &PredicateNamespace) { - if (str[0] == '!') -+#ifdef CAPSTONE -+ o << "~(Bits & " << PredicateNamespace << "_" -+ << str.slice(1,str.size()) << ")"; -+#else - o << "!Bits[" << PredicateNamespace << "::" - << str.slice(1,str.size()) << "]"; -+#endif - else -+#ifdef CAPSTONE -+ o << "(Bits & " << PredicateNamespace << "_" << str << ")"; -+#else - o << "Bits[" << PredicateNamespace << "::" << str << "]"; -+#endif - } - - bool FilterChooser::emitPredicateMatch(raw_ostream &o, unsigned &Indentation, -@@ -2047,6 +2151,17 @@ static bool populateInstruction(CodeGenTarget &Target, - // fieldFromInstruction(). - static void emitFieldFromInstruction(formatted_raw_ostream &OS) { - OS << "// Helper function for extracting fields from encoded instructions.\n" -+#ifdef CAPSTONE -+ << "#define FieldFromInstruction(fname, InsnType) \\\n" -+ << "static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \\\n" -+ << "{ \\\n" -+ << " InsnType fieldMask; \\\n" -+ << " if (numBits == sizeof(InsnType)*8) \\\n" -+ << " fieldMask = (InsnType)(-1LL); \\\n" -+ << " else \\\n" -+ << " fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \\\n" -+ << " return (insn & fieldMask) >> startBit; \\\n" -+#else - << "template\n" - << "static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,\n" - << " unsigned numBits) {\n" -@@ -2058,12 +2173,92 @@ static void emitFieldFromInstruction(formatted_raw_ostream &OS) { - << " else\n" - << " fieldMask = (((InsnType)1 << numBits) - 1) << startBit;\n" - << " return (insn & fieldMask) >> startBit;\n" -+#endif - << "}\n\n"; - } - - // emitDecodeInstruction - Emit the templated helper function - // decodeInstruction(). - static void emitDecodeInstruction(formatted_raw_ostream &OS) { -+#ifdef CAPSTONE -+ OS << "#define DecodeInstruction(fname, fieldname, decoder, InsnType) \\\n" -+ << "static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \\\n" -+ << " InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \\\n" -+ << "{ \\\n" -+ << " uint64_t Bits = getFeatureBits(feature); \\\n" -+ << " const uint8_t *Ptr = DecodeTable; \\\n" -+ << " uint32_t CurFieldValue = 0, ExpectedValue; \\\n" -+ << " DecodeStatus S = MCDisassembler_Success; \\\n" -+ << " unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \\\n" -+ << " InsnType Val, FieldValue, PositiveMask, NegativeMask; \\\n" -+ << " bool Pred, Fail; \\\n" -+ << " for (;;) { \\\n" -+ << " switch (*Ptr) { \\\n" -+ << " default: \\\n" -+ << " return MCDisassembler_Fail; \\\n" -+ << " case MCD_OPC_ExtractField: { \\\n" -+ << " Start = *++Ptr; \\\n" -+ << " Len = *++Ptr; \\\n" -+ << " ++Ptr; \\\n" -+ << " CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \\\n" -+ << " break; \\\n" -+ << " } \\\n" -+ << " case MCD_OPC_FilterValue: { \\\n" -+ << " Val = (InsnType)decodeULEB128(++Ptr, &Len); \\\n" -+ << " Ptr += Len; \\\n" -+ << " NumToSkip = *Ptr++; \\\n" -+ << " NumToSkip |= (*Ptr++) << 8; \\\n" -+ << " if (Val != CurFieldValue) \\\n" -+ << " Ptr += NumToSkip; \\\n" -+ << " break; \\\n" -+ << " } \\\n" -+ << " case MCD_OPC_CheckField: { \\\n" -+ << " Start = *++Ptr; \\\n" -+ << " Len = *++Ptr; \\\n" -+ << " FieldValue = fieldname(insn, Start, Len); \\\n" -+ << " ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \\\n" -+ << " Ptr += Len; \\\n" -+ << " NumToSkip = *Ptr++; \\\n" -+ << " NumToSkip |= (*Ptr++) << 8; \\\n" -+ << " if (ExpectedValue != FieldValue) \\\n" -+ << " Ptr += NumToSkip; \\\n" -+ << " break; \\\n" -+ << " } \\\n" -+ << " case MCD_OPC_CheckPredicate: { \\\n" -+ << " PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \\\n" -+ << " Ptr += Len; \\\n" -+ << " NumToSkip = *Ptr++; \\\n" -+ << " NumToSkip |= (*Ptr++) << 8; \\\n" -+ << " Pred = checkDecoderPredicate(PIdx, Bits); \\\n" -+ << " if (!Pred) \\\n" -+ << " Ptr += NumToSkip; \\\n" -+ << " (void)Pred; \\\n" -+ << " break; \\\n" -+ << " } \\\n" -+ << " case MCD_OPC_Decode: { \\\n" -+ << " Opc = (unsigned)decodeULEB128(++Ptr, &Len); \\\n" -+ << " Ptr += Len; \\\n" -+ << " DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \\\n" -+ << " Ptr += Len; \\\n" -+ << " MCInst_setOpcode(MI, Opc); \\\n" -+ << " return decoder(S, DecodeIdx, insn, MI, Address, MRI); \\\n" -+ << " } \\\n" -+ << " case MCD_OPC_SoftFail: { \\\n" -+ << " PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \\\n" -+ << " Ptr += Len; \\\n" -+ << " NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \\\n" -+ << " Ptr += Len; \\\n" -+ << " Fail = (insn & PositiveMask) || (~insn & NegativeMask); \\\n" -+ << " if (Fail) \\\n" -+ << " S = MCDisassembler_SoftFail; \\\n" -+ << " break; \\\n" -+ << " } \\\n" -+ << " case MCD_OPC_Fail: { \\\n" -+ << " return MCDisassembler_Fail; \\\n" -+ << " } \\\n" -+ << " } \\\n" -+ << " } \\\n" -+#else - OS << "template\n" - << "static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], " - "MCInst &MI,\n" -@@ -2240,12 +2435,18 @@ static void emitDecodeInstruction(formatted_raw_ostream &OS) { - << " }\n" - << " llvm_unreachable(\"bogosity detected in disassembler state " - "machine!\");\n" -+#endif - << "}\n\n"; - } - - // Emits disassembler code for instruction decoding. - void FixedLenDecoderEmitter::run(raw_ostream &o) { - formatted_raw_ostream OS(o); -+#ifdef CAPSTONE -+ OS << "#include \"../../MCInst.h\"\n"; -+ OS << "#include \"../../LEB128.h\"\n"; -+ OS << "\n"; -+#else - OS << "#include \"llvm/MC/MCInst.h\"\n"; - OS << "#include \"llvm/Support/Debug.h\"\n"; - OS << "#include \"llvm/Support/DataTypes.h\"\n"; -@@ -2254,6 +2455,7 @@ void FixedLenDecoderEmitter::run(raw_ostream &o) { - OS << "#include \n"; - OS << '\n'; - OS << "namespace llvm {\n\n"; -+#endif - - emitFieldFromInstruction(OS); - -@@ -2322,7 +2524,13 @@ void FixedLenDecoderEmitter::run(raw_ostream &o) { - // Emit the main entry point for the decoder, decodeInstruction(). - emitDecodeInstruction(OS); - -+#ifdef CAPSTONE -+ OS << "FieldFromInstruction(fieldFromInstruction, uint64_t)\n"; -+ OS << "DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint64_t)\n"; -+ OS << "DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint64_t)\n"; -+#else - OS << "\n} // End llvm namespace\n"; -+#endif - } - - namespace llvm { --- -2.19.1 - diff --git a/contrib/sysz_update/0005-capstone-generate-GenAsmWriter.inc.patch b/contrib/sysz_update/0005-capstone-generate-GenAsmWriter.inc.patch deleted file mode 100644 index cd1353eb7f..0000000000 --- a/contrib/sysz_update/0005-capstone-generate-GenAsmWriter.inc.patch +++ /dev/null @@ -1,225 +0,0 @@ -From 5569e48b9cb34a33910e1e850fbfabc999f016a2 Mon Sep 17 00:00:00 2001 -From: mephi42 -Date: Tue, 7 Aug 2018 20:00:08 +0200 -Subject: [PATCH 5/7] capstone: generate *GenAsmWriter.inc - ---- - utils/TableGen/AsmWriterEmitter.cpp | 89 +++++++++++++++++++++++++++-- - utils/TableGen/AsmWriterInst.cpp | 4 ++ - 2 files changed, 87 insertions(+), 6 deletions(-) - -diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp -index 3c4c9c8e5c6..133800d217c 100644 ---- a/utils/TableGen/AsmWriterEmitter.cpp -+++ b/utils/TableGen/AsmWriterEmitter.cpp -@@ -272,16 +272,22 @@ static void UnescapeString(std::string &Str) { - /// clearing the Instructions vector. - void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { - Record *AsmWriter = Target.getAsmWriter(); -+#ifndef CAPSTONE - StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); -+#endif - bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); - - O << - "/// printInstruction - This method is automatically generated by tablegen\n" - "/// from the instruction set description.\n" -+#ifdef CAPSTONE -+ "static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)\n{\n"; -+#else - "void " << Target.getName() << ClassName - << "::printInstruction(const MCInst *MI, " - << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "") - << "raw_ostream &O) {\n"; -+#endif - - // Build an aggregate string, and build a table of offsets into it. - SequenceToOffsetTable StringTable; -@@ -379,9 +385,16 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { - } - - // Emit the string table itself. -+#ifdef CAPSTONE -+ O << "#ifndef CAPSTONE_DIET\n"; -+#endif - O << " static const char AsmStrs[] = {\n"; - StringTable.emit(O, printChar); -- O << " };\n\n"; -+ O << " };\n" -+#ifdef CAPSTONE -+ << "#endif\n" -+#endif -+ << "\n"; - - // Emit the lookup tables in pieces to minimize wasted bytes. - unsigned BytesNeeded = ((OpcodeInfoBits - BitsLeft) + 7) / 8; -@@ -409,21 +422,45 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { - // If the total bits is more than 32-bits we need to use a 64-bit type. - if (BitsLeft < (OpcodeInfoBits - 32)) - BitsOS << "(uint64_t)"; -- BitsOS << "OpInfo" << Table << "[MI->getOpcode()] << " << Shift << ";\n"; -+ BitsOS << "OpInfo" << Table << "[" -+#ifdef CAPSTONE -+ << "MCInst_getOpcode(MI)" -+#else -+ << "MI->getOpcode()" -+#endif -+ << "] << " << Shift << ";\n"; - // Prepare the shift for the next iteration and increment the table count. - Shift += TableSize; - ++Table; - } - - // Emit the initial tab character. -+#ifndef CAPSTONE - O << " O << \"\\t\";\n\n"; -+#endif - - O << " // Emit the opcode for the instruction.\n"; - O << BitsString; - - // Emit the starting string. -- O << " assert(Bits != 0 && \"Cannot print this instruction.\");\n" -- << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n"; -+ O << " " -+#ifdef CAPSTONE -+ << "// " -+#endif -+ << "assert(Bits != 0 && \"Cannot print this instruction.\");\n" -+#ifdef CAPSTONE -+ << "#ifndef CAPSTONE_DIET\n" -+ << " SStream_concat0(O, " -+#else -+ << " O << " -+#endif -+ << "AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1" -+#ifdef CAPSTONE -+ << ");\n" -+ << "#endif\n\n"; -+#else -+ << ");\n\n"; -+#endif - - // Output the table driven operand information. - BitsLeft = OpcodeInfoBits-AsmStrBits; -@@ -455,7 +492,11 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { - O << " switch ((Bits >> " - << (OpcodeInfoBits-BitsLeft) << ") & " - << ((1 << NumBits)-1) << ") {\n" -- << " default: llvm_unreachable(\"Invalid command number.\");\n"; -+ << " default: " -+#ifdef CAPSTONE -+ << "// " -+#endif -+ << "llvm_unreachable(\"Invalid command number.\");\n"; - - // Print out all the cases. - for (unsigned j = 0, e = Commands.size(); j != e; ++j) { -@@ -536,6 +577,9 @@ emitRegisterNameString(raw_ostream &O, StringRef AltName, - } - - StringTable.layout(); -+#ifdef CAPSTONE -+ O << "#ifndef CAPSTONE_DIET\n"; -+#endif - O << " static const char AsmStrs" << AltName << "[] = {\n"; - StringTable.emit(O, printChar); - O << " };\n\n"; -@@ -552,8 +596,10 @@ emitRegisterNameString(raw_ostream &O, StringRef AltName, - } - - void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { -+#ifndef CAPSTONE - Record *AsmWriter = Target.getAsmWriter(); - StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); -+#endif - const auto &Registers = Target.getRegBank().getRegisters(); - const std::vector &AltNameIndices = Target.getRegAltNameIndices(); - bool hasAltNames = AltNameIndices.size() > 1; -@@ -563,12 +609,20 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { - "\n\n/// getRegisterName - This method is automatically generated by tblgen\n" - "/// from the register set description. This returns the assembler name\n" - "/// for the specified register.\n" -+#ifdef CAPSTONE -+ "static const char *getRegisterName(unsigned RegNo)\n{\n"; -+#else - "const char *" << Target.getName() << ClassName << "::"; - if (hasAltNames) - O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n"; - else - O << "getRegisterName(unsigned RegNo) {\n"; -- O << " assert(RegNo && RegNo < " << (Registers.size()+1) -+#endif -+ O << " " -+#ifdef CAPSTONE -+ << "// " -+#endif -+ << "assert(RegNo && RegNo < " << (Registers.size()+1) - << " && \"Invalid register number!\");\n" - << "\n"; - -@@ -595,10 +649,22 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { - } - O << " }\n"; - } else { -+#ifdef CAPSTONE -+ O << " //int i;\n" -+ << " //for (i = 0; i < sizeof(RegAsmOffset); i++)\n" -+ << " // printf(\"%s = %u\\n\", AsmStrs+RegAsmOffset[i], i + 1);\n" -+ << " //printf(\"*************************\\n\");\n" -+#else - O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n" - << " \"Invalid alt name index for register!\");\n" -+#endif - << " return AsmStrs+RegAsmOffset[RegNo-1];\n"; - } -+#ifdef CAPSTONE -+ O << "#else\n" -+ << " return NULL;\n" -+ << "#endif\n"; -+#endif - O << "}\n"; - } - -@@ -1135,9 +1201,20 @@ AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) { - } - - void AsmWriterEmitter::run(raw_ostream &O) { -+#ifdef CAPSTONE -+ O << "/* Capstone Disassembly Engine */\n" -+ "/* By Nguyen Anh Quynh , 2013-2015 */\n" -+ "\n" -+ "#include \t// debug\n" -+ "#include \n" -+ "\n" -+ "\n"; -+#endif - EmitPrintInstruction(O); - EmitGetRegisterName(O); -+#ifndef CAPSTONE - EmitPrintAliasInstruction(O); -+#endif - } - - namespace llvm { -diff --git a/utils/TableGen/AsmWriterInst.cpp b/utils/TableGen/AsmWriterInst.cpp -index 2c19e5d663d..6fa751e50df 100644 ---- a/utils/TableGen/AsmWriterInst.cpp -+++ b/utils/TableGen/AsmWriterInst.cpp -@@ -28,9 +28,13 @@ static bool isIdentChar(char C) { - - std::string AsmWriterOperand::getCode(bool PassSubtarget) const { - if (OperandType == isLiteralTextOperand) { -+#ifdef CAPSTONE -+ return "SStream_concat0(O, \"" + Str + "\");"; -+#else - if (Str.size() == 1) - return "O << '" + Str + "';"; - return "O << \"" + Str + "\";"; -+#endif - } - - if (OperandType == isLiteralStatementOperand) --- -2.19.1 - diff --git a/contrib/sysz_update/0006-capstone-generate-MappingInsn.inc.patch b/contrib/sysz_update/0006-capstone-generate-MappingInsn.inc.patch deleted file mode 100644 index 7ee22d7877..0000000000 --- a/contrib/sysz_update/0006-capstone-generate-MappingInsn.inc.patch +++ /dev/null @@ -1,174 +0,0 @@ -From 7a436110ef15c803dc8524af2fb5612bcacbb126 Mon Sep 17 00:00:00 2001 -From: mephi42 -Date: Tue, 7 Aug 2018 20:55:32 +0200 -Subject: [PATCH 6/7] capstone: generate *MappingInsn.inc - ---- - lib/Target/SystemZ/CMakeLists.txt | 1 + - utils/TableGen/InstrInfoEmitter.cpp | 95 +++++++++++++++++++++++++++++ - utils/TableGen/TableGen.cpp | 6 ++ - utils/TableGen/TableGenBackends.h | 1 + - 4 files changed, 103 insertions(+) - -diff --git a/lib/Target/SystemZ/CMakeLists.txt b/lib/Target/SystemZ/CMakeLists.txt -index f83b4242fb4..4b5d9c4a3b2 100644 ---- a/lib/Target/SystemZ/CMakeLists.txt -+++ b/lib/Target/SystemZ/CMakeLists.txt -@@ -6,6 +6,7 @@ tablegen(LLVM SystemZGenCallingConv.inc -gen-callingconv) - tablegen(LLVM SystemZGenDAGISel.inc -gen-dag-isel) - tablegen(LLVM SystemZGenDisassemblerTables.inc -gen-disassembler) - tablegen(LLVM SystemZGenInstrInfo.inc -gen-instr-info) -+tablegen(LLVM SystemZMappingInsn.inc -mapping-insn) - tablegen(LLVM SystemZGenMCCodeEmitter.inc -gen-emitter) - tablegen(LLVM SystemZGenRegisterInfo.inc -gen-register-info) - tablegen(LLVM SystemZGenSubtargetInfo.inc -gen-subtarget) -diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp -index 2f3a2729262..14ab1ea8a72 100644 ---- a/utils/TableGen/InstrInfoEmitter.cpp -+++ b/utils/TableGen/InstrInfoEmitter.cpp -@@ -744,4 +744,99 @@ void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) { - #endif - } - -+#ifdef CAPSTONE -+std::string GetPublicName(const CodeGenInstruction *Inst) { -+ std::string Name = Inst->TheDef->getName(); -+ // Apply backward compatibility fixups. -+ // BRNLE -> BNLER. -+ if (Name.length() >= 5 && Name.substr(0, 5) == "BRAsm") { -+ Name = "B" + Name.substr(5, Name.length() - 5) + "R"; -+ } -+ // SSKEOpt -> SSKE. -+ while (Name.length() >= 3 && Name.substr(Name.length() - 3, 3) == "Opt") { -+ Name = Name.substr(0, Name.length() - 3); -+ } -+ // BRCLAsm -> BRCL. -+ while (true) { -+ size_t pos = Name.find("Asm"); -+ if (pos == std::string::npos) { -+ break; -+ } -+ Name = Name.substr(0, pos) + Name.substr(pos + 3); -+ } -+ // CPSDRxx -> CPSDR. -+ if (Name.length() >= 2) { -+ std::string Suffix2 = Name.substr(Name.length() - 2, 2); -+ if (Suffix2 == "dd" || Suffix2 == "ds" || -+ Suffix2 == "sd" || Suffix2 == "ss") { -+ Name = Name.substr(0, Name.length() - 2); -+ } -+ } -+ return "SYSZ_INS_" + Name; -+} -+ -+std::string GetRegisterName(Record *Reg) { -+ std::string Name = Reg->getName(); -+ for (char& c : Name) { -+ c = toupper(c); -+ } -+ // R0L, R0D -> R0. -+ if (Name.length() >= 3 && -+ Name[Name.length() - 3] == 'R' && -+ (Name[Name.length() - 1] == 'L' || -+ Name[Name.length() - 1] == 'D')) { -+ Name = Name.substr(0, Name.length() - 3) + Name[Name.length() - 2]; -+ } -+ return "SYSZ_REG_" + Name; -+} -+ -+std::string GetGroupName(Record *Pred) { -+ std::string Name = Pred->getName(); -+ for (char& c : Name) { -+ c = toupper(c); -+ } -+ if (Name.length() >= 7 && Name.substr(0, 7) == "FEATURE") { -+ Name = Name.substr(7); -+ } -+ return "SYSZ_GRP_" + Name; -+} -+ -+void EmitMappingInsn(RecordKeeper &RK, raw_ostream &OS) { -+ OS << "// This is auto-gen data for Capstone engine (www.capstone-engine.org)\n" -+ "// By Nguyen Anh Quynh \n" -+ "\n"; -+ CodeGenTarget Target(RK); -+ for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) { -+ if (Inst->TheDef->getValueAsBit("isPseudo") || -+ Inst->TheDef->getValueAsBit("isCodeGenOnly")) { -+ continue; -+ } -+ OS << "{\n" -+ << "\t" << Target.getName() << "_" << Inst->TheDef->getName() << ", " -+ << GetPublicName(Inst) << ",\n" -+ << "#ifndef CAPSTONE_DIET\n" -+ << "\t{ "; -+ for (Record *Use : Inst->TheDef->getValueAsListOfDefs("Uses")) { -+ OS << GetRegisterName(Use) << ", "; -+ } -+ OS << "0 }, { "; -+ for (Record *Def : Inst->TheDef->getValueAsListOfDefs("Defs")) { -+ OS << GetRegisterName(Def) << ", "; -+ } -+ OS << "0 }, { "; -+ ListInit *Predicates = Inst->TheDef->getValueAsListInit("Predicates"); -+ for (unsigned i = 0; i < Predicates->size(); ++i) { -+ OS << GetGroupName(Predicates->getElementAsRecord(i)) << ", "; -+ } -+ OS << "0 }, " -+ << Inst->TheDef->getValueAsBit("isBranch") -+ << ", " -+ << Inst->TheDef->getValueAsBit("isIndirectBranch") -+ << "\n" -+ << "#endif\n" -+ << "},\n"; -+ } -+} -+#endif -+ - } // end llvm namespace -diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp -index cf1404d8769..bbb4e860536 100644 ---- a/utils/TableGen/TableGen.cpp -+++ b/utils/TableGen/TableGen.cpp -@@ -27,6 +27,7 @@ enum ActionType { - GenEmitter, - GenRegisterInfo, - GenInstrInfo, -+ MappingInsn, - GenInstrDocs, - GenAsmWriter, - GenAsmMatcher, -@@ -65,6 +66,8 @@ namespace { - "Generate registers and register classes info"), - clEnumValN(GenInstrInfo, "gen-instr-info", - "Generate instruction descriptions"), -+ clEnumValN(MappingInsn, "mapping-insn", -+ ""), - clEnumValN(GenInstrDocs, "gen-instr-docs", - "Generate instruction documentation"), - clEnumValN(GenCallingConv, "gen-callingconv", -@@ -135,6 +138,9 @@ bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) { - case GenInstrInfo: - EmitInstrInfo(Records, OS); - break; -+ case MappingInsn: -+ EmitMappingInsn(Records, OS); -+ break; - case GenInstrDocs: - EmitInstrDocs(Records, OS); - break; -diff --git a/utils/TableGen/TableGenBackends.h b/utils/TableGen/TableGenBackends.h -index 1329a6d833f..a41e46b1db0 100644 ---- a/utils/TableGen/TableGenBackends.h -+++ b/utils/TableGen/TableGenBackends.h -@@ -75,6 +75,7 @@ void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS); - void EmitDisassembler(RecordKeeper &RK, raw_ostream &OS); - void EmitFastISel(RecordKeeper &RK, raw_ostream &OS); - void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS); -+void EmitMappingInsn(RecordKeeper &RK, raw_ostream &OS); - void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS); - void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS); - void EmitCompressInst(RecordKeeper &RK, raw_ostream &OS); --- -2.19.1 - diff --git a/contrib/sysz_update/0007-capstone-generate-GenInsnNameMaps.inc.patch b/contrib/sysz_update/0007-capstone-generate-GenInsnNameMaps.inc.patch deleted file mode 100644 index 019540d653..0000000000 --- a/contrib/sysz_update/0007-capstone-generate-GenInsnNameMaps.inc.patch +++ /dev/null @@ -1,110 +0,0 @@ -From b42f9f2014ec49a22077b6610863d9341a74e142 Mon Sep 17 00:00:00 2001 -From: mephi42 -Date: Fri, 17 Aug 2018 11:07:39 +0200 -Subject: [PATCH 7/7] capstone: generate *GenInsnNameMaps.inc - ---- - lib/Target/SystemZ/CMakeLists.txt | 1 + - utils/TableGen/InstrInfoEmitter.cpp | 29 +++++++++++++++++++++++++++++ - utils/TableGen/TableGen.cpp | 6 ++++++ - utils/TableGen/TableGenBackends.h | 1 + - 4 files changed, 37 insertions(+) - -diff --git a/lib/Target/SystemZ/CMakeLists.txt b/lib/Target/SystemZ/CMakeLists.txt -index 4b5d9c4a3b2..2c64e0a94b8 100644 ---- a/lib/Target/SystemZ/CMakeLists.txt -+++ b/lib/Target/SystemZ/CMakeLists.txt -@@ -7,6 +7,7 @@ tablegen(LLVM SystemZGenDAGISel.inc -gen-dag-isel) - tablegen(LLVM SystemZGenDisassemblerTables.inc -gen-disassembler) - tablegen(LLVM SystemZGenInstrInfo.inc -gen-instr-info) - tablegen(LLVM SystemZMappingInsn.inc -mapping-insn) -+tablegen(LLVM SystemZGenInsnNameMaps.inc -gen-insn-name-maps) - tablegen(LLVM SystemZGenMCCodeEmitter.inc -gen-emitter) - tablegen(LLVM SystemZGenRegisterInfo.inc -gen-register-info) - tablegen(LLVM SystemZGenSubtargetInfo.inc -gen-subtarget) -diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp -index 14ab1ea8a72..ccf8170ca62 100644 ---- a/utils/TableGen/InstrInfoEmitter.cpp -+++ b/utils/TableGen/InstrInfoEmitter.cpp -@@ -837,6 +837,35 @@ void EmitMappingInsn(RecordKeeper &RK, raw_ostream &OS) { - << "},\n"; - } - } -+ -+std::string GetMnemonic(const CodeGenInstruction *Inst) { -+ std::string Mnemonic = Inst->AsmString; -+ -+ for (size_t i = 0; i < Mnemonic.length(); i++) { -+ if (Mnemonic[i] == '\t') { -+ return Mnemonic.substr(0, i); -+ } -+ } -+ return Mnemonic; -+} -+ -+void EmitInsnNameMaps(RecordKeeper &RK, raw_ostream &OS) { -+ OS << "// This is auto-gen data for Capstone engine (www.capstone-engine.org)\n" -+ "// By Nguyen Anh Quynh \n" -+ "\n"; -+ CodeGenTarget Target(RK); -+ std::map M; -+ for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) { -+ if (Inst->TheDef->getValueAsBit("isPseudo") || -+ Inst->TheDef->getValueAsBit("isCodeGenOnly")) { -+ continue; -+ } -+ M[GetPublicName(Inst)] = GetMnemonic(Inst); -+ } -+ for (auto &P : M) { -+ OS << "\t{ " << P.first << ", \"" << P.second << "\" },\n"; -+ } -+} - #endif - - } // end llvm namespace -diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp -index bbb4e860536..27c6603de5a 100644 ---- a/utils/TableGen/TableGen.cpp -+++ b/utils/TableGen/TableGen.cpp -@@ -28,6 +28,7 @@ enum ActionType { - GenRegisterInfo, - GenInstrInfo, - MappingInsn, -+ GenInsnNameMaps, - GenInstrDocs, - GenAsmWriter, - GenAsmMatcher, -@@ -68,6 +69,8 @@ namespace { - "Generate instruction descriptions"), - clEnumValN(MappingInsn, "mapping-insn", - ""), -+ clEnumValN(GenInsnNameMaps, "gen-insn-name-maps", -+ ""), - clEnumValN(GenInstrDocs, "gen-instr-docs", - "Generate instruction documentation"), - clEnumValN(GenCallingConv, "gen-callingconv", -@@ -141,6 +144,9 @@ bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) { - case MappingInsn: - EmitMappingInsn(Records, OS); - break; -+ case GenInsnNameMaps: -+ EmitInsnNameMaps(Records, OS); -+ break; - case GenInstrDocs: - EmitInstrDocs(Records, OS); - break; -diff --git a/utils/TableGen/TableGenBackends.h b/utils/TableGen/TableGenBackends.h -index a41e46b1db0..5656e5be849 100644 ---- a/utils/TableGen/TableGenBackends.h -+++ b/utils/TableGen/TableGenBackends.h -@@ -76,6 +76,7 @@ void EmitDisassembler(RecordKeeper &RK, raw_ostream &OS); - void EmitFastISel(RecordKeeper &RK, raw_ostream &OS); - void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS); - void EmitMappingInsn(RecordKeeper &RK, raw_ostream &OS); -+void EmitInsnNameMaps(RecordKeeper &RK, raw_ostream &OS); - void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS); - void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS); - void EmitCompressInst(RecordKeeper &RK, raw_ostream &OS); --- -2.19.1 - diff --git a/contrib/sysz_update/README.md b/contrib/sysz_update/README.md deleted file mode 100644 index c50c7d18ba..0000000000 --- a/contrib/sysz_update/README.md +++ /dev/null @@ -1,58 +0,0 @@ -# How to update SystemZ tables. - -* Checkout LLVM. Patches are tested on commit `c13d5969^`, because - `c13d5969` changed the decode table format. -* Apply patches from the current directory. -* Run tablegen. - ``` - cd $LLVM - mkdir build - cd build - cmake -DCMAKE_CXX_FLAGS=-DCAPSTONE .. - make SystemZCommonTableGen -j$(getconf _NPROCESSORS_ONLN) - ``` -* Copy `.inc` files. - ``` - cp arch/SystemZ/SystemZGenInsnNameMaps.inc \ - arch/SystemZ/SystemZGenInsnNameMaps.inc.old - for inc in $(cd arch/SystemZ && ls *.inc); do - cp $LLVM/build/lib/Target/SystemZ/$inc arch/SystemZ/ - done - ``` -* Fixup `SystemZGenInsnNameMaps.inc`. - ``` - comm -1 -3 \ - <(grep SYSZ_INS_ arch/SystemZ/SystemZGenInsnNameMaps.inc.new - cat arch/SystemZ/SystemZGenInsnNameMaps.inc.old \ - arch/SystemZ/SystemZGenInsnNameMaps.inc.new \ - >arch/SystemZ/SystemZGenInsnNameMaps.inc - ``` -* Add new groups, insns, registers and formats. - * `include/capstone/systemz.h` - * `enum sysz_insn`: - ``` - comm -1 -3 \ - <(perl -ne 'if (/(SYSZ_INS_.+),/) { print "\t$1,\n" }' \ - 0) { - MCInst_Init(&mci); + MCInst_Init(&mci, handle->arch); mci.csh = handle; // relative branches need to know the address & size of current insn @@ -1442,7 +1458,7 @@ bool CAPSTONE_API cs_disasm_iter(csh ud, const uint8_t **code, size_t *size, handle->errnum = CS_ERR_OK; - MCInst_Init(&mci); + MCInst_Init(&mci, handle->arch); mci.csh = handle; // relative branches need to know the address & size of current insn @@ -1700,9 +1716,9 @@ int CAPSTONE_API cs_op_count(csh ud, const cs_insn *insn, unsigned int op_type) if (insn->detail->sparc.operands[i].type == (sparc_op_type)op_type) count++; break; - case CS_ARCH_SYSZ: - for (i = 0; i < insn->detail->sysz.op_count; i++) - if (insn->detail->sysz.operands[i].type == (sysz_op_type)op_type) + case CS_ARCH_SYSTEMZ: + for (i = 0; i < insn->detail->systemz.op_count; i++) + if (insn->detail->systemz.operands[i].type == (systemz_op_type)op_type) count++; break; case CS_ARCH_XCORE: @@ -1852,9 +1868,9 @@ int CAPSTONE_API cs_op_index(csh ud, const cs_insn *insn, unsigned int op_type, return i; } break; - case CS_ARCH_SYSZ: - for (i = 0; i < insn->detail->sysz.op_count; i++) { - if (insn->detail->sysz.operands[i].type == (sysz_op_type)op_type) + case CS_ARCH_SYSTEMZ: + for (i = 0; i < insn->detail->systemz.op_count; i++) { + if (insn->detail->systemz.operands[i].type == (systemz_op_type)op_type) count++; if (count == post) return i; diff --git a/cstool/cstool.c b/cstool/cstool.c index 2dba612f32..48327d9d2e 100644 --- a/cstool/cstool.c +++ b/cstool/cstool.c @@ -146,8 +146,16 @@ static struct { { "sparc", "Sparc, big endian", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN }, { "sparcv9", "Sparc v9, big endian", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN | CS_MODE_V9 }, - { "systemz", "SystemZ, big endian", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN }, - { "s390x", "SystemZ s390x, big endian", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN }, + { "systemz", "systemz (s390x) - all features", CS_ARCH_SYSTEMZ, CS_MODE_BIG_ENDIAN }, + { "systemz_arch8", "(arch8/z10/generic)\n", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH8 | CS_MODE_BIG_ENDIAN }, + { "systemz_arch9", "(arch9/z196)\n", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH9 | CS_MODE_BIG_ENDIAN }, + { "systemz_arch10", "(arch10/zec12)\n", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH10 | CS_MODE_BIG_ENDIAN }, + { "systemz_arch11", "(arch11/z13)\n", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH11 | CS_MODE_BIG_ENDIAN }, + { "systemz_arch12", "(arch12/z14)\n", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH12 | CS_MODE_BIG_ENDIAN }, + { "systemz_arch13", "(arch13/z15)\n", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH13 | CS_MODE_BIG_ENDIAN }, + { "systemz_arch14", "(arch14/z16)\n", CS_ARCH_SYSTEMZ, CS_MODE_SYSTEMZ_ARCH14 | CS_MODE_BIG_ENDIAN }, + + { "s390x", "SystemZ s390x, big endian", CS_ARCH_SYSTEMZ, CS_MODE_BIG_ENDIAN }, { "xcore", "xcore, big endian", CS_ARCH_XCORE, CS_MODE_BIG_ENDIAN }, @@ -283,7 +291,7 @@ static const char *get_arch_name(cs_arch arch) case CS_ARCH_X86: return "x86"; case CS_ARCH_PPC: return "PowerPC"; case CS_ARCH_SPARC: return "Sparc"; - case CS_ARCH_SYSZ: return "SysZ"; + case CS_ARCH_SYSTEMZ: return "SystemZ"; case CS_ARCH_XCORE: return "Xcore"; case CS_ARCH_M68K: return "M68K"; case CS_ARCH_TMS320C64X: return "TMS320C64X"; @@ -370,8 +378,8 @@ static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins) case CS_ARCH_SPARC: print_insn_detail_sparc(handle, ins); break; - case CS_ARCH_SYSZ: - print_insn_detail_sysz(handle, ins); + case CS_ARCH_SYSTEMZ: + print_insn_detail_systemz(handle, ins); break; case CS_ARCH_XCORE: print_insn_detail_xcore(handle, ins); @@ -581,8 +589,8 @@ int main(int argc, char **argv) printf("sparc=1 "); } - if (cs_support(CS_ARCH_SYSZ)) { - printf("sysz=1 "); + if (cs_support(CS_ARCH_SYSTEMZ)) { + printf("systemz=1 "); } if (cs_support(CS_ARCH_XCORE)) { @@ -767,7 +775,7 @@ int main(int argc, char **argv) for (; j < 16; j++) { printf(" "); } - } else if (arch == CS_ARCH_SYSZ) { + } else if (arch == CS_ARCH_SYSTEMZ) { for (; j < 6; j++) { printf(" "); } diff --git a/cstool/cstool.h b/cstool/cstool.h index d0d73d1e89..0c4a8098e5 100644 --- a/cstool/cstool.h +++ b/cstool/cstool.h @@ -7,7 +7,7 @@ void print_insn_detail_aarch64(csh handle, cs_insn *ins); void print_insn_detail_mips(csh handle, cs_insn *ins); void print_insn_detail_ppc(csh handle, cs_insn *ins); void print_insn_detail_sparc(csh handle, cs_insn *ins); -void print_insn_detail_sysz(csh handle, cs_insn *ins); +void print_insn_detail_systemz(csh handle, cs_insn *ins); void print_insn_detail_xcore(csh handle, cs_insn *ins); void print_insn_detail_m68k(csh handle, cs_insn *ins); void print_insn_detail_tms320c64x(csh handle, cs_insn *ins); diff --git a/cstool/cstool_systemz.c b/cstool/cstool_systemz.c index aa3962685a..90ed798775 100644 --- a/cstool/cstool_systemz.c +++ b/cstool/cstool_systemz.c @@ -6,50 +6,84 @@ #include #include "cstool.h" -void print_insn_detail_sysz(csh handle, cs_insn *ins) +void print_insn_detail_systemz(csh handle, cs_insn *ins) { - cs_sysz *sysz; + cs_systemz *systemz; int i; // detail can be NULL on "data" instruction if SKIPDATA option is turned ON if (ins->detail == NULL) return; - sysz = &(ins->detail->sysz); - if (sysz->op_count) - printf("\top_count: %u\n", sysz->op_count); + systemz = &(ins->detail->systemz); + if (systemz->op_count) + printf("\top_count: %u\n", systemz->op_count); - for (i = 0; i < sysz->op_count; i++) { - cs_sysz_op *op = &(sysz->operands[i]); + for (i = 0; i < systemz->op_count; i++) { + cs_systemz_op *op = &(systemz->operands[i]); switch((int)op->type) { default: break; - case SYSZ_OP_REG: + case SYSTEMZ_OP_REG: printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); break; - case SYSZ_OP_ACREG: - printf("\t\toperands[%u].type: ACREG = %u\n", i, op->reg); - break; - case SYSZ_OP_IMM: + case SYSTEMZ_OP_IMM: printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); break; - case SYSZ_OP_MEM: + case SYSTEMZ_OP_MEM: printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.base != SYSZ_REG_INVALID) + if (op->mem.base != SYSTEMZ_REG_INVALID) printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base)); - if (op->mem.index != SYSZ_REG_INVALID) + if (op->mem.index != SYSTEMZ_REG_INVALID) printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index)); - if (op->mem.length != 0) - printf("\t\t\toperands[%u].mem.length: 0x%" PRIx64 "\n", i, op->mem.length); - if (op->mem.disp != 0) - printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp); - + if (op->mem.length != 0) { + if (op->mem.am == SYSTEMZ_AM_BDL) { + printf("\t\t\toperands[%u].mem.length: 0x%" PRIx64 "\n", i, op->mem.length); + } else { + printf("\t\t\toperands[%u].mem.length: 0x%" PRIx64 "\n", i, op->mem.length); + } + } + printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp); + switch(op->mem.am) { + default: + printf("\t\t\toperands[%u].mem.am: UNHANDLED\n", i); + break; + case SYSTEMZ_AM_BD: + printf("\t\t\toperands[%u].mem.am: SYSTEMZ_AM_BD\n", i); + break; + case SYSTEMZ_AM_BDX: + printf("\t\t\toperands[%u].mem.am: SYSTEMZ_AM_BDX\n", i); + break; + case SYSTEMZ_AM_BDL: + printf("\t\t\toperands[%u].mem.am: SYSTEMZ_AM_BDL\n", i); + break; + case SYSTEMZ_AM_BDR: + printf("\t\t\toperands[%u].mem.am: SYSTEMZ_AM_BDR\n", i); + break; + case SYSTEMZ_AM_BDV: + printf("\t\t\toperands[%u].mem.am: SYSTEMZ_AM_BDV\n", i); + break; + } break; } + switch(op->access) { + default: + break; + case CS_AC_READ: + printf("\t\toperands[%u].access: READ\n", i); + break; + case CS_AC_WRITE: + printf("\t\toperands[%u].access: WRITE\n", i); + break; + case CS_AC_READ | CS_AC_WRITE: + printf("\t\toperands[%u].access: READ | WRITE\n", i); + break; + } + } - if (sysz->cc != 0) - printf("\tCode condition: %u\n", sysz->cc); + if (systemz->cc != SYSTEMZ_CC_INVALID) + printf("\tCode condition: %u\n", systemz->cc); } diff --git a/docs/cs_v6_release_guide.md b/docs/cs_v6_release_guide.md index ee94914cdd..7d1e732c85 100644 --- a/docs/cs_v6_release_guide.md +++ b/docs/cs_v6_release_guide.md @@ -34,6 +34,62 @@ The `auto-sync` updater, the additional updates of ARM, AArch64 and PPC, as well With all that said, we hope you enjoy the new release! +## New features + +**LoongArch** + +- Architecture support was added (based on LLVM-18). + +**HPPA** + +- Architecture support was added. + +**Alpha** + +- Architecture support was added (based on LLVM-3) +- System operands are provided with way more detail in separated operand. + +**AArch64** + +- Updated to LLVM-18 +- Adding new instructions of SME, SVE2 extensions. With it the `sme` and `pred` operands are added. +- System operands are provided with way more detail in separated operand. + +**PPC** + +- Updated to LLVM-16 +- The instruction encoding formats are added for PPC. They are accessible via `cs_ppc->format`. +They do follow loosely the ISA formats of instructions but not quite. Unfortunately, +LLV doesn't group the instruction formats perfectly aligned with the ISA. +Nonetheless, we hope this additional information is useful to you. +- Branching information in `cs_ppc->bc` is way more detailed now. +- The Paired Single extension was added. + +**SystemZ** + +- Updated to LLVM-18 +- Operands have now read/write access information +- Memory operands have now the address mode specified +- Immediate oprands have a new `imm_width` field. storing the bit width if known. +- CPU features can be enabled or disabled by SystemZ architecture (arch8-arch14). + +**Mips** + +- Updated to LLVM-18 +- Support added for: `microMips32r3`, `microMips32r6`, `Mips16`, `Mips I ISA`, `Mips II ISA`, `Mips32 r2 ISA`, `Mips32 r3 ISA`, `Mips32 r5 ISA`, `Mips32 r6 ISA`, `Mips III ISA`, `Mips IV ISA`, `Mips V ISA`, `Mips64 r2 ISA`, `Mips64 r3 ISA`, `Mips64 r5 ISA`, `Mips64 r6 ISA`, `Octeon (cnMIPS)`, `Octeon+ (cnMIPS+)`, `NanoMips` +- Support for different register naming style (`CS_OPT_SYNTAX_NO_DOLLAR`, `CS_OPT_SYNTAX_NOREGNAME`) + +**RISCV** + +- Operands have now read/write access information + +**Code quality** + +- ASAN: All tests are now run with the address sanitizer enabled. This includes checking for leaks. +- Coverity code scanning workflow added. +- Testing was re-written from scratch. Now allowing fine-grained testing of all details and is more convenient to use by contributors. + + ## Breaking changes **All `auto-sync` architectures** @@ -49,6 +105,7 @@ With all that said, we hope you enjoy the new release! | Post-index | Post-index memory access has the disponent now set in the `MEMORY` operand! No longer as separated `reg`/`imm` operand. | The CS memory operand had a field which was there for disponents. Not having it set, for post-index operands was inconsistent. | Edit `ARM_set_detail_op_mem()` and add an immediate operand instead of setting the disponent. | | Sign `mem.disp` | `mem.disp` is now always positive and the `subtracted` flag indicates if it should be subtracted. | It was inconsistent before. | Change behavior in `ARM_set_detail_op_mem()` | | `ARM_CC` | `ARM_CC` → `ARMCC` and value change | They match the same LLVM enum. Better for LLVM compatibility and code generation. | Change it manually. | +| `ARMCC_*` | `ARMCC_EQ == 0` but `ARMCC_INVALID != 0` | They match the LLVM enum. Better for LLVM compatibility and code generation. | Change by hand. | | System registers | System registers are no longer saved in `cs_arm->reg`, but are separated and have more detail. | System operands follow their own encoding logic. Hence, they should be separated in the details as well. | None | | System operands | System operands have now the encoding of LLVM (SYSm value mostly) | See note about system registers. | None | | Instruction enum | Multiple instructions which were only alias were removed from the instruction enum. | Alias are always disassembled as their real instructions and an additional field identifies which alias it is. | None | @@ -68,7 +125,6 @@ With all that said, we hope you enjoy the new release! | `crx` | `ppc_ops_crx` was removed. | It was never used in the first place. | None. | | `(RA\|0)` | The `(RA\|0)` cases (see ISA for details) for which `0` is used, the `PPC_REG_ZERO` register is used. The register name of it is `0`. | Mimics LLVM behavior. | None. | - **AArch64** | Keyword | Change | Justification | Possible revert | @@ -79,26 +135,44 @@ With all that said, we hope you enjoy the new release! | `writeback` | `writeback` member was moved to detail. | See ARM explanation. | See ARM. | | `arm64_vas` | `arm64_vas` renamed to `AArch64Layout_VectorLayout` | LLVM compatibility. | None. | | Register alias | Register alias (`x29 = fp` etc.) are not printed if LLVM doesn't do it. Old Capstone register alias can be enabled by `CS_OPT_SYNTAX_CS_REG_ALIAS`. | Mimic LLVM as close as possible. | Enable option. | +| `AArch64CC_*` | `AArch64CC_EQ == 0` but `AArch64CC_INVALID != 0` | They match the LLVM enum. Better for LLVM compatibility and code generation. | Change by hand. | -**Note about AArch64** +**Mips** -`ARM64` was everywhere renamed to `AArch64`. This is a necessity to ensure that the update scripts stay reasonably simple. -Capstone was very inconsistent with the naming before (sometimes `AArch64` sometimes `ARM64`). -Because Capstone uses a huge amount of LLVM code, we renamed everything to `AArch64`. This reduces complexity enormously because it follows the naming of LLVM. +| Keyword | Change | Justification | Possible revert | +|---------|--------|---------------|-----------------| +| `CS_OPT_SYNTAX_NO_DOLLAR` | Adds options which removes the `$` (dollar sign) from the register name. | New Feature | Enable option. | +| `CS_OPT_SYNTAX_NOREGNAME` | Implements the options to output raw register numbers (only the standard GPR are numeric). | Was not implemented | Enable option. | +| `cs_mips_op.uimm` | Access for the unsigned immediate value of the IMM operand. | Was missing | None. | +| `cs_mips_op.is_unsigned` | Defines if the IMM operand is signed (when false) or unsigned (when true). | Was missing | None. | +| `cs_mips_op.is_reglist` | Defines if the REG operand is part of a list of registers. | Was missing | None. | +| `cs_mips_op.access` | Defines how is this operand accessed, i.e. READ, WRITE or READ & WRITE. | Was missing | None. | + +**SystemZ** + +| Keyword | Change | Justification | Possible revert | +|---------|--------|---------------|-----------------| +| `SYSTEMZ_CC_*` | `SYSTEMZ_CC_O = 0` and `SYSTEMZ_CC_INVALID != 0` | They match the same LLVM values. Better for LLVM compatibility and code generation. | Change by hand. | -Because this would completely break maintaining Capstone `v6` and `pre-v6` in a project, we added two solutions: +**Note about AArch64 and SystemZ** + +`ARM64` was everywhere renamed to `AArch64`. And `SYSZ` to `SYSTEMZ`. This is a necessity to ensure that the update scripts stay reasonably simple. +Capstone was very inconsistent with the naming before (sometimes `AArch64` sometimes `ARM64`. Sometimes `SYSZ` sometimes `SYSTEMZ`). +Because Capstone uses a huge amount of LLVM code, we renamed everything to `AArch64` and `SystemZ`. This reduces complexity enormously because it follows the naming of LLVM. + +Because this would completely break maintaining Capstone `v6` and `pre-v6` in a project, we added compatibility headers: 1. Make `arm64.h` a compatibility header which merely maps every member to the one in the `aarch64.h` header. -2. Macros for meta-programming which select the right name. +2. The `systemz.h` header includes the `SYSZ` to `SYSZTEMZ` mapping if `CAPSTONE_SYSTEMZ_COMPAT_HEADER` is defined. -We will continue to maintain both solutions. -So if you need to support the previous version of Capstone as well, you can use either of the solutions. +We will continue to maintain both headers. _Compatibility header_ -If you want to use the compatibility header and stick with the `ARM64` naming, you can define `CAPSTONE_AARCH64_COMPAT_HEADER` before including `capstone.h`. +If you want to use the compatibility header and stick with the `ARM64`/`SYSZ` naming, you can define `CAPSTONE_AARCH64_COMPAT_HEADER` and `CAPSTONE_SYSTEMZ_COMPAT_HEADER` before including `capstone.h`. ```c +#define CAPSTONE_SYSTEMZ_COMPAT_HEADER #define CAPSTONE_AARCH64_COMPAT_HEADER #include @@ -108,6 +182,7 @@ If you want to use the compatibility header and stick with the `ARM64` naming, y _Meta programming macros_ The following `sed` commands in a sh script should ease the replacement of `ARM64` with the macros a lot. +These macros are also part of the latest `v4` and `v5` release. ```sh #!/bin/sh @@ -137,6 +212,8 @@ echo "Replace detail->arm64" sed -i -E "s/detail->arm64/detail->CS_aarch64()/g" $1 ``` +_Example renaming with `sed`_ + Simple renaming from `ARM64` to `AArch64`: ```sh @@ -165,19 +242,34 @@ echo "Replace detail->arm64" sed -i "s|detail->arm64|detail->aarch64|g" $1 ``` -Write it into `rename_arm64.sh` and run it on files with `sh rename_arm64.sh ` +Simple renaming from `SYSZ` to `SYSTEMZ`: +```sh +#!/bin/sh +echo "Replace enum names" -**Mips** +sed -i "s|CS_ARCH_SYSZ|CS_ARCH_SYSTEMZ|g" $1 +sed -i "s|SYSZ_INS_|SYSTEMZ_INS_|g" $1 +sed -i "s|SYSZ_REG_|SYSTEMZ_REG_|g" $1 +sed -i "s|SYSZ_OP_|SYSTEMZ_OP_|g" $1 +sed -i "s|SYSZ_CC_|SYSTEMZ_CC_|g" $1 -| Keyword | Change | Justification | Possible revert | -|---------|--------|---------------|-----------------| -| `CS_OPT_SYNTAX_NO_DOLLAR` | Adds options which removes the `$` (dollar sign) from the register name. | New Feature | Enable option. | -| `CS_OPT_SYNTAX_NOREGNAME` | Implements the options to output raw register numbers (only the standard GPR are numeric). | Was not implemented | Enable option. | -| `cs_mips_op.uimm` | Access for the unsigned immediate value of the IMM operand. | Was missing | None. | -| `cs_mips_op.is_unsigned` | Defines if the IMM operand is signed (when false) or unsigned (when true). | Was missing | None. | -| `cs_mips_op.is_reglist` | Defines if the REG operand is part of a list of registers. | Was missing | None. | -| `cs_mips_op.access` | Defines how is this operand accessed, i.e. READ, WRITE or READ & WRITE. | Was missing | None. | +echo "Replace type identifiers" + +sed -i "s|sysz_reg|systemz_reg|g" $1 +sed -i "s|sysz_cc |systemz_cc |g" $1 +sed -i "s|cs_sysz|cs_systemz|g" $1 +sed -i "s|sysz_op_type|systemz_op_type|g" $1 +sed -i "s|sysz_op_type|systemz_op_type|g" $1 +sed -i "s|sysz_op_mem|systemz_op_mem|g" $1 +sed -i "s|sysz_op|systemz_op|g" $1 + +echo "Replace detail->sysz" + +sed -i "s|detail->sysz|detail->systemz|g" $1 +``` + +Write it into `rename_arm64.sh` and run it on files with `sh rename_arm64.sh ` **Note about AArch64** @@ -340,4 +432,4 @@ $ cstool -s arm 0c100097000000008fa2000034213456 4 00 00 00 00 andeq r0, r0, r0 8 8f a2 00 00 andeq r10, r0, pc, lsl #5 10 34 21 34 56 shasxpl r2, r4, r4 -``` \ No newline at end of file +``` diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h index 6fa23162ed..440d91e7df 100644 --- a/include/capstone/capstone.h +++ b/include/capstone/capstone.h @@ -139,12 +139,16 @@ typedef enum cs_arch { CS_ARCH_ARM64 = 1, ///< ARM64 #else CS_ARCH_AARCH64 = 1, ///< AArch64 +#endif +#ifdef CAPSTONE_SYSTEMZ_COMPAT_HEADER + CS_ARCH_SYSZ = 2, ///< SystemZ architecture +#else + CS_ARCH_SYSTEMZ = 2, ///< SystemZ architecture #endif CS_ARCH_MIPS, ///< Mips architecture CS_ARCH_X86, ///< X86 architecture (including x86 & x86-64) CS_ARCH_PPC, ///< PowerPC architecture CS_ARCH_SPARC, ///< Sparc architecture - CS_ARCH_SYSZ, ///< SystemZ architecture CS_ARCH_XCORE, ///< XCore architecture CS_ARCH_M68K, ///< 68K architecture CS_ARCH_TMS320C64X, ///< TMS320C64x architecture @@ -263,6 +267,21 @@ typedef enum cs_mode { CS_MODE_HPPA_20W = CS_MODE_HPPA_20 | (1 << 3), ///< HPPA 2.0 wide CS_MODE_LOONGARCH32 = 1 << 0, ///< LoongArch32 CS_MODE_LOONGARCH64 = 1 << 1, ///< LoongArch64 + CS_MODE_SYSTEMZ_ARCH8 = 1 << 1, ///< Enables features of the ARCH8 processor + CS_MODE_SYSTEMZ_ARCH9 = 1 << 2, ///< Enables features of the ARCH9 processor + CS_MODE_SYSTEMZ_ARCH10 = 1 << 3, ///< Enables features of the ARCH10 processor + CS_MODE_SYSTEMZ_ARCH11 = 1 << 4, ///< Enables features of the ARCH11 processor + CS_MODE_SYSTEMZ_ARCH12 = 1 << 5, ///< Enables features of the ARCH12 processor + CS_MODE_SYSTEMZ_ARCH13 = 1 << 6, ///< Enables features of the ARCH13 processor + CS_MODE_SYSTEMZ_ARCH14 = 1 << 7, ///< Enables features of the ARCH14 processor + CS_MODE_SYSTEMZ_Z10 = 1 << 8, ///< Enables features of the Z10 processor + CS_MODE_SYSTEMZ_Z196 = 1 << 9, ///< Enables features of the Z196 processor + CS_MODE_SYSTEMZ_ZEC12 = 1 << 10, ///< Enables features of the ZEC12 processor + CS_MODE_SYSTEMZ_Z13 = 1 << 11, ///< Enables features of the Z13 processor + CS_MODE_SYSTEMZ_Z14 = 1 << 12, ///< Enables features of the Z14 processor + CS_MODE_SYSTEMZ_Z15 = 1 << 13, ///< Enables features of the Z15 processor + CS_MODE_SYSTEMZ_Z16 = 1 << 14, ///< Enables features of the Z16 processor + CS_MODE_SYSTEMZ_GENERIC = 1 << 15, ///< Enables features of the generic processor } cs_mode; typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size); @@ -451,12 +470,17 @@ typedef struct cs_detail { #else cs_aarch64 aarch64; ///< AArch6464 architecture (aka ARM64) #endif + +#ifdef CAPSTONE_SYSTEMZ_COMPAT_HEADER + cs_sysz sysz; ///< SystemZ architecture +#else + cs_systemz systemz; ///< SystemZ architecture (aka SysZ) +#endif cs_arm arm; ///< ARM architecture (including Thumb/Thumb2) cs_m68k m68k; ///< M68K architecture cs_mips mips; ///< MIPS architecture cs_ppc ppc; ///< PowerPC architecture cs_sparc sparc; ///< Sparc architecture - cs_sysz sysz; ///< SystemZ architecture cs_xcore xcore; ///< XCore architecture cs_tms320c64x tms320c64x; ///< TMS320C64x architecture cs_m680x m680x; ///< M680X architecture @@ -591,7 +615,10 @@ void CAPSTONE_API cs_arch_register_powerpc(void); CAPSTONE_EXPORT void CAPSTONE_API cs_arch_register_sparc(void); CAPSTONE_EXPORT -void CAPSTONE_API cs_arch_register_sysz(void); +void CAPSTONE_API cs_arch_register_systemz(void); +#ifdef CAPSTONE_SYSTEMZ_COMPAT_HEADER +#define cs_arch_register_sysz cs_arch_register_systemz +#endif CAPSTONE_EXPORT void CAPSTONE_API cs_arch_register_xcore(void); CAPSTONE_EXPORT diff --git a/include/capstone/systemz.h b/include/capstone/systemz.h index 5be27df45b..8a1c5641dc 100644 --- a/include/capstone/systemz.h +++ b/include/capstone/systemz.h @@ -3,2596 +3,3023 @@ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2014-2015 */ +/* By Rot127 , 2024 */ #ifdef __cplusplus extern "C" { #endif #include "platform.h" - -#ifdef _MSC_VER -#pragma warning(disable:4201) -#endif +#include "cs_operand.h" /// Enums corresponding to SystemZ condition codes -typedef enum sysz_cc { - SYSZ_CC_INVALID = 0, ///< invalid CC (default) - - SYSZ_CC_O, - SYSZ_CC_H, - SYSZ_CC_NLE, - SYSZ_CC_L, - SYSZ_CC_NHE, - SYSZ_CC_LH, - SYSZ_CC_NE, - SYSZ_CC_E, - SYSZ_CC_NLH, - SYSZ_CC_HE, - SYSZ_CC_NL, - SYSZ_CC_LE, - SYSZ_CC_NH, - SYSZ_CC_NO, -} sysz_cc; +typedef enum systemz_cc { + SYSTEMZ_CC_O, + SYSTEMZ_CC_H, + SYSTEMZ_CC_NLE, + SYSTEMZ_CC_L, + SYSTEMZ_CC_NHE, + SYSTEMZ_CC_LH, + SYSTEMZ_CC_NE, + SYSTEMZ_CC_E, + SYSTEMZ_CC_NLH, + SYSTEMZ_CC_HE, + SYSTEMZ_CC_NL, + SYSTEMZ_CC_LE, + SYSTEMZ_CC_NH, + SYSTEMZ_CC_NO, + SYSTEMZ_CC_INVALID, +} systemz_cc; /// Operand type for instruction's operands -typedef enum sysz_op_type { - SYSZ_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). - SYSZ_OP_REG, ///< = CS_OP_REG (Register operand). - SYSZ_OP_IMM, ///< = CS_OP_IMM (Immediate operand). - SYSZ_OP_MEM, ///< = CS_OP_MEM (Memory operand). - SYSZ_OP_ACREG = 64, ///< Access register operand. -} sysz_op_type; +typedef enum systemz_op_type { + SYSTEMZ_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized). + SYSTEMZ_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand). + SYSTEMZ_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand). + SYSTEMZ_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand). +} systemz_op_type; /// SystemZ registers -typedef enum sysz_reg { - SYSZ_REG_INVALID = 0, +typedef enum systemz_reg { + // generated content begin + // clang-format off + + SYSTEMZ_REG_INVALID = 0, + SYSTEMZ_REG_CC = 1, + SYSTEMZ_REG_FPC = 2, + SYSTEMZ_REG_A0 = 3, + SYSTEMZ_REG_A1 = 4, + SYSTEMZ_REG_A2 = 5, + SYSTEMZ_REG_A3 = 6, + SYSTEMZ_REG_A4 = 7, + SYSTEMZ_REG_A5 = 8, + SYSTEMZ_REG_A6 = 9, + SYSTEMZ_REG_A7 = 10, + SYSTEMZ_REG_A8 = 11, + SYSTEMZ_REG_A9 = 12, + SYSTEMZ_REG_A10 = 13, + SYSTEMZ_REG_A11 = 14, + SYSTEMZ_REG_A12 = 15, + SYSTEMZ_REG_A13 = 16, + SYSTEMZ_REG_A14 = 17, + SYSTEMZ_REG_A15 = 18, + SYSTEMZ_REG_C0 = 19, + SYSTEMZ_REG_C1 = 20, + SYSTEMZ_REG_C2 = 21, + SYSTEMZ_REG_C3 = 22, + SYSTEMZ_REG_C4 = 23, + SYSTEMZ_REG_C5 = 24, + SYSTEMZ_REG_C6 = 25, + SYSTEMZ_REG_C7 = 26, + SYSTEMZ_REG_C8 = 27, + SYSTEMZ_REG_C9 = 28, + SYSTEMZ_REG_C10 = 29, + SYSTEMZ_REG_C11 = 30, + SYSTEMZ_REG_C12 = 31, + SYSTEMZ_REG_C13 = 32, + SYSTEMZ_REG_C14 = 33, + SYSTEMZ_REG_C15 = 34, + SYSTEMZ_REG_V0 = 35, + SYSTEMZ_REG_V1 = 36, + SYSTEMZ_REG_V2 = 37, + SYSTEMZ_REG_V3 = 38, + SYSTEMZ_REG_V4 = 39, + SYSTEMZ_REG_V5 = 40, + SYSTEMZ_REG_V6 = 41, + SYSTEMZ_REG_V7 = 42, + SYSTEMZ_REG_V8 = 43, + SYSTEMZ_REG_V9 = 44, + SYSTEMZ_REG_V10 = 45, + SYSTEMZ_REG_V11 = 46, + SYSTEMZ_REG_V12 = 47, + SYSTEMZ_REG_V13 = 48, + SYSTEMZ_REG_V14 = 49, + SYSTEMZ_REG_V15 = 50, + SYSTEMZ_REG_V16 = 51, + SYSTEMZ_REG_V17 = 52, + SYSTEMZ_REG_V18 = 53, + SYSTEMZ_REG_V19 = 54, + SYSTEMZ_REG_V20 = 55, + SYSTEMZ_REG_V21 = 56, + SYSTEMZ_REG_V22 = 57, + SYSTEMZ_REG_V23 = 58, + SYSTEMZ_REG_V24 = 59, + SYSTEMZ_REG_V25 = 60, + SYSTEMZ_REG_V26 = 61, + SYSTEMZ_REG_V27 = 62, + SYSTEMZ_REG_V28 = 63, + SYSTEMZ_REG_V29 = 64, + SYSTEMZ_REG_V30 = 65, + SYSTEMZ_REG_V31 = 66, + SYSTEMZ_REG_F0D = 67, + SYSTEMZ_REG_F1D = 68, + SYSTEMZ_REG_F2D = 69, + SYSTEMZ_REG_F3D = 70, + SYSTEMZ_REG_F4D = 71, + SYSTEMZ_REG_F5D = 72, + SYSTEMZ_REG_F6D = 73, + SYSTEMZ_REG_F7D = 74, + SYSTEMZ_REG_F8D = 75, + SYSTEMZ_REG_F9D = 76, + SYSTEMZ_REG_F10D = 77, + SYSTEMZ_REG_F11D = 78, + SYSTEMZ_REG_F12D = 79, + SYSTEMZ_REG_F13D = 80, + SYSTEMZ_REG_F14D = 81, + SYSTEMZ_REG_F15D = 82, + SYSTEMZ_REG_F16D = 83, + SYSTEMZ_REG_F17D = 84, + SYSTEMZ_REG_F18D = 85, + SYSTEMZ_REG_F19D = 86, + SYSTEMZ_REG_F20D = 87, + SYSTEMZ_REG_F21D = 88, + SYSTEMZ_REG_F22D = 89, + SYSTEMZ_REG_F23D = 90, + SYSTEMZ_REG_F24D = 91, + SYSTEMZ_REG_F25D = 92, + SYSTEMZ_REG_F26D = 93, + SYSTEMZ_REG_F27D = 94, + SYSTEMZ_REG_F28D = 95, + SYSTEMZ_REG_F29D = 96, + SYSTEMZ_REG_F30D = 97, + SYSTEMZ_REG_F31D = 98, + SYSTEMZ_REG_F0Q = 99, + SYSTEMZ_REG_F1Q = 100, + SYSTEMZ_REG_F4Q = 101, + SYSTEMZ_REG_F5Q = 102, + SYSTEMZ_REG_F8Q = 103, + SYSTEMZ_REG_F9Q = 104, + SYSTEMZ_REG_F12Q = 105, + SYSTEMZ_REG_F13Q = 106, + SYSTEMZ_REG_F0S = 107, + SYSTEMZ_REG_F1S = 108, + SYSTEMZ_REG_F2S = 109, + SYSTEMZ_REG_F3S = 110, + SYSTEMZ_REG_F4S = 111, + SYSTEMZ_REG_F5S = 112, + SYSTEMZ_REG_F6S = 113, + SYSTEMZ_REG_F7S = 114, + SYSTEMZ_REG_F8S = 115, + SYSTEMZ_REG_F9S = 116, + SYSTEMZ_REG_F10S = 117, + SYSTEMZ_REG_F11S = 118, + SYSTEMZ_REG_F12S = 119, + SYSTEMZ_REG_F13S = 120, + SYSTEMZ_REG_F14S = 121, + SYSTEMZ_REG_F15S = 122, + SYSTEMZ_REG_F16S = 123, + SYSTEMZ_REG_F17S = 124, + SYSTEMZ_REG_F18S = 125, + SYSTEMZ_REG_F19S = 126, + SYSTEMZ_REG_F20S = 127, + SYSTEMZ_REG_F21S = 128, + SYSTEMZ_REG_F22S = 129, + SYSTEMZ_REG_F23S = 130, + SYSTEMZ_REG_F24S = 131, + SYSTEMZ_REG_F25S = 132, + SYSTEMZ_REG_F26S = 133, + SYSTEMZ_REG_F27S = 134, + SYSTEMZ_REG_F28S = 135, + SYSTEMZ_REG_F29S = 136, + SYSTEMZ_REG_F30S = 137, + SYSTEMZ_REG_F31S = 138, + SYSTEMZ_REG_R0D = 139, + SYSTEMZ_REG_R1D = 140, + SYSTEMZ_REG_R2D = 141, + SYSTEMZ_REG_R3D = 142, + SYSTEMZ_REG_R4D = 143, + SYSTEMZ_REG_R5D = 144, + SYSTEMZ_REG_R6D = 145, + SYSTEMZ_REG_R7D = 146, + SYSTEMZ_REG_R8D = 147, + SYSTEMZ_REG_R9D = 148, + SYSTEMZ_REG_R10D = 149, + SYSTEMZ_REG_R11D = 150, + SYSTEMZ_REG_R12D = 151, + SYSTEMZ_REG_R13D = 152, + SYSTEMZ_REG_R14D = 153, + SYSTEMZ_REG_R15D = 154, + SYSTEMZ_REG_R0H = 155, + SYSTEMZ_REG_R1H = 156, + SYSTEMZ_REG_R2H = 157, + SYSTEMZ_REG_R3H = 158, + SYSTEMZ_REG_R4H = 159, + SYSTEMZ_REG_R5H = 160, + SYSTEMZ_REG_R6H = 161, + SYSTEMZ_REG_R7H = 162, + SYSTEMZ_REG_R8H = 163, + SYSTEMZ_REG_R9H = 164, + SYSTEMZ_REG_R10H = 165, + SYSTEMZ_REG_R11H = 166, + SYSTEMZ_REG_R12H = 167, + SYSTEMZ_REG_R13H = 168, + SYSTEMZ_REG_R14H = 169, + SYSTEMZ_REG_R15H = 170, + SYSTEMZ_REG_R0L = 171, + SYSTEMZ_REG_R1L = 172, + SYSTEMZ_REG_R2L = 173, + SYSTEMZ_REG_R3L = 174, + SYSTEMZ_REG_R4L = 175, + SYSTEMZ_REG_R5L = 176, + SYSTEMZ_REG_R6L = 177, + SYSTEMZ_REG_R7L = 178, + SYSTEMZ_REG_R8L = 179, + SYSTEMZ_REG_R9L = 180, + SYSTEMZ_REG_R10L = 181, + SYSTEMZ_REG_R11L = 182, + SYSTEMZ_REG_R12L = 183, + SYSTEMZ_REG_R13L = 184, + SYSTEMZ_REG_R14L = 185, + SYSTEMZ_REG_R15L = 186, + SYSTEMZ_REG_R0Q = 187, + SYSTEMZ_REG_R2Q = 188, + SYSTEMZ_REG_R4Q = 189, + SYSTEMZ_REG_R6Q = 190, + SYSTEMZ_REG_R8Q = 191, + SYSTEMZ_REG_R10Q = 192, + SYSTEMZ_REG_R12Q = 193, + SYSTEMZ_REG_R14Q = 194, + SYSTEMZ_REG_ENDING, // 195 + + // clang-format on + // generated content end - SYSZ_REG_0, - SYSZ_REG_1, - SYSZ_REG_2, - SYSZ_REG_3, - SYSZ_REG_4, - SYSZ_REG_5, - SYSZ_REG_6, - SYSZ_REG_7, - SYSZ_REG_8, - SYSZ_REG_9, - SYSZ_REG_10, - SYSZ_REG_11, - SYSZ_REG_12, - SYSZ_REG_13, - SYSZ_REG_14, - SYSZ_REG_15, - SYSZ_REG_CC, - SYSZ_REG_F0, - SYSZ_REG_F1, - SYSZ_REG_F2, - SYSZ_REG_F3, - SYSZ_REG_F4, - SYSZ_REG_F5, - SYSZ_REG_F6, - SYSZ_REG_F7, - SYSZ_REG_F8, - SYSZ_REG_F9, - SYSZ_REG_F10, - SYSZ_REG_F11, - SYSZ_REG_F12, - SYSZ_REG_F13, - SYSZ_REG_F14, - SYSZ_REG_F15, + // alias registers + // None +} systemz_reg; - SYSZ_REG_R0L, +typedef enum { + SYSTEMZ_INSN_FORM_INVALID = 0, + // generated content begin + // clang-format off - SYSZ_REG_A0, - SYSZ_REG_A1, - SYSZ_REG_A2, - SYSZ_REG_A3, - SYSZ_REG_A4, - SYSZ_REG_A5, - SYSZ_REG_A6, - SYSZ_REG_A7, - SYSZ_REG_A8, - SYSZ_REG_A9, - SYSZ_REG_A10, - SYSZ_REG_A11, - SYSZ_REG_A12, - SYSZ_REG_A13, - SYSZ_REG_A14, - SYSZ_REG_A15, - SYSZ_REG_C0, - SYSZ_REG_C1, - SYSZ_REG_C2, - SYSZ_REG_C3, - SYSZ_REG_C4, - SYSZ_REG_C5, - SYSZ_REG_C6, - SYSZ_REG_C7, - SYSZ_REG_C8, - SYSZ_REG_C9, - SYSZ_REG_C10, - SYSZ_REG_C11, - SYSZ_REG_C12, - SYSZ_REG_C13, - SYSZ_REG_C14, - SYSZ_REG_C15, - SYSZ_REG_V0, - SYSZ_REG_V1, - SYSZ_REG_V2, - SYSZ_REG_V3, - SYSZ_REG_V4, - SYSZ_REG_V5, - SYSZ_REG_V6, - SYSZ_REG_V7, - SYSZ_REG_V8, - SYSZ_REG_V9, - SYSZ_REG_V10, - SYSZ_REG_V11, - SYSZ_REG_V12, - SYSZ_REG_V13, - SYSZ_REG_V14, - SYSZ_REG_V15, - SYSZ_REG_V16, - SYSZ_REG_V17, - SYSZ_REG_V18, - SYSZ_REG_V19, - SYSZ_REG_V20, - SYSZ_REG_V21, - SYSZ_REG_V22, - SYSZ_REG_V23, - SYSZ_REG_V24, - SYSZ_REG_V25, - SYSZ_REG_V26, - SYSZ_REG_V27, - SYSZ_REG_V28, - SYSZ_REG_V29, - SYSZ_REG_V30, - SYSZ_REG_V31, - SYSZ_REG_F16, - SYSZ_REG_F17, - SYSZ_REG_F18, - SYSZ_REG_F19, - SYSZ_REG_F20, - SYSZ_REG_F21, - SYSZ_REG_F22, - SYSZ_REG_F23, - SYSZ_REG_F24, - SYSZ_REG_F25, - SYSZ_REG_F26, - SYSZ_REG_F27, - SYSZ_REG_F28, - SYSZ_REG_F29, - SYSZ_REG_F30, - SYSZ_REG_F31, - SYSZ_REG_F0Q, - SYSZ_REG_F4Q, + SYSTEMZ_INSN_FORM_INSTRXA, + SYSTEMZ_INSN_FORM_INSTRXE, + SYSTEMZ_INSN_FORM_INSTRRE, + SYSTEMZ_INSN_FORM_INSTRR, + SYSTEMZ_INSN_FORM_INSTRRFA, + SYSTEMZ_INSN_FORM_INSTRILA, + SYSTEMZ_INSN_FORM_INSTRXYA, + SYSTEMZ_INSN_FORM_INSTRIA, + SYSTEMZ_INSN_FORM_INSTRIED, + SYSTEMZ_INSN_FORM_INSTSIY, + SYSTEMZ_INSN_FORM_INSTSSB, + SYSTEMZ_INSN_FORM_INSTRXB, + SYSTEMZ_INSN_FORM_INSTRXYB, + SYSTEMZ_INSN_FORM_INSTSMI, + SYSTEMZ_INSN_FORM_INSTMII, + SYSTEMZ_INSN_FORM_INSTRIB, + SYSTEMZ_INSN_FORM_INSTRILB, + SYSTEMZ_INSN_FORM_INSTRIC, + SYSTEMZ_INSN_FORM_INSTRILC, + SYSTEMZ_INSN_FORM_INSTRSI, + SYSTEMZ_INSN_FORM_INSTRIEE, + SYSTEMZ_INSN_FORM_INSTRSA, + SYSTEMZ_INSN_FORM_INSTRSYA, + SYSTEMZ_INSN_FORM_INSTRRFE, + SYSTEMZ_INSN_FORM_INSTRSLB, + SYSTEMZ_INSN_FORM_INSTS, + SYSTEMZ_INSN_FORM_INSTSIL, + SYSTEMZ_INSN_FORM_INSTRIS, + SYSTEMZ_INSN_FORM_INSTRIEC, + SYSTEMZ_INSN_FORM_INSTRIEA, + SYSTEMZ_INSN_FORM_INSTRRS, + SYSTEMZ_INSN_FORM_INSTRIEB, + SYSTEMZ_INSN_FORM_INSTRRFC, + SYSTEMZ_INSN_FORM_INSTSSA, + SYSTEMZ_INSN_FORM_INSTRSYB, + SYSTEMZ_INSN_FORM_INSTSI, + SYSTEMZ_INSN_FORM_INSTRSB, + SYSTEMZ_INSN_FORM_INSTRRFB, + SYSTEMZ_INSN_FORM_INSTRRFD, + SYSTEMZ_INSN_FORM_INSTSSF, + SYSTEMZ_INSN_FORM_INSTSSE, + SYSTEMZ_INSN_FORM_INSTRIEG, + SYSTEMZ_INSN_FORM_INSTRXF, + SYSTEMZ_INSN_FORM_INSTRRD, + SYSTEMZ_INSN_FORM_INSTSSD, + SYSTEMZ_INSN_FORM_INSTIE, + SYSTEMZ_INSN_FORM_INSTE, + SYSTEMZ_INSN_FORM_INSTRIEF, + SYSTEMZ_INSN_FORM_INSTSSC, + SYSTEMZ_INSN_FORM_INSTI, + SYSTEMZ_INSN_FORM_INSTRSLA, + SYSTEMZ_INSN_FORM_INSTVRRC, + SYSTEMZ_INSN_FORM_INSTVRRD, + SYSTEMZ_INSN_FORM_INSTVRIF, + SYSTEMZ_INSN_FORM_INSTVRRA, + SYSTEMZ_INSN_FORM_INSTVRRB, + SYSTEMZ_INSN_FORM_INSTVRRK, + SYSTEMZ_INSN_FORM_INSTVRRH, + SYSTEMZ_INSN_FORM_INSTVRRJ, + SYSTEMZ_INSN_FORM_INSTVRRI, + SYSTEMZ_INSN_FORM_INSTVRII, + SYSTEMZ_INSN_FORM_INSTVRID, + SYSTEMZ_INSN_FORM_INSTVRSA, + SYSTEMZ_INSN_FORM_INSTVRRE, + SYSTEMZ_INSN_FORM_INSTVRIE, + SYSTEMZ_INSN_FORM_INSTVRIA, + SYSTEMZ_INSN_FORM_INSTVRV, + SYSTEMZ_INSN_FORM_INSTVRIB, + SYSTEMZ_INSN_FORM_INSTVRX, + SYSTEMZ_INSN_FORM_INSTVRSC, + SYSTEMZ_INSN_FORM_INSTVRIH, + SYSTEMZ_INSN_FORM_INSTVRSB, + SYSTEMZ_INSN_FORM_INSTVSI, + SYSTEMZ_INSN_FORM_INSTVRSD, + SYSTEMZ_INSN_FORM_INSTVRRF, + SYSTEMZ_INSN_FORM_INSTVRIG, + SYSTEMZ_INSN_FORM_INSTVRIC, + SYSTEMZ_INSN_FORM_INSTVRRG, - SYSZ_REG_ENDING, -} sysz_reg; + // clang-format on + // generated content end + +} systemz_insn_form; + +typedef enum { + SYSTEMZ_AM_INVALID = 0, + SYSTEMZ_AM_BD, ///< Base and displacement are set. + SYSTEMZ_AM_BDX, ///< Base, displacement and index register are set. + SYSTEMZ_AM_BDL, ///< Base, displacement and length (immediate) are set. + SYSTEMZ_AM_BDR, ///< Base, displacement and length (register) are set. + SYSTEMZ_AM_BDV, ///< Base, displacement and index vector register are set. +} systemz_addr_mode; + +typedef struct { + systemz_insn_form form; +} systemz_suppl_info; /// Instruction's operand referring to memory -/// This is associated with SYSZ_OP_MEM operand type above -typedef struct sysz_op_mem { - uint8_t base; ///< base register, can be safely interpreted as - ///< a value of type `sysz_reg`, but it is only +/// This is associated with SYSTEMZ_OP_MEM operand type above +typedef struct systemz_op_mem { + systemz_addr_mode am; ///< Address mode. Indicates which field below are set. + uint8_t /* systemz_reg */ base; ///< base register, can be safely interpreted as + ///< a value of type `systemz_reg`, but it is only ///< one byte wide - uint8_t index; ///< index register, same conditions apply here - uint64_t length; ///< BDLAddr operand + uint8_t /* systemz_reg */ index; ///< Index register, same conditions apply here + uint64_t length; ///< Length component. Can be a register or immediate. int64_t disp; ///< displacement/offset value -} sysz_op_mem; +} systemz_op_mem; /// Instruction operand -typedef struct cs_sysz_op { - sysz_op_type type; ///< operand type +typedef struct cs_systemz_op { + systemz_op_type type; ///< operand type union { - sysz_reg reg; ///< register value for REG operand + systemz_reg reg; ///< register value for REG operand int64_t imm; ///< immediate value for IMM operand - sysz_op_mem mem; ///< base/disp value for MEM operand + systemz_op_mem mem; ///< base/disp value for MEM operand }; -} cs_sysz_op; + cs_ac_type access; ///< R/W access of the operand. + uint8_t imm_width; ///< Bit width of the immediate. 0 if not specified. +} cs_systemz_op; + +#define MAX_SYSTEMZ_OPS 6 // Instruction structure -typedef struct cs_sysz { - sysz_cc cc; ///< Code condition +typedef struct cs_systemz { + systemz_cc cc; ///< Code condition + systemz_insn_form format; ///< The instruction format. /// Number of operands of this instruction, /// or 0 when instruction has no operand. uint8_t op_count; - cs_sysz_op operands[6]; ///< operands for this instruction. -} cs_sysz; + cs_systemz_op operands[MAX_SYSTEMZ_OPS]; ///< operands for this instruction. +} cs_systemz; /// SystemZ instruction -typedef enum sysz_insn { - SYSZ_INS_INVALID = 0, +typedef enum systemz_insn { + // generated content begin + // clang-format off - SYSZ_INS_A, - SYSZ_INS_ADB, - SYSZ_INS_ADBR, - SYSZ_INS_AEB, - SYSZ_INS_AEBR, - SYSZ_INS_AFI, - SYSZ_INS_AG, - SYSZ_INS_AGF, - SYSZ_INS_AGFI, - SYSZ_INS_AGFR, - SYSZ_INS_AGHI, - SYSZ_INS_AGHIK, - SYSZ_INS_AGR, - SYSZ_INS_AGRK, - SYSZ_INS_AGSI, - SYSZ_INS_AH, - SYSZ_INS_AHI, - SYSZ_INS_AHIK, - SYSZ_INS_AHY, - SYSZ_INS_AIH, - SYSZ_INS_AL, - SYSZ_INS_ALC, - SYSZ_INS_ALCG, - SYSZ_INS_ALCGR, - SYSZ_INS_ALCR, - SYSZ_INS_ALFI, - SYSZ_INS_ALG, - SYSZ_INS_ALGF, - SYSZ_INS_ALGFI, - SYSZ_INS_ALGFR, - SYSZ_INS_ALGHSIK, - SYSZ_INS_ALGR, - SYSZ_INS_ALGRK, - SYSZ_INS_ALHSIK, - SYSZ_INS_ALR, - SYSZ_INS_ALRK, - SYSZ_INS_ALY, - SYSZ_INS_AR, - SYSZ_INS_ARK, - SYSZ_INS_ASI, - SYSZ_INS_AXBR, - SYSZ_INS_AY, - SYSZ_INS_BCR, - SYSZ_INS_BRC, - SYSZ_INS_BRCL, - SYSZ_INS_CGIJ, - SYSZ_INS_CGRJ, - SYSZ_INS_CIJ, - SYSZ_INS_CLGIJ, - SYSZ_INS_CLGRJ, - SYSZ_INS_CLIJ, - SYSZ_INS_CLRJ, - SYSZ_INS_CRJ, - SYSZ_INS_BER, - SYSZ_INS_JE, - SYSZ_INS_JGE, - SYSZ_INS_LOCE, - SYSZ_INS_LOCGE, - SYSZ_INS_LOCGRE, - SYSZ_INS_LOCRE, - SYSZ_INS_STOCE, - SYSZ_INS_STOCGE, - SYSZ_INS_BHR, - SYSZ_INS_BHER, - SYSZ_INS_JHE, - SYSZ_INS_JGHE, - SYSZ_INS_LOCHE, - SYSZ_INS_LOCGHE, - SYSZ_INS_LOCGRHE, - SYSZ_INS_LOCRHE, - SYSZ_INS_STOCHE, - SYSZ_INS_STOCGHE, - SYSZ_INS_JH, - SYSZ_INS_JGH, - SYSZ_INS_LOCH, - SYSZ_INS_LOCGH, - SYSZ_INS_LOCGRH, - SYSZ_INS_LOCRH, - SYSZ_INS_STOCH, - SYSZ_INS_STOCGH, - SYSZ_INS_CGIJNLH, - SYSZ_INS_CGRJNLH, - SYSZ_INS_CIJNLH, - SYSZ_INS_CLGIJNLH, - SYSZ_INS_CLGRJNLH, - SYSZ_INS_CLIJNLH, - SYSZ_INS_CLRJNLH, - SYSZ_INS_CRJNLH, - SYSZ_INS_CGIJE, - SYSZ_INS_CGRJE, - SYSZ_INS_CIJE, - SYSZ_INS_CLGIJE, - SYSZ_INS_CLGRJE, - SYSZ_INS_CLIJE, - SYSZ_INS_CLRJE, - SYSZ_INS_CRJE, - SYSZ_INS_CGIJNLE, - SYSZ_INS_CGRJNLE, - SYSZ_INS_CIJNLE, - SYSZ_INS_CLGIJNLE, - SYSZ_INS_CLGRJNLE, - SYSZ_INS_CLIJNLE, - SYSZ_INS_CLRJNLE, - SYSZ_INS_CRJNLE, - SYSZ_INS_CGIJH, - SYSZ_INS_CGRJH, - SYSZ_INS_CIJH, - SYSZ_INS_CLGIJH, - SYSZ_INS_CLGRJH, - SYSZ_INS_CLIJH, - SYSZ_INS_CLRJH, - SYSZ_INS_CRJH, - SYSZ_INS_CGIJNL, - SYSZ_INS_CGRJNL, - SYSZ_INS_CIJNL, - SYSZ_INS_CLGIJNL, - SYSZ_INS_CLGRJNL, - SYSZ_INS_CLIJNL, - SYSZ_INS_CLRJNL, - SYSZ_INS_CRJNL, - SYSZ_INS_CGIJHE, - SYSZ_INS_CGRJHE, - SYSZ_INS_CIJHE, - SYSZ_INS_CLGIJHE, - SYSZ_INS_CLGRJHE, - SYSZ_INS_CLIJHE, - SYSZ_INS_CLRJHE, - SYSZ_INS_CRJHE, - SYSZ_INS_CGIJNHE, - SYSZ_INS_CGRJNHE, - SYSZ_INS_CIJNHE, - SYSZ_INS_CLGIJNHE, - SYSZ_INS_CLGRJNHE, - SYSZ_INS_CLIJNHE, - SYSZ_INS_CLRJNHE, - SYSZ_INS_CRJNHE, - SYSZ_INS_CGIJL, - SYSZ_INS_CGRJL, - SYSZ_INS_CIJL, - SYSZ_INS_CLGIJL, - SYSZ_INS_CLGRJL, - SYSZ_INS_CLIJL, - SYSZ_INS_CLRJL, - SYSZ_INS_CRJL, - SYSZ_INS_CGIJNH, - SYSZ_INS_CGRJNH, - SYSZ_INS_CIJNH, - SYSZ_INS_CLGIJNH, - SYSZ_INS_CLGRJNH, - SYSZ_INS_CLIJNH, - SYSZ_INS_CLRJNH, - SYSZ_INS_CRJNH, - SYSZ_INS_CGIJLE, - SYSZ_INS_CGRJLE, - SYSZ_INS_CIJLE, - SYSZ_INS_CLGIJLE, - SYSZ_INS_CLGRJLE, - SYSZ_INS_CLIJLE, - SYSZ_INS_CLRJLE, - SYSZ_INS_CRJLE, - SYSZ_INS_CGIJNE, - SYSZ_INS_CGRJNE, - SYSZ_INS_CIJNE, - SYSZ_INS_CLGIJNE, - SYSZ_INS_CLGRJNE, - SYSZ_INS_CLIJNE, - SYSZ_INS_CLRJNE, - SYSZ_INS_CRJNE, - SYSZ_INS_CGIJLH, - SYSZ_INS_CGRJLH, - SYSZ_INS_CIJLH, - SYSZ_INS_CLGIJLH, - SYSZ_INS_CLGRJLH, - SYSZ_INS_CLIJLH, - SYSZ_INS_CLRJLH, - SYSZ_INS_CRJLH, - SYSZ_INS_BLR, - SYSZ_INS_BLER, - SYSZ_INS_JLE, - SYSZ_INS_JGLE, - SYSZ_INS_LOCLE, - SYSZ_INS_LOCGLE, - SYSZ_INS_LOCGRLE, - SYSZ_INS_LOCRLE, - SYSZ_INS_STOCLE, - SYSZ_INS_STOCGLE, - SYSZ_INS_BLHR, - SYSZ_INS_JLH, - SYSZ_INS_JGLH, - SYSZ_INS_LOCLH, - SYSZ_INS_LOCGLH, - SYSZ_INS_LOCGRLH, - SYSZ_INS_LOCRLH, - SYSZ_INS_STOCLH, - SYSZ_INS_STOCGLH, - SYSZ_INS_JL, - SYSZ_INS_JGL, - SYSZ_INS_LOCL, - SYSZ_INS_LOCGL, - SYSZ_INS_LOCGRL, - SYSZ_INS_LOCRL, - SYSZ_INS_LOC, - SYSZ_INS_LOCG, - SYSZ_INS_LOCGR, - SYSZ_INS_LOCR, - SYSZ_INS_STOCL, - SYSZ_INS_STOCGL, - SYSZ_INS_BNER, - SYSZ_INS_JNE, - SYSZ_INS_JGNE, - SYSZ_INS_LOCNE, - SYSZ_INS_LOCGNE, - SYSZ_INS_LOCGRNE, - SYSZ_INS_LOCRNE, - SYSZ_INS_STOCNE, - SYSZ_INS_STOCGNE, - SYSZ_INS_BNHR, - SYSZ_INS_BNHER, - SYSZ_INS_JNHE, - SYSZ_INS_JGNHE, - SYSZ_INS_LOCNHE, - SYSZ_INS_LOCGNHE, - SYSZ_INS_LOCGRNHE, - SYSZ_INS_LOCRNHE, - SYSZ_INS_STOCNHE, - SYSZ_INS_STOCGNHE, - SYSZ_INS_JNH, - SYSZ_INS_JGNH, - SYSZ_INS_LOCNH, - SYSZ_INS_LOCGNH, - SYSZ_INS_LOCGRNH, - SYSZ_INS_LOCRNH, - SYSZ_INS_STOCNH, - SYSZ_INS_STOCGNH, - SYSZ_INS_BNLR, - SYSZ_INS_BNLER, - SYSZ_INS_JNLE, - SYSZ_INS_JGNLE, - SYSZ_INS_LOCNLE, - SYSZ_INS_LOCGNLE, - SYSZ_INS_LOCGRNLE, - SYSZ_INS_LOCRNLE, - SYSZ_INS_STOCNLE, - SYSZ_INS_STOCGNLE, - SYSZ_INS_BNLHR, - SYSZ_INS_JNLH, - SYSZ_INS_JGNLH, - SYSZ_INS_LOCNLH, - SYSZ_INS_LOCGNLH, - SYSZ_INS_LOCGRNLH, - SYSZ_INS_LOCRNLH, - SYSZ_INS_STOCNLH, - SYSZ_INS_STOCGNLH, - SYSZ_INS_JNL, - SYSZ_INS_JGNL, - SYSZ_INS_LOCNL, - SYSZ_INS_LOCGNL, - SYSZ_INS_LOCGRNL, - SYSZ_INS_LOCRNL, - SYSZ_INS_STOCNL, - SYSZ_INS_STOCGNL, - SYSZ_INS_BNOR, - SYSZ_INS_JNO, - SYSZ_INS_JGNO, - SYSZ_INS_LOCNO, - SYSZ_INS_LOCGNO, - SYSZ_INS_LOCGRNO, - SYSZ_INS_LOCRNO, - SYSZ_INS_STOCNO, - SYSZ_INS_STOCGNO, - SYSZ_INS_BOR, - SYSZ_INS_JO, - SYSZ_INS_JGO, - SYSZ_INS_LOCO, - SYSZ_INS_LOCGO, - SYSZ_INS_LOCGRO, - SYSZ_INS_LOCRO, - SYSZ_INS_STOCO, - SYSZ_INS_STOCGO, - SYSZ_INS_STOC, - SYSZ_INS_STOCG, - SYSZ_INS_BASR, - SYSZ_INS_BR, - SYSZ_INS_BRAS, - SYSZ_INS_BRASL, - SYSZ_INS_J, - SYSZ_INS_JG, - SYSZ_INS_BRCT, - SYSZ_INS_BRCTG, - SYSZ_INS_C, - SYSZ_INS_CDB, - SYSZ_INS_CDBR, - SYSZ_INS_CDFBR, - SYSZ_INS_CDGBR, - SYSZ_INS_CDLFBR, - SYSZ_INS_CDLGBR, - SYSZ_INS_CEB, - SYSZ_INS_CEBR, - SYSZ_INS_CEFBR, - SYSZ_INS_CEGBR, - SYSZ_INS_CELFBR, - SYSZ_INS_CELGBR, - SYSZ_INS_CFDBR, - SYSZ_INS_CFEBR, - SYSZ_INS_CFI, - SYSZ_INS_CFXBR, - SYSZ_INS_CG, - SYSZ_INS_CGDBR, - SYSZ_INS_CGEBR, - SYSZ_INS_CGF, - SYSZ_INS_CGFI, - SYSZ_INS_CGFR, - SYSZ_INS_CGFRL, - SYSZ_INS_CGH, - SYSZ_INS_CGHI, - SYSZ_INS_CGHRL, - SYSZ_INS_CGHSI, - SYSZ_INS_CGR, - SYSZ_INS_CGRL, - SYSZ_INS_CGXBR, - SYSZ_INS_CH, - SYSZ_INS_CHF, - SYSZ_INS_CHHSI, - SYSZ_INS_CHI, - SYSZ_INS_CHRL, - SYSZ_INS_CHSI, - SYSZ_INS_CHY, - SYSZ_INS_CIH, - SYSZ_INS_CL, - SYSZ_INS_CLC, - SYSZ_INS_CLFDBR, - SYSZ_INS_CLFEBR, - SYSZ_INS_CLFHSI, - SYSZ_INS_CLFI, - SYSZ_INS_CLFXBR, - SYSZ_INS_CLG, - SYSZ_INS_CLGDBR, - SYSZ_INS_CLGEBR, - SYSZ_INS_CLGF, - SYSZ_INS_CLGFI, - SYSZ_INS_CLGFR, - SYSZ_INS_CLGFRL, - SYSZ_INS_CLGHRL, - SYSZ_INS_CLGHSI, - SYSZ_INS_CLGR, - SYSZ_INS_CLGRL, - SYSZ_INS_CLGXBR, - SYSZ_INS_CLHF, - SYSZ_INS_CLHHSI, - SYSZ_INS_CLHRL, - SYSZ_INS_CLI, - SYSZ_INS_CLIH, - SYSZ_INS_CLIY, - SYSZ_INS_CLR, - SYSZ_INS_CLRL, - SYSZ_INS_CLST, - SYSZ_INS_CLY, - SYSZ_INS_CPSDR, - SYSZ_INS_CR, - SYSZ_INS_CRL, - SYSZ_INS_CS, - SYSZ_INS_CSG, - SYSZ_INS_CSY, - SYSZ_INS_CXBR, - SYSZ_INS_CXFBR, - SYSZ_INS_CXGBR, - SYSZ_INS_CXLFBR, - SYSZ_INS_CXLGBR, - SYSZ_INS_CY, - SYSZ_INS_DDB, - SYSZ_INS_DDBR, - SYSZ_INS_DEB, - SYSZ_INS_DEBR, - SYSZ_INS_DL, - SYSZ_INS_DLG, - SYSZ_INS_DLGR, - SYSZ_INS_DLR, - SYSZ_INS_DSG, - SYSZ_INS_DSGF, - SYSZ_INS_DSGFR, - SYSZ_INS_DSGR, - SYSZ_INS_DXBR, - SYSZ_INS_EAR, - SYSZ_INS_FIDBR, - SYSZ_INS_FIDBRA, - SYSZ_INS_FIEBR, - SYSZ_INS_FIEBRA, - SYSZ_INS_FIXBR, - SYSZ_INS_FIXBRA, - SYSZ_INS_FLOGR, - SYSZ_INS_IC, - SYSZ_INS_ICY, - SYSZ_INS_IIHF, - SYSZ_INS_IIHH, - SYSZ_INS_IIHL, - SYSZ_INS_IILF, - SYSZ_INS_IILH, - SYSZ_INS_IILL, - SYSZ_INS_IPM, - SYSZ_INS_L, - SYSZ_INS_LA, - SYSZ_INS_LAA, - SYSZ_INS_LAAG, - SYSZ_INS_LAAL, - SYSZ_INS_LAALG, - SYSZ_INS_LAN, - SYSZ_INS_LANG, - SYSZ_INS_LAO, - SYSZ_INS_LAOG, - SYSZ_INS_LARL, - SYSZ_INS_LAX, - SYSZ_INS_LAXG, - SYSZ_INS_LAY, - SYSZ_INS_LB, - SYSZ_INS_LBH, - SYSZ_INS_LBR, - SYSZ_INS_LCDBR, - SYSZ_INS_LCEBR, - SYSZ_INS_LCGFR, - SYSZ_INS_LCGR, - SYSZ_INS_LCR, - SYSZ_INS_LCXBR, - SYSZ_INS_LD, - SYSZ_INS_LDEB, - SYSZ_INS_LDEBR, - SYSZ_INS_LDGR, - SYSZ_INS_LDR, - SYSZ_INS_LDXBR, - SYSZ_INS_LDXBRA, - SYSZ_INS_LDY, - SYSZ_INS_LE, - SYSZ_INS_LEDBR, - SYSZ_INS_LEDBRA, - SYSZ_INS_LER, - SYSZ_INS_LEXBR, - SYSZ_INS_LEXBRA, - SYSZ_INS_LEY, - SYSZ_INS_LFH, - SYSZ_INS_LG, - SYSZ_INS_LGB, - SYSZ_INS_LGBR, - SYSZ_INS_LGDR, - SYSZ_INS_LGF, - SYSZ_INS_LGFI, - SYSZ_INS_LGFR, - SYSZ_INS_LGFRL, - SYSZ_INS_LGH, - SYSZ_INS_LGHI, - SYSZ_INS_LGHR, - SYSZ_INS_LGHRL, - SYSZ_INS_LGR, - SYSZ_INS_LGRL, - SYSZ_INS_LH, - SYSZ_INS_LHH, - SYSZ_INS_LHI, - SYSZ_INS_LHR, - SYSZ_INS_LHRL, - SYSZ_INS_LHY, - SYSZ_INS_LLC, - SYSZ_INS_LLCH, - SYSZ_INS_LLCR, - SYSZ_INS_LLGC, - SYSZ_INS_LLGCR, - SYSZ_INS_LLGF, - SYSZ_INS_LLGFR, - SYSZ_INS_LLGFRL, - SYSZ_INS_LLGH, - SYSZ_INS_LLGHR, - SYSZ_INS_LLGHRL, - SYSZ_INS_LLH, - SYSZ_INS_LLHH, - SYSZ_INS_LLHR, - SYSZ_INS_LLHRL, - SYSZ_INS_LLIHF, - SYSZ_INS_LLIHH, - SYSZ_INS_LLIHL, - SYSZ_INS_LLILF, - SYSZ_INS_LLILH, - SYSZ_INS_LLILL, - SYSZ_INS_LMG, - SYSZ_INS_LNDBR, - SYSZ_INS_LNEBR, - SYSZ_INS_LNGFR, - SYSZ_INS_LNGR, - SYSZ_INS_LNR, - SYSZ_INS_LNXBR, - SYSZ_INS_LPDBR, - SYSZ_INS_LPEBR, - SYSZ_INS_LPGFR, - SYSZ_INS_LPGR, - SYSZ_INS_LPR, - SYSZ_INS_LPXBR, - SYSZ_INS_LR, - SYSZ_INS_LRL, - SYSZ_INS_LRV, - SYSZ_INS_LRVG, - SYSZ_INS_LRVGR, - SYSZ_INS_LRVR, - SYSZ_INS_LT, - SYSZ_INS_LTDBR, - SYSZ_INS_LTEBR, - SYSZ_INS_LTG, - SYSZ_INS_LTGF, - SYSZ_INS_LTGFR, - SYSZ_INS_LTGR, - SYSZ_INS_LTR, - SYSZ_INS_LTXBR, - SYSZ_INS_LXDB, - SYSZ_INS_LXDBR, - SYSZ_INS_LXEB, - SYSZ_INS_LXEBR, - SYSZ_INS_LXR, - SYSZ_INS_LY, - SYSZ_INS_LZDR, - SYSZ_INS_LZER, - SYSZ_INS_LZXR, - SYSZ_INS_MADB, - SYSZ_INS_MADBR, - SYSZ_INS_MAEB, - SYSZ_INS_MAEBR, - SYSZ_INS_MDB, - SYSZ_INS_MDBR, - SYSZ_INS_MDEB, - SYSZ_INS_MDEBR, - SYSZ_INS_MEEB, - SYSZ_INS_MEEBR, - SYSZ_INS_MGHI, - SYSZ_INS_MH, - SYSZ_INS_MHI, - SYSZ_INS_MHY, - SYSZ_INS_MLG, - SYSZ_INS_MLGR, - SYSZ_INS_MS, - SYSZ_INS_MSDB, - SYSZ_INS_MSDBR, - SYSZ_INS_MSEB, - SYSZ_INS_MSEBR, - SYSZ_INS_MSFI, - SYSZ_INS_MSG, - SYSZ_INS_MSGF, - SYSZ_INS_MSGFI, - SYSZ_INS_MSGFR, - SYSZ_INS_MSGR, - SYSZ_INS_MSR, - SYSZ_INS_MSY, - SYSZ_INS_MVC, - SYSZ_INS_MVGHI, - SYSZ_INS_MVHHI, - SYSZ_INS_MVHI, - SYSZ_INS_MVI, - SYSZ_INS_MVIY, - SYSZ_INS_MVST, - SYSZ_INS_MXBR, - SYSZ_INS_MXDB, - SYSZ_INS_MXDBR, - SYSZ_INS_N, - SYSZ_INS_NC, - SYSZ_INS_NG, - SYSZ_INS_NGR, - SYSZ_INS_NGRK, - SYSZ_INS_NI, - SYSZ_INS_NIHF, - SYSZ_INS_NIHH, - SYSZ_INS_NIHL, - SYSZ_INS_NILF, - SYSZ_INS_NILH, - SYSZ_INS_NILL, - SYSZ_INS_NIY, - SYSZ_INS_NR, - SYSZ_INS_NRK, - SYSZ_INS_NY, - SYSZ_INS_O, - SYSZ_INS_OC, - SYSZ_INS_OG, - SYSZ_INS_OGR, - SYSZ_INS_OGRK, - SYSZ_INS_OI, - SYSZ_INS_OIHF, - SYSZ_INS_OIHH, - SYSZ_INS_OIHL, - SYSZ_INS_OILF, - SYSZ_INS_OILH, - SYSZ_INS_OILL, - SYSZ_INS_OIY, - SYSZ_INS_OR, - SYSZ_INS_ORK, - SYSZ_INS_OY, - SYSZ_INS_PFD, - SYSZ_INS_PFDRL, - SYSZ_INS_RISBG, - SYSZ_INS_RISBHG, - SYSZ_INS_RISBLG, - SYSZ_INS_RLL, - SYSZ_INS_RLLG, - SYSZ_INS_RNSBG, - SYSZ_INS_ROSBG, - SYSZ_INS_RXSBG, - SYSZ_INS_S, - SYSZ_INS_SDB, - SYSZ_INS_SDBR, - SYSZ_INS_SEB, - SYSZ_INS_SEBR, - SYSZ_INS_SG, - SYSZ_INS_SGF, - SYSZ_INS_SGFR, - SYSZ_INS_SGR, - SYSZ_INS_SGRK, - SYSZ_INS_SH, - SYSZ_INS_SHY, - SYSZ_INS_SL, - SYSZ_INS_SLB, - SYSZ_INS_SLBG, - SYSZ_INS_SLBR, - SYSZ_INS_SLFI, - SYSZ_INS_SLG, - SYSZ_INS_SLBGR, - SYSZ_INS_SLGF, - SYSZ_INS_SLGFI, - SYSZ_INS_SLGFR, - SYSZ_INS_SLGR, - SYSZ_INS_SLGRK, - SYSZ_INS_SLL, - SYSZ_INS_SLLG, - SYSZ_INS_SLLK, - SYSZ_INS_SLR, - SYSZ_INS_SLRK, - SYSZ_INS_SLY, - SYSZ_INS_SQDB, - SYSZ_INS_SQDBR, - SYSZ_INS_SQEB, - SYSZ_INS_SQEBR, - SYSZ_INS_SQXBR, - SYSZ_INS_SR, - SYSZ_INS_SRA, - SYSZ_INS_SRAG, - SYSZ_INS_SRAK, - SYSZ_INS_SRK, - SYSZ_INS_SRL, - SYSZ_INS_SRLG, - SYSZ_INS_SRLK, - SYSZ_INS_SRST, - SYSZ_INS_ST, - SYSZ_INS_STC, - SYSZ_INS_STCH, - SYSZ_INS_STCY, - SYSZ_INS_STD, - SYSZ_INS_STDY, - SYSZ_INS_STE, - SYSZ_INS_STEY, - SYSZ_INS_STFH, - SYSZ_INS_STG, - SYSZ_INS_STGRL, - SYSZ_INS_STH, - SYSZ_INS_STHH, - SYSZ_INS_STHRL, - SYSZ_INS_STHY, - SYSZ_INS_STMG, - SYSZ_INS_STRL, - SYSZ_INS_STRV, - SYSZ_INS_STRVG, - SYSZ_INS_STY, - SYSZ_INS_SXBR, - SYSZ_INS_SY, - SYSZ_INS_TM, - SYSZ_INS_TMHH, - SYSZ_INS_TMHL, - SYSZ_INS_TMLH, - SYSZ_INS_TMLL, - SYSZ_INS_TMY, - SYSZ_INS_X, - SYSZ_INS_XC, - SYSZ_INS_XG, - SYSZ_INS_XGR, - SYSZ_INS_XGRK, - SYSZ_INS_XI, - SYSZ_INS_XIHF, - SYSZ_INS_XILF, - SYSZ_INS_XIY, - SYSZ_INS_XR, - SYSZ_INS_XRK, - SYSZ_INS_XY, - SYSZ_INS_AD, - SYSZ_INS_ADR, - SYSZ_INS_ADTR, - SYSZ_INS_ADTRA, - SYSZ_INS_AE, - SYSZ_INS_AER, - SYSZ_INS_AGH, - SYSZ_INS_AHHHR, - SYSZ_INS_AHHLR, - SYSZ_INS_ALGSI, - SYSZ_INS_ALHHHR, - SYSZ_INS_ALHHLR, - SYSZ_INS_ALSI, - SYSZ_INS_ALSIH, - SYSZ_INS_ALSIHN, - SYSZ_INS_AP, - SYSZ_INS_AU, - SYSZ_INS_AUR, - SYSZ_INS_AW, - SYSZ_INS_AWR, - SYSZ_INS_AXR, - SYSZ_INS_AXTR, - SYSZ_INS_AXTRA, - SYSZ_INS_B, - SYSZ_INS_BAKR, - SYSZ_INS_BAL, - SYSZ_INS_BALR, - SYSZ_INS_BAS, - SYSZ_INS_BASSM, - SYSZ_INS_BC, - SYSZ_INS_BCT, - SYSZ_INS_BCTG, - SYSZ_INS_BCTGR, - SYSZ_INS_BCTR, - SYSZ_INS_BE, - SYSZ_INS_BH, - SYSZ_INS_BHE, - SYSZ_INS_BI, - SYSZ_INS_BIC, - SYSZ_INS_BIE, - SYSZ_INS_BIH, - SYSZ_INS_BIHE, - SYSZ_INS_BIL, - SYSZ_INS_BILE, - SYSZ_INS_BILH, - SYSZ_INS_BIM, - SYSZ_INS_BINE, - SYSZ_INS_BINH, - SYSZ_INS_BINHE, - SYSZ_INS_BINL, - SYSZ_INS_BINLE, - SYSZ_INS_BINLH, - SYSZ_INS_BINM, - SYSZ_INS_BINO, - SYSZ_INS_BINP, - SYSZ_INS_BINZ, - SYSZ_INS_BIO, - SYSZ_INS_BIP, - SYSZ_INS_BIZ, - SYSZ_INS_BL, - SYSZ_INS_BLE, - SYSZ_INS_BLH, - SYSZ_INS_BM, - SYSZ_INS_BMR, - SYSZ_INS_BNE, - SYSZ_INS_BNH, - SYSZ_INS_BNHE, - SYSZ_INS_BNL, - SYSZ_INS_BNLE, - SYSZ_INS_BNLH, - SYSZ_INS_BNM, - SYSZ_INS_BNMR, - SYSZ_INS_BNO, - SYSZ_INS_BNP, - SYSZ_INS_BNPR, - SYSZ_INS_BNZ, - SYSZ_INS_BNZR, - SYSZ_INS_BO, - SYSZ_INS_BP, - SYSZ_INS_BPP, - SYSZ_INS_BPR, - SYSZ_INS_BPRP, - SYSZ_INS_BRCTH, - SYSZ_INS_BRXH, - SYSZ_INS_BRXHG, - SYSZ_INS_BRXLE, - SYSZ_INS_BRXLG, - SYSZ_INS_BSA, - SYSZ_INS_BSG, - SYSZ_INS_BSM, - SYSZ_INS_BXH, - SYSZ_INS_BXHG, - SYSZ_INS_BXLE, - SYSZ_INS_BXLEG, - SYSZ_INS_BZ, - SYSZ_INS_BZR, - SYSZ_INS_CD, - SYSZ_INS_CDFBRA, - SYSZ_INS_CDFR, - SYSZ_INS_CDFTR, - SYSZ_INS_CDGBRA, - SYSZ_INS_CDGR, - SYSZ_INS_CDGTR, - SYSZ_INS_CDGTRA, - SYSZ_INS_CDLFTR, - SYSZ_INS_CDLGTR, - SYSZ_INS_CDPT, - SYSZ_INS_CDR, - SYSZ_INS_CDS, - SYSZ_INS_CDSG, - SYSZ_INS_CDSTR, - SYSZ_INS_CDSY, - SYSZ_INS_CDTR, - SYSZ_INS_CDUTR, - SYSZ_INS_CDZT, - SYSZ_INS_CE, - SYSZ_INS_CEDTR, - SYSZ_INS_CEFBRA, - SYSZ_INS_CEFR, - SYSZ_INS_CEGBRA, - SYSZ_INS_CEGR, - SYSZ_INS_CER, - SYSZ_INS_CEXTR, - SYSZ_INS_CFC, - SYSZ_INS_CFDBRA, - SYSZ_INS_CFDR, - SYSZ_INS_CFDTR, - SYSZ_INS_CFEBRA, - SYSZ_INS_CFER, - SYSZ_INS_CFXBRA, - SYSZ_INS_CFXR, - SYSZ_INS_CFXTR, - SYSZ_INS_CGDBRA, - SYSZ_INS_CGDR, - SYSZ_INS_CGDTR, - SYSZ_INS_CGDTRA, - SYSZ_INS_CGEBRA, - SYSZ_INS_CGER, - SYSZ_INS_CGIB, - SYSZ_INS_CGIBE, - SYSZ_INS_CGIBH, - SYSZ_INS_CGIBHE, - SYSZ_INS_CGIBL, - SYSZ_INS_CGIBLE, - SYSZ_INS_CGIBLH, - SYSZ_INS_CGIBNE, - SYSZ_INS_CGIBNH, - SYSZ_INS_CGIBNHE, - SYSZ_INS_CGIBNL, - SYSZ_INS_CGIBNLE, - SYSZ_INS_CGIBNLH, - SYSZ_INS_CGIT, - SYSZ_INS_CGITE, - SYSZ_INS_CGITH, - SYSZ_INS_CGITHE, - SYSZ_INS_CGITL, - SYSZ_INS_CGITLE, - SYSZ_INS_CGITLH, - SYSZ_INS_CGITNE, - SYSZ_INS_CGITNH, - SYSZ_INS_CGITNHE, - SYSZ_INS_CGITNL, - SYSZ_INS_CGITNLE, - SYSZ_INS_CGITNLH, - SYSZ_INS_CGRB, - SYSZ_INS_CGRBE, - SYSZ_INS_CGRBH, - SYSZ_INS_CGRBHE, - SYSZ_INS_CGRBL, - SYSZ_INS_CGRBLE, - SYSZ_INS_CGRBLH, - SYSZ_INS_CGRBNE, - SYSZ_INS_CGRBNH, - SYSZ_INS_CGRBNHE, - SYSZ_INS_CGRBNL, - SYSZ_INS_CGRBNLE, - SYSZ_INS_CGRBNLH, - SYSZ_INS_CGRT, - SYSZ_INS_CGRTE, - SYSZ_INS_CGRTH, - SYSZ_INS_CGRTHE, - SYSZ_INS_CGRTL, - SYSZ_INS_CGRTLE, - SYSZ_INS_CGRTLH, - SYSZ_INS_CGRTNE, - SYSZ_INS_CGRTNH, - SYSZ_INS_CGRTNHE, - SYSZ_INS_CGRTNL, - SYSZ_INS_CGRTNLE, - SYSZ_INS_CGRTNLH, - SYSZ_INS_CGXBRA, - SYSZ_INS_CGXR, - SYSZ_INS_CGXTR, - SYSZ_INS_CGXTRA, - SYSZ_INS_CHHR, - SYSZ_INS_CHLR, - SYSZ_INS_CIB, - SYSZ_INS_CIBE, - SYSZ_INS_CIBH, - SYSZ_INS_CIBHE, - SYSZ_INS_CIBL, - SYSZ_INS_CIBLE, - SYSZ_INS_CIBLH, - SYSZ_INS_CIBNE, - SYSZ_INS_CIBNH, - SYSZ_INS_CIBNHE, - SYSZ_INS_CIBNL, - SYSZ_INS_CIBNLE, - SYSZ_INS_CIBNLH, - SYSZ_INS_CIT, - SYSZ_INS_CITE, - SYSZ_INS_CITH, - SYSZ_INS_CITHE, - SYSZ_INS_CITL, - SYSZ_INS_CITLE, - SYSZ_INS_CITLH, - SYSZ_INS_CITNE, - SYSZ_INS_CITNH, - SYSZ_INS_CITNHE, - SYSZ_INS_CITNL, - SYSZ_INS_CITNLE, - SYSZ_INS_CITNLH, - SYSZ_INS_CKSM, - SYSZ_INS_CLCL, - SYSZ_INS_CLCLE, - SYSZ_INS_CLCLU, - SYSZ_INS_CLFDTR, - SYSZ_INS_CLFIT, - SYSZ_INS_CLFITE, - SYSZ_INS_CLFITH, - SYSZ_INS_CLFITHE, - SYSZ_INS_CLFITL, - SYSZ_INS_CLFITLE, - SYSZ_INS_CLFITLH, - SYSZ_INS_CLFITNE, - SYSZ_INS_CLFITNH, - SYSZ_INS_CLFITNHE, - SYSZ_INS_CLFITNL, - SYSZ_INS_CLFITNLE, - SYSZ_INS_CLFITNLH, - SYSZ_INS_CLFXTR, - SYSZ_INS_CLGDTR, - SYSZ_INS_CLGIB, - SYSZ_INS_CLGIBE, - SYSZ_INS_CLGIBH, - SYSZ_INS_CLGIBHE, - SYSZ_INS_CLGIBL, - SYSZ_INS_CLGIBLE, - SYSZ_INS_CLGIBLH, - SYSZ_INS_CLGIBNE, - SYSZ_INS_CLGIBNH, - SYSZ_INS_CLGIBNHE, - SYSZ_INS_CLGIBNL, - SYSZ_INS_CLGIBNLE, - SYSZ_INS_CLGIBNLH, - SYSZ_INS_CLGIT, - SYSZ_INS_CLGITE, - SYSZ_INS_CLGITH, - SYSZ_INS_CLGITHE, - SYSZ_INS_CLGITL, - SYSZ_INS_CLGITLE, - SYSZ_INS_CLGITLH, - SYSZ_INS_CLGITNE, - SYSZ_INS_CLGITNH, - SYSZ_INS_CLGITNHE, - SYSZ_INS_CLGITNL, - SYSZ_INS_CLGITNLE, - SYSZ_INS_CLGITNLH, - SYSZ_INS_CLGRB, - SYSZ_INS_CLGRBE, - SYSZ_INS_CLGRBH, - SYSZ_INS_CLGRBHE, - SYSZ_INS_CLGRBL, - SYSZ_INS_CLGRBLE, - SYSZ_INS_CLGRBLH, - SYSZ_INS_CLGRBNE, - SYSZ_INS_CLGRBNH, - SYSZ_INS_CLGRBNHE, - SYSZ_INS_CLGRBNL, - SYSZ_INS_CLGRBNLE, - SYSZ_INS_CLGRBNLH, - SYSZ_INS_CLGRT, - SYSZ_INS_CLGRTE, - SYSZ_INS_CLGRTH, - SYSZ_INS_CLGRTHE, - SYSZ_INS_CLGRTL, - SYSZ_INS_CLGRTLE, - SYSZ_INS_CLGRTLH, - SYSZ_INS_CLGRTNE, - SYSZ_INS_CLGRTNH, - SYSZ_INS_CLGRTNHE, - SYSZ_INS_CLGRTNL, - SYSZ_INS_CLGRTNLE, - SYSZ_INS_CLGRTNLH, - SYSZ_INS_CLGT, - SYSZ_INS_CLGTE, - SYSZ_INS_CLGTH, - SYSZ_INS_CLGTHE, - SYSZ_INS_CLGTL, - SYSZ_INS_CLGTLE, - SYSZ_INS_CLGTLH, - SYSZ_INS_CLGTNE, - SYSZ_INS_CLGTNH, - SYSZ_INS_CLGTNHE, - SYSZ_INS_CLGTNL, - SYSZ_INS_CLGTNLE, - SYSZ_INS_CLGTNLH, - SYSZ_INS_CLGXTR, - SYSZ_INS_CLHHR, - SYSZ_INS_CLHLR, - SYSZ_INS_CLIB, - SYSZ_INS_CLIBE, - SYSZ_INS_CLIBH, - SYSZ_INS_CLIBHE, - SYSZ_INS_CLIBL, - SYSZ_INS_CLIBLE, - SYSZ_INS_CLIBLH, - SYSZ_INS_CLIBNE, - SYSZ_INS_CLIBNH, - SYSZ_INS_CLIBNHE, - SYSZ_INS_CLIBNL, - SYSZ_INS_CLIBNLE, - SYSZ_INS_CLIBNLH, - SYSZ_INS_CLM, - SYSZ_INS_CLMH, - SYSZ_INS_CLMY, - SYSZ_INS_CLRB, - SYSZ_INS_CLRBE, - SYSZ_INS_CLRBH, - SYSZ_INS_CLRBHE, - SYSZ_INS_CLRBL, - SYSZ_INS_CLRBLE, - SYSZ_INS_CLRBLH, - SYSZ_INS_CLRBNE, - SYSZ_INS_CLRBNH, - SYSZ_INS_CLRBNHE, - SYSZ_INS_CLRBNL, - SYSZ_INS_CLRBNLE, - SYSZ_INS_CLRBNLH, - SYSZ_INS_CLRT, - SYSZ_INS_CLRTE, - SYSZ_INS_CLRTH, - SYSZ_INS_CLRTHE, - SYSZ_INS_CLRTL, - SYSZ_INS_CLRTLE, - SYSZ_INS_CLRTLH, - SYSZ_INS_CLRTNE, - SYSZ_INS_CLRTNH, - SYSZ_INS_CLRTNHE, - SYSZ_INS_CLRTNL, - SYSZ_INS_CLRTNLE, - SYSZ_INS_CLRTNLH, - SYSZ_INS_CLT, - SYSZ_INS_CLTE, - SYSZ_INS_CLTH, - SYSZ_INS_CLTHE, - SYSZ_INS_CLTL, - SYSZ_INS_CLTLE, - SYSZ_INS_CLTLH, - SYSZ_INS_CLTNE, - SYSZ_INS_CLTNH, - SYSZ_INS_CLTNHE, - SYSZ_INS_CLTNL, - SYSZ_INS_CLTNLE, - SYSZ_INS_CLTNLH, - SYSZ_INS_CMPSC, - SYSZ_INS_CP, - SYSZ_INS_CPDT, - SYSZ_INS_CPXT, - SYSZ_INS_CPYA, - SYSZ_INS_CRB, - SYSZ_INS_CRBE, - SYSZ_INS_CRBH, - SYSZ_INS_CRBHE, - SYSZ_INS_CRBL, - SYSZ_INS_CRBLE, - SYSZ_INS_CRBLH, - SYSZ_INS_CRBNE, - SYSZ_INS_CRBNH, - SYSZ_INS_CRBNHE, - SYSZ_INS_CRBNL, - SYSZ_INS_CRBNLE, - SYSZ_INS_CRBNLH, - SYSZ_INS_CRDTE, - SYSZ_INS_CRT, - SYSZ_INS_CRTE, - SYSZ_INS_CRTH, - SYSZ_INS_CRTHE, - SYSZ_INS_CRTL, - SYSZ_INS_CRTLE, - SYSZ_INS_CRTLH, - SYSZ_INS_CRTNE, - SYSZ_INS_CRTNH, - SYSZ_INS_CRTNHE, - SYSZ_INS_CRTNL, - SYSZ_INS_CRTNLE, - SYSZ_INS_CRTNLH, - SYSZ_INS_CSCH, - SYSZ_INS_CSDTR, - SYSZ_INS_CSP, - SYSZ_INS_CSPG, - SYSZ_INS_CSST, - SYSZ_INS_CSXTR, - SYSZ_INS_CU12, - SYSZ_INS_CU14, - SYSZ_INS_CU21, - SYSZ_INS_CU24, - SYSZ_INS_CU41, - SYSZ_INS_CU42, - SYSZ_INS_CUDTR, - SYSZ_INS_CUSE, - SYSZ_INS_CUTFU, - SYSZ_INS_CUUTF, - SYSZ_INS_CUXTR, - SYSZ_INS_CVB, - SYSZ_INS_CVBG, - SYSZ_INS_CVBY, - SYSZ_INS_CVD, - SYSZ_INS_CVDG, - SYSZ_INS_CVDY, - SYSZ_INS_CXFBRA, - SYSZ_INS_CXFR, - SYSZ_INS_CXFTR, - SYSZ_INS_CXGBRA, - SYSZ_INS_CXGR, - SYSZ_INS_CXGTR, - SYSZ_INS_CXGTRA, - SYSZ_INS_CXLFTR, - SYSZ_INS_CXLGTR, - SYSZ_INS_CXPT, - SYSZ_INS_CXR, - SYSZ_INS_CXSTR, - SYSZ_INS_CXTR, - SYSZ_INS_CXUTR, - SYSZ_INS_CXZT, - SYSZ_INS_CZDT, - SYSZ_INS_CZXT, - SYSZ_INS_D, - SYSZ_INS_DD, - SYSZ_INS_DDR, - SYSZ_INS_DDTR, - SYSZ_INS_DDTRA, - SYSZ_INS_DE, - SYSZ_INS_DER, - SYSZ_INS_DIAG, - SYSZ_INS_DIDBR, - SYSZ_INS_DIEBR, - SYSZ_INS_DP, - SYSZ_INS_DR, - SYSZ_INS_DXR, - SYSZ_INS_DXTR, - SYSZ_INS_DXTRA, - SYSZ_INS_ECAG, - SYSZ_INS_ECCTR, - SYSZ_INS_ECPGA, - SYSZ_INS_ECTG, - SYSZ_INS_ED, - SYSZ_INS_EDMK, - SYSZ_INS_EEDTR, - SYSZ_INS_EEXTR, - SYSZ_INS_EFPC, - SYSZ_INS_EPAIR, - SYSZ_INS_EPAR, - SYSZ_INS_EPCTR, - SYSZ_INS_EPSW, - SYSZ_INS_EREG, - SYSZ_INS_EREGG, - SYSZ_INS_ESAIR, - SYSZ_INS_ESAR, - SYSZ_INS_ESDTR, - SYSZ_INS_ESEA, - SYSZ_INS_ESTA, - SYSZ_INS_ESXTR, - SYSZ_INS_ETND, - SYSZ_INS_EX, - SYSZ_INS_EXRL, - SYSZ_INS_FIDR, - SYSZ_INS_FIDTR, - SYSZ_INS_FIER, - SYSZ_INS_FIXR, - SYSZ_INS_FIXTR, - SYSZ_INS_HDR, - SYSZ_INS_HER, - SYSZ_INS_HSCH, - SYSZ_INS_IAC, - SYSZ_INS_ICM, - SYSZ_INS_ICMH, - SYSZ_INS_ICMY, - SYSZ_INS_IDTE, - SYSZ_INS_IEDTR, - SYSZ_INS_IEXTR, - SYSZ_INS_IPK, - SYSZ_INS_IPTE, - SYSZ_INS_IRBM, - SYSZ_INS_ISKE, - SYSZ_INS_IVSK, - SYSZ_INS_JGM, - SYSZ_INS_JGNM, - SYSZ_INS_JGNP, - SYSZ_INS_JGNZ, - SYSZ_INS_JGP, - SYSZ_INS_JGZ, - SYSZ_INS_JM, - SYSZ_INS_JNM, - SYSZ_INS_JNP, - SYSZ_INS_JNZ, - SYSZ_INS_JP, - SYSZ_INS_JZ, - SYSZ_INS_KDB, - SYSZ_INS_KDBR, - SYSZ_INS_KDTR, - SYSZ_INS_KEB, - SYSZ_INS_KEBR, - SYSZ_INS_KIMD, - SYSZ_INS_KLMD, - SYSZ_INS_KM, - SYSZ_INS_KMA, - SYSZ_INS_KMAC, - SYSZ_INS_KMC, - SYSZ_INS_KMCTR, - SYSZ_INS_KMF, - SYSZ_INS_KMO, - SYSZ_INS_KXBR, - SYSZ_INS_KXTR, - SYSZ_INS_LAE, - SYSZ_INS_LAEY, - SYSZ_INS_LAM, - SYSZ_INS_LAMY, - SYSZ_INS_LASP, - SYSZ_INS_LAT, - SYSZ_INS_LCBB, - SYSZ_INS_LCCTL, - SYSZ_INS_LCDFR, - SYSZ_INS_LCDR, - SYSZ_INS_LCER, - SYSZ_INS_LCTL, - SYSZ_INS_LCTLG, - SYSZ_INS_LCXR, - SYSZ_INS_LDE, - SYSZ_INS_LDER, - SYSZ_INS_LDETR, - SYSZ_INS_LDXR, - SYSZ_INS_LDXTR, - SYSZ_INS_LEDR, - SYSZ_INS_LEDTR, - SYSZ_INS_LEXR, - SYSZ_INS_LFAS, - SYSZ_INS_LFHAT, - SYSZ_INS_LFPC, - SYSZ_INS_LGAT, - SYSZ_INS_LGG, - SYSZ_INS_LGSC, - SYSZ_INS_LLGFAT, - SYSZ_INS_LLGFSG, - SYSZ_INS_LLGT, - SYSZ_INS_LLGTAT, - SYSZ_INS_LLGTR, - SYSZ_INS_LLZRGF, - SYSZ_INS_LM, - SYSZ_INS_LMD, - SYSZ_INS_LMH, - SYSZ_INS_LMY, - SYSZ_INS_LNDFR, - SYSZ_INS_LNDR, - SYSZ_INS_LNER, - SYSZ_INS_LNXR, - SYSZ_INS_LOCFH, - SYSZ_INS_LOCFHE, - SYSZ_INS_LOCFHH, - SYSZ_INS_LOCFHHE, - SYSZ_INS_LOCFHL, - SYSZ_INS_LOCFHLE, - SYSZ_INS_LOCFHLH, - SYSZ_INS_LOCFHM, - SYSZ_INS_LOCFHNE, - SYSZ_INS_LOCFHNH, - SYSZ_INS_LOCFHNHE, - SYSZ_INS_LOCFHNL, - SYSZ_INS_LOCFHNLE, - SYSZ_INS_LOCFHNLH, - SYSZ_INS_LOCFHNM, - SYSZ_INS_LOCFHNO, - SYSZ_INS_LOCFHNP, - SYSZ_INS_LOCFHNZ, - SYSZ_INS_LOCFHO, - SYSZ_INS_LOCFHP, - SYSZ_INS_LOCFHR, - SYSZ_INS_LOCFHRE, - SYSZ_INS_LOCFHRH, - SYSZ_INS_LOCFHRHE, - SYSZ_INS_LOCFHRL, - SYSZ_INS_LOCFHRLE, - SYSZ_INS_LOCFHRLH, - SYSZ_INS_LOCFHRM, - SYSZ_INS_LOCFHRNE, - SYSZ_INS_LOCFHRNH, - SYSZ_INS_LOCFHRNHE, - SYSZ_INS_LOCFHRNL, - SYSZ_INS_LOCFHRNLE, - SYSZ_INS_LOCFHRNLH, - SYSZ_INS_LOCFHRNM, - SYSZ_INS_LOCFHRNO, - SYSZ_INS_LOCFHRNP, - SYSZ_INS_LOCFHRNZ, - SYSZ_INS_LOCFHRO, - SYSZ_INS_LOCFHRP, - SYSZ_INS_LOCFHRZ, - SYSZ_INS_LOCFHZ, - SYSZ_INS_LOCGHI, - SYSZ_INS_LOCGHIE, - SYSZ_INS_LOCGHIH, - SYSZ_INS_LOCGHIHE, - SYSZ_INS_LOCGHIL, - SYSZ_INS_LOCGHILE, - SYSZ_INS_LOCGHILH, - SYSZ_INS_LOCGHIM, - SYSZ_INS_LOCGHINE, - SYSZ_INS_LOCGHINH, - SYSZ_INS_LOCGHINHE, - SYSZ_INS_LOCGHINL, - SYSZ_INS_LOCGHINLE, - SYSZ_INS_LOCGHINLH, - SYSZ_INS_LOCGHINM, - SYSZ_INS_LOCGHINO, - SYSZ_INS_LOCGHINP, - SYSZ_INS_LOCGHINZ, - SYSZ_INS_LOCGHIO, - SYSZ_INS_LOCGHIP, - SYSZ_INS_LOCGHIZ, - SYSZ_INS_LOCGM, - SYSZ_INS_LOCGNM, - SYSZ_INS_LOCGNP, - SYSZ_INS_LOCGNZ, - SYSZ_INS_LOCGP, - SYSZ_INS_LOCGRM, - SYSZ_INS_LOCGRNM, - SYSZ_INS_LOCGRNP, - SYSZ_INS_LOCGRNZ, - SYSZ_INS_LOCGRP, - SYSZ_INS_LOCGRZ, - SYSZ_INS_LOCGZ, - SYSZ_INS_LOCHHI, - SYSZ_INS_LOCHHIE, - SYSZ_INS_LOCHHIH, - SYSZ_INS_LOCHHIHE, - SYSZ_INS_LOCHHIL, - SYSZ_INS_LOCHHILE, - SYSZ_INS_LOCHHILH, - SYSZ_INS_LOCHHIM, - SYSZ_INS_LOCHHINE, - SYSZ_INS_LOCHHINH, - SYSZ_INS_LOCHHINHE, - SYSZ_INS_LOCHHINL, - SYSZ_INS_LOCHHINLE, - SYSZ_INS_LOCHHINLH, - SYSZ_INS_LOCHHINM, - SYSZ_INS_LOCHHINO, - SYSZ_INS_LOCHHINP, - SYSZ_INS_LOCHHINZ, - SYSZ_INS_LOCHHIO, - SYSZ_INS_LOCHHIP, - SYSZ_INS_LOCHHIZ, - SYSZ_INS_LOCHI, - SYSZ_INS_LOCHIE, - SYSZ_INS_LOCHIH, - SYSZ_INS_LOCHIHE, - SYSZ_INS_LOCHIL, - SYSZ_INS_LOCHILE, - SYSZ_INS_LOCHILH, - SYSZ_INS_LOCHIM, - SYSZ_INS_LOCHINE, - SYSZ_INS_LOCHINH, - SYSZ_INS_LOCHINHE, - SYSZ_INS_LOCHINL, - SYSZ_INS_LOCHINLE, - SYSZ_INS_LOCHINLH, - SYSZ_INS_LOCHINM, - SYSZ_INS_LOCHINO, - SYSZ_INS_LOCHINP, - SYSZ_INS_LOCHINZ, - SYSZ_INS_LOCHIO, - SYSZ_INS_LOCHIP, - SYSZ_INS_LOCHIZ, - SYSZ_INS_LOCM, - SYSZ_INS_LOCNM, - SYSZ_INS_LOCNP, - SYSZ_INS_LOCNZ, - SYSZ_INS_LOCP, - SYSZ_INS_LOCRM, - SYSZ_INS_LOCRNM, - SYSZ_INS_LOCRNP, - SYSZ_INS_LOCRNZ, - SYSZ_INS_LOCRP, - SYSZ_INS_LOCRZ, - SYSZ_INS_LOCZ, - SYSZ_INS_LPCTL, - SYSZ_INS_LPD, - SYSZ_INS_LPDFR, - SYSZ_INS_LPDG, - SYSZ_INS_LPDR, - SYSZ_INS_LPER, - SYSZ_INS_LPP, - SYSZ_INS_LPQ, - SYSZ_INS_LPSW, - SYSZ_INS_LPSWE, - SYSZ_INS_LPTEA, - SYSZ_INS_LPXR, - SYSZ_INS_LRA, - SYSZ_INS_LRAG, - SYSZ_INS_LRAY, - SYSZ_INS_LRDR, - SYSZ_INS_LRER, - SYSZ_INS_LRVH, - SYSZ_INS_LSCTL, - SYSZ_INS_LTDR, - SYSZ_INS_LTDTR, - SYSZ_INS_LTER, - SYSZ_INS_LTXR, - SYSZ_INS_LTXTR, - SYSZ_INS_LURA, - SYSZ_INS_LURAG, - SYSZ_INS_LXD, - SYSZ_INS_LXDR, - SYSZ_INS_LXDTR, - SYSZ_INS_LXE, - SYSZ_INS_LXER, - SYSZ_INS_LZRF, - SYSZ_INS_LZRG, - SYSZ_INS_M, - SYSZ_INS_MAD, - SYSZ_INS_MADR, - SYSZ_INS_MAE, - SYSZ_INS_MAER, - SYSZ_INS_MAY, - SYSZ_INS_MAYH, - SYSZ_INS_MAYHR, - SYSZ_INS_MAYL, - SYSZ_INS_MAYLR, - SYSZ_INS_MAYR, - SYSZ_INS_MC, - SYSZ_INS_MD, - SYSZ_INS_MDE, - SYSZ_INS_MDER, - SYSZ_INS_MDR, - SYSZ_INS_MDTR, - SYSZ_INS_MDTRA, - SYSZ_INS_ME, - SYSZ_INS_MEE, - SYSZ_INS_MEER, - SYSZ_INS_MER, - SYSZ_INS_MFY, - SYSZ_INS_MG, - SYSZ_INS_MGH, - SYSZ_INS_MGRK, - SYSZ_INS_ML, - SYSZ_INS_MLR, - SYSZ_INS_MP, - SYSZ_INS_MR, - SYSZ_INS_MSC, - SYSZ_INS_MSCH, - SYSZ_INS_MSD, - SYSZ_INS_MSDR, - SYSZ_INS_MSE, - SYSZ_INS_MSER, - SYSZ_INS_MSGC, - SYSZ_INS_MSGRKC, - SYSZ_INS_MSRKC, - SYSZ_INS_MSTA, - SYSZ_INS_MVCDK, - SYSZ_INS_MVCIN, - SYSZ_INS_MVCK, - SYSZ_INS_MVCL, - SYSZ_INS_MVCLE, - SYSZ_INS_MVCLU, - SYSZ_INS_MVCOS, - SYSZ_INS_MVCP, - SYSZ_INS_MVCS, - SYSZ_INS_MVCSK, - SYSZ_INS_MVN, - SYSZ_INS_MVO, - SYSZ_INS_MVPG, - SYSZ_INS_MVZ, - SYSZ_INS_MXD, - SYSZ_INS_MXDR, - SYSZ_INS_MXR, - SYSZ_INS_MXTR, - SYSZ_INS_MXTRA, - SYSZ_INS_MY, - SYSZ_INS_MYH, - SYSZ_INS_MYHR, - SYSZ_INS_MYL, - SYSZ_INS_MYLR, - SYSZ_INS_MYR, - SYSZ_INS_NIAI, - SYSZ_INS_NTSTG, - SYSZ_INS_PACK, - SYSZ_INS_PALB, - SYSZ_INS_PC, - SYSZ_INS_PCC, - SYSZ_INS_PCKMO, - SYSZ_INS_PFMF, - SYSZ_INS_PFPO, - SYSZ_INS_PGIN, - SYSZ_INS_PGOUT, - SYSZ_INS_PKA, - SYSZ_INS_PKU, - SYSZ_INS_PLO, - SYSZ_INS_POPCNT, - SYSZ_INS_PPA, - SYSZ_INS_PPNO, - SYSZ_INS_PR, - SYSZ_INS_PRNO, - SYSZ_INS_PT, - SYSZ_INS_PTF, - SYSZ_INS_PTFF, - SYSZ_INS_PTI, - SYSZ_INS_PTLB, - SYSZ_INS_QADTR, - SYSZ_INS_QAXTR, - SYSZ_INS_QCTRI, - SYSZ_INS_QSI, - SYSZ_INS_RCHP, - SYSZ_INS_RISBGN, - SYSZ_INS_RP, - SYSZ_INS_RRBE, - SYSZ_INS_RRBM, - SYSZ_INS_RRDTR, - SYSZ_INS_RRXTR, - SYSZ_INS_RSCH, - SYSZ_INS_SAC, - SYSZ_INS_SACF, - SYSZ_INS_SAL, - SYSZ_INS_SAM24, - SYSZ_INS_SAM31, - SYSZ_INS_SAM64, - SYSZ_INS_SAR, - SYSZ_INS_SCCTR, - SYSZ_INS_SCHM, - SYSZ_INS_SCK, - SYSZ_INS_SCKC, - SYSZ_INS_SCKPF, - SYSZ_INS_SD, - SYSZ_INS_SDR, - SYSZ_INS_SDTR, - SYSZ_INS_SDTRA, - SYSZ_INS_SE, - SYSZ_INS_SER, - SYSZ_INS_SFASR, - SYSZ_INS_SFPC, - SYSZ_INS_SGH, - SYSZ_INS_SHHHR, - SYSZ_INS_SHHLR, - SYSZ_INS_SIE, - SYSZ_INS_SIGA, - SYSZ_INS_SIGP, - SYSZ_INS_SLA, - SYSZ_INS_SLAG, - SYSZ_INS_SLAK, - SYSZ_INS_SLDA, - SYSZ_INS_SLDL, - SYSZ_INS_SLDT, - SYSZ_INS_SLHHHR, - SYSZ_INS_SLHHLR, - SYSZ_INS_SLXT, - SYSZ_INS_SP, - SYSZ_INS_SPCTR, - SYSZ_INS_SPKA, - SYSZ_INS_SPM, - SYSZ_INS_SPT, - SYSZ_INS_SPX, - SYSZ_INS_SQD, - SYSZ_INS_SQDR, - SYSZ_INS_SQE, - SYSZ_INS_SQER, - SYSZ_INS_SQXR, - SYSZ_INS_SRDA, - SYSZ_INS_SRDL, - SYSZ_INS_SRDT, - SYSZ_INS_SRNM, - SYSZ_INS_SRNMB, - SYSZ_INS_SRNMT, - SYSZ_INS_SRP, - SYSZ_INS_SRSTU, - SYSZ_INS_SRXT, - SYSZ_INS_SSAIR, - SYSZ_INS_SSAR, - SYSZ_INS_SSCH, - SYSZ_INS_SSKE, - SYSZ_INS_SSM, - SYSZ_INS_STAM, - SYSZ_INS_STAMY, - SYSZ_INS_STAP, - SYSZ_INS_STCK, - SYSZ_INS_STCKC, - SYSZ_INS_STCKE, - SYSZ_INS_STCKF, - SYSZ_INS_STCM, - SYSZ_INS_STCMH, - SYSZ_INS_STCMY, - SYSZ_INS_STCPS, - SYSZ_INS_STCRW, - SYSZ_INS_STCTG, - SYSZ_INS_STCTL, - SYSZ_INS_STFL, - SYSZ_INS_STFLE, - SYSZ_INS_STFPC, - SYSZ_INS_STGSC, - SYSZ_INS_STIDP, - SYSZ_INS_STM, - SYSZ_INS_STMH, - SYSZ_INS_STMY, - SYSZ_INS_STNSM, - SYSZ_INS_STOCFH, - SYSZ_INS_STOCFHE, - SYSZ_INS_STOCFHH, - SYSZ_INS_STOCFHHE, - SYSZ_INS_STOCFHL, - SYSZ_INS_STOCFHLE, - SYSZ_INS_STOCFHLH, - SYSZ_INS_STOCFHM, - SYSZ_INS_STOCFHNE, - SYSZ_INS_STOCFHNH, - SYSZ_INS_STOCFHNHE, - SYSZ_INS_STOCFHNL, - SYSZ_INS_STOCFHNLE, - SYSZ_INS_STOCFHNLH, - SYSZ_INS_STOCFHNM, - SYSZ_INS_STOCFHNO, - SYSZ_INS_STOCFHNP, - SYSZ_INS_STOCFHNZ, - SYSZ_INS_STOCFHO, - SYSZ_INS_STOCFHP, - SYSZ_INS_STOCFHZ, - SYSZ_INS_STOCGM, - SYSZ_INS_STOCGNM, - SYSZ_INS_STOCGNP, - SYSZ_INS_STOCGNZ, - SYSZ_INS_STOCGP, - SYSZ_INS_STOCGZ, - SYSZ_INS_STOCM, - SYSZ_INS_STOCNM, - SYSZ_INS_STOCNP, - SYSZ_INS_STOCNZ, - SYSZ_INS_STOCP, - SYSZ_INS_STOCZ, - SYSZ_INS_STOSM, - SYSZ_INS_STPQ, - SYSZ_INS_STPT, - SYSZ_INS_STPX, - SYSZ_INS_STRAG, - SYSZ_INS_STRVH, - SYSZ_INS_STSCH, - SYSZ_INS_STSI, - SYSZ_INS_STURA, - SYSZ_INS_STURG, - SYSZ_INS_SU, - SYSZ_INS_SUR, - SYSZ_INS_SVC, - SYSZ_INS_SW, - SYSZ_INS_SWR, - SYSZ_INS_SXR, - SYSZ_INS_SXTR, - SYSZ_INS_SXTRA, - SYSZ_INS_TABORT, - SYSZ_INS_TAM, - SYSZ_INS_TAR, - SYSZ_INS_TB, - SYSZ_INS_TBDR, - SYSZ_INS_TBEDR, - SYSZ_INS_TBEGIN, - SYSZ_INS_TBEGINC, - SYSZ_INS_TCDB, - SYSZ_INS_TCEB, - SYSZ_INS_TCXB, - SYSZ_INS_TDCDT, - SYSZ_INS_TDCET, - SYSZ_INS_TDCXT, - SYSZ_INS_TDGDT, - SYSZ_INS_TDGET, - SYSZ_INS_TDGXT, - SYSZ_INS_TEND, - SYSZ_INS_THDER, - SYSZ_INS_THDR, - SYSZ_INS_TP, - SYSZ_INS_TPI, - SYSZ_INS_TPROT, - SYSZ_INS_TR, - SYSZ_INS_TRACE, - SYSZ_INS_TRACG, - SYSZ_INS_TRAP2, - SYSZ_INS_TRAP4, - SYSZ_INS_TRE, - SYSZ_INS_TROO, - SYSZ_INS_TROT, - SYSZ_INS_TRT, - SYSZ_INS_TRTE, - SYSZ_INS_TRTO, - SYSZ_INS_TRTR, - SYSZ_INS_TRTRE, - SYSZ_INS_TRTT, - SYSZ_INS_TS, - SYSZ_INS_TSCH, - SYSZ_INS_UNPK, - SYSZ_INS_UNPKA, - SYSZ_INS_UNPKU, - SYSZ_INS_UPT, - SYSZ_INS_VA, - SYSZ_INS_VAB, - SYSZ_INS_VAC, - SYSZ_INS_VACC, - SYSZ_INS_VACCB, - SYSZ_INS_VACCC, - SYSZ_INS_VACCCQ, - SYSZ_INS_VACCF, - SYSZ_INS_VACCG, - SYSZ_INS_VACCH, - SYSZ_INS_VACCQ, - SYSZ_INS_VACQ, - SYSZ_INS_VAF, - SYSZ_INS_VAG, - SYSZ_INS_VAH, - SYSZ_INS_VAP, - SYSZ_INS_VAQ, - SYSZ_INS_VAVG, - SYSZ_INS_VAVGB, - SYSZ_INS_VAVGF, - SYSZ_INS_VAVGG, - SYSZ_INS_VAVGH, - SYSZ_INS_VAVGL, - SYSZ_INS_VAVGLB, - SYSZ_INS_VAVGLF, - SYSZ_INS_VAVGLG, - SYSZ_INS_VAVGLH, - SYSZ_INS_VBPERM, - SYSZ_INS_VCDG, - SYSZ_INS_VCDGB, - SYSZ_INS_VCDLG, - SYSZ_INS_VCDLGB, - SYSZ_INS_VCEQ, - SYSZ_INS_VCEQB, - SYSZ_INS_VCEQBS, - SYSZ_INS_VCEQF, - SYSZ_INS_VCEQFS, - SYSZ_INS_VCEQG, - SYSZ_INS_VCEQGS, - SYSZ_INS_VCEQH, - SYSZ_INS_VCEQHS, - SYSZ_INS_VCGD, - SYSZ_INS_VCGDB, - SYSZ_INS_VCH, - SYSZ_INS_VCHB, - SYSZ_INS_VCHBS, - SYSZ_INS_VCHF, - SYSZ_INS_VCHFS, - SYSZ_INS_VCHG, - SYSZ_INS_VCHGS, - SYSZ_INS_VCHH, - SYSZ_INS_VCHHS, - SYSZ_INS_VCHL, - SYSZ_INS_VCHLB, - SYSZ_INS_VCHLBS, - SYSZ_INS_VCHLF, - SYSZ_INS_VCHLFS, - SYSZ_INS_VCHLG, - SYSZ_INS_VCHLGS, - SYSZ_INS_VCHLH, - SYSZ_INS_VCHLHS, - SYSZ_INS_VCKSM, - SYSZ_INS_VCLGD, - SYSZ_INS_VCLGDB, - SYSZ_INS_VCLZ, - SYSZ_INS_VCLZB, - SYSZ_INS_VCLZF, - SYSZ_INS_VCLZG, - SYSZ_INS_VCLZH, - SYSZ_INS_VCP, - SYSZ_INS_VCTZ, - SYSZ_INS_VCTZB, - SYSZ_INS_VCTZF, - SYSZ_INS_VCTZG, - SYSZ_INS_VCTZH, - SYSZ_INS_VCVB, - SYSZ_INS_VCVBG, - SYSZ_INS_VCVD, - SYSZ_INS_VCVDG, - SYSZ_INS_VDP, - SYSZ_INS_VEC, - SYSZ_INS_VECB, - SYSZ_INS_VECF, - SYSZ_INS_VECG, - SYSZ_INS_VECH, - SYSZ_INS_VECL, - SYSZ_INS_VECLB, - SYSZ_INS_VECLF, - SYSZ_INS_VECLG, - SYSZ_INS_VECLH, - SYSZ_INS_VERIM, - SYSZ_INS_VERIMB, - SYSZ_INS_VERIMF, - SYSZ_INS_VERIMG, - SYSZ_INS_VERIMH, - SYSZ_INS_VERLL, - SYSZ_INS_VERLLB, - SYSZ_INS_VERLLF, - SYSZ_INS_VERLLG, - SYSZ_INS_VERLLH, - SYSZ_INS_VERLLV, - SYSZ_INS_VERLLVB, - SYSZ_INS_VERLLVF, - SYSZ_INS_VERLLVG, - SYSZ_INS_VERLLVH, - SYSZ_INS_VESL, - SYSZ_INS_VESLB, - SYSZ_INS_VESLF, - SYSZ_INS_VESLG, - SYSZ_INS_VESLH, - SYSZ_INS_VESLV, - SYSZ_INS_VESLVB, - SYSZ_INS_VESLVF, - SYSZ_INS_VESLVG, - SYSZ_INS_VESLVH, - SYSZ_INS_VESRA, - SYSZ_INS_VESRAB, - SYSZ_INS_VESRAF, - SYSZ_INS_VESRAG, - SYSZ_INS_VESRAH, - SYSZ_INS_VESRAV, - SYSZ_INS_VESRAVB, - SYSZ_INS_VESRAVF, - SYSZ_INS_VESRAVG, - SYSZ_INS_VESRAVH, - SYSZ_INS_VESRL, - SYSZ_INS_VESRLB, - SYSZ_INS_VESRLF, - SYSZ_INS_VESRLG, - SYSZ_INS_VESRLH, - SYSZ_INS_VESRLV, - SYSZ_INS_VESRLVB, - SYSZ_INS_VESRLVF, - SYSZ_INS_VESRLVG, - SYSZ_INS_VESRLVH, - SYSZ_INS_VFA, - SYSZ_INS_VFADB, - SYSZ_INS_VFAE, - SYSZ_INS_VFAEB, - SYSZ_INS_VFAEBS, - SYSZ_INS_VFAEF, - SYSZ_INS_VFAEFS, - SYSZ_INS_VFAEH, - SYSZ_INS_VFAEHS, - SYSZ_INS_VFAEZB, - SYSZ_INS_VFAEZBS, - SYSZ_INS_VFAEZF, - SYSZ_INS_VFAEZFS, - SYSZ_INS_VFAEZH, - SYSZ_INS_VFAEZHS, - SYSZ_INS_VFASB, - SYSZ_INS_VFCE, - SYSZ_INS_VFCEDB, - SYSZ_INS_VFCEDBS, - SYSZ_INS_VFCESB, - SYSZ_INS_VFCESBS, - SYSZ_INS_VFCH, - SYSZ_INS_VFCHDB, - SYSZ_INS_VFCHDBS, - SYSZ_INS_VFCHE, - SYSZ_INS_VFCHEDB, - SYSZ_INS_VFCHEDBS, - SYSZ_INS_VFCHESB, - SYSZ_INS_VFCHESBS, - SYSZ_INS_VFCHSB, - SYSZ_INS_VFCHSBS, - SYSZ_INS_VFD, - SYSZ_INS_VFDDB, - SYSZ_INS_VFDSB, - SYSZ_INS_VFEE, - SYSZ_INS_VFEEB, - SYSZ_INS_VFEEBS, - SYSZ_INS_VFEEF, - SYSZ_INS_VFEEFS, - SYSZ_INS_VFEEH, - SYSZ_INS_VFEEHS, - SYSZ_INS_VFEEZB, - SYSZ_INS_VFEEZBS, - SYSZ_INS_VFEEZF, - SYSZ_INS_VFEEZFS, - SYSZ_INS_VFEEZH, - SYSZ_INS_VFEEZHS, - SYSZ_INS_VFENE, - SYSZ_INS_VFENEB, - SYSZ_INS_VFENEBS, - SYSZ_INS_VFENEF, - SYSZ_INS_VFENEFS, - SYSZ_INS_VFENEH, - SYSZ_INS_VFENEHS, - SYSZ_INS_VFENEZB, - SYSZ_INS_VFENEZBS, - SYSZ_INS_VFENEZF, - SYSZ_INS_VFENEZFS, - SYSZ_INS_VFENEZH, - SYSZ_INS_VFENEZHS, - SYSZ_INS_VFI, - SYSZ_INS_VFIDB, - SYSZ_INS_VFISB, - SYSZ_INS_VFKEDB, - SYSZ_INS_VFKEDBS, - SYSZ_INS_VFKESB, - SYSZ_INS_VFKESBS, - SYSZ_INS_VFKHDB, - SYSZ_INS_VFKHDBS, - SYSZ_INS_VFKHEDB, - SYSZ_INS_VFKHEDBS, - SYSZ_INS_VFKHESB, - SYSZ_INS_VFKHESBS, - SYSZ_INS_VFKHSB, - SYSZ_INS_VFKHSBS, - SYSZ_INS_VFLCDB, - SYSZ_INS_VFLCSB, - SYSZ_INS_VFLL, - SYSZ_INS_VFLLS, - SYSZ_INS_VFLNDB, - SYSZ_INS_VFLNSB, - SYSZ_INS_VFLPDB, - SYSZ_INS_VFLPSB, - SYSZ_INS_VFLR, - SYSZ_INS_VFLRD, - SYSZ_INS_VFM, - SYSZ_INS_VFMA, - SYSZ_INS_VFMADB, - SYSZ_INS_VFMASB, - SYSZ_INS_VFMAX, - SYSZ_INS_VFMAXDB, - SYSZ_INS_VFMAXSB, - SYSZ_INS_VFMDB, - SYSZ_INS_VFMIN, - SYSZ_INS_VFMINDB, - SYSZ_INS_VFMINSB, - SYSZ_INS_VFMS, - SYSZ_INS_VFMSB, - SYSZ_INS_VFMSDB, - SYSZ_INS_VFMSSB, - SYSZ_INS_VFNMA, - SYSZ_INS_VFNMADB, - SYSZ_INS_VFNMASB, - SYSZ_INS_VFNMS, - SYSZ_INS_VFNMSDB, - SYSZ_INS_VFNMSSB, - SYSZ_INS_VFPSO, - SYSZ_INS_VFPSODB, - SYSZ_INS_VFPSOSB, - SYSZ_INS_VFS, - SYSZ_INS_VFSDB, - SYSZ_INS_VFSQ, - SYSZ_INS_VFSQDB, - SYSZ_INS_VFSQSB, - SYSZ_INS_VFSSB, - SYSZ_INS_VFTCI, - SYSZ_INS_VFTCIDB, - SYSZ_INS_VFTCISB, - SYSZ_INS_VGBM, - SYSZ_INS_VGEF, - SYSZ_INS_VGEG, - SYSZ_INS_VGFM, - SYSZ_INS_VGFMA, - SYSZ_INS_VGFMAB, - SYSZ_INS_VGFMAF, - SYSZ_INS_VGFMAG, - SYSZ_INS_VGFMAH, - SYSZ_INS_VGFMB, - SYSZ_INS_VGFMF, - SYSZ_INS_VGFMG, - SYSZ_INS_VGFMH, - SYSZ_INS_VGM, - SYSZ_INS_VGMB, - SYSZ_INS_VGMF, - SYSZ_INS_VGMG, - SYSZ_INS_VGMH, - SYSZ_INS_VISTR, - SYSZ_INS_VISTRB, - SYSZ_INS_VISTRBS, - SYSZ_INS_VISTRF, - SYSZ_INS_VISTRFS, - SYSZ_INS_VISTRH, - SYSZ_INS_VISTRHS, - SYSZ_INS_VL, - SYSZ_INS_VLBB, - SYSZ_INS_VLC, - SYSZ_INS_VLCB, - SYSZ_INS_VLCF, - SYSZ_INS_VLCG, - SYSZ_INS_VLCH, - SYSZ_INS_VLDE, - SYSZ_INS_VLDEB, - SYSZ_INS_VLEB, - SYSZ_INS_VLED, - SYSZ_INS_VLEDB, - SYSZ_INS_VLEF, - SYSZ_INS_VLEG, - SYSZ_INS_VLEH, - SYSZ_INS_VLEIB, - SYSZ_INS_VLEIF, - SYSZ_INS_VLEIG, - SYSZ_INS_VLEIH, - SYSZ_INS_VLGV, - SYSZ_INS_VLGVB, - SYSZ_INS_VLGVF, - SYSZ_INS_VLGVG, - SYSZ_INS_VLGVH, - SYSZ_INS_VLIP, - SYSZ_INS_VLL, - SYSZ_INS_VLLEZ, - SYSZ_INS_VLLEZB, - SYSZ_INS_VLLEZF, - SYSZ_INS_VLLEZG, - SYSZ_INS_VLLEZH, - SYSZ_INS_VLLEZLF, - SYSZ_INS_VLM, - SYSZ_INS_VLP, - SYSZ_INS_VLPB, - SYSZ_INS_VLPF, - SYSZ_INS_VLPG, - SYSZ_INS_VLPH, - SYSZ_INS_VLR, - SYSZ_INS_VLREP, - SYSZ_INS_VLREPB, - SYSZ_INS_VLREPF, - SYSZ_INS_VLREPG, - SYSZ_INS_VLREPH, - SYSZ_INS_VLRL, - SYSZ_INS_VLRLR, - SYSZ_INS_VLVG, - SYSZ_INS_VLVGB, - SYSZ_INS_VLVGF, - SYSZ_INS_VLVGG, - SYSZ_INS_VLVGH, - SYSZ_INS_VLVGP, - SYSZ_INS_VMAE, - SYSZ_INS_VMAEB, - SYSZ_INS_VMAEF, - SYSZ_INS_VMAEH, - SYSZ_INS_VMAH, - SYSZ_INS_VMAHB, - SYSZ_INS_VMAHF, - SYSZ_INS_VMAHH, - SYSZ_INS_VMAL, - SYSZ_INS_VMALB, - SYSZ_INS_VMALE, - SYSZ_INS_VMALEB, - SYSZ_INS_VMALEF, - SYSZ_INS_VMALEH, - SYSZ_INS_VMALF, - SYSZ_INS_VMALH, - SYSZ_INS_VMALHB, - SYSZ_INS_VMALHF, - SYSZ_INS_VMALHH, - SYSZ_INS_VMALHW, - SYSZ_INS_VMALO, - SYSZ_INS_VMALOB, - SYSZ_INS_VMALOF, - SYSZ_INS_VMALOH, - SYSZ_INS_VMAO, - SYSZ_INS_VMAOB, - SYSZ_INS_VMAOF, - SYSZ_INS_VMAOH, - SYSZ_INS_VME, - SYSZ_INS_VMEB, - SYSZ_INS_VMEF, - SYSZ_INS_VMEH, - SYSZ_INS_VMH, - SYSZ_INS_VMHB, - SYSZ_INS_VMHF, - SYSZ_INS_VMHH, - SYSZ_INS_VML, - SYSZ_INS_VMLB, - SYSZ_INS_VMLE, - SYSZ_INS_VMLEB, - SYSZ_INS_VMLEF, - SYSZ_INS_VMLEH, - SYSZ_INS_VMLF, - SYSZ_INS_VMLH, - SYSZ_INS_VMLHB, - SYSZ_INS_VMLHF, - SYSZ_INS_VMLHH, - SYSZ_INS_VMLHW, - SYSZ_INS_VMLO, - SYSZ_INS_VMLOB, - SYSZ_INS_VMLOF, - SYSZ_INS_VMLOH, - SYSZ_INS_VMN, - SYSZ_INS_VMNB, - SYSZ_INS_VMNF, - SYSZ_INS_VMNG, - SYSZ_INS_VMNH, - SYSZ_INS_VMNL, - SYSZ_INS_VMNLB, - SYSZ_INS_VMNLF, - SYSZ_INS_VMNLG, - SYSZ_INS_VMNLH, - SYSZ_INS_VMO, - SYSZ_INS_VMOB, - SYSZ_INS_VMOF, - SYSZ_INS_VMOH, - SYSZ_INS_VMP, - SYSZ_INS_VMRH, - SYSZ_INS_VMRHB, - SYSZ_INS_VMRHF, - SYSZ_INS_VMRHG, - SYSZ_INS_VMRHH, - SYSZ_INS_VMRL, - SYSZ_INS_VMRLB, - SYSZ_INS_VMRLF, - SYSZ_INS_VMRLG, - SYSZ_INS_VMRLH, - SYSZ_INS_VMSL, - SYSZ_INS_VMSLG, - SYSZ_INS_VMSP, - SYSZ_INS_VMX, - SYSZ_INS_VMXB, - SYSZ_INS_VMXF, - SYSZ_INS_VMXG, - SYSZ_INS_VMXH, - SYSZ_INS_VMXL, - SYSZ_INS_VMXLB, - SYSZ_INS_VMXLF, - SYSZ_INS_VMXLG, - SYSZ_INS_VMXLH, - SYSZ_INS_VN, - SYSZ_INS_VNC, - SYSZ_INS_VNN, - SYSZ_INS_VNO, - SYSZ_INS_VNX, - SYSZ_INS_VO, - SYSZ_INS_VOC, - SYSZ_INS_VONE, - SYSZ_INS_VPDI, - SYSZ_INS_VPERM, - SYSZ_INS_VPK, - SYSZ_INS_VPKF, - SYSZ_INS_VPKG, - SYSZ_INS_VPKH, - SYSZ_INS_VPKLS, - SYSZ_INS_VPKLSF, - SYSZ_INS_VPKLSFS, - SYSZ_INS_VPKLSG, - SYSZ_INS_VPKLSGS, - SYSZ_INS_VPKLSH, - SYSZ_INS_VPKLSHS, - SYSZ_INS_VPKS, - SYSZ_INS_VPKSF, - SYSZ_INS_VPKSFS, - SYSZ_INS_VPKSG, - SYSZ_INS_VPKSGS, - SYSZ_INS_VPKSH, - SYSZ_INS_VPKSHS, - SYSZ_INS_VPKZ, - SYSZ_INS_VPOPCT, - SYSZ_INS_VPOPCTB, - SYSZ_INS_VPOPCTF, - SYSZ_INS_VPOPCTG, - SYSZ_INS_VPOPCTH, - SYSZ_INS_VPSOP, - SYSZ_INS_VREP, - SYSZ_INS_VREPB, - SYSZ_INS_VREPF, - SYSZ_INS_VREPG, - SYSZ_INS_VREPH, - SYSZ_INS_VREPI, - SYSZ_INS_VREPIB, - SYSZ_INS_VREPIF, - SYSZ_INS_VREPIG, - SYSZ_INS_VREPIH, - SYSZ_INS_VRP, - SYSZ_INS_VS, - SYSZ_INS_VSB, - SYSZ_INS_VSBCBI, - SYSZ_INS_VSBCBIQ, - SYSZ_INS_VSBI, - SYSZ_INS_VSBIQ, - SYSZ_INS_VSCBI, - SYSZ_INS_VSCBIB, - SYSZ_INS_VSCBIF, - SYSZ_INS_VSCBIG, - SYSZ_INS_VSCBIH, - SYSZ_INS_VSCBIQ, - SYSZ_INS_VSCEF, - SYSZ_INS_VSCEG, - SYSZ_INS_VSDP, - SYSZ_INS_VSEG, - SYSZ_INS_VSEGB, - SYSZ_INS_VSEGF, - SYSZ_INS_VSEGH, - SYSZ_INS_VSEL, - SYSZ_INS_VSF, - SYSZ_INS_VSG, - SYSZ_INS_VSH, - SYSZ_INS_VSL, - SYSZ_INS_VSLB, - SYSZ_INS_VSLDB, - SYSZ_INS_VSP, - SYSZ_INS_VSQ, - SYSZ_INS_VSRA, - SYSZ_INS_VSRAB, - SYSZ_INS_VSRL, - SYSZ_INS_VSRLB, - SYSZ_INS_VSRP, - SYSZ_INS_VST, - SYSZ_INS_VSTEB, - SYSZ_INS_VSTEF, - SYSZ_INS_VSTEG, - SYSZ_INS_VSTEH, - SYSZ_INS_VSTL, - SYSZ_INS_VSTM, - SYSZ_INS_VSTRC, - SYSZ_INS_VSTRCB, - SYSZ_INS_VSTRCBS, - SYSZ_INS_VSTRCF, - SYSZ_INS_VSTRCFS, - SYSZ_INS_VSTRCH, - SYSZ_INS_VSTRCHS, - SYSZ_INS_VSTRCZB, - SYSZ_INS_VSTRCZBS, - SYSZ_INS_VSTRCZF, - SYSZ_INS_VSTRCZFS, - SYSZ_INS_VSTRCZH, - SYSZ_INS_VSTRCZHS, - SYSZ_INS_VSTRL, - SYSZ_INS_VSTRLR, - SYSZ_INS_VSUM, - SYSZ_INS_VSUMB, - SYSZ_INS_VSUMG, - SYSZ_INS_VSUMGF, - SYSZ_INS_VSUMGH, - SYSZ_INS_VSUMH, - SYSZ_INS_VSUMQ, - SYSZ_INS_VSUMQF, - SYSZ_INS_VSUMQG, - SYSZ_INS_VTM, - SYSZ_INS_VTP, - SYSZ_INS_VUPH, - SYSZ_INS_VUPHB, - SYSZ_INS_VUPHF, - SYSZ_INS_VUPHH, - SYSZ_INS_VUPKZ, - SYSZ_INS_VUPL, - SYSZ_INS_VUPLB, - SYSZ_INS_VUPLF, - SYSZ_INS_VUPLH, - SYSZ_INS_VUPLHB, - SYSZ_INS_VUPLHF, - SYSZ_INS_VUPLHH, - SYSZ_INS_VUPLHW, - SYSZ_INS_VUPLL, - SYSZ_INS_VUPLLB, - SYSZ_INS_VUPLLF, - SYSZ_INS_VUPLLH, - SYSZ_INS_VX, - SYSZ_INS_VZERO, - SYSZ_INS_WCDGB, - SYSZ_INS_WCDLGB, - SYSZ_INS_WCGDB, - SYSZ_INS_WCLGDB, - SYSZ_INS_WFADB, - SYSZ_INS_WFASB, - SYSZ_INS_WFAXB, - SYSZ_INS_WFC, - SYSZ_INS_WFCDB, - SYSZ_INS_WFCEDB, - SYSZ_INS_WFCEDBS, - SYSZ_INS_WFCESB, - SYSZ_INS_WFCESBS, - SYSZ_INS_WFCEXB, - SYSZ_INS_WFCEXBS, - SYSZ_INS_WFCHDB, - SYSZ_INS_WFCHDBS, - SYSZ_INS_WFCHEDB, - SYSZ_INS_WFCHEDBS, - SYSZ_INS_WFCHESB, - SYSZ_INS_WFCHESBS, - SYSZ_INS_WFCHEXB, - SYSZ_INS_WFCHEXBS, - SYSZ_INS_WFCHSB, - SYSZ_INS_WFCHSBS, - SYSZ_INS_WFCHXB, - SYSZ_INS_WFCHXBS, - SYSZ_INS_WFCSB, - SYSZ_INS_WFCXB, - SYSZ_INS_WFDDB, - SYSZ_INS_WFDSB, - SYSZ_INS_WFDXB, - SYSZ_INS_WFIDB, - SYSZ_INS_WFISB, - SYSZ_INS_WFIXB, - SYSZ_INS_WFK, - SYSZ_INS_WFKDB, - SYSZ_INS_WFKEDB, - SYSZ_INS_WFKEDBS, - SYSZ_INS_WFKESB, - SYSZ_INS_WFKESBS, - SYSZ_INS_WFKEXB, - SYSZ_INS_WFKEXBS, - SYSZ_INS_WFKHDB, - SYSZ_INS_WFKHDBS, - SYSZ_INS_WFKHEDB, - SYSZ_INS_WFKHEDBS, - SYSZ_INS_WFKHESB, - SYSZ_INS_WFKHESBS, - SYSZ_INS_WFKHEXB, - SYSZ_INS_WFKHEXBS, - SYSZ_INS_WFKHSB, - SYSZ_INS_WFKHSBS, - SYSZ_INS_WFKHXB, - SYSZ_INS_WFKHXBS, - SYSZ_INS_WFKSB, - SYSZ_INS_WFKXB, - SYSZ_INS_WFLCDB, - SYSZ_INS_WFLCSB, - SYSZ_INS_WFLCXB, - SYSZ_INS_WFLLD, - SYSZ_INS_WFLLS, - SYSZ_INS_WFLNDB, - SYSZ_INS_WFLNSB, - SYSZ_INS_WFLNXB, - SYSZ_INS_WFLPDB, - SYSZ_INS_WFLPSB, - SYSZ_INS_WFLPXB, - SYSZ_INS_WFLRD, - SYSZ_INS_WFLRX, - SYSZ_INS_WFMADB, - SYSZ_INS_WFMASB, - SYSZ_INS_WFMAXB, - SYSZ_INS_WFMAXDB, - SYSZ_INS_WFMAXSB, - SYSZ_INS_WFMAXXB, - SYSZ_INS_WFMDB, - SYSZ_INS_WFMINDB, - SYSZ_INS_WFMINSB, - SYSZ_INS_WFMINXB, - SYSZ_INS_WFMSB, - SYSZ_INS_WFMSDB, - SYSZ_INS_WFMSSB, - SYSZ_INS_WFMSXB, - SYSZ_INS_WFMXB, - SYSZ_INS_WFNMADB, - SYSZ_INS_WFNMASB, - SYSZ_INS_WFNMAXB, - SYSZ_INS_WFNMSDB, - SYSZ_INS_WFNMSSB, - SYSZ_INS_WFNMSXB, - SYSZ_INS_WFPSODB, - SYSZ_INS_WFPSOSB, - SYSZ_INS_WFPSOXB, - SYSZ_INS_WFSDB, - SYSZ_INS_WFSQDB, - SYSZ_INS_WFSQSB, - SYSZ_INS_WFSQXB, - SYSZ_INS_WFSSB, - SYSZ_INS_WFSXB, - SYSZ_INS_WFTCIDB, - SYSZ_INS_WFTCISB, - SYSZ_INS_WFTCIXB, - SYSZ_INS_WLDEB, - SYSZ_INS_WLEDB, - SYSZ_INS_XSCH, - SYSZ_INS_ZAP, + SYSTEMZ_INS_INVALID, + SYSTEMZ_INS_A, + SYSTEMZ_INS_AD, + SYSTEMZ_INS_ADB, + SYSTEMZ_INS_ADBR, + SYSTEMZ_INS_ADR, + SYSTEMZ_INS_ADTR, + SYSTEMZ_INS_ADTRA, + SYSTEMZ_INS_AE, + SYSTEMZ_INS_AEB, + SYSTEMZ_INS_AEBR, + SYSTEMZ_INS_AER, + SYSTEMZ_INS_AFI, + SYSTEMZ_INS_AG, + SYSTEMZ_INS_AGF, + SYSTEMZ_INS_AGFI, + SYSTEMZ_INS_AGFR, + SYSTEMZ_INS_AGH, + SYSTEMZ_INS_AGHI, + SYSTEMZ_INS_AGHIK, + SYSTEMZ_INS_AGR, + SYSTEMZ_INS_AGRK, + SYSTEMZ_INS_AGSI, + SYSTEMZ_INS_AH, + SYSTEMZ_INS_AHHHR, + SYSTEMZ_INS_AHHLR, + SYSTEMZ_INS_AHI, + SYSTEMZ_INS_AHIK, + SYSTEMZ_INS_AHY, + SYSTEMZ_INS_AIH, + SYSTEMZ_INS_AL, + SYSTEMZ_INS_ALC, + SYSTEMZ_INS_ALCG, + SYSTEMZ_INS_ALCGR, + SYSTEMZ_INS_ALCR, + SYSTEMZ_INS_ALFI, + SYSTEMZ_INS_ALG, + SYSTEMZ_INS_ALGF, + SYSTEMZ_INS_ALGFI, + SYSTEMZ_INS_ALGFR, + SYSTEMZ_INS_ALGHSIK, + SYSTEMZ_INS_ALGR, + SYSTEMZ_INS_ALGRK, + SYSTEMZ_INS_ALGSI, + SYSTEMZ_INS_ALHHHR, + SYSTEMZ_INS_ALHHLR, + SYSTEMZ_INS_ALHSIK, + SYSTEMZ_INS_ALR, + SYSTEMZ_INS_ALRK, + SYSTEMZ_INS_ALSI, + SYSTEMZ_INS_ALSIH, + SYSTEMZ_INS_ALSIHN, + SYSTEMZ_INS_ALY, + SYSTEMZ_INS_AP, + SYSTEMZ_INS_AR, + SYSTEMZ_INS_ARK, + SYSTEMZ_INS_ASI, + SYSTEMZ_INS_AU, + SYSTEMZ_INS_AUR, + SYSTEMZ_INS_AW, + SYSTEMZ_INS_AWR, + SYSTEMZ_INS_AXBR, + SYSTEMZ_INS_AXR, + SYSTEMZ_INS_AXTR, + SYSTEMZ_INS_AXTRA, + SYSTEMZ_INS_AY, + SYSTEMZ_INS_B, + SYSTEMZ_INS_BAKR, + SYSTEMZ_INS_BAL, + SYSTEMZ_INS_BALR, + SYSTEMZ_INS_BAS, + SYSTEMZ_INS_BASR, + SYSTEMZ_INS_BASSM, + SYSTEMZ_INS_BE, + SYSTEMZ_INS_BH, + SYSTEMZ_INS_BHE, + SYSTEMZ_INS_BL, + SYSTEMZ_INS_BLE, + SYSTEMZ_INS_BLH, + SYSTEMZ_INS_BM, + SYSTEMZ_INS_BNE, + SYSTEMZ_INS_BNH, + SYSTEMZ_INS_BNHE, + SYSTEMZ_INS_BNL, + SYSTEMZ_INS_BNLE, + SYSTEMZ_INS_BNLH, + SYSTEMZ_INS_BNM, + SYSTEMZ_INS_BNO, + SYSTEMZ_INS_BNP, + SYSTEMZ_INS_BNZ, + SYSTEMZ_INS_BO, + SYSTEMZ_INS_BP, + SYSTEMZ_INS_BZ, + SYSTEMZ_INS_BC, + SYSTEMZ_INS_BCR, + SYSTEMZ_INS_BCT, + SYSTEMZ_INS_BCTG, + SYSTEMZ_INS_BCTGR, + SYSTEMZ_INS_BCTR, + SYSTEMZ_INS_BI, + SYSTEMZ_INS_BIE, + SYSTEMZ_INS_BIH, + SYSTEMZ_INS_BIHE, + SYSTEMZ_INS_BIL, + SYSTEMZ_INS_BILE, + SYSTEMZ_INS_BILH, + SYSTEMZ_INS_BIM, + SYSTEMZ_INS_BINE, + SYSTEMZ_INS_BINH, + SYSTEMZ_INS_BINHE, + SYSTEMZ_INS_BINL, + SYSTEMZ_INS_BINLE, + SYSTEMZ_INS_BINLH, + SYSTEMZ_INS_BINM, + SYSTEMZ_INS_BINO, + SYSTEMZ_INS_BINP, + SYSTEMZ_INS_BINZ, + SYSTEMZ_INS_BIO, + SYSTEMZ_INS_BIP, + SYSTEMZ_INS_BIZ, + SYSTEMZ_INS_BIC, + SYSTEMZ_INS_BPP, + SYSTEMZ_INS_BPRP, + SYSTEMZ_INS_BR, + SYSTEMZ_INS_BRAS, + SYSTEMZ_INS_BRASL, + SYSTEMZ_INS_BER, + SYSTEMZ_INS_BHR, + SYSTEMZ_INS_BHER, + SYSTEMZ_INS_BLR, + SYSTEMZ_INS_BLER, + SYSTEMZ_INS_BLHR, + SYSTEMZ_INS_BMR, + SYSTEMZ_INS_BNER, + SYSTEMZ_INS_BNHR, + SYSTEMZ_INS_BNHER, + SYSTEMZ_INS_BNLR, + SYSTEMZ_INS_BNLER, + SYSTEMZ_INS_BNLHR, + SYSTEMZ_INS_BNMR, + SYSTEMZ_INS_BNOR, + SYSTEMZ_INS_BNPR, + SYSTEMZ_INS_BNZR, + SYSTEMZ_INS_BOR, + SYSTEMZ_INS_BPR, + SYSTEMZ_INS_BZR, + SYSTEMZ_INS_BRC, + SYSTEMZ_INS_BRCL, + SYSTEMZ_INS_BRCT, + SYSTEMZ_INS_BRCTG, + SYSTEMZ_INS_BRCTH, + SYSTEMZ_INS_BRXH, + SYSTEMZ_INS_BRXHG, + SYSTEMZ_INS_BRXLE, + SYSTEMZ_INS_BRXLG, + SYSTEMZ_INS_BSA, + SYSTEMZ_INS_BSG, + SYSTEMZ_INS_BSM, + SYSTEMZ_INS_BXH, + SYSTEMZ_INS_BXHG, + SYSTEMZ_INS_BXLE, + SYSTEMZ_INS_BXLEG, + SYSTEMZ_INS_C, + SYSTEMZ_INS_CD, + SYSTEMZ_INS_CDB, + SYSTEMZ_INS_CDBR, + SYSTEMZ_INS_CDFBR, + SYSTEMZ_INS_CDFBRA, + SYSTEMZ_INS_CDFR, + SYSTEMZ_INS_CDFTR, + SYSTEMZ_INS_CDGBR, + SYSTEMZ_INS_CDGBRA, + SYSTEMZ_INS_CDGR, + SYSTEMZ_INS_CDGTR, + SYSTEMZ_INS_CDGTRA, + SYSTEMZ_INS_CDLFBR, + SYSTEMZ_INS_CDLFTR, + SYSTEMZ_INS_CDLGBR, + SYSTEMZ_INS_CDLGTR, + SYSTEMZ_INS_CDPT, + SYSTEMZ_INS_CDR, + SYSTEMZ_INS_CDS, + SYSTEMZ_INS_CDSG, + SYSTEMZ_INS_CDSTR, + SYSTEMZ_INS_CDSY, + SYSTEMZ_INS_CDTR, + SYSTEMZ_INS_CDUTR, + SYSTEMZ_INS_CDZT, + SYSTEMZ_INS_CE, + SYSTEMZ_INS_CEB, + SYSTEMZ_INS_CEBR, + SYSTEMZ_INS_CEDTR, + SYSTEMZ_INS_CEFBR, + SYSTEMZ_INS_CEFBRA, + SYSTEMZ_INS_CEFR, + SYSTEMZ_INS_CEGBR, + SYSTEMZ_INS_CEGBRA, + SYSTEMZ_INS_CEGR, + SYSTEMZ_INS_CELFBR, + SYSTEMZ_INS_CELGBR, + SYSTEMZ_INS_CER, + SYSTEMZ_INS_CEXTR, + SYSTEMZ_INS_CFC, + SYSTEMZ_INS_CFDBR, + SYSTEMZ_INS_CFDBRA, + SYSTEMZ_INS_CFDR, + SYSTEMZ_INS_CFDTR, + SYSTEMZ_INS_CFEBR, + SYSTEMZ_INS_CFEBRA, + SYSTEMZ_INS_CFER, + SYSTEMZ_INS_CFI, + SYSTEMZ_INS_CFXBR, + SYSTEMZ_INS_CFXBRA, + SYSTEMZ_INS_CFXR, + SYSTEMZ_INS_CFXTR, + SYSTEMZ_INS_CG, + SYSTEMZ_INS_CGDBR, + SYSTEMZ_INS_CGDBRA, + SYSTEMZ_INS_CGDR, + SYSTEMZ_INS_CGDTR, + SYSTEMZ_INS_CGDTRA, + SYSTEMZ_INS_CGEBR, + SYSTEMZ_INS_CGEBRA, + SYSTEMZ_INS_CGER, + SYSTEMZ_INS_CGF, + SYSTEMZ_INS_CGFI, + SYSTEMZ_INS_CGFR, + SYSTEMZ_INS_CGFRL, + SYSTEMZ_INS_CGH, + SYSTEMZ_INS_CGHI, + SYSTEMZ_INS_CGHRL, + SYSTEMZ_INS_CGHSI, + SYSTEMZ_INS_CGIB, + SYSTEMZ_INS_CGIBE, + SYSTEMZ_INS_CGIBH, + SYSTEMZ_INS_CGIBHE, + SYSTEMZ_INS_CGIBL, + SYSTEMZ_INS_CGIBLE, + SYSTEMZ_INS_CGIBLH, + SYSTEMZ_INS_CGIBNE, + SYSTEMZ_INS_CGIBNH, + SYSTEMZ_INS_CGIBNHE, + SYSTEMZ_INS_CGIBNL, + SYSTEMZ_INS_CGIBNLE, + SYSTEMZ_INS_CGIBNLH, + SYSTEMZ_INS_CGIJ, + SYSTEMZ_INS_CGIJE, + SYSTEMZ_INS_CGIJH, + SYSTEMZ_INS_CGIJHE, + SYSTEMZ_INS_CGIJL, + SYSTEMZ_INS_CGIJLE, + SYSTEMZ_INS_CGIJLH, + SYSTEMZ_INS_CGIJNE, + SYSTEMZ_INS_CGIJNH, + SYSTEMZ_INS_CGIJNHE, + SYSTEMZ_INS_CGIJNL, + SYSTEMZ_INS_CGIJNLE, + SYSTEMZ_INS_CGIJNLH, + SYSTEMZ_INS_CGIT, + SYSTEMZ_INS_CGITE, + SYSTEMZ_INS_CGITH, + SYSTEMZ_INS_CGITHE, + SYSTEMZ_INS_CGITL, + SYSTEMZ_INS_CGITLE, + SYSTEMZ_INS_CGITLH, + SYSTEMZ_INS_CGITNE, + SYSTEMZ_INS_CGITNH, + SYSTEMZ_INS_CGITNHE, + SYSTEMZ_INS_CGITNL, + SYSTEMZ_INS_CGITNLE, + SYSTEMZ_INS_CGITNLH, + SYSTEMZ_INS_CGR, + SYSTEMZ_INS_CGRB, + SYSTEMZ_INS_CGRBE, + SYSTEMZ_INS_CGRBH, + SYSTEMZ_INS_CGRBHE, + SYSTEMZ_INS_CGRBL, + SYSTEMZ_INS_CGRBLE, + SYSTEMZ_INS_CGRBLH, + SYSTEMZ_INS_CGRBNE, + SYSTEMZ_INS_CGRBNH, + SYSTEMZ_INS_CGRBNHE, + SYSTEMZ_INS_CGRBNL, + SYSTEMZ_INS_CGRBNLE, + SYSTEMZ_INS_CGRBNLH, + SYSTEMZ_INS_CGRJ, + SYSTEMZ_INS_CGRJE, + SYSTEMZ_INS_CGRJH, + SYSTEMZ_INS_CGRJHE, + SYSTEMZ_INS_CGRJL, + SYSTEMZ_INS_CGRJLE, + SYSTEMZ_INS_CGRJLH, + SYSTEMZ_INS_CGRJNE, + SYSTEMZ_INS_CGRJNH, + SYSTEMZ_INS_CGRJNHE, + SYSTEMZ_INS_CGRJNL, + SYSTEMZ_INS_CGRJNLE, + SYSTEMZ_INS_CGRJNLH, + SYSTEMZ_INS_CGRL, + SYSTEMZ_INS_CGRT, + SYSTEMZ_INS_CGRTE, + SYSTEMZ_INS_CGRTH, + SYSTEMZ_INS_CGRTHE, + SYSTEMZ_INS_CGRTL, + SYSTEMZ_INS_CGRTLE, + SYSTEMZ_INS_CGRTLH, + SYSTEMZ_INS_CGRTNE, + SYSTEMZ_INS_CGRTNH, + SYSTEMZ_INS_CGRTNHE, + SYSTEMZ_INS_CGRTNL, + SYSTEMZ_INS_CGRTNLE, + SYSTEMZ_INS_CGRTNLH, + SYSTEMZ_INS_CGXBR, + SYSTEMZ_INS_CGXBRA, + SYSTEMZ_INS_CGXR, + SYSTEMZ_INS_CGXTR, + SYSTEMZ_INS_CGXTRA, + SYSTEMZ_INS_CH, + SYSTEMZ_INS_CHF, + SYSTEMZ_INS_CHHR, + SYSTEMZ_INS_CHHSI, + SYSTEMZ_INS_CHI, + SYSTEMZ_INS_CHLR, + SYSTEMZ_INS_CHRL, + SYSTEMZ_INS_CHSI, + SYSTEMZ_INS_CHY, + SYSTEMZ_INS_CIB, + SYSTEMZ_INS_CIBE, + SYSTEMZ_INS_CIBH, + SYSTEMZ_INS_CIBHE, + SYSTEMZ_INS_CIBL, + SYSTEMZ_INS_CIBLE, + SYSTEMZ_INS_CIBLH, + SYSTEMZ_INS_CIBNE, + SYSTEMZ_INS_CIBNH, + SYSTEMZ_INS_CIBNHE, + SYSTEMZ_INS_CIBNL, + SYSTEMZ_INS_CIBNLE, + SYSTEMZ_INS_CIBNLH, + SYSTEMZ_INS_CIH, + SYSTEMZ_INS_CIJ, + SYSTEMZ_INS_CIJE, + SYSTEMZ_INS_CIJH, + SYSTEMZ_INS_CIJHE, + SYSTEMZ_INS_CIJL, + SYSTEMZ_INS_CIJLE, + SYSTEMZ_INS_CIJLH, + SYSTEMZ_INS_CIJNE, + SYSTEMZ_INS_CIJNH, + SYSTEMZ_INS_CIJNHE, + SYSTEMZ_INS_CIJNL, + SYSTEMZ_INS_CIJNLE, + SYSTEMZ_INS_CIJNLH, + SYSTEMZ_INS_CIT, + SYSTEMZ_INS_CITE, + SYSTEMZ_INS_CITH, + SYSTEMZ_INS_CITHE, + SYSTEMZ_INS_CITL, + SYSTEMZ_INS_CITLE, + SYSTEMZ_INS_CITLH, + SYSTEMZ_INS_CITNE, + SYSTEMZ_INS_CITNH, + SYSTEMZ_INS_CITNHE, + SYSTEMZ_INS_CITNL, + SYSTEMZ_INS_CITNLE, + SYSTEMZ_INS_CITNLH, + SYSTEMZ_INS_CKSM, + SYSTEMZ_INS_CL, + SYSTEMZ_INS_CLC, + SYSTEMZ_INS_CLCL, + SYSTEMZ_INS_CLCLE, + SYSTEMZ_INS_CLCLU, + SYSTEMZ_INS_CLFDBR, + SYSTEMZ_INS_CLFDTR, + SYSTEMZ_INS_CLFEBR, + SYSTEMZ_INS_CLFHSI, + SYSTEMZ_INS_CLFI, + SYSTEMZ_INS_CLFIT, + SYSTEMZ_INS_CLFITE, + SYSTEMZ_INS_CLFITH, + SYSTEMZ_INS_CLFITHE, + SYSTEMZ_INS_CLFITL, + SYSTEMZ_INS_CLFITLE, + SYSTEMZ_INS_CLFITLH, + SYSTEMZ_INS_CLFITNE, + SYSTEMZ_INS_CLFITNH, + SYSTEMZ_INS_CLFITNHE, + SYSTEMZ_INS_CLFITNL, + SYSTEMZ_INS_CLFITNLE, + SYSTEMZ_INS_CLFITNLH, + SYSTEMZ_INS_CLFXBR, + SYSTEMZ_INS_CLFXTR, + SYSTEMZ_INS_CLG, + SYSTEMZ_INS_CLGDBR, + SYSTEMZ_INS_CLGDTR, + SYSTEMZ_INS_CLGEBR, + SYSTEMZ_INS_CLGF, + SYSTEMZ_INS_CLGFI, + SYSTEMZ_INS_CLGFR, + SYSTEMZ_INS_CLGFRL, + SYSTEMZ_INS_CLGHRL, + SYSTEMZ_INS_CLGHSI, + SYSTEMZ_INS_CLGIB, + SYSTEMZ_INS_CLGIBE, + SYSTEMZ_INS_CLGIBH, + SYSTEMZ_INS_CLGIBHE, + SYSTEMZ_INS_CLGIBL, + SYSTEMZ_INS_CLGIBLE, + SYSTEMZ_INS_CLGIBLH, + SYSTEMZ_INS_CLGIBNE, + SYSTEMZ_INS_CLGIBNH, + SYSTEMZ_INS_CLGIBNHE, + SYSTEMZ_INS_CLGIBNL, + SYSTEMZ_INS_CLGIBNLE, + SYSTEMZ_INS_CLGIBNLH, + SYSTEMZ_INS_CLGIJ, + SYSTEMZ_INS_CLGIJE, + SYSTEMZ_INS_CLGIJH, + SYSTEMZ_INS_CLGIJHE, + SYSTEMZ_INS_CLGIJL, + SYSTEMZ_INS_CLGIJLE, + SYSTEMZ_INS_CLGIJLH, + SYSTEMZ_INS_CLGIJNE, + SYSTEMZ_INS_CLGIJNH, + SYSTEMZ_INS_CLGIJNHE, + SYSTEMZ_INS_CLGIJNL, + SYSTEMZ_INS_CLGIJNLE, + SYSTEMZ_INS_CLGIJNLH, + SYSTEMZ_INS_CLGIT, + SYSTEMZ_INS_CLGITE, + SYSTEMZ_INS_CLGITH, + SYSTEMZ_INS_CLGITHE, + SYSTEMZ_INS_CLGITL, + SYSTEMZ_INS_CLGITLE, + SYSTEMZ_INS_CLGITLH, + SYSTEMZ_INS_CLGITNE, + SYSTEMZ_INS_CLGITNH, + SYSTEMZ_INS_CLGITNHE, + SYSTEMZ_INS_CLGITNL, + SYSTEMZ_INS_CLGITNLE, + SYSTEMZ_INS_CLGITNLH, + SYSTEMZ_INS_CLGR, + SYSTEMZ_INS_CLGRB, + SYSTEMZ_INS_CLGRBE, + SYSTEMZ_INS_CLGRBH, + SYSTEMZ_INS_CLGRBHE, + SYSTEMZ_INS_CLGRBL, + SYSTEMZ_INS_CLGRBLE, + SYSTEMZ_INS_CLGRBLH, + SYSTEMZ_INS_CLGRBNE, + SYSTEMZ_INS_CLGRBNH, + SYSTEMZ_INS_CLGRBNHE, + SYSTEMZ_INS_CLGRBNL, + SYSTEMZ_INS_CLGRBNLE, + SYSTEMZ_INS_CLGRBNLH, + SYSTEMZ_INS_CLGRJ, + SYSTEMZ_INS_CLGRJE, + SYSTEMZ_INS_CLGRJH, + SYSTEMZ_INS_CLGRJHE, + SYSTEMZ_INS_CLGRJL, + SYSTEMZ_INS_CLGRJLE, + SYSTEMZ_INS_CLGRJLH, + SYSTEMZ_INS_CLGRJNE, + SYSTEMZ_INS_CLGRJNH, + SYSTEMZ_INS_CLGRJNHE, + SYSTEMZ_INS_CLGRJNL, + SYSTEMZ_INS_CLGRJNLE, + SYSTEMZ_INS_CLGRJNLH, + SYSTEMZ_INS_CLGRL, + SYSTEMZ_INS_CLGRT, + SYSTEMZ_INS_CLGRTE, + SYSTEMZ_INS_CLGRTH, + SYSTEMZ_INS_CLGRTHE, + SYSTEMZ_INS_CLGRTL, + SYSTEMZ_INS_CLGRTLE, + SYSTEMZ_INS_CLGRTLH, + SYSTEMZ_INS_CLGRTNE, + SYSTEMZ_INS_CLGRTNH, + SYSTEMZ_INS_CLGRTNHE, + SYSTEMZ_INS_CLGRTNL, + SYSTEMZ_INS_CLGRTNLE, + SYSTEMZ_INS_CLGRTNLH, + SYSTEMZ_INS_CLGT, + SYSTEMZ_INS_CLGTE, + SYSTEMZ_INS_CLGTH, + SYSTEMZ_INS_CLGTHE, + SYSTEMZ_INS_CLGTL, + SYSTEMZ_INS_CLGTLE, + SYSTEMZ_INS_CLGTLH, + SYSTEMZ_INS_CLGTNE, + SYSTEMZ_INS_CLGTNH, + SYSTEMZ_INS_CLGTNHE, + SYSTEMZ_INS_CLGTNL, + SYSTEMZ_INS_CLGTNLE, + SYSTEMZ_INS_CLGTNLH, + SYSTEMZ_INS_CLGXBR, + SYSTEMZ_INS_CLGXTR, + SYSTEMZ_INS_CLHF, + SYSTEMZ_INS_CLHHR, + SYSTEMZ_INS_CLHHSI, + SYSTEMZ_INS_CLHLR, + SYSTEMZ_INS_CLHRL, + SYSTEMZ_INS_CLI, + SYSTEMZ_INS_CLIB, + SYSTEMZ_INS_CLIBE, + SYSTEMZ_INS_CLIBH, + SYSTEMZ_INS_CLIBHE, + SYSTEMZ_INS_CLIBL, + SYSTEMZ_INS_CLIBLE, + SYSTEMZ_INS_CLIBLH, + SYSTEMZ_INS_CLIBNE, + SYSTEMZ_INS_CLIBNH, + SYSTEMZ_INS_CLIBNHE, + SYSTEMZ_INS_CLIBNL, + SYSTEMZ_INS_CLIBNLE, + SYSTEMZ_INS_CLIBNLH, + SYSTEMZ_INS_CLIH, + SYSTEMZ_INS_CLIJ, + SYSTEMZ_INS_CLIJE, + SYSTEMZ_INS_CLIJH, + SYSTEMZ_INS_CLIJHE, + SYSTEMZ_INS_CLIJL, + SYSTEMZ_INS_CLIJLE, + SYSTEMZ_INS_CLIJLH, + SYSTEMZ_INS_CLIJNE, + SYSTEMZ_INS_CLIJNH, + SYSTEMZ_INS_CLIJNHE, + SYSTEMZ_INS_CLIJNL, + SYSTEMZ_INS_CLIJNLE, + SYSTEMZ_INS_CLIJNLH, + SYSTEMZ_INS_CLIY, + SYSTEMZ_INS_CLM, + SYSTEMZ_INS_CLMH, + SYSTEMZ_INS_CLMY, + SYSTEMZ_INS_CLR, + SYSTEMZ_INS_CLRB, + SYSTEMZ_INS_CLRBE, + SYSTEMZ_INS_CLRBH, + SYSTEMZ_INS_CLRBHE, + SYSTEMZ_INS_CLRBL, + SYSTEMZ_INS_CLRBLE, + SYSTEMZ_INS_CLRBLH, + SYSTEMZ_INS_CLRBNE, + SYSTEMZ_INS_CLRBNH, + SYSTEMZ_INS_CLRBNHE, + SYSTEMZ_INS_CLRBNL, + SYSTEMZ_INS_CLRBNLE, + SYSTEMZ_INS_CLRBNLH, + SYSTEMZ_INS_CLRJ, + SYSTEMZ_INS_CLRJE, + SYSTEMZ_INS_CLRJH, + SYSTEMZ_INS_CLRJHE, + SYSTEMZ_INS_CLRJL, + SYSTEMZ_INS_CLRJLE, + SYSTEMZ_INS_CLRJLH, + SYSTEMZ_INS_CLRJNE, + SYSTEMZ_INS_CLRJNH, + SYSTEMZ_INS_CLRJNHE, + SYSTEMZ_INS_CLRJNL, + SYSTEMZ_INS_CLRJNLE, + SYSTEMZ_INS_CLRJNLH, + SYSTEMZ_INS_CLRL, + SYSTEMZ_INS_CLRT, + SYSTEMZ_INS_CLRTE, + SYSTEMZ_INS_CLRTH, + SYSTEMZ_INS_CLRTHE, + SYSTEMZ_INS_CLRTL, + SYSTEMZ_INS_CLRTLE, + SYSTEMZ_INS_CLRTLH, + SYSTEMZ_INS_CLRTNE, + SYSTEMZ_INS_CLRTNH, + SYSTEMZ_INS_CLRTNHE, + SYSTEMZ_INS_CLRTNL, + SYSTEMZ_INS_CLRTNLE, + SYSTEMZ_INS_CLRTNLH, + SYSTEMZ_INS_CLST, + SYSTEMZ_INS_CLT, + SYSTEMZ_INS_CLTE, + SYSTEMZ_INS_CLTH, + SYSTEMZ_INS_CLTHE, + SYSTEMZ_INS_CLTL, + SYSTEMZ_INS_CLTLE, + SYSTEMZ_INS_CLTLH, + SYSTEMZ_INS_CLTNE, + SYSTEMZ_INS_CLTNH, + SYSTEMZ_INS_CLTNHE, + SYSTEMZ_INS_CLTNL, + SYSTEMZ_INS_CLTNLE, + SYSTEMZ_INS_CLTNLH, + SYSTEMZ_INS_CLY, + SYSTEMZ_INS_CMPSC, + SYSTEMZ_INS_CP, + SYSTEMZ_INS_CPDT, + SYSTEMZ_INS_CPSDR, + SYSTEMZ_INS_CPXT, + SYSTEMZ_INS_CPYA, + SYSTEMZ_INS_CR, + SYSTEMZ_INS_CRB, + SYSTEMZ_INS_CRBE, + SYSTEMZ_INS_CRBH, + SYSTEMZ_INS_CRBHE, + SYSTEMZ_INS_CRBL, + SYSTEMZ_INS_CRBLE, + SYSTEMZ_INS_CRBLH, + SYSTEMZ_INS_CRBNE, + SYSTEMZ_INS_CRBNH, + SYSTEMZ_INS_CRBNHE, + SYSTEMZ_INS_CRBNL, + SYSTEMZ_INS_CRBNLE, + SYSTEMZ_INS_CRBNLH, + SYSTEMZ_INS_CRDTE, + SYSTEMZ_INS_CRJ, + SYSTEMZ_INS_CRJE, + SYSTEMZ_INS_CRJH, + SYSTEMZ_INS_CRJHE, + SYSTEMZ_INS_CRJL, + SYSTEMZ_INS_CRJLE, + SYSTEMZ_INS_CRJLH, + SYSTEMZ_INS_CRJNE, + SYSTEMZ_INS_CRJNH, + SYSTEMZ_INS_CRJNHE, + SYSTEMZ_INS_CRJNL, + SYSTEMZ_INS_CRJNLE, + SYSTEMZ_INS_CRJNLH, + SYSTEMZ_INS_CRL, + SYSTEMZ_INS_CRT, + SYSTEMZ_INS_CRTE, + SYSTEMZ_INS_CRTH, + SYSTEMZ_INS_CRTHE, + SYSTEMZ_INS_CRTL, + SYSTEMZ_INS_CRTLE, + SYSTEMZ_INS_CRTLH, + SYSTEMZ_INS_CRTNE, + SYSTEMZ_INS_CRTNH, + SYSTEMZ_INS_CRTNHE, + SYSTEMZ_INS_CRTNL, + SYSTEMZ_INS_CRTNLE, + SYSTEMZ_INS_CRTNLH, + SYSTEMZ_INS_CS, + SYSTEMZ_INS_CSCH, + SYSTEMZ_INS_CSDTR, + SYSTEMZ_INS_CSG, + SYSTEMZ_INS_CSP, + SYSTEMZ_INS_CSPG, + SYSTEMZ_INS_CSST, + SYSTEMZ_INS_CSXTR, + SYSTEMZ_INS_CSY, + SYSTEMZ_INS_CU12, + SYSTEMZ_INS_CU14, + SYSTEMZ_INS_CU21, + SYSTEMZ_INS_CU24, + SYSTEMZ_INS_CU41, + SYSTEMZ_INS_CU42, + SYSTEMZ_INS_CUDTR, + SYSTEMZ_INS_CUSE, + SYSTEMZ_INS_CUTFU, + SYSTEMZ_INS_CUUTF, + SYSTEMZ_INS_CUXTR, + SYSTEMZ_INS_CVB, + SYSTEMZ_INS_CVBG, + SYSTEMZ_INS_CVBY, + SYSTEMZ_INS_CVD, + SYSTEMZ_INS_CVDG, + SYSTEMZ_INS_CVDY, + SYSTEMZ_INS_CXBR, + SYSTEMZ_INS_CXFBR, + SYSTEMZ_INS_CXFBRA, + SYSTEMZ_INS_CXFR, + SYSTEMZ_INS_CXFTR, + SYSTEMZ_INS_CXGBR, + SYSTEMZ_INS_CXGBRA, + SYSTEMZ_INS_CXGR, + SYSTEMZ_INS_CXGTR, + SYSTEMZ_INS_CXGTRA, + SYSTEMZ_INS_CXLFBR, + SYSTEMZ_INS_CXLFTR, + SYSTEMZ_INS_CXLGBR, + SYSTEMZ_INS_CXLGTR, + SYSTEMZ_INS_CXPT, + SYSTEMZ_INS_CXR, + SYSTEMZ_INS_CXSTR, + SYSTEMZ_INS_CXTR, + SYSTEMZ_INS_CXUTR, + SYSTEMZ_INS_CXZT, + SYSTEMZ_INS_CY, + SYSTEMZ_INS_CZDT, + SYSTEMZ_INS_CZXT, + SYSTEMZ_INS_D, + SYSTEMZ_INS_DD, + SYSTEMZ_INS_DDB, + SYSTEMZ_INS_DDBR, + SYSTEMZ_INS_DDR, + SYSTEMZ_INS_DDTR, + SYSTEMZ_INS_DDTRA, + SYSTEMZ_INS_DE, + SYSTEMZ_INS_DEB, + SYSTEMZ_INS_DEBR, + SYSTEMZ_INS_DER, + SYSTEMZ_INS_DFLTCC, + SYSTEMZ_INS_DIAG, + SYSTEMZ_INS_DIDBR, + SYSTEMZ_INS_DIEBR, + SYSTEMZ_INS_DL, + SYSTEMZ_INS_DLG, + SYSTEMZ_INS_DLGR, + SYSTEMZ_INS_DLR, + SYSTEMZ_INS_DP, + SYSTEMZ_INS_DR, + SYSTEMZ_INS_DSG, + SYSTEMZ_INS_DSGF, + SYSTEMZ_INS_DSGFR, + SYSTEMZ_INS_DSGR, + SYSTEMZ_INS_DXBR, + SYSTEMZ_INS_DXR, + SYSTEMZ_INS_DXTR, + SYSTEMZ_INS_DXTRA, + SYSTEMZ_INS_EAR, + SYSTEMZ_INS_ECAG, + SYSTEMZ_INS_ECCTR, + SYSTEMZ_INS_ECPGA, + SYSTEMZ_INS_ECTG, + SYSTEMZ_INS_ED, + SYSTEMZ_INS_EDMK, + SYSTEMZ_INS_EEDTR, + SYSTEMZ_INS_EEXTR, + SYSTEMZ_INS_EFPC, + SYSTEMZ_INS_EPAIR, + SYSTEMZ_INS_EPAR, + SYSTEMZ_INS_EPCTR, + SYSTEMZ_INS_EPSW, + SYSTEMZ_INS_EREG, + SYSTEMZ_INS_EREGG, + SYSTEMZ_INS_ESAIR, + SYSTEMZ_INS_ESAR, + SYSTEMZ_INS_ESDTR, + SYSTEMZ_INS_ESEA, + SYSTEMZ_INS_ESTA, + SYSTEMZ_INS_ESXTR, + SYSTEMZ_INS_ETND, + SYSTEMZ_INS_EX, + SYSTEMZ_INS_EXRL, + SYSTEMZ_INS_FIDBR, + SYSTEMZ_INS_FIDBRA, + SYSTEMZ_INS_FIDR, + SYSTEMZ_INS_FIDTR, + SYSTEMZ_INS_FIEBR, + SYSTEMZ_INS_FIEBRA, + SYSTEMZ_INS_FIER, + SYSTEMZ_INS_FIXBR, + SYSTEMZ_INS_FIXBRA, + SYSTEMZ_INS_FIXR, + SYSTEMZ_INS_FIXTR, + SYSTEMZ_INS_FLOGR, + SYSTEMZ_INS_HDR, + SYSTEMZ_INS_HER, + SYSTEMZ_INS_HSCH, + SYSTEMZ_INS_IAC, + SYSTEMZ_INS_IC, + SYSTEMZ_INS_ICM, + SYSTEMZ_INS_ICMH, + SYSTEMZ_INS_ICMY, + SYSTEMZ_INS_ICY, + SYSTEMZ_INS_IDTE, + SYSTEMZ_INS_IEDTR, + SYSTEMZ_INS_IEXTR, + SYSTEMZ_INS_IIHF, + SYSTEMZ_INS_IIHH, + SYSTEMZ_INS_IIHL, + SYSTEMZ_INS_IILF, + SYSTEMZ_INS_IILH, + SYSTEMZ_INS_IILL, + SYSTEMZ_INS_IPK, + SYSTEMZ_INS_IPM, + SYSTEMZ_INS_IPTE, + SYSTEMZ_INS_IRBM, + SYSTEMZ_INS_ISKE, + SYSTEMZ_INS_IVSK, + SYSTEMZ_INS_J, + SYSTEMZ_INS_JE, + SYSTEMZ_INS_JH, + SYSTEMZ_INS_JHE, + SYSTEMZ_INS_JL, + SYSTEMZ_INS_JLE, + SYSTEMZ_INS_JLH, + SYSTEMZ_INS_JM, + SYSTEMZ_INS_JNE, + SYSTEMZ_INS_JNH, + SYSTEMZ_INS_JNHE, + SYSTEMZ_INS_JNL, + SYSTEMZ_INS_JNLE, + SYSTEMZ_INS_JNLH, + SYSTEMZ_INS_JNM, + SYSTEMZ_INS_JNO, + SYSTEMZ_INS_JNP, + SYSTEMZ_INS_JNZ, + SYSTEMZ_INS_JO, + SYSTEMZ_INS_JP, + SYSTEMZ_INS_JZ, + SYSTEMZ_INS_J_G_LU_, + SYSTEMZ_INS_J_G_L_E, + SYSTEMZ_INS_J_G_L_H, + SYSTEMZ_INS_J_G_L_HE, + SYSTEMZ_INS_J_G_L_L, + SYSTEMZ_INS_J_G_L_LE, + SYSTEMZ_INS_J_G_L_LH, + SYSTEMZ_INS_J_G_L_M, + SYSTEMZ_INS_J_G_L_NE, + SYSTEMZ_INS_J_G_L_NH, + SYSTEMZ_INS_J_G_L_NHE, + SYSTEMZ_INS_J_G_L_NL, + SYSTEMZ_INS_J_G_L_NLE, + SYSTEMZ_INS_J_G_L_NLH, + SYSTEMZ_INS_J_G_L_NM, + SYSTEMZ_INS_J_G_L_NO, + SYSTEMZ_INS_J_G_L_NP, + SYSTEMZ_INS_J_G_L_NZ, + SYSTEMZ_INS_J_G_L_O, + SYSTEMZ_INS_J_G_L_P, + SYSTEMZ_INS_J_G_L_Z, + SYSTEMZ_INS_KDB, + SYSTEMZ_INS_KDBR, + SYSTEMZ_INS_KDSA, + SYSTEMZ_INS_KDTR, + SYSTEMZ_INS_KEB, + SYSTEMZ_INS_KEBR, + SYSTEMZ_INS_KIMD, + SYSTEMZ_INS_KLMD, + SYSTEMZ_INS_KM, + SYSTEMZ_INS_KMA, + SYSTEMZ_INS_KMAC, + SYSTEMZ_INS_KMC, + SYSTEMZ_INS_KMCTR, + SYSTEMZ_INS_KMF, + SYSTEMZ_INS_KMO, + SYSTEMZ_INS_KXBR, + SYSTEMZ_INS_KXTR, + SYSTEMZ_INS_L, + SYSTEMZ_INS_LA, + SYSTEMZ_INS_LAA, + SYSTEMZ_INS_LAAG, + SYSTEMZ_INS_LAAL, + SYSTEMZ_INS_LAALG, + SYSTEMZ_INS_LAE, + SYSTEMZ_INS_LAEY, + SYSTEMZ_INS_LAM, + SYSTEMZ_INS_LAMY, + SYSTEMZ_INS_LAN, + SYSTEMZ_INS_LANG, + SYSTEMZ_INS_LAO, + SYSTEMZ_INS_LAOG, + SYSTEMZ_INS_LARL, + SYSTEMZ_INS_LASP, + SYSTEMZ_INS_LAT, + SYSTEMZ_INS_LAX, + SYSTEMZ_INS_LAXG, + SYSTEMZ_INS_LAY, + SYSTEMZ_INS_LB, + SYSTEMZ_INS_LBEAR, + SYSTEMZ_INS_LBH, + SYSTEMZ_INS_LBR, + SYSTEMZ_INS_LCBB, + SYSTEMZ_INS_LCCTL, + SYSTEMZ_INS_LCDBR, + SYSTEMZ_INS_LCDFR, + SYSTEMZ_INS_LCDR, + SYSTEMZ_INS_LCEBR, + SYSTEMZ_INS_LCER, + SYSTEMZ_INS_LCGFR, + SYSTEMZ_INS_LCGR, + SYSTEMZ_INS_LCR, + SYSTEMZ_INS_LCTL, + SYSTEMZ_INS_LCTLG, + SYSTEMZ_INS_LCXBR, + SYSTEMZ_INS_LCXR, + SYSTEMZ_INS_LD, + SYSTEMZ_INS_LDE, + SYSTEMZ_INS_LDEB, + SYSTEMZ_INS_LDEBR, + SYSTEMZ_INS_LDER, + SYSTEMZ_INS_LDETR, + SYSTEMZ_INS_LDGR, + SYSTEMZ_INS_LDR, + SYSTEMZ_INS_LDXBR, + SYSTEMZ_INS_LDXBRA, + SYSTEMZ_INS_LDXR, + SYSTEMZ_INS_LDXTR, + SYSTEMZ_INS_LDY, + SYSTEMZ_INS_LE, + SYSTEMZ_INS_LEDBR, + SYSTEMZ_INS_LEDBRA, + SYSTEMZ_INS_LEDR, + SYSTEMZ_INS_LEDTR, + SYSTEMZ_INS_LER, + SYSTEMZ_INS_LEXBR, + SYSTEMZ_INS_LEXBRA, + SYSTEMZ_INS_LEXR, + SYSTEMZ_INS_LEY, + SYSTEMZ_INS_LFAS, + SYSTEMZ_INS_LFH, + SYSTEMZ_INS_LFHAT, + SYSTEMZ_INS_LFPC, + SYSTEMZ_INS_LG, + SYSTEMZ_INS_LGAT, + SYSTEMZ_INS_LGB, + SYSTEMZ_INS_LGBR, + SYSTEMZ_INS_LGDR, + SYSTEMZ_INS_LGF, + SYSTEMZ_INS_LGFI, + SYSTEMZ_INS_LGFR, + SYSTEMZ_INS_LGFRL, + SYSTEMZ_INS_LGG, + SYSTEMZ_INS_LGH, + SYSTEMZ_INS_LGHI, + SYSTEMZ_INS_LGHR, + SYSTEMZ_INS_LGHRL, + SYSTEMZ_INS_LGR, + SYSTEMZ_INS_LGRL, + SYSTEMZ_INS_LGSC, + SYSTEMZ_INS_LH, + SYSTEMZ_INS_LHH, + SYSTEMZ_INS_LHI, + SYSTEMZ_INS_LHR, + SYSTEMZ_INS_LHRL, + SYSTEMZ_INS_LHY, + SYSTEMZ_INS_LLC, + SYSTEMZ_INS_LLCH, + SYSTEMZ_INS_LLCR, + SYSTEMZ_INS_LLGC, + SYSTEMZ_INS_LLGCR, + SYSTEMZ_INS_LLGF, + SYSTEMZ_INS_LLGFAT, + SYSTEMZ_INS_LLGFR, + SYSTEMZ_INS_LLGFRL, + SYSTEMZ_INS_LLGFSG, + SYSTEMZ_INS_LLGH, + SYSTEMZ_INS_LLGHR, + SYSTEMZ_INS_LLGHRL, + SYSTEMZ_INS_LLGT, + SYSTEMZ_INS_LLGTAT, + SYSTEMZ_INS_LLGTR, + SYSTEMZ_INS_LLH, + SYSTEMZ_INS_LLHH, + SYSTEMZ_INS_LLHR, + SYSTEMZ_INS_LLHRL, + SYSTEMZ_INS_LLIHF, + SYSTEMZ_INS_LLIHH, + SYSTEMZ_INS_LLIHL, + SYSTEMZ_INS_LLILF, + SYSTEMZ_INS_LLILH, + SYSTEMZ_INS_LLILL, + SYSTEMZ_INS_LLZRGF, + SYSTEMZ_INS_LM, + SYSTEMZ_INS_LMD, + SYSTEMZ_INS_LMG, + SYSTEMZ_INS_LMH, + SYSTEMZ_INS_LMY, + SYSTEMZ_INS_LNDBR, + SYSTEMZ_INS_LNDFR, + SYSTEMZ_INS_LNDR, + SYSTEMZ_INS_LNEBR, + SYSTEMZ_INS_LNER, + SYSTEMZ_INS_LNGFR, + SYSTEMZ_INS_LNGR, + SYSTEMZ_INS_LNR, + SYSTEMZ_INS_LNXBR, + SYSTEMZ_INS_LNXR, + SYSTEMZ_INS_LOC, + SYSTEMZ_INS_LOCE, + SYSTEMZ_INS_LOCH, + SYSTEMZ_INS_LOCHE, + SYSTEMZ_INS_LOCL, + SYSTEMZ_INS_LOCLE, + SYSTEMZ_INS_LOCLH, + SYSTEMZ_INS_LOCM, + SYSTEMZ_INS_LOCNE, + SYSTEMZ_INS_LOCNH, + SYSTEMZ_INS_LOCNHE, + SYSTEMZ_INS_LOCNL, + SYSTEMZ_INS_LOCNLE, + SYSTEMZ_INS_LOCNLH, + SYSTEMZ_INS_LOCNM, + SYSTEMZ_INS_LOCNO, + SYSTEMZ_INS_LOCNP, + SYSTEMZ_INS_LOCNZ, + SYSTEMZ_INS_LOCO, + SYSTEMZ_INS_LOCP, + SYSTEMZ_INS_LOCZ, + SYSTEMZ_INS_LOCFH, + SYSTEMZ_INS_LOCFHE, + SYSTEMZ_INS_LOCFHH, + SYSTEMZ_INS_LOCFHHE, + SYSTEMZ_INS_LOCFHL, + SYSTEMZ_INS_LOCFHLE, + SYSTEMZ_INS_LOCFHLH, + SYSTEMZ_INS_LOCFHM, + SYSTEMZ_INS_LOCFHNE, + SYSTEMZ_INS_LOCFHNH, + SYSTEMZ_INS_LOCFHNHE, + SYSTEMZ_INS_LOCFHNL, + SYSTEMZ_INS_LOCFHNLE, + SYSTEMZ_INS_LOCFHNLH, + SYSTEMZ_INS_LOCFHNM, + SYSTEMZ_INS_LOCFHNO, + SYSTEMZ_INS_LOCFHNP, + SYSTEMZ_INS_LOCFHNZ, + SYSTEMZ_INS_LOCFHO, + SYSTEMZ_INS_LOCFHP, + SYSTEMZ_INS_LOCFHZ, + SYSTEMZ_INS_LOCFHR, + SYSTEMZ_INS_LOCFHRE, + SYSTEMZ_INS_LOCFHRH, + SYSTEMZ_INS_LOCFHRHE, + SYSTEMZ_INS_LOCFHRL, + SYSTEMZ_INS_LOCFHRLE, + SYSTEMZ_INS_LOCFHRLH, + SYSTEMZ_INS_LOCFHRM, + SYSTEMZ_INS_LOCFHRNE, + SYSTEMZ_INS_LOCFHRNH, + SYSTEMZ_INS_LOCFHRNHE, + SYSTEMZ_INS_LOCFHRNL, + SYSTEMZ_INS_LOCFHRNLE, + SYSTEMZ_INS_LOCFHRNLH, + SYSTEMZ_INS_LOCFHRNM, + SYSTEMZ_INS_LOCFHRNO, + SYSTEMZ_INS_LOCFHRNP, + SYSTEMZ_INS_LOCFHRNZ, + SYSTEMZ_INS_LOCFHRO, + SYSTEMZ_INS_LOCFHRP, + SYSTEMZ_INS_LOCFHRZ, + SYSTEMZ_INS_LOCG, + SYSTEMZ_INS_LOCGE, + SYSTEMZ_INS_LOCGH, + SYSTEMZ_INS_LOCGHE, + SYSTEMZ_INS_LOCGL, + SYSTEMZ_INS_LOCGLE, + SYSTEMZ_INS_LOCGLH, + SYSTEMZ_INS_LOCGM, + SYSTEMZ_INS_LOCGNE, + SYSTEMZ_INS_LOCGNH, + SYSTEMZ_INS_LOCGNHE, + SYSTEMZ_INS_LOCGNL, + SYSTEMZ_INS_LOCGNLE, + SYSTEMZ_INS_LOCGNLH, + SYSTEMZ_INS_LOCGNM, + SYSTEMZ_INS_LOCGNO, + SYSTEMZ_INS_LOCGNP, + SYSTEMZ_INS_LOCGNZ, + SYSTEMZ_INS_LOCGO, + SYSTEMZ_INS_LOCGP, + SYSTEMZ_INS_LOCGZ, + SYSTEMZ_INS_LOCGHI, + SYSTEMZ_INS_LOCGHIE, + SYSTEMZ_INS_LOCGHIH, + SYSTEMZ_INS_LOCGHIHE, + SYSTEMZ_INS_LOCGHIL, + SYSTEMZ_INS_LOCGHILE, + SYSTEMZ_INS_LOCGHILH, + SYSTEMZ_INS_LOCGHIM, + SYSTEMZ_INS_LOCGHINE, + SYSTEMZ_INS_LOCGHINH, + SYSTEMZ_INS_LOCGHINHE, + SYSTEMZ_INS_LOCGHINL, + SYSTEMZ_INS_LOCGHINLE, + SYSTEMZ_INS_LOCGHINLH, + SYSTEMZ_INS_LOCGHINM, + SYSTEMZ_INS_LOCGHINO, + SYSTEMZ_INS_LOCGHINP, + SYSTEMZ_INS_LOCGHINZ, + SYSTEMZ_INS_LOCGHIO, + SYSTEMZ_INS_LOCGHIP, + SYSTEMZ_INS_LOCGHIZ, + SYSTEMZ_INS_LOCGR, + SYSTEMZ_INS_LOCGRE, + SYSTEMZ_INS_LOCGRH, + SYSTEMZ_INS_LOCGRHE, + SYSTEMZ_INS_LOCGRL, + SYSTEMZ_INS_LOCGRLE, + SYSTEMZ_INS_LOCGRLH, + SYSTEMZ_INS_LOCGRM, + SYSTEMZ_INS_LOCGRNE, + SYSTEMZ_INS_LOCGRNH, + SYSTEMZ_INS_LOCGRNHE, + SYSTEMZ_INS_LOCGRNL, + SYSTEMZ_INS_LOCGRNLE, + SYSTEMZ_INS_LOCGRNLH, + SYSTEMZ_INS_LOCGRNM, + SYSTEMZ_INS_LOCGRNO, + SYSTEMZ_INS_LOCGRNP, + SYSTEMZ_INS_LOCGRNZ, + SYSTEMZ_INS_LOCGRO, + SYSTEMZ_INS_LOCGRP, + SYSTEMZ_INS_LOCGRZ, + SYSTEMZ_INS_LOCHHI, + SYSTEMZ_INS_LOCHHIE, + SYSTEMZ_INS_LOCHHIH, + SYSTEMZ_INS_LOCHHIHE, + SYSTEMZ_INS_LOCHHIL, + SYSTEMZ_INS_LOCHHILE, + SYSTEMZ_INS_LOCHHILH, + SYSTEMZ_INS_LOCHHIM, + SYSTEMZ_INS_LOCHHINE, + SYSTEMZ_INS_LOCHHINH, + SYSTEMZ_INS_LOCHHINHE, + SYSTEMZ_INS_LOCHHINL, + SYSTEMZ_INS_LOCHHINLE, + SYSTEMZ_INS_LOCHHINLH, + SYSTEMZ_INS_LOCHHINM, + SYSTEMZ_INS_LOCHHINO, + SYSTEMZ_INS_LOCHHINP, + SYSTEMZ_INS_LOCHHINZ, + SYSTEMZ_INS_LOCHHIO, + SYSTEMZ_INS_LOCHHIP, + SYSTEMZ_INS_LOCHHIZ, + SYSTEMZ_INS_LOCHI, + SYSTEMZ_INS_LOCHIE, + SYSTEMZ_INS_LOCHIH, + SYSTEMZ_INS_LOCHIHE, + SYSTEMZ_INS_LOCHIL, + SYSTEMZ_INS_LOCHILE, + SYSTEMZ_INS_LOCHILH, + SYSTEMZ_INS_LOCHIM, + SYSTEMZ_INS_LOCHINE, + SYSTEMZ_INS_LOCHINH, + SYSTEMZ_INS_LOCHINHE, + SYSTEMZ_INS_LOCHINL, + SYSTEMZ_INS_LOCHINLE, + SYSTEMZ_INS_LOCHINLH, + SYSTEMZ_INS_LOCHINM, + SYSTEMZ_INS_LOCHINO, + SYSTEMZ_INS_LOCHINP, + SYSTEMZ_INS_LOCHINZ, + SYSTEMZ_INS_LOCHIO, + SYSTEMZ_INS_LOCHIP, + SYSTEMZ_INS_LOCHIZ, + SYSTEMZ_INS_LOCR, + SYSTEMZ_INS_LOCRE, + SYSTEMZ_INS_LOCRH, + SYSTEMZ_INS_LOCRHE, + SYSTEMZ_INS_LOCRL, + SYSTEMZ_INS_LOCRLE, + SYSTEMZ_INS_LOCRLH, + SYSTEMZ_INS_LOCRM, + SYSTEMZ_INS_LOCRNE, + SYSTEMZ_INS_LOCRNH, + SYSTEMZ_INS_LOCRNHE, + SYSTEMZ_INS_LOCRNL, + SYSTEMZ_INS_LOCRNLE, + SYSTEMZ_INS_LOCRNLH, + SYSTEMZ_INS_LOCRNM, + SYSTEMZ_INS_LOCRNO, + SYSTEMZ_INS_LOCRNP, + SYSTEMZ_INS_LOCRNZ, + SYSTEMZ_INS_LOCRO, + SYSTEMZ_INS_LOCRP, + SYSTEMZ_INS_LOCRZ, + SYSTEMZ_INS_LPCTL, + SYSTEMZ_INS_LPD, + SYSTEMZ_INS_LPDBR, + SYSTEMZ_INS_LPDFR, + SYSTEMZ_INS_LPDG, + SYSTEMZ_INS_LPDR, + SYSTEMZ_INS_LPEBR, + SYSTEMZ_INS_LPER, + SYSTEMZ_INS_LPGFR, + SYSTEMZ_INS_LPGR, + SYSTEMZ_INS_LPP, + SYSTEMZ_INS_LPQ, + SYSTEMZ_INS_LPR, + SYSTEMZ_INS_LPSW, + SYSTEMZ_INS_LPSWE, + SYSTEMZ_INS_LPSWEY, + SYSTEMZ_INS_LPTEA, + SYSTEMZ_INS_LPXBR, + SYSTEMZ_INS_LPXR, + SYSTEMZ_INS_LR, + SYSTEMZ_INS_LRA, + SYSTEMZ_INS_LRAG, + SYSTEMZ_INS_LRAY, + SYSTEMZ_INS_LRDR, + SYSTEMZ_INS_LRER, + SYSTEMZ_INS_LRL, + SYSTEMZ_INS_LRV, + SYSTEMZ_INS_LRVG, + SYSTEMZ_INS_LRVGR, + SYSTEMZ_INS_LRVH, + SYSTEMZ_INS_LRVR, + SYSTEMZ_INS_LSCTL, + SYSTEMZ_INS_LT, + SYSTEMZ_INS_LTDBR, + SYSTEMZ_INS_LTDR, + SYSTEMZ_INS_LTDTR, + SYSTEMZ_INS_LTEBR, + SYSTEMZ_INS_LTER, + SYSTEMZ_INS_LTG, + SYSTEMZ_INS_LTGF, + SYSTEMZ_INS_LTGFR, + SYSTEMZ_INS_LTGR, + SYSTEMZ_INS_LTR, + SYSTEMZ_INS_LTXBR, + SYSTEMZ_INS_LTXR, + SYSTEMZ_INS_LTXTR, + SYSTEMZ_INS_LURA, + SYSTEMZ_INS_LURAG, + SYSTEMZ_INS_LXD, + SYSTEMZ_INS_LXDB, + SYSTEMZ_INS_LXDBR, + SYSTEMZ_INS_LXDR, + SYSTEMZ_INS_LXDTR, + SYSTEMZ_INS_LXE, + SYSTEMZ_INS_LXEB, + SYSTEMZ_INS_LXEBR, + SYSTEMZ_INS_LXER, + SYSTEMZ_INS_LXR, + SYSTEMZ_INS_LY, + SYSTEMZ_INS_LZDR, + SYSTEMZ_INS_LZER, + SYSTEMZ_INS_LZRF, + SYSTEMZ_INS_LZRG, + SYSTEMZ_INS_LZXR, + SYSTEMZ_INS_M, + SYSTEMZ_INS_MAD, + SYSTEMZ_INS_MADB, + SYSTEMZ_INS_MADBR, + SYSTEMZ_INS_MADR, + SYSTEMZ_INS_MAE, + SYSTEMZ_INS_MAEB, + SYSTEMZ_INS_MAEBR, + SYSTEMZ_INS_MAER, + SYSTEMZ_INS_MAY, + SYSTEMZ_INS_MAYH, + SYSTEMZ_INS_MAYHR, + SYSTEMZ_INS_MAYL, + SYSTEMZ_INS_MAYLR, + SYSTEMZ_INS_MAYR, + SYSTEMZ_INS_MC, + SYSTEMZ_INS_MD, + SYSTEMZ_INS_MDB, + SYSTEMZ_INS_MDBR, + SYSTEMZ_INS_MDE, + SYSTEMZ_INS_MDEB, + SYSTEMZ_INS_MDEBR, + SYSTEMZ_INS_MDER, + SYSTEMZ_INS_MDR, + SYSTEMZ_INS_MDTR, + SYSTEMZ_INS_MDTRA, + SYSTEMZ_INS_ME, + SYSTEMZ_INS_MEE, + SYSTEMZ_INS_MEEB, + SYSTEMZ_INS_MEEBR, + SYSTEMZ_INS_MEER, + SYSTEMZ_INS_MER, + SYSTEMZ_INS_MFY, + SYSTEMZ_INS_MG, + SYSTEMZ_INS_MGH, + SYSTEMZ_INS_MGHI, + SYSTEMZ_INS_MGRK, + SYSTEMZ_INS_MH, + SYSTEMZ_INS_MHI, + SYSTEMZ_INS_MHY, + SYSTEMZ_INS_ML, + SYSTEMZ_INS_MLG, + SYSTEMZ_INS_MLGR, + SYSTEMZ_INS_MLR, + SYSTEMZ_INS_MP, + SYSTEMZ_INS_MR, + SYSTEMZ_INS_MS, + SYSTEMZ_INS_MSC, + SYSTEMZ_INS_MSCH, + SYSTEMZ_INS_MSD, + SYSTEMZ_INS_MSDB, + SYSTEMZ_INS_MSDBR, + SYSTEMZ_INS_MSDR, + SYSTEMZ_INS_MSE, + SYSTEMZ_INS_MSEB, + SYSTEMZ_INS_MSEBR, + SYSTEMZ_INS_MSER, + SYSTEMZ_INS_MSFI, + SYSTEMZ_INS_MSG, + SYSTEMZ_INS_MSGC, + SYSTEMZ_INS_MSGF, + SYSTEMZ_INS_MSGFI, + SYSTEMZ_INS_MSGFR, + SYSTEMZ_INS_MSGR, + SYSTEMZ_INS_MSGRKC, + SYSTEMZ_INS_MSR, + SYSTEMZ_INS_MSRKC, + SYSTEMZ_INS_MSTA, + SYSTEMZ_INS_MSY, + SYSTEMZ_INS_MVC, + SYSTEMZ_INS_MVCDK, + SYSTEMZ_INS_MVCIN, + SYSTEMZ_INS_MVCK, + SYSTEMZ_INS_MVCL, + SYSTEMZ_INS_MVCLE, + SYSTEMZ_INS_MVCLU, + SYSTEMZ_INS_MVCOS, + SYSTEMZ_INS_MVCP, + SYSTEMZ_INS_MVCRL, + SYSTEMZ_INS_MVCS, + SYSTEMZ_INS_MVCSK, + SYSTEMZ_INS_MVGHI, + SYSTEMZ_INS_MVHHI, + SYSTEMZ_INS_MVHI, + SYSTEMZ_INS_MVI, + SYSTEMZ_INS_MVIY, + SYSTEMZ_INS_MVN, + SYSTEMZ_INS_MVO, + SYSTEMZ_INS_MVPG, + SYSTEMZ_INS_MVST, + SYSTEMZ_INS_MVZ, + SYSTEMZ_INS_MXBR, + SYSTEMZ_INS_MXD, + SYSTEMZ_INS_MXDB, + SYSTEMZ_INS_MXDBR, + SYSTEMZ_INS_MXDR, + SYSTEMZ_INS_MXR, + SYSTEMZ_INS_MXTR, + SYSTEMZ_INS_MXTRA, + SYSTEMZ_INS_MY, + SYSTEMZ_INS_MYH, + SYSTEMZ_INS_MYHR, + SYSTEMZ_INS_MYL, + SYSTEMZ_INS_MYLR, + SYSTEMZ_INS_MYR, + SYSTEMZ_INS_N, + SYSTEMZ_INS_NC, + SYSTEMZ_INS_NCGRK, + SYSTEMZ_INS_NCRK, + SYSTEMZ_INS_NG, + SYSTEMZ_INS_NGR, + SYSTEMZ_INS_NGRK, + SYSTEMZ_INS_NI, + SYSTEMZ_INS_NIAI, + SYSTEMZ_INS_NIHF, + SYSTEMZ_INS_NIHH, + SYSTEMZ_INS_NIHL, + SYSTEMZ_INS_NILF, + SYSTEMZ_INS_NILH, + SYSTEMZ_INS_NILL, + SYSTEMZ_INS_NIY, + SYSTEMZ_INS_NNGRK, + SYSTEMZ_INS_NNPA, + SYSTEMZ_INS_NNRK, + SYSTEMZ_INS_NOGRK, + SYSTEMZ_INS_NOP, + SYSTEMZ_INS_NORK, + SYSTEMZ_INS_NR, + SYSTEMZ_INS_NRK, + SYSTEMZ_INS_NTSTG, + SYSTEMZ_INS_NXGRK, + SYSTEMZ_INS_NXRK, + SYSTEMZ_INS_NY, + SYSTEMZ_INS_O, + SYSTEMZ_INS_OC, + SYSTEMZ_INS_OCGRK, + SYSTEMZ_INS_OCRK, + SYSTEMZ_INS_OG, + SYSTEMZ_INS_OGR, + SYSTEMZ_INS_OGRK, + SYSTEMZ_INS_OI, + SYSTEMZ_INS_OIHF, + SYSTEMZ_INS_OIHH, + SYSTEMZ_INS_OIHL, + SYSTEMZ_INS_OILF, + SYSTEMZ_INS_OILH, + SYSTEMZ_INS_OILL, + SYSTEMZ_INS_OIY, + SYSTEMZ_INS_OR, + SYSTEMZ_INS_ORK, + SYSTEMZ_INS_OY, + SYSTEMZ_INS_PACK, + SYSTEMZ_INS_PALB, + SYSTEMZ_INS_PC, + SYSTEMZ_INS_PCC, + SYSTEMZ_INS_PCKMO, + SYSTEMZ_INS_PFD, + SYSTEMZ_INS_PFDRL, + SYSTEMZ_INS_PFMF, + SYSTEMZ_INS_PFPO, + SYSTEMZ_INS_PGIN, + SYSTEMZ_INS_PGOUT, + SYSTEMZ_INS_PKA, + SYSTEMZ_INS_PKU, + SYSTEMZ_INS_PLO, + SYSTEMZ_INS_POPCNT, + SYSTEMZ_INS_PPA, + SYSTEMZ_INS_PPNO, + SYSTEMZ_INS_PR, + SYSTEMZ_INS_PRNO, + SYSTEMZ_INS_PT, + SYSTEMZ_INS_PTF, + SYSTEMZ_INS_PTFF, + SYSTEMZ_INS_PTI, + SYSTEMZ_INS_PTLB, + SYSTEMZ_INS_QADTR, + SYSTEMZ_INS_QAXTR, + SYSTEMZ_INS_QCTRI, + SYSTEMZ_INS_QPACI, + SYSTEMZ_INS_QSI, + SYSTEMZ_INS_RCHP, + SYSTEMZ_INS_RDP, + SYSTEMZ_INS_RISBG, + SYSTEMZ_INS_RISBGN, + SYSTEMZ_INS_RISBHG, + SYSTEMZ_INS_RISBLG, + SYSTEMZ_INS_RLL, + SYSTEMZ_INS_RLLG, + SYSTEMZ_INS_RNSBG, + SYSTEMZ_INS_ROSBG, + SYSTEMZ_INS_RP, + SYSTEMZ_INS_RRBE, + SYSTEMZ_INS_RRBM, + SYSTEMZ_INS_RRDTR, + SYSTEMZ_INS_RRXTR, + SYSTEMZ_INS_RSCH, + SYSTEMZ_INS_RXSBG, + SYSTEMZ_INS_S, + SYSTEMZ_INS_SAC, + SYSTEMZ_INS_SACF, + SYSTEMZ_INS_SAL, + SYSTEMZ_INS_SAM24, + SYSTEMZ_INS_SAM31, + SYSTEMZ_INS_SAM64, + SYSTEMZ_INS_SAR, + SYSTEMZ_INS_SCCTR, + SYSTEMZ_INS_SCHM, + SYSTEMZ_INS_SCK, + SYSTEMZ_INS_SCKC, + SYSTEMZ_INS_SCKPF, + SYSTEMZ_INS_SD, + SYSTEMZ_INS_SDB, + SYSTEMZ_INS_SDBR, + SYSTEMZ_INS_SDR, + SYSTEMZ_INS_SDTR, + SYSTEMZ_INS_SDTRA, + SYSTEMZ_INS_SE, + SYSTEMZ_INS_SEB, + SYSTEMZ_INS_SEBR, + SYSTEMZ_INS_SELFHR, + SYSTEMZ_INS_SELFHRE, + SYSTEMZ_INS_SELFHRH, + SYSTEMZ_INS_SELFHRHE, + SYSTEMZ_INS_SELFHRL, + SYSTEMZ_INS_SELFHRLE, + SYSTEMZ_INS_SELFHRLH, + SYSTEMZ_INS_SELFHRM, + SYSTEMZ_INS_SELFHRNE, + SYSTEMZ_INS_SELFHRNH, + SYSTEMZ_INS_SELFHRNHE, + SYSTEMZ_INS_SELFHRNL, + SYSTEMZ_INS_SELFHRNLE, + SYSTEMZ_INS_SELFHRNLH, + SYSTEMZ_INS_SELFHRNM, + SYSTEMZ_INS_SELFHRNO, + SYSTEMZ_INS_SELFHRNP, + SYSTEMZ_INS_SELFHRNZ, + SYSTEMZ_INS_SELFHRO, + SYSTEMZ_INS_SELFHRP, + SYSTEMZ_INS_SELFHRZ, + SYSTEMZ_INS_SELGR, + SYSTEMZ_INS_SELGRE, + SYSTEMZ_INS_SELGRH, + SYSTEMZ_INS_SELGRHE, + SYSTEMZ_INS_SELGRL, + SYSTEMZ_INS_SELGRLE, + SYSTEMZ_INS_SELGRLH, + SYSTEMZ_INS_SELGRM, + SYSTEMZ_INS_SELGRNE, + SYSTEMZ_INS_SELGRNH, + SYSTEMZ_INS_SELGRNHE, + SYSTEMZ_INS_SELGRNL, + SYSTEMZ_INS_SELGRNLE, + SYSTEMZ_INS_SELGRNLH, + SYSTEMZ_INS_SELGRNM, + SYSTEMZ_INS_SELGRNO, + SYSTEMZ_INS_SELGRNP, + SYSTEMZ_INS_SELGRNZ, + SYSTEMZ_INS_SELGRO, + SYSTEMZ_INS_SELGRP, + SYSTEMZ_INS_SELGRZ, + SYSTEMZ_INS_SELR, + SYSTEMZ_INS_SELRE, + SYSTEMZ_INS_SELRH, + SYSTEMZ_INS_SELRHE, + SYSTEMZ_INS_SELRL, + SYSTEMZ_INS_SELRLE, + SYSTEMZ_INS_SELRLH, + SYSTEMZ_INS_SELRM, + SYSTEMZ_INS_SELRNE, + SYSTEMZ_INS_SELRNH, + SYSTEMZ_INS_SELRNHE, + SYSTEMZ_INS_SELRNL, + SYSTEMZ_INS_SELRNLE, + SYSTEMZ_INS_SELRNLH, + SYSTEMZ_INS_SELRNM, + SYSTEMZ_INS_SELRNO, + SYSTEMZ_INS_SELRNP, + SYSTEMZ_INS_SELRNZ, + SYSTEMZ_INS_SELRO, + SYSTEMZ_INS_SELRP, + SYSTEMZ_INS_SELRZ, + SYSTEMZ_INS_SER, + SYSTEMZ_INS_SFASR, + SYSTEMZ_INS_SFPC, + SYSTEMZ_INS_SG, + SYSTEMZ_INS_SGF, + SYSTEMZ_INS_SGFR, + SYSTEMZ_INS_SGH, + SYSTEMZ_INS_SGR, + SYSTEMZ_INS_SGRK, + SYSTEMZ_INS_SH, + SYSTEMZ_INS_SHHHR, + SYSTEMZ_INS_SHHLR, + SYSTEMZ_INS_SHY, + SYSTEMZ_INS_SIE, + SYSTEMZ_INS_SIGA, + SYSTEMZ_INS_SIGP, + SYSTEMZ_INS_SL, + SYSTEMZ_INS_SLA, + SYSTEMZ_INS_SLAG, + SYSTEMZ_INS_SLAK, + SYSTEMZ_INS_SLB, + SYSTEMZ_INS_SLBG, + SYSTEMZ_INS_SLBGR, + SYSTEMZ_INS_SLBR, + SYSTEMZ_INS_SLDA, + SYSTEMZ_INS_SLDL, + SYSTEMZ_INS_SLDT, + SYSTEMZ_INS_SLFI, + SYSTEMZ_INS_SLG, + SYSTEMZ_INS_SLGF, + SYSTEMZ_INS_SLGFI, + SYSTEMZ_INS_SLGFR, + SYSTEMZ_INS_SLGR, + SYSTEMZ_INS_SLGRK, + SYSTEMZ_INS_SLHHHR, + SYSTEMZ_INS_SLHHLR, + SYSTEMZ_INS_SLL, + SYSTEMZ_INS_SLLG, + SYSTEMZ_INS_SLLK, + SYSTEMZ_INS_SLR, + SYSTEMZ_INS_SLRK, + SYSTEMZ_INS_SLXT, + SYSTEMZ_INS_SLY, + SYSTEMZ_INS_SORTL, + SYSTEMZ_INS_SP, + SYSTEMZ_INS_SPCTR, + SYSTEMZ_INS_SPKA, + SYSTEMZ_INS_SPM, + SYSTEMZ_INS_SPT, + SYSTEMZ_INS_SPX, + SYSTEMZ_INS_SQD, + SYSTEMZ_INS_SQDB, + SYSTEMZ_INS_SQDBR, + SYSTEMZ_INS_SQDR, + SYSTEMZ_INS_SQE, + SYSTEMZ_INS_SQEB, + SYSTEMZ_INS_SQEBR, + SYSTEMZ_INS_SQER, + SYSTEMZ_INS_SQXBR, + SYSTEMZ_INS_SQXR, + SYSTEMZ_INS_SR, + SYSTEMZ_INS_SRA, + SYSTEMZ_INS_SRAG, + SYSTEMZ_INS_SRAK, + SYSTEMZ_INS_SRDA, + SYSTEMZ_INS_SRDL, + SYSTEMZ_INS_SRDT, + SYSTEMZ_INS_SRK, + SYSTEMZ_INS_SRL, + SYSTEMZ_INS_SRLG, + SYSTEMZ_INS_SRLK, + SYSTEMZ_INS_SRNM, + SYSTEMZ_INS_SRNMB, + SYSTEMZ_INS_SRNMT, + SYSTEMZ_INS_SRP, + SYSTEMZ_INS_SRST, + SYSTEMZ_INS_SRSTU, + SYSTEMZ_INS_SRXT, + SYSTEMZ_INS_SSAIR, + SYSTEMZ_INS_SSAR, + SYSTEMZ_INS_SSCH, + SYSTEMZ_INS_SSKE, + SYSTEMZ_INS_SSM, + SYSTEMZ_INS_ST, + SYSTEMZ_INS_STAM, + SYSTEMZ_INS_STAMY, + SYSTEMZ_INS_STAP, + SYSTEMZ_INS_STBEAR, + SYSTEMZ_INS_STC, + SYSTEMZ_INS_STCH, + SYSTEMZ_INS_STCK, + SYSTEMZ_INS_STCKC, + SYSTEMZ_INS_STCKE, + SYSTEMZ_INS_STCKF, + SYSTEMZ_INS_STCM, + SYSTEMZ_INS_STCMH, + SYSTEMZ_INS_STCMY, + SYSTEMZ_INS_STCPS, + SYSTEMZ_INS_STCRW, + SYSTEMZ_INS_STCTG, + SYSTEMZ_INS_STCTL, + SYSTEMZ_INS_STCY, + SYSTEMZ_INS_STD, + SYSTEMZ_INS_STDY, + SYSTEMZ_INS_STE, + SYSTEMZ_INS_STEY, + SYSTEMZ_INS_STFH, + SYSTEMZ_INS_STFL, + SYSTEMZ_INS_STFLE, + SYSTEMZ_INS_STFPC, + SYSTEMZ_INS_STG, + SYSTEMZ_INS_STGRL, + SYSTEMZ_INS_STGSC, + SYSTEMZ_INS_STH, + SYSTEMZ_INS_STHH, + SYSTEMZ_INS_STHRL, + SYSTEMZ_INS_STHY, + SYSTEMZ_INS_STIDP, + SYSTEMZ_INS_STM, + SYSTEMZ_INS_STMG, + SYSTEMZ_INS_STMH, + SYSTEMZ_INS_STMY, + SYSTEMZ_INS_STNSM, + SYSTEMZ_INS_STOC, + SYSTEMZ_INS_STOCE, + SYSTEMZ_INS_STOCH, + SYSTEMZ_INS_STOCHE, + SYSTEMZ_INS_STOCL, + SYSTEMZ_INS_STOCLE, + SYSTEMZ_INS_STOCLH, + SYSTEMZ_INS_STOCM, + SYSTEMZ_INS_STOCNE, + SYSTEMZ_INS_STOCNH, + SYSTEMZ_INS_STOCNHE, + SYSTEMZ_INS_STOCNL, + SYSTEMZ_INS_STOCNLE, + SYSTEMZ_INS_STOCNLH, + SYSTEMZ_INS_STOCNM, + SYSTEMZ_INS_STOCNO, + SYSTEMZ_INS_STOCNP, + SYSTEMZ_INS_STOCNZ, + SYSTEMZ_INS_STOCO, + SYSTEMZ_INS_STOCP, + SYSTEMZ_INS_STOCZ, + SYSTEMZ_INS_STOCFH, + SYSTEMZ_INS_STOCFHE, + SYSTEMZ_INS_STOCFHH, + SYSTEMZ_INS_STOCFHHE, + SYSTEMZ_INS_STOCFHL, + SYSTEMZ_INS_STOCFHLE, + SYSTEMZ_INS_STOCFHLH, + SYSTEMZ_INS_STOCFHM, + SYSTEMZ_INS_STOCFHNE, + SYSTEMZ_INS_STOCFHNH, + SYSTEMZ_INS_STOCFHNHE, + SYSTEMZ_INS_STOCFHNL, + SYSTEMZ_INS_STOCFHNLE, + SYSTEMZ_INS_STOCFHNLH, + SYSTEMZ_INS_STOCFHNM, + SYSTEMZ_INS_STOCFHNO, + SYSTEMZ_INS_STOCFHNP, + SYSTEMZ_INS_STOCFHNZ, + SYSTEMZ_INS_STOCFHO, + SYSTEMZ_INS_STOCFHP, + SYSTEMZ_INS_STOCFHZ, + SYSTEMZ_INS_STOCG, + SYSTEMZ_INS_STOCGE, + SYSTEMZ_INS_STOCGH, + SYSTEMZ_INS_STOCGHE, + SYSTEMZ_INS_STOCGL, + SYSTEMZ_INS_STOCGLE, + SYSTEMZ_INS_STOCGLH, + SYSTEMZ_INS_STOCGM, + SYSTEMZ_INS_STOCGNE, + SYSTEMZ_INS_STOCGNH, + SYSTEMZ_INS_STOCGNHE, + SYSTEMZ_INS_STOCGNL, + SYSTEMZ_INS_STOCGNLE, + SYSTEMZ_INS_STOCGNLH, + SYSTEMZ_INS_STOCGNM, + SYSTEMZ_INS_STOCGNO, + SYSTEMZ_INS_STOCGNP, + SYSTEMZ_INS_STOCGNZ, + SYSTEMZ_INS_STOCGO, + SYSTEMZ_INS_STOCGP, + SYSTEMZ_INS_STOCGZ, + SYSTEMZ_INS_STOSM, + SYSTEMZ_INS_STPQ, + SYSTEMZ_INS_STPT, + SYSTEMZ_INS_STPX, + SYSTEMZ_INS_STRAG, + SYSTEMZ_INS_STRL, + SYSTEMZ_INS_STRV, + SYSTEMZ_INS_STRVG, + SYSTEMZ_INS_STRVH, + SYSTEMZ_INS_STSCH, + SYSTEMZ_INS_STSI, + SYSTEMZ_INS_STURA, + SYSTEMZ_INS_STURG, + SYSTEMZ_INS_STY, + SYSTEMZ_INS_SU, + SYSTEMZ_INS_SUR, + SYSTEMZ_INS_SVC, + SYSTEMZ_INS_SW, + SYSTEMZ_INS_SWR, + SYSTEMZ_INS_SXBR, + SYSTEMZ_INS_SXR, + SYSTEMZ_INS_SXTR, + SYSTEMZ_INS_SXTRA, + SYSTEMZ_INS_SY, + SYSTEMZ_INS_TABORT, + SYSTEMZ_INS_TAM, + SYSTEMZ_INS_TAR, + SYSTEMZ_INS_TB, + SYSTEMZ_INS_TBDR, + SYSTEMZ_INS_TBEDR, + SYSTEMZ_INS_TBEGIN, + SYSTEMZ_INS_TBEGINC, + SYSTEMZ_INS_TCDB, + SYSTEMZ_INS_TCEB, + SYSTEMZ_INS_TCXB, + SYSTEMZ_INS_TDCDT, + SYSTEMZ_INS_TDCET, + SYSTEMZ_INS_TDCXT, + SYSTEMZ_INS_TDGDT, + SYSTEMZ_INS_TDGET, + SYSTEMZ_INS_TDGXT, + SYSTEMZ_INS_TEND, + SYSTEMZ_INS_THDER, + SYSTEMZ_INS_THDR, + SYSTEMZ_INS_TM, + SYSTEMZ_INS_TMHH, + SYSTEMZ_INS_TMHL, + SYSTEMZ_INS_TMLH, + SYSTEMZ_INS_TMLL, + SYSTEMZ_INS_TMY, + SYSTEMZ_INS_TP, + SYSTEMZ_INS_TPI, + SYSTEMZ_INS_TPROT, + SYSTEMZ_INS_TR, + SYSTEMZ_INS_TRACE, + SYSTEMZ_INS_TRACG, + SYSTEMZ_INS_TRAP2, + SYSTEMZ_INS_TRAP4, + SYSTEMZ_INS_TRE, + SYSTEMZ_INS_TROO, + SYSTEMZ_INS_TROT, + SYSTEMZ_INS_TRT, + SYSTEMZ_INS_TRTE, + SYSTEMZ_INS_TRTO, + SYSTEMZ_INS_TRTR, + SYSTEMZ_INS_TRTRE, + SYSTEMZ_INS_TRTT, + SYSTEMZ_INS_TS, + SYSTEMZ_INS_TSCH, + SYSTEMZ_INS_UNPK, + SYSTEMZ_INS_UNPKA, + SYSTEMZ_INS_UNPKU, + SYSTEMZ_INS_UPT, + SYSTEMZ_INS_VA, + SYSTEMZ_INS_VAB, + SYSTEMZ_INS_VAC, + SYSTEMZ_INS_VACC, + SYSTEMZ_INS_VACCB, + SYSTEMZ_INS_VACCC, + SYSTEMZ_INS_VACCCQ, + SYSTEMZ_INS_VACCF, + SYSTEMZ_INS_VACCG, + SYSTEMZ_INS_VACCH, + SYSTEMZ_INS_VACCQ, + SYSTEMZ_INS_VACQ, + SYSTEMZ_INS_VAF, + SYSTEMZ_INS_VAG, + SYSTEMZ_INS_VAH, + SYSTEMZ_INS_VAP, + SYSTEMZ_INS_VAQ, + SYSTEMZ_INS_VAVG, + SYSTEMZ_INS_VAVGB, + SYSTEMZ_INS_VAVGF, + SYSTEMZ_INS_VAVGG, + SYSTEMZ_INS_VAVGH, + SYSTEMZ_INS_VAVGL, + SYSTEMZ_INS_VAVGLB, + SYSTEMZ_INS_VAVGLF, + SYSTEMZ_INS_VAVGLG, + SYSTEMZ_INS_VAVGLH, + SYSTEMZ_INS_VBPERM, + SYSTEMZ_INS_VCDG, + SYSTEMZ_INS_VCDGB, + SYSTEMZ_INS_VCDLG, + SYSTEMZ_INS_VCDLGB, + SYSTEMZ_INS_VCEFB, + SYSTEMZ_INS_VCELFB, + SYSTEMZ_INS_VCEQ, + SYSTEMZ_INS_VCEQB, + SYSTEMZ_INS_VCEQBS, + SYSTEMZ_INS_VCEQF, + SYSTEMZ_INS_VCEQFS, + SYSTEMZ_INS_VCEQG, + SYSTEMZ_INS_VCEQGS, + SYSTEMZ_INS_VCEQH, + SYSTEMZ_INS_VCEQHS, + SYSTEMZ_INS_VCFEB, + SYSTEMZ_INS_VCFN, + SYSTEMZ_INS_VCFPL, + SYSTEMZ_INS_VCFPS, + SYSTEMZ_INS_VCGD, + SYSTEMZ_INS_VCGDB, + SYSTEMZ_INS_VCH, + SYSTEMZ_INS_VCHB, + SYSTEMZ_INS_VCHBS, + SYSTEMZ_INS_VCHF, + SYSTEMZ_INS_VCHFS, + SYSTEMZ_INS_VCHG, + SYSTEMZ_INS_VCHGS, + SYSTEMZ_INS_VCHH, + SYSTEMZ_INS_VCHHS, + SYSTEMZ_INS_VCHL, + SYSTEMZ_INS_VCHLB, + SYSTEMZ_INS_VCHLBS, + SYSTEMZ_INS_VCHLF, + SYSTEMZ_INS_VCHLFS, + SYSTEMZ_INS_VCHLG, + SYSTEMZ_INS_VCHLGS, + SYSTEMZ_INS_VCHLH, + SYSTEMZ_INS_VCHLHS, + SYSTEMZ_INS_VCKSM, + SYSTEMZ_INS_VCLFEB, + SYSTEMZ_INS_VCLFNH, + SYSTEMZ_INS_VCLFNL, + SYSTEMZ_INS_VCLFP, + SYSTEMZ_INS_VCLGD, + SYSTEMZ_INS_VCLGDB, + SYSTEMZ_INS_VCLZ, + SYSTEMZ_INS_VCLZB, + SYSTEMZ_INS_VCLZDP, + SYSTEMZ_INS_VCLZF, + SYSTEMZ_INS_VCLZG, + SYSTEMZ_INS_VCLZH, + SYSTEMZ_INS_VCNF, + SYSTEMZ_INS_VCP, + SYSTEMZ_INS_VCRNF, + SYSTEMZ_INS_VCSFP, + SYSTEMZ_INS_VCSPH, + SYSTEMZ_INS_VCTZ, + SYSTEMZ_INS_VCTZB, + SYSTEMZ_INS_VCTZF, + SYSTEMZ_INS_VCTZG, + SYSTEMZ_INS_VCTZH, + SYSTEMZ_INS_VCVB, + SYSTEMZ_INS_VCVBG, + SYSTEMZ_INS_VCVD, + SYSTEMZ_INS_VCVDG, + SYSTEMZ_INS_VDP, + SYSTEMZ_INS_VEC, + SYSTEMZ_INS_VECB, + SYSTEMZ_INS_VECF, + SYSTEMZ_INS_VECG, + SYSTEMZ_INS_VECH, + SYSTEMZ_INS_VECL, + SYSTEMZ_INS_VECLB, + SYSTEMZ_INS_VECLF, + SYSTEMZ_INS_VECLG, + SYSTEMZ_INS_VECLH, + SYSTEMZ_INS_VERIM, + SYSTEMZ_INS_VERIMB, + SYSTEMZ_INS_VERIMF, + SYSTEMZ_INS_VERIMG, + SYSTEMZ_INS_VERIMH, + SYSTEMZ_INS_VERLL, + SYSTEMZ_INS_VERLLB, + SYSTEMZ_INS_VERLLF, + SYSTEMZ_INS_VERLLG, + SYSTEMZ_INS_VERLLH, + SYSTEMZ_INS_VERLLV, + SYSTEMZ_INS_VERLLVB, + SYSTEMZ_INS_VERLLVF, + SYSTEMZ_INS_VERLLVG, + SYSTEMZ_INS_VERLLVH, + SYSTEMZ_INS_VESL, + SYSTEMZ_INS_VESLB, + SYSTEMZ_INS_VESLF, + SYSTEMZ_INS_VESLG, + SYSTEMZ_INS_VESLH, + SYSTEMZ_INS_VESLV, + SYSTEMZ_INS_VESLVB, + SYSTEMZ_INS_VESLVF, + SYSTEMZ_INS_VESLVG, + SYSTEMZ_INS_VESLVH, + SYSTEMZ_INS_VESRA, + SYSTEMZ_INS_VESRAB, + SYSTEMZ_INS_VESRAF, + SYSTEMZ_INS_VESRAG, + SYSTEMZ_INS_VESRAH, + SYSTEMZ_INS_VESRAV, + SYSTEMZ_INS_VESRAVB, + SYSTEMZ_INS_VESRAVF, + SYSTEMZ_INS_VESRAVG, + SYSTEMZ_INS_VESRAVH, + SYSTEMZ_INS_VESRL, + SYSTEMZ_INS_VESRLB, + SYSTEMZ_INS_VESRLF, + SYSTEMZ_INS_VESRLG, + SYSTEMZ_INS_VESRLH, + SYSTEMZ_INS_VESRLV, + SYSTEMZ_INS_VESRLVB, + SYSTEMZ_INS_VESRLVF, + SYSTEMZ_INS_VESRLVG, + SYSTEMZ_INS_VESRLVH, + SYSTEMZ_INS_VFA, + SYSTEMZ_INS_VFADB, + SYSTEMZ_INS_VFAE, + SYSTEMZ_INS_VFAEB, + SYSTEMZ_INS_VFAEBS, + SYSTEMZ_INS_VFAEF, + SYSTEMZ_INS_VFAEFS, + SYSTEMZ_INS_VFAEH, + SYSTEMZ_INS_VFAEHS, + SYSTEMZ_INS_VFAEZB, + SYSTEMZ_INS_VFAEZBS, + SYSTEMZ_INS_VFAEZF, + SYSTEMZ_INS_VFAEZFS, + SYSTEMZ_INS_VFAEZH, + SYSTEMZ_INS_VFAEZHS, + SYSTEMZ_INS_VFASB, + SYSTEMZ_INS_VFCE, + SYSTEMZ_INS_VFCEDB, + SYSTEMZ_INS_VFCEDBS, + SYSTEMZ_INS_VFCESB, + SYSTEMZ_INS_VFCESBS, + SYSTEMZ_INS_VFCH, + SYSTEMZ_INS_VFCHDB, + SYSTEMZ_INS_VFCHDBS, + SYSTEMZ_INS_VFCHE, + SYSTEMZ_INS_VFCHEDB, + SYSTEMZ_INS_VFCHEDBS, + SYSTEMZ_INS_VFCHESB, + SYSTEMZ_INS_VFCHESBS, + SYSTEMZ_INS_VFCHSB, + SYSTEMZ_INS_VFCHSBS, + SYSTEMZ_INS_VFD, + SYSTEMZ_INS_VFDDB, + SYSTEMZ_INS_VFDSB, + SYSTEMZ_INS_VFEE, + SYSTEMZ_INS_VFEEB, + SYSTEMZ_INS_VFEEBS, + SYSTEMZ_INS_VFEEF, + SYSTEMZ_INS_VFEEFS, + SYSTEMZ_INS_VFEEH, + SYSTEMZ_INS_VFEEHS, + SYSTEMZ_INS_VFEEZB, + SYSTEMZ_INS_VFEEZBS, + SYSTEMZ_INS_VFEEZF, + SYSTEMZ_INS_VFEEZFS, + SYSTEMZ_INS_VFEEZH, + SYSTEMZ_INS_VFEEZHS, + SYSTEMZ_INS_VFENE, + SYSTEMZ_INS_VFENEB, + SYSTEMZ_INS_VFENEBS, + SYSTEMZ_INS_VFENEF, + SYSTEMZ_INS_VFENEFS, + SYSTEMZ_INS_VFENEH, + SYSTEMZ_INS_VFENEHS, + SYSTEMZ_INS_VFENEZB, + SYSTEMZ_INS_VFENEZBS, + SYSTEMZ_INS_VFENEZF, + SYSTEMZ_INS_VFENEZFS, + SYSTEMZ_INS_VFENEZH, + SYSTEMZ_INS_VFENEZHS, + SYSTEMZ_INS_VFI, + SYSTEMZ_INS_VFIDB, + SYSTEMZ_INS_VFISB, + SYSTEMZ_INS_VFKEDB, + SYSTEMZ_INS_VFKEDBS, + SYSTEMZ_INS_VFKESB, + SYSTEMZ_INS_VFKESBS, + SYSTEMZ_INS_VFKHDB, + SYSTEMZ_INS_VFKHDBS, + SYSTEMZ_INS_VFKHEDB, + SYSTEMZ_INS_VFKHEDBS, + SYSTEMZ_INS_VFKHESB, + SYSTEMZ_INS_VFKHESBS, + SYSTEMZ_INS_VFKHSB, + SYSTEMZ_INS_VFKHSBS, + SYSTEMZ_INS_VFLCDB, + SYSTEMZ_INS_VFLCSB, + SYSTEMZ_INS_VFLL, + SYSTEMZ_INS_VFLLS, + SYSTEMZ_INS_VFLNDB, + SYSTEMZ_INS_VFLNSB, + SYSTEMZ_INS_VFLPDB, + SYSTEMZ_INS_VFLPSB, + SYSTEMZ_INS_VFLR, + SYSTEMZ_INS_VFLRD, + SYSTEMZ_INS_VFM, + SYSTEMZ_INS_VFMA, + SYSTEMZ_INS_VFMADB, + SYSTEMZ_INS_VFMASB, + SYSTEMZ_INS_VFMAX, + SYSTEMZ_INS_VFMAXDB, + SYSTEMZ_INS_VFMAXSB, + SYSTEMZ_INS_VFMDB, + SYSTEMZ_INS_VFMIN, + SYSTEMZ_INS_VFMINDB, + SYSTEMZ_INS_VFMINSB, + SYSTEMZ_INS_VFMS, + SYSTEMZ_INS_VFMSB, + SYSTEMZ_INS_VFMSDB, + SYSTEMZ_INS_VFMSSB, + SYSTEMZ_INS_VFNMA, + SYSTEMZ_INS_VFNMADB, + SYSTEMZ_INS_VFNMASB, + SYSTEMZ_INS_VFNMS, + SYSTEMZ_INS_VFNMSDB, + SYSTEMZ_INS_VFNMSSB, + SYSTEMZ_INS_VFPSO, + SYSTEMZ_INS_VFPSODB, + SYSTEMZ_INS_VFPSOSB, + SYSTEMZ_INS_VFS, + SYSTEMZ_INS_VFSDB, + SYSTEMZ_INS_VFSQ, + SYSTEMZ_INS_VFSQDB, + SYSTEMZ_INS_VFSQSB, + SYSTEMZ_INS_VFSSB, + SYSTEMZ_INS_VFTCI, + SYSTEMZ_INS_VFTCIDB, + SYSTEMZ_INS_VFTCISB, + SYSTEMZ_INS_VGBM, + SYSTEMZ_INS_VGEF, + SYSTEMZ_INS_VGEG, + SYSTEMZ_INS_VGFM, + SYSTEMZ_INS_VGFMA, + SYSTEMZ_INS_VGFMAB, + SYSTEMZ_INS_VGFMAF, + SYSTEMZ_INS_VGFMAG, + SYSTEMZ_INS_VGFMAH, + SYSTEMZ_INS_VGFMB, + SYSTEMZ_INS_VGFMF, + SYSTEMZ_INS_VGFMG, + SYSTEMZ_INS_VGFMH, + SYSTEMZ_INS_VGM, + SYSTEMZ_INS_VGMB, + SYSTEMZ_INS_VGMF, + SYSTEMZ_INS_VGMG, + SYSTEMZ_INS_VGMH, + SYSTEMZ_INS_VISTR, + SYSTEMZ_INS_VISTRB, + SYSTEMZ_INS_VISTRBS, + SYSTEMZ_INS_VISTRF, + SYSTEMZ_INS_VISTRFS, + SYSTEMZ_INS_VISTRH, + SYSTEMZ_INS_VISTRHS, + SYSTEMZ_INS_VL, + SYSTEMZ_INS_VLBB, + SYSTEMZ_INS_VLBR, + SYSTEMZ_INS_VLBRF, + SYSTEMZ_INS_VLBRG, + SYSTEMZ_INS_VLBRH, + SYSTEMZ_INS_VLBRQ, + SYSTEMZ_INS_VLBRREP, + SYSTEMZ_INS_VLBRREPF, + SYSTEMZ_INS_VLBRREPG, + SYSTEMZ_INS_VLBRREPH, + SYSTEMZ_INS_VLC, + SYSTEMZ_INS_VLCB, + SYSTEMZ_INS_VLCF, + SYSTEMZ_INS_VLCG, + SYSTEMZ_INS_VLCH, + SYSTEMZ_INS_VLDE, + SYSTEMZ_INS_VLDEB, + SYSTEMZ_INS_VLEB, + SYSTEMZ_INS_VLEBRF, + SYSTEMZ_INS_VLEBRG, + SYSTEMZ_INS_VLEBRH, + SYSTEMZ_INS_VLED, + SYSTEMZ_INS_VLEDB, + SYSTEMZ_INS_VLEF, + SYSTEMZ_INS_VLEG, + SYSTEMZ_INS_VLEH, + SYSTEMZ_INS_VLEIB, + SYSTEMZ_INS_VLEIF, + SYSTEMZ_INS_VLEIG, + SYSTEMZ_INS_VLEIH, + SYSTEMZ_INS_VLER, + SYSTEMZ_INS_VLERF, + SYSTEMZ_INS_VLERG, + SYSTEMZ_INS_VLERH, + SYSTEMZ_INS_VLGV, + SYSTEMZ_INS_VLGVB, + SYSTEMZ_INS_VLGVF, + SYSTEMZ_INS_VLGVG, + SYSTEMZ_INS_VLGVH, + SYSTEMZ_INS_VLIP, + SYSTEMZ_INS_VLL, + SYSTEMZ_INS_VLLEBRZ, + SYSTEMZ_INS_VLLEBRZE, + SYSTEMZ_INS_VLLEBRZF, + SYSTEMZ_INS_VLLEBRZG, + SYSTEMZ_INS_VLLEBRZH, + SYSTEMZ_INS_VLLEZ, + SYSTEMZ_INS_VLLEZB, + SYSTEMZ_INS_VLLEZF, + SYSTEMZ_INS_VLLEZG, + SYSTEMZ_INS_VLLEZH, + SYSTEMZ_INS_VLLEZLF, + SYSTEMZ_INS_VLM, + SYSTEMZ_INS_VLP, + SYSTEMZ_INS_VLPB, + SYSTEMZ_INS_VLPF, + SYSTEMZ_INS_VLPG, + SYSTEMZ_INS_VLPH, + SYSTEMZ_INS_VLR, + SYSTEMZ_INS_VLREP, + SYSTEMZ_INS_VLREPB, + SYSTEMZ_INS_VLREPF, + SYSTEMZ_INS_VLREPG, + SYSTEMZ_INS_VLREPH, + SYSTEMZ_INS_VLRL, + SYSTEMZ_INS_VLRLR, + SYSTEMZ_INS_VLVG, + SYSTEMZ_INS_VLVGB, + SYSTEMZ_INS_VLVGF, + SYSTEMZ_INS_VLVGG, + SYSTEMZ_INS_VLVGH, + SYSTEMZ_INS_VLVGP, + SYSTEMZ_INS_VMAE, + SYSTEMZ_INS_VMAEB, + SYSTEMZ_INS_VMAEF, + SYSTEMZ_INS_VMAEH, + SYSTEMZ_INS_VMAH, + SYSTEMZ_INS_VMAHB, + SYSTEMZ_INS_VMAHF, + SYSTEMZ_INS_VMAHH, + SYSTEMZ_INS_VMAL, + SYSTEMZ_INS_VMALB, + SYSTEMZ_INS_VMALE, + SYSTEMZ_INS_VMALEB, + SYSTEMZ_INS_VMALEF, + SYSTEMZ_INS_VMALEH, + SYSTEMZ_INS_VMALF, + SYSTEMZ_INS_VMALH, + SYSTEMZ_INS_VMALHB, + SYSTEMZ_INS_VMALHF, + SYSTEMZ_INS_VMALHH, + SYSTEMZ_INS_VMALHW, + SYSTEMZ_INS_VMALO, + SYSTEMZ_INS_VMALOB, + SYSTEMZ_INS_VMALOF, + SYSTEMZ_INS_VMALOH, + SYSTEMZ_INS_VMAO, + SYSTEMZ_INS_VMAOB, + SYSTEMZ_INS_VMAOF, + SYSTEMZ_INS_VMAOH, + SYSTEMZ_INS_VME, + SYSTEMZ_INS_VMEB, + SYSTEMZ_INS_VMEF, + SYSTEMZ_INS_VMEH, + SYSTEMZ_INS_VMH, + SYSTEMZ_INS_VMHB, + SYSTEMZ_INS_VMHF, + SYSTEMZ_INS_VMHH, + SYSTEMZ_INS_VML, + SYSTEMZ_INS_VMLB, + SYSTEMZ_INS_VMLE, + SYSTEMZ_INS_VMLEB, + SYSTEMZ_INS_VMLEF, + SYSTEMZ_INS_VMLEH, + SYSTEMZ_INS_VMLF, + SYSTEMZ_INS_VMLH, + SYSTEMZ_INS_VMLHB, + SYSTEMZ_INS_VMLHF, + SYSTEMZ_INS_VMLHH, + SYSTEMZ_INS_VMLHW, + SYSTEMZ_INS_VMLO, + SYSTEMZ_INS_VMLOB, + SYSTEMZ_INS_VMLOF, + SYSTEMZ_INS_VMLOH, + SYSTEMZ_INS_VMN, + SYSTEMZ_INS_VMNB, + SYSTEMZ_INS_VMNF, + SYSTEMZ_INS_VMNG, + SYSTEMZ_INS_VMNH, + SYSTEMZ_INS_VMNL, + SYSTEMZ_INS_VMNLB, + SYSTEMZ_INS_VMNLF, + SYSTEMZ_INS_VMNLG, + SYSTEMZ_INS_VMNLH, + SYSTEMZ_INS_VMO, + SYSTEMZ_INS_VMOB, + SYSTEMZ_INS_VMOF, + SYSTEMZ_INS_VMOH, + SYSTEMZ_INS_VMP, + SYSTEMZ_INS_VMRH, + SYSTEMZ_INS_VMRHB, + SYSTEMZ_INS_VMRHF, + SYSTEMZ_INS_VMRHG, + SYSTEMZ_INS_VMRHH, + SYSTEMZ_INS_VMRL, + SYSTEMZ_INS_VMRLB, + SYSTEMZ_INS_VMRLF, + SYSTEMZ_INS_VMRLG, + SYSTEMZ_INS_VMRLH, + SYSTEMZ_INS_VMSL, + SYSTEMZ_INS_VMSLG, + SYSTEMZ_INS_VMSP, + SYSTEMZ_INS_VMX, + SYSTEMZ_INS_VMXB, + SYSTEMZ_INS_VMXF, + SYSTEMZ_INS_VMXG, + SYSTEMZ_INS_VMXH, + SYSTEMZ_INS_VMXL, + SYSTEMZ_INS_VMXLB, + SYSTEMZ_INS_VMXLF, + SYSTEMZ_INS_VMXLG, + SYSTEMZ_INS_VMXLH, + SYSTEMZ_INS_VN, + SYSTEMZ_INS_VNC, + SYSTEMZ_INS_VNN, + SYSTEMZ_INS_VNO, + SYSTEMZ_INS_VNX, + SYSTEMZ_INS_VO, + SYSTEMZ_INS_VOC, + SYSTEMZ_INS_VONE, + SYSTEMZ_INS_VPDI, + SYSTEMZ_INS_VPERM, + SYSTEMZ_INS_VPK, + SYSTEMZ_INS_VPKF, + SYSTEMZ_INS_VPKG, + SYSTEMZ_INS_VPKH, + SYSTEMZ_INS_VPKLS, + SYSTEMZ_INS_VPKLSF, + SYSTEMZ_INS_VPKLSFS, + SYSTEMZ_INS_VPKLSG, + SYSTEMZ_INS_VPKLSGS, + SYSTEMZ_INS_VPKLSH, + SYSTEMZ_INS_VPKLSHS, + SYSTEMZ_INS_VPKS, + SYSTEMZ_INS_VPKSF, + SYSTEMZ_INS_VPKSFS, + SYSTEMZ_INS_VPKSG, + SYSTEMZ_INS_VPKSGS, + SYSTEMZ_INS_VPKSH, + SYSTEMZ_INS_VPKSHS, + SYSTEMZ_INS_VPKZ, + SYSTEMZ_INS_VPKZR, + SYSTEMZ_INS_VPOPCT, + SYSTEMZ_INS_VPOPCTB, + SYSTEMZ_INS_VPOPCTF, + SYSTEMZ_INS_VPOPCTG, + SYSTEMZ_INS_VPOPCTH, + SYSTEMZ_INS_VPSOP, + SYSTEMZ_INS_VREP, + SYSTEMZ_INS_VREPB, + SYSTEMZ_INS_VREPF, + SYSTEMZ_INS_VREPG, + SYSTEMZ_INS_VREPH, + SYSTEMZ_INS_VREPI, + SYSTEMZ_INS_VREPIB, + SYSTEMZ_INS_VREPIF, + SYSTEMZ_INS_VREPIG, + SYSTEMZ_INS_VREPIH, + SYSTEMZ_INS_VRP, + SYSTEMZ_INS_VS, + SYSTEMZ_INS_VSB, + SYSTEMZ_INS_VSBCBI, + SYSTEMZ_INS_VSBCBIQ, + SYSTEMZ_INS_VSBI, + SYSTEMZ_INS_VSBIQ, + SYSTEMZ_INS_VSCBI, + SYSTEMZ_INS_VSCBIB, + SYSTEMZ_INS_VSCBIF, + SYSTEMZ_INS_VSCBIG, + SYSTEMZ_INS_VSCBIH, + SYSTEMZ_INS_VSCBIQ, + SYSTEMZ_INS_VSCEF, + SYSTEMZ_INS_VSCEG, + SYSTEMZ_INS_VSCHDP, + SYSTEMZ_INS_VSCHP, + SYSTEMZ_INS_VSCHSP, + SYSTEMZ_INS_VSCHXP, + SYSTEMZ_INS_VSCSHP, + SYSTEMZ_INS_VSDP, + SYSTEMZ_INS_VSEG, + SYSTEMZ_INS_VSEGB, + SYSTEMZ_INS_VSEGF, + SYSTEMZ_INS_VSEGH, + SYSTEMZ_INS_VSEL, + SYSTEMZ_INS_VSF, + SYSTEMZ_INS_VSG, + SYSTEMZ_INS_VSH, + SYSTEMZ_INS_VSL, + SYSTEMZ_INS_VSLB, + SYSTEMZ_INS_VSLD, + SYSTEMZ_INS_VSLDB, + SYSTEMZ_INS_VSP, + SYSTEMZ_INS_VSQ, + SYSTEMZ_INS_VSRA, + SYSTEMZ_INS_VSRAB, + SYSTEMZ_INS_VSRD, + SYSTEMZ_INS_VSRL, + SYSTEMZ_INS_VSRLB, + SYSTEMZ_INS_VSRP, + SYSTEMZ_INS_VSRPR, + SYSTEMZ_INS_VST, + SYSTEMZ_INS_VSTBR, + SYSTEMZ_INS_VSTBRF, + SYSTEMZ_INS_VSTBRG, + SYSTEMZ_INS_VSTBRH, + SYSTEMZ_INS_VSTBRQ, + SYSTEMZ_INS_VSTEB, + SYSTEMZ_INS_VSTEBRF, + SYSTEMZ_INS_VSTEBRG, + SYSTEMZ_INS_VSTEBRH, + SYSTEMZ_INS_VSTEF, + SYSTEMZ_INS_VSTEG, + SYSTEMZ_INS_VSTEH, + SYSTEMZ_INS_VSTER, + SYSTEMZ_INS_VSTERF, + SYSTEMZ_INS_VSTERG, + SYSTEMZ_INS_VSTERH, + SYSTEMZ_INS_VSTL, + SYSTEMZ_INS_VSTM, + SYSTEMZ_INS_VSTRC, + SYSTEMZ_INS_VSTRCB, + SYSTEMZ_INS_VSTRCBS, + SYSTEMZ_INS_VSTRCF, + SYSTEMZ_INS_VSTRCFS, + SYSTEMZ_INS_VSTRCH, + SYSTEMZ_INS_VSTRCHS, + SYSTEMZ_INS_VSTRCZB, + SYSTEMZ_INS_VSTRCZBS, + SYSTEMZ_INS_VSTRCZF, + SYSTEMZ_INS_VSTRCZFS, + SYSTEMZ_INS_VSTRCZH, + SYSTEMZ_INS_VSTRCZHS, + SYSTEMZ_INS_VSTRL, + SYSTEMZ_INS_VSTRLR, + SYSTEMZ_INS_VSTRS, + SYSTEMZ_INS_VSTRSB, + SYSTEMZ_INS_VSTRSF, + SYSTEMZ_INS_VSTRSH, + SYSTEMZ_INS_VSTRSZB, + SYSTEMZ_INS_VSTRSZF, + SYSTEMZ_INS_VSTRSZH, + SYSTEMZ_INS_VSUM, + SYSTEMZ_INS_VSUMB, + SYSTEMZ_INS_VSUMG, + SYSTEMZ_INS_VSUMGF, + SYSTEMZ_INS_VSUMGH, + SYSTEMZ_INS_VSUMH, + SYSTEMZ_INS_VSUMQ, + SYSTEMZ_INS_VSUMQF, + SYSTEMZ_INS_VSUMQG, + SYSTEMZ_INS_VTM, + SYSTEMZ_INS_VTP, + SYSTEMZ_INS_VUPH, + SYSTEMZ_INS_VUPHB, + SYSTEMZ_INS_VUPHF, + SYSTEMZ_INS_VUPHH, + SYSTEMZ_INS_VUPKZ, + SYSTEMZ_INS_VUPKZH, + SYSTEMZ_INS_VUPKZL, + SYSTEMZ_INS_VUPL, + SYSTEMZ_INS_VUPLB, + SYSTEMZ_INS_VUPLF, + SYSTEMZ_INS_VUPLH, + SYSTEMZ_INS_VUPLHB, + SYSTEMZ_INS_VUPLHF, + SYSTEMZ_INS_VUPLHH, + SYSTEMZ_INS_VUPLHW, + SYSTEMZ_INS_VUPLL, + SYSTEMZ_INS_VUPLLB, + SYSTEMZ_INS_VUPLLF, + SYSTEMZ_INS_VUPLLH, + SYSTEMZ_INS_VX, + SYSTEMZ_INS_VZERO, + SYSTEMZ_INS_WCDGB, + SYSTEMZ_INS_WCDLGB, + SYSTEMZ_INS_WCEFB, + SYSTEMZ_INS_WCELFB, + SYSTEMZ_INS_WCFEB, + SYSTEMZ_INS_WCGDB, + SYSTEMZ_INS_WCLFEB, + SYSTEMZ_INS_WCLGDB, + SYSTEMZ_INS_WFADB, + SYSTEMZ_INS_WFASB, + SYSTEMZ_INS_WFAXB, + SYSTEMZ_INS_WFC, + SYSTEMZ_INS_WFCDB, + SYSTEMZ_INS_WFCEDB, + SYSTEMZ_INS_WFCEDBS, + SYSTEMZ_INS_WFCESB, + SYSTEMZ_INS_WFCESBS, + SYSTEMZ_INS_WFCEXB, + SYSTEMZ_INS_WFCEXBS, + SYSTEMZ_INS_WFCHDB, + SYSTEMZ_INS_WFCHDBS, + SYSTEMZ_INS_WFCHEDB, + SYSTEMZ_INS_WFCHEDBS, + SYSTEMZ_INS_WFCHESB, + SYSTEMZ_INS_WFCHESBS, + SYSTEMZ_INS_WFCHEXB, + SYSTEMZ_INS_WFCHEXBS, + SYSTEMZ_INS_WFCHSB, + SYSTEMZ_INS_WFCHSBS, + SYSTEMZ_INS_WFCHXB, + SYSTEMZ_INS_WFCHXBS, + SYSTEMZ_INS_WFCSB, + SYSTEMZ_INS_WFCXB, + SYSTEMZ_INS_WFDDB, + SYSTEMZ_INS_WFDSB, + SYSTEMZ_INS_WFDXB, + SYSTEMZ_INS_WFIDB, + SYSTEMZ_INS_WFISB, + SYSTEMZ_INS_WFIXB, + SYSTEMZ_INS_WFK, + SYSTEMZ_INS_WFKDB, + SYSTEMZ_INS_WFKEDB, + SYSTEMZ_INS_WFKEDBS, + SYSTEMZ_INS_WFKESB, + SYSTEMZ_INS_WFKESBS, + SYSTEMZ_INS_WFKEXB, + SYSTEMZ_INS_WFKEXBS, + SYSTEMZ_INS_WFKHDB, + SYSTEMZ_INS_WFKHDBS, + SYSTEMZ_INS_WFKHEDB, + SYSTEMZ_INS_WFKHEDBS, + SYSTEMZ_INS_WFKHESB, + SYSTEMZ_INS_WFKHESBS, + SYSTEMZ_INS_WFKHEXB, + SYSTEMZ_INS_WFKHEXBS, + SYSTEMZ_INS_WFKHSB, + SYSTEMZ_INS_WFKHSBS, + SYSTEMZ_INS_WFKHXB, + SYSTEMZ_INS_WFKHXBS, + SYSTEMZ_INS_WFKSB, + SYSTEMZ_INS_WFKXB, + SYSTEMZ_INS_WFLCDB, + SYSTEMZ_INS_WFLCSB, + SYSTEMZ_INS_WFLCXB, + SYSTEMZ_INS_WFLLD, + SYSTEMZ_INS_WFLLS, + SYSTEMZ_INS_WFLNDB, + SYSTEMZ_INS_WFLNSB, + SYSTEMZ_INS_WFLNXB, + SYSTEMZ_INS_WFLPDB, + SYSTEMZ_INS_WFLPSB, + SYSTEMZ_INS_WFLPXB, + SYSTEMZ_INS_WFLRD, + SYSTEMZ_INS_WFLRX, + SYSTEMZ_INS_WFMADB, + SYSTEMZ_INS_WFMASB, + SYSTEMZ_INS_WFMAXB, + SYSTEMZ_INS_WFMAXDB, + SYSTEMZ_INS_WFMAXSB, + SYSTEMZ_INS_WFMAXXB, + SYSTEMZ_INS_WFMDB, + SYSTEMZ_INS_WFMINDB, + SYSTEMZ_INS_WFMINSB, + SYSTEMZ_INS_WFMINXB, + SYSTEMZ_INS_WFMSB, + SYSTEMZ_INS_WFMSDB, + SYSTEMZ_INS_WFMSSB, + SYSTEMZ_INS_WFMSXB, + SYSTEMZ_INS_WFMXB, + SYSTEMZ_INS_WFNMADB, + SYSTEMZ_INS_WFNMASB, + SYSTEMZ_INS_WFNMAXB, + SYSTEMZ_INS_WFNMSDB, + SYSTEMZ_INS_WFNMSSB, + SYSTEMZ_INS_WFNMSXB, + SYSTEMZ_INS_WFPSODB, + SYSTEMZ_INS_WFPSOSB, + SYSTEMZ_INS_WFPSOXB, + SYSTEMZ_INS_WFSDB, + SYSTEMZ_INS_WFSQDB, + SYSTEMZ_INS_WFSQSB, + SYSTEMZ_INS_WFSQXB, + SYSTEMZ_INS_WFSSB, + SYSTEMZ_INS_WFSXB, + SYSTEMZ_INS_WFTCIDB, + SYSTEMZ_INS_WFTCISB, + SYSTEMZ_INS_WFTCIXB, + SYSTEMZ_INS_WLDEB, + SYSTEMZ_INS_WLEDB, + SYSTEMZ_INS_X, + SYSTEMZ_INS_XC, + SYSTEMZ_INS_XG, + SYSTEMZ_INS_XGR, + SYSTEMZ_INS_XGRK, + SYSTEMZ_INS_XI, + SYSTEMZ_INS_XIHF, + SYSTEMZ_INS_XILF, + SYSTEMZ_INS_XIY, + SYSTEMZ_INS_XR, + SYSTEMZ_INS_XRK, + SYSTEMZ_INS_XSCH, + SYSTEMZ_INS_XY, + SYSTEMZ_INS_ZAP, - SYSZ_INS_ENDING, // <-- mark the end of the list of instructions -} sysz_insn; + // clang-format on + // generated content end + + SYSTEMZ_INS_ENDING, + + SYSTEMZ_INS_ALIAS_BEGIN, + // generated content begin + // clang-format off + + SYSTEMZ_INS_ALIAS_VISTRB, // Real instr.: SYSTEMZ_VISTRB + SYSTEMZ_INS_ALIAS_VISTR, // Real instr.: SYSTEMZ_VISTR + SYSTEMZ_INS_ALIAS_VFEEB, // Real instr.: SYSTEMZ_VFEEB + SYSTEMZ_INS_ALIAS_VFEE, // Real instr.: SYSTEMZ_VFEE + SYSTEMZ_INS_ALIAS_VFAEB, // Real instr.: SYSTEMZ_VFAEB + SYSTEMZ_INS_ALIAS_VFAEBS, // Real instr.: SYSTEMZ_VFAEBS + SYSTEMZ_INS_ALIAS_VFAE, // Real instr.: SYSTEMZ_VFAE + SYSTEMZ_INS_ALIAS_VSTRSB, // Real instr.: SYSTEMZ_VSTRSB + SYSTEMZ_INS_ALIAS_VSTRS, // Real instr.: SYSTEMZ_VSTRS + SYSTEMZ_INS_ALIAS_VSTRCB, // Real instr.: SYSTEMZ_VSTRCB + SYSTEMZ_INS_ALIAS_VSTRCBS, // Real instr.: SYSTEMZ_VSTRCBS + SYSTEMZ_INS_ALIAS_VSTRC, // Real instr.: SYSTEMZ_VSTRC + SYSTEMZ_INS_ALIAS_VFAEH, // Real instr.: SYSTEMZ_VFAEH + SYSTEMZ_INS_ALIAS_VFAEHS, // Real instr.: SYSTEMZ_VFAEHS + SYSTEMZ_INS_ALIAS_VFAEF, // Real instr.: SYSTEMZ_VFAEF + SYSTEMZ_INS_ALIAS_VFAEFS, // Real instr.: SYSTEMZ_VFAEFS + SYSTEMZ_INS_ALIAS_VFAEZB, // Real instr.: SYSTEMZ_VFAEZB + SYSTEMZ_INS_ALIAS_VFAEZBS, // Real instr.: SYSTEMZ_VFAEZBS + SYSTEMZ_INS_ALIAS_VFAEZH, // Real instr.: SYSTEMZ_VFAEZH + SYSTEMZ_INS_ALIAS_VFAEZHS, // Real instr.: SYSTEMZ_VFAEZHS + SYSTEMZ_INS_ALIAS_VFAEZF, // Real instr.: SYSTEMZ_VFAEZF + SYSTEMZ_INS_ALIAS_VFAEZFS, // Real instr.: SYSTEMZ_VFAEZFS + SYSTEMZ_INS_ALIAS_VFEEH, // Real instr.: SYSTEMZ_VFEEH + SYSTEMZ_INS_ALIAS_VFEEF, // Real instr.: SYSTEMZ_VFEEF + SYSTEMZ_INS_ALIAS_VFENE, // Real instr.: SYSTEMZ_VFENE + SYSTEMZ_INS_ALIAS_VFENEB, // Real instr.: SYSTEMZ_VFENEB + SYSTEMZ_INS_ALIAS_VFENEH, // Real instr.: SYSTEMZ_VFENEH + SYSTEMZ_INS_ALIAS_VFENEF, // Real instr.: SYSTEMZ_VFENEF + SYSTEMZ_INS_ALIAS_VISTRH, // Real instr.: SYSTEMZ_VISTRH + SYSTEMZ_INS_ALIAS_VISTRF, // Real instr.: SYSTEMZ_VISTRF + SYSTEMZ_INS_ALIAS_VSTRCH, // Real instr.: SYSTEMZ_VSTRCH + SYSTEMZ_INS_ALIAS_VSTRCHS, // Real instr.: SYSTEMZ_VSTRCHS + SYSTEMZ_INS_ALIAS_VSTRCF, // Real instr.: SYSTEMZ_VSTRCF + SYSTEMZ_INS_ALIAS_VSTRCFS, // Real instr.: SYSTEMZ_VSTRCFS + SYSTEMZ_INS_ALIAS_VSTRCZB, // Real instr.: SYSTEMZ_VSTRCZB + SYSTEMZ_INS_ALIAS_VSTRCZBS, // Real instr.: SYSTEMZ_VSTRCZBS + SYSTEMZ_INS_ALIAS_VSTRCZH, // Real instr.: SYSTEMZ_VSTRCZH + SYSTEMZ_INS_ALIAS_VSTRCZHS, // Real instr.: SYSTEMZ_VSTRCZHS + SYSTEMZ_INS_ALIAS_VSTRCZF, // Real instr.: SYSTEMZ_VSTRCZF + SYSTEMZ_INS_ALIAS_VSTRCZFS, // Real instr.: SYSTEMZ_VSTRCZFS + SYSTEMZ_INS_ALIAS_VSTRSH, // Real instr.: SYSTEMZ_VSTRSH + SYSTEMZ_INS_ALIAS_VSTRSF, // Real instr.: SYSTEMZ_VSTRSF + + // clang-format on + // generated content end + + // Hard-coded alias come here + + SYSTEMZ_INS_ALIAS_END, +} systemz_insn; /// Group of SystemZ instructions -typedef enum sysz_insn_group { - SYSZ_GRP_INVALID = 0, ///< = CS_GRP_INVALID +typedef enum systemz_insn_group { + SYSTEMZ_GRP_INVALID = 0, ///< = CS_GRP_INVALID // Generic groups // all jump instructions (conditional+direct+indirect jumps) - SYSZ_GRP_JUMP, ///< = CS_GRP_JUMP + SYSTEMZ_GRP_JUMP, ///< = CS_GRP_JUMP + SYSTEMZ_GRP_CALL, ///< CS_GRP_CALL + SYSTEMZ_GRP_RET, ///< CS_GRP_RET + SYSTEMZ_GRP_INT, ///< CS_GRP_INT + SYSTEMZ_GRP_IRET, ///< CS_GRP_IRET + SYSTEMZ_GRP_PRIVILEGE, ///< CS_GRP_PRIVILEGE + SYSTEMZ_GRP_BRANCH_RELATIVE, ///< CS_GRP_BRANCH_RELATIVE + // generated content begin + // clang-format off + + SYSTEMZ_FEATURE_FEATURESOFTFLOAT = 128, + SYSTEMZ_FEATURE_FEATUREBACKCHAIN, + SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, + SYSTEMZ_FEATURE_FEATUREFASTSERIALIZATION, + SYSTEMZ_FEATURE_FEATUREFPEXTENSION, + SYSTEMZ_FEATURE_FEATUREHIGHWORD, + SYSTEMZ_FEATURE_FEATUREINTERLOCKEDACCESS1, + SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, + SYSTEMZ_FEATURE_FEATUREPOPULATIONCOUNT, + SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST3, + SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST4, + SYSTEMZ_FEATURE_FEATURERESETREFERENCEBITSMULTIPLE, + SYSTEMZ_FEATURE_FEATUREEXECUTIONHINT, + SYSTEMZ_FEATURE_FEATURELOADANDTRAP, + SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, + SYSTEMZ_FEATURE_FEATUREPROCESSORASSIST, + SYSTEMZ_FEATURE_FEATURETRANSACTIONALEXECUTION, + SYSTEMZ_FEATURE_FEATUREDFPZONEDCONVERSION, + SYSTEMZ_FEATURE_FEATUREENHANCEDDAT2, + SYSTEMZ_FEATURE_FEATURELOADANDZERORIGHTMOSTBYTE, + SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, + SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST5, + SYSTEMZ_FEATURE_FEATUREDFPPACKEDCONVERSION, + SYSTEMZ_FEATURE_FEATUREVECTOR, + SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, + SYSTEMZ_FEATURE_FEATUREGUARDEDSTORAGE, + SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST7, + SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST8, + SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, + SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, + SYSTEMZ_FEATURE_FEATUREINSERTREFERENCEBITSMULTIPLE, + SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, + SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST9, + SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, + SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT, + SYSTEMZ_FEATURE_FEATUREENHANCEDSORT, + SYSTEMZ_FEATURE_FEATUREDEFLATECONVERSION, + SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT2, + SYSTEMZ_FEATURE_FEATURENNPASSIST, + SYSTEMZ_FEATURE_FEATUREBEARENHANCEMENT, + SYSTEMZ_FEATURE_FEATURERESETDATPROTECTION, + SYSTEMZ_FEATURE_FEATUREPROCESSORACTIVITYINSTRUMENTATION, - // Architecture-specific groups - SYSZ_GRP_DISTINCTOPS = 128, - SYSZ_GRP_FPEXTENSION, - SYSZ_GRP_HIGHWORD, - SYSZ_GRP_INTERLOCKEDACCESS1, - SYSZ_GRP_LOADSTOREONCOND, - SYSZ_GRP_DFPPACKEDCONVERSION, - SYSZ_GRP_DFPZONEDCONVERSION, - SYSZ_GRP_ENHANCEDDAT2, - SYSZ_GRP_EXECUTIONHINT, - SYSZ_GRP_GUARDEDSTORAGE, - SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE, - SYSZ_GRP_LOADANDTRAP, - SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, - SYSZ_GRP_LOADSTOREONCOND2, - SYSZ_GRP_MESSAGESECURITYASSIST3, - SYSZ_GRP_MESSAGESECURITYASSIST4, - SYSZ_GRP_MESSAGESECURITYASSIST5, - SYSZ_GRP_MESSAGESECURITYASSIST7, - SYSZ_GRP_MESSAGESECURITYASSIST8, - SYSZ_GRP_MISCELLANEOUSEXTENSIONS, - SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, - SYSZ_GRP_NOVECTOR, - SYSZ_GRP_POPULATIONCOUNT, - SYSZ_GRP_PROCESSORASSIST, - SYSZ_GRP_RESETREFERENCEBITSMULTIPLE, - SYSZ_GRP_TRANSACTIONALEXECUTION, - SYSZ_GRP_VECTOR, - SYSZ_GRP_VECTORENHANCEMENTS1, - SYSZ_GRP_VECTORPACKEDDECIMAL, + // clang-format on + // generated content end - SYSZ_GRP_ENDING, // <-- mark the end of the list of groups -} sysz_insn_group; + SYSTEMZ_GRP_ENDING, // <-- mark the end of the list of groups +} systemz_insn_group; + +#ifdef CAPSTONE_SYSTEMZ_COMPAT_HEADER +#include "systemz_compatibility.h" +#endif #ifdef __cplusplus } diff --git a/include/capstone/systemz_compatibility.h b/include/capstone/systemz_compatibility.h new file mode 100644 index 0000000000..ef397d7423 --- /dev/null +++ b/include/capstone/systemz_compatibility.h @@ -0,0 +1,2966 @@ +#ifndef CAPSTONE_SYSZ_H +#define CAPSTONE_SYSZ_H + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2014-2015 */ +/* By Rot127 , 2024 */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "platform.h" +#include "cs_operand.h" + +typedef enum { + SYSZ_CC_O = SYSTEMZ_CC_O, + SYSZ_CC_H = SYSTEMZ_CC_H, + SYSZ_CC_NLE = SYSTEMZ_CC_NLE, + SYSZ_CC_L = SYSTEMZ_CC_L, + SYSZ_CC_NHE = SYSTEMZ_CC_NHE, + SYSZ_CC_LH = SYSTEMZ_CC_LH, + SYSZ_CC_NE = SYSTEMZ_CC_NE, + SYSZ_CC_E = SYSTEMZ_CC_E, + SYSZ_CC_NLH = SYSTEMZ_CC_NLH, + SYSZ_CC_HE = SYSTEMZ_CC_HE, + SYSZ_CC_NL = SYSTEMZ_CC_NL, + SYSZ_CC_LE = SYSTEMZ_CC_LE, + SYSZ_CC_NH = SYSTEMZ_CC_NH, + SYSZ_CC_NO = SYSTEMZ_CC_NO, + SYSZ_CC_INVALID = SYSTEMZ_CC_INVALID, +} sysz_cc; + +typedef enum { + SYSZ_OP_INVALID = SYSTEMZ_OP_INVALID, + SYSZ_OP_REG = SYSTEMZ_OP_REG, + SYSZ_OP_IMM = SYSTEMZ_OP_IMM, + SYSZ_OP_MEM = SYSTEMZ_OP_MEM, +} sysz_op_type; + +typedef enum { + + SYSZ_REG_INVALID = SYSTEMZ_REG_INVALID, + SYSZ_REG_CC = SYSTEMZ_REG_CC, + SYSZ_REG_FPC = SYSTEMZ_REG_FPC, + SYSZ_REG_A0 = SYSTEMZ_REG_A0, + SYSZ_REG_A1 = SYSTEMZ_REG_A1, + SYSZ_REG_A2 = SYSTEMZ_REG_A2, + SYSZ_REG_A3 = SYSTEMZ_REG_A3, + SYSZ_REG_A4 = SYSTEMZ_REG_A4, + SYSZ_REG_A5 = SYSTEMZ_REG_A5, + SYSZ_REG_A6 = SYSTEMZ_REG_A6, + SYSZ_REG_A7 = SYSTEMZ_REG_A7, + SYSZ_REG_A8 = SYSTEMZ_REG_A8, + SYSZ_REG_A9 = SYSTEMZ_REG_A9, + SYSZ_REG_A10 = SYSTEMZ_REG_A10, + SYSZ_REG_A11 = SYSTEMZ_REG_A11, + SYSZ_REG_A12 = SYSTEMZ_REG_A12, + SYSZ_REG_A13 = SYSTEMZ_REG_A13, + SYSZ_REG_A14 = SYSTEMZ_REG_A14, + SYSZ_REG_A15 = SYSTEMZ_REG_A15, + SYSZ_REG_C0 = SYSTEMZ_REG_C0, + SYSZ_REG_C1 = SYSTEMZ_REG_C1, + SYSZ_REG_C2 = SYSTEMZ_REG_C2, + SYSZ_REG_C3 = SYSTEMZ_REG_C3, + SYSZ_REG_C4 = SYSTEMZ_REG_C4, + SYSZ_REG_C5 = SYSTEMZ_REG_C5, + SYSZ_REG_C6 = SYSTEMZ_REG_C6, + SYSZ_REG_C7 = SYSTEMZ_REG_C7, + SYSZ_REG_C8 = SYSTEMZ_REG_C8, + SYSZ_REG_C9 = SYSTEMZ_REG_C9, + SYSZ_REG_C10 = SYSTEMZ_REG_C10, + SYSZ_REG_C11 = SYSTEMZ_REG_C11, + SYSZ_REG_C12 = SYSTEMZ_REG_C12, + SYSZ_REG_C13 = SYSTEMZ_REG_C13, + SYSZ_REG_C14 = SYSTEMZ_REG_C14, + SYSZ_REG_C15 = SYSTEMZ_REG_C15, + SYSZ_REG_V0 = SYSTEMZ_REG_V0, + SYSZ_REG_V1 = SYSTEMZ_REG_V1, + SYSZ_REG_V2 = SYSTEMZ_REG_V2, + SYSZ_REG_V3 = SYSTEMZ_REG_V3, + SYSZ_REG_V4 = SYSTEMZ_REG_V4, + SYSZ_REG_V5 = SYSTEMZ_REG_V5, + SYSZ_REG_V6 = SYSTEMZ_REG_V6, + SYSZ_REG_V7 = SYSTEMZ_REG_V7, + SYSZ_REG_V8 = SYSTEMZ_REG_V8, + SYSZ_REG_V9 = SYSTEMZ_REG_V9, + SYSZ_REG_V10 = SYSTEMZ_REG_V10, + SYSZ_REG_V11 = SYSTEMZ_REG_V11, + SYSZ_REG_V12 = SYSTEMZ_REG_V12, + SYSZ_REG_V13 = SYSTEMZ_REG_V13, + SYSZ_REG_V14 = SYSTEMZ_REG_V14, + SYSZ_REG_V15 = SYSTEMZ_REG_V15, + SYSZ_REG_V16 = SYSTEMZ_REG_V16, + SYSZ_REG_V17 = SYSTEMZ_REG_V17, + SYSZ_REG_V18 = SYSTEMZ_REG_V18, + SYSZ_REG_V19 = SYSTEMZ_REG_V19, + SYSZ_REG_V20 = SYSTEMZ_REG_V20, + SYSZ_REG_V21 = SYSTEMZ_REG_V21, + SYSZ_REG_V22 = SYSTEMZ_REG_V22, + SYSZ_REG_V23 = SYSTEMZ_REG_V23, + SYSZ_REG_V24 = SYSTEMZ_REG_V24, + SYSZ_REG_V25 = SYSTEMZ_REG_V25, + SYSZ_REG_V26 = SYSTEMZ_REG_V26, + SYSZ_REG_V27 = SYSTEMZ_REG_V27, + SYSZ_REG_V28 = SYSTEMZ_REG_V28, + SYSZ_REG_V29 = SYSTEMZ_REG_V29, + SYSZ_REG_V30 = SYSTEMZ_REG_V30, + SYSZ_REG_V31 = SYSTEMZ_REG_V31, + SYSZ_REG_F0D = SYSTEMZ_REG_F0D, + SYSZ_REG_F1D = SYSTEMZ_REG_F1D, + SYSZ_REG_F2D = SYSTEMZ_REG_F2D, + SYSZ_REG_F3D = SYSTEMZ_REG_F3D, + SYSZ_REG_F4D = SYSTEMZ_REG_F4D, + SYSZ_REG_F5D = SYSTEMZ_REG_F5D, + SYSZ_REG_F6D = SYSTEMZ_REG_F6D, + SYSZ_REG_F7D = SYSTEMZ_REG_F7D, + SYSZ_REG_F8D = SYSTEMZ_REG_F8D, + SYSZ_REG_F9D = SYSTEMZ_REG_F9D, + SYSZ_REG_F10D = SYSTEMZ_REG_F10D, + SYSZ_REG_F11D = SYSTEMZ_REG_F11D, + SYSZ_REG_F12D = SYSTEMZ_REG_F12D, + SYSZ_REG_F13D = SYSTEMZ_REG_F13D, + SYSZ_REG_F14D = SYSTEMZ_REG_F14D, + SYSZ_REG_F15D = SYSTEMZ_REG_F15D, + SYSZ_REG_F16D = SYSTEMZ_REG_F16D, + SYSZ_REG_F17D = SYSTEMZ_REG_F17D, + SYSZ_REG_F18D = SYSTEMZ_REG_F18D, + SYSZ_REG_F19D = SYSTEMZ_REG_F19D, + SYSZ_REG_F20D = SYSTEMZ_REG_F20D, + SYSZ_REG_F21D = SYSTEMZ_REG_F21D, + SYSZ_REG_F22D = SYSTEMZ_REG_F22D, + SYSZ_REG_F23D = SYSTEMZ_REG_F23D, + SYSZ_REG_F24D = SYSTEMZ_REG_F24D, + SYSZ_REG_F25D = SYSTEMZ_REG_F25D, + SYSZ_REG_F26D = SYSTEMZ_REG_F26D, + SYSZ_REG_F27D = SYSTEMZ_REG_F27D, + SYSZ_REG_F28D = SYSTEMZ_REG_F28D, + SYSZ_REG_F29D = SYSTEMZ_REG_F29D, + SYSZ_REG_F30D = SYSTEMZ_REG_F30D, + SYSZ_REG_F31D = SYSTEMZ_REG_F31D, + SYSZ_REG_F0Q = SYSTEMZ_REG_F0Q, + SYSZ_REG_F1Q = SYSTEMZ_REG_F1Q, + SYSZ_REG_F4Q = SYSTEMZ_REG_F4Q, + SYSZ_REG_F5Q = SYSTEMZ_REG_F5Q, + SYSZ_REG_F8Q = SYSTEMZ_REG_F8Q, + SYSZ_REG_F9Q = SYSTEMZ_REG_F9Q, + SYSZ_REG_F12Q = SYSTEMZ_REG_F12Q, + SYSZ_REG_F13Q = SYSTEMZ_REG_F13Q, + SYSZ_REG_F0S = SYSTEMZ_REG_F0S, + SYSZ_REG_F1S = SYSTEMZ_REG_F1S, + SYSZ_REG_F2S = SYSTEMZ_REG_F2S, + SYSZ_REG_F3S = SYSTEMZ_REG_F3S, + SYSZ_REG_F4S = SYSTEMZ_REG_F4S, + SYSZ_REG_F5S = SYSTEMZ_REG_F5S, + SYSZ_REG_F6S = SYSTEMZ_REG_F6S, + SYSZ_REG_F7S = SYSTEMZ_REG_F7S, + SYSZ_REG_F8S = SYSTEMZ_REG_F8S, + SYSZ_REG_F9S = SYSTEMZ_REG_F9S, + SYSZ_REG_F10S = SYSTEMZ_REG_F10S, + SYSZ_REG_F11S = SYSTEMZ_REG_F11S, + SYSZ_REG_F12S = SYSTEMZ_REG_F12S, + SYSZ_REG_F13S = SYSTEMZ_REG_F13S, + SYSZ_REG_F14S = SYSTEMZ_REG_F14S, + SYSZ_REG_F15S = SYSTEMZ_REG_F15S, + SYSZ_REG_F16S = SYSTEMZ_REG_F16S, + SYSZ_REG_F17S = SYSTEMZ_REG_F17S, + SYSZ_REG_F18S = SYSTEMZ_REG_F18S, + SYSZ_REG_F19S = SYSTEMZ_REG_F19S, + SYSZ_REG_F20S = SYSTEMZ_REG_F20S, + SYSZ_REG_F21S = SYSTEMZ_REG_F21S, + SYSZ_REG_F22S = SYSTEMZ_REG_F22S, + SYSZ_REG_F23S = SYSTEMZ_REG_F23S, + SYSZ_REG_F24S = SYSTEMZ_REG_F24S, + SYSZ_REG_F25S = SYSTEMZ_REG_F25S, + SYSZ_REG_F26S = SYSTEMZ_REG_F26S, + SYSZ_REG_F27S = SYSTEMZ_REG_F27S, + SYSZ_REG_F28S = SYSTEMZ_REG_F28S, + SYSZ_REG_F29S = SYSTEMZ_REG_F29S, + SYSZ_REG_F30S = SYSTEMZ_REG_F30S, + SYSZ_REG_F31S = SYSTEMZ_REG_F31S, + SYSZ_REG_R0D = SYSTEMZ_REG_R0D, + SYSZ_REG_R1D = SYSTEMZ_REG_R1D, + SYSZ_REG_R2D = SYSTEMZ_REG_R2D, + SYSZ_REG_R3D = SYSTEMZ_REG_R3D, + SYSZ_REG_R4D = SYSTEMZ_REG_R4D, + SYSZ_REG_R5D = SYSTEMZ_REG_R5D, + SYSZ_REG_R6D = SYSTEMZ_REG_R6D, + SYSZ_REG_R7D = SYSTEMZ_REG_R7D, + SYSZ_REG_R8D = SYSTEMZ_REG_R8D, + SYSZ_REG_R9D = SYSTEMZ_REG_R9D, + SYSZ_REG_R10D = SYSTEMZ_REG_R10D, + SYSZ_REG_R11D = SYSTEMZ_REG_R11D, + SYSZ_REG_R12D = SYSTEMZ_REG_R12D, + SYSZ_REG_R13D = SYSTEMZ_REG_R13D, + SYSZ_REG_R14D = SYSTEMZ_REG_R14D, + SYSZ_REG_R15D = SYSTEMZ_REG_R15D, + SYSZ_REG_R0H = SYSTEMZ_REG_R0H, + SYSZ_REG_R1H = SYSTEMZ_REG_R1H, + SYSZ_REG_R2H = SYSTEMZ_REG_R2H, + SYSZ_REG_R3H = SYSTEMZ_REG_R3H, + SYSZ_REG_R4H = SYSTEMZ_REG_R4H, + SYSZ_REG_R5H = SYSTEMZ_REG_R5H, + SYSZ_REG_R6H = SYSTEMZ_REG_R6H, + SYSZ_REG_R7H = SYSTEMZ_REG_R7H, + SYSZ_REG_R8H = SYSTEMZ_REG_R8H, + SYSZ_REG_R9H = SYSTEMZ_REG_R9H, + SYSZ_REG_R10H = SYSTEMZ_REG_R10H, + SYSZ_REG_R11H = SYSTEMZ_REG_R11H, + SYSZ_REG_R12H = SYSTEMZ_REG_R12H, + SYSZ_REG_R13H = SYSTEMZ_REG_R13H, + SYSZ_REG_R14H = SYSTEMZ_REG_R14H, + SYSZ_REG_R15H = SYSTEMZ_REG_R15H, + SYSZ_REG_R0L = SYSTEMZ_REG_R0L, + SYSZ_REG_R1L = SYSTEMZ_REG_R1L, + SYSZ_REG_R2L = SYSTEMZ_REG_R2L, + SYSZ_REG_R3L = SYSTEMZ_REG_R3L, + SYSZ_REG_R4L = SYSTEMZ_REG_R4L, + SYSZ_REG_R5L = SYSTEMZ_REG_R5L, + SYSZ_REG_R6L = SYSTEMZ_REG_R6L, + SYSZ_REG_R7L = SYSTEMZ_REG_R7L, + SYSZ_REG_R8L = SYSTEMZ_REG_R8L, + SYSZ_REG_R9L = SYSTEMZ_REG_R9L, + SYSZ_REG_R10L = SYSTEMZ_REG_R10L, + SYSZ_REG_R11L = SYSTEMZ_REG_R11L, + SYSZ_REG_R12L = SYSTEMZ_REG_R12L, + SYSZ_REG_R13L = SYSTEMZ_REG_R13L, + SYSZ_REG_R14L = SYSTEMZ_REG_R14L, + SYSZ_REG_R15L = SYSTEMZ_REG_R15L, + SYSZ_REG_R0Q = SYSTEMZ_REG_R0Q, + SYSZ_REG_R2Q = SYSTEMZ_REG_R2Q, + SYSZ_REG_R4Q = SYSTEMZ_REG_R4Q, + SYSZ_REG_R6Q = SYSTEMZ_REG_R6Q, + SYSZ_REG_R8Q = SYSTEMZ_REG_R8Q, + SYSZ_REG_R10Q = SYSTEMZ_REG_R10Q, + SYSZ_REG_R12Q = SYSTEMZ_REG_R12Q, + SYSZ_REG_R14Q = SYSTEMZ_REG_R14Q, + SYSZ_REG_ENDING = SYSTEMZ_REG_ENDING, + + +} sysz_reg; + +typedef enum { + SYSZ_INSN_FORM_INVALID = SYSTEMZ_INSN_FORM_INVALID, + + SYSZ_INSN_FORM_INSTRXA = SYSTEMZ_INSN_FORM_INSTRXA, + SYSZ_INSN_FORM_INSTRXE = SYSTEMZ_INSN_FORM_INSTRXE, + SYSZ_INSN_FORM_INSTRRE = SYSTEMZ_INSN_FORM_INSTRRE, + SYSZ_INSN_FORM_INSTRR = SYSTEMZ_INSN_FORM_INSTRR, + SYSZ_INSN_FORM_INSTRRFA = SYSTEMZ_INSN_FORM_INSTRRFA, + SYSZ_INSN_FORM_INSTRILA = SYSTEMZ_INSN_FORM_INSTRILA, + SYSZ_INSN_FORM_INSTRXYA = SYSTEMZ_INSN_FORM_INSTRXYA, + SYSZ_INSN_FORM_INSTRIA = SYSTEMZ_INSN_FORM_INSTRIA, + SYSZ_INSN_FORM_INSTRIED = SYSTEMZ_INSN_FORM_INSTRIED, + SYSZ_INSN_FORM_INSTSIY = SYSTEMZ_INSN_FORM_INSTSIY, + SYSZ_INSN_FORM_INSTSSB = SYSTEMZ_INSN_FORM_INSTSSB, + SYSZ_INSN_FORM_INSTRXB = SYSTEMZ_INSN_FORM_INSTRXB, + SYSZ_INSN_FORM_INSTRXYB = SYSTEMZ_INSN_FORM_INSTRXYB, + SYSZ_INSN_FORM_INSTSMI = SYSTEMZ_INSN_FORM_INSTSMI, + SYSZ_INSN_FORM_INSTMII = SYSTEMZ_INSN_FORM_INSTMII, + SYSZ_INSN_FORM_INSTRIB = SYSTEMZ_INSN_FORM_INSTRIB, + SYSZ_INSN_FORM_INSTRILB = SYSTEMZ_INSN_FORM_INSTRILB, + SYSZ_INSN_FORM_INSTRIC = SYSTEMZ_INSN_FORM_INSTRIC, + SYSZ_INSN_FORM_INSTRILC = SYSTEMZ_INSN_FORM_INSTRILC, + SYSZ_INSN_FORM_INSTRSI = SYSTEMZ_INSN_FORM_INSTRSI, + SYSZ_INSN_FORM_INSTRIEE = SYSTEMZ_INSN_FORM_INSTRIEE, + SYSZ_INSN_FORM_INSTRSA = SYSTEMZ_INSN_FORM_INSTRSA, + SYSZ_INSN_FORM_INSTRSYA = SYSTEMZ_INSN_FORM_INSTRSYA, + SYSZ_INSN_FORM_INSTRRFE = SYSTEMZ_INSN_FORM_INSTRRFE, + SYSZ_INSN_FORM_INSTRSLB = SYSTEMZ_INSN_FORM_INSTRSLB, + SYSZ_INSN_FORM_INSTS = SYSTEMZ_INSN_FORM_INSTS, + SYSZ_INSN_FORM_INSTSIL = SYSTEMZ_INSN_FORM_INSTSIL, + SYSZ_INSN_FORM_INSTRIS = SYSTEMZ_INSN_FORM_INSTRIS, + SYSZ_INSN_FORM_INSTRIEC = SYSTEMZ_INSN_FORM_INSTRIEC, + SYSZ_INSN_FORM_INSTRIEA = SYSTEMZ_INSN_FORM_INSTRIEA, + SYSZ_INSN_FORM_INSTRRS = SYSTEMZ_INSN_FORM_INSTRRS, + SYSZ_INSN_FORM_INSTRIEB = SYSTEMZ_INSN_FORM_INSTRIEB, + SYSZ_INSN_FORM_INSTRRFC = SYSTEMZ_INSN_FORM_INSTRRFC, + SYSZ_INSN_FORM_INSTSSA = SYSTEMZ_INSN_FORM_INSTSSA, + SYSZ_INSN_FORM_INSTRSYB = SYSTEMZ_INSN_FORM_INSTRSYB, + SYSZ_INSN_FORM_INSTSI = SYSTEMZ_INSN_FORM_INSTSI, + SYSZ_INSN_FORM_INSTRSB = SYSTEMZ_INSN_FORM_INSTRSB, + SYSZ_INSN_FORM_INSTRRFB = SYSTEMZ_INSN_FORM_INSTRRFB, + SYSZ_INSN_FORM_INSTRRFD = SYSTEMZ_INSN_FORM_INSTRRFD, + SYSZ_INSN_FORM_INSTSSF = SYSTEMZ_INSN_FORM_INSTSSF, + SYSZ_INSN_FORM_INSTSSE = SYSTEMZ_INSN_FORM_INSTSSE, + SYSZ_INSN_FORM_INSTRIEG = SYSTEMZ_INSN_FORM_INSTRIEG, + SYSZ_INSN_FORM_INSTRXF = SYSTEMZ_INSN_FORM_INSTRXF, + SYSZ_INSN_FORM_INSTRRD = SYSTEMZ_INSN_FORM_INSTRRD, + SYSZ_INSN_FORM_INSTSSD = SYSTEMZ_INSN_FORM_INSTSSD, + SYSZ_INSN_FORM_INSTIE = SYSTEMZ_INSN_FORM_INSTIE, + SYSZ_INSN_FORM_INSTE = SYSTEMZ_INSN_FORM_INSTE, + SYSZ_INSN_FORM_INSTRIEF = SYSTEMZ_INSN_FORM_INSTRIEF, + SYSZ_INSN_FORM_INSTSSC = SYSTEMZ_INSN_FORM_INSTSSC, + SYSZ_INSN_FORM_INSTI = SYSTEMZ_INSN_FORM_INSTI, + SYSZ_INSN_FORM_INSTRSLA = SYSTEMZ_INSN_FORM_INSTRSLA, + SYSZ_INSN_FORM_INSTVRRC = SYSTEMZ_INSN_FORM_INSTVRRC, + SYSZ_INSN_FORM_INSTVRRD = SYSTEMZ_INSN_FORM_INSTVRRD, + SYSZ_INSN_FORM_INSTVRIF = SYSTEMZ_INSN_FORM_INSTVRIF, + SYSZ_INSN_FORM_INSTVRRA = SYSTEMZ_INSN_FORM_INSTVRRA, + SYSZ_INSN_FORM_INSTVRRB = SYSTEMZ_INSN_FORM_INSTVRRB, + SYSZ_INSN_FORM_INSTVRRK = SYSTEMZ_INSN_FORM_INSTVRRK, + SYSZ_INSN_FORM_INSTVRRH = SYSTEMZ_INSN_FORM_INSTVRRH, + SYSZ_INSN_FORM_INSTVRRJ = SYSTEMZ_INSN_FORM_INSTVRRJ, + SYSZ_INSN_FORM_INSTVRRI = SYSTEMZ_INSN_FORM_INSTVRRI, + SYSZ_INSN_FORM_INSTVRII = SYSTEMZ_INSN_FORM_INSTVRII, + SYSZ_INSN_FORM_INSTVRID = SYSTEMZ_INSN_FORM_INSTVRID, + SYSZ_INSN_FORM_INSTVRSA = SYSTEMZ_INSN_FORM_INSTVRSA, + SYSZ_INSN_FORM_INSTVRRE = SYSTEMZ_INSN_FORM_INSTVRRE, + SYSZ_INSN_FORM_INSTVRIE = SYSTEMZ_INSN_FORM_INSTVRIE, + SYSZ_INSN_FORM_INSTVRIA = SYSTEMZ_INSN_FORM_INSTVRIA, + SYSZ_INSN_FORM_INSTVRV = SYSTEMZ_INSN_FORM_INSTVRV, + SYSZ_INSN_FORM_INSTVRIB = SYSTEMZ_INSN_FORM_INSTVRIB, + SYSZ_INSN_FORM_INSTVRX = SYSTEMZ_INSN_FORM_INSTVRX, + SYSZ_INSN_FORM_INSTVRSC = SYSTEMZ_INSN_FORM_INSTVRSC, + SYSZ_INSN_FORM_INSTVRIH = SYSTEMZ_INSN_FORM_INSTVRIH, + SYSZ_INSN_FORM_INSTVRSB = SYSTEMZ_INSN_FORM_INSTVRSB, + SYSZ_INSN_FORM_INSTVSI = SYSTEMZ_INSN_FORM_INSTVSI, + SYSZ_INSN_FORM_INSTVRSD = SYSTEMZ_INSN_FORM_INSTVRSD, + SYSZ_INSN_FORM_INSTVRRF = SYSTEMZ_INSN_FORM_INSTVRRF, + SYSZ_INSN_FORM_INSTVRIG = SYSTEMZ_INSN_FORM_INSTVRIG, + SYSZ_INSN_FORM_INSTVRIC = SYSTEMZ_INSN_FORM_INSTVRIC, + SYSZ_INSN_FORM_INSTVRRG = SYSTEMZ_INSN_FORM_INSTVRRG, + + +} sysz_insn_form; + +typedef enum { + SYSZ_AM_INVALID = SYSTEMZ_AM_INVALID, + SYSZ_AM_BD = SYSTEMZ_AM_BD, + SYSZ_AM_BDX = SYSTEMZ_AM_BDX, + SYSZ_AM_BDL = SYSTEMZ_AM_BDL, + SYSZ_AM_BDR = SYSTEMZ_AM_BDR, + SYSZ_AM_BDV = SYSTEMZ_AM_BDV, +} sysz_addr_mode; + +typedef systemz_suppl_info sysz_suppl_info; + +typedef systemz_op_mem sysz_op_mem; + +typedef cs_systemz_op cs_sysz_op; + +#define MAX_SYSZ_OPS 6 + +typedef cs_systemz cs_sysz; + +typedef enum { + + SYSZ_INS_INVALID = SYSTEMZ_INS_INVALID, + SYSZ_INS_A = SYSTEMZ_INS_A, + SYSZ_INS_AD = SYSTEMZ_INS_AD, + SYSZ_INS_ADB = SYSTEMZ_INS_ADB, + SYSZ_INS_ADBR = SYSTEMZ_INS_ADBR, + SYSZ_INS_ADR = SYSTEMZ_INS_ADR, + SYSZ_INS_ADTR = SYSTEMZ_INS_ADTR, + SYSZ_INS_ADTRA = SYSTEMZ_INS_ADTRA, + SYSZ_INS_AE = SYSTEMZ_INS_AE, + SYSZ_INS_AEB = SYSTEMZ_INS_AEB, + SYSZ_INS_AEBR = SYSTEMZ_INS_AEBR, + SYSZ_INS_AER = SYSTEMZ_INS_AER, + SYSZ_INS_AFI = SYSTEMZ_INS_AFI, + SYSZ_INS_AG = SYSTEMZ_INS_AG, + SYSZ_INS_AGF = SYSTEMZ_INS_AGF, + SYSZ_INS_AGFI = SYSTEMZ_INS_AGFI, + SYSZ_INS_AGFR = SYSTEMZ_INS_AGFR, + SYSZ_INS_AGH = SYSTEMZ_INS_AGH, + SYSZ_INS_AGHI = SYSTEMZ_INS_AGHI, + SYSZ_INS_AGHIK = SYSTEMZ_INS_AGHIK, + SYSZ_INS_AGR = SYSTEMZ_INS_AGR, + SYSZ_INS_AGRK = SYSTEMZ_INS_AGRK, + SYSZ_INS_AGSI = SYSTEMZ_INS_AGSI, + SYSZ_INS_AH = SYSTEMZ_INS_AH, + SYSZ_INS_AHHHR = SYSTEMZ_INS_AHHHR, + SYSZ_INS_AHHLR = SYSTEMZ_INS_AHHLR, + SYSZ_INS_AHI = SYSTEMZ_INS_AHI, + SYSZ_INS_AHIK = SYSTEMZ_INS_AHIK, + SYSZ_INS_AHY = SYSTEMZ_INS_AHY, + SYSZ_INS_AIH = SYSTEMZ_INS_AIH, + SYSZ_INS_AL = SYSTEMZ_INS_AL, + SYSZ_INS_ALC = SYSTEMZ_INS_ALC, + SYSZ_INS_ALCG = SYSTEMZ_INS_ALCG, + SYSZ_INS_ALCGR = SYSTEMZ_INS_ALCGR, + SYSZ_INS_ALCR = SYSTEMZ_INS_ALCR, + SYSZ_INS_ALFI = SYSTEMZ_INS_ALFI, + SYSZ_INS_ALG = SYSTEMZ_INS_ALG, + SYSZ_INS_ALGF = SYSTEMZ_INS_ALGF, + SYSZ_INS_ALGFI = SYSTEMZ_INS_ALGFI, + SYSZ_INS_ALGFR = SYSTEMZ_INS_ALGFR, + SYSZ_INS_ALGHSIK = SYSTEMZ_INS_ALGHSIK, + SYSZ_INS_ALGR = SYSTEMZ_INS_ALGR, + SYSZ_INS_ALGRK = SYSTEMZ_INS_ALGRK, + SYSZ_INS_ALGSI = SYSTEMZ_INS_ALGSI, + SYSZ_INS_ALHHHR = SYSTEMZ_INS_ALHHHR, + SYSZ_INS_ALHHLR = SYSTEMZ_INS_ALHHLR, + SYSZ_INS_ALHSIK = SYSTEMZ_INS_ALHSIK, + SYSZ_INS_ALR = SYSTEMZ_INS_ALR, + SYSZ_INS_ALRK = SYSTEMZ_INS_ALRK, + SYSZ_INS_ALSI = SYSTEMZ_INS_ALSI, + SYSZ_INS_ALSIH = SYSTEMZ_INS_ALSIH, + SYSZ_INS_ALSIHN = SYSTEMZ_INS_ALSIHN, + SYSZ_INS_ALY = SYSTEMZ_INS_ALY, + SYSZ_INS_AP = SYSTEMZ_INS_AP, + SYSZ_INS_AR = SYSTEMZ_INS_AR, + SYSZ_INS_ARK = SYSTEMZ_INS_ARK, + SYSZ_INS_ASI = SYSTEMZ_INS_ASI, + SYSZ_INS_AU = SYSTEMZ_INS_AU, + SYSZ_INS_AUR = SYSTEMZ_INS_AUR, + SYSZ_INS_AW = SYSTEMZ_INS_AW, + SYSZ_INS_AWR = SYSTEMZ_INS_AWR, + SYSZ_INS_AXBR = SYSTEMZ_INS_AXBR, + SYSZ_INS_AXR = SYSTEMZ_INS_AXR, + SYSZ_INS_AXTR = SYSTEMZ_INS_AXTR, + SYSZ_INS_AXTRA = SYSTEMZ_INS_AXTRA, + SYSZ_INS_AY = SYSTEMZ_INS_AY, + SYSZ_INS_B = SYSTEMZ_INS_B, + SYSZ_INS_BAKR = SYSTEMZ_INS_BAKR, + SYSZ_INS_BAL = SYSTEMZ_INS_BAL, + SYSZ_INS_BALR = SYSTEMZ_INS_BALR, + SYSZ_INS_BAS = SYSTEMZ_INS_BAS, + SYSZ_INS_BASR = SYSTEMZ_INS_BASR, + SYSZ_INS_BASSM = SYSTEMZ_INS_BASSM, + SYSZ_INS_BE = SYSTEMZ_INS_BE, + SYSZ_INS_BH = SYSTEMZ_INS_BH, + SYSZ_INS_BHE = SYSTEMZ_INS_BHE, + SYSZ_INS_BL = SYSTEMZ_INS_BL, + SYSZ_INS_BLE = SYSTEMZ_INS_BLE, + SYSZ_INS_BLH = SYSTEMZ_INS_BLH, + SYSZ_INS_BM = SYSTEMZ_INS_BM, + SYSZ_INS_BNE = SYSTEMZ_INS_BNE, + SYSZ_INS_BNH = SYSTEMZ_INS_BNH, + SYSZ_INS_BNHE = SYSTEMZ_INS_BNHE, + SYSZ_INS_BNL = SYSTEMZ_INS_BNL, + SYSZ_INS_BNLE = SYSTEMZ_INS_BNLE, + SYSZ_INS_BNLH = SYSTEMZ_INS_BNLH, + SYSZ_INS_BNM = SYSTEMZ_INS_BNM, + SYSZ_INS_BNO = SYSTEMZ_INS_BNO, + SYSZ_INS_BNP = SYSTEMZ_INS_BNP, + SYSZ_INS_BNZ = SYSTEMZ_INS_BNZ, + SYSZ_INS_BO = SYSTEMZ_INS_BO, + SYSZ_INS_BP = SYSTEMZ_INS_BP, + SYSZ_INS_BZ = SYSTEMZ_INS_BZ, + SYSZ_INS_BC = SYSTEMZ_INS_BC, + SYSZ_INS_BCR = SYSTEMZ_INS_BCR, + SYSZ_INS_BCT = SYSTEMZ_INS_BCT, + SYSZ_INS_BCTG = SYSTEMZ_INS_BCTG, + SYSZ_INS_BCTGR = SYSTEMZ_INS_BCTGR, + SYSZ_INS_BCTR = SYSTEMZ_INS_BCTR, + SYSZ_INS_BI = SYSTEMZ_INS_BI, + SYSZ_INS_BIE = SYSTEMZ_INS_BIE, + SYSZ_INS_BIH = SYSTEMZ_INS_BIH, + SYSZ_INS_BIHE = SYSTEMZ_INS_BIHE, + SYSZ_INS_BIL = SYSTEMZ_INS_BIL, + SYSZ_INS_BILE = SYSTEMZ_INS_BILE, + SYSZ_INS_BILH = SYSTEMZ_INS_BILH, + SYSZ_INS_BIM = SYSTEMZ_INS_BIM, + SYSZ_INS_BINE = SYSTEMZ_INS_BINE, + SYSZ_INS_BINH = SYSTEMZ_INS_BINH, + SYSZ_INS_BINHE = SYSTEMZ_INS_BINHE, + SYSZ_INS_BINL = SYSTEMZ_INS_BINL, + SYSZ_INS_BINLE = SYSTEMZ_INS_BINLE, + SYSZ_INS_BINLH = SYSTEMZ_INS_BINLH, + SYSZ_INS_BINM = SYSTEMZ_INS_BINM, + SYSZ_INS_BINO = SYSTEMZ_INS_BINO, + SYSZ_INS_BINP = SYSTEMZ_INS_BINP, + SYSZ_INS_BINZ = SYSTEMZ_INS_BINZ, + SYSZ_INS_BIO = SYSTEMZ_INS_BIO, + SYSZ_INS_BIP = SYSTEMZ_INS_BIP, + SYSZ_INS_BIZ = SYSTEMZ_INS_BIZ, + SYSZ_INS_BIC = SYSTEMZ_INS_BIC, + SYSZ_INS_BPP = SYSTEMZ_INS_BPP, + SYSZ_INS_BPRP = SYSTEMZ_INS_BPRP, + SYSZ_INS_BR = SYSTEMZ_INS_BR, + SYSZ_INS_BRAS = SYSTEMZ_INS_BRAS, + SYSZ_INS_BRASL = SYSTEMZ_INS_BRASL, + SYSZ_INS_BER = SYSTEMZ_INS_BER, + SYSZ_INS_BHR = SYSTEMZ_INS_BHR, + SYSZ_INS_BHER = SYSTEMZ_INS_BHER, + SYSZ_INS_BLR = SYSTEMZ_INS_BLR, + SYSZ_INS_BLER = SYSTEMZ_INS_BLER, + SYSZ_INS_BLHR = SYSTEMZ_INS_BLHR, + SYSZ_INS_BMR = SYSTEMZ_INS_BMR, + SYSZ_INS_BNER = SYSTEMZ_INS_BNER, + SYSZ_INS_BNHR = SYSTEMZ_INS_BNHR, + SYSZ_INS_BNHER = SYSTEMZ_INS_BNHER, + SYSZ_INS_BNLR = SYSTEMZ_INS_BNLR, + SYSZ_INS_BNLER = SYSTEMZ_INS_BNLER, + SYSZ_INS_BNLHR = SYSTEMZ_INS_BNLHR, + SYSZ_INS_BNMR = SYSTEMZ_INS_BNMR, + SYSZ_INS_BNOR = SYSTEMZ_INS_BNOR, + SYSZ_INS_BNPR = SYSTEMZ_INS_BNPR, + SYSZ_INS_BNZR = SYSTEMZ_INS_BNZR, + SYSZ_INS_BOR = SYSTEMZ_INS_BOR, + SYSZ_INS_BPR = SYSTEMZ_INS_BPR, + SYSZ_INS_BZR = SYSTEMZ_INS_BZR, + SYSZ_INS_BRC = SYSTEMZ_INS_BRC, + SYSZ_INS_BRCL = SYSTEMZ_INS_BRCL, + SYSZ_INS_BRCT = SYSTEMZ_INS_BRCT, + SYSZ_INS_BRCTG = SYSTEMZ_INS_BRCTG, + SYSZ_INS_BRCTH = SYSTEMZ_INS_BRCTH, + SYSZ_INS_BRXH = SYSTEMZ_INS_BRXH, + SYSZ_INS_BRXHG = SYSTEMZ_INS_BRXHG, + SYSZ_INS_BRXLE = SYSTEMZ_INS_BRXLE, + SYSZ_INS_BRXLG = SYSTEMZ_INS_BRXLG, + SYSZ_INS_BSA = SYSTEMZ_INS_BSA, + SYSZ_INS_BSG = SYSTEMZ_INS_BSG, + SYSZ_INS_BSM = SYSTEMZ_INS_BSM, + SYSZ_INS_BXH = SYSTEMZ_INS_BXH, + SYSZ_INS_BXHG = SYSTEMZ_INS_BXHG, + SYSZ_INS_BXLE = SYSTEMZ_INS_BXLE, + SYSZ_INS_BXLEG = SYSTEMZ_INS_BXLEG, + SYSZ_INS_C = SYSTEMZ_INS_C, + SYSZ_INS_CD = SYSTEMZ_INS_CD, + SYSZ_INS_CDB = SYSTEMZ_INS_CDB, + SYSZ_INS_CDBR = SYSTEMZ_INS_CDBR, + SYSZ_INS_CDFBR = SYSTEMZ_INS_CDFBR, + SYSZ_INS_CDFBRA = SYSTEMZ_INS_CDFBRA, + SYSZ_INS_CDFR = SYSTEMZ_INS_CDFR, + SYSZ_INS_CDFTR = SYSTEMZ_INS_CDFTR, + SYSZ_INS_CDGBR = SYSTEMZ_INS_CDGBR, + SYSZ_INS_CDGBRA = SYSTEMZ_INS_CDGBRA, + SYSZ_INS_CDGR = SYSTEMZ_INS_CDGR, + SYSZ_INS_CDGTR = SYSTEMZ_INS_CDGTR, + SYSZ_INS_CDGTRA = SYSTEMZ_INS_CDGTRA, + SYSZ_INS_CDLFBR = SYSTEMZ_INS_CDLFBR, + SYSZ_INS_CDLFTR = SYSTEMZ_INS_CDLFTR, + SYSZ_INS_CDLGBR = SYSTEMZ_INS_CDLGBR, + SYSZ_INS_CDLGTR = SYSTEMZ_INS_CDLGTR, + SYSZ_INS_CDPT = SYSTEMZ_INS_CDPT, + SYSZ_INS_CDR = SYSTEMZ_INS_CDR, + SYSZ_INS_CDS = SYSTEMZ_INS_CDS, + SYSZ_INS_CDSG = SYSTEMZ_INS_CDSG, + SYSZ_INS_CDSTR = SYSTEMZ_INS_CDSTR, + SYSZ_INS_CDSY = SYSTEMZ_INS_CDSY, + SYSZ_INS_CDTR = SYSTEMZ_INS_CDTR, + SYSZ_INS_CDUTR = SYSTEMZ_INS_CDUTR, + SYSZ_INS_CDZT = SYSTEMZ_INS_CDZT, + SYSZ_INS_CE = SYSTEMZ_INS_CE, + SYSZ_INS_CEB = SYSTEMZ_INS_CEB, + SYSZ_INS_CEBR = SYSTEMZ_INS_CEBR, + SYSZ_INS_CEDTR = SYSTEMZ_INS_CEDTR, + SYSZ_INS_CEFBR = SYSTEMZ_INS_CEFBR, + SYSZ_INS_CEFBRA = SYSTEMZ_INS_CEFBRA, + SYSZ_INS_CEFR = SYSTEMZ_INS_CEFR, + SYSZ_INS_CEGBR = SYSTEMZ_INS_CEGBR, + SYSZ_INS_CEGBRA = SYSTEMZ_INS_CEGBRA, + SYSZ_INS_CEGR = SYSTEMZ_INS_CEGR, + SYSZ_INS_CELFBR = SYSTEMZ_INS_CELFBR, + SYSZ_INS_CELGBR = SYSTEMZ_INS_CELGBR, + SYSZ_INS_CER = SYSTEMZ_INS_CER, + SYSZ_INS_CEXTR = SYSTEMZ_INS_CEXTR, + SYSZ_INS_CFC = SYSTEMZ_INS_CFC, + SYSZ_INS_CFDBR = SYSTEMZ_INS_CFDBR, + SYSZ_INS_CFDBRA = SYSTEMZ_INS_CFDBRA, + SYSZ_INS_CFDR = SYSTEMZ_INS_CFDR, + SYSZ_INS_CFDTR = SYSTEMZ_INS_CFDTR, + SYSZ_INS_CFEBR = SYSTEMZ_INS_CFEBR, + SYSZ_INS_CFEBRA = SYSTEMZ_INS_CFEBRA, + SYSZ_INS_CFER = SYSTEMZ_INS_CFER, + SYSZ_INS_CFI = SYSTEMZ_INS_CFI, + SYSZ_INS_CFXBR = SYSTEMZ_INS_CFXBR, + SYSZ_INS_CFXBRA = SYSTEMZ_INS_CFXBRA, + SYSZ_INS_CFXR = SYSTEMZ_INS_CFXR, + SYSZ_INS_CFXTR = SYSTEMZ_INS_CFXTR, + SYSZ_INS_CG = SYSTEMZ_INS_CG, + SYSZ_INS_CGDBR = SYSTEMZ_INS_CGDBR, + SYSZ_INS_CGDBRA = SYSTEMZ_INS_CGDBRA, + SYSZ_INS_CGDR = SYSTEMZ_INS_CGDR, + SYSZ_INS_CGDTR = SYSTEMZ_INS_CGDTR, + SYSZ_INS_CGDTRA = SYSTEMZ_INS_CGDTRA, + SYSZ_INS_CGEBR = SYSTEMZ_INS_CGEBR, + SYSZ_INS_CGEBRA = SYSTEMZ_INS_CGEBRA, + SYSZ_INS_CGER = SYSTEMZ_INS_CGER, + SYSZ_INS_CGF = SYSTEMZ_INS_CGF, + SYSZ_INS_CGFI = SYSTEMZ_INS_CGFI, + SYSZ_INS_CGFR = SYSTEMZ_INS_CGFR, + SYSZ_INS_CGFRL = SYSTEMZ_INS_CGFRL, + SYSZ_INS_CGH = SYSTEMZ_INS_CGH, + SYSZ_INS_CGHI = SYSTEMZ_INS_CGHI, + SYSZ_INS_CGHRL = SYSTEMZ_INS_CGHRL, + SYSZ_INS_CGHSI = SYSTEMZ_INS_CGHSI, + SYSZ_INS_CGIB = SYSTEMZ_INS_CGIB, + SYSZ_INS_CGIBE = SYSTEMZ_INS_CGIBE, + SYSZ_INS_CGIBH = SYSTEMZ_INS_CGIBH, + SYSZ_INS_CGIBHE = SYSTEMZ_INS_CGIBHE, + SYSZ_INS_CGIBL = SYSTEMZ_INS_CGIBL, + SYSZ_INS_CGIBLE = SYSTEMZ_INS_CGIBLE, + SYSZ_INS_CGIBLH = SYSTEMZ_INS_CGIBLH, + SYSZ_INS_CGIBNE = SYSTEMZ_INS_CGIBNE, + SYSZ_INS_CGIBNH = SYSTEMZ_INS_CGIBNH, + SYSZ_INS_CGIBNHE = SYSTEMZ_INS_CGIBNHE, + SYSZ_INS_CGIBNL = SYSTEMZ_INS_CGIBNL, + SYSZ_INS_CGIBNLE = SYSTEMZ_INS_CGIBNLE, + SYSZ_INS_CGIBNLH = SYSTEMZ_INS_CGIBNLH, + SYSZ_INS_CGIJ = SYSTEMZ_INS_CGIJ, + SYSZ_INS_CGIJE = SYSTEMZ_INS_CGIJE, + SYSZ_INS_CGIJH = SYSTEMZ_INS_CGIJH, + SYSZ_INS_CGIJHE = SYSTEMZ_INS_CGIJHE, + SYSZ_INS_CGIJL = SYSTEMZ_INS_CGIJL, + SYSZ_INS_CGIJLE = SYSTEMZ_INS_CGIJLE, + SYSZ_INS_CGIJLH = SYSTEMZ_INS_CGIJLH, + SYSZ_INS_CGIJNE = SYSTEMZ_INS_CGIJNE, + SYSZ_INS_CGIJNH = SYSTEMZ_INS_CGIJNH, + SYSZ_INS_CGIJNHE = SYSTEMZ_INS_CGIJNHE, + SYSZ_INS_CGIJNL = SYSTEMZ_INS_CGIJNL, + SYSZ_INS_CGIJNLE = SYSTEMZ_INS_CGIJNLE, + SYSZ_INS_CGIJNLH = SYSTEMZ_INS_CGIJNLH, + SYSZ_INS_CGIT = SYSTEMZ_INS_CGIT, + SYSZ_INS_CGITE = SYSTEMZ_INS_CGITE, + SYSZ_INS_CGITH = SYSTEMZ_INS_CGITH, + SYSZ_INS_CGITHE = SYSTEMZ_INS_CGITHE, + SYSZ_INS_CGITL = SYSTEMZ_INS_CGITL, + SYSZ_INS_CGITLE = SYSTEMZ_INS_CGITLE, + SYSZ_INS_CGITLH = SYSTEMZ_INS_CGITLH, + SYSZ_INS_CGITNE = SYSTEMZ_INS_CGITNE, + SYSZ_INS_CGITNH = SYSTEMZ_INS_CGITNH, + SYSZ_INS_CGITNHE = SYSTEMZ_INS_CGITNHE, + SYSZ_INS_CGITNL = SYSTEMZ_INS_CGITNL, + SYSZ_INS_CGITNLE = SYSTEMZ_INS_CGITNLE, + SYSZ_INS_CGITNLH = SYSTEMZ_INS_CGITNLH, + SYSZ_INS_CGR = SYSTEMZ_INS_CGR, + SYSZ_INS_CGRB = SYSTEMZ_INS_CGRB, + SYSZ_INS_CGRBE = SYSTEMZ_INS_CGRBE, + SYSZ_INS_CGRBH = SYSTEMZ_INS_CGRBH, + SYSZ_INS_CGRBHE = SYSTEMZ_INS_CGRBHE, + SYSZ_INS_CGRBL = SYSTEMZ_INS_CGRBL, + SYSZ_INS_CGRBLE = SYSTEMZ_INS_CGRBLE, + SYSZ_INS_CGRBLH = SYSTEMZ_INS_CGRBLH, + SYSZ_INS_CGRBNE = SYSTEMZ_INS_CGRBNE, + SYSZ_INS_CGRBNH = SYSTEMZ_INS_CGRBNH, + SYSZ_INS_CGRBNHE = SYSTEMZ_INS_CGRBNHE, + SYSZ_INS_CGRBNL = SYSTEMZ_INS_CGRBNL, + SYSZ_INS_CGRBNLE = SYSTEMZ_INS_CGRBNLE, + SYSZ_INS_CGRBNLH = SYSTEMZ_INS_CGRBNLH, + SYSZ_INS_CGRJ = SYSTEMZ_INS_CGRJ, + SYSZ_INS_CGRJE = SYSTEMZ_INS_CGRJE, + SYSZ_INS_CGRJH = SYSTEMZ_INS_CGRJH, + SYSZ_INS_CGRJHE = SYSTEMZ_INS_CGRJHE, + SYSZ_INS_CGRJL = SYSTEMZ_INS_CGRJL, + SYSZ_INS_CGRJLE = SYSTEMZ_INS_CGRJLE, + SYSZ_INS_CGRJLH = SYSTEMZ_INS_CGRJLH, + SYSZ_INS_CGRJNE = SYSTEMZ_INS_CGRJNE, + SYSZ_INS_CGRJNH = SYSTEMZ_INS_CGRJNH, + SYSZ_INS_CGRJNHE = SYSTEMZ_INS_CGRJNHE, + SYSZ_INS_CGRJNL = SYSTEMZ_INS_CGRJNL, + SYSZ_INS_CGRJNLE = SYSTEMZ_INS_CGRJNLE, + SYSZ_INS_CGRJNLH = SYSTEMZ_INS_CGRJNLH, + SYSZ_INS_CGRL = SYSTEMZ_INS_CGRL, + SYSZ_INS_CGRT = SYSTEMZ_INS_CGRT, + SYSZ_INS_CGRTE = SYSTEMZ_INS_CGRTE, + SYSZ_INS_CGRTH = SYSTEMZ_INS_CGRTH, + SYSZ_INS_CGRTHE = SYSTEMZ_INS_CGRTHE, + SYSZ_INS_CGRTL = SYSTEMZ_INS_CGRTL, + SYSZ_INS_CGRTLE = SYSTEMZ_INS_CGRTLE, + SYSZ_INS_CGRTLH = SYSTEMZ_INS_CGRTLH, + SYSZ_INS_CGRTNE = SYSTEMZ_INS_CGRTNE, + SYSZ_INS_CGRTNH = SYSTEMZ_INS_CGRTNH, + SYSZ_INS_CGRTNHE = SYSTEMZ_INS_CGRTNHE, + SYSZ_INS_CGRTNL = SYSTEMZ_INS_CGRTNL, + SYSZ_INS_CGRTNLE = SYSTEMZ_INS_CGRTNLE, + SYSZ_INS_CGRTNLH = SYSTEMZ_INS_CGRTNLH, + SYSZ_INS_CGXBR = SYSTEMZ_INS_CGXBR, + SYSZ_INS_CGXBRA = SYSTEMZ_INS_CGXBRA, + SYSZ_INS_CGXR = SYSTEMZ_INS_CGXR, + SYSZ_INS_CGXTR = SYSTEMZ_INS_CGXTR, + SYSZ_INS_CGXTRA = SYSTEMZ_INS_CGXTRA, + SYSZ_INS_CH = SYSTEMZ_INS_CH, + SYSZ_INS_CHF = SYSTEMZ_INS_CHF, + SYSZ_INS_CHHR = SYSTEMZ_INS_CHHR, + SYSZ_INS_CHHSI = SYSTEMZ_INS_CHHSI, + SYSZ_INS_CHI = SYSTEMZ_INS_CHI, + SYSZ_INS_CHLR = SYSTEMZ_INS_CHLR, + SYSZ_INS_CHRL = SYSTEMZ_INS_CHRL, + SYSZ_INS_CHSI = SYSTEMZ_INS_CHSI, + SYSZ_INS_CHY = SYSTEMZ_INS_CHY, + SYSZ_INS_CIB = SYSTEMZ_INS_CIB, + SYSZ_INS_CIBE = SYSTEMZ_INS_CIBE, + SYSZ_INS_CIBH = SYSTEMZ_INS_CIBH, + SYSZ_INS_CIBHE = SYSTEMZ_INS_CIBHE, + SYSZ_INS_CIBL = SYSTEMZ_INS_CIBL, + SYSZ_INS_CIBLE = SYSTEMZ_INS_CIBLE, + SYSZ_INS_CIBLH = SYSTEMZ_INS_CIBLH, + SYSZ_INS_CIBNE = SYSTEMZ_INS_CIBNE, + SYSZ_INS_CIBNH = SYSTEMZ_INS_CIBNH, + SYSZ_INS_CIBNHE = SYSTEMZ_INS_CIBNHE, + SYSZ_INS_CIBNL = SYSTEMZ_INS_CIBNL, + SYSZ_INS_CIBNLE = SYSTEMZ_INS_CIBNLE, + SYSZ_INS_CIBNLH = SYSTEMZ_INS_CIBNLH, + SYSZ_INS_CIH = SYSTEMZ_INS_CIH, + SYSZ_INS_CIJ = SYSTEMZ_INS_CIJ, + SYSZ_INS_CIJE = SYSTEMZ_INS_CIJE, + SYSZ_INS_CIJH = SYSTEMZ_INS_CIJH, + SYSZ_INS_CIJHE = SYSTEMZ_INS_CIJHE, + SYSZ_INS_CIJL = SYSTEMZ_INS_CIJL, + SYSZ_INS_CIJLE = SYSTEMZ_INS_CIJLE, + SYSZ_INS_CIJLH = SYSTEMZ_INS_CIJLH, + SYSZ_INS_CIJNE = SYSTEMZ_INS_CIJNE, + SYSZ_INS_CIJNH = SYSTEMZ_INS_CIJNH, + SYSZ_INS_CIJNHE = SYSTEMZ_INS_CIJNHE, + SYSZ_INS_CIJNL = SYSTEMZ_INS_CIJNL, + SYSZ_INS_CIJNLE = SYSTEMZ_INS_CIJNLE, + SYSZ_INS_CIJNLH = SYSTEMZ_INS_CIJNLH, + SYSZ_INS_CIT = SYSTEMZ_INS_CIT, + SYSZ_INS_CITE = SYSTEMZ_INS_CITE, + SYSZ_INS_CITH = SYSTEMZ_INS_CITH, + SYSZ_INS_CITHE = SYSTEMZ_INS_CITHE, + SYSZ_INS_CITL = SYSTEMZ_INS_CITL, + SYSZ_INS_CITLE = SYSTEMZ_INS_CITLE, + SYSZ_INS_CITLH = SYSTEMZ_INS_CITLH, + SYSZ_INS_CITNE = SYSTEMZ_INS_CITNE, + SYSZ_INS_CITNH = SYSTEMZ_INS_CITNH, + SYSZ_INS_CITNHE = SYSTEMZ_INS_CITNHE, + SYSZ_INS_CITNL = SYSTEMZ_INS_CITNL, + SYSZ_INS_CITNLE = SYSTEMZ_INS_CITNLE, + SYSZ_INS_CITNLH = SYSTEMZ_INS_CITNLH, + SYSZ_INS_CKSM = SYSTEMZ_INS_CKSM, + SYSZ_INS_CL = SYSTEMZ_INS_CL, + SYSZ_INS_CLC = SYSTEMZ_INS_CLC, + SYSZ_INS_CLCL = SYSTEMZ_INS_CLCL, + SYSZ_INS_CLCLE = SYSTEMZ_INS_CLCLE, + SYSZ_INS_CLCLU = SYSTEMZ_INS_CLCLU, + SYSZ_INS_CLFDBR = SYSTEMZ_INS_CLFDBR, + SYSZ_INS_CLFDTR = SYSTEMZ_INS_CLFDTR, + SYSZ_INS_CLFEBR = SYSTEMZ_INS_CLFEBR, + SYSZ_INS_CLFHSI = SYSTEMZ_INS_CLFHSI, + SYSZ_INS_CLFI = SYSTEMZ_INS_CLFI, + SYSZ_INS_CLFIT = SYSTEMZ_INS_CLFIT, + SYSZ_INS_CLFITE = SYSTEMZ_INS_CLFITE, + SYSZ_INS_CLFITH = SYSTEMZ_INS_CLFITH, + SYSZ_INS_CLFITHE = SYSTEMZ_INS_CLFITHE, + SYSZ_INS_CLFITL = SYSTEMZ_INS_CLFITL, + SYSZ_INS_CLFITLE = SYSTEMZ_INS_CLFITLE, + SYSZ_INS_CLFITLH = SYSTEMZ_INS_CLFITLH, + SYSZ_INS_CLFITNE = SYSTEMZ_INS_CLFITNE, + SYSZ_INS_CLFITNH = SYSTEMZ_INS_CLFITNH, + SYSZ_INS_CLFITNHE = SYSTEMZ_INS_CLFITNHE, + SYSZ_INS_CLFITNL = SYSTEMZ_INS_CLFITNL, + SYSZ_INS_CLFITNLE = SYSTEMZ_INS_CLFITNLE, + SYSZ_INS_CLFITNLH = SYSTEMZ_INS_CLFITNLH, + SYSZ_INS_CLFXBR = SYSTEMZ_INS_CLFXBR, + SYSZ_INS_CLFXTR = SYSTEMZ_INS_CLFXTR, + SYSZ_INS_CLG = SYSTEMZ_INS_CLG, + SYSZ_INS_CLGDBR = SYSTEMZ_INS_CLGDBR, + SYSZ_INS_CLGDTR = SYSTEMZ_INS_CLGDTR, + SYSZ_INS_CLGEBR = SYSTEMZ_INS_CLGEBR, + SYSZ_INS_CLGF = SYSTEMZ_INS_CLGF, + SYSZ_INS_CLGFI = SYSTEMZ_INS_CLGFI, + SYSZ_INS_CLGFR = SYSTEMZ_INS_CLGFR, + SYSZ_INS_CLGFRL = SYSTEMZ_INS_CLGFRL, + SYSZ_INS_CLGHRL = SYSTEMZ_INS_CLGHRL, + SYSZ_INS_CLGHSI = SYSTEMZ_INS_CLGHSI, + SYSZ_INS_CLGIB = SYSTEMZ_INS_CLGIB, + SYSZ_INS_CLGIBE = SYSTEMZ_INS_CLGIBE, + SYSZ_INS_CLGIBH = SYSTEMZ_INS_CLGIBH, + SYSZ_INS_CLGIBHE = SYSTEMZ_INS_CLGIBHE, + SYSZ_INS_CLGIBL = SYSTEMZ_INS_CLGIBL, + SYSZ_INS_CLGIBLE = SYSTEMZ_INS_CLGIBLE, + SYSZ_INS_CLGIBLH = SYSTEMZ_INS_CLGIBLH, + SYSZ_INS_CLGIBNE = SYSTEMZ_INS_CLGIBNE, + SYSZ_INS_CLGIBNH = SYSTEMZ_INS_CLGIBNH, + SYSZ_INS_CLGIBNHE = SYSTEMZ_INS_CLGIBNHE, + SYSZ_INS_CLGIBNL = SYSTEMZ_INS_CLGIBNL, + SYSZ_INS_CLGIBNLE = SYSTEMZ_INS_CLGIBNLE, + SYSZ_INS_CLGIBNLH = SYSTEMZ_INS_CLGIBNLH, + SYSZ_INS_CLGIJ = SYSTEMZ_INS_CLGIJ, + SYSZ_INS_CLGIJE = SYSTEMZ_INS_CLGIJE, + SYSZ_INS_CLGIJH = SYSTEMZ_INS_CLGIJH, + SYSZ_INS_CLGIJHE = SYSTEMZ_INS_CLGIJHE, + SYSZ_INS_CLGIJL = SYSTEMZ_INS_CLGIJL, + SYSZ_INS_CLGIJLE = SYSTEMZ_INS_CLGIJLE, + SYSZ_INS_CLGIJLH = SYSTEMZ_INS_CLGIJLH, + SYSZ_INS_CLGIJNE = SYSTEMZ_INS_CLGIJNE, + SYSZ_INS_CLGIJNH = SYSTEMZ_INS_CLGIJNH, + SYSZ_INS_CLGIJNHE = SYSTEMZ_INS_CLGIJNHE, + SYSZ_INS_CLGIJNL = SYSTEMZ_INS_CLGIJNL, + SYSZ_INS_CLGIJNLE = SYSTEMZ_INS_CLGIJNLE, + SYSZ_INS_CLGIJNLH = SYSTEMZ_INS_CLGIJNLH, + SYSZ_INS_CLGIT = SYSTEMZ_INS_CLGIT, + SYSZ_INS_CLGITE = SYSTEMZ_INS_CLGITE, + SYSZ_INS_CLGITH = SYSTEMZ_INS_CLGITH, + SYSZ_INS_CLGITHE = SYSTEMZ_INS_CLGITHE, + SYSZ_INS_CLGITL = SYSTEMZ_INS_CLGITL, + SYSZ_INS_CLGITLE = SYSTEMZ_INS_CLGITLE, + SYSZ_INS_CLGITLH = SYSTEMZ_INS_CLGITLH, + SYSZ_INS_CLGITNE = SYSTEMZ_INS_CLGITNE, + SYSZ_INS_CLGITNH = SYSTEMZ_INS_CLGITNH, + SYSZ_INS_CLGITNHE = SYSTEMZ_INS_CLGITNHE, + SYSZ_INS_CLGITNL = SYSTEMZ_INS_CLGITNL, + SYSZ_INS_CLGITNLE = SYSTEMZ_INS_CLGITNLE, + SYSZ_INS_CLGITNLH = SYSTEMZ_INS_CLGITNLH, + SYSZ_INS_CLGR = SYSTEMZ_INS_CLGR, + SYSZ_INS_CLGRB = SYSTEMZ_INS_CLGRB, + SYSZ_INS_CLGRBE = SYSTEMZ_INS_CLGRBE, + SYSZ_INS_CLGRBH = SYSTEMZ_INS_CLGRBH, + SYSZ_INS_CLGRBHE = SYSTEMZ_INS_CLGRBHE, + SYSZ_INS_CLGRBL = SYSTEMZ_INS_CLGRBL, + SYSZ_INS_CLGRBLE = SYSTEMZ_INS_CLGRBLE, + SYSZ_INS_CLGRBLH = SYSTEMZ_INS_CLGRBLH, + SYSZ_INS_CLGRBNE = SYSTEMZ_INS_CLGRBNE, + SYSZ_INS_CLGRBNH = SYSTEMZ_INS_CLGRBNH, + SYSZ_INS_CLGRBNHE = SYSTEMZ_INS_CLGRBNHE, + SYSZ_INS_CLGRBNL = SYSTEMZ_INS_CLGRBNL, + SYSZ_INS_CLGRBNLE = SYSTEMZ_INS_CLGRBNLE, + SYSZ_INS_CLGRBNLH = SYSTEMZ_INS_CLGRBNLH, + SYSZ_INS_CLGRJ = SYSTEMZ_INS_CLGRJ, + SYSZ_INS_CLGRJE = SYSTEMZ_INS_CLGRJE, + SYSZ_INS_CLGRJH = SYSTEMZ_INS_CLGRJH, + SYSZ_INS_CLGRJHE = SYSTEMZ_INS_CLGRJHE, + SYSZ_INS_CLGRJL = SYSTEMZ_INS_CLGRJL, + SYSZ_INS_CLGRJLE = SYSTEMZ_INS_CLGRJLE, + SYSZ_INS_CLGRJLH = SYSTEMZ_INS_CLGRJLH, + SYSZ_INS_CLGRJNE = SYSTEMZ_INS_CLGRJNE, + SYSZ_INS_CLGRJNH = SYSTEMZ_INS_CLGRJNH, + SYSZ_INS_CLGRJNHE = SYSTEMZ_INS_CLGRJNHE, + SYSZ_INS_CLGRJNL = SYSTEMZ_INS_CLGRJNL, + SYSZ_INS_CLGRJNLE = SYSTEMZ_INS_CLGRJNLE, + SYSZ_INS_CLGRJNLH = SYSTEMZ_INS_CLGRJNLH, + SYSZ_INS_CLGRL = SYSTEMZ_INS_CLGRL, + SYSZ_INS_CLGRT = SYSTEMZ_INS_CLGRT, + SYSZ_INS_CLGRTE = SYSTEMZ_INS_CLGRTE, + SYSZ_INS_CLGRTH = SYSTEMZ_INS_CLGRTH, + SYSZ_INS_CLGRTHE = SYSTEMZ_INS_CLGRTHE, + SYSZ_INS_CLGRTL = SYSTEMZ_INS_CLGRTL, + SYSZ_INS_CLGRTLE = SYSTEMZ_INS_CLGRTLE, + SYSZ_INS_CLGRTLH = SYSTEMZ_INS_CLGRTLH, + SYSZ_INS_CLGRTNE = SYSTEMZ_INS_CLGRTNE, + SYSZ_INS_CLGRTNH = SYSTEMZ_INS_CLGRTNH, + SYSZ_INS_CLGRTNHE = SYSTEMZ_INS_CLGRTNHE, + SYSZ_INS_CLGRTNL = SYSTEMZ_INS_CLGRTNL, + SYSZ_INS_CLGRTNLE = SYSTEMZ_INS_CLGRTNLE, + SYSZ_INS_CLGRTNLH = SYSTEMZ_INS_CLGRTNLH, + SYSZ_INS_CLGT = SYSTEMZ_INS_CLGT, + SYSZ_INS_CLGTE = SYSTEMZ_INS_CLGTE, + SYSZ_INS_CLGTH = SYSTEMZ_INS_CLGTH, + SYSZ_INS_CLGTHE = SYSTEMZ_INS_CLGTHE, + SYSZ_INS_CLGTL = SYSTEMZ_INS_CLGTL, + SYSZ_INS_CLGTLE = SYSTEMZ_INS_CLGTLE, + SYSZ_INS_CLGTLH = SYSTEMZ_INS_CLGTLH, + SYSZ_INS_CLGTNE = SYSTEMZ_INS_CLGTNE, + SYSZ_INS_CLGTNH = SYSTEMZ_INS_CLGTNH, + SYSZ_INS_CLGTNHE = SYSTEMZ_INS_CLGTNHE, + SYSZ_INS_CLGTNL = SYSTEMZ_INS_CLGTNL, + SYSZ_INS_CLGTNLE = SYSTEMZ_INS_CLGTNLE, + SYSZ_INS_CLGTNLH = SYSTEMZ_INS_CLGTNLH, + SYSZ_INS_CLGXBR = SYSTEMZ_INS_CLGXBR, + SYSZ_INS_CLGXTR = SYSTEMZ_INS_CLGXTR, + SYSZ_INS_CLHF = SYSTEMZ_INS_CLHF, + SYSZ_INS_CLHHR = SYSTEMZ_INS_CLHHR, + SYSZ_INS_CLHHSI = SYSTEMZ_INS_CLHHSI, + SYSZ_INS_CLHLR = SYSTEMZ_INS_CLHLR, + SYSZ_INS_CLHRL = SYSTEMZ_INS_CLHRL, + SYSZ_INS_CLI = SYSTEMZ_INS_CLI, + SYSZ_INS_CLIB = SYSTEMZ_INS_CLIB, + SYSZ_INS_CLIBE = SYSTEMZ_INS_CLIBE, + SYSZ_INS_CLIBH = SYSTEMZ_INS_CLIBH, + SYSZ_INS_CLIBHE = SYSTEMZ_INS_CLIBHE, + SYSZ_INS_CLIBL = SYSTEMZ_INS_CLIBL, + SYSZ_INS_CLIBLE = SYSTEMZ_INS_CLIBLE, + SYSZ_INS_CLIBLH = SYSTEMZ_INS_CLIBLH, + SYSZ_INS_CLIBNE = SYSTEMZ_INS_CLIBNE, + SYSZ_INS_CLIBNH = SYSTEMZ_INS_CLIBNH, + SYSZ_INS_CLIBNHE = SYSTEMZ_INS_CLIBNHE, + SYSZ_INS_CLIBNL = SYSTEMZ_INS_CLIBNL, + SYSZ_INS_CLIBNLE = SYSTEMZ_INS_CLIBNLE, + SYSZ_INS_CLIBNLH = SYSTEMZ_INS_CLIBNLH, + SYSZ_INS_CLIH = SYSTEMZ_INS_CLIH, + SYSZ_INS_CLIJ = SYSTEMZ_INS_CLIJ, + SYSZ_INS_CLIJE = SYSTEMZ_INS_CLIJE, + SYSZ_INS_CLIJH = SYSTEMZ_INS_CLIJH, + SYSZ_INS_CLIJHE = SYSTEMZ_INS_CLIJHE, + SYSZ_INS_CLIJL = SYSTEMZ_INS_CLIJL, + SYSZ_INS_CLIJLE = SYSTEMZ_INS_CLIJLE, + SYSZ_INS_CLIJLH = SYSTEMZ_INS_CLIJLH, + SYSZ_INS_CLIJNE = SYSTEMZ_INS_CLIJNE, + SYSZ_INS_CLIJNH = SYSTEMZ_INS_CLIJNH, + SYSZ_INS_CLIJNHE = SYSTEMZ_INS_CLIJNHE, + SYSZ_INS_CLIJNL = SYSTEMZ_INS_CLIJNL, + SYSZ_INS_CLIJNLE = SYSTEMZ_INS_CLIJNLE, + SYSZ_INS_CLIJNLH = SYSTEMZ_INS_CLIJNLH, + SYSZ_INS_CLIY = SYSTEMZ_INS_CLIY, + SYSZ_INS_CLM = SYSTEMZ_INS_CLM, + SYSZ_INS_CLMH = SYSTEMZ_INS_CLMH, + SYSZ_INS_CLMY = SYSTEMZ_INS_CLMY, + SYSZ_INS_CLR = SYSTEMZ_INS_CLR, + SYSZ_INS_CLRB = SYSTEMZ_INS_CLRB, + SYSZ_INS_CLRBE = SYSTEMZ_INS_CLRBE, + SYSZ_INS_CLRBH = SYSTEMZ_INS_CLRBH, + SYSZ_INS_CLRBHE = SYSTEMZ_INS_CLRBHE, + SYSZ_INS_CLRBL = SYSTEMZ_INS_CLRBL, + SYSZ_INS_CLRBLE = SYSTEMZ_INS_CLRBLE, + SYSZ_INS_CLRBLH = SYSTEMZ_INS_CLRBLH, + SYSZ_INS_CLRBNE = SYSTEMZ_INS_CLRBNE, + SYSZ_INS_CLRBNH = SYSTEMZ_INS_CLRBNH, + SYSZ_INS_CLRBNHE = SYSTEMZ_INS_CLRBNHE, + SYSZ_INS_CLRBNL = SYSTEMZ_INS_CLRBNL, + SYSZ_INS_CLRBNLE = SYSTEMZ_INS_CLRBNLE, + SYSZ_INS_CLRBNLH = SYSTEMZ_INS_CLRBNLH, + SYSZ_INS_CLRJ = SYSTEMZ_INS_CLRJ, + SYSZ_INS_CLRJE = SYSTEMZ_INS_CLRJE, + SYSZ_INS_CLRJH = SYSTEMZ_INS_CLRJH, + SYSZ_INS_CLRJHE = SYSTEMZ_INS_CLRJHE, + SYSZ_INS_CLRJL = SYSTEMZ_INS_CLRJL, + SYSZ_INS_CLRJLE = SYSTEMZ_INS_CLRJLE, + SYSZ_INS_CLRJLH = SYSTEMZ_INS_CLRJLH, + SYSZ_INS_CLRJNE = SYSTEMZ_INS_CLRJNE, + SYSZ_INS_CLRJNH = SYSTEMZ_INS_CLRJNH, + SYSZ_INS_CLRJNHE = SYSTEMZ_INS_CLRJNHE, + SYSZ_INS_CLRJNL = SYSTEMZ_INS_CLRJNL, + SYSZ_INS_CLRJNLE = SYSTEMZ_INS_CLRJNLE, + SYSZ_INS_CLRJNLH = SYSTEMZ_INS_CLRJNLH, + SYSZ_INS_CLRL = SYSTEMZ_INS_CLRL, + SYSZ_INS_CLRT = SYSTEMZ_INS_CLRT, + SYSZ_INS_CLRTE = SYSTEMZ_INS_CLRTE, + SYSZ_INS_CLRTH = SYSTEMZ_INS_CLRTH, + SYSZ_INS_CLRTHE = SYSTEMZ_INS_CLRTHE, + SYSZ_INS_CLRTL = SYSTEMZ_INS_CLRTL, + SYSZ_INS_CLRTLE = SYSTEMZ_INS_CLRTLE, + SYSZ_INS_CLRTLH = SYSTEMZ_INS_CLRTLH, + SYSZ_INS_CLRTNE = SYSTEMZ_INS_CLRTNE, + SYSZ_INS_CLRTNH = SYSTEMZ_INS_CLRTNH, + SYSZ_INS_CLRTNHE = SYSTEMZ_INS_CLRTNHE, + SYSZ_INS_CLRTNL = SYSTEMZ_INS_CLRTNL, + SYSZ_INS_CLRTNLE = SYSTEMZ_INS_CLRTNLE, + SYSZ_INS_CLRTNLH = SYSTEMZ_INS_CLRTNLH, + SYSZ_INS_CLST = SYSTEMZ_INS_CLST, + SYSZ_INS_CLT = SYSTEMZ_INS_CLT, + SYSZ_INS_CLTE = SYSTEMZ_INS_CLTE, + SYSZ_INS_CLTH = SYSTEMZ_INS_CLTH, + SYSZ_INS_CLTHE = SYSTEMZ_INS_CLTHE, + SYSZ_INS_CLTL = SYSTEMZ_INS_CLTL, + SYSZ_INS_CLTLE = SYSTEMZ_INS_CLTLE, + SYSZ_INS_CLTLH = SYSTEMZ_INS_CLTLH, + SYSZ_INS_CLTNE = SYSTEMZ_INS_CLTNE, + SYSZ_INS_CLTNH = SYSTEMZ_INS_CLTNH, + SYSZ_INS_CLTNHE = SYSTEMZ_INS_CLTNHE, + SYSZ_INS_CLTNL = SYSTEMZ_INS_CLTNL, + SYSZ_INS_CLTNLE = SYSTEMZ_INS_CLTNLE, + SYSZ_INS_CLTNLH = SYSTEMZ_INS_CLTNLH, + SYSZ_INS_CLY = SYSTEMZ_INS_CLY, + SYSZ_INS_CMPSC = SYSTEMZ_INS_CMPSC, + SYSZ_INS_CP = SYSTEMZ_INS_CP, + SYSZ_INS_CPDT = SYSTEMZ_INS_CPDT, + SYSZ_INS_CPSDR = SYSTEMZ_INS_CPSDR, + SYSZ_INS_CPXT = SYSTEMZ_INS_CPXT, + SYSZ_INS_CPYA = SYSTEMZ_INS_CPYA, + SYSZ_INS_CR = SYSTEMZ_INS_CR, + SYSZ_INS_CRB = SYSTEMZ_INS_CRB, + SYSZ_INS_CRBE = SYSTEMZ_INS_CRBE, + SYSZ_INS_CRBH = SYSTEMZ_INS_CRBH, + SYSZ_INS_CRBHE = SYSTEMZ_INS_CRBHE, + SYSZ_INS_CRBL = SYSTEMZ_INS_CRBL, + SYSZ_INS_CRBLE = SYSTEMZ_INS_CRBLE, + SYSZ_INS_CRBLH = SYSTEMZ_INS_CRBLH, + SYSZ_INS_CRBNE = SYSTEMZ_INS_CRBNE, + SYSZ_INS_CRBNH = SYSTEMZ_INS_CRBNH, + SYSZ_INS_CRBNHE = SYSTEMZ_INS_CRBNHE, + SYSZ_INS_CRBNL = SYSTEMZ_INS_CRBNL, + SYSZ_INS_CRBNLE = SYSTEMZ_INS_CRBNLE, + SYSZ_INS_CRBNLH = SYSTEMZ_INS_CRBNLH, + SYSZ_INS_CRDTE = SYSTEMZ_INS_CRDTE, + SYSZ_INS_CRJ = SYSTEMZ_INS_CRJ, + SYSZ_INS_CRJE = SYSTEMZ_INS_CRJE, + SYSZ_INS_CRJH = SYSTEMZ_INS_CRJH, + SYSZ_INS_CRJHE = SYSTEMZ_INS_CRJHE, + SYSZ_INS_CRJL = SYSTEMZ_INS_CRJL, + SYSZ_INS_CRJLE = SYSTEMZ_INS_CRJLE, + SYSZ_INS_CRJLH = SYSTEMZ_INS_CRJLH, + SYSZ_INS_CRJNE = SYSTEMZ_INS_CRJNE, + SYSZ_INS_CRJNH = SYSTEMZ_INS_CRJNH, + SYSZ_INS_CRJNHE = SYSTEMZ_INS_CRJNHE, + SYSZ_INS_CRJNL = SYSTEMZ_INS_CRJNL, + SYSZ_INS_CRJNLE = SYSTEMZ_INS_CRJNLE, + SYSZ_INS_CRJNLH = SYSTEMZ_INS_CRJNLH, + SYSZ_INS_CRL = SYSTEMZ_INS_CRL, + SYSZ_INS_CRT = SYSTEMZ_INS_CRT, + SYSZ_INS_CRTE = SYSTEMZ_INS_CRTE, + SYSZ_INS_CRTH = SYSTEMZ_INS_CRTH, + SYSZ_INS_CRTHE = SYSTEMZ_INS_CRTHE, + SYSZ_INS_CRTL = SYSTEMZ_INS_CRTL, + SYSZ_INS_CRTLE = SYSTEMZ_INS_CRTLE, + SYSZ_INS_CRTLH = SYSTEMZ_INS_CRTLH, + SYSZ_INS_CRTNE = SYSTEMZ_INS_CRTNE, + SYSZ_INS_CRTNH = SYSTEMZ_INS_CRTNH, + SYSZ_INS_CRTNHE = SYSTEMZ_INS_CRTNHE, + SYSZ_INS_CRTNL = SYSTEMZ_INS_CRTNL, + SYSZ_INS_CRTNLE = SYSTEMZ_INS_CRTNLE, + SYSZ_INS_CRTNLH = SYSTEMZ_INS_CRTNLH, + SYSZ_INS_CS = SYSTEMZ_INS_CS, + SYSZ_INS_CSCH = SYSTEMZ_INS_CSCH, + SYSZ_INS_CSDTR = SYSTEMZ_INS_CSDTR, + SYSZ_INS_CSG = SYSTEMZ_INS_CSG, + SYSZ_INS_CSP = SYSTEMZ_INS_CSP, + SYSZ_INS_CSPG = SYSTEMZ_INS_CSPG, + SYSZ_INS_CSST = SYSTEMZ_INS_CSST, + SYSZ_INS_CSXTR = SYSTEMZ_INS_CSXTR, + SYSZ_INS_CSY = SYSTEMZ_INS_CSY, + SYSZ_INS_CU12 = SYSTEMZ_INS_CU12, + SYSZ_INS_CU14 = SYSTEMZ_INS_CU14, + SYSZ_INS_CU21 = SYSTEMZ_INS_CU21, + SYSZ_INS_CU24 = SYSTEMZ_INS_CU24, + SYSZ_INS_CU41 = SYSTEMZ_INS_CU41, + SYSZ_INS_CU42 = SYSTEMZ_INS_CU42, + SYSZ_INS_CUDTR = SYSTEMZ_INS_CUDTR, + SYSZ_INS_CUSE = SYSTEMZ_INS_CUSE, + SYSZ_INS_CUTFU = SYSTEMZ_INS_CUTFU, + SYSZ_INS_CUUTF = SYSTEMZ_INS_CUUTF, + SYSZ_INS_CUXTR = SYSTEMZ_INS_CUXTR, + SYSZ_INS_CVB = SYSTEMZ_INS_CVB, + SYSZ_INS_CVBG = SYSTEMZ_INS_CVBG, + SYSZ_INS_CVBY = SYSTEMZ_INS_CVBY, + SYSZ_INS_CVD = SYSTEMZ_INS_CVD, + SYSZ_INS_CVDG = SYSTEMZ_INS_CVDG, + SYSZ_INS_CVDY = SYSTEMZ_INS_CVDY, + SYSZ_INS_CXBR = SYSTEMZ_INS_CXBR, + SYSZ_INS_CXFBR = SYSTEMZ_INS_CXFBR, + SYSZ_INS_CXFBRA = SYSTEMZ_INS_CXFBRA, + SYSZ_INS_CXFR = SYSTEMZ_INS_CXFR, + SYSZ_INS_CXFTR = SYSTEMZ_INS_CXFTR, + SYSZ_INS_CXGBR = SYSTEMZ_INS_CXGBR, + SYSZ_INS_CXGBRA = SYSTEMZ_INS_CXGBRA, + SYSZ_INS_CXGR = SYSTEMZ_INS_CXGR, + SYSZ_INS_CXGTR = SYSTEMZ_INS_CXGTR, + SYSZ_INS_CXGTRA = SYSTEMZ_INS_CXGTRA, + SYSZ_INS_CXLFBR = SYSTEMZ_INS_CXLFBR, + SYSZ_INS_CXLFTR = SYSTEMZ_INS_CXLFTR, + SYSZ_INS_CXLGBR = SYSTEMZ_INS_CXLGBR, + SYSZ_INS_CXLGTR = SYSTEMZ_INS_CXLGTR, + SYSZ_INS_CXPT = SYSTEMZ_INS_CXPT, + SYSZ_INS_CXR = SYSTEMZ_INS_CXR, + SYSZ_INS_CXSTR = SYSTEMZ_INS_CXSTR, + SYSZ_INS_CXTR = SYSTEMZ_INS_CXTR, + SYSZ_INS_CXUTR = SYSTEMZ_INS_CXUTR, + SYSZ_INS_CXZT = SYSTEMZ_INS_CXZT, + SYSZ_INS_CY = SYSTEMZ_INS_CY, + SYSZ_INS_CZDT = SYSTEMZ_INS_CZDT, + SYSZ_INS_CZXT = SYSTEMZ_INS_CZXT, + SYSZ_INS_D = SYSTEMZ_INS_D, + SYSZ_INS_DD = SYSTEMZ_INS_DD, + SYSZ_INS_DDB = SYSTEMZ_INS_DDB, + SYSZ_INS_DDBR = SYSTEMZ_INS_DDBR, + SYSZ_INS_DDR = SYSTEMZ_INS_DDR, + SYSZ_INS_DDTR = SYSTEMZ_INS_DDTR, + SYSZ_INS_DDTRA = SYSTEMZ_INS_DDTRA, + SYSZ_INS_DE = SYSTEMZ_INS_DE, + SYSZ_INS_DEB = SYSTEMZ_INS_DEB, + SYSZ_INS_DEBR = SYSTEMZ_INS_DEBR, + SYSZ_INS_DER = SYSTEMZ_INS_DER, + SYSZ_INS_DFLTCC = SYSTEMZ_INS_DFLTCC, + SYSZ_INS_DIAG = SYSTEMZ_INS_DIAG, + SYSZ_INS_DIDBR = SYSTEMZ_INS_DIDBR, + SYSZ_INS_DIEBR = SYSTEMZ_INS_DIEBR, + SYSZ_INS_DL = SYSTEMZ_INS_DL, + SYSZ_INS_DLG = SYSTEMZ_INS_DLG, + SYSZ_INS_DLGR = SYSTEMZ_INS_DLGR, + SYSZ_INS_DLR = SYSTEMZ_INS_DLR, + SYSZ_INS_DP = SYSTEMZ_INS_DP, + SYSZ_INS_DR = SYSTEMZ_INS_DR, + SYSZ_INS_DSG = SYSTEMZ_INS_DSG, + SYSZ_INS_DSGF = SYSTEMZ_INS_DSGF, + SYSZ_INS_DSGFR = SYSTEMZ_INS_DSGFR, + SYSZ_INS_DSGR = SYSTEMZ_INS_DSGR, + SYSZ_INS_DXBR = SYSTEMZ_INS_DXBR, + SYSZ_INS_DXR = SYSTEMZ_INS_DXR, + SYSZ_INS_DXTR = SYSTEMZ_INS_DXTR, + SYSZ_INS_DXTRA = SYSTEMZ_INS_DXTRA, + SYSZ_INS_EAR = SYSTEMZ_INS_EAR, + SYSZ_INS_ECAG = SYSTEMZ_INS_ECAG, + SYSZ_INS_ECCTR = SYSTEMZ_INS_ECCTR, + SYSZ_INS_ECPGA = SYSTEMZ_INS_ECPGA, + SYSZ_INS_ECTG = SYSTEMZ_INS_ECTG, + SYSZ_INS_ED = SYSTEMZ_INS_ED, + SYSZ_INS_EDMK = SYSTEMZ_INS_EDMK, + SYSZ_INS_EEDTR = SYSTEMZ_INS_EEDTR, + SYSZ_INS_EEXTR = SYSTEMZ_INS_EEXTR, + SYSZ_INS_EFPC = SYSTEMZ_INS_EFPC, + SYSZ_INS_EPAIR = SYSTEMZ_INS_EPAIR, + SYSZ_INS_EPAR = SYSTEMZ_INS_EPAR, + SYSZ_INS_EPCTR = SYSTEMZ_INS_EPCTR, + SYSZ_INS_EPSW = SYSTEMZ_INS_EPSW, + SYSZ_INS_EREG = SYSTEMZ_INS_EREG, + SYSZ_INS_EREGG = SYSTEMZ_INS_EREGG, + SYSZ_INS_ESAIR = SYSTEMZ_INS_ESAIR, + SYSZ_INS_ESAR = SYSTEMZ_INS_ESAR, + SYSZ_INS_ESDTR = SYSTEMZ_INS_ESDTR, + SYSZ_INS_ESEA = SYSTEMZ_INS_ESEA, + SYSZ_INS_ESTA = SYSTEMZ_INS_ESTA, + SYSZ_INS_ESXTR = SYSTEMZ_INS_ESXTR, + SYSZ_INS_ETND = SYSTEMZ_INS_ETND, + SYSZ_INS_EX = SYSTEMZ_INS_EX, + SYSZ_INS_EXRL = SYSTEMZ_INS_EXRL, + SYSZ_INS_FIDBR = SYSTEMZ_INS_FIDBR, + SYSZ_INS_FIDBRA = SYSTEMZ_INS_FIDBRA, + SYSZ_INS_FIDR = SYSTEMZ_INS_FIDR, + SYSZ_INS_FIDTR = SYSTEMZ_INS_FIDTR, + SYSZ_INS_FIEBR = SYSTEMZ_INS_FIEBR, + SYSZ_INS_FIEBRA = SYSTEMZ_INS_FIEBRA, + SYSZ_INS_FIER = SYSTEMZ_INS_FIER, + SYSZ_INS_FIXBR = SYSTEMZ_INS_FIXBR, + SYSZ_INS_FIXBRA = SYSTEMZ_INS_FIXBRA, + SYSZ_INS_FIXR = SYSTEMZ_INS_FIXR, + SYSZ_INS_FIXTR = SYSTEMZ_INS_FIXTR, + SYSZ_INS_FLOGR = SYSTEMZ_INS_FLOGR, + SYSZ_INS_HDR = SYSTEMZ_INS_HDR, + SYSZ_INS_HER = SYSTEMZ_INS_HER, + SYSZ_INS_HSCH = SYSTEMZ_INS_HSCH, + SYSZ_INS_IAC = SYSTEMZ_INS_IAC, + SYSZ_INS_IC = SYSTEMZ_INS_IC, + SYSZ_INS_ICM = SYSTEMZ_INS_ICM, + SYSZ_INS_ICMH = SYSTEMZ_INS_ICMH, + SYSZ_INS_ICMY = SYSTEMZ_INS_ICMY, + SYSZ_INS_ICY = SYSTEMZ_INS_ICY, + SYSZ_INS_IDTE = SYSTEMZ_INS_IDTE, + SYSZ_INS_IEDTR = SYSTEMZ_INS_IEDTR, + SYSZ_INS_IEXTR = SYSTEMZ_INS_IEXTR, + SYSZ_INS_IIHF = SYSTEMZ_INS_IIHF, + SYSZ_INS_IIHH = SYSTEMZ_INS_IIHH, + SYSZ_INS_IIHL = SYSTEMZ_INS_IIHL, + SYSZ_INS_IILF = SYSTEMZ_INS_IILF, + SYSZ_INS_IILH = SYSTEMZ_INS_IILH, + SYSZ_INS_IILL = SYSTEMZ_INS_IILL, + SYSZ_INS_IPK = SYSTEMZ_INS_IPK, + SYSZ_INS_IPM = SYSTEMZ_INS_IPM, + SYSZ_INS_IPTE = SYSTEMZ_INS_IPTE, + SYSZ_INS_IRBM = SYSTEMZ_INS_IRBM, + SYSZ_INS_ISKE = SYSTEMZ_INS_ISKE, + SYSZ_INS_IVSK = SYSTEMZ_INS_IVSK, + SYSZ_INS_J = SYSTEMZ_INS_J, + SYSZ_INS_JE = SYSTEMZ_INS_JE, + SYSZ_INS_JH = SYSTEMZ_INS_JH, + SYSZ_INS_JHE = SYSTEMZ_INS_JHE, + SYSZ_INS_JL = SYSTEMZ_INS_JL, + SYSZ_INS_JLE = SYSTEMZ_INS_JLE, + SYSZ_INS_JLH = SYSTEMZ_INS_JLH, + SYSZ_INS_JM = SYSTEMZ_INS_JM, + SYSZ_INS_JNE = SYSTEMZ_INS_JNE, + SYSZ_INS_JNH = SYSTEMZ_INS_JNH, + SYSZ_INS_JNHE = SYSTEMZ_INS_JNHE, + SYSZ_INS_JNL = SYSTEMZ_INS_JNL, + SYSZ_INS_JNLE = SYSTEMZ_INS_JNLE, + SYSZ_INS_JNLH = SYSTEMZ_INS_JNLH, + SYSZ_INS_JNM = SYSTEMZ_INS_JNM, + SYSZ_INS_JNO = SYSTEMZ_INS_JNO, + SYSZ_INS_JNP = SYSTEMZ_INS_JNP, + SYSZ_INS_JNZ = SYSTEMZ_INS_JNZ, + SYSZ_INS_JO = SYSTEMZ_INS_JO, + SYSZ_INS_JP = SYSTEMZ_INS_JP, + SYSZ_INS_JZ = SYSTEMZ_INS_JZ, + SYSZ_INS_J_G_LU_ = SYSTEMZ_INS_J_G_LU_, + SYSZ_INS_J_G_L_E = SYSTEMZ_INS_J_G_L_E, + SYSZ_INS_J_G_L_H = SYSTEMZ_INS_J_G_L_H, + SYSZ_INS_J_G_L_HE = SYSTEMZ_INS_J_G_L_HE, + SYSZ_INS_J_G_L_L = SYSTEMZ_INS_J_G_L_L, + SYSZ_INS_J_G_L_LE = SYSTEMZ_INS_J_G_L_LE, + SYSZ_INS_J_G_L_LH = SYSTEMZ_INS_J_G_L_LH, + SYSZ_INS_J_G_L_M = SYSTEMZ_INS_J_G_L_M, + SYSZ_INS_J_G_L_NE = SYSTEMZ_INS_J_G_L_NE, + SYSZ_INS_J_G_L_NH = SYSTEMZ_INS_J_G_L_NH, + SYSZ_INS_J_G_L_NHE = SYSTEMZ_INS_J_G_L_NHE, + SYSZ_INS_J_G_L_NL = SYSTEMZ_INS_J_G_L_NL, + SYSZ_INS_J_G_L_NLE = SYSTEMZ_INS_J_G_L_NLE, + SYSZ_INS_J_G_L_NLH = SYSTEMZ_INS_J_G_L_NLH, + SYSZ_INS_J_G_L_NM = SYSTEMZ_INS_J_G_L_NM, + SYSZ_INS_J_G_L_NO = SYSTEMZ_INS_J_G_L_NO, + SYSZ_INS_J_G_L_NP = SYSTEMZ_INS_J_G_L_NP, + SYSZ_INS_J_G_L_NZ = SYSTEMZ_INS_J_G_L_NZ, + SYSZ_INS_J_G_L_O = SYSTEMZ_INS_J_G_L_O, + SYSZ_INS_J_G_L_P = SYSTEMZ_INS_J_G_L_P, + SYSZ_INS_J_G_L_Z = SYSTEMZ_INS_J_G_L_Z, + SYSZ_INS_KDB = SYSTEMZ_INS_KDB, + SYSZ_INS_KDBR = SYSTEMZ_INS_KDBR, + SYSZ_INS_KDSA = SYSTEMZ_INS_KDSA, + SYSZ_INS_KDTR = SYSTEMZ_INS_KDTR, + SYSZ_INS_KEB = SYSTEMZ_INS_KEB, + SYSZ_INS_KEBR = SYSTEMZ_INS_KEBR, + SYSZ_INS_KIMD = SYSTEMZ_INS_KIMD, + SYSZ_INS_KLMD = SYSTEMZ_INS_KLMD, + SYSZ_INS_KM = SYSTEMZ_INS_KM, + SYSZ_INS_KMA = SYSTEMZ_INS_KMA, + SYSZ_INS_KMAC = SYSTEMZ_INS_KMAC, + SYSZ_INS_KMC = SYSTEMZ_INS_KMC, + SYSZ_INS_KMCTR = SYSTEMZ_INS_KMCTR, + SYSZ_INS_KMF = SYSTEMZ_INS_KMF, + SYSZ_INS_KMO = SYSTEMZ_INS_KMO, + SYSZ_INS_KXBR = SYSTEMZ_INS_KXBR, + SYSZ_INS_KXTR = SYSTEMZ_INS_KXTR, + SYSZ_INS_L = SYSTEMZ_INS_L, + SYSZ_INS_LA = SYSTEMZ_INS_LA, + SYSZ_INS_LAA = SYSTEMZ_INS_LAA, + SYSZ_INS_LAAG = SYSTEMZ_INS_LAAG, + SYSZ_INS_LAAL = SYSTEMZ_INS_LAAL, + SYSZ_INS_LAALG = SYSTEMZ_INS_LAALG, + SYSZ_INS_LAE = SYSTEMZ_INS_LAE, + SYSZ_INS_LAEY = SYSTEMZ_INS_LAEY, + SYSZ_INS_LAM = SYSTEMZ_INS_LAM, + SYSZ_INS_LAMY = SYSTEMZ_INS_LAMY, + SYSZ_INS_LAN = SYSTEMZ_INS_LAN, + SYSZ_INS_LANG = SYSTEMZ_INS_LANG, + SYSZ_INS_LAO = SYSTEMZ_INS_LAO, + SYSZ_INS_LAOG = SYSTEMZ_INS_LAOG, + SYSZ_INS_LARL = SYSTEMZ_INS_LARL, + SYSZ_INS_LASP = SYSTEMZ_INS_LASP, + SYSZ_INS_LAT = SYSTEMZ_INS_LAT, + SYSZ_INS_LAX = SYSTEMZ_INS_LAX, + SYSZ_INS_LAXG = SYSTEMZ_INS_LAXG, + SYSZ_INS_LAY = SYSTEMZ_INS_LAY, + SYSZ_INS_LB = SYSTEMZ_INS_LB, + SYSZ_INS_LBEAR = SYSTEMZ_INS_LBEAR, + SYSZ_INS_LBH = SYSTEMZ_INS_LBH, + SYSZ_INS_LBR = SYSTEMZ_INS_LBR, + SYSZ_INS_LCBB = SYSTEMZ_INS_LCBB, + SYSZ_INS_LCCTL = SYSTEMZ_INS_LCCTL, + SYSZ_INS_LCDBR = SYSTEMZ_INS_LCDBR, + SYSZ_INS_LCDFR = SYSTEMZ_INS_LCDFR, + SYSZ_INS_LCDR = SYSTEMZ_INS_LCDR, + SYSZ_INS_LCEBR = SYSTEMZ_INS_LCEBR, + SYSZ_INS_LCER = SYSTEMZ_INS_LCER, + SYSZ_INS_LCGFR = SYSTEMZ_INS_LCGFR, + SYSZ_INS_LCGR = SYSTEMZ_INS_LCGR, + SYSZ_INS_LCR = SYSTEMZ_INS_LCR, + SYSZ_INS_LCTL = SYSTEMZ_INS_LCTL, + SYSZ_INS_LCTLG = SYSTEMZ_INS_LCTLG, + SYSZ_INS_LCXBR = SYSTEMZ_INS_LCXBR, + SYSZ_INS_LCXR = SYSTEMZ_INS_LCXR, + SYSZ_INS_LD = SYSTEMZ_INS_LD, + SYSZ_INS_LDE = SYSTEMZ_INS_LDE, + SYSZ_INS_LDEB = SYSTEMZ_INS_LDEB, + SYSZ_INS_LDEBR = SYSTEMZ_INS_LDEBR, + SYSZ_INS_LDER = SYSTEMZ_INS_LDER, + SYSZ_INS_LDETR = SYSTEMZ_INS_LDETR, + SYSZ_INS_LDGR = SYSTEMZ_INS_LDGR, + SYSZ_INS_LDR = SYSTEMZ_INS_LDR, + SYSZ_INS_LDXBR = SYSTEMZ_INS_LDXBR, + SYSZ_INS_LDXBRA = SYSTEMZ_INS_LDXBRA, + SYSZ_INS_LDXR = SYSTEMZ_INS_LDXR, + SYSZ_INS_LDXTR = SYSTEMZ_INS_LDXTR, + SYSZ_INS_LDY = SYSTEMZ_INS_LDY, + SYSZ_INS_LE = SYSTEMZ_INS_LE, + SYSZ_INS_LEDBR = SYSTEMZ_INS_LEDBR, + SYSZ_INS_LEDBRA = SYSTEMZ_INS_LEDBRA, + SYSZ_INS_LEDR = SYSTEMZ_INS_LEDR, + SYSZ_INS_LEDTR = SYSTEMZ_INS_LEDTR, + SYSZ_INS_LER = SYSTEMZ_INS_LER, + SYSZ_INS_LEXBR = SYSTEMZ_INS_LEXBR, + SYSZ_INS_LEXBRA = SYSTEMZ_INS_LEXBRA, + SYSZ_INS_LEXR = SYSTEMZ_INS_LEXR, + SYSZ_INS_LEY = SYSTEMZ_INS_LEY, + SYSZ_INS_LFAS = SYSTEMZ_INS_LFAS, + SYSZ_INS_LFH = SYSTEMZ_INS_LFH, + SYSZ_INS_LFHAT = SYSTEMZ_INS_LFHAT, + SYSZ_INS_LFPC = SYSTEMZ_INS_LFPC, + SYSZ_INS_LG = SYSTEMZ_INS_LG, + SYSZ_INS_LGAT = SYSTEMZ_INS_LGAT, + SYSZ_INS_LGB = SYSTEMZ_INS_LGB, + SYSZ_INS_LGBR = SYSTEMZ_INS_LGBR, + SYSZ_INS_LGDR = SYSTEMZ_INS_LGDR, + SYSZ_INS_LGF = SYSTEMZ_INS_LGF, + SYSZ_INS_LGFI = SYSTEMZ_INS_LGFI, + SYSZ_INS_LGFR = SYSTEMZ_INS_LGFR, + SYSZ_INS_LGFRL = SYSTEMZ_INS_LGFRL, + SYSZ_INS_LGG = SYSTEMZ_INS_LGG, + SYSZ_INS_LGH = SYSTEMZ_INS_LGH, + SYSZ_INS_LGHI = SYSTEMZ_INS_LGHI, + SYSZ_INS_LGHR = SYSTEMZ_INS_LGHR, + SYSZ_INS_LGHRL = SYSTEMZ_INS_LGHRL, + SYSZ_INS_LGR = SYSTEMZ_INS_LGR, + SYSZ_INS_LGRL = SYSTEMZ_INS_LGRL, + SYSZ_INS_LGSC = SYSTEMZ_INS_LGSC, + SYSZ_INS_LH = SYSTEMZ_INS_LH, + SYSZ_INS_LHH = SYSTEMZ_INS_LHH, + SYSZ_INS_LHI = SYSTEMZ_INS_LHI, + SYSZ_INS_LHR = SYSTEMZ_INS_LHR, + SYSZ_INS_LHRL = SYSTEMZ_INS_LHRL, + SYSZ_INS_LHY = SYSTEMZ_INS_LHY, + SYSZ_INS_LLC = SYSTEMZ_INS_LLC, + SYSZ_INS_LLCH = SYSTEMZ_INS_LLCH, + SYSZ_INS_LLCR = SYSTEMZ_INS_LLCR, + SYSZ_INS_LLGC = SYSTEMZ_INS_LLGC, + SYSZ_INS_LLGCR = SYSTEMZ_INS_LLGCR, + SYSZ_INS_LLGF = SYSTEMZ_INS_LLGF, + SYSZ_INS_LLGFAT = SYSTEMZ_INS_LLGFAT, + SYSZ_INS_LLGFR = SYSTEMZ_INS_LLGFR, + SYSZ_INS_LLGFRL = SYSTEMZ_INS_LLGFRL, + SYSZ_INS_LLGFSG = SYSTEMZ_INS_LLGFSG, + SYSZ_INS_LLGH = SYSTEMZ_INS_LLGH, + SYSZ_INS_LLGHR = SYSTEMZ_INS_LLGHR, + SYSZ_INS_LLGHRL = SYSTEMZ_INS_LLGHRL, + SYSZ_INS_LLGT = SYSTEMZ_INS_LLGT, + SYSZ_INS_LLGTAT = SYSTEMZ_INS_LLGTAT, + SYSZ_INS_LLGTR = SYSTEMZ_INS_LLGTR, + SYSZ_INS_LLH = SYSTEMZ_INS_LLH, + SYSZ_INS_LLHH = SYSTEMZ_INS_LLHH, + SYSZ_INS_LLHR = SYSTEMZ_INS_LLHR, + SYSZ_INS_LLHRL = SYSTEMZ_INS_LLHRL, + SYSZ_INS_LLIHF = SYSTEMZ_INS_LLIHF, + SYSZ_INS_LLIHH = SYSTEMZ_INS_LLIHH, + SYSZ_INS_LLIHL = SYSTEMZ_INS_LLIHL, + SYSZ_INS_LLILF = SYSTEMZ_INS_LLILF, + SYSZ_INS_LLILH = SYSTEMZ_INS_LLILH, + SYSZ_INS_LLILL = SYSTEMZ_INS_LLILL, + SYSZ_INS_LLZRGF = SYSTEMZ_INS_LLZRGF, + SYSZ_INS_LM = SYSTEMZ_INS_LM, + SYSZ_INS_LMD = SYSTEMZ_INS_LMD, + SYSZ_INS_LMG = SYSTEMZ_INS_LMG, + SYSZ_INS_LMH = SYSTEMZ_INS_LMH, + SYSZ_INS_LMY = SYSTEMZ_INS_LMY, + SYSZ_INS_LNDBR = SYSTEMZ_INS_LNDBR, + SYSZ_INS_LNDFR = SYSTEMZ_INS_LNDFR, + SYSZ_INS_LNDR = SYSTEMZ_INS_LNDR, + SYSZ_INS_LNEBR = SYSTEMZ_INS_LNEBR, + SYSZ_INS_LNER = SYSTEMZ_INS_LNER, + SYSZ_INS_LNGFR = SYSTEMZ_INS_LNGFR, + SYSZ_INS_LNGR = SYSTEMZ_INS_LNGR, + SYSZ_INS_LNR = SYSTEMZ_INS_LNR, + SYSZ_INS_LNXBR = SYSTEMZ_INS_LNXBR, + SYSZ_INS_LNXR = SYSTEMZ_INS_LNXR, + SYSZ_INS_LOC = SYSTEMZ_INS_LOC, + SYSZ_INS_LOCE = SYSTEMZ_INS_LOCE, + SYSZ_INS_LOCH = SYSTEMZ_INS_LOCH, + SYSZ_INS_LOCHE = SYSTEMZ_INS_LOCHE, + SYSZ_INS_LOCL = SYSTEMZ_INS_LOCL, + SYSZ_INS_LOCLE = SYSTEMZ_INS_LOCLE, + SYSZ_INS_LOCLH = SYSTEMZ_INS_LOCLH, + SYSZ_INS_LOCM = SYSTEMZ_INS_LOCM, + SYSZ_INS_LOCNE = SYSTEMZ_INS_LOCNE, + SYSZ_INS_LOCNH = SYSTEMZ_INS_LOCNH, + SYSZ_INS_LOCNHE = SYSTEMZ_INS_LOCNHE, + SYSZ_INS_LOCNL = SYSTEMZ_INS_LOCNL, + SYSZ_INS_LOCNLE = SYSTEMZ_INS_LOCNLE, + SYSZ_INS_LOCNLH = SYSTEMZ_INS_LOCNLH, + SYSZ_INS_LOCNM = SYSTEMZ_INS_LOCNM, + SYSZ_INS_LOCNO = SYSTEMZ_INS_LOCNO, + SYSZ_INS_LOCNP = SYSTEMZ_INS_LOCNP, + SYSZ_INS_LOCNZ = SYSTEMZ_INS_LOCNZ, + SYSZ_INS_LOCO = SYSTEMZ_INS_LOCO, + SYSZ_INS_LOCP = SYSTEMZ_INS_LOCP, + SYSZ_INS_LOCZ = SYSTEMZ_INS_LOCZ, + SYSZ_INS_LOCFH = SYSTEMZ_INS_LOCFH, + SYSZ_INS_LOCFHE = SYSTEMZ_INS_LOCFHE, + SYSZ_INS_LOCFHH = SYSTEMZ_INS_LOCFHH, + SYSZ_INS_LOCFHHE = SYSTEMZ_INS_LOCFHHE, + SYSZ_INS_LOCFHL = SYSTEMZ_INS_LOCFHL, + SYSZ_INS_LOCFHLE = SYSTEMZ_INS_LOCFHLE, + SYSZ_INS_LOCFHLH = SYSTEMZ_INS_LOCFHLH, + SYSZ_INS_LOCFHM = SYSTEMZ_INS_LOCFHM, + SYSZ_INS_LOCFHNE = SYSTEMZ_INS_LOCFHNE, + SYSZ_INS_LOCFHNH = SYSTEMZ_INS_LOCFHNH, + SYSZ_INS_LOCFHNHE = SYSTEMZ_INS_LOCFHNHE, + SYSZ_INS_LOCFHNL = SYSTEMZ_INS_LOCFHNL, + SYSZ_INS_LOCFHNLE = SYSTEMZ_INS_LOCFHNLE, + SYSZ_INS_LOCFHNLH = SYSTEMZ_INS_LOCFHNLH, + SYSZ_INS_LOCFHNM = SYSTEMZ_INS_LOCFHNM, + SYSZ_INS_LOCFHNO = SYSTEMZ_INS_LOCFHNO, + SYSZ_INS_LOCFHNP = SYSTEMZ_INS_LOCFHNP, + SYSZ_INS_LOCFHNZ = SYSTEMZ_INS_LOCFHNZ, + SYSZ_INS_LOCFHO = SYSTEMZ_INS_LOCFHO, + SYSZ_INS_LOCFHP = SYSTEMZ_INS_LOCFHP, + SYSZ_INS_LOCFHZ = SYSTEMZ_INS_LOCFHZ, + SYSZ_INS_LOCFHR = SYSTEMZ_INS_LOCFHR, + SYSZ_INS_LOCFHRE = SYSTEMZ_INS_LOCFHRE, + SYSZ_INS_LOCFHRH = SYSTEMZ_INS_LOCFHRH, + SYSZ_INS_LOCFHRHE = SYSTEMZ_INS_LOCFHRHE, + SYSZ_INS_LOCFHRL = SYSTEMZ_INS_LOCFHRL, + SYSZ_INS_LOCFHRLE = SYSTEMZ_INS_LOCFHRLE, + SYSZ_INS_LOCFHRLH = SYSTEMZ_INS_LOCFHRLH, + SYSZ_INS_LOCFHRM = SYSTEMZ_INS_LOCFHRM, + SYSZ_INS_LOCFHRNE = SYSTEMZ_INS_LOCFHRNE, + SYSZ_INS_LOCFHRNH = SYSTEMZ_INS_LOCFHRNH, + SYSZ_INS_LOCFHRNHE = SYSTEMZ_INS_LOCFHRNHE, + SYSZ_INS_LOCFHRNL = SYSTEMZ_INS_LOCFHRNL, + SYSZ_INS_LOCFHRNLE = SYSTEMZ_INS_LOCFHRNLE, + SYSZ_INS_LOCFHRNLH = SYSTEMZ_INS_LOCFHRNLH, + SYSZ_INS_LOCFHRNM = SYSTEMZ_INS_LOCFHRNM, + SYSZ_INS_LOCFHRNO = SYSTEMZ_INS_LOCFHRNO, + SYSZ_INS_LOCFHRNP = SYSTEMZ_INS_LOCFHRNP, + SYSZ_INS_LOCFHRNZ = SYSTEMZ_INS_LOCFHRNZ, + SYSZ_INS_LOCFHRO = SYSTEMZ_INS_LOCFHRO, + SYSZ_INS_LOCFHRP = SYSTEMZ_INS_LOCFHRP, + SYSZ_INS_LOCFHRZ = SYSTEMZ_INS_LOCFHRZ, + SYSZ_INS_LOCG = SYSTEMZ_INS_LOCG, + SYSZ_INS_LOCGE = SYSTEMZ_INS_LOCGE, + SYSZ_INS_LOCGH = SYSTEMZ_INS_LOCGH, + SYSZ_INS_LOCGHE = SYSTEMZ_INS_LOCGHE, + SYSZ_INS_LOCGL = SYSTEMZ_INS_LOCGL, + SYSZ_INS_LOCGLE = SYSTEMZ_INS_LOCGLE, + SYSZ_INS_LOCGLH = SYSTEMZ_INS_LOCGLH, + SYSZ_INS_LOCGM = SYSTEMZ_INS_LOCGM, + SYSZ_INS_LOCGNE = SYSTEMZ_INS_LOCGNE, + SYSZ_INS_LOCGNH = SYSTEMZ_INS_LOCGNH, + SYSZ_INS_LOCGNHE = SYSTEMZ_INS_LOCGNHE, + SYSZ_INS_LOCGNL = SYSTEMZ_INS_LOCGNL, + SYSZ_INS_LOCGNLE = SYSTEMZ_INS_LOCGNLE, + SYSZ_INS_LOCGNLH = SYSTEMZ_INS_LOCGNLH, + SYSZ_INS_LOCGNM = SYSTEMZ_INS_LOCGNM, + SYSZ_INS_LOCGNO = SYSTEMZ_INS_LOCGNO, + SYSZ_INS_LOCGNP = SYSTEMZ_INS_LOCGNP, + SYSZ_INS_LOCGNZ = SYSTEMZ_INS_LOCGNZ, + SYSZ_INS_LOCGO = SYSTEMZ_INS_LOCGO, + SYSZ_INS_LOCGP = SYSTEMZ_INS_LOCGP, + SYSZ_INS_LOCGZ = SYSTEMZ_INS_LOCGZ, + SYSZ_INS_LOCGHI = SYSTEMZ_INS_LOCGHI, + SYSZ_INS_LOCGHIE = SYSTEMZ_INS_LOCGHIE, + SYSZ_INS_LOCGHIH = SYSTEMZ_INS_LOCGHIH, + SYSZ_INS_LOCGHIHE = SYSTEMZ_INS_LOCGHIHE, + SYSZ_INS_LOCGHIL = SYSTEMZ_INS_LOCGHIL, + SYSZ_INS_LOCGHILE = SYSTEMZ_INS_LOCGHILE, + SYSZ_INS_LOCGHILH = SYSTEMZ_INS_LOCGHILH, + SYSZ_INS_LOCGHIM = SYSTEMZ_INS_LOCGHIM, + SYSZ_INS_LOCGHINE = SYSTEMZ_INS_LOCGHINE, + SYSZ_INS_LOCGHINH = SYSTEMZ_INS_LOCGHINH, + SYSZ_INS_LOCGHINHE = SYSTEMZ_INS_LOCGHINHE, + SYSZ_INS_LOCGHINL = SYSTEMZ_INS_LOCGHINL, + SYSZ_INS_LOCGHINLE = SYSTEMZ_INS_LOCGHINLE, + SYSZ_INS_LOCGHINLH = SYSTEMZ_INS_LOCGHINLH, + SYSZ_INS_LOCGHINM = SYSTEMZ_INS_LOCGHINM, + SYSZ_INS_LOCGHINO = SYSTEMZ_INS_LOCGHINO, + SYSZ_INS_LOCGHINP = SYSTEMZ_INS_LOCGHINP, + SYSZ_INS_LOCGHINZ = SYSTEMZ_INS_LOCGHINZ, + SYSZ_INS_LOCGHIO = SYSTEMZ_INS_LOCGHIO, + SYSZ_INS_LOCGHIP = SYSTEMZ_INS_LOCGHIP, + SYSZ_INS_LOCGHIZ = SYSTEMZ_INS_LOCGHIZ, + SYSZ_INS_LOCGR = SYSTEMZ_INS_LOCGR, + SYSZ_INS_LOCGRE = SYSTEMZ_INS_LOCGRE, + SYSZ_INS_LOCGRH = SYSTEMZ_INS_LOCGRH, + SYSZ_INS_LOCGRHE = SYSTEMZ_INS_LOCGRHE, + SYSZ_INS_LOCGRL = SYSTEMZ_INS_LOCGRL, + SYSZ_INS_LOCGRLE = SYSTEMZ_INS_LOCGRLE, + SYSZ_INS_LOCGRLH = SYSTEMZ_INS_LOCGRLH, + SYSZ_INS_LOCGRM = SYSTEMZ_INS_LOCGRM, + SYSZ_INS_LOCGRNE = SYSTEMZ_INS_LOCGRNE, + SYSZ_INS_LOCGRNH = SYSTEMZ_INS_LOCGRNH, + SYSZ_INS_LOCGRNHE = SYSTEMZ_INS_LOCGRNHE, + SYSZ_INS_LOCGRNL = SYSTEMZ_INS_LOCGRNL, + SYSZ_INS_LOCGRNLE = SYSTEMZ_INS_LOCGRNLE, + SYSZ_INS_LOCGRNLH = SYSTEMZ_INS_LOCGRNLH, + SYSZ_INS_LOCGRNM = SYSTEMZ_INS_LOCGRNM, + SYSZ_INS_LOCGRNO = SYSTEMZ_INS_LOCGRNO, + SYSZ_INS_LOCGRNP = SYSTEMZ_INS_LOCGRNP, + SYSZ_INS_LOCGRNZ = SYSTEMZ_INS_LOCGRNZ, + SYSZ_INS_LOCGRO = SYSTEMZ_INS_LOCGRO, + SYSZ_INS_LOCGRP = SYSTEMZ_INS_LOCGRP, + SYSZ_INS_LOCGRZ = SYSTEMZ_INS_LOCGRZ, + SYSZ_INS_LOCHHI = SYSTEMZ_INS_LOCHHI, + SYSZ_INS_LOCHHIE = SYSTEMZ_INS_LOCHHIE, + SYSZ_INS_LOCHHIH = SYSTEMZ_INS_LOCHHIH, + SYSZ_INS_LOCHHIHE = SYSTEMZ_INS_LOCHHIHE, + SYSZ_INS_LOCHHIL = SYSTEMZ_INS_LOCHHIL, + SYSZ_INS_LOCHHILE = SYSTEMZ_INS_LOCHHILE, + SYSZ_INS_LOCHHILH = SYSTEMZ_INS_LOCHHILH, + SYSZ_INS_LOCHHIM = SYSTEMZ_INS_LOCHHIM, + SYSZ_INS_LOCHHINE = SYSTEMZ_INS_LOCHHINE, + SYSZ_INS_LOCHHINH = SYSTEMZ_INS_LOCHHINH, + SYSZ_INS_LOCHHINHE = SYSTEMZ_INS_LOCHHINHE, + SYSZ_INS_LOCHHINL = SYSTEMZ_INS_LOCHHINL, + SYSZ_INS_LOCHHINLE = SYSTEMZ_INS_LOCHHINLE, + SYSZ_INS_LOCHHINLH = SYSTEMZ_INS_LOCHHINLH, + SYSZ_INS_LOCHHINM = SYSTEMZ_INS_LOCHHINM, + SYSZ_INS_LOCHHINO = SYSTEMZ_INS_LOCHHINO, + SYSZ_INS_LOCHHINP = SYSTEMZ_INS_LOCHHINP, + SYSZ_INS_LOCHHINZ = SYSTEMZ_INS_LOCHHINZ, + SYSZ_INS_LOCHHIO = SYSTEMZ_INS_LOCHHIO, + SYSZ_INS_LOCHHIP = SYSTEMZ_INS_LOCHHIP, + SYSZ_INS_LOCHHIZ = SYSTEMZ_INS_LOCHHIZ, + SYSZ_INS_LOCHI = SYSTEMZ_INS_LOCHI, + SYSZ_INS_LOCHIE = SYSTEMZ_INS_LOCHIE, + SYSZ_INS_LOCHIH = SYSTEMZ_INS_LOCHIH, + SYSZ_INS_LOCHIHE = SYSTEMZ_INS_LOCHIHE, + SYSZ_INS_LOCHIL = SYSTEMZ_INS_LOCHIL, + SYSZ_INS_LOCHILE = SYSTEMZ_INS_LOCHILE, + SYSZ_INS_LOCHILH = SYSTEMZ_INS_LOCHILH, + SYSZ_INS_LOCHIM = SYSTEMZ_INS_LOCHIM, + SYSZ_INS_LOCHINE = SYSTEMZ_INS_LOCHINE, + SYSZ_INS_LOCHINH = SYSTEMZ_INS_LOCHINH, + SYSZ_INS_LOCHINHE = SYSTEMZ_INS_LOCHINHE, + SYSZ_INS_LOCHINL = SYSTEMZ_INS_LOCHINL, + SYSZ_INS_LOCHINLE = SYSTEMZ_INS_LOCHINLE, + SYSZ_INS_LOCHINLH = SYSTEMZ_INS_LOCHINLH, + SYSZ_INS_LOCHINM = SYSTEMZ_INS_LOCHINM, + SYSZ_INS_LOCHINO = SYSTEMZ_INS_LOCHINO, + SYSZ_INS_LOCHINP = SYSTEMZ_INS_LOCHINP, + SYSZ_INS_LOCHINZ = SYSTEMZ_INS_LOCHINZ, + SYSZ_INS_LOCHIO = SYSTEMZ_INS_LOCHIO, + SYSZ_INS_LOCHIP = SYSTEMZ_INS_LOCHIP, + SYSZ_INS_LOCHIZ = SYSTEMZ_INS_LOCHIZ, + SYSZ_INS_LOCR = SYSTEMZ_INS_LOCR, + SYSZ_INS_LOCRE = SYSTEMZ_INS_LOCRE, + SYSZ_INS_LOCRH = SYSTEMZ_INS_LOCRH, + SYSZ_INS_LOCRHE = SYSTEMZ_INS_LOCRHE, + SYSZ_INS_LOCRL = SYSTEMZ_INS_LOCRL, + SYSZ_INS_LOCRLE = SYSTEMZ_INS_LOCRLE, + SYSZ_INS_LOCRLH = SYSTEMZ_INS_LOCRLH, + SYSZ_INS_LOCRM = SYSTEMZ_INS_LOCRM, + SYSZ_INS_LOCRNE = SYSTEMZ_INS_LOCRNE, + SYSZ_INS_LOCRNH = SYSTEMZ_INS_LOCRNH, + SYSZ_INS_LOCRNHE = SYSTEMZ_INS_LOCRNHE, + SYSZ_INS_LOCRNL = SYSTEMZ_INS_LOCRNL, + SYSZ_INS_LOCRNLE = SYSTEMZ_INS_LOCRNLE, + SYSZ_INS_LOCRNLH = SYSTEMZ_INS_LOCRNLH, + SYSZ_INS_LOCRNM = SYSTEMZ_INS_LOCRNM, + SYSZ_INS_LOCRNO = SYSTEMZ_INS_LOCRNO, + SYSZ_INS_LOCRNP = SYSTEMZ_INS_LOCRNP, + SYSZ_INS_LOCRNZ = SYSTEMZ_INS_LOCRNZ, + SYSZ_INS_LOCRO = SYSTEMZ_INS_LOCRO, + SYSZ_INS_LOCRP = SYSTEMZ_INS_LOCRP, + SYSZ_INS_LOCRZ = SYSTEMZ_INS_LOCRZ, + SYSZ_INS_LPCTL = SYSTEMZ_INS_LPCTL, + SYSZ_INS_LPD = SYSTEMZ_INS_LPD, + SYSZ_INS_LPDBR = SYSTEMZ_INS_LPDBR, + SYSZ_INS_LPDFR = SYSTEMZ_INS_LPDFR, + SYSZ_INS_LPDG = SYSTEMZ_INS_LPDG, + SYSZ_INS_LPDR = SYSTEMZ_INS_LPDR, + SYSZ_INS_LPEBR = SYSTEMZ_INS_LPEBR, + SYSZ_INS_LPER = SYSTEMZ_INS_LPER, + SYSZ_INS_LPGFR = SYSTEMZ_INS_LPGFR, + SYSZ_INS_LPGR = SYSTEMZ_INS_LPGR, + SYSZ_INS_LPP = SYSTEMZ_INS_LPP, + SYSZ_INS_LPQ = SYSTEMZ_INS_LPQ, + SYSZ_INS_LPR = SYSTEMZ_INS_LPR, + SYSZ_INS_LPSW = SYSTEMZ_INS_LPSW, + SYSZ_INS_LPSWE = SYSTEMZ_INS_LPSWE, + SYSZ_INS_LPSWEY = SYSTEMZ_INS_LPSWEY, + SYSZ_INS_LPTEA = SYSTEMZ_INS_LPTEA, + SYSZ_INS_LPXBR = SYSTEMZ_INS_LPXBR, + SYSZ_INS_LPXR = SYSTEMZ_INS_LPXR, + SYSZ_INS_LR = SYSTEMZ_INS_LR, + SYSZ_INS_LRA = SYSTEMZ_INS_LRA, + SYSZ_INS_LRAG = SYSTEMZ_INS_LRAG, + SYSZ_INS_LRAY = SYSTEMZ_INS_LRAY, + SYSZ_INS_LRDR = SYSTEMZ_INS_LRDR, + SYSZ_INS_LRER = SYSTEMZ_INS_LRER, + SYSZ_INS_LRL = SYSTEMZ_INS_LRL, + SYSZ_INS_LRV = SYSTEMZ_INS_LRV, + SYSZ_INS_LRVG = SYSTEMZ_INS_LRVG, + SYSZ_INS_LRVGR = SYSTEMZ_INS_LRVGR, + SYSZ_INS_LRVH = SYSTEMZ_INS_LRVH, + SYSZ_INS_LRVR = SYSTEMZ_INS_LRVR, + SYSZ_INS_LSCTL = SYSTEMZ_INS_LSCTL, + SYSZ_INS_LT = SYSTEMZ_INS_LT, + SYSZ_INS_LTDBR = SYSTEMZ_INS_LTDBR, + SYSZ_INS_LTDR = SYSTEMZ_INS_LTDR, + SYSZ_INS_LTDTR = SYSTEMZ_INS_LTDTR, + SYSZ_INS_LTEBR = SYSTEMZ_INS_LTEBR, + SYSZ_INS_LTER = SYSTEMZ_INS_LTER, + SYSZ_INS_LTG = SYSTEMZ_INS_LTG, + SYSZ_INS_LTGF = SYSTEMZ_INS_LTGF, + SYSZ_INS_LTGFR = SYSTEMZ_INS_LTGFR, + SYSZ_INS_LTGR = SYSTEMZ_INS_LTGR, + SYSZ_INS_LTR = SYSTEMZ_INS_LTR, + SYSZ_INS_LTXBR = SYSTEMZ_INS_LTXBR, + SYSZ_INS_LTXR = SYSTEMZ_INS_LTXR, + SYSZ_INS_LTXTR = SYSTEMZ_INS_LTXTR, + SYSZ_INS_LURA = SYSTEMZ_INS_LURA, + SYSZ_INS_LURAG = SYSTEMZ_INS_LURAG, + SYSZ_INS_LXD = SYSTEMZ_INS_LXD, + SYSZ_INS_LXDB = SYSTEMZ_INS_LXDB, + SYSZ_INS_LXDBR = SYSTEMZ_INS_LXDBR, + SYSZ_INS_LXDR = SYSTEMZ_INS_LXDR, + SYSZ_INS_LXDTR = SYSTEMZ_INS_LXDTR, + SYSZ_INS_LXE = SYSTEMZ_INS_LXE, + SYSZ_INS_LXEB = SYSTEMZ_INS_LXEB, + SYSZ_INS_LXEBR = SYSTEMZ_INS_LXEBR, + SYSZ_INS_LXER = SYSTEMZ_INS_LXER, + SYSZ_INS_LXR = SYSTEMZ_INS_LXR, + SYSZ_INS_LY = SYSTEMZ_INS_LY, + SYSZ_INS_LZDR = SYSTEMZ_INS_LZDR, + SYSZ_INS_LZER = SYSTEMZ_INS_LZER, + SYSZ_INS_LZRF = SYSTEMZ_INS_LZRF, + SYSZ_INS_LZRG = SYSTEMZ_INS_LZRG, + SYSZ_INS_LZXR = SYSTEMZ_INS_LZXR, + SYSZ_INS_M = SYSTEMZ_INS_M, + SYSZ_INS_MAD = SYSTEMZ_INS_MAD, + SYSZ_INS_MADB = SYSTEMZ_INS_MADB, + SYSZ_INS_MADBR = SYSTEMZ_INS_MADBR, + SYSZ_INS_MADR = SYSTEMZ_INS_MADR, + SYSZ_INS_MAE = SYSTEMZ_INS_MAE, + SYSZ_INS_MAEB = SYSTEMZ_INS_MAEB, + SYSZ_INS_MAEBR = SYSTEMZ_INS_MAEBR, + SYSZ_INS_MAER = SYSTEMZ_INS_MAER, + SYSZ_INS_MAY = SYSTEMZ_INS_MAY, + SYSZ_INS_MAYH = SYSTEMZ_INS_MAYH, + SYSZ_INS_MAYHR = SYSTEMZ_INS_MAYHR, + SYSZ_INS_MAYL = SYSTEMZ_INS_MAYL, + SYSZ_INS_MAYLR = SYSTEMZ_INS_MAYLR, + SYSZ_INS_MAYR = SYSTEMZ_INS_MAYR, + SYSZ_INS_MC = SYSTEMZ_INS_MC, + SYSZ_INS_MD = SYSTEMZ_INS_MD, + SYSZ_INS_MDB = SYSTEMZ_INS_MDB, + SYSZ_INS_MDBR = SYSTEMZ_INS_MDBR, + SYSZ_INS_MDE = SYSTEMZ_INS_MDE, + SYSZ_INS_MDEB = SYSTEMZ_INS_MDEB, + SYSZ_INS_MDEBR = SYSTEMZ_INS_MDEBR, + SYSZ_INS_MDER = SYSTEMZ_INS_MDER, + SYSZ_INS_MDR = SYSTEMZ_INS_MDR, + SYSZ_INS_MDTR = SYSTEMZ_INS_MDTR, + SYSZ_INS_MDTRA = SYSTEMZ_INS_MDTRA, + SYSZ_INS_ME = SYSTEMZ_INS_ME, + SYSZ_INS_MEE = SYSTEMZ_INS_MEE, + SYSZ_INS_MEEB = SYSTEMZ_INS_MEEB, + SYSZ_INS_MEEBR = SYSTEMZ_INS_MEEBR, + SYSZ_INS_MEER = SYSTEMZ_INS_MEER, + SYSZ_INS_MER = SYSTEMZ_INS_MER, + SYSZ_INS_MFY = SYSTEMZ_INS_MFY, + SYSZ_INS_MG = SYSTEMZ_INS_MG, + SYSZ_INS_MGH = SYSTEMZ_INS_MGH, + SYSZ_INS_MGHI = SYSTEMZ_INS_MGHI, + SYSZ_INS_MGRK = SYSTEMZ_INS_MGRK, + SYSZ_INS_MH = SYSTEMZ_INS_MH, + SYSZ_INS_MHI = SYSTEMZ_INS_MHI, + SYSZ_INS_MHY = SYSTEMZ_INS_MHY, + SYSZ_INS_ML = SYSTEMZ_INS_ML, + SYSZ_INS_MLG = SYSTEMZ_INS_MLG, + SYSZ_INS_MLGR = SYSTEMZ_INS_MLGR, + SYSZ_INS_MLR = SYSTEMZ_INS_MLR, + SYSZ_INS_MP = SYSTEMZ_INS_MP, + SYSZ_INS_MR = SYSTEMZ_INS_MR, + SYSZ_INS_MS = SYSTEMZ_INS_MS, + SYSZ_INS_MSC = SYSTEMZ_INS_MSC, + SYSZ_INS_MSCH = SYSTEMZ_INS_MSCH, + SYSZ_INS_MSD = SYSTEMZ_INS_MSD, + SYSZ_INS_MSDB = SYSTEMZ_INS_MSDB, + SYSZ_INS_MSDBR = SYSTEMZ_INS_MSDBR, + SYSZ_INS_MSDR = SYSTEMZ_INS_MSDR, + SYSZ_INS_MSE = SYSTEMZ_INS_MSE, + SYSZ_INS_MSEB = SYSTEMZ_INS_MSEB, + SYSZ_INS_MSEBR = SYSTEMZ_INS_MSEBR, + SYSZ_INS_MSER = SYSTEMZ_INS_MSER, + SYSZ_INS_MSFI = SYSTEMZ_INS_MSFI, + SYSZ_INS_MSG = SYSTEMZ_INS_MSG, + SYSZ_INS_MSGC = SYSTEMZ_INS_MSGC, + SYSZ_INS_MSGF = SYSTEMZ_INS_MSGF, + SYSZ_INS_MSGFI = SYSTEMZ_INS_MSGFI, + SYSZ_INS_MSGFR = SYSTEMZ_INS_MSGFR, + SYSZ_INS_MSGR = SYSTEMZ_INS_MSGR, + SYSZ_INS_MSGRKC = SYSTEMZ_INS_MSGRKC, + SYSZ_INS_MSR = SYSTEMZ_INS_MSR, + SYSZ_INS_MSRKC = SYSTEMZ_INS_MSRKC, + SYSZ_INS_MSTA = SYSTEMZ_INS_MSTA, + SYSZ_INS_MSY = SYSTEMZ_INS_MSY, + SYSZ_INS_MVC = SYSTEMZ_INS_MVC, + SYSZ_INS_MVCDK = SYSTEMZ_INS_MVCDK, + SYSZ_INS_MVCIN = SYSTEMZ_INS_MVCIN, + SYSZ_INS_MVCK = SYSTEMZ_INS_MVCK, + SYSZ_INS_MVCL = SYSTEMZ_INS_MVCL, + SYSZ_INS_MVCLE = SYSTEMZ_INS_MVCLE, + SYSZ_INS_MVCLU = SYSTEMZ_INS_MVCLU, + SYSZ_INS_MVCOS = SYSTEMZ_INS_MVCOS, + SYSZ_INS_MVCP = SYSTEMZ_INS_MVCP, + SYSZ_INS_MVCRL = SYSTEMZ_INS_MVCRL, + SYSZ_INS_MVCS = SYSTEMZ_INS_MVCS, + SYSZ_INS_MVCSK = SYSTEMZ_INS_MVCSK, + SYSZ_INS_MVGHI = SYSTEMZ_INS_MVGHI, + SYSZ_INS_MVHHI = SYSTEMZ_INS_MVHHI, + SYSZ_INS_MVHI = SYSTEMZ_INS_MVHI, + SYSZ_INS_MVI = SYSTEMZ_INS_MVI, + SYSZ_INS_MVIY = SYSTEMZ_INS_MVIY, + SYSZ_INS_MVN = SYSTEMZ_INS_MVN, + SYSZ_INS_MVO = SYSTEMZ_INS_MVO, + SYSZ_INS_MVPG = SYSTEMZ_INS_MVPG, + SYSZ_INS_MVST = SYSTEMZ_INS_MVST, + SYSZ_INS_MVZ = SYSTEMZ_INS_MVZ, + SYSZ_INS_MXBR = SYSTEMZ_INS_MXBR, + SYSZ_INS_MXD = SYSTEMZ_INS_MXD, + SYSZ_INS_MXDB = SYSTEMZ_INS_MXDB, + SYSZ_INS_MXDBR = SYSTEMZ_INS_MXDBR, + SYSZ_INS_MXDR = SYSTEMZ_INS_MXDR, + SYSZ_INS_MXR = SYSTEMZ_INS_MXR, + SYSZ_INS_MXTR = SYSTEMZ_INS_MXTR, + SYSZ_INS_MXTRA = SYSTEMZ_INS_MXTRA, + SYSZ_INS_MY = SYSTEMZ_INS_MY, + SYSZ_INS_MYH = SYSTEMZ_INS_MYH, + SYSZ_INS_MYHR = SYSTEMZ_INS_MYHR, + SYSZ_INS_MYL = SYSTEMZ_INS_MYL, + SYSZ_INS_MYLR = SYSTEMZ_INS_MYLR, + SYSZ_INS_MYR = SYSTEMZ_INS_MYR, + SYSZ_INS_N = SYSTEMZ_INS_N, + SYSZ_INS_NC = SYSTEMZ_INS_NC, + SYSZ_INS_NCGRK = SYSTEMZ_INS_NCGRK, + SYSZ_INS_NCRK = SYSTEMZ_INS_NCRK, + SYSZ_INS_NG = SYSTEMZ_INS_NG, + SYSZ_INS_NGR = SYSTEMZ_INS_NGR, + SYSZ_INS_NGRK = SYSTEMZ_INS_NGRK, + SYSZ_INS_NI = SYSTEMZ_INS_NI, + SYSZ_INS_NIAI = SYSTEMZ_INS_NIAI, + SYSZ_INS_NIHF = SYSTEMZ_INS_NIHF, + SYSZ_INS_NIHH = SYSTEMZ_INS_NIHH, + SYSZ_INS_NIHL = SYSTEMZ_INS_NIHL, + SYSZ_INS_NILF = SYSTEMZ_INS_NILF, + SYSZ_INS_NILH = SYSTEMZ_INS_NILH, + SYSZ_INS_NILL = SYSTEMZ_INS_NILL, + SYSZ_INS_NIY = SYSTEMZ_INS_NIY, + SYSZ_INS_NNGRK = SYSTEMZ_INS_NNGRK, + SYSZ_INS_NNPA = SYSTEMZ_INS_NNPA, + SYSZ_INS_NNRK = SYSTEMZ_INS_NNRK, + SYSZ_INS_NOGRK = SYSTEMZ_INS_NOGRK, + SYSZ_INS_NOP = SYSTEMZ_INS_NOP, + SYSZ_INS_NORK = SYSTEMZ_INS_NORK, + SYSZ_INS_NR = SYSTEMZ_INS_NR, + SYSZ_INS_NRK = SYSTEMZ_INS_NRK, + SYSZ_INS_NTSTG = SYSTEMZ_INS_NTSTG, + SYSZ_INS_NXGRK = SYSTEMZ_INS_NXGRK, + SYSZ_INS_NXRK = SYSTEMZ_INS_NXRK, + SYSZ_INS_NY = SYSTEMZ_INS_NY, + SYSZ_INS_O = SYSTEMZ_INS_O, + SYSZ_INS_OC = SYSTEMZ_INS_OC, + SYSZ_INS_OCGRK = SYSTEMZ_INS_OCGRK, + SYSZ_INS_OCRK = SYSTEMZ_INS_OCRK, + SYSZ_INS_OG = SYSTEMZ_INS_OG, + SYSZ_INS_OGR = SYSTEMZ_INS_OGR, + SYSZ_INS_OGRK = SYSTEMZ_INS_OGRK, + SYSZ_INS_OI = SYSTEMZ_INS_OI, + SYSZ_INS_OIHF = SYSTEMZ_INS_OIHF, + SYSZ_INS_OIHH = SYSTEMZ_INS_OIHH, + SYSZ_INS_OIHL = SYSTEMZ_INS_OIHL, + SYSZ_INS_OILF = SYSTEMZ_INS_OILF, + SYSZ_INS_OILH = SYSTEMZ_INS_OILH, + SYSZ_INS_OILL = SYSTEMZ_INS_OILL, + SYSZ_INS_OIY = SYSTEMZ_INS_OIY, + SYSZ_INS_OR = SYSTEMZ_INS_OR, + SYSZ_INS_ORK = SYSTEMZ_INS_ORK, + SYSZ_INS_OY = SYSTEMZ_INS_OY, + SYSZ_INS_PACK = SYSTEMZ_INS_PACK, + SYSZ_INS_PALB = SYSTEMZ_INS_PALB, + SYSZ_INS_PC = SYSTEMZ_INS_PC, + SYSZ_INS_PCC = SYSTEMZ_INS_PCC, + SYSZ_INS_PCKMO = SYSTEMZ_INS_PCKMO, + SYSZ_INS_PFD = SYSTEMZ_INS_PFD, + SYSZ_INS_PFDRL = SYSTEMZ_INS_PFDRL, + SYSZ_INS_PFMF = SYSTEMZ_INS_PFMF, + SYSZ_INS_PFPO = SYSTEMZ_INS_PFPO, + SYSZ_INS_PGIN = SYSTEMZ_INS_PGIN, + SYSZ_INS_PGOUT = SYSTEMZ_INS_PGOUT, + SYSZ_INS_PKA = SYSTEMZ_INS_PKA, + SYSZ_INS_PKU = SYSTEMZ_INS_PKU, + SYSZ_INS_PLO = SYSTEMZ_INS_PLO, + SYSZ_INS_POPCNT = SYSTEMZ_INS_POPCNT, + SYSZ_INS_PPA = SYSTEMZ_INS_PPA, + SYSZ_INS_PPNO = SYSTEMZ_INS_PPNO, + SYSZ_INS_PR = SYSTEMZ_INS_PR, + SYSZ_INS_PRNO = SYSTEMZ_INS_PRNO, + SYSZ_INS_PT = SYSTEMZ_INS_PT, + SYSZ_INS_PTF = SYSTEMZ_INS_PTF, + SYSZ_INS_PTFF = SYSTEMZ_INS_PTFF, + SYSZ_INS_PTI = SYSTEMZ_INS_PTI, + SYSZ_INS_PTLB = SYSTEMZ_INS_PTLB, + SYSZ_INS_QADTR = SYSTEMZ_INS_QADTR, + SYSZ_INS_QAXTR = SYSTEMZ_INS_QAXTR, + SYSZ_INS_QCTRI = SYSTEMZ_INS_QCTRI, + SYSZ_INS_QPACI = SYSTEMZ_INS_QPACI, + SYSZ_INS_QSI = SYSTEMZ_INS_QSI, + SYSZ_INS_RCHP = SYSTEMZ_INS_RCHP, + SYSZ_INS_RDP = SYSTEMZ_INS_RDP, + SYSZ_INS_RISBG = SYSTEMZ_INS_RISBG, + SYSZ_INS_RISBGN = SYSTEMZ_INS_RISBGN, + SYSZ_INS_RISBHG = SYSTEMZ_INS_RISBHG, + SYSZ_INS_RISBLG = SYSTEMZ_INS_RISBLG, + SYSZ_INS_RLL = SYSTEMZ_INS_RLL, + SYSZ_INS_RLLG = SYSTEMZ_INS_RLLG, + SYSZ_INS_RNSBG = SYSTEMZ_INS_RNSBG, + SYSZ_INS_ROSBG = SYSTEMZ_INS_ROSBG, + SYSZ_INS_RP = SYSTEMZ_INS_RP, + SYSZ_INS_RRBE = SYSTEMZ_INS_RRBE, + SYSZ_INS_RRBM = SYSTEMZ_INS_RRBM, + SYSZ_INS_RRDTR = SYSTEMZ_INS_RRDTR, + SYSZ_INS_RRXTR = SYSTEMZ_INS_RRXTR, + SYSZ_INS_RSCH = SYSTEMZ_INS_RSCH, + SYSZ_INS_RXSBG = SYSTEMZ_INS_RXSBG, + SYSZ_INS_S = SYSTEMZ_INS_S, + SYSZ_INS_SAC = SYSTEMZ_INS_SAC, + SYSZ_INS_SACF = SYSTEMZ_INS_SACF, + SYSZ_INS_SAL = SYSTEMZ_INS_SAL, + SYSZ_INS_SAM24 = SYSTEMZ_INS_SAM24, + SYSZ_INS_SAM31 = SYSTEMZ_INS_SAM31, + SYSZ_INS_SAM64 = SYSTEMZ_INS_SAM64, + SYSZ_INS_SAR = SYSTEMZ_INS_SAR, + SYSZ_INS_SCCTR = SYSTEMZ_INS_SCCTR, + SYSZ_INS_SCHM = SYSTEMZ_INS_SCHM, + SYSZ_INS_SCK = SYSTEMZ_INS_SCK, + SYSZ_INS_SCKC = SYSTEMZ_INS_SCKC, + SYSZ_INS_SCKPF = SYSTEMZ_INS_SCKPF, + SYSZ_INS_SD = SYSTEMZ_INS_SD, + SYSZ_INS_SDB = SYSTEMZ_INS_SDB, + SYSZ_INS_SDBR = SYSTEMZ_INS_SDBR, + SYSZ_INS_SDR = SYSTEMZ_INS_SDR, + SYSZ_INS_SDTR = SYSTEMZ_INS_SDTR, + SYSZ_INS_SDTRA = SYSTEMZ_INS_SDTRA, + SYSZ_INS_SE = SYSTEMZ_INS_SE, + SYSZ_INS_SEB = SYSTEMZ_INS_SEB, + SYSZ_INS_SEBR = SYSTEMZ_INS_SEBR, + SYSZ_INS_SELFHR = SYSTEMZ_INS_SELFHR, + SYSZ_INS_SELFHRE = SYSTEMZ_INS_SELFHRE, + SYSZ_INS_SELFHRH = SYSTEMZ_INS_SELFHRH, + SYSZ_INS_SELFHRHE = SYSTEMZ_INS_SELFHRHE, + SYSZ_INS_SELFHRL = SYSTEMZ_INS_SELFHRL, + SYSZ_INS_SELFHRLE = SYSTEMZ_INS_SELFHRLE, + SYSZ_INS_SELFHRLH = SYSTEMZ_INS_SELFHRLH, + SYSZ_INS_SELFHRM = SYSTEMZ_INS_SELFHRM, + SYSZ_INS_SELFHRNE = SYSTEMZ_INS_SELFHRNE, + SYSZ_INS_SELFHRNH = SYSTEMZ_INS_SELFHRNH, + SYSZ_INS_SELFHRNHE = SYSTEMZ_INS_SELFHRNHE, + SYSZ_INS_SELFHRNL = SYSTEMZ_INS_SELFHRNL, + SYSZ_INS_SELFHRNLE = SYSTEMZ_INS_SELFHRNLE, + SYSZ_INS_SELFHRNLH = SYSTEMZ_INS_SELFHRNLH, + SYSZ_INS_SELFHRNM = SYSTEMZ_INS_SELFHRNM, + SYSZ_INS_SELFHRNO = SYSTEMZ_INS_SELFHRNO, + SYSZ_INS_SELFHRNP = SYSTEMZ_INS_SELFHRNP, + SYSZ_INS_SELFHRNZ = SYSTEMZ_INS_SELFHRNZ, + SYSZ_INS_SELFHRO = SYSTEMZ_INS_SELFHRO, + SYSZ_INS_SELFHRP = SYSTEMZ_INS_SELFHRP, + SYSZ_INS_SELFHRZ = SYSTEMZ_INS_SELFHRZ, + SYSZ_INS_SELGR = SYSTEMZ_INS_SELGR, + SYSZ_INS_SELGRE = SYSTEMZ_INS_SELGRE, + SYSZ_INS_SELGRH = SYSTEMZ_INS_SELGRH, + SYSZ_INS_SELGRHE = SYSTEMZ_INS_SELGRHE, + SYSZ_INS_SELGRL = SYSTEMZ_INS_SELGRL, + SYSZ_INS_SELGRLE = SYSTEMZ_INS_SELGRLE, + SYSZ_INS_SELGRLH = SYSTEMZ_INS_SELGRLH, + SYSZ_INS_SELGRM = SYSTEMZ_INS_SELGRM, + SYSZ_INS_SELGRNE = SYSTEMZ_INS_SELGRNE, + SYSZ_INS_SELGRNH = SYSTEMZ_INS_SELGRNH, + SYSZ_INS_SELGRNHE = SYSTEMZ_INS_SELGRNHE, + SYSZ_INS_SELGRNL = SYSTEMZ_INS_SELGRNL, + SYSZ_INS_SELGRNLE = SYSTEMZ_INS_SELGRNLE, + SYSZ_INS_SELGRNLH = SYSTEMZ_INS_SELGRNLH, + SYSZ_INS_SELGRNM = SYSTEMZ_INS_SELGRNM, + SYSZ_INS_SELGRNO = SYSTEMZ_INS_SELGRNO, + SYSZ_INS_SELGRNP = SYSTEMZ_INS_SELGRNP, + SYSZ_INS_SELGRNZ = SYSTEMZ_INS_SELGRNZ, + SYSZ_INS_SELGRO = SYSTEMZ_INS_SELGRO, + SYSZ_INS_SELGRP = SYSTEMZ_INS_SELGRP, + SYSZ_INS_SELGRZ = SYSTEMZ_INS_SELGRZ, + SYSZ_INS_SELR = SYSTEMZ_INS_SELR, + SYSZ_INS_SELRE = SYSTEMZ_INS_SELRE, + SYSZ_INS_SELRH = SYSTEMZ_INS_SELRH, + SYSZ_INS_SELRHE = SYSTEMZ_INS_SELRHE, + SYSZ_INS_SELRL = SYSTEMZ_INS_SELRL, + SYSZ_INS_SELRLE = SYSTEMZ_INS_SELRLE, + SYSZ_INS_SELRLH = SYSTEMZ_INS_SELRLH, + SYSZ_INS_SELRM = SYSTEMZ_INS_SELRM, + SYSZ_INS_SELRNE = SYSTEMZ_INS_SELRNE, + SYSZ_INS_SELRNH = SYSTEMZ_INS_SELRNH, + SYSZ_INS_SELRNHE = SYSTEMZ_INS_SELRNHE, + SYSZ_INS_SELRNL = SYSTEMZ_INS_SELRNL, + SYSZ_INS_SELRNLE = SYSTEMZ_INS_SELRNLE, + SYSZ_INS_SELRNLH = SYSTEMZ_INS_SELRNLH, + SYSZ_INS_SELRNM = SYSTEMZ_INS_SELRNM, + SYSZ_INS_SELRNO = SYSTEMZ_INS_SELRNO, + SYSZ_INS_SELRNP = SYSTEMZ_INS_SELRNP, + SYSZ_INS_SELRNZ = SYSTEMZ_INS_SELRNZ, + SYSZ_INS_SELRO = SYSTEMZ_INS_SELRO, + SYSZ_INS_SELRP = SYSTEMZ_INS_SELRP, + SYSZ_INS_SELRZ = SYSTEMZ_INS_SELRZ, + SYSZ_INS_SER = SYSTEMZ_INS_SER, + SYSZ_INS_SFASR = SYSTEMZ_INS_SFASR, + SYSZ_INS_SFPC = SYSTEMZ_INS_SFPC, + SYSZ_INS_SG = SYSTEMZ_INS_SG, + SYSZ_INS_SGF = SYSTEMZ_INS_SGF, + SYSZ_INS_SGFR = SYSTEMZ_INS_SGFR, + SYSZ_INS_SGH = SYSTEMZ_INS_SGH, + SYSZ_INS_SGR = SYSTEMZ_INS_SGR, + SYSZ_INS_SGRK = SYSTEMZ_INS_SGRK, + SYSZ_INS_SH = SYSTEMZ_INS_SH, + SYSZ_INS_SHHHR = SYSTEMZ_INS_SHHHR, + SYSZ_INS_SHHLR = SYSTEMZ_INS_SHHLR, + SYSZ_INS_SHY = SYSTEMZ_INS_SHY, + SYSZ_INS_SIE = SYSTEMZ_INS_SIE, + SYSZ_INS_SIGA = SYSTEMZ_INS_SIGA, + SYSZ_INS_SIGP = SYSTEMZ_INS_SIGP, + SYSZ_INS_SL = SYSTEMZ_INS_SL, + SYSZ_INS_SLA = SYSTEMZ_INS_SLA, + SYSZ_INS_SLAG = SYSTEMZ_INS_SLAG, + SYSZ_INS_SLAK = SYSTEMZ_INS_SLAK, + SYSZ_INS_SLB = SYSTEMZ_INS_SLB, + SYSZ_INS_SLBG = SYSTEMZ_INS_SLBG, + SYSZ_INS_SLBGR = SYSTEMZ_INS_SLBGR, + SYSZ_INS_SLBR = SYSTEMZ_INS_SLBR, + SYSZ_INS_SLDA = SYSTEMZ_INS_SLDA, + SYSZ_INS_SLDL = SYSTEMZ_INS_SLDL, + SYSZ_INS_SLDT = SYSTEMZ_INS_SLDT, + SYSZ_INS_SLFI = SYSTEMZ_INS_SLFI, + SYSZ_INS_SLG = SYSTEMZ_INS_SLG, + SYSZ_INS_SLGF = SYSTEMZ_INS_SLGF, + SYSZ_INS_SLGFI = SYSTEMZ_INS_SLGFI, + SYSZ_INS_SLGFR = SYSTEMZ_INS_SLGFR, + SYSZ_INS_SLGR = SYSTEMZ_INS_SLGR, + SYSZ_INS_SLGRK = SYSTEMZ_INS_SLGRK, + SYSZ_INS_SLHHHR = SYSTEMZ_INS_SLHHHR, + SYSZ_INS_SLHHLR = SYSTEMZ_INS_SLHHLR, + SYSZ_INS_SLL = SYSTEMZ_INS_SLL, + SYSZ_INS_SLLG = SYSTEMZ_INS_SLLG, + SYSZ_INS_SLLK = SYSTEMZ_INS_SLLK, + SYSZ_INS_SLR = SYSTEMZ_INS_SLR, + SYSZ_INS_SLRK = SYSTEMZ_INS_SLRK, + SYSZ_INS_SLXT = SYSTEMZ_INS_SLXT, + SYSZ_INS_SLY = SYSTEMZ_INS_SLY, + SYSZ_INS_SORTL = SYSTEMZ_INS_SORTL, + SYSZ_INS_SP = SYSTEMZ_INS_SP, + SYSZ_INS_SPCTR = SYSTEMZ_INS_SPCTR, + SYSZ_INS_SPKA = SYSTEMZ_INS_SPKA, + SYSZ_INS_SPM = SYSTEMZ_INS_SPM, + SYSZ_INS_SPT = SYSTEMZ_INS_SPT, + SYSZ_INS_SPX = SYSTEMZ_INS_SPX, + SYSZ_INS_SQD = SYSTEMZ_INS_SQD, + SYSZ_INS_SQDB = SYSTEMZ_INS_SQDB, + SYSZ_INS_SQDBR = SYSTEMZ_INS_SQDBR, + SYSZ_INS_SQDR = SYSTEMZ_INS_SQDR, + SYSZ_INS_SQE = SYSTEMZ_INS_SQE, + SYSZ_INS_SQEB = SYSTEMZ_INS_SQEB, + SYSZ_INS_SQEBR = SYSTEMZ_INS_SQEBR, + SYSZ_INS_SQER = SYSTEMZ_INS_SQER, + SYSZ_INS_SQXBR = SYSTEMZ_INS_SQXBR, + SYSZ_INS_SQXR = SYSTEMZ_INS_SQXR, + SYSZ_INS_SR = SYSTEMZ_INS_SR, + SYSZ_INS_SRA = SYSTEMZ_INS_SRA, + SYSZ_INS_SRAG = SYSTEMZ_INS_SRAG, + SYSZ_INS_SRAK = SYSTEMZ_INS_SRAK, + SYSZ_INS_SRDA = SYSTEMZ_INS_SRDA, + SYSZ_INS_SRDL = SYSTEMZ_INS_SRDL, + SYSZ_INS_SRDT = SYSTEMZ_INS_SRDT, + SYSZ_INS_SRK = SYSTEMZ_INS_SRK, + SYSZ_INS_SRL = SYSTEMZ_INS_SRL, + SYSZ_INS_SRLG = SYSTEMZ_INS_SRLG, + SYSZ_INS_SRLK = SYSTEMZ_INS_SRLK, + SYSZ_INS_SRNM = SYSTEMZ_INS_SRNM, + SYSZ_INS_SRNMB = SYSTEMZ_INS_SRNMB, + SYSZ_INS_SRNMT = SYSTEMZ_INS_SRNMT, + SYSZ_INS_SRP = SYSTEMZ_INS_SRP, + SYSZ_INS_SRST = SYSTEMZ_INS_SRST, + SYSZ_INS_SRSTU = SYSTEMZ_INS_SRSTU, + SYSZ_INS_SRXT = SYSTEMZ_INS_SRXT, + SYSZ_INS_SSAIR = SYSTEMZ_INS_SSAIR, + SYSZ_INS_SSAR = SYSTEMZ_INS_SSAR, + SYSZ_INS_SSCH = SYSTEMZ_INS_SSCH, + SYSZ_INS_SSKE = SYSTEMZ_INS_SSKE, + SYSZ_INS_SSM = SYSTEMZ_INS_SSM, + SYSZ_INS_ST = SYSTEMZ_INS_ST, + SYSZ_INS_STAM = SYSTEMZ_INS_STAM, + SYSZ_INS_STAMY = SYSTEMZ_INS_STAMY, + SYSZ_INS_STAP = SYSTEMZ_INS_STAP, + SYSZ_INS_STBEAR = SYSTEMZ_INS_STBEAR, + SYSZ_INS_STC = SYSTEMZ_INS_STC, + SYSZ_INS_STCH = SYSTEMZ_INS_STCH, + SYSZ_INS_STCK = SYSTEMZ_INS_STCK, + SYSZ_INS_STCKC = SYSTEMZ_INS_STCKC, + SYSZ_INS_STCKE = SYSTEMZ_INS_STCKE, + SYSZ_INS_STCKF = SYSTEMZ_INS_STCKF, + SYSZ_INS_STCM = SYSTEMZ_INS_STCM, + SYSZ_INS_STCMH = SYSTEMZ_INS_STCMH, + SYSZ_INS_STCMY = SYSTEMZ_INS_STCMY, + SYSZ_INS_STCPS = SYSTEMZ_INS_STCPS, + SYSZ_INS_STCRW = SYSTEMZ_INS_STCRW, + SYSZ_INS_STCTG = SYSTEMZ_INS_STCTG, + SYSZ_INS_STCTL = SYSTEMZ_INS_STCTL, + SYSZ_INS_STCY = SYSTEMZ_INS_STCY, + SYSZ_INS_STD = SYSTEMZ_INS_STD, + SYSZ_INS_STDY = SYSTEMZ_INS_STDY, + SYSZ_INS_STE = SYSTEMZ_INS_STE, + SYSZ_INS_STEY = SYSTEMZ_INS_STEY, + SYSZ_INS_STFH = SYSTEMZ_INS_STFH, + SYSZ_INS_STFL = SYSTEMZ_INS_STFL, + SYSZ_INS_STFLE = SYSTEMZ_INS_STFLE, + SYSZ_INS_STFPC = SYSTEMZ_INS_STFPC, + SYSZ_INS_STG = SYSTEMZ_INS_STG, + SYSZ_INS_STGRL = SYSTEMZ_INS_STGRL, + SYSZ_INS_STGSC = SYSTEMZ_INS_STGSC, + SYSZ_INS_STH = SYSTEMZ_INS_STH, + SYSZ_INS_STHH = SYSTEMZ_INS_STHH, + SYSZ_INS_STHRL = SYSTEMZ_INS_STHRL, + SYSZ_INS_STHY = SYSTEMZ_INS_STHY, + SYSZ_INS_STIDP = SYSTEMZ_INS_STIDP, + SYSZ_INS_STM = SYSTEMZ_INS_STM, + SYSZ_INS_STMG = SYSTEMZ_INS_STMG, + SYSZ_INS_STMH = SYSTEMZ_INS_STMH, + SYSZ_INS_STMY = SYSTEMZ_INS_STMY, + SYSZ_INS_STNSM = SYSTEMZ_INS_STNSM, + SYSZ_INS_STOC = SYSTEMZ_INS_STOC, + SYSZ_INS_STOCE = SYSTEMZ_INS_STOCE, + SYSZ_INS_STOCH = SYSTEMZ_INS_STOCH, + SYSZ_INS_STOCHE = SYSTEMZ_INS_STOCHE, + SYSZ_INS_STOCL = SYSTEMZ_INS_STOCL, + SYSZ_INS_STOCLE = SYSTEMZ_INS_STOCLE, + SYSZ_INS_STOCLH = SYSTEMZ_INS_STOCLH, + SYSZ_INS_STOCM = SYSTEMZ_INS_STOCM, + SYSZ_INS_STOCNE = SYSTEMZ_INS_STOCNE, + SYSZ_INS_STOCNH = SYSTEMZ_INS_STOCNH, + SYSZ_INS_STOCNHE = SYSTEMZ_INS_STOCNHE, + SYSZ_INS_STOCNL = SYSTEMZ_INS_STOCNL, + SYSZ_INS_STOCNLE = SYSTEMZ_INS_STOCNLE, + SYSZ_INS_STOCNLH = SYSTEMZ_INS_STOCNLH, + SYSZ_INS_STOCNM = SYSTEMZ_INS_STOCNM, + SYSZ_INS_STOCNO = SYSTEMZ_INS_STOCNO, + SYSZ_INS_STOCNP = SYSTEMZ_INS_STOCNP, + SYSZ_INS_STOCNZ = SYSTEMZ_INS_STOCNZ, + SYSZ_INS_STOCO = SYSTEMZ_INS_STOCO, + SYSZ_INS_STOCP = SYSTEMZ_INS_STOCP, + SYSZ_INS_STOCZ = SYSTEMZ_INS_STOCZ, + SYSZ_INS_STOCFH = SYSTEMZ_INS_STOCFH, + SYSZ_INS_STOCFHE = SYSTEMZ_INS_STOCFHE, + SYSZ_INS_STOCFHH = SYSTEMZ_INS_STOCFHH, + SYSZ_INS_STOCFHHE = SYSTEMZ_INS_STOCFHHE, + SYSZ_INS_STOCFHL = SYSTEMZ_INS_STOCFHL, + SYSZ_INS_STOCFHLE = SYSTEMZ_INS_STOCFHLE, + SYSZ_INS_STOCFHLH = SYSTEMZ_INS_STOCFHLH, + SYSZ_INS_STOCFHM = SYSTEMZ_INS_STOCFHM, + SYSZ_INS_STOCFHNE = SYSTEMZ_INS_STOCFHNE, + SYSZ_INS_STOCFHNH = SYSTEMZ_INS_STOCFHNH, + SYSZ_INS_STOCFHNHE = SYSTEMZ_INS_STOCFHNHE, + SYSZ_INS_STOCFHNL = SYSTEMZ_INS_STOCFHNL, + SYSZ_INS_STOCFHNLE = SYSTEMZ_INS_STOCFHNLE, + SYSZ_INS_STOCFHNLH = SYSTEMZ_INS_STOCFHNLH, + SYSZ_INS_STOCFHNM = SYSTEMZ_INS_STOCFHNM, + SYSZ_INS_STOCFHNO = SYSTEMZ_INS_STOCFHNO, + SYSZ_INS_STOCFHNP = SYSTEMZ_INS_STOCFHNP, + SYSZ_INS_STOCFHNZ = SYSTEMZ_INS_STOCFHNZ, + SYSZ_INS_STOCFHO = SYSTEMZ_INS_STOCFHO, + SYSZ_INS_STOCFHP = SYSTEMZ_INS_STOCFHP, + SYSZ_INS_STOCFHZ = SYSTEMZ_INS_STOCFHZ, + SYSZ_INS_STOCG = SYSTEMZ_INS_STOCG, + SYSZ_INS_STOCGE = SYSTEMZ_INS_STOCGE, + SYSZ_INS_STOCGH = SYSTEMZ_INS_STOCGH, + SYSZ_INS_STOCGHE = SYSTEMZ_INS_STOCGHE, + SYSZ_INS_STOCGL = SYSTEMZ_INS_STOCGL, + SYSZ_INS_STOCGLE = SYSTEMZ_INS_STOCGLE, + SYSZ_INS_STOCGLH = SYSTEMZ_INS_STOCGLH, + SYSZ_INS_STOCGM = SYSTEMZ_INS_STOCGM, + SYSZ_INS_STOCGNE = SYSTEMZ_INS_STOCGNE, + SYSZ_INS_STOCGNH = SYSTEMZ_INS_STOCGNH, + SYSZ_INS_STOCGNHE = SYSTEMZ_INS_STOCGNHE, + SYSZ_INS_STOCGNL = SYSTEMZ_INS_STOCGNL, + SYSZ_INS_STOCGNLE = SYSTEMZ_INS_STOCGNLE, + SYSZ_INS_STOCGNLH = SYSTEMZ_INS_STOCGNLH, + SYSZ_INS_STOCGNM = SYSTEMZ_INS_STOCGNM, + SYSZ_INS_STOCGNO = SYSTEMZ_INS_STOCGNO, + SYSZ_INS_STOCGNP = SYSTEMZ_INS_STOCGNP, + SYSZ_INS_STOCGNZ = SYSTEMZ_INS_STOCGNZ, + SYSZ_INS_STOCGO = SYSTEMZ_INS_STOCGO, + SYSZ_INS_STOCGP = SYSTEMZ_INS_STOCGP, + SYSZ_INS_STOCGZ = SYSTEMZ_INS_STOCGZ, + SYSZ_INS_STOSM = SYSTEMZ_INS_STOSM, + SYSZ_INS_STPQ = SYSTEMZ_INS_STPQ, + SYSZ_INS_STPT = SYSTEMZ_INS_STPT, + SYSZ_INS_STPX = SYSTEMZ_INS_STPX, + SYSZ_INS_STRAG = SYSTEMZ_INS_STRAG, + SYSZ_INS_STRL = SYSTEMZ_INS_STRL, + SYSZ_INS_STRV = SYSTEMZ_INS_STRV, + SYSZ_INS_STRVG = SYSTEMZ_INS_STRVG, + SYSZ_INS_STRVH = SYSTEMZ_INS_STRVH, + SYSZ_INS_STSCH = SYSTEMZ_INS_STSCH, + SYSZ_INS_STSI = SYSTEMZ_INS_STSI, + SYSZ_INS_STURA = SYSTEMZ_INS_STURA, + SYSZ_INS_STURG = SYSTEMZ_INS_STURG, + SYSZ_INS_STY = SYSTEMZ_INS_STY, + SYSZ_INS_SU = SYSTEMZ_INS_SU, + SYSZ_INS_SUR = SYSTEMZ_INS_SUR, + SYSZ_INS_SVC = SYSTEMZ_INS_SVC, + SYSZ_INS_SW = SYSTEMZ_INS_SW, + SYSZ_INS_SWR = SYSTEMZ_INS_SWR, + SYSZ_INS_SXBR = SYSTEMZ_INS_SXBR, + SYSZ_INS_SXR = SYSTEMZ_INS_SXR, + SYSZ_INS_SXTR = SYSTEMZ_INS_SXTR, + SYSZ_INS_SXTRA = SYSTEMZ_INS_SXTRA, + SYSZ_INS_SY = SYSTEMZ_INS_SY, + SYSZ_INS_TABORT = SYSTEMZ_INS_TABORT, + SYSZ_INS_TAM = SYSTEMZ_INS_TAM, + SYSZ_INS_TAR = SYSTEMZ_INS_TAR, + SYSZ_INS_TB = SYSTEMZ_INS_TB, + SYSZ_INS_TBDR = SYSTEMZ_INS_TBDR, + SYSZ_INS_TBEDR = SYSTEMZ_INS_TBEDR, + SYSZ_INS_TBEGIN = SYSTEMZ_INS_TBEGIN, + SYSZ_INS_TBEGINC = SYSTEMZ_INS_TBEGINC, + SYSZ_INS_TCDB = SYSTEMZ_INS_TCDB, + SYSZ_INS_TCEB = SYSTEMZ_INS_TCEB, + SYSZ_INS_TCXB = SYSTEMZ_INS_TCXB, + SYSZ_INS_TDCDT = SYSTEMZ_INS_TDCDT, + SYSZ_INS_TDCET = SYSTEMZ_INS_TDCET, + SYSZ_INS_TDCXT = SYSTEMZ_INS_TDCXT, + SYSZ_INS_TDGDT = SYSTEMZ_INS_TDGDT, + SYSZ_INS_TDGET = SYSTEMZ_INS_TDGET, + SYSZ_INS_TDGXT = SYSTEMZ_INS_TDGXT, + SYSZ_INS_TEND = SYSTEMZ_INS_TEND, + SYSZ_INS_THDER = SYSTEMZ_INS_THDER, + SYSZ_INS_THDR = SYSTEMZ_INS_THDR, + SYSZ_INS_TM = SYSTEMZ_INS_TM, + SYSZ_INS_TMHH = SYSTEMZ_INS_TMHH, + SYSZ_INS_TMHL = SYSTEMZ_INS_TMHL, + SYSZ_INS_TMLH = SYSTEMZ_INS_TMLH, + SYSZ_INS_TMLL = SYSTEMZ_INS_TMLL, + SYSZ_INS_TMY = SYSTEMZ_INS_TMY, + SYSZ_INS_TP = SYSTEMZ_INS_TP, + SYSZ_INS_TPI = SYSTEMZ_INS_TPI, + SYSZ_INS_TPROT = SYSTEMZ_INS_TPROT, + SYSZ_INS_TR = SYSTEMZ_INS_TR, + SYSZ_INS_TRACE = SYSTEMZ_INS_TRACE, + SYSZ_INS_TRACG = SYSTEMZ_INS_TRACG, + SYSZ_INS_TRAP2 = SYSTEMZ_INS_TRAP2, + SYSZ_INS_TRAP4 = SYSTEMZ_INS_TRAP4, + SYSZ_INS_TRE = SYSTEMZ_INS_TRE, + SYSZ_INS_TROO = SYSTEMZ_INS_TROO, + SYSZ_INS_TROT = SYSTEMZ_INS_TROT, + SYSZ_INS_TRT = SYSTEMZ_INS_TRT, + SYSZ_INS_TRTE = SYSTEMZ_INS_TRTE, + SYSZ_INS_TRTO = SYSTEMZ_INS_TRTO, + SYSZ_INS_TRTR = SYSTEMZ_INS_TRTR, + SYSZ_INS_TRTRE = SYSTEMZ_INS_TRTRE, + SYSZ_INS_TRTT = SYSTEMZ_INS_TRTT, + SYSZ_INS_TS = SYSTEMZ_INS_TS, + SYSZ_INS_TSCH = SYSTEMZ_INS_TSCH, + SYSZ_INS_UNPK = SYSTEMZ_INS_UNPK, + SYSZ_INS_UNPKA = SYSTEMZ_INS_UNPKA, + SYSZ_INS_UNPKU = SYSTEMZ_INS_UNPKU, + SYSZ_INS_UPT = SYSTEMZ_INS_UPT, + SYSZ_INS_VA = SYSTEMZ_INS_VA, + SYSZ_INS_VAB = SYSTEMZ_INS_VAB, + SYSZ_INS_VAC = SYSTEMZ_INS_VAC, + SYSZ_INS_VACC = SYSTEMZ_INS_VACC, + SYSZ_INS_VACCB = SYSTEMZ_INS_VACCB, + SYSZ_INS_VACCC = SYSTEMZ_INS_VACCC, + SYSZ_INS_VACCCQ = SYSTEMZ_INS_VACCCQ, + SYSZ_INS_VACCF = SYSTEMZ_INS_VACCF, + SYSZ_INS_VACCG = SYSTEMZ_INS_VACCG, + SYSZ_INS_VACCH = SYSTEMZ_INS_VACCH, + SYSZ_INS_VACCQ = SYSTEMZ_INS_VACCQ, + SYSZ_INS_VACQ = SYSTEMZ_INS_VACQ, + SYSZ_INS_VAF = SYSTEMZ_INS_VAF, + SYSZ_INS_VAG = SYSTEMZ_INS_VAG, + SYSZ_INS_VAH = SYSTEMZ_INS_VAH, + SYSZ_INS_VAP = SYSTEMZ_INS_VAP, + SYSZ_INS_VAQ = SYSTEMZ_INS_VAQ, + SYSZ_INS_VAVG = SYSTEMZ_INS_VAVG, + SYSZ_INS_VAVGB = SYSTEMZ_INS_VAVGB, + SYSZ_INS_VAVGF = SYSTEMZ_INS_VAVGF, + SYSZ_INS_VAVGG = SYSTEMZ_INS_VAVGG, + SYSZ_INS_VAVGH = SYSTEMZ_INS_VAVGH, + SYSZ_INS_VAVGL = SYSTEMZ_INS_VAVGL, + SYSZ_INS_VAVGLB = SYSTEMZ_INS_VAVGLB, + SYSZ_INS_VAVGLF = SYSTEMZ_INS_VAVGLF, + SYSZ_INS_VAVGLG = SYSTEMZ_INS_VAVGLG, + SYSZ_INS_VAVGLH = SYSTEMZ_INS_VAVGLH, + SYSZ_INS_VBPERM = SYSTEMZ_INS_VBPERM, + SYSZ_INS_VCDG = SYSTEMZ_INS_VCDG, + SYSZ_INS_VCDGB = SYSTEMZ_INS_VCDGB, + SYSZ_INS_VCDLG = SYSTEMZ_INS_VCDLG, + SYSZ_INS_VCDLGB = SYSTEMZ_INS_VCDLGB, + SYSZ_INS_VCEFB = SYSTEMZ_INS_VCEFB, + SYSZ_INS_VCELFB = SYSTEMZ_INS_VCELFB, + SYSZ_INS_VCEQ = SYSTEMZ_INS_VCEQ, + SYSZ_INS_VCEQB = SYSTEMZ_INS_VCEQB, + SYSZ_INS_VCEQBS = SYSTEMZ_INS_VCEQBS, + SYSZ_INS_VCEQF = SYSTEMZ_INS_VCEQF, + SYSZ_INS_VCEQFS = SYSTEMZ_INS_VCEQFS, + SYSZ_INS_VCEQG = SYSTEMZ_INS_VCEQG, + SYSZ_INS_VCEQGS = SYSTEMZ_INS_VCEQGS, + SYSZ_INS_VCEQH = SYSTEMZ_INS_VCEQH, + SYSZ_INS_VCEQHS = SYSTEMZ_INS_VCEQHS, + SYSZ_INS_VCFEB = SYSTEMZ_INS_VCFEB, + SYSZ_INS_VCFN = SYSTEMZ_INS_VCFN, + SYSZ_INS_VCFPL = SYSTEMZ_INS_VCFPL, + SYSZ_INS_VCFPS = SYSTEMZ_INS_VCFPS, + SYSZ_INS_VCGD = SYSTEMZ_INS_VCGD, + SYSZ_INS_VCGDB = SYSTEMZ_INS_VCGDB, + SYSZ_INS_VCH = SYSTEMZ_INS_VCH, + SYSZ_INS_VCHB = SYSTEMZ_INS_VCHB, + SYSZ_INS_VCHBS = SYSTEMZ_INS_VCHBS, + SYSZ_INS_VCHF = SYSTEMZ_INS_VCHF, + SYSZ_INS_VCHFS = SYSTEMZ_INS_VCHFS, + SYSZ_INS_VCHG = SYSTEMZ_INS_VCHG, + SYSZ_INS_VCHGS = SYSTEMZ_INS_VCHGS, + SYSZ_INS_VCHH = SYSTEMZ_INS_VCHH, + SYSZ_INS_VCHHS = SYSTEMZ_INS_VCHHS, + SYSZ_INS_VCHL = SYSTEMZ_INS_VCHL, + SYSZ_INS_VCHLB = SYSTEMZ_INS_VCHLB, + SYSZ_INS_VCHLBS = SYSTEMZ_INS_VCHLBS, + SYSZ_INS_VCHLF = SYSTEMZ_INS_VCHLF, + SYSZ_INS_VCHLFS = SYSTEMZ_INS_VCHLFS, + SYSZ_INS_VCHLG = SYSTEMZ_INS_VCHLG, + SYSZ_INS_VCHLGS = SYSTEMZ_INS_VCHLGS, + SYSZ_INS_VCHLH = SYSTEMZ_INS_VCHLH, + SYSZ_INS_VCHLHS = SYSTEMZ_INS_VCHLHS, + SYSZ_INS_VCKSM = SYSTEMZ_INS_VCKSM, + SYSZ_INS_VCLFEB = SYSTEMZ_INS_VCLFEB, + SYSZ_INS_VCLFNH = SYSTEMZ_INS_VCLFNH, + SYSZ_INS_VCLFNL = SYSTEMZ_INS_VCLFNL, + SYSZ_INS_VCLFP = SYSTEMZ_INS_VCLFP, + SYSZ_INS_VCLGD = SYSTEMZ_INS_VCLGD, + SYSZ_INS_VCLGDB = SYSTEMZ_INS_VCLGDB, + SYSZ_INS_VCLZ = SYSTEMZ_INS_VCLZ, + SYSZ_INS_VCLZB = SYSTEMZ_INS_VCLZB, + SYSZ_INS_VCLZDP = SYSTEMZ_INS_VCLZDP, + SYSZ_INS_VCLZF = SYSTEMZ_INS_VCLZF, + SYSZ_INS_VCLZG = SYSTEMZ_INS_VCLZG, + SYSZ_INS_VCLZH = SYSTEMZ_INS_VCLZH, + SYSZ_INS_VCNF = SYSTEMZ_INS_VCNF, + SYSZ_INS_VCP = SYSTEMZ_INS_VCP, + SYSZ_INS_VCRNF = SYSTEMZ_INS_VCRNF, + SYSZ_INS_VCSFP = SYSTEMZ_INS_VCSFP, + SYSZ_INS_VCSPH = SYSTEMZ_INS_VCSPH, + SYSZ_INS_VCTZ = SYSTEMZ_INS_VCTZ, + SYSZ_INS_VCTZB = SYSTEMZ_INS_VCTZB, + SYSZ_INS_VCTZF = SYSTEMZ_INS_VCTZF, + SYSZ_INS_VCTZG = SYSTEMZ_INS_VCTZG, + SYSZ_INS_VCTZH = SYSTEMZ_INS_VCTZH, + SYSZ_INS_VCVB = SYSTEMZ_INS_VCVB, + SYSZ_INS_VCVBG = SYSTEMZ_INS_VCVBG, + SYSZ_INS_VCVD = SYSTEMZ_INS_VCVD, + SYSZ_INS_VCVDG = SYSTEMZ_INS_VCVDG, + SYSZ_INS_VDP = SYSTEMZ_INS_VDP, + SYSZ_INS_VEC = SYSTEMZ_INS_VEC, + SYSZ_INS_VECB = SYSTEMZ_INS_VECB, + SYSZ_INS_VECF = SYSTEMZ_INS_VECF, + SYSZ_INS_VECG = SYSTEMZ_INS_VECG, + SYSZ_INS_VECH = SYSTEMZ_INS_VECH, + SYSZ_INS_VECL = SYSTEMZ_INS_VECL, + SYSZ_INS_VECLB = SYSTEMZ_INS_VECLB, + SYSZ_INS_VECLF = SYSTEMZ_INS_VECLF, + SYSZ_INS_VECLG = SYSTEMZ_INS_VECLG, + SYSZ_INS_VECLH = SYSTEMZ_INS_VECLH, + SYSZ_INS_VERIM = SYSTEMZ_INS_VERIM, + SYSZ_INS_VERIMB = SYSTEMZ_INS_VERIMB, + SYSZ_INS_VERIMF = SYSTEMZ_INS_VERIMF, + SYSZ_INS_VERIMG = SYSTEMZ_INS_VERIMG, + SYSZ_INS_VERIMH = SYSTEMZ_INS_VERIMH, + SYSZ_INS_VERLL = SYSTEMZ_INS_VERLL, + SYSZ_INS_VERLLB = SYSTEMZ_INS_VERLLB, + SYSZ_INS_VERLLF = SYSTEMZ_INS_VERLLF, + SYSZ_INS_VERLLG = SYSTEMZ_INS_VERLLG, + SYSZ_INS_VERLLH = SYSTEMZ_INS_VERLLH, + SYSZ_INS_VERLLV = SYSTEMZ_INS_VERLLV, + SYSZ_INS_VERLLVB = SYSTEMZ_INS_VERLLVB, + SYSZ_INS_VERLLVF = SYSTEMZ_INS_VERLLVF, + SYSZ_INS_VERLLVG = SYSTEMZ_INS_VERLLVG, + SYSZ_INS_VERLLVH = SYSTEMZ_INS_VERLLVH, + SYSZ_INS_VESL = SYSTEMZ_INS_VESL, + SYSZ_INS_VESLB = SYSTEMZ_INS_VESLB, + SYSZ_INS_VESLF = SYSTEMZ_INS_VESLF, + SYSZ_INS_VESLG = SYSTEMZ_INS_VESLG, + SYSZ_INS_VESLH = SYSTEMZ_INS_VESLH, + SYSZ_INS_VESLV = SYSTEMZ_INS_VESLV, + SYSZ_INS_VESLVB = SYSTEMZ_INS_VESLVB, + SYSZ_INS_VESLVF = SYSTEMZ_INS_VESLVF, + SYSZ_INS_VESLVG = SYSTEMZ_INS_VESLVG, + SYSZ_INS_VESLVH = SYSTEMZ_INS_VESLVH, + SYSZ_INS_VESRA = SYSTEMZ_INS_VESRA, + SYSZ_INS_VESRAB = SYSTEMZ_INS_VESRAB, + SYSZ_INS_VESRAF = SYSTEMZ_INS_VESRAF, + SYSZ_INS_VESRAG = SYSTEMZ_INS_VESRAG, + SYSZ_INS_VESRAH = SYSTEMZ_INS_VESRAH, + SYSZ_INS_VESRAV = SYSTEMZ_INS_VESRAV, + SYSZ_INS_VESRAVB = SYSTEMZ_INS_VESRAVB, + SYSZ_INS_VESRAVF = SYSTEMZ_INS_VESRAVF, + SYSZ_INS_VESRAVG = SYSTEMZ_INS_VESRAVG, + SYSZ_INS_VESRAVH = SYSTEMZ_INS_VESRAVH, + SYSZ_INS_VESRL = SYSTEMZ_INS_VESRL, + SYSZ_INS_VESRLB = SYSTEMZ_INS_VESRLB, + SYSZ_INS_VESRLF = SYSTEMZ_INS_VESRLF, + SYSZ_INS_VESRLG = SYSTEMZ_INS_VESRLG, + SYSZ_INS_VESRLH = SYSTEMZ_INS_VESRLH, + SYSZ_INS_VESRLV = SYSTEMZ_INS_VESRLV, + SYSZ_INS_VESRLVB = SYSTEMZ_INS_VESRLVB, + SYSZ_INS_VESRLVF = SYSTEMZ_INS_VESRLVF, + SYSZ_INS_VESRLVG = SYSTEMZ_INS_VESRLVG, + SYSZ_INS_VESRLVH = SYSTEMZ_INS_VESRLVH, + SYSZ_INS_VFA = SYSTEMZ_INS_VFA, + SYSZ_INS_VFADB = SYSTEMZ_INS_VFADB, + SYSZ_INS_VFAE = SYSTEMZ_INS_VFAE, + SYSZ_INS_VFAEB = SYSTEMZ_INS_VFAEB, + SYSZ_INS_VFAEBS = SYSTEMZ_INS_VFAEBS, + SYSZ_INS_VFAEF = SYSTEMZ_INS_VFAEF, + SYSZ_INS_VFAEFS = SYSTEMZ_INS_VFAEFS, + SYSZ_INS_VFAEH = SYSTEMZ_INS_VFAEH, + SYSZ_INS_VFAEHS = SYSTEMZ_INS_VFAEHS, + SYSZ_INS_VFAEZB = SYSTEMZ_INS_VFAEZB, + SYSZ_INS_VFAEZBS = SYSTEMZ_INS_VFAEZBS, + SYSZ_INS_VFAEZF = SYSTEMZ_INS_VFAEZF, + SYSZ_INS_VFAEZFS = SYSTEMZ_INS_VFAEZFS, + SYSZ_INS_VFAEZH = SYSTEMZ_INS_VFAEZH, + SYSZ_INS_VFAEZHS = SYSTEMZ_INS_VFAEZHS, + SYSZ_INS_VFASB = SYSTEMZ_INS_VFASB, + SYSZ_INS_VFCE = SYSTEMZ_INS_VFCE, + SYSZ_INS_VFCEDB = SYSTEMZ_INS_VFCEDB, + SYSZ_INS_VFCEDBS = SYSTEMZ_INS_VFCEDBS, + SYSZ_INS_VFCESB = SYSTEMZ_INS_VFCESB, + SYSZ_INS_VFCESBS = SYSTEMZ_INS_VFCESBS, + SYSZ_INS_VFCH = SYSTEMZ_INS_VFCH, + SYSZ_INS_VFCHDB = SYSTEMZ_INS_VFCHDB, + SYSZ_INS_VFCHDBS = SYSTEMZ_INS_VFCHDBS, + SYSZ_INS_VFCHE = SYSTEMZ_INS_VFCHE, + SYSZ_INS_VFCHEDB = SYSTEMZ_INS_VFCHEDB, + SYSZ_INS_VFCHEDBS = SYSTEMZ_INS_VFCHEDBS, + SYSZ_INS_VFCHESB = SYSTEMZ_INS_VFCHESB, + SYSZ_INS_VFCHESBS = SYSTEMZ_INS_VFCHESBS, + SYSZ_INS_VFCHSB = SYSTEMZ_INS_VFCHSB, + SYSZ_INS_VFCHSBS = SYSTEMZ_INS_VFCHSBS, + SYSZ_INS_VFD = SYSTEMZ_INS_VFD, + SYSZ_INS_VFDDB = SYSTEMZ_INS_VFDDB, + SYSZ_INS_VFDSB = SYSTEMZ_INS_VFDSB, + SYSZ_INS_VFEE = SYSTEMZ_INS_VFEE, + SYSZ_INS_VFEEB = SYSTEMZ_INS_VFEEB, + SYSZ_INS_VFEEBS = SYSTEMZ_INS_VFEEBS, + SYSZ_INS_VFEEF = SYSTEMZ_INS_VFEEF, + SYSZ_INS_VFEEFS = SYSTEMZ_INS_VFEEFS, + SYSZ_INS_VFEEH = SYSTEMZ_INS_VFEEH, + SYSZ_INS_VFEEHS = SYSTEMZ_INS_VFEEHS, + SYSZ_INS_VFEEZB = SYSTEMZ_INS_VFEEZB, + SYSZ_INS_VFEEZBS = SYSTEMZ_INS_VFEEZBS, + SYSZ_INS_VFEEZF = SYSTEMZ_INS_VFEEZF, + SYSZ_INS_VFEEZFS = SYSTEMZ_INS_VFEEZFS, + SYSZ_INS_VFEEZH = SYSTEMZ_INS_VFEEZH, + SYSZ_INS_VFEEZHS = SYSTEMZ_INS_VFEEZHS, + SYSZ_INS_VFENE = SYSTEMZ_INS_VFENE, + SYSZ_INS_VFENEB = SYSTEMZ_INS_VFENEB, + SYSZ_INS_VFENEBS = SYSTEMZ_INS_VFENEBS, + SYSZ_INS_VFENEF = SYSTEMZ_INS_VFENEF, + SYSZ_INS_VFENEFS = SYSTEMZ_INS_VFENEFS, + SYSZ_INS_VFENEH = SYSTEMZ_INS_VFENEH, + SYSZ_INS_VFENEHS = SYSTEMZ_INS_VFENEHS, + SYSZ_INS_VFENEZB = SYSTEMZ_INS_VFENEZB, + SYSZ_INS_VFENEZBS = SYSTEMZ_INS_VFENEZBS, + SYSZ_INS_VFENEZF = SYSTEMZ_INS_VFENEZF, + SYSZ_INS_VFENEZFS = SYSTEMZ_INS_VFENEZFS, + SYSZ_INS_VFENEZH = SYSTEMZ_INS_VFENEZH, + SYSZ_INS_VFENEZHS = SYSTEMZ_INS_VFENEZHS, + SYSZ_INS_VFI = SYSTEMZ_INS_VFI, + SYSZ_INS_VFIDB = SYSTEMZ_INS_VFIDB, + SYSZ_INS_VFISB = SYSTEMZ_INS_VFISB, + SYSZ_INS_VFKEDB = SYSTEMZ_INS_VFKEDB, + SYSZ_INS_VFKEDBS = SYSTEMZ_INS_VFKEDBS, + SYSZ_INS_VFKESB = SYSTEMZ_INS_VFKESB, + SYSZ_INS_VFKESBS = SYSTEMZ_INS_VFKESBS, + SYSZ_INS_VFKHDB = SYSTEMZ_INS_VFKHDB, + SYSZ_INS_VFKHDBS = SYSTEMZ_INS_VFKHDBS, + SYSZ_INS_VFKHEDB = SYSTEMZ_INS_VFKHEDB, + SYSZ_INS_VFKHEDBS = SYSTEMZ_INS_VFKHEDBS, + SYSZ_INS_VFKHESB = SYSTEMZ_INS_VFKHESB, + SYSZ_INS_VFKHESBS = SYSTEMZ_INS_VFKHESBS, + SYSZ_INS_VFKHSB = SYSTEMZ_INS_VFKHSB, + SYSZ_INS_VFKHSBS = SYSTEMZ_INS_VFKHSBS, + SYSZ_INS_VFLCDB = SYSTEMZ_INS_VFLCDB, + SYSZ_INS_VFLCSB = SYSTEMZ_INS_VFLCSB, + SYSZ_INS_VFLL = SYSTEMZ_INS_VFLL, + SYSZ_INS_VFLLS = SYSTEMZ_INS_VFLLS, + SYSZ_INS_VFLNDB = SYSTEMZ_INS_VFLNDB, + SYSZ_INS_VFLNSB = SYSTEMZ_INS_VFLNSB, + SYSZ_INS_VFLPDB = SYSTEMZ_INS_VFLPDB, + SYSZ_INS_VFLPSB = SYSTEMZ_INS_VFLPSB, + SYSZ_INS_VFLR = SYSTEMZ_INS_VFLR, + SYSZ_INS_VFLRD = SYSTEMZ_INS_VFLRD, + SYSZ_INS_VFM = SYSTEMZ_INS_VFM, + SYSZ_INS_VFMA = SYSTEMZ_INS_VFMA, + SYSZ_INS_VFMADB = SYSTEMZ_INS_VFMADB, + SYSZ_INS_VFMASB = SYSTEMZ_INS_VFMASB, + SYSZ_INS_VFMAX = SYSTEMZ_INS_VFMAX, + SYSZ_INS_VFMAXDB = SYSTEMZ_INS_VFMAXDB, + SYSZ_INS_VFMAXSB = SYSTEMZ_INS_VFMAXSB, + SYSZ_INS_VFMDB = SYSTEMZ_INS_VFMDB, + SYSZ_INS_VFMIN = SYSTEMZ_INS_VFMIN, + SYSZ_INS_VFMINDB = SYSTEMZ_INS_VFMINDB, + SYSZ_INS_VFMINSB = SYSTEMZ_INS_VFMINSB, + SYSZ_INS_VFMS = SYSTEMZ_INS_VFMS, + SYSZ_INS_VFMSB = SYSTEMZ_INS_VFMSB, + SYSZ_INS_VFMSDB = SYSTEMZ_INS_VFMSDB, + SYSZ_INS_VFMSSB = SYSTEMZ_INS_VFMSSB, + SYSZ_INS_VFNMA = SYSTEMZ_INS_VFNMA, + SYSZ_INS_VFNMADB = SYSTEMZ_INS_VFNMADB, + SYSZ_INS_VFNMASB = SYSTEMZ_INS_VFNMASB, + SYSZ_INS_VFNMS = SYSTEMZ_INS_VFNMS, + SYSZ_INS_VFNMSDB = SYSTEMZ_INS_VFNMSDB, + SYSZ_INS_VFNMSSB = SYSTEMZ_INS_VFNMSSB, + SYSZ_INS_VFPSO = SYSTEMZ_INS_VFPSO, + SYSZ_INS_VFPSODB = SYSTEMZ_INS_VFPSODB, + SYSZ_INS_VFPSOSB = SYSTEMZ_INS_VFPSOSB, + SYSZ_INS_VFS = SYSTEMZ_INS_VFS, + SYSZ_INS_VFSDB = SYSTEMZ_INS_VFSDB, + SYSZ_INS_VFSQ = SYSTEMZ_INS_VFSQ, + SYSZ_INS_VFSQDB = SYSTEMZ_INS_VFSQDB, + SYSZ_INS_VFSQSB = SYSTEMZ_INS_VFSQSB, + SYSZ_INS_VFSSB = SYSTEMZ_INS_VFSSB, + SYSZ_INS_VFTCI = SYSTEMZ_INS_VFTCI, + SYSZ_INS_VFTCIDB = SYSTEMZ_INS_VFTCIDB, + SYSZ_INS_VFTCISB = SYSTEMZ_INS_VFTCISB, + SYSZ_INS_VGBM = SYSTEMZ_INS_VGBM, + SYSZ_INS_VGEF = SYSTEMZ_INS_VGEF, + SYSZ_INS_VGEG = SYSTEMZ_INS_VGEG, + SYSZ_INS_VGFM = SYSTEMZ_INS_VGFM, + SYSZ_INS_VGFMA = SYSTEMZ_INS_VGFMA, + SYSZ_INS_VGFMAB = SYSTEMZ_INS_VGFMAB, + SYSZ_INS_VGFMAF = SYSTEMZ_INS_VGFMAF, + SYSZ_INS_VGFMAG = SYSTEMZ_INS_VGFMAG, + SYSZ_INS_VGFMAH = SYSTEMZ_INS_VGFMAH, + SYSZ_INS_VGFMB = SYSTEMZ_INS_VGFMB, + SYSZ_INS_VGFMF = SYSTEMZ_INS_VGFMF, + SYSZ_INS_VGFMG = SYSTEMZ_INS_VGFMG, + SYSZ_INS_VGFMH = SYSTEMZ_INS_VGFMH, + SYSZ_INS_VGM = SYSTEMZ_INS_VGM, + SYSZ_INS_VGMB = SYSTEMZ_INS_VGMB, + SYSZ_INS_VGMF = SYSTEMZ_INS_VGMF, + SYSZ_INS_VGMG = SYSTEMZ_INS_VGMG, + SYSZ_INS_VGMH = SYSTEMZ_INS_VGMH, + SYSZ_INS_VISTR = SYSTEMZ_INS_VISTR, + SYSZ_INS_VISTRB = SYSTEMZ_INS_VISTRB, + SYSZ_INS_VISTRBS = SYSTEMZ_INS_VISTRBS, + SYSZ_INS_VISTRF = SYSTEMZ_INS_VISTRF, + SYSZ_INS_VISTRFS = SYSTEMZ_INS_VISTRFS, + SYSZ_INS_VISTRH = SYSTEMZ_INS_VISTRH, + SYSZ_INS_VISTRHS = SYSTEMZ_INS_VISTRHS, + SYSZ_INS_VL = SYSTEMZ_INS_VL, + SYSZ_INS_VLBB = SYSTEMZ_INS_VLBB, + SYSZ_INS_VLBR = SYSTEMZ_INS_VLBR, + SYSZ_INS_VLBRF = SYSTEMZ_INS_VLBRF, + SYSZ_INS_VLBRG = SYSTEMZ_INS_VLBRG, + SYSZ_INS_VLBRH = SYSTEMZ_INS_VLBRH, + SYSZ_INS_VLBRQ = SYSTEMZ_INS_VLBRQ, + SYSZ_INS_VLBRREP = SYSTEMZ_INS_VLBRREP, + SYSZ_INS_VLBRREPF = SYSTEMZ_INS_VLBRREPF, + SYSZ_INS_VLBRREPG = SYSTEMZ_INS_VLBRREPG, + SYSZ_INS_VLBRREPH = SYSTEMZ_INS_VLBRREPH, + SYSZ_INS_VLC = SYSTEMZ_INS_VLC, + SYSZ_INS_VLCB = SYSTEMZ_INS_VLCB, + SYSZ_INS_VLCF = SYSTEMZ_INS_VLCF, + SYSZ_INS_VLCG = SYSTEMZ_INS_VLCG, + SYSZ_INS_VLCH = SYSTEMZ_INS_VLCH, + SYSZ_INS_VLDE = SYSTEMZ_INS_VLDE, + SYSZ_INS_VLDEB = SYSTEMZ_INS_VLDEB, + SYSZ_INS_VLEB = SYSTEMZ_INS_VLEB, + SYSZ_INS_VLEBRF = SYSTEMZ_INS_VLEBRF, + SYSZ_INS_VLEBRG = SYSTEMZ_INS_VLEBRG, + SYSZ_INS_VLEBRH = SYSTEMZ_INS_VLEBRH, + SYSZ_INS_VLED = SYSTEMZ_INS_VLED, + SYSZ_INS_VLEDB = SYSTEMZ_INS_VLEDB, + SYSZ_INS_VLEF = SYSTEMZ_INS_VLEF, + SYSZ_INS_VLEG = SYSTEMZ_INS_VLEG, + SYSZ_INS_VLEH = SYSTEMZ_INS_VLEH, + SYSZ_INS_VLEIB = SYSTEMZ_INS_VLEIB, + SYSZ_INS_VLEIF = SYSTEMZ_INS_VLEIF, + SYSZ_INS_VLEIG = SYSTEMZ_INS_VLEIG, + SYSZ_INS_VLEIH = SYSTEMZ_INS_VLEIH, + SYSZ_INS_VLER = SYSTEMZ_INS_VLER, + SYSZ_INS_VLERF = SYSTEMZ_INS_VLERF, + SYSZ_INS_VLERG = SYSTEMZ_INS_VLERG, + SYSZ_INS_VLERH = SYSTEMZ_INS_VLERH, + SYSZ_INS_VLGV = SYSTEMZ_INS_VLGV, + SYSZ_INS_VLGVB = SYSTEMZ_INS_VLGVB, + SYSZ_INS_VLGVF = SYSTEMZ_INS_VLGVF, + SYSZ_INS_VLGVG = SYSTEMZ_INS_VLGVG, + SYSZ_INS_VLGVH = SYSTEMZ_INS_VLGVH, + SYSZ_INS_VLIP = SYSTEMZ_INS_VLIP, + SYSZ_INS_VLL = SYSTEMZ_INS_VLL, + SYSZ_INS_VLLEBRZ = SYSTEMZ_INS_VLLEBRZ, + SYSZ_INS_VLLEBRZE = SYSTEMZ_INS_VLLEBRZE, + SYSZ_INS_VLLEBRZF = SYSTEMZ_INS_VLLEBRZF, + SYSZ_INS_VLLEBRZG = SYSTEMZ_INS_VLLEBRZG, + SYSZ_INS_VLLEBRZH = SYSTEMZ_INS_VLLEBRZH, + SYSZ_INS_VLLEZ = SYSTEMZ_INS_VLLEZ, + SYSZ_INS_VLLEZB = SYSTEMZ_INS_VLLEZB, + SYSZ_INS_VLLEZF = SYSTEMZ_INS_VLLEZF, + SYSZ_INS_VLLEZG = SYSTEMZ_INS_VLLEZG, + SYSZ_INS_VLLEZH = SYSTEMZ_INS_VLLEZH, + SYSZ_INS_VLLEZLF = SYSTEMZ_INS_VLLEZLF, + SYSZ_INS_VLM = SYSTEMZ_INS_VLM, + SYSZ_INS_VLP = SYSTEMZ_INS_VLP, + SYSZ_INS_VLPB = SYSTEMZ_INS_VLPB, + SYSZ_INS_VLPF = SYSTEMZ_INS_VLPF, + SYSZ_INS_VLPG = SYSTEMZ_INS_VLPG, + SYSZ_INS_VLPH = SYSTEMZ_INS_VLPH, + SYSZ_INS_VLR = SYSTEMZ_INS_VLR, + SYSZ_INS_VLREP = SYSTEMZ_INS_VLREP, + SYSZ_INS_VLREPB = SYSTEMZ_INS_VLREPB, + SYSZ_INS_VLREPF = SYSTEMZ_INS_VLREPF, + SYSZ_INS_VLREPG = SYSTEMZ_INS_VLREPG, + SYSZ_INS_VLREPH = SYSTEMZ_INS_VLREPH, + SYSZ_INS_VLRL = SYSTEMZ_INS_VLRL, + SYSZ_INS_VLRLR = SYSTEMZ_INS_VLRLR, + SYSZ_INS_VLVG = SYSTEMZ_INS_VLVG, + SYSZ_INS_VLVGB = SYSTEMZ_INS_VLVGB, + SYSZ_INS_VLVGF = SYSTEMZ_INS_VLVGF, + SYSZ_INS_VLVGG = SYSTEMZ_INS_VLVGG, + SYSZ_INS_VLVGH = SYSTEMZ_INS_VLVGH, + SYSZ_INS_VLVGP = SYSTEMZ_INS_VLVGP, + SYSZ_INS_VMAE = SYSTEMZ_INS_VMAE, + SYSZ_INS_VMAEB = SYSTEMZ_INS_VMAEB, + SYSZ_INS_VMAEF = SYSTEMZ_INS_VMAEF, + SYSZ_INS_VMAEH = SYSTEMZ_INS_VMAEH, + SYSZ_INS_VMAH = SYSTEMZ_INS_VMAH, + SYSZ_INS_VMAHB = SYSTEMZ_INS_VMAHB, + SYSZ_INS_VMAHF = SYSTEMZ_INS_VMAHF, + SYSZ_INS_VMAHH = SYSTEMZ_INS_VMAHH, + SYSZ_INS_VMAL = SYSTEMZ_INS_VMAL, + SYSZ_INS_VMALB = SYSTEMZ_INS_VMALB, + SYSZ_INS_VMALE = SYSTEMZ_INS_VMALE, + SYSZ_INS_VMALEB = SYSTEMZ_INS_VMALEB, + SYSZ_INS_VMALEF = SYSTEMZ_INS_VMALEF, + SYSZ_INS_VMALEH = SYSTEMZ_INS_VMALEH, + SYSZ_INS_VMALF = SYSTEMZ_INS_VMALF, + SYSZ_INS_VMALH = SYSTEMZ_INS_VMALH, + SYSZ_INS_VMALHB = SYSTEMZ_INS_VMALHB, + SYSZ_INS_VMALHF = SYSTEMZ_INS_VMALHF, + SYSZ_INS_VMALHH = SYSTEMZ_INS_VMALHH, + SYSZ_INS_VMALHW = SYSTEMZ_INS_VMALHW, + SYSZ_INS_VMALO = SYSTEMZ_INS_VMALO, + SYSZ_INS_VMALOB = SYSTEMZ_INS_VMALOB, + SYSZ_INS_VMALOF = SYSTEMZ_INS_VMALOF, + SYSZ_INS_VMALOH = SYSTEMZ_INS_VMALOH, + SYSZ_INS_VMAO = SYSTEMZ_INS_VMAO, + SYSZ_INS_VMAOB = SYSTEMZ_INS_VMAOB, + SYSZ_INS_VMAOF = SYSTEMZ_INS_VMAOF, + SYSZ_INS_VMAOH = SYSTEMZ_INS_VMAOH, + SYSZ_INS_VME = SYSTEMZ_INS_VME, + SYSZ_INS_VMEB = SYSTEMZ_INS_VMEB, + SYSZ_INS_VMEF = SYSTEMZ_INS_VMEF, + SYSZ_INS_VMEH = SYSTEMZ_INS_VMEH, + SYSZ_INS_VMH = SYSTEMZ_INS_VMH, + SYSZ_INS_VMHB = SYSTEMZ_INS_VMHB, + SYSZ_INS_VMHF = SYSTEMZ_INS_VMHF, + SYSZ_INS_VMHH = SYSTEMZ_INS_VMHH, + SYSZ_INS_VML = SYSTEMZ_INS_VML, + SYSZ_INS_VMLB = SYSTEMZ_INS_VMLB, + SYSZ_INS_VMLE = SYSTEMZ_INS_VMLE, + SYSZ_INS_VMLEB = SYSTEMZ_INS_VMLEB, + SYSZ_INS_VMLEF = SYSTEMZ_INS_VMLEF, + SYSZ_INS_VMLEH = SYSTEMZ_INS_VMLEH, + SYSZ_INS_VMLF = SYSTEMZ_INS_VMLF, + SYSZ_INS_VMLH = SYSTEMZ_INS_VMLH, + SYSZ_INS_VMLHB = SYSTEMZ_INS_VMLHB, + SYSZ_INS_VMLHF = SYSTEMZ_INS_VMLHF, + SYSZ_INS_VMLHH = SYSTEMZ_INS_VMLHH, + SYSZ_INS_VMLHW = SYSTEMZ_INS_VMLHW, + SYSZ_INS_VMLO = SYSTEMZ_INS_VMLO, + SYSZ_INS_VMLOB = SYSTEMZ_INS_VMLOB, + SYSZ_INS_VMLOF = SYSTEMZ_INS_VMLOF, + SYSZ_INS_VMLOH = SYSTEMZ_INS_VMLOH, + SYSZ_INS_VMN = SYSTEMZ_INS_VMN, + SYSZ_INS_VMNB = SYSTEMZ_INS_VMNB, + SYSZ_INS_VMNF = SYSTEMZ_INS_VMNF, + SYSZ_INS_VMNG = SYSTEMZ_INS_VMNG, + SYSZ_INS_VMNH = SYSTEMZ_INS_VMNH, + SYSZ_INS_VMNL = SYSTEMZ_INS_VMNL, + SYSZ_INS_VMNLB = SYSTEMZ_INS_VMNLB, + SYSZ_INS_VMNLF = SYSTEMZ_INS_VMNLF, + SYSZ_INS_VMNLG = SYSTEMZ_INS_VMNLG, + SYSZ_INS_VMNLH = SYSTEMZ_INS_VMNLH, + SYSZ_INS_VMO = SYSTEMZ_INS_VMO, + SYSZ_INS_VMOB = SYSTEMZ_INS_VMOB, + SYSZ_INS_VMOF = SYSTEMZ_INS_VMOF, + SYSZ_INS_VMOH = SYSTEMZ_INS_VMOH, + SYSZ_INS_VMP = SYSTEMZ_INS_VMP, + SYSZ_INS_VMRH = SYSTEMZ_INS_VMRH, + SYSZ_INS_VMRHB = SYSTEMZ_INS_VMRHB, + SYSZ_INS_VMRHF = SYSTEMZ_INS_VMRHF, + SYSZ_INS_VMRHG = SYSTEMZ_INS_VMRHG, + SYSZ_INS_VMRHH = SYSTEMZ_INS_VMRHH, + SYSZ_INS_VMRL = SYSTEMZ_INS_VMRL, + SYSZ_INS_VMRLB = SYSTEMZ_INS_VMRLB, + SYSZ_INS_VMRLF = SYSTEMZ_INS_VMRLF, + SYSZ_INS_VMRLG = SYSTEMZ_INS_VMRLG, + SYSZ_INS_VMRLH = SYSTEMZ_INS_VMRLH, + SYSZ_INS_VMSL = SYSTEMZ_INS_VMSL, + SYSZ_INS_VMSLG = SYSTEMZ_INS_VMSLG, + SYSZ_INS_VMSP = SYSTEMZ_INS_VMSP, + SYSZ_INS_VMX = SYSTEMZ_INS_VMX, + SYSZ_INS_VMXB = SYSTEMZ_INS_VMXB, + SYSZ_INS_VMXF = SYSTEMZ_INS_VMXF, + SYSZ_INS_VMXG = SYSTEMZ_INS_VMXG, + SYSZ_INS_VMXH = SYSTEMZ_INS_VMXH, + SYSZ_INS_VMXL = SYSTEMZ_INS_VMXL, + SYSZ_INS_VMXLB = SYSTEMZ_INS_VMXLB, + SYSZ_INS_VMXLF = SYSTEMZ_INS_VMXLF, + SYSZ_INS_VMXLG = SYSTEMZ_INS_VMXLG, + SYSZ_INS_VMXLH = SYSTEMZ_INS_VMXLH, + SYSZ_INS_VN = SYSTEMZ_INS_VN, + SYSZ_INS_VNC = SYSTEMZ_INS_VNC, + SYSZ_INS_VNN = SYSTEMZ_INS_VNN, + SYSZ_INS_VNO = SYSTEMZ_INS_VNO, + SYSZ_INS_VNX = SYSTEMZ_INS_VNX, + SYSZ_INS_VO = SYSTEMZ_INS_VO, + SYSZ_INS_VOC = SYSTEMZ_INS_VOC, + SYSZ_INS_VONE = SYSTEMZ_INS_VONE, + SYSZ_INS_VPDI = SYSTEMZ_INS_VPDI, + SYSZ_INS_VPERM = SYSTEMZ_INS_VPERM, + SYSZ_INS_VPK = SYSTEMZ_INS_VPK, + SYSZ_INS_VPKF = SYSTEMZ_INS_VPKF, + SYSZ_INS_VPKG = SYSTEMZ_INS_VPKG, + SYSZ_INS_VPKH = SYSTEMZ_INS_VPKH, + SYSZ_INS_VPKLS = SYSTEMZ_INS_VPKLS, + SYSZ_INS_VPKLSF = SYSTEMZ_INS_VPKLSF, + SYSZ_INS_VPKLSFS = SYSTEMZ_INS_VPKLSFS, + SYSZ_INS_VPKLSG = SYSTEMZ_INS_VPKLSG, + SYSZ_INS_VPKLSGS = SYSTEMZ_INS_VPKLSGS, + SYSZ_INS_VPKLSH = SYSTEMZ_INS_VPKLSH, + SYSZ_INS_VPKLSHS = SYSTEMZ_INS_VPKLSHS, + SYSZ_INS_VPKS = SYSTEMZ_INS_VPKS, + SYSZ_INS_VPKSF = SYSTEMZ_INS_VPKSF, + SYSZ_INS_VPKSFS = SYSTEMZ_INS_VPKSFS, + SYSZ_INS_VPKSG = SYSTEMZ_INS_VPKSG, + SYSZ_INS_VPKSGS = SYSTEMZ_INS_VPKSGS, + SYSZ_INS_VPKSH = SYSTEMZ_INS_VPKSH, + SYSZ_INS_VPKSHS = SYSTEMZ_INS_VPKSHS, + SYSZ_INS_VPKZ = SYSTEMZ_INS_VPKZ, + SYSZ_INS_VPKZR = SYSTEMZ_INS_VPKZR, + SYSZ_INS_VPOPCT = SYSTEMZ_INS_VPOPCT, + SYSZ_INS_VPOPCTB = SYSTEMZ_INS_VPOPCTB, + SYSZ_INS_VPOPCTF = SYSTEMZ_INS_VPOPCTF, + SYSZ_INS_VPOPCTG = SYSTEMZ_INS_VPOPCTG, + SYSZ_INS_VPOPCTH = SYSTEMZ_INS_VPOPCTH, + SYSZ_INS_VPSOP = SYSTEMZ_INS_VPSOP, + SYSZ_INS_VREP = SYSTEMZ_INS_VREP, + SYSZ_INS_VREPB = SYSTEMZ_INS_VREPB, + SYSZ_INS_VREPF = SYSTEMZ_INS_VREPF, + SYSZ_INS_VREPG = SYSTEMZ_INS_VREPG, + SYSZ_INS_VREPH = SYSTEMZ_INS_VREPH, + SYSZ_INS_VREPI = SYSTEMZ_INS_VREPI, + SYSZ_INS_VREPIB = SYSTEMZ_INS_VREPIB, + SYSZ_INS_VREPIF = SYSTEMZ_INS_VREPIF, + SYSZ_INS_VREPIG = SYSTEMZ_INS_VREPIG, + SYSZ_INS_VREPIH = SYSTEMZ_INS_VREPIH, + SYSZ_INS_VRP = SYSTEMZ_INS_VRP, + SYSZ_INS_VS = SYSTEMZ_INS_VS, + SYSZ_INS_VSB = SYSTEMZ_INS_VSB, + SYSZ_INS_VSBCBI = SYSTEMZ_INS_VSBCBI, + SYSZ_INS_VSBCBIQ = SYSTEMZ_INS_VSBCBIQ, + SYSZ_INS_VSBI = SYSTEMZ_INS_VSBI, + SYSZ_INS_VSBIQ = SYSTEMZ_INS_VSBIQ, + SYSZ_INS_VSCBI = SYSTEMZ_INS_VSCBI, + SYSZ_INS_VSCBIB = SYSTEMZ_INS_VSCBIB, + SYSZ_INS_VSCBIF = SYSTEMZ_INS_VSCBIF, + SYSZ_INS_VSCBIG = SYSTEMZ_INS_VSCBIG, + SYSZ_INS_VSCBIH = SYSTEMZ_INS_VSCBIH, + SYSZ_INS_VSCBIQ = SYSTEMZ_INS_VSCBIQ, + SYSZ_INS_VSCEF = SYSTEMZ_INS_VSCEF, + SYSZ_INS_VSCEG = SYSTEMZ_INS_VSCEG, + SYSZ_INS_VSCHDP = SYSTEMZ_INS_VSCHDP, + SYSZ_INS_VSCHP = SYSTEMZ_INS_VSCHP, + SYSZ_INS_VSCHSP = SYSTEMZ_INS_VSCHSP, + SYSZ_INS_VSCHXP = SYSTEMZ_INS_VSCHXP, + SYSZ_INS_VSCSHP = SYSTEMZ_INS_VSCSHP, + SYSZ_INS_VSDP = SYSTEMZ_INS_VSDP, + SYSZ_INS_VSEG = SYSTEMZ_INS_VSEG, + SYSZ_INS_VSEGB = SYSTEMZ_INS_VSEGB, + SYSZ_INS_VSEGF = SYSTEMZ_INS_VSEGF, + SYSZ_INS_VSEGH = SYSTEMZ_INS_VSEGH, + SYSZ_INS_VSEL = SYSTEMZ_INS_VSEL, + SYSZ_INS_VSF = SYSTEMZ_INS_VSF, + SYSZ_INS_VSG = SYSTEMZ_INS_VSG, + SYSZ_INS_VSH = SYSTEMZ_INS_VSH, + SYSZ_INS_VSL = SYSTEMZ_INS_VSL, + SYSZ_INS_VSLB = SYSTEMZ_INS_VSLB, + SYSZ_INS_VSLD = SYSTEMZ_INS_VSLD, + SYSZ_INS_VSLDB = SYSTEMZ_INS_VSLDB, + SYSZ_INS_VSP = SYSTEMZ_INS_VSP, + SYSZ_INS_VSQ = SYSTEMZ_INS_VSQ, + SYSZ_INS_VSRA = SYSTEMZ_INS_VSRA, + SYSZ_INS_VSRAB = SYSTEMZ_INS_VSRAB, + SYSZ_INS_VSRD = SYSTEMZ_INS_VSRD, + SYSZ_INS_VSRL = SYSTEMZ_INS_VSRL, + SYSZ_INS_VSRLB = SYSTEMZ_INS_VSRLB, + SYSZ_INS_VSRP = SYSTEMZ_INS_VSRP, + SYSZ_INS_VSRPR = SYSTEMZ_INS_VSRPR, + SYSZ_INS_VST = SYSTEMZ_INS_VST, + SYSZ_INS_VSTBR = SYSTEMZ_INS_VSTBR, + SYSZ_INS_VSTBRF = SYSTEMZ_INS_VSTBRF, + SYSZ_INS_VSTBRG = SYSTEMZ_INS_VSTBRG, + SYSZ_INS_VSTBRH = SYSTEMZ_INS_VSTBRH, + SYSZ_INS_VSTBRQ = SYSTEMZ_INS_VSTBRQ, + SYSZ_INS_VSTEB = SYSTEMZ_INS_VSTEB, + SYSZ_INS_VSTEBRF = SYSTEMZ_INS_VSTEBRF, + SYSZ_INS_VSTEBRG = SYSTEMZ_INS_VSTEBRG, + SYSZ_INS_VSTEBRH = SYSTEMZ_INS_VSTEBRH, + SYSZ_INS_VSTEF = SYSTEMZ_INS_VSTEF, + SYSZ_INS_VSTEG = SYSTEMZ_INS_VSTEG, + SYSZ_INS_VSTEH = SYSTEMZ_INS_VSTEH, + SYSZ_INS_VSTER = SYSTEMZ_INS_VSTER, + SYSZ_INS_VSTERF = SYSTEMZ_INS_VSTERF, + SYSZ_INS_VSTERG = SYSTEMZ_INS_VSTERG, + SYSZ_INS_VSTERH = SYSTEMZ_INS_VSTERH, + SYSZ_INS_VSTL = SYSTEMZ_INS_VSTL, + SYSZ_INS_VSTM = SYSTEMZ_INS_VSTM, + SYSZ_INS_VSTRC = SYSTEMZ_INS_VSTRC, + SYSZ_INS_VSTRCB = SYSTEMZ_INS_VSTRCB, + SYSZ_INS_VSTRCBS = SYSTEMZ_INS_VSTRCBS, + SYSZ_INS_VSTRCF = SYSTEMZ_INS_VSTRCF, + SYSZ_INS_VSTRCFS = SYSTEMZ_INS_VSTRCFS, + SYSZ_INS_VSTRCH = SYSTEMZ_INS_VSTRCH, + SYSZ_INS_VSTRCHS = SYSTEMZ_INS_VSTRCHS, + SYSZ_INS_VSTRCZB = SYSTEMZ_INS_VSTRCZB, + SYSZ_INS_VSTRCZBS = SYSTEMZ_INS_VSTRCZBS, + SYSZ_INS_VSTRCZF = SYSTEMZ_INS_VSTRCZF, + SYSZ_INS_VSTRCZFS = SYSTEMZ_INS_VSTRCZFS, + SYSZ_INS_VSTRCZH = SYSTEMZ_INS_VSTRCZH, + SYSZ_INS_VSTRCZHS = SYSTEMZ_INS_VSTRCZHS, + SYSZ_INS_VSTRL = SYSTEMZ_INS_VSTRL, + SYSZ_INS_VSTRLR = SYSTEMZ_INS_VSTRLR, + SYSZ_INS_VSTRS = SYSTEMZ_INS_VSTRS, + SYSZ_INS_VSTRSB = SYSTEMZ_INS_VSTRSB, + SYSZ_INS_VSTRSF = SYSTEMZ_INS_VSTRSF, + SYSZ_INS_VSTRSH = SYSTEMZ_INS_VSTRSH, + SYSZ_INS_VSTRSZB = SYSTEMZ_INS_VSTRSZB, + SYSZ_INS_VSTRSZF = SYSTEMZ_INS_VSTRSZF, + SYSZ_INS_VSTRSZH = SYSTEMZ_INS_VSTRSZH, + SYSZ_INS_VSUM = SYSTEMZ_INS_VSUM, + SYSZ_INS_VSUMB = SYSTEMZ_INS_VSUMB, + SYSZ_INS_VSUMG = SYSTEMZ_INS_VSUMG, + SYSZ_INS_VSUMGF = SYSTEMZ_INS_VSUMGF, + SYSZ_INS_VSUMGH = SYSTEMZ_INS_VSUMGH, + SYSZ_INS_VSUMH = SYSTEMZ_INS_VSUMH, + SYSZ_INS_VSUMQ = SYSTEMZ_INS_VSUMQ, + SYSZ_INS_VSUMQF = SYSTEMZ_INS_VSUMQF, + SYSZ_INS_VSUMQG = SYSTEMZ_INS_VSUMQG, + SYSZ_INS_VTM = SYSTEMZ_INS_VTM, + SYSZ_INS_VTP = SYSTEMZ_INS_VTP, + SYSZ_INS_VUPH = SYSTEMZ_INS_VUPH, + SYSZ_INS_VUPHB = SYSTEMZ_INS_VUPHB, + SYSZ_INS_VUPHF = SYSTEMZ_INS_VUPHF, + SYSZ_INS_VUPHH = SYSTEMZ_INS_VUPHH, + SYSZ_INS_VUPKZ = SYSTEMZ_INS_VUPKZ, + SYSZ_INS_VUPKZH = SYSTEMZ_INS_VUPKZH, + SYSZ_INS_VUPKZL = SYSTEMZ_INS_VUPKZL, + SYSZ_INS_VUPL = SYSTEMZ_INS_VUPL, + SYSZ_INS_VUPLB = SYSTEMZ_INS_VUPLB, + SYSZ_INS_VUPLF = SYSTEMZ_INS_VUPLF, + SYSZ_INS_VUPLH = SYSTEMZ_INS_VUPLH, + SYSZ_INS_VUPLHB = SYSTEMZ_INS_VUPLHB, + SYSZ_INS_VUPLHF = SYSTEMZ_INS_VUPLHF, + SYSZ_INS_VUPLHH = SYSTEMZ_INS_VUPLHH, + SYSZ_INS_VUPLHW = SYSTEMZ_INS_VUPLHW, + SYSZ_INS_VUPLL = SYSTEMZ_INS_VUPLL, + SYSZ_INS_VUPLLB = SYSTEMZ_INS_VUPLLB, + SYSZ_INS_VUPLLF = SYSTEMZ_INS_VUPLLF, + SYSZ_INS_VUPLLH = SYSTEMZ_INS_VUPLLH, + SYSZ_INS_VX = SYSTEMZ_INS_VX, + SYSZ_INS_VZERO = SYSTEMZ_INS_VZERO, + SYSZ_INS_WCDGB = SYSTEMZ_INS_WCDGB, + SYSZ_INS_WCDLGB = SYSTEMZ_INS_WCDLGB, + SYSZ_INS_WCEFB = SYSTEMZ_INS_WCEFB, + SYSZ_INS_WCELFB = SYSTEMZ_INS_WCELFB, + SYSZ_INS_WCFEB = SYSTEMZ_INS_WCFEB, + SYSZ_INS_WCGDB = SYSTEMZ_INS_WCGDB, + SYSZ_INS_WCLFEB = SYSTEMZ_INS_WCLFEB, + SYSZ_INS_WCLGDB = SYSTEMZ_INS_WCLGDB, + SYSZ_INS_WFADB = SYSTEMZ_INS_WFADB, + SYSZ_INS_WFASB = SYSTEMZ_INS_WFASB, + SYSZ_INS_WFAXB = SYSTEMZ_INS_WFAXB, + SYSZ_INS_WFC = SYSTEMZ_INS_WFC, + SYSZ_INS_WFCDB = SYSTEMZ_INS_WFCDB, + SYSZ_INS_WFCEDB = SYSTEMZ_INS_WFCEDB, + SYSZ_INS_WFCEDBS = SYSTEMZ_INS_WFCEDBS, + SYSZ_INS_WFCESB = SYSTEMZ_INS_WFCESB, + SYSZ_INS_WFCESBS = SYSTEMZ_INS_WFCESBS, + SYSZ_INS_WFCEXB = SYSTEMZ_INS_WFCEXB, + SYSZ_INS_WFCEXBS = SYSTEMZ_INS_WFCEXBS, + SYSZ_INS_WFCHDB = SYSTEMZ_INS_WFCHDB, + SYSZ_INS_WFCHDBS = SYSTEMZ_INS_WFCHDBS, + SYSZ_INS_WFCHEDB = SYSTEMZ_INS_WFCHEDB, + SYSZ_INS_WFCHEDBS = SYSTEMZ_INS_WFCHEDBS, + SYSZ_INS_WFCHESB = SYSTEMZ_INS_WFCHESB, + SYSZ_INS_WFCHESBS = SYSTEMZ_INS_WFCHESBS, + SYSZ_INS_WFCHEXB = SYSTEMZ_INS_WFCHEXB, + SYSZ_INS_WFCHEXBS = SYSTEMZ_INS_WFCHEXBS, + SYSZ_INS_WFCHSB = SYSTEMZ_INS_WFCHSB, + SYSZ_INS_WFCHSBS = SYSTEMZ_INS_WFCHSBS, + SYSZ_INS_WFCHXB = SYSTEMZ_INS_WFCHXB, + SYSZ_INS_WFCHXBS = SYSTEMZ_INS_WFCHXBS, + SYSZ_INS_WFCSB = SYSTEMZ_INS_WFCSB, + SYSZ_INS_WFCXB = SYSTEMZ_INS_WFCXB, + SYSZ_INS_WFDDB = SYSTEMZ_INS_WFDDB, + SYSZ_INS_WFDSB = SYSTEMZ_INS_WFDSB, + SYSZ_INS_WFDXB = SYSTEMZ_INS_WFDXB, + SYSZ_INS_WFIDB = SYSTEMZ_INS_WFIDB, + SYSZ_INS_WFISB = SYSTEMZ_INS_WFISB, + SYSZ_INS_WFIXB = SYSTEMZ_INS_WFIXB, + SYSZ_INS_WFK = SYSTEMZ_INS_WFK, + SYSZ_INS_WFKDB = SYSTEMZ_INS_WFKDB, + SYSZ_INS_WFKEDB = SYSTEMZ_INS_WFKEDB, + SYSZ_INS_WFKEDBS = SYSTEMZ_INS_WFKEDBS, + SYSZ_INS_WFKESB = SYSTEMZ_INS_WFKESB, + SYSZ_INS_WFKESBS = SYSTEMZ_INS_WFKESBS, + SYSZ_INS_WFKEXB = SYSTEMZ_INS_WFKEXB, + SYSZ_INS_WFKEXBS = SYSTEMZ_INS_WFKEXBS, + SYSZ_INS_WFKHDB = SYSTEMZ_INS_WFKHDB, + SYSZ_INS_WFKHDBS = SYSTEMZ_INS_WFKHDBS, + SYSZ_INS_WFKHEDB = SYSTEMZ_INS_WFKHEDB, + SYSZ_INS_WFKHEDBS = SYSTEMZ_INS_WFKHEDBS, + SYSZ_INS_WFKHESB = SYSTEMZ_INS_WFKHESB, + SYSZ_INS_WFKHESBS = SYSTEMZ_INS_WFKHESBS, + SYSZ_INS_WFKHEXB = SYSTEMZ_INS_WFKHEXB, + SYSZ_INS_WFKHEXBS = SYSTEMZ_INS_WFKHEXBS, + SYSZ_INS_WFKHSB = SYSTEMZ_INS_WFKHSB, + SYSZ_INS_WFKHSBS = SYSTEMZ_INS_WFKHSBS, + SYSZ_INS_WFKHXB = SYSTEMZ_INS_WFKHXB, + SYSZ_INS_WFKHXBS = SYSTEMZ_INS_WFKHXBS, + SYSZ_INS_WFKSB = SYSTEMZ_INS_WFKSB, + SYSZ_INS_WFKXB = SYSTEMZ_INS_WFKXB, + SYSZ_INS_WFLCDB = SYSTEMZ_INS_WFLCDB, + SYSZ_INS_WFLCSB = SYSTEMZ_INS_WFLCSB, + SYSZ_INS_WFLCXB = SYSTEMZ_INS_WFLCXB, + SYSZ_INS_WFLLD = SYSTEMZ_INS_WFLLD, + SYSZ_INS_WFLLS = SYSTEMZ_INS_WFLLS, + SYSZ_INS_WFLNDB = SYSTEMZ_INS_WFLNDB, + SYSZ_INS_WFLNSB = SYSTEMZ_INS_WFLNSB, + SYSZ_INS_WFLNXB = SYSTEMZ_INS_WFLNXB, + SYSZ_INS_WFLPDB = SYSTEMZ_INS_WFLPDB, + SYSZ_INS_WFLPSB = SYSTEMZ_INS_WFLPSB, + SYSZ_INS_WFLPXB = SYSTEMZ_INS_WFLPXB, + SYSZ_INS_WFLRD = SYSTEMZ_INS_WFLRD, + SYSZ_INS_WFLRX = SYSTEMZ_INS_WFLRX, + SYSZ_INS_WFMADB = SYSTEMZ_INS_WFMADB, + SYSZ_INS_WFMASB = SYSTEMZ_INS_WFMASB, + SYSZ_INS_WFMAXB = SYSTEMZ_INS_WFMAXB, + SYSZ_INS_WFMAXDB = SYSTEMZ_INS_WFMAXDB, + SYSZ_INS_WFMAXSB = SYSTEMZ_INS_WFMAXSB, + SYSZ_INS_WFMAXXB = SYSTEMZ_INS_WFMAXXB, + SYSZ_INS_WFMDB = SYSTEMZ_INS_WFMDB, + SYSZ_INS_WFMINDB = SYSTEMZ_INS_WFMINDB, + SYSZ_INS_WFMINSB = SYSTEMZ_INS_WFMINSB, + SYSZ_INS_WFMINXB = SYSTEMZ_INS_WFMINXB, + SYSZ_INS_WFMSB = SYSTEMZ_INS_WFMSB, + SYSZ_INS_WFMSDB = SYSTEMZ_INS_WFMSDB, + SYSZ_INS_WFMSSB = SYSTEMZ_INS_WFMSSB, + SYSZ_INS_WFMSXB = SYSTEMZ_INS_WFMSXB, + SYSZ_INS_WFMXB = SYSTEMZ_INS_WFMXB, + SYSZ_INS_WFNMADB = SYSTEMZ_INS_WFNMADB, + SYSZ_INS_WFNMASB = SYSTEMZ_INS_WFNMASB, + SYSZ_INS_WFNMAXB = SYSTEMZ_INS_WFNMAXB, + SYSZ_INS_WFNMSDB = SYSTEMZ_INS_WFNMSDB, + SYSZ_INS_WFNMSSB = SYSTEMZ_INS_WFNMSSB, + SYSZ_INS_WFNMSXB = SYSTEMZ_INS_WFNMSXB, + SYSZ_INS_WFPSODB = SYSTEMZ_INS_WFPSODB, + SYSZ_INS_WFPSOSB = SYSTEMZ_INS_WFPSOSB, + SYSZ_INS_WFPSOXB = SYSTEMZ_INS_WFPSOXB, + SYSZ_INS_WFSDB = SYSTEMZ_INS_WFSDB, + SYSZ_INS_WFSQDB = SYSTEMZ_INS_WFSQDB, + SYSZ_INS_WFSQSB = SYSTEMZ_INS_WFSQSB, + SYSZ_INS_WFSQXB = SYSTEMZ_INS_WFSQXB, + SYSZ_INS_WFSSB = SYSTEMZ_INS_WFSSB, + SYSZ_INS_WFSXB = SYSTEMZ_INS_WFSXB, + SYSZ_INS_WFTCIDB = SYSTEMZ_INS_WFTCIDB, + SYSZ_INS_WFTCISB = SYSTEMZ_INS_WFTCISB, + SYSZ_INS_WFTCIXB = SYSTEMZ_INS_WFTCIXB, + SYSZ_INS_WLDEB = SYSTEMZ_INS_WLDEB, + SYSZ_INS_WLEDB = SYSTEMZ_INS_WLEDB, + SYSZ_INS_X = SYSTEMZ_INS_X, + SYSZ_INS_XC = SYSTEMZ_INS_XC, + SYSZ_INS_XG = SYSTEMZ_INS_XG, + SYSZ_INS_XGR = SYSTEMZ_INS_XGR, + SYSZ_INS_XGRK = SYSTEMZ_INS_XGRK, + SYSZ_INS_XI = SYSTEMZ_INS_XI, + SYSZ_INS_XIHF = SYSTEMZ_INS_XIHF, + SYSZ_INS_XILF = SYSTEMZ_INS_XILF, + SYSZ_INS_XIY = SYSTEMZ_INS_XIY, + SYSZ_INS_XR = SYSTEMZ_INS_XR, + SYSZ_INS_XRK = SYSTEMZ_INS_XRK, + SYSZ_INS_XSCH = SYSTEMZ_INS_XSCH, + SYSZ_INS_XY = SYSTEMZ_INS_XY, + SYSZ_INS_ZAP = SYSTEMZ_INS_ZAP, + + + SYSZ_INS_ENDING = SYSTEMZ_INS_ENDING, + + SYSZ_INS_ALIAS_BEGIN = SYSTEMZ_INS_ALIAS_BEGIN, + + SYSZ_INS_ALIAS_VISTRB = SYSTEMZ_INS_ALIAS_VISTRB, + SYSZ_INS_ALIAS_VISTR = SYSTEMZ_INS_ALIAS_VISTR, + SYSZ_INS_ALIAS_VFEEB = SYSTEMZ_INS_ALIAS_VFEEB, + SYSZ_INS_ALIAS_VFEE = SYSTEMZ_INS_ALIAS_VFEE, + SYSZ_INS_ALIAS_VFAEB = SYSTEMZ_INS_ALIAS_VFAEB, + SYSZ_INS_ALIAS_VFAEBS = SYSTEMZ_INS_ALIAS_VFAEBS, + SYSZ_INS_ALIAS_VFAE = SYSTEMZ_INS_ALIAS_VFAE, + SYSZ_INS_ALIAS_VSTRSB = SYSTEMZ_INS_ALIAS_VSTRSB, + SYSZ_INS_ALIAS_VSTRS = SYSTEMZ_INS_ALIAS_VSTRS, + SYSZ_INS_ALIAS_VSTRCB = SYSTEMZ_INS_ALIAS_VSTRCB, + SYSZ_INS_ALIAS_VSTRCBS = SYSTEMZ_INS_ALIAS_VSTRCBS, + SYSZ_INS_ALIAS_VSTRC = SYSTEMZ_INS_ALIAS_VSTRC, + SYSZ_INS_ALIAS_VFAEH = SYSTEMZ_INS_ALIAS_VFAEH, + SYSZ_INS_ALIAS_VFAEHS = SYSTEMZ_INS_ALIAS_VFAEHS, + SYSZ_INS_ALIAS_VFAEF = SYSTEMZ_INS_ALIAS_VFAEF, + SYSZ_INS_ALIAS_VFAEFS = SYSTEMZ_INS_ALIAS_VFAEFS, + SYSZ_INS_ALIAS_VFAEZB = SYSTEMZ_INS_ALIAS_VFAEZB, + SYSZ_INS_ALIAS_VFAEZBS = SYSTEMZ_INS_ALIAS_VFAEZBS, + SYSZ_INS_ALIAS_VFAEZH = SYSTEMZ_INS_ALIAS_VFAEZH, + SYSZ_INS_ALIAS_VFAEZHS = SYSTEMZ_INS_ALIAS_VFAEZHS, + SYSZ_INS_ALIAS_VFAEZF = SYSTEMZ_INS_ALIAS_VFAEZF, + SYSZ_INS_ALIAS_VFAEZFS = SYSTEMZ_INS_ALIAS_VFAEZFS, + SYSZ_INS_ALIAS_VFEEH = SYSTEMZ_INS_ALIAS_VFEEH, + SYSZ_INS_ALIAS_VFEEF = SYSTEMZ_INS_ALIAS_VFEEF, + SYSZ_INS_ALIAS_VFENE = SYSTEMZ_INS_ALIAS_VFENE, + SYSZ_INS_ALIAS_VFENEB = SYSTEMZ_INS_ALIAS_VFENEB, + SYSZ_INS_ALIAS_VFENEH = SYSTEMZ_INS_ALIAS_VFENEH, + SYSZ_INS_ALIAS_VFENEF = SYSTEMZ_INS_ALIAS_VFENEF, + SYSZ_INS_ALIAS_VISTRH = SYSTEMZ_INS_ALIAS_VISTRH, + SYSZ_INS_ALIAS_VISTRF = SYSTEMZ_INS_ALIAS_VISTRF, + SYSZ_INS_ALIAS_VSTRCH = SYSTEMZ_INS_ALIAS_VSTRCH, + SYSZ_INS_ALIAS_VSTRCHS = SYSTEMZ_INS_ALIAS_VSTRCHS, + SYSZ_INS_ALIAS_VSTRCF = SYSTEMZ_INS_ALIAS_VSTRCF, + SYSZ_INS_ALIAS_VSTRCFS = SYSTEMZ_INS_ALIAS_VSTRCFS, + SYSZ_INS_ALIAS_VSTRCZB = SYSTEMZ_INS_ALIAS_VSTRCZB, + SYSZ_INS_ALIAS_VSTRCZBS = SYSTEMZ_INS_ALIAS_VSTRCZBS, + SYSZ_INS_ALIAS_VSTRCZH = SYSTEMZ_INS_ALIAS_VSTRCZH, + SYSZ_INS_ALIAS_VSTRCZHS = SYSTEMZ_INS_ALIAS_VSTRCZHS, + SYSZ_INS_ALIAS_VSTRCZF = SYSTEMZ_INS_ALIAS_VSTRCZF, + SYSZ_INS_ALIAS_VSTRCZFS = SYSTEMZ_INS_ALIAS_VSTRCZFS, + SYSZ_INS_ALIAS_VSTRSH = SYSTEMZ_INS_ALIAS_VSTRSH, + SYSZ_INS_ALIAS_VSTRSF = SYSTEMZ_INS_ALIAS_VSTRSF, + + + + SYSZ_INS_ALIAS_END = SYSTEMZ_INS_ALIAS_END, +} sysz_insn; + +typedef enum { + SYSZ_GRP_INVALID = SYSTEMZ_GRP_INVALID, + + SYSZ_GRP_JUMP = SYSTEMZ_GRP_JUMP, + SYSZ_GRP_CALL = SYSTEMZ_GRP_CALL, + SYSZ_GRP_RET = SYSTEMZ_GRP_RET, + SYSZ_GRP_INT = SYSTEMZ_GRP_INT, + SYSZ_GRP_IRET = SYSTEMZ_GRP_IRET, + SYSZ_GRP_PRIVILEGE = SYSTEMZ_GRP_PRIVILEGE, + SYSZ_GRP_BRANCH_RELATIVE = SYSTEMZ_GRP_BRANCH_RELATIVE, + + SYSZ_FEATURE_FEATURESOFTFLOAT = SYSTEMZ_FEATURE_FEATURESOFTFLOAT, + SYSZ_FEATURE_FEATUREBACKCHAIN = SYSTEMZ_FEATURE_FEATUREBACKCHAIN, + SYSZ_FEATURE_FEATUREDISTINCTOPS = SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, + SYSZ_FEATURE_FEATUREFASTSERIALIZATION = SYSTEMZ_FEATURE_FEATUREFASTSERIALIZATION, + SYSZ_FEATURE_FEATUREFPEXTENSION = SYSTEMZ_FEATURE_FEATUREFPEXTENSION, + SYSZ_FEATURE_FEATUREHIGHWORD = SYSTEMZ_FEATURE_FEATUREHIGHWORD, + SYSZ_FEATURE_FEATUREINTERLOCKEDACCESS1 = SYSTEMZ_FEATURE_FEATUREINTERLOCKEDACCESS1, + SYSZ_FEATURE_FEATURELOADSTOREONCOND = SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND, + SYSZ_FEATURE_FEATUREPOPULATIONCOUNT = SYSTEMZ_FEATURE_FEATUREPOPULATIONCOUNT, + SYSZ_FEATURE_FEATUREMESSAGESECURITYASSIST3 = SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST3, + SYSZ_FEATURE_FEATUREMESSAGESECURITYASSIST4 = SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST4, + SYSZ_FEATURE_FEATURERESETREFERENCEBITSMULTIPLE = SYSTEMZ_FEATURE_FEATURERESETREFERENCEBITSMULTIPLE, + SYSZ_FEATURE_FEATUREEXECUTIONHINT = SYSTEMZ_FEATURE_FEATUREEXECUTIONHINT, + SYSZ_FEATURE_FEATURELOADANDTRAP = SYSTEMZ_FEATURE_FEATURELOADANDTRAP, + SYSZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS = SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS, + SYSZ_FEATURE_FEATUREPROCESSORASSIST = SYSTEMZ_FEATURE_FEATUREPROCESSORASSIST, + SYSZ_FEATURE_FEATURETRANSACTIONALEXECUTION = SYSTEMZ_FEATURE_FEATURETRANSACTIONALEXECUTION, + SYSZ_FEATURE_FEATUREDFPZONEDCONVERSION = SYSTEMZ_FEATURE_FEATUREDFPZONEDCONVERSION, + SYSZ_FEATURE_FEATUREENHANCEDDAT2 = SYSTEMZ_FEATURE_FEATUREENHANCEDDAT2, + SYSZ_FEATURE_FEATURELOADANDZERORIGHTMOSTBYTE = SYSTEMZ_FEATURE_FEATURELOADANDZERORIGHTMOSTBYTE, + SYSZ_FEATURE_FEATURELOADSTOREONCOND2 = SYSTEMZ_FEATURE_FEATURELOADSTOREONCOND2, + SYSZ_FEATURE_FEATUREMESSAGESECURITYASSIST5 = SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST5, + SYSZ_FEATURE_FEATUREDFPPACKEDCONVERSION = SYSTEMZ_FEATURE_FEATUREDFPPACKEDCONVERSION, + SYSZ_FEATURE_FEATUREVECTOR = SYSTEMZ_FEATURE_FEATUREVECTOR, + SYSZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2 = SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS2, + SYSZ_FEATURE_FEATUREGUARDEDSTORAGE = SYSTEMZ_FEATURE_FEATUREGUARDEDSTORAGE, + SYSZ_FEATURE_FEATUREMESSAGESECURITYASSIST7 = SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST7, + SYSZ_FEATURE_FEATUREMESSAGESECURITYASSIST8 = SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST8, + SYSZ_FEATURE_FEATUREVECTORENHANCEMENTS1 = SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS1, + SYSZ_FEATURE_FEATUREVECTORPACKEDDECIMAL = SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMAL, + SYSZ_FEATURE_FEATUREINSERTREFERENCEBITSMULTIPLE = SYSTEMZ_FEATURE_FEATUREINSERTREFERENCEBITSMULTIPLE, + SYSZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3 = SYSTEMZ_FEATURE_FEATUREMISCELLANEOUSEXTENSIONS3, + SYSZ_FEATURE_FEATUREMESSAGESECURITYASSIST9 = SYSTEMZ_FEATURE_FEATUREMESSAGESECURITYASSIST9, + SYSZ_FEATURE_FEATUREVECTORENHANCEMENTS2 = SYSTEMZ_FEATURE_FEATUREVECTORENHANCEMENTS2, + SYSZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT = SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT, + SYSZ_FEATURE_FEATUREENHANCEDSORT = SYSTEMZ_FEATURE_FEATUREENHANCEDSORT, + SYSZ_FEATURE_FEATUREDEFLATECONVERSION = SYSTEMZ_FEATURE_FEATUREDEFLATECONVERSION, + SYSZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT2 = SYSTEMZ_FEATURE_FEATUREVECTORPACKEDDECIMALENHANCEMENT2, + SYSZ_FEATURE_FEATURENNPASSIST = SYSTEMZ_FEATURE_FEATURENNPASSIST, + SYSZ_FEATURE_FEATUREBEARENHANCEMENT = SYSTEMZ_FEATURE_FEATUREBEARENHANCEMENT, + SYSZ_FEATURE_FEATURERESETDATPROTECTION = SYSTEMZ_FEATURE_FEATURERESETDATPROTECTION, + SYSZ_FEATURE_FEATUREPROCESSORACTIVITYINSTRUMENTATION = SYSTEMZ_FEATURE_FEATUREPROCESSORACTIVITYINSTRUMENTATION, + + + SYSZ_GRP_ENDING = SYSTEMZ_GRP_ENDING, +} sysz_insn_group; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/suite/auto-sync/.gitignore b/suite/auto-sync/.gitignore index 95a3a6a432..7bc61ff5ea 100644 --- a/suite/auto-sync/.gitignore +++ b/suite/auto-sync/.gitignore @@ -9,4 +9,4 @@ src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/Output src/autosync/lit_config/test_dir_* src/autosync/lit_config/.lit_test_times.txt src/autosync/Tests/MCUpdaterTests/test_output -src/autosync/Tests/MCUpdaterTests/ARCH/Output +src/autosync/Tests/MCUpdaterTests/**/Output diff --git a/suite/auto-sync/c_tests/CMakeLists.txt b/suite/auto-sync/c_tests/CMakeLists.txt deleted file mode 100644 index ae54d3101a..0000000000 --- a/suite/auto-sync/c_tests/CMakeLists.txt +++ /dev/null @@ -1,16 +0,0 @@ -cmake_minimum_required(VERSION 3.15) - -set(AUTO_SYNC_C_TEST_SRC_DIR ${AUTO_SYNC_C_TEST_DIR}/src) -set(AUTO_SYNC_C_TEST_INC_DIR ${AUTO_SYNC_C_TEST_DIR}/include) - -include_directories(${AUTO_SYNC_C_TEST_INC_DIR} ${PROJECT_SOURCE_DIR}/include) - -file(GLOB AUTO_SYNC_C_SRC ${AUTO_SYNC_C_TEST_SRC_DIR}/*.c) -add_executable(compat_header_build_test ${AUTO_SYNC_C_SRC}) -add_dependencies(compat_header_build_test capstone) -target_link_libraries(compat_header_build_test PUBLIC capstone) - -add_test(NAME ASCompatibilityHeaderTest - COMMAND compat_header_build_test - WORKING_DIRECTORY ${AUTO_SYNC_C_TEST_DIR} -) diff --git a/suite/auto-sync/pyproject.toml b/suite/auto-sync/pyproject.toml index cf560c27a4..ab605d6ccb 100644 --- a/suite/auto-sync/pyproject.toml +++ b/suite/auto-sync/pyproject.toml @@ -22,3 +22,6 @@ requires-python = ">= 3.11" [tool.setuptools] packages = ["autosync", "autosync.cpptranslator", "autosync.cpptranslator.patches"] package-dir = {"" = "src"} + +[project.scripts] +ASUpdater = "autosync.ASUpdater:main" diff --git a/suite/auto-sync/src/autosync/ASUpdater.py b/suite/auto-sync/src/autosync/ASUpdater.py index 15ec433871..aea83a90e8 100755 --- a/suite/auto-sync/src/autosync/ASUpdater.py +++ b/suite/auto-sync/src/autosync/ASUpdater.py @@ -10,17 +10,19 @@ import shutil import subprocess import sys +import json from enum import StrEnum from pathlib import Path from autosync.cpptranslator.Configurator import Configurator from autosync.cpptranslator.CppTranslator import Translator from autosync.HeaderPatcher import CompatHeaderBuilder, HeaderPatcher -from autosync.Helper import check_py_version, convert_loglevel, fail_exit, get_path +from autosync.Helper import convert_loglevel, fail_exit, get_path from autosync.IncGenerator import IncGenerator from autosync.MCUpdater import MCUpdater +from autosync.Targets import ARCH_LLVM_NAMING class USteps(StrEnum): @@ -44,7 +46,7 @@ def __init__( steps: list[USteps], inc_list: list, no_clean: bool, - refactor: bool, + copy_translated: bool, differ_no_auto_apply: bool, wait_for_user: bool = True, ) -> None: @@ -63,7 +65,7 @@ def __init__( ] else: self.steps = steps - self.refactor = refactor + self.copy_translated = copy_translated self.differ_no_auto_apply = differ_no_auto_apply self.arch_dir = get_path("{CS_ARCH_MODULE_DIR}").joinpath(self.arch) if not self.no_clean_build: @@ -72,12 +74,16 @@ def __init__( self.arch, self.inc_list, ) + with open(get_path("{MCUPDATER_CONFIG_FILE}")) as f: + self.mcupdater_conf = json.loads(f.read()) + self.mc_updater = MCUpdater( self.arch, get_path("{LLVM_MC_TEST_DIR}"), None, None, - True if self.arch == "ARM" else False, + self.arch in self.mcupdater_conf["unify_test_cases"], + multi_mode=True, ) def clean_build_dir(self) -> None: @@ -108,10 +114,10 @@ def patch_main_header(self) -> list: if self.arch == "AArch64": # Update the compatibility header builder = CompatHeaderBuilder( - aarch64_h=main_header, - arm64_h=get_path("{CS_INCLUDE_DIR}").joinpath(f"arm64.h"), + v6=main_header, + v5=get_path("{CS_INCLUDE_DIR}").joinpath(f"arm64.h"), ) - builder.generate_aarch64_compat_header() + builder.generate_v5_compat_header() return patched def copy_files(self, path: Path, dest: Path) -> None: @@ -173,36 +179,44 @@ def update(self) -> None: self.diff() if USteps.MC in self.steps: self.mc_updater.gen_all() - if self.write: - # Copy .inc files - log.info(f"Copy .inc files to {self.arch_dir}") - i = 0 - arch_header = get_path("{CS_INCLUDE_DIR}").joinpath( - f"{self.arch.lower()}.h" - ) - for file in get_path("{C_INC_OUT_DIR}").iterdir(): - if HeaderPatcher.file_in_main_header(arch_header, file.name): - continue + if not self.write: + # Done + exit(0) + + # Copy .inc files + log.info(f"Copy .inc files to {self.arch_dir}") + i = 0 + arch_header = get_path("{CS_INCLUDE_DIR}").joinpath(f"{self.arch.lower()}.h") + for file in get_path("{C_INC_OUT_DIR}").iterdir(): + if HeaderPatcher.file_in_main_header(arch_header, file.name): + continue + self.copy_files(file, self.arch_dir) + i += 1 + log.info(f"Copied {i} files") + + i = 0 + if self.copy_translated: + # Diffed files + log.info(f"Copy translated files to {self.arch_dir}") + for file in get_path("{CPP_TRANSLATOR_TRANSLATION_OUT_DIR}").iterdir(): self.copy_files(file, self.arch_dir) i += 1 - log.info(f"Copied {i} files") - - i = 0 + else: # Diffed files log.info(f"Copy diffed files to {self.arch_dir}") for file in get_path("{CPP_TRANSLATOR_DIFF_OUT_DIR}").iterdir(): self.copy_files(file, self.arch_dir) i += 1 - log.info(f"Copied {i} files") - - # MC tests - i = 0 - mc_dir = get_path("{MC_DIR}").joinpath(self.arch) - log.info(f"Copy MC test files to {mc_dir}") - for file in get_path("{MCUPDATER_OUT_DIR}").iterdir(): - self.copy_files(file, mc_dir) - i += 1 - log.info(f"Copied {i} files") + log.info(f"Copied {i} files") + + # MC tests + i = 0 + mc_dir = get_path("{MC_DIR}").joinpath(self.arch) + log.info(f"Copy MC test files to {mc_dir}") + for file in get_path("{MCUPDATER_OUT_DIR}").iterdir(): + self.copy_files(file, mc_dir) + i += 1 + log.info(f"Copied {i} files") exit(0) @@ -216,7 +230,7 @@ def parse_args() -> argparse.Namespace: "-a", dest="arch", help="Name of target architecture.", - choices=["ARM", "PPC", "AArch64", "Alpha", "LoongArch", "Mips"], + choices=ARCH_LLVM_NAMING, required=True, ) parser.add_argument( @@ -278,9 +292,9 @@ def parse_args() -> argparse.Namespace: default=["All"], ) parser.add_argument( - "--refactor", - dest="refactor", - help="Sets change update behavior to ease refactoring and new implementations.", + "--copy-translated", + dest="copy_translated", + help="Copy the translated files and not the files produced by the Differ.", action="store_true", ) parser.add_argument( @@ -293,9 +307,7 @@ def parse_args() -> argparse.Namespace: return arguments -if __name__ == "__main__": - check_py_version() - +def main(): args = parse_args() log.basicConfig( level=convert_loglevel(args.verbosity), @@ -310,8 +322,12 @@ def parse_args() -> argparse.Namespace: args.steps, args.inc_list, args.no_clean, - args.refactor, + args.copy_translated, args.no_auto_apply, args.wait_for_user, ) Updater.update() + + +if __name__ == "__main__": + main() diff --git a/suite/auto-sync/src/autosync/HeaderPatcher.py b/suite/auto-sync/src/autosync/HeaderPatcher.py index 7f51eb1a26..6368605be6 100755 --- a/suite/auto-sync/src/autosync/HeaderPatcher.py +++ b/suite/auto-sync/src/autosync/HeaderPatcher.py @@ -18,10 +18,10 @@ def parse_args() -> argparse.Namespace: parser.add_argument("--header", dest="header", help="Path header file.", type=Path) parser.add_argument("--inc", dest="inc", help="Path inc file.", type=Path) parser.add_argument( - "--aarch64", dest="aarch64", help="aarch64.h header file location", type=Path + "--v6", dest="v6", help="aarch64.h/systemz.h header file location", type=Path ) parser.add_argument( - "--arm64", dest="arm64", help="arm64.h header file location", type=Path + "--v5", dest="v5", help="arm64.h/systemz_v5.h header file location", type=Path ) parser.add_argument( "-c", dest="compat", help="Generate compatibility header", action="store_true" @@ -120,78 +120,98 @@ def file_in_main_header(header: Path, filename: str) -> bool: class CompatHeaderBuilder: - - def __init__(self, aarch64_h: Path, arm64_h: Path): - self.aarch64_h = aarch64_h - self.arm64_h = arm64_h - - def replace_typedef_struct(self, aarch64_lines: list[str]) -> list[str]: + def __init__(self, v6: Path, v5: Path, arch: str): + self.v6 = v6 + self.v5 = v5 + match arch: + case "aarch64": + self.v6_lower = "aarch64" + self.v6_upper = "AARCH64" + self.v6_camel = "AArch64" + self.v5_lower = "arm64" + self.v5_upper = "ARM64" + case "systemz": + self.v6_lower = "systemz" + self.v6_upper = "SYSTEMZ" + self.v6_camel = "SystemZ" + self.v5_lower = "sysz" + self.v5_upper = "SYSZ" + case _: + raise ValueError(f"{arch} not handled") + + def replace_typedef_struct(self, v6_lines: list[str]) -> list[str]: output = list() typedef = "" - for line in aarch64_lines: + for line in v6_lines: if typedef: if not re.search(r"^}\s[\w_]+;", line): # Skip struct content continue type_name = re.findall(r"[\w_]+", line)[0] output.append( - f"typedef {type_name} {re.sub('aarch64','arm64', type_name)};\n" + f"typedef {type_name} {re.sub(self.v6_lower,self.v5_lower, type_name)};\n" ) typedef = "" continue - if re.search(f"^typedef\s+(struct|union)", line): + if re.search(rf"^typedef\s+(struct|union)", line): typedef = line continue output.append(line) return output - def replace_typedef_enum(self, aarch64_lines: list[str]) -> list[str]: + def replace_typedef_enum(self, v6_lines: list[str]) -> list[str]: output = list() typedef = "" - for line in aarch64_lines: + for line in v6_lines: if typedef: if not re.search(r"^}\s[\w_]+;", line): # Replace name - if "AArch64" not in line and "AARCH64" not in line: + if self.v6_camel not in line and self.v6_upper not in line: output.append(line) continue - found = re.findall(r"(AArch64|AARCH64)([\w_]+)", line) + found = re.findall( + rf"({self.v6_camel}|{self.v6_upper})([\w_]+)", line + ) entry_name: str = "".join(found[0]) - arm64_name = entry_name.replace("AArch64", "ARM64").replace( - "AARCH64", "ARM64" + v5_name = entry_name.replace(self.v6_camel, self.v6_camel).replace( + self.v6_upper, self.v5_upper ) patched_line = re.sub( - r"(AArch64|AARCH64).+", f"{arm64_name} = {entry_name},", line + rf"({self.v6_camel}|{self.v6_upper}).+", + f"{v5_name} = {entry_name},", + line, ) output.append(patched_line) continue # We still have LLVM and CS naming conventions mixed - p = re.sub(r"aarch64", "arm64", line) - p = re.sub(r"(AArch64|AARCH64)", "ARM64", p) + p = re.sub(self.v6_lower, self.v5_lower, line) + p = re.sub(rf"({self.v6_camel}|{self.v6_upper})", self.v5_upper, p) output.append(p) typedef = "" continue - if re.search(f"^typedef\s+enum", line): + if re.search(rf"^typedef\s+enum", line): typedef = line output.append("typedef enum {\n") continue output.append(line) return output - def remove_comments(self, aarch64_lines: list[str]) -> list[str]: + def remove_comments(self, v6_lines: list[str]) -> list[str]: output = list() - for line in aarch64_lines: + for line in v6_lines: if re.search(r"^\s*//", line) and "// SPDX" not in line: continue output.append(line) return output - def replace_aarch64(self, aarch64_lines: list[str]) -> list[str]: + def replace_v6_prefix(self, v6_lines: list[str]) -> list[str]: output = list() in_typedef = False - for line in aarch64_lines: + for line in v6_lines: + if "CAPSTONE_SYSTEMZ_COMPAT_HEADER" in line: + output.append(line) if in_typedef: if re.search(r"^}\s[\w_]+;", line): in_typedef = False @@ -202,46 +222,61 @@ def replace_aarch64(self, aarch64_lines: list[str]) -> list[str]: in_typedef = True output.append(line) continue - output.append(re.sub(r"(AArch64|AARCH64)", "ARM64", line)) + output.append( + re.sub(rf"({self.v6_camel}|{self.v6_upper})", self.v5_upper, line) + ) return output - def replace_include_guards(self, aarch64_lines: list[str]) -> list[str]: + def replace_include_guards(self, v6_lines: list[str]) -> list[str]: output = list() - for line in aarch64_lines: + skip = False + for line in v6_lines: + if "CAPSTONE_SYSTEMZ_COMPAT_HEADER" in line: + # The compat heade is inlcuded in the v6 header. + # Because v5 and v6 header share the same name. + skip = True + continue + elif skip and "#endif" in line: + skip = False + continue + elif skip: + continue + if not re.search(r"^#(ifndef|define)", line): output.append(line) continue - output.append(re.sub(r"AARCH64", "ARM64", line)) + output.append(re.sub(self.v6_upper, self.v5_upper, line)) return output - def inject_aarch64_header(self, aarch64_lines: list[str]) -> list[str]: + def inject_v6_header(self, v6_lines: list[str]) -> list[str]: output = list() header_inserted = False - for line in aarch64_lines: + for line in v6_lines: if re.search(r"^#include", line): if not header_inserted: - output.append("#include \n") + output.append(f"#include \n") header_inserted = True output.append(line) return output - def generate_aarch64_compat_header(self) -> bool: + def generate_v5_compat_header(self) -> bool: """ Translates the aarch64.h header into the arm64.h header and renames all aarch64 occurrences. It does simple regex matching and replacing. + Same for systemz.h and SYSTEMZ -> SYSZ. But the output file is systemz_compatibility.h. """ log.info("Generate compatibility header") - with open(self.aarch64_h) as f: - aarch64 = f.readlines() + with open(self.v6) as f: + v6_lines = f.readlines() - patched = self.replace_typedef_struct(aarch64) + patched = self.replace_typedef_struct(v6_lines) patched = self.replace_typedef_enum(patched) patched = self.remove_comments(patched) - patched = self.replace_aarch64(patched) + patched = self.replace_v6_prefix(patched) patched = self.replace_include_guards(patched) - patched = self.inject_aarch64_header(patched) + patched = self.inject_v6_header(patched) - with open(self.arm64_h, "w+") as f: + with open(self.v5, "w+") as f: f.writelines(patched) @@ -250,10 +285,8 @@ def generate_aarch64_compat_header(self) -> bool: if (not args.patch and not args.compat) or (args.patch and args.compat): print("You need to specify either -c or -p") exit(1) - if args.compat and not (args.aarch64 and args.arm64): - print( - "Generating the arm64 compatibility header requires --arm64 and --aarch64" - ) + if args.compat and not (args.v6 and args.v5): + print("Generating the v5 compatibility header requires --v5 and --v6") exit(1) if args.patch and not (args.inc and args.header): print("Patching headers requires --inc and --header") @@ -264,5 +297,12 @@ def generate_aarch64_compat_header(self) -> bool: patcher.patch_header() exit(0) - builder = CompatHeaderBuilder(args.aarch64, args.arm64) - builder.generate_aarch64_compat_header() + if "aarch64" in args.v6.name: + arch = "aarch64" + elif "systemz" in args.v6.name: + arch = "systemz" + else: + raise ValueError(f"Does not know the arch for header file: {args.v6.name}") + + builder = CompatHeaderBuilder(args.v6, args.v5, arch) + builder.generate_v5_compat_header() diff --git a/suite/auto-sync/src/autosync/Helper.py b/suite/auto-sync/src/autosync/Helper.py index b91c1cbb82..d39eeb0894 100644 --- a/suite/auto-sync/src/autosync/Helper.py +++ b/suite/auto-sync/src/autosync/Helper.py @@ -168,9 +168,3 @@ def fail_exit(msg: str) -> None: """Logs a fatal message and exits with error code 1.""" log.fatal(msg) exit(1) - - -def check_py_version() -> None: - if not sys.hexversion >= 0x030B00F0: - log.fatal("Python >= v3.11 required.") - exit(1) diff --git a/suite/auto-sync/src/autosync/IncGenerator.py b/suite/auto-sync/src/autosync/IncGenerator.py index e29c22e2d7..a4334838e8 100644 --- a/suite/auto-sync/src/autosync/IncGenerator.py +++ b/suite/auto-sync/src/autosync/IncGenerator.py @@ -4,6 +4,7 @@ # SPDX-License-Identifier: BSD-3 import logging as log +import json import os import re import shutil @@ -12,58 +13,6 @@ from autosync.Helper import fail_exit, get_path -inc_tables = [ - { - "name": "Disassembler", - "tblgen_arg": "--gen-disassembler", - "inc_name": "DisassemblerTables", - "only_arch": [], - "lang": ["CCS", "C++"], - }, - { - "name": "AsmWriter", - "tblgen_arg": "--gen-asm-writer", - "inc_name": "AsmWriter", - "only_arch": [], - "lang": ["CCS", "C++"], - }, - { - "name": "RegisterInfo", - "tblgen_arg": "--gen-register-info", - "inc_name": "RegisterInfo", - "only_arch": [], - "lang": ["CCS"], - }, - { - "name": "InstrInfo", - "tblgen_arg": "--gen-instr-info", - "inc_name": "InstrInfo", - "only_arch": [], - "lang": ["CCS"], - }, - { - "name": "SubtargetInfo", - "tblgen_arg": "--gen-subtarget", - "inc_name": "SubtargetInfo", - "only_arch": [], - "lang": ["CCS"], - }, - { - "name": "Mapping", - "tblgen_arg": "--gen-asm-matcher", - "inc_name": None, - "only_arch": [], - "lang": ["CCS"], - }, - { - "name": "SystemOperand", - "tblgen_arg": "--gen-searchable-tables", - "inc_name": None, - "only_arch": ["AArch64", "ARM"], - "lang": ["CCS"], - }, -] - class IncGenerator: def __init__(self, arch: str, inc_list: list) -> None: @@ -79,6 +28,8 @@ def __init__(self, arch: str, inc_list: list) -> None: self.llvm_tblgen: Path = get_path("{LLVM_TBLGEN_BIN}") self.output_dir_c_inc = get_path("{C_INC_OUT_DIR}") self.output_dir_cpp_inc = get_path("{CPP_INC_OUT_DIR}") + with open(get_path("{INC_GEN_CONF_FILE}")) as f: + self.conf = json.loads(f.read()) self.check_paths() def check_paths(self) -> None: @@ -133,7 +84,7 @@ def move_mapping_files(self) -> None: shutil.move(sys_ops_table_file, new_sys_ops_file) def gen_incs(self) -> None: - for table in inc_tables: + for table in self.conf["inc_tables"]: if "All" not in self.inc_list and table["name"] not in self.inc_list: log.debug(f"Skip {table['name']} generation") continue diff --git a/suite/auto-sync/src/autosync/MCUpdater.py b/suite/auto-sync/src/autosync/MCUpdater.py index c8ee9f4e3b..9d6b5adeb0 100755 --- a/suite/auto-sync/src/autosync/MCUpdater.py +++ b/suite/auto-sync/src/autosync/MCUpdater.py @@ -20,13 +20,15 @@ def __init__(self, cmd_line: str, mattr: str): self.cmd: str = "" self.opts: str = "" self.file: Path | None = None - self.mattr: str = mattr + self.additional_mattr: str = mattr self.cmd, self.opts, self.file = self.parse_llvm_mc_line(cmd_line) if not (self.cmd and self.opts and self.file): log.warning(f"Could not parse llvm-mc command: {cmd_line}") elif not "--show-encoding" in self.cmd: self.cmd = re.sub("llvm-mc", "llvm-mc --show-encoding", self.cmd) + elif not "--disassemble" in self.cmd: + self.cmd = re.sub("llvm-mc", "llvm-mc --disassemble", self.cmd) def parse_llvm_mc_line(self, line: str) -> tuple[str, str, Path]: test_file_base_dir = str(get_path("{LLVM_LIT_TEST_DIR}").absolute()) @@ -42,20 +44,26 @@ def parse_llvm_mc_line(self, line: str) -> tuple[str, str, Path]: opts = ",".join([m.group(2) for m in arch]) if arch else "" if mattr: opts += "" if not opts else "," - opts += ",".join([m.group(2).strip("+") for m in mattr]) + processed_attr = list() + for m in mattr: + attribute = m.group(2).strip("+") + processed_attr.append(attribute) + opts += ",".join(processed_attr) return cmd, opts, Path(test_file) def exec(self) -> sp.CompletedProcess: with open(self.file, "b+r") as f: content = f.read() - if self.mattr: + if self.additional_mattr: # If mattr exists, patch it into the cmd if "mattr" in self.cmd: self.cmd = re.sub( - r"mattr[=\s]+", f"mattr={self.mattr} -mattr=", self.cmd + r"mattr[=\s]+", f"mattr={self.additional_mattr} -mattr=", self.cmd ) else: - self.cmd = re.sub(r"llvm-mc", f"llvm-mc -mattr={self.mattr}", self.cmd) + self.cmd = re.sub( + r"llvm-mc", f"llvm-mc -mattr={self.additional_mattr}", self.cmd + ) log.debug(f"Run: {self.cmd}") result = sp.run(self.cmd.split(" "), input=content, capture_output=True) @@ -78,11 +86,7 @@ class MCTest: def __init__(self, arch: str, opts: list[str], encoding: str, asm_text: str): self.arch = arch - if arch.lower() in ["arm", "powerpc", "ppc", "aarch64"]: - # Arch and PPC require this option for MC tests. - self.opts = ["CS_OPT_NO_BRANCH_OFFSET"] + opts - else: - self.opts = opts + self.opts = opts self.encoding: list[str] = [encoding] self.asm_text: list[str] = [asm_text] @@ -263,7 +267,7 @@ def __init__( else "" ) # A list of options which are always added. - self.mandatory_options: str = ( + self.mandatory_options: list[str] = ( self.conf["mandatory_options"][self.arch] if self.arch in self.conf["mandatory_options"] else list() @@ -274,13 +278,15 @@ def __init__( else list() ) self.remove_options = [x.lower() for x in self.remove_options] - self.replace_option_map: str = ( + self.replace_option_map: dict = ( self.conf["replace_option_map"][self.arch] if self.arch in self.conf["replace_option_map"] else {} ) self.replace_option_map = { - k.lower(): v for k, v in self.replace_option_map.items() + k.lower(): v + for k, v in self.replace_option_map.items() + if k.lower not in self.remove_options } self.multi_mode = multi_mode @@ -297,12 +303,14 @@ def check_prerequisites(self, paths): ) def write_to_build_dir(self): + no_tests_file = 0 file_cnt = 0 test_cnt = 0 overwritten = 0 files_written = set() for test in sorted(self.test_files): if not test.has_tests(): + no_tests_file += 1 continue file_cnt += 1 test_cnt += test.num_test_cases() @@ -332,7 +340,7 @@ def write_to_build_dir(self): f"The following file exists already: {filename}\n" "This is not allowed in multi-mode." ) - else: + elif not self.multi_mode and filename.exists(): log.debug(f"Overwrite: {filename}") overwritten += 1 with open(filename, write_mode) as f: @@ -340,7 +348,10 @@ def write_to_build_dir(self): log.debug(f"Write {filename}") files_written.add(filename) log.info( - f"Processed {file_cnt} files with {test_cnt} test cases. Generated {len(files_written)} files" + f"Got {len(self.test_files)} test files.\n" + f"\t\tProcessed {file_cnt} files with {test_cnt} test cases.\n" + f"\t\tIgnored {no_tests_file} without tests.\n" + f"\t\tGenerated {len(files_written)} files" ) if overwritten > 0: log.warning( @@ -544,4 +555,5 @@ def parse_args() -> argparse.Namespace: args.excluded_files, args.included_files, args.unified_tests, + True, ).gen_all() diff --git a/suite/auto-sync/src/autosync/Targets.py b/suite/auto-sync/src/autosync/Targets.py index d3dfdd1c5a..2b616d39f8 100644 --- a/suite/auto-sync/src/autosync/Targets.py +++ b/suite/auto-sync/src/autosync/Targets.py @@ -1,4 +1,27 @@ # Copyright © 2024 Rot127 # SPDX-License-Identifier: BSD-3 -TARGETS_LLVM_NAMING = ["ARM", "PowerPC", "Alpha", "AArch64", "LoongArch"] +# Names of the target architectures as they are listed under llvm/lib/Target/ +TARGETS_LLVM_NAMING = [ + "ARM", + "PowerPC", + "Alpha", + "AArch64", + "LoongArch", + "SystemZ", + "Mips", +] + +# Names of the target architecture as they are used in code and pretty much everywhere else. +ARCH_LLVM_NAMING = ["ARM", "PPC", "Alpha", "AArch64", "LoongArch", "SystemZ", "Mips"] + +# Maps the target full name to the name used in code (and pretty much everywhere else). +TARGET_TO_IN_CODE_NAME = { + "ARM": "ARM", + "PowerPC": "PPC", + "Alpha": "Alpha", + "AArch64": "AArch64", + "LoongArch": "LoongArch", + "SystemZ": "SystemZ", + "Mips": "Mips", +} diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/SystemZ/test_systemz_mapping.txt b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/SystemZ/test_systemz_mapping.txt new file mode 100644 index 0000000000..a824d895da --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/SystemZ/test_systemz_mapping.txt @@ -0,0 +1,16 @@ +# For z13 and above. +# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z13 -show-encoding %s \ +# RUN: | FileCheck %s +# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=arch11 -show-encoding %s \ +# RUN: | FileCheck %s + +#CHECK: cdpt %f0, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0xae] +#CHECK: cdpt %f15, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0xae] +#CHECK: cdpt %f0, 0(1), 15 # encoding: [0xed,0x00,0x00,0x00,0x0f,0xae] +#CHECK: cdpt %f0, 0(1,%r1), 0 # encoding: [0xed,0x00,0x10,0x00,0x00,0xae] + + + cdpt %f0, 0(1), 0 + cdpt %f15, 0(1), 0 + cdpt %f0, 0(1), 15 + cdpt %f0, 0(1,%r1), 0 diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/mode_mapping/test_systemz_mapping.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/mode_mapping/test_systemz_mapping.txt.yaml new file mode 100644 index 0000000000..7289cc256a --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/mode_mapping/test_systemz_mapping.txt.yaml @@ -0,0 +1,80 @@ +test_cases: + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "CS_MODE_BIG_ENDIAN", "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13" ] + expected: + insns: + - + asm_text: "cdpt %f0, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "CS_MODE_BIG_ENDIAN", "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13" ] + expected: + insns: + - + asm_text: "cdpt %f15, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x0f, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "CS_MODE_BIG_ENDIAN", "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13" ] + expected: + insns: + - + asm_text: "cdpt %f0, 0(1), 15" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "CS_MODE_BIG_ENDIAN", "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13" ] + expected: + insns: + - + asm_text: "cdpt %f0, 0(1,%r1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "CS_MODE_BIG_ENDIAN", "s390x-linux-gnu", "CS_MODE_SYSTEMZ_ARCH11" ] + expected: + insns: + - + asm_text: "cdpt %f0, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "CS_MODE_BIG_ENDIAN", "s390x-linux-gnu", "CS_MODE_SYSTEMZ_ARCH11" ] + expected: + insns: + - + asm_text: "cdpt %f15, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x0f, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "CS_MODE_BIG_ENDIAN", "s390x-linux-gnu", "CS_MODE_SYSTEMZ_ARCH11" ] + expected: + insns: + - + asm_text: "cdpt %f0, 0(1), 15" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "CS_MODE_BIG_ENDIAN", "s390x-linux-gnu", "CS_MODE_SYSTEMZ_ARCH11" ] + expected: + insns: + - + asm_text: "cdpt %f0, 0(1,%r1), 0" diff --git a/suite/auto-sync/src/autosync/Tests/test_header_patcher.py b/suite/auto-sync/src/autosync/Tests/test_header_patcher.py index 31a2f473f5..8c5d23a4e4 100644 --- a/suite/auto-sync/src/autosync/Tests/test_header_patcher.py +++ b/suite/auto-sync/src/autosync/Tests/test_header_patcher.py @@ -15,10 +15,6 @@ def setUpClass(cls): get_path("{HEADER_PATCHER_TEST_INC_FILE}"), write_file=False, ) - cls.compat_gen = CompatHeaderBuilder( - get_path("{HEADER_GEN_TEST_AARCH64_FILE}"), - get_path("{HEADER_GEN_TEST_ARM64_OUT_FILE}"), - ) def test_header_patching(self): self.hpatcher.patch_header() @@ -50,9 +46,26 @@ def test_header_patching(self): ), ) - def test_compat_header_gen(self): - self.compat_gen.generate_aarch64_compat_header() + def test_compat_header_gen_arm64(self): + self.compat_gen = CompatHeaderBuilder( + get_path("{HEADER_GEN_TEST_AARCH64_FILE}"), + get_path("{HEADER_GEN_TEST_ARM64_OUT_FILE}"), + "aarch64", + ) + self.compat_gen.generate_v5_compat_header() with open(get_path("{HEADER_GEN_TEST_ARM64_FILE}")) as f: correct = f.read() with open(get_path("{HEADER_GEN_TEST_ARM64_OUT_FILE}")) as f: self.assertEqual(f.read(), correct) + + def test_compat_header_gen_arm64(self): + self.compat_gen = CompatHeaderBuilder( + get_path("{HEADER_GEN_TEST_SYSTEMZ_FILE}"), + get_path("{HEADER_GEN_TEST_SYSZ_OUT_FILE}"), + "systemz", + ) + self.compat_gen.generate_v5_compat_header() + with open(get_path("{HEADER_GEN_TEST_SYSZ_FILE}")) as f: + correct = f.read() + with open(get_path("{HEADER_GEN_TEST_SYSZ_OUT_FILE}")) as f: + self.assertEqual(f.read(), correct) diff --git a/suite/auto-sync/src/autosync/Tests/test_mcupdater.py b/suite/auto-sync/src/autosync/Tests/test_mcupdater.py index eefa205179..dd6f29dd6c 100644 --- a/suite/auto-sync/src/autosync/Tests/test_mcupdater.py +++ b/suite/auto-sync/src/autosync/Tests/test_mcupdater.py @@ -3,10 +3,12 @@ import logging import os +import shutil import sys import unittest from pathlib import Path +from threading import Lock from autosync.Helper import get_path, test_only_overwrite_path_var from autosync.MCUpdater import MCUpdater @@ -20,22 +22,34 @@ def setUpClass(cls): format="%(levelname)-5s - %(message)s", force=True, ) + cls.mutex = Lock() + + @staticmethod + def del_path(file: Path): + if not file.exists(): + return + logging.debug(f"Delete old file: {file}") + if file.is_dir(): + shutil.rmtree(file) + else: + os.remove(file) def test_test_case_gen(self): """ To enforce sequential execution of the tests, we execute them in here. And don't make them a separated test. """ - self.assertTrue(self.unified_test_cases(), "Failed: unified_test_cases") - self.assertTrue(self.separated_test_cases(), "Failed: separated_test_cases") - self.assertTrue( - self.multi_mode_unified_test_cases(), - "Failed: multi_mode_unified_test_cases", - ) - self.assertTrue( - self.multi_mode_separated_test_cases(), - "Failed: multi_mode_separated_test_cases", - ) + with self.mutex: + self.assertTrue(self.unified_test_cases(), "Failed: unified_test_cases") + self.assertTrue(self.separated_test_cases(), "Failed: separated_test_cases") + self.assertTrue( + self.multi_mode_unified_test_cases(), + "Failed: multi_mode_unified_test_cases", + ) + self.assertTrue( + self.multi_mode_separated_test_cases(), + "Failed: multi_mode_separated_test_cases", + ) def unified_test_cases(self): out_dir = Path( @@ -44,8 +58,7 @@ def unified_test_cases(self): if not out_dir.exists(): out_dir.mkdir(parents=True) for file in out_dir.iterdir(): - logging.debug(f"Delete old file: {file}") - os.remove(file) + self.del_path(file) test_only_overwrite_path_var( "{MCUPDATER_OUT_DIR}", out_dir, @@ -63,8 +76,7 @@ def separated_test_cases(self): if not out_dir.exists(): out_dir.mkdir(parents=True) for file in out_dir.iterdir(): - logging.debug(f"Delete old file: {file}") - os.remove(file) + self.del_path(file) test_only_overwrite_path_var( "{MCUPDATER_OUT_DIR}", out_dir, @@ -82,8 +94,7 @@ def multi_mode_unified_test_cases(self): if not out_dir.exists(): out_dir.mkdir(parents=True) for file in out_dir.iterdir(): - logging.debug(f"Delete old file: {file}") - os.remove(file) + self.del_path(file) test_only_overwrite_path_var( "{MCUPDATER_OUT_DIR}", out_dir, @@ -108,8 +119,7 @@ def multi_mode_separated_test_cases(self): if not out_dir.exists(): out_dir.mkdir(parents=True) for file in out_dir.iterdir(): - logging.debug(f"Delete old file: {file}") - os.remove(file) + self.del_path(file) test_only_overwrite_path_var( "{MCUPDATER_OUT_DIR}", out_dir, @@ -128,28 +138,57 @@ def multi_mode_separated_test_cases(self): ) def test_no_symbol_tests(self): - out_dir = Path(get_path("{MCUPDATER_TEST_OUT_DIR}").joinpath("no_symbol")) - if not out_dir.exists(): - out_dir.mkdir(parents=True) - for file in out_dir.iterdir(): - logging.debug(f"Delete old file: {file}") - os.remove(file) - test_only_overwrite_path_var( - "{MCUPDATER_OUT_DIR}", - out_dir, - ) - self.updater = MCUpdater( - "ARCH", - get_path("{MCUPDATER_TEST_DIR}"), - [], - [], - False, - ) - self.updater.gen_all() - self.assertFalse( - out_dir.joinpath("test_no_symbol.s.txt.yaml").exists(), - "File should not exist", - ) + with self.mutex: + out_dir = Path(get_path("{MCUPDATER_TEST_OUT_DIR}").joinpath("no_symbol")) + if not out_dir.exists(): + out_dir.mkdir(parents=True) + for file in out_dir.iterdir(): + self.del_path(file) + test_only_overwrite_path_var( + "{MCUPDATER_OUT_DIR}", + out_dir, + ) + self.updater = MCUpdater( + "ARCH", + get_path("{MCUPDATER_TEST_DIR}"), + [], + [], + False, + ) + self.updater.gen_all() + self.assertFalse( + out_dir.joinpath("test_no_symbol.s.txt.yaml").exists(), + "File should not exist", + ) + + def test_systemz_mapping(self): + with self.mutex: + out_dir = Path( + get_path("{MCUPDATER_TEST_OUT_DIR}").joinpath("mode_mapping/") + ) + if not out_dir.exists(): + out_dir.mkdir(parents=True) + for file in out_dir.iterdir(): + self.del_path(file) + test_only_overwrite_path_var( + "{MCUPDATER_OUT_DIR}", + out_dir, + ) + self.updater = MCUpdater( + "SystemZ", + get_path("{MCUPDATER_TEST_DIR}"), + [], + [], + False, + ) + self.updater.gen_all() + self.assertTrue( + self.compare_files( + out_dir, + ["test_systemz_mapping.txt.yaml"], + ), + "File mismatch", + ) def compare_files(self, out_dir: Path, filenames: list[str]) -> bool: if not out_dir.is_dir(): @@ -159,11 +198,13 @@ def compare_files(self, out_dir: Path, filenames: list[str]) -> bool: parent_name = out_dir.parent.name expected_dir = ( get_path("{MCUPDATER_TEST_DIR_EXPECTED}") - .joinpath(parent_name) - .joinpath(out_dir.name) + # Dirty for now. Sorry. + .joinpath(parent_name if parent_name != "test_output" else "").joinpath( + out_dir.name + ) ) if not expected_dir.exists() or not expected_dir.is_dir(): - logging.error(f"{expected_dir} is not a directory.") + logging.error(f"Expected: {expected_dir} is not a directory.") return False for file in filenames: efile = expected_dir.joinpath(file) diff --git a/suite/auto-sync/src/autosync/Tests/test_systemz_header.h b/suite/auto-sync/src/autosync/Tests/test_systemz_header.h new file mode 100644 index 0000000000..bbd122fe3f --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/test_systemz_header.h @@ -0,0 +1,142 @@ + +/// Enums corresponding to SystemZ condition codes +typedef enum systemz_cc { + SYSTEMZ_CC_O, + SYSTEMZ_CC_H, + + SYSTEMZ_CC_NH, + SYSTEMZ_CC_NO, + SYSTEMZ_CC_INVALID, +} systemz_cc; + +/// Group of SystemZ instructions +typedef enum systemz_insn_group { + SYSTEMZ_GRP_INVALID = 0, ///< = CS_GRP_INVALID + + // Generic groups + // all jump instructions (conditional+direct+indirect jumps) + SYSTEMZ_GRP_JUMP, ///< = CS_GRP_JUMP + SYSTEMZ_GRP_CALL, ///< CS_GRP_CALL + SYSTEMZ_GRP_RET, ///< CS_GRP_RET + SYSTEMZ_GRP_INT, ///< CS_GRP_INT + SYSTEMZ_GRP_IRET, ///< CS_GRP_IRET + SYSTEMZ_GRP_PRIVILEGE, ///< CS_GRP_PRIVILEGE + SYSTEMZ_GRP_BRANCH_RELATIVE, ///< CS_GRP_BRANCH_RELATIVE + // generated content begin + // clang-format off + + SYSTEMZ_FEATURE_FEATURESOFTFLOAT = 128, + SYSTEMZ_FEATURE_FEATUREBACKCHAIN, + SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, + SYSTEMZ_FEATURE_FEATUREFASTSERIALIZATION, + SYSTEMZ_FEATURE_FEATURERESETDATPROTECTION, + SYSTEMZ_FEATURE_FEATUREPROCESSORACTIVITYINSTRUMENTATION, + + // clang-format on + // generated content end + + SYSTEMZ_GRP_ENDING, // <-- mark the end of the list of groups +} systemz_insn_group; + + +/// Operand type for instruction's operands +typedef enum systemz_op_type { + SYSTEMZ_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized). + SYSTEMZ_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand). + SYSTEMZ_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand). + SYSTEMZ_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand). +} systemz_op_type; + +/// SystemZ registers +typedef enum systemz_reg { + // generated content begin + // clang-format off + + SYSTEMZ_REG_INVALID = 0, + SYSTEMZ_REG_CC = 1, + SYSTEMZ_REG_FPC = 2, + SYSTEMZ_REG_R12Q = 193, + SYSTEMZ_REG_R14Q = 194, + SYSTEMZ_REG_ENDING, // 195 + + // clang-format on + // generated content end + + // alias registers + // None +} systemz_reg; + +typedef struct { + systemz_insn_form form; +} systemz_suppl_info; + +/// Instruction's operand referring to memory +/// This is associated with SYSTEMZ_OP_MEM operand type above +typedef struct systemz_op_mem { + systemz_addr_mode am; ///< Address mode. Indicates which field below are set. + uint8_t /* systemz_reg */ base; ///< base register, can be safely interpreted as + ///< a value of type `systemz_reg`, but it is only + ///< one byte wide + uint8_t /* systemz_reg */ index; ///< Index register, same conditions apply here + uint64_t length; ///< Length component. Can be a register or immediate. + int64_t disp; ///< displacement/offset value +} systemz_op_mem; + +/// Instruction operand +typedef struct cs_systemz_op { + systemz_op_type type; ///< operand type + union { + systemz_reg reg; ///< register value for REG operand + int64_t imm; ///< immediate value for IMM operand + systemz_op_mem mem; ///< base/disp value for MEM operand + }; + cs_ac_type access; ///< R/W access of the operand. + uint8_t imm_width; ///< Bit width of the immediate. 0 if not specified. +} cs_systemz_op; + +#define MAX_SYSTEMZ_OPS 6 + +// Instruction structure +typedef struct cs_systemz { + systemz_cc cc; ///< Code condition + systemz_insn_form format; ///< The instruction format. + /// Number of operands of this instruction, + /// or 0 when instruction has no operand. + uint8_t op_count; + cs_systemz_op operands[MAX_SYSTEMZ_OPS]; ///< operands for this instruction. +} cs_systemz; + +/// SystemZ instruction +typedef enum systemz_insn { + // generated content begin + // clang-format off + + SYSTEMZ_INS_INVALID, + SYSTEMZ_INS_A, + SYSTEMZ_INS_ZAP, + + // clang-format on + // generated content end + + SYSTEMZ_INS_ENDING, + + SYSTEMZ_INS_ALIAS_BEGIN, + // generated content begin + // clang-format off + + SYSTEMZ_INS_ALIAS_VISTRB, // Real instr.: SYSTEMZ_VISTRB + SYSTEMZ_INS_ALIAS_VSTRCZFS, // Real instr.: SYSTEMZ_VSTRCZFS + SYSTEMZ_INS_ALIAS_VSTRSH, // Real instr.: SYSTEMZ_VSTRSH + SYSTEMZ_INS_ALIAS_VSTRSF, // Real instr.: SYSTEMZ_VSTRSF + + // clang-format on + // generated content end + + // Hard-coded alias come here + + SYSTEMZ_INS_ALIAS_END, +} systemz_insn; + +#ifdef CAPSTONE_SYSTEMZ_COMPAT_HEADER +#include "systemz_compatibility.h" +#endif diff --git a/suite/auto-sync/src/autosync/Tests/test_sysz_header.h b/suite/auto-sync/src/autosync/Tests/test_sysz_header.h new file mode 100644 index 0000000000..cf9af2e145 --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/test_sysz_header.h @@ -0,0 +1,83 @@ + +typedef enum { + SYSZ_CC_O = SYSTEMZ_CC_O, + SYSZ_CC_H = SYSTEMZ_CC_H, + + SYSZ_CC_NH = SYSTEMZ_CC_NH, + SYSZ_CC_NO = SYSTEMZ_CC_NO, + SYSZ_CC_INVALID = SYSTEMZ_CC_INVALID, +} sysz_cc; + +typedef enum { + SYSZ_GRP_INVALID = SYSTEMZ_GRP_INVALID, + + SYSZ_GRP_JUMP = SYSTEMZ_GRP_JUMP, + SYSZ_GRP_CALL = SYSTEMZ_GRP_CALL, + SYSZ_GRP_RET = SYSTEMZ_GRP_RET, + SYSZ_GRP_INT = SYSTEMZ_GRP_INT, + SYSZ_GRP_IRET = SYSTEMZ_GRP_IRET, + SYSZ_GRP_PRIVILEGE = SYSTEMZ_GRP_PRIVILEGE, + SYSZ_GRP_BRANCH_RELATIVE = SYSTEMZ_GRP_BRANCH_RELATIVE, + + SYSZ_FEATURE_FEATURESOFTFLOAT = SYSTEMZ_FEATURE_FEATURESOFTFLOAT, + SYSZ_FEATURE_FEATUREBACKCHAIN = SYSTEMZ_FEATURE_FEATUREBACKCHAIN, + SYSZ_FEATURE_FEATUREDISTINCTOPS = SYSTEMZ_FEATURE_FEATUREDISTINCTOPS, + SYSZ_FEATURE_FEATUREFASTSERIALIZATION = SYSTEMZ_FEATURE_FEATUREFASTSERIALIZATION, + SYSZ_FEATURE_FEATURERESETDATPROTECTION = SYSTEMZ_FEATURE_FEATURERESETDATPROTECTION, + SYSZ_FEATURE_FEATUREPROCESSORACTIVITYINSTRUMENTATION = SYSTEMZ_FEATURE_FEATUREPROCESSORACTIVITYINSTRUMENTATION, + + + SYSZ_GRP_ENDING = SYSTEMZ_GRP_ENDING, +} sysz_insn_group; + + +typedef enum { + SYSZ_OP_INVALID = SYSTEMZ_OP_INVALID, + SYSZ_OP_REG = SYSTEMZ_OP_REG, + SYSZ_OP_IMM = SYSTEMZ_OP_IMM, + SYSZ_OP_MEM = SYSTEMZ_OP_MEM, +} sysz_op_type; + +typedef enum { + + SYSZ_REG_INVALID = SYSTEMZ_REG_INVALID, + SYSZ_REG_CC = SYSTEMZ_REG_CC, + SYSZ_REG_FPC = SYSTEMZ_REG_FPC, + SYSZ_REG_R12Q = SYSTEMZ_REG_R12Q, + SYSZ_REG_R14Q = SYSTEMZ_REG_R14Q, + SYSZ_REG_ENDING = SYSTEMZ_REG_ENDING, + + +} sysz_reg; + +typedef systemz_suppl_info sysz_suppl_info; + +typedef systemz_op_mem sysz_op_mem; + +typedef cs_systemz_op cs_sysz_op; + +#define MAX_SYSZ_OPS 6 + +typedef cs_systemz cs_sysz; + +typedef enum { + + SYSZ_INS_INVALID = SYSTEMZ_INS_INVALID, + SYSZ_INS_A = SYSTEMZ_INS_A, + SYSZ_INS_ZAP = SYSTEMZ_INS_ZAP, + + + SYSZ_INS_ENDING = SYSTEMZ_INS_ENDING, + + SYSZ_INS_ALIAS_BEGIN = SYSTEMZ_INS_ALIAS_BEGIN, + + SYSZ_INS_ALIAS_VISTRB = SYSTEMZ_INS_ALIAS_VISTRB, + SYSZ_INS_ALIAS_VSTRCZFS = SYSTEMZ_INS_ALIAS_VSTRCZFS, + SYSZ_INS_ALIAS_VSTRSH = SYSTEMZ_INS_ALIAS_VSTRSH, + SYSZ_INS_ALIAS_VSTRSF = SYSTEMZ_INS_ALIAS_VSTRSF, + + + + SYSZ_INS_ALIAS_END = SYSTEMZ_INS_ALIAS_END, +} sysz_insn; + diff --git a/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py b/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py index 38d28adac5..2535cc6684 100755 --- a/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py +++ b/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py @@ -6,6 +6,7 @@ import argparse import logging as log import sys +import re from pathlib import Path import termcolor @@ -87,6 +88,7 @@ print_prominent_warning, run_clang_format, ) +from autosync.cpptranslator.patches.isUInt import IsUInt class Translator: @@ -136,6 +138,7 @@ class Translator: CreateOperand0.__name__: 0, # ◁───┐ `CreateOperand0` removes most calls to MI.addOperand(). AddOperand.__name__: 1, # ────────┘ The ones left are fixed with the `AddOperand` patch. CreateOperand1.__name__: 0, + IsUInt.__name__: 0, GetOpcode.__name__: 0, SetOpcode.__name__: 0, GetOperand.__name__: 0, @@ -248,6 +251,8 @@ def init_patches(self): patch = CreateOperand0(p) case CreateOperand1.__name__: patch = CreateOperand1(p) + case IsUInt.__name__: + patch = IsUInt(p) case GetOpcode.__name__: patch = GetOpcode(p) case SetOpcode.__name__: @@ -391,6 +396,17 @@ def apply_patch(self, patch: Patch) -> bool: file_constraints = apply_only_to[patch_name] if self.current_src_path_in.name in file_constraints["files"]: return True + elif ( + re.search("InstPrinter.cpp", self.current_src_path_in.name) + and patch_name == AddCSDetail.__name__ + ): + print_prominent_warning( + ( + f"The AddCSDetail patch is not applied to {self.current_src_path_in.name}. " + "Have you forgotten to add it to arch_config.json?" + ), + False, + ) return False def translate(self) -> None: diff --git a/suite/auto-sync/src/autosync/cpptranslator/Differ.py b/suite/auto-sync/src/autosync/cpptranslator/Differ.py index b65c85b04d..2bf338ad41 100755 --- a/suite/auto-sync/src/autosync/cpptranslator/Differ.py +++ b/suite/auto-sync/src/autosync/cpptranslator/Differ.py @@ -16,6 +16,7 @@ from tree_sitter import Language, Node, Parser, Tree +from autosync.Targets import ARCH_LLVM_NAMING from autosync.cpptranslator.Configurator import Configurator from autosync.Helper import ( bold, @@ -925,7 +926,7 @@ def parse_args() -> argparse.Namespace: "-a", dest="arch", help="Name of target architecture (ignored with -t option)", - choices=["ARM", "PPC", "AArch64", "Alpha", "LoongArch", "Mips"], + choices=ARCH_LLVM_NAMING, required=True, ) parser.add_argument( diff --git a/suite/auto-sync/src/autosync/cpptranslator/Tests/test_patches.py b/suite/auto-sync/src/autosync/cpptranslator/Tests/test_patches.py index f84b38e5f4..45f4874d16 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/Tests/test_patches.py +++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/test_patches.py @@ -78,6 +78,7 @@ from autosync.cpptranslator.patches.UsingDeclaration import UsingDeclaration from autosync.cpptranslator.TemplateCollector import TemplateCollector from autosync.Helper import get_path +from autosync.cpptranslator.patches.isUInt import IsUInt class TestPatches(unittest.TestCase): @@ -132,7 +133,7 @@ def test_addoperand(self): def test_assert(self): patch = Assert(0) syntax = b"assert(0 == 0)" - self.check_patching_result(patch, syntax, b"") + self.check_patching_result(patch, syntax, b"CS_ASSERT((0 == 0));") def test_bitcaststdarray(self): patch = BitCastStdArray(0) @@ -308,11 +309,21 @@ def test_getoperand(self): syntax = b"MI.getOperand(0);" self.check_patching_result(patch, syntax, b"MCInst_getOperand(MI, (0))") - def test_getoperandregimm(self): + def test_getoperandreg(self): patch = GetOperandRegImm(0) syntax = b"OPERAND.getReg()" self.check_patching_result(patch, syntax, b"MCOperand_getReg(OPERAND)") + def test_getoperandimm(self): + patch = GetOperandRegImm(0) + syntax = b"OPERAND.getImm()" + self.check_patching_result(patch, syntax, b"MCOperand_getImm(OPERAND)") + + def test_getoperandexpr(self): + patch = GetOperandRegImm(0) + syntax = b"OPERAND.getExpr()" + self.check_patching_result(patch, syntax, b"MCOperand_getExpr(OPERAND)") + def test_getregclass(self): patch = GetRegClass(0) syntax = b"MRI.getRegClass(RegClass);" @@ -378,11 +389,21 @@ def test_ispredicate(self): b"MCOperandInfo_isPredicate(&OpInfo[i])", ) - def test_isregimm(self): + def test_isreg(self): patch = IsOperandRegImm(0) syntax = b"OPERAND.isReg()" self.check_patching_result(patch, syntax, b"MCOperand_isReg(OPERAND)") + def test_isimm(self): + patch = IsOperandRegImm(0) + syntax = b"OPERAND.isImm()" + self.check_patching_result(patch, syntax, b"MCOperand_isImm(OPERAND)") + + def test_isexpr(self): + patch = IsOperandRegImm(0) + syntax = b"OPERAND.isExpr()" + self.check_patching_result(patch, syntax, b"MCOperand_isExpr(OPERAND)") + def test_llvmfallthrough(self): patch = LLVMFallThrough(0) syntax = b"LLVM_FALLTHROUGH;" @@ -579,3 +600,8 @@ def test_usingdecl(self): patch = UsingDeclaration(0) syntax = b"using namespace llvm;" self.check_patching_result(patch, syntax, b"") + + def test_isuintn(self): + patch = IsUInt(0) + syntax = b"isUInt(FirstRU);" + self.check_patching_result(patch, syntax, b"isUIntN(RegUnitBits, FirstRU)") diff --git a/suite/auto-sync/src/autosync/cpptranslator/arch_config.json b/suite/auto-sync/src/autosync/cpptranslator/arch_config.json index 3de3c4efe5..d75297de79 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/arch_config.json +++ b/suite/auto-sync/src/autosync/cpptranslator/arch_config.json @@ -13,7 +13,8 @@ "PPCInstPrinter.cpp", "AArch64InstPrinter.cpp", "LoongArchInstPrinter.cpp", - "MipsInstPrinter.cpp" + "MipsInstPrinter.cpp", + "SystemZInstPrinter.cpp" ] }, "InlineToStaticInline": { @@ -213,5 +214,33 @@ "isReg" ], "manually_edited_files": [] + }, + "SystemZ": { + "files_to_translate": [ + { + "in": "{LLVM_ROOT}/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp", + "out": "SystemZDisassembler.c" + },{ + "in": "{LLVM_ROOT}/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp", + "out": "SystemZInstPrinter.c" + },{ + "in": "{LLVM_ROOT}/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.h", + "out": "SystemZInstPrinter.h" + },{ + "in": "{LLVM_ROOT}/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp", + "out": "SystemZMCTargetDesc.c" + },{ + "in": "{LLVM_ROOT}/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h", + "out": "SystemZMCTargetDesc.h" + } + ], + "files_for_template_search": [ + "{CPP_INC_OUT_DIR}/SystemZGenDisassemblerTables.inc", + "{CPP_INC_OUT_DIR}/SystemZGenAsmWriter.inc", + "{LLVM_ROOT}/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp", + "{LLVM_ROOT}/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp" + ], + "templates_with_arg_deduction": [], + "manually_edited_files": [] } } diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py b/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py index 84afa6952c..9d76f040ee 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py @@ -35,6 +35,7 @@ class AddCSDetail(Patch): b"(SStream*O,ARM_AM::ShiftOpcShOpc,unsignedShImm,boolgetUseMarkup())", # ARM - printRegImmShift b"(MCInst*MI,unsignedOpNo,SStream*O,constchar*Modifier)", # PPC - printPredicateOperand b"(MCInst*MI,uint64_tAddress,unsignedOpNo,SStream*O)", # PPC - printBranchOperand + b"(MCInst*MI,intOpNum,SStream*O)", # SystemZ ] def __init__(self, priority: int, arch: str): diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/Assert.py b/suite/auto-sync/src/autosync/cpptranslator/patches/Assert.py index ce439dc2c8..f058080c6f 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/Assert.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/Assert.py @@ -3,6 +3,7 @@ from tree_sitter import Node +from autosync.cpptranslator.patches.Helper import get_text from autosync.cpptranslator.patches.Patch import Patch @@ -19,7 +20,7 @@ def get_search_pattern(self) -> str: "(expression_statement" " (call_expression" ' ((identifier) @id (#eq? @id "assert"))' - " (argument_list)" + " ((argument_list) @arg_list)" " )" ") @assert" ) @@ -27,5 +28,9 @@ def get_search_pattern(self) -> str: def get_main_capture_name(self) -> str: return "assert" - def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: - return b"" + def get_patch( + self, captures: list[tuple[Node, str]], src: bytes, **kwargs + ) -> bytes: + arg_list = captures[2][0] + args = get_text(src, arg_list.start_byte, arg_list.end_byte) + return b"CS_ASSERT(" + args + b");" diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/GetOperandRegImm.py b/suite/auto-sync/src/autosync/cpptranslator/patches/GetOperandRegImm.py index c47b390389..af9f8edc67 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/GetOperandRegImm.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/GetOperandRegImm.py @@ -23,7 +23,7 @@ def get_search_pattern(self) -> str: "(call_expression" " (field_expression" " ((_) @operand)" - ' ((field_identifier) @field_id (#match? @field_id "get(Reg|Imm)"))' + ' ((field_identifier) @field_id (#match? @field_id "get(Reg|Imm|Expr)"))' " )" ' ((argument_list) @arg_list (#eq? @arg_list "()"))' ") @get_operand" @@ -36,7 +36,7 @@ def get_main_capture_name(self) -> str: def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: # The operand operand: Node = get_capture_node(captures, "operand") - # 'getReg()/getImm()' + # 'getReg()/getImm()\getExpr' get_reg_imm = get_capture_node(captures, "field_id") fcn = get_text(src, get_reg_imm.start_byte, get_reg_imm.end_byte) diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py b/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py index 01b69b5bec..6d9cf46296 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py @@ -66,6 +66,8 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: return res + get_LoongArch_includes(filename) + get_general_macros() case "Mips": return res + get_Mips_includes(filename) + get_general_macros() + case "SystemZ": + return res + get_SystemZ_includes(filename) + get_general_macros() case "TEST_ARCH": return res + b"test_output" case _: @@ -333,6 +335,59 @@ def get_Mips_includes(filename: str) -> bytes: exit(1) +def get_SystemZ_includes(filename: str) -> bytes: + match filename: + case "SystemZDisassembler.cpp": + return ( + b'#include "../../MCInst.h"\n' + + b'#include "../../MathExtras.h"\n' + + b'#include "../../cs_priv.h"\n' + + b'#include "../../utils.h"\n\n' + + b'#include "SystemZMCTargetDesc.h"\n' + + b'#include "SystemZDisassemblerExtension.h"\n\n' + + b"#define GET_SUBTARGETINFO_ENUM\n" + + b'#include "SystemZGenSubtargetInfo.inc"\n\n' + + b"#define GET_INSTRINFO_ENUM\n" + + b'#include "SystemZGenInstrInfo.inc"\n\n' + + b"#define GET_REGINFO_ENUM\n" + + b'#include "SystemZGenRegisterInfo.inc"\n\n' + ) + case "SystemZInstPrinter.cpp": + return ( + b'#include "../../MCAsmInfo.h"\n' + + b'#include "SystemZMapping.h"\n' + + b'#include "SystemZInstPrinter.h"\n\n' + + b"#define GET_SUBTARGETINFO_ENUM\n" + + b'#include "SystemZGenSubtargetInfo.inc"\n\n' + + b"#define GET_INSTRINFO_ENUM\n" + + b'#include "SystemZGenInstrInfo.inc"\n\n' + + b"#define GET_REGINFO_ENUM\n" + + b'#include "SystemZGenRegisterInfo.inc"\n\n' + ) + case "SystemZInstPrinter.h": + return b"\n" + case "SystemZMCTargetDesc.h": + return ( + b'#include "../../MCInstPrinter.h"\n' + b'#include "../../cs_priv.h"\n' + ) + case "SystemZMCTargetDesc.cpp": + return ( + b'#include "../../MCInst.h"\n' + + b'#include "../../MCRegisterInfo.h"\n\n' + + b'#include "SystemZMCTargetDesc.h"\n' + + b'#include "SystemZInstPrinter.h"\n\n' + + b"#define GET_INSTRINFO_MC_DESC\n" + + b"#define ENABLE_INSTR_PREDICATE_VERIFIER\n" + + b'#include "SystemZGenInstrInfo.inc"\n\n' + + b"#define GET_SUBTARGETINFO_MC_DESC\n" + + b'#include "SystemZGenSubtargetInfo.inc"\n\n' + + b"#define GET_REGINFO_MC_DESC\n" + + b'#include "SystemZGenRegisterInfo.inc"\n\n' + ) + log.fatal(f"No includes given for SystemZ source file: {filename}") + exit(1) + + def get_general_macros(): return ( b"#define CONCAT(a, b) CONCAT_(a, b)\n" b"#define CONCAT_(a, b) a ## _ ## b\n" diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/IsRegImm.py b/suite/auto-sync/src/autosync/cpptranslator/patches/IsRegImm.py index 7fe5f14267..b8c02d8c16 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/IsRegImm.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/IsRegImm.py @@ -23,7 +23,7 @@ def get_search_pattern(self) -> str: "(call_expression" " (field_expression" " ((_) @operand)" - ' ((field_identifier) @field_id (#match? @field_id "is(Reg|Imm)"))' + ' ((field_identifier) @field_id (#match? @field_id "is(Reg|Imm|Expr)"))' " )" " (argument_list)" ") @is_operand" @@ -36,7 +36,7 @@ def get_main_capture_name(self) -> str: def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: # The operand operand: Node = captures[1][0] - # 'isReg()/isImm()' + # 'isReg()/isImm()/isExpr' get_reg_imm = captures[2][0] fcn = get_text(src, get_reg_imm.start_byte, get_reg_imm.end_byte) diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/isUInt.py b/suite/auto-sync/src/autosync/cpptranslator/patches/isUInt.py new file mode 100644 index 0000000000..69403a1d27 --- /dev/null +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/isUInt.py @@ -0,0 +1,45 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + +from tree_sitter import Node + +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch +from autosync.cpptranslator.TemplateCollector import TemplateCollector + + +class IsUInt(Patch): + """ + Patch isUInt(...) + to isUInt(..., N) + """ + + def __init__(self, priority: int): + super().__init__(priority) + + def get_search_pattern(self) -> str: + return ( + "(call_expression" + " (template_function" + ' ((identifier) @id (#eq? @id "isUInt"))' + " ((template_argument_list) @templ_args)" + " )" + " ((argument_list) @arg_list)" + ") @is_u_int" + ) + + def get_main_capture_name(self) -> str: + return "is_u_int" + + def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: + identifier: Node = captures[1][0] + templ_args: Node = captures[2][0] + args_list: Node = captures[3][0] + + name = get_text(src, identifier.start_byte, identifier.end_byte) + targs = get_text(src, templ_args.start_byte, templ_args.end_byte).strip(b"<>") + args = get_text(src, args_list.start_byte, args_list.end_byte).strip(b"()") + + res = name + b"N(" + targs + b", " + args + b")" + + return res diff --git a/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json b/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json index 6781acfaa5..9b50870d57 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json +++ b/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json @@ -3291,4 +3291,4 @@ "edit": "" } } -} \ No newline at end of file +} diff --git a/suite/auto-sync/src/autosync/inc_gen.json b/suite/auto-sync/src/autosync/inc_gen.json new file mode 100644 index 0000000000..dad25f703d --- /dev/null +++ b/suite/auto-sync/src/autosync/inc_gen.json @@ -0,0 +1,53 @@ +{ + "inc_tables": [ + { + "name": "Disassembler", + "tblgen_arg": "--gen-disassembler", + "inc_name": "DisassemblerTables", + "only_arch": [], + "lang": ["CCS", "C++"] + }, + { + "name": "AsmWriter", + "tblgen_arg": "--gen-asm-writer", + "inc_name": "AsmWriter", + "only_arch": [], + "lang": ["CCS", "C++"] + }, + { + "name": "RegisterInfo", + "tblgen_arg": "--gen-register-info", + "inc_name": "RegisterInfo", + "only_arch": [], + "lang": ["CCS"] + }, + { + "name": "InstrInfo", + "tblgen_arg": "--gen-instr-info", + "inc_name": "InstrInfo", + "only_arch": [], + "lang": ["CCS"] + }, + { + "name": "SubtargetInfo", + "tblgen_arg": "--gen-subtarget", + "inc_name": "SubtargetInfo", + "only_arch": [], + "lang": ["CCS"] + }, + { + "name": "Mapping", + "tblgen_arg": "--gen-asm-matcher", + "inc_name": "", + "only_arch": [], + "lang": ["CCS"] + }, + { + "name": "SystemOperand", + "tblgen_arg": "--gen-searchable-tables", + "inc_name": "", + "only_arch": ["AArch64", "ARM"], + "lang": ["CCS"] + } + ] +} diff --git a/suite/auto-sync/src/autosync/mcupdater.json b/suite/auto-sync/src/autosync/mcupdater.json index 71fb8218d4..92a6fb9651 100644 --- a/suite/auto-sync/src/autosync/mcupdater.json +++ b/suite/auto-sync/src/autosync/mcupdater.json @@ -1,4 +1,7 @@ { + "unify_test_cases": [ + "ARM" + ], "additional_mattr": { "AArch64": @@ -15,6 +18,18 @@ "Mips": [ "CS_OPT_SYNTAX_NOREGNAME" + ], + "PPC": + [ + "CS_OPT_NO_BRANCH_OFFSET" + ], + "ARM": + [ + "CS_OPT_NO_BRANCH_OFFSET" + ], + "AArch64": + [ + "CS_OPT_NO_BRANCH_OFFSET" ] }, "remove_options": @@ -74,6 +89,23 @@ "i7200": "CS_MODE_I7200", "mips_nofloat": "CS_MODE_MIPS_NOFLOAT", "mips_ptr64": "CS_MODE_MIPS_PTR64" + }, + "SystemZ": { + "arch8": "CS_MODE_SYSTEMZ_ARCH8", + "arch9": "CS_MODE_SYSTEMZ_ARCH9", + "arch10": "CS_MODE_SYSTEMZ_ARCH10", + "arch11": "CS_MODE_SYSTEMZ_ARCH11", + "arch12": "CS_MODE_SYSTEMZ_ARCH12", + "arch13": "CS_MODE_SYSTEMZ_ARCH13", + "arch14": "CS_MODE_SYSTEMZ_ARCH14", + "z10": "CS_MODE_SYSTEMZ_Z10", + "z196": "CS_MODE_SYSTEMZ_Z196", + "zec12": "CS_MODE_SYSTEMZ_ZEC12", + "z13": "CS_MODE_SYSTEMZ_Z13", + "z14": "CS_MODE_SYSTEMZ_Z14", + "z15": "CS_MODE_SYSTEMZ_Z15", + "z16": "CS_MODE_SYSTEMZ_Z16", + "generic": "CS_MODE_SYSTEMZ_GENERIC" } } -} \ No newline at end of file +} diff --git a/suite/auto-sync/src/autosync/path_vars.json b/suite/auto-sync/src/autosync/path_vars.json index 8f51c14bba..cbe15ef7c8 100644 --- a/suite/auto-sync/src/autosync/path_vars.json +++ b/suite/auto-sync/src/autosync/path_vars.json @@ -9,6 +9,7 @@ "{VENDOR_DIR}": "{AUTO_SYNC_ROOT}/vendor/", "{BUILD_DIR}": "{AUTO_SYNC_ROOT}/build/", "{C_INC_OUT_DIR}": "{BUILD_DIR}/llvm_c_inc/", + "{INC_GEN_CONF_FILE}": "{AUTO_SYNC_SRC}/inc_gen.json", "{CPP_INC_OUT_DIR}": "{BUILD_DIR}/llvm_cpp_inc/", "{CPP_TRANSLATOR_DIR}": "{AUTO_SYNC_SRC}/cpptranslator/", "{CPP_TRANSLATOR_CONFIG}": "{CPP_TRANSLATOR_DIR}/arch_config.json", @@ -27,6 +28,9 @@ "{HEADER_GEN_TEST_AARCH64_FILE}": "{AUTO_SYNC_SRC}/Tests/test_aarch64_header.h", "{HEADER_GEN_TEST_ARM64_FILE}": "{AUTO_SYNC_SRC}/Tests/test_arm64_header.h", "{HEADER_GEN_TEST_ARM64_OUT_FILE}": "{AUTO_SYNC_SRC}/Tests/test_arm64_header.h.out", + "{HEADER_GEN_TEST_SYSTEMZ_FILE}": "{AUTO_SYNC_SRC}/Tests/test_systemz_header.h", + "{HEADER_GEN_TEST_SYSZ_FILE}": "{AUTO_SYNC_SRC}/Tests/test_sysz_header.h", + "{HEADER_GEN_TEST_SYSZ_OUT_FILE}": "{AUTO_SYNC_SRC}/Tests/test_sysz_header.h.out", "{DIFFER_TEST_DIR}": "{CPP_TRANSLATOR_TEST_DIR}/Differ/", "{DIFFER_TEST_CONFIG_FILE}": "{DIFFER_TEST_DIR}/test_arch_config.json", "{DIFFER_TEST_OLD_SRC_DIR}": "{DIFFER_TEST_DIR}/old_src/", @@ -47,6 +51,7 @@ "{CPP_TRANSLATOR_TRANSLATION_OUT_DIR}", "{CPP_TRANSLATOR_DIFF_OUT_DIR}", "{HEADER_GEN_TEST_ARM64_OUT_FILE}", + "{HEADER_GEN_TEST_SYSZ_OUT_FILE}", "{MCUPDATER_OUT_DIR}", "{MCUPDATER_TEST_OUT_DIR}" ], diff --git a/suite/capstone_get_setup.c b/suite/capstone_get_setup.c index 2298db00ab..ae5d4c3898 100644 --- a/suite/capstone_get_setup.c +++ b/suite/capstone_get_setup.c @@ -34,7 +34,7 @@ int main() if (cs_support(CS_ARCH_SPARC)) { printf("sparc=1 "); } - if (cs_support(CS_ARCH_SYSZ)) { + if (cs_support(CS_ARCH_SYSTEMZ)) { printf("sysz=1 "); } if (cs_support(CS_ARCH_XCORE)) { diff --git a/suite/cstest/include/test_detail_systemz.h b/suite/cstest/include/test_detail_systemz.h index d7c0231a08..3f886627f6 100644 --- a/suite/cstest/include/test_detail_systemz.h +++ b/suite/cstest/include/test_detail_systemz.h @@ -10,9 +10,12 @@ typedef struct { char *type; + char *access; char *reg; int64_t imm; + uint8_t imm_width; + char *mem_am; char *mem_base; char *mem_index; int64_t mem_disp; @@ -22,9 +25,16 @@ typedef struct { static const cyaml_schema_field_t test_detail_systemz_op_mapping_schema[] = { CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetailSystemZOp, type, 0, CYAML_UNLIMITED), + CYAML_FIELD_STRING_PTR("access", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSystemZOp, access, 0, CYAML_UNLIMITED), CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetailSystemZOp, reg, 0, CYAML_UNLIMITED), CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailSystemZOp, imm), + CYAML_FIELD_UINT("imm_width", CYAML_FLAG_OPTIONAL, TestDetailSystemZOp, + imm_width), + CYAML_FIELD_STRING_PTR( + "mem_am", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSystemZOp, mem_am, 0, CYAML_UNLIMITED), CYAML_FIELD_STRING_PTR( "mem_base", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetailSystemZOp, mem_base, 0, CYAML_UNLIMITED), @@ -44,11 +54,15 @@ static const cyaml_schema_value_t test_detail_systemz_op_schema = { }; typedef struct { + char *format; TestDetailSystemZOp **operands; uint32_t operands_count; } TestDetailSystemZ; static const cyaml_schema_field_t test_detail_systemz_mapping_schema[] = { + CYAML_FIELD_STRING_PTR( + "format", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailSystemZ, format, 0, CYAML_UNLIMITED), CYAML_FIELD_SEQUENCE( "operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetailSystemZ, operands, &test_detail_systemz_op_schema, 0, @@ -65,7 +79,7 @@ TestDetailSystemZOp * test_detail_systemz_op_clone(const TestDetailSystemZOp *detail); void test_detail_systemz_op_free(TestDetailSystemZOp *detail); -bool test_expected_systemz(csh *handle, const cs_sysz *actual, +bool test_expected_systemz(csh *handle, const cs_systemz *actual, const TestDetailSystemZ *expected); #endif // TEST_DETAIL_SYSTEMZ_H diff --git a/suite/cstest/include/test_mapping.h b/suite/cstest/include/test_mapping.h index f796840b08..bab38b5545 100644 --- a/suite/cstest/include/test_mapping.h +++ b/suite/cstest/include/test_mapping.h @@ -31,7 +31,7 @@ static const cs_enum_id_map test_arch_map[] = { { .str = "CS_ARCH_RISCV", .val = CS_ARCH_RISCV }, { .str = "CS_ARCH_SH", .val = CS_ARCH_SH }, { .str = "CS_ARCH_SPARC", .val = CS_ARCH_SPARC }, - { .str = "CS_ARCH_SYSZ", .val = CS_ARCH_SYSZ }, + { .str = "CS_ARCH_SYSTEMZ", .val = CS_ARCH_SYSTEMZ }, { .str = "CS_ARCH_TMS320C64X", .val = CS_ARCH_TMS320C64X }, { .str = "CS_ARCH_TRICORE", .val = CS_ARCH_TRICORE }, { .str = "CS_ARCH_WASM", .val = CS_ARCH_WASM }, @@ -52,7 +52,7 @@ static const cs_enum_id_map test_arch_map[] = { { .str = "riscv", .val = CS_ARCH_RISCV }, { .str = "sh", .val = CS_ARCH_SH }, { .str = "sparc", .val = CS_ARCH_SPARC }, - { .str = "systemz", .val = CS_ARCH_SYSZ }, + { .str = "systemz", .val = CS_ARCH_SYSTEMZ }, { .str = "tms320c64x", .val = CS_ARCH_TMS320C64X }, { .str = "tricore", .val = CS_ARCH_TRICORE }, { .str = "wasm", .val = CS_ARCH_WASM }, @@ -142,6 +142,21 @@ static const cs_enum_id_map test_mode_map[] = { { .str = "CS_MODE_SHDSP", .val = CS_MODE_SHDSP }, { .str = "CS_MODE_SHFPU", .val = CS_MODE_SHFPU }, { .str = "CS_MODE_SPE", .val = CS_MODE_SPE }, + { .str = "CS_MODE_SYSTEMZ_ARCH10", .val = CS_MODE_SYSTEMZ_ARCH10 }, + { .str = "CS_MODE_SYSTEMZ_ARCH11", .val = CS_MODE_SYSTEMZ_ARCH11 }, + { .str = "CS_MODE_SYSTEMZ_ARCH12", .val = CS_MODE_SYSTEMZ_ARCH12 }, + { .str = "CS_MODE_SYSTEMZ_ARCH13", .val = CS_MODE_SYSTEMZ_ARCH13 }, + { .str = "CS_MODE_SYSTEMZ_ARCH14", .val = CS_MODE_SYSTEMZ_ARCH14 }, + { .str = "CS_MODE_SYSTEMZ_ARCH8", .val = CS_MODE_SYSTEMZ_ARCH8 }, + { .str = "CS_MODE_SYSTEMZ_ARCH9", .val = CS_MODE_SYSTEMZ_ARCH9 }, + { .str = "CS_MODE_SYSTEMZ_GENERIC", .val = CS_MODE_SYSTEMZ_GENERIC }, + { .str = "CS_MODE_SYSTEMZ_Z10", .val = CS_MODE_SYSTEMZ_Z10 }, + { .str = "CS_MODE_SYSTEMZ_Z13", .val = CS_MODE_SYSTEMZ_Z13 }, + { .str = "CS_MODE_SYSTEMZ_Z14", .val = CS_MODE_SYSTEMZ_Z14 }, + { .str = "CS_MODE_SYSTEMZ_Z15", .val = CS_MODE_SYSTEMZ_Z15 }, + { .str = "CS_MODE_SYSTEMZ_Z16", .val = CS_MODE_SYSTEMZ_Z16 }, + { .str = "CS_MODE_SYSTEMZ_Z196", .val = CS_MODE_SYSTEMZ_Z196 }, + { .str = "CS_MODE_SYSTEMZ_ZEC12", .val = CS_MODE_SYSTEMZ_ZEC12 }, { .str = "CS_MODE_THUMB", .val = CS_MODE_THUMB }, { .str = "CS_MODE_TRICORE_110", .val = CS_MODE_TRICORE_110 }, { .str = "CS_MODE_TRICORE_120", .val = CS_MODE_TRICORE_120 }, @@ -186,6 +201,7 @@ static const TestOptionMapEntry test_option_map[] = { static const cs_enum_id_map cs_enum_map[] = { { .str = "AAAAAAAAAAAAAAAAAAAAAAAAAA", .val = 0xffffff }, // For testing + { .str = "AAAAAAAAAAAAAAAAAAAAAAAAAB", .val = 0xffffff }, // For testing { .str = "AARCH64LAYOUT_INVALID", .val = AARCH64LAYOUT_INVALID }, { .str = "AARCH64LAYOUT_VL_16B", .val = AARCH64LAYOUT_VL_16B }, { .str = "AARCH64LAYOUT_VL_16S", .val = AARCH64LAYOUT_VL_16S }, @@ -1159,10 +1175,106 @@ static const cs_enum_id_map cs_enum_map[] = { { .str = "SPARC_OP_IMM", .val = SPARC_OP_IMM }, { .str = "SPARC_OP_MEM", .val = SPARC_OP_MEM }, { .str = "SPARC_OP_REG", .val = SPARC_OP_REG }, - { .str = "SYSZ_OP_ACREG", .val = SYSZ_OP_ACREG }, - { .str = "SYSZ_OP_IMM", .val = SYSZ_OP_IMM }, - { .str = "SYSZ_OP_MEM", .val = SYSZ_OP_MEM }, - { .str = "SYSZ_OP_REG", .val = SYSZ_OP_REG }, + { .str = "SYSTEMZ_AM_BD", .val = SYSTEMZ_AM_BD }, + { .str = "SYSTEMZ_AM_BDL", .val = SYSTEMZ_AM_BDL }, + { .str = "SYSTEMZ_AM_BDR", .val = SYSTEMZ_AM_BDR }, + { .str = "SYSTEMZ_AM_BDV", .val = SYSTEMZ_AM_BDV }, + { .str = "SYSTEMZ_AM_BDX", .val = SYSTEMZ_AM_BDX }, + { .str = "SYSTEMZ_CC_E", .val = SYSTEMZ_CC_E }, + { .str = "SYSTEMZ_CC_H", .val = SYSTEMZ_CC_H }, + { .str = "SYSTEMZ_CC_HE", .val = SYSTEMZ_CC_HE }, + { .str = "SYSTEMZ_CC_L", .val = SYSTEMZ_CC_L }, + { .str = "SYSTEMZ_CC_LE", .val = SYSTEMZ_CC_LE }, + { .str = "SYSTEMZ_CC_LH", .val = SYSTEMZ_CC_LH }, + { .str = "SYSTEMZ_CC_NE", .val = SYSTEMZ_CC_NE }, + { .str = "SYSTEMZ_CC_NH", .val = SYSTEMZ_CC_NH }, + { .str = "SYSTEMZ_CC_NHE", .val = SYSTEMZ_CC_NHE }, + { .str = "SYSTEMZ_CC_NL", .val = SYSTEMZ_CC_NL }, + { .str = "SYSTEMZ_CC_NLE", .val = SYSTEMZ_CC_NLE }, + { .str = "SYSTEMZ_CC_NLH", .val = SYSTEMZ_CC_NLH }, + { .str = "SYSTEMZ_CC_NO", .val = SYSTEMZ_CC_NO }, + { .str = "SYSTEMZ_CC_O", .val = SYSTEMZ_CC_O }, + { .str = "SYSTEMZ_INSN_FORM_INSTE", .val = SYSTEMZ_INSN_FORM_INSTE }, + { .str = "SYSTEMZ_INSN_FORM_INSTI", .val = SYSTEMZ_INSN_FORM_INSTI }, + { .str = "SYSTEMZ_INSN_FORM_INSTIE", .val = SYSTEMZ_INSN_FORM_INSTIE }, + { .str = "SYSTEMZ_INSN_FORM_INSTMII", .val = SYSTEMZ_INSN_FORM_INSTMII }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIA", .val = SYSTEMZ_INSN_FORM_INSTRIA }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIB", .val = SYSTEMZ_INSN_FORM_INSTRIB }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIC", .val = SYSTEMZ_INSN_FORM_INSTRIC }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIEA", .val = SYSTEMZ_INSN_FORM_INSTRIEA }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIEB", .val = SYSTEMZ_INSN_FORM_INSTRIEB }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIEC", .val = SYSTEMZ_INSN_FORM_INSTRIEC }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIED", .val = SYSTEMZ_INSN_FORM_INSTRIED }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIEE", .val = SYSTEMZ_INSN_FORM_INSTRIEE }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIEF", .val = SYSTEMZ_INSN_FORM_INSTRIEF }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIEG", .val = SYSTEMZ_INSN_FORM_INSTRIEG }, + { .str = "SYSTEMZ_INSN_FORM_INSTRILA", .val = SYSTEMZ_INSN_FORM_INSTRILA }, + { .str = "SYSTEMZ_INSN_FORM_INSTRILB", .val = SYSTEMZ_INSN_FORM_INSTRILB }, + { .str = "SYSTEMZ_INSN_FORM_INSTRILC", .val = SYSTEMZ_INSN_FORM_INSTRILC }, + { .str = "SYSTEMZ_INSN_FORM_INSTRIS", .val = SYSTEMZ_INSN_FORM_INSTRIS }, + { .str = "SYSTEMZ_INSN_FORM_INSTRR", .val = SYSTEMZ_INSN_FORM_INSTRR }, + { .str = "SYSTEMZ_INSN_FORM_INSTRRD", .val = SYSTEMZ_INSN_FORM_INSTRRD }, + { .str = "SYSTEMZ_INSN_FORM_INSTRRE", .val = SYSTEMZ_INSN_FORM_INSTRRE }, + { .str = "SYSTEMZ_INSN_FORM_INSTRRFA", .val = SYSTEMZ_INSN_FORM_INSTRRFA }, + { .str = "SYSTEMZ_INSN_FORM_INSTRRFB", .val = SYSTEMZ_INSN_FORM_INSTRRFB }, + { .str = "SYSTEMZ_INSN_FORM_INSTRRFC", .val = SYSTEMZ_INSN_FORM_INSTRRFC }, + { .str = "SYSTEMZ_INSN_FORM_INSTRRFD", .val = SYSTEMZ_INSN_FORM_INSTRRFD }, + { .str = "SYSTEMZ_INSN_FORM_INSTRRFE", .val = SYSTEMZ_INSN_FORM_INSTRRFE }, + { .str = "SYSTEMZ_INSN_FORM_INSTRRS", .val = SYSTEMZ_INSN_FORM_INSTRRS }, + { .str = "SYSTEMZ_INSN_FORM_INSTRSA", .val = SYSTEMZ_INSN_FORM_INSTRSA }, + { .str = "SYSTEMZ_INSN_FORM_INSTRSB", .val = SYSTEMZ_INSN_FORM_INSTRSB }, + { .str = "SYSTEMZ_INSN_FORM_INSTRSI", .val = SYSTEMZ_INSN_FORM_INSTRSI }, + { .str = "SYSTEMZ_INSN_FORM_INSTRSLA", .val = SYSTEMZ_INSN_FORM_INSTRSLA }, + { .str = "SYSTEMZ_INSN_FORM_INSTRSLB", .val = SYSTEMZ_INSN_FORM_INSTRSLB }, + { .str = "SYSTEMZ_INSN_FORM_INSTRSYA", .val = SYSTEMZ_INSN_FORM_INSTRSYA }, + { .str = "SYSTEMZ_INSN_FORM_INSTRSYB", .val = SYSTEMZ_INSN_FORM_INSTRSYB }, + { .str = "SYSTEMZ_INSN_FORM_INSTRXA", .val = SYSTEMZ_INSN_FORM_INSTRXA }, + { .str = "SYSTEMZ_INSN_FORM_INSTRXB", .val = SYSTEMZ_INSN_FORM_INSTRXB }, + { .str = "SYSTEMZ_INSN_FORM_INSTRXE", .val = SYSTEMZ_INSN_FORM_INSTRXE }, + { .str = "SYSTEMZ_INSN_FORM_INSTRXF", .val = SYSTEMZ_INSN_FORM_INSTRXF }, + { .str = "SYSTEMZ_INSN_FORM_INSTRXYA", .val = SYSTEMZ_INSN_FORM_INSTRXYA }, + { .str = "SYSTEMZ_INSN_FORM_INSTRXYB", .val = SYSTEMZ_INSN_FORM_INSTRXYB }, + { .str = "SYSTEMZ_INSN_FORM_INSTS", .val = SYSTEMZ_INSN_FORM_INSTS }, + { .str = "SYSTEMZ_INSN_FORM_INSTSI", .val = SYSTEMZ_INSN_FORM_INSTSI }, + { .str = "SYSTEMZ_INSN_FORM_INSTSIL", .val = SYSTEMZ_INSN_FORM_INSTSIL }, + { .str = "SYSTEMZ_INSN_FORM_INSTSIY", .val = SYSTEMZ_INSN_FORM_INSTSIY }, + { .str = "SYSTEMZ_INSN_FORM_INSTSMI", .val = SYSTEMZ_INSN_FORM_INSTSMI }, + { .str = "SYSTEMZ_INSN_FORM_INSTSSA", .val = SYSTEMZ_INSN_FORM_INSTSSA }, + { .str = "SYSTEMZ_INSN_FORM_INSTSSB", .val = SYSTEMZ_INSN_FORM_INSTSSB }, + { .str = "SYSTEMZ_INSN_FORM_INSTSSC", .val = SYSTEMZ_INSN_FORM_INSTSSC }, + { .str = "SYSTEMZ_INSN_FORM_INSTSSD", .val = SYSTEMZ_INSN_FORM_INSTSSD }, + { .str = "SYSTEMZ_INSN_FORM_INSTSSE", .val = SYSTEMZ_INSN_FORM_INSTSSE }, + { .str = "SYSTEMZ_INSN_FORM_INSTSSF", .val = SYSTEMZ_INSN_FORM_INSTSSF }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRIA", .val = SYSTEMZ_INSN_FORM_INSTVRIA }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRIB", .val = SYSTEMZ_INSN_FORM_INSTVRIB }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRIC", .val = SYSTEMZ_INSN_FORM_INSTVRIC }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRID", .val = SYSTEMZ_INSN_FORM_INSTVRID }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRIE", .val = SYSTEMZ_INSN_FORM_INSTVRIE }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRIF", .val = SYSTEMZ_INSN_FORM_INSTVRIF }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRIG", .val = SYSTEMZ_INSN_FORM_INSTVRIG }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRIH", .val = SYSTEMZ_INSN_FORM_INSTVRIH }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRII", .val = SYSTEMZ_INSN_FORM_INSTVRII }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRA", .val = SYSTEMZ_INSN_FORM_INSTVRRA }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRB", .val = SYSTEMZ_INSN_FORM_INSTVRRB }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRC", .val = SYSTEMZ_INSN_FORM_INSTVRRC }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRD", .val = SYSTEMZ_INSN_FORM_INSTVRRD }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRE", .val = SYSTEMZ_INSN_FORM_INSTVRRE }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRF", .val = SYSTEMZ_INSN_FORM_INSTVRRF }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRG", .val = SYSTEMZ_INSN_FORM_INSTVRRG }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRH", .val = SYSTEMZ_INSN_FORM_INSTVRRH }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRI", .val = SYSTEMZ_INSN_FORM_INSTVRRI }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRJ", .val = SYSTEMZ_INSN_FORM_INSTVRRJ }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRRK", .val = SYSTEMZ_INSN_FORM_INSTVRRK }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRSA", .val = SYSTEMZ_INSN_FORM_INSTVRSA }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRSB", .val = SYSTEMZ_INSN_FORM_INSTVRSB }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRSC", .val = SYSTEMZ_INSN_FORM_INSTVRSC }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRSD", .val = SYSTEMZ_INSN_FORM_INSTVRSD }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRV", .val = SYSTEMZ_INSN_FORM_INSTVRV }, + { .str = "SYSTEMZ_INSN_FORM_INSTVRX", .val = SYSTEMZ_INSN_FORM_INSTVRX }, + { .str = "SYSTEMZ_INSN_FORM_INSTVSI", .val = SYSTEMZ_INSN_FORM_INSTVSI }, + { .str = "SYSTEMZ_OP_IMM", .val = SYSTEMZ_OP_IMM }, + { .str = "SYSTEMZ_OP_MEM", .val = SYSTEMZ_OP_MEM }, + { .str = "SYSTEMZ_OP_REG", .val = SYSTEMZ_OP_REG }, { .str = "TMS320C64X_FUNIT_D", .val = TMS320C64X_FUNIT_D }, { .str = "TMS320C64X_FUNIT_L", .val = TMS320C64X_FUNIT_L }, { .str = "TMS320C64X_FUNIT_M", .val = TMS320C64X_FUNIT_M }, @@ -1361,6 +1473,8 @@ static const cs_enum_id_map cs_enum_map[] = { { .str = "XCORE_OP_IMM", .val = XCORE_OP_IMM }, { .str = "XCORE_OP_MEM", .val = XCORE_OP_MEM }, { .str = "XCORE_OP_REG", .val = XCORE_OP_REG }, + { .str = "zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzx", + .val = 0xffffff }, // For testing { .str = "zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz", .val = 0xffffff }, // For testing }; diff --git a/suite/cstest/include/test_run.h b/suite/cstest/include/test_run.h index c21700cf26..096fc80758 100644 --- a/suite/cstest/include/test_run.h +++ b/suite/cstest/include/test_run.h @@ -21,6 +21,7 @@ typedef struct { uint32_t failed; ///< Number of failed test cases. uint32_t errors; ///< Number errors (parsing errors etc). uint32_t skipped; ///< Number skipped test cases. + uint32_t decoded_insns; ///< Number of total decoded instructions. } TestRunStats; typedef struct { @@ -39,6 +40,7 @@ typedef struct { size_t arch_bits; ///< Bits of the architecture. TestCase *tcase; ///< The test case to check. csh handle; ///< The Capstone instance for this test. Setup and teared down by the cmocka handlers. + uint32_t decoded_insns; ///< Counts the number of decoded instructions of this test case. } UnitTestState; TestRunResult cstest_run_tests(char **test_file_paths, uint32_t path_count, diff --git a/suite/cstest/src/cstest.c b/suite/cstest/src/cstest.c index 6c25f5db9e..1181db9f38 100644 --- a/suite/cstest/src/cstest.c +++ b/suite/cstest/src/cstest.c @@ -69,6 +69,7 @@ void print_test_run_stats(const TestRunStats *stats) printf("\tSuccessful: %" PRId32 "\n", stats->successful); printf("\tSkipped: %" PRId32 "\n", stats->skipped); printf("\tFailed: %" PRId32 "\n", stats->failed); + printf("\n\tDecoded instructions: %" PRId32 "\n", stats->decoded_insns); printf("-----------------------------------------\n"); printf("\n"); } diff --git a/suite/cstest/src/test_detail.c b/suite/cstest/src/test_detail.c index 0128217ae3..f63c38c904 100644 --- a/suite/cstest/src/test_detail.c +++ b/suite/cstest/src/test_detail.c @@ -356,7 +356,7 @@ bool test_expected_detail(csh *handle, const cs_insn *insn, expected->xcore); } if (expected->systemz) { - return test_expected_systemz(handle, &actual->sysz, + return test_expected_systemz(handle, &actual->systemz, expected->systemz); } if (expected->sparc) { diff --git a/suite/cstest/src/test_detail_systemz.c b/suite/cstest/src/test_detail_systemz.c index a15fbca632..390721d208 100644 --- a/suite/cstest/src/test_detail_systemz.c +++ b/suite/cstest/src/test_detail_systemz.c @@ -17,6 +17,7 @@ void test_detail_systemz_free(TestDetailSystemZ *detail) if (!detail) { return; } + cs_mem_free(detail->format); for (size_t i = 0; i < detail->operands_count; ++i) { test_detail_systemz_op_free(detail->operands[i]); } @@ -28,6 +29,7 @@ TestDetailSystemZ *test_detail_systemz_clone(const TestDetailSystemZ *detail) { TestDetailSystemZ *clone = test_detail_systemz_new(); + clone->format = detail->format ? strdup(detail->format) : NULL; clone->operands_count = detail->operands_count; if (detail->operands_count > 0) { clone->operands = cs_mem_calloc(sizeof(TestDetailSystemZOp *), @@ -51,8 +53,11 @@ TestDetailSystemZOp *test_detail_systemz_op_clone(const TestDetailSystemZOp *op) TestDetailSystemZOp *clone = test_detail_systemz_op_new(); clone->type = op->type ? strdup(op->type) : NULL; + clone->access = op->access ? strdup(op->access) : NULL; clone->reg = op->reg ? strdup(op->reg) : NULL; clone->imm = op->imm; + clone->imm_width = op->imm_width; + clone->mem_am = op->mem_am ? strdup(op->mem_am) : NULL; clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL; clone->mem_index = op->mem_index ? strdup(op->mem_index) : NULL; clone->mem_disp = op->mem_disp; @@ -67,43 +72,74 @@ void test_detail_systemz_op_free(TestDetailSystemZOp *op) return; } cs_mem_free(op->type); + cs_mem_free(op->access); cs_mem_free(op->reg); + cs_mem_free(op->mem_am); cs_mem_free(op->mem_base); cs_mem_free(op->mem_index); cs_mem_free(op); } -bool test_expected_systemz(csh *handle, const cs_sysz *actual, +bool test_expected_systemz(csh *handle, const cs_systemz *actual, const TestDetailSystemZ *expected) { assert(handle && actual && expected); + compare_enum_ret(actual->format, expected->format, false); compare_uint8_ret(actual->op_count, expected->operands_count, false); for (size_t i = 0; i < actual->op_count; ++i) { - const cs_sysz_op *op = &actual->operands[i]; + const cs_systemz_op *op = &actual->operands[i]; TestDetailSystemZOp *eop = expected->operands[i]; compare_enum_ret(op->type, eop->type, false); + compare_enum_ret(op->access, eop->access, false); switch (op->type) { default: fprintf(stderr, "arm op type %" PRId32 " not handled.\n", op->type); return false; - case SYSZ_OP_REG: - case SYSZ_OP_ACREG: + case SYSTEMZ_OP_REG: compare_reg_ret(*handle, op->reg, eop->reg, false); break; - case SYSZ_OP_IMM: + case SYSTEMZ_OP_IMM: compare_int64_ret(op->imm, eop->imm, false); + compare_uint8_ret(op->imm_width, eop->imm_width, false); break; - case SYSZ_OP_MEM: - compare_reg_ret(*handle, op->mem.base, eop->mem_base, + case SYSTEMZ_OP_MEM: + compare_enum_ret(op->mem.am, eop->mem_am, false); + switch(op->mem.am) { + default: + assert(0 && "Address mode not handled\n"); + break; + case SYSTEMZ_AM_BD: + compare_reg_ret(*handle, op->mem.base, eop->mem_base, false); - compare_reg_ret(*handle, op->mem.index, eop->mem_index, + compare_reg_ret(*handle, op->mem.index, eop->mem_index, false); - compare_int64_ret(op->mem.disp, eop->mem_disp, false); - compare_uint64_ret(op->mem.length, eop->mem_length, + break; + case SYSTEMZ_AM_BDX: + case SYSTEMZ_AM_BDV: + compare_reg_ret(*handle, op->mem.base, eop->mem_base, + false); + compare_int64_ret(op->mem.disp, eop->mem_disp, false); + compare_reg_ret(*handle, op->mem.index, eop->mem_index, + false); + break; + case SYSTEMZ_AM_BDL: + compare_reg_ret(*handle, op->mem.base, eop->mem_base, + false); + compare_int64_ret(op->mem.disp, eop->mem_disp, false); + compare_uint64_ret(op->mem.length, eop->mem_length, + false); + break; + case SYSTEMZ_AM_BDR: + compare_reg_ret(*handle, op->mem.base, eop->mem_base, + false); + compare_int64_ret(op->mem.disp, eop->mem_disp, false); + compare_uint64_ret(op->mem.length, eop->mem_length, false); + break; + } break; } } diff --git a/suite/cstest/src/test_run.c b/suite/cstest/src/test_run.c index 06919c6c3a..e385908463 100644 --- a/suite/cstest/src/test_run.c +++ b/suite/cstest/src/test_run.c @@ -128,6 +128,7 @@ static bool parse_input_options(const TestInput *input, cs_arch *arch, } opt_arr[opt_idx++] = test_option_map[k].opt; opt_found = true; + break; } } if (!opt_found) { @@ -245,6 +246,7 @@ static void cstest_unit_test(void **state) tcase->input->address, 0, &insns); test_expected_compare(&ustate->handle, tcase->expected, insns, insns_count, ustate->arch_bits); + ustate->decoded_insns += insns_count; cs_free(insns, insns_count); } @@ -293,10 +295,17 @@ static void eval_test_cases(TestFile **test_files, TestRunStats *stats) utest_table[tci].test_func = cstest_unit_test; } } + assert(tci == stats->tc_total); // Use private function here, because the API takes only constant tables. int failed_tests = _cmocka_run_group_tests( "All test cases", utest_table, stats->tc_total, NULL, NULL); for (size_t i = 0; i < stats->tc_total; ++i) { + UnitTestState *ustate = utest_table[i].initial_state; + if (!ustate) { + // Skipped test case + continue; + } + stats->decoded_insns += ustate->decoded_insns; cs_mem_free((char *)utest_table[i].name); cs_mem_free(utest_table[i].initial_state); } diff --git a/suite/cstest/test/CMakeLists.txt b/suite/cstest/test/CMakeLists.txt index b1c56cf592..adbe573546 100644 --- a/suite/cstest/test/CMakeLists.txt +++ b/suite/cstest/test/CMakeLists.txt @@ -13,11 +13,11 @@ add_executable(unit_test ${CSTEST_TEST_SRC}) add_dependencies(unit_test libcstest) target_link_libraries(unit_test PUBLIC libcstest) -add_test(NAME UnitCSTest +add_test(NAME unit_cstest COMMAND unit_test WORKING_DIRECTORY ${CSTEST_TEST_DIR} ) -add_test(NAME IntegrationCSTest +add_test(NAME integration_cstest COMMAND python3 ${CSTEST_TEST_DIR}/integration_tests.py cstest WORKING_DIRECTORY ${CSTEST_TEST_DIR} ) diff --git a/suite/cstest/test/src/unit_tests.c b/suite/cstest/test/src/unit_tests.c index fcc34e4be1..d8d6386809 100644 --- a/suite/cstest/test/src/unit_tests.c +++ b/suite/cstest/test/src/unit_tests.c @@ -19,6 +19,26 @@ bool test_cs_enum_get_val() val); return false; } + // Get second value + val = enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), + "AAAAAAAAAAAAAAAAAAAAAAAAAB", + &found); + if (!found || val != 0xffffff) { + fprintf(stderr, + "enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), AAAAAAAAAAAAAAAAAAAAAAAAAB) failed is %d.\n", + val); + return false; + } + + // Get second to last value + val = enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), + "zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzx", &found); + if (!found || val != 0xffffff) { + fprintf(stderr, + "enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzx) failed is %d.\n", + val); + return false; + } // Get last value val = enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), diff --git a/suite/fuzz.py b/suite/fuzz.py index f1955ea065..ca87bdf354 100755 --- a/suite/fuzz.py +++ b/suite/fuzz.py @@ -40,7 +40,7 @@ (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC", 0), (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC, print register with number only", CS_OPT_SYNTAX_NOREGNAME), (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, "Sparc", 0), - (CS_ARCH_SYSZ, 0, "SystemZ", 0), + (CS_ARCH_SYSTEMZ, 0, "SystemZ", 0), (CS_ARCH_XCORE, 0, "XCore", 0), (CS_ARCH_M68K, 0, "M68K", 0), (CS_ARCH_RISCV, CS_MODE_RISCV32, "riscv32", 0), diff --git a/suite/fuzz/drivermc.c b/suite/fuzz/drivermc.c index 5b53543d3c..f883482e7b 100644 --- a/suite/fuzz/drivermc.c +++ b/suite/fuzz/drivermc.c @@ -73,7 +73,7 @@ int main(int argc, char** argv) Data[0] = 15; } else if (strcmp(arch, "CS_ARCH_SPARC") == 0 && strcmp(mode, "CS_MODE_BIG_ENDIAN + CS_MODE_V9") == 0) { Data[0] = 16; - } else if (strcmp(arch, "CS_ARCH_SYSZ") == 0 && strcmp(mode, "0") == 0) { + } else if (strcmp(arch, "CS_ARCH_SYSTEMZ") == 0 && strcmp(mode, "0") == 0) { Data[0] = 17; } else if (strcmp(arch, "CS_ARCH_XCORE") == 0 && strcmp(mode, "0") == 0) { Data[0] = 18; diff --git a/suite/fuzz/fuzz_diff.c b/suite/fuzz/fuzz_diff.c index f0f39fdc67..df69df3e6e 100644 --- a/suite/fuzz/fuzz_diff.c +++ b/suite/fuzz/fuzz_diff.c @@ -120,7 +120,7 @@ struct platform platforms[] = { }, { //item 17 - CS_ARCH_SYSZ, + CS_ARCH_SYSTEMZ, (cs_mode)0, "SystemZ" }, diff --git a/suite/fuzz/fuzz_harness.c b/suite/fuzz/fuzz_harness.c index b69d3ba47d..27962914c7 100644 --- a/suite/fuzz/fuzz_harness.c +++ b/suite/fuzz/fuzz_harness.c @@ -98,7 +98,7 @@ int main(int argc, char **argv) "SparcV9" }, { - CS_ARCH_SYSZ, + CS_ARCH_SYSTEMZ, (cs_mode)0, "SystemZ" }, diff --git a/suite/fuzz/platform.c b/suite/fuzz/platform.c index ea5f46723b..ac4d8db941 100644 --- a/suite/fuzz/platform.c +++ b/suite/fuzz/platform.c @@ -122,8 +122,8 @@ struct platform platforms[] = { }, { //item 17 - CS_ARCH_SYSZ, - (cs_mode) 0, + CS_ARCH_SYSTEMZ, + (cs_mode) CS_MODE_BIG_ENDIAN, "SystemZ", "systemz" }, diff --git a/suite/test_corpus3.py b/suite/test_corpus3.py index 0b9f214286..3e634eb6e9 100755 --- a/suite/test_corpus3.py +++ b/suite/test_corpus3.py @@ -38,7 +38,7 @@ def test_file(fname): "CS_ARCH_MIPS": CS_ARCH_MIPS, "CS_ARCH_PPC": CS_ARCH_PPC, "CS_ARCH_SPARC": CS_ARCH_SPARC, - "CS_ARCH_SYSZ": CS_ARCH_SYSZ, + "CS_ARCH_SYSTEMZ": CS_ARCH_SYSTEMZ, "CS_ARCH_X86": CS_ARCH_X86, "CS_ARCH_XCORE": CS_ARCH_XCORE, "CS_ARCH_RISCV": CS_ARCH_RISCV, @@ -107,7 +107,7 @@ def test_file(fname): ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN"): 15, ("CS_ARCH_SPARC", "CS_MODE_BIG_ENDIAN"): 16, ("CS_ARCH_SPARC", "CS_MODE_BIG_ENDIAN+CS_MODE_V9"): 17, - ("CS_ARCH_SYSZ", "0"): 18, + ("CS_ARCH_SYSTEMZ", "CS_MODE_BIG_ENDIAN"): 18, ("CS_ARCH_XCORE", "0"): 19, ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_BIG_ENDIAN"): 20, ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): 21, diff --git a/tests/MC/SystemZ/insn-good-z196.s.yaml b/tests/MC/SystemZ/insn-good-z196.s.yaml deleted file mode 100644 index 036a7344af..0000000000 --- a/tests/MC/SystemZ/insn-good-z196.s.yaml +++ /dev/null @@ -1,5149 +0,0 @@ -test_cases: - - - input: - bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xd9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aghik %r0, %r0, -32768" - - - input: - bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xd9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aghik %r0, %r0, -1" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xd9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aghik %r0, %r0, 0" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x01, 0x00, 0xd9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aghik %r0, %r0, 1" - - - input: - bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xd9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aghik %r0, %r0, 32767" - - - input: - bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xd9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aghik %r0, %r15, 0" - - - input: - bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xd9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aghik %r15, %r0, 0" - - - input: - bytes: [ 0xec, 0x78, 0xff, 0xf0, 0x00, 0xd9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aghik %r7, %r8, -16" - - - input: - bytes: [ 0xb9, 0xe8, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agrk %r0, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xe8, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agrk %r0, %r0, %r15" - - - input: - bytes: [ 0xb9, 0xe8, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agrk %r0, %r15, %r0" - - - input: - bytes: [ 0xb9, 0xe8, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agrk %r15, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xe8, 0x90, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agrk %r7, %r8, %r9" - - - input: - bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xd8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahik %r0, %r0, -32768" - - - input: - bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xd8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahik %r0, %r0, -1" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xd8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahik %r0, %r0, 0" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x01, 0x00, 0xd8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahik %r0, %r0, 1" - - - input: - bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xd8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahik %r0, %r0, 32767" - - - input: - bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xd8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahik %r0, %r15, 0" - - - input: - bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xd8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahik %r15, %r0, 0" - - - input: - bytes: [ 0xec, 0x78, 0xff, 0xf0, 0x00, 0xd8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahik %r7, %r8, -16" - - - input: - bytes: [ 0xcc, 0x08, 0x80, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aih %r0, -2147483648" - - - input: - bytes: [ 0xcc, 0x08, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aih %r0, -1" - - - input: - bytes: [ 0xcc, 0x08, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aih %r0, 0" - - - input: - bytes: [ 0xcc, 0x08, 0x00, 0x00, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aih %r0, 1" - - - input: - bytes: [ 0xcc, 0x08, 0x7f, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aih %r0, 2147483647" - - - input: - bytes: [ 0xcc, 0xf8, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aih %r15, 0" - - - input: - bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xdb ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alghsik %r0, %r0, -32768" - - - input: - bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xdb ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alghsik %r0, %r0, -1" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xdb ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alghsik %r0, %r0, 0" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x01, 0x00, 0xdb ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alghsik %r0, %r0, 1" - - - input: - bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xdb ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alghsik %r0, %r0, 32767" - - - input: - bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xdb ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alghsik %r0, %r15, 0" - - - input: - bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xdb ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alghsik %r15, %r0, 0" - - - input: - bytes: [ 0xec, 0x78, 0xff, 0xf0, 0x00, 0xdb ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alghsik %r7, %r8, -16" - - - input: - bytes: [ 0xb9, 0xea, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algrk %r0, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xea, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algrk %r0, %r0, %r15" - - - input: - bytes: [ 0xb9, 0xea, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algrk %r0, %r15, %r0" - - - input: - bytes: [ 0xb9, 0xea, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algrk %r15, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xea, 0x90, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algrk %r7, %r8, %r9" - - - input: - bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xda ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alhsik %r0, %r0, -32768" - - - input: - bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xda ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alhsik %r0, %r0, -1" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xda ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alhsik %r0, %r0, 0" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x01, 0x00, 0xda ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alhsik %r0, %r0, 1" - - - input: - bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xda ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alhsik %r0, %r0, 32767" - - - input: - bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xda ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alhsik %r0, %r15, 0" - - - input: - bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xda ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alhsik %r15, %r0, 0" - - - input: - bytes: [ 0xec, 0x78, 0xff, 0xf0, 0x00, 0xda ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alhsik %r7, %r8, -16" - - - input: - bytes: [ 0xb9, 0xfa, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alrk %r0, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xfa, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alrk %r0, %r0, %r15" - - - input: - bytes: [ 0xb9, 0xfa, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alrk %r0, %r15, %r0" - - - input: - bytes: [ 0xb9, 0xfa, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alrk %r15, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xfa, 0x90, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alrk %r7, %r8, %r9" - - - input: - bytes: [ 0xb9, 0xf8, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ark %r0, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xf8, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ark %r0, %r0, %r15" - - - input: - bytes: [ 0xb9, 0xf8, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ark %r0, %r15, %r0" - - - input: - bytes: [ 0xb9, 0xf8, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ark %r15, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xf8, 0x90, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ark %r7, %r8, %r9" - - - input: - bytes: [ 0xb3, 0x91, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdlfbr %f0, 0, %r0, 0" - - - input: - bytes: [ 0xb3, 0x91, 0x0f, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdlfbr %f0, 0, %r0, 15" - - - input: - bytes: [ 0xb3, 0x91, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdlfbr %f0, 0, %r15, 0" - - - input: - bytes: [ 0xb3, 0x91, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdlfbr %f0, 15, %r0, 0" - - - input: - bytes: [ 0xb3, 0x91, 0x57, 0x46 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdlfbr %f4, 5, %r6, 7" - - - input: - bytes: [ 0xb3, 0x91, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdlfbr %f15, 0, %r0, 0" - - - input: - bytes: [ 0xb3, 0xa1, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdlgbr %f0, 0, %r0, 0" - - - input: - bytes: [ 0xb3, 0xa1, 0x0f, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdlgbr %f0, 0, %r0, 15" - - - input: - bytes: [ 0xb3, 0xa1, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdlgbr %f0, 0, %r15, 0" - - - input: - bytes: [ 0xb3, 0xa1, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdlgbr %f0, 15, %r0, 0" - - - input: - bytes: [ 0xb3, 0xa1, 0x57, 0x46 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdlgbr %f4, 5, %r6, 7" - - - input: - bytes: [ 0xb3, 0xa1, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdlgbr %f15, 0, %r0, 0" - - - input: - bytes: [ 0xb3, 0x90, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "celfbr %f0, 0, %r0, 0" - - - input: - bytes: [ 0xb3, 0x90, 0x0f, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "celfbr %f0, 0, %r0, 15" - - - input: - bytes: [ 0xb3, 0x90, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "celfbr %f0, 0, %r15, 0" - - - input: - bytes: [ 0xb3, 0x90, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "celfbr %f0, 15, %r0, 0" - - - input: - bytes: [ 0xb3, 0x90, 0x57, 0x46 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "celfbr %f4, 5, %r6, 7" - - - input: - bytes: [ 0xb3, 0x90, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "celfbr %f15, 0, %r0, 0" - - - input: - bytes: [ 0xb3, 0xa0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "celgbr %f0, 0, %r0, 0" - - - input: - bytes: [ 0xb3, 0xa0, 0x0f, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "celgbr %f0, 0, %r0, 15" - - - input: - bytes: [ 0xb3, 0xa0, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "celgbr %f0, 0, %r15, 0" - - - input: - bytes: [ 0xb3, 0xa0, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "celgbr %f0, 15, %r0, 0" - - - input: - bytes: [ 0xb3, 0xa0, 0x57, 0x46 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "celgbr %f4, 5, %r6, 7" - - - input: - bytes: [ 0xb3, 0xa0, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "celgbr %f15, 0, %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xcd ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chf %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xcd ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chf %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xcd ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chf %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xcd ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chf %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xcd ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chf %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xcd ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chf %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xcd ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chf %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xcd ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chf %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xcd ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chf %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xcd ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chf %r15, 0" - - - input: - bytes: [ 0xcc, 0x0d, 0x80, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cih %r0, -2147483648" - - - input: - bytes: [ 0xcc, 0x0d, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cih %r0, -1" - - - input: - bytes: [ 0xcc, 0x0d, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cih %r0, 0" - - - input: - bytes: [ 0xcc, 0x0d, 0x00, 0x00, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cih %r0, 1" - - - input: - bytes: [ 0xcc, 0x0d, 0x7f, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cih %r0, 2147483647" - - - input: - bytes: [ 0xcc, 0xfd, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cih %r15, 0" - - - input: - bytes: [ 0xb3, 0x9d, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfdbr %r0, 0, %f0, 0" - - - input: - bytes: [ 0xb3, 0x9d, 0x0f, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfdbr %r0, 0, %f0, 15" - - - input: - bytes: [ 0xb3, 0x9d, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfdbr %r0, 0, %f15, 0" - - - input: - bytes: [ 0xb3, 0x9d, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfdbr %r0, 15, %f0, 0" - - - input: - bytes: [ 0xb3, 0x9d, 0x57, 0x46 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfdbr %r4, 5, %f6, 7" - - - input: - bytes: [ 0xb3, 0x9d, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfdbr %r15, 0, %f0, 0" - - - input: - bytes: [ 0xb3, 0x9c, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfebr %r0, 0, %f0, 0" - - - input: - bytes: [ 0xb3, 0x9c, 0x0f, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfebr %r0, 0, %f0, 15" - - - input: - bytes: [ 0xb3, 0x9c, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfebr %r0, 0, %f15, 0" - - - input: - bytes: [ 0xb3, 0x9c, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfebr %r0, 15, %f0, 0" - - - input: - bytes: [ 0xb3, 0x9c, 0x57, 0x46 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfebr %r4, 5, %f6, 7" - - - input: - bytes: [ 0xb3, 0x9c, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfebr %r15, 0, %f0, 0" - - - input: - bytes: [ 0xb3, 0x9e, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfxbr %r0, 0, %f0, 0" - - - input: - bytes: [ 0xb3, 0x9e, 0x0f, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfxbr %r0, 0, %f0, 15" - - - input: - bytes: [ 0xb3, 0x9e, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfxbr %r0, 0, %f13, 0" - - - input: - bytes: [ 0xb3, 0x9e, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfxbr %r0, 15, %f0, 0" - - - input: - bytes: [ 0xb3, 0x9e, 0x59, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfxbr %r7, 5, %f8, 9" - - - input: - bytes: [ 0xb3, 0x9e, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfxbr %r15, 0, %f0, 0" - - - input: - bytes: [ 0xb3, 0xad, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgdbr %r0, 0, %f0, 0" - - - input: - bytes: [ 0xb3, 0xad, 0x0f, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgdbr %r0, 0, %f0, 15" - - - input: - bytes: [ 0xb3, 0xad, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgdbr %r0, 0, %f15, 0" - - - input: - bytes: [ 0xb3, 0xad, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgdbr %r0, 15, %f0, 0" - - - input: - bytes: [ 0xb3, 0xad, 0x57, 0x46 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgdbr %r4, 5, %f6, 7" - - - input: - bytes: [ 0xb3, 0xad, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgdbr %r15, 0, %f0, 0" - - - input: - bytes: [ 0xb3, 0xac, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgebr %r0, 0, %f0, 0" - - - input: - bytes: [ 0xb3, 0xac, 0x0f, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgebr %r0, 0, %f0, 15" - - - input: - bytes: [ 0xb3, 0xac, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgebr %r0, 0, %f15, 0" - - - input: - bytes: [ 0xb3, 0xac, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgebr %r0, 15, %f0, 0" - - - input: - bytes: [ 0xb3, 0xac, 0x57, 0x46 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgebr %r4, 5, %f6, 7" - - - input: - bytes: [ 0xb3, 0xac, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgebr %r15, 0, %f0, 0" - - - input: - bytes: [ 0xb3, 0xae, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgxbr %r0, 0, %f0, 0" - - - input: - bytes: [ 0xb3, 0xae, 0x0f, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgxbr %r0, 0, %f0, 15" - - - input: - bytes: [ 0xb3, 0xae, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgxbr %r0, 0, %f13, 0" - - - input: - bytes: [ 0xb3, 0xae, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgxbr %r0, 15, %f0, 0" - - - input: - bytes: [ 0xb3, 0xae, 0x59, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgxbr %r7, 5, %f8, 9" - - - input: - bytes: [ 0xb3, 0xae, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgxbr %r15, 0, %f0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xcf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clhf %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xcf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clhf %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xcf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clhf %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xcf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clhf %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xcf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clhf %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xcf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clhf %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xcf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clhf %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xcf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clhf %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xcf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clhf %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xcf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clhf %r15, 0" - - - input: - bytes: [ 0xcc, 0x0f, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clih %r0, 0" - - - input: - bytes: [ 0xcc, 0x0f, 0x00, 0x00, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clih %r0, 1" - - - input: - bytes: [ 0xcc, 0x0f, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clih %r0, 4294967295" - - - input: - bytes: [ 0xcc, 0xff, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clih %r15, 0" - - - input: - bytes: [ 0xb3, 0x92, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxlfbr %f0, 0, %r0, 0" - - - input: - bytes: [ 0xb3, 0x92, 0x0f, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxlfbr %f0, 0, %r0, 15" - - - input: - bytes: [ 0xb3, 0x92, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxlfbr %f0, 0, %r15, 0" - - - input: - bytes: [ 0xb3, 0x92, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxlfbr %f0, 15, %r0, 0" - - - input: - bytes: [ 0xb3, 0x92, 0x5a, 0x49 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxlfbr %f4, 5, %r9, 10" - - - input: - bytes: [ 0xb3, 0x92, 0x00, 0xd0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxlfbr %f13, 0, %r0, 0" - - - input: - bytes: [ 0xb3, 0xa2, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxlgbr %f0, 0, %r0, 0" - - - input: - bytes: [ 0xb3, 0xa2, 0x0f, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxlgbr %f0, 0, %r0, 15" - - - input: - bytes: [ 0xb3, 0xa2, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxlgbr %f0, 0, %r15, 0" - - - input: - bytes: [ 0xb3, 0xa2, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxlgbr %f0, 15, %r0, 0" - - - input: - bytes: [ 0xb3, 0xa2, 0x5a, 0x49 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxlgbr %f4, 5, %r9, 10" - - - input: - bytes: [ 0xb3, 0xa2, 0x00, 0xd0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxlgbr %f13, 0, %r0, 0" - - - input: - bytes: [ 0xb3, 0x5f, 0x0f, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fidbra %f0, 0, %f0, 15" - - - input: - bytes: [ 0xb3, 0x5f, 0x57, 0x46 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fidbra %f4, 5, %f6, 7" - - - input: - bytes: [ 0xb3, 0x57, 0x0f, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fiebra %f0, 0, %f0, 15" - - - input: - bytes: [ 0xb3, 0x57, 0x57, 0x46 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fiebra %f4, 5, %f6, 7" - - - input: - bytes: [ 0xb3, 0x47, 0x0f, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fixbra %f0, 0, %f0, 15" - - - input: - bytes: [ 0xb3, 0x47, 0x59, 0x48 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fixbra %f4, 5, %f8, 9" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laa %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xf8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laa %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laa %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xf8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laa %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laa %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laa %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laa %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xf8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laa %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xf8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laa %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laa %r0, %r15, 0" - - - input: - bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laa %r15, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laag %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xe8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laag %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laag %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xe8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laag %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laag %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laag %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laag %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xe8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laag %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xe8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laag %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laag %r0, %r15, 0" - - - input: - bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe8 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laag %r15, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xfa ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laal %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xfa ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laal %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xfa ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laal %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xfa ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laal %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xfa ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laal %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xfa ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laal %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xfa ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laal %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xfa ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laal %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xfa ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laal %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xfa ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laal %r0, %r15, 0" - - - input: - bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xfa ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laal %r15, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xea ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laalg %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xea ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laalg %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xea ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laalg %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xea ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laalg %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xea ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laalg %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xea ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laalg %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xea ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laalg %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xea ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laalg %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xea ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laalg %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xea ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laalg %r0, %r15, 0" - - - input: - bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xea ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laalg %r15, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lan %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xf4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lan %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lan %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xf4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lan %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lan %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lan %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lan %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xf4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lan %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xf4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lan %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lan %r0, %r15, 0" - - - input: - bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lan %r15, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lang %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xe4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lang %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lang %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xe4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lang %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lang %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lang %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lang %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xe4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lang %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xe4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lang %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lang %r0, %r15, 0" - - - input: - bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lang %r15, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lao %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xf6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lao %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lao %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xf6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lao %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lao %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lao %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lao %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xf6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lao %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xf6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lao %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lao %r0, %r15, 0" - - - input: - bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lao %r15, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laog %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xe6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laog %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laog %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xe6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laog %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laog %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laog %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laog %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xe6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laog %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xe6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laog %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laog %r0, %r15, 0" - - - input: - bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laog %r15, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lax %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xf7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lax %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lax %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xf7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lax %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lax %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lax %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lax %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xf7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lax %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xf7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lax %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lax %r0, %r15, 0" - - - input: - bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lax %r15, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laxg %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xe7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laxg %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laxg %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xe7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laxg %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laxg %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laxg %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laxg %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xe7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laxg %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xe7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laxg %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laxg %r0, %r15, 0" - - - input: - bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "laxg %r15, %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lbh %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lbh %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lbh %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lbh %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lbh %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lbh %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lbh %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lbh %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lbh %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lbh %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xca ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lfh %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xca ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lfh %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xca ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lfh %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xca ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lfh %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xca ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lfh %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xca ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lfh %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xca ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lfh %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xca ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lfh %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xca ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lfh %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xca ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lfh %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhh %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhh %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhh %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhh %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhh %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhh %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhh %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhh %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhh %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc4 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhh %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llch %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llch %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llch %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llch %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llch %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llch %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llch %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llch %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llch %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llch %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llhh %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llhh %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llhh %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llhh %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llhh %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llhh %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llhh %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llhh %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llhh %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc6 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llhh %r15, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "loc %r0, 0, 0" - - - input: - bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "loc %r0, 0, 15" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "loc %r0, -524288, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "loc %r0, 524287, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "loc %r0, 0(%r1), 0" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "loc %r0, 0(%r15), 0" - - - input: - bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "loc %r15, 0, 0" - - - input: - bytes: [ 0xeb, 0x11, 0x30, 0x02, 0x00, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "loco %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x12, 0x30, 0x02, 0x00, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "loch %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x13, 0x30, 0x02, 0x00, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locnle %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x14, 0x30, 0x02, 0x00, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locl %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x15, 0x30, 0x02, 0x00, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locnhe %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x16, 0x30, 0x02, 0x00, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "loclh %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x17, 0x30, 0x02, 0x00, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locne %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x18, 0x30, 0x02, 0x00, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "loce %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x19, 0x30, 0x02, 0x00, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locnlh %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1a, 0x30, 0x02, 0x00, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "loche %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1b, 0x30, 0x02, 0x00, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locnl %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1c, 0x30, 0x02, 0x00, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locle %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1d, 0x30, 0x02, 0x00, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locnh %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1e, 0x30, 0x02, 0x00, 0xf2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locno %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locg %r0, 0, 0" - - - input: - bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locg %r0, 0, 15" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locg %r0, -524288, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locg %r0, 524287, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locg %r0, 0(%r1), 0" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locg %r0, 0(%r15), 0" - - - input: - bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locg %r15, 0, 0" - - - input: - bytes: [ 0xeb, 0x11, 0x30, 0x02, 0x00, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgo %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x12, 0x30, 0x02, 0x00, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgh %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x13, 0x30, 0x02, 0x00, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgnle %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x14, 0x30, 0x02, 0x00, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgl %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x15, 0x30, 0x02, 0x00, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgnhe %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x16, 0x30, 0x02, 0x00, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locglh %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x17, 0x30, 0x02, 0x00, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgne %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x18, 0x30, 0x02, 0x00, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locge %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x19, 0x30, 0x02, 0x00, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgnlh %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1a, 0x30, 0x02, 0x00, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locghe %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1b, 0x30, 0x02, 0x00, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgnl %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1c, 0x30, 0x02, 0x00, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgle %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1d, 0x30, 0x02, 0x00, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgnh %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1e, 0x30, 0x02, 0x00, 0xe2 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgno %r1, 2(%r3)" - - - input: - bytes: [ 0xb9, 0xe2, 0x00, 0x12 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgr %r1, %r2, 0" - - - input: - bytes: [ 0xb9, 0xe2, 0xf0, 0x12 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgr %r1, %r2, 15" - - - input: - bytes: [ 0xb9, 0xe2, 0x10, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgro %r1, %r3" - - - input: - bytes: [ 0xb9, 0xe2, 0x20, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgrh %r1, %r3" - - - input: - bytes: [ 0xb9, 0xe2, 0x30, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgrnle %r1, %r3" - - - input: - bytes: [ 0xb9, 0xe2, 0x40, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgrl %r1, %r3" - - - input: - bytes: [ 0xb9, 0xe2, 0x50, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgrnhe %r1, %r3" - - - input: - bytes: [ 0xb9, 0xe2, 0x60, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgrlh %r1, %r3" - - - input: - bytes: [ 0xb9, 0xe2, 0x70, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgrne %r1, %r3" - - - input: - bytes: [ 0xb9, 0xe2, 0x80, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgre %r1, %r3" - - - input: - bytes: [ 0xb9, 0xe2, 0x90, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgrnlh %r1, %r3" - - - input: - bytes: [ 0xb9, 0xe2, 0xa0, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgrhe %r1, %r3" - - - input: - bytes: [ 0xb9, 0xe2, 0xb0, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgrnl %r1, %r3" - - - input: - bytes: [ 0xb9, 0xe2, 0xc0, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgrle %r1, %r3" - - - input: - bytes: [ 0xb9, 0xe2, 0xd0, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgrnh %r1, %r3" - - - input: - bytes: [ 0xb9, 0xe2, 0xe0, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locgrno %r1, %r3" - - - input: - bytes: [ 0xb9, 0xf2, 0x00, 0x12 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locr %r1, %r2, 0" - - - input: - bytes: [ 0xb9, 0xf2, 0xf0, 0x12 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locr %r1, %r2, 15" - - - input: - bytes: [ 0xb9, 0xf2, 0x10, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locro %r1, %r3" - - - input: - bytes: [ 0xb9, 0xf2, 0x20, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locrh %r1, %r3" - - - input: - bytes: [ 0xb9, 0xf2, 0x30, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locrnle %r1, %r3" - - - input: - bytes: [ 0xb9, 0xf2, 0x40, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locrl %r1, %r3" - - - input: - bytes: [ 0xb9, 0xf2, 0x50, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locrnhe %r1, %r3" - - - input: - bytes: [ 0xb9, 0xf2, 0x60, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locrlh %r1, %r3" - - - input: - bytes: [ 0xb9, 0xf2, 0x70, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locrne %r1, %r3" - - - input: - bytes: [ 0xb9, 0xf2, 0x80, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locre %r1, %r3" - - - input: - bytes: [ 0xb9, 0xf2, 0x90, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locrnlh %r1, %r3" - - - input: - bytes: [ 0xb9, 0xf2, 0xa0, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locrhe %r1, %r3" - - - input: - bytes: [ 0xb9, 0xf2, 0xb0, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locrnl %r1, %r3" - - - input: - bytes: [ 0xb9, 0xf2, 0xc0, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locrle %r1, %r3" - - - input: - bytes: [ 0xb9, 0xf2, 0xd0, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locrnh %r1, %r3" - - - input: - bytes: [ 0xb9, 0xf2, 0xe0, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "locrno %r1, %r3" - - - input: - bytes: [ 0xb9, 0xe4, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ngrk %r0, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xe4, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ngrk %r0, %r0, %r15" - - - input: - bytes: [ 0xb9, 0xe4, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ngrk %r0, %r15, %r0" - - - input: - bytes: [ 0xb9, 0xe4, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ngrk %r15, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xe4, 0x90, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ngrk %r7, %r8, %r9" - - - input: - bytes: [ 0xb9, 0xf4, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nrk %r0, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xf4, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nrk %r0, %r0, %r15" - - - input: - bytes: [ 0xb9, 0xf4, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nrk %r0, %r15, %r0" - - - input: - bytes: [ 0xb9, 0xf4, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nrk %r15, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xf4, 0x90, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nrk %r7, %r8, %r9" - - - input: - bytes: [ 0xb9, 0xe6, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ogrk %r0, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xe6, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ogrk %r0, %r0, %r15" - - - input: - bytes: [ 0xb9, 0xe6, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ogrk %r0, %r15, %r0" - - - input: - bytes: [ 0xb9, 0xe6, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ogrk %r15, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xe6, 0x90, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ogrk %r7, %r8, %r9" - - - input: - bytes: [ 0xb9, 0xf6, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ork %r0, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xf6, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ork %r0, %r0, %r15" - - - input: - bytes: [ 0xb9, 0xf6, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ork %r0, %r15, %r0" - - - input: - bytes: [ 0xb9, 0xf6, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ork %r15, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xf6, 0x90, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ork %r7, %r8, %r9" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x5d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risbhg %r0, %r0, 0, 0, 0" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x5d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risbhg %r0, %r0, 0, 0, 63" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x5d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risbhg %r0, %r0, 0, 255, 0" - - - input: - bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x5d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risbhg %r0, %r0, 255, 0, 0" - - - input: - bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x5d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risbhg %r0, %r15, 0, 0, 0" - - - input: - bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x5d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risbhg %r15, %r0, 0, 0, 0" - - - input: - bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x5d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risbhg %r4, %r5, 6, 7, 8" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risblg %r0, %r0, 0, 0, 0" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risblg %r0, %r0, 0, 0, 63" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risblg %r0, %r0, 0, 255, 0" - - - input: - bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risblg %r0, %r0, 255, 0, 0" - - - input: - bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risblg %r0, %r15, 0, 0, 0" - - - input: - bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risblg %r15, %r0, 0, 0, 0" - - - input: - bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risblg %r4, %r5, 6, 7, 8" - - - input: - bytes: [ 0xb9, 0xe9, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgrk %r0, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xe9, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgrk %r0, %r0, %r15" - - - input: - bytes: [ 0xb9, 0xe9, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgrk %r0, %r15, %r0" - - - input: - bytes: [ 0xb9, 0xe9, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgrk %r15, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xe9, 0x90, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgrk %r7, %r8, %r9" - - - input: - bytes: [ 0xb9, 0xeb, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgrk %r0, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xeb, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgrk %r0, %r0, %r15" - - - input: - bytes: [ 0xb9, 0xeb, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgrk %r0, %r15, %r0" - - - input: - bytes: [ 0xb9, 0xeb, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgrk %r15, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xeb, 0x90, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgrk %r7, %r8, %r9" - - - input: - bytes: [ 0xb9, 0xfb, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slrk %r0, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xfb, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slrk %r0, %r0, %r15" - - - input: - bytes: [ 0xb9, 0xfb, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slrk %r0, %r15, %r0" - - - input: - bytes: [ 0xb9, 0xfb, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slrk %r15, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xfb, 0x90, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slrk %r7, %r8, %r9" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xdf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllk %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0xdf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllk %r15, %r1, 0" - - - input: - bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0xdf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllk %r1, %r15, 0" - - - input: - bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0xdf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllk %r15, %r15, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xdf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllk %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xdf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllk %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xdf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllk %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xdf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllk %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xdf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllk %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xdf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllk %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xdf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllk %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xdf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllk %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xdc ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srak %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0xdc ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srak %r15, %r1, 0" - - - input: - bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0xdc ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srak %r1, %r15, 0" - - - input: - bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0xdc ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srak %r15, %r15, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xdc ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srak %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xdc ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srak %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xdc ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srak %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xdc ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srak %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xdc ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srak %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xdc ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srak %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xdc ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srak %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xdc ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srak %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0xb9, 0xf9, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srk %r0, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xf9, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srk %r0, %r0, %r15" - - - input: - bytes: [ 0xb9, 0xf9, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srk %r0, %r15, %r0" - - - input: - bytes: [ 0xb9, 0xf9, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srk %r15, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xf9, 0x90, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srk %r7, %r8, %r9" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xde ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlk %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0xde ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlk %r15, %r1, 0" - - - input: - bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0xde ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlk %r1, %r15, 0" - - - input: - bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0xde ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlk %r15, %r15, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xde ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlk %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xde ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlk %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xde ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlk %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xde ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlk %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xde ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlk %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xde ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlk %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xde ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlk %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xde ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlk %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stch %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stch %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stch %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stch %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stch %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stch %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stch %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stch %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stch %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stch %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthh %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthh %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthh %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthh %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthh %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthh %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthh %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthh %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthh %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc7 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthh %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xcb ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stfh %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xcb ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stfh %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xcb ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stfh %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xcb ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stfh %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xcb ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stfh %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xcb ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stfh %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xcb ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stfh %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xcb ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stfh %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xcb ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stfh %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xcb ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stfh %r15, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stoc %r0, 0, 0" - - - input: - bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stoc %r0, 0, 15" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stoc %r0, -524288, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stoc %r0, 524287, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stoc %r0, 0(%r1), 0" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stoc %r0, 0(%r15), 0" - - - input: - bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stoc %r15, 0, 0" - - - input: - bytes: [ 0xeb, 0x11, 0x30, 0x02, 0x00, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stoco %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x12, 0x30, 0x02, 0x00, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stoch %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x13, 0x30, 0x02, 0x00, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocnle %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x14, 0x30, 0x02, 0x00, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocl %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x15, 0x30, 0x02, 0x00, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocnhe %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x16, 0x30, 0x02, 0x00, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stoclh %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x17, 0x30, 0x02, 0x00, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocne %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x18, 0x30, 0x02, 0x00, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stoce %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x19, 0x30, 0x02, 0x00, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocnlh %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1a, 0x30, 0x02, 0x00, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stoche %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1b, 0x30, 0x02, 0x00, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocnl %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1c, 0x30, 0x02, 0x00, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocle %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1d, 0x30, 0x02, 0x00, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocnh %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1e, 0x30, 0x02, 0x00, 0xf3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocno %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocg %r0, 0, 0" - - - input: - bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocg %r0, 0, 15" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocg %r0, -524288, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocg %r0, 524287, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocg %r0, 0(%r1), 0" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocg %r0, 0(%r15), 0" - - - input: - bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocg %r15, 0, 0" - - - input: - bytes: [ 0xeb, 0x11, 0x30, 0x02, 0x00, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocgo %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x12, 0x30, 0x02, 0x00, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocgh %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x13, 0x30, 0x02, 0x00, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocgnle %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x14, 0x30, 0x02, 0x00, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocgl %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x15, 0x30, 0x02, 0x00, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocgnhe %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x16, 0x30, 0x02, 0x00, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocglh %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x17, 0x30, 0x02, 0x00, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocgne %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x18, 0x30, 0x02, 0x00, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocge %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x19, 0x30, 0x02, 0x00, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocgnlh %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1a, 0x30, 0x02, 0x00, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocghe %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1b, 0x30, 0x02, 0x00, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocgnl %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1c, 0x30, 0x02, 0x00, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocgle %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1d, 0x30, 0x02, 0x00, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocgnh %r1, 2(%r3)" - - - input: - bytes: [ 0xeb, 0x1e, 0x30, 0x02, 0x00, 0xe3 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stocgno %r1, 2(%r3)" - - - input: - bytes: [ 0xb9, 0xe7, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xgrk %r0, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xe7, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xgrk %r0, %r0, %r15" - - - input: - bytes: [ 0xb9, 0xe7, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xgrk %r0, %r15, %r0" - - - input: - bytes: [ 0xb9, 0xe7, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xgrk %r15, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xe7, 0x90, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xgrk %r7, %r8, %r9" - - - input: - bytes: [ 0xb9, 0xf7, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xrk %r0, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xf7, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xrk %r0, %r0, %r15" - - - input: - bytes: [ 0xb9, 0xf7, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xrk %r0, %r15, %r0" - - - input: - bytes: [ 0xb9, 0xf7, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xrk %r15, %r0, %r0" - - - input: - bytes: [ 0xb9, 0xf7, 0x90, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xrk %r7, %r8, %r9" diff --git a/tests/MC/SystemZ/insn-good.s.yaml b/tests/MC/SystemZ/insn-good.s.yaml deleted file mode 100644 index 8afc270aca..0000000000 --- a/tests/MC/SystemZ/insn-good.s.yaml +++ /dev/null @@ -1,20242 +0,0 @@ -test_cases: - - - input: - bytes: [ 0x5a, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "a %r0, 0" - - - input: - bytes: [ 0x5a, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "a %r0, 4095" - - - input: - bytes: [ 0x5a, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "a %r0, 0(%r1)" - - - input: - bytes: [ 0x5a, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "a %r0, 0(%r15)" - - - input: - bytes: [ 0x5a, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "a %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x5a, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "a %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x5a, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "a %r15, 0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "adb %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "adb %f0, 4095" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "adb %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "adb %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "adb %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "adb %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "adb %f15, 0" - - - input: - bytes: [ 0xb3, 0x1a, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "adbr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x1a, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "adbr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x1a, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "adbr %f7, %f8" - - - input: - bytes: [ 0xb3, 0x1a, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "adbr %f15, %f0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aeb %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aeb %f0, 4095" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aeb %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aeb %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aeb %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aeb %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aeb %f15, 0" - - - input: - bytes: [ 0xb3, 0x0a, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aebr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x0a, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aebr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x0a, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aebr %f7, %f8" - - - input: - bytes: [ 0xb3, 0x0a, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aebr %f15, %f0" - - - input: - bytes: [ 0xc2, 0x09, 0x80, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "afi %r0, -2147483648" - - - input: - bytes: [ 0xc2, 0x09, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "afi %r0, -1" - - - input: - bytes: [ 0xc2, 0x09, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "afi %r0, 0" - - - input: - bytes: [ 0xc2, 0x09, 0x00, 0x00, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "afi %r0, 1" - - - input: - bytes: [ 0xc2, 0x09, 0x7f, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "afi %r0, 2147483647" - - - input: - bytes: [ 0xc2, 0xf9, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "afi %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x08 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ag %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x08 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ag %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x08 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ag %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x08 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ag %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x08 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ag %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x08 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ag %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x08 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ag %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x08 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ag %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x08 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ag %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x08 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ag %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x18 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agf %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x18 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agf %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x18 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agf %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x18 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agf %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x18 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agf %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x18 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agf %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x18 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agf %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x18 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agf %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x18 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agf %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x18 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agf %r15, 0" - - - input: - bytes: [ 0xc2, 0x08, 0x80, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agfi %r0, -2147483648" - - - input: - bytes: [ 0xc2, 0x08, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agfi %r0, -1" - - - input: - bytes: [ 0xc2, 0x08, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agfi %r0, 0" - - - input: - bytes: [ 0xc2, 0x08, 0x00, 0x00, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agfi %r0, 1" - - - input: - bytes: [ 0xc2, 0x08, 0x7f, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agfi %r0, 2147483647" - - - input: - bytes: [ 0xc2, 0xf8, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agfi %r15, 0" - - - input: - bytes: [ 0xb9, 0x18, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agfr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x18, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agfr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x18, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agfr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x18, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agfr %r7, %r8" - - - input: - bytes: [ 0xa7, 0x0b, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aghi %r0, -32768" - - - input: - bytes: [ 0xa7, 0x0b, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aghi %r0, -1" - - - input: - bytes: [ 0xa7, 0x0b, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aghi %r0, 0" - - - input: - bytes: [ 0xa7, 0x0b, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aghi %r0, 1" - - - input: - bytes: [ 0xa7, 0x0b, 0x7f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aghi %r0, 32767" - - - input: - bytes: [ 0xa7, 0xfb, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aghi %r15, 0" - - - input: - bytes: [ 0xb9, 0x08, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x08, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x08, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x08, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agr %r7, %r8" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agsi -524288, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agsi -1, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agsi 0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agsi 1, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agsi 524287, 0" - - - input: - bytes: [ 0xeb, 0x80, 0x00, 0x00, 0x00, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agsi 0, -128" - - - input: - bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agsi 0, -1" - - - input: - bytes: [ 0xeb, 0x01, 0x00, 0x00, 0x00, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agsi 0, 1" - - - input: - bytes: [ 0xeb, 0x7f, 0x00, 0x00, 0x00, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agsi 0, 127" - - - input: - bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agsi 0(%r1), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agsi 0(%r15), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agsi 524287(%r1), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "agsi 524287(%r15), 42" - - - input: - bytes: [ 0x4a, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ah %r0, 0" - - - input: - bytes: [ 0x4a, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ah %r0, 4095" - - - input: - bytes: [ 0x4a, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ah %r0, 0(%r1)" - - - input: - bytes: [ 0x4a, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ah %r0, 0(%r15)" - - - input: - bytes: [ 0x4a, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ah %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x4a, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ah %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x4a, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ah %r15, 0" - - - input: - bytes: [ 0xa7, 0x0a, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahi %r0, -32768" - - - input: - bytes: [ 0xa7, 0x0a, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahi %r0, -1" - - - input: - bytes: [ 0xa7, 0x0a, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahi %r0, 0" - - - input: - bytes: [ 0xa7, 0x0a, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahi %r0, 1" - - - input: - bytes: [ 0xa7, 0x0a, 0x7f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahi %r0, 32767" - - - input: - bytes: [ 0xa7, 0xfa, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahi %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahy %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahy %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahy %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahy %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahy %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahy %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahy %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahy %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahy %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x7a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ahy %r15, 0" - - - input: - bytes: [ 0x5e, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "al %r0, 0" - - - input: - bytes: [ 0x5e, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "al %r0, 4095" - - - input: - bytes: [ 0x5e, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "al %r0, 0(%r1)" - - - input: - bytes: [ 0x5e, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "al %r0, 0(%r15)" - - - input: - bytes: [ 0x5e, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "al %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x5e, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "al %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x5e, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "al %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x98 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alc %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x98 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alc %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x98 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alc %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x98 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alc %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x98 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alc %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x98 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alc %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x98 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alc %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x98 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alc %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x98 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alc %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x98 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alc %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x88 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alcg %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x88 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alcg %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x88 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alcg %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x88 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alcg %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x88 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alcg %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x88 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alcg %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x88 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alcg %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x88 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alcg %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x88 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alcg %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x88 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alcg %r15, 0" - - - input: - bytes: [ 0xb9, 0x88, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alcgr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x88, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alcgr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x88, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alcgr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x88, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alcgr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x98, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alcr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x98, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alcr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x98, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alcr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x98, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alcr %r7, %r8" - - - input: - bytes: [ 0xc2, 0x0b, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alfi %r0, 0" - - - input: - bytes: [ 0xc2, 0x0b, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alfi %r0, 4294967295" - - - input: - bytes: [ 0xc2, 0xfb, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alfi %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alg %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alg %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alg %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alg %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alg %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alg %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alg %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alg %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alg %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alg %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algf %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algf %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algf %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algf %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algf %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algf %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algf %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algf %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algf %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x1a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algf %r15, 0" - - - input: - bytes: [ 0xc2, 0x0a, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algfi %r0, 0" - - - input: - bytes: [ 0xc2, 0x0a, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algfi %r0, 4294967295" - - - input: - bytes: [ 0xc2, 0xfa, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algfi %r15, 0" - - - input: - bytes: [ 0xb9, 0x1a, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algfr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x1a, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algfr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x1a, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algfr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x1a, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algfr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x0a, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x0a, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x0a, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x0a, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "algr %r7, %r8" - - - input: - bytes: [ 0x1e, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alr %r0, %r0" - - - input: - bytes: [ 0x1e, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alr %r0, %r15" - - - input: - bytes: [ 0x1e, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alr %r15, %r0" - - - input: - bytes: [ 0x1e, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "alr %r7, %r8" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x5e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aly %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x5e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aly %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x5e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aly %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x5e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aly %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x5e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aly %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x5e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aly %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x5e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aly %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x5e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aly %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x5e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aly %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x5e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "aly %r15, 0" - - - input: - bytes: [ 0x1a, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ar %r0, %r0" - - - input: - bytes: [ 0x1a, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ar %r0, %r15" - - - input: - bytes: [ 0x1a, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ar %r15, %r0" - - - input: - bytes: [ 0x1a, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ar %r7, %r8" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x6a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "asi -524288, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x6a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "asi -1, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x6a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "asi 0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x6a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "asi 1, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x6a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "asi 524287, 0" - - - input: - bytes: [ 0xeb, 0x80, 0x00, 0x00, 0x00, 0x6a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "asi 0, -128" - - - input: - bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x6a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "asi 0, -1" - - - input: - bytes: [ 0xeb, 0x01, 0x00, 0x00, 0x00, 0x6a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "asi 0, 1" - - - input: - bytes: [ 0xeb, 0x7f, 0x00, 0x00, 0x00, 0x6a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "asi 0, 127" - - - input: - bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x6a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "asi 0(%r1), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x6a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "asi 0(%r15), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x6a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "asi 524287(%r1), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x6a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "asi 524287(%r15), 42" - - - input: - bytes: [ 0xb3, 0x4a, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "axbr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x4a, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "axbr %f0, %f13" - - - input: - bytes: [ 0xb3, 0x4a, 0x00, 0x88 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "axbr %f8, %f8" - - - input: - bytes: [ 0xb3, 0x4a, 0x00, 0xd0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "axbr %f13, %f0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x5a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ay %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x5a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ay %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x5a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ay %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x5a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ay %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x5a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ay %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x5a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ay %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x5a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ay %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x5a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ay %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x5a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ay %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x5a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ay %r15, 0" - - - input: - bytes: [ 0x0d, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "basr %r0, %r1" - - - input: - bytes: [ 0x0d, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "basr %r0, %r15" - - - input: - bytes: [ 0x0d, 0xe9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "basr %r14, %r9" - - - input: - bytes: [ 0x0d, 0xf1 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "basr %r15, %r1" - - - input: - bytes: [ 0x07, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "bcr 0, %r0" - - - input: - bytes: [ 0x07, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "bcr 0, %r15" - - - input: - bytes: [ 0x07, 0x1f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "bor %r15" - - - input: - bytes: [ 0x07, 0x2f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "bhr %r15" - - - input: - bytes: [ 0x07, 0x3f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "bnler %r15" - - - input: - bytes: [ 0x07, 0x4f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "blr %r15" - - - input: - bytes: [ 0x07, 0x5f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "bnher %r15" - - - input: - bytes: [ 0x07, 0x6f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "blhr %r15" - - - input: - bytes: [ 0x07, 0x7f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "bner %r15" - - - input: - bytes: [ 0x07, 0x8f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ber %r15" - - - input: - bytes: [ 0x07, 0x9f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "bnlhr %r15" - - - input: - bytes: [ 0x07, 0xaf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "bher %r15" - - - input: - bytes: [ 0x07, 0xbf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "bnlr %r15" - - - input: - bytes: [ 0x07, 0xcf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "bler %r15" - - - input: - bytes: [ 0x07, 0xdf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "bnhr %r15" - - - input: - bytes: [ 0x07, 0xef ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "bnor %r15" - - - input: - bytes: [ 0x07, 0xf1 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "br %r1" - - - input: - bytes: [ 0x07, 0xfe ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "br %r14" - - - input: - bytes: [ 0x07, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "br %r15" - - - input: - bytes: [ 0x59, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "c %r0, 0" - - - input: - bytes: [ 0x59, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "c %r0, 4095" - - - input: - bytes: [ 0x59, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "c %r0, 0(%r1)" - - - input: - bytes: [ 0x59, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "c %r0, 0(%r15)" - - - input: - bytes: [ 0x59, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "c %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x59, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "c %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x59, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "c %r15, 0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x19 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdb %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x19 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdb %f0, 4095" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x19 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdb %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x19 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdb %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x19 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdb %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x19 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdb %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x19 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdb %f15, 0" - - - input: - bytes: [ 0xb3, 0x19, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdbr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x19, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdbr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x19, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdbr %f7, %f8" - - - input: - bytes: [ 0xb3, 0x19, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdbr %f15, %f0" - - - input: - bytes: [ 0xb3, 0x95, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdfbr %f0, %r0" - - - input: - bytes: [ 0xb3, 0x95, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdfbr %f0, %r15" - - - input: - bytes: [ 0xb3, 0x95, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdfbr %f15, %r0" - - - input: - bytes: [ 0xb3, 0x95, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdfbr %f7, %r8" - - - input: - bytes: [ 0xb3, 0x95, 0x00, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdfbr %f15, %r15" - - - input: - bytes: [ 0xb3, 0xa5, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdgbr %f0, %r0" - - - input: - bytes: [ 0xb3, 0xa5, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdgbr %f0, %r15" - - - input: - bytes: [ 0xb3, 0xa5, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdgbr %f15, %r0" - - - input: - bytes: [ 0xb3, 0xa5, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdgbr %f7, %r8" - - - input: - bytes: [ 0xb3, 0xa5, 0x00, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cdgbr %f15, %r15" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ceb %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ceb %f0, 4095" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ceb %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ceb %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ceb %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ceb %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ceb %f15, 0" - - - input: - bytes: [ 0xb3, 0x09, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cebr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x09, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cebr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x09, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cebr %f7, %f8" - - - input: - bytes: [ 0xb3, 0x09, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cebr %f15, %f0" - - - input: - bytes: [ 0xb3, 0x94, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cefbr %f0, %r0" - - - input: - bytes: [ 0xb3, 0x94, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cefbr %f0, %r15" - - - input: - bytes: [ 0xb3, 0x94, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cefbr %f15, %r0" - - - input: - bytes: [ 0xb3, 0x94, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cefbr %f7, %r8" - - - input: - bytes: [ 0xb3, 0x94, 0x00, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cefbr %f15, %r15" - - - input: - bytes: [ 0xb3, 0xa4, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cegbr %f0, %r0" - - - input: - bytes: [ 0xb3, 0xa4, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cegbr %f0, %r15" - - - input: - bytes: [ 0xb3, 0xa4, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cegbr %f15, %r0" - - - input: - bytes: [ 0xb3, 0xa4, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cegbr %f7, %r8" - - - input: - bytes: [ 0xb3, 0xa4, 0x00, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cegbr %f15, %r15" - - - input: - bytes: [ 0xb3, 0x99, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfdbr %r0, 0, %f0" - - - input: - bytes: [ 0xb3, 0x99, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfdbr %r0, 0, %f15" - - - input: - bytes: [ 0xb3, 0x99, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfdbr %r0, 15, %f0" - - - input: - bytes: [ 0xb3, 0x99, 0x50, 0x46 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfdbr %r4, 5, %f6" - - - input: - bytes: [ 0xb3, 0x99, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfdbr %r15, 0, %f0" - - - input: - bytes: [ 0xb3, 0x98, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfebr %r0, 0, %f0" - - - input: - bytes: [ 0xb3, 0x98, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfebr %r0, 0, %f15" - - - input: - bytes: [ 0xb3, 0x98, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfebr %r0, 15, %f0" - - - input: - bytes: [ 0xb3, 0x98, 0x50, 0x46 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfebr %r4, 5, %f6" - - - input: - bytes: [ 0xb3, 0x98, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfebr %r15, 0, %f0" - - - input: - bytes: [ 0xc2, 0x0d, 0x80, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfi %r0, -2147483648" - - - input: - bytes: [ 0xc2, 0x0d, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfi %r0, -1" - - - input: - bytes: [ 0xc2, 0x0d, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfi %r0, 0" - - - input: - bytes: [ 0xc2, 0x0d, 0x00, 0x00, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfi %r0, 1" - - - input: - bytes: [ 0xc2, 0x0d, 0x7f, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfi %r0, 2147483647" - - - input: - bytes: [ 0xc2, 0xfd, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfi %r15, 0" - - - input: - bytes: [ 0xb3, 0x9a, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfxbr %r0, 0, %f0" - - - input: - bytes: [ 0xb3, 0x9a, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfxbr %r0, 0, %f13" - - - input: - bytes: [ 0xb3, 0x9a, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfxbr %r0, 15, %f0" - - - input: - bytes: [ 0xb3, 0x9a, 0x50, 0x48 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfxbr %r4, 5, %f8" - - - input: - bytes: [ 0xb3, 0x9a, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cfxbr %r15, 0, %f0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x20 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cg %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x20 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cg %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x20 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cg %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x20 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cg %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x20 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cg %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x20 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cg %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x20 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cg %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x20 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cg %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x20 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cg %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x20 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cg %r15, 0" - - - input: - bytes: [ 0xb3, 0xa9, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgdbr %r0, 0, %f0" - - - input: - bytes: [ 0xb3, 0xa9, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgdbr %r0, 0, %f15" - - - input: - bytes: [ 0xb3, 0xa9, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgdbr %r0, 15, %f0" - - - input: - bytes: [ 0xb3, 0xa9, 0x50, 0x46 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgdbr %r4, 5, %f6" - - - input: - bytes: [ 0xb3, 0xa9, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgdbr %r15, 0, %f0" - - - input: - bytes: [ 0xb3, 0xa8, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgebr %r0, 0, %f0" - - - input: - bytes: [ 0xb3, 0xa8, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgebr %r0, 0, %f15" - - - input: - bytes: [ 0xb3, 0xa8, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgebr %r0, 15, %f0" - - - input: - bytes: [ 0xb3, 0xa8, 0x50, 0x46 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgebr %r4, 5, %f6" - - - input: - bytes: [ 0xb3, 0xa8, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgebr %r15, 0, %f0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgf %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgf %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgf %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgf %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgf %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgf %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgf %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgf %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgf %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgf %r15, 0" - - - input: - bytes: [ 0xc2, 0x0c, 0x80, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgfi %r0, -2147483648" - - - input: - bytes: [ 0xc2, 0x0c, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgfi %r0, -1" - - - input: - bytes: [ 0xc2, 0x0c, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgfi %r0, 0" - - - input: - bytes: [ 0xc2, 0x0c, 0x00, 0x00, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgfi %r0, 1" - - - input: - bytes: [ 0xc2, 0x0c, 0x7f, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgfi %r0, 2147483647" - - - input: - bytes: [ 0xc2, 0xfc, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgfi %r15, 0" - - - input: - bytes: [ 0xb9, 0x30, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgfr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x30, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgfr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x30, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgfr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x30, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgfr %r7, %r8" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x34 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgh %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x34 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgh %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x34 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgh %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x34 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgh %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x34 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgh %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x34 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgh %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x34 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgh %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x34 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgh %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x34 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgh %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x34 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgh %r15, 0" - - - input: - bytes: [ 0xa7, 0x0f, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cghi %r0, -32768" - - - input: - bytes: [ 0xa7, 0x0f, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cghi %r0, -1" - - - input: - bytes: [ 0xa7, 0x0f, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cghi %r0, 0" - - - input: - bytes: [ 0xa7, 0x0f, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cghi %r0, 1" - - - input: - bytes: [ 0xa7, 0x0f, 0x7f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cghi %r0, 32767" - - - input: - bytes: [ 0xa7, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cghi %r15, 0" - - - input: - bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cghsi 0, 0" - - - input: - bytes: [ 0xe5, 0x58, 0x0f, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cghsi 4095, 0" - - - input: - bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cghsi 0, -32768" - - - input: - bytes: [ 0xe5, 0x58, 0x00, 0x00, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cghsi 0, -1" - - - input: - bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cghsi 0, 0" - - - input: - bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cghsi 0, 1" - - - input: - bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x7f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cghsi 0, 32767" - - - input: - bytes: [ 0xe5, 0x58, 0x10, 0x00, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cghsi 0(%r1), 42" - - - input: - bytes: [ 0xe5, 0x58, 0xf0, 0x00, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cghsi 0(%r15), 42" - - - input: - bytes: [ 0xe5, 0x58, 0x1f, 0xff, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cghsi 4095(%r1), 42" - - - input: - bytes: [ 0xe5, 0x58, 0xff, 0xff, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cghsi 4095(%r15), 42" - - - input: - bytes: [ 0xb9, 0x20, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x20, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x20, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x20, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgr %r7, %r8" - - - input: - bytes: [ 0xb3, 0xaa, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgxbr %r0, 0, %f0" - - - input: - bytes: [ 0xb3, 0xaa, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgxbr %r0, 0, %f13" - - - input: - bytes: [ 0xb3, 0xaa, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgxbr %r0, 15, %f0" - - - input: - bytes: [ 0xb3, 0xaa, 0x50, 0x48 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgxbr %r4, 5, %f8" - - - input: - bytes: [ 0xb3, 0xaa, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cgxbr %r15, 0, %f0" - - - input: - bytes: [ 0x49, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ch %r0, 0" - - - input: - bytes: [ 0x49, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ch %r0, 4095" - - - input: - bytes: [ 0x49, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ch %r0, 0(%r1)" - - - input: - bytes: [ 0x49, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ch %r0, 0(%r15)" - - - input: - bytes: [ 0x49, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ch %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x49, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ch %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x49, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ch %r15, 0" - - - input: - bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chhsi 0, 0" - - - input: - bytes: [ 0xe5, 0x54, 0x0f, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chhsi 4095, 0" - - - input: - bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chhsi 0, -32768" - - - input: - bytes: [ 0xe5, 0x54, 0x00, 0x00, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chhsi 0, -1" - - - input: - bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chhsi 0, 0" - - - input: - bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chhsi 0, 1" - - - input: - bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x7f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chhsi 0, 32767" - - - input: - bytes: [ 0xe5, 0x54, 0x10, 0x00, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chhsi 0(%r1), 42" - - - input: - bytes: [ 0xe5, 0x54, 0xf0, 0x00, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chhsi 0(%r15), 42" - - - input: - bytes: [ 0xe5, 0x54, 0x1f, 0xff, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chhsi 4095(%r1), 42" - - - input: - bytes: [ 0xe5, 0x54, 0xff, 0xff, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chhsi 4095(%r15), 42" - - - input: - bytes: [ 0xa7, 0x0e, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chi %r0, -32768" - - - input: - bytes: [ 0xa7, 0x0e, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chi %r0, -1" - - - input: - bytes: [ 0xa7, 0x0e, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chi %r0, 0" - - - input: - bytes: [ 0xa7, 0x0e, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chi %r0, 1" - - - input: - bytes: [ 0xa7, 0x0e, 0x7f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chi %r0, 32767" - - - input: - bytes: [ 0xa7, 0xfe, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chi %r15, 0" - - - input: - bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chsi 0, 0" - - - input: - bytes: [ 0xe5, 0x5c, 0x0f, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chsi 4095, 0" - - - input: - bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chsi 0, -32768" - - - input: - bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chsi 0, -1" - - - input: - bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chsi 0, 0" - - - input: - bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chsi 0, 1" - - - input: - bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x7f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chsi 0, 32767" - - - input: - bytes: [ 0xe5, 0x5c, 0x10, 0x00, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chsi 0(%r1), 42" - - - input: - bytes: [ 0xe5, 0x5c, 0xf0, 0x00, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chsi 0(%r15), 42" - - - input: - bytes: [ 0xe5, 0x5c, 0x1f, 0xff, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chsi 4095(%r1), 42" - - - input: - bytes: [ 0xe5, 0x5c, 0xff, 0xff, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chsi 4095(%r15), 42" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x79 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chy %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x79 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chy %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x79 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chy %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x79 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chy %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x79 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chy %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x79 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chy %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x79 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chy %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x79 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chy %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x79 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chy %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x79 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "chy %r15, 0" - - - input: - bytes: [ 0x55, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cl %r0, 0" - - - input: - bytes: [ 0x55, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cl %r0, 4095" - - - input: - bytes: [ 0x55, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cl %r0, 0(%r1)" - - - input: - bytes: [ 0x55, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cl %r0, 0(%r15)" - - - input: - bytes: [ 0x55, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cl %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x55, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cl %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x55, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cl %r15, 0" - - - input: - bytes: [ 0xd5, 0x00, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clc 0(1), 0" - - - input: - bytes: [ 0xd5, 0x00, 0x00, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clc 0(1), 0(%r1)" - - - input: - bytes: [ 0xd5, 0x00, 0x00, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clc 0(1), 0(%r15)" - - - input: - bytes: [ 0xd5, 0x00, 0x00, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clc 0(1), 4095" - - - input: - bytes: [ 0xd5, 0x00, 0x00, 0x00, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clc 0(1), 4095(%r1)" - - - input: - bytes: [ 0xd5, 0x00, 0x00, 0x00, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clc 0(1), 4095(%r15)" - - - input: - bytes: [ 0xd5, 0x00, 0x10, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clc 0(1, %r1), 0" - - - input: - bytes: [ 0xd5, 0x00, 0xf0, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clc 0(1, %r15), 0" - - - input: - bytes: [ 0xd5, 0x00, 0x1f, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clc 4095(1, %r1), 0" - - - input: - bytes: [ 0xd5, 0x00, 0xff, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clc 4095(1, %r15), 0" - - - input: - bytes: [ 0xd5, 0xff, 0x10, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clc 0(256, %r1), 0" - - - input: - bytes: [ 0xd5, 0xff, 0xf0, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clc 0(256, %r15), 0" - - - input: - bytes: [ 0xe5, 0x5d, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfhsi 0, 0" - - - input: - bytes: [ 0xe5, 0x5d, 0x0f, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfhsi 4095, 0" - - - input: - bytes: [ 0xe5, 0x5d, 0x00, 0x00, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfhsi 0, 65535" - - - input: - bytes: [ 0xe5, 0x5d, 0x10, 0x00, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfhsi 0(%r1), 42" - - - input: - bytes: [ 0xe5, 0x5d, 0xf0, 0x00, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfhsi 0(%r15), 42" - - - input: - bytes: [ 0xe5, 0x5d, 0x1f, 0xff, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfhsi 4095(%r1), 42" - - - input: - bytes: [ 0xe5, 0x5d, 0xff, 0xff, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfhsi 4095(%r15), 42" - - - input: - bytes: [ 0xc2, 0x0f, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfi %r0, 0" - - - input: - bytes: [ 0xc2, 0x0f, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfi %r0, 4294967295" - - - input: - bytes: [ 0xc2, 0xff, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clfi %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x21 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clg %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x21 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clg %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x21 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clg %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x21 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clg %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x21 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clg %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x21 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clg %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x21 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clg %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x21 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clg %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x21 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clg %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x21 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clg %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x31 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgf %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x31 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgf %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x31 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgf %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x31 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgf %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x31 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgf %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x31 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgf %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x31 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgf %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x31 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgf %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x31 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgf %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x31 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgf %r15, 0" - - - input: - bytes: [ 0xc2, 0x0e, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgfi %r0, 0" - - - input: - bytes: [ 0xc2, 0x0e, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgfi %r0, 4294967295" - - - input: - bytes: [ 0xc2, 0xfe, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgfi %r15, 0" - - - input: - bytes: [ 0xb9, 0x31, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgfr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x31, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgfr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x31, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgfr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x31, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgfr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x21, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x21, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x21, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x21, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clgr %r7, %r8" - - - input: - bytes: [ 0xe5, 0x55, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clhhsi 0, 0" - - - input: - bytes: [ 0xe5, 0x55, 0x0f, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clhhsi 4095, 0" - - - input: - bytes: [ 0xe5, 0x55, 0x00, 0x00, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clhhsi 0, 65535" - - - input: - bytes: [ 0xe5, 0x55, 0x10, 0x00, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clhhsi 0(%r1), 42" - - - input: - bytes: [ 0xe5, 0x55, 0xf0, 0x00, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clhhsi 0(%r15), 42" - - - input: - bytes: [ 0xe5, 0x55, 0x1f, 0xff, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clhhsi 4095(%r1), 42" - - - input: - bytes: [ 0xe5, 0x55, 0xff, 0xff, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clhhsi 4095(%r15), 42" - - - input: - bytes: [ 0x95, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cli 0, 0" - - - input: - bytes: [ 0x95, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cli 4095, 0" - - - input: - bytes: [ 0x95, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cli 0, 255" - - - input: - bytes: [ 0x95, 0x2a, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cli 0(%r1), 42" - - - input: - bytes: [ 0x95, 0x2a, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cli 0(%r15), 42" - - - input: - bytes: [ 0x95, 0x2a, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cli 4095(%r1), 42" - - - input: - bytes: [ 0x95, 0x2a, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cli 4095(%r15), 42" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cliy -524288, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cliy -1, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cliy 0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cliy 1, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cliy 524287, 0" - - - input: - bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cliy 0, 255" - - - input: - bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cliy 0(%r1), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cliy 0(%r15), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cliy 524287(%r1), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cliy 524287(%r15), 42" - - - input: - bytes: [ 0x15, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clr %r0, %r0" - - - input: - bytes: [ 0x15, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clr %r0, %r15" - - - input: - bytes: [ 0x15, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clr %r15, %r0" - - - input: - bytes: [ 0x15, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clr %r7, %r8" - - - input: - bytes: [ 0xb2, 0x5d, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clst %r0, %r0" - - - input: - bytes: [ 0xb2, 0x5d, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clst %r0, %r15" - - - input: - bytes: [ 0xb2, 0x5d, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clst %r15, %r0" - - - input: - bytes: [ 0xb2, 0x5d, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "clst %r7, %r8" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cly %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cly %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cly %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cly %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cly %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cly %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cly %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cly %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cly %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cly %r15, 0" - - - input: - bytes: [ 0xb3, 0x72, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cpsdr %f0, %f0, %f0" - - - input: - bytes: [ 0xb3, 0x72, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cpsdr %f0, %f0, %f15" - - - input: - bytes: [ 0xb3, 0x72, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cpsdr %f0, %f15, %f0" - - - input: - bytes: [ 0xb3, 0x72, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cpsdr %f15, %f0, %f0" - - - input: - bytes: [ 0xb3, 0x72, 0x20, 0x13 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cpsdr %f1, %f2, %f3" - - - input: - bytes: [ 0xb3, 0x72, 0xf0, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cpsdr %f15, %f15, %f15" - - - input: - bytes: [ 0x19, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cr %r0, %r0" - - - input: - bytes: [ 0x19, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cr %r0, %r15" - - - input: - bytes: [ 0x19, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cr %r15, %r0" - - - input: - bytes: [ 0x19, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cr %r7, %r8" - - - input: - bytes: [ 0xba, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cs %r0, %r0, 0" - - - input: - bytes: [ 0xba, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cs %r0, %r0, 4095" - - - input: - bytes: [ 0xba, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cs %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xba, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cs %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xba, 0x00, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cs %r0, %r0, 4095(%r1)" - - - input: - bytes: [ 0xba, 0x00, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cs %r0, %r0, 4095(%r15)" - - - input: - bytes: [ 0xba, 0x0f, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cs %r0, %r15, 0" - - - input: - bytes: [ 0xba, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cs %r15, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csg %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csg %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csg %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csg %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csg %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csg %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csg %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csg %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csg %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csg %r0, %r15, 0" - - - input: - bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0x30 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csg %r15, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csy %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csy %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csy %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csy %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csy %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csy %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csy %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csy %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csy %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csy %r0, %r15, 0" - - - input: - bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "csy %r15, %r0, 0" - - - input: - bytes: [ 0xb3, 0x49, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxbr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x49, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxbr %f0, %f13" - - - input: - bytes: [ 0xb3, 0x49, 0x00, 0x88 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxbr %f8, %f8" - - - input: - bytes: [ 0xb3, 0x49, 0x00, 0xd0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxbr %f13, %f0" - - - input: - bytes: [ 0xb3, 0x96, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxfbr %f0, %r0" - - - input: - bytes: [ 0xb3, 0x96, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxfbr %f0, %r15" - - - input: - bytes: [ 0xb3, 0x96, 0x00, 0xd0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxfbr %f13, %r0" - - - input: - bytes: [ 0xb3, 0x96, 0x00, 0x87 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxfbr %f8, %r7" - - - input: - bytes: [ 0xb3, 0x96, 0x00, 0xdf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxfbr %f13, %r15" - - - input: - bytes: [ 0xb3, 0xa6, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxgbr %f0, %r0" - - - input: - bytes: [ 0xb3, 0xa6, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxgbr %f0, %r15" - - - input: - bytes: [ 0xb3, 0xa6, 0x00, 0xd0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxgbr %f13, %r0" - - - input: - bytes: [ 0xb3, 0xa6, 0x00, 0x87 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxgbr %f8, %r7" - - - input: - bytes: [ 0xb3, 0xa6, 0x00, 0xdf ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cxgbr %f13, %r15" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x59 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cy %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x59 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cy %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x59 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cy %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x59 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cy %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x59 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cy %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x59 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cy %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x59 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cy %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x59 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cy %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x59 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cy %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x59 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "cy %r15, 0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ddb %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ddb %f0, 4095" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ddb %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ddb %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ddb %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ddb %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ddb %f15, 0" - - - input: - bytes: [ 0xb3, 0x1d, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ddbr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x1d, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ddbr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x1d, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ddbr %f7, %f8" - - - input: - bytes: [ 0xb3, 0x1d, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ddbr %f15, %f0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "deb %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "deb %f0, 4095" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "deb %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "deb %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "deb %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "deb %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "deb %f15, 0" - - - input: - bytes: [ 0xb3, 0x0d, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "debr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x0d, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "debr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x0d, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "debr %f7, %f8" - - - input: - bytes: [ 0xb3, 0x0d, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "debr %f15, %f0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x97 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dl %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x97 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dl %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x97 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dl %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x97 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dl %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x97 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dl %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x97 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dl %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x97 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dl %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x97 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dl %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x97 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dl %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x97 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dl %r14, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x87 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlg %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x87 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlg %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x87 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlg %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x87 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlg %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x87 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlg %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x87 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlg %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x87 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlg %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x87 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlg %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x87 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlg %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x87 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlg %r14, 0" - - - input: - bytes: [ 0xb9, 0x87, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlgr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x87, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlgr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x87, 0x00, 0xe0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlgr %r14, %r0" - - - input: - bytes: [ 0xb9, 0x87, 0x00, 0x69 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlgr %r6, %r9" - - - input: - bytes: [ 0xb9, 0x97, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x97, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x97, 0x00, 0xe0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlr %r14, %r0" - - - input: - bytes: [ 0xb9, 0x97, 0x00, 0x69 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlr %r6, %r9" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsg %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsg %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsg %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsg %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsg %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsg %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsg %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsg %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsg %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsg %r14, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsgf %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsgf %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsgf %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsgf %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsgf %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsgf %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsgf %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsgf %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsgf %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsgf %r14, 0" - - - input: - bytes: [ 0xb9, 0x1d, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsgfr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x1d, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsgfr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x1d, 0x00, 0xe0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsgfr %r14, %r0" - - - input: - bytes: [ 0xb9, 0x1d, 0x00, 0x69 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsgfr %r6, %r9" - - - input: - bytes: [ 0xb9, 0x0d, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsgr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x0d, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsgr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x0d, 0x00, 0xe0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsgr %r14, %r0" - - - input: - bytes: [ 0xb9, 0x0d, 0x00, 0x69 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dsgr %r6, %r9" - - - input: - bytes: [ 0xb3, 0x4d, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dxbr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x4d, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dxbr %f0, %f13" - - - input: - bytes: [ 0xb3, 0x4d, 0x00, 0x88 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dxbr %f8, %f8" - - - input: - bytes: [ 0xb3, 0x4d, 0x00, 0xd0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dxbr %f13, %f0" - - - input: - bytes: [ 0xb2, 0x4f, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ear %r0, %a0" - - - input: - bytes: [ 0xb2, 0x4f, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ear %r0, %a15" - - - input: - bytes: [ 0xb2, 0x4f, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ear %r15, %a0" - - - input: - bytes: [ 0xb2, 0x4f, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ear %r7, %a8" - - - input: - bytes: [ 0xb2, 0x4f, 0x00, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ear %r15, %a15" - - - input: - bytes: [ 0xb3, 0x5f, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fidbr %f0, 0, %f0" - - - input: - bytes: [ 0xb3, 0x5f, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fidbr %f0, 0, %f15" - - - input: - bytes: [ 0xb3, 0x5f, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fidbr %f0, 15, %f0" - - - input: - bytes: [ 0xb3, 0x5f, 0x50, 0x46 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fidbr %f4, 5, %f6" - - - input: - bytes: [ 0xb3, 0x5f, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fidbr %f15, 0, %f0" - - - input: - bytes: [ 0xb3, 0x57, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fiebr %f0, 0, %f0" - - - input: - bytes: [ 0xb3, 0x57, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fiebr %f0, 0, %f15" - - - input: - bytes: [ 0xb3, 0x57, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fiebr %f0, 15, %f0" - - - input: - bytes: [ 0xb3, 0x57, 0x50, 0x46 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fiebr %f4, 5, %f6" - - - input: - bytes: [ 0xb3, 0x57, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fiebr %f15, 0, %f0" - - - input: - bytes: [ 0xb3, 0x47, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fixbr %f0, 0, %f0" - - - input: - bytes: [ 0xb3, 0x47, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fixbr %f0, 0, %f13" - - - input: - bytes: [ 0xb3, 0x47, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fixbr %f0, 15, %f0" - - - input: - bytes: [ 0xb3, 0x47, 0x50, 0x48 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fixbr %f4, 5, %f8" - - - input: - bytes: [ 0xb3, 0x47, 0x00, 0xd0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "fixbr %f13, 0, %f0" - - - input: - bytes: [ 0xb9, 0x83, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "flogr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x83, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "flogr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x83, 0x00, 0xa9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "flogr %r10, %r9" - - - input: - bytes: [ 0xb9, 0x83, 0x00, 0xe0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "flogr %r14, %r0" - - - input: - bytes: [ 0x43, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ic %r0, 0" - - - input: - bytes: [ 0x43, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ic %r0, 4095" - - - input: - bytes: [ 0x43, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ic %r0, 0(%r1)" - - - input: - bytes: [ 0x43, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ic %r0, 0(%r15)" - - - input: - bytes: [ 0x43, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ic %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x43, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ic %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x43, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ic %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x73 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "icy %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x73 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "icy %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x73 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "icy %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x73 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "icy %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x73 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "icy %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x73 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "icy %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x73 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "icy %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x73 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "icy %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x73 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "icy %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x73 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "icy %r15, 0" - - - input: - bytes: [ 0xc0, 0x08, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iihf %r0, 0" - - - input: - bytes: [ 0xc0, 0x08, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iihf %r0, 4294967295" - - - input: - bytes: [ 0xc0, 0xf8, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iihf %r15, 0" - - - input: - bytes: [ 0xa5, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iihh %r0, 0" - - - input: - bytes: [ 0xa5, 0x00, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iihh %r0, 32768" - - - input: - bytes: [ 0xa5, 0x00, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iihh %r0, 65535" - - - input: - bytes: [ 0xa5, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iihh %r15, 0" - - - input: - bytes: [ 0xa5, 0x01, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iihl %r0, 0" - - - input: - bytes: [ 0xa5, 0x01, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iihl %r0, 32768" - - - input: - bytes: [ 0xa5, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iihl %r0, 65535" - - - input: - bytes: [ 0xa5, 0xf1, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iihl %r15, 0" - - - input: - bytes: [ 0xc0, 0x09, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iilf %r0, 0" - - - input: - bytes: [ 0xc0, 0x09, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iilf %r0, 4294967295" - - - input: - bytes: [ 0xc0, 0xf9, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iilf %r15, 0" - - - input: - bytes: [ 0xa5, 0x02, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iilh %r0, 0" - - - input: - bytes: [ 0xa5, 0x02, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iilh %r0, 32768" - - - input: - bytes: [ 0xa5, 0x02, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iilh %r0, 65535" - - - input: - bytes: [ 0xa5, 0xf2, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iilh %r15, 0" - - - input: - bytes: [ 0xa5, 0x03, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iill %r0, 0" - - - input: - bytes: [ 0xa5, 0x03, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iill %r0, 32768" - - - input: - bytes: [ 0xa5, 0x03, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iill %r0, 65535" - - - input: - bytes: [ 0xa5, 0xf3, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "iill %r15, 0" - - - input: - bytes: [ 0xb2, 0x22, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ipm %r0" - - - input: - bytes: [ 0xb2, 0x22, 0x00, 0x10 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ipm %r1" - - - input: - bytes: [ 0xb2, 0x22, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ipm %r15" - - - input: - bytes: [ 0x58, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "l %r0, 0" - - - input: - bytes: [ 0x58, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "l %r0, 4095" - - - input: - bytes: [ 0x58, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "l %r0, 0(%r1)" - - - input: - bytes: [ 0x58, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "l %r0, 0(%r15)" - - - input: - bytes: [ 0x58, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "l %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x58, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "l %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x58, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "l %r15, 0" - - - input: - bytes: [ 0x41, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "la %r0, 0" - - - input: - bytes: [ 0x41, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "la %r0, 4095" - - - input: - bytes: [ 0x41, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "la %r0, 0(%r1)" - - - input: - bytes: [ 0x41, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "la %r0, 0(%r15)" - - - input: - bytes: [ 0x41, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "la %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x41, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "la %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x41, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "la %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x71 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lay %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x71 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lay %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x71 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lay %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x71 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lay %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x71 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lay %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x71 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lay %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x71 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lay %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x71 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lay %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x71 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lay %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x71 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lay %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x76 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lb %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x76 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lb %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x76 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lb %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x76 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lb %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x76 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lb %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x76 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lb %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x76 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lb %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x76 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lb %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x76 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lb %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x76 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lb %r15, 0" - - - input: - bytes: [ 0xb9, 0x26, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lbr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x26, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lbr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x26, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lbr %r15, %r0" - - - input: - bytes: [ 0xb3, 0x13, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcdbr %f0, %f9" - - - input: - bytes: [ 0xb3, 0x13, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcdbr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x13, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcdbr %f15, %f0" - - - input: - bytes: [ 0xb3, 0x13, 0x00, 0xf9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcdbr %f15, %f9" - - - input: - bytes: [ 0xb3, 0x03, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcebr %f0, %f9" - - - input: - bytes: [ 0xb3, 0x03, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcebr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x03, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcebr %f15, %f0" - - - input: - bytes: [ 0xb3, 0x03, 0x00, 0xf9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcebr %f15, %f9" - - - input: - bytes: [ 0xb9, 0x13, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcgfr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x13, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcgfr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x13, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcgfr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x13, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcgfr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x03, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcgr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x03, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcgr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x03, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcgr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x03, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcgr %r7, %r8" - - - input: - bytes: [ 0x13, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcr %r0, %r0" - - - input: - bytes: [ 0x13, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcr %r0, %r15" - - - input: - bytes: [ 0x13, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcr %r15, %r0" - - - input: - bytes: [ 0x13, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcr %r7, %r8" - - - input: - bytes: [ 0xb3, 0x43, 0x00, 0x08 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcxbr %f0, %f8" - - - input: - bytes: [ 0xb3, 0x43, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcxbr %f0, %f13" - - - input: - bytes: [ 0xb3, 0x43, 0x00, 0xd0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcxbr %f13, %f0" - - - input: - bytes: [ 0xb3, 0x43, 0x00, 0xd9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lcxbr %f13, %f9" - - - input: - bytes: [ 0x68, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ld %f0, 0" - - - input: - bytes: [ 0x68, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ld %f0, 4095" - - - input: - bytes: [ 0x68, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ld %f0, 0(%r1)" - - - input: - bytes: [ 0x68, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ld %f0, 0(%r15)" - - - input: - bytes: [ 0x68, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ld %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x68, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ld %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x68, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ld %f15, 0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldeb %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldeb %f0, 4095" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldeb %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldeb %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldeb %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldeb %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldeb %f15, 0" - - - input: - bytes: [ 0xb3, 0x04, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldebr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x04, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldebr %f7, %f8" - - - input: - bytes: [ 0xb3, 0x04, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldebr %f15, %f0" - - - input: - bytes: [ 0xb3, 0xc1, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldgr %f0, %r0" - - - input: - bytes: [ 0xb3, 0xc1, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldgr %f0, %r15" - - - input: - bytes: [ 0xb3, 0xc1, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldgr %f15, %r0" - - - input: - bytes: [ 0xb3, 0xc1, 0x00, 0x79 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldgr %f7, %r9" - - - input: - bytes: [ 0xb3, 0xc1, 0x00, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldgr %f15, %r15" - - - input: - bytes: [ 0x28, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldr %f0, %f9" - - - input: - bytes: [ 0x28, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldr %f0, %f15" - - - input: - bytes: [ 0x28, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldr %f15, %f0" - - - input: - bytes: [ 0x28, 0xf9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldr %f15, %f9" - - - input: - bytes: [ 0xb3, 0x45, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldxbr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x45, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldxbr %f0, %f13" - - - input: - bytes: [ 0xb3, 0x45, 0x00, 0x8c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldxbr %f8, %f12" - - - input: - bytes: [ 0xb3, 0x45, 0x00, 0xd0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldxbr %f13, %f0" - - - input: - bytes: [ 0xb3, 0x45, 0x00, 0xdd ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldxbr %f13, %f13" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x80, 0x65 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldy %f0, -524288" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0xff, 0x65 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldy %f0, -1" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x65 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldy %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x01, 0x00, 0x65 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldy %f0, 1" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x7f, 0x65 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldy %f0, 524287" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x65 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldy %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x65 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldy %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x7f, 0x65 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldy %f0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x7f, 0x65 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldy %f0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x65 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldy %f15, 0" - - - input: - bytes: [ 0x78, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "le %f0, 0" - - - input: - bytes: [ 0x78, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "le %f0, 4095" - - - input: - bytes: [ 0x78, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "le %f0, 0(%r1)" - - - input: - bytes: [ 0x78, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "le %f0, 0(%r15)" - - - input: - bytes: [ 0x78, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "le %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x78, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "le %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x78, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "le %f15, 0" - - - input: - bytes: [ 0xb3, 0x44, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ledbr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x44, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ledbr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x44, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ledbr %f7, %f8" - - - input: - bytes: [ 0xb3, 0x44, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ledbr %f15, %f0" - - - input: - bytes: [ 0xb3, 0x44, 0x00, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ledbr %f15, %f15" - - - input: - bytes: [ 0x38, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ler %f0, %f9" - - - input: - bytes: [ 0x38, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ler %f0, %f15" - - - input: - bytes: [ 0x38, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ler %f15, %f0" - - - input: - bytes: [ 0x38, 0xf9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ler %f15, %f9" - - - input: - bytes: [ 0xb3, 0x46, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lexbr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x46, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lexbr %f0, %f13" - - - input: - bytes: [ 0xb3, 0x46, 0x00, 0x8c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lexbr %f8, %f12" - - - input: - bytes: [ 0xb3, 0x46, 0x00, 0xd0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lexbr %f13, %f0" - - - input: - bytes: [ 0xb3, 0x46, 0x00, 0xdd ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lexbr %f13, %f13" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x80, 0x64 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ley %f0, -524288" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0xff, 0x64 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ley %f0, -1" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x64 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ley %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x01, 0x00, 0x64 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ley %f0, 1" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x7f, 0x64 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ley %f0, 524287" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x64 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ley %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x64 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ley %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x7f, 0x64 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ley %f0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x7f, 0x64 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ley %f0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x64 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ley %f15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lg %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lg %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lg %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lg %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lg %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lg %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lg %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lg %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lg %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lg %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x77 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgb %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x77 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgb %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x77 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgb %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x77 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgb %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x77 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgb %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x77 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgb %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x77 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgb %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x77 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgb %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x77 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgb %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x77 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgb %r15, 0" - - - input: - bytes: [ 0xb9, 0x06, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgbr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x06, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgbr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x06, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgbr %r15, %r0" - - - input: - bytes: [ 0xb3, 0xcd, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgdr %r0, %f0" - - - input: - bytes: [ 0xb3, 0xcd, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgdr %r0, %f15" - - - input: - bytes: [ 0xb3, 0xcd, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgdr %r15, %f0" - - - input: - bytes: [ 0xb3, 0xcd, 0x00, 0x88 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgdr %r8, %f8" - - - input: - bytes: [ 0xb3, 0xcd, 0x00, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgdr %r15, %f15" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgf %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgf %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgf %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgf %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgf %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgf %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgf %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgf %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgf %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgf %r15, 0" - - - input: - bytes: [ 0xc0, 0x01, 0x80, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgfi %r0, -2147483648" - - - input: - bytes: [ 0xc0, 0x01, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgfi %r0, -1" - - - input: - bytes: [ 0xc0, 0x01, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgfi %r0, 0" - - - input: - bytes: [ 0xc0, 0x01, 0x00, 0x00, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgfi %r0, 1" - - - input: - bytes: [ 0xc0, 0x01, 0x7f, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgfi %r0, 2147483647" - - - input: - bytes: [ 0xc0, 0xf1, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgfi %r15, 0" - - - input: - bytes: [ 0xb9, 0x14, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgfr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x14, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgfr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x14, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgfr %r15, %r0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x15 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgh %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x15 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgh %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x15 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgh %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x15 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgh %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x15 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgh %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x15 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgh %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x15 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgh %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x15 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgh %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x15 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgh %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x15 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgh %r15, 0" - - - input: - bytes: [ 0xa7, 0x09, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lghi %r0, -32768" - - - input: - bytes: [ 0xa7, 0x09, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lghi %r0, -1" - - - input: - bytes: [ 0xa7, 0x09, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lghi %r0, 0" - - - input: - bytes: [ 0xa7, 0x09, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lghi %r0, 1" - - - input: - bytes: [ 0xa7, 0x09, 0x7f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lghi %r0, 32767" - - - input: - bytes: [ 0xa7, 0xf9, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lghi %r15, 0" - - - input: - bytes: [ 0xb9, 0x07, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lghr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x07, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lghr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x07, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lghr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x04, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgr %r0, %r9" - - - input: - bytes: [ 0xb9, 0x04, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x04, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x04, 0x00, 0xf9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgr %r15, %r9" - - - input: - bytes: [ 0x48, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lh %r0, 0" - - - input: - bytes: [ 0x48, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lh %r0, 4095" - - - input: - bytes: [ 0x48, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lh %r0, 0(%r1)" - - - input: - bytes: [ 0x48, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lh %r0, 0(%r15)" - - - input: - bytes: [ 0x48, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lh %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x48, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lh %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x48, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lh %r15, 0" - - - input: - bytes: [ 0xa7, 0x08, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhi %r0, -32768" - - - input: - bytes: [ 0xa7, 0x08, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhi %r0, -1" - - - input: - bytes: [ 0xa7, 0x08, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhi %r0, 0" - - - input: - bytes: [ 0xa7, 0x08, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhi %r0, 1" - - - input: - bytes: [ 0xa7, 0x08, 0x7f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhi %r0, 32767" - - - input: - bytes: [ 0xa7, 0xf8, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhi %r15, 0" - - - input: - bytes: [ 0xb9, 0x27, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x27, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x27, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhr %r15, %r0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhy %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhy %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhy %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhy %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhy %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhy %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhy %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhy %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhy %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lhy %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x94 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llc %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x94 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llc %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x94 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llc %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x94 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llc %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x94 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llc %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x94 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llc %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x94 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llc %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x94 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llc %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x94 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llc %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x94 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llc %r15, 0" - - - input: - bytes: [ 0xb9, 0x94, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llcr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x94, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llcr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x94, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llcr %r15, %r0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x90 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgc %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x90 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgc %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x90 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgc %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x90 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgc %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x90 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgc %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x90 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgc %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x90 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgc %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x90 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgc %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x90 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgc %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x90 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgc %r15, 0" - - - input: - bytes: [ 0xb9, 0x84, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgcr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x84, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgcr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x84, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgcr %r15, %r0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x16 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgf %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x16 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgf %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x16 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgf %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x16 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgf %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x16 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgf %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x16 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgf %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x16 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgf %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x16 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgf %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x16 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgf %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x16 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgf %r15, 0" - - - input: - bytes: [ 0xb9, 0x16, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgfr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x16, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgfr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x16, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgfr %r15, %r0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x91 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgh %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x91 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgh %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x91 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgh %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x91 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgh %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x91 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgh %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x91 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgh %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x91 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgh %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x91 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgh %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x91 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgh %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x91 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llgh %r15, 0" - - - input: - bytes: [ 0xb9, 0x85, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llghr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x85, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llghr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x85, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llghr %r15, %r0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x95 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llh %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x95 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llh %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x95 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llh %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x95 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llh %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x95 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llh %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x95 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llh %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x95 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llh %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x95 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llh %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x95 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llh %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x95 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llh %r15, 0" - - - input: - bytes: [ 0xb9, 0x95, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llhr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x95, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llhr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x95, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llhr %r15, %r0" - - - input: - bytes: [ 0xc0, 0x0e, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llihf %r0, 0" - - - input: - bytes: [ 0xc0, 0x0e, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llihf %r0, 4294967295" - - - input: - bytes: [ 0xc0, 0xfe, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llihf %r15, 0" - - - input: - bytes: [ 0xa5, 0x0c, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llihh %r0, 0" - - - input: - bytes: [ 0xa5, 0x0c, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llihh %r0, 32768" - - - input: - bytes: [ 0xa5, 0x0c, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llihh %r0, 65535" - - - input: - bytes: [ 0xa5, 0xfc, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llihh %r15, 0" - - - input: - bytes: [ 0xa5, 0x0d, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llihl %r0, 0" - - - input: - bytes: [ 0xa5, 0x0d, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llihl %r0, 32768" - - - input: - bytes: [ 0xa5, 0x0d, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llihl %r0, 65535" - - - input: - bytes: [ 0xa5, 0xfd, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llihl %r15, 0" - - - input: - bytes: [ 0xc0, 0x0f, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llilf %r0, 0" - - - input: - bytes: [ 0xc0, 0x0f, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llilf %r0, 4294967295" - - - input: - bytes: [ 0xc0, 0xff, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llilf %r15, 0" - - - input: - bytes: [ 0xa5, 0x0e, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llilh %r0, 0" - - - input: - bytes: [ 0xa5, 0x0e, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llilh %r0, 32768" - - - input: - bytes: [ 0xa5, 0x0e, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llilh %r0, 65535" - - - input: - bytes: [ 0xa5, 0xfe, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llilh %r15, 0" - - - input: - bytes: [ 0xa5, 0x0f, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llill %r0, 0" - - - input: - bytes: [ 0xa5, 0x0f, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llill %r0, 32768" - - - input: - bytes: [ 0xa5, 0x0f, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llill %r0, 65535" - - - input: - bytes: [ 0xa5, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "llill %r15, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lmg %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lmg %r0, %r15, 0" - - - input: - bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lmg %r14, %r15, 0" - - - input: - bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lmg %r15, %r15, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lmg %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lmg %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lmg %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lmg %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lmg %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lmg %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lmg %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lmg %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x04 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lmg %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0xb3, 0x11, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lndbr %f0, %f9" - - - input: - bytes: [ 0xb3, 0x11, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lndbr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x11, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lndbr %f15, %f0" - - - input: - bytes: [ 0xb3, 0x11, 0x00, 0xf9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lndbr %f15, %f9" - - - input: - bytes: [ 0xb3, 0x01, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lnebr %f0, %f9" - - - input: - bytes: [ 0xb3, 0x01, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lnebr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x01, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lnebr %f15, %f0" - - - input: - bytes: [ 0xb3, 0x01, 0x00, 0xf9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lnebr %f15, %f9" - - - input: - bytes: [ 0xb9, 0x11, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lngfr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x11, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lngfr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x11, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lngfr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x11, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lngfr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x01, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lngr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x01, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lngr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x01, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lngr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x01, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lngr %r7, %r8" - - - input: - bytes: [ 0x11, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lnr %r0, %r0" - - - input: - bytes: [ 0x11, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lnr %r0, %r15" - - - input: - bytes: [ 0x11, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lnr %r15, %r0" - - - input: - bytes: [ 0x11, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lnr %r7, %r8" - - - input: - bytes: [ 0xb3, 0x41, 0x00, 0x08 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lnxbr %f0, %f8" - - - input: - bytes: [ 0xb3, 0x41, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lnxbr %f0, %f13" - - - input: - bytes: [ 0xb3, 0x41, 0x00, 0xd0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lnxbr %f13, %f0" - - - input: - bytes: [ 0xb3, 0x41, 0x00, 0xd9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lnxbr %f13, %f9" - - - input: - bytes: [ 0xb3, 0x10, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpdbr %f0, %f9" - - - input: - bytes: [ 0xb3, 0x10, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpdbr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x10, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpdbr %f15, %f0" - - - input: - bytes: [ 0xb3, 0x10, 0x00, 0xf9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpdbr %f15, %f9" - - - input: - bytes: [ 0xb3, 0x00, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpebr %f0, %f9" - - - input: - bytes: [ 0xb3, 0x00, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpebr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x00, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpebr %f15, %f0" - - - input: - bytes: [ 0xb3, 0x00, 0x00, 0xf9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpebr %f15, %f9" - - - input: - bytes: [ 0xb9, 0x10, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpgfr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x10, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpgfr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x10, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpgfr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x10, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpgfr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpgr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x00, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpgr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x00, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpgr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x00, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpgr %r7, %r8" - - - input: - bytes: [ 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpr %r0, %r0" - - - input: - bytes: [ 0x10, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpr %r0, %r15" - - - input: - bytes: [ 0x10, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpr %r15, %r0" - - - input: - bytes: [ 0x10, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpr %r7, %r8" - - - input: - bytes: [ 0xb3, 0x40, 0x00, 0x08 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpxbr %f0, %f8" - - - input: - bytes: [ 0xb3, 0x40, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpxbr %f0, %f13" - - - input: - bytes: [ 0xb3, 0x40, 0x00, 0xd0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpxbr %f13, %f0" - - - input: - bytes: [ 0xb3, 0x40, 0x00, 0xd9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lpxbr %f13, %f9" - - - input: - bytes: [ 0x18, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lr %r0, %r9" - - - input: - bytes: [ 0x18, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lr %r0, %r15" - - - input: - bytes: [ 0x18, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lr %r15, %r0" - - - input: - bytes: [ 0x18, 0xf9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lr %r15, %r9" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrv %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrv %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrv %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrv %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrv %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrv %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrv %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrv %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrv %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x1e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrv %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvg %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvg %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvg %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvg %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvg %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvg %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvg %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvg %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvg %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvg %r15, 0" - - - input: - bytes: [ 0xb9, 0x0f, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvgr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x0f, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvgr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x0f, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvgr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x0f, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvgr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x0f, 0x00, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvgr %r15, %r15" - - - input: - bytes: [ 0xb9, 0x1f, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x1f, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x1f, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x1f, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x1f, 0x00, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lrvr %r15, %r15" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x12 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lt %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x12 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lt %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x12 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lt %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x12 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lt %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x12 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lt %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x12 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lt %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x12 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lt %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x12 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lt %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x12 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lt %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x12 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lt %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x02 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltg %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x02 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltg %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x02 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltg %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x02 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltg %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x02 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltg %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x02 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltg %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x02 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltg %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x02 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltg %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x02 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltg %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x02 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltg %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x32 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltgf %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x32 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltgf %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x32 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltgf %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x32 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltgf %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x32 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltgf %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x32 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltgf %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x32 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltgf %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x32 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltgf %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x32 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltgf %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x32 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltgf %r15, 0" - - - input: - bytes: [ 0xb3, 0x12, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltdbr %f0, %f9" - - - input: - bytes: [ 0xb3, 0x12, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltdbr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x12, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltdbr %f15, %f0" - - - input: - bytes: [ 0xb3, 0x12, 0x00, 0xf9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltdbr %f15, %f9" - - - input: - bytes: [ 0xb3, 0x02, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltebr %f0, %f9" - - - input: - bytes: [ 0xb3, 0x02, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltebr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x02, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltebr %f15, %f0" - - - input: - bytes: [ 0xb3, 0x02, 0x00, 0xf9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltebr %f15, %f9" - - - input: - bytes: [ 0xb9, 0x12, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltgfr %r0, %r9" - - - input: - bytes: [ 0xb9, 0x12, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltgfr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x12, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltgfr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x12, 0x00, 0xf9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltgfr %r15, %r9" - - - input: - bytes: [ 0xb9, 0x02, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltgr %r0, %r9" - - - input: - bytes: [ 0xb9, 0x02, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltgr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x02, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltgr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x02, 0x00, 0xf9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltgr %r15, %r9" - - - input: - bytes: [ 0x12, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltr %r0, %r9" - - - input: - bytes: [ 0x12, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltr %r0, %r15" - - - input: - bytes: [ 0x12, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltr %r15, %r0" - - - input: - bytes: [ 0x12, 0xf9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltr %r15, %r9" - - - input: - bytes: [ 0xb3, 0x42, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltxbr %f0, %f9" - - - input: - bytes: [ 0xb3, 0x42, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltxbr %f0, %f13" - - - input: - bytes: [ 0xb3, 0x42, 0x00, 0xd0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltxbr %f13, %f0" - - - input: - bytes: [ 0xb3, 0x42, 0x00, 0xd9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ltxbr %f13, %f9" - - - input: - bytes: [ 0xb3, 0x65, 0x00, 0x08 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lxr %f0, %f8" - - - input: - bytes: [ 0xb3, 0x65, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lxr %f0, %f13" - - - input: - bytes: [ 0xb3, 0x65, 0x00, 0xd0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lxr %f13, %f0" - - - input: - bytes: [ 0xb3, 0x65, 0x00, 0xd9 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lxr %f13, %f9" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x58 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ly %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x58 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ly %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x58 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ly %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x58 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ly %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x58 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ly %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x58 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ly %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x58 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ly %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x58 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ly %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x58 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ly %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x58 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ly %r15, 0" - - - input: - bytes: [ 0xb3, 0x75, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lzdr %f0" - - - input: - bytes: [ 0xb3, 0x75, 0x00, 0x70 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lzdr %f7" - - - input: - bytes: [ 0xb3, 0x75, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lzdr %f15" - - - input: - bytes: [ 0xb3, 0x74, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lzer %f0" - - - input: - bytes: [ 0xb3, 0x74, 0x00, 0x70 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lzer %f7" - - - input: - bytes: [ 0xb3, 0x74, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lzer %f15" - - - input: - bytes: [ 0xb3, 0x76, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lzxr %f0" - - - input: - bytes: [ 0xb3, 0x76, 0x00, 0x80 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lzxr %f8" - - - input: - bytes: [ 0xb3, 0x76, 0x00, 0xd0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lzxr %f13" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "madb %f0, %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "madb %f0, %f0, 4095" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "madb %f0, %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "madb %f0, %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "madb %f0, %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "madb %f0, %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "madb %f0, %f15, 0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x1e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "madb %f15, %f0, 0" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x1e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "madb %f15, %f15, 0" - - - input: - bytes: [ 0xb3, 0x1e, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "madbr %f0, %f0, %f0" - - - input: - bytes: [ 0xb3, 0x1e, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "madbr %f0, %f0, %f15" - - - input: - bytes: [ 0xb3, 0x1e, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "madbr %f0, %f15, %f0" - - - input: - bytes: [ 0xb3, 0x1e, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "madbr %f15, %f0, %f0" - - - input: - bytes: [ 0xb3, 0x1e, 0x70, 0x89 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "madbr %f7, %f8, %f9" - - - input: - bytes: [ 0xb3, 0x1e, 0xf0, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "madbr %f15, %f15, %f15" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "maeb %f0, %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "maeb %f0, %f0, 4095" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "maeb %f0, %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "maeb %f0, %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "maeb %f0, %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "maeb %f0, %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "maeb %f0, %f15, 0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x0e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "maeb %f15, %f0, 0" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x0e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "maeb %f15, %f15, 0" - - - input: - bytes: [ 0xb3, 0x0e, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "maebr %f0, %f0, %f0" - - - input: - bytes: [ 0xb3, 0x0e, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "maebr %f0, %f0, %f15" - - - input: - bytes: [ 0xb3, 0x0e, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "maebr %f0, %f15, %f0" - - - input: - bytes: [ 0xb3, 0x0e, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "maebr %f15, %f0, %f0" - - - input: - bytes: [ 0xb3, 0x0e, 0x70, 0x89 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "maebr %f7, %f8, %f9" - - - input: - bytes: [ 0xb3, 0x0e, 0xf0, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "maebr %f15, %f15, %f15" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdb %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdb %f0, 4095" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdb %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdb %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdb %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdb %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdb %f15, 0" - - - input: - bytes: [ 0xb3, 0x1c, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdbr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x1c, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdbr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x1c, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdbr %f7, %f8" - - - input: - bytes: [ 0xb3, 0x1c, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdbr %f15, %f0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdeb %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdeb %f0, 4095" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdeb %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdeb %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdeb %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdeb %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdeb %f15, 0" - - - input: - bytes: [ 0xb3, 0x0c, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdebr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x0c, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdebr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x0c, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdebr %f7, %f8" - - - input: - bytes: [ 0xb3, 0x0c, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mdebr %f15, %f0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x17 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "meeb %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x17 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "meeb %f0, 4095" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x17 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "meeb %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x17 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "meeb %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x17 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "meeb %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x17 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "meeb %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x17 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "meeb %f15, 0" - - - input: - bytes: [ 0xb3, 0x17, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "meebr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x17, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "meebr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x17, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "meebr %f7, %f8" - - - input: - bytes: [ 0xb3, 0x17, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "meebr %f15, %f0" - - - input: - bytes: [ 0xa7, 0x0d, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mghi %r0, -32768" - - - input: - bytes: [ 0xa7, 0x0d, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mghi %r0, -1" - - - input: - bytes: [ 0xa7, 0x0d, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mghi %r0, 0" - - - input: - bytes: [ 0xa7, 0x0d, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mghi %r0, 1" - - - input: - bytes: [ 0xa7, 0x0d, 0x7f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mghi %r0, 32767" - - - input: - bytes: [ 0xa7, 0xfd, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mghi %r15, 0" - - - input: - bytes: [ 0x4c, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mh %r0, 0" - - - input: - bytes: [ 0x4c, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mh %r0, 4095" - - - input: - bytes: [ 0x4c, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mh %r0, 0(%r1)" - - - input: - bytes: [ 0x4c, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mh %r0, 0(%r15)" - - - input: - bytes: [ 0x4c, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mh %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x4c, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mh %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x4c, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mh %r15, 0" - - - input: - bytes: [ 0xa7, 0x0c, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mhi %r0, -32768" - - - input: - bytes: [ 0xa7, 0x0c, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mhi %r0, -1" - - - input: - bytes: [ 0xa7, 0x0c, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mhi %r0, 0" - - - input: - bytes: [ 0xa7, 0x0c, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mhi %r0, 1" - - - input: - bytes: [ 0xa7, 0x0c, 0x7f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mhi %r0, 32767" - - - input: - bytes: [ 0xa7, 0xfc, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mhi %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x7c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mhy %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x7c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mhy %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x7c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mhy %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x7c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mhy %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x7c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mhy %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x7c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mhy %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x7c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mhy %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x7c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mhy %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x7c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mhy %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x7c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mhy %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x86 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mlg %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x86 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mlg %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x86 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mlg %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x86 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mlg %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x86 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mlg %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x86 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mlg %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x86 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mlg %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x86 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mlg %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x86 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mlg %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x86 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mlg %r14, 0" - - - input: - bytes: [ 0xb9, 0x86, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mlgr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x86, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mlgr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x86, 0x00, 0xe0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mlgr %r14, %r0" - - - input: - bytes: [ 0xb9, 0x86, 0x00, 0x69 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mlgr %r6, %r9" - - - input: - bytes: [ 0x71, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ms %r0, 0" - - - input: - bytes: [ 0x71, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ms %r0, 4095" - - - input: - bytes: [ 0x71, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ms %r0, 0(%r1)" - - - input: - bytes: [ 0x71, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ms %r0, 0(%r15)" - - - input: - bytes: [ 0x71, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ms %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x71, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ms %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x71, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ms %r15, 0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msdb %f0, %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msdb %f0, %f0, 4095" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msdb %f0, %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msdb %f0, %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msdb %f0, %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msdb %f0, %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msdb %f0, %f15, 0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x1f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msdb %f15, %f0, 0" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x1f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msdb %f15, %f15, 0" - - - input: - bytes: [ 0xb3, 0x1f, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msdbr %f0, %f0, %f0" - - - input: - bytes: [ 0xb3, 0x1f, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msdbr %f0, %f0, %f15" - - - input: - bytes: [ 0xb3, 0x1f, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msdbr %f0, %f15, %f0" - - - input: - bytes: [ 0xb3, 0x1f, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msdbr %f15, %f0, %f0" - - - input: - bytes: [ 0xb3, 0x1f, 0x70, 0x89 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msdbr %f7, %f8, %f9" - - - input: - bytes: [ 0xb3, 0x1f, 0xf0, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msdbr %f15, %f15, %f15" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mseb %f0, %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mseb %f0, %f0, 4095" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mseb %f0, %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mseb %f0, %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mseb %f0, %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mseb %f0, %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mseb %f0, %f15, 0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mseb %f15, %f0, 0" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mseb %f15, %f15, 0" - - - input: - bytes: [ 0xb3, 0x0f, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msebr %f0, %f0, %f0" - - - input: - bytes: [ 0xb3, 0x0f, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msebr %f0, %f0, %f15" - - - input: - bytes: [ 0xb3, 0x0f, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msebr %f0, %f15, %f0" - - - input: - bytes: [ 0xb3, 0x0f, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msebr %f15, %f0, %f0" - - - input: - bytes: [ 0xb3, 0x0f, 0x70, 0x89 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msebr %f7, %f8, %f9" - - - input: - bytes: [ 0xb3, 0x0f, 0xf0, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msebr %f15, %f15, %f15" - - - input: - bytes: [ 0xc2, 0x01, 0x80, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msfi %r0, -2147483648" - - - input: - bytes: [ 0xc2, 0x01, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msfi %r0, -1" - - - input: - bytes: [ 0xc2, 0x01, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msfi %r0, 0" - - - input: - bytes: [ 0xc2, 0x01, 0x00, 0x00, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msfi %r0, 1" - - - input: - bytes: [ 0xc2, 0x01, 0x7f, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msfi %r0, 2147483647" - - - input: - bytes: [ 0xc2, 0xf1, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msfi %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msg %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msg %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msg %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msg %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msg %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msg %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msg %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msg %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msg %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msg %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgf %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgf %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgf %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgf %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgf %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgf %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgf %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgf %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgf %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgf %r15, 0" - - - input: - bytes: [ 0xc2, 0x00, 0x80, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgfi %r0, -2147483648" - - - input: - bytes: [ 0xc2, 0x00, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgfi %r0, -1" - - - input: - bytes: [ 0xc2, 0x00, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgfi %r0, 0" - - - input: - bytes: [ 0xc2, 0x00, 0x00, 0x00, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgfi %r0, 1" - - - input: - bytes: [ 0xc2, 0x00, 0x7f, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgfi %r0, 2147483647" - - - input: - bytes: [ 0xc2, 0xf0, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgfi %r15, 0" - - - input: - bytes: [ 0xb9, 0x1c, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgfr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x1c, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgfr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x1c, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgfr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x1c, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgfr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x0c, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x0c, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x0c, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x0c, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msgr %r7, %r8" - - - input: - bytes: [ 0xb2, 0x52, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msr %r0, %r0" - - - input: - bytes: [ 0xb2, 0x52, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msr %r0, %r15" - - - input: - bytes: [ 0xb2, 0x52, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msr %r15, %r0" - - - input: - bytes: [ 0xb2, 0x52, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msr %r7, %r8" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msy %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msy %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msy %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msy %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msy %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msy %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msy %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msy %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msy %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "msy %r15, 0" - - - input: - bytes: [ 0xd2, 0x00, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvc 0(1), 0" - - - input: - bytes: [ 0xd2, 0x00, 0x00, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvc 0(1), 0(%r1)" - - - input: - bytes: [ 0xd2, 0x00, 0x00, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvc 0(1), 0(%r15)" - - - input: - bytes: [ 0xd2, 0x00, 0x00, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvc 0(1), 4095" - - - input: - bytes: [ 0xd2, 0x00, 0x00, 0x00, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvc 0(1), 4095(%r1)" - - - input: - bytes: [ 0xd2, 0x00, 0x00, 0x00, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvc 0(1), 4095(%r15)" - - - input: - bytes: [ 0xd2, 0x00, 0x10, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvc 0(1, %r1), 0" - - - input: - bytes: [ 0xd2, 0x00, 0xf0, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvc 0(1, %r15), 0" - - - input: - bytes: [ 0xd2, 0x00, 0x1f, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvc 4095(1, %r1), 0" - - - input: - bytes: [ 0xd2, 0x00, 0xff, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvc 4095(1, %r15), 0" - - - input: - bytes: [ 0xd2, 0xff, 0x10, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvc 0(256, %r1), 0" - - - input: - bytes: [ 0xd2, 0xff, 0xf0, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvc 0(256, %r15), 0" - - - input: - bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvghi 0, 0" - - - input: - bytes: [ 0xe5, 0x48, 0x0f, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvghi 4095, 0" - - - input: - bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvghi 0, -32768" - - - input: - bytes: [ 0xe5, 0x48, 0x00, 0x00, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvghi 0, -1" - - - input: - bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvghi 0, 0" - - - input: - bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvghi 0, 1" - - - input: - bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x7f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvghi 0, 32767" - - - input: - bytes: [ 0xe5, 0x48, 0x10, 0x00, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvghi 0(%r1), 42" - - - input: - bytes: [ 0xe5, 0x48, 0xf0, 0x00, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvghi 0(%r15), 42" - - - input: - bytes: [ 0xe5, 0x48, 0x1f, 0xff, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvghi 4095(%r1), 42" - - - input: - bytes: [ 0xe5, 0x48, 0xff, 0xff, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvghi 4095(%r15), 42" - - - input: - bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhhi 0, 0" - - - input: - bytes: [ 0xe5, 0x44, 0x0f, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhhi 4095, 0" - - - input: - bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhhi 0, -32768" - - - input: - bytes: [ 0xe5, 0x44, 0x00, 0x00, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhhi 0, -1" - - - input: - bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhhi 0, 0" - - - input: - bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhhi 0, 1" - - - input: - bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x7f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhhi 0, 32767" - - - input: - bytes: [ 0xe5, 0x44, 0x10, 0x00, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhhi 0(%r1), 42" - - - input: - bytes: [ 0xe5, 0x44, 0xf0, 0x00, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhhi 0(%r15), 42" - - - input: - bytes: [ 0xe5, 0x44, 0x1f, 0xff, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhhi 4095(%r1), 42" - - - input: - bytes: [ 0xe5, 0x44, 0xff, 0xff, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhhi 4095(%r15), 42" - - - input: - bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhi 0, 0" - - - input: - bytes: [ 0xe5, 0x4c, 0x0f, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhi 4095, 0" - - - input: - bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhi 0, -32768" - - - input: - bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhi 0, -1" - - - input: - bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhi 0, 0" - - - input: - bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhi 0, 1" - - - input: - bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x7f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhi 0, 32767" - - - input: - bytes: [ 0xe5, 0x4c, 0x10, 0x00, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhi 0(%r1), 42" - - - input: - bytes: [ 0xe5, 0x4c, 0xf0, 0x00, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhi 0(%r15), 42" - - - input: - bytes: [ 0xe5, 0x4c, 0x1f, 0xff, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhi 4095(%r1), 42" - - - input: - bytes: [ 0xe5, 0x4c, 0xff, 0xff, 0x00, 0x2a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvhi 4095(%r15), 42" - - - input: - bytes: [ 0x92, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvi 0, 0" - - - input: - bytes: [ 0x92, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvi 4095, 0" - - - input: - bytes: [ 0x92, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvi 0, 255" - - - input: - bytes: [ 0x92, 0x2a, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvi 0(%r1), 42" - - - input: - bytes: [ 0x92, 0x2a, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvi 0(%r15), 42" - - - input: - bytes: [ 0x92, 0x2a, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvi 4095(%r1), 42" - - - input: - bytes: [ 0x92, 0x2a, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvi 4095(%r15), 42" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x52 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mviy -524288, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x52 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mviy -1, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x52 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mviy 0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x52 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mviy 1, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x52 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mviy 524287, 0" - - - input: - bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x52 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mviy 0, 255" - - - input: - bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x52 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mviy 0(%r1), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x52 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mviy 0(%r15), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x52 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mviy 524287(%r1), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x52 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mviy 524287(%r15), 42" - - - input: - bytes: [ 0xb2, 0x55, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvst %r0, %r0" - - - input: - bytes: [ 0xb2, 0x55, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvst %r0, %r15" - - - input: - bytes: [ 0xb2, 0x55, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvst %r15, %r0" - - - input: - bytes: [ 0xb2, 0x55, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mvst %r7, %r8" - - - input: - bytes: [ 0xb3, 0x4c, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mxbr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x4c, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mxbr %f0, %f13" - - - input: - bytes: [ 0xb3, 0x4c, 0x00, 0x85 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mxbr %f8, %f5" - - - input: - bytes: [ 0xb3, 0x4c, 0x00, 0xdd ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mxbr %f13, %f13" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x07 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mxdb %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x07 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mxdb %f0, 4095" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x07 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mxdb %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x07 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mxdb %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x07 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mxdb %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x07 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mxdb %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xd0, 0x00, 0x00, 0x00, 0x07 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mxdb %f13, 0" - - - input: - bytes: [ 0xb3, 0x07, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mxdbr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x07, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mxdbr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x07, 0x00, 0x88 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mxdbr %f8, %f8" - - - input: - bytes: [ 0xb3, 0x07, 0x00, 0xd0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "mxdbr %f13, %f0" - - - input: - bytes: [ 0x54, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "n %r0, 0" - - - input: - bytes: [ 0x54, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "n %r0, 4095" - - - input: - bytes: [ 0x54, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "n %r0, 0(%r1)" - - - input: - bytes: [ 0x54, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "n %r0, 0(%r15)" - - - input: - bytes: [ 0x54, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "n %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x54, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "n %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x54, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "n %r15, 0" - - - input: - bytes: [ 0xd4, 0x00, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nc 0(1), 0" - - - input: - bytes: [ 0xd4, 0x00, 0x00, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nc 0(1), 0(%r1)" - - - input: - bytes: [ 0xd4, 0x00, 0x00, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nc 0(1), 0(%r15)" - - - input: - bytes: [ 0xd4, 0x00, 0x00, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nc 0(1), 4095" - - - input: - bytes: [ 0xd4, 0x00, 0x00, 0x00, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nc 0(1), 4095(%r1)" - - - input: - bytes: [ 0xd4, 0x00, 0x00, 0x00, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nc 0(1), 4095(%r15)" - - - input: - bytes: [ 0xd4, 0x00, 0x10, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nc 0(1, %r1), 0" - - - input: - bytes: [ 0xd4, 0x00, 0xf0, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nc 0(1, %r15), 0" - - - input: - bytes: [ 0xd4, 0x00, 0x1f, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nc 4095(1, %r1), 0" - - - input: - bytes: [ 0xd4, 0x00, 0xff, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nc 4095(1, %r15), 0" - - - input: - bytes: [ 0xd4, 0xff, 0x10, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nc 0(256, %r1), 0" - - - input: - bytes: [ 0xd4, 0xff, 0xf0, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nc 0(256, %r15), 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x80 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ng %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x80 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ng %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x80 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ng %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x80 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ng %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x80 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ng %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x80 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ng %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x80 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ng %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x80 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ng %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x80 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ng %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x80 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ng %r15, 0" - - - input: - bytes: [ 0xb9, 0x80, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ngr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x80, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ngr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x80, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ngr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x80, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ngr %r7, %r8" - - - input: - bytes: [ 0x94, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ni 0, 0" - - - input: - bytes: [ 0x94, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ni 4095, 0" - - - input: - bytes: [ 0x94, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ni 0, 255" - - - input: - bytes: [ 0x94, 0x2a, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ni 0(%r1), 42" - - - input: - bytes: [ 0x94, 0x2a, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ni 0(%r15), 42" - - - input: - bytes: [ 0x94, 0x2a, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ni 4095(%r1), 42" - - - input: - bytes: [ 0x94, 0x2a, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ni 4095(%r15), 42" - - - input: - bytes: [ 0xc0, 0x0a, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nihf %r0, 0" - - - input: - bytes: [ 0xc0, 0x0a, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nihf %r0, 4294967295" - - - input: - bytes: [ 0xc0, 0xfa, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nihf %r15, 0" - - - input: - bytes: [ 0xa5, 0x04, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nihh %r0, 0" - - - input: - bytes: [ 0xa5, 0x04, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nihh %r0, 32768" - - - input: - bytes: [ 0xa5, 0x04, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nihh %r0, 65535" - - - input: - bytes: [ 0xa5, 0xf4, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nihh %r15, 0" - - - input: - bytes: [ 0xa5, 0x05, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nihl %r0, 0" - - - input: - bytes: [ 0xa5, 0x05, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nihl %r0, 32768" - - - input: - bytes: [ 0xa5, 0x05, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nihl %r0, 65535" - - - input: - bytes: [ 0xa5, 0xf5, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nihl %r15, 0" - - - input: - bytes: [ 0xc0, 0x0b, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nilf %r0, 0" - - - input: - bytes: [ 0xc0, 0x0b, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nilf %r0, 4294967295" - - - input: - bytes: [ 0xc0, 0xfb, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nilf %r15, 0" - - - input: - bytes: [ 0xa5, 0x06, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nilh %r0, 0" - - - input: - bytes: [ 0xa5, 0x06, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nilh %r0, 32768" - - - input: - bytes: [ 0xa5, 0x06, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nilh %r0, 65535" - - - input: - bytes: [ 0xa5, 0xf6, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nilh %r15, 0" - - - input: - bytes: [ 0xa5, 0x07, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nill %r0, 0" - - - input: - bytes: [ 0xa5, 0x07, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nill %r0, 32768" - - - input: - bytes: [ 0xa5, 0x07, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nill %r0, 65535" - - - input: - bytes: [ 0xa5, 0xf7, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nill %r15, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "niy -524288, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "niy -1, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "niy 0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "niy 1, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "niy 524287, 0" - - - input: - bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "niy 0, 255" - - - input: - bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "niy 0(%r1), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "niy 0(%r15), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "niy 524287(%r1), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "niy 524287(%r15), 42" - - - input: - bytes: [ 0x14, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nr %r0, %r0" - - - input: - bytes: [ 0x14, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nr %r0, %r15" - - - input: - bytes: [ 0x14, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nr %r15, %r0" - - - input: - bytes: [ 0x14, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "nr %r7, %r8" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ny %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ny %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ny %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ny %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ny %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ny %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ny %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ny %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ny %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ny %r15, 0" - - - input: - bytes: [ 0x56, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "o %r0, 0" - - - input: - bytes: [ 0x56, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "o %r0, 4095" - - - input: - bytes: [ 0x56, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "o %r0, 0(%r1)" - - - input: - bytes: [ 0x56, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "o %r0, 0(%r15)" - - - input: - bytes: [ 0x56, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "o %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x56, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "o %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x56, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "o %r15, 0" - - - input: - bytes: [ 0xd6, 0x00, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oc 0(1), 0" - - - input: - bytes: [ 0xd6, 0x00, 0x00, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oc 0(1), 0(%r1)" - - - input: - bytes: [ 0xd6, 0x00, 0x00, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oc 0(1), 0(%r15)" - - - input: - bytes: [ 0xd6, 0x00, 0x00, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oc 0(1), 4095" - - - input: - bytes: [ 0xd6, 0x00, 0x00, 0x00, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oc 0(1), 4095(%r1)" - - - input: - bytes: [ 0xd6, 0x00, 0x00, 0x00, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oc 0(1), 4095(%r15)" - - - input: - bytes: [ 0xd6, 0x00, 0x10, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oc 0(1, %r1), 0" - - - input: - bytes: [ 0xd6, 0x00, 0xf0, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oc 0(1, %r15), 0" - - - input: - bytes: [ 0xd6, 0x00, 0x1f, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oc 4095(1, %r1), 0" - - - input: - bytes: [ 0xd6, 0x00, 0xff, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oc 4095(1, %r15), 0" - - - input: - bytes: [ 0xd6, 0xff, 0x10, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oc 0(256, %r1), 0" - - - input: - bytes: [ 0xd6, 0xff, 0xf0, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oc 0(256, %r15), 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x81 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "og %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x81 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "og %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x81 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "og %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x81 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "og %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x81 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "og %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x81 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "og %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x81 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "og %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x81 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "og %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x81 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "og %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x81 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "og %r15, 0" - - - input: - bytes: [ 0xb9, 0x81, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ogr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x81, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ogr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x81, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ogr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x81, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ogr %r7, %r8" - - - input: - bytes: [ 0x96, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oi 0, 0" - - - input: - bytes: [ 0x96, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oi 4095, 0" - - - input: - bytes: [ 0x96, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oi 0, 255" - - - input: - bytes: [ 0x96, 0x2a, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oi 0(%r1), 42" - - - input: - bytes: [ 0x96, 0x2a, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oi 0(%r15), 42" - - - input: - bytes: [ 0x96, 0x2a, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oi 4095(%r1), 42" - - - input: - bytes: [ 0x96, 0x2a, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oi 4095(%r15), 42" - - - input: - bytes: [ 0xc0, 0x0c, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oihf %r0, 0" - - - input: - bytes: [ 0xc0, 0x0c, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oihf %r0, 4294967295" - - - input: - bytes: [ 0xc0, 0xfc, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oihf %r15, 0" - - - input: - bytes: [ 0xa5, 0x08, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oihh %r0, 0" - - - input: - bytes: [ 0xa5, 0x08, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oihh %r0, 32768" - - - input: - bytes: [ 0xa5, 0x08, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oihh %r0, 65535" - - - input: - bytes: [ 0xa5, 0xf8, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oihh %r15, 0" - - - input: - bytes: [ 0xa5, 0x09, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oihl %r0, 0" - - - input: - bytes: [ 0xa5, 0x09, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oihl %r0, 32768" - - - input: - bytes: [ 0xa5, 0x09, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oihl %r0, 65535" - - - input: - bytes: [ 0xa5, 0xf9, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oihl %r15, 0" - - - input: - bytes: [ 0xc0, 0x0d, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oilf %r0, 0" - - - input: - bytes: [ 0xc0, 0x0d, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oilf %r0, 4294967295" - - - input: - bytes: [ 0xc0, 0xfd, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oilf %r15, 0" - - - input: - bytes: [ 0xa5, 0x0a, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oilh %r0, 0" - - - input: - bytes: [ 0xa5, 0x0a, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oilh %r0, 32768" - - - input: - bytes: [ 0xa5, 0x0a, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oilh %r0, 65535" - - - input: - bytes: [ 0xa5, 0xfa, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oilh %r15, 0" - - - input: - bytes: [ 0xa5, 0x0b, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oill %r0, 0" - - - input: - bytes: [ 0xa5, 0x0b, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oill %r0, 32768" - - - input: - bytes: [ 0xa5, 0x0b, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oill %r0, 65535" - - - input: - bytes: [ 0xa5, 0xfb, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oill %r15, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oiy -524288, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oiy -1, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oiy 0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oiy 1, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oiy 524287, 0" - - - input: - bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oiy 0, 255" - - - input: - bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oiy 0(%r1), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oiy 0(%r15), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oiy 524287(%r1), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oiy 524287(%r15), 42" - - - input: - bytes: [ 0x16, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "or %r0, %r0" - - - input: - bytes: [ 0x16, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "or %r0, %r15" - - - input: - bytes: [ 0x16, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "or %r15, %r0" - - - input: - bytes: [ 0x16, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "or %r7, %r8" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oy %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oy %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oy %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oy %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oy %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oy %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oy %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oy %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oy %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "oy %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x36 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "pfd 0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x36 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "pfd 0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x36 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "pfd 0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x36 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "pfd 0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x36 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "pfd 0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x36 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "pfd 0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x36 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "pfd 0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x36 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "pfd 0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x36 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "pfd 0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x36 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "pfd 15, 0" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risbg %r0, %r0, 0, 0, 0" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risbg %r0, %r0, 0, 0, 63" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risbg %r0, %r0, 0, 255, 0" - - - input: - bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risbg %r0, %r0, 255, 0, 0" - - - input: - bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risbg %r0, %r15, 0, 0, 0" - - - input: - bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risbg %r15, %r0, 0, 0, 0" - - - input: - bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x55 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "risbg %r4, %r5, 6, 7, 8" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rnsbg %r0, %r0, 0, 0, 0" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rnsbg %r0, %r0, 0, 0, 63" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rnsbg %r0, %r0, 0, 255, 0" - - - input: - bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rnsbg %r0, %r0, 255, 0, 0" - - - input: - bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rnsbg %r0, %r15, 0, 0, 0" - - - input: - bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rnsbg %r15, %r0, 0, 0, 0" - - - input: - bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x54 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rnsbg %r4, %r5, 6, 7, 8" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rosbg %r0, %r0, 0, 0, 0" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rosbg %r0, %r0, 0, 0, 63" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rosbg %r0, %r0, 0, 255, 0" - - - input: - bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rosbg %r0, %r0, 255, 0, 0" - - - input: - bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rosbg %r0, %r15, 0, 0, 0" - - - input: - bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rosbg %r15, %r0, 0, 0, 0" - - - input: - bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x56 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rosbg %r4, %r5, 6, 7, 8" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rxsbg %r0, %r0, 0, 0, 0" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rxsbg %r0, %r0, 0, 0, 63" - - - input: - bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rxsbg %r0, %r0, 0, 255, 0" - - - input: - bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rxsbg %r0, %r0, 255, 0, 0" - - - input: - bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rxsbg %r0, %r15, 0, 0, 0" - - - input: - bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rxsbg %r15, %r0, 0, 0, 0" - - - input: - bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rxsbg %r4, %r5, 6, 7, 8" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rll %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rll %r15, %r1, 0" - - - input: - bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rll %r1, %r15, 0" - - - input: - bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rll %r15, %r15, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rll %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rll %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rll %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rll %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rll %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rll %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rll %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x1d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rll %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rllg %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rllg %r15, %r1, 0" - - - input: - bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rllg %r1, %r15, 0" - - - input: - bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rllg %r15, %r15, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rllg %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rllg %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rllg %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rllg %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rllg %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rllg %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rllg %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x1c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "rllg %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0x5b, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "s %r0, 0" - - - input: - bytes: [ 0x5b, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "s %r0, 4095" - - - input: - bytes: [ 0x5b, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "s %r0, 0(%r1)" - - - input: - bytes: [ 0x5b, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "s %r0, 0(%r15)" - - - input: - bytes: [ 0x5b, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "s %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x5b, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "s %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x5b, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "s %r15, 0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sdb %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sdb %f0, 4095" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sdb %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sdb %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sdb %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sdb %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sdb %f15, 0" - - - input: - bytes: [ 0xb3, 0x1b, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sdbr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x1b, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sdbr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x1b, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sdbr %f7, %f8" - - - input: - bytes: [ 0xb3, 0x1b, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sdbr %f15, %f0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "seb %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "seb %f0, 4095" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "seb %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "seb %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "seb %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "seb %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "seb %f15, 0" - - - input: - bytes: [ 0xb3, 0x0b, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sebr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x0b, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sebr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x0b, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sebr %f7, %f8" - - - input: - bytes: [ 0xb3, 0x0b, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sebr %f15, %f0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sg %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sg %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sg %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sg %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sg %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sg %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sg %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sg %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sg %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x09 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sg %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x19 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgf %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x19 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgf %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x19 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgf %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x19 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgf %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x19 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgf %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x19 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgf %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x19 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgf %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x19 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgf %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x19 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgf %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x19 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgf %r15, 0" - - - input: - bytes: [ 0xb9, 0x19, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgfr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x19, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgfr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x19, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgfr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x19, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgfr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x09, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x09, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x09, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x09, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sgr %r7, %r8" - - - input: - bytes: [ 0x4b, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sh %r0, 0" - - - input: - bytes: [ 0x4b, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sh %r0, 4095" - - - input: - bytes: [ 0x4b, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sh %r0, 0(%r1)" - - - input: - bytes: [ 0x4b, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sh %r0, 0(%r15)" - - - input: - bytes: [ 0x4b, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sh %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x4b, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sh %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x4b, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sh %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x7b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "shy %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x7b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "shy %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x7b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "shy %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x7b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "shy %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x7b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "shy %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x7b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "shy %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x7b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "shy %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x7b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "shy %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x7b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "shy %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x7b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "shy %r15, 0" - - - input: - bytes: [ 0x5f, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sl %r0, 0" - - - input: - bytes: [ 0x5f, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sl %r0, 4095" - - - input: - bytes: [ 0x5f, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sl %r0, 0(%r1)" - - - input: - bytes: [ 0x5f, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sl %r0, 0(%r15)" - - - input: - bytes: [ 0x5f, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sl %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x5f, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sl %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x5f, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sl %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x99 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slb %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x99 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slb %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x99 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slb %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x99 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slb %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x99 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slb %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x99 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slb %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x99 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slb %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x99 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slb %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x99 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slb %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x99 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slb %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x89 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slbg %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x89 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slbg %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x89 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slbg %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x89 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slbg %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x89 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slbg %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x89 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slbg %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x89 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slbg %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x89 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slbg %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x89 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slbg %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x89 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slbg %r15, 0" - - - input: - bytes: [ 0xb9, 0x89, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slbgr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x89, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slbgr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x89, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slbgr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x89, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slbgr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x99, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slbr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x99, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slbr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x99, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slbr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x99, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slbr %r7, %r8" - - - input: - bytes: [ 0xc2, 0x05, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slfi %r0, 0" - - - input: - bytes: [ 0xc2, 0x05, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slfi %r0, 4294967295" - - - input: - bytes: [ 0xc2, 0xf5, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slfi %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slg %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slg %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slg %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slg %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slg %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slg %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slg %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slg %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slg %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x0b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slg %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgf %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgf %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgf %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgf %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgf %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgf %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgf %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgf %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgf %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x1b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgf %r15, 0" - - - input: - bytes: [ 0xc2, 0x04, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgfi %r0, 0" - - - input: - bytes: [ 0xc2, 0x04, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgfi %r0, 4294967295" - - - input: - bytes: [ 0xc2, 0xf4, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgfi %r15, 0" - - - input: - bytes: [ 0xb9, 0x1b, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgfr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x1b, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgfr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x1b, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgfr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x1b, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgfr %r7, %r8" - - - input: - bytes: [ 0xb9, 0x0b, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x0b, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x0b, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x0b, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slgr %r7, %r8" - - - input: - bytes: [ 0x89, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sll %r0, 0" - - - input: - bytes: [ 0x89, 0x70, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sll %r7, 0" - - - input: - bytes: [ 0x89, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sll %r15, 0" - - - input: - bytes: [ 0x89, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sll %r0, 4095" - - - input: - bytes: [ 0x89, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sll %r0, 0(%r1)" - - - input: - bytes: [ 0x89, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sll %r0, 0(%r15)" - - - input: - bytes: [ 0x89, 0x00, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sll %r0, 4095(%r1)" - - - input: - bytes: [ 0x89, 0x00, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sll %r0, 4095(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllg %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllg %r15, %r1, 0" - - - input: - bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllg %r1, %r15, 0" - - - input: - bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllg %r15, %r15, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllg %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllg %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllg %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllg %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllg %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllg %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllg %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sllg %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0x1f, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slr %r0, %r0" - - - input: - bytes: [ 0x1f, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slr %r0, %r15" - - - input: - bytes: [ 0x1f, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slr %r15, %r0" - - - input: - bytes: [ 0x1f, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "slr %r7, %r8" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x5f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sly %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x5f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sly %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x5f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sly %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x5f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sly %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x5f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sly %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x5f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sly %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x5f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sly %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x5f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sly %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x5f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sly %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x5f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sly %r15, 0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x15 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqdb %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x15 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqdb %f0, 4095" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x15 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqdb %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x15 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqdb %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x15 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqdb %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x15 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqdb %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x15 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqdb %f15, 0" - - - input: - bytes: [ 0xb3, 0x15, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqdbr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x15, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqdbr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x15, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqdbr %f7, %f8" - - - input: - bytes: [ 0xb3, 0x15, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqdbr %f15, %f0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqeb %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqeb %f0, 4095" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqeb %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqeb %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqeb %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqeb %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x14 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqeb %f15, 0" - - - input: - bytes: [ 0xb3, 0x14, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqebr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x14, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqebr %f0, %f15" - - - input: - bytes: [ 0xb3, 0x14, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqebr %f7, %f8" - - - input: - bytes: [ 0xb3, 0x14, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqebr %f15, %f0" - - - input: - bytes: [ 0xb3, 0x16, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqxbr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x16, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqxbr %f0, %f13" - - - input: - bytes: [ 0xb3, 0x16, 0x00, 0x88 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqxbr %f8, %f8" - - - input: - bytes: [ 0xb3, 0x16, 0x00, 0xd0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sqxbr %f13, %f0" - - - input: - bytes: [ 0x1b, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sr %r0, %r0" - - - input: - bytes: [ 0x1b, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sr %r0, %r15" - - - input: - bytes: [ 0x1b, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sr %r15, %r0" - - - input: - bytes: [ 0x1b, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sr %r7, %r8" - - - input: - bytes: [ 0x8a, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sra %r0, 0" - - - input: - bytes: [ 0x8a, 0x70, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sra %r7, 0" - - - input: - bytes: [ 0x8a, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sra %r15, 0" - - - input: - bytes: [ 0x8a, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sra %r0, 4095" - - - input: - bytes: [ 0x8a, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sra %r0, 0(%r1)" - - - input: - bytes: [ 0x8a, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sra %r0, 0(%r15)" - - - input: - bytes: [ 0x8a, 0x00, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sra %r0, 4095(%r1)" - - - input: - bytes: [ 0x8a, 0x00, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sra %r0, 4095(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srag %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srag %r15, %r1, 0" - - - input: - bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srag %r1, %r15, 0" - - - input: - bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srag %r15, %r15, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srag %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srag %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srag %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srag %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srag %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srag %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srag %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x0a ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srag %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0x88, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srl %r0, 0" - - - input: - bytes: [ 0x88, 0x70, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srl %r7, 0" - - - input: - bytes: [ 0x88, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srl %r15, 0" - - - input: - bytes: [ 0x88, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srl %r0, 4095" - - - input: - bytes: [ 0x88, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srl %r0, 0(%r1)" - - - input: - bytes: [ 0x88, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srl %r0, 0(%r15)" - - - input: - bytes: [ 0x88, 0x00, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srl %r0, 4095(%r1)" - - - input: - bytes: [ 0x88, 0x00, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srl %r0, 4095(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlg %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlg %r15, %r1, 0" - - - input: - bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlg %r1, %r15, 0" - - - input: - bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlg %r15, %r15, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlg %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlg %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlg %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlg %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlg %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlg %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlg %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x0c ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srlg %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0xb2, 0x5e, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srst %r0, %r0" - - - input: - bytes: [ 0xb2, 0x5e, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srst %r0, %r15" - - - input: - bytes: [ 0xb2, 0x5e, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srst %r15, %r0" - - - input: - bytes: [ 0xb2, 0x5e, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "srst %r7, %r8" - - - input: - bytes: [ 0x50, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "st %r0, 0" - - - input: - bytes: [ 0x50, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "st %r0, 4095" - - - input: - bytes: [ 0x50, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "st %r0, 0(%r1)" - - - input: - bytes: [ 0x50, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "st %r0, 0(%r15)" - - - input: - bytes: [ 0x50, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "st %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x50, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "st %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x50, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "st %r15, 0" - - - input: - bytes: [ 0x42, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stc %r0, 0" - - - input: - bytes: [ 0x42, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stc %r0, 4095" - - - input: - bytes: [ 0x42, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stc %r0, 0(%r1)" - - - input: - bytes: [ 0x42, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stc %r0, 0(%r15)" - - - input: - bytes: [ 0x42, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stc %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x42, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stc %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x42, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stc %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x72 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stcy %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x72 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stcy %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x72 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stcy %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x72 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stcy %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x72 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stcy %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x72 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stcy %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x72 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stcy %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x72 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stcy %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x72 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stcy %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x72 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stcy %r15, 0" - - - input: - bytes: [ 0x60, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "std %f0, 0" - - - input: - bytes: [ 0x60, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "std %f0, 4095" - - - input: - bytes: [ 0x60, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "std %f0, 0(%r1)" - - - input: - bytes: [ 0x60, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "std %f0, 0(%r15)" - - - input: - bytes: [ 0x60, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "std %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x60, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "std %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x60, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "std %f15, 0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x80, 0x67 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stdy %f0, -524288" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0xff, 0x67 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stdy %f0, -1" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x67 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stdy %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x01, 0x00, 0x67 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stdy %f0, 1" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x7f, 0x67 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stdy %f0, 524287" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x67 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stdy %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x67 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stdy %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x7f, 0x67 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stdy %f0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x7f, 0x67 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stdy %f0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x67 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stdy %f15, 0" - - - input: - bytes: [ 0x70, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ste %f0, 0" - - - input: - bytes: [ 0x70, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ste %f0, 4095" - - - input: - bytes: [ 0x70, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ste %f0, 0(%r1)" - - - input: - bytes: [ 0x70, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ste %f0, 0(%r15)" - - - input: - bytes: [ 0x70, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ste %f0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x70, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ste %f0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x70, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ste %f15, 0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x80, 0x66 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stey %f0, -524288" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0xff, 0x66 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stey %f0, -1" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x66 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stey %f0, 0" - - - input: - bytes: [ 0xed, 0x00, 0x00, 0x01, 0x00, 0x66 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stey %f0, 1" - - - input: - bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x7f, 0x66 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stey %f0, 524287" - - - input: - bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x66 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stey %f0, 0(%r1)" - - - input: - bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x66 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stey %f0, 0(%r15)" - - - input: - bytes: [ 0xed, 0x01, 0xff, 0xff, 0x7f, 0x66 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stey %f0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x7f, 0x66 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stey %f0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x66 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stey %f15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stg %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stg %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stg %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stg %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stg %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stg %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stg %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stg %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stg %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stg %r15, 0" - - - input: - bytes: [ 0x40, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sth %r0, 0" - - - input: - bytes: [ 0x40, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sth %r0, 4095" - - - input: - bytes: [ 0x40, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sth %r0, 0(%r1)" - - - input: - bytes: [ 0x40, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sth %r0, 0(%r15)" - - - input: - bytes: [ 0x40, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sth %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x40, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sth %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x40, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sth %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x70 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthy %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x70 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthy %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x70 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthy %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x70 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthy %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x70 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthy %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x70 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthy %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x70 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthy %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x70 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthy %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x70 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthy %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x70 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sthy %r15, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stmg %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stmg %r0, %r15, 0" - - - input: - bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stmg %r14, %r15, 0" - - - input: - bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stmg %r15, %r15, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stmg %r0, %r0, -524288" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stmg %r0, %r0, -1" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stmg %r0, %r0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stmg %r0, %r0, 1" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stmg %r0, %r0, 524287" - - - input: - bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stmg %r0, %r0, 0(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stmg %r0, %r0, 0(%r15)" - - - input: - bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stmg %r0, %r0, 524287(%r1)" - - - input: - bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x24 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "stmg %r0, %r0, 524287(%r15)" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x3e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strv %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x3e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strv %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x3e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strv %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x3e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strv %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x3e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strv %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x3e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strv %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x3e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strv %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x3e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strv %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x3e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strv %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x3e ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strv %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x2f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strvg %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x2f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strvg %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x2f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strvg %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x2f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strvg %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x2f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strvg %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x2f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strvg %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x2f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strvg %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x2f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strvg %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x2f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strvg %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x2f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "strvg %r15, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x50 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sty %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x50 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sty %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x50 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sty %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x50 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sty %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x50 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sty %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x50 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sty %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x50 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sty %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x50 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sty %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x50 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sty %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x50 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sty %r15, 0" - - - input: - bytes: [ 0xb3, 0x4b, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sxbr %f0, %f0" - - - input: - bytes: [ 0xb3, 0x4b, 0x00, 0x0d ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sxbr %f0, %f13" - - - input: - bytes: [ 0xb3, 0x4b, 0x00, 0x88 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sxbr %f8, %f8" - - - input: - bytes: [ 0xb3, 0x4b, 0x00, 0xd0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sxbr %f13, %f0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x5b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sy %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x5b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sy %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x5b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sy %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x5b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sy %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x5b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sy %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x5b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sy %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x5b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sy %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x5b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sy %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x5b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sy %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x5b ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "sy %r15, 0" - - - input: - bytes: [ 0x91, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tm 0, 0" - - - input: - bytes: [ 0x91, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tm 4095, 0" - - - input: - bytes: [ 0x91, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tm 0, 255" - - - input: - bytes: [ 0x91, 0x2a, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tm 0(%r1), 42" - - - input: - bytes: [ 0x91, 0x2a, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tm 0(%r15), 42" - - - input: - bytes: [ 0x91, 0x2a, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tm 4095(%r1), 42" - - - input: - bytes: [ 0x91, 0x2a, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tm 4095(%r15), 42" - - - input: - bytes: [ 0xa7, 0x02, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmhh %r0, 0" - - - input: - bytes: [ 0xa7, 0x02, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmhh %r0, 32768" - - - input: - bytes: [ 0xa7, 0x02, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmhh %r0, 65535" - - - input: - bytes: [ 0xa7, 0xf2, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmhh %r15, 0" - - - input: - bytes: [ 0xa7, 0x03, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmhl %r0, 0" - - - input: - bytes: [ 0xa7, 0x03, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmhl %r0, 32768" - - - input: - bytes: [ 0xa7, 0x03, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmhl %r0, 65535" - - - input: - bytes: [ 0xa7, 0xf3, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmhl %r15, 0" - - - input: - bytes: [ 0xa7, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmlh %r0, 0" - - - input: - bytes: [ 0xa7, 0x00, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmlh %r0, 32768" - - - input: - bytes: [ 0xa7, 0x00, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmlh %r0, 65535" - - - input: - bytes: [ 0xa7, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmlh %r15, 0" - - - input: - bytes: [ 0xa7, 0x01, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmll %r0, 0" - - - input: - bytes: [ 0xa7, 0x01, 0x80, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmll %r0, 32768" - - - input: - bytes: [ 0xa7, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmll %r0, 65535" - - - input: - bytes: [ 0xa7, 0xf1, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmll %r15, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmy -524288, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmy -1, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmy 0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmy 1, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmy 524287, 0" - - - input: - bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmy 0, 255" - - - input: - bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmy 0(%r1), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmy 0(%r15), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmy 524287(%r1), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x51 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "tmy 524287(%r15), 42" - - - input: - bytes: [ 0x57, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "x %r0, 0" - - - input: - bytes: [ 0x57, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "x %r0, 4095" - - - input: - bytes: [ 0x57, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "x %r0, 0(%r1)" - - - input: - bytes: [ 0x57, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "x %r0, 0(%r15)" - - - input: - bytes: [ 0x57, 0x01, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "x %r0, 4095(%r1, %r15)" - - - input: - bytes: [ 0x57, 0x0f, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "x %r0, 4095(%r15, %r1)" - - - input: - bytes: [ 0x57, 0xf0, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "x %r15, 0" - - - input: - bytes: [ 0xd7, 0x00, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xc 0(1), 0" - - - input: - bytes: [ 0xd7, 0x00, 0x00, 0x00, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xc 0(1), 0(%r1)" - - - input: - bytes: [ 0xd7, 0x00, 0x00, 0x00, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xc 0(1), 0(%r15)" - - - input: - bytes: [ 0xd7, 0x00, 0x00, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xc 0(1), 4095" - - - input: - bytes: [ 0xd7, 0x00, 0x00, 0x00, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xc 0(1), 4095(%r1)" - - - input: - bytes: [ 0xd7, 0x00, 0x00, 0x00, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xc 0(1), 4095(%r15)" - - - input: - bytes: [ 0xd7, 0x00, 0x10, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xc 0(1, %r1), 0" - - - input: - bytes: [ 0xd7, 0x00, 0xf0, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xc 0(1, %r15), 0" - - - input: - bytes: [ 0xd7, 0x00, 0x1f, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xc 4095(1, %r1), 0" - - - input: - bytes: [ 0xd7, 0x00, 0xff, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xc 4095(1, %r15), 0" - - - input: - bytes: [ 0xd7, 0xff, 0x10, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xc 0(256, %r1), 0" - - - input: - bytes: [ 0xd7, 0xff, 0xf0, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xc 0(256, %r15), 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x82 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xg %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x82 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xg %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x82 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xg %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x82 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xg %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x82 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xg %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x82 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xg %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x82 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xg %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x82 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xg %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x82 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xg %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x82 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xg %r15, 0" - - - input: - bytes: [ 0xb9, 0x82, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xgr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x82, 0x00, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xgr %r0, %r15" - - - input: - bytes: [ 0xb9, 0x82, 0x00, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xgr %r15, %r0" - - - input: - bytes: [ 0xb9, 0x82, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xgr %r7, %r8" - - - input: - bytes: [ 0x97, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xi 0, 0" - - - input: - bytes: [ 0x97, 0x00, 0x0f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xi 4095, 0" - - - input: - bytes: [ 0x97, 0xff, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xi 0, 255" - - - input: - bytes: [ 0x97, 0x2a, 0x10, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xi 0(%r1), 42" - - - input: - bytes: [ 0x97, 0x2a, 0xf0, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xi 0(%r15), 42" - - - input: - bytes: [ 0x97, 0x2a, 0x1f, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xi 4095(%r1), 42" - - - input: - bytes: [ 0x97, 0x2a, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xi 4095(%r15), 42" - - - input: - bytes: [ 0xc0, 0x06, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xihf %r0, 0" - - - input: - bytes: [ 0xc0, 0x06, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xihf %r0, 4294967295" - - - input: - bytes: [ 0xc0, 0xf6, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xihf %r15, 0" - - - input: - bytes: [ 0xc0, 0x07, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xilf %r0, 0" - - - input: - bytes: [ 0xc0, 0x07, 0xff, 0xff, 0xff, 0xff ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xilf %r0, 4294967295" - - - input: - bytes: [ 0xc0, 0xf7, 0x00, 0x00, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xilf %r15, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xiy -524288, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xiy -1, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xiy 0, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xiy 1, 0" - - - input: - bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xiy 524287, 0" - - - input: - bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xiy 0, 255" - - - input: - bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xiy 0(%r1), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xiy 0(%r15), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xiy 524287(%r1), 42" - - - input: - bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xiy 524287(%r15), 42" - - - input: - bytes: [ 0x17, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xr %r0, %r0" - - - input: - bytes: [ 0x17, 0x0f ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xr %r0, %r15" - - - input: - bytes: [ 0x17, 0xf0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xr %r15, %r0" - - - input: - bytes: [ 0x17, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xr %r7, %r8" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xy %r0, -524288" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xy %r0, -1" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xy %r0, 0" - - - input: - bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xy %r0, 1" - - - input: - bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xy %r0, 524287" - - - input: - bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xy %r0, 0(%r1)" - - - input: - bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xy %r0, 0(%r15)" - - - input: - bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xy %r0, 524287(%r1, %r15)" - - - input: - bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xy %r0, 524287(%r15, %r1)" - - - input: - bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x57 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "xy %r15, 0" diff --git a/tests/MC/SystemZ/insns-z13.txt.yaml b/tests/MC/SystemZ/insns-z13.txt.yaml new file mode 100644 index 0000000000..ebffb1aaa6 --- /dev/null +++ b/tests/MC/SystemZ/insns-z13.txt.yaml @@ -0,0 +1,15890 @@ +test_cases: + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdpt %f0, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdpt %f15, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x0f, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdpt %f0, 0(1), 15" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdpt %f0, 0(1,%r1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdpt %f0, 0(1,%r15), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x1f, 0xff, 0x00, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdpt %f0, 4095(1,%r1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0xff, 0xff, 0x00, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdpt %f0, 4095(1,%r15), 0" + + - + input: + bytes: [ 0xed, 0xff, 0x10, 0x00, 0x00, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdpt %f0, 0(256,%r1), 0" + + - + input: + bytes: [ 0xed, 0xff, 0xf0, 0x00, 0x00, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdpt %f0, 0(256,%r15), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpdt %f0, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpdt %f15, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x0f, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpdt %f0, 0(1), 15" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpdt %f0, 0(1,%r1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpdt %f0, 0(1,%r15), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x1f, 0xff, 0x00, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpdt %f0, 4095(1,%r1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0xff, 0xff, 0x00, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpdt %f0, 4095(1,%r15), 0" + + - + input: + bytes: [ 0xed, 0xff, 0x10, 0x00, 0x00, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpdt %f0, 0(256,%r1), 0" + + - + input: + bytes: [ 0xed, 0xff, 0xf0, 0x00, 0x00, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpdt %f0, 0(256,%r15), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpxt %f0, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xd0, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpxt %f13, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x0f, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpxt %f0, 0(1), 15" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpxt %f0, 0(1,%r1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpxt %f0, 0(1,%r15), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x1f, 0xff, 0x00, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpxt %f0, 4095(1,%r1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0xff, 0xff, 0x00, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpxt %f0, 4095(1,%r15), 0" + + - + input: + bytes: [ 0xed, 0xff, 0x10, 0x00, 0x00, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpxt %f0, 0(256,%r1), 0" + + - + input: + bytes: [ 0xed, 0xff, 0xf0, 0x00, 0x00, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpxt %f0, 0(256,%r15), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxpt %f0, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xd0, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxpt %f13, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x0f, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxpt %f0, 0(1), 15" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxpt %f0, 0(1,%r1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxpt %f0, 0(1,%r15), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x1f, 0xff, 0x00, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxpt %f0, 4095(1,%r1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0xff, 0xff, 0x00, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxpt %f0, 4095(1,%r15), 0" + + - + input: + bytes: [ 0xed, 0xff, 0x10, 0x00, 0x00, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxpt %f0, 0(256,%r1), 0" + + - + input: + bytes: [ 0xed, 0xff, 0xf0, 0x00, 0x00, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxpt %f0, 0(256,%r15), 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x27 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcbb %r0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xf0, 0x27 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcbb %r0, 0, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x0f, 0xff, 0x00, 0x27 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcbb %r0, 4095, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x00, 0x27 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcbb %r0, 0(%r15), 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x10, 0x00, 0x00, 0x27 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcbb %r0, 0(%r15,%r1), 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x00, 0x27 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcbb %r15, 0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x45, 0x67, 0x80, 0x27 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcbb %r2, 1383(%r3,%r4), 8" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llzrgf %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llzrgf %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llzrgf %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llzrgf %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llzrgf %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llzrgf %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llzrgf %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llzrgf %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llzrgf %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llzrgf %r15, 0" + + - + input: + bytes: [ 0xec, 0xb0, 0x00, 0x2a, 0x00, 0x42 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochi %r11, 42, 0" + + - + input: + bytes: [ 0xec, 0xb1, 0x00, 0x2a, 0x00, 0x42 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochio %r11, 42" + + - + input: + bytes: [ 0xec, 0xb2, 0x00, 0x2a, 0x00, 0x42 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochih %r11, 42" + + - + input: + bytes: [ 0xec, 0xb3, 0x00, 0x2a, 0x00, 0x42 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochinle %r11, 42" + + - + input: + bytes: [ 0xec, 0xb4, 0xff, 0xff, 0x00, 0x42 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochil %r11, -1" + + - + input: + bytes: [ 0xec, 0xb5, 0x00, 0x2a, 0x00, 0x42 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochinhe %r11, 42" + + - + input: + bytes: [ 0xec, 0xb6, 0xff, 0xff, 0x00, 0x42 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochilh %r11, -1" + + - + input: + bytes: [ 0xec, 0xb7, 0x00, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochine %r11, 0" + + - + input: + bytes: [ 0xec, 0xb8, 0x00, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochie %r11, 0" + + - + input: + bytes: [ 0xec, 0xb9, 0x00, 0x2a, 0x00, 0x42 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochinlh %r11, 42" + + - + input: + bytes: [ 0xec, 0xba, 0x00, 0xff, 0x00, 0x42 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochihe %r11, 255" + + - + input: + bytes: [ 0xec, 0xbb, 0x00, 0xff, 0x00, 0x42 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochinl %r11, 255" + + - + input: + bytes: [ 0xec, 0xbc, 0x7f, 0xff, 0x00, 0x42 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochile %r11, 32767" + + - + input: + bytes: [ 0xec, 0xbd, 0x7f, 0xff, 0x00, 0x42 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochinh %r11, 32767" + + - + input: + bytes: [ 0xec, 0xbe, 0x7f, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochino %r11, 32512" + + - + input: + bytes: [ 0xec, 0xbf, 0x7f, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochi %r11, 32512, 15" + + - + input: + bytes: [ 0xec, 0xb0, 0x00, 0x2a, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locghi %r11, 42, 0" + + - + input: + bytes: [ 0xec, 0xb1, 0x00, 0x2a, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locghio %r11, 42" + + - + input: + bytes: [ 0xec, 0xb2, 0x00, 0x2a, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locghih %r11, 42" + + - + input: + bytes: [ 0xec, 0xb3, 0x00, 0x2a, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locghinle %r11, 42" + + - + input: + bytes: [ 0xec, 0xb4, 0xff, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locghil %r11, -1" + + - + input: + bytes: [ 0xec, 0xb5, 0x00, 0x2a, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locghinhe %r11, 42" + + - + input: + bytes: [ 0xec, 0xb6, 0xff, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locghilh %r11, -1" + + - + input: + bytes: [ 0xec, 0xb7, 0x00, 0x00, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locghine %r11, 0" + + - + input: + bytes: [ 0xec, 0xb8, 0x00, 0x00, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locghie %r11, 0" + + - + input: + bytes: [ 0xec, 0xb9, 0x00, 0x2a, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locghinlh %r11, 42" + + - + input: + bytes: [ 0xec, 0xba, 0x00, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locghihe %r11, 255" + + - + input: + bytes: [ 0xec, 0xbb, 0x00, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locghinl %r11, 255" + + - + input: + bytes: [ 0xec, 0xbc, 0x7f, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locghile %r11, 32767" + + - + input: + bytes: [ 0xec, 0xbd, 0x7f, 0xff, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locghinh %r11, 32767" + + - + input: + bytes: [ 0xec, 0xbe, 0x7f, 0x00, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locghino %r11, 32512" + + - + input: + bytes: [ 0xec, 0xbf, 0x7f, 0x00, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locghi %r11, 32512, 15" + + - + input: + bytes: [ 0xec, 0xb0, 0x00, 0x2a, 0x00, 0x4e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochhi %r11, 42, 0" + + - + input: + bytes: [ 0xec, 0xb1, 0x00, 0x2a, 0x00, 0x4e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochhio %r11, 42" + + - + input: + bytes: [ 0xec, 0xb2, 0x00, 0x2a, 0x00, 0x4e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochhih %r11, 42" + + - + input: + bytes: [ 0xec, 0xb3, 0x00, 0x2a, 0x00, 0x4e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochhinle %r11, 42" + + - + input: + bytes: [ 0xec, 0xb4, 0xff, 0xff, 0x00, 0x4e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochhil %r11, -1" + + - + input: + bytes: [ 0xec, 0xb5, 0x00, 0x2a, 0x00, 0x4e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochhinhe %r11, 42" + + - + input: + bytes: [ 0xec, 0xb6, 0xff, 0xff, 0x00, 0x4e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochhilh %r11, -1" + + - + input: + bytes: [ 0xec, 0xb7, 0x00, 0x00, 0x00, 0x4e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochhine %r11, 0" + + - + input: + bytes: [ 0xec, 0xb8, 0x00, 0x00, 0x00, 0x4e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochhie %r11, 0" + + - + input: + bytes: [ 0xec, 0xb9, 0x00, 0x2a, 0x00, 0x4e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochhinlh %r11, 42" + + - + input: + bytes: [ 0xec, 0xba, 0x00, 0xff, 0x00, 0x4e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochhihe %r11, 255" + + - + input: + bytes: [ 0xec, 0xbb, 0x00, 0xff, 0x00, 0x4e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochhinl %r11, 255" + + - + input: + bytes: [ 0xec, 0xbc, 0x7f, 0xff, 0x00, 0x4e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochhile %r11, 32767" + + - + input: + bytes: [ 0xec, 0xbd, 0x7f, 0xff, 0x00, 0x4e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochhinh %r11, 32767" + + - + input: + bytes: [ 0xec, 0xbe, 0x7f, 0x00, 0x00, 0x4e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochhino %r11, 32512" + + - + input: + bytes: [ 0xec, 0xbf, 0x7f, 0x00, 0x00, 0x4e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lochhi %r11, 32512, 15" + + - + input: + bytes: [ 0xeb, 0x70, 0x88, 0xff, 0x01, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfh %r7, 6399(%r8), 0" + + - + input: + bytes: [ 0xeb, 0x71, 0x88, 0xff, 0x01, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfho %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x72, 0x88, 0xff, 0x01, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhh %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x73, 0x88, 0xff, 0x01, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhnle %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x74, 0x88, 0xff, 0x01, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhl %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x75, 0x88, 0xff, 0x01, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhnhe %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x76, 0x88, 0xff, 0x01, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhlh %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x77, 0x88, 0xff, 0x01, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhne %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x78, 0x88, 0xff, 0x01, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhe %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x79, 0x88, 0xff, 0x01, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhnlh %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x7a, 0x88, 0xff, 0x01, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhhe %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x7b, 0x88, 0xff, 0x01, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhnl %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x7c, 0x88, 0xff, 0x01, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhle %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x7d, 0x88, 0xff, 0x01, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhnh %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x7e, 0x88, 0xff, 0x01, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhno %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x7f, 0x88, 0xff, 0x01, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfh %r7, 6399(%r8), 15" + + - + input: + bytes: [ 0xb9, 0xe0, 0x00, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhr %r11, %r3, 0" + + - + input: + bytes: [ 0xb9, 0xe0, 0x10, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhro %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe0, 0x20, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhrh %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe0, 0x30, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhrnle %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe0, 0x40, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhrl %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe0, 0x50, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhrnhe %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe0, 0x60, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhrlh %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe0, 0x70, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhrne %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe0, 0x80, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhre %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe0, 0x90, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhrnlh %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe0, 0xa0, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhrhe %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe0, 0xb0, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhrnl %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe0, 0xc0, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhrle %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe0, 0xd0, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhrnh %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe0, 0xe0, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhrno %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe0, 0xf0, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locfhr %r11, %r3, 15" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrf %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrf %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrf %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrf %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrf %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrf %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrf %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrf %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrf %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrf %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzrg %r15, 0" + + - + input: + bytes: [ 0xb9, 0x3c, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ppno %r2, %r10" + + - + input: + bytes: [ 0xb9, 0x3c, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ppno %r2, %r14" + + - + input: + bytes: [ 0xb9, 0x3c, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ppno %r14, %r2" + + - + input: + bytes: [ 0xb9, 0x3c, 0x00, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ppno %r14, %r10" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfh %r0, 0, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfh %r0, 0, 15" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfh %r0, -524288, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfh %r0, 524287, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfh %r0, 0(%r1), 0" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfh %r0, 0(%r15), 0" + + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfh %r15, 0, 0" + + - + input: + bytes: [ 0xeb, 0x11, 0x30, 0x02, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfho %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x12, 0x30, 0x02, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfhh %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x13, 0x30, 0x02, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfhnle %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x14, 0x30, 0x02, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfhl %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x15, 0x30, 0x02, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfhnhe %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x16, 0x30, 0x02, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfhlh %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x17, 0x30, 0x02, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfhne %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x18, 0x30, 0x02, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfhe %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x19, 0x30, 0x02, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfhnlh %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x1a, 0x30, 0x02, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfhhe %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x1b, 0x30, 0x02, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfhnl %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x1c, 0x30, 0x02, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfhle %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x1d, 0x30, 0x02, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfhnh %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x1e, 0x30, 0x02, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfhno %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x1f, 0x30, 0x02, 0x00, 0xe1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocfh %r1, 2(%r3), 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "va %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "va %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "va %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vab %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vab %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vab %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x0b, 0x00, 0x00, 0xbb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vac %v0, %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x34, 0x5b, 0x00, 0x65, 0xbb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vac %v3, %v20, %v5, %v22, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xfb, 0x00, 0xff, 0xbb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vac %v31, %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vacc %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vacc %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vacc %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaccb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaccb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaccb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x0b, 0x00, 0x00, 0xb9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaccc %v0, %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x34, 0x5b, 0x00, 0x65, 0xb9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaccc %v3, %v20, %v5, %v22, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xfb, 0x00, 0xff, 0xb9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaccc %v31, %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x04, 0x00, 0x00, 0xb9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vacccq %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x54, 0x00, 0x65, 0xb9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vacccq %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf4, 0x00, 0xff, 0xb9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vacccq %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaccf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaccf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaccf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaccg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaccg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaccg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vacch %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vacch %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vacch %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x40, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaccq %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x4a, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaccq %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x4e, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaccq %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x04, 0x00, 0x00, 0xbb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vacq %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x54, 0x00, 0x65, 0xbb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vacq %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf4, 0x00, 0xff, 0xbb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vacq %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vag %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vag %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vag %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vah %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vah %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vah %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x40, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaq %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x4a, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaq %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x4e, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vaq %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavg %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavg %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavg %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavgb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavgb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavgb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavgf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavgf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavgf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavgg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavgg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavgg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavgh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavgh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavgh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavgl %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavgl %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavgl %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavglb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavglb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavglb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavglf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavglf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavglf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavglg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavglg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavglg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavglh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavglh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vavglh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcdg %v0, %v0, 11, 0, 0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0xa4, 0xb8, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcdg %v19, %v14, 11, 4, 10" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0xf7, 0xbc, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcdg %v31, %v31, 11, 7, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcdgb %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0xa4, 0x38, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcdgb %v19, %v14, 4, 10" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0xf7, 0x3c, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcdgb %v31, %v31, 7, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcdlg %v0, %v0, 11, 0, 0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0xa4, 0xb8, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcdlg %v19, %v14, 11, 4, 10" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0xf7, 0xbc, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcdlg %v31, %v31, 11, 7, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcdlgb %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0xa4, 0x38, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcdlgb %v19, %v14, 4, 10" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0xf7, 0x3c, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcdlgb %v31, %v31, 7, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x90, 0xb0, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceq %v0, %v0, %v0, 11, 9" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x90, 0xba, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceq %v18, %v3, %v20, 11, 9" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x90, 0xb4, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceq %v7, %v24, %v9, 11, 9" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x90, 0xbe, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceq %v31, %v31, %v31, 11, 9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceqb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceqb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceqb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x04, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceqbs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceqf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceqf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceqf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x24, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceqfs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceqg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceqg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceqg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x34, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceqgs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceqh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceqh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceqh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x14, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vceqhs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcgd %v0, %v0, 11, 0, 0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0xa4, 0xb8, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcgd %v19, %v14, 11, 4, 10" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0xf7, 0xbc, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcgd %v31, %v31, 11, 7, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcgdb %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0xa4, 0x38, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcgdb %v19, %v14, 4, 10" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0xf7, 0x3c, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcgdb %v31, %v31, 7, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x90, 0xb0, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vch %v0, %v0, %v0, 11, 9" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x90, 0xba, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vch %v18, %v3, %v20, 11, 9" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x90, 0xb4, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vch %v7, %v24, %v9, 11, 9" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x90, 0xbe, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vch %v31, %v31, %v31, 11, 9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x04, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchbs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x24, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchfs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x34, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchgs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x14, 0xfb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchhs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x90, 0xb0, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchl %v0, %v0, %v0, 11, 9" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x90, 0xba, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchl %v18, %v3, %v20, 11, 9" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x90, 0xb4, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchl %v7, %v24, %v9, 11, 9" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x90, 0xbe, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchl %v31, %v31, %v31, 11, 9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchlb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchlb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchlb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x04, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchlbs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchlf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchlf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchlf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x24, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchlfs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchlg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchlg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchlg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x34, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchlgs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchlh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchlh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchlh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x14, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vchlhs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x66 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcksm %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x66 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcksm %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x66 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcksm %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclgd %v0, %v0, 11, 0, 0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0xa4, 0xb8, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclgd %v19, %v14, 11, 4, 10" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0xf7, 0xbc, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclgd %v31, %v31, 11, 7, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclgdb %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0xa4, 0x38, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclgdb %v19, %v14, 4, 10" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0xf7, 0x3c, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclgdb %v31, %v31, 7, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclz %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0xb8, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclz %v19, %v14, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0xbc, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclz %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclzb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x08, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclzb %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x0c, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclzb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclzf %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x28, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclzf %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x2c, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclzf %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclzg %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x38, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclzg %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x3c, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclzg %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclzh %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x18, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclzh %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x1c, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclzh %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vctz %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0xb8, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vctz %v19, %v14, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0xbc, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vctz %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vctzb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x08, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vctzb %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x0c, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vctzb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vctzf %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x28, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vctzf %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x2c, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vctzf %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vctzg %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x38, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vctzg %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x3c, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vctzg %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vctzh %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x18, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vctzh %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x1c, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vctzh %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vec %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0xb8, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vec %v19, %v14, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0xbc, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vec %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vecb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x08, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vecb %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x0c, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vecb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vecf %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x28, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vecf %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x2c, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vecf %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vecg %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x38, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vecg %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x3c, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vecg %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vech %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x18, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vech %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x1c, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vech %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vecl %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0xb8, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vecl %v19, %v14, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0xbc, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vecl %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veclb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x08, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veclb %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x0c, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veclb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veclf %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x28, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veclf %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x2c, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veclf %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veclg %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x38, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veclg %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x3c, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veclg %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veclh %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x18, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veclh %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x1c, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veclh %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verim %v0, %v0, %v0, 0, 11" + + - + input: + bytes: [ 0xe7, 0x34, 0x50, 0x67, 0xb4, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verim %v3, %v20, %v5, 103, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0xff, 0xbe, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verim %v31, %v31, %v31, 255, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verimb %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x34, 0x50, 0x67, 0x04, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verimb %v3, %v20, %v5, 103" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0xff, 0x0e, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verimb %v31, %v31, %v31, 255" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verimf %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x34, 0x50, 0x67, 0x24, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verimf %v3, %v20, %v5, 103" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0xff, 0x2e, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verimf %v31, %v31, %v31, 255" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verimg %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x34, 0x50, 0x67, 0x34, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verimg %v3, %v20, %v5, 103" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0xff, 0x3e, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verimg %v31, %v31, %v31, 255" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verimh %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x34, 0x50, 0x67, 0x14, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verimh %v3, %v20, %v5, 103" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0xff, 0x1e, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verimh %v31, %v31, %v31, 255" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x33 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verll %v0, %v0, 0, 11" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0xb4, 0x33 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verll %v12, %v18, 1110(%r3), 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0xbc, 0x33 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verll %v31, %v31, 4095(%r15), 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x33 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllb %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0x04, 0x33 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllb %v12, %v18, 1110(%r3)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x0c, 0x33 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllb %v31, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x33 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllf %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0x24, 0x33 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllf %v12, %v18, 1110(%r3)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x2c, 0x33 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllf %v31, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x33 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllg %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0x34, 0x33 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllg %v12, %v18, 1110(%r3)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x3c, 0x33 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllg %v31, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x33 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllh %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0x14, 0x33 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllh %v12, %v18, 1110(%r3)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x1c, 0x33 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllh %v31, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllv %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllv %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllv %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllvb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllvb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllvb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllvf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllvf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllvf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllvg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllvg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllvg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllvh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllvh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "verllvh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesl %v0, %v0, 0, 11" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0xb4, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesl %v12, %v18, 1110(%r3), 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0xbc, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesl %v31, %v31, 4095(%r15), 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslb %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0x04, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslb %v12, %v18, 1110(%r3)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x0c, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslb %v31, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslf %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0x24, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslf %v12, %v18, 1110(%r3)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x2c, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslf %v31, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslg %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0x34, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslg %v12, %v18, 1110(%r3)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x3c, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslg %v31, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslh %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0x14, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslh %v12, %v18, 1110(%r3)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x1c, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslh %v31, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslv %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslv %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslv %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslvb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslvb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslvb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslvf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslvf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslvf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslvg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslvg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslvg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslvh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslvh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "veslvh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesra %v0, %v0, 0, 11" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0xb4, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesra %v12, %v18, 1110(%r3), 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0xbc, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesra %v31, %v31, 4095(%r15), 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrab %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0x04, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrab %v12, %v18, 1110(%r3)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x0c, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrab %v31, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesraf %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0x24, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesraf %v12, %v18, 1110(%r3)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x2c, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesraf %v31, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrag %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0x34, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrag %v12, %v18, 1110(%r3)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x3c, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrag %v31, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrah %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0x14, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrah %v12, %v18, 1110(%r3)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x1c, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrah %v31, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrav %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrav %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrav %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesravb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesravb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesravb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesravf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesravf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesravf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesravg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesravg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesravg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesravh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesravh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesravh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrl %v0, %v0, 0, 11" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0xb4, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrl %v12, %v18, 1110(%r3), 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0xbc, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrl %v31, %v31, 4095(%r15), 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlb %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0x04, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlb %v12, %v18, 1110(%r3)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x0c, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlb %v31, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlf %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0x24, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlf %v12, %v18, 1110(%r3)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x2c, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlf %v31, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlg %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0x34, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlg %v12, %v18, 1110(%r3)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x3c, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlg %v31, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlh %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0x14, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlh %v12, %v18, 1110(%r3)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x1c, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlh %v31, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlv %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlv %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlv %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlvb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlvb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlvb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlvf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlvf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlvf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlvg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlvg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlvg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlvh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlvh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vesrlvh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x09, 0xb0, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfa %v0, %v0, %v0, 11, 9" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x09, 0xba, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfa %v18, %v3, %v20, 11, 9" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x09, 0xbe, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfa %v31, %v31, %v31, 11, 9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfadb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfadb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfadb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfae %v0, %v0, %v0, 11, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xc0, 0xb0, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfae %v0, %v0, %v0, 11, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfae %v18, %v3, %v20, 11, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x40, 0xbe, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfae %v31, %v31, %v31, 11, 4" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaeb %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xc0, 0x00, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaeb %v0, %v0, %v0, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaeb %v18, %v3, %v20, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x40, 0x0e, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaeb %v31, %v31, %v31, 4" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x90, 0x0e, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaebs %v31, %v31, %v31, 8" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x60, 0x0e, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaezb %v31, %v31, %v31, 4" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0xb0, 0x0e, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaezbs %v31, %v31, %v31, 8" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaef %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xc0, 0x20, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaef %v0, %v0, %v0, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaef %v18, %v3, %v20, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x40, 0x2e, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaef %v31, %v31, %v31, 4" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x90, 0x2e, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaefs %v31, %v31, %v31, 8" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x60, 0x2e, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaezf %v31, %v31, %v31, 4" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0xb0, 0x2e, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaezfs %v31, %v31, %v31, 8" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaeh %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xc0, 0x10, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaeh %v0, %v0, %v0, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaeh %v18, %v3, %v20, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x40, 0x1e, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaeh %v31, %v31, %v31, 4" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x90, 0x1e, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaehs %v31, %v31, %v31, 8" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x60, 0x1e, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaezh %v31, %v31, %v31, 4" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0xb0, 0x1e, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfaezhs %v31, %v31, %v31, 8" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x09, 0xb0, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfce %v0, %v0, %v0, 11, 9, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x09, 0xba, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfce %v18, %v3, %v20, 11, 9, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x09, 0xbe, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfce %v31, %v31, %v31, 11, 9, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfcedb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfcedb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfcedb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x10, 0x30, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfcedbs %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x10, 0x3a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfcedbs %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x10, 0x3e, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfcedbs %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x09, 0xb0, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfch %v0, %v0, %v0, 11, 9, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x09, 0xba, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfch %v18, %v3, %v20, 11, 9, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x09, 0xbe, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfch %v31, %v31, %v31, 11, 9, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchdb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchdb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchdb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x10, 0x30, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchdbs %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x10, 0x3a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchdbs %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x10, 0x3e, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchdbs %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x09, 0xb0, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfche %v0, %v0, %v0, 11, 9, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x09, 0xba, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfche %v18, %v3, %v20, 11, 9, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x09, 0xbe, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfche %v31, %v31, %v31, 11, 9, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchedb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchedb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchedb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x10, 0x30, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchedbs %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x10, 0x3a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchedbs %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x10, 0x3e, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchedbs %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x09, 0xb0, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfd %v0, %v0, %v0, 11, 9" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x09, 0xba, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfd %v18, %v3, %v20, 11, 9" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x09, 0xbe, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfd %v31, %v31, %v31, 11, 9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfddb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfddb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfddb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfee %v0, %v0, %v0, 11, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xc0, 0xb0, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfee %v0, %v0, %v0, 11, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfee %v18, %v3, %v20, 11, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfee %v31, %v31, %v31, 11, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeeb %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xc0, 0x00, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeeb %v0, %v0, %v0, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeeb %v18, %v3, %v20, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeeb %v31, %v31, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x04, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeebs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x20, 0x0a, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeezb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x30, 0x04, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeezbs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeef %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xc0, 0x20, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeef %v0, %v0, %v0, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeef %v18, %v3, %v20, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeef %v31, %v31, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x24, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeefs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x20, 0x2a, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeezf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x30, 0x24, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeezfs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeeh %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xc0, 0x10, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeeh %v0, %v0, %v0, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeeh %v18, %v3, %v20, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeeh %v31, %v31, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x14, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeehs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x20, 0x1a, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeezh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x30, 0x14, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeezhs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfene %v0, %v0, %v0, 11, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xc0, 0xb0, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfene %v0, %v0, %v0, 11, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfene %v18, %v3, %v20, 11, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfene %v31, %v31, %v31, 11, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeneb %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xc0, 0x00, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeneb %v0, %v0, %v0, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeneb %v18, %v3, %v20, 0" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x04, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfenebs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeneb %v31, %v31, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x20, 0x0a, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfenezb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x30, 0x04, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfenezbs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfenef %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xc0, 0x20, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfenef %v0, %v0, %v0, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfenef %v18, %v3, %v20, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfenef %v31, %v31, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x24, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfenefs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x20, 0x2a, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfenezf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x30, 0x24, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfenezfs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeneh %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xc0, 0x10, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeneh %v0, %v0, %v0, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeneh %v18, %v3, %v20, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfeneh %v31, %v31, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x14, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfenehs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x20, 0x1a, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfenezh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x30, 0x14, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfenezhs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfi %v0, %v0, 11, 0, 0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0xa4, 0xb8, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfi %v19, %v14, 11, 4, 10" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0xf7, 0xbc, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfi %v31, %v31, 11, 7, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfidb %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0xa4, 0x38, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfidb %v19, %v14, 4, 10" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0xf7, 0x3c, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfidb %v31, %v31, 7, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflcdb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x38, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflcdb %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x3c, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflcdb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x10, 0x30, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflndb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x10, 0x38, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflndb %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x10, 0x3c, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflndb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x20, 0x30, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflpdb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x20, 0x38, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflpdb %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x20, 0x3c, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflpdb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x09, 0xb0, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfm %v0, %v0, %v0, 11, 9" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x09, 0xba, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfm %v18, %v3, %v20, 11, 9" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x09, 0xbe, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfm %v31, %v31, %v31, 11, 9" + + - + input: + bytes: [ 0xe7, 0x00, 0x0b, 0x09, 0x00, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfma %v0, %v0, %v0, %v0, 9, 11" + + - + input: + bytes: [ 0xe7, 0x34, 0x5b, 0x09, 0x65, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfma %v3, %v20, %v5, %v22, 9, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xfb, 0x09, 0xff, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfma %v31, %v31, %v31, %v31, 9, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x03, 0x00, 0x00, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmadb %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x53, 0x00, 0x65, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmadb %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf3, 0x00, 0xff, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmadb %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmdb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmdb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmdb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x0b, 0x09, 0x00, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfms %v0, %v0, %v0, %v0, 9, 11" + + - + input: + bytes: [ 0xe7, 0x34, 0x5b, 0x09, 0x65, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfms %v3, %v20, %v5, %v22, 9, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xfb, 0x09, 0xff, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfms %v31, %v31, %v31, %v31, 9, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x03, 0x00, 0x00, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmsdb %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x53, 0x00, 0x65, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmsdb %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf3, 0x00, 0xff, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmsdb %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x79, 0xb0, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfpso %v0, %v0, 11, 9, 7" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x79, 0xb8, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfpso %v19, %v14, 11, 9, 7" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x79, 0xbc, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfpso %v31, %v31, 11, 9, 7" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x70, 0x30, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfpsodb %v0, %v0, 7" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x70, 0x38, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfpsodb %v19, %v14, 7" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x70, 0x3c, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfpsodb %v31, %v31, 7" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x09, 0xb0, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfs %v0, %v0, %v0, 11, 9" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x09, 0xba, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfs %v18, %v3, %v20, 11, 9" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x09, 0xbe, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfs %v31, %v31, %v31, 11, 9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfsdb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfsdb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfsdb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x09, 0xb0, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfsq %v0, %v0, 11, 9" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x09, 0xb8, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfsq %v19, %v14, 11, 9" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x09, 0xbc, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfsq %v31, %v31, 11, 9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfsqdb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x38, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfsqdb %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x3c, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfsqdb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x09, 0xb0, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vftci %v0, %v0, 0, 11, 9" + + - + input: + bytes: [ 0xe7, 0x34, 0x56, 0x79, 0xb8, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vftci %v19, %v4, 1383, 11, 9" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xf9, 0xbc, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vftci %v31, %v31, 4095, 11, 9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vftcidb %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x34, 0x56, 0x70, 0x38, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vftcidb %v19, %v4, 1383" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xf0, 0x3c, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vftcidb %v31, %v31, 4095" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x01, 0x00, 0x44 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgbm %v0, 1" + + - + input: + bytes: [ 0xe7, 0x00, 0xff, 0xfe, 0x00, 0x44 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgbm %v0, 65534" + + - + input: + bytes: [ 0xe7, 0x10, 0x12, 0x34, 0x08, 0x44 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgbm %v17, 4660" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x44 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vzero %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xff, 0xff, 0x00, 0x44 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vone %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0xff, 0xff, 0x08, 0x44 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vone %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x13 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgef %v0, 0(%v0,0), 0" + + - + input: + bytes: [ 0xe7, 0xa3, 0x73, 0xe8, 0x24, 0x13 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgef %v10, 1000(%v19,%r7), 2" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x3c, 0x13 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgef %v31, 4095(%v31,%r15), 3" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgeg %v0, 0(%v0,0), 0" + + - + input: + bytes: [ 0xe7, 0xa3, 0x73, 0xe8, 0x14, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgeg %v10, 1000(%v19,%r7), 1" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x1c, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgeg %v31, 4095(%v31,%r15), 1" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xb4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfm %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0xb4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfm %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0xb4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfm %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x0b, 0x00, 0x00, 0xbc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfma %v0, %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x34, 0x5b, 0x00, 0x65, 0xbc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfma %v3, %v20, %v5, %v22, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xfb, 0x00, 0xff, 0xbc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfma %v31, %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xbc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmab %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x50, 0x00, 0x65, 0xbc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmab %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xff, 0xbc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmab %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0x00, 0xbc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmaf %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x52, 0x00, 0x65, 0xbc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmaf %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf2, 0x00, 0xff, 0xbc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmaf %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x03, 0x00, 0x00, 0xbc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmag %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x53, 0x00, 0x65, 0xbc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmag %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf3, 0x00, 0xff, 0xbc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmag %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x01, 0x00, 0x00, 0xbc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmah %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x51, 0x00, 0x65, 0xbc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmah %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf1, 0x00, 0xff, 0xbc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmah %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xb4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xb4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xb4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xb4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xb4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xb4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xb4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xb4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xb4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xb4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xb4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xb4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgfmh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgm %v0, 0, 0, 11" + + - + input: + bytes: [ 0xe7, 0x60, 0x37, 0x42, 0xb8, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgm %v22, 55, 66, 11" + + - + input: + bytes: [ 0xe7, 0xf0, 0xff, 0xff, 0xb8, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgm %v31, 255, 255, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgmb %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x60, 0x37, 0x42, 0x08, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgmb %v22, 55, 66" + + - + input: + bytes: [ 0xe7, 0xf0, 0xff, 0xff, 0x08, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgmb %v31, 255, 255" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgmf %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x60, 0x37, 0x42, 0x28, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgmf %v22, 55, 66" + + - + input: + bytes: [ 0xe7, 0xf0, 0xff, 0xff, 0x28, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgmf %v31, 255, 255" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgmg %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x60, 0x37, 0x42, 0x38, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgmg %v22, 55, 66" + + - + input: + bytes: [ 0xe7, 0xf0, 0xff, 0xff, 0x38, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgmg %v31, 255, 255" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgmh %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x60, 0x37, 0x42, 0x18, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgmh %v22, 55, 66" + + - + input: + bytes: [ 0xe7, 0xf0, 0xff, 0xff, 0x18, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vgmh %v31, 255, 255" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vistr %v0, %v0, 11, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xc0, 0xb0, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vistr %v0, %v0, 11, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x00, 0x00, 0xb8, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vistr %v18, %v3, 11, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0xbc, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vistr %v31, %v31, 11, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vistrb %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xc0, 0x00, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vistrb %v0, %v0, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x00, 0x00, 0x08, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vistrb %v18, %v3, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x0c, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vistrb %v31, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x78, 0x00, 0x10, 0x04, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vistrbs %v7, %v24" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vistrf %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xc0, 0x20, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vistrf %v0, %v0, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x00, 0x00, 0x28, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vistrf %v18, %v3, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x2c, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vistrf %v31, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x78, 0x00, 0x10, 0x24, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vistrfs %v7, %v24" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vistrh %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xc0, 0x10, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vistrh %v0, %v0, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x00, 0x00, 0x18, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vistrh %v18, %v3, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x1c, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vistrh %v31, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x78, 0x00, 0x10, 0x14, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vistrhs %v7, %v24" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vl %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x40, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vl %v0, 0, 4" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0x08, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vl %v17, 2475(%r7,%r8)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x08, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vl %v31, 4095(%r15,%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbb %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0xc8, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbb %v17, 2475(%r7,%r8), 12" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0xf8, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbb %v31, 4095(%r15,%r15), 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlc %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0xb8, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlc %v19, %v14, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0xbc, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlc %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlcb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x08, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlcb %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x0c, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlcb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlcf %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x28, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlcf %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x2c, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlcf %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlcg %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x38, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlcg %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x3c, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlcg %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlch %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x18, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlch %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x1c, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlch %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x09, 0xb0, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlde %v0, %v0, 11, 9" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x09, 0xb8, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlde %v19, %v14, 11, 9" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x09, 0xbc, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlde %v31, %v31, 11, 9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vldeb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x28, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vldeb %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x2c, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vldeb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleb %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0xc8, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleb %v17, 2475(%r7,%r8), 12" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0xf8, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleb %v31, 4095(%r15,%r15), 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xc5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vled %v0, %v0, 11, 0, 0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0xa4, 0xb8, 0xc5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vled %v19, %v14, 11, 4, 10" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0xf7, 0xbc, 0xc5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vled %v31, %v31, 11, 7, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xc5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vledb %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0xa4, 0x38, 0xc5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vledb %v19, %v14, 4, 10" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0xf7, 0x3c, 0xc5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vledb %v31, %v31, 7, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlef %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0x28, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlef %v17, 2475(%r7,%r8), 2" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x38, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlef %v31, 4095(%r15,%r15), 3" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleg %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0x18, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleg %v17, 2475(%r7,%r8), 1" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x18, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleg %v31, 4095(%r15,%r15), 1" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleh %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0x58, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleh %v17, 2475(%r7,%r8), 5" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x78, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleh %v31, 4095(%r15,%r15), 7" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleib %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x70, 0x89, 0xab, 0xc8, 0x40 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleib %v23, -30293, 12" + + - + input: + bytes: [ 0xe7, 0xf0, 0xff, 0xff, 0xf8, 0x40 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleib %v31, -1, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x43 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleif %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x70, 0x89, 0xab, 0x28, 0x43 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleif %v23, -30293, 2" + + - + input: + bytes: [ 0xe7, 0xf0, 0xff, 0xff, 0x38, 0x43 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleif %v31, -1, 3" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x42 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleig %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x70, 0x89, 0xab, 0x18, 0x42 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleig %v23, -30293, 1" + + - + input: + bytes: [ 0xe7, 0xf0, 0xff, 0xff, 0x18, 0x42 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleig %v31, -1, 1" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x41 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleih %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x70, 0x89, 0xab, 0x58, 0x41 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleih %v23, -30293, 5" + + - + input: + bytes: [ 0xe7, 0xf0, 0xff, 0xff, 0x78, 0x41 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vleih %v31, -1, 7" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlgv %r0, %v0, 0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x45, 0x67, 0xb4, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlgv %r2, %v19, 1383(%r4), 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0xb4, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlgv %r15, %v31, 4095(%r15), 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlgvb %r0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x45, 0x67, 0x04, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlgvb %r2, %v19, 1383(%r4)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x04, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlgvb %r15, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlgvf %r0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x45, 0x67, 0x24, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlgvf %r2, %v19, 1383(%r4)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x24, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlgvf %r15, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlgvg %r0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x45, 0x67, 0x34, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlgvg %r2, %v19, 1383(%r4)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x34, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlgvg %r15, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlgvh %r0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x45, 0x67, 0x14, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlgvh %r2, %v19, 1383(%r4)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x14, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlgvh %r15, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x37 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vll %v0, %r0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x45, 0x67, 0x08, 0x37 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vll %v18, %r3, 1383(%r4)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x08, 0x37 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vll %v31, %r15, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllez %v0, 0, 11" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0xb8, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllez %v17, 2475(%r7,%r8), 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0xb8, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllez %v31, 4095(%r15,%r15), 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllezb %v0, 0" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0x08, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllezb %v17, 2475(%r7,%r8)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x08, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllezb %v31, 4095(%r15,%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllezf %v0, 0" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0x28, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllezf %v17, 2475(%r7,%r8)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x28, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllezf %v31, 4095(%r15,%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllezg %v0, 0" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0x38, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllezg %v17, 2475(%r7,%r8)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x38, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllezg %v31, 4095(%r15,%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllezh %v0, 0" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0x18, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllezh %v17, 2475(%r7,%r8)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x18, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllezh %v31, 4095(%r15,%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x36 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlm %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x40, 0x36 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlm %v0, %v0, 0, 4" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0x04, 0x36 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlm %v12, %v18, 1110(%r3)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x0c, 0x36 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlm %v31, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlp %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0xb8, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlp %v19, %v14, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0xbc, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlp %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlpb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x08, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlpb %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x0c, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlpb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlpf %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x28, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlpf %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x2c, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlpf %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlpg %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x38, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlpg %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x3c, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlpg %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlph %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x18, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlph %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x1c, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlph %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlr %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x08, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlr %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x0c, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlr %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrep %v0, 0, 11" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0xb8, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrep %v17, 2475(%r7,%r8), 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0xb8, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrep %v31, 4095(%r15,%r15), 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrepb %v0, 0" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0x08, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrepb %v17, 2475(%r7,%r8)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x08, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrepb %v31, 4095(%r15,%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrepf %v0, 0" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0x28, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrepf %v17, 2475(%r7,%r8)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x28, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrepf %v31, 4095(%r15,%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrepg %v0, 0" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0x38, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrepg %v17, 2475(%r7,%r8)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x38, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrepg %v31, 4095(%r15,%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlreph %v0, 0" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0x18, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlreph %v17, 2475(%r7,%r8)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x18, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlreph %v31, 4095(%r15,%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x22 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlvg %v0, %r0, 0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x45, 0x67, 0xb8, 0x22 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlvg %v18, %r3, 1383(%r4), 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0xb8, 0x22 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlvg %v31, %r15, 4095(%r15), 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x22 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlvgb %v0, %r0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x45, 0x67, 0x08, 0x22 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlvgb %v18, %r3, 1383(%r4)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x08, 0x22 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlvgb %v31, %r15, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x22 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlvgf %v0, %r0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x45, 0x67, 0x28, 0x22 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlvgf %v18, %r3, 1383(%r4)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x28, 0x22 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlvgf %v31, %r15, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x22 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlvgg %v0, %r0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x45, 0x67, 0x38, 0x22 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlvgg %v18, %r3, 1383(%r4)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x38, 0x22 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlvgg %v31, %r15, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x22 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlvgh %v0, %r0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x45, 0x67, 0x18, 0x22 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlvgh %v18, %r3, 1383(%r4)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x18, 0x22 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlvgh %v31, %r15, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x62 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlvgp %v0, %r0, %r0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x08, 0x62 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlvgp %v18, %r3, %r4" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x08, 0x62 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlvgp %v31, %r15, %r15" + + - + input: + bytes: [ 0xe7, 0x00, 0x0b, 0x00, 0x00, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmae %v0, %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x34, 0x5b, 0x00, 0x65, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmae %v3, %v20, %v5, %v22, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xfb, 0x00, 0xff, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmae %v31, %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaeb %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x50, 0x00, 0x65, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaeb %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xff, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaeb %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0x00, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaef %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x52, 0x00, 0x65, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaef %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf2, 0x00, 0xff, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaef %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x01, 0x00, 0x00, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaeh %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x51, 0x00, 0x65, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaeh %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf1, 0x00, 0xff, 0xae ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaeh %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x0b, 0x00, 0x00, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmah %v0, %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x34, 0x5b, 0x00, 0x65, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmah %v3, %v20, %v5, %v22, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xfb, 0x00, 0xff, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmah %v31, %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmahb %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x50, 0x00, 0x65, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmahb %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xff, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmahb %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0x00, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmahf %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x52, 0x00, 0x65, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmahf %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf2, 0x00, 0xff, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmahf %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x01, 0x00, 0x00, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmahh %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x51, 0x00, 0x65, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmahh %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf1, 0x00, 0xff, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmahh %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x0b, 0x00, 0x00, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmal %v0, %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x34, 0x5b, 0x00, 0x65, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmal %v3, %v20, %v5, %v22, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xfb, 0x00, 0xff, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmal %v31, %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalb %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x50, 0x00, 0x65, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalb %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xff, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalb %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x0b, 0x00, 0x00, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmale %v0, %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x34, 0x5b, 0x00, 0x65, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmale %v3, %v20, %v5, %v22, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xfb, 0x00, 0xff, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmale %v31, %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaleb %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x50, 0x00, 0x65, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaleb %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xff, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaleb %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0x00, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalef %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x52, 0x00, 0x65, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalef %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf2, 0x00, 0xff, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalef %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x01, 0x00, 0x00, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaleh %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x51, 0x00, 0x65, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaleh %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf1, 0x00, 0xff, 0xac ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaleh %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0x00, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalf %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x52, 0x00, 0x65, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalf %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf2, 0x00, 0xff, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalf %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x0b, 0x00, 0x00, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalh %v0, %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x34, 0x5b, 0x00, 0x65, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalh %v3, %v20, %v5, %v22, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xfb, 0x00, 0xff, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalh %v31, %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalhb %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x50, 0x00, 0x65, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalhb %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xff, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalhb %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0x00, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalhf %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x52, 0x00, 0x65, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalhf %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf2, 0x00, 0xff, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalhf %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x01, 0x00, 0x00, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalhh %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x51, 0x00, 0x65, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalhh %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf1, 0x00, 0xff, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalhh %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x01, 0x00, 0x00, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalhw %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x51, 0x00, 0x65, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalhw %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf1, 0x00, 0xff, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalhw %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x0b, 0x00, 0x00, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalo %v0, %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x34, 0x5b, 0x00, 0x65, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalo %v3, %v20, %v5, %v22, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xfb, 0x00, 0xff, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalo %v31, %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalob %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x50, 0x00, 0x65, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalob %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xff, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalob %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0x00, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalof %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x52, 0x00, 0x65, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalof %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf2, 0x00, 0xff, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmalof %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x01, 0x00, 0x00, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaloh %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x51, 0x00, 0x65, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaloh %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf1, 0x00, 0xff, 0xad ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaloh %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x0b, 0x00, 0x00, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmao %v0, %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x34, 0x5b, 0x00, 0x65, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmao %v3, %v20, %v5, %v22, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xfb, 0x00, 0xff, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmao %v31, %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaob %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x50, 0x00, 0x65, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaob %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xff, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaob %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0x00, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaof %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x52, 0x00, 0x65, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaof %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf2, 0x00, 0xff, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaof %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x01, 0x00, 0x00, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaoh %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x51, 0x00, 0x65, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaoh %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf1, 0x00, 0xff, 0xaf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmaoh %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xa6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vme %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0xa6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vme %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0xa6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vme %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xa6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmeb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xa6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmeb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xa6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmeb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xa6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmef %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xa6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmef %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xa6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmef %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xa6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmeh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xa6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmeh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xa6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmeh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xa3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmh %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0xa3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmh %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0xa3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmh %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xa3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmhb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xa3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmhb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xa3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmhb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xa3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmhf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xa3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmhf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xa3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmhf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xa3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmhh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xa3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmhh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xa3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmhh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xa2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vml %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0xa2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vml %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0xa2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vml %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xa2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xa2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xa2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xa4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmle %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0xa4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmle %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0xa4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmle %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xa4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmleb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xa4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmleb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xa4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmleb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xa4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlef %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xa4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlef %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xa4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlef %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xa4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmleh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xa4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmleh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xa4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmleh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xa2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xa2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xa2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xa1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlh %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0xa1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlh %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0xa1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlh %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xa1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlhb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xa1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlhb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xa1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlhb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xa1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlhf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xa1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlhf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xa1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlhf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xa1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlhh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xa1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlhh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xa1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlhh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xa2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlhw %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xa2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlhw %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xa2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlhw %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xa5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlo %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0xa5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlo %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0xa5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlo %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xa5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlob %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xa5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlob %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xa5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlob %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xa5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlof %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xa5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlof %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xa5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmlof %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xa5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmloh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xa5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmloh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xa5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmloh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmn %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmn %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmn %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmng %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmng %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmng %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnl %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnl %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnl %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnlb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnlb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnlb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnlf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnlf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnlf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnlg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnlg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnlg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnlh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnlh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmnlh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xa7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmo %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0xa7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmo %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0xa7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmo %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xa7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmob %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xa7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmob %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xa7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmob %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xa7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmof %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xa7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmof %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xa7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmof %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xa7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmoh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xa7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmoh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xa7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmoh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x61 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrh %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0x61 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrh %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0x61 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrh %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x61 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrhb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x61 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrhb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x61 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrhb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x61 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrhf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0x61 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrhf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0x61 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrhf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x61 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrhg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0x61 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrhg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0x61 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrhg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x61 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrhh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0x61 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrhh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0x61 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrhh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x60 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrl %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0x60 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrl %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0x60 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrl %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x60 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrlb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x60 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrlb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x60 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrlb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x60 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrlf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0x60 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrlf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0x60 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrlf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x60 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrlg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0x60 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrlg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0x60 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrlg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x60 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrlh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0x60 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrlh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0x60 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmrlh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmx %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmx %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmx %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxl %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxl %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxl %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxlb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxlb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxlb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxlf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxlf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxlf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxlg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxlg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxlg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxlh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxlh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmxlh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vn %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vn %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vn %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x69 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vnc %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x69 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vnc %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x69 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vnc %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x6b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vno %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x6b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vno %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x6b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vno %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x6a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vo %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x6a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vo %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x6a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vo %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x84 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpdi %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x34, 0x50, 0x00, 0x44, 0x84 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpdi %v3, %v20, %v5, 4" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xfe, 0x84 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpdi %v31, %v31, %v31, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x8c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vperm %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x50, 0x00, 0x65, 0x8c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vperm %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xff, 0x8c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vperm %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpk %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpk %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpk %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x90, 0xb0, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkls %v0, %v0, %v0, 11, 9" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x90, 0xba, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkls %v18, %v3, %v20, 11, 9" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x90, 0xbe, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkls %v31, %v31, %v31, 11, 9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpklsf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpklsf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpklsf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x24, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpklsfs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpklsg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpklsg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpklsg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x34, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpklsgs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpklsh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpklsh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpklsh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x14, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpklshs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x90, 0xb0, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpks %v0, %v0, %v0, 11, 9" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x90, 0xba, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpks %v18, %v3, %v20, 11, 9" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x90, 0xbe, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpks %v31, %v31, %v31, 11, 9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpksf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpksf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpksf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x24, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpksfs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpksg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpksg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpksg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x34, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpksgs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpksh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpksh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpksh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x78, 0x90, 0x10, 0x14, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkshs %v7, %v24, %v9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopct %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x08, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopct %v19, %v14, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x0c, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopct %v31, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrep %v0, %v0, 0, 11" + + - + input: + bytes: [ 0xe7, 0x34, 0x56, 0x78, 0xb8, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrep %v19, %v4, 22136, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0xbc, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrep %v31, %v31, 65535, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepb %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x34, 0x56, 0x78, 0x08, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepb %v19, %v4, 22136" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x0c, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepb %v31, %v31, 65535" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepf %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x34, 0x56, 0x78, 0x28, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepf %v19, %v4, 22136" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x2c, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepf %v31, %v31, 65535" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepg %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x34, 0x56, 0x78, 0x38, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepg %v19, %v4, 22136" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x3c, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepg %v31, %v31, 65535" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vreph %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x34, 0x56, 0x78, 0x18, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vreph %v19, %v4, 22136" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x1c, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vreph %v31, %v31, 65535" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepi %v0, 0, 11" + + - + input: + bytes: [ 0xe7, 0x70, 0x89, 0xab, 0xb8, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepi %v23, -30293, 11" + + - + input: + bytes: [ 0xe7, 0xf0, 0xff, 0xff, 0xb8, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepi %v31, -1, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepib %v0, 0" + + - + input: + bytes: [ 0xe7, 0x70, 0x89, 0xab, 0x08, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepib %v23, -30293" + + - + input: + bytes: [ 0xe7, 0xf0, 0xff, 0xff, 0x08, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepib %v31, -1" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepif %v0, 0" + + - + input: + bytes: [ 0xe7, 0x70, 0x89, 0xab, 0x28, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepif %v23, -30293" + + - + input: + bytes: [ 0xe7, 0xf0, 0xff, 0xff, 0x28, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepif %v31, -1" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepig %v0, 0" + + - + input: + bytes: [ 0xe7, 0x70, 0x89, 0xab, 0x38, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepig %v23, -30293" + + - + input: + bytes: [ 0xe7, 0xf0, 0xff, 0xff, 0x38, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepig %v31, -1" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepih %v0, 0" + + - + input: + bytes: [ 0xe7, 0x70, 0x89, 0xab, 0x18, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepih %v23, -30293" + + - + input: + bytes: [ 0xe7, 0xf0, 0xff, 0xff, 0x18, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrepih %v31, -1" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vs %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vs %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vs %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x0b, 0x00, 0x00, 0xbd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsbcbi %v0, %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x34, 0x5b, 0x00, 0x65, 0xbd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsbcbi %v3, %v20, %v5, %v22, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xfb, 0x00, 0xff, 0xbd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsbcbi %v31, %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x04, 0x00, 0x00, 0xbd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsbcbiq %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x54, 0x00, 0x65, 0xbd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsbcbiq %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf4, 0x00, 0xff, 0xbd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsbcbiq %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x0b, 0x00, 0x00, 0xbf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsbi %v0, %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x34, 0x5b, 0x00, 0x65, 0xbf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsbi %v3, %v20, %v5, %v22, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xfb, 0x00, 0xff, 0xbf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsbi %v31, %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x04, 0x00, 0x00, 0xbf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsbiq %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x54, 0x00, 0x65, 0xbf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsbiq %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf4, 0x00, 0xff, 0xbf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsbiq %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xf5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscbi %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0xf5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscbi %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0xf5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscbi %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xf5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscbib %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0xf5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscbib %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0xf5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscbib %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xf5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscbif %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xf5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscbif %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xf5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscbif %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xf5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscbig %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xf5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscbig %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xf5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscbig %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xf5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscbih %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xf5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscbih %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xf5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscbih %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x40, 0xf5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscbiq %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x4a, 0xf5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscbiq %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x4e, 0xf5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscbiq %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscef %v0, 0(%v0,0), 0" + + - + input: + bytes: [ 0xe7, 0xa3, 0x73, 0xe8, 0x24, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscef %v10, 1000(%v19,%r7), 2" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x3c, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscef %v31, 4095(%v31,%r15), 3" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsceg %v0, 0(%v0,0), 0" + + - + input: + bytes: [ 0xe7, 0xa3, 0x73, 0xe8, 0x14, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsceg %v10, 1000(%v19,%r7), 1" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x1c, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsceg %v31, 4095(%v31,%r15), 1" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vseg %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0xb8, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vseg %v19, %v14, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0xbc, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vseg %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsegb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x08, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsegb %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x0c, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsegb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsegf %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x28, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsegf %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x2c, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsegf %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsegh %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x18, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsegh %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x1c, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsegh %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x8d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsel %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x34, 0x50, 0x00, 0x65, 0x8d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsel %v3, %v20, %v5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xff, 0x8d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsel %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsl %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsl %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsl %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vslb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vslb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vslb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsldb %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x34, 0x50, 0x67, 0x04, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsldb %v3, %v20, %v5, 103" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0xff, 0x0e, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsldb %v31, %v31, %v31, 255" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x40, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsq %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x4a, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsq %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x4e, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsq %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsra %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsra %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsra %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x7f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrab %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x7f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrab %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x7f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrab %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x7c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrl %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x7c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrl %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x7c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrl %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x7d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrlb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x7d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrlb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x7d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrlb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vst %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x40, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vst %v0, 0, 4" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0x08, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vst %v17, 2475(%r7,%r8)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x08, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vst %v31, 4095(%r15,%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsteb %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0xc8, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsteb %v17, 2475(%r7,%r8), 12" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0xf8, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsteb %v31, 4095(%r15,%r15), 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstef %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0x28, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstef %v17, 2475(%r7,%r8), 2" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x38, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstef %v31, 4095(%r15,%r15), 3" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsteg %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0x18, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsteg %v17, 2475(%r7,%r8), 1" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x18, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsteg %v31, 4095(%r15,%r15), 1" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsteh %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x17, 0x89, 0xab, 0x58, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsteh %v17, 2475(%r7,%r8), 5" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x78, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsteh %v31, 4095(%r15,%r15), 7" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstl %v0, %r0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x45, 0x67, 0x08, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstl %v18, %r3, 1383(%r4)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x08, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstl %v31, %r15, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstm %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x40, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstm %v0, %v0, 0, 4" + + - + input: + bytes: [ 0xe7, 0xc2, 0x34, 0x56, 0x04, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstm %v12, %v18, 1110(%r3)" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xff, 0x0c, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstm %v31, %v31, 4095(%r15)" + + - + input: + bytes: [ 0xe7, 0x00, 0x0b, 0x00, 0x00, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrc %v0, %v0, %v0, %v0, 11, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x0b, 0xc0, 0x00, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrc %v0, %v0, %v0, %v0, 11, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x4b, 0x00, 0x5a, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrc %v18, %v3, %v20, %v5, 11, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0xfb, 0x40, 0xff, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrc %v31, %v31, %v31, %v31, 11, 4" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrcb %v0, %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xc0, 0x00, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrcb %v0, %v0, %v0, %v0, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x5a, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrcb %v18, %v3, %v20, %v5, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x40, 0xff, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrcb %v31, %v31, %v31, %v31, 4" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x90, 0xff, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrcbs %v31, %v31, %v31, %v31, 8" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x60, 0xff, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrczb %v31, %v31, %v31, %v31, 4" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0xb0, 0xff, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrczbs %v31, %v31, %v31, %v31, 8" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0x00, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrcf %v0, %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0xc0, 0x00, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrcf %v0, %v0, %v0, %v0, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x42, 0x00, 0x5a, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrcf %v18, %v3, %v20, %v5, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0xf2, 0x40, 0xff, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrcf %v31, %v31, %v31, %v31, 4" + + - + input: + bytes: [ 0xe7, 0xff, 0xf2, 0x90, 0xff, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrcfs %v31, %v31, %v31, %v31, 8" + + - + input: + bytes: [ 0xe7, 0xff, 0xf2, 0x60, 0xff, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrczf %v31, %v31, %v31, %v31, 4" + + - + input: + bytes: [ 0xe7, 0xff, 0xf2, 0xb0, 0xff, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrczfs %v31, %v31, %v31, %v31, 8" + + - + input: + bytes: [ 0xe7, 0x00, 0x01, 0x00, 0x00, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrch %v0, %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x01, 0xc0, 0x00, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrch %v0, %v0, %v0, %v0, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x41, 0x00, 0x5a, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrch %v18, %v3, %v20, %v5, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0xf1, 0x40, 0xff, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrch %v31, %v31, %v31, %v31, 4" + + - + input: + bytes: [ 0xe7, 0xff, 0xf1, 0x90, 0xff, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrchs %v31, %v31, %v31, %v31, 8" + + - + input: + bytes: [ 0xe7, 0xff, 0xf1, 0x60, 0xff, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrczh %v31, %v31, %v31, %v31, 4" + + - + input: + bytes: [ 0xe7, 0xff, 0xf1, 0xb0, 0xff, 0x8a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrczhs %v31, %v31, %v31, %v31, 8" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x64 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsum %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0x64 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsum %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0x64 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsum %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x64 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x64 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x64 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x65 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumg %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0x65 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumg %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0x65 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumg %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x65 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumgf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0x65 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumgf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0x65 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumgf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x65 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumgh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0x65 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumgh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0x65 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumgh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x64 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumh %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x1a, 0x64 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumh %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x1e, 0x64 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumh %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0x67 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumq %v0, %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0xba, 0x67 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumq %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0xbe, 0x67 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumq %v31, %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x67 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumqf %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0x67 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumqf %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x2e, 0x67 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumqf %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x67 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumqg %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x3a, 0x67 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumqg %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x3e, 0x67 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsumqg %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xd8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vtm %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x08, 0xd8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vtm %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x0c, 0xd8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vtm %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xd7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuph %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0xb8, 0xd7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuph %v19, %v14, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0xbc, 0xd7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuph %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xd7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuphb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x08, 0xd7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuphb %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x0c, 0xd7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuphb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xd7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuphf %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x28, 0xd7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuphf %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x2c, 0xd7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuphf %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xd7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuphh %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x18, 0xd7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuphh %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x1c, 0xd7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuphh %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xd6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupl %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0xb8, 0xd6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupl %v19, %v14, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0xbc, 0xd6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupl %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xd6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x08, 0xd6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplb %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x0c, 0xd6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xd6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplf %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x28, 0xd6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplf %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x2c, 0xd6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplf %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xd5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplh %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0xb8, 0xd5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplh %v19, %v14, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0xbc, 0xd5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplh %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xd5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplhb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x08, 0xd5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplhb %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x0c, 0xd5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplhb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xd5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplhf %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x28, 0xd5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplhf %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x2c, 0xd5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplhf %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xd5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplhh %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x18, 0xd5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplhh %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x1c, 0xd5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplhh %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xd6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplhw %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x18, 0xd6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplhw %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x1c, 0xd6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vuplhw %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xb0, 0xd4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupll %v0, %v0, 11" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0xb8, 0xd4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupll %v19, %v14, 11" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0xbc, 0xd4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupll %v31, %v31, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xd4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupllb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x08, 0xd4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupllb %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x0c, 0xd4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupllb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xd4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupllf %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x28, 0xd4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupllf %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x2c, 0xd4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupllf %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0xd4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupllh %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x18, 0xd4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupllh %v19, %v14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x1c, 0xd4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupllh %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x6d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vx %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x6d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vx %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x00, 0x0e, 0x6d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vx %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcdgb %f0, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0xac, 0x38, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcdgb %v19, %f14, 4, 10" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0xff, 0x3c, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcdgb %v31, %v31, 7, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcdlgb %f0, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0xac, 0x38, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcdlgb %v19, %f14, 4, 10" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0xff, 0x3c, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcdlgb %v31, %v31, 7, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcgdb %f0, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0xac, 0x38, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcgdb %v19, %f14, 4, 10" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0xff, 0x3c, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcgdb %v31, %v31, 7, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wclgdb %f0, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0xac, 0x38, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wclgdb %v19, %f14, 4, 10" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0xff, 0x3c, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wclgdb %v31, %v31, 7, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfadb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x3a, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfadb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x08, 0x3e, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfadb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x09, 0xb0, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfc %f0, %f0, 11, 9" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x09, 0xb8, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfc %v19, %f14, 11, 9" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x09, 0xbc, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfc %v31, %v31, 11, 9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcdb %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x38, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcdb %v19, %f14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x3c, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcdb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcedb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x3a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcedb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x08, 0x3e, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcedb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x18, 0x30, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcedbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x18, 0x3a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcedbs %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x18, 0x3e, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcedbs %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchdb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x3a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchdb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x08, 0x3e, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchdb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x18, 0x30, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchdbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x18, 0x3a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchdbs %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x18, 0x3e, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchdbs %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchedb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x3a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchedb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x08, 0x3e, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchedb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x18, 0x30, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchedbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x18, 0x3a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchedbs %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x18, 0x3e, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchedbs %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfddb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x3a, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfddb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x08, 0x3e, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfddb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfidb %f0, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0xac, 0x38, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfidb %v19, %f14, 4, 10" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0xff, 0x3c, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfidb %v31, %v31, 7, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x09, 0xb0, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfk %f0, %f0, 11, 9" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x09, 0xb8, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfk %v19, %f14, 11, 9" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x09, 0xbc, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfk %v31, %v31, 11, 9" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkdb %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x00, 0x38, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkdb %v19, %f14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x00, 0x3c, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkdb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflcdb %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x08, 0x38, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflcdb %v19, %f14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x08, 0x3c, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflcdb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x18, 0x30, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflndb %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x18, 0x38, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflndb %v19, %f14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x18, 0x3c, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflndb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x28, 0x30, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflpdb %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x28, 0x38, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflpdb %v19, %f14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x28, 0x3c, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflpdb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x03, 0x08, 0x00, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmadb %f0, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x34, 0x53, 0x08, 0x65, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmadb %f3, %v20, %f5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf3, 0x08, 0xff, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmadb %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmdb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x3a, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmdb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x08, 0x3e, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmdb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x03, 0x08, 0x00, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmsdb %f0, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x34, 0x53, 0x08, 0x65, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmsdb %f3, %v20, %f5, %v22" + + - + input: + bytes: [ 0xe7, 0xff, 0xf3, 0x08, 0xff, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmsdb %v31, %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x78, 0x30, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfpsodb %f0, %f0, 7" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x78, 0x38, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfpsodb %v19, %f14, 7" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x78, 0x3c, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfpsodb %v31, %v31, 7" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsdb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x3a, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsdb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0xff, 0xf0, 0x08, 0x3e, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsdb %v31, %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsqdb %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x08, 0x38, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsqdb %v19, %f14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x08, 0x3c, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsqdb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wftcidb %f0, %f0, 0" + + - + input: + bytes: [ 0xe7, 0x34, 0x56, 0x78, 0x38, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wftcidb %v19, %f4, 1383" + + - + input: + bytes: [ 0xe7, 0xff, 0xff, 0xf8, 0x3c, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wftcidb %v31, %v31, 4095" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wldeb %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0x08, 0x28, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wldeb %v19, %f14" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0x08, 0x2c, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wldeb %v31, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xc5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wledb %f0, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x3e, 0x00, 0xac, 0x38, 0xc5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wledb %v19, %f14, 4, 10" + + - + input: + bytes: [ 0xe7, 0xff, 0x00, 0xff, 0x3c, 0xc5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wledb %v31, %v31, 7, 15" diff --git a/tests/MC/SystemZ/insns-z14.txt.yaml b/tests/MC/SystemZ/insns-z14.txt.yaml new file mode 100644 index 0000000000..c6c243b6e1 --- /dev/null +++ b/tests/MC/SystemZ/insns-z14.txt.yaml @@ -0,0 +1,10830 @@ +test_cases: + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agh %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agh %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agh %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agh %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agh %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agh %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agh %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agh %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agh %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agh %r15, 0" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x80, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bi -524288" + + - + input: + bytes: [ 0xe3, 0xf0, 0x0f, 0xff, 0xff, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bi -1" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bi 0" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x01, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bi 1" + + - + input: + bytes: [ 0xe3, 0xf0, 0x0f, 0xff, 0x7f, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bi 524287" + + - + input: + bytes: [ 0xe3, 0xf0, 0x10, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bi 0(%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0xf0, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bi 0(%r15)" + + - + input: + bytes: [ 0xe3, 0xf1, 0xff, 0xff, 0x7f, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bi 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0xff, 0x1f, 0xff, 0x7f, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bi 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bic 0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bic 0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bic 0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bic 0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bic 0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bic 0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bic 0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bic 0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bic 0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0x10, 0xf0, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bio 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x20, 0xf0, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bih 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x30, 0xf0, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binle 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x40, 0xf0, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bil 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x50, 0xf0, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binhe 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x60, 0xf0, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bilh 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x70, 0xf0, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bine 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x80, 0xf0, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bie 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x90, 0xf0, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binlh 0(%r15)" + + - + input: + bytes: [ 0xe3, 0xa0, 0xf0, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bihe 0(%r15)" + + - + input: + bytes: [ 0xe3, 0xb0, 0xf0, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binl 0(%r15)" + + - + input: + bytes: [ 0xe3, 0xc0, 0xf0, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bile 0(%r15)" + + - + input: + bytes: [ 0xe3, 0xd0, 0xf0, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "binh 0(%r15)" + + - + input: + bytes: [ 0xe3, 0xe0, 0xf0, 0x00, 0x00, 0x47 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bino 0(%r15)" + + - + input: + bytes: [ 0xb9, 0xac, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "irbm %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xac, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "irbm %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xac, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "irbm %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xac, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "irbm %r7, %r8" + + - + input: + bytes: [ 0xb9, 0xac, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "irbm %r15, %r15" + + - + input: + bytes: [ 0xb9, 0x29, 0x20, 0x22 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kma %r2, %r2, %r2" + + - + input: + bytes: [ 0xb9, 0x29, 0x80, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kma %r2, %r8, %r14" + + - + input: + bytes: [ 0xb9, 0x29, 0x80, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kma %r14, %r8, %r2" + + - + input: + bytes: [ 0xb9, 0x29, 0x80, 0x6a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kma %r6, %r8, %r10" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgg %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgsc %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgsc %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgsc %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgsc %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgsc %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgsc %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgsc %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgsc %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgsc %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfsg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfsg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfsg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfsg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfsg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfsg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfsg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfsg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfsg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfsg %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x84 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x84 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x84 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x84 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x84 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x84 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x84 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x84 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x84 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x84 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mg %r14, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mgh %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mgh %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mgh %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mgh %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mgh %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mgh %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mgh %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mgh %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mgh %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mgh %r15, 0" + + - + input: + bytes: [ 0xb9, 0xec, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mgrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xec, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mgrk %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xec, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mgrk %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xec, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mgrk %r14, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xec, 0x90, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mgrk %r6, %r8, %r9" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msc %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msc %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msc %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msc %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msc %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msc %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msc %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msc %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msc %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x53 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msc %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x83 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgc %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x83 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgc %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x83 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgc %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x83 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgc %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x83 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgc %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x83 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgc %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x83 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgc %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x83 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgc %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x83 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgc %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x83 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgc %r15, 0" + + - + input: + bytes: [ 0xb9, 0xfd, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msrkc %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xfd, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msrkc %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xfd, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msrkc %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xfd, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msrkc %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xfd, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msrkc %r7, %r8, %r9" + + - + input: + bytes: [ 0xb9, 0xed, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgrkc %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xed, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgrkc %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xed, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgrkc %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xed, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgrkc %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xed, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgrkc %r7, %r8, %r9" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x39 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgh %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x39 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgh %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x39 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgh %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x39 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgh %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x39 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgh %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x39 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgh %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x39 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgh %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x39 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgh %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x39 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgh %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x39 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgh %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stgsc %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stgsc %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stgsc %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stgsc %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stgsc %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stgsc %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stgsc %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stgsc %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stgsc %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vap %v0, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vap %v0, %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0xf0, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vap %v0, %v0, %v0, 255, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x02, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vap %v0, %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vap %v0, %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vap %v31, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xd1, 0x50, 0xb7, 0x96, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vap %v13, %v17, %v21, 121, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vbperm %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x00, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vbperm %v0, %v0, %v15" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x02, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vbperm %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x00, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vbperm %v0, %v15, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x04, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vbperm %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x00, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vbperm %v15, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x08, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vbperm %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vbperm %v18, %v3, %v20" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcp %v0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcp %v0, %v0, 15" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x00, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcp %v15, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcp %v31, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcp %v0, %v15, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x02, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcp %v0, %v31, 0" + + - + input: + bytes: [ 0xe6, 0x03, 0x20, 0x40, 0x02, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcp %v3, %v18, 4" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvb %r0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvb %r0, %v0, 15" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvb %r15, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvb %r0, %v15, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvb %r0, %v31, 0" + + - + input: + bytes: [ 0xe6, 0x32, 0x00, 0x40, 0x04, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvb %r3, %v18, 4" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvbg %r0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvbg %r0, %v0, 15" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvbg %r15, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x00, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvbg %r0, %v15, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvbg %r0, %v31, 0" + + - + input: + bytes: [ 0xe6, 0x32, 0x00, 0x40, 0x04, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvbg %r3, %v18, 4" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvd %v0, %r0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvd %v0, %r0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0xf0, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvd %v0, %r0, 255, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvd %v0, %r15, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvd %v15, %r0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvd %v31, %r0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x29, 0x00, 0xb3, 0x48, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvd %v18, %r9, 52, 11" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x5a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvdg %v0, %r0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x5a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvdg %v0, %r0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0xf0, 0x5a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvdg %v0, %r0, 255, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x00, 0x5a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvdg %v0, %r15, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x5a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvdg %v15, %r0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x5a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvdg %v31, %r0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x29, 0x00, 0xb3, 0x48, 0x5a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvdg %v18, %r9, 52, 11" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vdp %v0, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vdp %v0, %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0xf0, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vdp %v0, %v0, %v0, 255, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x02, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vdp %v0, %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vdp %v0, %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vdp %v31, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xd1, 0x50, 0xb7, 0x96, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vdp %v13, %v17, %v21, 121, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfasb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x22, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfasb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfasb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfasb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfasb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfcesb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x22, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfcesb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfcesb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfcesb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfcesb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x10, 0x20, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfcesbs %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x10, 0x22, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfcesbs %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x10, 0x24, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfcesbs %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x10, 0x28, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfcesbs %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x10, 0x2a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfcesbs %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchsb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x22, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchsb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchsb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchsb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchsb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x10, 0x20, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchsbs %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x10, 0x22, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchsbs %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x10, 0x24, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchsbs %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x10, 0x28, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchsbs %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x10, 0x2a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchsbs %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchesb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x22, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchesb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchesb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchesb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchesb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x10, 0x20, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchesbs %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x10, 0x22, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchesbs %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x10, 0x24, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchesbs %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x10, 0x28, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchesbs %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x10, 0x2a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfchesbs %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfdsb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x22, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfdsb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfdsb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfdsb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfdsb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfisb %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xf0, 0x20, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfisb %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x04, 0x20, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfisb %v0, %v0, 4, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x07, 0x20, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfisb %v0, %v0, 7, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfisb %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfisb %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0xa4, 0x24, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfisb %v14, %v17, 4, 10" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x04, 0x30, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkedb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x04, 0x32, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkedb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x04, 0x34, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkedb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x04, 0x38, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkedb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x04, 0x3a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkedb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x14, 0x30, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkedbs %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x14, 0x32, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkedbs %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x14, 0x34, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkedbs %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x14, 0x38, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkedbs %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x14, 0x3a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkedbs %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x04, 0x20, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkesb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x04, 0x22, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkesb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x04, 0x24, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkesb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x04, 0x28, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkesb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x04, 0x2a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkesb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x14, 0x20, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkesbs %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x14, 0x22, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkesbs %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x14, 0x24, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkesbs %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x14, 0x28, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkesbs %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x14, 0x2a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkesbs %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x04, 0x30, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhdb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x04, 0x32, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhdb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x04, 0x34, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhdb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x04, 0x38, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhdb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x04, 0x3a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhdb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x14, 0x30, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhdbs %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x14, 0x32, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhdbs %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x14, 0x34, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhdbs %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x14, 0x38, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhdbs %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x14, 0x3a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhdbs %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x04, 0x20, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhsb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x04, 0x22, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhsb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x04, 0x24, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhsb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x04, 0x28, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhsb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x04, 0x2a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhsb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x14, 0x20, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhsbs %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x14, 0x22, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhsbs %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x14, 0x24, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhsbs %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x14, 0x28, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhsbs %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x14, 0x2a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhsbs %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x04, 0x30, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhedb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x04, 0x32, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhedb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x04, 0x34, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhedb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x04, 0x38, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhedb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x04, 0x3a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhedb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x14, 0x30, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhedbs %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x14, 0x32, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhedbs %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x14, 0x34, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhedbs %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x14, 0x38, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhedbs %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x14, 0x3a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhedbs %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x04, 0x20, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhesb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x04, 0x22, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhesb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x04, 0x24, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhesb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x04, 0x28, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhesb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x04, 0x2a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhesb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x14, 0x20, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhesbs %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x14, 0x22, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhesbs %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x14, 0x24, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhesbs %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x14, 0x28, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhesbs %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x14, 0x2a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfkhesbs %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x30, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfpsosb %v0, %v0, 3" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xf0, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfpsosb %v0, %v0, 15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x30, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfpsosb %v0, %v15, 3" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x30, 0x24, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfpsosb %v0, %v31, 3" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x30, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfpsosb %v15, %v0, 3" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x30, 0x28, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfpsosb %v31, %v0, 3" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x70, 0x24, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfpsosb %v14, %v17, 7" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflcsb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflcsb %v0, %v15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflcsb %v0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflcsb %v15, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflcsb %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x00, 0x24, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflcsb %v14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x10, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflnsb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x10, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflnsb %v0, %v15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x10, 0x24, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflnsb %v0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x10, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflnsb %v15, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x10, 0x28, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflnsb %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x10, 0x24, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflnsb %v14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x20, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflpsb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x20, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflpsb %v0, %v15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x20, 0x24, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflpsb %v0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x20, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflpsb %v15, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x20, 0x28, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflpsb %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x20, 0x24, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vflpsb %v14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmax %v0, %v0, %v0, 0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xf0, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmax %v0, %v0, %v0, 15, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0f, 0x00, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmax %v0, %v0, %v0, 0, 15, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x40, 0x00, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmax %v0, %v0, %v0, 0, 0, 4" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x02, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmax %v0, %v0, %v31, 0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x04, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmax %v0, %v31, %v0, 0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x08, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmax %v31, %v0, %v0, 0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0xc9, 0xba, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmax %v18, %v3, %v20, 11, 9, 12" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmaxdb %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x40, 0x30, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmaxdb %v0, %v0, %v0, 4" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x32, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmaxdb %v0, %v0, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x34, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmaxdb %v0, %v31, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x38, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmaxdb %v31, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0xc0, 0x3a, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmaxdb %v18, %v3, %v20, 12" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmaxsb %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x40, 0x20, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmaxsb %v0, %v0, %v0, 4" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x22, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmaxsb %v0, %v0, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmaxsb %v0, %v31, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmaxsb %v31, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0xc0, 0x2a, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmaxsb %v18, %v3, %v20, 12" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmin %v0, %v0, %v0, 0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xf0, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmin %v0, %v0, %v0, 15, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0f, 0x00, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmin %v0, %v0, %v0, 0, 15, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x40, 0x00, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmin %v0, %v0, %v0, 0, 0, 4" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x02, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmin %v0, %v0, %v31, 0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x04, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmin %v0, %v31, %v0, 0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x08, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmin %v31, %v0, %v0, 0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0xc9, 0xba, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmin %v18, %v3, %v20, 11, 9, 12" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmindb %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x40, 0x30, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmindb %v0, %v0, %v0, 4" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x32, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmindb %v0, %v0, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x34, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmindb %v0, %v31, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x38, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmindb %v31, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0xc0, 0x3a, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmindb %v18, %v3, %v20, 12" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfminsb %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x40, 0x20, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfminsb %v0, %v0, %v0, 4" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x22, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfminsb %v0, %v0, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfminsb %v0, %v31, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfminsb %v31, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0xc0, 0x2a, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfminsb %v18, %v3, %v20, 12" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0x00, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmasb %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0xf1, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmasb %v0, %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0xf2, 0x00, 0x02, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmasb %v0, %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x02, 0x00, 0x04, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmasb %v0, %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x02, 0x00, 0x08, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmasb %v31, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x52, 0x00, 0x97, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmasb %v13, %v17, %v21, %v25" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmsb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x22, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmsb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmsb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmsb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmsb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0x00, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmssb %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0xf1, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmssb %v0, %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0xf2, 0x00, 0x02, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmssb %v0, %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x02, 0x00, 0x04, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmssb %v0, %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x02, 0x00, 0x08, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmssb %v31, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x52, 0x00, 0x97, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfmssb %v13, %v17, %v21, %v25" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnma %v0, %v0, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x0f, 0x00, 0x00, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnma %v0, %v0, %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0f, 0x00, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnma %v0, %v0, %v0, %v0, 15, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xf1, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnma %v0, %v0, %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x02, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnma %v0, %v0, %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x04, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnma %v0, %v31, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x08, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnma %v31, %v0, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x5b, 0x09, 0x97, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnma %v13, %v17, %v21, %v25, 9, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x03, 0x00, 0x00, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmadb %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0x03, 0x00, 0xf1, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmadb %v0, %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0xf3, 0x00, 0x02, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmadb %v0, %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x03, 0x00, 0x04, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmadb %v0, %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x03, 0x00, 0x08, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmadb %v31, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x53, 0x00, 0x97, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmadb %v13, %v17, %v21, %v25" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0x00, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmasb %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0xf1, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmasb %v0, %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0xf2, 0x00, 0x02, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmasb %v0, %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x02, 0x00, 0x04, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmasb %v0, %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x02, 0x00, 0x08, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmasb %v31, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x52, 0x00, 0x97, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmasb %v13, %v17, %v21, %v25" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnms %v0, %v0, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x0f, 0x00, 0x00, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnms %v0, %v0, %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0f, 0x00, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnms %v0, %v0, %v0, %v0, 15, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xf1, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnms %v0, %v0, %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x02, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnms %v0, %v0, %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x04, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnms %v0, %v31, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x08, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnms %v31, %v0, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x5b, 0x09, 0x97, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnms %v13, %v17, %v21, %v25, 9, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x03, 0x00, 0x00, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmsdb %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0x03, 0x00, 0xf1, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmsdb %v0, %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0xf3, 0x00, 0x02, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmsdb %v0, %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x03, 0x00, 0x04, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmsdb %v0, %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x03, 0x00, 0x08, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmsdb %v31, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x53, 0x00, 0x97, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmsdb %v13, %v17, %v21, %v25" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0x00, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmssb %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0xf1, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmssb %v0, %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0xf2, 0x00, 0x02, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmssb %v0, %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x02, 0x00, 0x04, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmssb %v0, %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x02, 0x00, 0x08, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmssb %v31, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x52, 0x00, 0x97, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfnmssb %v13, %v17, %v21, %v25" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfssb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x22, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfssb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfssb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfssb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x2a, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfssb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfsqsb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x20, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfsqsb %v0, %v15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfsqsb %v0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x20, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfsqsb %v15, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfsqsb %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x00, 0x24, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vfsqsb %v14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vftcisb %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0xff, 0xf0, 0x20, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vftcisb %v0, %v0, 4095" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x20, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vftcisb %v0, %v15, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vftcisb %v0, %v31, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x20, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vftcisb %v15, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vftcisb %v31, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x45, 0x67, 0x80, 0x24, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vftcisb %v4, %v21, 1656" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlip %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlip %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0xff, 0xff, 0x00, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlip %v0, 65535, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlip %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlip %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x10, 0x12, 0x34, 0x78, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlip %v17, 4660, 7" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x60, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllezlf %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x0f, 0xff, 0x60, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllezlf %v0, 4095" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x60, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllezlf %v0, 0(%r15)" + + - + input: + bytes: [ 0xe7, 0x0f, 0x10, 0x00, 0x60, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllezlf %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x60, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllezlf %v15, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x68, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllezlf %v31, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x45, 0x67, 0x68, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllezlf %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x35 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrl %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x00, 0x35 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrl %v0, 4095, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x35 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrl %v0, 0(%r15), 0" + + - + input: + bytes: [ 0xe6, 0xff, 0x00, 0x00, 0x00, 0x35 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrl %v0, 0, 255" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x35 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrl %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf1, 0x35 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrl %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x03, 0x45, 0x67, 0x21, 0x35 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrl %v18, 1383(%r4), 3" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x37 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrlr %v0, %r0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x00, 0x37 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrlr %v0, %r0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x37 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrlr %v0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x00, 0x37 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrlr %v0, %r15, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x37 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrlr %v15, %r0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf1, 0x37 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrlr %v31, %r0, 0" + + - + input: + bytes: [ 0xe6, 0x03, 0x45, 0x67, 0x21, 0x37 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlrlr %v18, %r3, 1383(%r4)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsl %v0, %v0, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x0f, 0x00, 0x00, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsl %v0, %v0, %v0, %v0, 15, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xc0, 0x00, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsl %v0, %v0, %v0, %v0, 0, 12" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xf0, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsl %v0, %v0, %v0, %v15, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xf1, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsl %v0, %v0, %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x00, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsl %v0, %v0, %v15, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x02, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsl %v0, %v0, %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x00, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsl %v0, %v15, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x04, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsl %v0, %v31, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x00, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsl %v15, %v0, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x08, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsl %v31, %v0, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x40, 0x5a, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsl %v18, %v3, %v20, %v5, 0, 4" + + - + input: + bytes: [ 0xe7, 0x23, 0x4b, 0x80, 0x5a, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsl %v18, %v3, %v20, %v5, 11, 8" + + - + input: + bytes: [ 0xe7, 0x00, 0x03, 0x00, 0x00, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmslg %v0, %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x03, 0xc0, 0x00, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmslg %v0, %v0, %v0, %v0, 12" + + - + input: + bytes: [ 0xe7, 0x00, 0x03, 0x00, 0xf0, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmslg %v0, %v0, %v0, %v15, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x03, 0x00, 0xf1, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmslg %v0, %v0, %v0, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf3, 0x00, 0x00, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmslg %v0, %v0, %v15, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf3, 0x00, 0x02, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmslg %v0, %v0, %v31, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x03, 0x00, 0x00, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmslg %v0, %v15, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x03, 0x00, 0x04, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmslg %v0, %v31, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x03, 0x00, 0x00, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmslg %v15, %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x03, 0x00, 0x08, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmslg %v31, %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x43, 0x40, 0x5a, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmslg %v18, %v3, %v20, %v5, 4" + + - + input: + bytes: [ 0xe7, 0x23, 0x43, 0x80, 0x5a, 0xb8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmslg %v18, %v3, %v20, %v5, 8" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmp %v0, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmp %v0, %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0xf0, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmp %v0, %v0, %v0, 255, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x02, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmp %v0, %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmp %v0, %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmp %v31, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xd1, 0x50, 0xb7, 0x96, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmp %v13, %v17, %v21, 121, 11" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x79 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsp %v0, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x79 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsp %v0, %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0xf0, 0x79 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsp %v0, %v0, %v0, 255, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x02, 0x79 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsp %v0, %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x79 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsp %v0, %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x79 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsp %v31, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xd1, 0x50, 0xb7, 0x96, 0x79 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vmsp %v13, %v17, %v21, 121, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x6e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vnn %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x02, 0x6e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vnn %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x04, 0x6e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vnn %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x08, 0x6e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vnn %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x6e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vnn %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x6c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vnx %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x02, 0x6c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vnx %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x04, 0x6c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vnx %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x08, 0x6c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vnx %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x6c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vnx %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x6f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "voc %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x02, 0x6f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "voc %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x04, 0x6f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "voc %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x08, 0x6f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "voc %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x00, 0x0a, 0x6f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "voc %v18, %v3, %v20" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkz %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x00, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkz %v0, 4095, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkz %v0, 0(%r15), 0" + + - + input: + bytes: [ 0xe6, 0xff, 0x00, 0x00, 0x00, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkz %v0, 0, 255" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkz %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf1, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkz %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x03, 0x45, 0x67, 0x21, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkz %v18, 1383(%r4), 3" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopctb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopctb %v0, %v15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x04, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopctb %v0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopctb %v15, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x08, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopctb %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x00, 0x04, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopctb %v14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopctf %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x20, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopctf %v0, %v15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopctf %v0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x20, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopctf %v15, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopctf %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x00, 0x24, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopctf %v14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x30, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopctg %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x30, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopctg %v0, %v15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x34, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopctg %v0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x30, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopctg %v15, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x38, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopctg %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x00, 0x34, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopctg %v14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x10, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopcth %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x10, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopcth %v0, %v15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x14, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopcth %v0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x10, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopcth %v15, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x18, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopcth %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x00, 0x14, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpopcth %v14, %v17" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x5b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpsop %v0, %v0, 0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x5b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpsop %v0, %v0, 0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0xff, 0x00, 0x00, 0x5b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpsop %v0, %v0, 0, 255, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0xf0, 0x5b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpsop %v0, %v0, 255, 0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x5b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpsop %v0, %v31, 0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x5b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpsop %v31, %v0, 0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xd1, 0x79, 0xb3, 0x44, 0x5b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpsop %v13, %v17, 52, 121, 11" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x7b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrp %v0, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x7b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrp %v0, %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0xf0, 0x7b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrp %v0, %v0, %v0, 255, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x02, 0x7b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrp %v0, %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x7b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrp %v0, %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x7b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrp %v31, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xd1, 0x50, 0xb7, 0x96, 0x7b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vrp %v13, %v17, %v21, 121, 11" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsdp %v0, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsdp %v0, %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0xf0, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsdp %v0, %v0, %v0, 255, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x02, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsdp %v0, %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsdp %v0, %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsdp %v31, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xd1, 0x50, 0xb7, 0x96, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsdp %v13, %v17, %v21, 121, 11" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsp %v0, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsp %v0, %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0xf0, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsp %v0, %v0, %v0, 255, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x02, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsp %v0, %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsp %v0, %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsp %v31, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xd1, 0x50, 0xb7, 0x96, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsp %v13, %v17, %v21, 121, 11" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrp %v0, %v0, 0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrp %v0, %v0, 0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0xff, 0x00, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrp %v0, %v0, 0, 255, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0xf0, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrp %v0, %v0, 255, 0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrp %v0, %v31, 0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrp %v31, %v0, 0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xd1, 0x79, 0xb3, 0x44, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrp %v13, %v17, 52, 121, 11" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x3d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrl %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x00, 0x3d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrl %v0, 4095, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x3d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrl %v0, 0(%r15), 0" + + - + input: + bytes: [ 0xe6, 0xff, 0x00, 0x00, 0x00, 0x3d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrl %v0, 0, 255" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x3d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrl %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf1, 0x3d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrl %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x03, 0x45, 0x67, 0x21, 0x3d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrl %v18, 1383(%r4), 3" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrlr %v0, %r0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x00, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrlr %v0, %r0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrlr %v0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x00, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrlr %v0, %r15, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrlr %v15, %r0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf1, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrlr %v31, %r0, 0" + + - + input: + bytes: [ 0xe6, 0x03, 0x45, 0x67, 0x21, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrlr %v18, %r3, 1383(%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vtp %v0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x00, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vtp %v15" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vtp %v31" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkz %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x00, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkz %v0, 4095, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkz %v0, 0(%r15), 0" + + - + input: + bytes: [ 0xe6, 0xff, 0x00, 0x00, 0x00, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkz %v0, 0, 255" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkz %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf1, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkz %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x03, 0x45, 0x67, 0x21, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkz %v18, 1383(%r4), 3" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfasb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfasb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x22, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfasb %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x24, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfasb %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x28, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfasb %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x2a, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfasb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x40, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfaxb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x42, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfaxb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x44, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfaxb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x48, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfaxb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x4a, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfaxb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcsb %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcsb %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x20, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcsb %f0, %f15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcsb %f0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x20, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcsb %f15, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcsb %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x00, 0x24, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcsb %f14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x40, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcxb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x40, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcxb %v0, %v15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x44, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcxb %v0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x40, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcxb %v15, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x48, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcxb %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x00, 0x44, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcxb %v14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcesb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcesb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x22, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcesb %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x24, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcesb %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x28, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcesb %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x2a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcesb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x18, 0x20, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcesbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x18, 0x20, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcesbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x18, 0x22, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcesbs %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x18, 0x24, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcesbs %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x18, 0x28, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcesbs %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x18, 0x2a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcesbs %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x40, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcexb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x42, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcexb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x44, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcexb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x48, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcexb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x4a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcexb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x18, 0x40, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcexbs %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x18, 0x42, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcexbs %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x18, 0x44, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcexbs %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x18, 0x48, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcexbs %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x18, 0x4a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfcexbs %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchsb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchsb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x22, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchsb %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x24, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchsb %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x28, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchsb %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x2a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchsb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x18, 0x20, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchsbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x18, 0x20, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchsbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x18, 0x22, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchsbs %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x18, 0x24, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchsbs %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x18, 0x28, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchsbs %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x18, 0x2a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchsbs %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x40, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchxb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x42, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchxb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x44, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchxb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x48, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchxb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x4a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchxb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x18, 0x40, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchxbs %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x18, 0x42, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchxbs %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x18, 0x44, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchxbs %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x18, 0x48, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchxbs %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x18, 0x4a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchxbs %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchesb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchesb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x22, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchesb %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x24, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchesb %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x28, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchesb %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x2a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchesb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x18, 0x20, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchesbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x18, 0x20, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchesbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x18, 0x22, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchesbs %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x18, 0x24, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchesbs %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x18, 0x28, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchesbs %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x18, 0x2a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchesbs %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x40, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchexb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x42, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchexb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x44, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchexb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x48, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchexb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x4a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchexb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x18, 0x40, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchexbs %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x18, 0x42, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchexbs %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x18, 0x44, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchexbs %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x18, 0x48, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchexbs %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x18, 0x4a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfchexbs %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfdsb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfdsb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x22, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfdsb %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x24, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfdsb %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x28, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfdsb %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x2a, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfdsb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x40, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfdxb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x42, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfdxb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x44, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfdxb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x48, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfdxb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x4a, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfdxb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfisb %f0, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfisb %f0, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xf8, 0x20, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfisb %f0, %f0, 0, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x20, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfisb %f0, %f0, 4, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0f, 0x20, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfisb %f0, %f0, 7, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x24, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfisb %f0, %v31, 0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x28, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfisb %v31, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0xac, 0x24, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfisb %f14, %v17, 4, 10" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x40, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfixb %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xf8, 0x40, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfixb %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x40, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfixb %v0, %v0, 4, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0f, 0x40, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfixb %v0, %v0, 7, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x44, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfixb %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x48, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfixb %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0xac, 0x44, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfixb %v14, %v17, 4, 10" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfksb %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfksb %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x20, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfksb %f0, %f15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfksb %f0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x20, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfksb %f15, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfksb %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x00, 0x24, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfksb %f14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x40, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkxb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x40, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkxb %v0, %v15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x44, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkxb %v0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x40, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkxb %v15, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x48, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkxb %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x00, 0x44, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkxb %v14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x30, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkedb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x30, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkedb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x0c, 0x32, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkedb %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x0c, 0x34, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkedb %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x0c, 0x38, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkedb %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x0c, 0x3a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkedb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x1c, 0x30, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkedbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x1c, 0x30, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkedbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x1c, 0x32, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkedbs %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x1c, 0x34, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkedbs %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x1c, 0x38, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkedbs %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x1c, 0x3a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkedbs %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x20, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkesb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x20, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkesb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x0c, 0x22, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkesb %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x0c, 0x24, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkesb %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x0c, 0x28, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkesb %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x0c, 0x2a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkesb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x1c, 0x20, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkesbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x1c, 0x20, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkesbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x1c, 0x22, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkesbs %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x1c, 0x24, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkesbs %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x1c, 0x28, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkesbs %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x1c, 0x2a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkesbs %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x40, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkexb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x0c, 0x42, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkexb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x0c, 0x44, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkexb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x0c, 0x48, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkexb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x0c, 0x4a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkexb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x1c, 0x40, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkexbs %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x1c, 0x42, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkexbs %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x1c, 0x44, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkexbs %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x1c, 0x48, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkexbs %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x1c, 0x4a, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkexbs %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x30, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhdb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x30, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhdb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x0c, 0x32, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhdb %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x0c, 0x34, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhdb %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x0c, 0x38, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhdb %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x0c, 0x3a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhdb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x1c, 0x30, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhdbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x1c, 0x30, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhdbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x1c, 0x32, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhdbs %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x1c, 0x34, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhdbs %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x1c, 0x38, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhdbs %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x1c, 0x3a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhdbs %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x20, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhsb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x20, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhsb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x0c, 0x22, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhsb %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x0c, 0x24, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhsb %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x0c, 0x28, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhsb %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x0c, 0x2a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhsb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x1c, 0x20, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhsbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x1c, 0x20, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhsbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x1c, 0x22, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhsbs %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x1c, 0x24, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhsbs %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x1c, 0x28, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhsbs %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x1c, 0x2a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhsbs %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x40, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhxb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x0c, 0x42, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhxb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x0c, 0x44, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhxb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x0c, 0x48, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhxb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x0c, 0x4a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhxb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x1c, 0x40, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhxbs %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x1c, 0x42, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhxbs %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x1c, 0x44, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhxbs %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x1c, 0x48, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhxbs %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x1c, 0x4a, 0xeb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhxbs %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x30, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhedb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x30, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhedb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x0c, 0x32, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhedb %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x0c, 0x34, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhedb %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x0c, 0x38, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhedb %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x0c, 0x3a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhedb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x1c, 0x30, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhedbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x1c, 0x30, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhedbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x1c, 0x32, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhedbs %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x1c, 0x34, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhedbs %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x1c, 0x38, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhedbs %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x1c, 0x3a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhedbs %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x20, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhesb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x20, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhesb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x0c, 0x22, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhesb %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x0c, 0x24, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhesb %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x0c, 0x28, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhesb %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x0c, 0x2a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhesb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x1c, 0x20, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhesbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x1c, 0x20, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhesbs %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x1c, 0x22, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhesbs %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x1c, 0x24, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhesbs %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x1c, 0x28, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhesbs %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x1c, 0x2a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhesbs %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x40, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhexb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x0c, 0x42, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhexb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x0c, 0x44, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhexb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x0c, 0x48, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhexb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x0c, 0x4a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhexb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x1c, 0x40, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhexbs %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x1c, 0x42, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhexbs %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x1c, 0x44, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhexbs %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x1c, 0x48, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhexbs %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x1c, 0x4a, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfkhexbs %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x38, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfpsosb %f0, %f0, 3" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x38, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfpsosb %f0, %f0, 3" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xf8, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfpsosb %f0, %f0, 15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x38, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfpsosb %f0, %f15, 3" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x38, 0x24, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfpsosb %f0, %v31, 3" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x38, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfpsosb %f15, %f0, 3" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x38, 0x28, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfpsosb %v31, %f0, 3" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x78, 0x24, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfpsosb %f14, %v17, 7" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x38, 0x40, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfpsoxb %v0, %v0, 3" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xf8, 0x40, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfpsoxb %v0, %v0, 15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x38, 0x40, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfpsoxb %v0, %v15, 3" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x38, 0x44, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfpsoxb %v0, %v31, 3" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x38, 0x40, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfpsoxb %v15, %v0, 3" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x38, 0x48, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfpsoxb %v31, %v0, 3" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x78, 0x44, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfpsoxb %v14, %v17, 7" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflcsb %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflcsb %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflcsb %f0, %f15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x24, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflcsb %f0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflcsb %f15, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x28, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflcsb %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x08, 0x24, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflcsb %f14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x40, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflcxb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x40, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflcxb %v0, %v15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x44, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflcxb %v0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x40, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflcxb %v15, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x48, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflcxb %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x08, 0x44, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflcxb %v14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x18, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflnsb %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x18, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflnsb %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x18, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflnsb %f0, %f15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x18, 0x24, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflnsb %f0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x18, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflnsb %f15, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x18, 0x28, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflnsb %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x18, 0x24, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflnsb %f14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x18, 0x40, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflnxb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x18, 0x40, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflnxb %v0, %v15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x18, 0x44, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflnxb %v0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x18, 0x40, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflnxb %v15, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x18, 0x48, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflnxb %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x18, 0x44, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflnxb %v14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x28, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflpsb %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x28, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflpsb %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x28, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflpsb %f0, %f15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x28, 0x24, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflpsb %f0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x28, 0x20, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflpsb %f15, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x28, 0x28, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflpsb %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x28, 0x24, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflpsb %f14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x28, 0x40, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflpxb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x28, 0x40, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflpxb %v0, %v15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x28, 0x44, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflpxb %v0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x28, 0x40, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflpxb %v15, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x28, 0x48, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflpxb %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x28, 0x44, 0xcc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflpxb %v14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflld %v0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflld %v0, %f0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x30, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflld %v0, %f15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x34, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflld %v0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x30, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflld %v15, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x38, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflld %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x08, 0x34, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflld %v14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x40, 0xc5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflrx %f0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x40, 0xc5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflrx %f0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xf8, 0x40, 0xc5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflrx %f0, %v0, 0, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x40, 0xc5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflrx %f0, %v0, 4, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0f, 0x40, 0xc5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflrx %f0, %v0, 7, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x44, 0xc5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflrx %f0, %v31, 0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x48, 0xc5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflrx %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0xac, 0x44, 0xc5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wflrx %f14, %v17, 4, 10" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxdb %f0, %f0, %f0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxdb %f0, %f0, %f0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x48, 0x30, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxdb %f0, %f0, %f0, 4" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x32, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxdb %f0, %f0, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x34, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxdb %f0, %v31, %f0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x38, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxdb %v31, %f0, %f0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0xb8, 0x3a, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxdb %v18, %f3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxsb %f0, %f0, %f0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxsb %f0, %f0, %f0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x48, 0x20, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxsb %f0, %f0, %f0, 4" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x22, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxsb %f0, %f0, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x24, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxsb %f0, %v31, %f0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x28, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxsb %v31, %f0, %f0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0xb8, 0x2a, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxsb %v18, %f3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x40, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxxb %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x48, 0x40, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxxb %v0, %v0, %v0, 4" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x42, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxxb %v0, %v0, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x44, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxxb %v0, %v31, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x48, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxxb %v31, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0xb8, 0x4a, 0xef ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxxb %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmindb %f0, %f0, %f0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x30, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmindb %f0, %f0, %f0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x48, 0x30, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmindb %f0, %f0, %f0, 4" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x32, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmindb %f0, %f0, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x34, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmindb %f0, %v31, %f0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x38, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmindb %v31, %f0, %f0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0xb8, 0x3a, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmindb %v18, %f3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfminsb %f0, %f0, %f0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfminsb %f0, %f0, %f0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x48, 0x20, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfminsb %f0, %f0, %f0, 4" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x22, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfminsb %f0, %f0, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x24, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfminsb %f0, %v31, %f0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x28, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfminsb %v31, %f0, %f0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0xb8, 0x2a, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfminsb %v18, %f3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x40, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfminxb %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x48, 0x40, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfminxb %v0, %v0, %v0, 4" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x42, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfminxb %v0, %v0, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x44, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfminxb %v0, %v31, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x48, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfminxb %v31, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0xb8, 0x4a, 0xee ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfminxb %v18, %v3, %v20, 11" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x08, 0x00, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmasb %f0, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x08, 0x00, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmasb %f0, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x08, 0xf1, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmasb %f0, %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0xf2, 0x08, 0x02, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmasb %f0, %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x02, 0x08, 0x04, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmasb %f0, %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x02, 0x08, 0x08, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmasb %v31, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x52, 0x08, 0x97, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmasb %f13, %v17, %v21, %v25" + + - + input: + bytes: [ 0xe7, 0x00, 0x04, 0x08, 0x00, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxb %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0x04, 0x08, 0xf1, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxb %v0, %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0xf4, 0x08, 0x02, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxb %v0, %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x04, 0x08, 0x04, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxb %v0, %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x04, 0x08, 0x08, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxb %v31, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x54, 0x08, 0x97, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmaxb %v13, %v17, %v21, %v25" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmsb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmsb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x22, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmsb %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x24, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmsb %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x28, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmsb %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x2a, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmsb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x40, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmxb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x42, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmxb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x44, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmxb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x48, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmxb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x4a, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmxb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x08, 0x00, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmssb %f0, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x08, 0x00, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmssb %f0, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x08, 0xf1, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmssb %f0, %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0xf2, 0x08, 0x02, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmssb %f0, %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x02, 0x08, 0x04, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmssb %f0, %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x02, 0x08, 0x08, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmssb %v31, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x52, 0x08, 0x97, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmssb %f13, %v17, %v21, %v25" + + - + input: + bytes: [ 0xe7, 0x00, 0x04, 0x08, 0x00, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmsxb %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0x04, 0x08, 0xf1, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmsxb %v0, %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0xf4, 0x08, 0x02, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmsxb %v0, %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x04, 0x08, 0x04, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmsxb %v0, %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x04, 0x08, 0x08, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmsxb %v31, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x54, 0x08, 0x97, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfmsxb %v13, %v17, %v21, %v25" + + - + input: + bytes: [ 0xe7, 0x00, 0x03, 0x08, 0x00, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmadb %f0, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x03, 0x08, 0x00, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmadb %f0, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x03, 0x08, 0xf1, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmadb %f0, %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0xf3, 0x08, 0x02, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmadb %f0, %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x03, 0x08, 0x04, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmadb %f0, %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x03, 0x08, 0x08, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmadb %v31, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x53, 0x08, 0x97, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmadb %f13, %v17, %v21, %v25" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x08, 0x00, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmasb %f0, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x08, 0x00, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmasb %f0, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x08, 0xf1, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmasb %f0, %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0xf2, 0x08, 0x02, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmasb %f0, %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x02, 0x08, 0x04, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmasb %f0, %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x02, 0x08, 0x08, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmasb %v31, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x52, 0x08, 0x97, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmasb %f13, %v17, %v21, %v25" + + - + input: + bytes: [ 0xe7, 0x00, 0x04, 0x08, 0x00, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmaxb %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0x04, 0x08, 0xf1, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmaxb %v0, %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0xf4, 0x08, 0x02, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmaxb %v0, %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x04, 0x08, 0x04, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmaxb %v0, %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x04, 0x08, 0x08, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmaxb %v31, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x54, 0x08, 0x97, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmaxb %v13, %v17, %v21, %v25" + + - + input: + bytes: [ 0xe7, 0x00, 0x03, 0x08, 0x00, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmsdb %f0, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x03, 0x08, 0x00, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmsdb %f0, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x03, 0x08, 0xf1, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmsdb %f0, %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0xf3, 0x08, 0x02, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmsdb %f0, %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x03, 0x08, 0x04, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmsdb %f0, %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x03, 0x08, 0x08, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmsdb %v31, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x53, 0x08, 0x97, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmsdb %f13, %v17, %v21, %v25" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x08, 0x00, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmssb %f0, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x08, 0x00, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmssb %f0, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x08, 0xf1, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmssb %f0, %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0xf2, 0x08, 0x02, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmssb %f0, %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x02, 0x08, 0x04, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmssb %f0, %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x02, 0x08, 0x08, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmssb %v31, %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x52, 0x08, 0x97, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmssb %f13, %v17, %v21, %v25" + + - + input: + bytes: [ 0xe7, 0x00, 0x04, 0x08, 0x00, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmsxb %v0, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0x04, 0x08, 0xf1, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmsxb %v0, %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x00, 0xf4, 0x08, 0x02, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmsxb %v0, %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x04, 0x08, 0x04, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmsxb %v0, %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x04, 0x08, 0x08, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmsxb %v31, %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x54, 0x08, 0x97, 0x9e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfnmsxb %v13, %v17, %v21, %v25" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfssb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfssb %f0, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x22, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfssb %f0, %f0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x24, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfssb %f0, %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x28, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfssb %v31, %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x2a, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfssb %v18, %f3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x40, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsxb %v0, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x08, 0x42, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsxb %v0, %v0, %v31" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x44, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsxb %v0, %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x48, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsxb %v31, %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x08, 0x4a, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsxb %v18, %v3, %v20" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsqsb %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsqsb %f0, %f0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x20, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsqsb %f0, %f15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x24, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsqsb %f0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x20, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsqsb %f15, %f0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x28, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsqsb %v31, %f0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x08, 0x24, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsqsb %f14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x40, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsqxb %v0, %v0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x40, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsqxb %v0, %v15" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x44, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsqxb %v0, %v31" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x40, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsqxb %v15, %v0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x48, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsqxb %v31, %v0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0x08, 0x44, 0xce ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wfsqxb %v14, %v17" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wftcisb %f0, %f0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wftcisb %f0, %f0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0xff, 0xf8, 0x20, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wftcisb %f0, %f0, 4095" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x20, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wftcisb %f0, %f15, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x24, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wftcisb %f0, %v31, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x20, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wftcisb %f15, %f0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x28, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wftcisb %v31, %f0, 0" + + - + input: + bytes: [ 0xe7, 0x45, 0x67, 0x88, 0x24, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wftcisb %f4, %v21, 1656" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x40, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wftcixb %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0xff, 0xf8, 0x40, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wftcixb %v0, %v0, 4095" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x40, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wftcixb %v0, %v15, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x44, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wftcixb %v0, %v31, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x40, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wftcixb %v15, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x48, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wftcixb %v31, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x45, 0x67, 0x88, 0x44, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z14", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wftcixb %v4, %v21, 1656" diff --git a/tests/MC/SystemZ/insns-z15.txt.yaml b/tests/MC/SystemZ/insns-z15.txt.yaml new file mode 100644 index 0000000000..8c8ff9e915 --- /dev/null +++ b/tests/MC/SystemZ/insns-z15.txt.yaml @@ -0,0 +1,4920 @@ +test_cases: + - + input: + bytes: [ 0xb9, 0x39, 0x20, 0x22 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dfltcc %r2, %r2, %r2" + + - + input: + bytes: [ 0xb9, 0x39, 0xf0, 0x28 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dfltcc %r2, %r8, %r15" + + - + input: + bytes: [ 0xb9, 0x39, 0x20, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dfltcc %r14, %r8, %r2" + + - + input: + bytes: [ 0xb9, 0x39, 0xa0, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dfltcc %r6, %r8, %r10" + + - + input: + bytes: [ 0xb9, 0x3a, 0x00, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kdsa %r0, %r2" + + - + input: + bytes: [ 0xb9, 0x3a, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kdsa %r0, %r14" + + - + input: + bytes: [ 0xb9, 0x3a, 0x00, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kdsa %r15, %r2" + + - + input: + bytes: [ 0xb9, 0x3a, 0x00, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kdsa %r7, %r10" + + - + input: + bytes: [ 0xe5, 0x0a, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcrl 0, 0" + + - + input: + bytes: [ 0xe5, 0x0a, 0x10, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcrl 0(%r1), 0(%r2)" + + - + input: + bytes: [ 0xe5, 0x0a, 0x10, 0xa0, 0xf1, 0x40 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcrl 160(%r1), 320(%r15)" + + - + input: + bytes: [ 0xe5, 0x0a, 0x10, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcrl 0(%r1), 4095" + + - + input: + bytes: [ 0xe5, 0x0a, 0x10, 0x00, 0x2f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcrl 0(%r1), 4095(%r2)" + + - + input: + bytes: [ 0xe5, 0x0a, 0x10, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcrl 0(%r1), 4095(%r15)" + + - + input: + bytes: [ 0xe5, 0x0a, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcrl 0(%r1), 0" + + - + input: + bytes: [ 0xe5, 0x0a, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcrl 0(%r15), 0" + + - + input: + bytes: [ 0xe5, 0x0a, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcrl 4095(%r1), 0" + + - + input: + bytes: [ 0xe5, 0x0a, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcrl 4095(%r15), 0" + + - + input: + bytes: [ 0xb9, 0xe5, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ncgrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xe5, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ncgrk %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xe5, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ncgrk %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xe5, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ncgrk %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xe5, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ncgrk %r7, %r8, %r9" + + - + input: + bytes: [ 0xb9, 0xf5, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ncrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xf5, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ncrk %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xf5, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ncrk %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xf5, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ncrk %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xf5, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ncrk %r7, %r8, %r9" + + - + input: + bytes: [ 0xb9, 0x64, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nngrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x64, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nngrk %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x64, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nngrk %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x64, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nngrk %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x64, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nngrk %r7, %r8, %r9" + + - + input: + bytes: [ 0xb9, 0x74, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nnrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x74, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nnrk %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x74, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nnrk %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x74, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nnrk %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x74, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nnrk %r7, %r8, %r9" + + - + input: + bytes: [ 0xb9, 0x66, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nogrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x66, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nogrk %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x66, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nogrk %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x66, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nogrk %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x66, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nogrk %r7, %r8, %r9" + + - + input: + bytes: [ 0xb9, 0x76, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nork %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x76, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nork %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x76, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nork %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x76, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nork %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x76, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nork %r7, %r8, %r9" + + - + input: + bytes: [ 0xb9, 0x67, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nxgrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x67, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nxgrk %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x67, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nxgrk %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x67, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nxgrk %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x67, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nxgrk %r7, %r8, %r9" + + - + input: + bytes: [ 0xb9, 0x77, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nxrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x77, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nxrk %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x77, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nxrk %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x77, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nxrk %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x77, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nxrk %r7, %r8, %r9" + + - + input: + bytes: [ 0xb9, 0x65, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ocgrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x65, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ocgrk %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x65, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ocgrk %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x65, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ocgrk %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x65, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ocgrk %r7, %r8, %r9" + + - + input: + bytes: [ 0xb9, 0x75, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ocrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x75, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ocrk %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x75, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ocrk %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x75, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ocrk %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x75, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ocrk %r7, %r8, %r9" + + - + input: + bytes: [ 0xb9, 0xe1, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "popcnt %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xe1, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "popcnt %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xe1, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "popcnt %r14, %r0" + + - + input: + bytes: [ 0xb9, 0xe1, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "popcnt %r6, %r8" + + - + input: + bytes: [ 0xb9, 0xe1, 0x10, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "popcnt %r4, %r13, 1" + + - + input: + bytes: [ 0xb9, 0xe1, 0xf0, 0x4d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "popcnt %r4, %r13, 15" + + - + input: + bytes: [ 0xb9, 0xe3, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selgr %r0, %r0, %r0, 0" + + - + input: + bytes: [ 0xb9, 0xe3, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selgr %r0, %r0, %r0, 15" + + - + input: + bytes: [ 0xb9, 0xe3, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selgr %r0, %r0, %r15, 0" + + - + input: + bytes: [ 0xb9, 0xe3, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selgr %r0, %r15, %r0, 0" + + - + input: + bytes: [ 0xb9, 0xe3, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selgr %r15, %r0, %r0, 0" + + - + input: + bytes: [ 0xb9, 0xe3, 0x31, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selgro %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xe3, 0x32, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selgrh %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xe3, 0x33, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selgrnle %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xe3, 0x34, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selgrl %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xe3, 0x35, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selgrnhe %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xe3, 0x36, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selgrlh %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xe3, 0x37, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selgrne %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xe3, 0x38, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selgre %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xe3, 0x39, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selgrnlh %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xe3, 0x3a, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selgrhe %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xe3, 0x3b, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selgrnl %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xe3, 0x3c, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selgrle %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xe3, 0x3d, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selgrnh %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xe3, 0x3e, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selgrno %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xc0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selfhr %r0, %r0, %r0, 0" + + - + input: + bytes: [ 0xb9, 0xc0, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selfhr %r0, %r0, %r0, 15" + + - + input: + bytes: [ 0xb9, 0xc0, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selfhr %r0, %r0, %r15, 0" + + - + input: + bytes: [ 0xb9, 0xc0, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selfhr %r0, %r15, %r0, 0" + + - + input: + bytes: [ 0xb9, 0xc0, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selfhr %r15, %r0, %r0, 0" + + - + input: + bytes: [ 0xb9, 0xc0, 0x31, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selfhro %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xc0, 0x32, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selfhrh %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xc0, 0x33, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selfhrnle %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xc0, 0x34, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selfhrl %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xc0, 0x35, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selfhrnhe %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xc0, 0x36, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selfhrlh %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xc0, 0x37, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selfhrne %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xc0, 0x38, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selfhre %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xc0, 0x39, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selfhrnlh %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xc0, 0x3a, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selfhrhe %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xc0, 0x3b, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selfhrnl %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xc0, 0x3c, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selfhrle %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xc0, 0x3d, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selfhrnh %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xc0, 0x3e, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selfhrno %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selr %r0, %r0, %r0, 0" + + - + input: + bytes: [ 0xb9, 0xf0, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selr %r0, %r0, %r0, 15" + + - + input: + bytes: [ 0xb9, 0xf0, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selr %r0, %r0, %r15, 0" + + - + input: + bytes: [ 0xb9, 0xf0, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selr %r0, %r15, %r0, 0" + + - + input: + bytes: [ 0xb9, 0xf0, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selr %r15, %r0, %r0, 0" + + - + input: + bytes: [ 0xb9, 0xf0, 0x31, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selro %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xf0, 0x32, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selrh %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xf0, 0x33, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selrnle %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xf0, 0x34, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selrl %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xf0, 0x35, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selrnhe %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xf0, 0x36, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selrlh %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xf0, 0x37, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selrne %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xf0, 0x38, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selre %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xf0, 0x39, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selrnlh %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xf0, 0x3a, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selrhe %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xf0, 0x3b, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selrnl %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xf0, 0x3c, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selrle %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xf0, 0x3d, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selrnh %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0xf0, 0x3e, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "selrno %r1, %r2, %r3" + + - + input: + bytes: [ 0xb9, 0x38, 0x00, 0x22 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sortl %r2, %r2" + + - + input: + bytes: [ 0xb9, 0x38, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sortl %r2, %r14" + + - + input: + bytes: [ 0xb9, 0x38, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sortl %r14, %r2" + + - + input: + bytes: [ 0xb9, 0x38, 0x00, 0x6a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sortl %r6, %r10" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcefb %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xf0, 0x20, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcefb %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x04, 0x20, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcefb %v0, %v0, 4, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcefb %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcefb %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0xa4, 0x24, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcefb %v14, %v17, 4, 10" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcelfb %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xf0, 0x20, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcelfb %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x04, 0x20, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcelfb %v0, %v0, 4, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcelfb %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcelfb %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0xa4, 0x24, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcelfb %v14, %v17, 4, 10" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcfeb %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xf0, 0x20, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcfeb %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x04, 0x20, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcfeb %v0, %v0, 4, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcfeb %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcfeb %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0xa4, 0x24, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcfeb %v14, %v17, 4, 10" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x20, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfeb %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xf0, 0x20, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfeb %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x04, 0x20, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfeb %v0, %v0, 4, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x24, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfeb %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x28, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfeb %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0xa4, 0x24, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfeb %v14, %v17, 4, 10" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvb %r0, %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x32, 0x00, 0x46, 0x04, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvb %r3, %v18, 4, 6" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0x00, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvbg %r0, %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x32, 0x00, 0x46, 0x04, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcvbg %r3, %v18, 4, 6" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbr %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbr %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x00, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbr %v0, 4095, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbr %v0, 0(%r15), 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbr %v0, 0(%r15,%r1), 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbr %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbr %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0xb8, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbr %v18, 1383(%r3,%r4), 11" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrf %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x20, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrf %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrf %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrf %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x20, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrf %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x28, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrf %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x28, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrf %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x30, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrg %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x30, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrg %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x30, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrg %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x30, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrg %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x30, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrg %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x38, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrg %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x38, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrg %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x10, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrh %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x10, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrh %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x10, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrh %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x10, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrh %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x10, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrh %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x18, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrh %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x18, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrh %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x40, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrq %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x40, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrq %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x40, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrq %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x40, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrq %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x40, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrq %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x48, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrq %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x48, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrq %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrep %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrep %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x00, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrep %v0, 4095, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrep %v0, 0(%r15), 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrep %v0, 0(%r15,%r1), 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrep %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrep %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0xb8, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrep %v18, 1383(%r3,%r4), 11" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrepf %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x20, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrepf %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrepf %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrepf %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x20, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrepf %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x28, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrepf %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x28, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrepf %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x30, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrepg %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x30, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrepg %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x30, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrepg %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x30, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrepg %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x30, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrepg %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x38, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrepg %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x38, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrrepg %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x10, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrreph %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x10, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrreph %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x10, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrreph %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x10, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrreph %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x10, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrreph %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x18, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrreph %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x18, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlbrreph %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrf %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x30, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrf %v0, 0, 3" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x00, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrf %v0, 4095, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrf %v0, 0(%r15), 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrf %v0, 0(%r15,%r1), 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrf %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrf %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x28, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrf %v18, 1383(%r3,%r4), 2" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrg %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x10, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrg %v0, 0, 1" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x00, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrg %v0, 4095, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrg %v0, 0(%r15), 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrg %v0, 0(%r15,%r1), 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrg %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrg %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x18, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrg %v18, 1383(%r3,%r4), 1" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrh %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x70, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrh %v0, 0, 7" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrh %v0, 4095, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrh %v0, 0(%r15), 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrh %v0, 0(%r15,%r1), 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrh %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrh %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x48, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlebrh %v18, 1383(%r3,%r4), 4" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vler %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vler %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x00, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vler %v0, 4095, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vler %v0, 0(%r15), 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vler %v0, 0(%r15,%r1), 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vler %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vler %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0xb8, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vler %v18, 1383(%r3,%r4), 11" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x20, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerf %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x20, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerf %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x20, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerf %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x20, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerf %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x20, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerf %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x28, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerf %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x28, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerf %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x30, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerg %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x30, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerg %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x30, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerg %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x30, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerg %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x30, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerg %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x38, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerg %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x38, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerg %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x10, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerh %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x10, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerh %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x10, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerh %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x10, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerh %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x10, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerh %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x18, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerh %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x18, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vlerh %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrz %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrz %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrz %v0, 4095, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrz %v0, 0(%r15), 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrz %v0, 0(%r15,%r1), 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrz %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrz %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0xb8, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrz %v18, 1383(%r3,%r4), 11" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x60, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrze %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x60, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrze %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x60, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrze %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x60, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrze %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x60, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrze %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x68, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrze %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x68, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrze %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzf %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x20, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzf %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzf %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzf %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x20, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzf %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x28, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzf %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x28, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzf %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x30, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzg %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x30, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzg %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x30, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzg %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x30, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzg %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x30, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzg %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x38, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzg %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x38, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzg %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzh %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x10, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzh %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzh %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzh %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x10, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzh %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x18, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzh %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x18, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vllebrzh %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x86 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsld %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xff, 0x00, 0x86 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsld %v0, %v0, %v0, 255" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x02, 0x86 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsld %v0, %v0, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x04, 0x86 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsld %v0, %v31, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x08, 0x86 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsld %v31, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x50, 0x79, 0x06, 0x86 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsld %v13, %v17, %v21, 121" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrd %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xff, 0x00, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrd %v0, %v0, %v0, 255" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x02, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrd %v0, %v0, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x04, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrd %v0, %v31, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x08, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrd %v31, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xd1, 0x50, 0x79, 0x06, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrd %v13, %v17, %v21, 121" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbr %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbr %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbr %v0, 4095, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbr %v0, 0(%r15), 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbr %v0, 0(%r15,%r1), 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbr %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbr %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0xb8, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbr %v18, 1383(%r3,%r4), 11" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x20, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrf %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x20, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrf %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x20, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrf %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x20, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrf %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x20, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrf %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x28, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrf %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x28, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrf %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x30, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrg %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x30, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrg %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x30, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrg %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x30, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrg %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x30, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrg %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x38, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrg %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x38, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrg %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x10, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrh %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x10, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrh %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x10, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrh %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x10, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrh %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x10, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrh %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x18, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrh %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x18, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrh %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x40, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrq %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x40, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrq %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x40, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrq %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x40, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrq %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x40, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrq %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x48, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrq %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x48, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstbrq %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrf %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x30, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrf %v0, 0, 3" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrf %v0, 4095, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrf %v0, 0(%r15), 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrf %v0, 0(%r15,%r1), 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrf %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrf %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x28, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrf %v18, 1383(%r3,%r4), 2" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrg %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x10, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrg %v0, 0, 1" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrg %v0, 4095, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrg %v0, 0(%r15), 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrg %v0, 0(%r15,%r1), 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrg %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrg %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x18, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrg %v18, 1383(%r3,%r4), 1" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrh %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x70, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrh %v0, 0, 7" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrh %v0, 4095, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrh %v0, 0(%r15), 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrh %v0, 0(%r15,%r1), 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrh %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrh %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x48, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstebrh %v18, 1383(%r3,%r4), 4" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vster %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vster %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vster %v0, 4095, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vster %v0, 0(%r15), 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vster %v0, 0(%r15,%r1), 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vster %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vster %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0xb8, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vster %v18, 1383(%r3,%r4), 11" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x20, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterf %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x20, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterf %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x20, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterf %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x20, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterf %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x20, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterf %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x28, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterf %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x28, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterf %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x30, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterg %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x30, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterg %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x30, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterg %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x30, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterg %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x30, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterg %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x38, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterg %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x38, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterg %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x10, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterh %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x0f, 0xff, 0x10, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterh %v0, 4095" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x10, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterh %v0, 0(%r15)" + + - + input: + bytes: [ 0xe6, 0x0f, 0x10, 0x00, 0x10, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterh %v0, 0(%r15,%r1)" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x10, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterh %v15, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x18, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterh %v31, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x45, 0x67, 0x18, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsterh %v18, 1383(%r3,%r4)" + + - + input: + bytes: [ 0xe7, 0x00, 0x0b, 0x00, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrs %v0, %v0, %v0, %v0, 11, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x0b, 0xc0, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrs %v0, %v0, %v0, %v0, 11, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x4b, 0x00, 0x5a, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrs %v18, %v3, %v20, %v5, 11, 0" + + - + input: + bytes: [ 0xe7, 0xff, 0xfb, 0x40, 0xff, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrs %v31, %v31, %v31, %v31, 11, 4" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsb %v0, %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsb %v0, %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xc0, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsb %v0, %v0, %v0, %v0, 12" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xf0, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsb %v0, %v0, %v0, %v15, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x00, 0xf1, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsb %v0, %v0, %v0, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsb %v0, %v0, %v15, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf0, 0x00, 0x02, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsb %v0, %v0, %v31, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsb %v0, %v15, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x00, 0x04, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsb %v0, %v31, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsb %v15, %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x00, 0x08, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsb %v31, %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x40, 0x5a, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsb %v18, %v3, %v20, %v5, 4" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0xc0, 0x5a, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsb %v18, %v3, %v20, %v5, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x40, 0x20, 0x5a, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrszb %v18, %v3, %v20, %v5" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsf %v0, %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsf %v0, %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0xc0, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsf %v0, %v0, %v0, %v0, 12" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0xf0, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsf %v0, %v0, %v0, %v15, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x02, 0x00, 0xf1, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsf %v0, %v0, %v0, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf2, 0x00, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsf %v0, %v0, %v15, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf2, 0x00, 0x02, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsf %v0, %v0, %v31, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x02, 0x00, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsf %v0, %v15, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x02, 0x00, 0x04, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsf %v0, %v31, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x02, 0x00, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsf %v15, %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x02, 0x00, 0x08, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsf %v31, %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x42, 0x40, 0x5a, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsf %v18, %v3, %v20, %v5, 4" + + - + input: + bytes: [ 0xe7, 0x23, 0x42, 0xc0, 0x5a, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsf %v18, %v3, %v20, %v5, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x42, 0x20, 0x5a, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrszf %v18, %v3, %v20, %v5" + + - + input: + bytes: [ 0xe7, 0x00, 0x01, 0x00, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsh %v0, %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x01, 0x00, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsh %v0, %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x01, 0xc0, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsh %v0, %v0, %v0, %v0, 12" + + - + input: + bytes: [ 0xe7, 0x00, 0x01, 0x00, 0xf0, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsh %v0, %v0, %v0, %v15, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x01, 0x00, 0xf1, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsh %v0, %v0, %v0, %v31, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf1, 0x00, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsh %v0, %v0, %v15, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0xf1, 0x00, 0x02, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsh %v0, %v0, %v31, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x01, 0x00, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsh %v0, %v15, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x01, 0x00, 0x04, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsh %v0, %v31, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x01, 0x00, 0x00, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsh %v15, %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x01, 0x00, 0x08, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsh %v31, %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe7, 0x23, 0x41, 0x40, 0x5a, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsh %v18, %v3, %v20, %v5, 4" + + - + input: + bytes: [ 0xe7, 0x23, 0x41, 0xc0, 0x5a, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrsh %v18, %v3, %v20, %v5, 12" + + - + input: + bytes: [ 0xe7, 0x23, 0x41, 0x20, 0x5a, 0x8b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vstrszh %v18, %v3, %v20, %v5" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcefb %f0, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcefb %f0, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xf8, 0x20, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcefb %f0, %f0, 0, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x20, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcefb %f0, %f0, 4, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x24, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcefb %f0, %v31, 0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x28, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcefb %v31, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0xac, 0x24, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcefb %f14, %v17, 4, 10" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcelfb %f0, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcelfb %f0, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xf8, 0x20, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcelfb %f0, %f0, 0, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x20, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcelfb %f0, %f0, 4, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x24, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcelfb %f0, %v31, 0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x28, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcelfb %v31, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0xac, 0x24, 0xc1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcelfb %f14, %v17, 4, 10" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcfeb %f0, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcfeb %f0, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xf8, 0x20, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcfeb %f0, %f0, 0, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x20, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcfeb %f0, %f0, 4, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x24, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcfeb %f0, %v31, 0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x28, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcfeb %v31, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0xac, 0x24, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wcfeb %f14, %v17, 4, 10" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wclfeb %f0, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x08, 0x20, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wclfeb %f0, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0xf8, 0x20, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wclfeb %f0, %f0, 0, 15" + + - + input: + bytes: [ 0xe7, 0x00, 0x00, 0x0c, 0x20, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wclfeb %f0, %f0, 4, 0" + + - + input: + bytes: [ 0xe7, 0x0f, 0x00, 0x08, 0x24, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wclfeb %f0, %v31, 0, 0" + + - + input: + bytes: [ 0xe7, 0xf0, 0x00, 0x08, 0x28, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wclfeb %v31, %f0, 0, 0" + + - + input: + bytes: [ 0xe7, 0xe1, 0x00, 0xac, 0x24, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z15", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "wclfeb %f14, %v17, 4, 10" diff --git a/tests/MC/SystemZ/insns-z16.txt.yaml b/tests/MC/SystemZ/insns-z16.txt.yaml new file mode 100644 index 0000000000..d32c689af4 --- /dev/null +++ b/tests/MC/SystemZ/insns-z16.txt.yaml @@ -0,0 +1,1650 @@ +test_cases: + - + input: + bytes: [ 0xb2, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbear 0" + + - + input: + bytes: [ 0xb2, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbear 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbear 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbear 4095" + + - + input: + bytes: [ 0xb2, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbear 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbear 4095(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpswey -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpswey -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpswey 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpswey 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpswey 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpswey 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpswey 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpswey 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpswey 524287(%r15)" + + - + input: + bytes: [ 0xb9, 0x3b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nnpa" + + - + input: + bytes: [ 0xb2, 0x8f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qpaci 0" + + - + input: + bytes: [ 0xb2, 0x8f, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qpaci 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x8f, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qpaci 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x8f, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qpaci 4095" + + - + input: + bytes: [ 0xb2, 0x8f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qpaci 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x8f, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qpaci 4095(%r15)" + + - + input: + bytes: [ 0xb9, 0x8b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rdp %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x8b, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rdp %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x8b, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rdp %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x8b, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rdp %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x8b, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rdp %r0, %r0, %r0, 15" + + - + input: + bytes: [ 0xb9, 0x8b, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rdp %r4, %r5, %r6, 7" + + - + input: + bytes: [ 0xb2, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stbear 0" + + - + input: + bytes: [ 0xb2, 0x01, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stbear 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x01, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stbear 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x01, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stbear 4095" + + - + input: + bytes: [ 0xb2, 0x01, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stbear 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stbear 4095(%r15)" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x5d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcfn %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x5d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcfn %v0, %v0, 15, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0x00, 0x5d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcfn %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x00, 0x5d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcfn %v0, %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x5d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcfn %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x5d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcfn %v15, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x5d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcfn %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xe1, 0x00, 0x09, 0xb4, 0x5d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcfn %v14, %v17, 11, 9" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x5e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfnl %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x5e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfnl %v0, %v0, 15, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0x00, 0x5e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfnl %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x00, 0x5e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfnl %v0, %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x5e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfnl %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x5e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfnl %v15, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x5e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfnl %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xe1, 0x00, 0x09, 0xb4, 0x5e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfnl %v14, %v17, 11, 9" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfnh %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfnh %v0, %v0, 15, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfnh %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfnh %v0, %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfnh %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfnh %v15, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfnh %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xe1, 0x00, 0x09, 0xb4, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclfnh %v14, %v17, 11, 9" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcnf %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcnf %v0, %v0, 15, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcnf %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcnf %v0, %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcnf %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcnf %v15, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcnf %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xe1, 0x00, 0x09, 0xb4, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcnf %v14, %v17, 11, 9" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcrnf %v0, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcrnf %v0, %v0, %v0, 15, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0x00, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcrnf %v0, %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x02, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcrnf %v0, %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcrnf %v0, %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcrnf %v31, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x40, 0x09, 0xba, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcrnf %v18, %v3, %v20, 11, 9" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclzdp %v0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclzdp %v0, %v0, 15" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclzdp %v0, %v15, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclzdp %v0, %v31, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclzdp %v15, %v0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclzdp %v31, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x00, 0xc0, 0x08, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vclzdp %v18, %v3, 12" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x7d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcsph %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x7d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcsph %v0, %v0, %v0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x7d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcsph %v0, %v0, %v15, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x02, 0x7d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcsph %v0, %v0, %v31, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x00, 0x7d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcsph %v0, %v15, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x7d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcsph %v0, %v31, %v0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x7d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcsph %v15, %v0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x7d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcsph %v31, %v0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x40, 0xc0, 0x0a, 0x7d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vcsph %v18, %v3, %v20, 12" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkzr %v0, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkzr %v0, %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0xf0, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkzr %v0, %v0, %v0, 255, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x02, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkzr %v0, %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkzr %v0, %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkzr %v31, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xd1, 0x50, 0xb7, 0x96, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vpkzr %v13, %v17, %v21, 121, 11" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschp %v0, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschp %v0, %v0, %v0, 15, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschp %v0, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0xf0, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschp %v0, %v0, %v0, 15, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xc0, 0x00, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschp %v0, %v0, %v0, 0, 12" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x00, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschp %v0, %v0, %v15, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x02, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschp %v0, %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x00, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschp %v0, %v15, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschp %v0, %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschp %v15, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschp %v31, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x40, 0x40, 0xba, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschp %v18, %v3, %v20, 11, 4" + + - + input: + bytes: [ 0xe6, 0x23, 0x40, 0xf0, 0x0a, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschp %v18, %v3, %v20, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x20, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschsp %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x20, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschsp %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xc0, 0x20, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschsp %v0, %v0, %v0, 12" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x20, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschsp %v0, %v0, %v15, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x22, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschsp %v0, %v0, %v31, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x20, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschsp %v0, %v15, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x24, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschsp %v0, %v31, %v0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x20, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschsp %v15, %v0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x28, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschsp %v31, %v0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x40, 0x00, 0x2a, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschsp %v18, %v3, %v20, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x30, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschdp %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x30, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschdp %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xc0, 0x30, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschdp %v0, %v0, %v0, 12" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x30, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschdp %v0, %v0, %v15, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x32, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschdp %v0, %v0, %v31, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x30, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschdp %v0, %v15, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x34, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschdp %v0, %v31, %v0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x30, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschdp %v15, %v0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x38, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschdp %v31, %v0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x40, 0x00, 0x3a, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschdp %v18, %v3, %v20, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x40, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschxp %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x40, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschxp %v0, %v0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xc0, 0x40, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschxp %v0, %v0, %v0, 12" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x40, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschxp %v0, %v0, %v15, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x42, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschxp %v0, %v0, %v31, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x40, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschxp %v0, %v15, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x44, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschxp %v0, %v31, %v0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x40, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschxp %v15, %v0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x48, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschxp %v31, %v0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x40, 0x00, 0x4a, 0x74 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vschxp %v18, %v3, %v20, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x7c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscshp %v0, %v0, %v0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x02, 0x7c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscshp %v0, %v0, %v31" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x7c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscshp %v0, %v31, %v0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x7c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscshp %v31, %v0, %v0" + + - + input: + bytes: [ 0xe6, 0x23, 0x40, 0x00, 0x0a, 0x7c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vscshp %v18, %v3, %v20" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrpr %v0, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrpr %v0, %v0, %v0, 0, 15" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x0f, 0xf0, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrpr %v0, %v0, %v0, 255, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0xf0, 0x00, 0x02, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrpr %v0, %v0, %v31, 0, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrpr %v0, %v31, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrpr %v31, %v0, %v0, 0, 0" + + - + input: + bytes: [ 0xe6, 0xd1, 0x50, 0xb7, 0x96, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vsrpr %v13, %v17, %v21, 121, 11" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkzh %v0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkzh %v0, %v0, 15" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkzh %v0, %v15, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkzh %v0, %v31, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkzh %v15, %v0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkzh %v31, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x00, 0xc0, 0x08, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkzh %v18, %v3, 12" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0x00, 0x00, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkzl %v0, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x00, 0x00, 0xf0, 0x00, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkzl %v0, %v0, 15" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x00, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkzl %v0, %v15, 0" + + - + input: + bytes: [ 0xe6, 0x0f, 0x00, 0x00, 0x04, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkzl %v0, %v31, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x00, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkzl %v15, %v0, 0" + + - + input: + bytes: [ 0xe6, 0xf0, 0x00, 0x00, 0x08, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkzl %v31, %v0, 0" + + - + input: + bytes: [ 0xe6, 0x23, 0x00, 0xc0, 0x08, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z16", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "vupkzl %v18, %v3, 12" diff --git a/tests/MC/SystemZ/insns.txt.yaml b/tests/MC/SystemZ/insns.txt.yaml new file mode 100644 index 0000000000..08d705b428 --- /dev/null +++ b/tests/MC/SystemZ/insns.txt.yaml @@ -0,0 +1,62770 @@ +test_cases: + - + input: + bytes: [ 0x5a, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "a %r0, 0" + + - + input: + bytes: [ 0x5a, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "a %r0, 4095" + + - + input: + bytes: [ 0x5a, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "a %r0, 0(%r1)" + + - + input: + bytes: [ 0x5a, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "a %r0, 0(%r15)" + + - + input: + bytes: [ 0x5a, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "a %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x5a, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "a %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x5a, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "a %r15, 0" + + - + input: + bytes: [ 0x6a, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ad %f0, 0" + + - + input: + bytes: [ 0x6a, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ad %f0, 4095" + + - + input: + bytes: [ 0x6a, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ad %f0, 0(%r1)" + + - + input: + bytes: [ 0x6a, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ad %f0, 0(%r15)" + + - + input: + bytes: [ 0x6a, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ad %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x6a, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ad %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x6a, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ad %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adb %f15, 0" + + - + input: + bytes: [ 0xb3, 0x1a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adbr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x1a, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adbr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x1a, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adbr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x1a, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adbr %f15, %f0" + + - + input: + bytes: [ 0x2a, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adr %f0, %f0" + + - + input: + bytes: [ 0x2a, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adr %f0, %f15" + + - + input: + bytes: [ 0x2a, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adr %f7, %f8" + + - + input: + bytes: [ 0x2a, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0xd2, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adtr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xd2, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adtr %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0xd2, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adtr %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0xd2, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adtr %f15, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xd2, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adtr %f7, %f8, %f9" + + - + input: + bytes: [ 0xb3, 0xd2, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adtra %f0, %f0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xd2, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adtra %f0, %f0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xd2, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adtra %f0, %f0, %f15, 1" + + - + input: + bytes: [ 0xb3, 0xd2, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adtra %f0, %f15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xd2, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adtra %f15, %f0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xd2, 0x9a, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "adtra %f7, %f8, %f9, 10" + + - + input: + bytes: [ 0x7a, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ae %f0, 0" + + - + input: + bytes: [ 0x7a, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ae %f0, 4095" + + - + input: + bytes: [ 0x7a, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ae %f0, 0(%r1)" + + - + input: + bytes: [ 0x7a, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ae %f0, 0(%r15)" + + - + input: + bytes: [ 0x7a, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ae %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x7a, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ae %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x7a, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ae %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aeb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aeb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aeb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aeb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aeb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aeb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aeb %f15, 0" + + - + input: + bytes: [ 0xb3, 0x0a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aebr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x0a, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aebr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x0a, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aebr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x0a, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aebr %f15, %f0" + + - + input: + bytes: [ 0x3a, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aer %f0, %f0" + + - + input: + bytes: [ 0x3a, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aer %f0, %f15" + + - + input: + bytes: [ 0x3a, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aer %f7, %f8" + + - + input: + bytes: [ 0x3a, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aer %f15, %f0" + + - + input: + bytes: [ 0xc2, 0x09, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "afi %r0, -2147483648" + + - + input: + bytes: [ 0xc2, 0x09, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "afi %r0, -1" + + - + input: + bytes: [ 0xc2, 0x09, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "afi %r0, 0" + + - + input: + bytes: [ 0xc2, 0x09, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "afi %r0, 1" + + - + input: + bytes: [ 0xc2, 0x09, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "afi %r0, 2147483647" + + - + input: + bytes: [ 0xc2, 0xf9, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "afi %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ag %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ag %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ag %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ag %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ag %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ag %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ag %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ag %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ag %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ag %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x18 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agf %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x18 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agf %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agf %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x18 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agf %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x18 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agf %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agf %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agf %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x18 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agf %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x18 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agf %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agf %r15, 0" + + - + input: + bytes: [ 0xc2, 0x08, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agfi %r0, -2147483648" + + - + input: + bytes: [ 0xc2, 0x08, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agfi %r0, -1" + + - + input: + bytes: [ 0xc2, 0x08, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agfi %r0, 0" + + - + input: + bytes: [ 0xc2, 0x08, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agfi %r0, 1" + + - + input: + bytes: [ 0xc2, 0x08, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agfi %r0, 2147483647" + + - + input: + bytes: [ 0xc2, 0xf8, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agfi %r15, 0" + + - + input: + bytes: [ 0xb9, 0x18, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agfr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x18, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agfr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x18, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agfr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x18, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agfr %r7, %r8" + + - + input: + bytes: [ 0xa7, 0x0b, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aghi %r0, -32768" + + - + input: + bytes: [ 0xa7, 0x0b, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aghi %r0, -1" + + - + input: + bytes: [ 0xa7, 0x0b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aghi %r0, 0" + + - + input: + bytes: [ 0xa7, 0x0b, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aghi %r0, 1" + + - + input: + bytes: [ 0xa7, 0x0b, 0x7f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aghi %r0, 32767" + + - + input: + bytes: [ 0xa7, 0xfb, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aghi %r15, 0" + + - + input: + bytes: [ 0xec, 0x01, 0x80, 0x00, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aghik %r0, %r1, -32768" + + - + input: + bytes: [ 0xec, 0x23, 0xff, 0xff, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aghik %r2, %r3, -1" + + - + input: + bytes: [ 0xec, 0x45, 0x00, 0x00, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aghik %r4, %r5, 0" + + - + input: + bytes: [ 0xec, 0x67, 0x00, 0x01, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aghik %r6, %r7, 1" + + - + input: + bytes: [ 0xec, 0x8f, 0x7f, 0xff, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aghik %r8, %r15, 32767" + + - + input: + bytes: [ 0xb9, 0x08, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x08, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x08, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x08, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0xe8, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xe8, 0x40, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agrk %r2, %r3, %r4" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agsi -524288, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agsi -1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agsi 0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agsi 1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agsi 524287, 0" + + - + input: + bytes: [ 0xeb, 0x80, 0x00, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agsi 0, -128" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agsi 0, -1" + + - + input: + bytes: [ 0xeb, 0x01, 0x00, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agsi 0, 1" + + - + input: + bytes: [ 0xeb, 0x7f, 0x00, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agsi 0, 127" + + - + input: + bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agsi 0(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agsi 0(%r15), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agsi 524287(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "agsi 524287(%r15), 42" + + - + input: + bytes: [ 0x4a, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ah %r0, 0" + + - + input: + bytes: [ 0x4a, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ah %r0, 4095" + + - + input: + bytes: [ 0x4a, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ah %r0, 0(%r1)" + + - + input: + bytes: [ 0x4a, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ah %r0, 0(%r15)" + + - + input: + bytes: [ 0x4a, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ah %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x4a, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ah %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x4a, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ah %r15, 0" + + - + input: + bytes: [ 0xb9, 0xc8, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahhhr %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xc8, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahhhr %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xc8, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahhhr %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xc8, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahhhr %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xc8, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahhhr %r7, %r8, %r9" + + - + input: + bytes: [ 0xb9, 0xd8, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahhlr %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xd8, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahhlr %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xd8, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahhlr %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xd8, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahhlr %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xd8, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahhlr %r7, %r8, %r9" + + - + input: + bytes: [ 0xa7, 0x0a, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahi %r0, -32768" + + - + input: + bytes: [ 0xa7, 0x0a, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahi %r0, -1" + + - + input: + bytes: [ 0xa7, 0x0a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahi %r0, 0" + + - + input: + bytes: [ 0xa7, 0x0a, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahi %r0, 1" + + - + input: + bytes: [ 0xa7, 0x0a, 0x7f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahi %r0, 32767" + + - + input: + bytes: [ 0xa7, 0xfa, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahi %r15, 0" + + - + input: + bytes: [ 0xec, 0x01, 0x80, 0x00, 0x00, 0xd8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahik %r0, %r1, -32768" + + - + input: + bytes: [ 0xec, 0x23, 0xff, 0xff, 0x00, 0xd8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahik %r2, %r3, -1" + + - + input: + bytes: [ 0xec, 0x45, 0x00, 0x00, 0x00, 0xd8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahik %r4, %r5, 0" + + - + input: + bytes: [ 0xec, 0x67, 0x00, 0x01, 0x00, 0xd8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahik %r6, %r7, 1" + + - + input: + bytes: [ 0xec, 0x8f, 0x7f, 0xff, 0x00, 0xd8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahik %r8, %r15, 32767" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahy %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahy %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahy %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahy %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahy %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahy %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahy %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahy %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahy %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x7a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ahy %r15, 0" + + - + input: + bytes: [ 0xcc, 0x08, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aih %r0, -2147483648" + + - + input: + bytes: [ 0xcc, 0x08, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aih %r0, -1" + + - + input: + bytes: [ 0xcc, 0x08, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aih %r0, 0" + + - + input: + bytes: [ 0xcc, 0x08, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aih %r0, 1" + + - + input: + bytes: [ 0xcc, 0x08, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aih %r0, 2147483647" + + - + input: + bytes: [ 0xcc, 0xf8, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aih %r15, 0" + + - + input: + bytes: [ 0x5e, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "al %r0, 0" + + - + input: + bytes: [ 0x5e, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "al %r0, 4095" + + - + input: + bytes: [ 0x5e, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "al %r0, 0(%r1)" + + - + input: + bytes: [ 0x5e, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "al %r0, 0(%r15)" + + - + input: + bytes: [ 0x5e, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "al %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x5e, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "al %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x5e, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "al %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alc %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alc %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alc %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alc %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alc %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alc %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alc %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alc %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alc %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alc %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alcg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alcg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alcg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alcg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alcg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alcg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alcg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alcg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alcg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alcg %r15, 0" + + - + input: + bytes: [ 0xb9, 0x88, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alcgr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x88, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alcgr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x88, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alcgr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x88, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alcgr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x98, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alcr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x98, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alcr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x98, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alcr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x98, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alcr %r7, %r8" + + - + input: + bytes: [ 0xc2, 0x0b, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alfi %r0, 0" + + - + input: + bytes: [ 0xc2, 0x0b, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alfi %r0, 4294967295" + + - + input: + bytes: [ 0xc2, 0xfb, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alfi %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alg %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algf %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algf %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algf %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algf %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algf %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algf %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algf %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algf %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algf %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x1a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algf %r15, 0" + + - + input: + bytes: [ 0xc2, 0x0a, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algfi %r0, 0" + + - + input: + bytes: [ 0xc2, 0x0a, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algfi %r0, 4294967295" + + - + input: + bytes: [ 0xc2, 0xfa, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algfi %r15, 0" + + - + input: + bytes: [ 0xb9, 0x1a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algfr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x1a, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algfr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x1a, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algfr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x1a, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algfr %r7, %r8" + + - + input: + bytes: [ 0xec, 0x01, 0x80, 0x00, 0x00, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alghsik %r0, %r1, -32768" + + - + input: + bytes: [ 0xec, 0x23, 0xff, 0xff, 0x00, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alghsik %r2, %r3, -1" + + - + input: + bytes: [ 0xec, 0x45, 0x00, 0x00, 0x00, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alghsik %r4, %r5, 0" + + - + input: + bytes: [ 0xec, 0x67, 0x00, 0x01, 0x00, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alghsik %r6, %r7, 1" + + - + input: + bytes: [ 0xec, 0x8f, 0x7f, 0xff, 0x00, 0xdb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alghsik %r8, %r15, 32767" + + - + input: + bytes: [ 0xb9, 0x0a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x0a, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x0a, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x0a, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0xea, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xea, 0x40, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algrk %r2, %r3, %r4" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algsi -524288, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algsi -1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algsi 0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algsi 1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algsi 524287, 0" + + - + input: + bytes: [ 0xeb, 0x80, 0x00, 0x00, 0x00, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algsi 0, -128" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algsi 0, -1" + + - + input: + bytes: [ 0xeb, 0x01, 0x00, 0x00, 0x00, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algsi 0, 1" + + - + input: + bytes: [ 0xeb, 0x7f, 0x00, 0x00, 0x00, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algsi 0, 127" + + - + input: + bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algsi 0(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algsi 0(%r15), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algsi 524287(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x7e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "algsi 524287(%r15), 42" + + - + input: + bytes: [ 0xb9, 0xca, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alhhhr %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xca, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alhhhr %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xca, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alhhhr %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xca, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alhhhr %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xca, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alhhhr %r7, %r8, %r9" + + - + input: + bytes: [ 0xb9, 0xda, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alhhlr %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xda, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alhhlr %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xda, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alhhlr %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xda, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alhhlr %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xda, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alhhlr %r7, %r8, %r9" + + - + input: + bytes: [ 0xec, 0x01, 0x80, 0x00, 0x00, 0xda ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alhsik %r0, %r1, -32768" + + - + input: + bytes: [ 0xec, 0x23, 0xff, 0xff, 0x00, 0xda ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alhsik %r2, %r3, -1" + + - + input: + bytes: [ 0xec, 0x45, 0x00, 0x00, 0x00, 0xda ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alhsik %r4, %r5, 0" + + - + input: + bytes: [ 0xec, 0x67, 0x00, 0x01, 0x00, 0xda ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alhsik %r6, %r7, 1" + + - + input: + bytes: [ 0xec, 0x8f, 0x7f, 0xff, 0x00, 0xda ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alhsik %r8, %r15, 32767" + + - + input: + bytes: [ 0x1e, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alr %r0, %r0" + + - + input: + bytes: [ 0x1e, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alr %r0, %r15" + + - + input: + bytes: [ 0x1e, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alr %r15, %r0" + + - + input: + bytes: [ 0x1e, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0xfa, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xfa, 0x40, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alrk %r2, %r3, %r4" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x6e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsi -524288, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x6e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsi -1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x6e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsi 0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x6e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsi 1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x6e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsi 524287, 0" + + - + input: + bytes: [ 0xeb, 0x80, 0x00, 0x00, 0x00, 0x6e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsi 0, -128" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x6e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsi 0, -1" + + - + input: + bytes: [ 0xeb, 0x01, 0x00, 0x00, 0x00, 0x6e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsi 0, 1" + + - + input: + bytes: [ 0xeb, 0x7f, 0x00, 0x00, 0x00, 0x6e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsi 0, 127" + + - + input: + bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x6e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsi 0(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x6e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsi 0(%r15), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x6e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsi 524287(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x6e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsi 524287(%r15), 42" + + - + input: + bytes: [ 0xcc, 0x0a, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsih %r0, -2147483648" + + - + input: + bytes: [ 0xcc, 0x0a, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsih %r0, -1" + + - + input: + bytes: [ 0xcc, 0x0a, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsih %r0, 0" + + - + input: + bytes: [ 0xcc, 0x0a, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsih %r0, 1" + + - + input: + bytes: [ 0xcc, 0x0a, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsih %r0, 2147483647" + + - + input: + bytes: [ 0xcc, 0xfa, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsih %r15, 0" + + - + input: + bytes: [ 0xcc, 0x0b, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsihn %r0, -2147483648" + + - + input: + bytes: [ 0xcc, 0x0b, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsihn %r0, -1" + + - + input: + bytes: [ 0xcc, 0x0b, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsihn %r0, 0" + + - + input: + bytes: [ 0xcc, 0x0b, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsihn %r0, 1" + + - + input: + bytes: [ 0xcc, 0x0b, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsihn %r0, 2147483647" + + - + input: + bytes: [ 0xcc, 0xfb, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "alsihn %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x5e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aly %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x5e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aly %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x5e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aly %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x5e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aly %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x5e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aly %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x5e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aly %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x5e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aly %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x5e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aly %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x5e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aly %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x5e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aly %r15, 0" + + - + input: + bytes: [ 0xfa, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ap 0(1), 0(1)" + + - + input: + bytes: [ 0xfa, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ap 0(1), 0(1,%r1)" + + - + input: + bytes: [ 0xfa, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ap 0(1), 0(1,%r15)" + + - + input: + bytes: [ 0xfa, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ap 0(1), 4095(1)" + + - + input: + bytes: [ 0xfa, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ap 0(1), 4095(1,%r1)" + + - + input: + bytes: [ 0xfa, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ap 0(1), 4095(1,%r15)" + + - + input: + bytes: [ 0xfa, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ap 0(1,%r1), 0(1)" + + - + input: + bytes: [ 0xfa, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ap 0(1,%r15), 0(1)" + + - + input: + bytes: [ 0xfa, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ap 4095(1,%r1), 0(1)" + + - + input: + bytes: [ 0xfa, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ap 4095(1,%r15), 0(1)" + + - + input: + bytes: [ 0xfa, 0xf0, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ap 0(16,%r1), 0(1)" + + - + input: + bytes: [ 0xfa, 0xf0, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ap 0(16,%r15), 0(1)" + + - + input: + bytes: [ 0xfa, 0x0f, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ap 0(1), 0(16,%r1)" + + - + input: + bytes: [ 0xfa, 0x0f, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ap 0(1), 0(16,%r15)" + + - + input: + bytes: [ 0x1a, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ar %r0, %r0" + + - + input: + bytes: [ 0x1a, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ar %r0, %r15" + + - + input: + bytes: [ 0x1a, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ar %r15, %r0" + + - + input: + bytes: [ 0x1a, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ar %r7, %r8" + + - + input: + bytes: [ 0xb9, 0xf8, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ark %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xf8, 0x40, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ark %r2, %r3, %r4" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x6a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asi -524288, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x6a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asi -1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x6a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asi 0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x6a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asi 1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x6a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asi 524287, 0" + + - + input: + bytes: [ 0xeb, 0x80, 0x00, 0x00, 0x00, 0x6a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asi 0, -128" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x6a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asi 0, -1" + + - + input: + bytes: [ 0xeb, 0x01, 0x00, 0x00, 0x00, 0x6a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asi 0, 1" + + - + input: + bytes: [ 0xeb, 0x7f, 0x00, 0x00, 0x00, 0x6a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asi 0, 127" + + - + input: + bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x6a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asi 0(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x6a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asi 0(%r15), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x6a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asi 524287(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x6a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "asi 524287(%r15), 42" + + - + input: + bytes: [ 0x7e, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "au %f0, 0" + + - + input: + bytes: [ 0x7e, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "au %f0, 4095" + + - + input: + bytes: [ 0x7e, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "au %f0, 0(%r1)" + + - + input: + bytes: [ 0x7e, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "au %f0, 0(%r15)" + + - + input: + bytes: [ 0x7e, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "au %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x7e, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "au %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x7e, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "au %f15, 0" + + - + input: + bytes: [ 0x3e, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aur %f0, %f0" + + - + input: + bytes: [ 0x3e, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aur %f0, %f15" + + - + input: + bytes: [ 0x3e, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aur %f7, %f8" + + - + input: + bytes: [ 0x3e, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aur %f15, %f0" + + - + input: + bytes: [ 0x6e, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aw %f0, 0" + + - + input: + bytes: [ 0x6e, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aw %f0, 4095" + + - + input: + bytes: [ 0x6e, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aw %f0, 0(%r1)" + + - + input: + bytes: [ 0x6e, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aw %f0, 0(%r15)" + + - + input: + bytes: [ 0x6e, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aw %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x6e, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aw %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x6e, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "aw %f15, 0" + + - + input: + bytes: [ 0x2e, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "awr %f0, %f0" + + - + input: + bytes: [ 0x2e, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "awr %f0, %f15" + + - + input: + bytes: [ 0x2e, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "awr %f7, %f8" + + - + input: + bytes: [ 0x2e, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "awr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x4a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "axbr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x4a, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "axbr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x4a, 0x00, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "axbr %f8, %f8" + + - + input: + bytes: [ 0xb3, 0x4a, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "axbr %f13, %f0" + + - + input: + bytes: [ 0x36, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "axr %f0, %f0" + + - + input: + bytes: [ 0x36, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "axr %f0, %f13" + + - + input: + bytes: [ 0x36, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "axr %f8, %f8" + + - + input: + bytes: [ 0x36, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "axr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0xda, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "axtr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xda, 0xd0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "axtr %f0, %f0, %f13" + + - + input: + bytes: [ 0xb3, 0xda, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "axtr %f0, %f13, %f0" + + - + input: + bytes: [ 0xb3, 0xda, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "axtr %f13, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xda, 0x80, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "axtr %f8, %f8, %f8" + + - + input: + bytes: [ 0xb3, 0xda, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "axtra %f0, %f0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xda, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "axtra %f0, %f0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xda, 0xd1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "axtra %f0, %f0, %f13, 1" + + - + input: + bytes: [ 0xb3, 0xda, 0x01, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "axtra %f0, %f13, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xda, 0x01, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "axtra %f13, %f0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xda, 0x88, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "axtra %f8, %f8, %f8, 8" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x5a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ay %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x5a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ay %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x5a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ay %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x5a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ay %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x5a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ay %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x5a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ay %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x5a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ay %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x5a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ay %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x5a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ay %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x5a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ay %r15, 0" + + - + input: + bytes: [ 0x47, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "b 0" + + - + input: + bytes: [ 0x47, 0xf0, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "b 4095" + + - + input: + bytes: [ 0x47, 0xf0, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "b 0(%r1)" + + - + input: + bytes: [ 0x47, 0xf0, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "b 0(%r15)" + + - + input: + bytes: [ 0x47, 0xf1, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "b 4095(%r1,%r15)" + + - + input: + bytes: [ 0x47, 0xff, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "b 4095(%r15,%r1)" + + - + input: + bytes: [ 0xb2, 0x40, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bakr %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x40, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bakr %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x40, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bakr %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x40, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bakr %r7, %r8" + + - + input: + bytes: [ 0x45, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bal %r0, 0" + + - + input: + bytes: [ 0x45, 0x10, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bal %r1, 4095" + + - + input: + bytes: [ 0x45, 0x20, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bal %r2, 0(%r1)" + + - + input: + bytes: [ 0x45, 0x30, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bal %r3, 0(%r15)" + + - + input: + bytes: [ 0x45, 0xe1, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bal %r14, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x45, 0xff, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bal %r15, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x05, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "balr %r0, %r1" + + - + input: + bytes: [ 0x05, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "balr %r0, %r15" + + - + input: + bytes: [ 0x05, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "balr %r1, 0" + + - + input: + bytes: [ 0x05, 0xe9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "balr %r14, %r9" + + - + input: + bytes: [ 0x05, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "balr %r15, %r1" + + - + input: + bytes: [ 0x4d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bas %r0, 0" + + - + input: + bytes: [ 0x4d, 0x10, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bas %r1, 4095" + + - + input: + bytes: [ 0x4d, 0x20, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bas %r2, 0(%r1)" + + - + input: + bytes: [ 0x4d, 0x30, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bas %r3, 0(%r15)" + + - + input: + bytes: [ 0x4d, 0xe1, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bas %r14, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x4d, 0xff, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bas %r15, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x0d, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "basr %r0, %r1" + + - + input: + bytes: [ 0x0d, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "basr %r0, %r15" + + - + input: + bytes: [ 0x0d, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "basr %r1, 0" + + - + input: + bytes: [ 0x0d, 0xe9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "basr %r14, %r9" + + - + input: + bytes: [ 0x0d, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "basr %r15, %r1" + + - + input: + bytes: [ 0x0c, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bassm %r0, %r1" + + - + input: + bytes: [ 0x0c, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bassm %r0, %r15" + + - + input: + bytes: [ 0x0c, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bassm %r1, 0" + + - + input: + bytes: [ 0x0c, 0xe9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bassm %r14, %r9" + + - + input: + bytes: [ 0x0c, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bassm %r15, %r1" + + - + input: + bytes: [ 0x47, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bc 0, 0" + + - + input: + bytes: [ 0x47, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bc 0, 4095" + + - + input: + bytes: [ 0x47, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bc 0, 0(%r1)" + + - + input: + bytes: [ 0x47, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bc 0, 0(%r15)" + + - + input: + bytes: [ 0x47, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bc 0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x47, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bc 0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x47, 0x10, 0xd0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bo 0(%r13)" + + - + input: + bytes: [ 0x47, 0x20, 0xc0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bh 0(%r12)" + + - + input: + bytes: [ 0x47, 0x30, 0xb0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bnle 0(%r11)" + + - + input: + bytes: [ 0x47, 0x40, 0xa0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bl 0(%r10)" + + - + input: + bytes: [ 0x47, 0x50, 0x90, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bnhe 0(%r9)" + + - + input: + bytes: [ 0x47, 0x60, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "blh 0(%r8)" + + - + input: + bytes: [ 0x47, 0x70, 0x70, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bne 0(%r7)" + + - + input: + bytes: [ 0x47, 0x80, 0x60, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "be 0(%r6)" + + - + input: + bytes: [ 0x47, 0x90, 0x50, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bnlh 0(%r5)" + + - + input: + bytes: [ 0x47, 0xa0, 0x40, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bhe 0(%r4)" + + - + input: + bytes: [ 0x47, 0xb0, 0x30, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bnl 0(%r3)" + + - + input: + bytes: [ 0x47, 0xc0, 0x20, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ble 0(%r2)" + + - + input: + bytes: [ 0x47, 0xd0, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bnh 0(%r1)" + + - + input: + bytes: [ 0x47, 0xe0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bno 0" + + - + input: + bytes: [ 0x07, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bcr 0, %r14" + + - + input: + bytes: [ 0x07, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bor %r13" + + - + input: + bytes: [ 0x07, 0x2c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bhr %r12" + + - + input: + bytes: [ 0x07, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bnler %r11" + + - + input: + bytes: [ 0x07, 0x4a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "blr %r10" + + - + input: + bytes: [ 0x07, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bnher %r9" + + - + input: + bytes: [ 0x07, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "blhr %r8" + + - + input: + bytes: [ 0x07, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bner %r7" + + - + input: + bytes: [ 0x07, 0x86 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ber %r6" + + - + input: + bytes: [ 0x07, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bnlhr %r5" + + - + input: + bytes: [ 0x07, 0xa4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bher %r4" + + - + input: + bytes: [ 0x07, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bnlr %r3" + + - + input: + bytes: [ 0x07, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bler %r2" + + - + input: + bytes: [ 0x07, 0xd1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bnhr %r1" + + - + input: + bytes: [ 0x07, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bnor 0" + + - + input: + bytes: [ 0x07, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "br %r1" + + - + input: + bytes: [ 0x07, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "br %r14" + + - + input: + bytes: [ 0x07, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "br %r15" + + - + input: + bytes: [ 0x46, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bct %r0, 0" + + - + input: + bytes: [ 0x46, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bct %r0, 4095" + + - + input: + bytes: [ 0x46, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bct %r0, 0(%r1)" + + - + input: + bytes: [ 0x46, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bct %r0, 0(%r15)" + + - + input: + bytes: [ 0x46, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bct %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x46, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bct %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x46, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bct %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bctg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bctg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bctg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bctg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bctg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bctg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bctg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bctg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bctg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bctg %r15, 0" + + - + input: + bytes: [ 0xb9, 0x46, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bctgr %r0, %r9" + + - + input: + bytes: [ 0xb9, 0x46, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bctgr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x46, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bctgr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x46, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bctgr %r15, %r9" + + - + input: + bytes: [ 0x06, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bctr %r0, %r9" + + - + input: + bytes: [ 0x06, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bctr %r0, %r15" + + - + input: + bytes: [ 0x06, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bctr %r15, %r0" + + - + input: + bytes: [ 0x06, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bctr %r15, %r9" + + - + input: + bytes: [ 0xb2, 0x5a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bsa %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x5a, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bsa %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x5a, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bsa %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x5a, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bsa %r7, %r8" + + - + input: + bytes: [ 0xb2, 0x58, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bsg %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x58, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bsg %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x58, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bsg %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x58, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bsg %r7, %r8" + + - + input: + bytes: [ 0x0b, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bsm %r0, %r1" + + - + input: + bytes: [ 0x0b, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bsm %r0, %r15" + + - + input: + bytes: [ 0x0b, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bsm %r1, 0" + + - + input: + bytes: [ 0x0b, 0xe9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bsm %r14, %r9" + + - + input: + bytes: [ 0x0b, 0xf1 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bsm %r15, %r1" + + - + input: + bytes: [ 0x86, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxh %r0, %r0, 0" + + - + input: + bytes: [ 0x86, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxh %r0, %r15, 0" + + - + input: + bytes: [ 0x86, 0xef, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxh %r14, %r15, 0" + + - + input: + bytes: [ 0x86, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxh %r15, %r15, 0" + + - + input: + bytes: [ 0x86, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxh %r0, %r0, 4095" + + - + input: + bytes: [ 0x86, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxh %r0, %r0, 1" + + - + input: + bytes: [ 0x86, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxh %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0x86, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxh %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0x86, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxh %r0, %r0, 4095(%r1)" + + - + input: + bytes: [ 0x86, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxh %r0, %r0, 4095(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x44 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxhg %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x44 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxhg %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x44 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxhg %r14, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x44 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxhg %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x44 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxhg %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x44 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxhg %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x44 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxhg %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x44 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxhg %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x44 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxhg %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x44 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxhg %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x44 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxhg %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x44 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxhg %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x44 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxhg %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0x87, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxle %r0, %r0, 0" + + - + input: + bytes: [ 0x87, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxle %r0, %r15, 0" + + - + input: + bytes: [ 0x87, 0xef, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxle %r14, %r15, 0" + + - + input: + bytes: [ 0x87, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxle %r15, %r15, 0" + + - + input: + bytes: [ 0x87, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxle %r0, %r0, 4095" + + - + input: + bytes: [ 0x87, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxle %r0, %r0, 1" + + - + input: + bytes: [ 0x87, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxle %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0x87, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxle %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0x87, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxle %r0, %r0, 4095(%r1)" + + - + input: + bytes: [ 0x87, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxle %r0, %r0, 4095(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxleg %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxleg %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxleg %r14, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxleg %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxleg %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxleg %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxleg %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxleg %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxleg %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxleg %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxleg %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxleg %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "bxleg %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0x59, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c %r0, 0" + + - + input: + bytes: [ 0x59, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c %r0, 4095" + + - + input: + bytes: [ 0x59, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c %r0, 0(%r1)" + + - + input: + bytes: [ 0x59, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c %r0, 0(%r15)" + + - + input: + bytes: [ 0x59, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x59, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x59, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "c %r15, 0" + + - + input: + bytes: [ 0x69, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cd %f0, 0" + + - + input: + bytes: [ 0x69, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cd %f0, 4095" + + - + input: + bytes: [ 0x69, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cd %f0, 0(%r1)" + + - + input: + bytes: [ 0x69, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cd %f0, 0(%r15)" + + - + input: + bytes: [ 0x69, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cd %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x69, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cd %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x69, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cd %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x19 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x19 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x19 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x19 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x19 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x19 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x19 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdb %f15, 0" + + - + input: + bytes: [ 0xb3, 0x19, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdbr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x19, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdbr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x19, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdbr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x19, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdbr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x95, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdfbr %f0, %r0" + + - + input: + bytes: [ 0xb3, 0x95, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdfbr %f0, %r15" + + - + input: + bytes: [ 0xb3, 0x95, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdfbr %f15, %r0" + + - + input: + bytes: [ 0xb3, 0x95, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdfbr %f7, %r8" + + - + input: + bytes: [ 0xb3, 0x95, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdfbr %f15, %r15" + + - + input: + bytes: [ 0xb3, 0x95, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdfbra %f0, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0x95, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdfbra %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb3, 0x95, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdfbra %f0, 0, %r15, 1" + + - + input: + bytes: [ 0xb3, 0x95, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdfbra %f0, 15, %r0, 1" + + - + input: + bytes: [ 0xb3, 0x95, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdfbra %f4, 5, %r6, 7" + + - + input: + bytes: [ 0xb3, 0x95, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdfbra %f15, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xb5, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdfr %f0, %r0" + + - + input: + bytes: [ 0xb3, 0xb5, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdfr %f0, %r15" + + - + input: + bytes: [ 0xb3, 0xb5, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdfr %f15, %r0" + + - + input: + bytes: [ 0xb3, 0xb5, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdfr %f7, %r8" + + - + input: + bytes: [ 0xb3, 0xb5, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdfr %f15, %r15" + + - + input: + bytes: [ 0xb9, 0x51, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdftr %f0, 0, %r0, 0" + + - + input: + bytes: [ 0xb9, 0x51, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdftr %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb9, 0x51, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdftr %f0, 0, %r15, 0" + + - + input: + bytes: [ 0xb9, 0x51, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdftr %f0, 15, %r0, 0" + + - + input: + bytes: [ 0xb9, 0x51, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdftr %f4, 5, %r6, 7" + + - + input: + bytes: [ 0xb9, 0x51, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdftr %f15, 0, %r0, 0" + + - + input: + bytes: [ 0xb3, 0xa5, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgbr %f0, %r0" + + - + input: + bytes: [ 0xb3, 0xa5, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgbr %f0, %r15" + + - + input: + bytes: [ 0xb3, 0xa5, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgbr %f15, %r0" + + - + input: + bytes: [ 0xb3, 0xa5, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgbr %f7, %r8" + + - + input: + bytes: [ 0xb3, 0xa5, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgbr %f15, %r15" + + - + input: + bytes: [ 0xb3, 0xa5, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgbra %f0, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xa5, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgbra %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb3, 0xa5, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgbra %f0, 0, %r15, 1" + + - + input: + bytes: [ 0xb3, 0xa5, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgbra %f0, 15, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xa5, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgbra %f4, 5, %r6, 7" + + - + input: + bytes: [ 0xb3, 0xa5, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgbra %f15, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xc5, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgr %f0, %r0" + + - + input: + bytes: [ 0xb3, 0xc5, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgr %f0, %r15" + + - + input: + bytes: [ 0xb3, 0xc5, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgr %f15, %r0" + + - + input: + bytes: [ 0xb3, 0xc5, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgr %f7, %r8" + + - + input: + bytes: [ 0xb3, 0xc5, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgr %f15, %r15" + + - + input: + bytes: [ 0xb3, 0xf1, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgtr %f0, %r0" + + - + input: + bytes: [ 0xb3, 0xf1, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgtr %f0, %r15" + + - + input: + bytes: [ 0xb3, 0xf1, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgtr %f15, %r0" + + - + input: + bytes: [ 0xb3, 0xf1, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgtr %f7, %r8" + + - + input: + bytes: [ 0xb3, 0xf1, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgtr %f15, %r15" + + - + input: + bytes: [ 0xb3, 0xf1, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgtra %f0, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xf1, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgtra %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb3, 0xf1, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgtra %f0, 0, %r15, 1" + + - + input: + bytes: [ 0xb3, 0xf1, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgtra %f0, 15, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xf1, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgtra %f4, 5, %r6, 7" + + - + input: + bytes: [ 0xb3, 0xf1, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdgtra %f15, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0x91, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlfbr %f0, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0x91, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlfbr %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb3, 0x91, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlfbr %f0, 0, %r15, 1" + + - + input: + bytes: [ 0xb3, 0x91, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlfbr %f0, 15, %r0, 1" + + - + input: + bytes: [ 0xb3, 0x91, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlfbr %f4, 5, %r6, 7" + + - + input: + bytes: [ 0xb3, 0x91, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlfbr %f15, 0, %r0, 1" + + - + input: + bytes: [ 0xb9, 0x53, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlftr %f0, 0, %r0, 0" + + - + input: + bytes: [ 0xb9, 0x53, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlftr %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb9, 0x53, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlftr %f0, 0, %r15, 0" + + - + input: + bytes: [ 0xb9, 0x53, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlftr %f0, 15, %r0, 0" + + - + input: + bytes: [ 0xb9, 0x53, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlftr %f4, 5, %r6, 7" + + - + input: + bytes: [ 0xb9, 0x53, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlftr %f15, 0, %r0, 0" + + - + input: + bytes: [ 0xb3, 0xa1, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlgbr %f0, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xa1, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlgbr %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb3, 0xa1, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlgbr %f0, 0, %r15, 1" + + - + input: + bytes: [ 0xb3, 0xa1, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlgbr %f0, 15, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xa1, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlgbr %f4, 5, %r6, 7" + + - + input: + bytes: [ 0xb3, 0xa1, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlgbr %f15, 0, %r0, 1" + + - + input: + bytes: [ 0xb9, 0x52, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlgtr %f0, 0, %r0, 0" + + - + input: + bytes: [ 0xb9, 0x52, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlgtr %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb9, 0x52, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlgtr %f0, 0, %r15, 0" + + - + input: + bytes: [ 0xb9, 0x52, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlgtr %f0, 15, %r0, 0" + + - + input: + bytes: [ 0xb9, 0x52, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlgtr %f4, 5, %r6, 7" + + - + input: + bytes: [ 0xb9, 0x52, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdlgtr %f15, 0, %r0, 0" + + - + input: + bytes: [ 0x29, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdr %f0, %f0" + + - + input: + bytes: [ 0x29, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdr %f0, %f15" + + - + input: + bytes: [ 0x29, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdr %f7, %f8" + + - + input: + bytes: [ 0x29, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdr %f15, %f0" + + - + input: + bytes: [ 0xbb, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cds %r0, %r0, 0" + + - + input: + bytes: [ 0xbb, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cds %r0, %r0, 4095" + + - + input: + bytes: [ 0xbb, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cds %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xbb, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cds %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xbb, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cds %r0, %r0, 4095(%r1)" + + - + input: + bytes: [ 0xbb, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cds %r0, %r0, 4095(%r15)" + + - + input: + bytes: [ 0xbb, 0x0e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cds %r0, %r14, 0" + + - + input: + bytes: [ 0xbb, 0xe0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cds %r14, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsg %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsg %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsg %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsg %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsg %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsg %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsg %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsg %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsg %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x0e, 0x00, 0x00, 0x00, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsg %r0, %r14, 0" + + - + input: + bytes: [ 0xeb, 0xe0, 0x00, 0x00, 0x00, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsg %r14, %r0, 0" + + - + input: + bytes: [ 0xb3, 0xf3, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdstr %f0, %r0" + + - + input: + bytes: [ 0xb3, 0xf3, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdstr %f0, %r15" + + - + input: + bytes: [ 0xb3, 0xf3, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdstr %f15, %r0" + + - + input: + bytes: [ 0xb3, 0xf3, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdstr %f7, %r8" + + - + input: + bytes: [ 0xb3, 0xf3, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdstr %f15, %r15" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsy %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsy %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsy %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsy %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsy %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsy %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsy %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsy %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsy %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x0e, 0x00, 0x00, 0x00, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsy %r0, %r14, 0" + + - + input: + bytes: [ 0xeb, 0xe0, 0x00, 0x00, 0x00, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdsy %r14, %r0, 0" + + - + input: + bytes: [ 0xb3, 0xe4, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdtr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xe4, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdtr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0xe4, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdtr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0xe4, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdtr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0xf2, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdutr %f0, %r0" + + - + input: + bytes: [ 0xb3, 0xf2, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdutr %f0, %r15" + + - + input: + bytes: [ 0xb3, 0xf2, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdutr %f15, %r0" + + - + input: + bytes: [ 0xb3, 0xf2, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdutr %f7, %r8" + + - + input: + bytes: [ 0xb3, 0xf2, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdutr %f15, %r15" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdzt %f0, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdzt %f15, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x0f, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdzt %f0, 0(1), 15" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdzt %f0, 0(1,%r1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdzt %f0, 0(1,%r15), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x1f, 0xff, 0x00, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdzt %f0, 4095(1,%r1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0xff, 0xff, 0x00, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdzt %f0, 4095(1,%r15), 0" + + - + input: + bytes: [ 0xed, 0xff, 0x10, 0x00, 0x00, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdzt %f0, 0(256,%r1), 0" + + - + input: + bytes: [ 0xed, 0xff, 0xf0, 0x00, 0x00, 0xaa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cdzt %f0, 0(256,%r15), 0" + + - + input: + bytes: [ 0x79, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ce %f0, 0" + + - + input: + bytes: [ 0x79, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ce %f0, 4095" + + - + input: + bytes: [ 0x79, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ce %f0, 0(%r1)" + + - + input: + bytes: [ 0x79, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ce %f0, 0(%r15)" + + - + input: + bytes: [ 0x79, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ce %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x79, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ce %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x79, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ce %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ceb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ceb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ceb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ceb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ceb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ceb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ceb %f15, 0" + + - + input: + bytes: [ 0xb3, 0x09, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cebr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x09, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cebr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x09, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cebr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x09, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cebr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0xf4, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cedtr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xf4, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cedtr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0xf4, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cedtr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0xf4, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cedtr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x94, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cefbr %f0, %r0" + + - + input: + bytes: [ 0xb3, 0x94, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cefbr %f0, %r15" + + - + input: + bytes: [ 0xb3, 0x94, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cefbr %f15, %r0" + + - + input: + bytes: [ 0xb3, 0x94, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cefbr %f7, %r8" + + - + input: + bytes: [ 0xb3, 0x94, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cefbr %f15, %r15" + + - + input: + bytes: [ 0xb3, 0x94, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cefbra %f0, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0x94, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cefbra %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb3, 0x94, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cefbra %f0, 0, %r15, 1" + + - + input: + bytes: [ 0xb3, 0x94, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cefbra %f0, 15, %r0, 1" + + - + input: + bytes: [ 0xb3, 0x94, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cefbra %f4, 5, %r6, 7" + + - + input: + bytes: [ 0xb3, 0x94, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cefbra %f15, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xb4, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cefr %f0, %r0" + + - + input: + bytes: [ 0xb3, 0xb4, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cefr %f0, %r15" + + - + input: + bytes: [ 0xb3, 0xb4, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cefr %f15, %r0" + + - + input: + bytes: [ 0xb3, 0xb4, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cefr %f7, %r8" + + - + input: + bytes: [ 0xb3, 0xb4, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cefr %f15, %r15" + + - + input: + bytes: [ 0xb3, 0xa4, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cegbr %f0, %r0" + + - + input: + bytes: [ 0xb3, 0xa4, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cegbr %f0, %r15" + + - + input: + bytes: [ 0xb3, 0xa4, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cegbr %f15, %r0" + + - + input: + bytes: [ 0xb3, 0xa4, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cegbr %f7, %r8" + + - + input: + bytes: [ 0xb3, 0xa4, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cegbr %f15, %r15" + + - + input: + bytes: [ 0xb3, 0xa4, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cegbra %f0, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xa4, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cegbra %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb3, 0xa4, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cegbra %f0, 0, %r15, 1" + + - + input: + bytes: [ 0xb3, 0xa4, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cegbra %f0, 15, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xa4, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cegbra %f4, 5, %r6, 7" + + - + input: + bytes: [ 0xb3, 0xa4, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cegbra %f15, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xc4, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cegr %f0, %r0" + + - + input: + bytes: [ 0xb3, 0xc4, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cegr %f0, %r15" + + - + input: + bytes: [ 0xb3, 0xc4, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cegr %f15, %r0" + + - + input: + bytes: [ 0xb3, 0xc4, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cegr %f7, %r8" + + - + input: + bytes: [ 0xb3, 0xc4, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cegr %f15, %r15" + + - + input: + bytes: [ 0xb3, 0x90, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "celfbr %f0, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0x90, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "celfbr %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb3, 0x90, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "celfbr %f0, 0, %r15, 1" + + - + input: + bytes: [ 0xb3, 0x90, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "celfbr %f0, 15, %r0, 1" + + - + input: + bytes: [ 0xb3, 0x90, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "celfbr %f4, 5, %r6, 7" + + - + input: + bytes: [ 0xb3, 0x90, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "celfbr %f15, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xa0, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "celgbr %f0, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xa0, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "celgbr %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb3, 0xa0, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "celgbr %f0, 0, %r15, 1" + + - + input: + bytes: [ 0xb3, 0xa0, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "celgbr %f0, 15, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xa0, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "celgbr %f4, 5, %r6, 7" + + - + input: + bytes: [ 0xb3, 0xa0, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "celgbr %f15, 0, %r0, 1" + + - + input: + bytes: [ 0x39, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cer %f0, %f0" + + - + input: + bytes: [ 0x39, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cer %f0, %f15" + + - + input: + bytes: [ 0x39, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cer %f7, %f8" + + - + input: + bytes: [ 0x39, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cer %f15, %f0" + + - + input: + bytes: [ 0xb3, 0xfc, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cextr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xfc, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cextr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0xfc, 0x00, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cextr %f8, %f8" + + - + input: + bytes: [ 0xb3, 0xfc, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cextr %f13, %f0" + + - + input: + bytes: [ 0xb2, 0x1a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfc 0" + + - + input: + bytes: [ 0xb2, 0x1a, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfc 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x1a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfc 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x1a, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfc 4095" + + - + input: + bytes: [ 0xb2, 0x1a, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfc 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x1a, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfc 4095(%r15)" + + - + input: + bytes: [ 0xb3, 0x99, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdbr %r0, 0, %f0" + + - + input: + bytes: [ 0xb3, 0x99, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdbr %r0, 0, %f15" + + - + input: + bytes: [ 0xb3, 0x99, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdbr %r0, 15, %f0" + + - + input: + bytes: [ 0xb3, 0x99, 0x50, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdbr %r4, 5, %f6" + + - + input: + bytes: [ 0xb3, 0x99, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdbr %r15, 0, %f0" + + - + input: + bytes: [ 0xb3, 0x99, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdbra %r0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x99, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdbra %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0x99, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdbra %r0, 0, %f15, 1" + + - + input: + bytes: [ 0xb3, 0x99, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdbra %r0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x99, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdbra %r4, 5, %f6, 7" + + - + input: + bytes: [ 0xb3, 0x99, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdbra %r15, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xb9, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdr %r0, 0, %f0" + + - + input: + bytes: [ 0xb3, 0xb9, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdr %r0, 0, %f15" + + - + input: + bytes: [ 0xb3, 0xb9, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdr %r0, 15, %f0" + + - + input: + bytes: [ 0xb3, 0xb9, 0x50, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdr %r4, 5, %f6" + + - + input: + bytes: [ 0xb3, 0xb9, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdr %r15, 0, %f0" + + - + input: + bytes: [ 0xb9, 0x41, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdtr %r0, 0, %f0, 0" + + - + input: + bytes: [ 0xb9, 0x41, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdtr %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb9, 0x41, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdtr %r0, 0, %f15, 0" + + - + input: + bytes: [ 0xb9, 0x41, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdtr %r0, 15, %f0, 0" + + - + input: + bytes: [ 0xb9, 0x41, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdtr %r4, 5, %f6, 7" + + - + input: + bytes: [ 0xb9, 0x41, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfdtr %r15, 0, %f0, 0" + + - + input: + bytes: [ 0xb3, 0x98, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfebr %r0, 0, %f0" + + - + input: + bytes: [ 0xb3, 0x98, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfebr %r0, 0, %f15" + + - + input: + bytes: [ 0xb3, 0x98, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfebr %r0, 15, %f0" + + - + input: + bytes: [ 0xb3, 0x98, 0x50, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfebr %r4, 5, %f6" + + - + input: + bytes: [ 0xb3, 0x98, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfebr %r15, 0, %f0" + + - + input: + bytes: [ 0xb3, 0x98, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfebra %r0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x98, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfebra %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0x98, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfebra %r0, 0, %f15, 1" + + - + input: + bytes: [ 0xb3, 0x98, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfebra %r0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x98, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfebra %r4, 5, %f6, 7" + + - + input: + bytes: [ 0xb3, 0x98, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfebra %r15, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xb8, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfer %r0, 0, %f0" + + - + input: + bytes: [ 0xb3, 0xb8, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfer %r0, 0, %f15" + + - + input: + bytes: [ 0xb3, 0xb8, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfer %r0, 15, %f0" + + - + input: + bytes: [ 0xb3, 0xb8, 0x50, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfer %r4, 5, %f6" + + - + input: + bytes: [ 0xb3, 0xb8, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfer %r15, 0, %f0" + + - + input: + bytes: [ 0xc2, 0x0d, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfi %r0, -2147483648" + + - + input: + bytes: [ 0xc2, 0x0d, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfi %r0, -1" + + - + input: + bytes: [ 0xc2, 0x0d, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfi %r0, 0" + + - + input: + bytes: [ 0xc2, 0x0d, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfi %r0, 1" + + - + input: + bytes: [ 0xc2, 0x0d, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfi %r0, 2147483647" + + - + input: + bytes: [ 0xc2, 0xfd, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfi %r15, 0" + + - + input: + bytes: [ 0xb3, 0x9a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxbr %r0, 0, %f0" + + - + input: + bytes: [ 0xb3, 0x9a, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxbr %r0, 0, %f13" + + - + input: + bytes: [ 0xb3, 0x9a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxbr %r0, 15, %f0" + + - + input: + bytes: [ 0xb3, 0x9a, 0x50, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxbr %r4, 5, %f8" + + - + input: + bytes: [ 0xb3, 0x9a, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxbr %r15, 0, %f0" + + - + input: + bytes: [ 0xb3, 0x9a, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxbra %r0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x9a, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxbra %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0x9a, 0x01, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxbra %r0, 0, %f13, 1" + + - + input: + bytes: [ 0xb3, 0x9a, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxbra %r0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x9a, 0x59, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxbra %r4, 5, %f8, 9" + + - + input: + bytes: [ 0xb3, 0x9a, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxbra %r15, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xba, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxr %r0, 0, %f0" + + - + input: + bytes: [ 0xb3, 0xba, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxr %r0, 0, %f13" + + - + input: + bytes: [ 0xb3, 0xba, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxr %r0, 15, %f0" + + - + input: + bytes: [ 0xb3, 0xba, 0x50, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxr %r4, 5, %f8" + + - + input: + bytes: [ 0xb3, 0xba, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxr %r15, 0, %f0" + + - + input: + bytes: [ 0xb9, 0x49, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxtr %r0, 0, %f0, 0" + + - + input: + bytes: [ 0xb9, 0x49, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxtr %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb9, 0x49, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxtr %r0, 0, %f13, 0" + + - + input: + bytes: [ 0xb9, 0x49, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxtr %r0, 15, %f0, 0" + + - + input: + bytes: [ 0xb9, 0x49, 0x59, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxtr %r7, 5, %f8, 9" + + - + input: + bytes: [ 0xb9, 0x49, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cfxtr %r15, 0, %f0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cg %r15, 0" + + - + input: + bytes: [ 0xb3, 0xa9, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdbr %r0, 0, %f0" + + - + input: + bytes: [ 0xb3, 0xa9, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdbr %r0, 0, %f15" + + - + input: + bytes: [ 0xb3, 0xa9, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdbr %r0, 15, %f0" + + - + input: + bytes: [ 0xb3, 0xa9, 0x50, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdbr %r4, 5, %f6" + + - + input: + bytes: [ 0xb3, 0xa9, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdbr %r15, 0, %f0" + + - + input: + bytes: [ 0xb3, 0xa9, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdbra %r0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xa9, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdbra %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xa9, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdbra %r0, 0, %f15, 1" + + - + input: + bytes: [ 0xb3, 0xa9, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdbra %r0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xa9, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdbra %r4, 5, %f6, 7" + + - + input: + bytes: [ 0xb3, 0xa9, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdbra %r15, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xc9, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdr %r0, 0, %f0" + + - + input: + bytes: [ 0xb3, 0xc9, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdr %r0, 0, %f15" + + - + input: + bytes: [ 0xb3, 0xc9, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdr %r0, 15, %f0" + + - + input: + bytes: [ 0xb3, 0xc9, 0x50, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdr %r4, 5, %f6" + + - + input: + bytes: [ 0xb3, 0xc9, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdr %r15, 0, %f0" + + - + input: + bytes: [ 0xb3, 0xe1, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdtr %r0, 0, %f0" + + - + input: + bytes: [ 0xb3, 0xe1, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdtr %r0, 0, %f15" + + - + input: + bytes: [ 0xb3, 0xe1, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdtr %r0, 15, %f0" + + - + input: + bytes: [ 0xb3, 0xe1, 0x50, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdtr %r4, 5, %f6" + + - + input: + bytes: [ 0xb3, 0xe1, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdtr %r15, 0, %f0" + + - + input: + bytes: [ 0xb3, 0xe1, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdtra %r0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xe1, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdtra %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xe1, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdtra %r0, 0, %f15, 1" + + - + input: + bytes: [ 0xb3, 0xe1, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdtra %r0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xe1, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdtra %r4, 5, %f6, 7" + + - + input: + bytes: [ 0xb3, 0xe1, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgdtra %r15, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xa8, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgebr %r0, 0, %f0" + + - + input: + bytes: [ 0xb3, 0xa8, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgebr %r0, 0, %f15" + + - + input: + bytes: [ 0xb3, 0xa8, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgebr %r0, 15, %f0" + + - + input: + bytes: [ 0xb3, 0xa8, 0x50, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgebr %r4, 5, %f6" + + - + input: + bytes: [ 0xb3, 0xa8, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgebr %r15, 0, %f0" + + - + input: + bytes: [ 0xb3, 0xa8, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgebra %r0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xa8, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgebra %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xa8, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgebra %r0, 0, %f15, 1" + + - + input: + bytes: [ 0xb3, 0xa8, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgebra %r0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xa8, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgebra %r4, 5, %f6, 7" + + - + input: + bytes: [ 0xb3, 0xa8, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgebra %r15, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xc8, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cger %r0, 0, %f0" + + - + input: + bytes: [ 0xb3, 0xc8, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cger %r0, 0, %f15" + + - + input: + bytes: [ 0xb3, 0xc8, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cger %r0, 15, %f0" + + - + input: + bytes: [ 0xb3, 0xc8, 0x50, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cger %r4, 5, %f6" + + - + input: + bytes: [ 0xb3, 0xc8, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cger %r15, 0, %f0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgf %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgf %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgf %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgf %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgf %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgf %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgf %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgf %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgf %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgf %r15, 0" + + - + input: + bytes: [ 0xc2, 0x0c, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgfi %r0, -2147483648" + + - + input: + bytes: [ 0xc2, 0x0c, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgfi %r0, -1" + + - + input: + bytes: [ 0xc2, 0x0c, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgfi %r0, 0" + + - + input: + bytes: [ 0xc2, 0x0c, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgfi %r0, 1" + + - + input: + bytes: [ 0xc2, 0x0c, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgfi %r0, 2147483647" + + - + input: + bytes: [ 0xc2, 0xfc, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgfi %r15, 0" + + - + input: + bytes: [ 0xb9, 0x30, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgfr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x30, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgfr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x30, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgfr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x30, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgfr %r7, %r8" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgh %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgh %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgh %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgh %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgh %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgh %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgh %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgh %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgh %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgh %r15, 0" + + - + input: + bytes: [ 0xa7, 0x0f, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cghi %r0, -32768" + + - + input: + bytes: [ 0xa7, 0x0f, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cghi %r0, -1" + + - + input: + bytes: [ 0xa7, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cghi %r0, 0" + + - + input: + bytes: [ 0xa7, 0x0f, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cghi %r0, 1" + + - + input: + bytes: [ 0xa7, 0x0f, 0x7f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cghi %r0, 32767" + + - + input: + bytes: [ 0xa7, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cghi %r15, 0" + + - + input: + bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cghsi 0, 0" + + - + input: + bytes: [ 0xe5, 0x58, 0x0f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cghsi 4095, 0" + + - + input: + bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cghsi 0, -32768" + + - + input: + bytes: [ 0xe5, 0x58, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cghsi 0, -1" + + - + input: + bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cghsi 0, 0" + + - + input: + bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cghsi 0, 1" + + - + input: + bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x7f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cghsi 0, 32767" + + - + input: + bytes: [ 0xe5, 0x58, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cghsi 0(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x58, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cghsi 0(%r15), 42" + + - + input: + bytes: [ 0xe5, 0x58, 0x1f, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cghsi 4095(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x58, 0xff, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cghsi 4095(%r15), 42" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgib %r0, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x80, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgib %r0, -128, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xff, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgib %r0, -1, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x7f, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgib %r0, 127, 0, 0" + + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgib %r15, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x70, 0x00, 0x00, 0x64, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgib %r7, 100, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgib %r0, 0, 0, 4095(%r15)" + + - + input: + bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgib %r0, 0, 0, 0(%r8)" + + - + input: + bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgib %r0, 0, 0, 4095(%r7)" + + - + input: + bytes: [ 0xec, 0x01, 0x00, 0x00, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgib %r0, 0, 1, 0" + + - + input: + bytes: [ 0xec, 0x02, 0x00, 0x00, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgibh %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x03, 0x00, 0x00, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgib %r0, 0, 3, 0" + + - + input: + bytes: [ 0xec, 0x04, 0x00, 0x00, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgibl %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x05, 0x00, 0x00, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgib %r0, 0, 5, 0" + + - + input: + bytes: [ 0xec, 0x06, 0x00, 0x00, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgiblh %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x07, 0x00, 0x00, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgib %r0, 0, 7, 0" + + - + input: + bytes: [ 0xec, 0x08, 0x00, 0x00, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgibe %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x09, 0x00, 0x00, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgib %r0, 0, 9, 0" + + - + input: + bytes: [ 0xec, 0x0a, 0x00, 0x00, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgibhe %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x0b, 0x00, 0x00, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgib %r0, 0, 11, 0" + + - + input: + bytes: [ 0xec, 0x0c, 0x00, 0x00, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgible %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x0d, 0x00, 0x00, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgib %r0, 0, 13, 0" + + - + input: + bytes: [ 0xec, 0x0e, 0x00, 0x00, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgib %r0, 0, 14, 0" + + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xfc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgib %r0, 0, 15, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x20, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgith %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x40, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgitl %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x80, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgite %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x60, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgitlh %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xa0, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgithe %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xc0, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgitle %r0, 0" + + - + input: + bytes: [ 0xb9, 0x20, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x20, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x20, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x20, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgr %r7, %r8" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrb %r0, %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrb %r0, %r15, 0, 0" + + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrb %r15, %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x78, 0x00, 0x00, 0x00, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrb %r7, %r8, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrb %r0, %r0, 0, 4095(%r15)" + + - + input: + bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrb %r0, %r0, 0, 0(%r8)" + + - + input: + bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrb %r0, %r0, 0, 4095(%r7)" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x10, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrb %r0, %r0, 1, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x20, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrbh %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x30, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrb %r0, %r0, 3, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x40, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrbl %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x50, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrb %r0, %r0, 5, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x60, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrblh %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x70, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrb %r0, %r0, 7, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x80, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrbe %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x90, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrb %r0, %r0, 9, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xa0, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrbhe %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xb0, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrb %r0, %r0, 11, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xc0, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrble %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xd0, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrb %r0, %r0, 13, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xe0, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrb %r0, %r0, 14, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xf0, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrb %r0, %r0, 15, 0" + + - + input: + bytes: [ 0xb9, 0x60, 0x20, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrth %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x60, 0x40, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrtl %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x60, 0x80, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrte %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x60, 0x60, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrtlh %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x60, 0xa0, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrthe %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x60, 0xc0, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgrtle %r0, %r1" + + - + input: + bytes: [ 0xb3, 0xaa, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxbr %r0, 0, %f0" + + - + input: + bytes: [ 0xb3, 0xaa, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxbr %r0, 0, %f13" + + - + input: + bytes: [ 0xb3, 0xaa, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxbr %r0, 15, %f0" + + - + input: + bytes: [ 0xb3, 0xaa, 0x50, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxbr %r4, 5, %f8" + + - + input: + bytes: [ 0xb3, 0xaa, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxbr %r15, 0, %f0" + + - + input: + bytes: [ 0xb3, 0xaa, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxbra %r0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xaa, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxbra %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xaa, 0x01, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxbra %r0, 0, %f13, 1" + + - + input: + bytes: [ 0xb3, 0xaa, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxbra %r0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xaa, 0x59, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxbra %r4, 5, %f8, 9" + + - + input: + bytes: [ 0xb3, 0xaa, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxbra %r15, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xca, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxr %r0, 0, %f0" + + - + input: + bytes: [ 0xb3, 0xca, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxr %r0, 0, %f13" + + - + input: + bytes: [ 0xb3, 0xca, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxr %r0, 15, %f0" + + - + input: + bytes: [ 0xb3, 0xca, 0x50, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxr %r4, 5, %f8" + + - + input: + bytes: [ 0xb3, 0xca, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxr %r15, 0, %f0" + + - + input: + bytes: [ 0xb3, 0xe9, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxtr %r0, 0, %f0" + + - + input: + bytes: [ 0xb3, 0xe9, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxtr %r0, 0, %f13" + + - + input: + bytes: [ 0xb3, 0xe9, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxtr %r0, 15, %f0" + + - + input: + bytes: [ 0xb3, 0xe9, 0x50, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxtr %r4, 5, %f8" + + - + input: + bytes: [ 0xb3, 0xe9, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxtr %r15, 0, %f0" + + - + input: + bytes: [ 0xb3, 0xe9, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxtra %r0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xe9, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxtra %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xe9, 0x01, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxtra %r0, 0, %f13, 1" + + - + input: + bytes: [ 0xb3, 0xe9, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxtra %r0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xe9, 0x59, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxtra %r7, 5, %f8, 9" + + - + input: + bytes: [ 0xb3, 0xe9, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cgxtra %r15, 0, %f0, 1" + + - + input: + bytes: [ 0x49, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ch %r0, 0" + + - + input: + bytes: [ 0x49, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ch %r0, 4095" + + - + input: + bytes: [ 0x49, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ch %r0, 0(%r1)" + + - + input: + bytes: [ 0x49, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ch %r0, 0(%r15)" + + - + input: + bytes: [ 0x49, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ch %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x49, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ch %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x49, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ch %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xcd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chf %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xcd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chf %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xcd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chf %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xcd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chf %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xcd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chf %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xcd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chf %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xcd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chf %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xcd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chf %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xcd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chf %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xcd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chf %r15, 0" + + - + input: + bytes: [ 0xb9, 0xcd, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chhr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xcd, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chhr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xcd, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chhr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xcd, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chhr %r7, %r8" + + - + input: + bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chhsi 0, 0" + + - + input: + bytes: [ 0xe5, 0x54, 0x0f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chhsi 4095, 0" + + - + input: + bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chhsi 0, -32768" + + - + input: + bytes: [ 0xe5, 0x54, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chhsi 0, -1" + + - + input: + bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chhsi 0, 0" + + - + input: + bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chhsi 0, 1" + + - + input: + bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x7f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chhsi 0, 32767" + + - + input: + bytes: [ 0xe5, 0x54, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chhsi 0(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x54, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chhsi 0(%r15), 42" + + - + input: + bytes: [ 0xe5, 0x54, 0x1f, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chhsi 4095(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x54, 0xff, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chhsi 4095(%r15), 42" + + - + input: + bytes: [ 0xa7, 0x0e, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chi %r0, -32768" + + - + input: + bytes: [ 0xa7, 0x0e, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chi %r0, -1" + + - + input: + bytes: [ 0xa7, 0x0e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chi %r0, 0" + + - + input: + bytes: [ 0xa7, 0x0e, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chi %r0, 1" + + - + input: + bytes: [ 0xa7, 0x0e, 0x7f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chi %r0, 32767" + + - + input: + bytes: [ 0xa7, 0xfe, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chi %r15, 0" + + - + input: + bytes: [ 0xb9, 0xdd, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chlr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xdd, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chlr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xdd, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chlr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xdd, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chlr %r7, %r8" + + - + input: + bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chsi 0, 0" + + - + input: + bytes: [ 0xe5, 0x5c, 0x0f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chsi 4095, 0" + + - + input: + bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chsi 0, -32768" + + - + input: + bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chsi 0, -1" + + - + input: + bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chsi 0, 0" + + - + input: + bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chsi 0, 1" + + - + input: + bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x7f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chsi 0, 32767" + + - + input: + bytes: [ 0xe5, 0x5c, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chsi 0(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x5c, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chsi 0(%r15), 42" + + - + input: + bytes: [ 0xe5, 0x5c, 0x1f, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chsi 4095(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x5c, 0xff, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chsi 4095(%r15), 42" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x79 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chy %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x79 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chy %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x79 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chy %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x79 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chy %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x79 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chy %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x79 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chy %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x79 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chy %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x79 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chy %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x79 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chy %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x79 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "chy %r15, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cib %r0, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x80, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cib %r0, -128, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xff, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cib %r0, -1, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x7f, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cib %r0, 127, 0, 0" + + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cib %r15, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x70, 0x00, 0x00, 0x64, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cib %r7, 100, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cib %r0, 0, 0, 4095(%r15)" + + - + input: + bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cib %r0, 0, 0, 0(%r8)" + + - + input: + bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cib %r0, 0, 0, 4095(%r7)" + + - + input: + bytes: [ 0xec, 0x01, 0x00, 0x00, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cib %r0, 0, 1, 0" + + - + input: + bytes: [ 0xec, 0x02, 0x00, 0x00, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cibh %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x03, 0x00, 0x00, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cib %r0, 0, 3, 0" + + - + input: + bytes: [ 0xec, 0x04, 0x00, 0x00, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cibl %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x05, 0x00, 0x00, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cib %r0, 0, 5, 0" + + - + input: + bytes: [ 0xec, 0x06, 0x00, 0x00, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ciblh %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x07, 0x00, 0x00, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cib %r0, 0, 7, 0" + + - + input: + bytes: [ 0xec, 0x08, 0x00, 0x00, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cibe %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x09, 0x00, 0x00, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cib %r0, 0, 9, 0" + + - + input: + bytes: [ 0xec, 0x0a, 0x00, 0x00, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cibhe %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x0b, 0x00, 0x00, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cib %r0, 0, 11, 0" + + - + input: + bytes: [ 0xec, 0x0c, 0x00, 0x00, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cible %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x0d, 0x00, 0x00, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cib %r0, 0, 13, 0" + + - + input: + bytes: [ 0xec, 0x0e, 0x00, 0x00, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cib %r0, 0, 14, 0" + + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xfe ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cib %r0, 0, 15, 0" + + - + input: + bytes: [ 0xcc, 0x0d, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cih %r0, -2147483648" + + - + input: + bytes: [ 0xcc, 0x0d, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cih %r0, -1" + + - + input: + bytes: [ 0xcc, 0x0d, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cih %r0, 0" + + - + input: + bytes: [ 0xcc, 0x0d, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cih %r0, 1" + + - + input: + bytes: [ 0xcc, 0x0d, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cih %r0, 2147483647" + + - + input: + bytes: [ 0xcc, 0xfd, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cih %r15, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x20, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cith %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x40, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "citl %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x80, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cite %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x60, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "citlh %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xa0, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cithe %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xc0, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "citle %r0, 0" + + - + input: + bytes: [ 0xb2, 0x41, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cksm %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x41, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cksm %r0, %r14" + + - + input: + bytes: [ 0xb2, 0x41, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cksm %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x41, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cksm %r6, %r8" + + - + input: + bytes: [ 0x55, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cl %r0, 0" + + - + input: + bytes: [ 0x55, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cl %r0, 4095" + + - + input: + bytes: [ 0x55, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cl %r0, 0(%r1)" + + - + input: + bytes: [ 0x55, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cl %r0, 0(%r15)" + + - + input: + bytes: [ 0x55, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cl %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x55, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cl %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x55, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cl %r15, 0" + + - + input: + bytes: [ 0xd5, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clc 0(1), 0" + + - + input: + bytes: [ 0xd5, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clc 0(1), 0(%r1)" + + - + input: + bytes: [ 0xd5, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clc 0(1), 0(%r15)" + + - + input: + bytes: [ 0xd5, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clc 0(1), 4095" + + - + input: + bytes: [ 0xd5, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clc 0(1), 4095(%r1)" + + - + input: + bytes: [ 0xd5, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clc 0(1), 4095(%r15)" + + - + input: + bytes: [ 0xd5, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clc 0(1,%r1), 0" + + - + input: + bytes: [ 0xd5, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clc 0(1,%r15), 0" + + - + input: + bytes: [ 0xd5, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clc 4095(1,%r1), 0" + + - + input: + bytes: [ 0xd5, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clc 4095(1,%r15), 0" + + - + input: + bytes: [ 0xd5, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clc 0(256,%r1), 0" + + - + input: + bytes: [ 0xd5, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clc 0(256,%r15), 0" + + - + input: + bytes: [ 0x0f, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clcl %r0, %r8" + + - + input: + bytes: [ 0x0f, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clcl %r0, %r14" + + - + input: + bytes: [ 0x0f, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clcl %r14, %r0" + + - + input: + bytes: [ 0x0f, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clcl %r14, %r8" + + - + input: + bytes: [ 0xa9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clcle %r0, %r0, 0" + + - + input: + bytes: [ 0xa9, 0x0e, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clcle %r0, %r14, 4095" + + - + input: + bytes: [ 0xa9, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clcle %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xa9, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clcle %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xa9, 0x0e, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clcle %r0, %r14, 4095(%r15)" + + - + input: + bytes: [ 0xa9, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clcle %r0, %r0, 4095(%r1)" + + - + input: + bytes: [ 0xa9, 0xe0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clcle %r14, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clclu %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clclu %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x0e, 0x00, 0x00, 0x00, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clclu %r0, %r14, 0" + + - + input: + bytes: [ 0xeb, 0x0e, 0x00, 0x01, 0x00, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clclu %r0, %r14, 1" + + - + input: + bytes: [ 0xeb, 0x08, 0x0f, 0xff, 0x7f, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clclu %r0, %r8, 524287" + + - + input: + bytes: [ 0xeb, 0x08, 0x10, 0x00, 0x00, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clclu %r0, %r8, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x04, 0xf0, 0x00, 0x00, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clclu %r0, %r4, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x04, 0xff, 0xff, 0x7f, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clclu %r0, %r4, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clclu %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0xe0, 0x00, 0x00, 0x00, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clclu %r14, %r0, 0" + + - + input: + bytes: [ 0xb3, 0x9d, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfdbr %r0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x9d, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfdbr %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0x9d, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfdbr %r0, 0, %f15, 1" + + - + input: + bytes: [ 0xb3, 0x9d, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfdbr %r0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x9d, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfdbr %r4, 5, %f6, 7" + + - + input: + bytes: [ 0xb3, 0x9d, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfdbr %r15, 0, %f0, 1" + + - + input: + bytes: [ 0xb9, 0x43, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfdtr %r0, 0, %f0, 0" + + - + input: + bytes: [ 0xb9, 0x43, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfdtr %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb9, 0x43, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfdtr %r0, 0, %f15, 0" + + - + input: + bytes: [ 0xb9, 0x43, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfdtr %r0, 15, %f0, 0" + + - + input: + bytes: [ 0xb9, 0x43, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfdtr %r4, 5, %f6, 7" + + - + input: + bytes: [ 0xb9, 0x43, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfdtr %r15, 0, %f0, 0" + + - + input: + bytes: [ 0xb3, 0x9c, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfebr %r0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x9c, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfebr %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0x9c, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfebr %r0, 0, %f15, 1" + + - + input: + bytes: [ 0xb3, 0x9c, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfebr %r0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x9c, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfebr %r4, 5, %f6, 7" + + - + input: + bytes: [ 0xb3, 0x9c, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfebr %r15, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x9e, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfxbr %r0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x9e, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfxbr %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0x9e, 0x01, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfxbr %r0, 0, %f13, 1" + + - + input: + bytes: [ 0xb3, 0x9e, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfxbr %r0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x9e, 0x59, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfxbr %r4, 5, %f8, 9" + + - + input: + bytes: [ 0xb3, 0x9e, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfxbr %r15, 0, %f0, 1" + + - + input: + bytes: [ 0xb9, 0x4b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfxtr %r0, 0, %f0, 0" + + - + input: + bytes: [ 0xb9, 0x4b, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfxtr %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb9, 0x4b, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfxtr %r0, 0, %f13, 0" + + - + input: + bytes: [ 0xb9, 0x4b, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfxtr %r0, 15, %f0, 0" + + - + input: + bytes: [ 0xb9, 0x4b, 0x59, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfxtr %r7, 5, %f8, 9" + + - + input: + bytes: [ 0xb9, 0x4b, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfxtr %r15, 0, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xad, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgdbr %r0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xad, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgdbr %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xad, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgdbr %r0, 0, %f15, 1" + + - + input: + bytes: [ 0xb3, 0xad, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgdbr %r0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xad, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgdbr %r4, 5, %f6, 7" + + - + input: + bytes: [ 0xb3, 0xad, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgdbr %r15, 0, %f0, 1" + + - + input: + bytes: [ 0xb9, 0x42, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgdtr %r0, 0, %f0, 0" + + - + input: + bytes: [ 0xb9, 0x42, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgdtr %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb9, 0x42, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgdtr %r0, 0, %f15, 0" + + - + input: + bytes: [ 0xb9, 0x42, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgdtr %r0, 15, %f0, 0" + + - + input: + bytes: [ 0xb9, 0x42, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgdtr %r4, 5, %f6, 7" + + - + input: + bytes: [ 0xb9, 0x42, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgdtr %r15, 0, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xac, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgebr %r0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xac, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgebr %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xac, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgebr %r0, 0, %f15, 1" + + - + input: + bytes: [ 0xb3, 0xac, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgebr %r0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xac, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgebr %r4, 5, %f6, 7" + + - + input: + bytes: [ 0xb3, 0xac, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgebr %r15, 0, %f0, 1" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgib %r0, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x80, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgib %r0, 128, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xff, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgib %r0, 255, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x7f, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgib %r0, 127, 0, 0" + + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgib %r15, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x70, 0x00, 0x00, 0x64, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgib %r7, 100, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgib %r0, 0, 0, 4095(%r15)" + + - + input: + bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgib %r0, 0, 0, 0(%r8)" + + - + input: + bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgib %r0, 0, 0, 4095(%r7)" + + - + input: + bytes: [ 0xec, 0x01, 0x00, 0x00, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgib %r0, 0, 1, 0" + + - + input: + bytes: [ 0xec, 0x02, 0x00, 0x00, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgibh %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x03, 0x00, 0x00, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgib %r0, 0, 3, 0" + + - + input: + bytes: [ 0xec, 0x04, 0x00, 0x00, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgibl %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x05, 0x00, 0x00, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgib %r0, 0, 5, 0" + + - + input: + bytes: [ 0xec, 0x06, 0x00, 0x00, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgiblh %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x07, 0x00, 0x00, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgib %r0, 0, 7, 0" + + - + input: + bytes: [ 0xec, 0x08, 0x00, 0x00, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgibe %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x09, 0x00, 0x00, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgib %r0, 0, 9, 0" + + - + input: + bytes: [ 0xec, 0x0a, 0x00, 0x00, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgibhe %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x0b, 0x00, 0x00, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgib %r0, 0, 11, 0" + + - + input: + bytes: [ 0xec, 0x0c, 0x00, 0x00, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgible %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x0d, 0x00, 0x00, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgib %r0, 0, 13, 0" + + - + input: + bytes: [ 0xec, 0x0e, 0x00, 0x00, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgib %r0, 0, 14, 0" + + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgib %r0, 0, 15, 0" + + - + input: + bytes: [ 0xb3, 0xae, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgxbr %r0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xae, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgxbr %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xae, 0x01, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgxbr %r0, 0, %f13, 1" + + - + input: + bytes: [ 0xb3, 0xae, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgxbr %r0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xae, 0x59, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgxbr %r4, 5, %f8, 9" + + - + input: + bytes: [ 0xb3, 0xae, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgxbr %r15, 0, %f0, 1" + + - + input: + bytes: [ 0xb9, 0x4a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgxtr %r0, 0, %f0, 0" + + - + input: + bytes: [ 0xb9, 0x4a, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgxtr %r0, 0, %f0, 15" + + - + input: + bytes: [ 0xb9, 0x4a, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgxtr %r0, 0, %f13, 0" + + - + input: + bytes: [ 0xb9, 0x4a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgxtr %r0, 15, %f0, 0" + + - + input: + bytes: [ 0xb9, 0x4a, 0x59, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgxtr %r7, 5, %f8, 9" + + - + input: + bytes: [ 0xb9, 0x4a, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgxtr %r15, 0, %f0, 0" + + - + input: + bytes: [ 0xe5, 0x5d, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfhsi 0, 0" + + - + input: + bytes: [ 0xe5, 0x5d, 0x0f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfhsi 4095, 0" + + - + input: + bytes: [ 0xe5, 0x5d, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfhsi 0, 65535" + + - + input: + bytes: [ 0xe5, 0x5d, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfhsi 0(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x5d, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfhsi 0(%r15), 42" + + - + input: + bytes: [ 0xe5, 0x5d, 0x1f, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfhsi 4095(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x5d, 0xff, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfhsi 4095(%r15), 42" + + - + input: + bytes: [ 0xc2, 0x0f, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfi %r0, 0" + + - + input: + bytes: [ 0xc2, 0x0f, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfi %r0, 4294967295" + + - + input: + bytes: [ 0xc2, 0xff, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfi %r15, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x20, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfith %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x40, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfitl %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x80, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfite %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x60, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfitlh %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xa0, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfithe %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xc0, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clfitle %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clg %r15, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x20, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgith %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x40, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgitl %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x80, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgite %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x60, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgitlh %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xa0, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgithe %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xc0, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgitle %r0, 0" + + - + input: + bytes: [ 0xc2, 0x0e, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgfi %r0, 0" + + - + input: + bytes: [ 0xc2, 0x0e, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgfi %r0, 4294967295" + + - + input: + bytes: [ 0xc2, 0xfe, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgfi %r15, 0" + + - + input: + bytes: [ 0xb9, 0x31, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgfr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x31, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgfr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x31, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgfr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x31, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgfr %r7, %r8" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgf %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgf %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgf %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgf %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgf %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgf %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgf %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgf %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgf %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x31 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgf %r15, 0" + + - + input: + bytes: [ 0xe5, 0x59, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clghsi 0, 0" + + - + input: + bytes: [ 0xe5, 0x59, 0x0f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clghsi 4095, 0" + + - + input: + bytes: [ 0xe5, 0x59, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clghsi 0, 65535" + + - + input: + bytes: [ 0xe5, 0x59, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clghsi 0(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x59, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clghsi 0(%r15), 42" + + - + input: + bytes: [ 0xe5, 0x59, 0x1f, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clghsi 4095(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x59, 0xff, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clghsi 4095(%r15), 42" + + - + input: + bytes: [ 0xb9, 0x21, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x21, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x21, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x21, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgr %r7, %r8" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrb %r0, %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrb %r0, %r15, 0, 0" + + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrb %r15, %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x78, 0x00, 0x00, 0x00, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrb %r7, %r8, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrb %r0, %r0, 0, 4095(%r15)" + + - + input: + bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrb %r0, %r0, 0, 0(%r8)" + + - + input: + bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrb %r0, %r0, 0, 4095(%r7)" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x10, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrb %r0, %r0, 1, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x20, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrbh %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x30, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrb %r0, %r0, 3, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x40, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrbl %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x50, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrb %r0, %r0, 5, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x60, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrblh %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x70, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrb %r0, %r0, 7, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x80, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrbe %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x90, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrb %r0, %r0, 9, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xa0, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrbhe %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xb0, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrb %r0, %r0, 11, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xc0, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrble %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xd0, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrb %r0, %r0, 13, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xe0, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrb %r0, %r0, 14, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xf0, 0xe5 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrb %r0, %r0, 15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xcf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhf %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xcf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhf %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xcf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhf %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xcf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhf %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xcf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhf %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xcf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhf %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xcf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhf %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xcf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhf %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xcf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhf %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xcf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhf %r15, 0" + + - + input: + bytes: [ 0xb9, 0xcf, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhhr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xcf, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhhr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xcf, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhhr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xcf, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhhr %r7, %r8" + + - + input: + bytes: [ 0xe5, 0x55, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhhsi 0, 0" + + - + input: + bytes: [ 0xe5, 0x55, 0x0f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhhsi 4095, 0" + + - + input: + bytes: [ 0xe5, 0x55, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhhsi 0, 65535" + + - + input: + bytes: [ 0xe5, 0x55, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhhsi 0(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x55, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhhsi 0(%r15), 42" + + - + input: + bytes: [ 0xe5, 0x55, 0x1f, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhhsi 4095(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x55, 0xff, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhhsi 4095(%r15), 42" + + - + input: + bytes: [ 0xb9, 0xdf, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhlr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xdf, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhlr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xdf, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhlr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xdf, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clhlr %r7, %r8" + + - + input: + bytes: [ 0x95, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cli 0, 0" + + - + input: + bytes: [ 0x95, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cli 4095, 0" + + - + input: + bytes: [ 0x95, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cli 0, 255" + + - + input: + bytes: [ 0x95, 0x2a, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cli 0(%r1), 42" + + - + input: + bytes: [ 0x95, 0x2a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cli 0(%r15), 42" + + - + input: + bytes: [ 0x95, 0x2a, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cli 4095(%r1), 42" + + - + input: + bytes: [ 0x95, 0x2a, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cli 4095(%r15), 42" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clib %r0, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x80, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clib %r0, 128, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clib %r0, 255, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x7f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clib %r0, 127, 0, 0" + + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clib %r15, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x70, 0x00, 0x00, 0x64, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clib %r7, 100, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clib %r0, 0, 0, 4095(%r15)" + + - + input: + bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clib %r0, 0, 0, 0(%r8)" + + - + input: + bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clib %r0, 0, 0, 4095(%r7)" + + - + input: + bytes: [ 0xec, 0x01, 0x00, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clib %r0, 0, 1, 0" + + - + input: + bytes: [ 0xec, 0x02, 0x00, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clibh %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x03, 0x00, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clib %r0, 0, 3, 0" + + - + input: + bytes: [ 0xec, 0x04, 0x00, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clibl %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x05, 0x00, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clib %r0, 0, 5, 0" + + - + input: + bytes: [ 0xec, 0x06, 0x00, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cliblh %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x07, 0x00, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clib %r0, 0, 7, 0" + + - + input: + bytes: [ 0xec, 0x08, 0x00, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clibe %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x09, 0x00, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clib %r0, 0, 9, 0" + + - + input: + bytes: [ 0xec, 0x0a, 0x00, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clibhe %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x0b, 0x00, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clib %r0, 0, 11, 0" + + - + input: + bytes: [ 0xec, 0x0c, 0x00, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clible %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x0d, 0x00, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clib %r0, 0, 13, 0" + + - + input: + bytes: [ 0xec, 0x0e, 0x00, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clib %r0, 0, 14, 0" + + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clib %r0, 0, 15, 0" + + - + input: + bytes: [ 0xcc, 0x0f, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clih %r0, 0" + + - + input: + bytes: [ 0xcc, 0x0f, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clih %r0, 1" + + - + input: + bytes: [ 0xcc, 0x0f, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clih %r0, 4294967295" + + - + input: + bytes: [ 0xcc, 0xff, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clih %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cliy -524288, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cliy -1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cliy 0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cliy 1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cliy 524287, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cliy 0, 255" + + - + input: + bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cliy 0(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cliy 0(%r15), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cliy 524287(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cliy 524287(%r15), 42" + + - + input: + bytes: [ 0xbd, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clm %r0, 0, 0" + + - + input: + bytes: [ 0xbd, 0x0f, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clm %r0, 15, 4095" + + - + input: + bytes: [ 0xbd, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clm %r0, 0, 0(%r1)" + + - + input: + bytes: [ 0xbd, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clm %r0, 0, 0(%r15)" + + - + input: + bytes: [ 0xbd, 0x0f, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clm %r0, 15, 4095(%r15)" + + - + input: + bytes: [ 0xbd, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clm %r0, 0, 4095(%r1)" + + - + input: + bytes: [ 0xbd, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clm %r15, 0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmh %r0, 0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmh %r0, 0, -1" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmh %r0, 15, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x01, 0x00, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmh %r0, 15, 1" + + - + input: + bytes: [ 0xeb, 0x08, 0x0f, 0xff, 0x7f, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmh %r0, 8, 524287" + + - + input: + bytes: [ 0xeb, 0x08, 0x10, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmh %r0, 8, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x04, 0xf0, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmh %r0, 4, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x04, 0xff, 0xff, 0x7f, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmh %r0, 4, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmh %r0, 0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmh %r15, 0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmy %r0, 0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmy %r0, 0, -1" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmy %r0, 15, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x01, 0x00, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmy %r0, 15, 1" + + - + input: + bytes: [ 0xeb, 0x08, 0x0f, 0xff, 0x7f, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmy %r0, 8, 524287" + + - + input: + bytes: [ 0xeb, 0x08, 0x10, 0x00, 0x00, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmy %r0, 8, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x04, 0xf0, 0x00, 0x00, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmy %r0, 4, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x04, 0xff, 0xff, 0x7f, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmy %r0, 4, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmy %r0, 0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0x21 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clmy %r15, 0, 0" + + - + input: + bytes: [ 0x15, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clr %r0, %r0" + + - + input: + bytes: [ 0x15, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clr %r0, %r15" + + - + input: + bytes: [ 0x15, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clr %r15, %r0" + + - + input: + bytes: [ 0x15, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clr %r7, %r8" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrb %r0, %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrb %r0, %r15, 0, 0" + + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrb %r15, %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x78, 0x00, 0x00, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrb %r7, %r8, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrb %r0, %r0, 0, 4095(%r15)" + + - + input: + bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrb %r0, %r0, 0, 0(%r8)" + + - + input: + bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrb %r0, %r0, 0, 4095(%r7)" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x10, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrb %r0, %r0, 1, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x20, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrbh %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x30, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrb %r0, %r0, 3, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x40, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrbl %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x50, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrb %r0, %r0, 5, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x60, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrblh %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x70, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrb %r0, %r0, 7, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x80, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrbe %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x90, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrb %r0, %r0, 9, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xa0, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrbhe %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xb0, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrb %r0, %r0, 11, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xc0, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrble %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xd0, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrb %r0, %r0, 13, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xe0, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrb %r0, %r0, 14, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xf0, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrb %r0, %r0, 15, 0" + + - + input: + bytes: [ 0xb9, 0x61, 0x20, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrth %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x61, 0x40, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrtl %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x61, 0x80, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrte %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x61, 0x60, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrtlh %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x61, 0xa0, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrthe %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x61, 0xc0, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgrtle %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x73, 0x20, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrth %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x73, 0x40, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrtl %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x73, 0x80, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrte %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x73, 0x60, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrtlh %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x73, 0xa0, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrthe %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x73, 0xc0, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clrtle %r0, %r1" + + - + input: + bytes: [ 0xeb, 0x02, 0x00, 0x00, 0x80, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clth %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x02, 0x0f, 0xff, 0xff, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clth %r0, -1" + + - + input: + bytes: [ 0xeb, 0x02, 0x00, 0x00, 0x00, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clth %r0, 0" + + - + input: + bytes: [ 0xeb, 0x02, 0x00, 0x01, 0x00, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clth %r0, 1" + + - + input: + bytes: [ 0xeb, 0x02, 0x0f, 0xff, 0x7f, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clth %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x02, 0x10, 0x00, 0x00, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clth %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x02, 0xf0, 0x00, 0x00, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clth %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x02, 0x60, 0x39, 0x03, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clth %r0, 12345(%r6)" + + - + input: + bytes: [ 0xeb, 0x12, 0x00, 0x00, 0x00, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clth %r1, 0" + + - + input: + bytes: [ 0xeb, 0x14, 0x00, 0x00, 0x00, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cltl %r1, 0" + + - + input: + bytes: [ 0xeb, 0x18, 0x00, 0x00, 0x00, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clte %r1, 0" + + - + input: + bytes: [ 0xeb, 0x16, 0x00, 0x00, 0x00, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cltlh %r1, 0" + + - + input: + bytes: [ 0xeb, 0x1a, 0x00, 0x00, 0x00, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clthe %r1, 0" + + - + input: + bytes: [ 0xeb, 0x1c, 0x00, 0x00, 0x00, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cltle %r1, 0" + + - + input: + bytes: [ 0xeb, 0x02, 0x00, 0x00, 0x80, 0x2b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgth %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x02, 0x0f, 0xff, 0xff, 0x2b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgth %r0, -1" + + - + input: + bytes: [ 0xeb, 0x02, 0x00, 0x00, 0x00, 0x2b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgth %r0, 0" + + - + input: + bytes: [ 0xeb, 0x02, 0x00, 0x01, 0x00, 0x2b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgth %r0, 1" + + - + input: + bytes: [ 0xeb, 0x02, 0x0f, 0xff, 0x7f, 0x2b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgth %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x02, 0x10, 0x00, 0x00, 0x2b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgth %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x02, 0xf0, 0x00, 0x00, 0x2b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgth %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x02, 0x60, 0x39, 0x03, 0x2b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgth %r0, 12345(%r6)" + + - + input: + bytes: [ 0xeb, 0x12, 0x00, 0x00, 0x00, 0x2b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgth %r1, 0" + + - + input: + bytes: [ 0xeb, 0x14, 0x00, 0x00, 0x00, 0x2b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgtl %r1, 0" + + - + input: + bytes: [ 0xeb, 0x18, 0x00, 0x00, 0x00, 0x2b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgte %r1, 0" + + - + input: + bytes: [ 0xeb, 0x16, 0x00, 0x00, 0x00, 0x2b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgtlh %r1, 0" + + - + input: + bytes: [ 0xeb, 0x1a, 0x00, 0x00, 0x00, 0x2b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgthe %r1, 0" + + - + input: + bytes: [ 0xeb, 0x1c, 0x00, 0x00, 0x00, 0x2b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clgtle %r1, 0" + + - + input: + bytes: [ 0xb2, 0x5d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clst %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x5d, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clst %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x5d, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clst %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x5d, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "clst %r7, %r8" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cly %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cly %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cly %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cly %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cly %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cly %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cly %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cly %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cly %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cly %r15, 0" + + - + input: + bytes: [ 0xb2, 0x63, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpsc %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x63, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpsc %r0, %r14" + + - + input: + bytes: [ 0xb2, 0x63, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpsc %r14, %r0" + + - + input: + bytes: [ 0xb2, 0x63, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cmpsc %r6, %r8" + + - + input: + bytes: [ 0xf9, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cp 0(1), 0(1)" + + - + input: + bytes: [ 0xf9, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cp 0(1), 0(1,%r1)" + + - + input: + bytes: [ 0xf9, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cp 0(1), 0(1,%r15)" + + - + input: + bytes: [ 0xf9, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cp 0(1), 4095(1)" + + - + input: + bytes: [ 0xf9, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cp 0(1), 4095(1,%r1)" + + - + input: + bytes: [ 0xf9, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cp 0(1), 4095(1,%r15)" + + - + input: + bytes: [ 0xf9, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cp 0(1,%r1), 0(1)" + + - + input: + bytes: [ 0xf9, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cp 0(1,%r15), 0(1)" + + - + input: + bytes: [ 0xf9, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cp 4095(1,%r1), 0(1)" + + - + input: + bytes: [ 0xf9, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cp 4095(1,%r15), 0(1)" + + - + input: + bytes: [ 0xf9, 0xf0, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cp 0(16,%r1), 0(1)" + + - + input: + bytes: [ 0xf9, 0xf0, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cp 0(16,%r15), 0(1)" + + - + input: + bytes: [ 0xf9, 0x0f, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cp 0(1), 0(16,%r1)" + + - + input: + bytes: [ 0xf9, 0x0f, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cp 0(1), 0(16,%r15)" + + - + input: + bytes: [ 0xb3, 0x72, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpsdr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x72, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpsdr %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x72, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpsdr %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x72, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpsdr %f15, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x72, 0x20, 0x13 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpsdr %f1, %f2, %f3" + + - + input: + bytes: [ 0xb3, 0x72, 0xf0, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpsdr %f15, %f15, %f15" + + - + input: + bytes: [ 0xb2, 0x4d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpya %a0, %a0" + + - + input: + bytes: [ 0xb2, 0x4d, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpya %a0, %a15" + + - + input: + bytes: [ 0xb2, 0x4d, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpya %a15, %a0" + + - + input: + bytes: [ 0xb2, 0x4d, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpya %a7, %a8" + + - + input: + bytes: [ 0xb2, 0x4d, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cpya %a15, %a15" + + - + input: + bytes: [ 0x19, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cr %r0, %r0" + + - + input: + bytes: [ 0x19, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cr %r0, %r15" + + - + input: + bytes: [ 0x19, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cr %r15, %r0" + + - + input: + bytes: [ 0x19, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cr %r7, %r8" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crb %r0, %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crb %r0, %r15, 0, 0" + + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crb %r15, %r0, 0, 0" + + - + input: + bytes: [ 0xec, 0x78, 0x00, 0x00, 0x00, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crb %r7, %r8, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crb %r0, %r0, 0, 4095(%r15)" + + - + input: + bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crb %r0, %r0, 0, 0(%r8)" + + - + input: + bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crb %r0, %r0, 0, 4095(%r7)" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x10, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crb %r0, %r0, 1, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x20, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crbh %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x30, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crb %r0, %r0, 3, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x40, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crbl %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x50, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crb %r0, %r0, 5, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x60, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crblh %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x70, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crb %r0, %r0, 7, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x80, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crbe %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x90, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crb %r0, %r0, 9, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xa0, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crbhe %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xb0, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crb %r0, %r0, 11, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xc0, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crble %r0, %r0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xd0, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crb %r0, %r0, 13, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xe0, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crb %r0, %r0, 14, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0xf0, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crb %r0, %r0, 15, 0" + + - + input: + bytes: [ 0xb9, 0x8f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crdte %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x8f, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crdte %r0, %r0, %r14" + + - + input: + bytes: [ 0xb9, 0x8f, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crdte %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x8f, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crdte %r14, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x8f, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crdte %r0, %r0, %r0, 15" + + - + input: + bytes: [ 0xb9, 0x8f, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crdte %r4, %r5, %r6, 7" + + - + input: + bytes: [ 0xb9, 0x72, 0x20, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crth %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x72, 0x40, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crtl %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x72, 0x80, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crte %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x72, 0x60, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crtlh %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x72, 0xa0, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crthe %r0, %r1" + + - + input: + bytes: [ 0xb9, 0x72, 0xc0, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "crtle %r0, %r1" + + - + input: + bytes: [ 0xba, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cs %r0, %r0, 0" + + - + input: + bytes: [ 0xba, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cs %r0, %r0, 4095" + + - + input: + bytes: [ 0xba, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cs %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xba, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cs %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xba, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cs %r0, %r0, 4095(%r1)" + + - + input: + bytes: [ 0xba, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cs %r0, %r0, 4095(%r15)" + + - + input: + bytes: [ 0xba, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cs %r0, %r15, 0" + + - + input: + bytes: [ 0xba, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cs %r15, %r0, 0" + + - + input: + bytes: [ 0xb2, 0x30, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csch" + + - + input: + bytes: [ 0xb3, 0xe3, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csdtr %r0, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xe3, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csdtr %r0, %f15, 0" + + - + input: + bytes: [ 0xb3, 0xe3, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csdtr %r0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xe3, 0x06, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csdtr %r4, %f5, 6" + + - + input: + bytes: [ 0xb3, 0xe3, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csdtr %r15, %f0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csg %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csg %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csg %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csg %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csg %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csg %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csg %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csg %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csg %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csg %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0x30 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csg %r15, %r0, 0" + + - + input: + bytes: [ 0xb2, 0x50, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csp %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x50, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csp %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x50, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csp %r14, %r0" + + - + input: + bytes: [ 0xb2, 0x50, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csp %r6, %r8" + + - + input: + bytes: [ 0xb9, 0x8a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cspg %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x8a, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cspg %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x8a, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cspg %r14, %r0" + + - + input: + bytes: [ 0xb9, 0x8a, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cspg %r6, %r8" + + - + input: + bytes: [ 0xc8, 0x02, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csst 0, 0, %r0" + + - + input: + bytes: [ 0xc8, 0x22, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csst 0, 4095, %r2" + + - + input: + bytes: [ 0xc8, 0x22, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csst 0, 0(%r1), %r2" + + - + input: + bytes: [ 0xc8, 0x22, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csst 0, 0(%r15), %r2" + + - + input: + bytes: [ 0xc8, 0x22, 0x10, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csst 0(%r1), 4095(%r15), %r2" + + - + input: + bytes: [ 0xc8, 0x22, 0x10, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csst 0(%r1), 0(%r15), %r2" + + - + input: + bytes: [ 0xc8, 0x22, 0x1f, 0xff, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csst 4095(%r1), 0(%r15), %r2" + + - + input: + bytes: [ 0xb3, 0xeb, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csxtr %r0, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xeb, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csxtr %r0, %f13, 0" + + - + input: + bytes: [ 0xb3, 0xeb, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csxtr %r0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xeb, 0x06, 0x45 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csxtr %r4, %f5, 6" + + - + input: + bytes: [ 0xb3, 0xeb, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csxtr %r14, %f0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csy %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csy %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csy %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csy %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csy %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csy %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csy %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csy %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csy %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csy %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "csy %r15, %r0, 0" + + - + input: + bytes: [ 0xb2, 0xa7, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu12 %r0, %r0" + + - + input: + bytes: [ 0xb2, 0xa7, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu12 %r0, %r14" + + - + input: + bytes: [ 0xb2, 0xa7, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu12 %r14, %r0" + + - + input: + bytes: [ 0xb2, 0xa7, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu12 %r6, %r8" + + - + input: + bytes: [ 0xb2, 0xa7, 0x10, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu12 %r4, %r12, 1" + + - + input: + bytes: [ 0xb2, 0xa7, 0xf0, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu12 %r4, %r12, 15" + + - + input: + bytes: [ 0xb9, 0xb0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu14 %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xb0, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu14 %r0, %r14" + + - + input: + bytes: [ 0xb9, 0xb0, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu14 %r14, %r0" + + - + input: + bytes: [ 0xb9, 0xb0, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu14 %r6, %r8" + + - + input: + bytes: [ 0xb9, 0xb0, 0x10, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu14 %r4, %r12, 1" + + - + input: + bytes: [ 0xb9, 0xb0, 0xf0, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu14 %r4, %r12, 15" + + - + input: + bytes: [ 0xb2, 0xa6, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu21 %r0, %r0" + + - + input: + bytes: [ 0xb2, 0xa6, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu21 %r0, %r14" + + - + input: + bytes: [ 0xb2, 0xa6, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu21 %r14, %r0" + + - + input: + bytes: [ 0xb2, 0xa6, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu21 %r6, %r8" + + - + input: + bytes: [ 0xb2, 0xa6, 0x10, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu21 %r4, %r12, 1" + + - + input: + bytes: [ 0xb2, 0xa6, 0xf0, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu21 %r4, %r12, 15" + + - + input: + bytes: [ 0xb9, 0xb1, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu24 %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xb1, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu24 %r0, %r14" + + - + input: + bytes: [ 0xb9, 0xb1, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu24 %r14, %r0" + + - + input: + bytes: [ 0xb9, 0xb1, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu24 %r6, %r8" + + - + input: + bytes: [ 0xb9, 0xb1, 0x10, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu24 %r4, %r12, 1" + + - + input: + bytes: [ 0xb9, 0xb1, 0xf0, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu24 %r4, %r12, 15" + + - + input: + bytes: [ 0xb9, 0xb2, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu41 %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xb2, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu41 %r0, %r14" + + - + input: + bytes: [ 0xb9, 0xb2, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu41 %r14, %r0" + + - + input: + bytes: [ 0xb9, 0xb2, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu41 %r6, %r8" + + - + input: + bytes: [ 0xb9, 0xb3, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu42 %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xb3, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu42 %r0, %r14" + + - + input: + bytes: [ 0xb9, 0xb3, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu42 %r14, %r0" + + - + input: + bytes: [ 0xb9, 0xb3, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cu42 %r6, %r8" + + - + input: + bytes: [ 0xb3, 0xe2, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cudtr %r0, %f0" + + - + input: + bytes: [ 0xb3, 0xe2, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cudtr %r0, %f15" + + - + input: + bytes: [ 0xb3, 0xe2, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cudtr %r15, %f0" + + - + input: + bytes: [ 0xb3, 0xe2, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cudtr %r7, %f8" + + - + input: + bytes: [ 0xb3, 0xe2, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cudtr %r15, %f15" + + - + input: + bytes: [ 0xb2, 0x57, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cuse %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x57, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cuse %r0, %r14" + + - + input: + bytes: [ 0xb2, 0x57, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cuse %r14, %r0" + + - + input: + bytes: [ 0xb2, 0x57, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cuse %r6, %r8" + + - + input: + bytes: [ 0xb3, 0xea, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cuxtr %r0, %f0" + + - + input: + bytes: [ 0xb3, 0xea, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cuxtr %r0, %f13" + + - + input: + bytes: [ 0xb3, 0xea, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cuxtr %r14, %f0" + + - + input: + bytes: [ 0xb3, 0xea, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cuxtr %r6, %f8" + + - + input: + bytes: [ 0xb3, 0xea, 0x00, 0xed ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cuxtr %r14, %f13" + + - + input: + bytes: [ 0x4f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvb %r0, 0" + + - + input: + bytes: [ 0x4f, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvb %r0, 4095" + + - + input: + bytes: [ 0x4f, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvb %r0, 0(%r1)" + + - + input: + bytes: [ 0x4f, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvb %r0, 0(%r15)" + + - + input: + bytes: [ 0x4f, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvb %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x4f, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvb %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x4f, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvb %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvbg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvbg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvbg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvbg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvbg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvbg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvbg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvbg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvbg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvbg %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvby %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvby %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvby %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvby %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvby %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvby %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvby %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvby %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvby %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvby %r15, 0" + + - + input: + bytes: [ 0x4e, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvd %r0, 0" + + - + input: + bytes: [ 0x4e, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvd %r0, 4095" + + - + input: + bytes: [ 0x4e, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvd %r0, 0(%r1)" + + - + input: + bytes: [ 0x4e, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvd %r0, 0(%r15)" + + - + input: + bytes: [ 0x4e, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvd %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x4e, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvd %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x4e, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvd %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdg %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdy %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdy %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdy %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdy %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdy %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdy %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdy %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdy %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdy %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cvdy %r15, 0" + + - + input: + bytes: [ 0xb3, 0x49, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxbr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x49, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxbr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x49, 0x00, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxbr %f8, %f8" + + - + input: + bytes: [ 0xb3, 0x49, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxbr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0x96, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxfbr %f0, %r0" + + - + input: + bytes: [ 0xb3, 0x96, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxfbr %f0, %r15" + + - + input: + bytes: [ 0xb3, 0x96, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxfbr %f13, %r0" + + - + input: + bytes: [ 0xb3, 0x96, 0x00, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxfbr %f8, %r7" + + - + input: + bytes: [ 0xb3, 0x96, 0x00, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxfbr %f13, %r15" + + - + input: + bytes: [ 0xb3, 0x96, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxfbra %f0, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0x96, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxfbra %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb3, 0x96, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxfbra %f0, 0, %r15, 1" + + - + input: + bytes: [ 0xb3, 0x96, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxfbra %f0, 15, %r0, 1" + + - + input: + bytes: [ 0xb3, 0x96, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxfbra %f4, 5, %r6, 7" + + - + input: + bytes: [ 0xb3, 0x96, 0x01, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxfbra %f13, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xb6, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxfr %f0, %r0" + + - + input: + bytes: [ 0xb3, 0xb6, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxfr %f0, %r15" + + - + input: + bytes: [ 0xb3, 0xb6, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxfr %f13, %r0" + + - + input: + bytes: [ 0xb3, 0xb6, 0x00, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxfr %f8, %r7" + + - + input: + bytes: [ 0xb3, 0xb6, 0x00, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxfr %f13, %r15" + + - + input: + bytes: [ 0xb9, 0x59, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxftr %f0, 0, %r0, 0" + + - + input: + bytes: [ 0xb9, 0x59, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxftr %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb9, 0x59, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxftr %f0, 0, %r15, 0" + + - + input: + bytes: [ 0xb9, 0x59, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxftr %f0, 15, %r0, 0" + + - + input: + bytes: [ 0xb9, 0x59, 0x5a, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxftr %f4, 5, %r9, 10" + + - + input: + bytes: [ 0xb9, 0x59, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxftr %f13, 0, %r0, 0" + + - + input: + bytes: [ 0xb3, 0xa6, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgbr %f0, %r0" + + - + input: + bytes: [ 0xb3, 0xa6, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgbr %f0, %r15" + + - + input: + bytes: [ 0xb3, 0xa6, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgbr %f13, %r0" + + - + input: + bytes: [ 0xb3, 0xa6, 0x00, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgbr %f8, %r7" + + - + input: + bytes: [ 0xb3, 0xa6, 0x00, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgbr %f13, %r15" + + - + input: + bytes: [ 0xb3, 0xa6, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgbra %f0, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xa6, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgbra %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb3, 0xa6, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgbra %f0, 0, %r15, 1" + + - + input: + bytes: [ 0xb3, 0xa6, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgbra %f0, 15, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xa6, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgbra %f4, 5, %r6, 7" + + - + input: + bytes: [ 0xb3, 0xa6, 0x01, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgbra %f13, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xc6, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgr %f0, %r0" + + - + input: + bytes: [ 0xb3, 0xc6, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgr %f0, %r15" + + - + input: + bytes: [ 0xb3, 0xc6, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgr %f13, %r0" + + - + input: + bytes: [ 0xb3, 0xc6, 0x00, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgr %f8, %r7" + + - + input: + bytes: [ 0xb3, 0xc6, 0x00, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgr %f13, %r15" + + - + input: + bytes: [ 0xb3, 0xf9, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgtr %f0, %r0" + + - + input: + bytes: [ 0xb3, 0xf9, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgtr %f0, %r15" + + - + input: + bytes: [ 0xb3, 0xf9, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgtr %f13, %r0" + + - + input: + bytes: [ 0xb3, 0xf9, 0x00, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgtr %f8, %r7" + + - + input: + bytes: [ 0xb3, 0xf9, 0x00, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgtr %f13, %r15" + + - + input: + bytes: [ 0xb3, 0xf9, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgtra %f0, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xf9, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgtra %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb3, 0xf9, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgtra %f0, 0, %r15, 1" + + - + input: + bytes: [ 0xb3, 0xf9, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgtra %f0, 15, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xf9, 0x5a, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgtra %f4, 5, %r9, 10" + + - + input: + bytes: [ 0xb3, 0xf9, 0x01, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxgtra %f13, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0x92, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlfbr %f0, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0x92, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlfbr %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb3, 0x92, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlfbr %f0, 0, %r15, 1" + + - + input: + bytes: [ 0xb3, 0x92, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlfbr %f0, 15, %r0, 1" + + - + input: + bytes: [ 0xb3, 0x92, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlfbr %f4, 5, %r6, 7" + + - + input: + bytes: [ 0xb3, 0x92, 0x01, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlfbr %f13, 0, %r0, 1" + + - + input: + bytes: [ 0xb9, 0x5b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlftr %f0, 0, %r0, 0" + + - + input: + bytes: [ 0xb9, 0x5b, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlftr %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb9, 0x5b, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlftr %f0, 0, %r15, 0" + + - + input: + bytes: [ 0xb9, 0x5b, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlftr %f0, 15, %r0, 0" + + - + input: + bytes: [ 0xb9, 0x5b, 0x5a, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlftr %f4, 5, %r9, 10" + + - + input: + bytes: [ 0xb9, 0x5b, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlftr %f13, 0, %r0, 0" + + - + input: + bytes: [ 0xb3, 0xa2, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlgbr %f0, 0, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xa2, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlgbr %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb3, 0xa2, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlgbr %f0, 0, %r15, 1" + + - + input: + bytes: [ 0xb3, 0xa2, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlgbr %f0, 15, %r0, 1" + + - + input: + bytes: [ 0xb3, 0xa2, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlgbr %f4, 5, %r6, 7" + + - + input: + bytes: [ 0xb3, 0xa2, 0x01, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlgbr %f13, 0, %r0, 1" + + - + input: + bytes: [ 0xb9, 0x5a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlgtr %f0, 0, %r0, 0" + + - + input: + bytes: [ 0xb9, 0x5a, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlgtr %f0, 0, %r0, 15" + + - + input: + bytes: [ 0xb9, 0x5a, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlgtr %f0, 0, %r15, 0" + + - + input: + bytes: [ 0xb9, 0x5a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlgtr %f0, 15, %r0, 0" + + - + input: + bytes: [ 0xb9, 0x5a, 0x5a, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlgtr %f4, 5, %r9, 10" + + - + input: + bytes: [ 0xb9, 0x5a, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxlgtr %f13, 0, %r0, 0" + + - + input: + bytes: [ 0xb3, 0x69, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x69, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x69, 0x00, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxr %f8, %f8" + + - + input: + bytes: [ 0xb3, 0x69, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0xfb, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxstr %f0, %r0" + + - + input: + bytes: [ 0xb3, 0xfb, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxstr %f0, %r14" + + - + input: + bytes: [ 0xb3, 0xfb, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxstr %f13, %r0" + + - + input: + bytes: [ 0xb3, 0xfb, 0x00, 0x86 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxstr %f8, %r6" + + - + input: + bytes: [ 0xb3, 0xfb, 0x00, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxstr %f13, %r14" + + - + input: + bytes: [ 0xb3, 0xec, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxtr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xec, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxtr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0xec, 0x00, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxtr %f8, %f8" + + - + input: + bytes: [ 0xb3, 0xec, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxtr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0xfa, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxutr %f0, %r0" + + - + input: + bytes: [ 0xb3, 0xfa, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxutr %f0, %r14" + + - + input: + bytes: [ 0xb3, 0xfa, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxutr %f13, %r0" + + - + input: + bytes: [ 0xb3, 0xfa, 0x00, 0x86 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxutr %f8, %r6" + + - + input: + bytes: [ 0xb3, 0xfa, 0x00, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxutr %f13, %r14" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxzt %f0, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xd0, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxzt %f13, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x0f, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxzt %f0, 0(1), 15" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxzt %f0, 0(1,%r1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxzt %f0, 0(1,%r15), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x1f, 0xff, 0x00, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxzt %f0, 4095(1,%r1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0xff, 0xff, 0x00, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxzt %f0, 4095(1,%r15), 0" + + - + input: + bytes: [ 0xed, 0xff, 0x10, 0x00, 0x00, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxzt %f0, 0(256,%r1), 0" + + - + input: + bytes: [ 0xed, 0xff, 0xf0, 0x00, 0x00, 0xab ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cxzt %f0, 0(256,%r15), 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cy %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cy %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cy %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cy %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cy %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cy %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cy %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cy %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cy %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "cy %r15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0xa8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "czdt %f0, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0xa8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "czdt %f15, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x0f, 0xa8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "czdt %f0, 0(1), 15" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0xa8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "czdt %f0, 0(1,%r1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0xa8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "czdt %f0, 0(1,%r15), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x1f, 0xff, 0x00, 0xa8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "czdt %f0, 4095(1,%r1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0xff, 0xff, 0x00, 0xa8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "czdt %f0, 4095(1,%r15), 0" + + - + input: + bytes: [ 0xed, 0xff, 0x10, 0x00, 0x00, 0xa8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "czdt %f0, 0(256,%r1), 0" + + - + input: + bytes: [ 0xed, 0xff, 0xf0, 0x00, 0x00, 0xa8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "czdt %f0, 0(256,%r15), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "czxt %f0, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xd0, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "czxt %f13, 0(1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x0f, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "czxt %f0, 0(1), 15" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "czxt %f0, 0(1,%r1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "czxt %f0, 0(1,%r15), 0" + + - + input: + bytes: [ 0xed, 0x00, 0x1f, 0xff, 0x00, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "czxt %f0, 4095(1,%r1), 0" + + - + input: + bytes: [ 0xed, 0x00, 0xff, 0xff, 0x00, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "czxt %f0, 4095(1,%r15), 0" + + - + input: + bytes: [ 0xed, 0xff, 0x10, 0x00, 0x00, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "czxt %f0, 0(256,%r1), 0" + + - + input: + bytes: [ 0xed, 0xff, 0xf0, 0x00, 0x00, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "czxt %f0, 0(256,%r15), 0" + + - + input: + bytes: [ 0x5d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "d %r0, 0" + + - + input: + bytes: [ 0x5d, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "d %r0, 4095" + + - + input: + bytes: [ 0x5d, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "d %r0, 0(%r1)" + + - + input: + bytes: [ 0x5d, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "d %r0, 0(%r15)" + + - + input: + bytes: [ 0x5d, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "d %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x5d, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "d %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x5d, 0xe0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "d %r14, 0" + + - + input: + bytes: [ 0x6d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dd %f0, 0" + + - + input: + bytes: [ 0x6d, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dd %f0, 4095" + + - + input: + bytes: [ 0x6d, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dd %f0, 0(%r1)" + + - + input: + bytes: [ 0x6d, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dd %f0, 0(%r15)" + + - + input: + bytes: [ 0x6d, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dd %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x6d, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dd %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x6d, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dd %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddb %f15, 0" + + - + input: + bytes: [ 0xb3, 0x1d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddbr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x1d, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddbr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x1d, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddbr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x1d, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddbr %f15, %f0" + + - + input: + bytes: [ 0x2d, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddr %f0, %f0" + + - + input: + bytes: [ 0x2d, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddr %f0, %f15" + + - + input: + bytes: [ 0x2d, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddr %f7, %f8" + + - + input: + bytes: [ 0x2d, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0xd1, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddtr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xd1, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddtr %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0xd1, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddtr %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0xd1, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddtr %f15, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xd1, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddtr %f7, %f8, %f9" + + - + input: + bytes: [ 0xb3, 0xd1, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddtra %f0, %f0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xd1, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddtra %f0, %f0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xd1, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddtra %f0, %f0, %f15, 1" + + - + input: + bytes: [ 0xb3, 0xd1, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddtra %f0, %f15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xd1, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddtra %f15, %f0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xd1, 0x9a, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ddtra %f7, %f8, %f9, 10" + + - + input: + bytes: [ 0x7d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "de %f0, 0" + + - + input: + bytes: [ 0x7d, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "de %f0, 4095" + + - + input: + bytes: [ 0x7d, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "de %f0, 0(%r1)" + + - + input: + bytes: [ 0x7d, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "de %f0, 0(%r15)" + + - + input: + bytes: [ 0x7d, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "de %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x7d, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "de %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x7d, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "de %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "deb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "deb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "deb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "deb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "deb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "deb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "deb %f15, 0" + + - + input: + bytes: [ 0xb3, 0x0d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "debr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x0d, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "debr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x0d, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "debr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x0d, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "debr %f15, %f0" + + - + input: + bytes: [ 0x3d, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "der %f0, %f0" + + - + input: + bytes: [ 0x3d, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "der %f0, %f15" + + - + input: + bytes: [ 0x3d, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "der %f7, %f8" + + - + input: + bytes: [ 0x3d, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "der %f15, %f0" + + - + input: + bytes: [ 0x83, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "diag %r0, %r0, 0" + + - + input: + bytes: [ 0x83, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "diag %r0, %r15, 0" + + - + input: + bytes: [ 0x83, 0xef, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "diag %r14, %r15, 0" + + - + input: + bytes: [ 0x83, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "diag %r15, %r15, 0" + + - + input: + bytes: [ 0x83, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "diag %r0, %r0, 4095" + + - + input: + bytes: [ 0x83, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "diag %r0, %r0, 1" + + - + input: + bytes: [ 0x83, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "diag %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0x83, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "diag %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0x83, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "diag %r0, %r0, 4095(%r1)" + + - + input: + bytes: [ 0x83, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "diag %r0, %r0, 4095(%r15)" + + - + input: + bytes: [ 0xb3, 0x5b, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "didbr %f0, %f0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x5b, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "didbr %f0, %f0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0x5b, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "didbr %f0, %f0, %f15, 1" + + - + input: + bytes: [ 0xb3, 0x5b, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "didbr %f0, %f15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x5b, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "didbr %f4, %f5, %f6, 7" + + - + input: + bytes: [ 0xb3, 0x5b, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "didbr %f15, %f0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x53, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "diebr %f0, %f0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x53, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "diebr %f0, %f0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0x53, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "diebr %f0, %f0, %f15, 1" + + - + input: + bytes: [ 0xb3, 0x53, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "diebr %f0, %f15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x53, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "diebr %f4, %f5, %f6, 7" + + - + input: + bytes: [ 0xb3, 0x53, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "diebr %f15, %f0, %f0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dl %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dl %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dl %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dl %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dl %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dl %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dl %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dl %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dl %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x97 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dl %r14, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dlg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dlg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dlg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dlg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dlg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dlg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dlg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dlg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dlg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x87 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dlg %r14, 0" + + - + input: + bytes: [ 0xb9, 0x87, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dlgr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x87, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dlgr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x87, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dlgr %r14, %r0" + + - + input: + bytes: [ 0xb9, 0x87, 0x00, 0x69 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dlgr %r6, %r9" + + - + input: + bytes: [ 0xb9, 0x97, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dlr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x97, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dlr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x97, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dlr %r14, %r0" + + - + input: + bytes: [ 0xb9, 0x97, 0x00, 0x69 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dlr %r6, %r9" + + - + input: + bytes: [ 0xfd, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dp 0(1), 0(1)" + + - + input: + bytes: [ 0xfd, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dp 0(1), 0(1,%r1)" + + - + input: + bytes: [ 0xfd, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dp 0(1), 0(1,%r15)" + + - + input: + bytes: [ 0xfd, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dp 0(1), 4095(1)" + + - + input: + bytes: [ 0xfd, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dp 0(1), 4095(1,%r1)" + + - + input: + bytes: [ 0xfd, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dp 0(1), 4095(1,%r15)" + + - + input: + bytes: [ 0xfd, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dp 0(1,%r1), 0(1)" + + - + input: + bytes: [ 0xfd, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dp 0(1,%r15), 0(1)" + + - + input: + bytes: [ 0xfd, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dp 4095(1,%r1), 0(1)" + + - + input: + bytes: [ 0xfd, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dp 4095(1,%r15), 0(1)" + + - + input: + bytes: [ 0xfd, 0xf0, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dp 0(16,%r1), 0(1)" + + - + input: + bytes: [ 0xfd, 0xf0, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dp 0(16,%r15), 0(1)" + + - + input: + bytes: [ 0xfd, 0x0f, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dp 0(1), 0(16,%r1)" + + - + input: + bytes: [ 0xfd, 0x0f, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dp 0(1), 0(16,%r15)" + + - + input: + bytes: [ 0x1d, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dr %r0, %r0" + + - + input: + bytes: [ 0x1d, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dr %r0, %r15" + + - + input: + bytes: [ 0x1d, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dr %r14, %r0" + + - + input: + bytes: [ 0x1d, 0x69 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dr %r6, %r9" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsg %r14, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsgf %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsgf %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsgf %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsgf %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsgf %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsgf %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsgf %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsgf %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsgf %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsgf %r14, 0" + + - + input: + bytes: [ 0xb9, 0x1d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsgfr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x1d, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsgfr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x1d, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsgfr %r14, %r0" + + - + input: + bytes: [ 0xb9, 0x1d, 0x00, 0x69 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsgfr %r6, %r9" + + - + input: + bytes: [ 0xb9, 0x0d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsgr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x0d, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsgr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x0d, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsgr %r14, %r0" + + - + input: + bytes: [ 0xb9, 0x0d, 0x00, 0x69 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dsgr %r6, %r9" + + - + input: + bytes: [ 0xb3, 0x4d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dxbr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x4d, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dxbr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x4d, 0x00, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dxbr %f8, %f8" + + - + input: + bytes: [ 0xb3, 0x4d, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dxbr %f13, %f0" + + - + input: + bytes: [ 0xb2, 0x2d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dxr %f0, %f0" + + - + input: + bytes: [ 0xb2, 0x2d, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dxr %f0, %f13" + + - + input: + bytes: [ 0xb2, 0x2d, 0x00, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dxr %f8, %f8" + + - + input: + bytes: [ 0xb2, 0x2d, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dxr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0xd9, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dxtr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xd9, 0xd0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dxtr %f0, %f0, %f13" + + - + input: + bytes: [ 0xb3, 0xd9, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dxtr %f0, %f13, %f0" + + - + input: + bytes: [ 0xb3, 0xd9, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dxtr %f13, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xd9, 0x80, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dxtr %f8, %f8, %f8" + + - + input: + bytes: [ 0xb3, 0xd9, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dxtra %f0, %f0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xd9, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dxtra %f0, %f0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xd9, 0xd1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dxtra %f0, %f0, %f13, 1" + + - + input: + bytes: [ 0xb3, 0xd9, 0x01, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dxtra %f0, %f13, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xd9, 0x01, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dxtra %f13, %f0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xd9, 0x88, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "dxtra %f8, %f8, %f8, 8" + + - + input: + bytes: [ 0xb2, 0x4f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ear %r0, %a0" + + - + input: + bytes: [ 0xb2, 0x4f, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ear %r0, %a15" + + - + input: + bytes: [ 0xb2, 0x4f, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ear %r15, %a0" + + - + input: + bytes: [ 0xb2, 0x4f, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ear %r7, %a8" + + - + input: + bytes: [ 0xb2, 0x4f, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ear %r15, %a15" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecag %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecag %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecag %r14, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecag %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecag %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecag %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecag %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecag %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecag %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecag %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecag %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecag %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecag %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xb2, 0xe4, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecctr %r0, %r0" + + - + input: + bytes: [ 0xb2, 0xe4, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecctr %r0, %r15" + + - + input: + bytes: [ 0xb2, 0xe4, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecctr %r15, %r0" + + - + input: + bytes: [ 0xb2, 0xe4, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecctr %r7, %r8" + + - + input: + bytes: [ 0xb2, 0xed, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecpga %r0, %r0" + + - + input: + bytes: [ 0xb2, 0xed, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecpga %r0, %r15" + + - + input: + bytes: [ 0xb2, 0xed, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecpga %r15, %r0" + + - + input: + bytes: [ 0xb2, 0xed, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ecpga %r7, %r8" + + - + input: + bytes: [ 0xc8, 0x01, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ectg 0, 0, %r0" + + - + input: + bytes: [ 0xc8, 0x21, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ectg 0, 4095, %r2" + + - + input: + bytes: [ 0xc8, 0x21, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ectg 0, 0(%r1), %r2" + + - + input: + bytes: [ 0xc8, 0x21, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ectg 0, 0(%r15), %r2" + + - + input: + bytes: [ 0xc8, 0x21, 0x10, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ectg 0(%r1), 4095(%r15), %r2" + + - + input: + bytes: [ 0xc8, 0x21, 0x10, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ectg 0(%r1), 0(%r15), %r2" + + - + input: + bytes: [ 0xc8, 0x21, 0x1f, 0xff, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ectg 4095(%r1), 0(%r15), %r2" + + - + input: + bytes: [ 0xde, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ed 0(1), 0" + + - + input: + bytes: [ 0xde, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ed 0(1), 0(%r1)" + + - + input: + bytes: [ 0xde, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ed 0(1), 0(%r15)" + + - + input: + bytes: [ 0xde, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ed 0(1), 4095" + + - + input: + bytes: [ 0xde, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ed 0(1), 4095(%r1)" + + - + input: + bytes: [ 0xde, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ed 0(1), 4095(%r15)" + + - + input: + bytes: [ 0xde, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ed 0(1,%r1), 0" + + - + input: + bytes: [ 0xde, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ed 0(1,%r15), 0" + + - + input: + bytes: [ 0xde, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ed 4095(1,%r1), 0" + + - + input: + bytes: [ 0xde, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ed 4095(1,%r15), 0" + + - + input: + bytes: [ 0xde, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ed 0(256,%r1), 0" + + - + input: + bytes: [ 0xde, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ed 0(256,%r15), 0" + + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "edmk 0(1), 0" + + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "edmk 0(1), 0(%r1)" + + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "edmk 0(1), 0(%r15)" + + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "edmk 0(1), 4095" + + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "edmk 0(1), 4095(%r1)" + + - + input: + bytes: [ 0xdf, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "edmk 0(1), 4095(%r15)" + + - + input: + bytes: [ 0xdf, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "edmk 0(1,%r1), 0" + + - + input: + bytes: [ 0xdf, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "edmk 0(1,%r15), 0" + + - + input: + bytes: [ 0xdf, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "edmk 4095(1,%r1), 0" + + - + input: + bytes: [ 0xdf, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "edmk 4095(1,%r15), 0" + + - + input: + bytes: [ 0xdf, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "edmk 0(256,%r1), 0" + + - + input: + bytes: [ 0xdf, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "edmk 0(256,%r15), 0" + + - + input: + bytes: [ 0xb3, 0xe5, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "eedtr %f0, %f9" + + - + input: + bytes: [ 0xb3, 0xe5, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "eedtr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0xe5, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "eedtr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0xe5, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "eedtr %f15, %f9" + + - + input: + bytes: [ 0xb3, 0xed, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "eextr %f0, %f8" + + - + input: + bytes: [ 0xb3, 0xed, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "eextr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0xed, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "eextr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0xed, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "eextr %f13, %f9" + + - + input: + bytes: [ 0xb3, 0x8c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "efpc %r0" + + - + input: + bytes: [ 0xb3, 0x8c, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "efpc %r1" + + - + input: + bytes: [ 0xb3, 0x8c, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "efpc %r15" + + - + input: + bytes: [ 0xb2, 0x26, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "epar %r0" + + - + input: + bytes: [ 0xb2, 0x26, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "epar %r1" + + - + input: + bytes: [ 0xb2, 0x26, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "epar %r15" + + - + input: + bytes: [ 0xb9, 0x9a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "epair %r0" + + - + input: + bytes: [ 0xb9, 0x9a, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "epair %r1" + + - + input: + bytes: [ 0xb9, 0x9a, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "epair %r15" + + - + input: + bytes: [ 0xb2, 0xe5, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "epctr %r0, %r0" + + - + input: + bytes: [ 0xb2, 0xe5, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "epctr %r0, %r15" + + - + input: + bytes: [ 0xb2, 0xe5, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "epctr %r15, %r0" + + - + input: + bytes: [ 0xb2, 0xe5, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "epctr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x8d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "epsw %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x8d, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "epsw %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x8d, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "epsw %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x8d, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "epsw %r6, %r8" + + - + input: + bytes: [ 0xb2, 0x49, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ereg %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x49, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ereg %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x49, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ereg %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x49, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ereg %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x0e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "eregg %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x0e, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "eregg %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x0e, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "eregg %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x0e, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "eregg %r7, %r8" + + - + input: + bytes: [ 0xb2, 0x27, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esar %r0" + + - + input: + bytes: [ 0xb2, 0x27, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esar %r1" + + - + input: + bytes: [ 0xb2, 0x27, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esar %r15" + + - + input: + bytes: [ 0xb9, 0x9b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esair %r0" + + - + input: + bytes: [ 0xb9, 0x9b, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esair %r1" + + - + input: + bytes: [ 0xb9, 0x9b, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esair %r15" + + - + input: + bytes: [ 0xb3, 0xe7, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esdtr %f0, %f9" + + - + input: + bytes: [ 0xb3, 0xe7, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esdtr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0xe7, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esdtr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0xe7, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esdtr %f15, %f9" + + - + input: + bytes: [ 0xb9, 0x9d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esea %r0" + + - + input: + bytes: [ 0xb9, 0x9d, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esea %r1" + + - + input: + bytes: [ 0xb9, 0x9d, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esea %r15" + + - + input: + bytes: [ 0xb2, 0x4a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esta %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x4a, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esta %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x4a, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esta %r14, %r0" + + - + input: + bytes: [ 0xb2, 0x4a, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esta %r6, %r8" + + - + input: + bytes: [ 0xb3, 0xef, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esxtr %f0, %f8" + + - + input: + bytes: [ 0xb3, 0xef, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esxtr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0xef, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esxtr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0xef, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "esxtr %f13, %f9" + + - + input: + bytes: [ 0xb2, 0xec, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "etnd %r0" + + - + input: + bytes: [ 0xb2, 0xec, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "etnd %r15" + + - + input: + bytes: [ 0xb2, 0xec, 0x00, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "etnd %r7" + + - + input: + bytes: [ 0x44, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ex 0, 0" + + - + input: + bytes: [ 0x44, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ex 0, 4095" + + - + input: + bytes: [ 0x44, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ex 0, 0(%r1)" + + - + input: + bytes: [ 0x44, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ex 0, 0(%r15)" + + - + input: + bytes: [ 0x44, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ex 0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x44, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ex 0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x44, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ex %r15, 0" + + - + input: + bytes: [ 0xb3, 0x5f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidbr %f0, 0, %f0" + + - + input: + bytes: [ 0xb3, 0x5f, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidbr %f0, 0, %f15" + + - + input: + bytes: [ 0xb3, 0x5f, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidbr %f0, 15, %f0" + + - + input: + bytes: [ 0xb3, 0x5f, 0x50, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidbr %f4, 5, %f6" + + - + input: + bytes: [ 0xb3, 0x5f, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidbr %f15, 0, %f0" + + - + input: + bytes: [ 0xb3, 0x5f, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidbra %f0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x5f, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidbra %f0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0x5f, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidbra %f0, 0, %f15, 1" + + - + input: + bytes: [ 0xb3, 0x5f, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidbra %f0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x5f, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidbra %f4, 5, %f6, 7" + + - + input: + bytes: [ 0xb3, 0x5f, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidbra %f15, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x7f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x7f, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x7f, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidr %f4, %f6" + + - + input: + bytes: [ 0xb3, 0x7f, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0xd7, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidtr %f0, 0, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xd7, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidtr %f0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xd7, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidtr %f0, 0, %f15, 0" + + - + input: + bytes: [ 0xb3, 0xd7, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidtr %f0, 15, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xd7, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidtr %f4, 5, %f6, 7" + + - + input: + bytes: [ 0xb3, 0xd7, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fidtr %f15, 0, %f0, 0" + + - + input: + bytes: [ 0xb3, 0x57, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fiebr %f0, 0, %f0" + + - + input: + bytes: [ 0xb3, 0x57, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fiebr %f0, 0, %f15" + + - + input: + bytes: [ 0xb3, 0x57, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fiebr %f0, 15, %f0" + + - + input: + bytes: [ 0xb3, 0x57, 0x50, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fiebr %f4, 5, %f6" + + - + input: + bytes: [ 0xb3, 0x57, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fiebr %f15, 0, %f0" + + - + input: + bytes: [ 0xb3, 0x57, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fiebra %f0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x57, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fiebra %f0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0x57, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fiebra %f0, 0, %f15, 1" + + - + input: + bytes: [ 0xb3, 0x57, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fiebra %f0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x57, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fiebra %f4, 5, %f6, 7" + + - + input: + bytes: [ 0xb3, 0x57, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fiebra %f15, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x77, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fier %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x77, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fier %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x77, 0x00, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fier %f4, %f6" + + - + input: + bytes: [ 0xb3, 0x77, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fier %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x47, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixbr %f0, 0, %f0" + + - + input: + bytes: [ 0xb3, 0x47, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixbr %f0, 0, %f13" + + - + input: + bytes: [ 0xb3, 0x47, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixbr %f0, 15, %f0" + + - + input: + bytes: [ 0xb3, 0x47, 0x50, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixbr %f4, 5, %f8" + + - + input: + bytes: [ 0xb3, 0x47, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixbr %f13, 0, %f0" + + - + input: + bytes: [ 0xb3, 0x47, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixbra %f0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x47, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixbra %f0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0x47, 0x01, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixbra %f0, 0, %f13, 1" + + - + input: + bytes: [ 0xb3, 0x47, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixbra %f0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x47, 0x59, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixbra %f4, 5, %f8, 9" + + - + input: + bytes: [ 0xb3, 0x47, 0x01, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixbra %f13, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x67, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x67, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x67, 0x00, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixr %f4, %f8" + + - + input: + bytes: [ 0xb3, 0x67, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0xdf, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixtr %f0, 0, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xdf, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixtr %f0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xdf, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixtr %f0, 0, %f13, 0" + + - + input: + bytes: [ 0xb3, 0xdf, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixtr %f0, 15, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xdf, 0x59, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixtr %f4, 5, %f8, 9" + + - + input: + bytes: [ 0xb3, 0xdf, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "fixtr %f13, 0, %f0, 0" + + - + input: + bytes: [ 0xb9, 0x83, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "flogr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x83, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "flogr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x83, 0x00, 0xa9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "flogr %r10, %r9" + + - + input: + bytes: [ 0xb9, 0x83, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "flogr %r14, %r0" + + - + input: + bytes: [ 0x24, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "hdr %f0, %f0" + + - + input: + bytes: [ 0x24, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "hdr %f0, %f15" + + - + input: + bytes: [ 0x24, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "hdr %f7, %f8" + + - + input: + bytes: [ 0x24, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "hdr %f15, %f0" + + - + input: + bytes: [ 0x34, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "her %f0, %f0" + + - + input: + bytes: [ 0x34, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "her %f0, %f15" + + - + input: + bytes: [ 0x34, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "her %f7, %f8" + + - + input: + bytes: [ 0x34, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "her %f15, %f0" + + - + input: + bytes: [ 0xb2, 0x31, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "hsch" + + - + input: + bytes: [ 0xb2, 0x24, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iac %r0" + + - + input: + bytes: [ 0xb2, 0x24, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iac %r1" + + - + input: + bytes: [ 0xb2, 0x24, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iac %r15" + + - + input: + bytes: [ 0x43, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ic %r0, 0" + + - + input: + bytes: [ 0x43, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ic %r0, 4095" + + - + input: + bytes: [ 0x43, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ic %r0, 0(%r1)" + + - + input: + bytes: [ 0x43, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ic %r0, 0(%r15)" + + - + input: + bytes: [ 0x43, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ic %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x43, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ic %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x43, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ic %r15, 0" + + - + input: + bytes: [ 0xbf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icm %r0, 0, 0" + + - + input: + bytes: [ 0xbf, 0x0f, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icm %r0, 15, 4095" + + - + input: + bytes: [ 0xbf, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icm %r0, 0, 0(%r1)" + + - + input: + bytes: [ 0xbf, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icm %r0, 0, 0(%r15)" + + - + input: + bytes: [ 0xbf, 0x0f, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icm %r0, 15, 4095(%r15)" + + - + input: + bytes: [ 0xbf, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icm %r0, 0, 4095(%r1)" + + - + input: + bytes: [ 0xbf, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icm %r15, 0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmh %r0, 0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmh %r0, 0, -1" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmh %r0, 15, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x01, 0x00, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmh %r0, 15, 1" + + - + input: + bytes: [ 0xeb, 0x08, 0x0f, 0xff, 0x7f, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmh %r0, 8, 524287" + + - + input: + bytes: [ 0xeb, 0x08, 0x10, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmh %r0, 8, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x04, 0xf0, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmh %r0, 4, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x04, 0xff, 0xff, 0x7f, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmh %r0, 4, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmh %r0, 0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmh %r15, 0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmy %r0, 0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmy %r0, 0, -1" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmy %r0, 15, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x01, 0x00, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmy %r0, 15, 1" + + - + input: + bytes: [ 0xeb, 0x08, 0x0f, 0xff, 0x7f, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmy %r0, 8, 524287" + + - + input: + bytes: [ 0xeb, 0x08, 0x10, 0x00, 0x00, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmy %r0, 8, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x04, 0xf0, 0x00, 0x00, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmy %r0, 4, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x04, 0xff, 0xff, 0x7f, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmy %r0, 4, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmy %r0, 0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icmy %r15, 0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icy %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icy %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icy %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icy %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icy %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icy %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icy %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icy %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icy %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x73 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "icy %r15, 0" + + - + input: + bytes: [ 0xb9, 0x8e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "idte %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x8e, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "idte %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x8e, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "idte %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x8e, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "idte %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x8e, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "idte %r0, %r0, %r0, 15" + + - + input: + bytes: [ 0xb9, 0x8e, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "idte %r4, %r5, %r6, 7" + + - + input: + bytes: [ 0xb3, 0xf6, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iedtr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xf6, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iedtr %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0xf6, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iedtr %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0xf6, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iedtr %f15, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xf6, 0x20, 0x13 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iedtr %f1, %f2, %f3" + + - + input: + bytes: [ 0xb3, 0xf6, 0xf0, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iedtr %f15, %f15, %f15" + + - + input: + bytes: [ 0xb3, 0xfe, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iextr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xfe, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iextr %f0, %f0, %f13" + + - + input: + bytes: [ 0xb3, 0xfe, 0xd0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iextr %f0, %f13, %f0" + + - + input: + bytes: [ 0xb3, 0xfe, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iextr %f13, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xfe, 0x80, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iextr %f1, %f8, %f4" + + - + input: + bytes: [ 0xb3, 0xfe, 0xd0, 0xdd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iextr %f13, %f13, %f13" + + - + input: + bytes: [ 0xc0, 0x08, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iihf %r0, 0" + + - + input: + bytes: [ 0xc0, 0x08, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iihf %r0, 4294967295" + + - + input: + bytes: [ 0xc0, 0xf8, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iihf %r15, 0" + + - + input: + bytes: [ 0xa5, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iihh %r0, 0" + + - + input: + bytes: [ 0xa5, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iihh %r0, 32768" + + - + input: + bytes: [ 0xa5, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iihh %r0, 65535" + + - + input: + bytes: [ 0xa5, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iihh %r15, 0" + + - + input: + bytes: [ 0xa5, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iihl %r0, 0" + + - + input: + bytes: [ 0xa5, 0x01, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iihl %r0, 32768" + + - + input: + bytes: [ 0xa5, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iihl %r0, 65535" + + - + input: + bytes: [ 0xa5, 0xf1, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iihl %r15, 0" + + - + input: + bytes: [ 0xc0, 0x09, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iilf %r0, 0" + + - + input: + bytes: [ 0xc0, 0x09, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iilf %r0, 4294967295" + + - + input: + bytes: [ 0xc0, 0xf9, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iilf %r15, 0" + + - + input: + bytes: [ 0xa5, 0x02, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iilh %r0, 0" + + - + input: + bytes: [ 0xa5, 0x02, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iilh %r0, 32768" + + - + input: + bytes: [ 0xa5, 0x02, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iilh %r0, 65535" + + - + input: + bytes: [ 0xa5, 0xf2, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iilh %r15, 0" + + - + input: + bytes: [ 0xa5, 0x03, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iill %r0, 0" + + - + input: + bytes: [ 0xa5, 0x03, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iill %r0, 32768" + + - + input: + bytes: [ 0xa5, 0x03, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iill %r0, 65535" + + - + input: + bytes: [ 0xa5, 0xf3, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iill %r15, 0" + + - + input: + bytes: [ 0xb2, 0x0b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ipk" + + - + input: + bytes: [ 0xb2, 0x22, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ipm %r0" + + - + input: + bytes: [ 0xb2, 0x22, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ipm %r1" + + - + input: + bytes: [ 0xb2, 0x22, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ipm %r15" + + - + input: + bytes: [ 0xb2, 0x21, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ipte %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x21, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ipte %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x21, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ipte %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x21, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ipte %r0, %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x21, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ipte %r0, %r0, %r0, 15" + + - + input: + bytes: [ 0xb2, 0x21, 0x9a, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ipte %r7, %r8, %r9, 10" + + - + input: + bytes: [ 0xb2, 0x29, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iske %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x29, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iske %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x29, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iske %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x29, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "iske %r7, %r8" + + - + input: + bytes: [ 0xb2, 0x23, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ivsk %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x23, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ivsk %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x23, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ivsk %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x23, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ivsk %r7, %r8" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kdb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x18 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kdb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kdb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kdb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x18 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kdb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x18 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kdb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x18 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kdb %f15, 0" + + - + input: + bytes: [ 0xb3, 0x18, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kdbr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x18, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kdbr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x18, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kdbr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x18, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kdbr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0xe0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kdtr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xe0, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kdtr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0xe0, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kdtr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0xe0, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kdtr %f15, %f0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "keb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "keb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "keb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "keb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "keb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "keb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "keb %f15, 0" + + - + input: + bytes: [ 0xb3, 0x08, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kebr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x08, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kebr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x08, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kebr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x08, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kebr %f15, %f0" + + - + input: + bytes: [ 0xb9, 0x3e, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kimd %r2, %r10" + + - + input: + bytes: [ 0xb9, 0x3e, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kimd %r2, %r14" + + - + input: + bytes: [ 0xb9, 0x3e, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kimd %r14, %r2" + + - + input: + bytes: [ 0xb9, 0x3e, 0x00, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kimd %r14, %r10" + + - + input: + bytes: [ 0xb9, 0x3f, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "klmd %r2, %r10" + + - + input: + bytes: [ 0xb9, 0x3f, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "klmd %r2, %r14" + + - + input: + bytes: [ 0xb9, 0x3f, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "klmd %r14, %r2" + + - + input: + bytes: [ 0xb9, 0x3f, 0x00, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "klmd %r14, %r10" + + - + input: + bytes: [ 0xb9, 0x2e, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "km %r2, %r10" + + - + input: + bytes: [ 0xb9, 0x2e, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "km %r2, %r14" + + - + input: + bytes: [ 0xb9, 0x2e, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "km %r14, %r2" + + - + input: + bytes: [ 0xb9, 0x2e, 0x00, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "km %r14, %r10" + + - + input: + bytes: [ 0xb9, 0x1e, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmac %r2, %r10" + + - + input: + bytes: [ 0xb9, 0x1e, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmac %r2, %r14" + + - + input: + bytes: [ 0xb9, 0x1e, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmac %r14, %r2" + + - + input: + bytes: [ 0xb9, 0x1e, 0x00, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmac %r14, %r10" + + - + input: + bytes: [ 0xb9, 0x2f, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmc %r2, %r10" + + - + input: + bytes: [ 0xb9, 0x2f, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmc %r2, %r14" + + - + input: + bytes: [ 0xb9, 0x2f, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmc %r14, %r2" + + - + input: + bytes: [ 0xb9, 0x2f, 0x00, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmc %r14, %r10" + + - + input: + bytes: [ 0xb9, 0x2d, 0x40, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmctr %r2, %r4, %r10" + + - + input: + bytes: [ 0xb9, 0x2d, 0x60, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmctr %r2, %r6, %r14" + + - + input: + bytes: [ 0xb9, 0x2d, 0x80, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmctr %r14, %r8, %r2" + + - + input: + bytes: [ 0xb9, 0x2d, 0xc0, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmctr %r14, %r12, %r10" + + - + input: + bytes: [ 0xb9, 0x2a, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmf %r2, %r10" + + - + input: + bytes: [ 0xb9, 0x2a, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmf %r2, %r14" + + - + input: + bytes: [ 0xb9, 0x2a, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmf %r14, %r2" + + - + input: + bytes: [ 0xb9, 0x2a, 0x00, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmf %r14, %r10" + + - + input: + bytes: [ 0xb9, 0x2b, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmo %r2, %r10" + + - + input: + bytes: [ 0xb9, 0x2b, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmo %r2, %r14" + + - + input: + bytes: [ 0xb9, 0x2b, 0x00, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmo %r14, %r2" + + - + input: + bytes: [ 0xb9, 0x2b, 0x00, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kmo %r14, %r10" + + - + input: + bytes: [ 0xb3, 0x48, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kxbr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x48, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kxbr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x48, 0x00, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kxbr %f8, %f8" + + - + input: + bytes: [ 0xb3, 0x48, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kxbr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0xe8, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kxtr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xe8, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kxtr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0xe8, 0x00, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kxtr %f8, %f8" + + - + input: + bytes: [ 0xb3, 0xe8, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "kxtr %f13, %f0" + + - + input: + bytes: [ 0x58, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "l %r0, 0" + + - + input: + bytes: [ 0x58, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "l %r0, 4095" + + - + input: + bytes: [ 0x58, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "l %r0, 0(%r1)" + + - + input: + bytes: [ 0x58, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "l %r0, 0(%r15)" + + - + input: + bytes: [ 0x58, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "l %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x58, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "l %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x58, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "l %r15, 0" + + - + input: + bytes: [ 0x41, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "la %r0, 0" + + - + input: + bytes: [ 0x41, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "la %r0, 4095" + + - + input: + bytes: [ 0x41, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "la %r0, 0(%r1)" + + - + input: + bytes: [ 0x41, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "la %r0, 0(%r15)" + + - + input: + bytes: [ 0x41, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "la %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x41, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "la %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x41, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "la %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laa %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laa %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laa %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laa %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laa %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laa %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laa %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laa %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laa %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laa %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laa %r15, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laag %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laag %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laag %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laag %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laag %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laag %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laag %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laag %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laag %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laag %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laag %r15, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xfa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laal %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xfa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laal %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xfa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laal %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xfa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laal %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xfa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laal %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xfa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laal %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xfa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laal %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xfa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laal %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xfa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laal %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xfa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laal %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xfa ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laal %r15, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laalg %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laalg %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laalg %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laalg %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laalg %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laalg %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laalg %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laalg %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laalg %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laalg %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xea ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laalg %r15, %r0, 0" + + - + input: + bytes: [ 0x51, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lae %r0, 0" + + - + input: + bytes: [ 0x51, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lae %r0, 4095" + + - + input: + bytes: [ 0x51, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lae %r0, 0(%r1)" + + - + input: + bytes: [ 0x51, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lae %r0, 0(%r15)" + + - + input: + bytes: [ 0x51, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lae %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x51, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lae %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x51, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lae %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laey %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laey %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laey %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laey %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laey %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laey %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laey %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laey %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laey %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x75 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laey %r15, 0" + + - + input: + bytes: [ 0x9a, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lam %a0, %a0, 0" + + - + input: + bytes: [ 0x9a, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lam %a0, %a15, 0" + + - + input: + bytes: [ 0x9a, 0xef, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lam %a14, %a15, 0" + + - + input: + bytes: [ 0x9a, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lam %a15, %a15, 0" + + - + input: + bytes: [ 0x9a, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lam %a0, %a0, 4095" + + - + input: + bytes: [ 0x9a, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lam %a0, %a0, 1" + + - + input: + bytes: [ 0x9a, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lam %a0, %a0, 0(%r1)" + + - + input: + bytes: [ 0x9a, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lam %a0, %a0, 0(%r15)" + + - + input: + bytes: [ 0x9a, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lam %a0, %a0, 4095(%r1)" + + - + input: + bytes: [ 0x9a, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lam %a0, %a0, 4095(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x9a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lamy %a0, %a0, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x9a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lamy %a0, %a15, 0" + + - + input: + bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x9a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lamy %a14, %a15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x9a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lamy %a15, %a15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x9a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lamy %a0, %a0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x9a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lamy %a0, %a0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x9a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lamy %a0, %a0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x9a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lamy %a0, %a0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x9a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lamy %a0, %a0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x9a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lamy %a0, %a0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x9a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lamy %a0, %a0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x9a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lamy %a0, %a0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x9a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lamy %a0, %a0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lan %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xf4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lan %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lan %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xf4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lan %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lan %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lan %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lan %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xf4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lan %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xf4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lan %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lan %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lan %r15, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lang %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lang %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lang %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lang %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lang %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lang %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lang %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lang %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lang %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lang %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lang %r15, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lao %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lao %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lao %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lao %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lao %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lao %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lao %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lao %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lao %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lao %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lao %r15, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laog %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xe6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laog %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laog %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xe6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laog %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laog %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laog %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laog %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xe6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laog %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xe6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laog %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laog %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laog %r15, %r0, 0" + + - + input: + bytes: [ 0xe5, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lasp 0, 0" + + - + input: + bytes: [ 0xe5, 0x00, 0x10, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lasp 0(%r1), 0(%r2)" + + - + input: + bytes: [ 0xe5, 0x00, 0x10, 0xa0, 0xf1, 0x40 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lasp 160(%r1), 320(%r15)" + + - + input: + bytes: [ 0xe5, 0x00, 0x10, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lasp 0(%r1), 4095" + + - + input: + bytes: [ 0xe5, 0x00, 0x10, 0x00, 0x2f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lasp 0(%r1), 4095(%r2)" + + - + input: + bytes: [ 0xe5, 0x00, 0x10, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lasp 0(%r1), 4095(%r15)" + + - + input: + bytes: [ 0xe5, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lasp 0(%r1), 0" + + - + input: + bytes: [ 0xe5, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lasp 0(%r15), 0" + + - + input: + bytes: [ 0xe5, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lasp 4095(%r1), 0" + + - + input: + bytes: [ 0xe5, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lasp 4095(%r15), 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lat %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lat %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lat %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lat %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lat %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lat %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lat %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lat %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lat %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x9f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lat %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lax %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lax %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lax %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lax %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lax %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lax %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lax %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lax %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lax %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lax %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lax %r15, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laxg %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laxg %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laxg %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laxg %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laxg %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laxg %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laxg %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laxg %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laxg %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laxg %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "laxg %r15, %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lay %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lay %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lay %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lay %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lay %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lay %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lay %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lay %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lay %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x71 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lay %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x76 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lb %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x76 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lb %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x76 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lb %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x76 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lb %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x76 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lb %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x76 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lb %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x76 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lb %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x76 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lb %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x76 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lb %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x76 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lb %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbh %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbh %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbh %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbh %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbh %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbh %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbh %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbh %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbh %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbh %r15, 0" + + - + input: + bytes: [ 0xb9, 0x26, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x26, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x26, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lbr %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x84, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcctl 0" + + - + input: + bytes: [ 0xb2, 0x84, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcctl 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x84, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcctl 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x84, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcctl 4095" + + - + input: + bytes: [ 0xb2, 0x84, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcctl 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x84, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcctl 4095(%r15)" + + - + input: + bytes: [ 0xb3, 0x13, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcdbr %f0, %f9" + + - + input: + bytes: [ 0xb3, 0x13, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcdbr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x13, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcdbr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x13, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcdbr %f15, %f9" + + - + input: + bytes: [ 0x23, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcdr %f0, %f9" + + - + input: + bytes: [ 0x23, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcdr %f0, %f15" + + - + input: + bytes: [ 0x23, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcdr %f15, %f0" + + - + input: + bytes: [ 0x23, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcdr %f15, %f9" + + - + input: + bytes: [ 0xb3, 0x03, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcebr %f0, %f9" + + - + input: + bytes: [ 0xb3, 0x03, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcebr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x03, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcebr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x03, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcebr %f15, %f9" + + - + input: + bytes: [ 0x33, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcer %f0, %f9" + + - + input: + bytes: [ 0x33, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcer %f0, %f15" + + - + input: + bytes: [ 0x33, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcer %f15, %f0" + + - + input: + bytes: [ 0x33, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcer %f15, %f9" + + - + input: + bytes: [ 0xb9, 0x13, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcgfr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x13, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcgfr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x13, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcgfr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x13, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcgfr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x03, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcgr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x03, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcgr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x03, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcgr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x03, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcgr %r7, %r8" + + - + input: + bytes: [ 0x13, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcr %r0, %r0" + + - + input: + bytes: [ 0x13, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcr %r0, %r15" + + - + input: + bytes: [ 0x13, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcr %r15, %r0" + + - + input: + bytes: [ 0x13, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcr %r7, %r8" + + - + input: + bytes: [ 0xb7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctl %c0, %c0, 0" + + - + input: + bytes: [ 0xb7, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctl %c0, %c15, 0" + + - + input: + bytes: [ 0xb7, 0xef, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctl %c14, %c15, 0" + + - + input: + bytes: [ 0xb7, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctl %c15, %c15, 0" + + - + input: + bytes: [ 0xb7, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctl %c0, %c0, 4095" + + - + input: + bytes: [ 0xb7, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctl %c0, %c0, 1" + + - + input: + bytes: [ 0xb7, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctl %c0, %c0, 0(%r1)" + + - + input: + bytes: [ 0xb7, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctl %c0, %c0, 0(%r15)" + + - + input: + bytes: [ 0xb7, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctl %c0, %c0, 4095(%r1)" + + - + input: + bytes: [ 0xb7, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctl %c0, %c0, 4095(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctlg %c0, %c0, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctlg %c0, %c15, 0" + + - + input: + bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctlg %c14, %c15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctlg %c15, %c15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctlg %c0, %c0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctlg %c0, %c0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctlg %c0, %c0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctlg %c0, %c0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctlg %c0, %c0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctlg %c0, %c0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctlg %c0, %c0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctlg %c0, %c0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lctlg %c0, %c0, 524287(%r15)" + + - + input: + bytes: [ 0xb3, 0x43, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcxbr %f0, %f8" + + - + input: + bytes: [ 0xb3, 0x43, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcxbr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x43, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcxbr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0x43, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcxbr %f13, %f9" + + - + input: + bytes: [ 0xb3, 0x63, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcxr %f0, %f8" + + - + input: + bytes: [ 0xb3, 0x63, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcxr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x63, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcxr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0x63, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lcxr %f13, %f9" + + - + input: + bytes: [ 0x68, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld %f0, 0" + + - + input: + bytes: [ 0x68, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld %f0, 4095" + + - + input: + bytes: [ 0x68, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld %f0, 0(%r1)" + + - + input: + bytes: [ 0x68, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld %f0, 0(%r15)" + + - + input: + bytes: [ 0x68, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x68, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x68, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ld %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lde %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lde %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lde %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lde %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lde %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lde %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lde %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldeb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldeb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldeb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldeb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldeb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldeb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldeb %f15, 0" + + - + input: + bytes: [ 0xb3, 0x04, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldebr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x04, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldebr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x04, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldebr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x24, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lder %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x24, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lder %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x24, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lder %f15, %f0" + + - + input: + bytes: [ 0xb3, 0xd4, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldetr %f0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xd4, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldetr %f0, %f15, 0" + + - + input: + bytes: [ 0xb3, 0xd4, 0x09, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldetr %f7, %f8, 9" + + - + input: + bytes: [ 0xb3, 0xd4, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldetr %f15, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xc1, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldgr %f0, %r0" + + - + input: + bytes: [ 0xb3, 0xc1, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldgr %f0, %r15" + + - + input: + bytes: [ 0xb3, 0xc1, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldgr %f15, %r0" + + - + input: + bytes: [ 0xb3, 0xc1, 0x00, 0x79 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldgr %f7, %r9" + + - + input: + bytes: [ 0xb3, 0xc1, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldgr %f15, %r15" + + - + input: + bytes: [ 0x28, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldr %f0, %f9" + + - + input: + bytes: [ 0x28, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldr %f0, %f15" + + - + input: + bytes: [ 0x28, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldr %f15, %f0" + + - + input: + bytes: [ 0x28, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldr %f15, %f9" + + - + input: + bytes: [ 0xb3, 0x45, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxbr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x45, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxbr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x45, 0x00, 0x8c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxbr %f8, %f12" + + - + input: + bytes: [ 0xb3, 0x45, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxbr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0x45, 0x00, 0xdd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxbr %f13, %f13" + + - + input: + bytes: [ 0xb3, 0x45, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxbra %f0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x45, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxbra %f0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0x45, 0x01, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxbra %f0, 0, %f13, 1" + + - + input: + bytes: [ 0xb3, 0x45, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxbra %f0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x45, 0x59, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxbra %f4, 5, %f8, 9" + + - + input: + bytes: [ 0xb3, 0x45, 0x01, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxbra %f13, 0, %f0, 1" + + - + input: + bytes: [ 0x25, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxr %f0, %f0" + + - + input: + bytes: [ 0x25, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxr %f0, %f13" + + - + input: + bytes: [ 0x25, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxr %f7, %f8" + + - + input: + bytes: [ 0x25, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxr %f15, %f0" + + - + input: + bytes: [ 0x25, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxr %f15, %f13" + + - + input: + bytes: [ 0xb3, 0xdd, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxtr %f0, 0, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xdd, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxtr %f0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xdd, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxtr %f0, 0, %f13, 0" + + - + input: + bytes: [ 0xb3, 0xdd, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxtr %f0, 15, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xdd, 0x59, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxtr %f4, 5, %f8, 9" + + - + input: + bytes: [ 0xb3, 0xdd, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldxtr %f13, 0, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x80, 0x65 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldy %f0, -524288" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0xff, 0x65 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldy %f0, -1" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x65 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldy %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x01, 0x00, 0x65 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldy %f0, 1" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x7f, 0x65 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldy %f0, 524287" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x65 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldy %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x65 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldy %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x7f, 0x65 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldy %f0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x7f, 0x65 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldy %f0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x65 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ldy %f15, 0" + + - + input: + bytes: [ 0x78, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "le %f0, 0" + + - + input: + bytes: [ 0x78, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "le %f0, 4095" + + - + input: + bytes: [ 0x78, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "le %f0, 0(%r1)" + + - + input: + bytes: [ 0x78, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "le %f0, 0(%r15)" + + - + input: + bytes: [ 0x78, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "le %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x78, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "le %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x78, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "le %f15, 0" + + - + input: + bytes: [ 0xb3, 0x44, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledbr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x44, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledbr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x44, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledbr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x44, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledbr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x44, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledbr %f15, %f15" + + - + input: + bytes: [ 0xb3, 0x44, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledbra %f0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x44, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledbra %f0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0x44, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledbra %f0, 0, %f15, 1" + + - + input: + bytes: [ 0xb3, 0x44, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledbra %f0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x44, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledbra %f4, 5, %f6, 7" + + - + input: + bytes: [ 0xb3, 0x44, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledbra %f15, 0, %f0, 1" + + - + input: + bytes: [ 0x35, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledr %f0, %f0" + + - + input: + bytes: [ 0x35, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledr %f0, %f15" + + - + input: + bytes: [ 0x35, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledr %f7, %f8" + + - + input: + bytes: [ 0x35, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledr %f15, %f0" + + - + input: + bytes: [ 0x35, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledr %f15, %f15" + + - + input: + bytes: [ 0xb3, 0xd5, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledtr %f0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xd5, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledtr %f0, 0, %f15, 0" + + - + input: + bytes: [ 0xb3, 0xd5, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledtr %f0, 15, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xd5, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledtr %f4, 5, %f6, 7" + + - + input: + bytes: [ 0xb3, 0xd5, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ledtr %f15, 0, %f0, 0" + + - + input: + bytes: [ 0x38, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ler %f0, %f9" + + - + input: + bytes: [ 0x38, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ler %f0, %f15" + + - + input: + bytes: [ 0x38, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ler %f15, %f0" + + - + input: + bytes: [ 0x38, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ler %f15, %f9" + + - + input: + bytes: [ 0xb3, 0x46, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lexbr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x46, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lexbr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x46, 0x00, 0x8c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lexbr %f8, %f12" + + - + input: + bytes: [ 0xb3, 0x46, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lexbr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0x46, 0x00, 0xdd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lexbr %f13, %f13" + + - + input: + bytes: [ 0xb3, 0x46, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lexbra %f0, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x46, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lexbra %f0, 0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0x46, 0x01, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lexbra %f0, 0, %f13, 1" + + - + input: + bytes: [ 0xb3, 0x46, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lexbra %f0, 15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x46, 0x59, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lexbra %f4, 5, %f8, 9" + + - + input: + bytes: [ 0xb3, 0x46, 0x01, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lexbra %f13, 0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0x66, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lexr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x66, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lexr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x66, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lexr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x66, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lexr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x66, 0x00, 0xfd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lexr %f15, %f13" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x80, 0x64 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ley %f0, -524288" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0xff, 0x64 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ley %f0, -1" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x64 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ley %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x01, 0x00, 0x64 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ley %f0, 1" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x7f, 0x64 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ley %f0, 524287" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x64 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ley %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x64 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ley %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x7f, 0x64 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ley %f0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x7f, 0x64 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ley %f0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x64 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ley %f15, 0" + + - + input: + bytes: [ 0xb2, 0xbd, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfas 0" + + - + input: + bytes: [ 0xb2, 0xbd, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfas 0(%r1)" + + - + input: + bytes: [ 0xb2, 0xbd, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfas 0(%r15)" + + - + input: + bytes: [ 0xb2, 0xbd, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfas 4095" + + - + input: + bytes: [ 0xb2, 0xbd, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfas 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0xbd, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfas 4095(%r15)" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfh %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfh %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfh %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfh %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfh %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfh %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfh %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfh %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfh %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xca ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfh %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfhat %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfhat %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfhat %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfhat %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfhat %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfhat %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfhat %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfhat %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfhat %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfhat %r15, 0" + + - + input: + bytes: [ 0xb2, 0x9d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfpc 0" + + - + input: + bytes: [ 0xb2, 0x9d, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfpc 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x9d, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfpc 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x9d, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfpc 4095" + + - + input: + bytes: [ 0xb2, 0x9d, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfpc 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x9d, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lfpc 4095(%r15)" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lg %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgat %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgat %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgat %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgat %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgat %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgat %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgat %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgat %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgat %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgat %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgb %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgb %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgb %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgb %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgb %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgb %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgb %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgb %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgb %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x77 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgb %r15, 0" + + - + input: + bytes: [ 0xb9, 0x06, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgbr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x06, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgbr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x06, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgbr %r15, %r0" + + - + input: + bytes: [ 0xb3, 0xcd, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgdr %r0, %f0" + + - + input: + bytes: [ 0xb3, 0xcd, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgdr %r0, %f15" + + - + input: + bytes: [ 0xb3, 0xcd, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgdr %r15, %f0" + + - + input: + bytes: [ 0xb3, 0xcd, 0x00, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgdr %r8, %f8" + + - + input: + bytes: [ 0xb3, 0xcd, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgdr %r15, %f15" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgf %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgf %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgf %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgf %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgf %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgf %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgf %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgf %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgf %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgf %r15, 0" + + - + input: + bytes: [ 0xc0, 0x01, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgfi %r0, -2147483648" + + - + input: + bytes: [ 0xc0, 0x01, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgfi %r0, -1" + + - + input: + bytes: [ 0xc0, 0x01, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgfi %r0, 0" + + - + input: + bytes: [ 0xc0, 0x01, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgfi %r0, 1" + + - + input: + bytes: [ 0xc0, 0x01, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgfi %r0, 2147483647" + + - + input: + bytes: [ 0xc0, 0xf1, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgfi %r15, 0" + + - + input: + bytes: [ 0xb9, 0x14, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgfr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x14, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgfr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x14, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgfr %r15, %r0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x15 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgh %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x15 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgh %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x15 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgh %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x15 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgh %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x15 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgh %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x15 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgh %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x15 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgh %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x15 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgh %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x15 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgh %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x15 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgh %r15, 0" + + - + input: + bytes: [ 0xa7, 0x09, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lghi %r0, -32768" + + - + input: + bytes: [ 0xa7, 0x09, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lghi %r0, -1" + + - + input: + bytes: [ 0xa7, 0x09, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lghi %r0, 0" + + - + input: + bytes: [ 0xa7, 0x09, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lghi %r0, 1" + + - + input: + bytes: [ 0xa7, 0x09, 0x7f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lghi %r0, 32767" + + - + input: + bytes: [ 0xa7, 0xf9, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lghi %r15, 0" + + - + input: + bytes: [ 0xb9, 0x07, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lghr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x07, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lghr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x07, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lghr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x04, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgr %r0, %r9" + + - + input: + bytes: [ 0xb9, 0x04, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x04, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x04, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lgr %r15, %r9" + + - + input: + bytes: [ 0x48, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lh %r0, 0" + + - + input: + bytes: [ 0x48, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lh %r0, 4095" + + - + input: + bytes: [ 0x48, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lh %r0, 0(%r1)" + + - + input: + bytes: [ 0x48, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lh %r0, 0(%r15)" + + - + input: + bytes: [ 0x48, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lh %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x48, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lh %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x48, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lh %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhh %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhh %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhh %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhh %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhh %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhh %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhh %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhh %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhh %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc4 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhh %r15, 0" + + - + input: + bytes: [ 0xa7, 0x08, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhi %r0, -32768" + + - + input: + bytes: [ 0xa7, 0x08, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhi %r0, -1" + + - + input: + bytes: [ 0xa7, 0x08, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhi %r0, 0" + + - + input: + bytes: [ 0xa7, 0x08, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhi %r0, 1" + + - + input: + bytes: [ 0xa7, 0x08, 0x7f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhi %r0, 32767" + + - + input: + bytes: [ 0xa7, 0xf8, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhi %r15, 0" + + - + input: + bytes: [ 0xb9, 0x27, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x27, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x27, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhr %r15, %r0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhy %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhy %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhy %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhy %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhy %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhy %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhy %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhy %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhy %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lhy %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llc %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llc %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llc %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llc %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llc %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llc %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llc %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llc %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llc %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x94 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llc %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llch %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llch %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llch %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llch %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llch %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llch %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llch %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llch %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llch %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llch %r15, 0" + + - + input: + bytes: [ 0xb9, 0x94, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llcr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x94, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llcr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x94, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llcr %r15, %r0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgc %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgc %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgc %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgc %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgc %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgc %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgc %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgc %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgc %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgc %r15, 0" + + - + input: + bytes: [ 0xb9, 0x84, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgcr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x84, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgcr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x84, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgcr %r15, %r0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x16 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgf %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x16 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgf %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x16 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgf %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x16 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgf %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x16 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgf %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x16 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgf %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x16 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgf %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x16 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgf %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x16 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgf %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x16 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgf %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x9d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfat %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x9d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfat %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x9d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfat %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x9d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfat %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x9d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfat %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x9d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfat %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x9d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfat %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x9d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfat %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x9d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfat %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x9d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfat %r15, 0" + + - + input: + bytes: [ 0xb9, 0x16, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x16, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x16, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgfr %r15, %r0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x91 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgh %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x91 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgh %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x91 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgh %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x91 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgh %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x91 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgh %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x91 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgh %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x91 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgh %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x91 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgh %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x91 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgh %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x91 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgh %r15, 0" + + - + input: + bytes: [ 0xb9, 0x85, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llghr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x85, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llghr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x85, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llghr %r15, %r0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x17 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgt %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x17 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgt %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x17 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgt %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x17 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgt %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x17 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgt %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x17 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgt %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x17 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgt %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x17 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgt %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x17 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgt %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x17 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgt %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x9c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgtat %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x9c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgtat %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x9c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgtat %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x9c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgtat %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x9c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgtat %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x9c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgtat %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x9c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgtat %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x9c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgtat %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x9c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgtat %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x9c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgtat %r15, 0" + + - + input: + bytes: [ 0xb9, 0x17, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgtr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x17, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgtr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x17, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llgtr %r15, %r0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llh %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llh %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llh %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llh %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llh %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llh %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llh %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llh %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llh %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x95 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llh %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llhh %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llhh %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llhh %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llhh %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llhh %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llhh %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llhh %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llhh %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llhh %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc6 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llhh %r15, 0" + + - + input: + bytes: [ 0xb9, 0x95, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llhr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x95, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llhr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x95, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llhr %r15, %r0" + + - + input: + bytes: [ 0xc0, 0x0e, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llihf %r0, 0" + + - + input: + bytes: [ 0xc0, 0x0e, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llihf %r0, 4294967295" + + - + input: + bytes: [ 0xc0, 0xfe, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llihf %r15, 0" + + - + input: + bytes: [ 0xa5, 0x0c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llihh %r0, 0" + + - + input: + bytes: [ 0xa5, 0x0c, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llihh %r0, 32768" + + - + input: + bytes: [ 0xa5, 0x0c, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llihh %r0, 65535" + + - + input: + bytes: [ 0xa5, 0xfc, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llihh %r15, 0" + + - + input: + bytes: [ 0xa5, 0x0d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llihl %r0, 0" + + - + input: + bytes: [ 0xa5, 0x0d, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llihl %r0, 32768" + + - + input: + bytes: [ 0xa5, 0x0d, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llihl %r0, 65535" + + - + input: + bytes: [ 0xa5, 0xfd, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llihl %r15, 0" + + - + input: + bytes: [ 0xc0, 0x0f, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llilf %r0, 0" + + - + input: + bytes: [ 0xc0, 0x0f, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llilf %r0, 4294967295" + + - + input: + bytes: [ 0xc0, 0xff, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llilf %r15, 0" + + - + input: + bytes: [ 0xa5, 0x0e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llilh %r0, 0" + + - + input: + bytes: [ 0xa5, 0x0e, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llilh %r0, 32768" + + - + input: + bytes: [ 0xa5, 0x0e, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llilh %r0, 65535" + + - + input: + bytes: [ 0xa5, 0xfe, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llilh %r15, 0" + + - + input: + bytes: [ 0xa5, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llill %r0, 0" + + - + input: + bytes: [ 0xa5, 0x0f, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llill %r0, 32768" + + - + input: + bytes: [ 0xa5, 0x0f, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llill %r0, 65535" + + - + input: + bytes: [ 0xa5, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "llill %r15, 0" + + - + input: + bytes: [ 0x98, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lm %r0, %r0, 0" + + - + input: + bytes: [ 0x98, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lm %r0, %r15, 0" + + - + input: + bytes: [ 0x98, 0xef, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lm %r14, %r15, 0" + + - + input: + bytes: [ 0x98, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lm %r15, %r15, 0" + + - + input: + bytes: [ 0x98, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lm %r0, %r0, 4095" + + - + input: + bytes: [ 0x98, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lm %r0, %r0, 1" + + - + input: + bytes: [ 0x98, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lm %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0x98, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lm %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0x98, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lm %r0, %r0, 4095(%r1)" + + - + input: + bytes: [ 0x98, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lm %r0, %r0, 4095(%r15)" + + - + input: + bytes: [ 0xef, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmd %r0, %r0, 0, 0" + + - + input: + bytes: [ 0xef, 0x24, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmd %r2, %r4, 0, 4095" + + - + input: + bytes: [ 0xef, 0x24, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmd %r2, %r4, 0, 0(%r1)" + + - + input: + bytes: [ 0xef, 0x24, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmd %r2, %r4, 0, 0(%r15)" + + - + input: + bytes: [ 0xef, 0x24, 0x10, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmd %r2, %r4, 0(%r1), 4095(%r15)" + + - + input: + bytes: [ 0xef, 0x24, 0x10, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmd %r2, %r4, 0(%r1), 0(%r15)" + + - + input: + bytes: [ 0xef, 0x24, 0x1f, 0xff, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmd %r2, %r4, 4095(%r1), 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmg %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmg %r14, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmg %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmg %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmh %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmh %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmh %r14, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmh %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmh %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmh %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmh %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmh %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmh %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmh %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmh %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmh %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmh %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmy %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmy %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmy %r14, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmy %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmy %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmy %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmy %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmy %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmy %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmy %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmy %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmy %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x98 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lmy %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xb3, 0x11, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lndbr %f0, %f9" + + - + input: + bytes: [ 0xb3, 0x11, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lndbr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x11, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lndbr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x11, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lndbr %f15, %f9" + + - + input: + bytes: [ 0x21, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lndr %f0, %f9" + + - + input: + bytes: [ 0x21, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lndr %f0, %f15" + + - + input: + bytes: [ 0x21, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lndr %f15, %f0" + + - + input: + bytes: [ 0x21, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lndr %f15, %f9" + + - + input: + bytes: [ 0xb3, 0x01, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lnebr %f0, %f9" + + - + input: + bytes: [ 0xb3, 0x01, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lnebr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x01, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lnebr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x01, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lnebr %f15, %f9" + + - + input: + bytes: [ 0x31, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lner %f0, %f9" + + - + input: + bytes: [ 0x31, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lner %f0, %f15" + + - + input: + bytes: [ 0x31, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lner %f15, %f0" + + - + input: + bytes: [ 0x31, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lner %f15, %f9" + + - + input: + bytes: [ 0xb9, 0x11, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lngfr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x11, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lngfr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x11, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lngfr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x11, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lngfr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lngr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x01, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lngr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x01, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lngr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x01, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lngr %r7, %r8" + + - + input: + bytes: [ 0x11, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lnr %r0, %r0" + + - + input: + bytes: [ 0x11, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lnr %r0, %r15" + + - + input: + bytes: [ 0x11, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lnr %r15, %r0" + + - + input: + bytes: [ 0x11, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lnr %r7, %r8" + + - + input: + bytes: [ 0xb3, 0x41, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lnxbr %f0, %f8" + + - + input: + bytes: [ 0xb3, 0x41, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lnxbr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x41, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lnxbr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0x41, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lnxbr %f13, %f9" + + - + input: + bytes: [ 0xb3, 0x61, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lnxr %f0, %f8" + + - + input: + bytes: [ 0xb3, 0x61, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lnxr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x61, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lnxr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0x61, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lnxr %f13, %f9" + + - + input: + bytes: [ 0xeb, 0x70, 0x88, 0xff, 0x01, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "loc %r7, 6399(%r8), 0" + + - + input: + bytes: [ 0xeb, 0x71, 0x88, 0xff, 0x01, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "loco %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x72, 0x88, 0xff, 0x01, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "loch %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x73, 0x88, 0xff, 0x01, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locnle %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x74, 0x88, 0xff, 0x01, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locl %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x75, 0x88, 0xff, 0x01, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locnhe %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x76, 0x88, 0xff, 0x01, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "loclh %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x77, 0x88, 0xff, 0x01, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locne %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x78, 0x88, 0xff, 0x01, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "loce %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x79, 0x88, 0xff, 0x01, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locnlh %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x7a, 0x88, 0xff, 0x01, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "loche %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x7b, 0x88, 0xff, 0x01, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locnl %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x7c, 0x88, 0xff, 0x01, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locle %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x7d, 0x88, 0xff, 0x01, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locnh %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x7e, 0x88, 0xff, 0x01, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locno %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x7f, 0x88, 0xff, 0x01, 0xf2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "loc %r7, 6399(%r8), 15" + + - + input: + bytes: [ 0xeb, 0x70, 0x88, 0xff, 0x01, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locg %r7, 6399(%r8), 0" + + - + input: + bytes: [ 0xeb, 0x71, 0x88, 0xff, 0x01, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgo %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x72, 0x88, 0xff, 0x01, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgh %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x73, 0x88, 0xff, 0x01, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgnle %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x74, 0x88, 0xff, 0x01, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgl %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x75, 0x88, 0xff, 0x01, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgnhe %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x76, 0x88, 0xff, 0x01, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locglh %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x77, 0x88, 0xff, 0x01, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgne %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x78, 0x88, 0xff, 0x01, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locge %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x79, 0x88, 0xff, 0x01, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgnlh %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x7a, 0x88, 0xff, 0x01, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locghe %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x7b, 0x88, 0xff, 0x01, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgnl %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x7c, 0x88, 0xff, 0x01, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgle %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x7d, 0x88, 0xff, 0x01, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgnh %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x7e, 0x88, 0xff, 0x01, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgno %r7, 6399(%r8)" + + - + input: + bytes: [ 0xeb, 0x7f, 0x88, 0xff, 0x01, 0xe2 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locg %r7, 6399(%r8), 15" + + - + input: + bytes: [ 0xb9, 0xf2, 0x00, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locr %r11, %r3, 0" + + - + input: + bytes: [ 0xb9, 0xf2, 0x10, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locro %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xf2, 0x20, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locrh %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xf2, 0x30, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locrnle %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xf2, 0x40, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locrl %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xf2, 0x50, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locrnhe %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xf2, 0x60, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locrlh %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xf2, 0x70, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locrne %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xf2, 0x80, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locre %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xf2, 0x90, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locrnlh %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xf2, 0xa0, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locrhe %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xf2, 0xb0, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locrnl %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xf2, 0xc0, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locrle %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xf2, 0xd0, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locrnh %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xf2, 0xe0, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locrno %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xf2, 0xf0, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locr %r11, %r3, 15" + + - + input: + bytes: [ 0xb9, 0xe2, 0x00, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgr %r11, %r3, 0" + + - + input: + bytes: [ 0xb9, 0xe2, 0x10, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgro %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe2, 0x20, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgrh %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe2, 0x30, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgrnle %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe2, 0x40, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgrl %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe2, 0x50, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgrnhe %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe2, 0x60, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgrlh %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe2, 0x70, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgrne %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe2, 0x80, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgre %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe2, 0x90, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgrnlh %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe2, 0xa0, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgrhe %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe2, 0xb0, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgrnl %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe2, 0xc0, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgrle %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe2, 0xd0, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgrnh %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe2, 0xe0, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgrno %r11, %r3" + + - + input: + bytes: [ 0xb9, 0xe2, 0xf0, 0xb3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "locgr %r11, %r3, 15" + + - + input: + bytes: [ 0xb2, 0x85, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpctl 0" + + - + input: + bytes: [ 0xb2, 0x85, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpctl 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x85, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpctl 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x85, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpctl 4095" + + - + input: + bytes: [ 0xb2, 0x85, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpctl 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x85, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpctl 4095(%r15)" + + - + input: + bytes: [ 0xc8, 0x04, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpd %r0, 0, 0" + + - + input: + bytes: [ 0xc8, 0x24, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpd %r2, 0, 4095" + + - + input: + bytes: [ 0xc8, 0x24, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpd %r2, 0, 0(%r1)" + + - + input: + bytes: [ 0xc8, 0x24, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpd %r2, 0, 0(%r15)" + + - + input: + bytes: [ 0xc8, 0x24, 0x10, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpd %r2, 0(%r1), 4095(%r15)" + + - + input: + bytes: [ 0xc8, 0x24, 0x10, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpd %r2, 0(%r1), 0(%r15)" + + - + input: + bytes: [ 0xc8, 0x24, 0x1f, 0xff, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpd %r2, 4095(%r1), 0(%r15)" + + - + input: + bytes: [ 0xb3, 0x10, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpdbr %f0, %f9" + + - + input: + bytes: [ 0xb3, 0x10, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpdbr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x10, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpdbr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x10, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpdbr %f15, %f9" + + - + input: + bytes: [ 0xc8, 0x05, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpdg %r0, 0, 0" + + - + input: + bytes: [ 0xc8, 0x25, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpdg %r2, 0, 4095" + + - + input: + bytes: [ 0xc8, 0x25, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpdg %r2, 0, 0(%r1)" + + - + input: + bytes: [ 0xc8, 0x25, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpdg %r2, 0, 0(%r15)" + + - + input: + bytes: [ 0xc8, 0x25, 0x10, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpdg %r2, 0(%r1), 4095(%r15)" + + - + input: + bytes: [ 0xc8, 0x25, 0x10, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpdg %r2, 0(%r1), 0(%r15)" + + - + input: + bytes: [ 0xc8, 0x25, 0x1f, 0xff, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpdg %r2, 4095(%r1), 0(%r15)" + + - + input: + bytes: [ 0x20, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpdr %f0, %f9" + + - + input: + bytes: [ 0x20, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpdr %f0, %f15" + + - + input: + bytes: [ 0x20, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpdr %f15, %f0" + + - + input: + bytes: [ 0x20, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpdr %f15, %f9" + + - + input: + bytes: [ 0xb3, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpebr %f0, %f9" + + - + input: + bytes: [ 0xb3, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpebr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x00, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpebr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x00, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpebr %f15, %f9" + + - + input: + bytes: [ 0x30, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lper %f0, %f9" + + - + input: + bytes: [ 0x30, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lper %f0, %f15" + + - + input: + bytes: [ 0x30, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lper %f15, %f0" + + - + input: + bytes: [ 0x30, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lper %f15, %f9" + + - + input: + bytes: [ 0xb9, 0x10, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpgfr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x10, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpgfr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x10, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpgfr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x10, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpgfr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpgr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpgr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x00, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpgr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x00, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpgr %r7, %r8" + + - + input: + bytes: [ 0xb2, 0x80, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpp 0" + + - + input: + bytes: [ 0xb2, 0x80, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpp 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x80, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpp 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x80, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpp 4095" + + - + input: + bytes: [ 0xb2, 0x80, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpp 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x80, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpp 4095(%r15)" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpq %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpq %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpq %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpq %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpq %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpq %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpq %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpq %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpq %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x8f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpq %r14, 0" + + - + input: + bytes: [ 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpr %r0, %r0" + + - + input: + bytes: [ 0x10, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpr %r0, %r15" + + - + input: + bytes: [ 0x10, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpr %r15, %r0" + + - + input: + bytes: [ 0x10, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpr %r7, %r8" + + - + input: + bytes: [ 0x82, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpsw 0" + + - + input: + bytes: [ 0x82, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpsw 0(%r1)" + + - + input: + bytes: [ 0x82, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpsw 0(%r15)" + + - + input: + bytes: [ 0x82, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpsw 4095" + + - + input: + bytes: [ 0x82, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpsw 4095(%r1)" + + - + input: + bytes: [ 0x82, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpsw 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0xb2, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpswe 0" + + - + input: + bytes: [ 0xb2, 0xb2, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpswe 0(%r1)" + + - + input: + bytes: [ 0xb2, 0xb2, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpswe 0(%r15)" + + - + input: + bytes: [ 0xb2, 0xb2, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpswe 4095" + + - + input: + bytes: [ 0xb2, 0xb2, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpswe 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0xb2, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpswe 4095(%r15)" + + - + input: + bytes: [ 0xb9, 0xaa, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lptea %r0, %r0, %r0, 0" + + - + input: + bytes: [ 0xb9, 0xaa, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lptea %r0, %r0, %r0, 15" + + - + input: + bytes: [ 0xb9, 0xaa, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lptea %r0, %r0, %r15, 0" + + - + input: + bytes: [ 0xb9, 0xaa, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lptea %r0, %r15, %r0, 0" + + - + input: + bytes: [ 0xb9, 0xaa, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lptea %r4, %r5, %r6, 7" + + - + input: + bytes: [ 0xb9, 0xaa, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lptea %r15, %r0, %r0, 0" + + - + input: + bytes: [ 0xb3, 0x40, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpxbr %f0, %f8" + + - + input: + bytes: [ 0xb3, 0x40, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpxbr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x40, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpxbr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0x40, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpxbr %f13, %f9" + + - + input: + bytes: [ 0xb3, 0x60, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpxr %f0, %f8" + + - + input: + bytes: [ 0xb3, 0x60, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpxr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x60, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpxr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0x60, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lpxr %f13, %f9" + + - + input: + bytes: [ 0x18, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lr %r0, %r9" + + - + input: + bytes: [ 0x18, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lr %r0, %r15" + + - + input: + bytes: [ 0x18, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lr %r15, %r0" + + - + input: + bytes: [ 0x18, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lr %r15, %r9" + + - + input: + bytes: [ 0xb1, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lra %r0, 0" + + - + input: + bytes: [ 0xb1, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lra %r0, 4095" + + - + input: + bytes: [ 0xb1, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lra %r0, 0(%r1)" + + - + input: + bytes: [ 0xb1, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lra %r0, 0(%r15)" + + - + input: + bytes: [ 0xb1, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lra %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xb1, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lra %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xb1, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lra %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrag %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrag %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrag %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrag %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrag %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrag %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrag %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrag %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrag %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrag %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x13 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lray %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x13 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lray %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x13 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lray %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x13 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lray %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x13 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lray %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x13 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lray %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x13 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lray %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x13 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lray %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x13 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lray %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x13 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lray %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrv %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrv %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrv %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrv %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrv %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrv %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrv %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrv %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrv %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x1e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrv %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvg %r15, 0" + + - + input: + bytes: [ 0xb9, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvgr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x0f, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvgr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x0f, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvgr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x0f, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvgr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x0f, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvgr %r15, %r15" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvh %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvh %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvh %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvh %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvh %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvh %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvh %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvh %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvh %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x1f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvh %r15, 0" + + - + input: + bytes: [ 0xb9, 0x1f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x1f, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x1f, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x1f, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x1f, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lrvr %r15, %r15" + + - + input: + bytes: [ 0xb2, 0x87, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lsctl 0" + + - + input: + bytes: [ 0xb2, 0x87, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lsctl 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x87, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lsctl 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x87, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lsctl 4095" + + - + input: + bytes: [ 0xb2, 0x87, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lsctl 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x87, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lsctl 4095(%r15)" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lt %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lt %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lt %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lt %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lt %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lt %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lt %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lt %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lt %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lt %r15, 0" + + - + input: + bytes: [ 0xb3, 0x12, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltdbr %f0, %f9" + + - + input: + bytes: [ 0xb3, 0x12, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltdbr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x12, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltdbr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x12, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltdbr %f15, %f9" + + - + input: + bytes: [ 0x22, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltdr %f0, %f9" + + - + input: + bytes: [ 0x22, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltdr %f0, %f15" + + - + input: + bytes: [ 0x22, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltdr %f15, %f0" + + - + input: + bytes: [ 0x22, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltdr %f15, %f9" + + - + input: + bytes: [ 0xb3, 0xd6, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltdtr %f0, %f9" + + - + input: + bytes: [ 0xb3, 0xd6, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltdtr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0xd6, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltdtr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0xd6, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltdtr %f15, %f9" + + - + input: + bytes: [ 0xb3, 0x02, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltebr %f0, %f9" + + - + input: + bytes: [ 0xb3, 0x02, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltebr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x02, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltebr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x02, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltebr %f15, %f9" + + - + input: + bytes: [ 0x32, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lter %f0, %f9" + + - + input: + bytes: [ 0x32, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lter %f0, %f15" + + - + input: + bytes: [ 0x32, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lter %f15, %f0" + + - + input: + bytes: [ 0x32, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lter %f15, %f9" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltg %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x32 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltgf %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x32 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltgf %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x32 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltgf %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x32 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltgf %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x32 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltgf %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x32 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltgf %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x32 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltgf %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x32 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltgf %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x32 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltgf %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x32 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltgf %r15, 0" + + - + input: + bytes: [ 0xb9, 0x12, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltgfr %r0, %r9" + + - + input: + bytes: [ 0xb9, 0x12, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltgfr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x12, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltgfr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x12, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltgfr %r15, %r9" + + - + input: + bytes: [ 0xb9, 0x02, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltgr %r0, %r9" + + - + input: + bytes: [ 0xb9, 0x02, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltgr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x02, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltgr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x02, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltgr %r15, %r9" + + - + input: + bytes: [ 0x12, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltr %r0, %r9" + + - + input: + bytes: [ 0x12, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltr %r0, %r15" + + - + input: + bytes: [ 0x12, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltr %r15, %r0" + + - + input: + bytes: [ 0x12, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltr %r15, %r9" + + - + input: + bytes: [ 0xb3, 0x42, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltxbr %f0, %f9" + + - + input: + bytes: [ 0xb3, 0x42, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltxbr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x42, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltxbr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0x42, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltxbr %f13, %f9" + + - + input: + bytes: [ 0xb3, 0x62, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltxr %f0, %f9" + + - + input: + bytes: [ 0xb3, 0x62, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltxr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x62, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltxr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0x62, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltxr %f13, %f9" + + - + input: + bytes: [ 0xb3, 0xde, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltxtr %f0, %f9" + + - + input: + bytes: [ 0xb3, 0xde, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltxtr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0xde, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltxtr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0xde, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ltxtr %f13, %f9" + + - + input: + bytes: [ 0xb2, 0x4b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lura %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x4b, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lura %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x4b, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lura %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x4b, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lura %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x05, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lurag %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x05, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lurag %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x05, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lurag %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x05, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lurag %r7, %r8" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxd %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxd %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxd %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxd %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxd %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xd0, 0x00, 0x00, 0x00, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxd %f13, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxdb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxdb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxdb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxdb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxdb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxdb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xd0, 0x00, 0x00, 0x00, 0x05 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxdb %f13, 0" + + - + input: + bytes: [ 0xb3, 0x05, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxdbr %f0, %f8" + + - + input: + bytes: [ 0xb3, 0x05, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxdbr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x05, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxdbr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0x05, 0x00, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxdbr %f13, %f15" + + - + input: + bytes: [ 0xb3, 0x25, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxdr %f0, %f8" + + - + input: + bytes: [ 0xb3, 0x25, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxdr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x25, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxdr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0x25, 0x00, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxdr %f13, %f15" + + - + input: + bytes: [ 0xb3, 0xdc, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxdtr %f0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xdc, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxdtr %f0, %f15, 0" + + - + input: + bytes: [ 0xb3, 0xdc, 0x09, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxdtr %f5, %f8, 9" + + - + input: + bytes: [ 0xb3, 0xdc, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxdtr %f13, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxe %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxe %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxe %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxe %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxe %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xd0, 0x00, 0x00, 0x00, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxe %f13, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxeb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxeb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxeb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxeb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxeb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxeb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xd0, 0x00, 0x00, 0x00, 0x06 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxeb %f13, 0" + + - + input: + bytes: [ 0xb3, 0x06, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxebr %f0, %f8" + + - + input: + bytes: [ 0xb3, 0x06, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxebr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x06, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxebr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0x06, 0x00, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxebr %f13, %f15" + + - + input: + bytes: [ 0xb3, 0x26, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxer %f0, %f8" + + - + input: + bytes: [ 0xb3, 0x26, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxer %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x26, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxer %f13, %f0" + + - + input: + bytes: [ 0xb3, 0x26, 0x00, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxer %f13, %f15" + + - + input: + bytes: [ 0xb3, 0x65, 0x00, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxr %f0, %f8" + + - + input: + bytes: [ 0xb3, 0x65, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x65, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0x65, 0x00, 0xd9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lxr %f13, %f9" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ly %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ly %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ly %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ly %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ly %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ly %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ly %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ly %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ly %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ly %r15, 0" + + - + input: + bytes: [ 0xb3, 0x75, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzdr %f0" + + - + input: + bytes: [ 0xb3, 0x75, 0x00, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzdr %f7" + + - + input: + bytes: [ 0xb3, 0x75, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzdr %f15" + + - + input: + bytes: [ 0xb3, 0x74, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzer %f0" + + - + input: + bytes: [ 0xb3, 0x74, 0x00, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzer %f7" + + - + input: + bytes: [ 0xb3, 0x74, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzer %f15" + + - + input: + bytes: [ 0xb3, 0x76, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzxr %f0" + + - + input: + bytes: [ 0xb3, 0x76, 0x00, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzxr %f8" + + - + input: + bytes: [ 0xb3, 0x76, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "lzxr %f13" + + - + input: + bytes: [ 0x5c, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "m %r0, 0" + + - + input: + bytes: [ 0x5c, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "m %r0, 4095" + + - + input: + bytes: [ 0x5c, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "m %r0, 0(%r1)" + + - + input: + bytes: [ 0x5c, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "m %r0, 0(%r15)" + + - + input: + bytes: [ 0x5c, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "m %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x5c, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "m %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x5c, 0xe0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "m %r14, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mad %f0, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mad %f0, %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mad %f0, %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mad %f0, %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mad %f0, %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mad %f0, %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mad %f0, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mad %f15, %f0, 0" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mad %f15, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madb %f0, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madb %f0, %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madb %f0, %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madb %f0, %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madb %f0, %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madb %f0, %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madb %f0, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x1e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madb %f15, %f0, 0" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x1e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madb %f15, %f15, 0" + + - + input: + bytes: [ 0xb3, 0x1e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madbr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x1e, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madbr %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x1e, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madbr %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x1e, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madbr %f15, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x1e, 0x70, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madbr %f7, %f8, %f9" + + - + input: + bytes: [ 0xb3, 0x1e, 0xf0, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madbr %f15, %f15, %f15" + + - + input: + bytes: [ 0xb3, 0x3e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x3e, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madr %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x3e, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madr %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x3e, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madr %f15, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x3e, 0x70, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madr %f7, %f8, %f9" + + - + input: + bytes: [ 0xb3, 0x3e, 0xf0, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "madr %f15, %f15, %f15" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mae %f0, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mae %f0, %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mae %f0, %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mae %f0, %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mae %f0, %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mae %f0, %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mae %f0, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mae %f15, %f0, 0" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x2e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mae %f15, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maeb %f0, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maeb %f0, %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maeb %f0, %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maeb %f0, %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maeb %f0, %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maeb %f0, %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maeb %f0, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maeb %f15, %f0, 0" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maeb %f15, %f15, 0" + + - + input: + bytes: [ 0xb3, 0x0e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maebr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x0e, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maebr %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x0e, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maebr %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x0e, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maebr %f15, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x0e, 0x70, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maebr %f7, %f8, %f9" + + - + input: + bytes: [ 0xb3, 0x0e, 0xf0, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maebr %f15, %f15, %f15" + + - + input: + bytes: [ 0xb3, 0x2e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maer %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x2e, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maer %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x2e, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maer %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x2e, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maer %f15, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x2e, 0x70, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maer %f7, %f8, %f9" + + - + input: + bytes: [ 0xb3, 0x2e, 0xf0, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maer %f15, %f15, %f15" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "may %f0, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "may %f0, %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "may %f0, %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "may %f0, %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "may %f0, %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "may %f0, %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "may %f0, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xd0, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "may %f13, %f0, 0" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xd0, 0x3a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "may %f13, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayh %f0, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayh %f0, %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayh %f0, %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayh %f0, %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayh %f0, %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayh %f0, %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayh %f0, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayh %f15, %f0, 0" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x3c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayh %f15, %f15, 0" + + - + input: + bytes: [ 0xb3, 0x3c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayhr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x3c, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayhr %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x3c, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayhr %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x3c, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayhr %f15, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x3c, 0x70, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayhr %f7, %f8, %f9" + + - + input: + bytes: [ 0xb3, 0x3c, 0xf0, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayhr %f15, %f15, %f15" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayl %f0, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayl %f0, %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayl %f0, %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayl %f0, %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayl %f0, %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayl %f0, %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayl %f0, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayl %f15, %f0, 0" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x38 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayl %f15, %f15, 0" + + - + input: + bytes: [ 0xb3, 0x38, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maylr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x38, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maylr %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x38, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maylr %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x38, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maylr %f15, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x38, 0x70, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maylr %f7, %f8, %f9" + + - + input: + bytes: [ 0xb3, 0x38, 0xf0, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "maylr %f15, %f15, %f15" + + - + input: + bytes: [ 0xb3, 0x3a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x3a, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayr %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x3a, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayr %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x3a, 0xd0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayr %f13, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x3a, 0x50, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayr %f5, %f8, %f9" + + - + input: + bytes: [ 0xb3, 0x3a, 0xd0, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mayr %f13, %f15, %f15" + + - + input: + bytes: [ 0xaf, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mc 0, 0" + + - + input: + bytes: [ 0xaf, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mc 4095, 0" + + - + input: + bytes: [ 0xaf, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mc 0, 255" + + - + input: + bytes: [ 0xaf, 0x2a, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mc 0(%r1), 42" + + - + input: + bytes: [ 0xaf, 0x2a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mc 0(%r15), 42" + + - + input: + bytes: [ 0xaf, 0x2a, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mc 4095(%r1), 42" + + - + input: + bytes: [ 0xaf, 0x2a, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mc 4095(%r15), 42" + + - + input: + bytes: [ 0x6c, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "md %f0, 0" + + - + input: + bytes: [ 0x6c, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "md %f0, 4095" + + - + input: + bytes: [ 0x6c, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "md %f0, 0(%r1)" + + - + input: + bytes: [ 0x6c, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "md %f0, 0(%r15)" + + - + input: + bytes: [ 0x6c, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "md %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x6c, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "md %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x6c, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "md %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdb %f15, 0" + + - + input: + bytes: [ 0xb3, 0x1c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdbr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x1c, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdbr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x1c, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdbr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x1c, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdbr %f15, %f0" + + - + input: + bytes: [ 0x7c, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mde %f0, 0" + + - + input: + bytes: [ 0x7c, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mde %f0, 4095" + + - + input: + bytes: [ 0x7c, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mde %f0, 0(%r1)" + + - + input: + bytes: [ 0x7c, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mde %f0, 0(%r15)" + + - + input: + bytes: [ 0x7c, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mde %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x7c, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mde %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x7c, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mde %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdeb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdeb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdeb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdeb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdeb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdeb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdeb %f15, 0" + + - + input: + bytes: [ 0xb3, 0x0c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdebr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x0c, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdebr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x0c, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdebr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x0c, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdebr %f15, %f0" + + - + input: + bytes: [ 0x3c, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mder %f0, %f0" + + - + input: + bytes: [ 0x3c, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mder %f0, %f15" + + - + input: + bytes: [ 0x3c, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mder %f7, %f8" + + - + input: + bytes: [ 0x3c, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mder %f15, %f0" + + - + input: + bytes: [ 0x2c, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdr %f0, %f0" + + - + input: + bytes: [ 0x2c, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdr %f0, %f15" + + - + input: + bytes: [ 0x2c, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdr %f7, %f8" + + - + input: + bytes: [ 0x2c, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0xd0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdtr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xd0, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdtr %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0xd0, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdtr %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0xd0, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdtr %f15, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xd0, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdtr %f7, %f8, %f9" + + - + input: + bytes: [ 0xb3, 0xd0, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdtra %f0, %f0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xd0, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdtra %f0, %f0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xd0, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdtra %f0, %f0, %f15, 1" + + - + input: + bytes: [ 0xb3, 0xd0, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdtra %f0, %f15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xd0, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdtra %f15, %f0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xd0, 0x9a, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mdtra %f7, %f8, %f9, 10" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x37 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mee %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x37 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mee %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x37 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mee %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x37 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mee %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x37 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mee %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x37 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mee %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x37 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mee %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x17 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "meeb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x17 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "meeb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x17 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "meeb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x17 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "meeb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x17 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "meeb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x17 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "meeb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x17 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "meeb %f15, 0" + + - + input: + bytes: [ 0xb3, 0x17, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "meebr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x17, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "meebr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x17, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "meebr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x17, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "meebr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x37, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "meer %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x37, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "meer %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x37, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "meer %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x37, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "meer %f15, %f0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfy %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfy %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfy %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfy %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfy %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfy %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfy %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfy %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfy %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x5c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mfy %r14, 0" + + - + input: + bytes: [ 0xa7, 0x0d, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mghi %r0, -32768" + + - + input: + bytes: [ 0xa7, 0x0d, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mghi %r0, -1" + + - + input: + bytes: [ 0xa7, 0x0d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mghi %r0, 0" + + - + input: + bytes: [ 0xa7, 0x0d, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mghi %r0, 1" + + - + input: + bytes: [ 0xa7, 0x0d, 0x7f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mghi %r0, 32767" + + - + input: + bytes: [ 0xa7, 0xfd, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mghi %r15, 0" + + - + input: + bytes: [ 0x4c, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mh %r0, 0" + + - + input: + bytes: [ 0x4c, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mh %r0, 4095" + + - + input: + bytes: [ 0x4c, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mh %r0, 0(%r1)" + + - + input: + bytes: [ 0x4c, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mh %r0, 0(%r15)" + + - + input: + bytes: [ 0x4c, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mh %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x4c, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mh %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x4c, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mh %r15, 0" + + - + input: + bytes: [ 0xa7, 0x0c, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mhi %r0, -32768" + + - + input: + bytes: [ 0xa7, 0x0c, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mhi %r0, -1" + + - + input: + bytes: [ 0xa7, 0x0c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mhi %r0, 0" + + - + input: + bytes: [ 0xa7, 0x0c, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mhi %r0, 1" + + - + input: + bytes: [ 0xa7, 0x0c, 0x7f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mhi %r0, 32767" + + - + input: + bytes: [ 0xa7, 0xfc, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mhi %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x7c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mhy %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x7c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mhy %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x7c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mhy %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x7c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mhy %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x7c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mhy %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x7c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mhy %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x7c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mhy %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x7c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mhy %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x7c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mhy %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x7c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mhy %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ml %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ml %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ml %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ml %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ml %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ml %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ml %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ml %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ml %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x96 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ml %r14, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x86 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mlg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x86 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mlg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x86 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mlg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x86 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mlg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x86 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mlg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x86 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mlg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x86 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mlg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x86 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mlg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x86 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mlg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x86 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mlg %r14, 0" + + - + input: + bytes: [ 0xb9, 0x86, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mlgr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x86, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mlgr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x86, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mlgr %r14, %r0" + + - + input: + bytes: [ 0xb9, 0x86, 0x00, 0x69 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mlgr %r6, %r9" + + - + input: + bytes: [ 0xb9, 0x96, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mlr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x96, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mlr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x96, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mlr %r14, %r0" + + - + input: + bytes: [ 0xb9, 0x96, 0x00, 0x69 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mlr %r6, %r9" + + - + input: + bytes: [ 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mp 0(1), 0(1)" + + - + input: + bytes: [ 0xfc, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mp 0(1), 0(1,%r1)" + + - + input: + bytes: [ 0xfc, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mp 0(1), 0(1,%r15)" + + - + input: + bytes: [ 0xfc, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mp 0(1), 4095(1)" + + - + input: + bytes: [ 0xfc, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mp 0(1), 4095(1,%r1)" + + - + input: + bytes: [ 0xfc, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mp 0(1), 4095(1,%r15)" + + - + input: + bytes: [ 0xfc, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mp 0(1,%r1), 0(1)" + + - + input: + bytes: [ 0xfc, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mp 0(1,%r15), 0(1)" + + - + input: + bytes: [ 0xfc, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mp 4095(1,%r1), 0(1)" + + - + input: + bytes: [ 0xfc, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mp 4095(1,%r15), 0(1)" + + - + input: + bytes: [ 0xfc, 0xf0, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mp 0(16,%r1), 0(1)" + + - + input: + bytes: [ 0xfc, 0xf0, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mp 0(16,%r15), 0(1)" + + - + input: + bytes: [ 0xfc, 0x0f, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mp 0(1), 0(16,%r1)" + + - + input: + bytes: [ 0xfc, 0x0f, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mp 0(1), 0(16,%r15)" + + - + input: + bytes: [ 0x1c, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mr %r0, %r0" + + - + input: + bytes: [ 0x1c, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mr %r0, %r15" + + - + input: + bytes: [ 0x1c, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mr %r14, %r0" + + - + input: + bytes: [ 0x1c, 0x69 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mr %r6, %r9" + + - + input: + bytes: [ 0x71, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ms %r0, 0" + + - + input: + bytes: [ 0x71, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ms %r0, 4095" + + - + input: + bytes: [ 0x71, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ms %r0, 0(%r1)" + + - + input: + bytes: [ 0x71, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ms %r0, 0(%r15)" + + - + input: + bytes: [ 0x71, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ms %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x71, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ms %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x71, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ms %r15, 0" + + - + input: + bytes: [ 0xb2, 0x32, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msch 0" + + - + input: + bytes: [ 0xb2, 0x32, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msch 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x32, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msch 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x32, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msch 4095" + + - + input: + bytes: [ 0xb2, 0x32, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msch 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x32, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msch 4095(%r15)" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msd %f0, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msd %f0, %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msd %f0, %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msd %f0, %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msd %f0, %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msd %f0, %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msd %f0, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msd %f15, %f0, 0" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msd %f15, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdb %f0, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdb %f0, %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdb %f0, %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdb %f0, %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdb %f0, %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdb %f0, %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdb %f0, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x1f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdb %f15, %f0, 0" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x1f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdb %f15, %f15, 0" + + - + input: + bytes: [ 0xb3, 0x1f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdbr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x1f, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdbr %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x1f, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdbr %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x1f, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdbr %f15, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x1f, 0x70, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdbr %f7, %f8, %f9" + + - + input: + bytes: [ 0xb3, 0x1f, 0xf0, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdbr %f15, %f15, %f15" + + - + input: + bytes: [ 0xb3, 0x3f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x3f, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdr %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x3f, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdr %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x3f, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdr %f15, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x3f, 0x70, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdr %f7, %f8, %f9" + + - + input: + bytes: [ 0xb3, 0x3f, 0xf0, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msdr %f15, %f15, %f15" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mse %f0, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mse %f0, %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mse %f0, %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mse %f0, %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mse %f0, %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mse %f0, %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mse %f0, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mse %f15, %f0, 0" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mse %f15, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mseb %f0, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mseb %f0, %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mseb %f0, %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mseb %f0, %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mseb %f0, %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mseb %f0, %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mseb %f0, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mseb %f15, %f0, 0" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mseb %f15, %f15, 0" + + - + input: + bytes: [ 0xb3, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msebr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x0f, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msebr %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x0f, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msebr %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x0f, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msebr %f15, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x0f, 0x70, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msebr %f7, %f8, %f9" + + - + input: + bytes: [ 0xb3, 0x0f, 0xf0, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msebr %f15, %f15, %f15" + + - + input: + bytes: [ 0xb3, 0x2f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mser %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x2f, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mser %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x2f, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mser %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x2f, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mser %f15, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x2f, 0x70, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mser %f7, %f8, %f9" + + - + input: + bytes: [ 0xb3, 0x2f, 0xf0, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mser %f15, %f15, %f15" + + - + input: + bytes: [ 0xc2, 0x01, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msfi %r0, -2147483648" + + - + input: + bytes: [ 0xc2, 0x01, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msfi %r0, -1" + + - + input: + bytes: [ 0xc2, 0x01, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msfi %r0, 0" + + - + input: + bytes: [ 0xc2, 0x01, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msfi %r0, 1" + + - + input: + bytes: [ 0xc2, 0x01, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msfi %r0, 2147483647" + + - + input: + bytes: [ 0xc2, 0xf1, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msfi %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msg %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgf %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgf %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgf %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgf %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgf %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgf %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgf %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgf %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgf %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgf %r15, 0" + + - + input: + bytes: [ 0xc2, 0x00, 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgfi %r0, -2147483648" + + - + input: + bytes: [ 0xc2, 0x00, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgfi %r0, -1" + + - + input: + bytes: [ 0xc2, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgfi %r0, 0" + + - + input: + bytes: [ 0xc2, 0x00, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgfi %r0, 1" + + - + input: + bytes: [ 0xc2, 0x00, 0x7f, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgfi %r0, 2147483647" + + - + input: + bytes: [ 0xc2, 0xf0, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgfi %r15, 0" + + - + input: + bytes: [ 0xb9, 0x1c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgfr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x1c, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgfr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x1c, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgfr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x1c, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgfr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x0c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x0c, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x0c, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x0c, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msgr %r7, %r8" + + - + input: + bytes: [ 0xb2, 0x52, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msr %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x52, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msr %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x52, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msr %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x52, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msr %r7, %r8" + + - + input: + bytes: [ 0xb2, 0x47, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msta %r0" + + - + input: + bytes: [ 0xb2, 0x47, 0x00, 0x20 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msta %r2" + + - + input: + bytes: [ 0xb2, 0x47, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msta %r14" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msy %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msy %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msy %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msy %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msy %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msy %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msy %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msy %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msy %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "msy %r15, 0" + + - + input: + bytes: [ 0xd2, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvc 0(1), 0" + + - + input: + bytes: [ 0xd2, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvc 0(1), 0(%r1)" + + - + input: + bytes: [ 0xd2, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvc 0(1), 0(%r15)" + + - + input: + bytes: [ 0xd2, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvc 0(1), 4095" + + - + input: + bytes: [ 0xd2, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvc 0(1), 4095(%r1)" + + - + input: + bytes: [ 0xd2, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvc 0(1), 4095(%r15)" + + - + input: + bytes: [ 0xd2, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvc 0(1,%r1), 0" + + - + input: + bytes: [ 0xd2, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvc 0(1,%r15), 0" + + - + input: + bytes: [ 0xd2, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvc 4095(1,%r1), 0" + + - + input: + bytes: [ 0xd2, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvc 4095(1,%r15), 0" + + - + input: + bytes: [ 0xd2, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvc 0(256,%r1), 0" + + - + input: + bytes: [ 0xd2, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvc 0(256,%r15), 0" + + - + input: + bytes: [ 0xe5, 0x0f, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcdk 0, 0" + + - + input: + bytes: [ 0xe5, 0x0f, 0x10, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcdk 0(%r1), 0(%r2)" + + - + input: + bytes: [ 0xe5, 0x0f, 0x10, 0xa0, 0xf1, 0x40 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcdk 160(%r1), 320(%r15)" + + - + input: + bytes: [ 0xe5, 0x0f, 0x10, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcdk 0(%r1), 4095" + + - + input: + bytes: [ 0xe5, 0x0f, 0x10, 0x00, 0x2f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcdk 0(%r1), 4095(%r2)" + + - + input: + bytes: [ 0xe5, 0x0f, 0x10, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcdk 0(%r1), 4095(%r15)" + + - + input: + bytes: [ 0xe5, 0x0f, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcdk 0(%r1), 0" + + - + input: + bytes: [ 0xe5, 0x0f, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcdk 0(%r15), 0" + + - + input: + bytes: [ 0xe5, 0x0f, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcdk 4095(%r1), 0" + + - + input: + bytes: [ 0xe5, 0x0f, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcdk 4095(%r15), 0" + + - + input: + bytes: [ 0xe8, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcin 0(1), 0" + + - + input: + bytes: [ 0xe8, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcin 0(1), 0(%r1)" + + - + input: + bytes: [ 0xe8, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcin 0(1), 0(%r15)" + + - + input: + bytes: [ 0xe8, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcin 0(1), 4095" + + - + input: + bytes: [ 0xe8, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcin 0(1), 4095(%r1)" + + - + input: + bytes: [ 0xe8, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcin 0(1), 4095(%r15)" + + - + input: + bytes: [ 0xe8, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcin 0(1,%r1), 0" + + - + input: + bytes: [ 0xe8, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcin 0(1,%r15), 0" + + - + input: + bytes: [ 0xe8, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcin 4095(1,%r1), 0" + + - + input: + bytes: [ 0xe8, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcin 4095(1,%r15), 0" + + - + input: + bytes: [ 0xe8, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcin 0(256,%r1), 0" + + - + input: + bytes: [ 0xe8, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcin 0(256,%r15), 0" + + - + input: + bytes: [ 0xd9, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvck 0(%r0), 0, %r0" + + - + input: + bytes: [ 0xd9, 0x02, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvck 0(%r0), 4095, %r2" + + - + input: + bytes: [ 0xd9, 0x02, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvck 0(%r0), 0(%r1), %r2" + + - + input: + bytes: [ 0xd9, 0x02, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvck 0(%r0), 0(%r15), %r2" + + - + input: + bytes: [ 0xd9, 0x02, 0x10, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvck 0(%r0,%r1), 4095(%r15), %r2" + + - + input: + bytes: [ 0xd9, 0x02, 0x10, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvck 0(%r0,%r1), 0(%r15), %r2" + + - + input: + bytes: [ 0xd9, 0xf2, 0x1f, 0xff, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvck 4095(%r15,%r1), 0(%r15), %r2" + + - + input: + bytes: [ 0x0e, 0x08 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcl %r0, %r8" + + - + input: + bytes: [ 0x0e, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcl %r0, %r14" + + - + input: + bytes: [ 0x0e, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcl %r14, %r0" + + - + input: + bytes: [ 0x0e, 0xe8 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcl %r14, %r8" + + - + input: + bytes: [ 0xa8, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcle %r0, %r0, 0" + + - + input: + bytes: [ 0xa8, 0x0e, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcle %r0, %r14, 4095" + + - + input: + bytes: [ 0xa8, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcle %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xa8, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcle %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xa8, 0x0e, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcle %r0, %r14, 4095(%r15)" + + - + input: + bytes: [ 0xa8, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcle %r0, %r0, 4095(%r1)" + + - + input: + bytes: [ 0xa8, 0xe0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcle %r14, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvclu %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvclu %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x0e, 0x00, 0x00, 0x00, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvclu %r0, %r14, 0" + + - + input: + bytes: [ 0xeb, 0x0e, 0x00, 0x01, 0x00, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvclu %r0, %r14, 1" + + - + input: + bytes: [ 0xeb, 0x08, 0x0f, 0xff, 0x7f, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvclu %r0, %r8, 524287" + + - + input: + bytes: [ 0xeb, 0x08, 0x10, 0x00, 0x00, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvclu %r0, %r8, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x04, 0xf0, 0x00, 0x00, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvclu %r0, %r4, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x04, 0xff, 0xff, 0x7f, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvclu %r0, %r4, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvclu %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0xe0, 0x00, 0x00, 0x00, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvclu %r14, %r0, 0" + + - + input: + bytes: [ 0xc8, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcos 0, 0, %r0" + + - + input: + bytes: [ 0xc8, 0x20, 0x10, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcos 0(%r1), 0(%r15), %r2" + + - + input: + bytes: [ 0xc8, 0x20, 0x10, 0x01, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcos 1(%r1), 0(%r15), %r2" + + - + input: + bytes: [ 0xc8, 0x20, 0x1f, 0xff, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcos 4095(%r1), 0(%r15), %r2" + + - + input: + bytes: [ 0xc8, 0x20, 0x10, 0x00, 0xf0, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcos 0(%r1), 1(%r15), %r2" + + - + input: + bytes: [ 0xc8, 0x20, 0x10, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcos 0(%r1), 4095(%r15), %r2" + + - + input: + bytes: [ 0xda, 0x03, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcp 0(%r0), 0, %r3" + + - + input: + bytes: [ 0xda, 0x13, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcp 0(%r1), 0, %r3" + + - + input: + bytes: [ 0xda, 0x13, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcp 0(%r1), 0(%r1), %r3" + + - + input: + bytes: [ 0xda, 0x13, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcp 0(%r1), 0(%r15), %r3" + + - + input: + bytes: [ 0xda, 0x13, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcp 0(%r1), 4095, %r3" + + - + input: + bytes: [ 0xda, 0x13, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcp 0(%r1), 4095(%r1), %r3" + + - + input: + bytes: [ 0xda, 0x13, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcp 0(%r1), 4095(%r15), %r3" + + - + input: + bytes: [ 0xda, 0x23, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcp 0(%r2,%r1), 0, %r3" + + - + input: + bytes: [ 0xda, 0x23, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcp 0(%r2,%r15), 0, %r3" + + - + input: + bytes: [ 0xda, 0x23, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcp 4095(%r2,%r1), 0, %r3" + + - + input: + bytes: [ 0xda, 0x23, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcp 4095(%r2,%r15), 0, %r3" + + - + input: + bytes: [ 0xda, 0x23, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcp 0(%r2,%r1), 0, %r3" + + - + input: + bytes: [ 0xda, 0x23, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcp 0(%r2,%r15), 0, %r3" + + - + input: + bytes: [ 0xdb, 0x03, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcs 0(%r0), 0, %r3" + + - + input: + bytes: [ 0xdb, 0x13, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcs 0(%r1), 0, %r3" + + - + input: + bytes: [ 0xdb, 0x13, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcs 0(%r1), 0(%r1), %r3" + + - + input: + bytes: [ 0xdb, 0x13, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcs 0(%r1), 0(%r15), %r3" + + - + input: + bytes: [ 0xdb, 0x13, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcs 0(%r1), 4095, %r3" + + - + input: + bytes: [ 0xdb, 0x13, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcs 0(%r1), 4095(%r1), %r3" + + - + input: + bytes: [ 0xdb, 0x13, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcs 0(%r1), 4095(%r15), %r3" + + - + input: + bytes: [ 0xdb, 0x23, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcs 0(%r2,%r1), 0, %r3" + + - + input: + bytes: [ 0xdb, 0x23, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcs 0(%r2,%r15), 0, %r3" + + - + input: + bytes: [ 0xdb, 0x23, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcs 4095(%r2,%r1), 0, %r3" + + - + input: + bytes: [ 0xdb, 0x23, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcs 4095(%r2,%r15), 0, %r3" + + - + input: + bytes: [ 0xdb, 0x23, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcs 0(%r2,%r1), 0, %r3" + + - + input: + bytes: [ 0xdb, 0x23, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcs 0(%r2,%r15), 0, %r3" + + - + input: + bytes: [ 0xe5, 0x0e, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcsk 0, 0" + + - + input: + bytes: [ 0xe5, 0x0e, 0x10, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcsk 0(%r1), 0(%r2)" + + - + input: + bytes: [ 0xe5, 0x0e, 0x10, 0xa0, 0xf1, 0x40 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcsk 160(%r1), 320(%r15)" + + - + input: + bytes: [ 0xe5, 0x0e, 0x10, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcsk 0(%r1), 4095" + + - + input: + bytes: [ 0xe5, 0x0e, 0x10, 0x00, 0x2f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcsk 0(%r1), 4095(%r2)" + + - + input: + bytes: [ 0xe5, 0x0e, 0x10, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcsk 0(%r1), 4095(%r15)" + + - + input: + bytes: [ 0xe5, 0x0e, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcsk 0(%r1), 0" + + - + input: + bytes: [ 0xe5, 0x0e, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcsk 0(%r15), 0" + + - + input: + bytes: [ 0xe5, 0x0e, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcsk 4095(%r1), 0" + + - + input: + bytes: [ 0xe5, 0x0e, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvcsk 4095(%r15), 0" + + - + input: + bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvghi 0, 0" + + - + input: + bytes: [ 0xe5, 0x48, 0x0f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvghi 4095, 0" + + - + input: + bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvghi 0, -32768" + + - + input: + bytes: [ 0xe5, 0x48, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvghi 0, -1" + + - + input: + bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvghi 0, 0" + + - + input: + bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvghi 0, 1" + + - + input: + bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x7f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvghi 0, 32767" + + - + input: + bytes: [ 0xe5, 0x48, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvghi 0(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x48, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvghi 0(%r15), 42" + + - + input: + bytes: [ 0xe5, 0x48, 0x1f, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvghi 4095(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x48, 0xff, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvghi 4095(%r15), 42" + + - + input: + bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhhi 0, 0" + + - + input: + bytes: [ 0xe5, 0x44, 0x0f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhhi 4095, 0" + + - + input: + bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhhi 0, -32768" + + - + input: + bytes: [ 0xe5, 0x44, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhhi 0, -1" + + - + input: + bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhhi 0, 0" + + - + input: + bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhhi 0, 1" + + - + input: + bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x7f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhhi 0, 32767" + + - + input: + bytes: [ 0xe5, 0x44, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhhi 0(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x44, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhhi 0(%r15), 42" + + - + input: + bytes: [ 0xe5, 0x44, 0x1f, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhhi 4095(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x44, 0xff, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhhi 4095(%r15), 42" + + - + input: + bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhi 0, 0" + + - + input: + bytes: [ 0xe5, 0x4c, 0x0f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhi 4095, 0" + + - + input: + bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhi 0, -32768" + + - + input: + bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhi 0, -1" + + - + input: + bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhi 0, 0" + + - + input: + bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhi 0, 1" + + - + input: + bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x7f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhi 0, 32767" + + - + input: + bytes: [ 0xe5, 0x4c, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhi 0(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x4c, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhi 0(%r15), 42" + + - + input: + bytes: [ 0xe5, 0x4c, 0x1f, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhi 4095(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x4c, 0xff, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvhi 4095(%r15), 42" + + - + input: + bytes: [ 0x92, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvi 0, 0" + + - + input: + bytes: [ 0x92, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvi 4095, 0" + + - + input: + bytes: [ 0x92, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvi 0, 255" + + - + input: + bytes: [ 0x92, 0x2a, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvi 0(%r1), 42" + + - + input: + bytes: [ 0x92, 0x2a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvi 0(%r15), 42" + + - + input: + bytes: [ 0x92, 0x2a, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvi 4095(%r1), 42" + + - + input: + bytes: [ 0x92, 0x2a, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvi 4095(%r15), 42" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mviy -524288, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mviy -1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mviy 0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mviy 1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mviy 524287, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mviy 0, 255" + + - + input: + bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mviy 0(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mviy 0(%r15), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mviy 524287(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x52 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mviy 524287(%r15), 42" + + - + input: + bytes: [ 0xd1, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvn 0(1), 0" + + - + input: + bytes: [ 0xd1, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvn 0(1), 0(%r1)" + + - + input: + bytes: [ 0xd1, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvn 0(1), 0(%r15)" + + - + input: + bytes: [ 0xd1, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvn 0(1), 4095" + + - + input: + bytes: [ 0xd1, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvn 0(1), 4095(%r1)" + + - + input: + bytes: [ 0xd1, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvn 0(1), 4095(%r15)" + + - + input: + bytes: [ 0xd1, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvn 0(1,%r1), 0" + + - + input: + bytes: [ 0xd1, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvn 0(1,%r15), 0" + + - + input: + bytes: [ 0xd1, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvn 4095(1,%r1), 0" + + - + input: + bytes: [ 0xd1, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvn 4095(1,%r15), 0" + + - + input: + bytes: [ 0xd1, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvn 0(256,%r1), 0" + + - + input: + bytes: [ 0xd1, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvn 0(256,%r15), 0" + + - + input: + bytes: [ 0xf1, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvo 0(1), 0(1)" + + - + input: + bytes: [ 0xf1, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvo 0(1), 0(1,%r1)" + + - + input: + bytes: [ 0xf1, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvo 0(1), 0(1,%r15)" + + - + input: + bytes: [ 0xf1, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvo 0(1), 4095(1)" + + - + input: + bytes: [ 0xf1, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvo 0(1), 4095(1,%r1)" + + - + input: + bytes: [ 0xf1, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvo 0(1), 4095(1,%r15)" + + - + input: + bytes: [ 0xf1, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvo 0(1,%r1), 0(1)" + + - + input: + bytes: [ 0xf1, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvo 0(1,%r15), 0(1)" + + - + input: + bytes: [ 0xf1, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvo 4095(1,%r1), 0(1)" + + - + input: + bytes: [ 0xf1, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvo 4095(1,%r15), 0(1)" + + - + input: + bytes: [ 0xf1, 0xf0, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvo 0(16,%r1), 0(1)" + + - + input: + bytes: [ 0xf1, 0xf0, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvo 0(16,%r15), 0(1)" + + - + input: + bytes: [ 0xf1, 0x0f, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvo 0(1), 0(16,%r1)" + + - + input: + bytes: [ 0xf1, 0x0f, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvo 0(1), 0(16,%r15)" + + - + input: + bytes: [ 0xb2, 0x54, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvpg %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x54, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvpg %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x54, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvpg %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x54, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvpg %r7, %r8" + + - + input: + bytes: [ 0xb2, 0x55, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvst %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x55, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvst %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x55, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvst %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x55, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvst %r7, %r8" + + - + input: + bytes: [ 0xd3, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvz 0(1), 0" + + - + input: + bytes: [ 0xd3, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvz 0(1), 0(%r1)" + + - + input: + bytes: [ 0xd3, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvz 0(1), 0(%r15)" + + - + input: + bytes: [ 0xd3, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvz 0(1), 4095" + + - + input: + bytes: [ 0xd3, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvz 0(1), 4095(%r1)" + + - + input: + bytes: [ 0xd3, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvz 0(1), 4095(%r15)" + + - + input: + bytes: [ 0xd3, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvz 0(1,%r1), 0" + + - + input: + bytes: [ 0xd3, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvz 0(1,%r15), 0" + + - + input: + bytes: [ 0xd3, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvz 4095(1,%r1), 0" + + - + input: + bytes: [ 0xd3, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvz 4095(1,%r15), 0" + + - + input: + bytes: [ 0xd3, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvz 0(256,%r1), 0" + + - + input: + bytes: [ 0xd3, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mvz 0(256,%r15), 0" + + - + input: + bytes: [ 0xb3, 0x4c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxbr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x4c, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxbr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x4c, 0x00, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxbr %f8, %f5" + + - + input: + bytes: [ 0xb3, 0x4c, 0x00, 0xdd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxbr %f13, %f13" + + - + input: + bytes: [ 0x67, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxd %f0, 0" + + - + input: + bytes: [ 0x67, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxd %f0, 4095" + + - + input: + bytes: [ 0x67, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxd %f0, 0(%r1)" + + - + input: + bytes: [ 0x67, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxd %f0, 0(%r15)" + + - + input: + bytes: [ 0x67, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxd %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x67, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxd %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x67, 0xd0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxd %f13, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxdb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxdb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxdb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxdb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxdb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxdb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xd0, 0x00, 0x00, 0x00, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxdb %f13, 0" + + - + input: + bytes: [ 0xb3, 0x07, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxdbr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x07, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxdbr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x07, 0x00, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxdbr %f8, %f8" + + - + input: + bytes: [ 0xb3, 0x07, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxdbr %f13, %f0" + + - + input: + bytes: [ 0x27, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxdr %f0, %f0" + + - + input: + bytes: [ 0x27, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxdr %f0, %f15" + + - + input: + bytes: [ 0x27, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxdr %f8, %f8" + + - + input: + bytes: [ 0x27, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxdr %f13, %f0" + + - + input: + bytes: [ 0x26, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxr %f0, %f0" + + - + input: + bytes: [ 0x26, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxr %f0, %f13" + + - + input: + bytes: [ 0x26, 0x85 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxr %f8, %f5" + + - + input: + bytes: [ 0x26, 0xdd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxr %f13, %f13" + + - + input: + bytes: [ 0xb3, 0xd8, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxtr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xd8, 0xd0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxtr %f0, %f0, %f13" + + - + input: + bytes: [ 0xb3, 0xd8, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxtr %f0, %f13, %f0" + + - + input: + bytes: [ 0xb3, 0xd8, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxtr %f13, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xd8, 0x80, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxtr %f8, %f8, %f8" + + - + input: + bytes: [ 0xb3, 0xd8, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxtra %f0, %f0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xd8, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxtra %f0, %f0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xd8, 0xd1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxtra %f0, %f0, %f13, 1" + + - + input: + bytes: [ 0xb3, 0xd8, 0x01, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxtra %f0, %f13, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xd8, 0x01, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxtra %f13, %f0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xd8, 0x88, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mxtra %f8, %f8, %f8, 8" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "my %f0, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "my %f0, %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "my %f0, %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "my %f0, %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "my %f0, %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "my %f0, %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "my %f0, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xd0, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "my %f13, %f0, 0" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xd0, 0x3b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "my %f13, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x3d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myh %f0, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x3d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myh %f0, %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x3d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myh %f0, %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x3d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myh %f0, %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x3d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myh %f0, %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x3d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myh %f0, %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x3d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myh %f0, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x3d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myh %f15, %f0, 0" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x3d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myh %f15, %f15, 0" + + - + input: + bytes: [ 0xb3, 0x3d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myhr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x3d, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myhr %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x3d, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myhr %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x3d, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myhr %f15, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x3d, 0x70, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myhr %f7, %f8, %f9" + + - + input: + bytes: [ 0xb3, 0x3d, 0xf0, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myhr %f15, %f15, %f15" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x39 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myl %f0, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x39 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myl %f0, %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x39 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myl %f0, %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x39 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myl %f0, %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x39 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myl %f0, %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x39 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myl %f0, %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x39 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myl %f0, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x39 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myl %f15, %f0, 0" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x39 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myl %f15, %f15, 0" + + - + input: + bytes: [ 0xb3, 0x39, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mylr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x39, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mylr %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x39, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mylr %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x39, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mylr %f15, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x39, 0x70, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mylr %f7, %f8, %f9" + + - + input: + bytes: [ 0xb3, 0x39, 0xf0, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "mylr %f15, %f15, %f15" + + - + input: + bytes: [ 0xb3, 0x3b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x3b, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myr %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x3b, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myr %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x3b, 0xd0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myr %f13, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x3b, 0x50, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myr %f5, %f8, %f9" + + - + input: + bytes: [ 0xb3, 0x3b, 0xd0, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "myr %f13, %f15, %f15" + + - + input: + bytes: [ 0x54, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "n %r0, 0" + + - + input: + bytes: [ 0x54, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "n %r0, 4095" + + - + input: + bytes: [ 0x54, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "n %r0, 0(%r1)" + + - + input: + bytes: [ 0x54, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "n %r0, 0(%r15)" + + - + input: + bytes: [ 0x54, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "n %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x54, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "n %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x54, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "n %r15, 0" + + - + input: + bytes: [ 0xd4, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nc 0(1), 0" + + - + input: + bytes: [ 0xd4, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nc 0(1), 0(%r1)" + + - + input: + bytes: [ 0xd4, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nc 0(1), 0(%r15)" + + - + input: + bytes: [ 0xd4, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nc 0(1), 4095" + + - + input: + bytes: [ 0xd4, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nc 0(1), 4095(%r1)" + + - + input: + bytes: [ 0xd4, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nc 0(1), 4095(%r15)" + + - + input: + bytes: [ 0xd4, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nc 0(1,%r1), 0" + + - + input: + bytes: [ 0xd4, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nc 0(1,%r15), 0" + + - + input: + bytes: [ 0xd4, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nc 4095(1,%r1), 0" + + - + input: + bytes: [ 0xd4, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nc 4095(1,%r15), 0" + + - + input: + bytes: [ 0xd4, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nc 0(256,%r1), 0" + + - + input: + bytes: [ 0xd4, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nc 0(256,%r15), 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ng %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ng %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ng %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ng %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ng %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ng %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ng %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ng %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ng %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ng %r15, 0" + + - + input: + bytes: [ 0xb9, 0x80, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ngr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x80, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ngr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x80, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ngr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x80, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ngr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0xe4, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ngrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xe4, 0x40, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ngrk %r2, %r3, %r4" + + - + input: + bytes: [ 0x94, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ni 0, 0" + + - + input: + bytes: [ 0x94, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ni 4095, 0" + + - + input: + bytes: [ 0x94, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ni 0, 255" + + - + input: + bytes: [ 0x94, 0x2a, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ni 0(%r1), 42" + + - + input: + bytes: [ 0x94, 0x2a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ni 0(%r15), 42" + + - + input: + bytes: [ 0x94, 0x2a, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ni 4095(%r1), 42" + + - + input: + bytes: [ 0x94, 0x2a, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ni 4095(%r15), 42" + + - + input: + bytes: [ 0xb2, 0xfa, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "niai 0, 0" + + - + input: + bytes: [ 0xb2, 0xfa, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "niai 15, 0" + + - + input: + bytes: [ 0xb2, 0xfa, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "niai 0, 15" + + - + input: + bytes: [ 0xb2, 0xfa, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "niai 15, 15" + + - + input: + bytes: [ 0xc0, 0x0a, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nihf %r0, 0" + + - + input: + bytes: [ 0xc0, 0x0a, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nihf %r0, 4294967295" + + - + input: + bytes: [ 0xc0, 0xfa, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nihf %r15, 0" + + - + input: + bytes: [ 0xa5, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nihh %r0, 0" + + - + input: + bytes: [ 0xa5, 0x04, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nihh %r0, 32768" + + - + input: + bytes: [ 0xa5, 0x04, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nihh %r0, 65535" + + - + input: + bytes: [ 0xa5, 0xf4, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nihh %r15, 0" + + - + input: + bytes: [ 0xa5, 0x05, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nihl %r0, 0" + + - + input: + bytes: [ 0xa5, 0x05, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nihl %r0, 32768" + + - + input: + bytes: [ 0xa5, 0x05, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nihl %r0, 65535" + + - + input: + bytes: [ 0xa5, 0xf5, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nihl %r15, 0" + + - + input: + bytes: [ 0xc0, 0x0b, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nilf %r0, 0" + + - + input: + bytes: [ 0xc0, 0x0b, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nilf %r0, 4294967295" + + - + input: + bytes: [ 0xc0, 0xfb, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nilf %r15, 0" + + - + input: + bytes: [ 0xa5, 0x06, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nilh %r0, 0" + + - + input: + bytes: [ 0xa5, 0x06, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nilh %r0, 32768" + + - + input: + bytes: [ 0xa5, 0x06, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nilh %r0, 65535" + + - + input: + bytes: [ 0xa5, 0xf6, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nilh %r15, 0" + + - + input: + bytes: [ 0xa5, 0x07, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nill %r0, 0" + + - + input: + bytes: [ 0xa5, 0x07, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nill %r0, 32768" + + - + input: + bytes: [ 0xa5, 0x07, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nill %r0, 65535" + + - + input: + bytes: [ 0xa5, 0xf7, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nill %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "niy -524288, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "niy -1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "niy 0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "niy 1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "niy 524287, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "niy 0, 255" + + - + input: + bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "niy 0(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "niy 0(%r15), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "niy 524287(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "niy 524287(%r15), 42" + + - + input: + bytes: [ 0x14, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nr %r0, %r0" + + - + input: + bytes: [ 0x14, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nr %r0, %r15" + + - + input: + bytes: [ 0x14, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nr %r15, %r0" + + - + input: + bytes: [ 0x14, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0xf4, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xf4, 0x40, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "nrk %r2, %r3, %r4" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ntstg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ntstg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ntstg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ntstg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ntstg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ntstg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ntstg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ntstg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ntstg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ntstg %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ny %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ny %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ny %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ny %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ny %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ny %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ny %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ny %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ny %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ny %r15, 0" + + - + input: + bytes: [ 0x56, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "o %r0, 0" + + - + input: + bytes: [ 0x56, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "o %r0, 4095" + + - + input: + bytes: [ 0x56, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "o %r0, 0(%r1)" + + - + input: + bytes: [ 0x56, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "o %r0, 0(%r15)" + + - + input: + bytes: [ 0x56, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "o %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x56, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "o %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x56, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "o %r15, 0" + + - + input: + bytes: [ 0xd6, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oc 0(1), 0" + + - + input: + bytes: [ 0xd6, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oc 0(1), 0(%r1)" + + - + input: + bytes: [ 0xd6, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oc 0(1), 0(%r15)" + + - + input: + bytes: [ 0xd6, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oc 0(1), 4095" + + - + input: + bytes: [ 0xd6, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oc 0(1), 4095(%r1)" + + - + input: + bytes: [ 0xd6, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oc 0(1), 4095(%r15)" + + - + input: + bytes: [ 0xd6, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oc 0(1,%r1), 0" + + - + input: + bytes: [ 0xd6, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oc 0(1,%r15), 0" + + - + input: + bytes: [ 0xd6, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oc 4095(1,%r1), 0" + + - + input: + bytes: [ 0xd6, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oc 4095(1,%r15), 0" + + - + input: + bytes: [ 0xd6, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oc 0(256,%r1), 0" + + - + input: + bytes: [ 0xd6, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oc 0(256,%r15), 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "og %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "og %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "og %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "og %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "og %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "og %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "og %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "og %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "og %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x81 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "og %r15, 0" + + - + input: + bytes: [ 0xb9, 0x81, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ogr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x81, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ogr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x81, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ogr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x81, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ogr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0xe6, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ogrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xe6, 0x40, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ogrk %r2, %r3, %r4" + + - + input: + bytes: [ 0x96, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oi 0, 0" + + - + input: + bytes: [ 0x96, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oi 4095, 0" + + - + input: + bytes: [ 0x96, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oi 0, 255" + + - + input: + bytes: [ 0x96, 0x2a, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oi 0(%r1), 42" + + - + input: + bytes: [ 0x96, 0x2a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oi 0(%r15), 42" + + - + input: + bytes: [ 0x96, 0x2a, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oi 4095(%r1), 42" + + - + input: + bytes: [ 0x96, 0x2a, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oi 4095(%r15), 42" + + - + input: + bytes: [ 0xc0, 0x0c, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oihf %r0, 0" + + - + input: + bytes: [ 0xc0, 0x0c, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oihf %r0, 4294967295" + + - + input: + bytes: [ 0xc0, 0xfc, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oihf %r15, 0" + + - + input: + bytes: [ 0xa5, 0x08, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oihh %r0, 0" + + - + input: + bytes: [ 0xa5, 0x08, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oihh %r0, 32768" + + - + input: + bytes: [ 0xa5, 0x08, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oihh %r0, 65535" + + - + input: + bytes: [ 0xa5, 0xf8, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oihh %r15, 0" + + - + input: + bytes: [ 0xa5, 0x09, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oihl %r0, 0" + + - + input: + bytes: [ 0xa5, 0x09, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oihl %r0, 32768" + + - + input: + bytes: [ 0xa5, 0x09, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oihl %r0, 65535" + + - + input: + bytes: [ 0xa5, 0xf9, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oihl %r15, 0" + + - + input: + bytes: [ 0xc0, 0x0d, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oilf %r0, 0" + + - + input: + bytes: [ 0xc0, 0x0d, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oilf %r0, 4294967295" + + - + input: + bytes: [ 0xc0, 0xfd, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oilf %r15, 0" + + - + input: + bytes: [ 0xa5, 0x0a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oilh %r0, 0" + + - + input: + bytes: [ 0xa5, 0x0a, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oilh %r0, 32768" + + - + input: + bytes: [ 0xa5, 0x0a, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oilh %r0, 65535" + + - + input: + bytes: [ 0xa5, 0xfa, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oilh %r15, 0" + + - + input: + bytes: [ 0xa5, 0x0b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oill %r0, 0" + + - + input: + bytes: [ 0xa5, 0x0b, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oill %r0, 32768" + + - + input: + bytes: [ 0xa5, 0x0b, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oill %r0, 65535" + + - + input: + bytes: [ 0xa5, 0xfb, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oill %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oiy -524288, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oiy -1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oiy 0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oiy 1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oiy 524287, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oiy 0, 255" + + - + input: + bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oiy 0(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oiy 0(%r15), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oiy 524287(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oiy 524287(%r15), 42" + + - + input: + bytes: [ 0x16, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "or %r0, %r0" + + - + input: + bytes: [ 0x16, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "or %r0, %r15" + + - + input: + bytes: [ 0x16, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "or %r15, %r0" + + - + input: + bytes: [ 0x16, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "or %r7, %r8" + + - + input: + bytes: [ 0xb9, 0xf6, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ork %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xf6, 0x40, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ork %r2, %r3, %r4" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oy %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oy %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oy %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oy %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oy %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oy %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oy %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oy %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oy %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "oy %r15, 0" + + - + input: + bytes: [ 0xf2, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pack 0(1), 0(1)" + + - + input: + bytes: [ 0xf2, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pack 0(1), 0(1,%r1)" + + - + input: + bytes: [ 0xf2, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pack 0(1), 0(1,%r15)" + + - + input: + bytes: [ 0xf2, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pack 0(1), 4095(1)" + + - + input: + bytes: [ 0xf2, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pack 0(1), 4095(1,%r1)" + + - + input: + bytes: [ 0xf2, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pack 0(1), 4095(1,%r15)" + + - + input: + bytes: [ 0xf2, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pack 0(1,%r1), 0(1)" + + - + input: + bytes: [ 0xf2, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pack 0(1,%r15), 0(1)" + + - + input: + bytes: [ 0xf2, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pack 4095(1,%r1), 0(1)" + + - + input: + bytes: [ 0xf2, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pack 4095(1,%r15), 0(1)" + + - + input: + bytes: [ 0xf2, 0xf0, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pack 0(16,%r1), 0(1)" + + - + input: + bytes: [ 0xf2, 0xf0, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pack 0(16,%r15), 0(1)" + + - + input: + bytes: [ 0xf2, 0x0f, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pack 0(1), 0(16,%r1)" + + - + input: + bytes: [ 0xf2, 0x0f, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pack 0(1), 0(16,%r15)" + + - + input: + bytes: [ 0xb2, 0x48, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "palb" + + - + input: + bytes: [ 0xb2, 0x18, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pc 0" + + - + input: + bytes: [ 0xb2, 0x18, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pc 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x18, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pc 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x18, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pc 4095" + + - + input: + bytes: [ 0xb2, 0x18, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pc 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x18, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pc 4095(%r15)" + + - + input: + bytes: [ 0xb9, 0x2c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pcc" + + - + input: + bytes: [ 0xb9, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pckmo" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x36 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pfd 0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x36 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pfd 0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x36 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pfd 0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x36 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pfd 0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x36 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pfd 0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x36 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pfd 0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x36 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pfd 0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x36 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pfd 0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x36 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pfd 0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x36 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pfd 15, 0" + + - + input: + bytes: [ 0xb9, 0xaf, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pfmf %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xaf, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pfmf %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xaf, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pfmf %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xaf, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pfmf %r7, %r8" + + - + input: + bytes: [ 0xb9, 0xaf, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pfmf %r15, %r15" + + - + input: + bytes: [ 0x01, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pfpo" + + - + input: + bytes: [ 0xb2, 0x2e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pgin %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x2e, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pgin %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x2e, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pgin %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x2e, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pgin %r7, %r8" + + - + input: + bytes: [ 0xb2, 0x2e, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pgin %r15, %r15" + + - + input: + bytes: [ 0xb2, 0x2f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pgout %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x2f, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pgout %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x2f, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pgout %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x2f, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pgout %r7, %r8" + + - + input: + bytes: [ 0xb2, 0x2f, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pgout %r15, %r15" + + - + input: + bytes: [ 0xe9, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pka 0, 0(1)" + + - + input: + bytes: [ 0xe9, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pka 0, 0(1,%r1)" + + - + input: + bytes: [ 0xe9, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pka 0, 0(1,%r15)" + + - + input: + bytes: [ 0xe9, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pka 0, 4095(1)" + + - + input: + bytes: [ 0xe9, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pka 0, 4095(1,%r1)" + + - + input: + bytes: [ 0xe9, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pka 0, 4095(1,%r15)" + + - + input: + bytes: [ 0xe9, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pka 0(%r1), 0(1)" + + - + input: + bytes: [ 0xe9, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pka 0(%r15), 0(1)" + + - + input: + bytes: [ 0xe9, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pka 4095(%r1), 0(1)" + + - + input: + bytes: [ 0xe9, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pka 4095(%r15), 0(1)" + + - + input: + bytes: [ 0xe9, 0xff, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pka 0, 0(256,%r1)" + + - + input: + bytes: [ 0xe9, 0xff, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pka 0, 0(256,%r15)" + + - + input: + bytes: [ 0xe1, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pku 0, 0(1)" + + - + input: + bytes: [ 0xe1, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pku 0, 0(1,%r1)" + + - + input: + bytes: [ 0xe1, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pku 0, 0(1,%r15)" + + - + input: + bytes: [ 0xe1, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pku 0, 4095(1)" + + - + input: + bytes: [ 0xe1, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pku 0, 4095(1,%r1)" + + - + input: + bytes: [ 0xe1, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pku 0, 4095(1,%r15)" + + - + input: + bytes: [ 0xe1, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pku 0(%r1), 0(1)" + + - + input: + bytes: [ 0xe1, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pku 0(%r15), 0(1)" + + - + input: + bytes: [ 0xe1, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pku 4095(%r1), 0(1)" + + - + input: + bytes: [ 0xe1, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pku 4095(%r15), 0(1)" + + - + input: + bytes: [ 0xe1, 0xff, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pku 0, 0(256,%r1)" + + - + input: + bytes: [ 0xe1, 0xff, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pku 0, 0(256,%r15)" + + - + input: + bytes: [ 0xee, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "plo %r0, 0, %r0, 0" + + - + input: + bytes: [ 0xee, 0x24, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "plo %r2, 0, %r4, 4095" + + - + input: + bytes: [ 0xee, 0x24, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "plo %r2, 0, %r4, 0(%r1)" + + - + input: + bytes: [ 0xee, 0x24, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "plo %r2, 0, %r4, 0(%r15)" + + - + input: + bytes: [ 0xee, 0x24, 0x10, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "plo %r2, 0(%r1), %r4, 4095(%r15)" + + - + input: + bytes: [ 0xee, 0x24, 0x10, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "plo %r2, 0(%r1), %r4, 0(%r15)" + + - + input: + bytes: [ 0xee, 0x24, 0x1f, 0xff, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "plo %r2, 4095(%r1), %r4, 0(%r15)" + + - + input: + bytes: [ 0xb9, 0xe1, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "popcnt %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xe1, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "popcnt %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xe1, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "popcnt %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xe1, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "popcnt %r7, %r8" + + - + input: + bytes: [ 0xb2, 0xe8, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ppa %r0, %r0, 0" + + - + input: + bytes: [ 0xb2, 0xe8, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ppa %r0, %r0, 15" + + - + input: + bytes: [ 0xb2, 0xe8, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ppa %r0, %r15, 0" + + - + input: + bytes: [ 0xb2, 0xe8, 0x70, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ppa %r4, %r6, 7" + + - + input: + bytes: [ 0xb2, 0xe8, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ppa %r15, %r0, 0" + + - + input: + bytes: [ 0x01, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pr" + + - + input: + bytes: [ 0xb2, 0x28, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pt %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x28, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pt %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x28, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pt %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x28, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pt %r7, %r8" + + - + input: + bytes: [ 0xb9, 0xa2, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ptf %r0" + + - + input: + bytes: [ 0xb9, 0xa2, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ptf %r1" + + - + input: + bytes: [ 0xb9, 0xa2, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ptf %r15" + + - + input: + bytes: [ 0x01, 0x04 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ptff" + + - + input: + bytes: [ 0xb9, 0x9e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pti %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x9e, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pti %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x9e, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pti %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x9e, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "pti %r7, %r8" + + - + input: + bytes: [ 0xb2, 0x0d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ptlb" + + - + input: + bytes: [ 0xb3, 0xf5, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qadtr %f0, %f0, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xf5, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qadtr %f0, %f0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xf5, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qadtr %f0, %f0, %f15, 0" + + - + input: + bytes: [ 0xb3, 0xf5, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qadtr %f0, %f15, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xf5, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qadtr %f4, %f5, %f6, 7" + + - + input: + bytes: [ 0xb3, 0xf5, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qadtr %f15, %f0, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xfd, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qaxtr %f0, %f0, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xfd, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qaxtr %f0, %f0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xfd, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qaxtr %f0, %f0, %f13, 0" + + - + input: + bytes: [ 0xb3, 0xfd, 0xd0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qaxtr %f0, %f13, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xfd, 0x88, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qaxtr %f8, %f8, %f8, 8" + + - + input: + bytes: [ 0xb3, 0xfd, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qaxtr %f13, %f0, %f0, 0" + + - + input: + bytes: [ 0xb2, 0x8e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qctri 0" + + - + input: + bytes: [ 0xb2, 0x8e, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qctri 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x8e, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qctri 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x8e, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qctri 4095" + + - + input: + bytes: [ 0xb2, 0x8e, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qctri 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x8e, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qctri 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0x86, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qsi 0" + + - + input: + bytes: [ 0xb2, 0x86, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qsi 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x86, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qsi 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x86, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qsi 4095" + + - + input: + bytes: [ 0xb2, 0x86, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qsi 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x86, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "qsi 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0x3b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rchp" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbg %r0, %r0, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbg %r0, %r0, 0, 0, 63" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbg %r0, %r0, 0, 255, 0" + + - + input: + bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbg %r0, %r0, 255, 0, 0" + + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbg %r0, %r15, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbg %r15, %r0, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbg %r4, %r5, 6, 7, 8" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbgn %r0, %r0, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbgn %r0, %r0, 0, 0, 63" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbgn %r0, %r0, 0, 255, 0" + + - + input: + bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbgn %r0, %r0, 255, 0, 0" + + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbgn %r0, %r15, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbgn %r15, %r0, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbgn %r4, %r5, 6, 7, 8" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x5d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbhg %r0, %r0, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x5d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbhg %r0, %r0, 0, 0, 63" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x5d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbhg %r0, %r0, 0, 255, 0" + + - + input: + bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x5d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbhg %r0, %r0, 255, 0, 0" + + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x5d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbhg %r0, %r15, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x5d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbhg %r15, %r0, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x5d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risbhg %r4, %r5, 6, 7, 8" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risblg %r0, %r0, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risblg %r0, %r0, 0, 0, 63" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risblg %r0, %r0, 0, 255, 0" + + - + input: + bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risblg %r0, %r0, 255, 0, 0" + + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risblg %r0, %r15, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risblg %r15, %r0, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "risblg %r4, %r5, 6, 7, 8" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rll %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rll %r15, %r1, 0" + + - + input: + bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rll %r1, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rll %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rll %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rll %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rll %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rll %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rll %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rll %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rll %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x1d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rll %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rllg %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rllg %r15, %r1, 0" + + - + input: + bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rllg %r1, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rllg %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rllg %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rllg %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rllg %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rllg %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rllg %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rllg %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rllg %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x1c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rllg %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rnsbg %r0, %r0, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rnsbg %r0, %r0, 0, 0, 63" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rnsbg %r0, %r0, 0, 255, 0" + + - + input: + bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rnsbg %r0, %r0, 255, 0, 0" + + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rnsbg %r0, %r15, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rnsbg %r15, %r0, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rnsbg %r4, %r5, 6, 7, 8" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rosbg %r0, %r0, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rosbg %r0, %r0, 0, 0, 63" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rosbg %r0, %r0, 0, 255, 0" + + - + input: + bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rosbg %r0, %r0, 255, 0, 0" + + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rosbg %r0, %r15, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rosbg %r15, %r0, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x56 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rosbg %r4, %r5, 6, 7, 8" + + - + input: + bytes: [ 0xb2, 0x77, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rp 0" + + - + input: + bytes: [ 0xb2, 0x77, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rp 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x77, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rp 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x77, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rp 4095" + + - + input: + bytes: [ 0xb2, 0x77, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rp 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x77, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rp 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0x2a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrbe %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x2a, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrbe %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x2a, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrbe %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x2a, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrbe %r7, %r8" + + - + input: + bytes: [ 0xb2, 0x2a, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrbe %r15, %r15" + + - + input: + bytes: [ 0xb9, 0xae, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrbm %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xae, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrbm %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xae, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrbm %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xae, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrbm %r7, %r8" + + - + input: + bytes: [ 0xb9, 0xae, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrbm %r15, %r15" + + - + input: + bytes: [ 0xb3, 0xf7, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrdtr %f0, %f0, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xf7, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrdtr %f0, %f0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xf7, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrdtr %f0, %f0, %f15, 0" + + - + input: + bytes: [ 0xb3, 0xf7, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrdtr %f0, %f15, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xf7, 0x57, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrdtr %f4, %f5, %f6, 7" + + - + input: + bytes: [ 0xb3, 0xf7, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrdtr %f15, %f0, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrxtr %f0, %f0, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xff, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrxtr %f0, %f0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xff, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrxtr %f0, %f0, %f13, 0" + + - + input: + bytes: [ 0xb3, 0xff, 0xd0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrxtr %f0, %f13, %f0, 0" + + - + input: + bytes: [ 0xb3, 0xff, 0x88, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrxtr %f8, %f8, %f8, 8" + + - + input: + bytes: [ 0xb3, 0xff, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rrxtr %f13, %f0, %f0, 0" + + - + input: + bytes: [ 0xb2, 0x38, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rsch" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rxsbg %r0, %r0, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rxsbg %r0, %r0, 0, 0, 63" + + - + input: + bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rxsbg %r0, %r0, 0, 255, 0" + + - + input: + bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rxsbg %r0, %r0, 255, 0, 0" + + - + input: + bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rxsbg %r0, %r15, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rxsbg %r15, %r0, 0, 0, 0" + + - + input: + bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "rxsbg %r4, %r5, 6, 7, 8" + + - + input: + bytes: [ 0x5b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s %r0, 0" + + - + input: + bytes: [ 0x5b, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s %r0, 4095" + + - + input: + bytes: [ 0x5b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s %r0, 0(%r1)" + + - + input: + bytes: [ 0x5b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s %r0, 0(%r15)" + + - + input: + bytes: [ 0x5b, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x5b, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x5b, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "s %r15, 0" + + - + input: + bytes: [ 0xb2, 0x19, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sac 0" + + - + input: + bytes: [ 0xb2, 0x19, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sac 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x19, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sac 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x19, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sac 4095" + + - + input: + bytes: [ 0xb2, 0x19, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sac 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x19, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sac 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0x79, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sacf 0" + + - + input: + bytes: [ 0xb2, 0x79, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sacf 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x79, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sacf 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x79, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sacf 4095" + + - + input: + bytes: [ 0xb2, 0x79, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sacf 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x79, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sacf 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0x37, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sal" + + - + input: + bytes: [ 0x01, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sam24" + + - + input: + bytes: [ 0x01, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sam31" + + - + input: + bytes: [ 0x01, 0x0e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sam64" + + - + input: + bytes: [ 0xb2, 0x4e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sar %a0, %r0" + + - + input: + bytes: [ 0xb2, 0x4e, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sar %a0, %r15" + + - + input: + bytes: [ 0xb2, 0x4e, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sar %a15, %r0" + + - + input: + bytes: [ 0xb2, 0x4e, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sar %a7, %r8" + + - + input: + bytes: [ 0xb2, 0x4e, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sar %a15, %r15" + + - + input: + bytes: [ 0xb2, 0xe0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "scctr %r0, %r0" + + - + input: + bytes: [ 0xb2, 0xe0, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "scctr %r0, %r15" + + - + input: + bytes: [ 0xb2, 0xe0, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "scctr %r15, %r0" + + - + input: + bytes: [ 0xb2, 0xe0, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "scctr %r7, %r8" + + - + input: + bytes: [ 0xb2, 0x3c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "schm" + + - + input: + bytes: [ 0xb2, 0x04, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sck 0" + + - + input: + bytes: [ 0xb2, 0x04, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sck 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x04, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sck 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x04, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sck 4095" + + - + input: + bytes: [ 0xb2, 0x04, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sck 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x04, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sck 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0x06, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sckc 0" + + - + input: + bytes: [ 0xb2, 0x06, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sckc 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x06, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sckc 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x06, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sckc 4095" + + - + input: + bytes: [ 0xb2, 0x06, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sckc 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x06, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sckc 4095(%r15)" + + - + input: + bytes: [ 0x01, 0x07 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sckpf" + + - + input: + bytes: [ 0x6b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sd %f0, 0" + + - + input: + bytes: [ 0x6b, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sd %f0, 4095" + + - + input: + bytes: [ 0x6b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sd %f0, 0(%r1)" + + - + input: + bytes: [ 0x6b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sd %f0, 0(%r15)" + + - + input: + bytes: [ 0x6b, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sd %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x6b, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sd %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x6b, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sd %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdb %f15, 0" + + - + input: + bytes: [ 0xb3, 0x1b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdbr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x1b, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdbr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x1b, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdbr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x1b, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdbr %f15, %f0" + + - + input: + bytes: [ 0x2b, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdr %f0, %f0" + + - + input: + bytes: [ 0x2b, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdr %f0, %f15" + + - + input: + bytes: [ 0x2b, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdr %f7, %f8" + + - + input: + bytes: [ 0x2b, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0xd3, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdtr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xd3, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdtr %f0, %f0, %f15" + + - + input: + bytes: [ 0xb3, 0xd3, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdtr %f0, %f15, %f0" + + - + input: + bytes: [ 0xb3, 0xd3, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdtr %f15, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xd3, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdtr %f7, %f8, %f9" + + - + input: + bytes: [ 0xb3, 0xd3, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdtra %f0, %f0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xd3, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdtra %f0, %f0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xd3, 0xf1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdtra %f0, %f0, %f15, 1" + + - + input: + bytes: [ 0xb3, 0xd3, 0x01, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdtra %f0, %f15, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xd3, 0x01, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdtra %f15, %f0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xd3, 0x9a, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sdtra %f7, %f8, %f9, 10" + + - + input: + bytes: [ 0x7b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "se %f0, 0" + + - + input: + bytes: [ 0x7b, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "se %f0, 4095" + + - + input: + bytes: [ 0x7b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "se %f0, 0(%r1)" + + - + input: + bytes: [ 0x7b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "se %f0, 0(%r15)" + + - + input: + bytes: [ 0x7b, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "se %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x7b, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "se %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x7b, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "se %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "seb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "seb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "seb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "seb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "seb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "seb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "seb %f15, 0" + + - + input: + bytes: [ 0xb3, 0x0b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sebr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x0b, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sebr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x0b, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sebr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x0b, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sebr %f15, %f0" + + - + input: + bytes: [ 0x3b, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ser %f0, %f0" + + - + input: + bytes: [ 0x3b, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ser %f0, %f15" + + - + input: + bytes: [ 0x3b, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ser %f7, %f8" + + - + input: + bytes: [ 0x3b, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ser %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x85, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sfasr %r0" + + - + input: + bytes: [ 0xb3, 0x85, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sfasr %r1" + + - + input: + bytes: [ 0xb3, 0x85, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sfasr %r15" + + - + input: + bytes: [ 0xb3, 0x84, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sfpc %r0" + + - + input: + bytes: [ 0xb3, 0x84, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sfpc %r1" + + - + input: + bytes: [ 0xb3, 0x84, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sfpc %r15" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sg %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x19 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgf %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x19 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgf %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x19 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgf %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x19 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgf %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x19 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgf %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x19 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgf %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x19 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgf %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x19 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgf %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x19 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgf %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x19 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgf %r15, 0" + + - + input: + bytes: [ 0xb9, 0x19, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgfr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x19, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgfr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x19, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgfr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x19, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgfr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x09, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x09, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x09, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x09, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0xe9, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xe9, 0x40, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sgrk %r2, %r3, %r4" + + - + input: + bytes: [ 0x4b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sh %r0, 0" + + - + input: + bytes: [ 0x4b, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sh %r0, 4095" + + - + input: + bytes: [ 0x4b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sh %r0, 0(%r1)" + + - + input: + bytes: [ 0x4b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sh %r0, 0(%r15)" + + - + input: + bytes: [ 0x4b, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sh %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x4b, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sh %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x4b, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sh %r15, 0" + + - + input: + bytes: [ 0xb9, 0xc9, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shhhr %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xc9, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shhhr %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xc9, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shhhr %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xc9, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shhhr %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xc9, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shhhr %r7, %r8, %r9" + + - + input: + bytes: [ 0xb9, 0xd9, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shhlr %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xd9, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shhlr %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xd9, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shhlr %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xd9, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shhlr %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xd9, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shhlr %r7, %r8, %r9" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x7b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shy %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x7b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shy %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x7b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shy %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x7b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shy %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x7b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shy %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x7b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shy %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x7b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shy %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x7b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shy %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x7b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shy %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x7b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "shy %r15, 0" + + - + input: + bytes: [ 0xb2, 0x14, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sie 0" + + - + input: + bytes: [ 0xb2, 0x14, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sie 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x14, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sie 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x14, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sie 4095" + + - + input: + bytes: [ 0xb2, 0x14, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sie 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x14, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sie 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0x74, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "siga 0" + + - + input: + bytes: [ 0xb2, 0x74, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "siga 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x74, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "siga 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x74, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "siga 4095" + + - + input: + bytes: [ 0xb2, 0x74, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "siga 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x74, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "siga 4095(%r15)" + + - + input: + bytes: [ 0xae, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sigp %r0, %r0, 0" + + - + input: + bytes: [ 0xae, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sigp %r0, %r15, 0" + + - + input: + bytes: [ 0xae, 0xef, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sigp %r14, %r15, 0" + + - + input: + bytes: [ 0xae, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sigp %r15, %r15, 0" + + - + input: + bytes: [ 0xae, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sigp %r0, %r0, 4095" + + - + input: + bytes: [ 0xae, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sigp %r0, %r0, 1" + + - + input: + bytes: [ 0xae, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sigp %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xae, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sigp %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xae, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sigp %r0, %r0, 4095(%r1)" + + - + input: + bytes: [ 0xae, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sigp %r0, %r0, 4095(%r15)" + + - + input: + bytes: [ 0x5f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sl %r0, 0" + + - + input: + bytes: [ 0x5f, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sl %r0, 4095" + + - + input: + bytes: [ 0x5f, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sl %r0, 0(%r1)" + + - + input: + bytes: [ 0x5f, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sl %r0, 0(%r15)" + + - + input: + bytes: [ 0x5f, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sl %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x5f, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sl %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x5f, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sl %r15, 0" + + - + input: + bytes: [ 0x8b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sla %r0, 0" + + - + input: + bytes: [ 0x8b, 0x70, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sla %r7, 0" + + - + input: + bytes: [ 0x8b, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sla %r15, 0" + + - + input: + bytes: [ 0x8b, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sla %r0, 4095" + + - + input: + bytes: [ 0x8b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sla %r0, 0(%r1)" + + - + input: + bytes: [ 0x8b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sla %r0, 0(%r15)" + + - + input: + bytes: [ 0x8b, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sla %r0, 4095(%r1)" + + - + input: + bytes: [ 0x8b, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sla %r0, 4095(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slag %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slag %r15, %r1, 0" + + - + input: + bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slag %r1, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slag %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slag %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slag %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slag %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slag %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slag %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slag %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slag %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slag %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xdd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slak %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0xdd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slak %r15, %r1, 0" + + - + input: + bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0xdd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slak %r1, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0xdd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slak %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xdd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slak %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xdd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slak %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xdd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slak %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xdd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slak %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xdd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slak %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xdd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slak %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xdd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slak %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xdd ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slak %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x99 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slb %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x99 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slb %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x99 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slb %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x99 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slb %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x99 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slb %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x99 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slb %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x99 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slb %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x99 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slb %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x99 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slb %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x99 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slb %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x89 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbg %r15, 0" + + - + input: + bytes: [ 0xb9, 0x89, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbgr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x89, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbgr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x89, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbgr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x89, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbgr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x99, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x99, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x99, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x99, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slbr %r7, %r8" + + - + input: + bytes: [ 0x8f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slda %r0, 0" + + - + input: + bytes: [ 0x8f, 0x60, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slda %r6, 0" + + - + input: + bytes: [ 0x8f, 0xe0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slda %r14, 0" + + - + input: + bytes: [ 0x8f, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slda %r0, 4095" + + - + input: + bytes: [ 0x8f, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slda %r0, 0(%r1)" + + - + input: + bytes: [ 0x8f, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slda %r0, 0(%r15)" + + - + input: + bytes: [ 0x8f, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slda %r0, 4095(%r1)" + + - + input: + bytes: [ 0x8f, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slda %r0, 4095(%r15)" + + - + input: + bytes: [ 0x8d, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldl %r0, 0" + + - + input: + bytes: [ 0x8d, 0x60, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldl %r6, 0" + + - + input: + bytes: [ 0x8d, 0xe0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldl %r14, 0" + + - + input: + bytes: [ 0x8d, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldl %r0, 4095" + + - + input: + bytes: [ 0x8d, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldl %r0, 0(%r1)" + + - + input: + bytes: [ 0x8d, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldl %r0, 0(%r15)" + + - + input: + bytes: [ 0x8d, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldl %r0, 4095(%r1)" + + - + input: + bytes: [ 0x8d, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldl %r0, 4095(%r15)" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldt %f0, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x40 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldt %f0, %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldt %f0, %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldt %f0, %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x40 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldt %f0, %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x40 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldt %f0, %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x40 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldt %f0, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x40 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldt %f15, %f0, 0" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x40 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sldt %f15, %f15, 0" + + - + input: + bytes: [ 0xc2, 0x05, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slfi %r0, 0" + + - + input: + bytes: [ 0xc2, 0x05, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slfi %r0, 4294967295" + + - + input: + bytes: [ 0xc2, 0xf5, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slfi %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slg %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgf %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgf %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgf %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgf %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgf %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgf %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgf %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgf %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgf %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x1b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgf %r15, 0" + + - + input: + bytes: [ 0xc2, 0x04, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgfi %r0, 0" + + - + input: + bytes: [ 0xc2, 0x04, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgfi %r0, 4294967295" + + - + input: + bytes: [ 0xc2, 0xf4, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgfi %r15, 0" + + - + input: + bytes: [ 0xb9, 0x1b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgfr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x1b, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgfr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x1b, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgfr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x1b, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgfr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x0b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x0b, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x0b, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x0b, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0xeb, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xeb, 0x40, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slgrk %r2, %r3, %r4" + + - + input: + bytes: [ 0xb9, 0xcb, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slhhhr %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xcb, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slhhhr %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xcb, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slhhhr %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xcb, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slhhhr %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xcb, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slhhhr %r7, %r8, %r9" + + - + input: + bytes: [ 0xb9, 0xdb, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slhhlr %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xdb, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slhhlr %r0, %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xdb, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slhhlr %r0, %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xdb, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slhhlr %r15, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xdb, 0x90, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slhhlr %r7, %r8, %r9" + + - + input: + bytes: [ 0x89, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sll %r0, 0" + + - + input: + bytes: [ 0x89, 0x70, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sll %r7, 0" + + - + input: + bytes: [ 0x89, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sll %r15, 0" + + - + input: + bytes: [ 0x89, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sll %r0, 4095" + + - + input: + bytes: [ 0x89, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sll %r0, 0(%r1)" + + - + input: + bytes: [ 0x89, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sll %r0, 0(%r15)" + + - + input: + bytes: [ 0x89, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sll %r0, 4095(%r1)" + + - + input: + bytes: [ 0x89, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sll %r0, 4095(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllg %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllg %r15, %r1, 0" + + - + input: + bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllg %r1, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllg %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllg %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllg %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllg %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllg %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllg %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllg %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllg %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllg %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllk %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllk %r15, %r1, 0" + + - + input: + bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllk %r1, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllk %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllk %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllk %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllk %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllk %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllk %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllk %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllk %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xdf ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sllk %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0x1f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slr %r0, %r0" + + - + input: + bytes: [ 0x1f, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slr %r0, %r15" + + - + input: + bytes: [ 0x1f, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slr %r15, %r0" + + - + input: + bytes: [ 0x1f, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0xfb, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xfb, 0x40, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slrk %r2, %r3, %r4" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slxt %f0, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slxt %f0, %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slxt %f0, %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slxt %f0, %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slxt %f0, %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slxt %f0, %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xd0, 0x00, 0x00, 0x00, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slxt %f0, %f13, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xd0, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slxt %f13, %f0, 0" + + - + input: + bytes: [ 0xed, 0xd0, 0x00, 0x00, 0xd0, 0x48 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "slxt %f13, %f13, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sly %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sly %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sly %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sly %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sly %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sly %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sly %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sly %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sly %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x5f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sly %r15, 0" + + - + input: + bytes: [ 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sp 0(1), 0(1)" + + - + input: + bytes: [ 0xfb, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sp 0(1), 0(1,%r1)" + + - + input: + bytes: [ 0xfb, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sp 0(1), 0(1,%r15)" + + - + input: + bytes: [ 0xfb, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sp 0(1), 4095(1)" + + - + input: + bytes: [ 0xfb, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sp 0(1), 4095(1,%r1)" + + - + input: + bytes: [ 0xfb, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sp 0(1), 4095(1,%r15)" + + - + input: + bytes: [ 0xfb, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sp 0(1,%r1), 0(1)" + + - + input: + bytes: [ 0xfb, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sp 0(1,%r15), 0(1)" + + - + input: + bytes: [ 0xfb, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sp 4095(1,%r1), 0(1)" + + - + input: + bytes: [ 0xfb, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sp 4095(1,%r15), 0(1)" + + - + input: + bytes: [ 0xfb, 0xf0, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sp 0(16,%r1), 0(1)" + + - + input: + bytes: [ 0xfb, 0xf0, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sp 0(16,%r15), 0(1)" + + - + input: + bytes: [ 0xfb, 0x0f, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sp 0(1), 0(16,%r1)" + + - + input: + bytes: [ 0xfb, 0x0f, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sp 0(1), 0(16,%r15)" + + - + input: + bytes: [ 0xb2, 0xe1, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spctr %r0, %r0" + + - + input: + bytes: [ 0xb2, 0xe1, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spctr %r0, %r15" + + - + input: + bytes: [ 0xb2, 0xe1, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spctr %r15, %r0" + + - + input: + bytes: [ 0xb2, 0xe1, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spctr %r7, %r8" + + - + input: + bytes: [ 0xb2, 0x0a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spka 0" + + - + input: + bytes: [ 0xb2, 0x0a, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spka 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x0a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spka 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x0a, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spka 4095" + + - + input: + bytes: [ 0xb2, 0x0a, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spka 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x0a, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spka 4095(%r15)" + + - + input: + bytes: [ 0x04, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spm %r0" + + - + input: + bytes: [ 0x04, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spm %r1" + + - + input: + bytes: [ 0x04, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spm %r15" + + - + input: + bytes: [ 0xb2, 0x08, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spt 0" + + - + input: + bytes: [ 0xb2, 0x08, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spt 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x08, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spt 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x08, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spt 4095" + + - + input: + bytes: [ 0xb2, 0x08, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spt 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x08, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spt 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0x10, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spx 0" + + - + input: + bytes: [ 0xb2, 0x10, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spx 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x10, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spx 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x10, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spx 4095" + + - + input: + bytes: [ 0xb2, 0x10, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spx 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x10, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "spx 4095(%r15)" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x35 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqd %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x35 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqd %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x35 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqd %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x35 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqd %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x35 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqd %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x35 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqd %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x35 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqd %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x15 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqdb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x15 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqdb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x15 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqdb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x15 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqdb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x15 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqdb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x15 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqdb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x15 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqdb %f15, 0" + + - + input: + bytes: [ 0xb3, 0x15, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqdbr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x15, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqdbr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x15, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqdbr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x15, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqdbr %f15, %f0" + + - + input: + bytes: [ 0xb2, 0x44, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqdr %f0, %f0" + + - + input: + bytes: [ 0xb2, 0x44, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqdr %f0, %f15" + + - + input: + bytes: [ 0xb2, 0x44, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqdr %f7, %f8" + + - + input: + bytes: [ 0xb2, 0x44, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqdr %f15, %f0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqe %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqe %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqe %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqe %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqe %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqe %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x34 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqe %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqeb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqeb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqeb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqeb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqeb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqeb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x14 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqeb %f15, 0" + + - + input: + bytes: [ 0xb3, 0x14, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqebr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x14, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqebr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x14, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqebr %f7, %f8" + + - + input: + bytes: [ 0xb3, 0x14, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqebr %f15, %f0" + + - + input: + bytes: [ 0xb2, 0x45, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqer %f0, %f0" + + - + input: + bytes: [ 0xb2, 0x45, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqer %f0, %f15" + + - + input: + bytes: [ 0xb2, 0x45, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqer %f7, %f8" + + - + input: + bytes: [ 0xb2, 0x45, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqer %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x16, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqxbr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x16, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqxbr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x16, 0x00, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqxbr %f8, %f8" + + - + input: + bytes: [ 0xb3, 0x16, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqxbr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0x36, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqxr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x36, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqxr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x36, 0x00, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqxr %f8, %f8" + + - + input: + bytes: [ 0xb3, 0x36, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sqxr %f13, %f0" + + - + input: + bytes: [ 0x1b, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sr %r0, %r0" + + - + input: + bytes: [ 0x1b, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sr %r0, %r15" + + - + input: + bytes: [ 0x1b, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sr %r15, %r0" + + - + input: + bytes: [ 0x1b, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sr %r7, %r8" + + - + input: + bytes: [ 0x8a, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sra %r0, 0" + + - + input: + bytes: [ 0x8a, 0x70, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sra %r7, 0" + + - + input: + bytes: [ 0x8a, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sra %r15, 0" + + - + input: + bytes: [ 0x8a, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sra %r0, 4095" + + - + input: + bytes: [ 0x8a, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sra %r0, 0(%r1)" + + - + input: + bytes: [ 0x8a, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sra %r0, 0(%r15)" + + - + input: + bytes: [ 0x8a, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sra %r0, 4095(%r1)" + + - + input: + bytes: [ 0x8a, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sra %r0, 4095(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srag %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srag %r15, %r1, 0" + + - + input: + bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srag %r1, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srag %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srag %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srag %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srag %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srag %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srag %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srag %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srag %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x0a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srag %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xdc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srak %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0xdc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srak %r15, %r1, 0" + + - + input: + bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0xdc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srak %r1, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0xdc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srak %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xdc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srak %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xdc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srak %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xdc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srak %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xdc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srak %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xdc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srak %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xdc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srak %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xdc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srak %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xdc ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srak %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0x8e, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srda %r0, 0" + + - + input: + bytes: [ 0x8e, 0x60, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srda %r6, 0" + + - + input: + bytes: [ 0x8e, 0xe0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srda %r14, 0" + + - + input: + bytes: [ 0x8e, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srda %r0, 4095" + + - + input: + bytes: [ 0x8e, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srda %r0, 0(%r1)" + + - + input: + bytes: [ 0x8e, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srda %r0, 0(%r15)" + + - + input: + bytes: [ 0x8e, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srda %r0, 4095(%r1)" + + - + input: + bytes: [ 0x8e, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srda %r0, 4095(%r15)" + + - + input: + bytes: [ 0x8c, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srdl %r0, 0" + + - + input: + bytes: [ 0x8c, 0x60, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srdl %r6, 0" + + - + input: + bytes: [ 0x8c, 0xe0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srdl %r14, 0" + + - + input: + bytes: [ 0x8c, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srdl %r0, 4095" + + - + input: + bytes: [ 0x8c, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srdl %r0, 0(%r1)" + + - + input: + bytes: [ 0x8c, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srdl %r0, 0(%r15)" + + - + input: + bytes: [ 0x8c, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srdl %r0, 4095(%r1)" + + - + input: + bytes: [ 0x8c, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srdl %r0, 4095(%r15)" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x41 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srdt %f0, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x41 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srdt %f0, %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x41 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srdt %f0, %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x41 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srdt %f0, %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x41 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srdt %f0, %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x41 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srdt %f0, %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x41 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srdt %f0, %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x41 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srdt %f15, %f0, 0" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x41 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srdt %f15, %f15, 0" + + - + input: + bytes: [ 0xb9, 0xf9, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xf9, 0x40, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srk %r2, %r3, %r4" + + - + input: + bytes: [ 0x88, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srl %r0, 0" + + - + input: + bytes: [ 0x88, 0x70, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srl %r7, 0" + + - + input: + bytes: [ 0x88, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srl %r15, 0" + + - + input: + bytes: [ 0x88, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srl %r0, 4095" + + - + input: + bytes: [ 0x88, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srl %r0, 0(%r1)" + + - + input: + bytes: [ 0x88, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srl %r0, 0(%r15)" + + - + input: + bytes: [ 0x88, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srl %r0, 4095(%r1)" + + - + input: + bytes: [ 0x88, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srl %r0, 4095(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlg %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlg %r15, %r1, 0" + + - + input: + bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlg %r1, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlg %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlg %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlg %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlg %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlg %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlg %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlg %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlg %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x0c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlg %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlk %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlk %r15, %r1, 0" + + - + input: + bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlk %r1, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlk %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlk %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlk %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlk %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlk %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlk %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlk %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlk %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xde ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srlk %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xb2, 0x99, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srnm 0" + + - + input: + bytes: [ 0xb2, 0x99, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srnm 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x99, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srnm 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x99, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srnm 4095" + + - + input: + bytes: [ 0xb2, 0x99, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srnm 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x99, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srnm 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0xb8, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srnmb 0" + + - + input: + bytes: [ 0xb2, 0xb8, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srnmb 0(%r1)" + + - + input: + bytes: [ 0xb2, 0xb8, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srnmb 0(%r15)" + + - + input: + bytes: [ 0xb2, 0xb8, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srnmb 4095" + + - + input: + bytes: [ 0xb2, 0xb8, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srnmb 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0xb8, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srnmb 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0xb9, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srnmt 0" + + - + input: + bytes: [ 0xb2, 0xb9, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srnmt 0(%r1)" + + - + input: + bytes: [ 0xb2, 0xb9, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srnmt 0(%r15)" + + - + input: + bytes: [ 0xb2, 0xb9, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srnmt 4095" + + - + input: + bytes: [ 0xb2, 0xb9, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srnmt 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0xb9, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srnmt 4095(%r15)" + + - + input: + bytes: [ 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srp 0(1), 0, 0" + + - + input: + bytes: [ 0xf0, 0x0f, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srp 0(1), 0, 15" + + - + input: + bytes: [ 0xf0, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srp 0(1), 0(%r1), 0" + + - + input: + bytes: [ 0xf0, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srp 0(1), 0(%r15), 0" + + - + input: + bytes: [ 0xf0, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srp 0(1), 4095, 0" + + - + input: + bytes: [ 0xf0, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srp 0(1), 4095(%r1), 0" + + - + input: + bytes: [ 0xf0, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srp 0(1), 4095(%r15), 0" + + - + input: + bytes: [ 0xf0, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srp 0(1,%r1), 0, 0" + + - + input: + bytes: [ 0xf0, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srp 0(1,%r15), 0, 0" + + - + input: + bytes: [ 0xf0, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srp 4095(1,%r1), 0, 0" + + - + input: + bytes: [ 0xf0, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srp 4095(1,%r15), 0, 0" + + - + input: + bytes: [ 0xf0, 0xf0, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srp 0(16,%r1), 0, 0" + + - + input: + bytes: [ 0xf0, 0xf0, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srp 0(16,%r15), 0, 0" + + - + input: + bytes: [ 0xb2, 0x5e, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srst %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x5e, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srst %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x5e, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srst %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x5e, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srst %r7, %r8" + + - + input: + bytes: [ 0xb9, 0xbe, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srstu %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xbe, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srstu %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xbe, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srstu %r15, %r0" + + - + input: + bytes: [ 0xb9, 0xbe, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srstu %r7, %r8" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srxt %f0, %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srxt %f0, %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srxt %f0, %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srxt %f0, %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srxt %f0, %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srxt %f0, %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xd0, 0x00, 0x00, 0x00, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srxt %f0, %f13, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0xd0, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srxt %f13, %f0, 0" + + - + input: + bytes: [ 0xed, 0xd0, 0x00, 0x00, 0xd0, 0x49 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "srxt %f13, %f13, 0" + + - + input: + bytes: [ 0xb2, 0x25, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ssar %r0" + + - + input: + bytes: [ 0xb2, 0x25, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ssar %r1" + + - + input: + bytes: [ 0xb2, 0x25, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ssar %r15" + + - + input: + bytes: [ 0xb9, 0x9f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ssair %r0" + + - + input: + bytes: [ 0xb9, 0x9f, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ssair %r1" + + - + input: + bytes: [ 0xb9, 0x9f, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ssair %r15" + + - + input: + bytes: [ 0xb2, 0x33, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ssch 0" + + - + input: + bytes: [ 0xb2, 0x33, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ssch 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x33, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ssch 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x33, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ssch 4095" + + - + input: + bytes: [ 0xb2, 0x33, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ssch 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x33, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ssch 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0x2b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sske %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x2b, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sske %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x2b, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sske %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x2b, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sske %r0, %r0, 15" + + - + input: + bytes: [ 0xb2, 0x2b, 0x70, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sske %r4, %r6, 7" + + - + input: + bytes: [ 0x80, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ssm 0" + + - + input: + bytes: [ 0x80, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ssm 0(%r1)" + + - + input: + bytes: [ 0x80, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ssm 0(%r15)" + + - + input: + bytes: [ 0x80, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ssm 4095" + + - + input: + bytes: [ 0x80, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ssm 4095(%r1)" + + - + input: + bytes: [ 0x80, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ssm 4095(%r15)" + + - + input: + bytes: [ 0x50, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "st %r0, 0" + + - + input: + bytes: [ 0x50, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "st %r0, 4095" + + - + input: + bytes: [ 0x50, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "st %r0, 0(%r1)" + + - + input: + bytes: [ 0x50, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "st %r0, 0(%r15)" + + - + input: + bytes: [ 0x50, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "st %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x50, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "st %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x50, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "st %r15, 0" + + - + input: + bytes: [ 0x9b, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stam %a0, %a0, 0" + + - + input: + bytes: [ 0x9b, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stam %a0, %a15, 0" + + - + input: + bytes: [ 0x9b, 0xef, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stam %a14, %a15, 0" + + - + input: + bytes: [ 0x9b, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stam %a15, %a15, 0" + + - + input: + bytes: [ 0x9b, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stam %a0, %a0, 4095" + + - + input: + bytes: [ 0x9b, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stam %a0, %a0, 1" + + - + input: + bytes: [ 0x9b, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stam %a0, %a0, 0(%r1)" + + - + input: + bytes: [ 0x9b, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stam %a0, %a0, 0(%r15)" + + - + input: + bytes: [ 0x9b, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stam %a0, %a0, 4095(%r1)" + + - + input: + bytes: [ 0x9b, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stam %a0, %a0, 4095(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x9b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stamy %a0, %a0, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x9b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stamy %a0, %a15, 0" + + - + input: + bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x9b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stamy %a14, %a15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x9b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stamy %a15, %a15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x9b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stamy %a0, %a0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x9b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stamy %a0, %a0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x9b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stamy %a0, %a0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x9b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stamy %a0, %a0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x9b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stamy %a0, %a0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x9b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stamy %a0, %a0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x9b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stamy %a0, %a0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x9b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stamy %a0, %a0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x9b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stamy %a0, %a0, 524287(%r15)" + + - + input: + bytes: [ 0xb2, 0x12, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stap 0" + + - + input: + bytes: [ 0xb2, 0x12, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stap 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x12, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stap 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x12, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stap 4095" + + - + input: + bytes: [ 0xb2, 0x12, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stap 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x12, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stap 4095(%r15)" + + - + input: + bytes: [ 0x42, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stc %r0, 0" + + - + input: + bytes: [ 0x42, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stc %r0, 4095" + + - + input: + bytes: [ 0x42, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stc %r0, 0(%r1)" + + - + input: + bytes: [ 0x42, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stc %r0, 0(%r15)" + + - + input: + bytes: [ 0x42, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stc %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x42, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stc %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x42, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stc %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stch %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stch %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stch %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stch %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stch %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stch %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stch %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stch %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stch %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stch %r15, 0" + + - + input: + bytes: [ 0xb2, 0x05, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stck 0" + + - + input: + bytes: [ 0xb2, 0x05, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stck 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x05, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stck 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x05, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stck 4095" + + - + input: + bytes: [ 0xb2, 0x05, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stck 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x05, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stck 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0x07, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stckc 0" + + - + input: + bytes: [ 0xb2, 0x07, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stckc 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x07, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stckc 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x07, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stckc 4095" + + - + input: + bytes: [ 0xb2, 0x07, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stckc 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x07, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stckc 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0x78, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcke 0" + + - + input: + bytes: [ 0xb2, 0x78, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcke 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x78, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcke 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x78, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcke 4095" + + - + input: + bytes: [ 0xb2, 0x78, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcke 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x78, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcke 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0x7c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stckf 0" + + - + input: + bytes: [ 0xb2, 0x7c, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stckf 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x7c, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stckf 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x7c, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stckf 4095" + + - + input: + bytes: [ 0xb2, 0x7c, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stckf 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x7c, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stckf 4095(%r15)" + + - + input: + bytes: [ 0xbe, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcm %r0, 0, 0" + + - + input: + bytes: [ 0xbe, 0x0f, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcm %r0, 15, 4095" + + - + input: + bytes: [ 0xbe, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcm %r0, 0, 0(%r1)" + + - + input: + bytes: [ 0xbe, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcm %r0, 0, 0(%r15)" + + - + input: + bytes: [ 0xbe, 0x0f, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcm %r0, 15, 4095(%r15)" + + - + input: + bytes: [ 0xbe, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcm %r0, 0, 4095(%r1)" + + - + input: + bytes: [ 0xbe, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcm %r15, 0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x2c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmh %r0, 0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x2c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmh %r0, 0, -1" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x2c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmh %r0, 15, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x01, 0x00, 0x2c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmh %r0, 15, 1" + + - + input: + bytes: [ 0xeb, 0x08, 0x0f, 0xff, 0x7f, 0x2c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmh %r0, 8, 524287" + + - + input: + bytes: [ 0xeb, 0x08, 0x10, 0x00, 0x00, 0x2c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmh %r0, 8, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x04, 0xf0, 0x00, 0x00, 0x2c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmh %r0, 4, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x04, 0xff, 0xff, 0x7f, 0x2c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmh %r0, 4, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x2c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmh %r0, 0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0x2c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmh %r15, 0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x2d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmy %r0, 0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x2d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmy %r0, 0, -1" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x2d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmy %r0, 15, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x01, 0x00, 0x2d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmy %r0, 15, 1" + + - + input: + bytes: [ 0xeb, 0x08, 0x0f, 0xff, 0x7f, 0x2d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmy %r0, 8, 524287" + + - + input: + bytes: [ 0xeb, 0x08, 0x10, 0x00, 0x00, 0x2d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmy %r0, 8, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x04, 0xf0, 0x00, 0x00, 0x2d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmy %r0, 4, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x04, 0xff, 0xff, 0x7f, 0x2d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmy %r0, 4, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x2d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmy %r0, 0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0x2d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcmy %r15, 0, 0" + + - + input: + bytes: [ 0xb2, 0x3a, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcps 0" + + - + input: + bytes: [ 0xb2, 0x3a, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcps 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x3a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcps 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x3a, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcps 4095" + + - + input: + bytes: [ 0xb2, 0x3a, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcps 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x3a, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcps 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0x39, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcrw 0" + + - + input: + bytes: [ 0xb2, 0x39, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcrw 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x39, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcrw 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x39, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcrw 4095" + + - + input: + bytes: [ 0xb2, 0x39, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcrw 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x39, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcrw 4095(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctg %c0, %c0, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctg %c0, %c15, 0" + + - + input: + bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctg %c14, %c15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctg %c15, %c15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctg %c0, %c0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctg %c0, %c0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctg %c0, %c0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctg %c0, %c0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctg %c0, %c0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctg %c0, %c0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctg %c0, %c0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctg %c0, %c0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x25 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctg %c0, %c0, 524287(%r15)" + + - + input: + bytes: [ 0xb6, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctl %c0, %c0, 0" + + - + input: + bytes: [ 0xb6, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctl %c0, %c15, 0" + + - + input: + bytes: [ 0xb6, 0xef, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctl %c14, %c15, 0" + + - + input: + bytes: [ 0xb6, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctl %c15, %c15, 0" + + - + input: + bytes: [ 0xb6, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctl %c0, %c0, 4095" + + - + input: + bytes: [ 0xb6, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctl %c0, %c0, 1" + + - + input: + bytes: [ 0xb6, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctl %c0, %c0, 0(%r1)" + + - + input: + bytes: [ 0xb6, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctl %c0, %c0, 0(%r15)" + + - + input: + bytes: [ 0xb6, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctl %c0, %c0, 4095(%r1)" + + - + input: + bytes: [ 0xb6, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stctl %c0, %c0, 4095(%r15)" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcy %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcy %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcy %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcy %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcy %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcy %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcy %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcy %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcy %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x72 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stcy %r15, 0" + + - + input: + bytes: [ 0x60, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "std %f0, 0" + + - + input: + bytes: [ 0x60, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "std %f0, 4095" + + - + input: + bytes: [ 0x60, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "std %f0, 0(%r1)" + + - + input: + bytes: [ 0x60, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "std %f0, 0(%r15)" + + - + input: + bytes: [ 0x60, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "std %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x60, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "std %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x60, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "std %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x80, 0x67 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stdy %f0, -524288" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0xff, 0x67 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stdy %f0, -1" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x67 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stdy %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x01, 0x00, 0x67 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stdy %f0, 1" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x7f, 0x67 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stdy %f0, 524287" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x67 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stdy %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x67 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stdy %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x7f, 0x67 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stdy %f0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x7f, 0x67 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stdy %f0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x67 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stdy %f15, 0" + + - + input: + bytes: [ 0x70, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ste %f0, 0" + + - + input: + bytes: [ 0x70, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ste %f0, 4095" + + - + input: + bytes: [ 0x70, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ste %f0, 0(%r1)" + + - + input: + bytes: [ 0x70, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ste %f0, 0(%r15)" + + - + input: + bytes: [ 0x70, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ste %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x70, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ste %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x70, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ste %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x80, 0x66 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stey %f0, -524288" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0xff, 0x66 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stey %f0, -1" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x66 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stey %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x01, 0x00, 0x66 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stey %f0, 1" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x7f, 0x66 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stey %f0, 524287" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x66 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stey %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x66 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stey %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x7f, 0x66 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stey %f0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x7f, 0x66 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stey %f0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x66 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stey %f15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfh %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfh %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfh %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfh %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfh %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfh %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfh %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfh %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfh %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xcb ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfh %r15, 0" + + - + input: + bytes: [ 0xb2, 0xb1, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfl 0" + + - + input: + bytes: [ 0xb2, 0xb1, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfl 0(%r1)" + + - + input: + bytes: [ 0xb2, 0xb1, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfl 0(%r15)" + + - + input: + bytes: [ 0xb2, 0xb1, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfl 4095" + + - + input: + bytes: [ 0xb2, 0xb1, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfl 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0xb1, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfl 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0xb0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfle 0" + + - + input: + bytes: [ 0xb2, 0xb0, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfle 0(%r1)" + + - + input: + bytes: [ 0xb2, 0xb0, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfle 0(%r15)" + + - + input: + bytes: [ 0xb2, 0xb0, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfle 4095" + + - + input: + bytes: [ 0xb2, 0xb0, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfle 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0xb0, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfle 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0x9c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfpc 0" + + - + input: + bytes: [ 0xb2, 0x9c, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfpc 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x9c, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfpc 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x9c, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfpc 4095" + + - + input: + bytes: [ 0xb2, 0x9c, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfpc 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x9c, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stfpc 4095(%r15)" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stg %r15, 0" + + - + input: + bytes: [ 0x40, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sth %r0, 0" + + - + input: + bytes: [ 0x40, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sth %r0, 4095" + + - + input: + bytes: [ 0x40, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sth %r0, 0(%r1)" + + - + input: + bytes: [ 0x40, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sth %r0, 0(%r15)" + + - + input: + bytes: [ 0x40, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sth %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x40, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sth %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x40, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sth %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthh %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthh %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthh %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthh %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthh %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthh %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthh %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthh %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthh %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc7 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthh %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthy %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthy %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthy %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthy %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthy %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthy %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthy %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthy %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthy %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x70 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sthy %r15, 0" + + - + input: + bytes: [ 0xb2, 0x02, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stidp 0" + + - + input: + bytes: [ 0xb2, 0x02, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stidp 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x02, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stidp 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x02, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stidp 4095" + + - + input: + bytes: [ 0xb2, 0x02, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stidp 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x02, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stidp 4095(%r15)" + + - + input: + bytes: [ 0x90, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stm %r0, %r0, 0" + + - + input: + bytes: [ 0x90, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stm %r0, %r15, 0" + + - + input: + bytes: [ 0x90, 0xef, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stm %r14, %r15, 0" + + - + input: + bytes: [ 0x90, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stm %r15, %r15, 0" + + - + input: + bytes: [ 0x90, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stm %r0, %r0, 4095" + + - + input: + bytes: [ 0x90, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stm %r0, %r0, 1" + + - + input: + bytes: [ 0x90, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stm %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0x90, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stm %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0x90, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stm %r0, %r0, 4095(%r1)" + + - + input: + bytes: [ 0x90, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stm %r0, %r0, 4095(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmg %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmg %r14, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmg %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x24 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmg %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmh %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmh %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmh %r14, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmh %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmh %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmh %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmh %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmh %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmh %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmh %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmh %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmh %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x26 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmh %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmy %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmy %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmy %r14, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmy %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmy %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmy %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmy %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmy %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmy %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmy %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmy %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmy %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x90 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stmy %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0xac, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stnsm 0, 0" + + - + input: + bytes: [ 0xac, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stnsm 4095, 0" + + - + input: + bytes: [ 0xac, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stnsm 0, 255" + + - + input: + bytes: [ 0xac, 0x2a, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stnsm 0(%r1), 42" + + - + input: + bytes: [ 0xac, 0x2a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stnsm 0(%r15), 42" + + - + input: + bytes: [ 0xac, 0x2a, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stnsm 4095(%r1), 42" + + - + input: + bytes: [ 0xac, 0x2a, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stnsm 4095(%r15), 42" + + - + input: + bytes: [ 0xeb, 0x10, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stoc %r1, 2(%r3), 0" + + - + input: + bytes: [ 0xeb, 0x11, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stoco %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x12, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stoch %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x13, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocnle %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x14, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocl %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x15, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocnhe %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x16, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stoclh %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x17, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocne %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x18, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stoce %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x19, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocnlh %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x1a, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stoche %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x1b, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocnl %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x1c, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocle %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x1d, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocnh %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x1e, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocno %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x1f, 0x30, 0x02, 0x00, 0xf3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stoc %r1, 2(%r3), 15" + + - + input: + bytes: [ 0xeb, 0x10, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocg %r1, 2(%r3), 0" + + - + input: + bytes: [ 0xeb, 0x11, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocgo %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x12, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocgh %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x13, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocgnle %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x14, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocgl %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x15, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocgnhe %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x16, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocglh %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x17, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocgne %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x18, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocge %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x19, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocgnlh %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x1a, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocghe %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x1b, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocgnl %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x1c, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocgle %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x1d, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocgnh %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x1e, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocgno %r1, 2(%r3)" + + - + input: + bytes: [ 0xeb, 0x1f, 0x30, 0x02, 0x00, 0xe3 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stocg %r1, 2(%r3), 15" + + - + input: + bytes: [ 0xad, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stosm 0, 0" + + - + input: + bytes: [ 0xad, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stosm 4095, 0" + + - + input: + bytes: [ 0xad, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stosm 0, 255" + + - + input: + bytes: [ 0xad, 0x2a, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stosm 0(%r1), 42" + + - + input: + bytes: [ 0xad, 0x2a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stosm 0(%r15), 42" + + - + input: + bytes: [ 0xad, 0x2a, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stosm 4095(%r1), 42" + + - + input: + bytes: [ 0xad, 0x2a, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stosm 4095(%r15), 42" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpq %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpq %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpq %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpq %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpq %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpq %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpq %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpq %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpq %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x8e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpq %r14, 0" + + - + input: + bytes: [ 0xb2, 0x09, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpt 0" + + - + input: + bytes: [ 0xb2, 0x09, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpt 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x09, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpt 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x09, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpt 4095" + + - + input: + bytes: [ 0xb2, 0x09, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpt 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x09, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpt 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0x11, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpx 0" + + - + input: + bytes: [ 0xb2, 0x11, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpx 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x11, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpx 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x11, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpx 4095" + + - + input: + bytes: [ 0xb2, 0x11, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpx 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x11, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stpx 4095(%r15)" + + - + input: + bytes: [ 0xe5, 0x02, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strag 0, 0" + + - + input: + bytes: [ 0xe5, 0x02, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strag 0, 4095" + + - + input: + bytes: [ 0xe5, 0x02, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strag 0, 0(%r1)" + + - + input: + bytes: [ 0xe5, 0x02, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strag 0, 0(%r15)" + + - + input: + bytes: [ 0xe5, 0x02, 0x10, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strag 0(%r1), 4095(%r15)" + + - + input: + bytes: [ 0xe5, 0x02, 0x1f, 0xff, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strag 4095(%r1), 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strv %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strv %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strv %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strv %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strv %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strv %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strv %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strv %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strv %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x3e ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strv %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x2f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvg %r15, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvh %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvh %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvh %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvh %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvh %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvh %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvh %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvh %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvh %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x3f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "strvh %r15, 0" + + - + input: + bytes: [ 0xb2, 0x34, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stsch 0" + + - + input: + bytes: [ 0xb2, 0x34, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stsch 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x34, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stsch 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x34, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stsch 4095" + + - + input: + bytes: [ 0xb2, 0x34, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stsch 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x34, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stsch 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0x7d, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stsi 0" + + - + input: + bytes: [ 0xb2, 0x7d, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stsi 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x7d, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stsi 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x7d, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stsi 4095" + + - + input: + bytes: [ 0xb2, 0x7d, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stsi 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x7d, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stsi 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0x46, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stura %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x46, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stura %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x46, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stura %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x46, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "stura %r7, %r8" + + - + input: + bytes: [ 0xb9, 0x25, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sturg %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x25, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sturg %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x25, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sturg %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x25, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sturg %r7, %r8" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sty %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sty %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sty %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sty %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sty %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sty %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sty %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sty %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sty %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sty %r15, 0" + + - + input: + bytes: [ 0x7f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "su %f0, 0" + + - + input: + bytes: [ 0x7f, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "su %f0, 4095" + + - + input: + bytes: [ 0x7f, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "su %f0, 0(%r1)" + + - + input: + bytes: [ 0x7f, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "su %f0, 0(%r15)" + + - + input: + bytes: [ 0x7f, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "su %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x7f, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "su %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x7f, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "su %f15, 0" + + - + input: + bytes: [ 0x3f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sur %f0, %f0" + + - + input: + bytes: [ 0x3f, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sur %f0, %f15" + + - + input: + bytes: [ 0x3f, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sur %f7, %f8" + + - + input: + bytes: [ 0x3f, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sur %f15, %f0" + + - + input: + bytes: [ 0x0a, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "svc 0" + + - + input: + bytes: [ 0x0a, 0x03 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "svc 3" + + - + input: + bytes: [ 0x0a, 0x80 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "svc 128" + + - + input: + bytes: [ 0x0a, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "svc 255" + + - + input: + bytes: [ 0x6f, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sw %f0, 0" + + - + input: + bytes: [ 0x6f, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sw %f0, 4095" + + - + input: + bytes: [ 0x6f, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sw %f0, 0(%r1)" + + - + input: + bytes: [ 0x6f, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sw %f0, 0(%r15)" + + - + input: + bytes: [ 0x6f, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sw %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x6f, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sw %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x6f, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sw %f15, 0" + + - + input: + bytes: [ 0x2f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "swr %f0, %f0" + + - + input: + bytes: [ 0x2f, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "swr %f0, %f15" + + - + input: + bytes: [ 0x2f, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "swr %f7, %f8" + + - + input: + bytes: [ 0x2f, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "swr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x4b, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sxbr %f0, %f0" + + - + input: + bytes: [ 0xb3, 0x4b, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sxbr %f0, %f13" + + - + input: + bytes: [ 0xb3, 0x4b, 0x00, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sxbr %f8, %f8" + + - + input: + bytes: [ 0xb3, 0x4b, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sxbr %f13, %f0" + + - + input: + bytes: [ 0x37, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sxr %f0, %f0" + + - + input: + bytes: [ 0x37, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sxr %f0, %f13" + + - + input: + bytes: [ 0x37, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sxr %f8, %f8" + + - + input: + bytes: [ 0x37, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sxr %f13, %f0" + + - + input: + bytes: [ 0xb3, 0xdb, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sxtr %f0, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xdb, 0xd0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sxtr %f0, %f0, %f13" + + - + input: + bytes: [ 0xb3, 0xdb, 0x00, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sxtr %f0, %f13, %f0" + + - + input: + bytes: [ 0xb3, 0xdb, 0x00, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sxtr %f13, %f0, %f0" + + - + input: + bytes: [ 0xb3, 0xdb, 0x80, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sxtr %f8, %f8, %f8" + + - + input: + bytes: [ 0xb3, 0xdb, 0x01, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sxtra %f0, %f0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xdb, 0x0f, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sxtra %f0, %f0, %f0, 15" + + - + input: + bytes: [ 0xb3, 0xdb, 0xd1, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sxtra %f0, %f0, %f13, 1" + + - + input: + bytes: [ 0xb3, 0xdb, 0x01, 0x0d ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sxtra %f0, %f13, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xdb, 0x01, 0xd0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sxtra %f13, %f0, %f0, 1" + + - + input: + bytes: [ 0xb3, 0xdb, 0x88, 0x88 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sxtra %f8, %f8, %f8, 8" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x5b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sy %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x5b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sy %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x5b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sy %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x5b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sy %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x5b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sy %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x5b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sy %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x5b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sy %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x5b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sy %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x5b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sy %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x5b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "sy %r15, 0" + + - + input: + bytes: [ 0xb2, 0xfc, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tabort 0" + + - + input: + bytes: [ 0xb2, 0xfc, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tabort 0(%r1)" + + - + input: + bytes: [ 0xb2, 0xfc, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tabort 0(%r15)" + + - + input: + bytes: [ 0xb2, 0xfc, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tabort 4095" + + - + input: + bytes: [ 0xb2, 0xfc, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tabort 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0xfc, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tabort 4095(%r15)" + + - + input: + bytes: [ 0x01, 0x0b ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tam" + + - + input: + bytes: [ 0xb2, 0x4c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tar %a0, %r0" + + - + input: + bytes: [ 0xb2, 0x4c, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tar %a0, %r15" + + - + input: + bytes: [ 0xb2, 0x4c, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tar %a15, %r0" + + - + input: + bytes: [ 0xb2, 0x4c, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tar %a7, %r8" + + - + input: + bytes: [ 0xb2, 0x2c, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tb %r0, %r0" + + - + input: + bytes: [ 0xb2, 0x2c, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tb %r0, %r15" + + - + input: + bytes: [ 0xb2, 0x2c, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tb %r15, %r0" + + - + input: + bytes: [ 0xb2, 0x2c, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tb %r7, %r8" + + - + input: + bytes: [ 0xb2, 0x2c, 0x00, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tb %r15, %r15" + + - + input: + bytes: [ 0xb3, 0x51, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbdr %f0, 0, %f0" + + - + input: + bytes: [ 0xb3, 0x51, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbdr %f0, 0, %f15" + + - + input: + bytes: [ 0xb3, 0x51, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbdr %f0, 15, %f0" + + - + input: + bytes: [ 0xb3, 0x51, 0x50, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbdr %f4, 5, %f6" + + - + input: + bytes: [ 0xb3, 0x51, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbdr %f15, 0, %f0" + + - + input: + bytes: [ 0xb3, 0x50, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbedr %f0, 0, %f0" + + - + input: + bytes: [ 0xb3, 0x50, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbedr %f0, 0, %f15" + + - + input: + bytes: [ 0xb3, 0x50, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbedr %f0, 15, %f0" + + - + input: + bytes: [ 0xb3, 0x50, 0x50, 0x46 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbedr %f4, 5, %f6" + + - + input: + bytes: [ 0xb3, 0x50, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbedr %f15, 0, %f0" + + - + input: + bytes: [ 0xe5, 0x60, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbegin 0, 0" + + - + input: + bytes: [ 0xe5, 0x60, 0x0f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbegin 4095, 0" + + - + input: + bytes: [ 0xe5, 0x60, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbegin 0, 0" + + - + input: + bytes: [ 0xe5, 0x60, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbegin 0, 1" + + - + input: + bytes: [ 0xe5, 0x60, 0x00, 0x00, 0x7f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbegin 0, 32767" + + - + input: + bytes: [ 0xe5, 0x60, 0x00, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbegin 0, 32768" + + - + input: + bytes: [ 0xe5, 0x60, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbegin 0, 65535" + + - + input: + bytes: [ 0xe5, 0x60, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbegin 0(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x60, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbegin 0(%r15), 42" + + - + input: + bytes: [ 0xe5, 0x60, 0x1f, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbegin 4095(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x60, 0xff, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbegin 4095(%r15), 42" + + - + input: + bytes: [ 0xe5, 0x61, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbeginc 0, 0" + + - + input: + bytes: [ 0xe5, 0x61, 0x0f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbeginc 4095, 0" + + - + input: + bytes: [ 0xe5, 0x61, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbeginc 0, 0" + + - + input: + bytes: [ 0xe5, 0x61, 0x00, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbeginc 0, 1" + + - + input: + bytes: [ 0xe5, 0x61, 0x00, 0x00, 0x7f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbeginc 0, 32767" + + - + input: + bytes: [ 0xe5, 0x61, 0x00, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbeginc 0, 32768" + + - + input: + bytes: [ 0xe5, 0x61, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbeginc 0, 65535" + + - + input: + bytes: [ 0xe5, 0x61, 0x10, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbeginc 0(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x61, 0xf0, 0x00, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbeginc 0(%r15), 42" + + - + input: + bytes: [ 0xe5, 0x61, 0x1f, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbeginc 4095(%r1), 42" + + - + input: + bytes: [ 0xe5, 0x61, 0xff, 0xff, 0x00, 0x2a ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tbeginc 4095(%r15), 42" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x11 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tcdb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x11 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tcdb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x11 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tcdb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x11 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tcdb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x11 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tcdb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x11 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tcdb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x11 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tcdb %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tceb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tceb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tceb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tceb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tceb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tceb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x10 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tceb %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tcxb %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tcxb %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tcxb %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tcxb %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tcxb %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tcxb %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xd0, 0x00, 0x00, 0x00, 0x12 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tcxb %f13, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcdt %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcdt %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcdt %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcdt %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcdt %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcdt %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x54 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcdt %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcet %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcet %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcet %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcet %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcet %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcet %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x50 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcet %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcxt %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcxt %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcxt %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcxt %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcxt %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcxt %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xd0, 0x00, 0x00, 0x00, 0x58 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdcxt %f13, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdgdt %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdgdt %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdgdt %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdgdt %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdgdt %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdgdt %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x55 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdgdt %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdget %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdget %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdget %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdget %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdget %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdget %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdget %f15, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdgxt %f0, 0" + + - + input: + bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdgxt %f0, 4095" + + - + input: + bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdgxt %f0, 0(%r1)" + + - + input: + bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdgxt %f0, 0(%r15)" + + - + input: + bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdgxt %f0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdgxt %f0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0xed, 0xd0, 0x00, 0x00, 0x00, 0x59 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tdgxt %f13, 0" + + - + input: + bytes: [ 0xb2, 0xf8, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tend" + + - + input: + bytes: [ 0xb3, 0x58, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "thder %f0, %f9" + + - + input: + bytes: [ 0xb3, 0x58, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "thder %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x58, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "thder %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x58, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "thder %f15, %f9" + + - + input: + bytes: [ 0xb3, 0x59, 0x00, 0x09 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "thdr %f0, %f9" + + - + input: + bytes: [ 0xb3, 0x59, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "thdr %f0, %f15" + + - + input: + bytes: [ 0xb3, 0x59, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "thdr %f15, %f0" + + - + input: + bytes: [ 0xb3, 0x59, 0x00, 0xf9 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "thdr %f15, %f9" + + - + input: + bytes: [ 0x91, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tm 0, 0" + + - + input: + bytes: [ 0x91, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tm 4095, 0" + + - + input: + bytes: [ 0x91, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tm 0, 255" + + - + input: + bytes: [ 0x91, 0x2a, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tm 0(%r1), 42" + + - + input: + bytes: [ 0x91, 0x2a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tm 0(%r15), 42" + + - + input: + bytes: [ 0x91, 0x2a, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tm 4095(%r1), 42" + + - + input: + bytes: [ 0x91, 0x2a, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tm 4095(%r15), 42" + + - + input: + bytes: [ 0xa7, 0x02, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmhh %r0, 0" + + - + input: + bytes: [ 0xa7, 0x02, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmhh %r0, 32768" + + - + input: + bytes: [ 0xa7, 0x02, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmhh %r0, 65535" + + - + input: + bytes: [ 0xa7, 0xf2, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmhh %r15, 0" + + - + input: + bytes: [ 0xa7, 0x03, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmhl %r0, 0" + + - + input: + bytes: [ 0xa7, 0x03, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmhl %r0, 32768" + + - + input: + bytes: [ 0xa7, 0x03, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmhl %r0, 65535" + + - + input: + bytes: [ 0xa7, 0xf3, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmhl %r15, 0" + + - + input: + bytes: [ 0xa7, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmlh %r0, 0" + + - + input: + bytes: [ 0xa7, 0x00, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmlh %r0, 32768" + + - + input: + bytes: [ 0xa7, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmlh %r0, 65535" + + - + input: + bytes: [ 0xa7, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmlh %r15, 0" + + - + input: + bytes: [ 0xa7, 0x01, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmll %r0, 0" + + - + input: + bytes: [ 0xa7, 0x01, 0x80, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmll %r0, 32768" + + - + input: + bytes: [ 0xa7, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmll %r0, 65535" + + - + input: + bytes: [ 0xa7, 0xf1, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmll %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmy -524288, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmy -1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmy 0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmy 1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmy 524287, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmy 0, 255" + + - + input: + bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmy 0(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmy 0(%r15), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmy 524287(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x51 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tmy 524287(%r15), 42" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tp 0(1)" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tp 0(1,%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tp 0(1,%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x00, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tp 4095(1,%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x00, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tp 4095(1,%r15)" + + - + input: + bytes: [ 0xeb, 0xf0, 0x10, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tp 0(16,%r1)" + + - + input: + bytes: [ 0xeb, 0xf0, 0xf0, 0x00, 0x00, 0xc0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tp 0(16,%r15)" + + - + input: + bytes: [ 0xb2, 0x36, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tpi 0" + + - + input: + bytes: [ 0xb2, 0x36, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tpi 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x36, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tpi 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x36, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tpi 4095" + + - + input: + bytes: [ 0xb2, 0x36, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tpi 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x36, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tpi 4095(%r15)" + + - + input: + bytes: [ 0xe5, 0x01, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tprot 0, 0" + + - + input: + bytes: [ 0xe5, 0x01, 0x10, 0x00, 0x20, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tprot 0(%r1), 0(%r2)" + + - + input: + bytes: [ 0xe5, 0x01, 0x10, 0xa0, 0xf1, 0x40 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tprot 160(%r1), 320(%r15)" + + - + input: + bytes: [ 0xe5, 0x01, 0x10, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tprot 0(%r1), 4095" + + - + input: + bytes: [ 0xe5, 0x01, 0x10, 0x00, 0x2f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tprot 0(%r1), 4095(%r2)" + + - + input: + bytes: [ 0xe5, 0x01, 0x10, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tprot 0(%r1), 4095(%r15)" + + - + input: + bytes: [ 0xe5, 0x01, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tprot 0(%r1), 0" + + - + input: + bytes: [ 0xe5, 0x01, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tprot 0(%r15), 0" + + - + input: + bytes: [ 0xe5, 0x01, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tprot 4095(%r1), 0" + + - + input: + bytes: [ 0xe5, 0x01, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tprot 4095(%r15), 0" + + - + input: + bytes: [ 0xdc, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tr 0(1), 0" + + - + input: + bytes: [ 0xdc, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tr 0(1), 0(%r1)" + + - + input: + bytes: [ 0xdc, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tr 0(1), 0(%r15)" + + - + input: + bytes: [ 0xdc, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tr 0(1), 4095" + + - + input: + bytes: [ 0xdc, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tr 0(1), 4095(%r1)" + + - + input: + bytes: [ 0xdc, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tr 0(1), 4095(%r15)" + + - + input: + bytes: [ 0xdc, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tr 0(1,%r1), 0" + + - + input: + bytes: [ 0xdc, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tr 0(1,%r15), 0" + + - + input: + bytes: [ 0xdc, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tr 4095(1,%r1), 0" + + - + input: + bytes: [ 0xdc, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tr 4095(1,%r15), 0" + + - + input: + bytes: [ 0xdc, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tr 0(256,%r1), 0" + + - + input: + bytes: [ 0xdc, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tr 0(256,%r15), 0" + + - + input: + bytes: [ 0x99, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trace %r0, %r0, 0" + + - + input: + bytes: [ 0x99, 0x0f, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trace %r0, %r15, 0" + + - + input: + bytes: [ 0x99, 0xef, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trace %r14, %r15, 0" + + - + input: + bytes: [ 0x99, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trace %r15, %r15, 0" + + - + input: + bytes: [ 0x99, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trace %r0, %r0, 4095" + + - + input: + bytes: [ 0x99, 0x00, 0x00, 0x01 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trace %r0, %r0, 1" + + - + input: + bytes: [ 0x99, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trace %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0x99, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trace %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0x99, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trace %r0, %r0, 4095(%r1)" + + - + input: + bytes: [ 0x99, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trace %r0, %r0, 4095(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tracg %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tracg %r0, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tracg %r14, %r15, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tracg %r15, %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tracg %r0, %r0, -524288" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tracg %r0, %r0, -1" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tracg %r0, %r0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tracg %r0, %r0, 1" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tracg %r0, %r0, 524287" + + - + input: + bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tracg %r0, %r0, 0(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tracg %r0, %r0, 0(%r15)" + + - + input: + bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tracg %r0, %r0, 524287(%r1)" + + - + input: + bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tracg %r0, %r0, 524287(%r15)" + + - + input: + bytes: [ 0x01, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trap2" + + - + input: + bytes: [ 0xb2, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trap4 0" + + - + input: + bytes: [ 0xb2, 0xff, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trap4 0(%r1)" + + - + input: + bytes: [ 0xb2, 0xff, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trap4 0(%r15)" + + - + input: + bytes: [ 0xb2, 0xff, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trap4 4095" + + - + input: + bytes: [ 0xb2, 0xff, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trap4 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trap4 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0xa5, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tre %r0, %r0" + + - + input: + bytes: [ 0xb2, 0xa5, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tre %r0, %r15" + + - + input: + bytes: [ 0xb2, 0xa5, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tre %r14, %r0" + + - + input: + bytes: [ 0xb2, 0xa5, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tre %r6, %r8" + + - + input: + bytes: [ 0xb9, 0x93, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "troo %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x93, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "troo %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x93, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "troo %r14, %r0" + + - + input: + bytes: [ 0xb9, 0x93, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "troo %r6, %r8" + + - + input: + bytes: [ 0xb9, 0x93, 0x10, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "troo %r4, %r12, 1" + + - + input: + bytes: [ 0xb9, 0x93, 0xf0, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "troo %r4, %r12, 15" + + - + input: + bytes: [ 0xb9, 0x92, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trot %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x92, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trot %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x92, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trot %r14, %r0" + + - + input: + bytes: [ 0xb9, 0x92, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trot %r6, %r8" + + - + input: + bytes: [ 0xb9, 0x92, 0x10, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trot %r4, %r12, 1" + + - + input: + bytes: [ 0xb9, 0x92, 0xf0, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trot %r4, %r12, 15" + + - + input: + bytes: [ 0xdd, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trt 0(1), 0" + + - + input: + bytes: [ 0xdd, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trt 0(1), 0(%r1)" + + - + input: + bytes: [ 0xdd, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trt 0(1), 0(%r15)" + + - + input: + bytes: [ 0xdd, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trt 0(1), 4095" + + - + input: + bytes: [ 0xdd, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trt 0(1), 4095(%r1)" + + - + input: + bytes: [ 0xdd, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trt 0(1), 4095(%r15)" + + - + input: + bytes: [ 0xdd, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trt 0(1,%r1), 0" + + - + input: + bytes: [ 0xdd, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trt 0(1,%r15), 0" + + - + input: + bytes: [ 0xdd, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trt 4095(1,%r1), 0" + + - + input: + bytes: [ 0xdd, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trt 4095(1,%r15), 0" + + - + input: + bytes: [ 0xdd, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trt 0(256,%r1), 0" + + - + input: + bytes: [ 0xdd, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trt 0(256,%r15), 0" + + - + input: + bytes: [ 0xb9, 0xbf, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trte %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xbf, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trte %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xbf, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trte %r14, %r0" + + - + input: + bytes: [ 0xb9, 0xbf, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trte %r6, %r8" + + - + input: + bytes: [ 0xb9, 0xbf, 0x10, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trte %r4, %r12, 1" + + - + input: + bytes: [ 0xb9, 0xbf, 0xf0, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trte %r4, %r12, 15" + + - + input: + bytes: [ 0xb9, 0x91, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trto %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x91, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trto %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x91, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trto %r14, %r0" + + - + input: + bytes: [ 0xb9, 0x91, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trto %r6, %r8" + + - + input: + bytes: [ 0xb9, 0x91, 0x10, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trto %r4, %r12, 1" + + - + input: + bytes: [ 0xb9, 0x91, 0xf0, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trto %r4, %r12, 15" + + - + input: + bytes: [ 0xd0, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtr 0(1), 0" + + - + input: + bytes: [ 0xd0, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtr 0(1), 0(%r1)" + + - + input: + bytes: [ 0xd0, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtr 0(1), 0(%r15)" + + - + input: + bytes: [ 0xd0, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtr 0(1), 4095" + + - + input: + bytes: [ 0xd0, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtr 0(1), 4095(%r1)" + + - + input: + bytes: [ 0xd0, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtr 0(1), 4095(%r15)" + + - + input: + bytes: [ 0xd0, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtr 0(1,%r1), 0" + + - + input: + bytes: [ 0xd0, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtr 0(1,%r15), 0" + + - + input: + bytes: [ 0xd0, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtr 4095(1,%r1), 0" + + - + input: + bytes: [ 0xd0, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtr 4095(1,%r15), 0" + + - + input: + bytes: [ 0xd0, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtr 0(256,%r1), 0" + + - + input: + bytes: [ 0xd0, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtr 0(256,%r15), 0" + + - + input: + bytes: [ 0xb9, 0xbd, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtre %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xbd, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtre %r0, %r15" + + - + input: + bytes: [ 0xb9, 0xbd, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtre %r14, %r0" + + - + input: + bytes: [ 0xb9, 0xbd, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtre %r6, %r8" + + - + input: + bytes: [ 0xb9, 0xbd, 0x10, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtre %r4, %r12, 1" + + - + input: + bytes: [ 0xb9, 0xbd, 0xf0, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtre %r4, %r12, 15" + + - + input: + bytes: [ 0xb9, 0x90, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtt %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x90, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtt %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x90, 0x00, 0xe0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtt %r14, %r0" + + - + input: + bytes: [ 0xb9, 0x90, 0x00, 0x68 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtt %r6, %r8" + + - + input: + bytes: [ 0xb9, 0x90, 0x10, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtt %r4, %r12, 1" + + - + input: + bytes: [ 0xb9, 0x90, 0xf0, 0x4c ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "trtt %r4, %r12, 15" + + - + input: + bytes: [ 0x93, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ts 0" + + - + input: + bytes: [ 0x93, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ts 0(%r1)" + + - + input: + bytes: [ 0x93, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ts 0(%r15)" + + - + input: + bytes: [ 0x93, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ts 4095" + + - + input: + bytes: [ 0x93, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ts 4095(%r1)" + + - + input: + bytes: [ 0x93, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "ts 4095(%r15)" + + - + input: + bytes: [ 0xb2, 0x35, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tsch 0" + + - + input: + bytes: [ 0xb2, 0x35, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tsch 0(%r1)" + + - + input: + bytes: [ 0xb2, 0x35, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tsch 0(%r15)" + + - + input: + bytes: [ 0xb2, 0x35, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tsch 4095" + + - + input: + bytes: [ 0xb2, 0x35, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tsch 4095(%r1)" + + - + input: + bytes: [ 0xb2, 0x35, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "tsch 4095(%r15)" + + - + input: + bytes: [ 0xf3, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpk 0(1), 0(1)" + + - + input: + bytes: [ 0xf3, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpk 0(1), 0(1,%r1)" + + - + input: + bytes: [ 0xf3, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpk 0(1), 0(1,%r15)" + + - + input: + bytes: [ 0xf3, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpk 0(1), 4095(1)" + + - + input: + bytes: [ 0xf3, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpk 0(1), 4095(1,%r1)" + + - + input: + bytes: [ 0xf3, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpk 0(1), 4095(1,%r15)" + + - + input: + bytes: [ 0xf3, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpk 0(1,%r1), 0(1)" + + - + input: + bytes: [ 0xf3, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpk 0(1,%r15), 0(1)" + + - + input: + bytes: [ 0xf3, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpk 4095(1,%r1), 0(1)" + + - + input: + bytes: [ 0xf3, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpk 4095(1,%r15), 0(1)" + + - + input: + bytes: [ 0xf3, 0xf0, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpk 0(16,%r1), 0(1)" + + - + input: + bytes: [ 0xf3, 0xf0, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpk 0(16,%r15), 0(1)" + + - + input: + bytes: [ 0xf3, 0x0f, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpk 0(1), 0(16,%r1)" + + - + input: + bytes: [ 0xf3, 0x0f, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpk 0(1), 0(16,%r15)" + + - + input: + bytes: [ 0xea, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpka 0(1), 0" + + - + input: + bytes: [ 0xea, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpka 0(1), 0(%r1)" + + - + input: + bytes: [ 0xea, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpka 0(1), 0(%r15)" + + - + input: + bytes: [ 0xea, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpka 0(1), 4095" + + - + input: + bytes: [ 0xea, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpka 0(1), 4095(%r1)" + + - + input: + bytes: [ 0xea, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpka 0(1), 4095(%r15)" + + - + input: + bytes: [ 0xea, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpka 0(1,%r1), 0" + + - + input: + bytes: [ 0xea, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpka 0(1,%r15), 0" + + - + input: + bytes: [ 0xea, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpka 4095(1,%r1), 0" + + - + input: + bytes: [ 0xea, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpka 4095(1,%r15), 0" + + - + input: + bytes: [ 0xea, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpka 0(256,%r1), 0" + + - + input: + bytes: [ 0xea, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpka 0(256,%r15), 0" + + - + input: + bytes: [ 0xe2, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpku 0(1), 0" + + - + input: + bytes: [ 0xe2, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpku 0(1), 0(%r1)" + + - + input: + bytes: [ 0xe2, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpku 0(1), 0(%r15)" + + - + input: + bytes: [ 0xe2, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpku 0(1), 4095" + + - + input: + bytes: [ 0xe2, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpku 0(1), 4095(%r1)" + + - + input: + bytes: [ 0xe2, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpku 0(1), 4095(%r15)" + + - + input: + bytes: [ 0xe2, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpku 0(1,%r1), 0" + + - + input: + bytes: [ 0xe2, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpku 0(1,%r15), 0" + + - + input: + bytes: [ 0xe2, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpku 4095(1,%r1), 0" + + - + input: + bytes: [ 0xe2, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpku 4095(1,%r15), 0" + + - + input: + bytes: [ 0xe2, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpku 0(256,%r1), 0" + + - + input: + bytes: [ 0xe2, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "unpku 0(256,%r15), 0" + + - + input: + bytes: [ 0x01, 0x02 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "upt" + + - + input: + bytes: [ 0x57, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "x %r0, 0" + + - + input: + bytes: [ 0x57, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "x %r0, 4095" + + - + input: + bytes: [ 0x57, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "x %r0, 0(%r1)" + + - + input: + bytes: [ 0x57, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "x %r0, 0(%r15)" + + - + input: + bytes: [ 0x57, 0x01, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "x %r0, 4095(%r1,%r15)" + + - + input: + bytes: [ 0x57, 0x0f, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "x %r0, 4095(%r15,%r1)" + + - + input: + bytes: [ 0x57, 0xf0, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "x %r15, 0" + + - + input: + bytes: [ 0xd7, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xc 0(1), 0" + + - + input: + bytes: [ 0xd7, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xc 0(1), 0(%r1)" + + - + input: + bytes: [ 0xd7, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xc 0(1), 0(%r15)" + + - + input: + bytes: [ 0xd7, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xc 0(1), 4095" + + - + input: + bytes: [ 0xd7, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xc 0(1), 4095(%r1)" + + - + input: + bytes: [ 0xd7, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xc 0(1), 4095(%r15)" + + - + input: + bytes: [ 0xd7, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xc 0(1,%r1), 0" + + - + input: + bytes: [ 0xd7, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xc 0(1,%r15), 0" + + - + input: + bytes: [ 0xd7, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xc 4095(1,%r1), 0" + + - + input: + bytes: [ 0xd7, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xc 4095(1,%r15), 0" + + - + input: + bytes: [ 0xd7, 0xff, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xc 0(256,%r1), 0" + + - + input: + bytes: [ 0xd7, 0xff, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xc 0(256,%r15), 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xg %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xg %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xg %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xg %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xg %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xg %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xg %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xg %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xg %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x82 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xg %r15, 0" + + - + input: + bytes: [ 0xb9, 0x82, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xgr %r0, %r0" + + - + input: + bytes: [ 0xb9, 0x82, 0x00, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xgr %r0, %r15" + + - + input: + bytes: [ 0xb9, 0x82, 0x00, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xgr %r15, %r0" + + - + input: + bytes: [ 0xb9, 0x82, 0x00, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xgr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0xe7, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xgrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xe7, 0x40, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xgrk %r2, %r3, %r4" + + - + input: + bytes: [ 0x97, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xi 0, 0" + + - + input: + bytes: [ 0x97, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xi 4095, 0" + + - + input: + bytes: [ 0x97, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xi 0, 255" + + - + input: + bytes: [ 0x97, 0x2a, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xi 0(%r1), 42" + + - + input: + bytes: [ 0x97, 0x2a, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xi 0(%r15), 42" + + - + input: + bytes: [ 0x97, 0x2a, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xi 4095(%r1), 42" + + - + input: + bytes: [ 0x97, 0x2a, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xi 4095(%r15), 42" + + - + input: + bytes: [ 0xc0, 0x06, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xihf %r0, 0" + + - + input: + bytes: [ 0xc0, 0x06, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xihf %r0, 4294967295" + + - + input: + bytes: [ 0xc0, 0xf6, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xihf %r15, 0" + + - + input: + bytes: [ 0xc0, 0x07, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xilf %r0, 0" + + - + input: + bytes: [ 0xc0, 0x07, 0xff, 0xff, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xilf %r0, 4294967295" + + - + input: + bytes: [ 0xc0, 0xf7, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xilf %r15, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xiy -524288, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xiy -1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xiy 0, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xiy 1, 0" + + - + input: + bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xiy 524287, 0" + + - + input: + bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xiy 0, 255" + + - + input: + bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xiy 0(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xiy 0(%r15), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xiy 524287(%r1), 42" + + - + input: + bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xiy 524287(%r15), 42" + + - + input: + bytes: [ 0x17, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xr %r0, %r0" + + - + input: + bytes: [ 0x17, 0x0f ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xr %r0, %r15" + + - + input: + bytes: [ 0x17, 0xf0 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xr %r15, %r0" + + - + input: + bytes: [ 0x17, 0x78 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xr %r7, %r8" + + - + input: + bytes: [ 0xb9, 0xf7, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xrk %r0, %r0, %r0" + + - + input: + bytes: [ 0xb9, 0xf7, 0x40, 0x23 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xrk %r2, %r3, %r4" + + - + input: + bytes: [ 0xb2, 0x76, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xsch" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xy %r0, -524288" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xy %r0, -1" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xy %r0, 0" + + - + input: + bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xy %r0, 1" + + - + input: + bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xy %r0, 524287" + + - + input: + bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xy %r0, 0(%r1)" + + - + input: + bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xy %r0, 0(%r15)" + + - + input: + bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xy %r0, 524287(%r1,%r15)" + + - + input: + bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xy %r0, 524287(%r15,%r1)" + + - + input: + bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x57 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "xy %r15, 0" + + - + input: + bytes: [ 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "zap 0(1), 0(1)" + + - + input: + bytes: [ 0xf8, 0x00, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "zap 0(1), 0(1,%r1)" + + - + input: + bytes: [ 0xf8, 0x00, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "zap 0(1), 0(1,%r15)" + + - + input: + bytes: [ 0xf8, 0x00, 0x00, 0x00, 0x0f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "zap 0(1), 4095(1)" + + - + input: + bytes: [ 0xf8, 0x00, 0x00, 0x00, 0x1f, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "zap 0(1), 4095(1,%r1)" + + - + input: + bytes: [ 0xf8, 0x00, 0x00, 0x00, 0xff, 0xff ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "zap 0(1), 4095(1,%r15)" + + - + input: + bytes: [ 0xf8, 0x00, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "zap 0(1,%r1), 0(1)" + + - + input: + bytes: [ 0xf8, 0x00, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "zap 0(1,%r15), 0(1)" + + - + input: + bytes: [ 0xf8, 0x00, 0x1f, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "zap 4095(1,%r1), 0(1)" + + - + input: + bytes: [ 0xf8, 0x00, 0xff, 0xff, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "zap 4095(1,%r15), 0(1)" + + - + input: + bytes: [ 0xf8, 0xf0, 0x10, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "zap 0(16,%r1), 0(1)" + + - + input: + bytes: [ 0xf8, 0xf0, 0xf0, 0x00, 0x00, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "zap 0(16,%r15), 0(1)" + + - + input: + bytes: [ 0xf8, 0x0f, 0x00, 0x00, 0x10, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "zap 0(1), 0(16,%r1)" + + - + input: + bytes: [ 0xf8, 0x0f, 0x00, 0x00, 0xf0, 0x00 ] + arch: "CS_ARCH_SYSTEMZ" + options: [ "s390x-linux-gnu", "zEC12", "CS_MODE_BIG_ENDIAN" ] + expected: + insns: + - + asm_text: "zap 0(1), 0(16,%r15)" diff --git a/tests/MC/SystemZ/regs-good.s.yaml b/tests/MC/SystemZ/regs-good.s.yaml deleted file mode 100644 index cec0be83f2..0000000000 --- a/tests/MC/SystemZ/regs-good.s.yaml +++ /dev/null @@ -1,397 +0,0 @@ -test_cases: - - - input: - bytes: [ 0x18, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lr %r0, %r1" - - - input: - bytes: [ 0x18, 0x23 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lr %r2, %r3" - - - input: - bytes: [ 0x18, 0x45 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lr %r4, %r5" - - - input: - bytes: [ 0x18, 0x67 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lr %r6, %r7" - - - input: - bytes: [ 0x18, 0x89 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lr %r8, %r9" - - - input: - bytes: [ 0x18, 0xab ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lr %r10, %r11" - - - input: - bytes: [ 0x18, 0xcd ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lr %r12, %r13" - - - input: - bytes: [ 0x18, 0xef ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lr %r14, %r15" - - - input: - bytes: [ 0xb9, 0x04, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgr %r0, %r1" - - - input: - bytes: [ 0xb9, 0x04, 0x00, 0x23 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgr %r2, %r3" - - - input: - bytes: [ 0xb9, 0x04, 0x00, 0x45 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgr %r4, %r5" - - - input: - bytes: [ 0xb9, 0x04, 0x00, 0x67 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgr %r6, %r7" - - - input: - bytes: [ 0xb9, 0x04, 0x00, 0x89 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgr %r8, %r9" - - - input: - bytes: [ 0xb9, 0x04, 0x00, 0xab ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgr %r10, %r11" - - - input: - bytes: [ 0xb9, 0x04, 0x00, 0xcd ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgr %r12, %r13" - - - input: - bytes: [ 0xb9, 0x04, 0x00, 0xef ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lgr %r14, %r15" - - - input: - bytes: [ 0xb9, 0x97, 0x00, 0x00 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlr %r0, %r0" - - - input: - bytes: [ 0xb9, 0x97, 0x00, 0x20 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlr %r2, %r0" - - - input: - bytes: [ 0xb9, 0x97, 0x00, 0x40 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlr %r4, %r0" - - - input: - bytes: [ 0xb9, 0x97, 0x00, 0x60 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlr %r6, %r0" - - - input: - bytes: [ 0xb9, 0x97, 0x00, 0x80 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlr %r8, %r0" - - - input: - bytes: [ 0xb9, 0x97, 0x00, 0xa0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlr %r10, %r0" - - - input: - bytes: [ 0xb9, 0x97, 0x00, 0xc0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlr %r12, %r0" - - - input: - bytes: [ 0xb9, 0x97, 0x00, 0xe0 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "dlr %r14, %r0" - - - input: - bytes: [ 0x38, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ler %f0, %f1" - - - input: - bytes: [ 0x38, 0x23 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ler %f2, %f3" - - - input: - bytes: [ 0x38, 0x45 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ler %f4, %f5" - - - input: - bytes: [ 0x38, 0x67 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ler %f6, %f7" - - - input: - bytes: [ 0x38, 0x89 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ler %f8, %f9" - - - input: - bytes: [ 0x38, 0xab ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ler %f10, %f11" - - - input: - bytes: [ 0x38, 0xcd ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ler %f12, %f13" - - - input: - bytes: [ 0x38, 0xef ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ler %f14, %f15" - - - input: - bytes: [ 0x28, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldr %f0, %f1" - - - input: - bytes: [ 0x28, 0x23 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldr %f2, %f3" - - - input: - bytes: [ 0x28, 0x45 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldr %f4, %f5" - - - input: - bytes: [ 0x28, 0x67 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldr %f6, %f7" - - - input: - bytes: [ 0x28, 0x89 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldr %f8, %f9" - - - input: - bytes: [ 0x28, 0xab ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldr %f10, %f11" - - - input: - bytes: [ 0x28, 0xcd ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldr %f12, %f13" - - - input: - bytes: [ 0x28, 0xef ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "ldr %f14, %f15" - - - input: - bytes: [ 0xb3, 0x65, 0x00, 0x01 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lxr %f0, %f1" - - - input: - bytes: [ 0xb3, 0x65, 0x00, 0x45 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lxr %f4, %f5" - - - input: - bytes: [ 0xb3, 0x65, 0x00, 0x89 ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lxr %f8, %f9" - - - input: - bytes: [ 0xb3, 0x65, 0x00, 0xcd ] - arch: "CS_ARCH_SYSZ" - options: [ ] - expected: - insns: - - - asm_text: "lxr %f12, %f13" diff --git a/tests/details/cs_common_details.yaml b/tests/details/cs_common_details.yaml index 3ed8537eb1..b9803d2091 100644 --- a/tests/details/cs_common_details.yaml +++ b/tests/details/cs_common_details.yaml @@ -722,8 +722,8 @@ test_cases: - input: bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x5a, 0x0f, 0x1f, 0xff, 0xc2, 0x09, 0x80, 0x00, 0x00, 0x00, 0x07, 0xf7, 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x57, 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x57, 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x24, 0xb2, 0x4f, 0x00, 0x78 ] - arch: "CS_ARCH_SYSZ" - options: [ CS_OPT_DETAIL ] + arch: "CS_ARCH_SYSTEMZ" + options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ] address: 0x1000 expected: insns: @@ -734,9 +734,9 @@ test_cases: details: regs_impl_write: [ cc ] - - asm_text: "a %r0, 0xfff(%r15, %r1)" + asm_text: "a %r0, 0xfff(%r15,%r1)" mnemonic: "a" - op_str: "%r0, 0xfff(%r15, %r1)" + op_str: "%r0, 0xfff(%r15,%r1)" details: regs_impl_write: [ cc ] - @@ -758,9 +758,9 @@ test_cases: details: regs_impl_write: [ cc ] - - asm_text: "xy %r0, 0x7ffff(%r1, %r15)" + asm_text: "xy %r0, 0x7ffff(%r1,%r15)" mnemonic: "xy" - op_str: "%r0, 0x7ffff(%r1, %r15)" + op_str: "%r0, 0x7ffff(%r1,%r15)" details: regs_impl_write: [ cc ] - diff --git a/tests/details/systemz.yaml b/tests/details/systemz.yaml index da96cbe659..52579fd8a1 100644 --- a/tests/details/systemz.yaml +++ b/tests/details/systemz.yaml @@ -2,8 +2,8 @@ test_cases: - input: bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x5a, 0x0f, 0x1f, 0xff, 0xc2, 0x09, 0x80, 0x00, 0x00, 0x00, 0x07, 0xf7, 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x57, 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x57, 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x24, 0xb2, 0x4f, 0x00, 0x78, 0xec, 0x18, 0x00, 0x00, 0xc1, 0x7f ] - arch: "CS_ARCH_SYSZ" - options: [ CS_OPT_DETAIL ] + arch: "CS_ARCH_SYSTEMZ" + options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_SYSTEMZ_ARCH14 ] address: 0x1000 expected: insns: @@ -13,23 +13,24 @@ test_cases: systemz: operands: - - type: SYSZ_OP_REG + type: SYSTEMZ_OP_REG reg: f0 - - type: SYSZ_OP_IMM - imm: 0x0 + type: SYSTEMZ_OP_MEM + mem_am: SYSTEMZ_AM_BDX + mem_disp: 0x0 - - asm_text: "a %r0, 0xfff(%r15, %r1)" + asm_text: "a %r0, 0xfff(%r15,%r1)" details: systemz: operands: - - type: SYSZ_OP_REG - reg: "0" + type: SYSTEMZ_OP_REG + reg: "r0" - - type: SYSZ_OP_MEM - mem_base: "1" - mem_index: "15" + type: SYSTEMZ_OP_MEM + mem_base: "r1" + mem_index: "r15" mem_disp: 0xfff - asm_text: "afi %r0, -0x80000000" @@ -37,10 +38,11 @@ test_cases: systemz: operands: - - type: SYSZ_OP_REG - reg: "0" + type: SYSTEMZ_OP_REG + reg: "r0" - - type: SYSZ_OP_IMM + type: SYSTEMZ_OP_IMM + imm_width: 32 imm: -0x80000000 - asm_text: "br %r7" @@ -48,32 +50,33 @@ test_cases: systemz: operands: - - type: SYSZ_OP_REG - reg: "7" + type: SYSTEMZ_OP_REG + reg: "r7" - asm_text: "xiy 0x7ffff(%r15), 0x2a" details: systemz: operands: - - type: SYSZ_OP_MEM - mem_base: "15" + type: SYSTEMZ_OP_MEM + mem_base: "r15" mem_disp: 0x7ffff - - type: SYSZ_OP_IMM + type: SYSTEMZ_OP_IMM + imm_width: 8 imm: 0x2a - - asm_text: "xy %r0, 0x7ffff(%r1, %r15)" + asm_text: "xy %r0, 0x7ffff(%r1,%r15)" details: systemz: operands: - - type: SYSZ_OP_REG - reg: "0" + type: SYSTEMZ_OP_REG + reg: "r0" - - type: SYSZ_OP_MEM - mem_base: "15" - mem_index: "1" + type: SYSTEMZ_OP_MEM + mem_base: "r15" + mem_index: "r1" mem_disp: 0x7ffff - asm_text: "stmg %r0, %r0, 0(%r15)" @@ -81,24 +84,24 @@ test_cases: systemz: operands: - - type: SYSZ_OP_REG - reg: "0" + type: SYSTEMZ_OP_REG + reg: "r0" - - type: SYSZ_OP_REG - reg: "0" + type: SYSTEMZ_OP_REG + reg: "r0" - - type: SYSZ_OP_MEM - mem_base: "15" + type: SYSTEMZ_OP_MEM + mem_base: "r15" - asm_text: "ear %r7, %a8" details: systemz: operands: - - type: SYSZ_OP_REG - reg: "7" + type: SYSTEMZ_OP_REG + reg: "r7" - - type: SYSZ_OP_REG + type: SYSTEMZ_OP_REG reg: a8 - asm_text: "clije %r1, 0xc1, 0x1028" @@ -106,12 +109,13 @@ test_cases: systemz: operands: - - type: SYSZ_OP_REG - reg: "1" + type: SYSTEMZ_OP_REG + reg: "r1" - - type: SYSZ_OP_IMM + type: SYSTEMZ_OP_IMM + imm_width: 8 imm: 0xc1 - - type: SYSZ_OP_IMM + type: SYSTEMZ_OP_IMM + imm_width: 0 imm: 0x1028 - diff --git a/tests/integration/CMakeLists.txt b/tests/integration/CMakeLists.txt index 4aee948202..20e94b12c5 100644 --- a/tests/integration/CMakeLists.txt +++ b/tests/integration/CMakeLists.txt @@ -15,3 +15,20 @@ if (CAPSTONE_BUILD_LEGACY_TESTS) add_test(NAME "legacy_${TBIN}" COMMAND ${TBIN}) endforeach() endif() + +# Compatibility header test +set(COMPAT_C_TEST_DIR ${TESTS_INTEGRATION_DIR}/compat_header) +set(COMPAT_C_TEST_SRC_DIR ${COMPAT_C_TEST_DIR}/src) +set(COMPAT_C_TEST_INC_DIR ${COMPAT_C_TEST_DIR}/include) + +include_directories(${COMPAT_C_TEST_INC_DIR} ${PROJECT_SOURCE_DIR}/include) + +file(GLOB COMPAT_C_SRC ${COMPAT_C_TEST_SRC_DIR}/*.c) +add_executable(compat_header_build_test ${COMPAT_C_SRC}) +add_dependencies(compat_header_build_test capstone) +target_link_libraries(compat_header_build_test PUBLIC capstone) + +add_test(NAME integration_compat_headers + COMMAND compat_header_build_test + WORKING_DIRECTORY ${COMPAT_C_TEST_DIR} +) diff --git a/suite/auto-sync/c_tests/README.md b/tests/integration/compat_header/README.md similarity index 100% rename from suite/auto-sync/c_tests/README.md rename to tests/integration/compat_header/README.md diff --git a/tests/integration/compat_header/include/compat.h b/tests/integration/compat_header/include/compat.h new file mode 100644 index 0000000000..3dd5b69fcc --- /dev/null +++ b/tests/integration/compat_header/include/compat.h @@ -0,0 +1,5 @@ +// SPDX-FileCopyrightText: 2024 Rot127 +// SPDX-License-Identifier: BSD-3.0-Clause + +int arm64(void); +int sysz(void); diff --git a/tests/integration/compat_header/src/main.c b/tests/integration/compat_header/src/main.c new file mode 100644 index 0000000000..06f5358487 --- /dev/null +++ b/tests/integration/compat_header/src/main.c @@ -0,0 +1,16 @@ +// SPDX-FileCopyrightText: 2024 Rot127 +// SPDX-License-Identifier: BSD-3.0-Clause + +#include "compat.h" +#include + +int main() { + if (arm64() != 0) { + printf("Failed the arm64 compatibility header test.\n"); + return -1; + } + if (sysz() != 0) { + printf("Failed the sysz compatibility header test.\n"); + return -1; + } +} diff --git a/suite/auto-sync/c_tests/src/test_arm64_compatibility_header.c b/tests/integration/compat_header/src/test_arm64_compatibility_header.c similarity index 92% rename from suite/auto-sync/c_tests/src/test_arm64_compatibility_header.c rename to tests/integration/compat_header/src/test_arm64_compatibility_header.c index d1ddb86440..8dcf866050 100644 --- a/suite/auto-sync/c_tests/src/test_arm64_compatibility_header.c +++ b/tests/integration/compat_header/src/test_arm64_compatibility_header.c @@ -7,8 +7,9 @@ #define CAPSTONE_AARCH64_COMPAT_HEADER #include -int main(void) +int arm64(void) { + printf("\nARM64\n\n"); csh handle; if (cs_open(CS_ARCH_ARM64, CS_MODE_BIG_ENDIAN, &handle) != CS_ERR_OK) { @@ -19,7 +20,7 @@ int main(void) cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); cs_insn *insn; - uint8_t bytes[] = "0x1a,0x48,0xa0,0xf8"; + uint8_t bytes[] = { 0x30, 0x78, 0x31, 0x61 }; size_t count = cs_disasm(handle, bytes, sizeof(bytes), 0x1000, 1, &insn); if (count != 1) { @@ -65,3 +66,5 @@ int main(void) cs_close(&handle); return -1; } + +#undef CAPSTONE_AARCH64_COMPAT_HEADER diff --git a/tests/integration/compat_header/src/test_sysz_compatibility_header.c b/tests/integration/compat_header/src/test_sysz_compatibility_header.c new file mode 100644 index 0000000000..860976d7a2 --- /dev/null +++ b/tests/integration/compat_header/src/test_sysz_compatibility_header.c @@ -0,0 +1,100 @@ +// SPDX-FileCopyrightText: 2024 Rot127 +// SPDX-License-Identifier: BSD-3.0-Clause + +#include +#include + +#define CAPSTONE_SYSTEMZ_COMPAT_HEADER +#include + + // 0 5a 0f 1f ff a %r0, 0xfff(%r15,%r1) + // ID: 1 (a) + // op_count: 2 + // operands[0].type: REG = r0 + // operands[0].access: WRITE + // operands[1].type: MEM + // operands[1].mem.base: REG = r1 + // operands[1].mem.index: REG = r15 + // operands[1].mem.disp: 0xfff + // operands[1].mem.am: SYSTEMZ_AM_BDX + // operands[1].access: READ + + +int sysz(void) +{ + printf("\nSYSZ\n\n"); + csh handle; + + if (cs_open(CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN, &handle) != CS_ERR_OK) { + fprintf(stderr, "cs_open failed\n"); + return -1; + } + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + cs_insn *insn; + uint8_t bytes[] = { 0x5a, 0x0f, 0x1f, 0xff }; + size_t count = + cs_disasm(handle, bytes, sizeof(bytes), 0x1000, 1, &insn); + if (count != 1) { + fprintf(stderr, "Failed to disassemble code.\n"); + goto err; + } + printf("0x%" PRIx64 ":\t%s\t\t%s\n", insn[0].address, insn[0].mnemonic, + insn[0].op_str); + printf("A register = %s\n", + cs_reg_name(handle, insn[0].detail->sysz.operands[0].reg)); + printf("An mem am = %" PRId32 "\n", + insn[0].detail->sysz.operands[1].mem.am); + printf("An mem disp = %" PRId64 "\n", + insn[0].detail->sysz.operands[1].mem.disp); + printf("Mem base = %s\n", + cs_reg_name(handle, insn[0].detail->sysz.operands[1].mem.base)); + printf("Mem index = %s\n", + cs_reg_name(handle, insn[0].detail->sysz.operands[1].mem.index)); + + if (insn[0].address != 0x1000) { + fprintf(stderr, "Address wrong.\n"); + goto err; + } + if (strcmp(insn[0].mnemonic, "a") != 0) { + fprintf(stderr, "Mnemonic wrong.\n"); + goto err; + } + if (strcmp(insn[0].op_str, "%r0, 0xfff(%r15,%r1)") != 0) { + fprintf(stderr, "op_str wrong.\n"); + goto err; + } + if (strcmp(cs_reg_name(handle, insn[0].detail->sysz.operands[0].reg), + "r0") != 0) { + fprintf(stderr, "register wrong.\n"); + goto err; + } + if (((sysz_addr_mode) insn[0].detail->sysz.operands[1].mem.am) != SYSZ_AM_BDX) { + fprintf(stderr, "mem.am wrong\n"); + goto err; + } + if (insn[0].detail->sysz.operands[1].mem.disp != 0xfff) { + fprintf(stderr, "mem.disp wrong\n"); + goto err; + } + if (strcmp(cs_reg_name(handle, insn[0].detail->sysz.operands[1].mem.base), "r1") != 0) { + fprintf(stderr, "mem.base wrong\n"); + goto err; + } + if (strcmp(cs_reg_name(handle, insn[0].detail->sysz.operands[1].mem.index), "r15") != 0) { + fprintf(stderr, "mem.index wrong\n"); + goto err; + } + + cs_free(insn, count); + cs_close(&handle); + return 0; + +err: + printf("ERROR: Failed to disassemble given code corrcetly!\n"); + cs_free(insn, count); + cs_close(&handle); + return -1; +} +#undef CAPSTONE_SYSTEMZ_COMPAT_HEADER diff --git a/tests/integration/test_iter.c b/tests/integration/test_iter.c index 172d2c6a39..ec611fe523 100644 --- a/tests/integration/test_iter.c +++ b/tests/integration/test_iter.c @@ -56,8 +56,8 @@ static void test() #define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" #define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" #endif -#ifdef CAPSTONE_HAS_SYSZ -#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78" +#ifdef CAPSTONE_HAS_SYSTEMZ +#define SYSTEMZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78" #endif #ifdef CAPSTONE_HAS_XCORE #define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10" @@ -204,12 +204,12 @@ struct platform platforms[] = { "SparcV9" }, #endif -#ifdef CAPSTONE_HAS_SYSZ +#ifdef CAPSTONE_HAS_SYSTEMZ { - CS_ARCH_SYSZ, - (cs_mode)0, - (unsigned char*)SYSZ_CODE, - sizeof(SYSZ_CODE) - 1, + CS_ARCH_SYSTEMZ, + (cs_mode)CS_MODE_BIG_ENDIAN, + (unsigned char*)SYSTEMZ_CODE, + sizeof(SYSTEMZ_CODE) - 1, "SystemZ" }, #endif diff --git a/tests/unit/CMakeLists.txt b/tests/unit/CMakeLists.txt index e69de29bb2..2718f594f3 100644 --- a/tests/unit/CMakeLists.txt +++ b/tests/unit/CMakeLists.txt @@ -0,0 +1,14 @@ +cmake_minimum_required(VERSION 3.15) + +# Old integration tests. +if (CAPSTONE_BUILD_LEGACY_TESTS) + enable_testing() + set(UNIT_TEST_SOURCES sstream.c) + + foreach(TSRC ${UNIT_TEST_SOURCES}) + string(REGEX REPLACE ".c$" "" TBIN ${TSRC}) + add_executable(${TBIN} "${TESTS_UNIT_DIR}/${TSRC}") + target_link_libraries(${TBIN} PRIVATE capstone) + add_test(NAME "unit_${TBIN}" COMMAND ${TBIN}) + endforeach() +endif() diff --git a/tests/unit/sstream.c b/tests/unit/sstream.c new file mode 100644 index 0000000000..c4f158b6c2 --- /dev/null +++ b/tests/unit/sstream.c @@ -0,0 +1,347 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "../SStream.h" +#include "../utils.h" +#include +#include + +#define CHECK_EQUAL_RET_FALSE(OS, str) \ + do { \ + if (strcmp(OS.buffer, str) != 0) { \ + printf("OS.buffer != str\n"); \ + printf("OS.buffer: %s\n", OS.buffer); \ + printf("str : %s\n", str); \ + return false; \ + } \ + } while (0); + +static void overflow_SStream_concat0(SStream *OS, bool *returned_in_time) +{ + char buf[SSTREAM_BUF_LEN + 1] = { 0 }; + memset(&buf, 'A', SSTREAM_BUF_LEN); + SStream_concat0(OS, buf); + *returned_in_time = OS->buffer[SSTREAM_BUF_LEN - 1] == '\0'; +} + +static void overflow_SStream_concat(SStream *OS, bool *returned_in_time) +{ + char buf[SSTREAM_BUF_LEN + 1] = { 0 }; + memset(&buf, 'A', SSTREAM_BUF_LEN); + SStream_concat(OS, "%s", buf); + *returned_in_time = OS->buffer[SSTREAM_BUF_LEN - 1] == '\0'; +} + +static void overflow_SStream_concat1(SStream *OS, bool *returned_in_time) +{ + char buf[SSTREAM_BUF_LEN] = { 0 }; + memset(&buf, 'A', SSTREAM_BUF_LEN - 1); + SStream_concat0(OS, buf); + // Should return here because null byte is overflown. + SStream_concat1(OS, 'A'); + *returned_in_time = OS->buffer[SSTREAM_BUF_LEN - 1] == '\0'; +} + +static bool test_overflow_check() +{ + printf("Test test_overflow_check\n"); + + SStream OS = { 0 }; + SStream_Init(&OS); + bool returned_in_time = true; + overflow_SStream_concat0(&OS, &returned_in_time); + if (!returned_in_time) { + printf("Failed overflow_SStream_concat0\n"); + return false; + } + overflow_SStream_concat(&OS, &returned_in_time); + if (!returned_in_time) { + printf("Failed overflow_SStream_concat\n"); + return false; + } + overflow_SStream_concat1(&OS, &returned_in_time); + if (!returned_in_time) { + printf("Failed overflow_SStream_concat1\n"); + return false; + } + return true; +} + +static bool test_markup_os() +{ + printf("Test test_markup_os\n"); + + SStream OS = { 0 }; + SStream_Init(&OS); + SStream_concat0(&OS, "0"); + CHECK_EQUAL_RET_FALSE(OS, "0"); + OS.markup_stream = true; + printUInt64(&OS, 0); + CHECK_EQUAL_RET_FALSE(OS, "00"); + markup_OS(&OS, Markup_Immediate); + printUInt64(&OS, 0); + CHECK_EQUAL_RET_FALSE(OS, "00"); + markup_OS(&OS, Markup_Memory); + printUInt32(&OS, 0); + CHECK_EQUAL_RET_FALSE(OS, "00"); + markup_OS(&OS, Markup_Target); + printUInt32(&OS, 0); + CHECK_EQUAL_RET_FALSE(OS, "00"); + markup_OS(&OS, Markup_Register); + SStream_concat0(&OS, "r19"); + CHECK_EQUAL_RET_FALSE(OS, "00"); + return true; +} + +bool test_printint8() +{ + printf("Test test_printint8\n"); + + SStream OS = { 0 }; + SStream_Init(&OS); + printInt8(&OS, HEX_THRESHOLD + 1); + CHECK_EQUAL_RET_FALSE(OS, "0xa"); + SStream_Flush(&OS, NULL); + + printInt8(&OS, HEX_THRESHOLD); + CHECK_EQUAL_RET_FALSE(OS, "9"); + SStream_Flush(&OS, NULL); + + printInt8(&OS, -(HEX_THRESHOLD + 1)); + CHECK_EQUAL_RET_FALSE(OS, "-0xa"); + SStream_Flush(&OS, NULL); + + printInt8(&OS, -HEX_THRESHOLD); + CHECK_EQUAL_RET_FALSE(OS, "-9"); + SStream_Flush(&OS, NULL); + + printInt8(&OS, INT8_MAX); + CHECK_EQUAL_RET_FALSE(OS, "0x7f"); + SStream_Flush(&OS, NULL); + + printInt8(&OS, INT8_MIN); + CHECK_EQUAL_RET_FALSE(OS, "-0x80"); + SStream_Flush(&OS, NULL); + return true; +} + +bool test_printint16() +{ + printf("Test test_printint16\n"); + + SStream OS = { 0 }; + SStream_Init(&OS); + printInt16(&OS, HEX_THRESHOLD + 1); + CHECK_EQUAL_RET_FALSE(OS, "0xa"); + SStream_Flush(&OS, NULL); + + printInt16(&OS, HEX_THRESHOLD); + CHECK_EQUAL_RET_FALSE(OS, "9"); + SStream_Flush(&OS, NULL); + + printInt16(&OS, -(HEX_THRESHOLD + 1)); + CHECK_EQUAL_RET_FALSE(OS, "-0xa"); + SStream_Flush(&OS, NULL); + + printInt16(&OS, -HEX_THRESHOLD); + CHECK_EQUAL_RET_FALSE(OS, "-9"); + SStream_Flush(&OS, NULL); + + printInt16(&OS, INT16_MAX); + CHECK_EQUAL_RET_FALSE(OS, "0x7fff"); + SStream_Flush(&OS, NULL); + + printInt16(&OS, INT16_MIN); + CHECK_EQUAL_RET_FALSE(OS, "-0x8000"); + SStream_Flush(&OS, NULL); + return true; +} + +bool test_printint32() +{ + printf("Test test_printint32\n"); + + SStream OS = { 0 }; + SStream_Init(&OS); + printInt32(&OS, HEX_THRESHOLD + 1); + CHECK_EQUAL_RET_FALSE(OS, "0xa"); + SStream_Flush(&OS, NULL); + + printInt32(&OS, HEX_THRESHOLD); + CHECK_EQUAL_RET_FALSE(OS, "9"); + SStream_Flush(&OS, NULL); + + printInt32(&OS, -(HEX_THRESHOLD + 1)); + CHECK_EQUAL_RET_FALSE(OS, "-0xa"); + SStream_Flush(&OS, NULL); + + printInt32(&OS, -HEX_THRESHOLD); + CHECK_EQUAL_RET_FALSE(OS, "-9"); + SStream_Flush(&OS, NULL); + + printInt32(&OS, INT32_MAX); + CHECK_EQUAL_RET_FALSE(OS, "0x7fffffff"); + SStream_Flush(&OS, NULL); + + printInt32(&OS, INT32_MIN); + CHECK_EQUAL_RET_FALSE(OS, "-0x80000000"); + SStream_Flush(&OS, NULL); + return true; +} + +bool test_printint64() +{ + printf("Test test_printint64\n"); + + SStream OS = { 0 }; + SStream_Init(&OS); + printInt64(&OS, HEX_THRESHOLD + 1); + CHECK_EQUAL_RET_FALSE(OS, "0xa"); + SStream_Flush(&OS, NULL); + + printInt64(&OS, HEX_THRESHOLD); + CHECK_EQUAL_RET_FALSE(OS, "9"); + SStream_Flush(&OS, NULL); + + printInt64(&OS, -(HEX_THRESHOLD + 1)); + CHECK_EQUAL_RET_FALSE(OS, "-0xa"); + SStream_Flush(&OS, NULL); + + printInt64(&OS, -HEX_THRESHOLD); + CHECK_EQUAL_RET_FALSE(OS, "-9"); + SStream_Flush(&OS, NULL); + + printInt64(&OS, INT64_MAX); + CHECK_EQUAL_RET_FALSE(OS, "0x7fffffffffffffff"); + SStream_Flush(&OS, NULL); + + printInt64(&OS, INT64_MIN); + CHECK_EQUAL_RET_FALSE(OS, "-0x8000000000000000"); + SStream_Flush(&OS, NULL); + return true; +} + +bool test_printint32_bang() +{ + printf("Test test_printint32Bang\n"); + + SStream OS = { 0 }; + SStream_Init(&OS); + printInt32Bang(&OS, HEX_THRESHOLD + 1); + CHECK_EQUAL_RET_FALSE(OS, "#0xa"); + SStream_Flush(&OS, NULL); + + printInt32Bang(&OS, HEX_THRESHOLD); + CHECK_EQUAL_RET_FALSE(OS, "#9"); + SStream_Flush(&OS, NULL); + + printInt32Bang(&OS, -(HEX_THRESHOLD + 1)); + CHECK_EQUAL_RET_FALSE(OS, "#-0xa"); + SStream_Flush(&OS, NULL); + + printInt32Bang(&OS, -HEX_THRESHOLD); + CHECK_EQUAL_RET_FALSE(OS, "#-9"); + SStream_Flush(&OS, NULL); + + printInt32Bang(&OS, INT32_MAX); + CHECK_EQUAL_RET_FALSE(OS, "#0x7fffffff"); + SStream_Flush(&OS, NULL); + + printInt32Bang(&OS, INT32_MIN); + CHECK_EQUAL_RET_FALSE(OS, "#-0x80000000"); + SStream_Flush(&OS, NULL); + return true; +} + +bool test_printint64_bang() +{ + printf("Test test_printint64Bang\n"); + + SStream OS = { 0 }; + SStream_Init(&OS); + printInt64Bang(&OS, HEX_THRESHOLD + 1); + CHECK_EQUAL_RET_FALSE(OS, "#0xa"); + SStream_Flush(&OS, NULL); + + printInt64Bang(&OS, HEX_THRESHOLD); + CHECK_EQUAL_RET_FALSE(OS, "#9"); + SStream_Flush(&OS, NULL); + + printInt64Bang(&OS, -(HEX_THRESHOLD + 1)); + CHECK_EQUAL_RET_FALSE(OS, "#-0xa"); + SStream_Flush(&OS, NULL); + + printInt64Bang(&OS, -HEX_THRESHOLD); + CHECK_EQUAL_RET_FALSE(OS, "#-9"); + SStream_Flush(&OS, NULL); + + printInt64Bang(&OS, INT64_MAX); + CHECK_EQUAL_RET_FALSE(OS, "#0x7fffffffffffffff"); + SStream_Flush(&OS, NULL); + + printInt64Bang(&OS, INT64_MIN); + CHECK_EQUAL_RET_FALSE(OS, "#-0x8000000000000000"); + SStream_Flush(&OS, NULL); + return true; +} + +bool test_printuint32_bang() +{ + printf("Test test_printuint32Bang\n"); + + SStream OS = { 0 }; + SStream_Init(&OS); + printUInt32Bang(&OS, HEX_THRESHOLD + 1); + CHECK_EQUAL_RET_FALSE(OS, "#0xa"); + SStream_Flush(&OS, NULL); + + printUInt32Bang(&OS, HEX_THRESHOLD); + CHECK_EQUAL_RET_FALSE(OS, "#9"); + SStream_Flush(&OS, NULL); + + printUInt32Bang(&OS, UINT32_MAX); + CHECK_EQUAL_RET_FALSE(OS, "#0xffffffff"); + SStream_Flush(&OS, NULL); + return true; +} + +bool test_printuint64_bang() +{ + printf("Test test_printuint64Bang\n"); + + SStream OS = { 0 }; + SStream_Init(&OS); + printUInt64Bang(&OS, HEX_THRESHOLD + 1); + CHECK_EQUAL_RET_FALSE(OS, "#0xa"); + SStream_Flush(&OS, NULL); + + printUInt64Bang(&OS, HEX_THRESHOLD); + CHECK_EQUAL_RET_FALSE(OS, "#9"); + SStream_Flush(&OS, NULL); + + printUInt64Bang(&OS, UINT64_MAX); + CHECK_EQUAL_RET_FALSE(OS, "#0xffffffffffffffff"); + SStream_Flush(&OS, NULL); + return true; +} + +int main() +{ + bool result = true; + result &= test_markup_os(); + result &= test_overflow_check(); + result &= test_printint8(); + result &= test_printint16(); + result &= test_printint32(); + result &= test_printint64(); + result &= test_printint32_bang(); + result &= test_printint64_bang(); + result &= test_printuint32_bang(); + result &= test_printuint64_bang(); + if (result) { + printf("All tests passed.\n"); + } else { + printf("Some tests failed.\n"); + } + return result ? 0 : -1; +} diff --git a/utils.c b/utils.c index 3edf519c57..75c22c2bed 100644 --- a/utils.c +++ b/utils.c @@ -82,6 +82,56 @@ bool arr_exist(uint16_t *arr, unsigned char max, unsigned int id) return false; } +/// @brief Checks if the @id is in the @table. @table has @table_size elements. +/// @param table The table with the values to compare to. +/// @param table_size The number elements in the table. +/// @param id The identifier to search for in the table. +/// @return True if @id is part of the @table, false otherwise. +bool arr_exist_int(int *table, size_t table_size, int id) +{ + int i; + for (i = 0; i < table_size; i++) { + if (table[i] == id) + return true; + } + + return false; +} + +/// Reads 8 bytes in the endian order specified in MI->cs->mode. +uint64_t readBytes64(MCInst *MI, const uint8_t *Bytes) +{ + assert(MI && Bytes); + uint64_t Insn; + if (MODE_IS_BIG_ENDIAN(MI->csh->mode)) + Insn = ((uint64_t)Bytes[7] << 0) | ((uint64_t)Bytes[6] << 8) | + ((uint64_t)Bytes[5] << 16) | ((uint64_t)Bytes[4] << 24) | + ((uint64_t)Bytes[3] << 32) | ((uint64_t)Bytes[2] << 40) | + ((uint64_t)Bytes[1] << 48) | ((uint64_t)Bytes[0] << 56); + else + Insn = ((uint64_t)Bytes[7] << 56) | ((uint64_t)Bytes[6] << 48) | + ((uint64_t)Bytes[5] << 40) | ((uint64_t)Bytes[4] << 32) | + ((uint64_t)Bytes[3] << 24) | ((uint64_t)Bytes[2] << 16) | + ((uint64_t)Bytes[1] << 8) | ((uint64_t)Bytes[0] << 0); + return Insn; +} + +/// Reads 6 bytes in the endian order specified in MI->cs->mode. +uint64_t readBytes48(MCInst *MI, const uint8_t *Bytes) +{ + assert(MI && Bytes); + uint64_t Insn; + if (MODE_IS_BIG_ENDIAN(MI->csh->mode)) + Insn = ((uint64_t)Bytes[5] << 0) | ((uint64_t)Bytes[4] << 8) | + ((uint64_t)Bytes[3] << 16) | ((uint64_t)Bytes[2] << 24) | + ((uint64_t)Bytes[1] << 32) | ((uint64_t)Bytes[0] << 40); + else + Insn = ((uint64_t)Bytes[5] << 40) | ((uint64_t)Bytes[4] << 32) | + ((uint64_t)Bytes[3] << 24) | ((uint64_t)Bytes[2] << 16) | + ((uint64_t)Bytes[1] << 8) | ((uint64_t)Bytes[0] << 0); + return Insn; +} + /// Reads 4 bytes in the endian order specified in MI->cs->mode. uint32_t readBytes32(MCInst *MI, const uint8_t *Bytes) { diff --git a/utils.h b/utils.h index 3cca580c8f..c9c82bc275 100644 --- a/utils.h +++ b/utils.h @@ -35,11 +35,13 @@ int cs_snprintf(char *buffer, size_t size, const char *fmt, ...); // check if an id is existent in an array bool arr_exist8(unsigned char *arr, unsigned char max, unsigned int id); - bool arr_exist(uint16_t *arr, unsigned char max, unsigned int id); +bool arr_exist_int(int *table, size_t table_size, int id); uint16_t readBytes16(MCInst *MI, const uint8_t *Bytes); uint32_t readBytes32(MCInst *MI, const uint8_t *Bytes); +uint64_t readBytes48(MCInst *MI, const uint8_t *Bytes); +uint64_t readBytes64(MCInst *MI, const uint8_t *Bytes); void append_to_str_lower(char *str, size_t str_size, const char *src); void append_to_str(char *str, size_t str_buf_size, const char *src); diff --git a/windowsce/COMPILE.md b/windowsce/COMPILE.md index 2aaceb8c2d..4ee27888a7 100644 --- a/windowsce/COMPILE.md +++ b/windowsce/COMPILE.md @@ -83,7 +83,7 @@ Capstone supports the following architectures: ARM, ARM64 (AArch64), M68K, MIPS, - `MIPS` - `POWERPC` - `SPARC` -- `SYSZ` +- `SYSTEMZ` - `X86` - `XCORE`. From 3a2cd3c331888237ea642043b2118c85eb68914b Mon Sep 17 00:00:00 2001 From: Rot127 <45763064+Rot127@users.noreply.github.com> Date: Wed, 18 Sep 2024 13:19:42 +0000 Subject: [PATCH 5/5] Coverity defects (#2469) * Fix CID 508418 - Uninitialized struct * Fix CID 509089 - Fix OOB read and write * Fix CID 509088 - OOB. Also adds tests and to ensure no OOB access. * Fix CID 509085 - Resource leak. * Fix CID 508414 and companions - Using undefined values. * Fix CID 508405 - Use of uninitialized value * Remove unnecessary and badly implemented dev fuzz code. * Fix CID 508396 - Uninitialzied variable. * Fix CID 508393, 508365 -- OOB read. * Fix CID 432207 - OVerlapping memory access. * Remove unused functions * Fix CID 432170 - Overlapping memory access. * Fix CID 166022 - Check for negative index * Let strncat not depend n src operand. * Fix 509083 and 509084 - NULL dereference * Remove duplicated code. * Initialize sysop * Fix resource leak * Remove unreachable code. * Remove duplicate code. * Add assert to check return value of cmoack * Fixed: d should be a signed value, since it is checked against < 0 * Add missing break. * Add NULL check * Fix signs of binary search comparisons. * Add explicit cast of or result * Fix correct scope of case. * Handle invalid integer type. * Return UINT_MAX instead of implicitly casted -1 * Remove dead code * Fix type of im * Fix type of d * Remove duplicated code. * Add returns after CS_ASSERTS * Check for len == 0 case. * Ensure shift operates on uint64 * Replace strcpy with strncpy. * Handle edge cases for 32bit rotate * Fix some out of enum warnings * Replace a strcpy with strncpy. * Fix increment of address * Skip some linting * Fix: set instruction id * Remove unused enum * Replace the last usages of strcpy with SStream functions. * Increase number of allowed AArch64 operands. * Check safety of incrementing t the next operand. * Fix naming of operand * Update python constants * Fix option setup of CS_OPT_DETAIL_REAL * Document DETAIL_REAL has to be used with CS_OPT_ON. * Run Coverity scan every Monday. * Remove dead code * Fix OOB read * Rename macro to reflect it is only used with sstreams * Fix rebase issues --- .github/workflows/coverity.yml | 2 +- MCInstPrinter.c | 4 +- Mapping.c | 12 +- Mapping.h | 16 + MathExtras.h | 12 +- SStream.c | 98 +++++- SStream.h | 10 + arch/AArch64/AArch64AddressingModes.h | 5 +- arch/AArch64/AArch64InstPrinter.c | 10 +- arch/AArch64/AArch64Mapping.c | 54 ++-- arch/ARM/ARMAddressingModes.h | 7 +- arch/ARM/ARMInstPrinter.c | 13 +- arch/ARM/ARMMapping.c | 26 +- arch/Alpha/AlphaGenDisassemblerTables.inc | 1 + arch/HPPA/HPPADisassembler.c | 14 +- arch/M680X/M680XDisassembler.c | 6 +- arch/M68K/M68KDisassembler.c | 7 - arch/MOS65XX/MOS65XXModule.c | 2 +- arch/PowerPC/PPCMapping.c | 7 +- arch/RISCV/RISCVGenAsmWriter.inc | 20 +- arch/RISCV/RISCVGenDisassemblerTables.inc | 3 +- arch/SH/SHDisassembler.c | 17 +- arch/Sparc/SparcInstPrinter.c | 8 +- arch/Sparc/SparcInstPrinter.h | 2 +- arch/TMS320C64x/TMS320C64xDisassembler.c | 8 +- arch/TMS320C64x/TMS320C64xInstPrinter.c | 64 ++-- arch/TMS320C64x/TMS320C64xInstPrinter.h | 2 +- arch/TriCore/TriCoreDisassembler.c | 6 +- arch/TriCore/TriCoreInstPrinter.c | 6 +- arch/WASM/WASMDisassembler.c | 3 - arch/X86/X86ATTInstPrinter.c | 9 +- arch/X86/X86Mapping.c | 2 +- arch/X86/X86Mapping.h | 2 +- arch/XCore/XCoreInstPrinter.c | 13 +- arch/XCore/XCoreInstPrinter.h | 2 +- bindings/python/capstone/__init__.py | 4 +- bindings/python/capstone/arm_const.py | 2 + bindings/python/capstone/hppa_const.py | 1 - bindings/python/capstone/sh_const.py | 3 - bindings/python/capstone/systemz_const.py | 1 + bindings/python/capstone/tricore_const.py | 1 - cs.c | 64 +--- cs_priv.h | 2 +- cstool/cstool.c | 60 +--- cstool/cstool_aarch64.c | 1 + cstool/cstool_arm.c | 3 +- cstool/cstool_systemz.c | 6 +- cstool/cstool_x86.c | 4 + docs/cs_v6_release_guide.md | 2 +- include/capstone/aarch64.h | 4 +- include/capstone/alpha.h | 4 +- include/capstone/arm.h | 5 +- include/capstone/hppa.h | 4 +- include/capstone/loongarch.h | 4 +- include/capstone/mips.h | 4 +- include/capstone/riscv.h | 4 +- include/capstone/sh.h | 9 +- include/capstone/tricore.h | 4 +- .../src/autosync/Tests/test_aarch64_header.h | 4 +- suite/cstest/src/test_case.c | 15 +- suite/cstest/src/test_detail_x86.c | 4 +- suite/cstest/src/test_run.c | 8 +- suite/fuzz/platform.c | 6 +- tests/issues/issues.yaml | 74 +++++ tests/unit/CMakeLists.txt | 20 +- tests/unit/include/unit_test.h | 44 +++ tests/unit/sstream.c | 303 ++++++++++++++---- tests/unit/utils.c | 76 +++++ utils.c | 23 +- utils.h | 2 +- 70 files changed, 843 insertions(+), 405 deletions(-) create mode 100644 tests/unit/include/unit_test.h create mode 100644 tests/unit/utils.c diff --git a/.github/workflows/coverity.yml b/.github/workflows/coverity.yml index 75810e2eed..9c54620b20 100644 --- a/.github/workflows/coverity.yml +++ b/.github/workflows/coverity.yml @@ -2,7 +2,7 @@ name: Coverity Scan on: workflow_dispatch: schedule: - - cron: '0 0 01 * *' # On the 1st every month at midnight UTC + - cron: '0 0 * * 1' # On every Monday at midnight UTC # Automatically cancel any previous workflow on new push. diff --git a/MCInstPrinter.c b/MCInstPrinter.c index 4e509c6eee..687fbf359c 100644 --- a/MCInstPrinter.c +++ b/MCInstPrinter.c @@ -232,8 +232,8 @@ unsigned int binsearch_IndexTypeStrEncoding(const struct IndexTypeStr *index, si right = size - 1; - size_t str_left_cmp = strcmp(name, index[0].name); - size_t str_right_cmp = strcmp(name, index[right].name); + int str_left_cmp = strcmp(name, index[0].name); + int str_right_cmp = strcmp(name, index[right].name); if (str_left_cmp < 0 || str_right_cmp > 0) // not found return -1; diff --git a/Mapping.c b/Mapping.c index d2ef694d5d..c39ae7f850 100644 --- a/Mapping.c +++ b/Mapping.c @@ -150,7 +150,10 @@ void map_implicit_reads(MCInst *MI, const insn_map *imap) return; } detail->regs_read[detail->regs_read_count++] = reg; - reg = imap[Opcode].regs_use[++i]; + if (i + 1 < MAX_IMPL_R_REGS) { + // Select next one + reg = imap[Opcode].regs_use[++i]; + } } #endif // CAPSTONE_DIET } @@ -175,7 +178,10 @@ void map_implicit_writes(MCInst *MI, const insn_map *imap) return; } detail->regs_write[detail->regs_write_count++] = reg; - reg = imap[Opcode].regs_mod[++i]; + if (i + 1 < MAX_IMPL_W_REGS) { + // Select next one + reg = imap[Opcode].regs_mod[++i]; + } } #endif // CAPSTONE_DIET } @@ -348,7 +354,7 @@ DEFINE_get_detail_op(systemz, SystemZ); /// So it can be toggled between disas() calls. bool map_use_alias_details(const MCInst *MI) { assert(MI); - return !(MI->csh->detail_opt & CS_OPT_DETAIL_REAL); + return (MI->csh->detail_opt & CS_OPT_ON) && !(MI->csh->detail_opt & CS_OPT_DETAIL_REAL); } /// Sets the setDetailOps flag to @p Val. diff --git a/Mapping.h b/Mapping.h index 473075ea2d..790f1cb1a3 100644 --- a/Mapping.h +++ b/Mapping.h @@ -209,6 +209,22 @@ DEFINE_get_arch_detail(mips, Mips); DEFINE_get_arch_detail(riscv, RISCV); DEFINE_get_arch_detail(systemz, SystemZ); +#define DEFINE_check_safe_inc(Arch, ARCH) \ + static inline void Arch##_check_safe_inc() { \ + CS_ASSERT(Arch##_get_detail(MI)->op_count + 1 < NUM_##ARCH##_OPS); \ + } + +DEFINE_check_safe_inc(ARM, ARM); +DEFINE_check_safe_inc(PPC, PPC); +DEFINE_check_safe_inc(TriCore, TRICORE); +DEFINE_check_safe_inc(AArch64, AARCH64); +DEFINE_check_safe_inc(Alpha, ALPHA); +DEFINE_check_safe_inc(HPPA, HPPA); +DEFINE_check_safe_inc(LoongArch, LOONGARCH); +DEFINE_check_safe_inc(RISCV, RISCV); +DEFINE_check_safe_inc(SystemZ, SYSTEMZ); +DEFINE_check_safe_inc(Mips, MIPS); + static inline bool detail_is_set(const MCInst *MI) { assert(MI && MI->flat_insn); diff --git a/MathExtras.h b/MathExtras.h index eb3b989713..19dfba4f6a 100644 --- a/MathExtras.h +++ b/MathExtras.h @@ -29,6 +29,8 @@ #endif #endif +#include + // NOTE: The following support functions use the _32/_64 extensions instead of // type overloading so that signed and unsigned integers can be used without // ambiguity. @@ -280,15 +282,21 @@ static inline unsigned CountPopulation_64(uint64_t Value) { } /// Log2_32 - This function returns the floor log base 2 of the specified value, -/// -1 if the value is zero. (32 bit edition.) +/// UINT_MAX if the value is zero. (32 bit edition.) /// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2 static inline unsigned Log2_32(uint32_t Value) { + if (Value == 0) { + return UINT_MAX; + } return 31 - CountLeadingZeros_32(Value); } /// Log2_64 - This function returns the floor log base 2 of the specified value, -/// -1 if the value is zero. (64 bit edition.) +/// UINT_MAX if the value is zero. (64 bit edition.) static inline unsigned Log2_64(uint64_t Value) { + if (Value == 0) { + return UINT32_MAX; + } return 63 - CountLeadingZeros_64(Value); } diff --git a/SStream.c b/SStream.c index 68c685c051..a69150710c 100644 --- a/SStream.c +++ b/SStream.c @@ -18,20 +18,108 @@ #include "cs_priv.h" #include "utils.h" -#ifdef _MSC_VER -#pragma warning(disable: 4996) // disable MSVC's warning on strcpy() -#endif - void SStream_Init(SStream *ss) { assert(ss); ss->index = 0; - ss->buffer[0] = '\0'; + memset(ss->buffer, 0, sizeof(ss->buffer)); ss->is_closed = false; ss->markup_stream = false; ss->prefixed_by_markup = false; } +/// Returns the a pointer to the internal string buffer of the stream. +/// For reading only. +const char *SStream_rbuf(const SStream *ss) { + assert(ss); + return ss->buffer; +} + +/// Searches in the stream for the first (from the left) occurrence of @elem and replaces +/// it with @repl. It returns the pointer *after* the replaced character +/// or NULL if no character was replaced. +/// +/// It will never replace the final \0 byte in the stream buffer. +const char *SStream_replc(const SStream *ss, char elem, char repl) { + assert(ss); + char *found = strchr(ss->buffer, elem); + if (!found || found == ss->buffer + (SSTREAM_BUF_LEN - 1)) { + return NULL; + } + *found = repl; + found++; + return found; +} + +/// Searches in the stream for the first (from the left) occurrence of @chr and replaces +/// it with @rstr. +void SStream_replc_str(SStream *ss, char chr, const char *rstr) { + assert(ss && rstr); + char *found = strchr(ss->buffer, chr); + if (!found || found == ss->buffer + (SSTREAM_BUF_LEN - 1)) { + return; + } + size_t post_len = strlen(found + 1); + size_t buf_str_len = strlen(ss->buffer); + size_t repl_len = strlen(rstr); + if (repl_len - 1 + buf_str_len >= SSTREAM_BUF_LEN) { + return; + } + memmove(found + repl_len, found + 1, post_len); + memcpy(found, rstr, repl_len); + ss->index = strlen(ss->buffer); +} + +/// Removes the space characters '\t' and ' ' from the beginning of the stream buffer. +void SStream_trimls(SStream *ss) { + assert(ss); + size_t buf_off = 0; + /// Remove leading spaces + while (ss->buffer[buf_off] == ' ' || ss->buffer[buf_off] == '\t') { + buf_off++; + } + if (buf_off > 0) { + memmove(ss->buffer, ss->buffer + buf_off, SSTREAM_BUF_LEN - buf_off); + ss->index -= buf_off; + } +} + +/// Extract the mnemonic to @mnem_buf and the operand string into @op_str_buf from the stream buffer. +/// The mnemonic is everything up until the first ' ' or '\t' character. +/// The operand string is everything after the first ' ' or '\t' sequence. +void SStream_extract_mnem_opstr(const SStream *ss, char *mnem_buf, size_t mnem_buf_size, char *op_str_buf, size_t op_str_buf_size) { + assert(ss && mnem_buf && mnem_buf_size > 0 && op_str_buf && op_str_buf_size > 0); + size_t off = 0; + // Copy all non space chars to as mnemonic. + while (ss->buffer[off] && ss->buffer[off] != ' ' && ss->buffer[off] != '\t') { + if (off < mnem_buf_size - 1) { + // Only copy if there is space left. + mnem_buf[off] = ss->buffer[off]; + } + off++; + } + if (!ss->buffer[off]) { + return; + } + + // Iterate until next non space char. + do { + off++; + } while (ss->buffer[off] && (ss->buffer[off] == ' ' || ss->buffer[off] == '\t')); + + if (!ss->buffer[off]) { + return; + } + + // Copy all follow up characters as op_str + const char *ss_op_str = ss->buffer + off; + off = 0; + while (ss_op_str[off] && off < op_str_buf_size - 1) { + op_str_buf[off] = ss_op_str[off]; + off++; + } +} + /// Empty the stream @ss to given @file (stdin/stderr). /// @file can be NULL. Then the buffer content is not emitted. void SStream_Flush(SStream *ss, FILE *file) diff --git a/SStream.h b/SStream.h index 35c90738d4..8789ea6cc6 100644 --- a/SStream.h +++ b/SStream.h @@ -40,6 +40,16 @@ do { \ void SStream_Init(SStream *ss); +const char *SStream_replc(const SStream *ss, char elem, char repl); + +void SStream_replc_str(SStream *ss, char chr, const char *rstr); + +const char *SStream_rbuf(const SStream *ss); + +void SStream_extract_mnem_opstr(const SStream *ss, char *mnem_buf, size_t mnem_buf_size, char *op_str_buf, size_t op_str_buf_size); + +void SStream_trimls(SStream *ss); + void SStream_Flush(SStream *ss, FILE *file); void SStream_Open(SStream *ss); diff --git a/arch/AArch64/AArch64AddressingModes.h b/arch/AArch64/AArch64AddressingModes.h index e77378d6e0..273b3eaa50 100644 --- a/arch/AArch64/AArch64AddressingModes.h +++ b/arch/AArch64/AArch64AddressingModes.h @@ -390,7 +390,10 @@ static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val, unsigned imms = val & 0x3f; int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); - assert(len >= 1); + if (len < 1) { + assert(len >= 1 && "Unhandled integer type"); + return 0; + } unsigned size = (1 << len); unsigned R = immr & (size - 1); diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c index 4db25f2ab6..9d7f2bd7b0 100644 --- a/arch/AArch64/AArch64InstPrinter.c +++ b/arch/AArch64/AArch64InstPrinter.c @@ -727,7 +727,7 @@ Search_IC: { !AArch64_testFeatureList(MI->csh->mode, IC->FeaturesRequired)) return false; if (detail_is_set(MI)) { - aarch64_sysop sysop; + aarch64_sysop sysop = { 0 }; sysop.reg = IC->SysReg; sysop.sub_type = AARCH64_OP_IC; AArch64_get_detail_op(MI, 0)->type = AARCH64_OP_SYSREG; @@ -754,7 +754,7 @@ Search_IC: { MI->csh->mode, DC->FeaturesRequired)) return false; if (detail_is_set(MI)) { - aarch64_sysop sysop; + aarch64_sysop sysop = { 0 }; sysop.alias = DC->SysAlias; sysop.sub_type = AARCH64_OP_DC; AArch64_get_detail_op(MI, 0)->type = @@ -777,7 +777,7 @@ Search_IC: { return false; if (detail_is_set(MI)) { - aarch64_sysop sysop; + aarch64_sysop sysop = { 0 }; sysop.alias = AT->SysAlias; sysop.sub_type = AARCH64_OP_AT; AArch64_get_detail_op(MI, 0)->type = @@ -799,7 +799,7 @@ Search_IC: { return false; if (detail_is_set(MI)) { - aarch64_sysop sysop; + aarch64_sysop sysop = { 0 }; sysop.reg = TLBI->SysReg; sysop.sub_type = AARCH64_OP_TLBI; AArch64_get_detail_op(MI, 0)->type = AARCH64_OP_SYSREG; @@ -868,7 +868,7 @@ bool printSyspAlias(MCInst *MI, SStream *O) return false; if (detail_is_set(MI)) { - aarch64_sysop sysop; + aarch64_sysop sysop = { 0 }; sysop.reg = TLBI->SysReg; sysop.sub_type = AARCH64_OP_TLBI; AArch64_get_detail_op(MI, 0)->type = AARCH64_OP_SYSREG; diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c index 68d588c190..bf2be7aa92 100644 --- a/arch/AArch64/AArch64Mapping.c +++ b/arch/AArch64/AArch64Mapping.c @@ -595,7 +595,7 @@ static void AArch64_add_not_defined_ops(MCInst *MI, const SStream *OS) const char *disp_off = NULL; disp_off = strstr(OS->buffer, " za"); if (disp_off) { - aarch64_sysop sysop; + aarch64_sysop sysop = { 0 }; sysop.alias.svcr = AARCH64_SVCR_SVCRZA; sysop.sub_type = AARCH64_OP_SVCR; AArch64_insert_detail_op_sys(MI, -1, sysop, @@ -604,7 +604,7 @@ static void AArch64_add_not_defined_ops(MCInst *MI, const SStream *OS) } disp_off = strstr(OS->buffer, " sm"); if (disp_off) { - aarch64_sysop sysop; + aarch64_sysop sysop = { 0 }; sysop.alias.svcr = AARCH64_SVCR_SVCRSM; sysop.sub_type = AARCH64_OP_SVCR; AArch64_insert_detail_op_sys(MI, -1, sysop, @@ -1384,7 +1384,7 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group, } case AArch64_OP_GROUP_BarriernXSOption: { unsigned Val = MCInst_getOpVal(MI, OpNum); - aarch64_sysop sysop; + aarch64_sysop sysop = { 0 }; const AArch64DBnXS_DBnXS *DB = AArch64DBnXS_lookupDBnXSByEncoding(Val); if (DB) @@ -1398,7 +1398,7 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group, case AArch64_OP_GROUP_BarrierOption: { unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); unsigned Opcode = MCInst_getOpcode(MI); - aarch64_sysop sysop; + aarch64_sysop sysop = { 0 }; if (Opcode == AArch64_ISB) { const AArch64ISB_ISB *ISB = @@ -1434,7 +1434,7 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group, break; } case AArch64_OP_GROUP_BTIHintOp: { - aarch64_sysop sysop; + aarch64_sysop sysop = { 0 }; unsigned btihintop = MCInst_getOpVal(MI, OpNum) ^ 32; const AArch64BTIHint_BTI *BTI = AArch64BTIHint_lookupBTIByEncoding(btihintop); @@ -1523,6 +1523,7 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group, (int) (AARCH64_REG_ZAD0 + I)); AArch64_inc_op_count(MI); } + AArch64_get_detail(MI)->is_doing_sme = false; break; } case AArch64_OP_GROUP_MRSSystemRegister: @@ -1541,7 +1542,7 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group, if (Reg && !isValidSysReg) Reg = AArch64SysReg_lookupSysRegByName(Reg->AltName); - aarch64_sysop sysop; + aarch64_sysop sysop = { 0 }; // If Reg is NULL it is a generic system register. if (Reg) sysop.reg = Reg->SysReg; @@ -1560,7 +1561,7 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group, unsigned psbhintop = MCInst_getOpVal(MI, OpNum); const AArch64PSBHint_PSB *PSB = AArch64PSBHint_lookupPSBByEncoding(psbhintop); - aarch64_sysop sysop; + aarch64_sysop sysop = { 0 }; if (PSB) sysop.alias = PSB->SysAlias; else @@ -1574,7 +1575,7 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group, unsigned prfop = MCInst_getOpVal(MI, OpNum); const AArch64PRFM_PRFM *PRFM = AArch64PRFM_lookupPRFMByEncoding(prfop); - aarch64_sysop sysop; + aarch64_sysop sysop = { 0 }; if (PRFM) sysop.alias = PRFM->SysAlias; else @@ -1611,7 +1612,7 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group, unsigned svcrop = MCInst_getOpVal(MI, OpNum); const AArch64SVCR_SVCR *SVCR = AArch64SVCR_lookupSVCRByEncoding(svcrop); - aarch64_sysop sysop; + aarch64_sysop sysop = { 0 }; if (SVCR) sysop.alias = SVCR->SysAlias; else @@ -1629,7 +1630,7 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group, AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM, Val); break; } - aarch64_sysop sysop; + aarch64_sysop sysop = { 0 }; sysop.alias = Pat->SysAlias; sysop.sub_type = AARCH64_OP_SVEPREDPAT; AArch64_set_detail_op_sys(MI, OpNum, sysop, @@ -1646,7 +1647,7 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group, Val); if (!Pat) break; - aarch64_sysop sysop; + aarch64_sysop sysop = { 0 }; sysop.alias = Pat->SysAlias; sysop.sub_type = AARCH64_OP_SVEVECLENSPECIFIER; AArch64_set_detail_op_sys(MI, OpNum, sysop, @@ -1667,7 +1668,7 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group, case AArch64_OP_GROUP_SystemPStateField: { unsigned Val = MCInst_getOpVal(MI, OpNum); - aarch64_sysop sysop; + aarch64_sysop sysop = { 0 }; const AArch64PState_PStateImm0_15 *PStateImm15 = AArch64PState_lookupPStateImm0_15ByEncoding(Val); const AArch64PState_PStateImm0_1 *PStateImm1 = @@ -1881,7 +1882,7 @@ static void add_cs_detail_template_1(MCInst *MI, aarch64_op_group op_group, case AArch64_OP_GROUP_PrefetchOp_1: { bool IsSVEPrefetch = (bool)temp_arg_0; unsigned prfop = MCInst_getOpVal(MI, (OpNum)); - aarch64_sysop sysop; + aarch64_sysop sysop = { 0 }; if (IsSVEPrefetch) { const AArch64SVEPRFM_SVEPRFM *PRFM = AArch64SVEPRFM_lookupSVEPRFMByEncoding(prfop); @@ -2036,7 +2037,7 @@ static void add_cs_detail_template_2(MCInst *MI, aarch64_op_group op_group, const AArch64ExactFPImm_ExactFPImm *Imm1Desc = AArch64ExactFPImm_lookupExactFPImmByEnum(ImmIs1); unsigned Val = MCInst_getOpVal(MI, (OpNum)); - aarch64_sysop sysop; + aarch64_sysop sysop = { 0 }; sysop.imm = Val ? Imm1Desc->SysImm : Imm0Desc->SysImm; sysop.sub_type = AARCH64_OP_EXACTFPIMM; AArch64_set_detail_op_sys(MI, OpNum, sysop, AARCH64_OP_SYSIMM); @@ -2474,6 +2475,8 @@ void AArch64_set_detail_op_reg(MCInst *MI, unsigned OpNum, aarch64_reg Reg) { if (!detail_is_set(MI)) return; + AArch64_check_safe_inc(); + if (Reg == AARCH64_REG_ZA || (Reg >= AARCH64_REG_ZAB0 && Reg < AARCH64_REG_ZT0)) { // A tile register should be treated as SME operand. @@ -2519,6 +2522,7 @@ void AArch64_set_detail_op_imm(MCInst *MI, unsigned OpNum, { if (!detail_is_set(MI)) return; + AArch64_check_safe_inc(); if (AArch64_get_detail(MI)->is_doing_sme) { assert(map_get_op_type(MI, OpNum) & CS_OP_BOUND); @@ -2553,6 +2557,7 @@ void AArch64_set_detail_op_imm_range(MCInst *MI, unsigned OpNum, { if (!detail_is_set(MI)) return; + AArch64_check_safe_inc(); if (AArch64_get_detail(MI)->is_doing_sme) { assert(map_get_op_type(MI, OpNum) & CS_OP_BOUND); @@ -2585,6 +2590,7 @@ void AArch64_set_detail_op_mem(MCInst *MI, unsigned OpNum, uint64_t Val) { if (!detail_is_set(MI)) return; + AArch64_check_safe_inc(); assert(map_get_op_type(MI, OpNum) & CS_OP_MEM); AArch64_set_mem_access(MI, true); @@ -2670,6 +2676,8 @@ void AArch64_set_detail_op_float(MCInst *MI, unsigned OpNum, float Val) { if (!detail_is_set(MI)) return; + AArch64_check_safe_inc(); + AArch64_get_detail_op(MI, 0)->type = AARCH64_OP_FP; AArch64_get_detail_op(MI, 0)->fp = Val; AArch64_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); @@ -2683,6 +2691,8 @@ void AArch64_set_detail_op_sys(MCInst *MI, unsigned OpNum, aarch64_sysop sys_op, { if (!detail_is_set(MI)) return; + AArch64_check_safe_inc(); + AArch64_get_detail_op(MI, 0)->type = type; AArch64_get_detail_op(MI, 0)->sysop = sys_op; AArch64_inc_op_count(MI); @@ -2691,6 +2701,7 @@ void AArch64_set_detail_op_sys(MCInst *MI, unsigned OpNum, aarch64_sysop sys_op, void AArch64_set_detail_op_pred(MCInst *MI, unsigned OpNum) { if (!detail_is_set(MI)) return; + AArch64_check_safe_inc(); if (AArch64_get_detail_op(MI, 0)->type == AARCH64_OP_INVALID) { setup_pred_operand(MI); @@ -2718,6 +2729,8 @@ void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum, { if (!detail_is_set(MI)) return; + AArch64_check_safe_inc(); + AArch64_get_detail_op(MI, 0)->type = AARCH64_OP_SME; switch (part) { default: @@ -2794,9 +2807,9 @@ static void insert_op(MCInst *MI, unsigned index, cs_aarch64_op op) return; } + AArch64_check_safe_inc(); cs_aarch64_op *ops = AArch64_get_detail(MI)->operands; int i = AArch64_get_detail(MI)->op_count; - assert(i < MAX_AARCH64_OPS); if (index == -1) { ops[i] = op; AArch64_inc_op_count(MI); @@ -2818,7 +2831,7 @@ void AArch64_insert_detail_op_float_at(MCInst *MI, unsigned index, double val, if (!detail_is_set(MI)) return; - assert(AArch64_get_detail(MI)->op_count < MAX_AARCH64_OPS); + AArch64_check_safe_inc(); cs_aarch64_op op; AArch64_setup_op(&op); @@ -2838,7 +2851,7 @@ void AArch64_insert_detail_op_reg_at(MCInst *MI, unsigned index, if (!detail_is_set(MI)) return; - assert(AArch64_get_detail(MI)->op_count < MAX_AARCH64_OPS); + AArch64_check_safe_inc(); cs_aarch64_op op; AArch64_setup_op(&op); @@ -2856,8 +2869,7 @@ void AArch64_insert_detail_op_imm_at(MCInst *MI, unsigned index, int64_t Imm) { if (!detail_is_set(MI)) return; - - assert(AArch64_get_detail(MI)->op_count < MAX_AARCH64_OPS); + AArch64_check_safe_inc(); cs_aarch64_op op; AArch64_setup_op(&op); @@ -2873,7 +2885,7 @@ void AArch64_insert_detail_op_sys(MCInst *MI, unsigned index, aarch64_sysop sys_ { if (!detail_is_set(MI)) return; - assert(AArch64_get_detail(MI)->op_count < MAX_AARCH64_OPS); + AArch64_check_safe_inc(); cs_aarch64_op op; AArch64_setup_op(&op); @@ -2887,7 +2899,7 @@ void AArch64_insert_detail_op_sme(MCInst *MI, unsigned index, aarch64_op_sme sme { if (!detail_is_set(MI)) return; - assert(AArch64_get_detail(MI)->op_count < MAX_AARCH64_OPS); + AArch64_check_safe_inc(); cs_aarch64_op op; AArch64_setup_op(&op); diff --git a/arch/ARM/ARMAddressingModes.h b/arch/ARM/ARMAddressingModes.h index 16d4b14337..bcfa89c964 100644 --- a/arch/ARM/ARMAddressingModes.h +++ b/arch/ARM/ARMAddressingModes.h @@ -28,6 +28,7 @@ #define CS_ARM_ADDRESSINGMODES_H #include +#include "../../cs_priv.h" #include #include #include @@ -120,7 +121,11 @@ static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_SubMode Mode) /// static inline unsigned ARM_AM_rotr32(unsigned Val, unsigned Amt) { - return (Val >> Amt) | (Val << ((32 - Amt) & 31)); + CS_ASSERT(Amt >= 32); + if (Amt == 32) { + return Val; + } + return (Val >> Amt) | (Val << ((32 - Amt) & 31)); // NOLINT(clang-analyzer-core.BitwiseShift) } /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits. diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c index 4dfbfc0165..0457952baf 100644 --- a/arch/ARM/ARMInstPrinter.c +++ b/arch/ARM/ARMInstPrinter.c @@ -490,20 +490,13 @@ void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O) SStream_concat0(O, "[pc, "); int32_t OffImm = (int32_t)MCOperand_getImm(MO1); - bool isSub = OffImm < 0; // Special value for #-0. All others are normal. if (OffImm == INT32_MIN) OffImm = 0; - if (isSub) { - SStream_concat(O, "%s", markup("")); - } else { - SStream_concat(O, "%s", markup("")); - } + SStream_concat(O, "%s", markup("")); SStream_concat(O, "%s", "]"); SStream_concat0(O, markup(">")); } diff --git a/arch/ARM/ARMMapping.c b/arch/ARM/ARMMapping.c index 22ba146d32..7e8f5407e1 100644 --- a/arch/ARM/ARMMapping.c +++ b/arch/ARM/ARMMapping.c @@ -935,6 +935,7 @@ static void ARM_set_mem_access(MCInst *MI, bool status) #endif } else { // done, select the next operand slot + ARM_check_safe_inc(); ARM_inc_op_count(MI); } } @@ -1160,6 +1161,7 @@ static void add_cs_detail_general(MCInst *MI, arm_op_group op_group, unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, i)); + ARM_check_safe_inc(); ARM_get_detail_op(MI, 0)->type = ARM_OP_REG; ARM_get_detail_op(MI, 0)->reg = Reg; ARM_get_detail_op(MI, 0)->access = access; @@ -1173,7 +1175,7 @@ static void add_cs_detail_general(MCInst *MI, arm_op_group op_group, unsigned CondBit0 = Firstcond & 1; unsigned NumTZ = CountTrailingZeros_32(Mask); unsigned Pos, e; - ARM_PredBlockMask PredMask = 0; + ARM_PredBlockMask PredMask = ARM_PredBlockMaskInvalid; // Check the documentation of ARM_PredBlockMask how the bits are set. for (Pos = 3, e = NumTZ; Pos > e; --Pos) { @@ -1192,7 +1194,7 @@ static void add_cs_detail_general(MCInst *MI, arm_op_group op_group, case ARM_OP_GROUP_VPTMask: { unsigned Mask = MCInst_getOpVal(MI, OpNum); unsigned NumTZ = CountTrailingZeros_32(Mask); - ARM_PredBlockMask PredMask = 0; + ARM_PredBlockMask PredMask = ARM_PredBlockMaskInvalid; // Check the documentation of ARM_PredBlockMask how the bits are set. for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { @@ -1661,6 +1663,7 @@ static void add_cs_detail_general(MCInst *MI, arm_op_group op_group, int32_t OffImm = MCInst_getOpVal(MI, OpNum); if (OffImm == INT32_MIN) OffImm = 0; + ARM_check_safe_inc(); ARM_get_detail_op(MI, 0)->type = ARM_OP_MEM; ARM_get_detail_op(MI, 0)->mem.base = ARM_REG_PC; ARM_get_detail_op(MI, 0)->mem.index = ARM_REG_INVALID; @@ -1683,6 +1686,7 @@ static void add_cs_detail_general(MCInst *MI, arm_op_group op_group, } case ARM_OP_GROUP_SetendOperand: { bool be = MCInst_getOpVal(MI, OpNum) != 0; + ARM_check_safe_inc(); if (be) { ARM_get_detail_op(MI, 0)->type = ARM_OP_SETEND; ARM_get_detail_op(MI, 0)->setend = ARM_SETEND_BE; @@ -1793,6 +1797,7 @@ static void add_cs_detail_template_1(MCInst *MI, arm_op_group op_group, if (AlwaysPrintImm0) map_add_implicit_write(MI, MCInst_getOpVal(MI, OpNum)); + ARM_check_safe_inc(); cs_arm_op *Op = ARM_get_detail_op(MI, 0); Op->type = ARM_OP_MEM; Op->mem.base = MCInst_getOpVal(MI, OpNum); @@ -1932,7 +1937,7 @@ void ARM_insert_detail_op_reg_at(MCInst *MI, unsigned index, arm_reg Reg, if (!detail_is_set(MI)) return; - assert(ARM_get_detail(MI)->op_count < MAX_ARM_OPS); + ARM_check_safe_inc(); cs_arm_op op; ARM_setup_op(&op); @@ -1942,7 +1947,6 @@ void ARM_insert_detail_op_reg_at(MCInst *MI, unsigned index, arm_reg Reg, cs_arm_op *ops = ARM_get_detail(MI)->operands; int i = ARM_get_detail(MI)->op_count; - assert(i < MAX_ARM_OPS); for (; i > 0 && i > index; --i) { ops[i] = ops[i - 1]; } @@ -1957,8 +1961,7 @@ void ARM_insert_detail_op_imm_at(MCInst *MI, unsigned index, int64_t Val, { if (!detail_is_set(MI)) return; - - assert(ARM_get_detail(MI)->op_count < MAX_ARM_OPS); + ARM_check_safe_inc(); cs_arm_op op; ARM_setup_op(&op); @@ -1968,7 +1971,6 @@ void ARM_insert_detail_op_imm_at(MCInst *MI, unsigned index, int64_t Val, cs_arm_op *ops = ARM_get_detail(MI)->operands; int i = ARM_get_detail(MI)->op_count; - assert(i < MAX_ARM_OPS); for (; i > 0 && i > index; --i) { ops[i] = ops[i - 1]; } @@ -1982,6 +1984,7 @@ void ARM_set_detail_op_reg(MCInst *MI, unsigned OpNum, arm_reg Reg) { if (!detail_is_set(MI)) return; + ARM_check_safe_inc(); assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM)); assert(map_get_op_type(MI, OpNum) == CS_OP_REG); @@ -1998,6 +2001,7 @@ void ARM_set_detail_op_imm(MCInst *MI, unsigned OpNum, arm_op_type ImmType, { if (!detail_is_set(MI)) return; + ARM_check_safe_inc(); assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM)); assert(map_get_op_type(MI, OpNum) == CS_OP_IMM); assert(ImmType == ARM_OP_IMM || ImmType == ARM_OP_PIMM || @@ -2107,12 +2111,14 @@ void ARM_set_detail_op_sysop(MCInst *MI, int Val, arm_op_type type, { if (!detail_is_set(MI)) return; + ARM_check_safe_inc(); + ARM_get_detail_op(MI, 0)->type = type; switch (type) { default: assert(0 && "Unknown system operand type."); case ARM_OP_SYSREG: - ARM_get_detail_op(MI, 0)->sysop.reg.mclasssysreg = Val; + ARM_get_detail_op(MI, 0)->sysop.reg.mclasssysreg = Val; // NOLINT(clang-analyzer-optin.core.EnumCastOutOfRange) break; case ARM_OP_BANKEDREG: ARM_get_detail_op(MI, 0)->sysop.reg.bankedreg = Val; @@ -2121,7 +2127,7 @@ void ARM_set_detail_op_sysop(MCInst *MI, int Val, arm_op_type type, case ARM_OP_CPSR: ARM_get_detail_op(MI, 0)->reg = type == ARM_OP_SPSR ? ARM_REG_SPSR : ARM_REG_CPSR; - ARM_get_detail_op(MI, 0)->sysop.psr_bits = Val; + ARM_get_detail_op(MI, 0)->sysop.psr_bits = Val; // NOLINT(clang-analyzer-optin.core.EnumCastOutOfRange) break; } ARM_get_detail_op(MI, 0)->sysop.sysm = Sysm; @@ -2136,6 +2142,8 @@ void ARM_set_detail_op_float(MCInst *MI, unsigned OpNum, uint64_t Imm) { if (!detail_is_set(MI)) return; + ARM_check_safe_inc(); + ARM_get_detail_op(MI, 0)->type = ARM_OP_FP; ARM_get_detail_op(MI, 0)->fp = ARM_AM_getFPImmFloat(Imm); ARM_inc_op_count(MI); diff --git a/arch/Alpha/AlphaGenDisassemblerTables.inc b/arch/Alpha/AlphaGenDisassemblerTables.inc index a67ae33cb2..b00fb1cbff 100644 --- a/arch/Alpha/AlphaGenDisassemblerTables.inc +++ b/arch/Alpha/AlphaGenDisassemblerTables.inc @@ -718,6 +718,7 @@ static bool checkDecoderPredicate(MCInst *Inst, unsigned Idx) { static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ uint64_t Address, const void *Decoder, bool *DecodeComplete) \ { \ + *DecodeComplete = true; \ InsnType tmp; \ switch (Idx) { \ default: /* llvm_unreachable("Invalid index!"); */ \ diff --git a/arch/HPPA/HPPADisassembler.c b/arch/HPPA/HPPADisassembler.c index 7db01d7e93..48a2805a87 100644 --- a/arch/HPPA/HPPADisassembler.c +++ b/arch/HPPA/HPPADisassembler.c @@ -221,8 +221,8 @@ static void push_str_modifier(hppa_ext *hppa, const char *modifier) hppa_modifier *mod = &hppa->modifiers[hppa->mod_num++]; assert(hppa->mod_num <= HPPA_MAX_MODIFIERS_LEN); mod->type = HPPA_MOD_STR; - assert(strlen(modifier) <= HPPA_STR_MODIFIER_LEN); - strcpy(mod->str_mod, modifier); + assert(strlen(modifier) < HPPA_STR_MODIFIER_LEN); + strncpy(mod->str_mod, modifier, HPPA_STR_MODIFIER_LEN - 1); } } @@ -1457,7 +1457,7 @@ static void fill_ldst_w_insn_name(MCInst *MI, uint32_t insn) } } -static void fill_ldst_w_mods(uint32_t insn, hppa_ext *hppa_ext, uint32_t im) +static void fill_ldst_w_mods(uint32_t insn, hppa_ext *hppa_ext, int32_t im) { if (im >= 0) { push_str_modifier(hppa_ext, "mb"); @@ -1470,7 +1470,7 @@ static bool decode_ldst_w(const cs_struct *ud, MCInst *MI, uint32_t insn) { uint32_t opcode = insn >> 26; uint32_t ext = get_insn_bit(insn, 29); - uint32_t im = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); + int32_t im = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); im &= ~3; uint32_t r = get_insn_field(insn, 11, 15); uint32_t b = get_insn_field(insn, 6, 10); @@ -3621,7 +3621,7 @@ static bool decode_load(const cs_struct *ud, MCInst *MI, uint32_t insn) { uint32_t opcode = insn >> 26; if (MODE_IS_HPPA_20(ud->mode)) { - uint32_t d = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); + int32_t d = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); if (opcode == HPPA_OP_TYPE_LDWM) { if (d < 0) { push_str_modifier(HPPA_EXT_REF(MI), "mb"); @@ -3644,7 +3644,7 @@ static bool decode_store(const cs_struct *ud, MCInst *MI, uint32_t insn) uint32_t opcode = insn >> 26; CREATE_GR_REG(MI, get_insn_field(insn, 11, 15)); if (MODE_IS_HPPA_20(ud->mode)) { - uint32_t d = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); + int d = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); if (opcode == HPPA_OP_TYPE_STWM) { if (d < 0) { push_str_modifier(HPPA_EXT_REF(MI), "mb"); @@ -3834,4 +3834,4 @@ bool HPPA_getInstruction(csh ud, const uint8_t *code, size_t code_len, return true; } -#endif \ No newline at end of file +#endif diff --git a/arch/M680X/M680XDisassembler.c b/arch/M680X/M680XDisassembler.c index 6e71c465f3..92bf5d58cb 100644 --- a/arch/M680X/M680XDisassembler.c +++ b/arch/M680X/M680XDisassembler.c @@ -1125,7 +1125,7 @@ static void reg_bits_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) add_insn_group(MI->flat_insn->detail, M680X_GRP_RET); for (bit_index = 0; bit_index < 8; ++bit_index) { - if (reg_bits & (1 << bit_index)) + if (reg_bits & (1 << bit_index) && reg_to_reg_ids) add_reg_operand(info, reg_to_reg_ids[bit_index]); } } @@ -1680,7 +1680,7 @@ static void indexedS16_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) uint16_t offset = 0; read_word(info, &offset, *address); - address += 2; + *address += 2; add_indexed_operand(info, M680X_REG_S, false, 0, M680X_OFFSET_BITS_16, offset, false); @@ -1774,7 +1774,7 @@ static void loop_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) op->type = M680X_OP_RELATIVE; - op->rel.offset = (post_byte & 0x10) ? 0xff00 | rel : rel; + op->rel.offset = (post_byte & 0x10) ? (int16_t) (0xff00 | rel) : rel; op->rel.address = *address + op->rel.offset; diff --git a/arch/M68K/M68KDisassembler.c b/arch/M68K/M68KDisassembler.c index 61d8b3dbf5..51c29d4653 100644 --- a/arch/M68K/M68KDisassembler.c +++ b/arch/M68K/M68KDisassembler.c @@ -321,13 +321,6 @@ static void get_with_index_address_mode(m68k_info *info, cs_m68k_op* op, uint32_ op->mem.base_reg = M68K_REG_INVALID; op->mem.index_reg = M68K_REG_INVALID; - /* Not sure how to deal with this? - if (EXT_EFFECTIVE_ZERO(extension)) { - strcpy(mode, "0"); - break; - } - */ - op->mem.in_disp = EXT_BASE_DISPLACEMENT_PRESENT(extension) ? (EXT_BASE_DISPLACEMENT_LONG(extension) ? read_imm_32(info) : read_imm_16(info)) : 0; op->mem.out_disp = EXT_OUTER_DISPLACEMENT_PRESENT(extension) ? (EXT_OUTER_DISPLACEMENT_LONG(extension) ? read_imm_32(info) : read_imm_16(info)) : 0; diff --git a/arch/MOS65XX/MOS65XXModule.c b/arch/MOS65XX/MOS65XXModule.c index ec89e94c99..841fe35459 100644 --- a/arch/MOS65XX/MOS65XXModule.c +++ b/arch/MOS65XX/MOS65XXModule.c @@ -55,7 +55,7 @@ cs_err MOS65XX_option(cs_struct *handle, cs_opt_type type, size_t value) info->long_m = value & CS_MODE_MOS65XX_65816_LONG_M ? 1 : 0; info->long_x = value & CS_MODE_MOS65XX_65816_LONG_X ? 1 : 0; - handle->mode = (cs_mode)value; + handle->mode = (cs_mode)value; // NOLINT(clang-analyzer-optin.core.EnumCastOutOfRange) break; case CS_OPT_SYNTAX: switch(value) { diff --git a/arch/PowerPC/PPCMapping.c b/arch/PowerPC/PPCMapping.c index 888db80bcc..83e0ed54ce 100644 --- a/arch/PowerPC/PPCMapping.c +++ b/arch/PowerPC/PPCMapping.c @@ -401,6 +401,7 @@ static void add_cs_detail_general(MCInst *MI, ppc_op_group op_group, return; unsigned Val = MCInst_getOpVal(MI, OpNum) << 2; int32_t Imm = SignExtend32(Val, 32); + PPC_check_safe_inc(); PPC_get_detail_op(MI, 0)->type = PPC_OP_IMM; PPC_get_detail_op(MI, 0)->imm = Imm; PPC_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); @@ -424,6 +425,7 @@ static void add_cs_detail_general(MCInst *MI, ppc_op_group op_group, uint64_t Address = MI->address + Imm; if (IS_32BIT(MI->csh->mode)) Address &= 0xffffffff; + PPC_check_safe_inc(); PPC_get_detail_op(MI, 0)->type = PPC_OP_IMM; PPC_get_detail_op(MI, 0)->imm = Address; PPC_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); @@ -566,6 +568,7 @@ void PPC_set_detail_op_reg(MCInst *MI, unsigned OpNum, ppc_reg Reg) { if (!detail_is_set(MI)) return; + PPC_check_safe_inc(); assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM)); assert(map_get_op_type(MI, OpNum) == CS_OP_REG); @@ -581,6 +584,7 @@ void PPC_set_detail_op_imm(MCInst *MI, unsigned OpNum, int64_t Imm) { if (!detail_is_set(MI)) return; + PPC_check_safe_inc(); assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM)); assert(map_get_op_type(MI, OpNum) == CS_OP_IMM); @@ -594,6 +598,7 @@ void PPC_set_mem_access(MCInst *MI, bool status) { if (!detail_is_set(MI)) return; + PPC_check_safe_inc(); if ((!status && !doing_mem(MI)) || (status && doing_mem(MI))) return; // Nothing to do @@ -629,7 +634,7 @@ void PPC_insert_detail_op_imm_at(MCInst *MI, unsigned index, int64_t Val, if (!detail_is_set(MI) || !map_fill_detail_ops(MI)) return; - assert(PPC_get_detail(MI)->op_count < PPC_NUM_OPS); + PPC_check_safe_inc(); cs_ppc_op op; PPC_setup_op(&op); diff --git a/arch/RISCV/RISCVGenAsmWriter.inc b/arch/RISCV/RISCVGenAsmWriter.inc index b4dde75836..c8a6aac644 100644 --- a/arch/RISCV/RISCVGenAsmWriter.inc +++ b/arch/RISCV/RISCVGenAsmWriter.inc @@ -1198,7 +1198,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) // Fragment 0 encoded into 2 bits for 4 unique commands. switch ((uint32_t)((Bits >> 12) & 3)) { - default: CS_ASSERT(0 && "Invalid command number."); + default: + CS_ASSERT(0 && "Invalid command number."); + return; case 0: // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... return; @@ -1226,7 +1228,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) // Fragment 1 encoded into 2 bits for 3 unique commands. switch ((uint32_t)((Bits >> 14) & 3)) { - default: CS_ASSERT(0 && "Invalid command number."); + default: + CS_ASSERT(0 && "Invalid command number."); + return; case 0: // PseudoCALL, PseudoTAIL, C_J, C_JAL, C_JALR, C_JR return; @@ -1247,7 +1251,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) // Fragment 2 encoded into 2 bits for 3 unique commands. switch ((uint32_t)((Bits >> 16) & 3)) { - default: CS_ASSERT(0 && "Invalid command number."); + default: + CS_ASSERT(0 && "Invalid command number."); + return; case 0: // PseudoLA, PseudoLI, PseudoLLA, ADD, ADDI, ADDIW, ADDW, AND, ANDI, AUIP... printOperand(MI, 1, O); @@ -1268,7 +1274,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) // Fragment 3 encoded into 2 bits for 4 unique commands. switch ((uint32_t)((Bits >> 18) & 3)) { - default: CS_ASSERT(0 && "Invalid command number."); + default: + CS_ASSERT(0 && "Invalid command number."); + return; case 0: // PseudoLA, PseudoLI, PseudoLLA, AUIPC, C_BEQZ, C_BNEZ, C_LI, C_LUI, C_M... return; @@ -1468,7 +1476,9 @@ getRegisterName(unsigned RegNo, unsigned AltIdx) }; switch(AltIdx) { - default: CS_ASSERT(0 && "Invalid register alt name index!"); + default: + CS_ASSERT(0 && "Invalid register alt name index!"); + return 0; case RISCV_ABIRegAltName: CS_ASSERT(*(AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]) && "Invalid alt name index for register!"); diff --git a/arch/RISCV/RISCVGenDisassemblerTables.inc b/arch/RISCV/RISCVGenDisassemblerTables.inc index 2efe6960aa..c06f18d655 100644 --- a/arch/RISCV/RISCVGenDisassemblerTables.inc +++ b/arch/RISCV/RISCVGenDisassemblerTables.inc @@ -1736,7 +1736,8 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI,\ NumToSkip |= (*Ptr++) << 8;\ NumToSkip |= (*Ptr++) << 16;\ \ - MCInst TmpMI;\ + MCInst TmpMI = { 0 }; \ + MCInst_Init(&TmpMI, CS_ARCH_RISCV); \ MCInst_setOpcode(&TmpMI, Opc);\ bool DecodeComplete = false;\ S = decoder(S, DecodeIdx, insn, &TmpMI, Address, DisAsm, &DecodeComplete);\ diff --git a/arch/SH/SHDisassembler.c b/arch/SH/SHDisassembler.c index 8f788096b4..76d5e4c02f 100644 --- a/arch/SH/SHDisassembler.c +++ b/arch/SH/SHDisassembler.c @@ -99,7 +99,7 @@ static void set_groups(cs_detail *detail, int n, ...) va_start(g, n); while (n > 0) { sh_insn_group grp; - grp = va_arg(g, sh_insn_group); + grp = va_arg(g, sh_insn_group); // NOLINT(clang-analyzer-valist.Uninitialized) if (detail) { detail->groups[detail->groups_count] = grp; detail->groups_count++; @@ -934,7 +934,7 @@ static bool op4xxb(uint16_t code, uint64_t address, MCInst *MI, cs_mode mode, rw = write; break; case 2: - insn = SH_INS_JMP; + MCInst_setOpcode(MI, SH_INS_JMP); grp = SH_GRP_JUMP; break; case 8: @@ -1605,6 +1605,9 @@ static bool set_dsp_move_d(sh_info *info, int xy, uint16_t code, cs_mode mode, c int op; static const sh_reg base[] = {SH_REG_DSP_A0, SH_REG_DSP_X0}; switch (xy) { + default: + printf("Invalid xy value %" PRId32 "\n", xy); + return MCDisassembler_Fail; case 0: op = (code >> 2) & 3; dir = 1 - ((code >> 5) & 1); @@ -1762,14 +1765,14 @@ static void set_reg_dsp_write_z(sh_info *info, int pos, int r, } static bool dsp_op_cc_3opr(uint32_t code, sh_info *info, sh_dsp_insn insn, - sh_dsp_insn_type insn2, cs_detail *detail) + sh_dsp_insn insn2, cs_detail *detail) { info->op.operands[2].dsp.cc = (code >> 8) & 3; if (info->op.operands[2].dsp.cc > 0) { info->op.operands[2].dsp.insn = insn; } else { if (insn2 != SH_INS_DSP_INVALID) - info->op.operands[2].dsp.insn = (sh_dsp_insn) insn2; + info->op.operands[2].dsp.insn = insn2; else return MCDisassembler_Fail; } @@ -1914,11 +1917,11 @@ static bool decode_dsp_3op(const uint32_t code, sh_info *info, } case 0x08: return dsp_op_cc_3opr(code, info, - SH_INS_DSP_PSUB, (sh_dsp_insn_type) SH_INS_DSP_PSUBC, + SH_INS_DSP_PSUB, SH_INS_DSP_PSUBC, detail); case 0x09: return dsp_op_cc_3opr(code, info, - SH_INS_DSP_PXOR, (sh_dsp_insn_type) SH_INS_DSP_PWSB, + SH_INS_DSP_PXOR, SH_INS_DSP_PWSB, detail); case 0x0a: switch(sx) { @@ -1958,7 +1961,7 @@ static bool decode_dsp_3op(const uint32_t code, sh_info *info, case 0x0d: return dsp_op_cc_3opr(code, info, SH_INS_DSP_POR, - (sh_dsp_insn_type) SH_INS_DSP_PWAD, + SH_INS_DSP_PWAD, detail); case 0x0e: if (cc == 0) { diff --git a/arch/Sparc/SparcInstPrinter.c b/arch/Sparc/SparcInstPrinter.c index 9ea8129ece..c7d13d4eff 100644 --- a/arch/Sparc/SparcInstPrinter.c +++ b/arch/Sparc/SparcInstPrinter.c @@ -73,7 +73,7 @@ static void set_mem_access(MCInst *MI, bool status) } } -void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) +void Sparc_post_printer(csh ud, cs_insn *insn, SStream *insn_asm, MCInst *mci) { if (((cs_struct *)ud)->detail_opt != CS_OPT_ON) return; @@ -81,8 +81,10 @@ void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) // fix up some instructions if (insn->id == SPARC_INS_CASX) { // first op is actually a memop, not regop + uint8_t base = (uint8_t)insn->detail->sparc.operands[0].reg; + memset(&insn->detail->sparc.operands[0], 0, sizeof(cs_sparc_op)); insn->detail->sparc.operands[0].type = SPARC_OP_MEM; - insn->detail->sparc.operands[0].mem.base = (uint8_t)insn->detail->sparc.operands[0].reg; + insn->detail->sparc.operands[0].mem.base = base; insn->detail->sparc.operands[0].mem.disp = 0; } } @@ -333,7 +335,7 @@ static void printCCOperand(MCInst *MI, int opNum, SStream *O) SStream_concat0(O, SPARCCondCodeToString((sparc_cc)CC)); if (MI->csh->detail_opt) - MI->flat_insn->detail->sparc.cc = (sparc_cc)CC; + MI->flat_insn->detail->sparc.cc = (sparc_cc)CC; // NOLINT(clang-analyzer-optin.core.EnumCastOutOfRange) } diff --git a/arch/Sparc/SparcInstPrinter.h b/arch/Sparc/SparcInstPrinter.h index 4cd891ee41..eefc8a5845 100644 --- a/arch/Sparc/SparcInstPrinter.h +++ b/arch/Sparc/SparcInstPrinter.h @@ -10,7 +10,7 @@ void Sparc_printInst(MCInst *MI, SStream *O, void *Info); -void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); +void Sparc_post_printer(csh ud, cs_insn *insn, SStream *insn_asm, MCInst *mci); void Sparc_addReg(MCInst *MI, int reg); diff --git a/arch/TMS320C64x/TMS320C64xDisassembler.c b/arch/TMS320C64x/TMS320C64xDisassembler.c index 2829187833..fe265a7acd 100644 --- a/arch/TMS320C64x/TMS320C64xDisassembler.c +++ b/arch/TMS320C64x/TMS320C64xDisassembler.c @@ -269,8 +269,8 @@ static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val, if((base >= TMS320C64X_REG_A0) && (base <= TMS320C64X_REG_A31)) base = (base - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); - else if((base >= TMS320C64X_REG_B0) && (base <= TMS320C64X_REG_B31)) - base = (base - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); + // base cannot be a B register, because it was ANDed above with 0x1f. + // And the TMS320C64X_REG_B0 > 31 basereg = getReg(GPRegsDecoderTable, base); if (basereg == ~0U) return MCDisassembler_Fail; @@ -292,8 +292,8 @@ static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val, case 15: if((offset >= TMS320C64X_REG_A0) && (offset <= TMS320C64X_REG_A31)) offset = (offset - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); - else if((offset >= TMS320C64X_REG_B0) && (offset <= TMS320C64X_REG_B31)) - offset = (offset - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); + // offset cannot be a B register, because it was ANDed above with 0x1f. + // And the TMS320C64X_REG_B0 > 31 offsetreg = getReg(GPRegsDecoderTable, offset); if (offsetreg == ~0U) return MCDisassembler_Fail; diff --git a/arch/TMS320C64x/TMS320C64xInstPrinter.c b/arch/TMS320C64x/TMS320C64xInstPrinter.c index 3e20e2b36b..e4b807eb44 100644 --- a/arch/TMS320C64x/TMS320C64xInstPrinter.c +++ b/arch/TMS320C64x/TMS320C64xInstPrinter.c @@ -3,17 +3,6 @@ #ifdef CAPSTONE_HAS_TMS320C64X -#ifdef _MSC_VER -// Disable security warnings for strcpy -#ifndef _CRT_SECURE_NO_WARNINGS -#define _CRT_SECURE_NO_WARNINGS -#endif - -// Banned API Usage : strcpy is a Banned API as listed in dontuse.h for -// security purposes. -#pragma warning(disable:28719) -#endif - #include #include @@ -33,10 +22,11 @@ static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O); static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O); static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O); -void TMS320C64x_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) +void TMS320C64x_post_printer(csh ud, cs_insn *insn, SStream *insn_asm, MCInst *mci) { SStream ss; - char *p, *p2, tmp[8]; + const char *op_str_ptr, *p2; + char tmp[8] = { 0 }; unsigned int unit = 0; int i; cs_tms320c64x *tms320c64x; @@ -71,50 +61,56 @@ void TMS320C64x_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID) SStream_concat(&ss, "[%c%s]|", (tms320c64x->condition.zero == 1) ? '!' : '|', cs_reg_name(ud, tms320c64x->condition.reg)); - p = strchr(insn_asm, '\t'); - if (p != NULL) - *p++ = '\0'; + // Sorry for all the fixes below. I don't have time to add more helper SStream functions. + // Before that they messed around with the private buffer of th stream. + // So it is better now. But still not effecient. + op_str_ptr = strchr(SStream_rbuf(insn_asm), '\t'); - SStream_concat0(&ss, insn_asm); - if ((p != NULL) && (((p2 = strchr(p, '[')) != NULL) || ((p2 = strchr(p, '(')) != NULL))) { - while ((p2 > p) && ((*p2 != 'a') && (*p2 != 'b'))) + if ((op_str_ptr != NULL) && (((p2 = strchr(op_str_ptr, '[')) != NULL) || ((p2 = strchr(op_str_ptr, '(')) != NULL))) { + while ((p2 > op_str_ptr) && ((*p2 != 'a') && (*p2 != 'b'))) p2--; - if (p2 == p) { - strcpy(insn_asm, "Invalid!"); + if (p2 == op_str_ptr) { + SStream_Flush(insn_asm, NULL); + SStream_concat0(insn_asm, "Invalid!"); return; } if (*p2 == 'a') - strcpy(tmp, "1T"); + strncpy(tmp, "1T", sizeof(tmp)); else - strcpy(tmp, "2T"); + strncpy(tmp, "2T", sizeof(tmp)); } else { tmp[0] = '\0'; } + SStream mnem_post = { 0 }; + SStream_Init(&mnem_post); switch(tms320c64x->funit.unit) { case TMS320C64X_FUNIT_D: - SStream_concat(&ss, ".D%s%u", tmp, tms320c64x->funit.side); + SStream_concat(&mnem_post, ".D%s%u", tmp, tms320c64x->funit.side); break; case TMS320C64X_FUNIT_L: - SStream_concat(&ss, ".L%s%u", tmp, tms320c64x->funit.side); + SStream_concat(&mnem_post, ".L%s%u", tmp, tms320c64x->funit.side); break; case TMS320C64X_FUNIT_M: - SStream_concat(&ss, ".M%s%u", tmp, tms320c64x->funit.side); + SStream_concat(&mnem_post, ".M%s%u", tmp, tms320c64x->funit.side); break; case TMS320C64X_FUNIT_S: - SStream_concat(&ss, ".S%s%u", tmp, tms320c64x->funit.side); + SStream_concat(&mnem_post, ".S%s%u", tmp, tms320c64x->funit.side); break; } if (tms320c64x->funit.crosspath > 0) - SStream_concat0(&ss, "X"); + SStream_concat0(&mnem_post, "X"); - if (p != NULL) - SStream_concat(&ss, "\t%s", p); + if (op_str_ptr != NULL) { + // There is an op_str + SStream_concat1(&mnem_post, '\t'); + SStream_replc_str(insn_asm, '\t', SStream_rbuf(&mnem_post)); + } if (tms320c64x->parallel != 0) - SStream_concat0(&ss, "\t||"); - - /* insn_asm is a buffer from an SStream, so there should be enough space */ - strcpy(insn_asm, ss.buffer); + SStream_concat0(insn_asm, "\t||"); + SStream_concat0(&ss, SStream_rbuf(insn_asm)); + SStream_Flush(insn_asm, NULL); + SStream_concat0(insn_asm, SStream_rbuf(&ss)); } } diff --git a/arch/TMS320C64x/TMS320C64xInstPrinter.h b/arch/TMS320C64x/TMS320C64xInstPrinter.h index 3a79139e8c..bf8318e282 100644 --- a/arch/TMS320C64x/TMS320C64xInstPrinter.h +++ b/arch/TMS320C64x/TMS320C64xInstPrinter.h @@ -10,6 +10,6 @@ void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info); -void TMS320C64x_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); +void TMS320C64x_post_printer(csh ud, cs_insn *insn, SStream *insn_asm, MCInst *mci); #endif diff --git a/arch/TriCore/TriCoreDisassembler.c b/arch/TriCore/TriCoreDisassembler.c index 40aad5e684..3a06c26d5c 100644 --- a/arch/TriCore/TriCoreDisassembler.c +++ b/arch/TriCore/TriCoreDisassembler.c @@ -766,13 +766,13 @@ static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn, status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], Decoder); break; + } default: status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder); } - if (status != MCDisassembler_Success) - return status; - } + if (status != MCDisassembler_Success) + return status; } } diff --git a/arch/TriCore/TriCoreInstPrinter.c b/arch/TriCore/TriCoreInstPrinter.c index 342ee89563..225d9b611c 100644 --- a/arch/TriCore/TriCoreInstPrinter.c +++ b/arch/TriCore/TriCoreInstPrinter.c @@ -277,8 +277,8 @@ static void printDisp24Imm(MCInst *MI, int OpNum, SStream *O) case TRICORE_JA_b: case TRICORE_JLA_b: // = {disp24[23:20], 7’b0000000, disp24[19:0], 1’b0}; - res = ((wrapping_u32(disp) & 0xf00000) << 28) | - ((wrapping_u32(disp) & 0xfffff) << 1); + res = ((wrapping_u32(disp) & 0xf00000ULL) << 28) | + ((wrapping_u32(disp) & 0xfffffULL) << 1); break; case TRICORE_J_b: case TRICORE_JL_b: @@ -346,7 +346,7 @@ static void printDisp8Imm(MCInst *MI, int OpNum, SStream *O) int64_t res = 0; switch (MCInst_getOpcode(MI)) { case TRICORE_CALL_sb: - disp = DISP1(8); + res = DISP1(8); break; case TRICORE_J_sb: case TRICORE_JNZ_sb: diff --git a/arch/WASM/WASMDisassembler.c b/arch/WASM/WASMDisassembler.c index a05ee0c757..e04297dacb 100644 --- a/arch/WASM/WASMDisassembler.c +++ b/arch/WASM/WASMDisassembler.c @@ -459,9 +459,6 @@ static bool read_memoryimmediate(const uint8_t *code, size_t code_len, uint16_t len = tmp; data[1] = get_varuint32(&code[len], code_len - len, &tmp); - if (len == -1) { - return false; - } if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.operands[1].type = WASM_OP_VARUINT32; diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c index 6bff62062f..9840ed0bd9 100644 --- a/arch/X86/X86ATTInstPrinter.c +++ b/arch/X86/X86ATTInstPrinter.c @@ -582,8 +582,9 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) int64_t imm = MCOperand_getImm(Op); uint8_t opsize = X86_immediate_size(MCInst_getOpcode(MI), &encsize); - if (opsize == 1) // print 1 byte immediate in positive form + if (opsize == 1) { // print 1 byte immediate in positive form imm = imm & 0xff; + } switch(MI->flat_insn->id) { default: @@ -598,9 +599,9 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) switch(opsize) { default: break; - case 1: - imm &= 0xff; - break; + // case 1 cannot occur because above imm was ANDed with 0xff, + // making it effectively always positive. + // So this switch is never reached. case 2: imm &= 0xffff; break; diff --git a/arch/X86/X86Mapping.c b/arch/X86/X86Mapping.c index 46ecfcb77b..b0935892cd 100644 --- a/arch/X86/X86Mapping.c +++ b/arch/X86/X86Mapping.c @@ -2246,7 +2246,7 @@ unsigned short X86_register_map(unsigned short id) /// The post-printer function. Used to fixup flaws in the disassembly information /// of certain instructions. -void X86_postprinter(csh handle, cs_insn *insn, char *mnem, MCInst *mci) { +void X86_postprinter(csh handle, cs_insn *insn, SStream *mnem, MCInst *mci) { if (!insn || !insn->detail) { return; } diff --git a/arch/X86/X86Mapping.h b/arch/X86/X86Mapping.h index 933f208dfa..f9a50513ac 100644 --- a/arch/X86/X86Mapping.h +++ b/arch/X86/X86Mapping.h @@ -91,6 +91,6 @@ unsigned short X86_register_map(unsigned short id); unsigned int find_insn(unsigned int id); -void X86_postprinter(csh handle, cs_insn *insn, char *mnem, MCInst *mci); +void X86_postprinter(csh handle, cs_insn *insn, SStream *mnem, MCInst *mci); #endif diff --git a/arch/XCore/XCoreInstPrinter.c b/arch/XCore/XCoreInstPrinter.c index 4a02c2bede..4a1e4ed18a 100644 --- a/arch/XCore/XCoreInstPrinter.c +++ b/arch/XCore/XCoreInstPrinter.c @@ -16,11 +16,6 @@ #ifdef CAPSTONE_HAS_XCORE -#ifdef _MSC_VER -#pragma warning(disable : 4996) // disable MSVC's warning on strcpy() -#pragma warning(disable : 28719) // disable MSVC's warning on strcpy() -#endif - #include #include #include @@ -36,7 +31,7 @@ static const char *getRegisterName(unsigned RegNo); -void XCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) +void XCore_post_printer(csh ud, cs_insn *insn, SStream *insn_asm, MCInst *mci) { /* if (((cs_struct *)ud)->detail != CS_OPT_ON) @@ -51,7 +46,7 @@ void XCore_insn_extract(MCInst *MI, const char *code) char *p, *p2; char tmp[128]; - strcpy(tmp, code); // safe because code is way shorter than 128 bytes + strncpy(tmp, code, sizeof(tmp) - 1); // safe because code is way shorter than 128 bytes // find the first space p = strchr(tmp, ' '); @@ -167,8 +162,10 @@ static void set_mem_access(MCInst *MI, bool status, int reg) } else { // the last op should be the memory base MI->flat_insn->detail->xcore.op_count--; + uint8_t base = MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg; + memset(&MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count], 0, sizeof(cs_xcore_op)); MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM; - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg; + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = base; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0; if (reg > 0) diff --git a/arch/XCore/XCoreInstPrinter.h b/arch/XCore/XCoreInstPrinter.h index f9d0001316..4d5a5e0a07 100644 --- a/arch/XCore/XCoreInstPrinter.h +++ b/arch/XCore/XCoreInstPrinter.h @@ -10,7 +10,7 @@ void XCore_printInst(MCInst *MI, SStream *O, void *Info); -void XCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); +void XCore_post_printer(csh ud, cs_insn *insn, SStream *insn_asm, MCInst *mci); // extract details from assembly code @code void XCore_insn_extract(MCInst *MI, const char *code); diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py index ce3d026945..4e2f765aca 100755 --- a/bindings/python/capstone/__init__.py +++ b/bindings/python/capstone/__init__.py @@ -1129,8 +1129,8 @@ def option(self, opt_type, opt_value): status = _cs.cs_option(self.csh, opt_type, opt_value) if status != CS_ERR_OK: raise CsError(status) - if opt_type == CS_OPT_DETAIL: - self._detail = opt_value == CS_OPT_ON + if opt_type == CS_OPT_DETAIL or opt_type == CS_OPT_DETAIL_REAL: + self._detail = (opt_value & CS_OPT_ON) != 0 elif opt_type == CS_OPT_SKIPDATA: self._skipdata = opt_value == CS_OPT_ON elif opt_type == CS_OPT_UNSIGNED: diff --git a/bindings/python/capstone/arm_const.py b/bindings/python/capstone/arm_const.py index dbc09e3bd9..cd5da0b6c9 100644 --- a/bindings/python/capstone/arm_const.py +++ b/bindings/python/capstone/arm_const.py @@ -21,6 +21,8 @@ ARMVCC_None = 0 ARMVCC_Then = 1 ARMVCC_Else = 2 + +ARM_PredBlockMaskInvalid = 0 ARM_T = 0x8 ARM_TT = 0x4 ARM_TE = 0xc diff --git a/bindings/python/capstone/hppa_const.py b/bindings/python/capstone/hppa_const.py index e5bca15446..789a99a977 100644 --- a/bindings/python/capstone/hppa_const.py +++ b/bindings/python/capstone/hppa_const.py @@ -1,6 +1,5 @@ from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [hppa_const.py] -HPPA_MAX_OPS = 5 HPPA_STR_MODIFIER_LEN = 8 HPPA_MAX_MODIFIERS_LEN = 5 diff --git a/bindings/python/capstone/sh_const.py b/bindings/python/capstone/sh_const.py index 3d7faf4e31..d604f5c1bf 100644 --- a/bindings/python/capstone/sh_const.py +++ b/bindings/python/capstone/sh_const.py @@ -142,9 +142,6 @@ SH_OP_MEM_TBR_DISP = 9 SH_INS_DSP_INVALID = 0 -SH_INS_DSP_DOUBLE = 1 -SH_INS_DSP_SINGLE = 2 -SH_INS_DSP_PARALLEL = 3 SH_INS_DSP_NOP = 1 SH_INS_DSP_MOV = 2 SH_INS_DSP_PSHL = 3 diff --git a/bindings/python/capstone/systemz_const.py b/bindings/python/capstone/systemz_const.py index 5a72b5878e..8ce8c230d2 100644 --- a/bindings/python/capstone/systemz_const.py +++ b/bindings/python/capstone/systemz_const.py @@ -15,6 +15,7 @@ SYSTEMZ_CC_LE = 11 SYSTEMZ_CC_NH = 12 SYSTEMZ_CC_NO = 13 +SYSTEMZ_CC_INVALID = 14 SYSTEMZ_OP_INVALID = CS_OP_INVALID SYSTEMZ_OP_REG = CS_OP_REG SYSTEMZ_OP_IMM = CS_OP_IMM diff --git a/bindings/python/capstone/tricore_const.py b/bindings/python/capstone/tricore_const.py index cb0fdf709e..d0672f0759 100644 --- a/bindings/python/capstone/tricore_const.py +++ b/bindings/python/capstone/tricore_const.py @@ -4,7 +4,6 @@ TRICORE_OP_REG = CS_OP_REG TRICORE_OP_IMM = CS_OP_IMM TRICORE_OP_MEM = CS_OP_MEM -TRICORE_OP_COUNT = 8 TRICORE_REG_INVALID = 0 TRICORE_REG_FCX = 1 diff --git a/cs.c b/cs.c index 3ebe390070..405f6aed15 100644 --- a/cs.c +++ b/cs.c @@ -1,9 +1,7 @@ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ -#ifdef _MSC_VER -#pragma warning(disable:4996) // disable MSVC's warning on strcpy() -#pragma warning(disable:28719) // disable MSVC's warning on strcpy() -#endif + +#include "SStream.h" #if defined(CAPSTONE_HAS_OSXKERNEL) #include #include @@ -866,35 +864,14 @@ static int str_replace(char *result, char *target, const char *str1, char *str2) } #endif -/// The asm string sometimes has a leading space or tab. -/// Here we remove it. -static void fixup_asm_string(char *asm_str) { - if (!asm_str) { - return; - } - int i = 0; - int k = 0; - bool text_reached = (asm_str[0] != ' ' && asm_str[0] != '\t'); - while (asm_str[i]) { - if (!text_reached && (asm_str[i] == ' ' || asm_str[i] == '\t')) { - ++i; - text_reached = true; - continue; - } - asm_str[k] = asm_str[i]; - ++k, ++i; - } - asm_str[k] = '\0'; -} - // fill insn with mnemonic & operands info -static void fill_insn(struct cs_struct *handle, cs_insn *insn, char *buffer, MCInst *mci, +static void fill_insn(struct cs_struct *handle, cs_insn *insn, SStream *OS, MCInst *mci, PostPrinter_t postprinter, const uint8_t *code) { #ifndef CAPSTONE_DIET - char *sp, *mnem; + char *sp; #endif - fixup_asm_string(buffer); + SStream_trimls(OS); uint16_t copy_size = MIN(sizeof(insn->bytes), insn->size); // fill the instruction bytes. @@ -909,23 +886,17 @@ static void fill_insn(struct cs_struct *handle, cs_insn *insn, char *buffer, MCI // post printer handles some corner cases (hacky) if (postprinter) - postprinter((csh)handle, insn, buffer, mci); + postprinter((csh)handle, insn, OS, mci); #ifndef CAPSTONE_DIET - mnem = insn->mnemonic; - // memset(mnem, 0, CS_MNEMONIC_SIZE); - for (sp = buffer; *sp; sp++) { - if (*sp == ' '|| *sp == '\t') - break; + memset(insn->mnemonic, '\0', sizeof(insn->mnemonic)); + memset(insn->op_str, '\0', sizeof(insn->op_str)); + SStream_extract_mnem_opstr(OS, insn->mnemonic, sizeof(insn->mnemonic), insn->op_str, sizeof(insn->op_str)); + for (sp = insn->mnemonic; *sp; sp++) { if (*sp == '|') // lock|rep prefix for x86 *sp = ' '; - // copy to @mnemonic - *mnem = *sp; - mnem++; } - *mnem = '\0'; - // we might have customized mnemonic if (handle->mnem_list) { struct insn_mnem *tmp = handle->mnem_list; @@ -944,17 +915,6 @@ static void fill_insn(struct cs_struct *handle, cs_insn *insn, char *buffer, MCI tmp = tmp->next; } } - - // copy @op_str - if (*sp) { - // find the next non-space char - sp++; - for (; ((*sp == ' ') || (*sp == '\t')); sp++); - strncpy(insn->op_str, sp, sizeof(insn->op_str) - 1); - insn->op_str[sizeof(insn->op_str) - 1] = '\0'; - } else - insn->op_str[0] = '\0'; - #endif } @@ -1279,7 +1239,7 @@ size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64 handle->insn_id(handle, insn_cache, mci.Opcode); handle->printer(&mci, &ss, handle->printer_info); - fill_insn(handle, insn_cache, ss.buffer, &mci, handle->post_printer, buffer); + fill_insn(handle, insn_cache, &ss, &mci, handle->post_printer, buffer); // adjust for pseudo opcode (X86) if (handle->arch == CS_ARCH_X86 && insn_cache->id != X86_INS_VCMP) @@ -1485,7 +1445,7 @@ bool CAPSTONE_API cs_disasm_iter(csh ud, const uint8_t **code, size_t *size, handle->printer(&mci, &ss, handle->printer_info); - fill_insn(handle, insn, ss.buffer, &mci, handle->post_printer, *code); + fill_insn(handle, insn, &ss, &mci, handle->post_printer, *code); // adjust for pseudo opcode (X86) if (handle->arch == CS_ARCH_X86) diff --git a/cs_priv.h b/cs_priv.h index c4866ddfd5..954acaed9c 100644 --- a/cs_priv.h +++ b/cs_priv.h @@ -16,7 +16,7 @@ typedef void (*Printer_t)(MCInst *MI, SStream *OS, void *info); // function to be called after Printer_t // this is the best time to gather insn's characteristics -typedef void (*PostPrinter_t)(csh handle, cs_insn *, char *mnem, MCInst *mci); +typedef void (*PostPrinter_t)(csh handle, cs_insn *, SStream *mnem, MCInst *mci); typedef bool (*Disasm_t)(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); diff --git a/cstool/cstool.c b/cstool/cstool.c index 48327d9d2e..78312b99d6 100644 --- a/cstool/cstool.c +++ b/cstool/cstool.c @@ -347,7 +347,6 @@ static void usage(char *prog) printf(" -a Print Capstone register alias (if any). Otherwise LLVM register names are emitted.\n"); printf(" -s decode in SKIPDATA mode\n"); printf(" -u show immediates as unsigned\n"); - printf(" -f Dev fuzzing: Disassembles to 0xffffffff.\n\n"); printf(" -v show version & Capstone core build info\n\n"); } @@ -439,53 +438,6 @@ static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins) printf("\n"); } -static uint32_t read_le(uint8_t *buf, size_t size) { - uint32_t res = 0; - for (size_t i = 0, j = size - 1; i < size; ++i, --j) { - res |= buf[i] << j * 8; - } - return res; -} - -static void to_buf(uint32_t num, uint8_t *buf) { - for (size_t i = 0, j = 3; i < 4; ++i, --j) { - buf[i] = (num >> j) & 0xff; - } -} - -static void run_dev_fuzz(csh handle, uint8_t *bytes, uint32_t size) { - uint8_t buf[4] = {0}; - uint32_t bytes_as_num = read_le(bytes, size); - uint32_t address = 0xffffffff; - - printf("Run dev fuzz\n"); - printf("Start: 0x%" PRIx32 "\n", bytes_as_num); - printf("End: 0xffffffff\n" - "Address: 0x%" PRIx32 "\n", address); - - cs_insn *insn; - while (true) { - printf("\rProgress: 0x%08x\t\t", bytes_as_num); - fflush(stdout); - cs_disasm(handle, buf, 4, address, 0, &insn); - if (insn && insn->detail) - free(insn->detail); - free(insn); - bytes_as_num++; - to_buf(bytes_as_num, buf); - if (bytes_as_num == 0xffffffff) { - printf("\rProgress: 0x%08x\t\t", bytes_as_num); - fflush(stdout); - cs_disasm(handle, (uint8_t*)&buf, 4, address, 0, &insn); - if (insn && insn->detail) - free(insn->detail); - free(insn); - printf("\n"); - return; - } - } -} - static cs_mode find_additional_modes(const char *input, cs_arch arch) { if (!input) { return 0; @@ -541,7 +493,6 @@ int main(int argc, char **argv) bool skipdata = false; bool custom_reg_alias = false; bool set_real_detail = false; - bool dev_fuzz = false; int args_left; while ((c = getopt (argc, argv, "rasudhvf")) != -1) { @@ -659,9 +610,6 @@ int main(int argc, char **argv) printf("\n"); return 0; - case 'f': - dev_fuzz = true; - break; case 'h': usage(argv[0]); return 0; @@ -745,13 +693,7 @@ int main(int argc, char **argv) } if (set_real_detail) { - cs_option(handle, CS_OPT_DETAIL, CS_OPT_DETAIL_REAL); - } - - if (dev_fuzz) { - run_dev_fuzz(handle, assembly, size); - cs_close(&handle); - return 0; + cs_option(handle, CS_OPT_DETAIL, (CS_OPT_DETAIL_REAL | CS_OPT_ON)); } count = cs_disasm(handle, assembly, size, address, 0, &insn); diff --git a/cstool/cstool_aarch64.c b/cstool/cstool_aarch64.c index 294193a587..3b6f194c1a 100644 --- a/cstool/cstool_aarch64.c +++ b/cstool/cstool_aarch64.c @@ -28,6 +28,7 @@ void print_insn_detail_aarch64(csh handle, cs_insn *ins) cs_aarch64_op *op = &(aarch64->operands[i]); switch(op->type) { default: + printf("\t\tOperand type %" PRId32 " not handled\n", op->type); break; case AARCH64_OP_REG: printf("\t\toperands[%u].type: REG = %s%s\n", i, cs_reg_name(handle, op->reg), op->is_vreg ? " (vreg)" : ""); diff --git a/cstool/cstool_arm.c b/cstool/cstool_arm.c index 439d11063e..134a36398b 100644 --- a/cstool/cstool_arm.c +++ b/cstool/cstool_arm.c @@ -82,11 +82,12 @@ void print_insn_detail_arm(csh handle, cs_insn *ins) printf("\t\toperands[%u].type: MASK = %" PRIu8 "\n", i, op->sysop.msr_mask); break; case ARM_OP_BANKEDREG: - // FIXME: Printing the name is currenliy not supported if the encodings overlap + // FIXME: Printing the name is currently not supported if the encodings overlap // with system registers. printf("\t\toperands[%u].type: BANKEDREG = %" PRIu32 "\n", i, (uint32_t) op->sysop.reg.bankedreg); if (op->sysop.msr_mask != UINT8_MAX) printf("\t\toperands[%u].type: MASK = %" PRIu8 "\n", i, op->sysop.msr_mask); + break; case ARM_OP_SPSR: case ARM_OP_CPSR: { const char type = op->type == ARM_OP_SPSR ? 'S' : 'C'; diff --git a/cstool/cstool_systemz.c b/cstool/cstool_systemz.c index 90ed798775..0aae05cce2 100644 --- a/cstool/cstool_systemz.c +++ b/cstool/cstool_systemz.c @@ -39,11 +39,7 @@ void print_insn_detail_systemz(csh handle, cs_insn *ins) printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index)); if (op->mem.length != 0) { - if (op->mem.am == SYSTEMZ_AM_BDL) { - printf("\t\t\toperands[%u].mem.length: 0x%" PRIx64 "\n", i, op->mem.length); - } else { - printf("\t\t\toperands[%u].mem.length: 0x%" PRIx64 "\n", i, op->mem.length); - } + printf("\t\t\toperands[%u].mem.length: 0x%" PRIx64 "\n", i, op->mem.length); } printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp); switch(op->mem.am) { diff --git a/cstool/cstool_x86.c b/cstool/cstool_x86.c index bba46d848b..fa1ded3b51 100644 --- a/cstool/cstool_x86.c +++ b/cstool/cstool_x86.c @@ -240,6 +240,10 @@ void print_insn_detail_x86(csh ud, cs_mode mode, cs_insn *ins) printf("\timm_count: %u\n", count); for (i = 1; i < count + 1; i++) { int index = cs_op_index(ud, ins, X86_OP_IMM, i); + if (index < 0) { + printf("Operand was not found!\n"); + break; + } printf("\t\timms[%u]: 0x%" PRIx64 "\n", i, x86->operands[index].imm); } } diff --git a/docs/cs_v6_release_guide.md b/docs/cs_v6_release_guide.md index 7d1e732c85..24df9a6e15 100644 --- a/docs/cs_v6_release_guide.md +++ b/docs/cs_v6_release_guide.md @@ -338,7 +338,7 @@ Additionally, you can now choose between the alias details and the real details. If you always want the real instruction detail decoded (also for alias instructions), you can enable the option with ``` -cs_option(handle, CS_OPT_DETAIL, CS_OPT_DETAIL_REAL); +cs_option(handle, CS_OPT_DETAIL, CS_OPT_DETAIL_REAL | CS_OPT_ON); ``` For the `cstool` you can enable it with the `-r` flag. diff --git a/include/capstone/aarch64.h b/include/capstone/aarch64.h index 83fc7faf3e..cae337a80d 100644 --- a/include/capstone/aarch64.h +++ b/include/capstone/aarch64.h @@ -2852,7 +2852,7 @@ typedef struct { cs_ac_type mem_acc; ///< CGI memory access according to mayLoad and mayStore } aarch64_suppl_info; -#define MAX_AARCH64_OPS 8 +#define NUM_AARCH64_OPS 16 /// Instruction structure typedef struct cs_aarch64 { @@ -2865,7 +2865,7 @@ typedef struct cs_aarch64 { /// or 0 when instruction has no operand. uint8_t op_count; - cs_aarch64_op operands[MAX_AARCH64_OPS]; ///< operands for this instruction. + cs_aarch64_op operands[NUM_AARCH64_OPS]; ///< operands for this instruction. } cs_aarch64; /// AArch64 instruction diff --git a/include/capstone/alpha.h b/include/capstone/alpha.h index 839ce02b41..3d36cba380 100644 --- a/include/capstone/alpha.h +++ b/include/capstone/alpha.h @@ -19,7 +19,7 @@ extern "C" { #pragma warning(disable : 4201) #endif -#define MAX_ALPHA_OPS 3 +#define NUM_ALPHA_OPS 3 //> Operand type for instruction's operands typedef enum alpha_op_type { @@ -43,7 +43,7 @@ typedef struct cs_alpha { // Number of operands of this instruction, // or 0 when instruction has no operand. uint8_t op_count; - cs_alpha_op operands[MAX_ALPHA_OPS]; // operands for this instruction. + cs_alpha_op operands[NUM_ALPHA_OPS]; // operands for this instruction. } cs_alpha; diff --git a/include/capstone/arm.h b/include/capstone/arm.h index 3824da4472..24430c2710 100644 --- a/include/capstone/arm.h +++ b/include/capstone/arm.h @@ -125,6 +125,7 @@ typedef enum VPTCodes { /// Txy = xy10 /// Txyz = xyz1 typedef enum PredBlockMask { + ARM_PredBlockMaskInvalid = 0, ARM_T = 0x8, // 0b1000 ARM_TT = 0x4, // 0b0100 ARM_TE = 0xc, // 0b1100 @@ -890,7 +891,7 @@ typedef struct cs_arm_op { int8_t neon_lane; } cs_arm_op; -#define MAX_ARM_OPS 36 +#define NUM_ARM_OPS 36 /// Instruction structure typedef struct cs_arm { @@ -910,7 +911,7 @@ typedef struct cs_arm { /// or 0 when instruction has no operand. uint8_t op_count; - cs_arm_op operands[MAX_ARM_OPS]; ///< operands for this instruction. + cs_arm_op operands[NUM_ARM_OPS]; ///< operands for this instruction. } cs_arm; /// ARM instruction diff --git a/include/capstone/hppa.h b/include/capstone/hppa.h index fffb6ef73d..097126d91b 100644 --- a/include/capstone/hppa.h +++ b/include/capstone/hppa.h @@ -8,7 +8,7 @@ extern "C" { #include "cs_operand.h" #include "platform.h" -#define HPPA_MAX_OPS 5 +#define NUM_HPPA_OPS 5 #define HPPA_STR_MODIFIER_LEN 8 #define HPPA_MAX_MODIFIERS_LEN 5 @@ -492,7 +492,7 @@ typedef struct cs_hppa { // Number of operands of this instruction, // or 0 when instruction has no operand. uint8_t op_count; - cs_hppa_op operands[HPPA_MAX_OPS]; ///< operands for hppa instruction. + cs_hppa_op operands[NUM_HPPA_OPS]; ///< operands for hppa instruction. } cs_hppa; /// HPPA modifiers type. Can be string (most of them) or int (uid, sop) diff --git a/include/capstone/loongarch.h b/include/capstone/loongarch.h index f75e5ca183..6eb977adfe 100644 --- a/include/capstone/loongarch.h +++ b/include/capstone/loongarch.h @@ -177,6 +177,8 @@ typedef struct { memory_access; ///< Memory access (none/read/write/read+write) } loongarch_suppl_info; +#define NUM_LOONGARCH_OPS 8 + /// Instruction structure typedef struct cs_loongarch { /// The instruction format. Can be use to determine the bit encoding of the instruction. @@ -185,7 +187,7 @@ typedef struct cs_loongarch { /// Number of operands of this instruction, /// or 0 when instruction has no operand. uint8_t op_count; - cs_loongarch_op operands[8]; ///< operands for this instruction. + cs_loongarch_op operands[NUM_LOONGARCH_OPS]; ///< operands for this instruction. } cs_loongarch; /// LoongArch registers diff --git a/include/capstone/mips.h b/include/capstone/mips.h index 5ab203c7de..c776d3ac1a 100644 --- a/include/capstone/mips.h +++ b/include/capstone/mips.h @@ -696,12 +696,14 @@ typedef struct cs_mips_op { uint8_t access; } cs_mips_op; +#define NUM_MIPS_OPS 10 + /// Instruction structure typedef struct cs_mips { /// Number of operands of this instruction, /// or 0 when instruction has no operand. uint8_t op_count; - cs_mips_op operands[10]; ///< operands for this instruction. + cs_mips_op operands[NUM_MIPS_OPS]; ///< operands for this instruction. } cs_mips; /// MIPS instruction diff --git a/include/capstone/riscv.h b/include/capstone/riscv.h index bd8d563b39..09b8fedd3b 100644 --- a/include/capstone/riscv.h +++ b/include/capstone/riscv.h @@ -49,6 +49,8 @@ typedef struct cs_riscv_op { uint8_t access; ///< How is this operand accessed? (READ, WRITE or READ|WRITE) } cs_riscv_op; +#define NUM_RISCV_OPS 8 + // Instruction structure typedef struct cs_riscv { // Does this instruction need effective address or not. @@ -56,7 +58,7 @@ typedef struct cs_riscv { // Number of operands of this instruction, // or 0 when instruction has no operand. uint8_t op_count; - cs_riscv_op operands[8]; // operands for this instruction. + cs_riscv_op operands[NUM_RISCV_OPS]; // operands for this instruction. } cs_riscv; //> RISCV registers diff --git a/include/capstone/sh.h b/include/capstone/sh.h index 688de07159..7f81313f11 100644 --- a/include/capstone/sh.h +++ b/include/capstone/sh.h @@ -182,15 +182,8 @@ typedef struct sh_op_mem { uint32_t disp; /// <= displacement } sh_op_mem; -// SH-DSP instcutions define -typedef enum sh_dsp_insn_type { - SH_INS_DSP_INVALID, - SH_INS_DSP_DOUBLE, - SH_INS_DSP_SINGLE, - SH_INS_DSP_PARALLEL, -} sh_dsp_insn_type; - typedef enum sh_dsp_insn { + SH_INS_DSP_INVALID = 0, SH_INS_DSP_NOP = 1, SH_INS_DSP_MOV, SH_INS_DSP_PSHL, diff --git a/include/capstone/tricore.h b/include/capstone/tricore.h index 4cf22f59d3..0e9c9daacf 100644 --- a/include/capstone/tricore.h +++ b/include/capstone/tricore.h @@ -47,13 +47,13 @@ typedef struct cs_tricore_op { uint8_t access; ///< How is this operand accessed? (READ, WRITE or READ|WRITE) } cs_tricore_op; -#define TRICORE_OP_COUNT 8 +#define NUM_TRICORE_OPS 8 /// Instruction structure typedef struct cs_tricore { uint8_t op_count; ///< number of operands of this instruction. cs_tricore_op - operands[TRICORE_OP_COUNT]; ///< operands for this instruction. + operands[NUM_TRICORE_OPS]; ///< operands for this instruction. /// TODO: Mark the modified flags register in td files and regenerate inc files bool update_flags; ///< whether the flags register is updated. } cs_tricore; diff --git a/suite/auto-sync/src/autosync/Tests/test_aarch64_header.h b/suite/auto-sync/src/autosync/Tests/test_aarch64_header.h index a98b290d7c..2f223ec5e1 100644 --- a/suite/auto-sync/src/autosync/Tests/test_aarch64_header.h +++ b/suite/auto-sync/src/autosync/Tests/test_aarch64_header.h @@ -37,7 +37,7 @@ typedef enum aarch64_op_type_upper { AARCH64_OP_SYSALIASIII, // Comment } aarch64_op_type_upper; -#define MAX_AARCH64_OPS 8 +#define NUM_AARCH64_OPS 8 /// Instruction structure typedef struct cs_aarch64 { @@ -50,7 +50,7 @@ typedef struct cs_aarch64 { /// or 0 when instruction has no operand. uint8_t op_count; - cs_aarch64_op operands[MAX_AARCH64_OPS]; ///< operands for this instruction. + cs_aarch64_op operands[NUM_AARCH64_OPS]; ///< operands for this instruction. } cs_aarch64; #endif diff --git a/suite/cstest/src/test_case.c b/suite/cstest/src/test_case.c index cd1ece6bbe..61d4a0823a 100644 --- a/suite/cstest/src/test_case.c +++ b/suite/cstest/src/test_case.c @@ -61,17 +61,18 @@ char *test_input_stringify(const TestInput *test_input, const char *postfix) char *byte_seq = byte_seq_to_str(test_input->bytes, test_input->bytes_count); if (!msg) { + cs_mem_free(byte_seq); return NULL; } char opt_seq[128] = { 0 }; - append_to_str(opt_seq, sizeof(opt_seq), "["); + str_append_no_realloc(opt_seq, sizeof(opt_seq), "["); for (size_t i = 0; i < test_input->options_count; ++i) { - append_to_str(opt_seq, sizeof(opt_seq), test_input->options[i]); + str_append_no_realloc(opt_seq, sizeof(opt_seq), test_input->options[i]); if (i < test_input->options_count - 1) { - append_to_str(opt_seq, sizeof(opt_seq), ", "); + str_append_no_realloc(opt_seq, sizeof(opt_seq), ", "); } } - append_to_str(opt_seq, sizeof(opt_seq), "]"); + str_append_no_realloc(opt_seq, sizeof(opt_seq), "]"); cs_snprintf(msg, msg_len, "%sTestInput { arch: %s, options: %s, addr: 0x%" PRIx64 ", bytes: %s }", @@ -210,12 +211,12 @@ void test_expected_compare(csh *handle, TestExpected *expected, cs_insn *insns, // Either all in op_str or split in mnemonic and op_str char asm_text[256] = { 0 }; if (insns[i].mnemonic[0] != '\0') { - append_to_str(asm_text, sizeof(asm_text), + str_append_no_realloc(asm_text, sizeof(asm_text), insns[i].mnemonic); - append_to_str(asm_text, sizeof(asm_text), " "); + str_append_no_realloc(asm_text, sizeof(asm_text), " "); } if (insns[i].op_str[0] != '\0') { - append_to_str(asm_text, sizeof(asm_text), + str_append_no_realloc(asm_text, sizeof(asm_text), insns[i].op_str); } if (!compare_asm_text(asm_text, expec_data->asm_text, diff --git a/suite/cstest/src/test_detail_x86.c b/suite/cstest/src/test_detail_x86.c index b7a3836511..1b66f1c05e 100644 --- a/suite/cstest/src/test_detail_x86.c +++ b/suite/cstest/src/test_detail_x86.c @@ -79,7 +79,7 @@ TestDetailX86 *test_detail_x86_clone(TestDetailX86 *detail) clone->eflags = detail->eflags ? cs_mem_calloc(sizeof(char *), detail->eflags_count) : NULL; - for (size_t i = 0; i < detail->eflags_count; ++i) { + for (size_t i = 0; clone->eflags && i < detail->eflags_count; ++i) { clone->eflags[i] = detail->eflags[i] ? strdup(detail->eflags[i]) : NULL; } @@ -89,7 +89,7 @@ TestDetailX86 *test_detail_x86_clone(TestDetailX86 *detail) detail->fpu_flags ? cs_mem_calloc(sizeof(char *), detail->fpu_flags_count) : NULL; - for (size_t i = 0; i < detail->fpu_flags_count; ++i) { + for (size_t i = 0; clone->fpu_flags && i < detail->fpu_flags_count; ++i) { clone->fpu_flags[i] = detail->fpu_flags[i] ? strdup(detail->fpu_flags[i]) : NULL; diff --git a/suite/cstest/src/test_run.c b/suite/cstest/src/test_run.c index e385908463..13c921ac9c 100644 --- a/suite/cstest/src/test_run.c +++ b/suite/cstest/src/test_run.c @@ -175,13 +175,7 @@ static bool open_cs_handle(UnitTestState *ustate) } else { ustate->arch_bits = 32; } - if (err != CS_ERR_OK) { - goto option_error; - } - if (err != CS_ERR_OK) { - goto option_error; - } for (size_t i = 0; i < options_set; ++i) { err = cs_option(ustate->handle, options[i].type, options[i].val); @@ -299,6 +293,8 @@ static void eval_test_cases(TestFile **test_files, TestRunStats *stats) // Use private function here, because the API takes only constant tables. int failed_tests = _cmocka_run_group_tests( "All test cases", utest_table, stats->tc_total, NULL, NULL); + assert(failed_tests >= 0 && "Faulty return value"); + for (size_t i = 0; i < stats->tc_total; ++i) { UnitTestState *ustate = utest_table[i].initial_state; if (!ustate) { diff --git a/suite/fuzz/platform.c b/suite/fuzz/platform.c index ac4d8db941..20f6454651 100644 --- a/suite/fuzz/platform.c +++ b/suite/fuzz/platform.c @@ -401,7 +401,11 @@ unsigned int platform_len(void) { // get platform entry encoded n (first byte for input data of OSS fuzz) unsigned int get_platform_entry(uint8_t n) { - return n % platform_len(); + unsigned len = platform_len(); + if (len == 0) { + return 0; + } + return n % len; } // get cstoolname from encoded n (first byte for input data of OSS fuzz) diff --git a/tests/issues/issues.yaml b/tests/issues/issues.yaml index cc0a17cc6d..8dc7232b3b 100644 --- a/tests/issues/issues.yaml +++ b/tests/issues/issues.yaml @@ -4957,3 +4957,77 @@ test_cases: expected: insns: - asm_text: "jalrc $t9" + + - + input: + name: "issue 2471 -- max operands overflow" + bytes: [ 0xff, 0x00, 0x08, 0xc0 ] + arch: "CS_ARCH_AARCH64" + options: [ CS_OPT_DETAIL, CS_OPT_DETAIL_REAL ] + address: 0x0 + expected: + insns: + - + asm_text: "zero {za}" + is_alias: 1 + details: + aarch64: + operands: + - + type: AARCH64_OP_SME + sme: + type: AARCH64_SME_OP_TILE + tile: za0.d + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_D + - + type: AARCH64_OP_SME + sme: + type: AARCH64_SME_OP_TILE + tile: za1.d + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_D + - + type: AARCH64_OP_SME + sme: + type: AARCH64_SME_OP_TILE + tile: za2.d + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_D + - + type: AARCH64_OP_SME + sme: + type: AARCH64_SME_OP_TILE + tile: za3.d + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_D + - + type: AARCH64_OP_SME + sme: + type: AARCH64_SME_OP_TILE + tile: za4.d + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_D + - + type: AARCH64_OP_SME + sme: + type: AARCH64_SME_OP_TILE + tile: za5.d + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_D + - + type: AARCH64_OP_SME + sme: + type: AARCH64_SME_OP_TILE + tile: za6.d + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_D + - + type: AARCH64_OP_SME + sme: + type: AARCH64_SME_OP_TILE + tile: za7.d + access: CS_AC_READ + vas: AARCH64LAYOUT_VL_D + regs_read: [ za0.d, za1.d, za2.d, za3.d, za4.d, za5.d, za6.d, za7.d ] + groups: [ HasSME ] diff --git a/tests/unit/CMakeLists.txt b/tests/unit/CMakeLists.txt index 2718f594f3..4ac56ef879 100644 --- a/tests/unit/CMakeLists.txt +++ b/tests/unit/CMakeLists.txt @@ -1,14 +1,12 @@ cmake_minimum_required(VERSION 3.15) -# Old integration tests. -if (CAPSTONE_BUILD_LEGACY_TESTS) - enable_testing() - set(UNIT_TEST_SOURCES sstream.c) +enable_testing() +set(UNIT_TEST_SOURCES sstream.c utils.c) +include_directories(include) - foreach(TSRC ${UNIT_TEST_SOURCES}) - string(REGEX REPLACE ".c$" "" TBIN ${TSRC}) - add_executable(${TBIN} "${TESTS_UNIT_DIR}/${TSRC}") - target_link_libraries(${TBIN} PRIVATE capstone) - add_test(NAME "unit_${TBIN}" COMMAND ${TBIN}) - endforeach() -endif() +foreach(TSRC ${UNIT_TEST_SOURCES}) + string(REGEX REPLACE ".c$" "" TBIN ${TSRC}) + add_executable(${TBIN} "${TESTS_UNIT_DIR}/${TSRC}") + target_link_libraries(${TBIN} PRIVATE capstone) + add_test(NAME "unit_${TBIN}" COMMAND ${TBIN}) +endforeach() diff --git a/tests/unit/include/unit_test.h b/tests/unit/include/unit_test.h new file mode 100644 index 0000000000..bf5b5cae01 --- /dev/null +++ b/tests/unit/include/unit_test.h @@ -0,0 +1,44 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#define CHECK_OS_EQUAL_RET_FALSE(OS, str) \ + do { \ + if (strcmp(OS.buffer, str) != 0) { \ + printf("OS.buffer != str\n"); \ + printf("OS.buffer: %s\n", OS.buffer); \ + printf("str : %s\n", str); \ + return false; \ + } \ + } while (0); + +#define CHECK_STR_EQUAL_RET_FALSE(a, b) \ + do { \ + if (strcmp(a, b) != 0) { \ + printf("%s != %s\n", a, b); \ + return false; \ + } \ + } while (0); + +#define CHECK_NULL_RET_FALSE(ptr) \ + do { \ + if (ptr != NULL) { \ + printf(#ptr " is not NULL\n"); \ + return false; \ + } \ + } while (0); + +#define CHECK_PTR_EQUAL_RET_FALSE(a, b) \ + do { \ + if (a != b) { \ + printf("%p != %p\n", a, b); \ + return false; \ + } \ + } while (0); + +#define CHECK_INT_EQUAL_RET_FALSE(a, b) \ + do { \ + if (a != b) { \ + printf("%" PRId32 " != %" PRId32 "\n", a, b); \ + return false; \ + } \ + } while (0); diff --git a/tests/unit/sstream.c b/tests/unit/sstream.c index c4f158b6c2..8f60485759 100644 --- a/tests/unit/sstream.c +++ b/tests/unit/sstream.c @@ -1,21 +1,12 @@ // Copyright © 2024 Rot127 // SPDX-License-Identifier: BSD-3 +#include "unit_test.h" #include "../SStream.h" #include "../utils.h" #include #include -#define CHECK_EQUAL_RET_FALSE(OS, str) \ - do { \ - if (strcmp(OS.buffer, str) != 0) { \ - printf("OS.buffer != str\n"); \ - printf("OS.buffer: %s\n", OS.buffer); \ - printf("str : %s\n", str); \ - return false; \ - } \ - } while (0); - static void overflow_SStream_concat0(SStream *OS, bool *returned_in_time) { char buf[SSTREAM_BUF_LEN + 1] = { 0 }; @@ -74,22 +65,22 @@ static bool test_markup_os() SStream OS = { 0 }; SStream_Init(&OS); SStream_concat0(&OS, "0"); - CHECK_EQUAL_RET_FALSE(OS, "0"); + CHECK_OS_EQUAL_RET_FALSE(OS, "0"); OS.markup_stream = true; printUInt64(&OS, 0); - CHECK_EQUAL_RET_FALSE(OS, "00"); + CHECK_OS_EQUAL_RET_FALSE(OS, "00"); markup_OS(&OS, Markup_Immediate); printUInt64(&OS, 0); - CHECK_EQUAL_RET_FALSE(OS, "00"); + CHECK_OS_EQUAL_RET_FALSE(OS, "00"); markup_OS(&OS, Markup_Memory); printUInt32(&OS, 0); - CHECK_EQUAL_RET_FALSE(OS, "00"); + CHECK_OS_EQUAL_RET_FALSE(OS, "00"); markup_OS(&OS, Markup_Target); printUInt32(&OS, 0); - CHECK_EQUAL_RET_FALSE(OS, "00"); + CHECK_OS_EQUAL_RET_FALSE(OS, "00"); markup_OS(&OS, Markup_Register); SStream_concat0(&OS, "r19"); - CHECK_EQUAL_RET_FALSE(OS, "00"); + CHECK_OS_EQUAL_RET_FALSE(OS, "00"); return true; } @@ -100,27 +91,27 @@ bool test_printint8() SStream OS = { 0 }; SStream_Init(&OS); printInt8(&OS, HEX_THRESHOLD + 1); - CHECK_EQUAL_RET_FALSE(OS, "0xa"); + CHECK_OS_EQUAL_RET_FALSE(OS, "0xa"); SStream_Flush(&OS, NULL); printInt8(&OS, HEX_THRESHOLD); - CHECK_EQUAL_RET_FALSE(OS, "9"); + CHECK_OS_EQUAL_RET_FALSE(OS, "9"); SStream_Flush(&OS, NULL); printInt8(&OS, -(HEX_THRESHOLD + 1)); - CHECK_EQUAL_RET_FALSE(OS, "-0xa"); + CHECK_OS_EQUAL_RET_FALSE(OS, "-0xa"); SStream_Flush(&OS, NULL); printInt8(&OS, -HEX_THRESHOLD); - CHECK_EQUAL_RET_FALSE(OS, "-9"); + CHECK_OS_EQUAL_RET_FALSE(OS, "-9"); SStream_Flush(&OS, NULL); printInt8(&OS, INT8_MAX); - CHECK_EQUAL_RET_FALSE(OS, "0x7f"); + CHECK_OS_EQUAL_RET_FALSE(OS, "0x7f"); SStream_Flush(&OS, NULL); printInt8(&OS, INT8_MIN); - CHECK_EQUAL_RET_FALSE(OS, "-0x80"); + CHECK_OS_EQUAL_RET_FALSE(OS, "-0x80"); SStream_Flush(&OS, NULL); return true; } @@ -132,27 +123,27 @@ bool test_printint16() SStream OS = { 0 }; SStream_Init(&OS); printInt16(&OS, HEX_THRESHOLD + 1); - CHECK_EQUAL_RET_FALSE(OS, "0xa"); + CHECK_OS_EQUAL_RET_FALSE(OS, "0xa"); SStream_Flush(&OS, NULL); printInt16(&OS, HEX_THRESHOLD); - CHECK_EQUAL_RET_FALSE(OS, "9"); + CHECK_OS_EQUAL_RET_FALSE(OS, "9"); SStream_Flush(&OS, NULL); printInt16(&OS, -(HEX_THRESHOLD + 1)); - CHECK_EQUAL_RET_FALSE(OS, "-0xa"); + CHECK_OS_EQUAL_RET_FALSE(OS, "-0xa"); SStream_Flush(&OS, NULL); printInt16(&OS, -HEX_THRESHOLD); - CHECK_EQUAL_RET_FALSE(OS, "-9"); + CHECK_OS_EQUAL_RET_FALSE(OS, "-9"); SStream_Flush(&OS, NULL); printInt16(&OS, INT16_MAX); - CHECK_EQUAL_RET_FALSE(OS, "0x7fff"); + CHECK_OS_EQUAL_RET_FALSE(OS, "0x7fff"); SStream_Flush(&OS, NULL); printInt16(&OS, INT16_MIN); - CHECK_EQUAL_RET_FALSE(OS, "-0x8000"); + CHECK_OS_EQUAL_RET_FALSE(OS, "-0x8000"); SStream_Flush(&OS, NULL); return true; } @@ -164,27 +155,27 @@ bool test_printint32() SStream OS = { 0 }; SStream_Init(&OS); printInt32(&OS, HEX_THRESHOLD + 1); - CHECK_EQUAL_RET_FALSE(OS, "0xa"); + CHECK_OS_EQUAL_RET_FALSE(OS, "0xa"); SStream_Flush(&OS, NULL); printInt32(&OS, HEX_THRESHOLD); - CHECK_EQUAL_RET_FALSE(OS, "9"); + CHECK_OS_EQUAL_RET_FALSE(OS, "9"); SStream_Flush(&OS, NULL); printInt32(&OS, -(HEX_THRESHOLD + 1)); - CHECK_EQUAL_RET_FALSE(OS, "-0xa"); + CHECK_OS_EQUAL_RET_FALSE(OS, "-0xa"); SStream_Flush(&OS, NULL); printInt32(&OS, -HEX_THRESHOLD); - CHECK_EQUAL_RET_FALSE(OS, "-9"); + CHECK_OS_EQUAL_RET_FALSE(OS, "-9"); SStream_Flush(&OS, NULL); printInt32(&OS, INT32_MAX); - CHECK_EQUAL_RET_FALSE(OS, "0x7fffffff"); + CHECK_OS_EQUAL_RET_FALSE(OS, "0x7fffffff"); SStream_Flush(&OS, NULL); printInt32(&OS, INT32_MIN); - CHECK_EQUAL_RET_FALSE(OS, "-0x80000000"); + CHECK_OS_EQUAL_RET_FALSE(OS, "-0x80000000"); SStream_Flush(&OS, NULL); return true; } @@ -196,27 +187,27 @@ bool test_printint64() SStream OS = { 0 }; SStream_Init(&OS); printInt64(&OS, HEX_THRESHOLD + 1); - CHECK_EQUAL_RET_FALSE(OS, "0xa"); + CHECK_OS_EQUAL_RET_FALSE(OS, "0xa"); SStream_Flush(&OS, NULL); printInt64(&OS, HEX_THRESHOLD); - CHECK_EQUAL_RET_FALSE(OS, "9"); + CHECK_OS_EQUAL_RET_FALSE(OS, "9"); SStream_Flush(&OS, NULL); printInt64(&OS, -(HEX_THRESHOLD + 1)); - CHECK_EQUAL_RET_FALSE(OS, "-0xa"); + CHECK_OS_EQUAL_RET_FALSE(OS, "-0xa"); SStream_Flush(&OS, NULL); printInt64(&OS, -HEX_THRESHOLD); - CHECK_EQUAL_RET_FALSE(OS, "-9"); + CHECK_OS_EQUAL_RET_FALSE(OS, "-9"); SStream_Flush(&OS, NULL); printInt64(&OS, INT64_MAX); - CHECK_EQUAL_RET_FALSE(OS, "0x7fffffffffffffff"); + CHECK_OS_EQUAL_RET_FALSE(OS, "0x7fffffffffffffff"); SStream_Flush(&OS, NULL); printInt64(&OS, INT64_MIN); - CHECK_EQUAL_RET_FALSE(OS, "-0x8000000000000000"); + CHECK_OS_EQUAL_RET_FALSE(OS, "-0x8000000000000000"); SStream_Flush(&OS, NULL); return true; } @@ -228,27 +219,27 @@ bool test_printint32_bang() SStream OS = { 0 }; SStream_Init(&OS); printInt32Bang(&OS, HEX_THRESHOLD + 1); - CHECK_EQUAL_RET_FALSE(OS, "#0xa"); + CHECK_OS_EQUAL_RET_FALSE(OS, "#0xa"); SStream_Flush(&OS, NULL); printInt32Bang(&OS, HEX_THRESHOLD); - CHECK_EQUAL_RET_FALSE(OS, "#9"); + CHECK_OS_EQUAL_RET_FALSE(OS, "#9"); SStream_Flush(&OS, NULL); printInt32Bang(&OS, -(HEX_THRESHOLD + 1)); - CHECK_EQUAL_RET_FALSE(OS, "#-0xa"); + CHECK_OS_EQUAL_RET_FALSE(OS, "#-0xa"); SStream_Flush(&OS, NULL); printInt32Bang(&OS, -HEX_THRESHOLD); - CHECK_EQUAL_RET_FALSE(OS, "#-9"); + CHECK_OS_EQUAL_RET_FALSE(OS, "#-9"); SStream_Flush(&OS, NULL); printInt32Bang(&OS, INT32_MAX); - CHECK_EQUAL_RET_FALSE(OS, "#0x7fffffff"); + CHECK_OS_EQUAL_RET_FALSE(OS, "#0x7fffffff"); SStream_Flush(&OS, NULL); printInt32Bang(&OS, INT32_MIN); - CHECK_EQUAL_RET_FALSE(OS, "#-0x80000000"); + CHECK_OS_EQUAL_RET_FALSE(OS, "#-0x80000000"); SStream_Flush(&OS, NULL); return true; } @@ -260,27 +251,27 @@ bool test_printint64_bang() SStream OS = { 0 }; SStream_Init(&OS); printInt64Bang(&OS, HEX_THRESHOLD + 1); - CHECK_EQUAL_RET_FALSE(OS, "#0xa"); + CHECK_OS_EQUAL_RET_FALSE(OS, "#0xa"); SStream_Flush(&OS, NULL); printInt64Bang(&OS, HEX_THRESHOLD); - CHECK_EQUAL_RET_FALSE(OS, "#9"); + CHECK_OS_EQUAL_RET_FALSE(OS, "#9"); SStream_Flush(&OS, NULL); printInt64Bang(&OS, -(HEX_THRESHOLD + 1)); - CHECK_EQUAL_RET_FALSE(OS, "#-0xa"); + CHECK_OS_EQUAL_RET_FALSE(OS, "#-0xa"); SStream_Flush(&OS, NULL); printInt64Bang(&OS, -HEX_THRESHOLD); - CHECK_EQUAL_RET_FALSE(OS, "#-9"); + CHECK_OS_EQUAL_RET_FALSE(OS, "#-9"); SStream_Flush(&OS, NULL); printInt64Bang(&OS, INT64_MAX); - CHECK_EQUAL_RET_FALSE(OS, "#0x7fffffffffffffff"); + CHECK_OS_EQUAL_RET_FALSE(OS, "#0x7fffffffffffffff"); SStream_Flush(&OS, NULL); printInt64Bang(&OS, INT64_MIN); - CHECK_EQUAL_RET_FALSE(OS, "#-0x8000000000000000"); + CHECK_OS_EQUAL_RET_FALSE(OS, "#-0x8000000000000000"); SStream_Flush(&OS, NULL); return true; } @@ -292,15 +283,15 @@ bool test_printuint32_bang() SStream OS = { 0 }; SStream_Init(&OS); printUInt32Bang(&OS, HEX_THRESHOLD + 1); - CHECK_EQUAL_RET_FALSE(OS, "#0xa"); + CHECK_OS_EQUAL_RET_FALSE(OS, "#0xa"); SStream_Flush(&OS, NULL); printUInt32Bang(&OS, HEX_THRESHOLD); - CHECK_EQUAL_RET_FALSE(OS, "#9"); + CHECK_OS_EQUAL_RET_FALSE(OS, "#9"); SStream_Flush(&OS, NULL); printUInt32Bang(&OS, UINT32_MAX); - CHECK_EQUAL_RET_FALSE(OS, "#0xffffffff"); + CHECK_OS_EQUAL_RET_FALSE(OS, "#0xffffffff"); SStream_Flush(&OS, NULL); return true; } @@ -312,16 +303,208 @@ bool test_printuint64_bang() SStream OS = { 0 }; SStream_Init(&OS); printUInt64Bang(&OS, HEX_THRESHOLD + 1); - CHECK_EQUAL_RET_FALSE(OS, "#0xa"); + CHECK_OS_EQUAL_RET_FALSE(OS, "#0xa"); SStream_Flush(&OS, NULL); printUInt64Bang(&OS, HEX_THRESHOLD); - CHECK_EQUAL_RET_FALSE(OS, "#9"); + CHECK_OS_EQUAL_RET_FALSE(OS, "#9"); SStream_Flush(&OS, NULL); printUInt64Bang(&OS, UINT64_MAX); - CHECK_EQUAL_RET_FALSE(OS, "#0xffffffffffffffff"); + CHECK_OS_EQUAL_RET_FALSE(OS, "#0xffffffffffffffff"); + SStream_Flush(&OS, NULL); + return true; +} + +bool test_trimls() { + printf("Test test_replc\n"); + + SStream OS = { 0 }; + SStream_Init(&OS); + SStream_concat0(&OS, "AAA"); + SStream_trimls(&OS); + CHECK_OS_EQUAL_RET_FALSE(OS, "AAA"); + SStream_Flush(&OS, NULL); + + SStream_concat0(&OS, "\t AAA"); + SStream_trimls(&OS); + CHECK_OS_EQUAL_RET_FALSE(OS, "AAA"); + + // Don't remove middle tabs and spaces + SStream_concat0(&OS, "\t AAA"); + SStream_trimls(&OS); + CHECK_OS_EQUAL_RET_FALSE(OS, "AAA\t AAA"); + SStream_Flush(&OS, NULL); + + // Test do nothing + SStream_trimls(&OS); + CHECK_OS_EQUAL_RET_FALSE(OS, ""); + + // Everywhere tabs + char cmp_buf[SSTREAM_BUF_LEN] = { 0 }; + memset(cmp_buf, '\t', sizeof(cmp_buf) - 1); + SStream_trimls(&OS); + CHECK_OS_EQUAL_RET_FALSE(OS, ""); + CHECK_INT_EQUAL_RET_FALSE(OS.index, 0); + return true; +} + +bool test_copy_mnem_opstr() { + printf("Test test_copy_mnem_opstr\n"); + + SStream OS = { 0 }; + SStream_Init(&OS); + SStream_concat0(&OS, "AAA\tBBBB"); + + char mnem_1[1] = { 0 }; + char opstr_1[1] = { 0 }; + SStream_extract_mnem_opstr(&OS, mnem_1, sizeof(mnem_1), opstr_1, sizeof(opstr_1)); + CHECK_STR_EQUAL_RET_FALSE(mnem_1, ""); + CHECK_STR_EQUAL_RET_FALSE(opstr_1, ""); + + char mnem_3[3] = { 0 }; + char opstr_3[3] = { 0 }; + SStream_extract_mnem_opstr(&OS, mnem_3, sizeof(mnem_3), opstr_3, sizeof(opstr_3)); + CHECK_STR_EQUAL_RET_FALSE(mnem_3, "AA"); + CHECK_STR_EQUAL_RET_FALSE(opstr_3, "BB"); + + char mnem_4[4] = { 0 }; + char opstr_4[4] = { 0 }; + SStream_extract_mnem_opstr(&OS, mnem_4, sizeof(mnem_4), opstr_4, sizeof(opstr_4)); + CHECK_STR_EQUAL_RET_FALSE(mnem_4, "AAA"); + CHECK_STR_EQUAL_RET_FALSE(opstr_4, "BBB"); + + char mnem_5[5] = { 0 }; + char opstr_5[5] = { 0 }; + SStream_extract_mnem_opstr(&OS, mnem_5, sizeof(mnem_5), opstr_5, sizeof(opstr_5)); + CHECK_STR_EQUAL_RET_FALSE(mnem_5, "AAA"); + CHECK_STR_EQUAL_RET_FALSE(opstr_5, "BBBB"); + + // No mnemonic + char mnem_9[9] = { 0 }; + char opstr_9[9] = { 0 }; + SStream_Flush(&OS, NULL); + SStream_concat0(&OS, " AAA\tBBBB"); + SStream_extract_mnem_opstr(&OS, mnem_9, sizeof(mnem_9), opstr_9, sizeof(opstr_9)); + CHECK_STR_EQUAL_RET_FALSE(mnem_9, ""); + CHECK_STR_EQUAL_RET_FALSE(opstr_9, "AAA\tBBBB"); + + // No opstr + char mnem_6[6] = { 0 }; + char opstr_6[6] = { 0 }; + SStream_Flush(&OS, NULL); + SStream_concat0(&OS, "AAA \t"); + SStream_extract_mnem_opstr(&OS, mnem_6, sizeof(mnem_6), opstr_6, sizeof(opstr_6)); + CHECK_STR_EQUAL_RET_FALSE(mnem_6, "AAA"); + CHECK_STR_EQUAL_RET_FALSE(opstr_6, ""); + + return true; +} + +bool test_replc() +{ + printf("Test test_replc\n"); + + SStream OS = { 0 }; + SStream_Init(&OS); + char cmp_buf[SSTREAM_BUF_LEN] = { 0 }; + memset(cmp_buf, 'A', sizeof(cmp_buf) - 1); + cmp_buf[100] = 'C'; + SStream_concat0(&OS, cmp_buf); + + cmp_buf[0] = 'B'; + const char *next = SStream_replc(&OS, 'A', 'B'); + CHECK_PTR_EQUAL_RET_FALSE(SStream_rbuf(&OS) + 1, next); + CHECK_OS_EQUAL_RET_FALSE(OS, cmp_buf); + + cmp_buf[1] = 'B'; + next = SStream_replc(&OS, 'A', 'B'); + CHECK_PTR_EQUAL_RET_FALSE(SStream_rbuf(&OS) + 2, next); + CHECK_OS_EQUAL_RET_FALSE(OS, cmp_buf); + + cmp_buf[100] = 'A'; // Replace the C from before + next = SStream_replc(&OS, 'C', 'A'); + CHECK_PTR_EQUAL_RET_FALSE(SStream_rbuf(&OS) + 101, next); + CHECK_OS_EQUAL_RET_FALSE(OS, cmp_buf); + + // X doesn't exist + next = SStream_replc(&OS, 'X', 'A'); + CHECK_NULL_RET_FALSE(next); + + // Replacing \0 byte is forbidden. + next = SStream_replc(&OS, '\0', 'A'); + CHECK_NULL_RET_FALSE(next); + + // But replacing any \0 byte is allowed. + SStream_Flush(&OS, NULL); + next = SStream_replc(&OS, '\0', 'A'); + CHECK_PTR_EQUAL_RET_FALSE(SStream_rbuf(&OS) + 1, next); + CHECK_OS_EQUAL_RET_FALSE(OS, "A"); + + return true; +} + + +bool test_replc_str() +{ + printf("Test test_replc_str\n"); + + SStream OS = { 0 }; + SStream_Init(&OS); + + SStream_replc_str(&OS, 'A', "REPLACED"); + CHECK_OS_EQUAL_RET_FALSE(OS, ""); + CHECK_INT_EQUAL_RET_FALSE(OS.index, 0); + + SStream_replc_str(&OS, '\0', "REPLACED"); + CHECK_OS_EQUAL_RET_FALSE(OS, "REPLACED"); + CHECK_INT_EQUAL_RET_FALSE(OS.index, 8); + + SStream_Flush(&OS, NULL); + SStream_concat0(&OS, "\tA--X"); + SStream_replc_str(&OS, 'A', "REPLACED"); + CHECK_OS_EQUAL_RET_FALSE(OS, "\tREPLACED--X"); + CHECK_INT_EQUAL_RET_FALSE(OS.index, 12); + SStream_replc_str(&OS, 'X', "REPLACED"); + CHECK_OS_EQUAL_RET_FALSE(OS, "\tREPLACED--REPLACED"); + CHECK_INT_EQUAL_RET_FALSE(OS.index, 19); + + /// Too big strings are ignored. + char repl[SSTREAM_BUF_LEN] = { 0 }; + memset(repl, 'A', sizeof(repl) - 1); SStream_Flush(&OS, NULL); + SStream_concat0(&OS, "\tA--"); + SStream_replc_str(&OS, 'A', repl); + CHECK_OS_EQUAL_RET_FALSE(OS, "\tA--"); + CHECK_INT_EQUAL_RET_FALSE(OS.index, 4); + + /// Last null byte is not replaced. + memset(repl, 'A', sizeof(repl) - 1); + SStream_Flush(&OS, NULL); + SStream_concat0(&OS, repl); + SStream_replc_str(&OS, '\0', repl); + CHECK_OS_EQUAL_RET_FALSE(OS, repl); + CHECK_INT_EQUAL_RET_FALSE(OS.index, 511); + + /// Last char is replaced. + memset(repl, 'A', sizeof(repl) - 1); + repl[sizeof(repl) - 2] = 'X'; + SStream_Flush(&OS, NULL); + SStream_concat0(&OS, repl); + SStream_replc_str(&OS, 'X', "Y"); + repl[sizeof(repl) - 2] = 'Y'; + CHECK_OS_EQUAL_RET_FALSE(OS, repl); + CHECK_INT_EQUAL_RET_FALSE(OS.index, 511); + + // Possible overflow + char too_long[SSTREAM_BUF_LEN + 10] = { 0 }; + memset(too_long, 'A', sizeof(too_long) - 1); + SStream_Flush(&OS, NULL); + SStream_concat0(&OS, "\tA--"); + SStream_replc_str(&OS, 'A', too_long); + CHECK_OS_EQUAL_RET_FALSE(OS, "\tA--"); + CHECK_INT_EQUAL_RET_FALSE(OS.index, 4); + return true; } @@ -338,6 +521,10 @@ int main() result &= test_printint64_bang(); result &= test_printuint32_bang(); result &= test_printuint64_bang(); + result &= test_replc(); + result &= test_replc_str(); + result &= test_copy_mnem_opstr(); + result &= test_trimls(); if (result) { printf("All tests passed.\n"); } else { diff --git a/tests/unit/utils.c b/tests/unit/utils.c new file mode 100644 index 0000000000..d5dd88b312 --- /dev/null +++ b/tests/unit/utils.c @@ -0,0 +1,76 @@ +// Copyright © 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "unit_test.h" +#include "../utils.h" +#include +#include + +static bool test_str_append_no_realloc() +{ + printf("Test test_str_append_no_realloc\n"); + + char str_a[] = "AAAA\0\0\0\0\0"; + char str_b[] = "BBBB"; + char str_c[] = "\0\0\0\0\0"; + + CHECK_NULL_RET_FALSE(str_append(NULL, NULL)); + CHECK_NULL_RET_FALSE(str_append(str_a, NULL)); + CHECK_NULL_RET_FALSE(str_append(NULL, str_b)); + + str_append_no_realloc(str_a, sizeof(str_a), str_c); + CHECK_STR_EQUAL_RET_FALSE(str_a, "AAAA"); + + str_append_no_realloc(str_a, sizeof(str_a), str_b); + CHECK_STR_EQUAL_RET_FALSE(str_a, "AAAABBBB"); + + str_append_no_realloc(str_c, sizeof(str_c), str_b); + CHECK_STR_EQUAL_RET_FALSE(str_c, "BBBB"); + + str_append_no_realloc(str_b, sizeof(str_b), str_c); + CHECK_STR_EQUAL_RET_FALSE(str_b, "BBBB"); + + return true; +} + +static bool test_str_append() +{ + printf("Test test_str_append\n"); + char *str_a = NULL; + char *str_b = NULL; + CHECK_NULL_RET_FALSE(str_append(str_a, str_b)); + + str_a = calloc(5, sizeof(char)); + memcpy(str_a, "AAAA", 5); + CHECK_NULL_RET_FALSE(str_append(str_a, str_b)); + + str_b = calloc(5, sizeof(char)); + str_a = str_append(str_a, str_b); + CHECK_STR_EQUAL_RET_FALSE(str_a, "AAAA"); + + memcpy(str_b, "BBBB", 5); + str_a = str_append(str_a, str_b); + CHECK_STR_EQUAL_RET_FALSE(str_a, "AAAABBBB"); + + memset(str_a, 0, strlen(str_a) + 1); + str_a = str_append(str_a, str_b); + CHECK_STR_EQUAL_RET_FALSE(str_a, "BBBB"); + free(str_a); + free(str_b); + + return true; +} + +int main() +{ + bool result = true; + result &= test_str_append(); + result &= test_str_append_no_realloc(); + + if (result) { + printf("All tests passed.\n"); + } else { + printf("Some tests failed.\n"); + } + return result ? 0 : -1; +} diff --git a/utils.c b/utils.c index 75c22c2bed..fb744bcbcc 100644 --- a/utils.c +++ b/utils.c @@ -181,36 +181,37 @@ void append_to_str_lower(char *str, size_t str_size, const char *src) { str[i] = '\0'; } -/// @brief Appends the string @p src to the string @p str. @p src is put to lower case. -/// @param str The string to append to. -/// @param str_buf_size Size of buffer @p str. +/// @brief Appends the string @p src to the string @p dest. +/// @p dest is can be a stack allocated buffer. +/// +/// @param dest The string to append to. +/// @param dest_buf_size Size of buffer @p str. /// @param src The string to append. /// Does nothing if any of the given strings is NULL. -void append_to_str(char *str, size_t str_buf_size, const char *src) { - if (!str || !src) { +void str_append_no_realloc(char *dest, size_t dest_buf_size, const char *src) { + if (!dest || !src) { return; } - if (strlen(str) + strlen(src) + 1 > str_buf_size) { - assert("str_size does not match actual string length." && 0); + if (strlen(dest) + strlen(src) + 1 > dest_buf_size) { + printf("str_size does not match actual string length.\n"); return; } - strncat(str, src, str_buf_size); + strncat(dest, src, dest_buf_size - strlen(dest)); } /// Allocates memory of strlen(str_a) + strlen(str_b) + 1 chars /// and copies all strings into it as str_a + str_b /// str_a is passed to realloc and should not be used afterwards. -/// Returns the result. +/// Returns the concatenated string. /// Returns NULL in case of failure. char *str_append(char *str_a, const char *str_b) { if (!str_a || !str_b) { return NULL; } - assert(str_a && str_b); size_t asize = strlen(str_a) + strlen(str_b) + 1; str_a = realloc(str_a, asize); - strncat(str_a, str_b, asize); + strncat(str_a, str_b, asize - strlen(str_a)); return str_a; } diff --git a/utils.h b/utils.h index c9c82bc275..baa87e2572 100644 --- a/utils.h +++ b/utils.h @@ -44,7 +44,7 @@ uint64_t readBytes48(MCInst *MI, const uint8_t *Bytes); uint64_t readBytes64(MCInst *MI, const uint8_t *Bytes); void append_to_str_lower(char *str, size_t str_size, const char *src); -void append_to_str(char *str, size_t str_buf_size, const char *src); +void str_append_no_realloc(char *str, size_t str_buf_size, const char *src); char *str_append(char *str_a, const char *str_b); static inline bool strings_match(const char *str0, const char *str1) { return strcmp(str0, str1) == 0; }